From 421efbcbd12439af697346825d09c2f100817c0a Mon Sep 17 00:00:00 2001
From: Xavier Brown <xavierqb@proton.me>
Date: Thu, 19 Sep 2024 17:19:15 -0500
Subject: [PATCH] v24.8.1

---
 .github/workflows/merge-announce.yml          |    20 +
 .github/workflows/pr-announce.yml             |    25 +
 config/boards/armsom-aim7-io.csc              |    21 +
 config/boards/ayn-odin2.eos                   |   155 +
 config/boards/bananapi.conf                   |    15 +
 config/boards/gateway-gz80x.conf              |    19 +
 config/boards/nanopct6.conf                   |   107 +
 config/boards/nanopim4v2.conf                 |    35 +
 config/boards/odroidc4.conf                   |    11 +
 config/boards/odroidhc4.conf                  |   112 +
 config/boards/pinebook-pro.csc                |    42 +
 config/boards/retro-lite-cm5.csc              |    26 +
 config/boards/rk3328-heltec.csc               |    13 +
 config/boards/rock-3a.conf                    |    15 +
 config/boards/rockpro64.csc                   |    78 +
 config/boards/x96q.tvb                        |    11 +
 config/boards/youyeetoo-r1-v3.wip             |    53 +
 config/bootenv/rk356x.txt                     |     4 +
 .../kernel/linux-rockchip-rk3588-6.11.config  | 11042 ++++
 config/sources/families/meson-axg.conf        |    23 +
 config/sources/git_sources.json               |   202 +
 ...-cpuinfo-consistent-on-arm64-and-arm.patch |    29 +
 ...atform-selection-brcm-soc-support.disabled |    22 +
 .../bcm2711-6.10/1003-remote-wakeup.patch     |   193 +
 .../bcm2711-6.10/2001-rename-msd.patch        |    50 +
 patch/kernel/archive/imx6-6.10/.placeholder   |     0
 ...meson8b-usb2-Add-support-for-reading.patch |    46 +
 ...n8b-usb2-Add-support-for-reading-the.patch |   102 +
 ...onn-gpio-Fall-back-to-polling-the-GP.patch |   146 +
 ...register-child-USB-connector-devices.patch |    49 +
 ...d-GPIO-controller-capabilities-to-th.patch |    30 +
 ...odroidc1-Enable-the-Micro-USB-OTG-co.patch |    74 +
 ...Add-bindings-for-the-Amlogic-Meson-C.patch |   104 +
 ...a-new-driver-for-the-CVBS-DAC-CVBS-P.patch |   445 +
 ...lay-meson-vpu-Add-the-CVBS-DAC-prope.patch |    48 +
 ...pport-for-using-a-PHY-for-the-CVBS-D.patch |   317 +
 ...k-meson8b-Add-the-RMII-reference-clo.patch |    30 +
 ...k-meson8b-Add-the-Meson8-Ethernet-RM.patch |    30 +
 ...b-Add-the-Ethernet-RMII-clock-tree-o.patch |   162 +
 ...dwmac-meson-Add-the-Ethernet-clock-i.patch |    52 +
 ...mac-meson-Rename-the-SPEED_100-macro.patch |    44 +
 ...wmac-meson-Manage-the-ethernet-clock.patch |   117 +
 ...-meson-Initialize-all-known-PREG_ETH.patch |    76 +
 ...son8-Add-the-clock-input-to-the-Ethe.patch |    34 +
 ...k-meson8b-add-the-rtc_32k-oscillator.patch |    29 +
 ...son8b-Add-the-mpeg_rtc_osc_sel-clock.patch |   108 +
 ...d-address-cells-size-cells-and-range.patch |    84 +
 ...ware-Document-the-Amlogic-Meson6-8-8.patch |    75 +
 ...cpus-Document-Meson8-TrustZone-firmw.patch |    31 +
 ...d-support-for-the-TrustZone-firmware.patch |   436 +
 ...p-Add-support-for-SoCs-running-on-Tr.patch |    75 +
 ...n-mx-socinfo-Add-support-for-the-Tru.patch |    68 +
 ...fuse-Add-support-for-the-TrustZone-f.patch |    73 +
 ...on8-Add-the-PWM_C-DV9-and-PWM_D-pins.patch |    45 +
 ...lay-meson-vpu-add-support-for-Meson8.patch |    32 +
 ...son8-Meson8b-Meson8m2-specific-vpu_c.patch |    39 +
 ...-bits-per-pixel-for-the-framebuffer-.patch |    66 +
 ...separate-list-of-supported-formats-f.patch |    83 +
 ...IU_OSD1_CTRL_STAT2-alpha-replace-val.patch |    52 +
 ...-the-RGB-to-YUV-converter-on-Meson8-.patch |    34 +
 ...-meson_vpu_init-to-work-with-Meson8-.patch |    84 +
 ...be-the-HDMI-PHY-frequency-limits-of-.patch |    56 +
 ...e-the-HDMI-encoder-for-Meson8-8b-8m2.patch |   144 +
 ...set-ycbcr_420_allowed-on-64-bit-SoCs.patch |    34 +
 ...-Make-the-HHI-registers-optional-WIP.patch |   100 +
 ...pport-for-the-Meson8-8b-8m2-TranSwit.patch |  2131 +
 ...on-Meson8-Meson8b-Meson8m2-VCLK-HACK.patch |   458 +
 ...-support-for-Meson8-Meson8b-Meson8m2.patch |    52 +
 .../0059-ARM-dts-meson-add-the-VPU-WiP.patch  |   272 +
 ...s-meson8-add-the-HDMI-controller-WiP.patch |   125 +
 ...8-Add-the-shared-CMA-dma-memory-pool.patch |    36 +
 ...meson8-add-the-AO-CEC-controller-WiP.patch |    50 +
 ...-meson8b-add-the-HDMI-controller-WiP.patch |   120 +
 ...eson8b-add-the-AO-CEC-controller-WiP.patch |    50 +
 ...odroid-c1-enable-HDMI-for-the-Odroid.patch |   106 +
 ...-clock-speed-before-sending-HS-CMD13.patch |    76 +
 ...-modify-and-simplify-calculation-in-.patch |    39 +
 .../meson-6.10/onecloud-0001-add-dts.patch    |   440 +
 .../onecloud-0002-dts-Support-HDMI.patch      |    96 +
 .../meson64-6.10/0000.patching_config.yaml    |    38 +
 .../board-bananapi-cm4-cm4io.patch            |    77 +
 .../meson64-6.10/board-bananapi-m2s.patch     |    62 +
 ...01-sd-use-270-mmc-clock-phase-via-dt.patch |    45 +
 ...d-bananapim5-002-add-wifi-bt-support.patch |   112 +
 ...oard-bananapism1-add-uart_A-and-AO_B.patch |    85 +
 ...ard-khadas-vim3-fix-missing-i2c3-nod.patch |    37 +
 ...ard-khadas-vims-add-rtc-vrtc-aliases.patch |    58 +
 .../board-nanopi-k2-add-uartC-alias.patch     |    26 +
 .../board-nanopi-k2-enable-emmc.patch         |    35 +
 .../board-odroidc2-add-uartA-uartC.patch      |    50 +
 .../board-odroidc2-enable-SPI.patch           |    52 +
 .../board-odroidc2-enable-scpi-dvfs.patch     |    27 +
 ...sable-autosuspend-for-Genesys-Logic-.patch |    33 +
 .../meson64-6.10/board-odroidc4-reset.patch   |    35 +
 .../board-odroidhc4-enable-fan1_input.patch   |    29 +
 ...ard-odroidn2plus-Add-missing-CPU-opp.patch |    46 +
 ...s-add-aliases-for-serial-i2c-and-spi.patch |    36 +
 ...add-support-for-the-usb-c-controller.patch |   104 +
 ...-dts-slow-down-sdio-for-working-wifi.patch |    29 +
 .../board-t95z-add-rc-remote-keymap.patch     |   153 +
 .../driver-power-meson64-reset.patch          |   236 +
 .../drv-spi-spidev-remove-warnings.patch      |    41 +
 .../dt/meson-axg-amper-gateway-am-gz80x.dts   |    87 +
 .../dt/meson-g12-enable-spinor.dtsi           |    13 +
 .../dt/meson-g12a-radxa-zero-spidev.dts       |    29 +
 .../meson-g12b-a311d-khadas-vim3-spidev.dts   |    29 +
 .../meson-g12b-a311d-khadas-vim3-spinor.dts   |    11 +
 .../dt/meson-g12b-odroid-n2-plus-spidev.dts   |    21 +
 .../dt/meson-g12b-odroid-n2-plus-spinor.dts   |    11 +
 .../dt/meson-g12b-odroid-n2-spinor.dts        |    11 +
 .../dt/meson-g12b-radxa-zero2-spidev.dts      |    29 +
 .../dt/meson-g12b-waveshare-cm4-io-base-b.dts |    64 +
 .../dt/meson-gxm-mini-m8s-pro.dts             |    91 +
 .../meson64-6.10/dt/meson-gxm-t95z-plus.dts   |   166 +
 .../meson-sm1-jethome-jethub-j200-spinor.dts  |    11 +
 .../dt/meson-sm1-jethome-jethub-j200.dts      |   705 +
 .../dt/meson-sm1-khadas-vim3l-spidev.dts      |    29 +
 .../dt/meson-sm1-khadas-vim3l-spinor.dts      |    11 +
 .../dt/meson-sm1-odroid-c4-spidev.dts         |    24 +
 .../meson64-6.10/dt/meson-sm1-ugoos-x3.dts    |   293 +
 ...eral-add-Amlogic-Meson-GX-PM-Suspend.patch |   134 +
 ...eral-add-overlay-compilation-support.patch |    64 +
 ...isplay-add-support-for-Titanmec-TM16.patch |   585 +
 ...hdmi-call-hdmi_set_cts_n-after-clock.patch |    30 +
 ...eral-drm-panfrost-fix-reference-leak.patch |    38 +
 ...ral-fix-Kodi-sysinfo-CPU-information.patch |    31 +
 ...add-new-display-resolution-2560x1440.patch |    72 +
 ...odec-reorder-channel-allocation-list.patch |   202 +
 ...put-touchscreen-Add-D-WAV-Multitouch.patch |   636 +
 ...cec-silence-CEC-timeout-message-HACK.patch |    40 +
 .../general-memory-marked-nomap.patch         |    38 +
 ...aiu-Fix-HDMI-codec-control-selection.patch |   232 +
 ...c-meson-gx-Add-core-tx-rx-eMMC-SD-SD.patch |   108 +
 ...s-meson-update-meson-axg-device-tree.patch |    44 +
 ...pdate-mmc-meson-gx-documentation-for.patch |    51 +
 ...ral-meson-vdec-add-HEVC-decode-codec.patch |  1608 +
 ...n-vdec-add-handling-to-HEVC-decoder-.patch |   157 +
 ...ec-check-if-parser-has-really-parser.patch |    51 +
 ...n-vdec-improve-mmu-and-fbc-handling-.patch |   587 +
 .../general-meson64-overlays.patch            |    27 +
 .../general-si2168-fix-cmd-timeout.patch      |    28 +
 ...mlogic-meson-gx-socinfo-Add-S905L-ID.patch |    30 +
 ...eson-gx-socinfo-add-new-A113X-SoC-id.patch |    29 +
 ...n-gx-socinfo-move-common-code-to-hea.patch |   339 +
 ...n-gx-socinfo-sm-Add-Amlogic-secure-m.patch |   275 +
 ...add-dts-links-to-secure-monitor-for-.patch |    68 +
 ...amlogic-amlogic-meson-gx-ao-secure-a.patch |    31 +
 ...soc-remove-mono-channel-as-it-curren.patch |    37 +
 ...al-spi-nor-add-support-for-XT25F128B.patch |    96 +
 ...prove-handling-of-hubs-with-no-ports.patch |    53 +
 .../hwmon-emc2305-fixups-for-driver.patch     |   212 +
 ...gpio-irq-patch-from-https-lkml.org-l.patch |   100 +
 ...rm64-dts-jethub-j1xx-add-eeprom-node.patch |    54 +
 ...o-secure-monitor-for-jethub.patch.disabled |    39 +
 ...amlogic-add-binding-for-JetHome-JetH.patch |    28 +
 .../kernel-6.8-tools-cgroup-makefile.patch    |    41 +
 ...-g12a-pinctrl-add-missing-ir-options.patch |    91 +
 ...b-pinctrl-Add-missing-pinmux-for-pwm.patch |   125 +
 ...x-dts-add-support-for-GX-PM-and-VRTC.patch |    40 +
 .../meson-gxbb-dts-i2cX-missing-pins.patch    |    35 +
 ...n-gxbb-vdec-add-HEVC-support-to-GXBB.patch |    39 +
 ...son-set-p212-p23x-q20x-SDIO-to-100MH.patch |   125 +
 ...eson-gxm-vdec-add-VP9-support-to-GXM.patch |    43 +
 .../meson-sm1-dts-add-higher-clocks.patch     |    34 +
 .../archive/meson64-6.10/overlay/Makefile     |    42 +
 .../overlay/README.meson-overlays             |    20 +
 .../meson64-6.10/overlay/meson-fixup.scr-cmd  |     4 +
 .../overlay/meson-g12-gxl-cma-pool-896MB.dtso |    19 +
 .../overlay/meson-g12-pwm-gpiox-5-fan.dtso    |    43 +
 .../meson-g12a-radxa-zero-gpio-10-led.dtso    |    26 +
 .../meson-g12a-radxa-zero-gpio-8-led.dtso     |    26 +
 ...adxa-zero-i2c-ao-m0-gpioao-2-gpioao-3.dtso |    15 +
 ...-radxa-zero-i2c-ee-m1-gpioh-6-gpioh-7.dtso |    15 +
 ...adxa-zero-i2c-ee-m1-gpiox-10-gpiox-11.dtso |    15 +
 ...adxa-zero-i2c-ee-m3-gpioa-14-gpioa-15.dtso |    15 +
 ...eson-g12a-radxa-zero-pwm-c-on-gpiox-8.dtso |    17 +
 ...-g12a-radxa-zero-pwmao-a-on-gpioao-11.dtso |    17 +
 .../meson-g12a-radxa-zero-spi-spidev.dtso     |    38 +
 ...a-zero-uart-ao-a-on-gpioao-0-gpioao-1.dtso |    15 +
 ...a-zero-uart-ao-b-on-gpioao-2-gpioao-3.dtso |    15 +
 ...a-zero-uart-ao-b-on-gpioao-8-gpioao-9.dtso |    15 +
 .../meson-g12a-radxa-zero-uart-ee-c.dtso      |    15 +
 ...son-g12b-bananapi-cm4-pwm-gpioh-5-fan.dtso |    63 +
 .../meson-g12b-bananapi-m2s-rtl8822cs.dtso    |    22 +
 .../overlay/meson-g12b-odroid-n2-spi.dtso     |    23 +
 .../meson-g12b-waveshare-cm4-io-base-usb.dtso |    20 +
 .../meson64-6.10/overlay/meson-i2cA.dtso      |    17 +
 .../meson64-6.10/overlay/meson-i2cB.dtso      |    17 +
 .../meson-sm1-bananapi-m5-rtl8822cs.dtso      |    22 +
 .../overlay/meson-sm1-bananapi-uartA.dtso     |    15 +
 .../overlay/meson-sm1-bananapi-uartAO_B.dtso  |    14 +
 .../meson-sm1-bananapi-uartA_cts_rts.dtso     |    17 +
 .../meson-sm1-jethome-jethub-j200-spi.dtso    |    19 +
 .../meson64-6.10/overlay/meson-uartA.dtso     |    11 +
 .../meson64-6.10/overlay/meson-uartC.dtso     |    11 +
 .../meson64-6.10/overlay/meson-w1-gpio.dtso   |    20 +
 .../meson64-6.10/overlay/meson-w1AB-gpio.dtso |    32 +
 .../dt/meson-axg-amper-gateway-am-gz80x.dts   |    87 +
 .../09-pci-link-retraining.patch.disabled     |   219 +
 ...-libata-add-ledtrig-support.patch.disabled |   136 +
 ...Enable-ATA-port-LED-trigger.patch.disabled |    30 +
 ...-mvebu-gpio-add_wake_on_gpio_support.patch |    88 +
 ...-hardcoded-timer-assignment.patch.disabled |   411 +
 ...-helios4-dts-add-wake-on-lan-support.patch |    21 +
 .../compile-dtb-with-symbol-support.patch     |    12 +
 ...s-disable-spi-flash-on-a388-microsom.patch |    10 +
 ..._DMA_block_memory_allocation_to_2048.patch |    11 +
 ...lock_atheros_regulatory_restrictions.patch |    70 +
 .../odroidxu4-6.6/patch-6.6.44-45.patch       |  5821 ++
 .../odroidxu4-6.6/patch-6.6.45-46.patch       |  6300 ++
 .../odroidxu4-6.6/patch-6.6.46-47.patch       |  4211 ++
 .../rockchip-6.10/0000.patching_config.yaml   |    35 +
 .../archive/rockchip-6.10/armbian.series      |    53 +
 .../archive/rockchip-6.10/dt/rk322x-box.dts   |   782 +
 .../rockchip-6.10/dt/rk3288-xt-q8l-v10.dts    |  1128 +
 .../kernel-6.8-tools-cgroup-makefile.patch    |    17 +
 .../archive/rockchip-6.10/libreelec.series    |     9 +
 .../archive/rockchip-6.10/overlay/Makefile    |    54 +
 .../overlay/README.rk322x-overlays            |    98 +
 .../overlay/README.rockchip-overlays          |    78 +
 .../overlay/rk322x-bt-8723cs.dtso             |    19 +
 .../overlay/rk322x-cpu-hs-lv.dtso             |    68 +
 .../rockchip-6.10/overlay/rk322x-cpu-hs.dtso  |    28 +
 .../overlay/rk322x-cpu-stability.dtso         |    52 +
 .../overlay/rk322x-ddr3-330.dtso              |    28 +
 .../overlay/rk322x-ddr3-528.dtso              |    28 +
 .../overlay/rk322x-ddr3-660.dtso              |    28 +
 .../overlay/rk322x-ddr3-800.dtso              |    28 +
 .../overlay/rk322x-emmc-ddr-ph180.dtso        |    14 +
 .../overlay/rk322x-emmc-ddr-ph45.dtso         |    14 +
 .../overlay/rk322x-emmc-hs200.dtso            |    13 +
 .../overlay/rk322x-emmc-pins.dtso             |    34 +
 .../rockchip-6.10/overlay/rk322x-emmc.dtso    |    20 +
 .../overlay/rk322x-fixup.scr-cmd              |     4 +
 .../overlay/rk322x-ir-wakeup.dtso             |    16 +
 .../overlay/rk322x-led-conf-default.dtso      |    22 +
 .../overlay/rk322x-led-conf1.dtso             |    64 +
 .../overlay/rk322x-led-conf2.dtso             |    64 +
 .../overlay/rk322x-led-conf3.dtso             |    64 +
 .../overlay/rk322x-led-conf4.dtso             |    96 +
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 .../overlay/rk322x-led-conf7.dtso             |   180 +
 .../overlay/rk322x-led-conf8.dtso             |   109 +
 .../rockchip-6.10/overlay/rk322x-nand.dtso    |    22 +
 .../overlay/rk322x-usb-otg-peripheral.dtso    |    11 +
 .../overlay/rk322x-wlan-alt-wiring.dtso       |    67 +
 .../overlay/rockchip-ds1307.dtbo              |   Bin 0 -> 485 bytes
 .../overlay/rockchip-ds1307.dtso              |    23 +
 .../overlay/rockchip-fixup.scr-cmd            |     4 +
 .../rockchip-6.10/overlay/rockchip-i2c1.dtbo  |   Bin 0 -> 262 bytes
 .../rockchip-6.10/overlay/rockchip-i2c1.dtso  |    16 +
 .../rockchip-6.10/overlay/rockchip-i2c4.dtbo  |   Bin 0 -> 262 bytes
 .../rockchip-6.10/overlay/rockchip-i2c4.dtso  |    16 +
 .../rockchip-6.10/overlay/rockchip-spi0.dtbo  |   Bin 0 -> 262 bytes
 .../rockchip-6.10/overlay/rockchip-spi0.dtso  |    16 +
 .../rockchip-6.10/overlay/rockchip-spi2.dtbo  |   Bin 0 -> 262 bytes
 .../rockchip-6.10/overlay/rockchip-spi2.dtso  |    16 +
 .../overlay/rockchip-spidev0.dtbo             |   Bin 0 -> 572 bytes
 .../overlay/rockchip-spidev0.dtso             |    35 +
 .../overlay/rockchip-spidev2.dtbo             |   Bin 0 -> 572 bytes
 .../overlay/rockchip-spidev2.dtso             |    35 +
 .../rockchip-6.10/overlay/rockchip-uart1.dtbo |   Bin 0 -> 263 bytes
 .../rockchip-6.10/overlay/rockchip-uart1.dtso |    16 +
 .../rockchip-6.10/overlay/rockchip-uart2.dtbo |   Bin 0 -> 263 bytes
 .../rockchip-6.10/overlay/rockchip-uart2.dtso |    16 +
 .../rockchip-6.10/overlay/rockchip-uart3.dtbo |   Bin 0 -> 263 bytes
 .../rockchip-6.10/overlay/rockchip-uart3.dtso |    16 +
 .../rockchip-6.10/overlay/rockchip-uart4.dtbo |   Bin 0 -> 263 bytes
 .../rockchip-6.10/overlay/rockchip-uart4.dtso |    16 +
 .../overlay/rockchip-w1-gpio.dtbo             |   Bin 0 -> 487 bytes
 .../overlay/rockchip-w1-gpio.dtso             |    23 +
 .../bt-broadcom-serdev-workaround.patch       |    27 +
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 .../driver-rk322x-audio-codec.patch           |   914 +
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 .../driver-tinkerboard-alc4040-codec.patch    |    19 +
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 .../drm-rk322x-yuv-10bit-modes.patch          |    44 +
 .../drm-rockchip-hardware-cursor.patch        |   358 +
 .../patches.armbian/dts-miqi-fan.patch        |    45 +
 .../patches.armbian/dts-miqi-hevc-rga.patch   |    42 +
 .../patches.armbian/dts-miqi-mali-gpu.patch   |    35 +
 .../dts-miqi-regulator-fix.patch              |    45 +
 .../patches.armbian/dts-rk322x-iep-node.patch |    34 +
 .../dts-rk322x-pinctrl-nand.patch             |    93 +
 .../dts-rk3288-disable-serial-dma.patch       |    40 +
 .../dts-rk3288-fix-mmc-aliases.patch          |    20 +
 .../dts-rk3288-gpu-500mhz-opp.patch           |    42 +
 .../dts-rk3288-pinctrl-spi2.patch             |    31 +
 .../dts-rk3288-thermal-rearrange-zones.patch  |    32 +
 .../dts-tinkerboard-bt-rtl8723bs.patch        |    34 +
 .../dts-tinkerboard-bt-uart-pins.patch        |    62 +
 .../dts-tinkerboard-hevc-rga.patch            |    43 +
 .../dts-tinkerboard-sdio-wifi.patch           |    98 +
 .../dts-tinkerboard-sdmmc-properties.patch    |    33 +
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 ...eral-add-overlay-compilation-support.patch |    64 +
 .../general-add-overlay-configfs.patch        |   358 +
 ...eral-add-restart-handler-for-act8846.patch |    71 +
 .../general-dwc2-fix-wait-peripheral.patch    |    26 +
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 ...eral-linux-export-mm-trace-rss-stats.patch |    24 +
 .../general-rk322x-gpio-ir-driver.patch       |   786 +
 .../general-rockchip-various-fixes.patch      |   770 +
 .../ir-keymap-rk322x-box.patch                |   119 +
 .../ir-keymap-xt-q8l-v10.patch                |   118 +
 .../misc-tinkerboard-spi-interface.patch      |    20 +
 .../mmc-tinkerboard-sdmmc-reboot-fix.patch    |   116 +
 .../rk322x-dmc-driver-01-sipv2-calls.patch    |   234 +
 .../rk322x-dmc-driver-02-sip-constants.patch  |    67 +
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 .../rk322x-dmc-driver-04-driver.patch         |  1155 +
 .../rk322x-dwc2-no-clock-gating.patch         |    27 +
 .../rk322x-usb-reset-props.patch              |    75 +
 .../wifi-ath9k-no-bulk-EP3-EP4.patch          |   102 +
 .../wifi-brcmfmac-add-bcm43342.patch          |    45 +
 .../wifi-brcmfmac-ap6330-firmware.patch       |    23 +
 .../patches.armbian/wifi-driver-esp8089.patch | 10931 ++++
 .../patches.armbian/wifi-driver-ssv6051.patch | 49482 ++++++++++++++++
 .../linux-0002-rockchip-from-list.patch       |   131 +
 .../linux-0011-v4l2-from-list.patch           |   659 +
 .../linux-1000-drm-rockchip.patch             |  2956 +
 .../linux-1001-v4l2-rockchip.patch            |   506 +
 .../linux-1002-for-libreelec.patch            |   688 +
 .../linux-1003-temp-dw_hdmi-rockchip.patch    |    63 +
 .../linux-2000-v4l2-wip-rkvdec-hevc.patch     |  3226 +
 .../linux-2001-v4l2-wip-iep-driver.patch      |  1805 +
 .../kernel/archive/rockchip-6.10/series.conf  |    62 +
 ...nopsys-designware-hdmi-rx-controller.patch |  3770 ++
 .../overlay/rockchip-rk3588-hdmirx.dtso       |    20 +
 .../rk3588-rock-5b_dts_add_rfkill-bt.patch    |    31 +
 .../0000.patching_config.yaml                 |    47 +
 .../0001-general-add-overlay-support.patch    |    69 +
 .../0010-fix-clk-divisions.patch              |   142 +
 .../0011-irqchip-fix-its-timeout-issue.patch  |   214 +
 .../0024-RK3588-Add-Crypto-Support.patch      |  2322 +
 .../0025-RK3588-Add-HW-RNG-Support.patch      |   663 +
 ...588-Add-VPU121-H.264-Decoder-Support.patch |   395 +
 .../0027-RK3588-Add-rkvdec2-Support-v3.patch  |  3887 ++
 ...Initialize-h264-frame_mbs_only_flag-.patch |    43 +
 ...64-dts-rockchip-rk3588-add-RGA2-node.patch |    34 +
 ...nopsys-designware-hdmi-rx-controller.patch |  3967 ++
 ...chip-samsung-hdptx-Enable-runtime-PM.patch |   123 +
 ...hip-samsung-hdptx-Add-clock-provider.patch |   323 +
 ...p-samsung-hdptx-Add-FRL-EARC-support.patch |   547 +
 ...-vop2-Improve-display-modes-handling.patch |   715 +
 ...itial-support-for-DW-HDMI-Controller.patch |  2603 +
 ...kchip-Add-HDMI0-bridge-CLK-to-rk3588.patch |    94 +
 ...ckchip-vop2-add-clocks-reset-support.patch |   187 +
 .../0801-wireless-add-bcm43752.patch          |    74 +
 .../0802-wireless-add-clk-property.patch      |    51 +
 ...b-Slow-down-emmc-to-hs200-and-add-ts.patch |    37 +
 ...dts-rockchip-Enable-HDMI0-on-rock-5b.patch |    67 +
 ...-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch |    41 +
 .../1020-Add-HDMI-and-VOP2-to-Rock-5A.patch   |    57 +
 ...rm64-dts-enable-gpu-node-for-rock-5a.patch |    36 +
 ...dd-missing-nodes-to-Orange-Pi-5-Plus.patch |   322 +
 ...ip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch |    39 +
 ...hip-Add-HDMI-support-to-ArmSoM-Sige7.patch |    64 +
 ...ip-Add-ap6275p-wireless-support-to-A.patch |    39 +
 .../1040-board-khadas-edge2-add-nodes.patch   |   359 +
 .../1041-board-khadas-edge2-mcu.patch         |   441 +
 ...dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch |    38 +
 .../dt/rk3588-bananapi-m7.dts                 |    10 +
 .../dt/rk3588-hinlink-h88k.dts                |   858 +
 .../dt/rk3588-mixtile-blade3.dts              |   712 +
 .../dt/rk3588-nanopc-cm3588-nas.dts           |  1436 +
 .../dt/rk3588s-nanopi-r6c.dts                 |    19 +
 .../dt/rk3588s-nanopi-r6s.dts                 |   865 +
 .../dt/rk3588s-orangepi-5.dts                 |   814 +
 .../dt/rk3588s-orangepi-5b.dts                |    48 +
 .../dt/rk3588s-rock-5c.dts                    |   825 +
 .../rockchip-rk3588-6.11/overlay/Makefile     |    46 +
 .../overlay/rockchip-rk3588-hdmirx.dtso       |    20 +
 .../overlay/rockchip-rk3588-i2c8-m2.dtso      |    14 +
 .../overlay/rockchip-rk3588-pwm0-m0.dtso      |    14 +
 .../overlay/rockchip-rk3588-pwm0-m1.dtso      |    13 +
 .../overlay/rockchip-rk3588-pwm0-m2.dtso      |    13 +
 .../overlay/rockchip-rk3588-pwm1-m0.dtso      |    14 +
 .../overlay/rockchip-rk3588-pwm1-m1.dtso      |    13 +
 .../overlay/rockchip-rk3588-pwm1-m2.dtso      |    13 +
 .../overlay/rockchip-rk3588-pwm10-m0.dtso     |    13 +
 .../overlay/rockchip-rk3588-pwm11-m0.dtso     |    13 +
 .../overlay/rockchip-rk3588-pwm11-m1.dtso     |    21 +
 .../overlay/rockchip-rk3588-pwm12-m0.dtso     |    13 +
 .../overlay/rockchip-rk3588-pwm13-m0.dtso     |    13 +
 .../overlay/rockchip-rk3588-pwm13-m2.dtso     |    13 +
 .../overlay/rockchip-rk3588-pwm14-m0.dtso     |    14 +
 .../overlay/rockchip-rk3588-pwm14-m1.dtso     |    14 +
 .../overlay/rockchip-rk3588-pwm14-m2.dtso     |    13 +
 .../overlay/rockchip-rk3588-pwm15-m0.dtso     |    21 +
 .../overlay/rockchip-rk3588-pwm15-m1.dtso     |    13 +
 .../overlay/rockchip-rk3588-pwm15-m2.dtso     |    13 +
 .../overlay/rockchip-rk3588-pwm15-m3.dtso     |    21 +
 .../overlay/rockchip-rk3588-pwm2-m1.dtso      |    21 +
 .../overlay/rockchip-rk3588-pwm3-m0.dtso      |    13 +
 .../overlay/rockchip-rk3588-pwm3-m1.dtso      |    21 +
 .../overlay/rockchip-rk3588-pwm3-m2.dtso      |    13 +
 .../overlay/rockchip-rk3588-pwm3-m3.dtso      |    13 +
 .../overlay/rockchip-rk3588-pwm5-m2.dtso      |    21 +
 .../overlay/rockchip-rk3588-pwm6-m0.dtso      |    21 +
 .../overlay/rockchip-rk3588-pwm6-m2.dtso      |    21 +
 .../overlay/rockchip-rk3588-pwm7-m0.dtso      |    21 +
 .../overlay/rockchip-rk3588-pwm7-m3.dtso      |    21 +
 .../overlay/rockchip-rk3588-pwm8-m0.dtso      |    21 +
 .../overlay/rockchip-rk3588-sata1.dtso        |    20 +
 .../overlay/rockchip-rk3588-sata2.dtso        |    20 +
 .../overlay/rockchip-rk3588-uart1-m1.dtso     |    13 +
 .../overlay/rockchip-rk3588-uart3-m1.dtso     |    13 +
 .../overlay/rockchip-rk3588-uart4-m2.dtso     |    13 +
 .../overlay/rockchip-rk3588-uart6-m1.dtso     |    13 +
 .../overlay/rockchip-rk3588-uart7-m2.dtso     |    13 +
 .../overlay/rockchip-rk3588-uart8-m1.dtso     |    13 +
 .../rockchip64-6.10/0000.patching_config.yaml |    37 +
 .../add-board-fine3399-dts.patch              |   876 +
 .../rockchip64-6.10/add-board-helios64.patch  |  1038 +
 .../add-board-xiaobao-nas-dts.patch           |   779 +
 .../board-firefly-rk3399-dts.patch            |   282 +
 ...rd-helios64-dts-fix-stability-issues.patch |    72 +
 .../board-helios64-remove-pcie-ep-gpios.patch |    25 +
 .../board-nanopc-t4-add-typec-dp.patch        |   147 +
 ...board-nanopi-m4v2-dts-add-sound-card.patch |   190 +
 .../board-nanopi-r2c-plus.patch               |    30 +
 .../rockchip64-6.10/board-nanopi-r2s.patch    |   735 +
 .../board-nanopi-r4s-pwmfan.patch             |    58 +
 .../board-orangepi-r1-plus.patch              |   216 +
 .../board-orangepi-rk3399-pcie.patch          |    68 +
 .../board-pbp-add-dp-alt-mode.patch           |   421 +
 .../board-radxa-e25-sdmmc0-fix.patch          |    35 +
 .../board-radxa-e25-usb3-and-emmc-fix.patch   |    64 +
 .../board-rk3328-roc-cc-dts-enable-dmc.patch  |    75 +
 .../board-rk3328-roc-cc-dts-ram-profile.patch |   330 +
 .../board-rk3328-roc-pc-dts-ram-profile.patch |   301 +
 .../rockchip64-6.10/board-rk3328-roc-pc.patch |   593 +
 .../board-rock3a-emmc-sfc.patch               |    54 +
 .../rockchip64-6.10/board-rock3a-usb3.patch   |    44 +
 .../board-rock64-mail-supply.patch            |    29 +
 .../board-rockpi3-enable-dmc.patch            |    44 +
 .../board-rockpi4-0003-arm64-dts-pcie.patch   |   130 +
 ...oard-rockpis-0001-arm64-dts.patch.disabled |   408 +
 ...s-rk3308-Add-gmac-node-at-dtsi-level.patch |    24 +
 ...ip-add-cpu-s-thermal-config-for-rk33.patch |    87 +
 ...ockchip-add-tsadc-support-for-rk3308.patch |    71 +
 ...chip-add-i2s_8ch-for-rk3308.patch.disabled |   126 +
 ...12-arm64-dts-rk3308-Add-rk-timer-rtc.patch |    32 +
 ...K3308-internal-codec-driver.patch.disabled |  2638 +
 ...nc-rk3308_codec-to-BSP-tree.patch.disabled |  6738 +++
 ...-Add-acodec-node-for-rk3308.patch.disabled |    50 +
 ...-replace-codec-to-component.patch.disabled |   459 +
 ...027-arm64-dts-rk3308-add-otp-cpuinfo.patch |   115 +
 ...s-rk3308-add-reserved-memory-ramoops.patch |    99 +
 ...ckpro64-0001-Add-pcie-bus-scan-delay.patch |    64 +
 ...d-rockpro64-change-rx_delay-for-gmac.patch |    26 +
 .../board-rockpro64-fix-emmc.patch            |   123 +
 ...board-rockpro64-fix-spi1-flash-speed.patch |   105 +
 .../board-rockpro64-work-led-heartbeat.patch  |    95 +
 .../board-rocks0-0001-deviceTree.patch        |   366 +
 .../rockchip64-6.10/board-station-p2.patch    |   580 +
 .../drv-spi-spidev-remove-warnings.patch      |    41 +
 .../dt/rk3308-sakurapi-rk3308b.dts            |   226 +
 .../archive/rockchip64-6.10/dt/rk3318-box.dts |  1007 +
 .../rockchip64-6.10/dt/rk3328-heltec.dts      |   288 +
 .../dt/rk3328-nanopi-neo3-rev02.dts           |   195 +
 .../dt/rk3328-nanopi-r2-rev00.dts             |   126 +
 .../dt/rk3328-nanopi-r2-rev06.dts             |    92 +
 .../dt/rk3328-nanopi-r2-rev20.dts             |    39 +
 .../dt/rk3328-orangepi-r1-plus-lts.dts        |   449 +
 .../rockchip64-6.10/dt/rk3328-z28pro.dts      |     1 +
 .../rockchip64-6.10/dt/rk3399-fine3399.dts    |   797 +
 .../rockchip64-6.10/dt/rk3399-nanopi-m4v2.dts |    87 +
 .../rockchip64-6.10/dt/rk3399-nanopi-r4se.dts |    17 +
 .../dt/rk3399-orangepi-4-lts.dts              |  1334 +
 .../rockchip64-6.10/dt/rk3399-orangepi-4.dts  |  1194 +
 .../rockchip64-6.10/dt/rk3399-rock-pi-4.dts   |     1 +
 .../rockchip64-6.10/dt/rk3399-rock-pi-4c.dts  |    69 +
 .../rockchip64-6.10/dt/rk3399-tinker-2.dts    |   751 +
 .../rockchip64-6.10/dt/rk3399-xiaobao-nas.dts |   774 +
 .../dt/rk3399pro-tinker-edge-r.dts            |  1080 +
 .../dt/rk3566-firefly-roc-pc.dts              |   760 +
 .../rockchip64-6.10/dt/rk3566-jp-tvbox.dts    |   579 +
 .../dt/rk3566-orangepi-3b-sata.dts            |    17 +
 .../rockchip64-6.10/dt/rk3566-orangepi-3b.dts |   869 +
 .../rockchip64-6.10/dt/rk3566-panther-x2.dts  |   579 +
 .../dt/rk3566-radxa-zero-3.dtsi               |   531 +
 .../dt/rk3566-radxa-zero-3e.dts               |    52 +
 .../dt/rk3566-radxa-zero-3w.dts               |    92 +
 .../rockchip64-6.10/dt/rk3566-rock-3c.dts     |   786 +
 .../dt/rk3568-hinlink-h66k.dts                |    21 +
 .../dt/rk3568-hinlink-h68k.dts                |   889 +
 .../rockchip64-6.10/dt/rk3568-odroid-m1.dts   |   775 +
 .../general-add-miniDP-dt-doc.patch           |   133 +
 .../general-add-miniDP-virtual-extcon.patch   |   382 +
 ...eral-add-overlay-compilation-support.patch |    64 +
 .../general-add-overlay-configfs.patch        |   419 +
 .../general-add-panel-simple-dsi.patch        |   856 +
 .../general-add-pll-hdmi-timings.patch        |   155 +
 .../general-add-xtx-spi-nor-chips.patch       |    82 +
 .../general-cryptov1-trng.patch               |   304 +
 .../general-disable-mtu-validation.patch      |    51 +
 .../general-fix-es8316-kernel-panic.patch     |   105 +
 .../general-fix-inno-usb2-phy-init.patch      |    28 +
 ...fix-mmc-signal-voltage-before-reboot.patch |    46 +
 .../general-hdmi-clock-fixes.patch            |   523 +
 ..._DMA_block_memory_allocation_to_2048.patch |    21 +
 .../general-legacy-rockchip-hwrng.patch       |   436 +
 .../general-legacy-rockchip-hwrng_5.10.patch  |   523 +
 ...l-possibility-of-disabling-rk808-rtc.patch |    51 +
 .../general-rk3328-dtsi-trb-ent-quirk.patch   |    61 +
 ...08-configurable-switch-voltage-steps.patch |   104 +
 .../general-rockchip-overlays.patch           |    28 +
 .../general-rt5651-add-mclk.patch             |   133 +
 .../general-v4l2-iep-driver.patch             |  1808 +
 .../general-v4l2-rkvdec-00-fixes.patch        |   659 +
 .../general-v4l2-rkvdec-01-vp9.patch          |   493 +
 .../general-v4l2-rkvdec-02-hevc.patch         |  3226 +
 ...eneral-workaround-broadcom-bt-serdev.patch |    26 +
 .../kernel-6.8-tools-cgroup-makefile.patch    |    17 +
 .../media-0001-Add-rkvdec2-Support-v3.patch   |     1 +
 ...Initialize-h264-frame_mbs_only_flag-.patch |     1 +
 ...edia-0003-rk3568-disable-hantro-h264.patch |    63 +
 ...-r8152-add-LED-configuration-from-OF.patch |    79 +
 .../archive/rockchip64-6.10/overlay/Makefile  |    57 +
 .../overlay/README.rockchip-overlays          |   259 +
 .../overlay/rk3308-b@1.3ghz.dtso              |    27 +
 .../rockchip64-6.10/overlay/rk3308-bs.dtso    |    39 +
 .../overlay/rk3308-bs@1.3ghz.dtso             |    26 +
 .../rockchip64-6.10/overlay/rk3308-emmc.dtso  |    13 +
 .../overlay/rk3308-s0-ext-antenna.dtso        |    48 +
 .../overlay/rk3308-sdio@10mhz.dtso            |    14 +
 .../overlay/rk3308-sdio@4mhz.dtso             |    14 +
 .../overlay/rockchip-fixup.scr-cmd            |    65 +
 .../overlay/rockchip-rk3318-box-cpu-hs.dtso   |    24 +
 .../overlay/rockchip-rk3318-box-emmc-ddr.dtso |    14 +
 .../rockchip-rk3318-box-emmc-hs200.dtso       |    14 +
 .../rockchip-rk3318-box-led-conf1.dtso        |    49 +
 .../rockchip-rk3318-box-led-conf2.dtso        |    63 +
 .../rockchip-rk3318-box-led-conf3.dtso        |   305 +
 .../rockchip-rk3318-box-led-conf4.dtso        |    38 +
 .../rockchip-rk3318-box-wlan-ap6330.dtso      |   106 +
 .../rockchip-rk3318-box-wlan-ap6334.dtso      |   117 +
 .../overlay/rockchip-rk3318-box-wlan-ext.dtso |    33 +
 .../overlay/rockchip-rk3328-i2c0.dtso         |    13 +
 .../overlay/rockchip-rk3328-i2s1-pcm5102.dtso |   104 +
 .../overlay/rockchip-rk3328-opp-1.4ghz.dtso   |    15 +
 .../overlay/rockchip-rk3328-opp-1.5ghz.dtso   |    15 +
 .../overlay/rockchip-rk3328-spi-spidev.dtso   |    33 +
 .../overlay/rockchip-rk3328-uart1.dtso        |    17 +
 .../overlay/rockchip-rk3399-dwc3-0-host.dtso  |    13 +
 .../overlay/rockchip-rk3399-i2c7.dtso         |    11 +
 .../overlay/rockchip-rk3399-i2c8.dtso         |    11 +
 .../overlay/rockchip-rk3399-opp-2ghz.dtso     |    24 +
 .../overlay/rockchip-rk3399-pcie-gen2.dtso    |    12 +
 .../rockchip-rk3399-spi-jedec-nor.dtso        |    72 +
 .../overlay/rockchip-rk3399-spi-spidev.dtso   |    72 +
 .../overlay/rockchip-rk3399-uart4.dtso        |    20 +
 .../overlay/rockchip-rk3399-w1-gpio.dtso      |    20 +
 .../overlay/rockchip-rk3566-sata2.dtso        |    20 +
 .../overlay/rockchip-rk3568-hk-i2c0.dtso      |    14 +
 .../overlay/rockchip-rk3568-hk-i2c1.dtso      |    12 +
 .../overlay/rockchip-rk3568-hk-pwm1.dtso      |    13 +
 .../overlay/rockchip-rk3568-hk-pwm2.dtso      |    13 +
 .../overlay/rockchip-rk3568-hk-pwm9.dtso      |    13 +
 .../rockchip-rk3568-hk-spi-spidev.dtso        |    22 +
 .../rockchip-rk3568-hk-uart0-rts_cts.dtso     |    14 +
 .../overlay/rockchip-rk3568-hk-uart0.dtso     |    13 +
 .../overlay/rockchip-rk3568-hk-uart1.dtso     |    15 +
 .../rockchip-rk3568-nanopi-r5c-leds.dtso      |    11 +
 .../rockchip-rk3568-nanopi-r5s-leds.dtso      |    15 +
 .../rockchip-rockpi4cplus-usb-host.dtso       |    16 +
 .../overlay/rockchip-rockpro64-lcd.dtso       |    58 +
 ...28-iomux-width-flag-for-GPIO2-B-pins.patch |    13 +
 .../regulator-add-fan53200-driver.patch       |   597 +
 .../rk3308-0001-pinctrl-slew-mux.patch        |   257 +
 .../rk3308-0002-iodomains.patch               |   159 +
 ...3308-0003-pinctrl-io-voltage-domains.patch |   202 +
 .../rk3308-add-missing-i2s-controllers.patch  |    82 +
 .../rk3328-add-dmc-driver.patch               |  1901 +
 .../rockchip64-6.10/rk3328-add-rga-node.patch |    37 +
 .../rk3328-dtsi-mali-opp-table.patch          |    48 +
 .../rk3328-dtsi-mmc-reset-properties.patch    |    43 +
 .../rk3328-dtsi-sdmmc-ext-node.patch          |    37 +
 .../rockchip64-6.10/rk3328-dtsi-spdif.patch   |   128 +
 .../rk3328-dtsi-usb3-reset-properties.patch   |    25 +
 .../rk3328-gpu-cooling-target.patch           |    37 +
 .../rk3328-roc-cc-add-missing-nodes.patch     |    79 +
 .../rk3399-add-sclk-i2sout-src-clock.patch    |    98 +
 .../rk3399-dmc-polling-rate.patch             |    35 +
 ...k3399-enable-dwc3-xhci-usb-trb-quirk.patch |   119 +
 .../rockchip64-6.10/rk3399-fix-pci-phy.patch  |    47 +
 .../rockchip64-6.10/rk3399-fix-usb-phy.patch  |    26 +
 ...plement-rockchip-PCIe-bus-scan-delay.patch |   181 +
 .../rk3399-sd-drive-level-8ma.patch           |   159 +
 .../rk3399-sd-pwr-pinctrl.patch               |    28 +
 .../rk3399-unlock-temperature.patch           |   127 +
 .../rk356x-add-rkvdec2-support.patch          |    59 +
 .../rk35xx-montjoie-crypto-v2-rk35xx.patch    |  2327 +
 .../wifi-4003-add-bcm43342-chip.patch         |    45 +
 .../wifi-4003-ssv-6051-driver.patch           | 49482 ++++++++++++++++
 ...oard-rockpis-0001-arm64-dts.patch.disabled |   406 +
 .../rockchip64-6.6/board-station-p2.patch     |   580 +
 ...drivers-regulator-fan53555-bug-fixed.patch |    44 +
 .../rockchip64-6.6/dt/rk3328-heltec.dts       |   288 +
 ...28-iomux-width-flag-for-GPIO2-B-pins.patch |    13 +
 ...drivers-regulator-fan53555-bug-fixed.patch |    44 +
 .../rockchip64-6.9/dt/rk3328-heltec.dts       |   288 +
 ...28-iomux-width-flag-for-GPIO2-B-pins.patch |    13 +
 ...e-ASAP-after-writing-new-instruction.patch |    63 +
 .../ARM-dts-axp813-Add-charger-LED.patch      |    30 +
 ...Book-Touch-Lux-3-display-ctp-support.patch |   185 +
 .../ARM-dts-sun5i-Add-soc-handle.patch        |    26 +
 ...book-touch-lux-3-Add-RTC-clock-cells.patch |    27 +
 .../ARM-dts-sun8i-a83t-Add-MBUS-node.patch    |    39 +
 ...us-video-codec-support-to-A83T-untes.patch |    37 +
 ...M-dts-sun8i-a83t-Add-hdmi-sound-card.patch |    48 +
 ...un8i-a83t-Add-missing-GPU-trip-point.patch |    35 +
 ...-hdmi-sound-card-on-boards-with-hdmi.patch |    69 +
 ...prove-CPU-OPP-tables-go-up-to-1.8GHz.patch |   134 +
 ...s-sun8i-a83t-Set-fifo-size-for-uarts.patch |    59 +
 ...-a83t-tbs-a711-Add-PN544-NFC-support.patch |    66 +
 ...711-Add-camera-sensors-HM5065-GC2145.patch |   180 +
 ...-a83t-tbs-a711-Add-flash-led-support.patch |    32 +
 ...-Add-powerup-down-support-for-the-3G.patch |    61 +
 ...-Add-regulators-to-the-accelerometer.patch |    30 +
 ...11-Add-sound-support-via-AC100-codec.patch |   131 +
 ...1-Add-support-for-the-vibrator-motor.patch |    39 +
 ...8i-a83t-tbs-a711-Enable-charging-LED.patch |    31 +
 ...-Give-Linux-more-privileges-over-SCP.patch |    47 +
 ...711-Increase-voltage-on-the-vibrator.patch |    30 +
 ...s-bananapi-m2-zero-Enable-HDMI-audio.patch |    42 +
 ...-hdmi-sound-card-on-boards-with-hdmi.patch |   272 +
 ...se-my-own-more-aggressive-OPPs-on-H3.patch |    72 +
 ...-pi-one-Enable-all-gpio-header-UARTs.patch |    49 +
 ...pc-Increase-max-CPUX-voltage-to-1.4V.patch |    31 +
 ...RM-dts-sun8i-r40-Add-hdmi-sound-card.patch |    48 +
 ...-bananapi-m2-ultra-Enable-HDMI-audio.patch |    42 +
 ...-bananapi-m2-berry-Enable-HDMI-audio.patch |    42 +
 .../ARM-dts-suni-a83t-Add-i2s0-pins.patch     |    29 +
 .../ARM-dts-sunxi-Add-aliases-for-MMC.patch   |    66 +
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 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
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 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
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 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
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 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/spi-fixes.patch
 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch
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 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
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 create mode 100644 patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/add-dtb-overlay-for-zero2w.patch
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 create mode 100644 patch/kernel/rk35xx-legacy/001-hid-sony.patch
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 create mode 100644 patch/u-boot/u-boot-tqma/0003-imx-mkimage_fit_atf_imx8mp.sh-add-script-for-imx8mp.patch
 create mode 100644 patch/u-boot/v2024.04/board_gateway-gz80x/001-Add-board-Amper-Gateway-AM-GZ80x.patch
 create mode 100644 patch/u-boot/v2024.04/board_gateway-gz80x/002-HACK-mmc-meson-gx-limit-to-24MHz.patch
 create mode 100644 patch/u-boot/v2024.04/board_gateway-gz80x/003-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch
 create mode 100644 patch/u-boot/v2024.04/board_gateway-gz80x/004-HACK-meson64-boot-target-usb.patch
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 create mode 100644 patch/u-boot/v2024.07/board_orangepi5-plus/orangepi5-plus_kaslrseed.patch

diff --git a/.github/workflows/merge-announce.yml b/.github/workflows/merge-announce.yml
new file mode 100644
index 000000000000..7b53e680b795
--- /dev/null
+++ b/.github/workflows/merge-announce.yml
@@ -0,0 +1,20 @@
+name: push
+
+on:
+  push:
+    branches: [ main ]
+
+jobs:
+  announcepush:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Get repo
+        uses: actions/checkout@v4
+        with:
+          ref: ${{ github.event.pull_request.head.sha }}
+      - name: Send push to Discord
+        run: |
+          curl -i -H "Accept: application/json" -H "Content-Type: application/json" -X POST --data \
+          "{\"username\": \"Github\", \"avatar_url\": \"${{ secrets.AVATARURL }}\", \"content\": \"\
+          :white_check_mark: **Merged** into [$GITHUB_REPOSITORY](<$GITHUB_SERVER_URL/$GITHUB_REPOSITORY>) by [$GITHUB_ACTOR](<$GITHUB_SERVER_URL/$GITHUB_ACTOR>) - \
+          [Link](<$GITHUB_SERVER_URL/$GITHUB_REPOSITORY/commit/$GITHUB_SHA>): *$(git show -s --format=%s)*\"}" ${{ secrets.WEBHOOKURL }}
diff --git a/.github/workflows/pr-announce.yml b/.github/workflows/pr-announce.yml
new file mode 100644
index 000000000000..6953ba98d567
--- /dev/null
+++ b/.github/workflows/pr-announce.yml
@@ -0,0 +1,25 @@
+name: "Announce PR on Discord for review"
+run-name: 'Announce PR #${{ github.event.pull_request.number }} on Discord for review'
+
+on:
+  pull_request:
+    types: [ labeled ]
+
+jobs:
+  Announce:
+    permissions:
+      pull-requests: read
+
+    runs-on: ubuntu-latest
+    if: ${{ github.repository == 'armbian/build' && github.event.label.id == '6210849975' }}
+    steps:
+      - name: Get repo
+        uses: actions/checkout@v4
+        with:
+          ref: ${{ github.event.pull_request.head.sha }}
+      - name: Discord webhook
+        run: |
+          curl -i -H "Accept: application/json" -H "Content-Type: application/json" -X POST --data \
+          "{\"username\": \"Github\", \"avatar_url\": \"${{ secrets.AVATARURL }}\", \"content\": \"\
+          :arrow_heading_up: **Pull request** to [$GITHUB_REPOSITORY](<$GITHUB_SERVER_URL/$GITHUB_REPOSITORY>) by [$GITHUB_ACTOR](<$GITHUB_SERVER_URL/$GITHUB_ACTOR>) - **Please review!** \
+          :point_right: [Link](<$GITHUB_SERVER_URL/$GITHUB_REPOSITORY/pull/${{github.event.pull_request.number}}>): *$(git show -s --format=%s)*\"}" ${{ secrets.WEBHOOKURL }}
diff --git a/config/boards/armsom-aim7-io.csc b/config/boards/armsom-aim7-io.csc
new file mode 100644
index 000000000000..bfb4099e2010
--- /dev/null
+++ b/config/boards/armsom-aim7-io.csc
@@ -0,0 +1,21 @@
+# Rockchip RK3588 SoC octa core 8-32GB SoC 2.5GBe eMMC USB3 NvME
+BOARD_NAME="ArmSoM AIM7 IO"
+BOARDFAMILY="rockchip-rk3588"
+BOARD_MAINTAINER=""
+BOOTCONFIG="armsom-aim7-io-rk3588_defconfig"
+KERNEL_TARGET="vendor"
+FULL_DESKTOP="yes"
+BOOT_LOGO="desktop"
+BOOT_FDT_FILE="rockchip/rk3588-armsom-aim7-io.dtb"
+BOOT_SCENARIO="spl-blobs"
+IMAGE_PARTITION_TABLE="gpt"
+
+function post_family_tweaks__armsom-aim7-io_naming_audios() {
+	display_alert "$BOARD" "Renaming audios" "info"
+
+	mkdir -p $SDCARD/etc/udev/rules.d/
+	echo 'SUBSYSTEM=="sound", ENV{ID_PATH}=="platform-hdmi0-sound", ENV{SOUND_DESCRIPTION}="HDMI0 Audio"' > $SDCARD/etc/udev/rules.d/90-naming-audios.rules
+	echo 'SUBSYSTEM=="sound", ENV{ID_PATH}=="platform-dp0-sound", ENV{SOUND_DESCRIPTION}="DP0 Audio"' >> $SDCARD/etc/udev/rules.d/90-naming-audios.rules
+
+	return 0
+}
diff --git a/config/boards/ayn-odin2.eos b/config/boards/ayn-odin2.eos
new file mode 100644
index 000000000000..9cbef2db7a2c
--- /dev/null
+++ b/config/boards/ayn-odin2.eos
@@ -0,0 +1,155 @@
+# Generate kernel and rootfs image for Qcom ABL Custom booting
+declare -g BOARD_NAME="Ayn Odin2"
+declare -g BOARD_MAINTAINER="FantasyGmm"
+declare -g BOARDFAMILY="qcom-abl"
+declare -g KERNEL_TARGET="sm8550"
+declare -g KERNELPATCHDIR="sm8550-6.7"
+declare -g EXTRAWIFI="no"
+declare -g BOOTCONFIG="none"
+declare -g BOOTFS_TYPE="fat"
+declare -g BOOTSIZE="256"
+declare -g BOOTIMG_CMDLINE_EXTRA="clk_ignore_unused pd_ignore_unused panic=30 audit=0 allow_mismatched_32bit_el0 rw mem_sleep_default=s2idle"
+declare -g IMAGE_PARTITION_TABLE="gpt"
+
+# Use the full firmware, complete linux-firmware plus Armbian's
+declare -g BOARD_FIRMWARE_INSTALL="-full"
+
+declare -g DESKTOP_AUTOLOGIN="yes"
+
+function post_family_config_branch_sm8550__edk2_kernel() {
+	declare -g KERNELSOURCE='https://github.com/edk2-porting/linux-next'
+	declare -g KERNEL_MAJOR_MINOR="6.7" # Major and minor versions of this kernel.
+	declare -g KERNELBRANCH="branch:integration/ayn-odin2"
+	declare -g LINUXCONFIG="linux-${ARCH}-${BRANCH}" # for this board: linux-arm64-sm8550
+	display_alert "Setting up kernel ${KERNEL_MAJOR_MINOR} for" "${BOARD}" "info"
+}
+
+function ayn-odin2_is_userspace_supported() {
+	[[ "${RELEASE}" == "trixie" || "${RELEASE}" == "sid" || "${RELEASE}" == "mantic" || "${RELEASE}" == "noble" ]] && return 0
+	return 1
+}
+
+function post_family_tweaks__enable_services() {
+	if ! ayn-odin2_is_userspace_supported; then
+		if [[ "${RELEASE}" != "" ]]; then
+			display_alert "Missing userspace for ${BOARD}" "${RELEASE} does not have the userspace necessary to support the ${BOARD}" "warn"
+		fi
+		return 0
+	fi
+
+	if [[ "${RELEASE}" == "noble" ]]; then
+		display_alert "Adding Mesa PPA For Ubuntu " "${BOARD}" "info"
+		do_with_retries 3 chroot_sdcard add-apt-repository ppa:oibaf/graphics-drivers --yes --no-update
+	fi
+
+	# We need unudhcpd from armbian repo, so enable it
+	mv "${SDCARD}"/etc/apt/sources.list.d/armbian.list.disabled "${SDCARD}"/etc/apt/sources.list.d/armbian.list
+
+	# Add zink env
+	echo '__GLX_VENDOR_LIBRARY_NAME=mesa' | tee -a "${SDCARD}"/etc/environment
+	echo 'MESA_LOADER_DRIVER_OVERRIDE=zink' | tee -a "${SDCARD}"/etc/environment
+	echo 'GALLIUM_DRIVER=zink' | tee -a "${SDCARD}"/etc/environment
+	# Add Gamepad udev rule
+	echo 'SUBSYSTEM=="input", ATTRS{name}=="Ayn Odin2 Gamepad", MODE="0666", ENV{ID_INPUT_MOUSE}="0", ENV{ID_INPUT_JOYSTICK}="1"' > "${SDCARD}"/etc/udev/rules.d/99-ignore-gamepad.rules
+	# No driver support for suspend
+	chroot_sdcard systemctl mask suspend.target
+	# Add Bt Mac Fixed service
+	install -Dm655 $SRC/packages/bsp/ayn-odin2/bt-fixed-mac.sh "${SDCARD}"/usr/local/bin/
+	install -Dm644 $SRC/packages/bsp/ayn-odin2/bt-fixed-mac.service "${SDCARD}"/usr/lib/systemd/system/
+	chroot_sdcard systemctl enable bt-fixed-mac
+
+	do_with_retries 3 chroot_sdcard_apt_get_update
+	display_alert "$BOARD" "Installing board tweaks" "info"
+	do_with_retries 3 chroot_sdcard_apt_get_install alsa-ucm-conf unudhcpd mkbootimg git
+
+	# Disable armbian repo back
+	mv "${SDCARD}"/etc/apt/sources.list.d/armbian.list "${SDCARD}"/etc/apt/sources.list.d/armbian.list.disabled
+	do_with_retries 3 chroot_sdcard_apt_get_update
+
+	do_with_retries 3 chroot_sdcard_apt_get_install mesa-vulkan-drivers qbootctl qrtr-tools protection-domain-mapper tqftpserv
+
+	# Kernel postinst script to update abl boot partition
+	install -Dm655 $SRC/packages/bsp/ayn-odin2/zz-update-abl-kernel "${SDCARD}"/etc/kernel/postinst.d/
+
+	cp $SRC/packages/bsp/ayn-odin2/LinuxLoader.cfg "${SDCARD}"/boot/
+
+	return 0
+}
+
+function post_family_tweaks__preset_configs() {
+	display_alert "$BOARD" "preset configs for rootfs" "info"
+	# Set PRESET_NET_CHANGE_DEFAULTS to 1 to apply any network related settings below
+	echo "PRESET_NET_CHANGE_DEFAULTS=1" > "${SDCARD}"/root/.not_logged_in_yet
+
+	# Enable WiFi or Ethernet.
+	#      NB: If both are enabled, WiFi will take priority and Ethernet will be disabled.
+	echo "PRESET_NET_ETHERNET_ENABLED=0" >> "${SDCARD}"/root/.not_logged_in_yet
+	echo "PRESET_NET_WIFI_ENABLED=1" >> "${SDCARD}"/root/.not_logged_in_yet
+
+	# Preset user default shell, you can choose bash or zsh
+	echo "PRESET_USER_SHELL=zsh" >> "${SDCARD}"/root/.not_logged_in_yet
+
+	# Set PRESET_CONNECT_WIRELESS=y if you want to connect wifi manually at first login
+	echo "PRESET_CONNECT_WIRELESS=n" >> "${SDCARD}"/root/.not_logged_in_yet
+
+	# Set SET_LANG_BASED_ON_LOCATION=n if you want to choose "Set user language based on your location?" with "n" at first login
+	echo "SET_LANG_BASED_ON_LOCATION=y" >> "${SDCARD}"/root/.not_logged_in_yet
+
+	# Preset default locale
+	echo "PRESET_LOCALE=en_US.UTF-8" >> "${SDCARD}"/root/.not_logged_in_yet
+
+	# Preset timezone
+	echo "PRESET_TIMEZONE=Etc/UTC" >> "${SDCARD}"/root/.not_logged_in_yet
+
+	# Preset root password
+	echo "PRESET_ROOT_PASSWORD=admin" >> "${SDCARD}"/root/.not_logged_in_yet
+
+	# Preset username
+	echo "PRESET_USER_NAME=odin" >> "${SDCARD}"/root/.not_logged_in_yet
+
+	# Preset user password
+	echo "PRESET_USER_PASSWORD=admin" >> "${SDCARD}"/root/.not_logged_in_yet
+
+	# Preset user default realname
+	echo "PRESET_DEFAULT_REALNAME=Odin" >> "${SDCARD}"/root/.not_logged_in_yet
+}
+
+function post_family_tweaks_bsp__firmware_in_initrd() {
+	random_mac=$(openssl rand -hex 6 | sed 's/\(..\)/\1:/g; s/.$//')
+	declare -g BOOTIMG_CMDLINE_EXTRA="${BOOTIMG_CMDLINE_EXTRA} bt_mac=${random_mac}"
+	display_alert "Generate a random Bluetooth MAC address, Mac:${random_mac}" "info"
+	display_alert "Adding to bsp-cli" "${BOARD}: firmware in initrd" "info"
+	declare file_added_to_bsp_destination # Will be filled in by add_file_from_stdin_to_bsp_destination
+	# Using odin2's firmware for now
+	add_file_from_stdin_to_bsp_destination "/etc/initramfs-tools/hooks/ayn-odin2-firmware" <<- 'FIRMWARE_HOOK'
+		#!/bin/bash
+		[[ "$1" == "prereqs" ]] && exit 0
+		. /usr/share/initramfs-tools/hook-functions
+		for f in /lib/firmware/qcom/sm8550/ayn/odin2/* ; do
+			add_firmware "${f#/lib/firmware/}"
+		done
+		add_firmware "qcom/a740_sqe.fw" # Extra one for dpu
+		add_firmware "qcom/gmu_gen70200.bin" # Extra one for gpu
+		# Extra one for wifi
+		for f in /lib/firmware/ath12k/WCN7850/hw2.0/* ; do
+			add_firmware "${f#/lib/firmware/}"
+		done
+		# Extra one for bt
+		for f in /lib/firmware/qca/* ; do
+			add_firmware "${f#/lib/firmware/}"
+		done 
+	FIRMWARE_HOOK
+	run_host_command_logged chmod -v +x "${file_added_to_bsp_destination}"
+}
+
+function pre_umount_final_image__update_ABL_settings() {
+	if [ -z "$BOOTFS_TYPE" ]; then
+		return 0
+	fi
+	display_alert "Update ABL settings for " "${BOARD}" "info"
+	uuid_line=$(head -n 1 "${SDCARD}"/etc/fstab)
+	rootfs_image_uuid=$(echo "${uuid_line}" | awk '{print $1}' | awk -F '=' '{print $2}')
+	initrd_name=$(find "${SDCARD}/boot/" -type f -name "config-*" | sed 's/.*config-//')
+	sed -i "s/UUID_PLACEHOLDER/${rootfs_image_uuid}/g" "${MOUNT}"/boot/LinuxLoader.cfg
+	sed -i "s/INITRD_PLACEHOLDER/${initrd_name}/g" "${MOUNT}"/boot/LinuxLoader.cfg
+}
diff --git a/config/boards/bananapi.conf b/config/boards/bananapi.conf
new file mode 100644
index 000000000000..15079e1aeff7
--- /dev/null
+++ b/config/boards/bananapi.conf
@@ -0,0 +1,15 @@
+# Allwinner A20 dual core 1Gb RAM SoC 1xSATA GBE
+BOARD_NAME="Banana Pi"
+BOARDFAMILY="sun7i"
+BOARD_MAINTAINER="janprunk"
+BOOTCONFIG="Bananapi_defconfig"
+KERNEL_TARGET="legacy,current,edge"
+KERNEL_TEST_TARGET="current"
+
+function post_config_uboot_target__extra_configs_for_bananapi() {
+	display_alert "$BOARD" "set dram clock" "info"
+	run_host_command_logged scripts/config --set-val CONFIG_DRAM_CLK "384"
+
+	display_alert "$BOARD" "disable de2 to improve edid detection" "info"
+	run_host_command_logged scripts/config --disable CONFIG_VIDEO_DE2
+}
diff --git a/config/boards/gateway-gz80x.conf b/config/boards/gateway-gz80x.conf
new file mode 100644
index 000000000000..6640b7803714
--- /dev/null
+++ b/config/boards/gateway-gz80x.conf
@@ -0,0 +1,19 @@
+# Amlogic A113X quad core 1Gb RAM SoC, eMMC 8Gb
+BOARD_NAME="Gateway GZ80x"
+BOARDFAMILY="meson-axg"
+BOARD_MAINTAINER="pyavitz"
+BOOTCONFIG="amper_gateway_am-gz80x_defconfig"
+KERNEL_TARGET="current,edge"
+KERNEL_TEST_TARGET="current"
+BOOTBRANCH_BOARD="tag:v2024.04"
+BOOTPATCHDIR="v2024.04"
+BOOT_FDT_FILE="amlogic/meson-axg-amper-gateway-am-gz80x.dtb"
+SRC_EXTLINUX="yes"
+SRC_CMDLINE="console=ttyAML0,115200n8 clk_ignore_unused loglevel=7"
+HAS_VIDEO_OUTPUT="no"
+
+function post_family_tweaks_bsp__gateway_gz80x_udev() {
+	mkdir -p "${destination}"/etc/udev/rules.d
+	display_alert "$BOARD" "Install zwave udev rule" "info"
+	echo 'KERNEL=="ttyAML2", NAME="tts/%n", SYMLINK+="zwave", GROUP="dialout", MODE="0660"' > "${destination}"/etc/udev/rules.d/10-zwave.rules
+}
diff --git a/config/boards/nanopct6.conf b/config/boards/nanopct6.conf
new file mode 100644
index 000000000000..a73349ef347d
--- /dev/null
+++ b/config/boards/nanopct6.conf
@@ -0,0 +1,107 @@
+# Rockchip RK3588S octa core 8GB RAM SoC eMMC USB3 USB2 1x GbE 2x 2.5GbE
+BOARD_NAME="NanoPC T6"
+BOARDFAMILY="rockchip-rk3588"
+BOARD_MAINTAINER="Tonymac32"
+BOOTCONFIG="nanopc_t6_defconfig" # vendor name, not standard, see hook below, set BOOT_SOC below to compensate
+BOOT_SOC="rk3588"
+KERNEL_TARGET="edge,current,vendor"
+KERNEL_TEST_TARGET="vendor,current"
+FULL_DESKTOP="yes"
+BOOT_LOGO="desktop"
+BOOT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
+BOOT_SCENARIO="spl-blobs"
+BOOT_SUPPORT_SPI="yes"
+BOOT_SPI_RKSPI_LOADER="yes"
+IMAGE_PARTITION_TABLE="gpt"
+declare -g UEFI_EDK2_BOARD_ID="nanopc-t6" # This _only_ used for uefi-edk2-rk3588 extension
+
+function post_family_tweaks__nanopct6_naming_audios() {
+	display_alert "$BOARD" "Renaming nanopct6 audio" "info"
+
+	mkdir -p $SDCARD/etc/udev/rules.d/
+	echo 'SUBSYSTEM=="sound", ENV{ID_PATH}=="platform-hdmi0-sound", ENV{SOUND_DESCRIPTION}="HDMI0 Audio"' > $SDCARD/etc/udev/rules.d/90-naming-audios.rules
+
+	return 0
+}
+
+# Mainline u-boot or Kwiboo's tree
+function post_family_config_branch_edge__nanopct6_use_mainline_uboot() {
+	display_alert "$BOARD" "mainline (next branch) u-boot overrides for $BOARD / $BRANCH" "info"
+
+	declare -g BOOTCONFIG="nanopc-t6-rk3588_defconfig"                    # override the default for the board/family
+	declare -g BOOTDELAY=1                                                # Wait for UART interrupt to enter UMS/RockUSB mode etc
+	declare -g BOOTSOURCE="https://github.com/Kwiboo/u-boot-rockchip.git" # We ❤️ Kwiboo's tree
+	declare -g BOOTBRANCH="branch:rk3xxx-2024.07"                         # commit:xx as of 2024-06-04
+	declare -g BOOTPATCHDIR="v2024.04/board_${BOARD}"                     # empty; defconfig changes are done in hook below
+	declare -g BOOTDIR="u-boot-${BOARD}"                                  # do not share u-boot directory
+	declare -g UBOOT_TARGET_MAP="BL31=${RKBIN_DIR}/${BL31_BLOB} ROCKCHIP_TPL=${RKBIN_DIR}/${DDR_BLOB};;u-boot-rockchip.bin u-boot-rockchip-spi.bin"
+	unset uboot_custom_postprocess write_uboot_platform write_uboot_platform_mtd # disable stuff from rockchip64_common; we're using binman here which does all the work already
+
+	# Just use the binman-provided u-boot-rockchip.bin, which is ready-to-go
+	function write_uboot_platform() {
+		dd "if=$1/u-boot-rockchip.bin" "of=$2" bs=32k seek=1 conv=notrunc status=none
+	}
+
+	function write_uboot_platform_mtd() {
+		flashcp -v -p "$1/u-boot-rockchip-spi.bin" /dev/mtd0
+	}
+}
+
+function post_config_uboot_target__extra_configs_for_nanopct6_mainline_environment_in_spi() {
+	[[ "${BRANCH}" != "edge" ]] && return 0
+
+	display_alert "$BOARD" "u-boot configs for ${BOOTBRANCH} u-boot config BRANCH=${BRANCH}" "info"
+	run_host_command_logged scripts/config --set-val CONFIG_ENV_IS_NOWHERE "n"
+	run_host_command_logged scripts/config --set-val CONFIG_ENV_IS_IN_SPI_FLASH "y"
+	run_host_command_logged scripts/config --set-val CONFIG_ENV_SECT_SIZE_AUTO "y"
+	run_host_command_logged scripts/config --set-val CONFIG_ENV_OVERWRITE "y"
+	run_host_command_logged scripts/config --set-val CONFIG_ENV_SIZE "0x20000"
+	run_host_command_logged scripts/config --set-val CONFIG_ENV_OFFSET "0xc00000"
+
+	display_alert "u-boot for ${BOARD}" "u-boot: enable preboot & flash user LED in preboot" "info"
+	run_host_command_logged scripts/config --enable CONFIG_USE_PREBOOT
+	run_host_command_logged scripts/config --set-str CONFIG_PREBOOT "'led user-led on; sleep 0.1; led user-led off'" # double quotes required due to run_host_command_logged's quirks
+
+	display_alert "u-boot for ${BOARD}" "u-boot: enable EFI debugging command" "info"
+	run_host_command_logged scripts/config --enable CMD_EFIDEBUG
+	run_host_command_logged scripts/config --enable CMD_NVEDIT_EFI
+
+	display_alert "u-boot for ${BOARD}" "u-boot: enable more compression support" "info"
+	run_host_command_logged scripts/config --enable CONFIG_LZO
+	run_host_command_logged scripts/config --enable CONFIG_BZIP2
+	run_host_command_logged scripts/config --enable CONFIG_ZSTD
+
+	display_alert "u-boot for ${BOARD}" "u-boot: enable gpio LED support" "info"
+	run_host_command_logged scripts/config --enable CONFIG_LED
+	run_host_command_logged scripts/config --enable CONFIG_LED_GPIO
+
+	display_alert "u-boot for ${BOARD}" "u-boot: enable networking cmds" "info"
+	run_host_command_logged scripts/config --enable CONFIG_CMD_NFS
+	run_host_command_logged scripts/config --enable CONFIG_CMD_WGET
+	run_host_command_logged scripts/config --enable CONFIG_CMD_DNS
+	run_host_command_logged scripts/config --enable CONFIG_PROT_TCP
+	run_host_command_logged scripts/config --enable CONFIG_PROT_TCP_SACK
+
+	# UMS, RockUSB, gadget stuff
+	declare -a enable_configs=("CONFIG_CMD_USB_MASS_STORAGE" "CONFIG_USB_GADGET" "USB_GADGET_DOWNLOAD" "CONFIG_USB_FUNCTION_ROCKUSB" "CONFIG_USB_FUNCTION_ACM" "CONFIG_CMD_ROCKUSB" "CONFIG_CMD_USB_MASS_STORAGE")
+	for config in "${enable_configs[@]}"; do
+		display_alert "u-boot for ${BOARD}/${BRANCH}" "u-boot: enable ${config}" "info"
+		run_host_command_logged scripts/config --enable "${config}"
+	done
+	# Auto-enabled by the above, force off...
+	run_host_command_logged scripts/config --disable USB_FUNCTION_FASTBOOT
+
+}
+
+# Include fw_setenv, configured to point to the correct spot on the SPI Flash
+PACKAGE_LIST_BOARD="libubootenv-tool" # libubootenv-tool provides fw_printenv and fw_setenv, for talking to U-Boot environment
+function post_family_tweaks__config_nanopct6_fwenv() {
+	[[ "${BRANCH}" != "edge" ]] && return 0
+	display_alert "Configuring fw_printenv and fw_setenv" "for ${BOARD} and u-boot ${BOOTBRANCH}" "info"
+	# Addresses below come from CONFIG_ENV_OFFSET and CONFIG_ENV_SIZE in defconfig
+	cat <<- 'FW_ENV_CONFIG' > "${SDCARD}"/etc/fw_env.config
+		# MTD/SPI u-boot env for the ${BOARD_NAME}
+		# MTD device name Device offset Env. size Flash sector size Number of sectors
+		/dev/mtd0         0xc00000      0x20000
+	FW_ENV_CONFIG
+}
diff --git a/config/boards/nanopim4v2.conf b/config/boards/nanopim4v2.conf
new file mode 100644
index 000000000000..949288283ee3
--- /dev/null
+++ b/config/boards/nanopim4v2.conf
@@ -0,0 +1,35 @@
+# Rockchip RK3399 hexa core 4GB RAM SoC GBE eMMC USB3 USB-C WiFi/BT
+BOARD_NAME="NanoPi M4V2"
+BOARDFAMILY="rockchip64" # Used to be rk3399
+BOARD_MAINTAINER="igorpecovnik"
+BOOTCONFIG="nanopi-m4v2-rk3399_defconfig"
+KERNEL_TARGET="current,edge"
+KERNEL_TEST_TARGET="current"
+FULL_DESKTOP="yes"
+ASOUND_STATE="asound.state.rt5651"
+BOOT_LOGO="desktop"
+
+function post_family_tweaks__m4v2() {
+	display_alert "$BOARD" "Installing board tweaks" "info"
+
+	# enable fan support
+	chroot $SDCARD /bin/bash -c "systemctl --no-reload enable nanopim4-pwm-fan.service >/dev/null 2>&1"
+
+	return 0
+}
+function post_family_tweaks_bsp__M4V2() {
+	display_alert "Installing BSP firmware and fixups"
+
+	# Bluetooth for most of others (custom patchram is needed only in legacy)
+	install -m 755 $SRC/packages/bsp/rk3399/brcm_patchram_plus_rk3399 $destination/usr/bin
+	cp $SRC/packages/bsp/rk3399/rk3399-bluetooth.service $destination/lib/systemd/system/
+
+	# Swap out the chip for some boards
+	sed -i s%BCM4345C5%BCM4356A2%g $destination/lib/systemd/system/rk3399-bluetooth.service
+
+	# Fan support
+	cp $SRC/packages/bsp/nanopim4/nanopim4-pwm-fan.service $destination/lib/systemd/system/
+	install -m 755 $SRC/packages/bsp/nanopim4/nanopim4-pwm-fan.sh $destination/usr/bin/nanopim4-pwm-fan.sh
+
+	return 0
+}
diff --git a/config/boards/odroidc4.conf b/config/boards/odroidc4.conf
new file mode 100644
index 000000000000..f244972e9037
--- /dev/null
+++ b/config/boards/odroidc4.conf
@@ -0,0 +1,11 @@
+# Amlogic S905X3 quad core 4GB RAM SoC eMMC GBE USB3 SPI
+BOARD_NAME="Odroid C4"
+BOARDFAMILY="meson-sm1"
+BOARD_MAINTAINER=""
+BOOTCONFIG="odroid-c4_defconfig"
+KERNEL_TARGET="current,edge"
+KERNEL_TEST_TARGET="current"
+MODULES_BLACKLIST="simpledrm" # SimpleDRM conflicts with Panfrost
+FULL_DESKTOP="yes"
+SERIALCON="ttyAML0"
+BOOT_LOGO="desktop"
diff --git a/config/boards/odroidhc4.conf b/config/boards/odroidhc4.conf
new file mode 100644
index 000000000000..3f492b964839
--- /dev/null
+++ b/config/boards/odroidhc4.conf
@@ -0,0 +1,112 @@
+# Amlogic S905X3 quad core 4GB RAM SoC GBE USB3 SPI 2 x SATA
+BOARD_NAME="Odroid HC4"
+BOARDFAMILY="meson-sm1"
+BOARD_MAINTAINER=""
+BOOTCONFIG="odroid-c4_defconfig" # for the SD card; but also 'odroid-hc4_defconfig', see below at pre_config_uboot_target
+KERNEL_TARGET="current,edge"
+KERNEL_TEST_TARGET="current"
+MODULES_BLACKLIST="simpledrm" # SimpleDRM conflicts with Panfrost
+FULL_DESKTOP="no"
+SERIALCON="ttyAML0"
+BOOT_FDT_FILE="amlogic/meson-sm1-odroid-hc4.dtb"
+PACKAGE_LIST_BOARD="lm-sensors fancontrol" # SPI, sensors, manual fan control via 'pwmconfig'
+
+# Newer u-boot for the HC4. There's patches in `board_odroidhc4` for the defconfigs used in the UBOOT_TARGET_MAP below.
+BOOTBRANCH_BOARD="tag:v2024.04"
+BOOTPATCHDIR="v2024.04"
+
+# We build u-boot twice: C4 config for SD cards, and HC4 (with SATA/PCI/SPI) config for SPI.
+UBOOT_TARGET_MAP="
+armbian_target=sd u-boot-dtb.img;;u-boot.bin.sd.bin:u-boot.bin u-boot-dtb.img
+armbian_target=spi u-boot-dtb.img;;u-boot.bin:u-boot-spi.bin
+"
+
+# The SPI version (u-boot-spi.bin, built from odroid-hc4_defconfig above) is then used by nand-sata-install / armbian-install
+function write_uboot_platform_mtd() {
+	declare -a extra_opts_flashcp=("--verbose")
+	if flashcp -h | grep -q -e '--partition'; then
+		echo "Confirmed flashcp supports --partition -- read and write only changed blocks." >&2
+		extra_opts_flashcp+=("--partition")
+	else
+		echo "flashcp does not support --partition, will write full SPI flash blocks." >&2
+	fi
+	flashcp "${extra_opts_flashcp[@]}" "${1}/u-boot-spi.bin" /dev/mtd0
+}
+
+# FIP blobs; the C4 & HC4 fip blobs are actually the same, still LE carries both.
+function post_uboot_custom_postprocess__odroid_hc4_uboot() {
+	display_alert "Signing u-boot FIP" "${BOARD}" "info"
+	uboot_g12_postprocess "${SRC}"/cache/sources/amlogic-boot-fip/odroid-hc4 g12a
+}
+
+# switch defconfig according to target, so we can still use the same post_config_uboot_target for both.
+function pre_config_uboot_target__odroidhc4_defconfig_per_target() {
+	case "${target_make}" in
+		"armbian_target=spi "*)
+			BOOTCONFIG="odroid-hc4_defconfig"
+			;;
+		"armbian_target=sd "*)
+			BOOTCONFIG="odroid-c4_defconfig"
+			;;
+		*)
+			exit_with_error "Unknown target_make: '${target_make}', unknown BOOTCONFIG."
+			;;
+	esac
+	display_alert "setting BOOTCONFIG for target" "${target_make}: '${BOOTCONFIG}'" "info"
+}
+
+# Enable extra u-boot .config options, this way we avoid patching defconfig
+function post_config_uboot_target__extra_configs_for_odroid_hc4() {
+	display_alert "u-boot for ${BOARD}" "u-boot: enable preboot & pci+usb start in preboot" "info"
+	run_host_command_logged scripts/config --enable CONFIG_USE_PREBOOT
+	run_host_command_logged scripts/config --set-str CONFIG_PREBOOT "'run boot_pci_enum; usb start'" # double quotes required due to run_host_command_logged's quirks
+
+	display_alert "u-boot for ${BOARD}" "u-boot: enable EFI debugging command" "info"
+	run_host_command_logged scripts/config --enable CMD_EFIDEBUG
+	run_host_command_logged scripts/config --enable CMD_NVEDIT_EFI
+
+	## WAIT ## display_alert "u-boot for ${BOARD}" "u-boot: disable EFI Video Framebuffer" "info"
+	## WAIT ## run_host_command_logged scripts/config --disable CONFIG_VIDEO_DT_SIMPLEFB # "Enables the code to pass the framebuffer to the kernel as a simple framebuffer in the device tree."
+	## WAIT ## # CONFIG_VIDEO_EFI is unrelated: its about _using_ an EFI framebuffer when booted by an EFI-capable bootloader earlier in the chain. Not about _providing_ an EFI framebuffer. That's simplefb.
+	## WAIT ## # CONFIG_FDT_SIMPLEFB seems to be rpi-specific and 100% unrelated here
+
+	display_alert "u-boot for ${BOARD}" "u-boot: enable I2C support" "info"
+	run_host_command_logged scripts/config --enable CONFIG_DM_I2C
+	run_host_command_logged scripts/config --enable CONFIG_SYS_I2C_MESON
+	run_host_command_logged scripts/config --enable CONFIG_CMD_I2C
+
+	display_alert "u-boot for ${BOARD}" "u-boot: enable more compression support" "info"
+	run_host_command_logged scripts/config --enable CONFIG_LZO
+	run_host_command_logged scripts/config --enable CONFIG_BZIP2
+	run_host_command_logged scripts/config --enable CONFIG_ZSTD
+
+	display_alert "u-boot for ${BOARD}" "u-boot: enable gpio LED support" "info"
+	run_host_command_logged scripts/config --enable CONFIG_LED
+	run_host_command_logged scripts/config --enable CONFIG_LED_GPIO
+
+	display_alert "u-boot for ${BOARD}" "u-boot: enable networking cmds" "info"
+	run_host_command_logged scripts/config --enable CONFIG_CMD_NFS
+	run_host_command_logged scripts/config --enable CONFIG_CMD_WGET
+	run_host_command_logged scripts/config --enable CONFIG_CMD_DNS
+	run_host_command_logged scripts/config --enable CONFIG_PROT_TCP
+	run_host_command_logged scripts/config --enable CONFIG_PROT_TCP_SACK
+}
+
+# @TODO: this is no longer needed in `edge` branch -- Neil has sent a patch with a trip for the cooling map in the DT - also doesn't hurt.
+function post_family_tweaks__config_odroidhc4_fancontrol() {
+	display_alert "Configuring fancontrol" "for Odroid HC4" "info"
+	cat <<- FANCONTROL > "${SDCARD}"/etc/fancontrol
+		# Default config for the Odroid HC4 -- adjust to your needs (MINTEMP=40)
+		INTERVAL=10
+		DEVPATH=hwmon0=devices/virtual/thermal/thermal_zone0 hwmon2=devices/platform/pwm-fan
+		DEVNAME=hwmon0=cpu_thermal hwmon2=pwmfan
+		FCTEMPS=hwmon2/pwm1=hwmon0/temp1_input
+		FCFANS= hwmon2/pwm1=hwmon2/fan1_input
+		MINTEMP=hwmon2/pwm1=40
+		MAXTEMP=hwmon2/pwm1=60
+		MINSTART=hwmon2/pwm1=150
+		MINSTOP=hwmon2/pwm1=30
+		MAXPWM=hwmon2/pwm1=180
+	FANCONTROL
+	chroot_sdcard systemctl enable fancontrol.service
+}
diff --git a/config/boards/pinebook-pro.csc b/config/boards/pinebook-pro.csc
new file mode 100644
index 000000000000..3a251f2bb839
--- /dev/null
+++ b/config/boards/pinebook-pro.csc
@@ -0,0 +1,42 @@
+# Rockchip RK3399 hexa core 2G/4GB SoC Laptop eMMC USB3 WiFi
+BOARD_NAME="Pinebook Pro"
+BOARDFAMILY="rockchip64"
+BOARD_MAINTAINER="TRSx80 ahoneybun"
+BOOTCONFIG="pinebook-pro-rk3399_defconfig"
+BOOT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb"
+KERNEL_TARGET="current,edge"
+KERNEL_TEST_TARGET="current"
+FULL_DESKTOP="yes"
+BOOT_LOGO="desktop"
+BOOT_SCENARIO="blobless"
+ASOUND_STATE="asound.state.pinebook-pro"
+BOOTBRANCH_BOARD="tag:v2022.04"
+BOOTPATCHDIR="u-boot-rockchip64-v2022.04"
+
+function post_family_tweaks__PBP() {
+	display_alert "$BOARD" "Installing board tweaks" "info"
+
+	chroot $SDCARD /bin/bash -c "echo SuspendState=freeze >> /etc/systemd/sleep.conf"
+	chroot $SDCARD /bin/bash -c "echo HandlePowerKey=ignore >> /etc/systemd/login.d"
+
+	return 0
+}
+
+function post_family_tweaks_bsp__PBP_BSP() {
+	display_alert "Installing BSP firmware and fixups"
+
+	# special keys
+	mkdir -p "${destination}"/etc/skel/.config/xfce4/xfconf/xfce-perchannel-xml/
+	cp $SRC/packages/bsp/pinebook-pro/pointers.xml "${destination}"/etc/skel/.config/xfce4/xfconf/xfce-perchannel-xml/
+
+	# touchpad and keyboard tweaks
+	mkdir -p "${destination}"/etc/X11/xorg.conf.d/
+	# from https://github.com/ayufan-rock64/linux-package/tree/master/root-pinebookpro
+	cp "${SRC}"/packages/bsp/pinebook-pro/40-pinebookpro-touchpad.conf "${destination}"/etc/X11/xorg.conf.d/
+
+	# keyboard hwdb
+	mkdir -p "${destination}"/etc/udev/hwdb.d/
+	cp "${SRC}"/packages/bsp/pinebook-pro/10-usb-kbd.hwdb "${destination}"/etc/udev/hwdb.d/
+
+	return 0
+}
diff --git a/config/boards/retro-lite-cm5.csc b/config/boards/retro-lite-cm5.csc
new file mode 100644
index 000000000000..6f2a1c66ba09
--- /dev/null
+++ b/config/boards/retro-lite-cm5.csc
@@ -0,0 +1,26 @@
+# Rockchip RK3588S octa core 4/8/16GB RAM SoC NVMe USB3 USB-C GbE
+BOARD_NAME="Retro Lite CM5"
+BOARDFAMILY="rockchip-rk3588"
+BOARD_MAINTAINER="ginkage"
+BOOT_SOC="rk3588"
+BOOTCONFIG="retro-lite-cm5-rk3588s_defconfig"
+KERNEL_TARGET="vendor"
+FULL_DESKTOP="yes"
+BOOT_LOGO="desktop"
+BOOT_FDT_FILE="rockchip/rk3588s-retro-lite-cm5.dtb"
+BOOT_SCENARIO="spl-blobs"
+IMAGE_PARTITION_TABLE="gpt"
+DDR_BLOB="rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin"
+BL31_BLOB="rk35/rk3588_bl31_v1.45.elf"
+
+function post_family_tweaks__retrolitecm5_naming_audios() {
+	display_alert "$BOARD" "Renaming Retro Lite CM5 audios" "info"
+
+	mkdir -p $SDCARD/etc/udev/rules.d/
+	echo 'SUBSYSTEM=="sound", ENV{ID_PATH}=="platform-hdmi0-sound", ENV{SOUND_DESCRIPTION}="HDMI0 Audio"' > $SDCARD/etc/udev/rules.d/90-naming-audios.rules
+	echo 'SUBSYSTEM=="sound", ENV{ID_PATH}=="platform-dp0-sound", ENV{SOUND_DESCRIPTION}="DP0 Audio"' >> $SDCARD/etc/udev/rules.d/90-naming-audios.rules
+	echo 'SUBSYSTEM=="sound", ENV{ID_PATH}=="platform-wm8960-sound", ENV{SOUND_DESCRIPTION}="WM8960 Audio"' >> $SDCARD/etc/udev/rules.d/90-naming-audios.rules
+
+	return 0
+}
+
diff --git a/config/boards/rk3328-heltec.csc b/config/boards/rk3328-heltec.csc
new file mode 100644
index 000000000000..b317a864a373
--- /dev/null
+++ b/config/boards/rk3328-heltec.csc
@@ -0,0 +1,13 @@
+# Rockchip RK3328 quad core 2GB RAM SoC WIFI/BT eMMC
+BOARD_NAME="RK3328-Heltec"
+BOARDFAMILY="rockchip64"
+BOARD_MAINTAINER="sicXnull"
+BOOTCONFIG="evb-rk3328_defconfig"
+KERNEL_TARGET="current,edge"
+KERNEL_TEST_TARGET="current"
+FULL_DESKTOP="yes"
+BOOT_LOGO="desktop"
+BOOT_FDT_FILE="rockchip/rk3328-heltec.dtb"
+IMAGE_PARTITION_TABLE="gpt"
+BOOT_SCENARIO="spl-blobs"
+BOOTFS_TYPE="fat"
diff --git a/config/boards/rock-3a.conf b/config/boards/rock-3a.conf
new file mode 100644
index 000000000000..eff0a0747012
--- /dev/null
+++ b/config/boards/rock-3a.conf
@@ -0,0 +1,15 @@
+# Rockchip RK3568 quad core 1-8GB SoC GBe eMMC USB3
+BOARD_NAME="Rock 3A"
+BOARDFAMILY="rk35xx"
+BOARD_MAINTAINER="amazingfate ZazaBR vamzii catalinii"
+BOOTCONFIG="rock-3a-rk3568_defconfig"
+KERNEL_TARGET="edge,current,vendor"
+KERNEL_TEST_TARGET="current"
+FULL_DESKTOP="yes"
+BOOT_LOGO="desktop"
+BOOT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
+BOOT_SCENARIO="spl-blobs"
+BOOT_SUPPORT_SPI="yes"
+BOOT_SPI_RKSPI_LOADER="yes"
+IMAGE_PARTITION_TABLE="gpt"
+BOOTFS_TYPE="fat"
diff --git a/config/boards/rockpro64.csc b/config/boards/rockpro64.csc
new file mode 100644
index 000000000000..0069befa4cdf
--- /dev/null
+++ b/config/boards/rockpro64.csc
@@ -0,0 +1,78 @@
+# Rockchip RK3399 hexa core 2G/4GB SoC GBe eMMC USB3 WiFi
+BOARD_NAME="RockPro 64"
+BOARDFAMILY="rockchip64"
+BOARD_MAINTAINER="joekhoobyar"
+BOOTCONFIG="rockpro64-rk3399_defconfig"
+KERNEL_TARGET="current,edge"
+KERNEL_TEST_TARGET="current"
+FULL_DESKTOP="yes"
+BOOT_LOGO="desktop"
+BOOT_SCENARIO="blobless"
+BOOT_SUPPORT_SPI=yes
+
+# u-boot v2024.04-rc4 for rockpro64
+BOOTBRANCH_BOARD="tag:v2024.04-rc4"
+BOOTPATCHDIR="v2024.04"
+
+# Include fw_setenv, configured to point to the correct spot on the SPI Flash
+PACKAGE_LIST_BOARD="libubootenv-tool" # libubootenv-tool provides fw_printenv and fw_setenv, for talking to U-Boot environment
+
+function post_family_config__use_mainline_uboot_rockpro64() {
+	# Use latest lts 2.8 ATF
+	ATFBRANCH='tag:lts-v2.8.16'
+	ATFPATCHDIR="atf-rockchip64" # patches for logging etc
+	display_alert "$BOARD" "using ATF (blobless) ${ATFBRANCH} for ${BOOTBRANCH_BOARD} u-boot" "info"
+	# bl31.elf is copied directly from ATF build dir to uboot dir (by armbian u-boot build system)
+	UBOOT_TARGET_MAP="BL31=bl31.elf;;u-boot-rockchip.bin u-boot-rockchip-spi.bin"
+
+	# Ignore most of the rockchip64_common stuff, we're using binman here which does all the work already
+	unset uboot_custom_postprocess write_uboot_platform write_uboot_platform_mtd
+
+	function write_uboot_platform() {
+		dd "if=$1/u-boot-rockchip.bin" "of=$2" bs=32k seek=1 conv=notrunc status=none
+	}
+
+	function write_uboot_platform_mtd() {
+		flashcp -v -p "$1/u-boot-rockchip-spi.bin" /dev/mtd0
+	}
+}
+
+# From Kwiboo:
+#  ... "note that u-boot mainline for rk3328/rk3399 suffers from a limitation in that the u-boot.bin may not exceed 1000 KiB or the stack may overwrite part of it during runtime, resulting in strange unexplained issues.
+#       This has been fixed in current U-Boot next branch with https://github.com/u-boot/u-boot/commit/5e7cd8a119953dc2f466fea81e230d683ee03493 and should be included with v2024.07-rc1
+#       If your u-boot.bin build output is less than 950 KiB in size you should not suffer from this limitation/issue."
+#  ... "The real limit will be at most 1 MiB - 16 KiB (malloc heap on stack) = 1008 KiB and any additional runtime usage of the stack will take up until U-Boot has been relocated to top of RAM,
+#       lets say an additional 16 KiB (same as malloc heap) to be on the safer side, so I would suggest you check for e.g. < 992 KiB or similar instead of < 1 MiB.
+#       As long as the generated u-boot.bin is < 992 KiB I think it should be safe, and I do not think the stack usage will be that much before relocation so < 1000 KiB may also be fine 😎"
+# rpardini: close call; the u-boot.bin is 994920 bytes. Let's check for >992KiB and break the build if it's too large.
+function post_uboot_custom_postprocess__check_bin_size_less_than_992KiB() {
+	declare one_bin
+	declare -i uboot_bin_size
+	declare -a bins_to_check=("u-boot.bin")
+	for one_bin in "${bins_to_check[@]}"; do
+		uboot_bin_size=$(stat -c %s "${one_bin}")
+		display_alert "Checking u-boot ${BOARD} bin size" "'${one_bin}' is less than 992KiB (1015808 bytes): ${uboot_bin_size} bytes" "info"
+		if [[ ${uboot_bin_size} -ge 1015808 ]]; then
+			display_alert "u-boot for ${BOARD}" "'${one_bin}' is larger than 992KiB (1015808 bytes): ${uboot_bin_size} bytes" "err"
+			exit_with_error "u-boot ${BOARD} bin size check failed"
+		fi
+	done
+}
+
+function post_config_uboot_target__extra_configs_for_rockpro64() {
+	# Taken from https://gitlab.manjaro.org/manjaro-arm/packages/core/uboot-rockpro64/-/blob/master/PKGBUILD
+	display_alert "$BOARD" "u-boot configs for ${BOOTBRANCH_BOARD} u-boot config" "info"
+	run_host_command_logged scripts/config --set-val CONFIG_OF_LIBFDT_OVERLAY "y"
+	run_host_command_logged scripts/config --set-val CONFIG_MMC_HS400_SUPPORT "y"
+	run_host_command_logged scripts/config --set-val CONFIG_USE_PREBOOT "n"
+}
+
+function post_family_tweaks__config_rockpro64_fwenv() {
+	display_alert "Configuring fw_printenv and fw_setenv" "for ${BOARD} and u-boot ${BOOTBRANCH_BOARD}" "info"
+	# Addresses below come from CONFIG_ENV_OFFSET and CONFIG_ENV_SIZE in https://github.com/u-boot/u-boot/blob/v2024.04-rc4/configs/rockpro64-rk3399_defconfig
+	cat <<- 'FW_ENV_CONFIG' > "${SDCARD}"/etc/fw_env.config
+		# MTD on the SPI for the Rockpro64
+		# MTD device name Device offset Env. size Flash sector size Number of sectors
+		/dev/mtd0                       0x3F8000                      0x8000
+	FW_ENV_CONFIG
+}
diff --git a/config/boards/x96q.tvb b/config/boards/x96q.tvb
new file mode 100644
index 000000000000..5a4667cd2adb
--- /dev/null
+++ b/config/boards/x96q.tvb
@@ -0,0 +1,11 @@
+# Allwinner H313 TVBox with 2GB of RAM and EMMC
+BOARD_NAME="X96Q TV Box"
+BOARDFAMILY="sun50iw9"
+BOARD_MAINTAINER="sicXnull"
+BOOTCONFIG="x96q_lpddr3_defconfig"
+BOOT_LOGO="desktop"
+KERNEL_TARGET="current"
+KERNEL_TEST_TARGET="current"
+FORCE_BOOTSCRIPT_UPDATE="yes"
+OVERLAY_PREFIX="sun50i-h616"
+enable_extension "uwe5622-allwinner"
diff --git a/config/boards/youyeetoo-r1-v3.wip b/config/boards/youyeetoo-r1-v3.wip
new file mode 100644
index 000000000000..8420072da81d
--- /dev/null
+++ b/config/boards/youyeetoo-r1-v3.wip
@@ -0,0 +1,53 @@
+# Rockchip RK3588S octa core 32GB RAM SoC eMMC NvME 1x USB3 3x USB2 1x GbE
+BOARD_NAME="Youyeetoo R1 v3"
+BOARDFAMILY="rockchip-rk3588"
+BOARD_MAINTAINER="superkali"
+BOOTCONFIG="generic-rk3588_defconfig" # vendor name, not standard, see hook below, set BOOT_SOC below to compensate
+BOOT_SOC="rk3588"
+KERNEL_TARGET="vendor"
+FULL_DESKTOP="yes"
+BOOT_LOGO="desktop"
+IMAGE_PARTITION_TABLE="gpt"
+BOOT_FDT_FILE="rockchip/rk3588s-youyeetoo-r1.dtb"
+BOOT_SCENARIO="spl-blobs"
+
+function post_family_tweaks__youyeetoo_r1_naming_audios() {
+	display_alert "$BOARD" "Renaming Youyeetoo R1 audios" "info"
+
+	mkdir -p $SDCARD/etc/udev/rules.d/
+	echo 'SUBSYSTEM=="sound", ENV{ID_PATH}=="platform-hdmi0-sound", ENV{SOUND_DESCRIPTION}="HDMI0 Audio"' > $SDCARD/etc/udev/rules.d/90-naming-audios.rules
+	echo 'SUBSYSTEM=="sound", ENV{ID_PATH}=="platform-es8388-sound", ENV{SOUND_DESCRIPTION}="ES8388 Audio"' >> $SDCARD/etc/udev/rules.d/90-naming-audios.rules
+
+	return 0
+}
+
+function post_family_tweaks__youyeetoo_r1_naming_udev_network_interfaces() {
+	display_alert "$BOARD" "Renaming Youyeetoo R1 network interfaces to eth0" "info"
+
+	mkdir -p $SDCARD/etc/udev/rules.d/
+	cat <<- EOF > "${SDCARD}/etc/udev/rules.d/70-persistent-net.rules"
+		SUBSYSTEM=="net", ACTION=="add", DRIVERS=="?*", KERNELS=="fe1c0000.ethernet", NAME:="eth0"
+	EOF
+}
+
+# Mainline U-Boot
+function post_family_config__youyeetoo_r1_use_mainline_uboot() {
+	display_alert "$BOARD" "Using mainline U-Boot for $BOARD / $BRANCH" "info"
+
+	declare -g BOOTCONFIG="generic-rk3588_defconfig"             # Use generic defconfig which should boot all RK3588 boards
+	declare -g BOOTDELAY=1                                       # Wait for UART interrupt to enter UMS/RockUSB mode etc
+	declare -g BOOTSOURCE="https://github.com/u-boot/u-boot.git" # We ❤️ Mainline U-Boot
+	declare -g BOOTBRANCH="tag:v2024.07"
+	declare -g BOOTPATCHDIR="v2024.07"
+	# Don't set BOOTDIR, allow shared U-Boot source directory for disk space efficiency
+
+	declare -g UBOOT_TARGET_MAP="BL31=${RKBIN_DIR}/${BL31_BLOB} ROCKCHIP_TPL=${RKBIN_DIR}/${DDR_BLOB};;u-boot-rockchip.bin"
+
+	# Disable stuff from rockchip64_common; we're using binman here which does all the work already
+	unset uboot_custom_postprocess write_uboot_platform write_uboot_platform_mtd
+
+	# Just use the binman-provided u-boot-rockchip.bin, which is ready-to-go
+	function write_uboot_platform() {
+		dd "if=$1/u-boot-rockchip.bin" "of=$2" bs=32k seek=1 conv=notrunc status=none
+	}
+}
diff --git a/config/bootenv/rk356x.txt b/config/bootenv/rk356x.txt
new file mode 100644
index 000000000000..472418799e60
--- /dev/null
+++ b/config/bootenv/rk356x.txt
@@ -0,0 +1,4 @@
+verbosity=1
+bootlogo=false
+console=both
+extraargs=cma=256M
diff --git a/config/kernel/linux-rockchip-rk3588-6.11.config b/config/kernel/linux-rockchip-rk3588-6.11.config
new file mode 100644
index 000000000000..94c6c5a44077
--- /dev/null
+++ b/config/kernel/linux-rockchip-rk3588-6.11.config
@@ -0,0 +1,11042 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm64 6.11.0-rc4 Kernel Configuration
+#
+CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 13.2.0-23ubuntu4) 13.2.0"
+CONFIG_CC_IS_GCC=y
+CONFIG_GCC_VERSION=130200
+CONFIG_CLANG_VERSION=0
+CONFIG_AS_IS_GNU=y
+CONFIG_AS_VERSION=24200
+CONFIG_LD_IS_BFD=y
+CONFIG_LD_VERSION=24200
+CONFIG_LLD_VERSION=0
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_BROKEN=y
+CONFIG_CC_HAS_ASM_INLINE=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_PAHOLE_VERSION=125
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_TABLE_SORT=y
+CONFIG_THREAD_INFO_IN_TASK=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_COMPILE_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_BUILD_SALT=""
+CONFIG_DEFAULT_INIT=""
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_WATCH_QUEUE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_USELIB=y
+CONFIG_AUDIT=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_INJECTION=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_SIM=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+# end of IRQ subsystem
+
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_TIME_KUNIT_TEST=m
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ_FULL is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+# end of Timers subsystem
+
+CONFIG_BPF=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
+
+#
+# BPF subsystem
+#
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF_JIT=y
+# CONFIG_BPF_JIT_ALWAYS_ON is not set
+CONFIG_BPF_JIT_DEFAULT_ON=y
+# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
+# CONFIG_BPF_PRELOAD is not set
+CONFIG_BPF_LSM=y
+# end of BPF subsystem
+
+CONFIG_PREEMPT_BUILD=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPTION=y
+# CONFIG_PREEMPT_DYNAMIC is not set
+CONFIG_SCHED_CORE=y
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_SCHED_AVG_IRQ=y
+CONFIG_SCHED_HW_PRESSURE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+# CONFIG_PSI is not set
+# end of CPU/Task time and stats accounting
+
+CONFIG_CPU_ISOLATION=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+CONFIG_PREEMPT_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_TREE_SRCU=y
+CONFIG_TASKS_RCU_GENERIC=y
+CONFIG_NEED_TASKS_RCU=y
+CONFIG_TASKS_RCU=y
+CONFIG_TASKS_TRACE_RCU=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RCU_NEED_SEGCBLIST=y
+# end of RCU Subsystem
+
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKHEADERS=m
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+# CONFIG_PRINTK_INDEX is not set
+CONFIG_GENERIC_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# CONFIG_UCLAMP_TASK is not set
+# end of Scheduler features
+
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_NO_STRINGOP_OVERFLOW=y
+CONFIG_CC_NO_STRINGOP_OVERFLOW=y
+CONFIG_ARCH_SUPPORTS_INT128=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+CONFIG_SLAB_OBJ_EXT=y
+CONFIG_CGROUPS=y
+CONFIG_PAGE_COUNTER=y
+# CONFIG_CGROUP_FAVOR_DYNMODS is not set
+CONFIG_MEMCG=y
+# CONFIG_MEMCG_V1 is not set
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_SCHED_MM_CID=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_MISC=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_TIME_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_ZSTD=y
+CONFIG_BOOT_CONFIG=y
+# CONFIG_BOOT_CONFIG_FORCE is not set
+# CONFIG_BOOT_CONFIG_EMBED is not set
+CONFIG_INITRAMFS_PRESERVE_MTIME=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
+CONFIG_SYSCTL=y
+CONFIG_HAVE_UID16=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_MULTIUSER=y
+# CONFIG_SGETMASK_SYSCALL is not set
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_SMALL is not set
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_IO_URING=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_MEMBARRIER=y
+CONFIG_KCMP=y
+CONFIG_RSEQ=y
+# CONFIG_DEBUG_RSEQ is not set
+CONFIG_CACHESTAT_SYSCALL=y
+# CONFIG_PC104 is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_SELFTEST is not set
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_GUEST_PERF_EVENTS=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# end of Kernel Performance Events And Counters
+
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+
+#
+# Kexec and crash features
+#
+CONFIG_KEXEC_CORE=y
+CONFIG_HAVE_IMA_KEXEC=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
+# CONFIG_KEXEC_SIG is not set
+# CONFIG_CRASH_DUMP is not set
+# end of Kexec and crash features
+# end of General setup
+
+CONFIG_ARM64=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_64BIT=y
+CONFIG_MMU=y
+CONFIG_ARM64_CONT_PTE_SHIFT=4
+CONFIG_ARM64_CONT_PMD_SHIFT=4
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_SMP=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
+
+#
+# Platform selection
+#
+# CONFIG_ARCH_ACTIONS is not set
+# CONFIG_ARCH_AIROHA is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_ALPINE is not set
+# CONFIG_ARCH_APPLE is not set
+# CONFIG_ARCH_BCM is not set
+# CONFIG_ARCH_BERLIN is not set
+# CONFIG_ARCH_BITMAIN is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SPARX5 is not set
+# CONFIG_ARCH_K3 is not set
+# CONFIG_ARCH_LG1K is not set
+# CONFIG_ARCH_HISI is not set
+# CONFIG_ARCH_KEEMBAY is not set
+# CONFIG_ARCH_MEDIATEK is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_ARCH_NXP is not set
+# CONFIG_ARCH_MA35 is not set
+# CONFIG_ARCH_NPCM is not set
+# CONFIG_ARCH_PENSANDO is not set
+# CONFIG_ARCH_QCOM is not set
+# CONFIG_ARCH_REALTEK is not set
+# CONFIG_ARCH_RENESAS is not set
+CONFIG_ARCH_ROCKCHIP=y
+# CONFIG_ARCH_SEATTLE is not set
+# CONFIG_ARCH_INTEL_SOCFPGA is not set
+# CONFIG_ARCH_STM32 is not set
+# CONFIG_ARCH_SYNQUACER is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_SPRD is not set
+# CONFIG_ARCH_THUNDER is not set
+# CONFIG_ARCH_THUNDER2 is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VISCONTI is not set
+# CONFIG_ARCH_XGENE is not set
+# CONFIG_ARCH_ZYNQMP is not set
+# end of Platform selection
+
+#
+# Kernel Features
+#
+
+#
+# ARM errata workarounds via the alternatives framework
+#
+CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_834220=y
+CONFIG_ARM64_ERRATUM_1742098=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1418040=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1319367=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_ERRATUM_2441007=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1463225=y
+CONFIG_ARM64_ERRATUM_1542419=y
+CONFIG_ARM64_ERRATUM_1508412=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2441009=y
+CONFIG_ARM64_ERRATUM_2457168=y
+CONFIG_ARM64_ERRATUM_2645198=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
+CONFIG_ARM64_ERRATUM_2966298=y
+CONFIG_ARM64_ERRATUM_3117295=y
+CONFIG_ARM64_ERRATUM_3194386=y
+CONFIG_CAVIUM_ERRATUM_22375=y
+CONFIG_CAVIUM_ERRATUM_23144=y
+CONFIG_CAVIUM_ERRATUM_23154=y
+CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CAVIUM_ERRATUM_30115=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_FUJITSU_ERRATUM_010001=y
+CONFIG_HISILICON_ERRATUM_161600802=y
+CONFIG_QCOM_FALKOR_ERRATUM_1003=y
+CONFIG_QCOM_FALKOR_ERRATUM_1009=y
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
+CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
+CONFIG_ROCKCHIP_ERRATUM_3588001=y
+CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
+# end of ARM errata workarounds via the alternatives framework
+
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_16K_PAGES is not set
+# CONFIG_ARM64_64K_PAGES is not set
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+# CONFIG_ARM64_VA_BITS_52 is not set
+CONFIG_ARM64_VA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PA_BITS=48
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_CLUSTER=y
+CONFIG_SCHED_SMT=y
+CONFIG_NR_CPUS=256
+CONFIG_HOTPLUG_CPU=y
+CONFIG_NUMA=y
+CONFIG_NODES_SHIFT=4
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_250 is not set
+CONFIG_HZ_300=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=300
+CONFIG_SCHED_HRTICK=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_PARAVIRT=y
+CONFIG_PARAVIRT_TIME_ACCOUNTING=y
+CONFIG_ARCH_SUPPORTS_KEXEC=y
+CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y
+CONFIG_ARCH_SELECTS_KEXEC_FILE=y
+CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y
+CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y
+CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
+CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
+CONFIG_TRANS_TABLE=y
+CONFIG_XEN_DOM0=y
+CONFIG_XEN=y
+CONFIG_ARCH_FORCE_MAX_ORDER=10
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_COMPAT=y
+CONFIG_KUSER_HELPERS=y
+CONFIG_COMPAT_ALIGNMENT_FIXUPS=y
+CONFIG_ARMV8_DEPRECATED=y
+CONFIG_SWP_EMULATION=y
+CONFIG_CP15_BARRIER_EMULATION=y
+CONFIG_SETEND_EMULATION=y
+
+#
+# ARMv8.1 architectural features
+#
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_PAN=y
+CONFIG_AS_HAS_LSE_ATOMICS=y
+CONFIG_ARM64_LSE_ATOMICS=y
+CONFIG_ARM64_USE_LSE_ATOMICS=y
+# end of ARMv8.1 architectural features
+
+#
+# ARMv8.2 architectural features
+#
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_SHA3=y
+# CONFIG_ARM64_PMEM is not set
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_CNP=y
+# end of ARMv8.2 architectural features
+
+#
+# ARMv8.3 architectural features
+#
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
+CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
+CONFIG_AS_HAS_ARMV8_3=y
+CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
+CONFIG_AS_HAS_LDAPR=y
+# end of ARMv8.3 architectural features
+
+#
+# ARMv8.4 architectural features
+#
+CONFIG_ARM64_AMU_EXTN=y
+CONFIG_AS_HAS_ARMV8_4=y
+CONFIG_ARM64_TLB_RANGE=y
+# end of ARMv8.4 architectural features
+
+#
+# ARMv8.5 architectural features
+#
+CONFIG_AS_HAS_ARMV8_5=y
+CONFIG_ARM64_BTI=y
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
+CONFIG_ARM64_E0PD=y
+CONFIG_ARM64_AS_HAS_MTE=y
+CONFIG_ARM64_MTE=y
+# end of ARMv8.5 architectural features
+
+#
+# ARMv8.7 architectural features
+#
+CONFIG_ARM64_EPAN=y
+# end of ARMv8.7 architectural features
+
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_PSEUDO_NMI=y
+# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
+CONFIG_RELOCATABLE=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_ARM64_CONTPTE=y
+# end of Kernel Features
+
+#
+# Boot options
+#
+# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set
+CONFIG_CMDLINE=""
+CONFIG_EFI_STUB=y
+CONFIG_EFI=y
+# CONFIG_COMPRESSED_INSTALL is not set
+CONFIG_DMI=y
+# end of Boot options
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_SUSPEND_SKIP_SYNC is not set
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HIBERNATION_COMP_LZO=y
+# CONFIG_HIBERNATION_COMP_LZ4 is not set
+CONFIG_HIBERNATION_DEF_COMP="lzo"
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+# CONFIG_PM_AUTOSLEEP is not set
+# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
+# CONFIG_PM_WAKELOCKS is not set
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_CPU_PM=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# end of Power management options
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Idle
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_GOV_TEO=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DT_IDLE_GENPD=y
+
+#
+# ARM CPU Idle Drivers
+#
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+# end of ARM CPU Idle Drivers
+# end of CPU Idle
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+
+#
+# CPU frequency scaling drivers
+#
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+# CONFIG_ARM_SCMI_CPUFREQ is not set
+# CONFIG_ACPI_CPPC_CPUFREQ is not set
+# end of CPU Frequency scaling
+# end of CPU Power Management
+
+CONFIG_ARCH_SUPPORTS_ACPI=y
+CONFIG_ACPI=y
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_CCA_REQUIRED=y
+CONFIG_ACPI_TABLE_LIB=y
+CONFIG_ACPI_THERMAL_LIB=y
+# CONFIG_ACPI_DEBUGGER is not set
+CONFIG_ACPI_SPCR_TABLE=y
+# CONFIG_ACPI_FPDT is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_AC=m
+CONFIG_ACPI_BATTERY=m
+CONFIG_ACPI_BUTTON=m
+# CONFIG_ACPI_TINY_POWER_BUTTON is not set
+CONFIG_ACPI_VIDEO=m
+CONFIG_ACPI_FAN=m
+# CONFIG_ACPI_TAD is not set
+CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_MCFG=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_IPMI=m
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_THERMAL=m
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+# CONFIG_ACPI_DEBUG is not set
+CONFIG_ACPI_PCI_SLOT=y
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_HED=y
+# CONFIG_ACPI_BGRT is not set
+CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
+CONFIG_ACPI_NHLT=y
+CONFIG_ACPI_NUMA=y
+CONFIG_ACPI_HMAT=y
+CONFIG_HAVE_ACPI_APEI=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+# CONFIG_ACPI_APEI_PCIEAER is not set
+CONFIG_ACPI_APEI_SEA=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_EINJ=y
+CONFIG_ACPI_APEI_EINJ_CXL=y
+# CONFIG_ACPI_APEI_ERST_DEBUG is not set
+CONFIG_ACPI_WATCHDOG=y
+CONFIG_ACPI_CONFIGFS=m
+# CONFIG_ACPI_PFRUT is not set
+CONFIG_ACPI_IORT=y
+CONFIG_ACPI_GTDT=y
+# CONFIG_ACPI_AGDI is not set
+CONFIG_ACPI_APMT=y
+CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PCC=y
+# CONFIG_ACPI_FFH is not set
+CONFIG_PMIC_OPREGION=y
+CONFIG_ACPI_VIOT=y
+CONFIG_ACPI_PRMT=y
+CONFIG_KVM_COMMON=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
+CONFIG_HAVE_KVM_DIRTY_RING=y
+CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y
+CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y
+CONFIG_KVM_MMIO=y
+CONFIG_HAVE_KVM_MSI=y
+CONFIG_HAVE_KVM_READONLY_MEM=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_KVM_VFIO=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_HAVE_KVM_IRQ_BYPASS=y
+CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
+CONFIG_KVM_GENERIC_MMU_NOTIFIER=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+# CONFIG_NVHE_EL2_DEBUG is not set
+CONFIG_CPU_MITIGATIONS=y
+
+#
+# General architecture-dependent options
+#
+CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_STATIC_KEYS_SELFTEST is not set
+CONFIG_UPROBES=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
+CONFIG_HAVE_NMI=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_KEEPINITRD=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_RUST=y
+CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_PERF_EVENTS_NMI=y
+CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
+CONFIG_HAVE_CMPXCHG_LOCAL=y
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SECCOMP_CACHE_DEBUG is not set
+CONFIG_HAVE_ARCH_STACKLEAK=y
+CONFIG_HAVE_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
+# CONFIG_SHADOW_CALL_STACK is not set
+CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
+CONFIG_LTO_NONE=y
+CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
+CONFIG_HAVE_CONTEXT_TRACKING_USER=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOVE_PUD=y
+CONFIG_HAVE_MOVE_PMD=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
+CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_ARCH_WANT_PMD_MKWRITE=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_ARCH_WANTS_EXECMEM_LATE=y
+CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_HAVE_PAGE_SIZE_4KB=y
+CONFIG_PAGE_SIZE_4KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SHIFT=12
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_HAVE_ARCH_VMAP_STACK=y
+CONFIG_VMAP_STACK=y
+CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_HAVE_ARCH_COMPILER_H=y
+CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+# CONFIG_LOCK_EVENT_COUNTS is not set
+CONFIG_ARCH_HAS_RELR=y
+CONFIG_HAVE_PREEMPT_DYNAMIC=y
+CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
+CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y
+CONFIG_ARCH_HAS_HW_PTE_YOUNG=y
+CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# end of GCOV-based kernel profiling
+
+CONFIG_HAVE_GCC_PLUGINS=y
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FUNCTION_ALIGNMENT=4
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_MODULES=y
+# CONFIG_MODULE_DEBUG is not set
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
+CONFIG_MODVERSIONS=y
+CONFIG_ASM_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_MODULE_SIG is not set
+CONFIG_MODULE_COMPRESS_NONE=y
+# CONFIG_MODULE_COMPRESS_GZIP is not set
+# CONFIG_MODULE_COMPRESS_XZ is not set
+# CONFIG_MODULE_COMPRESS_ZSTD is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+CONFIG_MODPROBE_PATH="/sbin/modprobe"
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_CGROUP_PUNT_BIO=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_ICQ=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_WRITE_MOUNTED=y
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_WBT=y
+CONFIG_BLK_WBT_MQ=y
+CONFIG_BLK_CGROUP_IOLATENCY=y
+# CONFIG_BLK_CGROUP_FC_APPID is not set
+# CONFIG_BLK_CGROUP_IOCOST is not set
+# CONFIG_BLK_CGROUP_IOPRIO is not set
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_SED_OPAL=y
+# CONFIG_BLK_INLINE_ENCRYPTION is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_AIX_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_CMDLINE_PARTITION=y
+# end of Partition Types
+
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BLK_MQ_STACKING=y
+
+#
+# IO Schedulers
+#
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_IOSCHED_BFQ=y
+CONFIG_BFQ_GROUP_IOSCHED=y
+# CONFIG_BFQ_CGROUP_DEBUG is not set
+# end of IO Schedulers
+
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PADATA=y
+CONFIG_ASN1=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
+CONFIG_FREEZER=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_HAVE_ELF_PROT=y
+CONFIG_ARCH_USE_GNU_PROPERTY=y
+CONFIG_ELFCORE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_BINFMT_MISC=m
+CONFIG_COREDUMP=y
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_ZPOOL=y
+CONFIG_SWAP=y
+CONFIG_ZSWAP=y
+CONFIG_ZSWAP_DEFAULT_ON=y
+# CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD is not set
+CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD=y
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
+CONFIG_ZSWAP_ZPOOL_DEFAULT="z3fold"
+CONFIG_ZBUD=y
+CONFIG_Z3FOLD=y
+CONFIG_HAVE_ZSMALLOC=y
+CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC_STAT is not set
+CONFIG_ZSMALLOC_CHAIN_SIZE=8
+
+#
+# Slab allocator options
+#
+CONFIG_SLUB=y
+# CONFIG_SLUB_TINY is not set
+CONFIG_SLAB_MERGE_DEFAULT=y
+CONFIG_SLAB_FREELIST_RANDOM=y
+# CONFIG_SLAB_FREELIST_HARDENED is not set
+# CONFIG_SLAB_BUCKETS is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_SLUB_CPU_PARTIAL=y
+# CONFIG_RANDOM_KMALLOC_CACHES is not set
+# end of Slab allocator options
+
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_HAVE_GUP_FAST=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+# CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_COMPACTION=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_PAGE_REPORTING=y
+CONFIG_MIGRATION=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_ARCH_ENABLE_THP_MIGRATION=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_PCP_BATCH_SCALE_MAX=5
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_MMU_NOTIFIER=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_MEMORY_FAILURE=y
+# CONFIG_HWPOISON_INJECT is not set
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
+CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
+# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set
+CONFIG_THP_SWAP=y
+# CONFIG_READ_ONLY_THP_FOR_FS is not set
+CONFIG_PGTABLE_HAS_HUGE_LEAVES=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_CMA=y
+# CONFIG_CMA_DEBUGFS is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMA_AREAS=7
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
+CONFIG_PAGE_IDLE_FLAG=y
+CONFIG_IDLE_PAGE_TRACKING=y
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
+CONFIG_ARCH_HAS_PTE_DEVMAP=y
+CONFIG_ARCH_HAS_ZONE_DMA_SET=y
+CONFIG_ZONE_DMA=y
+CONFIG_ZONE_DMA32=y
+CONFIG_GET_FREE_REGION=y
+CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
+CONFIG_ARCH_USES_PG_ARCH_X=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PERCPU_STATS=y
+# CONFIG_GUP_TEST is not set
+# CONFIG_DMAPOOL_TEST is not set
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
+CONFIG_MAPPING_DIRTY_HELPERS=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_SECRETMEM=y
+# CONFIG_ANON_VMA_NAME is not set
+# CONFIG_USERFAULTFD is not set
+CONFIG_LRU_GEN=y
+# CONFIG_LRU_GEN_ENABLED is not set
+# CONFIG_LRU_GEN_STATS is not set
+CONFIG_LRU_GEN_WALKS_MMU=y
+CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_LOCK_MM_AND_FIND_VMA=y
+CONFIG_IOMMU_MM_DATA=y
+CONFIG_EXECMEM=y
+
+#
+# Data Access Monitoring
+#
+# CONFIG_DAMON is not set
+# end of Data Access Monitoring
+# end of Memory Management options
+
+CONFIG_NET=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NET_REDIRECT=y
+CONFIG_SKB_DECRYPTED=y
+CONFIG_SKB_EXTENSIONS=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
+CONFIG_UNIX=y
+CONFIG_AF_UNIX_OOB=y
+CONFIG_UNIX_DIAG=m
+CONFIG_TLS=m
+CONFIG_TLS_DEVICE=y
+# CONFIG_TLS_TOE is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_OFFLOAD=y
+CONFIG_XFRM_ALGO=m
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_INTERFACE=m
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_XFRM_AH=m
+CONFIG_XFRM_ESP=m
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_XDP_SOCKETS=y
+# CONFIG_XDP_SOCKETS_DIAG is not set
+CONFIG_NET_HANDSHAKE=y
+# CONFIG_NET_HANDSHAKE_KUNIT_TEST is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IP_TUNNEL=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE_COMMON=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
+CONFIG_NET_UDP_TUNNEL=m
+CONFIG_NET_FOU=m
+CONFIG_NET_FOU_IP_TUNNELS=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_ESP_OFFLOAD=m
+# CONFIG_INET_ESPINTCP is not set
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_TABLE_PERTURB_ORDER=16
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+CONFIG_INET_UDP_DIAG=m
+CONFIG_INET_RAW_DIAG=m
+CONFIG_INET_DIAG_DESTROY=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_NV=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_TCP_CONG_DCTCP=m
+CONFIG_TCP_CONG_CDG=m
+CONFIG_TCP_CONG_BBR=m
+# CONFIG_DEFAULT_CUBIC is not set
+CONFIG_DEFAULT_RENO=y
+CONFIG_DEFAULT_TCP_CONG="reno"
+CONFIG_TCP_SIGPOOL=y
+# CONFIG_TCP_AO is not set
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_ESP_OFFLOAD=m
+# CONFIG_INET6_ESPINTCP is not set
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_IPV6_ILA=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_IPV6_VTI=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
+CONFIG_IPV6_FOU=m
+CONFIG_IPV6_FOU_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_IPV6_SEG6_LWTUNNEL=y
+CONFIG_IPV6_SEG6_HMAC=y
+CONFIG_IPV6_SEG6_BPF=y
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
+CONFIG_NETLABEL=y
+# CONFIG_MPTCP is not set
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NETWORK_PHY_TIMESTAMPING=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=m
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_EGRESS=y
+CONFIG_NETFILTER_SKIP_EGRESS=y
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_FAMILY_BRIDGE=y
+CONFIG_NETFILTER_FAMILY_ARP=y
+CONFIG_NETFILTER_BPF_LINK=y
+CONFIG_NETFILTER_NETLINK_HOOK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_NETLINK_OSF=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_LOG_SYSLOG=m
+CONFIG_NETFILTER_CONNCOUNT=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CONNTRACK_LABELS=y
+CONFIG_NF_CONNTRACK_OVS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NF_CT_NETLINK_HELPER=m
+CONFIG_NETFILTER_NETLINK_GLUE_CT=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_NAT_MASQUERADE=y
+CONFIG_NF_NAT_OVS=y
+CONFIG_NETFILTER_SYNPROXY=m
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_INET=y
+CONFIG_NF_TABLES_NETDEV=y
+CONFIG_NFT_NUMGEN=m
+CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
+CONFIG_NFT_CONNLIMIT=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_REDIR=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_TUNNEL=m
+CONFIG_NFT_QUEUE=m
+CONFIG_NFT_QUOTA=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_REJECT_INET=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_FIB=m
+CONFIG_NFT_FIB_INET=m
+CONFIG_NFT_XFRM=m
+CONFIG_NFT_SOCKET=m
+CONFIG_NFT_OSF=m
+CONFIG_NFT_TPROXY=m
+CONFIG_NFT_SYNPROXY=m
+CONFIG_NF_DUP_NETDEV=m
+CONFIG_NFT_DUP_NETDEV=m
+CONFIG_NFT_FWD_NETDEV=m
+CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NFT_REJECT_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
+CONFIG_NF_FLOW_TABLE_PROCFS=y
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XTABLES_COMPAT=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_AUDIT=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_NAT=m
+CONFIG_NETFILTER_XT_TARGET_NETMAP=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CGROUP=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_CPU=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MATCH_L2TP=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+# end of Core Netfilter Configuration
+
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPMARK=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_IPMAC=m
+CONFIG_IP_SET_HASH_MAC=m
+CONFIG_IP_SET_HASH_NETPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETNET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_FO=m
+CONFIG_IP_VS_OVF=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_MH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+CONFIG_IP_VS_TWOS=m
+
+#
+# IPVS SH scheduler
+#
+CONFIG_IP_VS_SH_TAB_BITS=8
+
+#
+# IPVS MH scheduler
+#
+CONFIG_IP_VS_MH_TAB_INDEX=12
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+CONFIG_IP_VS_NFCT=y
+CONFIG_IP_VS_PE_SIP=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_IP_NF_IPTABLES_LEGACY=m
+CONFIG_NF_SOCKET_IPV4=m
+CONFIG_NF_TPROXY_IPV4=m
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NFT_REJECT_IPV4=m
+CONFIG_NFT_DUP_IPV4=m
+CONFIG_NFT_FIB_IPV4=m
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_DUP_IPV4=m
+CONFIG_NF_LOG_ARP=m
+CONFIG_NF_LOG_IPV4=m
+CONFIG_NF_REJECT_IPV4=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_SYNPROXY=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_SECURITY=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_NFT_COMPAT_ARP=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+# end of IP: Netfilter Configuration
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_IP6_NF_IPTABLES_LEGACY=m
+CONFIG_NF_SOCKET_IPV6=m
+CONFIG_NF_TPROXY_IPV6=m
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NFT_REJECT_IPV6=m
+CONFIG_NFT_DUP_IPV6=m
+CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_DUP_IPV6=m
+CONFIG_NF_REJECT_IPV6=m
+CONFIG_NF_LOG_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_TARGET_SYNPROXY=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_SECURITY=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+# end of IPv6: Netfilter Configuration
+
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_TABLES_BRIDGE=m
+CONFIG_NFT_BRIDGE_META=m
+CONFIG_NFT_BRIDGE_REJECT=m
+CONFIG_NF_CONNTRACK_BRIDGE=m
+CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+
+#
+# DCCP CCIDs Configuration
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_TFRC_LIB=y
+# end of DCCP CCIDs Configuration
+
+#
+# DCCP Kernel Hacking
+#
+# CONFIG_IP_DCCP_DEBUG is not set
+# end of DCCP Kernel Hacking
+
+CONFIG_IP_SCTP=m
+CONFIG_SCTP_DBG_OBJCNT=y
+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
+CONFIG_SCTP_COOKIE_HMAC_MD5=y
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_INET_SCTP_DIAG=m
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+# CONFIG_RDS_DEBUG is not set
+CONFIG_TIPC=m
+CONFIG_TIPC_MEDIA_UDP=y
+CONFIG_TIPC_CRYPTO=y
+CONFIG_TIPC_DIAG=m
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+CONFIG_ATM_CLIP_NO_ICMP=y
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+CONFIG_ATM_BR2684_IPFILTER=y
+CONFIG_L2TP=m
+CONFIG_L2TP_DEBUGFS=m
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=m
+CONFIG_L2TP_ETH=m
+CONFIG_STP=y
+CONFIG_GARP=y
+CONFIG_MRP=y
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_BRIDGE_MRP=y
+# CONFIG_BRIDGE_CFM is not set
+CONFIG_NET_DSA=m
+CONFIG_NET_DSA_TAG_NONE=m
+CONFIG_NET_DSA_TAG_AR9331=m
+CONFIG_NET_DSA_TAG_BRCM_COMMON=m
+CONFIG_NET_DSA_TAG_BRCM=m
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
+CONFIG_NET_DSA_TAG_HELLCREEK=m
+CONFIG_NET_DSA_TAG_GSWIP=m
+CONFIG_NET_DSA_TAG_DSA_COMMON=m
+CONFIG_NET_DSA_TAG_DSA=m
+CONFIG_NET_DSA_TAG_EDSA=m
+CONFIG_NET_DSA_TAG_MTK=m
+CONFIG_NET_DSA_TAG_KSZ=m
+CONFIG_NET_DSA_TAG_OCELOT=m
+CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
+CONFIG_NET_DSA_TAG_QCA=m
+CONFIG_NET_DSA_TAG_RTL4_A=m
+CONFIG_NET_DSA_TAG_RTL8_4=m
+CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
+CONFIG_NET_DSA_TAG_LAN9303=m
+CONFIG_NET_DSA_TAG_SJA1105=m
+CONFIG_NET_DSA_TAG_TRAILER=m
+CONFIG_NET_DSA_TAG_VSC73XX_8021Q=m
+CONFIG_NET_DSA_TAG_XRS700X=m
+CONFIG_VLAN_8021Q=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_LLC=y
+CONFIG_LLC2=m
+CONFIG_ATALK=m
+CONFIG_X25=m
+CONFIG_LAPB=m
+CONFIG_PHONET=m
+CONFIG_6LOWPAN=m
+# CONFIG_6LOWPAN_DEBUGFS is not set
+CONFIG_6LOWPAN_NHC=m
+CONFIG_6LOWPAN_NHC_DEST=m
+CONFIG_6LOWPAN_NHC_FRAGMENT=m
+CONFIG_6LOWPAN_NHC_HOP=m
+CONFIG_6LOWPAN_NHC_IPV6=m
+CONFIG_6LOWPAN_NHC_MOBILITY=m
+CONFIG_6LOWPAN_NHC_ROUTING=m
+CONFIG_6LOWPAN_NHC_UDP=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
+CONFIG_6LOWPAN_GHC_UDP=m
+CONFIG_6LOWPAN_GHC_ICMPV6=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
+CONFIG_IEEE802154=m
+CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
+CONFIG_IEEE802154_SOCKET=m
+CONFIG_IEEE802154_6LOWPAN=m
+CONFIG_MAC802154=m
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_CBS=m
+CONFIG_NET_SCH_ETF=m
+CONFIG_NET_SCH_MQPRIO_LIB=m
+CONFIG_NET_SCH_TAPRIO=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_SKBPRIO=m
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_CODEL=m
+CONFIG_NET_SCH_FQ_CODEL=m
+CONFIG_NET_SCH_CAKE=m
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_HHF=m
+CONFIG_NET_SCH_PIE=m
+CONFIG_NET_SCH_FQ_PIE=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_SCH_PLUG=m
+CONFIG_NET_SCH_ETS=m
+CONFIG_NET_SCH_DEFAULT=y
+# CONFIG_DEFAULT_FQ is not set
+# CONFIG_DEFAULT_CODEL is not set
+# CONFIG_DEFAULT_FQ_CODEL is not set
+# CONFIG_DEFAULT_FQ_PIE is not set
+# CONFIG_DEFAULT_SFQ is not set
+CONFIG_DEFAULT_PFIFO_FAST=y
+CONFIG_DEFAULT_NET_SCH="pfifo_fast"
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_CGROUP=m
+CONFIG_NET_CLS_BPF=m
+CONFIG_NET_CLS_FLOWER=m
+CONFIG_NET_CLS_MATCHALL=m
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_EMATCH_CANID=m
+CONFIG_NET_EMATCH_IPSET=m
+CONFIG_NET_EMATCH_IPT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_SAMPLE=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_NET_ACT_CSUM=m
+CONFIG_NET_ACT_MPLS=m
+CONFIG_NET_ACT_VLAN=m
+CONFIG_NET_ACT_BPF=m
+CONFIG_NET_ACT_CONNMARK=m
+CONFIG_NET_ACT_CTINFO=m
+CONFIG_NET_ACT_SKBMOD=m
+CONFIG_NET_ACT_IFE=m
+CONFIG_NET_ACT_TUNNEL_KEY=m
+CONFIG_NET_ACT_CT=m
+CONFIG_NET_ACT_GATE=m
+CONFIG_NET_IFE_SKBMARK=m
+CONFIG_NET_IFE_SKBPRIO=m
+CONFIG_NET_IFE_SKBTCINDEX=m
+# CONFIG_NET_TC_SKB_EXT is not set
+CONFIG_NET_SCH_FIFO=y
+CONFIG_DCB=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_BATMAN_V=y
+CONFIG_BATMAN_ADV_BLA=y
+CONFIG_BATMAN_ADV_DAT=y
+CONFIG_BATMAN_ADV_NC=y
+CONFIG_BATMAN_ADV_MCAST=y
+CONFIG_BATMAN_ADV_DEBUG=y
+CONFIG_BATMAN_ADV_TRACING=y
+CONFIG_OPENVSWITCH=m
+CONFIG_OPENVSWITCH_GRE=m
+CONFIG_OPENVSWITCH_VXLAN=m
+CONFIG_OPENVSWITCH_GENEVE=m
+CONFIG_VSOCKETS=m
+CONFIG_VSOCKETS_DIAG=m
+CONFIG_VSOCKETS_LOOPBACK=m
+CONFIG_VIRTIO_VSOCKETS=m
+CONFIG_VIRTIO_VSOCKETS_COMMON=m
+CONFIG_NETLINK_DIAG=m
+CONFIG_MPLS=y
+CONFIG_NET_MPLS_GSO=m
+CONFIG_MPLS_ROUTING=m
+CONFIG_MPLS_IPTUNNEL=m
+CONFIG_NET_NSH=m
+CONFIG_HSR=m
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_L3_MASTER_DEV=y
+# CONFIG_QRTR is not set
+# CONFIG_NET_NCSI is not set
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_MAX_SKB_FRAGS=17
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_XPS=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_CGROUP_NET_CLASSID=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+CONFIG_BPF_STREAM_PARSER=y
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+CONFIG_NET_DROP_MONITOR=m
+# end of Network testing
+# end of Networking options
+
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+CONFIG_AX25=m
+CONFIG_AX25_DAMA_SLAVE=y
+CONFIG_NETROM=m
+CONFIG_ROSE=m
+
+#
+# AX.25 network device drivers
+#
+CONFIG_MKISS=m
+CONFIG_6PACK=m
+CONFIG_BPQETHER=m
+CONFIG_BAYCOM_SER_FDX=m
+CONFIG_BAYCOM_SER_HDX=m
+CONFIG_YAM=m
+# end of AX.25 network device drivers
+
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_GW=m
+CONFIG_CAN_J1939=m
+# CONFIG_CAN_ISOTP is not set
+CONFIG_BT=m
+CONFIG_BT_BREDR=y
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_LE=y
+CONFIG_BT_LE_L2CAP_ECRED=y
+CONFIG_BT_6LOWPAN=m
+CONFIG_BT_LEDS=y
+# CONFIG_BT_MSFTEXT is not set
+CONFIG_BT_AOSPEXT=y
+# CONFIG_BT_DEBUGFS is not set
+# CONFIG_BT_SELFTEST is not set
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_INTEL=m
+CONFIG_BT_BCM=m
+CONFIG_BT_RTL=m
+CONFIG_BT_QCA=m
+CONFIG_BT_MTK=m
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
+CONFIG_BT_HCIBTUSB_POLL_SYNC=y
+CONFIG_BT_HCIBTUSB_BCM=y
+CONFIG_BT_HCIBTUSB_MTK=y
+CONFIG_BT_HCIBTUSB_RTL=y
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_SERDEV=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_NOKIA=m
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_RTL=y
+CONFIG_BT_HCIUART_QCA=y
+CONFIG_BT_HCIUART_AG6XX=y
+CONFIG_BT_HCIUART_MRVL=y
+CONFIG_BT_HCIBCM203X=m
+# CONFIG_BT_HCIBCM4377 is not set
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_BT_ATH3K=m
+CONFIG_BT_MTKSDIO=m
+CONFIG_BT_MTKUART=m
+CONFIG_BT_HCIRSI=m
+CONFIG_BT_VIRTIO=m
+# CONFIG_BT_NXPUART is not set
+# CONFIG_BT_INTEL_PCIE is not set
+# end of Bluetooth device drivers
+
+CONFIG_AF_RXRPC=m
+# CONFIG_AF_RXRPC_IPV6 is not set
+# CONFIG_AF_RXRPC_INJECT_LOSS is not set
+# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set
+# CONFIG_AF_RXRPC_DEBUG is not set
+# CONFIG_RXKAD is not set
+# CONFIG_RXPERF is not set
+# CONFIG_AF_KCM is not set
+CONFIG_STREAM_PARSER=y
+# CONFIG_MCTP is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_CFG80211_WEXT_EXPORT=y
+# CONFIG_CFG80211_KUNIT_TEST is not set
+CONFIG_LIB80211=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_KUNIT_TEST is not set
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+CONFIG_RFKILL=m
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=m
+CONFIG_NET_9P=m
+CONFIG_NET_9P_FD=m
+CONFIG_NET_9P_VIRTIO=m
+CONFIG_NET_9P_XEN=m
+# CONFIG_NET_9P_DEBUG is not set
+CONFIG_CAIF=m
+# CONFIG_CAIF_DEBUG is not set
+CONFIG_CAIF_NETDEV=m
+CONFIG_CAIF_USB=m
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
+CONFIG_NFC=m
+CONFIG_NFC_DIGITAL=m
+CONFIG_NFC_NCI=m
+CONFIG_NFC_NCI_SPI=m
+CONFIG_NFC_NCI_UART=m
+CONFIG_NFC_HCI=m
+CONFIG_NFC_SHDLC=y
+
+#
+# Near Field Communication (NFC) devices
+#
+CONFIG_NFC_TRF7970A=m
+CONFIG_NFC_SIM=m
+CONFIG_NFC_PORT100=m
+CONFIG_NFC_VIRTUAL_NCI=m
+CONFIG_NFC_FDP=m
+CONFIG_NFC_FDP_I2C=m
+CONFIG_NFC_PN544=m
+CONFIG_NFC_PN544_I2C=m
+CONFIG_NFC_PN533=m
+CONFIG_NFC_PN533_USB=m
+CONFIG_NFC_PN533_I2C=m
+CONFIG_NFC_PN532_UART=m
+CONFIG_NFC_MICROREAD=m
+CONFIG_NFC_MICROREAD_I2C=m
+CONFIG_NFC_MRVL=m
+CONFIG_NFC_MRVL_USB=m
+CONFIG_NFC_MRVL_UART=m
+CONFIG_NFC_MRVL_I2C=m
+CONFIG_NFC_MRVL_SPI=m
+CONFIG_NFC_ST21NFCA=m
+CONFIG_NFC_ST21NFCA_I2C=m
+CONFIG_NFC_ST_NCI=m
+CONFIG_NFC_ST_NCI_I2C=m
+CONFIG_NFC_ST_NCI_SPI=m
+CONFIG_NFC_NXP_NCI=m
+CONFIG_NFC_NXP_NCI_I2C=m
+CONFIG_NFC_S3FWRN5=m
+CONFIG_NFC_S3FWRN5_I2C=m
+CONFIG_NFC_S3FWRN82_UART=m
+CONFIG_NFC_ST95HF=m
+# end of Near Field Communication (NFC) devices
+
+CONFIG_PSAMPLE=m
+CONFIG_NET_IFE=m
+CONFIG_LWTUNNEL=y
+CONFIG_LWTUNNEL_BPF=y
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+CONFIG_SOCK_VALIDATE_XMIT=y
+CONFIG_NET_IEEE8021Q_HELPERS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SOCK_MSG=y
+CONFIG_NET_DEVLINK=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_FAILOVER=y
+CONFIG_ETHTOOL_NETLINK=y
+# CONFIG_NETDEV_ADDR_LIST_TEST is not set
+# CONFIG_NET_TEST is not set
+
+#
+# Device Drivers
+#
+CONFIG_ARM_AMBA=y
+CONFIG_HAVE_PCI=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEAER_INJECT=m
+CONFIG_PCIEAER_CXL=y
+CONFIG_PCIE_ECRC=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+CONFIG_PCIE_PME=y
+# CONFIG_PCIE_DPC is not set
+# CONFIG_PCIE_PTM is not set
+CONFIG_PCI_MSI=y
+CONFIG_PCI_QUIRKS=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+CONFIG_PCI_STUB=y
+# CONFIG_PCI_PF_STUB is not set
+CONFIG_PCI_ATS=y
+CONFIG_PCI_DOE=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_PCI_LABEL=y
+# CONFIG_PCI_DYNAMIC_OF_NODES is not set
+# CONFIG_PCIE_BUS_TUNE_OFF is not set
+CONFIG_PCIE_BUS_DEFAULT=y
+# CONFIG_PCIE_BUS_SAFE is not set
+# CONFIG_PCIE_BUS_PERFORMANCE is not set
+# CONFIG_PCIE_BUS_PEER2PEER is not set
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+# CONFIG_HOTPLUG_PCI_ACPI_AMPERE_ALTRA is not set
+# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# PCI controller drivers
+#
+CONFIG_PCIE_ALTERA=y
+CONFIG_PCIE_ALTERA_MSI=y
+CONFIG_PCI_HOST_THUNDER_PEM=y
+CONFIG_PCI_HOST_THUNDER_ECAM=y
+# CONFIG_PCI_FTPCI100 is not set
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+# CONFIG_PCIE_HISI_ERR is not set
+CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCIE_ROCKCHIP_HOST=y
+CONFIG_PCIE_ROCKCHIP_EP=y
+CONFIG_PCI_XGENE=y
+CONFIG_PCI_XGENE_MSI=y
+# CONFIG_PCIE_XILINX is not set
+
+#
+# Cadence-based PCIe controllers
+#
+# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
+# CONFIG_PCIE_CADENCE_PLAT_EP is not set
+# end of Cadence-based PCIe controllers
+
+#
+# DesignWare-based PCIe controllers
+#
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_DW_EP=y
+# CONFIG_PCIE_AL is not set
+# CONFIG_PCI_MESON is not set
+CONFIG_PCI_HISI=y
+# CONFIG_PCIE_KIRIN is not set
+CONFIG_PCIE_DW_PLAT=y
+CONFIG_PCIE_DW_PLAT_HOST=y
+CONFIG_PCIE_DW_PLAT_EP=y
+CONFIG_PCIE_ROCKCHIP_DW=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+# CONFIG_PCIE_ROCKCHIP_DW_EP is not set
+# end of DesignWare-based PCIe controllers
+
+#
+# Mobiveil-based PCIe controllers
+#
+# end of Mobiveil-based PCIe controllers
+
+#
+# PLDA-based PCIe controllers
+#
+# CONFIG_PCIE_MICROCHIP_HOST is not set
+# end of PLDA-based PCIe controllers
+# end of PCI controller drivers
+
+#
+# PCI Endpoint
+#
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=m
+CONFIG_PCI_EPF_NTB=m
+# end of PCI Endpoint
+
+#
+# PCI switch controller drivers
+#
+# CONFIG_PCI_SW_SWITCHTEC is not set
+# end of PCI switch controller drivers
+
+CONFIG_CXL_BUS=m
+CONFIG_CXL_PCI=m
+# CONFIG_CXL_MEM_RAW_COMMANDS is not set
+CONFIG_CXL_ACPI=m
+CONFIG_CXL_MEM=m
+CONFIG_CXL_PORT=m
+CONFIG_CXL_SUSPEND=y
+CONFIG_CXL_REGION=y
+# CONFIG_CXL_REGION_INVALIDATION_TEST is not set
+# CONFIG_PCCARD is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_AUXILIARY_BUS=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_FW_LOADER_DEBUG=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER is not set
+# CONFIG_FW_LOADER_COMPRESS is not set
+CONFIG_FW_CACHE=y
+CONFIG_FW_UPLOAD=y
+# end of Firmware loader
+
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_ALLOW_DEV_COREDUMP=y
+CONFIG_DEV_COREDUMP=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+CONFIG_HMEM_REPORTING=y
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+# CONFIG_DM_KUNIT_TEST is not set
+# CONFIG_DRIVER_PE_KUNIT_TEST is not set
+CONFIG_SYS_HYPERVISOR=y
+CONFIG_GENERIC_CPU_DEVICES=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_SOC_BUS=y
+CONFIG_REGMAP=y
+# CONFIG_REGMAP_KUNIT is not set
+# CONFIG_REGMAP_BUILD is not set
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SLIMBUS=m
+CONFIG_REGMAP_SPI=m
+CONFIG_REGMAP_SPMI=m
+CONFIG_REGMAP_W1=m
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_SOUNDWIRE=m
+CONFIG_REGMAP_SOUNDWIRE_MBQ=m
+CONFIG_REGMAP_SCCB=m
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_DMA_FENCE_TRACE is not set
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_ARCH_NUMA=y
+# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+CONFIG_ARM_CCI=y
+CONFIG_ARM_CCI400_COMMON=y
+# CONFIG_MOXTET is not set
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_MHI_BUS=m
+# CONFIG_MHI_BUS_DEBUG is not set
+CONFIG_MHI_BUS_PCI_GENERIC=m
+# CONFIG_MHI_BUS_EP is not set
+# end of Bus devices
+
+#
+# Cache Drivers
+#
+# end of Cache Drivers
+
+CONFIG_CONNECTOR=m
+
+#
+# Firmware Drivers
+#
+
+#
+# ARM System Control and Management Interface Protocol
+#
+CONFIG_ARM_SCMI_PROTOCOL=y
+# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_MSG=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
+# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE is not set
+CONFIG_ARM_SCMI_POWER_CONTROL=m
+# end of ARM System Control and Management Interface Protocol
+
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SDE_INTERFACE=y
+# CONFIG_FIRMWARE_MEMMAP is not set
+CONFIG_DMIID=y
+CONFIG_DMI_SYSFS=y
+CONFIG_ISCSI_IBFT=y
+# CONFIG_FW_CFG_SYSFS is not set
+CONFIG_SYSFB=y
+CONFIG_SYSFB_SIMPLEFB=y
+CONFIG_ARM_FFA_TRANSPORT=m
+CONFIG_ARM_FFA_SMCCC=y
+CONFIG_FW_CS_DSP=m
+# CONFIG_GOOGLE_FIRMWARE is not set
+
+#
+# EFI (Extensible Firmware Interface) Support
+#
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_VARS_PSTORE=y
+CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
+CONFIG_EFI_SOFT_RESERVE=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_GENERIC_STUB=y
+# CONFIG_EFI_ZBOOT is not set
+CONFIG_EFI_ARMSTUB_DTB_LOADER=y
+CONFIG_EFI_BOOTLOADER_CONTROL=m
+CONFIG_EFI_CAPSULE_LOADER=m
+CONFIG_EFI_TEST=m
+CONFIG_RESET_ATTACK_MITIGATION=y
+CONFIG_EFI_DISABLE_PCI_DMA=y
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+# CONFIG_EFI_COCO_SECRET is not set
+# end of EFI (Extensible Firmware Interface) Support
+
+CONFIG_UEFI_CPER=y
+CONFIG_UEFI_CPER_ARM=y
+# CONFIG_TEE_STMM_EFI is not set
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_PSCI_CHECKER=y
+
+#
+# Qualcomm firmware drivers
+#
+# end of Qualcomm firmware drivers
+
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
+CONFIG_ARM_SMCCC_SOC_ID=y
+
+#
+# Tegra firmware driver
+#
+# end of Tegra firmware driver
+# end of Firmware Drivers
+
+CONFIG_GNSS=m
+CONFIG_GNSS_SERIAL=m
+CONFIG_GNSS_MTK_SERIAL=m
+CONFIG_GNSS_SIRF_SERIAL=m
+CONFIG_GNSS_UBX_SERIAL=m
+# CONFIG_GNSS_USB is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+
+#
+# Partition parsers
+#
+CONFIG_MTD_CMDLINE_PARTS=m
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_AFS_PARTS=m
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# end of Partition parsers
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+
+#
+# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
+#
+CONFIG_FTL=m
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=m
+CONFIG_RFD_FTL=m
+CONFIG_SSFDC=m
+CONFIG_SM_FTL=m
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_PSTORE is not set
+CONFIG_MTD_SWAP=m
+# CONFIG_MTD_PARTITIONED_MASTER is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# end of RAM/ROM/Flash chip drivers
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PHYSMAP_VERSATILE is not set
+# CONFIG_MTD_PHYSMAP_GEMINI is not set
+CONFIG_MTD_PHYSMAP_GPIO_ADDR=y
+CONFIG_MTD_PCI=m
+# CONFIG_MTD_PLATRAM is not set
+# end of Mapping drivers for chip access
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_MCHP23K256 is not set
+CONFIG_MTD_MCHP48L640=m
+CONFIG_MTD_SST25L=y
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# end of Self-contained MTD device drivers
+
+#
+# NAND
+#
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_ONENAND=m
+# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
+# CONFIG_MTD_ONENAND_GENERIC is not set
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+CONFIG_MTD_RAW_NAND=y
+
+#
+# Raw/parallel NAND flash controllers
+#
+CONFIG_MTD_NAND_DENALI=y
+# CONFIG_MTD_NAND_DENALI_PCI is not set
+CONFIG_MTD_NAND_DENALI_DT=y
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_BRCMNAND is not set
+# CONFIG_MTD_NAND_MXIC is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_CADENCE is not set
+# CONFIG_MTD_NAND_ARASAN is not set
+# CONFIG_MTD_NAND_INTEL_LGM is not set
+CONFIG_MTD_NAND_ROCKCHIP=m
+
+#
+# Misc
+#
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_RICOH is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_SPI_NAND=m
+
+#
+# ECC engine support
+#
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
+# CONFIG_MTD_NAND_ECC_SW_BCH is not set
+CONFIG_MTD_NAND_ECC_MXIC=y
+# end of ECC engine support
+# end of NAND
+
+#
+# LPDDR & LPDDR2 PCM memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# end of LPDDR & LPDDR2 PCM memory drivers
+
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
+CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
+# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_BLOCK is not set
+# CONFIG_MTD_UBI_NVMEM is not set
+CONFIG_MTD_HYPERBUS=m
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+# CONFIG_OF_KUNIT_TEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_NUMA=y
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+
+#
+# Protocols
+#
+CONFIG_PNPACPI=y
+CONFIG_BLK_DEV=y
+CONFIG_BLK_DEV_NULL_BLK=m
+CONFIG_CDROM=y
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+CONFIG_ZRAM=m
+CONFIG_ZRAM_DEF_COMP_LZORLE=y
+# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
+# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
+# CONFIG_ZRAM_DEF_COMP_LZO is not set
+# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
+# CONFIG_ZRAM_DEF_COMP_842 is not set
+CONFIG_ZRAM_DEF_COMP="lzo-rle"
+CONFIG_ZRAM_WRITEBACK=y
+# CONFIG_ZRAM_TRACK_ENTRY_ACTIME is not set
+# CONFIG_ZRAM_MEMORY_TRACKING is not set
+# CONFIG_ZRAM_MULTI_COMP is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+CONFIG_BLK_DEV_DRBD=m
+# CONFIG_DRBD_FAULT_INJECTION is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_CDROM_PKTCDVD is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_XEN_BLKDEV_FRONTEND=m
+CONFIG_XEN_BLKDEV_BACKEND=m
+CONFIG_VIRTIO_BLK=y
+CONFIG_BLK_DEV_RBD=m
+CONFIG_BLK_DEV_UBLK=m
+CONFIG_BLKDEV_UBLK_LEGACY_OPCODES=y
+
+#
+# NVME Support
+#
+CONFIG_NVME_KEYRING=m
+CONFIG_NVME_AUTH=y
+CONFIG_NVME_CORE=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_NVME_MULTIPATH=y
+# CONFIG_NVME_VERBOSE_ERRORS is not set
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_FABRICS=m
+CONFIG_NVME_FC=m
+CONFIG_NVME_TCP=m
+CONFIG_NVME_TCP_TLS=y
+CONFIG_NVME_HOST_AUTH=y
+CONFIG_NVME_TARGET=m
+# CONFIG_NVME_TARGET_DEBUGFS is not set
+CONFIG_NVME_TARGET_PASSTHRU=y
+CONFIG_NVME_TARGET_LOOP=m
+CONFIG_NVME_TARGET_FC=m
+CONFIG_NVME_TARGET_FCLOOP=m
+CONFIG_NVME_TARGET_TCP=m
+CONFIG_NVME_TARGET_TCP_TLS=y
+CONFIG_NVME_TARGET_AUTH=y
+# end of NVME Support
+
+#
+# Misc devices
+#
+CONFIG_AD525X_DPOT=m
+CONFIG_AD525X_DPOT_I2C=m
+CONFIG_AD525X_DPOT_SPI=m
+# CONFIG_DUMMY_IRQ is not set
+CONFIG_PHANTOM=m
+CONFIG_TIFM_CORE=m
+CONFIG_TIFM_7XX1=m
+# CONFIG_ICS932S401 is not set
+CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_HI6421V600_IRQ=m
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+CONFIG_SRAM=y
+CONFIG_DW_XDATA_PCIE=m
+# CONFIG_PCI_ENDPOINT_TEST is not set
+CONFIG_XILINX_SDFEC=m
+CONFIG_MISC_RTSX=m
+# CONFIG_HISI_HIKEY_USB is not set
+# CONFIG_OPEN_DICE is not set
+CONFIG_VCPU_STALL_DETECTOR=m
+# CONFIG_NSM is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_AT25=m
+CONFIG_EEPROM_MAX6875=m
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_IDT_89HPESX is not set
+CONFIG_EEPROM_EE1004=m
+# end of EEPROM support
+
+CONFIG_CB710_CORE=m
+# CONFIG_CB710_DEBUG is not set
+CONFIG_CB710_DEBUG_ASSUMPTIONS=y
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# end of Texas Instruments shared transport line discipline
+
+# CONFIG_SENSORS_LIS3_I2C is not set
+CONFIG_ALTERA_STAPL=m
+# CONFIG_VMWARE_VMCI is not set
+CONFIG_GENWQE=m
+CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0
+CONFIG_ECHO=m
+CONFIG_BCM_VK=m
+# CONFIG_BCM_VK_TTY is not set
+CONFIG_MISC_ALCOR_PCI=m
+CONFIG_MISC_RTSX_PCI=m
+CONFIG_MISC_RTSX_USB=m
+CONFIG_UACCE=m
+# CONFIG_PVPANIC is not set
+CONFIG_GP_PCI1XXXX=m
+# CONFIG_KEBA_CP500 is not set
+# end of Misc devices
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+# CONFIG_SCSI_LIB_KUNIT_TEST is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_SCSI_ENCLOSURE=m
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_PROTO_TEST is not set
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SRP_ATTRS=m
+# end of SCSI Transports
+
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=y
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+CONFIG_SCSI_BNX2_ISCSI=m
+CONFIG_SCSI_BNX2X_FCOE=m
+CONFIG_BE2ISCSI=m
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+CONFIG_SCSI_HPSA=m
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_HISI_SAS is not set
+CONFIG_SCSI_MVSAS=m
+# CONFIG_SCSI_MVSAS_DEBUG is not set
+CONFIG_SCSI_MVSAS_TASKLET=y
+CONFIG_SCSI_MVUMI=m
+# CONFIG_SCSI_ADVANSYS is not set
+CONFIG_SCSI_ARCMSR=m
+CONFIG_SCSI_ESAS2R=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_MM=m
+CONFIG_MEGARAID_MAILBOX=m
+CONFIG_MEGARAID_LEGACY=m
+CONFIG_MEGARAID_SAS=m
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+# CONFIG_SCSI_MPT2SAS is not set
+CONFIG_SCSI_MPI3MR=m
+# CONFIG_SCSI_SMARTPQI is not set
+# CONFIG_SCSI_HPTIOP is not set
+CONFIG_SCSI_BUSLOGIC=m
+CONFIG_SCSI_FLASHPOINT=y
+# CONFIG_SCSI_MYRB is not set
+# CONFIG_SCSI_MYRS is not set
+# CONFIG_XEN_SCSI_FRONTEND is not set
+CONFIG_LIBFC=m
+CONFIG_LIBFCOE=m
+CONFIG_FCOE=m
+CONFIG_SCSI_SNIC=m
+# CONFIG_SCSI_SNIC_DEBUG_FS is not set
+CONFIG_SCSI_DMX3191D=m
+# CONFIG_SCSI_FDOMAIN_PCI is not set
+# CONFIG_SCSI_IPS is not set
+CONFIG_SCSI_INITIO=m
+CONFIG_SCSI_INIA100=m
+CONFIG_SCSI_STEX=m
+CONFIG_SCSI_SYM53C8XX_2=m
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+CONFIG_SCSI_SYM53C8XX_MMIO=y
+CONFIG_SCSI_IPR=m
+CONFIG_SCSI_IPR_TRACE=y
+CONFIG_SCSI_IPR_DUMP=y
+CONFIG_SCSI_QLOGIC_1280=m
+CONFIG_SCSI_QLA_FC=m
+CONFIG_TCM_QLA2XXX=m
+# CONFIG_TCM_QLA2XXX_DEBUG is not set
+CONFIG_SCSI_QLA_ISCSI=m
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_EFCT is not set
+CONFIG_SCSI_DC395x=m
+CONFIG_SCSI_AM53C974=m
+CONFIG_SCSI_WD719X=m
+CONFIG_SCSI_DEBUG=m
+CONFIG_SCSI_PMCRAID=m
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_BFA_FC is not set
+CONFIG_SCSI_VIRTIO=y
+CONFIG_SCSI_CHELSIO_FCOE=m
+CONFIG_SCSI_DH=y
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DH_HP_SW=m
+CONFIG_SCSI_DH_EMC=m
+CONFIG_SCSI_DH_ALUA=m
+# end of SCSI device support
+
+CONFIG_ATA=y
+CONFIG_SATA_HOST=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATA_FORCE=y
+CONFIG_ATA_ACPI=y
+# CONFIG_SATA_ZPODD is not set
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_MOBILE_LPM_POLICY=0
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_DWC=y
+CONFIG_AHCI_CEVA=y
+CONFIG_SATA_INIC162X=m
+CONFIG_SATA_ACARD_AHCI=m
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+CONFIG_PDC_ADMA=m
+CONFIG_SATA_QSTOR=m
+CONFIG_SATA_SX4=m
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+CONFIG_ATA_PIIX=y
+# CONFIG_SATA_DWC is not set
+CONFIG_SATA_MV=m
+CONFIG_SATA_NV=m
+CONFIG_SATA_PROMISE=m
+CONFIG_SATA_SIL=m
+CONFIG_SATA_SIS=m
+CONFIG_SATA_SVW=m
+CONFIG_SATA_ULI=m
+CONFIG_SATA_VIA=m
+CONFIG_SATA_VITESSE=m
+
+#
+# PATA SFF controllers with BMDMA
+#
+CONFIG_PATA_ALI=m
+CONFIG_PATA_AMD=m
+CONFIG_PATA_ARTOP=m
+CONFIG_PATA_ATIIXP=m
+CONFIG_PATA_ATP867X=m
+CONFIG_PATA_CMD64X=m
+CONFIG_PATA_CYPRESS=m
+CONFIG_PATA_EFAR=m
+CONFIG_PATA_HPT366=m
+CONFIG_PATA_HPT37X=m
+CONFIG_PATA_HPT3X2N=m
+CONFIG_PATA_HPT3X3=m
+# CONFIG_PATA_HPT3X3_DMA is not set
+CONFIG_PATA_IT8213=m
+CONFIG_PATA_IT821X=m
+CONFIG_PATA_JMICRON=m
+CONFIG_PATA_MARVELL=m
+CONFIG_PATA_NETCELL=m
+CONFIG_PATA_NINJA32=m
+CONFIG_PATA_NS87415=m
+CONFIG_PATA_OLDPIIX=m
+CONFIG_PATA_OPTIDMA=m
+CONFIG_PATA_PDC2027X=m
+CONFIG_PATA_PDC_OLD=m
+# CONFIG_PATA_RADISYS is not set
+CONFIG_PATA_RDC=m
+CONFIG_PATA_SCH=m
+CONFIG_PATA_SERVERWORKS=m
+CONFIG_PATA_SIL680=m
+CONFIG_PATA_SIS=m
+CONFIG_PATA_TOSHIBA=m
+CONFIG_PATA_TRIFLEX=m
+CONFIG_PATA_VIA=m
+CONFIG_PATA_WINBOND=m
+
+#
+# PIO-only SFF controllers
+#
+CONFIG_PATA_CMD640_PCI=m
+CONFIG_PATA_MPIIX=m
+CONFIG_PATA_NS87410=m
+CONFIG_PATA_OPTI=m
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+CONFIG_PATA_ACPI=m
+CONFIG_ATA_GENERIC=y
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_AUTODETECT=y
+CONFIG_MD_BITMAP_FILE=y
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_CLUSTER=m
+CONFIG_BCACHE=m
+# CONFIG_BCACHE_DEBUG is not set
+# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_BUFIO=m
+# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
+CONFIG_DM_BIO_PRISON=m
+CONFIG_DM_PERSISTENT_DATA=m
+CONFIG_DM_UNSTRIPED=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
+CONFIG_DM_CACHE_SMQ=m
+CONFIG_DM_WRITECACHE=m
+# CONFIG_DM_EBS is not set
+CONFIG_DM_ERA=m
+CONFIG_DM_CLONE=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_RAID=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+# CONFIG_DM_MULTIPATH_HST is not set
+CONFIG_DM_MULTIPATH_IOA=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_DUST=m
+CONFIG_DM_UEVENT=y
+CONFIG_DM_FLAKEY=m
+CONFIG_DM_VERITY=m
+# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
+CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_SWITCH=m
+CONFIG_DM_LOG_WRITES=m
+CONFIG_DM_INTEGRITY=m
+CONFIG_DM_ZONED=m
+CONFIG_DM_AUDIT=y
+# CONFIG_DM_VDO is not set
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
+CONFIG_TCM_USER2=m
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_TCM_FC=m
+CONFIG_ISCSI_TARGET=m
+# CONFIG_REMOTE_TARGET is not set
+CONFIG_FUSION=y
+CONFIG_FUSION_SPI=m
+CONFIG_FUSION_FC=m
+CONFIG_FUSION_SAS=m
+CONFIG_FUSION_MAX_SGE=128
+CONFIG_FUSION_CTL=m
+CONFIG_FUSION_LAN=m
+# CONFIG_FUSION_LOGGING is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+CONFIG_FIREWIRE_NOSY=m
+# end of IEEE 1394 (FireWire) support
+
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+CONFIG_BONDING=m
+CONFIG_DUMMY=m
+CONFIG_WIREGUARD=m
+# CONFIG_WIREGUARD_DEBUG is not set
+CONFIG_EQUALIZER=m
+CONFIG_NET_FC=y
+CONFIG_IFB=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVLAN=m
+CONFIG_IPVTAP=m
+CONFIG_VXLAN=m
+CONFIG_GENEVE=m
+CONFIG_BAREUDP=m
+CONFIG_GTP=m
+# CONFIG_PFCP is not set
+CONFIG_AMT=m
+CONFIG_MACSEC=m
+CONFIG_NETCONSOLE=y
+CONFIG_NETCONSOLE_DYNAMIC=y
+# CONFIG_NETCONSOLE_EXTENDED_LOG is not set
+CONFIG_NETPOLL=y
+CONFIG_NET_POLL_CONTROLLER=y
+CONFIG_TUN=m
+CONFIG_TAP=m
+CONFIG_TUN_VNET_CROSS_LE=y
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=m
+CONFIG_NLMON=m
+# CONFIG_NETKIT is not set
+CONFIG_NET_VRF=m
+CONFIG_MHI_NET=m
+# CONFIG_ARCNET is not set
+CONFIG_ATM_DRIVERS=y
+CONFIG_ATM_DUMMY=m
+CONFIG_ATM_TCP=m
+CONFIG_ATM_LANAI=m
+CONFIG_ATM_ENI=m
+# CONFIG_ATM_ENI_DEBUG is not set
+# CONFIG_ATM_ENI_TUNE_BURST is not set
+CONFIG_ATM_NICSTAR=m
+# CONFIG_ATM_NICSTAR_USE_SUNI is not set
+# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set
+CONFIG_ATM_IDT77252=m
+# CONFIG_ATM_IDT77252_DEBUG is not set
+# CONFIG_ATM_IDT77252_RCV_ALL is not set
+CONFIG_ATM_IDT77252_USE_SUNI=y
+CONFIG_ATM_IA=m
+# CONFIG_ATM_IA_DEBUG is not set
+CONFIG_ATM_FORE200E=m
+# CONFIG_ATM_FORE200E_USE_TASKLET is not set
+CONFIG_ATM_FORE200E_TX_RETRY=16
+CONFIG_ATM_FORE200E_DEBUG=0
+CONFIG_ATM_HE=m
+# CONFIG_ATM_HE_USE_SUNI is not set
+CONFIG_ATM_SOLOS=m
+CONFIG_CAIF_DRIVERS=y
+CONFIG_CAIF_TTY=m
+CONFIG_CAIF_VIRTIO=m
+
+#
+# Distributed Switch Architecture drivers
+#
+CONFIG_B53=m
+CONFIG_B53_SPI_DRIVER=m
+CONFIG_B53_MDIO_DRIVER=m
+CONFIG_B53_MMAP_DRIVER=m
+CONFIG_B53_SRAB_DRIVER=m
+CONFIG_B53_SERDES=m
+CONFIG_NET_DSA_BCM_SF2=m
+CONFIG_NET_DSA_LOOP=m
+CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
+CONFIG_NET_DSA_LANTIQ_GSWIP=m
+CONFIG_NET_DSA_MT7530=m
+CONFIG_NET_DSA_MT7530_MDIO=m
+CONFIG_NET_DSA_MT7530_MMIO=m
+CONFIG_NET_DSA_MV88E6060=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
+CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
+# CONFIG_NET_DSA_MICROCHIP_KSZ_PTP is not set
+CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
+CONFIG_NET_DSA_MV88E6XXX=m
+# CONFIG_NET_DSA_MV88E6XXX_PTP is not set
+# CONFIG_NET_DSA_MSCC_OCELOT_EXT is not set
+# CONFIG_NET_DSA_MSCC_SEVILLE is not set
+CONFIG_NET_DSA_AR9331=m
+CONFIG_NET_DSA_QCA8K=m
+# CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT is not set
+CONFIG_NET_DSA_SJA1105=m
+# CONFIG_NET_DSA_SJA1105_PTP is not set
+CONFIG_NET_DSA_XRS700X=m
+CONFIG_NET_DSA_XRS700X_I2C=m
+CONFIG_NET_DSA_XRS700X_MDIO=m
+CONFIG_NET_DSA_REALTEK=m
+# CONFIG_NET_DSA_REALTEK_MDIO is not set
+# CONFIG_NET_DSA_REALTEK_SMI is not set
+CONFIG_NET_DSA_SMSC_LAN9303=m
+CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
+CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
+CONFIG_NET_DSA_VITESSE_VSC73XX=m
+CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
+CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
+# end of Distributed Switch Architecture drivers
+
+CONFIG_ETHERNET=y
+CONFIG_MDIO=m
+CONFIG_NET_VENDOR_3COM=y
+# CONFIG_VORTEX is not set
+# CONFIG_TYPHOON is not set
+CONFIG_NET_VENDOR_ADAPTEC=y
+# CONFIG_ADAPTEC_STARFIRE is not set
+CONFIG_NET_VENDOR_AGERE=y
+CONFIG_ET131X=m
+CONFIG_NET_VENDOR_ALACRITECH=y
+# CONFIG_SLICOSS is not set
+CONFIG_NET_VENDOR_ALTEON=y
+CONFIG_ACENIC=m
+# CONFIG_ACENIC_OMIT_TIGON_I is not set
+CONFIG_ALTERA_TSE=m
+CONFIG_NET_VENDOR_AMAZON=y
+# CONFIG_ENA_ETHERNET is not set
+CONFIG_NET_VENDOR_AMD=y
+CONFIG_AMD8111_ETH=m
+CONFIG_PCNET32=m
+CONFIG_AMD_XGBE=m
+# CONFIG_AMD_XGBE_DCB is not set
+# CONFIG_PDS_CORE is not set
+CONFIG_NET_VENDOR_AQUANTIA=y
+CONFIG_AQTION=m
+CONFIG_NET_VENDOR_ARC=y
+# CONFIG_EMAC_ROCKCHIP is not set
+CONFIG_NET_VENDOR_ASIX=y
+# CONFIG_SPI_AX88796C is not set
+CONFIG_NET_VENDOR_ATHEROS=y
+CONFIG_ATL2=m
+CONFIG_ATL1=m
+CONFIG_ATL1E=m
+CONFIG_ATL1C=m
+CONFIG_ALX=m
+CONFIG_NET_VENDOR_BROADCOM=y
+CONFIG_B44=m
+CONFIG_B44_PCI_AUTOSELECT=y
+CONFIG_B44_PCICORE_AUTOSELECT=y
+CONFIG_B44_PCI=y
+CONFIG_BCMGENET=m
+CONFIG_BNX2=m
+CONFIG_CNIC=m
+CONFIG_TIGON3=m
+CONFIG_TIGON3_HWMON=y
+CONFIG_BNX2X=m
+CONFIG_BNX2X_SRIOV=y
+CONFIG_SYSTEMPORT=m
+CONFIG_BNXT=m
+CONFIG_BNXT_SRIOV=y
+CONFIG_BNXT_FLOWER_OFFLOAD=y
+# CONFIG_BNXT_DCB is not set
+CONFIG_BNXT_HWMON=y
+CONFIG_NET_VENDOR_CADENCE=y
+CONFIG_MACB=y
+CONFIG_MACB_USE_HWSTAMP=y
+# CONFIG_MACB_PCI is not set
+CONFIG_NET_VENDOR_CAVIUM=y
+CONFIG_THUNDER_NIC_PF=y
+# CONFIG_THUNDER_NIC_VF is not set
+CONFIG_THUNDER_NIC_BGX=y
+CONFIG_THUNDER_NIC_RGX=y
+CONFIG_CAVIUM_PTP=y
+# CONFIG_LIQUIDIO is not set
+# CONFIG_LIQUIDIO_VF is not set
+CONFIG_NET_VENDOR_CHELSIO=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_CHELSIO_T4 is not set
+# CONFIG_CHELSIO_T4VF is not set
+CONFIG_NET_VENDOR_CISCO=y
+# CONFIG_ENIC is not set
+CONFIG_NET_VENDOR_CORTINA=y
+# CONFIG_GEMINI_ETHERNET is not set
+CONFIG_NET_VENDOR_DAVICOM=y
+# CONFIG_DM9051 is not set
+CONFIG_DNET=m
+CONFIG_NET_VENDOR_DEC=y
+# CONFIG_NET_TULIP is not set
+CONFIG_NET_VENDOR_DLINK=y
+CONFIG_DL2K=m
+CONFIG_SUNDANCE=m
+# CONFIG_SUNDANCE_MMIO is not set
+CONFIG_NET_VENDOR_EMULEX=y
+# CONFIG_BE2NET is not set
+CONFIG_NET_VENDOR_ENGLEDER=y
+# CONFIG_TSNEP is not set
+CONFIG_NET_VENDOR_EZCHIP=y
+# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
+CONFIG_NET_VENDOR_FUNGIBLE=y
+# CONFIG_FUN_ETH is not set
+CONFIG_NET_VENDOR_GOOGLE=y
+# CONFIG_GVE is not set
+CONFIG_NET_VENDOR_HISILICON=y
+CONFIG_HIX5HD2_GMAC=y
+# CONFIG_HISI_FEMAC is not set
+# CONFIG_HIP04_ETH is not set
+CONFIG_HNS_MDIO=y
+CONFIG_HNS=y
+CONFIG_HNS_DSAF=y
+CONFIG_HNS_ENET=y
+CONFIG_HNS3=y
+CONFIG_HNS3_HCLGE=y
+# CONFIG_HNS3_DCB is not set
+# CONFIG_HNS3_HCLGEVF is not set
+CONFIG_HNS3_ENET=y
+CONFIG_NET_VENDOR_HUAWEI=y
+# CONFIG_HINIC is not set
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_LIBETH=m
+CONFIG_LIBIE=m
+CONFIG_E100=m
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_IGB=m
+CONFIG_IGB_HWMON=y
+CONFIG_IGBVF=m
+CONFIG_IXGBE=m
+CONFIG_IXGBE_HWMON=y
+CONFIG_IXGBE_DCB=y
+CONFIG_IXGBE_IPSEC=y
+CONFIG_IXGBEVF=m
+CONFIG_IXGBEVF_IPSEC=y
+CONFIG_I40E=m
+# CONFIG_I40E_DCB is not set
+CONFIG_IAVF=m
+CONFIG_I40EVF=m
+# CONFIG_ICE is not set
+CONFIG_FM10K=m
+# CONFIG_IGC is not set
+# CONFIG_IDPF is not set
+CONFIG_JME=m
+CONFIG_NET_VENDOR_ADI=y
+CONFIG_ADIN1110=m
+CONFIG_NET_VENDOR_LITEX=y
+CONFIG_LITEX_LITEETH=m
+CONFIG_NET_VENDOR_MARVELL=y
+CONFIG_MVMDIO=m
+CONFIG_SKGE=m
+# CONFIG_SKGE_DEBUG is not set
+CONFIG_SKGE_GENESIS=y
+CONFIG_SKY2=m
+# CONFIG_SKY2_DEBUG is not set
+CONFIG_OCTEONTX2_MBOX=m
+# CONFIG_OCTEONTX2_AF is not set
+CONFIG_OCTEONTX2_PF=m
+CONFIG_OCTEONTX2_VF=m
+# CONFIG_OCTEON_EP is not set
+# CONFIG_OCTEON_EP_VF is not set
+# CONFIG_PRESTERA is not set
+CONFIG_NET_VENDOR_MELLANOX=y
+CONFIG_MLX4_EN=m
+CONFIG_MLX4_EN_DCB=y
+CONFIG_MLX4_CORE=m
+CONFIG_MLX4_DEBUG=y
+CONFIG_MLX4_CORE_GEN2=y
+CONFIG_MLX5_CORE=m
+# CONFIG_MLX5_FPGA is not set
+CONFIG_MLX5_CORE_EN=y
+CONFIG_MLX5_EN_ARFS=y
+CONFIG_MLX5_EN_RXNFC=y
+CONFIG_MLX5_MPFS=y
+CONFIG_MLX5_ESWITCH=y
+CONFIG_MLX5_BRIDGE=y
+CONFIG_MLX5_CORE_EN_DCB=y
+# CONFIG_MLX5_CORE_IPOIB is not set
+# CONFIG_MLX5_MACSEC is not set
+# CONFIG_MLX5_EN_IPSEC is not set
+# CONFIG_MLX5_EN_TLS is not set
+CONFIG_MLX5_SW_STEERING=y
+# CONFIG_MLX5_SF is not set
+# CONFIG_MLX5_DPLL is not set
+# CONFIG_MLXSW_CORE is not set
+# CONFIG_MLXFW is not set
+CONFIG_MLXBF_GIGE=m
+CONFIG_NET_VENDOR_META=y
+CONFIG_NET_VENDOR_MICREL=y
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_KSZ884X_PCI=m
+CONFIG_NET_VENDOR_MICROCHIP=y
+CONFIG_ENC28J60=m
+CONFIG_ENC28J60_WRITEVERIFY=y
+# CONFIG_ENCX24J600 is not set
+# CONFIG_LAN743X is not set
+# CONFIG_LAN966X_SWITCH is not set
+# CONFIG_VCAP is not set
+CONFIG_NET_VENDOR_MICROSEMI=y
+CONFIG_MSCC_OCELOT_SWITCH_LIB=m
+CONFIG_MSCC_OCELOT_SWITCH=m
+CONFIG_NET_VENDOR_MICROSOFT=y
+CONFIG_NET_VENDOR_MYRI=y
+CONFIG_MYRI10GE=m
+# CONFIG_FEALNX is not set
+CONFIG_NET_VENDOR_NI=y
+# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NATSEMI=m
+CONFIG_NS83820=m
+CONFIG_NET_VENDOR_NETERION=y
+# CONFIG_S2IO is not set
+CONFIG_NET_VENDOR_NETRONOME=y
+# CONFIG_NFP is not set
+CONFIG_NET_VENDOR_8390=y
+CONFIG_NE2K_PCI=m
+CONFIG_NET_VENDOR_NVIDIA=y
+CONFIG_FORCEDETH=m
+CONFIG_NET_VENDOR_OKI=y
+CONFIG_ETHOC=m
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+CONFIG_HAMACHI=m
+CONFIG_YELLOWFIN=m
+CONFIG_NET_VENDOR_PENSANDO=y
+CONFIG_IONIC=m
+CONFIG_NET_VENDOR_QLOGIC=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_QLCNIC is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_QED is not set
+CONFIG_NET_VENDOR_BROCADE=y
+CONFIG_BNA=m
+CONFIG_NET_VENDOR_QUALCOMM=y
+CONFIG_QCA7000=m
+# CONFIG_QCA7000_SPI is not set
+CONFIG_QCA7000_UART=m
+CONFIG_QCOM_EMAC=m
+CONFIG_RMNET=m
+CONFIG_NET_VENDOR_RDC=y
+# CONFIG_R6040 is not set
+CONFIG_NET_VENDOR_REALTEK=y
+CONFIG_8139CP=m
+CONFIG_8139TOO=m
+CONFIG_8139TOO_PIO=y
+CONFIG_8139TOO_TUNE_TWISTER=y
+CONFIG_8139TOO_8129=y
+CONFIG_8139_OLD_RX_RESET=y
+CONFIG_R8169=m
+CONFIG_R8169_LEDS=y
+CONFIG_NET_VENDOR_RENESAS=y
+CONFIG_NET_VENDOR_ROCKER=y
+CONFIG_ROCKER=m
+CONFIG_NET_VENDOR_SAMSUNG=y
+# CONFIG_SXGBE_ETH is not set
+CONFIG_NET_VENDOR_SEEQ=y
+CONFIG_NET_VENDOR_SILAN=y
+# CONFIG_SC92031 is not set
+CONFIG_NET_VENDOR_SIS=y
+# CONFIG_SIS900 is not set
+# CONFIG_SIS190 is not set
+CONFIG_NET_VENDOR_SOLARFLARE=y
+# CONFIG_SFC is not set
+# CONFIG_SFC_FALCON is not set
+# CONFIG_SFC_SIENA is not set
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_SMC91X=y
+# CONFIG_EPIC100 is not set
+CONFIG_SMSC911X=y
+# CONFIG_SMSC9420 is not set
+CONFIG_NET_VENDOR_SOCIONEXT=y
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_DWMAC_DWC_QOS_ETH is not set
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_ROCKCHIP=y
+# CONFIG_DWMAC_INTEL_PLAT is not set
+# CONFIG_STMMAC_PCI is not set
+CONFIG_NET_VENDOR_SUN=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NIU is not set
+CONFIG_NET_VENDOR_SYNOPSYS=y
+# CONFIG_DWC_XLGMAC is not set
+CONFIG_NET_VENDOR_TEHUTI=y
+CONFIG_TEHUTI=m
+# CONFIG_TEHUTI_TN40 is not set
+CONFIG_NET_VENDOR_TI=y
+# CONFIG_TI_CPSW_PHY_SEL is not set
+# CONFIG_TLAN is not set
+CONFIG_NET_VENDOR_VERTEXCOM=y
+# CONFIG_MSE102X is not set
+CONFIG_NET_VENDOR_VIA=y
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+CONFIG_NET_VENDOR_WANGXUN=y
+CONFIG_LIBWX=m
+CONFIG_NGBE=m
+# CONFIG_TXGBE is not set
+CONFIG_NET_VENDOR_WIZNET=y
+# CONFIG_WIZNET_W5100 is not set
+# CONFIG_WIZNET_W5300 is not set
+CONFIG_NET_VENDOR_XILINX=y
+CONFIG_XILINX_EMACLITE=m
+CONFIG_XILINX_LL_TEMAC=m
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PHYLINK=y
+CONFIG_PHYLIB=y
+CONFIG_SWPHY=y
+CONFIG_LED_TRIGGER_PHY=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_FIXED_PHY=y
+CONFIG_SFP=m
+
+#
+# MII PHY device drivers
+#
+# CONFIG_AIR_EN8811H_PHY is not set
+CONFIG_AMD_PHY=m
+CONFIG_ADIN_PHY=m
+CONFIG_ADIN1100_PHY=m
+CONFIG_AQUANTIA_PHY=m
+CONFIG_AX88796B_PHY=m
+CONFIG_BROADCOM_PHY=m
+# CONFIG_BCM54140_PHY is not set
+CONFIG_BCM7XXX_PHY=m
+CONFIG_BCM84881_PHY=m
+CONFIG_BCM87XX_PHY=m
+CONFIG_BCM_NET_PHYLIB=m
+CONFIG_BCM_NET_PHYPTP=m
+CONFIG_CICADA_PHY=m
+# CONFIG_CORTINA_PHY is not set
+CONFIG_DAVICOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_LXT_PHY=m
+# CONFIG_INTEL_XWAY_PHY is not set
+CONFIG_LSI_ET1011C_PHY=m
+CONFIG_MARVELL_PHY=m
+CONFIG_MARVELL_10G_PHY=m
+# CONFIG_MARVELL_88Q2XXX_PHY is not set
+CONFIG_MARVELL_88X2222_PHY=m
+CONFIG_MAXLINEAR_GPHY=m
+CONFIG_MEDIATEK_GE_PHY=m
+# CONFIG_MEDIATEK_GE_SOC_PHY is not set
+CONFIG_MICREL_PHY=y
+# CONFIG_MICROCHIP_T1S_PHY is not set
+CONFIG_MICROCHIP_PHY=m
+CONFIG_MICROCHIP_T1_PHY=m
+CONFIG_MICROSEMI_PHY=m
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_NATIONAL_PHY=m
+# CONFIG_NXP_CBTX_PHY is not set
+CONFIG_NXP_C45_TJA11XX_PHY=m
+# CONFIG_NXP_TJA11XX_PHY is not set
+# CONFIG_NCN26000_PHY is not set
+CONFIG_QCOM_NET_PHYLIB=m
+CONFIG_AT803X_PHY=m
+# CONFIG_QCA83XX_PHY is not set
+# CONFIG_QCA808X_PHY is not set
+# CONFIG_QCA807X_PHY is not set
+CONFIG_QSEMI_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_RENESAS_PHY is not set
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_SMSC_PHY=m
+# CONFIG_STE10XP is not set
+# CONFIG_TERANETICS_PHY is not set
+# CONFIG_DP83822_PHY is not set
+CONFIG_DP83TC811_PHY=m
+CONFIG_DP83848_PHY=m
+# CONFIG_DP83867_PHY is not set
+CONFIG_DP83869_PHY=m
+CONFIG_DP83TD510_PHY=m
+# CONFIG_DP83TG720_PHY is not set
+CONFIG_VITESSE_PHY=m
+# CONFIG_XILINX_GMII2RGMII is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PSE_CONTROLLER=y
+CONFIG_PSE_REGULATOR=m
+# CONFIG_PSE_PD692X0 is not set
+# CONFIG_PSE_TPS23881 is not set
+CONFIG_CAN_DEV=m
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_VXCAN=m
+CONFIG_CAN_NETLINK=y
+CONFIG_CAN_CALC_BITTIMING=y
+CONFIG_CAN_RX_OFFLOAD=y
+# CONFIG_CAN_CAN327 is not set
+# CONFIG_CAN_FLEXCAN is not set
+CONFIG_CAN_GRCAN=m
+CONFIG_CAN_KVASER_PCIEFD=m
+CONFIG_CAN_SLCAN=m
+CONFIG_CAN_XILINXCAN=m
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PLATFORM=m
+CONFIG_CAN_C_CAN_PCI=m
+CONFIG_CAN_CC770=m
+CONFIG_CAN_CC770_PLATFORM=m
+# CONFIG_CAN_CTUCANFD_PCI is not set
+# CONFIG_CAN_CTUCANFD_PLATFORM is not set
+# CONFIG_CAN_ESD_402_PCI is not set
+# CONFIG_CAN_IFI_CANFD is not set
+CONFIG_CAN_M_CAN=m
+CONFIG_CAN_M_CAN_PCI=m
+CONFIG_CAN_M_CAN_PLATFORM=m
+CONFIG_CAN_M_CAN_TCAN4X5X=m
+CONFIG_CAN_PEAK_PCIEFD=m
+CONFIG_CAN_SJA1000=m
+CONFIG_CAN_EMS_PCI=m
+CONFIG_CAN_F81601=m
+CONFIG_CAN_KVASER_PCI=m
+CONFIG_CAN_PEAK_PCI=m
+CONFIG_CAN_PEAK_PCIEC=y
+CONFIG_CAN_PLX_PCI=m
+CONFIG_CAN_SJA1000_PLATFORM=m
+CONFIG_CAN_SOFTING=m
+
+#
+# CAN SPI interfaces
+#
+CONFIG_CAN_HI311X=m
+CONFIG_CAN_MCP251X=m
+CONFIG_CAN_MCP251XFD=m
+# CONFIG_CAN_MCP251XFD_SANITY is not set
+# end of CAN SPI interfaces
+
+#
+# CAN USB interfaces
+#
+CONFIG_CAN_8DEV_USB=m
+CONFIG_CAN_EMS_USB=m
+CONFIG_CAN_ESD_USB=m
+CONFIG_CAN_ETAS_ES58X=m
+# CONFIG_CAN_F81604 is not set
+CONFIG_CAN_GS_USB=m
+CONFIG_CAN_KVASER_USB=m
+CONFIG_CAN_MCBA_USB=m
+CONFIG_CAN_PEAK_USB=m
+CONFIG_CAN_UCAN=m
+# end of CAN USB interfaces
+
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_OF_MDIO=y
+CONFIG_ACPI_MDIO=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BCM_UNIMAC=m
+CONFIG_MDIO_CAVIUM=y
+CONFIG_MDIO_GPIO=m
+# CONFIG_MDIO_HISI_FEMAC is not set
+CONFIG_MDIO_I2C=m
+CONFIG_MDIO_MVUSB=m
+CONFIG_MDIO_MSCC_MIIM=m
+# CONFIG_MDIO_OCTEON is not set
+# CONFIG_MDIO_IPQ4019 is not set
+CONFIG_MDIO_IPQ8064=m
+CONFIG_MDIO_REGMAP=m
+CONFIG_MDIO_THUNDER=y
+
+#
+# MDIO Multiplexers
+#
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=m
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+
+#
+# PCS device drivers
+#
+CONFIG_PCS_XPCS=y
+CONFIG_PCS_LYNX=m
+CONFIG_PCS_MTK_LYNXI=m
+# end of PCS device drivers
+
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOATM=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOE_HASH_BITS_1 is not set
+# CONFIG_PPPOE_HASH_BITS_2 is not set
+CONFIG_PPPOE_HASH_BITS_4=y
+# CONFIG_PPPOE_HASH_BITS_8 is not set
+CONFIG_PPPOE_HASH_BITS=4
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_SLIP=m
+CONFIG_SLHC=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_HSO=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_CDC_PHONET=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_USB_NET_CH9200=m
+CONFIG_USB_NET_AQC111=m
+CONFIG_USB_RTL8153_ECM=m
+CONFIG_WLAN=y
+CONFIG_WLAN_VENDOR_ADMTEK=y
+CONFIG_ADM8211=m
+CONFIG_ATH_COMMON=m
+CONFIG_WLAN_VENDOR_ATH=y
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH5K=m
+# CONFIG_ATH5K_DEBUG is not set
+# CONFIG_ATH5K_TRACER is not set
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_BTCOEX_SUPPORT=y
+CONFIG_ATH9K=m
+CONFIG_ATH9K_PCI=y
+CONFIG_ATH9K_AHB=y
+CONFIG_ATH9K_DYNACK=y
+CONFIG_ATH9K_WOW=y
+CONFIG_ATH9K_RFKILL=y
+CONFIG_ATH9K_CHANNEL_CONTEXT=y
+CONFIG_ATH9K_PCOEM=y
+CONFIG_ATH9K_PCI_NO_EEPROM=m
+CONFIG_ATH9K_HTC=m
+# CONFIG_ATH9K_HTC_DEBUGFS is not set
+CONFIG_ATH9K_HWRNG=y
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+CONFIG_CARL9170_HWRNG=y
+CONFIG_ATH6KL=m
+CONFIG_ATH6KL_SDIO=m
+CONFIG_ATH6KL_USB=m
+# CONFIG_ATH6KL_DEBUG is not set
+# CONFIG_ATH6KL_TRACING is not set
+CONFIG_AR5523=m
+CONFIG_WIL6210=m
+CONFIG_WIL6210_ISR_COR=y
+# CONFIG_WIL6210_TRACING is not set
+# CONFIG_WIL6210_DEBUGFS is not set
+CONFIG_ATH10K=m
+CONFIG_ATH10K_CE=y
+CONFIG_ATH10K_PCI=m
+CONFIG_ATH10K_AHB=y
+CONFIG_ATH10K_SDIO=m
+CONFIG_ATH10K_USB=m
+# CONFIG_ATH10K_DEBUG is not set
+# CONFIG_ATH10K_DEBUGFS is not set
+CONFIG_ATH10K_LEDS=y
+# CONFIG_ATH10K_TRACING is not set
+CONFIG_WCN36XX=m
+# CONFIG_WCN36XX_DEBUGFS is not set
+CONFIG_ATH11K=m
+CONFIG_ATH11K_AHB=m
+# CONFIG_ATH11K_PCI is not set
+# CONFIG_ATH11K_DEBUG is not set
+# CONFIG_ATH11K_TRACING is not set
+# CONFIG_ATH12K is not set
+CONFIG_WLAN_VENDOR_ATMEL=y
+CONFIG_AT76C50X_USB=m
+CONFIG_WLAN_VENDOR_BROADCOM=y
+CONFIG_B43=m
+CONFIG_B43_BCMA=y
+CONFIG_B43_SSB=y
+CONFIG_B43_BUSES_BCMA_AND_SSB=y
+# CONFIG_B43_BUSES_BCMA is not set
+# CONFIG_B43_BUSES_SSB is not set
+CONFIG_B43_PCI_AUTOSELECT=y
+CONFIG_B43_PCICORE_AUTOSELECT=y
+CONFIG_B43_SDIO=y
+CONFIG_B43_BCMA_PIO=y
+CONFIG_B43_PIO=y
+CONFIG_B43_PHY_G=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_PHY_LP=y
+CONFIG_B43_PHY_HT=y
+CONFIG_B43_LEDS=y
+CONFIG_B43_HWRNG=y
+# CONFIG_B43_DEBUG is not set
+CONFIG_B43LEGACY=m
+CONFIG_B43LEGACY_PCI_AUTOSELECT=y
+CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
+CONFIG_B43LEGACY_LEDS=y
+CONFIG_B43LEGACY_HWRNG=y
+# CONFIG_B43LEGACY_DEBUG is not set
+CONFIG_B43LEGACY_DMA=y
+CONFIG_B43LEGACY_PIO=y
+CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
+# CONFIG_B43LEGACY_DMA_MODE is not set
+# CONFIG_B43LEGACY_PIO_MODE is not set
+CONFIG_BRCMUTIL=m
+CONFIG_BRCMSMAC=m
+CONFIG_BRCMSMAC_LEDS=y
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_PROTO_MSGBUF=y
+CONFIG_BRCMFMAC_SDIO=y
+CONFIG_BRCMFMAC_USB=y
+CONFIG_BRCMFMAC_PCIE=y
+CONFIG_BRCM_TRACING=y
+# CONFIG_BRCMDBG is not set
+CONFIG_WLAN_VENDOR_INTEL=y
+CONFIG_IPW2100=m
+CONFIG_IPW2100_MONITOR=y
+# CONFIG_IPW2100_DEBUG is not set
+CONFIG_IPW2200=m
+CONFIG_IPW2200_MONITOR=y
+CONFIG_IPW2200_RADIOTAP=y
+CONFIG_IPW2200_PROMISCUOUS=y
+CONFIG_IPW2200_QOS=y
+# CONFIG_IPW2200_DEBUG is not set
+CONFIG_LIBIPW=m
+# CONFIG_LIBIPW_DEBUG is not set
+CONFIG_IWLEGACY=m
+CONFIG_IWL4965=m
+CONFIG_IWL3945=m
+
+#
+# iwl3945 / iwl4965 Debugging Options
+#
+# CONFIG_IWLEGACY_DEBUG is not set
+# end of iwl3945 / iwl4965 Debugging Options
+
+CONFIG_IWLWIFI=m
+CONFIG_IWLWIFI_LEDS=y
+CONFIG_IWLDVM=m
+CONFIG_IWLMVM=m
+CONFIG_IWLWIFI_OPMODE_MODULAR=y
+
+#
+# Debugging Options
+#
+# CONFIG_IWLWIFI_DEBUG is not set
+CONFIG_IWLWIFI_DEVICE_TRACING=y
+# end of Debugging Options
+
+CONFIG_WLAN_VENDOR_INTERSIL=y
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_PCI is not set
+CONFIG_P54_SPI=m
+CONFIG_P54_SPI_DEFAULT_EEPROM=y
+CONFIG_P54_LEDS=y
+CONFIG_WLAN_VENDOR_MARVELL=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+# CONFIG_LIBERTAS_DEBUG is not set
+CONFIG_LIBERTAS_MESH=y
+CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_MWL8K=m
+CONFIG_WLAN_VENDOR_MEDIATEK=y
+CONFIG_MT7601U=m
+CONFIG_MT76_CORE=m
+CONFIG_MT76_LEDS=y
+CONFIG_MT76_USB=m
+CONFIG_MT76_SDIO=m
+CONFIG_MT76x02_LIB=m
+CONFIG_MT76x02_USB=m
+CONFIG_MT76_CONNAC_LIB=m
+CONFIG_MT792x_LIB=m
+CONFIG_MT792x_USB=m
+CONFIG_MT76x0_COMMON=m
+CONFIG_MT76x0U=m
+CONFIG_MT76x0E=m
+CONFIG_MT76x2_COMMON=m
+CONFIG_MT76x2E=m
+CONFIG_MT76x2U=m
+CONFIG_MT7603E=m
+CONFIG_MT7615_COMMON=m
+CONFIG_MT7615E=m
+CONFIG_MT7663_USB_SDIO_COMMON=m
+CONFIG_MT7663U=m
+CONFIG_MT7663S=m
+CONFIG_MT7915E=m
+CONFIG_MT7921_COMMON=m
+CONFIG_MT7921E=m
+CONFIG_MT7921S=m
+CONFIG_MT7921U=m
+CONFIG_MT7996E=m
+CONFIG_MT7925_COMMON=m
+CONFIG_MT7925E=m
+CONFIG_MT7925U=m
+CONFIG_WLAN_VENDOR_MICROCHIP=y
+CONFIG_WILC1000=m
+CONFIG_WILC1000_SDIO=m
+CONFIG_WILC1000_SPI=m
+# CONFIG_WILC1000_HW_OOB_INTR is not set
+CONFIG_WLAN_VENDOR_PURELIFI=y
+# CONFIG_PLFXLC is not set
+CONFIG_WLAN_VENDOR_RALINK=y
+CONFIG_RT2X00=m
+CONFIG_RT2400PCI=m
+CONFIG_RT2500PCI=m
+CONFIG_RT61PCI=m
+CONFIG_RT2800PCI=m
+CONFIG_RT2800PCI_RT33XX=y
+CONFIG_RT2800PCI_RT35XX=y
+CONFIG_RT2800PCI_RT53XX=y
+CONFIG_RT2800PCI_RT3290=y
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2800_LIB_MMIO=m
+CONFIG_RT2X00_LIB_MMIO=m
+CONFIG_RT2X00_LIB_PCI=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_WLAN_VENDOR_REALTEK=y
+CONFIG_RTL8180=m
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+CONFIG_RTL_CARDS=m
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192SE=m
+CONFIG_RTL8192DE=m
+CONFIG_RTL8723AE=m
+CONFIG_RTL8723BE=m
+CONFIG_RTL8188EE=m
+CONFIG_RTL8192EE=m
+CONFIG_RTL8821AE=m
+CONFIG_RTL8192CU=m
+# CONFIG_RTL8192DU is not set
+CONFIG_RTLWIFI=m
+CONFIG_RTLWIFI_PCI=m
+CONFIG_RTLWIFI_USB=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192C_COMMON=m
+CONFIG_RTL8192D_COMMON=m
+CONFIG_RTL8723_COMMON=m
+CONFIG_RTLBTCOEXIST=m
+CONFIG_RTL8XXXU=m
+# CONFIG_RTL8XXXU_UNTESTED is not set
+CONFIG_RTW88=m
+CONFIG_RTW88_CORE=m
+CONFIG_RTW88_PCI=m
+CONFIG_RTW88_USB=m
+CONFIG_RTW88_8822B=m
+CONFIG_RTW88_8822C=m
+CONFIG_RTW88_8723X=m
+CONFIG_RTW88_8723D=m
+CONFIG_RTW88_8821C=m
+CONFIG_RTW88_8822BE=m
+# CONFIG_RTW88_8822BS is not set
+CONFIG_RTW88_8822BU=m
+CONFIG_RTW88_8822CE=m
+# CONFIG_RTW88_8822CS is not set
+CONFIG_RTW88_8822CU=m
+CONFIG_RTW88_8723DE=m
+# CONFIG_RTW88_8723DS is not set
+# CONFIG_RTW88_8723CS is not set
+CONFIG_RTW88_8723DU=m
+CONFIG_RTW88_8821CE=m
+# CONFIG_RTW88_8821CS is not set
+CONFIG_RTW88_8821CU=m
+# CONFIG_RTW88_DEBUG is not set
+# CONFIG_RTW88_DEBUGFS is not set
+CONFIG_RTW89=m
+CONFIG_RTW89_CORE=m
+CONFIG_RTW89_PCI=m
+CONFIG_RTW89_8851B=m
+CONFIG_RTW89_8852A=m
+CONFIG_RTW89_8852B_COMMON=m
+CONFIG_RTW89_8852B=m
+CONFIG_RTW89_8852C=m
+CONFIG_RTW89_8851BE=m
+CONFIG_RTW89_8852AE=m
+CONFIG_RTW89_8852BE=m
+CONFIG_RTW89_8852CE=m
+# CONFIG_RTW89_8922AE is not set
+# CONFIG_RTW89_DEBUGMSG is not set
+# CONFIG_RTW89_DEBUGFS is not set
+CONFIG_WLAN_VENDOR_RSI=y
+CONFIG_RSI_91X=m
+# CONFIG_RSI_DEBUGFS is not set
+CONFIG_RSI_SDIO=m
+CONFIG_RSI_USB=m
+CONFIG_RSI_COEX=y
+CONFIG_WLAN_VENDOR_SILABS=y
+CONFIG_WFX=m
+CONFIG_WLAN_VENDOR_ST=y
+CONFIG_CW1200=m
+CONFIG_CW1200_WLAN_SDIO=m
+CONFIG_CW1200_WLAN_SPI=m
+CONFIG_WLAN_VENDOR_TI=y
+CONFIG_WL1251=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE=m
+CONFIG_WLCORE_SPI=m
+CONFIG_WLCORE_SDIO=m
+# CONFIG_RTL8723DS is not set
+# CONFIG_RTL8822BU is not set
+# CONFIG_RTL8821CU is not set
+# CONFIG_88XXAU is not set
+# CONFIG_RTL8192EU is not set
+# CONFIG_RTL8189FS is not set
+# CONFIG_RTL8189ES is not set
+CONFIG_WLAN_VENDOR_ZYDAS=y
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+CONFIG_WLAN_VENDOR_QUANTENNA=y
+CONFIG_QTNFMAC=m
+CONFIG_QTNFMAC_PCIE=m
+CONFIG_MAC80211_HWSIM=m
+CONFIG_VIRT_WIFI=m
+CONFIG_WAN=y
+CONFIG_HDLC=m
+CONFIG_HDLC_RAW=m
+CONFIG_HDLC_RAW_ETH=m
+# CONFIG_HDLC_CISCO is not set
+# CONFIG_HDLC_FR is not set
+# CONFIG_HDLC_PPP is not set
+# CONFIG_HDLC_X25 is not set
+# CONFIG_FRAMER is not set
+# CONFIG_PCI200SYN is not set
+# CONFIG_WANXL is not set
+# CONFIG_PC300TOO is not set
+# CONFIG_FARSYNC is not set
+# CONFIG_LAPBETHER is not set
+CONFIG_IEEE802154_DRIVERS=m
+CONFIG_IEEE802154_FAKELB=m
+CONFIG_IEEE802154_AT86RF230=m
+CONFIG_IEEE802154_MRF24J40=m
+CONFIG_IEEE802154_CC2520=m
+CONFIG_IEEE802154_ATUSB=m
+CONFIG_IEEE802154_ADF7242=m
+CONFIG_IEEE802154_CA8210=m
+# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
+CONFIG_IEEE802154_MCR20A=m
+CONFIG_IEEE802154_HWSIM=m
+
+#
+# Wireless WAN
+#
+CONFIG_WWAN=m
+CONFIG_WWAN_DEBUGFS=y
+CONFIG_WWAN_HWSIM=m
+CONFIG_MHI_WWAN_CTRL=m
+CONFIG_MHI_WWAN_MBIM=m
+CONFIG_RPMSG_WWAN_CTRL=m
+CONFIG_IOSM=m
+CONFIG_MTK_T7XX=m
+# end of Wireless WAN
+
+CONFIG_XEN_NETDEV_FRONTEND=m
+CONFIG_XEN_NETDEV_BACKEND=m
+CONFIG_VMXNET3=m
+CONFIG_FUJITSU_ES=m
+CONFIG_NETDEVSIM=m
+CONFIG_NET_FAILOVER=y
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_SPARSEKMAP=m
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_VIVALDIFMAP=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KUNIT_TEST is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ADC=m
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_QT1050=m
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=m
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_PINEPHONE is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_OMAP4 is not set
+# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_CROS_EC=y
+# CONFIG_KEYBOARD_CAP11XX is not set
+# CONFIG_KEYBOARD_BCM is not set
+# CONFIG_KEYBOARD_CYPRESS_SF is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_SMBUS=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+CONFIG_MOUSE_SYNAPTICS_I2C=m
+CONFIG_MOUSE_SYNAPTICS_USB=m
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_ANALOG=m
+CONFIG_JOYSTICK_A3D=m
+CONFIG_JOYSTICK_ADC=m
+CONFIG_JOYSTICK_ADI=m
+CONFIG_JOYSTICK_COBRA=m
+CONFIG_JOYSTICK_GF2K=m
+CONFIG_JOYSTICK_GRIP=m
+CONFIG_JOYSTICK_GRIP_MP=m
+CONFIG_JOYSTICK_GUILLEMOT=m
+CONFIG_JOYSTICK_INTERACT=m
+CONFIG_JOYSTICK_SIDEWINDER=m
+CONFIG_JOYSTICK_TMDC=m
+CONFIG_JOYSTICK_IFORCE=m
+CONFIG_JOYSTICK_IFORCE_USB=m
+CONFIG_JOYSTICK_IFORCE_232=m
+CONFIG_JOYSTICK_WARRIOR=m
+CONFIG_JOYSTICK_MAGELLAN=m
+CONFIG_JOYSTICK_SPACEORB=m
+CONFIG_JOYSTICK_SPACEBALL=m
+CONFIG_JOYSTICK_STINGER=m
+CONFIG_JOYSTICK_TWIDJOY=m
+CONFIG_JOYSTICK_ZHENHUA=m
+CONFIG_JOYSTICK_AS5011=m
+CONFIG_JOYSTICK_JOYDUMP=m
+CONFIG_JOYSTICK_XPAD=m
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_JOYSTICK_PSXPAD_SPI=m
+CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
+CONFIG_JOYSTICK_PXRC=m
+CONFIG_JOYSTICK_QWIIC=m
+CONFIG_JOYSTICK_FSIA6B=m
+CONFIG_JOYSTICK_SENSEHAT=m
+# CONFIG_JOYSTICK_SEESAW is not set
+CONFIG_INPUT_TABLET=y
+# CONFIG_TABLET_USB_ACECAD is not set
+# CONFIG_TABLET_USB_AIPTEK is not set
+# CONFIG_TABLET_USB_HANWANG is not set
+# CONFIG_TABLET_USB_KBTAB is not set
+# CONFIG_TABLET_USB_PEGASUS is not set
+# CONFIG_TABLET_SERIAL_WACOM4 is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=m
+CONFIG_TOUCHSCREEN_AD7877=m
+CONFIG_TOUCHSCREEN_AD7879=m
+CONFIG_TOUCHSCREEN_AD7879_I2C=m
+CONFIG_TOUCHSCREEN_AD7879_SPI=m
+CONFIG_TOUCHSCREEN_ADC=m
+CONFIG_TOUCHSCREEN_AR1021_I2C=m
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y
+CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
+CONFIG_TOUCHSCREEN_BU21013=m
+CONFIG_TOUCHSCREEN_BU21029=m
+CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
+CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
+CONFIG_TOUCHSCREEN_CY8CTMA140=m
+CONFIG_TOUCHSCREEN_CY8CTMG110=m
+CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
+CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
+CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
+CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
+CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
+CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
+# CONFIG_TOUCHSCREEN_CYTTSP5 is not set
+CONFIG_TOUCHSCREEN_DYNAPRO=m
+CONFIG_TOUCHSCREEN_HAMPSHIRE=m
+CONFIG_TOUCHSCREEN_EETI=m
+CONFIG_TOUCHSCREEN_EGALAX=m
+CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
+CONFIG_TOUCHSCREEN_EXC3000=m
+CONFIG_TOUCHSCREEN_FUJITSU=m
+CONFIG_TOUCHSCREEN_GOODIX=m
+# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set
+# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set
+CONFIG_TOUCHSCREEN_HIDEEP=m
+CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
+# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set
+CONFIG_TOUCHSCREEN_ILI210X=m
+CONFIG_TOUCHSCREEN_ILITEK=m
+CONFIG_TOUCHSCREEN_S6SY761=m
+CONFIG_TOUCHSCREEN_GUNZE=m
+CONFIG_TOUCHSCREEN_EKTF2127=m
+CONFIG_TOUCHSCREEN_ELAN=m
+CONFIG_TOUCHSCREEN_ELO=m
+CONFIG_TOUCHSCREEN_WACOM_W8001=m
+CONFIG_TOUCHSCREEN_WACOM_I2C=m
+CONFIG_TOUCHSCREEN_MAX11801=m
+CONFIG_TOUCHSCREEN_MCS5000=m
+CONFIG_TOUCHSCREEN_MMS114=m
+CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
+CONFIG_TOUCHSCREEN_MSG2638=m
+CONFIG_TOUCHSCREEN_MTOUCH=m
+# CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS is not set
+CONFIG_TOUCHSCREEN_IMAGIS=m
+CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
+CONFIG_TOUCHSCREEN_INEXIO=m
+CONFIG_TOUCHSCREEN_PENMOUNT=m
+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
+CONFIG_TOUCHSCREEN_TOUCHWIN=m
+CONFIG_TOUCHSCREEN_PIXCIR=m
+CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
+CONFIG_TOUCHSCREEN_USB_EGALAX=y
+CONFIG_TOUCHSCREEN_USB_PANJIT=y
+CONFIG_TOUCHSCREEN_USB_3M=y
+CONFIG_TOUCHSCREEN_USB_ITM=y
+CONFIG_TOUCHSCREEN_USB_ETURBO=y
+CONFIG_TOUCHSCREEN_USB_GUNZE=y
+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
+CONFIG_TOUCHSCREEN_USB_GOTOP=y
+CONFIG_TOUCHSCREEN_USB_JASTEC=y
+CONFIG_TOUCHSCREEN_USB_ELO=y
+CONFIG_TOUCHSCREEN_USB_E2I=y
+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
+CONFIG_TOUCHSCREEN_USB_NEXIO=y
+CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
+CONFIG_TOUCHSCREEN_TOUCHIT213=m
+CONFIG_TOUCHSCREEN_TSC_SERIO=m
+CONFIG_TOUCHSCREEN_TSC200X_CORE=m
+CONFIG_TOUCHSCREEN_TSC2004=m
+CONFIG_TOUCHSCREEN_TSC2005=m
+CONFIG_TOUCHSCREEN_TSC2007=m
+CONFIG_TOUCHSCREEN_TSC2007_IIO=y
+CONFIG_TOUCHSCREEN_RM_TS=m
+CONFIG_TOUCHSCREEN_SILEAD=m
+CONFIG_TOUCHSCREEN_SIS_I2C=m
+CONFIG_TOUCHSCREEN_ST1232=m
+CONFIG_TOUCHSCREEN_STMFTS=m
+CONFIG_TOUCHSCREEN_SUR40=m
+CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
+CONFIG_TOUCHSCREEN_SX8654=m
+CONFIG_TOUCHSCREEN_TPS6507X=m
+CONFIG_TOUCHSCREEN_ZET6223=m
+CONFIG_TOUCHSCREEN_ZFORCE=m
+CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
+CONFIG_TOUCHSCREEN_ROHM_BU21023=m
+CONFIG_TOUCHSCREEN_IQS5XX=m
+# CONFIG_TOUCHSCREEN_IQS7211 is not set
+CONFIG_TOUCHSCREEN_ZINITIX=m
+# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_E3X0_BUTTON is not set
+# CONFIG_INPUT_MMA8450 is not set
+CONFIG_INPUT_GPIO_BEEPER=m
+CONFIG_INPUT_GPIO_DECODER=m
+CONFIG_INPUT_GPIO_VIBRA=m
+CONFIG_INPUT_ATI_REMOTE2=m
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_REGULATOR_HAPTIC is not set
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_PWM_VIBRA is not set
+CONFIG_INPUT_RK805_PWRKEY=m
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+CONFIG_INPUT_DA7280_HAPTICS=m
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_IBM_PANEL is not set
+# CONFIG_INPUT_IMS_PCU is not set
+# CONFIG_INPUT_IQS269A is not set
+CONFIG_INPUT_IQS626A=m
+CONFIG_INPUT_IQS7222=m
+# CONFIG_INPUT_CMA3000 is not set
+CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
+CONFIG_INPUT_SOC_BUTTON_ARRAY=m
+# CONFIG_INPUT_DRV260X_HAPTICS is not set
+# CONFIG_INPUT_DRV2665_HAPTICS is not set
+# CONFIG_INPUT_DRV2667_HAPTICS is not set
+CONFIG_RMI4_CORE=m
+CONFIG_RMI4_I2C=m
+CONFIG_RMI4_SPI=m
+CONFIG_RMI4_SMB=m
+CONFIG_RMI4_F03=y
+CONFIG_RMI4_F03_SERIO=m
+CONFIG_RMI4_2D_SENSOR=y
+CONFIG_RMI4_F11=y
+CONFIG_RMI4_F12=y
+CONFIG_RMI4_F30=y
+CONFIG_RMI4_F34=y
+CONFIG_RMI4_F3A=y
+CONFIG_RMI4_F54=y
+CONFIG_RMI4_F55=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_AMBAKMI=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+CONFIG_SERIO_ALTERA_PS2=m
+# CONFIG_SERIO_PS2MULT is not set
+CONFIG_SERIO_ARC_PS2=m
+# CONFIG_SERIO_APBPS2 is not set
+# CONFIG_SERIO_GPIO_PS2 is not set
+# CONFIG_USERIO is not set
+CONFIG_GAMEPORT=m
+# CONFIG_GAMEPORT_EMU10K1 is not set
+# CONFIG_GAMEPORT_FM801 is not set
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_LEGACY_TIOCSTI=y
+CONFIG_LDISC_AUTOLOAD=y
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_16550A_VARIANTS=y
+CONFIG_SERIAL_8250_FINTEK=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PCI=m
+CONFIG_SERIAL_8250_EXAR=m
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_RUNTIME_UARTS=8
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_PCI1XXXX is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_SERIAL_8250_RT288X is not set
+CONFIG_SERIAL_8250_PERICOM=y
+CONFIG_SERIAL_OF_PLATFORM=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_AMBA_PL010=y
+CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_JSM=m
+CONFIG_SERIAL_SIFIVE=m
+CONFIG_SERIAL_SCCNXP=y
+CONFIG_SERIAL_SCCNXP_CONSOLE=y
+# CONFIG_SERIAL_SC16IS7XX is not set
+CONFIG_SERIAL_ALTERA_JTAGUART=m
+CONFIG_SERIAL_ALTERA_UART=m
+CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
+CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_ARC=m
+CONFIG_SERIAL_ARC_NR_PORTS=1
+CONFIG_SERIAL_RP2=m
+CONFIG_SERIAL_RP2_NR_UARTS=32
+CONFIG_SERIAL_FSL_LPUART=m
+CONFIG_SERIAL_FSL_LINFLEXUART=m
+CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
+CONFIG_SERIAL_SPRD=m
+CONFIG_SERIAL_LITEUART=m
+CONFIG_SERIAL_LITEUART_MAX_PORTS=1
+# end of Serial drivers
+
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_MOXA_INTELLIO=m
+CONFIG_MOXA_SMARTIO=m
+CONFIG_N_HDLC=m
+CONFIG_N_GSM=m
+CONFIG_NOZOMI=m
+CONFIG_NULL_TTY=m
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_IRQ=y
+CONFIG_HVC_XEN=y
+CONFIG_HVC_XEN_FRONTEND=y
+# CONFIG_HVC_DCC is not set
+CONFIG_RPMSG_TTY=m
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+# CONFIG_TTY_PRINTK is not set
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_IPMI_DMI_DECODE=y
+CONFIG_IPMI_PLAT_DATA=y
+# CONFIG_IPMI_PANIC_EVENT is not set
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+# CONFIG_IPMI_SSIF is not set
+CONFIG_IPMI_IPMB=m
+# CONFIG_IPMI_WATCHDOG is not set
+# CONFIG_IPMI_POWEROFF is not set
+# CONFIG_SSIF_IPMI_BMC is not set
+# CONFIG_IPMB_DEVICE_INTERFACE is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+# CONFIG_HW_RANDOM_BA431 is not set
+CONFIG_HW_RANDOM_VIRTIO=m
+CONFIG_HW_RANDOM_OPTEE=m
+# CONFIG_HW_RANDOM_CCTRNG is not set
+# CONFIG_HW_RANDOM_XIPHERA is not set
+CONFIG_HW_RANDOM_ROCKCHIP=m
+CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
+CONFIG_HW_RANDOM_CN10K=y
+# CONFIG_APPLICOM is not set
+CONFIG_DEVMEM=y
+CONFIG_DEVPORT=y
+CONFIG_TCG_TPM=y
+# CONFIG_TCG_TPM2_HMAC is not set
+CONFIG_HW_RANDOM_TPM=y
+# CONFIG_TCG_TIS is not set
+# CONFIG_TCG_TIS_SPI is not set
+# CONFIG_TCG_TIS_I2C is not set
+CONFIG_TCG_TIS_I2C_CR50=m
+# CONFIG_TCG_TIS_I2C_ATMEL is not set
+CONFIG_TCG_TIS_I2C_INFINEON=y
+# CONFIG_TCG_TIS_I2C_NUVOTON is not set
+# CONFIG_TCG_ATMEL is not set
+# CONFIG_TCG_INFINEON is not set
+# CONFIG_TCG_XEN is not set
+CONFIG_TCG_CRB=y
+# CONFIG_TCG_VTPM_PROXY is not set
+# CONFIG_TCG_FTPM_TEE is not set
+# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
+# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
+CONFIG_XILLYBUS_CLASS=m
+# CONFIG_XILLYBUS is not set
+CONFIG_XILLYUSB=m
+# end of Character devices
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+CONFIG_I2C_ARB_GPIO_CHALLENGE=m
+CONFIG_I2C_MUX_GPIO=m
+CONFIG_I2C_MUX_GPMUX=m
+CONFIG_I2C_MUX_LTC4306=m
+CONFIG_I2C_MUX_PCA9541=m
+CONFIG_I2C_MUX_PCA954x=m
+CONFIG_I2C_MUX_PINCTRL=m
+CONFIG_I2C_MUX_REG=m
+CONFIG_I2C_DEMUX_PINCTRL=m
+CONFIG_I2C_MUX_MLXCPLD=m
+# end of Multiplexer I2C Chip support
+
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_SMBUS=m
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_ALGOPCA=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+CONFIG_I2C_CCGX_UCSI=m
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_AMD_MP2 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_NVIDIA_GPU is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_ZHAOXIN is not set
+
+#
+# ACPI drivers
+#
+CONFIG_I2C_SCMI=m
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_CADENCE=m
+CONFIG_I2C_CBUS_GPIO=m
+CONFIG_I2C_DESIGNWARE_CORE=y
+# CONFIG_I2C_DESIGNWARE_SLAVE is not set
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_DESIGNWARE_PCI=m
+CONFIG_I2C_EMEV2=m
+CONFIG_I2C_GPIO=m
+CONFIG_I2C_GPIO_FAULT_INJECTOR=y
+CONFIG_I2C_HISI=m
+# CONFIG_I2C_NOMADIK is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PCA_PLATFORM=m
+CONFIG_I2C_RK3X=y
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_THUNDERX is not set
+CONFIG_I2C_XILINX=m
+
+#
+# External I2C/SMBus adapter drivers
+#
+CONFIG_I2C_DIOLAN_U2C=m
+CONFIG_I2C_CP2615=m
+CONFIG_I2C_PCI1XXXX=m
+CONFIG_I2C_ROBOTFUZZ_OSIF=m
+CONFIG_I2C_TAOS_EVM=m
+CONFIG_I2C_TINY_USB=m
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_MLXCPLD is not set
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_VIRTIO=m
+# end of I2C Hardware Bus support
+
+CONFIG_I2C_STUB=m
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=m
+CONFIG_I2C_SLAVE_TESTUNIT=m
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# end of I2C support
+
+CONFIG_I3C=m
+CONFIG_CDNS_I3C_MASTER=m
+CONFIG_DW_I3C_MASTER=m
+CONFIG_SVC_I3C_MASTER=m
+CONFIG_MIPI_I3C_HCI=m
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ALTERA=m
+CONFIG_SPI_ALTERA_CORE=m
+CONFIG_SPI_AXI_SPI_ENGINE=m
+CONFIG_SPI_BITBANG=m
+CONFIG_SPI_CADENCE=m
+CONFIG_SPI_CADENCE_QUADSPI=y
+CONFIG_SPI_CADENCE_XSPI=m
+# CONFIG_SPI_CH341 is not set
+CONFIG_SPI_DESIGNWARE=m
+# CONFIG_SPI_DW_DMA is not set
+CONFIG_SPI_DW_PCI=m
+CONFIG_SPI_DW_MMIO=m
+CONFIG_SPI_HISI_KUNPENG=m
+CONFIG_SPI_HISI_SFC_V3XX=m
+CONFIG_SPI_GPIO=m
+CONFIG_SPI_FSL_LIB=m
+CONFIG_SPI_FSL_SPI=m
+CONFIG_SPI_MICROCHIP_CORE=m
+CONFIG_SPI_MICROCHIP_CORE_QSPI=m
+CONFIG_SPI_OC_TINY=m
+# CONFIG_SPI_PCI1XXXX is not set
+CONFIG_SPI_PL022=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_ROCKCHIP_SFC=y
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SIFIVE is not set
+# CONFIG_SPI_SN_F_OSPI is not set
+CONFIG_SPI_MXIC=m
+# CONFIG_SPI_THUNDERX is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+# CONFIG_SPI_AMD is not set
+
+#
+# SPI Multiplexer support
+#
+CONFIG_SPI_MUX=m
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_LOOPBACK_TEST=m
+CONFIG_SPI_TLE62X0=m
+CONFIG_SPI_SLAVE=y
+CONFIG_SPI_SLAVE_TIME=m
+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+# CONFIG_HSI is not set
+CONFIG_PPS=y
+# CONFIG_PPS_DEBUG is not set
+
+#
+# PPS clients support
+#
+# CONFIG_PPS_CLIENT_KTIMER is not set
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_GPIO=m
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_DP83640_PHY=m
+CONFIG_PTP_1588_CLOCK_INES=m
+CONFIG_PTP_1588_CLOCK_KVM=m
+CONFIG_PTP_1588_CLOCK_IDT82P33=m
+CONFIG_PTP_1588_CLOCK_IDTCM=m
+# CONFIG_PTP_1588_CLOCK_FC3W is not set
+# CONFIG_PTP_1588_CLOCK_MOCK is not set
+CONFIG_PTP_1588_CLOCK_OCP=m
+# end of PTP clock support
+
+CONFIG_PINCTRL=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_PINMUX=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_PINCONF=y
+CONFIG_GENERIC_PINCONF=y
+# CONFIG_DEBUG_PINCTRL is not set
+# CONFIG_PINCTRL_AMD is not set
+# CONFIG_PINCTRL_AW9523 is not set
+CONFIG_PINCTRL_CY8C95X0=m
+# CONFIG_PINCTRL_MCP23S08 is not set
+# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+CONFIG_PINCTRL_RK805=m
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SCMI is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_STMFX=m
+CONFIG_PINCTRL_SX150X=y
+# CONFIG_PINCTRL_IMX_SCMI is not set
+
+#
+# Renesas pinctrl drivers
+#
+# end of Renesas pinctrl drivers
+
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_FASTPATH_LIMIT=512
+CONFIG_OF_GPIO=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_OF_GPIO_MM_GPIOCHIP=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_REGMAP=m
+CONFIG_GPIO_MAX730X=m
+CONFIG_GPIO_IDIO_16=m
+
+#
+# Memory mapped GPIO drivers
+#
+CONFIG_GPIO_74XX_MMIO=m
+CONFIG_GPIO_ALTERA=m
+# CONFIG_GPIO_AMDPT is not set
+CONFIG_GPIO_CADENCE=m
+CONFIG_GPIO_DWAPB=m
+CONFIG_GPIO_EXAR=m
+# CONFIG_GPIO_FTGPIO010 is not set
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_GRGPIO=m
+CONFIG_GPIO_HISI=m
+CONFIG_GPIO_HLWD=m
+CONFIG_GPIO_LOGICVC=m
+CONFIG_GPIO_MB86S7X=m
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_ROCKCHIP=y
+# CONFIG_GPIO_SIFIVE is not set
+CONFIG_GPIO_SYSCON=y
+CONFIG_GPIO_XGENE=y
+CONFIG_GPIO_XILINX=y
+CONFIG_GPIO_AMD_FCH=m
+# end of Memory mapped GPIO drivers
+
+#
+# I2C GPIO expanders
+#
+CONFIG_GPIO_ADNP=m
+# CONFIG_GPIO_FXL6408 is not set
+# CONFIG_GPIO_DS4520 is not set
+CONFIG_GPIO_GW_PLD=m
+CONFIG_GPIO_MAX7300=m
+CONFIG_GPIO_MAX732X=m
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PCA9570=m
+CONFIG_GPIO_PCF857X=m
+CONFIG_GPIO_TPIC2810=m
+# end of I2C GPIO expanders
+
+#
+# MFD GPIO expanders
+#
+# CONFIG_GPIO_CROS_EC is not set
+# end of MFD GPIO expanders
+
+#
+# PCI GPIO expanders
+#
+CONFIG_GPIO_PCI_IDIO_16=m
+CONFIG_GPIO_PCIE_IDIO_24=m
+CONFIG_GPIO_RDC321X=m
+# end of PCI GPIO expanders
+
+#
+# SPI GPIO expanders
+#
+CONFIG_GPIO_74X164=m
+CONFIG_GPIO_MAX3191X=m
+CONFIG_GPIO_MAX7301=m
+CONFIG_GPIO_MC33880=m
+CONFIG_GPIO_PISOSR=m
+CONFIG_GPIO_XRA1403=m
+# end of SPI GPIO expanders
+
+#
+# USB GPIO expanders
+#
+# end of USB GPIO expanders
+
+#
+# Virtual GPIO drivers
+#
+CONFIG_GPIO_AGGREGATOR=m
+# CONFIG_GPIO_LATCH is not set
+CONFIG_GPIO_MOCKUP=m
+CONFIG_GPIO_VIRTIO=m
+# CONFIG_GPIO_SIM is not set
+# end of Virtual GPIO drivers
+
+#
+# GPIO Debugging utilities
+#
+# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set
+# CONFIG_GPIO_VIRTUSER is not set
+# end of GPIO Debugging utilities
+
+CONFIG_W1=m
+CONFIG_W1_CON=y
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_AMD_AXI is not set
+CONFIG_W1_MASTER_MATROX=m
+CONFIG_W1_MASTER_DS2490=m
+CONFIG_W1_MASTER_DS2482=m
+CONFIG_W1_MASTER_GPIO=m
+CONFIG_W1_MASTER_SGI=m
+# CONFIG_W1_MASTER_UART is not set
+# end of 1-wire Bus Masters
+
+#
+# 1-wire Slaves
+#
+CONFIG_W1_SLAVE_THERM=m
+CONFIG_W1_SLAVE_SMEM=m
+CONFIG_W1_SLAVE_DS2405=m
+CONFIG_W1_SLAVE_DS2408=m
+CONFIG_W1_SLAVE_DS2408_READBACK=y
+CONFIG_W1_SLAVE_DS2413=m
+CONFIG_W1_SLAVE_DS2406=m
+CONFIG_W1_SLAVE_DS2423=m
+CONFIG_W1_SLAVE_DS2805=m
+CONFIG_W1_SLAVE_DS2430=m
+CONFIG_W1_SLAVE_DS2431=m
+CONFIG_W1_SLAVE_DS2433=m
+# CONFIG_W1_SLAVE_DS2433_CRC is not set
+CONFIG_W1_SLAVE_DS2438=m
+CONFIG_W1_SLAVE_DS250X=m
+CONFIG_W1_SLAVE_DS2780=m
+CONFIG_W1_SLAVE_DS2781=m
+CONFIG_W1_SLAVE_DS28E04=m
+CONFIG_W1_SLAVE_DS28E17=m
+# end of 1-wire Slaves
+
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+# CONFIG_POWER_RESET_LTC2952 is not set
+CONFIG_POWER_RESET_REGULATOR=y
+CONFIG_POWER_RESET_RESTART=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_REBOOT_MODE=y
+CONFIG_SYSCON_REBOOT_MODE=y
+# CONFIG_NVMEM_REBOOT_MODE is not set
+# CONFIG_POWER_SEQUENCING is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_GENERIC_ADC_BATTERY=m
+# CONFIG_IP5XXX_POWER is not set
+# CONFIG_TEST_POWER is not set
+CONFIG_CHARGER_ADP5061=m
+CONFIG_BATTERY_CW2015=m
+CONFIG_BATTERY_DS2760=m
+CONFIG_BATTERY_DS2780=m
+CONFIG_BATTERY_DS2781=m
+CONFIG_BATTERY_DS2782=m
+# CONFIG_BATTERY_SAMSUNG_SDI is not set
+CONFIG_BATTERY_SBS=m
+CONFIG_CHARGER_SBS=m
+CONFIG_MANAGER_SBS=m
+CONFIG_BATTERY_BQ27XXX=m
+CONFIG_BATTERY_BQ27XXX_I2C=m
+CONFIG_BATTERY_BQ27XXX_HDQ=m
+# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
+CONFIG_BATTERY_MAX17040=m
+CONFIG_BATTERY_MAX17042=m
+# CONFIG_BATTERY_MAX1720X is not set
+CONFIG_BATTERY_MAX1721X=m
+CONFIG_CHARGER_ISP1704=m
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+CONFIG_CHARGER_GPIO=m
+# CONFIG_CHARGER_MANAGER is not set
+CONFIG_CHARGER_LT3651=m
+CONFIG_CHARGER_LTC4162L=m
+CONFIG_CHARGER_DETECTOR_MAX14656=m
+# CONFIG_CHARGER_MAX77976 is not set
+# CONFIG_CHARGER_MT6370 is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24190 is not set
+# CONFIG_CHARGER_BQ24257 is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_BQ2515X is not set
+# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_BQ25980 is not set
+CONFIG_CHARGER_BQ256XX=m
+# CONFIG_CHARGER_RK817 is not set
+CONFIG_CHARGER_SMB347=m
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+CONFIG_BATTERY_GOLDFISH=m
+CONFIG_BATTERY_RT5033=m
+# CONFIG_CHARGER_RT9455 is not set
+# CONFIG_CHARGER_RT9467 is not set
+# CONFIG_CHARGER_RT9471 is not set
+# CONFIG_CHARGER_CROS_USBPD is not set
+CONFIG_CHARGER_CROS_PCHG=m
+CONFIG_CHARGER_CROS_CONTROL=m
+CONFIG_CHARGER_UCS1002=m
+# CONFIG_CHARGER_BD99954 is not set
+# CONFIG_BATTERY_UG3105 is not set
+# CONFIG_FUEL_GAUGE_MM8013 is not set
+CONFIG_HWMON=y
+CONFIG_HWMON_VID=m
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+CONFIG_SENSORS_AD7314=m
+CONFIG_SENSORS_AD7414=m
+CONFIG_SENSORS_AD7418=m
+CONFIG_SENSORS_ADM1025=m
+CONFIG_SENSORS_ADM1026=m
+CONFIG_SENSORS_ADM1029=m
+CONFIG_SENSORS_ADM1031=m
+CONFIG_SENSORS_ADM1177=m
+CONFIG_SENSORS_ADM9240=m
+CONFIG_SENSORS_ADT7X10=m
+CONFIG_SENSORS_ADT7310=m
+CONFIG_SENSORS_ADT7410=m
+CONFIG_SENSORS_ADT7411=m
+CONFIG_SENSORS_ADT7462=m
+CONFIG_SENSORS_ADT7470=m
+CONFIG_SENSORS_ADT7475=m
+CONFIG_SENSORS_AHT10=m
+CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
+CONFIG_SENSORS_AS370=m
+CONFIG_SENSORS_ASC7621=m
+# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set
+CONFIG_SENSORS_AXI_FAN_CONTROL=m
+CONFIG_SENSORS_ARM_SCMI=m
+CONFIG_SENSORS_ARM_SCPI=m
+CONFIG_SENSORS_ATXP1=m
+# CONFIG_SENSORS_CHIPCAP2 is not set
+# CONFIG_SENSORS_CORSAIR_CPRO is not set
+CONFIG_SENSORS_CORSAIR_PSU=m
+CONFIG_SENSORS_CROS_EC=y
+CONFIG_SENSORS_DRIVETEMP=m
+CONFIG_SENSORS_DS620=m
+CONFIG_SENSORS_DS1621=m
+CONFIG_SENSORS_I5K_AMB=m
+CONFIG_SENSORS_F71805F=m
+CONFIG_SENSORS_F71882FG=m
+CONFIG_SENSORS_F75375S=m
+CONFIG_SENSORS_FTSTEUTATES=m
+# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set
+CONFIG_SENSORS_GL518SM=m
+CONFIG_SENSORS_GL520SM=m
+CONFIG_SENSORS_G760A=m
+CONFIG_SENSORS_G762=m
+CONFIG_SENSORS_GPIO_FAN=m
+CONFIG_SENSORS_HIH6130=m
+# CONFIG_SENSORS_HS3001 is not set
+CONFIG_SENSORS_IBMAEM=m
+CONFIG_SENSORS_IBMPEX=m
+CONFIG_SENSORS_IIO_HWMON=m
+CONFIG_SENSORS_IT87=m
+CONFIG_SENSORS_JC42=m
+# CONFIG_SENSORS_POWERZ is not set
+CONFIG_SENSORS_POWR1220=m
+CONFIG_SENSORS_LINEAGE=m
+CONFIG_SENSORS_LTC2945=m
+CONFIG_SENSORS_LTC2947=m
+CONFIG_SENSORS_LTC2947_I2C=m
+CONFIG_SENSORS_LTC2947_SPI=m
+CONFIG_SENSORS_LTC2990=m
+# CONFIG_SENSORS_LTC2991 is not set
+CONFIG_SENSORS_LTC2992=m
+CONFIG_SENSORS_LTC4151=m
+CONFIG_SENSORS_LTC4215=m
+CONFIG_SENSORS_LTC4222=m
+CONFIG_SENSORS_LTC4245=m
+CONFIG_SENSORS_LTC4260=m
+CONFIG_SENSORS_LTC4261=m
+# CONFIG_SENSORS_LTC4282 is not set
+CONFIG_SENSORS_MAX1111=m
+CONFIG_SENSORS_MAX127=m
+CONFIG_SENSORS_MAX16065=m
+CONFIG_SENSORS_MAX1619=m
+CONFIG_SENSORS_MAX1668=m
+CONFIG_SENSORS_MAX197=m
+CONFIG_SENSORS_MAX31722=m
+CONFIG_SENSORS_MAX31730=m
+CONFIG_SENSORS_MAX31760=m
+# CONFIG_MAX31827 is not set
+CONFIG_SENSORS_MAX6620=m
+CONFIG_SENSORS_MAX6621=m
+CONFIG_SENSORS_MAX6639=m
+CONFIG_SENSORS_MAX6650=m
+CONFIG_SENSORS_MAX6697=m
+CONFIG_SENSORS_MAX31790=m
+# CONFIG_SENSORS_MC34VR500 is not set
+CONFIG_SENSORS_MCP3021=m
+CONFIG_SENSORS_TC654=m
+CONFIG_SENSORS_TPS23861=m
+# CONFIG_SENSORS_MR75203 is not set
+CONFIG_SENSORS_ADCXX=m
+CONFIG_SENSORS_LM63=m
+CONFIG_SENSORS_LM70=m
+CONFIG_SENSORS_LM73=m
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM77=m
+CONFIG_SENSORS_LM78=m
+CONFIG_SENSORS_LM80=m
+CONFIG_SENSORS_LM83=m
+CONFIG_SENSORS_LM85=m
+CONFIG_SENSORS_LM87=m
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_LM92=m
+CONFIG_SENSORS_LM93=m
+CONFIG_SENSORS_LM95234=m
+CONFIG_SENSORS_LM95241=m
+CONFIG_SENSORS_LM95245=m
+CONFIG_SENSORS_PC87360=m
+CONFIG_SENSORS_PC87427=m
+CONFIG_SENSORS_NTC_THERMISTOR=m
+CONFIG_SENSORS_NCT6683=m
+CONFIG_SENSORS_NCT6775_CORE=m
+CONFIG_SENSORS_NCT6775=m
+CONFIG_SENSORS_NCT6775_I2C=m
+CONFIG_SENSORS_NCT7802=m
+CONFIG_SENSORS_NCT7904=m
+CONFIG_SENSORS_NPCM7XX=m
+CONFIG_SENSORS_NZXT_KRAKEN2=m
+# CONFIG_SENSORS_NZXT_KRAKEN3 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
+CONFIG_SENSORS_OCC_P8_I2C=m
+CONFIG_SENSORS_OCC=m
+CONFIG_SENSORS_PCF8591=m
+CONFIG_PMBUS=m
+CONFIG_SENSORS_PMBUS=m
+# CONFIG_SENSORS_ACBEL_FSG032 is not set
+# CONFIG_SENSORS_ADM1266 is not set
+CONFIG_SENSORS_ADM1275=m
+# CONFIG_SENSORS_ADP1050 is not set
+CONFIG_SENSORS_BEL_PFE=m
+CONFIG_SENSORS_BPA_RS600=m
+# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
+CONFIG_SENSORS_FSP_3Y=m
+CONFIG_SENSORS_IBM_CFFPS=m
+CONFIG_SENSORS_DPS920AB=m
+CONFIG_SENSORS_INSPUR_IPSPS=m
+CONFIG_SENSORS_IR35221=m
+CONFIG_SENSORS_IR36021=m
+CONFIG_SENSORS_IR38064=m
+# CONFIG_SENSORS_IR38064_REGULATOR is not set
+CONFIG_SENSORS_IRPS5401=m
+CONFIG_SENSORS_ISL68137=m
+CONFIG_SENSORS_LM25066=m
+# CONFIG_SENSORS_LM25066_REGULATOR is not set
+CONFIG_SENSORS_LT7182S=m
+CONFIG_SENSORS_LTC2978=m
+CONFIG_SENSORS_LTC2978_REGULATOR=y
+CONFIG_SENSORS_LTC3815=m
+# CONFIG_SENSORS_LTC4286 is not set
+CONFIG_SENSORS_MAX15301=m
+CONFIG_SENSORS_MAX16064=m
+CONFIG_SENSORS_MAX16601=m
+CONFIG_SENSORS_MAX20730=m
+CONFIG_SENSORS_MAX20751=m
+CONFIG_SENSORS_MAX31785=m
+CONFIG_SENSORS_MAX34440=m
+CONFIG_SENSORS_MAX8688=m
+# CONFIG_SENSORS_MP2856 is not set
+CONFIG_SENSORS_MP2888=m
+# CONFIG_SENSORS_MP2891 is not set
+# CONFIG_SENSORS_MP2975 is not set
+# CONFIG_SENSORS_MP2993 is not set
+# CONFIG_SENSORS_MP5023 is not set
+# CONFIG_SENSORS_MP5920 is not set
+# CONFIG_SENSORS_MP5990 is not set
+# CONFIG_SENSORS_MP9941 is not set
+# CONFIG_SENSORS_MPQ7932 is not set
+# CONFIG_SENSORS_MPQ8785 is not set
+CONFIG_SENSORS_PIM4328=m
+# CONFIG_SENSORS_PLI1209BC is not set
+CONFIG_SENSORS_PM6764TR=m
+CONFIG_SENSORS_PXE1610=m
+CONFIG_SENSORS_Q54SJ108A2=m
+CONFIG_SENSORS_STPDDC60=m
+# CONFIG_SENSORS_TDA38640 is not set
+CONFIG_SENSORS_TPS40422=m
+CONFIG_SENSORS_TPS53679=m
+CONFIG_SENSORS_TPS546D24=m
+CONFIG_SENSORS_UCD9000=m
+CONFIG_SENSORS_UCD9200=m
+# CONFIG_SENSORS_XDP710 is not set
+CONFIG_SENSORS_XDPE152=m
+CONFIG_SENSORS_XDPE122=m
+# CONFIG_SENSORS_XDPE122_REGULATOR is not set
+CONFIG_SENSORS_ZL6100=m
+# CONFIG_SENSORS_PT5161L is not set
+CONFIG_SENSORS_PWM_FAN=m
+CONFIG_SENSORS_SBTSI=m
+CONFIG_SENSORS_SBRMI=m
+CONFIG_SENSORS_SHT15=m
+CONFIG_SENSORS_SHT21=m
+CONFIG_SENSORS_SHT3x=m
+CONFIG_SENSORS_SHT4x=m
+CONFIG_SENSORS_SHTC1=m
+CONFIG_SENSORS_SIS5595=m
+CONFIG_SENSORS_DME1737=m
+CONFIG_SENSORS_EMC1403=m
+CONFIG_SENSORS_EMC2103=m
+CONFIG_SENSORS_EMC2305=m
+CONFIG_SENSORS_EMC6W201=m
+CONFIG_SENSORS_SMSC47M1=m
+CONFIG_SENSORS_SMSC47M192=m
+CONFIG_SENSORS_SMSC47B397=m
+CONFIG_SENSORS_SCH56XX_COMMON=m
+CONFIG_SENSORS_SCH5627=m
+CONFIG_SENSORS_SCH5636=m
+CONFIG_SENSORS_STTS751=m
+CONFIG_SENSORS_ADC128D818=m
+CONFIG_SENSORS_ADS7828=m
+CONFIG_SENSORS_ADS7871=m
+CONFIG_SENSORS_AMC6821=m
+CONFIG_SENSORS_INA209=m
+CONFIG_SENSORS_INA2XX=m
+# CONFIG_SENSORS_INA238 is not set
+CONFIG_SENSORS_INA3221=m
+# CONFIG_SENSORS_SPD5118 is not set
+CONFIG_SENSORS_TC74=m
+CONFIG_SENSORS_THMC50=m
+CONFIG_SENSORS_TMP102=m
+CONFIG_SENSORS_TMP103=m
+CONFIG_SENSORS_TMP108=m
+CONFIG_SENSORS_TMP401=m
+CONFIG_SENSORS_TMP421=m
+# CONFIG_SENSORS_TMP464 is not set
+CONFIG_SENSORS_TMP513=m
+CONFIG_SENSORS_VEXPRESS=m
+CONFIG_SENSORS_VIA686A=m
+CONFIG_SENSORS_VT1211=m
+CONFIG_SENSORS_VT8231=m
+CONFIG_SENSORS_W83773G=m
+CONFIG_SENSORS_W83781D=m
+CONFIG_SENSORS_W83791D=m
+CONFIG_SENSORS_W83792D=m
+CONFIG_SENSORS_W83793=m
+CONFIG_SENSORS_W83795=m
+# CONFIG_SENSORS_W83795_FANCTRL is not set
+CONFIG_SENSORS_W83L785TS=m
+CONFIG_SENSORS_W83L786NG=m
+CONFIG_SENSORS_W83627HF=m
+CONFIG_SENSORS_W83627EHF=m
+CONFIG_SENSORS_XGENE=m
+
+#
+# ACPI drivers
+#
+CONFIG_SENSORS_ACPI_POWER=m
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_NETLINK is not set
+CONFIG_THERMAL_STATISTICS=y
+# CONFIG_THERMAL_DEBUGFS is not set
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
+# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_MMIO=m
+CONFIG_ROCKCHIP_THERMAL=y
+# CONFIG_GENERIC_ADC_THERMAL is not set
+CONFIG_KHADAS_MCU_FAN_THERMAL=m
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+CONFIG_WATCHDOG_SYSFS=y
+# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
+
+#
+# Watchdog Pretimeout Governors
+#
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
+
+#
+# Watchdog Device Drivers
+#
+CONFIG_SOFT_WATCHDOG=m
+# CONFIG_CROS_EC_WATCHDOG is not set
+CONFIG_GPIO_WATCHDOG=m
+CONFIG_WDAT_WDT=m
+# CONFIG_XILINX_WATCHDOG is not set
+# CONFIG_XILINX_WINDOW_WATCHDOG is not set
+# CONFIG_ZIIRAVE_WATCHDOG is not set
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_ARM_SBSA_WATCHDOG=y
+# CONFIG_CADENCE_WATCHDOG is not set
+CONFIG_DW_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
+CONFIG_ARM_SMC_WATCHDOG=y
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_I6300ESB_WDT is not set
+# CONFIG_HP_WATCHDOG is not set
+# CONFIG_MEN_A21_WDT is not set
+# CONFIG_XEN_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+CONFIG_PCIPCWATCHDOG=m
+CONFIG_WDTPCI=m
+
+#
+# USB-based Watchdog Cards
+#
+CONFIG_USBPCWATCHDOG=m
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+CONFIG_SSB_SDIOHOST=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_BCMA_POSSIBLE=y
+CONFIG_BCMA=m
+CONFIG_BCMA_BLOCKIO=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_SFLASH=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DEBUG=y
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_ACT8945A is not set
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_SMPRO is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_BD9571MWV is not set
+# CONFIG_MFD_AXP20X_I2C is not set
+CONFIG_MFD_CROS_EC_DEV=y
+# CONFIG_MFD_CS42L43_I2C is not set
+# CONFIG_MFD_CS42L43_SDW is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_MFD_MAX5970 is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_GATEWORKS_GSC is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_MFD_MP2629 is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_MFD_HI6421_SPMI is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_IQS62X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_88PM886_PMIC is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77541 is not set
+# CONFIG_MFD_MAX77620 is not set
+# CONFIG_MFD_MAX77650 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77714 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MT6360 is not set
+CONFIG_MFD_MT6370=m
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+CONFIG_MFD_OCELOT=m
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+CONFIG_MFD_NTXEC=m
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_SY7636A is not set
+CONFIG_MFD_RDC321X=m
+# CONFIG_MFD_RT4831 is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RT5120 is not set
+# CONFIG_MFD_RC5T583 is not set
+CONFIG_MFD_RK8XX=m
+CONFIG_MFD_RK8XX_I2C=m
+CONFIG_MFD_RK8XX_SPI=m
+# CONFIG_MFD_RN5T618 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+CONFIG_MFD_SIMPLE_MFD_I2C=m
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_TI_LMU is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TI_LP87565 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MFD_TPS65219 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TPS6594_I2C is not set
+# CONFIG_MFD_TPS6594_SPI is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+CONFIG_MFD_WL1273_CORE=m
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TQMX86 is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_LOCHNAGAR is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_ROHM_BD718XX is not set
+# CONFIG_MFD_ROHM_BD71828 is not set
+# CONFIG_MFD_ROHM_BD957XMUF is not set
+# CONFIG_MFD_ROHM_BD96801 is not set
+# CONFIG_MFD_STPMIC1 is not set
+CONFIG_MFD_STMFX=m
+# CONFIG_MFD_WCD934X is not set
+# CONFIG_MFD_ATC260X_I2C is not set
+CONFIG_MFD_KHADAS_MCU=m
+# CONFIG_MFD_QCOM_PM8008 is not set
+# CONFIG_MFD_CS40L50_I2C is not set
+# CONFIG_MFD_CS40L50_SPI is not set
+CONFIG_MFD_VEXPRESS_SYSREG=y
+# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
+CONFIG_MFD_RSMU_I2C=m
+CONFIG_MFD_RSMU_SPI=m
+# end of Multifunction device drivers
+
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_NETLINK_EVENTS is not set
+# CONFIG_REGULATOR_88PG86X is not set
+CONFIG_REGULATOR_ACT8865=y
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_ARM_SCMI is not set
+# CONFIG_REGULATOR_AW37503 is not set
+# CONFIG_REGULATOR_CROS_EC is not set
+# CONFIG_REGULATOR_DA9121 is not set
+# CONFIG_REGULATOR_DA9210 is not set
+# CONFIG_REGULATOR_DA9211 is not set
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FAN53880=m
+CONFIG_REGULATOR_GPIO=y
+# CONFIG_REGULATOR_ISL9305 is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+# CONFIG_REGULATOR_LTC3589 is not set
+# CONFIG_REGULATOR_LTC3676 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX77503 is not set
+# CONFIG_REGULATOR_MAX77857 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+CONFIG_REGULATOR_MAX8893=m
+# CONFIG_REGULATOR_MAX8952 is not set
+CONFIG_REGULATOR_MAX8973=y
+# CONFIG_REGULATOR_MAX20086 is not set
+# CONFIG_REGULATOR_MAX20411 is not set
+# CONFIG_REGULATOR_MAX77826 is not set
+CONFIG_REGULATOR_MCP16502=m
+CONFIG_REGULATOR_MP5416=m
+CONFIG_REGULATOR_MP8859=m
+CONFIG_REGULATOR_MP886X=m
+CONFIG_REGULATOR_MPQ7920=m
+# CONFIG_REGULATOR_MT6311 is not set
+CONFIG_REGULATOR_MT6315=m
+CONFIG_REGULATOR_MT6370=m
+CONFIG_REGULATOR_PCA9450=y
+CONFIG_REGULATOR_PF8X00=m
+CONFIG_REGULATOR_PFUZE100=m
+# CONFIG_REGULATOR_PV88060 is not set
+# CONFIG_REGULATOR_PV88080 is not set
+# CONFIG_REGULATOR_PV88090 is not set
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+# CONFIG_REGULATOR_RAA215300 is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
+CONFIG_REGULATOR_RK808=m
+# CONFIG_REGULATOR_RT4801 is not set
+# CONFIG_REGULATOR_RT4803 is not set
+# CONFIG_REGULATOR_RT5190A is not set
+# CONFIG_REGULATOR_RT5739 is not set
+CONFIG_REGULATOR_RT5759=m
+CONFIG_REGULATOR_RT6160=m
+# CONFIG_REGULATOR_RT6190 is not set
+CONFIG_REGULATOR_RT6245=m
+CONFIG_REGULATOR_RTQ2134=m
+# CONFIG_REGULATOR_RTMV20 is not set
+CONFIG_REGULATOR_RTQ6752=m
+# CONFIG_REGULATOR_RTQ2208 is not set
+CONFIG_REGULATOR_SLG51000=m
+# CONFIG_REGULATOR_SY8106A is not set
+CONFIG_REGULATOR_SY8824X=m
+# CONFIG_REGULATOR_SY8827N is not set
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS6286X is not set
+# CONFIG_REGULATOR_TPS6287X is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS65132 is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_REGULATOR_VCTRL=m
+CONFIG_REGULATOR_VEXPRESS=m
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
+CONFIG_RC_CORE=m
+CONFIG_LIRC=y
+CONFIG_RC_MAP=m
+CONFIG_RC_DECODERS=y
+CONFIG_IR_IMON_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_RCMM_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_SHARP_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_XMP_DECODER=m
+CONFIG_RC_DEVICES=y
+CONFIG_IR_ENE=m
+CONFIG_IR_FINTEK=m
+CONFIG_IR_GPIO_CIR=m
+CONFIG_IR_GPIO_TX=m
+CONFIG_IR_HIX5HD2=m
+CONFIG_IR_IGORPLUGUSB=m
+CONFIG_IR_IGUANA=m
+CONFIG_IR_IMON=m
+CONFIG_IR_IMON_RAW=m
+CONFIG_IR_ITE_CIR=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_NUVOTON=m
+CONFIG_IR_PWM_TX=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_SERIAL=m
+CONFIG_IR_SERIAL_TRANSMITTER=y
+CONFIG_IR_SPI=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_IR_TOY=m
+CONFIG_IR_TTUSBIR=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_RC_LOOPBACK=m
+CONFIG_RC_XBOX_DVD=m
+CONFIG_CEC_CORE=m
+CONFIG_CEC_NOTIFIER=y
+CONFIG_CEC_PIN=y
+
+#
+# CEC support
+#
+# CONFIG_MEDIA_CEC_RC is not set
+CONFIG_CEC_PIN_ERROR_INJ=y
+CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_CEC_CH7322=m
+CONFIG_CEC_CROS_EC=m
+CONFIG_CEC_GPIO=m
+CONFIG_USB_PULSE8_CEC=m
+CONFIG_USB_RAINSHADOW_CEC=m
+# end of CEC support
+
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+
+#
+# Media device types
+#
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+# end of Media device types
+
+CONFIG_VIDEO_DEV=m
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_DVB_CORE=m
+
+#
+# Video4Linux options
+#
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+CONFIG_VIDEO_FIXED_MINOR_RANGES=y
+CONFIG_VIDEO_TUNER=m
+CONFIG_V4L2_JPEG_HELPER=m
+CONFIG_V4L2_H264=m
+CONFIG_V4L2_VP9=m
+CONFIG_V4L2_MEM2MEM_DEV=m
+CONFIG_V4L2_FLASH_LED_CLASS=m
+CONFIG_V4L2_FWNODE=m
+CONFIG_V4L2_ASYNC=m
+CONFIG_V4L2_CCI=m
+CONFIG_V4L2_CCI_I2C=m
+# end of Video4Linux options
+
+#
+# Media controller options
+#
+CONFIG_MEDIA_CONTROLLER_DVB=y
+# end of Media controller options
+
+#
+# Digital TV options
+#
+CONFIG_DVB_MMAP=y
+CONFIG_DVB_NET=y
+CONFIG_DVB_MAX_ADAPTERS=16
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_DEMUX_SECTION_LOSS_LOG=y
+# CONFIG_DVB_ULE_DEBUG is not set
+# end of Digital TV options
+
+#
+# Media drivers
+#
+
+#
+# Drivers filtered as selected at 'Filter media drivers'
+#
+
+#
+# Media drivers
+#
+CONFIG_MEDIA_USB_SUPPORT=y
+
+#
+# Webcam devices
+#
+CONFIG_USB_GSPCA=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_DTCS033=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_JL2005BCD=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STK1135=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TOUPTEK=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_USB_GL860=m
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_USB_S2255=m
+CONFIG_VIDEO_USBTV=m
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+
+#
+# Analog TV USB devices
+#
+CONFIG_VIDEO_GO7007=m
+CONFIG_VIDEO_GO7007_USB=m
+CONFIG_VIDEO_GO7007_LOADER=m
+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_STK1160=m
+
+#
+# Analog/digital TV USB devices
+#
+CONFIG_VIDEO_AU0828=m
+CONFIG_VIDEO_AU0828_V4L2=y
+CONFIG_VIDEO_AU0828_RC=y
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+
+#
+# Digital TV USB devices
+#
+CONFIG_DVB_AS102=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_DVBSKY=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_USB_ZD1301=m
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_CXUSB=m
+# CONFIG_DVB_USB_CXUSB_ANALOG is not set
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_DIB3000MC=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_SMS_USB_DRV=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+
+#
+# Webcam, TV (analog/digital) USB devices
+#
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_V4L2=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_EM28XX_RC=m
+
+#
+# Software defined radio USB devices
+#
+CONFIG_USB_AIRSPY=m
+CONFIG_USB_HACKRF=m
+CONFIG_USB_MSI2500=m
+CONFIG_MEDIA_PCI_SUPPORT=y
+
+#
+# Media capture support
+#
+# CONFIG_VIDEO_MGB4 is not set
+CONFIG_VIDEO_SOLO6X10=m
+# CONFIG_VIDEO_TW5864 is not set
+CONFIG_VIDEO_TW68=m
+# CONFIG_VIDEO_TW686X is not set
+CONFIG_VIDEO_ZORAN=m
+# CONFIG_VIDEO_ZORAN_DC30 is not set
+# CONFIG_VIDEO_ZORAN_ZR36060 is not set
+
+#
+# Media capture/analog TV support
+#
+CONFIG_VIDEO_DT3155=m
+CONFIG_VIDEO_IVTV=m
+CONFIG_VIDEO_IVTV_ALSA=m
+CONFIG_VIDEO_FB_IVTV=m
+CONFIG_VIDEO_HEXIUM_GEMINI=m
+CONFIG_VIDEO_HEXIUM_ORION=m
+CONFIG_VIDEO_MXB=m
+
+#
+# Media capture/analog/hybrid TV support
+#
+CONFIG_VIDEO_BT848=m
+CONFIG_DVB_BT8XX=m
+CONFIG_VIDEO_CX18=m
+CONFIG_VIDEO_CX18_ALSA=m
+CONFIG_VIDEO_CX23885=m
+CONFIG_MEDIA_ALTERA_CI=m
+CONFIG_VIDEO_CX25821=m
+CONFIG_VIDEO_CX25821_ALSA=m
+CONFIG_VIDEO_CX88=m
+CONFIG_VIDEO_CX88_ALSA=m
+CONFIG_VIDEO_CX88_BLACKBIRD=m
+CONFIG_VIDEO_CX88_DVB=m
+CONFIG_VIDEO_CX88_ENABLE_VP3054=y
+CONFIG_VIDEO_CX88_VP3054=m
+CONFIG_VIDEO_CX88_MPEG=m
+CONFIG_VIDEO_SAA7134=m
+CONFIG_VIDEO_SAA7134_ALSA=m
+CONFIG_VIDEO_SAA7134_RC=y
+CONFIG_VIDEO_SAA7134_DVB=m
+CONFIG_VIDEO_SAA7134_GO7007=m
+CONFIG_VIDEO_SAA7164=m
+
+#
+# Media digital TV PCI Adapters
+#
+CONFIG_DVB_B2C2_FLEXCOP_PCI=m
+# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
+CONFIG_DVB_DDBRIDGE=m
+# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
+CONFIG_DVB_DM1105=m
+CONFIG_MANTIS_CORE=m
+CONFIG_DVB_MANTIS=m
+CONFIG_DVB_HOPPER=m
+# CONFIG_DVB_NETUP_UNIDVB is not set
+CONFIG_DVB_NGENE=m
+CONFIG_DVB_PLUTO2=m
+CONFIG_DVB_PT1=m
+CONFIG_DVB_PT3=m
+CONFIG_DVB_SMIPCIE=m
+CONFIG_DVB_BUDGET_CORE=m
+CONFIG_DVB_BUDGET=m
+CONFIG_DVB_BUDGET_CI=m
+CONFIG_DVB_BUDGET_AV=m
+# CONFIG_IPU_BRIDGE is not set
+CONFIG_RADIO_ADAPTERS=m
+CONFIG_RADIO_MAXIRADIO=m
+CONFIG_RADIO_SAA7706H=m
+CONFIG_RADIO_SHARK=m
+CONFIG_RADIO_SHARK2=m
+CONFIG_RADIO_SI4713=m
+CONFIG_RADIO_TEA575X=m
+CONFIG_RADIO_TEA5764=m
+CONFIG_RADIO_TEF6862=m
+CONFIG_RADIO_WL1273=m
+CONFIG_USB_DSBR=m
+CONFIG_USB_KEENE=m
+CONFIG_USB_MA901=m
+CONFIG_USB_MR800=m
+CONFIG_USB_RAREMONO=m
+CONFIG_RADIO_SI470X=m
+CONFIG_USB_SI470X=m
+CONFIG_I2C_SI470X=m
+CONFIG_USB_SI4713=m
+CONFIG_PLATFORM_SI4713=m
+CONFIG_I2C_SI4713=m
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SDR_PLATFORM_DRIVERS=y
+CONFIG_DVB_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
+CONFIG_VIDEO_MUX=m
+
+#
+# Allegro DVT media platform drivers
+#
+
+#
+# Amlogic media platform drivers
+#
+
+#
+# Amphion drivers
+#
+
+#
+# Aspeed media platform drivers
+#
+
+#
+# Atmel media platform drivers
+#
+
+#
+# Cadence media platform drivers
+#
+CONFIG_VIDEO_CADENCE_CSI2RX=m
+CONFIG_VIDEO_CADENCE_CSI2TX=m
+
+#
+# Chips&Media media platform drivers
+#
+# CONFIG_VIDEO_E5010_JPEG_ENC is not set
+
+#
+# Intel media platform drivers
+#
+
+#
+# Marvell media platform drivers
+#
+CONFIG_VIDEO_CAFE_CCIC=m
+
+#
+# Mediatek media platform drivers
+#
+
+#
+# Microchip Technology, Inc. media platform drivers
+#
+
+#
+# Nuvoton media platform drivers
+#
+
+#
+# NVidia media platform drivers
+#
+
+#
+# NXP media platform drivers
+#
+
+#
+# Qualcomm media platform drivers
+#
+
+#
+# Raspberry Pi media platform drivers
+#
+# CONFIG_VIDEO_RASPBERRYPI_PISP_BE is not set
+
+#
+# Renesas media platform drivers
+#
+
+#
+# Rockchip media platform drivers
+#
+CONFIG_VIDEO_ROCKCHIP_RGA=m
+CONFIG_VIDEO_ROCKCHIP_ISP1=m
+CONFIG_VIDEO_ROCKCHIP_VDEC2=m
+
+#
+# Samsung media platform drivers
+#
+
+#
+# STMicroelectronics media platform drivers
+#
+
+#
+# Sunxi media platform drivers
+#
+CONFIG_VIDEO_SYNOPSYS_HDMIRX=m
+CONFIG_HDMIRX_LOAD_DEFAULT_EDID=y
+
+#
+# Texas Instruments drivers
+#
+
+#
+# Verisilicon media platform drivers
+#
+CONFIG_VIDEO_HANTRO=m
+CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+
+#
+# VIA media platform drivers
+#
+
+#
+# Xilinx media platform drivers
+#
+CONFIG_VIDEO_XILINX=m
+CONFIG_VIDEO_XILINX_CSI2RXSS=m
+CONFIG_VIDEO_XILINX_TPG=m
+CONFIG_VIDEO_XILINX_VTC=m
+
+#
+# MMC/SDIO DVB adapters
+#
+CONFIG_SMS_SDIO_DRV=m
+CONFIG_V4L_TEST_DRIVERS=y
+CONFIG_VIDEO_VIM2M=m
+CONFIG_VIDEO_VICODEC=m
+CONFIG_VIDEO_VIMC=m
+CONFIG_VIDEO_VIVID=m
+CONFIG_VIDEO_VIVID_CEC=y
+CONFIG_VIDEO_VIVID_MAX_DEVS=64
+# CONFIG_VIDEO_VISL is not set
+CONFIG_DVB_TEST_DRIVERS=y
+CONFIG_DVB_VIDTV=m
+CONFIG_MEDIA_COMMON_OPTIONS=y
+
+#
+# common driver options
+#
+CONFIG_CYPRESS_FIRMWARE=m
+CONFIG_TTPCI_EEPROM=m
+CONFIG_UVC_COMMON=m
+CONFIG_VIDEO_CX2341X=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_VIDEO_SAA7146=m
+CONFIG_VIDEO_SAA7146_VV=m
+CONFIG_SMS_SIANO_MDTV=m
+CONFIG_SMS_SIANO_RC=y
+# CONFIG_SMS_SIANO_DEBUGFS is not set
+CONFIG_VIDEO_V4L2_TPG=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_V4L2=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_DMA_CONTIG=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+CONFIG_VIDEOBUF2_DVB=m
+# end of Media drivers
+
+#
+# Media ancillary drivers
+#
+CONFIG_MEDIA_ATTACH=y
+
+#
+# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
+#
+CONFIG_VIDEO_IR_I2C=m
+CONFIG_VIDEO_CAMERA_SENSOR=y
+CONFIG_VIDEO_APTINA_PLL=m
+CONFIG_VIDEO_CCS_PLL=m
+# CONFIG_VIDEO_ALVIUM_CSI2 is not set
+# CONFIG_VIDEO_AR0521 is not set
+# CONFIG_VIDEO_GC0308 is not set
+# CONFIG_VIDEO_GC05A2 is not set
+# CONFIG_VIDEO_GC08A3 is not set
+# CONFIG_VIDEO_GC2145 is not set
+CONFIG_VIDEO_HI556=m
+CONFIG_VIDEO_HI846=m
+# CONFIG_VIDEO_HI847 is not set
+CONFIG_VIDEO_IMX208=m
+CONFIG_VIDEO_IMX214=m
+CONFIG_VIDEO_IMX219=m
+CONFIG_VIDEO_IMX258=m
+CONFIG_VIDEO_IMX274=m
+# CONFIG_VIDEO_IMX283 is not set
+CONFIG_VIDEO_IMX290=m
+# CONFIG_VIDEO_IMX296 is not set
+CONFIG_VIDEO_IMX319=m
+CONFIG_VIDEO_IMX334=m
+CONFIG_VIDEO_IMX335=m
+CONFIG_VIDEO_IMX355=m
+CONFIG_VIDEO_IMX412=m
+# CONFIG_VIDEO_IMX415 is not set
+CONFIG_VIDEO_MAX9271_LIB=m
+CONFIG_VIDEO_MT9M001=m
+CONFIG_VIDEO_MT9M111=m
+# CONFIG_VIDEO_MT9M114 is not set
+CONFIG_VIDEO_MT9P031=m
+CONFIG_VIDEO_MT9T112=m
+CONFIG_VIDEO_MT9V011=m
+CONFIG_VIDEO_MT9V032=m
+CONFIG_VIDEO_MT9V111=m
+# CONFIG_VIDEO_OG01A1B is not set
+# CONFIG_VIDEO_OV01A10 is not set
+CONFIG_VIDEO_OV02A10=m
+# CONFIG_VIDEO_OV08D10 is not set
+# CONFIG_VIDEO_OV08X40 is not set
+CONFIG_VIDEO_OV13858=m
+CONFIG_VIDEO_OV13B10=m
+CONFIG_VIDEO_OV2640=m
+CONFIG_VIDEO_OV2659=m
+CONFIG_VIDEO_OV2680=m
+CONFIG_VIDEO_OV2685=m
+CONFIG_VIDEO_OV2740=m
+# CONFIG_VIDEO_OV4689 is not set
+CONFIG_VIDEO_OV5640=m
+CONFIG_VIDEO_OV5645=m
+CONFIG_VIDEO_OV5647=m
+CONFIG_VIDEO_OV5648=m
+CONFIG_VIDEO_OV5670=m
+CONFIG_VIDEO_OV5675=m
+# CONFIG_VIDEO_OV5693 is not set
+CONFIG_VIDEO_OV5695=m
+# CONFIG_VIDEO_OV64A40 is not set
+CONFIG_VIDEO_OV6650=m
+CONFIG_VIDEO_OV7251=m
+CONFIG_VIDEO_OV7640=m
+CONFIG_VIDEO_OV7670=m
+CONFIG_VIDEO_OV772X=m
+CONFIG_VIDEO_OV7740=m
+CONFIG_VIDEO_OV8856=m
+# CONFIG_VIDEO_OV8858 is not set
+CONFIG_VIDEO_OV8865=m
+CONFIG_VIDEO_OV9282=m
+CONFIG_VIDEO_OV9640=m
+CONFIG_VIDEO_OV9650=m
+CONFIG_VIDEO_OV9734=m
+CONFIG_VIDEO_RDACM20=m
+CONFIG_VIDEO_RDACM21=m
+CONFIG_VIDEO_RJ54N1=m
+CONFIG_VIDEO_S5C73M3=m
+CONFIG_VIDEO_S5K5BAF=m
+CONFIG_VIDEO_S5K6A3=m
+# CONFIG_VIDEO_VGXY61 is not set
+CONFIG_VIDEO_CCS=m
+CONFIG_VIDEO_ET8EK8=m
+
+#
+# Camera ISPs
+#
+# CONFIG_VIDEO_THP7312 is not set
+# end of Camera ISPs
+
+#
+# Lens drivers
+#
+CONFIG_VIDEO_AD5820=m
+CONFIG_VIDEO_AK7375=m
+CONFIG_VIDEO_DW9714=m
+# CONFIG_VIDEO_DW9719 is not set
+CONFIG_VIDEO_DW9768=m
+CONFIG_VIDEO_DW9807_VCM=m
+# end of Lens drivers
+
+#
+# Flash devices
+#
+CONFIG_VIDEO_ADP1653=m
+CONFIG_VIDEO_LM3560=m
+CONFIG_VIDEO_LM3646=m
+# end of Flash devices
+
+#
+# Audio decoders, processors and mixers
+#
+CONFIG_VIDEO_CS3308=m
+CONFIG_VIDEO_CS5345=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_SONY_BTF_MPX=m
+# CONFIG_VIDEO_TDA1997X is not set
+CONFIG_VIDEO_TDA7432=m
+CONFIG_VIDEO_TDA9840=m
+CONFIG_VIDEO_TEA6415C=m
+CONFIG_VIDEO_TEA6420=m
+# CONFIG_VIDEO_TLV320AIC23B is not set
+CONFIG_VIDEO_TVAUDIO=m
+CONFIG_VIDEO_UDA1342=m
+CONFIG_VIDEO_VP27SMPX=m
+CONFIG_VIDEO_WM8739=m
+CONFIG_VIDEO_WM8775=m
+# end of Audio decoders, processors and mixers
+
+#
+# RDS decoders
+#
+CONFIG_VIDEO_SAA6588=m
+# end of RDS decoders
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_ADV7183 is not set
+# CONFIG_VIDEO_ADV748X is not set
+# CONFIG_VIDEO_ADV7604 is not set
+# CONFIG_VIDEO_ADV7842 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_ISL7998X is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_MAX9286 is not set
+# CONFIG_VIDEO_ML86V7667 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+CONFIG_VIDEO_SAA711X=m
+# CONFIG_VIDEO_TC358743 is not set
+# CONFIG_VIDEO_TC358746 is not set
+# CONFIG_VIDEO_TVP514X is not set
+CONFIG_VIDEO_TVP5150=m
+# CONFIG_VIDEO_TVP7002 is not set
+CONFIG_VIDEO_TW2804=m
+# CONFIG_VIDEO_TW9900 is not set
+CONFIG_VIDEO_TW9903=m
+CONFIG_VIDEO_TW9906=m
+# CONFIG_VIDEO_TW9910 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_SAA717X=m
+CONFIG_VIDEO_CX25840=m
+# end of Video decoders
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_ADV7393 is not set
+# CONFIG_VIDEO_AK881X is not set
+CONFIG_VIDEO_SAA7127=m
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_THS8200 is not set
+# end of Video encoders
+
+#
+# Video improvement chips
+#
+CONFIG_VIDEO_UPD64031A=m
+CONFIG_VIDEO_UPD64083=m
+# end of Video improvement chips
+
+#
+# Audio/Video compression chips
+#
+CONFIG_VIDEO_SAA6752HS=m
+# end of Audio/Video compression chips
+
+#
+# SDR tuner chips
+#
+# CONFIG_SDR_MAX2175 is not set
+# end of SDR tuner chips
+
+#
+# Miscellaneous helper chips
+#
+# CONFIG_VIDEO_I2C is not set
+CONFIG_VIDEO_M52790=m
+# CONFIG_VIDEO_ST_MIPID02 is not set
+# CONFIG_VIDEO_THS7303 is not set
+# end of Miscellaneous helper chips
+
+#
+# Video serializers and deserializers
+#
+# CONFIG_VIDEO_DS90UB913 is not set
+# CONFIG_VIDEO_DS90UB953 is not set
+# CONFIG_VIDEO_DS90UB960 is not set
+# CONFIG_VIDEO_MAX96714 is not set
+# CONFIG_VIDEO_MAX96717 is not set
+# end of Video serializers and deserializers
+
+#
+# Media SPI Adapters
+#
+CONFIG_CXD2880_SPI_DRV=m
+CONFIG_VIDEO_GS1662=m
+# end of Media SPI Adapters
+
+CONFIG_MEDIA_TUNER=m
+
+#
+# Customize TV tuners
+#
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER_M88RS6000T=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MSI001=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MXL301RF=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_QM1D1B0004=m
+CONFIG_MEDIA_TUNER_QM1D1C0042=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_R820T=m
+CONFIG_MEDIA_TUNER_SI2157=m
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TDA18250=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_XC5000=m
+# end of Customize TV tuners
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_M88DS3103=m
+CONFIG_DVB_MXL5XX=m
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV0910=m
+CONFIG_DVB_STV6110x=m
+CONFIG_DVB_STV6111=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_MN88472=m
+CONFIG_DVB_MN88473=m
+CONFIG_DVB_SI2165=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_CX24117=m
+CONFIG_DVB_CX24120=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_TDA10071=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AS102_FE=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_CXD2841ER=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+# CONFIG_DVB_DIB9000 is not set
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_GP8PSK_FE=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+CONFIG_DVB_RTL2832_SDR=m
+# CONFIG_DVB_S5H1432 is not set
+CONFIG_DVB_SI2168=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_ZD1301_DEMOD=m
+CONFIG_DVB_ZL10353=m
+# CONFIG_DVB_CXD2880 is not set
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_STV0297=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_VES1820=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LGDT3306A=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_MXL692=m
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+CONFIG_DVB_S921=m
+
+#
+# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
+#
+# CONFIG_DVB_MN88443X is not set
+CONFIG_DVB_TC90522=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_A8293=m
+CONFIG_DVB_AF9033=m
+# CONFIG_DVB_ASCOT2E is not set
+CONFIG_DVB_ATBM8830=m
+# CONFIG_DVB_HELENE is not set
+# CONFIG_DVB_HORUS3A is not set
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_IX2505V=m
+# CONFIG_DVB_LGS8GL5 is not set
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_LNBH25=m
+# CONFIG_DVB_LNBH29 is not set
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_DRX39XYJ=m
+
+#
+# Common Interface (EN50221) controller drivers
+#
+CONFIG_DVB_CXD2099=m
+CONFIG_DVB_SP2=m
+# end of Customise DVB Frontends
+
+#
+# Tools to develop new frontends
+#
+CONFIG_DVB_DUMMY_FE=m
+# end of Media ancillary drivers
+
+#
+# Graphics support
+#
+CONFIG_APERTURE_HELPERS=y
+CONFIG_SCREEN_INFO=y
+CONFIG_VIDEO=y
+# CONFIG_AUXDISPLAY is not set
+CONFIG_DRM=m
+CONFIG_DRM_MIPI_DBI=m
+CONFIG_DRM_MIPI_DSI=y
+# CONFIG_DRM_DEBUG_MM is not set
+CONFIG_DRM_KUNIT_TEST_HELPERS=m
+CONFIG_DRM_KUNIT_TEST=m
+CONFIG_DRM_KMS_HELPER=m
+# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
+# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_DISPLAY_HELPER=m
+CONFIG_DRM_DISPLAY_DP_AUX_BUS=m
+# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set
+# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set
+CONFIG_DRM_DISPLAY_DP_HELPER=y
+CONFIG_DRM_DISPLAY_HDCP_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y
+CONFIG_DRM_TTM=m
+CONFIG_DRM_EXEC=m
+CONFIG_DRM_GPUVM=m
+CONFIG_DRM_BUDDY=m
+CONFIG_DRM_VRAM_HELPER=m
+CONFIG_DRM_TTM_HELPER=m
+CONFIG_DRM_GEM_DMA_HELPER=m
+CONFIG_DRM_GEM_SHMEM_HELPER=m
+CONFIG_DRM_SCHED=m
+
+#
+# I2C encoder or helper chips
+#
+CONFIG_DRM_I2C_CH7006=m
+CONFIG_DRM_I2C_SIL164=m
+CONFIG_DRM_I2C_NXP_TDA998X=m
+CONFIG_DRM_I2C_NXP_TDA9950=m
+# end of I2C encoder or helper chips
+
+#
+# ARM devices
+#
+CONFIG_DRM_HDLCD=m
+CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y
+# CONFIG_DRM_MALI_DISPLAY is not set
+CONFIG_DRM_KOMEDA=m
+# end of ARM devices
+
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_AMDGPU is not set
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_XE is not set
+CONFIG_DRM_VGEM=m
+# CONFIG_DRM_VKMS is not set
+CONFIG_DRM_ROCKCHIP=m
+CONFIG_ROCKCHIP_VOP=y
+CONFIG_ROCKCHIP_VOP2=y
+CONFIG_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_ROCKCHIP_CDN_DP=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_HDMI_QP=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_ROCKCHIP_LVDS=y
+CONFIG_ROCKCHIP_RGB=y
+CONFIG_ROCKCHIP_RK3066_HDMI=y
+CONFIG_DRM_VMWGFX=m
+CONFIG_DRM_UDL=m
+CONFIG_DRM_AST=m
+CONFIG_DRM_MGAG200=m
+CONFIG_DRM_QXL=m
+CONFIG_DRM_VIRTIO_GPU=m
+CONFIG_DRM_VIRTIO_GPU_KMS=y
+CONFIG_DRM_PANEL=y
+
+#
+# Display Panels
+#
+CONFIG_DRM_PANEL_ABT_Y030XX067A=m
+CONFIG_DRM_PANEL_ARM_VERSATILE=m
+# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
+# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
+# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
+CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
+# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set
+CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
+# CONFIG_DRM_PANEL_EBBG_FT8719 is not set
+CONFIG_DRM_PANEL_ELIDA_KD35T133=m
+CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
+CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
+CONFIG_DRM_PANEL_DSI_CM=m
+CONFIG_DRM_PANEL_LVDS=m
+# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set
+# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set
+# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
+CONFIG_DRM_PANEL_ILITEK_IL9322=m
+CONFIG_DRM_PANEL_ILITEK_ILI9341=m
+# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set
+CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
+# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set
+CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
+CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
+# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
+# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set
+CONFIG_DRM_PANEL_JDI_LT070ME05000=m
+# CONFIG_DRM_PANEL_JDI_R63452 is not set
+CONFIG_DRM_PANEL_KHADAS_TS050=m
+CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
+# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
+CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
+# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set
+CONFIG_DRM_PANEL_LG_LB035Q02=m
+# CONFIG_DRM_PANEL_LG_LG4573 is not set
+# CONFIG_DRM_PANEL_LG_SW43408 is not set
+# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set
+# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
+CONFIG_DRM_PANEL_NEC_NL8048HL11=m
+# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
+CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
+CONFIG_DRM_PANEL_NOVATEK_NT35510=m
+CONFIG_DRM_PANEL_NOVATEK_NT35560=m
+# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
+CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
+# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set
+CONFIG_DRM_PANEL_NOVATEK_NT39016=m
+CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
+# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
+CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
+# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
+CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
+# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set
+# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set
+CONFIG_DRM_PANEL_RONBO_RB070D30=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
+CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
+CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set
+CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
+# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
+CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
+CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
+CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
+CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
+CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
+CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
+CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
+CONFIG_DRM_PANEL_SITRONIX_ST7701=m
+# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
+CONFIG_DRM_PANEL_SONY_ACX565AKM=m
+# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
+# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
+# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set
+CONFIG_DRM_PANEL_EDP=m
+CONFIG_DRM_PANEL_SIMPLE=m
+# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set
+CONFIG_DRM_PANEL_TDO_TL070WSH30=m
+CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
+CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
+CONFIG_DRM_PANEL_TPO_TPG110=m
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set
+# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
+# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
+CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
+CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
+# end of Display Panels
+
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_PANEL_BRIDGE=y
+
+#
+# Display Interface Bridges
+#
+CONFIG_DRM_CHIPONE_ICN6211=m
+CONFIG_DRM_CHRONTEL_CH7033=m
+CONFIG_DRM_CROS_EC_ANX7688=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
+CONFIG_DRM_ITE_IT6505=m
+CONFIG_DRM_LONTIUM_LT8912B=m
+CONFIG_DRM_LONTIUM_LT9211=m
+CONFIG_DRM_LONTIUM_LT9611=m
+CONFIG_DRM_LONTIUM_LT9611UXC=m
+CONFIG_DRM_ITE_IT66121=m
+CONFIG_DRM_LVDS_CODEC=m
+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
+CONFIG_DRM_NWL_MIPI_DSI=m
+# CONFIG_DRM_NXP_PTN3460 is not set
+# CONFIG_DRM_PARADE_PS8622 is not set
+CONFIG_DRM_PARADE_PS8640=m
+# CONFIG_DRM_SAMSUNG_DSIM is not set
+# CONFIG_DRM_SIL_SII8620 is not set
+CONFIG_DRM_SII902X=m
+CONFIG_DRM_SII9234=m
+CONFIG_DRM_SIMPLE_BRIDGE=m
+CONFIG_DRM_THINE_THC63LVD1024=m
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
+CONFIG_DRM_TOSHIBA_TC358764=m
+# CONFIG_DRM_TOSHIBA_TC358767 is not set
+CONFIG_DRM_TOSHIBA_TC358768=m
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
+# CONFIG_DRM_TI_DLPC3433 is not set
+# CONFIG_DRM_TI_TFP410 is not set
+CONFIG_DRM_TI_SN65DSI83=m
+# CONFIG_DRM_TI_SN65DSI86 is not set
+CONFIG_DRM_TI_TPD12S015=m
+CONFIG_DRM_ANALOGIX_ANX6345=m
+CONFIG_DRM_ANALOGIX_ANX78XX=m
+CONFIG_DRM_ANALOGIX_DP=m
+# CONFIG_DRM_ANALOGIX_ANX7625 is not set
+CONFIG_DRM_I2C_ADV7511=m
+CONFIG_DRM_I2C_ADV7511_AUDIO=y
+CONFIG_DRM_I2C_ADV7511_CEC=y
+CONFIG_DRM_CDNS_DSI=m
+CONFIG_DRM_CDNS_DSI_J721E=y
+# CONFIG_DRM_CDNS_MHDP8546 is not set
+CONFIG_DRM_DW_HDMI=m
+CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
+# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
+CONFIG_DRM_DW_HDMI_CEC=m
+CONFIG_DRM_DW_HDMI_QP=m
+CONFIG_DRM_DW_MIPI_DSI=m
+# end of Display Interface Bridges
+
+CONFIG_DRM_ETNAVIV=m
+CONFIG_DRM_ETNAVIV_THERMAL=y
+CONFIG_DRM_HISI_HIBMC=m
+CONFIG_DRM_HISI_KIRIN=m
+CONFIG_DRM_LOGICVC=m
+# CONFIG_DRM_ARCPGU is not set
+CONFIG_DRM_BOCHS=m
+# CONFIG_DRM_CIRRUS_QEMU is not set
+CONFIG_DRM_GM12U320=m
+CONFIG_DRM_PANEL_MIPI_DBI=m
+CONFIG_DRM_SIMPLEDRM=m
+CONFIG_TINYDRM_HX8357D=m
+# CONFIG_TINYDRM_ILI9163 is not set
+CONFIG_TINYDRM_ILI9225=m
+CONFIG_TINYDRM_ILI9341=m
+CONFIG_TINYDRM_ILI9486=m
+CONFIG_TINYDRM_MI0283QT=m
+CONFIG_TINYDRM_REPAPER=m
+CONFIG_TINYDRM_ST7586=m
+CONFIG_TINYDRM_ST7735R=m
+CONFIG_DRM_PL111=m
+CONFIG_DRM_XEN=y
+CONFIG_DRM_XEN_FRONTEND=m
+CONFIG_DRM_LIMA=m
+CONFIG_DRM_PANFROST=m
+CONFIG_DRM_PANTHOR=m
+CONFIG_DRM_TIDSS=m
+CONFIG_DRM_GUD=m
+CONFIG_DRM_SSD130X=m
+CONFIG_DRM_SSD130X_I2C=m
+CONFIG_DRM_SSD130X_SPI=m
+# CONFIG_DRM_POWERVR is not set
+CONFIG_DRM_EXPORT_FOR_TESTS=y
+CONFIG_DRM_LIB_RANDOM=y
+# CONFIG_DRM_WERROR is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+
+#
+# Frame buffer Devices
+#
+CONFIG_FB=y
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+CONFIG_FB_UVESA=m
+CONFIG_FB_EFI=y
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SMSCUFX is not set
+CONFIG_FB_UDL=m
+# CONFIG_FB_IBM_GXT4500 is not set
+CONFIG_FB_VIRTUAL=m
+CONFIG_XEN_FBDEV_FRONTEND=y
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_FB_SIMPLE=m
+CONFIG_FB_SSD1307=m
+# CONFIG_FB_SM712 is not set
+CONFIG_FB_CORE=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_DEVICE=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYSMEM_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DMAMEM_HELPERS=y
+CONFIG_FB_IOMEM_FOPS=y
+CONFIG_FB_IOMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_BACKLIGHT=m
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI922X is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=m
+# CONFIG_LCD_AMS369FG06 is not set
+# CONFIG_LCD_LMS501KF03 is not set
+# CONFIG_LCD_HX8357 is not set
+CONFIG_LCD_OTM3225A=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTD253 is not set
+# CONFIG_BACKLIGHT_KTD2801 is not set
+# CONFIG_BACKLIGHT_KTZ8866 is not set
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_MT6370=m
+CONFIG_BACKLIGHT_QCOM_WLED=m
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3509 is not set
+# CONFIG_BACKLIGHT_LM3630A is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+CONFIG_BACKLIGHT_LP855X=y
+# CONFIG_BACKLIGHT_MP3309C is not set
+CONFIG_BACKLIGHT_GPIO=m
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+CONFIG_BACKLIGHT_LED=m
+# end of Backlight & LCD device support
+
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
+# end of Console display driver support
+
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# end of Graphics support
+
+# CONFIG_DRM_ACCEL is not set
+CONFIG_SOUND=m
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+CONFIG_SND_DMAENGINE_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_CORE_TEST is not set
+CONFIG_SND_COMPRESS_OFFLOAD=m
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+# CONFIG_SND_OSSEMUL is not set
+CONFIG_SND_PCM_TIMER=y
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_MAX_CARDS=32
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+CONFIG_SND_CTL_FAST_LOOKUP=y
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_CTL_INPUT_VALIDATION=y
+CONFIG_SND_VMASTER=y
+CONFIG_SND_CTL_LED=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQ_MIDI=m
+CONFIG_SND_SEQ_MIDI_EMUL=m
+CONFIG_SND_SEQ_VIRMIDI=m
+# CONFIG_SND_SEQ_UMP is not set
+CONFIG_SND_MPU401_UART=m
+CONFIG_SND_OPL3_LIB=m
+CONFIG_SND_OPL3_LIB_SEQ=m
+CONFIG_SND_VX_LIB=m
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_ALOOP=m
+# CONFIG_SND_PCMTEST is not set
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_SERIAL_GENERIC=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_AC97_POWER_SAVE=y
+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
+CONFIG_SND_PCI=y
+CONFIG_SND_AD1889=m
+CONFIG_SND_ALS300=m
+CONFIG_SND_ALI5451=m
+CONFIG_SND_ATIIXP=m
+CONFIG_SND_ATIIXP_MODEM=m
+CONFIG_SND_AU8810=m
+CONFIG_SND_AU8820=m
+CONFIG_SND_AU8830=m
+CONFIG_SND_AW2=m
+CONFIG_SND_AZT3328=m
+CONFIG_SND_BT87X=m
+CONFIG_SND_BT87X_OVERCLOCK=y
+CONFIG_SND_CA0106=m
+CONFIG_SND_CMIPCI=m
+CONFIG_SND_OXYGEN_LIB=m
+CONFIG_SND_OXYGEN=m
+CONFIG_SND_CS4281=m
+CONFIG_SND_CS46XX=m
+CONFIG_SND_CS46XX_NEW_DSP=y
+CONFIG_SND_CTXFI=m
+CONFIG_SND_DARLA20=m
+CONFIG_SND_GINA20=m
+CONFIG_SND_LAYLA20=m
+CONFIG_SND_DARLA24=m
+CONFIG_SND_GINA24=m
+CONFIG_SND_LAYLA24=m
+CONFIG_SND_MONA=m
+CONFIG_SND_MIA=m
+CONFIG_SND_ECHO3G=m
+CONFIG_SND_INDIGO=m
+CONFIG_SND_INDIGOIO=m
+CONFIG_SND_INDIGODJ=m
+CONFIG_SND_INDIGOIOX=m
+CONFIG_SND_INDIGODJX=m
+CONFIG_SND_EMU10K1=m
+CONFIG_SND_EMU10K1_SEQ=m
+CONFIG_SND_EMU10K1X=m
+CONFIG_SND_ENS1370=m
+CONFIG_SND_ENS1371=m
+CONFIG_SND_ES1938=m
+CONFIG_SND_ES1968=m
+CONFIG_SND_ES1968_INPUT=y
+CONFIG_SND_ES1968_RADIO=y
+CONFIG_SND_FM801=m
+CONFIG_SND_FM801_TEA575X_BOOL=y
+CONFIG_SND_HDSP=m
+CONFIG_SND_HDSPM=m
+CONFIG_SND_ICE1712=m
+CONFIG_SND_ICE1724=m
+CONFIG_SND_INTEL8X0=m
+CONFIG_SND_INTEL8X0M=m
+CONFIG_SND_KORG1212=m
+CONFIG_SND_LOLA=m
+CONFIG_SND_LX6464ES=m
+CONFIG_SND_MAESTRO3=m
+CONFIG_SND_MAESTRO3_INPUT=y
+CONFIG_SND_MIXART=m
+CONFIG_SND_NM256=m
+CONFIG_SND_PCXHR=m
+CONFIG_SND_RIPTIDE=m
+CONFIG_SND_RME32=m
+CONFIG_SND_RME96=m
+CONFIG_SND_RME9652=m
+CONFIG_SND_SONICVIBES=m
+CONFIG_SND_TRIDENT=m
+CONFIG_SND_VIA82XX=m
+CONFIG_SND_VIA82XX_MODEM=m
+CONFIG_SND_VIRTUOSO=m
+CONFIG_SND_VX222=m
+CONFIG_SND_YMFPCI=m
+
+#
+# HD-Audio
+#
+CONFIG_SND_HDA=m
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_RECONFIG=y
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_INPUT_BEEP_MODE=1
+CONFIG_SND_HDA_PATCH_LOADER=y
+# CONFIG_SND_HDA_CIRRUS_SCODEC_KUNIT_TEST is not set
+CONFIG_SND_HDA_SCODEC_CS35L41=m
+CONFIG_SND_HDA_CS_DSP_CONTROLS=m
+CONFIG_SND_HDA_SCODEC_COMPONENT=m
+CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
+CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
+# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set
+# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set
+# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_ANALOG=m
+CONFIG_SND_HDA_CODEC_SIGMATEL=m
+CONFIG_SND_HDA_CODEC_VIA=m
+CONFIG_SND_HDA_CODEC_HDMI=m
+CONFIG_SND_HDA_CODEC_CIRRUS=m
+CONFIG_SND_HDA_CODEC_CS8409=m
+CONFIG_SND_HDA_CODEC_CONEXANT=m
+# CONFIG_SND_HDA_CODEC_SENARYTECH is not set
+CONFIG_SND_HDA_CODEC_CA0110=m
+CONFIG_SND_HDA_CODEC_CA0132=m
+CONFIG_SND_HDA_CODEC_CA0132_DSP=y
+CONFIG_SND_HDA_CODEC_CMEDIA=m
+CONFIG_SND_HDA_CODEC_SI3054=m
+CONFIG_SND_HDA_GENERIC=m
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
+CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y
+# CONFIG_SND_HDA_CTL_DEV_ID is not set
+# end of HD-Audio
+
+CONFIG_SND_HDA_CORE=m
+CONFIG_SND_HDA_DSP_LOADER=y
+CONFIG_SND_HDA_EXT_CORE=m
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+CONFIG_SND_INTEL_NHLT=y
+CONFIG_SND_INTEL_DSP_CONFIG=m
+CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set
+CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
+CONFIG_SND_USB_UA101=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_USB_HIFACE=m
+CONFIG_SND_BCD2000=m
+CONFIG_SND_USB_LINE6=m
+CONFIG_SND_USB_POD=m
+CONFIG_SND_USB_PODHD=m
+CONFIG_SND_USB_TONEPORT=m
+CONFIG_SND_USB_VARIAX=m
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_COMPRESS=y
+# CONFIG_SND_SOC_TOPOLOGY_BUILD is not set
+# CONFIG_SND_SOC_CARD_KUNIT_TEST is not set
+CONFIG_SND_SOC_UTILS_KUNIT_TEST=m
+CONFIG_SND_SOC_ACPI=m
+CONFIG_SND_SOC_ADI=m
+CONFIG_SND_SOC_ADI_AXI_I2S=m
+CONFIG_SND_SOC_ADI_AXI_SPDIF=m
+CONFIG_SND_SOC_AMD_ACP=m
+CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
+CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
+CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
+# CONFIG_SND_AMD_ACP_CONFIG is not set
+CONFIG_SND_ATMEL_SOC=m
+CONFIG_SND_SOC_MIKROE_PROTO=m
+CONFIG_SND_BCM63XX_I2S_WHISTLER=m
+CONFIG_SND_DESIGNWARE_I2S=m
+CONFIG_SND_DESIGNWARE_PCM=y
+
+#
+# SoC Audio for Freescale CPUs
+#
+
+#
+# Common SoC Audio options for Freescale CPUs:
+#
+CONFIG_SND_SOC_FSL_ASRC=m
+CONFIG_SND_SOC_FSL_SAI=m
+CONFIG_SND_SOC_FSL_MQS=m
+CONFIG_SND_SOC_FSL_AUDMIX=m
+CONFIG_SND_SOC_FSL_SSI=m
+CONFIG_SND_SOC_FSL_SPDIF=m
+CONFIG_SND_SOC_FSL_ESAI=m
+CONFIG_SND_SOC_FSL_MICFIL=m
+CONFIG_SND_SOC_FSL_EASRC=m
+CONFIG_SND_SOC_FSL_XCVR=m
+CONFIG_SND_SOC_FSL_UTILS=m
+CONFIG_SND_SOC_FSL_RPMSG=m
+CONFIG_SND_SOC_IMX_AUDMUX=m
+# end of SoC Audio for Freescale CPUs
+
+# CONFIG_SND_SOC_CHV3_I2S is not set
+CONFIG_SND_I2S_HI6210_I2S=m
+CONFIG_SND_SOC_IMG=y
+CONFIG_SND_SOC_IMG_I2S_IN=m
+CONFIG_SND_SOC_IMG_I2S_OUT=m
+CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
+CONFIG_SND_SOC_IMG_SPDIF_IN=m
+CONFIG_SND_SOC_IMG_SPDIF_OUT=m
+CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
+CONFIG_SND_SOC_MTK_BTCVSD=m
+CONFIG_SND_SOC_ROCKCHIP=m
+CONFIG_SND_SOC_ROCKCHIP_I2S=m
+CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
+CONFIG_SND_SOC_ROCKCHIP_PDM=m
+CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
+CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
+CONFIG_SND_SOC_ROCKCHIP_RT5645=m
+CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
+CONFIG_SND_SOC_RK3399_GRU_SOUND=m
+CONFIG_SND_SOC_SOF_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_PCI=m
+CONFIG_SND_SOC_SOF_ACPI=m
+CONFIG_SND_SOC_SOF_OF=m
+CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y
+# CONFIG_SND_SOC_SOF_MTK_TOPLEVEL is not set
+
+#
+# STMicroelectronics STM32 SOC audio support
+#
+# end of STMicroelectronics STM32 SOC audio support
+
+CONFIG_SND_SOC_XILINX_I2S=m
+CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
+CONFIG_SND_SOC_XILINX_SPDIF=m
+CONFIG_SND_SOC_XTFPGA_I2S=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+
+#
+# CODEC drivers
+#
+CONFIG_SND_SOC_WM_ADSP=m
+CONFIG_SND_SOC_AC97_CODEC=m
+CONFIG_SND_SOC_ADAU_UTILS=m
+CONFIG_SND_SOC_ADAU1372=m
+CONFIG_SND_SOC_ADAU1372_I2C=m
+CONFIG_SND_SOC_ADAU1372_SPI=m
+CONFIG_SND_SOC_ADAU1701=m
+CONFIG_SND_SOC_ADAU17X1=m
+CONFIG_SND_SOC_ADAU1761=m
+CONFIG_SND_SOC_ADAU1761_I2C=m
+CONFIG_SND_SOC_ADAU1761_SPI=m
+CONFIG_SND_SOC_ADAU7002=m
+CONFIG_SND_SOC_ADAU7118=m
+CONFIG_SND_SOC_ADAU7118_HW=m
+CONFIG_SND_SOC_ADAU7118_I2C=m
+CONFIG_SND_SOC_AK4104=m
+CONFIG_SND_SOC_AK4118=m
+CONFIG_SND_SOC_AK4375=m
+CONFIG_SND_SOC_AK4458=m
+CONFIG_SND_SOC_AK4554=m
+CONFIG_SND_SOC_AK4613=m
+# CONFIG_SND_SOC_AK4619 is not set
+CONFIG_SND_SOC_AK4642=m
+CONFIG_SND_SOC_AK5386=m
+CONFIG_SND_SOC_AK5558=m
+CONFIG_SND_SOC_ALC5623=m
+# CONFIG_SND_SOC_AUDIO_IIO_AUX is not set
+CONFIG_SND_SOC_AW8738=m
+# CONFIG_SND_SOC_AW88395 is not set
+# CONFIG_SND_SOC_AW88261 is not set
+# CONFIG_SND_SOC_AW87390 is not set
+# CONFIG_SND_SOC_AW88399 is not set
+CONFIG_SND_SOC_BD28623=m
+CONFIG_SND_SOC_BT_SCO=m
+# CONFIG_SND_SOC_CHV3_CODEC is not set
+CONFIG_SND_SOC_CROS_EC_CODEC=m
+CONFIG_SND_SOC_CS_AMP_LIB=m
+# CONFIG_SND_SOC_CS_AMP_LIB_TEST is not set
+CONFIG_SND_SOC_CS35L32=m
+CONFIG_SND_SOC_CS35L33=m
+CONFIG_SND_SOC_CS35L34=m
+CONFIG_SND_SOC_CS35L35=m
+CONFIG_SND_SOC_CS35L36=m
+CONFIG_SND_SOC_CS35L41_LIB=m
+CONFIG_SND_SOC_CS35L41=m
+CONFIG_SND_SOC_CS35L41_SPI=m
+CONFIG_SND_SOC_CS35L41_I2C=m
+CONFIG_SND_SOC_CS35L45=m
+CONFIG_SND_SOC_CS35L45_SPI=m
+CONFIG_SND_SOC_CS35L45_I2C=m
+# CONFIG_SND_SOC_CS35L56_I2C is not set
+# CONFIG_SND_SOC_CS35L56_SPI is not set
+# CONFIG_SND_SOC_CS35L56_SDW is not set
+CONFIG_SND_SOC_CS42L42_CORE=m
+CONFIG_SND_SOC_CS42L42=m
+# CONFIG_SND_SOC_CS42L42_SDW is not set
+CONFIG_SND_SOC_CS42L51=m
+CONFIG_SND_SOC_CS42L51_I2C=m
+CONFIG_SND_SOC_CS42L52=m
+CONFIG_SND_SOC_CS42L56=m
+CONFIG_SND_SOC_CS42L73=m
+CONFIG_SND_SOC_CS42L83=m
+CONFIG_SND_SOC_CS4234=m
+CONFIG_SND_SOC_CS4265=m
+CONFIG_SND_SOC_CS4270=m
+CONFIG_SND_SOC_CS4271=m
+CONFIG_SND_SOC_CS4271_I2C=m
+CONFIG_SND_SOC_CS4271_SPI=m
+CONFIG_SND_SOC_CS42XX8=m
+CONFIG_SND_SOC_CS42XX8_I2C=m
+CONFIG_SND_SOC_CS43130=m
+CONFIG_SND_SOC_CS4341=m
+CONFIG_SND_SOC_CS4349=m
+CONFIG_SND_SOC_CS53L30=m
+# CONFIG_SND_SOC_CS530X_I2C is not set
+CONFIG_SND_SOC_CX2072X=m
+CONFIG_SND_SOC_DA7213=m
+CONFIG_SND_SOC_DA7219=m
+CONFIG_SND_SOC_DMIC=m
+CONFIG_SND_SOC_HDMI_CODEC=m
+CONFIG_SND_SOC_ES7134=m
+CONFIG_SND_SOC_ES7241=m
+# CONFIG_SND_SOC_ES8311 is not set
+CONFIG_SND_SOC_ES8316=m
+CONFIG_SND_SOC_ES8326=m
+CONFIG_SND_SOC_ES8328=m
+CONFIG_SND_SOC_ES8328_I2C=m
+CONFIG_SND_SOC_ES8328_SPI=m
+CONFIG_SND_SOC_GTM601=m
+CONFIG_SND_SOC_HDA=m
+CONFIG_SND_SOC_ICS43432=m
+# CONFIG_SND_SOC_IDT821034 is not set
+CONFIG_SND_SOC_INNO_RK3036=m
+CONFIG_SND_SOC_MAX98088=m
+CONFIG_SND_SOC_MAX98090=m
+CONFIG_SND_SOC_MAX98357A=m
+CONFIG_SND_SOC_MAX98504=m
+CONFIG_SND_SOC_MAX9867=m
+CONFIG_SND_SOC_MAX98927=m
+CONFIG_SND_SOC_MAX98520=m
+# CONFIG_SND_SOC_MAX98363 is not set
+CONFIG_SND_SOC_MAX98373=m
+CONFIG_SND_SOC_MAX98373_I2C=m
+CONFIG_SND_SOC_MAX98373_SDW=m
+# CONFIG_SND_SOC_MAX98388 is not set
+CONFIG_SND_SOC_MAX98390=m
+CONFIG_SND_SOC_MAX98396=m
+CONFIG_SND_SOC_MAX9860=m
+CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
+CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
+CONFIG_SND_SOC_PCM1681=m
+CONFIG_SND_SOC_PCM1789=m
+CONFIG_SND_SOC_PCM1789_I2C=m
+CONFIG_SND_SOC_PCM179X=m
+CONFIG_SND_SOC_PCM179X_I2C=m
+CONFIG_SND_SOC_PCM179X_SPI=m
+CONFIG_SND_SOC_PCM186X=m
+CONFIG_SND_SOC_PCM186X_I2C=m
+CONFIG_SND_SOC_PCM186X_SPI=m
+CONFIG_SND_SOC_PCM3060=m
+CONFIG_SND_SOC_PCM3060_I2C=m
+CONFIG_SND_SOC_PCM3060_SPI=m
+CONFIG_SND_SOC_PCM3168A=m
+CONFIG_SND_SOC_PCM3168A_I2C=m
+CONFIG_SND_SOC_PCM3168A_SPI=m
+CONFIG_SND_SOC_PCM5102A=m
+CONFIG_SND_SOC_PCM512x=m
+CONFIG_SND_SOC_PCM512x_I2C=m
+CONFIG_SND_SOC_PCM512x_SPI=m
+# CONFIG_SND_SOC_PCM6240 is not set
+# CONFIG_SND_SOC_PEB2466 is not set
+# CONFIG_SND_SOC_RK3308 is not set
+CONFIG_SND_SOC_RK3328=m
+# CONFIG_SND_SOC_RK817 is not set
+CONFIG_SND_SOC_RL6231=m
+# CONFIG_SND_SOC_RT1017_SDCA_SDW is not set
+CONFIG_SND_SOC_RT1308_SDW=m
+CONFIG_SND_SOC_RT1316_SDW=m
+# CONFIG_SND_SOC_RT1318_SDW is not set
+# CONFIG_SND_SOC_RT1320_SDW is not set
+CONFIG_SND_SOC_RT5514=m
+CONFIG_SND_SOC_RT5514_SPI=m
+CONFIG_SND_SOC_RT5616=m
+CONFIG_SND_SOC_RT5631=m
+CONFIG_SND_SOC_RT5640=m
+CONFIG_SND_SOC_RT5645=m
+CONFIG_SND_SOC_RT5659=m
+CONFIG_SND_SOC_RT5682=m
+CONFIG_SND_SOC_RT5682_I2C=m
+CONFIG_SND_SOC_RT5682_SDW=m
+CONFIG_SND_SOC_RT700=m
+CONFIG_SND_SOC_RT700_SDW=m
+CONFIG_SND_SOC_RT711=m
+CONFIG_SND_SOC_RT711_SDW=m
+CONFIG_SND_SOC_RT711_SDCA_SDW=m
+# CONFIG_SND_SOC_RT712_SDCA_SDW is not set
+# CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW is not set
+# CONFIG_SND_SOC_RT722_SDCA_SDW is not set
+CONFIG_SND_SOC_RT715=m
+CONFIG_SND_SOC_RT715_SDW=m
+CONFIG_SND_SOC_RT715_SDCA_SDW=m
+# CONFIG_SND_SOC_RT9120 is not set
+# CONFIG_SND_SOC_RTQ9128 is not set
+# CONFIG_SND_SOC_SDW_MOCKUP is not set
+CONFIG_SND_SOC_SGTL5000=m
+CONFIG_SND_SOC_SIGMADSP=m
+CONFIG_SND_SOC_SIGMADSP_I2C=m
+CONFIG_SND_SOC_SIGMADSP_REGMAP=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+CONFIG_SND_SOC_SIMPLE_MUX=m
+# CONFIG_SND_SOC_SMA1303 is not set
+CONFIG_SND_SOC_SPDIF=m
+CONFIG_SND_SOC_SRC4XXX_I2C=m
+CONFIG_SND_SOC_SRC4XXX=m
+CONFIG_SND_SOC_SSM2305=m
+CONFIG_SND_SOC_SSM2518=m
+CONFIG_SND_SOC_SSM2602=m
+CONFIG_SND_SOC_SSM2602_SPI=m
+CONFIG_SND_SOC_SSM2602_I2C=m
+# CONFIG_SND_SOC_SSM3515 is not set
+CONFIG_SND_SOC_SSM4567=m
+CONFIG_SND_SOC_STA32X=m
+CONFIG_SND_SOC_STA350=m
+CONFIG_SND_SOC_STI_SAS=m
+CONFIG_SND_SOC_TAS2552=m
+CONFIG_SND_SOC_TAS2562=m
+CONFIG_SND_SOC_TAS2764=m
+CONFIG_SND_SOC_TAS2770=m
+CONFIG_SND_SOC_TAS2780=m
+# CONFIG_SND_SOC_TAS2781_I2C is not set
+CONFIG_SND_SOC_TAS5086=m
+CONFIG_SND_SOC_TAS571X=m
+CONFIG_SND_SOC_TAS5720=m
+CONFIG_SND_SOC_TAS5805M=m
+CONFIG_SND_SOC_TAS6424=m
+CONFIG_SND_SOC_TDA7419=m
+CONFIG_SND_SOC_TFA9879=m
+CONFIG_SND_SOC_TFA989X=m
+CONFIG_SND_SOC_TLV320ADC3XXX=m
+CONFIG_SND_SOC_TLV320AIC23=m
+CONFIG_SND_SOC_TLV320AIC23_I2C=m
+CONFIG_SND_SOC_TLV320AIC23_SPI=m
+CONFIG_SND_SOC_TLV320AIC31XX=m
+CONFIG_SND_SOC_TLV320AIC32X4=m
+CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
+CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
+CONFIG_SND_SOC_TLV320AIC3X=m
+CONFIG_SND_SOC_TLV320AIC3X_I2C=m
+CONFIG_SND_SOC_TLV320AIC3X_SPI=m
+CONFIG_SND_SOC_TLV320ADCX140=m
+CONFIG_SND_SOC_TS3A227E=m
+CONFIG_SND_SOC_TSCS42XX=m
+CONFIG_SND_SOC_TSCS454=m
+CONFIG_SND_SOC_UDA1334=m
+CONFIG_SND_SOC_WCD_CLASSH=m
+CONFIG_SND_SOC_WCD9335=m
+CONFIG_SND_SOC_WCD_MBHC=m
+# CONFIG_SND_SOC_WCD937X_SDW is not set
+CONFIG_SND_SOC_WCD938X=m
+CONFIG_SND_SOC_WCD938X_SDW=m
+# CONFIG_SND_SOC_WCD939X_SDW is not set
+CONFIG_SND_SOC_WM8510=m
+CONFIG_SND_SOC_WM8523=m
+CONFIG_SND_SOC_WM8524=m
+CONFIG_SND_SOC_WM8580=m
+CONFIG_SND_SOC_WM8711=m
+CONFIG_SND_SOC_WM8728=m
+CONFIG_SND_SOC_WM8731=m
+CONFIG_SND_SOC_WM8731_I2C=m
+CONFIG_SND_SOC_WM8731_SPI=m
+CONFIG_SND_SOC_WM8737=m
+CONFIG_SND_SOC_WM8741=m
+CONFIG_SND_SOC_WM8750=m
+CONFIG_SND_SOC_WM8753=m
+CONFIG_SND_SOC_WM8770=m
+CONFIG_SND_SOC_WM8776=m
+CONFIG_SND_SOC_WM8782=m
+CONFIG_SND_SOC_WM8804=m
+CONFIG_SND_SOC_WM8804_I2C=m
+CONFIG_SND_SOC_WM8804_SPI=m
+CONFIG_SND_SOC_WM8903=m
+CONFIG_SND_SOC_WM8904=m
+CONFIG_SND_SOC_WM8940=m
+CONFIG_SND_SOC_WM8960=m
+# CONFIG_SND_SOC_WM8961 is not set
+CONFIG_SND_SOC_WM8962=m
+CONFIG_SND_SOC_WM8974=m
+CONFIG_SND_SOC_WM8978=m
+CONFIG_SND_SOC_WM8985=m
+CONFIG_SND_SOC_WSA881X=m
+CONFIG_SND_SOC_WSA883X=m
+# CONFIG_SND_SOC_WSA884X is not set
+CONFIG_SND_SOC_ZL38060=m
+CONFIG_SND_SOC_MAX9759=m
+CONFIG_SND_SOC_MT6351=m
+CONFIG_SND_SOC_MT6358=m
+CONFIG_SND_SOC_MT6660=m
+CONFIG_SND_SOC_NAU8315=m
+CONFIG_SND_SOC_NAU8540=m
+CONFIG_SND_SOC_NAU8810=m
+CONFIG_SND_SOC_NAU8821=m
+CONFIG_SND_SOC_NAU8822=m
+CONFIG_SND_SOC_NAU8824=m
+CONFIG_SND_SOC_TPA6130A2=m
+CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
+CONFIG_SND_SOC_LPASS_WSA_MACRO=m
+CONFIG_SND_SOC_LPASS_VA_MACRO=m
+CONFIG_SND_SOC_LPASS_RX_MACRO=m
+CONFIG_SND_SOC_LPASS_TX_MACRO=m
+# end of CODEC drivers
+
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_AUDIO_GRAPH_CARD=m
+CONFIG_SND_AUDIO_GRAPH_CARD2=m
+CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
+CONFIG_SND_TEST_COMPONENT=m
+CONFIG_SND_SYNTH_EMUX=m
+CONFIG_SND_XEN_FRONTEND=m
+CONFIG_SND_VIRTIO=m
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=m
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=m
+CONFIG_HID_ACCUTOUCH=m
+CONFIG_HID_ACRUX=m
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=m
+CONFIG_HID_APPLEIR=m
+CONFIG_HID_ASUS=m
+CONFIG_HID_AUREAL=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_BETOP_FF=m
+CONFIG_HID_BIGBEN_FF=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CORSAIR=m
+CONFIG_HID_COUGAR=m
+CONFIG_HID_MACALLY=m
+CONFIG_HID_PRODIKEYS=m
+CONFIG_HID_CMEDIA=m
+CONFIG_HID_CP2112=m
+CONFIG_HID_CREATIVE_SB0540=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=m
+CONFIG_HID_ELAN=m
+CONFIG_HID_ELECOM=m
+CONFIG_HID_ELO=m
+# CONFIG_HID_EVISION is not set
+CONFIG_HID_EZKEY=m
+CONFIG_HID_FT260=m
+CONFIG_HID_GEMBIRD=m
+CONFIG_HID_GFRM=m
+CONFIG_HID_GLORIOUS=m
+CONFIG_HID_HOLTEK=m
+CONFIG_HOLTEK_FF=y
+CONFIG_HID_VIVALDI_COMMON=m
+CONFIG_HID_GOOGLE_HAMMER=m
+# CONFIG_HID_GOOGLE_STADIA_FF is not set
+CONFIG_HID_VIVALDI=m
+CONFIG_HID_GT683R=m
+CONFIG_HID_KEYTOUCH=m
+CONFIG_HID_KYE=m
+CONFIG_HID_UCLOGIC=m
+CONFIG_HID_WALTOP=m
+CONFIG_HID_VIEWSONIC=m
+CONFIG_HID_VRC2=m
+CONFIG_HID_XIAOMI=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_ICADE=m
+CONFIG_HID_ITE=m
+CONFIG_HID_JABRA=m
+CONFIG_HID_TWINHAN=m
+CONFIG_HID_KENSINGTON=m
+CONFIG_HID_LCPOWER=m
+CONFIG_HID_LED=m
+CONFIG_HID_LENOVO=m
+# CONFIG_HID_LETSKETCH is not set
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_LOGITECH_DJ=m
+CONFIG_HID_LOGITECH_HIDPP=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_LOGIWHEELS_FF=y
+CONFIG_HID_MAGICMOUSE=m
+CONFIG_HID_MALTRON=m
+CONFIG_HID_MAYFLASH=m
+CONFIG_HID_MEGAWORLD_FF=m
+CONFIG_HID_REDRAGON=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_MULTITOUCH=m
+CONFIG_HID_NINTENDO=m
+# CONFIG_NINTENDO_FF is not set
+CONFIG_HID_NTI=m
+CONFIG_HID_NTRIG=m
+# CONFIG_HID_NVIDIA_SHIELD is not set
+CONFIG_HID_ORTEK=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PENMOUNT=m
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_PICOLCD=m
+CONFIG_HID_PICOLCD_FB=y
+CONFIG_HID_PICOLCD_BACKLIGHT=y
+CONFIG_HID_PICOLCD_LCD=y
+CONFIG_HID_PICOLCD_LEDS=y
+CONFIG_HID_PICOLCD_CIR=y
+CONFIG_HID_PLANTRONICS=m
+CONFIG_HID_PXRC=m
+# CONFIG_HID_RAZER is not set
+CONFIG_HID_PRIMAX=m
+CONFIG_HID_RETRODE=m
+CONFIG_HID_ROCCAT=m
+CONFIG_HID_SAITEK=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SEMITEK=m
+# CONFIG_HID_SIGMAMICRO is not set
+CONFIG_HID_SONY=m
+CONFIG_SONY_FF=y
+CONFIG_HID_SPEEDLINK=m
+CONFIG_HID_STEAM=m
+# CONFIG_STEAM_FF is not set
+CONFIG_HID_STEELSERIES=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_RMI=m
+CONFIG_HID_GREENASIA=m
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=m
+CONFIG_HID_TOPSEED=m
+CONFIG_HID_TOPRE=m
+CONFIG_HID_THINGM=m
+CONFIG_HID_THRUSTMASTER=m
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_HID_UDRAW_PS3=m
+CONFIG_HID_U2FZERO=m
+CONFIG_HID_WACOM=m
+CONFIG_HID_WIIMOTE=m
+# CONFIG_HID_WINWING is not set
+CONFIG_HID_XINMO=m
+CONFIG_HID_ZEROPLUS=m
+CONFIG_ZEROPLUS_FF=y
+CONFIG_HID_ZYDACRON=m
+CONFIG_HID_SENSOR_HUB=m
+CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
+CONFIG_HID_ALPS=m
+# CONFIG_HID_MCP2200 is not set
+CONFIG_HID_MCP2221=m
+# CONFIG_HID_KUNIT_TEST is not set
+# end of Special HID drivers
+
+#
+# HID-BPF support
+#
+# end of HID-BPF support
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+# end of USB HID support
+
+CONFIG_I2C_HID=y
+CONFIG_I2C_HID_ACPI=m
+CONFIG_I2C_HID_OF=m
+CONFIG_I2C_HID_OF_ELAN=m
+CONFIG_I2C_HID_OF_GOODIX=m
+CONFIG_I2C_HID_CORE=m
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_LED_TRIG=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_CONN_GPIO=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_PCI=y
+# CONFIG_USB_PCI_AMD is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_FEW_INIT_RETRIES is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_PRODUCTLIST is not set
+# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
+CONFIG_USB_OTG_FSM=m
+CONFIG_USB_LEDS_TRIGGER_USBPORT=y
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1
+CONFIG_USB_MON=m
+
+#
+# USB Host Controller Drivers
+#
+CONFIG_USB_C67X00_HCD=m
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DBGCAP is not set
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_PCI_RENESAS is not set
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_EHCI_FSL=m
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OXU210HP_HCD=m
+CONFIG_USB_ISP116X_HCD=m
+CONFIG_USB_MAX3421_HCD=m
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_UHCI_HCD=m
+CONFIG_USB_SL811_HCD=m
+CONFIG_USB_SL811_HCD_ISO=y
+CONFIG_USB_R8A66597_HCD=m
+CONFIG_USB_HCD_BCMA=m
+CONFIG_USB_HCD_SSB=m
+CONFIG_USB_HCD_TEST_MODE=y
+# CONFIG_USB_XEN_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+CONFIG_USB_TMC=m
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+CONFIG_USB_UAS=m
+
+#
+# USB Imaging devices
+#
+CONFIG_USB_MDC800=m
+CONFIG_USB_MICROTEK=m
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_VHCI_HC_PORTS=8
+CONFIG_USBIP_VHCI_NR_HCS=1
+CONFIG_USBIP_HOST=m
+CONFIG_USBIP_VUDC=m
+# CONFIG_USBIP_DEBUG is not set
+
+#
+# USB dual-mode controller drivers
+#
+CONFIG_USB_CDNS_SUPPORT=m
+CONFIG_USB_CDNS_HOST=y
+CONFIG_USB_CDNS3=m
+# CONFIG_USB_CDNS3_GADGET is not set
+# CONFIG_USB_CDNS3_HOST is not set
+CONFIG_USB_CDNS3_PCI_WRAP=m
+CONFIG_USB_CDNSP_PCI=m
+CONFIG_USB_CDNSP_GADGET=y
+CONFIG_USB_CDNSP_HOST=y
+CONFIG_USB_MUSB_HDRC=y
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_GADGET is not set
+CONFIG_USB_MUSB_DUAL_ROLE=y
+
+#
+# Platform Glue Layer
+#
+
+#
+# MUSB DMA mode
+#
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_ULPI=y
+# CONFIG_USB_DWC3_HOST is not set
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_DUAL_ROLE=y
+
+#
+# Platform Glue Driver Support
+#
+CONFIG_USB_DWC3_PCI=y
+CONFIG_USB_DWC3_HAPS=y
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC2=y
+# CONFIG_USB_DWC2_HOST is not set
+
+#
+# Gadget/Dual-role mode requires USB Gadget support to be enabled
+#
+# CONFIG_USB_DWC2_PERIPHERAL is not set
+CONFIG_USB_DWC2_DUAL_ROLE=y
+CONFIG_USB_DWC2_PCI=m
+# CONFIG_USB_DWC2_DEBUG is not set
+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_PCI=y
+CONFIG_USB_CHIPIDEA_MSM=y
+CONFIG_USB_CHIPIDEA_NPCM=y
+CONFIG_USB_CHIPIDEA_IMX=y
+CONFIG_USB_CHIPIDEA_GENERIC=y
+CONFIG_USB_CHIPIDEA_TEGRA=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_ISP1760_HCD=y
+CONFIG_USB_ISP1761_UDC=y
+# CONFIG_USB_ISP1760_HOST_ROLE is not set
+# CONFIG_USB_ISP1760_GADGET_ROLE is not set
+CONFIG_USB_ISP1760_DUAL_ROLE=y
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_F8153X=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_METRO=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MXUPORT=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_SAFE=m
+CONFIG_USB_SERIAL_SAFE_PADDED=y
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_XSENS_MT=m
+CONFIG_USB_SERIAL_WISHBONE=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_QT2=m
+CONFIG_USB_SERIAL_UPD78F0730=m
+CONFIG_USB_SERIAL_XR=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_ADUTUX=m
+CONFIG_USB_SEVSEG=m
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+CONFIG_USB_IDMOUSE=m
+CONFIG_USB_APPLEDISPLAY=m
+CONFIG_APPLE_MFI_FASTCHARGE=m
+# CONFIG_USB_LJCA is not set
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_LD=m
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_IOWARRIOR=m
+CONFIG_USB_TEST=m
+CONFIG_USB_EHSET_TEST_FIXTURE=m
+CONFIG_USB_ISIGHTFW=m
+CONFIG_USB_YUREX=m
+CONFIG_USB_EZUSB_FX2=m
+CONFIG_USB_HUB_USB251XB=m
+CONFIG_USB_HSIC_USB3503=y
+CONFIG_USB_HSIC_USB4604=m
+CONFIG_USB_LINK_LAYER_TEST=m
+CONFIG_USB_CHAOSKEY=m
+# CONFIG_USB_ONBOARD_DEV is not set
+CONFIG_USB_ATM=m
+CONFIG_USB_SPEEDTOUCH=m
+CONFIG_USB_CXACRU=m
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_XUSBATM=m
+
+#
+# USB Physical Layer drivers
+#
+CONFIG_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_ISP1301=m
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
+# end of USB Physical Layer drivers
+
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+CONFIG_U_SERIAL_CONSOLE=y
+
+#
+# USB Peripheral Controller
+#
+CONFIG_USB_GR_UDC=m
+CONFIG_USB_R8A66597=m
+CONFIG_USB_PXA27X=m
+CONFIG_USB_MV_UDC=m
+CONFIG_USB_MV_U3D=m
+CONFIG_USB_SNP_CORE=m
+CONFIG_USB_SNP_UDC_PLAT=m
+CONFIG_USB_M66592=m
+CONFIG_USB_BDC_UDC=m
+CONFIG_USB_AMD5536UDC=m
+CONFIG_USB_NET2272=m
+# CONFIG_USB_NET2272_DMA is not set
+CONFIG_USB_NET2280=m
+CONFIG_USB_GOKU=m
+CONFIG_USB_EG20T=m
+CONFIG_USB_GADGET_XILINX=m
+CONFIG_USB_MAX3420_UDC=m
+# CONFIG_USB_CDNS2_UDC is not set
+CONFIG_USB_DUMMY_HCD=m
+# end of USB Peripheral Controller
+
+CONFIG_USB_LIBCOMPOSITE=m
+CONFIG_USB_F_ACM=m
+CONFIG_USB_F_SS_LB=m
+CONFIG_USB_U_SERIAL=m
+CONFIG_USB_U_ETHER=m
+CONFIG_USB_U_AUDIO=m
+CONFIG_USB_F_SERIAL=m
+CONFIG_USB_F_OBEX=m
+CONFIG_USB_F_NCM=m
+CONFIG_USB_F_ECM=m
+CONFIG_USB_F_PHONET=m
+CONFIG_USB_F_EEM=m
+CONFIG_USB_F_SUBSET=m
+CONFIG_USB_F_RNDIS=m
+CONFIG_USB_F_MASS_STORAGE=m
+CONFIG_USB_F_FS=m
+CONFIG_USB_F_UAC1=m
+CONFIG_USB_F_UAC1_LEGACY=m
+CONFIG_USB_F_UAC2=m
+CONFIG_USB_F_UVC=m
+CONFIG_USB_F_MIDI=m
+CONFIG_USB_F_HID=m
+CONFIG_USB_F_PRINTER=m
+CONFIG_USB_F_TCM=m
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+# CONFIG_USB_CONFIGFS_PHONET is not set
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+# CONFIG_USB_CONFIGFS_F_MIDI2 is not set
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_USB_CONFIGFS_F_TCM=y
+
+#
+# USB Gadget precomposed configurations
+#
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ZERO_HNPTEST is not set
+CONFIG_USB_AUDIO=m
+CONFIG_GADGET_UAC1=y
+# CONFIG_GADGET_UAC1_LEGACY is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_FUNCTIONFS_ETH=y
+CONFIG_USB_FUNCTIONFS_RNDIS=y
+CONFIG_USB_FUNCTIONFS_GENERIC=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_GADGET_TARGET=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_G_NOKIA=m
+CONFIG_USB_G_ACM_MS=m
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_RNDIS=y
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_G_HID=m
+# CONFIG_USB_G_DBGP is not set
+CONFIG_USB_G_WEBCAM=m
+CONFIG_USB_RAW_GADGET=m
+# end of USB Gadget precomposed configurations
+
+CONFIG_TYPEC=y
+CONFIG_TYPEC_TCPM=m
+CONFIG_TYPEC_TCPCI=m
+CONFIG_TYPEC_RT1711H=m
+CONFIG_TYPEC_TCPCI_MT6370=m
+CONFIG_TYPEC_TCPCI_MAXIM=m
+CONFIG_TYPEC_FUSB302=m
+CONFIG_TYPEC_UCSI=m
+CONFIG_UCSI_CCG=m
+CONFIG_UCSI_ACPI=m
+CONFIG_UCSI_STM32G0=m
+CONFIG_TYPEC_TPS6598X=m
+CONFIG_TYPEC_ANX7411=m
+CONFIG_TYPEC_RT1719=m
+CONFIG_TYPEC_HD3SS3220=m
+CONFIG_TYPEC_STUSB160X=m
+CONFIG_TYPEC_WUSB3801=m
+
+#
+# USB Type-C Multiplexer/DeMultiplexer Switch support
+#
+CONFIG_TYPEC_MUX_FSA4480=m
+# CONFIG_TYPEC_MUX_GPIO_SBU is not set
+CONFIG_TYPEC_MUX_PI3USB30532=m
+# CONFIG_TYPEC_MUX_IT5205 is not set
+# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
+# CONFIG_TYPEC_MUX_PTN36502 is not set
+# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set
+# end of USB Type-C Multiplexer/DeMultiplexer Switch support
+
+#
+# USB Type-C Alternate Mode drivers
+#
+CONFIG_TYPEC_DP_ALTMODE=m
+CONFIG_TYPEC_NVIDIA_ALTMODE=m
+# end of USB Type-C Alternate Mode drivers
+
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_MMC=y
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_PWRSEQ_SD8787=m
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_SDIO_UART=m
+CONFIG_MMC_TEST=y
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_STM32_SDMMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_AT91=m
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_F_SDH30=y
+CONFIG_MMC_SDHCI_MILBEAUT=m
+CONFIG_MMC_ALCOR=m
+CONFIG_MMC_TIFM_SD=m
+CONFIG_MMC_SPI=y
+# CONFIG_MMC_CB710 is not set
+CONFIG_MMC_VIA_SDMMC=m
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_BLUEFIELD=m
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_MMC_DW_HI3798CV200=y
+# CONFIG_MMC_DW_HI3798MV200 is not set
+CONFIG_MMC_DW_K3=y
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_VUB300=m
+CONFIG_MMC_USHC=m
+CONFIG_MMC_USDHI6ROL0=m
+CONFIG_MMC_REALTEK_PCI=m
+CONFIG_MMC_REALTEK_USB=m
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_HSQ=m
+# CONFIG_MMC_TOSHIBA_PCI is not set
+CONFIG_MMC_MTK=m
+CONFIG_MMC_SDHCI_XENON=y
+# CONFIG_MMC_LITEX is not set
+CONFIG_SCSI_UFSHCD=y
+# CONFIG_SCSI_UFS_BSG is not set
+CONFIG_SCSI_UFS_HWMON=y
+CONFIG_SCSI_UFSHCD_PCI=m
+# CONFIG_SCSI_UFS_DWC_TC_PCI is not set
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set
+# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=m
+# CONFIG_LEDS_CLASS_MULTICOLOR is not set
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+
+#
+# LED drivers
+#
+CONFIG_LEDS_AN30259A=m
+# CONFIG_LEDS_AW200XX is not set
+# CONFIG_LEDS_AW2013 is not set
+# CONFIG_LEDS_BCM6328 is not set
+# CONFIG_LEDS_BCM6358 is not set
+CONFIG_LEDS_CR0014114=m
+CONFIG_LEDS_EL15203000=m
+# CONFIG_LEDS_LM3530 is not set
+CONFIG_LEDS_LM3532=m
+# CONFIG_LEDS_LM3642 is not set
+CONFIG_LEDS_LM3692X=m
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP3952 is not set
+# CONFIG_LEDS_LP8860 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA963X is not set
+# CONFIG_LEDS_PCA995X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+CONFIG_LEDS_PWM=m
+CONFIG_LEDS_REGULATOR=m
+# CONFIG_LEDS_BD2606MVV is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_TLC591XX is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_IS31FL319X is not set
+# CONFIG_LEDS_IS31FL32XX is not set
+
+#
+# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
+#
+# CONFIG_LEDS_BLINKM is not set
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_MLXREG=m
+CONFIG_LEDS_USER=y
+CONFIG_LEDS_SPI_BYTE=m
+CONFIG_LEDS_TI_LMU_COMMON=m
+CONFIG_LEDS_LM3697=m
+
+#
+# Flash and Torch LED drivers
+#
+# CONFIG_LEDS_AAT1290 is not set
+# CONFIG_LEDS_AS3645A is not set
+# CONFIG_LEDS_KTD2692 is not set
+# CONFIG_LEDS_LM3601X is not set
+# CONFIG_LEDS_MT6370_FLASH is not set
+# CONFIG_LEDS_RT4505 is not set
+# CONFIG_LEDS_RT8515 is not set
+# CONFIG_LEDS_SGM3140 is not set
+# CONFIG_LEDS_SY7802 is not set
+
+#
+# RGB LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_ONESHOT=m
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_MTD=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=y
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_LEDS_TRIGGER_TRANSIENT=m
+CONFIG_LEDS_TRIGGER_CAMERA=m
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_NETDEV=m
+CONFIG_LEDS_TRIGGER_PATTERN=m
+CONFIG_LEDS_TRIGGER_TTY=m
+# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set
+
+#
+# Simple LED drivers
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_GHES=y
+# CONFIG_EDAC_THUNDERX is not set
+# CONFIG_EDAC_XGENE is not set
+CONFIG_EDAC_DMC520=m
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+CONFIG_RTC_LIB_KUNIT_TEST=m
+CONFIG_RTC_NVMEM=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
+# CONFIG_RTC_DRV_ABEOZ9 is not set
+# CONFIG_RTC_DRV_ABX80X is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+CONFIG_RTC_DRV_HYM8563=y
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_MAX31335 is not set
+# CONFIG_RTC_DRV_NCT3018Y is not set
+CONFIG_RTC_DRV_RK808=m
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_ISL12026 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8523 is not set
+# CONFIG_RTC_DRV_PCF85063 is not set
+# CONFIG_RTC_DRV_PCF85363 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8010 is not set
+# CONFIG_RTC_DRV_RX8111 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3028 is not set
+# CONFIG_RTC_DRV_RV3032 is not set
+# CONFIG_RTC_DRV_RV8803 is not set
+# CONFIG_RTC_DRV_SD3078 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1302 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6916 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+
+#
+# SPI and I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_PCF2127 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+# CONFIG_RTC_DRV_RX6110 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1685_FAMILY is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+# CONFIG_RTC_DRV_EFI is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+CONFIG_RTC_DRV_OPTEE=m
+# CONFIG_RTC_DRV_ZYNQMP is not set
+# CONFIG_RTC_DRV_CROS_EC is not set
+# CONFIG_RTC_DRV_NTXEC is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+# CONFIG_RTC_DRV_CADENCE is not set
+# CONFIG_RTC_DRV_FTRTC010 is not set
+# CONFIG_RTC_DRV_R7301 is not set
+
+#
+# HID Sensor RTC drivers
+#
+# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
+# CONFIG_RTC_DRV_GOLDFISH is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_OF=y
+CONFIG_ALTERA_MSGDMA=m
+# CONFIG_AMBA_PL08X is not set
+CONFIG_BCM_SBA_RAID=m
+CONFIG_DW_AXI_DMAC=m
+CONFIG_FSL_EDMA=y
+CONFIG_FSL_QDMA=m
+# CONFIG_INTEL_IDMA64 is not set
+CONFIG_MV_XOR_V2=y
+CONFIG_PL330_DMA=y
+CONFIG_PLX_DMA=m
+# CONFIG_XILINX_DMA is not set
+# CONFIG_XILINX_XDMA is not set
+# CONFIG_XILINX_ZYNQMP_DMA is not set
+# CONFIG_XILINX_ZYNQMP_DPDMA is not set
+CONFIG_QCOM_HIDMA_MGMT=y
+CONFIG_QCOM_HIDMA=y
+CONFIG_DW_DMAC_CORE=m
+CONFIG_DW_DMAC=m
+CONFIG_DW_DMAC_PCI=m
+CONFIG_DW_EDMA=m
+CONFIG_DW_EDMA_PCIE=m
+CONFIG_SF_PDMA=m
+
+#
+# DMA Clients
+#
+CONFIG_ASYNC_TX_DMA=y
+# CONFIG_DMATEST is not set
+CONFIG_DMA_ENGINE_RAID=y
+
+#
+# DMABUF options
+#
+CONFIG_SYNC_FILE=y
+# CONFIG_SW_SYNC is not set
+CONFIG_UDMABUF=y
+# CONFIG_DMABUF_MOVE_NOTIFY is not set
+# CONFIG_DMABUF_DEBUG is not set
+CONFIG_DMABUF_SELFTESTS=m
+CONFIG_DMABUF_HEAPS=y
+CONFIG_DMABUF_SYSFS_STATS=y
+CONFIG_DMABUF_HEAPS_SYSTEM=y
+CONFIG_DMABUF_HEAPS_CMA=y
+# end of DMABUF options
+
+CONFIG_UIO=m
+CONFIG_UIO_CIF=m
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_DMEM_GENIRQ is not set
+CONFIG_UIO_AEC=m
+CONFIG_UIO_SERCOS3=m
+CONFIG_UIO_PCI_GENERIC=m
+# CONFIG_UIO_NETX is not set
+# CONFIG_UIO_MF624 is not set
+CONFIG_VFIO=y
+CONFIG_VFIO_GROUP=y
+CONFIG_VFIO_CONTAINER=y
+CONFIG_VFIO_IOMMU_TYPE1=y
+# CONFIG_VFIO_NOIOMMU is not set
+CONFIG_VFIO_VIRQFD=y
+# CONFIG_VFIO_DEBUGFS is not set
+
+#
+# VFIO support for PCI devices
+#
+CONFIG_VFIO_PCI_CORE=y
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI=y
+CONFIG_MLX5_VFIO_PCI=m
+# CONFIG_HISI_ACC_VFIO_PCI is not set
+# CONFIG_NVGRACE_GPU_VFIO_PCI is not set
+# end of VFIO support for PCI devices
+
+#
+# VFIO support for platform devices
+#
+# CONFIG_VFIO_PLATFORM is not set
+# CONFIG_VFIO_AMBA is not set
+# end of VFIO support for platform devices
+
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VMGENID=y
+CONFIG_NITRO_ENCLAVES=m
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+CONFIG_VIRTIO_MENU=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_VDPA=m
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_INPUT=m
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
+# CONFIG_VIRTIO_DEBUG is not set
+CONFIG_VDPA=m
+CONFIG_VDPA_SIM=m
+CONFIG_VDPA_SIM_NET=m
+CONFIG_VDPA_SIM_BLOCK=m
+CONFIG_VDPA_USER=m
+CONFIG_IFCVF=m
+CONFIG_MLX5_VDPA=y
+CONFIG_MLX5_VDPA_NET=m
+# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set
+CONFIG_VP_VDPA=m
+# CONFIG_SNET_VDPA is not set
+# CONFIG_OCTEONEP_VDPA is not set
+CONFIG_VHOST_IOTLB=m
+CONFIG_VHOST_RING=m
+CONFIG_VHOST_TASK=y
+CONFIG_VHOST=m
+CONFIG_VHOST_MENU=y
+CONFIG_VHOST_NET=m
+CONFIG_VHOST_SCSI=m
+# CONFIG_VHOST_VSOCK is not set
+CONFIG_VHOST_VDPA=m
+# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# CONFIG_HYPERV is not set
+# end of Microsoft Hyper-V guest support
+
+#
+# Xen driver support
+#
+CONFIG_XEN_BALLOON=y
+CONFIG_XEN_SCRUB_PAGES_DEFAULT=y
+CONFIG_XEN_DEV_EVTCHN=y
+CONFIG_XEN_BACKEND=y
+CONFIG_XENFS=y
+CONFIG_XEN_COMPAT_XENFS=y
+CONFIG_XEN_SYS_HYPERVISOR=y
+CONFIG_XEN_XENBUS_FRONTEND=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+# CONFIG_XEN_GRANT_DMA_ALLOC is not set
+CONFIG_SWIOTLB_XEN=y
+CONFIG_XEN_PCI_STUB=y
+CONFIG_XEN_PCIDEV_STUB=m
+# CONFIG_XEN_PVCALLS_FRONTEND is not set
+# CONFIG_XEN_PVCALLS_BACKEND is not set
+CONFIG_XEN_SCSI_BACKEND=m
+CONFIG_XEN_PRIVCMD=y
+CONFIG_XEN_EFI=y
+CONFIG_XEN_AUTO_XLATE=y
+CONFIG_XEN_FRONT_PGDIR_SHBUF=m
+# CONFIG_XEN_VIRTIO is not set
+# end of Xen driver support
+
+# CONFIG_GREYBUS is not set
+# CONFIG_COMEDI is not set
+CONFIG_STAGING=y
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+CONFIG_RTL8192E=m
+CONFIG_RTL8723BS=m
+CONFIG_R8712U=m
+CONFIG_RTS5208=m
+CONFIG_VT6655=m
+CONFIG_VT6656=m
+
+#
+# IIO staging drivers
+#
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16240 is not set
+# end of Accelerometers
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7816 is not set
+# end of Analog to digital converters
+
+#
+# Analog digital bi-direction converters
+#
+# CONFIG_ADT7316 is not set
+# end of Analog digital bi-direction converters
+
+#
+# Direct Digital Synthesis
+#
+CONFIG_AD9832=m
+CONFIG_AD9834=m
+# end of Direct Digital Synthesis
+
+#
+# Network Analyzer, Impedance Converters
+#
+# CONFIG_AD5933 is not set
+# end of Network Analyzer, Impedance Converters
+# end of IIO staging drivers
+
+CONFIG_FB_SM750=m
+CONFIG_STAGING_MEDIA=y
+CONFIG_DVB_AV7110_IR=y
+CONFIG_DVB_AV7110=m
+CONFIG_DVB_AV7110_OSD=y
+CONFIG_DVB_SP8870=m
+# CONFIG_VIDEO_MAX96712 is not set
+CONFIG_VIDEO_ROCKCHIP_VDEC=m
+
+#
+# StarFive media platform drivers
+#
+CONFIG_STAGING_MEDIA_DEPRECATED=y
+
+#
+# Atmel media platform drivers
+#
+# CONFIG_LTE_GDM724X is not set
+CONFIG_FB_TFT=m
+CONFIG_FB_TFT_AGM1264K_FL=m
+CONFIG_FB_TFT_BD663474=m
+CONFIG_FB_TFT_HX8340BN=m
+CONFIG_FB_TFT_HX8347D=m
+CONFIG_FB_TFT_HX8353D=m
+CONFIG_FB_TFT_HX8357D=m
+CONFIG_FB_TFT_ILI9163=m
+CONFIG_FB_TFT_ILI9320=m
+CONFIG_FB_TFT_ILI9325=m
+CONFIG_FB_TFT_ILI9340=m
+CONFIG_FB_TFT_ILI9341=m
+CONFIG_FB_TFT_ILI9481=m
+CONFIG_FB_TFT_ILI9486=m
+CONFIG_FB_TFT_PCD8544=m
+CONFIG_FB_TFT_RA8875=m
+CONFIG_FB_TFT_S6D02A1=m
+CONFIG_FB_TFT_S6D1121=m
+CONFIG_FB_TFT_SEPS525=m
+CONFIG_FB_TFT_SH1106=m
+CONFIG_FB_TFT_SSD1289=m
+CONFIG_FB_TFT_SSD1305=m
+CONFIG_FB_TFT_SSD1306=m
+CONFIG_FB_TFT_SSD1331=m
+CONFIG_FB_TFT_SSD1351=m
+CONFIG_FB_TFT_ST7735R=m
+CONFIG_FB_TFT_ST7789V=m
+CONFIG_FB_TFT_TINYLCD=m
+CONFIG_FB_TFT_TLS8204=m
+CONFIG_FB_TFT_UC1611=m
+CONFIG_FB_TFT_UC1701=m
+CONFIG_FB_TFT_UPD161704=m
+# CONFIG_MOST_COMPONENTS is not set
+# CONFIG_KS7010 is not set
+# CONFIG_XIL_AXIS_FIFO is not set
+CONFIG_FIELDBUS_DEV=m
+CONFIG_HMS_ANYBUSS_BUS=m
+# CONFIG_ARCX_ANYBUS_CONTROLLER is not set
+# CONFIG_HMS_PROFINET is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_RTL8723CS is not set
+# CONFIG_GOLDFISH is not set
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CHROMEOS_ACPI=m
+# CONFIG_CHROMEOS_TBMC is not set
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+# CONFIG_CROS_EC_RPMSG is not set
+CONFIG_CROS_EC_SPI=y
+# CONFIG_CROS_EC_UART is not set
+CONFIG_CROS_EC_PROTO=y
+# CONFIG_CROS_KBD_LED_BACKLIGHT is not set
+CONFIG_CROS_EC_CHARDEV=y
+CONFIG_CROS_EC_LIGHTBAR=y
+CONFIG_CROS_EC_VBC=y
+CONFIG_CROS_EC_DEBUGFS=y
+CONFIG_CROS_EC_SENSORHUB=y
+CONFIG_CROS_EC_SYSFS=y
+CONFIG_CROS_EC_TYPEC=m
+# CONFIG_CROS_HPS_I2C is not set
+CONFIG_CROS_USBPD_NOTIFY=y
+# CONFIG_CHROMEOS_PRIVACY_SCREEN is not set
+CONFIG_CROS_TYPEC_SWITCH=m
+# CONFIG_CROS_KUNIT_EC_PROTO_TEST is not set
+# CONFIG_CZNIC_PLATFORMS is not set
+# CONFIG_MELLANOX_PLATFORM is not set
+CONFIG_SURFACE_PLATFORMS=y
+# CONFIG_SURFACE_3_POWER_OPREGION is not set
+# CONFIG_SURFACE_GPE is not set
+# CONFIG_SURFACE_HOTPLUG is not set
+# CONFIG_SURFACE_PRO3_BUTTON is not set
+# CONFIG_SURFACE_AGGREGATOR is not set
+CONFIG_ARM64_PLATFORM_DEVICES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Clock driver for ARM Reference designs
+#
+# CONFIG_CLK_ICST is not set
+# CONFIG_CLK_SP810 is not set
+# CONFIG_CLK_VEXPRESS_OSC is not set
+# end of Clock driver for ARM Reference designs
+
+# CONFIG_LMK04832 is not set
+# CONFIG_COMMON_CLK_MAX9485 is not set
+CONFIG_COMMON_CLK_RK808=m
+CONFIG_COMMON_CLK_SCMI=y
+# CONFIG_COMMON_CLK_SCPI is not set
+# CONFIG_COMMON_CLK_SI5341 is not set
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI514 is not set
+# CONFIG_COMMON_CLK_SI544 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_COMMON_CLK_CDCE925 is not set
+# CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
+# CONFIG_COMMON_CLK_XGENE is not set
+CONFIG_COMMON_CLK_PWM=y
+# CONFIG_COMMON_CLK_RS9_PCIE is not set
+# CONFIG_COMMON_CLK_SI521XX is not set
+# CONFIG_COMMON_CLK_VC3 is not set
+# CONFIG_COMMON_CLK_VC5 is not set
+# CONFIG_COMMON_CLK_VC7 is not set
+# CONFIG_COMMON_CLK_FIXED_MMIO is not set
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3568=y
+CONFIG_CLK_RK3588=y
+# CONFIG_XILINX_VCU is not set
+# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
+# CONFIG_CLK_KUNIT_TEST is not set
+# CONFIG_CLK_GATE_KUNIT_TEST is not set
+# CONFIG_CLK_FD_KUNIT_TEST is not set
+# CONFIG_HWSPINLOCK is not set
+
+#
+# Clock Source drivers
+#
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_ACPI=y
+CONFIG_TIMER_PROBE=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_FSL_ERRATUM_A008585=y
+CONFIG_HISILICON_ERRATUM_161010101=y
+CONFIG_ARM64_ERRATUM_858921=y
+# end of Clock Source drivers
+
+CONFIG_MAILBOX=y
+CONFIG_ARM_MHU=y
+CONFIG_ARM_MHU_V2=m
+# CONFIG_ARM_MHU_V3 is not set
+CONFIG_PLATFORM_MHU=y
+# CONFIG_PL320_MBOX is not set
+CONFIG_ROCKCHIP_MBOX=y
+CONFIG_PCC=y
+# CONFIG_ALTERA_MBOX is not set
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_API=y
+CONFIG_IOMMUFD_DRIVER=y
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+# end of Generic IOMMU Pagetable Support
+
+# CONFIG_IOMMU_DEBUGFS is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_OF_IOMMU=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_SVA=y
+CONFIG_IOMMU_IOPF=y
+# CONFIG_IOMMUFD is not set
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ARM_SMMU=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+CONFIG_ARM_SMMU_V3=y
+CONFIG_ARM_SMMU_V3_SVA=y
+# CONFIG_ARM_SMMU_V3_KUNIT_TEST is not set
+CONFIG_VIRTIO_IOMMU=m
+
+#
+# Remoteproc drivers
+#
+CONFIG_REMOTEPROC=y
+# CONFIG_REMOTEPROC_CDEV is not set
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+CONFIG_RPMSG=y
+# CONFIG_RPMSG_CHAR is not set
+# CONFIG_RPMSG_CTRL is not set
+CONFIG_RPMSG_NS=m
+CONFIG_RPMSG_QCOM_GLINK=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+# CONFIG_RPMSG_VIRTIO is not set
+# end of Rpmsg drivers
+
+CONFIG_SOUNDWIRE=m
+
+#
+# SoundWire Devices
+#
+# CONFIG_SOUNDWIRE_AMD is not set
+# CONFIG_SOUNDWIRE_INTEL is not set
+CONFIG_SOUNDWIRE_QCOM=m
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# end of Amlogic SoC drivers
+
+#
+# Broadcom SoC drivers
+#
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_RCPM is not set
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# fujitsu SoC drivers
+#
+# CONFIG_A64FX_DIAG is not set
+# end of fujitsu SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# Enable LiteX SoC Builder specific drivers
+#
+CONFIG_LITEX=y
+CONFIG_LITEX_SOC_CONTROLLER=m
+# end of Enable LiteX SoC Builder specific drivers
+
+# CONFIG_WPCM450_SOC is not set
+
+#
+# Qualcomm SoC drivers
+#
+# CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set
+# CONFIG_QCOM_PMIC_GLINK is not set
+CONFIG_QCOM_QMI_HELPERS=m
+# CONFIG_QCOM_PBS is not set
+# end of Qualcomm SoC drivers
+
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_SOC_TI=y
+
+#
+# Xilinx SoC drivers
+#
+# end of Xilinx SoC drivers
+# end of SOC (System On Chip) specific Drivers
+
+#
+# PM Domains
+#
+
+#
+# Amlogic PM Domains
+#
+# end of Amlogic PM Domains
+
+CONFIG_ARM_SCMI_PERF_DOMAIN=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+
+#
+# Broadcom PM Domains
+#
+# end of Broadcom PM Domains
+
+#
+# i.MX PM Domains
+#
+# end of i.MX PM Domains
+
+#
+# Qualcomm PM Domains
+#
+# end of Qualcomm PM Domains
+
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# end of PM Domains
+
+CONFIG_PM_DEVFREQ=y
+
+#
+# DEVFREQ Governors
+#
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=m
+CONFIG_DEVFREQ_GOV_POWERSAVE=m
+CONFIG_DEVFREQ_GOV_USERSPACE=m
+CONFIG_DEVFREQ_GOV_PASSIVE=m
+
+#
+# DEVFREQ Drivers
+#
+CONFIG_ARM_RK3399_DMC_DEVFREQ=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
+CONFIG_EXTCON=y
+
+#
+# Extcon Device Drivers
+#
+CONFIG_EXTCON_ADC_JACK=m
+# CONFIG_EXTCON_FSA9480 is not set
+CONFIG_EXTCON_GPIO=y
+# CONFIG_EXTCON_MAX3355 is not set
+CONFIG_EXTCON_PTN5150=m
+# CONFIG_EXTCON_RT8973A is not set
+# CONFIG_EXTCON_SM5502 is not set
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_EXTCON_USBC_CROS_EC=y
+CONFIG_EXTCON_USBC_TUSB320=m
+CONFIG_MEMORY=y
+# CONFIG_ARM_PL172_MPMC is not set
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_BUFFER_CB=m
+# CONFIG_IIO_BUFFER_DMA is not set
+# CONFIG_IIO_BUFFER_DMAENGINE is not set
+CONFIG_IIO_BUFFER_HW_CONSUMER=m
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_IIO_CONFIGFS=m
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+CONFIG_IIO_SW_DEVICE=m
+CONFIG_IIO_SW_TRIGGER=m
+CONFIG_IIO_TRIGGERED_EVENT=m
+
+#
+# Accelerometers
+#
+CONFIG_ADIS16201=m
+CONFIG_ADIS16209=m
+CONFIG_ADXL313=m
+CONFIG_ADXL313_I2C=m
+CONFIG_ADXL313_SPI=m
+CONFIG_ADXL345=m
+CONFIG_ADXL345_I2C=m
+CONFIG_ADXL345_SPI=m
+CONFIG_ADXL355=m
+CONFIG_ADXL355_I2C=m
+CONFIG_ADXL355_SPI=m
+CONFIG_ADXL367=m
+CONFIG_ADXL367_SPI=m
+CONFIG_ADXL367_I2C=m
+CONFIG_ADXL372=m
+CONFIG_ADXL372_SPI=m
+CONFIG_ADXL372_I2C=m
+CONFIG_BMA180=m
+CONFIG_BMA220=m
+CONFIG_BMA400=m
+CONFIG_BMA400_I2C=m
+CONFIG_BMA400_SPI=m
+CONFIG_BMC150_ACCEL=m
+CONFIG_BMC150_ACCEL_I2C=m
+CONFIG_BMC150_ACCEL_SPI=m
+CONFIG_BMI088_ACCEL=m
+CONFIG_BMI088_ACCEL_I2C=m
+CONFIG_BMI088_ACCEL_SPI=m
+CONFIG_DA280=m
+CONFIG_DA311=m
+CONFIG_DMARD06=m
+CONFIG_DMARD09=m
+CONFIG_DMARD10=m
+CONFIG_FXLS8962AF=m
+CONFIG_FXLS8962AF_I2C=m
+CONFIG_FXLS8962AF_SPI=m
+CONFIG_HID_SENSOR_ACCEL_3D=m
+CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
+CONFIG_IIO_ST_ACCEL_3AXIS=m
+CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
+CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
+# CONFIG_IIO_KX022A_SPI is not set
+# CONFIG_IIO_KX022A_I2C is not set
+CONFIG_KXSD9=m
+CONFIG_KXSD9_SPI=m
+CONFIG_KXSD9_I2C=m
+CONFIG_KXCJK1013=m
+CONFIG_MC3230=m
+CONFIG_MMA7455=m
+CONFIG_MMA7455_I2C=m
+CONFIG_MMA7455_SPI=m
+CONFIG_MMA7660=m
+CONFIG_MMA8452=m
+CONFIG_MMA9551_CORE=m
+CONFIG_MMA9551=m
+CONFIG_MMA9553=m
+# CONFIG_MSA311 is not set
+CONFIG_MXC4005=m
+CONFIG_MXC6255=m
+CONFIG_SCA3000=m
+CONFIG_SCA3300=m
+CONFIG_STK8312=m
+CONFIG_STK8BA50=m
+# end of Accelerometers
+
+#
+# Analog to digital converters
+#
+CONFIG_AD_SIGMA_DELTA=m
+# CONFIG_AD4130 is not set
+CONFIG_AD7091R=m
+CONFIG_AD7091R5=m
+# CONFIG_AD7091R8 is not set
+CONFIG_AD7124=m
+# CONFIG_AD7173 is not set
+# CONFIG_AD7192 is not set
+CONFIG_AD7266=m
+# CONFIG_AD7280 is not set
+CONFIG_AD7291=m
+CONFIG_AD7292=m
+CONFIG_AD7298=m
+# CONFIG_AD7380 is not set
+CONFIG_AD7476=m
+CONFIG_AD7606=m
+CONFIG_AD7606_IFACE_PARALLEL=m
+CONFIG_AD7606_IFACE_SPI=m
+CONFIG_AD7766=m
+CONFIG_AD7768_1=m
+# CONFIG_AD7780 is not set
+CONFIG_AD7791=m
+CONFIG_AD7793=m
+CONFIG_AD7887=m
+CONFIG_AD7923=m
+# CONFIG_AD7944 is not set
+CONFIG_AD7949=m
+CONFIG_AD799X=m
+# CONFIG_AD9467 is not set
+# CONFIG_CC10001_ADC is not set
+# CONFIG_ENVELOPE_DETECTOR is not set
+# CONFIG_HI8435 is not set
+# CONFIG_HX711 is not set
+# CONFIG_INA2XX_ADC is not set
+# CONFIG_LTC2309 is not set
+# CONFIG_LTC2471 is not set
+# CONFIG_LTC2485 is not set
+CONFIG_LTC2496=m
+# CONFIG_LTC2497 is not set
+# CONFIG_MAX1027 is not set
+# CONFIG_MAX11100 is not set
+# CONFIG_MAX1118 is not set
+CONFIG_MAX11205=m
+# CONFIG_MAX11410 is not set
+# CONFIG_MAX1241 is not set
+CONFIG_MAX1363=m
+# CONFIG_MAX34408 is not set
+CONFIG_MAX9611=m
+CONFIG_MCP320X=m
+CONFIG_MCP3422=m
+# CONFIG_MCP3564 is not set
+CONFIG_MCP3911=m
+# CONFIG_MEDIATEK_MT6370_ADC is not set
+# CONFIG_NAU7802 is not set
+# CONFIG_PAC1934 is not set
+# CONFIG_QCOM_SPMI_IADC is not set
+# CONFIG_QCOM_SPMI_VADC is not set
+# CONFIG_QCOM_SPMI_ADC5 is not set
+CONFIG_ROCKCHIP_SARADC=y
+CONFIG_RICHTEK_RTQ6056=m
+# CONFIG_SD_ADC_MODULATOR is not set
+CONFIG_TI_ADC081C=m
+CONFIG_TI_ADC0832=m
+CONFIG_TI_ADC084S021=m
+CONFIG_TI_ADC12138=m
+CONFIG_TI_ADC108S102=m
+CONFIG_TI_ADC128S052=m
+CONFIG_TI_ADC161S626=m
+CONFIG_TI_ADS1015=m
+# CONFIG_TI_ADS1119 is not set
+# CONFIG_TI_ADS7924 is not set
+# CONFIG_TI_ADS1100 is not set
+# CONFIG_TI_ADS1298 is not set
+CONFIG_TI_ADS7950=m
+CONFIG_TI_ADS8344=m
+CONFIG_TI_ADS8688=m
+CONFIG_TI_ADS124S08=m
+CONFIG_TI_ADS131E08=m
+# CONFIG_TI_LMP92064 is not set
+# CONFIG_TI_TLC4541 is not set
+CONFIG_TI_TSC2046=m
+# CONFIG_VF610_ADC is not set
+CONFIG_XILINX_XADC=m
+# end of Analog to digital converters
+
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74115 is not set
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
+#
+# Analog Front Ends
+#
+# CONFIG_IIO_RESCALE is not set
+# end of Analog Front Ends
+
+#
+# Amplifiers
+#
+# CONFIG_AD8366 is not set
+# CONFIG_ADA4250 is not set
+CONFIG_HMC425=m
+# end of Amplifiers
+
+#
+# Capacitance to digital converters
+#
+# CONFIG_AD7150 is not set
+# CONFIG_AD7746 is not set
+# end of Capacitance to digital converters
+
+#
+# Chemical Sensors
+#
+# CONFIG_AOSONG_AGS02MA is not set
+# CONFIG_ATLAS_PH_SENSOR is not set
+# CONFIG_ATLAS_EZO_SENSOR is not set
+CONFIG_BME680=m
+CONFIG_BME680_I2C=m
+CONFIG_BME680_SPI=m
+# CONFIG_CCS811 is not set
+# CONFIG_ENS160 is not set
+# CONFIG_IAQCORE is not set
+CONFIG_PMS7003=m
+# CONFIG_SCD30_CORE is not set
+CONFIG_SCD4X=m
+CONFIG_SENSIRION_SGP30=m
+CONFIG_SENSIRION_SGP40=m
+CONFIG_SPS30=m
+CONFIG_SPS30_I2C=m
+CONFIG_SPS30_SERIAL=m
+CONFIG_SENSEAIR_SUNRISE_CO2=m
+# CONFIG_VZ89X is not set
+# end of Chemical Sensors
+
+CONFIG_IIO_CROS_EC_SENSORS_CORE=m
+CONFIG_IIO_CROS_EC_SENSORS=m
+# CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE is not set
+
+#
+# Hid Sensor IIO Common
+#
+CONFIG_HID_SENSOR_IIO_COMMON=m
+CONFIG_HID_SENSOR_IIO_TRIGGER=m
+# end of Hid Sensor IIO Common
+
+CONFIG_IIO_MS_SENSORS_I2C=m
+
+#
+# IIO SCMI Sensors
+#
+CONFIG_IIO_SCMI=m
+# end of IIO SCMI Sensors
+
+#
+# SSP Sensor Common
+#
+# CONFIG_IIO_SSP_SENSORHUB is not set
+# end of SSP Sensor Common
+
+CONFIG_IIO_ST_SENSORS_I2C=m
+CONFIG_IIO_ST_SENSORS_SPI=m
+CONFIG_IIO_ST_SENSORS_CORE=m
+
+#
+# Digital to analog converters
+#
+# CONFIG_AD3552R is not set
+# CONFIG_AD5064 is not set
+# CONFIG_AD5360 is not set
+# CONFIG_AD5380 is not set
+# CONFIG_AD5421 is not set
+# CONFIG_AD5446 is not set
+# CONFIG_AD5449 is not set
+# CONFIG_AD5592R is not set
+# CONFIG_AD5593R is not set
+# CONFIG_AD5504 is not set
+# CONFIG_AD5624R_SPI is not set
+# CONFIG_AD9739A is not set
+# CONFIG_LTC2688 is not set
+CONFIG_AD5686=m
+CONFIG_AD5686_SPI=m
+CONFIG_AD5696_I2C=m
+# CONFIG_AD5755 is not set
+CONFIG_AD5758=m
+# CONFIG_AD5761 is not set
+# CONFIG_AD5764 is not set
+CONFIG_AD5766=m
+CONFIG_AD5770R=m
+# CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
+# CONFIG_AD7303 is not set
+# CONFIG_AD8801 is not set
+# CONFIG_DPOT_DAC is not set
+# CONFIG_DS4424 is not set
+CONFIG_LTC1660=m
+# CONFIG_LTC2632 is not set
+# CONFIG_M62332 is not set
+# CONFIG_MAX517 is not set
+# CONFIG_MAX5522 is not set
+# CONFIG_MAX5821 is not set
+# CONFIG_MCP4725 is not set
+# CONFIG_MCP4728 is not set
+# CONFIG_MCP4821 is not set
+# CONFIG_MCP4922 is not set
+# CONFIG_TI_DAC082S085 is not set
+CONFIG_TI_DAC5571=m
+CONFIG_TI_DAC7311=m
+CONFIG_TI_DAC7612=m
+# CONFIG_VF610_DAC is not set
+# end of Digital to analog converters
+
+#
+# IIO dummy driver
+#
+CONFIG_IIO_SIMPLE_DUMMY=m
+# CONFIG_IIO_SIMPLE_DUMMY_EVENTS is not set
+# CONFIG_IIO_SIMPLE_DUMMY_BUFFER is not set
+# end of IIO dummy driver
+
+#
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
+#
+# Frequency Synthesizers DDS/PLL
+#
+
+#
+# Clock Generator/Distribution
+#
+CONFIG_AD9523=m
+# end of Clock Generator/Distribution
+
+#
+# Phase-Locked Loop (PLL) frequency synthesizers
+#
+# CONFIG_ADF4350 is not set
+CONFIG_ADF4371=m
+# CONFIG_ADF4377 is not set
+# CONFIG_ADMFM2000 is not set
+# CONFIG_ADMV1013 is not set
+# CONFIG_ADMV1014 is not set
+# CONFIG_ADMV4420 is not set
+CONFIG_ADRF6780=m
+# end of Phase-Locked Loop (PLL) frequency synthesizers
+# end of Frequency Synthesizers DDS/PLL
+
+#
+# Digital gyroscope sensors
+#
+CONFIG_ADIS16080=m
+CONFIG_ADIS16130=m
+CONFIG_ADIS16136=m
+CONFIG_ADIS16260=m
+# CONFIG_ADXRS290 is not set
+CONFIG_ADXRS450=m
+CONFIG_BMG160=m
+CONFIG_BMG160_I2C=m
+CONFIG_BMG160_SPI=m
+CONFIG_FXAS21002C=m
+CONFIG_FXAS21002C_I2C=m
+CONFIG_FXAS21002C_SPI=m
+CONFIG_HID_SENSOR_GYRO_3D=m
+CONFIG_MPU3050=m
+CONFIG_MPU3050_I2C=m
+CONFIG_IIO_ST_GYRO_3AXIS=m
+CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
+CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
+CONFIG_ITG3200=m
+# end of Digital gyroscope sensors
+
+#
+# Health Sensors
+#
+
+#
+# Heart Rate Monitors
+#
+CONFIG_AFE4403=m
+CONFIG_AFE4404=m
+CONFIG_MAX30100=m
+CONFIG_MAX30102=m
+# end of Heart Rate Monitors
+# end of Health Sensors
+
+#
+# Humidity sensors
+#
+CONFIG_AM2315=m
+CONFIG_DHT11=m
+CONFIG_HDC100X=m
+# CONFIG_HDC2010 is not set
+# CONFIG_HDC3020 is not set
+CONFIG_HID_SENSOR_HUMIDITY=m
+CONFIG_HTS221=m
+CONFIG_HTS221_I2C=m
+CONFIG_HTS221_SPI=m
+CONFIG_HTU21=m
+CONFIG_SI7005=m
+CONFIG_SI7020=m
+# end of Humidity sensors
+
+#
+# Inertial measurement units
+#
+# CONFIG_ADIS16400 is not set
+CONFIG_ADIS16460=m
+# CONFIG_ADIS16475 is not set
+# CONFIG_ADIS16480 is not set
+# CONFIG_BMI160_I2C is not set
+# CONFIG_BMI160_SPI is not set
+# CONFIG_BMI323_I2C is not set
+# CONFIG_BMI323_SPI is not set
+# CONFIG_BOSCH_BNO055_SERIAL is not set
+# CONFIG_BOSCH_BNO055_I2C is not set
+CONFIG_FXOS8700=m
+CONFIG_FXOS8700_I2C=m
+CONFIG_FXOS8700_SPI=m
+# CONFIG_KMX61 is not set
+# CONFIG_INV_ICM42600_I2C is not set
+# CONFIG_INV_ICM42600_SPI is not set
+# CONFIG_INV_MPU6050_I2C is not set
+# CONFIG_INV_MPU6050_SPI is not set
+# CONFIG_IIO_ST_LSM6DSX is not set
+CONFIG_IIO_ST_LSM9DS0=m
+CONFIG_IIO_ST_LSM9DS0_I2C=m
+CONFIG_IIO_ST_LSM9DS0_SPI=m
+# end of Inertial measurement units
+
+CONFIG_IIO_ADIS_LIB=m
+CONFIG_IIO_ADIS_LIB_BUFFER=y
+
+#
+# Light sensors
+#
+CONFIG_ACPI_ALS=m
+CONFIG_ADJD_S311=m
+CONFIG_ADUX1020=m
+CONFIG_AL3010=m
+CONFIG_AL3320A=m
+CONFIG_APDS9300=m
+# CONFIG_APDS9306 is not set
+CONFIG_APDS9960=m
+# CONFIG_AS73211 is not set
+CONFIG_BH1750=m
+CONFIG_BH1780=m
+CONFIG_CM32181=m
+CONFIG_CM3232=m
+CONFIG_CM3323=m
+CONFIG_CM3605=m
+CONFIG_CM36651=m
+CONFIG_IIO_CROS_EC_LIGHT_PROX=m
+CONFIG_GP2AP002=m
+CONFIG_GP2AP020A00F=m
+CONFIG_SENSORS_ISL29018=m
+CONFIG_SENSORS_ISL29028=m
+CONFIG_ISL29125=m
+# CONFIG_ISL76682 is not set
+CONFIG_HID_SENSOR_ALS=m
+CONFIG_HID_SENSOR_PROX=m
+CONFIG_JSA1212=m
+# CONFIG_ROHM_BU27008 is not set
+# CONFIG_ROHM_BU27034 is not set
+CONFIG_RPR0521=m
+# CONFIG_LTR390 is not set
+CONFIG_LTR501=m
+# CONFIG_LTRF216A is not set
+CONFIG_LV0104CS=m
+CONFIG_MAX44000=m
+CONFIG_MAX44009=m
+CONFIG_NOA1305=m
+CONFIG_OPT3001=m
+# CONFIG_OPT4001 is not set
+CONFIG_PA12203001=m
+CONFIG_SI1133=m
+CONFIG_SI1145=m
+CONFIG_STK3310=m
+CONFIG_ST_UVIS25=m
+CONFIG_ST_UVIS25_I2C=m
+CONFIG_ST_UVIS25_SPI=m
+CONFIG_TCS3414=m
+CONFIG_TCS3472=m
+CONFIG_SENSORS_TSL2563=m
+CONFIG_TSL2583=m
+CONFIG_TSL2591=m
+CONFIG_TSL2772=m
+CONFIG_TSL4531=m
+CONFIG_US5182D=m
+CONFIG_VCNL4000=m
+CONFIG_VCNL4035=m
+CONFIG_VEML6030=m
+# CONFIG_VEML6040 is not set
+CONFIG_VEML6070=m
+# CONFIG_VEML6075 is not set
+CONFIG_VL6180=m
+CONFIG_ZOPT2201=m
+# end of Light sensors
+
+#
+# Magnetometer sensors
+#
+# CONFIG_AF8133J is not set
+CONFIG_AK8974=m
+CONFIG_AK8975=m
+CONFIG_AK09911=m
+CONFIG_BMC150_MAGN=m
+CONFIG_BMC150_MAGN_I2C=m
+CONFIG_BMC150_MAGN_SPI=m
+CONFIG_MAG3110=m
+CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
+CONFIG_MMC35240=m
+CONFIG_IIO_ST_MAGN_3AXIS=m
+CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
+CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
+CONFIG_SENSORS_HMC5843=m
+CONFIG_SENSORS_HMC5843_I2C=m
+CONFIG_SENSORS_HMC5843_SPI=m
+CONFIG_SENSORS_RM3100=m
+CONFIG_SENSORS_RM3100_I2C=m
+CONFIG_SENSORS_RM3100_SPI=m
+# CONFIG_TI_TMAG5273 is not set
+CONFIG_YAMAHA_YAS530=m
+# end of Magnetometer sensors
+
+#
+# Multiplexers
+#
+# CONFIG_IIO_MUX is not set
+# end of Multiplexers
+
+#
+# Inclinometer sensors
+#
+CONFIG_HID_SENSOR_INCLINOMETER_3D=m
+CONFIG_HID_SENSOR_DEVICE_ROTATION=m
+# end of Inclinometer sensors
+
+# CONFIG_IIO_GTS_KUNIT_TEST is not set
+CONFIG_IIO_FORMAT_KUNIT_TEST=m
+
+#
+# Triggers - standalone
+#
+CONFIG_IIO_HRTIMER_TRIGGER=m
+CONFIG_IIO_INTERRUPT_TRIGGER=m
+CONFIG_IIO_TIGHTLOOP_TRIGGER=m
+CONFIG_IIO_SYSFS_TRIGGER=m
+# end of Triggers - standalone
+
+#
+# Linear and angular position sensors
+#
+CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
+# end of Linear and angular position sensors
+
+#
+# Digital potentiometers
+#
+CONFIG_AD5110=m
+CONFIG_AD5272=m
+CONFIG_DS1803=m
+CONFIG_MAX5432=m
+# CONFIG_MAX5481 is not set
+# CONFIG_MAX5487 is not set
+CONFIG_MCP4018=m
+# CONFIG_MCP4131 is not set
+# CONFIG_MCP4531 is not set
+CONFIG_MCP41010=m
+# CONFIG_TPL0102 is not set
+# CONFIG_X9250 is not set
+# end of Digital potentiometers
+
+#
+# Digital potentiostats
+#
+# CONFIG_LMP91000 is not set
+# end of Digital potentiostats
+
+#
+# Pressure sensors
+#
+# CONFIG_ABP060MG is not set
+# CONFIG_ROHM_BM1390 is not set
+CONFIG_BMP280=m
+CONFIG_BMP280_I2C=m
+CONFIG_BMP280_SPI=m
+# CONFIG_IIO_CROS_EC_BARO is not set
+CONFIG_DLHL60D=m
+CONFIG_DPS310=m
+CONFIG_HID_SENSOR_PRESS=m
+# CONFIG_HP03 is not set
+# CONFIG_HSC030PA is not set
+CONFIG_ICP10100=m
+# CONFIG_MPL115_I2C is not set
+# CONFIG_MPL115_SPI is not set
+CONFIG_MPL3115=m
+# CONFIG_MPRLS0025PA is not set
+# CONFIG_MS5611 is not set
+# CONFIG_MS5637 is not set
+# CONFIG_IIO_ST_PRESS is not set
+# CONFIG_T5403 is not set
+# CONFIG_HP206C is not set
+# CONFIG_ZPA2326 is not set
+# end of Pressure sensors
+
+#
+# Lightning sensors
+#
+# CONFIG_AS3935 is not set
+# end of Lightning sensors
+
+#
+# Proximity and distance sensors
+#
+CONFIG_CROS_EC_MKBP_PROXIMITY=m
+# CONFIG_IRSD200 is not set
+CONFIG_ISL29501=m
+# CONFIG_LIDAR_LITE_V2 is not set
+CONFIG_MB1232=m
+CONFIG_PING=m
+# CONFIG_RFD77402 is not set
+# CONFIG_SRF04 is not set
+# CONFIG_SX9310 is not set
+# CONFIG_SX9324 is not set
+# CONFIG_SX9360 is not set
+# CONFIG_SX9500 is not set
+# CONFIG_SRF08 is not set
+# CONFIG_VCNL3020 is not set
+CONFIG_VL53L0X_I2C=m
+# end of Proximity and distance sensors
+
+#
+# Resolver to digital converters
+#
+# CONFIG_AD2S90 is not set
+# CONFIG_AD2S1200 is not set
+# CONFIG_AD2S1210 is not set
+# end of Resolver to digital converters
+
+#
+# Temperature sensors
+#
+CONFIG_LTC2983=m
+CONFIG_MAXIM_THERMOCOUPLE=m
+CONFIG_HID_SENSOR_TEMP=m
+CONFIG_MLX90614=m
+CONFIG_MLX90632=m
+# CONFIG_MLX90635 is not set
+CONFIG_TMP006=m
+CONFIG_TMP007=m
+CONFIG_TMP117=m
+CONFIG_TSYS01=m
+CONFIG_TSYS02D=m
+# CONFIG_MAX30208 is not set
+CONFIG_MAX31856=m
+CONFIG_MAX31865=m
+# CONFIG_MCP9600 is not set
+# end of Temperature sensors
+
+# CONFIG_NTB is not set
+CONFIG_PWM=y
+# CONFIG_PWM_DEBUG is not set
+CONFIG_PWM_ATMEL_TCB=m
+CONFIG_PWM_CLK=m
+CONFIG_PWM_CROS_EC=m
+CONFIG_PWM_DWC_CORE=m
+CONFIG_PWM_DWC=m
+# CONFIG_PWM_FSL_FTM is not set
+# CONFIG_PWM_GPIO is not set
+CONFIG_PWM_NTXEC=m
+# CONFIG_PWM_PCA9685 is not set
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_XILINX=m
+
+#
+# IRQ chip support
+#
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_MAX_NR=1
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_IRQ_MSI_LIB=y
+# CONFIG_AL_FIC is not set
+# CONFIG_LAN966X_OIC is not set
+# CONFIG_XILINX_INTC is not set
+CONFIG_PARTITION_PERCPU=y
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_GPIO is not set
+CONFIG_RESET_SCMI=y
+# CONFIG_RESET_SIMPLE is not set
+# CONFIG_RESET_TI_SYSCON is not set
+CONFIG_RESET_TI_TPS380X=m
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PHY_MIPI_DPHY=y
+CONFIG_PHY_CAN_TRANSCEIVER=m
+
+#
+# PHY drivers for Broadcom platforms
+#
+CONFIG_BCM_KONA_USB2_PHY=m
+# end of PHY drivers for Broadcom platforms
+
+CONFIG_PHY_CADENCE_TORRENT=m
+CONFIG_PHY_CADENCE_DPHY=m
+# CONFIG_PHY_CADENCE_DPHY_RX is not set
+CONFIG_PHY_CADENCE_SIERRA=m
+# CONFIG_PHY_CADENCE_SALVO is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
+# CONFIG_PHY_CPCAP_USB is not set
+CONFIG_PHY_MAPPHONE_MDM6600=m
+# CONFIG_PHY_OCELOT_SERDES is not set
+CONFIG_PHY_QCOM_USB_HS=y
+CONFIG_PHY_QCOM_USB_HSIC=y
+CONFIG_PHY_ROCKCHIP_DP=y
+CONFIG_PHY_ROCKCHIP_DPHY_RX0=m
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m
+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_PHY_SAMSUNG_USB2=y
+# CONFIG_PHY_TUSB1210 is not set
+# end of PHY Subsystem
+
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+CONFIG_ARM_CCI_PMU=y
+CONFIG_ARM_CCI400_PMU=y
+CONFIG_ARM_CCI5xx_PMU=y
+CONFIG_ARM_CCN=y
+# CONFIG_ARM_CMN is not set
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PMU_ACPI=y
+CONFIG_ARM_SMMU_V3_PMU=m
+CONFIG_ARM_PMUV3=y
+# CONFIG_ARM_DSU_PMU is not set
+# CONFIG_ARM_SPE_PMU is not set
+CONFIG_ARM_DMC620_PMU=m
+CONFIG_ALIBABA_UNCORE_DRW_PMU=m
+CONFIG_HISI_PMU=y
+# CONFIG_HISI_PCIE_PMU is not set
+CONFIG_HNS3_PMU=m
+# CONFIG_DWC_PCIE_PMU is not set
+# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
+CONFIG_CXL_PMU=m
+# end of Performance monitor support
+
+CONFIG_RAS=y
+# CONFIG_USB4 is not set
+
+#
+# Android
+#
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder,anbox-binder,anbox-hwbinder,anbox-vndbinder"
+# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
+# end of Android
+
+# CONFIG_LIBNVDIMM is not set
+CONFIG_DAX=y
+CONFIG_DEV_DAX=m
+CONFIG_DEV_DAX_HMEM=m
+CONFIG_DEV_DAX_CXL=m
+CONFIG_DEV_DAX_HMEM_DEVICES=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVMEM_LAYOUTS=y
+
+#
+# Layout Types
+#
+# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set
+# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set
+# end of Layout Types
+
+CONFIG_NVMEM_RMEM=m
+CONFIG_NVMEM_ROCKCHIP_EFUSE=m
+CONFIG_NVMEM_ROCKCHIP_OTP=m
+CONFIG_NVMEM_SPMI_SDAM=m
+CONFIG_NVMEM_U_BOOT_ENV=m
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+CONFIG_HISI_PTT=m
+# end of HW tracing support
+
+CONFIG_FPGA=y
+# CONFIG_ALTERA_PR_IP_CORE is not set
+# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
+# CONFIG_FPGA_MGR_ALTERA_CVP is not set
+# CONFIG_FPGA_MGR_XILINX_SELECTMAP is not set
+# CONFIG_FPGA_MGR_XILINX_SPI is not set
+# CONFIG_FPGA_MGR_ICE40_SPI is not set
+# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
+CONFIG_FPGA_BRIDGE=m
+CONFIG_ALTERA_FREEZE_BRIDGE=m
+# CONFIG_XILINX_PR_DECOUPLER is not set
+CONFIG_FPGA_REGION=m
+CONFIG_OF_FPGA_REGION=m
+# CONFIG_FPGA_DFL is not set
+CONFIG_FPGA_MGR_MICROCHIP_SPI=m
+# CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI is not set
+# CONFIG_FSI is not set
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+# CONFIG_OPTEE_INSECURE_LOAD_IMAGE is not set
+# CONFIG_ARM_TSTEE is not set
+CONFIG_MULTIPLEXER=y
+
+#
+# Multiplexer drivers
+#
+CONFIG_MUX_ADG792A=m
+CONFIG_MUX_ADGS1408=m
+CONFIG_MUX_GPIO=m
+CONFIG_MUX_MMIO=m
+# end of Multiplexer drivers
+
+CONFIG_PM_OPP=y
+# CONFIG_SIOX is not set
+CONFIG_SLIMBUS=m
+CONFIG_SLIM_QCOM_CTRL=m
+CONFIG_INTERCONNECT=y
+CONFIG_COUNTER=m
+CONFIG_INTERRUPT_CNT=m
+CONFIG_MOST=m
+# CONFIG_MOST_USB_HDM is not set
+# CONFIG_MOST_CDEV is not set
+CONFIG_MOST_SND=m
+# CONFIG_PECI is not set
+# CONFIG_HTE is not set
+# CONFIG_CDX_BUS is not set
+CONFIG_DPLL=y
+# end of Device Drivers
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_VALIDATE_FS_PARSER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_STACK=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_LEGACY_DIRECT_IO=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_EXT4_KUNIT_TESTS=m
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+CONFIG_JFS_SECURITY=y
+# CONFIG_JFS_DEBUG is not set
+CONFIG_JFS_STATISTICS=y
+CONFIG_XFS_FS=m
+CONFIG_XFS_SUPPORT_V4=y
+CONFIG_XFS_SUPPORT_ASCII_CI=y
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_RT=y
+# CONFIG_XFS_ONLINE_SCRUB is not set
+# CONFIG_XFS_WARN is not set
+# CONFIG_XFS_DEBUG is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
+CONFIG_OCFS2_FS=m
+CONFIG_OCFS2_FS_O2CB=m
+CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+CONFIG_OCFS2_FS_STATS=y
+CONFIG_OCFS2_DEBUG_MASKLOG=y
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_BTRFS_FS=y
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_ASSERT is not set
+# CONFIG_BTRFS_FS_REF_VERIFY is not set
+CONFIG_NILFS2_FS=m
+CONFIG_F2FS_FS=y
+CONFIG_F2FS_STAT_FS=y
+CONFIG_F2FS_FS_XATTR=y
+CONFIG_F2FS_FS_POSIX_ACL=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_CHECK_FS=y
+# CONFIG_F2FS_FAULT_INJECTION is not set
+CONFIG_F2FS_FS_COMPRESSION=y
+CONFIG_F2FS_FS_LZO=y
+CONFIG_F2FS_FS_LZORLE=y
+CONFIG_F2FS_FS_LZ4=y
+CONFIG_F2FS_FS_LZ4HC=y
+CONFIG_F2FS_FS_ZSTD=y
+CONFIG_F2FS_IOSTAT=y
+# CONFIG_F2FS_UNFAIR_RWSEM is not set
+CONFIG_BCACHEFS_FS=m
+CONFIG_BCACHEFS_QUOTA=y
+CONFIG_BCACHEFS_ERASURE_CODING=y
+CONFIG_BCACHEFS_POSIX_ACL=y
+# CONFIG_BCACHEFS_DEBUG is not set
+# CONFIG_BCACHEFS_TESTS is not set
+# CONFIG_BCACHEFS_LOCK_TIME_STATS is not set
+# CONFIG_BCACHEFS_NO_LATENCY_ACCT is not set
+CONFIG_BCACHEFS_SIX_OPTIMISTIC_SPIN=y
+# CONFIG_MEAN_AND_VARIANCE_UNIT_TEST is not set
+CONFIG_ZONEFS_FS=m
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_ALGS=y
+CONFIG_FS_VERITY=y
+CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_QUOTA_DEBUG is not set
+CONFIG_QUOTA_TREE=m
+CONFIG_QFMT_V1=m
+CONFIG_QFMT_V2=m
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS_FS=m
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=m
+CONFIG_VIRTIO_FS=m
+CONFIG_FUSE_PASSTHROUGH=y
+CONFIG_OVERLAY_FS=y
+# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
+CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
+# CONFIG_OVERLAY_FS_INDEX is not set
+CONFIG_OVERLAY_FS_XINO_AUTO=y
+# CONFIG_OVERLAY_FS_METACOPY is not set
+# CONFIG_OVERLAY_FS_DEBUG is not set
+
+#
+# Caches
+#
+CONFIG_NETFS_SUPPORT=m
+CONFIG_NETFS_STATS=y
+# CONFIG_NETFS_DEBUG is not set
+CONFIG_FSCACHE=y
+CONFIG_FSCACHE_STATS=y
+CONFIG_CACHEFILES=m
+# CONFIG_CACHEFILES_DEBUG is not set
+# CONFIG_CACHEFILES_ERROR_INJECTION is not set
+# CONFIG_CACHEFILES_ONDEMAND is not set
+# end of Caches
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+# end of CD-ROM/DVD Filesystems
+
+#
+# DOS/FAT/EXFAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=936
+CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
+# CONFIG_FAT_DEFAULT_UTF8 is not set
+# CONFIG_FAT_KUNIT_TEST is not set
+CONFIG_EXFAT_FS=y
+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_NTFS3_FS=y
+# CONFIG_NTFS3_64BIT_CLUSTER is not set
+CONFIG_NTFS3_LZX_XPRESS=y
+CONFIG_NTFS3_FS_POSIX_ACL=y
+CONFIG_NTFS_FS=y
+# end of DOS/FAT/EXFAT/NT Filesystems
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TMPFS_INODE64 is not set
+# CONFIG_TMPFS_QUOTA is not set
+CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_EFIVAR_FS=y
+# end of Pseudo filesystems
+
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_ORANGEFS_FS=m
+CONFIG_ADFS_FS=m
+# CONFIG_ADFS_FS_RW is not set
+CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=y
+CONFIG_ECRYPT_FS_MESSAGING=y
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+CONFIG_BEFS_FS=m
+# CONFIG_BEFS_DEBUG is not set
+CONFIG_BFS_FS=m
+CONFIG_EFS_FS=m
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+# CONFIG_JFFS2_CMODE_PRIORITY is not set
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+CONFIG_UBIFS_FS=m
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UBIFS_FS_ZSTD=y
+# CONFIG_UBIFS_ATIME_SUPPORT is not set
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_SECURITY=y
+# CONFIG_UBIFS_FS_AUTHENTICATION is not set
+CONFIG_CRAMFS=m
+CONFIG_CRAMFS_BLOCKDEV=y
+CONFIG_CRAMFS_MTD=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_ZSTD=y
+CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_VXFS_FS=m
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
+CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
+# CONFIG_QNX6FS_DEBUG is not set
+CONFIG_ROMFS_FS=m
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
+CONFIG_PSTORE_COMPRESS=y
+# CONFIG_PSTORE_CONSOLE is not set
+# CONFIG_PSTORE_PMSG is not set
+CONFIG_PSTORE_RAM=m
+CONFIG_PSTORE_ZONE=m
+CONFIG_PSTORE_BLK=m
+CONFIG_PSTORE_BLK_BLKDEV=""
+CONFIG_PSTORE_BLK_KMSG_SIZE=64
+CONFIG_PSTORE_BLK_MAX_REASON=2
+CONFIG_SYSV_FS=m
+CONFIG_UFS_FS=m
+CONFIG_UFS_FS_WRITE=y
+# CONFIG_UFS_DEBUG is not set
+CONFIG_EROFS_FS=m
+# CONFIG_EROFS_FS_DEBUG is not set
+CONFIG_EROFS_FS_XATTR=y
+CONFIG_EROFS_FS_POSIX_ACL=y
+CONFIG_EROFS_FS_SECURITY=y
+# CONFIG_EROFS_FS_ZIP is not set
+# CONFIG_EROFS_FS_ONDEMAND is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V2=m
+CONFIG_NFS_V3=m
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=m
+CONFIG_NFS_SWAP=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=m
+CONFIG_PNFS_BLOCK=m
+CONFIG_PNFS_FLEXFILE_LAYOUT=m
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+CONFIG_NFS_V4_1_MIGRATION=y
+CONFIG_NFS_V4_SECURITY_LABEL=y
+CONFIG_NFS_FSCACHE=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFS_DEBUG=y
+CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+CONFIG_NFS_V4_2_READ_PLUS=y
+CONFIG_NFSD=m
+# CONFIG_NFSD_V2 is not set
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD_PNFS=y
+CONFIG_NFSD_BLOCKLAYOUT=y
+CONFIG_NFSD_SCSILAYOUT=y
+CONFIG_NFSD_FLEXFILELAYOUT=y
+# CONFIG_NFSD_V4_2_INTER_SSC is not set
+CONFIG_NFSD_V4_SECURITY_LABEL=y
+# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set
+CONFIG_GRACE_PERIOD=m
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_NFS_V4_2_SSC_HELPER=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_SUNRPC_SWAP=y
+CONFIG_RPCSEC_GSS_KRB5=m
+CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y
+# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set
+# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set
+# CONFIG_RPCSEC_GSS_KRB5_KUNIT_TEST is not set
+CONFIG_SUNRPC_DEBUG=y
+CONFIG_CEPH_FS=m
+CONFIG_CEPH_FSCACHE=y
+CONFIG_CEPH_FS_POSIX_ACL=y
+CONFIG_CEPH_FS_SECURITY_LABEL=y
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS2=y
+CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
+CONFIG_CIFS_UPCALL=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_CIFS_DEBUG=y
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
+CONFIG_CIFS_DFS_UPCALL=y
+# CONFIG_CIFS_SWN_UPCALL is not set
+CONFIG_CIFS_FSCACHE=y
+CONFIG_SMB_SERVER=m
+CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
+CONFIG_SMB_SERVER_KERBEROS5=y
+CONFIG_SMBFS=m
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+# CONFIG_AFS_DEBUG is not set
+CONFIG_AFS_FSCACHE=y
+# CONFIG_AFS_DEBUG_CURSOR is not set
+CONFIG_9P_FS=m
+CONFIG_9P_FSCACHE=y
+CONFIG_9P_FS_POSIX_ACL=y
+CONFIG_9P_FS_SECURITY=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
+CONFIG_NLS_UTF8=m
+CONFIG_NLS_UCS2_UTILS=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+CONFIG_UNICODE=y
+# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
+CONFIG_IO_WQ=y
+# end of File systems
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_KEYS_REQUEST_CACHE=y
+CONFIG_PERSISTENT_KEYRINGS=y
+CONFIG_TRUSTED_KEYS=y
+CONFIG_HAVE_TRUSTED_KEYS=y
+CONFIG_TRUSTED_KEYS_TPM=y
+CONFIG_TRUSTED_KEYS_TEE=y
+CONFIG_ENCRYPTED_KEYS=y
+# CONFIG_USER_DECRYPTED_DATA is not set
+CONFIG_KEY_DH_OPERATIONS=y
+CONFIG_SECURITY_DMESG_RESTRICT=y
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_NETWORK_XFRM=y
+CONFIG_SECURITY_PATH=y
+CONFIG_LSM_MMAP_MIN_ADDR=0
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_FORTIFY_SOURCE=y
+# CONFIG_STATIC_USERMODEHELPER is not set
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
+CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
+# CONFIG_SECURITY_SELINUX_DEBUG is not set
+CONFIG_SECURITY_SMACK=y
+# CONFIG_SECURITY_SMACK_BRINGUP is not set
+CONFIG_SECURITY_SMACK_NETFILTER=y
+CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y
+CONFIG_SECURITY_TOMOYO=y
+CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048
+CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024
+# CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER is not set
+CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init"
+CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER="/sbin/init"
+# CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING is not set
+CONFIG_SECURITY_APPARMOR=y
+# CONFIG_SECURITY_APPARMOR_DEBUG is not set
+CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
+CONFIG_SECURITY_APPARMOR_HASH=y
+CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
+CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
+CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
+# CONFIG_SECURITY_APPARMOR_KUNIT_TEST is not set
+# CONFIG_SECURITY_LOADPIN is not set
+CONFIG_SECURITY_YAMA=y
+CONFIG_SECURITY_SAFESETID=y
+# CONFIG_SECURITY_LOCKDOWN_LSM is not set
+# CONFIG_SECURITY_LANDLOCK is not set
+CONFIG_INTEGRITY=y
+CONFIG_INTEGRITY_SIGNATURE=y
+CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
+CONFIG_INTEGRITY_TRUSTED_KEYRING=y
+CONFIG_INTEGRITY_PLATFORM_KEYRING=y
+# CONFIG_INTEGRITY_MACHINE_KEYRING is not set
+CONFIG_LOAD_UEFI_KEYS=y
+CONFIG_INTEGRITY_AUDIT=y
+CONFIG_IMA=y
+# CONFIG_IMA_KEXEC is not set
+CONFIG_IMA_MEASURE_PCR_IDX=10
+CONFIG_IMA_LSM_RULES=y
+CONFIG_IMA_NG_TEMPLATE=y
+# CONFIG_IMA_SIG_TEMPLATE is not set
+CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng"
+CONFIG_IMA_DEFAULT_HASH_SHA1=y
+# CONFIG_IMA_DEFAULT_HASH_SHA256 is not set
+# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set
+CONFIG_IMA_DEFAULT_HASH="sha1"
+# CONFIG_IMA_WRITE_POLICY is not set
+# CONFIG_IMA_READ_POLICY is not set
+CONFIG_IMA_APPRAISE=y
+# CONFIG_IMA_ARCH_POLICY is not set
+# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set
+CONFIG_IMA_APPRAISE_BOOTPARAM=y
+# CONFIG_IMA_APPRAISE_MODSIG is not set
+# CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY is not set
+# CONFIG_IMA_BLACKLIST_KEYRING is not set
+# CONFIG_IMA_LOAD_X509 is not set
+CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y
+CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y
+# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
+# CONFIG_IMA_DISABLE_HTABLE is not set
+CONFIG_EVM=y
+CONFIG_EVM_ATTR_FSUUID=y
+CONFIG_EVM_EXTRA_SMACK_XATTRS=y
+# CONFIG_EVM_ADD_XATTRS is not set
+# CONFIG_EVM_LOAD_X509 is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_APPARMOR=y
+# CONFIG_DEFAULT_SECURITY_DAC is not set
+CONFIG_LSM="lockdown,yama,integrity,apparmor"
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_INIT_STACK_ALL_PATTERN is not set
+# CONFIG_INIT_STACK_ALL_ZERO is not set
+CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+# CONFIG_ZERO_CALL_USED_REGS is not set
+# end of Memory initialization
+
+#
+# Hardening of kernel data structures
+#
+# CONFIG_LIST_HARDENED is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# end of Hardening of kernel data structures
+
+CONFIG_RANDSTRUCT_NONE=y
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_XOR_BLOCKS=y
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA=y
+CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA=y
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_SIG=y
+CONFIG_CRYPTO_SIG2=y
+CONFIG_CRYPTO_SKCIPHER=y
+CONFIG_CRYPTO_SKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_PCRYPT=m
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_ENGINE=m
+# end of Crypto core or helper
+
+#
+# Public-key cryptography
+#
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
+CONFIG_CRYPTO_ECC=m
+CONFIG_CRYPTO_ECDH=m
+CONFIG_CRYPTO_ECDSA=m
+CONFIG_CRYPTO_ECRDSA=m
+CONFIG_CRYPTO_CURVE25519=m
+# end of Public-key cryptography
+
+#
+# Block ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_AES_TI=m
+CONFIG_CRYPTO_ANUBIS=m
+# CONFIG_CRYPTO_ARIA is not set
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SM4=m
+CONFIG_CRYPTO_SM4_GENERIC=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+# end of Block ciphers
+
+#
+# Length-preserving ciphers and modes
+#
+CONFIG_CRYPTO_ADIANTUM=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_CHACHA20=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_HCTR2 is not set
+CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_NHPOLY1305=y
+# end of Length-preserving ciphers and modes
+
+#
+# AEAD (authenticated encryption with associated data) ciphers
+#
+CONFIG_CRYPTO_AEGIS128=m
+CONFIG_CRYPTO_AEGIS128_SIMD=y
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_GENIV=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_CRYPTO_ESSIV=m
+# end of AEAD (authenticated encryption with associated data) ciphers
+
+#
+# Hashes, digests, and MACs
+#
+CONFIG_CRYPTO_BLAKE2B=y
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_GHASH=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_POLY1305=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SM3=m
+CONFIG_CRYPTO_SM3_GENERIC=m
+CONFIG_CRYPTO_STREEBOG=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_XXHASH=y
+# end of Hashes, digests, and MACs
+
+#
+# CRCs (cyclic redundancy checks)
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+# end of CRCs (cyclic redundancy checks)
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_842=m
+CONFIG_CRYPTO_LZ4=m
+CONFIG_CRYPTO_LZ4HC=m
+CONFIG_CRYPTO_ZSTD=y
+# end of Compression
+
+#
+# Random number generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+# CONFIG_CRYPTO_DRBG_HASH is not set
+# CONFIG_CRYPTO_DRBG_CTR is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
+CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
+CONFIG_CRYPTO_JITTERENTROPY_OSR=1
+CONFIG_CRYPTO_KDF800108_CTR=y
+# end of Random number generation
+
+#
+# Userspace interface
+#
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API_RNG=m
+# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
+CONFIG_CRYPTO_USER_API_AEAD=m
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+# end of Userspace interface
+
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_NHPOLY1305_NEON=y
+CONFIG_CRYPTO_CHACHA20_NEON=y
+
+#
+# Accelerated Cryptographic Algorithms for CPU (arm64)
+#
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_POLY1305_NEON=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64=y
+CONFIG_CRYPTO_SHA512_ARM64_CE=m
+CONFIG_CRYPTO_SHA3_ARM64=m
+# CONFIG_CRYPTO_SM3_NEON is not set
+CONFIG_CRYPTO_SM3_ARM64_CE=m
+# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
+CONFIG_CRYPTO_AES_ARM64_BS=y
+CONFIG_CRYPTO_SM4_ARM64_CE=m
+# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
+# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
+# end of Accelerated Cryptographic Algorithms for CPU (arm64)
+
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_ATMEL_I2C=m
+CONFIG_CRYPTO_DEV_ATMEL_ECC=m
+CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
+# CONFIG_CRYPTO_DEV_CCP is not set
+CONFIG_CRYPTO_DEV_NITROX=m
+CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
+# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
+# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
+# CONFIG_CRYPTO_DEV_QAT_C62X is not set
+# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
+# CONFIG_CRYPTO_DEV_QAT_420XX is not set
+# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
+# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
+# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
+CONFIG_CRYPTO_DEV_CAVIUM_ZIP=m
+CONFIG_CRYPTO_DEV_ROCKCHIP=m
+# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
+CONFIG_CRYPTO_DEV_ROCKCHIP2=m
+# CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set
+CONFIG_CRYPTO_DEV_VIRTIO=m
+CONFIG_CRYPTO_DEV_SAFEXCEL=m
+CONFIG_CRYPTO_DEV_CCREE=m
+CONFIG_CRYPTO_DEV_HISI_SEC=m
+CONFIG_CRYPTO_DEV_HISI_SEC2=m
+CONFIG_CRYPTO_DEV_HISI_QM=m
+CONFIG_CRYPTO_DEV_HISI_ZIP=m
+CONFIG_CRYPTO_DEV_HISI_HPRE=m
+CONFIG_CRYPTO_DEV_HISI_TRNG=m
+# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+CONFIG_PKCS7_MESSAGE_PARSER=y
+CONFIG_PKCS7_TEST_KEY=m
+CONFIG_SIGNED_PE_FILE_VERIFICATION=y
+# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
+
+#
+# Certificates for signature checking
+#
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSTEM_TRUSTED_KEYS=""
+CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
+CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096
+CONFIG_SECONDARY_TRUSTED_KEYRING=y
+# CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN is not set
+CONFIG_SYSTEM_BLACKLIST_KEYRING=y
+CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
+# CONFIG_SYSTEM_REVOCATION_LIST is not set
+# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set
+# end of Certificates for signature checking
+
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=y
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_LINEAR_RANGES=y
+CONFIG_PACKING=y
+CONFIG_BITREVERSE=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_CORDIC=m
+CONFIG_PRIME_NUMBERS=m
+CONFIG_RATIONAL=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
+CONFIG_INDIRECT_PIO=y
+# CONFIG_TRACE_MMIO_ACCESS is not set
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC64=y
+CONFIG_CRC4=m
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_CRC8=m
+CONFIG_XXHASH=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_AUDIT_COMPAT_GENERIC=y
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_842_COMPRESS=m
+CONFIG_842_DECOMPRESS=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_COMPRESS=y
+CONFIG_LZ4HC_COMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_MICROLZMA=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_TEST=m
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_ZSTD=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_REED_SOLOMON=m
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC16=y
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_BTREE=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_CLOSURES=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_DMA_OPS=y
+CONFIG_NEED_SG_DMA_FLAGS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_SWIOTLB=y
+# CONFIG_SWIOTLB_DYNAMIC is not set
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMA_NEED_SYNC=y
+CONFIG_DMA_RESTRICTED_POOL=y
+CONFIG_DMA_NONCOHERENT_MMAP=y
+CONFIG_DMA_COHERENT_POOL=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_CMA=y
+# CONFIG_DMA_NUMA_CMA is not set
+
+#
+# Default contiguous memory area size:
+#
+CONFIG_CMA_SIZE_MBYTES=384
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_ALIGNMENT=8
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_DMA_MAP_BENCHMARK is not set
+CONFIG_SGL_ALLOC=y
+CONFIG_CHECK_SIGNATURE=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_GLOB=y
+CONFIG_GLOB_SELFTEST=m
+CONFIG_NLATTR=y
+CONFIG_LRU_CACHE=m
+CONFIG_CLZ_TAB=y
+CONFIG_IRQ_POLL=y
+CONFIG_MPILIB=y
+CONFIG_SIGNATURE=y
+CONFIG_DIMLIB=y
+CONFIG_LIBFDT=y
+CONFIG_OID_REGISTRY=y
+CONFIG_UCS2_STRING=y
+CONFIG_HAVE_GENERIC_VDSO=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+CONFIG_FONT_ACORN_8x8=y
+# CONFIG_FONT_MINI_4x6 is not set
+CONFIG_FONT_6x10=y
+# CONFIG_FONT_10x18 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+CONFIG_FONT_TER16x32=y
+# CONFIG_FONT_6x8 is not set
+CONFIG_SG_SPLIT=y
+CONFIG_SG_POOL=y
+CONFIG_MEMREGION=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_STACKDEPOT=y
+CONFIG_STACKDEPOT_MAX_FRAMES=64
+CONFIG_SBITMAP=y
+# CONFIG_LWQ_TEST is not set
+# end of Library routines
+
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_ASN1_ENCODER=y
+CONFIG_POLYNOMIAL=m
+CONFIG_FIRMWARE_TABLE=y
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+# CONFIG_STACKTRACE_BUILD_ID is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DYNAMIC_DEBUG_CORE=y
+CONFIG_SYMBOLIC_ERRNAME=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# end of printk and dmesg options
+
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MISC=y
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_AS_HAS_NON_CONST_ULEB128=y
+CONFIG_DEBUG_INFO_NONE=y
+# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+# CONFIG_DEBUG_INFO_DWARF5 is not set
+CONFIG_FRAME_WARN=2048
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_HEADERS_INSTALL is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_VMLINUX_MAP is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+#
+# Generic Kernel Debugging Instruments
+#
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
+# CONFIG_DEBUG_FS_ALLOW_NONE is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARCH_HAS_UBSAN=y
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_ARCH_KCSAN=y
+CONFIG_HAVE_KCSAN_COMPILER=y
+# CONFIG_KCSAN is not set
+# end of Generic Kernel Debugging Instruments
+
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# CONFIG_DEBUG_NET is not set
+# end of Networking Debugging
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_TABLE_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_PAGE_REF is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
+CONFIG_ARCH_HAS_DEBUG_WX=y
+# CONFIG_DEBUG_WX is not set
+CONFIG_GENERIC_PTDUMP=y
+# CONFIG_PTDUMP_DEBUGFS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_PER_VMA_LOCK_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SHRINKER_DEBUG is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_VM_PGTABLE is not set
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+# CONFIG_DEBUG_VIRTUAL is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_MEM_ALLOC_PROFILING is not set
+CONFIG_HAVE_ARCH_KASAN=y
+CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
+CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
+CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_CC_HAS_KASAN_SW_TAGS=y
+CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
+# CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
+# end of Memory Debugging
+
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Oops, Lockups and Hangs
+#
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_SOFTLOCKUP_DETECTOR is not set
+CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_WQ_WATCHDOG is not set
+# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
+CONFIG_TEST_LOCKUP=m
+# end of Debug Oops, Lockups and Hangs
+
+#
+# Scheduler Debugging
+#
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHED_INFO=y
+# CONFIG_SCHEDSTATS is not set
+# end of Scheduler Debugging
+
+# CONFIG_DEBUG_TIMEKEEPING is not set
+# CONFIG_DEBUG_PREEMPT is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+# CONFIG_DEBUG_IRQFLAGS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+
+#
+# Debug kernel data structures
+#
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CLOSURES is not set
+# CONFIG_DEBUG_MAPLE_TREE is not set
+# end of Debug kernel data structures
+
+#
+# RCU Debugging
+#
+# CONFIG_RCU_SCALE_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_REF_SCALE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
+# CONFIG_RCU_CPU_STALL_CPUTIME is not set
+CONFIG_RCU_TRACE=y
+# CONFIG_RCU_EQS_DEBUG is not set
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_DEBUG_CGROUP_REF is not set
+CONFIG_USER_STACKTRACE_SUPPORT=y
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_BOOTTIME_TRACING is not set
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_HWLAT_TRACER is not set
+# CONFIG_OSNOISE_TRACER is not set
+# CONFIG_TIMERLAT_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_FTRACE_SYSCALLS is not set
+# CONFIG_TRACER_SNAPSHOT is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_KPROBE_EVENTS=y
+CONFIG_UPROBE_EVENTS=y
+CONFIG_BPF_EVENTS=y
+CONFIG_DYNAMIC_EVENTS=y
+CONFIG_PROBE_EVENTS=y
+# CONFIG_BPF_KPROBE_OVERRIDE is not set
+# CONFIG_SYNTH_EVENTS is not set
+# CONFIG_USER_EVENTS is not set
+# CONFIG_HIST_TRIGGERS is not set
+# CONFIG_TRACE_EVENT_INJECT is not set
+# CONFIG_TRACEPOINT_BENCHMARK is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_TRACE_EVAL_MAP_FILE is not set
+# CONFIG_RING_BUFFER_STARTUP_TEST is not set
+# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
+# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
+# CONFIG_KPROBE_EVENT_GEN_TEST is not set
+# CONFIG_RV is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y
+CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+
+#
+# arm64 Debugging
+#
+# CONFIG_PID_IN_CONTEXTIDR is not set
+# CONFIG_ARM64_RELOC_TEST is not set
+# CONFIG_CORESIGHT is not set
+# end of arm64 Debugging
+
+#
+# Kernel Testing and Coverage
+#
+CONFIG_KUNIT=m
+# CONFIG_KUNIT_DEBUGFS is not set
+# CONFIG_KUNIT_TEST is not set
+# CONFIG_KUNIT_EXAMPLE_TEST is not set
+# CONFIG_KUNIT_ALL_TESTS is not set
+# CONFIG_KUNIT_DEFAULT_ENABLED is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+CONFIG_FUNCTION_ERROR_INJECTION=y
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+# CONFIG_KCOV is not set
+CONFIG_RUNTIME_TESTING_MENU=y
+# CONFIG_TEST_DHRY is not set
+# CONFIG_LKDTM is not set
+# CONFIG_CPUMASK_KUNIT_TEST is not set
+# CONFIG_TEST_LIST_SORT is not set
+CONFIG_TEST_MIN_HEAP=m
+# CONFIG_TEST_SORT is not set
+CONFIG_TEST_DIV64=m
+# CONFIG_TEST_IOV_ITER is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_TEST_REF_TRACKER is not set
+# CONFIG_RBTREE_TEST is not set
+CONFIG_REED_SOLOMON_TEST=m
+# CONFIG_INTERVAL_TREE_TEST is not set
+# CONFIG_PERCPU_TEST is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+CONFIG_ASYNC_RAID6_TEST=m
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_STRING_KUNIT_TEST is not set
+# CONFIG_STRING_HELPERS_KUNIT_TEST is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_PRINTF is not set
+CONFIG_TEST_SCANF=m
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_UUID is not set
+CONFIG_TEST_XARRAY=m
+# CONFIG_TEST_MAPLE_TREE is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_IDA is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_BITOPS is not set
+CONFIG_TEST_VMALLOC=m
+CONFIG_TEST_BPF=m
+CONFIG_TEST_BLACKHOLE_DEV=m
+# CONFIG_FIND_BIT_BENCHMARK is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_SYSCTL is not set
+# CONFIG_BITFIELD_KUNIT is not set
+# CONFIG_CHECKSUM_KUNIT is not set
+# CONFIG_HASH_KUNIT_TEST is not set
+CONFIG_RESOURCE_KUNIT_TEST=m
+# CONFIG_SYSCTL_KUNIT_TEST is not set
+# CONFIG_LIST_KUNIT_TEST is not set
+# CONFIG_HASHTABLE_KUNIT_TEST is not set
+# CONFIG_LINEAR_RANGES_TEST is not set
+CONFIG_CMDLINE_KUNIT_TEST=m
+# CONFIG_BITS_TEST is not set
+CONFIG_SLUB_KUNIT_TEST=m
+CONFIG_RATIONAL_KUNIT_TEST=m
+CONFIG_MEMCPY_KUNIT_TEST=m
+# CONFIG_IS_SIGNED_TYPE_KUNIT_TEST is not set
+# CONFIG_OVERFLOW_KUNIT_TEST is not set
+# CONFIG_STACKINIT_KUNIT_TEST is not set
+# CONFIG_FORTIFY_KUNIT_TEST is not set
+# CONFIG_SIPHASH_KUNIT_TEST is not set
+# CONFIG_USERCOPY_KUNIT_TEST is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_TEST_STATIC_KEYS is not set
+# CONFIG_TEST_DYNAMIC_DEBUG is not set
+# CONFIG_TEST_KMOD is not set
+CONFIG_TEST_MEMCAT_P=m
+# CONFIG_TEST_MEMINIT is not set
+# CONFIG_TEST_FREE_PAGES is not set
+# CONFIG_TEST_FPU is not set
+# CONFIG_TEST_OBJPOOL is not set
+CONFIG_ARCH_USE_MEMTEST=y
+CONFIG_MEMTEST=y
+# end of Kernel Testing and Coverage
+
+#
+# Rust hacking
+#
+# end of Rust hacking
+# end of Kernel hacking
diff --git a/config/sources/families/meson-axg.conf b/config/sources/families/meson-axg.conf
new file mode 100644
index 000000000000..1449aba633ba
--- /dev/null
+++ b/config/sources/families/meson-axg.conf
@@ -0,0 +1,23 @@
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2024 Armbian
+#
+# This file is a part of the Armbian Build Framework
+# https://github.com/armbian/build/
+#
+
+# shellcheck source=config/sources/families/include/meson64_common.inc
+source "${BASH_SOURCE%/*}/include/meson64_common.inc"
+if [[ "$BOARD" == "gateway-gz80x" ]]; then
+	UBOOT_TARGET_MAP="u-boot-dtb.img;;u-boot.bin u-boot-dtb.img"
+fi
+
+uboot_custom_postprocess() {
+	if [[ "$BOARD" == "gateway-gz80x" ]]; then
+		uboot_axg_postprocess_ng "$SRC/cache/sources/amlogic-boot-fip/jethub-j100"
+	else
+		echo "Don't know how to handle FIP trees for board '${BOARD}'"
+		exit 1
+	fi
+}
diff --git a/config/sources/git_sources.json b/config/sources/git_sources.json
new file mode 100644
index 000000000000..80905987897d
--- /dev/null
+++ b/config/sources/git_sources.json
@@ -0,0 +1,202 @@
+[
+  {
+    "source": "https://github.com/armbian/firmware",
+    "branch": "master",
+    "sha1": "511deee7289cb9a5dee6ba142d18a09933d5ba00"
+  },
+  {
+    "source": "https://github.com/armbian/config",
+    "branch": "master",
+    "sha1": "59ed13e1598431b6016a7bb8ea5615bb52dbd351"
+  },
+  {
+    "source": "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git",
+    "branch": "main",
+    "sha1": "5649ca751a23ff3b4b2b2caa4d5978af3afb5c1b"
+  },
+  {
+    "source": "https://github.com/starfive-tech/linux",
+    "branch": "JH7110_VisionFive2_devel",
+    "sha1": "a61d1d826ca3060fd76ab31d37c691fc09b52fc0"
+  },
+  {
+    "source": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
+    "branch": "linux-6.10.y",
+    "sha1": "7ba498d9d1bb67bcbc2a79f19a9054cdc8b95098"
+  },
+  {
+    "source": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
+    "branch": "linux-6.6.y",
+    "sha1": "4c1a2d4cd9a5b6c55739a80c5b9efbca322adad7"
+  },
+  {
+    "source": "https://github.com/AvaotaSBC/linux.git",
+    "branch": "linux-5.15",
+    "sha1": "af5fc555764e1ad015ba43f9b5151ee9180c0be6"
+  },
+  {
+    "source": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
+    "branch": "linux-6.1.y",
+    "sha1": "ee5e09825b810498caeaaa3d46a3410768471053"
+  },
+  {
+    "source": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
+    "branch": "linux-6.9.y",
+    "sha1": "bb67b270b37e8bd9c96829d58ffe758635651e90"
+  },
+  {
+    "source": "https://github.com/armbian/linux-rockchip.git",
+    "branch": "rk-6.1-rkr3",
+    "sha1": "30da05a12335a6ccc1ca262e2b783f99b69731ec"
+  },
+  {
+    "source": "https://github.com/radxa/u-boot.git",
+    "branch": "next-dev-v2024.03",
+    "sha1": "f73b1eede495c82cd5d7ed20cc484a22d670136f"
+  },
+  {
+    "source": "https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux.git",
+    "branch": "rk3588-v6.9",
+    "sha1": "23bb9c65a88c114bbe945b7ef5366bb02d3d9b80"
+  },
+  {
+    "source": "https://github.com/edk2-porting/linux-next",
+    "branch": "integration/ayn-odin2",
+    "sha1": "9a94c7a1294c58ffa6d19bc5cc50b2009ffb40c9"
+  },
+  {
+    "source": "https://github.com/khadas/linux.git",
+    "branch": "khadas-vims-5.15.y",
+    "sha1": "dd276a72527a5d00f09cf4105a8acfadb5c49c0b"
+  },
+  {
+    "source": "https://github.com/khadas/common_drivers",
+    "branch": "khadas-vims-5.15.y",
+    "sha1": "5e2f70d55dd211d15b3db71ffba671003bf3e512"
+  },
+  {
+    "source": "https://source.denx.de/u-boot/u-boot.git",
+    "branch": "v2024.01",
+    "sha1": "aa6d5f7192d5860458b5ef0163aad1d94e9bde70"
+  },
+  {
+    "source": "https://github.com/SolidRun/u-boot.git",
+    "branch": "v2018.01-solidrun-imx6",
+    "sha1": "5b6bc28ead0674ed9c9b7afa35f35828aad07cda"
+  },
+  {
+    "source": "https://github.com/functionland/u-boot.git",
+    "branch": "next-dev",
+    "sha1": "46da2bfe5068535caf919a36c6fcc5a7e744a04b"
+  },
+  {
+    "source": "https://github.com/stvhay/u-boot.git",
+    "branch": "rockchip-rk3588-unified",
+    "sha1": "2f6e967dc901ae570f522d1b47309e7c34acf542"
+  },
+  {
+    "source": "https://github.com/khadas/u-boot.git",
+    "branch": "khadas-edges-v2017.09",
+    "sha1": "b70d025cfadadb132f78fe01e75e007f4070bd10"
+  },
+  {
+    "source": "https://github.com/khadas/u-boot.git",
+    "branch": "khadas-vims-v2019.01",
+    "sha1": "aae94d9eb9f1fa2c01e2c5dba9c57ef37ac91aea"
+  },
+  {
+    "source": "https://github.com/radxa/u-boot.git",
+    "branch": "rk35xx-2024.01",
+    "sha1": "31b85240876dc43492b0826a74b99c23fbf6ed9d"
+  },
+  {
+    "source": "https://github.com/chainsx/thead-kernel",
+    "branch": "th1520",
+    "sha1": "a76d97e234b6613fc20a3dcbfc99128fe9b05e7a"
+  },
+  {
+    "source": "https://github.com/chainsx/thead-u-boot",
+    "branch": "extlinux",
+    "sha1": "990e122d26d1ef94f4e0e1bbf5d7df58e8393eee"
+  },
+  {
+    "source": "https://github.com/tq-systems/u-boot-tqmaxx.git",
+    "branch": "TQMa8-v2020.04_imx_5.4.70_2.3.0",
+    "sha1": "1e3fada66dba19bd4e06f1cb33f36ff025f95146"
+  },
+  {
+    "source": "https://github.com/Kwiboo/u-boot-rockchip.git",
+    "branch": "rk3xxx-2024.04",
+    "sha1": "830cfcfdf54a1f08a3ca7fc17e69b4bc18cece50"
+  },
+  {
+    "source": "https://github.com/Kwiboo/u-boot-rockchip.git",
+    "branch": "rk3xxx-2024.07",
+    "sha1": "2e2ae1fb69a25217640bfe2fb9abaf9f4fbacead"
+  },
+  {
+    "source": "https://github.com/hardkernel/u-boot.git",
+    "branch": "odroidc-v2011.03",
+    "sha1": "b7b8dc21b64b9494618325c9b4d2fbae728aeed6"
+  },
+  {
+    "source": "https://github.com/hardkernel/u-boot.git",
+    "branch": "odroidxu4-v2017.05",
+    "sha1": "42ac93dcfbbb8a08c2bdc02e19f96eb35a81891a"
+  },
+  {
+    "source": "https://github.com/hardkernel/linux",
+    "branch": "odroid-6.6.y",
+    "sha1": "e5dcbb1ea6b49685611bcc5553900291855895b4"
+  },
+  {
+    "source": "https://github.com/orangepi-xunlong/u-boot-orangepi.git",
+    "branch": "v2017.09-rk3588",
+    "sha1": "5e34a2115e1dd9128892b828d869f74677361a78"
+  },
+  {
+    "source": "https://github.com/chainsx/phytium-linux-kernel",
+    "branch": "linux-5.10",
+    "sha1": "b17835d38155a8c2bcb3e2d0f3f55989bf2f1b98"
+  },
+  {
+    "source": "https://github.com/chainsx/phytium-linux-kernel",
+    "branch": "linux-6.6",
+    "sha1": "b9b9d633ab5b213fe492a62f35c6cfd5a2614f42"
+  },
+  {
+    "source": "https://github.com/raspberrypi/linux",
+    "branch": "rpi-6.1.y",
+    "sha1": "fbd8b3facb36ce888b1cdcf5f45a78475a8208f2"
+  },
+  {
+    "source": "https://github.com/raspberrypi/linux",
+    "branch": "rpi-6.6.y",
+    "sha1": "15ca476264094b25d0a210109a061192a468117b"
+  },
+  {
+    "source": "https://github.com/raspberrypi/linux",
+    "branch": "rpi-6.10.y",
+    "sha1": "084962e99477691e0abe232731e3a24b14b05147"
+  },
+  {
+    "source": "https://github.com/jhovold/linux.git",
+    "branch": "wip/sc8280xp-6.10",
+    "sha1": "f0239008542ebdcd4a94755124b5700649df5c39"
+  },
+  {
+    "source": "https://github.com/jglathe/linux_ms_dev_kit.git",
+    "branch": "jg/wdk2023-gunyah-6.7-rc6",
+    "sha1": "401bea57d6b96f440142b9039d483c671c4a9587"
+  },
+  {
+    "source": "https://github.com/SolidRun/u-boot",
+    "branch": "v2018.01-solidrun-a38x",
+    "sha1": "a8004c1f1112ca2f867badccce5a76f052034853"
+  },
+  {
+    "source": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
+    "branch": "linux-5.15.y",
+    "sha1": "fa93fa65db6e232b5f2226dd86c9f066ec6dfd97"
+  }
+]
diff --git a/patch/kernel/archive/bcm2711-6.10/0001-Make-proc-cpuinfo-consistent-on-arm64-and-arm.patch b/patch/kernel/archive/bcm2711-6.10/0001-Make-proc-cpuinfo-consistent-on-arm64-and-arm.patch
new file mode 100644
index 000000000000..fda816869467
--- /dev/null
+++ b/patch/kernel/archive/bcm2711-6.10/0001-Make-proc-cpuinfo-consistent-on-arm64-and-arm.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: graysky <graysky@archlinux.us>
+Date: Mon, 7 Dec 2020 13:03:40 -0500
+Subject: Make /proc/cpuinfo consistent on arm64 and arm
+
+Signed-off-by: graysky <graysky@archlinux.us>
+---
+ arch/arm64/kernel/cpuinfo.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
+index ee36fa8be3af..049bdca2655c 100644
+--- a/arch/arm64/kernel/cpuinfo.c
++++ b/arch/arm64/kernel/cpuinfo.c
+@@ -193,9 +193,8 @@ static int c_show(struct seq_file *m, void *v)
+ 		 * "processor".  Give glibc what it expects.
+ 		 */
+ 		seq_printf(m, "processor\t: %d\n", i);
+-		if (compat)
+-			seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
+-				   MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
++		seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
++			   MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
+ 
+ 		seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
+ 			   loops_per_jiffy / (500000UL/HZ),
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/bcm2711-6.10/001-force-platform-selection-brcm-soc-support.disabled b/patch/kernel/archive/bcm2711-6.10/001-force-platform-selection-brcm-soc-support.disabled
new file mode 100644
index 000000000000..01ef6aecd3b6
--- /dev/null
+++ b/patch/kernel/archive/bcm2711-6.10/001-force-platform-selection-brcm-soc-support.disabled
@@ -0,0 +1,22 @@
+diff -Naur a/arch/arm/Kconfig b/arch/arm/Kconfig
+--- a/arch/arm/Kconfig	2022-12-11 17:15:18.000000000 -0500
++++ b/arch/arm/Kconfig	2022-12-13 10:24:24.085749880 -0500
+@@ -2,6 +2,7 @@
+ config ARM
+ 	bool
+ 	default y
++	select ARCH_BCM
+ 	select ARCH_32BIT_OFF_T
+ 	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
+ 	select ARCH_HAS_BINFMT_FLAT
+diff -Naur a/arch/arm64/Kconfig b/arch/arm64/Kconfig
+--- a/arch/arm64/Kconfig	2022-12-11 17:15:18.000000000 -0500
++++ b/arch/arm64/Kconfig	2022-12-13 10:28:40.045233987 -0500
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ config ARM64
+ 	def_bool y
++	select ARCH_BCM
+ 	select ACPI_APMT if ACPI
+ 	select ACPI_CCA_REQUIRED if ACPI
+ 	select ACPI_GENERIC_GSI if ACPI
diff --git a/patch/kernel/archive/bcm2711-6.10/1003-remote-wakeup.patch b/patch/kernel/archive/bcm2711-6.10/1003-remote-wakeup.patch
new file mode 100644
index 000000000000..39ef8d9e3a24
--- /dev/null
+++ b/patch/kernel/archive/bcm2711-6.10/1003-remote-wakeup.patch
@@ -0,0 +1,193 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+Date: Mon, 29 Aug 2022 08:43:24 +0200
+Subject: [ARCHEOLOGY] Add patches needed for Pi-KVM on Rpi4 (#4127)
+
+> X-Git-Archeology: > recovered message: > * Add patches needed for Pi-KVM on Rpi4
+> X-Git-Archeology: > recovered message: > * Remove patch that does not belong here
+> X-Git-Archeology: > recovered message: > * Update config
+> X-Git-Archeology: > recovered message: > * Update edge config
+> X-Git-Archeology: - Revision 2fb3aaaf86a7463ef1d26f4d623e1d3289ea4f25: https://github.com/armbian/build/commit/2fb3aaaf86a7463ef1d26f4d623e1d3289ea4f25
+> X-Git-Archeology:   Date: Mon, 29 Aug 2022 08:43:24 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Add patches needed for Pi-KVM on Rpi4 (#4127)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision acf5810cbe38c7578907ecd06e61abb0a446df1e: https://github.com/armbian/build/commit/acf5810cbe38c7578907ecd06e61abb0a446df1e
+> X-Git-Archeology:   Date: Sat, 11 Mar 2023 19:19:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igor@armbian.com>
+> X-Git-Archeology:   Subject: Move Rpi kernels to 6.2, move current to legacy (#4898)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 5f2a1af2193187f0b994d6f163b94f370a01134f: https://github.com/armbian/build/commit/5f2a1af2193187f0b994d6f163b94f370a01134f
+> X-Git-Archeology:   Date: Fri, 28 Apr 2023 21:32:52 +0200
+> X-Git-Archeology:   From: Ricardo Pardini <ricardo@pardini.net>
+> X-Git-Archeology:   Subject: `bcm2711`/`edge`: bump to `6.3` (`rpi4b`, RPi Foundation Kernel)
+> X-Git-Archeology:
+---
+ drivers/usb/dwc2/gadget.c           | 73 ++++++++++
+ drivers/usb/gadget/function/f_hid.c | 14 ++
+ drivers/usb/gadget/function/u_hid.h |  1 +
+ 3 files changed, 88 insertions(+)
+
+diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
+index 8b15742d9e8a..a7d997a205d5 100644
+--- a/drivers/usb/dwc2/gadget.c
++++ b/drivers/usb/dwc2/gadget.c
+@@ -4763,6 +4763,78 @@ static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed sp
+ 	spin_unlock_irqrestore(&hsotg->lock, flags);
+ }
+ 
++/**
++ * dwc2_hsotg_wakeup - send wakeup signal to the host
++ * @gadget: The usb gadget state
++ *
++ * If the gadget is in device mode and in the L1 or L2 state,
++ * it sends a wakeup signal to the host.
++ */
++static int dwc2_hsotg_wakeup(struct usb_gadget *gadget)
++{
++	struct dwc2_hsotg *hsotg = to_hsotg(gadget);
++	int ret = -1;
++	unsigned long flags;
++
++	spin_lock_irqsave(&hsotg->lock, flags);
++
++	if (!hsotg->remote_wakeup_allowed) {
++		dev_dbg(hsotg->dev,
++			"wakeup: signalling skipped: is not allowed by host\n");
++		goto skip;
++	}
++	if (hsotg->lx_state != DWC2_L1 && hsotg->lx_state != DWC2_L2) {
++		dev_dbg(hsotg->dev,
++			"wakeup: signalling skipped: gadget not in L1/L2 state: %d\n", hsotg->lx_state);
++		goto skip;
++	}
++	if (!dwc2_is_device_mode(hsotg)) {
++		dev_dbg(hsotg->dev,
++			"wakeup: signalling skipped: gadget not in device mode\n");
++		goto skip;
++	}
++
++	/*if (hsotg->in_ppd) {
++		if (dwc2_exit_partial_power_down(hsotg, 1, true))
++			dev_err(hsotg->dev, "wakeup: exit partial_power_down failed\n");
++		call_gadget(hsotg, resume);
++	}*/
++	if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended) {
++		u32 pcgctl;
++
++		dev_dbg(hsotg->dev, "wakeup: exiting device clock gating\n");
++
++		/* Clear the Gate hclk. */
++		pcgctl = dwc2_readl(hsotg, PCGCTL);
++		pcgctl &= ~PCGCTL_GATEHCLK;
++		dwc2_writel(hsotg, pcgctl, PCGCTL);
++		udelay(5);
++
++		/* Phy Clock bit. */
++		pcgctl = dwc2_readl(hsotg, PCGCTL);
++		pcgctl &= ~PCGCTL_STOPPCLK;
++		dwc2_writel(hsotg, pcgctl, PCGCTL);
++		udelay(5);
++
++		hsotg->bus_suspended = false;
++	}
++
++	dev_dbg(hsotg->dev, "wakeup: sending signal to the host");
++
++	dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
++	mdelay(10);
++	dwc2_clear_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
++
++	/* After the signalling, the USB core wakes up to L0 */
++	call_gadget(hsotg, resume);
++	hsotg->lx_state = DWC2_L0;
++
++	ret = 0;
++skip:
++	spin_unlock_irqrestore(&hsotg->lock, flags);
++	return ret;
++}
++
+ static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
+ 	.get_frame	= dwc2_hsotg_gadget_getframe,
+ 	.set_selfpowered	= dwc2_hsotg_set_selfpowered,
+@@ -4772,6 +4844,7 @@ static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
+ 	.udc_set_speed		= dwc2_gadget_set_speed,
+ 	.vbus_session		= dwc2_hsotg_vbus_session,
+ 	.vbus_draw		= dwc2_hsotg_vbus_draw,
++	.wakeup			= dwc2_hsotg_wakeup,
+ };
+ 
+ /**
+diff --git a/drivers/usb/gadget/function/f_hid.c b/drivers/usb/gadget/function/f_hid.c
+index ea85e2c701a1..846942e4275a 100644
+--- a/drivers/usb/gadget/function/f_hid.c
++++ b/drivers/usb/gadget/function/f_hid.c
+@@ -58,6 +58,8 @@ struct f_hidg {
+ 	 *              will be used to receive reports.
+ 	 */
+ 	bool				use_out_ep;
++	/* attempt to wake up the host before write */
++	bool				wakeup_on_write;
+ 
+ 	/* recv report */
+ 	spinlock_t			read_spinlock;
+@@ -434,10 +436,19 @@ static ssize_t f_hidg_write(struct file *file, const char __user *buffer,
+ 			    size_t count, loff_t *offp)
+ {
+ 	struct f_hidg *hidg  = file->private_data;
++	struct usb_composite_dev *cdev = hidg->func.config->cdev;
+ 	struct usb_request *req;
+ 	unsigned long flags;
+ 	ssize_t status = -ENOMEM;
+ 
++	/*
++	 * remote wakeup is allowed only when the corresponding bit
++	 * in config descriptor is set and wakeup_on_write is enabled.
++     * FIXME: cdev->config can be NULLed on disconnect.
++	 */
++	if (hidg->wakeup_on_write /*&& cdev->config->bmAttributes & 0x20*/)
++		usb_gadget_wakeup(cdev->gadget);
++
+ 	spin_lock_irqsave(&hidg->write_spinlock, flags);
+ 
+ 	if (!hidg->req) {
+@@ -1101,6 +1112,7 @@ CONFIGFS_ATTR(f_hid_opts_, name)
+ F_HID_OPT(subclass, 8, 255);
+ F_HID_OPT(protocol, 8, 255);
+ F_HID_OPT(no_out_endpoint, 8, 1);
++F_HID_OPT(wakeup_on_write, 8, 1);
+ F_HID_OPT(report_length, 16, 65535);
+ 
+ static ssize_t f_hid_opts_report_desc_show(struct config_item *item, char *page)
+@@ -1161,6 +1173,7 @@ static struct configfs_attribute *hid_attrs[] = {
+ 	&f_hid_opts_attr_subclass,
+ 	&f_hid_opts_attr_protocol,
+ 	&f_hid_opts_attr_no_out_endpoint,
++	&f_hid_opts_attr_wakeup_on_write,
+ 	&f_hid_opts_attr_report_length,
+ 	&f_hid_opts_attr_report_desc,
+ 	&f_hid_opts_attr_dev,
+@@ -1296,6 +1309,7 @@ static struct usb_function *hidg_alloc(struct usb_function_instance *fi)
+ 		}
+ 	}
+ 	hidg->use_out_ep = !opts->no_out_endpoint;
++	hidg->wakeup_on_write = opts->wakeup_on_write;
+ 
+ 	++opts->refcnt;
+ 	mutex_unlock(&opts->lock);
+diff --git a/drivers/usb/gadget/function/u_hid.h b/drivers/usb/gadget/function/u_hid.h
+index 84bb70292855..f7fcaf1eaf1d 100644
+--- a/drivers/usb/gadget/function/u_hid.h
++++ b/drivers/usb/gadget/function/u_hid.h
+@@ -21,6 +21,7 @@ struct f_hid_opts {
+ 	unsigned char			subclass;
+ 	unsigned char			protocol;
+ 	unsigned char			no_out_endpoint;
++	unsigned char			wakeup_on_write;
+ 	unsigned short			report_length;
+ 	unsigned short			report_desc_length;
+ 	unsigned char			*report_desc;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/bcm2711-6.10/2001-rename-msd.patch b/patch/kernel/archive/bcm2711-6.10/2001-rename-msd.patch
new file mode 100644
index 000000000000..1714836d0d74
--- /dev/null
+++ b/patch/kernel/archive/bcm2711-6.10/2001-rename-msd.patch
@@ -0,0 +1,50 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+Date: Mon, 29 Aug 2022 08:43:24 +0200
+Subject: [ARCHEOLOGY] Add patches needed for Pi-KVM on Rpi4 (#4127)
+
+> X-Git-Archeology: > recovered message: > * Add patches needed for Pi-KVM on Rpi4
+> X-Git-Archeology: > recovered message: > * Remove patch that does not belong here
+> X-Git-Archeology: > recovered message: > * Update config
+> X-Git-Archeology: > recovered message: > * Update edge config
+> X-Git-Archeology: - Revision 2fb3aaaf86a7463ef1d26f4d623e1d3289ea4f25: https://github.com/armbian/build/commit/2fb3aaaf86a7463ef1d26f4d623e1d3289ea4f25
+> X-Git-Archeology:   Date: Mon, 29 Aug 2022 08:43:24 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Add patches needed for Pi-KVM on Rpi4 (#4127)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision acf5810cbe38c7578907ecd06e61abb0a446df1e: https://github.com/armbian/build/commit/acf5810cbe38c7578907ecd06e61abb0a446df1e
+> X-Git-Archeology:   Date: Sat, 11 Mar 2023 19:19:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igor@armbian.com>
+> X-Git-Archeology:   Subject: Move Rpi kernels to 6.2, move current to legacy (#4898)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 5f2a1af2193187f0b994d6f163b94f370a01134f: https://github.com/armbian/build/commit/5f2a1af2193187f0b994d6f163b94f370a01134f
+> X-Git-Archeology:   Date: Fri, 28 Apr 2023 21:32:52 +0200
+> X-Git-Archeology:   From: Ricardo Pardini <ricardo@pardini.net>
+> X-Git-Archeology:   Subject: `bcm2711`/`edge`: bump to `6.3` (`rpi4b`, RPi Foundation Kernel)
+> X-Git-Archeology:
+---
+ drivers/usb/gadget/function/f_mass_storage.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/usb/gadget/function/f_mass_storage.c b/drivers/usb/gadget/function/f_mass_storage.c
+index da07e45ae6df..723d70766a49 100644
+--- a/drivers/usb/gadget/function/f_mass_storage.c
++++ b/drivers/usb/gadget/function/f_mass_storage.c
+@@ -2967,11 +2967,11 @@ void fsg_common_set_inquiry_string(struct fsg_common *common, const char *vn,
+ 	/* Prepare inquiryString */
+ 	i = get_default_bcdDevice();
+ 	snprintf(common->inquiry_string, sizeof(common->inquiry_string),
+-		 "%-8s%-16s%04x", vn ?: "Linux",
++		 "%-8s%-16s%04x", vn ?: "PiKVM",
+ 		 /* Assume product name dependent on the first LUN */
+ 		 pn ?: ((*common->luns)->cdrom
+-		     ? "File-CD Gadget"
+-		     : "File-Stor Gadget"),
++		     ? "CD-ROM Drive"
++		     : "Flash Drive"),
+ 		 i);
+ }
+ EXPORT_SYMBOL_GPL(fsg_common_set_inquiry_string);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/imx6-6.10/.placeholder b/patch/kernel/archive/imx6-6.10/.placeholder
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/patch/kernel/archive/meson-6.10/0007-dt-bindings-phy-meson8b-usb2-Add-support-for-reading.patch b/patch/kernel/archive/meson-6.10/0007-dt-bindings-phy-meson8b-usb2-Add-support-for-reading.patch
new file mode 100644
index 000000000000..b0df035c222e
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0007-dt-bindings-phy-meson8b-usb2-Add-support-for-reading.patch
@@ -0,0 +1,46 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 16 Jun 2021 20:34:01 +0200
+Subject: dt-bindings: phy: meson8b-usb2: Add support for reading the ID signal
+
+The first USB PHY on Amlogic Meson8/8b/8m2/GXBB SoCs is OTG capable.
+This means that the USB "ID" signal is routed to the PHY. Add support
+for the gpio-controller and #gpio-cells properties so the value of
+the "ID" signal can be read as a GPIO (from the PHY) for example by
+an "gpio-usb-b-connector".
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
++++ b/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
+@@ -6,6 +6,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
+ 
+ title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY
+ 
++description: |
++  OTG capable PHYs have the USB "ID" signal routed to them.
++  This can be read out via the PHY-provided GPIO controller.
++
+ maintainers:
+   - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ 
+@@ -31,6 +35,11 @@ properties:
+       - const: usb_general
+       - const: usb
+ 
++  '#gpio-cells':
++    const: 2
++
++  gpio-controller: true
++
+   resets:
+     minItems: 1
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0008-phy-amlogic-meson8b-usb2-Add-support-for-reading-the.patch b/patch/kernel/archive/meson-6.10/0008-phy-amlogic-meson8b-usb2-Add-support-for-reading-the.patch
new file mode 100644
index 000000000000..3bf658ac3c9f
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0008-phy-amlogic-meson8b-usb2-Add-support-for-reading-the.patch
@@ -0,0 +1,102 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 3 May 2020 21:40:27 +0200
+Subject: phy: amlogic: meson8b-usb2: Add support for reading the "ID" signal
+
+The first USB PHY on Amlogic Meson8/8b/8m2/GXBB SoCs is OTG capable.
+This means that the USB "ID" signal is routed to the PHY. Add support
+for the gpio-controller and #gpio-cells properties so the value of
+the "ID" signal can be read as a GPIO (from the PHY) for example by
+the usb-conn-gpio driver.
+
+The registers also have a bit for the VBUS signal. That either is not
+wired in hardware inside the SoC silicon or not wired on the boards
+(e.g. Odroid-C1), which is why it's value is not exposed for now.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/phy/amlogic/phy-meson8b-usb2.c | 42 +++++++++-
+ 1 file changed, 41 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/phy/amlogic/phy-meson8b-usb2.c b/drivers/phy/amlogic/phy-meson8b-usb2.c
+index 111111111111..222222222222 100644
+--- a/drivers/phy/amlogic/phy-meson8b-usb2.c
++++ b/drivers/phy/amlogic/phy-meson8b-usb2.c
+@@ -7,6 +7,7 @@
+ 
+ #include <linux/clk.h>
+ #include <linux/delay.h>
++#include <linux/gpio/driver.h>
+ #include <linux/io.h>
+ #include <linux/mod_devicetable.h>
+ #include <linux/module.h>
+@@ -127,6 +128,7 @@ struct phy_meson8b_usb2_priv {
+ 	struct clk					*clk_usb_general;
+ 	struct clk					*clk_usb;
+ 	struct reset_control				*reset;
++	struct gpio_chip				gpiochip;
+ 	const struct phy_meson8b_usb2_match_data	*match;
+ };
+ 
+@@ -236,12 +238,44 @@ static const struct phy_ops phy_meson8b_usb2_ops = {
+ 	.owner		= THIS_MODULE,
+ };
+ 
++static int phy_meson8b_usb2_id_gpio_get_direction(struct gpio_chip *gc,
++						  unsigned int offset)
++{
++	return GPIO_LINE_DIRECTION_IN;
++}
++
++static int phy_meson8b_usb2_id_gpio_get_value(struct gpio_chip *gc,
++					      unsigned int offset)
++{
++	struct phy_meson8b_usb2_priv *priv = gpiochip_get_data(gc);
++	unsigned int val;
++
++	regmap_read(priv->regmap, REG_ADP_BC, &val);
++
++	return (val & REG_ADP_BC_ID_DIG) ? 1 : 0;
++}
++
++static int phy_meson8b_usb2_id_gpiochip_add(struct device *dev,
++					    struct phy_meson8b_usb2_priv *priv)
++{
++	priv->gpiochip.label = dev_name(dev);
++	priv->gpiochip.parent = dev;
++	priv->gpiochip.get_direction = phy_meson8b_usb2_id_gpio_get_direction;
++	priv->gpiochip.get = phy_meson8b_usb2_id_gpio_get_value;
++	priv->gpiochip.of_gpio_n_cells = 2;
++	priv->gpiochip.base = -1;
++	priv->gpiochip.ngpio = 1;
++
++	return devm_gpiochip_add_data(dev, &priv->gpiochip, priv);
++}
++
+ static int phy_meson8b_usb2_probe(struct platform_device *pdev)
+ {
+ 	struct phy_meson8b_usb2_priv *priv;
+-	struct phy *phy;
+ 	struct phy_provider *phy_provider;
+ 	void __iomem *base;
++	struct phy *phy;
++	int ret;
+ 
+ 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+@@ -280,6 +314,12 @@ static int phy_meson8b_usb2_probe(struct platform_device *pdev)
+ 		return -EINVAL;
+ 	}
+ 
++	if (device_property_read_bool(&pdev->dev, "gpio-controller")) {
++		ret = phy_meson8b_usb2_id_gpiochip_add(&pdev->dev, priv);
++		if (ret)
++			return ret;
++	}
++
+ 	phy = devm_phy_create(&pdev->dev, NULL, &phy_meson8b_usb2_ops);
+ 	if (IS_ERR(phy)) {
+ 		return dev_err_probe(&pdev->dev, PTR_ERR(phy),
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0009-usb-common-usb-conn-gpio-Fall-back-to-polling-the-GP.patch b/patch/kernel/archive/meson-6.10/0009-usb-common-usb-conn-gpio-Fall-back-to-polling-the-GP.patch
new file mode 100644
index 000000000000..d8c082fea941
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0009-usb-common-usb-conn-gpio-Fall-back-to-polling-the-GP.patch
@@ -0,0 +1,146 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 16 Jun 2021 21:07:50 +0200
+Subject: usb: common: usb-conn-gpio: Fall back to polling the GPIO
+
+On some SoCs (for example: Amlogic Meson8/8b/8m2 and GXBB) the ID GPIO
+cannot generate an interrupt. Fall back to polling the GPIO(s) in that
+case.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/usb/common/usb-conn-gpio.c | 76 ++++++----
+ 1 file changed, 48 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/usb/common/usb-conn-gpio.c b/drivers/usb/common/usb-conn-gpio.c
+index 111111111111..222222222222 100644
+--- a/drivers/usb/common/usb-conn-gpio.c
++++ b/drivers/usb/common/usb-conn-gpio.c
+@@ -23,6 +23,7 @@
+ 
+ #define USB_GPIO_DEB_MS		20	/* ms */
+ #define USB_GPIO_DEB_US		((USB_GPIO_DEB_MS) * 1000)	/* us */
++#define USB_GPIO_POLL_MS	1000
+ 
+ #define USB_CONN_IRQF	\
+ 	(IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT)
+@@ -45,6 +46,23 @@ struct usb_conn_info {
+ 	bool initial_detection;
+ };
+ 
++static void usb_conn_queue_dwork(struct usb_conn_info *info,
++				 unsigned long delay)
++{
++	queue_delayed_work(system_power_efficient_wq, &info->dw_det, delay);
++}
++
++static void usb_conn_gpio_start_polling(struct usb_conn_info *info)
++{
++	usb_conn_queue_dwork(info, msecs_to_jiffies(USB_GPIO_POLL_MS));
++}
++
++static bool usb_conn_gpio_needs_polling(struct usb_conn_info *info)
++{
++	/* We need to poll if one of the GPIOs cannot generate an IRQ. */
++	return info->id_irq < 0 || info->vbus_irq < 0;
++}
++
+ /*
+  * "DEVICE" = VBUS and "HOST" = !ID, so we have:
+  * Both "DEVICE" and "HOST" can't be set as active at the same time
+@@ -88,7 +106,10 @@ static void usb_conn_detect_cable(struct work_struct *work)
+ 		usb_role_string(info->last_role), usb_role_string(role), id, vbus);
+ 
+ 	if (!info->initial_detection && info->last_role == role) {
+-		dev_warn(info->dev, "repeated role: %s\n", usb_role_string(role));
++		if (usb_conn_gpio_needs_polling(info))
++			usb_conn_gpio_start_polling(info);
++		else
++			dev_warn(info->dev, "repeated role: %s\n", usb_role_string(role));
+ 		return;
+ 	}
+ 
+@@ -114,12 +135,9 @@ static void usb_conn_detect_cable(struct work_struct *work)
+ 			regulator_is_enabled(info->vbus) ? "enabled" : "disabled");
+ 
+ 	power_supply_changed(info->charger);
+-}
+ 
+-static void usb_conn_queue_dwork(struct usb_conn_info *info,
+-				 unsigned long delay)
+-{
+-	queue_delayed_work(system_power_efficient_wq, &info->dw_det, delay);
++	if (usb_conn_gpio_needs_polling(info))
++		usb_conn_gpio_start_polling(info);
+ }
+ 
+ static irqreturn_t usb_conn_isr(int irq, void *dev_id)
+@@ -226,34 +244,34 @@ static int usb_conn_probe(struct platform_device *pdev)
+ 	if (info->id_gpiod) {
+ 		info->id_irq = gpiod_to_irq(info->id_gpiod);
+ 		if (info->id_irq < 0) {
+-			dev_err(dev, "failed to get ID IRQ\n");
+-			ret = info->id_irq;
+-			goto put_role_sw;
+-		}
+-
+-		ret = devm_request_threaded_irq(dev, info->id_irq, NULL,
+-						usb_conn_isr, USB_CONN_IRQF,
+-						pdev->name, info);
+-		if (ret < 0) {
+-			dev_err(dev, "failed to request ID IRQ\n");
+-			goto put_role_sw;
++			dev_info(dev,
++				 "failed to get ID IRQ - falling back to polling\n");
++		} else {
++			ret = devm_request_threaded_irq(dev, info->id_irq,
++							NULL, usb_conn_isr,
++							USB_CONN_IRQF,
++							pdev->name, info);
++			if (ret < 0) {
++				dev_err(dev, "failed to request ID IRQ\n");
++				goto put_role_sw;
++			}
+ 		}
+ 	}
+ 
+ 	if (info->vbus_gpiod) {
+ 		info->vbus_irq = gpiod_to_irq(info->vbus_gpiod);
+ 		if (info->vbus_irq < 0) {
+-			dev_err(dev, "failed to get VBUS IRQ\n");
+-			ret = info->vbus_irq;
+-			goto put_role_sw;
+-		}
+-
+-		ret = devm_request_threaded_irq(dev, info->vbus_irq, NULL,
+-						usb_conn_isr, USB_CONN_IRQF,
+-						pdev->name, info);
+-		if (ret < 0) {
+-			dev_err(dev, "failed to request VBUS IRQ\n");
+-			goto put_role_sw;
++			dev_info(dev,
++				 "failed to get VBUS IRQ - falling back to polling\n");
++		} else {
++			ret = devm_request_threaded_irq(dev, info->vbus_irq,
++							NULL, usb_conn_isr,
++							USB_CONN_IRQF,
++							pdev->name, info);
++			if (ret < 0) {
++				dev_err(dev, "failed to request VBUS IRQ\n");
++				goto put_role_sw;
++			}
+ 		}
+ 	}
+ 
+@@ -300,6 +318,8 @@ static int __maybe_unused usb_conn_suspend(struct device *dev)
+ 	if (info->vbus_gpiod)
+ 		disable_irq(info->vbus_irq);
+ 
++	cancel_delayed_work_sync(&info->dw_det);
++
+ 	pinctrl_pm_select_sleep_state(dev);
+ 
+ 	return 0;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0010-usb-dwc2-register-child-USB-connector-devices.patch b/patch/kernel/archive/meson-6.10/0010-usb-dwc2-register-child-USB-connector-devices.patch
new file mode 100644
index 000000000000..4153e833ff88
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0010-usb-dwc2-register-child-USB-connector-devices.patch
@@ -0,0 +1,49 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 4 Jul 2020 21:04:29 +0200
+Subject: usb: dwc2: register child (USB connector) devices
+
+Populate the child devices/nodes of the dwc2 controller. Typically these
+are USB connectors with a compatible string (and additional properties)
+like "gpio-usb-b-connector".
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/usb/dwc2/platform.c | 14 ++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
+index 111111111111..222222222222 100644
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
+@@ -12,6 +12,7 @@
+ #include <linux/device.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/of.h>
++#include <linux/of_platform.h>
+ #include <linux/mutex.h>
+ #include <linux/platform_device.h>
+ #include <linux/phy/phy.h>
+@@ -620,6 +621,19 @@ static int dwc2_driver_probe(struct platform_device *dev)
+ 		}
+ 	}
+ #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
++
++	retval = devm_of_platform_populate(&dev->dev);
++	if (retval) {
++		dev_err(hsotg->dev,
++			"Failed to create child devices/connectors for %p\n",
++			dev->dev.of_node);
++
++		if (hsotg->gadget_enabled)
++			dwc2_hsotg_remove(hsotg);
++
++		goto error_debugfs;
++	}
++
+ 	return 0;
+ 
+ #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0011-ARM-dts-meson-Add-GPIO-controller-capabilities-to-th.patch b/patch/kernel/archive/meson-6.10/0011-ARM-dts-meson-Add-GPIO-controller-capabilities-to-th.patch
new file mode 100644
index 000000000000..517c014cce8b
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0011-ARM-dts-meson-Add-GPIO-controller-capabilities-to-th.patch
@@ -0,0 +1,30 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 16 Jun 2021 20:38:07 +0200
+Subject: ARM: dts: meson: Add GPIO controller capabilities to the first USB
+ PHY
+
+This is needed for boards that implement OTG functionality to read out
+the value of the "ID" signal (e.g. on Micro USB connectors).
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson.dtsi
+@@ -124,6 +124,8 @@ usb0_phy: phy@8800 {
+ 				compatible = "amlogic,meson-mx-usb2-phy";
+ 				#phy-cells = <0>;
+ 				reg = <0x8800 0x20>;
++				gpio-controller;
++				#gpio-cells = <2>;
+ 				status = "disabled";
+ 			};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0012-ARM-dts-meson8b-odroidc1-Enable-the-Micro-USB-OTG-co.patch b/patch/kernel/archive/meson-6.10/0012-ARM-dts-meson8b-odroidc1-Enable-the-Micro-USB-OTG-co.patch
new file mode 100644
index 000000000000..a31cf329e8c3
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0012-ARM-dts-meson8b-odroidc1-Enable-the-Micro-USB-OTG-co.patch
@@ -0,0 +1,74 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 4 May 2020 00:16:00 +0200
+Subject: ARM: dts: meson8b: odroidc1: Enable the Micro USB OTG connector
+
+Enable &usb0 which is routed to the Micro USB connector. The port
+supports OTG modes and the role switch is implemented by reading out the
+"ID" signal from &usb0_phy.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts | 34 +++++++++-
+ 1 file changed, 33 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts
++++ b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts
+@@ -93,6 +93,20 @@ rtc32k_xtal: rtc32k-xtal-clk {
+ 		#clock-cells = <0>;
+ 	};
+ 
++	usb0_vbus: regulator-usb0-vbus {
++		/* Richtek RT9715EGB */
++		compatible = "regulator-fixed";
++
++		regulator-name = "USB0_VBUS";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++
++		vin-supply = <&p5v0>;
++
++		gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++	};
++
+ 	vcc_1v8: regulator-vcc-1v8 {
+ 		/*
+ 		 * RICHTEK RT9179 configured for a fixed output voltage of
+@@ -363,8 +377,18 @@ &uart_AO {
+ 	pinctrl-names = "default";
+ };
+ 
+-&usb1_phy {
++&usb0 {
+ 	status = "okay";
++
++	dr_mode = "otg";
++	usb-role-switch;
++
++	connector {
++		compatible = "gpio-usb-b-connector", "usb-b-connector";
++		type = "micro";
++		id-gpios = <&usb0_phy 0 GPIO_ACTIVE_HIGH>;
++		vbus-supply = <&usb0_vbus>;
++	};
+ };
+ 
+ &usb1 {
+@@ -381,3 +405,11 @@ hub@1 {
+ 		reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+ 	};
+ };
++
++&usb0_phy {
++	status = "okay";
++};
++
++&usb1_phy {
++	status = "okay";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0013-dt-bindings-phy-Add-bindings-for-the-Amlogic-Meson-C.patch b/patch/kernel/archive/meson-6.10/0013-dt-bindings-phy-Add-bindings-for-the-Amlogic-Meson-C.patch
new file mode 100644
index 000000000000..4aba87f6ff5b
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0013-dt-bindings-phy-Add-bindings-for-the-Amlogic-Meson-C.patch
@@ -0,0 +1,104 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 11 Oct 2021 23:37:19 +0200
+Subject: dt-bindings: phy: Add bindings for the Amlogic Meson CVBS DAC
+
+Amlogic Meson SoCs embed a Composite Video Baseband Signal DAC. Add the
+bindings for this IP.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml | 82 ++++++++++
+ 1 file changed, 82 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml
+@@ -0,0 +1,82 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/amlogic,meson-cvbs-dac-phy.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Amlogic Meson Composite Video Baseband Signal DAC
++
++maintainers:
++  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++
++description: |+
++  The CVBS DAC node should be the child of a syscon node with the
++  required property:
++
++  compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
++
++  Refer to the bindings described in
++  Documentation/devicetree/bindings/mfd/syscon.yaml
++
++properties:
++  $nodename:
++    pattern: "^video-dac@[0-9a-f]+$"
++
++  compatible:
++    oneOf:
++      - items:
++          - enum:
++              - amlogic,meson8-cvbs-dac
++              - amlogic,meson8b-cvbs-dac
++              - amlogic,meson-gxbb-cvbs-dac
++              - amlogic,meson-gxl-cvbs-dac
++              - amlogic,meson-g12a-cvbs-dac
++          - const: amlogic,meson-cvbs-dac
++      - const: amlogic,meson-cvbs-dac
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    minItems: 1
++
++  nvmem-cells:
++    minItems: 1
++
++  nvmem-cell-names:
++    items:
++      - const: cvbs_trimming
++
++  "#phy-cells":
++    const: 0
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - "#phy-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    video-dac@2f4 {
++      compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac";
++      reg = <0x2f4 0x8>;
++
++      #phy-cells = <0>;
++
++      clocks = <&vdac_clock>;
++
++      nvmem-cells = <&cvbs_trimming>;
++      nvmem-cell-names = "cvbs_trimming";
++    };
++  - |
++    video-dac@2ec {
++      compatible = "amlogic,meson-g12a-cvbs-dac", "amlogic,meson-cvbs-dac";
++      reg = <0x2ec 0x8>;
++
++      #phy-cells = <0>;
++
++      clocks = <&vdac_clock>;
++    };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0014-phy-amlogic-Add-a-new-driver-for-the-CVBS-DAC-CVBS-P.patch b/patch/kernel/archive/meson-6.10/0014-phy-amlogic-Add-a-new-driver-for-the-CVBS-DAC-CVBS-P.patch
new file mode 100644
index 000000000000..494e8cd7abd2
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0014-phy-amlogic-Add-a-new-driver-for-the-CVBS-DAC-CVBS-P.patch
@@ -0,0 +1,445 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 11 Oct 2021 23:05:25 +0200
+Subject: phy: amlogic: Add a new driver for the CVBS DAC (CVBS PHY)
+
+Amlogic Meson SoCs embed a CVBS DAC which converts the signal from the
+VPU to analog. The IP has evolved over time with the SoC generations:
+- Meson8/8b/8m2 has per-chip calibrated data for the CDAC_GSW register
+- GXBB is overall similar to Meson8/8b/8m2 except that it doesn't have
+  per-chip calibration data and uses 0x0 in CDAC_GSW always
+- GXL/GXM are overall similar to GXBB but require a CDAC_VREF_ADJ value
+  of 0xf (of which the actual meaning is unknown)
+- G12A/G12B/SM1 use different register offsets and different values for
+  CDAC_CTRL_RESV2, CDAC_VREF_ADJ and CDAC_RL_ADJ. Like other SoCs from
+  GXBB onwards they don't need any per-chip data.
+
+For backwards compatibility with old .dtbs the driver gets
+platform_device_id's so the VPU driver can register the PHY as platform
+device if not provided via .dtb.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/phy/amlogic/Kconfig              |  10 +
+ drivers/phy/amlogic/Makefile             |   1 +
+ drivers/phy/amlogic/phy-meson-cvbs-dac.c | 376 ++++++++++
+ 3 files changed, 387 insertions(+)
+
+diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/phy/amlogic/Kconfig
++++ b/drivers/phy/amlogic/Kconfig
+@@ -25,6 +25,16 @@ config PHY_MESON8B_USB2
+ 	  Meson8b and GXBB SoCs.
+ 	  If unsure, say N.
+ 
++config PHY_MESON_CVBS_DAC
++	tristate "Amlogic Meson CVBS DAC PHY driver"
++	depends on ARCH_MESON || COMPILE_TEST
++	depends on OF
++	select MFD_SYSCON
++	help
++	  Enable this to support the CVBS DAC (PHY) found in Amlogic
++	  Meson SoCs.
++	  If unsure, say N.
++
+ config PHY_MESON_GXL_USB2
+ 	tristate "Meson GXL and GXM USB2 PHY drivers"
+ 	default ARCH_MESON
+diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/phy/amlogic/Makefile
++++ b/drivers/phy/amlogic/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ obj-$(CONFIG_PHY_MESON8_HDMI_TX)		+= phy-meson8-hdmi-tx.o
+ obj-$(CONFIG_PHY_MESON8B_USB2)			+= phy-meson8b-usb2.o
++obj-$(CONFIG_PHY_MESON_CVBS_DAC)		+= phy-meson-cvbs-dac.o
+ obj-$(CONFIG_PHY_MESON_GXL_USB2)		+= phy-meson-gxl-usb2.o
+ obj-$(CONFIG_PHY_MESON_G12A_USB2)		+= phy-meson-g12a-usb2.o
+ obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE)		+= phy-meson-g12a-usb3-pcie.o
+diff --git a/drivers/phy/amlogic/phy-meson-cvbs-dac.c b/drivers/phy/amlogic/phy-meson-cvbs-dac.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/phy/amlogic/phy-meson-cvbs-dac.c
+@@ -0,0 +1,376 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (C) 2016 BayLibre, SAS
++ * Copyright (C) 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mod_devicetable.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/property.h>
++#include <linux/mfd/syscon.h>
++#include <linux/nvmem-consumer.h>
++
++#define HHI_VDAC_CNTL0_MESON8			0x2F4 /* 0xbd offset in data sheet */
++#define HHI_VDAC_CNTL1_MESON8			0x2F8 /* 0xbe offset in data sheet */
++
++#define HHI_VDAC_CNTL0_G12A			0x2EC /* 0xbd offset in data sheet */
++#define HHI_VDAC_CNTL1_G12A			0x2F0 /* 0xbe offset in data sheet */
++
++enum phy_meson_cvbs_dac_reg {
++	MESON_CDAC_CTRL_RESV1,
++	MESON_CDAC_CTRL_RESV2,
++	MESON_CDAC_VREF_ADJ,
++	MESON_CDAC_RL_ADJ,
++	MESON_CDAC_CLK_PHASE_SEL,
++	MESON_CDAC_DRIVER_ADJ,
++	MESON_CDAC_EXT_VREF_EN,
++	MESON_CDAC_BIAS_C,
++	MESON_VDAC_CNTL0_RESERVED,
++	MESON_CDAC_GSW,
++	MESON_CDAC_PWD,
++	MESON_VDAC_CNTL1_RESERVED,
++	MESON_CVBS_DAC_NUM_REGS
++};
++
++struct phy_meson_cvbs_dac_data {
++	const struct reg_field	*reg_fields;
++	u8			cdac_ctrl_resv2_enable_val;
++	u8			cdac_vref_adj_enable_val;
++	u8			cdac_rl_adj_enable_val;
++	u8			cdac_pwd_disable_val;
++	bool			needs_cvbs_trimming_nvmem_cell;
++};
++
++struct phy_meson_cvbs_dac_priv {
++	struct regmap_field			*regs[MESON_CVBS_DAC_NUM_REGS];
++	const struct phy_meson_cvbs_dac_data	*data;
++	u8					cdac_gsw_enable_val;
++};
++
++static const struct reg_field phy_meson8_cvbs_dac_reg_fields[] = {
++	[MESON_CDAC_CTRL_RESV1] =	REG_FIELD(HHI_VDAC_CNTL0_MESON8, 0, 7),
++	[MESON_CDAC_CTRL_RESV2] =	REG_FIELD(HHI_VDAC_CNTL0_MESON8, 8, 15),
++	[MESON_CDAC_VREF_ADJ] =		REG_FIELD(HHI_VDAC_CNTL0_MESON8, 16, 20),
++	[MESON_CDAC_RL_ADJ] =		REG_FIELD(HHI_VDAC_CNTL0_MESON8, 21, 23),
++	[MESON_CDAC_CLK_PHASE_SEL] =	REG_FIELD(HHI_VDAC_CNTL0_MESON8, 24, 24),
++	[MESON_CDAC_DRIVER_ADJ] =	REG_FIELD(HHI_VDAC_CNTL0_MESON8, 25, 25),
++	[MESON_CDAC_EXT_VREF_EN] =	REG_FIELD(HHI_VDAC_CNTL0_MESON8, 26, 26),
++	[MESON_CDAC_BIAS_C] =		REG_FIELD(HHI_VDAC_CNTL0_MESON8, 27, 27),
++	[MESON_VDAC_CNTL0_RESERVED] =	REG_FIELD(HHI_VDAC_CNTL0_MESON8, 28, 31),
++	[MESON_CDAC_GSW] =		REG_FIELD(HHI_VDAC_CNTL1_MESON8, 0, 2),
++	[MESON_CDAC_PWD] =		REG_FIELD(HHI_VDAC_CNTL1_MESON8, 3, 3),
++	[MESON_VDAC_CNTL1_RESERVED] =	REG_FIELD(HHI_VDAC_CNTL1_MESON8, 4, 31),
++};
++
++static const struct reg_field phy_meson_g12a_cvbs_dac_reg_fields[] = {
++	[MESON_CDAC_CTRL_RESV1] =	REG_FIELD(HHI_VDAC_CNTL0_G12A, 0, 7),
++	[MESON_CDAC_CTRL_RESV2] =	REG_FIELD(HHI_VDAC_CNTL0_G12A, 8, 15),
++	[MESON_CDAC_VREF_ADJ] =		REG_FIELD(HHI_VDAC_CNTL0_G12A, 16, 20),
++	[MESON_CDAC_RL_ADJ] =		REG_FIELD(HHI_VDAC_CNTL0_G12A, 21, 23),
++	[MESON_CDAC_CLK_PHASE_SEL] =	REG_FIELD(HHI_VDAC_CNTL0_G12A, 24, 24),
++	[MESON_CDAC_DRIVER_ADJ] =	REG_FIELD(HHI_VDAC_CNTL0_G12A, 25, 25),
++	[MESON_CDAC_EXT_VREF_EN] =	REG_FIELD(HHI_VDAC_CNTL0_G12A, 26, 26),
++	[MESON_CDAC_BIAS_C] =		REG_FIELD(HHI_VDAC_CNTL0_G12A, 27, 27),
++	[MESON_VDAC_CNTL0_RESERVED] =	REG_FIELD(HHI_VDAC_CNTL0_G12A, 28, 31),
++	[MESON_CDAC_GSW] =		REG_FIELD(HHI_VDAC_CNTL1_G12A, 0, 2),
++	[MESON_CDAC_PWD] =		REG_FIELD(HHI_VDAC_CNTL1_G12A, 3, 3),
++	[MESON_VDAC_CNTL1_RESERVED] =	REG_FIELD(HHI_VDAC_CNTL1_G12A, 4, 31),
++};
++
++static const struct phy_meson_cvbs_dac_data phy_meson8_cvbs_dac_data = {
++	.reg_fields			= phy_meson8_cvbs_dac_reg_fields,
++	.cdac_ctrl_resv2_enable_val	= 0x0,
++	.cdac_vref_adj_enable_val	= 0x0,
++	.cdac_rl_adj_enable_val		= 0x0,
++	.cdac_pwd_disable_val		= 0x1,
++	.needs_cvbs_trimming_nvmem_cell	= true,
++};
++
++static const struct phy_meson_cvbs_dac_data phy_meson_gxbb_cvbs_dac_data = {
++	.reg_fields			= phy_meson8_cvbs_dac_reg_fields,
++	.cdac_ctrl_resv2_enable_val	= 0x0,
++	.cdac_vref_adj_enable_val	= 0x0,
++	.cdac_rl_adj_enable_val		= 0x0,
++	.cdac_pwd_disable_val		= 0x1,
++	.needs_cvbs_trimming_nvmem_cell	= false,
++};
++
++static const struct phy_meson_cvbs_dac_data phy_meson_gxl_cvbs_dac_data = {
++	.reg_fields			= phy_meson8_cvbs_dac_reg_fields,
++	.cdac_ctrl_resv2_enable_val	= 0x0,
++	.cdac_vref_adj_enable_val	= 0xf,
++	.cdac_rl_adj_enable_val		= 0x0,
++	.cdac_pwd_disable_val		= 0x1,
++	.needs_cvbs_trimming_nvmem_cell	= false,
++};
++
++static const struct phy_meson_cvbs_dac_data phy_meson_g12a_cvbs_dac_data = {
++	.reg_fields			= phy_meson_g12a_cvbs_dac_reg_fields,
++	.cdac_ctrl_resv2_enable_val	= 0x60,
++	.cdac_vref_adj_enable_val	= 0x10,
++	.cdac_rl_adj_enable_val		= 0x4,
++	.cdac_pwd_disable_val		= 0x0,
++	.needs_cvbs_trimming_nvmem_cell	= false,
++};
++
++static int phy_meson_cvbs_dac_power_on(struct phy *phy)
++{
++	struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy);
++
++	regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV1], 0x1);
++	regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV2],
++			   priv->data->cdac_ctrl_resv2_enable_val);
++	regmap_field_write(priv->regs[MESON_CDAC_VREF_ADJ],
++			   priv->data->cdac_vref_adj_enable_val);
++	regmap_field_write(priv->regs[MESON_CDAC_RL_ADJ],
++			   priv->data->cdac_rl_adj_enable_val);
++	regmap_field_write(priv->regs[MESON_CDAC_GSW],
++			   priv->cdac_gsw_enable_val);
++	regmap_field_write(priv->regs[MESON_CDAC_PWD], 0x0);
++
++	return 0;
++}
++
++static int phy_meson_cvbs_dac_power_off(struct phy *phy)
++{
++	struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy);
++
++	regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV1], 0x0);
++	regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV2], 0x0);
++	regmap_field_write(priv->regs[MESON_CDAC_VREF_ADJ], 0x0);
++	regmap_field_write(priv->regs[MESON_CDAC_RL_ADJ], 0x0);
++	regmap_field_write(priv->regs[MESON_CDAC_GSW], 0x0);
++	regmap_field_write(priv->regs[MESON_CDAC_PWD],
++			   priv->data->cdac_pwd_disable_val);
++
++	return 0;
++}
++
++static int phy_meson_cvbs_dac_init(struct phy *phy)
++{
++	struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy);
++
++	regmap_field_write(priv->regs[MESON_CDAC_CLK_PHASE_SEL], 0x0);
++	regmap_field_write(priv->regs[MESON_CDAC_DRIVER_ADJ], 0x0);
++	regmap_field_write(priv->regs[MESON_CDAC_EXT_VREF_EN], 0x0);
++	regmap_field_write(priv->regs[MESON_CDAC_BIAS_C], 0x0);
++	regmap_field_write(priv->regs[MESON_VDAC_CNTL0_RESERVED], 0x0);
++	regmap_field_write(priv->regs[MESON_VDAC_CNTL1_RESERVED], 0x0);
++
++	return phy_meson_cvbs_dac_power_off(phy);
++}
++
++static const struct phy_ops phy_meson_cvbs_dac_ops = {
++	.init		= phy_meson_cvbs_dac_init,
++	.power_on	= phy_meson_cvbs_dac_power_on,
++	.power_off	= phy_meson_cvbs_dac_power_off,
++	.owner		= THIS_MODULE,
++};
++
++static u8 phy_meson_cvbs_trimming_version(u8 trimming1)
++{
++	if ((trimming1 & 0xf0) == 0xa0)
++		return 5;
++	else if ((trimming1 & 0xf0) == 0x40)
++		return 2;
++	else if ((trimming1 & 0xc0) == 0x80)
++		return 1;
++	else if ((trimming1 & 0xc0) == 0x00)
++		return 0;
++	else
++		return 0xff;
++}
++
++static int phy_meson_cvbs_read_trimming(struct device *dev,
++					struct phy_meson_cvbs_dac_priv *priv)
++{
++	struct nvmem_cell *cell;
++	u8 *trimming;
++	size_t len;
++
++	cell = devm_nvmem_cell_get(dev, "cvbs_trimming");
++	if (IS_ERR(cell))
++		return dev_err_probe(dev, PTR_ERR(cell),
++				     "Failed to get the 'cvbs_trimming' nvmem-cell\n");
++
++	trimming = nvmem_cell_read(cell, &len);
++	if (IS_ERR(trimming)) {
++		/*
++		 * TrustZone firmware may block access to the CVBS trimming
++		 * data stored in the eFuse. On those devices the trimming data
++		 * is stored in the u-boot environment. However, the known
++		 * examples of trimming data in the u-boot environment are all
++		 * zero.
++		 */
++		dev_dbg(dev,
++			"Failed to read the 'cvbs_trimming' nvmem-cell - falling back to a default value\n");
++		priv->cdac_gsw_enable_val = 0x0;
++		return 0;
++	}
++
++	if (len != 2) {
++		kfree(trimming);
++		return dev_err_probe(dev, -EINVAL,
++				     "Read the 'cvbs_trimming' nvmem-cell with invalid length\n");
++	}
++
++	switch (phy_meson_cvbs_trimming_version(trimming[1])) {
++	case 1:
++	case 2:
++	case 5:
++		priv->cdac_gsw_enable_val = trimming[0] & 0x7;
++		break;
++	default:
++		priv->cdac_gsw_enable_val = 0x0;
++		break;
++	}
++
++	kfree(trimming);
++
++	return 0;
++}
++
++static int phy_meson_cvbs_dac_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct phy_meson_cvbs_dac_priv *priv;
++	struct phy_provider *phy_provider;
++	struct device *dev = &pdev->dev;
++	struct regmap *hhi;
++	struct phy *phy;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	if (np) {
++		priv->data = device_get_match_data(dev);
++		if (!priv->data)
++			return dev_err_probe(dev, -EINVAL,
++					     "Could not find the OF match data\n");
++
++		hhi = syscon_node_to_regmap(np->parent);
++		if (IS_ERR(hhi))
++			return dev_err_probe(dev, PTR_ERR(hhi),
++					     "Failed to get the parent syscon\n");
++	} else {
++		const struct platform_device_id *pdev_id;
++
++		pdev_id = platform_get_device_id(pdev);
++		if (!pdev_id)
++			return dev_err_probe(dev, -EINVAL,
++					     "Failed to find platform device ID\n");
++
++		priv->data = (void *)pdev_id->driver_data;
++		if (!priv->data)
++			return dev_err_probe(dev, -EINVAL,
++					     "Could not find the platform driver data\n");
++
++		hhi = syscon_regmap_lookup_by_compatible("amlogic,meson-gx-hhi-sysctrl");
++		if (IS_ERR(hhi))
++			return dev_err_probe(dev, PTR_ERR(hhi),
++					     "Failed to get the \"amlogic,meson-gx-hhi-sysctrl\" syscon\n");
++	}
++
++	if (priv->data->needs_cvbs_trimming_nvmem_cell) {
++		ret = phy_meson_cvbs_read_trimming(dev, priv);
++		if (ret)
++			return ret;
++	}
++
++	ret = devm_regmap_field_bulk_alloc(dev, hhi, priv->regs,
++					   priv->data->reg_fields,
++					   MESON_CVBS_DAC_NUM_REGS);
++	if (ret)
++		return dev_err_probe(dev, ret,
++				     "Failed to create regmap fields\n");
++
++	phy = devm_phy_create(dev, np, &phy_meson_cvbs_dac_ops);
++	if (IS_ERR(phy))
++		return PTR_ERR(phy);
++
++	phy_set_drvdata(phy, priv);
++
++	if (np) {
++		phy_provider = devm_of_phy_provider_register(dev,
++							     of_phy_simple_xlate);
++		ret = PTR_ERR_OR_ZERO(phy_provider);
++		if (ret)
++			return dev_err_probe(dev, ret,
++					     "Failed to register PHY provider\n");
++	} else {
++		platform_set_drvdata(pdev, phy);
++	}
++
++	return 0;
++}
++
++static const struct of_device_id phy_meson_cvbs_dac_of_match[] = {
++	{
++		.compatible = "amlogic,meson8-cvbs-dac",
++		.data = &phy_meson8_cvbs_dac_data,
++	},
++	{
++		.compatible = "amlogic,meson8b-cvbs-dac",
++		.data = &phy_meson8_cvbs_dac_data,
++	},
++	{
++		.compatible = "amlogic,meson-gxbb-cvbs-dac",
++		.data = &phy_meson_gxbb_cvbs_dac_data,
++	},
++	{
++		.compatible = "amlogic,meson-gxl-cvbs-dac",
++		.data = &phy_meson_gxl_cvbs_dac_data,
++	},
++	{
++		.compatible = "amlogic,meson-g12a-cvbs-dac",
++		.data = &phy_meson_g12a_cvbs_dac_data,
++	},
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, phy_meson_cvbs_dac_of_match);
++
++/*
++ * The platform_device_id table is used for backwards compatibility with old
++ * .dtbs which don't have a CVBS DAC node (where the VPU DRM driver registers
++ * this as a platform device. Support for additional SoCs should only be added
++ * to the of_device_id table above.
++ */
++static const struct platform_device_id phy_meson_cvbs_dac_device_ids[] = {
++	{
++		.name = "meson-gxbb-cvbs-dac",
++		.driver_data = (kernel_ulong_t)&phy_meson_gxbb_cvbs_dac_data,
++	},
++	{
++		.name = "meson-gxl-cvbs-dac",
++		.driver_data = (kernel_ulong_t)&phy_meson_gxl_cvbs_dac_data,
++	},
++	{
++		.name = "meson-g12a-cvbs-dac",
++		.driver_data = (kernel_ulong_t)&phy_meson_g12a_cvbs_dac_data,
++	},
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(platform, phy_meson_cvbs_dac_device_ids);
++
++static struct platform_driver phy_meson_cvbs_dac_driver = {
++	.driver = {
++		.name		= "phy-meson-cvbs-dac",
++		.of_match_table	= phy_meson_cvbs_dac_of_match,
++	},
++	.id_table = phy_meson_cvbs_dac_device_ids,
++	.probe = phy_meson_cvbs_dac_probe,
++};
++module_platform_driver(phy_meson_cvbs_dac_driver);
++
++MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
++MODULE_DESCRIPTION("Amlogic Meson CVBS DAC driver");
++MODULE_LICENSE("GPL v2");
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0015-dt-bindings-display-meson-vpu-Add-the-CVBS-DAC-prope.patch b/patch/kernel/archive/meson-6.10/0015-dt-bindings-display-meson-vpu-Add-the-CVBS-DAC-prope.patch
new file mode 100644
index 000000000000..0775d10d8271
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0015-dt-bindings-display-meson-vpu-Add-the-CVBS-DAC-prope.patch
@@ -0,0 +1,48 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 20 Oct 2021 22:19:25 +0200
+Subject: dt-bindings: display: meson-vpu: Add the CVBS DAC properties
+
+The CVBS DAC converts the digital video signal to the (analog) composite
+video baseband signal (CVBS). This DAC is part of the HHI registers.
+Add the phy and phy-names property to describe the relation between the
+VPU (which outputs the digital signal) and the CVBS DAC.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml | 12 ++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
++++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
+@@ -82,6 +82,15 @@ properties:
+     description: should point to a canvas provider node
+     $ref: /schemas/types.yaml#/definitions/phandle
+ 
++  phys:
++    maxItems: 1
++    description:
++      PHY specifier for the CVBS DAC
++
++  phy-names:
++    items:
++      - const: cvbs-dac
++
+   power-domains:
+     maxItems: 1
+     description: phandle to the associated power domain
+@@ -130,6 +139,9 @@ examples:
+         #size-cells = <0>;
+         amlogic,canvas = <&canvas>;
+ 
++        phys = <&cvbs_dac_phy>;
++        phy-names = "cvbs-dac";
++
+         /* CVBS VDAC output port */
+         port@0 {
+             reg = <0>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0016-drm-meson-Add-support-for-using-a-PHY-for-the-CVBS-D.patch b/patch/kernel/archive/meson-6.10/0016-drm-meson-Add-support-for-using-a-PHY-for-the-CVBS-D.patch
new file mode 100644
index 000000000000..4ef1ee3d5e9f
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0016-drm-meson-Add-support-for-using-a-PHY-for-the-CVBS-D.patch
@@ -0,0 +1,317 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Apr 2020 22:06:53 +0200
+Subject: drm/meson: Add support for using a PHY for the CVBS DAC
+
+Currently the VPU driver hardcodes the initialization, power-on and
+power-off sequences for the CVBS DAC. The registers for the CVBS DAC are
+in the HHI register area. Also the CVBS DAC is a PHY so it can be
+modelled as such. Add support for using a PHY as CVBS DAC to de-couple
+the VPU driver from the HHI registers (at least for this part of the
+implementation).
+Register a platform device for the PHY (which creates a lookup entry to
+compensate for the missing .dtb entry) which takes over all
+HHI_VDAC_CNTL register management.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/Kconfig              |   1 +
+ drivers/gpu/drm/meson/meson_drv.h          |   6 +
+ drivers/gpu/drm/meson/meson_encoder_cvbs.c | 132 ++++++++--
+ drivers/gpu/drm/meson/meson_venc.c         |  13 -
+ 4 files changed, 110 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/Kconfig
++++ b/drivers/gpu/drm/meson/Kconfig
+@@ -10,6 +10,7 @@ config DRM_MESON
+ 	select REGMAP_MMIO
+ 	select MESON_CANVAS
+ 	select CEC_CORE if CEC_NOTIFIER
++	imply PHY_MESON_CVBS_DAC
+ 
+ config DRM_MESON_DW_HDMI
+ 	tristate "HDMI Synopsys Controller support for Amlogic Meson Display"
+diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_drv.h
++++ b/drivers/gpu/drm/meson/meson_drv.h
+@@ -16,6 +16,8 @@ struct drm_device;
+ struct drm_plane;
+ struct meson_drm;
+ struct meson_afbcd_ops;
++struct phy;
++struct platform_device;
+ 
+ enum vpu_compatible {
+ 	VPU_COMPATIBLE_GXBB = 0,
+@@ -61,6 +63,10 @@ struct meson_drm {
+ 
+ 	const struct meson_drm_soc_limits *limits;
+ 
++	struct phy *cvbs_dac;
++	bool cvbs_dac_enabled;
++	struct platform_device *cvbs_dac_pdev;
++
+ 	/* Components Data */
+ 	struct {
+ 		bool osd1_enabled;
+diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c
++++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
+@@ -11,6 +11,8 @@
+ 
+ #include <linux/export.h>
+ #include <linux/of_graph.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
+ 
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_bridge.h>
+@@ -24,12 +26,6 @@
+ #include "meson_vclk.h"
+ #include "meson_encoder_cvbs.h"
+ 
+-/* HHI VDAC Registers */
+-#define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */
+-#define HHI_VDAC_CNTL0_G12A	0x2EC /* 0xbd offset in data sheet */
+-#define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */
+-#define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbe offset in data sheet */
+-
+ struct meson_encoder_cvbs {
+ 	struct drm_encoder	encoder;
+ 	struct drm_bridge	bridge;
+@@ -87,11 +83,28 @@ static int meson_encoder_cvbs_attach(struct drm_bridge *bridge,
+ {
+ 	struct meson_encoder_cvbs *meson_encoder_cvbs =
+ 					bridge_to_meson_encoder_cvbs(bridge);
++	int ret;
++
++	ret = phy_init(meson_encoder_cvbs->priv->cvbs_dac);
++	if (ret)
++		return ret;
+ 
+ 	return drm_bridge_attach(bridge->encoder, meson_encoder_cvbs->next_bridge,
+ 				 &meson_encoder_cvbs->bridge, flags);
+ }
+ 
++static void meson_encoder_cvbs_detach(struct drm_bridge *bridge)
++{
++	struct meson_encoder_cvbs *meson_encoder_cvbs =
++					bridge_to_meson_encoder_cvbs(bridge);
++	int ret;
++
++	ret = phy_exit(meson_encoder_cvbs->priv->cvbs_dac);
++	if (ret)
++		dev_err(meson_encoder_cvbs->priv->dev,
++			"Failed to exit the CVBS DAC\n");
++}
++
+ static int meson_encoder_cvbs_get_modes(struct drm_bridge *bridge,
+ 					struct drm_connector *connector)
+ {
+@@ -148,6 +161,7 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
+ 	struct drm_connector_state *conn_state;
+ 	struct drm_crtc_state *crtc_state;
+ 	struct drm_connector *connector;
++	int ret;
+ 
+ 	connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
+ 	if (WARN_ON(!connector))
+@@ -177,16 +191,13 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
+ 	writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0,
+ 			    priv->io_base + _REG(VENC_VDAC_DACSEL0));
+ 
+-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
+-	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
+-		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001);
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
+-	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001);
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
++	if (!priv->cvbs_dac_enabled) {
++		ret = phy_power_on(priv->cvbs_dac);
++		if (ret)
++			dev_err(priv->dev,
++				"Failed to power on the CVBS DAC\n");
++		else
++			priv->cvbs_dac_enabled = true;
+ 	}
+ }
+ 
+@@ -196,19 +207,22 @@ static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge,
+ 	struct meson_encoder_cvbs *meson_encoder_cvbs =
+ 					bridge_to_meson_encoder_cvbs(bridge);
+ 	struct meson_drm *priv = meson_encoder_cvbs->priv;
++	int ret;
+ 
+-	/* Disable CVBS VDAC */
+-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
+-	} else {
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
+-	}
++	if (!priv->cvbs_dac_enabled)
++		return;
++
++	ret = phy_power_off(priv->cvbs_dac);
++	if (ret)
++		dev_err(priv->dev,
++			"Failed to power off the CVBS DAC\n");
++	else
++		priv->cvbs_dac_enabled = false;
+ }
+ 
+ static const struct drm_bridge_funcs meson_encoder_cvbs_bridge_funcs = {
+ 	.attach = meson_encoder_cvbs_attach,
++	.detach = meson_encoder_cvbs_detach,
+ 	.mode_valid = meson_encoder_cvbs_mode_valid,
+ 	.get_modes = meson_encoder_cvbs_get_modes,
+ 	.atomic_enable = meson_encoder_cvbs_atomic_enable,
+@@ -219,6 +233,54 @@ static const struct drm_bridge_funcs meson_encoder_cvbs_bridge_funcs = {
+ 	.atomic_reset = drm_atomic_helper_bridge_reset,
+ };
+ 
++static int meson_cvbs_dac_probe(struct meson_drm *priv)
++{
++	struct platform_device *pdev;
++	const char *platform_id_name;
++
++	priv->cvbs_dac = devm_phy_optional_get(priv->dev, "cvbs-dac");
++	if (IS_ERR(priv->cvbs_dac))
++		return dev_err_probe(priv->dev, PTR_ERR(priv->cvbs_dac),
++				     "Failed to get the 'cvbs-dac' PHY\n");
++	else if (priv->cvbs_dac)
++		return 0;
++
++	switch (priv->compat) {
++	case VPU_COMPATIBLE_GXBB:
++		platform_id_name = "meson-gxbb-cvbs-dac";
++		break;
++	case VPU_COMPATIBLE_GXL:
++	case VPU_COMPATIBLE_GXM:
++		platform_id_name = "meson-gxl-cvbs-dac";
++		break;
++	case VPU_COMPATIBLE_G12A:
++		platform_id_name = "meson-g12a-cvbs-dac";
++		break;
++	default:
++		return dev_err_probe(priv->dev, -EINVAL,
++				     "No CVBS DAC platform ID found\n");
++	}
++
++	pdev = platform_device_register_data(priv->dev, platform_id_name,
++					     PLATFORM_DEVID_AUTO, NULL, 0);
++	if (IS_ERR(pdev))
++		return dev_err_probe(priv->dev, PTR_ERR(pdev),
++				     "Failed to register fallback CVBS DAC PHY platform device\n");
++
++	priv->cvbs_dac = platform_get_drvdata(pdev);
++	if (IS_ERR(priv->cvbs_dac)) {
++		platform_device_unregister(pdev);
++		return dev_err_probe(priv->dev, PTR_ERR(priv->cvbs_dac),
++				     "Failed to get the 'cvbs-dac' PHY from it's platform device\n");
++	}
++
++	dev_info(priv->dev, "Using fallback for old .dtbs without CVBS DAC\n");
++
++	priv->cvbs_dac_pdev = pdev;
++
++	return 0;
++}
++
+ int meson_encoder_cvbs_probe(struct meson_drm *priv)
+ {
+ 	struct drm_device *drm = priv->drm;
+@@ -255,6 +317,10 @@ int meson_encoder_cvbs_probe(struct meson_drm *priv)
+ 
+ 	meson_encoder_cvbs->priv = priv;
+ 
++	ret = meson_cvbs_dac_probe(priv);
++	if (ret)
++		return ret;
++
+ 	/* Encoder */
+ 	ret = drm_simple_encoder_init(priv->drm, &meson_encoder_cvbs->encoder,
+ 				      DRM_MODE_ENCODER_TVDAC);
+@@ -268,21 +334,27 @@ int meson_encoder_cvbs_probe(struct meson_drm *priv)
+ 	ret = drm_bridge_attach(&meson_encoder_cvbs->encoder, &meson_encoder_cvbs->bridge, NULL,
+ 				DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+ 	if (ret) {
+-		dev_err(priv->dev, "Failed to attach bridge: %d\n", ret);
+-		return ret;
++		dev_err_probe(priv->dev, ret, "Failed to attach bridge\n");
++		goto err_unregister_cvbs_dac_pdev;
+ 	}
+ 
+ 	/* Initialize & attach Bridge Connector */
+ 	connector = drm_bridge_connector_init(priv->drm, &meson_encoder_cvbs->encoder);
+-	if (IS_ERR(connector))
+-		return dev_err_probe(priv->dev, PTR_ERR(connector),
+-				     "Unable to create CVBS bridge connector\n");
++	if (IS_ERR(connector)) {
++		ret = dev_err_probe(priv->dev, PTR_ERR(connector),
++				    "Unable to create CVBS bridge connector\n");
++		goto err_unregister_cvbs_dac_pdev;
++	}
+ 
+ 	drm_connector_attach_encoder(connector, &meson_encoder_cvbs->encoder);
+ 
+ 	priv->encoders[MESON_ENC_CVBS] = meson_encoder_cvbs;
+ 
+ 	return 0;
++
++err_unregister_cvbs_dac_pdev:
++	platform_device_unregister(priv->cvbs_dac_pdev);
++	return ret;
+ }
+ 
+ void meson_encoder_cvbs_remove(struct meson_drm *priv)
+@@ -293,4 +365,6 @@ void meson_encoder_cvbs_remove(struct meson_drm *priv)
+ 		meson_encoder_cvbs = priv->encoders[MESON_ENC_CVBS];
+ 		drm_bridge_remove(&meson_encoder_cvbs->bridge);
+ 	}
++
++	platform_device_unregister(priv->cvbs_dac_pdev);
+ }
+diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_venc.c
++++ b/drivers/gpu/drm/meson/meson_venc.c
+@@ -62,10 +62,6 @@
+ 
+ /* HHI Registers */
+ #define HHI_GCLK_MPEG2		0x148 /* 0x52 offset in data sheet */
+-#define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */
+-#define HHI_VDAC_CNTL0_G12A	0x2EC /* 0xbb offset in data sheet */
+-#define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */
+-#define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbc offset in data sheet */
+ #define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 offset in data sheet */
+ 
+ struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
+@@ -1968,15 +1964,6 @@ void meson_venc_disable_vsync(struct meson_drm *priv)
+ 
+ void meson_venc_init(struct meson_drm *priv)
+ {
+-	/* Disable CVBS VDAC */
+-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8);
+-	} else {
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
+-		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
+-	}
+-
+ 	/* Power Down Dacs */
+ 	writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0018-dt-bindings-clock-meson8b-Add-the-RMII-reference-clo.patch b/patch/kernel/archive/meson-6.10/0018-dt-bindings-clock-meson8b-Add-the-RMII-reference-clo.patch
new file mode 100644
index 000000000000..41f977d085c3
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0018-dt-bindings-clock-meson8b-Add-the-RMII-reference-clo.patch
@@ -0,0 +1,30 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 1 May 2020 23:16:07 +0200
+Subject: dt-bindings: clock: meson8b: Add the RMII reference clock input
+
+Amlogic Meson8 SoCs need an external 50MHz RMII reference clock. This is
+either provided by the Ethernet PHY or an external oscillator. Add the
+documentation for this clock input.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
++++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+@@ -16,6 +16,8 @@ Required Properties:
+   * "xtal": the 24MHz system oscillator
+   * "ddr_pll": the DDR PLL clock
+   * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
++  * "rmii_clk": (if present) the 50MHz RMII reference clock (from the PHY or
++                an external oscillator
+ 
+ Parent node should have the following properties :
+ - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0019-dt-bindings-clock-meson8b-Add-the-Meson8-Ethernet-RM.patch b/patch/kernel/archive/meson-6.10/0019-dt-bindings-clock-meson8b-Add-the-Meson8-Ethernet-RM.patch
new file mode 100644
index 000000000000..ae1ab785b416
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0019-dt-bindings-clock-meson8b-Add-the-Meson8-Ethernet-RM.patch
@@ -0,0 +1,30 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 1 May 2020 23:23:49 +0200
+Subject: dt-bindings: clock: meson8b: Add the Meson8 Ethernet (RMII) clocks
+
+Export CLKID_ETH_CLK (and it's parents) because it is used as input for
+the Ethernet controller on Meson8 SoCs.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ include/dt-bindings/clock/meson8b-clkc.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
+index 111111111111..222222222222 100644
+--- a/include/dt-bindings/clock/meson8b-clkc.h
++++ b/include/dt-bindings/clock/meson8b-clkc.h
+@@ -221,5 +221,9 @@
+ #define CLKID_VCLK2_EN		215
+ #define CLKID_VID_PLL_LVDS_EN	216
+ #define CLKID_HDMI_PLL_DCO_IN   217
++#define CLKID_ETH_CLK_SEL	218
++#define CLKID_ETH_CLK_DIV	219
++#define CLKID_ETH_CLK_PHASE	220
++#define CLKID_ETH_CLK		221
+ 
+ #endif /* __MESON8B_CLKC_H */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0020-clk-meson-meson8b-Add-the-Ethernet-RMII-clock-tree-o.patch b/patch/kernel/archive/meson-6.10/0020-clk-meson-meson8b-Add-the-Ethernet-RMII-clock-tree-o.patch
new file mode 100644
index 000000000000..451f73d4c91f
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0020-clk-meson-meson8b-Add-the-Ethernet-RMII-clock-tree-o.patch
@@ -0,0 +1,162 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 1 May 2020 23:25:13 +0200
+Subject: clk: meson: meson8b: Add the Ethernet (RMII) clock tree on Meson8
+
+Add the Ethernet clock tree on Meson8 which consists of:
+- an input mux - the only known input is the RMII reference clock signal
+  which is an input on one of the SoC's pads
+- a divider
+- 0deg or 180deg phase change
+- a gate to enable/disable the clock
+
+Add these clocks only for Meson8 because they're only known to be used
+there.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/clk/meson/Kconfig   |  1 +
+ drivers/clk/meson/meson8b.c | 81 ++++++++++
+ drivers/clk/meson/meson8b.h |  1 +
+ 3 files changed, 83 insertions(+)
+
+diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/clk/meson/Kconfig
++++ b/drivers/clk/meson/Kconfig
+@@ -59,6 +59,7 @@ config COMMON_CLK_MESON8B
+ 	select COMMON_CLK_MESON_REGMAP
+ 	select COMMON_CLK_MESON_CLKC_UTILS
+ 	select COMMON_CLK_MESON_MPLL
++	select COMMON_CLK_MESON_PHASE
+ 	select COMMON_CLK_MESON_PLL
+ 	select MFD_SYSCON
+ 	select RESET_CONTROLLER
+diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
+index 111111111111..222222222222 100644
+--- a/drivers/clk/meson/meson8b.c
++++ b/drivers/clk/meson/meson8b.c
+@@ -19,6 +19,7 @@
+ #include "meson8b.h"
+ #include "clk-regmap.h"
+ #include "meson-clkc-utils.h"
++#include "clk-phase.h"
+ #include "clk-pll.h"
+ #include "clk-mpll.h"
+ 
+@@ -2682,6 +2683,78 @@ static struct clk_regmap meson8b_cts_i958 = {
+ 	},
+ };
+ 
++static u32 meson8_eth_clk_mux_table[] = { 7 };
++
++static struct clk_regmap meson8_eth_clk_sel = {
++	.data = &(struct clk_regmap_mux_data) {
++		.offset = HHI_ETH_CLK_CNTL,
++		.mask = 0x7,
++		.shift = 9,
++		.table = meson8_eth_clk_mux_table,
++	},
++	.hw.init = &(struct clk_init_data) {
++		.name = "eth_clk_sel",
++		.ops = &clk_regmap_mux_ops,
++		.parent_data = &(const struct clk_parent_data) {
++			/* TODO: all other parents are unknown */
++			.fw_name = "rmii_clk",
++		},
++		.num_parents = 1,
++	},
++};
++
++static struct clk_regmap meson8_eth_clk_div = {
++	.data = &(struct clk_regmap_div_data) {
++		.offset = HHI_ETH_CLK_CNTL,
++		.shift = 0,
++		.width = 8,
++	},
++	.hw.init = &(struct clk_init_data) {
++		.name = "eth_clk_div",
++		.ops = &clk_regmap_divider_ops,
++		.parent_hws = (const struct clk_hw *[]) {
++			&meson8_eth_clk_sel.hw
++		},
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT,
++	},
++};
++
++static struct clk_regmap meson8_eth_clk_phase = {
++	.data = &(struct meson_clk_phase_data) {
++		.ph = {
++			.reg_off = HHI_ETH_CLK_CNTL,
++			.shift = 14,
++			.width = 1,
++		},
++	},
++	.hw.init = &(struct clk_init_data){
++		.name = "eth_clk_inverted",
++		.ops = &meson_clk_phase_ops,
++		.parent_hws = (const struct clk_hw *[]) {
++			&meson8_eth_clk_div.hw
++		},
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT,
++	},
++};
++
++static struct clk_regmap meson8_eth_clk_gate = {
++	.data = &(struct clk_regmap_gate_data) {
++		.offset = HHI_ETH_CLK_CNTL,
++		.bit_idx = 8,
++	},
++	.hw.init = &(struct clk_init_data){
++		.name = "eth_clk_en",
++		.ops = &clk_regmap_gate_ops,
++		.parent_hws = (const struct clk_hw *[]) {
++			&meson8_eth_clk_phase.hw
++		},
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT,
++	},
++};
++
+ #define MESON_GATE(_name, _reg, _bit) \
+ 	MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
+ 
+@@ -2978,6 +3051,10 @@ static struct clk_hw *meson8_hw_clks[] = {
+ 	[CLKID_CTS_I958]	    = &meson8b_cts_i958.hw,
+ 	[CLKID_VID_PLL_LVDS_EN]	    = &meson8b_vid_pll_lvds_en.hw,
+ 	[CLKID_HDMI_PLL_DCO_IN]	    = &hdmi_pll_dco_in.hw,
++	[CLKID_ETH_CLK_SEL]	    = &meson8_eth_clk_sel.hw,
++	[CLKID_ETH_CLK_DIV]	    = &meson8_eth_clk_div.hw,
++	[CLKID_ETH_CLK_PHASE]	    = &meson8_eth_clk_phase.hw,
++	[CLKID_ETH_CLK]		    = &meson8_eth_clk_gate.hw,
+ };
+ 
+ static struct clk_hw *meson8b_hw_clks[] = {
+@@ -3606,6 +3683,10 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
+ 	&meson8b_cts_mclk_i958,
+ 	&meson8b_cts_i958,
+ 	&meson8b_vid_pll_lvds_en,
++	&meson8_eth_clk_sel,
++	&meson8_eth_clk_div,
++	&meson8_eth_clk_phase,
++	&meson8_eth_clk_gate,
+ };
+ 
+ static const struct meson8b_clk_reset_line {
+diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
+index 111111111111..222222222222 100644
+--- a/drivers/clk/meson/meson8b.h
++++ b/drivers/clk/meson/meson8b.h
+@@ -43,6 +43,7 @@
+ #define HHI_MALI_CLK_CNTL		0x1b0 /* 0x6c offset in data sheet */
+ #define HHI_VPU_CLK_CNTL		0x1bc /* 0x6f offset in data sheet */
+ #define HHI_HDMI_CLK_CNTL		0x1cc /* 0x73 offset in data sheet */
++#define HHI_ETH_CLK_CNTL		0x1d8 /* 0x76 offset in data sheet */
+ #define HHI_VDEC_CLK_CNTL		0x1e0 /* 0x78 offset in data sheet */
+ #define HHI_VDEC2_CLK_CNTL		0x1e4 /* 0x79 offset in data sheet */
+ #define HHI_VDEC3_CLK_CNTL		0x1e8 /* 0x7a offset in data sheet */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0021-dt-bindings-net-dwmac-meson-Add-the-Ethernet-clock-i.patch b/patch/kernel/archive/meson-6.10/0021-dt-bindings-net-dwmac-meson-Add-the-Ethernet-clock-i.patch
new file mode 100644
index 000000000000..ec3546c577fb
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0021-dt-bindings-net-dwmac-meson-Add-the-Ethernet-clock-i.patch
@@ -0,0 +1,52 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 1 May 2020 23:37:35 +0200
+Subject: dt-bindings: net: dwmac-meson: Add the Ethernet clock input for
+ Meson6/8
+
+The additional DWMAC register on Amlogic Meson6 and Meson8 SoCs take a
+clock input (which is provided by the HHI clock controller). For RMII
+mode this clock is derived from the RMII reference clock. Document this
+clock input so the clock can be enabled when needed.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml | 22 ++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
++++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
+@@ -127,6 +127,28 @@ allOf:
+             - 2800
+             - 3000
+ 
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - amlogic,meson6-dwmac
++    then:
++      properties:
++        clocks:
++          minItems: 1
++          maxItems: 2
++          items:
++            - description: GMAC main clock
++            - description: The RMII reference clock
++
++        clock-names:
++          minItems: 1
++          maxItems: 2
++          items:
++            - const: stmmaceth
++            - const: ethernet
++
+ properties:
+   compatible:
+     additionalItems: true
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0022-net-stmmac-dwmac-meson-Rename-the-SPEED_100-macro.patch b/patch/kernel/archive/meson-6.10/0022-net-stmmac-dwmac-meson-Rename-the-SPEED_100-macro.patch
new file mode 100644
index 000000000000..37d4aecc6bbd
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0022-net-stmmac-dwmac-meson-Rename-the-SPEED_100-macro.patch
@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Dec 2021 04:07:05 +0100
+Subject: net: stmmac: dwmac-meson: Rename the SPEED_100 macro
+
+The SPEED_100 macro is part of the PREG_ETHERNET_ADDR0 register. Rename
+it accordingly to make this relationship clear.
+While here also add a comment what the SPEED_100 bit actually does.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
+index 111111111111..222222222222 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
+@@ -15,7 +15,8 @@
+ 
+ #include "stmmac_platform.h"
+ 
+-#define ETHMAC_SPEED_100	BIT(1)
++/* divides the input clock by 20 (= 0x0) or 2 (= 0x1) */
++#define PREG_ETHERNET_ADDR0_SPEED_100	BIT(1)
+ 
+ struct meson_dwmac {
+ 	struct device	*dev;
+@@ -31,10 +32,10 @@ static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed, unsigned
+ 
+ 	switch (speed) {
+ 	case SPEED_10:
+-		val &= ~ETHMAC_SPEED_100;
++		val &= ~PREG_ETHERNET_ADDR0_SPEED_100;
+ 		break;
+ 	case SPEED_100:
+-		val |= ETHMAC_SPEED_100;
++		val |= PREG_ETHERNET_ADDR0_SPEED_100;
+ 		break;
+ 	}
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0023-net-stmmac-dwmac-meson-Manage-the-ethernet-clock.patch b/patch/kernel/archive/meson-6.10/0023-net-stmmac-dwmac-meson-Manage-the-ethernet-clock.patch
new file mode 100644
index 000000000000..a2a4b0111beb
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0023-net-stmmac-dwmac-meson-Manage-the-ethernet-clock.patch
@@ -0,0 +1,117 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Dec 2021 04:22:53 +0100
+Subject: net: stmmac: dwmac-meson: Manage the "ethernet" clock
+
+Meson6 and Meson8 (both use the same glue registers on top of the DWMAC
+IP) have a dedicated Ethernet clock. For RMII mode the SoC has an input
+for an external RMII reference clock signal (which can be provided by
+either the PHY or an external oscillator). This clock needs to run at
+50MHz because the additional glue registers can divide by 2 - to achieve
+25MHz for 100Mbit/s line speed, or 20 - to achieve 2.5MHz for 10Mbit/s
+line speed.
+
+Set the correct frequency for this clock and enable it during init. Also
+enable the ETHMAC_DIV_EN bit which enables the divider in the glue
+registers, based on the Ethernet clock input.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c | 51 +++++++++-
+ 1 file changed, 50 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
+index 111111111111..222222222222 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
+@@ -5,6 +5,7 @@
+  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
+  */
+ 
++#include <linux/clk.h>
+ #include <linux/device.h>
+ #include <linux/ethtool.h>
+ #include <linux/io.h>
+@@ -15,12 +16,15 @@
+ 
+ #include "stmmac_platform.h"
+ 
++#define PREG_ETHERNET_ADDR0_DIV_EN	BIT(0)
++
+ /* divides the input clock by 20 (= 0x0) or 2 (= 0x1) */
+ #define PREG_ETHERNET_ADDR0_SPEED_100	BIT(1)
+ 
+ struct meson_dwmac {
+ 	struct device	*dev;
+ 	void __iomem	*reg;
++	struct clk	*ethernet_clk;
+ };
+ 
+ static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode)
+@@ -42,6 +46,33 @@ static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed, unsigned
+ 	writel(val, dwmac->reg);
+ }
+ 
++static int meson6_dwmac_init(struct platform_device *pdev, void *priv)
++{
++	struct meson_dwmac *dwmac = priv;
++	int ret;
++
++	ret = clk_set_rate(dwmac->ethernet_clk, 50 * 1000 * 1000);
++	if (ret)
++		return ret;
++
++	ret = clk_prepare_enable(dwmac->ethernet_clk);
++	if (ret)
++		return ret;
++
++	writel(readl(dwmac->reg) | PREG_ETHERNET_ADDR0_DIV_EN, dwmac->reg);
++
++	return 0;
++}
++
++static void meson6_dwmac_exit(struct platform_device *pdev, void *priv)
++{
++	struct meson_dwmac *dwmac = priv;
++
++	writel(readl(dwmac->reg) & ~PREG_ETHERNET_ADDR0_DIV_EN, dwmac->reg);
++
++	clk_disable_unprepare(dwmac->ethernet_clk);
++}
++
+ static int meson6_dwmac_probe(struct platform_device *pdev)
+ {
+ 	struct plat_stmmacenet_data *plat_dat;
+@@ -65,10 +96,28 @@ static int meson6_dwmac_probe(struct platform_device *pdev)
+ 	if (IS_ERR(dwmac->reg))
+ 		return PTR_ERR(dwmac->reg);
+ 
++	dwmac->ethernet_clk = devm_clk_get_optional(&pdev->dev, "ethernet");
++	if (IS_ERR(dwmac->ethernet_clk))
++		return PTR_ERR(dwmac->ethernet_clk);
++
+ 	plat_dat->bsp_priv = dwmac;
++	plat_dat->init = meson6_dwmac_init;
++	plat_dat->exit = meson6_dwmac_exit;
+ 	plat_dat->fix_mac_speed = meson6_dwmac_fix_mac_speed;
+ 
+-	return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
++	ret = meson6_dwmac_init(pdev, dwmac);
++	if (ret)
++		return ret;
++
++	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
++	if (ret)
++		goto err_exit_dwmac;
++
++	return 0;
++
++err_exit_dwmac:
++	meson6_dwmac_exit(pdev, dwmac);
++	return ret;
+ }
+ 
+ static const struct of_device_id meson6_dwmac_match[] = {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0024-net-stmmac-dwmac-meson-Initialize-all-known-PREG_ETH.patch b/patch/kernel/archive/meson-6.10/0024-net-stmmac-dwmac-meson-Initialize-all-known-PREG_ETH.patch
new file mode 100644
index 000000000000..de3a2f4aba60
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0024-net-stmmac-dwmac-meson-Initialize-all-known-PREG_ETH.patch
@@ -0,0 +1,76 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Dec 2021 04:18:30 +0100
+Subject: net: stmmac: dwmac-meson: Initialize all known PREG_ETHERNET_ADDR0
+ bits
+
+Initialize all known PREG_ETHERNET_ADDR0 register bits to be less
+dependent on the bootloader to set them up correctly.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c | 25 ++++++++--
+ 1 file changed, 22 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
+index 111111111111..222222222222 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
+@@ -5,6 +5,7 @@
+  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
+  */
+ 
++#include <linux/bitfield.h>
+ #include <linux/clk.h>
+ #include <linux/device.h>
+ #include <linux/ethtool.h>
+@@ -16,10 +17,20 @@
+ 
+ #include "stmmac_platform.h"
+ 
+-#define PREG_ETHERNET_ADDR0_DIV_EN	BIT(0)
++#define PREG_ETHERNET_ADDR0_DIV_EN			BIT(0)
+ 
+ /* divides the input clock by 20 (= 0x0) or 2 (= 0x1) */
+-#define PREG_ETHERNET_ADDR0_SPEED_100	BIT(1)
++#define PREG_ETHERNET_ADDR0_SPEED_100			BIT(1)
++
++/* 0x0 = little, 0x1 = big */
++#define PREG_ETHERNET_ADDR0_DATA_ENDIANNESS		BIT(2)
++
++/* 0x0 = same order, 0x1: unknown */
++#define PREG_ETHERNET_ADDR0_DESC_ENDIANNESS		BIT(3)
++
++#define PREG_ETHERNET_ADDR0_MII_MODE			GENMASK(6, 4)
++#define PREG_ETHERNET_ADDR0_MII_MODE_RGMII		0x1
++#define PREG_ETHERNET_ADDR0_MII_MODE_RMII		0x4
+ 
+ struct meson_dwmac {
+ 	struct device	*dev;
+@@ -49,6 +60,7 @@ static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed, unsigned
+ static int meson6_dwmac_init(struct platform_device *pdev, void *priv)
+ {
+ 	struct meson_dwmac *dwmac = priv;
++	u32 val;
+ 	int ret;
+ 
+ 	ret = clk_set_rate(dwmac->ethernet_clk, 50 * 1000 * 1000);
+@@ -59,7 +71,14 @@ static int meson6_dwmac_init(struct platform_device *pdev, void *priv)
+ 	if (ret)
+ 		return ret;
+ 
+-	writel(readl(dwmac->reg) | PREG_ETHERNET_ADDR0_DIV_EN, dwmac->reg);
++	val = readl(dwmac->reg);
++	val &= ~PREG_ETHERNET_ADDR0_DATA_ENDIANNESS;
++	val &= ~PREG_ETHERNET_ADDR0_DESC_ENDIANNESS;
++	val &= ~PREG_ETHERNET_ADDR0_MII_MODE;
++	val |= FIELD_PREP(PREG_ETHERNET_ADDR0_MII_MODE,
++			  PREG_ETHERNET_ADDR0_MII_MODE_RMII);
++	val |= PREG_ETHERNET_ADDR0_DIV_EN;
++	writel(val, dwmac->reg);
+ 
+ 	return 0;
+ }
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0025-ARM-dts-meson-meson8-Add-the-clock-input-to-the-Ethe.patch b/patch/kernel/archive/meson-6.10/0025-ARM-dts-meson-meson8-Add-the-clock-input-to-the-Ethe.patch
new file mode 100644
index 000000000000..f8c9c33b075d
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0025-ARM-dts-meson-meson8-Add-the-clock-input-to-the-Ethe.patch
@@ -0,0 +1,34 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 1 May 2020 23:47:47 +0200
+Subject: ARM: dts: meson: meson8: Add the clock input to the Ethernet
+ controller
+
+The Ethernet controller on Meson8 has an additional clock input from the
+HHI clock controller. The clock signal provides the RMII reference clock
+which is used to generate the internal 25MHz or 2.5MHz clocks depending
+on the line speed.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson8.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi
+@@ -613,8 +613,8 @@ temperature_calib: calib@1f4 {
+ };
+ 
+ &ethmac {
+-	clocks = <&clkc CLKID_ETH>;
+-	clock-names = "stmmaceth";
++	clocks = <&clkc CLKID_ETH>, <&clkc CLKID_ETH_CLK>;
++	clock-names = "stmmaceth", "ethernet";
+ 
+ 	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0026-dt-bindings-clock-meson8b-add-the-rtc_32k-oscillator.patch b/patch/kernel/archive/meson-6.10/0026-dt-bindings-clock-meson8b-add-the-rtc_32k-oscillator.patch
new file mode 100644
index 000000000000..e87a6e8b80a8
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0026-dt-bindings-clock-meson8b-add-the-rtc_32k-oscillator.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 1 Jan 2021 19:01:08 +0100
+Subject: dt-bindings: clock: meson8b: add the rtc_32k oscillator input
+
+The CLK81 tree can be driven off the 32kHz oscillator connected to the
+SoCs RTC32K_XI and RTC32K_XO pads. Add this clock as a valid input.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
++++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+@@ -18,6 +18,8 @@ Required Properties:
+   * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
+   * "rmii_clk": (if present) the 50MHz RMII reference clock (from the PHY or
+                 an external oscillator
++  * "rtc_32k": the clock signal from the 32kHz oscillator connected to the
++               RTC32K_XI and RTC32K_XO pads
+ 
+ Parent node should have the following properties :
+ - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0027-clk-meson-meson8b-Add-the-mpeg_rtc_osc_sel-clock.patch b/patch/kernel/archive/meson-6.10/0027-clk-meson-meson8b-Add-the-mpeg_rtc_osc_sel-clock.patch
new file mode 100644
index 000000000000..2271ffe73580
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0027-clk-meson-meson8b-Add-the-mpeg_rtc_osc_sel-clock.patch
@@ -0,0 +1,108 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 1 Jan 2021 18:55:05 +0100
+Subject: clk: meson: meson8b: Add the mpeg_rtc_osc_sel clock
+
+The first input of the CLK81 clock tree uses the SoC's external
+oscillators. By default it's the 24MHz XTAL from which most frequencies
+in this SoC are derived. For power-saving purposes there's a mux to
+switch the input between the 24MHz XTAL and the 32kHz RTC oscillator.
+Add support for that mux add it to the CLK81 clock tree for a better
+representation of how the hardware is actually designed.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/clk/meson/meson8b.c              | 26 +++++++++-
+ include/dt-bindings/clock/meson8b-clkc.h |  1 +
+ 2 files changed, 25 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
+index 111111111111..222222222222 100644
+--- a/drivers/clk/meson/meson8b.c
++++ b/drivers/clk/meson/meson8b.c
+@@ -611,7 +611,24 @@ static struct clk_regmap meson8b_mpll2 = {
+ 	},
+ };
+ 
+-static u32 mux_table_clk81[]	= { 6, 5, 7 };
++static struct clk_regmap meson8b_mpeg_rtc_osc_sel = {
++	.data = &(struct clk_regmap_mux_data){
++		.offset = HHI_MPEG_CLK_CNTL,
++		.mask = 0x1,
++		.shift = 9,
++	},
++	.hw.init = &(struct clk_init_data){
++		.name = "mpeg_rtc_osc_sel",
++		.ops = &clk_regmap_mux_ro_ops,
++		.parent_data = (const struct clk_parent_data[]) {
++			{ .fw_name = "xtal", .index = -1, },
++			{ .fw_name = "rtc_32k", .index = -1, },
++		},
++		.num_parents = 2,
++	},
++};
++
++static u32 mux_table_clk81[] = { 0, 6, 5, 7 };
+ static struct clk_regmap meson8b_mpeg_clk_sel = {
+ 	.data = &(struct clk_regmap_mux_data){
+ 		.offset = HHI_MPEG_CLK_CNTL,
+@@ -628,11 +645,12 @@ static struct clk_regmap meson8b_mpeg_clk_sel = {
+ 		 * fclk_div4, fclk_div3, fclk_div5
+ 		 */
+ 		.parent_hws = (const struct clk_hw *[]) {
++			&meson8b_mpeg_rtc_osc_sel.hw,
+ 			&meson8b_fclk_div3.hw,
+ 			&meson8b_fclk_div4.hw,
+ 			&meson8b_fclk_div5.hw,
+ 		},
+-		.num_parents = 3,
++		.num_parents = 4,
+ 	},
+ };
+ 
+@@ -3055,6 +3073,7 @@ static struct clk_hw *meson8_hw_clks[] = {
+ 	[CLKID_ETH_CLK_DIV]	    = &meson8_eth_clk_div.hw,
+ 	[CLKID_ETH_CLK_PHASE]	    = &meson8_eth_clk_phase.hw,
+ 	[CLKID_ETH_CLK]		    = &meson8_eth_clk_gate.hw,
++	[CLKID_MPEG_RTC_OSC_SEL]    = &meson8b_mpeg_rtc_osc_sel.hw,
+ };
+ 
+ static struct clk_hw *meson8b_hw_clks[] = {
+@@ -3270,6 +3289,7 @@ static struct clk_hw *meson8b_hw_clks[] = {
+ 	[CLKID_CTS_I958]	    = &meson8b_cts_i958.hw,
+ 	[CLKID_VID_PLL_LVDS_EN]	    = &meson8b_vid_pll_lvds_en.hw,
+ 	[CLKID_HDMI_PLL_DCO_IN]	    = &hdmi_pll_dco_in.hw,
++	[CLKID_MPEG_RTC_OSC_SEL]    = &meson8b_mpeg_rtc_osc_sel.hw,
+ };
+ 
+ static struct clk_hw *meson8m2_hw_clks[] = {
+@@ -3487,6 +3507,7 @@ static struct clk_hw *meson8m2_hw_clks[] = {
+ 	[CLKID_CTS_I958]	    = &meson8b_cts_i958.hw,
+ 	[CLKID_VID_PLL_LVDS_EN]	    = &meson8b_vid_pll_lvds_en.hw,
+ 	[CLKID_HDMI_PLL_DCO_IN]	    = &hdmi_pll_dco_in.hw,
++	[CLKID_MPEG_RTC_OSC_SEL]    = &meson8b_mpeg_rtc_osc_sel.hw,
+ };
+ 
+ static struct clk_regmap *const meson8b_clk_regmaps[] = {
+@@ -3687,6 +3708,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
+ 	&meson8_eth_clk_div,
+ 	&meson8_eth_clk_phase,
+ 	&meson8_eth_clk_gate,
++	&meson8b_mpeg_rtc_osc_sel,
+ };
+ 
+ static const struct meson8b_clk_reset_line {
+diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
+index 111111111111..222222222222 100644
+--- a/include/dt-bindings/clock/meson8b-clkc.h
++++ b/include/dt-bindings/clock/meson8b-clkc.h
+@@ -225,5 +225,6 @@
+ #define CLKID_ETH_CLK_DIV	219
+ #define CLKID_ETH_CLK_PHASE	220
+ #define CLKID_ETH_CLK		221
++#define CLKID_MPEG_RTC_OSC_SEL	222
+ 
+ #endif /* __MESON8B_CLKC_H */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0028-ARM-dts-meson-Add-address-cells-size-cells-and-range.patch b/patch/kernel/archive/meson-6.10/0028-ARM-dts-meson-Add-address-cells-size-cells-and-range.patch
new file mode 100644
index 000000000000..7e534e33657f
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0028-ARM-dts-meson-Add-address-cells-size-cells-and-range.patch
@@ -0,0 +1,84 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 28 Aug 2021 18:50:10 +0200
+Subject: ARM: dts: meson: Add #address-cells, #size-cells and ranges to hhi
+
+The HHI node has multiple child-nodes. Add #address-cells, #size-cells
+and ranges properties to the hhi node itself so the child-nodes can get
+their own offset and register sizes. Also add the reg property to the
+clock and power domain controllers inside the hhi region.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson.dtsi   | 3 +++
+ arch/arm/boot/dts/amlogic/meson8.dtsi  | 6 ++++--
+ arch/arm/boot/dts/amlogic/meson8b.dtsi | 6 ++++--
+ 3 files changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson.dtsi
+@@ -35,6 +35,9 @@ hhi: system-controller@4000 {
+ 					     "simple-mfd",
+ 					     "syscon";
+ 				reg = <0x4000 0x400>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0x0 0x4000 0x400>;
+ 			};
+ 
+ 			aiu: audio-controller@5400 {
+diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi
+@@ -625,16 +625,18 @@ &gpio_intc {
+ };
+ 
+ &hhi {
+-	clkc: clock-controller {
++	clkc: clock-controller@0 {
+ 		compatible = "amlogic,meson8-clkc";
++		reg = <0x0 0x39c>;
+ 		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ 		clock-names = "xtal", "ddr_pll";
+ 		#clock-cells = <1>;
+ 		#reset-cells = <1>;
+ 	};
+ 
+-	pwrc: power-controller {
++	pwrc: power-controller@100 {
+ 		compatible = "amlogic,meson8-pwrc";
++		reg = <0x100 0x10>;
+ 		#power-domain-cells = <1>;
+ 		amlogic,ao-sysctrl = <&pmu>;
+ 		clocks = <&clkc CLKID_VPU>;
+diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8b.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi
+@@ -586,16 +586,18 @@ &gpio_intc {
+ };
+ 
+ &hhi {
+-	clkc: clock-controller {
++	clkc: clock-controller@0 {
+ 		compatible = "amlogic,meson8b-clkc";
++		reg = <0x0 0x39c>;
+ 		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ 		clock-names = "xtal", "ddr_pll";
+ 		#clock-cells = <1>;
+ 		#reset-cells = <1>;
+ 	};
+ 
+-	pwrc: power-controller {
++	pwrc: power-controller@100 {
+ 		compatible = "amlogic,meson8b-pwrc";
++		reg = <0x100 0x10>;
+ 		#power-domain-cells = <1>;
+ 		amlogic,ao-sysctrl = <&pmu>;
+ 		resets = <&reset RESET_DBLK>,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0029-dt-bindings-firmware-Document-the-Amlogic-Meson6-8-8.patch b/patch/kernel/archive/meson-6.10/0029-dt-bindings-firmware-Document-the-Amlogic-Meson6-8-8.patch
new file mode 100644
index 000000000000..c7e40d3c8a67
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0029-dt-bindings-firmware-Document-the-Amlogic-Meson6-8-8.patch
@@ -0,0 +1,75 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 17 May 2021 22:50:25 +0200
+Subject: dt-bindings: firmware: Document the Amlogic Meson6/8/8b/8m2 TrustZone
+
+Amlogic Meson6/8/8b/8m2 SoCs can optionally use a TrustZone secure
+firmware. This prevents anything outside of the TEE (Trusted
+Execution Environment aka TrustZone secure firmware) from accessing
+certain functionality of these SoCs, such as (but not limited to):
+Bringing up/down secondary SMP cores, accessing the eFuse and getting
+the SoC misc version.
+ARM SMCCC is used for communication with the TrustZone secure
+firmware.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/firmware/meson/amlogic,meson-mx-trustzone-firmware.yaml | 47 ++++++++++
+ 1 file changed, 47 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/firmware/meson/amlogic,meson-mx-trustzone-firmware.yaml b/Documentation/devicetree/bindings/firmware/meson/amlogic,meson-mx-trustzone-firmware.yaml
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/Documentation/devicetree/bindings/firmware/meson/amlogic,meson-mx-trustzone-firmware.yaml
+@@ -0,0 +1,47 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++# Copyright 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++%YAML 1.2
++---
++$id: "http://devicetree.org/schemas/firmware/meson/amlogic,meson-mx-trustzone-firmware.yaml#"
++$schema: "http://devicetree.org/meta-schemas/core.yaml#"
++
++title: Amlogic Meson6/8/8b/8m2 TrustZone secure firmware
++
++description: |
++  Amlogic Meson6/8/8b/8m2 SoCs can optionally use a TrustZone secure
++  firmware. This prevents anything outside of the TEE (Trusted
++  Execution Environment aka TrustZone secure firmware) from accessing
++  certain functionality of these SoCs, such as (but not limited to):
++  Bringing up/down secondary SMP cores, accessing the eFuse and getting
++  the SoC misc version.
++  ARM SMCCC is used for communication with the TrustZone secure
++  firmware.
++
++maintainers:
++  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++
++properties:
++  compatible:
++    oneOf:
++      - items:
++          - enum:
++              - amlogic,meson6-trustzone-firmware
++              - amlogic,meson8-trustzone-firmware
++              - amlogic,meson8b-trustzone-firmware
++              - amlogic,meson8m2-trustzone-firmware
++          - const: amlogic,meson-mx-trustzone-firmware
++
++required:
++  - compatible
++
++additionalProperties: false
++
++examples:
++  - |
++    firmware {
++      trustzone-firmware {
++        compatible = "amlogic,meson8m2-trustzone-firmware",
++                     "amlogic,meson-mx-trustzone-firmware";
++      };
++    };
++...
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0030-dt-bindings-arm-cpus-Document-Meson8-TrustZone-firmw.patch b/patch/kernel/archive/meson-6.10/0030-dt-bindings-arm-cpus-Document-Meson8-TrustZone-firmw.patch
new file mode 100644
index 000000000000..1c5b8d4bd6f9
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0030-dt-bindings-arm-cpus-Document-Meson8-TrustZone-firmw.patch
@@ -0,0 +1,31 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 18 Dec 2021 16:38:16 +0100
+Subject: dt-bindings: arm: cpus: Document Meson8 TrustZone firmware
+ enable-method
+
+Amlogic Meson8 SoCs can run a TrustZone firmware. This results in the
+CPU registers not being accessible directly and instead require firmware
+calls for booting the secondary cores or powering off a CPU. Add a new
+compatible string for this enable-method.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/arm/cpus.yaml
++++ b/Documentation/devicetree/bindings/arm/cpus.yaml
+@@ -216,6 +216,7 @@ properties:
+           - allwinner,sun9i-a80-smp
+           - allwinner,sun8i-a83t-smp
+           - amlogic,meson8-smp
++          - amlogic,meson8-trustzone-firmware-smp
+           - amlogic,meson8b-smp
+           - arm,realview-smp
+           - aspeed,ast2600-smp
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0031-ARM-meson-Add-support-for-the-TrustZone-firmware.patch b/patch/kernel/archive/meson-6.10/0031-ARM-meson-Add-support-for-the-TrustZone-firmware.patch
new file mode 100644
index 000000000000..5d0fca16bab9
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0031-ARM-meson-Add-support-for-the-TrustZone-firmware.patch
@@ -0,0 +1,436 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 3 May 2021 00:34:53 +0200
+Subject: ARM: meson: Add support for the TrustZone firmware
+
+Amlogic Meson6/8/8b/8m2 SoCs can optionally use a TrustZone secure
+firmware. This prevents anything outside of the TEE (Trusted
+Execution Environment aka TrustZone secure firmware) from accessing
+certain functionality of these SoCs, such as (but not limited to):
+Bringing up/down secondary SMP cores, accessing the eFuse and getting
+the SoC misc version.
+ARM SMCCC is used for communication with the TrustZone secure
+firmware.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/mach-meson/Makefile                      |   2 +-
+ arch/arm/mach-meson/meson.c                       |   4 +
+ arch/arm/mach-meson/tz_firmware.c                 | 250 ++++++++++
+ arch/arm/mach-meson/tz_firmware.h                 |  76 +++
+ include/linux/firmware/meson/meson_mx_trustzone.h |  37 ++
+ 5 files changed, 368 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
+index 111111111111..222222222222 100644
+--- a/arch/arm/mach-meson/Makefile
++++ b/arch/arm/mach-meson/Makefile
+@@ -1,3 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+-obj-$(CONFIG_ARCH_MESON) += meson.o
++obj-$(CONFIG_ARCH_MESON) += meson.o tz_firmware.o
+ obj-$(CONFIG_SMP) += platsmp.o
+diff --git a/arch/arm/mach-meson/meson.c b/arch/arm/mach-meson/meson.c
+index 111111111111..222222222222 100644
+--- a/arch/arm/mach-meson/meson.c
++++ b/arch/arm/mach-meson/meson.c
+@@ -5,6 +5,8 @@
+ 
+ #include <asm/mach/arch.h>
+ 
++#include "tz_firmware.h"
++
+ static const char * const meson_common_board_compat[] = {
+ 	"amlogic,meson6",
+ 	"amlogic,meson8",
+@@ -17,4 +19,6 @@ DT_MACHINE_START(MESON, "Amlogic Meson platform")
+ 	.dt_compat	= meson_common_board_compat,
+ 	.l2c_aux_val	= 0,
+ 	.l2c_aux_mask	= ~0,
++	.init_early	= meson_mx_trustzone_firmware_init,
++	.reserve	= meson_mx_trustzone_firmware_reserve_mem,
+ MACHINE_END
+diff --git a/arch/arm/mach-meson/tz_firmware.c b/arch/arm/mach-meson/tz_firmware.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/arch/arm/mach-meson/tz_firmware.c
+@@ -0,0 +1,250 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++ */
++
++#include <linux/arm-smccc.h>
++#include <linux/firmware/meson/meson_mx_trustzone.h>
++#include <linux/memblock.h>
++#include <linux/of.h>
++
++#include <asm/firmware.h>
++#include <asm/hardware/cache-l2x0.h>
++#include <asm/outercache.h>
++
++#include "tz_firmware.h"
++
++struct meson_mx_trustzone_firmware_memconfig {
++	unsigned char name[64];
++	unsigned int start_phy_addr;
++	unsigned int end_phy_addr;
++} __packed;
++
++static struct meson_mx_trustzone_firmware_memconfig meson_firmware_memconfig[2];
++
++static int meson_mx_trustzone_firmware_hal_api(unsigned int cmd, u32 *args)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(MESON_CALL_TRUSTZONE_HAL_API, cmd, virt_to_phys(args), 0,
++		      0, 0, 0, 0, &res);
++
++	return res.a0;
++}
++
++static u32 meson_mx_trustzone_firmware_mon(unsigned int cmd, unsigned int arg0,
++					   unsigned int arg1)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(MESON_CALL_TRUSTZONE_MON, cmd, arg0, arg1, 0, 0, 0, 0,
++		      &res);
++
++	return res.a0;
++}
++
++static int meson_mx_trustzone_firmware_set_cpu_boot_addr(int cpu,
++							 unsigned long boot_addr){
++	return meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_CORE_BOOTADDR_INDEX,
++					       cpu, boot_addr);
++}
++
++static int meson_mx_trustzone_firmware_cpu_boot(int cpu)
++{
++	u32 ret, corectrl;
++
++	corectrl = meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_CORE_RD_CTRL_INDEX,
++						   0, 0);
++
++	corectrl |= BIT(cpu);
++
++	ret = meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_CORE_WR_CTRL_INDEX,
++					      corectrl, 0);
++	if (ret != corectrl)
++		return -EINVAL;
++
++	return 0;
++}
++
++static void meson_mx_trustzone_firmware_l2x0_write_sec(unsigned long val,
++						       unsigned int reg)
++{
++	u32 fn;
++
++	switch (reg) {
++	case L2X0_CTRL:
++		fn = MESON_TRUSTZONE_MON_L2X0_CTRL_INDEX;
++		break;
++
++	case L2X0_AUX_CTRL:
++		fn = MESON_TRUSTZONE_MON_L2X0_AUXCTRL_INDEX;
++		break;
++
++	case L310_TAG_LATENCY_CTRL:
++		fn = MESON_TRUSTZONE_MON_L2X0_TAGLATENCY_INDEX;
++		break;
++
++	case L310_DATA_LATENCY_CTRL:
++		fn = MESON_TRUSTZONE_MON_L2X0_DATALATENCY_INDEX;
++		break;
++
++	case L310_ADDR_FILTER_START:
++		fn = MESON_TRUSTZONE_MON_L2X0_FILTERSTART_INDEX;
++		break;
++
++	case L310_ADDR_FILTER_END:
++		fn = MESON_TRUSTZONE_MON_L2X0_FILTEREND_INDEX;
++		break;
++
++	case L2X0_DEBUG_CTRL:
++		fn = MESON_TRUSTZONE_MON_L2X0_DEBUG_INDEX;
++		break;
++
++	case L310_PREFETCH_CTRL:
++		fn = MESON_TRUSTZONE_MON_L2X0_PREFETCH_INDEX;
++		break;
++
++	case L310_POWER_CTRL:
++		fn = MESON_TRUSTZONE_MON_L2X0_POWER_INDEX;
++		break;
++
++	default:
++		pr_warn("Amlogic Meson TrustZone - unsupported L2X0 register 0x%08x\n",
++			reg);
++		return;
++	}
++
++	WARN_ON(meson_mx_trustzone_firmware_mon(fn, val, 0));
++}
++
++static int __maybe_unused meson_mx_trustzone_firmware_l2x0_init(void)
++{
++	if (IS_ENABLED(CONFIG_CACHE_L2X0))
++		outer_cache.write_sec = meson_mx_trustzone_firmware_l2x0_write_sec;
++
++	return 0;
++}
++
++static const struct firmware_ops meson_mx_trustzone_firmware_ops = {
++	.set_cpu_boot_addr	= meson_mx_trustzone_firmware_set_cpu_boot_addr,
++	.cpu_boot		= meson_mx_trustzone_firmware_cpu_boot,
++	.l2x0_init		= meson_mx_trustzone_firmware_l2x0_init,
++};
++
++void __init meson_mx_trustzone_firmware_init(void)
++{
++	if (!meson_mx_trustzone_firmware_available())
++		return;
++
++	pr_info("Running under Amlogic Meson TrustZone secure firmware.\n");
++
++	register_firmware_ops(&meson_mx_trustzone_firmware_ops);
++
++	call_firmware_op(l2x0_init);
++}
++
++static void __init meson_mx_trustzone_firmware_memconfig_init(void)
++{
++	unsigned int i, size;
++	u32 args[2] = {
++		__pa_symbol(meson_firmware_memconfig),
++		ARRAY_SIZE(meson_firmware_memconfig),
++	};
++	int ret;
++
++	ret = meson_mx_trustzone_firmware_hal_api(MESON_TRUSTZONE_HAL_API_MEMCONFIG,
++						  args);
++	if (ret) {
++		pr_err("Amlogic Meson TrustZone memconfig failed: %d\n", ret);
++		return;
++	}
++
++	for (i = 0; i < ARRAY_SIZE(meson_firmware_memconfig); i++) {
++		size = meson_firmware_memconfig[i].end_phy_addr -
++		       meson_firmware_memconfig[i].start_phy_addr;
++
++		pr_debug("\tAmlogic Meson TrustZone memblock[%d]: %s (%u bytes)\n",
++			 i, meson_firmware_memconfig[i].name, size);
++
++		ret = memblock_mark_nomap(meson_firmware_memconfig[i].start_phy_addr,
++					  size);
++		if (ret)
++			pr_err("Failed to reserve %u bytes for Amlogic Meson TrustZone memblock[%d] (%s): %d\n",
++			       size, i, meson_firmware_memconfig[i].name, ret);
++	}
++}
++
++static void __init meson_mx_trustzone_firmware_monitor_memory_init(void)
++{
++	u32 base, size;
++	int ret;
++
++	base = meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_MEM_BASE,
++					       0, 0);
++	WARN_ON(!base);
++
++	size = meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_MEM_TOTAL_SIZE,
++					       0, 0);
++	WARN_ON(!size);
++
++	ret = memblock_mark_nomap(base, size);
++	if (ret)
++		pr_err("Failed to reserve %u bytes of Amlogic Meson TrustZone monitor memory: %d\n",
++		       size, ret);
++}
++
++void __init meson_mx_trustzone_firmware_reserve_mem(void)
++{
++	if (!meson_mx_trustzone_firmware_available())
++		return;
++
++	meson_mx_trustzone_firmware_monitor_memory_init();
++	meson_mx_trustzone_firmware_memconfig_init();
++}
++
++bool meson_mx_trustzone_firmware_available(void)
++{
++	struct device_node *np;
++
++	np = of_find_compatible_node(NULL, NULL,
++				     "amlogic,meson-mx-trustzone-firmware");
++	if (!np)
++		return false;
++
++	of_node_put(np);
++
++	return true;
++}
++EXPORT_SYMBOL_GPL(meson_mx_trustzone_firmware_available);
++
++int meson_mx_trustzone_firmware_efuse_read(unsigned int offset,
++					   unsigned int bytes, void *buf)
++{
++	unsigned int read_bytes;
++	u32 args[5] = {
++		MESON_TRUSTZONE_HAL_API_EFUSE_CMD_READ,
++		offset,
++		bytes,
++		__pa_symbol(buf),
++		virt_to_phys(&read_bytes)
++	};
++	int ret;
++
++	ret = meson_mx_trustzone_firmware_hal_api(MESON_TRUSTZONE_HAL_API_EFUSE,
++						  args);
++	if (ret)
++		return -EIO;
++
++	if (read_bytes != bytes)
++		return -EINVAL;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(meson_mx_trustzone_firmware_efuse_read);
++
++u32 meson_mx_trustzone_read_soc_rev1(void)
++{
++	return meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_CORE_RD_SOC_REV1,
++					       0, 0);
++}
++EXPORT_SYMBOL_GPL(meson_mx_trustzone_read_soc_rev1);
+diff --git a/arch/arm/mach-meson/tz_firmware.h b/arch/arm/mach-meson/tz_firmware.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/arch/arm/mach-meson/tz_firmware.h
+@@ -0,0 +1,76 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Amlogic Meson6/8/8b/8m2 secure TrustZone firmware definitions.
++ *
++ * Based on meson-secure.c and meson-secure.h from the Amlogic vendor kernel:
++ *   Copyright (C) 2002 ARM Ltd.
++ *   Copyright (c) 2010, Code Aurora Forum. All rights reserved.
++ *   Copyright (C) 2013 Amlogic, Inc.
++ *     Author: Platform-SH@amlogic.com
++ *
++ * Copyright (C) 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++ */
++
++/* Meson Secure Monitor/HAL APIs */
++#define MESON_CALL_TRUSTZONE_API			0x1
++#define MESON_CALL_TRUSTZONE_MON			0x4
++#define MESON_CALL_TRUSTZONE_HAL_API			0x5
++
++/* Secure Monitor mode APIs */
++#define MESON_TRUSTZONE_MON_TYPE_MASK			0xF00
++#define MESON_TRUSTZONE_MON_FUNC_MASK			0x0FF
++
++#define MESON_TRUSTZONE_MON_L2X0			0x100
++#define MESON_TRUSTZONE_MON_L2X0_CTRL_INDEX		0x101
++#define MESON_TRUSTZONE_MON_L2X0_AUXCTRL_INDEX		0x102
++#define MESON_TRUSTZONE_MON_L2X0_PREFETCH_INDEX		0x103
++#define MESON_TRUSTZONE_MON_L2X0_TAGLATENCY_INDEX	0x104
++#define MESON_TRUSTZONE_MON_L2X0_DATALATENCY_INDEX	0x105
++#define MESON_TRUSTZONE_MON_L2X0_FILTERSTART_INDEX	0x106
++#define MESON_TRUSTZONE_MON_L2X0_FILTEREND_INDEX	0x107
++#define MESON_TRUSTZONE_MON_L2X0_DEBUG_INDEX		0x108
++#define MESON_TRUSTZONE_MON_L2X0_POWER_INDEX		0x109
++
++#define MESON_TRUSTZONE_MON_CORE			0x200
++#define MESON_TRUSTZONE_MON_CORE_RD_CTRL_INDEX		0x201
++#define MESON_TRUSTZONE_MON_CORE_WR_CTRL_INDEX		0x202
++#define MESON_TRUSTZONE_MON_CORE_RD_STATUS0_INDEX	0x203
++#define MESON_TRUSTZONE_MON_CORE_WR_STATUS0_INDEX	0x204
++#define MESON_TRUSTZONE_MON_CORE_RD_STATUS1_INDEX	0x205
++#define MESON_TRUSTZONE_MON_CORE_WR_STATUS1_INDEX	0x206
++#define MESON_TRUSTZONE_MON_CORE_BOOTADDR_INDEX		0x207
++#define MESON_TRUSTZONE_MON_CORE_DDR_INDEX		0x208
++#define MESON_TRUSTZONE_MON_CORE_RD_SOC_REV1		0x209
++#define MESON_TRUSTZONE_MON_CORE_RD_SOC_REV2		0x20A
++
++#define MESON_TRUSTZONE_MON_SUSPEND_FIRMWARE		0x300
++#define MESON_TRUSTZONE_MON_SAVE_CPU_GIC		0x400
++
++#define MESON_TRUSTZONE_MON_RTC				0x500
++#define MESON_TRUSTZONE_MON_RTC_RD_REG_INDEX		0x501
++#define MESON_TRUSTZONE_MON_RTC_WR_REG_INDEX		0x502
++
++#define MESON_TRUSTZONE_MON_REG				0x600
++#define MESON_TRUSTZONE_MON_REG_RD_INDEX		0x601
++#define MESON_TRUSTZONE_MON_REG_WR_INDEX		0x602
++
++#define MESON_TRUSTZONE_MON_MEM				0x700
++#define MESON_TRUSTZONE_MON_MEM_BASE			0x701
++#define MESON_TRUSTZONE_MON_MEM_TOTAL_SIZE		0x702
++#define MESON_TRUSTZONE_MON_MEM_FLASH			0x703
++#define MESON_TRUSTZONE_MON_MEM_FLASH_SIZE		0x704
++#define MESON_TRUSTZONE_MON_MEM_GE2D			0x705
++
++/* Secure HAL APIs*/
++#define MESON_TRUSTZONE_HAL_API_EFUSE			0x100
++#define MESON_TRUSTZONE_HAL_API_EFUSE_CMD_READ		0x0
++#define MESON_TRUSTZONE_HAL_API_EFUSE_CMD_WRITE		0x1
++#define MESON_TRUSTZONE_HAL_API_EFUSE_CMD_VERIFY_IMG	0x3
++
++#define MESON_TRUSTZONE_HAL_API_STORAGE			0x200
++
++#define MESON_TRUSTZONE_HAL_API_MEMCONFIG		0x300
++#define MESON_TRUSTZONE_HAL_API_MEMCONFIG_GE2D		0x301
++
++void __init meson_mx_trustzone_firmware_init(void);
++void __init meson_mx_trustzone_firmware_reserve_mem(void);
+diff --git a/include/linux/firmware/meson/meson_mx_trustzone.h b/include/linux/firmware/meson/meson_mx_trustzone.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/include/linux/firmware/meson/meson_mx_trustzone.h
+@@ -0,0 +1,37 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (C) 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++ */
++
++#include <linux/errno.h>
++#include <linux/types.h>
++
++#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_MESON)
++
++bool meson_mx_trustzone_firmware_available(void);
++
++int meson_mx_trustzone_firmware_efuse_read(unsigned int offset,
++					   unsigned int bytes, void *buf);
++
++u32 meson_mx_trustzone_read_soc_rev1(void);
++
++#else
++
++static inline bool meson_mx_trustzone_firmware_available(void)
++{
++	return false;
++}
++
++static inline int meson_mx_trustzone_firmware_efuse_read(unsigned int offset,
++							 unsigned int bytes,
++							 void *buf)
++{
++	return -EINVAL;
++}
++
++static inline u32 meson_mx_trustzone_read_soc_rev1(void)
++{
++	return 0;
++}
++
++#endif
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0032-ARM-meson-platsmp-Add-support-for-SoCs-running-on-Tr.patch b/patch/kernel/archive/meson-6.10/0032-ARM-meson-platsmp-Add-support-for-SoCs-running-on-Tr.patch
new file mode 100644
index 000000000000..df0e646f58d9
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0032-ARM-meson-platsmp-Add-support-for-SoCs-running-on-Tr.patch
@@ -0,0 +1,75 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 3 May 2021 08:36:16 +0200
+Subject: ARM: meson: platsmp: Add support for SoCs running on TrustZone
+ firmware
+
+When the SoC is running on the TrustZone firmware we cannot modify the
+SMP related registers. Add a new set of SMP ops which use firmware calls
+to set the startup (function) address and core control (on/off).
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/mach-meson/platsmp.c | 33 ++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c
+index 111111111111..222222222222 100644
+--- a/arch/arm/mach-meson/platsmp.c
++++ b/arch/arm/mach-meson/platsmp.c
+@@ -16,6 +16,7 @@
+ 
+ #include <asm/cacheflush.h>
+ #include <asm/cp15.h>
++#include <asm/firmware.h>
+ #include <asm/smp_scu.h>
+ #include <asm/smp_plat.h>
+ 
+@@ -291,6 +292,31 @@ static int meson8b_smp_boot_secondary(unsigned int cpu,
+ 	return 0;
+ }
+ 
++static int meson8_smp_trustzone_firmware_boot_secondary(unsigned int cpu,
++							struct task_struct *idle)
++{
++	unsigned int addr = __pa_symbol(secondary_startup);
++	int ret;
++
++	ret = call_firmware_op(set_cpu_boot_addr, cpu, addr);
++	if (ret) {
++		pr_err("Failed to set aux core boot address for CPU%u using TrustZone secure firmware\n",
++			cpu);
++		return ret;
++	}
++
++	ret = call_firmware_op(cpu_boot, cpu);
++	if (ret) {
++		pr_err("Failed to modify core control for CPU%u using TrustZone secure firmware\n",
++			cpu);
++		return ret;
++	}
++
++	udelay(10);
++
++	return 0;
++}
++
+ #ifdef CONFIG_HOTPLUG_CPU
+ static void meson8_smp_cpu_die(unsigned int cpu)
+ {
+@@ -428,5 +454,12 @@ static struct smp_operations meson8b_smp_ops __initdata = {
+ #endif
+ };
+ 
++static struct smp_operations meson8_smp_trustzone_firmware_ops __initdata = {
++	.smp_boot_secondary	= meson8_smp_trustzone_firmware_boot_secondary,
++};
++
+ CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops);
+ CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops);
++CPU_METHOD_OF_DECLARE(meson8_trustzone_firmware_smp,
++		      "amlogic,meson8-trustzone-firmware-smp",
++		      &meson8_smp_trustzone_firmware_ops);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0033-soc-amlogic-meson-mx-socinfo-Add-support-for-the-Tru.patch b/patch/kernel/archive/meson-6.10/0033-soc-amlogic-meson-mx-socinfo-Add-support-for-the-Tru.patch
new file mode 100644
index 000000000000..ab4633b2e36d
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0033-soc-amlogic-meson-mx-socinfo-Add-support-for-the-Tru.patch
@@ -0,0 +1,68 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 16 May 2021 19:48:54 +0200
+Subject: soc: amlogic: meson-mx-socinfo: Add support for the TrustZone
+ firmware
+
+When the TrustZone firmware is enabled the SoC is configured so the boot
+ROM cannot be read from the (untrusted) Linux kernel. Instead a firmware
+call needs to be used to get the SoC's "misc" version.
+Add support for the firmware call to retrieve the SoC's misc version if
+the TrustZone firmware is loaded.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/soc/amlogic/meson-mx-socinfo.c | 23 ++++++----
+ 1 file changed, 15 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/soc/amlogic/meson-mx-socinfo.c b/drivers/soc/amlogic/meson-mx-socinfo.c
+index 111111111111..222222222222 100644
+--- a/drivers/soc/amlogic/meson-mx-socinfo.c
++++ b/drivers/soc/amlogic/meson-mx-socinfo.c
+@@ -4,6 +4,7 @@
+  * SPDX-License-Identifier: GPL-2.0+
+  */
+ 
++#include <linux/firmware/meson/meson_mx_trustzone.h>
+ #include <linux/io.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+@@ -118,10 +119,12 @@ static int __init meson_mx_socinfo_init(void)
+ 	if (IS_ERR(assist_regmap))
+ 		return PTR_ERR(assist_regmap);
+ 
+-	bootrom_regmap =
+-		syscon_regmap_lookup_by_compatible("amlogic,meson-mx-bootrom");
+-	if (IS_ERR(bootrom_regmap))
+-		return PTR_ERR(bootrom_regmap);
++	if (!meson_mx_trustzone_firmware_available()) {
++		bootrom_regmap =
++			syscon_regmap_lookup_by_compatible("amlogic,meson-mx-bootrom");
++		if (IS_ERR(bootrom_regmap))
++			return PTR_ERR(bootrom_regmap);
++	}
+ 
+ 	np = of_find_matching_node(NULL, meson_mx_socinfo_analog_top_ids);
+ 	if (np) {
+@@ -141,10 +144,14 @@ static int __init meson_mx_socinfo_init(void)
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	ret = regmap_read(bootrom_regmap, MESON_MX_BOOTROM_MISC_VER,
+-			  &misc_ver);
+-	if (ret < 0)
+-		return ret;
++	if (meson_mx_trustzone_firmware_available()) {
++		misc_ver = meson_mx_trustzone_read_soc_rev1();
++	} else {
++		ret = regmap_read(bootrom_regmap, MESON_MX_BOOTROM_MISC_VER,
++				  &misc_ver);
++		if (ret < 0)
++			return ret;
++	}
+ 
+ 	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+ 	if (!soc_dev_attr)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0034-nvmem-meson-mx-efuse-Add-support-for-the-TrustZone-f.patch b/patch/kernel/archive/meson-6.10/0034-nvmem-meson-mx-efuse-Add-support-for-the-TrustZone-f.patch
new file mode 100644
index 000000000000..a4019c70a137
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0034-nvmem-meson-mx-efuse-Add-support-for-the-TrustZone-f.patch
@@ -0,0 +1,73 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 3 May 2021 00:35:22 +0200
+Subject: nvmem: meson-mx-efuse: Add support for the TrustZone firmware
+ interface
+
+Some boards have a TrustZone firmware which prevents us from accessing
+(most of) the eFuse registers. On these boards we must use read the
+eFuse through TrustZone firmware calls (using SMC).
+Implement a .reg_read op using the Meson TrustZone firmware interface.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/nvmem/meson-mx-efuse.c | 29 +++++++++-
+ 1 file changed, 28 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/nvmem/meson-mx-efuse.c b/drivers/nvmem/meson-mx-efuse.c
+index 111111111111..222222222222 100644
+--- a/drivers/nvmem/meson-mx-efuse.c
++++ b/drivers/nvmem/meson-mx-efuse.c
+@@ -9,6 +9,7 @@
+ #include <linux/bitops.h>
+ #include <linux/clk.h>
+ #include <linux/delay.h>
++#include <linux/firmware/meson/meson_mx_trustzone.h>
+ #include <linux/io.h>
+ #include <linux/iopoll.h>
+ #include <linux/module.h>
+@@ -165,6 +166,28 @@ static int meson_mx_efuse_read(void *context, unsigned int offset,
+ 	return err;
+ }
+ 
++static int meson_mx_efuse_read_trustzone_firmware(void *context,
++						  unsigned int offset,
++						  void *buf, size_t bytes)
++{
++	struct meson_mx_efuse *efuse = context;
++	unsigned int tmp;
++	int i, ret;
++
++	for (i = 0; i < bytes; i += efuse->config.word_size) {
++		ret = meson_mx_trustzone_firmware_efuse_read(offset + i,
++							     sizeof(tmp),
++							     &tmp);
++		if (ret)
++			return ret;
++
++		memcpy(buf + i, &tmp,
++		       min_t(size_t, bytes - i, efuse->config.word_size));
++	}
++
++	return 0;
++}
++
+ static const struct meson_mx_efuse_platform_data meson6_efuse_data = {
+ 	.name = "meson6-efuse",
+ 	.word_size = 1,
+@@ -215,7 +238,11 @@ static int meson_mx_efuse_probe(struct platform_device *pdev)
+ 	efuse->config.word_size = drvdata->word_size;
+ 	efuse->config.size = SZ_512;
+ 	efuse->config.read_only = true;
+-	efuse->config.reg_read = meson_mx_efuse_read;
++
++	if (meson_mx_trustzone_firmware_available())
++		efuse->config.reg_read = meson_mx_efuse_read_trustzone_firmware;
++	else
++		efuse->config.reg_read = meson_mx_efuse_read;
+ 
+ 	efuse->core_clk = devm_clk_get(&pdev->dev, "core");
+ 	if (IS_ERR(efuse->core_clk)) {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0036-ARM-dts-meson8-Add-the-PWM_C-DV9-and-PWM_D-pins.patch b/patch/kernel/archive/meson-6.10/0036-ARM-dts-meson8-Add-the-PWM_C-DV9-and-PWM_D-pins.patch
new file mode 100644
index 000000000000..efea3f1a0dbb
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0036-ARM-dts-meson8-Add-the-PWM_C-DV9-and-PWM_D-pins.patch
@@ -0,0 +1,45 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Thu, 22 Jul 2021 08:27:29 +0200
+Subject: ARM: dts: meson8: Add the PWM_C (DV9) and PWM_D pins
+
+There are some Meson8m2 boards which don't use a PMIC (like Ricoh
+RN5T618) but use two PWM regulators for VCCK and VDDEE. Add the PWM_C
+(DV9) and PWM_D pins so the pinctrl settings can be applied on those
+boards.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson8.dtsi | 16 ++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi
+@@ -479,6 +479,22 @@ gpio: banks@80b0 {
+ 			gpio-ranges = <&pinctrl_cbus 0 0 120>;
+ 		};
+ 
++		pwm_c_dv9_pins: pwm-c-dv9 {
++			mux {
++				groups = "pwm_c_dv9";
++				function = "pwm_c";
++				bias-disable;
++			};
++		};
++
++		pwm_d_pins: pwm-d {
++			mux {
++				groups = "pwm_d";
++				function = "pwm_d";
++				bias-disable;
++			};
++		};
++
+ 		sd_a_pins: sd-a {
+ 			mux {
+ 				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0045-dt-bindings-display-meson-vpu-add-support-for-Meson8.patch b/patch/kernel/archive/meson-6.10/0045-dt-bindings-display-meson-vpu-add-support-for-Meson8.patch
new file mode 100644
index 000000000000..22a9eebf8ac7
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0045-dt-bindings-display-meson-vpu-add-support-for-Meson8.patch
@@ -0,0 +1,32 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Apr 2020 22:16:15 +0200
+Subject: dt-bindings: display: meson-vpu: add support for Meson8/8b/8m2 - WiP
+
+WiP
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
++++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
+@@ -66,8 +66,12 @@ properties:
+           - const: amlogic,meson-gx-vpu
+       - enum:
+           - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
++          - amlogic,meson8-vpu
++          - amlogic,meson8b-vpu
++          - amlogic,meson8m2-vpu
+ 
+   reg:
++    minItems: 1
+     maxItems: 2
+ 
+   reg-names:
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0046-drm-meson-add-Meson8-Meson8b-Meson8m2-specific-vpu_c.patch b/patch/kernel/archive/meson-6.10/0046-drm-meson-add-Meson8-Meson8b-Meson8m2-specific-vpu_c.patch
new file mode 100644
index 000000000000..65820dd16898
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0046-drm-meson-add-Meson8-Meson8b-Meson8m2-specific-vpu_c.patch
@@ -0,0 +1,39 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Apr 2020 21:50:45 +0200
+Subject: drm/meson: add Meson8/Meson8b/Meson8m2 specific vpu_compatible
+ entries
+
+Add values for Meson8/Meson8b/Meson8m2 to enum vpu_compatible so quirks
+for these earlier hardware generations can be added to the driver.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_drv.h | 11 ++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_drv.h
++++ b/drivers/gpu/drm/meson/meson_drv.h
+@@ -20,10 +20,13 @@ struct phy;
+ struct platform_device;
+ 
+ enum vpu_compatible {
+-	VPU_COMPATIBLE_GXBB = 0,
+-	VPU_COMPATIBLE_GXL  = 1,
+-	VPU_COMPATIBLE_GXM  = 2,
+-	VPU_COMPATIBLE_G12A = 3,
++	VPU_COMPATIBLE_M8 = 0,
++	VPU_COMPATIBLE_M8B = 1,
++	VPU_COMPATIBLE_M8M2 = 2,
++	VPU_COMPATIBLE_GXBB = 3,
++	VPU_COMPATIBLE_GXL  = 4,
++	VPU_COMPATIBLE_GXM  = 5,
++	VPU_COMPATIBLE_G12A = 6,
+ };
+ 
+ enum {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0047-drm-meson-Use-24-bits-per-pixel-for-the-framebuffer-.patch b/patch/kernel/archive/meson-6.10/0047-drm-meson-Use-24-bits-per-pixel-for-the-framebuffer-.patch
new file mode 100644
index 000000000000..cd0b0904223b
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0047-drm-meson-Use-24-bits-per-pixel-for-the-framebuffer-.patch
@@ -0,0 +1,66 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 26 Apr 2020 00:00:09 +0200
+Subject: drm/meson: Use 24 bits per pixel for the framebuffer on Meson8/8b/8m2
+
+All SoC generations before GXBB don't have a way to configure the
+alpha value for DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888. These
+formats have an X component instead of an alpha component. On
+Meson8/8b/8m2 there is no way to configure the alpha value to use
+instead of the X component. This results in the fact that the
+formats with X component are only supported on GXBB and newer. Use
+24 bits per pixel and therefore DRM_FORMAT_RGB888 to get a
+working framebuffer console.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_drv.c | 26 +++++++++-
+ 1 file changed, 25 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_drv.c
++++ b/drivers/gpu/drm/meson/meson_drv.c
+@@ -159,6 +159,30 @@ static void meson_vpu_init(struct meson_drm *priv)
+ 	writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
+ }
+ 
++static void meson_fbdev_setup(struct meson_drm *priv)
++{
++	unsigned int preferred_bpp;
++
++	/*
++	 * All SoC generations before GXBB don't have a way to configure the
++	 * alpha value for DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888. These
++	 * formats have an X component instead of an alpha component. On
++	 * Meson8/8b/8m2 there is no way to configure the alpha value to use
++	 * instead of the X component. This results in the fact that the
++	 * formats with X component are only supported on GXBB and newer. Use
++	 * 24 bits per pixel and therefore DRM_FORMAT_RGB888 to get a
++	 * working framebuffer console.
++	 */
++	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2))
++		preferred_bpp = 24;
++	else
++		preferred_bpp = 32;
++
++	drm_fbdev_dma_setup(priv->drm, preferred_bpp);
++}
++
+ struct meson_drm_soc_attr {
+ 	struct meson_drm_soc_limits limits;
+ 	const struct soc_device_attribute *attrs;
+@@ -362,7 +386,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
+ 	if (ret)
+ 		goto uninstall_irq;
+ 
+-	drm_fbdev_dma_setup(drm, 32);
++	meson_fbdev_setup(priv);
+ 
+ 	return 0;
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0048-drm-meson-Use-a-separate-list-of-supported-formats-f.patch b/patch/kernel/archive/meson-6.10/0048-drm-meson-Use-a-separate-list-of-supported-formats-f.patch
new file mode 100644
index 000000000000..476a7933e8a7
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0048-drm-meson-Use-a-separate-list-of-supported-formats-f.patch
@@ -0,0 +1,83 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Apr 2020 21:53:21 +0200
+Subject: drm/meson: Use a separate list of supported formats for 32-bit SoCs
+
+The VIU_OSD1_CTRL_STAT2 and VIU_OSD2_CTRL_STAT2 registers on
+Meson8/Meson8b/Meson8m2 don't have the following bits:
+- replaced_alpha_en in bit [14]
+- replaced_alpha in bits [13:6]
+
+This results in formats with X component (currently DRM_FORMAT_XRGB8888
+and DRM_FORMAT_XBGR8888 are supported on GXBB and later) are not
+supported. Depending on the application this may work (kmscube for
+example - which seems to properly set 0xff as alpha component), but
+there's other examples (Kodi for example) where there are alpha blending
+issues because the alpha value is not defined (and thus some random
+value).
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_plane.c | 30 +++++++++-
+ 1 file changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_plane.c
++++ b/drivers/gpu/drm/meson/meson_plane.c
+@@ -471,7 +471,20 @@ static const struct drm_plane_funcs meson_plane_funcs = {
+ 	.format_mod_supported   = meson_plane_format_mod_supported,
+ };
+ 
+-static const uint32_t supported_drm_formats[] = {
++/*
++ * X components (for example in DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888)
++ * are not supported because these older SoC's are lacking the OSD_REPLACE_EN
++ * bit to replace the X alpha component with a static value, leaving the alpha
++ * component in an undefined state.
++ */
++static const uint32_t supported_drm_formats_m8[] = {
++	DRM_FORMAT_ARGB8888,
++	DRM_FORMAT_ABGR8888,
++	DRM_FORMAT_RGB888,
++	DRM_FORMAT_RGB565,
++};
++
++static const uint32_t supported_drm_formats_gx[] = {
+ 	DRM_FORMAT_ARGB8888,
+ 	DRM_FORMAT_ABGR8888,
+ 	DRM_FORMAT_XRGB8888,
+@@ -533,6 +546,8 @@ int meson_plane_create(struct meson_drm *priv)
+ {
+ 	struct meson_plane *meson_plane;
+ 	struct drm_plane *plane;
++	unsigned int num_drm_formats;
++	const uint32_t *drm_formats;
+ 	const uint64_t *format_modifiers = format_modifiers_default;
+ 
+ 	meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane),
+@@ -548,10 +563,19 @@ int meson_plane_create(struct meson_drm *priv)
+ 	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+ 		format_modifiers = format_modifiers_afbc_g12a;
+ 
++	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) {
++		drm_formats = supported_drm_formats_m8;
++		num_drm_formats = ARRAY_SIZE(supported_drm_formats_m8);
++	} else {
++		drm_formats = supported_drm_formats_gx;
++		num_drm_formats = ARRAY_SIZE(supported_drm_formats_gx);
++	}
++
+ 	drm_universal_plane_init(priv->drm, plane, 0xFF,
+ 				 &meson_plane_funcs,
+-				 supported_drm_formats,
+-				 ARRAY_SIZE(supported_drm_formats),
++				 drm_formats, num_drm_formats,
+ 				 format_modifiers,
+ 				 DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0049-drm-meson-Skip-VIU_OSD1_CTRL_STAT2-alpha-replace-val.patch b/patch/kernel/archive/meson-6.10/0049-drm-meson-Skip-VIU_OSD1_CTRL_STAT2-alpha-replace-val.patch
new file mode 100644
index 000000000000..3e3f2d47a692
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0049-drm-meson-Skip-VIU_OSD1_CTRL_STAT2-alpha-replace-val.patch
@@ -0,0 +1,52 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 31 Jan 2022 23:02:59 +0100
+Subject: drm/meson: Skip VIU_OSD1_CTRL_STAT2 alpha replace value
+ initialization
+
+The VIU_OSD1_CTRL_STAT2 and VIU_OSD2_CTRL_STAT2 registers on
+Meson8/Meson8b/Meson8m2 don't have the following bits:
+- replaced_alpha_en in bit [14]
+- replaced_alpha in bits [13:6]
+
+Don't initialize the replaced_alpha register bits in VIU_OSD1_CTRL_STAT2
+on Meson8/Meson8b/Meson8m2 because they are not implemented on those
+SoCs.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_viu.c | 18 ++++++----
+ 1 file changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_viu.c
++++ b/drivers/gpu/drm/meson/meson_viu.c
+@@ -448,13 +448,17 @@ void meson_viu_init(struct meson_drm *priv)
+ 	writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
+ 	writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
+ 
+-	/* Set OSD alpha replace value */
+-	writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
+-			    0xff << OSD_REPLACE_SHIFT,
+-			    priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
+-	writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
+-			    0xff << OSD_REPLACE_SHIFT,
+-			    priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
++	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) &&
++	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) &&
++	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) {
++		/* Set OSD alpha replace value */
++		writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
++				    0xff << OSD_REPLACE_SHIFT,
++				    priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
++		writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
++				    0xff << OSD_REPLACE_SHIFT,
++				    priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
++	}
+ 
+ 	/* Disable VD1 AFBC */
+ 	/* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0050-drm-meson-Enable-the-RGB-to-YUV-converter-on-Meson8-.patch b/patch/kernel/archive/meson-6.10/0050-drm-meson-Enable-the-RGB-to-YUV-converter-on-Meson8-.patch
new file mode 100644
index 000000000000..f8e8e65c2c98
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0050-drm-meson-Enable-the-RGB-to-YUV-converter-on-Meson8-.patch
@@ -0,0 +1,34 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Apr 2020 22:00:57 +0200
+Subject: drm/meson: Enable the RGB to YUV converter on Meson8/Meson8b/Meson8m2
+
+Set VIU_OSD1_BLK0_CFG_W0[7] to 1 to enable RGB to YUV converter, just
+like on GXBB.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_plane.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_plane.c
++++ b/drivers/gpu/drm/meson/meson_plane.c
+@@ -200,8 +200,11 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
+ 			priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD;
+ 	}
+ 
+-	/* On GXBB, Use the old non-HDR RGB2YUV converter */
+-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
++	/* On GXBB and earlier, Use the old non-HDR RGB2YUV converter */
++	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
+ 		priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
+ 
+ 	if (priv->viu.osd1_afbcd &&
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0051-drm-meson-Update-meson_vpu_init-to-work-with-Meson8-.patch b/patch/kernel/archive/meson-6.10/0051-drm-meson-Update-meson_vpu_init-to-work-with-Meson8-.patch
new file mode 100644
index 000000000000..6b9753736f3e
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0051-drm-meson-Update-meson_vpu_init-to-work-with-Meson8-.patch
@@ -0,0 +1,84 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Apr 2020 22:03:27 +0200
+Subject: drm/meson: Update meson_vpu_init to work with Meson8/Meson8b/Meson8m2
+
+Don't modify the VPU_RDARB_MODE_* registers because they only exist on
+GXBB and newer SoCs. Initialize the VPU_MEM_PD_REG0 and VPU_MEM_PD_REG1
+to 0x0 (meaning: enable everything), just like vendor u-boot does for
+Meson8/Meson8b/Meson8m2.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_drv.c | 55 ++++++----
+ 1 file changed, 33 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_drv.c
++++ b/drivers/gpu/drm/meson/meson_drv.c
+@@ -135,28 +135,39 @@ static struct regmap_config meson_regmap_config = {
+ 
+ static void meson_vpu_init(struct meson_drm *priv)
+ {
+-	u32 value;
+-
+-	/*
+-	 * Slave dc0 and dc5 connected to master port 1.
+-	 * By default other slaves are connected to master port 0.
+-	 */
+-	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
+-		VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
+-	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
+-
+-	/* Slave dc0 connected to master port 1 */
+-	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
+-	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
+-
+-	/* Slave dc4 and dc7 connected to master port 1 */
+-	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
+-		VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
+-	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
+-
+-	/* Slave dc1 connected to master port 1 */
+-	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
+-	writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
++	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) {
++		writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG0));
++		writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG1));
++	} else {
++		u32 value;
++
++		/*
++		* Slave dc0 and dc5 connected to master port 1.
++		* By default other slaves are connected to master port 0.
++		*/
++		value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
++			VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
++		writel_relaxed(value,
++			       priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
++
++		/* Slave dc0 connected to master port 1 */
++		value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
++		writel_relaxed(value,
++			       priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
++
++		/* Slave dc4 and dc7 connected to master port 1 */
++		value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
++			VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
++		writel_relaxed(value,
++			       priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
++
++		/* Slave dc1 connected to master port 1 */
++		value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
++		writel_relaxed(value,
++			       priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
++	}
+ }
+ 
+ static void meson_fbdev_setup(struct meson_drm *priv)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0052-drm-meson-Describe-the-HDMI-PHY-frequency-limits-of-.patch b/patch/kernel/archive/meson-6.10/0052-drm-meson-Describe-the-HDMI-PHY-frequency-limits-of-.patch
new file mode 100644
index 000000000000..831dc9e93104
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0052-drm-meson-Describe-the-HDMI-PHY-frequency-limits-of-.patch
@@ -0,0 +1,56 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 23 Dec 2020 21:18:35 +0100
+Subject: drm/meson: Describe the HDMI PHY frequency limits of Meson8/8b/8m2
+
+The maximum HDMI PLL frequency used by the vendor kernel is 2.976GHz.
+For Meson8 and Meson8b (both "HDMI 1.4 4k" capable) the maximum HDMI PHY
+frequency therefore is 2.976GHz. This makes sure we don't expose any
+HDMI 2.0 modes.
+Meson8b only supports up to 1080p according to it's datasheet. Limit the
+Meson8b SoC's to 1.65GHz (similar to what's already there for GXL S805X
+and S805Y).
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_drv.c | 18 +++++++++-
+ 1 file changed, 17 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_drv.c
++++ b/drivers/gpu/drm/meson/meson_drv.c
+@@ -200,13 +200,29 @@ struct meson_drm_soc_attr {
+ };
+ 
+ static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = {
+-	/* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */
++	/* The maximum frequency of HDMI PHY on Meson8 and Meson8m2 is ~3GHz */
++	{
++		.limits = {
++			.max_hdmi_phy_freq = 2976000,
++		},
++		.attrs = (const struct soc_device_attribute []) {
++			{ .soc_id = "Meson8 (S802)", },
++			{ .soc_id = "Meson8m2 (S812)", },
++			{ /* sentinel */ },
++		}
++	},
++	/*
++	 * GXL S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz.
++	 * Meson8b (S805) only supports "1200p@60 max resolution" according to
++	 * the public datasheet.
++	 */
+ 	{
+ 		.limits = {
+ 			.max_hdmi_phy_freq = 1650000,
+ 		},
+ 		.attrs = (const struct soc_device_attribute []) {
+ 			{ .soc_id = "GXL (S805*)", },
++			{ .soc_id = "Meson8b (S805)", },
+ 			{ /* sentinel */ }
+ 		}
+ 	},
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0053-drm-meson-Update-the-HDMI-encoder-for-Meson8-8b-8m2.patch b/patch/kernel/archive/meson-6.10/0053-drm-meson-Update-the-HDMI-encoder-for-Meson8-8b-8m2.patch
new file mode 100644
index 000000000000..bb2c0c6e4eba
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0053-drm-meson-Update-the-HDMI-encoder-for-Meson8-8b-8m2.patch
@@ -0,0 +1,144 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 6 Oct 2021 23:34:04 +0200
+Subject: drm/meson: Update the HDMI encoder for Meson8/8b/8m2
+
+Meson8/8b/8m2 uses VPU_HDMI_OUTPUT_YCBCR for YUV444 while newer SoCs use
+VPU_HDMI_OUTPUT_CBYCR. Also the 32-bit SoCs use VPU_HDMI_OUTPUT_CRYCB
+for RGB. These are the only two known mappings for the 32-bit SoCs.
+
+The VPU_HDMI_FMT_CTRL register with it's YUV444 to YUV422/YUV420
+converter is not present on these older SoCs. Avoid writing this
+reserved register on these 32-bit SoCs.
+
+MEDIA_BUS_FMT_RGB888_1X24 cannot be exposed as output format because the
+RGB to YUV converter is always enabled in meson_plane_atomic_update()
+(so there's currently no way to configure it).
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_encoder_hdmi.c | 66 +++++++---
+ 1 file changed, 49 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c
++++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
+@@ -190,13 +190,13 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge,
+ {
+ 	struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge);
+ 	struct drm_atomic_state *state = bridge_state->base.state;
+-	unsigned int ycrcb_map = VPU_HDMI_OUTPUT_CBYCR;
+ 	struct meson_drm *priv = encoder_hdmi->priv;
+ 	struct drm_connector_state *conn_state;
+ 	const struct drm_display_mode *mode;
+ 	struct drm_crtc_state *crtc_state;
+ 	struct drm_connector *connector;
+ 	bool yuv420_mode = false;
++	unsigned int ycrcb_map;
+ 	int vic;
+ 
+ 	connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
+@@ -217,11 +217,21 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge,
+ 
+ 	dev_dbg(priv->dev, "\"%s\" vic %d\n", mode->name, vic);
+ 
+-	if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) {
++	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) {
++		if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_RGB888_1X24)
++			ycrcb_map = VPU_HDMI_OUTPUT_YCBCR;
++		else
++			ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
++	} else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) {
+ 		ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
+ 		yuv420_mode = true;
+-	} else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
++	} else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16) {
+ 		ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
++	} else {
++		ycrcb_map = VPU_HDMI_OUTPUT_CBYCR;
++	}
+ 
+ 	/* VENC + VENC-DVI Mode setup */
+ 	meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode);
+@@ -229,17 +239,21 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge,
+ 	/* VCLK Set clock */
+ 	meson_encoder_hdmi_set_vclk(encoder_hdmi, mode);
+ 
+-	if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24)
+-		/* Setup YUV420 to HDMI-TX, no 10bit diphering */
+-		writel_relaxed(2 | (2 << 2),
+-			       priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
+-	else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
+-		/* Setup YUV422 to HDMI-TX, no 10bit diphering */
+-		writel_relaxed(1 | (2 << 2),
+-				priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
+-	else
+-		/* Setup YUV444 to HDMI-TX, no 10bit diphering */
+-		writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
++	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) &&
++	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) &&
++	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) {
++		if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24)
++			/* Setup YUV420 to HDMI-TX, no 10bit diphering */
++			writel_relaxed(2 | (2 << 2),
++				       priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
++		else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
++			/* Setup YUV422 to HDMI-TX, no 10bit diphering */
++			writel_relaxed(1 | (2 << 2),
++				       priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
++		else
++			/* Setup YUV444 to HDMI-TX, no 10bit diphering */
++			writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
++	}
+ 
+ 	dev_dbg(priv->dev, "%s\n", priv->venc.hdmi_use_enci ? "VENCI" : "VENCP");
+ 
+@@ -262,7 +276,11 @@ static void meson_encoder_hdmi_atomic_disable(struct drm_bridge *bridge,
+ 	writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
+ }
+ 
+-static const u32 meson_encoder_hdmi_out_bus_fmts[] = {
++static const u32 meson8_encoder_hdmi_out_bus_fmts[] = {
++	MEDIA_BUS_FMT_YUV8_1X24,
++};
++
++static const u32 meson_gx_encoder_hdmi_out_bus_fmts[] = {
+ 	MEDIA_BUS_FMT_YUV8_1X24,
+ 	MEDIA_BUS_FMT_UYVY8_1X16,
+ 	MEDIA_BUS_FMT_UYYVYY8_0_5X24,
+@@ -276,13 +294,27 @@ meson_encoder_hdmi_get_inp_bus_fmts(struct drm_bridge *bridge,
+ 					u32 output_fmt,
+ 					unsigned int *num_input_fmts)
+ {
++	struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge);
++	struct meson_drm *priv = encoder_hdmi->priv;
++	unsigned int num_out_bus_fmts;
++	const u32 *out_bus_fmts;
+ 	u32 *input_fmts = NULL;
+ 	int i;
+ 
++	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) {
++		num_out_bus_fmts = ARRAY_SIZE(meson8_encoder_hdmi_out_bus_fmts);
++		out_bus_fmts = meson8_encoder_hdmi_out_bus_fmts;
++	} else {
++		num_out_bus_fmts = ARRAY_SIZE(meson_gx_encoder_hdmi_out_bus_fmts);
++		out_bus_fmts = meson_gx_encoder_hdmi_out_bus_fmts;
++	}
++
+ 	*num_input_fmts = 0;
+ 
+-	for (i = 0 ; i < ARRAY_SIZE(meson_encoder_hdmi_out_bus_fmts) ; ++i) {
+-		if (output_fmt == meson_encoder_hdmi_out_bus_fmts[i]) {
++	for (i = 0 ; i < num_out_bus_fmts ; ++i) {
++		if (output_fmt == out_bus_fmts[i]) {
+ 			*num_input_fmts = 1;
+ 			input_fmts = kcalloc(*num_input_fmts,
+ 					     sizeof(*input_fmts),
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0054-drm-meson-Only-set-ycbcr_420_allowed-on-64-bit-SoCs.patch b/patch/kernel/archive/meson-6.10/0054-drm-meson-Only-set-ycbcr_420_allowed-on-64-bit-SoCs.patch
new file mode 100644
index 000000000000..45b855a35195
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0054-drm-meson-Only-set-ycbcr_420_allowed-on-64-bit-SoCs.patch
@@ -0,0 +1,34 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 6 Oct 2021 23:37:44 +0200
+Subject: drm/meson: Only set ycbcr_420_allowed on 64-bit SoCs
+
+The 32-bit SoCs don't support YUV420 so we don't enable that
+functionality there.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_encoder_hdmi.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c
++++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
+@@ -481,8 +481,11 @@ int meson_encoder_hdmi_probe(struct meson_drm *priv)
+ 
+ 	drm_connector_attach_max_bpc_property(meson_encoder_hdmi->connector, 8, 8);
+ 
+-	/* Handle this here until handled by drm_bridge_connector_init() */
+-	meson_encoder_hdmi->connector->ycbcr_420_allowed = true;
++	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) &&
++	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) &&
++	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2))
++		/* Handle this here until handled by drm_bridge_connector_init() */
++		meson_encoder_hdmi->connector->ycbcr_420_allowed = true;
+ 
+ 	pdev = of_find_device_by_node(remote);
+ 	of_node_put(remote);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0055-drm-meson-Make-the-HHI-registers-optional-WIP.patch b/patch/kernel/archive/meson-6.10/0055-drm-meson-Make-the-HHI-registers-optional-WIP.patch
new file mode 100644
index 000000000000..c9b549bb4b9c
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0055-drm-meson-Make-the-HHI-registers-optional-WIP.patch
@@ -0,0 +1,100 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Thu, 7 Oct 2021 19:09:49 +0200
+Subject: drm/meson: Make the HHI registers optional - WIP
+
+The HHI area contains the clock controller registers as well as the
+registers for the CVBS DAC. Make the HHI registers optional because the
+functionality provided by them can be handled by separate drivers
+(especially on the 32-bit SoCs).
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_drv.c  | 35 +++++-----
+ drivers/gpu/drm/meson/meson_venc.c | 11 ++-
+ 2 files changed, 27 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_drv.c
++++ b/drivers/gpu/drm/meson/meson_drv.c
+@@ -271,24 +271,27 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
+ 
+ 	priv->io_base = regs;
+ 
++	/*
++	 * The HHI resource is optional because it contains the clocks and CVBS
++	 * encoder registers. These are managed by separate drivers though.
++	 */
+ 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
+-	if (!res) {
+-		ret = -EINVAL;
+-		goto free_drm;
+-	}
+-	/* Simply ioremap since it may be a shared register zone */
+-	regs = devm_ioremap(dev, res->start, resource_size(res));
+-	if (!regs) {
+-		ret = -EADDRNOTAVAIL;
+-		goto free_drm;
+-	}
++	if (res) {
++		/* Simply ioremap since it may be a shared register zone */
++		regs = devm_ioremap(dev, res->start, resource_size(res));
++		if (!regs) {
++			ret = -EADDRNOTAVAIL;
++			goto free_drm;
++		}
+ 
+-	priv->hhi = devm_regmap_init_mmio(dev, regs,
+-					  &meson_regmap_config);
+-	if (IS_ERR(priv->hhi)) {
+-		dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
+-		ret = PTR_ERR(priv->hhi);
+-		goto free_drm;
++		priv->hhi = devm_regmap_init_mmio(dev, regs,
++						  &meson_regmap_config);
++		if (IS_ERR(priv->hhi)) {
++			dev_err(&pdev->dev,
++				"Couldn't create the HHI regmap\n");
++			ret = PTR_ERR(priv->hhi);
++			goto video_clock_exit;
++		}
+ 	}
+ 
+ 	priv->canvas = meson_canvas_get(dev);
+diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_venc.c
++++ b/drivers/gpu/drm/meson/meson_venc.c
+@@ -1953,12 +1953,16 @@ void meson_venc_enable_vsync(struct meson_drm *priv)
+ 		writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
+ 			       priv->io_base + _REG(VENC_INTCTRL));
+ 	}
+-	regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
++
++	if (priv->hhi)
++		regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
+ }
+ 
+ void meson_venc_disable_vsync(struct meson_drm *priv)
+ {
+-	regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);
++	if (priv->hhi)
++		regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);
++
+ 	writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
+ }
+ 
+@@ -1968,7 +1972,8 @@ void meson_venc_init(struct meson_drm *priv)
+ 	writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
+ 
+ 	/* Disable HDMI PHY */
+-	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
++	if (priv->hhi)
++		regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
+ 
+ 	/* Disable HDMI */
+ 	writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI |
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0056-drm-meson-Add-support-for-the-Meson8-8b-8m2-TranSwit.patch b/patch/kernel/archive/meson-6.10/0056-drm-meson-Add-support-for-the-Meson8-8b-8m2-TranSwit.patch
new file mode 100644
index 000000000000..f9bbd04e9ff5
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0056-drm-meson-Add-support-for-the-Meson8-8b-8m2-TranSwit.patch
@@ -0,0 +1,2131 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 5 May 2019 02:29:42 +0200
+Subject: drm/meson: Add support for the Meson8/8b/8m2 TranSwitch HDMI
+ transmitter - WiP
+
+WiP
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/Kconfig                 |   10 +
+ drivers/gpu/drm/meson/Makefile                |    1 +
+ drivers/gpu/drm/meson/meson_transwitch_hdmi.c | 1537 ++++++++++
+ drivers/gpu/drm/meson/meson_transwitch_hdmi.h |  536 ++++
+ 4 files changed, 2084 insertions(+)
+
+diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/Kconfig
++++ b/drivers/gpu/drm/meson/Kconfig
+@@ -25,3 +25,13 @@ config DRM_MESON_DW_MIPI_DSI
+ 	default y if DRM_MESON
+ 	select DRM_DW_MIPI_DSI
+ 	select GENERIC_PHY_MIPI_DPHY
++
++config DRM_MESON_TRANSWITCH_HDMI
++	tristate "Amlogic Meson8/8b/8m2 TranSwitch HDMI 1.4 Controller support"
++	depends on ARM || COMPILE_TEST
++	depends on DRM_MESON
++	default y if DRM_MESON
++	select DRM_DISPLAY_HDMI_HELPER
++	select DRM_DISPLAY_HELPER
++	select REGMAP_MMIO
++	select SND_SOC_HDMI_CODEC if SND_SOC
+diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/Makefile
++++ b/drivers/gpu/drm/meson/Makefile
+@@ -7,3 +7,4 @@ meson-drm-y += meson_encoder_hdmi.o meson_encoder_dsi.o
+ obj-$(CONFIG_DRM_MESON) += meson-drm.o
+ obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
+ obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
++obj-$(CONFIG_DRM_MESON_TRANSWITCH_HDMI) += meson_transwitch_hdmi.o
+diff --git a/drivers/gpu/drm/meson/meson_transwitch_hdmi.c b/drivers/gpu/drm/meson/meson_transwitch_hdmi.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/gpu/drm/meson/meson_transwitch_hdmi.c
+@@ -0,0 +1,1537 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (C) 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++ *
++ * All registers and magic values are taken from Amlogic's GPL kernel sources:
++ *   Copyright (C) 2010 Amlogic, Inc.
++ */
++
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++
++#include <drm/display/drm_hdmi_helper.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_bridge.h>
++#include <drm/drm_connector.h>
++#include <drm/drm_device.h>
++#include <drm/drm_edid.h>
++#include <drm/drm_probe_helper.h>
++#include <drm/drm_print.h>
++
++#include <sound/hdmi-codec.h>
++
++#include <uapi/linux/media-bus-format.h>
++
++#include "meson_transwitch_hdmi.h"
++
++#define HDMI_ADDR_PORT					0x0
++#define HDMI_DATA_PORT					0x4
++#define HDMI_CTRL_PORT					0x8
++	#define HDMI_CTRL_PORT_APB3_ERR_EN		BIT(15)
++
++struct meson_txc_hdmi {
++	struct device			*dev;
++
++	struct regmap			*regmap;
++
++	struct clk			*pclk;
++	struct clk			*sys_clk;
++
++	struct phy			*phy;
++	bool				phy_is_on;
++
++	struct mutex			codec_mutex;
++	enum drm_connector_status	last_connector_status;
++	hdmi_codec_plugged_cb		codec_plugged_cb;
++	struct device			*codec_dev;
++
++	struct platform_device		*hdmi_codec_pdev;
++
++	struct drm_connector		*current_connector;
++
++	struct drm_bridge		bridge;
++	struct drm_bridge		*next_bridge;
++};
++
++#define bridge_to_meson_txc_hdmi(x) container_of(x, struct meson_txc_hdmi, bridge)
++
++static const struct regmap_range meson_txc_hdmi_regmap_ranges[] = {
++	regmap_reg_range(0x0000, 0x07ff),
++	regmap_reg_range(0x8000, 0x800c),
++};
++
++static const struct regmap_access_table meson_txc_hdmi_regmap_access = {
++	.yes_ranges = meson_txc_hdmi_regmap_ranges,
++	.n_yes_ranges = ARRAY_SIZE(meson_txc_hdmi_regmap_ranges),
++};
++
++static int meson_txc_hdmi_reg_read(void *context, unsigned int addr,
++				   unsigned int *data)
++{
++	void __iomem *base = context;
++
++	writel(addr, base + HDMI_ADDR_PORT);
++	writel(addr, base + HDMI_ADDR_PORT);
++
++	*data = readl(base + HDMI_DATA_PORT);
++
++	return 0;
++}
++
++static int meson_txc_hdmi_reg_write(void *context, unsigned int addr,
++				    unsigned int data)
++{
++	void __iomem *base = context;
++
++	writel(addr, base + HDMI_ADDR_PORT);
++	writel(addr, base + HDMI_ADDR_PORT);
++
++	writel(data, base + HDMI_DATA_PORT);
++
++	return 0;
++}
++
++static const struct regmap_config meson_txc_hdmi_regmap_config = {
++	.reg_bits = 16,
++	.val_bits = 16,
++	.reg_stride = 1,
++	.reg_read = meson_txc_hdmi_reg_read,
++	.reg_write = meson_txc_hdmi_reg_write,
++	.rd_table = &meson_txc_hdmi_regmap_access,
++	.wr_table = &meson_txc_hdmi_regmap_access,
++	.max_register = HDMI_OTHER_RX_PACKET_INTR_CLR,
++	.fast_io = true,
++};
++
++static void meson_txc_hdmi_write_infoframe(struct regmap *regmap,
++					   unsigned int tx_pkt_reg, u8 *buf,
++					   unsigned int len, bool enable)
++{
++	unsigned int i;
++
++	/* Write the data bytes by starting at register offset 1 */
++	for (i = HDMI_INFOFRAME_HEADER_SIZE; i < len; i++)
++		regmap_write(regmap,
++			     tx_pkt_reg + i - HDMI_INFOFRAME_HEADER_SIZE + 1,
++			     buf[i]);
++
++	/* Zero all remaining data bytes */
++	for (; i < 0x1c; i++)
++		regmap_write(regmap, tx_pkt_reg + i, 0x00);
++
++	/* Write the header (which we skipped above) */
++	regmap_write(regmap, tx_pkt_reg + 0x00, buf[3]);
++	regmap_write(regmap, tx_pkt_reg + 0x1c, buf[0]);
++	regmap_write(regmap, tx_pkt_reg + 0x1d, buf[1]);
++	regmap_write(regmap, tx_pkt_reg + 0x1e, buf[2]);
++
++	regmap_write(regmap, tx_pkt_reg + 0x1f, enable ? 0xff : 0x00);
++}
++
++static void meson_txc_hdmi_disable_infoframe(struct meson_txc_hdmi *priv,
++					     unsigned int tx_pkt_reg)
++{
++	u8 buf[HDMI_INFOFRAME_HEADER_SIZE] = { 0 };
++
++	meson_txc_hdmi_write_infoframe(priv->regmap, tx_pkt_reg, buf,
++				       HDMI_INFOFRAME_HEADER_SIZE, false);
++}
++
++static void meson_txc_hdmi_sys5_reset_assert(struct meson_txc_hdmi *priv)
++{
++	/* A comment in the vendor driver says: bit5,6 is converted */
++	regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2,
++		     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN |
++		     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN);
++	usleep_range(10, 20);
++
++	regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2,
++		     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN |
++		     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN);
++	usleep_range(10, 20);
++
++	regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1,
++		     TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN |
++		     TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN |
++		     TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN |
++		     TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN |
++		     TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN |
++		     TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 |
++		     TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 |
++		     TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0);
++	usleep_range(10, 20);
++}
++
++static void meson_txc_hdmi_sys5_reset_deassert(struct meson_txc_hdmi *priv)
++{
++	/* Release the resets except tmds_clk */
++	regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1,
++		     TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN);
++	usleep_range(10, 20);
++
++	/* Release the tmds_clk reset as well */
++	regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x0);
++	usleep_range(10, 20);
++
++	regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2,
++		     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN |
++		     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN |
++		     TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST);
++	usleep_range(10, 20);
++
++	regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2,
++		     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN |
++		     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN);
++	usleep_range(10, 20);
++}
++
++static void meson_txc_hdmi_config_hdcp_registers(struct meson_txc_hdmi *priv)
++{
++	regmap_write(priv->regmap, TX_HDCP_CONFIG0,
++		     FIELD_PREP(TX_HDCP_CONFIG0_ROM_ENCRYPT_OFF, 0x3));
++	regmap_write(priv->regmap, TX_HDCP_MEM_CONFIG, 0x0);
++	regmap_write(priv->regmap, TX_HDCP_ENCRYPT_BYTE, 0x0);
++
++	regmap_write(priv->regmap, TX_HDCP_MODE, TX_HDCP_MODE_CLEAR_AVMUTE);
++
++	regmap_write(priv->regmap, TX_HDCP_MODE, TX_HDCP_MODE_ESS_CONFIG);
++}
++
++static u8 meson_txc_hdmi_bus_fmt_to_color_depth(unsigned int bus_format)
++{
++	switch (bus_format) {
++	case MEDIA_BUS_FMT_RGB888_1X24:
++	case MEDIA_BUS_FMT_YUV8_1X24:
++	case MEDIA_BUS_FMT_UYVY8_1X16:
++		/* 8 bit */
++		return 0x0;
++
++	case MEDIA_BUS_FMT_RGB101010_1X30:
++	case MEDIA_BUS_FMT_YUV10_1X30:
++	case MEDIA_BUS_FMT_UYVY10_1X20:
++		/* 10 bit */
++		return 0x1;
++
++	case MEDIA_BUS_FMT_RGB121212_1X36:
++	case MEDIA_BUS_FMT_YUV12_1X36:
++	case MEDIA_BUS_FMT_UYVY12_1X24:
++		/* 12 bit */
++		return 0x2;
++
++	case MEDIA_BUS_FMT_RGB161616_1X48:
++	case MEDIA_BUS_FMT_YUV16_1X48:
++		/* 16 bit */
++		return 0x3;
++
++	default:
++		/* unknown, default to 8 bit */
++		return 0x0;
++	}
++}
++
++static u8 meson_txc_hdmi_bus_fmt_to_color_format(unsigned int bus_format)
++{
++	switch (bus_format) {
++	case MEDIA_BUS_FMT_YUV8_1X24:
++	case MEDIA_BUS_FMT_YUV10_1X30:
++	case MEDIA_BUS_FMT_YUV12_1X36:
++	case MEDIA_BUS_FMT_YUV16_1X48:
++		/* Documented as YCbCr444 */
++		return 0x1;
++
++	case MEDIA_BUS_FMT_UYVY8_1X16:
++	case MEDIA_BUS_FMT_UYVY10_1X20:
++	case MEDIA_BUS_FMT_UYVY12_1X24:
++		/* Documented as YCbCr422 */
++		return 0x3;
++
++	case MEDIA_BUS_FMT_RGB888_1X24:
++	case MEDIA_BUS_FMT_RGB101010_1X30:
++	case MEDIA_BUS_FMT_RGB121212_1X36:
++	case MEDIA_BUS_FMT_RGB161616_1X48:
++	default:
++		/* Documented as RGB444 */
++		return 0x0;
++	}
++}
++
++static void meson_txc_hdmi_config_color_space(struct meson_txc_hdmi *priv,
++					      unsigned int input_bus_format,
++					      unsigned int output_bus_format,
++					      enum hdmi_quantization_range quant_range,
++					      enum hdmi_colorimetry colorimetry)
++{
++	unsigned int regval;
++
++	regmap_write(priv->regmap, TX_VIDEO_DTV_MODE,
++		     FIELD_PREP(TX_VIDEO_DTV_MODE_COLOR_DEPTH,
++				meson_txc_hdmi_bus_fmt_to_color_depth(output_bus_format)));
++
++	regmap_write(priv->regmap, TX_VIDEO_DTV_OPTION_L,
++		     FIELD_PREP(TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_FORMAT,
++				meson_txc_hdmi_bus_fmt_to_color_format(output_bus_format)) |
++		     FIELD_PREP(TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_FORMAT,
++				meson_txc_hdmi_bus_fmt_to_color_format(input_bus_format)) |
++		     FIELD_PREP(TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_DEPTH,
++				meson_txc_hdmi_bus_fmt_to_color_depth(output_bus_format)) |
++		     FIELD_PREP(TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_DEPTH,
++				meson_txc_hdmi_bus_fmt_to_color_depth(input_bus_format)));
++
++	if (quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
++		regval = FIELD_PREP(TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE,
++				    TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235) |
++			 FIELD_PREP(TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE,
++				    TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235);
++	else
++		regval = FIELD_PREP(TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE,
++				    TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255) |
++			 FIELD_PREP(TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE,
++				    TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255);
++
++	regmap_write(priv->regmap, TX_VIDEO_DTV_OPTION_H, regval);
++
++	if (colorimetry == HDMI_COLORIMETRY_ITU_601) {
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B0, 0x2f);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B1, 0x1d);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R0, 0x8b);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R1, 0x4c);
++
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB0, 0x18);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB1, 0x58);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR0, 0xd0);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR1, 0xb6);
++	} else {
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B0, 0x7b);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B1, 0x12);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R0, 0x6c);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R1, 0x36);
++
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB0, 0xf2);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB1, 0x2f);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR0, 0xd4);
++		regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR1, 0x77);
++	}
++}
++
++static void meson_txc_hdmi_config_serializer_clock(struct meson_txc_hdmi *priv,
++						   enum hdmi_colorimetry colorimetry)
++{
++	/* Serializer Internal clock setting */
++	if (colorimetry == HDMI_COLORIMETRY_ITU_601)
++		regmap_write(priv->regmap, TX_SYS1_PLL, 0x24);
++	else
++		regmap_write(priv->regmap, TX_SYS1_PLL, 0x22);
++
++#if 0
++	// TODO: not ported yet
++	if ((param->VIC==HDMI_1080p60)&&(param->color_depth==COLOR_30BIT)&&(hdmi_rd_reg(0x018)==0x22)) {
++		regmap_write(priv->regmap, TX_SYS1_PLL, 0x12);
++	}
++#endif
++}
++
++static void meson_txc_hdmi_reconfig_packet_setting(struct meson_txc_hdmi *priv,
++						   u8 cea_mode)
++{
++	u8 alloc_active2, alloc_eof1, alloc_sof1, alloc_sof2;
++
++	regmap_write(priv->regmap, TX_PACKET_CONTROL_1,
++		     FIELD_PREP(TX_PACKET_CONTROL_1_PACKET_START_LATENCY, 58));
++	regmap_write(priv->regmap, TX_PACKET_CONTROL_2,
++		     TX_PACKET_CONTROL_2_HORIZONTAL_GC_PACKET_TRANSPORT_EN);
++
++	switch (cea_mode) {
++	case 31:
++		/* 1920x1080p50 */
++		alloc_active2 = 0x12;
++		alloc_eof1 = 0x10;
++		alloc_sof1 = 0xb6;
++		alloc_sof2 = 0x11;
++		break;
++	case 93:
++		/* 3840x2160p24 */
++		alloc_active2 = 0x12;
++		alloc_eof1 = 0x47;
++		alloc_sof1 = 0xf8;
++		alloc_sof2 = 0x52;
++		break;
++	case 94:
++		/* 3840x2160p25 */
++		alloc_active2 = 0x12;
++		alloc_eof1 = 0x44;
++		alloc_sof1 = 0xda;
++		alloc_sof2 = 0x52;
++		break;
++	case 95:
++		/* 3840x2160p30 */
++		alloc_active2 = 0x0f;
++		alloc_eof1 = 0x3a;
++		alloc_sof1 = 0x60;
++		alloc_sof2 = 0x52;
++		break;
++	case 98:
++		/* 4096x2160p24 */
++		alloc_active2 = 0x12;
++		alloc_eof1 = 0x47;
++		alloc_sof1 = 0xf8;
++		alloc_sof2 = 0x52;
++		break;
++	default:
++		/* Disable the special packet settings only */
++		regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_1, 0x00);
++		return;
++	}
++
++	/*
++	 * The vendor driver says: manually configure these register to get
++	 * stable video timings.
++	 */
++	regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_1, 0x01);
++	regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_2, alloc_active2);
++	regmap_write(priv->regmap, TX_PACKET_ALLOC_EOF_1, alloc_eof1);
++	regmap_write(priv->regmap, TX_PACKET_ALLOC_EOF_2, 0x12);
++	regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_0, 0x01);
++	regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_1, 0x00);
++	regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_2, 0x0a);
++	regmap_write(priv->regmap, TX_PACKET_ALLOC_SOF_1, alloc_sof1);
++	regmap_write(priv->regmap, TX_PACKET_ALLOC_SOF_2, alloc_sof2);
++	regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_1,
++			   TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING,
++			   TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING);
++}
++
++static void meson_txc_hdmi_set_avi_infoframe(struct meson_txc_hdmi *priv,
++					     struct drm_connector *conn,
++					     const struct drm_display_mode *mode,
++					     const struct drm_connector_state *conn_state,
++					     unsigned int output_bus_format,
++					     enum hdmi_quantization_range quant_range,
++					     enum hdmi_colorimetry colorimetry)
++{
++	u8 buf[HDMI_INFOFRAME_SIZE(AVI)], *video_code;
++	struct hdmi_avi_infoframe frame;
++	int ret;
++
++	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, conn, mode);
++	if (ret < 0) {
++		drm_err(priv->bridge.dev,
++			"Failed to setup AVI infoframe: %d\n", ret);
++		return;
++	}
++
++	switch (output_bus_format) {
++	case MEDIA_BUS_FMT_YUV8_1X24:
++	case MEDIA_BUS_FMT_YUV10_1X30:
++	case MEDIA_BUS_FMT_YUV12_1X36:
++	case MEDIA_BUS_FMT_YUV16_1X48:
++		frame.colorspace = HDMI_COLORSPACE_YUV444;
++		break;
++
++	case MEDIA_BUS_FMT_UYVY8_1X16:
++	case MEDIA_BUS_FMT_UYVY10_1X20:
++	case MEDIA_BUS_FMT_UYVY12_1X24:
++		frame.colorspace = HDMI_COLORSPACE_YUV422;
++		break;
++
++	case MEDIA_BUS_FMT_RGB888_1X24:
++	case MEDIA_BUS_FMT_RGB101010_1X30:
++	case MEDIA_BUS_FMT_RGB121212_1X36:
++	case MEDIA_BUS_FMT_RGB161616_1X48:
++	default:
++		frame.colorspace = HDMI_COLORSPACE_RGB;
++		break;
++	}
++
++	drm_hdmi_avi_infoframe_colorimetry(&frame, conn_state);
++	drm_hdmi_avi_infoframe_quant_range(&frame, conn, mode, quant_range);
++	drm_hdmi_avi_infoframe_bars(&frame, conn_state);
++
++	ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
++	if (ret < 0) {
++		drm_err(priv->bridge.dev,
++			"Failed to pack AVI infoframe: %d\n", ret);
++		return;
++	}
++
++	video_code = &buf[HDMI_INFOFRAME_HEADER_SIZE + 3];
++	if (*video_code > 108) {
++		regmap_write(priv->regmap, TX_PKT_REG_EXCEPT0_BASE_ADDR,
++			     *video_code);
++		*video_code = 0x00;
++	} else {
++		regmap_write(priv->regmap, TX_PKT_REG_EXCEPT0_BASE_ADDR,
++			     0x00);
++	}
++
++	meson_txc_hdmi_write_infoframe(priv->regmap,
++				       TX_PKT_REG_AVI_INFO_BASE_ADDR, buf,
++				       sizeof(buf), true);
++}
++
++static void meson_txc_hdmi_set_vendor_infoframe(struct meson_txc_hdmi *priv,
++						struct drm_connector *conn,
++						const struct drm_display_mode *mode)
++{
++	u8 buf[HDMI_INFOFRAME_HEADER_SIZE + 6];
++	struct hdmi_vendor_infoframe frame;
++	int ret;
++
++	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame, conn, mode);
++	if (ret) {
++		drm_dbg(priv->bridge.dev,
++			"Failed to setup vendor infoframe: %d\n", ret);
++		return;
++	}
++
++	ret = hdmi_vendor_infoframe_pack(&frame, buf, sizeof(buf));
++	if (ret < 0) {
++		drm_err(priv->bridge.dev,
++			"Failed to pack vendor infoframe: %d\n", ret);
++		return;
++	}
++
++	meson_txc_hdmi_write_infoframe(priv->regmap,
++				       TX_PKT_REG_VEND_INFO_BASE_ADDR, buf,
++				       sizeof(buf), true);
++}
++
++static void meson_txc_hdmi_set_spd_infoframe(struct meson_txc_hdmi *priv)
++{
++	u8 buf[HDMI_INFOFRAME_SIZE(SPD)];
++	struct hdmi_spd_infoframe frame;
++	int ret;
++
++	ret = hdmi_spd_infoframe_init(&frame, "Amlogic", "Meson TXC HDMI");
++	if (ret < 0) {
++		drm_err(priv->bridge.dev,
++			"Failed to setup SPD infoframe: %d\n", ret);
++		return;
++	}
++
++	ret = hdmi_spd_infoframe_pack(&frame, buf, sizeof(buf));
++	if (ret < 0) {
++		drm_err(priv->bridge.dev,
++			"Failed to pack SDP infoframe: %d\n", ret);
++		return;
++	}
++
++	meson_txc_hdmi_write_infoframe(priv->regmap,
++				       TX_PKT_REG_SPD_INFO_BASE_ADDR, buf,
++				       sizeof(buf), true);
++}
++
++static void meson_txc_hdmi_handle_plugged_change(struct meson_txc_hdmi *priv)
++{
++	bool plugged;
++
++	plugged = priv->last_connector_status == connector_status_connected;
++
++	if (priv->codec_dev && priv->codec_plugged_cb)
++		priv->codec_plugged_cb(priv->codec_dev, plugged);
++}
++
++static int meson_txc_hdmi_bridge_attach(struct drm_bridge *bridge,
++					enum drm_bridge_attach_flags flags)
++{
++	struct meson_txc_hdmi *priv = bridge->driver_private;
++
++	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
++		drm_err(bridge->dev,
++			"DRM_BRIDGE_ATTACH_NO_CONNECTOR flag is not set but needed\n");
++		return -EINVAL;
++	}
++
++	return drm_bridge_attach(bridge->encoder, priv->next_bridge, bridge,
++				 flags);
++}
++
++/* Can return a maximum of 11 possible output formats for a mode/connector */
++#define MAX_OUTPUT_SEL_FORMATS	11
++
++static u32 *
++meson_txc_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
++						 struct drm_bridge_state *bridge_state,
++						 struct drm_crtc_state *crtc_state,
++						 struct drm_connector_state *conn_state,
++						 unsigned int *num_output_fmts)
++{
++	struct drm_connector *conn = conn_state->connector;
++	struct drm_display_info *info = &conn->display_info;
++	u8 max_bpc = conn_state->max_requested_bpc;
++	unsigned int i = 0;
++	u32 *output_fmts;
++
++	*num_output_fmts = 0;
++
++	output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
++			      GFP_KERNEL);
++	if (!output_fmts)
++		return NULL;
++
++	/* If we are the only bridge, avoid negotiating with ourselves */
++	if (list_is_singular(&bridge->encoder->bridge_chain)) {
++		*num_output_fmts = 1;
++		output_fmts[0] = MEDIA_BUS_FMT_FIXED;
++
++		return output_fmts;
++	}
++
++	/*
++	 * Order bus formats from 16bit to 8bit and from YUV422 to RGB
++	 * if supported. In any case the default RGB888 format is added
++	 */
++
++	if (max_bpc >= 16 && info->bpc == 16) {
++		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
++			output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
++
++		output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
++	}
++
++	if (max_bpc >= 12 && info->bpc >= 12) {
++		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
++			output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
++
++		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
++			output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
++
++		output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
++	}
++
++	if (max_bpc >= 10 && info->bpc >= 10) {
++		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
++			output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
++
++		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
++			output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
++
++		output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
++	}
++
++	if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
++		output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
++
++	if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
++		output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
++
++	/* Default 8bit RGB fallback */
++	output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
++
++	*num_output_fmts = i;
++
++	return output_fmts;
++}
++
++/* Can return a maximum of 3 possible input formats for an output format */
++#define MAX_INPUT_SEL_FORMATS	3
++
++static u32 *
++meson_txc_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
++						struct drm_bridge_state *bridge_state,
++						struct drm_crtc_state *crtc_state,
++						struct drm_connector_state *conn_state,
++						u32 output_fmt,
++						unsigned int *num_input_fmts)
++{
++	u32 *input_fmts;
++	unsigned int i = 0;
++
++	*num_input_fmts = 0;
++
++	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
++			     GFP_KERNEL);
++	if (!input_fmts)
++		return NULL;
++
++	switch (output_fmt) {
++	/* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
++	case MEDIA_BUS_FMT_FIXED:
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
++		break;
++
++	/* 8bit */
++	case MEDIA_BUS_FMT_RGB888_1X24:
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
++		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
++		break;
++	case MEDIA_BUS_FMT_YUV8_1X24:
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
++		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
++		break;
++	case MEDIA_BUS_FMT_UYVY8_1X16:
++		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
++		break;
++
++	/* 10bit */
++	case MEDIA_BUS_FMT_RGB101010_1X30:
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
++		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
++		break;
++	case MEDIA_BUS_FMT_YUV10_1X30:
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
++		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
++		break;
++	case MEDIA_BUS_FMT_UYVY10_1X20:
++		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
++		break;
++
++	/* 12bit */
++	case MEDIA_BUS_FMT_RGB121212_1X36:
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
++		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
++		break;
++	case MEDIA_BUS_FMT_YUV12_1X36:
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
++		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
++		break;
++	case MEDIA_BUS_FMT_UYVY12_1X24:
++		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
++		break;
++
++	/* 16bit */
++	case MEDIA_BUS_FMT_RGB161616_1X48:
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
++		break;
++	case MEDIA_BUS_FMT_YUV16_1X48:
++		input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
++		input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
++		break;
++	}
++
++	*num_input_fmts = i;
++
++	if (*num_input_fmts == 0) {
++		kfree(input_fmts);
++		input_fmts = NULL;
++	}
++
++	return input_fmts;
++}
++
++static void meson_txc_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
++						struct drm_bridge_state *old_bridge_state)
++{
++	struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge);
++	struct drm_atomic_state *state = old_bridge_state->base.state;
++	enum hdmi_quantization_range quant_range;
++	struct drm_connector_state *conn_state;
++	struct drm_bridge_state *bridge_state;
++	const struct drm_display_mode *mode;
++	enum hdmi_colorimetry colorimetry;
++	struct drm_crtc_state *crtc_state;
++	struct drm_connector *connector;
++	unsigned int i;
++	u8 cea_mode;
++
++	bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
++
++	connector = drm_atomic_get_new_connector_for_encoder(state,
++							     bridge->encoder);
++	if (WARN_ON(!connector))
++		return;
++
++	conn_state = drm_atomic_get_new_connector_state(state, connector);
++	if (WARN_ON(!conn_state))
++		return;
++
++	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
++	if (WARN_ON(!crtc_state))
++		return;
++
++	priv->current_connector = connector;
++
++	mode = &crtc_state->adjusted_mode;
++
++	cea_mode = drm_match_cea_mode(mode);
++
++	if (connector->display_info.is_hdmi) {
++		quant_range = drm_default_rgb_quant_range(mode);
++
++		switch (cea_mode) {
++		case 2 ... 3:
++		case 6 ... 7:
++		case 17 ... 18:
++		case 21 ... 22:
++			colorimetry = HDMI_COLORIMETRY_ITU_601;
++			break;
++
++		default:
++			colorimetry = HDMI_COLORIMETRY_ITU_709;
++			break;
++		}
++
++		meson_txc_hdmi_set_avi_infoframe(priv, connector, mode,
++						 conn_state,
++						 bridge_state->output_bus_cfg.format,
++						 quant_range, colorimetry);
++		meson_txc_hdmi_set_vendor_infoframe(priv, connector, mode);
++		meson_txc_hdmi_set_spd_infoframe(priv);
++	} else {
++		quant_range = HDMI_QUANTIZATION_RANGE_FULL;
++		colorimetry = HDMI_COLORIMETRY_NONE;
++	}
++
++	meson_txc_hdmi_sys5_reset_assert(priv);
++
++	meson_txc_hdmi_config_hdcp_registers(priv);
++
++	if (cea_mode == 39)
++		regmap_write(priv->regmap, TX_VIDEO_DTV_TIMING, 0x0);
++	else
++		regmap_write(priv->regmap, TX_VIDEO_DTV_TIMING,
++			     TX_VIDEO_DTV_TIMING_DISABLE_VIC39_CORRECTION);
++
++	regmap_write(priv->regmap, TX_CORE_DATA_CAPTURE_2,
++		     TX_CORE_DATA_CAPTURE_2_INTERNAL_PACKET_ENABLE);
++	regmap_write(priv->regmap, TX_CORE_DATA_MONITOR_1,
++		     TX_CORE_DATA_MONITOR_1_LANE0 |
++		     FIELD_PREP(TX_CORE_DATA_MONITOR_1_SELECT_LANE0, 0x7));
++	regmap_write(priv->regmap, TX_CORE_DATA_MONITOR_2,
++		     FIELD_PREP(TX_CORE_DATA_MONITOR_2_MONITOR_SELECT, 0x2));
++
++	if (connector->display_info.is_hdmi)
++		regmap_write(priv->regmap, TX_TMDS_MODE,
++			     TX_TMDS_MODE_FORCED_HDMI |
++			     TX_TMDS_MODE_HDMI_CONFIG);
++	else
++		regmap_write(priv->regmap, TX_TMDS_MODE,
++			     TX_TMDS_MODE_FORCED_HDMI);
++
++	regmap_write(priv->regmap, TX_SYS4_CONNECT_SEL_1, 0x0);
++
++	/*
++	 * Set tmds_clk pattern to be "0000011111" before being sent to AFE
++	 * clock channel.
++	 */
++	regmap_write(priv->regmap, TX_SYS4_CK_INV_VIDEO,
++		     TX_SYS4_CK_INV_VIDEO_TMDS_CLK_PATTERN);
++
++	regmap_write(priv->regmap, TX_SYS5_FIFO_CONFIG,
++		     TX_SYS5_FIFO_CONFIG_CLK_CHANNEL3_OUTPUT_ENABLE |
++		     TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_ENABLE |
++		     TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_ENABLE |
++		     TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_ENABLE);
++
++	meson_txc_hdmi_config_color_space(priv,
++					  bridge_state->input_bus_cfg.format,
++					  bridge_state->output_bus_cfg.format,
++					  quant_range, colorimetry);
++
++	meson_txc_hdmi_sys5_reset_deassert(priv);
++
++	meson_txc_hdmi_config_serializer_clock(priv, colorimetry);
++	meson_txc_hdmi_reconfig_packet_setting(priv, cea_mode);
++
++	/* all resets need to be applied twice */
++	for (i = 0; i < 2; i++) {
++		regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1,
++			     TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN |
++			     TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN |
++			     TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN |
++			     TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN |
++			     TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN |
++			     TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 |
++			     TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 |
++			     TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0);
++		regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2,
++			     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN |
++			     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN |
++			     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN |
++			     TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN |
++			     TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST |
++			     TX_SYS5_TX_SOFT_RESET_2_TX_DDC_HDCP_RSTN |
++			     TX_SYS5_TX_SOFT_RESET_2_TX_DDC_EDID_RSTN |
++			     TX_SYS5_TX_SOFT_RESET_2_TX_DIG_RESET_N_CH3);
++		usleep_range(5000, 10000);
++		regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x00);
++		regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, 0x00);
++		usleep_range(5000, 10000);
++	}
++
++	if (!priv->phy_is_on) {
++		int ret;
++
++		ret = phy_power_on(priv->phy);
++		if (ret)
++			drm_err(bridge->dev, "Failed to turn on PHY\n");
++		else
++			priv->phy_is_on = true;
++	}
++}
++
++static void meson_txc_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
++						 struct drm_bridge_state *old_bridge_state)
++{
++	struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge);
++
++	priv->current_connector = NULL;
++
++	if (priv->phy_is_on) {
++		int ret;
++
++		ret = phy_power_off(priv->phy);
++		if (ret)
++			drm_err(bridge->dev, "Failed to turn off PHY\n");
++		else
++			priv->phy_is_on = false;
++	}
++
++	meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AUDIO_INFO_BASE_ADDR);
++	meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AVI_INFO_BASE_ADDR);
++	meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_EXCEPT0_BASE_ADDR);
++	meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_VEND_INFO_BASE_ADDR);
++}
++
++static enum drm_mode_status
++meson_txc_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
++				 const struct drm_display_info *info,
++				 const struct drm_display_mode *mode)
++{
++	return MODE_OK;
++}
++
++static enum drm_connector_status meson_txc_hdmi_bridge_detect(struct drm_bridge *bridge)
++{
++	struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge);
++	enum drm_connector_status status;
++	unsigned int val;
++
++	regmap_read(priv->regmap, TX_HDCP_ST_EDID_STATUS, &val);
++	if (val & TX_HDCP_ST_EDID_STATUS_HPD_STATUS)
++		status = connector_status_connected;
++	else
++		status = connector_status_disconnected;
++
++	mutex_lock(&priv->codec_mutex);
++	if (priv->last_connector_status != status) {
++		priv->last_connector_status = status;
++		meson_txc_hdmi_handle_plugged_change(priv);
++	}
++	mutex_unlock(&priv->codec_mutex);
++
++	return status;
++}
++
++static int meson_txc_hdmi_get_edid_block(void *data, u8 *buf, unsigned int block,
++					 size_t len)
++{
++	unsigned int i, regval, start = block * EDID_LENGTH;
++	struct meson_txc_hdmi *priv = data;
++	int ret;
++
++	/* Start the DDC transaction */
++	regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG,
++			   TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, 0);
++	regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG,
++			   TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG,
++			   TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG);
++
++	ret = regmap_read_poll_timeout(priv->regmap,
++				       TX_HDCP_ST_EDID_STATUS,
++				       regval,
++				       (regval & TX_HDCP_ST_EDID_STATUS_EDID_DATA_READY),
++				       1000, 200000);
++
++	regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG,
++			   TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, 0);
++
++	if (ret)
++		return ret;
++
++	for (i = 0; i < len; i++) {
++		regmap_read(priv->regmap, TX_RX_EDID_OFFSET + start + i,
++			    &regval);
++		buf[i] = regval;
++	}
++
++	return 0;
++}
++
++static const struct drm_edid *meson_txc_hdmi_bridge_edid_read(struct drm_bridge *bridge,
++							      struct drm_connector *connector)
++{
++	struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge);
++	const struct drm_edid *drm_edid;
++
++	drm_edid = drm_edid_read_custom(connector,
++					meson_txc_hdmi_get_edid_block, priv);
++	if (!drm_edid) {
++		drm_dbg(priv->bridge.dev, "Failed to get EDID\n");
++		return NULL;
++	}
++
++	return drm_edid;
++}
++
++static const struct drm_bridge_funcs meson_txc_hdmi_bridge_funcs = {
++	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
++	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
++	.atomic_reset = drm_atomic_helper_bridge_reset,
++	.attach = meson_txc_hdmi_bridge_attach,
++	.atomic_get_output_bus_fmts = meson_txc_hdmi_bridge_atomic_get_output_bus_fmts,
++	.atomic_get_input_bus_fmts = meson_txc_hdmi_bridge_atomic_get_input_bus_fmts,
++	.atomic_enable = meson_txc_hdmi_bridge_atomic_enable,
++	.atomic_disable = meson_txc_hdmi_bridge_atomic_disable,
++	.mode_valid = meson_txc_hdmi_bridge_mode_valid,
++	.detect = meson_txc_hdmi_bridge_detect,
++	.edid_read = meson_txc_hdmi_bridge_edid_read,
++};
++
++static int meson_txc_hdmi_hw_init(struct meson_txc_hdmi *priv)
++{
++	unsigned long ddc_i2c_bus_clk_hz = 500 * 1000;
++	unsigned long sys_clk_hz = 24 * 1000 * 1000;
++	int ret;
++
++	ret = phy_init(priv->phy);
++	if (ret) {
++		dev_err(priv->dev, "Failed to initialize the PHY: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_set_rate(priv->sys_clk, sys_clk_hz);
++	if (ret) {
++		dev_err(priv->dev, "Failed to set HDMI system clock to 24MHz\n");
++		goto err_phy_exit;
++	}
++
++	ret = clk_prepare_enable(priv->sys_clk);
++	if (ret) {
++		dev_err(priv->dev, "Failed to enable the sys clk\n");
++		goto err_phy_exit;
++	}
++
++	regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1,
++			   HDMI_OTHER_CTRL1_POWER_ON,
++			   HDMI_OTHER_CTRL1_POWER_ON);
++
++	regmap_write(priv->regmap, TX_HDMI_PHY_CONFIG0,
++		     TX_HDMI_PHY_CONFIG0_HDMI_COMMON_B7_B0);
++
++	regmap_write(priv->regmap, TX_HDCP_MODE, 0x40);
++
++	/*
++	 * The vendor driver comments that this is a setting for "Band-gap and
++	 * main-bias". 0x1d = power-up, 0x00 = power-down.
++	 */
++	regmap_write(priv->regmap, TX_SYS1_AFE_TEST, 0x1d);
++
++	meson_txc_hdmi_config_serializer_clock(priv, HDMI_COLORIMETRY_NONE);
++
++	/*
++	 * The vendor driver has a comment with the following information for
++	 * the magic value:
++	 * bit[2:0]=011: CK channel output TMDS CLOCK
++	 * bit[2:0]=101, ck channel output PHYCLCK
++	 */
++	regmap_write(priv->regmap, TX_SYS1_AFE_CONNECT, 0xfb);
++
++	/* Termination resistor calib value */
++	regmap_write(priv->regmap, TX_CORE_CALIB_VALUE, 0x0f);
++
++	/* HPD glitch filter */
++	regmap_write(priv->regmap, TX_HDCP_HPD_FILTER_L, 0xa0);
++	regmap_write(priv->regmap, TX_HDCP_HPD_FILTER_H, 0xa0);
++
++	/* Disable MEM power-down */
++	regmap_write(priv->regmap, TX_MEM_PD_REG0, 0x0);
++
++	regmap_write(priv->regmap, TX_HDCP_CONFIG3,
++		     FIELD_PREP(TX_HDCP_CONFIG3_DDC_I2C_BUS_CLOCK_TIME_DIVIDER,
++				(sys_clk_hz / ddc_i2c_bus_clk_hz) - 1));
++
++	/* Enable software controlled DDC transaction */
++	regmap_write(priv->regmap, TX_HDCP_EDID_CONFIG,
++		     TX_HDCP_EDID_CONFIG_FORCED_MEM_COPY_DONE |
++		     TX_HDCP_EDID_CONFIG_MEM_COPY_DONE_CONFIG);
++	regmap_write(priv->regmap, TX_CORE_EDID_CONFIG_MORE,
++		     TX_CORE_EDID_CONFIG_MORE_SYS_TRIGGER_CONFIG_SEMI_MANU);
++
++	/* mask (= disable) all interrupts */
++	regmap_write(priv->regmap, HDMI_OTHER_INTR_MASKN, 0x0);
++
++	/* clear any pending interrupt */
++	regmap_write(priv->regmap, HDMI_OTHER_INTR_STAT_CLR,
++		     HDMI_OTHER_INTR_STAT_CLR_EDID_RISING |
++		     HDMI_OTHER_INTR_STAT_CLR_HPD_FALLING |
++		     HDMI_OTHER_INTR_STAT_CLR_HPD_RISING);
++
++	return 0;
++
++err_phy_exit:
++	phy_exit(priv->phy);
++	return 0;
++}
++
++static void meson_txc_hdmi_hw_exit(struct meson_txc_hdmi *priv)
++{
++	int ret;
++
++	/* mask (= disable) all interrupts */
++	regmap_write(priv->regmap, HDMI_OTHER_INTR_MASKN,
++		     HDMI_OTHER_INTR_MASKN_TX_EDID_INT_RISE |
++		     HDMI_OTHER_INTR_MASKN_TX_HPD_INT_FALL |
++		     HDMI_OTHER_INTR_MASKN_TX_HPD_INT_RISE);
++
++	regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1,
++			   HDMI_OTHER_CTRL1_POWER_ON, 0);
++
++	clk_disable_unprepare(priv->sys_clk);
++
++	ret = phy_exit(priv->phy);
++	if (ret)
++		dev_err(priv->dev, "Failed to exit the PHY: %d\n", ret);
++}
++
++static u32 meson_txc_hdmi_hdmi_codec_calc_audio_n(struct hdmi_codec_params *hparms)
++{
++	u32 audio_n;
++
++	if ((hparms->sample_rate % 44100) == 0)
++		audio_n = (128 * hparms->sample_rate) / 900;
++	else
++		audio_n = (128 * hparms->sample_rate) / 1000;
++
++	if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_EAC3 ||
++	    hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_DTS_HD)
++		audio_n *= 4;
++
++	return audio_n;
++}
++
++static u8 meson_txc_hdmi_hdmi_codec_coding_type(struct hdmi_codec_params *hparms)
++{
++	switch (hparms->cea.coding_type) {
++	case HDMI_AUDIO_CODING_TYPE_MLP:
++		return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_HBR_AUDIO_PACKET;
++	case HDMI_AUDIO_CODING_TYPE_DSD:
++		return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_ONE_BIT_AUDIO;
++	case HDMI_AUDIO_CODING_TYPE_DST:
++		return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_DST_AUDIO_PACKET;
++	default:
++		return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_AUDIO_SAMPLE_PACKET;
++	}
++}
++
++static int meson_txc_hdmi_hdmi_codec_hw_params(struct device *dev, void *data,
++					       struct hdmi_codec_daifmt *fmt,
++					       struct hdmi_codec_params *hparms)
++{
++	struct meson_txc_hdmi *priv = dev_get_drvdata(dev);
++	u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)];
++	u16 audio_tx_format;
++	u32 audio_n;
++	int len, i;
++
++	if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_MLP) {
++		/*
++		 * TODO: fixed CTS is not supported yet, it needs special
++		 * TX_SYS1_ACR_N_* settings
++		 */
++		return -EINVAL;
++	}
++
++	switch (hparms->sample_width) {
++	case 16:
++		audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK,
++					     TX_AUDIO_FORMAT_BIT_WIDTH_16);
++		break;
++
++	case 20:
++		audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK,
++					     TX_AUDIO_FORMAT_BIT_WIDTH_20);
++		break;
++
++	case 24:
++		audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK,
++					     TX_AUDIO_FORMAT_BIT_WIDTH_24);
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	switch (fmt->fmt) {
++	case HDMI_I2S:
++		regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1,
++				   HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON,
++				   HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON);
++
++		audio_tx_format |= TX_AUDIO_FORMAT_SPDIF_OR_I2S |
++				   TX_AUDIO_FORMAT_I2S_ONE_BIT_OR_I2S |
++				   FIELD_PREP(TX_AUDIO_FORMAT_I2S_FORMAT, 0x2);
++
++		if (hparms->channels > 2)
++			audio_tx_format |= TX_AUDIO_FORMAT_I2S_2_OR_8_CH;
++
++		regmap_write(priv->regmap, TX_AUDIO_FORMAT, audio_tx_format);
++
++		regmap_write(priv->regmap, TX_AUDIO_I2S, TX_AUDIO_I2S_ENABLE);
++		regmap_write(priv->regmap, TX_AUDIO_SPDIF, 0x0);
++		break;
++
++	case HDMI_SPDIF:
++		regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1,
++				   HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, 0x0);
++
++		if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_STREAM)
++			audio_tx_format |= TX_AUDIO_FORMAT_SPDIF_CHANNEL_STATUS_FROM_DATA_OR_REG;
++
++		regmap_write(priv->regmap, TX_AUDIO_FORMAT, audio_tx_format);
++
++		regmap_write(priv->regmap, TX_AUDIO_I2S, 0x0);
++		regmap_write(priv->regmap, TX_AUDIO_SPDIF, TX_AUDIO_SPDIF_ENABLE);
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	if (hparms->channels > 2)
++		regmap_write(priv->regmap, TX_AUDIO_HEADER,
++			     TX_AUDIO_HEADER_AUDIO_SAMPLE_PACKET_HEADER_LAYOUT1);
++	else
++		regmap_write(priv->regmap, TX_AUDIO_HEADER, 0x0);
++
++	regmap_write(priv->regmap, TX_AUDIO_SAMPLE,
++		     FIELD_PREP(TX_AUDIO_SAMPLE_CHANNEL_VALID,
++				BIT(hparms->channels) - 1));
++
++	audio_n = meson_txc_hdmi_hdmi_codec_calc_audio_n(hparms);
++
++	regmap_write(priv->regmap, TX_SYS1_ACR_N_0,
++		     FIELD_PREP(TX_SYS1_ACR_N_0_N_BYTE0,
++				(audio_n >> 0) & 0xff));
++	regmap_write(priv->regmap, TX_SYS1_ACR_N_1,
++		     FIELD_PREP(TX_SYS1_ACR_N_1_N_BYTE1,
++				(audio_n >> 8) & 0xff));
++	regmap_update_bits(priv->regmap, TX_SYS1_ACR_N_2,
++			   TX_SYS1_ACR_N_2_N_UPPER_NIBBLE,
++			   FIELD_PREP(TX_SYS1_ACR_N_2_N_UPPER_NIBBLE,
++				      (audio_n >> 16) & 0xf));
++
++	regmap_write(priv->regmap, TX_SYS0_ACR_CTS_0, 0x0);
++	regmap_write(priv->regmap, TX_SYS0_ACR_CTS_1, 0x0);
++	regmap_write(priv->regmap, TX_SYS0_ACR_CTS_2,
++		     TX_SYS0_ACR_CTS_2_FORCE_ARC_STABLE);
++
++	regmap_write(priv->regmap, TX_AUDIO_CONTROL,
++		     TX_AUDIO_CONTROL_AUTO_AUDIO_FIFO_CLEAR |
++		     FIELD_PREP(TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_MASK,
++				meson_txc_hdmi_hdmi_codec_coding_type(hparms)) |
++		     TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_FLAT);
++
++	len = hdmi_audio_infoframe_pack(&hparms->cea, buf, sizeof(buf));
++	if (len < 0)
++		return len;
++
++	meson_txc_hdmi_write_infoframe(priv->regmap,
++				       TX_PKT_REG_AUDIO_INFO_BASE_ADDR,
++				       buf, len, true);
++
++	for (i = 0; i < ARRAY_SIZE(hparms->iec.status); i++) {
++		unsigned char sub1, sub2;
++
++		sub1 = sub2 = hparms->iec.status[i];
++
++		if (i == 2) {
++			sub1 |= FIELD_PREP(IEC958_AES2_CON_CHANNEL, 1);
++			sub2 |= FIELD_PREP(IEC958_AES2_CON_CHANNEL, 2);
++		}
++
++		regmap_write(priv->regmap, TX_IEC60958_SUB1_OFFSET + i, sub1);
++		regmap_write(priv->regmap, TX_IEC60958_SUB2_OFFSET + i, sub2);
++	}
++
++	return 0;
++}
++
++static int meson_txc_hdmi_hdmi_codec_audio_startup(struct device *dev,
++						   void *data)
++{
++	struct meson_txc_hdmi *priv = dev_get_drvdata(dev);
++
++	regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_2,
++			   TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE, 0x0);
++
++	/* reset audio master and sample */
++	regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1,
++		     TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN |
++		     TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN);
++	regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x0);
++
++	regmap_write(priv->regmap, TX_AUDIO_CONTROL_MORE,
++		     TX_AUDIO_CONTROL_MORE_ENABLE);
++
++	regmap_write(priv->regmap, TX_AUDIO_FIFO,
++		     FIELD_PREP(TX_AUDIO_FIFO_FIFO_DEPTH_MASK,
++				TX_AUDIO_FIFO_FIFO_DEPTH_512) |
++		     FIELD_PREP(TX_AUDIO_FIFO_CRITICAL_THRESHOLD_MASK,
++			        TX_AUDIO_FIFO_CRITICAL_THRESHOLD_DEPTH_DIV16) |
++		     FIELD_PREP(TX_AUDIO_FIFO_NORMAL_THRESHOLD_MASK,
++			        TX_AUDIO_FIFO_NORMAL_THRESHOLD_DEPTH_DIV8));
++
++	regmap_write(priv->regmap, TX_AUDIO_LIPSYNC, 0x0);
++
++	regmap_write(priv->regmap, TX_SYS1_ACR_N_2,
++		     FIELD_PREP(TX_SYS1_ACR_N_2_N_MEAS_TOLERANCE, 0x3));
++
++	return 0;
++}
++
++static void meson_txc_hdmi_hdmi_codec_audio_shutdown(struct device *dev,
++						     void *data)
++{
++	struct meson_txc_hdmi *priv = dev_get_drvdata(dev);
++
++	meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AUDIO_INFO_BASE_ADDR);
++
++	regmap_write(priv->regmap, TX_AUDIO_CONTROL_MORE, 0x0);
++	regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1,
++			   HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, 0x0);
++
++	regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_2,
++			   TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE,
++			   TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE);
++}
++
++static int meson_txc_hdmi_hdmi_codec_mute_stream(struct device *dev,
++						 void *data, bool enable,
++						 int direction)
++{
++	struct meson_txc_hdmi *priv = dev_get_drvdata(dev);
++
++	regmap_write(priv->regmap, TX_AUDIO_PACK,
++		     enable ? 0 : TX_AUDIO_PACK_AUDIO_SAMPLE_PACKETS_ENABLE);
++
++	return 0;
++}
++
++static int meson_txc_hdmi_hdmi_codec_get_eld(struct device *dev, void *data,
++					     uint8_t *buf, size_t len)
++{
++	struct meson_txc_hdmi *priv = dev_get_drvdata(dev);
++
++	if (priv->current_connector)
++		memcpy(buf, priv->current_connector->eld,
++		       min_t(size_t, MAX_ELD_BYTES, len));
++	else
++		memset(buf, 0, len);
++
++	return 0;
++}
++
++static int meson_txc_hdmi_hdmi_codec_get_dai_id(struct snd_soc_component *component,
++						struct device_node *endpoint)
++{
++	struct of_endpoint of_ep;
++	int ret;
++
++	ret = of_graph_parse_endpoint(endpoint, &of_ep);
++	if (ret < 0)
++		return ret;
++
++	/*
++	 * HDMI sound should be located as reg = <2>
++	 * Then, it is sound port 0
++	 */
++	if (of_ep.port == 2)
++		return 0;
++
++	return -EINVAL;
++}
++
++static int meson_txc_hdmi_hdmi_codec_hook_plugged_cb(struct device *dev,
++						     void *data,
++						     hdmi_codec_plugged_cb fn,
++						     struct device *codec_dev)
++{
++	struct meson_txc_hdmi *priv = dev_get_drvdata(dev);
++
++	mutex_lock(&priv->codec_mutex);
++	priv->codec_plugged_cb = fn;
++	priv->codec_dev = codec_dev;
++	meson_txc_hdmi_handle_plugged_change(priv);
++	mutex_unlock(&priv->codec_mutex);
++
++	return 0;
++}
++
++static struct hdmi_codec_ops meson_txc_hdmi_hdmi_codec_ops = {
++	.hw_params		= meson_txc_hdmi_hdmi_codec_hw_params,
++	.audio_startup		= meson_txc_hdmi_hdmi_codec_audio_startup,
++	.audio_shutdown		= meson_txc_hdmi_hdmi_codec_audio_shutdown,
++	.mute_stream		= meson_txc_hdmi_hdmi_codec_mute_stream,
++	.get_eld		= meson_txc_hdmi_hdmi_codec_get_eld,
++	.get_dai_id		= meson_txc_hdmi_hdmi_codec_get_dai_id,
++	.hook_plugged_cb	= meson_txc_hdmi_hdmi_codec_hook_plugged_cb,
++};
++
++static const struct hdmi_codec_pdata meson_txc_hdmi_codec_pdata = {
++	.ops			= &meson_txc_hdmi_hdmi_codec_ops,
++	.i2s			= 1,
++	.spdif			= 1,
++	.max_i2s_channels	= 8,
++};
++
++static int meson_txc_hdmi_codec_init(struct meson_txc_hdmi *priv)
++{
++	priv->hdmi_codec_pdev = platform_device_register_data(priv->dev,
++							      HDMI_CODEC_DRV_NAME,
++							      PLATFORM_DEVID_AUTO,
++							      &meson_txc_hdmi_codec_pdata,
++							      sizeof(meson_txc_hdmi_codec_pdata));
++	return PTR_ERR_OR_ZERO(priv->hdmi_codec_pdev);
++}
++
++static int meson_txc_hdmi_probe(struct platform_device *pdev)
++{
++	struct device_node *endpoint, *remote;
++	struct device *dev = &pdev->dev;
++	struct meson_txc_hdmi *priv;
++	void __iomem *base;
++	u32 regval;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->dev = dev;
++
++	mutex_init(&priv->codec_mutex);
++
++	platform_set_drvdata(pdev, priv);
++
++	base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	priv->regmap = devm_regmap_init(dev, NULL, base,
++					&meson_txc_hdmi_regmap_config);
++	if (IS_ERR(priv->regmap))
++		return PTR_ERR(priv->regmap);
++
++	priv->pclk = devm_clk_get(dev, "pclk");
++	if (IS_ERR(priv->pclk))
++		return dev_err_probe(dev, PTR_ERR(priv->pclk),
++				     "Failed to get the pclk\n");
++
++	priv->sys_clk = devm_clk_get(dev, "sys");
++	if (IS_ERR(priv->sys_clk))
++		return dev_err_probe(dev, PTR_ERR(priv->sys_clk),
++				     "Failed to get the sys clock\n");
++
++	priv->phy = devm_phy_get(dev, "hdmi");
++	if (IS_ERR(priv->phy))
++		return dev_err_probe(dev, PTR_ERR(priv->phy),
++				     "Failed to get the HDMI PHY\n");
++
++	endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1);
++	if (!endpoint)
++		return dev_err_probe(dev, -ENODEV,
++				     "Missing endpoint in port@1\n");
++
++	remote = of_graph_get_remote_port_parent(endpoint);
++	of_node_put(endpoint);
++	if (!remote)
++		return dev_err_probe(dev, -ENODEV,
++				     "Endpoint in port@1 unconnected\n");
++
++	if (!of_device_is_available(remote)) {
++		of_node_put(remote);
++		return dev_err_probe(dev, -ENODEV,
++				     "port@1 remote device is disabled\n");
++	}
++
++	priv->next_bridge = of_drm_find_bridge(remote);
++	of_node_put(remote);
++	if (!priv->next_bridge)
++		return -EPROBE_DEFER;
++
++	ret = clk_prepare_enable(priv->pclk);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to enable the pclk\n");
++
++	regval = readl(base + HDMI_CTRL_PORT);
++	regval |= HDMI_CTRL_PORT_APB3_ERR_EN;
++	writel(regval, base + HDMI_CTRL_PORT);
++
++	ret = meson_txc_hdmi_hw_init(priv);
++	if (ret)
++		goto err_disable_clk;
++
++	ret = meson_txc_hdmi_codec_init(priv);
++	if (ret)
++		goto err_hw_exit;
++
++	priv->bridge.driver_private = priv;
++	priv->bridge.funcs = &meson_txc_hdmi_bridge_funcs;
++	priv->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
++	priv->bridge.of_node = dev->of_node;
++	priv->bridge.interlace_allowed = true;
++
++	drm_bridge_add(&priv->bridge);
++
++	return 0;
++
++err_hw_exit:
++	meson_txc_hdmi_hw_exit(priv);
++err_disable_clk:
++	clk_disable_unprepare(priv->pclk);
++	return ret;
++}
++
++static void meson_txc_hdmi_remove(struct platform_device *pdev)
++{
++	struct meson_txc_hdmi *priv = platform_get_drvdata(pdev);
++
++	platform_device_unregister(priv->hdmi_codec_pdev);
++
++	drm_bridge_remove(&priv->bridge);
++
++	meson_txc_hdmi_hw_exit(priv);
++
++	clk_disable_unprepare(priv->pclk);
++}
++
++static const struct of_device_id meson_txc_hdmi_of_table[] = {
++	{ .compatible = "amlogic,meson8-hdmi-tx" },
++	{ .compatible = "amlogic,meson8b-hdmi-tx" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, meson_txc_hdmi_of_table);
++
++static struct platform_driver meson_txc_hdmi_platform_driver = {
++	.probe		= meson_txc_hdmi_probe,
++	.remove_new	= meson_txc_hdmi_remove,
++	.driver		= {
++		.name		= "meson-transwitch-hdmi",
++		.of_match_table	= meson_txc_hdmi_of_table,
++	},
++};
++module_platform_driver(meson_txc_hdmi_platform_driver);
++
++MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
++MODULE_DESCRIPTION("Amlogic Meson8 and Meson8b TranSwitch HDMI 1.4 TX driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/gpu/drm/meson/meson_transwitch_hdmi.h b/drivers/gpu/drm/meson/meson_transwitch_hdmi.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/gpu/drm/meson/meson_transwitch_hdmi.h
+@@ -0,0 +1,536 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (C) 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++ *
++ * All registers and magic values are taken from Amlogic's GPL kernel sources:
++ *   Copyright (C) 2010 Amlogic, Inc.
++ */
++
++#include <linux/bitfield.h>
++#include <linux/bits.h>
++
++#ifndef __MESON_TRANSWITCH_HDMI_H__
++#define __MESON_TRANSWITCH_HDMI_H__
++
++/* HDMI TX register */
++
++// System config 0
++#define TX_SYS0_AFE_SIGNAL						0x0000
++#define TX_SYS0_AFE_LOOP						0x0001
++#define TX_SYS0_ACR_CTS_0						0x0002
++	#define TX_SYS0_ACR_CTS_0_AUDIO_CTS_BYTE0		GENMASK(7, 0)
++#define TX_SYS0_ACR_CTS_1						0x0003
++	#define TX_SYS0_ACR_CTS_1_AUDIO_CTS_BYTE1		GENMASK(7, 0)
++#define TX_SYS0_ACR_CTS_2						0x0004
++	#define TX_SYS0_ACR_CTS_2_FORCE_ARC_STABLE			BIT(5)
++#define TX_SYS0_BIST_CONTROL						0x0005
++	#define TX_SYS0_BIST_CONTROL_AFE_BIST_ENABLE			BIT(7)
++	#define TX_SYS0_BIST_CONTROL_TMDS_SHIFT_PATTERN_SELECT		BIT(6)
++	#define TX_SYS0_BIST_CONTROL_TMDS_PRBS_PATTERN_SELECT	GENMASK(5, 4)
++	#define TX_SYS0_BIST_CONTROL_TMDS_REPEAT_BIST_PATTERN	GENMASK(2, 0)
++
++#define TX_SYS0_BIST_DATA_0						0x0006
++#define TX_SYS0_BIST_DATA_1						0x0007
++#define TX_SYS0_BIST_DATA_2						0x0008
++#define TX_SYS0_BIST_DATA_3						0x0009
++#define TX_SYS0_BIST_DATA_4						0x000A
++#define TX_SYS0_BIST_DATA_5						0x000B
++#define TX_SYS0_BIST_DATA_6						0x000C
++#define TX_SYS0_BIST_DATA_7						0x000D
++#define TX_SYS0_BIST_DATA_8						0x000E
++#define TX_SYS0_BIST_DATA_9						0x000F
++
++// system config 1
++#define TX_HDMI_PHY_CONFIG0						0x0010
++	#define TX_HDMI_PHY_CONFIG0_HDMI_COMMON_B7_B0		GENMASK(7, 0)
++#define TX_HDMI_PHY_CONFIG1						0x0010
++	#define TX_HDMI_PHY_CONFIG1_HDMI_COMMON_B11_B8		GENMASK(3, 0)
++	#define TX_HDMI_PHY_CONFIG1_HDMI_CTL_REG_B3_B0		GENMASK(7, 4)
++#define TX_HDMI_PHY_CONFIG2						0x0012
++    #define TX_HDMI_PHY_CONFIG_HDMI_CTL_REG_B11_B4		GENMASK(7, 0)
++#define TX_HDMI_PHY_CONFIG3						0x0013
++	#define TX_HDMI_PHY_CONFIG3_HDMI_L2H_CTL		GENMASK(3, 0)
++	#define TX_HDMI_PHY_CONFIG3_HDMI_MDR_PU			GENMASK(7, 4)
++#define TX_HDMI_PHY_CONFIG4						0x0014
++	#define TX_HDMI_PHY_CONFIG4_HDMI_LF_PD				BIT(0)
++	#define TX_HDMI_PHY_CONFIG4_HDMI_PHY_CLK_EN			BIT(1)
++	#define TX_HDMI_PHY_CONFIG4_HDMI_MODE			GENMASK(3, 2)
++	#define TX_HDMI_PHY_CONFIG4_HDMI_MODE_NORMAL			0x0
++	#define TX_HDMI_PHY_CONFIG4_HDMI_MODE_CLK_CH3_EQUAL_CH0		0x1
++	#define TX_HDMI_PHY_CONFIG4_HDMI_MODE_ALTERNATE_HIGH_LOW	0x2
++	#define TX_HDMI_PHY_CONFIG4_HDMI_MODE_ALTERNATE_LOW_HIGH	0x3
++	#define TX_HDMI_PHY_CONFIG4_HDMI_PREM_CTL		GENMASK(7, 4)
++#define TX_HDMI_PHY_CONFIG5						0x0015
++	#define TX_HDMI_PHY_CONFIG5_HDMI_VCM_CTL		GENMASK(7, 5)
++	#define TX_HDMI_PHY_CONFIG5_HDMI_PREFCTL		GENMASK(2, 0)
++#define TX_HDMI_PHY_CONFIG6						0x0016
++	#define TX_HDMI_PHY_CONFIG6_HDMI_RTERM_CTL		GENMASK(3, 0)
++	#define TX_HDMI_PHY_CONFIG6_HDMI_SWING_CTL		GENMASK(7, 4)
++#define TX_SYS1_AFE_TEST						0x0017
++#define TX_SYS1_PLL							0x0018
++#define TX_SYS1_TUNE							0x0019
++#define TX_SYS1_AFE_CONNECT						0x001A
++
++#define TX_SYS1_ACR_N_0							0x001C
++	#define TX_SYS1_ACR_N_0_N_BYTE0				GENMASK(7, 0)
++#define TX_SYS1_ACR_N_1							0x001D
++	#define TX_SYS1_ACR_N_1_N_BYTE1				GENMASK(7, 0)
++#define TX_SYS1_ACR_N_2							0x001E
++	#define TX_SYS1_ACR_N_2_N_MEAS_TOLERANCE		GENMASK(7, 4)
++	#define TX_SYS1_ACR_N_2_N_UPPER_NIBBLE			GENMASK(3, 0)
++#define TX_SYS1_PRBS_DATA						0x001F
++	#define TX_SYS1_PRBS_DATA_PRBS_MODE			GENMASK(1, 0)
++	#define TX_SYS1_PRBS_DATA_PRBS_MODE_11				0x0
++	#define TX_SYS1_PRBS_DATA_PRBS_MODE_15				0x1
++	#define TX_SYS1_PRBS_DATA_PRBS_MODE_7				0x2
++	#define TX_SYS1_PRBS_DATA_PRBS_MODE_31				0x3
++
++// HDCP CONFIG
++#define TX_HDCP_ECC_CONFIG						0x0024
++#define TX_HDCP_CRC_CONFIG						0x0025
++#define TX_HDCP_EDID_CONFIG						0x0026
++	#define TX_HDCP_EDID_CONFIG_FORCED_SYS_TRIGGER			BIT(7)
++	#define TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG			BIT(6)
++	#define TX_HDCP_EDID_CONFIG_MEM_ACC_SEQ_MODE			BIT(5)
++	#define TX_HDCP_EDID_CONFIG_MEM_ACC_SEQ_START			BIT(4)
++	#define TX_HDCP_EDID_CONFIG_FORCED_MEM_COPY_DONE		BIT(3)
++	#define TX_HDCP_EDID_CONFIG_MEM_COPY_DONE_CONFIG		BIT(2)
++	#define TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG_SEMI_MANU	BIT(1)
++
++#define TX_HDCP_MEM_CONFIG						0x0027
++	#define TX_HDCP_MEM_CONFIG_READ_DECRYPT				BIT(3)
++
++#define TX_HDCP_HPD_FILTER_L						0x0028
++#define TX_HDCP_HPD_FILTER_H						0x0029
++#define TX_HDCP_ENCRYPT_BYTE						0x002A
++#define TX_HDCP_CONFIG0							0x002B
++	#define TX_HDCP_CONFIG0_ROM_ENCRYPT_OFF			GENMASK(4, 3)
++
++#define TX_HDCP_CONFIG1							0x002C
++#define TX_HDCP_CONFIG2							0x002D
++#define TX_HDCP_CONFIG3							0x002E
++	#define TX_HDCP_CONFIG3_DDC_I2C_BUS_CLOCK_TIME_DIVIDER	GENMASK(7, 0)
++
++#define TX_HDCP_MODE							0x002F
++	#define TX_HDCP_MODE_CP_DESIRED					BIT(7)
++	#define TX_HDCP_MODE_ESS_CONFIG					BIT(6)
++	#define TX_HDCP_MODE_SET_AVMUTE					BIT(5)
++	#define TX_HDCP_MODE_CLEAR_AVMUTE				BIT(4)
++	#define TX_HDCP_MODE_HDCP_1_1					BIT(3)
++	#define TX_HDCP_MODE_VSYNC_HSYNC_FORCED_POLARITY_SELECT		BIT(2)
++	#define TX_HDCP_MODE_FORCED_VSYNC_POLARITY			BIT(1)
++	#define TX_HDCP_MODE_FORCED_HSYNC_POLARITY			BIT(0)
++
++// Video config, part 1
++#define TX_VIDEO_ACTIVE_PIXELS_0					0x0030
++#define TX_VIDEO_ACTIVE_PIXELS_1					0x0031
++#define TX_VIDEO_FRONT_PIXELS						0x0032
++#define TX_VIDEO_HSYNC_PIXELS						0x0033
++#define TX_VIDEO_BACK_PIXELS						0x0034
++#define TX_VIDEO_ACTIVE_LINES_0						0x0035
++#define TX_VIDEO_ACTIVE_LINES_1						0x0036
++#define TX_VIDEO_EOF_LINES						0x0037
++#define TX_VIDEO_VSYNC_LINES						0x0038
++#define TX_VIDEO_SOF_LINES						0x0039
++#define TX_VIDEO_DTV_TIMING						0x003A
++	#define TX_VIDEO_DTV_TIMING_FORCE_DTV_TIMING_AUTO		BIT(7)
++	#define TX_VIDEO_DTV_TIMING_FORCE_VIDEO_SCAN			BIT(6)
++	#define TX_VIDEO_DTV_TIMING_FORCE_VIDEO_FIELD			BIT(5)
++	#define TX_VIDEO_DTV_TIMING_DISABLE_VIC39_CORRECTION		BIT(4)
++
++#define TX_VIDEO_DTV_MODE						0x003B
++	#define TX_VIDEO_DTV_MODE_FORCED_DEFAULT_PHASE			BIT(7)
++	#define TX_VIDEO_DTV_MODE_COLOR_DEPTH			GENMASK(1, 0)
++
++#define TX_VIDEO_DTV_FORMAT0						0x003C
++#define TX_VIDEO_DTV_FORMAT1						0x003D
++#define TX_VIDEO_PIXEL_PACK						0x003F
++// video config, part 2
++#define TX_VIDEO_CSC_COEFF_B0						0x0040
++#define TX_VIDEO_CSC_COEFF_B1						0x0041
++#define TX_VIDEO_CSC_COEFF_R0						0x0042
++#define TX_VIDEO_CSC_COEFF_R1						0x0043
++#define TX_VIDEO_CSC_COEFF_CB0						0x0044
++#define TX_VIDEO_CSC_COEFF_CB1						0x0045
++#define TX_VIDEO_CSC_COEFF_CR0						0x0046
++#define TX_VIDEO_CSC_COEFF_CR1						0x0047
++#define TX_VIDEO_DTV_OPTION_L						0x0048
++	#define TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_FORMAT	GENMASK(7, 6)
++	#define TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_FORMAT	GENMASK(5, 4)
++	#define TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_DEPTH	GENMASK(3, 2)
++	#define TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_DEPTH		GENMASK(1, 0)
++
++#define TX_VIDEO_DTV_OPTION_H						0x0049
++	#define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235		0x0
++	#define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_240		0x1
++	#define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_1_254			0x2
++	#define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255			0x3
++	#define TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE	GENMASK(3, 2)
++	#define TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE		GENMASK(1, 0)
++
++#define TX_VIDEO_DTV_FILTER						0x004A
++#define TX_VIDEO_DTV_DITHER						0x004B
++#define TX_VIDEO_DTV_DEDITHER						0x004C
++#define TX_VIDEO_PROC_CONFIG0						0x004E
++#define TX_VIDEO_PROC_CONFIG1						0x004F
++
++// Audio config
++#define TX_AUDIO_FORMAT							0x0058
++	#define TX_AUDIO_FORMAT_SPDIF_OR_I2S				BIT(7)
++	#define TX_AUDIO_FORMAT_I2S_2_OR_8_CH				BIT(6)
++	#define TX_AUDIO_FORMAT_I2S_FORMAT			GENMASK(5, 4)
++	#define TX_AUDIO_FORMAT_BIT_WIDTH_MASK			GENMASK(3, 2)
++	#define TX_AUDIO_FORMAT_BIT_WIDTH_16				0x1
++	#define TX_AUDIO_FORMAT_BIT_WIDTH_20				0x2
++	#define TX_AUDIO_FORMAT_BIT_WIDTH_24				0x3
++	#define TX_AUDIO_FORMAT_WS_POLARITY				BIT(1)
++	#define TX_AUDIO_FORMAT_I2S_ONE_BIT_OR_I2S			BIT(0)
++	#define TX_AUDIO_FORMAT_SPDIF_CHANNEL_STATUS_FROM_DATA_OR_REG	BIT(0)
++
++#define TX_AUDIO_SPDIF							0x0059
++	#define TX_AUDIO_SPDIF_ENABLE					BIT(0)
++#define TX_AUDIO_I2S							0x005A
++	#define TX_AUDIO_I2S_ENABLE					BIT(0)
++#define TX_AUDIO_FIFO							0x005B
++	#define TX_AUDIO_FIFO_FIFO_DEPTH_MASK			GENMASK(7, 4)
++	#define TX_AUDIO_FIFO_FIFO_DEPTH_512				0x4
++	#define TX_AUDIO_FIFO_CRITICAL_THRESHOLD_MASK		GENMASK(3, 2)
++	#define TX_AUDIO_FIFO_CRITICAL_THRESHOLD_DEPTH_DIV16		0x2
++	#define TX_AUDIO_FIFO_NORMAL_THRESHOLD_MASK		GENMASK(1, 0)
++	#define TX_AUDIO_FIFO_NORMAL_THRESHOLD_DEPTH_DIV8		0x1
++#define TX_AUDIO_LIPSYNC						0x005C
++	#define TX_AUDIO_LIPSYNC_NORMALIZED_LIPSYNC_PARAM	GENMASK(7, 0)
++#define TX_AUDIO_CONTROL						0x005D
++	#define TX_AUDIO_CONTROL_FORCED_AUDIO_FIFO_CLEAR		BIT(7)
++	#define TX_AUDIO_CONTROL_AUTO_AUDIO_FIFO_CLEAR			BIT(6)
++	#define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_MASK		GENMASK(5, 4)
++	#define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_AUDIO_SAMPLE_PACKET	0x0
++	#define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_ONE_BIT_AUDIO	0x1
++	#define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_HBR_AUDIO_PACKET	0x2
++	#define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_DST_AUDIO_PACKET	0x3
++	#define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_VALID		BIT(2)
++	#define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_USER		BIT(1)
++	#define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_FLAT		BIT(0)
++#define TX_AUDIO_HEADER							0x005E
++	#define TX_AUDIO_HEADER_AUDIO_SAMPLE_PACKET_HEADER_LAYOUT1	BIT(7)
++	#define TX_AUDIO_HEADER_SET_NORMAL_DOUBLE_IN_DST_PACKET_HEADER	BIT(6)
++#define TX_AUDIO_SAMPLE							0x005F
++	#define TX_AUDIO_SAMPLE_CHANNEL_VALID			GENMASK(7, 0)
++#define TX_AUDIO_VALID							0x0060
++#define TX_AUDIO_USER							0x0061
++#define TX_AUDIO_PACK							0x0062
++	#define TX_AUDIO_PACK_AUDIO_SAMPLE_PACKETS_ENABLE		BIT(0)
++#define TX_AUDIO_CONTROL_MORE						0x0064
++	#define TX_AUDIO_CONTROL_MORE_ENABLE				BIT(0)
++
++// tmds config
++#define TX_TMDS_MODE							0x0068
++	#define TX_TMDS_MODE_FORCED_HDMI				BIT(7)
++	#define TX_TMDS_MODE_HDMI_CONFIG				BIT(6)
++	#define TX_TMDS_MODE_BIT_SWAP					BIT(3)
++	#define TX_TMDS_MODE_CHANNEL_SWAP			GENMASK(2, 0)
++
++#define TX_TMDS_CONFIG0							0x006C
++#define TX_TMDS_CONFIG1							0x006D
++
++// packet config
++#define TX_PACKET_ALLOC_ACTIVE_1					0x0078
++#define TX_PACKET_ALLOC_ACTIVE_2					0x0079
++#define TX_PACKET_ALLOC_EOF_1						0x007A
++#define TX_PACKET_ALLOC_EOF_2						0x007B
++#define TX_PACKET_ALLOC_SOF_1						0x007C
++#define TX_PACKET_ALLOC_SOF_2						0x007D
++#define TX_PACKET_CONTROL_1						0x007E
++	#define TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING			BIT(7)
++	#define TX_PACKET_CONTROL_1_PACKET_ALLOC_MODE			BIT(6)
++	#define TX_PACKET_CONTROL_1_PACKET_START_LATENCY	GENMASK(5, 0)
++
++#define TX_PACKET_CONTROL_2						0x007F
++	#define TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE		BIT(3)
++	#define TX_PACKET_CONTROL_2_HORIZONTAL_GC_PACKET_TRANSPORT_EN	BIT(1)
++
++#define TX_CORE_EDID_CONFIG_MORE					0x0080
++	#define TX_CORE_EDID_CONFIG_MORE_KEEP_EDID_ERROR		BIT(1)
++	#define TX_CORE_EDID_CONFIG_MORE_SYS_TRIGGER_CONFIG_SEMI_MANU	BIT(0)
++
++#define TX_CORE_ALLOC_VSYNC_0						0x0081
++#define TX_CORE_ALLOC_VSYNC_1						0x0082
++#define TX_CORE_ALLOC_VSYNC_2						0x0083
++#define TX_MEM_PD_REG0							0x0084
++
++// core config
++#define TX_CORE_DATA_CAPTURE_1						0x00F0
++#define TX_CORE_DATA_CAPTURE_2						0x00F1
++	#define TX_CORE_DATA_CAPTURE_2_AUDIO_SOURCE_SELECT	GENMASK(7, 6)
++	#define TX_CORE_DATA_CAPTURE_2_EXTERNAL_PACKET_ENABLE		BIT(5)
++	#define TX_CORE_DATA_CAPTURE_2_INTERNAL_PACKET_ENABLE		BIT(4)
++	#define TX_CORE_DATA_CAPTURE_2_AFE_FIFO_SRC_LANE1	GENMASK(3, 2)
++	#define TX_CORE_DATA_CAPTURE_2_AFE_FIFO_SRC_LANE0	GENMASK(1, 0)
++
++#define TX_CORE_DATA_MONITOR_1						0x00F2
++	#define TX_CORE_DATA_MONITOR_1_LANE1				BIT(7)
++	#define TX_CORE_DATA_MONITOR_1_SELECT_LANE1		GENMASK(6, 4)
++	#define TX_CORE_DATA_MONITOR_1_LANE0				BIT(3)
++	#define TX_CORE_DATA_MONITOR_1_SELECT_LANE0		GENMASK(2, 0)
++
++#define TX_CORE_DATA_MONITOR_2						0x00F3
++	#define TX_CORE_DATA_MONITOR_2_MONITOR_SELECT		GENMASK(2, 0)
++
++#define TX_CORE_CALIB_MODE						0x00F4
++#define TX_CORE_CALIB_SAMPLE_DELAY					0x00F5
++#define TX_CORE_CALIB_VALUE_AUTO					0x00F6
++#define TX_CORE_CALIB_VALUE						0x00F7
++
++// system config 4
++#define TX_SYS4_TX_CKI_DDR						0x00A0
++#define TX_SYS4_TX_CKO_DDR						0x00A1
++#define TX_SYS4_RX_CKI_DDR						0x00A2
++#define TX_SYS4_RX_CKO_DDR						0x00A3
++#define TX_SYS4_CONNECT_SEL_0						0x00A4
++#define TX_SYS4_CONNECT_SEL_1						0x00A5
++	#define TX_SYS4_CONNECT_SEL_1_TX_CONNECT_SEL_UPPER_CHANNEL_DATA	BIT(6)
++
++#define TX_SYS4_CONNECT_SEL_2						0x00A6
++#define TX_SYS4_CONNECT_SEL_3						0x00A7
++#define TX_SYS4_CK_INV_VIDEO						0x00A8
++	#define TX_SYS4_CK_INV_VIDEO_TMDS_CLK_PATTERN			BIT(4)
++#define TX_SYS4_CK_INV_AUDIO						0x00A9
++#define TX_SYS4_CK_INV_AFE						0x00AA
++#define TX_SYS4_CK_INV_CH01						0x00AB
++#define TX_SYS4_CK_INV_CH2						0x00AC
++#define TX_SYS4_CK_CEC							0x00AD
++#define TX_SYS4_CK_SOURCE_1						0x00AE
++#define TX_SYS4_CK_SOURCE_2						0x00AF
++
++#define TX_IEC60958_SUB1_OFFSET						0x00B0
++#define TX_IEC60958_SUB2_OFFSET						0x00C8
++
++// system config 5
++#define TX_SYS5_TX_SOFT_RESET_1						0x00E0
++	#define TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN			BIT(7)
++	#define TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN			BIT(6)
++	#define TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN		BIT(5)
++	#define TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN		BIT(4)
++	#define TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN		BIT(3)
++	#define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2		BIT(2)
++	#define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1		BIT(1)
++	#define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0		BIT(0)
++
++#define TX_SYS5_TX_SOFT_RESET_2						0x00E1
++	#define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN			BIT(7)
++	#define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN			BIT(6)
++	#define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN			BIT(5)
++	#define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN			BIT(4)
++	#define TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST			BIT(3)
++	#define TX_SYS5_TX_SOFT_RESET_2_TX_DDC_HDCP_RSTN		BIT(2)
++	#define TX_SYS5_TX_SOFT_RESET_2_TX_DDC_EDID_RSTN		BIT(1)
++	#define TX_SYS5_TX_SOFT_RESET_2_TX_DIG_RESET_N_CH3		BIT(0)
++
++#define TX_SYS5_RX_SOFT_RESET_1						0x00E2
++#define TX_SYS5_RX_SOFT_RESET_2						0x00E3
++#define TX_SYS5_RX_SOFT_RESET_3						0x00E4
++#define TX_SYS5_SSTL_BIDIR_IN						0x00E5
++#define TX_SYS5_SSTL_IN							0x00E6
++#define TX_SYS5_SSTL_DIFF_IN						0x00E7
++#define TX_SYS5_FIFO_CONFIG						0x00E8
++	#define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_BYPASS		BIT(6)
++	#define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_BYPASS		BIT(5)
++	#define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_BYPASS		BIT(4)
++	#define TX_SYS5_FIFO_CONFIG_CLK_CHANNEL3_OUTPUT_ENABLE		BIT(3)
++	#define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_ENABLE		BIT(2)
++	#define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_ENABLE		BIT(1)
++	#define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_ENABLE		BIT(0)
++
++#define TX_SYS5_FIFO_SAMP01_CFG						0x00E9
++#define TX_SYS5_FIFO_SAMP23_CFG						0x00EA
++#define TX_SYS5_CONNECT_FIFO_CFG					0x00EB
++#define TX_SYS5_IO_CALIB_CONTROL					0x00EC
++#define TX_SYS5_SSTL_BIDIR_OUT						0x00ED
++#define TX_SYS5_SSTL_OUT						0x00EE
++#define TX_SYS5_SSTL_DIFF_OUT						0x00EF
++
++// HDCP shadow register
++#define TX_HDCP_SHW_BKSV_0						0x0100
++#define TX_HDCP_SHW_BKSV_1						0x0101
++#define TX_HDCP_SHW_BKSV_2						0x0102
++#define TX_HDCP_SHW_BKSV_3						0x0103
++#define TX_HDCP_SHW_BKSV_4						0x0104
++#define TX_HDCP_SHW_RI1_0						0x0108
++#define TX_HDCP_SHW_RI1_1						0x0109
++#define TX_HDCP_SHW_PJ1							0x010A
++#define TX_HDCP_SHW_AKSV_0						0x0110
++#define TX_HDCP_SHW_AKSV_1						0x0111
++#define TX_HDCP_SHW_AKSV_2						0x0112
++#define TX_HDCP_SHW_AKSV_3						0x0113
++#define TX_HDCP_SHW_AKSV_4						0x0114
++#define TX_HDCP_SHW_AINFO						0x0115
++#define TX_HDCP_SHW_AN_0						0x0118
++#define TX_HDCP_SHW_AN_1						0x0119
++#define TX_HDCP_SHW_AN_2						0x011A
++#define TX_HDCP_SHW_AN_3						0x011B
++#define TX_HDCP_SHW_AN_4						0x011C
++#define TX_HDCP_SHW_AN_5						0x011D
++#define TX_HDCP_SHW_AN_6						0x011E
++#define TX_HDCP_SHW_AN_7						0x011F
++#define TX_HDCP_SHW_V1_H0_0						0x0120
++#define TX_HDCP_SHW_V1_H0_1						0x0121
++#define TX_HDCP_SHW_V1_H0_2						0x0122
++#define TX_HDCP_SHW_V1_H0_3						0x0123
++#define TX_HDCP_SHW_V1_H1_0						0x0124
++#define TX_HDCP_SHW_V1_H1_1						0x0125
++#define TX_HDCP_SHW_V1_H1_2						0x0126
++#define TX_HDCP_SHW_V1_H1_3						0x0127
++#define TX_HDCP_SHW_V1_H2_0						0x0128
++#define TX_HDCP_SHW_V1_H2_1						0x0129
++#define TX_HDCP_SHW_V1_H2_2						0x012A
++#define TX_HDCP_SHW_V1_H2_3						0x012B
++#define TX_HDCP_SHW_V1_H3_0						0x012C
++#define TX_HDCP_SHW_V1_H3_1						0x012D
++#define TX_HDCP_SHW_V1_H3_2						0x012E
++#define TX_HDCP_SHW_V1_H3_3						0x012F
++#define TX_HDCP_SHW_V1_H4_0						0x0130
++#define TX_HDCP_SHW_V1_H4_1						0x0131
++#define TX_HDCP_SHW_V1_H4_2						0x0132
++#define TX_HDCP_SHW_V1_H4_3						0x0133
++#define TX_HDCP_SHW_BCAPS						0x0140
++#define TX_HDCP_SHW_BSTATUS_0						0x0141
++#define TX_HDCP_SHW_BSTATUS_1						0x0142
++#define TX_HDCP_SHW_KSV_FIFO						0x0143
++
++// system status 0
++#define TX_SYSST0_CONNECT_FIFO						0x0180
++#define TX_SYSST0_PLL_MONITOR						0x0181
++#define TX_SYSST0_AFE_FIFO						0x0182
++#define TX_SYSST0_ROM_STATUS						0x018F
++
++// hdcp status
++#define TX_HDCP_ST_AUTHENTICATION					0x0190
++#define TX_HDCP_ST_FRAME_COUNT						0x0191
++#define TX_HDCP_ST_STATUS_0						0x0192
++#define TX_HDCP_ST_STATUS_1						0x0193
++#define TX_HDCP_ST_STATUS_2						0x0194
++#define TX_HDCP_ST_STATUS_3						0x0195
++#define TX_HDCP_ST_EDID_STATUS						0x0196
++	#define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS		GENMASK(7, 6)
++	#define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_NO_SINK_ATTACHED	0x0
++	#define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_READING_EDID	0x1
++	#define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_DVI_MODE		0x2
++	#define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_HDMI_MODE		0x3
++	#define TX_HDCP_ST_EDID_STATUS_EDID_DATA_READY			BIT(4)
++	#define TX_HDCP_ST_EDID_STATUS_HPD_STATUS			BIT(1)
++
++#define TX_HDCP_ST_MEM_STATUS						0x0197
++#define TX_HDCP_ST_ST_MODE						0x019F
++
++// video status
++#define TX_VIDEO_ST_ACTIVE_PIXELS_1					0x01A0
++#define TX_VIDEO_ST_ACTIVE_PIXELS_2					0x01A1
++#define TX_VIDEO_ST_FRONT_PIXELS					0x01A2
++#define TX_VIDEO_ST_HSYNC_PIXELS					0x01A3
++#define TX_VIDEO_ST_BACK_PIXELS						0x01A4
++#define TX_VIDEO_ST_ACTIVE_LINES_1					0x01A5
++#define TX_VIDEO_ST_ACTIVE_LINES_2					0x01A6
++#define TX_VIDEO_ST_EOF_LINES						0x01A7
++#define TX_VIDEO_ST_VSYNC_LINES						0x01A8
++#define TX_VIDEO_ST_SOF_LINES						0x01A9
++#define TX_VIDEO_ST_DTV_TIMING						0x01AA
++#define TX_VIDEO_ST_DTV_MODE						0x01AB
++// audio status
++#define TX_VIDEO_ST_AUDIO_STATUS					0x01AC
++#define TX_AFE_STATUS_0							0x01AE
++#define TX_AFE_STATUS_1							0x01AF
++
++#define TX_IEC60958_ST_SUB1_OFFSET					0x01B0
++#define TX_IEC60958_ST_SUB2_OFFSET					0x01C8
++
++// system status 1
++#define TX_SYSST1_CALIB_BIT_RESULT_0					0x01E0
++#define TX_SYSST1_CALIB_BIT_RESULT_1					0x01E1
++//HDMI_STATUS_OUT[7:0]
++#define TX_HDMI_PHY_READBACK_0						0x01E2
++//HDMI_COMP_OUT[4]
++//HDMI_STATUS_OUT[11:8]
++#define TX_HDMI_PHY_READBACK_1						0x01E3
++#define TX_SYSST1_CALIB_BIT_RESULT_4					0x01E4
++#define TX_SYSST1_CALIB_BIT_RESULT_5					0x01E5
++#define TX_SYSST1_CALIB_BIT_RESULT_6					0x01E6
++#define TX_SYSST1_CALIB_BIT_RESULT_7					0x01E7
++#define TX_SYSST1_CALIB_BUS_RESULT_0					0x01E8
++#define TX_SYSST1_CALIB_BUS_RESULT_1					0x01E9
++#define TX_SYSST1_CALIB_BUS_RESULT_2					0x01EA
++#define TX_SYSST1_CALIB_BUS_RESULT_3					0x01EB
++#define TX_SYSST1_CALIB_BUS_RESULT_4					0x01EC
++#define TX_SYSST1_CALIB_BUS_RESULT_5					0x01ED
++#define TX_SYSST1_CALIB_BUS_RESULT_6					0x01EE
++#define TX_SYSST1_CALIB_BUS_RESULT_7					0x01EF
++
++// Packet status
++#define TX_PACKET_ST_REQUEST_STATUS_1					0x01F0
++#define TX_PACKET_ST_REQUEST_STATUS_2					0x01F1
++#define TX_PACKET_ST_REQUEST_MISSED_1					0x01F2
++#define TX_PACKET_ST_REQUEST_MISSED_2					0x01F3
++#define TX_PACKET_ST_ENCODE_STATUS_0					0x01F4
++#define TX_PACKET_ST_ENCODE_STATUS_1					0x01F5
++#define TX_PACKET_ST_ENCODE_STATUS_2					0x01F6
++#define TX_PACKET_ST_TIMER_STATUS					0x01F7
++
++// tmds status
++#define TX_TMDS_ST_CLOCK_METER_1					0x01F8
++#define TX_TMDS_ST_CLOCK_METER_2					0x01F9
++#define TX_TMDS_ST_CLOCK_METER_3					0x01FA
++#define TX_TMDS_ST_TMDS_STATUS_1					0x01FC
++#define TX_TMDS_ST_TMDS_STATUS_2					0x01FD
++#define TX_TMDS_ST_TMDS_STATUS_3					0x01FE
++#define TX_TMDS_ST_TMDS_STATUS_4					0x01FF
++
++// Packet register
++#define TX_PKT_REG_SPD_INFO_BASE_ADDR					0x0200
++#define TX_PKT_REG_VEND_INFO_BASE_ADDR					0x0220
++#define TX_PKT_REG_MPEG_INFO_BASE_ADDR					0x0240
++#define TX_PKT_REG_AVI_INFO_BASE_ADDR					0x0260
++#define TX_PKT_REG_AUDIO_INFO_BASE_ADDR					0x0280
++#define TX_PKT_REG_ACP_INFO_BASE_ADDR					0x02A0
++#define TX_PKT_REG_ISRC1_BASE_ADDR					0x02C0
++#define TX_PKT_REG_ISRC2_BASE_ADDR					0x02E0
++#define TX_PKT_REG_EXCEPT0_BASE_ADDR					0x0300
++#define TX_PKT_REG_EXCEPT1_BASE_ADDR					0x0320
++#define TX_PKT_REG_EXCEPT2_BASE_ADDR					0x0340
++#define TX_PKT_REG_EXCEPT3_BASE_ADDR					0x0360
++#define TX_PKT_REG_EXCEPT4_BASE_ADDR					0x0380
++#define TX_PKT_REG_GAMUT_P0_BASE_ADDR					0x03A0
++#define TX_PKT_REG_GAMUT_P1_1_BASE_ADDR					0x03C0
++#define TX_PKT_REG_GAMUT_P1_2_BASE_ADDR					0x03E0
++
++#define TX_RX_EDID_OFFSET						0x0600
++
++/* HDMI OTHER registers */
++
++#define HDMI_OTHER_CTRL0						0x8000
++#define HDMI_OTHER_CTRL1						0x8001
++	#define HDMI_OTHER_CTRL1_POWER_ON				BIT(15)
++	#define HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON			BIT(13)
++
++#define HDMI_OTHER_STATUS0						0x8002
++#define HDMI_OTHER_CTRL2						0x8003
++#define HDMI_OTHER_INTR_MASKN						0x8004
++	#define HDMI_OTHER_INTR_MASKN_TX_EDID_INT_RISE			BIT(2)
++	#define HDMI_OTHER_INTR_MASKN_TX_HPD_INT_FALL			BIT(1)
++	#define HDMI_OTHER_INTR_MASKN_TX_HPD_INT_RISE			BIT(0)
++
++#define HDMI_OTHER_INTR_STAT						0x8005
++	#define HDMI_OTHER_INTR_STAT_EDID_RISING			BIT(2)
++	#define HDMI_OTHER_INTR_STAT_HPD_FALLING			BIT(1)
++	#define HDMI_OTHER_INTR_STAT_HPD_RISING				BIT(0)
++
++#define HDMI_OTHER_INTR_STAT_CLR					0x8006
++	#define HDMI_OTHER_INTR_STAT_CLR_EDID_RISING			BIT(2)
++	#define HDMI_OTHER_INTR_STAT_CLR_HPD_FALLING			BIT(1)
++	#define HDMI_OTHER_INTR_STAT_CLR_HPD_RISING			BIT(0)
++
++#define HDMI_OTHER_AVI_INTR_MASKN0					0x8008
++#define HDMI_OTHER_AVI_INTR_MASKN1					0x8009
++#define HDMI_OTHER_RX_AINFO_INTR_MASKN0					0x800a
++#define HDMI_OTHER_RX_AINFO_INTR_MASKN1					0x800b
++#define HDMI_OTHER_RX_PACKET_INTR_CLR					0x800c
++
++#endif /* __MESON_TRANSWITCH_HDMI_H__ */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0057-drm-meson-Meson8-Meson8b-Meson8m2-VCLK-HACK.patch b/patch/kernel/archive/meson-6.10/0057-drm-meson-Meson8-Meson8b-Meson8m2-VCLK-HACK.patch
new file mode 100644
index 000000000000..54d3f132b155
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0057-drm-meson-Meson8-Meson8b-Meson8m2-VCLK-HACK.patch
@@ -0,0 +1,458 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Apr 2020 22:13:51 +0200
+Subject: drm/meson: Meson8/Meson8b/Meson8m2 VCLK - HACK
+
+WiP
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_drv.c  | 101 ++++++-
+ drivers/gpu/drm/meson/meson_drv.h  |  32 ++
+ drivers/gpu/drm/meson/meson_vclk.c | 146 ++++++++++
+ drivers/gpu/drm/meson/meson_venc.c |  24 +-
+ 4 files changed, 293 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_drv.c
++++ b/drivers/gpu/drm/meson/meson_drv.c
+@@ -170,6 +170,35 @@ static void meson_vpu_init(struct meson_drm *priv)
+ 	}
+ }
+ 
++static int meson_video_clock_init(struct meson_drm *priv)
++{
++	int ret;
++
++	ret = clk_bulk_prepare(VPU_VID_CLK_NUM, priv->vid_clks);
++	if (ret)
++		return dev_err_probe(priv->dev, ret,
++				     "Failed to prepare the video clocks\n");
++
++	ret = clk_bulk_prepare(priv->num_intr_clks, priv->intr_clks);
++	if (ret)
++		return dev_err_probe(priv->dev, ret,
++				     "Failed to prepare the interrupt clocks\n");
++
++	return 0;
++}
++
++static void meson_video_clock_exit(struct meson_drm *priv)
++{
++	if (priv->clk_dac_enabled)
++		clk_disable(priv->clk_dac);
++
++	if (priv->clk_venc_enabled)
++		clk_disable(priv->clk_venc);
++
++	clk_bulk_unprepare(priv->num_intr_clks, priv->intr_clks);
++	clk_bulk_unprepare(VPU_VID_CLK_NUM, priv->vid_clks);
++}
++
+ static void meson_fbdev_setup(struct meson_drm *priv)
+ {
+ 	unsigned int preferred_bpp;
+@@ -263,10 +292,59 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
+ 	priv->compat = match->compat;
+ 	priv->afbcd.ops = match->afbcd_ops;
+ 
++	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) {
++		priv->vid_pll_resets[VPU_RESET_VID_PLL_PRE].id = "vid_pll_pre";
++		priv->vid_pll_resets[VPU_RESET_VID_PLL_POST].id = "vid_pll_post";
++		priv->vid_pll_resets[VPU_RESET_VID_PLL_SOFT_PRE].id = "vid_pll_soft_pre";
++		priv->vid_pll_resets[VPU_RESET_VID_PLL_SOFT_POST].id = "vid_pll_soft_post";
++
++		ret = devm_reset_control_bulk_get_exclusive(dev,
++							    VPU_RESET_VID_PLL_NUM,
++							    priv->vid_pll_resets);
++		if (ret)
++			goto free_drm;
++
++		priv->intr_clks[0].id = "vpu_intr";
++		priv->intr_clks[1].id = "hdmi_intr_sync";
++		priv->intr_clks[2].id = "venci_int";
++		priv->num_intr_clks = 3;
++
++		ret = devm_clk_bulk_get(dev, priv->num_intr_clks,
++					priv->intr_clks);
++		if (ret)
++			goto free_drm;
++
++		priv->vid_clks[VPU_VID_CLK_TMDS].id = "tmds";
++		priv->vid_clks[VPU_VID_CLK_HDMI_TX_PIXEL].id = "hdmi_tx_pixel";
++		priv->vid_clks[VPU_VID_CLK_CTS_ENCP].id = "cts_encp";
++		priv->vid_clks[VPU_VID_CLK_CTS_ENCI].id = "cts_enci";
++		priv->vid_clks[VPU_VID_CLK_CTS_ENCT].id = "cts_enct";
++		priv->vid_clks[VPU_VID_CLK_CTS_ENCL].id = "cts_encl";
++		priv->vid_clks[VPU_VID_CLK_CTS_VDAC0].id = "cts_vdac0";
++
++		ret = devm_clk_bulk_get(dev, VPU_VID_CLK_NUM, priv->vid_clks);
++		if (ret)
++			goto free_drm;
++	} else {
++		priv->intr_clks[0].id = "vpu_intr";
++		priv->num_intr_clks = 1;
++
++		ret = devm_clk_bulk_get_optional(dev, priv->num_intr_clks,
++						 priv->intr_clks);
++		if (ret)
++			goto free_drm;
++	}
++
++	ret = meson_video_clock_init(priv);
++	if (ret)
++		goto free_drm;
++
+ 	regs = devm_platform_ioremap_resource_byname(pdev, "vpu");
+ 	if (IS_ERR(regs)) {
+ 		ret = PTR_ERR(regs);
+-		goto free_drm;
++		goto video_clock_exit;
+ 	}
+ 
+ 	priv->io_base = regs;
+@@ -281,7 +359,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
+ 		regs = devm_ioremap(dev, res->start, resource_size(res));
+ 		if (!regs) {
+ 			ret = -EADDRNOTAVAIL;
+-			goto free_drm;
++			goto video_clock_exit;
+ 		}
+ 
+ 		priv->hhi = devm_regmap_init_mmio(dev, regs,
+@@ -290,13 +368,13 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
+ 
+ 	priv->canvas = meson_canvas_get(dev);
+ 	if (IS_ERR(priv->canvas)) {
+ 		ret = PTR_ERR(priv->canvas);
+-		goto free_drm;
++		goto video_clock_exit;
+ 	}
+ 
+ 	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
+ 	if (ret)
+-		goto free_drm;
++		goto video_clock_exit;
+ 	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
+ 	if (ret)
+ 		goto free_canvas_osd1;
+@@ -425,6 +503,8 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
+ exit_afbcd:
+ 	if (priv->afbcd.ops)
+ 		priv->afbcd.ops->exit(priv);
++video_clock_exit:
++	meson_video_clock_exit(priv);
+ free_canvas_vd1_2:
+ 	meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
+ free_canvas_vd1_1:
+@@ -469,6 +549,8 @@ static void meson_drv_unbind(struct device *dev)
+ 
+ 	if (priv->afbcd.ops)
+ 		priv->afbcd.ops->exit(priv);
++
++	meson_video_clock_exit(priv);
+ }
+ 
+ static const struct component_master_ops meson_drv_master_ops = {
+@@ -483,6 +565,8 @@ static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
+ 	if (!priv)
+ 		return 0;
+ 
++	// TODO: video clock suspend
++
+ 	return drm_mode_config_helper_suspend(priv->drm);
+ }
+ 
+@@ -493,6 +577,7 @@ static int __maybe_unused meson_drv_pm_resume(struct device *dev)
+ 	if (!priv)
+ 		return 0;
+ 
++	meson_video_clock_init(priv);
+ 	meson_vpu_init(priv);
+ 	meson_venc_init(priv);
+ 	meson_vpp_init(priv);
+diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_drv.h
++++ b/drivers/gpu/drm/meson/meson_drv.h
+@@ -7,9 +7,11 @@
+ #ifndef __MESON_DRV_H
+ #define __MESON_DRV_H
+ 
++#include <linux/clk.h>
+ #include <linux/device.h>
+ #include <linux/of.h>
+ #include <linux/regmap.h>
++#include <linux/reset.h>
+ 
+ struct drm_crtc;
+ struct drm_device;
+@@ -45,6 +47,25 @@ struct meson_drm_soc_limits {
+ 	unsigned int max_hdmi_phy_freq;
+ };
+ 
++enum vpu_bulk_clk_id {
++	VPU_VID_CLK_TMDS = 0,
++	VPU_VID_CLK_HDMI_TX_PIXEL,
++	VPU_VID_CLK_CTS_ENCP,
++	VPU_VID_CLK_CTS_ENCI,
++	VPU_VID_CLK_CTS_ENCT,
++	VPU_VID_CLK_CTS_ENCL,
++	VPU_VID_CLK_CTS_VDAC0,
++	VPU_VID_CLK_NUM
++};
++
++enum vpu_bulk_vid_pll_reset_id {
++	VPU_RESET_VID_PLL_PRE = 0,
++	VPU_RESET_VID_PLL_POST,
++	VPU_RESET_VID_PLL_SOFT_PRE,
++	VPU_RESET_VID_PLL_SOFT_POST,
++	VPU_RESET_VID_PLL_NUM
++};
++
+ struct meson_drm {
+ 	struct device *dev;
+ 	enum vpu_compatible compat;
+@@ -70,6 +91,17 @@ struct meson_drm {
+ 	bool cvbs_dac_enabled;
+ 	struct platform_device *cvbs_dac_pdev;
+ 
++	struct clk_bulk_data intr_clks[3];
++	unsigned int num_intr_clks;
++	bool intr_clks_enabled;
++	struct clk_bulk_data vid_clks[VPU_VID_CLK_NUM];
++	bool vid_clk_rate_exclusive[VPU_VID_CLK_NUM];
++	struct clk *clk_venc;
++	bool clk_venc_enabled;
++	struct clk *clk_dac;
++	bool clk_dac_enabled;
++	struct reset_control_bulk_data vid_pll_resets[VPU_RESET_VID_PLL_NUM];
++
+ 	/* Components Data */
+ 	struct {
+ 		bool osd1_enabled;
+diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_vclk.c
++++ b/drivers/gpu/drm/meson/meson_vclk.c
+@@ -732,6 +732,11 @@ meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq)
+ 			return MODE_CLOCK_HIGH;
+ 	}
+ 
++	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2))
++		return MODE_OK;
++
+ 	if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
+ 		return MODE_OK;
+ 
+@@ -784,6 +789,11 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq,
+ 			return MODE_CLOCK_HIGH;
+ 	}
+ 
++	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2))
++		return MODE_OK;
++
+ 	for (i = 0 ; params[i].pixel_freq ; ++i) {
+ 		DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n",
+ 				 i, params[i].pixel_freq,
+@@ -1024,6 +1034,128 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
+ 	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
+ }
+ 
++static int meson_vclk_set_rate_exclusive(struct meson_drm *priv,
++					 enum vpu_bulk_clk_id clk_id,
++					 unsigned int rate_khz)
++{
++	struct clk *clk = priv->vid_clks[clk_id].clk;
++	int ret;
++
++	ret = clk_set_rate_exclusive(clk, rate_khz * 1000UL);
++	if (ret)
++		return ret;
++
++	priv->vid_clk_rate_exclusive[clk_id] = true;
++
++	return 0;
++}
++
++static void meson_vclk_disable_ccf(struct meson_drm *priv)
++{
++	unsigned int i;
++
++	/* allow all clocks to be changed in _enable again */
++	for (i = 0; i < VPU_VID_CLK_NUM; i++) {
++		if (!priv->vid_clk_rate_exclusive[i])
++			continue;
++
++		clk_rate_exclusive_put(priv->vid_clks[i].clk);
++		priv->vid_clk_rate_exclusive[i] = false;
++	}
++
++	if (priv->clk_dac_enabled) {
++		clk_disable(priv->clk_dac);
++		priv->clk_dac_enabled = false;
++	}
++
++	if (priv->clk_venc_enabled) {
++		clk_disable(priv->clk_venc);
++		priv->clk_venc_enabled = false;
++	}
++}
++
++static int meson_vclk_enable_ccf(struct meson_drm *priv, unsigned int target,
++				 bool hdmi_use_enci, unsigned int phy_freq,
++				 unsigned int dac_freq, unsigned int venc_freq)
++{
++	enum vpu_bulk_clk_id venc_clk_id, dac_clk_id;
++	int ret;
++
++	if (target == MESON_VCLK_TARGET_CVBS || hdmi_use_enci)
++		venc_clk_id = VPU_VID_CLK_CTS_ENCI;
++	else
++		venc_clk_id = VPU_VID_CLK_CTS_ENCP;
++
++	if (target == MESON_VCLK_TARGET_CVBS)
++		dac_clk_id = VPU_VID_CLK_CTS_VDAC0;
++	else
++		dac_clk_id = VPU_VID_CLK_HDMI_TX_PIXEL;
++
++	/*
++	 * The TMDS clock also updates the PLL. Protect the PLL rate so all
++	 * following clocks are derived from the PLL setting which matches the
++	 * TMDS clock.
++	 */
++	ret = meson_vclk_set_rate_exclusive(priv, VPU_VID_CLK_TMDS, phy_freq);
++	if (ret) {
++		dev_err(priv->dev, "Failed to set TMDS clock to %ukHz: %d\n",
++			phy_freq, ret);
++		goto out_enable_clocks;
++	}
++
++	/*
++	 * The DAC clock may be derived from a parent of the VENC clock so we
++	 * must protect the VENC clock from changing it's rate. This works
++	 * because the DAC freq can be divided by the VENC clock.
++	 */
++	ret = meson_vclk_set_rate_exclusive(priv, venc_clk_id, venc_freq);
++	if (ret) {
++		dev_warn(priv->dev,
++			 "Failed to set VENC clock to %ukHz while TMDS clock is %ukHz: %d\n",
++			 venc_freq, phy_freq, ret);
++		goto out_enable_clocks;
++	}
++
++	priv->clk_venc = priv->vid_clks[venc_clk_id].clk;
++
++	/*
++	 * after changing any of the VID_PLL_* clocks (which can happen when
++	 * update the VENC clock rate) we need to assert and then de-assert the
++	 * VID_DIVIDER_CNTL_* reset lines.
++	 */
++	reset_control_bulk_assert(VPU_RESET_VID_PLL_NUM, priv->vid_pll_resets);
++	reset_control_bulk_deassert(VPU_RESET_VID_PLL_NUM, priv->vid_pll_resets);
++
++	ret = meson_vclk_set_rate_exclusive(priv, dac_clk_id, dac_freq);
++	if (ret) {
++		dev_warn(priv->dev,
++			 "Failed to set pixel clock to %ukHz while TMDS clock is %ukHz: %d\n",
++			 dac_freq, phy_freq, ret);
++		goto out_enable_clocks;
++	}
++
++	priv->clk_dac = priv->vid_clks[dac_clk_id].clk;
++
++out_enable_clocks:
++	ret = clk_enable(priv->clk_venc);
++	if (ret)
++		dev_err(priv->dev,
++			"Failed to re-enable the VENC clock at %ukHz: %d\n",
++			venc_freq, ret);
++	else
++		priv->clk_venc_enabled = true;
++
++	ret = clk_enable(priv->clk_dac);
++	if (ret)
++		dev_err(priv->dev,
++			"Failed to re-enable the pixel clock at %ukHz: %d\n",
++			dac_freq, ret);
++	else
++		priv->clk_dac_enabled = true;
++
++	return ret;
++}
++
+ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
+ 		      unsigned int phy_freq, unsigned int vclk_freq,
+ 		      unsigned int venc_freq, unsigned int dac_freq,
+@@ -1034,6 +1166,20 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
+ 	unsigned int hdmi_tx_div;
+ 	unsigned int venc_div;
+ 
++	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
++	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) {
++		/* CVBS video clocks are generated off a 1296MHz base clock */
++		if (target == MESON_VCLK_TARGET_CVBS)
++			phy_freq = 1296000;
++
++		dev_err(priv->dev, "%s(target: %u, phy: %u, dac: %u, venc: %u, hdmi_use_enci: %u)\n", __func__, target, phy_freq, dac_freq, venc_freq, hdmi_use_enci);
++		meson_vclk_disable_ccf(priv);
++		meson_vclk_enable_ccf(priv, target, hdmi_use_enci, phy_freq,
++				      dac_freq, venc_freq);
++		return;
++	}
++
+ 	if (target == MESON_VCLK_TARGET_CVBS) {
+ 		meson_venci_cvbs_clock_config(priv);
+ 		return;
+diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_venc.c
++++ b/drivers/gpu/drm/meson/meson_venc.c
+@@ -1954,14 +1954,34 @@ void meson_venc_enable_vsync(struct meson_drm *priv)
+ 			       priv->io_base + _REG(VENC_INTCTRL));
+ 	}
+ 
+-	if (priv->hhi)
++	if (priv->intr_clks[0].clk) {
++		if (!priv->intr_clks_enabled) {
++			int ret;
++
++			ret = clk_bulk_enable(priv->num_intr_clks,
++					      priv->intr_clks);
++			if (ret)
++				dev_err(priv->dev,
++					"Failed to enable the interrupt clocks\n");
++			else
++				priv->intr_clks_enabled = true;
++		}
++	} else {
+ 		regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
++	}
+ }
+ 
+ void meson_venc_disable_vsync(struct meson_drm *priv)
+ {
+-	if (priv->hhi)
++	if (priv->intr_clks[0].clk) {
++		if (priv->intr_clks_enabled) {
++			clk_bulk_disable(priv->num_intr_clks,
++					 priv->intr_clks);
++			priv->intr_clks_enabled = false;
++		}
++	} else {
+ 		regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);
++	}
+ 
+ 	writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
+ }
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0058-drm-meson-Enable-support-for-Meson8-Meson8b-Meson8m2.patch b/patch/kernel/archive/meson-6.10/0058-drm-meson-Enable-support-for-Meson8-Meson8b-Meson8m2.patch
new file mode 100644
index 000000000000..8fe8197ee463
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0058-drm-meson-Enable-support-for-Meson8-Meson8b-Meson8m2.patch
@@ -0,0 +1,52 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 25 Apr 2020 22:14:27 +0200
+Subject: drm/meson: Enable support for Meson8/Meson8b/Meson8m2
+
+Add a compatible string for each of the three SoCs now that all hardware
+specific quirks are added to the driver.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/gpu/drm/meson/meson_drv.c | 18 ++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_drv.c
++++ b/drivers/gpu/drm/meson/meson_drv.c
+@@ -660,6 +660,18 @@ static void meson_drv_remove(struct platform_device *pdev)
+ 	component_master_del(&pdev->dev, &meson_drv_master_ops);
+ }
+ 
++static struct meson_drm_match_data meson_drm_m8_data = {
++	.compat = VPU_COMPATIBLE_M8,
++};
++
++static struct meson_drm_match_data meson_drm_m8b_data = {
++	.compat = VPU_COMPATIBLE_M8B,
++};
++
++static struct meson_drm_match_data meson_drm_m8m2_data = {
++	.compat = VPU_COMPATIBLE_M8M2,
++};
++
+ static struct meson_drm_match_data meson_drm_gxbb_data = {
+ 	.compat = VPU_COMPATIBLE_GXBB,
+ };
+@@ -679,6 +691,12 @@ static struct meson_drm_match_data meson_drm_g12a_data = {
+ };
+ 
+ static const struct of_device_id dt_match[] = {
++	{ .compatible = "amlogic,meson8-vpu",
++	  .data       = (void *)&meson_drm_m8_data },
++	{ .compatible = "amlogic,meson8b-vpu",
++	  .data       = (void *)&meson_drm_m8b_data },
++	{ .compatible = "amlogic,meson8m2-vpu",
++	  .data       = (void *)&meson_drm_m8m2_data },
+ 	{ .compatible = "amlogic,meson-gxbb-vpu",
+ 	  .data       = (void *)&meson_drm_gxbb_data },
+ 	{ .compatible = "amlogic,meson-gxl-vpu",
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0059-ARM-dts-meson-add-the-VPU-WiP.patch b/patch/kernel/archive/meson-6.10/0059-ARM-dts-meson-add-the-VPU-WiP.patch
new file mode 100644
index 000000000000..a2b3f861b14e
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0059-ARM-dts-meson-add-the-VPU-WiP.patch
@@ -0,0 +1,272 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 8 Dec 2018 13:50:48 +0100
+Subject: ARM: dts: meson: add the VPU - WiP
+
+WiP
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson.dtsi    | 10 ++
+ arch/arm/boot/dts/amlogic/meson8.dtsi   | 80 +++++++++
+ arch/arm/boot/dts/amlogic/meson8b.dtsi  | 81 ++++++++++
+ arch/arm/boot/dts/amlogic/meson8m2.dtsi |  4 +
+ 4 files changed, 175 insertions(+)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson.dtsi
+@@ -38,6 +38,16 @@ hhi: system-controller@4000 {
+ 				#address-cells = <1>;
+ 				#size-cells = <1>;
+ 				ranges = <0x0 0x4000 0x400>;
++
++
++				cvbs_dac: video-dac@2f4 {
++					compatible = "amlogic,meson-cvbs-dac";
++					reg = <0x2f4 0x8>;
++
++					#phy-cells = <0>;
++
++					status = "disabled";
++				};
+ 			};
+ 
+ 			aiu: audio-controller@5400 {
+diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi
+@@ -314,6 +314,71 @@ mali: gpu@c0000 {
+ 			operating-points-v2 = <&gpu_opp_table>;
+ 			#cooling-cells = <2>; /* min followed by max */
+ 		};
++
++		vpu: vpu@100000 {
++			compatible = "amlogic,meson8-vpu";
++
++			reg = <0x100000 0x10000>;
++			reg-names = "vpu";
++
++			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
++
++			amlogic,canvas = <&canvas>;
++
++			/*
++			 * The VCLK{,2}_IN path always needs to derived from
++			 * the CLKID_VID_PLL_FINAL_DIV so other clocks like
++			 * MPLL1 are not used (MPLL1 is reserved for audio
++			 * purposes).
++			 */
++			assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>,
++					  <&clkc CLKID_VCLK2_IN_SEL>;
++			assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>,
++						 <&clkc CLKID_VID_PLL_FINAL_DIV>;
++
++			clocks = <&clkc CLKID_VPU_INTR>,
++				 <&clkc CLKID_HDMI_INTR_SYNC>,
++				 <&clkc CLKID_GCLK_VENCI_INT>,
++				 <&clkc CLKID_HDMI_PLL_HDMI_OUT>,
++				 <&clkc CLKID_HDMI_TX_PIXEL>,
++				 <&clkc CLKID_CTS_ENCP>,
++				 <&clkc CLKID_CTS_ENCI>,
++				 <&clkc CLKID_CTS_ENCT>,
++				 <&clkc CLKID_CTS_ENCL>,
++				 <&clkc CLKID_CTS_VDAC0>;
++			clock-names = "vpu_intr",
++				      "hdmi_intr_sync",
++				      "venci_int",
++				      "tmds",
++				      "hdmi_tx_pixel",
++				      "cts_encp",
++				      "cts_enci",
++				      "cts_enct",
++				      "cts_encl",
++				      "cts_vdac0";
++
++			resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>,
++				 <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>,
++				 <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>,
++				 <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>;
++			reset-names = "vid_pll_pre",
++				      "vid_pll_post",
++				      "vid_pll_soft_pre",
++				      "vid_pll_soft_post";
++
++			phys = <&cvbs_dac>;
++			phy-names = "cvbs-dac";
++
++			power-domains = <&pwrc PWRC_MESON8_VPU_ID>;
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			/* CVBS VDAC output port */
++			cvbs_vdac_port: port@0 {
++				reg = <0>;
++			};
++		};
+ 	};
+ }; /* end of / */
+ 
+@@ -617,6 +682,17 @@ smp-sram@1ff80 {
+ 	};
+ };
+ 
++&cvbs_dac {
++	compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac";
++
++	clocks = <&clkc CLKID_CTS_VDAC0>;
++
++	nvmem-cells = <&cvbs_trimming>;
++	nvmem-cell-names = "cvbs_trimming";
++
++	status = "okay";
++};
++
+ &efuse {
+ 	compatible = "amlogic,meson8-efuse";
+ 	clocks = <&clkc CLKID_EFUSE>;
+@@ -626,6 +702,10 @@ temperature_calib: calib@1f4 {
+ 		/* only the upper two bytes are relevant */
+ 		reg = <0x1f4 0x4>;
+ 	};
++
++	cvbs_trimming: calib@1f8 {
++		reg = <0x1f8 0x2>;
++	};
+ };
+ 
+ &ethmac {
+diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8b.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi
+@@ -276,6 +276,71 @@ mali: gpu@c0000 {
+ 			operating-points-v2 = <&gpu_opp_table>;
+ 			#cooling-cells = <2>; /* min followed by max */
+ 		};
++
++		vpu: vpu@100000 {
++			compatible = "amlogic,meson8b-vpu";
++
++			reg = <0x100000 0x10000>;
++			reg-names = "vpu";
++
++			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
++
++			amlogic,canvas = <&canvas>;
++
++			/*
++			 * The VCLK{,2}_IN path always needs to derived from
++			 * the CLKID_VID_PLL_FINAL_DIV so other clocks like
++			 * MPLL1 are not used (MPLL1 is reserved for audio
++			 * purposes).
++			 */
++			assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>,
++					  <&clkc CLKID_VCLK2_IN_SEL>;
++			assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>,
++						 <&clkc CLKID_VID_PLL_FINAL_DIV>;
++
++			clocks = <&clkc CLKID_VPU_INTR>,
++				 <&clkc CLKID_HDMI_INTR_SYNC>,
++				 <&clkc CLKID_GCLK_VENCI_INT>,
++				 <&clkc CLKID_HDMI_PLL_HDMI_OUT>,
++				 <&clkc CLKID_HDMI_TX_PIXEL>,
++				 <&clkc CLKID_CTS_ENCP>,
++				 <&clkc CLKID_CTS_ENCI>,
++				 <&clkc CLKID_CTS_ENCT>,
++				 <&clkc CLKID_CTS_ENCL>,
++				 <&clkc CLKID_CTS_VDAC0>;
++			clock-names = "vpu_intr",
++				      "hdmi_intr_sync",
++				      "venci_int",
++				      "tmds",
++				      "hdmi_tx_pixel",
++				      "cts_encp",
++				      "cts_enci",
++				      "cts_enct",
++				      "cts_encl",
++				      "cts_vdac0";
++
++			resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>,
++				 <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>,
++				 <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>,
++				 <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>;
++			reset-names = "vid_pll_pre",
++				      "vid_pll_post",
++				      "vid_pll_soft_pre",
++				      "vid_pll_soft_post";
++
++			phys = <&cvbs_dac>;
++			phy-names = "cvbs-dac";
++
++			power-domains = <&pwrc PWRC_MESON8_VPU_ID>;
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			/* CVBS VDAC output port */
++			cvbs_vdac_port: port@0 {
++				reg = <0>;
++			};
++		};
+ 	};
+ }; /* end of / */
+ 
+@@ -389,6 +454,8 @@ &ao_arc_rproc {
+ 	sram = <&ao_arc_sram>;
+ 	resets = <&reset RESET_MEDIA_CPU>;
+ 	clocks = <&clkc CLKID_AO_MEDIA_CPU>;
++	status = "okay";
++	firmware-name = "zephyr.elf";
+ };
+ 
+ &cbus {
+@@ -547,6 +614,16 @@ smp-sram@1ff80 {
+ 	};
+ };
+ 
++&cvbs_dac {
++	compatible = "amlogic,meson8b-cvbs-dac", "amlogic,meson-cvbs-dac";
++
++	clocks = <&clkc CLKID_CTS_VDAC0>;
++
++	nvmem-cells = <&cvbs_trimming>;
++	nvmem-cell-names = "cvbs_trimming";
++
++	status = "okay";
++};
+ 
+ &efuse {
+ 	compatible = "amlogic,meson8b-efuse";
+@@ -557,6 +634,10 @@ temperature_calib: calib@1f4 {
+ 		/* only the upper two bytes are relevant */
+ 		reg = <0x1f4 0x4>;
+ 	};
++
++	cvbs_trimming: calib@1f8 {
++		reg = <0x1f8 0x2>;
++	};
+ };
+ 
+ &ethmac {
+diff --git a/arch/arm/boot/dts/amlogic/meson8m2.dtsi b/arch/arm/boot/dts/amlogic/meson8m2.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8m2.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8m2.dtsi
+@@ -96,6 +96,10 @@ &usb1_phy {
+ 	compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
+ };
+ 
++&vpu {
++	compatible = "amlogic,meson8m2-vpu";
++};
++
+ &wdt {
+ 	compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0060-ARM-dts-meson8-add-the-HDMI-controller-WiP.patch b/patch/kernel/archive/meson-6.10/0060-ARM-dts-meson8-add-the-HDMI-controller-WiP.patch
new file mode 100644
index 000000000000..210b28a90799
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0060-ARM-dts-meson8-add-the-HDMI-controller-WiP.patch
@@ -0,0 +1,125 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 5 May 2019 02:30:11 +0200
+Subject: ARM: dts: meson8: add the HDMI controller - WiP
+
+WiP
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson8.dtsi | 67 +++++++++-
+ 1 file changed, 65 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi
+@@ -315,6 +315,39 @@ mali: gpu@c0000 {
+ 			#cooling-cells = <2>; /* min followed by max */
+ 		};
+ 
++		hdmi_tx: hdmi-tx@42000 {
++			compatible = "amlogic,meson8-hdmi-tx";
++			reg = <0x42000 0xc>;
++			interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
++			phys = <&hdmi_tx_phy>;
++			phy-names = "hdmi";
++			clocks = <&clkc CLKID_HDMI_PCLK>,
++				 <&clkc CLKID_HDMI_SYS>;
++			clock-names = "pclk", "sys";
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			#sound-dai-cells = <1>;
++			sound-name-prefix = "HDMITX";
++
++			status = "disabled";
++
++			/* VPU VENC Input */
++			hdmi_tx_venc_port: port@0 {
++				reg = <0>;
++
++				hdmi_tx_in: endpoint {
++					remote-endpoint = <&hdmi_tx_out>;
++				};
++			};
++
++			/* TMDS Output */
++			hdmi_tx_tmds_port: port@1 {
++				reg = <1>;
++			};
++		};
++
+ 		vpu: vpu@100000 {
+ 			compatible = "amlogic,meson8-vpu";
+ 
+@@ -378,6 +411,15 @@ vpu: vpu@100000 {
+ 			cvbs_vdac_port: port@0 {
+ 				reg = <0>;
+ 			};
++
++			/* HDMI-TX output port */
++			hdmi_tx_port: port@1 {
++				reg = <1>;
++
++				hdmi_tx_out: endpoint {
++					remote-endpoint = <&hdmi_tx_in>;
++				};
++			};
+ 		};
+ 	};
+ }; /* end of / */
+@@ -544,11 +586,26 @@ gpio: banks@80b0 {
+ 			gpio-ranges = <&pinctrl_cbus 0 0 120>;
+ 		};
+ 
++		hdmi_hpd_pins: hdmi-hpd {
++			mux {
++				groups = "hdmi_hpd";
++				function = "hdmi";
++				bias-disable;
++			};
++		};
++
++		hdmi_i2c_pins: hdmi-i2c {
++			mux {
++				groups = "hdmi_sda", "hdmi_scl";
++				function = "hdmi";
++				bias-disable;
++			};
++		};
++
+ 		pwm_c_dv9_pins: pwm-c-dv9 {
+ 			mux {
+ 				groups = "pwm_c_dv9";
+ 				function = "pwm_c";
+-				bias-disable;
+ 			};
+ 		};
+ 
+@@ -556,7 +613,6 @@ pwm_d_pins: pwm-d {
+ 			mux {
+ 				groups = "pwm_d";
+ 				function = "pwm_d";
+-				bias-disable;
+ 			};
+ 		};
+ 
+@@ -740,6 +796,13 @@ pwrc: power-controller@100 {
+ 		assigned-clocks = <&clkc CLKID_VPU>;
+ 		assigned-clock-rates = <364285714>;
+ 	};
++
++	hdmi_tx_phy: hdmi-phy@3a0 {
++		compatible = "amlogic,meson8-hdmi-tx-phy";
++		clocks = <&clkc CLKID_HDMI_PLL_HDMI_OUT>;
++		reg = <0x3a0 0xc>;
++		#phy-cells = <0>;
++	};
+ };
+ 
+ &hwrng {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0061-ARM-dts-meson8-Add-the-shared-CMA-dma-memory-pool.patch b/patch/kernel/archive/meson-6.10/0061-ARM-dts-meson8-Add-the-shared-CMA-dma-memory-pool.patch
new file mode 100644
index 000000000000..4d04d132a2cc
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0061-ARM-dts-meson8-Add-the-shared-CMA-dma-memory-pool.patch
@@ -0,0 +1,36 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 4 Jun 2021 21:50:06 +0200
+Subject: ARM: dts: meson8: Add the shared CMA dma memory pool
+
+The 4K HDMI modes needs more CMA memory (than the default 64MiB) to be
+reserved at boot-time. Add a shared-dma-pool with increased size so the
+4K HDMI modes can be used.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson8.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi
+@@ -193,6 +193,14 @@ power-firmware@4f00000 {
+ 			reg = <0x4f00000 0x100000>;
+ 			no-map;
+ 		};
++
++		linux,cma {
++			compatible = "shared-dma-pool";
++			reusable;
++			size = <0x10000000>;
++			alignment = <0x400000>;
++			linux,cma-default;
++		};
+ 	};
+ 
+ 	thermal-zones {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0062-ARM-dts-meson8-add-the-AO-CEC-controller-WiP.patch b/patch/kernel/archive/meson-6.10/0062-ARM-dts-meson8-add-the-AO-CEC-controller-WiP.patch
new file mode 100644
index 000000000000..381efd34c424
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0062-ARM-dts-meson8-add-the-AO-CEC-controller-WiP.patch
@@ -0,0 +1,50 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 5 May 2019 11:44:08 +0200
+Subject: ARM: dts: meson8: add the AO CEC controller - WiP
+
+WiP
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson8.dtsi | 17 ++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi
+@@ -478,6 +478,14 @@ gpio_ao: ao-bank@14 {
+ 			gpio-ranges = <&pinctrl_aobus 0 0 16>;
+ 		};
+ 
++		hdmi_cec_ao_pins: hdmi-cec-ao {
++			mux {
++				groups = "hdmi_cec_ao";
++				function = "hdmi_cec_ao";
++				bias-pull-up;
++			};
++		};
++
+ 		i2s_am_clk_pins: i2s-am-clk-out {
+ 			mux {
+ 				groups = "i2s_am_clk_out_ao";
+@@ -542,6 +550,15 @@ mux {
+ 			};
+ 		};
+ 	};
++
++	cec_AO: cec@100 {
++		compatible = "amlogic,meson-gx-ao-cec"; // FIXME
++		reg = <0x100 0x14>;
++		interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
++		// TODO: 32768HZ clock
++		hdmi-phandle = <&hdmi_tx>;
++		status = "disabled";
++	};
+ };
+ 
+ &ao_arc_rproc {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0063-ARM-dts-meson8b-add-the-HDMI-controller-WiP.patch b/patch/kernel/archive/meson-6.10/0063-ARM-dts-meson8b-add-the-HDMI-controller-WiP.patch
new file mode 100644
index 000000000000..a4f1d844ae11
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0063-ARM-dts-meson8b-add-the-HDMI-controller-WiP.patch
@@ -0,0 +1,120 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 5 May 2019 02:30:29 +0200
+Subject: ARM: dts: meson8b: add the HDMI controller - WiP
+
+WiP
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson8b.dtsi | 69 ++++++++++
+ 1 file changed, 69 insertions(+)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8b.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi
+@@ -277,6 +277,39 @@ mali: gpu@c0000 {
+ 			#cooling-cells = <2>; /* min followed by max */
+ 		};
+ 
++		hdmi_tx: hdmi-tx@42000 {
++			compatible = "amlogic,meson8b-hdmi-tx";
++			reg = <0x42000 0xc>;
++			interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
++			phys = <&hdmi_tx_phy>;
++			phy-names = "hdmi";
++			clocks = <&clkc CLKID_HDMI_PCLK>,
++				 <&clkc CLKID_HDMI_SYS>;
++			clock-names = "pclk", "sys";
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			#sound-dai-cells = <1>;
++			sound-name-prefix = "HDMITX";
++
++			status = "disabled";
++
++			/* VPU VENC Input */
++			hdmi_tx_venc_port: port@0 {
++				reg = <0>;
++
++				hdmi_tx_in: endpoint {
++					remote-endpoint = <&hdmi_tx_out>;
++				};
++			};
++
++			/* TMDS Output */
++			hdmi_tx_tmds_port: port@1 {
++				reg = <1>;
++			};
++		};
++
+ 		vpu: vpu@100000 {
+ 			compatible = "amlogic,meson8b-vpu";
+ 
+@@ -336,10 +369,22 @@ vpu: vpu@100000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 
++			#sound-dai-cells = <0>;
++			sound-name-prefix = "HDMITX";
++
+ 			/* CVBS VDAC output port */
+ 			cvbs_vdac_port: port@0 {
+ 				reg = <0>;
+ 			};
++
++			/* HDMI-TX output port */
++			hdmi_tx_port: port@1 {
++				reg = <1>;
++
++				hdmi_tx_out: endpoint {
++					remote-endpoint = <&hdmi_tx_in>;
++				};
++			};
+ 		};
+ 	};
+ }; /* end of / */
+@@ -538,6 +583,22 @@ mux {
+ 			};
+ 		};
+ 
++		hdmi_hpd_pins: hdmi-hpd {
++			mux {
++				groups = "hdmi_hpd";
++				function = "hdmi";
++				bias-disable;
++			};
++		};
++
++		hdmi_i2c_pins: hdmi-i2c {
++			mux {
++				groups = "hdmi_sda", "hdmi_scl";
++				function = "hdmi";
++				bias-disable;
++			};
++		};
++
+ 		i2c_a_pins: i2c-a {
+ 			mux {
+ 				groups = "i2c_sda_a", "i2c_sck_a";
+@@ -700,6 +761,14 @@ pwrc: power-controller@100 {
+ 		assigned-clocks = <&clkc CLKID_VPU>;
+ 		assigned-clock-rates = <182142857>;
+ 	};
++
++	hdmi_tx_phy: hdmi-phy@3a0 {
++		compatible = "amlogic,meson8b-hdmi-tx-phy",
++			     "amlogic,meson8-hdmi-tx-phy";
++		clocks = <&clkc CLKID_HDMI_PLL_HDMI_OUT>;
++		reg = <0x3a0 0xc>;
++		#phy-cells = <0>;
++	};
+ };
+ 
+ &hwrng {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0064-ARM-dts-meson8b-add-the-AO-CEC-controller-WiP.patch b/patch/kernel/archive/meson-6.10/0064-ARM-dts-meson8b-add-the-AO-CEC-controller-WiP.patch
new file mode 100644
index 000000000000..a5b50dc4baf2
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0064-ARM-dts-meson8b-add-the-AO-CEC-controller-WiP.patch
@@ -0,0 +1,50 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 5 May 2019 11:44:20 +0200
+Subject: ARM: dts: meson8b: add the AO CEC controller - WiP
+
+WiP
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson8b.dtsi | 17 ++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8b.dtsi
++++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi
+@@ -435,6 +435,14 @@ gpio_ao: ao-bank@14 {
+ 			gpio-ranges = <&pinctrl_aobus 0 0 16>;
+ 		};
+ 
++		hdmi_cec_ao_pins: hdmi-cec-ao {
++			mux {
++				groups = "hdmi_cec_1";
++				function = "hdmi_cec";
++				bias-pull-up;
++			};
++		};
++
+ 		i2s_am_clk_pins: i2s-am-clk-out {
+ 			mux {
+ 				groups = "i2s_am_clk_out";
+@@ -491,6 +499,15 @@ mux {
+ 			};
+ 		};
+ 	};
++
++	cec_AO: cec@100 {
++		compatible = "amlogic,meson-gx-ao-cec"; // FIXME
++		reg = <0x100 0x14>;
++		interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
++		// TODO: 32768HZ clock
++		hdmi-phandle = <&hdmi_tx>;
++		status = "disabled";
++	};
+ };
+ 
+ &ao_arc_rproc {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/0066-ARM-dts-meson8b-odroid-c1-enable-HDMI-for-the-Odroid.patch b/patch/kernel/archive/meson-6.10/0066-ARM-dts-meson8b-odroid-c1-enable-HDMI-for-the-Odroid.patch
new file mode 100644
index 000000000000..59c7119076f2
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/0066-ARM-dts-meson8b-odroid-c1-enable-HDMI-for-the-Odroid.patch
@@ -0,0 +1,106 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 20 Mar 2020 15:17:51 +0100
+Subject: ARM: dts: meson8b: odroid-c1: enable HDMI for the Odroid-C1 - WiP
+
+WiP
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts | 59 ++++++++++
+ 1 file changed, 59 insertions(+)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts
++++ b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts
+@@ -32,6 +32,17 @@ emmc_pwrseq: emmc-pwrseq {
+ 		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ 	};
+ 
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_connector_in: endpoint {
++				remote-endpoint = <&hdmi_tx_tmds_out>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 		led-blue {
+@@ -93,6 +104,38 @@ rtc32k_xtal: rtc32k-xtal-clk {
+ 		#clock-cells = <0>;
+ 	};
+ 
++	sound {
++		compatible = "amlogic,gx-sound-card";
++		model = "ODROID-C1";
++
++		assigned-clocks = <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>;
++
++		dai-link-0 {
++			sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
++		};
++
++		dai-link-1 {
++			sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
++			dai-format = "i2s";
++			mclk-fs = <256>;
++
++			codec-0 {
++				sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
++			};
++		};
++
++		dai-link-2 {
++			sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
++
++			codec-0 {
++				sound-dai = <&hdmi_tx 0>;
++			};
++		};
++	};
++
+ 	usb0_vbus: regulator-usb0-vbus {
+ 		/* Richtek RT9715EGB */
+ 		compatible = "regulator-fixed";
+@@ -201,6 +244,10 @@ vdd_rtc: regulator-vdd-rtc {
+ 	};
+ };
+ 
++&aiu {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&vcck>;
+ };
+@@ -297,6 +344,18 @@ &gpio_ao {
+ 			  "SYS_LED", "", "";
+ };
+ 
++&hdmi_tx {
++	status = "okay";
++	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
++	pinctrl-names = "default";
++};
++
++&hdmi_tx_tmds_port {
++	hdmi_tx_tmds_out: endpoint {
++		remote-endpoint = <&hdmi_connector_in>;
++	};
++};
++
+ &ir_receiver {
+ 	status = "okay";
+ 	pinctrl-0 = <&ir_recv_pins>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/generic-Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch b/patch/kernel/archive/meson-6.10/generic-Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch
new file mode 100644
index 000000000000..aca6b585a17d
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/generic-Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch
@@ -0,0 +1,76 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hzy <hzyitc@outlook.com>
+Date: Sat, 18 Nov 2023 01:22:04 +0800
+Subject: Revert "mmc: core: Set HS clock speed before sending HS CMD13"
+
+This reverts commit 4bc31edebde51fcf8ad0794763b8679a7ecb5ec0.
+---
+ drivers/mmc/core/mmc.c | 23 ++--------
+ 1 file changed, 4 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
+index 111111111111..222222222222 100644
+--- a/drivers/mmc/core/mmc.c
++++ b/drivers/mmc/core/mmc.c
+@@ -1401,17 +1401,13 @@ static int mmc_select_hs400es(struct mmc_card *card)
+ 		goto out_err;
+ 	}
+ 
+-	/*
+-	 * Bump to HS timing and frequency. Some cards don't handle
+-	 * SEND_STATUS reliably at the initial frequency.
+-	 */
+ 	mmc_set_timing(host, MMC_TIMING_MMC_HS);
+-	mmc_set_bus_speed(card);
+-
+ 	err = mmc_switch_status(card, true);
+ 	if (err)
+ 		goto out_err;
+ 
++	mmc_set_clock(host, card->ext_csd.hs_max_dtr);
++
+ 	/* Switch card to DDR with strobe bit */
+ 	val = EXT_CSD_DDR_BUS_WIDTH_8 | EXT_CSD_BUS_WIDTH_STROBE;
+ 	err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+@@ -1469,7 +1465,7 @@ static int mmc_select_hs400es(struct mmc_card *card)
+ static int mmc_select_hs200(struct mmc_card *card)
+ {
+ 	struct mmc_host *host = card->host;
+-	unsigned int old_timing, old_signal_voltage, old_clock;
++	unsigned int old_timing, old_signal_voltage;
+ 	int err = -EINVAL;
+ 	u8 val;
+ 
+@@ -1500,17 +1496,8 @@ static int mmc_select_hs200(struct mmc_card *card)
+ 				   false, true, MMC_CMD_RETRIES);
+ 		if (err)
+ 			goto err;
+-
+-		/*
+-		 * Bump to HS timing and frequency. Some cards don't handle
+-		 * SEND_STATUS reliably at the initial frequency.
+-		 * NB: We can't move to full (HS200) speeds until after we've
+-		 * successfully switched over.
+-		 */
+ 		old_timing = host->ios.timing;
+-		old_clock = host->ios.clock;
+ 		mmc_set_timing(host, MMC_TIMING_MMC_HS200);
+-		mmc_set_clock(card->host, card->ext_csd.hs_max_dtr);
+ 
+ 		/*
+ 		 * For HS200, CRC errors are not a reliable way to know the
+@@ -1523,10 +1510,8 @@ static int mmc_select_hs200(struct mmc_card *card)
+ 		 * mmc_select_timing() assumes timing has not changed if
+ 		 * it is a switch error.
+ 		 */
+-		if (err == -EBADMSG) {
+-			mmc_set_clock(host, old_clock);
++		if (err == -EBADMSG)
+ 			mmc_set_timing(host, old_timing);
+-		}
+ 	}
+ err:
+ 	if (err) {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/generic-Revert-pwm-meson-modify-and-simplify-calculation-in-.patch b/patch/kernel/archive/meson-6.10/generic-Revert-pwm-meson-modify-and-simplify-calculation-in-.patch
new file mode 100644
index 000000000000..848cd3e4d562
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/generic-Revert-pwm-meson-modify-and-simplify-calculation-in-.patch
@@ -0,0 +1,39 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hzy <hzyitc@outlook.com>
+Date: Sat, 18 Nov 2023 01:22:04 +0800
+Subject: Revert "pwm: meson: modify and simplify calculation in
+ meson_pwm_get_state"
+
+This reverts commit 6b9352f3f8a1a35faf0efc1ad1807ee303467796.
+---
+ drivers/pwm/pwm-meson.c | 14 ++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
+index 111111111111..222222222222 100644
+--- a/drivers/pwm/pwm-meson.c
++++ b/drivers/pwm/pwm-meson.c
+@@ -322,8 +322,18 @@ static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ 	channel->lo = FIELD_GET(PWM_LOW_MASK, value);
+ 	channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
+ 
+-	state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->lo + channel->hi);
+-	state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
++	if (channel->lo == 0) {
++		state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
++		state->duty_cycle = state->period;
++	} else if (channel->lo >= channel->hi) {
++		state->period = meson_pwm_cnt_to_ns(chip, pwm,
++						    channel->lo + channel->hi);
++		state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
++							channel->hi);
++	} else {
++		state->period = 0;
++		state->duty_cycle = 0;
++	}
+ 
+ 	state->polarity = PWM_POLARITY_NORMAL;
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/onecloud-0001-add-dts.patch b/patch/kernel/archive/meson-6.10/onecloud-0001-add-dts.patch
new file mode 100644
index 000000000000..b9d9cc535d1a
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/onecloud-0001-add-dts.patch
@@ -0,0 +1,440 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hzy <hzyitc@outlook.com>
+Date: Sat, 1 Apr 2023 13:24:42 +0800
+Subject: ARM: dts: meson8b: Add DTS for Xunlei Onecloud
+
+Signed-off-by: hzy <hzyitc@outlook.com>
+---
+ arch/arm/boot/dts/amlogic/Makefile             |   1 +
+ arch/arm/boot/dts/amlogic/meson8b-onecloud.dts | 410 ++++++++++
+ 2 files changed, 411 insertions(+)
+
+diff --git a/arch/arm/boot/dts/amlogic/Makefile b/arch/arm/boot/dts/amlogic/Makefile
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/Makefile
++++ b/arch/arm/boot/dts/amlogic/Makefile
+@@ -6,4 +6,5 @@ dtb-$(CONFIG_MACH_MESON8) += \
+ 	meson8b-ec100.dtb \
+ 	meson8b-mxq.dtb \
+ 	meson8b-odroidc1.dtb \
++	meson8b-onecloud.dtb \
+ 	meson8m2-mxiii-plus.dtb
+diff --git a/arch/arm/boot/dts/amlogic/meson8b-onecloud.dts b/arch/arm/boot/dts/amlogic/meson8b-onecloud.dts
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/arch/arm/boot/dts/amlogic/meson8b-onecloud.dts
+@@ -0,0 +1,410 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Author: hzy <hzyitc@outlook.com>
++ */
++
++/dts-v1/;
++
++#include "meson8b.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++/ {
++	model = "Xunlei OneCloud";
++	compatible = "xunlei,onecloud", "amlogic,meson8b";
++
++	aliases {
++		serial0 = &uart_AO;
++		mmc0 = &sd_card_slot;
++		mmc1 = &sdhc;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x40000000 0x40000000>;
++	};
++
++	emmc_pwrseq: emmc-pwrseq {
++		compatible = "mmc-pwrseq-emmc";
++		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
++	};
++
++	button {
++		// compatible = "gpio-keys-polled";
++		// poll-interval = <100>;
++
++		compatible = "gpio-keys";
++
++		autorepeat;
++
++		reset-button {
++			label = "reset";
++			linux,code = <BTN_0>;
++
++			// gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_LOW>;
++
++			interrupt-parent = <&gpio_intc>;
++			interrupts = <5 IRQ_TYPE_LEVEL_LOW>; // GPIOAO 5
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		red {
++			label = "onecloud:red:alive";
++			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
++
++			default-state = "on";
++			linux,default-trigger = "default-on";
++		};
++
++		green {
++			label = "onecloud:green:alive";
++			gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
++
++			default-state = "off";
++			linux,default-trigger = "mmc1";
++		};
++
++		blue {
++			label = "onecloud:blue:alive";
++			gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
++
++			default-state = "off";
++			linux,default-trigger = "usb-host";
++		};
++	};
++
++	p12v: regulator-p12v {
++		compatible = "regulator-fixed";
++
++		regulator-name = "P12V";
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	vcc_5v: regulator-vcc-5v {
++		compatible = "regulator-fixed";
++
++		regulator-name = "VCC5V";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++
++		vin-supply = <&p12v>;
++
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	vcc_3v3: regulator-vcc-3v3 {
++		compatible = "regulator-fixed";
++
++		regulator-name = "VCC3V3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++
++		vin-supply = <&p12v>;
++
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	vcc_1v8: regulator-vcc-1v8 {
++		compatible = "regulator-fixed";
++
++		regulator-name = "VCC1V8";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++
++		vin-supply = <&p12v>;
++
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	vcc_ddr: regulator-vcc-ddr {
++		compatible = "regulator-fixed";
++
++		regulator-name = "VCC_DDR";
++		regulator-min-microvolt = <1500000>;
++		regulator-max-microvolt = <1500000>;
++
++		vin-supply = <&vcc_3v3>;
++
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	vcc_core: regulator-vcc-core {
++		compatible = "pwm-regulator";
++
++		regulator-name = "VCC_CORE";
++
++		//   +---------------------------------------------------+
++		//   |           The actual mapping in phyical           |
++		//   +------+--------+--------+--------+--------+--------+
++		//   |      |  100%  |   60%  |   30%  |   10%  |   0%   |
++		//   +------+--------+--------+--------+--------+--------+
++		//   | V1.0 |  677mV |  857mV |  992mV | 1082mV | 1127mV |
++		//   | V1.3 | 1116mV | 1121mV | 1125mV | 1128mV | 1129mV |
++		//   +------+--------+--------+--------+--------+--------+
++		//
++		// According to meson8b.dtsi, the CPU should be able to
++		// run at 504MHz with 870mV. But this regulator supplies
++		// not only CPU but also GPU. And according to the users'
++		// tests on V1.0, we need such higher voltages.
++
++		pwms = <&pwm_cd 1 12001 0>;	// PWM_D
++		pwm-dutycycle-range = <10 0>;
++		regulator-min-microvolt = <860000>;
++		regulator-max-microvolt = <1140000>;
++
++		pwm-supply = <&p12v>;
++
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
++&uart_AO {
++	status = "okay";
++	pinctrl-0 = <&uart_ao_a_pins>;
++	pinctrl-names = "default";
++};
++
++&pwm_cd {
++	status = "okay";
++	pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
++	pinctrl-names = "default";
++	clocks = <&xtal>, <&xtal>;
++	clock-names = "clkin0", "clkin1";
++};
++
++&cpu0 {
++	cpu-supply = <&vcc_core>;
++};
++
++&saradc {
++	status = "okay";
++	vref-supply = <&vcc_1v8>;
++};
++
++&mali {
++	// commented to allow cpufreq tweaking
++	// mali-supply = <&vcc_core>;
++};
++
++&gpio {
++	gpio-line-names =
++		/*  0 */ "WIFI_SDIO_D0 PIN18 (GPIOX_0)",
++		/*  1 */ "WIFI_SDIO_D1 PIN19 (GPIOX_1)",
++		/*  2 */ "WIFI_SDIO_D2 PIN14 (GPIOX_2)",
++		/*  3 */ "WIFI_SDIO_D3 PIN15 (GPIOX_3)",
++		/*  4 */ "WIFI_PCM_DIN PIN27 (GPIOX_4)",
++		/*  5 */ "WIFI_PCM_DOUT PIN25 (GPIOX_5)",
++		/*  6 */ "WIFI_PCM_SYNC PIN28 (GPIOX_6)",
++		/*  7 */ "WIFI_PCM_CLK PIN26 (GPIOX_7)",
++		/*  8 */ "WIFI_SDIO_CLK PIN17_Resistor (GPIOX_8)",
++		/*  9 */ "WIFI_SDIO_CMD PIN16 (GPIOX_9)",
++		/* 10 */ "GPIOX_10",
++		/* 11 */ "WIFI PIN12 (GPIOX_11)",
++		/* 12 */ "WIFI_UART_RX PIN43 (GPIOX_16)",
++		/* 13 */ "WIFI_UART_TX PIN42 (GPIOX_17)",
++		/* 14 */ "WIFI_UART_RTS PIN41_Resistor (GPIOX_18)",
++		/* 15 */ "WIFI_UART_CTS PIN44 (GPIOX_19)",
++		/* 16 */ "WIFI PIN34 (GPIOX_20)",
++		/* 17 */ "WIFI_WAKE PIN13 (GPIOX_21)",
++
++		/* 18 */ "Resistor_TopOf_LED (GPIOY_0)",
++		/* 19 */ "GPIOY_1",
++		/* 20 */ "GPIOY_3",
++		/* 21 */ "GPIOY_6",
++		/* 22 */ "GPIOY_7",
++		/* 23 */ "GPIOY_8",
++		/* 24 */ "GPIOY_9",
++		/* 25 */ "GPIOY_10",
++		/* 26 */ "GPIOY_11",
++		/* 27 */ "GPIOY_12",
++		/* 28 */ "Left_BottomOf_CPU (GPIOY_13)",
++		/* 29 */ "Right_BottomOf_CPU (GPIOY_14)",
++
++		/* 30 */ "GPIODV_9 (PWM_C)",
++		/* 31 */ "GPIODV_24",
++		/* 32 */ "GPIODV_25",
++		/* 33 */ "GPIODV_26",
++		/* 34 */ "GPIODV_27",
++		/* 35 */ "VCC_CPU_PWM (GPIODV_28)",
++		/* 36 */ "GPIODV_29",
++
++		/* 37 */ "HDMI_HPD (GPIOH_0)",
++		/* 38 */ "HDMI_SDA (GPIOH_1)",
++		/* 39 */ "HDMI_SCL (GPIOH_2)",
++		/* 40 */ "ETH_PHY_INTR (GPIOH_3)",
++		/* 41 */ "ETH_PHY_nRST (GPIOH_4)",
++		/* 42 */ "ETH_TXD1 (GPIOH_5)",
++		/* 43 */ "ETH_TXD0 (GPIOH_6)",
++		/* 44 */ "ETH_TXD3 (GPIOH_7)",
++		/* 45 */ "ETH_TXD2 (GPIOH_8)",
++		/* 46 */ "ETH_TX_CLK (GPIOH_9)",
++
++		/* 47 */ "SDCARD_D1 (CARD_0)",
++		/* 48 */ "SDCARD_D0 (CARD_1)",
++		/* 49 */ "SDCARD_CLK (CARD_2)",
++		/* 50 */ "SDCARD_CMD (CARD_3)",
++		/* 51 */ "SDCARD_D3 (CARD_4)",
++		/* 52 */ "SDCARD_D2 (CARD_5)",
++		/* 53 */ "SDCARD_CD (CARD_6)",
++
++		/* 54 */ "EMMC_D0 (BOOT_0)",
++		/* 55 */ "EMMC_D1 (BOOT_1)",
++		/* 56 */ "EMMC_D2 (BOOT_2)",
++		/* 57 */ "EMMC_D3 (BOOT_3)",
++		/* 58 */ "EMMC_D4 (BOOT_4)",
++		/* 59 */ "EMMC_D5 (BOOT_5)",
++		/* 60 */ "EMMC_D6 (BOOT_6)",
++		/* 61 */ "EMMC_D7 (BOOT_7)",
++		/* 62 */ "EMMC_CLK (BOOT_8)",
++		/* 63 */ "EMMC_nRST (BOOT_9)",
++		/* 64 */ "EMMC_CMD (BOOT_10)",
++		/* 65 */ "BOOT_11",
++		/* 66 */ "BOOT_12",
++		/* 67 */ "BOOT_13",
++		/* 68 */ "BOOT_14",
++		/* 69 */ "BOOT_15",
++		/* 70 */ "BOOT_16",
++		/* 71 */ "BOOT_17",
++		/* 72 */ "BOOT_18",
++
++		/* 73 */ "ETH_RXD1 (DIF_0_P)",
++		/* 74 */ "ETH_RXD0 (DIF_0_N)",
++		/* 75 */ "ETH_RX_DV (DIF_1_P)",
++		/* 76 */ "ETH_RX_CLK (DIF_1_N)",
++		/* 77 */ "ETH_RXD3 (DIF_2_P)",
++		/* 78 */ "ETH_RXD2 (DIF_2_N)",
++		/* 79 */ "ETH_TX_EN (DIF_3_P)",
++		/* 80 */ "ETH_REF_CLK (DIF_3_N)",
++		/* 81 */ "ETH_MDC (DIF_4_P)",
++		/* 82 */ "ETH_MDIO_EN (DIF_4_N)";
++};
++
++&gpio_ao {
++	gpio-line-names =
++		/*  0 */ "UART TX (GPIOAO_0)",
++		/*  1 */ "UART RX (GPIOAO_1)",
++		/*  2 */ "RED_LED (GPIOAO_2)",
++		/*  3 */ "GREEN_LED (GPIOAO_3)",
++		/*  4 */ "BLUE_LED (GPIOAO_4)",
++		/*  5 */ "BUTTON (GPIOAO_5)",
++		/*  6 */ "GPIOAO_6",
++		/*  7 */ "IR_IN (GPIOAO_7)",
++		/*  8 */ "GPIOAO_8",
++		/*  9 */ "GPIOAO_9",
++		/* 10 */ "GPIOAO_10",
++		/* 11 */ "GPIOAO_11",
++		/* 12 */ "GPIOAO_12",
++		/* 13 */ "GPIOAO_13",
++
++		/* 14 */ "GPIO_BSD_EN",
++		/* 15 */ "GPIO_TEST_N";
++};
++
++// eMMC
++&sdhc {
++	status = "okay";
++
++	pinctrl-0 = <&sdxc_c_pins>;
++	pinctrl-names = "default";
++
++	non-removable;
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	cap-mmc-highspeed;
++	mmc-hs200-1_8v;
++
++	mmc-pwrseq = <&emmc_pwrseq>;
++	vmmc-supply = <&vcc_3v3>;
++	// vqmmc-supply = <&vcc_3v3>;
++};
++
++&sdio {
++	status = "okay";
++
++	pinctrl-0 = <&sd_b_pins>;
++	pinctrl-names = "default";
++
++	// SD card
++	sd_card_slot: slot@1 {
++		compatible = "mmc-slot";
++		reg = <1>;
++		status = "okay";
++
++		bus-width = <4>;
++		no-sdio;
++		cap-mmc-highspeed;
++		cap-sd-highspeed;
++		disable-wp;
++
++		cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
++
++		vmmc-supply = <&vcc_3v3>;
++		// vqmmc-supply = <&vcc_3v3>;
++	};
++};
++
++&ethmac {
++	status = "okay";
++
++	pinctrl-0 = <&eth_rgmii_pins>;
++	pinctrl-names = "default";
++
++	phy-handle = <&eth_phy>;
++	phy-mode = "rgmii-rxid";
++
++	mdio {
++		compatible = "snps,dwmac-mdio";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		// Realtek RTL8211F (0x001cc916)
++		eth_phy: ethernet-phy@0 {
++			reg = <0>;
++
++			reset-assert-us = <10000>;
++			reset-deassert-us = <80000>;
++			reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
++
++			interrupt-parent = <&gpio_intc>;
++			interrupts = <17 IRQ_TYPE_LEVEL_LOW>; // GPIOH 3
++		};
++	};
++};
++
++&usb0 {
++	status = "okay";
++	dr_mode = "otg";
++	usb-role-switch;
++	role-switch-default-mode = "host";
++};
++
++&usb0_phy {
++	status = "okay";
++};
++
++&usb1 {
++	status = "okay";
++};
++
++&usb1_phy {
++	status = "okay";
++};
++
++&ir_receiver {
++	status = "okay";
++	pinctrl-0 = <&ir_recv_pins>;
++	pinctrl-names = "default";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson-6.10/onecloud-0002-dts-Support-HDMI.patch b/patch/kernel/archive/meson-6.10/onecloud-0002-dts-Support-HDMI.patch
new file mode 100644
index 000000000000..597a2676b2c1
--- /dev/null
+++ b/patch/kernel/archive/meson-6.10/onecloud-0002-dts-Support-HDMI.patch
@@ -0,0 +1,96 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hzy <hzyitc@outlook.com>
+Date: Sat, 1 Apr 2023 10:26:14 +0800
+Subject: ARM: dts: meson8b: onecloud: Support HDMI
+
+Signed-off-by: hzy <hzyitc@outlook.com>
+---
+ arch/arm/boot/dts/amlogic/meson8b-onecloud.dts | 58 ++++++++++
+ 1 file changed, 58 insertions(+)
+
+diff --git a/arch/arm/boot/dts/amlogic/meson8b-onecloud.dts b/arch/arm/boot/dts/amlogic/meson8b-onecloud.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/amlogic/meson8b-onecloud.dts
++++ b/arch/arm/boot/dts/amlogic/meson8b-onecloud.dts
+@@ -80,6 +80,48 @@ blue {
+ 		};
+ 	};
+ 
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_connector_in: endpoint {
++				remote-endpoint = <&hdmi_tx_tmds_out>;
++			};
++		};
++	};
++
++	sound {
++		compatible = "amlogic,gx-sound-card";
++
++		assigned-clocks = <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>;
++
++		dai-link-0 {
++			sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
++		};
++
++		dai-link-1 {
++			sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
++			dai-format = "i2s";
++			mclk-fs = <256>;
++
++			codec-0 {
++				sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
++			};
++		};
++
++		dai-link-2 {
++			sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
++
++			codec-0 {
++				sound-dai = <&hdmi_tx 0>;
++			};
++		};
++	};
++
+ 	p12v: regulator-p12v {
+ 		compatible = "regulator-fixed";
+ 
+@@ -199,6 +241,10 @@ &mali {
+ 	// mali-supply = <&vcc_core>;
+ };
+ 
++&aiu {
++	status = "okay";
++};
++
+ &gpio {
+ 	gpio-line-names =
+ 		/*  0 */ "WIFI_SDIO_D0 PIN18 (GPIOX_0)",
+@@ -403,6 +449,18 @@ &usb1_phy {
+ 	status = "okay";
+ };
+ 
++&hdmi_tx {
++	status = "okay";
++	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
++	pinctrl-names = "default";
++};
++
++&hdmi_tx_tmds_port {
++	hdmi_tx_tmds_out: endpoint {
++		remote-endpoint = <&hdmi_connector_in>;
++	};
++};
++
+ &ir_receiver {
+ 	status = "okay";
+ 	pinctrl-0 = <&ir_recv_pins>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/0000.patching_config.yaml b/patch/kernel/archive/meson64-6.10/0000.patching_config.yaml
new file mode 100644
index 000000000000..393d991777f2
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/0000.patching_config.yaml
@@ -0,0 +1,38 @@
+config:
+
+  # Just some info stuff; not used by the patching scripts
+  name: meson64-6.7
+  kind: kernel
+  type: mainline # or: vendor
+  branch: linux-6.7.y
+  last-known-good-tag: v6.7.0
+  maintainers:
+    - { github: rpardini, name: Ricardo Pardini, email: ricardo@pardini.net, armbian-forum: rpardini }
+
+  # .dts files in these directories will be copied as-is to the build tree; later ones overwrite earlier ones.
+  # This is meant to provide a way to "add a board DTS" without having to null-patch them in.
+  dts-directories:
+    # will copy patch/kernel/archive/meson64-MAJOR.MINOR/dt-boards/*.dts to arch/arm64/boot/dts/amlogic
+    - { source: "dt", target: "arch/arm64/boot/dts/amlogic" }
+
+  # every file in these directories will be copied as-is to the build tree; later ones overwrite earlier ones
+  # This is meant as a way to have overlays, bare, in a directory, without having to null-patch them in.
+  # @TODO need a solution to auto-Makefile the overlays as well
+  overlay-directories:
+    # will copy patch/kernel/archive/meson64-MAJOR.MINOR/overlay/**/* to arch/arm64/boot/dts/amlogic/overlay
+    - { source: "overlay", target: "arch/arm64/boot/dts/amlogic/overlay" }
+
+  # the Makefile in each of these directories will be magically patched to include the dts files copied
+  #  or patched-in; overlay subdir will be included "-y" if it exists.
+  # No more Makefile patching needed, yay!
+  auto-patch-dt-makefile:
+    - { directory: "arch/arm64/boot/dts/amlogic", config-var: "CONFIG_ARCH_MESON" }
+
+  # configuration for when applying patches to git / auto-rewriting patches (development cycle helpers)
+  patches-to-git:
+    do-not-commit-files:
+      - "MAINTAINERS" # constant churn, drop them. sorry.
+      - "Documentation/devicetree/bindings/arm/amlogic.yaml" # constant churn, conflicts on every bump, drop it. sorry.
+    do-not-commit-regexes: # Python-style regexes
+      - "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9]+)/Makefile$" # ignore DT Makefile patches, we've an auto-patcher now
+
diff --git a/patch/kernel/archive/meson64-6.10/board-bananapi-cm4-cm4io.patch b/patch/kernel/archive/meson64-6.10/board-bananapi-cm4-cm4io.patch
new file mode 100644
index 000000000000..2d8de7211968
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-bananapi-cm4-cm4io.patch
@@ -0,0 +1,77 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Tue, 25 Jul 2023 13:31:54 -0400
+Subject: arch: arm64: dts: amlogic: meson g12b bananapi cm4
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts |  9 +++++--
+ arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi      | 12 ++++++++--
+ 2 files changed, 17 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts
+@@ -50,14 +50,15 @@ leds {
+ 		led-blue {
+ 			color = <LED_COLOR_ID_BLUE>;
+ 			function = LED_FUNCTION_STATUS;
+-			gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
++			gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
+ 			linux,default-trigger = "heartbeat";
+ 		};
+ 
+ 		led-green {
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			function = LED_FUNCTION_STATUS;
+-			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
++			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
++			linux,default-trigger = "default-on";
+ 		};
+ 	};
+ 
+@@ -116,6 +117,10 @@ codec {
+ 	};
+ };
+ 
++&reboot {
++	sd-vqen = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
++};
++
+ &cecb_AO {
+ 	status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
+@@ -12,6 +12,15 @@ aliases {
+ 		rtc1 = &vrtc;
+ 	};
+ 
++	reboot: meson64-reboot {
++		compatible = "meson64,reboot";
++		sys_reset = <0x84000009>;
++		sys_poweroff = <0x84000008>;
++
++		sd-vqsw = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
++		sd-vmmc = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
++	};
++
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+@@ -369,8 +378,7 @@ &uart_A {
+ 
+ 	bluetooth {
+ 		compatible = "realtek,rtl8822cs-bt";
+-		enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+-		host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
++		enable-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+ 		device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
+ 	};
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-bananapi-m2s.patch b/patch/kernel/archive/meson64-6.10/board-bananapi-m2s.patch
new file mode 100644
index 000000000000..2ee977f5c7ed
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-bananapi-m2s.patch
@@ -0,0 +1,62 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@armbian.com>
+Date: Tue, 25 Jul 2023 13:34:18 -0400
+Subject: arch: arm64: dts: amlogic: meson g12b bananapi m2s
+
+Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts | 4 ++++
+ arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi          | 9 +++++++++
+ arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts | 4 ++++
+ 3 files changed, 17 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts
+@@ -18,6 +18,10 @@ aliases {
+ 	};
+ };
+ 
++&reboot {
++	sd-vqen = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
++};
++
+ /* Camera (CSI) bus */
+ &i2c1 {
+ 	status = "okay";
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
+@@ -17,6 +17,15 @@ aliases {
+ 		rtc1 = &vrtc;
+ 	};
+ 
++	reboot: meson64-reboot {
++		compatible = "meson64,reboot";
++		sys_reset = <0x84000009>;
++		sys_poweroff = <0x84000008>;
++
++		sd-vqsw = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
++		sd-vmmc = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
++	};
++
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts
+@@ -12,3 +12,7 @@ / {
+ 	compatible = "bananapi,bpi-m2s", "amlogic,s922x", "amlogic,g12b";
+ 	model = "BananaPi M2S";
+ };
++
++&reboot {
++	sd-vqen = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-bananapim5-001-sd-use-270-mmc-clock-phase-via-dt.patch b/patch/kernel/archive/meson64-6.10/board-bananapim5-001-sd-use-270-mmc-clock-phase-via-dt.patch
new file mode 100644
index 000000000000..a7fc8f521eca
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-bananapim5-001-sd-use-270-mmc-clock-phase-via-dt.patch
@@ -0,0 +1,45 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igor.pecovnik@gmail.com>
+Date: Sat, 11 Feb 2023 18:30:00 +0100
+Subject: BananaPi M5: 270 clock phase, via amlogic,mmc-phase
+
+Rework of Ricardo Pardini <ricardo@pardini.net> patch.
+
+Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/input/linux-event-codes.h>
+ #include <dt-bindings/gpio/meson-g12a-gpio.h>
++#include <dt-bindings/mmc/meson-gx-mmc.h>
+ 
+ / {
+ 	adc-keys {
+@@ -394,6 +395,8 @@ &sd_emmc_b {
+ 	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ 	vmmc-supply = <&tflash_vdd>;
+ 	vqmmc-supply = <&vddio_c>;
++
++	amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
+ };
+ 
+ /* eMMC */
+@@ -413,6 +416,8 @@ &sd_emmc_c {
+ 	mmc-pwrseq = <&emmc_pwrseq>;
+ 	vmmc-supply = <&vddao_3v3>;
+ 	vqmmc-supply = <&emmc_1v8>;
++
++	amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
+ };
+ 
+ &uart_AO {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-bananapim5-002-add-wifi-bt-support.patch b/patch/kernel/archive/meson64-6.10/board-bananapim5-002-add-wifi-bt-support.patch
new file mode 100644
index 000000000000..66db01e2cdb3
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-bananapim5-002-add-wifi-bt-support.patch
@@ -0,0 +1,112 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Wed, 2 Aug 2023 19:36:07 -0400
+Subject: arch: arm64: dts: amlogic: add wifi/bt support to bananapi m5
+
+The BPI-M5 has an optional RTL8822CS WiFi/BT mezzanine board. Describe
+the board but mark the sd_emmc_a and uart_A nodes disabled so they can
+be enabled via overlay or fdtput when the board is connected.
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts | 66 +++++++++-
+ 1 file changed, 65 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts
+@@ -25,6 +25,20 @@ cvbs_connector_in: endpoint {
+ 		};
+ 	};
+ 
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
++		clocks = <&wifi32k>;
++		clock-names = "ext_clock";
++	};
++
++	wifi32k: wifi32k {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++		pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
++	};
++
+ 	sound {
+ 		compatible = "amlogic,axg-sound-card";
+ 		model = "BPI-M5";
+@@ -149,7 +163,6 @@ &acodec {
+ 	status = "okay";
+ };
+ 
+-
+ &clkc_audio {
+ 	status = "okay";
+ };
+@@ -172,6 +185,42 @@ &frddr_c {
+ 	status = "okay";
+ };
+ 
++&pwm_ef {
++	status = "okay";
++	pinctrl-0 = <&pwm_e_pins>;
++	pinctrl-names = "default";
++};
++
++/* SDIO */
++&sd_emmc_a {
++	/* enable if WiFi/BT board connected */
++	status = "disabled";
++	pinctrl-0 = <&sdio_pins>;
++	pinctrl-1 = <&sdio_clk_gate_pins>;
++	pinctrl-names = "default", "clk-gate";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	bus-width = <4>;
++	sd-uhs-sdr104;
++	max-frequency = <50000000>;
++
++	non-removable;
++	disable-wp;
++
++	/* WiFi firmware requires power in suspend */
++	keep-power-in-suspend;
++
++	mmc-pwrseq = <&sdio_pwrseq>;
++
++	vmmc-supply = <&vddao_3v3>;
++	vqmmc-supply = <&vddao_1v8>;
++
++	rtl8822cs: wifi@1 {
++		reg = <1>;
++	};
++};
++
+ &tdmif_b {
+ 	status = "okay";
+ };
+@@ -219,3 +268,18 @@ &toddr_b {
+ &toddr_c {
+ 	status = "okay";
+ };
++
++&uart_A {
++	/* enable if WiFi/BT board connected */
++	status = "disabled";
++	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
++	pinctrl-names = "default";
++	uart-has-rtscts;
++
++	bluetooth {
++		compatible = "realtek,rtl8822cs-bt";
++		enable-gpios  = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
++		host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
++		device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
++	};
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-bananapism1-add-uart_A-and-AO_B.patch b/patch/kernel/archive/meson64-6.10/board-bananapism1-add-uart_A-and-AO_B.patch
new file mode 100644
index 000000000000..c3b48d2eb9ec
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-bananapism1-add-uart_A-and-AO_B.patch
@@ -0,0 +1,85 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Thu, 21 Sep 2023 07:46:59 -0400
+Subject: arm64: dts: amlogic: meson-sm1-bananapi: add uart A and AO_B
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi         |  9 +++++++++
+ arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts | 10 ++++++++++
+ arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi       |  7 +++++++
+ 3 files changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+@@ -1919,6 +1919,15 @@ mux {
+ 						};
+ 					};
+ 
++					uart_ao_b_pins: uart-b-ao {
++						mux {
++							groups = "uart_ao_b_tx_8",
++								 "uart_ao_b_rx_9";
++							function = "uart_ao_b";
++							bias-disable;
++						};
++					};
++
+ 					uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
+ 						mux {
+ 							groups = "uart_ao_a_cts",
+diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts
+@@ -13,6 +13,10 @@ / {
+ 	compatible = "bananapi,bpi-m2-pro", "amlogic,sm1";
+ 	model = "Banana Pi BPI-M2-PRO";
+ 
++	aliases {
++		serial1 = &uart_A;
++	};
++
+ 	sound {
+ 		compatible = "amlogic,axg-sound-card";
+ 		model = "BPI-M2-PRO";
+@@ -95,3 +99,9 @@ &tdmout_b {
+ &tohdmitx {
+ 	status = "okay";
+ };
++
++&uart_A {
++	status = "disabled";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart_a_pins>;
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
+@@ -26,6 +26,7 @@ button-sw3 {
+ 
+ 	aliases {
+ 		serial0 = &uart_AO;
++		serial4 = &uart_AO_B;
+ 		ethernet0 = &ethmac;
+ 	};
+ 
+@@ -426,6 +427,12 @@ &uart_AO {
+ 	pinctrl-names = "default";
+ };
+ 
++&uart_AO_B {
++	status = "disabled";
++	pinctrl-0 = <&uart_ao_b_pins>;
++	pinctrl-names = "default";
++};
++
+ &usb {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-khadas-vim3-fix-missing-i2c3-nod.patch b/patch/kernel/archive/meson64-6.10/board-khadas-vim3-fix-missing-i2c3-nod.patch
new file mode 100644
index 000000000000..46cf86cb4ac0
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-khadas-vim3-fix-missing-i2c3-nod.patch
@@ -0,0 +1,37 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Fri, 21 Feb 2020 04:43:22 +0000
+Subject: WIP: arm64: dts: meson: khadas-vim3: fix missing i2c3 node
+
+Fixes: c6d29c66e582 ("arm64: dts: meson-g12b-khadas-vim3: add initial device-tree")
+
+The i2c3 node was missed in the original device-tree and is required for the
+optional Khadas 3705 fan to work.
+
+Suggested-by: Art Nikpal <email2tema@gmail.com>
+Signed-off-by: Christian Hewittt <christianshewitt@gmail.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
+@@ -332,6 +332,13 @@ hdmi_tx_tmds_out: endpoint {
+ 	};
+ };
+ 
++&i2c3 {
++	clock-frequency = <100000>;
++	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &i2c_AO {
+ 	status = "okay";
+ 	pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-khadas-vims-add-rtc-vrtc-aliases.patch b/patch/kernel/archive/meson64-6.10/board-khadas-vims-add-rtc-vrtc-aliases.patch
new file mode 100644
index 000000000000..173fa7e50956
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-khadas-vims-add-rtc-vrtc-aliases.patch
@@ -0,0 +1,58 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Thu, 21 Jan 2021 01:35:36 +0000
+Subject: HACK: arm64: dts: meson: add rtc/vrtc aliases to Khadas VIM
+
+Add aliases to ensure the vrtc time (which normally proves first) is /dev/rtc1
+while the onboard rtc chip claims /dev/rtc0.
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+@@ -29,6 +29,8 @@ button-function {
+ 	aliases {
+ 		serial2 = &uart_AO_B;
+ 		ethernet0 = &ethmac;
++		rtc0 = &rtc;
++		rtc1 = &vrtc;
+ 	};
+ 
+ 	gpio-keys-polled {
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Sat, 6 Nov 2021 13:01:08 +0000
+Subject: HACK: arm64: dts: meson: add rtc/vrtc aliases to Khadas VIM2
+
+Add aliases to ensure the vrtc time (which normally proves first) is /dev/rtc1
+while the onboard rtc chip claims /dev/rtc0.
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+@@ -18,6 +18,8 @@ / {
+ 	aliases {
+ 		serial0 = &uart_AO;
+ 		serial2 = &uart_AO_B;
++		rtc0 = &rtc;
++		rtc1 = &vrtc;
+ 	};
+ 
+ 	chosen {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-nanopi-k2-add-uartC-alias.patch b/patch/kernel/archive/meson64-6.10/board-nanopi-k2-add-uartC-alias.patch
new file mode 100644
index 000000000000..f0e9918bd7db
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-nanopi-k2-add-uartC-alias.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Ayotte <martinayotte@yahoo.ca>
+Date: Thu, 6 Dec 2018 18:03:17 -0500
+Subject: add uartC alias for nanopi-k2
+
+add uartC alias for nanopi-k2
+- 839f2f151073928ed1e62d415ba5317f525b9e24: 1553615840: Martin Ayotte <martinayotte@yahoo.ca>: 'add uartA overlay for Odroid-C2'
+---
+ arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+@@ -15,6 +15,7 @@ / {
+ 
+ 	aliases {
+ 		serial0 = &uart_AO;
++		serial2 = &uart_C;
+ 		ethernet0 = &ethmac;
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-nanopi-k2-enable-emmc.patch b/patch/kernel/archive/meson64-6.10/board-nanopi-k2-enable-emmc.patch
new file mode 100644
index 000000000000..1ca16d7ef26b
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-nanopi-k2-enable-emmc.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igor.pecovnik@gmail.com>
+Date: Tue, 4 Jun 2019 21:35:48 +0200
+Subject: nanopik2 - enable eMMC
+
+[ nanopik2 ] enable eMMC support for u-boot and kernel
+---
+ arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+@@ -358,7 +358,7 @@ &sd_emmc_b {
+ 
+ /* eMMC */
+ &sd_emmc_c {
+-	status = "disabled";
++	status = "okay";
+ 	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ 	pinctrl-1 = <&emmc_clk_gate_pins>;
+ 	pinctrl-names = "default", "clk-gate";
+@@ -368,8 +368,6 @@ &sd_emmc_c {
+ 	non-removable;
+ 	disable-wp;
+ 	cap-mmc-highspeed;
+-	mmc-ddr-1_8v;
+-	mmc-hs200-1_8v;
+ 
+ 	mmc-pwrseq = <&emmc_pwrseq>;
+ 	vmmc-supply = <&vcc3v3>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-odroidc2-add-uartA-uartC.patch b/patch/kernel/archive/meson64-6.10/board-odroidc2-add-uartA-uartC.patch
new file mode 100644
index 000000000000..9388fecc5d67
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-odroidc2-add-uartA-uartC.patch
@@ -0,0 +1,50 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Ayotte <martinayotte@yahoo.ca>
+Date: Thu, 26 Oct 2017 16:31:22 +0300
+Subject: add uartA and uartC for Odroid-C2
+
+add uartA and uartC for Odroid-C2
+
+- 839f2f151073928ed1e62d415ba5317f525b9e24: Martin Ayotte <martinayotte@yahoo.ca>: 'add uartA overlay for Odroid-C2'
+- b5c9e6ee8d4a97c5092109a12164c131eb4b46e9: Martin Ayotte <martinayotte@yahoo.ca>: 'add uartA for odroidc2 in NEXT'
+- 22ca2b92a002fe22e2a61428741618295c424664: Martin Ayotte <martinayotte@yahoo.ca>: 'fix missing pinctrl-0 for ODroidC2 uartA'
+- 140da6ad43f4a0d47c221271f62bb7c0a57064ea: Martin Ayotte <martinayotte@yahoo.ca>: 'add uartC to OdroidC2'
+---
+ arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 14 ++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+@@ -17,6 +17,8 @@ / {
+ 
+ 	aliases {
+ 		serial0 = &uart_AO;
++		serial1 = &uart_A;
++		serial2 = &uart_C;
+ 		ethernet0 = &ethmac;
+ 	};
+ 
+@@ -383,6 +385,18 @@ &uart_AO {
+ 	pinctrl-names = "default";
+ };
+ 
++&uart_A {
++	status = "disabled";
++	pinctrl-0 = <&uart_a_pins>;
++	pinctrl-names = "default";
++};
++
++&uart_C {
++	status = "disabled";
++	pinctrl-0 = <&uart_c_pins>;
++	pinctrl-names = "default";
++};
++
+ &usb0_phy {
+ 	status = "disabled";
+ 	phy-supply = <&usb_otg_pwr>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-odroidc2-enable-SPI.patch b/patch/kernel/archive/meson64-6.10/board-odroidc2-enable-SPI.patch
new file mode 100644
index 000000000000..7c070a0abae3
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-odroidc2-enable-SPI.patch
@@ -0,0 +1,52 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Thomas McKahan <tonymckahan@gmail.com>
+Date: Sat, 6 Oct 2018 22:50:14 -0400
+Subject: Odroid C2 enable SPI
+
+Odroid C2 enable SPI
+
+- f928b31d8a1983fd8cfd9c97de084e532283b106: 1543550719: Thomas McKahan <tonymckahan@gmail.com>: '[ meson64-dev ] fix Odroid C2 boot, add spidev'
+---
+ arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 26 ++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+@@ -176,6 +176,32 @@ hdmi_connector_in: endpoint {
+ 		};
+ 	};
+ 
++	spi-gpio {
++		compatible = "spi-gpio";
++		#address-cells = <0x1>;
++		#size-cells = <0x0>;
++		ranges;
++		status = "disabled";
++		sck-gpios  = <&gpio GPIOX_2 0>;
++		miso-gpios = <&gpio GPIOX_4 0>;
++		mosi-gpios = <&gpio GPIOX_7 0>;
++		cs-gpios  = <&gpio GPIOX_3 0
++			     &gpio GPIOX_1 0>;
++		num-chipselects = <2>;
++
++		/* clients */
++		spidev0@0 {
++			compatible = "armbian,spi-dev";
++			reg = <0>;
++			spi-max-frequency = <500000>;
++		};
++		spidev0@1 {
++			compatible = "armbian,spi-dev";
++			reg = <1>;
++			spi-max-frequency = <500000>;
++		};
++	};
++
+ 	sound {
+ 		compatible = "amlogic,gx-sound-card";
+ 		model = "ODROID-C2";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-odroidc2-enable-scpi-dvfs.patch b/patch/kernel/archive/meson64-6.10/board-odroidc2-enable-scpi-dvfs.patch
new file mode 100644
index 000000000000..be0dc2ae930f
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-odroidc2-enable-scpi-dvfs.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: zador-blood-stained <zador-blood-stained@users.noreply.github.com>
+Date: Thu, 26 Oct 2017 16:31:22 +0300
+Subject: Enable odroidc2-dev DVFS
+
+Enable odroidc2-dev DVFS (#763)
+---
+ arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+@@ -360,7 +360,8 @@ &saradc {
+ };
+ 
+ &scpi_clocks {
+-	status = "disabled";
++	/* Works only with new blobs that have limited DVFS table */
++	status = "okay";
+ };
+ 
+ /* SD */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-odroidc2-usb-hub-disable-autosuspend-for-Genesys-Logic-.patch b/patch/kernel/archive/meson64-6.10/board-odroidc2-usb-hub-disable-autosuspend-for-Genesys-Logic-.patch
new file mode 100644
index 000000000000..10907691e923
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-odroidc2-usb-hub-disable-autosuspend-for-Genesys-Logic-.patch
@@ -0,0 +1,33 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Mon, 3 Jan 2022 10:44:17 +0000
+Subject: LOCAL: usb: hub: disable autosuspend for Genesys Logic Hubs
+
+Disable autosuspend in Genesys Logic hubs to allow USB devices on the
+Odroid C2 board to be used. The alternative to this patch is setting
+usbcore.autosuspend=-1 in boot params.
+
+This patch only impacts GXBB devices as GXL/GXM onwards use the newer
+dwc3 core which does not have the problem.
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+---
+ drivers/usb/core/hub.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
+index 111111111111..222222222222 100644
+--- a/drivers/usb/core/hub.c
++++ b/drivers/usb/core/hub.c
+@@ -5965,7 +5965,7 @@ static const struct usb_device_id hub_id_table[] = {
+ 			| USB_DEVICE_ID_MATCH_INT_CLASS,
+       .idVendor = USB_VENDOR_GENESYS_LOGIC,
+       .bInterfaceClass = USB_CLASS_HUB,
+-      .driver_info = HUB_QUIRK_CHECK_PORT_AUTOSUSPEND},
++      .driver_info = HUB_QUIRK_DISABLE_AUTOSUSPEND},
+     { .match_flags = USB_DEVICE_ID_MATCH_VENDOR
+ 			| USB_DEVICE_ID_MATCH_PRODUCT,
+       .idVendor = USB_VENDOR_TEXAS_INSTRUMENTS,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-odroidc4-reset.patch b/patch/kernel/archive/meson64-6.10/board-odroidc4-reset.patch
new file mode 100644
index 000000000000..8ad61c277cc6
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-odroidc4-reset.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ash Hughes <spirit.returned@gmail.com>
+Date: Sat, 18 Feb 2023 07:46:38 -0300
+Subject: adapted meson64-reboot driver, fix reboot on odroid C4 when using
+ UHS-II SD cards
+
+bring back fixed version of `odroid-reboot` driver (Fix reboot on odroid C4 when using UHS-II SD cards)
+---
+ arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
+@@ -11,6 +11,16 @@ / {
+ 	compatible = "hardkernel,odroid-c4", "amlogic,sm1";
+ 	model = "Hardkernel ODROID-C4";
+ 
++	meson64-reboot {
++		compatible = "meson64,reboot";
++		sys_reset = <0x84000009>;
++		sys_poweroff = <0x84000008>;
++
++		sd-vqen = <&gpio_ao GPIOE_2 GPIO_ACTIVE_HIGH>;
++		sd-vqsw = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>;
++		sd-vmmc = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-odroidhc4-enable-fan1_input.patch b/patch/kernel/archive/meson64-6.10/board-odroidhc4-enable-fan1_input.patch
new file mode 100644
index 000000000000..26720cb2eb82
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-odroidhc4-enable-fan1_input.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ricardo Pardini <ricardo@pardini.net>
+Date: Sun, 26 Jun 2022 03:47:06 +0200
+Subject: ODROID-HC4: add DT attributes to enable fan1_input
+
+- from vendor kernel modified DT
+- this allows userspace fancontrol/pwmconfig to work
+---
+ arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
+@@ -21,6 +21,10 @@ fan0: pwm-fan {
+ 		#cooling-cells = <2>;
+ 		cooling-levels = <0 120 170 220>;
+ 		pwms = <&pwm_cd 1 40000 0>;
++		fan-supply = <&vcc_5v>;
++		interrupt-parent = <&gpio_intc>;
++		interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
++		pulses-per-revolutions = <2>;
+ 	};
+ 
+ 	leds {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-odroidn2plus-Add-missing-CPU-opp.patch b/patch/kernel/archive/meson64-6.10/board-odroidn2plus-Add-missing-CPU-opp.patch
new file mode 100644
index 000000000000..d6511912b49c
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-odroidn2plus-Add-missing-CPU-opp.patch
@@ -0,0 +1,46 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igor.pecovnik@gmail.com>
+Date: Wed, 10 Feb 2021 18:07:08 +0100
+Subject: Add missing CPU opp values for clocking g12b / N2+ higher
+
+Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi | 16 ++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
+@@ -45,6 +45,14 @@ opp-1800000000 {
+ 			opp-hz = /bits/ 64 <1800000000>;
+ 			opp-microvolt = <1001000>;
+ 		};
++		opp-1908000000 {
++			opp-hz = /bits/ 64 <1908000000>;
++			opp-microvolt = <1030000>;
++		};
++		opp-2016000000 {
++			opp-hz = /bits/ 64 <2016000000>;
++			opp-microvolt = <1040000>;
++		};
+ 	};
+ 
+ 	cpub_opp_table_1: opp-table-1 {
+@@ -105,5 +113,13 @@ opp-2208000000 {
+                         opp-hz = /bits/ 64 <2208000000>;
+                         opp-microvolt = <1011000>;
+                 };
++		opp-2304000000 {
++			opp-hz = /bits/ 64 <2304000000>;
++			opp-microvolt = <1030000>;
++		};
++		opp-2400000000 {
++			opp-hz = /bits/ 64 <2400000000>;
++			opp-microvolt = <1040000>;
++		};
+ 	};
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-radxa-zero-dts-add-aliases-for-serial-i2c-and-spi.patch b/patch/kernel/archive/meson64-6.10/board-radxa-zero-dts-add-aliases-for-serial-i2c-and-spi.patch
new file mode 100644
index 000000000000..720442f1255a
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-radxa-zero-dts-add-aliases-for-serial-i2c-and-spi.patch
@@ -0,0 +1,36 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Tue, 24 Oct 2023 08:17:17 -0400
+Subject: arm64: dts: Radxa Zero: set aliases for serial, i2c and spi
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts | 12 ++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
+@@ -15,6 +15,18 @@ / {
+ 
+ 	aliases {
+ 		serial0 = &uart_AO;
++		serial1 = &uart_AO_B;
++		serial2 = &uart_A;
++		serial3 = &uart_B;
++		serial4 = &uart_C;
++		i2c0 = &i2c0;
++		i2c1 = &i2c1;
++		i2c2 = &i2c2;
++		i2c3 = &i2c3;
++		i2c4 = &i2c_AO;
++		spi0 = &spicc0;
++		spi1 = &spicc1;
++		spi2 = &spifc;
+ 	};
+ 
+ 	chosen {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch b/patch/kernel/archive/meson64-6.10/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch
new file mode 100644
index 000000000000..291b3494922d
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch
@@ -0,0 +1,104 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Tue, 17 Aug 2021 16:16:43 +0000
+Subject: arm64: dts: meson: radxa-zero: add support for the usb type-c
+ controller
+
+Radxa Zero uses an FUSB302 type-c controller, so lets enable it.
+
+NB: Polarity swapping via GPIO is not implemented in the current driver
+(see drivers/usb/typec/tcpm/fusb302.c) so it is not possible to handle
+GPIOAO_6 for USB3 polarity control.
+
+Includes:
+- arm64: dts: amlogic: fix interrupt storm from fusb302 on Radxa Zero
+  it makes load average >1. use correct pin for interrupt from fusb302.
+
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+Signed-off-by: Yuntian Zhang <yt@radxa.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts | 48 ++++++++++
+ 1 file changed, 48 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
+@@ -72,6 +72,14 @@ sdio_pwrseq: sdio-pwrseq {
+ 		clock-names = "ext_clock";
+ 	};
+ 
++	typec2_vbus: regulator-typec2_vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "TYPEC2_VBUS";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&ao_5v>;
++	};
++
+ 	ao_5v: regulator-ao-5v {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "AO_5V";
+@@ -202,6 +210,18 @@ wifi32k: wifi32k {
+ 	};
+ };
+ 
++&ao_pinctrl {
++	/* Ensure the TYPE C controller irq pin is not driven by the SoC */
++	fusb302_irq_pins: fusb302_irq {
++		mux {
++			groups = "GPIOAO_5";
++			function = "gpio_aobus";
++			bias-pull-up;
++			output-disable;
++		};
++	};
++};
++
+ &arb {
+ 	status = "okay";
+ };
+@@ -289,6 +309,26 @@ &ir {
+ 	pinctrl-names = "default";
+ };
+ 
++&i2c3 {
++	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	fusb302@22 {
++		compatible = "fcs,fusb302";
++		reg = <0x22>;
++
++		pinctrl-0 = <&fusb302_irq_pins>;
++		pinctrl-names = "default";
++		interrupt-parent = <&gpio_intc>;
++		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
++
++		vbus-supply = <&typec2_vbus>;
++
++		status = "okay";
++	};
++};
++
+ &pwm_AO_cd {
+ 	pinctrl-0 = <&pwm_ao_d_e_pins>;
+ 	pinctrl-names = "default";
+@@ -413,3 +453,11 @@ &uart_AO {
+ &usb {
+ 	status = "okay";
+ };
++
++&usb2_phy0 {
++	phy-supply = <&typec2_vbus>;
++};
++
++&usb3_pcie_phy {
++	phy-supply = <&typec2_vbus>;
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch b/patch/kernel/archive/meson64-6.10/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch
new file mode 100644
index 000000000000..d7aea9f2b106
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Yuntian Zhang <yt@radxa.com>
+Date: Mon, 27 Jun 2022 15:06:32 +0800
+Subject: VENDOR: Radxa Zero Wi-Fi fix
+
+Credit: pyavitz from Armbian
+
+Signed-off-by: Yuntian Zhang <yt@radxa.com>
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
+@@ -361,7 +361,7 @@ &sd_emmc_a {
+ 
+ 	bus-width = <4>;
+ 	cap-sd-highspeed;
+-	sd-uhs-sdr50;
++	cap-mmc-highspeed;
+ 	max-frequency = <100000000>;
+ 
+ 	non-removable;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/board-t95z-add-rc-remote-keymap.patch b/patch/kernel/archive/meson64-6.10/board-t95z-add-rc-remote-keymap.patch
new file mode 100644
index 000000000000..6c1722129a90
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/board-t95z-add-rc-remote-keymap.patch
@@ -0,0 +1,153 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Mon, 13 Feb 2023 11:38:16 +0000
+Subject: add rc keymaps for Sunvell T95Z Plus
+
+WIP: media: rc: add keymap for Sunvell T95Z Plus
+WIP: dt-bindings: media: rc: add rc-sunvell-t95z-plus
+Add a binding for the rc-sunvell-t95z-plus remote keymap
+WIP: dt-bindings: add sunvell vendor prefix
+Add vendor prefix for Shenzhen Sunvell Electronics Co., Ltd
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+---
+ Documentation/devicetree/bindings/media/rc.yaml        |  1 +
+ Documentation/devicetree/bindings/vendor-prefixes.yaml |  2 +
+ drivers/media/rc/keymaps/Makefile                      |  1 +
+ drivers/media/rc/keymaps/rc-sunvell-t95z-plus.c        | 75 ++++++++++
+ include/media/rc-map.h                                 |  1 +
+ 5 files changed, 80 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/media/rc.yaml b/Documentation/devicetree/bindings/media/rc.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/media/rc.yaml
++++ b/Documentation/devicetree/bindings/media/rc.yaml
+@@ -127,6 +127,7 @@ properties:
+       - rc-reddo
+       - rc-snapstream-firefly
+       - rc-streamzap
++      - rc-sunvell-t95z-plus
+       - rc-su3000
+       - rc-tanix-tx3mini
+       - rc-tanix-tx5max
+diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
+@@ -1411,6 +1411,8 @@ patternProperties:
+     description: Sundance DSP Inc.
+   "^sunplus,.*":
+     description: Sunplus Technology Co., Ltd.
++  "^sunvell,.*":
++    description: Shenzhen Sunvell Electronics Co., Ltd
+   "^SUNW,.*":
+     description: Sun Microsystems, Inc
+   "^supermicro,.*":
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -107,6 +107,7 @@ obj-$(CONFIG_RC_MAP) += \
+ 			rc-reddo.o \
+ 			rc-snapstream-firefly.o \
+ 			rc-streamzap.o \
++			rc-sunvell-t95z-plus.o \
+ 			rc-su3000.o \
+ 			rc-tanix-tx3mini.o \
+ 			rc-tanix-tx5max.o \
+diff --git a/drivers/media/rc/keymaps/rc-sunvell-t95z-plus.c b/drivers/media/rc/keymaps/rc-sunvell-t95z-plus.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-sunvell-t95z-plus.c
+@@ -0,0 +1,75 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com
++ */
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++/*
++ * Keytable for Sunvell T95Z Plus remote control
++ *
++ */
++
++static struct rc_map_table sunvell_t95z_plus[] = {
++	{ 0xdf1c, KEY_POWER },
++	// TV CONTROLS
++
++	{ 0xdf4b, KEY_PREVIOUS },
++	{ 0xdf01, KEY_SCREEN }, // TV
++	{ 0xdf5d, KEY_VOLUMEUP },
++
++	{ 0xdf4f, KEY_NEXT },
++	{ 0xdf5f, KEY_FAVORITES }, // KODI
++	{ 0xdf5c, KEY_VOLUMEDOWN },
++
++	{ 0xdf42, KEY_HOME },
++	{ 0xdf0a, KEY_BACK },
++
++	{ 0xdf1a, KEY_UP },
++	{ 0xdf47, KEY_LEFT },
++	{ 0xdf06, KEY_ENTER },
++	{ 0xdf07, KEY_RIGHT },
++	{ 0xdf48, KEY_DOWN },
++
++	{ 0xdf03, KEY_INFO }, // MOUSE
++	{ 0xdf18, KEY_MENU },
++
++	{ 0xdf54, KEY_1 },
++	{ 0xdf16, KEY_2 },
++	{ 0xdf15, KEY_3 },
++	{ 0xdf50, KEY_4 },
++	{ 0xdf12, KEY_5 },
++	{ 0xdf11, KEY_6 },
++	{ 0xdf4c, KEY_7 },
++	{ 0xdf0e, KEY_8 },
++	{ 0xdf0d, KEY_9 },
++	{ 0xdf41, KEY_WWW }, // WORLD
++	{ 0xdf0c, KEY_0 },
++	{ 0xdf10, KEY_DELETE },
++};
++
++static struct rc_map_list sunvell_t95z_plus_map = {
++	.map = {
++		.scan     = sunvell_t95z_plus,
++		.size     = ARRAY_SIZE(sunvell_t95z_plus),
++		.rc_proto = RC_PROTO_NEC,
++		.name     = RC_MAP_SUNVELL_T95Z_PLUS,
++	}
++};
++
++static int __init init_rc_map_sunvell_t95z_plus(void)
++{
++	return rc_map_register(&sunvell_t95z_plus_map);
++}
++
++static void __exit exit_rc_map_sunvell_t95z_plus(void)
++{
++	rc_map_unregister(&sunvell_t95z_plus_map);
++}
++
++module_init(init_rc_map_sunvell_t95z_plus)
++module_exit(exit_rc_map_sunvell_t95z_plus)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Christian Hewitt <christianshewitt@gmail.com>");
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index 111111111111..222222222222 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -314,6 +314,7 @@ struct rc_map *rc_map_get(const char *name);
+ #define RC_MAP_REDDO                     "rc-reddo"
+ #define RC_MAP_SNAPSTREAM_FIREFLY        "rc-snapstream-firefly"
+ #define RC_MAP_STREAMZAP                 "rc-streamzap"
++#define RC_MAP_SUNVELL_T95Z_PLUS         "rc-sunvell-t95z-plus"
+ #define RC_MAP_SU3000                    "rc-su3000"
+ #define RC_MAP_TANIX_TX3MINI             "rc-tanix-tx3mini"
+ #define RC_MAP_TANIX_TX5MAX              "rc-tanix-tx5max"
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/driver-power-meson64-reset.patch b/patch/kernel/archive/meson64-6.10/driver-power-meson64-reset.patch
new file mode 100644
index 000000000000..7197289a5f33
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/driver-power-meson64-reset.patch
@@ -0,0 +1,236 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@gmail.com>
+Date: Thu, 1 Jun 2023 06:32:23 +0200
+Subject: pyavitz meson64-generalized `odroid-reboot` driver
+
+---
+ drivers/power/reset/Kconfig          |   7 +
+ drivers/power/reset/Makefile         |   1 +
+ drivers/power/reset/meson64-reboot.c | 186 ++++++++++
+ 3 files changed, 194 insertions(+)
+
+diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/power/reset/Kconfig
++++ b/drivers/power/reset/Kconfig
+@@ -148,6 +148,13 @@ config POWER_RESET_ODROID_GO_ULTRA_POWEROFF
+ 	help
+ 	  This driver supports Power off for Odroid Go Ultra device.
+ 
++config POWER_RESET_MESON64
++	bool "Meson64 reboot/power-off driver"
++	depends on ARCH_MESON
++	help
++	  The driver supports restart / power off for amlogic
++	  g12a, g12b and sm1 SoCs
++
+ config POWER_RESET_PIIX4_POWEROFF
+ 	tristate "Intel PIIX4 power-off driver"
+ 	depends on PCI
+diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/power/reset/Makefile
++++ b/drivers/power/reset/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
+ obj-$(CONFIG_POWER_RESET_LINKSTATION) += linkstation-poweroff.o
+ obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
+ obj-$(CONFIG_POWER_RESET_MT6323) += mt6323-poweroff.o
++obj-$(CONFIG_POWER_RESET_MESON64) += meson64-reboot.o
+ obj-$(CONFIG_POWER_RESET_QCOM_PON) += qcom-pon.o
+ obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o
+ obj-$(CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF) += odroid-go-ultra-poweroff.o
+diff --git a/drivers/power/reset/meson64-reboot.c b/drivers/power/reset/meson64-reboot.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/power/reset/meson64-reboot.c
+@@ -0,0 +1,186 @@
++// SPDX-License-Identifier: (GPL-2.0)
++/*
++ * drivers/power/reset/meson64-reboot.c
++ *
++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
++ * Copyright (C) 2023 Ash Hughes (sehguh.hsa@gmail.com)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ */
++
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/module.h>
++#include <linux/reboot.h>
++
++#include <asm/system_misc.h>
++
++#include <asm/compiler.h>
++#include <linux/kdebug.h>
++#include <linux/arm-smccc.h>
++
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++
++int sd_vqsw;
++int sd_vmmc;
++int sd_vqen;
++
++static u32 psci_function_id_restart;
++static u32 psci_function_id_poweroff;
++
++#define CHECK_RET(ret) { \
++	if (ret) \
++	pr_err("[%s] gpio op failed(%d) at line %d\n",\
++			__func__, ret, __LINE__); \
++}
++
++static noinline int __invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
++					 u64 arg2)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc((unsigned long)function_id,
++			(unsigned long)arg0,
++			(unsigned long)arg1,
++			(unsigned long)arg2,
++			0, 0, 0, 0, &res);
++	return res.a0;
++}
++
++void meson64_card_reset(void)
++{
++	int ret = 0;
++
++	if ((sd_vqsw == 0) && (sd_vmmc == 0))
++		return;
++
++	if (sd_vqen == 0) {
++		gpio_free(sd_vqsw);
++		gpio_free(sd_vmmc);
++		ret = gpio_request_one(sd_vqsw,
++				GPIOF_OUT_INIT_LOW, "REBOOT");
++		CHECK_RET(ret);
++		mdelay(10);
++		ret = gpio_direction_output(sd_vqsw, 1);
++		CHECK_RET(ret);
++		ret = gpio_request_one(sd_vmmc,
++				GPIOF_OUT_INIT_LOW, "REBOOT");
++		CHECK_RET(ret);
++		mdelay(10);
++		ret = gpio_direction_output(sd_vqsw, 0);
++		CHECK_RET(ret);
++		ret = gpio_direction_output(sd_vmmc, 1);
++		CHECK_RET(ret);
++		mdelay(5);
++		gpio_free(sd_vqsw);
++		gpio_free(sd_vmmc);
++	} else {
++		gpio_free(sd_vqsw);
++		gpio_free(sd_vqen);
++		gpio_free(sd_vmmc);
++
++		ret = gpio_request_one(sd_vqsw,
++				GPIOF_OUT_INIT_LOW, "REBOOT");
++		CHECK_RET(ret);
++		ret = gpio_request_one(sd_vqen,
++				GPIOF_OUT_INIT_LOW, "REBOOT");
++		CHECK_RET(ret);
++		ret = gpio_request_one(sd_vmmc,
++				GPIOF_OUT_INIT_LOW, "REBOOT");
++		CHECK_RET(ret);
++		mdelay(100);
++		ret = gpio_direction_input(sd_vqen);
++		CHECK_RET(ret);
++		ret = gpio_direction_input(sd_vmmc);
++		CHECK_RET(ret);
++		ret = gpio_direction_input(sd_vqsw);
++		CHECK_RET(ret);
++		mdelay(5);
++		gpio_free(sd_vqen);
++		gpio_free(sd_vmmc);
++		gpio_free(sd_vqsw);
++	}
++}
++
++static int do_meson64_restart(struct notifier_block *this, unsigned long mode, void *cmd)
++{
++	meson64_card_reset();
++	return NOTIFY_DONE;
++}
++
++static struct notifier_block meson64_restart_handler = {
++	.notifier_call = do_meson64_restart,
++	.priority = 130,
++};
++
++static void do_meson64_poweroff(void)
++{
++	meson64_card_reset();
++
++	__invoke_psci_fn_smc(0x82000042, 1, 0, 0);
++}
++
++static int meson64_restart_probe(struct platform_device *pdev)
++{
++	struct device_node *of_node;
++	u32 id;
++
++	if (!of_property_read_u32(pdev->dev.of_node, "sys_reset", &id)) {
++		psci_function_id_restart = id;
++		register_restart_handler(&meson64_restart_handler);
++	}
++
++	if (!of_property_read_u32(pdev->dev.of_node, "sys_poweroff", &id)) {
++		psci_function_id_poweroff = id;
++		pm_power_off = do_meson64_poweroff;
++	}
++
++	of_node = pdev->dev.of_node;
++
++	sd_vqsw = of_get_named_gpio(of_node, "sd-vqsw", 0);
++	if (!gpio_is_valid(sd_vqsw)) sd_vqsw = 0;
++
++	sd_vmmc = of_get_named_gpio(of_node, "sd-vmmc", 0);
++	if (!gpio_is_valid(sd_vmmc)) sd_vmmc = 0;
++
++	sd_vqen = of_get_named_gpio(of_node, "sd-vqen", 0);
++	if (!gpio_is_valid(sd_vqen)) sd_vqen = 0;
++
++	return 0;
++}
++
++static const struct of_device_id of_meson64_restart_match[] = {
++	{ .compatible = "meson64,reboot", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, of_meson64_restart_match);
++
++static struct platform_driver meson64_restart_driver = {
++	.probe = meson64_restart_probe,
++	.driver = {
++		.name = "meson64-restart",
++		.of_match_table = of_match_ptr(of_meson64_restart_match),
++	},
++};
++
++static int __init meson64_restart_init(void)
++{
++	return platform_driver_register(&meson64_restart_driver);
++}
++device_initcall(meson64_restart_init);
++
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/drv-spi-spidev-remove-warnings.patch b/patch/kernel/archive/meson64-6.10/drv-spi-spidev-remove-warnings.patch
new file mode 100644
index 000000000000..80987aa16384
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/drv-spi-spidev-remove-warnings.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: John Doe <john.doe@somewhere.on.planet>
+Date: Wed, 14 Aug 2024 16:33:07 +0000
+Subject: rockchip64: edge: 6.10.5 drv:spi:spidev remove warnings
+
+Signed-off-by: John Doe <john.doe@somewhere.on.planet>
+---
+ drivers/spi/spidev.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index 5304728c6..64c4280de 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -698,10 +698,11 @@ static const struct file_operations spidev_fops = {
+ static const struct class spidev_class = {
+ 	.name = "spidev",
+ };
+ 
+ static const struct spi_device_id spidev_spi_ids[] = {
++	{ .name = "spi-dev" },
+ 	{ .name = "bh2228fv" },
+ 	{ .name = "dh2228fv" },
+ 	{ .name = "ltc2488" },
+ 	{ .name = "sx1301" },
+ 	{ .name = "bk4" },
+@@ -727,10 +728,11 @@ static int spidev_of_check(struct device *dev)
+ 	dev_err(dev, "spidev listed directly in DT is not supported\n");
+ 	return -EINVAL;
+ }
+ 
+ static const struct of_device_id spidev_dt_ids[] = {
++	{ .compatible = "armbian,spi-dev", .data = &spidev_of_check },
+ 	{ .compatible = "cisco,spi-petra", .data = &spidev_of_check },
+ 	{ .compatible = "dh,dhcom-board", .data = &spidev_of_check },
+ 	{ .compatible = "lineartechnology,ltc2488", .data = &spidev_of_check },
+ 	{ .compatible = "lwn,bk4", .data = &spidev_of_check },
+ 	{ .compatible = "menlo,m53cpld", .data = &spidev_of_check },
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-axg-amper-gateway-am-gz80x.dts b/patch/kernel/archive/meson64-6.10/dt/meson-axg-amper-gateway-am-gz80x.dts
new file mode 100644
index 000000000000..99b4cd095218
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-axg-amper-gateway-am-gz80x.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Patrick Yavitz <pyavitz@armbian.com>
+ *
+ */
+
+/dts-v1/;
+
+#include "meson-axg-jethome-jethub-j1xx.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "amper,gateway-am-gz80x", "amlogic,a113x", "amlogic,meson-axg";
+	model = "Amper Gateway AM-GZ80x";
+
+	aliases {
+		serial0 = &uart_AO;
+		serial1 = &uart_B;
+		serial2 = &uart_AO_B;
+		ethernet0 = &ethmac;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-blue {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-on";
+		};
+
+		led-green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc1";
+		};
+
+		led-red {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "usb-host";
+		};
+ 	};
+
+	/* 1024MB RAM */
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+};
+
+/delete-node/ &i2c1;
+
+/* wifi module */
+&sd_emmc_b {
+	non-removable;
+
+	rtl8189ftv: wifi@1 {
+		reg = <1>;
+	};
+};
+
+&uart_B {
+	status = "okay";
+	pinctrl-0 = <&uart_b_z_pins>;
+	pinctrl-names = "default";
+};
+
+/* UART Wireless module */
+&uart_AO_B {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_b_z_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&gpio GPIOZ_6 GPIO_ACTIVE_HIGH>;
+};
+
+&usb_pwr {
+	gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+};
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-g12-enable-spinor.dtsi b/patch/kernel/archive/meson64-6.10/dt/meson-g12-enable-spinor.dtsi
new file mode 100644
index 000000000000..a6f11e8cdfbe
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-g12-enable-spinor.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, and change bus-width to 4 then spifc can be enabled.
+ */
+&sd_emmc_c {
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>;
+	bus-width = <4>;
+};
+
+&spifc {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-g12a-radxa-zero-spidev.dts b/patch/kernel/archive/meson64-6.10/dt/meson-g12a-radxa-zero-spidev.dts
new file mode 100644
index 000000000000..5ee13525d158
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-g12a-radxa-zero-spidev.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-g12a-radxa-zero.dts"
+
+/ {
+	model = "Radxa Zero with SPIDEV and I2C - MOSI pin 19, CLK pin 23 - SDA pin 3, SCL pin 5";
+};
+
+&spicc1 {
+	pinctrl-0 = <&spicc1_pins &spicc1_ss0_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	spidev@0 {
+		compatible = "armbian,spi-dev";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_sck_a_pins &i2c3_sda_a_pins>;
+	pinctrl-names = "default";
+};
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-g12b-a311d-khadas-vim3-spidev.dts b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-a311d-khadas-vim3-spidev.dts
new file mode 100644
index 000000000000..8982a04c9d1f
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-a311d-khadas-vim3-spidev.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-g12b-a311d-khadas-vim3.dts"
+
+/ {
+	model = "Khadas VIM3 with SPIDEV and I2C - MOSI pin 37, CLK pin 16 - SDA pin 23, SCL pin 23";
+};
+
+&spicc1 {
+	pinctrl-0 = <&spicc1_pins &spicc1_ss0_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	spidev@0 {
+		compatible = "armbian,spi-dev";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_sck_a_pins &i2c3_sda_a_pins>;
+	pinctrl-names = "default";
+};
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-g12b-a311d-khadas-vim3-spinor.dts b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-a311d-khadas-vim3-spinor.dts
new file mode 100644
index 000000000000..e21dd8fd3e00
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-a311d-khadas-vim3-spinor.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-g12b-a311d-khadas-vim3.dts"
+
+/ {
+	model = "Khadas VIM3 with SPI NOR flash";
+};
+
+#include "meson-g12-enable-spinor.dtsi"
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-g12b-odroid-n2-plus-spidev.dts b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-odroid-n2-plus-spidev.dts
new file mode 100644
index 000000000000..a87ddd464773
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-odroid-n2-plus-spidev.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-g12b-odroid-n2-plus.dts"
+
+/ {
+	model = "Hardkernel ODROID-N2Plus with SPIDEV - MISO is pin 19, CLK is pin 23";
+};
+
+&spicc0 {
+	cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>;
+	status = "okay";
+	spidev@0 {
+		compatible = "armbian,spi-dev";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-g12b-odroid-n2-plus-spinor.dts b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-odroid-n2-plus-spinor.dts
new file mode 100644
index 000000000000..0677d7725b01
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-odroid-n2-plus-spinor.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-g12b-odroid-n2-plus.dts"
+
+/ {
+	model = "Hardkernel ODROID-N2Plus with SPI NOR flash";
+};
+
+#include "meson-g12-enable-spinor.dtsi"
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-g12b-odroid-n2-spinor.dts b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-odroid-n2-spinor.dts
new file mode 100644
index 000000000000..521498d9f6fa
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-odroid-n2-spinor.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-g12b-odroid-n2.dts"
+
+/ {
+	model = "Hardkernel ODROID-N2 with SPI NOR flash";
+};
+
+#include "meson-g12-enable-spinor.dtsi"
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-g12b-radxa-zero2-spidev.dts b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-radxa-zero2-spidev.dts
new file mode 100644
index 000000000000..0d16cde214a7
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-radxa-zero2-spidev.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-g12b-radxa-zero2.dts"
+
+/ {
+	model = "Radxa Zero2 with SPIDEV and I2C - MOSI pin 19, CLK pin 23 - SDA pin 3, SCL pin 5";
+};
+
+&spicc1 {
+	pinctrl-0 = <&spicc1_pins &spicc1_ss0_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	spidev@0 {
+		compatible = "armbian,spi-dev";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_sck_a_pins &i2c3_sda_a_pins>;
+	pinctrl-names = "default";
+};
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-g12b-waveshare-cm4-io-base-b.dts b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-waveshare-cm4-io-base-b.dts
new file mode 100644
index 000000000000..3957c8592730
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-g12b-waveshare-cm4-io-base-b.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Patrick Yavitz <pyavitz@xxxxx.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-bananapi-cm4-cm4io.dts"
+
+/ {
+	compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";
+	model = "Waveshare CM4-IO-BASE-B with BPI-CM4 Module";
+
+	aliases {
+		rtc0 = &rtc;
+	};
+};
+
+&i2c1 {
+	rtc: rtc@51 {
+		compatible = "nxp,pcf85063a";
+		reg = <0x51>;
+		wakeup-source;
+	};
+
+	fanctrl: emc2305@2f {
+		compatible = "smsc,emc2305";
+		reg = <0x2f>;
+		#cooling-cells = <0x02>;
+		wakeup-source;
+	};
+};
+
+&cpu_thermal {
+	trips {
+		fanmid0: fanmid0 {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	
+		fanmax0: fanmax0 {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&fanmid0>;
+			cooling-device = <&fanctrl 2 6>;
+		};
+
+		map1 {
+			trip = <&fanmax0>;
+			cooling-device = <&fanctrl 7 THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&usb {
+	dr_mode = "host";
+};
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-gxm-mini-m8s-pro.dts b/patch/kernel/archive/meson64-6.10/dt/meson-gxm-mini-m8s-pro.dts
new file mode 100644
index 000000000000..ef56c270d099
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-gxm-mini-m8s-pro.dts
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "azw,gt1-ultimate", "amlogic,s912", "amlogic,meson-gxm";
+	model = "Mini M8S Pro";
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-white {
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+			panic-indicator;
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1710000>;
+
+		button-function {
+			label = "update";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <10000>;
+		};
+	};
+};
+
+&ethmac {
+	pinctrl-0 = <&eth_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&external_phy>;
+	amlogic,tx-delay-ns = <2>;
+	phy-mode = "rgmii";
+};
+
+&external_mdio {
+	external_phy: ethernet-phy@0 {
+		/* Realtek RTL8211F (0x001cc916) */
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_15 */
+		interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&ir {
+	linux,rc-map-name = "rc-beelink-gs1";
+};
+
+&sd_emmc_a {
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "qcom,qca9377";
+	};
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "qcom,qca9377-bt";
+		enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-gxm-t95z-plus.dts b/patch/kernel/archive/meson64-6.10/dt/meson-gxm-t95z-plus.dts
new file mode 100644
index 000000000000..5f4bd19d5d77
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-gxm-t95z-plus.dts
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "sunvell,t95z-plus", "amlogic,s912", "amlogic,meson-gxm";
+	model = "Sunvell T95Z Plus";
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		led-blue {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio GPIODV_25 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			panic-indicator;
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1710000>;
+
+		button-function {
+			label = "update";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <10000>;
+		};
+	};
+
+	spi {
+		compatible = "spi-gpio";
+
+		/* T95Z v1 (enabled) */
+		sck-gpios = <&gpio GPIODV_22 GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&gpio GPIODV_23 GPIO_ACTIVE_HIGH>;
+		cs-gpios = <&gpio GPIODV_21 GPIO_ACTIVE_LOW>;
+
+		/* T95Z v2 (disabled)
+		sck-gpios = <&gpio GPIODV_19 GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&gpio GPIODV_18 GPIO_ACTIVE_HIGH>;
+		cs-gpios = <&gpio GPIODV_20 GPIO_ACTIVE_LOW>;
+		*/
+
+		num-chipselects = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		tm1628: led-controller@0 {
+			compatible = "titanmec,tm1628";
+			reg = <0>;
+			spi-3wire;
+			spi-lsb-first;
+			spi-rx-delay-us = <1>;
+			spi-max-frequency = <500000>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+
+			titanmec,segment-mapping = /bits/ 8 <4 5 6 1 2 3 7>;
+			titanmec,grid = /bits/ 8 <2 3 4 5 1>;
+
+			alarm@1,1 {
+				reg = <1 1>;
+				function = LED_FUNCTION_ALARM;
+			};
+
+			usb@1,2 {
+				reg = <1 2>;
+				function = LED_FUNCTION_USB;
+			};
+
+			play@1,3 {
+				reg = <1 3>;
+				function = "play";
+			};
+
+			pause@1,4 {
+				reg = <1 4>;
+				function = "pause";
+			};
+
+			colon@1,5 {
+				reg = <1 5>;
+				function = "colon";
+			};
+
+			lan@1,6 {
+				reg = <1 6>;
+				function = LED_FUNCTION_LAN;
+			};
+
+			wlan@1,7 {
+				reg = <1 7>;
+				function = LED_FUNCTION_WLAN;
+			};
+		};
+	};
+};
+
+&ethmac {
+	pinctrl-0 = <&eth_pins>;
+	pinctrl-names = "default";
+
+	phy-handle = <&external_phy>;
+	phy-mode = "rgmii";
+
+	amlogic,tx-delay-ns = <2>;
+};
+
+&external_mdio {
+	external_phy: ethernet-phy@1 {
+		/* ZTE ZX2AA500 */
+		compatible = "ethernet-phy-id0381.5c11",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+		max-speed = <1000>;
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_15 */
+		interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&sd_emmc_a {
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-sm1-jethome-jethub-j200-spinor.dts b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-jethome-jethub-j200-spinor.dts
new file mode 100644
index 000000000000..a9e4749f8395
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-jethome-jethub-j200-spinor.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-sm1-jethome-jethub-j200.dts"
+
+/ {
+	model = "JetHub D2 with SPI NOR flash";
+};
+
+#include "meson-g12-enable-spinor.dtsi"
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-sm1-jethome-jethub-j200.dts b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-jethome-jethub-j200.dts
new file mode 100644
index 000000000000..d5c761aa0a65
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-jethome-jethub-j200.dts
@@ -0,0 +1,705 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 JetHome
+ * Author: Viacheslav Bocharov <adeep@lexina.in>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1.dtsi"
+
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+
+/ {
+
+	compatible = "jethome,jethub-j200", "amlogic,sm1";
+	model = "JetHome JetHub D2";
+
+	aliases {
+		serial0 = &uart_AO;
+		ethernet0 = &ethmac;
+		rtc0 = &rtc;
+		rtc1 = &vrtc;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+	};
+
+	tflash_vdd: regulator-tflash_vdd {
+		compatible = "regulator-fixed";
+
+		regulator-name = "TFLASH_VDD";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	tf_io: gpio-regulator-tf_io {
+		compatible = "regulator-gpio";
+
+		regulator-name = "TF_IO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_5v>;
+
+		enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>;
+		enable-active-high;
+		regulator-always-on;
+
+		gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>;
+		gpios-states = <0>;
+
+		states = <3300000 0>,
+			 <1800000 1>;
+	};
+
+	flash_1v8: regulator-flash_1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "FLASH_1V8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_3v3>;
+		regulator-always-on;
+	};
+
+	main_12v: regulator-main_12v {
+		compatible = "regulator-fixed";
+		regulator-name = "12V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+	};
+
+	vcc_5v: regulator-vcc_5v {
+		compatible = "regulator-fixed";
+		regulator-name = "5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		vin-supply = <&main_12v>;
+		gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+		enable-active-high;
+	};
+
+	vcc_1v8: regulator-vcc_1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_1V8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_3v3>;
+		regulator-always-on;
+	};
+
+	vcc_3v3: regulator-vcc_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vddao_3v3>;
+		regulator-always-on;
+	};
+
+	vddcpu: regulator-vddcpu {
+		/*
+		 * MP8756GD Regulator.
+		 */
+		compatible = "pwm-regulator";
+
+		regulator-name = "VDDCPU";
+		regulator-min-microvolt = <721000>;
+		regulator-max-microvolt = <1022000>;
+
+		pwm-supply = <&main_12v>;
+
+		pwms = <&pwm_AO_cd 1 1250 0>;
+		pwm-dutycycle-range = <100 0>;
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	usb_pwr_en: regulator-usb_pwr_en {
+		compatible = "regulator-fixed";
+		regulator-name = "USB_PWR_EN";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_5v>;
+
+		/* Connected to the internal USB-Hub */
+		gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vddao_1v8: regulator-vddao_1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDAO_1V8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vddao_3v3>;
+		regulator-always-on;
+	};
+
+	vddao_3v3: regulator-vddao_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDAO_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&main_12v>;
+		regulator-always-on;
+	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi_tx_tmds_out>;
+			};
+		};
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		audio-aux-devs = <&tdmout_b>;
+		audio-routing = "TDM_B Playback", "TDMOUT_B OUT";
+
+		assigned-clocks = <&clkc CLKID_MPLL2>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+
+		/* 8ch hdmi interface */
+		dai-link-0 {
+			sound-dai = <&tdmif_b>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-0 = <1 1>;
+			dai-tdm-slot-tx-mask-1 = <1 1>;
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-tx-mask-3 = <1 1>;
+			mclk-fs = <256>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+			};
+		};
+
+		/* hdmi glue */
+		dai-link-1 {
+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+			codec {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+
+	meson64-reboot {
+		compatible = "meson64,reboot";
+		sys_reset = <0x84000009>;
+		sys_poweroff = <0x84000008>;
+
+		sd-vqen = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+		sd-vqsw = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>;
+		sd-vmmc = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+			panic-indicator;
+		};
+
+		led-red {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio GPIOH_5 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+	};
+
+	sound {
+		model = "JETHUB-D2";
+	};
+
+};
+
+&arb {
+	status = "okay";
+};
+
+&cec_AO {
+	pinctrl-0 = <&cec_ao_a_h_pins>;
+	pinctrl-names = "default";
+	status = "disabled";
+	hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+	pinctrl-0 = <&cec_ao_b_h_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vddcpu>;
+	operating-points-v2 = <&cpu_opp_table>;
+	clocks = <&clkc CLKID_CPU_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu1 {
+	cpu-supply = <&vddcpu>;
+	operating-points-v2 = <&cpu_opp_table>;
+	clocks = <&clkc CLKID_CPU1_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu2 {
+	cpu-supply = <&vddcpu>;
+	operating-points-v2 = <&cpu_opp_table>;
+	clocks = <&clkc CLKID_CPU2_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu3 {
+	cpu-supply = <&vddcpu>;
+	operating-points-v2 = <&cpu_opp_table>;
+	clocks = <&clkc CLKID_CPU3_CLK>;
+	clock-latency = <50000>;
+};
+
+&ext_mdio {
+	external_phy: ethernet-phy@0 {
+		/* Realtek RTL8211F (0x001cc916) */
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&ethmac {
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&external_phy>;
+	amlogic,tx-delay-ns = <2>;
+};
+
+&gpio {
+	gpio-line-names =
+		/* GPIOZ */
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* GPIOH */
+		"HDMITX_SDA", /* GPIOH_0 */
+		"HDMITX_SCL", /* GPIOH_1 */
+		"HDMITX_HPD_IN", /* GPIOH_2 */
+		"AO_CEC_A", /* GPIOH_3 */
+		"HUB_RESET", /* GPIOH_4 */
+		"LED_RED", /* GPIOH_5 */
+		"I2C_SDA_MODULES", /* GPIOH_6 */
+		"I2C_SCL_MODULES", /* GPIOH_7 */
+		"5V_EN", /* GPIOH_8 */
+		/* BOOT */
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* GPIOC */
+		"", "", "", "", "", "", "", "",
+		/* GPIOA */
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "",
+		"I2C_SDA_SYSBUS", /* GPIOA_14 */
+		"I2C_SCL_SYSBUS", /* GPIOA_15 */
+		/* GPIOX */
+		"", "", "", "", "", "", /* GPIOX_0 - GPIOX_5 */
+		"RS485_TX", /* GPIOX_6 */
+		"RS485_RX", /* GPIOX_7 */
+		"", "", "", "", "", "", /* GPIOX_8 - GPIOX_13 */
+		"", "", "", /* GPIOX_14 - GPIOX_16 */
+		"I2C_SDA_LCDBUS",  /* GPIOX_17 */
+		"I2C_SCL_LCDBUS",  /* GPIOX_18 */
+		""; /* GPIOX_19 */
+	/*
+	 * WARNING: The USB Hub needs a reset signal to be turned low in
+	 * order to be detected by the USB Controller. This signal should
+	 * be handled by a USB specific power sequence to reset the Hub
+	 * when the USB bus is powered down.
+	 */
+	usb-hub-hog {
+		gpio-hog;
+		gpios = <GPIOH_4 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "usb-hub-reset";
+	};
+
+};
+
+&gpio_ao {
+	gpio-line-names =
+		/* GPIOAO */
+		"CONSOLE_TX",  /* GPIOAO_0 */
+		"CONSOLE_RX",  /* GPIOAO_1 */
+		"USB_OTG_PWR_EN", /* GPIOAO_2 */
+		"TFLASH_VDD_EN",  /* GPIOAO_3 */
+		"MCU_RESET", /* GPIOAO_4 */
+		"POWER_GOOD", /* GPIOAO_5 */
+		"TF_3V3N_1V8_EN",  /* GPIOAO_6 */
+		"GPIO_EXPANDER_INT", /* GPIOAO_7 */
+		"MCU_UART_TX", /* GPIOAO_8 */
+		"MCU_UART_RX", /* GPIOAO_9 */
+		"BUTTON_USR", /* GPIOAO_10 */
+		"LED_GREEN", /* GPIOAO_11 */
+		/* GPIOE */
+		"VDDEE_PWM", "VDDCPU_PWM", "TF_PWR_EN";
+};
+
+&hdmi_tx {
+	status = "okay";
+	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+	pinctrl-names = "default";
+	hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+	hdmi_tx_tmds_out: endpoint {
+		remote-endpoint = <&hdmi_connector_in>;
+	};
+};
+
+&pwm_AO_cd {
+	pinctrl-0 = <&pwm_ao_d_e_pins>;
+	pinctrl-names = "default";
+	clocks = <&xtal>;
+	clock-names = "clkin1";
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+};
+
+/* SD card */
+&sd_emmc_b {
+	status = "okay";
+	pinctrl-0 = <&sdcard_c_pins>;
+	pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <200000000>;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	disable-wp;
+
+	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&tflash_vdd>;
+	vqmmc-supply = <&tf_io>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	status = "okay";
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	max-frequency = <200000000>;
+	disable-wp;
+
+	mmc-pwrseq = <&emmc_pwrseq>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&flash_1v8>;
+};
+
+&spifc {
+	status = "disabled";
+	pinctrl-0 = <&nor_pins>;
+	pinctrl-names = "default";
+
+	flash: nor-flash@0 {
+		compatible = "sst,w25q256", "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+	};
+};
+
+&tdmif_b {
+	status = "okay";
+};
+
+&tdmout_b {
+	status = "okay";
+};
+
+&tohdmitx {
+	status = "okay";
+};
+
+&uart_AO {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
+};
+
+&uart_AO_B {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_b_8_9_pins>;
+	pinctrl-names = "default";
+};
+
+&uart_B {
+	status = "okay";
+	pinctrl-0 = <&uart_b_pins>;
+	pinctrl-names = "default";
+};
+
+
+&usb {
+	status = "okay";
+	vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+	phy-supply = <&vcc_5v>;
+};
+
+
+/* I2C for modules */
+&i2c1 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+
+	/* GPIO expander */
+	u9: gpio@22 {
+		compatible = "nxp,pca9535";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gpio_intc>;
+		interrupts = <IRQID_GPIOAO_7 IRQ_TYPE_LEVEL_LOW>;
+
+		gpio-line-names =
+			"RELAY_1", "RELAY_2",
+			"", "",
+			"UXM1_RESET", "UXM1_BOOT",
+			"UXM2_RESET", "UXM2_BOOT",
+			"DIN_1", "DIN_2", "DIN_3",
+			"","","","","";
+	};
+
+	/* 1-wire */
+	w1: onewire@18 {
+		compatible = "maxim,ds2482";
+		reg = <0x18>;
+	};
+
+};
+
+
+/* I2C for lcd/etc */
+&i2c2 {
+	status = "okay";
+	pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+};
+
+/* I2C_EE_M3: I2C for CPU board */
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+
+	/* I2C for rtc */
+	rtc: rtc@51 {
+		status = "okay";
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+		wakeup-source;
+	};
+
+	/* FRAM on base board */
+	fram: eeprom@52 {
+		compatible = "atmel,24c64";
+		reg = <0x52>;
+		pagesize = <0x20>;
+		label = "fram";
+		address-width = <0x10>;
+		vcc-supply = <&vddao_3v3>;
+	};
+
+	/* EEPROM on CPU board */
+	eepromc: eeprom@54 {
+		compatible = "atmel,24c64";
+		reg = <0x54>;
+		pagesize = <0x20>;
+		label = "eepromc";
+		address-width = <0x10>;
+		vcc-supply = <&vddao_3v3>;
+	};
+
+	/* EEPROM on base board */
+	eeprompd: eeprom@56 {
+		compatible = "atmel,24c64";
+		reg = <0x56>;
+		pagesize = <0x20>;
+		label = "eeprompd";
+		address-width = <0x10>;
+		vcc-supply = <&vddao_3v3>;
+	};
+
+	/* EEPROM on power module */
+	eeprompm: eeprom@57 {
+		compatible = "atmel,24c64";
+		reg = <0x57>;
+		pagesize = <0x20>;
+		label = "eeprompm";
+		address-width = <0x10>;
+		vcc-supply = <&vddao_3v3>;
+	};
+
+	/* temperature sensors */
+	temp1: tmp102@48 {
+		compatible = "ti,tmp102";
+		reg = <0x48>;
+	};
+
+	temp2: tmp102@49 {
+		compatible = "ti,tmp102";
+		reg = <0x49>;
+	};
+
+};
+
+&efuse {
+	eth_mac: eth-mac@0 {
+		reg = <0x0 0x6>;
+	};
+
+	bt_mac: bt-mac@6 {
+		reg = <0x6 0x6>;
+	};
+
+	wifi_mac: wifi-mac@c {
+		reg = <0xc 0x6>;
+	};
+
+	bid: bid@12 {
+		reg = <0x12 0x20>;
+	};
+
+	sn: sn@32 {
+		reg = <0x32 0x20>;
+	};
+};
+
+&cpu_thermal {
+	trips {
+		cpu_passive: cpu-passive {
+			temperature = <70000>; /* millicelsius */
+			hysteresis = <2000>; /* millicelsius */
+			type = "passive";
+		};
+
+		cpu_hot: cpu-hot {
+			temperature = <85000>; /* millicelsius */
+			hysteresis = <2000>; /* millicelsius */
+			type = "hot";
+		};
+
+		cpu_critical: cpu-critical {
+			temperature = <90000>; /* millicelsius */
+			hysteresis = <2000>; /* millicelsius */
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cpu_passive>;
+			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+
+		map1 {
+			trip = <&cpu_hot>;
+			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&ddr_thermal {
+	trips {
+		ddr_passive: ddr-passive {
+			temperature = <70000>; /* millicelsius */
+			hysteresis = <2000>; /* millicelsius */
+			type = "passive";
+		};
+
+		ddr_critical: ddr-critical {
+			temperature = <85000>; /* millicelsius */
+			hysteresis = <2000>; /* millicelsius */
+			type = "critical";
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-sm1-khadas-vim3l-spidev.dts b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-khadas-vim3l-spidev.dts
new file mode 100644
index 000000000000..e7a0f5a3fc35
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-khadas-vim3l-spidev.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-sm1-khadas-vim3l.dts"
+
+/ {
+	model = "Khadas VIM3L with SPIDEV and I2C - MOSI pin 37, CLK pin 16 - SDA pin 23, SCL pin 23";
+};
+
+&spicc1 {
+	pinctrl-0 = <&spicc1_pins &spicc1_ss0_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	spidev@0 {
+		compatible = "armbian,spi-dev";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_sck_a_pins &i2c3_sda_a_pins>;
+	pinctrl-names = "default";
+};
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-sm1-khadas-vim3l-spinor.dts b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-khadas-vim3l-spinor.dts
new file mode 100644
index 000000000000..f0d547e0c9a6
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-khadas-vim3l-spinor.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-sm1-khadas-vim3l.dts"
+
+/ {
+	model = "Khadas VIM3L with SPI NOR flash";
+};
+
+#include "meson-g12-enable-spinor.dtsi"
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-sm1-odroid-c4-spidev.dts b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-odroid-c4-spidev.dts
new file mode 100644
index 000000000000..4688b40052ca
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-odroid-c4-spidev.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "meson-sm1-odroid-c4.dts"
+
+/ {
+	model = "Hardkernel ODROID-C4 - MOSI is pin y, CLK is pin x";
+};
+
+&spicc1 {
+	pinctrl-0 = <&spicc1_pins &spicc1_ss0_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	spidev@0 {
+		compatible = "armbian,spi-dev";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
diff --git a/patch/kernel/archive/meson64-6.10/dt/meson-sm1-ugoos-x3.dts b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-ugoos-x3.dts
new file mode 100644
index 000000000000..884a08836ae9
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/dt/meson-sm1-ugoos-x3.dts
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2021 flippy <uniqfreq@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-ac2xx.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+	compatible = "amlogic,sm1";
+	model = "Ugoos X3";
+
+	aliases {
+		rtc0 = &rtc;
+		rtc1 = &vrtc;
+		mmc0 = &sd_emmc_a;
+		mmc1 = &sd_emmc_b;
+		mmc2 = &sd_emmc_c;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		red_led {
+			label = "red";
+			gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		blue_led {
+			label = "blue";
+			gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "UGOOS-X3";
+		audio-aux-devs = <&tdmout_b>;
+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
+				"TDM_B Playback", "TDMOUT_B OUT";
+
+		assigned-clocks = <&clkc CLKID_MPLL2>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		/* 8ch hdmi interface */
+		dai-link-3 {
+			sound-dai = <&tdmif_b>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-0 = <1 1>;
+			dai-tdm-slot-tx-mask-1 = <1 1>;
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-tx-mask-3 = <1 1>;
+			mclk-fs = <256>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+			};
+		};
+
+		/* hdmi glue */
+		dai-link-4 {
+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+			codec {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&ao_5v>;
+		regulator-always-on;
+	};
+
+	usb_pwr_en: regulator-usb-pwr-en {
+		compatible = "regulator-fixed";
+		regulator-name = "USB_PWR_EN";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&ao_5v>;
+
+		gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&vddcpu {
+	regulator-min-microvolt = <721000>;
+	regulator-max-microvolt = <1022000>;
+	pwms = <&pwm_AO_cd 1 1250 0>;
+};
+
+&arb {
+	status = "okay";
+};
+
+&clkc_audio {
+	status = "okay";
+};
+
+&ethmac {
+	status = "okay";
+
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	phy-mode = "rgmii-txid";
+	phy-handle = <&external_phy>;
+
+	rx-internal-delay-ps = <800>;
+
+	snps,aal;
+	snps,rxpbl = <0x8>;
+	snps,txpbl = <0x8>;
+
+	rx-fifo-depth = <4096>;
+	tx-fifo-depth = <4096>;
+
+	nvmem-cells = <&eth_mac>;
+	nvmem-cell-names = "eth_mac";
+};
+
+&ext_mdio {
+	external_phy: ethernet-phy@0 {
+		/* Realtek RTL8211F (0x001cc916) */
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&tdmif_b {
+	status = "okay";
+};
+
+&tdmout_b {
+	status = "okay";
+};
+
+&tohdmitx {
+	status = "okay";
+};
+
+&uart_A {
+	status = "okay";
+
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+&usb {
+	dr_mode = "host";
+	vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+	phy-supply = <&ao_5v>;
+};
+
+&usb2_phy1 {
+	phy-supply = <&ao_5v>;
+};
+
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+	pinctrl-names = "default";
+
+	rtc: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		wakeup-source;
+
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+	};
+};
+
+/* SDIO */
+&sd_emmc_a {
+	/delete-property/ sd-uhs-sdr104;
+	sd-uhs-sdr50;
+	max-frequency = <100000000>;
+
+        //sd-uhs-ddr50;
+	//max-frequency = <50000000>;
+
+	//sd-uhs-sdr104;
+	//max-frequency = <200000000>;
+};
+
+/* SD card */
+&sd_emmc_b {
+	cap-sd-highspeed;
+	max-frequency = <100000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	max-frequency = <200000000>;
+};
+
+&cpu_opp_table {
+	opp-2016000000 {
+		opp-hz = /bits/ 64 <2016000000>;
+		opp-microvolt = <1000000>;
+	};
+};
+
+&efuse {
+	eth_mac: eth_mac@0 {
+		reg = <0x0 0x06>;
+	};
+
+	bt_mac: bt_mac@6 {
+		reg = <0x6 0x06>;
+	};
+
+	wifi_mac: wifi_mac@12 {
+		reg = <0x0c 0x06>;
+	};
+
+	usid: usid@18 {
+		reg = <0x12 0x10>;
+	};
+};
+/*
+&openvfd {
+	status = "disabled";
+};
+*/
\ No newline at end of file
diff --git a/patch/kernel/archive/meson64-6.10/general-add-Amlogic-Meson-GX-PM-Suspend.patch b/patch/kernel/archive/meson64-6.10/general-add-Amlogic-Meson-GX-PM-Suspend.patch
new file mode 100644
index 000000000000..c4fc44b09655
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-add-Amlogic-Meson-GX-PM-Suspend.patch
@@ -0,0 +1,134 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Thu, 3 Nov 2016 15:29:23 +0100
+Subject: HACK: arm64: meson: add Amlogic Meson GX PM Suspend
+
+The Amlogic Meson GX SoCs uses a non-standard argument to the
+PSCI CPU_SUSPEND call to enter system suspend.
+
+Implement such call within platform_suspend_ops.
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/firmware/meson/Kconfig       |  6 +
+ drivers/firmware/meson/Makefile      |  1 +
+ drivers/firmware/meson/meson_gx_pm.c | 86 ++++++++++
+ 3 files changed, 93 insertions(+)
+
+diff --git a/drivers/firmware/meson/Kconfig b/drivers/firmware/meson/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/firmware/meson/Kconfig
++++ b/drivers/firmware/meson/Kconfig
+@@ -9,3 +9,9 @@ config MESON_SM
+ 	depends on ARM64_4K_PAGES
+ 	help
+ 	  Say y here to enable the Amlogic secure monitor driver
++
++config MESON_GX_PM
++	bool
++	default ARCH_MESON if ARM64
++	help
++	  Say y here to enable the Amlogic GX SoC Power Management
+diff --git a/drivers/firmware/meson/Makefile b/drivers/firmware/meson/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/firmware/meson/Makefile
++++ b/drivers/firmware/meson/Makefile
+@@ -1,2 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ obj-$(CONFIG_MESON_SM) +=	meson_sm.o
++obj-$(CONFIG_MESON_GX_PM) +=	meson_gx_pm.o
+diff --git a/drivers/firmware/meson/meson_gx_pm.c b/drivers/firmware/meson/meson_gx_pm.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/firmware/meson/meson_gx_pm.c
+@@ -0,0 +1,86 @@
++/*
++ * Amlogic Meson GX Power Management
++ *
++ * Copyright (c) 2016 Baylibre, SAS.
++ * Author: Neil Armstrong <narmstrong@baylibre.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/suspend.h>
++#include <linux/arm-smccc.h>
++
++#include <uapi/linux/psci.h>
++
++#include <asm/suspend.h>
++
++/*
++ * The Amlogic GX SoCs uses a special argument value to the
++ * PSCI CPU_SUSPEND method to enter SUSPEND_MEM.
++ */
++
++#define MESON_SUSPEND_PARAM	0x0010000
++#define PSCI_FN_NATIVE(version, name)	PSCI_##version##_FN64_##name
++
++static int meson_gx_suspend_finish(unsigned long arg)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(PSCI_FN_NATIVE(0_2, CPU_SUSPEND), arg,
++		      virt_to_phys(cpu_resume), 0, 0, 0, 0, 0, &res);
++
++	return res.a0;
++}
++
++static int meson_gx_suspend_enter(suspend_state_t state)
++{
++	switch (state) {
++	case PM_SUSPEND_MEM:
++		return cpu_suspend(MESON_SUSPEND_PARAM,
++				   meson_gx_suspend_finish);
++	}
++
++	return -EINVAL;
++}
++
++static const struct platform_suspend_ops meson_gx_pm_ops = {
++		.enter = meson_gx_suspend_enter,
++		.valid = suspend_valid_only_mem,
++};
++
++static const struct of_device_id meson_gx_pm_match[] = {
++	{ .compatible = "amlogic,meson-gx-pm", },
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, meson_gx_pm_match);
++
++static int meson_gx_pm_probe(struct platform_device *pdev)
++{
++	suspend_set_ops(&meson_gx_pm_ops);
++
++	return 0;
++}
++
++static struct platform_driver meson_gx_pm_driver = {
++	.probe = meson_gx_pm_probe,
++	.driver = {
++		.name = "meson-gx-pm",
++		.of_match_table = meson_gx_pm_match,
++	},
++};
++
++module_platform_driver(meson_gx_pm_driver);
++
++MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
++MODULE_DESCRIPTION("Amlogic Meson GX PM driver");
++MODULE_LICENSE("GPL v2");
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-add-overlay-compilation-support.patch b/patch/kernel/archive/meson64-6.10/general-add-overlay-compilation-support.patch
new file mode 100644
index 000000000000..6cad873b4e4d
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-add-overlay-compilation-support.patch
@@ -0,0 +1,64 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 20 Jul 2024 13:58:49 +0200
+Subject: compile .scr and install overlays in right path
+
+---
+ scripts/Makefile.dtbinst | 13 +++++++++-
+ scripts/Makefile.lib     |  8 +++++-
+ 2 files changed, 19 insertions(+), 2 deletions(-)
+
+diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
+index 111111111111..222222222222 100644
+--- a/scripts/Makefile.dtbinst
++++ b/scripts/Makefile.dtbinst
+@@ -33,7 +33,18 @@ endef
+ 
+ $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d))))
+ 
+-dtbs := $(notdir $(dtbs))
++# Very convoluted way to flatten all the device tree
++# directories, but keep the "/overlay/" directory
++
++# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip)
++topmost_dir = $(firstword $(subst /, ,$(dtbs)))
++# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir"
++dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs)))
++# collect the non-overlay dtbs
++dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs))
++# compose the dtbs variable flattening all the non-overlays entries
++# and appending the overlays entries
++dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays)
+ 
+ endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL
+ 
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 111111111111..222222222222 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -394,15 +394,21 @@ quiet_cmd_wrap_S_dtb = WRAP    $@
+ 		echo '.balign STRUCT_ALIGNMENT';					\
+ 	} > $@
+ 
++quiet_cmd_scr = MKIMAGE $@
++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
++
+ $(obj)/%.dtb.S: $(obj)/%.dtb FORCE
+ 	$(call if_changed,wrap_S_dtb)
+ 
+ $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE
+ 	$(call if_changed,wrap_S_dtb)
+ 
++$(obj)/%.scr: $(src)/%.scr-cmd FORCE
++	$(call if_changed,scr)
++
+ quiet_cmd_dtc = DTC     $@
+ cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+-	$(DTC) -o $@ -b 0 \
++	$(DTC) -@ -o $@ -b 0 \
+ 		$(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \
+ 		-d $(depfile).dtc.tmp $(dtc-tmp) ; \
+ 	cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-driver-tm1628-auxdisplay-add-support-for-Titanmec-TM16.patch b/patch/kernel/archive/meson64-6.10/general-driver-tm1628-auxdisplay-add-support-for-Titanmec-TM16.patch
new file mode 100644
index 000000000000..0989fdb06d3f
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-driver-tm1628-auxdisplay-add-support-for-Titanmec-TM16.patch
@@ -0,0 +1,585 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <hkallweit1@gmail.com>
+Date: Sun, 20 Feb 2022 08:24:47 +0000
+Subject: FROMLIST(v5): auxdisplay: add support for Titanmec TM1628 7 segment
+ display controller + etc
+
+FROMLIST(v5): MAINTAINERS: Add entry for tm1628 auxdisplay driver
+
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+
+FROMLIST(v5): auxdisplay: add support for Titanmec TM1628 7 segment display controller
+
+This patch adds support for the Titanmec TM1628 7 segment display
+controller. It's based on previous RFC work from Andreas Farber.
+The RFC version placed the driver in the LED subsystem, but this was
+NAK'ed by the LED maintainer. Therefore I moved the driver to
+/drivers/auxdisplay what seems most reasonable to me.
+
+Further changes to the RFC version:
+- Driver can be built also w/o LED class support, for displays that
+  don't have any symbols to be exposed as LED's.
+- Simplified the code and rewrote a lot of it.
+- Driver is now kind of a MVP, but functionality should be sufficient
+  for most use cases.
+- Use the existing 7 segment support in uapi/linux/map_to_7segment.h
+  as suggested by Geert Uytterhoeven.
+
+Note: There's a number of chips from other manufacturers that are
+      almost identical, e.g. FD628, SM1628. Only difference I saw so
+      far is that they partially support other display modes.
+      TM1628: 6x12, 7x11
+      SM1628C: 4x13, 5x12, 6x11, 7x10
+      For typical displays on devices using these chips this
+      difference shouldn't matter.
+
+Successfully tested on a TX3 Mini TV box that has an SM1628C and a
+display with 4 digits and 7 symbols.
+
+Co-developed-by: Andreas Farber <afaerber@suse.de>
+Signed-off-by: Andreas Farber <afaerber@suse.de>
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+
+FROMLIST(v5): docs: ABI: document tm1628 attribute display-text
+
+Document the attribute for reading / writing the text to be displayed on
+the 7 segment display.
+
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+
+FROMLIST(v5): dt-bindings: auxdisplay: Add Titan Micro Electronics TM1628
+
+Add a YAML schema binding for TM1628 auxdisplay
+(7/11-segment LED) controller.
+
+This patch is partially based on previous RFC work from
+Andreas Farber <afaerber@suse.de>.
+
+Co-developed-by: Andreas Farber <afaerber@suse.de>
+Signed-off-by: Andreas Farber <afaerber@suse.de>
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+---
+ Documentation/ABI/testing/sysfs-devices-auxdisplay-tm1628         |   7 +
+ Documentation/devicetree/bindings/auxdisplay/titanmec,tm1628.yaml |  82 ++
+ drivers/auxdisplay/Kconfig                                        |  11 +
+ drivers/auxdisplay/Makefile                                       |   1 +
+ drivers/auxdisplay/tm1628.c                                       | 376 ++++++++++
+ 5 files changed, 477 insertions(+)
+
+diff --git a/Documentation/ABI/testing/sysfs-devices-auxdisplay-tm1628 b/Documentation/ABI/testing/sysfs-devices-auxdisplay-tm1628
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/Documentation/ABI/testing/sysfs-devices-auxdisplay-tm1628
+@@ -0,0 +1,7 @@
++What:		/sys/devices/.../display-text
++Date:		February 2022
++Contact:	Heiner Kallweit <hkallweit1@gmail.com>
++Description:
++		The text to be displayed on the 7 segment display.
++		Any printable character is allowed as input, but some
++		can not be displayed in a readable way with 7 segments.
+diff --git a/Documentation/devicetree/bindings/auxdisplay/titanmec,tm1628.yaml b/Documentation/devicetree/bindings/auxdisplay/titanmec,tm1628.yaml
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/Documentation/devicetree/bindings/auxdisplay/titanmec,tm1628.yaml
+@@ -0,0 +1,82 @@
++# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/leds/titanmec,tm1628.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Titan Micro Electronics TM1628 LED controller
++
++properties:
++  compatible:
++    enum:
++    - titanmec,tm1628
++
++  reg:
++    maxItems: 1
++
++  grid:
++    description:
++      Mapping of display digit position to grid number.
++      This implicitly defines the display size.
++    $ref: /schemas/types.yaml#/definitions/uint8-array
++    minItems: 1
++    maxItems: 7
++
++  segment-mapping:
++    description:
++      Mapping of 7 segment display segments A-G to bit numbers 1-12.
++    $ref: /schemas/types.yaml#/definitions/uint8-array
++    minItems: 7
++    maxItems: 7
++
++  "#address-cells":
++    const: 2
++
++  "#size-cells":
++    const: 0
++
++required:
++  - compatible
++  - reg
++
++patternProperties:
++  "^.*@[1-7],([1-9]|1[0-6])$":
++    type: object
++    description: |
++      Properties for a single LED.
++
++    properties:
++      reg:
++        description: |
++          1-based grid number, followed by 1-based segment bit number.
++        maxItems: 1
++
++    required:
++      - reg
++
++examples:
++  - |
++    #include <dt-bindings/leds/common.h>
++
++    spi {
++        #address-cells = <1>;
++        #size-cells = <0>;
++
++        led-controller@0 {
++            compatible = "titanmec,tm1628";
++            reg = <0>;
++            spi-3-wire;
++            spi-lsb-first;
++            spi-max-frequency = <500000>;
++            grid = /bits/ 8 <4 3 2 1>;
++            segment-mapping = /bits/ 8 <4 5 6 1 2 3 7>;
++            #address-cells = <2>;
++            #size-cells = <0>;
++
++            alarmn@5,4 {
++                reg = <5 4>;
++                function = LED_FUNCTION_ALARM;
++            };
++        };
++    };
++...
+diff --git a/drivers/auxdisplay/Kconfig b/drivers/auxdisplay/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/auxdisplay/Kconfig
++++ b/drivers/auxdisplay/Kconfig
+@@ -59,6 +59,17 @@ config LCD2S
+ 	  is a simple single color character display. You have to connect it
+ 	  to an I2C bus.
+ 
++config TM1628
++	tristate "TM1628 driver for LED 7/11 segment displays"
++	depends on SPI
++	depends on OF || COMPILE_TEST
++	help
++	  Say Y to enable support for Titan Micro Electronics TM1628
++	  LED controller.
++
++	  It's a 3-wire SPI device controlling a two-dimensional grid of
++	  LEDs. Dimming is applied to all outputs through an internal PWM.
++
+ menuconfig PARPORT_PANEL
+ 	tristate "Parallel port LCD/Keypad Panel support"
+ 	depends on PARPORT
+diff --git a/drivers/auxdisplay/Makefile b/drivers/auxdisplay/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/auxdisplay/Makefile
++++ b/drivers/auxdisplay/Makefile
+@@ -16,3 +16,4 @@ obj-$(CONFIG_LINEDISP)		+= line-display.o
+ obj-$(CONFIG_MAX6959)		+= max6959.o
+ obj-$(CONFIG_PARPORT_PANEL)	+= panel.o
+ obj-$(CONFIG_SEG_LED_GPIO)	+= seg-led-gpio.o
++obj-$(CONFIG_TM1628)		+= tm1628.o
+diff --git a/drivers/auxdisplay/tm1628.c b/drivers/auxdisplay/tm1628.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/auxdisplay/tm1628.c
+@@ -0,0 +1,376 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Titan Micro Electronics TM1628 LED controller
++ *
++ * Copyright (c) 2019 Andreas Färber
++ * Copyright (c) 2022 Heiner Kallweit
++ */
++
++#include <linux/ctype.h>
++#include <linux/delay.h>
++#include <linux/leds.h>
++#include <linux/module.h>
++#include <linux/property.h>
++#include <linux/spi/spi.h>
++#include <uapi/linux/map_to_7segment.h>
++
++#define TM1628_CMD_DISPLAY_MODE		(0 << 6)
++#define TM1628_DISPLAY_MODE_6_12	0x02
++#define TM1628_DISPLAY_MODE_7_11	0x03
++
++#define TM1628_CMD_DATA			(1 << 6)
++#define TM1628_DATA_TEST_MODE		BIT(3)
++#define TM1628_DATA_FIXED_ADDR		BIT(2)
++#define TM1628_DATA_WRITE_DATA		0x00
++#define TM1628_DATA_READ_DATA		0x02
++
++#define TM1628_CMD_DISPLAY_CTRL		(2 << 6)
++#define TM1628_DISPLAY_CTRL_DISPLAY_ON	BIT(3)
++
++#define TM1628_CMD_SET_ADDRESS		(3 << 6)
++
++#define TM1628_BRIGHTNESS_MAX		7
++#define NUM_LED_SEGS			7
++
++/* Physical limits, depending on the mode the chip may support less */
++#define MAX_GRID_SIZE			7
++#define MAX_SEGMENT_NUM			16
++
++struct tm1628_led {
++	struct led_classdev	leddev;
++	struct tm1628		*ctrl;
++	u32			grid;
++	u32			seg;
++};
++
++struct tm1628 {
++	struct spi_device		*spi;
++	__le16				data[MAX_GRID_SIZE];
++	struct mutex			disp_lock;
++	char				text[MAX_GRID_SIZE + 1];
++	u8				segment_mapping[NUM_LED_SEGS];
++	u8				grid[MAX_GRID_SIZE];
++	int				grid_size;
++	struct tm1628_led		leds[];
++};
++
++/* Command 1: Display Mode Setting */
++static int tm1628_set_display_mode(struct spi_device *spi, u8 grid_mode)
++{
++	const u8 cmd = TM1628_CMD_DISPLAY_MODE | grid_mode;
++
++	return spi_write(spi, &cmd, 1);
++}
++
++/* Command 3: Address Setting */
++static int tm1628_set_address(struct spi_device *spi, u8 offset)
++{
++	const u8 cmd = TM1628_CMD_SET_ADDRESS | (offset * sizeof(__le16));
++
++	return spi_write(spi, &cmd, 1);
++}
++
++/* Command 2: Data Setting */
++static int tm1628_write_data(struct spi_device *spi, unsigned int offset,
++			     unsigned int len)
++{
++	struct tm1628 *s = spi_get_drvdata(spi);
++	const u8 cmd = TM1628_CMD_DATA | TM1628_DATA_WRITE_DATA;
++	struct spi_transfer xfers[] = {
++		{
++			.tx_buf = &cmd,
++			.len = 1,
++		},
++		{
++			.tx_buf = (__force void *)(s->data + offset),
++			.len = len * sizeof(__le16),
++		},
++	};
++
++	if (offset + len > MAX_GRID_SIZE) {
++		dev_err(&spi->dev, "Invalid data address offset %u len %u\n",
++			offset, len);
++		return -EINVAL;
++	}
++
++	tm1628_set_address(spi, offset);
++
++	return spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers));
++}
++
++/* Command 4: Display Control */
++static int tm1628_set_display_ctrl(struct spi_device *spi, bool on)
++{
++	u8 cmd = TM1628_CMD_DISPLAY_CTRL | TM1628_BRIGHTNESS_MAX;
++
++	if (on)
++		cmd |= TM1628_DISPLAY_CTRL_DISPLAY_ON;
++
++	return spi_write(spi, &cmd, 1);
++}
++
++static int tm1628_show_text(struct tm1628 *s)
++{
++	static SEG7_CONVERSION_MAP(map_seg7, MAP_ASCII7SEG_ALPHANUM);
++	int msg_len, i, ret;
++
++	msg_len = strlen(s->text);
++
++	mutex_lock(&s->disp_lock);
++
++	for (i = 0; i < s->grid_size; i++) {
++		int pos = s->grid[i] - 1;
++		int j, char7_raw, char7;
++
++		if (i >= msg_len) {
++			s->data[pos] = 0;
++			continue;
++		}
++
++		char7_raw = map_to_seg7(&map_seg7, s->text[i]);
++
++		for (j = 0, char7 = 0; j < NUM_LED_SEGS; j++) {
++			if (char7_raw & BIT(j))
++				char7 |= BIT(s->segment_mapping[j] - 1);
++		}
++
++		s->data[pos] = cpu_to_le16(char7);
++	}
++
++	ret = tm1628_write_data(s->spi, 0, s->grid_size);
++
++	mutex_unlock(&s->disp_lock);
++
++	return ret;
++}
++
++static int tm1628_led_set_brightness(struct led_classdev *led_cdev,
++				     enum led_brightness brightness)
++{
++	struct tm1628_led *led = container_of(led_cdev, struct tm1628_led, leddev);
++	struct tm1628 *s = led->ctrl;
++	int ret, offset = led->grid - 1;
++	__le16 bit = cpu_to_le16(BIT(led->seg - 1));
++
++	mutex_lock(&s->disp_lock);
++
++	if (brightness == LED_OFF)
++		s->data[offset] &= ~bit;
++	else
++		s->data[offset] |= bit;
++
++	ret = tm1628_write_data(s->spi, offset, 1);
++
++	mutex_unlock(&s->disp_lock);
++
++	return ret;
++}
++
++static enum led_brightness tm1628_led_get_brightness(struct led_classdev *led_cdev)
++{
++	struct tm1628_led *led = container_of(led_cdev, struct tm1628_led, leddev);
++	struct tm1628 *s = led->ctrl;
++	int offset = led->grid - 1;
++	__le16 bit = cpu_to_le16(BIT(led->seg - 1));
++	bool on;
++
++	mutex_lock(&s->disp_lock);
++	on = s->data[offset] & bit;
++	mutex_unlock(&s->disp_lock);
++
++	return on ? LED_ON : LED_OFF;
++}
++
++static int tm1628_register_led(struct tm1628 *s, struct fwnode_handle *node,
++			       u32 grid, u32 seg, struct tm1628_led *led)
++{
++	struct device *dev = &s->spi->dev;
++	struct led_init_data init_data = { .fwnode = node };
++
++	led->ctrl = s;
++	led->grid = grid;
++	led->seg  = seg;
++	led->leddev.max_brightness = LED_ON;
++	led->leddev.brightness_set_blocking = tm1628_led_set_brightness;
++	led->leddev.brightness_get = tm1628_led_get_brightness;
++
++	return devm_led_classdev_register_ext(dev, &led->leddev, &init_data);
++}
++
++static ssize_t display_text_show(struct device *dev, struct device_attribute *attr,
++				 char *buf)
++{
++	struct tm1628 *s = dev_get_drvdata(dev);
++
++	return sysfs_emit(buf, "%s\n", s->text);
++}
++
++static ssize_t display_text_store(struct device *dev, struct device_attribute *attr,
++				  const char *buf, size_t count)
++{
++	struct tm1628 *s = dev_get_drvdata(dev);
++	int ret, i;
++
++	for (i = 0; i < count && i < s->grid_size && isprint(buf[i]); i++)
++		s->text[i] = buf[i];
++
++	s->text[i] = '\0';
++
++	ret = tm1628_show_text(s);
++	if (ret < 0)
++		return ret;
++
++	return count;
++}
++
++static const DEVICE_ATTR_RW(display_text);
++
++static int tm1628_spi_probe(struct spi_device *spi)
++{
++	struct fwnode_handle *child;
++	unsigned int num_leds;
++	struct tm1628 *s;
++	int ret, i;
++
++	num_leds = device_get_child_node_count(&spi->dev);
++
++	s = devm_kzalloc(&spi->dev, struct_size(s, leds, num_leds), GFP_KERNEL);
++	if (!s)
++		return -ENOMEM;
++
++	s->spi = spi;
++	spi_set_drvdata(spi, s);
++
++	mutex_init(&s->disp_lock);
++
++	/* According to TM1628 datasheet */
++	msleep(200);
++
++	/* Clear screen */
++	ret = tm1628_write_data(spi, 0, MAX_GRID_SIZE);
++	if (ret)
++		return ret;
++
++	/* For now we support 6x12 mode only. This should be sufficient for most use cases */
++	ret = tm1628_set_display_mode(spi, TM1628_DISPLAY_MODE_6_12);
++	if (ret)
++		return ret;
++
++	ret = tm1628_set_display_ctrl(spi, true);
++	if (ret)
++		return ret;
++
++	num_leds = 0;
++
++	if (!IS_REACHABLE(CONFIG_LEDS_CLASS))
++		goto no_leds;
++
++	device_for_each_child_node(&spi->dev, child) {
++		u32 reg[2];
++
++		ret = fwnode_property_read_u32_array(child, "reg", reg, 2);
++		if (ret) {
++			dev_err(&spi->dev, "Reading %s reg property failed (%d)\n",
++				fwnode_get_name(child), ret);
++			continue;
++		}
++
++		if (reg[0] == 0 || reg[0] > MAX_GRID_SIZE) {
++			dev_err(&spi->dev, "Invalid grid %u at %s\n",
++				reg[0], fwnode_get_name(child));
++			continue;
++		}
++
++		if (reg[1] == 0 || reg[1] > MAX_SEGMENT_NUM) {
++			dev_err(&spi->dev, "Invalid segment %u at %s\n",
++				reg[1], fwnode_get_name(child));
++			continue;
++		}
++
++		ret = tm1628_register_led(s, child, reg[0], reg[1], s->leds + num_leds);
++		if (ret) {
++			dev_err(&spi->dev, "Failed to register LED %s (%d)\n",
++				fwnode_get_name(child), ret);
++			continue;
++		}
++		num_leds++;
++	}
++
++no_leds:
++	ret = device_property_count_u8(&spi->dev, "titanmec,grid");
++	if (ret < 1 || ret > MAX_GRID_SIZE) {
++		dev_err(&spi->dev, "Invalid display length (%d)\n", ret);
++		return -EINVAL;
++	}
++
++	s->grid_size = ret;
++
++	ret = device_property_read_u8_array(&spi->dev, "titanmec,grid", s->grid, s->grid_size);
++	if (ret < 0)
++		return ret;
++
++	for (i = 0; i < s->grid_size; i++) {
++		if (s->grid[i] < 1 || s->grid[i] > s->grid_size)
++			return -EINVAL;
++	}
++
++	ret = device_property_read_u8_array(&spi->dev, "titanmec,segment-mapping",
++					    s->segment_mapping, NUM_LED_SEGS);
++	if (ret < 0)
++		return ret;
++
++	for (i = 0; i < NUM_LED_SEGS; i++) {
++		if (s->segment_mapping[i] < 1 || s->segment_mapping[i] > MAX_SEGMENT_NUM)
++			return -EINVAL;
++	}
++
++	ret = device_create_file(&spi->dev, &dev_attr_display_text);
++	if (ret)
++		return ret;
++
++	dev_info(&spi->dev, "Configured display with %u digits and %u symbols\n",
++		 s->grid_size, num_leds);
++
++	return 0;
++}
++
++static void tm1628_spi_remove(struct spi_device *spi)
++{
++	device_remove_file(&spi->dev, &dev_attr_display_text);
++	tm1628_set_display_ctrl(spi, false);
++}
++
++static void tm1628_spi_shutdown(struct spi_device *spi)
++{
++	tm1628_set_display_ctrl(spi, false);
++}
++
++static const struct of_device_id tm1628_spi_of_matches[] = {
++	{ .compatible = "titanmec,tm1628" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, tm1628_spi_of_matches);
++
++static const struct spi_device_id tm1628_spi_id_table[] = {
++	{ "tm1628" },
++	{},
++};
++MODULE_DEVICE_TABLE(spi, tm1628_spi_id_table);
++
++static struct spi_driver tm1628_spi_driver = {
++	.probe = tm1628_spi_probe,
++	.remove = tm1628_spi_remove,
++	.shutdown = tm1628_spi_shutdown,
++	.id_table = tm1628_spi_id_table,
++
++	.driver = {
++		.name = "tm1628",
++		.of_match_table = tm1628_spi_of_matches,
++	},
++};
++module_spi_driver(tm1628_spi_driver);
++
++MODULE_DESCRIPTION("TM1628 LED controller driver");
++MODULE_AUTHOR("Andreas Färber <afaerber@suse.de>");
++MODULE_AUTHOR("Heiner Kallweit <hkallweit1@gmail.com>");
++MODULE_LICENSE("GPL");
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch b/patch/kernel/archive/meson64-6.10/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch
new file mode 100644
index 000000000000..e7d09fac12d2
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch
@@ -0,0 +1,30 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 9 Jul 2018 21:25:15 +0200
+Subject: TEMP: drm: dw-hdmi: call hdmi_set_cts_n after clock is enabled
+
+Unknown patch. Archeology:
+- 99f6bef7de297253a659c22d4a35343a209f98b8: Igor Pecovnik <igorpecovnik@users.noreply.github.com>: 'Attach Meson64 CURRENT to 5.6.y and make DEV = CURRENT at this point. (#1956)'
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -768,6 +768,11 @@ static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
+ 	else
+ 		hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
+ 	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
++
++	if (enable) {
++		hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
++		hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
++	}
+ }
+ 
+ static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-drm-panfrost-fix-reference-leak.patch b/patch/kernel/archive/meson64-6.10/general-drm-panfrost-fix-reference-leak.patch
new file mode 100644
index 000000000000..97fb7f4d7a77
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-drm-panfrost-fix-reference-leak.patch
@@ -0,0 +1,38 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Qinglang Miao <miaoqinglang@huawei.com>
+Date: Sat, 28 Nov 2020 16:10:04 +0000
+Subject: drm/panfrost: fix reference leak in panfrost_job_hw_submit
+
+pm_runtime_get_sync will increment pm usage counter even it
+failed. Forgetting to putting operation will result in a
+reference leak here.
+
+A new function pm_runtime_resume_and_get is introduced in
+[0] to keep usage counter balanced. So We fix the reference
+leak by replacing it with new funtion.
+
+[0] dd8088d5a896 ("PM: runtime: Add  pm_runtime_resume_and_get to deal with usage counter")
+
+Fixes: f3ba91228e8e ("drm/panfrost: Add initial panfrost driver")
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
+---
+ drivers/gpu/drm/panfrost/panfrost_job.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/panfrost/panfrost_job.c
++++ b/drivers/gpu/drm/panfrost/panfrost_job.c
+@@ -204,7 +204,7 @@ static void panfrost_job_hw_submit(struct panfrost_job *job, int js)
+ 
+ 	panfrost_devfreq_record_busy(&pfdev->pfdevfreq);
+ 
+-	ret = pm_runtime_get_sync(pfdev->dev);
++	ret = pm_runtime_resume_and_get(pfdev->dev);
+ 	if (ret < 0)
+ 		return;
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-fix-Kodi-sysinfo-CPU-information.patch b/patch/kernel/archive/meson64-6.10/general-fix-Kodi-sysinfo-CPU-information.patch
new file mode 100644
index 000000000000..fc69ccc7fd77
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-fix-Kodi-sysinfo-CPU-information.patch
@@ -0,0 +1,31 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Sat, 13 Apr 2019 05:45:18 +0000
+Subject: HACK: arm64: fix Kodi sysinfo CPU information
+
+This allows the CPU information to show in the Kodi sysinfo screen, e.g.
+
+"ARMv8 Processor rev 4 (v81)" on Amlogic devices
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+---
+ arch/arm64/kernel/cpuinfo.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
+index 111111111111..222222222222 100644
+--- a/arch/arm64/kernel/cpuinfo.c
++++ b/arch/arm64/kernel/cpuinfo.c
+@@ -205,8 +205,7 @@ static int c_show(struct seq_file *m, void *v)
+ 		 * "processor".  Give glibc what it expects.
+ 		 */
+ 		seq_printf(m, "processor\t: %d\n", i);
+-		if (compat)
+-			seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
++		seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
+ 				   MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
+ 
+ 		seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-gpu-drm-add-new-display-resolution-2560x1440.patch b/patch/kernel/archive/meson64-6.10/general-gpu-drm-add-new-display-resolution-2560x1440.patch
new file mode 100644
index 000000000000..58d2d168894a
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-gpu-drm-add-new-display-resolution-2560x1440.patch
@@ -0,0 +1,72 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Dongjin Kim <tobetter@gmail.com>
+Date: Thu, 10 Sep 2020 11:01:33 +0900
+Subject: ODROID-COMMON: gpu/drm: add new display resolution 2560x1440
+
+Signed-off-by: Joy Cho <joy.cho@hardkernel.com>
+Signed-off-by: Dongjin Kim <tobetter@gmail.com>
+- rpardini: hammer for 6.4-rc5
+---
+ drivers/gpu/drm/meson/meson_vclk.c | 18 ++++++++++
+ drivers/gpu/drm/meson/meson_venc.c |  2 +-
+ 2 files changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_vclk.c
++++ b/drivers/gpu/drm/meson/meson_vclk.c
+@@ -357,6 +357,8 @@ enum {
+ 	MESON_VCLK_HDMI_594000,
+ /* 2970 /1 /1 /1 /5 /1  => /1 /2 */
+ 	MESON_VCLK_HDMI_594000_YUV420,
++/* 4830 /2 /1 /2 /5 /1  => /1 /1 */
++	MESON_VCLK_HDMI_241500,
+ };
+ 
+ struct meson_vclk_params {
+@@ -467,6 +469,18 @@ struct meson_vclk_params {
+ 		.vid_pll_div = VID_PLL_DIV_5,
+ 		.vclk_div = 1,
+ 	},
++	[MESON_VCLK_HDMI_241500] = {
++		.pll_freq = 4830000,
++		.phy_freq = 2415000,
++		.venc_freq = 241500,
++		.vclk_freq = 241500,
++		.pixel_freq = 241500,
++		.pll_od1 = 2,
++		.pll_od2 = 1,
++		.pll_od3 = 2,
++		.vid_pll_div = VID_PLL_DIV_5,
++		.vclk_div = 1,
++	},
+ 	{ /* sentinel */ },
+ };
+ 
+@@ -873,6 +887,10 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
+ 			m = 0xf7;
+ 			frac = vic_alternate_clock ? 0x8148 : 0x10000;
+ 			break;
++		case 4830000:
++			m = 0xc9;
++			frac = 0xd560;
++			break;
+ 		}
+ 
+ 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
+diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/meson/meson_venc.c
++++ b/drivers/gpu/drm/meson/meson_venc.c
+@@ -868,7 +868,7 @@ meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
+ 			    DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))
+ 		return MODE_BAD;
+ 
+-	if (mode->hdisplay < 400 || mode->hdisplay > 1920)
++	if (mode->hdisplay < 400 || mode->hdisplay > 2560)
+ 		return MODE_BAD_HVALUE;
+ 
+ 	if (mode->vdisplay < 480 || mode->vdisplay > 1920)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-hdmi-codec-reorder-channel-allocation-list.patch b/patch/kernel/archive/meson64-6.10/general-hdmi-codec-reorder-channel-allocation-list.patch
new file mode 100644
index 000000000000..78bb460cfc7d
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-hdmi-codec-reorder-channel-allocation-list.patch
@@ -0,0 +1,202 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 23 Dec 2018 02:24:38 +0100
+Subject: WIP: ASoC: hdmi-codec: reorder channel allocation list
+
+Wrong channel allocation is selected by hdmi_codec_get_ch_alloc_table_idx().
+
+E.g when ELD reports FL|FR|LFE|FC|RL|RR or FL|FR|LFE|FC|RL|RR|RC|RLC|RRC
+
+ca_id 0x01 with speaker mask FL|FR|LFE gets selected instead of
+ca_id 0x03 with speaker mask FL|FR|LFE|FC for 4 channels
+
+and
+
+ca_id 0x04 with speaker mask FL|FR|RC gets selected instead of
+ca_id 0x0b with speaker mask FL|FR|LFE|FC|RL|RR for 6 channels
+
+Fix this by reorder the channel allocation list with
+most specific speaker mask at the top.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ sound/soc/codecs/hdmi-codec.c | 140 +++++-----
+ 1 file changed, 77 insertions(+), 63 deletions(-)
+
+diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c
+index 111111111111..222222222222 100644
+--- a/sound/soc/codecs/hdmi-codec.c
++++ b/sound/soc/codecs/hdmi-codec.c
+@@ -185,84 +185,97 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = {
+ /*
+  * hdmi_codec_channel_alloc: speaker configuration available for CEA
+  *
+- * This is an ordered list that must match with hdmi_codec_8ch_chmaps struct
++ * This is an ordered list where ca_id must exist in hdmi_codec_8ch_chmaps
+  * The preceding ones have better chances to be selected by
+  * hdmi_codec_get_ch_alloc_table_idx().
+  */
+ static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
+ 	{ .ca_id = 0x00, .n_ch = 2,
+-	  .mask = FL | FR},
+-	/* 2.1 */
+-	{ .ca_id = 0x01, .n_ch = 4,
+-	  .mask = FL | FR | LFE},
+-	/* Dolby Surround */
++	  .mask = FL | FR },
++	{ .ca_id = 0x03, .n_ch = 4,
++	  .mask = FL | FR | LFE | FC },
+ 	{ .ca_id = 0x02, .n_ch = 4,
+ 	  .mask = FL | FR | FC },
+-	/* surround51 */
++	{ .ca_id = 0x01, .n_ch = 4,
++	  .mask = FL | FR | LFE },
+ 	{ .ca_id = 0x0b, .n_ch = 6,
+-	  .mask = FL | FR | LFE | FC | RL | RR},
+-	/* surround40 */
+-	{ .ca_id = 0x08, .n_ch = 6,
+-	  .mask = FL | FR | RL | RR },
+-	/* surround41 */
+-	{ .ca_id = 0x09, .n_ch = 6,
+-	  .mask = FL | FR | LFE | RL | RR },
+-	/* surround50 */
++	  .mask = FL | FR | LFE | FC | RL | RR },
+ 	{ .ca_id = 0x0a, .n_ch = 6,
+ 	  .mask = FL | FR | FC | RL | RR },
+-	/* 6.1 */
+-	{ .ca_id = 0x0f, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RL | RR | RC },
+-	/* surround71 */
++	{ .ca_id = 0x09, .n_ch = 6,
++	  .mask = FL | FR | LFE | RL | RR },
++	{ .ca_id = 0x08, .n_ch = 6,
++	  .mask = FL | FR | RL | RR },
++	{ .ca_id = 0x07, .n_ch = 6,
++	  .mask = FL | FR | LFE | FC | RC },
++	{ .ca_id = 0x06, .n_ch = 6,
++	  .mask = FL | FR | FC | RC },
++	{ .ca_id = 0x05, .n_ch = 6,
++	  .mask = FL | FR | LFE | RC },
++	{ .ca_id = 0x04, .n_ch = 6,
++	  .mask = FL | FR | RC },
+ 	{ .ca_id = 0x13, .n_ch = 8,
+ 	  .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
+-	/* others */
+-	{ .ca_id = 0x03, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC },
+-	{ .ca_id = 0x04, .n_ch = 8,
+-	  .mask = FL | FR | RC},
+-	{ .ca_id = 0x05, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC },
+-	{ .ca_id = 0x06, .n_ch = 8,
+-	  .mask = FL | FR | FC | RC },
+-	{ .ca_id = 0x07, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RC },
+-	{ .ca_id = 0x0c, .n_ch = 8,
+-	  .mask = FL | FR | RC | RL | RR },
+-	{ .ca_id = 0x0d, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | RC },
+-	{ .ca_id = 0x0e, .n_ch = 8,
+-	  .mask = FL | FR | FC | RL | RR | RC },
+-	{ .ca_id = 0x10, .n_ch = 8,
+-	  .mask = FL | FR | RL | RR | RLC | RRC },
+-	{ .ca_id = 0x11, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1f, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
+ 	{ .ca_id = 0x12, .n_ch = 8,
+ 	  .mask = FL | FR | FC | RL | RR | RLC | RRC },
+-	{ .ca_id = 0x14, .n_ch = 8,
+-	  .mask = FL | FR | FLC | FRC },
+-	{ .ca_id = 0x15, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FLC | FRC },
+-	{ .ca_id = 0x16, .n_ch = 8,
+-	  .mask = FL | FR | FC | FLC | FRC },
+-	{ .ca_id = 0x17, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | FLC | FRC },
+-	{ .ca_id = 0x18, .n_ch = 8,
+-	  .mask = FL | FR | RC | FLC | FRC },
+-	{ .ca_id = 0x19, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC | FLC | FRC },
+-	{ .ca_id = 0x1a, .n_ch = 8,
+-	  .mask = FL | FR | RC | FC | FLC | FRC },
+-	{ .ca_id = 0x1b, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC | FC | FLC | FRC },
+-	{ .ca_id = 0x1c, .n_ch = 8,
+-	  .mask = FL | FR | RL | RR | FLC | FRC },
+-	{ .ca_id = 0x1d, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | FLC | FRC },
+ 	{ .ca_id = 0x1e, .n_ch = 8,
+ 	  .mask = FL | FR | FC | RL | RR | FLC | FRC },
+-	{ .ca_id = 0x1f, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
++	{ .ca_id = 0x11, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1d, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | FLC | FRC },
++	{ .ca_id = 0x10, .n_ch = 8,
++	  .mask = FL | FR | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1c, .n_ch = 8,
++	  .mask = FL | FR | RL | RR | FLC | FRC },
++	{ .ca_id = 0x0f, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | RL | RR | RC },
++	{ .ca_id = 0x1b, .n_ch = 8,
++	  .mask = FL | FR | LFE | RC | FC | FLC | FRC },
++	{ .ca_id = 0x0e, .n_ch = 8,
++	  .mask = FL | FR | FC | RL | RR | RC },
++	{ .ca_id = 0x1a, .n_ch = 8,
++	  .mask = FL | FR | RC | FC | FLC | FRC },
++	{ .ca_id = 0x0d, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | RC },
++	{ .ca_id = 0x19, .n_ch = 8,
++	  .mask = FL | FR | LFE | RC | FLC | FRC },
++	{ .ca_id = 0x0c, .n_ch = 8,
++	  .mask = FL | FR | RC | RL | RR },
++	{ .ca_id = 0x18, .n_ch = 8,
++	  .mask = FL | FR | RC | FLC | FRC },
++	{ .ca_id = 0x17, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | FLC | FRC },
++	{ .ca_id = 0x16, .n_ch = 8,
++	  .mask = FL | FR | FC | FLC | FRC },
++	{ .ca_id = 0x15, .n_ch = 8,
++	  .mask = FL | FR | LFE | FLC | FRC },
++	{ .ca_id = 0x14, .n_ch = 8,
++	  .mask = FL | FR | FLC | FRC },
++	{ .ca_id = 0x0b, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | RL | RR },
++	{ .ca_id = 0x0a, .n_ch = 8,
++	  .mask = FL | FR | FC | RL | RR },
++	{ .ca_id = 0x09, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR },
++	{ .ca_id = 0x08, .n_ch = 8,
++	  .mask = FL | FR | RL | RR },
++	{ .ca_id = 0x07, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | RC },
++	{ .ca_id = 0x06, .n_ch = 8,
++	  .mask = FL | FR | FC | RC },
++	{ .ca_id = 0x05, .n_ch = 8,
++	  .mask = FL | FR | LFE | RC },
++	{ .ca_id = 0x04, .n_ch = 8,
++	  .mask = FL | FR | RC },
++	{ .ca_id = 0x03, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC },
++	{ .ca_id = 0x02, .n_ch = 8,
++	  .mask = FL | FR | FC },
++	{ .ca_id = 0x01, .n_ch = 8,
++	  .mask = FL | FR | LFE },
+ };
+ 
+ struct hdmi_codec_priv {
+@@ -371,7 +384,8 @@ static int hdmi_codec_chmap_ctl_get(struct snd_kcontrol *kcontrol,
+ 	struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
+ 	struct hdmi_codec_priv *hcp = info->private_data;
+ 
+-	map = info->chmap[hcp->chmap_idx].map;
++	if (hcp->chmap_idx != HDMI_CODEC_CHMAP_IDX_UNKNOWN)
++		map = info->chmap[hcp->chmap_idx].map;
+ 
+ 	for (i = 0; i < info->max_channels; i++) {
+ 		if (hcp->chmap_idx == HDMI_CODEC_CHMAP_IDX_UNKNOWN)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-input-touchscreen-Add-D-WAV-Multitouch.patch b/patch/kernel/archive/meson64-6.10/general-input-touchscreen-Add-D-WAV-Multitouch.patch
new file mode 100644
index 000000000000..ba6d7f51ad52
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-input-touchscreen-Add-D-WAV-Multitouch.patch
@@ -0,0 +1,636 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Hyeonki Hong <hhk7734@gmail.com>
+Date: Thu, 5 Mar 2020 19:01:43 +0900
+Subject: ODROID-COMMON: input/touchscreen: Add D-WAV Multitouch driver.
+
+Change-Id: Ia1c8c29d3f69c6ba5d630279c4cc98119b68ab71
+---
+ drivers/hid/hid-ids.h                   |   6 +
+ drivers/hid/hid-quirks.c                |   3 +
+ drivers/input/touchscreen/Kconfig       |  10 +
+ drivers/input/touchscreen/Makefile      |   1 +
+ drivers/input/touchscreen/dwav-usb-mt.c | 554 ++++++++++
+ 5 files changed, 574 insertions(+)
+
+diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
+index 111111111111..222222222222 100644
+--- a/drivers/hid/hid-ids.h
++++ b/drivers/hid/hid-ids.h
+@@ -1481,4 +1481,10 @@
+ #define USB_VENDOR_ID_SIGNOTEC			0x2133
+ #define USB_DEVICE_ID_SIGNOTEC_VIEWSONIC_PD1011	0x0018
+ 
++#define USB_DEVICE_ID_DWAV_MULTITOUCH	0x0005
++
++#define USB_VENDOR_ID_ODROID	0x16b4
++#define USB_DEVICE_ID_VU5	0x0704
++#define USB_DEVICE_ID_VU7PLUS	0x0705
++
+ #endif
+diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c
+index 111111111111..222222222222 100644
+--- a/drivers/hid/hid-quirks.c
++++ b/drivers/hid/hid-quirks.c
+@@ -891,6 +891,9 @@ static const struct hid_device_id hid_ignore_list[] = {
+ 	{ HID_USB_DEVICE(USB_VENDOR_ID_SYNAPTICS, USB_DEVICE_ID_SYNAPTICS_DPAD) },
+ #endif
+ 	{ HID_USB_DEVICE(USB_VENDOR_ID_YEALINK, USB_DEVICE_ID_YEALINK_P1K_P4K_B2K) },
++
++	{ HID_USB_DEVICE(USB_VENDOR_ID_ODROID, USB_DEVICE_ID_VU5) },
++	{ HID_USB_DEVICE(USB_VENDOR_ID_ODROID, USB_DEVICE_ID_VU7PLUS) },
+ 	{ }
+ };
+ 
+diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/input/touchscreen/Kconfig
++++ b/drivers/input/touchscreen/Kconfig
+@@ -1430,4 +1430,14 @@ config TOUCHSCREEN_HIMAX_HX83112B
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called himax_hx83112b.
+ 
++config TOUCHSCREEN_DWAV_USB_MT
++	tristate "D-WAV Scientific USB MultiTouch"
++	depends on USB_ARCH_HAS_HCD
++	select USB
++	help
++	  Say Y here if you have a D-WAV Scientific USB(HID) based MultiTouch
++	  controller.
++
++	  module will be called dwav-usb-mt.
++
+ endif
+diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/input/touchscreen/Makefile
++++ b/drivers/input/touchscreen/Makefile
+@@ -120,4 +120,5 @@ obj-$(CONFIG_TOUCHSCREEN_RASPBERRYPI_FW)	+= raspberrypi-ts.o
+ obj-$(CONFIG_TOUCHSCREEN_IQS5XX)	+= iqs5xx.o
+ obj-$(CONFIG_TOUCHSCREEN_IQS7211)	+= iqs7211.o
+ obj-$(CONFIG_TOUCHSCREEN_ZINITIX)	+= zinitix.o
++obj-$(CONFIG_TOUCHSCREEN_DWAV_USB_MT)	+= dwav-usb-mt.o
+ obj-$(CONFIG_TOUCHSCREEN_HIMAX_HX83112B)	+= himax_hx83112b.o
+diff --git a/drivers/input/touchscreen/dwav-usb-mt.c b/drivers/input/touchscreen/dwav-usb-mt.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/input/touchscreen/dwav-usb-mt.c
+@@ -0,0 +1,554 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * D-WAV Scientific USB(HID) MultiTouch Screen Driver(Based on usbtouchscreen.c)
++ *
++ * Copyright (C) Hardkernel, 2015
++ */
++
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/input.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/usb.h>
++#include <linux/usb/input.h>
++#include <linux/hid.h>
++
++#include <linux/input/mt.h>
++
++#define USB_VENDOR_ID_DWAV	0x0eef	/* 800 x 480, 7" DWAV touch */
++#define USB_DEVICE_ID_VU7	0x0005
++
++#define USB_VENDOR_ID_ODROID	0x16b4
++#define	USB_DEVICE_ID_VU5	0x0704
++#define	USB_DEVICE_ID_VU7PLUS	0x0705
++
++enum	{
++	ODROID_VU7 = 0,	/* 800 x 480, 7" Touch */
++	ODROID_VU5,	/* 800 x 480, 5" Touch */
++	ODROID_VU7PLUS,	/* 1024 x 600, 7" Touch */
++};
++
++struct usbtouch_device_info	{
++	char	name[64];
++	int	max_x;
++	int	max_y;
++	int	max_press;
++	int	max_finger;
++};
++
++const struct usbtouch_device_info DEV_INFO[] = {
++	[ODROID_VU7] = {
++		.name = "ODROID VU7 MultiTouch(800x480)",
++		.max_x = 800,
++		.max_y = 480,
++		.max_press = 255,
++		.max_finger = 5,
++	},
++	[ODROID_VU5] = {
++		.name = "ODROID VU5 MultiTouch(800x480)",
++		.max_x = 800,
++		.max_y = 480,
++		.max_press = 255,
++		.max_finger = 5,
++	},
++	[ODROID_VU7PLUS] = {
++		.name = "ODROID VU7 Plus MultiTouch(1024x600)",
++		.max_x = 1024,
++		.max_y = 600,
++		.max_press = 255,
++		.max_finger = 5,
++	},
++};
++
++static const struct usb_device_id dwav_usb_mt_devices[] = {
++	{USB_DEVICE(USB_VENDOR_ID_DWAV,   USB_DEVICE_ID_VU7),
++		.driver_info = ODROID_VU7},
++	{USB_DEVICE(USB_VENDOR_ID_ODROID, USB_DEVICE_ID_VU5),
++		.driver_info = ODROID_VU5},
++	{USB_DEVICE(USB_VENDOR_ID_ODROID, USB_DEVICE_ID_VU7PLUS),
++		.driver_info = ODROID_VU7PLUS},
++	{}
++};
++
++struct dwav_raw {                   /* Total 25 bytes */
++	unsigned char   header;     /* frame header 0xAA*/
++	unsigned char   press;
++	/* Touch flag (1:valid touch data, 0:touch finished) */
++	unsigned short  x1;         /* 1st x */
++	unsigned short  y1;         /* 1st y */
++	unsigned char   end;
++	/* 1st touch finish flags 0xBB, RPI only uses the first 7 bytes */
++	unsigned char   ids;        /* touch ID(bit field) */
++	unsigned short  y2;
++	unsigned short  x2;
++	unsigned short  y3;
++	unsigned short  x3;
++	unsigned short  y4;
++	unsigned short  x4;
++	unsigned short  y5;
++	unsigned short  x5;
++	unsigned char   tail;       /* frame end 0xCC */
++};
++
++#define	TS_EVENT_UNKNOWN	0x00
++#define	TS_EVENT_PRESS		0x01
++#define	TS_EVENT_RELEASE	0x02
++
++struct	finger_t	{
++	unsigned int	status;	/* ts event type */
++	unsigned int	x;	/* ts data x */
++	unsigned int	y;	/* ts data y */
++}	__packed;
++
++struct dwav_usb_mt  {
++	char		name[128], phys[64];
++
++	int		dev_id;
++	/* for URB Data DMA */
++	dma_addr_t	data_dma;
++	unsigned char	*data;
++	int		data_size;
++
++	struct urb		*irq;
++	struct usb_interface	*interface;
++	struct input_dev	*input;
++
++	struct finger_t		*finger;
++};
++
++static void dwav_usb_mt_report(struct dwav_usb_mt *dwav_usb_mt)
++{
++	int	id, max_x, max_y, max_press, max_finger;
++
++	max_x = DEV_INFO[dwav_usb_mt->dev_id].max_x;
++	max_y = DEV_INFO[dwav_usb_mt->dev_id].max_y;
++	max_press = DEV_INFO[dwav_usb_mt->dev_id].max_press;
++	max_finger = DEV_INFO[dwav_usb_mt->dev_id].max_finger;
++
++	for (id = 0; id < max_finger; id++)	{
++
++		if (dwav_usb_mt->finger[id].status == TS_EVENT_UNKNOWN)
++			continue;
++
++		if (dwav_usb_mt->finger[id].x >= max_x ||
++		    dwav_usb_mt->finger[id].y >= max_y)
++			continue;
++
++		input_mt_slot(dwav_usb_mt->input, id);
++
++		if (dwav_usb_mt->finger[id].status != TS_EVENT_RELEASE) {
++			input_mt_report_slot_state(dwav_usb_mt->input,
++					MT_TOOL_FINGER, true);
++			input_report_abs(dwav_usb_mt->input,
++					ABS_MT_POSITION_X,
++					dwav_usb_mt->finger[id].x);
++			input_report_abs(dwav_usb_mt->input,
++					ABS_MT_POSITION_Y,
++					dwav_usb_mt->finger[id].y);
++			input_report_abs(dwav_usb_mt->input,
++					ABS_MT_PRESSURE,
++					max_press);
++		} else {
++			input_mt_report_slot_state(dwav_usb_mt->input,
++					MT_TOOL_FINGER, false);
++			dwav_usb_mt->finger[id].status = TS_EVENT_UNKNOWN;
++		}
++		input_mt_report_pointer_emulation(dwav_usb_mt->input, true);
++		input_sync(dwav_usb_mt->input);
++	}
++}
++
++static void dwav_usb_mt_process(struct dwav_usb_mt *dwav_usb_mt,
++		unsigned char *pkt, int len)
++{
++	struct  dwav_raw *dwav_raw = (struct dwav_raw *)pkt;
++	unsigned char bit_mask, cnt;
++
++	for (cnt = 0, bit_mask = 0x01;
++	     cnt < DEV_INFO[dwav_usb_mt->dev_id].max_finger;
++	     cnt++, bit_mask <<= 1) {
++		if ((dwav_raw->ids & bit_mask) && dwav_raw->press) {
++			dwav_usb_mt->finger[cnt].status = TS_EVENT_PRESS;
++			switch (cnt) {
++			case	0:
++				dwav_usb_mt->finger[cnt].x
++					= cpu_to_be16(dwav_raw->x1);
++				dwav_usb_mt->finger[cnt].y
++					= cpu_to_be16(dwav_raw->y1);
++				break;
++			case	1:
++				dwav_usb_mt->finger[cnt].x
++					= cpu_to_be16(dwav_raw->x2);
++				dwav_usb_mt->finger[cnt].y
++					= cpu_to_be16(dwav_raw->y2);
++				break;
++			case	2:
++				dwav_usb_mt->finger[cnt].x
++					= cpu_to_be16(dwav_raw->x3);
++				dwav_usb_mt->finger[cnt].y
++					= cpu_to_be16(dwav_raw->y3);
++				break;
++			case	3:
++				dwav_usb_mt->finger[cnt].x
++					= cpu_to_be16(dwav_raw->x4);
++				dwav_usb_mt->finger[cnt].y
++					= cpu_to_be16(dwav_raw->y4);
++				break;
++			case	4:
++				dwav_usb_mt->finger[cnt].x
++					= cpu_to_be16(dwav_raw->x5);
++				dwav_usb_mt->finger[cnt].y
++					= cpu_to_be16(dwav_raw->y5);
++				break;
++			default:
++				break;
++			}
++		} else {
++			if (dwav_usb_mt->finger[cnt].status == TS_EVENT_PRESS)
++				dwav_usb_mt->finger[cnt].status
++					= TS_EVENT_RELEASE;
++			else
++				dwav_usb_mt->finger[cnt].status
++					= TS_EVENT_UNKNOWN;
++		}
++	}
++	dwav_usb_mt_report(dwav_usb_mt);
++}
++
++static void dwav_usb_mt_irq(struct urb *urb)
++{
++	struct dwav_usb_mt *dwav_usb_mt = urb->context;
++	struct device *dev = &dwav_usb_mt->interface->dev;
++	int retval;
++
++	switch (urb->status) {
++	case 0:
++		/* success */
++		break;
++	case -ETIME:
++		/* this urb is timing out */
++		dev_dbg(dev, "%s - urb timed out - was the device unplugged?\n",
++				__func__);
++		return;
++	case -ECONNRESET:
++	case -ENOENT:
++	case -ESHUTDOWN:
++	case -EPIPE:
++		/* this urb is terminated, clean up */
++		dev_dbg(dev, "%s - urb shutting down with status: %d\n",
++				__func__, urb->status);
++		return;
++	default:
++		dev_dbg(dev, "%s - nonzero urb status received: %d\n",
++				__func__, urb->status);
++		goto exit;
++	}
++
++	dwav_usb_mt_process(dwav_usb_mt, dwav_usb_mt->data, urb->actual_length);
++
++exit:
++	usb_mark_last_busy(interface_to_usbdev(dwav_usb_mt->interface));
++	retval = usb_submit_urb(urb, GFP_ATOMIC);
++	if (retval) {
++		dev_err(dev, "%s - usb_submit_urb failed with result: %d\n",
++				__func__, retval);
++	}
++}
++
++static int dwav_usb_mt_open(struct input_dev *input)
++{
++	struct dwav_usb_mt *dwav_usb_mt = input_get_drvdata(input);
++	int r;
++
++	dwav_usb_mt->irq->dev = interface_to_usbdev(dwav_usb_mt->interface);
++
++	r = usb_autopm_get_interface(dwav_usb_mt->interface) ? -EIO : 0;
++	if (r < 0)
++		goto out;
++
++	if (usb_submit_urb(dwav_usb_mt->irq, GFP_KERNEL)) {
++		r = -EIO;
++		goto out_put;
++	}
++
++	dwav_usb_mt->interface->needs_remote_wakeup = 1;
++out_put:
++	usb_autopm_put_interface(dwav_usb_mt->interface);
++out:
++	return r;
++}
++
++static void dwav_usb_mt_close(struct input_dev *input)
++{
++	struct dwav_usb_mt *dwav_usb_mt = input_get_drvdata(input);
++	int r;
++
++	usb_kill_urb(dwav_usb_mt->irq);
++
++	r = usb_autopm_get_interface(dwav_usb_mt->interface);
++
++	dwav_usb_mt->interface->needs_remote_wakeup = 0;
++	if (!r)
++		usb_autopm_put_interface(dwav_usb_mt->interface);
++}
++
++static int dwav_usb_mt_suspend(struct usb_interface *intf, pm_message_t message)
++{
++	struct dwav_usb_mt *dwav_usb_mt = usb_get_intfdata(intf);
++
++	usb_kill_urb(dwav_usb_mt->irq);
++
++	return 0;
++}
++
++static int dwav_usb_mt_resume(struct usb_interface *intf)
++{
++	struct dwav_usb_mt *dwav_usb_mt = usb_get_intfdata(intf);
++	struct input_dev *input = dwav_usb_mt->input;
++	int result = 0;
++
++	mutex_lock(&input->mutex);
++	if (input->users)
++		result = usb_submit_urb(dwav_usb_mt->irq, GFP_NOIO);
++	mutex_unlock(&input->mutex);
++
++	return result;
++}
++
++static int dwav_usb_mt_reset_resume(struct usb_interface *intf)
++{
++	struct dwav_usb_mt *dwav_usb_mt = usb_get_intfdata(intf);
++	struct input_dev *input = dwav_usb_mt->input;
++	int err = 0;
++
++	/* restart IO if needed */
++	mutex_lock(&input->mutex);
++	if (input->users)
++		err = usb_submit_urb(dwav_usb_mt->irq, GFP_NOIO);
++	mutex_unlock(&input->mutex);
++
++	return err;
++}
++
++static void dwav_usb_mt_free_buffers(struct usb_device *udev,
++				  struct dwav_usb_mt *dwav_usb_mt)
++{
++	usb_free_coherent(udev, dwav_usb_mt->data_size,
++			dwav_usb_mt->data, dwav_usb_mt->data_dma);
++}
++
++static struct usb_endpoint_descriptor *dwav_usb_mt_get_input_endpoint(
++		struct usb_host_interface *interface)
++{
++	int i;
++
++	for (i = 0; i < interface->desc.bNumEndpoints; i++) {
++		if (usb_endpoint_dir_in(&interface->endpoint[i].desc))
++			return &interface->endpoint[i].desc;
++	}
++
++	return NULL;
++}
++
++static int dwav_usb_mt_init(struct dwav_usb_mt *dwav_usb_mt, void *dev)
++{
++	int err;
++	struct input_dev *input_dev = (struct input_dev *)dev;
++
++	input_dev->name = dwav_usb_mt->name;
++	input_dev->phys = dwav_usb_mt->phys;
++
++	input_set_drvdata(input_dev, dwav_usb_mt);
++
++	input_dev->open = dwav_usb_mt_open;
++	input_dev->close = dwav_usb_mt_close;
++
++	input_dev->id.bustype = BUS_USB;
++
++	/* single touch */
++	input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
++	input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
++
++	input_set_abs_params(input_dev, ABS_X, 0,
++			     DEV_INFO[dwav_usb_mt->dev_id].max_x, 0, 0);
++	input_set_abs_params(input_dev, ABS_Y, 0,
++			     DEV_INFO[dwav_usb_mt->dev_id].max_y, 0, 0);
++
++	/* multi touch */
++	input_set_abs_params(input_dev, ABS_MT_POSITION_X, 0,
++			     DEV_INFO[dwav_usb_mt->dev_id].max_x, 0, 0);
++	input_set_abs_params(input_dev, ABS_MT_POSITION_Y, 0,
++			     DEV_INFO[dwav_usb_mt->dev_id].max_y, 0, 0);
++	input_mt_init_slots(input_dev,
++			     DEV_INFO[dwav_usb_mt->dev_id].max_finger, 0);
++
++	err = input_register_device(input_dev);
++	if (err) {
++		pr_err("%s - input_register_device failed, err: %d\n",
++				__func__, err);
++		return  err;
++	}
++
++	dwav_usb_mt->input = input_dev;
++
++	return  0;
++}
++
++static int dwav_usb_mt_probe(struct usb_interface *intf,
++			  const struct usb_device_id *id)
++{
++	struct dwav_usb_mt *dwav_usb_mt = NULL;
++	struct input_dev *input_dev = NULL;
++	struct usb_endpoint_descriptor *endpoint;
++	struct usb_device *udev = interface_to_usbdev(intf);
++
++	int err = 0;
++
++	endpoint = dwav_usb_mt_get_input_endpoint(intf->cur_altsetting);
++	if (!endpoint)
++		return  -ENXIO;
++
++	dwav_usb_mt = kzalloc(sizeof(struct dwav_usb_mt), GFP_KERNEL);
++	if (!dwav_usb_mt)
++		return  -ENOMEM;
++
++	dwav_usb_mt->dev_id = id->driver_info;
++
++	dwav_usb_mt->finger = kzalloc(sizeof(struct finger_t) *
++				      DEV_INFO[dwav_usb_mt->dev_id].max_finger,
++				      GFP_KERNEL);
++
++	if (!dwav_usb_mt->finger)
++		goto err_free_mem;
++
++	input_dev = input_allocate_device();
++	if (!input_dev)
++		goto err_free_mem;
++
++	dwav_usb_mt->data_size = sizeof(struct dwav_raw);
++	dwav_usb_mt->data = usb_alloc_coherent(udev, dwav_usb_mt->data_size,
++			GFP_KERNEL, &dwav_usb_mt->data_dma);
++	if (!dwav_usb_mt->data)
++		goto err_free_mem;
++
++	dwav_usb_mt->irq = usb_alloc_urb(0, GFP_KERNEL);
++	if (!dwav_usb_mt->irq) {
++		dev_dbg(&intf->dev,
++				"%s - usb_alloc_urb failed: usbtouch->irq\n",
++				__func__);
++		goto err_free_buffers;
++	}
++
++	if (usb_endpoint_type(endpoint) == USB_ENDPOINT_XFER_INT)   {
++		usb_fill_int_urb(dwav_usb_mt->irq, udev,
++			usb_rcvintpipe(udev, endpoint->bEndpointAddress),
++			dwav_usb_mt->data, dwav_usb_mt->data_size,
++			dwav_usb_mt_irq, dwav_usb_mt, endpoint->bInterval);
++	} else {
++		usb_fill_bulk_urb(dwav_usb_mt->irq, udev,
++			 usb_rcvbulkpipe(udev, endpoint->bEndpointAddress),
++			 dwav_usb_mt->data, dwav_usb_mt->data_size,
++			 dwav_usb_mt_irq, dwav_usb_mt);
++	}
++
++	dwav_usb_mt->irq->dev = udev;
++	dwav_usb_mt->irq->transfer_dma = dwav_usb_mt->data_dma;
++	dwav_usb_mt->irq->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
++
++	dwav_usb_mt->interface  = intf;
++
++	if (udev->manufacturer)
++		strscpy(dwav_usb_mt->name,
++				udev->manufacturer, sizeof(dwav_usb_mt->name));
++
++	if (udev->product) {
++		if (udev->manufacturer)
++			strlcat(dwav_usb_mt->name,
++					" ", sizeof(dwav_usb_mt->name));
++
++		strlcat(dwav_usb_mt->name,
++				udev->product, sizeof(dwav_usb_mt->name));
++	}
++
++	if (!strlen(dwav_usb_mt->name)) {
++		snprintf(dwav_usb_mt->name, sizeof(dwav_usb_mt->name),
++				"D-WAV Scientific MultiTouch %04x:%04x",
++				le16_to_cpu(udev->descriptor.idVendor),
++				le16_to_cpu(udev->descriptor.idProduct));
++	}
++
++	usb_make_path(udev, dwav_usb_mt->phys, sizeof(dwav_usb_mt->phys));
++	strlcat(dwav_usb_mt->phys, "/input0", sizeof(dwav_usb_mt->phys));
++
++	usb_to_input_id(udev, &input_dev->id);
++
++	input_dev->dev.parent = &intf->dev;
++
++	err = dwav_usb_mt_init(dwav_usb_mt, (void *)input_dev);
++	if (err)
++		goto err_free_urb;
++
++	usb_set_intfdata(intf, dwav_usb_mt);
++
++	dev_info(&intf->dev, "%s\n", DEV_INFO[dwav_usb_mt->dev_id].name);
++
++	return 0;
++
++err_free_urb:
++	usb_free_urb(dwav_usb_mt->irq);
++
++err_free_buffers:
++	dwav_usb_mt_free_buffers(udev, dwav_usb_mt);
++
++err_free_mem:
++	if (input_dev)
++		input_free_device(input_dev);
++	kfree(dwav_usb_mt);
++
++	return err;
++}
++
++static void dwav_usb_mt_disconnect(struct usb_interface *intf)
++{
++	struct dwav_usb_mt *dwav_usb_mt = usb_get_intfdata(intf);
++
++	if (!dwav_usb_mt)
++		return;
++
++	dev_dbg(&intf->dev,
++			"%s - dwav_usb_mt is initialized, cleaning up\n",
++			__func__);
++
++	usb_set_intfdata(intf, NULL);
++
++	/* this will stop IO via close */
++	input_unregister_device(dwav_usb_mt->input);
++
++	usb_free_urb(dwav_usb_mt->irq);
++
++	dwav_usb_mt_free_buffers(interface_to_usbdev(intf), dwav_usb_mt);
++
++	kfree(dwav_usb_mt);
++}
++
++MODULE_DEVICE_TABLE(usb, dwav_usb_mt_devices);
++
++static struct usb_driver dwav_usb_mt_driver = {
++	.name = "dwav_usb_mt",
++	.probe = dwav_usb_mt_probe,
++	.disconnect = dwav_usb_mt_disconnect,
++	.suspend = dwav_usb_mt_suspend,
++	.resume = dwav_usb_mt_resume,
++	.reset_resume = dwav_usb_mt_reset_resume,
++	.id_table = dwav_usb_mt_devices,
++	.supports_autosuspend = 1,
++};
++
++module_usb_driver(dwav_usb_mt_driver);
++
++MODULE_AUTHOR("Hardkernel Co.,Ltd");
++MODULE_DESCRIPTION("D-WAV USB(HID) MultiTouch Driver");
++MODULE_LICENSE("GPL");
++
++MODULE_ALIAS("dwav_usb_mt");
+\ No newline at end of file
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-media-cec-silence-CEC-timeout-message-HACK.patch b/patch/kernel/archive/meson64-6.10/general-media-cec-silence-CEC-timeout-message-HACK.patch
new file mode 100644
index 000000000000..4905e2e4fcb2
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-media-cec-silence-CEC-timeout-message-HACK.patch
@@ -0,0 +1,40 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Tue, 7 Jan 2020 07:12:47 +0000
+Subject: HACK: media: cec: silence CEC timeout message
+
+If testing with an AVR that does not pass-through CEC state the system
+log fills with timeout messages. Silence this to stop the log rotation
+and ensure other issues are visible.
+
+[   42.718009] cec-meson_ao_cec: message ff 84 50 00 01 timed out
+[   45.021994] cec-meson_ao_cec: message ff 87 00 15 82 timed out
+[   47.325965] cec-meson_ao_cec: message 10 timed out
+[   49.630023] cec-meson_ao_cec: message 10 timed out
+[   51.933960] cec-meson_ao_cec: message 10 timed out
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+---
+ drivers/media/cec/core/cec-adap.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/cec/core/cec-adap.c
++++ b/drivers/media/cec/core/cec-adap.c
+@@ -510,9 +510,9 @@ int cec_thread_func(void *_adap)
+ 			 * default).
+ 			 */
+ 			if (adap->transmitting) {
+-				pr_warn("cec-%s: message %*ph timed out\n", adap->name,
+-					adap->transmitting->msg.len,
+-					adap->transmitting->msg.msg);
++				//pr_warn("cec-%s: message %*ph timed out\n", adap->name,
++				//	adap->transmitting->msg.len,
++				//	adap->transmitting->msg.msg);
+ 				/* Just give up on this. */
+ 				cec_data_cancel(adap->transmitting,
+ 						CEC_TX_STATUS_TIMEOUT, 0);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-memory-marked-nomap.patch b/patch/kernel/archive/meson64-6.10/general-memory-marked-nomap.patch
new file mode 100644
index 000000000000..dc7329403333
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-memory-marked-nomap.patch
@@ -0,0 +1,38 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Agner <stefan@agner.ch>
+Date: Wed, 15 Sep 2021 05:00:45 +0000
+Subject: HACK: of: partial revert of fdt.c changes
+
+This resolves reports similar to the below which are present in dmesg
+since Linux 5.10; which are also causing crashes in some distros:
+
+[    0.000000] OF: fdt: Reserved memory: failed to reserve memory for node 'secmon@5000000': base 0x0000000005000000, size 3 MiB
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+---
+ drivers/of/of_reserved_mem.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c
+index 111111111111..222222222222 100644
+--- a/drivers/of/of_reserved_mem.c
++++ b/drivers/of/of_reserved_mem.c
+@@ -82,15 +82,6 @@ static int __init early_init_dt_reserve_memory(phys_addr_t base,
+ 					       phys_addr_t size, bool nomap)
+ {
+ 	if (nomap) {
+-		/*
+-		 * If the memory is already reserved (by another region), we
+-		 * should not allow it to be marked nomap, but don't worry
+-		 * if the region isn't memory as it won't be mapped.
+-		 */
+-		if (memblock_overlaps_region(&memblock.memory, base, size) &&
+-		    memblock_is_region_reserved(base, size))
+-			return -EBUSY;
+-
+ 		return memblock_mark_nomap(base, size);
+ 	}
+ 	return memblock_reserve(base, size);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-meson-aiu-Fix-HDMI-codec-control-selection.patch b/patch/kernel/archive/meson64-6.10/general-meson-aiu-Fix-HDMI-codec-control-selection.patch
new file mode 100644
index 000000000000..70d874407f2f
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-meson-aiu-Fix-HDMI-codec-control-selection.patch
@@ -0,0 +1,232 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 3 Oct 2021 05:35:48 +0000
+Subject: ASoC: meson: aiu: Fix HDMI codec control selection
+
+The HDMI controllers on Amlogic Meson SoCs which use the AIU
+audio-controller have two different audio format inputs:
+- I2S which is also the only configuration supported on GXBB, GXL and
+  GXM SoCs since there's no SPDIF support in the DesignWare HDMI
+  controller driver (at the time of writing this)
+- SPDIF can be used optionally, including pass-through formats
+
+Switching between these requires us to set different registers:
+AIU_HDMI_CLK_DATA_CTRL[1:0] "HDMI_DATA_CLK_SEL":
+- 0x0 disables the HDMI output clock
+- 0x1 selects the PCM clock
+- 0x2 selects the AIU clock
+- 0x3 is reserved
+
+AIU_HDMI_CLK_DATA_CTRL[5:4] "HDMI_DATA_SEL":
+- 0x0 outputs constant zero, disables HDMI data
+- 0x1 selects PCM data
+- 0x2 selects AIU I2S data
+- 0x3 is reserved
+
+AIU_CLK_CTRL_MORE[6] "HDMITX_SEL_AOCLKX2":
+- 0x0 selects cts_i958 as AIU clk to hdmi_tx_audio_master_clk
+- 0x1 selects cts_aoclkx2_int as AIU clk to hdmi_tx_audio_master_clk
+
+The Meson8/8b/8m2 vendor driver uses the following settings:
+SPDIF output to the HDMI controller:
+- 0x2 (AIU clock) in AIU_HDMI_CLK_DATA_CTRL[1:0]
+- 0x0 (no HDMI data) in AIU_HDMI_CLK_DATA_CTRL[5:4]
+- 0x0 (using cts_i958 as AIU clk) in AIU_CLK_CTRL_MORE[6]
+I2S output to the HDMI controller:
+- 0x2 (AIU clock) in AIU_HDMI_CLK_DATA_CTRL[1:0]
+- 0x2 (I2S data) in AIU_HDMI_CLK_DATA_CTRL[5:4]
+- 0x0 (using cts_aoclkx2_int as AIU clk) in AIU_CLK_CTRL_MORE[6]
+
+The GXBB/GXL/GXM vendor driver uses the following settings:
+SPDIF output to the HDMI controller:
+- not setting AIU_HDMI_CLK_DATA_CTRL at all
+- 0x0 (using cts_i958 as AIU clk) in AIU_CLK_CTRL_MORE[6]
+I2S output to the HDMI controller:
+- 0x2 (AIU clock) in AIU_HDMI_CLK_DATA_CTRL[1:0]
+- 0x2 (I2S data) in AIU_HDMI_CLK_DATA_CTRL[5:4]
+- 0x0 (using cts_aoclkx2_int as AIU clk) in AIU_CLK_CTRL_MORE[6]
+
+Set the three registers at the same time following what the vendor
+driver does on Meson8/8b/8m2 SoCs. This makes the SPDIF output to the
+HDMI controller work. The entries and order of the entries in the enum
+is not changed on purpose to not break old configurations.
+
+Fixes: b82b734c0e9a7 ("ASoC: meson: aiu: add hdmi codec control support")
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ sound/soc/meson/aiu-codec-ctrl.c  | 108 +++++++---
+ sound/soc/meson/aiu-encoder-i2s.c |   6 -
+ 2 files changed, 80 insertions(+), 34 deletions(-)
+
+diff --git a/sound/soc/meson/aiu-codec-ctrl.c b/sound/soc/meson/aiu-codec-ctrl.c
+index 111111111111..222222222222 100644
+--- a/sound/soc/meson/aiu-codec-ctrl.c
++++ b/sound/soc/meson/aiu-codec-ctrl.c
+@@ -12,14 +12,60 @@
+ #include "aiu.h"
+ #include "meson-codec-glue.h"
+ 
+-#define CTRL_CLK_SEL		GENMASK(1, 0)
+-#define CTRL_DATA_SEL_SHIFT	4
+-#define CTRL_DATA_SEL		(0x3 << CTRL_DATA_SEL_SHIFT)
+-
+-static const char * const aiu_codec_ctrl_mux_texts[] = {
+-	"DISABLED", "PCM", "I2S",
++#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL			GENMASK(1, 0)
++#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_DISABLE		0x0
++#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_PCM		0x1
++#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_AIU		0x2
++#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL			GENMASK(5, 4)
++#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_OUTPUT_ZERO	0x0
++#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_PCM_DATA	0x1
++#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_I2S_DATA	0x2
++
++#define AIU_CLK_CTRL_MORE_AMCLK				BIT(6)
++
++#define AIU_HDMI_CTRL_MUX_DISABLED			0
++#define AIU_HDMI_CTRL_MUX_PCM				1
++#define AIU_HDMI_CTRL_MUX_I2S				2
++
++static const char * const aiu_codec_hdmi_ctrl_mux_texts[] = {
++	[AIU_HDMI_CTRL_MUX_DISABLED] =  "DISABLED",
++	[AIU_HDMI_CTRL_MUX_PCM] = "PCM",
++	[AIU_HDMI_CTRL_MUX_I2S] = "I2S",
+ };
+ 
++static int aiu_codec_ctrl_mux_get_enum(struct snd_kcontrol *kcontrol,
++				       struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *component =
++		snd_soc_dapm_kcontrol_component(kcontrol);
++	unsigned int ctrl, more, mux = AIU_HDMI_CTRL_MUX_DISABLED;
++
++	ctrl = snd_soc_component_read(component, AIU_HDMI_CLK_DATA_CTRL);
++	if (FIELD_GET(AIU_HDMI_CLK_DATA_CTRL_CLK_SEL, ctrl) !=
++	    AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_AIU) {
++		goto out;
++	}
++
++	more = snd_soc_component_read(component, AIU_CLK_CTRL_MORE);
++	if (FIELD_GET(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL, ctrl) ==
++	    AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_I2S_DATA &&
++	    !!(more & AIU_CLK_CTRL_MORE_AMCLK)) {
++		mux = AIU_HDMI_CTRL_MUX_I2S;
++		goto out;
++	}
++
++	if (FIELD_GET(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL, ctrl) ==
++	    AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_OUTPUT_ZERO &&
++	    !(more & AIU_CLK_CTRL_MORE_AMCLK)) {
++		mux = AIU_HDMI_CTRL_MUX_PCM;
++		goto out;
++	}
++
++out:
++	ucontrol->value.enumerated.item[0] = mux;
++	return 0;
++}
++
+ static int aiu_codec_ctrl_mux_put_enum(struct snd_kcontrol *kcontrol,
+ 				       struct snd_ctl_elem_value *ucontrol)
+ {
+@@ -28,45 +74,51 @@ static int aiu_codec_ctrl_mux_put_enum(struct snd_kcontrol *kcontrol,
+ 	struct snd_soc_dapm_context *dapm =
+ 		snd_soc_dapm_kcontrol_dapm(kcontrol);
+ 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+-	unsigned int mux, changed;
++	unsigned int mux, ctrl, more;
+ 
+ 	mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
+-	changed = snd_soc_component_test_bits(component, e->reg,
+-					      CTRL_DATA_SEL,
+-					      FIELD_PREP(CTRL_DATA_SEL, mux));
+ 
+-	if (!changed)
+-		return 0;
++	if (mux == AIU_HDMI_CTRL_MUX_I2S) {
++		ctrl = FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL,
++				  AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_I2S_DATA);
++		more = AIU_CLK_CTRL_MORE_AMCLK;
++	} else {
++		ctrl = FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL,
++				  AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_OUTPUT_ZERO);
++		more = 0;
++	}
++
++	if (mux == AIU_HDMI_CTRL_MUX_DISABLED) {
++		ctrl |= FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_CLK_SEL,
++				   AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_DISABLE);
++	} else {
++		ctrl |= FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_CLK_SEL,
++				   AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_AIU);
++	}
+ 
+ 	/* Force disconnect of the mux while updating */
+ 	snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
+ 
+-	/* Reset the source first */
+-	snd_soc_component_update_bits(component, e->reg,
+-				      CTRL_CLK_SEL |
+-				      CTRL_DATA_SEL,
+-				      FIELD_PREP(CTRL_CLK_SEL, 0) |
+-				      FIELD_PREP(CTRL_DATA_SEL, 0));
++	snd_soc_component_update_bits(component, AIU_HDMI_CLK_DATA_CTRL,
++				      AIU_HDMI_CLK_DATA_CTRL_CLK_SEL |
++				      AIU_HDMI_CLK_DATA_CTRL_DATA_SEL,
++				      ctrl);
+ 
+-	/* Set the appropriate source */
+-	snd_soc_component_update_bits(component, e->reg,
+-				      CTRL_CLK_SEL |
+-				      CTRL_DATA_SEL,
+-				      FIELD_PREP(CTRL_CLK_SEL, mux) |
+-				      FIELD_PREP(CTRL_DATA_SEL, mux));
++	snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
++				      AIU_CLK_CTRL_MORE_AMCLK,
++				      more);
+ 
+ 	snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
+ 
+ 	return 1;
+ }
+ 
+-static SOC_ENUM_SINGLE_DECL(aiu_hdmi_ctrl_mux_enum, AIU_HDMI_CLK_DATA_CTRL,
+-			    CTRL_DATA_SEL_SHIFT,
+-			    aiu_codec_ctrl_mux_texts);
++static SOC_ENUM_SINGLE_VIRT_DECL(aiu_hdmi_ctrl_mux_enum,
++				 aiu_codec_hdmi_ctrl_mux_texts);
+ 
+ static const struct snd_kcontrol_new aiu_hdmi_ctrl_mux =
+ 	SOC_DAPM_ENUM_EXT("HDMI Source", aiu_hdmi_ctrl_mux_enum,
+-			  snd_soc_dapm_get_enum_double,
++			  aiu_codec_ctrl_mux_get_enum,
+ 			  aiu_codec_ctrl_mux_put_enum);
+ 
+ static const struct snd_soc_dapm_widget aiu_hdmi_ctrl_widgets[] = {
+diff --git a/sound/soc/meson/aiu-encoder-i2s.c b/sound/soc/meson/aiu-encoder-i2s.c
+index 111111111111..222222222222 100644
+--- a/sound/soc/meson/aiu-encoder-i2s.c
++++ b/sound/soc/meson/aiu-encoder-i2s.c
+@@ -23,7 +23,6 @@
+ #define AIU_CLK_CTRL_AOCLK_INVERT	BIT(6)
+ #define AIU_CLK_CTRL_LRCLK_INVERT	BIT(7)
+ #define AIU_CLK_CTRL_LRCLK_SKEW		GENMASK(9, 8)
+-#define AIU_CLK_CTRL_MORE_HDMI_AMCLK	BIT(6)
+ #define AIU_CLK_CTRL_MORE_I2S_DIV	GENMASK(5, 0)
+ #define AIU_CODEC_DAC_LRCLK_CTRL_DIV	GENMASK(11, 0)
+ 
+@@ -176,11 +175,6 @@ static int aiu_encoder_i2s_set_clocks(struct snd_soc_component *component,
+ 	if (ret)
+ 		return ret;
+ 
+-	/* Make sure amclk is used for HDMI i2s as well */
+-	snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
+-				      AIU_CLK_CTRL_MORE_HDMI_AMCLK,
+-				      AIU_CLK_CTRL_MORE_HDMI_AMCLK);
+-
+ 	return 0;
+ }
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-meson-mmc-1-arm64-amlogic-mmc-meson-gx-Add-core-tx-rx-eMMC-SD-SD.patch b/patch/kernel/archive/meson64-6.10/general-meson-mmc-1-arm64-amlogic-mmc-meson-gx-Add-core-tx-rx-eMMC-SD-SD.patch
new file mode 100644
index 000000000000..a0894a748f14
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-meson-mmc-1-arm64-amlogic-mmc-meson-gx-Add-core-tx-rx-eMMC-SD-SD.patch
@@ -0,0 +1,108 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Vyacheslav Bocharov <adeep@lexina.in>
+Date: Mon, 7 Nov 2022 14:19:08 +0100
+Subject: arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase
+ clock settings from devicetree data
+
+The mmc driver has the same phase values for all meson platforms. However,
+some platforms (and even some boards) require different values. This patch
+transfers the values from the set in the code to the variables in the
+device-tree file.
+
+Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
+---
+ drivers/mmc/host/meson-gx-mmc.c        | 19 +++--
+ include/dt-bindings/mmc/meson-gx-mmc.h | 35 ++++++++++
+ 2 files changed, 48 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
+index 111111111111..222222222222 100644
+--- a/drivers/mmc/host/meson-gx-mmc.c
++++ b/drivers/mmc/host/meson-gx-mmc.c
+@@ -27,6 +27,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/bitfield.h>
+ #include <linux/pinctrl/consumer.h>
++#include <dt-bindings/mmc/meson-gx-mmc.h>
+ 
+ #define DRIVER_NAME "meson-gx-mmc"
+ 
+@@ -36,8 +37,6 @@
+ #define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
+ #define   CLK_TX_PHASE_MASK GENMASK(11, 10)
+ #define   CLK_RX_PHASE_MASK GENMASK(13, 12)
+-#define   CLK_PHASE_0 0
+-#define   CLK_PHASE_180 2
+ #define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+ #define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+ #define   CLK_V2_ALWAYS_ON BIT(24)
+@@ -426,13 +425,21 @@ static int meson_mmc_clk_init(struct meson_host *host)
+ 	const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
+ 	const char *clk_parent[1];
+ 	u32 clk_reg;
+-
++	u32 phase[3]; // <core_phase, tx_phase, rx_phase>
++
++	if (!(host->dev && host->dev->of_node) || (device_property_read_u32_array(host->dev,
++	    "amlogic,mmc-phase", phase, 3) < 0)) {
++		dev_dbg(host->dev, "get amlogic,mmc-phase failed, use default phase settings\n");
++		phase[0] = CLK_PHASE_180;
++		phase[1] = CLK_PHASE_0;
++		phase[2] = CLK_PHASE_0;
++	}
+ 	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
+ 	clk_reg = CLK_ALWAYS_ON(host);
+ 	clk_reg |= CLK_DIV_MASK;
+-	clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
+-	clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
+-	clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
++	clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, phase[0]);
++	clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, phase[1]);
++	clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, phase[2]);
+ 	if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
+ 		clk_reg |= CLK_IRQ_SDIO_SLEEP(host);
+ 	writel(clk_reg, host->regs + SD_EMMC_CLOCK);
+diff --git a/include/dt-bindings/mmc/meson-gx-mmc.h b/include/dt-bindings/mmc/meson-gx-mmc.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/include/dt-bindings/mmc/meson-gx-mmc.h
+@@ -0,0 +1,35 @@
++/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
++/*
++ * Copyright (c) 2022 Vyacheslav Bocharov
++ * Author: Vyacheslav Bocharov <adeep@lexina.in>
++ */
++
++#ifndef _DT_BINDINGS_MESON_GX_MMC_H
++#define _DT_BINDINGS_MESON_GX_MMC_H
++
++/*
++ * Cfg_rx_phase: RX clock phase
++ * bits: 9:8 R/W
++ * default: 0
++ * Recommended value: 0
++ *
++ * Cfg_tx_phase: TX clock phase
++ * bits: 9:8 R/W
++ * default: 0
++ * Recommended value: 2
++ *
++ * Cfg_co_phase: Core clock phase
++ * bits: 9:8 R/W
++ * default: 0
++ * Recommended value: 2
++ *
++ * values: 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
++ */
++
++#define   CLK_PHASE_0 0
++#define   CLK_PHASE_90 1
++#define   CLK_PHASE_180 2
++#define   CLK_PHASE_270 3
++
++
++#endif
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-meson-mmc-2-arm64-amlogic-dts-meson-update-meson-axg-device-tree.patch b/patch/kernel/archive/meson64-6.10/general-meson-mmc-2-arm64-amlogic-dts-meson-update-meson-axg-device-tree.patch
new file mode 100644
index 000000000000..da5343474d41
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-meson-mmc-2-arm64-amlogic-dts-meson-update-meson-axg-device-tree.patch
@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Vyacheslav Bocharov <adeep@lexina.in>
+Date: Mon, 7 Nov 2022 16:19:08 +0300
+Subject: arm64: amlogic: dts: meson: update meson-axg device-tree for new
+ core, tx, rx phase clock settings.
+
+Use phase 270 for core MMC clock on axg meson boards.
+
+Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
+---
+ arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+@@ -13,6 +13,7 @@
+ #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
+ #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
+ #include <dt-bindings/power/meson-axg-power.h>
++#include <dt-bindings/mmc/meson-gx-mmc.h>
+ 
+ / {
+ 	compatible = "amlogic,meson-axg";
+@@ -1922,6 +1923,7 @@ sd_emmc_b: mmc@5000 {
+ 					<&clkc CLKID_SD_EMMC_B_CLK0>,
+ 					<&clkc CLKID_FCLK_DIV2>;
+ 				clock-names = "core", "clkin0", "clkin1";
++				amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
+ 				resets = <&reset RESET_SD_EMMC_B>;
+ 			};
+ 
+@@ -1935,6 +1937,7 @@ sd_emmc_c: mmc@7000 {
+ 					<&clkc CLKID_FCLK_DIV2>;
+ 				clock-names = "core", "clkin0", "clkin1";
+ 				resets = <&reset RESET_SD_EMMC_C>;
++				amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
+ 			};
+ 
+ 			nfc: nand-controller@7800 {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-meson-mmc-3-arm64-dts-docs-Update-mmc-meson-gx-documentation-for.patch b/patch/kernel/archive/meson64-6.10/general-meson-mmc-3-arm64-dts-docs-Update-mmc-meson-gx-documentation-for.patch
new file mode 100644
index 000000000000..3eb3b8314d0b
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-meson-mmc-3-arm64-dts-docs-Update-mmc-meson-gx-documentation-for.patch
@@ -0,0 +1,51 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Vyacheslav Bocharov <adeep@lexina.in>
+Date: Thu, 10 Nov 2022 14:52:47 +0300
+Subject: arm64: dts: docs: Update mmc meson-gx documentation for new config
+ option amlogic,mmc-phase
+
+- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx
+clock with values:
+	0: CLK_PHASE_0 - 0 phase
+	1: CLK_PHASE_90 - 90 phase
+	2: CLK_PHASE_180 - 180 phase
+	3: CLK_PHASE_270 - 270 phase
+By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
+
+Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
+- rpardini: in 6.4, Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt is gone
+  and now replaced by Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
+---
+ Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml | 11 ++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
++++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
+@@ -51,6 +51,16 @@ properties:
+       set when controller's internal DMA engine cannot access the DRAM memory,
+       like on the G12A dedicated SDIO controller.
+ 
++  amlogic,mmc-phases:
++    type: integer
++    description: |
++      3-element array of clock phases for core, tx, rx clock with values:
++      0: CLK_PHASE_0 - 0 phase
++      1: CLK_PHASE_90 - 90 phase
++      2: CLK_PHASE_180 - 180 phase
++      3: CLK_PHASE_270 - 270 phase
++      By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
++
+ required:
+   - compatible
+   - reg
+@@ -73,4 +83,5 @@ examples:
+         clock-names = "core", "clkin0", "clkin1";
+         pinctrl-0 = <&emm_pins>;
+         resets = <&reset_mmc>;
++        amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>;
+     };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-meson-vdec-add-HEVC-decode-codec.patch b/patch/kernel/archive/meson64-6.10/general-meson-vdec-add-HEVC-decode-codec.patch
new file mode 100644
index 000000000000..44e1694e0236
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-meson-vdec-add-HEVC-decode-codec.patch
@@ -0,0 +1,1608 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: benjamin545 <benjamin545@gmail.com>
+Date: Thu, 15 Jul 2021 17:08:42 -0400
+Subject: WIP: drivers: meson: vdec: add HEVC decode codec
+
+Unknown patch. From LibreELEC?
+---
+ drivers/staging/media/meson/vdec/Makefile        |    2 +-
+ drivers/staging/media/meson/vdec/codec_hevc.c    | 1440 ++++++++++
+ drivers/staging/media/meson/vdec/codec_hevc.h    |   13 +
+ drivers/staging/media/meson/vdec/esparser.c      |    2 +-
+ drivers/staging/media/meson/vdec/hevc_regs.h     |    1 +
+ drivers/staging/media/meson/vdec/vdec_platform.c |   49 +
+ 6 files changed, 1505 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/staging/media/meson/vdec/Makefile b/drivers/staging/media/meson/vdec/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/Makefile
++++ b/drivers/staging/media/meson/vdec/Makefile
+@@ -3,6 +3,6 @@
+ 
+ meson-vdec-objs = esparser.o vdec.o vdec_helpers.o vdec_platform.o
+ meson-vdec-objs += vdec_1.o vdec_hevc.o
+-meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_hevc_common.o codec_vp9.o
++meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_hevc_common.o codec_vp9.o codec_hevc.o
+ 
+ obj-$(CONFIG_VIDEO_MESON_VDEC) += meson-vdec.o
+diff --git a/drivers/staging/media/meson/vdec/codec_hevc.c b/drivers/staging/media/meson/vdec/codec_hevc.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/staging/media/meson/vdec/codec_hevc.c
+@@ -0,0 +1,1440 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (C) 2018 Maxime Jourdan <mjourdan@baylibre.com>
++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
++ */
++
++#include <media/v4l2-mem2mem.h>
++#include <media/videobuf2-dma-contig.h>
++
++#include "codec_hevc.h"
++#include "dos_regs.h"
++#include "hevc_regs.h"
++#include "vdec_helpers.h"
++#include "codec_hevc_common.h"
++
++/* HEVC reg mapping */
++#define HEVC_DEC_STATUS_REG	HEVC_ASSIST_SCRATCH_0
++	#define HEVC_ACTION_DONE	0xff
++#define HEVC_RPM_BUFFER		HEVC_ASSIST_SCRATCH_1
++#define HEVC_SHORT_TERM_RPS	HEVC_ASSIST_SCRATCH_2
++#define HEVC_VPS_BUFFER		HEVC_ASSIST_SCRATCH_3
++#define HEVC_SPS_BUFFER		HEVC_ASSIST_SCRATCH_4
++#define HEVC_PPS_BUFFER		HEVC_ASSIST_SCRATCH_5
++#define HEVC_SAO_UP		HEVC_ASSIST_SCRATCH_6
++#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
++#define H265_MMU_MAP_BUFFER	HEVC_ASSIST_SCRATCH_7
++#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
++#define HEVC_sao_mem_unit	HEVC_ASSIST_SCRATCH_9
++#define HEVC_SAO_ABV		HEVC_ASSIST_SCRATCH_A
++#define HEVC_sao_vb_size	HEVC_ASSIST_SCRATCH_B
++#define HEVC_SAO_VB		HEVC_ASSIST_SCRATCH_C
++#define HEVC_SCALELUT		HEVC_ASSIST_SCRATCH_D
++#define HEVC_WAIT_FLAG		HEVC_ASSIST_SCRATCH_E
++#define RPM_CMD_REG		HEVC_ASSIST_SCRATCH_F
++#define LMEM_DUMP_ADR		HEVC_ASSIST_SCRATCH_F
++#define DEBUG_REG1		HEVC_ASSIST_SCRATCH_G
++#define HEVC_DECODE_MODE2	HEVC_ASSIST_SCRATCH_H
++#define NAL_SEARCH_CTL		HEVC_ASSIST_SCRATCH_I
++#define HEVC_DECODE_MODE	HEVC_ASSIST_SCRATCH_J
++	#define DECODE_MODE_SINGLE 0
++#define DECODE_STOP_POS		HEVC_ASSIST_SCRATCH_K
++#define HEVC_AUX_ADR		HEVC_ASSIST_SCRATCH_L
++#define HEVC_AUX_DATA_SIZE	HEVC_ASSIST_SCRATCH_M
++#define HEVC_DECODE_SIZE	HEVC_ASSIST_SCRATCH_N
++
++#define AMRISC_MAIN_REQ		 0x04
++
++/* HEVC Constants */
++#define MAX_REF_PIC_NUM		24
++#define MAX_REF_ACTIVE		16
++#define MAX_TILE_COL_NUM	10
++#define MAX_TILE_ROW_NUM	20
++#define MAX_SLICE_NUM		800
++#define INVALID_POC		0x80000000
++
++/* HEVC Workspace layout */
++#define MPRED_MV_BUF_SIZE 0x120000
++
++#define IPP_SIZE	0x4000
++#define SAO_ABV_SIZE	0x30000
++#define SAO_VB_SIZE	0x30000
++#define SH_TM_RPS_SIZE	0x800
++#define VPS_SIZE	0x800
++#define SPS_SIZE	0x800
++#define PPS_SIZE	0x2000
++#define SAO_UP_SIZE	0x2800
++#define SWAP_BUF_SIZE	0x800
++#define SWAP_BUF2_SIZE	0x800
++#define SCALELUT_SIZE	0x8000
++#define DBLK_PARA_SIZE	0x20000
++#define DBLK_DATA_SIZE	0x80000
++#define DBLK_DATA2_SIZE	0x80000
++#define MMU_VBH_SIZE	0x5000
++#define MPRED_ABV_SIZE	0x8000
++#define MPRED_MV_SIZE	(MPRED_MV_BUF_SIZE * MAX_REF_PIC_NUM)
++#define RPM_BUF_SIZE	0x100
++#define LMEM_SIZE	0xA00
++
++#define IPP_OFFSET       0x00
++#define SAO_ABV_OFFSET   (IPP_OFFSET + IPP_SIZE)
++#define SAO_VB_OFFSET    (SAO_ABV_OFFSET + SAO_ABV_SIZE)
++#define SH_TM_RPS_OFFSET (SAO_VB_OFFSET + SAO_VB_SIZE)
++#define VPS_OFFSET       (SH_TM_RPS_OFFSET + SH_TM_RPS_SIZE)
++#define SPS_OFFSET       (VPS_OFFSET + VPS_SIZE)
++#define PPS_OFFSET       (SPS_OFFSET + SPS_SIZE)
++#define SAO_UP_OFFSET    (PPS_OFFSET + PPS_SIZE)
++#define SWAP_BUF_OFFSET  (SAO_UP_OFFSET + SAO_UP_SIZE)
++#define SWAP_BUF2_OFFSET (SWAP_BUF_OFFSET + SWAP_BUF_SIZE)
++#define SCALELUT_OFFSET  (SWAP_BUF2_OFFSET + SWAP_BUF2_SIZE)
++#define DBLK_PARA_OFFSET (SCALELUT_OFFSET + SCALELUT_SIZE)
++#define DBLK_DATA_OFFSET (DBLK_PARA_OFFSET + DBLK_PARA_SIZE)
++#define DBLK_DATA2_OFFSET (DBLK_DATA_OFFSET + DBLK_DATA_SIZE)
++#define MMU_VBH_OFFSET   (DBLK_DATA2_OFFSET + DBLK_DATA2_SIZE)
++#define MPRED_ABV_OFFSET (MMU_VBH_OFFSET + MMU_VBH_SIZE)
++#define MPRED_MV_OFFSET  (MPRED_ABV_OFFSET + MPRED_ABV_SIZE)
++#define RPM_OFFSET       (MPRED_MV_OFFSET + MPRED_MV_SIZE)
++#define LMEM_OFFSET      (RPM_OFFSET + RPM_BUF_SIZE)
++
++/* ISR decode status */
++#define HEVC_DEC_IDLE                        0x0
++#define HEVC_NAL_UNIT_VPS                    0x1
++#define HEVC_NAL_UNIT_SPS                    0x2
++#define HEVC_NAL_UNIT_PPS                    0x3
++#define HEVC_NAL_UNIT_CODED_SLICE_SEGMENT    0x4
++#define HEVC_CODED_SLICE_SEGMENT_DAT         0x5
++#define HEVC_SLICE_DECODING                  0x6
++#define HEVC_NAL_UNIT_SEI                    0x7
++#define HEVC_SLICE_SEGMENT_DONE              0x8
++#define HEVC_NAL_SEARCH_DONE                 0x9
++#define HEVC_DECPIC_DATA_DONE                0xa
++#define HEVC_DECPIC_DATA_ERROR               0xb
++#define HEVC_SEI_DAT                         0xc
++#define HEVC_SEI_DAT_DONE                    0xd
++
++/* RPM misc_flag0 */
++#define PCM_LOOP_FILTER_DISABLED_FLAG_BIT		0
++#define PCM_ENABLE_FLAG_BIT				1
++#define LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT	2
++#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT	3
++#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT	4
++#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT		5
++#define DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT		6
++#define SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT	7
++#define SLICE_SAO_LUMA_FLAG_BIT				8
++#define SLICE_SAO_CHROMA_FLAG_BIT			9
++#define SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 10
++
++/* Constants for HEVC_MPRED_CTRL1 */
++#define AMVP_MAX_NUM_CANDS_MEM	3
++#define AMVP_MAX_NUM_CANDS	2
++#define NUM_CHROMA_MODE		5
++#define DM_CHROMA_IDX		36
++
++/* Buffer sizes */
++#define SIZE_WORKSPACE ALIGN(LMEM_OFFSET + LMEM_SIZE, 64 * SZ_1K)
++#define SIZE_AUX (SZ_1K * 16)
++#define SIZE_FRAME_MMU (0x1200 * 4)
++#define RPM_SIZE 0x80
++#define RPS_USED_BIT 14
++
++/* Data received from the HW in this form, do not rearrange */
++union rpm_param {
++	struct {
++		u16 data[RPM_SIZE];
++	} l;
++	struct {
++		u16 CUR_RPS[MAX_REF_ACTIVE];
++		u16 num_ref_idx_l0_active;
++		u16 num_ref_idx_l1_active;
++		u16 slice_type;
++		u16 slice_temporal_mvp_enable_flag;
++		u16 dependent_slice_segment_flag;
++		u16 slice_segment_address;
++		u16 num_title_rows_minus1;
++		u16 pic_width_in_luma_samples;
++		u16 pic_height_in_luma_samples;
++		u16 log2_min_coding_block_size_minus3;
++		u16 log2_diff_max_min_coding_block_size;
++		u16 log2_max_pic_order_cnt_lsb_minus4;
++		u16 POClsb;
++		u16 collocated_from_l0_flag;
++		u16 collocated_ref_idx;
++		u16 log2_parallel_merge_level;
++		u16 five_minus_max_num_merge_cand;
++		u16 sps_num_reorder_pics_0;
++		u16 modification_flag;
++		u16 tiles_flags;
++		u16 num_tile_columns_minus1;
++		u16 num_tile_rows_minus1;
++		u16 tile_width[8];
++		u16 tile_height[8];
++		u16 misc_flag0;
++		u16 pps_beta_offset_div2;
++		u16 pps_tc_offset_div2;
++		u16 slice_beta_offset_div2;
++		u16 slice_tc_offset_div2;
++		u16 pps_cb_qp_offset;
++		u16 pps_cr_qp_offset;
++		u16 first_slice_segment_in_pic_flag;
++		u16 m_temporalId;
++		u16 m_nalUnitType;
++		u16 vui_num_units_in_tick_hi;
++		u16 vui_num_units_in_tick_lo;
++		u16 vui_time_scale_hi;
++		u16 vui_time_scale_lo;
++		u16 bit_depth;
++		u16 profile_etc;
++		u16 sei_frame_field_info;
++		u16 video_signal_type;
++		u16 modification_list[0x20];
++		u16 conformance_window_flag;
++		u16 conf_win_left_offset;
++		u16 conf_win_right_offset;
++		u16 conf_win_top_offset;
++		u16 conf_win_bottom_offset;
++		u16 chroma_format_idc;
++		u16 color_description;
++		u16 aspect_ratio_idc;
++		u16 sar_width;
++		u16 sar_height;
++	} p;
++};
++
++enum nal_unit_type {
++	NAL_UNIT_CODED_SLICE_BLA	= 16,
++	NAL_UNIT_CODED_SLICE_BLANT	= 17,
++	NAL_UNIT_CODED_SLICE_BLA_N_LP	= 18,
++	NAL_UNIT_CODED_SLICE_IDR	= 19,
++	NAL_UNIT_CODED_SLICE_IDR_N_LP	= 20,
++};
++
++enum slice_type {
++	B_SLICE = 0,
++	P_SLICE = 1,
++	I_SLICE = 2,
++};
++
++/* A frame being decoded */
++struct hevc_frame {
++	struct list_head list;
++	struct vb2_v4l2_buffer *vbuf;
++	u32 offset;
++	u32 poc;
++
++	int referenced;
++	u32 num_reorder_pic;
++
++	u32 cur_slice_idx;
++	u32 cur_slice_type;
++
++	/* 2 lists (L0/L1) ; 800 slices ; 16 refs */
++	u32 ref_poc_list[2][MAX_SLICE_NUM][MAX_REF_ACTIVE];
++	u32 ref_num[2];
++};
++
++struct codec_hevc {
++	struct mutex lock;
++
++	/* Common part of the HEVC decoder */
++	struct codec_hevc_common common;
++
++	/* Buffer for the HEVC Workspace */
++	void      *workspace_vaddr;
++	dma_addr_t workspace_paddr;
++
++	/* AUX buffer */
++	void      *aux_vaddr;
++	dma_addr_t aux_paddr;
++
++	/* Contains many information parsed from the bitstream */
++	union rpm_param rpm_param;
++
++	/* Information computed from the RPM */
++	u32 lcu_size; // Largest Coding Unit
++	u32 lcu_x_num;
++	u32 lcu_y_num;
++	u32 lcu_total;
++
++	/* Current Frame being handled */
++	struct hevc_frame *cur_frame;
++	u32 curr_poc;
++	/* Collocated Reference Picture */
++	struct hevc_frame *col_frame;
++	u32 col_poc;
++
++	/* All ref frames used by the HW at a given time */
++	struct list_head ref_frames_list;
++	u32 frames_num;
++
++	/* Coded resolution reported by the hardware */
++	u32 width, height;
++	/* Resolution minus the conformance window offsets */
++	u32 dst_width, dst_height;
++
++	u32 prev_tid0_poc;
++	u32 slice_segment_addr;
++	u32 slice_addr;
++	u32 ldc_flag;
++
++	/* Whether we detected the bitstream as 10-bit */
++	int is_10bit;
++};
++
++static u32 codec_hevc_num_pending_bufs(struct amvdec_session *sess)
++{
++	struct codec_hevc *hevc;
++	u32 ret;
++
++	hevc = sess->priv;
++	if (!hevc)
++		return 0;
++
++	mutex_lock(&hevc->lock);
++	ret = hevc->frames_num;
++	mutex_unlock(&hevc->lock);
++
++	return ret;
++}
++
++/* Update the L0 and L1 reference lists for a given frame */
++static void codec_hevc_update_frame_refs(struct amvdec_session *sess,
++					 struct hevc_frame *frame)
++{
++	struct codec_hevc *hevc = sess->priv;
++	union rpm_param *params = &hevc->rpm_param;
++	int num_ref_idx_l0_active =
++		(params->p.num_ref_idx_l0_active > MAX_REF_ACTIVE) ?
++		MAX_REF_ACTIVE : params->p.num_ref_idx_l0_active;
++	int num_ref_idx_l1_active =
++		(params->p.num_ref_idx_l1_active > MAX_REF_ACTIVE) ?
++		MAX_REF_ACTIVE : params->p.num_ref_idx_l1_active;
++	int ref_picset0[MAX_REF_ACTIVE] = { 0 };
++	int ref_picset1[MAX_REF_ACTIVE] = { 0 };
++	u16 *mod_list = params->p.modification_list;
++	int num_neg = 0;
++	int num_pos = 0;
++	int total_num;
++	int i;
++
++	for (i = 0; i < MAX_REF_ACTIVE; i++) {
++		frame->ref_poc_list[0][frame->cur_slice_idx][i] = 0;
++		frame->ref_poc_list[1][frame->cur_slice_idx][i] = 0;
++	}
++
++	for (i = 0; i < MAX_REF_ACTIVE; i++) {
++		u16 cur_rps = params->p.CUR_RPS[i];
++		int delt = cur_rps & ((1 << (RPS_USED_BIT - 1)) - 1);
++
++		if (cur_rps & 0x8000)
++			break;
++
++		if (!((cur_rps >> RPS_USED_BIT) & 1))
++			continue;
++
++		if ((cur_rps >> (RPS_USED_BIT - 1)) & 1) {
++			ref_picset0[num_neg] =
++			       frame->poc - ((1 << (RPS_USED_BIT - 1)) - delt);
++			num_neg++;
++		} else {
++			ref_picset1[num_pos] = frame->poc + delt;
++			num_pos++;
++		}
++	}
++
++	total_num = num_neg + num_pos;
++
++	if (total_num <= 0)
++		goto end;
++
++	for (i = 0; i < num_ref_idx_l0_active; i++) {
++		int cidx;
++		if (params->p.modification_flag & 0x1)
++			cidx = mod_list[i];
++		else
++			cidx = i % total_num;
++
++		frame->ref_poc_list[0][frame->cur_slice_idx][i] =
++			cidx >= num_neg ? ref_picset1[cidx - num_neg] :
++			ref_picset0[cidx];
++	}
++
++	if (params->p.slice_type != B_SLICE)
++		goto end;
++
++	if (params->p.modification_flag & 0x2) {
++		for (i = 0; i < num_ref_idx_l1_active; i++) {
++			int cidx;
++			if (params->p.modification_flag & 0x1)
++				cidx = mod_list[num_ref_idx_l0_active + i];
++			else
++				cidx = mod_list[i];
++
++			frame->ref_poc_list[1][frame->cur_slice_idx][i] =
++				(cidx >= num_pos) ? ref_picset0[cidx - num_pos]
++				: ref_picset1[cidx];
++		}
++	} else {
++		for (i = 0; i < num_ref_idx_l1_active; i++) {
++			int cidx = i % total_num;
++			frame->ref_poc_list[1][frame->cur_slice_idx][i] =
++				cidx >= num_pos ? ref_picset0[cidx - num_pos] :
++				ref_picset1[cidx];
++		}
++	}
++
++end:
++	frame->ref_num[0] = num_ref_idx_l0_active;
++	frame->ref_num[1] = num_ref_idx_l1_active;
++
++	dev_dbg(sess->core->dev,
++		"Frame %u; slice %u; slice_type %u; num_l0 %u; num_l1 %u\n",
++		frame->poc, frame->cur_slice_idx, params->p.slice_type,
++		frame->ref_num[0], frame->ref_num[1]);
++}
++
++static void codec_hevc_update_ldc_flag(struct codec_hevc *hevc)
++{
++	struct hevc_frame *frame = hevc->cur_frame;
++	u32 slice_type = frame->cur_slice_type;
++	u32 slice_idx = frame->cur_slice_idx;
++	int i;
++
++	hevc->ldc_flag = 0;
++
++	if (slice_type == I_SLICE)
++		return;
++
++	hevc->ldc_flag = 1;
++	for (i = 0; (i < frame->ref_num[0]) && hevc->ldc_flag; i++) {
++		if (frame->ref_poc_list[0][slice_idx][i] > frame->poc) {
++			hevc->ldc_flag = 0;
++			break;
++		}
++	}
++
++	if (slice_type == P_SLICE)
++		return;
++
++	for (i = 0; (i < frame->ref_num[1]) && hevc->ldc_flag; i++) {
++		if (frame->ref_poc_list[1][slice_idx][i] > frame->poc) {
++			hevc->ldc_flag = 0;
++			break;
++		}
++	}
++}
++
++/* Tag "old" frames that are no longer referenced */
++static void codec_hevc_update_referenced(struct codec_hevc *hevc)
++{
++	union rpm_param *param = &hevc->rpm_param;
++	struct hevc_frame *frame;
++	int i;
++	u32 curr_poc = hevc->curr_poc;
++
++	list_for_each_entry(frame, &hevc->ref_frames_list, list) {
++		int is_referenced = 0;
++		u32 poc_tmp;
++
++		if (!frame->referenced)
++			continue;
++
++		for (i = 0; i < MAX_REF_ACTIVE; i++) {
++			int delt;
++			if (param->p.CUR_RPS[i] & 0x8000)
++				break;
++
++			delt = param->p.CUR_RPS[i] &
++			       ((1 << (RPS_USED_BIT - 1)) - 1);
++			if (param->p.CUR_RPS[i] & (1 << (RPS_USED_BIT - 1))) {
++				poc_tmp = curr_poc -
++					  ((1 << (RPS_USED_BIT - 1)) - delt);
++			} else
++				poc_tmp = curr_poc + delt;
++			if (poc_tmp == frame->poc) {
++				is_referenced = 1;
++				break;
++			}
++		}
++
++		frame->referenced = is_referenced;
++	}
++}
++
++static struct hevc_frame *
++codec_hevc_get_lowest_poc_frame(struct codec_hevc *hevc)
++{
++	struct hevc_frame *tmp, *ret = NULL;
++	u32 poc = INT_MAX;
++
++	list_for_each_entry(tmp, &hevc->ref_frames_list, list) {
++		if (tmp->poc < poc) {
++			ret = tmp;
++			poc = tmp->poc;
++		}
++	}
++
++	return ret;
++}
++
++/* Try to output as many frames as possible */
++static void codec_hevc_output_frames(struct amvdec_session *sess)
++{
++	struct hevc_frame *tmp;
++	struct codec_hevc *hevc = sess->priv;
++
++	while ((tmp = codec_hevc_get_lowest_poc_frame(hevc))) {
++		if (hevc->curr_poc &&
++		    (tmp->referenced ||
++		     tmp->num_reorder_pic >= hevc->frames_num))
++			break;
++
++		dev_dbg(sess->core->dev, "DONE frame poc %u; vbuf %u\n",
++			tmp->poc, tmp->vbuf->vb2_buf.index);
++		amvdec_dst_buf_done_offset(sess, tmp->vbuf, tmp->offset,
++					   V4L2_FIELD_NONE, false);
++		list_del(&tmp->list);
++		kfree(tmp);
++		hevc->frames_num--;
++	}
++}
++
++
++static int
++codec_hevc_setup_workspace(struct amvdec_session *sess,
++			   struct codec_hevc *hevc)
++{
++	struct amvdec_core *core = sess->core;
++	u32 revision = core->platform->revision;
++	dma_addr_t wkaddr;
++
++	/* Allocate some memory for the HEVC decoder's state */
++	hevc->workspace_vaddr = dma_alloc_coherent(core->dev, SIZE_WORKSPACE,
++						   &wkaddr, GFP_KERNEL);
++	if (!hevc->workspace_vaddr)
++		return -ENOMEM;
++
++	hevc->workspace_paddr = wkaddr;
++
++	amvdec_write_dos(core, HEVCD_IPP_LINEBUFF_BASE, wkaddr + IPP_OFFSET);
++	amvdec_write_dos(core, HEVC_RPM_BUFFER, wkaddr + RPM_OFFSET);
++	amvdec_write_dos(core, HEVC_SHORT_TERM_RPS, wkaddr + SH_TM_RPS_OFFSET);
++	amvdec_write_dos(core, HEVC_VPS_BUFFER, wkaddr + VPS_OFFSET);
++	amvdec_write_dos(core, HEVC_SPS_BUFFER, wkaddr + SPS_OFFSET);
++	amvdec_write_dos(core, HEVC_PPS_BUFFER, wkaddr + PPS_OFFSET);
++	amvdec_write_dos(core, HEVC_SAO_UP, wkaddr + SAO_UP_OFFSET);
++
++	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, hevc->is_10bit)) {
++		amvdec_write_dos(core, HEVC_SAO_MMU_VH0_ADDR,
++				 wkaddr + MMU_VBH_OFFSET);
++		amvdec_write_dos(core, HEVC_SAO_MMU_VH1_ADDR,
++				 wkaddr + MMU_VBH_OFFSET + (MMU_VBH_SIZE / 2));
++
++		if (revision >= VDEC_REVISION_G12A)
++			amvdec_write_dos(core, HEVC_ASSIST_MMU_MAP_ADDR,
++					 hevc->common.mmu_map_paddr);
++		else
++			amvdec_write_dos(core, H265_MMU_MAP_BUFFER,
++					 hevc->common.mmu_map_paddr);
++	} else if (revision < VDEC_REVISION_G12A) {
++		amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER,
++				 wkaddr + SWAP_BUF_OFFSET);
++		amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER2,
++				 wkaddr + SWAP_BUF2_OFFSET);
++	}
++
++	amvdec_write_dos(core, HEVC_SCALELUT, wkaddr + SCALELUT_OFFSET);
++	amvdec_write_dos(core, HEVC_DBLK_CFG4, wkaddr + DBLK_PARA_OFFSET);
++	amvdec_write_dos(core, HEVC_DBLK_CFG5, wkaddr + DBLK_DATA_OFFSET);
++	if (revision >= VDEC_REVISION_G12A)
++		amvdec_write_dos(core, HEVC_DBLK_CFGE,
++				 wkaddr + DBLK_DATA2_OFFSET);
++
++	amvdec_write_dos(core, LMEM_DUMP_ADR, wkaddr + LMEM_OFFSET);
++
++	return 0;
++}
++
++static int codec_hevc_start(struct amvdec_session *sess)
++{
++	struct amvdec_core *core = sess->core;
++	struct codec_hevc *hevc;
++	u32 val;
++	int i;
++	int ret;
++
++	hevc = kzalloc(sizeof(*hevc), GFP_KERNEL);
++	if (!hevc)
++		return -ENOMEM;
++
++	INIT_LIST_HEAD(&hevc->ref_frames_list);
++	hevc->curr_poc = INVALID_POC;
++
++	ret = codec_hevc_setup_workspace(sess, hevc);
++	if (ret)
++		goto free_hevc;
++
++	val = BIT(0); /* stream_fetch_enable */
++	if (core->platform->revision >= VDEC_REVISION_G12A)
++		val |= (0xf << 25); /* arwlen_axi_max */
++	amvdec_write_dos_bits(core, HEVC_STREAM_CONTROL, val);
++
++	val = amvdec_read_dos(core, HEVC_PARSER_INT_CONTROL) & 0x03ffffff;
++	val |= (3 << 29) | BIT(27) | BIT(24) | BIT(22) | BIT(7) | BIT(4) |
++	       BIT(0);
++	amvdec_write_dos(core, HEVC_PARSER_INT_CONTROL, val);
++	amvdec_write_dos_bits(core, HEVC_SHIFT_STATUS, BIT(1) | BIT(0));
++	amvdec_write_dos(core, HEVC_SHIFT_CONTROL,
++			 (3 << 6) | BIT(5) | BIT(2) | BIT(0));
++	amvdec_write_dos(core, HEVC_CABAC_CONTROL, 1);
++	amvdec_write_dos(core, HEVC_PARSER_CORE_CONTROL, 1);
++	amvdec_write_dos(core, HEVC_DEC_STATUS_REG, 0);
++
++	amvdec_write_dos(core, HEVC_IQIT_SCALELUT_WR_ADDR, 0);
++	for (i = 0; i < 1024; ++i)
++		amvdec_write_dos(core, HEVC_IQIT_SCALELUT_DATA, 0);
++
++	amvdec_write_dos(core, HEVC_DECODE_SIZE, 0);
++
++	amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE, BIT(16));
++	for (i = 0; i < ARRAY_SIZE(vdec_hevc_parser_cmd); ++i)
++		amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE,
++				 vdec_hevc_parser_cmd[i]);
++
++	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
++	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
++	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
++	amvdec_write_dos(core, HEVC_PARSER_IF_CONTROL,
++			 BIT(5) | BIT(2) | BIT(0));
++
++	amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(0));
++	amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(1));
++
++	amvdec_write_dos(core, HEVC_WAIT_FLAG, 1);
++
++	/* clear mailbox interrupt */
++	amvdec_write_dos(core, HEVC_ASSIST_MBOX1_CLR_REG, 1);
++	/* enable mailbox interrupt */
++	amvdec_write_dos(core, HEVC_ASSIST_MBOX1_MASK, 1);
++	/* disable PSCALE for hardware sharing */
++	amvdec_write_dos(core, HEVC_PSCALE_CTRL, 0);
++	/* Let the uCode do all the parsing */
++	amvdec_write_dos(core, NAL_SEARCH_CTL, 0xc);
++
++	amvdec_write_dos(core, DECODE_STOP_POS, 0);
++	amvdec_write_dos(core, HEVC_DECODE_MODE, DECODE_MODE_SINGLE);
++	amvdec_write_dos(core, HEVC_DECODE_MODE2, 0);
++
++	/* AUX buffers */
++	hevc->aux_vaddr = dma_alloc_coherent(core->dev, SIZE_AUX,
++					     &hevc->aux_paddr, GFP_KERNEL);
++	if (!hevc->aux_vaddr) {
++		dev_err(core->dev, "Failed to request HEVC AUX\n");
++		ret = -ENOMEM;
++		goto free_hevc;
++	}
++
++	amvdec_write_dos(core, HEVC_AUX_ADR, hevc->aux_paddr);
++	amvdec_write_dos(core, HEVC_AUX_DATA_SIZE,
++			 (((SIZE_AUX) >> 4) << 16) | 0);
++	mutex_init(&hevc->lock);
++	sess->priv = hevc;
++
++	return 0;
++
++free_hevc:
++	kfree(hevc);
++	return ret;
++}
++
++static void codec_hevc_flush_output(struct amvdec_session *sess)
++{
++	struct codec_hevc *hevc = sess->priv;
++	struct hevc_frame *tmp;
++
++	while (!list_empty(&hevc->ref_frames_list)) {
++		tmp = codec_hevc_get_lowest_poc_frame(hevc);
++		amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE);
++		list_del(&tmp->list);
++		kfree(tmp);
++		hevc->frames_num--;
++	}
++}
++
++static int codec_hevc_stop(struct amvdec_session *sess)
++{
++	struct codec_hevc *hevc = sess->priv;
++	struct amvdec_core *core = sess->core;
++
++	mutex_lock(&hevc->lock);
++	codec_hevc_flush_output(sess);
++
++	if (hevc->workspace_vaddr)
++		dma_free_coherent(core->dev, SIZE_WORKSPACE,
++				  hevc->workspace_vaddr,
++				  hevc->workspace_paddr);
++
++	if (hevc->aux_vaddr)
++		dma_free_coherent(core->dev, SIZE_AUX,
++				  hevc->aux_vaddr, hevc->aux_paddr);
++
++	codec_hevc_free_fbc_buffers(sess, &hevc->common);
++	mutex_unlock(&hevc->lock);
++	mutex_destroy(&hevc->lock);
++
++	return 0;
++}
++
++static struct hevc_frame *
++codec_hevc_get_frame_by_poc(struct codec_hevc *hevc, u32 poc)
++{
++	struct hevc_frame *tmp;
++
++	list_for_each_entry(tmp, &hevc->ref_frames_list, list) {
++		if (tmp->poc == poc)
++			return tmp;
++	}
++
++	return NULL;
++}
++
++static struct hevc_frame *
++codec_hevc_prepare_new_frame(struct amvdec_session *sess)
++{
++	struct amvdec_core *core = sess->core;
++	struct hevc_frame *new_frame = NULL;
++	struct codec_hevc *hevc = sess->priv;
++	struct vb2_v4l2_buffer *vbuf;
++	union rpm_param *params = &hevc->rpm_param;
++
++	new_frame = kzalloc(sizeof(*new_frame), GFP_KERNEL);
++	if (!new_frame)
++		return NULL;
++
++	vbuf = v4l2_m2m_dst_buf_remove(sess->m2m_ctx);
++	if (!vbuf) {
++		dev_err(sess->core->dev, "No dst buffer available\n");
++		return NULL;
++	}
++
++	new_frame->vbuf = vbuf;
++	new_frame->referenced = 1;
++	new_frame->poc = hevc->curr_poc;
++	new_frame->cur_slice_type = params->p.slice_type;
++	new_frame->num_reorder_pic = params->p.sps_num_reorder_pics_0;
++	new_frame->offset = amvdec_read_dos(core, HEVC_SHIFT_BYTE_COUNT);
++
++	list_add_tail(&new_frame->list, &hevc->ref_frames_list);
++	hevc->frames_num++;
++
++	return new_frame;
++}
++
++static void
++codec_hevc_set_sao(struct amvdec_session *sess, struct hevc_frame *frame)
++{
++	struct amvdec_core *core = sess->core;
++	struct codec_hevc *hevc = sess->priv;
++	struct vb2_buffer *vb = &frame->vbuf->vb2_buf;
++	union rpm_param *param = &hevc->rpm_param;
++	u32 pic_height_cu =
++		(hevc->height + hevc->lcu_size - 1) / hevc->lcu_size;
++	u32 sao_mem_unit = (hevc->lcu_size == 16 ? 9 :
++			   hevc->lcu_size == 32 ? 14 : 24) << 4;
++	u32 sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu;
++	u32 misc_flag0 = param->p.misc_flag0;
++	dma_addr_t buf_y_paddr;
++	dma_addr_t buf_u_v_paddr;
++	u32 slice_deblocking_filter_disabled_flag;
++	u32 val, val_2;
++
++	val = (amvdec_read_dos(core, HEVC_SAO_CTRL0) & ~0xf) |
++	      ilog2(hevc->lcu_size);
++	amvdec_write_dos(core, HEVC_SAO_CTRL0, val);
++
++	amvdec_write_dos(core, HEVC_SAO_PIC_SIZE,
++			 hevc->width | (hevc->height << 16));
++	amvdec_write_dos(core, HEVC_SAO_PIC_SIZE_LCU,
++			 (hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
++
++	if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit) ||
++	    codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
++			       hevc->is_10bit))
++		buf_y_paddr =
++		     hevc->common.fbc_buffer_paddr[vb->index];
++	else
++		buf_y_paddr =
++		       vb2_dma_contig_plane_dma_addr(vb, 0);
++
++	if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
++		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000;
++		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
++		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
++	}
++
++	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
++		buf_y_paddr =
++		       vb2_dma_contig_plane_dma_addr(vb, 0);
++		buf_u_v_paddr =
++		       vb2_dma_contig_plane_dma_addr(vb, 1);
++		amvdec_write_dos(core, HEVC_SAO_Y_START_ADDR, buf_y_paddr);
++		amvdec_write_dos(core, HEVC_SAO_C_START_ADDR, buf_u_v_paddr);
++		amvdec_write_dos(core, HEVC_SAO_Y_WPTR, buf_y_paddr);
++		amvdec_write_dos(core, HEVC_SAO_C_WPTR, buf_u_v_paddr);
++	}
++
++	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
++			       hevc->is_10bit)) {
++		dma_addr_t header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
++		if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit))
++			header_adr = hevc->common.mmu_header_paddr[vb->index];
++		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
++		/* use HEVC_CM_HEADER_START_ADDR */
++		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
++		amvdec_write_dos_bits(core, HEVC_SAO_CTRL9, BIT(0));
++	}
++
++	amvdec_write_dos(core, HEVC_SAO_Y_LENGTH,
++			 amvdec_get_output_size(sess));
++	amvdec_write_dos(core, HEVC_SAO_C_LENGTH,
++			 (amvdec_get_output_size(sess) / 2));
++
++	if (frame->cur_slice_idx == 0) {
++		if (core->platform->revision >= VDEC_REVISION_G12A) {
++			if (core->platform->revision >= VDEC_REVISION_SM1)
++				val = 0xfc << 8;
++			else
++				val = 0x54 << 8;
++
++			/* enable first, compressed write */
++			if (codec_hevc_use_fbc(sess->pixfmt_cap,
++					       hevc->is_10bit))
++				val |= BIT(8);
++
++			/* enable second, uncompressed write */
++			if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
++				val |= BIT(9);
++
++			/* dblk pipeline mode=1 for performance */
++			if (hevc->width >= 1280)
++				val |= BIT(4);
++
++			amvdec_write_dos(core, HEVC_DBLK_CFGB, val);
++			amvdec_write_dos(core, HEVC_DBLK_STS1 + 16, BIT(28));
++		}
++
++		amvdec_write_dos(core, HEVC_DBLK_CFG2,
++				 hevc->width | (hevc->height << 16));
++
++		val = 0;
++		if ((misc_flag0 >> PCM_ENABLE_FLAG_BIT) & 0x1)
++			val |= ((misc_flag0 >>
++				 PCM_LOOP_FILTER_DISABLED_FLAG_BIT) & 0x1) << 3;
++
++		val |= (param->p.pps_cb_qp_offset & 0x1f) << 4;
++		val |= (param->p.pps_cr_qp_offset & 0x1f) << 9;
++		val |= (hevc->lcu_size == 64) ? 0 :
++		       ((hevc->lcu_size == 32) ? 1 : 2);
++		amvdec_write_dos(core, HEVC_DBLK_CFG1, val);
++	}
++
++	val = amvdec_read_dos(core, HEVC_SAO_CTRL1) & ~0x3ff3;
++	val |= 0xff0; /* Set endianness for 2-bytes swaps (nv12) */
++	if (core->platform->revision < VDEC_REVISION_G12A) {
++		if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit))
++			val |= BIT(0); /* disable cm compression */
++		/* TOFIX: Handle Amlogic Framebuffer compression */
++	}
++
++	amvdec_write_dos(core, HEVC_SAO_CTRL1, val);
++
++	if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
++		/* no downscale for NV12 */
++		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000;
++		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
++	}
++
++	val = amvdec_read_dos(core, HEVCD_IPP_AXIIF_CONFIG) & ~0x30;
++	val |= 0xf;
++	amvdec_write_dos(core, HEVCD_IPP_AXIIF_CONFIG, val);
++
++	val = 0;
++	val_2 = amvdec_read_dos(core, HEVC_SAO_CTRL0);
++	val_2 &= (~0x300);
++
++	slice_deblocking_filter_disabled_flag = (misc_flag0 >>
++			SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & 0x1;
++	if ((misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT))
++		&& (misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT))) {
++		val |= slice_deblocking_filter_disabled_flag << 2;
++
++		if (!slice_deblocking_filter_disabled_flag) {
++			val |= (param->p.slice_beta_offset_div2 & 0xf) << 3;
++			val |= (param->p.slice_tc_offset_div2 & 0xf) << 7;
++		}
++	} else {
++		val |=
++			((misc_flag0 >>
++			  PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & 0x1) << 2;
++
++		if (((misc_flag0 >> PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) &
++			 0x1) == 0) {
++			val |= (param->p.pps_beta_offset_div2 & 0xf) << 3;
++			val |= (param->p.pps_tc_offset_div2 & 0xf) << 7;
++		}
++	}
++	if ((misc_flag0 & (1 << PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT))
++		&& ((misc_flag0 & (1 << SLICE_SAO_LUMA_FLAG_BIT))
++			|| (misc_flag0 & (1 << SLICE_SAO_CHROMA_FLAG_BIT))
++			|| (!slice_deblocking_filter_disabled_flag))) {
++		val |=
++			((misc_flag0 >>
++			  SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
++			 & 0x1)	<< 1;
++		val_2 |=
++			((misc_flag0 >>
++			  SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
++			& 0x1) << 9;
++	} else {
++		val |=
++			((misc_flag0 >>
++			  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
++			 & 0x1) << 1;
++		val_2 |=
++			((misc_flag0 >>
++			  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
++			 & 0x1) << 9;
++	}
++
++	amvdec_write_dos(core, HEVC_DBLK_CFG9, val);
++	amvdec_write_dos(core, HEVC_SAO_CTRL0, val_2);
++
++	amvdec_write_dos(core, HEVC_sao_mem_unit, sao_mem_unit);
++	amvdec_write_dos(core, HEVC_SAO_ABV,
++			 hevc->workspace_paddr + SAO_ABV_OFFSET);
++	amvdec_write_dos(core, HEVC_sao_vb_size, sao_vb_size);
++	amvdec_write_dos(core, HEVC_SAO_VB,
++			 hevc->workspace_paddr + SAO_VB_OFFSET);
++}
++
++static dma_addr_t codec_hevc_get_frame_mv_paddr(struct codec_hevc *hevc,
++						struct hevc_frame *frame)
++{
++	return hevc->workspace_paddr + MPRED_MV_OFFSET +
++		(frame->vbuf->vb2_buf.index * MPRED_MV_BUF_SIZE);
++}
++
++static void
++codec_hevc_set_mpred_ctrl(struct amvdec_core *core, struct codec_hevc *hevc)
++{
++	union rpm_param *param = &hevc->rpm_param;
++	u32 slice_type = param->p.slice_type;
++	u32 lcu_size_log2 = ilog2(hevc->lcu_size);
++	u32 val;
++
++	val = slice_type |
++	      MPRED_CTRL0_ABOVE_EN |
++	      MPRED_CTRL0_MV_WR_EN |
++	      MPRED_CTRL0_BUF_LINEAR |
++	      (lcu_size_log2 << 16) |
++	      (3 << 20) | /* cu_size_log2 */
++	      (param->p.log2_parallel_merge_level << 24);
++
++	if (slice_type != I_SLICE)
++		val |= MPRED_CTRL0_MV_RD_EN;
++
++	if (param->p.collocated_from_l0_flag)
++		val |= MPRED_CTRL0_COL_FROM_L0;
++
++	if (param->p.slice_temporal_mvp_enable_flag)
++		val |= MPRED_CTRL0_TMVP;
++
++	if (hevc->ldc_flag)
++		val |= MPRED_CTRL0_LDC;
++
++	if (param->p.dependent_slice_segment_flag)
++		val |= MPRED_CTRL0_NEW_SLI_SEG;
++
++	if (param->p.slice_segment_address == 0)
++		val |= MPRED_CTRL0_NEW_PIC |
++		       MPRED_CTRL0_NEW_TILE;
++
++	amvdec_write_dos(core, HEVC_MPRED_CTRL0, val);
++
++	val = (5 - param->p.five_minus_max_num_merge_cand) |
++	      (AMVP_MAX_NUM_CANDS << 4) |
++	      (AMVP_MAX_NUM_CANDS_MEM << 8) |
++	      (NUM_CHROMA_MODE << 12) |
++	      (DM_CHROMA_IDX << 16);
++	amvdec_write_dos(core, HEVC_MPRED_CTRL1, val);
++}
++
++static void codec_hevc_set_mpred_mv(struct amvdec_core *core,
++				    struct codec_hevc *hevc,
++				    struct hevc_frame *frame,
++				    struct hevc_frame *col_frame)
++{
++	union rpm_param *param = &hevc->rpm_param;
++	u32 lcu_size_log2 = ilog2(hevc->lcu_size);
++	u32 mv_mem_unit = lcu_size_log2 == 6 ? 0x200 :
++			  lcu_size_log2 == 5 ? 0x80 : 0x20;
++	dma_addr_t col_mv_rd_start_addr, col_mv_rd_ptr, col_mv_rd_end_addr;
++	dma_addr_t mpred_mv_wr_ptr;
++	u32 val;
++
++	val = amvdec_read_dos(core, HEVC_MPRED_CURR_LCU);
++
++	col_mv_rd_start_addr = codec_hevc_get_frame_mv_paddr(hevc, col_frame);
++	mpred_mv_wr_ptr = codec_hevc_get_frame_mv_paddr(hevc, frame) +
++			  (hevc->slice_addr * mv_mem_unit);
++	col_mv_rd_ptr = col_mv_rd_start_addr +
++			(hevc->slice_addr * mv_mem_unit);
++	col_mv_rd_end_addr = col_mv_rd_start_addr +
++			     (hevc->lcu_total * mv_mem_unit);
++
++	amvdec_write_dos(core, HEVC_MPRED_MV_WR_START_ADDR,
++			 codec_hevc_get_frame_mv_paddr(hevc, frame));
++	amvdec_write_dos(core, HEVC_MPRED_MV_RD_START_ADDR,
++			 col_mv_rd_start_addr);
++
++	if (param->p.slice_segment_address == 0) {
++		amvdec_write_dos(core, HEVC_MPRED_ABV_START_ADDR,
++				 hevc->workspace_paddr + MPRED_ABV_OFFSET);
++		amvdec_write_dos(core, HEVC_MPRED_MV_WPTR, mpred_mv_wr_ptr);
++		amvdec_write_dos(core, HEVC_MPRED_MV_RPTR,
++				 col_mv_rd_start_addr);
++	} else {
++		amvdec_write_dos(core, HEVC_MPRED_MV_RPTR, col_mv_rd_ptr);
++	}
++
++	amvdec_write_dos(core, HEVC_MPRED_MV_RD_END_ADDR, col_mv_rd_end_addr);
++}
++
++/* Update motion prediction with the current slice */
++static void codec_hevc_set_mpred(struct amvdec_session *sess,
++				 struct hevc_frame *frame,
++				 struct hevc_frame *col_frame)
++{
++	struct amvdec_core *core = sess->core;
++	struct codec_hevc *hevc = sess->priv;
++	u32 *ref_num = frame->ref_num;
++	u32 *ref_poc_l0 = frame->ref_poc_list[0][frame->cur_slice_idx];
++	u32 *ref_poc_l1 = frame->ref_poc_list[1][frame->cur_slice_idx];
++	u32 val;
++	int i;
++
++	codec_hevc_set_mpred_ctrl(core, hevc);
++	codec_hevc_set_mpred_mv(core, hevc, frame, col_frame);
++
++	amvdec_write_dos(core, HEVC_MPRED_PIC_SIZE,
++			 hevc->width | (hevc->height << 16));
++
++	val = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
++	amvdec_write_dos(core, HEVC_MPRED_PIC_SIZE_LCU, val);
++
++	amvdec_write_dos(core, HEVC_MPRED_REF_NUM,
++			 (ref_num[1] << 8) | ref_num[0]);
++	amvdec_write_dos(core, HEVC_MPRED_REF_EN_L0, (1 << ref_num[0]) - 1);
++	amvdec_write_dos(core, HEVC_MPRED_REF_EN_L1, (1 << ref_num[1]) - 1);
++
++	amvdec_write_dos(core, HEVC_MPRED_CUR_POC, hevc->curr_poc);
++	amvdec_write_dos(core, HEVC_MPRED_COL_POC, hevc->col_poc);
++
++	for (i = 0; i < MAX_REF_ACTIVE; ++i) {
++		amvdec_write_dos(core, HEVC_MPRED_L0_REF00_POC + i * 4,
++				 ref_poc_l0[i]);
++		amvdec_write_dos(core, HEVC_MPRED_L1_REF00_POC + i * 4,
++				 ref_poc_l1[i]);
++	}
++}
++
++/*  motion compensation reference cache controller */
++static void codec_hevc_set_mcrcc(struct amvdec_session *sess)
++{
++	struct amvdec_core *core = sess->core;
++	struct codec_hevc *hevc = sess->priv;
++	u32 val, val_2;
++	int l0_cnt = 0;
++	int l1_cnt = 0x7fff;
++
++	if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
++		l0_cnt = hevc->cur_frame->ref_num[0];
++		l1_cnt = hevc->cur_frame->ref_num[1];
++	}
++
++	if (hevc->cur_frame->cur_slice_type == I_SLICE) {
++		amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0);
++		return;
++	}
++
++	if (hevc->cur_frame->cur_slice_type == P_SLICE) {
++		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
++				 BIT(1));
++		val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
++		val &= 0xffff;
++		val |= (val << 16);
++		amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val);
++
++		if (l0_cnt == 1) {
++			amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
++		} else {
++			val = amvdec_read_dos(core,
++					      HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
++			val &= 0xffff;
++			val |= (val << 16);
++			amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
++		}
++	} else { /* B_SLICE */
++		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 0);
++		val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
++		val &= 0xffff;
++		val |= (val << 16);
++		amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val);
++
++		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
++				 BIT(12) | BIT(1));
++		val_2 = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
++		val_2 &= 0xffff;
++		val_2 |= (val_2 << 16);
++		if (val == val_2 && l1_cnt > 1) {
++			val_2 = amvdec_read_dos(core,
++						HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
++			val_2 &= 0xffff;
++			val_2 |= (val_2 << 16);
++		}
++		amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
++	}
++
++	/* enable mcrcc progressive-mode */
++	amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0xff0);
++}
++
++static void codec_hevc_set_ref_list(struct amvdec_session *sess,
++				u32 ref_num, u32 *ref_poc_list)
++{
++	struct codec_hevc *hevc = sess->priv;
++	struct hevc_frame *ref_frame;
++	struct amvdec_core *core = sess->core;
++	int i;
++	u32 buf_id_y;
++	u32 buf_id_uv;
++
++	for (i = 0; i < ref_num; i++) {
++		ref_frame = codec_hevc_get_frame_by_poc(hevc, ref_poc_list[i]);
++
++		if (!ref_frame) {
++			dev_warn(core->dev, "Couldn't find ref. frame %u\n",
++				ref_poc_list[i]);
++			continue;
++		}
++
++		if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
++			buf_id_y = buf_id_uv = ref_frame->vbuf->vb2_buf.index;
++		} else {
++			buf_id_y = ref_frame->vbuf->vb2_buf.index * 2;
++			buf_id_uv = buf_id_y + 1;
++		}
++
++		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
++				 (buf_id_uv << 16) |
++				 (buf_id_uv << 8) |
++				 buf_id_y);
++	}
++}
++
++static void codec_hevc_set_mc(struct amvdec_session *sess,
++			      struct hevc_frame *frame)
++{
++	struct amvdec_core *core = sess->core;
++
++	if (frame->cur_slice_type == I_SLICE)
++		return;
++
++	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
++	codec_hevc_set_ref_list(sess, frame->ref_num[0],
++		frame->ref_poc_list[0][frame->cur_slice_idx]);
++
++	if (frame->cur_slice_type == P_SLICE)
++		return;
++
++	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
++			 BIT(12) | BIT(0));
++	codec_hevc_set_ref_list(sess, frame->ref_num[1],
++		frame->ref_poc_list[1][frame->cur_slice_idx]);
++}
++
++static void codec_hevc_update_col_frame(struct codec_hevc *hevc)
++{
++	struct hevc_frame *cur_frame = hevc->cur_frame;
++	union rpm_param *param = &hevc->rpm_param;
++	u32 list_no = 0;
++	u32 col_ref = param->p.collocated_ref_idx;
++	u32 col_from_l0 = param->p.collocated_from_l0_flag;
++	u32 cur_slice_idx = cur_frame->cur_slice_idx;
++
++	if (cur_frame->cur_slice_type == B_SLICE)
++		list_no = 1 - col_from_l0;
++
++	if (col_ref >= cur_frame->ref_num[list_no])
++		hevc->col_poc = INVALID_POC;
++	else
++		hevc->col_poc = cur_frame->ref_poc_list[list_no]
++						       [cur_slice_idx]
++						       [col_ref];
++
++	if (cur_frame->cur_slice_type == I_SLICE)
++		goto end;
++
++	if (hevc->col_poc != INVALID_POC)
++		hevc->col_frame = codec_hevc_get_frame_by_poc(hevc,
++							      hevc->col_poc);
++	else
++		hevc->col_frame = hevc->cur_frame;
++
++end:
++	if (!hevc->col_frame)
++		hevc->col_frame = hevc->cur_frame;
++}
++
++static void codec_hevc_update_pocs(struct amvdec_session *sess)
++{
++	struct codec_hevc *hevc = sess->priv;
++	union rpm_param *param = &hevc->rpm_param;
++	u32 nal_unit_type = param->p.m_nalUnitType;
++	u32 temporal_id = param->p.m_temporalId & 0x7;
++	int max_poc_lsb =
++		1 << (param->p.log2_max_pic_order_cnt_lsb_minus4 + 4);
++	int prev_poc_lsb;
++	int prev_poc_msb;
++	int poc_msb;
++	int poc_lsb = param->p.POClsb;
++
++	if (nal_unit_type == NAL_UNIT_CODED_SLICE_IDR ||
++	    nal_unit_type == NAL_UNIT_CODED_SLICE_IDR_N_LP) {
++		hevc->curr_poc = 0;
++		if ((temporal_id - 1) == 0)
++			hevc->prev_tid0_poc = hevc->curr_poc;
++
++		return;
++	}
++
++	prev_poc_lsb = hevc->prev_tid0_poc % max_poc_lsb;
++	prev_poc_msb = hevc->prev_tid0_poc - prev_poc_lsb;
++
++	if ((poc_lsb < prev_poc_lsb) &&
++	    ((prev_poc_lsb - poc_lsb) >= (max_poc_lsb / 2)))
++		poc_msb = prev_poc_msb + max_poc_lsb;
++	else if ((poc_lsb > prev_poc_lsb) &&
++		 ((poc_lsb - prev_poc_lsb) > (max_poc_lsb / 2)))
++		poc_msb = prev_poc_msb - max_poc_lsb;
++	else
++		poc_msb = prev_poc_msb;
++
++	if (nal_unit_type == NAL_UNIT_CODED_SLICE_BLA   ||
++	    nal_unit_type == NAL_UNIT_CODED_SLICE_BLANT ||
++	    nal_unit_type == NAL_UNIT_CODED_SLICE_BLA_N_LP)
++		poc_msb = 0;
++
++	hevc->curr_poc = (poc_msb + poc_lsb);
++	if ((temporal_id - 1) == 0)
++		hevc->prev_tid0_poc = hevc->curr_poc;
++}
++
++static void codec_hevc_process_segment_header(struct amvdec_session *sess)
++{
++	struct codec_hevc *hevc = sess->priv;
++	union rpm_param *param = &hevc->rpm_param;
++
++	if (param->p.first_slice_segment_in_pic_flag == 0) {
++		hevc->slice_segment_addr = param->p.slice_segment_address;
++		if (!param->p.dependent_slice_segment_flag)
++			hevc->slice_addr = hevc->slice_segment_addr;
++	} else {
++		hevc->slice_segment_addr = 0;
++		hevc->slice_addr = 0;
++	}
++
++	codec_hevc_update_pocs(sess);
++}
++
++static int codec_hevc_process_segment(struct amvdec_session *sess)
++{
++	struct codec_hevc *hevc = sess->priv;
++	struct amvdec_core *core = sess->core;
++	union rpm_param *param = &hevc->rpm_param;
++	u32 slice_segment_address = param->p.slice_segment_address;
++
++	/* First slice: new frame */
++	if (slice_segment_address == 0) {
++		codec_hevc_update_referenced(hevc);
++		codec_hevc_output_frames(sess);
++
++		hevc->cur_frame = codec_hevc_prepare_new_frame(sess);
++		if (!hevc->cur_frame)
++			return -1;
++	} else {
++		hevc->cur_frame->cur_slice_idx++;
++	}
++
++	codec_hevc_update_frame_refs(sess, hevc->cur_frame);
++	codec_hevc_update_col_frame(hevc);
++	codec_hevc_update_ldc_flag(hevc);
++	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
++			       hevc->is_10bit))
++		codec_hevc_fill_mmu_map(sess, &hevc->common,
++					&hevc->cur_frame->vbuf->vb2_buf,
++					hevc->is_10bit);
++	codec_hevc_set_mc(sess, hevc->cur_frame);
++	codec_hevc_set_mcrcc(sess);
++	codec_hevc_set_mpred(sess, hevc->cur_frame, hevc->col_frame);
++	codec_hevc_set_sao(sess, hevc->cur_frame);
++
++	amvdec_write_dos_bits(core, HEVC_WAIT_FLAG, BIT(1));
++	amvdec_write_dos(core, HEVC_DEC_STATUS_REG,
++			 HEVC_CODED_SLICE_SEGMENT_DAT);
++
++	/* Interrupt the firmware's processor */
++	amvdec_write_dos(core, HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
++
++	return 0;
++}
++
++static int codec_hevc_process_rpm(struct codec_hevc *hevc)
++{
++	union rpm_param *param = &hevc->rpm_param;
++	int src_changed = 0;
++	u32 dst_width, dst_height;
++	u32 lcu_size;
++	u32 is_10bit = 0;
++
++	if (param->p.slice_segment_address	||
++	    !param->p.pic_width_in_luma_samples	||
++	    !param->p.pic_height_in_luma_samples)
++		return 0;
++
++	if (param->p.bit_depth)
++		is_10bit = 1;
++
++	hevc->width = param->p.pic_width_in_luma_samples;
++	hevc->height = param->p.pic_height_in_luma_samples;
++	dst_width = hevc->width;
++	dst_height = hevc->height;
++
++	lcu_size = 1 << (param->p.log2_min_coding_block_size_minus3 +
++		   3 + param->p.log2_diff_max_min_coding_block_size);
++
++	hevc->lcu_x_num = (hevc->width + lcu_size - 1) / lcu_size;
++	hevc->lcu_y_num = (hevc->height + lcu_size - 1) / lcu_size;
++	hevc->lcu_total = hevc->lcu_x_num * hevc->lcu_y_num;
++
++	if (param->p.conformance_window_flag) {
++		u32 sub_width = 1, sub_height = 1;
++
++		switch (param->p.chroma_format_idc) {
++		case 1:
++			sub_height = 2; /* fallthrough */
++		case 2:
++			sub_width = 2;
++			break;
++		}
++
++		dst_width -= sub_width *
++			     (param->p.conf_win_left_offset +
++			      param->p.conf_win_right_offset);
++		dst_height -= sub_height *
++			      (param->p.conf_win_top_offset +
++			       param->p.conf_win_bottom_offset);
++	}
++
++	if (dst_width != hevc->dst_width ||
++	    dst_height != hevc->dst_height ||
++	    lcu_size != hevc->lcu_size ||
++	    is_10bit != hevc->is_10bit)
++		src_changed = 1;
++
++	hevc->dst_width = dst_width;
++	hevc->dst_height = dst_height;
++	hevc->lcu_size = lcu_size;
++	hevc->is_10bit = is_10bit;
++
++	return src_changed;
++}
++
++/*
++ * The RPM section within the workspace contains
++ * many information regarding the parsed bitstream
++ */
++static void codec_hevc_fetch_rpm(struct amvdec_session *sess)
++{
++	struct codec_hevc *hevc = sess->priv;
++	u16 *rpm_vaddr = hevc->workspace_vaddr + RPM_OFFSET;
++	int i, j;
++
++	for (i = 0; i < RPM_SIZE; i += 4)
++		for (j = 0; j < 4; j++)
++			hevc->rpm_param.l.data[i + j] = rpm_vaddr[i + 3 - j];
++}
++
++static void codec_hevc_resume(struct amvdec_session *sess)
++{
++	struct codec_hevc *hevc = sess->priv;
++
++	if (codec_hevc_setup_buffers(sess, &hevc->common, hevc->is_10bit)) {
++		amvdec_abort(sess);
++		return;
++	}
++
++	codec_hevc_setup_decode_head(sess, hevc->is_10bit);
++	codec_hevc_process_segment_header(sess);
++	if (codec_hevc_process_segment(sess))
++		amvdec_abort(sess);
++}
++
++static irqreturn_t codec_hevc_threaded_isr(struct amvdec_session *sess)
++{
++	struct amvdec_core *core = sess->core;
++	struct codec_hevc *hevc = sess->priv;
++	u32 dec_status = amvdec_read_dos(core, HEVC_DEC_STATUS_REG);
++
++	if (!hevc)
++		return IRQ_HANDLED;
++
++	mutex_lock(&hevc->lock);
++	if (dec_status != HEVC_SLICE_SEGMENT_DONE) {
++		dev_err(core->dev_dec, "Unrecognized dec_status: %08X\n",
++			dec_status);
++		amvdec_abort(sess);
++		goto unlock;
++	}
++
++	sess->keyframe_found = 1;
++	codec_hevc_fetch_rpm(sess);
++	if (codec_hevc_process_rpm(hevc)) {
++		amvdec_src_change(sess, hevc->dst_width, hevc->dst_height, 16,
++				  hevc->is_10bit ? 10 : 8);
++		goto unlock;
++	}
++
++	codec_hevc_process_segment_header(sess);
++	if (codec_hevc_process_segment(sess))
++		amvdec_abort(sess);
++
++unlock:
++	mutex_unlock(&hevc->lock);
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t codec_hevc_isr(struct amvdec_session *sess)
++{
++	return IRQ_WAKE_THREAD;
++}
++
++struct amvdec_codec_ops codec_hevc_ops = {
++	.start = codec_hevc_start,
++	.stop = codec_hevc_stop,
++	.isr = codec_hevc_isr,
++	.threaded_isr = codec_hevc_threaded_isr,
++	.num_pending_bufs = codec_hevc_num_pending_bufs,
++	.drain = codec_hevc_flush_output,
++	.resume = codec_hevc_resume,
++};
+diff --git a/drivers/staging/media/meson/vdec/codec_hevc.h b/drivers/staging/media/meson/vdec/codec_hevc.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/staging/media/meson/vdec/codec_hevc.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
++ */
++
++#ifndef __MESON_VDEC_CODEC_HEVC_H_
++#define __MESON_VDEC_CODEC_HEVC_H_
++
++#include "vdec.h"
++
++extern struct amvdec_codec_ops codec_hevc_ops;
++
++#endif
+diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/esparser.c
++++ b/drivers/staging/media/meson/vdec/esparser.c
+@@ -308,7 +308,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
+ 	 * they could pause when there is no capture buffer available and
+ 	 * resume on this notification.
+ 	 */
+-	if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9) {
++	if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9 || sess->fmt_out->pixfmt ==V4L2_PIX_FMT_HEVC) {
+ 		if (codec_ops->num_pending_bufs)
+ 			num_dst_bufs = codec_ops->num_pending_bufs(sess);
+ 
+diff --git a/drivers/staging/media/meson/vdec/hevc_regs.h b/drivers/staging/media/meson/vdec/hevc_regs.h
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/hevc_regs.h
++++ b/drivers/staging/media/meson/vdec/hevc_regs.h
+@@ -205,6 +205,7 @@
+ #define HEVC_CM_HEADER_START_ADDR 0xd8a0
+ #define HEVC_CM_HEADER_LENGTH 0xd8a4
+ #define HEVC_CM_HEADER_OFFSET 0xd8ac
++#define HEVC_SAO_CTRL9 0xd8b4
+ #define HEVC_SAO_MMU_VH0_ADDR 0xd8e8
+ #define HEVC_SAO_MMU_VH1_ADDR 0xd8ec
+ 
+diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/vdec_platform.c
++++ b/drivers/staging/media/meson/vdec/vdec_platform.c
+@@ -11,6 +11,7 @@
+ #include "vdec_hevc.h"
+ #include "codec_mpeg12.h"
+ #include "codec_h264.h"
++#include "codec_hevc.h"
+ #include "codec_vp9.h"
+ 
+ static const struct amvdec_format vdec_formats_gxbb[] = {
+@@ -64,6 +65,18 @@ static const struct amvdec_format vdec_formats_gxl[] = {
+ 		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+ 		.flags = V4L2_FMT_FLAG_COMPRESSED |
+ 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
++	}, {
++		.pixfmt = V4L2_PIX_FMT_HEVC,
++		.min_buffers = 4,
++		.max_buffers = 24,
++		.max_width = 3840,
++		.max_height = 2160,
++		.vdec_ops = &vdec_hevc_ops,
++		.codec_ops = &codec_hevc_ops,
++		.firmware_path = "meson/vdec/gxl_hevc.bin",
++		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
++		.flags = V4L2_FMT_FLAG_COMPRESSED |
++			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+ 	}, {
+ 		.pixfmt = V4L2_PIX_FMT_H264,
+ 		.min_buffers = 2,
+@@ -114,6 +127,18 @@ static const struct amvdec_format vdec_formats_gxm[] = {
+ 		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+ 		.flags = V4L2_FMT_FLAG_COMPRESSED |
+ 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
++	}, {
++		.pixfmt = V4L2_PIX_FMT_HEVC,
++		.min_buffers = 4,
++		.max_buffers = 24,
++		.max_width = 3840,
++		.max_height = 2160,
++		.vdec_ops = &vdec_hevc_ops,
++		.codec_ops = &codec_hevc_ops,
++		.firmware_path = "meson/vdec/gxl_hevc.bin",
++		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
++		.flags = V4L2_FMT_FLAG_COMPRESSED |
++			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+ 	}, {
+ 		.pixfmt = V4L2_PIX_FMT_H264,
+ 		.min_buffers = 2,
+@@ -165,6 +190,18 @@ static const struct amvdec_format vdec_formats_g12a[] = {
+ 		.flags = V4L2_FMT_FLAG_COMPRESSED |
+ 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+ 	}, {
++		.pixfmt = V4L2_PIX_FMT_HEVC,
++		.min_buffers = 4,
++		.max_buffers = 24,
++		.max_width = 3840,
++		.max_height = 2160,
++		.vdec_ops = &vdec_hevc_ops,
++		.codec_ops = &codec_hevc_ops,
++		.firmware_path = "meson/vdec/g12a_hevc_mmu.bin",
++		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
++		.flags = V4L2_FMT_FLAG_COMPRESSED |
++			 V4L2_FMT_FLAG_DYN_RESOLUTION,
++	},{
+ 		.pixfmt = V4L2_PIX_FMT_H264,
+ 		.min_buffers = 2,
+ 		.max_buffers = 24,
+@@ -214,6 +251,18 @@ static const struct amvdec_format vdec_formats_sm1[] = {
+ 		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+ 		.flags = V4L2_FMT_FLAG_COMPRESSED |
+ 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
++	}, {
++		.pixfmt = V4L2_PIX_FMT_HEVC,
++		.min_buffers = 4,
++		.max_buffers = 24,
++		.max_width = 3840,
++		.max_height = 2160,
++		.vdec_ops = &vdec_hevc_ops,
++		.codec_ops = &codec_hevc_ops,
++		.firmware_path = "meson/vdec/sm1_hevc_mmu.bin",
++		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
++		.flags = V4L2_FMT_FLAG_COMPRESSED |
++			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+ 	}, {
+ 		.pixfmt = V4L2_PIX_FMT_H264,
+ 		.min_buffers = 2,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-meson-vdec-add-handling-to-HEVC-decoder-.patch b/patch/kernel/archive/meson64-6.10/general-meson-vdec-add-handling-to-HEVC-decoder-.patch
new file mode 100644
index 000000000000..0db5d1468064
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-meson-vdec-add-handling-to-HEVC-decoder-.patch
@@ -0,0 +1,157 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: benjamin545 <benjamin545@gmail.com>
+Date: Mon, 2 Aug 2021 15:18:40 -0400
+Subject: WIP: drivers: meson: vdec: add handling to HEVC decoder to show
+ frames when ready
+
+..rather than when no longer referenced
+
+the HEVC decode driver would not show the next frame until it was no longer referenced,
+this would cause a backup of frames that were ready to render but held up by one or more
+frames that were still referenced. The decoded picture buffer would fill up and stall
+playback as no new frames could be placed in the decoded picture buffer.
+---
+ drivers/staging/media/meson/vdec/codec_hevc.c | 52 ++++++----
+ 1 file changed, 34 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/staging/media/meson/vdec/codec_hevc.c b/drivers/staging/media/meson/vdec/codec_hevc.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/codec_hevc.c
++++ b/drivers/staging/media/meson/vdec/codec_hevc.c
+@@ -223,6 +223,7 @@ struct hevc_frame {
+ 	u32 poc;
+ 
+ 	int referenced;
++	int show;
+ 	u32 num_reorder_pic;
+ 
+ 	u32 cur_slice_idx;
+@@ -448,9 +449,11 @@ static void codec_hevc_update_referenced(struct codec_hevc *hevc)
+ 			       ((1 << (RPS_USED_BIT - 1)) - 1);
+ 			if (param->p.CUR_RPS[i] & (1 << (RPS_USED_BIT - 1))) {
+ 				poc_tmp = curr_poc -
+-					  ((1 << (RPS_USED_BIT - 1)) - delt);
+-			} else
++				      ((1 << (RPS_USED_BIT - 1)) - delt);
++			} else {
+ 				poc_tmp = curr_poc + delt;
++			}
++
+ 			if (poc_tmp == frame->poc) {
+ 				is_referenced = 1;
+ 				break;
+@@ -462,13 +465,13 @@ static void codec_hevc_update_referenced(struct codec_hevc *hevc)
+ }
+ 
+ static struct hevc_frame *
+-codec_hevc_get_lowest_poc_frame(struct codec_hevc *hevc)
++codec_hevc_get_next_ready_frame(struct codec_hevc *hevc)
+ {
+ 	struct hevc_frame *tmp, *ret = NULL;
+ 	u32 poc = INT_MAX;
+ 
+ 	list_for_each_entry(tmp, &hevc->ref_frames_list, list) {
+-		if (tmp->poc < poc) {
++		if ((tmp->poc < poc) && tmp->show) {
+ 			ret = tmp;
+ 			poc = tmp->poc;
+ 		}
+@@ -478,28 +481,35 @@ codec_hevc_get_lowest_poc_frame(struct codec_hevc *hevc)
+ }
+ 
+ /* Try to output as many frames as possible */
+-static void codec_hevc_output_frames(struct amvdec_session *sess)
++static void codec_hevc_show_frames(struct amvdec_session *sess)
+ {
+-	struct hevc_frame *tmp;
++	struct hevc_frame *tmp, *n;
+ 	struct codec_hevc *hevc = sess->priv;
+ 
+-	while ((tmp = codec_hevc_get_lowest_poc_frame(hevc))) {
++	while ((tmp = codec_hevc_get_next_ready_frame(hevc))) {
+ 		if (hevc->curr_poc &&
+-		    (tmp->referenced ||
+-		     tmp->num_reorder_pic >= hevc->frames_num))
++		   (hevc->frames_num <= tmp->num_reorder_pic))
+ 			break;
+ 
+ 		dev_dbg(sess->core->dev, "DONE frame poc %u; vbuf %u\n",
+ 			tmp->poc, tmp->vbuf->vb2_buf.index);
+ 		amvdec_dst_buf_done_offset(sess, tmp->vbuf, tmp->offset,
+ 					   V4L2_FIELD_NONE, false);
++
++		tmp->show = 0;
++		hevc->frames_num--;
++	}
++
++	/* clean output frame buffer */
++	list_for_each_entry_safe(tmp, n, &hevc->ref_frames_list, list) {
++		if (tmp->referenced || tmp->show)
++			continue;
++
+ 		list_del(&tmp->list);
+ 		kfree(tmp);
+-		hevc->frames_num--;
+ 	}
+ }
+ 
+-
+ static int
+ codec_hevc_setup_workspace(struct amvdec_session *sess,
+ 			   struct codec_hevc *hevc)
+@@ -650,14 +660,17 @@ static int codec_hevc_start(struct amvdec_session *sess)
+ static void codec_hevc_flush_output(struct amvdec_session *sess)
+ {
+ 	struct codec_hevc *hevc = sess->priv;
+-	struct hevc_frame *tmp;
++	struct hevc_frame *tmp, *n;
+ 
+-	while (!list_empty(&hevc->ref_frames_list)) {
+-		tmp = codec_hevc_get_lowest_poc_frame(hevc);
++	while ((tmp = codec_hevc_get_next_ready_frame(hevc))) {
+ 		amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE);
++		tmp->show = 0;
++		hevc->frames_num--;
++	}
++
++	list_for_each_entry_safe(tmp, n, &hevc->ref_frames_list, list) {
+ 		list_del(&tmp->list);
+ 		kfree(tmp);
+-		hevc->frames_num--;
+ 	}
+ }
+ 
+@@ -719,6 +732,7 @@ codec_hevc_prepare_new_frame(struct amvdec_session *sess)
+ 
+ 	new_frame->vbuf = vbuf;
+ 	new_frame->referenced = 1;
++	new_frame->show = 1;
+ 	new_frame->poc = hevc->curr_poc;
+ 	new_frame->cur_slice_type = params->p.slice_type;
+ 	new_frame->num_reorder_pic = params->p.sps_num_reorder_pics_0;
+@@ -1267,7 +1281,7 @@ static int codec_hevc_process_segment(struct amvdec_session *sess)
+ 	/* First slice: new frame */
+ 	if (slice_segment_address == 0) {
+ 		codec_hevc_update_referenced(hevc);
+-		codec_hevc_output_frames(sess);
++		codec_hevc_show_frames(sess);
+ 
+ 		hevc->cur_frame = codec_hevc_prepare_new_frame(sess);
+ 		if (!hevc->cur_frame)
+@@ -1370,9 +1384,11 @@ static void codec_hevc_fetch_rpm(struct amvdec_session *sess)
+ 	u16 *rpm_vaddr = hevc->workspace_vaddr + RPM_OFFSET;
+ 	int i, j;
+ 
+-	for (i = 0; i < RPM_SIZE; i += 4)
++	for (i = 0; i < RPM_SIZE; i += 4) {
+ 		for (j = 0; j < 4; j++)
+-			hevc->rpm_param.l.data[i + j] = rpm_vaddr[i + 3 - j];
++			hevc->rpm_param.l.data[i + j] =
++				rpm_vaddr[i + 3 - j];
++	}
+ }
+ 
+ static void codec_hevc_resume(struct amvdec_session *sess)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-meson-vdec-check-if-parser-has-really-parser.patch b/patch/kernel/archive/meson64-6.10/general-meson-vdec-check-if-parser-has-really-parser.patch
new file mode 100644
index 000000000000..068d55ce7189
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-meson-vdec-check-if-parser-has-really-parser.patch
@@ -0,0 +1,51 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Mon, 22 Nov 2021 09:15:21 +0000
+Subject: WIP: drivers: meson: vdec: check if parser has really parser before
+ marking input buffer as error
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/staging/media/meson/vdec/esparser.c | 14 +++++++---
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/esparser.c
++++ b/drivers/staging/media/meson/vdec/esparser.c
+@@ -299,6 +299,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
+ 	u32 num_dst_bufs = 0;
+ 	u32 offset;
+ 	u32 pad_size;
++	u32 wp, wp2;
+ 
+ 	/*
+ 	 * When max ref frame is held by VP9, this should be -= 3 to prevent a
+@@ -352,15 +353,20 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
+ 	}
+ 
+ 	pad_size = esparser_pad_start_code(core, vb, payload_size);
++	wp = amvdec_read_parser(core, PARSER_VIDEO_WP);
+ 	ret = esparser_write_data(core, phy, payload_size + pad_size);
++	wp2 = amvdec_read_parser(core, PARSER_VIDEO_WP);
+ 
+ 	if (ret <= 0) {
+-		dev_warn(core->dev, "esparser: input parsing error\n");
+-		amvdec_remove_ts(sess, vb->timestamp);
+-		v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
+ 		amvdec_write_parser(core, PARSER_FETCH_CMD, 0);
+ 
+-		return 0;
++		if (ret < 0 || wp2 == wp) {
++			dev_err(core->dev, "esparser: input parsing error ret %d (%x <=> %x)\n", ret, wp, wp2);
++			amvdec_remove_ts(sess, vb->timestamp);
++			v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
++
++			return 0;
++		}
+ 	}
+ 
+ 	atomic_inc(&sess->esparser_queued_bufs);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-meson-vdec-improve-mmu-and-fbc-handling-.patch b/patch/kernel/archive/meson64-6.10/general-meson-vdec-improve-mmu-and-fbc-handling-.patch
new file mode 100644
index 000000000000..916ce5967629
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-meson-vdec-improve-mmu-and-fbc-handling-.patch
@@ -0,0 +1,587 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: benjamin545 <benjamin545@gmail.com>
+Date: Thu, 15 Jul 2021 16:32:39 -0400
+Subject: WIP: drivers: meson: vdec: improve mmu and fbc handling and add 10
+ bit handling
+
+Unknown patch. From LibreELEC?
+---
+ drivers/staging/media/meson/vdec/codec_h264.c        |   3 +-
+ drivers/staging/media/meson/vdec/codec_hevc_common.c | 164 ++++++----
+ drivers/staging/media/meson/vdec/codec_hevc_common.h |   3 +-
+ drivers/staging/media/meson/vdec/codec_vp9.c         |  36 +-
+ drivers/staging/media/meson/vdec/esparser.c          |   1 +
+ drivers/staging/media/meson/vdec/vdec.h              |   1 +
+ drivers/staging/media/meson/vdec/vdec_helpers.c      |  46 ++-
+ drivers/staging/media/meson/vdec/vdec_helpers.h      |  10 +-
+ 8 files changed, 163 insertions(+), 101 deletions(-)
+
+diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/codec_h264.c
++++ b/drivers/staging/media/meson/vdec/codec_h264.c
+@@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
+ 		frame_width, frame_height, crop_right, crop_bottom);
+ 
+ 	codec_h264_set_par(sess);
+-	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
++	amvdec_src_change(sess, frame_width, frame_height,
++			  h264->max_refs + 5, 8);
+ }
+ 
+ /*
+diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
++++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
+@@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
+ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
+ {
+ 	struct amvdec_core *core = sess->core;
+-	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
+-	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
++	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
++					 sess->pixfmt_cap, is_10bit);
++	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
++					       is_10bit, use_mmu);
++	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
+ 
+ 	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
+ 		/* Enable 2-plane reference read mode */
+@@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
+ 		return;
+ 	}
+ 
++	/* enable mem saving mode for 8-bit */
++	if (!is_10bit)
++		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
++	else
++		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
++
+ 	if (codec_hevc_use_mmu(core->platform->revision,
+ 			       sess->pixfmt_cap, is_10bit))
+ 		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
++	else if (!is_10bit)
++		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
+ 	else
+ 		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
+ 
+@@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
+ 
+ 		idx = vb->index;
+ 
+-		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
++		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
+ 			buf_y_paddr = comm->fbc_buffer_paddr[idx];
+ 		else
+ 			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
+@@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
+ {
+ 	struct amvdec_core *core = sess->core;
+ 	struct v4l2_m2m_buffer *buf;
+-	u32 revision = core->platform->revision;
+ 	u32 pixfmt_cap = sess->pixfmt_cap;
++    const u32 revision = core->platform->revision;
+ 	int i;
+ 
+ 	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
+@@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
+ 		dma_addr_t buf_uv_paddr = 0;
+ 		u32 idx = vb->index;
+ 
+-		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
+-			buf_y_paddr = comm->mmu_header_paddr[idx];
+-		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
+-			buf_y_paddr = comm->fbc_buffer_paddr[idx];
+-		else
+-			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
++		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
++			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
++				buf_y_paddr = comm->mmu_header_paddr[idx];
++			else
++				buf_y_paddr = comm->fbc_buffer_paddr[idx];
++		} else {
++ 			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
++		}
+ 
+ 		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
+ 				 buf_y_paddr >> 5);
+@@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
+ 		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
+ }
+ 
+-void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
++void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
+ 				 struct codec_hevc_common *comm)
+ {
+ 	struct device *dev = sess->core->dev;
+-	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
+ 	int i;
+ 
+ 	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
+-		if (comm->fbc_buffer_vaddr[i]) {
+-			dma_free_coherent(dev, am21_size,
+-					  comm->fbc_buffer_vaddr[i],
+-					  comm->fbc_buffer_paddr[i]);
+-			comm->fbc_buffer_vaddr[i] = NULL;
++		if (comm->mmu_header_vaddr[i]) {
++			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
++					  comm->mmu_header_vaddr[i],
++					  comm->mmu_header_paddr[i]);
++			comm->mmu_header_vaddr[i] = NULL;
+ 		}
+ 	}
+ }
+-EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
++EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
+ 
+-static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
++static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
+ 					struct codec_hevc_common *comm)
+ {
+ 	struct device *dev = sess->core->dev;
+ 	struct v4l2_m2m_buffer *buf;
+-	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
+ 
+ 	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
+ 		u32 idx = buf->vb.vb2_buf.index;
+ 		dma_addr_t paddr;
+-		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
+-						 GFP_KERNEL);
++		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
++						 &paddr, GFP_KERNEL);
+ 		if (!vaddr) {
+-			codec_hevc_free_fbc_buffers(sess, comm);
++			codec_hevc_free_mmu_headers(sess, comm);
+ 			return -ENOMEM;
+ 		}
+ 
+-		comm->fbc_buffer_vaddr[idx] = vaddr;
+-		comm->fbc_buffer_paddr[idx] = paddr;
++		comm->mmu_header_vaddr[idx] = vaddr;
++		comm->mmu_header_paddr[idx] = paddr;
+ 	}
+ 
+ 	return 0;
+ }
+ 
+-void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
++void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
+ 				 struct codec_hevc_common *comm)
+ {
+ 	struct device *dev = sess->core->dev;
++	u32 use_mmu;
++	u32 am21_size;
+ 	int i;
+ 
++	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
++					 sess->pixfmt_cap,
++					 sess->bitdepth == 10 ? 1 : 0);
++
++	am21_size = amvdec_amfbc_size(sess->width, sess->height,
++					  sess->bitdepth == 10 ? 1 : 0,  use_mmu);
++
+ 	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
+-		if (comm->mmu_header_vaddr[i]) {
+-			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
+-					  comm->mmu_header_vaddr[i],
+-					  comm->mmu_header_paddr[i]);
+-			comm->mmu_header_vaddr[i] = NULL;
++		if (comm->fbc_buffer_vaddr[i]) {
++			dma_free_coherent(dev, am21_size,
++					  comm->fbc_buffer_vaddr[i],
++					  comm->fbc_buffer_paddr[i]);
++			comm->fbc_buffer_vaddr[i] = NULL;
+ 		}
+ 	}
+ 
+@@ -213,33 +233,49 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
+ 				  comm->mmu_map_paddr);
+ 		comm->mmu_map_vaddr = NULL;
+ 	}
++
++    codec_hevc_free_mmu_headers(sess, comm);
+ }
+-EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
++EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
+ 
+-static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
++static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
+ 					struct codec_hevc_common *comm)
+ {
+ 	struct device *dev = sess->core->dev;
+ 	struct v4l2_m2m_buffer *buf;
++	u32 use_mmu;
++	u32 am21_size;
++	const u32 revision = sess->core->platform->revision;
++	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
++	int ret;
+ 
+-	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
+-						 &comm->mmu_map_paddr,
+-						 GFP_KERNEL);
+-	if (!comm->mmu_map_vaddr)
+-		return -ENOMEM;
++	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
++					 is_10bit);
++
++	am21_size = amvdec_amfbc_size(sess->width, sess->height,
++					  is_10bit, use_mmu);
+ 
+ 	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
+ 		u32 idx = buf->vb.vb2_buf.index;
+ 		dma_addr_t paddr;
+-		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
+-						 &paddr, GFP_KERNEL);
++		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
++						 GFP_KERNEL);
+ 		if (!vaddr) {
+-			codec_hevc_free_mmu_headers(sess, comm);
++			codec_hevc_free_fbc_buffers(sess, comm);
+ 			return -ENOMEM;
+ 		}
+ 
+-		comm->mmu_header_vaddr[idx] = vaddr;
+-		comm->mmu_header_paddr[idx] = paddr;
++		comm->fbc_buffer_vaddr[idx] = vaddr;
++		comm->fbc_buffer_paddr[idx] = paddr;
++	}
++
++	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
++	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
++		ret = codec_hevc_alloc_mmu_headers(sess, comm);
++		if (ret) {
++			codec_hevc_free_fbc_buffers(sess, comm);
++			return ret;
++		}
+ 	}
+ 
+ 	return 0;
+@@ -250,21 +286,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
+ 			     int is_10bit)
+ {
+ 	struct amvdec_core *core = sess->core;
++    struct device *dev = core->dev;
+ 	int ret;
+ 
+-	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
+-		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
+-		if (ret)
+-			return ret;
++	if (codec_hevc_use_mmu(core->platform->revision,
++			       sess->pixfmt_cap, is_10bit)) {
++		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
++							 &comm->mmu_map_paddr,
++							 GFP_KERNEL);
++		if (!comm->mmu_map_vaddr)
++			return -ENOMEM;
+ 	}
+ 
+ 	if (codec_hevc_use_mmu(core->platform->revision,
+-			       sess->pixfmt_cap, is_10bit)) {
+-		ret = codec_hevc_alloc_mmu_headers(sess, comm);
+-		if (ret) {
+-			codec_hevc_free_fbc_buffers(sess, comm);
+-			return ret;
+-		}
++			       sess->pixfmt_cap, is_10bit) ||
++	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
++		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
++		if (ret)
++ 			return ret;
+ 	}
+ 
+ 	if (core->platform->revision == VDEC_REVISION_GXBB)
+@@ -278,19 +317,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
+ 
+ void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
+ 			     struct codec_hevc_common *comm,
+-			     struct vb2_buffer *vb)
++			     struct vb2_buffer *vb,
++			     u32 is_10bit)
+ {
+-	u32 size = amvdec_am21c_size(sess->width, sess->height);
+-	u32 nb_pages = size / PAGE_SIZE;
++	u32 use_mmu;
++	u32 size;
++	u32 nb_pages;
+ 	u32 *mmu_map = comm->mmu_map_vaddr;
+ 	u32 first_page;
+ 	u32 i;
+ 
+-	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
+-		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
+-	else
+-		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
++	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
++				    	 sess->pixfmt_cap, is_10bit);
++
++	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
++				         use_mmu);
+ 
++	nb_pages = size / PAGE_SIZE;
++	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
+ 	for (i = 0; i < nb_pages; ++i)
+ 		mmu_map[i] = first_page + i;
+ }
+diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
++++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
+@@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
+ 
+ void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
+ 			     struct codec_hevc_common *comm,
+-			     struct vb2_buffer *vb);
++			     struct vb2_buffer *vb,
++			     u32 is_10bit);
+ 
+ #endif
+diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/codec_vp9.c
++++ b/drivers/staging/media/meson/vdec/codec_vp9.c
+@@ -458,12 +458,6 @@ struct codec_vp9 {
+ 	struct list_head ref_frames_list;
+ 	u32 frames_num;
+ 
+-	/* In case of downsampling (decoding with FBC but outputting in NV12M),
+-	 * we need to allocate additional buffers for FBC.
+-	 */
+-	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
+-	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
+-
+ 	int ref_frame_map[REF_FRAMES];
+ 	int next_ref_frame_map[REF_FRAMES];
+ 	struct vp9_frame *frame_refs[REFS_PER_FRAME];
+@@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
+ 		buf_y_paddr =
+ 		       vb2_dma_contig_plane_dma_addr(vb, 0);
+ 
+-	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
+-		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
+-		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
+-		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
+-	}
++	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
++ 		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
+ 
+ 	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
+ 		buf_y_paddr =
+@@ -920,8 +911,12 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
+ 
+ 	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+ 			       vp9->is_10bit)) {
+-		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
+-				 vp9->common.mmu_header_paddr[vb->index]);
++		dma_addr_t header_adr;
++		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
++			header_adr = vp9->common.mmu_header_paddr[vb->index];
++		else
++			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
++		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
+ 		/* use HEVC_CM_HEADER_START_ADDR */
+ 		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
+ 	}
+@@ -1148,9 +1143,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
+ {
+ 	struct amvdec_core *core = sess->core;
+ 	u32 scale = 0;
++	u32 use_mmu;
+ 	u32 sz;
+ 	int i;
+ 
++	use_mmu = codec_hevc_use_mmu(core->platform->revision,
++					 sess->pixfmt_cap, vp9->is_10bit);
++
+ 	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
+ 	codec_vp9_set_refs(sess, vp9);
+ 	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+@@ -1166,8 +1165,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
+ 		    vp9->frame_refs[i]->height != vp9->height)
+ 			scale = 1;
+ 
+-		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
+-					    vp9->frame_refs[i]->height);
++		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
++					    vp9->frame_refs[i]->height,
++					    vp9->is_10bit, use_mmu);
+ 
+ 		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
+ 				 vp9->frame_refs[i]->width);
+@@ -1283,7 +1283,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
+ 	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+ 			       vp9->is_10bit))
+ 		codec_hevc_fill_mmu_map(sess, &vp9->common,
+-					&vp9->cur_frame->vbuf->vb2_buf);
++					&vp9->cur_frame->vbuf->vb2_buf,
++					vp9->is_10bit);
+ 
+ 	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
+ 
+@@ -2130,7 +2131,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
+ 
+ 	codec_vp9_fetch_rpm(sess);
+ 	if (codec_vp9_process_rpm(vp9)) {
+-		amvdec_src_change(sess, vp9->width, vp9->height, 16);
++		amvdec_src_change(sess, vp9->width, vp9->height, 16,
++				  vp9->is_10bit ? 10 : 8);
+ 
+ 		/* No frame is actually processed */
+ 		vp9->cur_frame = NULL;
+diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/esparser.c
++++ b/drivers/staging/media/meson/vdec/esparser.c
+@@ -319,6 +319,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
+ 		if (esparser_vififo_get_free_space(sess) < payload_size ||
+ 		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
+ 			return -EAGAIN;
++
+ 	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
+ 		return -EAGAIN;
+ 	}
+diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/vdec.h
++++ b/drivers/staging/media/meson/vdec/vdec.h
+@@ -243,6 +243,7 @@ struct amvdec_session {
+ 	u32 width;
+ 	u32 height;
+ 	u32 colorspace;
++	u32 bitdepth;
+ 	u8 ycbcr_enc;
+ 	u8 quantization;
+ 	u8 xfer_func;
+diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/vdec_helpers.c
++++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
+@@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
+ }
+ EXPORT_SYMBOL_GPL(amvdec_write_parser);
+ 
+-/* 4 KiB per 64x32 block */
+-u32 amvdec_am21c_body_size(u32 width, u32 height)
++/* AMFBC body is made out of 64x32 blocks with varying block size */
++u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
+ {
+ 	u32 width_64 = ALIGN(width, 64) / 64;
+ 	u32 height_32 = ALIGN(height, 32) / 32;
++	u32 blk_size = 4096;
+ 
+-	return SZ_4K * width_64 * height_32;
++	if (!is_10bit) {
++		if (use_mmu)
++			blk_size = 3200;
++		else
++			blk_size = 3072;
++	}
++
++	return blk_size * width_64 * height_32;
+ }
+-EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
++EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
+ 
+ /* 32 bytes per 128x64 block */
+-u32 amvdec_am21c_head_size(u32 width, u32 height)
++u32 amvdec_amfbc_head_size(u32 width, u32 height)
+ {
+ 	u32 width_128 = ALIGN(width, 128) / 128;
+ 	u32 height_64 = ALIGN(height, 64) / 64;
+ 
+ 	return 32 * width_128 * height_64;
+ }
+-EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
++EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
+ 
+-u32 amvdec_am21c_size(u32 width, u32 height)
++u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
+ {
+-	return ALIGN(amvdec_am21c_body_size(width, height) +
+-		     amvdec_am21c_head_size(width, height), SZ_64K);
++	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
++		     amvdec_amfbc_head_size(width, height), SZ_64K);
+ }
+-EXPORT_SYMBOL_GPL(amvdec_am21c_size);
++EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
+ 
+ static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
+ {
+@@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
+ EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
+ 
+ void amvdec_src_change(struct amvdec_session *sess, u32 width,
+-		       u32 height, u32 dpb_size)
++		       u32 height, u32 dpb_size, u32 bitdepth)
+ {
+ 	static const struct v4l2_event ev = {
+ 		.type = V4L2_EVENT_SOURCE_CHANGE,
+@@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
+ 
+ 	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
+ 
++	sess->bitdepth = bitdepth;
++
+ 	/*
+ 	 * Check if the capture queue is already configured well for our
+-	 * usecase. If so, keep decoding with it and do not send the event
++	 * usecase. If so, keep decoding with it.
+ 	 */
+ 	if (sess->streamon_cap &&
+ 	    sess->width == width &&
+ 	    sess->height == height &&
+ 	    dpb_size <= sess->num_dst_bufs) {
+ 		sess->fmt_out->codec_ops->resume(sess);
+-		return;
+-	}
++	} else {
++		sess->status = STATUS_NEEDS_RESUME;
++		sess->changed_format = 0;
++ 	}
+ 
+-	sess->changed_format = 0;
+ 	sess->width = width;
+ 	sess->height = height;
+-	sess->status = STATUS_NEEDS_RESUME;
+ 
+-	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
+-		width, height, dpb_size);
++	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
++		width, height, dpb_size, bitdepth);
+ 	v4l2_event_queue_fh(&sess->fh, &ev);
+ }
+ EXPORT_SYMBOL_GPL(amvdec_src_change);
+diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/vdec_helpers.h
++++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
+@@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
+ u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
+ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
+ 
+-u32 amvdec_am21c_body_size(u32 width, u32 height);
+-u32 amvdec_am21c_head_size(u32 width, u32 height);
+-u32 amvdec_am21c_size(u32 width, u32 height);
++/* Helpers for the Amlogic compressed framebuffer format */
++u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
++u32 amvdec_amfbc_head_size(u32 width, u32 height);
++u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
+ 
+ /**
+  * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
+@@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
+  * @width: picture width detected by the hardware
+  * @height: picture height detected by the hardware
+  * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
++ * @bitdepth: Bit depth (usually 10 or 8) of the coded content
+  */
+ void amvdec_src_change(struct amvdec_session *sess, u32 width,
+-		       u32 height, u32 dpb_size);
++		       u32 height, u32 dpb_size, u32 bitdepth);
+ 
+ /**
+  * amvdec_abort() - Abort the current decoding session
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-meson64-overlays.patch b/patch/kernel/archive/meson64-6.10/general-meson64-overlays.patch
new file mode 100644
index 000000000000..2e10642b037c
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-meson64-overlays.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Zhang Ning <832666+zhangn1985@users.noreply.github.com>
+Date: Thu, 19 Sep 2019 16:20:31 +0800
+Subject: general: meson64 overlays
+
+Signed-off-by: Zhang Ning <832666+zhangn1985@users.noreply.github.com>
+---
+ scripts/Makefile.lib | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 111111111111..222222222222 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -93,6 +93,9 @@ base-dtb-y := $(filter %.dtb, $(call real-search, $(multi-dtb-y), .dtb, -dtbs))
+ 
+ always-y			+= $(dtb-y)
+ 
++# Overlay targets
++extra-y                                += $(dtbo-y) $(scr-y) $(dtbotxt-y)
++
+ # Add subdir path
+ 
+ ifneq ($(obj),.)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-si2168-fix-cmd-timeout.patch b/patch/kernel/archive/meson64-6.10/general-si2168-fix-cmd-timeout.patch
new file mode 100644
index 000000000000..5712b3ac8e64
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-si2168-fix-cmd-timeout.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Koumes <koumes@centrum.cz>
+Date: Sat, 1 Jun 2019 21:20:26 +0000
+Subject: si2168: fix cmd timeout
+
+Some demuxer si2168 commands may take 130-140 ms.
+(DVB-T/T2 tuner MyGica T230C v2).
+Details: https://github.com/CoreELEC/CoreELEC/pull/208
+---
+ drivers/media/dvb-frontends/si2168.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/dvb-frontends/si2168.c b/drivers/media/dvb-frontends/si2168.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/dvb-frontends/si2168.c
++++ b/drivers/media/dvb-frontends/si2168.c
+@@ -40,7 +40,7 @@ static int si2168_cmd_execute(struct i2c_client *client, struct si2168_cmd *cmd)
+ 
+ 	if (cmd->rlen) {
+ 		/* wait cmd execution terminate */
+-		#define TIMEOUT 70
++		#define TIMEOUT 200
+ 		timeout = jiffies + msecs_to_jiffies(TIMEOUT);
+ 		while (!time_after(jiffies, timeout)) {
+ 			ret = i2c_master_recv(client, cmd->args, cmd->rlen);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-socinfo-sm-1-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-1-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch
new file mode 100644
index 000000000000..67d3d3c7be90
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-1-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch
@@ -0,0 +1,30 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Tue, 4 Jun 2024 05:07:52 +0000
+Subject: soc: amlogic: meson-gx-socinfo: Add S905L ID
+
+Add the S905L SoC ID observed in several P271 boards:
+
+kernel: soc soc0: Amlogic Meson GXLX (S905L) Revision 26:a (c1:2) Detected
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+---
+ drivers/soc/amlogic/meson-gx-socinfo.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c
+index 111111111111..222222222222 100644
+--- a/drivers/soc/amlogic/meson-gx-socinfo.c
++++ b/drivers/soc/amlogic/meson-gx-socinfo.c
+@@ -64,6 +64,7 @@ static const struct meson_gx_package_id {
+ 	{ "962E", 0x24, 0x20, 0xf0 },
+ 	{ "A113X", 0x25, 0x37, 0xff },
+ 	{ "A113D", 0x25, 0x22, 0xff },
++	{ "S905L", 0x26, 0, 0x0 },
+ 	{ "S905D2", 0x28, 0x10, 0xf0 },
+ 	{ "S905Y2", 0x28, 0x30, 0xf0 },
+ 	{ "S905X2", 0x28, 0x40, 0xf0 },
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-socinfo-sm-2-soc-amlogic-meson-gx-socinfo-add-new-A113X-SoC-id.patch b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-2-soc-amlogic-meson-gx-socinfo-add-new-A113X-SoC-id.patch
new file mode 100644
index 000000000000..23b809425d0c
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-2-soc-amlogic-meson-gx-socinfo-add-new-A113X-SoC-id.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Viacheslav Bocharov <adeep@lexina.in>
+Date: Tue, 4 Jun 2024 17:04:51 +0300
+Subject: soc: amlogic: meson-gx-socinfo: add new A113X SoC id
+
+Add new definition for Amlogix A113X SoC found in JetHub D1/D1+ devices:
+
+soc soc0: Amlogic Meson AXG (A113X) Revision 25:b (43:2) Detected
+
+Signed-off-by: Viacheslav Bocharov <adeep@lexina.in>
+---
+ drivers/soc/amlogic/meson-gx-socinfo.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c
+index 111111111111..222222222222 100644
+--- a/drivers/soc/amlogic/meson-gx-socinfo.c
++++ b/drivers/soc/amlogic/meson-gx-socinfo.c
+@@ -63,6 +63,7 @@ static const struct meson_gx_package_id {
+ 	{ "962X", 0x24, 0x10, 0xf0 },
+ 	{ "962E", 0x24, 0x20, 0xf0 },
+ 	{ "A113X", 0x25, 0x37, 0xff },
++	{ "A113X", 0x25, 0x43, 0xff },
+ 	{ "A113D", 0x25, 0x22, 0xff },
+ 	{ "S905L", 0x26, 0, 0x0 },
+ 	{ "S905D2", 0x28, 0x10, 0xf0 },
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-socinfo-sm-3-soc-amlogic-meson-gx-socinfo-move-common-code-to-hea.patch b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-3-soc-amlogic-meson-gx-socinfo-move-common-code-to-hea.patch
new file mode 100644
index 000000000000..25b9ece37c1e
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-3-soc-amlogic-meson-gx-socinfo-move-common-code-to-hea.patch
@@ -0,0 +1,339 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Viacheslav Bocharov <adeep@lexina.in>
+Date: Tue, 4 Jun 2024 17:18:08 +0300
+Subject: soc: amlogic: meson-gx-socinfo: move common code to header file
+
+Move common constants and inline functions from meson-gx-socinfo driver
+to header file. Create new structures for store meson64 cpu_id and chip_id.
+
+Signed-off-by: Viacheslav Bocharov <adeep@lexina.in>
+---
+ drivers/soc/amlogic/meson-gx-socinfo-internal.h | 122 ++++++++
+ drivers/soc/amlogic/meson-gx-socinfo.c          | 140 +---------
+ 2 files changed, 137 insertions(+), 125 deletions(-)
+
+diff --git a/drivers/soc/amlogic/meson-gx-socinfo-internal.h b/drivers/soc/amlogic/meson-gx-socinfo-internal.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/soc/amlogic/meson-gx-socinfo-internal.h
+@@ -0,0 +1,122 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (c) 2017 BayLibre, SAS
++ * Copyright (c) 2024 JetHome
++ * Author: Neil Armstrong <neil.armstrong@linaro.org>
++ * Author: Viacheslav Bocharov <adeep@lexina.in>
++ *
++ */
++
++#ifndef _MESON_GX_SOCINFO_INTERNAL_H_
++#define _MESON_GX_SOCINFO_INTERNAL_H_
++
++#include <linux/types.h>
++
++#define AO_SEC_SD_CFG8		0xe0
++#define AO_SEC_SOCINFO_OFFSET	AO_SEC_SD_CFG8
++
++union meson_cpu_id {
++	struct { // cpu_id v1
++		u32 layout_ver:4;
++		u32 reserved:4;
++		u32 chip_rev:8;
++		u32 pack_id:8;
++		u32 major_id:8;
++	} v1;
++	struct { // cpu_id v2
++		u32 major_id:8;
++		u32 chip_rev:8;
++		u32 pack_id:8;
++		u32 reserved:4;
++		u32 layout_ver:4;
++	} v2;
++	u32	raw;
++};
++
++struct meson_sm_chip_id {
++	u32 version;
++	union meson_cpu_id cpu_id;
++	u8 serial[12];
++};
++
++static const struct meson_gx_soc_id {
++	const char *name;
++	unsigned int id;
++} soc_ids[] = {
++	{ "GXBB", 0x1f },
++	{ "GXTVBB", 0x20 },
++	{ "GXL", 0x21 },
++	{ "GXM", 0x22 },
++	{ "TXL", 0x23 },
++	{ "TXLX", 0x24 },
++	{ "AXG", 0x25 },
++	{ "GXLX", 0x26 },
++	{ "TXHD", 0x27 },
++	{ "G12A", 0x28 },
++	{ "G12B", 0x29 },
++	{ "SM1", 0x2b },
++	{ "A1", 0x2c },
++};
++
++static const struct meson_gx_package_id {
++	const char *name;
++	unsigned int major_id;
++	unsigned int pack_id;
++	unsigned int pack_mask;
++} soc_packages[] = {
++	{ "S905", 0x1f, 0, 0x20 }, /* pack_id != 0x20 */
++	{ "S905H", 0x1f, 0x3, 0xf }, /* pack_id & 0xf == 0x3 */
++	{ "S905M", 0x1f, 0x20, 0xf0 }, /* pack_id == 0x20 */
++	{ "S905D", 0x21, 0, 0xf0 },
++	{ "S905X", 0x21, 0x80, 0xf0 },
++	{ "S905W", 0x21, 0xa0, 0xf0 },
++	{ "S905L", 0x21, 0xc0, 0xf0 },
++	{ "S905M2", 0x21, 0xe0, 0xf0 },
++	{ "S805X", 0x21, 0x30, 0xf0 },
++	{ "S805Y", 0x21, 0xb0, 0xf0 },
++	{ "S912", 0x22, 0, 0x0 }, /* Only S912 is known for GXM */
++	{ "962X", 0x24, 0x10, 0xf0 },
++	{ "962E", 0x24, 0x20, 0xf0 },
++	{ "A113X", 0x25, 0x37, 0xff },
++	{ "A113X", 0x25, 0x43, 0xff },
++	{ "A113D", 0x25, 0x22, 0xff },
++	{ "S905L", 0x26, 0, 0x0 },
++	{ "S905D2", 0x28, 0x10, 0xf0 },
++	{ "S905Y2", 0x28, 0x30, 0xf0 },
++	{ "S905X2", 0x28, 0x40, 0xf0 },
++	{ "A311D", 0x29, 0x10, 0xf0 },
++	{ "S922X", 0x29, 0x40, 0xf0 },
++	{ "S905D3", 0x2b, 0x4, 0xf5 },
++	{ "S905X3", 0x2b, 0x5, 0xf5 },
++	{ "S905X3", 0x2b, 0x10, 0x3f },
++	{ "S905D3", 0x2b, 0x30, 0x3f },
++	{ "A113L", 0x2c, 0x0, 0xf8 },
++};
++
++static inline const char *socinfo_v1_to_package_id(union meson_cpu_id socinfo)
++{
++	int i;
++
++	for (i = 0 ; i < ARRAY_SIZE(soc_packages) ; ++i) {
++		if (soc_packages[i].major_id == socinfo.v1.major_id &&
++		    soc_packages[i].pack_id ==
++				(socinfo.v1.pack_id & soc_packages[i].pack_mask))
++			return soc_packages[i].name;
++	}
++
++	return "Unknown";
++}
++
++static inline const char *socinfo_v1_to_soc_id(union meson_cpu_id socinfo)
++{
++	int i;
++
++	for (i = 0 ; i < ARRAY_SIZE(soc_ids) ; ++i) {
++		if (soc_ids[i].id == socinfo.v1.major_id)
++			return soc_ids[i].name;
++	}
++
++	return "Unknown";
++}
++
++#endif /* _MESON_GX_SOCINFO_INTERNAL_H_ */
+diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c
+index 111111111111..222222222222 100644
+--- a/drivers/soc/amlogic/meson-gx-socinfo.c
++++ b/drivers/soc/amlogic/meson-gx-socinfo.c
+@@ -1,8 +1,8 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (c) 2017 BayLibre, SAS
+  * Author: Neil Armstrong <narmstrong@baylibre.com>
+  *
+- * SPDX-License-Identifier: GPL-2.0+
+  */
+ 
+ #include <linux/io.h>
+@@ -12,120 +12,10 @@
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
+ #include <linux/sys_soc.h>
+-#include <linux/bitfield.h>
+ #include <linux/regmap.h>
+ #include <linux/mfd/syscon.h>
+ 
+-#define AO_SEC_SD_CFG8		0xe0
+-#define AO_SEC_SOCINFO_OFFSET	AO_SEC_SD_CFG8
+-
+-#define SOCINFO_MAJOR	GENMASK(31, 24)
+-#define SOCINFO_PACK	GENMASK(23, 16)
+-#define SOCINFO_MINOR	GENMASK(15, 8)
+-#define SOCINFO_MISC	GENMASK(7, 0)
+-
+-static const struct meson_gx_soc_id {
+-	const char *name;
+-	unsigned int id;
+-} soc_ids[] = {
+-	{ "GXBB", 0x1f },
+-	{ "GXTVBB", 0x20 },
+-	{ "GXL", 0x21 },
+-	{ "GXM", 0x22 },
+-	{ "TXL", 0x23 },
+-	{ "TXLX", 0x24 },
+-	{ "AXG", 0x25 },
+-	{ "GXLX", 0x26 },
+-	{ "TXHD", 0x27 },
+-	{ "G12A", 0x28 },
+-	{ "G12B", 0x29 },
+-	{ "SM1", 0x2b },
+-	{ "A1", 0x2c },
+-};
+-
+-static const struct meson_gx_package_id {
+-	const char *name;
+-	unsigned int major_id;
+-	unsigned int pack_id;
+-	unsigned int pack_mask;
+-} soc_packages[] = {
+-	{ "S905", 0x1f, 0, 0x20 }, /* pack_id != 0x20 */
+-	{ "S905H", 0x1f, 0x3, 0xf }, /* pack_id & 0xf == 0x3 */
+-	{ "S905M", 0x1f, 0x20, 0xf0 }, /* pack_id == 0x20 */
+-	{ "S905D", 0x21, 0, 0xf0 },
+-	{ "S905X", 0x21, 0x80, 0xf0 },
+-	{ "S905W", 0x21, 0xa0, 0xf0 },
+-	{ "S905L", 0x21, 0xc0, 0xf0 },
+-	{ "S905M2", 0x21, 0xe0, 0xf0 },
+-	{ "S805X", 0x21, 0x30, 0xf0 },
+-	{ "S805Y", 0x21, 0xb0, 0xf0 },
+-	{ "S912", 0x22, 0, 0x0 }, /* Only S912 is known for GXM */
+-	{ "962X", 0x24, 0x10, 0xf0 },
+-	{ "962E", 0x24, 0x20, 0xf0 },
+-	{ "A113X", 0x25, 0x37, 0xff },
+-	{ "A113X", 0x25, 0x43, 0xff },
+-	{ "A113D", 0x25, 0x22, 0xff },
+-	{ "S905L", 0x26, 0, 0x0 },
+-	{ "S905D2", 0x28, 0x10, 0xf0 },
+-	{ "S905Y2", 0x28, 0x30, 0xf0 },
+-	{ "S905X2", 0x28, 0x40, 0xf0 },
+-	{ "A311D", 0x29, 0x10, 0xf0 },
+-	{ "S922X", 0x29, 0x40, 0xf0 },
+-	{ "S905D3", 0x2b, 0x4, 0xf5 },
+-	{ "S905X3", 0x2b, 0x5, 0xf5 },
+-	{ "S905X3", 0x2b, 0x10, 0x3f },
+-	{ "S905D3", 0x2b, 0x30, 0x3f },
+-	{ "A113L", 0x2c, 0x0, 0xf8 },
+-};
+-
+-static inline unsigned int socinfo_to_major(u32 socinfo)
+-{
+-	return FIELD_GET(SOCINFO_MAJOR, socinfo);
+-}
+-
+-static inline unsigned int socinfo_to_minor(u32 socinfo)
+-{
+-	return FIELD_GET(SOCINFO_MINOR, socinfo);
+-}
+-
+-static inline unsigned int socinfo_to_pack(u32 socinfo)
+-{
+-	return FIELD_GET(SOCINFO_PACK, socinfo);
+-}
+-
+-static inline unsigned int socinfo_to_misc(u32 socinfo)
+-{
+-	return FIELD_GET(SOCINFO_MISC, socinfo);
+-}
+-
+-static const char *socinfo_to_package_id(u32 socinfo)
+-{
+-	unsigned int pack = socinfo_to_pack(socinfo);
+-	unsigned int major = socinfo_to_major(socinfo);
+-	int i;
+-
+-	for (i = 0 ; i < ARRAY_SIZE(soc_packages) ; ++i) {
+-		if (soc_packages[i].major_id == major &&
+-		    soc_packages[i].pack_id ==
+-				(pack & soc_packages[i].pack_mask))
+-			return soc_packages[i].name;
+-	}
+-
+-	return "Unknown";
+-}
+-
+-static const char *socinfo_to_soc_id(u32 socinfo)
+-{
+-	unsigned int id = socinfo_to_major(socinfo);
+-	int i;
+-
+-	for (i = 0 ; i < ARRAY_SIZE(soc_ids) ; ++i) {
+-		if (soc_ids[i].id == id)
+-			return soc_ids[i].name;
+-	}
+-
+-	return "Unknown";
+-}
++#include "meson-gx-socinfo-internal.h"
+ 
+ static int __init meson_gx_socinfo_init(void)
+ {
+@@ -133,7 +23,7 @@ static int __init meson_gx_socinfo_init(void)
+ 	struct soc_device *soc_dev;
+ 	struct device_node *np;
+ 	struct regmap *regmap;
+-	unsigned int socinfo;
++	union meson_cpu_id socinfo;
+ 	struct device *dev;
+ 	int ret;
+ 
+@@ -162,11 +52,11 @@ static int __init meson_gx_socinfo_init(void)
+ 		return -ENODEV;
+ 	}
+ 
+-	ret = regmap_read(regmap, AO_SEC_SOCINFO_OFFSET, &socinfo);
++	ret = regmap_read(regmap, AO_SEC_SOCINFO_OFFSET, &socinfo.raw);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	if (!socinfo) {
++	if (!socinfo.raw) {
+ 		pr_err("%s: invalid chipid value\n", __func__);
+ 		return -EINVAL;
+ 	}
+@@ -177,13 +67,13 @@ static int __init meson_gx_socinfo_init(void)
+ 
+ 	soc_dev_attr->family = "Amlogic Meson";
+ 	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%x:%x - %x:%x",
+-					   socinfo_to_major(socinfo),
+-					   socinfo_to_minor(socinfo),
+-					   socinfo_to_pack(socinfo),
+-					   socinfo_to_misc(socinfo));
++					   socinfo.v1.major_id,
++					   socinfo.v1.chip_rev,
++					   socinfo.v1.pack_id,
++					   (socinfo.v1.reserved<<4) + socinfo.v1.layout_ver);
+ 	soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%s (%s)",
+-					 socinfo_to_soc_id(socinfo),
+-					 socinfo_to_package_id(socinfo));
++					 socinfo_v1_to_soc_id(socinfo),
++					 socinfo_v1_to_package_id(socinfo));
+ 
+ 	soc_dev = soc_device_register(soc_dev_attr);
+ 	if (IS_ERR(soc_dev)) {
+@@ -196,10 +86,10 @@ static int __init meson_gx_socinfo_init(void)
+ 
+ 	dev_info(dev, "Amlogic Meson %s Revision %x:%x (%x:%x) Detected\n",
+ 			soc_dev_attr->soc_id,
+-			socinfo_to_major(socinfo),
+-			socinfo_to_minor(socinfo),
+-			socinfo_to_pack(socinfo),
+-			socinfo_to_misc(socinfo));
++			socinfo.v1.major_id,
++			socinfo.v1.chip_rev,
++			socinfo.v1.pack_id,
++			(socinfo.v1.reserved<<4) + socinfo.v1.layout_ver);
+ 
+ 	return 0;
+ }
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-socinfo-sm-4-soc-amlogic-meson-gx-socinfo-sm-Add-Amlogic-secure-m.patch b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-4-soc-amlogic-meson-gx-socinfo-sm-Add-Amlogic-secure-m.patch
new file mode 100644
index 000000000000..4948c0b8c79b
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-4-soc-amlogic-meson-gx-socinfo-sm-Add-Amlogic-secure-m.patch
@@ -0,0 +1,275 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Viacheslav Bocharov <adeep@lexina.in>
+Date: Wed, 21 Feb 2024 16:41:30 +0300
+Subject: soc: amlogic: meson-gx-socinfo-sm: Add Amlogic secure-monitor SoC
+ Information driver
+
+Amlogic SoCs have a SoC information secure-monitor call for SoC type,
+package type, revision information and chipid.
+This patchs adds support for secure-monitor call decoding and exposing
+with the SoC bus infrastructure in addition to the previous SoC
+Information driver.
+
+Signed-off-by: Viacheslav Bocharov <adeep@lexina.in>
+---
+ drivers/soc/amlogic/Kconfig                     |  10 +
+ drivers/soc/amlogic/Makefile                    |   1 +
+ drivers/soc/amlogic/meson-gx-socinfo-internal.h |  14 +-
+ drivers/soc/amlogic/meson-gx-socinfo-sm.c       | 190 ++++++++++
+ 4 files changed, 211 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/soc/amlogic/Kconfig
++++ b/drivers/soc/amlogic/Kconfig
+@@ -26,6 +26,16 @@ config MESON_GX_SOCINFO
+ 	  Say yes to support decoding of Amlogic Meson GX SoC family
+ 	  information about the type, package and version.
+ 
++config MESON_GX_SOCINFO_SM
++	bool "Amlogic Meson GX SoC Information driver via Secure Monitor"
++	depends on (ARM64 && ARCH_MESON || COMPILE_TEST) && MESON_SM=y
++	default ARCH_MESON && MESON_SM
++	select SOC_BUS
++	help
++	  Say yes to support decoding of Amlogic Meson GX SoC family
++	  information about the type, package and version via secure
++	  monitor call.
++
+ config MESON_MX_SOCINFO
+ 	bool "Amlogic Meson MX SoC Information driver"
+ 	depends on (ARM && ARCH_MESON) || COMPILE_TEST
+diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/soc/amlogic/Makefile
++++ b/drivers/soc/amlogic/Makefile
+@@ -2,4 +2,5 @@
+ obj-$(CONFIG_MESON_CANVAS) += meson-canvas.o
+ obj-$(CONFIG_MESON_CLK_MEASURE) += meson-clk-measure.o
+ obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
++obj-$(CONFIG_MESON_GX_SOCINFO_SM) += meson-gx-socinfo-sm.o
+ obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
+diff --git a/drivers/soc/amlogic/meson-gx-socinfo-internal.h b/drivers/soc/amlogic/meson-gx-socinfo-internal.h
+index 111111111111..222222222222 100644
+--- a/drivers/soc/amlogic/meson-gx-socinfo-internal.h
++++ b/drivers/soc/amlogic/meson-gx-socinfo-internal.h
+@@ -33,10 +33,16 @@ union meson_cpu_id {
+ 	u32	raw;
+ };
+ 
+-struct meson_sm_chip_id {
+-	u32 version;
+-	union meson_cpu_id cpu_id;
+-	u8 serial[12];
++union meson_sm_chip_id {
++	struct { // cpu_id v2
++		u32 version;
++		union meson_cpu_id cpu_id;
++		u8 serial[12];
++	} v2;
++	struct { // raw
++		u32 version;
++		u8 buf[12+sizeof(union meson_cpu_id)];
++	} raw;
+ };
+ 
+ static const struct meson_gx_soc_id {
+diff --git a/drivers/soc/amlogic/meson-gx-socinfo-sm.c b/drivers/soc/amlogic/meson-gx-socinfo-sm.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/soc/amlogic/meson-gx-socinfo-sm.c
+@@ -0,0 +1,190 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (c) 2017 BayLibre, SAS
++ * Copyright (c) 2024 JetHome
++ * Author: Neil Armstrong <neil.armstrong@linaro.org>
++ * Author: Viacheslav Bocharov <adeep@lexina.in>
++ *
++ */
++
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/sys_soc.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++
++#include <linux/firmware/meson/meson_sm.h>
++
++#include "meson-gx-socinfo-internal.h"
++
++static char *socinfo_get_chipid(struct device *dev, struct meson_sm_firmware *fw,
++			       union meson_cpu_id *socinfo)
++{
++	char *buf;
++	union meson_sm_chip_id *id_buf;
++	int ret;
++
++	id_buf = kzalloc(sizeof(union meson_sm_chip_id)+1, GFP_KERNEL);
++	if (!id_buf)
++		return NULL;
++
++	ret = meson_sm_call_read(fw, id_buf, sizeof(union meson_sm_chip_id), SM_GET_CHIP_ID,
++				 2, 0, 0, 0, 0);
++	if (ret < 0) {
++		kfree(id_buf);
++		return NULL;
++	}
++	dev_info(dev, "got sm version call %i\n", id_buf->raw.version);
++
++	if (id_buf->raw.version != 2) {
++
++		u8 tmp;
++		/**
++		 * Legacy 12-byte chip ID read out, transform data
++		 * to expected order format
++		 */
++		memmove((void *)&id_buf->v2.serial, (void *)&id_buf->raw.buf, 12);
++		for (int i = 0; i < 6; i++) {
++			tmp = id_buf->v2.serial[i];
++			id_buf->v2.serial[i] = id_buf->v2.serial[11 - i];
++			id_buf->v2.serial[11 - i] = tmp;
++		}
++		id_buf->v2.cpu_id.v2.major_id = socinfo->v1.major_id;
++		id_buf->v2.cpu_id.v2.pack_id = socinfo->v1.pack_id;
++		id_buf->v2.cpu_id.v2.chip_rev = socinfo->v1.chip_rev;
++		id_buf->v2.cpu_id.v2.reserved = socinfo->v1.reserved;
++		id_buf->v2.cpu_id.v2.layout_ver = socinfo->v1.layout_ver;
++	} else {
++		/**
++		 * rewrite socinfo from regmap with value from secure monitor call
++		 */
++		socinfo->v1.major_id = id_buf->v2.cpu_id.v2.major_id;
++		socinfo->v1.pack_id = id_buf->v2.cpu_id.v2.pack_id;
++		socinfo->v1.chip_rev = id_buf->v2.cpu_id.v2.chip_rev;
++		socinfo->v1.reserved = id_buf->v2.cpu_id.v2.reserved;
++		socinfo->v1.layout_ver = id_buf->v2.cpu_id.v2.layout_ver;
++	}
++
++	buf = devm_kasprintf(dev, GFP_KERNEL, "%4phN%12phN", &(id_buf->v2.cpu_id),
++			     &(id_buf->v2.serial));
++
++	kfree(id_buf);
++
++	return buf;
++}
++
++static int meson_gx_socinfo_sm_probe(struct platform_device *pdev)
++{
++	struct soc_device_attribute *soc_dev_attr;
++	struct soc_device *soc_dev;
++	struct device_node *sm_np;
++	struct meson_sm_firmware *fw;
++	struct regmap *regmap;
++	union meson_cpu_id socinfo;
++	struct device *dev;
++	int ret;
++
++	/* check if chip-id is available */
++	if (!of_property_read_bool(pdev->dev.of_node, "amlogic,has-chip-id"))
++		return -ENODEV;
++
++	/* node should be a syscon */
++	regmap = syscon_node_to_regmap(pdev->dev.of_node);
++	if (IS_ERR(regmap))
++		return dev_err_probe(&pdev->dev, PTR_ERR(regmap), "failed to get regmap\n");
++
++	sm_np = of_parse_phandle(pdev->dev.of_node, "secure-monitor", 0);
++	if (!sm_np) {
++		dev_err(&pdev->dev, "no secure-monitor node found\n");
++		return -EINVAL;
++	}
++
++	fw = meson_sm_get(sm_np);
++	of_node_put(sm_np);
++	if (!fw) {
++		dev_dbg(&pdev->dev, "secure-monitor device not ready, probe later\n");
++		return -EPROBE_DEFER;
++	}
++
++	ret = regmap_read(regmap, AO_SEC_SOCINFO_OFFSET, &socinfo.raw);
++	if (ret < 0)
++		return ret;
++
++	if (!socinfo.raw) {
++		dev_err(&pdev->dev, "invalid regmap chipid value\n");
++		return -EINVAL;
++	}
++
++	soc_dev_attr = devm_kzalloc(&pdev->dev, sizeof(*soc_dev_attr),
++				    GFP_KERNEL);
++	if (!soc_dev_attr)
++		return -ENOMEM;
++
++	soc_dev_attr->serial_number = socinfo_get_chipid(&pdev->dev, fw, &socinfo);
++
++	soc_dev_attr->family = "Amlogic Meson";
++	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%x:%x - %x:%x",
++					   socinfo.v1.major_id,
++					   socinfo.v1.chip_rev,
++					   socinfo.v1.pack_id,
++					   (socinfo.v1.reserved<<4) + socinfo.v1.layout_ver);
++	soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%s (%s)",
++					 socinfo_v1_to_soc_id(socinfo),
++					 socinfo_v1_to_package_id(socinfo));
++
++	soc_dev = soc_device_register(soc_dev_attr);
++
++
++	if (IS_ERR(soc_dev)) {
++		kfree(soc_dev_attr->revision);
++		kfree_const(soc_dev_attr->soc_id);
++		return PTR_ERR(soc_dev);
++	}
++
++	dev = soc_device_to_device(soc_dev);
++	platform_set_drvdata(pdev, soc_dev);
++
++	dev_info(dev, "Amlogic Meson %s Revision %x:%x (%x:%x) Detected (SM)\n",
++			soc_dev_attr->soc_id,
++			socinfo.v1.major_id,
++			socinfo.v1.chip_rev,
++			socinfo.v1.pack_id,
++			(socinfo.v1.reserved<<4) + socinfo.v1.layout_ver);
++
++	return PTR_ERR_OR_ZERO(dev);
++}
++
++
++static int meson_gx_socinfo_sm_remove(struct platform_device *pdev)
++{
++	struct soc_device *soc_dev = platform_get_drvdata(pdev);
++
++	soc_device_unregister(soc_dev);
++	return 0;
++}
++
++static const struct of_device_id meson_gx_socinfo_match[] = {
++	{ .compatible = "amlogic,meson-gx-ao-secure", },
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, meson_gx_socinfo_match);
++
++static struct platform_driver meson_gx_socinfo_driver = {
++	.probe = meson_gx_socinfo_sm_probe,
++	.remove	= meson_gx_socinfo_sm_remove,
++	.driver = {
++		.name = "meson-gx-socinfo-sm",
++		.of_match_table = meson_gx_socinfo_match,
++	},
++};
++
++
++module_platform_driver(meson_gx_socinfo_driver);
++
++MODULE_AUTHOR("Viacheslav Bocharov <adeep@lexina.in>");
++MODULE_DESCRIPTION("Amlogic Meson GX SOC SM driver");
++MODULE_LICENSE("GPL");
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-socinfo-sm-5-arm64-dts-meson-add-dts-links-to-secure-monitor-for-.patch b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-5-arm64-dts-meson-add-dts-links-to-secure-monitor-for-.patch
new file mode 100644
index 000000000000..e37d769475d8
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-5-arm64-dts-meson-add-dts-links-to-secure-monitor-for-.patch
@@ -0,0 +1,68 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Viacheslav Bocharov <adeep@lexina.in>
+Date: Thu, 14 Mar 2024 09:59:54 +0300
+Subject: arm64: dts: meson: add dts links to secure-monitor for soc driver in
+ a1, axg, gx, g12
+
+Add links to secure-monitor in soc driver section for A1, AXG, GX, G12
+Amlogic family for use with meson-socinfo-sm driver.
+
+Signed-off-by: Viacheslav Bocharov <adeep@lexina.in>
+---
+ arch/arm64/boot/dts/amlogic/meson-a1.dtsi         | 1 +
+ arch/arm64/boot/dts/amlogic/meson-axg.dtsi        | 1 +
+ arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 1 +
+ arch/arm64/boot/dts/amlogic/meson-gx.dtsi         | 1 +
+ 4 files changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+@@ -407,6 +407,7 @@ hwrng: rng@5118 {
+ 			sec_AO: ao-secure@5a20 {
+ 				compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ 				reg = <0x0 0x5a20 0x0 0x140>;
++				secure-monitor = <&sm>;
+ 				amlogic,has-chip-id;
+ 			};
+ 
+diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+@@ -1690,6 +1690,7 @@ mux {
+ 			sec_AO: ao-secure@140 {
+ 				compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ 				reg = <0x0 0x140 0x0 0x140>;
++				secure-monitor = <&sm>;
+ 				amlogic,has-chip-id;
+ 			};
+ 
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+@@ -2054,6 +2054,7 @@ cec_AO: cec@100 {
+ 			sec_AO: ao-secure@140 {
+ 				compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ 				reg = <0x0 0x140 0x0 0x140>;
++				secure-monitor = <&sm>;
+ 				amlogic,has-chip-id;
+ 			};
+ 
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+@@ -471,6 +471,7 @@ cec_AO: cec@100 {
+ 			sec_AO: ao-secure@140 {
+ 				compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ 				reg = <0x0 0x140 0x0 0x140>;
++				secure-monitor = <&sm>;
+ 				amlogic,has-chip-id;
+ 			};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-socinfo-sm-6-dt-bindings-arm-amlogic-amlogic-meson-gx-ao-secure-a.patch b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-6-dt-bindings-arm-amlogic-amlogic-meson-gx-ao-secure-a.patch
new file mode 100644
index 000000000000..0f5fa737b394
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-socinfo-sm-6-dt-bindings-arm-amlogic-amlogic-meson-gx-ao-secure-a.patch
@@ -0,0 +1,31 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Viacheslav Bocharov <adeep@lexina.in>
+Date: Tue, 4 Jun 2024 17:54:53 +0300
+Subject: dt-bindings: arm: amlogic: amlogic,meson-gx-ao-secure: add
+ secure-monitor property
+
+Add secure-monitor property to schema for meson-gx-socinfo-sm driver.
+
+Signed-off-by: Viacheslav Bocharov <adeep@lexina.in>
+---
+ Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
++++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
+@@ -32,6 +32,10 @@ properties:
+   reg:
+     maxItems: 1
+ 
++  secure-monitor:
++    description: phandle to the secure-monitor node
++    $ref: /schemas/types.yaml#/definitions/phandle
++
+   amlogic,has-chip-id:
+     description: |
+       A firmware register encodes the SoC type, package and revision
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-sound-soc-remove-mono-channel-as-it-curren.patch b/patch/kernel/archive/meson64-6.10/general-sound-soc-remove-mono-channel-as-it-curren.patch
new file mode 100644
index 000000000000..90f716b22e64
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-sound-soc-remove-mono-channel-as-it-curren.patch
@@ -0,0 +1,37 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ckkim <changkon12@gmail.com>
+Date: Thu, 20 Feb 2020 18:52:57 +0900
+Subject: ODROID-N2: sound/soc: remove mono channel as it currently doesn't
+ work hdmi output.
+
+Change-Id: I4d43b802815779687ade974f049f2b0517a411d1
+Signed-off-by: ckkim <changkon12@gmail.com>
+---
+ sound/soc/meson/axg-frddr.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c
+index 111111111111..222222222222 100644
+--- a/sound/soc/meson/axg-frddr.c
++++ b/sound/soc/meson/axg-frddr.c
+@@ -108,7 +108,7 @@ static struct snd_soc_dai_driver axg_frddr_dai_drv = {
+ 	.name = "FRDDR",
+ 	.playback = {
+ 		.stream_name	= "Playback",
+-		.channels_min	= 1,
++		.channels_min	= 2,
+ 		.channels_max	= AXG_FIFO_CH_MAX,
+ 		.rates		= SNDRV_PCM_RATE_CONTINUOUS,
+ 		.rate_min	= 5515,
+@@ -185,7 +185,7 @@ static struct snd_soc_dai_driver g12a_frddr_dai_drv = {
+ 	.name = "FRDDR",
+ 	.playback = {
+ 		.stream_name	= "Playback",
+-		.channels_min	= 1,
++		.channels_min	= 2,
+ 		.channels_max	= AXG_FIFO_CH_MAX,
+ 		.rates		= SNDRV_PCM_RATE_CONTINUOUS,
+ 		.rate_min	= 5515,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-spi-nor-add-support-for-XT25F128B.patch b/patch/kernel/archive/meson64-6.10/general-spi-nor-add-support-for-XT25F128B.patch
new file mode 100644
index 000000000000..a2622bd020fd
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-spi-nor-add-support-for-XT25F128B.patch
@@ -0,0 +1,96 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andreas Rammhold <andreas@rammhold.de>
+Date: Thu, 28 Jan 2021 09:43:36 +0000
+Subject: spi-nor: add support for XT25F128B & XT25Q64
+
+This adds support for the XT25F128B as found on the RockPi4b SBC.
+- Ricardo Pardini <ricardo@pardini.net> 23/jan/2023: add XT25Q64 SPI NOR chip
+  - found on HK's vendor tree: https://github.com/hardkernel/linux/blame/05e3dc1688758bd401e0f7cdd9809a3f9251f7c1/drivers/mtd/spi-nor/spi-nor.c#L1024-L1026
+- Ricardo pardini <ricardo@pardini.net> 14/jan/2024: convert to new SNOR_ID format
+  - I just followed the lead Paolo used in rockchip64's 6.7
+
+Signed-off-by: Andreas Rammhold <andreas@rammhold.de>
+Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
+
+This continues the efforts done in [1] & [2] that went stale. I've
+tested this patch on my RockPi4b which only has the xt25f128b (and not
+the xt25f32b as also propsed in [2]). I have tried to obtain a copy of
+the datasheets but was unable to find them. Not sure whre you would get
+them.
+
+While [1] was already for the new spi-nor layout it was missing the bits
+in the core.{c,h} files.
+
+[1]: https://patchwork.ozlabs.org/project/linux-mtd/patch/CAMgqO2y9MYDj6antOaWLBRKU8vGEwqCB-Y1TkXTSWsmsed+W6A@mail.gmail.com/
+[2]: https://patchwork.ozlabs.org/project/linux-mtd/patch/20200206171941.GA2398@makrotopia.org/
+---
+ drivers/mtd/spi-nor/Makefile |  1 +
+ drivers/mtd/spi-nor/core.c   |  1 +
+ drivers/mtd/spi-nor/core.h   |  1 +
+ drivers/mtd/spi-nor/xtx.c    | 19 ++++++++++
+ 4 files changed, 22 insertions(+)
+
+diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -15,6 +15,7 @@ spi-nor-objs			+= sst.o
+ spi-nor-objs			+= winbond.o
+ spi-nor-objs			+= xilinx.o
+ spi-nor-objs			+= xmc.o
++spi-nor-objs			+= xtx.o
+ spi-nor-$(CONFIG_DEBUG_FS)	+= debugfs.o
+ obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o
+ 
+diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
+index 111111111111..222222222222 100644
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -1988,6 +1988,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
+ 	&spi_nor_winbond,
+ 	&spi_nor_xilinx,
+ 	&spi_nor_xmc,
++	&spi_nor_xtx,
+ };
+ 
+ static const struct flash_info spi_nor_generic_flash = {
+diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
+index 111111111111..222222222222 100644
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -605,6 +605,7 @@ extern const struct spi_nor_manufacturer spi_nor_sst;
+ extern const struct spi_nor_manufacturer spi_nor_winbond;
+ extern const struct spi_nor_manufacturer spi_nor_xilinx;
+ extern const struct spi_nor_manufacturer spi_nor_xmc;
++extern const struct spi_nor_manufacturer spi_nor_xtx;
+ 
+ extern const struct attribute_group *spi_nor_sysfs_groups[];
+ 
+diff --git a/drivers/mtd/spi-nor/xtx.c b/drivers/mtd/spi-nor/xtx.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/mtd/spi-nor/xtx.c
+@@ -0,0 +1,19 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/mtd/spi-nor.h>
++
++#include "core.h"
++
++static const struct flash_info xtx_parts[] = {
++ /* XTX (Shenzhen Xin Tian Xia Tech) */
++ // { "xt25f128b", INFO(0x0b4018, 0, 64 * 1024, 256) },
++ { "xt25f128b", SNOR_ID(0x0b, 0x40, 0x18) },
++ // { "XT25Q64",   INFO(0x0b6017, 0, 64 * 1024, 128) },
++ { "XT25Q64",   SNOR_ID(0x0b, 0x60, 0x17) },
++};
++
++const struct spi_nor_manufacturer spi_nor_xtx = {
++ .name = "xtx",
++ .parts = xtx_parts,
++ .nparts = ARRAY_SIZE(xtx_parts),
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/general-usb-core-improve-handling-of-hubs-with-no-ports.patch b/patch/kernel/archive/meson64-6.10/general-usb-core-improve-handling-of-hubs-with-no-ports.patch
new file mode 100644
index 000000000000..9b12a4079d18
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/general-usb-core-improve-handling-of-hubs-with-no-ports.patch
@@ -0,0 +1,53 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <hkallweit1@gmail.com>
+Date: Wed, 23 Feb 2022 02:21:19 +0000
+Subject: usb: core: improve handling of hubs with no ports
+
+I get the "hub doesn't have any ports" error message on a system with
+Amlogic S905W SoC. Seems the SoC has internal USB 3.0 supports but
+is crippled with regard to USB 3.0 ports.
+Maybe we shouldn't consider this scenario an error. So let's change
+the message to info level, but otherwise keep the handling of the
+scenario as it is today. With the patch it looks like this on my
+system.
+
+dwc2 c9100000.usb: supply vusb_d not found, using dummy regulator
+dwc2 c9100000.usb: supply vusb_a not found, using dummy regulator
+dwc2 c9100000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
+xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
+xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
+xhci-hcd xhci-hcd.0.auto: hcc params 0x0228f664 hci version 0x100 quirks 0x0000000002010010
+xhci-hcd xhci-hcd.0.auto: irq 49, io mem 0xc9000000
+hub 1-0:1.0: USB hub found
+hub 1-0:1.0: 2 ports detected
+xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
+xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
+xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
+usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
+hub 2-0:1.0: USB hub found
+hub 2-0:1.0: hub has no ports, exiting
+
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+---
+ drivers/usb/core/hub.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
+index 111111111111..222222222222 100644
+--- a/drivers/usb/core/hub.c
++++ b/drivers/usb/core/hub.c
+@@ -1475,9 +1475,8 @@ static int hub_configure(struct usb_hub *hub,
+ 		ret = -ENODEV;
+ 		goto fail;
+ 	} else if (hub->descriptor->bNbrPorts == 0) {
+-		message = "hub doesn't have any ports!";
+-		ret = -ENODEV;
+-		goto fail;
++		dev_info(hub_dev, "hub has no ports, exiting\n");
++		return -ENODEV;
+ 	}
+ 
+ 	/*
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/hwmon-emc2305-fixups-for-driver.patch b/patch/kernel/archive/meson64-6.10/hwmon-emc2305-fixups-for-driver.patch
new file mode 100644
index 000000000000..14cbdd500365
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/hwmon-emc2305-fixups-for-driver.patch
@@ -0,0 +1,212 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Tue, 10 Oct 2023 18:54:22 -0400
+Subject: hwmon: emc2305: fixups for driver
+
+BPI-CM4 fan control
+
+hwmon: emc2305: fixups for driver
+The driver had a number of issues, checkpatch warnings/errors,
+and other limitations, so fix these up to make it usable.
+hwmon: emc2305: Change OF properties pwm-min & pwm-max to u8
+hwmon: emc2305: Add calls to initialize cooling maps
+https://github.com/raspberrypi/linux/commits/233096b8a9023f7e02960543c85447d46af81e81/drivers/hwmon/emc2305.c
+
+Tested-on: CM4-IO-BASE-B: https://www.waveshare.com/wiki/CM4-IO-BASE-B
+Signed-off-by: Phil Elwell <phil@raspberrypi.com>
+Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ drivers/hwmon/emc2305.c | 96 +++++++++-
+ 1 file changed, 88 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/hwmon/emc2305.c b/drivers/hwmon/emc2305.c
+index 111111111111..222222222222 100644
+--- a/drivers/hwmon/emc2305.c
++++ b/drivers/hwmon/emc2305.c
+@@ -12,12 +12,13 @@
+ #include <linux/platform_data/emc2305.h>
+ #include <linux/thermal.h>
+ 
++#define EMC2305_REG_FAN_STATUS		0x24
++#define EMC2305_REG_FAN_STALL_STATUS	0x25
+ #define EMC2305_REG_DRIVE_FAIL_STATUS	0x27
+ #define EMC2305_REG_VENDOR		0xfe
+ #define EMC2305_FAN_MAX			0xff
+ #define EMC2305_FAN_MIN			0x00
+ #define EMC2305_FAN_MAX_STATE		10
+-#define EMC2305_DEVICE			0x34
+ #define EMC2305_VENDOR			0x5d
+ #define EMC2305_REG_PRODUCT_ID		0xfd
+ #define EMC2305_TACH_REGS_UNUSE_BITS	3
+@@ -36,6 +37,7 @@
+ #define EMC2305_RPM_FACTOR		3932160
+ 
+ #define EMC2305_REG_FAN_DRIVE(n)	(0x30 + 0x10 * (n))
++#define EMC2305_REG_FAN_CFG(n)		(0x32 + 0x10 * (n))
+ #define EMC2305_REG_FAN_MIN_DRIVE(n)	(0x38 + 0x10 * (n))
+ #define EMC2305_REG_FAN_TACH(n)		(0x3e + 0x10 * (n))
+ 
+@@ -55,6 +57,16 @@ static const struct i2c_device_id emc2305_ids[] = {
+ };
+ MODULE_DEVICE_TABLE(i2c, emc2305_ids);
+ 
++static const struct of_device_id emc2305_dt_ids[] = {
++	{ .compatible = "smsc,emc2305" },
++	{ .compatible = "microchip,emc2305" },
++	{ .compatible = "microchip,emc2303" },
++	{ .compatible = "microchip,emc2302" },
++	{ .compatible = "microchip,emc2301" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, emc2305_dt_ids);
++
+ /**
+  * struct emc2305_cdev_data - device-specific cooling device state
+  * @cdev: cooling device
+@@ -100,6 +112,7 @@ struct emc2305_data {
+ 	u8 pwm_num;
+ 	bool pwm_separate;
+ 	u8 pwm_min[EMC2305_PWM_MAX];
++	u8 pwm_max;
+ 	struct emc2305_cdev_data cdev_data[EMC2305_PWM_MAX];
+ };
+ 
+@@ -272,7 +285,7 @@ static int emc2305_set_pwm(struct device *dev, long val, int channel)
+ 	struct i2c_client *client = data->client;
+ 	int ret;
+ 
+-	if (val < data->pwm_min[channel] || val > EMC2305_FAN_MAX)
++	if (val < data->pwm_min[channel] || val > data->pwm_max)
+ 		return -EINVAL;
+ 
+ 	ret = i2c_smbus_write_byte_data(client, EMC2305_REG_FAN_DRIVE(channel), val);
+@@ -283,6 +296,49 @@ static int emc2305_set_pwm(struct device *dev, long val, int channel)
+ 	return 0;
+ }
+ 
++static int emc2305_get_tz_of(struct device *dev)
++{
++	struct device_node *np = dev->of_node;
++	struct emc2305_data *data = dev_get_drvdata(dev);
++	int ret = 0;
++	u8 val;
++	int i;
++
++	/* OF parameters are optional - overwrite default setting
++	 * if some of them are provided.
++	 */
++
++	ret = of_property_read_u8(np, "emc2305,cooling-levels", &val);
++	if (!ret)
++		data->max_state = val;
++	else if (ret != -EINVAL)
++		return ret;
++
++	ret = of_property_read_u8(np, "emc2305,pwm-max", &val);
++	if (!ret)
++		data->pwm_max = val;
++	else if (ret != -EINVAL)
++		return ret;
++
++	ret = of_property_read_u8(np, "emc2305,pwm-min", &val);
++	if (!ret)
++		for (i = 0; i < EMC2305_PWM_MAX; i++)
++			data->pwm_min[i] = val;
++	else if (ret != -EINVAL)
++		return ret;
++
++	/* Not defined or 0 means one thermal zone over all cooling devices.
++	 * Otherwise - separated thermal zones for each PWM channel.
++	 */
++	ret = of_property_read_u8(np, "emc2305,pwm-channel", &val);
++	if (!ret)
++		data->pwm_separate = (val != 0);
++	else if (ret != -EINVAL)
++		return ret;
++
++	return 0;
++}
++
+ static int emc2305_set_single_tz(struct device *dev, int idx)
+ {
+ 	struct emc2305_data *data = dev_get_drvdata(dev);
+@@ -292,9 +348,17 @@ static int emc2305_set_single_tz(struct device *dev, int idx)
+ 	cdev_idx = (idx) ? idx - 1 : 0;
+ 	pwm = data->pwm_min[cdev_idx];
+ 
+-	data->cdev_data[cdev_idx].cdev =
+-		thermal_cooling_device_register(emc2305_fan_name[idx], data,
+-						&emc2305_cooling_ops);
++	if (dev->of_node)
++		data->cdev_data[cdev_idx].cdev =
++			devm_thermal_of_cooling_device_register(dev, dev->of_node,
++								emc2305_fan_name[idx],
++								data,
++								&emc2305_cooling_ops);
++	else
++		data->cdev_data[cdev_idx].cdev =
++			thermal_cooling_device_register(emc2305_fan_name[idx],
++							data,
++							&emc2305_cooling_ops);
+ 
+ 	if (IS_ERR(data->cdev_data[cdev_idx].cdev)) {
+ 		dev_err(dev, "Failed to register cooling device %s\n", emc2305_fan_name[idx]);
+@@ -347,9 +411,11 @@ static void emc2305_unset_tz(struct device *dev)
+ 	int i;
+ 
+ 	/* Unregister cooling device. */
+-	for (i = 0; i < EMC2305_PWM_MAX; i++)
+-		if (data->cdev_data[i].cdev)
+-			thermal_cooling_device_unregister(data->cdev_data[i].cdev);
++	if (!dev->of_node) {
++		for (i = 0; i < EMC2305_PWM_MAX; i++)
++			if (data->cdev_data[i].cdev)
++				thermal_cooling_device_unregister(data->cdev_data[i].cdev);
++	}
+ }
+ 
+ static umode_t
+@@ -571,11 +637,18 @@ static int emc2305_probe(struct i2c_client *client)
+ 		data->pwm_separate = pdata->pwm_separate;
+ 		for (i = 0; i < EMC2305_PWM_MAX; i++)
+ 			data->pwm_min[i] = pdata->pwm_min[i];
++		data->pwm_max = EMC2305_FAN_MAX;
+ 	} else {
+ 		data->max_state = EMC2305_FAN_MAX_STATE;
+ 		data->pwm_separate = false;
+ 		for (i = 0; i < EMC2305_PWM_MAX; i++)
+ 			data->pwm_min[i] = EMC2305_FAN_MIN;
++		data->pwm_max = EMC2305_FAN_MAX;
++		if (dev->of_node) {
++			ret = emc2305_get_tz_of(dev);
++			if (ret < 0)
++				return ret;
++		}
+ 	}
+ 
+ 	data->hwmon_dev = devm_hwmon_device_register_with_info(dev, "emc2305", data,
+@@ -596,6 +669,12 @@ static int emc2305_probe(struct i2c_client *client)
+ 			return ret;
+ 	}
+ 
++	/* Acknowledge any existing faults. Stops the device responding on the
++	 * SMBus alert address.
++	 */
++	i2c_smbus_read_byte_data(client, EMC2305_REG_FAN_STALL_STATUS);
++	i2c_smbus_read_byte_data(client, EMC2305_REG_FAN_STATUS);
++
+ 	return 0;
+ }
+ 
+@@ -610,6 +689,7 @@ static void emc2305_remove(struct i2c_client *client)
+ static struct i2c_driver emc2305_driver = {
+ 	.driver = {
+ 		.name = "emc2305",
++		.of_match_table = emc2305_dt_ids,
+ 	},
+ 	.probe = emc2305_probe,
+ 	.remove	  = emc2305_remove,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch b/patch/kernel/archive/meson64-6.10/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch
new file mode 100644
index 000000000000..d6c0036fae99
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch
@@ -0,0 +1,100 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: usera <adeep@lexina.in>
+Date: Mon, 12 Apr 2021 16:16:42 +0200
+Subject: Fix:meson64: add gpio irq (patch from
+ https://lkml.org/lkml/2020/11/27/8)
+
+Signed-off-by: Vyacheslav Bocharov <devel@lexina.in>
+---
+ drivers/pinctrl/meson/pinctrl-meson.c | 41 ++++++++++
+ drivers/pinctrl/meson/pinctrl-meson.h |  1 +
+ 2 files changed, 42 insertions(+)
+
+diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
+index 111111111111..222222222222 100644
+--- a/drivers/pinctrl/meson/pinctrl-meson.c
++++ b/drivers/pinctrl/meson/pinctrl-meson.c
+@@ -51,6 +51,7 @@
+ #include <linux/property.h>
+ #include <linux/regmap.h>
+ #include <linux/seq_file.h>
++#include <linux/of_irq.h>
+ 
+ #include "../core.h"
+ #include "../pinctrl-utils.h"
+@@ -601,6 +602,40 @@ static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
+ 	return !!(val & BIT(bit));
+ }
+ 
++static int meson_gpio_to_irq(struct gpio_chip *chip, unsigned int gpio)
++{
++	struct meson_pinctrl *pc = gpiochip_get_data(chip);
++	struct meson_bank *bank;
++	struct irq_fwspec fwspec;
++	int hwirq;
++
++	if (meson_get_bank(pc, gpio, &bank))
++		return -EINVAL;
++
++	if (bank->irq_first < 0) {
++		dev_warn(pc->dev, "no support irq for pin[%d]\n", gpio);
++		return -EINVAL;
++	}
++	if (!pc->of_irq) {
++		dev_err(pc->dev, "invalid device node of gpio INTC\n");
++		return -EINVAL;
++	}
++
++	hwirq = gpio - bank->first + bank->irq_first;
++	printk("gpio irq setup: hwirq: 0x%X irqfirst: 0x%X irqlast: 0x%X pin[%d]\n", hwirq, bank->irq_first, bank->irq_last, gpio);
++	if (hwirq > bank->irq_last)
++	{
++		dev_warn(pc->dev, "no more irq for pin[%d]\n", gpio);
++		return -EINVAL;
++	}
++	fwspec.fwnode = of_node_to_fwnode(pc->of_irq);
++	fwspec.param_count = 2;
++	fwspec.param[0] = hwirq;
++	fwspec.param[1] = IRQ_TYPE_NONE;
++
++	return irq_create_fwspec_mapping(&fwspec);
++}
++
+ static int meson_gpiolib_register(struct meson_pinctrl *pc)
+ {
+ 	int ret;
+@@ -616,6 +651,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc)
+ 	pc->chip.direction_output = meson_gpio_direction_output;
+ 	pc->chip.get = meson_gpio_get;
+ 	pc->chip.set = meson_gpio_set;
++	pc->chip.to_irq = meson_gpio_to_irq;
+ 	pc->chip.base = -1;
+ 	pc->chip.ngpio = pc->data->num_pins;
+ 	pc->chip.can_sleep = false;
+@@ -679,6 +715,11 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc)
+ 	pc->fwnode = gpiochip_node_get_first(pc->dev);
+ 	gpio_np = to_of_node(pc->fwnode);
+ 
++	pc->of_irq = of_find_compatible_node(NULL,
++					NULL, "amlogic,meson-gpio-intc");
++	if (!pc->of_irq)
++		pc->of_irq = of_find_compatible_node(NULL,
++				NULL, "amlogic,meson-gpio-intc-ext");
+ 	pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
+ 	if (IS_ERR_OR_NULL(pc->reg_mux)) {
+ 		dev_err(pc->dev, "mux registers not found\n");
+diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
+index 111111111111..222222222222 100644
+--- a/drivers/pinctrl/meson/pinctrl-meson.h
++++ b/drivers/pinctrl/meson/pinctrl-meson.h
+@@ -134,6 +134,7 @@ struct meson_pinctrl {
+ 	struct regmap *reg_ds;
+ 	struct gpio_chip chip;
+ 	struct fwnode_handle *fwnode;
++	struct device_node *of_irq;
+ };
+ 
+ #define FUNCTION(fn)							\
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/jethome-0002-arm64-dts-jethub-j1xx-add-eeprom-node.patch b/patch/kernel/archive/meson64-6.10/jethome-0002-arm64-dts-jethub-j1xx-add-eeprom-node.patch
new file mode 100644
index 000000000000..c9f14793d7d2
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/jethome-0002-arm64-dts-jethub-j1xx-add-eeprom-node.patch
@@ -0,0 +1,54 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Viacheslav Bocharov <adeep@lexina.in>
+Date: Fri, 20 Oct 2023 14:06:58 +0300
+Subject: arm64: dts: jethub-j1xx: add eeprom node
+
+Add node for eeprom on baseboard in JetHub D1+ device
+---
+ arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts | 12 ++++++++++
+ arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts | 12 ++++++++++
+ 2 files changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts
+@@ -47,3 +47,15 @@ eeprompd: eeprom@56 {
+ 		vcc-supply = <&vddao_3v3>;
+ 	};
+ };
++
++&i2c_AO {
++	/* EEPROM on base board */
++	eeprompd: eeprom@56 {
++                compatible = "atmel,24c64";
++                reg = <0x56>;
++                pagesize = <0x20>;
++		label = "eeprompd";
++		address-width = <0x10>;
++                vcc-supply = <&vddao_3v3>;
++        };
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts
+@@ -37,3 +37,15 @@ eeprompd: eeprom@56 {
+ 		vcc-supply = <&vddao_3v3>;
+ 	};
+ };
++
++&i2c_AO {
++	/* EEPROM on base board */
++	eeprompd: eeprom@56 {
++                compatible = "atmel,24c64";
++                reg = <0x56>;
++                pagesize = <0x20>;
++		label = "eeprompd";
++		address-width = <0x10>;
++                vcc-supply = <&vddao_3v3>;
++        };
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/jethome-0003-arm64-dts-meson-add-dts-links-to-secure-monitor-for-jethub.patch.disabled b/patch/kernel/archive/meson64-6.10/jethome-0003-arm64-dts-meson-add-dts-links-to-secure-monitor-for-jethub.patch.disabled
new file mode 100644
index 000000000000..a05a9a4e052e
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/jethome-0003-arm64-dts-meson-add-dts-links-to-secure-monitor-for-jethub.patch.disabled
@@ -0,0 +1,39 @@
+From 728157ef8e377f74289dc7397c2de4b3b6416ccc Mon Sep 17 00:00:00 2001
+From: Viacheslav Bocharov <adeep@lexina.in>
+Date: Thu, 22 Feb 2024 12:02:20 +0300
+Subject: [PATCH 5/5] arm64: dts: meson: add dts links to secure-monitor for
+ JetHub devices
+
+Signed-off-by: Viacheslav Bocharov <adeep@lexina.in>
+---
+ .../arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi | 4 ++++
+ .../boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts   | 4 ++++
+ 2 files changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi
+index db605f3a22b4..f3e679030788 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi
+@@ -348,3 +348,7 @@ &cpu2 {
+ &cpu3 {
+ 	#cooling-cells = <2>;
+ };
++
++&sec_AO {
++	secure-monitor = <&sm>;
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts
+index a18d6d241a5a..d75ba28d5e62 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts
+@@ -245,3 +245,7 @@ pcf8563: rtc@51 {
+ 		status = "okay";
+ 	};
+ };
++
++&sec_AO	{
++	secure-monitor = <&sm>;
++};
+-- 
+2.43.2
+
diff --git a/patch/kernel/archive/meson64-6.10/jethome-0003-dt-bindings-arm-amlogic-add-binding-for-JetHome-JetH.patch b/patch/kernel/archive/meson64-6.10/jethome-0003-dt-bindings-arm-amlogic-add-binding-for-JetHome-JetH.patch
new file mode 100644
index 000000000000..02e73c4f4b52
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/jethome-0003-dt-bindings-arm-amlogic-add-binding-for-JetHome-JetH.patch
@@ -0,0 +1,28 @@
+From e38ecc4ec467c5eb1b7e510877532239a43f7db8 Mon Sep 17 00:00:00 2001
+From: Viacheslav Bocharov <adeep@lexina.in>
+Date: Thu, 6 Jun 2024 14:31:12 +0300
+Subject: [PATCH 1/2] dt-bindings: arm: amlogic: add binding for JetHome JetHub
+ D2
+
+JetHome JetHub D2 is a home automation controller, based on Amlogic S905X3 SoC
+
+Signed-off-by: Viacheslav Bocharov <adeep@lexina.in>
+---
+ Documentation/devicetree/bindings/arm/amlogic.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
+index a374b98080fe..1acfb184aa9e 100644
+--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
++++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
+@@ -190,6 +190,7 @@ properties:
+               - hardkernel,odroid-c4
+               - hardkernel,odroid-hc4
+               - haochuangyi,h96-max
++              - jethome,jethub-j200
+               - khadas,vim3l
+               - libretech,aml-s905d3-cc
+               - seirobotics,sei610
+-- 
+2.45.2
+
diff --git a/patch/kernel/archive/meson64-6.10/kernel-6.8-tools-cgroup-makefile.patch b/patch/kernel/archive/meson64-6.10/kernel-6.8-tools-cgroup-makefile.patch
new file mode 100644
index 000000000000..02f1e527e6e7
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/kernel-6.8-tools-cgroup-makefile.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ColorfulRhino <131405023+ColorfulRhino@users.noreply.github.com>
+Date: Sat, 30 Mar 2024 21:09:12 +0100
+Subject: [ARCHEOLOGY] meson-s4t7: Fix custom_kernel_config: hash modification
+ has to happen inside the first function call
+
+> X-Git-Archeology: > recovered message: > Will be ignored on second time the function is called
+> X-Git-Archeology: - Revision 6ced5cc02637fb6dbc980aa77fcdc77f2ccf5067: https://github.com/armbian/build/commit/6ced5cc02637fb6dbc980aa77fcdc77f2ccf5067
+> X-Git-Archeology:   Date: Sat, 30 Mar 2024 21:09:12 +0100
+> X-Git-Archeology:   From: ColorfulRhino <131405023+ColorfulRhino@users.noreply.github.com>
+> X-Git-Archeology:   Subject: meson-s4t7: Fix custom_kernel_config: hash modification has to happen inside the first function call
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision caf0529240948df416b015aeea8c23e420a55ce6: https://github.com/armbian/build/commit/caf0529240948df416b015aeea8c23e420a55ce6
+> X-Git-Archeology:   Date: Sun, 31 Mar 2024 18:21:26 -0400
+> X-Git-Archeology:   From: Barry Lind (SteeManMI) <barrylind@yahoo.com>
+> X-Git-Archeology:   Subject: Bump meson64 edge from 6.7 to 6.8
+> X-Git-Archeology:
+---
+ tools/cgroup/Makefile | 11 ++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/tools/cgroup/Makefile b/tools/cgroup/Makefile
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/tools/cgroup/Makefile
+@@ -0,0 +1,11 @@
++# SPDX-License-Identifier: GPL-2.0
++# Makefile for cgroup tools
++
++CFLAGS = -Wall -Wextra
++
++all: cgroup_event_listener
++%: %.c
++	$(CC) $(CFLAGS) -o $@ $^
++
++clean:
++	$(RM) cgroup_event_listener
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/meson-g12a-pinctrl-add-missing-ir-options.patch b/patch/kernel/archive/meson64-6.10/meson-g12a-pinctrl-add-missing-ir-options.patch
new file mode 100644
index 000000000000..93b424652897
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/meson-g12a-pinctrl-add-missing-ir-options.patch
@@ -0,0 +1,91 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Yuntian Zhang <yt@radxa.com>
+Date: Mon, 25 Jul 2022 15:31:31 +0800
+Subject: pinctrl: meson-g12a: add missing ir options
+
+Those pins are defined in S905Y2 and A311D reference manuals.
+
+Signed-off-by: Yuntian Zhang <yt@radxa.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 16 ++++++++++
+ drivers/pinctrl/meson/pinctrl-meson-g12a.c        |  9 ++++++
+ 2 files changed, 25 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+@@ -563,6 +563,14 @@ mux {
+ 						};
+ 					};
+ 
++					remote_input_pins: remote-input {
++						mux {
++							groups = "remote_input";
++							function = "remote_input";
++							bias-disable;
++						};
++					};
++
+ 					mclk0_a_pins: mclk0-a {
+ 						mux {
+ 							groups = "mclk0_a";
+@@ -2034,6 +2042,14 @@ mux {
+ 							bias-disable;
+ 						};
+ 					};
++
++					remote_out_ao_pins: remote-out {
++						mux {
++							groups = "remote_ao_out";
++							function = "remote_ao_out";
++							bias-disable;
++						};
++					};
+ 				};
+ 			};
+ 
+diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
+index 111111111111..222222222222 100644
+--- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c
++++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
+@@ -216,6 +216,9 @@ static const unsigned int i2c3_sck_h_pins[]		= { GPIOH_1 };
+ static const unsigned int i2c3_sda_a_pins[]		= { GPIOA_14 };
+ static const unsigned int i2c3_sck_a_pins[]		= { GPIOA_15 };
+ 
++/* ir_in */
++static const unsigned int remote_input_pins[]	= { GPIOA_15 };
++
+ /* uart_a */
+ static const unsigned int uart_a_tx_pins[]		= { GPIOX_12 };
+ static const unsigned int uart_a_rx_pins[]		= { GPIOX_13 };
+@@ -737,6 +740,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = {
+ 	/* bank GPIOA */
+ 	GROUP(i2c3_sda_a,		2),
+ 	GROUP(i2c3_sck_a,		2),
++	GROUP(remote_input,		1),
+ 	GROUP(pdm_din0_a,		1),
+ 	GROUP(pdm_din1_a,		1),
+ 	GROUP(pdm_din2_a,		1),
+@@ -1022,6 +1026,10 @@ static const char * const i2c3_groups[] = {
+ 	"i2c3_sda_a", "i2c3_sck_a",
+ };
+ 
++static const char * const remote_input_groups[] = {
++	"remote_input",
++};
++
+ static const char * const uart_a_groups[] = {
+ 	"uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
+ };
+@@ -1266,6 +1274,7 @@ static struct meson_pmx_func meson_g12a_periphs_functions[] = {
+ 	FUNCTION(i2c1),
+ 	FUNCTION(i2c2),
+ 	FUNCTION(i2c3),
++	FUNCTION(remote_input),
+ 	FUNCTION(uart_a),
+ 	FUNCTION(uart_b),
+ 	FUNCTION(uart_c),
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/meson-g12b-pinctrl-Add-missing-pinmux-for-pwm.patch b/patch/kernel/archive/meson64-6.10/meson-g12b-pinctrl-Add-missing-pinmux-for-pwm.patch
new file mode 100644
index 000000000000..f929f37d34f1
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/meson-g12b-pinctrl-Add-missing-pinmux-for-pwm.patch
@@ -0,0 +1,125 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Yuntian Zhang <yt@radxa.com>
+Date: Thu, 13 Jan 2022 21:34:10 +0800
+Subject: pinctrl: meson: Add several missing pinmux for pwm functions
+
+The following pin definitions are mentioned in A311D Quick
+Reference Manual and S922X Public Datasheet, but not in S905Y2
+Quick Reference Manual, so adding them to meson-g12b family.
+
+They are currently exposed in Radxa Zero 2's GPIO header.
+
+Signed-off-by: Yuntian Zhang <yt@radxa.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 34 ++++++++++
+ drivers/pinctrl/meson/pinctrl-meson-g12a.c  | 14 +++-
+ 2 files changed, 45 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+@@ -149,3 +149,37 @@ &pmu {
+ &npu {
+ 	power-domains = <&pwrc PWRC_G12A_NNA_ID>;
+ };
++
++&periphs_pinctrl {
++	pwm_b_h_pins: pwm-b-h {
++		mux {
++			groups = "pwm_b_h";
++			function = "pwm_b";
++			bias-disable;
++		};
++	};
++
++	pwm_b_z_pins: pwm-b-z {
++		mux {
++			groups = "pwm_b_z";
++			function = "pwm_b";
++			bias-disable;
++		};
++	};
++
++	pwm_c_z_pins: pwm-c-z {
++		mux {
++			groups = "pwm_c_z";
++			function = "pwm_c";
++			bias-disable;
++		};
++	};
++
++	pwm_d_z_pins: pwm-d-z {
++		mux {
++			groups = "pwm_d_z";
++			function = "pwm_d";
++			bias-disable;
++		};
++	};
++};
+diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
+index 111111111111..222222222222 100644
+--- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c
++++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
+@@ -271,17 +271,21 @@ static const unsigned int eth_act_led_pins[]		= { GPIOZ_15 };
+ static const unsigned int pwm_a_pins[]			= { GPIOX_6 };
+ 
+ /* pwm_b */
++static const unsigned int pwm_b_h_pins[]		= { GPIOH_7 };
+ static const unsigned int pwm_b_x7_pins[]		= { GPIOX_7 };
+ static const unsigned int pwm_b_x19_pins[]		= { GPIOX_19 };
++static const unsigned int pwm_b_z_pins[]		= { GPIOZ_0 };
+ 
+ /* pwm_c */
+ static const unsigned int pwm_c_c_pins[]		= { GPIOC_4 };
+ static const unsigned int pwm_c_x5_pins[]		= { GPIOX_5 };
+ static const unsigned int pwm_c_x8_pins[]		= { GPIOX_8 };
++static const unsigned int pwm_c_z_pins[]		= { GPIOZ_1 };
+ 
+ /* pwm_d */
+ static const unsigned int pwm_d_x3_pins[]		= { GPIOX_3 };
+ static const unsigned int pwm_d_x6_pins[]		= { GPIOX_6 };
++static const unsigned int pwm_d_z_pins[]		= { GPIOZ_2 };
+ 
+ /* pwm_e */
+ static const unsigned int pwm_e_pins[]			= { GPIOX_16 };
+@@ -594,6 +598,9 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = {
+ 	GROUP(bt565_a_din5,		2),
+ 	GROUP(bt565_a_din6,		2),
+ 	GROUP(bt565_a_din7,		2),
++	GROUP(pwm_b_z,			5),
++	GROUP(pwm_c_z,			5),
++	GROUP(pwm_d_z,			2),
+ 	GROUP(tsin_b_valid_z,		3),
+ 	GROUP(tsin_b_sop_z,		3),
+ 	GROUP(tsin_b_din0_z,		3),
+@@ -726,6 +733,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = {
+ 	GROUP(uart_c_rts,		2),
+ 	GROUP(iso7816_clk_h,		1),
+ 	GROUP(iso7816_data_h,		1),
++	GROUP(pwm_b_h,			5),
+ 	GROUP(pwm_f_h,			4),
+ 	GROUP(cec_ao_a_h,		4),
+ 	GROUP(cec_ao_b_h,		5),
+@@ -1066,15 +1074,15 @@ static const char * const pwm_a_groups[] = {
+ };
+ 
+ static const char * const pwm_b_groups[] = {
+-	"pwm_b_x7", "pwm_b_x19",
++	"pwm_b_h", "pwm_b_x7", "pwm_b_x19", "pwm_b_z",
+ };
+ 
+ static const char * const pwm_c_groups[] = {
+-	"pwm_c_c", "pwm_c_x5", "pwm_c_x8",
++	"pwm_c_c", "pwm_c_x5", "pwm_c_x8", "pwm_c_z",
+ };
+ 
+ static const char * const pwm_d_groups[] = {
+-	"pwm_d_x3", "pwm_d_x6",
++	"pwm_d_x3", "pwm_d_x6", "pwm_d_z",
+ };
+ 
+ static const char * const pwm_e_groups[] = {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch b/patch/kernel/archive/meson64-6.10/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch
new file mode 100644
index 000000000000..21d7667755ff
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch
@@ -0,0 +1,40 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Thu, 3 Nov 2016 15:29:25 +0100
+Subject: HACK: arm64: dts: meson: add support for GX PM and Virtual RTC
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+@@ -223,6 +223,10 @@ sm: secure-monitor {
+ 		};
+ 	};
+ 
++	system-suspend {
++		compatible = "amlogic,meson-gx-pm";
++	};
++
+ 	efuse: efuse {
+ 		compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
+ 		#address-cells = <1>;
+@@ -461,6 +465,11 @@ clkc_AO: clock-controller {
+ 				};
+ 			};
+ 
++			vrtc: rtc@a8 {
++				compatible = "amlogic,meson-vrtc";
++				reg = <0x0 0x000a8 0x0 0x4>;
++			};
++
+ 			cec_AO: cec@100 {
+ 				compatible = "amlogic,meson-gx-ao-cec";
+ 				reg = <0x0 0x00100 0x0 0x14>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/meson-gxbb-dts-i2cX-missing-pins.patch b/patch/kernel/archive/meson64-6.10/meson-gxbb-dts-i2cX-missing-pins.patch
new file mode 100644
index 000000000000..57b65d9db285
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/meson-gxbb-dts-i2cX-missing-pins.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Ayotte <martinayotte@yahoo.ca>
+Date: Wed, 5 Dec 2018 17:35:05 -0500
+Subject: fix i2cA and i2cB miossing pins
+
+- c80617d145039a32b53e9f0908353aaea3d368a6: 1544111688: Martin Ayotte <martinayotte@yahoo.ca>: 'add i2c_B missing pins'
+---
+ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+@@ -333,6 +333,8 @@ &hwrng {
+ 
+ &i2c_A {
+ 	clocks = <&clkc CLKID_I2C>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c_a_pins>;
+ };
+ 
+ &i2c_AO {
+@@ -341,6 +343,8 @@ &i2c_AO {
+ 
+ &i2c_B {
+ 	clocks = <&clkc CLKID_I2C>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c_b_pins>;
+ };
+ 
+ &i2c_C {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch b/patch/kernel/archive/meson64-6.10/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch
new file mode 100644
index 000000000000..4d0717675485
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch
@@ -0,0 +1,39 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Sun, 21 Nov 2021 19:12:07 +0000
+Subject: WIP: drivers: meson: vdec: add HEVC support to GXBB
+
+It's not clear whether the GXL firmware is the same one used with GXBB
+but let's try it and see!
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+---
+ drivers/staging/media/meson/vdec/vdec_platform.c | 12 ++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/vdec_platform.c
++++ b/drivers/staging/media/meson/vdec/vdec_platform.c
+@@ -16,6 +16,18 @@
+ 
+ static const struct amvdec_format vdec_formats_gxbb[] = {
+ 	{
++		.pixfmt = V4L2_PIX_FMT_HEVC,
++		.min_buffers = 4,
++		.max_buffers = 24,
++		.max_width = 3840,
++		.max_height = 2160,
++		.vdec_ops = &vdec_hevc_ops,
++		.codec_ops = &codec_hevc_ops,
++		.firmware_path = "meson/vdec/gxl_hevc.bin",
++		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
++		.flags = V4L2_FMT_FLAG_COMPRESSED |
++			 V4L2_FMT_FLAG_DYN_RESOLUTION,
++        }, {
+ 		.pixfmt = V4L2_PIX_FMT_H264,
+ 		.min_buffers = 2,
+ 		.max_buffers = 24,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/meson-gxl-gxm-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch b/patch/kernel/archive/meson64-6.10/meson-gxl-gxm-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch
new file mode 100644
index 000000000000..925ab80df2c2
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/meson-gxl-gxm-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch
@@ -0,0 +1,125 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Tue, 18 Jan 2022 15:09:12 +0000
+Subject: WIP: arm64: dts: meson: set p212/p23x/q20x SDIO to 100MHz + add UHS
+ SDIO capabilities
+
+WIP: arm64: dts: meson: add UHS SDIO capabilities to p212/p23x/q20x
+
+Add UHS capabilities to the SDIO node to enable 100MHz speeds.
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+
+WIP: arm64: dts: meson: set p212/p23x/q20x SDIO to 100MHz
+
+Amlogic datasheets describe 50MHz max-frequency for SDIO on GXL/GXM but
+real-world tests on an assortment of GXL and GXM boards show noteable
+increases in throughput when max-frequency is 100MHz, so let's use it.
+
+Before results from a p231 device:
+
+Connecting to host 192.168.0.1, port 5201
+Reverse mode, remote host 192.168.0.1 is sending
+[  5] local 192.168.0.41 port 42550 connected to 192.168.0.1 port 5201
+[ ID] Interval           Transfer     Bitrate
+[  5]   0.00-1.00   sec  8.84 MBytes  74.2 Mbits/sec
+[  5]   1.00-2.00   sec  9.60 MBytes  80.5 Mbits/sec
+[  5]   2.00-3.00   sec  9.07 MBytes  76.1 Mbits/sec
+[  5]   3.00-4.00   sec  9.14 MBytes  76.6 Mbits/sec
+[  5]   4.00-5.00   sec  9.26 MBytes  77.7 Mbits/sec
+[  5]   5.00-6.00   sec  9.08 MBytes  76.2 Mbits/sec
+[  5]   6.00-7.00   sec  9.11 MBytes  76.4 Mbits/sec
+[  5]   7.00-8.00   sec  8.65 MBytes  72.5 Mbits/sec
+[  5]   8.00-9.00   sec  9.24 MBytes  77.5 Mbits/sec
+[  5]   9.00-10.00  sec  8.57 MBytes  71.9 Mbits/sec
+- - - - - - - - - - - - - - - - - - - - - - - - -
+[ ID] Interval           Transfer     Bitrate         Retr
+[  5]   0.00-10.27  sec  94.1 MBytes  76.8 Mbits/sec    0             sender
+[  5]   0.00-10.00  sec  90.6 MBytes  76.0 Mbits/sec                  receiver
+
+clock:		50000000 Hz
+actual clock:	50000000 Hz
+vdd:		21 (3.3 ~ 3.4 V)
+bus mode:	2 (push-pull)
+chip select:	0 (don't care)
+power mode:	2 (on)
+bus width:	2 (4 bits)
+timing spec:	2 (sd high-speed)
+signal voltage:	1 (1.80 V)
+driver type:	0 (driver type B)
+
+After results from a p231 device:
+
+Connecting to host 192.168.0.1, port 5201
+Reverse mode, remote host 192.168.0.1 is sending
+[  5] local 192.168.0.41 port 58534 connected to 192.168.0.1 port 5201
+[ ID] Interval           Transfer     Bitrate
+[  5]   0.00-1.00   sec  12.6 MBytes   106 Mbits/sec
+[  5]   1.00-2.00   sec  13.0 MBytes   109 Mbits/sec
+[  5]   2.00-3.00   sec  12.8 MBytes   107 Mbits/sec
+[  5]   3.00-4.00   sec  13.2 MBytes   111 Mbits/sec
+[  5]   4.00-5.00   sec  12.4 MBytes   104 Mbits/sec
+[  5]   5.00-6.00   sec  11.2 MBytes  93.9 Mbits/sec
+[  5]   6.00-7.00   sec  12.3 MBytes   103 Mbits/sec
+[  5]   7.00-8.00   sec  12.3 MBytes   103 Mbits/sec
+[  5]   8.00-9.00   sec  12.5 MBytes   105 Mbits/sec
+[  5]   9.00-10.00  sec  12.3 MBytes   103 Mbits/sec
+- - - - - - - - - - - - - - - - - - - - - - - - -
+[ ID] Interval           Transfer     Bitrate         Retr
+[  5]   0.00-10.22  sec   127 MBytes   104 Mbits/sec    0             sender
+[  5]   0.00-10.00  sec   125 MBytes   105 Mbits/sec                  receiver
+
+clock:		100000000 Hz
+actual clock:	100000000 Hz
+vdd:		21 (3.3 ~ 3.4 V)
+bus mode:	2 (push-pull)
+chip select:	0 (don't care)
+power mode:	2 (on)
+bus width:	2 (4 bits)
+timing spec:	6 (sd uhs SDR104)
+signal voltage:	1 (1.80 V)
+driver type:	0 (driver type B)
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi   | 6 +++++-
+ arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi | 6 +++++-
+ 2 files changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+@@ -256,7 +256,11 @@ &sd_emmc_a {
+ 
+ 	bus-width = <4>;
+ 	cap-sd-highspeed;
+-	max-frequency = <50000000>;
++	sd-uhs-sdr12;
++	sd-uhs-sdr25;
++	sd-uhs-sdr50;
++	sd-uhs-sdr104;
++	max-frequency = <100000000>;
+ 
+ 	non-removable;
+ 	disable-wp;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+@@ -121,7 +121,11 @@ &sd_emmc_a {
+ 
+ 	bus-width = <4>;
+ 	cap-sd-highspeed;
+-	max-frequency = <50000000>;
++	sd-uhs-sdr12;
++	sd-uhs-sdr25;
++	sd-uhs-sdr50;
++	sd-uhs-sdr104;
++	max-frequency = <100000000>;
+ 
+ 	non-removable;
+ 	disable-wp;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/meson-gxm-vdec-add-VP9-support-to-GXM.patch b/patch/kernel/archive/meson64-6.10/meson-gxm-vdec-add-VP9-support-to-GXM.patch
new file mode 100644
index 000000000000..ec42754188b8
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/meson-gxm-vdec-add-VP9-support-to-GXM.patch
@@ -0,0 +1,43 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Thu, 25 Nov 2021 11:31:43 +0000
+Subject: drivers: meson: vdec: add VP9 support to GXM
+
+VP9 support for GXM appears to have been missed from the original
+codec submission [0] but it works well, so let's add support.
+
+[0] https://github.com/torvalds/linux/commit/00c43088aa680989407b6afbda295f67b3f123f1
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+---
+ drivers/staging/media/meson/vdec/vdec_platform.c | 14 +++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/meson/vdec/vdec_platform.c
++++ b/drivers/staging/media/meson/vdec/vdec_platform.c
+@@ -27,7 +27,19 @@ static const struct amvdec_format vdec_formats_gxbb[] = {
+ 		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+ 		.flags = V4L2_FMT_FLAG_COMPRESSED |
+ 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+-        }, {
++	}, {
++		.pixfmt = V4L2_PIX_FMT_VP9,
++		.min_buffers = 16,
++		.max_buffers = 24,
++		.max_width = 3840,
++		.max_height = 2160,
++		.vdec_ops = &vdec_hevc_ops,
++		.codec_ops = &codec_vp9_ops,
++		.firmware_path = "meson/vdec/gxl_vp9.bin",
++		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
++		.flags = V4L2_FMT_FLAG_COMPRESSED |
++			V4L2_FMT_FLAG_DYN_RESOLUTION,
++	}, {
+ 		.pixfmt = V4L2_PIX_FMT_H264,
+ 		.min_buffers = 2,
+ 		.max_buffers = 24,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/meson-sm1-dts-add-higher-clocks.patch b/patch/kernel/archive/meson64-6.10/meson-sm1-dts-add-higher-clocks.patch
new file mode 100644
index 000000000000..fd5af09cfa28
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/meson-sm1-dts-add-higher-clocks.patch
@@ -0,0 +1,34 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igor.pecovnik@gmail.com>
+Date: Tue, 4 Aug 2020 22:51:56 +0200
+Subject: Add higher clocks for SM1 family
+
+Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+@@ -136,6 +136,16 @@ opp-1908000000 {
+ 			opp-hz = /bits/ 64 <1908000000>;
+ 			opp-microvolt = <950000>;
+ 		};
++
++		opp-2016000000 {
++			opp-hz = /bits/ 64 <2016000000>;
++			opp-microvolt = <1000000>;
++		};
++
++		opp-2100000000 {
++			opp-hz = /bits/ 64 <2100000000>;
++			opp-microvolt = <1022000>;
++		};
+ 	};
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/meson64-6.10/overlay/Makefile b/patch/kernel/archive/meson64-6.10/overlay/Makefile
new file mode 100644
index 000000000000..bbd0103cf53a
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/Makefile
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0
+dtbo-$(CONFIG_ARCH_MESON) += \
+	meson-i2cA.dtbo \
+	meson-i2cB.dtbo \
+	meson-uartA.dtbo \
+	meson-uartC.dtbo \
+	meson-w1-gpio.dtbo \
+	meson-w1AB-gpio.dtbo \
+	meson-g12-gxl-cma-pool-896MB.dtbo \
+	meson-g12-pwm-gpiox-5-fan.dtbo \
+	meson-g12a-radxa-zero-gpio-8-led.dtbo \
+	meson-g12a-radxa-zero-gpio-10-led.dtbo \
+	meson-g12a-radxa-zero-i2c-ao-m0-gpioao-2-gpioao-3.dtbo \
+	meson-g12a-radxa-zero-i2c-ee-m1-gpioh-6-gpioh-7.dtbo \
+	meson-g12a-radxa-zero-i2c-ee-m1-gpiox-10-gpiox-11.dtbo \
+	meson-g12a-radxa-zero-i2c-ee-m3-gpioa-14-gpioa-15.dtbo \
+	meson-g12a-radxa-zero-pwm-c-on-gpiox-8.dtbo \
+	meson-g12a-radxa-zero-pwmao-a-on-gpioao-11.dtbo \
+	meson-g12a-radxa-zero-spi-spidev.dtbo \
+	meson-g12a-radxa-zero-uart-ao-a-on-gpioao-0-gpioao-1.dtbo \
+	meson-g12a-radxa-zero-uart-ao-b-on-gpioao-2-gpioao-3.dtbo \
+	meson-g12a-radxa-zero-uart-ao-b-on-gpioao-8-gpioao-9.dtbo \
+	meson-g12a-radxa-zero-uart-ee-c.dtbo \
+	meson-g12b-bananapi-cm4-pwm-gpioh-5-fan.dtbo \
+	meson-g12b-bananapi-m2s-rtl8822cs.dtbo \
+	meson-g12b-odroid-n2-spi.dtbo \
+	meson-g12b-waveshare-cm4-io-base-usb.dtbo \
+	meson-sm1-bananapi-m5-rtl8822cs.dtbo \
+	meson-sm1-bananapi-uartA.dtbo \
+	meson-sm1-bananapi-uartA_cts_rts.dtbo \
+	meson-sm1-bananapi-uartAO_B.dtbo \
+	meson-sm1-jethome-jethub-j200-spi.dtbo
+
+scr-$(CONFIG_ARCH_MESON) += \
+       meson-fixup.scr
+
+dtbotxt-$(CONFIG_ARCH_MESON) += \
+       README.meson-overlays
+
+dtb-y += $(dtbo-y) $(scr-y) $(dtbotxt-y)
+
+clean-files    := *.dtbo *.scr
diff --git a/patch/kernel/archive/meson64-6.10/overlay/README.meson-overlays b/patch/kernel/archive/meson64-6.10/overlay/README.meson-overlays
new file mode 100644
index 000000000000..1b169a7a1525
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/README.meson-overlays
@@ -0,0 +1,20 @@
+This document describes overlays provided in the kernel packages
+For generic Armbian overlays documentation please see
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
+
+### Platform:
+
+meson (Amlogic)
+
+### Provided overlays:
+
+- i2c8
+
+### Overlay details:
+
+### i2c8
+
+Activates TWI/I2C bus 8
+
+I2C8 pins (SCL, SDA): GPIO1-C4, GPIO1-C5
+
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-fixup.scr-cmd b/patch/kernel/archive/meson64-6.10/overlay/meson-fixup.scr-cmd
new file mode 100644
index 000000000000..d4c39e20a3a2
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-fixup.scr-cmd
@@ -0,0 +1,4 @@
+# overlays fixup script
+# implements (or rather substitutes) overlay arguments functionality
+# using u-boot scripting, environment variables and "fdt" command
+
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12-gxl-cma-pool-896MB.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12-gxl-cma-pool-896MB.dtso
new file mode 100644
index 000000000000..f8c476b04e8c
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12-gxl-cma-pool-896MB.dtso
@@ -0,0 +1,19 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "amlogic,g12a", "amlogic,g12b", "amlogic,meson-gxl";
+
+	fragment@0 {
+		target-path = "/reserved-memory";
+		__overlay__ {
+			linux,cma {
+				compatible = "shared-dma-pool";
+				reusable;
+				size = <0x0 0x38000000>;
+				alignment = <0x0 0x400000>;
+				linux,cma-default;
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12-pwm-gpiox-5-fan.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12-pwm-gpiox-5-fan.dtso
new file mode 100644
index 000000000000..2042c7fed521
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12-pwm-gpiox-5-fan.dtso
@@ -0,0 +1,43 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	compatible = "amlogic,a311d", "amlogic,g12a", "amlogic,g12b", "amlogic,sm1";
+
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+			fan: gpio-fan {
+				compatible = "gpio-fan";
+				gpios = <&gpio GPIOX_5 GPIO_ACTIVE_HIGH>;
+				gpio-fan,speed-map = <0 0>, <5000 1>;
+				#cooling-cells = <2>;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&cpu_thermal>;
+		polling-delay = <2000>;
+		__overlay__ {
+			trips {
+				cpu_active: cpu-active {
+					temperature = <55000>;
+					hysteresis = <10000>;
+					type = "active";
+				};
+			};
+
+			cooling-maps {
+				map {
+					trip = <&cpu_active>;
+					cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-gpio-10-led.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-gpio-10-led.dtso
new file mode 100644
index 000000000000..d76430328955
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-gpio-10-led.dtso
@@ -0,0 +1,26 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target-path = "/";
+			__overlay__ {
+
+			leds {
+				compatible = "gpio-leds";
+
+				led-green {
+					label = "radxa-zero:green";
+					gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>;
+					linux,default-trigger = "heartbeat";
+					default-state = "on";
+				};
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-gpio-8-led.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-gpio-8-led.dtso
new file mode 100644
index 000000000000..9b294e97f79f
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-gpio-8-led.dtso
@@ -0,0 +1,26 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target-path = "/";
+			__overlay__ {
+
+			leds {
+				compatible = "gpio-leds";
+
+				led-green {
+					label = "radxa-zero:green";
+					gpios = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
+					linux,default-trigger = "heartbeat";
+					default-state = "on";
+				};
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ao-m0-gpioao-2-gpioao-3.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ao-m0-gpioao-2-gpioao-3.dtso
new file mode 100644
index 000000000000..3f241cb60179
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ao-m0-gpioao-2-gpioao-3.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&i2c_AO>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&i2c_ao_sck_pins &i2c_ao_sda_pins>;
+			pinctrl-names = "default";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpioh-6-gpioh-7.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpioh-6-gpioh-7.dtso
new file mode 100644
index 000000000000..a68284bf61b8
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpioh-6-gpioh-7.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&i2c1>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&i2c1_sda_h6_pins &i2c1_sck_h7_pins>;
+			pinctrl-names = "default";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpiox-10-gpiox-11.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpiox-10-gpiox-11.dtso
new file mode 100644
index 000000000000..eb9c402fb633
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpiox-10-gpiox-11.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&i2c1>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&i2c1_sda_x_pins &i2c1_sck_x_pins>;
+			pinctrl-names = "default";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ee-m3-gpioa-14-gpioa-15.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ee-m3-gpioa-14-gpioa-15.dtso
new file mode 100644
index 000000000000..12a7bc4d460b
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-i2c-ee-m3-gpioa-14-gpioa-15.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&i2c3>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&i2c3_sck_a_pins &i2c3_sda_a_pins>;
+			pinctrl-names = "default";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-pwm-c-on-gpiox-8.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-pwm-c-on-gpiox-8.dtso
new file mode 100644
index 000000000000..14ca6c1964f8
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-pwm-c-on-gpiox-8.dtso
@@ -0,0 +1,17 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&pwm_cd>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm_c_x8_pins>;
+			pinctrl-names = "default";
+			clocks = <&xtal>;
+			clock-names = "clkin2";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-pwmao-a-on-gpioao-11.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-pwmao-a-on-gpioao-11.dtso
new file mode 100644
index 000000000000..6edbe62224cc
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-pwmao-a-on-gpioao-11.dtso
@@ -0,0 +1,17 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&pwm_AO_ab>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm_ao_a_pins>;
+			pinctrl-names = "default";
+			clocks = <&xtal>;
+			clock-names = "clkin3";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-spi-spidev.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-spi-spidev.dtso
new file mode 100644
index 000000000000..3d49a512eafa
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-spi-spidev.dtso
@@ -0,0 +1,38 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&spicc0>;
+		__overlay__ {
+			pinctrl-0 = <&spicc0_x_pins &spicc0_ss0_x_pins>;
+			pinctrl-names = "default";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev@0 {
+				compatible = "armbian,spi-dev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <10000000>;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&spicc1>;
+		__overlay__ {
+			pinctrl-0 = <&spicc1_pins &spicc1_ss0_pins>;
+			pinctrl-names = "default";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev@0 {
+				compatible = "armbian,spi-dev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <10000000>;
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ao-a-on-gpioao-0-gpioao-1.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ao-a-on-gpioao-0-gpioao-1.dtso
new file mode 100644
index 000000000000..350448d20d88
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ao-a-on-gpioao-0-gpioao-1.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&uart_AO>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&uart_ao_a_pins>;
+			pinctrl-names = "default";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-2-gpioao-3.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-2-gpioao-3.dtso
new file mode 100644
index 000000000000..26790de42535
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-2-gpioao-3.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&uart_AO_B>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&uart_ao_b_2_3_pins>;
+			pinctrl-names = "default";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-8-gpioao-9.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-8-gpioao-9.dtso
new file mode 100644
index 000000000000..ff3e522854b0
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-8-gpioao-9.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&uart_AO_B>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&uart_ao_b_8_9_pins>;
+			pinctrl-names = "default";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ee-c.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ee-c.dtso
new file mode 100644
index 000000000000..afcf79eeab21
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12a-radxa-zero-uart-ee-c.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,zero", "amlogic,g12a";
+
+	fragment@0 {
+		target = <&uart_C>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&uart_c_pins &uart_c_cts_rts_pins>;
+			pinctrl-names = "default";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-bananapi-cm4-pwm-gpioh-5-fan.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-bananapi-cm4-pwm-gpioh-5-fan.dtso
new file mode 100644
index 000000000000..db8d326c8ab8
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-bananapi-cm4-pwm-gpioh-5-fan.dtso
@@ -0,0 +1,63 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";
+
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+			fan: gpio-fan {
+				compatible = "gpio-fan";
+				gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+				gpio-fan,speed-map = <0 0>, <5000 1>;
+				#cooling-cells = <2>;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&cpu_thermal>;
+		polling-delay = <2000>;
+		__overlay__ {
+			trips {
+				cpu_active: cpu-active {
+					temperature = <55000>;
+					hysteresis = <10000>;
+					type = "active";
+				};
+			};
+
+			cooling-maps {
+				map {
+					trip = <&cpu_active>;
+					cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&ddr_thermal>;
+		__overlay__ {
+			trips {
+				ddr_active: ddr-active {
+					temperature = <55000>;
+					hysteresis = <10000>;
+					type = "active";
+				};
+			};
+
+			cooling-maps {
+				map {
+					trip = <&ddr_active>;
+					cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-bananapi-m2s-rtl8822cs.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-bananapi-m2s-rtl8822cs.dtso
new file mode 100644
index 000000000000..f037f8ec4ad8
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-bananapi-m2s-rtl8822cs.dtso
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-m2s", "amlogic,a311d", "amlogic,g12b";
+
+	/* RTL8822CS SDIO WIFI */
+	fragment@0 {
+		target = <&sd_emmc_a>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	/* RTL8822CS BLUETOOTH */
+	fragment@1 {
+		target = <&uart_A>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-odroid-n2-spi.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-odroid-n2-spi.dtso
new file mode 100644
index 000000000000..658afb1fb58d
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-odroid-n2-spi.dtso
@@ -0,0 +1,23 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+	fragment@0 {
+		target = <&sd_emmc_c>;
+		__overlay__ {
+			pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>;
+			bus-width = <4>;
+		};
+	};
+
+	fragment@1 {
+		target = <&spifc>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-waveshare-cm4-io-base-usb.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-waveshare-cm4-io-base-usb.dtso
new file mode 100644
index 000000000000..0516113267d3
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-g12b-waveshare-cm4-io-base-usb.dtso
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";
+
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+			model = "Waveshare CM4-IO Baseboard with BPI-CM4 Module";
+		};
+	};
+	
+	fragment@1 {
+		target = <&usb>;
+		__overlay__ {
+			dr_mode = "host";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-i2cA.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-i2cA.dtso
new file mode 100644
index 000000000000..bfb72feb7e36
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-i2cA.dtso
@@ -0,0 +1,17 @@
+/dts-v1/;
+
+/ {
+    compatible = "amlogic,meson-gxbb";
+    fragment@0 {
+        target-path = "/aliases";
+        __overlay__ {
+            i2cA = "/soc/bus@c1100000/i2c@8500";
+        };
+    };
+    fragment@1 {
+	target-path = "/soc/bus@c1100000/i2c@8500";
+        __overlay__ {
+            status = "okay";
+        };
+    };
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-i2cB.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-i2cB.dtso
new file mode 100644
index 000000000000..d75867bce99b
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-i2cB.dtso
@@ -0,0 +1,17 @@
+/dts-v1/;
+
+/ {
+    compatible = "amlogic,meson-gxbb";
+    fragment@0 {
+        target-path = "/aliases";
+        __overlay__ {
+            i2cA = "/soc/bus@c1100000/i2c@87c0";
+        };
+    };
+    fragment@1 {
+	target-path = "/soc/bus@c1100000/i2c@87c0";
+        __overlay__ {
+            status = "okay";
+        };
+    };
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-m5-rtl8822cs.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-m5-rtl8822cs.dtso
new file mode 100644
index 000000000000..44323e6dac03
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-m5-rtl8822cs.dtso
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-m5", "amlogic,sm1";
+
+	/* RTL8822CS SDIO WIFI */
+	fragment@0 {
+		target = <&sd_emmc_a>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	/* RTL8822CS BLUETOOTH */
+	fragment@1 {
+		target = <&uart_A>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-uartA.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-uartA.dtso
new file mode 100644
index 000000000000..ea2f401786e6
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-uartA.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-m5", "bananapi,bpi-m2-pro", "amlogic,sm1";
+
+	fragment@0 {
+		target = <&uart_A>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
+
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-uartAO_B.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-uartAO_B.dtso
new file mode 100644
index 000000000000..efac8a5140b3
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-uartAO_B.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-m5", "bananapi,bpi-m2-pro", "amlogic,sm1";
+
+	fragment@0 {
+		target = <&uart_AO_B>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-uartA_cts_rts.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-uartA_cts_rts.dtso
new file mode 100644
index 000000000000..40276d8e5f8f
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-bananapi-uartA_cts_rts.dtso
@@ -0,0 +1,17 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-m5", "bananapi,bpi-m2-pro", "amlogic,sm1";
+
+	fragment@0 {
+		target = <&uart_A>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart_a_cts_rts_pins>;
+		};
+	};
+};
+
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-jethome-jethub-j200-spi.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-jethome-jethub-j200-spi.dtso
new file mode 100644
index 000000000000..eab65a1570db
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-sm1-jethome-jethub-j200-spi.dtso
@@ -0,0 +1,19 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&sd_emmc_c>;
+		__overlay__ {
+			pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>;
+			bus-width = <4>;
+		};
+	};
+
+	fragment@1 {
+		target = <&spifc>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-uartA.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-uartA.dtso
new file mode 100644
index 000000000000..3aecd60aaf64
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-uartA.dtso
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+    compatible = "amlogic,meson-gxbb";
+    fragment@0 {
+	target-path = "/soc/bus@c1100000/serial@84c0";
+        __overlay__ {
+            status = "okay";
+        };
+    };
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-uartC.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-uartC.dtso
new file mode 100644
index 000000000000..2b40ee4c02d3
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-uartC.dtso
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+    compatible = "amlogic,meson-gxbb";
+    fragment@0 {
+	target-path = "/soc/bus@c1100000/serial@8700";
+        __overlay__ {
+            status = "okay";
+        };
+    };
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-w1-gpio.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-w1-gpio.dtso
new file mode 100644
index 000000000000..ac76a4f20ab7
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-w1-gpio.dtso
@@ -0,0 +1,20 @@
+// Definitions for w1-gpio module (without external pullup)
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "amlogic,meson-gxbb";
+
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+
+			w1: onewire@0 {
+				compatible = "w1-gpio";
+				pinctrl-names = "default";
+				gpios = <&gpio 91 6>; // GPIOY_16
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.10/overlay/meson-w1AB-gpio.dtso b/patch/kernel/archive/meson64-6.10/overlay/meson-w1AB-gpio.dtso
new file mode 100644
index 000000000000..f6b0d7eff158
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.10/overlay/meson-w1AB-gpio.dtso
@@ -0,0 +1,32 @@
+// Definitions for w1-gpio module (without external pullup)
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "amlogic,meson-gxbb";
+
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+
+			w1a: onewire@0 {
+				compatible = "w1-gpio";
+				pinctrl-names = "default";
+				gpios = <&gpio 91 6>; // GPIOY_16
+				status = "okay";
+			};
+		};
+	};
+	fragment@1 {
+		target-path = "/";
+		__overlay__ {
+
+			w1b: onewire@1 {
+				compatible = "w1-gpio";
+				pinctrl-names = "default";
+				gpios = <&gpio 90 6>; // GPIOY_15
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/meson64-6.6/dt/meson-axg-amper-gateway-am-gz80x.dts b/patch/kernel/archive/meson64-6.6/dt/meson-axg-amper-gateway-am-gz80x.dts
new file mode 100644
index 000000000000..99b4cd095218
--- /dev/null
+++ b/patch/kernel/archive/meson64-6.6/dt/meson-axg-amper-gateway-am-gz80x.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Patrick Yavitz <pyavitz@armbian.com>
+ *
+ */
+
+/dts-v1/;
+
+#include "meson-axg-jethome-jethub-j1xx.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "amper,gateway-am-gz80x", "amlogic,a113x", "amlogic,meson-axg";
+	model = "Amper Gateway AM-GZ80x";
+
+	aliases {
+		serial0 = &uart_AO;
+		serial1 = &uart_B;
+		serial2 = &uart_AO_B;
+		ethernet0 = &ethmac;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-blue {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-on";
+		};
+
+		led-green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc1";
+		};
+
+		led-red {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "usb-host";
+		};
+ 	};
+
+	/* 1024MB RAM */
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+};
+
+/delete-node/ &i2c1;
+
+/* wifi module */
+&sd_emmc_b {
+	non-removable;
+
+	rtl8189ftv: wifi@1 {
+		reg = <1>;
+	};
+};
+
+&uart_B {
+	status = "okay";
+	pinctrl-0 = <&uart_b_z_pins>;
+	pinctrl-names = "default";
+};
+
+/* UART Wireless module */
+&uart_AO_B {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_b_z_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&gpio GPIOZ_6 GPIO_ACTIVE_HIGH>;
+};
+
+&usb_pwr {
+	gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+};
diff --git a/patch/kernel/archive/mvebu-6.10/09-pci-link-retraining.patch.disabled b/patch/kernel/archive/mvebu-6.10/09-pci-link-retraining.patch.disabled
new file mode 100644
index 000000000000..e04e8e17a6ba
--- /dev/null
+++ b/patch/kernel/archive/mvebu-6.10/09-pci-link-retraining.patch.disabled
@@ -0,0 +1,219 @@
+Subject: [PATCH v3] PCI: Disallow retraining link for Atheros chips on non-Gen1 PCIe bridges
+Atheros AR9xxx and QCA9xxx chips have behaviour issues not only after a
+bus reset, but also after doing retrain link, if PCIe bridge is not in
+GEN1 mode (at 2.5 GT/s speed):
+
+- QCA9880 and QCA9890 chips throw a Link Down event and completely
+  disappear from the bus and their config space is not accessible
+  afterwards.
+
+- QCA9377 chip throws a Link Down event followed by Link Up event, the
+  config space is accessible and PCI device ID is correct. But trying to
+  access chip's I/O space causes Uncorrected (Non-Fatal) AER error,
+  followed by Synchronous external abort 96000210 and Segmentation fault
+  of insmod while loading ath10k_pci.ko module.
+
+- AR9390 chip throws a Link Down event followed by Link Up event, config
+  space is accessible, but contains nonsense values. PCI device ID is
+  0xABCD which indicates HW bug that chip itself was not able to read
+  values from internal EEPROM/OTP.
+
+- AR9287 chip throws also Link Down and Link Up events, also has
+  accessible config space containing correct values. But ath9k driver
+  fails to initialize card from this state as it is unable to access HW
+  registers. This also indicates that the chip iself is not able to read
+  values from internal EEPROM/OTP.
+
+These issues related to PCI device ID 0xABCD and to reading internal
+EEPROM/OTP were previously discussed at ath9k-devel mailing list in
+following thread:
+
+  https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html
+
+After experiments we've come up with a solution: it seems that Retrain
+link can be called only when using GEN1 PCIe bridge or when PCIe bridge
+link speed is forced to 2.5 GT/s. Applying this workaround fixes all
+mentioned cards.
+
+This issue was reproduced with more cards:
+- Compex WLE900VX (QCA9880 based / device ID 0x003c)
+- QCNFA435 (QCA9377 based / device ID 0x0042)
+- Compex WLE200NX (AR9287 based / device ID 0x002e)
+- "noname" card (QCA9890 based / device ID 0x003c)
+- Wistron NKR-DNXAH1 (AR9390 based / device ID 0x0030)
+on Armada 385 with pci-mvebu.c driver and also on Armada 3720 with
+pci-aardvark.c driver.
+
+To workaround this issue, this change introduces a new PCI quirk called
+PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1, which is enabled for all
+Atheros chips with PCI_DEV_FLAGS_NO_BUS_RESET quirk, and also for Atheros
+chip AR9287.
+
+When this quirk is set, kernel disallows triggering PCI_EXP_LNKCTL_RL
+bit in config space of PCIe Bridge in the case when PCIe Bridge is
+capable of higher speed than 2.5 GT/s and this higher speed is already
+allowed. When PCIe Bridge has accessible LNKCTL2 register, we try to
+force target link speed to 2.5 GT/s. After this change it is possible
+to trigger PCI_EXP_LNKCTL_RL bit without issues.
+
+Currently only PCIe ASPM kernel code triggers this PCI_EXP_LNKCTL_RL bit,
+so quirk check is added only into pcie/aspm.c file.
+
+Signed-off-by: Pali Rohár <pali@kernel.org>
+Reported-by: Toke Høiland-Jørgensen <toke@redhat.com>
+Tested-by: Toke Høiland-Jørgensen <toke@redhat.com>
+Tested-by: Marek Behún <kabel@kernel.org>
+BugLink: https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
+BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=84821
+BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=192441
+BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=209833
+Cc: stable@vger.kernel.org # c80851f6ce63a ("PCI: Add PCI_EXP_LNKCTL2_TLS* macros")
+
+---
+Changes since v1:
+* Move whole quirk code into pcie_downgrade_link_to_gen1() function
+* Reformat to 80 chars per line where possible
+* Add quirk also for cards with AR9287 chip (PCI ID 0x002e)
+* Extend commit message description and add information about 0xABCD
+
+Changes since v2:
+* Add quirk also for Atheros QCA9377 chip
+---
+ drivers/pci/pcie/aspm.c | 44 +++++++++++++++++++++++++++++++++++++++++
+ drivers/pci/quirks.c    | 39 ++++++++++++++++++++++++++++--------
+ include/linux/pci.h     |  2 ++
+ 3 files changed, 77 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
+index ac0557a305af..729b0389562b 100644
+--- a/drivers/pci/pcie/aspm.c
++++ b/drivers/pci/pcie/aspm.c
+@@ -192,12 +192,56 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
+ 	link->clkpm_disable = blacklist ? 1 : 0;
+ }
+ 
++static int pcie_downgrade_link_to_gen1(struct pci_dev *parent)
++{
++	u16 reg16;
++	u32 reg32;
++	int ret;
++
++	/* Check if link is capable of higher speed than 2.5 GT/s */
++	pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &reg32);
++	if ((reg32 & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
++		return 0;
++
++	/* Check if link speed can be downgraded to 2.5 GT/s */
++	pcie_capability_read_dword(parent, PCI_EXP_LNKCAP2, &reg32);
++	if (!(reg32 & PCI_EXP_LNKCAP2_SLS_2_5GB)) {
++		pci_err(parent, "ASPM: Bridge does not support changing Link Speed to 2.5 GT/s\n");
++		return -EOPNOTSUPP;
++	}
++
++	/* Force link speed to 2.5 GT/s */
++	ret = pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL2,
++						 PCI_EXP_LNKCTL2_TLS,
++						 PCI_EXP_LNKCTL2_TLS_2_5GT);
++	if (!ret) {
++		/* Verify that new value was really set */
++		pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &reg16);
++		if ((reg16 & PCI_EXP_LNKCTL2_TLS) != PCI_EXP_LNKCTL2_TLS_2_5GT)
++			ret = -EINVAL;
++	}
++
++	if (ret) {
++		pci_err(parent, "ASPM: Changing Target Link Speed to 2.5 GT/s failed: %d\n", ret);
++		return ret;
++	}
++
++	pci_info(parent, "ASPM: Target Link Speed changed to 2.5 GT/s due to quirk\n");
++	return 0;
++}
++
+ static int pcie_retrain_link(struct pcie_link_state *link)
+ {
+ 	struct pci_dev *parent = link->pdev;
+ 	int rc;
+ 	u16 reg16;
+ 
++	if ((link->downstream->dev_flags & PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1) &&
++	    pcie_downgrade_link_to_gen1(parent)) {
++		pci_err(parent, "ASPM: Retrain Link at higher speed is disallowed by quirk\n");
++		return false;
++	}
++
+ 	/*
+ 	 * Ensure the updated LNKCTL parameters are used during link
+ 	 * training by checking that there is no ongoing link training to
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index 5d2acebc3..91d675e0d 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -3572,19 +3572,46 @@ static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
+ 			 quirk_nvidia_no_bus_reset);
+ 
++
++static void quirk_no_bus_reset_and_no_retrain_link(struct pci_dev *dev)
++{
++    dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET |
++            PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1;
++}
++
+ /*
+  * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
++ * Atheros AR9xxx and QCA9xxx chips do not behave after a bus reset and also
++ * after retrain link when PCIe bridge is not in GEN1 mode at 2.5 GT/s speed.
+  * The device will throw a Link Down error on AER-capable systems and
+  * regardless of AER, config space of the device is never accessible again
+  * and typically causes the system to hang or reset when access is attempted.
++ * Or if config space is accessible again then it contains only dummy values
++ * like fixed PCI device ID 0xABCD or values not initialized at all.
++ * Retrain link can be called only when using GEN1 PCIe bridge or when
++ * PCIe bridge has forced link speed to 2.5 GT/s via PCI_EXP_LNKCTL2 register.
++ * To reset these cards it is required to do PCIe Warm Reset via PERST# pin.
+  * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
++ * https://lore.kernel.org/r/87h7l8axqp.fsf@toke.dk/
++ * https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html
+  */
+-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
+-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
+-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
+-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
+-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
+-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x002e,
++			 quirk_no_bus_reset_and_no_retrain_link);
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030,
++			 quirk_no_bus_reset_and_no_retrain_link);
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032,
++			 quirk_no_bus_reset_and_no_retrain_link);
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033,
++			 quirk_no_bus_reset_and_no_retrain_link);
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034,
++			 quirk_no_bus_reset_and_no_retrain_link);
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e,
++                        quirk_no_bus_reset_and_no_retrain_link);
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c,
++			 quirk_no_bus_reset_and_no_retrain_link);
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0042,
++			 quirk_no_bus_reset_and_no_retrain_link);
++
+ 
+ /*
+  * Root port on some Cavium CN8xxx chips do not successfully complete a bus
+diff --git a/include/linux/pci.h b/include/linux/pci.h
+index 86c799c97b77..fdbf7254e4ab 100644
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -227,6 +227,8 @@ enum pci_dev_flags {
+ 	PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
+ 	/* Device does honor MSI masking despite saying otherwise */
+ 	PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
++	/* Don't Retrain Link for device when bridge is not in GEN1 mode */
++	PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1 = (__force pci_dev_flags_t) (1 << 12),
+ };
+ 
+ enum pci_irq_reroute_variant {
+-- 
+2.20.1
diff --git a/patch/kernel/archive/mvebu-6.10/91-01-libata-add-ledtrig-support.patch.disabled b/patch/kernel/archive/mvebu-6.10/91-01-libata-add-ledtrig-support.patch.disabled
new file mode 100644
index 000000000000..983ccb75076a
--- /dev/null
+++ b/patch/kernel/archive/mvebu-6.10/91-01-libata-add-ledtrig-support.patch.disabled
@@ -0,0 +1,136 @@
+Index: 6.1__mvebu__armhf/drivers/ata/Kconfig
+===================================================================
+--- 6.1__mvebu__armhf.orig/drivers/ata/Kconfig
++++ 6.1__mvebu__armhf/drivers/ata/Kconfig
+@@ -67,6 +67,22 @@ config ATA_FORCE
+ 
+ 	  If unsure, say Y.
+ 
++config ARCH_WANT_LIBATA_LEDS
++	bool
++
++config ATA_LEDS
++	bool "support ATA port LED triggers"
++	depends on ARCH_WANT_LIBATA_LEDS
++	select NEW_LEDS
++	select LEDS_CLASS
++	select LEDS_TRIGGERS
++	default y
++	help
++	  This option adds a LED trigger for each registered ATA port.
++	  It is used to drive disk activity leds connected via GPIO.
++
++	  If unsure, say N.
++
+ config ATA_ACPI
+ 	bool "ATA ACPI Support"
+ 	depends on ACPI
+Index: 6.1__mvebu__armhf/drivers/ata/libata-core.c
+===================================================================
+--- 6.1__mvebu__armhf.orig/drivers/ata/libata-core.c
++++ 6.1__mvebu__armhf/drivers/ata/libata-core.c
+@@ -663,6 +663,19 @@ u64 ata_tf_read_block(const struct ata_t
+ 	return block;
+ }
+ 
++#ifdef CONFIG_ATA_LEDS
++#define LIBATA_BLINK_DELAY 20 /* ms */
++static inline void ata_led_act(struct ata_port *ap)
++{
++	unsigned long led_delay = LIBATA_BLINK_DELAY;
++
++	if (unlikely(!ap->ledtrig))
++		return;
++
++	led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0);
++}
++#endif
++
+ /**
+  *	ata_build_rw_tf - Build ATA taskfile for given read/write request
+  *	@qc: Metadata associated with the taskfile to build
+@@ -4813,6 +4826,10 @@ void ata_qc_issue(struct ata_queued_cmd
+ 	struct ata_link *link = qc->dev->link;
+ 	u8 prot = qc->tf.protocol;
+ 
++#ifdef CONFIG_ATA_LEDS
++	ata_led_act(ap);
++#endif
++
+ 	/* Make sure only one non-NCQ command is outstanding. */
+	WARN_ON_ONCE(ata_tag_valid(link->active_tag));
+
+@@ -5328,6 +5345,9 @@ struct ata_port *ata_port_alloc(struct a
+ 	ap->stats.unhandled_irq = 1;
+ 	ap->stats.idle_irq = 1;
+ #endif
++#ifdef CONFIG_ATA_LEDS
++	ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL);
++#endif
+ 	ata_sff_port_init(ap);
+ 
+ 	return ap;
+@@ -5363,6 +5383,12 @@ static void ata_host_release(struct kref
+ 
+		kfree(ap->slave_link);
+		kfree(ap->ncq_sense_buf);
++#ifdef CONFIG_ATA_LEDS
++		if (ap->ledtrig) {
++			led_trigger_unregister(ap->ledtrig);
++			kfree(ap->ledtrig);
++		};
++#endif
+ 		kfree(ap);
+ 		host->ports[i] = NULL;
+ 	}
+@@ -5765,7 +5791,23 @@ int ata_host_register(struct ata_host *h
+ 		host->ports[i]->print_id = atomic_inc_return(&ata_print_id);
+ 		host->ports[i]->local_port_no = i + 1;
+ 	}
++#ifdef CONFIG_ATA_LEDS
++	for (i = 0; i < host->n_ports; i++) {
++		if (unlikely(!host->ports[i]->ledtrig))
++			continue;
+ 
++		snprintf(host->ports[i]->ledtrig_name,
++			sizeof(host->ports[i]->ledtrig_name), "ata%u",
++			host->ports[i]->print_id);
++
++		host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name;
++
++		if (led_trigger_register(host->ports[i]->ledtrig)) {
++			kfree(host->ports[i]->ledtrig);
++			host->ports[i]->ledtrig = NULL;
++		}
++	}
++#endif
+ 	/* Create associated sysfs transport objects  */
+ 	for (i = 0; i < host->n_ports; i++) {
+ 		rc = ata_tport_add(host->dev,host->ports[i]);
+Index: 6.1__mvebu__armhf/include/linux/libata.h
+===================================================================
+--- 6.1__mvebu__armhf.orig/include/linux/libata.h
++++ 6.1__mvebu__armhf/include/linux/libata.h
+@@ -23,6 +23,9 @@
+ #include <linux/cdrom.h>
+ #include <linux/sched.h>
+ #include <linux/async.h>
++#ifdef CONFIG_ATA_LEDS
++#include <linux/leds.h>
++#endif
+ 
+ /*
+  * Define if arch has non-standard setup.  This is a _PCI_ standard
+@@ -857,6 +860,12 @@ struct ata_port {
+ #ifdef CONFIG_ATA_ACPI
+ 	struct ata_acpi_gtm	__acpi_init_gtm; /* use ata_acpi_init_gtm() */
+ #endif
++
++#ifdef CONFIG_ATA_LEDS
++	struct led_trigger	*ledtrig;
++	char			ledtrig_name[8];
++#endif
++
+ 	/* owned by EH */
+ 	u8			sector_buf[ATA_SECT_SIZE] ____cacheline_aligned;
+ };
diff --git a/patch/kernel/archive/mvebu-6.10/91-02-Enable-ATA-port-LED-trigger.patch.disabled b/patch/kernel/archive/mvebu-6.10/91-02-Enable-ATA-port-LED-trigger.patch.disabled
new file mode 100644
index 000000000000..10680f98cb84
--- /dev/null
+++ b/patch/kernel/archive/mvebu-6.10/91-02-Enable-ATA-port-LED-trigger.patch.disabled
@@ -0,0 +1,30 @@
+From 9ee6345ef82f7af5f98e17a40e667f8ad6b2fa1b Mon Sep 17 00:00:00 2001
+From: aprayoga <adit.prayoga@gmail.com>
+Date: Sun, 3 Sep 2017 18:10:12 +0800
+Subject: Enable ATA port LED trigger
+
+---
+ arch/arm/configs/mvebu_v7_defconfig | 1 +
+ arch/arm/mach-mvebu/Kconfig         | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/arch/arm/configs/mvebu_v7_defconfig
++++ b/arch/arm/configs/mvebu_v7_defconfig
+@@ -58,6 +58,7 @@ CONFIG_MTD_UBI=y
+ CONFIG_EEPROM_AT24=y
+ CONFIG_BLK_DEV_SD=y
+ CONFIG_ATA=y
++CONFIG_ATA_LEDS=y
+ CONFIG_SATA_AHCI=y
+ CONFIG_AHCI_MVEBU=y
+ CONFIG_SATA_MV=y
+--- a/arch/arm/mach-mvebu/Kconfig
++++ b/arch/arm/mach-mvebu/Kconfig
+@@ -56,6 +56,7 @@ config MACH_ARMADA_375
+ config MACH_ARMADA_38X
+ 	bool "Marvell Armada 380/385 boards"
+ 	depends on ARCH_MULTI_V7
++	select ARCH_WANT_LIBATA_LEDS
+ 	select ARM_ERRATA_720789
+ 	select PL310_ERRATA_753970
+ 	select ARM_GIC
diff --git a/patch/kernel/archive/mvebu-6.10/92-mvebu-gpio-add_wake_on_gpio_support.patch b/patch/kernel/archive/mvebu-6.10/92-mvebu-gpio-add_wake_on_gpio_support.patch
new file mode 100644
index 000000000000..9274f2b1a1d7
--- /dev/null
+++ b/patch/kernel/archive/mvebu-6.10/92-mvebu-gpio-add_wake_on_gpio_support.patch
@@ -0,0 +1,88 @@
+--- a/drivers/gpio/gpio-mvebu.c
++++ b/drivers/gpio/gpio-mvebu.c
+@@ -40,6 +40,7 @@
+ #include <linux/gpio/consumer.h>
+ #include <linux/gpio/machine.h>
+ #include <linux/init.h>
++#include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
+ #include <linux/irqchip/chained_irq.h>
+@@ -111,7 +112,7 @@ struct mvebu_gpio_chip {
+ 	struct regmap     *regs;
+ 	u32		   offset;
+ 	struct regmap     *percpu_regs;
+-	int		   irqbase;
++	int		   bank_irq[4];
+ 	struct irq_domain *domain;
+ 	int		   soc_variant;
+ 
+@@ -601,6 +602,33 @@ static void mvebu_gpio_irq_handler(struc
+ }
+ 
+ /*
++ * Set interrupt number "irq" in the GPIO as a wake-up source.
++ * While system is running, all registered GPIO interrupts need to have
++ * wake-up enabled. When system is suspended, only selected GPIO interrupts
++ * need to have wake-up enabled.
++ * @param  irq          interrupt source number
++ * @param  enable       enable as wake-up if equal to non-zero
++ * @return       This function returns 0 on success.
++ */
++static int mvebu_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
++{
++	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
++	struct mvebu_gpio_chip *mvchip = gc->private;
++	int irq;
++	int bank;
++
++	bank = d->hwirq % 8;
++	irq = mvchip->bank_irq[bank];
++
++	if (enable)
++		enable_irq_wake(irq);
++	else
++		disable_irq_wake(irq);
++
++	return 0;
++}
++
++/*
+  * Functions implementing the pwm_chip methods
+  */
+ static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
+@@ -1219,7 +1247,7 @@ static int mvebu_gpio_probe(struct platf
+ 
+ 	err = irq_alloc_domain_generic_chips(
+ 	    mvchip->domain, ngpios, 2, np->name, handle_level_irq,
+-	    IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
++	    IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, IRQ_GC_INIT_NESTED_LOCK);
+ 	if (err) {
+ 		dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
+ 			mvchip->chip.label);
+@@ -1237,6 +1265,8 @@ static int mvebu_gpio_probe(struct platf
+ 	ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
+ 	ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
+ 	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
++	ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
++	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
+ 	ct->chip.name = mvchip->chip.label;
+ 
+ 	ct = &gc->chip_types[1];
+@@ -1245,6 +1275,8 @@ static int mvebu_gpio_probe(struct platf
+ 	ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
+ 	ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
+ 	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
++	ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
++	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
+ 	ct->handler = handle_edge_irq;
+ 	ct->chip.name = mvchip->chip.label;
+ 
+@@ -1260,6 +1292,7 @@ static int mvebu_gpio_probe(struct platf
+ 			continue;
+ 		irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
+ 						 mvchip);
++		mvchip->bank_irq[i] = irq;
+ 	}
+ 
+ 	return 0;
diff --git a/patch/kernel/archive/mvebu-6.10/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch.disabled b/patch/kernel/archive/mvebu-6.10/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch.disabled
new file mode 100644
index 000000000000..c0cb9d68f96b
--- /dev/null
+++ b/patch/kernel/archive/mvebu-6.10/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch.disabled
@@ -0,0 +1,411 @@
+Removes the hardcoded timer assignment of timers to pwm controllers.
+This allows to use more than one pwm per gpio bank.
+
+Original patch with chip_data interface by Heisath <jannis@imserv.org>
+
+Link: https://wiki.kobol.io/helios4/pwm/#patch-requirement
+Co-developed-by: Yureka Lilian <yuka@yuka.dev>
+Signed-off-by: Yureka Lilian <yuka@yuka.dev>
+Signed-off-by: Finn Behrens <me@kloenk.de>
+---
+ drivers/gpio/gpio-mvebu.c | 223 ++++++++++++++++++++++++--------------
+ 1 file changed, 139 insertions(+), 84 deletions(-)
+
+diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
+index a13f3c18ccd4..303ea3be0b69 100644
+--- a/drivers/gpio/gpio-mvebu.c
++++ b/drivers/gpio/gpio-mvebu.c
+@@ -94,21 +94,43 @@
+ 
+ #define MVEBU_MAX_GPIO_PER_BANK		32
+ 
+-struct mvebu_pwm {
++enum mvebu_pwm_ctrl {
++	MVEBU_PWM_CTRL_SET_A = 0,
++	MVEBU_PWM_CTRL_SET_B,
++	MVEBU_PWM_CTRL_MAX
++};
++
++struct mvebu_pwmchip {
+ 	struct regmap		*regs;
+ 	u32			 offset;
+ 	unsigned long		 clk_rate;
+-	struct gpio_desc	*gpiod;
+-	struct pwm_chip		 chip;
+ 	spinlock_t		 lock;
+-	struct mvebu_gpio_chip	*mvchip;
++	bool			 in_use;
+ 
+ 	/* Used to preserve GPIO/PWM registers across suspend/resume */
+-	u32			 blink_select;
+ 	u32			 blink_on_duration;
+ 	u32			 blink_off_duration;
+ };
+ 
++struct mvebu_pwm_chip_drv {
++	enum mvebu_pwm_ctrl	 ctrl;
++	struct gpio_desc	*gpiod;
++	bool			 master;
++};
++
++struct mvebu_pwm {
++	struct pwm_chip		 chip;
++	struct mvebu_gpio_chip	*mvchip;
++	struct mvebu_pwmchip	 controller;
++	enum mvebu_pwm_ctrl	 default_controller;
++
++	/* Used to preserve GPIO/PWM registers across suspend/resume */
++	u32				 blink_select;
++	struct mvebu_pwm_chip_drv	 drv[];
++};
++
++static struct mvebu_pwmchip  *mvebu_pwm_list[MVEBU_PWM_CTRL_MAX];
++
+ struct mvebu_gpio_chip {
+ 	struct gpio_chip   chip;
+ 	struct regmap     *regs;
+@@ -285,12 +307,12 @@ mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
+  * Functions returning offsets of individual registers for a given
+  * PWM controller.
+  */
+-static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
++static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwmchip *mvpwm)
+ {
+ 	return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
+ }
+ 
+-static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
++static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwmchip *mvpwm)
+ {
+ 	return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
+ }
+@@ -623,39 +645,71 @@ static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+ 	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
+ 	struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
+ 	struct gpio_desc *desc;
++	enum mvebu_pwm_ctrl id;
+ 	unsigned long flags;
+ 	int ret = 0;
++	struct mvebu_pwm_chip_drv *drv = &mvpwm->drv[pwm->hwpwm];
+ 
+-	spin_lock_irqsave(&mvpwm->lock, flags);
++	spin_lock_irqsave(&mvpwm->controller.lock, flags);
+ 
+-	if (mvpwm->gpiod) {
++	if (drv->gpiod || (mvchip->blink_en_reg & BIT(pwm->hwpwm))) {
+ 		ret = -EBUSY;
+-	} else {
+-		desc = gpiochip_request_own_desc(&mvchip->chip,
+-						 pwm->hwpwm, "mvebu-pwm",
+-						 GPIO_ACTIVE_HIGH,
+-						 GPIOD_OUT_LOW);
+-		if (IS_ERR(desc)) {
+-			ret = PTR_ERR(desc);
+-			goto out;
+-		}
++		goto out;
++	}
++
++	desc = gpiochip_request_own_desc(&mvchip->chip,
++					 pwm->hwpwm, "mvebu-pwm",
++					 GPIO_ACTIVE_HIGH,
++					 GPIOD_OUT_LOW);
++	if (IS_ERR(desc)) {
++		ret = PTR_ERR(desc);
++		goto out;
++	}
+ 
+-		mvpwm->gpiod = desc;
++	ret = gpiod_direction_output(desc, 0);
++	if (ret) {
++		gpiochip_free_own_desc(desc);
++		goto out;
+ 	}
++
++	for (id = MVEBU_PWM_CTRL_SET_A; id < MVEBU_PWM_CTRL_MAX; id++) {
++		if (!mvebu_pwm_list[id]->in_use) {
++			drv->ctrl = id;
++			drv->master = true;
++			mvebu_pwm_list[id]->in_use = true;
++			break;
++		}
++	}
++
++	if (!drv->master)
++		drv->ctrl = mvpwm->default_controller;
++
++	regmap_update_bits(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
++			   BIT(pwm->hwpwm), drv->ctrl ? BIT(pwm->hwpwm) : 0);
++
++	drv->gpiod = desc;
++
++	regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
++		    &mvpwm->blink_select);
+ out:
+-	spin_unlock_irqrestore(&mvpwm->lock, flags);
++	spin_unlock_irqrestore(&mvpwm->controller.lock, flags);
+ 	return ret;
+ }
+ 
+ static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
+ {
+ 	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
++	struct mvebu_pwm_chip_drv *drv = &mvpwm->drv[pwm->hwpwm];
+ 	unsigned long flags;
+ 
+-	spin_lock_irqsave(&mvpwm->lock, flags);
+-	gpiochip_free_own_desc(mvpwm->gpiod);
+-	mvpwm->gpiod = NULL;
+-	spin_unlock_irqrestore(&mvpwm->lock, flags);
++	spin_lock_irqsave(&mvpwm->controller.lock, flags);
++	if (drv->master)
++		mvebu_pwm_list[drv->ctrl]->in_use = false;
++
++	gpiochip_free_own_desc(drv->gpiod);
++	memset(drv, 0, sizeof(struct mvebu_pwm_chip_drv));
++
++	spin_unlock_irqrestore(&mvpwm->controller.lock, flags);
+ }
+ 
+ static int mvebu_pwm_get_state(struct pwm_chip *chip,
+@@ -665,28 +719,35 @@ static int mvebu_pwm_get_state(struct pwm_chip *chip,
+ 
+ 	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
+ 	struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
++	struct mvebu_pwm_chip_drv *drv = &mvpwm->drv[pwm->hwpwm];
++	struct mvebu_pwmchip *controller;
+ 	unsigned long long val;
+ 	unsigned long flags;
+ 	u32 u;
+ 
+-	spin_lock_irqsave(&mvpwm->lock, flags);
++	if (drv->gpiod)
++		controller = mvebu_pwm_list[drv->ctrl];
++	else
++		controller = &mvpwm->controller;
++
++	spin_lock_irqsave(&controller->lock, flags);
+ 
+-	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
++	regmap_read(controller->regs, mvebu_pwmreg_blink_on_duration(controller), &u);
+ 	/* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */
+ 	if (u > 0)
+ 		val = u;
+ 	else
+ 		val = UINT_MAX + 1ULL;
+ 	state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC,
+-			mvpwm->clk_rate);
++			controller->clk_rate);
+ 
+-	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
++	regmap_read(controller->regs, mvebu_pwmreg_blink_off_duration(controller), &u);
+ 	/* period = on + off duration */
+ 	if (u > 0)
+ 		val += u;
+ 	else
+ 		val += UINT_MAX + 1ULL;
+-	state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
++	state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, controller->clk_rate);
+ 
+ 	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
+ 	if (u)
+@@ -694,7 +755,7 @@ static int mvebu_pwm_get_state(struct pwm_chip *chip,
+ 	else
+ 		state->enabled = false;
+ 
+-	spin_unlock_irqrestore(&mvpwm->lock, flags);
++	spin_unlock_irqrestore(&controller->lock, flags);
+ 
+ 	return 0;
+ }
+@@ -703,6 +764,8 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ 			   const struct pwm_state *state)
+ {
+ 	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
++	struct mvebu_pwm_chip_drv *drv = &mvpwm->drv[pwm->hwpwm];
++	struct mvebu_pwmchip *controller;
+ 	struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
+ 	unsigned long long val;
+ 	unsigned long flags;
+@@ -711,7 +774,11 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ 	if (state->polarity != PWM_POLARITY_NORMAL)
+ 		return -EINVAL;
+ 
+-	val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
++	if (drv->gpiod)
++		controller = mvebu_pwm_list[drv->ctrl];
++	else
++		controller = &mvpwm->controller;
++	val = (unsigned long long) controller->clk_rate * state->duty_cycle;
+ 	do_div(val, NSEC_PER_SEC);
+ 	if (val > UINT_MAX + 1ULL)
+ 		return -EINVAL;
+@@ -726,7 +793,7 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ 	else
+ 		on = 1;
+ 
+-	val = (unsigned long long) mvpwm->clk_rate * state->period;
++	val = (unsigned long long) controller->clk_rate * state->period;
+ 	do_div(val, NSEC_PER_SEC);
+ 	val -= on;
+ 	if (val > UINT_MAX + 1ULL)
+@@ -738,16 +805,16 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ 	else
+ 		off = 1;
+ 
+-	spin_lock_irqsave(&mvpwm->lock, flags);
++	spin_lock_irqsave(&controller->lock, flags);
+ 
+-	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on);
+-	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off);
++	regmap_write(controller->regs, mvebu_pwmreg_blink_on_duration(controller), on);
++	regmap_write(controller->regs, mvebu_pwmreg_blink_off_duration(controller), off);
+ 	if (state->enabled)
+ 		mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
+ 	else
+ 		mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
+ 
+-	spin_unlock_irqrestore(&mvpwm->lock, flags);
++	spin_unlock_irqrestore(&controller->lock, flags);
+ 
+ 	return 0;
+ }
+@@ -762,25 +829,27 @@ static const struct pwm_ops mvebu_pwm_ops = {
+ static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
+ {
+ 	struct mvebu_pwm *mvpwm = mvchip->mvpwm;
++	struct mvebu_pwmchip *controller = &mvpwm->controller;
+ 
+ 	regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
+ 		    &mvpwm->blink_select);
+-	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
+-		    &mvpwm->blink_on_duration);
+-	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
+-		    &mvpwm->blink_off_duration);
++	regmap_read(controller->regs, mvebu_pwmreg_blink_on_duration(controller),
++		    &controller->blink_on_duration);
++	regmap_read(controller->regs, mvebu_pwmreg_blink_off_duration(controller),
++		    &controller->blink_off_duration);
+ }
+ 
+ static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
+ {
+ 	struct mvebu_pwm *mvpwm = mvchip->mvpwm;
++	struct mvebu_pwmchip *controller = &mvpwm->controller;
+ 
+ 	regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
+ 		     mvpwm->blink_select);
+-	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
+-		     mvpwm->blink_on_duration);
+-	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
+-		     mvpwm->blink_off_duration);
++	regmap_write(controller->regs, mvebu_pwmreg_blink_on_duration(controller),
++		     controller->blink_on_duration);
++	regmap_write(controller->regs, mvebu_pwmreg_blink_off_duration(controller),
++		     controller->blink_off_duration);
+ }
+ 
+ static int mvebu_pwm_probe(struct platform_device *pdev,
+@@ -792,6 +861,7 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
+ 	void __iomem *base;
+ 	u32 offset;
+ 	u32 set;
++	enum mvebu_pwm_ctrl ctrl_set;
+ 
+ 	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
+ 		int ret = of_property_read_u32(dev->of_node,
+@@ -813,57 +883,39 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
+ 	if (IS_ERR(mvchip->clk))
+ 		return PTR_ERR(mvchip->clk);
+ 
+-	mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
++	mvpwm = devm_kzalloc(dev, struct_size(mvpwm, drv, mvchip->chip.ngpio), GFP_KERNEL);
+ 	if (!mvpwm)
+ 		return -ENOMEM;
+ 	mvchip->mvpwm = mvpwm;
+ 	mvpwm->mvchip = mvchip;
+-	mvpwm->offset = offset;
+ 
+-	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
+-		mvpwm->regs = mvchip->regs;
++	base = devm_platform_ioremap_resource_byname(pdev, "pwm");
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++	mvpwm->controller.regs = devm_regmap_init_mmio(&pdev->dev, base,
++						       &mvebu_gpio_regmap_config);
++	if (IS_ERR(mvpwm->controller.regs))
++		return PTR_ERR(mvpwm->controller.regs);
+ 
+-		switch (mvchip->offset) {
+-		case AP80X_GPIO0_OFF_A8K:
+-		case CP11X_GPIO0_OFF_A8K:
+-			/* Blink counter A */
+-			set = 0;
+-			break;
+-		case CP11X_GPIO1_OFF_A8K:
+-			/* Blink counter B */
+-			set = U32_MAX;
+-			mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
+-			break;
+-		default:
+-			return -EINVAL;
+-		}
++	/*
++	 * User set A for lines of GPIO chip with id 0, B for GPIO chip
++	 * with id 1. Don't allow further GPIO chips to be used for PWM.
++	 */
++	if (id == 0) {
++		set = 0;
++		ctrl_set = MVEBU_PWM_CTRL_SET_A;
++	} else if (id == 1) {
++		set = U32_MAX;
++		ctrl_set = MVEBU_PWM_CTRL_SET_B;
+ 	} else {
+-		base = devm_platform_ioremap_resource_byname(pdev, "pwm");
+-		if (IS_ERR(base))
+-			return PTR_ERR(base);
+-
+-		mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
+-						    &mvebu_gpio_regmap_config);
+-		if (IS_ERR(mvpwm->regs))
+-			return PTR_ERR(mvpwm->regs);
+-
+-		/*
+-		 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
+-		 * with id 1. Don't allow further GPIO chips to be used for PWM.
+-		 */
+-		if (id == 0)
+-			set = 0;
+-		else if (id == 1)
+-			set = U32_MAX;
+-		else
+-			return -EINVAL;
++		return -EINVAL;
+ 	}
+ 
+ 	regmap_write(mvchip->regs,
+ 		     GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
+ 
+-	mvpwm->clk_rate = clk_get_rate(mvchip->clk);
+-	if (!mvpwm->clk_rate) {
++	mvpwm->controller.clk_rate = clk_get_rate(mvchip->clk);
++	if (!mvpwm->controller.clk_rate) {
+ 		dev_err(dev, "failed to get clock rate\n");
+ 		return -EINVAL;
+ 	}
+@@ -872,7 +924,10 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
+ 	mvpwm->chip.ops = &mvebu_pwm_ops;
+ 	mvpwm->chip.npwm = mvchip->chip.ngpio;
+ 
+-	spin_lock_init(&mvpwm->lock);
++	spin_lock_init(&mvpwm->controller.lock);
++
++	mvpwm->default_controller = ctrl_set;
++	mvebu_pwm_list[ctrl_set] = &mvpwm->controller;
+ 
+ 	return devm_pwmchip_add(dev, &mvpwm->chip);
+ }
+-- 
+2.43.0
+
+
diff --git a/patch/kernel/archive/mvebu-6.10/94-helios4-dts-add-wake-on-lan-support.patch b/patch/kernel/archive/mvebu-6.10/94-helios4-dts-add-wake-on-lan-support.patch
new file mode 100644
index 000000000000..2b75913fda46
--- /dev/null
+++ b/patch/kernel/archive/mvebu-6.10/94-helios4-dts-add-wake-on-lan-support.patch
@@ -0,0 +1,21 @@
+--- a/arch/arm/boot/dts/marvell/armada-388-helios4.dts
++++ b/arch/arm/boot/dts/marvell/armada-388-helios4.dts
+@@ -84,6 +84,18 @@
+ 		};
+ 	};
+ 
++	gpio-keys {
++		compatible = "gpio-keys";
++		pinctrl-0 = <&microsom_phy0_int_pins>;
++
++		wol {
++			label = "Wake-On-LAN";
++			linux,code = <KEY_WAKEUP>;
++			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
++			wakeup-source;
++		};
++	};
++
+ 	io-leds {
+ 		compatible = "gpio-leds";
+ 		sata1-led {
diff --git a/patch/kernel/archive/mvebu-6.10/compile-dtb-with-symbol-support.patch b/patch/kernel/archive/mvebu-6.10/compile-dtb-with-symbol-support.patch
new file mode 100644
index 000000000000..a2bd279ae41a
--- /dev/null
+++ b/patch/kernel/archive/mvebu-6.10/compile-dtb-with-symbol-support.patch
@@ -0,0 +1,12 @@
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -277,6 +277,9 @@ quiet_cmd_gzip = GZIP    $@
+ DTC ?= $(objtree)/scripts/dtc/dtc
+ DTC_FLAGS += -Wno-interrupt_provider
+ 
++# Enable overlay support
++DTC_FLAGS += -@
++
+ # Disable noisy checks by default
+ ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),)
+ DTC_FLAGS += -Wno-unit_address_vs_reg \
diff --git a/patch/kernel/archive/mvebu-6.10/dts-disable-spi-flash-on-a388-microsom.patch b/patch/kernel/archive/mvebu-6.10/dts-disable-spi-flash-on-a388-microsom.patch
new file mode 100644
index 000000000000..db5c77e0f006
--- /dev/null
+++ b/patch/kernel/archive/mvebu-6.10/dts-disable-spi-flash-on-a388-microsom.patch
@@ -0,0 +1,10 @@
+--- a/arch/arm/boot/dts/marvell/armada-38x-solidrun-microsom.dtsi
++++ b/arch/arm/boot/dts/marvell/armada-38x-solidrun-microsom.dtsi
+@@ -107,6 +107,7 @@
+ 		compatible = "w25q32", "jedec,spi-nor";
+ 		reg = <0>; /* Chip select 0 */
+ 		spi-max-frequency = <3000000>;
++		status = "disabled";
+ 	};
+ };
+ 
diff --git a/patch/kernel/archive/mvebu-6.10/general-increasing_DMA_block_memory_allocation_to_2048.patch b/patch/kernel/archive/mvebu-6.10/general-increasing_DMA_block_memory_allocation_to_2048.patch
new file mode 100644
index 000000000000..eef7296e75df
--- /dev/null
+++ b/patch/kernel/archive/mvebu-6.10/general-increasing_DMA_block_memory_allocation_to_2048.patch
@@ -0,0 +1,11 @@
+--- a/arch/arm/mm/dma-mapping.c
++++ b/arch/arm/mm/dma-mapping.c
+@@ -315,7 +315,7 @@ static void *__alloc_remap_buffer(struct
+ 				 pgprot_t prot, struct page **ret_page,
+ 				 const void *caller, bool want_vaddr);
+ 
+-#define DEFAULT_DMA_COHERENT_POOL_SIZE	SZ_256K
++#define DEFAULT_DMA_COHERENT_POOL_SIZE	SZ_2M
+ static struct gen_pool *atomic_pool __ro_after_init;
+ 
+ static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
diff --git a/patch/kernel/archive/mvebu-6.10/unlock_atheros_regulatory_restrictions.patch b/patch/kernel/archive/mvebu-6.10/unlock_atheros_regulatory_restrictions.patch
new file mode 100644
index 000000000000..7e57c379ad88
--- /dev/null
+++ b/patch/kernel/archive/mvebu-6.10/unlock_atheros_regulatory_restrictions.patch
@@ -0,0 +1,70 @@
+--- a/drivers/net/wireless/ath/regd.c
++++ b/drivers/net/wireless/ath/regd.c
+@@ -50,12 +50,9 @@ static int __ath_regd_init(struct ath_re
+ #define ATH_5GHZ_5725_5850	REG_RULE(5725-10, 5850+10, 80, 0, 30,\
+ 					 NL80211_RRF_NO_IR)
+ 
+-#define ATH_2GHZ_ALL		ATH_2GHZ_CH01_11, \
+-				ATH_2GHZ_CH12_13, \
+-				ATH_2GHZ_CH14
++#define ATH_2GHZ_ALL     REG_RULE(2400, 2483, 40, 0, 30, 0)
+ 
+-#define ATH_5GHZ_ALL		ATH_5GHZ_5150_5350, \
+-				ATH_5GHZ_5470_5850
++#define ATH_5GHZ_ALL     REG_RULE(5140, 5860, 40, 0, 30, 0)
+ 
+ /* This one skips what we call "mid band" */
+ #define ATH_5GHZ_NO_MIDBAND	ATH_5GHZ_5150_5350, \
+@@ -77,9 +74,8 @@ static const struct ieee80211_regdomain
+ 	.n_reg_rules = 4,
+ 	.alpha2 =  "99",
+ 	.reg_rules = {
+-		ATH_2GHZ_CH01_11,
+-		ATH_2GHZ_CH12_13,
+-		ATH_5GHZ_NO_MIDBAND,
++		ATH_2GHZ_ALL,
++		ATH_5GHZ_ALL,
+ 	}
+ };
+ 
+@@ -88,8 +84,8 @@ static const struct ieee80211_regdomain
+ 	.n_reg_rules = 3,
+ 	.alpha2 =  "99",
+ 	.reg_rules = {
+-		ATH_2GHZ_CH01_11,
+-		ATH_5GHZ_NO_MIDBAND,
++		ATH_2GHZ_ALL,
++		ATH_5GHZ_ALL,
+ 	}
+ };
+ 
+@@ -98,7 +94,7 @@ static const struct ieee80211_regdomain
+ 	.n_reg_rules = 3,
+ 	.alpha2 =  "99",
+ 	.reg_rules = {
+-		ATH_2GHZ_CH01_11,
++		ATH_2GHZ_ALL,
+ 		ATH_5GHZ_ALL,
+ 	}
+ };
+@@ -108,8 +104,7 @@ static const struct ieee80211_regdomain
+ 	.n_reg_rules = 4,
+ 	.alpha2 =  "99",
+ 	.reg_rules = {
+-		ATH_2GHZ_CH01_11,
+-		ATH_2GHZ_CH12_13,
++		ATH_2GHZ_ALL,
+ 		ATH_5GHZ_ALL,
+ 	}
+ };
+@@ -258,9 +253,7 @@ static bool ath_is_radar_freq(u16 center
+ 			      struct ath_regulatory *reg)
+ 
+ {
+-	if (reg->country_code == CTRY_INDIA)
+-		return (center_freq >= 5500 && center_freq <= 5700);
+-	return (center_freq >= 5260 && center_freq <= 5700);
++	return false;
+ }
+ 
+ static void ath_force_clear_no_ir_chan(struct wiphy *wiphy,
diff --git a/patch/kernel/archive/odroidxu4-6.6/patch-6.6.44-45.patch b/patch/kernel/archive/odroidxu4-6.6/patch-6.6.44-45.patch
new file mode 100644
index 000000000000..95da970d54ec
--- /dev/null
+++ b/patch/kernel/archive/odroidxu4-6.6/patch-6.6.44-45.patch
@@ -0,0 +1,5821 @@
+diff --git a/Makefile b/Makefile
+index 2e5d92ce2774d..0bd4bee2128b4 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1,7 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ VERSION = 6
+ PATCHLEVEL = 6
+-SUBLEVEL = 44
++SUBLEVEL = 45
+ EXTRAVERSION =
+ NAME = Hurr durr I'ma ninja sloth
+ 
+diff --git a/arch/arm/kernel/perf_callchain.c b/arch/arm/kernel/perf_callchain.c
+index 7147edbe56c67..1d230ac9d0eb5 100644
+--- a/arch/arm/kernel/perf_callchain.c
++++ b/arch/arm/kernel/perf_callchain.c
+@@ -85,8 +85,7 @@ static bool
+ callchain_trace(void *data, unsigned long pc)
+ {
+ 	struct perf_callchain_entry_ctx *entry = data;
+-	perf_callchain_store(entry, pc);
+-	return true;
++	return perf_callchain_store(entry, pc) == 0;
+ }
+ 
+ void
+diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+index 5effd8180cc41..e5993a365870c 100644
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -641,6 +641,7 @@ dwc_0: usb@8a00000 {
+ 				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ 				phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ 				phy-names = "usb2-phy", "usb3-phy";
++				snps,parkmode-disable-ss-quirk;
+ 				snps,is-utmi-l1-suspend;
+ 				snps,hird-threshold = /bits/ 8 <0x0>;
+ 				snps,dis_u2_susphy_quirk;
+@@ -683,6 +684,7 @@ dwc_1: usb@8c00000 {
+ 				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ 				phys = <&qusb_phy_1>, <&usb1_ssphy>;
+ 				phy-names = "usb2-phy", "usb3-phy";
++				snps,parkmode-disable-ss-quirk;
+ 				snps,is-utmi-l1-suspend;
+ 				snps,hird-threshold = /bits/ 8 <0x0>;
+ 				snps,dis_u2_susphy_quirk;
+diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
+index 9c072ce197358..7fcc15b6946ae 100644
+--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
++++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
+@@ -2159,7 +2159,8 @@ usb3_dwc3: usb@a800000 {
+ 				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ 				snps,dis_u2_susphy_quirk;
+ 				snps,dis_enblslpm_quirk;
+-				phys = <&qusb2phy>, <&usb1_ssphy>;
++				snps,parkmode-disable-ss-quirk;
++				phys = <&qusb2phy>, <&usb3phy>;
+ 				phy-names = "usb2-phy", "usb3-phy";
+ 				snps,has-lpm-erratum;
+ 				snps,hird-threshold = /bits/ 8 <0x10>;
+@@ -2168,33 +2169,26 @@ usb3_dwc3: usb@a800000 {
+ 
+ 		usb3phy: phy@c010000 {
+ 			compatible = "qcom,msm8998-qmp-usb3-phy";
+-			reg = <0x0c010000 0x18c>;
+-			status = "disabled";
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+-			ranges;
++			reg = <0x0c010000 0x1000>;
+ 
+ 			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
++				 <&gcc GCC_USB3_CLKREF_CLK>,
+ 				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+-				 <&gcc GCC_USB3_CLKREF_CLK>;
+-			clock-names = "aux", "cfg_ahb", "ref";
++				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
++			clock-names = "aux",
++				      "ref",
++				      "cfg_ahb",
++				      "pipe";
++			clock-output-names = "usb3_phy_pipe_clk_src";
++			#clock-cells = <0>;
++			#phy-cells = <0>;
+ 
+ 			resets = <&gcc GCC_USB3_PHY_BCR>,
+ 				 <&gcc GCC_USB3PHY_PHY_BCR>;
+-			reset-names = "phy", "common";
++			reset-names = "phy",
++				      "phy_phy";
+ 
+-			usb1_ssphy: phy@c010200 {
+-				reg = <0xc010200 0x128>,
+-				      <0xc010400 0x200>,
+-				      <0xc010c00 0x20c>,
+-				      <0xc010600 0x128>,
+-				      <0xc010800 0x200>;
+-				#phy-cells = <0>;
+-				#clock-cells = <0>;
+-				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+-				clock-names = "pipe0";
+-				clock-output-names = "usb3_phy_pipe_clk_src";
+-			};
++			status = "disabled";
+ 		};
+ 
+ 		qusb2phy: phy@c012000 {
+diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
+index f7c528ecb224b..68b1c017a9fd5 100644
+--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
++++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
+@@ -15,6 +15,7 @@
+ #include <dt-bindings/interconnect/qcom,osm-l3.h>
+ #include <dt-bindings/interconnect/qcom,sc7180.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/phy/phy-qcom-qmp.h>
+ #include <dt-bindings/phy/phy-qcom-qusb2.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+ #include <dt-bindings/reset/qcom,sdm845-aoss.h>
+@@ -2795,49 +2796,28 @@ usb_1_hsphy: phy@88e3000 {
+ 			nvmem-cells = <&qusb2p_hstx_trim>;
+ 		};
+ 
+-		usb_1_qmpphy: phy-wrapper@88e9000 {
++		usb_1_qmpphy: phy@88e8000 {
+ 			compatible = "qcom,sc7180-qmp-usb3-dp-phy";
+-			reg = <0 0x088e9000 0 0x18c>,
+-			      <0 0x088e8000 0 0x3c>,
+-			      <0 0x088ea000 0 0x18c>;
++			reg = <0 0x088e8000 0 0x3000>;
+ 			status = "disabled";
+-			#address-cells = <2>;
+-			#size-cells = <2>;
+-			ranges;
+ 
+ 			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+-				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ 				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+-				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+-			clock-names = "aux", "cfg_ahb", "ref", "com_aux";
++				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
++				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
++				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
++			clock-names = "aux",
++				      "ref",
++				      "com_aux",
++				      "usb3_pipe",
++				      "cfg_ahb";
+ 
+ 			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ 				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ 			reset-names = "phy", "common";
+ 
+-			usb_1_ssphy: usb3-phy@88e9200 {
+-				reg = <0 0x088e9200 0 0x128>,
+-				      <0 0x088e9400 0 0x200>,
+-				      <0 0x088e9c00 0 0x218>,
+-				      <0 0x088e9600 0 0x128>,
+-				      <0 0x088e9800 0 0x200>,
+-				      <0 0x088e9a00 0 0x18>;
+-				#clock-cells = <0>;
+-				#phy-cells = <0>;
+-				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+-				clock-names = "pipe0";
+-				clock-output-names = "usb3_phy_pipe_clk_src";
+-			};
+-
+-			dp_phy: dp-phy@88ea200 {
+-				reg = <0 0x088ea200 0 0x200>,
+-				      <0 0x088ea400 0 0x200>,
+-				      <0 0x088eaa00 0 0x200>,
+-				      <0 0x088ea600 0 0x200>,
+-				      <0 0x088ea800 0 0x200>;
+-				#clock-cells = <1>;
+-				#phy-cells = <0>;
+-			};
++			#clock-cells = <1>;
++			#phy-cells = <1>;
+ 		};
+ 
+ 		pmu@90b6300 {
+@@ -3001,7 +2981,8 @@ usb_1_dwc3: usb@a600000 {
+ 				iommus = <&apps_smmu 0x540 0>;
+ 				snps,dis_u2_susphy_quirk;
+ 				snps,dis_enblslpm_quirk;
+-				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
++				snps,parkmode-disable-ss-quirk;
++				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
+ 				phy-names = "usb2-phy", "usb3-phy";
+ 				maximum-speed = "super-speed";
+ 			};
+@@ -3307,8 +3288,9 @@ mdss_dp: displayport-controller@ae90000 {
+ 					      "ctrl_link_iface", "stream_pixel";
+ 				assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ 						  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+-				assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+-				phys = <&dp_phy>;
++				assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
++							 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
++				phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
+ 				phy-names = "dp";
+ 
+ 				operating-points-v2 = <&dp_opp_table>;
+@@ -3365,8 +3347,8 @@ dispcc: clock-controller@af00000 {
+ 				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ 				 <&mdss_dsi0_phy 0>,
+ 				 <&mdss_dsi0_phy 1>,
+-				 <&dp_phy 0>,
+-				 <&dp_phy 1>;
++				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
++				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+ 			clock-names = "bi_tcxo",
+ 				      "gcc_disp_gpll0_clk_src",
+ 				      "dsi0_phy_pll_out_byteclk",
+diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
+index b75de7caaa7e5..149c7962f2cbb 100644
+--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
+@@ -18,6 +18,7 @@
+ #include <dt-bindings/interconnect/qcom,sc7280.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/mailbox/qcom-ipcc.h>
++#include <dt-bindings/phy/phy-qcom-qmp.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+ #include <dt-bindings/reset/qcom,sdm845-aoss.h>
+ #include <dt-bindings/reset/qcom,sdm845-pdc.h>
+@@ -858,7 +859,7 @@ gcc: clock-controller@100000 {
+ 				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
+ 				 <0>, <&pcie1_lane>,
+ 				 <0>, <0>, <0>,
+-				 <&usb_1_ssphy>;
++				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+ 			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
+ 				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
+ 				      "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
+@@ -3351,49 +3352,26 @@ usb_2_hsphy: phy@88e4000 {
+ 			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+ 		};
+ 
+-		usb_1_qmpphy: phy-wrapper@88e9000 {
+-			compatible = "qcom,sc7280-qmp-usb3-dp-phy",
+-				     "qcom,sm8250-qmp-usb3-dp-phy";
+-			reg = <0 0x088e9000 0 0x200>,
+-			      <0 0x088e8000 0 0x40>,
+-			      <0 0x088ea000 0 0x200>;
++		usb_1_qmpphy: phy@88e8000 {
++			compatible = "qcom,sc7280-qmp-usb3-dp-phy";
++			reg = <0 0x088e8000 0 0x3000>;
+ 			status = "disabled";
+-			#address-cells = <2>;
+-			#size-cells = <2>;
+-			ranges;
+ 
+ 			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ 				 <&rpmhcc RPMH_CXO_CLK>,
+-				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+-			clock-names = "aux", "ref_clk_src", "com_aux";
++				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
++				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
++			clock-names = "aux",
++				      "ref",
++				      "com_aux",
++				      "usb3_pipe";
+ 
+ 			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ 				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ 			reset-names = "phy", "common";
+ 
+-			usb_1_ssphy: usb3-phy@88e9200 {
+-				reg = <0 0x088e9200 0 0x200>,
+-				      <0 0x088e9400 0 0x200>,
+-				      <0 0x088e9c00 0 0x400>,
+-				      <0 0x088e9600 0 0x200>,
+-				      <0 0x088e9800 0 0x200>,
+-				      <0 0x088e9a00 0 0x100>;
+-				#clock-cells = <0>;
+-				#phy-cells = <0>;
+-				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+-				clock-names = "pipe0";
+-				clock-output-names = "usb3_phy_pipe_clk_src";
+-			};
+-
+-			dp_phy: dp-phy@88ea200 {
+-				reg = <0 0x088ea200 0 0x200>,
+-				      <0 0x088ea400 0 0x200>,
+-				      <0 0x088eaa00 0 0x200>,
+-				      <0 0x088ea600 0 0x200>,
+-				      <0 0x088ea800 0 0x200>;
+-				#phy-cells = <0>;
+-				#clock-cells = <1>;
+-			};
++			#clock-cells = <1>;
++			#phy-cells = <1>;
+ 		};
+ 
+ 		usb_2: usb@8cf8800 {
+@@ -3702,7 +3680,8 @@ usb_1_dwc3: usb@a600000 {
+ 				iommus = <&apps_smmu 0xe0 0x0>;
+ 				snps,dis_u2_susphy_quirk;
+ 				snps,dis_enblslpm_quirk;
+-				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
++				snps,parkmode-disable-ss-quirk;
++				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
+ 				phy-names = "usb2-phy", "usb3-phy";
+ 				maximum-speed = "super-speed";
+ 			};
+@@ -3807,8 +3786,8 @@ dispcc: clock-controller@af00000 {
+ 				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ 				 <&mdss_dsi_phy 0>,
+ 				 <&mdss_dsi_phy 1>,
+-				 <&dp_phy 0>,
+-				 <&dp_phy 1>,
++				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
++				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+ 				 <&mdss_edp_phy 0>,
+ 				 <&mdss_edp_phy 1>;
+ 			clock-names = "bi_tcxo",
+@@ -4144,8 +4123,9 @@ mdss_dp: displayport-controller@ae90000 {
+ 						"stream_pixel";
+ 				assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ 						  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+-				assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+-				phys = <&dp_phy>;
++				assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
++							 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
++				phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
+ 				phy-names = "dp";
+ 
+ 				operating-points-v2 = <&dp_opp_table>;
+diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
+index 9d9b378c07e14..dcdc8a0cd1819 100644
+--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
+@@ -18,6 +18,7 @@
+ #include <dt-bindings/interconnect/qcom,osm-l3.h>
+ #include <dt-bindings/interconnect/qcom,sdm845.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/phy/phy-qcom-qmp.h>
+ #include <dt-bindings/phy/phy-qcom-qusb2.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+ #include <dt-bindings/reset/qcom,sdm845-aoss.h>
+@@ -3983,80 +3984,54 @@ usb_2_hsphy: phy@88e3000 {
+ 			nvmem-cells = <&qusb2s_hstx_trim>;
+ 		};
+ 
+-		usb_1_qmpphy: phy@88e9000 {
++		usb_1_qmpphy: phy@88e8000 {
+ 			compatible = "qcom,sdm845-qmp-usb3-dp-phy";
+-			reg = <0 0x088e9000 0 0x18c>,
+-			      <0 0x088e8000 0 0x38>,
+-			      <0 0x088ea000 0 0x40>;
++			reg = <0 0x088e8000 0 0x3000>;
+ 			status = "disabled";
+-			#address-cells = <2>;
+-			#size-cells = <2>;
+-			ranges;
+ 
+ 			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+-				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ 				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+-				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+-			clock-names = "aux", "cfg_ahb", "ref", "com_aux";
++				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
++				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
++				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
++			clock-names = "aux",
++				      "ref",
++				      "com_aux",
++				      "usb3_pipe",
++				      "cfg_ahb";
+ 
+ 			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ 				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ 			reset-names = "phy", "common";
+ 
+-			usb_1_ssphy: usb3-phy@88e9200 {
+-				reg = <0 0x088e9200 0 0x128>,
+-				      <0 0x088e9400 0 0x200>,
+-				      <0 0x088e9c00 0 0x218>,
+-				      <0 0x088e9600 0 0x128>,
+-				      <0 0x088e9800 0 0x200>,
+-				      <0 0x088e9a00 0 0x100>;
+-				#clock-cells = <0>;
+-				#phy-cells = <0>;
+-				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+-				clock-names = "pipe0";
+-				clock-output-names = "usb3_phy_pipe_clk_src";
+-			};
+-
+-			dp_phy: dp-phy@88ea200 {
+-				reg = <0 0x088ea200 0 0x200>,
+-				      <0 0x088ea400 0 0x200>,
+-				      <0 0x088eaa00 0 0x200>,
+-				      <0 0x088ea600 0 0x200>,
+-				      <0 0x088ea800 0 0x200>;
+-				#clock-cells = <1>;
+-				#phy-cells = <0>;
+-			};
++			#clock-cells = <1>;
++			#phy-cells = <1>;
+ 		};
+ 
+ 		usb_2_qmpphy: phy@88eb000 {
+ 			compatible = "qcom,sdm845-qmp-usb3-uni-phy";
+-			reg = <0 0x088eb000 0 0x18c>;
+-			status = "disabled";
+-			#address-cells = <2>;
+-			#size-cells = <2>;
+-			ranges;
++			reg = <0 0x088eb000 0 0x1000>;
+ 
+ 			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+ 				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ 				 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+-				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+-			clock-names = "aux", "cfg_ahb", "ref", "com_aux";
++				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
++				 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
++			clock-names = "aux",
++				      "cfg_ahb",
++				      "ref",
++				      "com_aux",
++				      "pipe";
++			clock-output-names = "usb3_uni_phy_pipe_clk_src";
++			#clock-cells = <0>;
++			#phy-cells = <0>;
+ 
+-			resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
+-				 <&gcc GCC_USB3_PHY_SEC_BCR>;
+-			reset-names = "phy", "common";
++			resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
++				 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
++			reset-names = "phy",
++				      "phy_phy";
+ 
+-			usb_2_ssphy: phy@88eb200 {
+-				reg = <0 0x088eb200 0 0x128>,
+-				      <0 0x088eb400 0 0x1fc>,
+-				      <0 0x088eb800 0 0x218>,
+-				      <0 0x088eb600 0 0x70>;
+-				#clock-cells = <0>;
+-				#phy-cells = <0>;
+-				clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+-				clock-names = "pipe0";
+-				clock-output-names = "usb3_uni_phy_pipe_clk_src";
+-			};
++			status = "disabled";
+ 		};
+ 
+ 		usb_1: usb@a6f8800 {
+@@ -4105,7 +4080,8 @@ usb_1_dwc3: usb@a600000 {
+ 				iommus = <&apps_smmu 0x740 0>;
+ 				snps,dis_u2_susphy_quirk;
+ 				snps,dis_enblslpm_quirk;
+-				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
++				snps,parkmode-disable-ss-quirk;
++				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
+ 				phy-names = "usb2-phy", "usb3-phy";
+ 			};
+ 		};
+@@ -4156,7 +4132,8 @@ usb_2_dwc3: usb@a800000 {
+ 				iommus = <&apps_smmu 0x760 0>;
+ 				snps,dis_u2_susphy_quirk;
+ 				snps,dis_enblslpm_quirk;
+-				phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
++				snps,parkmode-disable-ss-quirk;
++				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
+ 				phy-names = "usb2-phy", "usb3-phy";
+ 			};
+ 		};
+@@ -4573,8 +4550,9 @@ mdss_dp: displayport-controller@ae90000 {
+ 					      "ctrl_link_iface", "stream_pixel";
+ 				assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ 						  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+-				assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+-				phys = <&dp_phy>;
++				assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
++							 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
++				phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
+ 				phy-names = "dp";
+ 
+ 				operating-points-v2 = <&dp_opp_table>;
+@@ -4912,8 +4890,8 @@ dispcc: clock-controller@af00000 {
+ 				 <&mdss_dsi0_phy 1>,
+ 				 <&mdss_dsi1_phy 0>,
+ 				 <&mdss_dsi1_phy 1>,
+-				 <&dp_phy 0>,
+-				 <&dp_phy 1>;
++				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
++				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+ 			clock-names = "bi_tcxo",
+ 				      "gcc_disp_gpll0_clk_src",
+ 				      "gcc_disp_gpll0_div_clk_src",
+diff --git a/arch/arm64/include/asm/jump_label.h b/arch/arm64/include/asm/jump_label.h
+index 6aafbb7899916..4b99159150829 100644
+--- a/arch/arm64/include/asm/jump_label.h
++++ b/arch/arm64/include/asm/jump_label.h
+@@ -13,6 +13,7 @@
+ #include <linux/types.h>
+ #include <asm/insn.h>
+ 
++#define HAVE_JUMP_LABEL_BATCH
+ #define JUMP_LABEL_NOP_SIZE		AARCH64_INSN_SIZE
+ 
+ static __always_inline bool arch_static_branch(struct static_key * const key,
+diff --git a/arch/arm64/kernel/jump_label.c b/arch/arm64/kernel/jump_label.c
+index faf88ec9c48e8..f63ea915d6ad2 100644
+--- a/arch/arm64/kernel/jump_label.c
++++ b/arch/arm64/kernel/jump_label.c
+@@ -7,11 +7,12 @@
+  */
+ #include <linux/kernel.h>
+ #include <linux/jump_label.h>
++#include <linux/smp.h>
+ #include <asm/insn.h>
+ #include <asm/patching.h>
+ 
+-void arch_jump_label_transform(struct jump_entry *entry,
+-			       enum jump_label_type type)
++bool arch_jump_label_transform_queue(struct jump_entry *entry,
++				     enum jump_label_type type)
+ {
+ 	void *addr = (void *)jump_entry_code(entry);
+ 	u32 insn;
+@@ -25,4 +26,10 @@ void arch_jump_label_transform(struct jump_entry *entry,
+ 	}
+ 
+ 	aarch64_insn_patch_text_nosync(addr, insn);
++	return true;
++}
++
++void arch_jump_label_transform_apply(void)
++{
++	kick_all_cpus_sync();
+ }
+diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
+index c0be84a6e81fd..cc7747c5f21f3 100644
+--- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
++++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
+@@ -99,8 +99,8 @@ liointc1: interrupt-controller@1fe11440 {
+ 		rtc0: rtc@1fe07800 {
+ 			compatible = "loongson,ls2k1000-rtc";
+ 			reg = <0 0x1fe07800 0 0x78>;
+-			interrupt-parent = <&liointc0>;
+-			interrupts = <60 IRQ_TYPE_LEVEL_LOW>;
++			interrupt-parent = <&liointc1>;
++			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ 		};
+ 
+ 		uart0: serial@1fe00000 {
+@@ -108,7 +108,7 @@ uart0: serial@1fe00000 {
+ 			reg = <0 0x1fe00000 0 0x8>;
+ 			clock-frequency = <125000000>;
+ 			interrupt-parent = <&liointc0>;
+-			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
++			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ 			no-loopback-test;
+ 		};
+ 
+@@ -117,7 +117,6 @@ pci@1a000000 {
+ 			device_type = "pci";
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+-			#interrupt-cells = <2>;
+ 
+ 			reg = <0 0x1a000000 0 0x02000000>,
+ 				<0xfe 0x00000000 0 0x20000000>;
+@@ -132,8 +131,8 @@ gmac@3,0 {
+ 						   "pciclass0c03";
+ 
+ 				reg = <0x1800 0x0 0x0 0x0 0x0>;
+-				interrupts = <12 IRQ_TYPE_LEVEL_LOW>,
+-					     <13 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
++					     <13 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-names = "macirq", "eth_lpi";
+ 				interrupt-parent = <&liointc0>;
+ 				phy-mode = "rgmii-id";
+@@ -156,8 +155,8 @@ gmac@3,1 {
+ 						   "loongson, pci-gmac";
+ 
+ 				reg = <0x1900 0x0 0x0 0x0 0x0>;
+-				interrupts = <14 IRQ_TYPE_LEVEL_LOW>,
+-					     <15 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
++					     <15 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-names = "macirq", "eth_lpi";
+ 				interrupt-parent = <&liointc0>;
+ 				phy-mode = "rgmii-id";
+@@ -179,7 +178,7 @@ ehci@4,1 {
+ 						   "pciclass0c03";
+ 
+ 				reg = <0x2100 0x0 0x0 0x0 0x0>;
+-				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-parent = <&liointc1>;
+ 			};
+ 
+@@ -190,7 +189,7 @@ ohci@4,2 {
+ 						   "pciclass0c03";
+ 
+ 				reg = <0x2200 0x0 0x0 0x0 0x0>;
+-				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-parent = <&liointc1>;
+ 			};
+ 
+@@ -201,97 +200,121 @@ sata@8,0 {
+ 						   "pciclass0106";
+ 
+ 				reg = <0x4000 0x0 0x0 0x0 0x0>;
+-				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-parent = <&liointc0>;
+ 			};
+ 
+-			pci_bridge@9,0 {
++			pcie@9,0 {
+ 				compatible = "pci0014,7a19.0",
+ 						   "pci0014,7a19",
+ 						   "pciclass060400",
+ 						   "pciclass0604";
+ 
+ 				reg = <0x4800 0x0 0x0 0x0 0x0>;
++				#address-cells = <3>;
++				#size-cells = <2>;
++				device_type = "pci";
+ 				#interrupt-cells = <1>;
+-				interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-parent = <&liointc1>;
+ 				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>;
++				interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_HIGH>;
++				ranges;
+ 				external-facing;
+ 			};
+ 
+-			pci_bridge@a,0 {
++			pcie@a,0 {
+ 				compatible = "pci0014,7a09.0",
+ 						   "pci0014,7a09",
+ 						   "pciclass060400",
+ 						   "pciclass0604";
+ 
+ 				reg = <0x5000 0x0 0x0 0x0 0x0>;
++				#address-cells = <3>;
++				#size-cells = <2>;
++				device_type = "pci";
+ 				#interrupt-cells = <1>;
+-				interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-parent = <&liointc1>;
+ 				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>;
++				interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>;
++				ranges;
+ 				external-facing;
+ 			};
+ 
+-			pci_bridge@b,0 {
++			pcie@b,0 {
+ 				compatible = "pci0014,7a09.0",
+ 						   "pci0014,7a09",
+ 						   "pciclass060400",
+ 						   "pciclass0604";
+ 
+ 				reg = <0x5800 0x0 0x0 0x0 0x0>;
++				#address-cells = <3>;
++				#size-cells = <2>;
++				device_type = "pci";
+ 				#interrupt-cells = <1>;
+-				interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-parent = <&liointc1>;
+ 				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>;
++				interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>;
++				ranges;
+ 				external-facing;
+ 			};
+ 
+-			pci_bridge@c,0 {
++			pcie@c,0 {
+ 				compatible = "pci0014,7a09.0",
+ 						   "pci0014,7a09",
+ 						   "pciclass060400",
+ 						   "pciclass0604";
+ 
+ 				reg = <0x6000 0x0 0x0 0x0 0x0>;
++				#address-cells = <3>;
++				#size-cells = <2>;
++				device_type = "pci";
+ 				#interrupt-cells = <1>;
+-				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-parent = <&liointc1>;
+ 				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>;
++				interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>;
++				ranges;
+ 				external-facing;
+ 			};
+ 
+-			pci_bridge@d,0 {
++			pcie@d,0 {
+ 				compatible = "pci0014,7a19.0",
+ 						   "pci0014,7a19",
+ 						   "pciclass060400",
+ 						   "pciclass0604";
+ 
+ 				reg = <0x6800 0x0 0x0 0x0 0x0>;
++				#address-cells = <3>;
++				#size-cells = <2>;
++				device_type = "pci";
+ 				#interrupt-cells = <1>;
+-				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-parent = <&liointc1>;
+ 				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>;
++				interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>;
++				ranges;
+ 				external-facing;
+ 			};
+ 
+-			pci_bridge@e,0 {
++			pcie@e,0 {
+ 				compatible = "pci0014,7a09.0",
+ 						   "pci0014,7a09",
+ 						   "pciclass060400",
+ 						   "pciclass0604";
+ 
+ 				reg = <0x7000 0x0 0x0 0x0 0x0>;
++				#address-cells = <3>;
++				#size-cells = <2>;
++				device_type = "pci";
+ 				#interrupt-cells = <1>;
+-				interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
++				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-parent = <&liointc1>;
+ 				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>;
++				interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>;
++				ranges;
+ 				external-facing;
+ 			};
+ 
+diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
+index 5348d842c7453..e867fe465164e 100644
+--- a/arch/riscv/kernel/traps_misaligned.c
++++ b/arch/riscv/kernel/traps_misaligned.c
+@@ -151,51 +151,19 @@
+ #define PRECISION_S 0
+ #define PRECISION_D 1
+ 
+-#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn)			\
+-static inline type load_##type(const type *addr)			\
+-{									\
+-	type val;							\
+-	asm (#insn " %0, %1"						\
+-	: "=&r" (val) : "m" (*addr));					\
+-	return val;							\
+-}
++static inline u8 load_u8(const u8 *addr)
++{
++	u8 val;
+ 
+-#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn)			\
+-static inline void store_##type(type *addr, type val)			\
+-{									\
+-	asm volatile (#insn " %0, %1\n"					\
+-	: : "r" (val), "m" (*addr));					\
+-}
++	asm volatile("lbu %0, %1" : "=&r" (val) : "m" (*addr));
+ 
+-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu)
+-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu)
+-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb)
+-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh)
+-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw)
+-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u8, sb)
+-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u16, sh)
+-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u32, sw)
+-#if defined(CONFIG_64BIT)
+-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu)
+-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld)
+-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64, sd)
+-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld)
+-#else
+-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
+-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
+-
+-static inline u64 load_u64(const u64 *addr)
+-{
+-	return load_u32((u32 *)addr)
+-		+ ((u64)load_u32((u32 *)addr + 1) << 32);
++	return val;
+ }
+ 
+-static inline void store_u64(u64 *addr, u64 val)
++static inline void store_u8(u8 *addr, u8 val)
+ {
+-	store_u32((u32 *)addr, val);
+-	store_u32((u32 *)addr + 1, val >> 32);
++	asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr));
+ }
+-#endif
+ 
+ static inline ulong get_insn(ulong mepc)
+ {
+diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
+index 90d4ba36d1d06..655b2b1bb529f 100644
+--- a/arch/riscv/mm/fault.c
++++ b/arch/riscv/mm/fault.c
+@@ -61,26 +61,27 @@ static inline void no_context(struct pt_regs *regs, unsigned long addr)
+ 
+ static inline void mm_fault_error(struct pt_regs *regs, unsigned long addr, vm_fault_t fault)
+ {
++	if (!user_mode(regs)) {
++		no_context(regs, addr);
++		return;
++	}
++
+ 	if (fault & VM_FAULT_OOM) {
+ 		/*
+ 		 * We ran out of memory, call the OOM killer, and return the userspace
+ 		 * (which will retry the fault, or kill us if we got oom-killed).
+ 		 */
+-		if (!user_mode(regs)) {
+-			no_context(regs, addr);
+-			return;
+-		}
+ 		pagefault_out_of_memory();
+ 		return;
+ 	} else if (fault & (VM_FAULT_SIGBUS | VM_FAULT_HWPOISON | VM_FAULT_HWPOISON_LARGE)) {
+ 		/* Kernel mode? Handle exceptions or die */
+-		if (!user_mode(regs)) {
+-			no_context(regs, addr);
+-			return;
+-		}
+ 		do_trap(regs, SIGBUS, BUS_ADRERR, addr);
+ 		return;
++	} else if (fault & VM_FAULT_SIGSEGV) {
++		do_trap(regs, SIGSEGV, SEGV_MAPERR, addr);
++		return;
+ 	}
++
+ 	BUG();
+ }
+ 
+diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
+index 8adcb9419ad50..9b10e9655df8c 100644
+--- a/arch/riscv/mm/init.c
++++ b/arch/riscv/mm/init.c
+@@ -217,8 +217,6 @@ static void __init setup_bootmem(void)
+ 	 */
+ 	memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start);
+ 
+-	phys_ram_end = memblock_end_of_DRAM();
+-
+ 	/*
+ 	 * Make sure we align the start of the memory on a PMD boundary so that
+ 	 * at worst, we map the linear mapping with PMD mappings.
+@@ -233,6 +231,16 @@ static void __init setup_bootmem(void)
+ 	if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU))
+ 		kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;
+ 
++	/*
++	 * The size of the linear page mapping may restrict the amount of
++	 * usable RAM.
++	 */
++	if (IS_ENABLED(CONFIG_64BIT)) {
++		max_mapped_addr = __pa(PAGE_OFFSET) + KERN_VIRT_SIZE;
++		memblock_cap_memory_range(phys_ram_base,
++					  max_mapped_addr - phys_ram_base);
++	}
++
+ 	/*
+ 	 * Reserve physical address space that would be mapped to virtual
+ 	 * addresses greater than (void *)(-PAGE_SIZE) because:
+@@ -249,6 +257,7 @@ static void __init setup_bootmem(void)
+ 		memblock_reserve(max_mapped_addr, (phys_addr_t)-max_mapped_addr);
+ 	}
+ 
++	phys_ram_end = memblock_end_of_DRAM();
+ 	min_low_pfn = PFN_UP(phys_ram_base);
+ 	max_low_pfn = max_pfn = PFN_DOWN(phys_ram_end);
+ 	high_memory = (void *)(__va(PFN_PHYS(max_low_pfn)));
+@@ -1269,8 +1278,6 @@ static void __init create_linear_mapping_page_table(void)
+ 		if (start <= __pa(PAGE_OFFSET) &&
+ 		    __pa(PAGE_OFFSET) < end)
+ 			start = __pa(PAGE_OFFSET);
+-		if (end >= __pa(PAGE_OFFSET) + memory_limit)
+-			end = __pa(PAGE_OFFSET) + memory_limit;
+ 
+ 		create_linear_mapping_range(start, end, 0);
+ 	}
+diff --git a/arch/x86/include/asm/posted_intr.h b/arch/x86/include/asm/posted_intr.h
+new file mode 100644
+index 0000000000000..f0324c56f7af5
+--- /dev/null
++++ b/arch/x86/include/asm/posted_intr.h
+@@ -0,0 +1,88 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef _X86_POSTED_INTR_H
++#define _X86_POSTED_INTR_H
++
++#define POSTED_INTR_ON  0
++#define POSTED_INTR_SN  1
++
++#define PID_TABLE_ENTRY_VALID 1
++
++/* Posted-Interrupt Descriptor */
++struct pi_desc {
++	u32 pir[8];     /* Posted interrupt requested */
++	union {
++		struct {
++				/* bit 256 - Outstanding Notification */
++			u16	on	: 1,
++				/* bit 257 - Suppress Notification */
++				sn	: 1,
++				/* bit 271:258 - Reserved */
++				rsvd_1	: 14;
++				/* bit 279:272 - Notification Vector */
++			u8	nv;
++				/* bit 287:280 - Reserved */
++			u8	rsvd_2;
++				/* bit 319:288 - Notification Destination */
++			u32	ndst;
++		};
++		u64 control;
++	};
++	u32 rsvd[6];
++} __aligned(64);
++
++static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
++{
++	return test_and_set_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control);
++}
++
++static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
++{
++	return test_and_clear_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control);
++}
++
++static inline bool pi_test_and_clear_sn(struct pi_desc *pi_desc)
++{
++	return test_and_clear_bit(POSTED_INTR_SN, (unsigned long *)&pi_desc->control);
++}
++
++static inline bool pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
++{
++	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
++}
++
++static inline bool pi_is_pir_empty(struct pi_desc *pi_desc)
++{
++	return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS);
++}
++
++static inline void pi_set_sn(struct pi_desc *pi_desc)
++{
++	set_bit(POSTED_INTR_SN, (unsigned long *)&pi_desc->control);
++}
++
++static inline void pi_set_on(struct pi_desc *pi_desc)
++{
++	set_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control);
++}
++
++static inline void pi_clear_on(struct pi_desc *pi_desc)
++{
++	clear_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control);
++}
++
++static inline void pi_clear_sn(struct pi_desc *pi_desc)
++{
++	clear_bit(POSTED_INTR_SN, (unsigned long *)&pi_desc->control);
++}
++
++static inline bool pi_test_on(struct pi_desc *pi_desc)
++{
++	return test_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control);
++}
++
++static inline bool pi_test_sn(struct pi_desc *pi_desc)
++{
++	return test_bit(POSTED_INTR_SN, (unsigned long *)&pi_desc->control);
++}
++
++#endif /* _X86_POSTED_INTR_H */
+diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
+index 80e3fe184d17e..a99ffc3f3a3fd 100644
+--- a/arch/x86/kvm/Makefile
++++ b/arch/x86/kvm/Makefile
+@@ -26,6 +26,10 @@ kvm-intel-y		+= vmx/vmx.o vmx/vmenter.o vmx/pmu_intel.o vmx/vmcs12.o \
+ 			   vmx/hyperv.o vmx/nested.o vmx/posted_intr.o
+ kvm-intel-$(CONFIG_X86_SGX_KVM)	+= vmx/sgx.o
+ 
++ifdef CONFIG_HYPERV
++kvm-intel-y		+= vmx/vmx_onhyperv.o
++endif
++
+ kvm-amd-y		+= svm/svm.o svm/vmenter.o svm/pmu.o svm/nested.o svm/avic.o \
+ 			   svm/sev.o svm/hyperv.o
+ 
+diff --git a/arch/x86/kvm/vmx/hyperv.c b/arch/x86/kvm/vmx/hyperv.c
+index 313b8bb5b8a7c..de13dc14fe1d2 100644
+--- a/arch/x86/kvm/vmx/hyperv.c
++++ b/arch/x86/kvm/vmx/hyperv.c
+@@ -13,111 +13,6 @@
+ 
+ #define CC KVM_NESTED_VMENTER_CONSISTENCY_CHECK
+ 
+-/*
+- * Enlightened VMCSv1 doesn't support these:
+- *
+- *	POSTED_INTR_NV                  = 0x00000002,
+- *	GUEST_INTR_STATUS               = 0x00000810,
+- *	APIC_ACCESS_ADDR		= 0x00002014,
+- *	POSTED_INTR_DESC_ADDR           = 0x00002016,
+- *	EOI_EXIT_BITMAP0                = 0x0000201c,
+- *	EOI_EXIT_BITMAP1                = 0x0000201e,
+- *	EOI_EXIT_BITMAP2                = 0x00002020,
+- *	EOI_EXIT_BITMAP3                = 0x00002022,
+- *	GUEST_PML_INDEX			= 0x00000812,
+- *	PML_ADDRESS			= 0x0000200e,
+- *	VM_FUNCTION_CONTROL             = 0x00002018,
+- *	EPTP_LIST_ADDRESS               = 0x00002024,
+- *	VMREAD_BITMAP                   = 0x00002026,
+- *	VMWRITE_BITMAP                  = 0x00002028,
+- *
+- *	TSC_MULTIPLIER                  = 0x00002032,
+- *	PLE_GAP                         = 0x00004020,
+- *	PLE_WINDOW                      = 0x00004022,
+- *	VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
+- *
+- * Currently unsupported in KVM:
+- *	GUEST_IA32_RTIT_CTL		= 0x00002814,
+- */
+-#define EVMCS1_SUPPORTED_PINCTRL					\
+-	(PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |				\
+-	 PIN_BASED_EXT_INTR_MASK |					\
+-	 PIN_BASED_NMI_EXITING |					\
+-	 PIN_BASED_VIRTUAL_NMIS)
+-
+-#define EVMCS1_SUPPORTED_EXEC_CTRL					\
+-	(CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |				\
+-	 CPU_BASED_HLT_EXITING |					\
+-	 CPU_BASED_CR3_LOAD_EXITING |					\
+-	 CPU_BASED_CR3_STORE_EXITING |					\
+-	 CPU_BASED_UNCOND_IO_EXITING |					\
+-	 CPU_BASED_MOV_DR_EXITING |					\
+-	 CPU_BASED_USE_TSC_OFFSETTING |					\
+-	 CPU_BASED_MWAIT_EXITING |					\
+-	 CPU_BASED_MONITOR_EXITING |					\
+-	 CPU_BASED_INVLPG_EXITING |					\
+-	 CPU_BASED_RDPMC_EXITING |					\
+-	 CPU_BASED_INTR_WINDOW_EXITING |				\
+-	 CPU_BASED_CR8_LOAD_EXITING |					\
+-	 CPU_BASED_CR8_STORE_EXITING |					\
+-	 CPU_BASED_RDTSC_EXITING |					\
+-	 CPU_BASED_TPR_SHADOW |						\
+-	 CPU_BASED_USE_IO_BITMAPS |					\
+-	 CPU_BASED_MONITOR_TRAP_FLAG |					\
+-	 CPU_BASED_USE_MSR_BITMAPS |					\
+-	 CPU_BASED_NMI_WINDOW_EXITING |					\
+-	 CPU_BASED_PAUSE_EXITING |					\
+-	 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
+-
+-#define EVMCS1_SUPPORTED_2NDEXEC					\
+-	(SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |			\
+-	 SECONDARY_EXEC_WBINVD_EXITING |				\
+-	 SECONDARY_EXEC_ENABLE_VPID |					\
+-	 SECONDARY_EXEC_ENABLE_EPT |					\
+-	 SECONDARY_EXEC_UNRESTRICTED_GUEST |				\
+-	 SECONDARY_EXEC_DESC |						\
+-	 SECONDARY_EXEC_ENABLE_RDTSCP |					\
+-	 SECONDARY_EXEC_ENABLE_INVPCID |				\
+-	 SECONDARY_EXEC_ENABLE_XSAVES |					\
+-	 SECONDARY_EXEC_RDSEED_EXITING |				\
+-	 SECONDARY_EXEC_RDRAND_EXITING |				\
+-	 SECONDARY_EXEC_TSC_SCALING |					\
+-	 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |				\
+-	 SECONDARY_EXEC_PT_USE_GPA |					\
+-	 SECONDARY_EXEC_PT_CONCEAL_VMX |				\
+-	 SECONDARY_EXEC_BUS_LOCK_DETECTION |				\
+-	 SECONDARY_EXEC_NOTIFY_VM_EXITING |				\
+-	 SECONDARY_EXEC_ENCLS_EXITING)
+-
+-#define EVMCS1_SUPPORTED_3RDEXEC (0ULL)
+-
+-#define EVMCS1_SUPPORTED_VMEXIT_CTRL					\
+-	(VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |				\
+-	 VM_EXIT_SAVE_DEBUG_CONTROLS |					\
+-	 VM_EXIT_ACK_INTR_ON_EXIT |					\
+-	 VM_EXIT_HOST_ADDR_SPACE_SIZE |					\
+-	 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |				\
+-	 VM_EXIT_SAVE_IA32_PAT |					\
+-	 VM_EXIT_LOAD_IA32_PAT |					\
+-	 VM_EXIT_SAVE_IA32_EFER |					\
+-	 VM_EXIT_LOAD_IA32_EFER |					\
+-	 VM_EXIT_CLEAR_BNDCFGS |					\
+-	 VM_EXIT_PT_CONCEAL_PIP |					\
+-	 VM_EXIT_CLEAR_IA32_RTIT_CTL)
+-
+-#define EVMCS1_SUPPORTED_VMENTRY_CTRL					\
+-	(VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |				\
+-	 VM_ENTRY_LOAD_DEBUG_CONTROLS |					\
+-	 VM_ENTRY_IA32E_MODE |						\
+-	 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |				\
+-	 VM_ENTRY_LOAD_IA32_PAT |					\
+-	 VM_ENTRY_LOAD_IA32_EFER |					\
+-	 VM_ENTRY_LOAD_BNDCFGS |					\
+-	 VM_ENTRY_PT_CONCEAL_PIP |					\
+-	 VM_ENTRY_LOAD_IA32_RTIT_CTL)
+-
+-#define EVMCS1_SUPPORTED_VMFUNC (0)
+-
+ #define EVMCS1_OFFSET(x) offsetof(struct hv_enlightened_vmcs, x)
+ #define EVMCS1_FIELD(number, name, clean_field)[ROL16(number, 6)] = \
+ 		{EVMCS1_OFFSET(name), clean_field}
+@@ -608,40 +503,6 @@ int nested_evmcs_check_controls(struct vmcs12 *vmcs12)
+ 	return 0;
+ }
+ 
+-#if IS_ENABLED(CONFIG_HYPERV)
+-DEFINE_STATIC_KEY_FALSE(__kvm_is_using_evmcs);
+-
+-/*
+- * KVM on Hyper-V always uses the latest known eVMCSv1 revision, the assumption
+- * is: in case a feature has corresponding fields in eVMCS described and it was
+- * exposed in VMX feature MSRs, KVM is free to use it. Warn if KVM meets a
+- * feature which has no corresponding eVMCS field, this likely means that KVM
+- * needs to be updated.
+- */
+-#define evmcs_check_vmcs_conf(field, ctrl)					\
+-	do {									\
+-		typeof(vmcs_conf->field) unsupported;				\
+-										\
+-		unsupported = vmcs_conf->field & ~EVMCS1_SUPPORTED_ ## ctrl;	\
+-		if (unsupported) {						\
+-			pr_warn_once(#field " unsupported with eVMCS: 0x%llx\n",\
+-				     (u64)unsupported);				\
+-			vmcs_conf->field &= EVMCS1_SUPPORTED_ ## ctrl;		\
+-		}								\
+-	}									\
+-	while (0)
+-
+-void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
+-{
+-	evmcs_check_vmcs_conf(cpu_based_exec_ctrl, EXEC_CTRL);
+-	evmcs_check_vmcs_conf(pin_based_exec_ctrl, PINCTRL);
+-	evmcs_check_vmcs_conf(cpu_based_2nd_exec_ctrl, 2NDEXEC);
+-	evmcs_check_vmcs_conf(cpu_based_3rd_exec_ctrl, 3RDEXEC);
+-	evmcs_check_vmcs_conf(vmentry_ctrl, VMENTRY_CTRL);
+-	evmcs_check_vmcs_conf(vmexit_ctrl, VMEXIT_CTRL);
+-}
+-#endif
+-
+ int nested_enable_evmcs(struct kvm_vcpu *vcpu,
+ 			uint16_t *vmcs_version)
+ {
+diff --git a/arch/x86/kvm/vmx/hyperv.h b/arch/x86/kvm/vmx/hyperv.h
+index 9623fe1651c48..9401dbfaea7ce 100644
+--- a/arch/x86/kvm/vmx/hyperv.h
++++ b/arch/x86/kvm/vmx/hyperv.h
+@@ -14,12 +14,113 @@
+ #include "vmcs.h"
+ #include "vmcs12.h"
+ 
+-struct vmcs_config;
+-
+-#define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
+-
+ #define KVM_EVMCS_VERSION 1
+ 
++/*
++ * Enlightened VMCSv1 doesn't support these:
++ *
++ *	POSTED_INTR_NV                  = 0x00000002,
++ *	GUEST_INTR_STATUS               = 0x00000810,
++ *	APIC_ACCESS_ADDR		= 0x00002014,
++ *	POSTED_INTR_DESC_ADDR           = 0x00002016,
++ *	EOI_EXIT_BITMAP0                = 0x0000201c,
++ *	EOI_EXIT_BITMAP1                = 0x0000201e,
++ *	EOI_EXIT_BITMAP2                = 0x00002020,
++ *	EOI_EXIT_BITMAP3                = 0x00002022,
++ *	GUEST_PML_INDEX			= 0x00000812,
++ *	PML_ADDRESS			= 0x0000200e,
++ *	VM_FUNCTION_CONTROL             = 0x00002018,
++ *	EPTP_LIST_ADDRESS               = 0x00002024,
++ *	VMREAD_BITMAP                   = 0x00002026,
++ *	VMWRITE_BITMAP                  = 0x00002028,
++ *
++ *	TSC_MULTIPLIER                  = 0x00002032,
++ *	PLE_GAP                         = 0x00004020,
++ *	PLE_WINDOW                      = 0x00004022,
++ *	VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
++ *
++ * Currently unsupported in KVM:
++ *	GUEST_IA32_RTIT_CTL		= 0x00002814,
++ */
++#define EVMCS1_SUPPORTED_PINCTRL					\
++	(PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |				\
++	 PIN_BASED_EXT_INTR_MASK |					\
++	 PIN_BASED_NMI_EXITING |					\
++	 PIN_BASED_VIRTUAL_NMIS)
++
++#define EVMCS1_SUPPORTED_EXEC_CTRL					\
++	(CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |				\
++	 CPU_BASED_HLT_EXITING |					\
++	 CPU_BASED_CR3_LOAD_EXITING |					\
++	 CPU_BASED_CR3_STORE_EXITING |					\
++	 CPU_BASED_UNCOND_IO_EXITING |					\
++	 CPU_BASED_MOV_DR_EXITING |					\
++	 CPU_BASED_USE_TSC_OFFSETTING |					\
++	 CPU_BASED_MWAIT_EXITING |					\
++	 CPU_BASED_MONITOR_EXITING |					\
++	 CPU_BASED_INVLPG_EXITING |					\
++	 CPU_BASED_RDPMC_EXITING |					\
++	 CPU_BASED_INTR_WINDOW_EXITING |				\
++	 CPU_BASED_CR8_LOAD_EXITING |					\
++	 CPU_BASED_CR8_STORE_EXITING |					\
++	 CPU_BASED_RDTSC_EXITING |					\
++	 CPU_BASED_TPR_SHADOW |						\
++	 CPU_BASED_USE_IO_BITMAPS |					\
++	 CPU_BASED_MONITOR_TRAP_FLAG |					\
++	 CPU_BASED_USE_MSR_BITMAPS |					\
++	 CPU_BASED_NMI_WINDOW_EXITING |					\
++	 CPU_BASED_PAUSE_EXITING |					\
++	 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
++
++#define EVMCS1_SUPPORTED_2NDEXEC					\
++	(SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |			\
++	 SECONDARY_EXEC_WBINVD_EXITING |				\
++	 SECONDARY_EXEC_ENABLE_VPID |					\
++	 SECONDARY_EXEC_ENABLE_EPT |					\
++	 SECONDARY_EXEC_UNRESTRICTED_GUEST |				\
++	 SECONDARY_EXEC_DESC |						\
++	 SECONDARY_EXEC_ENABLE_RDTSCP |					\
++	 SECONDARY_EXEC_ENABLE_INVPCID |				\
++	 SECONDARY_EXEC_ENABLE_XSAVES |					\
++	 SECONDARY_EXEC_RDSEED_EXITING |				\
++	 SECONDARY_EXEC_RDRAND_EXITING |				\
++	 SECONDARY_EXEC_TSC_SCALING |					\
++	 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |				\
++	 SECONDARY_EXEC_PT_USE_GPA |					\
++	 SECONDARY_EXEC_PT_CONCEAL_VMX |				\
++	 SECONDARY_EXEC_BUS_LOCK_DETECTION |				\
++	 SECONDARY_EXEC_NOTIFY_VM_EXITING |				\
++	 SECONDARY_EXEC_ENCLS_EXITING)
++
++#define EVMCS1_SUPPORTED_3RDEXEC (0ULL)
++
++#define EVMCS1_SUPPORTED_VMEXIT_CTRL					\
++	(VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |				\
++	 VM_EXIT_SAVE_DEBUG_CONTROLS |					\
++	 VM_EXIT_ACK_INTR_ON_EXIT |					\
++	 VM_EXIT_HOST_ADDR_SPACE_SIZE |					\
++	 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |				\
++	 VM_EXIT_SAVE_IA32_PAT |					\
++	 VM_EXIT_LOAD_IA32_PAT |					\
++	 VM_EXIT_SAVE_IA32_EFER |					\
++	 VM_EXIT_LOAD_IA32_EFER |					\
++	 VM_EXIT_CLEAR_BNDCFGS |					\
++	 VM_EXIT_PT_CONCEAL_PIP |					\
++	 VM_EXIT_CLEAR_IA32_RTIT_CTL)
++
++#define EVMCS1_SUPPORTED_VMENTRY_CTRL					\
++	(VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |				\
++	 VM_ENTRY_LOAD_DEBUG_CONTROLS |					\
++	 VM_ENTRY_IA32E_MODE |						\
++	 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |				\
++	 VM_ENTRY_LOAD_IA32_PAT |					\
++	 VM_ENTRY_LOAD_IA32_EFER |					\
++	 VM_ENTRY_LOAD_BNDCFGS |					\
++	 VM_ENTRY_PT_CONCEAL_PIP |					\
++	 VM_ENTRY_LOAD_IA32_RTIT_CTL)
++
++#define EVMCS1_SUPPORTED_VMFUNC (0)
++
+ struct evmcs_field {
+ 	u16 offset;
+ 	u16 clean_field;
+@@ -65,114 +166,6 @@ static inline u64 evmcs_read_any(struct hv_enlightened_vmcs *evmcs,
+ 	return vmcs12_read_any((void *)evmcs, field, offset);
+ }
+ 
+-#if IS_ENABLED(CONFIG_HYPERV)
+-
+-DECLARE_STATIC_KEY_FALSE(__kvm_is_using_evmcs);
+-
+-static __always_inline bool kvm_is_using_evmcs(void)
+-{
+-	return static_branch_unlikely(&__kvm_is_using_evmcs);
+-}
+-
+-static __always_inline int get_evmcs_offset(unsigned long field,
+-					    u16 *clean_field)
+-{
+-	int offset = evmcs_field_offset(field, clean_field);
+-
+-	WARN_ONCE(offset < 0, "accessing unsupported EVMCS field %lx\n", field);
+-	return offset;
+-}
+-
+-static __always_inline void evmcs_write64(unsigned long field, u64 value)
+-{
+-	u16 clean_field;
+-	int offset = get_evmcs_offset(field, &clean_field);
+-
+-	if (offset < 0)
+-		return;
+-
+-	*(u64 *)((char *)current_evmcs + offset) = value;
+-
+-	current_evmcs->hv_clean_fields &= ~clean_field;
+-}
+-
+-static __always_inline void evmcs_write32(unsigned long field, u32 value)
+-{
+-	u16 clean_field;
+-	int offset = get_evmcs_offset(field, &clean_field);
+-
+-	if (offset < 0)
+-		return;
+-
+-	*(u32 *)((char *)current_evmcs + offset) = value;
+-	current_evmcs->hv_clean_fields &= ~clean_field;
+-}
+-
+-static __always_inline void evmcs_write16(unsigned long field, u16 value)
+-{
+-	u16 clean_field;
+-	int offset = get_evmcs_offset(field, &clean_field);
+-
+-	if (offset < 0)
+-		return;
+-
+-	*(u16 *)((char *)current_evmcs + offset) = value;
+-	current_evmcs->hv_clean_fields &= ~clean_field;
+-}
+-
+-static __always_inline u64 evmcs_read64(unsigned long field)
+-{
+-	int offset = get_evmcs_offset(field, NULL);
+-
+-	if (offset < 0)
+-		return 0;
+-
+-	return *(u64 *)((char *)current_evmcs + offset);
+-}
+-
+-static __always_inline u32 evmcs_read32(unsigned long field)
+-{
+-	int offset = get_evmcs_offset(field, NULL);
+-
+-	if (offset < 0)
+-		return 0;
+-
+-	return *(u32 *)((char *)current_evmcs + offset);
+-}
+-
+-static __always_inline u16 evmcs_read16(unsigned long field)
+-{
+-	int offset = get_evmcs_offset(field, NULL);
+-
+-	if (offset < 0)
+-		return 0;
+-
+-	return *(u16 *)((char *)current_evmcs + offset);
+-}
+-
+-static inline void evmcs_load(u64 phys_addr)
+-{
+-	struct hv_vp_assist_page *vp_ap =
+-		hv_get_vp_assist_page(smp_processor_id());
+-
+-	if (current_evmcs->hv_enlightenments_control.nested_flush_hypercall)
+-		vp_ap->nested_control.features.directhypercall = 1;
+-	vp_ap->current_nested_vmcs = phys_addr;
+-	vp_ap->enlighten_vmentry = 1;
+-}
+-
+-void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf);
+-#else /* !IS_ENABLED(CONFIG_HYPERV) */
+-static __always_inline bool kvm_is_using_evmcs(void) { return false; }
+-static __always_inline void evmcs_write64(unsigned long field, u64 value) {}
+-static __always_inline void evmcs_write32(unsigned long field, u32 value) {}
+-static __always_inline void evmcs_write16(unsigned long field, u16 value) {}
+-static __always_inline u64 evmcs_read64(unsigned long field) { return 0; }
+-static __always_inline u32 evmcs_read32(unsigned long field) { return 0; }
+-static __always_inline u16 evmcs_read16(unsigned long field) { return 0; }
+-static inline void evmcs_load(u64 phys_addr) {}
+-#endif /* IS_ENABLED(CONFIG_HYPERV) */
+-
+ #define EVMPTR_INVALID (-1ULL)
+ #define EVMPTR_MAP_PENDING (-2ULL)
+ 
+diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
+index d1b4a85def0a6..0ad66b9207e85 100644
+--- a/arch/x86/kvm/vmx/nested.c
++++ b/arch/x86/kvm/vmx/nested.c
+@@ -12,6 +12,7 @@
+ #include "mmu.h"
+ #include "nested.h"
+ #include "pmu.h"
++#include "posted_intr.h"
+ #include "sgx.h"
+ #include "trace.h"
+ #include "vmx.h"
+@@ -3830,8 +3831,8 @@ static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
+ 	if (!pi_test_and_clear_on(vmx->nested.pi_desc))
+ 		return 0;
+ 
+-	max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
+-	if (max_irr != 256) {
++	max_irr = pi_find_highest_vector(vmx->nested.pi_desc);
++	if (max_irr > 0) {
+ 		vapic_page = vmx->nested.virtual_apic_map.hva;
+ 		if (!vapic_page)
+ 			goto mmio_needed;
+@@ -3964,8 +3965,40 @@ static bool nested_vmx_preemption_timer_pending(struct kvm_vcpu *vcpu)
+ 
+ static bool vmx_has_nested_events(struct kvm_vcpu *vcpu, bool for_injection)
+ {
+-	return nested_vmx_preemption_timer_pending(vcpu) ||
+-	       to_vmx(vcpu)->nested.mtf_pending;
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	void *vapic = vmx->nested.virtual_apic_map.hva;
++	int max_irr, vppr;
++
++	if (nested_vmx_preemption_timer_pending(vcpu) ||
++	    vmx->nested.mtf_pending)
++		return true;
++
++	/*
++	 * Virtual Interrupt Delivery doesn't require manual injection.  Either
++	 * the interrupt is already in GUEST_RVI and will be recognized by CPU
++	 * at VM-Entry, or there is a KVM_REQ_EVENT pending and KVM will move
++	 * the interrupt from the PIR to RVI prior to entering the guest.
++	 */
++	if (for_injection)
++		return false;
++
++	if (!nested_cpu_has_vid(get_vmcs12(vcpu)) ||
++	    __vmx_interrupt_blocked(vcpu))
++		return false;
++
++	if (!vapic)
++		return false;
++
++	vppr = *((u32 *)(vapic + APIC_PROCPRI));
++
++	if (vmx->nested.pi_pending && vmx->nested.pi_desc &&
++	    pi_test_on(vmx->nested.pi_desc)) {
++		max_irr = pi_find_highest_vector(vmx->nested.pi_desc);
++		if (max_irr > 0 && (max_irr & 0xf0) > (vppr & 0xf0))
++			return true;
++	}
++
++	return false;
+ }
+ 
+ /*
+diff --git a/arch/x86/kvm/vmx/posted_intr.h b/arch/x86/kvm/vmx/posted_intr.h
+index 26992076552ef..1715d2ab07be5 100644
+--- a/arch/x86/kvm/vmx/posted_intr.h
++++ b/arch/x86/kvm/vmx/posted_intr.h
+@@ -2,97 +2,8 @@
+ #ifndef __KVM_X86_VMX_POSTED_INTR_H
+ #define __KVM_X86_VMX_POSTED_INTR_H
+ 
+-#define POSTED_INTR_ON  0
+-#define POSTED_INTR_SN  1
+-
+-#define PID_TABLE_ENTRY_VALID 1
+-
+-/* Posted-Interrupt Descriptor */
+-struct pi_desc {
+-	u32 pir[8];     /* Posted interrupt requested */
+-	union {
+-		struct {
+-				/* bit 256 - Outstanding Notification */
+-			u16	on	: 1,
+-				/* bit 257 - Suppress Notification */
+-				sn	: 1,
+-				/* bit 271:258 - Reserved */
+-				rsvd_1	: 14;
+-				/* bit 279:272 - Notification Vector */
+-			u8	nv;
+-				/* bit 287:280 - Reserved */
+-			u8	rsvd_2;
+-				/* bit 319:288 - Notification Destination */
+-			u32	ndst;
+-		};
+-		u64 control;
+-	};
+-	u32 rsvd[6];
+-} __aligned(64);
+-
+-static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
+-{
+-	return test_and_set_bit(POSTED_INTR_ON,
+-			(unsigned long *)&pi_desc->control);
+-}
+-
+-static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
+-{
+-	return test_and_clear_bit(POSTED_INTR_ON,
+-			(unsigned long *)&pi_desc->control);
+-}
+-
+-static inline bool pi_test_and_clear_sn(struct pi_desc *pi_desc)
+-{
+-	return test_and_clear_bit(POSTED_INTR_SN,
+-			(unsigned long *)&pi_desc->control);
+-}
+-
+-static inline bool pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
+-{
+-	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
+-}
+-
+-static inline bool pi_is_pir_empty(struct pi_desc *pi_desc)
+-{
+-	return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS);
+-}
+-
+-static inline void pi_set_sn(struct pi_desc *pi_desc)
+-{
+-	set_bit(POSTED_INTR_SN,
+-		(unsigned long *)&pi_desc->control);
+-}
+-
+-static inline void pi_set_on(struct pi_desc *pi_desc)
+-{
+-	set_bit(POSTED_INTR_ON,
+-		(unsigned long *)&pi_desc->control);
+-}
+-
+-static inline void pi_clear_on(struct pi_desc *pi_desc)
+-{
+-	clear_bit(POSTED_INTR_ON,
+-		(unsigned long *)&pi_desc->control);
+-}
+-
+-static inline void pi_clear_sn(struct pi_desc *pi_desc)
+-{
+-	clear_bit(POSTED_INTR_SN,
+-		(unsigned long *)&pi_desc->control);
+-}
+-
+-static inline bool pi_test_on(struct pi_desc *pi_desc)
+-{
+-	return test_bit(POSTED_INTR_ON,
+-			(unsigned long *)&pi_desc->control);
+-}
+-
+-static inline bool pi_test_sn(struct pi_desc *pi_desc)
+-{
+-	return test_bit(POSTED_INTR_SN,
+-			(unsigned long *)&pi_desc->control);
+-}
++#include <linux/find.h>
++#include <asm/posted_intr.h>
+ 
+ void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu);
+ void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu);
+@@ -103,4 +14,12 @@ int vmx_pi_update_irte(struct kvm *kvm, unsigned int host_irq,
+ 		       uint32_t guest_irq, bool set);
+ void vmx_pi_start_assignment(struct kvm *kvm);
+ 
++static inline int pi_find_highest_vector(struct pi_desc *pi_desc)
++{
++	int vec;
++
++	vec = find_last_bit((unsigned long *)pi_desc->pir, 256);
++	return vec < 256 ? vec : -1;
++}
++
+ #endif /* __KVM_X86_VMX_POSTED_INTR_H */
+diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
+index f5f652a546bf2..2e0106d9d371c 100644
+--- a/arch/x86/kvm/vmx/vmx.c
++++ b/arch/x86/kvm/vmx/vmx.c
+@@ -66,6 +66,8 @@
+ #include "vmx.h"
+ #include "x86.h"
+ #include "smm.h"
++#include "vmx_onhyperv.h"
++#include "posted_intr.h"
+ 
+ MODULE_AUTHOR("Qumranet");
+ MODULE_LICENSE("GPL");
+diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
+index 912b0c4697429..6be1627d888e5 100644
+--- a/arch/x86/kvm/vmx/vmx.h
++++ b/arch/x86/kvm/vmx/vmx.h
+@@ -7,10 +7,10 @@
+ #include <asm/kvm.h>
+ #include <asm/intel_pt.h>
+ #include <asm/perf_event.h>
++#include <asm/posted_intr.h>
+ 
+ #include "capabilities.h"
+ #include "../kvm_cache_regs.h"
+-#include "posted_intr.h"
+ #include "vmcs.h"
+ #include "vmx_ops.h"
+ #include "../cpuid.h"
+diff --git a/arch/x86/kvm/vmx/vmx_onhyperv.c b/arch/x86/kvm/vmx/vmx_onhyperv.c
+new file mode 100644
+index 0000000000000..b9a8b91166d02
+--- /dev/null
++++ b/arch/x86/kvm/vmx/vmx_onhyperv.c
+@@ -0,0 +1,36 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include "capabilities.h"
++#include "vmx_onhyperv.h"
++
++DEFINE_STATIC_KEY_FALSE(__kvm_is_using_evmcs);
++
++/*
++ * KVM on Hyper-V always uses the latest known eVMCSv1 revision, the assumption
++ * is: in case a feature has corresponding fields in eVMCS described and it was
++ * exposed in VMX feature MSRs, KVM is free to use it. Warn if KVM meets a
++ * feature which has no corresponding eVMCS field, this likely means that KVM
++ * needs to be updated.
++ */
++#define evmcs_check_vmcs_conf(field, ctrl)					\
++	do {									\
++		typeof(vmcs_conf->field) unsupported;				\
++										\
++		unsupported = vmcs_conf->field & ~EVMCS1_SUPPORTED_ ## ctrl;	\
++		if (unsupported) {						\
++			pr_warn_once(#field " unsupported with eVMCS: 0x%llx\n",\
++				     (u64)unsupported);				\
++			vmcs_conf->field &= EVMCS1_SUPPORTED_ ## ctrl;		\
++		}								\
++	}									\
++	while (0)
++
++void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
++{
++	evmcs_check_vmcs_conf(cpu_based_exec_ctrl, EXEC_CTRL);
++	evmcs_check_vmcs_conf(pin_based_exec_ctrl, PINCTRL);
++	evmcs_check_vmcs_conf(cpu_based_2nd_exec_ctrl, 2NDEXEC);
++	evmcs_check_vmcs_conf(cpu_based_3rd_exec_ctrl, 3RDEXEC);
++	evmcs_check_vmcs_conf(vmentry_ctrl, VMENTRY_CTRL);
++	evmcs_check_vmcs_conf(vmexit_ctrl, VMEXIT_CTRL);
++}
+diff --git a/arch/x86/kvm/vmx/vmx_onhyperv.h b/arch/x86/kvm/vmx/vmx_onhyperv.h
+new file mode 100644
+index 0000000000000..11541d272dbd8
+--- /dev/null
++++ b/arch/x86/kvm/vmx/vmx_onhyperv.h
+@@ -0,0 +1,124 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef __ARCH_X86_KVM_VMX_ONHYPERV_H__
++#define __ARCH_X86_KVM_VMX_ONHYPERV_H__
++
++#include <asm/hyperv-tlfs.h>
++
++#include <linux/jump_label.h>
++
++#include "capabilities.h"
++#include "hyperv.h"
++#include "vmcs12.h"
++
++#define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
++
++#if IS_ENABLED(CONFIG_HYPERV)
++
++DECLARE_STATIC_KEY_FALSE(__kvm_is_using_evmcs);
++
++static __always_inline bool kvm_is_using_evmcs(void)
++{
++	return static_branch_unlikely(&__kvm_is_using_evmcs);
++}
++
++static __always_inline int get_evmcs_offset(unsigned long field,
++					    u16 *clean_field)
++{
++	int offset = evmcs_field_offset(field, clean_field);
++
++	WARN_ONCE(offset < 0, "accessing unsupported EVMCS field %lx\n", field);
++	return offset;
++}
++
++static __always_inline void evmcs_write64(unsigned long field, u64 value)
++{
++	u16 clean_field;
++	int offset = get_evmcs_offset(field, &clean_field);
++
++	if (offset < 0)
++		return;
++
++	*(u64 *)((char *)current_evmcs + offset) = value;
++
++	current_evmcs->hv_clean_fields &= ~clean_field;
++}
++
++static __always_inline void evmcs_write32(unsigned long field, u32 value)
++{
++	u16 clean_field;
++	int offset = get_evmcs_offset(field, &clean_field);
++
++	if (offset < 0)
++		return;
++
++	*(u32 *)((char *)current_evmcs + offset) = value;
++	current_evmcs->hv_clean_fields &= ~clean_field;
++}
++
++static __always_inline void evmcs_write16(unsigned long field, u16 value)
++{
++	u16 clean_field;
++	int offset = get_evmcs_offset(field, &clean_field);
++
++	if (offset < 0)
++		return;
++
++	*(u16 *)((char *)current_evmcs + offset) = value;
++	current_evmcs->hv_clean_fields &= ~clean_field;
++}
++
++static __always_inline u64 evmcs_read64(unsigned long field)
++{
++	int offset = get_evmcs_offset(field, NULL);
++
++	if (offset < 0)
++		return 0;
++
++	return *(u64 *)((char *)current_evmcs + offset);
++}
++
++static __always_inline u32 evmcs_read32(unsigned long field)
++{
++	int offset = get_evmcs_offset(field, NULL);
++
++	if (offset < 0)
++		return 0;
++
++	return *(u32 *)((char *)current_evmcs + offset);
++}
++
++static __always_inline u16 evmcs_read16(unsigned long field)
++{
++	int offset = get_evmcs_offset(field, NULL);
++
++	if (offset < 0)
++		return 0;
++
++	return *(u16 *)((char *)current_evmcs + offset);
++}
++
++static inline void evmcs_load(u64 phys_addr)
++{
++	struct hv_vp_assist_page *vp_ap =
++		hv_get_vp_assist_page(smp_processor_id());
++
++	if (current_evmcs->hv_enlightenments_control.nested_flush_hypercall)
++		vp_ap->nested_control.features.directhypercall = 1;
++	vp_ap->current_nested_vmcs = phys_addr;
++	vp_ap->enlighten_vmentry = 1;
++}
++
++void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf);
++#else /* !IS_ENABLED(CONFIG_HYPERV) */
++static __always_inline bool kvm_is_using_evmcs(void) { return false; }
++static __always_inline void evmcs_write64(unsigned long field, u64 value) {}
++static __always_inline void evmcs_write32(unsigned long field, u32 value) {}
++static __always_inline void evmcs_write16(unsigned long field, u16 value) {}
++static __always_inline u64 evmcs_read64(unsigned long field) { return 0; }
++static __always_inline u32 evmcs_read32(unsigned long field) { return 0; }
++static __always_inline u16 evmcs_read16(unsigned long field) { return 0; }
++static inline void evmcs_load(u64 phys_addr) {}
++#endif /* IS_ENABLED(CONFIG_HYPERV) */
++
++#endif /* __ARCH_X86_KVM_VMX_ONHYPERV_H__ */
+diff --git a/arch/x86/kvm/vmx/vmx_ops.h b/arch/x86/kvm/vmx/vmx_ops.h
+index 6a0c6e81f7f3e..8060e5fc6dbd8 100644
+--- a/arch/x86/kvm/vmx/vmx_ops.h
++++ b/arch/x86/kvm/vmx/vmx_ops.h
+@@ -6,7 +6,7 @@
+ 
+ #include <asm/vmx.h>
+ 
+-#include "hyperv.h"
++#include "vmx_onhyperv.h"
+ #include "vmcs.h"
+ #include "../x86.h"
+ 
+diff --git a/drivers/bluetooth/btintel.c b/drivers/bluetooth/btintel.c
+index 3da3c266a66f3..a936219aebb81 100644
+--- a/drivers/bluetooth/btintel.c
++++ b/drivers/bluetooth/btintel.c
+@@ -2845,6 +2845,9 @@ static int btintel_setup_combined(struct hci_dev *hdev)
+ 		btintel_set_dsm_reset_method(hdev, &ver_tlv);
+ 
+ 		err = btintel_bootloader_setup_tlv(hdev, &ver_tlv);
++		if (err)
++			goto exit_error;
++
+ 		btintel_register_devcoredump_support(hdev);
+ 		break;
+ 	default:
+diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+index 84d7033e5efe8..ef51dfb39baa9 100644
+--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+@@ -40,10 +40,14 @@ struct qcom_cpufreq_match_data {
+ 	const char **genpd_names;
+ };
+ 
++struct qcom_cpufreq_drv_cpu {
++	int opp_token;
++};
++
+ struct qcom_cpufreq_drv {
+-	int *opp_tokens;
+ 	u32 versions;
+ 	const struct qcom_cpufreq_match_data *data;
++	struct qcom_cpufreq_drv_cpu cpus[];
+ };
+ 
+ static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
+@@ -243,42 +247,39 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
+ 		return -ENOENT;
+ 	}
+ 
+-	drv = kzalloc(sizeof(*drv), GFP_KERNEL);
+-	if (!drv)
++	drv = devm_kzalloc(&pdev->dev, struct_size(drv, cpus, num_possible_cpus()),
++		           GFP_KERNEL);
++	if (!drv) {
++		of_node_put(np);
+ 		return -ENOMEM;
++	}
+ 
+ 	match = pdev->dev.platform_data;
+ 	drv->data = match->data;
+ 	if (!drv->data) {
+-		ret = -ENODEV;
+-		goto free_drv;
++		of_node_put(np);
++		return -ENODEV;
+ 	}
+ 
+ 	if (drv->data->get_version) {
+ 		speedbin_nvmem = of_nvmem_cell_get(np, NULL);
+ 		if (IS_ERR(speedbin_nvmem)) {
+-			ret = dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
+-					    "Could not get nvmem cell\n");
+-			goto free_drv;
++			of_node_put(np);
++			return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
++					     "Could not get nvmem cell\n");
+ 		}
+ 
+ 		ret = drv->data->get_version(cpu_dev,
+ 							speedbin_nvmem, &pvs_name, drv);
+ 		if (ret) {
++			of_node_put(np);
+ 			nvmem_cell_put(speedbin_nvmem);
+-			goto free_drv;
++			return ret;
+ 		}
+ 		nvmem_cell_put(speedbin_nvmem);
+ 	}
+ 	of_node_put(np);
+ 
+-	drv->opp_tokens = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tokens),
+-				  GFP_KERNEL);
+-	if (!drv->opp_tokens) {
+-		ret = -ENOMEM;
+-		goto free_drv;
+-	}
+-
+ 	for_each_possible_cpu(cpu) {
+ 		struct dev_pm_opp_config config = {
+ 			.supported_hw = NULL,
+@@ -304,9 +305,9 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
+ 		}
+ 
+ 		if (config.supported_hw || config.genpd_names) {
+-			drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config);
+-			if (drv->opp_tokens[cpu] < 0) {
+-				ret = drv->opp_tokens[cpu];
++			drv->cpus[cpu].opp_token = dev_pm_opp_set_config(cpu_dev, &config);
++			if (drv->cpus[cpu].opp_token < 0) {
++				ret = drv->cpus[cpu].opp_token;
+ 				dev_err(cpu_dev, "Failed to set OPP config\n");
+ 				goto free_opp;
+ 			}
+@@ -325,11 +326,7 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
+ 
+ free_opp:
+ 	for_each_possible_cpu(cpu)
+-		dev_pm_opp_clear_config(drv->opp_tokens[cpu]);
+-	kfree(drv->opp_tokens);
+-free_drv:
+-	kfree(drv);
+-
++		dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
+ 	return ret;
+ }
+ 
+@@ -341,10 +338,7 @@ static void qcom_cpufreq_remove(struct platform_device *pdev)
+ 	platform_device_unregister(cpufreq_dt_pdev);
+ 
+ 	for_each_possible_cpu(cpu)
+-		dev_pm_opp_clear_config(drv->opp_tokens[cpu]);
+-
+-	kfree(drv->opp_tokens);
+-	kfree(drv);
++		dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
+ }
+ 
+ static struct platform_driver qcom_cpufreq_driver = {
+diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
+index 793f1a7ad5e34..53fdfd32a7e77 100644
+--- a/drivers/dma/fsl-edma-common.c
++++ b/drivers/dma/fsl-edma-common.c
+@@ -3,6 +3,7 @@
+ // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+ // Copyright (c) 2017 Sysam, Angelo Dureghello  <angelo@sysam.it>
+ 
++#include <linux/clk.h>
+ #include <linux/dmapool.h>
+ #include <linux/module.h>
+ #include <linux/slab.h>
+@@ -74,18 +75,10 @@ static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan)
+ 
+ 	flags = fsl_edma_drvflags(fsl_chan);
+ 	val = edma_readl_chreg(fsl_chan, ch_sbr);
+-	/* Remote/local swapped wrongly on iMX8 QM Audio edma */
+-	if (flags & FSL_EDMA_DRV_QUIRK_SWAPPED) {
+-		if (!fsl_chan->is_rxchan)
+-			val |= EDMA_V3_CH_SBR_RD;
+-		else
+-			val |= EDMA_V3_CH_SBR_WR;
+-	} else {
+-		if (fsl_chan->is_rxchan)
+-			val |= EDMA_V3_CH_SBR_RD;
+-		else
+-			val |= EDMA_V3_CH_SBR_WR;
+-	}
++	if (fsl_chan->is_rxchan)
++		val |= EDMA_V3_CH_SBR_RD;
++	else
++		val |= EDMA_V3_CH_SBR_WR;
+ 
+ 	if (fsl_chan->is_remote)
+ 		val &= ~(EDMA_V3_CH_SBR_RD | EDMA_V3_CH_SBR_WR);
+@@ -97,8 +90,8 @@ static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan)
+ 		 * ch_mux: With the exception of 0, attempts to write a value
+ 		 * already in use will be forced to 0.
+ 		 */
+-		if (!edma_readl_chreg(fsl_chan, ch_mux))
+-			edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux);
++		if (!edma_readl(fsl_chan->edma, fsl_chan->mux_addr))
++			edma_writel(fsl_chan->edma, fsl_chan->srcid, fsl_chan->mux_addr);
+ 	}
+ 
+ 	val = edma_readl_chreg(fsl_chan, ch_csr);
+@@ -134,7 +127,7 @@ static void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan)
+ 	flags = fsl_edma_drvflags(fsl_chan);
+ 
+ 	if (flags & FSL_EDMA_DRV_HAS_CHMUX)
+-		edma_writel_chreg(fsl_chan, 0, ch_mux);
++		edma_writel(fsl_chan->edma, 0, fsl_chan->mux_addr);
+ 
+ 	val &= ~EDMA_V3_CH_CSR_ERQ;
+ 	edma_writel_chreg(fsl_chan, val, ch_csr);
+@@ -754,6 +747,8 @@ struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan,
+ 	fsl_desc->iscyclic = false;
+ 
+ 	fsl_chan->is_sw = true;
++	if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_MEM_REMOTE)
++		fsl_chan->is_remote = true;
+ 
+ 	/* To match with copy_align and max_seg_size so 1 tcd is enough */
+ 	fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
+@@ -802,6 +797,9 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
+ {
+ 	struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
+ 
++	if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK)
++		clk_prepare_enable(fsl_chan->clk);
++
+ 	fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
+ 				sizeof(struct fsl_edma_hw_tcd),
+ 				32, 0);
+@@ -829,6 +827,9 @@ void fsl_edma_free_chan_resources(struct dma_chan *chan)
+ 	fsl_chan->tcd_pool = NULL;
+ 	fsl_chan->is_sw = false;
+ 	fsl_chan->srcid = 0;
++	fsl_chan->is_remote = false;
++	if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK)
++		clk_disable_unprepare(fsl_chan->clk);
+ }
+ 
+ void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
+diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
+index 92fe53faa53b1..6028389de408b 100644
+--- a/drivers/dma/fsl-edma-common.h
++++ b/drivers/dma/fsl-edma-common.h
+@@ -146,6 +146,7 @@ struct fsl_edma_chan {
+ 	enum dma_data_direction		dma_dir;
+ 	char				chan_name[32];
+ 	struct fsl_edma_hw_tcd __iomem *tcd;
++	void __iomem			*mux_addr;
+ 	u32				real_count;
+ 	struct work_struct		issue_worker;
+ 	struct platform_device		*pdev;
+@@ -177,8 +178,7 @@ struct fsl_edma_desc {
+ #define FSL_EDMA_DRV_HAS_PD		BIT(5)
+ #define FSL_EDMA_DRV_HAS_CHCLK		BIT(6)
+ #define FSL_EDMA_DRV_HAS_CHMUX		BIT(7)
+-/* imx8 QM audio edma remote local swapped */
+-#define FSL_EDMA_DRV_QUIRK_SWAPPED	BIT(8)
++#define FSL_EDMA_DRV_MEM_REMOTE		BIT(8)
+ /* control and status register is in tcd address space, edma3 reg layout */
+ #define FSL_EDMA_DRV_SPLIT_REG		BIT(9)
+ #define FSL_EDMA_DRV_BUS_8BYTE		BIT(10)
+@@ -207,6 +207,8 @@ struct fsl_edma_drvdata {
+ 	u32			chreg_off;
+ 	u32			chreg_space_sz;
+ 	u32			flags;
++	u32			mux_off;	/* channel mux register offset */
++	u32			mux_skip;	/* how much skip for each channel */
+ 	int			(*setup_irq)(struct platform_device *pdev,
+ 					     struct fsl_edma_engine *fsl_edma);
+ };
+diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
+index 42a338cbe6143..8a0ae90548997 100644
+--- a/drivers/dma/fsl-edma-main.c
++++ b/drivers/dma/fsl-edma-main.c
+@@ -340,16 +340,19 @@ static struct fsl_edma_drvdata imx7ulp_data = {
+ };
+ 
+ static struct fsl_edma_drvdata imx8qm_data = {
+-	.flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
++	.flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MEM_REMOTE,
+ 	.chreg_space_sz = 0x10000,
+ 	.chreg_off = 0x10000,
+ 	.setup_irq = fsl_edma3_irq_init,
+ };
+ 
+-static struct fsl_edma_drvdata imx8qm_audio_data = {
+-	.flags = FSL_EDMA_DRV_QUIRK_SWAPPED | FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
++static struct fsl_edma_drvdata imx8ulp_data = {
++	.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK |
++		 FSL_EDMA_DRV_EDMA3,
+ 	.chreg_space_sz = 0x10000,
+ 	.chreg_off = 0x10000,
++	.mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
++	.mux_skip = 0x10000,
+ 	.setup_irq = fsl_edma3_irq_init,
+ };
+ 
+@@ -364,6 +367,8 @@ static struct fsl_edma_drvdata imx93_data4 = {
+ 	.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4,
+ 	.chreg_space_sz = 0x8000,
+ 	.chreg_off = 0x10000,
++	.mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
++	.mux_skip = 0x8000,
+ 	.setup_irq = fsl_edma3_irq_init,
+ };
+ 
+@@ -372,7 +377,7 @@ static const struct of_device_id fsl_edma_dt_ids[] = {
+ 	{ .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
+ 	{ .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
+ 	{ .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
+-	{ .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data},
++	{ .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data},
+ 	{ .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
+ 	{ .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
+ 	{ /* sentinel */ }
+@@ -427,6 +432,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
+ 	struct fsl_edma_engine *fsl_edma;
+ 	const struct fsl_edma_drvdata *drvdata = NULL;
+ 	u32 chan_mask[2] = {0, 0};
++	char clk_name[36];
+ 	struct edma_regs *regs;
+ 	int chans;
+ 	int ret, i;
+@@ -540,12 +546,23 @@ static int fsl_edma_probe(struct platform_device *pdev)
+ 				offsetof(struct fsl_edma3_ch_reg, tcd) : 0;
+ 		fsl_chan->tcd = fsl_edma->membase
+ 				+ i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
++		fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip;
+ 
++		if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
++			snprintf(clk_name, sizeof(clk_name), "ch%02d", i);
++			fsl_chan->clk = devm_clk_get_enabled(&pdev->dev,
++							     (const char *)clk_name);
++
++			if (IS_ERR(fsl_chan->clk))
++				return PTR_ERR(fsl_chan->clk);
++		}
+ 		fsl_chan->pdev = pdev;
+ 		vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
+ 
+ 		edma_write_tcdreg(fsl_chan, 0, csr);
+ 		fsl_edma_chan_mux(fsl_chan, 0, false);
++		if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK)
++			clk_disable_unprepare(fsl_chan->clk);
+ 	}
+ 
+ 	ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
+diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
+index b59e3041fd627..f0e9f250669e2 100644
+--- a/drivers/firmware/Kconfig
++++ b/drivers/firmware/Kconfig
+@@ -229,6 +229,7 @@ config QCOM_SCM_DOWNLOAD_MODE_DEFAULT
+ config SYSFB
+ 	bool
+ 	select BOOT_VESA_SUPPORT
++	select SCREEN_INFO
+ 
+ config SYSFB_SIMPLEFB
+ 	bool "Mark VGA/VBE/EFI FB as generic system framebuffer"
+diff --git a/drivers/firmware/sysfb.c b/drivers/firmware/sysfb.c
+index 3c197db42c9d9..defd7a36cb08a 100644
+--- a/drivers/firmware/sysfb.c
++++ b/drivers/firmware/sysfb.c
+@@ -77,6 +77,8 @@ static __init int sysfb_init(void)
+ 	bool compatible;
+ 	int ret = 0;
+ 
++	screen_info_apply_fixups();
++
+ 	mutex_lock(&disable_lock);
+ 	if (disabled)
+ 		goto unlock_mutex;
+diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+index d0255ea98348d..247e7d675e2b9 100644
+--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+@@ -1556,7 +1556,7 @@ static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
+ }
+ 
+ static int
+-skl_ddi_calculate_wrpll(int clock /* in Hz */,
++skl_ddi_calculate_wrpll(int clock,
+ 			int ref_clock,
+ 			struct skl_wrpll_params *wrpll_params)
+ {
+@@ -1581,7 +1581,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
+ 	};
+ 	unsigned int dco, d, i;
+ 	unsigned int p0, p1, p2;
+-	u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
++	u64 afe_clock = (u64)clock * 1000 * 5; /* AFE Clock is 5x Pixel clock, in Hz */
+ 
+ 	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
+ 		for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
+@@ -1713,7 +1713,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
+ 
+ 	ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
+ 
+-	ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
++	ret = skl_ddi_calculate_wrpll(crtc_state->port_clock,
+ 				      i915->display.dpll.ref_clks.nssc, &wrpll_params);
+ 	if (ret)
+ 		return ret;
+diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_regs.h b/drivers/gpu/drm/i915/display/intel_hdcp_regs.h
+index 8023c85c7fa0e..74059384892af 100644
+--- a/drivers/gpu/drm/i915/display/intel_hdcp_regs.h
++++ b/drivers/gpu/drm/i915/display/intel_hdcp_regs.h
+@@ -249,7 +249,7 @@
+ #define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+ 					(GRAPHICS_VER(dev_priv) >= 12 ? \
+ 					 TRANS_HDCP2_STREAM_STATUS(trans) : \
+-					 PIPE_HDCP2_STREAM_STATUS(pipe))
++					 PIPE_HDCP2_STREAM_STATUS(port))
+ 
+ #define _PORTA_HDCP2_AUTH_STREAM		0x66F00
+ #define _PORTB_HDCP2_AUTH_STREAM		0x66F04
+diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
+index 3f90403d86cb4..0808b54d3c518 100644
+--- a/drivers/gpu/drm/i915/i915_perf.c
++++ b/drivers/gpu/drm/i915/i915_perf.c
+@@ -2781,26 +2781,6 @@ oa_configure_all_contexts(struct i915_perf_stream *stream,
+ 	return 0;
+ }
+ 
+-static int
+-gen12_configure_all_contexts(struct i915_perf_stream *stream,
+-			     const struct i915_oa_config *oa_config,
+-			     struct i915_active *active)
+-{
+-	struct flex regs[] = {
+-		{
+-			GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
+-			CTX_R_PWR_CLK_STATE,
+-		},
+-	};
+-
+-	if (stream->engine->class != RENDER_CLASS)
+-		return 0;
+-
+-	return oa_configure_all_contexts(stream,
+-					 regs, ARRAY_SIZE(regs),
+-					 active);
+-}
+-
+ static int
+ lrc_configure_all_contexts(struct i915_perf_stream *stream,
+ 			   const struct i915_oa_config *oa_config,
+@@ -2907,7 +2887,6 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
+ {
+ 	struct drm_i915_private *i915 = stream->perf->i915;
+ 	struct intel_uncore *uncore = stream->uncore;
+-	struct i915_oa_config *oa_config = stream->oa_config;
+ 	bool periodic = stream->periodic;
+ 	u32 period_exponent = stream->period_exponent;
+ 	u32 sqcnt1;
+@@ -2951,15 +2930,6 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
+ 
+ 	intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
+ 
+-	/*
+-	 * Update all contexts prior writing the mux configurations as we need
+-	 * to make sure all slices/subslices are ON before writing to NOA
+-	 * registers.
+-	 */
+-	ret = gen12_configure_all_contexts(stream, oa_config, active);
+-	if (ret)
+-		return ret;
+-
+ 	/*
+ 	 * For Gen12, performance counters are context
+ 	 * saved/restored. Only enable it for the context that
+@@ -3014,9 +2984,6 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream)
+ 				   _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
+ 	}
+ 
+-	/* Reset all contexts' slices/subslices configurations. */
+-	gen12_configure_all_contexts(stream, NULL, NULL);
+-
+ 	/* disable the context save/restore or OAR counters */
+ 	if (stream->ctx)
+ 		gen12_configure_oar_context(stream, NULL);
+diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c
+index 1b2ff0c40fc1c..6c599a9f49ee4 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
++++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
+@@ -64,7 +64,8 @@ struct drm_gem_object *nouveau_gem_prime_import_sg_table(struct drm_device *dev,
+ 	 * to the caller, instead of a normal nouveau_bo ttm reference. */
+ 	ret = drm_gem_object_init(dev, &nvbo->bo.base, size);
+ 	if (ret) {
+-		nouveau_bo_ref(NULL, &nvbo);
++		drm_gem_object_release(&nvbo->bo.base);
++		kfree(nvbo);
+ 		obj = ERR_PTR(-ENOMEM);
+ 		goto unlock;
+ 	}
+diff --git a/drivers/gpu/drm/virtio/virtgpu_submit.c b/drivers/gpu/drm/virtio/virtgpu_submit.c
+index 5c514946bbad9..d530c058f53e2 100644
+--- a/drivers/gpu/drm/virtio/virtgpu_submit.c
++++ b/drivers/gpu/drm/virtio/virtgpu_submit.c
+@@ -48,7 +48,7 @@ struct virtio_gpu_submit {
+ static int virtio_gpu_do_fence_wait(struct virtio_gpu_submit *submit,
+ 				    struct dma_fence *in_fence)
+ {
+-	u32 context = submit->fence_ctx + submit->ring_idx;
++	u64 context = submit->fence_ctx + submit->ring_idx;
+ 
+ 	if (dma_fence_match_context(in_fence, context))
+ 		return 0;
+diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
+index 5efc6a766f64e..588d50ababf60 100644
+--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
+@@ -32,7 +32,6 @@
+ #define VMW_FENCE_WRAP (1 << 31)
+ 
+ struct vmw_fence_manager {
+-	int num_fence_objects;
+ 	struct vmw_private *dev_priv;
+ 	spinlock_t lock;
+ 	struct list_head fence_list;
+@@ -124,13 +123,13 @@ static void vmw_fence_obj_destroy(struct dma_fence *f)
+ {
+ 	struct vmw_fence_obj *fence =
+ 		container_of(f, struct vmw_fence_obj, base);
+-
+ 	struct vmw_fence_manager *fman = fman_from_fence(fence);
+ 
+-	spin_lock(&fman->lock);
+-	list_del_init(&fence->head);
+-	--fman->num_fence_objects;
+-	spin_unlock(&fman->lock);
++	if (!list_empty(&fence->head)) {
++		spin_lock(&fman->lock);
++		list_del_init(&fence->head);
++		spin_unlock(&fman->lock);
++	}
+ 	fence->destroy(fence);
+ }
+ 
+@@ -257,7 +256,6 @@ static const struct dma_fence_ops vmw_fence_ops = {
+ 	.release = vmw_fence_obj_destroy,
+ };
+ 
+-
+ /*
+  * Execute signal actions on fences recently signaled.
+  * This is done from a workqueue so we don't have to execute
+@@ -355,7 +353,6 @@ static int vmw_fence_obj_init(struct vmw_fence_manager *fman,
+ 		goto out_unlock;
+ 	}
+ 	list_add_tail(&fence->head, &fman->fence_list);
+-	++fman->num_fence_objects;
+ 
+ out_unlock:
+ 	spin_unlock(&fman->lock);
+@@ -403,7 +400,7 @@ static bool vmw_fence_goal_new_locked(struct vmw_fence_manager *fman,
+ 				      u32 passed_seqno)
+ {
+ 	u32 goal_seqno;
+-	struct vmw_fence_obj *fence;
++	struct vmw_fence_obj *fence, *next_fence;
+ 
+ 	if (likely(!fman->seqno_valid))
+ 		return false;
+@@ -413,7 +410,7 @@ static bool vmw_fence_goal_new_locked(struct vmw_fence_manager *fman,
+ 		return false;
+ 
+ 	fman->seqno_valid = false;
+-	list_for_each_entry(fence, &fman->fence_list, head) {
++	list_for_each_entry_safe(fence, next_fence, &fman->fence_list, head) {
+ 		if (!list_empty(&fence->seq_passed_actions)) {
+ 			fman->seqno_valid = true;
+ 			vmw_fence_goal_write(fman->dev_priv,
+diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c b/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
+index c45b4724e4141..e20f64b67b266 100644
+--- a/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
+@@ -92,7 +92,7 @@ static int vmw_overlay_send_put(struct vmw_private *dev_priv,
+ {
+ 	struct vmw_escape_video_flush *flush;
+ 	size_t fifo_size;
+-	bool have_so = (dev_priv->active_display_unit == vmw_du_screen_object);
++	bool have_so = (dev_priv->active_display_unit != vmw_du_legacy);
+ 	int i, num_items;
+ 	SVGAGuestPtr ptr;
+ 
+diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+index 4ccab07faff08..cb03c589ab226 100644
+--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+@@ -868,6 +868,32 @@ vmw_stdu_connector_mode_valid(struct drm_connector *connector,
+ 	return MODE_OK;
+ }
+ 
++/*
++ * Trigger a modeset if the X,Y position of the Screen Target changes.
++ * This is needed when multi-mon is cycled. The original Screen Target will have
++ * the same mode but its relative X,Y position in the topology will change.
++ */
++static int vmw_stdu_connector_atomic_check(struct drm_connector *conn,
++					   struct drm_atomic_state *state)
++{
++	struct drm_connector_state *conn_state;
++	struct vmw_screen_target_display_unit *du;
++	struct drm_crtc_state *new_crtc_state;
++
++	conn_state = drm_atomic_get_connector_state(state, conn);
++	du = vmw_connector_to_stdu(conn);
++
++	if (!conn_state->crtc)
++		return 0;
++
++	new_crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
++	if (du->base.gui_x != du->base.set_gui_x ||
++	    du->base.gui_y != du->base.set_gui_y)
++		new_crtc_state->mode_changed = true;
++
++	return 0;
++}
++
+ static const struct drm_connector_funcs vmw_stdu_connector_funcs = {
+ 	.dpms = vmw_du_connector_dpms,
+ 	.detect = vmw_du_connector_detect,
+@@ -882,7 +908,8 @@ static const struct drm_connector_funcs vmw_stdu_connector_funcs = {
+ static const struct
+ drm_connector_helper_funcs vmw_stdu_connector_helper_funcs = {
+ 	.get_modes = vmw_connector_get_modes,
+-	.mode_valid = vmw_stdu_connector_mode_valid
++	.mode_valid = vmw_stdu_connector_mode_valid,
++	.atomic_check = vmw_stdu_connector_atomic_check,
+ };
+ 
+ 
+diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_client.c b/drivers/hid/amd-sfh-hid/amd_sfh_client.c
+index bdb578e0899f5..4b59687ff5d82 100644
+--- a/drivers/hid/amd-sfh-hid/amd_sfh_client.c
++++ b/drivers/hid/amd-sfh-hid/amd_sfh_client.c
+@@ -288,12 +288,22 @@ int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata)
+ 		mp2_ops->start(privdata, info);
+ 		cl_data->sensor_sts[i] = amd_sfh_wait_for_response
+ 						(privdata, cl_data->sensor_idx[i], SENSOR_ENABLED);
++
++		if (cl_data->sensor_sts[i] == SENSOR_ENABLED)
++			cl_data->is_any_sensor_enabled = true;
++	}
++
++	if (!cl_data->is_any_sensor_enabled ||
++	    (mp2_ops->discovery_status && mp2_ops->discovery_status(privdata) == 0)) {
++		dev_warn(dev, "Failed to discover, sensors not enabled is %d\n",
++			 cl_data->is_any_sensor_enabled);
++		rc = -EOPNOTSUPP;
++		goto cleanup;
+ 	}
+ 
+ 	for (i = 0; i < cl_data->num_hid_devices; i++) {
+ 		cl_data->cur_hid_dev = i;
+ 		if (cl_data->sensor_sts[i] == SENSOR_ENABLED) {
+-			cl_data->is_any_sensor_enabled = true;
+ 			rc = amdtp_hid_probe(i, cl_data);
+ 			if (rc)
+ 				goto cleanup;
+@@ -305,12 +315,6 @@ int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata)
+ 			cl_data->sensor_sts[i]);
+ 	}
+ 
+-	if (!cl_data->is_any_sensor_enabled ||
+-	   (mp2_ops->discovery_status && mp2_ops->discovery_status(privdata) == 0)) {
+-		dev_warn(dev, "Failed to discover, sensors not enabled is %d\n", cl_data->is_any_sensor_enabled);
+-		rc = -EOPNOTSUPP;
+-		goto cleanup;
+-	}
+ 	schedule_delayed_work(&cl_data->work_buffer, msecs_to_jiffies(AMD_SFH_IDLE_LOOP));
+ 	return 0;
+ 
+diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c
+index 002cbaa16bd16..d2fe14ce423e2 100644
+--- a/drivers/hid/wacom_wac.c
++++ b/drivers/hid/wacom_wac.c
+@@ -714,13 +714,12 @@ static int wacom_intuos_get_tool_type(int tool_id)
+ 	case 0x8e2: /* IntuosHT2 pen */
+ 	case 0x022:
+ 	case 0x200: /* Pro Pen 3 */
+-	case 0x04200: /* Pro Pen 3 */
+ 	case 0x10842: /* MobileStudio Pro Pro Pen slim */
+ 	case 0x14802: /* Intuos4/5 13HD/24HD Classic Pen */
+ 	case 0x16802: /* Cintiq 13HD Pro Pen */
+ 	case 0x18802: /* DTH2242 Pen */
+ 	case 0x10802: /* Intuos4/5 13HD/24HD General Pen */
+-	case 0x80842: /* Intuos Pro and Cintiq Pro 3D Pen */
++	case 0x8842: /* Intuos Pro and Cintiq Pro 3D Pen */
+ 		tool_type = BTN_TOOL_PEN;
+ 		break;
+ 
+diff --git a/drivers/leds/led-triggers.c b/drivers/leds/led-triggers.c
+index 4f5829b726a75..72fd2fe8f6fe8 100644
+--- a/drivers/leds/led-triggers.c
++++ b/drivers/leds/led-triggers.c
+@@ -194,11 +194,24 @@ int led_trigger_set(struct led_classdev *led_cdev, struct led_trigger *trig)
+ 		spin_unlock(&trig->leddev_list_lock);
+ 		led_cdev->trigger = trig;
+ 
++		/*
++		 * Some activate() calls use led_trigger_event() to initialize
++		 * the brightness of the LED for which the trigger is being set.
++		 * Ensure the led_cdev is visible on trig->led_cdevs for this.
++		 */
++		synchronize_rcu();
++
++		/*
++		 * If "set brightness to 0" is pending in workqueue,
++		 * we don't want that to be reordered after ->activate()
++		 */
++		flush_work(&led_cdev->set_brightness_work);
++
++		ret = 0;
+ 		if (trig->activate)
+ 			ret = trig->activate(led_cdev);
+ 		else
+-			ret = 0;
+-
++			led_set_brightness(led_cdev, trig->brightness);
+ 		if (ret)
+ 			goto err_activate;
+ 
+@@ -269,19 +282,6 @@ void led_trigger_set_default(struct led_classdev *led_cdev)
+ }
+ EXPORT_SYMBOL_GPL(led_trigger_set_default);
+ 
+-void led_trigger_rename_static(const char *name, struct led_trigger *trig)
+-{
+-	/* new name must be on a temporary string to prevent races */
+-	BUG_ON(name == trig->name);
+-
+-	down_write(&triggers_list_lock);
+-	/* this assumes that trig->name was originaly allocated to
+-	 * non constant storage */
+-	strcpy((char *)trig->name, name);
+-	up_write(&triggers_list_lock);
+-}
+-EXPORT_SYMBOL_GPL(led_trigger_rename_static);
+-
+ /* LED Trigger Interface */
+ 
+ int led_trigger_register(struct led_trigger *trig)
+@@ -386,6 +386,8 @@ void led_trigger_event(struct led_trigger *trig,
+ 	if (!trig)
+ 		return;
+ 
++	trig->brightness = brightness;
++
+ 	rcu_read_lock();
+ 	list_for_each_entry_rcu(led_cdev, &trig->led_cdevs, trig_list)
+ 		led_set_brightness(led_cdev, brightness);
+diff --git a/drivers/leds/trigger/ledtrig-timer.c b/drivers/leds/trigger/ledtrig-timer.c
+index b4688d1d9d2b2..1d213c999d40a 100644
+--- a/drivers/leds/trigger/ledtrig-timer.c
++++ b/drivers/leds/trigger/ledtrig-timer.c
+@@ -110,11 +110,6 @@ static int timer_trig_activate(struct led_classdev *led_cdev)
+ 		led_cdev->flags &= ~LED_INIT_DEFAULT_TRIGGER;
+ 	}
+ 
+-	/*
+-	 * If "set brightness to 0" is pending in workqueue, we don't
+-	 * want that to be reordered after blink_set()
+-	 */
+-	flush_work(&led_cdev->set_brightness_work);
+ 	led_blink_set(led_cdev, &led_cdev->blink_delay_on,
+ 		      &led_cdev->blink_delay_off);
+ 
+diff --git a/drivers/net/ethernet/intel/ice/ice_txrx.c b/drivers/net/ethernet/intel/ice/ice_txrx.c
+index 24c914015973e..49b1fa9651161 100644
+--- a/drivers/net/ethernet/intel/ice/ice_txrx.c
++++ b/drivers/net/ethernet/intel/ice/ice_txrx.c
+@@ -456,7 +456,7 @@ void ice_free_rx_ring(struct ice_rx_ring *rx_ring)
+ 	if (rx_ring->vsi->type == ICE_VSI_PF)
+ 		if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq))
+ 			xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
+-	rx_ring->xdp_prog = NULL;
++	WRITE_ONCE(rx_ring->xdp_prog, NULL);
+ 	if (rx_ring->xsk_pool) {
+ 		kfree(rx_ring->xdp_buf);
+ 		rx_ring->xdp_buf = NULL;
+diff --git a/drivers/net/ethernet/intel/ice/ice_xsk.c b/drivers/net/ethernet/intel/ice/ice_xsk.c
+index f53566cb6bfbd..67511153081ae 100644
+--- a/drivers/net/ethernet/intel/ice/ice_xsk.c
++++ b/drivers/net/ethernet/intel/ice/ice_xsk.c
+@@ -52,10 +52,8 @@ static void ice_qp_reset_stats(struct ice_vsi *vsi, u16 q_idx)
+ static void ice_qp_clean_rings(struct ice_vsi *vsi, u16 q_idx)
+ {
+ 	ice_clean_tx_ring(vsi->tx_rings[q_idx]);
+-	if (ice_is_xdp_ena_vsi(vsi)) {
+-		synchronize_rcu();
++	if (ice_is_xdp_ena_vsi(vsi))
+ 		ice_clean_tx_ring(vsi->xdp_rings[q_idx]);
+-	}
+ 	ice_clean_rx_ring(vsi->rx_rings[q_idx]);
+ }
+ 
+@@ -180,11 +178,12 @@ static int ice_qp_dis(struct ice_vsi *vsi, u16 q_idx)
+ 		usleep_range(1000, 2000);
+ 	}
+ 
++	synchronize_net();
++	netif_tx_stop_queue(netdev_get_tx_queue(vsi->netdev, q_idx));
++
+ 	ice_qvec_dis_irq(vsi, rx_ring, q_vector);
+ 	ice_qvec_toggle_napi(vsi, q_vector, false);
+ 
+-	netif_tx_stop_queue(netdev_get_tx_queue(vsi->netdev, q_idx));
+-
+ 	ice_fill_txq_meta(vsi, tx_ring, &txq_meta);
+ 	err = ice_vsi_stop_tx_ring(vsi, ICE_NO_RESET, 0, tx_ring, &txq_meta);
+ 	if (err)
+@@ -199,10 +198,8 @@ static int ice_qp_dis(struct ice_vsi *vsi, u16 q_idx)
+ 		if (err)
+ 			return err;
+ 	}
+-	err = ice_vsi_ctrl_one_rx_ring(vsi, false, q_idx, true);
+-	if (err)
+-		return err;
+ 
++	ice_vsi_ctrl_one_rx_ring(vsi, false, q_idx, false);
+ 	ice_qp_clean_rings(vsi, q_idx);
+ 	ice_qp_reset_stats(vsi, q_idx);
+ 
+@@ -1068,6 +1065,10 @@ bool ice_xmit_zc(struct ice_tx_ring *xdp_ring)
+ 
+ 	ice_clean_xdp_irq_zc(xdp_ring);
+ 
++	if (!netif_carrier_ok(xdp_ring->vsi->netdev) ||
++	    !netif_running(xdp_ring->vsi->netdev))
++		return true;
++
+ 	budget = ICE_DESC_UNUSED(xdp_ring);
+ 	budget = min_t(u16, budget, ICE_RING_QUARTER(xdp_ring));
+ 
+@@ -1111,7 +1112,7 @@ ice_xsk_wakeup(struct net_device *netdev, u32 queue_id,
+ 	struct ice_vsi *vsi = np->vsi;
+ 	struct ice_tx_ring *ring;
+ 
+-	if (test_bit(ICE_VSI_DOWN, vsi->state))
++	if (test_bit(ICE_VSI_DOWN, vsi->state) || !netif_carrier_ok(netdev))
+ 		return -ENETDOWN;
+ 
+ 	if (!ice_is_xdp_ena_vsi(vsi))
+diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c
+index e83700ad7e622..d80bbcdeb93ed 100644
+--- a/drivers/net/ethernet/intel/igc/igc_main.c
++++ b/drivers/net/ethernet/intel/igc/igc_main.c
+@@ -6208,21 +6208,6 @@ static int igc_save_qbv_schedule(struct igc_adapter *adapter,
+ 	size_t n;
+ 	int i;
+ 
+-	switch (qopt->cmd) {
+-	case TAPRIO_CMD_REPLACE:
+-		break;
+-	case TAPRIO_CMD_DESTROY:
+-		return igc_tsn_clear_schedule(adapter);
+-	case TAPRIO_CMD_STATS:
+-		igc_taprio_stats(adapter->netdev, &qopt->stats);
+-		return 0;
+-	case TAPRIO_CMD_QUEUE_STATS:
+-		igc_taprio_queue_stats(adapter->netdev, &qopt->queue_stats);
+-		return 0;
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-
+ 	if (qopt->base_time < 0)
+ 		return -ERANGE;
+ 
+@@ -6331,7 +6316,23 @@ static int igc_tsn_enable_qbv_scheduling(struct igc_adapter *adapter,
+ 	if (hw->mac.type != igc_i225)
+ 		return -EOPNOTSUPP;
+ 
+-	err = igc_save_qbv_schedule(adapter, qopt);
++	switch (qopt->cmd) {
++	case TAPRIO_CMD_REPLACE:
++		err = igc_save_qbv_schedule(adapter, qopt);
++		break;
++	case TAPRIO_CMD_DESTROY:
++		err = igc_tsn_clear_schedule(adapter);
++		break;
++	case TAPRIO_CMD_STATS:
++		igc_taprio_stats(adapter->netdev, &qopt->stats);
++		return 0;
++	case TAPRIO_CMD_QUEUE_STATS:
++		igc_taprio_queue_stats(adapter->netdev, &qopt->queue_stats);
++		return 0;
++	default:
++		return -EOPNOTSUPP;
++	}
++
+ 	if (err)
+ 		return err;
+ 
+diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+index 05f4aa11b95c3..34051c9abd97d 100644
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+@@ -953,13 +953,13 @@ static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
+ static void mvpp2_bm_pool_update_priv_fc(struct mvpp2 *priv, bool en)
+ {
+ 	struct mvpp2_port *port;
+-	int i;
++	int i, j;
+ 
+ 	for (i = 0; i < priv->port_count; i++) {
+ 		port = priv->port_list[i];
+ 		if (port->priv->percpu_pools) {
+-			for (i = 0; i < port->nrxqs; i++)
+-				mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i],
++			for (j = 0; j < port->nrxqs; j++)
++				mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[j],
+ 							port->tx_fc & en);
+ 		} else {
+ 			mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en);
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c
+index fadfa8b50bebe..8c4e3ecef5901 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c
+@@ -920,6 +920,7 @@ mlx5_tc_ct_entry_replace_rule(struct mlx5_tc_ct_priv *ct_priv,
+ 	mlx5_tc_ct_entry_destroy_mod_hdr(ct_priv, zone_rule->attr, mh);
+ 	mlx5_put_label_mapping(ct_priv, attr->ct_attr.ct_labels_id);
+ err_mod_hdr:
++	*attr = *old_attr;
+ 	kfree(old_attr);
+ err_attr:
+ 	kvfree(spec);
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c
+index ce29e31721208..de83567aae791 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c
+@@ -50,9 +50,10 @@ u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev)
+ 		    MLX5_CAP_FLOWTABLE_NIC_RX(mdev, decap))
+ 			caps |= MLX5_IPSEC_CAP_PACKET_OFFLOAD;
+ 
+-		if ((MLX5_CAP_FLOWTABLE_NIC_TX(mdev, ignore_flow_level) &&
+-		     MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ignore_flow_level)) ||
+-		    MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, ignore_flow_level))
++		if (IS_ENABLED(CONFIG_MLX5_CLS_ACT) &&
++		    ((MLX5_CAP_FLOWTABLE_NIC_TX(mdev, ignore_flow_level) &&
++		      MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ignore_flow_level)) ||
++		     MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, ignore_flow_level)))
+ 			caps |= MLX5_IPSEC_CAP_PRIO;
+ 
+ 		if (MLX5_CAP_FLOWTABLE_NIC_TX(mdev,
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+index 38263d5c98b34..50db127e6371b 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+@@ -1223,7 +1223,12 @@ int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
+ 	if (!an_changes && link_modes == eproto.admin)
+ 		goto out;
+ 
+-	mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
++	err = mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
++	if (err) {
++		netdev_err(priv->netdev, "%s: failed to set ptys reg: %d\n", __func__, err);
++		goto out;
++	}
++
+ 	mlx5_toggle_port_link(mdev);
+ 
+ out:
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c
+index 3a9cdf79403ae..6b17346aa4cef 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c
+@@ -206,6 +206,7 @@ int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
+ static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded)
+ {
+ 	struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
++	struct devlink *devlink = priv_to_devlink(dev);
+ 
+ 	/* if this is the driver that initiated the fw reset, devlink completed the reload */
+ 	if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
+@@ -217,9 +218,11 @@ static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unload
+ 			mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
+ 		else
+ 			mlx5_load_one(dev, true);
+-		devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0,
++		devl_lock(devlink);
++		devlink_remote_reload_actions_performed(devlink, 0,
+ 							BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
+ 							BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
++		devl_unlock(devlink);
+ 	}
+ }
+ 
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c
+index 612e666ec2635..e2230c8f18152 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c
+@@ -48,6 +48,7 @@ static struct mlx5_irq *
+ irq_pool_request_irq(struct mlx5_irq_pool *pool, struct irq_affinity_desc *af_desc)
+ {
+ 	struct irq_affinity_desc auto_desc = {};
++	struct mlx5_irq *irq;
+ 	u32 irq_index;
+ 	int err;
+ 
+@@ -64,9 +65,12 @@ irq_pool_request_irq(struct mlx5_irq_pool *pool, struct irq_affinity_desc *af_de
+ 		else
+ 			cpu_get(pool, cpumask_first(&af_desc->mask));
+ 	}
+-	return mlx5_irq_alloc(pool, irq_index,
+-			      cpumask_empty(&auto_desc.mask) ? af_desc : &auto_desc,
+-			      NULL);
++	irq = mlx5_irq_alloc(pool, irq_index,
++			     cpumask_empty(&auto_desc.mask) ? af_desc : &auto_desc,
++			     NULL);
++	if (IS_ERR(irq))
++		xa_erase(&pool->irqs, irq_index);
++	return irq;
+ }
+ 
+ /* Looking for the IRQ with the smallest refcount that fits req_mask.
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
+index dfc2ba6f780a2..18cf756bad8cc 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
+@@ -1512,7 +1512,7 @@ u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
+ 		goto unlock;
+ 
+ 	for (i = 0; i < ldev->ports; i++) {
+-		if (ldev->pf[MLX5_LAG_P1].netdev == slave) {
++		if (ldev->pf[i].netdev == slave) {
+ 			port = i;
+ 			break;
+ 		}
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c
+index 2237b3d01e0e5..11f11248feb8b 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/main.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c
+@@ -2130,7 +2130,6 @@ static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
+ 	/* Panic tear down fw command will stop the PCI bus communication
+ 	 * with the HCA, so the health poll is no longer needed.
+ 	 */
+-	mlx5_drain_health_wq(dev);
+ 	mlx5_stop_health_poll(dev, false);
+ 
+ 	ret = mlx5_cmd_fast_teardown_hca(dev);
+@@ -2165,6 +2164,7 @@ static void shutdown(struct pci_dev *pdev)
+ 
+ 	mlx5_core_info(dev, "Shutdown was called\n");
+ 	set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
++	mlx5_drain_health_wq(dev);
+ 	err = mlx5_try_fast_unload(dev);
+ 	if (err)
+ 		mlx5_unload_one(dev, false);
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c
+index 30218f37d5285..2028acbe85ca2 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c
+@@ -90,6 +90,7 @@ static void mlx5_sf_dev_shutdown(struct auxiliary_device *adev)
+ 	struct mlx5_core_dev *mdev = sf_dev->mdev;
+ 
+ 	set_bit(MLX5_BREAK_FW_WAIT, &mdev->intf_state);
++	mlx5_drain_health_wq(mdev);
+ 	mlx5_unload_one(mdev, false);
+ }
+ 
+diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
+index d759f3373b175..8a732edac15a0 100644
+--- a/drivers/net/ethernet/realtek/r8169_main.c
++++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -4256,7 +4256,8 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
+ 	if (unlikely(!rtl_tx_slots_avail(tp))) {
+ 		if (net_ratelimit())
+ 			netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
+-		goto err_stop_0;
++		netif_stop_queue(dev);
++		return NETDEV_TX_BUSY;
+ 	}
+ 
+ 	opts[1] = rtl8169_tx_vlan_tag(skb);
+@@ -4312,11 +4313,6 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
+ 	dev_kfree_skb_any(skb);
+ 	dev->stats.tx_dropped++;
+ 	return NETDEV_TX_OK;
+-
+-err_stop_0:
+-	netif_stop_queue(dev);
+-	dev->stats.tx_dropped++;
+-	return NETDEV_TX_BUSY;
+ }
+ 
+ static unsigned int rtl_last_frag_len(struct sk_buff *skb)
+diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+index 3297aff969c80..11e08cb8d3c3e 100644
+--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
++++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+@@ -1826,9 +1826,9 @@ static void axienet_dma_err_handler(struct work_struct *work)
+ 			   ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
+ 	axienet_set_mac_address(ndev, NULL);
+ 	axienet_set_multicast_list(ndev);
+-	axienet_setoptions(ndev, lp->options);
+ 	napi_enable(&lp->napi_rx);
+ 	napi_enable(&lp->napi_tx);
++	axienet_setoptions(ndev, lp->options);
+ }
+ 
+ /**
+diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
+index 029c82f88ee38..9a0432145645f 100644
+--- a/drivers/net/phy/micrel.c
++++ b/drivers/net/phy/micrel.c
+@@ -1293,6 +1293,8 @@ static int ksz9131_config_init(struct phy_device *phydev)
+ 	const struct device *dev_walker;
+ 	int ret;
+ 
++	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
++
+ 	dev_walker = &phydev->mdio.dev;
+ 	do {
+ 		of_node = dev_walker->of_node;
+@@ -1342,28 +1344,30 @@ static int ksz9131_config_init(struct phy_device *phydev)
+ #define MII_KSZ9131_AUTO_MDIX		0x1C
+ #define MII_KSZ9131_AUTO_MDI_SET	BIT(7)
+ #define MII_KSZ9131_AUTO_MDIX_SWAP_OFF	BIT(6)
++#define MII_KSZ9131_DIG_AXAN_STS	0x14
++#define MII_KSZ9131_DIG_AXAN_STS_LINK_DET	BIT(14)
++#define MII_KSZ9131_DIG_AXAN_STS_A_SELECT	BIT(12)
+ 
+ static int ksz9131_mdix_update(struct phy_device *phydev)
+ {
+ 	int ret;
+ 
+-	ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) {
+-		if (ret & MII_KSZ9131_AUTO_MDI_SET)
+-			phydev->mdix_ctrl = ETH_TP_MDI;
+-		else
+-			phydev->mdix_ctrl = ETH_TP_MDI_X;
++	if (phydev->mdix_ctrl != ETH_TP_MDI_AUTO) {
++		phydev->mdix = phydev->mdix_ctrl;
+ 	} else {
+-		phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
+-	}
++		ret = phy_read(phydev, MII_KSZ9131_DIG_AXAN_STS);
++		if (ret < 0)
++			return ret;
+ 
+-	if (ret & MII_KSZ9131_AUTO_MDI_SET)
+-		phydev->mdix = ETH_TP_MDI;
+-	else
+-		phydev->mdix = ETH_TP_MDI_X;
++		if (ret & MII_KSZ9131_DIG_AXAN_STS_LINK_DET) {
++			if (ret & MII_KSZ9131_DIG_AXAN_STS_A_SELECT)
++				phydev->mdix = ETH_TP_MDI;
++			else
++				phydev->mdix = ETH_TP_MDI_X;
++		} else {
++			phydev->mdix = ETH_TP_MDI_INVALID;
++		}
++	}
+ 
+ 	return 0;
+ }
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index 337899c69738e..2604d9663a5b2 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -1083,6 +1083,13 @@ static struct phy_driver realtek_drvs[] = {
+ 		.handle_interrupt = genphy_handle_interrupt_no_ack,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++	}, {
++		PHY_ID_MATCH_EXACT(0x001cc960),
++		.name		= "RTL8366S Gigabit Ethernet",
++		.suspend	= genphy_suspend,
++		.resume		= genphy_resume,
++		.read_mmd	= genphy_read_mmd_unsupported,
++		.write_mmd	= genphy_write_mmd_unsupported,
+ 	},
+ };
+ 
+diff --git a/drivers/net/usb/sr9700.c b/drivers/net/usb/sr9700.c
+index 0a662e42ed965..cb7d2f798fb43 100644
+--- a/drivers/net/usb/sr9700.c
++++ b/drivers/net/usb/sr9700.c
+@@ -179,6 +179,7 @@ static int sr_mdio_read(struct net_device *netdev, int phy_id, int loc)
+ 	struct usbnet *dev = netdev_priv(netdev);
+ 	__le16 res;
+ 	int rc = 0;
++	int err;
+ 
+ 	if (phy_id) {
+ 		netdev_dbg(netdev, "Only internal phy supported\n");
+@@ -189,11 +190,17 @@ static int sr_mdio_read(struct net_device *netdev, int phy_id, int loc)
+ 	if (loc == MII_BMSR) {
+ 		u8 value;
+ 
+-		sr_read_reg(dev, SR_NSR, &value);
++		err = sr_read_reg(dev, SR_NSR, &value);
++		if (err < 0)
++			return err;
++
+ 		if (value & NSR_LINKST)
+ 			rc = 1;
+ 	}
+-	sr_share_read_word(dev, 1, loc, &res);
++	err = sr_share_read_word(dev, 1, loc, &res);
++	if (err < 0)
++		return err;
++
+ 	if (rc == 1)
+ 		res = le16_to_cpu(res) | BMSR_LSTATUS;
+ 	else
+diff --git a/drivers/pci/search.c b/drivers/pci/search.c
+index b4c138a6ec025..53840634fbfc2 100644
+--- a/drivers/pci/search.c
++++ b/drivers/pci/search.c
+@@ -363,6 +363,37 @@ struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
+ }
+ EXPORT_SYMBOL(pci_get_class);
+ 
++/**
++ * pci_get_base_class - searching for a PCI device by matching against the base class code only
++ * @class: search for a PCI device with this base class code
++ * @from: Previous PCI device found in search, or %NULL for new search.
++ *
++ * Iterates through the list of known PCI devices. If a PCI device is found
++ * with a matching base class code, the reference count to the device is
++ * incremented. See pci_match_one_device() to figure out how does this works.
++ * A new search is initiated by passing %NULL as the @from argument.
++ * Otherwise if @from is not %NULL, searches continue from next device on the
++ * global list. The reference count for @from is always decremented if it is
++ * not %NULL.
++ *
++ * Returns:
++ * A pointer to a matched PCI device, %NULL Otherwise.
++ */
++struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from)
++{
++	struct pci_device_id id = {
++		.vendor = PCI_ANY_ID,
++		.device = PCI_ANY_ID,
++		.subvendor = PCI_ANY_ID,
++		.subdevice = PCI_ANY_ID,
++		.class_mask = 0xFF0000,
++		.class = class << 16,
++	};
++
++	return pci_get_dev_by_id(&id, from);
++}
++EXPORT_SYMBOL(pci_get_base_class);
++
+ /**
+  * pci_dev_present - Returns 1 if device matching the device list is present, 0 if not.
+  * @ids: A pointer to a null terminated list of struct pci_device_id structures
+diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
+index 5cf770a1bc312..4f6eade522024 100644
+--- a/drivers/perf/fsl_imx9_ddr_perf.c
++++ b/drivers/perf/fsl_imx9_ddr_perf.c
+@@ -476,12 +476,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
+ 	hwc->idx = counter;
+ 	hwc->state |= PERF_HES_STOPPED;
+ 
+-	if (flags & PERF_EF_START)
+-		ddr_perf_event_start(event, flags);
+-
+ 	/* read trans, write trans, read beat */
+ 	ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
+ 
++	if (flags & PERF_EF_START)
++		ddr_perf_event_start(event, flags);
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
+index ae16ecb15f2d9..901da688ea3f8 100644
+--- a/drivers/perf/riscv_pmu_sbi.c
++++ b/drivers/perf/riscv_pmu_sbi.c
+@@ -355,7 +355,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event)
+ 	 * but not in the user access mode as we want to use the other counters
+ 	 * that support sampling/filtering.
+ 	 */
+-	if (hwc->flags & PERF_EVENT_FLAG_LEGACY) {
++	if ((hwc->flags & PERF_EVENT_FLAG_LEGACY) && (event->attr.type == PERF_TYPE_HARDWARE)) {
+ 		if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES) {
+ 			cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH;
+ 			cmask = 1;
+diff --git a/drivers/platform/chrome/cros_ec_proto.c b/drivers/platform/chrome/cros_ec_proto.c
+index 475a6dd72db6b..809fabef3b44a 100644
+--- a/drivers/platform/chrome/cros_ec_proto.c
++++ b/drivers/platform/chrome/cros_ec_proto.c
+@@ -805,9 +805,11 @@ int cros_ec_get_next_event(struct cros_ec_device *ec_dev,
+ 	if (ret == -ENOPROTOOPT) {
+ 		dev_dbg(ec_dev->dev,
+ 			"GET_NEXT_EVENT returned invalid version error.\n");
++		mutex_lock(&ec_dev->lock);
+ 		ret = cros_ec_get_host_command_version_mask(ec_dev,
+ 							EC_CMD_GET_NEXT_EVENT,
+ 							&ver_mask);
++		mutex_unlock(&ec_dev->lock);
+ 		if (ret < 0 || ver_mask == 0)
+ 			/*
+ 			 * Do not change the MKBP supported version if we can't
+diff --git a/drivers/thermal/broadcom/bcm2835_thermal.c b/drivers/thermal/broadcom/bcm2835_thermal.c
+index 3acc9288b3105..3b1030fc4fbfe 100644
+--- a/drivers/thermal/broadcom/bcm2835_thermal.c
++++ b/drivers/thermal/broadcom/bcm2835_thermal.c
+@@ -185,7 +185,7 @@ static int bcm2835_thermal_probe(struct platform_device *pdev)
+ 		return err;
+ 	}
+ 
+-	data->clk = devm_clk_get(&pdev->dev, NULL);
++	data->clk = devm_clk_get_enabled(&pdev->dev, NULL);
+ 	if (IS_ERR(data->clk)) {
+ 		err = PTR_ERR(data->clk);
+ 		if (err != -EPROBE_DEFER)
+@@ -193,10 +193,6 @@ static int bcm2835_thermal_probe(struct platform_device *pdev)
+ 		return err;
+ 	}
+ 
+-	err = clk_prepare_enable(data->clk);
+-	if (err)
+-		return err;
+-
+ 	rate = clk_get_rate(data->clk);
+ 	if ((rate < 1920000) || (rate > 5000000))
+ 		dev_warn(&pdev->dev,
+@@ -211,7 +207,7 @@ static int bcm2835_thermal_probe(struct platform_device *pdev)
+ 		dev_err(&pdev->dev,
+ 			"Failed to register the thermal device: %d\n",
+ 			err);
+-		goto err_clk;
++		return err;
+ 	}
+ 
+ 	/*
+@@ -236,7 +232,7 @@ static int bcm2835_thermal_probe(struct platform_device *pdev)
+ 			dev_err(&pdev->dev,
+ 				"Not able to read trip_temp: %d\n",
+ 				err);
+-			goto err_tz;
++			return err;
+ 		}
+ 
+ 		/* set bandgap reference voltage and enable voltage regulator */
+@@ -269,32 +265,23 @@ static int bcm2835_thermal_probe(struct platform_device *pdev)
+ 	 */
+ 	err = thermal_add_hwmon_sysfs(tz);
+ 	if (err)
+-		goto err_tz;
++		return err;
+ 
+ 	bcm2835_thermal_debugfs(pdev);
+ 
+ 	return 0;
+-err_tz:
+-	devm_thermal_of_zone_unregister(&pdev->dev, tz);
+-err_clk:
+-	clk_disable_unprepare(data->clk);
+-
+-	return err;
+ }
+ 
+-static int bcm2835_thermal_remove(struct platform_device *pdev)
++static void bcm2835_thermal_remove(struct platform_device *pdev)
+ {
+ 	struct bcm2835_thermal_data *data = platform_get_drvdata(pdev);
+ 
+ 	debugfs_remove_recursive(data->debugfsdir);
+-	clk_disable_unprepare(data->clk);
+-
+-	return 0;
+ }
+ 
+ static struct platform_driver bcm2835_thermal_driver = {
+ 	.probe = bcm2835_thermal_probe,
+-	.remove = bcm2835_thermal_remove,
++	.remove_new = bcm2835_thermal_remove,
+ 	.driver = {
+ 		.name = "bcm2835_thermal",
+ 		.of_match_table = bcm2835_thermal_of_match_table,
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index b694d7669d320..1eb755a94940a 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -11,6 +11,10 @@ config APERTURE_HELPERS
+ 	  Support tracking and hand-over of aperture ownership. Required
+ 	  by graphics drivers for firmware-provided framebuffers.
+ 
++config SCREEN_INFO
++	bool
++	default n
++
+ config STI_CORE
+ 	bool
+ 	depends on PARISC
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index 6bbc039508995..6bbf87c1b579e 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -1,12 +1,16 @@
+ # SPDX-License-Identifier: GPL-2.0
+ 
+ obj-$(CONFIG_APERTURE_HELPERS)    += aperture.o
++obj-$(CONFIG_SCREEN_INFO)         += screen_info.o
+ obj-$(CONFIG_STI_CORE)            += sticore.o
+ obj-$(CONFIG_VGASTATE)            += vgastate.o
+ obj-$(CONFIG_VIDEO_CMDLINE)       += cmdline.o
+ obj-$(CONFIG_VIDEO_NOMODESET)     += nomodeset.o
+ obj-$(CONFIG_HDMI)                += hdmi.o
+ 
++screen_info-y			  := screen_info_generic.o
++screen_info-$(CONFIG_PCI)         += screen_info_pci.o
++
+ obj-$(CONFIG_VT)		  += console/
+ obj-$(CONFIG_FB_STI)		  += console/
+ obj-$(CONFIG_LOGO)		  += logo/
+diff --git a/drivers/video/fbdev/vesafb.c b/drivers/video/fbdev/vesafb.c
+index c0edceea0a793..a21581b40256c 100644
+--- a/drivers/video/fbdev/vesafb.c
++++ b/drivers/video/fbdev/vesafb.c
+@@ -243,6 +243,7 @@ static int vesafb_setup(char *options)
+ 
+ static int vesafb_probe(struct platform_device *dev)
+ {
++	struct screen_info *si = &screen_info;
+ 	struct fb_info *info;
+ 	struct vesafb_par *par;
+ 	int i, err;
+@@ -255,17 +256,17 @@ static int vesafb_probe(struct platform_device *dev)
+ 	fb_get_options("vesafb", &option);
+ 	vesafb_setup(option);
+ 
+-	if (screen_info.orig_video_isVGA != VIDEO_TYPE_VLFB)
++	if (si->orig_video_isVGA != VIDEO_TYPE_VLFB)
+ 		return -ENODEV;
+ 
+-	vga_compat = (screen_info.capabilities & 2) ? 0 : 1;
+-	vesafb_fix.smem_start = screen_info.lfb_base;
+-	vesafb_defined.bits_per_pixel = screen_info.lfb_depth;
++	vga_compat = !__screen_info_vbe_mode_nonvga(si);
++	vesafb_fix.smem_start = si->lfb_base;
++	vesafb_defined.bits_per_pixel = si->lfb_depth;
+ 	if (15 == vesafb_defined.bits_per_pixel)
+ 		vesafb_defined.bits_per_pixel = 16;
+-	vesafb_defined.xres = screen_info.lfb_width;
+-	vesafb_defined.yres = screen_info.lfb_height;
+-	vesafb_fix.line_length = screen_info.lfb_linelength;
++	vesafb_defined.xres = si->lfb_width;
++	vesafb_defined.yres = si->lfb_height;
++	vesafb_fix.line_length = si->lfb_linelength;
+ 	vesafb_fix.visual   = (vesafb_defined.bits_per_pixel == 8) ?
+ 		FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
+ 
+@@ -277,7 +278,7 @@ static int vesafb_probe(struct platform_device *dev)
+ 	/*   size_total -- all video memory we have. Used for mtrr
+ 	 *                 entries, resource allocation and bounds
+ 	 *                 checking. */
+-	size_total = screen_info.lfb_size * 65536;
++	size_total = si->lfb_size * 65536;
+ 	if (vram_total)
+ 		size_total = vram_total * 1024 * 1024;
+ 	if (size_total < size_vmode)
+@@ -297,7 +298,7 @@ static int vesafb_probe(struct platform_device *dev)
+ 	vesafb_fix.smem_len = size_remap;
+ 
+ #ifndef __i386__
+-	screen_info.vesapm_seg = 0;
++	si->vesapm_seg = 0;
+ #endif
+ 
+ 	if (!request_mem_region(vesafb_fix.smem_start, size_total, "vesafb")) {
+@@ -317,23 +318,26 @@ static int vesafb_probe(struct platform_device *dev)
+ 	par = info->par;
+ 	info->pseudo_palette = par->pseudo_palette;
+ 
+-	par->base = screen_info.lfb_base;
++	par->base = si->lfb_base;
+ 	par->size = size_total;
+ 
+ 	printk(KERN_INFO "vesafb: mode is %dx%dx%d, linelength=%d, pages=%d\n",
+-	       vesafb_defined.xres, vesafb_defined.yres, vesafb_defined.bits_per_pixel, vesafb_fix.line_length, screen_info.pages);
++	       vesafb_defined.xres, vesafb_defined.yres, vesafb_defined.bits_per_pixel,
++	       vesafb_fix.line_length, si->pages);
+ 
+-	if (screen_info.vesapm_seg) {
++	if (si->vesapm_seg) {
+ 		printk(KERN_INFO "vesafb: protected mode interface info at %04x:%04x\n",
+-		       screen_info.vesapm_seg,screen_info.vesapm_off);
++		       si->vesapm_seg, si->vesapm_off);
+ 	}
+ 
+-	if (screen_info.vesapm_seg < 0xc000)
++	if (si->vesapm_seg < 0xc000)
+ 		ypan = pmi_setpal = 0; /* not available or some DOS TSR ... */
+ 
+ 	if (ypan || pmi_setpal) {
++		unsigned long pmi_phys;
+ 		unsigned short *pmi_base;
+-		pmi_base  = (unsigned short*)phys_to_virt(((unsigned long)screen_info.vesapm_seg << 4) + screen_info.vesapm_off);
++		pmi_phys  = ((unsigned long)si->vesapm_seg << 4) + si->vesapm_off;
++		pmi_base  = (unsigned short *)phys_to_virt(pmi_phys);
+ 		pmi_start = (void*)((char*)pmi_base + pmi_base[1]);
+ 		pmi_pal   = (void*)((char*)pmi_base + pmi_base[2]);
+ 		printk(KERN_INFO "vesafb: pmi: set display start = %p, set palette = %p\n",pmi_start,pmi_pal);
+@@ -377,14 +381,14 @@ static int vesafb_probe(struct platform_device *dev)
+ 	vesafb_defined.left_margin  = (vesafb_defined.xres / 8) & 0xf8;
+ 	vesafb_defined.hsync_len    = (vesafb_defined.xres / 8) & 0xf8;
+ 
+-	vesafb_defined.red.offset    = screen_info.red_pos;
+-	vesafb_defined.red.length    = screen_info.red_size;
+-	vesafb_defined.green.offset  = screen_info.green_pos;
+-	vesafb_defined.green.length  = screen_info.green_size;
+-	vesafb_defined.blue.offset   = screen_info.blue_pos;
+-	vesafb_defined.blue.length   = screen_info.blue_size;
+-	vesafb_defined.transp.offset = screen_info.rsvd_pos;
+-	vesafb_defined.transp.length = screen_info.rsvd_size;
++	vesafb_defined.red.offset    = si->red_pos;
++	vesafb_defined.red.length    = si->red_size;
++	vesafb_defined.green.offset  = si->green_pos;
++	vesafb_defined.green.length  = si->green_size;
++	vesafb_defined.blue.offset   = si->blue_pos;
++	vesafb_defined.blue.length   = si->blue_size;
++	vesafb_defined.transp.offset = si->rsvd_pos;
++	vesafb_defined.transp.length = si->rsvd_size;
+ 
+ 	if (vesafb_defined.bits_per_pixel <= 8) {
+ 		depth = vesafb_defined.green.length;
+@@ -399,14 +403,14 @@ static int vesafb_probe(struct platform_device *dev)
+ 	       (vesafb_defined.bits_per_pixel > 8) ?
+ 	       "Truecolor" : (vga_compat || pmi_setpal) ?
+ 	       "Pseudocolor" : "Static Pseudocolor",
+-	       screen_info.rsvd_size,
+-	       screen_info.red_size,
+-	       screen_info.green_size,
+-	       screen_info.blue_size,
+-	       screen_info.rsvd_pos,
+-	       screen_info.red_pos,
+-	       screen_info.green_pos,
+-	       screen_info.blue_pos);
++	       si->rsvd_size,
++	       si->red_size,
++	       si->green_size,
++	       si->blue_size,
++	       si->rsvd_pos,
++	       si->red_pos,
++	       si->green_pos,
++	       si->blue_pos);
+ 
+ 	vesafb_fix.ypanstep  = ypan     ? 1 : 0;
+ 	vesafb_fix.ywrapstep = (ypan>1) ? 1 : 0;
+diff --git a/drivers/video/screen_info_generic.c b/drivers/video/screen_info_generic.c
+new file mode 100644
+index 0000000000000..64117c6367abb
+--- /dev/null
++++ b/drivers/video/screen_info_generic.c
+@@ -0,0 +1,146 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/export.h>
++#include <linux/ioport.h>
++#include <linux/screen_info.h>
++#include <linux/string.h>
++
++static void resource_init_named(struct resource *r,
++				resource_size_t start, resource_size_t size,
++				const char *name, unsigned int flags)
++{
++	memset(r, 0, sizeof(*r));
++
++	r->start = start;
++	r->end = start + size - 1;
++	r->name = name;
++	r->flags = flags;
++}
++
++static void resource_init_io_named(struct resource *r,
++				   resource_size_t start, resource_size_t size,
++				   const char *name)
++{
++	resource_init_named(r, start, size, name, IORESOURCE_IO);
++}
++
++static void resource_init_mem_named(struct resource *r,
++				   resource_size_t start, resource_size_t size,
++				   const char *name)
++{
++	resource_init_named(r, start, size, name, IORESOURCE_MEM);
++}
++
++static inline bool __screen_info_has_ega_gfx(unsigned int mode)
++{
++	switch (mode) {
++	case 0x0d:	/* 320x200-4 */
++	case 0x0e:	/* 640x200-4 */
++	case 0x0f:	/* 640x350-1 */
++	case 0x10:	/* 640x350-4 */
++		return true;
++	default:
++		return false;
++	}
++}
++
++static inline bool __screen_info_has_vga_gfx(unsigned int mode)
++{
++	switch (mode) {
++	case 0x10:	/* 640x480-1 */
++	case 0x12:	/* 640x480-4 */
++	case 0x13:	/* 320-200-8 */
++	case 0x6a:	/* 800x600-4 (VESA) */
++		return true;
++	default:
++		return __screen_info_has_ega_gfx(mode);
++	}
++}
++
++/**
++ * screen_info_resources() - Get resources from screen_info structure
++ * @si: the screen_info
++ * @r: pointer to an array of resource structures
++ * @num: number of elements in @r:
++ *
++ * Returns:
++ * The number of resources stored in @r on success, or a negative errno code otherwise.
++ *
++ * A call to screen_info_resources() returns the resources consumed by the
++ * screen_info's device or framebuffer. The result is stored in the caller-supplied
++ * array @r with up to @num elements. The function returns the number of
++ * initialized elements.
++ */
++ssize_t screen_info_resources(const struct screen_info *si, struct resource *r, size_t num)
++{
++	struct resource *pos = r;
++	unsigned int type = screen_info_video_type(si);
++	u64 base, size;
++
++	switch (type) {
++	case VIDEO_TYPE_MDA:
++		if (num > 0)
++			resource_init_io_named(pos++, 0x3b0, 12, "mda");
++		if (num > 1)
++			resource_init_io_named(pos++, 0x3bf, 0x01, "mda");
++		if (num > 2)
++			resource_init_mem_named(pos++, 0xb0000, 0x2000, "mda");
++		break;
++	case VIDEO_TYPE_CGA:
++		if (num > 0)
++			resource_init_io_named(pos++, 0x3d4, 0x02, "cga");
++		if (num > 1)
++			resource_init_mem_named(pos++, 0xb8000, 0x2000, "cga");
++		break;
++	case VIDEO_TYPE_EGAM:
++		if (num > 0)
++			resource_init_io_named(pos++, 0x3bf, 0x10, "ega");
++		if (num > 1)
++			resource_init_mem_named(pos++, 0xb0000, 0x8000, "ega");
++		break;
++	case VIDEO_TYPE_EGAC:
++		if (num > 0)
++			resource_init_io_named(pos++, 0x3c0, 0x20, "ega");
++		if (num > 1) {
++			if (__screen_info_has_ega_gfx(si->orig_video_mode))
++				resource_init_mem_named(pos++, 0xa0000, 0x10000, "ega");
++			else
++				resource_init_mem_named(pos++, 0xb8000, 0x8000, "ega");
++		}
++		break;
++	case VIDEO_TYPE_VGAC:
++		if (num > 0)
++			resource_init_io_named(pos++, 0x3c0, 0x20, "vga+");
++		if (num > 1) {
++			if (__screen_info_has_vga_gfx(si->orig_video_mode))
++				resource_init_mem_named(pos++, 0xa0000, 0x10000, "vga+");
++			else
++				resource_init_mem_named(pos++, 0xb8000, 0x8000, "vga+");
++		}
++		break;
++	case VIDEO_TYPE_VLFB:
++	case VIDEO_TYPE_EFI:
++		base = __screen_info_lfb_base(si);
++		if (!base)
++			break;
++		size = __screen_info_lfb_size(si, type);
++		if (!size)
++			break;
++		if (num > 0)
++			resource_init_mem_named(pos++, base, size, "lfb");
++		break;
++	case VIDEO_TYPE_PICA_S3:
++	case VIDEO_TYPE_MIPS_G364:
++	case VIDEO_TYPE_SGI:
++	case VIDEO_TYPE_TGAC:
++	case VIDEO_TYPE_SUN:
++	case VIDEO_TYPE_SUNPCI:
++	case VIDEO_TYPE_PMAC:
++	default:
++		/* not supported */
++		return -EINVAL;
++	}
++
++	return pos - r;
++}
++EXPORT_SYMBOL(screen_info_resources);
+diff --git a/drivers/video/screen_info_pci.c b/drivers/video/screen_info_pci.c
+new file mode 100644
+index 0000000000000..6c58335171410
+--- /dev/null
++++ b/drivers/video/screen_info_pci.c
+@@ -0,0 +1,136 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/pci.h>
++#include <linux/printk.h>
++#include <linux/screen_info.h>
++#include <linux/string.h>
++
++static struct pci_dev *screen_info_lfb_pdev;
++static size_t screen_info_lfb_bar;
++static resource_size_t screen_info_lfb_offset;
++static struct resource screen_info_lfb_res = DEFINE_RES_MEM(0, 0);
++
++static bool __screen_info_relocation_is_valid(const struct screen_info *si, struct resource *pr)
++{
++	u64 size = __screen_info_lfb_size(si, screen_info_video_type(si));
++
++	if (screen_info_lfb_offset > resource_size(pr))
++		return false;
++	if (size > resource_size(pr))
++		return false;
++	if (resource_size(pr) - size < screen_info_lfb_offset)
++		return false;
++
++	return true;
++}
++
++void screen_info_apply_fixups(void)
++{
++	struct screen_info *si = &screen_info;
++
++	if (screen_info_lfb_pdev) {
++		struct resource *pr = &screen_info_lfb_pdev->resource[screen_info_lfb_bar];
++
++		if (pr->start != screen_info_lfb_res.start) {
++			if (__screen_info_relocation_is_valid(si, pr)) {
++				/*
++				 * Only update base if we have an actual
++				 * relocation to a valid I/O range.
++				 */
++				__screen_info_set_lfb_base(si, pr->start + screen_info_lfb_offset);
++				pr_info("Relocating firmware framebuffer to offset %pa[d] within %pr\n",
++					&screen_info_lfb_offset, pr);
++			} else {
++				pr_warn("Invalid relocating, disabling firmware framebuffer\n");
++			}
++		}
++	}
++}
++
++static void screen_info_fixup_lfb(struct pci_dev *pdev)
++{
++	unsigned int type;
++	struct resource res[SCREEN_INFO_MAX_RESOURCES];
++	size_t i, numres;
++	int ret;
++	const struct screen_info *si = &screen_info;
++
++	if (screen_info_lfb_pdev)
++		return; // already found
++
++	type = screen_info_video_type(si);
++	if (type != VIDEO_TYPE_EFI)
++		return; // only applies to EFI
++
++	ret = screen_info_resources(si, res, ARRAY_SIZE(res));
++	if (ret < 0)
++		return;
++	numres = ret;
++
++	for (i = 0; i < numres; ++i) {
++		struct resource *r = &res[i];
++		const struct resource *pr;
++
++		if (!(r->flags & IORESOURCE_MEM))
++			continue;
++		pr = pci_find_resource(pdev, r);
++		if (!pr)
++			continue;
++
++		/*
++		 * We've found a PCI device with the framebuffer
++		 * resource. Store away the parameters to track
++		 * relocation of the framebuffer aperture.
++		 */
++		screen_info_lfb_pdev = pdev;
++		screen_info_lfb_bar = pr - pdev->resource;
++		screen_info_lfb_offset = r->start - pr->start;
++		memcpy(&screen_info_lfb_res, r, sizeof(screen_info_lfb_res));
++	}
++}
++DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY, 16,
++			       screen_info_fixup_lfb);
++
++static struct pci_dev *__screen_info_pci_dev(struct resource *res)
++{
++	struct pci_dev *pdev = NULL;
++	const struct resource *r = NULL;
++
++	if (!(res->flags & IORESOURCE_MEM))
++		return NULL;
++
++	while (!r && (pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
++		r = pci_find_resource(pdev, res);
++	}
++
++	return pdev;
++}
++
++/**
++ * screen_info_pci_dev() - Return PCI parent device that contains screen_info's framebuffer
++ * @si: the screen_info
++ *
++ * Returns:
++ * The screen_info's parent device or NULL on success, or a pointer-encoded
++ * errno value otherwise. The value NULL is not an error. It signals that no
++ * PCI device has been found.
++ */
++struct pci_dev *screen_info_pci_dev(const struct screen_info *si)
++{
++	struct resource res[SCREEN_INFO_MAX_RESOURCES];
++	ssize_t i, numres;
++
++	numres = screen_info_resources(si, res, ARRAY_SIZE(res));
++	if (numres < 0)
++		return ERR_PTR(numres);
++
++	for (i = 0; i < numres; ++i) {
++		struct pci_dev *pdev = __screen_info_pci_dev(&res[i]);
++
++		if (pdev)
++			return pdev;
++	}
++
++	return NULL;
++}
++EXPORT_SYMBOL(screen_info_pci_dev);
+diff --git a/fs/btrfs/block-group.c b/fs/btrfs/block-group.c
+index dd065349fae3a..4e999e1c14075 100644
+--- a/fs/btrfs/block-group.c
++++ b/fs/btrfs/block-group.c
+@@ -1214,8 +1214,8 @@ int btrfs_remove_block_group(struct btrfs_trans_handle *trans,
+ 	block_group->space_info->total_bytes -= block_group->length;
+ 	block_group->space_info->bytes_readonly -=
+ 		(block_group->length - block_group->zone_unusable);
+-	block_group->space_info->bytes_zone_unusable -=
+-		block_group->zone_unusable;
++	btrfs_space_info_update_bytes_zone_unusable(fs_info, block_group->space_info,
++						    -block_group->zone_unusable);
+ 	block_group->space_info->disk_total -= block_group->length * factor;
+ 
+ 	spin_unlock(&block_group->space_info->lock);
+@@ -1399,7 +1399,8 @@ static int inc_block_group_ro(struct btrfs_block_group *cache, int force)
+ 		if (btrfs_is_zoned(cache->fs_info)) {
+ 			/* Migrate zone_unusable bytes to readonly */
+ 			sinfo->bytes_readonly += cache->zone_unusable;
+-			sinfo->bytes_zone_unusable -= cache->zone_unusable;
++			btrfs_space_info_update_bytes_zone_unusable(cache->fs_info, sinfo,
++								    -cache->zone_unusable);
+ 			cache->zone_unusable = 0;
+ 		}
+ 		cache->ro++;
+@@ -3023,9 +3024,11 @@ void btrfs_dec_block_group_ro(struct btrfs_block_group *cache)
+ 		if (btrfs_is_zoned(cache->fs_info)) {
+ 			/* Migrate zone_unusable bytes back */
+ 			cache->zone_unusable =
+-				(cache->alloc_offset - cache->used) +
++				(cache->alloc_offset - cache->used - cache->pinned -
++				 cache->reserved) +
+ 				(cache->length - cache->zone_capacity);
+-			sinfo->bytes_zone_unusable += cache->zone_unusable;
++			btrfs_space_info_update_bytes_zone_unusable(cache->fs_info, sinfo,
++								    cache->zone_unusable);
+ 			sinfo->bytes_readonly -= cache->zone_unusable;
+ 		}
+ 		num_bytes = cache->length - cache->reserved -
+diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c
+index b89b558b15926..c6ecfd05e1db9 100644
+--- a/fs/btrfs/extent-tree.c
++++ b/fs/btrfs/extent-tree.c
+@@ -2749,7 +2749,8 @@ static int unpin_extent_range(struct btrfs_fs_info *fs_info,
+ 			readonly = true;
+ 		} else if (btrfs_is_zoned(fs_info)) {
+ 			/* Need reset before reusing in a zoned block group */
+-			space_info->bytes_zone_unusable += len;
++			btrfs_space_info_update_bytes_zone_unusable(fs_info, space_info,
++								    len);
+ 			readonly = true;
+ 		}
+ 		spin_unlock(&cache->lock);
+diff --git a/fs/btrfs/free-space-cache.c b/fs/btrfs/free-space-cache.c
+index dcfc0425115e9..f59e599766662 100644
+--- a/fs/btrfs/free-space-cache.c
++++ b/fs/btrfs/free-space-cache.c
+@@ -2721,8 +2721,10 @@ static int __btrfs_add_free_space_zoned(struct btrfs_block_group *block_group,
+ 	 * If the block group is read-only, we should account freed space into
+ 	 * bytes_readonly.
+ 	 */
+-	if (!block_group->ro)
++	if (!block_group->ro) {
+ 		block_group->zone_unusable += to_unusable;
++		WARN_ON(block_group->zone_unusable > block_group->length);
++	}
+ 	spin_unlock(&ctl->tree_lock);
+ 	if (!used) {
+ 		spin_lock(&block_group->lock);
+diff --git a/fs/btrfs/space-info.c b/fs/btrfs/space-info.c
+index 3f7a9605e2d3a..581bdd709ee0d 100644
+--- a/fs/btrfs/space-info.c
++++ b/fs/btrfs/space-info.c
+@@ -312,7 +312,7 @@ void btrfs_add_bg_to_space_info(struct btrfs_fs_info *info,
+ 	found->bytes_used += block_group->used;
+ 	found->disk_used += block_group->used * factor;
+ 	found->bytes_readonly += block_group->bytes_super;
+-	found->bytes_zone_unusable += block_group->zone_unusable;
++	btrfs_space_info_update_bytes_zone_unusable(info, found, block_group->zone_unusable);
+ 	if (block_group->length > 0)
+ 		found->full = 0;
+ 	btrfs_try_granting_tickets(info, found);
+@@ -524,8 +524,7 @@ void btrfs_dump_space_info(struct btrfs_fs_info *fs_info,
+ 
+ 		spin_lock(&cache->lock);
+ 		avail = cache->length - cache->used - cache->pinned -
+-			cache->reserved - cache->delalloc_bytes -
+-			cache->bytes_super - cache->zone_unusable;
++			cache->reserved - cache->bytes_super - cache->zone_unusable;
+ 		btrfs_info(fs_info,
+ "block group %llu has %llu bytes, %llu used %llu pinned %llu reserved %llu delalloc %llu super %llu zone_unusable (%llu bytes available) %s",
+ 			   cache->start, cache->length, cache->used, cache->pinned,
+diff --git a/fs/btrfs/space-info.h b/fs/btrfs/space-info.h
+index 0bb9d14e60a82..08a3bd10addcf 100644
+--- a/fs/btrfs/space-info.h
++++ b/fs/btrfs/space-info.h
+@@ -197,6 +197,7 @@ btrfs_space_info_update_##name(struct btrfs_fs_info *fs_info,		\
+ 
+ DECLARE_SPACE_INFO_UPDATE(bytes_may_use, "space_info");
+ DECLARE_SPACE_INFO_UPDATE(bytes_pinned, "pinned");
++DECLARE_SPACE_INFO_UPDATE(bytes_zone_unusable, "zone_unusable");
+ 
+ int btrfs_init_space_info(struct btrfs_fs_info *fs_info);
+ void btrfs_add_bg_to_space_info(struct btrfs_fs_info *info,
+diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c
+index d5eb8d44c6c81..cef119a2476bb 100644
+--- a/fs/ext4/inode.c
++++ b/fs/ext4/inode.c
+@@ -453,6 +453,35 @@ static void ext4_map_blocks_es_recheck(handle_t *handle,
+ }
+ #endif /* ES_AGGRESSIVE_TEST */
+ 
++static int ext4_map_query_blocks(handle_t *handle, struct inode *inode,
++				 struct ext4_map_blocks *map)
++{
++	unsigned int status;
++	int retval;
++
++	if (ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS))
++		retval = ext4_ext_map_blocks(handle, inode, map, 0);
++	else
++		retval = ext4_ind_map_blocks(handle, inode, map, 0);
++
++	if (retval <= 0)
++		return retval;
++
++	if (unlikely(retval != map->m_len)) {
++		ext4_warning(inode->i_sb,
++			     "ES len assertion failed for inode "
++			     "%lu: retval %d != map->m_len %d",
++			     inode->i_ino, retval, map->m_len);
++		WARN_ON(1);
++	}
++
++	status = map->m_flags & EXT4_MAP_UNWRITTEN ?
++			EXTENT_STATUS_UNWRITTEN : EXTENT_STATUS_WRITTEN;
++	ext4_es_insert_extent(inode, map->m_lblk, map->m_len,
++			      map->m_pblk, status);
++	return retval;
++}
++
+ /*
+  * The ext4_map_blocks() function tries to look up the requested blocks,
+  * and returns if the blocks are already mapped.
+@@ -1705,12 +1734,10 @@ static int ext4_da_map_blocks(struct inode *inode, sector_t iblock,
+ 
+ 	/* Lookup extent status tree firstly */
+ 	if (ext4_es_lookup_extent(inode, iblock, NULL, &es)) {
+-		if (ext4_es_is_hole(&es)) {
+-			retval = 0;
+-			down_read(&EXT4_I(inode)->i_data_sem);
++		if (ext4_es_is_hole(&es))
+ 			goto add_delayed;
+-		}
+ 
++found:
+ 		/*
+ 		 * Delayed extent could be allocated by fallocate.
+ 		 * So we need to check it.
+@@ -1747,49 +1774,42 @@ static int ext4_da_map_blocks(struct inode *inode, sector_t iblock,
+ 	down_read(&EXT4_I(inode)->i_data_sem);
+ 	if (ext4_has_inline_data(inode))
+ 		retval = 0;
+-	else if (ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS))
+-		retval = ext4_ext_map_blocks(NULL, inode, map, 0);
+ 	else
+-		retval = ext4_ind_map_blocks(NULL, inode, map, 0);
++		retval = ext4_map_query_blocks(NULL, inode, map);
++	up_read(&EXT4_I(inode)->i_data_sem);
++	if (retval)
++		return retval;
+ 
+ add_delayed:
+-	if (retval == 0) {
+-		int ret;
+-
+-		/*
+-		 * XXX: __block_prepare_write() unmaps passed block,
+-		 * is it OK?
+-		 */
+-
+-		ret = ext4_insert_delayed_block(inode, map->m_lblk);
+-		if (ret != 0) {
+-			retval = ret;
+-			goto out_unlock;
++	down_write(&EXT4_I(inode)->i_data_sem);
++	/*
++	 * Page fault path (ext4_page_mkwrite does not take i_rwsem)
++	 * and fallocate path (no folio lock) can race. Make sure we
++	 * lookup the extent status tree here again while i_data_sem
++	 * is held in write mode, before inserting a new da entry in
++	 * the extent status tree.
++	 */
++	if (ext4_es_lookup_extent(inode, iblock, NULL, &es)) {
++		if (!ext4_es_is_hole(&es)) {
++			up_write(&EXT4_I(inode)->i_data_sem);
++			goto found;
+ 		}
+-
+-		map_bh(bh, inode->i_sb, invalid_block);
+-		set_buffer_new(bh);
+-		set_buffer_delay(bh);
+-	} else if (retval > 0) {
+-		unsigned int status;
+-
+-		if (unlikely(retval != map->m_len)) {
+-			ext4_warning(inode->i_sb,
+-				     "ES len assertion failed for inode "
+-				     "%lu: retval %d != map->m_len %d",
+-				     inode->i_ino, retval, map->m_len);
+-			WARN_ON(1);
++	} else if (!ext4_has_inline_data(inode)) {
++		retval = ext4_map_query_blocks(NULL, inode, map);
++		if (retval) {
++			up_write(&EXT4_I(inode)->i_data_sem);
++			return retval;
+ 		}
+-
+-		status = map->m_flags & EXT4_MAP_UNWRITTEN ?
+-				EXTENT_STATUS_UNWRITTEN : EXTENT_STATUS_WRITTEN;
+-		ext4_es_insert_extent(inode, map->m_lblk, map->m_len,
+-				      map->m_pblk, status);
+ 	}
+ 
+-out_unlock:
+-	up_read((&EXT4_I(inode)->i_data_sem));
++	retval = ext4_insert_delayed_block(inode, map->m_lblk);
++	up_write(&EXT4_I(inode)->i_data_sem);
++	if (retval)
++		return retval;
+ 
++	map_bh(bh, inode->i_sb, invalid_block);
++	set_buffer_new(bh);
++	set_buffer_delay(bh);
+ 	return retval;
+ }
+ 
+diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c
+index 22080606b8769..804958c6de34c 100644
+--- a/fs/f2fs/segment.c
++++ b/fs/f2fs/segment.c
+@@ -3350,7 +3350,9 @@ static int __get_segment_type_6(struct f2fs_io_info *fio)
+ 		if (page_private_gcing(fio->page)) {
+ 			if (fio->sbi->am.atgc_enabled &&
+ 				(fio->io_type == FS_DATA_IO) &&
+-				(fio->sbi->gc_mode != GC_URGENT_HIGH))
++				(fio->sbi->gc_mode != GC_URGENT_HIGH) &&
++				__is_valid_data_blkaddr(fio->old_blkaddr) &&
++				!is_inode_flag_set(inode, FI_OPU_WRITE))
+ 				return CURSEG_ALL_DATA_ATGC;
+ 			else
+ 				return CURSEG_COLD_DATA;
+diff --git a/fs/file.c b/fs/file.c
+index a815f6eddc511..b64a84137c00f 100644
+--- a/fs/file.c
++++ b/fs/file.c
+@@ -1124,6 +1124,7 @@ __releases(&files->file_lock)
+ 	 * tables and this condition does not arise without those.
+ 	 */
+ 	fdt = files_fdtable(files);
++	fd = array_index_nospec(fd, fdt->max_fds);
+ 	tofree = fdt->fd[fd];
+ 	if (!tofree && fd_is_open(fd, fdt))
+ 		goto Ebusy;
+diff --git a/fs/proc/proc_sysctl.c b/fs/proc/proc_sysctl.c
+index 5b5cdc747cef3..071a71eb1a2d4 100644
+--- a/fs/proc/proc_sysctl.c
++++ b/fs/proc/proc_sysctl.c
+@@ -480,12 +480,10 @@ static struct inode *proc_sys_make_inode(struct super_block *sb,
+ 			make_empty_dir_inode(inode);
+ 	}
+ 
++	inode->i_uid = GLOBAL_ROOT_UID;
++	inode->i_gid = GLOBAL_ROOT_GID;
+ 	if (root->set_ownership)
+-		root->set_ownership(head, table, &inode->i_uid, &inode->i_gid);
+-	else {
+-		inode->i_uid = GLOBAL_ROOT_UID;
+-		inode->i_gid = GLOBAL_ROOT_GID;
+-	}
++		root->set_ownership(head, &inode->i_uid, &inode->i_gid);
+ 
+ 	return inode;
+ }
+diff --git a/include/linux/leds.h b/include/linux/leds.h
+index aa16dc2a8230f..d3056bc6f0a1a 100644
+--- a/include/linux/leds.h
++++ b/include/linux/leds.h
+@@ -474,6 +474,9 @@ struct led_trigger {
+ 	int		(*activate)(struct led_classdev *led_cdev);
+ 	void		(*deactivate)(struct led_classdev *led_cdev);
+ 
++	/* Brightness set by led_trigger_event */
++	enum led_brightness brightness;
++
+ 	/* LED-private triggers have this set */
+ 	struct led_hw_trigger_type *trigger_type;
+ 
+@@ -527,22 +530,11 @@ static inline void *led_get_trigger_data(struct led_classdev *led_cdev)
+ 	return led_cdev->trigger_data;
+ }
+ 
+-/**
+- * led_trigger_rename_static - rename a trigger
+- * @name: the new trigger name
+- * @trig: the LED trigger to rename
+- *
+- * Change a LED trigger name by copying the string passed in
+- * name into current trigger name, which MUST be large
+- * enough for the new string.
+- *
+- * Note that name must NOT point to the same string used
+- * during LED registration, as that could lead to races.
+- *
+- * This is meant to be used on triggers with statically
+- * allocated name.
+- */
+-void led_trigger_rename_static(const char *name, struct led_trigger *trig);
++static inline enum led_brightness
++led_trigger_get_brightness(const struct led_trigger *trigger)
++{
++	return trigger ? trigger->brightness : LED_OFF;
++}
+ 
+ #define module_led_trigger(__led_trigger) \
+ 	module_driver(__led_trigger, led_trigger_register, \
+@@ -580,6 +572,12 @@ static inline void *led_get_trigger_data(struct led_classdev *led_cdev)
+ 	return NULL;
+ }
+ 
++static inline enum led_brightness
++led_trigger_get_brightness(const struct led_trigger *trigger)
++{
++	return LED_OFF;
++}
++
+ #endif /* CONFIG_LEDS_TRIGGERS */
+ 
+ /* Trigger specific enum */
+diff --git a/include/linux/pci.h b/include/linux/pci.h
+index f141300116219..7b18a4b3efb0e 100644
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -1182,6 +1182,8 @@ struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
+ struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
+ 					    unsigned int devfn);
+ struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
++struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from);
++
+ int pci_dev_present(const struct pci_device_id *ids);
+ 
+ int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
+@@ -1958,6 +1960,9 @@ static inline struct pci_dev *pci_get_class(unsigned int class,
+ 					    struct pci_dev *from)
+ { return NULL; }
+ 
++static inline struct pci_dev *pci_get_base_class(unsigned int class,
++						 struct pci_dev *from)
++{ return NULL; }
+ 
+ static inline int pci_dev_present(const struct pci_device_id *ids)
+ { return 0; }
+diff --git a/include/linux/screen_info.h b/include/linux/screen_info.h
+index eab7081392d50..6a4a3cec4638b 100644
+--- a/include/linux/screen_info.h
++++ b/include/linux/screen_info.h
+@@ -4,6 +4,142 @@
+ 
+ #include <uapi/linux/screen_info.h>
+ 
++#include <linux/bits.h>
++
++/**
++ * SCREEN_INFO_MAX_RESOURCES - maximum number of resources per screen_info
++ */
++#define SCREEN_INFO_MAX_RESOURCES	3
++
++struct pci_dev;
++struct resource;
++
++static inline bool __screen_info_has_lfb(unsigned int type)
++{
++	return (type == VIDEO_TYPE_VLFB) || (type == VIDEO_TYPE_EFI);
++}
++
++static inline u64 __screen_info_lfb_base(const struct screen_info *si)
++{
++	u64 lfb_base = si->lfb_base;
++
++	if (si->capabilities & VIDEO_CAPABILITY_64BIT_BASE)
++		lfb_base |= (u64)si->ext_lfb_base << 32;
++
++	return lfb_base;
++}
++
++static inline void __screen_info_set_lfb_base(struct screen_info *si, u64 lfb_base)
++{
++	si->lfb_base = lfb_base & GENMASK_ULL(31, 0);
++	si->ext_lfb_base = (lfb_base & GENMASK_ULL(63, 32)) >> 32;
++
++	if (si->ext_lfb_base)
++		si->capabilities |= VIDEO_CAPABILITY_64BIT_BASE;
++	else
++		si->capabilities &= ~VIDEO_CAPABILITY_64BIT_BASE;
++}
++
++static inline u64 __screen_info_lfb_size(const struct screen_info *si, unsigned int type)
++{
++	u64 lfb_size = si->lfb_size;
++
++	if (type == VIDEO_TYPE_VLFB)
++		lfb_size <<= 16;
++	return lfb_size;
++}
++
++static inline bool __screen_info_vbe_mode_nonvga(const struct screen_info *si)
++{
++	/*
++	 * VESA modes typically run on VGA hardware. Set bit 5 signals that this
++	 * is not the case. Drivers can then not make use of VGA resources. See
++	 * Sec 4.4 of the VBE 2.0 spec.
++	 */
++	return si->vesa_attributes & BIT(5);
++}
++
++static inline unsigned int __screen_info_video_type(unsigned int type)
++{
++	switch (type) {
++	case VIDEO_TYPE_MDA:
++	case VIDEO_TYPE_CGA:
++	case VIDEO_TYPE_EGAM:
++	case VIDEO_TYPE_EGAC:
++	case VIDEO_TYPE_VGAC:
++	case VIDEO_TYPE_VLFB:
++	case VIDEO_TYPE_PICA_S3:
++	case VIDEO_TYPE_MIPS_G364:
++	case VIDEO_TYPE_SGI:
++	case VIDEO_TYPE_TGAC:
++	case VIDEO_TYPE_SUN:
++	case VIDEO_TYPE_SUNPCI:
++	case VIDEO_TYPE_PMAC:
++	case VIDEO_TYPE_EFI:
++		return type;
++	default:
++		return 0;
++	}
++}
++
++/**
++ * screen_info_video_type() - Decodes the video type from struct screen_info
++ * @si: an instance of struct screen_info
++ *
++ * Returns:
++ * A VIDEO_TYPE_ constant representing si's type of video display, or 0 otherwise.
++ */
++static inline unsigned int screen_info_video_type(const struct screen_info *si)
++{
++	unsigned int type;
++
++	// check if display output is on
++	if (!si->orig_video_isVGA)
++		return 0;
++
++	// check for a known VIDEO_TYPE_ constant
++	type = __screen_info_video_type(si->orig_video_isVGA);
++	if (type)
++		return si->orig_video_isVGA;
++
++	// check if text mode has been initialized
++	if (!si->orig_video_lines || !si->orig_video_cols)
++		return 0;
++
++	// 80x25 text, mono
++	if (si->orig_video_mode == 0x07) {
++		if ((si->orig_video_ega_bx & 0xff) != 0x10)
++			return VIDEO_TYPE_EGAM;
++		else
++			return VIDEO_TYPE_MDA;
++	}
++
++	// EGA/VGA, 16 colors
++	if ((si->orig_video_ega_bx & 0xff) != 0x10) {
++		if (si->orig_video_isVGA)
++			return VIDEO_TYPE_VGAC;
++		else
++			return VIDEO_TYPE_EGAC;
++	}
++
++	// the rest...
++	return VIDEO_TYPE_CGA;
++}
++
++ssize_t screen_info_resources(const struct screen_info *si, struct resource *r, size_t num);
++
++#if defined(CONFIG_PCI)
++void screen_info_apply_fixups(void);
++struct pci_dev *screen_info_pci_dev(const struct screen_info *si);
++#else
++static inline void screen_info_apply_fixups(void)
++{ }
++static inline struct pci_dev *screen_info_pci_dev(const struct screen_info *si)
++{
++	return NULL;
++}
++#endif
++
+ extern struct screen_info screen_info;
+ 
+ #endif /* _SCREEN_INFO_H */
+diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
+index 61b40ea81f4d3..698a71422a14b 100644
+--- a/include/linux/sysctl.h
++++ b/include/linux/sysctl.h
+@@ -205,7 +205,6 @@ struct ctl_table_root {
+ 	struct ctl_table_set default_set;
+ 	struct ctl_table_set *(*lookup)(struct ctl_table_root *root);
+ 	void (*set_ownership)(struct ctl_table_header *head,
+-			      struct ctl_table *table,
+ 			      kuid_t *uid, kgid_t *gid);
+ 	int (*permissions)(struct ctl_table_header *head, struct ctl_table *table);
+ };
+diff --git a/include/trace/events/btrfs.h b/include/trace/events/btrfs.h
+index b2db2c2f1c577..3c4d5ef6d4463 100644
+--- a/include/trace/events/btrfs.h
++++ b/include/trace/events/btrfs.h
+@@ -2430,6 +2430,14 @@ DEFINE_EVENT(btrfs__space_info_update, update_bytes_pinned,
+ 	TP_ARGS(fs_info, sinfo, old, diff)
+ );
+ 
++DEFINE_EVENT(btrfs__space_info_update, update_bytes_zone_unusable,
++
++	TP_PROTO(const struct btrfs_fs_info *fs_info,
++		 const struct btrfs_space_info *sinfo, u64 old, s64 diff),
++
++	TP_ARGS(fs_info, sinfo, old, diff)
++);
++
+ DECLARE_EVENT_CLASS(btrfs_raid56_bio,
+ 
+ 	TP_PROTO(const struct btrfs_raid_bio *rbio,
+diff --git a/include/trace/events/mptcp.h b/include/trace/events/mptcp.h
+index 563e48617374d..54e8fb5a229cd 100644
+--- a/include/trace/events/mptcp.h
++++ b/include/trace/events/mptcp.h
+@@ -34,7 +34,7 @@ TRACE_EVENT(mptcp_subflow_get_send,
+ 		struct sock *ssk;
+ 
+ 		__entry->active = mptcp_subflow_active(subflow);
+-		__entry->backup = subflow->backup;
++		__entry->backup = subflow->backup || subflow->request_bkup;
+ 
+ 		if (subflow->tcp_sock && sk_fullsock(subflow->tcp_sock))
+ 			__entry->free = sk_stream_memory_free(subflow->tcp_sock);
+diff --git a/init/Kconfig b/init/Kconfig
+index e403a29256357..e173364abd6c0 100644
+--- a/init/Kconfig
++++ b/init/Kconfig
+@@ -1898,6 +1898,7 @@ config RUST
+ 	depends on !MODVERSIONS
+ 	depends on !GCC_PLUGINS
+ 	depends on !RANDSTRUCT
++	depends on !SHADOW_CALL_STACK
+ 	depends on !DEBUG_INFO_BTF || PAHOLE_HAS_LANG_EXCLUDE
+ 	help
+ 	  Enables Rust support in the kernel.
+diff --git a/ipc/ipc_sysctl.c b/ipc/ipc_sysctl.c
+index 8c62e443f78b3..b2f39a86f4734 100644
+--- a/ipc/ipc_sysctl.c
++++ b/ipc/ipc_sysctl.c
+@@ -14,6 +14,7 @@
+ #include <linux/ipc_namespace.h>
+ #include <linux/msg.h>
+ #include <linux/slab.h>
++#include <linux/cred.h>
+ #include "util.h"
+ 
+ static int proc_ipc_dointvec_minmax_orphans(struct ctl_table *table, int write,
+@@ -190,25 +191,56 @@ static int set_is_seen(struct ctl_table_set *set)
+ 	return &current->nsproxy->ipc_ns->ipc_set == set;
+ }
+ 
++static void ipc_set_ownership(struct ctl_table_header *head,
++			      kuid_t *uid, kgid_t *gid)
++{
++	struct ipc_namespace *ns =
++		container_of(head->set, struct ipc_namespace, ipc_set);
++
++	kuid_t ns_root_uid = make_kuid(ns->user_ns, 0);
++	kgid_t ns_root_gid = make_kgid(ns->user_ns, 0);
++
++	*uid = uid_valid(ns_root_uid) ? ns_root_uid : GLOBAL_ROOT_UID;
++	*gid = gid_valid(ns_root_gid) ? ns_root_gid : GLOBAL_ROOT_GID;
++}
++
+ static int ipc_permissions(struct ctl_table_header *head, struct ctl_table *table)
+ {
+ 	int mode = table->mode;
+ 
+ #ifdef CONFIG_CHECKPOINT_RESTORE
+-	struct ipc_namespace *ns = current->nsproxy->ipc_ns;
++	struct ipc_namespace *ns =
++		container_of(head->set, struct ipc_namespace, ipc_set);
+ 
+ 	if (((table->data == &ns->ids[IPC_SEM_IDS].next_id) ||
+ 	     (table->data == &ns->ids[IPC_MSG_IDS].next_id) ||
+ 	     (table->data == &ns->ids[IPC_SHM_IDS].next_id)) &&
+ 	    checkpoint_restore_ns_capable(ns->user_ns))
+ 		mode = 0666;
++	else
+ #endif
+-	return mode;
++	{
++		kuid_t ns_root_uid;
++		kgid_t ns_root_gid;
++
++		ipc_set_ownership(head, &ns_root_uid, &ns_root_gid);
++
++		if (uid_eq(current_euid(), ns_root_uid))
++			mode >>= 6;
++
++		else if (in_egroup_p(ns_root_gid))
++			mode >>= 3;
++	}
++
++	mode &= 7;
++
++	return (mode << 6) | (mode << 3) | mode;
+ }
+ 
+ static struct ctl_table_root set_root = {
+ 	.lookup = set_lookup,
+ 	.permissions = ipc_permissions,
++	.set_ownership = ipc_set_ownership,
+ };
+ 
+ bool setup_ipc_sysctls(struct ipc_namespace *ns)
+diff --git a/ipc/mq_sysctl.c b/ipc/mq_sysctl.c
+index ebb5ed81c151a..6bb1c5397c69b 100644
+--- a/ipc/mq_sysctl.c
++++ b/ipc/mq_sysctl.c
+@@ -12,6 +12,7 @@
+ #include <linux/stat.h>
+ #include <linux/capability.h>
+ #include <linux/slab.h>
++#include <linux/cred.h>
+ 
+ static int msg_max_limit_min = MIN_MSGMAX;
+ static int msg_max_limit_max = HARD_MSGMAX;
+@@ -76,8 +77,42 @@ static int set_is_seen(struct ctl_table_set *set)
+ 	return &current->nsproxy->ipc_ns->mq_set == set;
+ }
+ 
++static void mq_set_ownership(struct ctl_table_header *head,
++			     kuid_t *uid, kgid_t *gid)
++{
++	struct ipc_namespace *ns =
++		container_of(head->set, struct ipc_namespace, mq_set);
++
++	kuid_t ns_root_uid = make_kuid(ns->user_ns, 0);
++	kgid_t ns_root_gid = make_kgid(ns->user_ns, 0);
++
++	*uid = uid_valid(ns_root_uid) ? ns_root_uid : GLOBAL_ROOT_UID;
++	*gid = gid_valid(ns_root_gid) ? ns_root_gid : GLOBAL_ROOT_GID;
++}
++
++static int mq_permissions(struct ctl_table_header *head, struct ctl_table *table)
++{
++	int mode = table->mode;
++	kuid_t ns_root_uid;
++	kgid_t ns_root_gid;
++
++	mq_set_ownership(head, &ns_root_uid, &ns_root_gid);
++
++	if (uid_eq(current_euid(), ns_root_uid))
++		mode >>= 6;
++
++	else if (in_egroup_p(ns_root_gid))
++		mode >>= 3;
++
++	mode &= 7;
++
++	return (mode << 6) | (mode << 3) | mode;
++}
++
+ static struct ctl_table_root set_root = {
+ 	.lookup = set_lookup,
++	.permissions = mq_permissions,
++	.set_ownership = mq_set_ownership,
+ };
+ 
+ bool setup_mq_sysctls(struct ipc_namespace *ns)
+diff --git a/mm/Kconfig b/mm/Kconfig
+index 264a2df5ecf5b..ece4f2847e2b4 100644
+--- a/mm/Kconfig
++++ b/mm/Kconfig
+@@ -704,6 +704,17 @@ config HUGETLB_PAGE_SIZE_VARIABLE
+ config CONTIG_ALLOC
+ 	def_bool (MEMORY_ISOLATION && COMPACTION) || CMA
+ 
++config PCP_BATCH_SCALE_MAX
++	int "Maximum scale factor of PCP (Per-CPU pageset) batch allocate/free"
++	default 5
++	range 0 6
++	help
++	  In page allocator, PCP (Per-CPU pageset) is refilled and drained in
++	  batches.  The batch number is scaled automatically to improve page
++	  allocation/free throughput.  But too large scale factor may hurt
++	  latency.  This option sets the upper limit of scale factor to limit
++	  the maximum latency.
++
+ config PHYS_ADDR_T_64BIT
+ 	def_bool 64BIT
+ 
+diff --git a/mm/page_alloc.c b/mm/page_alloc.c
+index e99d3223f0fc2..39bdbfb5313fb 100644
+--- a/mm/page_alloc.c
++++ b/mm/page_alloc.c
+@@ -2185,14 +2185,21 @@ void drain_zone_pages(struct zone *zone, struct per_cpu_pages *pcp)
+  */
+ static void drain_pages_zone(unsigned int cpu, struct zone *zone)
+ {
+-	struct per_cpu_pages *pcp;
++	struct per_cpu_pages *pcp = per_cpu_ptr(zone->per_cpu_pageset, cpu);
++	int count;
+ 
+-	pcp = per_cpu_ptr(zone->per_cpu_pageset, cpu);
+-	if (pcp->count) {
++	do {
+ 		spin_lock(&pcp->lock);
+-		free_pcppages_bulk(zone, pcp->count, pcp, 0);
++		count = pcp->count;
++		if (count) {
++			int to_drain = min(count,
++				pcp->batch << CONFIG_PCP_BATCH_SCALE_MAX);
++
++			free_pcppages_bulk(zone, to_drain, pcp, 0);
++			count -= to_drain;
++		}
+ 		spin_unlock(&pcp->lock);
+-	}
++	} while (count);
+ }
+ 
+ /*
+@@ -2343,7 +2350,7 @@ static int nr_pcp_free(struct per_cpu_pages *pcp, int high, bool free_high)
+ 	 * freeing of pages without any allocation.
+ 	 */
+ 	batch <<= pcp->free_factor;
+-	if (batch < max_nr_free)
++	if (batch < max_nr_free && pcp->free_factor < CONFIG_PCP_BATCH_SCALE_MAX)
+ 		pcp->free_factor++;
+ 	batch = clamp(batch, min_nr_free, max_nr_free);
+ 
+diff --git a/net/bluetooth/hci_sync.c b/net/bluetooth/hci_sync.c
+index b3f5714dab342..6dab0c99c82c7 100644
+--- a/net/bluetooth/hci_sync.c
++++ b/net/bluetooth/hci_sync.c
+@@ -2862,6 +2862,27 @@ static int hci_passive_scan_sync(struct hci_dev *hdev)
+ 	 */
+ 	filter_policy = hci_update_accept_list_sync(hdev);
+ 
++	/* If suspended and filter_policy set to 0x00 (no acceptlist) then
++	 * passive scanning cannot be started since that would require the host
++	 * to be woken up to process the reports.
++	 */
++	if (hdev->suspended && !filter_policy) {
++		/* Check if accept list is empty then there is no need to scan
++		 * while suspended.
++		 */
++		if (list_empty(&hdev->le_accept_list))
++			return 0;
++
++		/* If there are devices is the accept_list that means some
++		 * devices could not be programmed which in non-suspended case
++		 * means filter_policy needs to be set to 0x00 so the host needs
++		 * to filter, but since this is treating suspended case we
++		 * can ignore device needing host to filter to allow devices in
++		 * the acceptlist to be able to wakeup the system.
++		 */
++		filter_policy = 0x01;
++	}
++
+ 	/* When the controller is using random resolvable addresses and
+ 	 * with that having LE privacy enabled, then controllers with
+ 	 * Extended Scanner Filter Policies support can now enable support
+diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c
+index 7ea66de1442cc..8573dad6d8171 100644
+--- a/net/core/rtnetlink.c
++++ b/net/core/rtnetlink.c
+@@ -3263,7 +3263,7 @@ static int rtnl_dellink(struct sk_buff *skb, struct nlmsghdr *nlh,
+ 	if (ifm->ifi_index > 0)
+ 		dev = __dev_get_by_index(tgt_net, ifm->ifi_index);
+ 	else if (tb[IFLA_IFNAME] || tb[IFLA_ALT_IFNAME])
+-		dev = rtnl_dev_get(net, tb);
++		dev = rtnl_dev_get(tgt_net, tb);
+ 	else if (tb[IFLA_GROUP])
+ 		err = rtnl_group_dellink(tgt_net, nla_get_u32(tb[IFLA_GROUP]));
+ 	else
+diff --git a/net/ipv4/netfilter/iptable_nat.c b/net/ipv4/netfilter/iptable_nat.c
+index 56f6ecc43451e..12ca666d6e2c1 100644
+--- a/net/ipv4/netfilter/iptable_nat.c
++++ b/net/ipv4/netfilter/iptable_nat.c
+@@ -145,25 +145,27 @@ static struct pernet_operations iptable_nat_net_ops = {
+ 
+ static int __init iptable_nat_init(void)
+ {
+-	int ret = xt_register_template(&nf_nat_ipv4_table,
+-				       iptable_nat_table_init);
++	int ret;
+ 
++	/* net->gen->ptr[iptable_nat_net_id] must be allocated
++	 * before calling iptable_nat_table_init().
++	 */
++	ret = register_pernet_subsys(&iptable_nat_net_ops);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	ret = register_pernet_subsys(&iptable_nat_net_ops);
+-	if (ret < 0) {
+-		xt_unregister_template(&nf_nat_ipv4_table);
+-		return ret;
+-	}
++	ret = xt_register_template(&nf_nat_ipv4_table,
++				   iptable_nat_table_init);
++	if (ret < 0)
++		unregister_pernet_subsys(&iptable_nat_net_ops);
+ 
+ 	return ret;
+ }
+ 
+ static void __exit iptable_nat_exit(void)
+ {
+-	unregister_pernet_subsys(&iptable_nat_net_ops);
+ 	xt_unregister_template(&nf_nat_ipv4_table);
++	unregister_pernet_subsys(&iptable_nat_net_ops);
+ }
+ 
+ module_init(iptable_nat_init);
+diff --git a/net/ipv4/syncookies.c b/net/ipv4/syncookies.c
+index 3b4dafefb4b03..e143562077958 100644
+--- a/net/ipv4/syncookies.c
++++ b/net/ipv4/syncookies.c
+@@ -424,7 +424,8 @@ struct sock *cookie_v4_check(struct sock *sk, struct sk_buff *skb)
+ 	}
+ 
+ 	/* Try to redo what tcp_v4_send_synack did. */
+-	req->rsk_window_clamp = tp->window_clamp ? :dst_metric(&rt->dst, RTAX_WINDOW);
++	req->rsk_window_clamp = READ_ONCE(tp->window_clamp) ? :
++				dst_metric(&rt->dst, RTAX_WINDOW);
+ 	/* limit the window selection if the user enforce a smaller rx buffer */
+ 	full_space = tcp_full_space(sk);
+ 	if (sk->sk_userlocks & SOCK_RCVBUF_LOCK &&
+diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
+index 91c3d8264059d..1e3202f2b7a87 100644
+--- a/net/ipv4/tcp.c
++++ b/net/ipv4/tcp.c
+@@ -1723,7 +1723,7 @@ int tcp_set_rcvlowat(struct sock *sk, int val)
+ 	space = tcp_space_from_win(sk, val);
+ 	if (space > sk->sk_rcvbuf) {
+ 		WRITE_ONCE(sk->sk_rcvbuf, space);
+-		tcp_sk(sk)->window_clamp = val;
++		WRITE_ONCE(tcp_sk(sk)->window_clamp, val);
+ 	}
+ 	return 0;
+ }
+@@ -3386,7 +3386,7 @@ int tcp_set_window_clamp(struct sock *sk, int val)
+ 	if (!val) {
+ 		if (sk->sk_state != TCP_CLOSE)
+ 			return -EINVAL;
+-		tp->window_clamp = 0;
++		WRITE_ONCE(tp->window_clamp, 0);
+ 	} else {
+ 		u32 new_rcv_ssthresh, old_window_clamp = tp->window_clamp;
+ 		u32 new_window_clamp = val < SOCK_MIN_RCVBUF / 2 ?
+@@ -3395,7 +3395,7 @@ int tcp_set_window_clamp(struct sock *sk, int val)
+ 		if (new_window_clamp == old_window_clamp)
+ 			return 0;
+ 
+-		tp->window_clamp = new_window_clamp;
++		WRITE_ONCE(tp->window_clamp, new_window_clamp);
+ 		if (new_window_clamp < old_window_clamp) {
+ 			/* need to apply the reserved mem provisioning only
+ 			 * when shrinking the window clamp
+@@ -4020,7 +4020,7 @@ int do_tcp_getsockopt(struct sock *sk, int level,
+ 				      TCP_RTO_MAX / HZ);
+ 		break;
+ 	case TCP_WINDOW_CLAMP:
+-		val = tp->window_clamp;
++		val = READ_ONCE(tp->window_clamp);
+ 		break;
+ 	case TCP_INFO: {
+ 		struct tcp_info info;
+diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c
+index c2e4dac42453b..d0364cff65c9f 100644
+--- a/net/ipv4/tcp_input.c
++++ b/net/ipv4/tcp_input.c
+@@ -570,19 +570,20 @@ static void tcp_init_buffer_space(struct sock *sk)
+ 	maxwin = tcp_full_space(sk);
+ 
+ 	if (tp->window_clamp >= maxwin) {
+-		tp->window_clamp = maxwin;
++		WRITE_ONCE(tp->window_clamp, maxwin);
+ 
+ 		if (tcp_app_win && maxwin > 4 * tp->advmss)
+-			tp->window_clamp = max(maxwin -
+-					       (maxwin >> tcp_app_win),
+-					       4 * tp->advmss);
++			WRITE_ONCE(tp->window_clamp,
++				   max(maxwin - (maxwin >> tcp_app_win),
++				       4 * tp->advmss));
+ 	}
+ 
+ 	/* Force reservation of one segment. */
+ 	if (tcp_app_win &&
+ 	    tp->window_clamp > 2 * tp->advmss &&
+ 	    tp->window_clamp + tp->advmss > maxwin)
+-		tp->window_clamp = max(2 * tp->advmss, maxwin - tp->advmss);
++		WRITE_ONCE(tp->window_clamp,
++			   max(2 * tp->advmss, maxwin - tp->advmss));
+ 
+ 	tp->rcv_ssthresh = min(tp->rcv_ssthresh, tp->window_clamp);
+ 	tp->snd_cwnd_stamp = tcp_jiffies32;
+@@ -747,8 +748,7 @@ void tcp_rcv_space_adjust(struct sock *sk)
+ 	 * <prev RTT . ><current RTT .. ><next RTT .... >
+ 	 */
+ 
+-	if (READ_ONCE(sock_net(sk)->ipv4.sysctl_tcp_moderate_rcvbuf) &&
+-	    !(sk->sk_userlocks & SOCK_RCVBUF_LOCK)) {
++	if (READ_ONCE(sock_net(sk)->ipv4.sysctl_tcp_moderate_rcvbuf)) {
+ 		u64 rcvwin, grow;
+ 		int rcvbuf;
+ 
+@@ -764,11 +764,22 @@ void tcp_rcv_space_adjust(struct sock *sk)
+ 
+ 		rcvbuf = min_t(u64, tcp_space_from_win(sk, rcvwin),
+ 			       READ_ONCE(sock_net(sk)->ipv4.sysctl_tcp_rmem[2]));
+-		if (rcvbuf > sk->sk_rcvbuf) {
+-			WRITE_ONCE(sk->sk_rcvbuf, rcvbuf);
++		if (!(sk->sk_userlocks & SOCK_RCVBUF_LOCK)) {
++			if (rcvbuf > sk->sk_rcvbuf) {
++				WRITE_ONCE(sk->sk_rcvbuf, rcvbuf);
+ 
+-			/* Make the window clamp follow along.  */
+-			tp->window_clamp = tcp_win_from_space(sk, rcvbuf);
++				/* Make the window clamp follow along.  */
++				WRITE_ONCE(tp->window_clamp,
++					   tcp_win_from_space(sk, rcvbuf));
++			}
++		} else {
++			/* Make the window clamp follow along while being bounded
++			 * by SO_RCVBUF.
++			 */
++			int clamp = tcp_win_from_space(sk, min(rcvbuf, sk->sk_rcvbuf));
++
++			if (clamp > tp->window_clamp)
++				WRITE_ONCE(tp->window_clamp, clamp);
+ 		}
+ 	}
+ 	tp->rcvq_space.space = copied;
+@@ -6347,7 +6358,8 @@ static int tcp_rcv_synsent_state_process(struct sock *sk, struct sk_buff *skb,
+ 
+ 		if (!tp->rx_opt.wscale_ok) {
+ 			tp->rx_opt.snd_wscale = tp->rx_opt.rcv_wscale = 0;
+-			tp->window_clamp = min(tp->window_clamp, 65535U);
++			WRITE_ONCE(tp->window_clamp,
++				   min(tp->window_clamp, 65535U));
+ 		}
+ 
+ 		if (tp->rx_opt.saw_tstamp) {
+diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
+index 5631041ae12cb..15c49d559db53 100644
+--- a/net/ipv4/tcp_output.c
++++ b/net/ipv4/tcp_output.c
+@@ -203,16 +203,17 @@ static inline void tcp_event_ack_sent(struct sock *sk, u32 rcv_nxt)
+  * This MUST be enforced by all callers.
+  */
+ void tcp_select_initial_window(const struct sock *sk, int __space, __u32 mss,
+-			       __u32 *rcv_wnd, __u32 *window_clamp,
++			       __u32 *rcv_wnd, __u32 *__window_clamp,
+ 			       int wscale_ok, __u8 *rcv_wscale,
+ 			       __u32 init_rcv_wnd)
+ {
+ 	unsigned int space = (__space < 0 ? 0 : __space);
++	u32 window_clamp = READ_ONCE(*__window_clamp);
+ 
+ 	/* If no clamp set the clamp to the max possible scaled window */
+-	if (*window_clamp == 0)
+-		(*window_clamp) = (U16_MAX << TCP_MAX_WSCALE);
+-	space = min(*window_clamp, space);
++	if (window_clamp == 0)
++		window_clamp = (U16_MAX << TCP_MAX_WSCALE);
++	space = min(window_clamp, space);
+ 
+ 	/* Quantize space offering to a multiple of mss if possible. */
+ 	if (space > mss)
+@@ -239,12 +240,13 @@ void tcp_select_initial_window(const struct sock *sk, int __space, __u32 mss,
+ 		/* Set window scaling on max possible window */
+ 		space = max_t(u32, space, READ_ONCE(sock_net(sk)->ipv4.sysctl_tcp_rmem[2]));
+ 		space = max_t(u32, space, READ_ONCE(sysctl_rmem_max));
+-		space = min_t(u32, space, *window_clamp);
++		space = min_t(u32, space, window_clamp);
+ 		*rcv_wscale = clamp_t(int, ilog2(space) - 15,
+ 				      0, TCP_MAX_WSCALE);
+ 	}
+ 	/* Set the clamp no higher than max representable value */
+-	(*window_clamp) = min_t(__u32, U16_MAX << (*rcv_wscale), *window_clamp);
++	WRITE_ONCE(*__window_clamp,
++		   min_t(__u32, U16_MAX << (*rcv_wscale), window_clamp));
+ }
+ EXPORT_SYMBOL(tcp_select_initial_window);
+ 
+@@ -3787,7 +3789,7 @@ static void tcp_connect_init(struct sock *sk)
+ 	tcp_ca_dst_init(sk, dst);
+ 
+ 	if (!tp->window_clamp)
+-		tp->window_clamp = dst_metric(dst, RTAX_WINDOW);
++		WRITE_ONCE(tp->window_clamp, dst_metric(dst, RTAX_WINDOW));
+ 	tp->advmss = tcp_mss_clamp(tp, dst_metric_advmss(dst));
+ 
+ 	tcp_initialize_rcv_mss(sk);
+@@ -3795,7 +3797,7 @@ static void tcp_connect_init(struct sock *sk)
+ 	/* limit the window selection if the user enforce a smaller rx buffer */
+ 	if (sk->sk_userlocks & SOCK_RCVBUF_LOCK &&
+ 	    (tp->window_clamp > tcp_full_space(sk) || tp->window_clamp == 0))
+-		tp->window_clamp = tcp_full_space(sk);
++		WRITE_ONCE(tp->window_clamp, tcp_full_space(sk));
+ 
+ 	rcv_wnd = tcp_rwnd_init_bpf(sk);
+ 	if (rcv_wnd == 0)
+diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c
+index 68debc78189c2..2062ab94721e3 100644
+--- a/net/ipv6/ndisc.c
++++ b/net/ipv6/ndisc.c
+@@ -227,6 +227,7 @@ struct ndisc_options *ndisc_parse_options(const struct net_device *dev,
+ 		return NULL;
+ 	memset(ndopts, 0, sizeof(*ndopts));
+ 	while (opt_len) {
++		bool unknown = false;
+ 		int l;
+ 		if (opt_len < sizeof(struct nd_opt_hdr))
+ 			return NULL;
+@@ -262,22 +263,23 @@ struct ndisc_options *ndisc_parse_options(const struct net_device *dev,
+ 			break;
+ #endif
+ 		default:
+-			if (ndisc_is_useropt(dev, nd_opt)) {
+-				ndopts->nd_useropts_end = nd_opt;
+-				if (!ndopts->nd_useropts)
+-					ndopts->nd_useropts = nd_opt;
+-			} else {
+-				/*
+-				 * Unknown options must be silently ignored,
+-				 * to accommodate future extension to the
+-				 * protocol.
+-				 */
+-				ND_PRINTK(2, notice,
+-					  "%s: ignored unsupported option; type=%d, len=%d\n",
+-					  __func__,
+-					  nd_opt->nd_opt_type,
+-					  nd_opt->nd_opt_len);
+-			}
++			unknown = true;
++		}
++		if (ndisc_is_useropt(dev, nd_opt)) {
++			ndopts->nd_useropts_end = nd_opt;
++			if (!ndopts->nd_useropts)
++				ndopts->nd_useropts = nd_opt;
++		} else if (unknown) {
++			/*
++			 * Unknown options must be silently ignored,
++			 * to accommodate future extension to the
++			 * protocol.
++			 */
++			ND_PRINTK(2, notice,
++				  "%s: ignored unsupported option; type=%d, len=%d\n",
++				  __func__,
++				  nd_opt->nd_opt_type,
++				  nd_opt->nd_opt_len);
+ 		}
+ next_opt:
+ 		opt_len -= l;
+diff --git a/net/ipv6/netfilter/ip6table_nat.c b/net/ipv6/netfilter/ip6table_nat.c
+index bf3cb3a13600c..52d597b16b658 100644
+--- a/net/ipv6/netfilter/ip6table_nat.c
++++ b/net/ipv6/netfilter/ip6table_nat.c
+@@ -147,23 +147,27 @@ static struct pernet_operations ip6table_nat_net_ops = {
+ 
+ static int __init ip6table_nat_init(void)
+ {
+-	int ret = xt_register_template(&nf_nat_ipv6_table,
+-				       ip6table_nat_table_init);
++	int ret;
+ 
++	/* net->gen->ptr[ip6table_nat_net_id] must be allocated
++	 * before calling ip6t_nat_register_lookups().
++	 */
++	ret = register_pernet_subsys(&ip6table_nat_net_ops);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	ret = register_pernet_subsys(&ip6table_nat_net_ops);
++	ret = xt_register_template(&nf_nat_ipv6_table,
++				   ip6table_nat_table_init);
+ 	if (ret)
+-		xt_unregister_template(&nf_nat_ipv6_table);
++		unregister_pernet_subsys(&ip6table_nat_net_ops);
+ 
+ 	return ret;
+ }
+ 
+ static void __exit ip6table_nat_exit(void)
+ {
+-	unregister_pernet_subsys(&ip6table_nat_net_ops);
+ 	xt_unregister_template(&nf_nat_ipv6_table);
++	unregister_pernet_subsys(&ip6table_nat_net_ops);
+ }
+ 
+ module_init(ip6table_nat_init);
+diff --git a/net/ipv6/syncookies.c b/net/ipv6/syncookies.c
+index 8698b49dfc8de..593ead8a45d79 100644
+--- a/net/ipv6/syncookies.c
++++ b/net/ipv6/syncookies.c
+@@ -243,7 +243,7 @@ struct sock *cookie_v6_check(struct sock *sk, struct sk_buff *skb)
+ 			goto out_free;
+ 	}
+ 
+-	req->rsk_window_clamp = tp->window_clamp ? :dst_metric(dst, RTAX_WINDOW);
++	req->rsk_window_clamp = READ_ONCE(tp->window_clamp) ? :dst_metric(dst, RTAX_WINDOW);
+ 	/* limit the window selection if the user enforce a smaller rx buffer */
+ 	full_space = tcp_full_space(sk);
+ 	if (sk->sk_userlocks & SOCK_RCVBUF_LOCK &&
+diff --git a/net/iucv/af_iucv.c b/net/iucv/af_iucv.c
+index 498a0c35b7bb2..815b1df0b2d19 100644
+--- a/net/iucv/af_iucv.c
++++ b/net/iucv/af_iucv.c
+@@ -335,8 +335,8 @@ static void iucv_sever_path(struct sock *sk, int with_user_data)
+ 	struct iucv_sock *iucv = iucv_sk(sk);
+ 	struct iucv_path *path = iucv->path;
+ 
+-	if (iucv->path) {
+-		iucv->path = NULL;
++	/* Whoever resets the path pointer, must sever and free it. */
++	if (xchg(&iucv->path, NULL)) {
+ 		if (with_user_data) {
+ 			low_nmcpy(user_data, iucv->src_name);
+ 			high_nmcpy(user_data, iucv->dst_name);
+diff --git a/net/mptcp/mib.c b/net/mptcp/mib.c
+index c30405e768337..7884217f33eb2 100644
+--- a/net/mptcp/mib.c
++++ b/net/mptcp/mib.c
+@@ -19,7 +19,9 @@ static const struct snmp_mib mptcp_snmp_list[] = {
+ 	SNMP_MIB_ITEM("MPTCPRetrans", MPTCP_MIB_RETRANSSEGS),
+ 	SNMP_MIB_ITEM("MPJoinNoTokenFound", MPTCP_MIB_JOINNOTOKEN),
+ 	SNMP_MIB_ITEM("MPJoinSynRx", MPTCP_MIB_JOINSYNRX),
++	SNMP_MIB_ITEM("MPJoinSynBackupRx", MPTCP_MIB_JOINSYNBACKUPRX),
+ 	SNMP_MIB_ITEM("MPJoinSynAckRx", MPTCP_MIB_JOINSYNACKRX),
++	SNMP_MIB_ITEM("MPJoinSynAckBackupRx", MPTCP_MIB_JOINSYNACKBACKUPRX),
+ 	SNMP_MIB_ITEM("MPJoinSynAckHMacFailure", MPTCP_MIB_JOINSYNACKMAC),
+ 	SNMP_MIB_ITEM("MPJoinAckRx", MPTCP_MIB_JOINACKRX),
+ 	SNMP_MIB_ITEM("MPJoinAckHMacFailure", MPTCP_MIB_JOINACKMAC),
+diff --git a/net/mptcp/mib.h b/net/mptcp/mib.h
+index dd7fd1f246b5f..443604462ace8 100644
+--- a/net/mptcp/mib.h
++++ b/net/mptcp/mib.h
+@@ -12,7 +12,9 @@ enum linux_mptcp_mib_field {
+ 	MPTCP_MIB_RETRANSSEGS,		/* Segments retransmitted at the MPTCP-level */
+ 	MPTCP_MIB_JOINNOTOKEN,		/* Received MP_JOIN but the token was not found */
+ 	MPTCP_MIB_JOINSYNRX,		/* Received a SYN + MP_JOIN */
++	MPTCP_MIB_JOINSYNBACKUPRX,	/* Received a SYN + MP_JOIN + backup flag */
+ 	MPTCP_MIB_JOINSYNACKRX,		/* Received a SYN/ACK + MP_JOIN */
++	MPTCP_MIB_JOINSYNACKBACKUPRX,	/* Received a SYN/ACK + MP_JOIN + backup flag */
+ 	MPTCP_MIB_JOINSYNACKMAC,	/* HMAC was wrong on SYN/ACK + MP_JOIN */
+ 	MPTCP_MIB_JOINACKRX,		/* Received an ACK + MP_JOIN */
+ 	MPTCP_MIB_JOINACKMAC,		/* HMAC was wrong on ACK + MP_JOIN */
+diff --git a/net/mptcp/options.c b/net/mptcp/options.c
+index 63fc0758c22d4..85aafa94cc8ab 100644
+--- a/net/mptcp/options.c
++++ b/net/mptcp/options.c
+@@ -909,7 +909,7 @@ bool mptcp_synack_options(const struct request_sock *req, unsigned int *size,
+ 		return true;
+ 	} else if (subflow_req->mp_join) {
+ 		opts->suboptions = OPTION_MPTCP_MPJ_SYNACK;
+-		opts->backup = subflow_req->backup;
++		opts->backup = subflow_req->request_bkup;
+ 		opts->join_id = subflow_req->local_id;
+ 		opts->thmac = subflow_req->thmac;
+ 		opts->nonce = subflow_req->local_nonce;
+diff --git a/net/mptcp/pm_netlink.c b/net/mptcp/pm_netlink.c
+index f58bf77d76b81..db621933b2035 100644
+--- a/net/mptcp/pm_netlink.c
++++ b/net/mptcp/pm_netlink.c
+@@ -476,7 +476,6 @@ static void __mptcp_pm_send_ack(struct mptcp_sock *msk, struct mptcp_subflow_con
+ 	slow = lock_sock_fast(ssk);
+ 	if (prio) {
+ 		subflow->send_mp_prio = 1;
+-		subflow->backup = backup;
+ 		subflow->request_bkup = backup;
+ 	}
+ 
+@@ -1432,6 +1431,7 @@ static bool mptcp_pm_remove_anno_addr(struct mptcp_sock *msk,
+ 	ret = remove_anno_list_by_saddr(msk, addr);
+ 	if (ret || force) {
+ 		spin_lock_bh(&msk->pm.lock);
++		msk->pm.add_addr_signaled -= ret;
+ 		mptcp_pm_remove_addr(msk, &list);
+ 		spin_unlock_bh(&msk->pm.lock);
+ 	}
+@@ -1565,16 +1565,25 @@ void mptcp_pm_remove_addrs(struct mptcp_sock *msk, struct list_head *rm_list)
+ {
+ 	struct mptcp_rm_list alist = { .nr = 0 };
+ 	struct mptcp_pm_addr_entry *entry;
++	int anno_nr = 0;
+ 
+ 	list_for_each_entry(entry, rm_list, list) {
+-		if ((remove_anno_list_by_saddr(msk, &entry->addr) ||
+-		     lookup_subflow_by_saddr(&msk->conn_list, &entry->addr)) &&
+-		    alist.nr < MPTCP_RM_IDS_MAX)
+-			alist.ids[alist.nr++] = entry->addr.id;
++		if (alist.nr >= MPTCP_RM_IDS_MAX)
++			break;
++
++		/* only delete if either announced or matching a subflow */
++		if (remove_anno_list_by_saddr(msk, &entry->addr))
++			anno_nr++;
++		else if (!lookup_subflow_by_saddr(&msk->conn_list,
++						  &entry->addr))
++			continue;
++
++		alist.ids[alist.nr++] = entry->addr.id;
+ 	}
+ 
+ 	if (alist.nr) {
+ 		spin_lock_bh(&msk->pm.lock);
++		msk->pm.add_addr_signaled -= anno_nr;
+ 		mptcp_pm_remove_addr(msk, &alist);
+ 		spin_unlock_bh(&msk->pm.lock);
+ 	}
+@@ -1587,17 +1596,18 @@ void mptcp_pm_remove_addrs_and_subflows(struct mptcp_sock *msk,
+ 	struct mptcp_pm_addr_entry *entry;
+ 
+ 	list_for_each_entry(entry, rm_list, list) {
+-		if (lookup_subflow_by_saddr(&msk->conn_list, &entry->addr) &&
+-		    slist.nr < MPTCP_RM_IDS_MAX)
++		if (slist.nr < MPTCP_RM_IDS_MAX &&
++		    lookup_subflow_by_saddr(&msk->conn_list, &entry->addr))
+ 			slist.ids[slist.nr++] = entry->addr.id;
+ 
+-		if (remove_anno_list_by_saddr(msk, &entry->addr) &&
+-		    alist.nr < MPTCP_RM_IDS_MAX)
++		if (alist.nr < MPTCP_RM_IDS_MAX &&
++		    remove_anno_list_by_saddr(msk, &entry->addr))
+ 			alist.ids[alist.nr++] = entry->addr.id;
+ 	}
+ 
+ 	if (alist.nr) {
+ 		spin_lock_bh(&msk->pm.lock);
++		msk->pm.add_addr_signaled -= alist.nr;
+ 		mptcp_pm_remove_addr(msk, &alist);
+ 		spin_unlock_bh(&msk->pm.lock);
+ 	}
+diff --git a/net/mptcp/protocol.c b/net/mptcp/protocol.c
+index fbf2b26760731..c1d652a3f7a9b 100644
+--- a/net/mptcp/protocol.c
++++ b/net/mptcp/protocol.c
+@@ -352,8 +352,10 @@ static bool __mptcp_move_skb(struct mptcp_sock *msk, struct sock *ssk,
+ 	skb_orphan(skb);
+ 
+ 	/* try to fetch required memory from subflow */
+-	if (!mptcp_rmem_schedule(sk, ssk, skb->truesize))
++	if (!mptcp_rmem_schedule(sk, ssk, skb->truesize)) {
++		MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_RCVPRUNED);
+ 		goto drop;
++	}
+ 
+ 	has_rxtstamp = TCP_SKB_CB(skb)->has_rxtstamp;
+ 
+@@ -842,16 +844,13 @@ void mptcp_data_ready(struct sock *sk, struct sock *ssk)
+ 		sk_rbuf = ssk_rbuf;
+ 
+ 	/* over limit? can't append more skbs to msk, Also, no need to wake-up*/
+-	if (__mptcp_rmem(sk) > sk_rbuf) {
+-		MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_RCVPRUNED);
++	if (__mptcp_rmem(sk) > sk_rbuf)
+ 		return;
+-	}
+ 
+ 	/* Wake-up the reader only for in-sequence data */
+ 	mptcp_data_lock(sk);
+-	if (move_skbs_to_msk(msk, ssk))
++	if (move_skbs_to_msk(msk, ssk) && mptcp_epollin_ready(sk))
+ 		sk->sk_data_ready(sk);
+-
+ 	mptcp_data_unlock(sk);
+ }
+ 
+@@ -1418,13 +1417,15 @@ struct sock *mptcp_subflow_get_send(struct mptcp_sock *msk)
+ 	}
+ 
+ 	mptcp_for_each_subflow(msk, subflow) {
++		bool backup = subflow->backup || subflow->request_bkup;
++
+ 		trace_mptcp_subflow_get_send(subflow);
+ 		ssk =  mptcp_subflow_tcp_sock(subflow);
+ 		if (!mptcp_subflow_active(subflow))
+ 			continue;
+ 
+ 		tout = max(tout, mptcp_timeout_from_subflow(subflow));
+-		nr_active += !subflow->backup;
++		nr_active += !backup;
+ 		pace = subflow->avg_pacing_rate;
+ 		if (unlikely(!pace)) {
+ 			/* init pacing rate from socket */
+@@ -1435,9 +1436,9 @@ struct sock *mptcp_subflow_get_send(struct mptcp_sock *msk)
+ 		}
+ 
+ 		linger_time = div_u64((u64)READ_ONCE(ssk->sk_wmem_queued) << 32, pace);
+-		if (linger_time < send_info[subflow->backup].linger_time) {
+-			send_info[subflow->backup].ssk = ssk;
+-			send_info[subflow->backup].linger_time = linger_time;
++		if (linger_time < send_info[backup].linger_time) {
++			send_info[backup].ssk = ssk;
++			send_info[backup].linger_time = linger_time;
+ 		}
+ 	}
+ 	__mptcp_set_timeout(sk, tout);
+@@ -1918,6 +1919,7 @@ static int __mptcp_recvmsg_mskq(struct mptcp_sock *msk,
+ 			if (!(flags & MSG_PEEK)) {
+ 				MPTCP_SKB_CB(skb)->offset += count;
+ 				MPTCP_SKB_CB(skb)->map_seq += count;
++				msk->bytes_consumed += count;
+ 			}
+ 			break;
+ 		}
+@@ -1928,6 +1930,7 @@ static int __mptcp_recvmsg_mskq(struct mptcp_sock *msk,
+ 			WRITE_ONCE(msk->rmem_released, msk->rmem_released + skb->truesize);
+ 			__skb_unlink(skb, &msk->receive_queue);
+ 			__kfree_skb(skb);
++			msk->bytes_consumed += count;
+ 		}
+ 
+ 		if (copied >= len)
+@@ -2023,7 +2026,7 @@ static void mptcp_rcv_space_adjust(struct mptcp_sock *msk, int copied)
+ 				ssk = mptcp_subflow_tcp_sock(subflow);
+ 				slow = lock_sock_fast(ssk);
+ 				WRITE_ONCE(ssk->sk_rcvbuf, rcvbuf);
+-				tcp_sk(ssk)->window_clamp = window_clamp;
++				WRITE_ONCE(tcp_sk(ssk)->window_clamp, window_clamp);
+ 				tcp_cleanup_rbuf(ssk, 1);
+ 				unlock_sock_fast(ssk, slow);
+ 			}
+@@ -2752,6 +2755,7 @@ static void __mptcp_init_sock(struct sock *sk)
+ 	msk->rmem_fwd_alloc = 0;
+ 	WRITE_ONCE(msk->rmem_released, 0);
+ 	msk->timer_ival = TCP_RTO_MIN;
++	msk->scaling_ratio = TCP_DEFAULT_SCALING_RATIO;
+ 
+ 	WRITE_ONCE(msk->first, NULL);
+ 	inet_csk(sk)->icsk_sync_mss = mptcp_sync_mss;
+@@ -2984,16 +2988,9 @@ void __mptcp_unaccepted_force_close(struct sock *sk)
+ 	__mptcp_destroy_sock(sk);
+ }
+ 
+-static __poll_t mptcp_check_readable(struct mptcp_sock *msk)
++static __poll_t mptcp_check_readable(struct sock *sk)
+ {
+-	/* Concurrent splices from sk_receive_queue into receive_queue will
+-	 * always show at least one non-empty queue when checked in this order.
+-	 */
+-	if (skb_queue_empty_lockless(&((struct sock *)msk)->sk_receive_queue) &&
+-	    skb_queue_empty_lockless(&msk->receive_queue))
+-		return 0;
+-
+-	return EPOLLIN | EPOLLRDNORM;
++	return mptcp_epollin_ready(sk) ? EPOLLIN | EPOLLRDNORM : 0;
+ }
+ 
+ static void mptcp_check_listen_stop(struct sock *sk)
+@@ -3031,7 +3028,7 @@ bool __mptcp_close(struct sock *sk, long timeout)
+ 		goto cleanup;
+ 	}
+ 
+-	if (mptcp_check_readable(msk) || timeout < 0) {
++	if (mptcp_data_avail(msk) || timeout < 0) {
+ 		/* If the msk has read data, or the caller explicitly ask it,
+ 		 * do the MPTCP equivalent of TCP reset, aka MPTCP fastclose
+ 		 */
+@@ -3157,6 +3154,7 @@ static int mptcp_disconnect(struct sock *sk, int flags)
+ 	msk->snd_data_fin_enable = false;
+ 	msk->rcv_fastclose = false;
+ 	msk->use_64bit_ack = false;
++	msk->bytes_consumed = 0;
+ 	WRITE_ONCE(msk->csum_enabled, mptcp_is_checksum_enabled(sock_net(sk)));
+ 	mptcp_pm_data_reset(msk);
+ 	mptcp_ca_reset(sk);
+@@ -3983,7 +3981,7 @@ static __poll_t mptcp_poll(struct file *file, struct socket *sock,
+ 		mask |= EPOLLIN | EPOLLRDNORM | EPOLLRDHUP;
+ 
+ 	if (state != TCP_SYN_SENT && state != TCP_SYN_RECV) {
+-		mask |= mptcp_check_readable(msk);
++		mask |= mptcp_check_readable(sk);
+ 		if (shutdown & SEND_SHUTDOWN)
+ 			mask |= EPOLLOUT | EPOLLWRNORM;
+ 		else
+@@ -4021,6 +4019,7 @@ static const struct proto_ops mptcp_stream_ops = {
+ 	.sendmsg	   = inet_sendmsg,
+ 	.recvmsg	   = inet_recvmsg,
+ 	.mmap		   = sock_no_mmap,
++	.set_rcvlowat	   = mptcp_set_rcvlowat,
+ };
+ 
+ static struct inet_protosw mptcp_protosw = {
+@@ -4122,6 +4121,7 @@ static const struct proto_ops mptcp_v6_stream_ops = {
+ #ifdef CONFIG_COMPAT
+ 	.compat_ioctl	   = inet6_compat_ioctl,
+ #endif
++	.set_rcvlowat	   = mptcp_set_rcvlowat,
+ };
+ 
+ static struct proto mptcp_v6_prot;
+diff --git a/net/mptcp/protocol.h b/net/mptcp/protocol.h
+index 93ba48f4ae386..c28ac5dfd0b58 100644
+--- a/net/mptcp/protocol.h
++++ b/net/mptcp/protocol.h
+@@ -268,6 +268,7 @@ struct mptcp_sock {
+ 	atomic64_t	rcv_wnd_sent;
+ 	u64		rcv_data_fin_seq;
+ 	u64		bytes_retrans;
++	u64		bytes_consumed;
+ 	int		rmem_fwd_alloc;
+ 	int		snd_burst;
+ 	int		old_wspace;
+@@ -418,6 +419,7 @@ struct mptcp_subflow_request_sock {
+ 	u16	mp_capable : 1,
+ 		mp_join : 1,
+ 		backup : 1,
++		request_bkup : 1,
+ 		csum_reqd : 1,
+ 		allow_join_id0 : 1;
+ 	u8	local_id;
+@@ -674,6 +676,24 @@ struct sock *mptcp_subflow_get_retrans(struct mptcp_sock *msk);
+ int mptcp_sched_get_send(struct mptcp_sock *msk);
+ int mptcp_sched_get_retrans(struct mptcp_sock *msk);
+ 
++static inline u64 mptcp_data_avail(const struct mptcp_sock *msk)
++{
++	return READ_ONCE(msk->bytes_received) - READ_ONCE(msk->bytes_consumed);
++}
++
++static inline bool mptcp_epollin_ready(const struct sock *sk)
++{
++	/* mptcp doesn't have to deal with small skbs in the receive queue,
++	 * at it can always coalesce them
++	 */
++	return (mptcp_data_avail(mptcp_sk(sk)) >= sk->sk_rcvlowat) ||
++	       (mem_cgroup_sockets_enabled && sk->sk_memcg &&
++		mem_cgroup_under_socket_pressure(sk->sk_memcg)) ||
++	       READ_ONCE(tcp_memory_pressure);
++}
++
++int mptcp_set_rcvlowat(struct sock *sk, int val);
++
+ static inline bool __tcp_can_send(const struct sock *ssk)
+ {
+ 	/* only send if our side has not closed yet */
+@@ -748,6 +768,7 @@ static inline bool mptcp_is_fully_established(struct sock *sk)
+ 	return inet_sk_state_load(sk) == TCP_ESTABLISHED &&
+ 	       READ_ONCE(mptcp_sk(sk)->fully_established);
+ }
++
+ void mptcp_rcv_space_init(struct mptcp_sock *msk, const struct sock *ssk);
+ void mptcp_data_ready(struct sock *sk, struct sock *ssk);
+ bool mptcp_finish_join(struct sock *sk);
+diff --git a/net/mptcp/sockopt.c b/net/mptcp/sockopt.c
+index cc04b5e29dd35..bdfeecea814f3 100644
+--- a/net/mptcp/sockopt.c
++++ b/net/mptcp/sockopt.c
+@@ -1521,9 +1521,55 @@ void mptcp_sockopt_sync_locked(struct mptcp_sock *msk, struct sock *ssk)
+ 
+ 	msk_owned_by_me(msk);
+ 
++	ssk->sk_rcvlowat = 0;
++
+ 	if (READ_ONCE(subflow->setsockopt_seq) != msk->setsockopt_seq) {
+ 		sync_socket_options(msk, ssk);
+ 
+ 		subflow->setsockopt_seq = msk->setsockopt_seq;
+ 	}
+ }
++
++/* unfortunately this is different enough from the tcp version so
++ * that we can't factor it out
++ */
++int mptcp_set_rcvlowat(struct sock *sk, int val)
++{
++	struct mptcp_subflow_context *subflow;
++	int space, cap;
++
++	/* bpf can land here with a wrong sk type */
++	if (sk->sk_protocol == IPPROTO_TCP)
++		return -EINVAL;
++
++	if (sk->sk_userlocks & SOCK_RCVBUF_LOCK)
++		cap = sk->sk_rcvbuf >> 1;
++	else
++		cap = READ_ONCE(sock_net(sk)->ipv4.sysctl_tcp_rmem[2]) >> 1;
++	val = min(val, cap);
++	WRITE_ONCE(sk->sk_rcvlowat, val ? : 1);
++
++	/* Check if we need to signal EPOLLIN right now */
++	if (mptcp_epollin_ready(sk))
++		sk->sk_data_ready(sk);
++
++	if (sk->sk_userlocks & SOCK_RCVBUF_LOCK)
++		return 0;
++
++	space = __tcp_space_from_win(mptcp_sk(sk)->scaling_ratio, val);
++	if (space <= sk->sk_rcvbuf)
++		return 0;
++
++	/* propagate the rcvbuf changes to all the subflows */
++	WRITE_ONCE(sk->sk_rcvbuf, space);
++	mptcp_for_each_subflow(mptcp_sk(sk), subflow) {
++		struct sock *ssk = mptcp_subflow_tcp_sock(subflow);
++		bool slow;
++
++		slow = lock_sock_fast(ssk);
++		WRITE_ONCE(ssk->sk_rcvbuf, space);
++		WRITE_ONCE(tcp_sk(ssk)->window_clamp, val);
++		unlock_sock_fast(ssk, slow);
++	}
++	return 0;
++}
+diff --git a/net/mptcp/subflow.c b/net/mptcp/subflow.c
+index 23ee96c6abcbf..bc1efc1787720 100644
+--- a/net/mptcp/subflow.c
++++ b/net/mptcp/subflow.c
+@@ -166,6 +166,9 @@ static int subflow_check_req(struct request_sock *req,
+ 			return 0;
+ 	} else if (opt_mp_join) {
+ 		SUBFLOW_REQ_INC_STATS(req, MPTCP_MIB_JOINSYNRX);
++
++		if (mp_opt.backup)
++			SUBFLOW_REQ_INC_STATS(req, MPTCP_MIB_JOINSYNBACKUPRX);
+ 	}
+ 
+ 	if (opt_mp_capable && listener->request_mptcp) {
+@@ -558,6 +561,9 @@ static void subflow_finish_connect(struct sock *sk, const struct sk_buff *skb)
+ 		subflow->mp_join = 1;
+ 		MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_JOINSYNACKRX);
+ 
++		if (subflow->backup)
++			MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_JOINSYNACKBACKUPRX);
++
+ 		if (subflow_use_different_dport(msk, sk)) {
+ 			pr_debug("synack inet_dport=%d %d",
+ 				 ntohs(inet_sk(sk)->inet_dport),
+@@ -1192,14 +1198,22 @@ static void mptcp_subflow_discard_data(struct sock *ssk, struct sk_buff *skb,
+ {
+ 	struct mptcp_subflow_context *subflow = mptcp_subflow_ctx(ssk);
+ 	bool fin = TCP_SKB_CB(skb)->tcp_flags & TCPHDR_FIN;
+-	u32 incr;
++	struct tcp_sock *tp = tcp_sk(ssk);
++	u32 offset, incr, avail_len;
++
++	offset = tp->copied_seq - TCP_SKB_CB(skb)->seq;
++	if (WARN_ON_ONCE(offset > skb->len))
++		goto out;
+ 
+-	incr = limit >= skb->len ? skb->len + fin : limit;
++	avail_len = skb->len - offset;
++	incr = limit >= avail_len ? avail_len + fin : limit;
+ 
+-	pr_debug("discarding=%d len=%d seq=%d", incr, skb->len,
+-		 subflow->map_subflow_seq);
++	pr_debug("discarding=%d len=%d offset=%d seq=%d", incr, skb->len,
++		 offset, subflow->map_subflow_seq);
+ 	MPTCP_INC_STATS(sock_net(ssk), MPTCP_MIB_DUPDATA);
+ 	tcp_sk(ssk)->copied_seq += incr;
++
++out:
+ 	if (!before(tcp_sk(ssk)->copied_seq, TCP_SKB_CB(skb)->end_seq))
+ 		sk_eat_skb(ssk, skb);
+ 	if (mptcp_subflow_get_map_offset(subflow) >= subflow->map_data_len)
+@@ -1432,10 +1446,18 @@ static void subflow_data_ready(struct sock *sk)
+ 	WARN_ON_ONCE(!__mptcp_check_fallback(msk) && !subflow->mp_capable &&
+ 		     !subflow->mp_join && !(state & TCPF_CLOSE));
+ 
+-	if (mptcp_subflow_data_available(sk))
++	if (mptcp_subflow_data_available(sk)) {
+ 		mptcp_data_ready(parent, sk);
+-	else if (unlikely(sk->sk_err))
++
++		/* subflow-level lowat test are not relevant.
++		 * respect the msk-level threshold eventually mandating an immediate ack
++		 */
++		if (mptcp_data_avail(msk) < parent->sk_rcvlowat &&
++		    (tcp_sk(sk)->rcv_nxt - tcp_sk(sk)->rcv_wup) > inet_csk(sk)->icsk_ack.rcv_mss)
++			inet_csk(sk)->icsk_ack.pending |= ICSK_ACK_NOW;
++	} else if (unlikely(sk->sk_err)) {
+ 		subflow_error_report(sk);
++	}
+ }
+ 
+ static void subflow_write_space(struct sock *ssk)
+@@ -1968,6 +1990,7 @@ static void subflow_ulp_clone(const struct request_sock *req,
+ 		new_ctx->fully_established = 1;
+ 		new_ctx->remote_key_valid = 1;
+ 		new_ctx->backup = subflow_req->backup;
++		new_ctx->request_bkup = subflow_req->request_bkup;
+ 		WRITE_ONCE(new_ctx->remote_id, subflow_req->remote_id);
+ 		new_ctx->token = subflow_req->token;
+ 		new_ctx->thmac = subflow_req->thmac;
+diff --git a/net/sched/act_ct.c b/net/sched/act_ct.c
+index 3ac19516ed803..50d24e240e8fb 100644
+--- a/net/sched/act_ct.c
++++ b/net/sched/act_ct.c
+@@ -44,6 +44,8 @@ static DEFINE_MUTEX(zones_mutex);
+ struct zones_ht_key {
+ 	struct net *net;
+ 	u16 zone;
++	/* Note : pad[] must be the last field. */
++	u8  pad[];
+ };
+ 
+ struct tcf_ct_flow_table {
+@@ -60,7 +62,7 @@ struct tcf_ct_flow_table {
+ static const struct rhashtable_params zones_params = {
+ 	.head_offset = offsetof(struct tcf_ct_flow_table, node),
+ 	.key_offset = offsetof(struct tcf_ct_flow_table, key),
+-	.key_len = sizeof_field(struct tcf_ct_flow_table, key),
++	.key_len = offsetof(struct zones_ht_key, pad),
+ 	.automatic_shrinking = true,
+ };
+ 
+diff --git a/net/sysctl_net.c b/net/sysctl_net.c
+index 051ed5f6fc937..a0a7a79991f9f 100644
+--- a/net/sysctl_net.c
++++ b/net/sysctl_net.c
+@@ -54,7 +54,6 @@ static int net_ctl_permissions(struct ctl_table_header *head,
+ }
+ 
+ static void net_ctl_set_ownership(struct ctl_table_header *head,
+-				  struct ctl_table *table,
+ 				  kuid_t *uid, kgid_t *gid)
+ {
+ 	struct net *net = container_of(head->set, struct net, sysctls);
+diff --git a/net/wireless/sme.c b/net/wireless/sme.c
+index 9bba233b5a6ec..72d78dbc55ffd 100644
+--- a/net/wireless/sme.c
++++ b/net/wireless/sme.c
+@@ -1057,6 +1057,7 @@ void cfg80211_connect_done(struct net_device *dev,
+ 			cfg80211_hold_bss(
+ 				bss_from_pub(params->links[link].bss));
+ 		ev->cr.links[link].bss = params->links[link].bss;
++		ev->cr.links[link].status = params->links[link].status;
+ 
+ 		if (params->links[link].addr) {
+ 			ev->cr.links[link].addr = next;
+diff --git a/sound/core/seq/seq_ump_convert.c b/sound/core/seq/seq_ump_convert.c
+index e90b27a135e6f..d9dacfbe4a9ae 100644
+--- a/sound/core/seq/seq_ump_convert.c
++++ b/sound/core/seq/seq_ump_convert.c
+@@ -1192,44 +1192,53 @@ static int cvt_sysex_to_ump(struct snd_seq_client *dest,
+ {
+ 	struct snd_seq_ump_event ev_cvt;
+ 	unsigned char status;
+-	u8 buf[6], *xbuf;
++	u8 buf[8], *xbuf;
+ 	int offset = 0;
+ 	int len, err;
++	bool finished = false;
+ 
+ 	if (!snd_seq_ev_is_variable(event))
+ 		return 0;
+ 
+ 	setup_ump_event(&ev_cvt, event);
+-	for (;;) {
++	while (!finished) {
+ 		len = snd_seq_expand_var_event_at(event, sizeof(buf), buf, offset);
+ 		if (len <= 0)
+ 			break;
+-		if (WARN_ON(len > 6))
++		if (WARN_ON(len > sizeof(buf)))
+ 			break;
+-		offset += len;
++
+ 		xbuf = buf;
++		status = UMP_SYSEX_STATUS_CONTINUE;
++		/* truncate the sysex start-marker */
+ 		if (*xbuf == UMP_MIDI1_MSG_SYSEX_START) {
+ 			status = UMP_SYSEX_STATUS_START;
+-			xbuf++;
+ 			len--;
+-			if (len > 0 && xbuf[len - 1] == UMP_MIDI1_MSG_SYSEX_END) {
++			offset++;
++			xbuf++;
++		}
++
++		/* if the last of this packet or the 1st byte of the next packet
++		 * is the end-marker, finish the transfer with this packet
++		 */
++		if (len > 0 && len < 8 &&
++		    xbuf[len - 1] == UMP_MIDI1_MSG_SYSEX_END) {
++			if (status == UMP_SYSEX_STATUS_START)
+ 				status = UMP_SYSEX_STATUS_SINGLE;
+-				len--;
+-			}
+-		} else {
+-			if (xbuf[len - 1] == UMP_MIDI1_MSG_SYSEX_END) {
++			else
+ 				status = UMP_SYSEX_STATUS_END;
+-				len--;
+-			} else {
+-				status = UMP_SYSEX_STATUS_CONTINUE;
+-			}
++			len--;
++			finished = true;
+ 		}
++
++		len = min(len, 6);
+ 		fill_sysex7_ump(dest_port, ev_cvt.ump, status, xbuf, len);
+ 		err = __snd_seq_deliver_single_event(dest, dest_port,
+ 						     (struct snd_seq_event *)&ev_cvt,
+ 						     atomic, hop);
+ 		if (err < 0)
+ 			return err;
++		offset += len;
+ 	}
+ 	return 0;
+ }
+diff --git a/sound/firewire/amdtp-stream.c b/sound/firewire/amdtp-stream.c
+index c9f153f85ae6b..5f0f8d9c08d1e 100644
+--- a/sound/firewire/amdtp-stream.c
++++ b/sound/firewire/amdtp-stream.c
+@@ -77,6 +77,8 @@
+ // overrun. Actual device can skip more, then this module stops the packet streaming.
+ #define IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES	5
+ 
++static void pcm_period_work(struct work_struct *work);
++
+ /**
+  * amdtp_stream_init - initialize an AMDTP stream structure
+  * @s: the AMDTP stream to initialize
+@@ -105,6 +107,7 @@ int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit,
+ 	s->flags = flags;
+ 	s->context = ERR_PTR(-1);
+ 	mutex_init(&s->mutex);
++	INIT_WORK(&s->period_work, pcm_period_work);
+ 	s->packet_index = 0;
+ 
+ 	init_waitqueue_head(&s->ready_wait);
+@@ -347,6 +350,7 @@ EXPORT_SYMBOL(amdtp_stream_get_max_payload);
+  */
+ void amdtp_stream_pcm_prepare(struct amdtp_stream *s)
+ {
++	cancel_work_sync(&s->period_work);
+ 	s->pcm_buffer_pointer = 0;
+ 	s->pcm_period_pointer = 0;
+ }
+@@ -611,19 +615,21 @@ static void update_pcm_pointers(struct amdtp_stream *s,
+ 		// The program in user process should periodically check the status of intermediate
+ 		// buffer associated to PCM substream to process PCM frames in the buffer, instead
+ 		// of receiving notification of period elapsed by poll wait.
+-		if (!pcm->runtime->no_period_wakeup) {
+-			if (in_softirq()) {
+-				// In software IRQ context for 1394 OHCI.
+-				snd_pcm_period_elapsed(pcm);
+-			} else {
+-				// In process context of ALSA PCM application under acquired lock of
+-				// PCM substream.
+-				snd_pcm_period_elapsed_under_stream_lock(pcm);
+-			}
+-		}
++		if (!pcm->runtime->no_period_wakeup)
++			queue_work(system_highpri_wq, &s->period_work);
+ 	}
+ }
+ 
++static void pcm_period_work(struct work_struct *work)
++{
++	struct amdtp_stream *s = container_of(work, struct amdtp_stream,
++					      period_work);
++	struct snd_pcm_substream *pcm = READ_ONCE(s->pcm);
++
++	if (pcm)
++		snd_pcm_period_elapsed(pcm);
++}
++
+ static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params,
+ 			bool sched_irq)
+ {
+@@ -1852,11 +1858,14 @@ unsigned long amdtp_domain_stream_pcm_pointer(struct amdtp_domain *d,
+ {
+ 	struct amdtp_stream *irq_target = d->irq_target;
+ 
+-	// Process isochronous packets queued till recent isochronous cycle to handle PCM frames.
+ 	if (irq_target && amdtp_stream_running(irq_target)) {
+-		// In software IRQ context, the call causes dead-lock to disable the tasklet
+-		// synchronously.
+-		if (!in_softirq())
++		// use wq to prevent AB/BA deadlock competition for
++		// substream lock:
++		// fw_iso_context_flush_completions() acquires
++		// lock by ohci_flush_iso_completions(),
++		// amdtp-stream process_rx_packets() attempts to
++		// acquire same lock by snd_pcm_elapsed()
++		if (current_work() != &s->period_work)
+ 			fw_iso_context_flush_completions(irq_target->context);
+ 	}
+ 
+@@ -1912,6 +1921,7 @@ static void amdtp_stream_stop(struct amdtp_stream *s)
+ 		return;
+ 	}
+ 
++	cancel_work_sync(&s->period_work);
+ 	fw_iso_context_stop(s->context);
+ 	fw_iso_context_destroy(s->context);
+ 	s->context = ERR_PTR(-1);
+diff --git a/sound/firewire/amdtp-stream.h b/sound/firewire/amdtp-stream.h
+index a1ed2e80f91a7..775db3fc4959f 100644
+--- a/sound/firewire/amdtp-stream.h
++++ b/sound/firewire/amdtp-stream.h
+@@ -191,6 +191,7 @@ struct amdtp_stream {
+ 
+ 	/* For a PCM substream processing. */
+ 	struct snd_pcm_substream *pcm;
++	struct work_struct period_work;
+ 	snd_pcm_uframes_t pcm_buffer_pointer;
+ 	unsigned int pcm_period_pointer;
+ 	unsigned int pcm_frame_multiplier;
+diff --git a/sound/pci/hda/hda_controller.h b/sound/pci/hda/hda_controller.h
+index 8556031bcd68e..f31cb31d46362 100644
+--- a/sound/pci/hda/hda_controller.h
++++ b/sound/pci/hda/hda_controller.h
+@@ -28,7 +28,7 @@
+ #else
+ #define AZX_DCAPS_I915_COMPONENT 0		/* NOP */
+ #endif
+-/* 14 unused */
++#define AZX_DCAPS_AMD_ALLOC_FIX	(1 << 14)	/* AMD allocation workaround */
+ #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)	/* X-Fi workaround */
+ #define AZX_DCAPS_POSFIX_LPIB	(1 << 16)	/* Use LPIB as default */
+ #define AZX_DCAPS_AMD_WORKAROUND (1 << 17)	/* AMD-specific workaround */
+diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
+index a6a9d353fe635..d5c9f113e477a 100644
+--- a/sound/pci/hda/hda_intel.c
++++ b/sound/pci/hda/hda_intel.c
+@@ -40,6 +40,7 @@
+ 
+ #ifdef CONFIG_X86
+ /* for snoop control */
++#include <linux/dma-map-ops.h>
+ #include <asm/set_memory.h>
+ #include <asm/cpufeature.h>
+ #endif
+@@ -301,7 +302,7 @@ enum {
+ 
+ /* quirks for ATI HDMI with snoop off */
+ #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
+-	(AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
++	(AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_AMD_ALLOC_FIX)
+ 
+ /* quirks for AMD SB */
+ #define AZX_DCAPS_PRESET_AMD_SB \
+@@ -1715,6 +1716,13 @@ static void azx_check_snoop_available(struct azx *chip)
+ 	if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
+ 		snoop = false;
+ 
++#ifdef CONFIG_X86
++	/* check the presence of DMA ops (i.e. IOMMU), disable snoop conditionally */
++	if ((chip->driver_caps & AZX_DCAPS_AMD_ALLOC_FIX) &&
++	    !get_dma_ops(chip->card->dev))
++		snoop = false;
++#endif
++
+ 	chip->snoop = snoop;
+ 	if (!snoop) {
+ 		dev_info(chip->card->dev, "Force to non-snoop mode\n");
+diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c
+index e8209178d87bb..af921364195e4 100644
+--- a/sound/pci/hda/patch_conexant.c
++++ b/sound/pci/hda/patch_conexant.c
+@@ -21,12 +21,6 @@
+ #include "hda_jack.h"
+ #include "hda_generic.h"
+ 
+-enum {
+-	CX_HEADSET_NOPRESENT = 0,
+-	CX_HEADSET_PARTPRESENT,
+-	CX_HEADSET_ALLPRESENT,
+-};
+-
+ struct conexant_spec {
+ 	struct hda_gen_spec gen;
+ 
+@@ -48,7 +42,6 @@ struct conexant_spec {
+ 	unsigned int gpio_led;
+ 	unsigned int gpio_mute_led_mask;
+ 	unsigned int gpio_mic_led_mask;
+-	unsigned int headset_present_flag;
+ 	bool is_cx8070_sn6140;
+ };
+ 
+@@ -250,48 +243,19 @@ static void cx_process_headset_plugin(struct hda_codec *codec)
+ 	}
+ }
+ 
+-static void cx_update_headset_mic_vref(struct hda_codec *codec, unsigned int res)
++static void cx_update_headset_mic_vref(struct hda_codec *codec, struct hda_jack_callback *event)
+ {
+-	unsigned int phone_present, mic_persent, phone_tag, mic_tag;
+-	struct conexant_spec *spec = codec->spec;
++	unsigned int mic_present;
+ 
+ 	/* In cx8070 and sn6140, the node 16 can only be config to headphone or disabled,
+ 	 * the node 19 can only be config to microphone or disabled.
+ 	 * Check hp&mic tag to process headset pulgin&plugout.
+ 	 */
+-	phone_tag = snd_hda_codec_read(codec, 0x16, 0, AC_VERB_GET_UNSOLICITED_RESPONSE, 0x0);
+-	mic_tag = snd_hda_codec_read(codec, 0x19, 0, AC_VERB_GET_UNSOLICITED_RESPONSE, 0x0);
+-	if ((phone_tag & (res >> AC_UNSOL_RES_TAG_SHIFT)) ||
+-	    (mic_tag & (res >> AC_UNSOL_RES_TAG_SHIFT))) {
+-		phone_present = snd_hda_codec_read(codec, 0x16, 0, AC_VERB_GET_PIN_SENSE, 0x0);
+-		if (!(phone_present & AC_PINSENSE_PRESENCE)) {/* headphone plugout */
+-			spec->headset_present_flag = CX_HEADSET_NOPRESENT;
+-			snd_hda_codec_write(codec, 0x19, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x20);
+-			return;
+-		}
+-		if (spec->headset_present_flag == CX_HEADSET_NOPRESENT) {
+-			spec->headset_present_flag = CX_HEADSET_PARTPRESENT;
+-		} else if (spec->headset_present_flag == CX_HEADSET_PARTPRESENT) {
+-			mic_persent = snd_hda_codec_read(codec, 0x19, 0,
+-							 AC_VERB_GET_PIN_SENSE, 0x0);
+-			/* headset is present */
+-			if ((phone_present & AC_PINSENSE_PRESENCE) &&
+-			    (mic_persent & AC_PINSENSE_PRESENCE)) {
+-				cx_process_headset_plugin(codec);
+-				spec->headset_present_flag = CX_HEADSET_ALLPRESENT;
+-			}
+-		}
+-	}
+-}
+-
+-static void cx_jack_unsol_event(struct hda_codec *codec, unsigned int res)
+-{
+-	struct conexant_spec *spec = codec->spec;
+-
+-	if (spec->is_cx8070_sn6140)
+-		cx_update_headset_mic_vref(codec, res);
+-
+-	snd_hda_jack_unsol_event(codec, res);
++	mic_present = snd_hda_codec_read(codec, 0x19, 0, AC_VERB_GET_PIN_SENSE, 0x0);
++	if (!(mic_present & AC_PINSENSE_PRESENCE)) /* mic plugout */
++		snd_hda_codec_write(codec, 0x19, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x20);
++	else
++		cx_process_headset_plugin(codec);
+ }
+ 
+ #ifdef CONFIG_PM
+@@ -307,7 +271,7 @@ static const struct hda_codec_ops cx_auto_patch_ops = {
+ 	.build_pcms = snd_hda_gen_build_pcms,
+ 	.init = cx_auto_init,
+ 	.free = cx_auto_free,
+-	.unsol_event = cx_jack_unsol_event,
++	.unsol_event = snd_hda_jack_unsol_event,
+ #ifdef CONFIG_PM
+ 	.suspend = cx_auto_suspend,
+ 	.check_power_status = snd_hda_gen_check_power_status,
+@@ -1167,7 +1131,7 @@ static int patch_conexant_auto(struct hda_codec *codec)
+ 	case 0x14f11f86:
+ 	case 0x14f11f87:
+ 		spec->is_cx8070_sn6140 = true;
+-		spec->headset_present_flag = CX_HEADSET_NOPRESENT;
++		snd_hda_jack_detect_enable_callback(codec, 0x19, cx_update_headset_mic_vref);
+ 		break;
+ 	}
+ 
+diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
+index f3aca1c38b77d..0b33a00771450 100644
+--- a/sound/pci/hda/patch_realtek.c
++++ b/sound/pci/hda/patch_realtek.c
+@@ -9639,6 +9639,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
+ 	SND_PCI_QUIRK(0x1025, 0x079b, "Acer Aspire V5-573G", ALC282_FIXUP_ASPIRE_V5_PINS),
+ 	SND_PCI_QUIRK(0x1025, 0x080d, "Acer Aspire V5-122P", ALC269_FIXUP_ASPIRE_HEADSET_MIC),
+ 	SND_PCI_QUIRK(0x1025, 0x0840, "Acer Aspire E1", ALC269VB_FIXUP_ASPIRE_E1_COEF),
++	SND_PCI_QUIRK(0x1025, 0x100c, "Acer Aspire E5-574G", ALC255_FIXUP_ACER_LIMIT_INT_MIC_BOOST),
+ 	SND_PCI_QUIRK(0x1025, 0x101c, "Acer Veriton N2510G", ALC269_FIXUP_LIFEBOOK),
+ 	SND_PCI_QUIRK(0x1025, 0x102b, "Acer Aspire C24-860", ALC286_FIXUP_ACER_AIO_MIC_NO_PRESENCE),
+ 	SND_PCI_QUIRK(0x1025, 0x1065, "Acer Aspire C20-820", ALC269VC_FIXUP_ACER_HEADSET_MIC),
+diff --git a/sound/usb/stream.c b/sound/usb/stream.c
+index d5409f3879455..e14c725acebf2 100644
+--- a/sound/usb/stream.c
++++ b/sound/usb/stream.c
+@@ -244,8 +244,8 @@ static struct snd_pcm_chmap_elem *convert_chmap(int channels, unsigned int bits,
+ 		SNDRV_CHMAP_FR,		/* right front */
+ 		SNDRV_CHMAP_FC,		/* center front */
+ 		SNDRV_CHMAP_LFE,	/* LFE */
+-		SNDRV_CHMAP_SL,		/* left surround */
+-		SNDRV_CHMAP_SR,		/* right surround */
++		SNDRV_CHMAP_RL,		/* left surround */
++		SNDRV_CHMAP_RR,		/* right surround */
+ 		SNDRV_CHMAP_FLC,	/* left of center */
+ 		SNDRV_CHMAP_FRC,	/* right of center */
+ 		SNDRV_CHMAP_RC,		/* surround */
+diff --git a/tools/perf/util/callchain.c b/tools/perf/util/callchain.c
+index aee937d14fbbf..09e6b4e1401c9 100644
+--- a/tools/perf/util/callchain.c
++++ b/tools/perf/util/callchain.c
+@@ -1126,7 +1126,7 @@ int hist_entry__append_callchain(struct hist_entry *he, struct perf_sample *samp
+ int fill_callchain_info(struct addr_location *al, struct callchain_cursor_node *node,
+ 			bool hide_unresolved)
+ {
+-	struct machine *machine = maps__machine(node->ms.maps);
++	struct machine *machine = node->ms.maps ? maps__machine(node->ms.maps) : NULL;
+ 
+ 	maps__put(al->maps);
+ 	al->maps = maps__get(node->ms.maps);
+diff --git a/tools/testing/selftests/net/mptcp/mptcp_connect.c b/tools/testing/selftests/net/mptcp/mptcp_connect.c
+index d2043ec3bf6d6..4209b95690394 100644
+--- a/tools/testing/selftests/net/mptcp/mptcp_connect.c
++++ b/tools/testing/selftests/net/mptcp/mptcp_connect.c
+@@ -1115,11 +1115,11 @@ int main_loop_s(int listensock)
+ 		return 1;
+ 	}
+ 
+-	if (--cfg_repeat > 0) {
+-		if (cfg_input)
+-			close(fd);
++	if (cfg_input)
++		close(fd);
++
++	if (--cfg_repeat > 0)
+ 		goto again;
+-	}
+ 
+ 	return 0;
+ }
+diff --git a/tools/testing/selftests/net/mptcp/mptcp_join.sh b/tools/testing/selftests/net/mptcp/mptcp_join.sh
+index 231a95a8de9ee..a2dae2a3a93e0 100755
+--- a/tools/testing/selftests/net/mptcp/mptcp_join.sh
++++ b/tools/testing/selftests/net/mptcp/mptcp_join.sh
+@@ -1778,6 +1778,8 @@ chk_prio_nr()
+ {
+ 	local mp_prio_nr_tx=$1
+ 	local mp_prio_nr_rx=$2
++	local mpj_syn=$3
++	local mpj_syn_ack=$4
+ 	local count
+ 
+ 	print_check "ptx"
+@@ -1799,6 +1801,26 @@ chk_prio_nr()
+ 	else
+ 		print_ok
+ 	fi
++
++	print_check "syn backup"
++	count=$(mptcp_lib_get_counter ${ns1} "MPTcpExtMPJoinSynBackupRx")
++	if [ -z "$count" ]; then
++		print_skip
++	elif [ "$count" != "$mpj_syn" ]; then
++		fail_test "got $count JOIN[s] syn with Backup expected $mpj_syn"
++	else
++		print_ok
++	fi
++
++	print_check "synack backup"
++	count=$(mptcp_lib_get_counter ${ns2} "MPTcpExtMPJoinSynAckBackupRx")
++	if [ -z "$count" ]; then
++		print_skip
++	elif [ "$count" != "$mpj_syn_ack" ]; then
++		fail_test "got $count JOIN[s] synack with Backup expected $mpj_syn_ack"
++	else
++		print_ok
++	fi
+ }
+ 
+ chk_subflow_nr()
+@@ -2751,11 +2773,24 @@ backup_tests()
+ 		sflags=nobackup speed=slow \
+ 			run_tests $ns1 $ns2 10.0.1.1
+ 		chk_join_nr 1 1 1
+-		chk_prio_nr 0 1
++		chk_prio_nr 0 1 1 0
+ 	fi
+ 
+ 	# single address, backup
+ 	if reset "single address, backup" &&
++	   continue_if mptcp_lib_kallsyms_has "subflow_rebuild_header$"; then
++		pm_nl_set_limits $ns1 0 1
++		pm_nl_add_endpoint $ns1 10.0.2.1 flags signal,backup
++		pm_nl_set_limits $ns2 1 1
++		sflags=nobackup speed=slow \
++			run_tests $ns1 $ns2 10.0.1.1
++		chk_join_nr 1 1 1
++		chk_add_nr 1 1
++		chk_prio_nr 1 0 0 1
++	fi
++
++	# single address, switch to backup
++	if reset "single address, switch to backup" &&
+ 	   continue_if mptcp_lib_kallsyms_has "subflow_rebuild_header$"; then
+ 		pm_nl_set_limits $ns1 0 1
+ 		pm_nl_add_endpoint $ns1 10.0.2.1 flags signal
+@@ -2764,20 +2799,20 @@ backup_tests()
+ 			run_tests $ns1 $ns2 10.0.1.1
+ 		chk_join_nr 1 1 1
+ 		chk_add_nr 1 1
+-		chk_prio_nr 1 1
++		chk_prio_nr 1 1 0 0
+ 	fi
+ 
+ 	# single address with port, backup
+ 	if reset "single address with port, backup" &&
+ 	   continue_if mptcp_lib_kallsyms_has "subflow_rebuild_header$"; then
+ 		pm_nl_set_limits $ns1 0 1
+-		pm_nl_add_endpoint $ns1 10.0.2.1 flags signal port 10100
++		pm_nl_add_endpoint $ns1 10.0.2.1 flags signal,backup port 10100
+ 		pm_nl_set_limits $ns2 1 1
+-		sflags=backup speed=slow \
++		sflags=nobackup speed=slow \
+ 			run_tests $ns1 $ns2 10.0.1.1
+ 		chk_join_nr 1 1 1
+ 		chk_add_nr 1 1
+-		chk_prio_nr 1 1
++		chk_prio_nr 1 0 0 1
+ 	fi
+ 
+ 	if reset "mpc backup" &&
+@@ -2786,17 +2821,26 @@ backup_tests()
+ 		speed=slow \
+ 			run_tests $ns1 $ns2 10.0.1.1
+ 		chk_join_nr 0 0 0
+-		chk_prio_nr 0 1
++		chk_prio_nr 0 1 0 0
+ 	fi
+ 
+ 	if reset "mpc backup both sides" &&
+ 	   continue_if mptcp_lib_kallsyms_doesnt_have "T mptcp_subflow_send_ack$"; then
+-		pm_nl_add_endpoint $ns1 10.0.1.1 flags subflow,backup
++		pm_nl_set_limits $ns1 0 2
++		pm_nl_set_limits $ns2 1 2
++		pm_nl_add_endpoint $ns1 10.0.1.1 flags signal,backup
+ 		pm_nl_add_endpoint $ns2 10.0.1.2 flags subflow,backup
++
++		# 10.0.2.2 (non-backup) -> 10.0.1.1 (backup)
++		pm_nl_add_endpoint $ns2 10.0.2.2 flags subflow
++		# 10.0.1.2 (backup) -> 10.0.2.1 (non-backup)
++		pm_nl_add_endpoint $ns1 10.0.2.1 flags signal
++		ip -net "$ns2" route add 10.0.2.1 via 10.0.1.1 dev ns2eth1 # force this path
++
+ 		speed=slow \
+ 			run_tests $ns1 $ns2 10.0.1.1
+-		chk_join_nr 0 0 0
+-		chk_prio_nr 1 1
++		chk_join_nr 2 2 2
++		chk_prio_nr 1 1 1 1
+ 	fi
+ 
+ 	if reset "mpc switch to backup" &&
+@@ -2805,7 +2849,7 @@ backup_tests()
+ 		sflags=backup speed=slow \
+ 			run_tests $ns1 $ns2 10.0.1.1
+ 		chk_join_nr 0 0 0
+-		chk_prio_nr 0 1
++		chk_prio_nr 0 1 0 0
+ 	fi
+ 
+ 	if reset "mpc switch to backup both sides" &&
+@@ -2815,7 +2859,7 @@ backup_tests()
+ 		sflags=backup speed=slow \
+ 			run_tests $ns1 $ns2 10.0.1.1
+ 		chk_join_nr 0 0 0
+-		chk_prio_nr 1 1
++		chk_prio_nr 1 1 0 0
+ 	fi
+ }
+ 
+@@ -3215,7 +3259,7 @@ fullmesh_tests()
+ 		addr_nr_ns2=1 sflags=backup,fullmesh speed=slow \
+ 			run_tests $ns1 $ns2 10.0.1.1
+ 		chk_join_nr 2 2 2
+-		chk_prio_nr 0 1
++		chk_prio_nr 0 1 1 0
+ 		chk_rm_nr 0 1
+ 	fi
+ 
+@@ -3228,7 +3272,7 @@ fullmesh_tests()
+ 		sflags=nobackup,nofullmesh speed=slow \
+ 			run_tests $ns1 $ns2 10.0.1.1
+ 		chk_join_nr 2 2 2
+-		chk_prio_nr 0 1
++		chk_prio_nr 0 1 1 0
+ 		chk_rm_nr 0 1
+ 	fi
+ }
+@@ -3407,7 +3451,7 @@ userspace_tests()
+ 		sflags=backup speed=slow \
+ 			run_tests $ns1 $ns2 10.0.1.1
+ 		chk_join_nr 1 1 0
+-		chk_prio_nr 0 0
++		chk_prio_nr 0 0 0 0
+ 	fi
+ 
+ 	# userspace pm type prevents rm_addr
diff --git a/patch/kernel/archive/odroidxu4-6.6/patch-6.6.45-46.patch b/patch/kernel/archive/odroidxu4-6.6/patch-6.6.45-46.patch
new file mode 100644
index 000000000000..359d52eccf87
--- /dev/null
+++ b/patch/kernel/archive/odroidxu4-6.6/patch-6.6.45-46.patch
@@ -0,0 +1,6300 @@
+diff --git a/Documentation/admin-guide/cifs/usage.rst b/Documentation/admin-guide/cifs/usage.rst
+index 20aba92dfc5f5..3de599cf0779a 100644
+--- a/Documentation/admin-guide/cifs/usage.rst
++++ b/Documentation/admin-guide/cifs/usage.rst
+@@ -741,7 +741,7 @@ SecurityFlags		Flags which control security negotiation and
+ 			  may use NTLMSSP               		0x00080
+ 			  must use NTLMSSP           			0x80080
+ 			  seal (packet encryption)			0x00040
+-			  must seal (not implemented yet)               0x40040
++			  must seal                                     0x40040
+ 
+ cifsFYI			If set to non-zero value, additional debug information
+ 			will be logged to the system error log.  This field
+diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
+index 8d2f9ed3f1076..a7fe113897361 100644
+--- a/Documentation/admin-guide/kernel-parameters.txt
++++ b/Documentation/admin-guide/kernel-parameters.txt
+@@ -664,12 +664,6 @@
+ 			loops can be debugged more effectively on production
+ 			systems.
+ 
+-	clocksource.max_cswd_read_retries= [KNL]
+-			Number of clocksource_watchdog() retries due to
+-			external delays before the clock will be marked
+-			unstable.  Defaults to two retries, that is,
+-			three attempts to read the clock under test.
+-
+ 	clocksource.verify_n_cpus= [KNL]
+ 			Limit the number of CPUs checked for clocksources
+ 			marked with CLOCK_SOURCE_VERIFY_PERCPU that
+@@ -4655,11 +4649,9 @@
+ 
+ 	profile=	[KNL] Enable kernel profiling via /proc/profile
+ 			Format: [<profiletype>,]<number>
+-			Param: <profiletype>: "schedule", "sleep", or "kvm"
++			Param: <profiletype>: "schedule" or "kvm"
+ 				[defaults to kernel profiling]
+ 			Param: "schedule" - profile schedule points.
+-			Param: "sleep" - profile D-state sleeping (millisecs).
+-				Requires CONFIG_SCHEDSTATS
+ 			Param: "kvm" - profile VM exits.
+ 			Param: <number> - step/bucket size as a power of 2 for
+ 				statistical time based profiling.
+diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
+index 29fd5213eeb2b..357d6cb98161f 100644
+--- a/Documentation/arch/arm64/silicon-errata.rst
++++ b/Documentation/arch/arm64/silicon-errata.rst
+@@ -119,32 +119,68 @@ stable kernels.
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |
+ +----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-A76      | #3324349        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |
+ +----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-A77      | #3324348        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-A78      | #3324344        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-A78C     | #3324346,3324347| ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |
+ +----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-A710     | #3324338        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Cortex-A715     | #2645198        | ARM64_ERRATUM_2645198       |
+ +----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-A720     | #3456091        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-A725     | #3456106        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-X1       | #3324344        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-X1C      | #3324346        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Cortex-X2       | #2119858        | ARM64_ERRATUM_2119858       |
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |
+ +----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-X2       | #3324338        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-X3       | #3324335        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-X4       | #3194386        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Cortex-X925     | #3324334        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Neoverse-N1     | #1349291        | N/A                         |
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Neoverse-N1     | #1542419        | ARM64_ERRATUM_1542419       |
+ +----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Neoverse-N1     | #3324349        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Neoverse-N2     | #2139208        | ARM64_ERRATUM_2139208       |
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Neoverse-N2     | #2067961        | ARM64_ERRATUM_2067961       |
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Neoverse-N2     | #2253138        | ARM64_ERRATUM_2253138       |
+ +----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Neoverse-N2     | #3324339        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Neoverse-V1     | #3324341        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Neoverse-V2     | #3324336        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |
+++----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | MMU-500         | #841119,826419  | N/A                         |
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | MMU-600         | #1076982,1209401| N/A                         |
+diff --git a/Documentation/hwmon/corsair-psu.rst b/Documentation/hwmon/corsair-psu.rst
+index 16db34d464dd6..7ed794087f848 100644
+--- a/Documentation/hwmon/corsair-psu.rst
++++ b/Documentation/hwmon/corsair-psu.rst
+@@ -15,11 +15,11 @@ Supported devices:
+ 
+   Corsair HX850i
+ 
+-  Corsair HX1000i (Series 2022 and 2023)
++  Corsair HX1000i (Legacy and Series 2023)
+ 
+-  Corsair HX1200i
++  Corsair HX1200i (Legacy and Series 2023)
+ 
+-  Corsair HX1500i (Series 2022 and 2023)
++  Corsair HX1500i (Legacy and Series 2023)
+ 
+   Corsair RM550i
+ 
+diff --git a/Makefile b/Makefile
+index 0bd4bee2128b4..77de99984c2f1 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1,7 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ VERSION = 6
+ PATCHLEVEL = 6
+-SUBLEVEL = 45
++SUBLEVEL = 46
+ EXTRAVERSION =
+ NAME = Hurr durr I'ma ninja sloth
+ 
+diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
+index f9777ce2ccb2d..9e0c1ac3d13ee 100644
+--- a/arch/arm64/Kconfig
++++ b/arch/arm64/Kconfig
+@@ -1068,6 +1068,44 @@ config ARM64_ERRATUM_3117295
+ 
+ 	  If unsure, say Y.
+ 
++config ARM64_ERRATUM_3194386
++	bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
++	default y
++	help
++	  This option adds the workaround for the following errata:
++
++	  * ARM Cortex-A76 erratum 3324349
++	  * ARM Cortex-A77 erratum 3324348
++	  * ARM Cortex-A78 erratum 3324344
++	  * ARM Cortex-A78C erratum 3324346
++	  * ARM Cortex-A78C erratum 3324347
++	  * ARM Cortex-A710 erratam 3324338
++	  * ARM Cortex-A720 erratum 3456091
++	  * ARM Cortex-A725 erratum 3456106
++	  * ARM Cortex-X1 erratum 3324344
++	  * ARM Cortex-X1C erratum 3324346
++	  * ARM Cortex-X2 erratum 3324338
++	  * ARM Cortex-X3 erratum 3324335
++	  * ARM Cortex-X4 erratum 3194386
++	  * ARM Cortex-X925 erratum 3324334
++	  * ARM Neoverse-N1 erratum 3324349
++	  * ARM Neoverse N2 erratum 3324339
++	  * ARM Neoverse-V1 erratum 3324341
++	  * ARM Neoverse V2 erratum 3324336
++	  * ARM Neoverse-V3 erratum 3312417
++
++	  On affected cores "MSR SSBS, #0" instructions may not affect
++	  subsequent speculative instructions, which may permit unexepected
++	  speculative store bypassing.
++
++	  Work around this problem by placing a Speculation Barrier (SB) or
++	  Instruction Synchronization Barrier (ISB) after kernel changes to
++	  SSBS. The presence of the SSBS special-purpose register is hidden
++	  from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
++	  will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
++
++	  If unsure, say Y.
++
+ config CAVIUM_ERRATUM_22375
+ 	bool "Cavium erratum 22375, 24313"
+ 	default y
+diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
+index cf2987464c186..1ca947d5c9396 100644
+--- a/arch/arm64/include/asm/barrier.h
++++ b/arch/arm64/include/asm/barrier.h
+@@ -40,6 +40,10 @@
+  */
+ #define dgh()		asm volatile("hint #6" : : : "memory")
+ 
++#define spec_bar()	asm volatile(ALTERNATIVE("dsb nsh\nisb\n",		\
++						 SB_BARRIER_INSN"nop\n",	\
++						 ARM64_HAS_SB))
++
+ #ifdef CONFIG_ARM64_PSEUDO_NMI
+ #define pmr_sync()						\
+ 	do {							\
+diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
+index 52f076afeb960..5fd7caea44193 100644
+--- a/arch/arm64/include/asm/cputype.h
++++ b/arch/arm64/include/asm/cputype.h
+@@ -86,6 +86,14 @@
+ #define ARM_CPU_PART_CORTEX_X2		0xD48
+ #define ARM_CPU_PART_NEOVERSE_N2	0xD49
+ #define ARM_CPU_PART_CORTEX_A78C	0xD4B
++#define ARM_CPU_PART_CORTEX_X1C		0xD4C
++#define ARM_CPU_PART_CORTEX_X3		0xD4E
++#define ARM_CPU_PART_NEOVERSE_V2	0xD4F
++#define ARM_CPU_PART_CORTEX_A720	0xD81
++#define ARM_CPU_PART_CORTEX_X4		0xD82
++#define ARM_CPU_PART_NEOVERSE_V3	0xD84
++#define ARM_CPU_PART_CORTEX_X925	0xD85
++#define ARM_CPU_PART_CORTEX_A725	0xD87
+ 
+ #define APM_CPU_PART_XGENE		0x000
+ #define APM_CPU_VAR_POTENZA		0x00
+@@ -159,6 +167,14 @@
+ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
+ #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
+ #define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
++#define MIDR_CORTEX_X1C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
++#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
++#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
++#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
++#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
++#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
++#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
++#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+ #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
+ #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
+ #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
+diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
+index 7bba831f62c33..57b1d6a68256b 100644
+--- a/arch/arm64/kernel/cpu_errata.c
++++ b/arch/arm64/kernel/cpu_errata.c
+@@ -448,6 +448,30 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = {
+ };
+ #endif
+ 
++#ifdef CONFIG_ARM64_ERRATUM_3194386
++static const struct midr_range erratum_spec_ssbs_list[] = {
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
++	MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
++	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
++	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
++	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
++	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
++	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
++	{}
++};
++#endif
++
+ const struct arm64_cpu_capabilities arm64_errata[] = {
+ #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
+ 	{
+@@ -746,6 +770,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
+ 		.cpu_enable = cpu_clear_bf16_from_user_emulation,
+ 	},
+ #endif
++#ifdef CONFIG_ARM64_ERRATUM_3194386
++	{
++		.desc = "SSBS not fully self-synchronizing",
++		.capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,
++		ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list),
++	},
++#endif
+ #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
+ 	{
+ 		.desc = "ARM errata 2966298, 3117295",
+diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
+index 444a73c2e6385..7e96604559004 100644
+--- a/arch/arm64/kernel/cpufeature.c
++++ b/arch/arm64/kernel/cpufeature.c
+@@ -2190,6 +2190,17 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
+ }
+ #endif /* CONFIG_ARM64_MTE */
+ 
++static void user_feature_fixup(void)
++{
++	if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) {
++		struct arm64_ftr_reg *regp;
++
++		regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1);
++		if (regp)
++			regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK;
++	}
++}
++
+ static void elf_hwcap_fixup(void)
+ {
+ #ifdef CONFIG_ARM64_ERRATUM_1742098
+@@ -3345,6 +3356,7 @@ void __init setup_cpu_features(void)
+ 	u32 cwg;
+ 
+ 	setup_system_capabilities();
++	user_feature_fixup();
+ 	setup_elf_hwcaps(arm64_elf_hwcaps);
+ 
+ 	if (system_supports_32bit_el0()) {
+diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
+index 05f40c4e18fda..57503dc4b22fa 100644
+--- a/arch/arm64/kernel/proton-pack.c
++++ b/arch/arm64/kernel/proton-pack.c
+@@ -558,6 +558,18 @@ static enum mitigation_state spectre_v4_enable_hw_mitigation(void)
+ 
+ 	/* SCTLR_EL1.DSSBS was initialised to 0 during boot */
+ 	set_pstate_ssbs(0);
++
++	/*
++	 * SSBS is self-synchronizing and is intended to affect subsequent
++	 * speculative instructions, but some CPUs can speculate with a stale
++	 * value of SSBS.
++	 *
++	 * Mitigate this with an unconditional speculation barrier, as CPUs
++	 * could mis-speculate branches and bypass a conditional barrier.
++	 */
++	if (IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386))
++		spec_bar();
++
+ 	return SPECTRE_MITIGATED;
+ }
+ 
+diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
+index 5511bee15603a..c251ef3caae56 100644
+--- a/arch/arm64/tools/cpucaps
++++ b/arch/arm64/tools/cpucaps
+@@ -99,4 +99,5 @@ WORKAROUND_NVIDIA_CARMEL_CNP
+ WORKAROUND_QCOM_FALKOR_E1003
+ WORKAROUND_REPEAT_TLBI
+ WORKAROUND_SPECULATIVE_AT
++WORKAROUND_SPECULATIVE_SSBS
+ WORKAROUND_SPECULATIVE_UNPRIV_LOAD
+diff --git a/arch/loongarch/kernel/efi.c b/arch/loongarch/kernel/efi.c
+index 9fc10cea21e10..de4f3def4af0b 100644
+--- a/arch/loongarch/kernel/efi.c
++++ b/arch/loongarch/kernel/efi.c
+@@ -66,6 +66,12 @@ void __init efi_runtime_init(void)
+ 	set_bit(EFI_RUNTIME_SERVICES, &efi.flags);
+ }
+ 
++bool efi_poweroff_required(void)
++{
++	return efi_enabled(EFI_RUNTIME_SERVICES) &&
++		(acpi_gbl_reduced_hardware || acpi_no_s5);
++}
++
+ unsigned long __initdata screen_info_table = EFI_INVALID_TABLE_ADDR;
+ 
+ static void __init init_screen_info(void)
+diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
+index 2834a64064970..a077e6bf9475f 100644
+--- a/arch/parisc/Kconfig
++++ b/arch/parisc/Kconfig
+@@ -18,6 +18,7 @@ config PARISC
+ 	select ARCH_SUPPORTS_HUGETLBFS if PA20
+ 	select ARCH_SUPPORTS_MEMORY_FAILURE
+ 	select ARCH_STACKWALK
++	select ARCH_HAS_CACHE_LINE_SIZE
+ 	select ARCH_HAS_DEBUG_VM_PGTABLE
+ 	select HAVE_RELIABLE_STACKTRACE
+ 	select DMA_OPS
+diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
+index 2a60d7a72f1fa..a3f0f100f2194 100644
+--- a/arch/parisc/include/asm/cache.h
++++ b/arch/parisc/include/asm/cache.h
+@@ -20,7 +20,16 @@
+ 
+ #define SMP_CACHE_BYTES L1_CACHE_BYTES
+ 
+-#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
++#ifdef CONFIG_PA20
++#define ARCH_DMA_MINALIGN	128
++#else
++#define ARCH_DMA_MINALIGN	32
++#endif
++#define ARCH_KMALLOC_MINALIGN	16	/* ldcw requires 16-byte alignment */
++
++#define arch_slab_minalign()	((unsigned)dcache_stride)
++#define cache_line_size()	dcache_stride
++#define dma_get_cache_alignment cache_line_size
+ 
+ #define __read_mostly __section(".data..read_mostly")
+ 
+diff --git a/arch/parisc/net/bpf_jit_core.c b/arch/parisc/net/bpf_jit_core.c
+index d6ee2fd455503..7b9cb3cda27ee 100644
+--- a/arch/parisc/net/bpf_jit_core.c
++++ b/arch/parisc/net/bpf_jit_core.c
+@@ -114,7 +114,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
+ 			jit_data->header =
+ 				bpf_jit_binary_alloc(prog_size + extable_size,
+ 						     &jit_data->image,
+-						     sizeof(u32),
++						     sizeof(long),
+ 						     bpf_fill_ill_insns);
+ 			if (!jit_data->header) {
+ 				prog = orig_prog;
+diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
+index 621bac6b74011..24b7bd255e983 100644
+--- a/arch/x86/include/asm/msr-index.h
++++ b/arch/x86/include/asm/msr-index.h
+@@ -237,6 +237,7 @@
+ #define MSR_INTEGRITY_CAPS_ARRAY_BIST          BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT)
+ #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT	4
+ #define MSR_INTEGRITY_CAPS_PERIODIC_BIST	BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
++#define MSR_INTEGRITY_CAPS_SAF_GEN_MASK	GENMASK_ULL(10, 9)
+ 
+ #define MSR_LBR_NHM_FROM		0x00000680
+ #define MSR_LBR_NHM_TO			0x000006c0
+diff --git a/arch/x86/include/asm/qspinlock.h b/arch/x86/include/asm/qspinlock.h
+index cde8357bb226d..e897046c5d2c6 100644
+--- a/arch/x86/include/asm/qspinlock.h
++++ b/arch/x86/include/asm/qspinlock.h
+@@ -66,13 +66,15 @@ static inline bool vcpu_is_preempted(long cpu)
+ 
+ #ifdef CONFIG_PARAVIRT
+ /*
+- * virt_spin_lock_key - enables (by default) the virt_spin_lock() hijack.
++ * virt_spin_lock_key - disables by default the virt_spin_lock() hijack.
+  *
+- * Native (and PV wanting native due to vCPU pinning) should disable this key.
+- * It is done in this backwards fashion to only have a single direction change,
+- * which removes ordering between native_pv_spin_init() and HV setup.
++ * Native (and PV wanting native due to vCPU pinning) should keep this key
++ * disabled. Native does not touch the key.
++ *
++ * When in a guest then native_pv_lock_init() enables the key first and
++ * KVM/XEN might conditionally disable it later in the boot process again.
+  */
+-DECLARE_STATIC_KEY_TRUE(virt_spin_lock_key);
++DECLARE_STATIC_KEY_FALSE(virt_spin_lock_key);
+ 
+ /*
+  * Shortcut for the queued_spin_lock_slowpath() function that allows
+diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c
+index 767bf1c71aadd..2a2fc14955cd3 100644
+--- a/arch/x86/kernel/cpu/mtrr/mtrr.c
++++ b/arch/x86/kernel/cpu/mtrr/mtrr.c
+@@ -609,7 +609,7 @@ void mtrr_save_state(void)
+ {
+ 	int first_cpu;
+ 
+-	if (!mtrr_enabled())
++	if (!mtrr_enabled() || !mtrr_state.have_fixed)
+ 		return;
+ 
+ 	first_cpu = cpumask_first(cpu_online_mask);
+diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
+index 97f1436c1a203..8d51c86caa415 100644
+--- a/arch/x86/kernel/paravirt.c
++++ b/arch/x86/kernel/paravirt.c
+@@ -71,13 +71,12 @@ DEFINE_PARAVIRT_ASM(pv_native_irq_enable, "sti", .noinstr.text);
+ DEFINE_PARAVIRT_ASM(pv_native_read_cr2, "mov %cr2, %rax", .noinstr.text);
+ #endif
+ 
+-DEFINE_STATIC_KEY_TRUE(virt_spin_lock_key);
++DEFINE_STATIC_KEY_FALSE(virt_spin_lock_key);
+ 
+ void __init native_pv_lock_init(void)
+ {
+-	if (IS_ENABLED(CONFIG_PARAVIRT_SPINLOCKS) &&
+-	    !boot_cpu_has(X86_FEATURE_HYPERVISOR))
+-		static_branch_disable(&virt_spin_lock_key);
++	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
++		static_branch_enable(&virt_spin_lock_key);
+ }
+ 
+ static void native_tlb_remove_table(struct mmu_gather *tlb, void *table)
+diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c
+index 51b6b78e6b175..41d8c8f475a7c 100644
+--- a/arch/x86/mm/pti.c
++++ b/arch/x86/mm/pti.c
+@@ -374,14 +374,14 @@ pti_clone_pgtable(unsigned long start, unsigned long end,
+ 			 */
+ 			*target_pmd = *pmd;
+ 
+-			addr += PMD_SIZE;
++			addr = round_up(addr + 1, PMD_SIZE);
+ 
+ 		} else if (level == PTI_CLONE_PTE) {
+ 
+ 			/* Walk the page-table down to the pte level */
+ 			pte = pte_offset_kernel(pmd, addr);
+ 			if (pte_none(*pte)) {
+-				addr += PAGE_SIZE;
++				addr = round_up(addr + 1, PAGE_SIZE);
+ 				continue;
+ 			}
+ 
+@@ -401,7 +401,7 @@ pti_clone_pgtable(unsigned long start, unsigned long end,
+ 			/* Clone the PTE */
+ 			*target_pte = *pte;
+ 
+-			addr += PAGE_SIZE;
++			addr = round_up(addr + 1, PAGE_SIZE);
+ 
+ 		} else {
+ 			BUG();
+@@ -496,7 +496,7 @@ static void pti_clone_entry_text(void)
+ {
+ 	pti_clone_pgtable((unsigned long) __entry_text_start,
+ 			  (unsigned long) __entry_text_end,
+-			  PTI_CLONE_PMD);
++			  PTI_LEVEL_KERNEL_IMAGE);
+ }
+ 
+ /*
+diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c
+index 969bf81e8d546..7f7ad94f22b91 100644
+--- a/drivers/acpi/battery.c
++++ b/drivers/acpi/battery.c
+@@ -678,12 +678,18 @@ static ssize_t acpi_battery_alarm_store(struct device *dev,
+ 	return count;
+ }
+ 
+-static const struct device_attribute alarm_attr = {
++static struct device_attribute alarm_attr = {
+ 	.attr = {.name = "alarm", .mode = 0644},
+ 	.show = acpi_battery_alarm_show,
+ 	.store = acpi_battery_alarm_store,
+ };
+ 
++static struct attribute *acpi_battery_attrs[] = {
++	&alarm_attr.attr,
++	NULL
++};
++ATTRIBUTE_GROUPS(acpi_battery);
++
+ /*
+  * The Battery Hooking API
+  *
+@@ -823,7 +829,10 @@ static void __exit battery_hook_exit(void)
+ 
+ static int sysfs_add_battery(struct acpi_battery *battery)
+ {
+-	struct power_supply_config psy_cfg = { .drv_data = battery, };
++	struct power_supply_config psy_cfg = {
++		.drv_data = battery,
++		.attr_grp = acpi_battery_groups,
++	};
+ 	bool full_cap_broken = false;
+ 
+ 	if (!ACPI_BATTERY_CAPACITY_VALID(battery->full_charge_capacity) &&
+@@ -868,7 +877,7 @@ static int sysfs_add_battery(struct acpi_battery *battery)
+ 		return result;
+ 	}
+ 	battery_hook_add_battery(battery);
+-	return device_create_file(&battery->bat->dev, &alarm_attr);
++	return 0;
+ }
+ 
+ static void sysfs_remove_battery(struct acpi_battery *battery)
+@@ -879,7 +888,6 @@ static void sysfs_remove_battery(struct acpi_battery *battery)
+ 		return;
+ 	}
+ 	battery_hook_remove_battery(battery);
+-	device_remove_file(&battery->bat->dev, &alarm_attr);
+ 	power_supply_unregister(battery->bat);
+ 	battery->bat = NULL;
+ 	mutex_unlock(&battery->sysfs_lock);
+diff --git a/drivers/acpi/sbs.c b/drivers/acpi/sbs.c
+index 94e3c000df2e1..fdeb46ed21d69 100644
+--- a/drivers/acpi/sbs.c
++++ b/drivers/acpi/sbs.c
+@@ -77,7 +77,6 @@ struct acpi_battery {
+ 	u16 spec;
+ 	u8 id;
+ 	u8 present:1;
+-	u8 have_sysfs_alarm:1;
+ };
+ 
+ #define to_acpi_battery(x) power_supply_get_drvdata(x)
+@@ -462,12 +461,18 @@ static ssize_t acpi_battery_alarm_store(struct device *dev,
+ 	return count;
+ }
+ 
+-static const struct device_attribute alarm_attr = {
++static struct device_attribute alarm_attr = {
+ 	.attr = {.name = "alarm", .mode = 0644},
+ 	.show = acpi_battery_alarm_show,
+ 	.store = acpi_battery_alarm_store,
+ };
+ 
++static struct attribute *acpi_battery_attrs[] = {
++	&alarm_attr.attr,
++	NULL
++};
++ATTRIBUTE_GROUPS(acpi_battery);
++
+ /* --------------------------------------------------------------------------
+                                  Driver Interface
+    -------------------------------------------------------------------------- */
+@@ -518,7 +523,10 @@ static int acpi_battery_read(struct acpi_battery *battery)
+ static int acpi_battery_add(struct acpi_sbs *sbs, int id)
+ {
+ 	struct acpi_battery *battery = &sbs->battery[id];
+-	struct power_supply_config psy_cfg = { .drv_data = battery, };
++	struct power_supply_config psy_cfg = {
++		.drv_data = battery,
++		.attr_grp = acpi_battery_groups,
++	};
+ 	int result;
+ 
+ 	battery->id = id;
+@@ -548,10 +556,6 @@ static int acpi_battery_add(struct acpi_sbs *sbs, int id)
+ 		goto end;
+ 	}
+ 
+-	result = device_create_file(&battery->bat->dev, &alarm_attr);
+-	if (result)
+-		goto end;
+-	battery->have_sysfs_alarm = 1;
+       end:
+ 	pr_info("%s [%s]: Battery Slot [%s] (battery %s)\n",
+ 	       ACPI_SBS_DEVICE_NAME, acpi_device_bid(sbs->device),
+@@ -563,11 +567,8 @@ static void acpi_battery_remove(struct acpi_sbs *sbs, int id)
+ {
+ 	struct acpi_battery *battery = &sbs->battery[id];
+ 
+-	if (battery->bat) {
+-		if (battery->have_sysfs_alarm)
+-			device_remove_file(&battery->bat->dev, &alarm_attr);
++	if (battery->bat)
+ 		power_supply_unregister(battery->bat);
+-	}
+ }
+ 
+ static int acpi_charger_add(struct acpi_sbs *sbs)
+diff --git a/drivers/base/core.c b/drivers/base/core.c
+index aeb4644817d57..cb323700e952f 100644
+--- a/drivers/base/core.c
++++ b/drivers/base/core.c
+@@ -25,6 +25,7 @@
+ #include <linux/mutex.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/netdevice.h>
++#include <linux/rcupdate.h>
+ #include <linux/sched/signal.h>
+ #include <linux/sched/mm.h>
+ #include <linux/string_helpers.h>
+@@ -2565,6 +2566,7 @@ static const char *dev_uevent_name(const struct kobject *kobj)
+ static int dev_uevent(const struct kobject *kobj, struct kobj_uevent_env *env)
+ {
+ 	const struct device *dev = kobj_to_dev(kobj);
++	struct device_driver *driver;
+ 	int retval = 0;
+ 
+ 	/* add device node properties if present */
+@@ -2593,8 +2595,12 @@ static int dev_uevent(const struct kobject *kobj, struct kobj_uevent_env *env)
+ 	if (dev->type && dev->type->name)
+ 		add_uevent_var(env, "DEVTYPE=%s", dev->type->name);
+ 
+-	if (dev->driver)
+-		add_uevent_var(env, "DRIVER=%s", dev->driver->name);
++	/* Synchronize with module_remove_driver() */
++	rcu_read_lock();
++	driver = READ_ONCE(dev->driver);
++	if (driver)
++		add_uevent_var(env, "DRIVER=%s", driver->name);
++	rcu_read_unlock();
+ 
+ 	/* Add common DT information about the device */
+ 	of_device_uevent(dev, env);
+@@ -2664,11 +2670,8 @@ static ssize_t uevent_show(struct device *dev, struct device_attribute *attr,
+ 	if (!env)
+ 		return -ENOMEM;
+ 
+-	/* Synchronize with really_probe() */
+-	device_lock(dev);
+ 	/* let the kset specific function add its keys */
+ 	retval = kset->uevent_ops->uevent(&dev->kobj, env);
+-	device_unlock(dev);
+ 	if (retval)
+ 		goto out;
+ 
+diff --git a/drivers/base/module.c b/drivers/base/module.c
+index a1b55da07127d..b0b79b9c189d4 100644
+--- a/drivers/base/module.c
++++ b/drivers/base/module.c
+@@ -7,6 +7,7 @@
+ #include <linux/errno.h>
+ #include <linux/slab.h>
+ #include <linux/string.h>
++#include <linux/rcupdate.h>
+ #include "base.h"
+ 
+ static char *make_driver_name(struct device_driver *drv)
+@@ -97,6 +98,9 @@ void module_remove_driver(struct device_driver *drv)
+ 	if (!drv)
+ 		return;
+ 
++	/* Synchronize with dev_uevent() */
++	synchronize_rcu();
++
+ 	sysfs_remove_link(&drv->p->kobj, "module");
+ 
+ 	if (drv->owner)
+diff --git a/drivers/bluetooth/btnxpuart.c b/drivers/bluetooth/btnxpuart.c
+index 83e8e27a5ecec..b5d40e0e05f31 100644
+--- a/drivers/bluetooth/btnxpuart.c
++++ b/drivers/bluetooth/btnxpuart.c
+@@ -340,7 +340,7 @@ static void ps_cancel_timer(struct btnxpuart_dev *nxpdev)
+ 	struct ps_data *psdata = &nxpdev->psdata;
+ 
+ 	flush_work(&psdata->work);
+-	del_timer_sync(&psdata->ps_timer);
++	timer_shutdown_sync(&psdata->ps_timer);
+ }
+ 
+ static void ps_control(struct hci_dev *hdev, u8 ps_state)
+diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
+index 26919556ef5f0..b72b36e0abed8 100644
+--- a/drivers/clocksource/sh_cmt.c
++++ b/drivers/clocksource/sh_cmt.c
+@@ -528,6 +528,7 @@ static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
+ static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
+ {
+ 	struct sh_cmt_channel *ch = dev_id;
++	unsigned long flags;
+ 
+ 	/* clear flags */
+ 	sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
+@@ -558,6 +559,8 @@ static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
+ 
+ 	ch->flags &= ~FLAG_SKIPEVENT;
+ 
++	raw_spin_lock_irqsave(&ch->lock, flags);
++
+ 	if (ch->flags & FLAG_REPROGRAM) {
+ 		ch->flags &= ~FLAG_REPROGRAM;
+ 		sh_cmt_clock_event_program_verify(ch, 1);
+@@ -570,6 +573,8 @@ static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
+ 
+ 	ch->flags &= ~FLAG_IRQCONTEXT;
+ 
++	raw_spin_unlock_irqrestore(&ch->lock, flags);
++
+ 	return IRQ_HANDLED;
+ }
+ 
+@@ -780,12 +785,18 @@ static int sh_cmt_clock_event_next(unsigned long delta,
+ 				   struct clock_event_device *ced)
+ {
+ 	struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
++	unsigned long flags;
+ 
+ 	BUG_ON(!clockevent_state_oneshot(ced));
++
++	raw_spin_lock_irqsave(&ch->lock, flags);
++
+ 	if (likely(ch->flags & FLAG_IRQCONTEXT))
+ 		ch->next_match_value = delta - 1;
+ 	else
+-		sh_cmt_set_next(ch, delta - 1);
++		__sh_cmt_set_next(ch, delta - 1);
++
++	raw_spin_unlock_irqrestore(&ch->lock, flags);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
+index 1c512ed3fa6d9..5c0016c77d2ab 100644
+--- a/drivers/gpio/gpiolib.c
++++ b/drivers/gpio/gpiolib.c
+@@ -15,6 +15,7 @@
+ #include <linux/kernel.h>
+ #include <linux/list.h>
+ #include <linux/module.h>
++#include <linux/nospec.h>
+ #include <linux/of.h>
+ #include <linux/pinctrl/consumer.h>
+ #include <linux/seq_file.h>
+@@ -164,7 +165,7 @@ struct gpio_desc *gpiochip_get_desc(struct gpio_chip *gc,
+ 	if (hwnum >= gdev->ngpio)
+ 		return ERR_PTR(-EINVAL);
+ 
+-	return &gdev->descs[hwnum];
++	return &gdev->descs[array_index_nospec(hwnum, gdev->ngpio)];
+ }
+ EXPORT_SYMBOL_GPL(gpiochip_get_desc);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index ea1bce13db941..eb663eb811563 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3561,6 +3561,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 	mutex_init(&adev->grbm_idx_mutex);
+ 	mutex_init(&adev->mn_lock);
+ 	mutex_init(&adev->virt.vf_errors.lock);
++	mutex_init(&adev->virt.rlcg_reg_lock);
+ 	hash_init(adev->mn_hash);
+ 	mutex_init(&adev->psp.mutex);
+ 	mutex_init(&adev->notifier_lock);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+index de9d7f3dc2336..99dd86337e841 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+@@ -258,9 +258,8 @@ amdgpu_job_prepare_job(struct drm_sched_job *sched_job,
+ 	struct dma_fence *fence = NULL;
+ 	int r;
+ 
+-	/* Ignore soft recovered fences here */
+ 	r = drm_sched_entity_error(s_entity);
+-	if (r && r != -ENODATA)
++	if (r)
+ 		goto error;
+ 
+ 	if (!fence && job->gang_submit)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
+index ca5c86e5f7cd6..8e8afbd237bcd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
+@@ -334,7 +334,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size
+ 
+ 	set_ta_context_funcs(psp, ta_type, &context);
+ 
+-	if (!context->initialized) {
++	if (!context || !context->initialized) {
+ 		dev_err(adev->dev, "TA is not initialized\n");
+ 		ret = -EINVAL;
+ 		goto err_free_shared_buf;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 67b75ff0f7c37..7cba98f8bbdca 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1780,12 +1780,15 @@ static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
+ int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
+ 		struct ras_dispatch_if *info)
+ {
+-	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
+-	struct ras_ih_data *data = &obj->ih_data;
++	struct ras_manager *obj;
++	struct ras_ih_data *data;
+ 
++	obj = amdgpu_ras_find_obj(adev, &info->head);
+ 	if (!obj)
+ 		return -EINVAL;
+ 
++	data = &obj->ih_data;
++
+ 	if (data->inuse == 0)
+ 		return 0;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+index 96857ae7fb5bc..ff4f52e07cc0d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+@@ -1003,6 +1003,9 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
+ 	scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
+ 	scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
+ 	scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;
++
++	mutex_lock(&adev->virt.rlcg_reg_lock);
++
+ 	if (reg_access_ctrl->spare_int)
+ 		spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
+ 
+@@ -1058,6 +1061,9 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
+ 	}
+ 
+ 	ret = readl(scratch_reg0);
++
++	mutex_unlock(&adev->virt.rlcg_reg_lock);
++
+ 	return ret;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+index fabb83e9d9aec..23b6efa9d25df 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+@@ -263,6 +263,8 @@ struct amdgpu_virt {
+ 
+ 	/* the ucode id to signal the autoload */
+ 	uint32_t autoload_ucode_id;
++
++	struct mutex rlcg_reg_lock;
+ };
+ 
+ struct amdgpu_video_codec_info;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+index 349416e176a12..1cf1498204678 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+@@ -102,6 +102,11 @@ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
+ 	if (!r)
+ 		r = amdgpu_sync_push_to_job(&sync, p->job);
+ 	amdgpu_sync_free(&sync);
++
++	if (r) {
++		p->num_dw_left = 0;
++		amdgpu_job_free(p->job);
++	}
+ 	return r;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 60db3800666ec..94059aef762be 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2628,7 +2628,8 @@ static int dm_suspend(void *handle)
+ 
+ 		dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
+ 
+-		dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
++		if (dm->cached_dc_state)
++			dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
+ 
+ 		amdgpu_dm_commit_zero_streams(dm->dc);
+ 
+@@ -6483,7 +6484,8 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
+ 		aconnector->dc_sink = aconnector->dc_link->local_sink ?
+ 		aconnector->dc_link->local_sink :
+ 		aconnector->dc_em_sink;
+-		dc_sink_retain(aconnector->dc_sink);
++		if (aconnector->dc_sink)
++			dc_sink_retain(aconnector->dc_sink);
+ 	}
+ }
+ 
+@@ -7296,7 +7298,8 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
+ 				drm_add_modes_noedid(connector, 1920, 1080);
+ 	} else {
+ 		amdgpu_dm_connector_ddc_get_modes(connector, edid);
+-		amdgpu_dm_connector_add_common_modes(encoder, connector);
++		if (encoder)
++			amdgpu_dm_connector_add_common_modes(encoder, connector);
+ 		amdgpu_dm_connector_add_freesync_modes(connector, edid);
+ 	}
+ 	amdgpu_dm_fbc_init(connector);
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index 2104511f3b863..3880ddf1c820f 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -1266,6 +1266,9 @@ static bool is_dsc_need_re_compute(
+ 		}
+ 	}
+ 
++	if (new_stream_on_link_num == 0)
++		return false;
++
+ 	/* check current_state if there stream on link but it is not in
+ 	 * new request state
+ 	 */
+diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
+index b621b97711b61..a7f5b0f6272ce 100644
+--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
+@@ -162,7 +162,12 @@ static void set_hpo_fixed_vs_pe_retimer_dp_link_test_pattern(struct dc_link *lin
+ 		link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(
+ 				link_res->hpo_dp_link_enc, tp_params);
+ 	}
++
+ 	link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
++
++	// Give retimer extra time to lock before updating DP_TRAINING_PATTERN_SET to TPS1
++	if (tp_params->dp_phy_pattern == DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE)
++		msleep(30);
+ }
+ 
+ static void set_hpo_fixed_vs_pe_retimer_dp_lane_settings(struct dc_link *link,
+diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+index 9e4f8a4104a34..7bf46e4974f88 100644
+--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+@@ -927,7 +927,7 @@ static int pp_dpm_switch_power_profile(void *handle,
+ 		enum PP_SMC_POWER_PROFILE type, bool en)
+ {
+ 	struct pp_hwmgr *hwmgr = handle;
+-	long workload;
++	long workload[1];
+ 	uint32_t index;
+ 
+ 	if (!hwmgr || !hwmgr->pm_en)
+@@ -945,12 +945,12 @@ static int pp_dpm_switch_power_profile(void *handle,
+ 		hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
+ 		index = fls(hwmgr->workload_mask);
+ 		index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
+-		workload = hwmgr->workload_setting[index];
++		workload[0] = hwmgr->workload_setting[index];
+ 	} else {
+ 		hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
+ 		index = fls(hwmgr->workload_mask);
+ 		index = index <= Workload_Policy_Max ? index - 1 : 0;
+-		workload = hwmgr->workload_setting[index];
++		workload[0] = hwmgr->workload_setting[index];
+ 	}
+ 
+ 	if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
+@@ -960,7 +960,7 @@ static int pp_dpm_switch_power_profile(void *handle,
+ 	}
+ 
+ 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+-		hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
++		hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
+index 1d829402cd2e2..f4bd8e9357e22 100644
+--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
++++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
+@@ -269,7 +269,7 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_set
+ 						struct pp_power_state *new_ps)
+ {
+ 	uint32_t index;
+-	long workload;
++	long workload[1];
+ 
+ 	if (hwmgr->not_vf) {
+ 		if (!skip_display_settings)
+@@ -294,10 +294,10 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_set
+ 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+ 		index = fls(hwmgr->workload_mask);
+ 		index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
+-		workload = hwmgr->workload_setting[index];
++		workload[0] = hwmgr->workload_setting[index];
+ 
+-		if (hwmgr->power_profile_mode != workload && hwmgr->hwmgr_func->set_power_profile_mode)
+-			hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
++		if (hwmgr->power_profile_mode != workload[0] && hwmgr->hwmgr_func->set_power_profile_mode)
++			hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0);
+ 	}
+ 
+ 	return 0;
+diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+index aa91730e4eaff..163864bd51c34 100644
+--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+@@ -2957,6 +2957,7 @@ static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr)
+ 
+ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
+ {
++	struct amdgpu_device *adev = hwmgr->adev;
+ 	struct smu7_hwmgr *data;
+ 	int result = 0;
+ 
+@@ -2993,40 +2994,37 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
+ 	/* Initalize Dynamic State Adjustment Rule Settings */
+ 	result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
+ 
+-	if (0 == result) {
+-		struct amdgpu_device *adev = hwmgr->adev;
++	if (result)
++		goto fail;
+ 
+-		data->is_tlu_enabled = false;
++	data->is_tlu_enabled = false;
+ 
+-		hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
++	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
+ 							SMU7_MAX_HARDWARE_POWERLEVELS;
+-		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
+-		hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
++	hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
++	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
+ 
+-		data->pcie_gen_cap = adev->pm.pcie_gen_mask;
+-		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+-			data->pcie_spc_cap = 20;
+-		else
+-			data->pcie_spc_cap = 16;
+-		data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
+-
+-		hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
+-/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
+-		hwmgr->platform_descriptor.clockStep.engineClock = 500;
+-		hwmgr->platform_descriptor.clockStep.memoryClock = 500;
+-		smu7_thermal_parameter_init(hwmgr);
+-	} else {
+-		/* Ignore return value in here, we are cleaning up a mess. */
+-		smu7_hwmgr_backend_fini(hwmgr);
+-	}
++	data->pcie_gen_cap = adev->pm.pcie_gen_mask;
++	if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
++		data->pcie_spc_cap = 20;
++	else
++		data->pcie_spc_cap = 16;
++	data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
++
++	hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
++	/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
++	hwmgr->platform_descriptor.clockStep.engineClock = 500;
++	hwmgr->platform_descriptor.clockStep.memoryClock = 500;
++	smu7_thermal_parameter_init(hwmgr);
+ 
+ 	result = smu7_update_edc_leakage_table(hwmgr);
+-	if (result) {
+-		smu7_hwmgr_backend_fini(hwmgr);
+-		return result;
+-	}
++	if (result)
++		goto fail;
+ 
+ 	return 0;
++fail:
++	smu7_hwmgr_backend_fini(hwmgr);
++	return result;
+ }
+ 
+ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
+@@ -3316,8 +3314,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+ 			const struct pp_power_state *current_ps)
+ {
+ 	struct amdgpu_device *adev = hwmgr->adev;
+-	struct smu7_power_state *smu7_ps =
+-				cast_phw_smu7_power_state(&request_ps->hardware);
++	struct smu7_power_state *smu7_ps;
+ 	uint32_t sclk;
+ 	uint32_t mclk;
+ 	struct PP_Clocks minimum_clocks = {0};
+@@ -3334,6 +3331,10 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+ 	uint32_t latency;
+ 	bool latency_allowed = false;
+ 
++	smu7_ps = cast_phw_smu7_power_state(&request_ps->hardware);
++	if (!smu7_ps)
++		return -EINVAL;
++
+ 	data->battery_state = (PP_StateUILabel_Battery ==
+ 			request_ps->classification.ui_label);
+ 	data->mclk_ignore_signal = false;
+diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
+index b015a601b385a..eb744401e0567 100644
+--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
++++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
+@@ -1065,16 +1065,18 @@ static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+ 				struct pp_power_state  *prequest_ps,
+ 			const struct pp_power_state *pcurrent_ps)
+ {
+-	struct smu8_power_state *smu8_ps =
+-				cast_smu8_power_state(&prequest_ps->hardware);
+-
+-	const struct smu8_power_state *smu8_current_ps =
+-				cast_const_smu8_power_state(&pcurrent_ps->hardware);
+-
++	struct smu8_power_state *smu8_ps;
++	const struct smu8_power_state *smu8_current_ps;
+ 	struct smu8_hwmgr *data = hwmgr->backend;
+ 	struct PP_Clocks clocks = {0, 0, 0, 0};
+ 	bool force_high;
+ 
++	smu8_ps = cast_smu8_power_state(&prequest_ps->hardware);
++	smu8_current_ps = cast_const_smu8_power_state(&pcurrent_ps->hardware);
++
++	if (!smu8_ps || !smu8_current_ps)
++		return -EINVAL;
++
+ 	smu8_ps->need_dfs_bypass = true;
+ 
+ 	data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
+diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+index 6d6bc6a380b36..d43a530aba0e3 100644
+--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+@@ -3259,8 +3259,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+ 			const struct pp_power_state *current_ps)
+ {
+ 	struct amdgpu_device *adev = hwmgr->adev;
+-	struct vega10_power_state *vega10_ps =
+-				cast_phw_vega10_power_state(&request_ps->hardware);
++	struct vega10_power_state *vega10_ps;
+ 	uint32_t sclk;
+ 	uint32_t mclk;
+ 	struct PP_Clocks minimum_clocks = {0};
+@@ -3278,6 +3277,10 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+ 	uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
+ 	uint32_t latency;
+ 
++	vega10_ps = cast_phw_vega10_power_state(&request_ps->hardware);
++	if (!vega10_ps)
++		return -EINVAL;
++
+ 	data->battery_state = (PP_StateUILabel_Battery ==
+ 			request_ps->classification.ui_label);
+ 
+@@ -3415,13 +3418,17 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
+ 	const struct vega10_power_state *vega10_ps =
+ 			cast_const_phw_vega10_power_state(states->pnew_state);
+ 	struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
+-	uint32_t sclk = vega10_ps->performance_levels
+-			[vega10_ps->performance_level_count - 1].gfx_clock;
+ 	struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
+-	uint32_t mclk = vega10_ps->performance_levels
+-			[vega10_ps->performance_level_count - 1].mem_clock;
++	uint32_t sclk, mclk;
+ 	uint32_t i;
+ 
++	if (vega10_ps == NULL)
++		return -EINVAL;
++	sclk = vega10_ps->performance_levels
++			[vega10_ps->performance_level_count - 1].gfx_clock;
++	mclk = vega10_ps->performance_levels
++			[vega10_ps->performance_level_count - 1].mem_clock;
++
+ 	for (i = 0; i < sclk_table->count; i++) {
+ 		if (sclk == sclk_table->dpm_levels[i].value)
+ 			break;
+@@ -3728,6 +3735,9 @@ static int vega10_generate_dpm_level_enable_mask(
+ 			cast_const_phw_vega10_power_state(states->pnew_state);
+ 	int i;
+ 
++	if (vega10_ps == NULL)
++		return -EINVAL;
++
+ 	PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
+ 			"Attempt to Trim DPM States Failed!",
+ 			return -1);
+@@ -4995,6 +5005,8 @@ static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
+ 
+ 	vega10_psa = cast_const_phw_vega10_power_state(pstate1);
+ 	vega10_psb = cast_const_phw_vega10_power_state(pstate2);
++	if (vega10_psa == NULL || vega10_psb == NULL)
++		return -EINVAL;
+ 
+ 	/* If the two states don't even have the same number of performance levels
+ 	 * they cannot be the same state.
+@@ -5128,6 +5140,8 @@ static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
+ 		return -EINVAL;
+ 
+ 	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
++	if (vega10_ps == NULL)
++		return -EINVAL;
+ 
+ 	vega10_ps->performance_levels
+ 	[vega10_ps->performance_level_count - 1].gfx_clock =
+@@ -5179,6 +5193,8 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
+ 		return -EINVAL;
+ 
+ 	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
++	if (vega10_ps == NULL)
++		return -EINVAL;
+ 
+ 	vega10_ps->performance_levels
+ 	[vega10_ps->performance_level_count - 1].mem_clock =
+@@ -5420,6 +5436,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
+ 		return;
+ 
+ 	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
++	if (vega10_ps == NULL)
++		return;
++
+ 	max_level = vega10_ps->performance_level_count - 1;
+ 
+ 	if (vega10_ps->performance_levels[max_level].gfx_clock !=
+@@ -5442,6 +5461,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
+ 
+ 	ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
+ 	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
++	if (vega10_ps == NULL)
++		return;
++
+ 	max_level = vega10_ps->performance_level_count - 1;
+ 
+ 	if (vega10_ps->performance_levels[max_level].gfx_clock !=
+@@ -5632,6 +5654,8 @@ static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_
+ 		return -EINVAL;
+ 
+ 	vega10_ps = cast_const_phw_vega10_power_state(state);
++	if (vega10_ps == NULL)
++		return -EINVAL;
+ 
+ 	i = index > vega10_ps->performance_level_count - 1 ?
+ 			vega10_ps->performance_level_count - 1 : index;
+diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+index 56e4c312cb7a9..1402e468aa90f 100644
+--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+@@ -1846,7 +1846,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ {
+ 	int ret = 0;
+ 	int index = 0;
+-	long workload;
++	long workload[1];
+ 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ 
+ 	if (!skip_display_settings) {
+@@ -1886,10 +1886,10 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ 		smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
+ 		index = fls(smu->workload_mask);
+ 		index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
+-		workload = smu->workload_setting[index];
++		workload[0] = smu->workload_setting[index];
+ 
+-		if (smu->power_profile_mode != workload)
+-			smu_bump_power_profile_mode(smu, &workload, 0);
++		if (smu->power_profile_mode != workload[0])
++			smu_bump_power_profile_mode(smu, workload, 0);
+ 	}
+ 
+ 	return ret;
+@@ -1939,7 +1939,7 @@ static int smu_switch_power_profile(void *handle,
+ {
+ 	struct smu_context *smu = handle;
+ 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+-	long workload;
++	long workload[1];
+ 	uint32_t index;
+ 
+ 	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
+@@ -1952,17 +1952,17 @@ static int smu_switch_power_profile(void *handle,
+ 		smu->workload_mask &= ~(1 << smu->workload_prority[type]);
+ 		index = fls(smu->workload_mask);
+ 		index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
+-		workload = smu->workload_setting[index];
++		workload[0] = smu->workload_setting[index];
+ 	} else {
+ 		smu->workload_mask |= (1 << smu->workload_prority[type]);
+ 		index = fls(smu->workload_mask);
+ 		index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
+-		workload = smu->workload_setting[index];
++		workload[0] = smu->workload_setting[index];
+ 	}
+ 
+ 	if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
+ 		smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
+-		smu_bump_power_profile_mode(smu, &workload, 0);
++		smu_bump_power_profile_mode(smu, workload, 0);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+index 6a4f20fccf841..7b0bc9704eacb 100644
+--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
++++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+@@ -1027,7 +1027,6 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
+ 	u32 status_reg;
+ 	u8 *buffer = msg->buffer;
+ 	unsigned int i;
+-	int num_transferred = 0;
+ 	int ret;
+ 
+ 	/* Buffer size of AUX CH is 16 bytes */
+@@ -1079,7 +1078,6 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
+ 			reg = buffer[i];
+ 			writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
+ 			       4 * i);
+-			num_transferred++;
+ 		}
+ 	}
+ 
+@@ -1127,7 +1125,6 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
+ 			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
+ 				    4 * i);
+ 			buffer[i] = (unsigned char)reg;
+-			num_transferred++;
+ 		}
+ 	}
+ 
+@@ -1144,7 +1141,7 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
+ 		 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ)
+ 		msg->reply = DP_AUX_NATIVE_REPLY_ACK;
+ 
+-	return num_transferred > 0 ? num_transferred : -EBUSY;
++	return msg->size;
+ 
+ aux_error:
+ 	/* if aux err happen, reset aux */
+diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
+index 9023c0216a8a4..6ead31701e79e 100644
+--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
++++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
+@@ -4024,6 +4024,7 @@ static int drm_dp_mst_handle_up_req(struct drm_dp_mst_topology_mgr *mgr)
+ 	if (up_req->msg.req_type == DP_CONNECTION_STATUS_NOTIFY) {
+ 		const struct drm_dp_connection_status_notify *conn_stat =
+ 			&up_req->msg.u.conn_stat;
++		bool handle_csn;
+ 
+ 		drm_dbg_kms(mgr->dev, "Got CSN: pn: %d ldps:%d ddps: %d mcs: %d ip: %d pdt: %d\n",
+ 			    conn_stat->port_number,
+@@ -4032,6 +4033,16 @@ static int drm_dp_mst_handle_up_req(struct drm_dp_mst_topology_mgr *mgr)
+ 			    conn_stat->message_capability_status,
+ 			    conn_stat->input_port,
+ 			    conn_stat->peer_device_type);
++
++		mutex_lock(&mgr->probe_lock);
++		handle_csn = mgr->mst_primary->link_address_sent;
++		mutex_unlock(&mgr->probe_lock);
++
++		if (!handle_csn) {
++			drm_dbg_kms(mgr->dev, "Got CSN before finish topology probing. Skip it.");
++			kfree(up_req);
++			goto out;
++		}
+ 	} else if (up_req->msg.req_type == DP_RESOURCE_STATUS_NOTIFY) {
+ 		const struct drm_dp_resource_status_notify *res_stat =
+ 			&up_req->msg.u.resource_stat;
+diff --git a/drivers/gpu/drm/drm_client_modeset.c b/drivers/gpu/drm/drm_client_modeset.c
+index 0683a129b3628..51df7244de718 100644
+--- a/drivers/gpu/drm/drm_client_modeset.c
++++ b/drivers/gpu/drm/drm_client_modeset.c
+@@ -869,6 +869,11 @@ int drm_client_modeset_probe(struct drm_client_dev *client, unsigned int width,
+ 
+ 			kfree(modeset->mode);
+ 			modeset->mode = drm_mode_duplicate(dev, mode);
++			if (!modeset->mode) {
++				ret = -ENOMEM;
++				break;
++			}
++
+ 			drm_connector_get(connector);
+ 			modeset->connectors[modeset->num_connectors++] = connector;
+ 			modeset->x = offset->x;
+diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+index 310654542b42c..a59c17ec7fa36 100644
+--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
++++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+@@ -290,6 +290,41 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf)
+ 	return i915_error_to_vmf_fault(err);
+ }
+ 
++static void set_address_limits(struct vm_area_struct *area,
++			       struct i915_vma *vma,
++			       unsigned long obj_offset,
++			       unsigned long *start_vaddr,
++			       unsigned long *end_vaddr)
++{
++	unsigned long vm_start, vm_end, vma_size; /* user's memory parameters */
++	long start, end; /* memory boundaries */
++
++	/*
++	 * Let's move into the ">> PAGE_SHIFT"
++	 * domain to be sure not to lose bits
++	 */
++	vm_start = area->vm_start >> PAGE_SHIFT;
++	vm_end = area->vm_end >> PAGE_SHIFT;
++	vma_size = vma->size >> PAGE_SHIFT;
++
++	/*
++	 * Calculate the memory boundaries by considering the offset
++	 * provided by the user during memory mapping and the offset
++	 * provided for the partial mapping.
++	 */
++	start = vm_start;
++	start -= obj_offset;
++	start += vma->gtt_view.partial.offset;
++	end = start + vma_size;
++
++	start = max_t(long, start, vm_start);
++	end = min_t(long, end, vm_end);
++
++	/* Let's move back into the "<< PAGE_SHIFT" domain */
++	*start_vaddr = (unsigned long)start << PAGE_SHIFT;
++	*end_vaddr = (unsigned long)end << PAGE_SHIFT;
++}
++
+ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
+ {
+ #define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT)
+@@ -302,14 +337,18 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
+ 	struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
+ 	bool write = area->vm_flags & VM_WRITE;
+ 	struct i915_gem_ww_ctx ww;
++	unsigned long obj_offset;
++	unsigned long start, end; /* memory boundaries */
+ 	intel_wakeref_t wakeref;
+ 	struct i915_vma *vma;
+ 	pgoff_t page_offset;
++	unsigned long pfn;
+ 	int srcu;
+ 	int ret;
+ 
+-	/* We don't use vmf->pgoff since that has the fake offset */
++	obj_offset = area->vm_pgoff - drm_vma_node_start(&mmo->vma_node);
+ 	page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
++	page_offset += obj_offset;
+ 
+ 	trace_i915_gem_object_fault(obj, page_offset, true, write);
+ 
+@@ -402,12 +441,14 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
+ 	if (ret)
+ 		goto err_unpin;
+ 
++	set_address_limits(area, vma, obj_offset, &start, &end);
++
++	pfn = (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT;
++	pfn += (start - area->vm_start) >> PAGE_SHIFT;
++	pfn += obj_offset - vma->gtt_view.partial.offset;
++
+ 	/* Finally, remap it using the new GTT offset */
+-	ret = remap_io_mapping(area,
+-			       area->vm_start + (vma->gtt_view.partial.offset << PAGE_SHIFT),
+-			       (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
+-			       min_t(u64, vma->size, area->vm_end - area->vm_start),
+-			       &ggtt->iomap);
++	ret = remap_io_mapping(area, start, pfn, end - start, &ggtt->iomap);
+ 	if (ret)
+ 		goto err_fence;
+ 
+@@ -1088,6 +1129,8 @@ int i915_gem_fb_mmap(struct drm_i915_gem_object *obj, struct vm_area_struct *vma
+ 		mmo = mmap_offset_attach(obj, mmap_type, NULL);
+ 		if (IS_ERR(mmo))
+ 			return PTR_ERR(mmo);
++
++		vma->vm_pgoff += drm_vma_node_start(&mmo->vma_node);
+ 	}
+ 
+ 	/*
+diff --git a/drivers/gpu/drm/lima/lima_drv.c b/drivers/gpu/drm/lima/lima_drv.c
+index 10fd9154cc465..8c9b656eeb59d 100644
+--- a/drivers/gpu/drm/lima/lima_drv.c
++++ b/drivers/gpu/drm/lima/lima_drv.c
+@@ -486,3 +486,4 @@ module_platform_driver(lima_platform_driver);
+ MODULE_AUTHOR("Lima Project Developers");
+ MODULE_DESCRIPTION("Lima DRM Driver");
+ MODULE_LICENSE("GPL v2");
++MODULE_SOFTDEP("pre: governor_simpleondemand");
+diff --git a/drivers/gpu/drm/mgag200/mgag200_i2c.c b/drivers/gpu/drm/mgag200/mgag200_i2c.c
+index 0c48bdf3e7f80..f5c5d06d0d4bb 100644
+--- a/drivers/gpu/drm/mgag200/mgag200_i2c.c
++++ b/drivers/gpu/drm/mgag200/mgag200_i2c.c
+@@ -31,6 +31,8 @@
+ #include <linux/i2c.h>
+ #include <linux/pci.h>
+ 
++#include <drm/drm_managed.h>
++
+ #include "mgag200_drv.h"
+ 
+ static int mga_i2c_read_gpio(struct mga_device *mdev)
+@@ -86,7 +88,7 @@ static int mga_gpio_getscl(void *data)
+ 	return (mga_i2c_read_gpio(mdev) & i2c->clock) ? 1 : 0;
+ }
+ 
+-static void mgag200_i2c_release(void *res)
++static void mgag200_i2c_release(struct drm_device *dev, void *res)
+ {
+ 	struct mga_i2c_chan *i2c = res;
+ 
+@@ -115,7 +117,7 @@ int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan *i2c)
+ 	i2c->adapter.algo_data = &i2c->bit;
+ 
+ 	i2c->bit.udelay = 10;
+-	i2c->bit.timeout = 2;
++	i2c->bit.timeout = usecs_to_jiffies(2200);
+ 	i2c->bit.data = i2c;
+ 	i2c->bit.setsda		= mga_gpio_setsda;
+ 	i2c->bit.setscl		= mga_gpio_setscl;
+@@ -126,5 +128,5 @@ int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan *i2c)
+ 	if (ret)
+ 		return ret;
+ 
+-	return devm_add_action_or_reset(dev->dev, mgag200_i2c_release, i2c);
++	return drmm_add_action_or_reset(dev, mgag200_i2c_release, i2c);
+ }
+diff --git a/drivers/gpu/drm/nouveau/nouveau_uvmm.c b/drivers/gpu/drm/nouveau/nouveau_uvmm.c
+index 2bbcdc649e862..3d41e590d4712 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_uvmm.c
++++ b/drivers/gpu/drm/nouveau/nouveau_uvmm.c
+@@ -1320,6 +1320,7 @@ nouveau_uvmm_bind_job_submit(struct nouveau_job *job)
+ 
+ 		drm_gpuva_for_each_op(va_op, op->ops) {
+ 			struct drm_gem_object *obj = op_gem_obj(va_op);
++			struct nouveau_bo *nvbo;
+ 
+ 			if (unlikely(!obj))
+ 				continue;
+@@ -1330,8 +1331,9 @@ nouveau_uvmm_bind_job_submit(struct nouveau_job *job)
+ 			if (unlikely(va_op->op == DRM_GPUVA_OP_UNMAP))
+ 				continue;
+ 
+-			ret = nouveau_bo_validate(nouveau_gem_object(obj),
+-						  true, false);
++			nvbo = nouveau_gem_object(obj);
++			nouveau_bo_placement_set(nvbo, nvbo->valid_domains, 0);
++			ret = nouveau_bo_validate(nvbo, true, false);
+ 			if (ret) {
+ 				op = list_last_op(&bind_job->ops);
+ 				goto unwind;
+diff --git a/drivers/gpu/drm/radeon/pptable.h b/drivers/gpu/drm/radeon/pptable.h
+index 844f0490bf31f..ce8832916704f 100644
+--- a/drivers/gpu/drm/radeon/pptable.h
++++ b/drivers/gpu/drm/radeon/pptable.h
+@@ -439,7 +439,7 @@ typedef struct _StateArray{
+     //how many states we have 
+     UCHAR ucNumEntries;
+     
+-    ATOM_PPLIB_STATE_V2 states[] __counted_by(ucNumEntries);
++    ATOM_PPLIB_STATE_V2 states[] /* __counted_by(ucNumEntries) */;
+ }StateArray;
+ 
+ 
+diff --git a/drivers/hwmon/corsair-psu.c b/drivers/hwmon/corsair-psu.c
+index 2c7c92272fe39..f8f22b8a67cdf 100644
+--- a/drivers/hwmon/corsair-psu.c
++++ b/drivers/hwmon/corsair-psu.c
+@@ -875,15 +875,16 @@ static const struct hid_device_id corsairpsu_idtable[] = {
+ 	{ HID_USB_DEVICE(0x1b1c, 0x1c04) }, /* Corsair HX650i */
+ 	{ HID_USB_DEVICE(0x1b1c, 0x1c05) }, /* Corsair HX750i */
+ 	{ HID_USB_DEVICE(0x1b1c, 0x1c06) }, /* Corsair HX850i */
+-	{ HID_USB_DEVICE(0x1b1c, 0x1c07) }, /* Corsair HX1000i Series 2022 */
+-	{ HID_USB_DEVICE(0x1b1c, 0x1c08) }, /* Corsair HX1200i */
++	{ HID_USB_DEVICE(0x1b1c, 0x1c07) }, /* Corsair HX1000i Legacy */
++	{ HID_USB_DEVICE(0x1b1c, 0x1c08) }, /* Corsair HX1200i Legacy */
+ 	{ HID_USB_DEVICE(0x1b1c, 0x1c09) }, /* Corsair RM550i */
+ 	{ HID_USB_DEVICE(0x1b1c, 0x1c0a) }, /* Corsair RM650i */
+ 	{ HID_USB_DEVICE(0x1b1c, 0x1c0b) }, /* Corsair RM750i */
+ 	{ HID_USB_DEVICE(0x1b1c, 0x1c0c) }, /* Corsair RM850i */
+ 	{ HID_USB_DEVICE(0x1b1c, 0x1c0d) }, /* Corsair RM1000i */
+ 	{ HID_USB_DEVICE(0x1b1c, 0x1c1e) }, /* Corsair HX1000i Series 2023 */
+-	{ HID_USB_DEVICE(0x1b1c, 0x1c1f) }, /* Corsair HX1500i Series 2022 and 2023 */
++	{ HID_USB_DEVICE(0x1b1c, 0x1c1f) }, /* Corsair HX1500i Legacy and Series 2023 */
++	{ HID_USB_DEVICE(0x1b1c, 0x1c23) }, /* Corsair HX1200i Series 2023 */
+ 	{ },
+ };
+ MODULE_DEVICE_TABLE(hid, corsairpsu_idtable);
+diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
+index 5cc32a465f12e..b17411e97be68 100644
+--- a/drivers/i2c/busses/i2c-qcom-geni.c
++++ b/drivers/i2c/busses/i2c-qcom-geni.c
+@@ -991,8 +991,11 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
+ 		return ret;
+ 
+ 	ret = geni_se_resources_on(&gi2c->se);
+-	if (ret)
++	if (ret) {
++		clk_disable_unprepare(gi2c->core_clk);
++		geni_icc_disable(&gi2c->se);
+ 		return ret;
++	}
+ 
+ 	enable_irq(gi2c->irq);
+ 	gi2c->suspended = 0;
+diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c
+index 138c3f5e0093a..6520e09743912 100644
+--- a/drivers/i2c/i2c-smbus.c
++++ b/drivers/i2c/i2c-smbus.c
+@@ -34,6 +34,7 @@ static int smbus_do_alert(struct device *dev, void *addrp)
+ 	struct i2c_client *client = i2c_verify_client(dev);
+ 	struct alert_data *data = addrp;
+ 	struct i2c_driver *driver;
++	int ret;
+ 
+ 	if (!client || client->addr != data->addr)
+ 		return 0;
+@@ -47,16 +48,47 @@ static int smbus_do_alert(struct device *dev, void *addrp)
+ 	device_lock(dev);
+ 	if (client->dev.driver) {
+ 		driver = to_i2c_driver(client->dev.driver);
+-		if (driver->alert)
++		if (driver->alert) {
++			/* Stop iterating after we find the device */
+ 			driver->alert(client, data->type, data->data);
+-		else
++			ret = -EBUSY;
++		} else {
+ 			dev_warn(&client->dev, "no driver alert()!\n");
+-	} else
++			ret = -EOPNOTSUPP;
++		}
++	} else {
+ 		dev_dbg(&client->dev, "alert with no driver\n");
++		ret = -ENODEV;
++	}
++	device_unlock(dev);
++
++	return ret;
++}
++
++/* Same as above, but call back all drivers with alert handler */
++
++static int smbus_do_alert_force(struct device *dev, void *addrp)
++{
++	struct i2c_client *client = i2c_verify_client(dev);
++	struct alert_data *data = addrp;
++	struct i2c_driver *driver;
++
++	if (!client || (client->flags & I2C_CLIENT_TEN))
++		return 0;
++
++	/*
++	 * Drivers should either disable alerts, or provide at least
++	 * a minimal handler. Lock so the driver won't change.
++	 */
++	device_lock(dev);
++	if (client->dev.driver) {
++		driver = to_i2c_driver(client->dev.driver);
++		if (driver->alert)
++			driver->alert(client, data->type, data->data);
++	}
+ 	device_unlock(dev);
+ 
+-	/* Stop iterating after we find the device */
+-	return -EBUSY;
++	return 0;
+ }
+ 
+ /*
+@@ -67,6 +99,7 @@ static irqreturn_t smbus_alert(int irq, void *d)
+ {
+ 	struct i2c_smbus_alert *alert = d;
+ 	struct i2c_client *ara;
++	unsigned short prev_addr = I2C_CLIENT_END; /* Not a valid address */
+ 
+ 	ara = alert->ara;
+ 
+@@ -94,8 +127,25 @@ static irqreturn_t smbus_alert(int irq, void *d)
+ 			data.addr, data.data);
+ 
+ 		/* Notify driver for the device which issued the alert */
+-		device_for_each_child(&ara->adapter->dev, &data,
+-				      smbus_do_alert);
++		status = device_for_each_child(&ara->adapter->dev, &data,
++					       smbus_do_alert);
++		/*
++		 * If we read the same address more than once, and the alert
++		 * was not handled by a driver, it won't do any good to repeat
++		 * the loop because it will never terminate. Try again, this
++		 * time calling the alert handlers of all devices connected to
++		 * the bus, and abort the loop afterwards. If this helps, we
++		 * are all set. If it doesn't, there is nothing else we can do,
++		 * so we might as well abort the loop.
++		 * Note: This assumes that a driver with alert handler handles
++		 * the alert properly and clears it if necessary.
++		 */
++		if (data.addr == prev_addr && status != -EBUSY) {
++			device_for_each_child(&ara->adapter->dev, &data,
++					      smbus_do_alert_force);
++			break;
++		}
++		prev_addr = data.addr;
+ 	}
+ 
+ 	return IRQ_HANDLED;
+diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
+index 9d8f2c4060431..b35903a06902f 100644
+--- a/drivers/irqchip/irq-loongarch-cpu.c
++++ b/drivers/irqchip/irq-loongarch-cpu.c
+@@ -18,11 +18,13 @@ struct fwnode_handle *cpuintc_handle;
+ 
+ static u32 lpic_gsi_to_irq(u32 gsi)
+ {
++	int irq = 0;
++
+ 	/* Only pch irqdomain transferring is required for LoongArch. */
+ 	if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
+-		return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
++		irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
+ 
+-	return 0;
++	return (irq > 0) ? irq : 0;
+ }
+ 
+ static struct fwnode_handle *lpic_get_gsi_domain_id(u32 gsi)
+diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
+index 58881d3139792..244a8d489cac6 100644
+--- a/drivers/irqchip/irq-mbigen.c
++++ b/drivers/irqchip/irq-mbigen.c
+@@ -64,6 +64,20 @@ struct mbigen_device {
+ 	void __iomem		*base;
+ };
+ 
++static inline unsigned int get_mbigen_node_offset(unsigned int nid)
++{
++	unsigned int offset = nid * MBIGEN_NODE_OFFSET;
++
++	/*
++	 * To avoid touched clear register in unexpected way, we need to directly
++	 * skip clear register when access to more than 10 mbigen nodes.
++	 */
++	if (nid >= (REG_MBIGEN_CLEAR_OFFSET / MBIGEN_NODE_OFFSET))
++		offset += MBIGEN_NODE_OFFSET;
++
++	return offset;
++}
++
+ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
+ {
+ 	unsigned int nid, pin;
+@@ -72,8 +86,7 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
+ 	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
+ 	pin = hwirq % IRQS_PER_MBIGEN_NODE;
+ 
+-	return pin * 4 + nid * MBIGEN_NODE_OFFSET
+-			+ REG_MBIGEN_VEC_OFFSET;
++	return pin * 4 + get_mbigen_node_offset(nid) + REG_MBIGEN_VEC_OFFSET;
+ }
+ 
+ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
+@@ -88,8 +101,7 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
+ 	*mask = 1 << (irq_ofst % 32);
+ 	ofst = irq_ofst / 32 * 4;
+ 
+-	*addr = ofst + nid * MBIGEN_NODE_OFFSET
+-		+ REG_MBIGEN_TYPE_OFFSET;
++	*addr = ofst + get_mbigen_node_offset(nid) + REG_MBIGEN_TYPE_OFFSET;
+ }
+ 
+ static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
+diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
+index f88df39f41291..471e04eaf3230 100644
+--- a/drivers/irqchip/irq-meson-gpio.c
++++ b/drivers/irqchip/irq-meson-gpio.c
+@@ -173,7 +173,7 @@ struct meson_gpio_irq_controller {
+ 	void __iomem *base;
+ 	u32 channel_irqs[MAX_NUM_CHANNEL];
+ 	DECLARE_BITMAP(channel_map, MAX_NUM_CHANNEL);
+-	spinlock_t lock;
++	raw_spinlock_t lock;
+ };
+ 
+ static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
+@@ -182,14 +182,14 @@ static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
+ 	unsigned long flags;
+ 	u32 tmp;
+ 
+-	spin_lock_irqsave(&ctl->lock, flags);
++	raw_spin_lock_irqsave(&ctl->lock, flags);
+ 
+ 	tmp = readl_relaxed(ctl->base + reg);
+ 	tmp &= ~mask;
+ 	tmp |= val;
+ 	writel_relaxed(tmp, ctl->base + reg);
+ 
+-	spin_unlock_irqrestore(&ctl->lock, flags);
++	raw_spin_unlock_irqrestore(&ctl->lock, flags);
+ }
+ 
+ static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl)
+@@ -239,12 +239,12 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
+ 	unsigned long flags;
+ 	unsigned int idx;
+ 
+-	spin_lock_irqsave(&ctl->lock, flags);
++	raw_spin_lock_irqsave(&ctl->lock, flags);
+ 
+ 	/* Find a free channel */
+ 	idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels);
+ 	if (idx >= ctl->params->nr_channels) {
+-		spin_unlock_irqrestore(&ctl->lock, flags);
++		raw_spin_unlock_irqrestore(&ctl->lock, flags);
+ 		pr_err("No channel available\n");
+ 		return -ENOSPC;
+ 	}
+@@ -252,7 +252,7 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
+ 	/* Mark the channel as used */
+ 	set_bit(idx, ctl->channel_map);
+ 
+-	spin_unlock_irqrestore(&ctl->lock, flags);
++	raw_spin_unlock_irqrestore(&ctl->lock, flags);
+ 
+ 	/*
+ 	 * Setup the mux of the channel to route the signal of the pad
+@@ -562,7 +562,7 @@ static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *
+ 	if (!ctl)
+ 		return -ENOMEM;
+ 
+-	spin_lock_init(&ctl->lock);
++	raw_spin_lock_init(&ctl->lock);
+ 
+ 	ctl->base = of_iomap(node, 0);
+ 	if (!ctl->base) {
+diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx-intc.c
+index 238d3d3449496..7e08714d507f4 100644
+--- a/drivers/irqchip/irq-xilinx-intc.c
++++ b/drivers/irqchip/irq-xilinx-intc.c
+@@ -189,7 +189,7 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
+ 		irqc->intr_mask = 0;
+ 	}
+ 
+-	if (irqc->intr_mask >> irqc->nr_irq)
++	if ((u64)irqc->intr_mask >> irqc->nr_irq)
+ 		pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
+ 
+ 	pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",
+diff --git a/drivers/md/md.c b/drivers/md/md.c
+index b5dea664f946d..35b003b83ef1b 100644
+--- a/drivers/md/md.c
++++ b/drivers/md/md.c
+@@ -456,7 +456,6 @@ void mddev_suspend(struct mddev *mddev)
+ 	clear_bit_unlock(MD_ALLOW_SB_UPDATE, &mddev->flags);
+ 	wait_event(mddev->sb_wait, !test_bit(MD_UPDATING_SB, &mddev->flags));
+ 
+-	del_timer_sync(&mddev->safemode_timer);
+ 	/* restrict memory reclaim I/O during raid array is suspend */
+ 	mddev->noio_flag = memalloc_noio_save();
+ }
+diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
+index 1507540a9cb4e..2c7f11e576673 100644
+--- a/drivers/md/raid5.c
++++ b/drivers/md/raid5.c
+@@ -6326,7 +6326,9 @@ static sector_t reshape_request(struct mddev *mddev, sector_t sector_nr, int *sk
+ 	safepos = conf->reshape_safe;
+ 	sector_div(safepos, data_disks);
+ 	if (mddev->reshape_backwards) {
+-		BUG_ON(writepos < reshape_sectors);
++		if (WARN_ON(writepos < reshape_sectors))
++			return MaxSector;
++
+ 		writepos -= reshape_sectors;
+ 		readpos += reshape_sectors;
+ 		safepos += reshape_sectors;
+@@ -6344,14 +6346,18 @@ static sector_t reshape_request(struct mddev *mddev, sector_t sector_nr, int *sk
+ 	 * to set 'stripe_addr' which is where we will write to.
+ 	 */
+ 	if (mddev->reshape_backwards) {
+-		BUG_ON(conf->reshape_progress == 0);
++		if (WARN_ON(conf->reshape_progress == 0))
++			return MaxSector;
++
+ 		stripe_addr = writepos;
+-		BUG_ON((mddev->dev_sectors &
+-			~((sector_t)reshape_sectors - 1))
+-		       - reshape_sectors - stripe_addr
+-		       != sector_nr);
++		if (WARN_ON((mddev->dev_sectors &
++		    ~((sector_t)reshape_sectors - 1)) -
++		    reshape_sectors - stripe_addr != sector_nr))
++			return MaxSector;
+ 	} else {
+-		BUG_ON(writepos != sector_nr + reshape_sectors);
++		if (WARN_ON(writepos != sector_nr + reshape_sectors))
++			return MaxSector;
++
+ 		stripe_addr = sector_nr;
+ 	}
+ 
+diff --git a/drivers/media/platform/amphion/vdec.c b/drivers/media/platform/amphion/vdec.c
+index 133d77d1ea0c3..4f438eaa7d385 100644
+--- a/drivers/media/platform/amphion/vdec.c
++++ b/drivers/media/platform/amphion/vdec.c
+@@ -195,7 +195,6 @@ static int vdec_op_s_ctrl(struct v4l2_ctrl *ctrl)
+ 	struct vdec_t *vdec = inst->priv;
+ 	int ret = 0;
+ 
+-	vpu_inst_lock(inst);
+ 	switch (ctrl->id) {
+ 	case V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE:
+ 		vdec->params.display_delay_enable = ctrl->val;
+@@ -207,7 +206,6 @@ static int vdec_op_s_ctrl(struct v4l2_ctrl *ctrl)
+ 		ret = -EINVAL;
+ 		break;
+ 	}
+-	vpu_inst_unlock(inst);
+ 
+ 	return ret;
+ }
+diff --git a/drivers/media/platform/amphion/venc.c b/drivers/media/platform/amphion/venc.c
+index 4eb57d793a9c0..16ed4d21519cd 100644
+--- a/drivers/media/platform/amphion/venc.c
++++ b/drivers/media/platform/amphion/venc.c
+@@ -518,7 +518,6 @@ static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl)
+ 	struct venc_t *venc = inst->priv;
+ 	int ret = 0;
+ 
+-	vpu_inst_lock(inst);
+ 	switch (ctrl->id) {
+ 	case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
+ 		venc->params.profile = ctrl->val;
+@@ -579,7 +578,6 @@ static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl)
+ 		ret = -EINVAL;
+ 		break;
+ 	}
+-	vpu_inst_unlock(inst);
+ 
+ 	return ret;
+ }
+diff --git a/drivers/media/tuners/xc2028.c b/drivers/media/tuners/xc2028.c
+index 5a967edceca93..352b8a3679b72 100644
+--- a/drivers/media/tuners/xc2028.c
++++ b/drivers/media/tuners/xc2028.c
+@@ -1361,9 +1361,16 @@ static void load_firmware_cb(const struct firmware *fw,
+ 			     void *context)
+ {
+ 	struct dvb_frontend *fe = context;
+-	struct xc2028_data *priv = fe->tuner_priv;
++	struct xc2028_data *priv;
+ 	int rc;
+ 
++	if (!fe) {
++		pr_warn("xc2028: No frontend in %s\n", __func__);
++		return;
++	}
++
++	priv = fe->tuner_priv;
++
+ 	tuner_dbg("request_firmware_nowait(): %s\n", fw ? "OK" : "error");
+ 	if (!fw) {
+ 		tuner_err("Could not load firmware %s.\n", priv->fname);
+diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c
+index 5eef560bc8cd8..91c350b254126 100644
+--- a/drivers/media/usb/uvc/uvc_video.c
++++ b/drivers/media/usb/uvc/uvc_video.c
+@@ -214,13 +214,13 @@ static void uvc_fixup_video_ctrl(struct uvc_streaming *stream,
+ 		 * Compute a bandwidth estimation by multiplying the frame
+ 		 * size by the number of video frames per second, divide the
+ 		 * result by the number of USB frames (or micro-frames for
+-		 * high-speed devices) per second and add the UVC header size
+-		 * (assumed to be 12 bytes long).
++		 * high- and super-speed devices) per second and add the UVC
++		 * header size (assumed to be 12 bytes long).
+ 		 */
+ 		bandwidth = frame->wWidth * frame->wHeight / 8 * format->bpp;
+ 		bandwidth *= 10000000 / interval + 1;
+ 		bandwidth /= 1000;
+-		if (stream->dev->udev->speed == USB_SPEED_HIGH)
++		if (stream->dev->udev->speed >= USB_SPEED_HIGH)
+ 			bandwidth /= 8;
+ 		bandwidth += 12;
+ 
+@@ -478,6 +478,7 @@ uvc_video_clock_decode(struct uvc_streaming *stream, struct uvc_buffer *buf,
+ 	ktime_t time;
+ 	u16 host_sof;
+ 	u16 dev_sof;
++	u32 dev_stc;
+ 
+ 	switch (data[1] & (UVC_STREAM_PTS | UVC_STREAM_SCR)) {
+ 	case UVC_STREAM_PTS | UVC_STREAM_SCR:
+@@ -526,6 +527,34 @@ uvc_video_clock_decode(struct uvc_streaming *stream, struct uvc_buffer *buf,
+ 	if (dev_sof == stream->clock.last_sof)
+ 		return;
+ 
++	dev_stc = get_unaligned_le32(&data[header_size - 6]);
++
++	/*
++	 * STC (Source Time Clock) is the clock used by the camera. The UVC 1.5
++	 * standard states that it "must be captured when the first video data
++	 * of a video frame is put on the USB bus". This is generally understood
++	 * as requiring devices to clear the payload header's SCR bit before
++	 * the first packet containing video data.
++	 *
++	 * Most vendors follow that interpretation, but some (namely SunplusIT
++	 * on some devices) always set the `UVC_STREAM_SCR` bit, fill the SCR
++	 * field with 0's,and expect that the driver only processes the SCR if
++	 * there is data in the packet.
++	 *
++	 * Ignore all the hardware timestamp information if we haven't received
++	 * any data for this frame yet, the packet contains no data, and both
++	 * STC and SOF are zero. This heuristics should be safe on compliant
++	 * devices. This should be safe with compliant devices, as in the very
++	 * unlikely case where a UVC 1.1 device would send timing information
++	 * only before the first packet containing data, and both STC and SOF
++	 * happen to be zero for a particular frame, we would only miss one
++	 * clock sample from many and the clock recovery algorithm wouldn't
++	 * suffer from this condition.
++	 */
++	if (buf && buf->bytesused == 0 && len == header_size &&
++	    dev_stc == 0 && dev_sof == 0)
++		return;
++
+ 	stream->clock.last_sof = dev_sof;
+ 
+ 	host_sof = usb_get_current_frame_number(stream->dev->udev);
+@@ -575,7 +604,7 @@ uvc_video_clock_decode(struct uvc_streaming *stream, struct uvc_buffer *buf,
+ 	spin_lock_irqsave(&stream->clock.lock, flags);
+ 
+ 	sample = &stream->clock.samples[stream->clock.head];
+-	sample->dev_stc = get_unaligned_le32(&data[header_size - 6]);
++	sample->dev_stc = dev_stc;
+ 	sample->dev_sof = dev_sof;
+ 	sample->host_sof = host_sof;
+ 	sample->host_time = time;
+diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c
+index bfe4caa0c99d4..4cb79a4f24612 100644
+--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c
++++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c
+@@ -485,6 +485,8 @@ int mcp251xfd_ring_alloc(struct mcp251xfd_priv *priv)
+ 		clear_bit(MCP251XFD_FLAGS_FD_MODE, priv->flags);
+ 	}
+ 
++	tx_ring->obj_num_shift_to_u8 = BITS_PER_TYPE(tx_ring->obj_num) -
++		ilog2(tx_ring->obj_num);
+ 	tx_ring->obj_size = tx_obj_size;
+ 
+ 	rem = priv->rx_obj_num;
+diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-tef.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-tef.c
+index e5bd57b65aafe..5b0c7890d4b44 100644
+--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-tef.c
++++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-tef.c
+@@ -2,7 +2,7 @@
+ //
+ // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
+ //
+-// Copyright (c) 2019, 2020, 2021 Pengutronix,
++// Copyright (c) 2019, 2020, 2021, 2023 Pengutronix,
+ //               Marc Kleine-Budde <kernel@pengutronix.de>
+ //
+ // Based on:
+@@ -16,6 +16,11 @@
+ 
+ #include "mcp251xfd.h"
+ 
++static inline bool mcp251xfd_tx_fifo_sta_full(u32 fifo_sta)
++{
++	return !(fifo_sta & MCP251XFD_REG_FIFOSTA_TFNRFNIF);
++}
++
+ static inline int
+ mcp251xfd_tef_tail_get_from_chip(const struct mcp251xfd_priv *priv,
+ 				 u8 *tef_tail)
+@@ -55,56 +60,39 @@ static int mcp251xfd_check_tef_tail(const struct mcp251xfd_priv *priv)
+ 	return 0;
+ }
+ 
+-static int
+-mcp251xfd_handle_tefif_recover(const struct mcp251xfd_priv *priv, const u32 seq)
+-{
+-	const struct mcp251xfd_tx_ring *tx_ring = priv->tx;
+-	u32 tef_sta;
+-	int err;
+-
+-	err = regmap_read(priv->map_reg, MCP251XFD_REG_TEFSTA, &tef_sta);
+-	if (err)
+-		return err;
+-
+-	if (tef_sta & MCP251XFD_REG_TEFSTA_TEFOVIF) {
+-		netdev_err(priv->ndev,
+-			   "Transmit Event FIFO buffer overflow.\n");
+-		return -ENOBUFS;
+-	}
+-
+-	netdev_info(priv->ndev,
+-		    "Transmit Event FIFO buffer %s. (seq=0x%08x, tef_tail=0x%08x, tef_head=0x%08x, tx_head=0x%08x).\n",
+-		    tef_sta & MCP251XFD_REG_TEFSTA_TEFFIF ?
+-		    "full" : tef_sta & MCP251XFD_REG_TEFSTA_TEFNEIF ?
+-		    "not empty" : "empty",
+-		    seq, priv->tef->tail, priv->tef->head, tx_ring->head);
+-
+-	/* The Sequence Number in the TEF doesn't match our tef_tail. */
+-	return -EAGAIN;
+-}
+-
+ static int
+ mcp251xfd_handle_tefif_one(struct mcp251xfd_priv *priv,
+ 			   const struct mcp251xfd_hw_tef_obj *hw_tef_obj,
+ 			   unsigned int *frame_len_ptr)
+ {
+ 	struct net_device_stats *stats = &priv->ndev->stats;
++	u32 seq, tef_tail_masked, tef_tail;
+ 	struct sk_buff *skb;
+-	u32 seq, seq_masked, tef_tail_masked, tef_tail;
+ 
+-	seq = FIELD_GET(MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK,
++	 /* Use the MCP2517FD mask on the MCP2518FD, too. We only
++	  * compare 7 bits, this is enough to detect old TEF objects.
++	  */
++	seq = FIELD_GET(MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK,
+ 			hw_tef_obj->flags);
+-
+-	/* Use the MCP2517FD mask on the MCP2518FD, too. We only
+-	 * compare 7 bits, this should be enough to detect
+-	 * net-yet-completed, i.e. old TEF objects.
+-	 */
+-	seq_masked = seq &
+-		field_mask(MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK);
+ 	tef_tail_masked = priv->tef->tail &
+ 		field_mask(MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK);
+-	if (seq_masked != tef_tail_masked)
+-		return mcp251xfd_handle_tefif_recover(priv, seq);
++
++	/* According to mcp2518fd erratum DS80000789E 6. the FIFOCI
++	 * bits of a FIFOSTA register, here the TX FIFO tail index
++	 * might be corrupted and we might process past the TEF FIFO's
++	 * head into old CAN frames.
++	 *
++	 * Compare the sequence number of the currently processed CAN
++	 * frame with the expected sequence number. Abort with
++	 * -EBADMSG if an old CAN frame is detected.
++	 */
++	if (seq != tef_tail_masked) {
++		netdev_dbg(priv->ndev, "%s: chip=0x%02x ring=0x%02x\n", __func__,
++			   seq, tef_tail_masked);
++		stats->tx_fifo_errors++;
++
++		return -EBADMSG;
++	}
+ 
+ 	tef_tail = mcp251xfd_get_tef_tail(priv);
+ 	skb = priv->can.echo_skb[tef_tail];
+@@ -120,28 +108,44 @@ mcp251xfd_handle_tefif_one(struct mcp251xfd_priv *priv,
+ 	return 0;
+ }
+ 
+-static int mcp251xfd_tef_ring_update(struct mcp251xfd_priv *priv)
++static int
++mcp251xfd_get_tef_len(struct mcp251xfd_priv *priv, u8 *len_p)
+ {
+ 	const struct mcp251xfd_tx_ring *tx_ring = priv->tx;
+-	unsigned int new_head;
+-	u8 chip_tx_tail;
++	const u8 shift = tx_ring->obj_num_shift_to_u8;
++	u8 chip_tx_tail, tail, len;
++	u32 fifo_sta;
+ 	int err;
+ 
+-	err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);
++	err = regmap_read(priv->map_reg, MCP251XFD_REG_FIFOSTA(priv->tx->fifo_nr),
++			  &fifo_sta);
+ 	if (err)
+ 		return err;
+ 
+-	/* chip_tx_tail, is the next TX-Object send by the HW.
+-	 * The new TEF head must be >= the old head, ...
++	if (mcp251xfd_tx_fifo_sta_full(fifo_sta)) {
++		*len_p = tx_ring->obj_num;
++		return 0;
++	}
++
++	chip_tx_tail = FIELD_GET(MCP251XFD_REG_FIFOSTA_FIFOCI_MASK, fifo_sta);
++
++	err =  mcp251xfd_check_tef_tail(priv);
++	if (err)
++		return err;
++	tail = mcp251xfd_get_tef_tail(priv);
++
++	/* First shift to full u8. The subtraction works on signed
++	 * values, that keeps the difference steady around the u8
++	 * overflow. The right shift acts on len, which is an u8.
+ 	 */
+-	new_head = round_down(priv->tef->head, tx_ring->obj_num) + chip_tx_tail;
+-	if (new_head <= priv->tef->head)
+-		new_head += tx_ring->obj_num;
++	BUILD_BUG_ON(sizeof(tx_ring->obj_num) != sizeof(chip_tx_tail));
++	BUILD_BUG_ON(sizeof(tx_ring->obj_num) != sizeof(tail));
++	BUILD_BUG_ON(sizeof(tx_ring->obj_num) != sizeof(len));
+ 
+-	/* ... but it cannot exceed the TX head. */
+-	priv->tef->head = min(new_head, tx_ring->head);
++	len = (chip_tx_tail << shift) - (tail << shift);
++	*len_p = len >> shift;
+ 
+-	return mcp251xfd_check_tef_tail(priv);
++	return 0;
+ }
+ 
+ static inline int
+@@ -182,13 +186,12 @@ int mcp251xfd_handle_tefif(struct mcp251xfd_priv *priv)
+ 	u8 tef_tail, len, l;
+ 	int err, i;
+ 
+-	err = mcp251xfd_tef_ring_update(priv);
++	err = mcp251xfd_get_tef_len(priv, &len);
+ 	if (err)
+ 		return err;
+ 
+ 	tef_tail = mcp251xfd_get_tef_tail(priv);
+-	len = mcp251xfd_get_tef_len(priv);
+-	l = mcp251xfd_get_tef_linear_len(priv);
++	l = mcp251xfd_get_tef_linear_len(priv, len);
+ 	err = mcp251xfd_tef_obj_read(priv, hw_tef_obj, tef_tail, l);
+ 	if (err)
+ 		return err;
+@@ -203,12 +206,12 @@ int mcp251xfd_handle_tefif(struct mcp251xfd_priv *priv)
+ 		unsigned int frame_len = 0;
+ 
+ 		err = mcp251xfd_handle_tefif_one(priv, &hw_tef_obj[i], &frame_len);
+-		/* -EAGAIN means the Sequence Number in the TEF
+-		 * doesn't match our tef_tail. This can happen if we
+-		 * read the TEF objects too early. Leave loop let the
+-		 * interrupt handler call us again.
++		/* -EBADMSG means we're affected by mcp2518fd erratum
++		 * DS80000789E 6., i.e. the Sequence Number in the TEF
++		 * doesn't match our tef_tail. Don't process any
++		 * further and mark processed frames as good.
+ 		 */
+-		if (err == -EAGAIN)
++		if (err == -EBADMSG)
+ 			goto out_netif_wake_queue;
+ 		if (err)
+ 			return err;
+@@ -223,6 +226,8 @@ int mcp251xfd_handle_tefif(struct mcp251xfd_priv *priv)
+ 		struct mcp251xfd_tx_ring *tx_ring = priv->tx;
+ 		int offset;
+ 
++		ring->head += len;
++
+ 		/* Increment the TEF FIFO tail pointer 'len' times in
+ 		 * a single SPI message.
+ 		 *
+diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h b/drivers/net/can/spi/mcp251xfd/mcp251xfd.h
+index b35bfebd23f29..4628bf847bc9b 100644
+--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h
++++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd.h
+@@ -524,6 +524,7 @@ struct mcp251xfd_tef_ring {
+ 
+ 	/* u8 obj_num equals tx_ring->obj_num */
+ 	/* u8 obj_size equals sizeof(struct mcp251xfd_hw_tef_obj) */
++	/* u8 obj_num_shift_to_u8 equals tx_ring->obj_num_shift_to_u8 */
+ 
+ 	union mcp251xfd_write_reg_buf irq_enable_buf;
+ 	struct spi_transfer irq_enable_xfer;
+@@ -542,6 +543,7 @@ struct mcp251xfd_tx_ring {
+ 	u8 nr;
+ 	u8 fifo_nr;
+ 	u8 obj_num;
++	u8 obj_num_shift_to_u8;
+ 	u8 obj_size;
+ 
+ 	struct mcp251xfd_tx_obj obj[MCP251XFD_TX_OBJ_NUM_MAX];
+@@ -861,17 +863,8 @@ static inline u8 mcp251xfd_get_tef_tail(const struct mcp251xfd_priv *priv)
+ 	return priv->tef->tail & (priv->tx->obj_num - 1);
+ }
+ 
+-static inline u8 mcp251xfd_get_tef_len(const struct mcp251xfd_priv *priv)
++static inline u8 mcp251xfd_get_tef_linear_len(const struct mcp251xfd_priv *priv, u8 len)
+ {
+-	return priv->tef->head - priv->tef->tail;
+-}
+-
+-static inline u8 mcp251xfd_get_tef_linear_len(const struct mcp251xfd_priv *priv)
+-{
+-	u8 len;
+-
+-	len = mcp251xfd_get_tef_len(priv);
+-
+ 	return min_t(u8, len, priv->tx->obj_num - mcp251xfd_get_tef_tail(priv));
+ }
+ 
+diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
+index cd1f240c90f39..257df16768750 100644
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -678,8 +678,10 @@ static int bcm_sf2_mdio_register(struct dsa_switch *ds)
+ 			of_remove_property(child, prop);
+ 
+ 		phydev = of_phy_find_device(child);
+-		if (phydev)
++		if (phydev) {
+ 			phy_device_remove(phydev);
++			phy_device_free(phydev);
++		}
+ 	}
+ 
+ 	err = mdiobus_register(priv->slave_mii_bus);
+diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c b/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c
+index 1248792d7fd4d..0715ea5bf13ed 100644
+--- a/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c
++++ b/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c
+@@ -42,19 +42,15 @@ void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+ 	struct bcmgenet_priv *priv = netdev_priv(dev);
+ 	struct device *kdev = &priv->pdev->dev;
+ 
+-	if (dev->phydev) {
++	if (dev->phydev)
+ 		phy_ethtool_get_wol(dev->phydev, wol);
+-		if (wol->supported)
+-			return;
+-	}
+ 
+-	if (!device_can_wakeup(kdev)) {
+-		wol->supported = 0;
+-		wol->wolopts = 0;
++	/* MAC is not wake-up capable, return what the PHY does */
++	if (!device_can_wakeup(kdev))
+ 		return;
+-	}
+ 
+-	wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_FILTER;
++	/* Overlay MAC capabilities with that of the PHY queried before */
++	wol->supported |= WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_FILTER;
+ 	wol->wolopts = priv->wolopts;
+ 	memset(wol->sopass, 0, sizeof(wol->sopass));
+ 
+diff --git a/drivers/net/ethernet/freescale/fec_ptp.c b/drivers/net/ethernet/freescale/fec_ptp.c
+index e32f6724f5681..2e4f3e1782a25 100644
+--- a/drivers/net/ethernet/freescale/fec_ptp.c
++++ b/drivers/net/ethernet/freescale/fec_ptp.c
+@@ -775,6 +775,9 @@ void fec_ptp_stop(struct platform_device *pdev)
+ 	struct net_device *ndev = platform_get_drvdata(pdev);
+ 	struct fec_enet_private *fep = netdev_priv(ndev);
+ 
++	if (fep->pps_enable)
++		fec_ptp_enable_pps(fep, 0);
++
+ 	cancel_delayed_work_sync(&fep->time_keep);
+ 	hrtimer_cancel(&fep->perout_timer);
+ 	if (fep->ptp_clock)
+diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c
+index 600a2f5370875..b168a37a5dfff 100644
+--- a/drivers/net/ethernet/intel/ice/ice_main.c
++++ b/drivers/net/ethernet/intel/ice/ice_main.c
+@@ -557,6 +557,8 @@ ice_prepare_for_reset(struct ice_pf *pf, enum ice_reset_req reset_type)
+ 	if (test_bit(ICE_PREPARED_FOR_RESET, pf->state))
+ 		return;
+ 
++	synchronize_irq(pf->oicr_irq.virq);
++
+ 	ice_unplug_aux_dev(pf);
+ 
+ 	/* Notify VFs of impending reset */
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
+index 8d9743a5e42c7..79ec6fcc9e259 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
+@@ -2374,6 +2374,9 @@ static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct mlx5e_rq *rq, struct mlx5_cq
+ 	if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
+ 		return;
+ 
++	if (unlikely(!cstrides))
++		return;
++
+ 	wq  = &rq->mpwqe.wq;
+ 	wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
+ 	mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+index d5d2a4c776c1c..ded1bbda5266f 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+@@ -21,6 +21,7 @@
+ #define RGMII_IO_MACRO_CONFIG2		0x1C
+ #define RGMII_IO_MACRO_DEBUG1		0x20
+ #define EMAC_SYSTEM_LOW_POWER_DEBUG	0x28
++#define EMAC_WRAPPER_SGMII_PHY_CNTRL1	0xf4
+ 
+ /* RGMII_IO_MACRO_CONFIG fields */
+ #define RGMII_CONFIG_FUNC_CLK_EN		BIT(30)
+@@ -79,6 +80,9 @@
+ #define ETHQOS_MAC_CTRL_SPEED_MODE		BIT(14)
+ #define ETHQOS_MAC_CTRL_PORT_SEL		BIT(15)
+ 
++/* EMAC_WRAPPER_SGMII_PHY_CNTRL1 bits */
++#define SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN	BIT(3)
++
+ #define SGMII_10M_RX_CLK_DVDR			0x31
+ 
+ struct ethqos_emac_por {
+@@ -95,6 +99,7 @@ struct ethqos_emac_driver_data {
+ 	bool has_integrated_pcs;
+ 	u32 dma_addr_width;
+ 	struct dwmac4_addrs dwmac4_addrs;
++	bool needs_sgmii_loopback;
+ };
+ 
+ struct qcom_ethqos {
+@@ -113,6 +118,7 @@ struct qcom_ethqos {
+ 	unsigned int num_por;
+ 	bool rgmii_config_loopback_en;
+ 	bool has_emac_ge_3;
++	bool needs_sgmii_loopback;
+ };
+ 
+ static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
+@@ -187,8 +193,22 @@ ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed)
+ 	clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
+ }
+ 
++static void
++qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable)
++{
++	if (!ethqos->needs_sgmii_loopback ||
++	    ethqos->phy_mode != PHY_INTERFACE_MODE_2500BASEX)
++		return;
++
++	rgmii_updatel(ethqos,
++		      SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN,
++		      enable ? SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN : 0,
++		      EMAC_WRAPPER_SGMII_PHY_CNTRL1);
++}
++
+ static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
+ {
++	qcom_ethqos_set_sgmii_loopback(ethqos, true);
+ 	rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
+ 		      RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
+ }
+@@ -273,6 +293,7 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = {
+ 	.has_emac_ge_3 = true,
+ 	.link_clk_name = "phyaux",
+ 	.has_integrated_pcs = true,
++	.needs_sgmii_loopback = true,
+ 	.dma_addr_width = 36,
+ 	.dwmac4_addrs = {
+ 		.dma_chan = 0x00008100,
+@@ -646,6 +667,7 @@ static void ethqos_fix_mac_speed(void *priv, unsigned int speed, unsigned int mo
+ {
+ 	struct qcom_ethqos *ethqos = priv;
+ 
++	qcom_ethqos_set_sgmii_loopback(ethqos, false);
+ 	ethqos->speed = speed;
+ 	ethqos_update_link_clk(ethqos, speed);
+ 	ethqos_configure(ethqos);
+@@ -781,6 +803,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
+ 	ethqos->num_por = data->num_por;
+ 	ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
+ 	ethqos->has_emac_ge_3 = data->has_emac_ge_3;
++	ethqos->needs_sgmii_loopback = data->needs_sgmii_loopback;
+ 
+ 	ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
+ 	if (IS_ERR(ethqos->link_clk))
+diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
+index befbca01bfe37..b1380cf1b13ab 100644
+--- a/drivers/net/usb/qmi_wwan.c
++++ b/drivers/net/usb/qmi_wwan.c
+@@ -201,6 +201,7 @@ static int qmimux_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
+ 			break;
+ 		default:
+ 			/* not ip - do not know what to do */
++			kfree_skb(skbn);
+ 			goto skip;
+ 		}
+ 
+diff --git a/drivers/net/wireless/ath/ath12k/core.h b/drivers/net/wireless/ath/ath12k/core.h
+index c926952c956ef..33f4706af880d 100644
+--- a/drivers/net/wireless/ath/ath12k/core.h
++++ b/drivers/net/wireless/ath/ath12k/core.h
+@@ -181,6 +181,8 @@ enum ath12k_dev_flags {
+ 	ATH12K_FLAG_REGISTERED,
+ 	ATH12K_FLAG_QMI_FAIL,
+ 	ATH12K_FLAG_HTC_SUSPEND_COMPLETE,
++	ATH12K_FLAG_CE_IRQ_ENABLED,
++	ATH12K_FLAG_EXT_IRQ_ENABLED,
+ };
+ 
+ enum ath12k_monitor_flags {
+diff --git a/drivers/net/wireless/ath/ath12k/dp_rx.c b/drivers/net/wireless/ath/ath12k/dp_rx.c
+index 2c17b1e7681a5..d9bc07844fb71 100644
+--- a/drivers/net/wireless/ath/ath12k/dp_rx.c
++++ b/drivers/net/wireless/ath/ath12k/dp_rx.c
+@@ -2759,6 +2759,7 @@ int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev
+ 	peer = ath12k_peer_find(ab, vdev_id, peer_mac);
+ 	if (!peer) {
+ 		spin_unlock_bh(&ab->base_lock);
++		crypto_free_shash(tfm);
+ 		ath12k_warn(ab, "failed to find the peer to set up fragment info\n");
+ 		return -ENOENT;
+ 	}
+diff --git a/drivers/net/wireless/ath/ath12k/hif.h b/drivers/net/wireless/ath/ath12k/hif.h
+index 4cbf9b5c04b9c..c653ca1f59b22 100644
+--- a/drivers/net/wireless/ath/ath12k/hif.h
++++ b/drivers/net/wireless/ath/ath12k/hif.h
+@@ -10,17 +10,17 @@
+ #include "core.h"
+ 
+ struct ath12k_hif_ops {
+-	u32 (*read32)(struct ath12k_base *sc, u32 address);
+-	void (*write32)(struct ath12k_base *sc, u32 address, u32 data);
+-	void (*irq_enable)(struct ath12k_base *sc);
+-	void (*irq_disable)(struct ath12k_base *sc);
+-	int (*start)(struct ath12k_base *sc);
+-	void (*stop)(struct ath12k_base *sc);
+-	int (*power_up)(struct ath12k_base *sc);
+-	void (*power_down)(struct ath12k_base *sc);
++	u32 (*read32)(struct ath12k_base *ab, u32 address);
++	void (*write32)(struct ath12k_base *ab, u32 address, u32 data);
++	void (*irq_enable)(struct ath12k_base *ab);
++	void (*irq_disable)(struct ath12k_base *ab);
++	int (*start)(struct ath12k_base *ab);
++	void (*stop)(struct ath12k_base *ab);
++	int (*power_up)(struct ath12k_base *ab);
++	void (*power_down)(struct ath12k_base *ab);
+ 	int (*suspend)(struct ath12k_base *ab);
+ 	int (*resume)(struct ath12k_base *ab);
+-	int (*map_service_to_pipe)(struct ath12k_base *sc, u16 service_id,
++	int (*map_service_to_pipe)(struct ath12k_base *ab, u16 service_id,
+ 				   u8 *ul_pipe, u8 *dl_pipe);
+ 	int (*get_user_msi_vector)(struct ath12k_base *ab, char *user_name,
+ 				   int *num_vectors, u32 *user_base_data,
+diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c
+index 58cd678555964..041a9602f0e15 100644
+--- a/drivers/net/wireless/ath/ath12k/pci.c
++++ b/drivers/net/wireless/ath/ath12k/pci.c
+@@ -373,6 +373,8 @@ static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab)
+ {
+ 	int i;
+ 
++	clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
++
+ 	for (i = 0; i < ab->hw_params->ce_count; i++) {
+ 		if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
+ 			continue;
+@@ -406,6 +408,10 @@ static void ath12k_pci_ce_tasklet(struct tasklet_struct *t)
+ static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg)
+ {
+ 	struct ath12k_ce_pipe *ce_pipe = arg;
++	struct ath12k_base *ab = ce_pipe->ab;
++
++	if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))
++		return IRQ_HANDLED;
+ 
+ 	/* last interrupt received for this CE */
+ 	ce_pipe->timestamp = jiffies;
+@@ -424,12 +430,15 @@ static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp)
+ 		disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
+ }
+ 
+-static void __ath12k_pci_ext_irq_disable(struct ath12k_base *sc)
++static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab)
+ {
+ 	int i;
+ 
++	if (!test_and_clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
++		return;
++
+ 	for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
+-		struct ath12k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
++		struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
+ 
+ 		ath12k_pci_ext_grp_disable(irq_grp);
+ 
+@@ -483,6 +492,10 @@ static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)
+ static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg)
+ {
+ 	struct ath12k_ext_irq_grp *irq_grp = arg;
++	struct ath12k_base *ab = irq_grp->ab;
++
++	if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
++		return IRQ_HANDLED;
+ 
+ 	ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq);
+ 
+@@ -626,6 +639,8 @@ static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab)
+ {
+ 	int i;
+ 
++	set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
++
+ 	for (i = 0; i < ab->hw_params->ce_count; i++) {
+ 		if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
+ 			continue;
+@@ -956,6 +971,8 @@ void ath12k_pci_ext_irq_enable(struct ath12k_base *ab)
+ {
+ 	int i;
+ 
++	set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
++
+ 	for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
+ 		struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
+ 
+diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
+index 796c2a00fea4a..0fc7aa78b2e5b 100644
+--- a/drivers/nvme/host/pci.c
++++ b/drivers/nvme/host/pci.c
+@@ -826,9 +826,9 @@ static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
+ 		struct nvme_command *cmnd)
+ {
+ 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
++	struct bio_vec bv = rq_integrity_vec(req);
+ 
+-	iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
+-			rq_dma_dir(req), 0);
++	iod->meta_dma = dma_map_bvec(dev->dev, &bv, rq_dma_dir(req), 0);
+ 	if (dma_mapping_error(dev->dev, iod->meta_dma))
+ 		return BLK_STS_IOERR;
+ 	cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
+@@ -969,7 +969,7 @@ static __always_inline void nvme_pci_unmap_rq(struct request *req)
+ 	        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
+ 
+ 		dma_unmap_page(dev->dev, iod->meta_dma,
+-			       rq_integrity_vec(req)->bv_len, rq_dma_dir(req));
++			       rq_integrity_vec(req).bv_len, rq_dma_dir(req));
+ 	}
+ 
+ 	if (blk_rq_nr_phys_segments(req))
+diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
+index 306f886b52d20..4ff2aa4b484bc 100644
+--- a/drivers/platform/x86/intel/ifs/core.c
++++ b/drivers/platform/x86/intel/ifs/core.c
+@@ -1,6 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /* Copyright(c) 2022 Intel Corporation. */
+ 
++#include <linux/bitfield.h>
+ #include <linux/module.h>
+ #include <linux/kdev_t.h>
+ #include <linux/semaphore.h>
+@@ -94,6 +95,8 @@ static int __init ifs_init(void)
+ 	for (i = 0; i < IFS_NUMTESTS; i++) {
+ 		if (!(msrval & BIT(ifs_devices[i].test_caps->integrity_cap_bit)))
+ 			continue;
++		ifs_devices[i].rw_data.generation = FIELD_GET(MSR_INTEGRITY_CAPS_SAF_GEN_MASK,
++							      msrval);
+ 		ret = misc_register(&ifs_devices[i].misc);
+ 		if (ret)
+ 			goto err_exit;
+diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
+index 93191855890f2..6bc63ab705175 100644
+--- a/drivers/platform/x86/intel/ifs/ifs.h
++++ b/drivers/platform/x86/intel/ifs/ifs.h
+@@ -174,9 +174,17 @@ union ifs_chunks_auth_status {
+ union ifs_scan {
+ 	u64	data;
+ 	struct {
+-		u32	start	:8;
+-		u32	stop	:8;
+-		u32	rsvd	:16;
++		union {
++			struct {
++				u8	start;
++				u8	stop;
++				u16	rsvd;
++			} gen0;
++			struct {
++				u16	start;
++				u16	stop;
++			} gen2;
++		};
+ 		u32	delay	:31;
+ 		u32	sigmce	:1;
+ 	};
+@@ -186,9 +194,17 @@ union ifs_scan {
+ union ifs_status {
+ 	u64	data;
+ 	struct {
+-		u32	chunk_num		:8;
+-		u32	chunk_stop_index	:8;
+-		u32	rsvd1			:16;
++		union {
++			struct {
++				u8	chunk_num;
++				u8	chunk_stop_index;
++				u16	rsvd1;
++			} gen0;
++			struct {
++				u16	chunk_num;
++				u16	chunk_stop_index;
++			} gen2;
++		};
+ 		u32	error_code		:8;
+ 		u32	rsvd2			:22;
+ 		u32	control_error		:1;
+@@ -229,6 +245,7 @@ struct ifs_test_caps {
+  * @status: it holds simple status pass/fail/untested
+  * @scan_details: opaque scan status code from h/w
+  * @cur_batch: number indicating the currently loaded test file
++ * @generation: IFS test generation enumerated by hardware
+  */
+ struct ifs_data {
+ 	int	loaded_version;
+@@ -238,6 +255,7 @@ struct ifs_data {
+ 	int	status;
+ 	u64	scan_details;
+ 	u32	cur_batch;
++	u32	generation;
+ };
+ 
+ struct ifs_work {
+diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
+index 43c864add778f..c7a5bf24bef35 100644
+--- a/drivers/platform/x86/intel/ifs/runtest.c
++++ b/drivers/platform/x86/intel/ifs/runtest.c
+@@ -167,25 +167,35 @@ static int doscan(void *data)
+  */
+ static void ifs_test_core(int cpu, struct device *dev)
+ {
++	union ifs_status status = {};
+ 	union ifs_scan activate;
+-	union ifs_status status;
+ 	unsigned long timeout;
+ 	struct ifs_data *ifsd;
++	int to_start, to_stop;
++	int status_chunk;
+ 	u64 msrvals[2];
+ 	int retries;
+ 
+ 	ifsd = ifs_get_data(dev);
+ 
+-	activate.rsvd = 0;
++	activate.gen0.rsvd = 0;
+ 	activate.delay = IFS_THREAD_WAIT;
+ 	activate.sigmce = 0;
+-	activate.start = 0;
+-	activate.stop = ifsd->valid_chunks - 1;
++	to_start = 0;
++	to_stop = ifsd->valid_chunks - 1;
++
++	if (ifsd->generation) {
++		activate.gen2.start = to_start;
++		activate.gen2.stop = to_stop;
++	} else {
++		activate.gen0.start = to_start;
++		activate.gen0.stop = to_stop;
++	}
+ 
+ 	timeout = jiffies + HZ / 2;
+ 	retries = MAX_IFS_RETRIES;
+ 
+-	while (activate.start <= activate.stop) {
++	while (to_start <= to_stop) {
+ 		if (time_after(jiffies, timeout)) {
+ 			status.error_code = IFS_SW_TIMEOUT;
+ 			break;
+@@ -196,13 +206,14 @@ static void ifs_test_core(int cpu, struct device *dev)
+ 
+ 		status.data = msrvals[1];
+ 
+-		trace_ifs_status(cpu, activate, status);
++		trace_ifs_status(cpu, to_start, to_stop, status.data);
+ 
+ 		/* Some cases can be retried, give up for others */
+ 		if (!can_restart(status))
+ 			break;
+ 
+-		if (status.chunk_num == activate.start) {
++		status_chunk = ifsd->generation ? status.gen2.chunk_num : status.gen0.chunk_num;
++		if (status_chunk == to_start) {
+ 			/* Check for forward progress */
+ 			if (--retries == 0) {
+ 				if (status.error_code == IFS_NO_ERROR)
+@@ -211,7 +222,11 @@ static void ifs_test_core(int cpu, struct device *dev)
+ 			}
+ 		} else {
+ 			retries = MAX_IFS_RETRIES;
+-			activate.start = status.chunk_num;
++			if (ifsd->generation)
++				activate.gen2.start = status_chunk;
++			else
++				activate.gen0.start = status_chunk;
++			to_start = status_chunk;
+ 		}
+ 	}
+ 
+diff --git a/drivers/power/supply/axp288_charger.c b/drivers/power/supply/axp288_charger.c
+index b5903193e2f96..ac05942e4e6ac 100644
+--- a/drivers/power/supply/axp288_charger.c
++++ b/drivers/power/supply/axp288_charger.c
+@@ -178,18 +178,18 @@ static inline int axp288_charger_set_cv(struct axp288_chrg_info *info, int cv)
+ 	u8 reg_val;
+ 	int ret;
+ 
+-	if (cv <= CV_4100MV) {
+-		reg_val = CHRG_CCCV_CV_4100MV;
+-		cv = CV_4100MV;
+-	} else if (cv <= CV_4150MV) {
+-		reg_val = CHRG_CCCV_CV_4150MV;
+-		cv = CV_4150MV;
+-	} else if (cv <= CV_4200MV) {
++	if (cv >= CV_4350MV) {
++		reg_val = CHRG_CCCV_CV_4350MV;
++		cv = CV_4350MV;
++	} else if (cv >= CV_4200MV) {
+ 		reg_val = CHRG_CCCV_CV_4200MV;
+ 		cv = CV_4200MV;
++	} else if (cv >= CV_4150MV) {
++		reg_val = CHRG_CCCV_CV_4150MV;
++		cv = CV_4150MV;
+ 	} else {
+-		reg_val = CHRG_CCCV_CV_4350MV;
+-		cv = CV_4350MV;
++		reg_val = CHRG_CCCV_CV_4100MV;
++		cv = CV_4100MV;
+ 	}
+ 
+ 	reg_val = reg_val << CHRG_CCCV_CV_BIT_POS;
+@@ -337,8 +337,8 @@ static int axp288_charger_usb_set_property(struct power_supply *psy,
+ 		}
+ 		break;
+ 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
+-		scaled_val = min(val->intval, info->max_cv);
+-		scaled_val = DIV_ROUND_CLOSEST(scaled_val, 1000);
++		scaled_val = DIV_ROUND_CLOSEST(val->intval, 1000);
++		scaled_val = min(scaled_val, info->max_cv);
+ 		ret = axp288_charger_set_cv(info, scaled_val);
+ 		if (ret < 0) {
+ 			dev_warn(&info->pdev->dev, "set charge voltage failed\n");
+diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qcom_battmgr.c
+index ec163d1bcd189..44c6301f5f174 100644
+--- a/drivers/power/supply/qcom_battmgr.c
++++ b/drivers/power/supply/qcom_battmgr.c
+@@ -486,7 +486,7 @@ static int qcom_battmgr_bat_get_property(struct power_supply *psy,
+ 	int ret;
+ 
+ 	if (!battmgr->service_up)
+-		return -ENODEV;
++		return -EAGAIN;
+ 
+ 	if (battmgr->variant == QCOM_BATTMGR_SC8280XP)
+ 		ret = qcom_battmgr_bat_sc8280xp_update(battmgr, psp);
+@@ -683,7 +683,7 @@ static int qcom_battmgr_ac_get_property(struct power_supply *psy,
+ 	int ret;
+ 
+ 	if (!battmgr->service_up)
+-		return -ENODEV;
++		return -EAGAIN;
+ 
+ 	ret = qcom_battmgr_bat_sc8280xp_update(battmgr, psp);
+ 	if (ret)
+@@ -748,7 +748,7 @@ static int qcom_battmgr_usb_get_property(struct power_supply *psy,
+ 	int ret;
+ 
+ 	if (!battmgr->service_up)
+-		return -ENODEV;
++		return -EAGAIN;
+ 
+ 	if (battmgr->variant == QCOM_BATTMGR_SC8280XP)
+ 		ret = qcom_battmgr_bat_sc8280xp_update(battmgr, psp);
+@@ -867,7 +867,7 @@ static int qcom_battmgr_wls_get_property(struct power_supply *psy,
+ 	int ret;
+ 
+ 	if (!battmgr->service_up)
+-		return -ENODEV;
++		return -EAGAIN;
+ 
+ 	if (battmgr->variant == QCOM_BATTMGR_SC8280XP)
+ 		ret = qcom_battmgr_bat_sc8280xp_update(battmgr, psp);
+diff --git a/drivers/s390/char/sclp_sd.c b/drivers/s390/char/sclp_sd.c
+index f9e164be7568f..944e75beb160c 100644
+--- a/drivers/s390/char/sclp_sd.c
++++ b/drivers/s390/char/sclp_sd.c
+@@ -320,8 +320,14 @@ static int sclp_sd_store_data(struct sclp_sd_data *result, u8 di)
+ 			  &esize);
+ 	if (rc) {
+ 		/* Cancel running request if interrupted */
+-		if (rc == -ERESTARTSYS)
+-			sclp_sd_sync(page, SD_EQ_HALT, di, 0, 0, NULL, NULL);
++		if (rc == -ERESTARTSYS) {
++			if (sclp_sd_sync(page, SD_EQ_HALT, di, 0, 0, NULL, NULL)) {
++				pr_warn("Could not stop Store Data request - leaking at least %zu bytes\n",
++					(size_t)dsize * PAGE_SIZE);
++				data = NULL;
++				asce = 0;
++			}
++		}
+ 		vfree(data);
+ 		goto out;
+ 	}
+diff --git a/drivers/scsi/mpi3mr/mpi3mr_os.c b/drivers/scsi/mpi3mr/mpi3mr_os.c
+index 80d71041086e1..7f32619234696 100644
+--- a/drivers/scsi/mpi3mr/mpi3mr_os.c
++++ b/drivers/scsi/mpi3mr/mpi3mr_os.c
+@@ -3447,6 +3447,17 @@ static int mpi3mr_prepare_sg_scmd(struct mpi3mr_ioc *mrioc,
+ 		    scmd->sc_data_direction);
+ 		priv->meta_sg_valid = 1; /* To unmap meta sg DMA */
+ 	} else {
++		/*
++		 * Some firmware versions byte-swap the REPORT ZONES command
++		 * reply from ATA-ZAC devices by directly accessing in the host
++		 * buffer. This does not respect the default command DMA
++		 * direction and causes IOMMU page faults on some architectures
++		 * with an IOMMU enforcing write mappings (e.g. AMD hosts).
++		 * Avoid such issue by making the REPORT ZONES buffer mapping
++		 * bi-directional.
++		 */
++		if (scmd->cmnd[0] == ZBC_IN && scmd->cmnd[1] == ZI_REPORT_ZONES)
++			scmd->sc_data_direction = DMA_BIDIRECTIONAL;
+ 		sg_scmd = scsi_sglist(scmd);
+ 		sges_left = scsi_dma_map(scmd);
+ 	}
+diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
+index 04116e02ffe8c..8acf586dc8b2e 100644
+--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
++++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
+@@ -2671,6 +2671,22 @@ _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
+ 	_base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
+ }
+ 
++static inline int _base_scsi_dma_map(struct scsi_cmnd *cmd)
++{
++	/*
++	 * Some firmware versions byte-swap the REPORT ZONES command reply from
++	 * ATA-ZAC devices by directly accessing in the host buffer. This does
++	 * not respect the default command DMA direction and causes IOMMU page
++	 * faults on some architectures with an IOMMU enforcing write mappings
++	 * (e.g. AMD hosts). Avoid such issue by making the report zones buffer
++	 * mapping bi-directional.
++	 */
++	if (cmd->cmnd[0] == ZBC_IN && cmd->cmnd[1] == ZI_REPORT_ZONES)
++		cmd->sc_data_direction = DMA_BIDIRECTIONAL;
++
++	return scsi_dma_map(cmd);
++}
++
+ /**
+  * _base_build_sg_scmd - main sg creation routine
+  *		pcie_device is unused here!
+@@ -2717,7 +2733,7 @@ _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
+ 	sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
+ 
+ 	sg_scmd = scsi_sglist(scmd);
+-	sges_left = scsi_dma_map(scmd);
++	sges_left = _base_scsi_dma_map(scmd);
+ 	if (sges_left < 0)
+ 		return -ENOMEM;
+ 
+@@ -2861,7 +2877,7 @@ _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
+ 	}
+ 
+ 	sg_scmd = scsi_sglist(scmd);
+-	sges_left = scsi_dma_map(scmd);
++	sges_left = _base_scsi_dma_map(scmd);
+ 	if (sges_left < 0)
+ 		return -ENOMEM;
+ 
+diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
+index 079035db7dd85..3c0f7dc9614d1 100644
+--- a/drivers/spi/spi-fsl-lpspi.c
++++ b/drivers/spi/spi-fsl-lpspi.c
+@@ -296,7 +296,7 @@ static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
+ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
+ {
+ 	struct lpspi_config config = fsl_lpspi->config;
+-	unsigned int perclk_rate, scldiv;
++	unsigned int perclk_rate, scldiv, div;
+ 	u8 prescale;
+ 
+ 	perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
+@@ -313,8 +313,10 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
+ 		return -EINVAL;
+ 	}
+ 
++	div = DIV_ROUND_UP(perclk_rate, config.speed_hz);
++
+ 	for (prescale = 0; prescale < 8; prescale++) {
+-		scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2;
++		scldiv = div / (1 << prescale) - 2;
+ 		if (scldiv < 256) {
+ 			fsl_lpspi->config.prescale = prescale;
+ 			break;
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index 1a8dd10012448..b97206d47ec6d 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -704,6 +704,7 @@ static const struct file_operations spidev_fops = {
+ static struct class *spidev_class;
+ 
+ static const struct spi_device_id spidev_spi_ids[] = {
++	{ .name = "bh2228fv" },
+ 	{ .name = "dh2228fv" },
+ 	{ .name = "ltc2488" },
+ 	{ .name = "sx1301" },
+diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
+index 2eceef54e0b30..ed8798fdf522a 100644
+--- a/drivers/tty/serial/serial_core.c
++++ b/drivers/tty/serial/serial_core.c
+@@ -876,6 +876,14 @@ static int uart_set_info(struct tty_struct *tty, struct tty_port *port,
+ 	new_flags = (__force upf_t)new_info->flags;
+ 	old_custom_divisor = uport->custom_divisor;
+ 
++	if (!(uport->flags & UPF_FIXED_PORT)) {
++		unsigned int uartclk = new_info->baud_base * 16;
++		/* check needs to be done here before other settings made */
++		if (uartclk == 0) {
++			retval = -EINVAL;
++			goto exit;
++		}
++	}
+ 	if (!capable(CAP_SYS_ADMIN)) {
+ 		retval = -EPERM;
+ 		if (change_irq || change_port ||
+diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
+index 808979a093505..94edac17b95f8 100644
+--- a/drivers/ufs/core/ufshcd.c
++++ b/drivers/ufs/core/ufshcd.c
+@@ -3971,11 +3971,16 @@ static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
+ 			min_sleep_time_us =
+ 				MIN_DELAY_BEFORE_DME_CMDS_US - delta;
+ 		else
+-			return; /* no more delay required */
++			min_sleep_time_us = 0; /* no more delay required */
+ 	}
+ 
+-	/* allow sleep for extra 50us if needed */
+-	usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
++	if (min_sleep_time_us > 0) {
++		/* allow sleep for extra 50us if needed */
++		usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
++	}
++
++	/* update the last_dme_cmd_tstamp */
++	hba->last_dme_cmd_tstamp = ktime_get();
+ }
+ 
+ /**
+@@ -10157,9 +10162,6 @@ int ufshcd_system_restore(struct device *dev)
+ 	 */
+ 	ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H);
+ 
+-	/* Resuming from hibernate, assume that link was OFF */
+-	ufshcd_set_link_off(hba);
+-
+ 	return 0;
+ 
+ }
+diff --git a/drivers/usb/gadget/function/f_midi2.c b/drivers/usb/gadget/function/f_midi2.c
+index 0e38bb145e8f5..6908fdd4a83f3 100644
+--- a/drivers/usb/gadget/function/f_midi2.c
++++ b/drivers/usb/gadget/function/f_midi2.c
+@@ -642,12 +642,21 @@ static void process_ump_stream_msg(struct f_midi2_ep *ep, const u32 *data)
+ 		if (format)
+ 			return; // invalid
+ 		blk = (*data >> 8) & 0xff;
+-		if (blk >= ep->num_blks)
+-			return;
+-		if (*data & UMP_STREAM_MSG_REQUEST_FB_INFO)
+-			reply_ump_stream_fb_info(ep, blk);
+-		if (*data & UMP_STREAM_MSG_REQUEST_FB_NAME)
+-			reply_ump_stream_fb_name(ep, blk);
++		if (blk == 0xff) {
++			/* inquiry for all blocks */
++			for (blk = 0; blk < ep->num_blks; blk++) {
++				if (*data & UMP_STREAM_MSG_REQUEST_FB_INFO)
++					reply_ump_stream_fb_info(ep, blk);
++				if (*data & UMP_STREAM_MSG_REQUEST_FB_NAME)
++					reply_ump_stream_fb_name(ep, blk);
++			}
++		} else if (blk < ep->num_blks) {
++			/* only the specified block */
++			if (*data & UMP_STREAM_MSG_REQUEST_FB_INFO)
++				reply_ump_stream_fb_info(ep, blk);
++			if (*data & UMP_STREAM_MSG_REQUEST_FB_NAME)
++				reply_ump_stream_fb_name(ep, blk);
++		}
+ 		return;
+ 	}
+ }
+diff --git a/drivers/usb/gadget/function/u_audio.c b/drivers/usb/gadget/function/u_audio.c
+index ec1dceb087293..0be0966973c7f 100644
+--- a/drivers/usb/gadget/function/u_audio.c
++++ b/drivers/usb/gadget/function/u_audio.c
+@@ -592,16 +592,25 @@ int u_audio_start_capture(struct g_audio *audio_dev)
+ 	struct usb_ep *ep, *ep_fback;
+ 	struct uac_rtd_params *prm;
+ 	struct uac_params *params = &audio_dev->params;
+-	int req_len, i;
++	int req_len, i, ret;
+ 
+ 	prm = &uac->c_prm;
+ 	dev_dbg(dev, "start capture with rate %d\n", prm->srate);
+ 	ep = audio_dev->out_ep;
+-	config_ep_by_speed(gadget, &audio_dev->func, ep);
++	ret = config_ep_by_speed(gadget, &audio_dev->func, ep);
++	if (ret < 0) {
++		dev_err(dev, "config_ep_by_speed for out_ep failed (%d)\n", ret);
++		return ret;
++	}
++
+ 	req_len = ep->maxpacket;
+ 
+ 	prm->ep_enabled = true;
+-	usb_ep_enable(ep);
++	ret = usb_ep_enable(ep);
++	if (ret < 0) {
++		dev_err(dev, "usb_ep_enable failed for out_ep (%d)\n", ret);
++		return ret;
++	}
+ 
+ 	for (i = 0; i < params->req_number; i++) {
+ 		if (!prm->reqs[i]) {
+@@ -629,9 +638,18 @@ int u_audio_start_capture(struct g_audio *audio_dev)
+ 		return 0;
+ 
+ 	/* Setup feedback endpoint */
+-	config_ep_by_speed(gadget, &audio_dev->func, ep_fback);
++	ret = config_ep_by_speed(gadget, &audio_dev->func, ep_fback);
++	if (ret < 0) {
++		dev_err(dev, "config_ep_by_speed in_ep_fback failed (%d)\n", ret);
++		return ret; // TODO: Clean up out_ep
++	}
++
+ 	prm->fb_ep_enabled = true;
+-	usb_ep_enable(ep_fback);
++	ret = usb_ep_enable(ep_fback);
++	if (ret < 0) {
++		dev_err(dev, "usb_ep_enable failed for in_ep_fback (%d)\n", ret);
++		return ret; // TODO: Clean up out_ep
++	}
+ 	req_len = ep_fback->maxpacket;
+ 
+ 	req_fback = usb_ep_alloc_request(ep_fback, GFP_ATOMIC);
+@@ -687,13 +705,17 @@ int u_audio_start_playback(struct g_audio *audio_dev)
+ 	struct uac_params *params = &audio_dev->params;
+ 	unsigned int factor;
+ 	const struct usb_endpoint_descriptor *ep_desc;
+-	int req_len, i;
++	int req_len, i, ret;
+ 	unsigned int p_pktsize;
+ 
+ 	prm = &uac->p_prm;
+ 	dev_dbg(dev, "start playback with rate %d\n", prm->srate);
+ 	ep = audio_dev->in_ep;
+-	config_ep_by_speed(gadget, &audio_dev->func, ep);
++	ret = config_ep_by_speed(gadget, &audio_dev->func, ep);
++	if (ret < 0) {
++		dev_err(dev, "config_ep_by_speed for in_ep failed (%d)\n", ret);
++		return ret;
++	}
+ 
+ 	ep_desc = ep->desc;
+ 	/*
+@@ -720,7 +742,11 @@ int u_audio_start_playback(struct g_audio *audio_dev)
+ 	uac->p_residue_mil = 0;
+ 
+ 	prm->ep_enabled = true;
+-	usb_ep_enable(ep);
++	ret = usb_ep_enable(ep);
++	if (ret < 0) {
++		dev_err(dev, "usb_ep_enable failed for in_ep (%d)\n", ret);
++		return ret;
++	}
+ 
+ 	for (i = 0; i < params->req_number; i++) {
+ 		if (!prm->reqs[i]) {
+diff --git a/drivers/usb/gadget/function/u_serial.c b/drivers/usb/gadget/function/u_serial.c
+index a92eb6d909768..8962f96ae7294 100644
+--- a/drivers/usb/gadget/function/u_serial.c
++++ b/drivers/usb/gadget/function/u_serial.c
+@@ -1441,6 +1441,7 @@ void gserial_suspend(struct gserial *gser)
+ 	spin_lock(&port->port_lock);
+ 	spin_unlock(&serial_port_lock);
+ 	port->suspended = true;
++	port->start_delayed = true;
+ 	spin_unlock_irqrestore(&port->port_lock, flags);
+ }
+ EXPORT_SYMBOL_GPL(gserial_suspend);
+diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c
+index 358394fc3db93..9886e1cb13985 100644
+--- a/drivers/usb/gadget/udc/core.c
++++ b/drivers/usb/gadget/udc/core.c
+@@ -118,12 +118,10 @@ int usb_ep_enable(struct usb_ep *ep)
+ 		goto out;
+ 
+ 	/* UDC drivers can't handle endpoints with maxpacket size 0 */
+-	if (usb_endpoint_maxp(ep->desc) == 0) {
+-		/*
+-		 * We should log an error message here, but we can't call
+-		 * dev_err() because there's no way to find the gadget
+-		 * given only ep.
+-		 */
++	if (!ep->desc || usb_endpoint_maxp(ep->desc) == 0) {
++		WARN_ONCE(1, "%s: ep%d (%s) has %s\n", __func__, ep->address, ep->name,
++			  (!ep->desc) ? "NULL descriptor" : "maxpacket 0");
++
+ 		ret = -EINVAL;
+ 		goto out;
+ 	}
+diff --git a/drivers/usb/serial/usb_debug.c b/drivers/usb/serial/usb_debug.c
+index 6934970f180d7..5a8869cd95d52 100644
+--- a/drivers/usb/serial/usb_debug.c
++++ b/drivers/usb/serial/usb_debug.c
+@@ -76,6 +76,11 @@ static void usb_debug_process_read_urb(struct urb *urb)
+ 	usb_serial_generic_process_read_urb(urb);
+ }
+ 
++static void usb_debug_init_termios(struct tty_struct *tty)
++{
++	tty->termios.c_lflag &= ~(ECHO | ECHONL);
++}
++
+ static struct usb_serial_driver debug_device = {
+ 	.driver = {
+ 		.owner =	THIS_MODULE,
+@@ -85,6 +90,7 @@ static struct usb_serial_driver debug_device = {
+ 	.num_ports =		1,
+ 	.bulk_out_size =	USB_DEBUG_MAX_PACKET_SIZE,
+ 	.break_ctl =		usb_debug_break_ctl,
++	.init_termios =		usb_debug_init_termios,
+ 	.process_read_urb =	usb_debug_process_read_urb,
+ };
+ 
+@@ -96,6 +102,7 @@ static struct usb_serial_driver dbc_device = {
+ 	.id_table =		dbc_id_table,
+ 	.num_ports =		1,
+ 	.break_ctl =		usb_debug_break_ctl,
++	.init_termios =		usb_debug_init_termios,
+ 	.process_read_urb =	usb_debug_process_read_urb,
+ };
+ 
+diff --git a/drivers/usb/usbip/vhci_hcd.c b/drivers/usb/usbip/vhci_hcd.c
+index 37d1fc34e8a56..14a5f55f24fc8 100644
+--- a/drivers/usb/usbip/vhci_hcd.c
++++ b/drivers/usb/usbip/vhci_hcd.c
+@@ -745,6 +745,7 @@ static int vhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flag
+ 	 *
+ 	 */
+ 	if (usb_pipedevice(urb->pipe) == 0) {
++		struct usb_device *old;
+ 		__u8 type = usb_pipetype(urb->pipe);
+ 		struct usb_ctrlrequest *ctrlreq =
+ 			(struct usb_ctrlrequest *) urb->setup_packet;
+@@ -755,14 +756,15 @@ static int vhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flag
+ 			goto no_need_xmit;
+ 		}
+ 
++		old = vdev->udev;
+ 		switch (ctrlreq->bRequest) {
+ 		case USB_REQ_SET_ADDRESS:
+ 			/* set_address may come when a device is reset */
+ 			dev_info(dev, "SetAddress Request (%d) to port %d\n",
+ 				 ctrlreq->wValue, vdev->rhport);
+ 
+-			usb_put_dev(vdev->udev);
+ 			vdev->udev = usb_get_dev(urb->dev);
++			usb_put_dev(old);
+ 
+ 			spin_lock(&vdev->ud.lock);
+ 			vdev->ud.status = VDEV_ST_USED;
+@@ -781,8 +783,8 @@ static int vhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flag
+ 				usbip_dbg_vhci_hc(
+ 					"Not yet?:Get_Descriptor to device 0 (get max pipe size)\n");
+ 
+-			usb_put_dev(vdev->udev);
+ 			vdev->udev = usb_get_dev(urb->dev);
++			usb_put_dev(old);
+ 			goto out;
+ 
+ 		default:
+@@ -1067,6 +1069,7 @@ static void vhci_shutdown_connection(struct usbip_device *ud)
+ static void vhci_device_reset(struct usbip_device *ud)
+ {
+ 	struct vhci_device *vdev = container_of(ud, struct vhci_device, ud);
++	struct usb_device *old = vdev->udev;
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&ud->lock, flags);
+@@ -1074,8 +1077,8 @@ static void vhci_device_reset(struct usbip_device *ud)
+ 	vdev->speed  = 0;
+ 	vdev->devid  = 0;
+ 
+-	usb_put_dev(vdev->udev);
+ 	vdev->udev = NULL;
++	usb_put_dev(old);
+ 
+ 	if (ud->tcp_socket) {
+ 		sockfd_put(ud->tcp_socket);
+diff --git a/drivers/vhost/vdpa.c b/drivers/vhost/vdpa.c
+index fb590e346e43d..da2c31ccc1380 100644
+--- a/drivers/vhost/vdpa.c
++++ b/drivers/vhost/vdpa.c
+@@ -1378,13 +1378,7 @@ static vm_fault_t vhost_vdpa_fault(struct vm_fault *vmf)
+ 
+ 	notify = ops->get_vq_notification(vdpa, index);
+ 
+-	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+-	if (remap_pfn_range(vma, vmf->address & PAGE_MASK,
+-			    PFN_DOWN(notify.addr), PAGE_SIZE,
+-			    vma->vm_page_prot))
+-		return VM_FAULT_SIGBUS;
+-
+-	return VM_FAULT_NOPAGE;
++	return vmf_insert_pfn(vma, vmf->address & PAGE_MASK, PFN_DOWN(notify.addr));
+ }
+ 
+ static const struct vm_operations_struct vhost_vdpa_vm_ops = {
+diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
+index da88173bac432..923f064c7e3e9 100644
+--- a/drivers/xen/privcmd.c
++++ b/drivers/xen/privcmd.c
+@@ -841,7 +841,7 @@ static long privcmd_ioctl_mmap_resource(struct file *file,
+ #ifdef CONFIG_XEN_PRIVCMD_IRQFD
+ /* Irqfd support */
+ static struct workqueue_struct *irqfd_cleanup_wq;
+-static DEFINE_MUTEX(irqfds_lock);
++static DEFINE_SPINLOCK(irqfds_lock);
+ static LIST_HEAD(irqfds_list);
+ 
+ struct privcmd_kernel_irqfd {
+@@ -905,9 +905,11 @@ irqfd_wakeup(wait_queue_entry_t *wait, unsigned int mode, int sync, void *key)
+ 		irqfd_inject(kirqfd);
+ 
+ 	if (flags & EPOLLHUP) {
+-		mutex_lock(&irqfds_lock);
++		unsigned long flags;
++
++		spin_lock_irqsave(&irqfds_lock, flags);
+ 		irqfd_deactivate(kirqfd);
+-		mutex_unlock(&irqfds_lock);
++		spin_unlock_irqrestore(&irqfds_lock, flags);
+ 	}
+ 
+ 	return 0;
+@@ -925,6 +927,7 @@ irqfd_poll_func(struct file *file, wait_queue_head_t *wqh, poll_table *pt)
+ static int privcmd_irqfd_assign(struct privcmd_irqfd *irqfd)
+ {
+ 	struct privcmd_kernel_irqfd *kirqfd, *tmp;
++	unsigned long flags;
+ 	__poll_t events;
+ 	struct fd f;
+ 	void *dm_op;
+@@ -964,18 +967,18 @@ static int privcmd_irqfd_assign(struct privcmd_irqfd *irqfd)
+ 	init_waitqueue_func_entry(&kirqfd->wait, irqfd_wakeup);
+ 	init_poll_funcptr(&kirqfd->pt, irqfd_poll_func);
+ 
+-	mutex_lock(&irqfds_lock);
++	spin_lock_irqsave(&irqfds_lock, flags);
+ 
+ 	list_for_each_entry(tmp, &irqfds_list, list) {
+ 		if (kirqfd->eventfd == tmp->eventfd) {
+ 			ret = -EBUSY;
+-			mutex_unlock(&irqfds_lock);
++			spin_unlock_irqrestore(&irqfds_lock, flags);
+ 			goto error_eventfd;
+ 		}
+ 	}
+ 
+ 	list_add_tail(&kirqfd->list, &irqfds_list);
+-	mutex_unlock(&irqfds_lock);
++	spin_unlock_irqrestore(&irqfds_lock, flags);
+ 
+ 	/*
+ 	 * Check if there was an event already pending on the eventfd before we
+@@ -1007,12 +1010,13 @@ static int privcmd_irqfd_deassign(struct privcmd_irqfd *irqfd)
+ {
+ 	struct privcmd_kernel_irqfd *kirqfd;
+ 	struct eventfd_ctx *eventfd;
++	unsigned long flags;
+ 
+ 	eventfd = eventfd_ctx_fdget(irqfd->fd);
+ 	if (IS_ERR(eventfd))
+ 		return PTR_ERR(eventfd);
+ 
+-	mutex_lock(&irqfds_lock);
++	spin_lock_irqsave(&irqfds_lock, flags);
+ 
+ 	list_for_each_entry(kirqfd, &irqfds_list, list) {
+ 		if (kirqfd->eventfd == eventfd) {
+@@ -1021,7 +1025,7 @@ static int privcmd_irqfd_deassign(struct privcmd_irqfd *irqfd)
+ 		}
+ 	}
+ 
+-	mutex_unlock(&irqfds_lock);
++	spin_unlock_irqrestore(&irqfds_lock, flags);
+ 
+ 	eventfd_ctx_put(eventfd);
+ 
+@@ -1069,13 +1073,14 @@ static int privcmd_irqfd_init(void)
+ static void privcmd_irqfd_exit(void)
+ {
+ 	struct privcmd_kernel_irqfd *kirqfd, *tmp;
++	unsigned long flags;
+ 
+-	mutex_lock(&irqfds_lock);
++	spin_lock_irqsave(&irqfds_lock, flags);
+ 
+ 	list_for_each_entry_safe(kirqfd, tmp, &irqfds_list, list)
+ 		irqfd_deactivate(kirqfd);
+ 
+-	mutex_unlock(&irqfds_lock);
++	spin_unlock_irqrestore(&irqfds_lock, flags);
+ 
+ 	destroy_workqueue(irqfd_cleanup_wq);
+ }
+diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h
+index 06333a74d6c4c..86c7f8ce1715e 100644
+--- a/fs/btrfs/ctree.h
++++ b/fs/btrfs/ctree.h
+@@ -445,6 +445,7 @@ struct btrfs_file_private {
+ 	void *filldir_buf;
+ 	u64 last_index;
+ 	struct extent_state *llseek_cached_state;
++	bool fsync_skip_inode_lock;
+ };
+ 
+ static inline u32 BTRFS_LEAF_DATA_SIZE(const struct btrfs_fs_info *info)
+diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c
+index 9fbffd84b16c5..c6a95dfa59c81 100644
+--- a/fs/btrfs/extent_io.c
++++ b/fs/btrfs/extent_io.c
+@@ -2172,10 +2172,8 @@ void extent_write_locked_range(struct inode *inode, struct page *locked_page,
+ 
+ 		page = find_get_page(mapping, cur >> PAGE_SHIFT);
+ 		ASSERT(PageLocked(page));
+-		if (pages_dirty && page != locked_page) {
++		if (pages_dirty && page != locked_page)
+ 			ASSERT(PageDirty(page));
+-			clear_page_dirty_for_io(page);
+-		}
+ 
+ 		ret = __extent_writepage_io(BTRFS_I(inode), page, &bio_ctrl,
+ 					    i_size, &nr);
+diff --git a/fs/btrfs/file.c b/fs/btrfs/file.c
+index c997b790568fa..952cf145c6295 100644
+--- a/fs/btrfs/file.c
++++ b/fs/btrfs/file.c
+@@ -1535,21 +1535,37 @@ static ssize_t btrfs_direct_write(struct kiocb *iocb, struct iov_iter *from)
+ 	 * So here we disable page faults in the iov_iter and then retry if we
+ 	 * got -EFAULT, faulting in the pages before the retry.
+ 	 */
++again:
+ 	from->nofault = true;
+ 	dio = btrfs_dio_write(iocb, from, written);
+ 	from->nofault = false;
+ 
+-	/*
+-	 * iomap_dio_complete() will call btrfs_sync_file() if we have a dsync
+-	 * iocb, and that needs to lock the inode. So unlock it before calling
+-	 * iomap_dio_complete() to avoid a deadlock.
+-	 */
+-	btrfs_inode_unlock(BTRFS_I(inode), ilock_flags);
+-
+-	if (IS_ERR_OR_NULL(dio))
++	if (IS_ERR_OR_NULL(dio)) {
+ 		err = PTR_ERR_OR_ZERO(dio);
+-	else
++	} else {
++		struct btrfs_file_private stack_private = { 0 };
++		struct btrfs_file_private *private;
++		const bool have_private = (file->private_data != NULL);
++
++		if (!have_private)
++			file->private_data = &stack_private;
++
++		/*
++		 * If we have a synchoronous write, we must make sure the fsync
++		 * triggered by the iomap_dio_complete() call below doesn't
++		 * deadlock on the inode lock - we are already holding it and we
++		 * can't call it after unlocking because we may need to complete
++		 * partial writes due to the input buffer (or parts of it) not
++		 * being already faulted in.
++		 */
++		private = file->private_data;
++		private->fsync_skip_inode_lock = true;
+ 		err = iomap_dio_complete(dio);
++		private->fsync_skip_inode_lock = false;
++
++		if (!have_private)
++			file->private_data = NULL;
++	}
+ 
+ 	/* No increment (+=) because iomap returns a cumulative value. */
+ 	if (err > 0)
+@@ -1576,10 +1592,12 @@ static ssize_t btrfs_direct_write(struct kiocb *iocb, struct iov_iter *from)
+ 		} else {
+ 			fault_in_iov_iter_readable(from, left);
+ 			prev_left = left;
+-			goto relock;
++			goto again;
+ 		}
+ 	}
+ 
++	btrfs_inode_unlock(BTRFS_I(inode), ilock_flags);
++
+ 	/*
+ 	 * If 'err' is -ENOTBLK or we have not written all data, then it means
+ 	 * we must fallback to buffered IO.
+@@ -1778,6 +1796,7 @@ static inline bool skip_inode_logging(const struct btrfs_log_ctx *ctx)
+  */
+ int btrfs_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
+ {
++	struct btrfs_file_private *private = file->private_data;
+ 	struct dentry *dentry = file_dentry(file);
+ 	struct inode *inode = d_inode(dentry);
+ 	struct btrfs_fs_info *fs_info = btrfs_sb(inode->i_sb);
+@@ -1787,6 +1806,7 @@ int btrfs_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
+ 	int ret = 0, err;
+ 	u64 len;
+ 	bool full_sync;
++	const bool skip_ilock = (private ? private->fsync_skip_inode_lock : false);
+ 
+ 	trace_btrfs_sync_file(file, datasync);
+ 
+@@ -1814,7 +1834,10 @@ int btrfs_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
+ 	if (ret)
+ 		goto out;
+ 
+-	btrfs_inode_lock(BTRFS_I(inode), BTRFS_ILOCK_MMAP);
++	if (skip_ilock)
++		down_write(&BTRFS_I(inode)->i_mmap_lock);
++	else
++		btrfs_inode_lock(BTRFS_I(inode), BTRFS_ILOCK_MMAP);
+ 
+ 	atomic_inc(&root->log_batch);
+ 
+@@ -1838,7 +1861,10 @@ int btrfs_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
+ 	 */
+ 	ret = start_ordered_ops(inode, start, end);
+ 	if (ret) {
+-		btrfs_inode_unlock(BTRFS_I(inode), BTRFS_ILOCK_MMAP);
++		if (skip_ilock)
++			up_write(&BTRFS_I(inode)->i_mmap_lock);
++		else
++			btrfs_inode_unlock(BTRFS_I(inode), BTRFS_ILOCK_MMAP);
+ 		goto out;
+ 	}
+ 
+@@ -1941,7 +1967,10 @@ int btrfs_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
+ 	 * file again, but that will end up using the synchronization
+ 	 * inside btrfs_sync_log to keep things safe.
+ 	 */
+-	btrfs_inode_unlock(BTRFS_I(inode), BTRFS_ILOCK_MMAP);
++	if (skip_ilock)
++		up_write(&BTRFS_I(inode)->i_mmap_lock);
++	else
++		btrfs_inode_unlock(BTRFS_I(inode), BTRFS_ILOCK_MMAP);
+ 
+ 	if (ret == BTRFS_NO_LOG_SYNC) {
+ 		ret = btrfs_end_transaction(trans);
+@@ -2009,7 +2038,10 @@ int btrfs_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
+ 
+ out_release_extents:
+ 	btrfs_release_log_ctx_extents(&ctx);
+-	btrfs_inode_unlock(BTRFS_I(inode), BTRFS_ILOCK_MMAP);
++	if (skip_ilock)
++		up_write(&BTRFS_I(inode)->i_mmap_lock);
++	else
++		btrfs_inode_unlock(BTRFS_I(inode), BTRFS_ILOCK_MMAP);
+ 	goto out;
+ }
+ 
+diff --git a/fs/btrfs/free-space-cache.c b/fs/btrfs/free-space-cache.c
+index f59e599766662..3e141c4dd2630 100644
+--- a/fs/btrfs/free-space-cache.c
++++ b/fs/btrfs/free-space-cache.c
+@@ -855,6 +855,7 @@ static int __load_free_space_cache(struct btrfs_root *root, struct inode *inode,
+ 				spin_unlock(&ctl->tree_lock);
+ 				btrfs_err(fs_info,
+ 					"Duplicate entries in free space cache, dumping");
++				kmem_cache_free(btrfs_free_space_bitmap_cachep, e->bitmap);
+ 				kmem_cache_free(btrfs_free_space_cachep, e);
+ 				goto free_cache;
+ 			}
+diff --git a/fs/btrfs/print-tree.c b/fs/btrfs/print-tree.c
+index 0c93439e929fb..815a5fc3ff9d8 100644
+--- a/fs/btrfs/print-tree.c
++++ b/fs/btrfs/print-tree.c
+@@ -12,7 +12,7 @@
+ 
+ struct root_name_map {
+ 	u64 id;
+-	char name[16];
++	const char *name;
+ };
+ 
+ static const struct root_name_map root_map[] = {
+diff --git a/fs/ext4/inline.c b/fs/ext4/inline.c
+index 012d9259ff532..a604aa1d23aed 100644
+--- a/fs/ext4/inline.c
++++ b/fs/ext4/inline.c
+@@ -1411,7 +1411,11 @@ int ext4_inlinedir_to_tree(struct file *dir_file,
+ 			hinfo->hash = EXT4_DIRENT_HASH(de);
+ 			hinfo->minor_hash = EXT4_DIRENT_MINOR_HASH(de);
+ 		} else {
+-			ext4fs_dirhash(dir, de->name, de->name_len, hinfo);
++			err = ext4fs_dirhash(dir, de->name, de->name_len, hinfo);
++			if (err) {
++				ret = err;
++				goto out;
++			}
+ 		}
+ 		if ((hinfo->hash < start_hash) ||
+ 		    ((hinfo->hash == start_hash) &&
+diff --git a/fs/jbd2/journal.c b/fs/jbd2/journal.c
+index 0168d28427077..57264eb4d9da3 100644
+--- a/fs/jbd2/journal.c
++++ b/fs/jbd2/journal.c
+@@ -399,6 +399,7 @@ int jbd2_journal_write_metadata_buffer(transaction_t *transaction,
+ 		tmp = jbd2_alloc(bh_in->b_size, GFP_NOFS);
+ 		if (!tmp) {
+ 			brelse(new_bh);
++			free_buffer_head(new_bh);
+ 			return -ENOMEM;
+ 		}
+ 		spin_lock(&jh_in->b_state_lock);
+diff --git a/fs/smb/client/cifs_debug.c b/fs/smb/client/cifs_debug.c
+index c71ae5c043060..4a20e92474b23 100644
+--- a/fs/smb/client/cifs_debug.c
++++ b/fs/smb/client/cifs_debug.c
+@@ -1072,7 +1072,7 @@ static int cifs_security_flags_proc_open(struct inode *inode, struct file *file)
+ static void
+ cifs_security_flags_handle_must_flags(unsigned int *flags)
+ {
+-	unsigned int signflags = *flags & CIFSSEC_MUST_SIGN;
++	unsigned int signflags = *flags & (CIFSSEC_MUST_SIGN | CIFSSEC_MUST_SEAL);
+ 
+ 	if ((*flags & CIFSSEC_MUST_KRB5) == CIFSSEC_MUST_KRB5)
+ 		*flags = CIFSSEC_MUST_KRB5;
+diff --git a/fs/smb/client/cifsglob.h b/fs/smb/client/cifsglob.h
+index 53e00255d96b6..54a84003950a4 100644
+--- a/fs/smb/client/cifsglob.h
++++ b/fs/smb/client/cifsglob.h
+@@ -1922,7 +1922,7 @@ static inline bool is_replayable_error(int error)
+ #define   CIFSSEC_MAY_SIGN	0x00001
+ #define   CIFSSEC_MAY_NTLMV2	0x00004
+ #define   CIFSSEC_MAY_KRB5	0x00008
+-#define   CIFSSEC_MAY_SEAL	0x00040 /* not supported yet */
++#define   CIFSSEC_MAY_SEAL	0x00040
+ #define   CIFSSEC_MAY_NTLMSSP	0x00080 /* raw ntlmssp with ntlmv2 */
+ 
+ #define   CIFSSEC_MUST_SIGN	0x01001
+@@ -1932,11 +1932,11 @@ require use of the stronger protocol */
+ #define   CIFSSEC_MUST_NTLMV2	0x04004
+ #define   CIFSSEC_MUST_KRB5	0x08008
+ #ifdef CONFIG_CIFS_UPCALL
+-#define   CIFSSEC_MASK          0x8F08F /* flags supported if no weak allowed */
++#define   CIFSSEC_MASK          0xCF0CF /* flags supported if no weak allowed */
+ #else
+-#define	  CIFSSEC_MASK          0x87087 /* flags supported if no weak allowed */
++#define	  CIFSSEC_MASK          0xC70C7 /* flags supported if no weak allowed */
+ #endif /* UPCALL */
+-#define   CIFSSEC_MUST_SEAL	0x40040 /* not supported yet */
++#define   CIFSSEC_MUST_SEAL	0x40040
+ #define   CIFSSEC_MUST_NTLMSSP	0x80080 /* raw ntlmssp with ntlmv2 */
+ 
+ #define   CIFSSEC_DEF (CIFSSEC_MAY_SIGN | CIFSSEC_MAY_NTLMV2 | CIFSSEC_MAY_NTLMSSP | CIFSSEC_MAY_SEAL)
+diff --git a/fs/smb/client/inode.c b/fs/smb/client/inode.c
+index 9cdbc3ccc1d14..e74ba047902d8 100644
+--- a/fs/smb/client/inode.c
++++ b/fs/smb/client/inode.c
+@@ -1023,13 +1023,26 @@ static int reparse_info_to_fattr(struct cifs_open_info_data *data,
+ 	}
+ 
+ 	rc = -EOPNOTSUPP;
+-	switch ((data->reparse.tag = tag)) {
+-	case 0: /* SMB1 symlink */
++	data->reparse.tag = tag;
++	if (!data->reparse.tag) {
+ 		if (server->ops->query_symlink) {
+ 			rc = server->ops->query_symlink(xid, tcon,
+ 							cifs_sb, full_path,
+ 							&data->symlink_target);
+ 		}
++		if (rc == -EOPNOTSUPP)
++			data->reparse.tag = IO_REPARSE_TAG_INTERNAL;
++	}
++
++	switch (data->reparse.tag) {
++	case 0: /* SMB1 symlink */
++		break;
++	case IO_REPARSE_TAG_INTERNAL:
++		rc = 0;
++		if (le32_to_cpu(data->fi.Attributes) & ATTR_DIRECTORY) {
++			cifs_create_junction_fattr(fattr, sb);
++			goto out;
++		}
+ 		break;
+ 	case IO_REPARSE_TAG_MOUNT_POINT:
+ 		cifs_create_junction_fattr(fattr, sb);
+diff --git a/fs/smb/client/misc.c b/fs/smb/client/misc.c
+index 07c468ddb88a8..65d4b72b4d51a 100644
+--- a/fs/smb/client/misc.c
++++ b/fs/smb/client/misc.c
+@@ -1288,6 +1288,7 @@ int cifs_inval_name_dfs_link_error(const unsigned int xid,
+ 				   const char *full_path,
+ 				   bool *islink)
+ {
++	struct TCP_Server_Info *server = tcon->ses->server;
+ 	struct cifs_ses *ses = tcon->ses;
+ 	size_t len;
+ 	char *path;
+@@ -1304,12 +1305,12 @@ int cifs_inval_name_dfs_link_error(const unsigned int xid,
+ 	    !is_tcon_dfs(tcon))
+ 		return 0;
+ 
+-	spin_lock(&tcon->tc_lock);
+-	if (!tcon->origin_fullpath) {
+-		spin_unlock(&tcon->tc_lock);
++	spin_lock(&server->srv_lock);
++	if (!server->leaf_fullpath) {
++		spin_unlock(&server->srv_lock);
+ 		return 0;
+ 	}
+-	spin_unlock(&tcon->tc_lock);
++	spin_unlock(&server->srv_lock);
+ 
+ 	/*
+ 	 * Slow path - tcon is DFS and @full_path has prefix path, so attempt
+diff --git a/fs/smb/client/reparse.c b/fs/smb/client/reparse.c
+index a0ffbda907331..689d8a506d459 100644
+--- a/fs/smb/client/reparse.c
++++ b/fs/smb/client/reparse.c
+@@ -505,6 +505,10 @@ bool cifs_reparse_point_to_fattr(struct cifs_sb_info *cifs_sb,
+ 	}
+ 
+ 	switch (tag) {
++	case IO_REPARSE_TAG_INTERNAL:
++		if (!(fattr->cf_cifsattrs & ATTR_DIRECTORY))
++			return false;
++		fallthrough;
+ 	case IO_REPARSE_TAG_DFS:
+ 	case IO_REPARSE_TAG_DFSR:
+ 	case IO_REPARSE_TAG_MOUNT_POINT:
+diff --git a/fs/smb/client/reparse.h b/fs/smb/client/reparse.h
+index 6b55d1df9e2f8..2c0644bc4e65a 100644
+--- a/fs/smb/client/reparse.h
++++ b/fs/smb/client/reparse.h
+@@ -12,6 +12,12 @@
+ #include "fs_context.h"
+ #include "cifsglob.h"
+ 
++/*
++ * Used only by cifs.ko to ignore reparse points from files when client or
++ * server doesn't support FSCTL_GET_REPARSE_POINT.
++ */
++#define IO_REPARSE_TAG_INTERNAL ((__u32)~0U)
++
+ static inline dev_t reparse_nfs_mkdev(struct reparse_posix_data *buf)
+ {
+ 	u64 v = le64_to_cpu(*(__le64 *)buf->DataBuffer);
+@@ -78,10 +84,19 @@ static inline u32 reparse_mode_wsl_tag(mode_t mode)
+ static inline bool reparse_inode_match(struct inode *inode,
+ 				       struct cifs_fattr *fattr)
+ {
++	struct cifsInodeInfo *cinode = CIFS_I(inode);
+ 	struct timespec64 ctime = inode_get_ctime(inode);
+ 
+-	return (CIFS_I(inode)->cifsAttrs & ATTR_REPARSE) &&
+-		CIFS_I(inode)->reparse_tag == fattr->cf_cifstag &&
++	/*
++	 * Do not match reparse tags when client or server doesn't support
++	 * FSCTL_GET_REPARSE_POINT.  @fattr->cf_cifstag should contain correct
++	 * reparse tag from query dir response but the client won't be able to
++	 * read the reparse point data anyway.  This spares us a revalidation.
++	 */
++	if (cinode->reparse_tag != IO_REPARSE_TAG_INTERNAL &&
++	    cinode->reparse_tag != fattr->cf_cifstag)
++		return false;
++	return (cinode->cifsAttrs & ATTR_REPARSE) &&
+ 		timespec64_equal(&ctime, &fattr->cf_ctime);
+ }
+ 
+diff --git a/fs/smb/client/smb2inode.c b/fs/smb/client/smb2inode.c
+index 86f8c81791374..28031c7ba6b19 100644
+--- a/fs/smb/client/smb2inode.c
++++ b/fs/smb/client/smb2inode.c
+@@ -930,6 +930,8 @@ int smb2_query_path_info(const unsigned int xid,
+ 
+ 	switch (rc) {
+ 	case 0:
++		rc = parse_create_response(data, cifs_sb, &out_iov[0]);
++		break;
+ 	case -EOPNOTSUPP:
+ 		/*
+ 		 * BB TODO: When support for special files added to Samba
+diff --git a/fs/smb/client/smb2pdu.c b/fs/smb/client/smb2pdu.c
+index a5efce03cb58e..61df8a5c68242 100644
+--- a/fs/smb/client/smb2pdu.c
++++ b/fs/smb/client/smb2pdu.c
+@@ -80,6 +80,9 @@ int smb3_encryption_required(const struct cifs_tcon *tcon)
+ 	if (tcon->seal &&
+ 	    (tcon->ses->server->capabilities & SMB2_GLOBAL_CAP_ENCRYPTION))
+ 		return 1;
++	if (((global_secflags & CIFSSEC_MUST_SEAL) == CIFSSEC_MUST_SEAL) &&
++	    (tcon->ses->server->capabilities & SMB2_GLOBAL_CAP_ENCRYPTION))
++		return 1;
+ 	return 0;
+ }
+ 
+diff --git a/fs/tracefs/event_inode.c b/fs/tracefs/event_inode.c
+index b406bb3430f3d..aa54be1ce1242 100644
+--- a/fs/tracefs/event_inode.c
++++ b/fs/tracefs/event_inode.c
+@@ -113,7 +113,7 @@ static void release_ei(struct kref *ref)
+ 			entry->release(entry->name, ei->data);
+ 	}
+ 
+-	call_rcu(&ei->rcu, free_ei_rcu);
++	call_srcu(&eventfs_srcu, &ei->rcu, free_ei_rcu);
+ }
+ 
+ static inline void put_ei(struct eventfs_inode *ei)
+@@ -806,7 +806,7 @@ struct eventfs_inode *eventfs_create_dir(const char *name, struct eventfs_inode
+ 	/* Was the parent freed? */
+ 	if (list_empty(&ei->list)) {
+ 		cleanup_ei(ei);
+-		ei = NULL;
++		ei = ERR_PTR(-EBUSY);
+ 	}
+ 	return ei;
+ }
+diff --git a/fs/tracefs/inode.c b/fs/tracefs/inode.c
+index 4ea11d1f72ace..7d389dd5ed519 100644
+--- a/fs/tracefs/inode.c
++++ b/fs/tracefs/inode.c
+@@ -42,7 +42,7 @@ static struct inode *tracefs_alloc_inode(struct super_block *sb)
+ 	struct tracefs_inode *ti;
+ 	unsigned long flags;
+ 
+-	ti = kmem_cache_alloc(tracefs_inode_cachep, GFP_KERNEL);
++	ti = alloc_inode_sb(sb, tracefs_inode_cachep, GFP_KERNEL);
+ 	if (!ti)
+ 		return NULL;
+ 
+@@ -53,15 +53,14 @@ static struct inode *tracefs_alloc_inode(struct super_block *sb)
+ 	return &ti->vfs_inode;
+ }
+ 
+-static void tracefs_free_inode_rcu(struct rcu_head *rcu)
++static void tracefs_free_inode(struct inode *inode)
+ {
+-	struct tracefs_inode *ti;
++	struct tracefs_inode *ti = get_tracefs(inode);
+ 
+-	ti = container_of(rcu, struct tracefs_inode, rcu);
+ 	kmem_cache_free(tracefs_inode_cachep, ti);
+ }
+ 
+-static void tracefs_free_inode(struct inode *inode)
++static void tracefs_destroy_inode(struct inode *inode)
+ {
+ 	struct tracefs_inode *ti = get_tracefs(inode);
+ 	unsigned long flags;
+@@ -69,8 +68,6 @@ static void tracefs_free_inode(struct inode *inode)
+ 	spin_lock_irqsave(&tracefs_inode_lock, flags);
+ 	list_del_rcu(&ti->list);
+ 	spin_unlock_irqrestore(&tracefs_inode_lock, flags);
+-
+-	call_rcu(&ti->rcu, tracefs_free_inode_rcu);
+ }
+ 
+ static ssize_t default_read_file(struct file *file, char __user *buf,
+@@ -458,6 +455,7 @@ static int tracefs_drop_inode(struct inode *inode)
+ static const struct super_operations tracefs_super_operations = {
+ 	.alloc_inode    = tracefs_alloc_inode,
+ 	.free_inode     = tracefs_free_inode,
++	.destroy_inode  = tracefs_destroy_inode,
+ 	.drop_inode     = tracefs_drop_inode,
+ 	.statfs		= simple_statfs,
+ 	.remount_fs	= tracefs_remount,
+diff --git a/fs/tracefs/internal.h b/fs/tracefs/internal.h
+index f704d8348357e..d83c2a25f288e 100644
+--- a/fs/tracefs/internal.h
++++ b/fs/tracefs/internal.h
+@@ -10,10 +10,7 @@ enum {
+ };
+ 
+ struct tracefs_inode {
+-	union {
+-		struct inode            vfs_inode;
+-		struct rcu_head		rcu;
+-	};
++	struct inode            vfs_inode;
+ 	/* The below gets initialized with memset_after(ti, 0, vfs_inode) */
+ 	struct list_head	list;
+ 	unsigned long           flags;
+diff --git a/fs/udf/balloc.c b/fs/udf/balloc.c
+index 558ad046972ad..bb471ec364046 100644
+--- a/fs/udf/balloc.c
++++ b/fs/udf/balloc.c
+@@ -18,6 +18,7 @@
+ #include "udfdecl.h"
+ 
+ #include <linux/bitops.h>
++#include <linux/overflow.h>
+ 
+ #include "udf_i.h"
+ #include "udf_sb.h"
+@@ -140,7 +141,6 @@ static void udf_bitmap_free_blocks(struct super_block *sb,
+ {
+ 	struct udf_sb_info *sbi = UDF_SB(sb);
+ 	struct buffer_head *bh = NULL;
+-	struct udf_part_map *partmap;
+ 	unsigned long block;
+ 	unsigned long block_group;
+ 	unsigned long bit;
+@@ -149,19 +149,9 @@ static void udf_bitmap_free_blocks(struct super_block *sb,
+ 	unsigned long overflow;
+ 
+ 	mutex_lock(&sbi->s_alloc_mutex);
+-	partmap = &sbi->s_partmaps[bloc->partitionReferenceNum];
+-	if (bloc->logicalBlockNum + count < count ||
+-	    (bloc->logicalBlockNum + count) > partmap->s_partition_len) {
+-		udf_debug("%u < %d || %u + %u > %u\n",
+-			  bloc->logicalBlockNum, 0,
+-			  bloc->logicalBlockNum, count,
+-			  partmap->s_partition_len);
+-		goto error_return;
+-	}
+-
++	/* We make sure this cannot overflow when mounting the filesystem */
+ 	block = bloc->logicalBlockNum + offset +
+ 		(sizeof(struct spaceBitmapDesc) << 3);
+-
+ 	do {
+ 		overflow = 0;
+ 		block_group = block >> (sb->s_blocksize_bits + 3);
+@@ -391,7 +381,6 @@ static void udf_table_free_blocks(struct super_block *sb,
+ 				  uint32_t count)
+ {
+ 	struct udf_sb_info *sbi = UDF_SB(sb);
+-	struct udf_part_map *partmap;
+ 	uint32_t start, end;
+ 	uint32_t elen;
+ 	struct kernel_lb_addr eloc;
+@@ -400,16 +389,6 @@ static void udf_table_free_blocks(struct super_block *sb,
+ 	struct udf_inode_info *iinfo;
+ 
+ 	mutex_lock(&sbi->s_alloc_mutex);
+-	partmap = &sbi->s_partmaps[bloc->partitionReferenceNum];
+-	if (bloc->logicalBlockNum + count < count ||
+-	    (bloc->logicalBlockNum + count) > partmap->s_partition_len) {
+-		udf_debug("%u < %d || %u + %u > %u\n",
+-			  bloc->logicalBlockNum, 0,
+-			  bloc->logicalBlockNum, count,
+-			  partmap->s_partition_len);
+-		goto error_return;
+-	}
+-
+ 	iinfo = UDF_I(table);
+ 	udf_add_free_space(sb, sbi->s_partition, count);
+ 
+@@ -684,6 +663,17 @@ void udf_free_blocks(struct super_block *sb, struct inode *inode,
+ {
+ 	uint16_t partition = bloc->partitionReferenceNum;
+ 	struct udf_part_map *map = &UDF_SB(sb)->s_partmaps[partition];
++	uint32_t blk;
++
++	if (check_add_overflow(bloc->logicalBlockNum, offset, &blk) ||
++	    check_add_overflow(blk, count, &blk) ||
++	    bloc->logicalBlockNum + count > map->s_partition_len) {
++		udf_debug("Invalid request to free blocks: (%d, %u), off %u, "
++			  "len %u, partition len %u\n",
++			  partition, bloc->logicalBlockNum, offset, count,
++			  map->s_partition_len);
++		return;
++	}
+ 
+ 	if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP) {
+ 		udf_bitmap_free_blocks(sb, map->s_uspace.s_bitmap,
+diff --git a/fs/xfs/xfs_log_recover.c b/fs/xfs/xfs_log_recover.c
+index 57f366c3d3554..9f9d3abad2cf3 100644
+--- a/fs/xfs/xfs_log_recover.c
++++ b/fs/xfs/xfs_log_recover.c
+@@ -2965,7 +2965,7 @@ xlog_do_recovery_pass(
+ 	int			error = 0, h_size, h_len;
+ 	int			error2 = 0;
+ 	int			bblks, split_bblks;
+-	int			hblks, split_hblks, wrapped_hblks;
++	int			hblks = 1, split_hblks, wrapped_hblks;
+ 	int			i;
+ 	struct hlist_head	rhash[XLOG_RHASH_SIZE];
+ 	LIST_HEAD		(buffer_list);
+@@ -3021,14 +3021,22 @@ xlog_do_recovery_pass(
+ 		if (error)
+ 			goto bread_err1;
+ 
+-		hblks = xlog_logrec_hblks(log, rhead);
+-		if (hblks != 1) {
+-			kmem_free(hbp);
+-			hbp = xlog_alloc_buffer(log, hblks);
++		/*
++		 * This open codes xlog_logrec_hblks so that we can reuse the
++		 * fixed up h_size value calculated above.  Without that we'd
++		 * still allocate the buffer based on the incorrect on-disk
++		 * size.
++		 */
++		if (h_size > XLOG_HEADER_CYCLE_SIZE &&
++		    (rhead->h_version & cpu_to_be32(XLOG_VERSION_2))) {
++			hblks = DIV_ROUND_UP(h_size, XLOG_HEADER_CYCLE_SIZE);
++			if (hblks > 1) {
++				kmem_free(hbp);
++				hbp = xlog_alloc_buffer(log, hblks);
++			}
+ 		}
+ 	} else {
+ 		ASSERT(log->l_sectBBsize == 1);
+-		hblks = 1;
+ 		hbp = xlog_alloc_buffer(log, 1);
+ 		h_size = XLOG_BIG_RECORD_BSIZE;
+ 	}
+diff --git a/include/linux/blk-integrity.h b/include/linux/blk-integrity.h
+index 378b2459efe2d..f7cc8080672cc 100644
+--- a/include/linux/blk-integrity.h
++++ b/include/linux/blk-integrity.h
+@@ -105,14 +105,13 @@ static inline bool blk_integrity_rq(struct request *rq)
+ }
+ 
+ /*
+- * Return the first bvec that contains integrity data.  Only drivers that are
+- * limited to a single integrity segment should use this helper.
++ * Return the current bvec that contains the integrity data. bip_iter may be
++ * advanced to iterate over the integrity data.
+  */
+-static inline struct bio_vec *rq_integrity_vec(struct request *rq)
++static inline struct bio_vec rq_integrity_vec(struct request *rq)
+ {
+-	if (WARN_ON_ONCE(queue_max_integrity_segments(rq->q) > 1))
+-		return NULL;
+-	return rq->bio->bi_integrity->bip_vec;
++	return mp_bvec_iter_bvec(rq->bio->bi_integrity->bip_vec,
++				 rq->bio->bi_integrity->bip_iter);
+ }
+ #else /* CONFIG_BLK_DEV_INTEGRITY */
+ static inline int blk_rq_count_integrity_sg(struct request_queue *q,
+@@ -176,9 +175,10 @@ static inline int blk_integrity_rq(struct request *rq)
+ 	return 0;
+ }
+ 
+-static inline struct bio_vec *rq_integrity_vec(struct request *rq)
++static inline struct bio_vec rq_integrity_vec(struct request *rq)
+ {
+-	return NULL;
++	/* the optimizer will remove all calls to this function */
++	return (struct bio_vec){ };
+ }
+ #endif /* CONFIG_BLK_DEV_INTEGRITY */
+ #endif /* _LINUX_BLK_INTEGRITY_H */
+diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
+index 1d42d4b173271..0ad8b550bb4b4 100644
+--- a/include/linux/clocksource.h
++++ b/include/linux/clocksource.h
+@@ -291,7 +291,19 @@ static inline void timer_probe(void) {}
+ #define TIMER_ACPI_DECLARE(name, table_id, fn)		\
+ 	ACPI_DECLARE_PROBE_ENTRY(timer, name, table_id, 0, NULL, 0, fn)
+ 
+-extern ulong max_cswd_read_retries;
++static inline unsigned int clocksource_get_max_watchdog_retry(void)
++{
++	/*
++	 * When system is in the boot phase or under heavy workload, there
++	 * can be random big latencies during the clocksource/watchdog
++	 * read, so allow retries to filter the noise latency. As the
++	 * latency's frequency and maximum value goes up with the number of
++	 * CPUs, scale the number of retries with the number of online
++	 * CPUs.
++	 */
++	return (ilog2(num_online_cpus()) / 2) + 1;
++}
++
+ void clocksource_verify_percpu(struct clocksource *cs);
+ 
+ #endif /* _LINUX_CLOCKSOURCE_H */
+diff --git a/include/linux/fs.h b/include/linux/fs.h
+index ee5efad0d7801..56dce38c47862 100644
+--- a/include/linux/fs.h
++++ b/include/linux/fs.h
+@@ -642,6 +642,7 @@ struct inode {
+ 	umode_t			i_mode;
+ 	unsigned short		i_opflags;
+ 	kuid_t			i_uid;
++	struct list_head	i_lru;		/* inode LRU list */
+ 	kgid_t			i_gid;
+ 	unsigned int		i_flags;
+ 
+@@ -703,7 +704,6 @@ struct inode {
+ 	u16			i_wb_frn_avg_time;
+ 	u16			i_wb_frn_history;
+ #endif
+-	struct list_head	i_lru;		/* inode LRU list */
+ 	struct list_head	i_sb_list;
+ 	struct list_head	i_wb_list;	/* backing dev writeback list */
+ 	union {
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 0a85ff5c8db3c..abff4e3b6a58b 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2124,6 +2124,8 @@
+ 
+ #define PCI_VENDOR_ID_CHELSIO		0x1425
+ 
++#define PCI_VENDOR_ID_EDIMAX		0x1432
++
+ #define PCI_VENDOR_ID_ADLINK		0x144a
+ 
+ #define PCI_VENDOR_ID_SAMSUNG		0x144d
+diff --git a/include/linux/profile.h b/include/linux/profile.h
+index 11db1ec516e27..12da750a88a04 100644
+--- a/include/linux/profile.h
++++ b/include/linux/profile.h
+@@ -11,7 +11,6 @@
+ 
+ #define CPU_PROFILING	1
+ #define SCHED_PROFILING	2
+-#define SLEEP_PROFILING	3
+ #define KVM_PROFILING	4
+ 
+ struct proc_dir_entry;
+diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h
+index 696f8dc4aa53c..cb8bd759e8005 100644
+--- a/include/linux/trace_events.h
++++ b/include/linux/trace_events.h
+@@ -869,7 +869,6 @@ do {									\
+ struct perf_event;
+ 
+ DECLARE_PER_CPU(struct pt_regs, perf_trace_regs);
+-DECLARE_PER_CPU(int, bpf_kprobe_override);
+ 
+ extern int  perf_trace_init(struct perf_event *event);
+ extern void perf_trace_destroy(struct perf_event *event);
+diff --git a/include/linux/virtio_net.h b/include/linux/virtio_net.h
+index d1d7825318c32..6c395a2600e8d 100644
+--- a/include/linux/virtio_net.h
++++ b/include/linux/virtio_net.h
+@@ -56,7 +56,6 @@ static inline int virtio_net_hdr_to_skb(struct sk_buff *skb,
+ 	unsigned int thlen = 0;
+ 	unsigned int p_off = 0;
+ 	unsigned int ip_proto;
+-	u64 ret, remainder, gso_size;
+ 
+ 	if (hdr->gso_type != VIRTIO_NET_HDR_GSO_NONE) {
+ 		switch (hdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN) {
+@@ -99,16 +98,6 @@ static inline int virtio_net_hdr_to_skb(struct sk_buff *skb,
+ 		u32 off = __virtio16_to_cpu(little_endian, hdr->csum_offset);
+ 		u32 needed = start + max_t(u32, thlen, off + sizeof(__sum16));
+ 
+-		if (hdr->gso_size) {
+-			gso_size = __virtio16_to_cpu(little_endian, hdr->gso_size);
+-			ret = div64_u64_rem(skb->len, gso_size, &remainder);
+-			if (!(ret && (hdr->gso_size > needed) &&
+-						((remainder > needed) || (remainder == 0)))) {
+-				return -EINVAL;
+-			}
+-			skb_shinfo(skb)->tx_flags |= SKBFL_SHARED_FRAG;
+-		}
+-
+ 		if (!pskb_may_pull(skb, needed))
+ 			return -EINVAL;
+ 
+@@ -182,6 +171,11 @@ static inline int virtio_net_hdr_to_skb(struct sk_buff *skb,
+ 			if (gso_type != SKB_GSO_UDP_L4)
+ 				return -EINVAL;
+ 			break;
++		case SKB_GSO_TCPV4:
++		case SKB_GSO_TCPV6:
++			if (skb->csum_offset != offsetof(struct tcphdr, check))
++				return -EINVAL;
++			break;
+ 		}
+ 
+ 		/* Kernel has a special handling for GSO_BY_FRAGS. */
+diff --git a/include/net/ip6_route.h b/include/net/ip6_route.h
+index b32539bb0fb05..61cfc8891f820 100644
+--- a/include/net/ip6_route.h
++++ b/include/net/ip6_route.h
+@@ -128,18 +128,26 @@ void rt6_age_exceptions(struct fib6_info *f6i, struct fib6_gc_args *gc_args,
+ 
+ static inline int ip6_route_get_saddr(struct net *net, struct fib6_info *f6i,
+ 				      const struct in6_addr *daddr,
+-				      unsigned int prefs,
++				      unsigned int prefs, int l3mdev_index,
+ 				      struct in6_addr *saddr)
+ {
++	struct net_device *l3mdev;
++	struct net_device *dev;
++	bool same_vrf;
+ 	int err = 0;
+ 
+-	if (f6i && f6i->fib6_prefsrc.plen) {
++	rcu_read_lock();
++
++	l3mdev = dev_get_by_index_rcu(net, l3mdev_index);
++	if (!f6i || !f6i->fib6_prefsrc.plen || l3mdev)
++		dev = f6i ? fib6_info_nh_dev(f6i) : NULL;
++	same_vrf = !l3mdev || l3mdev_master_dev_rcu(dev) == l3mdev;
++	if (f6i && f6i->fib6_prefsrc.plen && same_vrf)
+ 		*saddr = f6i->fib6_prefsrc.addr;
+-	} else {
+-		struct net_device *dev = f6i ? fib6_info_nh_dev(f6i) : NULL;
++	else
++		err = ipv6_dev_get_saddr(net, same_vrf ? dev : l3mdev, daddr, prefs, saddr);
+ 
+-		err = ipv6_dev_get_saddr(net, dev, daddr, prefs, saddr);
+-	}
++	rcu_read_unlock();
+ 
+ 	return err;
+ }
+diff --git a/include/trace/events/intel_ifs.h b/include/trace/events/intel_ifs.h
+index d7353024016cc..af0af3f1d9b7c 100644
+--- a/include/trace/events/intel_ifs.h
++++ b/include/trace/events/intel_ifs.h
+@@ -10,25 +10,25 @@
+ 
+ TRACE_EVENT(ifs_status,
+ 
+-	TP_PROTO(int cpu, union ifs_scan activate, union ifs_status status),
++	TP_PROTO(int cpu, int start, int stop, u64 status),
+ 
+-	TP_ARGS(cpu, activate, status),
++	TP_ARGS(cpu, start, stop, status),
+ 
+ 	TP_STRUCT__entry(
+ 		__field(	u64,	status	)
+ 		__field(	int,	cpu	)
+-		__field(	u8,	start	)
+-		__field(	u8,	stop	)
++		__field(	u16,	start	)
++		__field(	u16,	stop	)
+ 	),
+ 
+ 	TP_fast_assign(
+ 		__entry->cpu	= cpu;
+-		__entry->start	= activate.start;
+-		__entry->stop	= activate.stop;
+-		__entry->status	= status.data;
++		__entry->start	= start;
++		__entry->stop	= stop;
++		__entry->status	= status;
+ 	),
+ 
+-	TP_printk("cpu: %d, start: %.2x, stop: %.2x, status: %llx",
++	TP_printk("cpu: %d, start: %.4x, stop: %.4x, status: %.16llx",
+ 		__entry->cpu,
+ 		__entry->start,
+ 		__entry->stop,
+diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c
+index 5c9888901ef44..46094f0c9fcda 100644
+--- a/kernel/irq/irqdesc.c
++++ b/kernel/irq/irqdesc.c
+@@ -517,6 +517,7 @@ static int alloc_descs(unsigned int start, unsigned int cnt, int node,
+ 				flags = IRQD_AFFINITY_MANAGED |
+ 					IRQD_MANAGED_SHUTDOWN;
+ 			}
++			flags |= IRQD_AFFINITY_SET;
+ 			mask = &affinity->mask;
+ 			node = cpu_to_node(cpumask_first(mask));
+ 			affinity++;
+diff --git a/kernel/jump_label.c b/kernel/jump_label.c
+index eec802175ccc6..1ed269b2c4035 100644
+--- a/kernel/jump_label.c
++++ b/kernel/jump_label.c
+@@ -231,7 +231,7 @@ void static_key_disable_cpuslocked(struct static_key *key)
+ 	}
+ 
+ 	jump_label_lock();
+-	if (atomic_cmpxchg(&key->enabled, 1, 0))
++	if (atomic_cmpxchg(&key->enabled, 1, 0) == 1)
+ 		jump_label_update(key);
+ 	jump_label_unlock();
+ }
+@@ -284,7 +284,7 @@ static void __static_key_slow_dec_cpuslocked(struct static_key *key)
+ 		return;
+ 
+ 	guard(mutex)(&jump_label_mutex);
+-	if (atomic_cmpxchg(&key->enabled, 1, 0))
++	if (atomic_cmpxchg(&key->enabled, 1, 0) == 1)
+ 		jump_label_update(key);
+ 	else
+ 		WARN_ON_ONCE(!static_key_slow_try_dec(key));
+diff --git a/kernel/kcov.c b/kernel/kcov.c
+index 9f4affae4fad4..72d9aa6fb50c3 100644
+--- a/kernel/kcov.c
++++ b/kernel/kcov.c
+@@ -161,6 +161,15 @@ static void kcov_remote_area_put(struct kcov_remote_area *area,
+ 	kmsan_unpoison_memory(&area->list, sizeof(area->list));
+ }
+ 
++/*
++ * Unlike in_serving_softirq(), this function returns false when called during
++ * a hardirq or an NMI that happened in the softirq context.
++ */
++static inline bool in_softirq_really(void)
++{
++	return in_serving_softirq() && !in_hardirq() && !in_nmi();
++}
++
+ static notrace bool check_kcov_mode(enum kcov_mode needed_mode, struct task_struct *t)
+ {
+ 	unsigned int mode;
+@@ -170,7 +179,7 @@ static notrace bool check_kcov_mode(enum kcov_mode needed_mode, struct task_stru
+ 	 * so we ignore code executed in interrupts, unless we are in a remote
+ 	 * coverage collection section in a softirq.
+ 	 */
+-	if (!in_task() && !(in_serving_softirq() && t->kcov_softirq))
++	if (!in_task() && !(in_softirq_really() && t->kcov_softirq))
+ 		return false;
+ 	mode = READ_ONCE(t->kcov_mode);
+ 	/*
+@@ -848,7 +857,7 @@ void kcov_remote_start(u64 handle)
+ 
+ 	if (WARN_ON(!kcov_check_handle(handle, true, true, true)))
+ 		return;
+-	if (!in_task() && !in_serving_softirq())
++	if (!in_task() && !in_softirq_really())
+ 		return;
+ 
+ 	local_lock_irqsave(&kcov_percpu_data.lock, flags);
+@@ -990,7 +999,7 @@ void kcov_remote_stop(void)
+ 	int sequence;
+ 	unsigned long flags;
+ 
+-	if (!in_task() && !in_serving_softirq())
++	if (!in_task() && !in_softirq_really())
+ 		return;
+ 
+ 	local_lock_irqsave(&kcov_percpu_data.lock, flags);
+diff --git a/kernel/kprobes.c b/kernel/kprobes.c
+index add63428c0b40..c10954bd84448 100644
+--- a/kernel/kprobes.c
++++ b/kernel/kprobes.c
+@@ -1558,8 +1558,8 @@ static bool is_cfi_preamble_symbol(unsigned long addr)
+ 	if (lookup_symbol_name(addr, symbuf))
+ 		return false;
+ 
+-	return str_has_prefix("__cfi_", symbuf) ||
+-		str_has_prefix("__pfx_", symbuf);
++	return str_has_prefix(symbuf, "__cfi_") ||
++		str_has_prefix(symbuf, "__pfx_");
+ }
+ 
+ static int check_kprobe_address_safe(struct kprobe *p,
+diff --git a/kernel/module/main.c b/kernel/module/main.c
+index 34d9e718c2c7d..b00e31721a73e 100644
+--- a/kernel/module/main.c
++++ b/kernel/module/main.c
+@@ -3081,7 +3081,7 @@ static bool idempotent(struct idempotent *u, const void *cookie)
+ 	struct idempotent *existing;
+ 	bool first;
+ 
+-	u->ret = 0;
++	u->ret = -EINTR;
+ 	u->cookie = cookie;
+ 	init_completion(&u->complete);
+ 
+@@ -3117,7 +3117,7 @@ static int idempotent_complete(struct idempotent *u, int ret)
+ 	hlist_for_each_entry_safe(pos, next, head, entry) {
+ 		if (pos->cookie != cookie)
+ 			continue;
+-		hlist_del(&pos->entry);
++		hlist_del_init(&pos->entry);
+ 		pos->ret = ret;
+ 		complete(&pos->complete);
+ 	}
+@@ -3125,6 +3125,28 @@ static int idempotent_complete(struct idempotent *u, int ret)
+ 	return ret;
+ }
+ 
++/*
++ * Wait for the idempotent worker.
++ *
++ * If we get interrupted, we need to remove ourselves from the
++ * the idempotent list, and the completion may still come in.
++ *
++ * The 'idem_lock' protects against the race, and 'idem.ret' was
++ * initialized to -EINTR and is thus always the right return
++ * value even if the idempotent work then completes between
++ * the wait_for_completion and the cleanup.
++ */
++static int idempotent_wait_for_completion(struct idempotent *u)
++{
++	if (wait_for_completion_interruptible(&u->complete)) {
++		spin_lock(&idem_lock);
++		if (!hlist_unhashed(&u->entry))
++			hlist_del(&u->entry);
++		spin_unlock(&idem_lock);
++	}
++	return u->ret;
++}
++
+ static int init_module_from_file(struct file *f, const char __user * uargs, int flags)
+ {
+ 	struct load_info info = { };
+@@ -3160,15 +3182,16 @@ static int idempotent_init_module(struct file *f, const char __user * uargs, int
+ 	if (!f || !(f->f_mode & FMODE_READ))
+ 		return -EBADF;
+ 
+-	/* See if somebody else is doing the operation? */
+-	if (idempotent(&idem, file_inode(f))) {
+-		wait_for_completion(&idem.complete);
+-		return idem.ret;
++	/* Are we the winners of the race and get to do this? */
++	if (!idempotent(&idem, file_inode(f))) {
++		int ret = init_module_from_file(f, uargs, flags);
++		return idempotent_complete(&idem, ret);
+ 	}
+ 
+-	/* Otherwise, we'll do it and complete others */
+-	return idempotent_complete(&idem,
+-		init_module_from_file(f, uargs, flags));
++	/*
++	 * Somebody else won the race and is loading the module.
++	 */
++	return idempotent_wait_for_completion(&idem);
+ }
+ 
+ SYSCALL_DEFINE3(finit_module, int, fd, const char __user *, uargs, int, flags)
+diff --git a/kernel/padata.c b/kernel/padata.c
+index c974568f65f5d..29545dd6dd53d 100644
+--- a/kernel/padata.c
++++ b/kernel/padata.c
+@@ -516,6 +516,13 @@ void __init padata_do_multithreaded(struct padata_mt_job *job)
+ 	ps.chunk_size = max(ps.chunk_size, job->min_chunk);
+ 	ps.chunk_size = roundup(ps.chunk_size, job->align);
+ 
++	/*
++	 * chunk_size can be 0 if the caller sets min_chunk to 0. So force it
++	 * to at least 1 to prevent divide-by-0 panic in padata_mt_helper().`
++	 */
++	if (!ps.chunk_size)
++		ps.chunk_size = 1U;
++
+ 	list_for_each_entry(pw, &works, pw_list)
+ 		queue_work(system_unbound_wq, &pw->pw_work);
+ 
+diff --git a/kernel/profile.c b/kernel/profile.c
+index 8a77769bc4b4c..984f819b701c9 100644
+--- a/kernel/profile.c
++++ b/kernel/profile.c
+@@ -57,20 +57,11 @@ static DEFINE_MUTEX(profile_flip_mutex);
+ int profile_setup(char *str)
+ {
+ 	static const char schedstr[] = "schedule";
+-	static const char sleepstr[] = "sleep";
+ 	static const char kvmstr[] = "kvm";
+ 	const char *select = NULL;
+ 	int par;
+ 
+-	if (!strncmp(str, sleepstr, strlen(sleepstr))) {
+-#ifdef CONFIG_SCHEDSTATS
+-		force_schedstat_enabled();
+-		prof_on = SLEEP_PROFILING;
+-		select = sleepstr;
+-#else
+-		pr_warn("kernel sleep profiling requires CONFIG_SCHEDSTATS\n");
+-#endif /* CONFIG_SCHEDSTATS */
+-	} else if (!strncmp(str, schedstr, strlen(schedstr))) {
++	if (!strncmp(str, schedstr, strlen(schedstr))) {
+ 		prof_on = SCHED_PROFILING;
+ 		select = schedstr;
+ 	} else if (!strncmp(str, kvmstr, strlen(kvmstr))) {
+diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c
+index 781146600aa49..46612fb15fc6d 100644
+--- a/kernel/rcu/rcutorture.c
++++ b/kernel/rcu/rcutorture.c
+@@ -2592,7 +2592,7 @@ static void rcu_torture_fwd_cb_cr(struct rcu_head *rhp)
+ 	spin_lock_irqsave(&rfp->rcu_fwd_lock, flags);
+ 	rfcpp = rfp->rcu_fwd_cb_tail;
+ 	rfp->rcu_fwd_cb_tail = &rfcp->rfc_next;
+-	WRITE_ONCE(*rfcpp, rfcp);
++	smp_store_release(rfcpp, rfcp);
+ 	WRITE_ONCE(rfp->n_launders_cb, rfp->n_launders_cb + 1);
+ 	i = ((jiffies - rfp->rcu_fwd_startat) / (HZ / FWD_CBS_HIST_DIV));
+ 	if (i >= ARRAY_SIZE(rfp->n_launders_hist))
+diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c
+index 8cf6a6fef7965..583cc29080764 100644
+--- a/kernel/rcu/tree.c
++++ b/kernel/rcu/tree.c
+@@ -4595,11 +4595,15 @@ void rcutree_migrate_callbacks(int cpu)
+ 	struct rcu_data *rdp = per_cpu_ptr(&rcu_data, cpu);
+ 	bool needwake;
+ 
+-	if (rcu_rdp_is_offloaded(rdp) ||
+-	    rcu_segcblist_empty(&rdp->cblist))
+-		return;  /* No callbacks to migrate. */
++	if (rcu_rdp_is_offloaded(rdp))
++		return;
+ 
+ 	raw_spin_lock_irqsave(&rcu_state.barrier_lock, flags);
++	if (rcu_segcblist_empty(&rdp->cblist)) {
++		raw_spin_unlock_irqrestore(&rcu_state.barrier_lock, flags);
++		return;  /* No callbacks to migrate. */
++	}
++
+ 	WARN_ON_ONCE(rcu_rdp_cpu_online(rdp));
+ 	rcu_barrier_entrain(rdp);
+ 	my_rdp = this_cpu_ptr(&rcu_data);
+diff --git a/kernel/sched/core.c b/kernel/sched/core.c
+index 92e4afeb71add..97571d390f184 100644
+--- a/kernel/sched/core.c
++++ b/kernel/sched/core.c
+@@ -9596,6 +9596,30 @@ void set_rq_offline(struct rq *rq)
+ 	}
+ }
+ 
++static inline void sched_set_rq_online(struct rq *rq, int cpu)
++{
++	struct rq_flags rf;
++
++	rq_lock_irqsave(rq, &rf);
++	if (rq->rd) {
++		BUG_ON(!cpumask_test_cpu(cpu, rq->rd->span));
++		set_rq_online(rq);
++	}
++	rq_unlock_irqrestore(rq, &rf);
++}
++
++static inline void sched_set_rq_offline(struct rq *rq, int cpu)
++{
++	struct rq_flags rf;
++
++	rq_lock_irqsave(rq, &rf);
++	if (rq->rd) {
++		BUG_ON(!cpumask_test_cpu(cpu, rq->rd->span));
++		set_rq_offline(rq);
++	}
++	rq_unlock_irqrestore(rq, &rf);
++}
++
+ /*
+  * used to mark begin/end of suspend/resume:
+  */
+@@ -9646,10 +9670,25 @@ static int cpuset_cpu_inactive(unsigned int cpu)
+ 	return 0;
+ }
+ 
++static inline void sched_smt_present_inc(int cpu)
++{
++#ifdef CONFIG_SCHED_SMT
++	if (cpumask_weight(cpu_smt_mask(cpu)) == 2)
++		static_branch_inc_cpuslocked(&sched_smt_present);
++#endif
++}
++
++static inline void sched_smt_present_dec(int cpu)
++{
++#ifdef CONFIG_SCHED_SMT
++	if (cpumask_weight(cpu_smt_mask(cpu)) == 2)
++		static_branch_dec_cpuslocked(&sched_smt_present);
++#endif
++}
++
+ int sched_cpu_activate(unsigned int cpu)
+ {
+ 	struct rq *rq = cpu_rq(cpu);
+-	struct rq_flags rf;
+ 
+ 	/*
+ 	 * Clear the balance_push callback and prepare to schedule
+@@ -9657,13 +9696,10 @@ int sched_cpu_activate(unsigned int cpu)
+ 	 */
+ 	balance_push_set(cpu, false);
+ 
+-#ifdef CONFIG_SCHED_SMT
+ 	/*
+ 	 * When going up, increment the number of cores with SMT present.
+ 	 */
+-	if (cpumask_weight(cpu_smt_mask(cpu)) == 2)
+-		static_branch_inc_cpuslocked(&sched_smt_present);
+-#endif
++	sched_smt_present_inc(cpu);
+ 	set_cpu_active(cpu, true);
+ 
+ 	if (sched_smp_initialized) {
+@@ -9681,12 +9717,7 @@ int sched_cpu_activate(unsigned int cpu)
+ 	 * 2) At runtime, if cpuset_cpu_active() fails to rebuild the
+ 	 *    domains.
+ 	 */
+-	rq_lock_irqsave(rq, &rf);
+-	if (rq->rd) {
+-		BUG_ON(!cpumask_test_cpu(cpu, rq->rd->span));
+-		set_rq_online(rq);
+-	}
+-	rq_unlock_irqrestore(rq, &rf);
++	sched_set_rq_online(rq, cpu);
+ 
+ 	return 0;
+ }
+@@ -9694,7 +9725,6 @@ int sched_cpu_activate(unsigned int cpu)
+ int sched_cpu_deactivate(unsigned int cpu)
+ {
+ 	struct rq *rq = cpu_rq(cpu);
+-	struct rq_flags rf;
+ 	int ret;
+ 
+ 	/*
+@@ -9725,20 +9755,14 @@ int sched_cpu_deactivate(unsigned int cpu)
+ 	 */
+ 	synchronize_rcu();
+ 
+-	rq_lock_irqsave(rq, &rf);
+-	if (rq->rd) {
+-		BUG_ON(!cpumask_test_cpu(cpu, rq->rd->span));
+-		set_rq_offline(rq);
+-	}
+-	rq_unlock_irqrestore(rq, &rf);
++	sched_set_rq_offline(rq, cpu);
+ 
+-#ifdef CONFIG_SCHED_SMT
+ 	/*
+ 	 * When going down, decrement the number of cores with SMT present.
+ 	 */
+-	if (cpumask_weight(cpu_smt_mask(cpu)) == 2)
+-		static_branch_dec_cpuslocked(&sched_smt_present);
++	sched_smt_present_dec(cpu);
+ 
++#ifdef CONFIG_SCHED_SMT
+ 	sched_core_cpu_deactivate(cpu);
+ #endif
+ 
+@@ -9748,6 +9772,8 @@ int sched_cpu_deactivate(unsigned int cpu)
+ 	sched_update_numa(cpu, false);
+ 	ret = cpuset_cpu_inactive(cpu);
+ 	if (ret) {
++		sched_smt_present_inc(cpu);
++		sched_set_rq_online(rq, cpu);
+ 		balance_push_set(cpu, false);
+ 		set_cpu_active(cpu, true);
+ 		sched_update_numa(cpu, true);
+diff --git a/kernel/sched/cputime.c b/kernel/sched/cputime.c
+index af7952f12e6cf..b453f8a6a7c76 100644
+--- a/kernel/sched/cputime.c
++++ b/kernel/sched/cputime.c
+@@ -595,6 +595,12 @@ void cputime_adjust(struct task_cputime *curr, struct prev_cputime *prev,
+ 	}
+ 
+ 	stime = mul_u64_u64_div_u64(stime, rtime, stime + utime);
++	/*
++	 * Because mul_u64_u64_div_u64() can approximate on some
++	 * achitectures; enforce the constraint that: a*b/(b+c) <= a.
++	 */
++	if (unlikely(stime > rtime))
++		stime = rtime;
+ 
+ update:
+ 	/*
+diff --git a/kernel/sched/stats.c b/kernel/sched/stats.c
+index 857f837f52cbe..966f4eacfe51d 100644
+--- a/kernel/sched/stats.c
++++ b/kernel/sched/stats.c
+@@ -92,16 +92,6 @@ void __update_stats_enqueue_sleeper(struct rq *rq, struct task_struct *p,
+ 
+ 			trace_sched_stat_blocked(p, delta);
+ 
+-			/*
+-			 * Blocking time is in units of nanosecs, so shift by
+-			 * 20 to get a milliseconds-range estimation of the
+-			 * amount of time that the task spent sleeping:
+-			 */
+-			if (unlikely(prof_on == SLEEP_PROFILING)) {
+-				profile_hits(SLEEP_PROFILING,
+-					     (void *)get_wchan(p),
+-					     delta >> 20);
+-			}
+ 			account_scheduler_latency(p, delta >> 10, 0);
+ 		}
+ 	}
+diff --git a/kernel/time/clocksource-wdtest.c b/kernel/time/clocksource-wdtest.c
+index df922f49d171b..d06185e054ea2 100644
+--- a/kernel/time/clocksource-wdtest.c
++++ b/kernel/time/clocksource-wdtest.c
+@@ -104,8 +104,8 @@ static void wdtest_ktime_clocksource_reset(void)
+ static int wdtest_func(void *arg)
+ {
+ 	unsigned long j1, j2;
++	int i, max_retries;
+ 	char *s;
+-	int i;
+ 
+ 	schedule_timeout_uninterruptible(holdoff * HZ);
+ 
+@@ -139,18 +139,19 @@ static int wdtest_func(void *arg)
+ 	WARN_ON_ONCE(time_before(j2, j1 + NSEC_PER_USEC));
+ 
+ 	/* Verify tsc-like stability with various numbers of errors injected. */
+-	for (i = 0; i <= max_cswd_read_retries + 1; i++) {
+-		if (i <= 1 && i < max_cswd_read_retries)
++	max_retries = clocksource_get_max_watchdog_retry();
++	for (i = 0; i <= max_retries + 1; i++) {
++		if (i <= 1 && i < max_retries)
+ 			s = "";
+-		else if (i <= max_cswd_read_retries)
++		else if (i <= max_retries)
+ 			s = ", expect message";
+ 		else
+ 			s = ", expect clock skew";
+-		pr_info("--- Watchdog with %dx error injection, %lu retries%s.\n", i, max_cswd_read_retries, s);
++		pr_info("--- Watchdog with %dx error injection, %d retries%s.\n", i, max_retries, s);
+ 		WRITE_ONCE(wdtest_ktime_read_ndelays, i);
+ 		schedule_timeout_uninterruptible(2 * HZ);
+ 		WARN_ON_ONCE(READ_ONCE(wdtest_ktime_read_ndelays));
+-		WARN_ON_ONCE((i <= max_cswd_read_retries) !=
++		WARN_ON_ONCE((i <= max_retries) !=
+ 			     !(clocksource_wdtest_ktime.flags & CLOCK_SOURCE_UNSTABLE));
+ 		wdtest_ktime_clocksource_reset();
+ 	}
+diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c
+index 3052b1f1168e2..3260bbe98894b 100644
+--- a/kernel/time/clocksource.c
++++ b/kernel/time/clocksource.c
+@@ -210,9 +210,6 @@ void clocksource_mark_unstable(struct clocksource *cs)
+ 	spin_unlock_irqrestore(&watchdog_lock, flags);
+ }
+ 
+-ulong max_cswd_read_retries = 2;
+-module_param(max_cswd_read_retries, ulong, 0644);
+-EXPORT_SYMBOL_GPL(max_cswd_read_retries);
+ static int verify_n_cpus = 8;
+ module_param(verify_n_cpus, int, 0644);
+ 
+@@ -224,11 +221,12 @@ enum wd_read_status {
+ 
+ static enum wd_read_status cs_watchdog_read(struct clocksource *cs, u64 *csnow, u64 *wdnow)
+ {
+-	unsigned int nretries;
++	unsigned int nretries, max_retries;
+ 	u64 wd_end, wd_end2, wd_delta;
+ 	int64_t wd_delay, wd_seq_delay;
+ 
+-	for (nretries = 0; nretries <= max_cswd_read_retries; nretries++) {
++	max_retries = clocksource_get_max_watchdog_retry();
++	for (nretries = 0; nretries <= max_retries; nretries++) {
+ 		local_irq_disable();
+ 		*wdnow = watchdog->read(watchdog);
+ 		*csnow = cs->read(cs);
+@@ -240,7 +238,7 @@ static enum wd_read_status cs_watchdog_read(struct clocksource *cs, u64 *csnow,
+ 		wd_delay = clocksource_cyc2ns(wd_delta, watchdog->mult,
+ 					      watchdog->shift);
+ 		if (wd_delay <= WATCHDOG_MAX_SKEW) {
+-			if (nretries > 1 || nretries >= max_cswd_read_retries) {
++			if (nretries > 1 && nretries >= max_retries) {
+ 				pr_warn("timekeeping watchdog on CPU%d: %s retried %d times before success\n",
+ 					smp_processor_id(), watchdog->name, nretries);
+ 			}
+diff --git a/kernel/time/ntp.c b/kernel/time/ntp.c
+index 406dccb79c2b6..8d2dd214ec682 100644
+--- a/kernel/time/ntp.c
++++ b/kernel/time/ntp.c
+@@ -727,17 +727,16 @@ static inline void process_adjtimex_modes(const struct __kernel_timex *txc,
+ 	}
+ 
+ 	if (txc->modes & ADJ_MAXERROR)
+-		time_maxerror = txc->maxerror;
++		time_maxerror = clamp(txc->maxerror, 0, NTP_PHASE_LIMIT);
+ 
+ 	if (txc->modes & ADJ_ESTERROR)
+-		time_esterror = txc->esterror;
++		time_esterror = clamp(txc->esterror, 0, NTP_PHASE_LIMIT);
+ 
+ 	if (txc->modes & ADJ_TIMECONST) {
+-		time_constant = txc->constant;
++		time_constant = clamp(txc->constant, 0, MAXTC);
+ 		if (!(time_status & STA_NANO))
+ 			time_constant += 4;
+-		time_constant = min(time_constant, (long)MAXTC);
+-		time_constant = max(time_constant, 0l);
++		time_constant = clamp(time_constant, 0, MAXTC);
+ 	}
+ 
+ 	if (txc->modes & ADJ_TAI &&
+diff --git a/kernel/time/tick-broadcast.c b/kernel/time/tick-broadcast.c
+index b4843099a8da7..ed58eebb4e8f4 100644
+--- a/kernel/time/tick-broadcast.c
++++ b/kernel/time/tick-broadcast.c
+@@ -1141,7 +1141,6 @@ void tick_broadcast_switch_to_oneshot(void)
+ #ifdef CONFIG_HOTPLUG_CPU
+ void hotplug_cpu__broadcast_tick_pull(int deadcpu)
+ {
+-	struct tick_device *td = this_cpu_ptr(&tick_cpu_device);
+ 	struct clock_event_device *bc;
+ 	unsigned long flags;
+ 
+@@ -1167,6 +1166,8 @@ void hotplug_cpu__broadcast_tick_pull(int deadcpu)
+ 		 * device to avoid the starvation.
+ 		 */
+ 		if (tick_check_broadcast_expired()) {
++			struct tick_device *td = this_cpu_ptr(&tick_cpu_device);
++
+ 			cpumask_clear_cpu(smp_processor_id(), tick_broadcast_force_mask);
+ 			tick_program_event(td->evtdev->next_event, 1);
+ 		}
+diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c
+index 8aab7ed414907..11b7000d5e1d4 100644
+--- a/kernel/time/timekeeping.c
++++ b/kernel/time/timekeeping.c
+@@ -2476,7 +2476,7 @@ int do_adjtimex(struct __kernel_timex *txc)
+ 		clock_set |= timekeeping_advance(TK_ADV_FREQ);
+ 
+ 	if (clock_set)
+-		clock_was_set(CLOCK_REALTIME);
++		clock_was_set(CLOCK_SET_WALL);
+ 
+ 	ntp_notify_cmos_timer();
+ 
+diff --git a/kernel/trace/tracing_map.c b/kernel/trace/tracing_map.c
+index a4dcf0f243521..3a56e7c8aa4f6 100644
+--- a/kernel/trace/tracing_map.c
++++ b/kernel/trace/tracing_map.c
+@@ -454,7 +454,7 @@ static struct tracing_map_elt *get_free_elt(struct tracing_map *map)
+ 	struct tracing_map_elt *elt = NULL;
+ 	int idx;
+ 
+-	idx = atomic_inc_return(&map->next_elt);
++	idx = atomic_fetch_add_unless(&map->next_elt, 1, map->max_elts);
+ 	if (idx < map->max_elts) {
+ 		elt = *(TRACING_MAP_ELT(map->elts, idx));
+ 		if (map->ops && map->ops->elt_init)
+@@ -699,7 +699,7 @@ void tracing_map_clear(struct tracing_map *map)
+ {
+ 	unsigned int i;
+ 
+-	atomic_set(&map->next_elt, -1);
++	atomic_set(&map->next_elt, 0);
+ 	atomic64_set(&map->hits, 0);
+ 	atomic64_set(&map->drops, 0);
+ 
+@@ -783,7 +783,7 @@ struct tracing_map *tracing_map_create(unsigned int map_bits,
+ 
+ 	map->map_bits = map_bits;
+ 	map->max_elts = (1 << map_bits);
+-	atomic_set(&map->next_elt, -1);
++	atomic_set(&map->next_elt, 0);
+ 
+ 	map->map_size = (1 << (map_bits + 1));
+ 	map->ops = ops;
+diff --git a/mm/huge_memory.c b/mm/huge_memory.c
+index 79fbd6ddec49f..7ac2877e76629 100644
+--- a/mm/huge_memory.c
++++ b/mm/huge_memory.c
+@@ -37,6 +37,7 @@
+ #include <linux/page_owner.h>
+ #include <linux/sched/sysctl.h>
+ #include <linux/memory-tiers.h>
++#include <linux/compat.h>
+ 
+ #include <asm/tlb.h>
+ #include <asm/pgalloc.h>
+@@ -601,6 +602,9 @@ static unsigned long __thp_get_unmapped_area(struct file *filp,
+ 	loff_t off_align = round_up(off, size);
+ 	unsigned long len_pad, ret;
+ 
++	if (!IS_ENABLED(CONFIG_64BIT) || in_compat_syscall())
++		return 0;
++
+ 	if (off_end <= off_align || (off_end - off_align) < size)
+ 		return 0;
+ 
+diff --git a/mm/hugetlb.c b/mm/hugetlb.c
+index a480affd475bf..fb7a531fce717 100644
+--- a/mm/hugetlb.c
++++ b/mm/hugetlb.c
+@@ -1769,13 +1769,6 @@ static void __update_and_free_hugetlb_folio(struct hstate *h,
+ 		return;
+ 	}
+ 
+-	/*
+-	 * Move PageHWPoison flag from head page to the raw error pages,
+-	 * which makes any healthy subpages reusable.
+-	 */
+-	if (unlikely(folio_test_hwpoison(folio)))
+-		folio_clear_hugetlb_hwpoison(folio);
+-
+ 	/*
+ 	 * If vmemmap pages were allocated above, then we need to clear the
+ 	 * hugetlb destructor under the hugetlb lock.
+@@ -1786,6 +1779,13 @@ static void __update_and_free_hugetlb_folio(struct hstate *h,
+ 		spin_unlock_irq(&hugetlb_lock);
+ 	}
+ 
++	/*
++	 * Move PageHWPoison flag from head page to the raw error pages,
++	 * which makes any healthy subpages reusable.
++	 */
++	if (unlikely(folio_test_hwpoison(folio)))
++		folio_clear_hugetlb_hwpoison(folio);
++
+ 	/*
+ 	 * Non-gigantic pages demoted from CMA allocated gigantic pages
+ 	 * need to be given back to CMA in free_gigantic_folio.
+diff --git a/mm/memcontrol.c b/mm/memcontrol.c
+index dd854cc65fd9d..fd1b707f5de40 100644
+--- a/mm/memcontrol.c
++++ b/mm/memcontrol.c
+@@ -5167,11 +5167,28 @@ static struct cftype mem_cgroup_legacy_files[] = {
+ 
+ #define MEM_CGROUP_ID_MAX	((1UL << MEM_CGROUP_ID_SHIFT) - 1)
+ static DEFINE_IDR(mem_cgroup_idr);
++static DEFINE_SPINLOCK(memcg_idr_lock);
++
++static int mem_cgroup_alloc_id(void)
++{
++	int ret;
++
++	idr_preload(GFP_KERNEL);
++	spin_lock(&memcg_idr_lock);
++	ret = idr_alloc(&mem_cgroup_idr, NULL, 1, MEM_CGROUP_ID_MAX + 1,
++			GFP_NOWAIT);
++	spin_unlock(&memcg_idr_lock);
++	idr_preload_end();
++	return ret;
++}
+ 
+ static void mem_cgroup_id_remove(struct mem_cgroup *memcg)
+ {
+ 	if (memcg->id.id > 0) {
++		spin_lock(&memcg_idr_lock);
+ 		idr_remove(&mem_cgroup_idr, memcg->id.id);
++		spin_unlock(&memcg_idr_lock);
++
+ 		memcg->id.id = 0;
+ 	}
+ }
+@@ -5294,8 +5311,7 @@ static struct mem_cgroup *mem_cgroup_alloc(void)
+ 	if (!memcg)
+ 		return ERR_PTR(error);
+ 
+-	memcg->id.id = idr_alloc(&mem_cgroup_idr, NULL,
+-				 1, MEM_CGROUP_ID_MAX + 1, GFP_KERNEL);
++	memcg->id.id = mem_cgroup_alloc_id();
+ 	if (memcg->id.id < 0) {
+ 		error = memcg->id.id;
+ 		goto fail;
+@@ -5430,7 +5446,9 @@ static int mem_cgroup_css_online(struct cgroup_subsys_state *css)
+ 	 * publish it here at the end of onlining. This matches the
+ 	 * regular ID destruction during offlining.
+ 	 */
++	spin_lock(&memcg_idr_lock);
+ 	idr_replace(&mem_cgroup_idr, memcg, memcg->id.id);
++	spin_unlock(&memcg_idr_lock);
+ 
+ 	return 0;
+ offline_kmem:
+diff --git a/net/bluetooth/hci_sync.c b/net/bluetooth/hci_sync.c
+index 6dab0c99c82c7..38fee34887d8a 100644
+--- a/net/bluetooth/hci_sync.c
++++ b/net/bluetooth/hci_sync.c
+@@ -2905,6 +2905,20 @@ static int hci_passive_scan_sync(struct hci_dev *hdev)
+ 	} else if (hci_is_adv_monitoring(hdev)) {
+ 		window = hdev->le_scan_window_adv_monitor;
+ 		interval = hdev->le_scan_int_adv_monitor;
++
++		/* Disable duplicates filter when scanning for advertisement
++		 * monitor for the following reasons.
++		 *
++		 * For HW pattern filtering (ex. MSFT), Realtek and Qualcomm
++		 * controllers ignore RSSI_Sampling_Period when the duplicates
++		 * filter is enabled.
++		 *
++		 * For SW pattern filtering, when we're not doing interleaved
++		 * scanning, it is necessary to disable duplicates filter,
++		 * otherwise hosts can only receive one advertisement and it's
++		 * impossible to know if a peer is still in range.
++		 */
++		filter_dups = LE_SCAN_FILTER_DUP_DISABLE;
+ 	} else {
+ 		window = hdev->le_scan_window;
+ 		interval = hdev->le_scan_interval;
+diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
+index 1164c6d927281..2651cc2d5c283 100644
+--- a/net/bluetooth/l2cap_core.c
++++ b/net/bluetooth/l2cap_core.c
+@@ -6775,6 +6775,7 @@ static void l2cap_conless_channel(struct l2cap_conn *conn, __le16 psm,
+ 	bt_cb(skb)->l2cap.psm = psm;
+ 
+ 	if (!chan->ops->recv(chan, skb)) {
++		l2cap_chan_unlock(chan);
+ 		l2cap_chan_put(chan);
+ 		return;
+ 	}
+diff --git a/net/bridge/br_multicast.c b/net/bridge/br_multicast.c
+index 38373b4fb7ddf..c38244d60ff86 100644
+--- a/net/bridge/br_multicast.c
++++ b/net/bridge/br_multicast.c
+@@ -2044,16 +2044,14 @@ void br_multicast_del_port(struct net_bridge_port *port)
+ {
+ 	struct net_bridge *br = port->br;
+ 	struct net_bridge_port_group *pg;
+-	HLIST_HEAD(deleted_head);
+ 	struct hlist_node *n;
+ 
+ 	/* Take care of the remaining groups, only perm ones should be left */
+ 	spin_lock_bh(&br->multicast_lock);
+ 	hlist_for_each_entry_safe(pg, n, &port->mglist, mglist)
+ 		br_multicast_find_del_pg(br, pg);
+-	hlist_move_list(&br->mcast_gc_list, &deleted_head);
+ 	spin_unlock_bh(&br->multicast_lock);
+-	br_multicast_gc(&deleted_head);
++	flush_work(&br->mcast_gc_work);
+ 	br_multicast_port_ctx_deinit(&port->multicast_ctx);
+ 	free_percpu(port->mcast_stats);
+ }
+diff --git a/net/core/link_watch.c b/net/core/link_watch.c
+index cb43f5aebfbcc..cf867f6e38bf1 100644
+--- a/net/core/link_watch.c
++++ b/net/core/link_watch.c
+@@ -153,9 +153,9 @@ static void linkwatch_schedule_work(int urgent)
+ 	 * override the existing timer.
+ 	 */
+ 	if (test_bit(LW_URGENT, &linkwatch_flags))
+-		mod_delayed_work(system_wq, &linkwatch_work, 0);
++		mod_delayed_work(system_unbound_wq, &linkwatch_work, 0);
+ 	else
+-		schedule_delayed_work(&linkwatch_work, delay);
++		queue_delayed_work(system_unbound_wq, &linkwatch_work, delay);
+ }
+ 
+ 
+diff --git a/net/ipv4/tcp_offload.c b/net/ipv4/tcp_offload.c
+index 8311c38267b55..69e6012ae82fb 100644
+--- a/net/ipv4/tcp_offload.c
++++ b/net/ipv4/tcp_offload.c
+@@ -73,6 +73,9 @@ struct sk_buff *tcp_gso_segment(struct sk_buff *skb,
+ 	if (thlen < sizeof(*th))
+ 		goto out;
+ 
++	if (unlikely(skb_checksum_start(skb) != skb_transport_header(skb)))
++		goto out;
++
+ 	if (!pskb_may_pull(skb, thlen))
+ 		goto out;
+ 
+diff --git a/net/ipv4/udp_offload.c b/net/ipv4/udp_offload.c
+index e5971890d637d..9cb13a50011ef 100644
+--- a/net/ipv4/udp_offload.c
++++ b/net/ipv4/udp_offload.c
+@@ -278,6 +278,10 @@ struct sk_buff *__udp_gso_segment(struct sk_buff *gso_skb,
+ 	if (gso_skb->len <= sizeof(*uh) + mss)
+ 		return ERR_PTR(-EINVAL);
+ 
++	if (unlikely(skb_checksum_start(gso_skb) !=
++		     skb_transport_header(gso_skb)))
++		return ERR_PTR(-EINVAL);
++
+ 	if (skb_gso_ok(gso_skb, features | NETIF_F_GSO_ROBUST)) {
+ 		/* Packet is from an untrusted source, reset gso_segs. */
+ 		skb_shinfo(gso_skb)->gso_segs = DIV_ROUND_UP(gso_skb->len - sizeof(*uh),
+diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c
+index f97cb368e5a81..db8d0e1bf69ff 100644
+--- a/net/ipv6/ip6_output.c
++++ b/net/ipv6/ip6_output.c
+@@ -1122,6 +1122,7 @@ static int ip6_dst_lookup_tail(struct net *net, const struct sock *sk,
+ 		from = rt ? rcu_dereference(rt->from) : NULL;
+ 		err = ip6_route_get_saddr(net, from, &fl6->daddr,
+ 					  sk ? inet6_sk(sk)->srcprefs : 0,
++					  fl6->flowi6_l3mdev,
+ 					  &fl6->saddr);
+ 		rcu_read_unlock();
+ 
+diff --git a/net/ipv6/route.c b/net/ipv6/route.c
+index eb3afaee62e8f..49ef5623c55e2 100644
+--- a/net/ipv6/route.c
++++ b/net/ipv6/route.c
+@@ -5678,7 +5678,7 @@ static int rt6_fill_node(struct net *net, struct sk_buff *skb,
+ 				goto nla_put_failure;
+ 	} else if (dest) {
+ 		struct in6_addr saddr_buf;
+-		if (ip6_route_get_saddr(net, rt, dest, 0, &saddr_buf) == 0 &&
++		if (ip6_route_get_saddr(net, rt, dest, 0, 0, &saddr_buf) == 0 &&
+ 		    nla_put_in6_addr(skb, RTA_PREFSRC, &saddr_buf))
+ 			goto nla_put_failure;
+ 	}
+diff --git a/net/l2tp/l2tp_core.c b/net/l2tp/l2tp_core.c
+index 8d21ff25f1602..70da78ab95202 100644
+--- a/net/l2tp/l2tp_core.c
++++ b/net/l2tp/l2tp_core.c
+@@ -88,6 +88,11 @@
+ /* Default trace flags */
+ #define L2TP_DEFAULT_DEBUG_FLAGS	0
+ 
++#define L2TP_DEPTH_NESTING		2
++#if L2TP_DEPTH_NESTING == SINGLE_DEPTH_NESTING
++#error "L2TP requires its own lockdep subclass"
++#endif
++
+ /* Private data stored for received packets in the skb.
+  */
+ struct l2tp_skb_cb {
+@@ -1041,7 +1046,13 @@ static int l2tp_xmit_core(struct l2tp_session *session, struct sk_buff *skb, uns
+ 	IPCB(skb)->flags &= ~(IPSKB_XFRM_TUNNEL_SIZE | IPSKB_XFRM_TRANSFORMED | IPSKB_REROUTED);
+ 	nf_reset_ct(skb);
+ 
+-	bh_lock_sock_nested(sk);
++	/* L2TP uses its own lockdep subclass to avoid lockdep splats caused by
++	 * nested socket calls on the same lockdep socket class. This can
++	 * happen when data from a user socket is routed over l2tp, which uses
++	 * another userspace socket.
++	 */
++	spin_lock_nested(&sk->sk_lock.slock, L2TP_DEPTH_NESTING);
++
+ 	if (sock_owned_by_user(sk)) {
+ 		kfree_skb(skb);
+ 		ret = NET_XMIT_DROP;
+@@ -1093,7 +1104,7 @@ static int l2tp_xmit_core(struct l2tp_session *session, struct sk_buff *skb, uns
+ 	ret = l2tp_xmit_queue(tunnel, skb, &inet->cork.fl);
+ 
+ out_unlock:
+-	bh_unlock_sock(sk);
++	spin_unlock(&sk->sk_lock.slock);
+ 
+ 	return ret;
+ }
+diff --git a/net/mptcp/options.c b/net/mptcp/options.c
+index 85aafa94cc8ab..604724cca887f 100644
+--- a/net/mptcp/options.c
++++ b/net/mptcp/options.c
+@@ -958,7 +958,8 @@ static bool check_fully_established(struct mptcp_sock *msk, struct sock *ssk,
+ 
+ 	if (subflow->remote_key_valid &&
+ 	    (((mp_opt->suboptions & OPTION_MPTCP_DSS) && mp_opt->use_ack) ||
+-	     ((mp_opt->suboptions & OPTION_MPTCP_ADD_ADDR) && !mp_opt->echo))) {
++	     ((mp_opt->suboptions & OPTION_MPTCP_ADD_ADDR) &&
++	      (!mp_opt->echo || subflow->mp_join)))) {
+ 		/* subflows are fully established as soon as we get any
+ 		 * additional ack, including ADD_ADDR.
+ 		 */
+diff --git a/net/mptcp/pm.c b/net/mptcp/pm.c
+index d8da5374d9e13..cf70a376398be 100644
+--- a/net/mptcp/pm.c
++++ b/net/mptcp/pm.c
+@@ -427,6 +427,18 @@ int mptcp_pm_get_local_id(struct mptcp_sock *msk, struct sock_common *skc)
+ 	return mptcp_pm_nl_get_local_id(msk, &skc_local);
+ }
+ 
++bool mptcp_pm_is_backup(struct mptcp_sock *msk, struct sock_common *skc)
++{
++	struct mptcp_addr_info skc_local;
++
++	mptcp_local_address((struct sock_common *)skc, &skc_local);
++
++	if (mptcp_pm_is_userspace(msk))
++		return mptcp_userspace_pm_is_backup(msk, &skc_local);
++
++	return mptcp_pm_nl_is_backup(msk, &skc_local);
++}
++
+ int mptcp_pm_get_flags_and_ifindex_by_id(struct mptcp_sock *msk, unsigned int id,
+ 					 u8 *flags, int *ifindex)
+ {
+diff --git a/net/mptcp/pm_netlink.c b/net/mptcp/pm_netlink.c
+index db621933b2035..2c49182c674f3 100644
+--- a/net/mptcp/pm_netlink.c
++++ b/net/mptcp/pm_netlink.c
+@@ -353,7 +353,7 @@ bool mptcp_pm_alloc_anno_list(struct mptcp_sock *msk,
+ 	add_entry = mptcp_lookup_anno_list_by_saddr(msk, addr);
+ 
+ 	if (add_entry) {
+-		if (mptcp_pm_is_kernel(msk))
++		if (WARN_ON_ONCE(mptcp_pm_is_kernel(msk)))
+ 			return false;
+ 
+ 		sk_reset_timer(sk, &add_entry->add_timer,
+@@ -520,8 +520,8 @@ __lookup_addr(struct pm_nl_pernet *pernet, const struct mptcp_addr_info *info,
+ 
+ static void mptcp_pm_create_subflow_or_signal_addr(struct mptcp_sock *msk)
+ {
++	struct mptcp_pm_addr_entry *local, *signal_and_subflow = NULL;
+ 	struct sock *sk = (struct sock *)msk;
+-	struct mptcp_pm_addr_entry *local;
+ 	unsigned int add_addr_signal_max;
+ 	unsigned int local_addr_max;
+ 	struct pm_nl_pernet *pernet;
+@@ -563,8 +563,6 @@ static void mptcp_pm_create_subflow_or_signal_addr(struct mptcp_sock *msk)
+ 
+ 	/* check first for announce */
+ 	if (msk->pm.add_addr_signaled < add_addr_signal_max) {
+-		local = select_signal_address(pernet, msk);
+-
+ 		/* due to racing events on both ends we can reach here while
+ 		 * previous add address is still running: if we invoke now
+ 		 * mptcp_pm_announce_addr(), that will fail and the
+@@ -575,16 +573,26 @@ static void mptcp_pm_create_subflow_or_signal_addr(struct mptcp_sock *msk)
+ 		if (msk->pm.addr_signal & BIT(MPTCP_ADD_ADDR_SIGNAL))
+ 			return;
+ 
+-		if (local) {
+-			if (mptcp_pm_alloc_anno_list(msk, &local->addr)) {
+-				__clear_bit(local->addr.id, msk->pm.id_avail_bitmap);
+-				msk->pm.add_addr_signaled++;
+-				mptcp_pm_announce_addr(msk, &local->addr, false);
+-				mptcp_pm_nl_addr_send_ack(msk);
+-			}
+-		}
++		local = select_signal_address(pernet, msk);
++		if (!local)
++			goto subflow;
++
++		/* If the alloc fails, we are on memory pressure, not worth
++		 * continuing, and trying to create subflows.
++		 */
++		if (!mptcp_pm_alloc_anno_list(msk, &local->addr))
++			return;
++
++		__clear_bit(local->addr.id, msk->pm.id_avail_bitmap);
++		msk->pm.add_addr_signaled++;
++		mptcp_pm_announce_addr(msk, &local->addr, false);
++		mptcp_pm_nl_addr_send_ack(msk);
++
++		if (local->flags & MPTCP_PM_ADDR_FLAG_SUBFLOW)
++			signal_and_subflow = local;
+ 	}
+ 
++subflow:
+ 	/* check if should create a new subflow */
+ 	while (msk->pm.local_addr_used < local_addr_max &&
+ 	       msk->pm.subflows < subflows_max) {
+@@ -592,9 +600,14 @@ static void mptcp_pm_create_subflow_or_signal_addr(struct mptcp_sock *msk)
+ 		bool fullmesh;
+ 		int i, nr;
+ 
+-		local = select_local_address(pernet, msk);
+-		if (!local)
+-			break;
++		if (signal_and_subflow) {
++			local = signal_and_subflow;
++			signal_and_subflow = NULL;
++		} else {
++			local = select_local_address(pernet, msk);
++			if (!local)
++				break;
++		}
+ 
+ 		fullmesh = !!(local->flags & MPTCP_PM_ADDR_FLAG_FULLMESH);
+ 
+@@ -1109,6 +1122,24 @@ int mptcp_pm_nl_get_local_id(struct mptcp_sock *msk, struct mptcp_addr_info *skc
+ 	return ret;
+ }
+ 
++bool mptcp_pm_nl_is_backup(struct mptcp_sock *msk, struct mptcp_addr_info *skc)
++{
++	struct pm_nl_pernet *pernet = pm_nl_get_pernet_from_msk(msk);
++	struct mptcp_pm_addr_entry *entry;
++	bool backup = false;
++
++	rcu_read_lock();
++	list_for_each_entry_rcu(entry, &pernet->local_addr_list, list) {
++		if (mptcp_addresses_equal(&entry->addr, skc, entry->addr.port)) {
++			backup = !!(entry->flags & MPTCP_PM_ADDR_FLAG_BACKUP);
++			break;
++		}
++	}
++	rcu_read_unlock();
++
++	return backup;
++}
++
+ #define MPTCP_PM_CMD_GRP_OFFSET       0
+ #define MPTCP_PM_EV_GRP_OFFSET        1
+ 
+@@ -1341,8 +1372,8 @@ static int mptcp_nl_cmd_add_addr(struct sk_buff *skb, struct genl_info *info)
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	if (addr.addr.port && !(addr.flags & MPTCP_PM_ADDR_FLAG_SIGNAL)) {
+-		GENL_SET_ERR_MSG(info, "flags must have signal when using port");
++	if (addr.addr.port && !address_use_port(&addr)) {
++		GENL_SET_ERR_MSG(info, "flags must have signal and not subflow when using port");
+ 		return -EINVAL;
+ 	}
+ 
+diff --git a/net/mptcp/pm_userspace.c b/net/mptcp/pm_userspace.c
+index f36f87a62dd0d..6738bad048cec 100644
+--- a/net/mptcp/pm_userspace.c
++++ b/net/mptcp/pm_userspace.c
+@@ -157,6 +157,24 @@ int mptcp_userspace_pm_get_local_id(struct mptcp_sock *msk,
+ 	return mptcp_userspace_pm_append_new_local_addr(msk, &new_entry, true);
+ }
+ 
++bool mptcp_userspace_pm_is_backup(struct mptcp_sock *msk,
++				  struct mptcp_addr_info *skc)
++{
++	struct mptcp_pm_addr_entry *entry;
++	bool backup = false;
++
++	spin_lock_bh(&msk->pm.lock);
++	list_for_each_entry(entry, &msk->pm.userspace_pm_local_addr_list, list) {
++		if (mptcp_addresses_equal(&entry->addr, skc, false)) {
++			backup = !!(entry->flags & MPTCP_PM_ADDR_FLAG_BACKUP);
++			break;
++		}
++	}
++	spin_unlock_bh(&msk->pm.lock);
++
++	return backup;
++}
++
+ int mptcp_nl_cmd_announce(struct sk_buff *skb, struct genl_info *info)
+ {
+ 	struct nlattr *token = info->attrs[MPTCP_PM_ATTR_TOKEN];
+diff --git a/net/mptcp/protocol.h b/net/mptcp/protocol.h
+index c28ac5dfd0b58..0201b1004a3b9 100644
+--- a/net/mptcp/protocol.h
++++ b/net/mptcp/protocol.h
+@@ -1032,6 +1032,9 @@ bool mptcp_pm_rm_addr_signal(struct mptcp_sock *msk, unsigned int remaining,
+ int mptcp_pm_get_local_id(struct mptcp_sock *msk, struct sock_common *skc);
+ int mptcp_pm_nl_get_local_id(struct mptcp_sock *msk, struct mptcp_addr_info *skc);
+ int mptcp_userspace_pm_get_local_id(struct mptcp_sock *msk, struct mptcp_addr_info *skc);
++bool mptcp_pm_is_backup(struct mptcp_sock *msk, struct sock_common *skc);
++bool mptcp_pm_nl_is_backup(struct mptcp_sock *msk, struct mptcp_addr_info *skc);
++bool mptcp_userspace_pm_is_backup(struct mptcp_sock *msk, struct mptcp_addr_info *skc);
+ 
+ static inline u8 subflow_get_local_id(const struct mptcp_subflow_context *subflow)
+ {
+diff --git a/net/mptcp/subflow.c b/net/mptcp/subflow.c
+index bc1efc1787720..927c2d5997dc7 100644
+--- a/net/mptcp/subflow.c
++++ b/net/mptcp/subflow.c
+@@ -100,6 +100,7 @@ static struct mptcp_sock *subflow_token_join_request(struct request_sock *req)
+ 		return NULL;
+ 	}
+ 	subflow_req->local_id = local_id;
++	subflow_req->request_bkup = mptcp_pm_is_backup(msk, (struct sock_common *)req);
+ 
+ 	return msk;
+ }
+@@ -601,6 +602,8 @@ static int subflow_chk_local_id(struct sock *sk)
+ 		return err;
+ 
+ 	subflow_set_local_id(subflow, err);
++	subflow->request_bkup = mptcp_pm_is_backup(msk, (struct sock_common *)sk);
++
+ 	return 0;
+ }
+ 
+diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
+index dd044a47c8723..ea139fca74cb9 100644
+--- a/net/netfilter/nf_tables_api.c
++++ b/net/netfilter/nf_tables_api.c
+@@ -3743,6 +3743,15 @@ static void nf_tables_rule_release(const struct nft_ctx *ctx, struct nft_rule *r
+ 	nf_tables_rule_destroy(ctx, rule);
+ }
+ 
++/** nft_chain_validate - loop detection and hook validation
++ *
++ * @ctx: context containing call depth and base chain
++ * @chain: chain to validate
++ *
++ * Walk through the rules of the given chain and chase all jumps/gotos
++ * and set lookups until either the jump limit is hit or all reachable
++ * chains have been validated.
++ */
+ int nft_chain_validate(const struct nft_ctx *ctx, const struct nft_chain *chain)
+ {
+ 	struct nft_expr *expr, *last;
+@@ -3764,6 +3773,9 @@ int nft_chain_validate(const struct nft_ctx *ctx, const struct nft_chain *chain)
+ 			if (!expr->ops->validate)
+ 				continue;
+ 
++			/* This may call nft_chain_validate() recursively,
++			 * callers that do so must increment ctx->level.
++			 */
+ 			err = expr->ops->validate(ctx, expr, &data);
+ 			if (err < 0)
+ 				return err;
+@@ -10621,146 +10633,6 @@ int nft_chain_validate_hooks(const struct nft_chain *chain,
+ }
+ EXPORT_SYMBOL_GPL(nft_chain_validate_hooks);
+ 
+-/*
+- * Loop detection - walk through the ruleset beginning at the destination chain
+- * of a new jump until either the source chain is reached (loop) or all
+- * reachable chains have been traversed.
+- *
+- * The loop check is performed whenever a new jump verdict is added to an
+- * expression or verdict map or a verdict map is bound to a new chain.
+- */
+-
+-static int nf_tables_check_loops(const struct nft_ctx *ctx,
+-				 const struct nft_chain *chain);
+-
+-static int nft_check_loops(const struct nft_ctx *ctx,
+-			   const struct nft_set_ext *ext)
+-{
+-	const struct nft_data *data;
+-	int ret;
+-
+-	data = nft_set_ext_data(ext);
+-	switch (data->verdict.code) {
+-	case NFT_JUMP:
+-	case NFT_GOTO:
+-		ret = nf_tables_check_loops(ctx, data->verdict.chain);
+-		break;
+-	default:
+-		ret = 0;
+-		break;
+-	}
+-
+-	return ret;
+-}
+-
+-static int nf_tables_loop_check_setelem(const struct nft_ctx *ctx,
+-					struct nft_set *set,
+-					const struct nft_set_iter *iter,
+-					struct nft_set_elem *elem)
+-{
+-	const struct nft_set_ext *ext = nft_set_elem_ext(set, elem->priv);
+-
+-	if (nft_set_ext_exists(ext, NFT_SET_EXT_FLAGS) &&
+-	    *nft_set_ext_flags(ext) & NFT_SET_ELEM_INTERVAL_END)
+-		return 0;
+-
+-	return nft_check_loops(ctx, ext);
+-}
+-
+-static int nft_set_catchall_loops(const struct nft_ctx *ctx,
+-				  struct nft_set *set)
+-{
+-	u8 genmask = nft_genmask_next(ctx->net);
+-	struct nft_set_elem_catchall *catchall;
+-	struct nft_set_ext *ext;
+-	int ret = 0;
+-
+-	list_for_each_entry_rcu(catchall, &set->catchall_list, list) {
+-		ext = nft_set_elem_ext(set, catchall->elem);
+-		if (!nft_set_elem_active(ext, genmask))
+-			continue;
+-
+-		ret = nft_check_loops(ctx, ext);
+-		if (ret < 0)
+-			return ret;
+-	}
+-
+-	return ret;
+-}
+-
+-static int nf_tables_check_loops(const struct nft_ctx *ctx,
+-				 const struct nft_chain *chain)
+-{
+-	const struct nft_rule *rule;
+-	const struct nft_expr *expr, *last;
+-	struct nft_set *set;
+-	struct nft_set_binding *binding;
+-	struct nft_set_iter iter;
+-
+-	if (ctx->chain == chain)
+-		return -ELOOP;
+-
+-	if (fatal_signal_pending(current))
+-		return -EINTR;
+-
+-	list_for_each_entry(rule, &chain->rules, list) {
+-		nft_rule_for_each_expr(expr, last, rule) {
+-			struct nft_immediate_expr *priv;
+-			const struct nft_data *data;
+-			int err;
+-
+-			if (strcmp(expr->ops->type->name, "immediate"))
+-				continue;
+-
+-			priv = nft_expr_priv(expr);
+-			if (priv->dreg != NFT_REG_VERDICT)
+-				continue;
+-
+-			data = &priv->data;
+-			switch (data->verdict.code) {
+-			case NFT_JUMP:
+-			case NFT_GOTO:
+-				err = nf_tables_check_loops(ctx,
+-							data->verdict.chain);
+-				if (err < 0)
+-					return err;
+-				break;
+-			default:
+-				break;
+-			}
+-		}
+-	}
+-
+-	list_for_each_entry(set, &ctx->table->sets, list) {
+-		if (!nft_is_active_next(ctx->net, set))
+-			continue;
+-		if (!(set->flags & NFT_SET_MAP) ||
+-		    set->dtype != NFT_DATA_VERDICT)
+-			continue;
+-
+-		list_for_each_entry(binding, &set->bindings, list) {
+-			if (!(binding->flags & NFT_SET_MAP) ||
+-			    binding->chain != chain)
+-				continue;
+-
+-			iter.genmask	= nft_genmask_next(ctx->net);
+-			iter.skip 	= 0;
+-			iter.count	= 0;
+-			iter.err	= 0;
+-			iter.fn		= nf_tables_loop_check_setelem;
+-
+-			set->ops->walk(ctx, set, &iter);
+-			if (!iter.err)
+-				iter.err = nft_set_catchall_loops(ctx, set);
+-
+-			if (iter.err < 0)
+-				return iter.err;
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+ /**
+  *	nft_parse_u32_check - fetch u32 attribute and check for maximum value
+  *
+@@ -10873,7 +10745,7 @@ static int nft_validate_register_store(const struct nft_ctx *ctx,
+ 		if (data != NULL &&
+ 		    (data->verdict.code == NFT_GOTO ||
+ 		     data->verdict.code == NFT_JUMP)) {
+-			err = nf_tables_check_loops(ctx, data->verdict.chain);
++			err = nft_chain_validate(ctx, data->verdict.chain);
+ 			if (err < 0)
+ 				return err;
+ 		}
+diff --git a/net/sctp/input.c b/net/sctp/input.c
+index 17fcaa9b0df94..a8a254a5008e5 100644
+--- a/net/sctp/input.c
++++ b/net/sctp/input.c
+@@ -735,15 +735,19 @@ static int __sctp_hash_endpoint(struct sctp_endpoint *ep)
+ 	struct sock *sk = ep->base.sk;
+ 	struct net *net = sock_net(sk);
+ 	struct sctp_hashbucket *head;
++	int err = 0;
+ 
+ 	ep->hashent = sctp_ep_hashfn(net, ep->base.bind_addr.port);
+ 	head = &sctp_ep_hashtable[ep->hashent];
+ 
++	write_lock(&head->lock);
+ 	if (sk->sk_reuseport) {
+ 		bool any = sctp_is_ep_boundall(sk);
+ 		struct sctp_endpoint *ep2;
+ 		struct list_head *list;
+-		int cnt = 0, err = 1;
++		int cnt = 0;
++
++		err = 1;
+ 
+ 		list_for_each(list, &ep->base.bind_addr.address_list)
+ 			cnt++;
+@@ -761,24 +765,24 @@ static int __sctp_hash_endpoint(struct sctp_endpoint *ep)
+ 			if (!err) {
+ 				err = reuseport_add_sock(sk, sk2, any);
+ 				if (err)
+-					return err;
++					goto out;
+ 				break;
+ 			} else if (err < 0) {
+-				return err;
++				goto out;
+ 			}
+ 		}
+ 
+ 		if (err) {
+ 			err = reuseport_alloc(sk, any);
+ 			if (err)
+-				return err;
++				goto out;
+ 		}
+ 	}
+ 
+-	write_lock(&head->lock);
+ 	hlist_add_head(&ep->node, &head->chain);
++out:
+ 	write_unlock(&head->lock);
+-	return 0;
++	return err;
+ }
+ 
+ /* Add an endpoint to the hash. Local BH-safe. */
+@@ -803,10 +807,9 @@ static void __sctp_unhash_endpoint(struct sctp_endpoint *ep)
+ 
+ 	head = &sctp_ep_hashtable[ep->hashent];
+ 
++	write_lock(&head->lock);
+ 	if (rcu_access_pointer(sk->sk_reuseport_cb))
+ 		reuseport_detach_sock(sk);
+-
+-	write_lock(&head->lock);
+ 	hlist_del_init(&ep->node);
+ 	write_unlock(&head->lock);
+ }
+diff --git a/net/smc/smc_stats.h b/net/smc/smc_stats.h
+index 9d32058db2b5d..e19177ce40923 100644
+--- a/net/smc/smc_stats.h
++++ b/net/smc/smc_stats.h
+@@ -19,7 +19,7 @@
+ 
+ #include "smc_clc.h"
+ 
+-#define SMC_MAX_FBACK_RSN_CNT 30
++#define SMC_MAX_FBACK_RSN_CNT 36
+ 
+ enum {
+ 	SMC_BUF_8K,
+diff --git a/net/sunrpc/sched.c b/net/sunrpc/sched.c
+index 6debf4fd42d4e..cef623ea15060 100644
+--- a/net/sunrpc/sched.c
++++ b/net/sunrpc/sched.c
+@@ -369,8 +369,10 @@ static void rpc_make_runnable(struct workqueue_struct *wq,
+ 	if (RPC_IS_ASYNC(task)) {
+ 		INIT_WORK(&task->u.tk_work, rpc_async_schedule);
+ 		queue_work(wq, &task->u.tk_work);
+-	} else
++	} else {
++		smp_mb__after_atomic();
+ 		wake_up_bit(&task->tk_runstate, RPC_TASK_QUEUED);
++	}
+ }
+ 
+ /*
+diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c
+index a551be47cb6c6..b7f62442d8268 100644
+--- a/net/unix/af_unix.c
++++ b/net/unix/af_unix.c
+@@ -1483,6 +1483,7 @@ static int unix_stream_connect(struct socket *sock, struct sockaddr *uaddr,
+ 	struct unix_sock *u = unix_sk(sk), *newu, *otheru;
+ 	struct net *net = sock_net(sk);
+ 	struct sk_buff *skb = NULL;
++	unsigned char state;
+ 	long timeo;
+ 	int err;
+ 
+@@ -1529,7 +1530,6 @@ static int unix_stream_connect(struct socket *sock, struct sockaddr *uaddr,
+ 		goto out;
+ 	}
+ 
+-	/* Latch state of peer */
+ 	unix_state_lock(other);
+ 
+ 	/* Apparently VFS overslept socket death. Retry. */
+@@ -1559,37 +1559,21 @@ static int unix_stream_connect(struct socket *sock, struct sockaddr *uaddr,
+ 		goto restart;
+ 	}
+ 
+-	/* Latch our state.
+-
+-	   It is tricky place. We need to grab our state lock and cannot
+-	   drop lock on peer. It is dangerous because deadlock is
+-	   possible. Connect to self case and simultaneous
+-	   attempt to connect are eliminated by checking socket
+-	   state. other is TCP_LISTEN, if sk is TCP_LISTEN we
+-	   check this before attempt to grab lock.
+-
+-	   Well, and we have to recheck the state after socket locked.
++	/* self connect and simultaneous connect are eliminated
++	 * by rejecting TCP_LISTEN socket to avoid deadlock.
+ 	 */
+-	switch (READ_ONCE(sk->sk_state)) {
+-	case TCP_CLOSE:
+-		/* This is ok... continue with connect */
+-		break;
+-	case TCP_ESTABLISHED:
+-		/* Socket is already connected */
+-		err = -EISCONN;
+-		goto out_unlock;
+-	default:
+-		err = -EINVAL;
++	state = READ_ONCE(sk->sk_state);
++	if (unlikely(state != TCP_CLOSE)) {
++		err = state == TCP_ESTABLISHED ? -EISCONN : -EINVAL;
+ 		goto out_unlock;
+ 	}
+ 
+ 	unix_state_lock_nested(sk, U_LOCK_SECOND);
+ 
+-	if (sk->sk_state != TCP_CLOSE) {
++	if (unlikely(sk->sk_state != TCP_CLOSE)) {
++		err = sk->sk_state == TCP_ESTABLISHED ? -EISCONN : -EINVAL;
+ 		unix_state_unlock(sk);
+-		unix_state_unlock(other);
+-		sock_put(other);
+-		goto restart;
++		goto out_unlock;
+ 	}
+ 
+ 	err = security_unix_stream_connect(sk, other, newsk);
+diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
+index 8f8f077e6cd40..be5c42d6ffbea 100644
+--- a/net/wireless/nl80211.c
++++ b/net/wireless/nl80211.c
+@@ -3398,6 +3398,33 @@ static int __nl80211_set_channel(struct cfg80211_registered_device *rdev,
+ 			if (chandef.chan != cur_chan)
+ 				return -EBUSY;
+ 
++			/* only allow this for regular channel widths */
++			switch (wdev->links[link_id].ap.chandef.width) {
++			case NL80211_CHAN_WIDTH_20_NOHT:
++			case NL80211_CHAN_WIDTH_20:
++			case NL80211_CHAN_WIDTH_40:
++			case NL80211_CHAN_WIDTH_80:
++			case NL80211_CHAN_WIDTH_80P80:
++			case NL80211_CHAN_WIDTH_160:
++			case NL80211_CHAN_WIDTH_320:
++				break;
++			default:
++				return -EINVAL;
++			}
++
++			switch (chandef.width) {
++			case NL80211_CHAN_WIDTH_20_NOHT:
++			case NL80211_CHAN_WIDTH_20:
++			case NL80211_CHAN_WIDTH_40:
++			case NL80211_CHAN_WIDTH_80:
++			case NL80211_CHAN_WIDTH_80P80:
++			case NL80211_CHAN_WIDTH_160:
++			case NL80211_CHAN_WIDTH_320:
++				break;
++			default:
++				return -EINVAL;
++			}
++
+ 			result = rdev_set_ap_chanwidth(rdev, dev, link_id,
+ 						       &chandef);
+ 			if (result)
+@@ -4446,10 +4473,7 @@ static void get_key_callback(void *c, struct key_params *params)
+ 	struct nlattr *key;
+ 	struct get_key_cookie *cookie = c;
+ 
+-	if ((params->key &&
+-	     nla_put(cookie->msg, NL80211_ATTR_KEY_DATA,
+-		     params->key_len, params->key)) ||
+-	    (params->seq &&
++	if ((params->seq &&
+ 	     nla_put(cookie->msg, NL80211_ATTR_KEY_SEQ,
+ 		     params->seq_len, params->seq)) ||
+ 	    (params->cipher &&
+@@ -4461,10 +4485,7 @@ static void get_key_callback(void *c, struct key_params *params)
+ 	if (!key)
+ 		goto nla_put_failure;
+ 
+-	if ((params->key &&
+-	     nla_put(cookie->msg, NL80211_KEY_DATA,
+-		     params->key_len, params->key)) ||
+-	    (params->seq &&
++	if ((params->seq &&
+ 	     nla_put(cookie->msg, NL80211_KEY_SEQ,
+ 		     params->seq_len, params->seq)) ||
+ 	    (params->cipher &&
+diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
+index 038db8902c9ed..82c0d3a3327ab 100644
+--- a/sound/pci/hda/patch_hdmi.c
++++ b/sound/pci/hda/patch_hdmi.c
+@@ -1989,6 +1989,8 @@ static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
+ }
+ 
+ static const struct snd_pci_quirk force_connect_list[] = {
++	SND_PCI_QUIRK(0x103c, 0x83e2, "HP EliteDesk 800 G4", 1),
++	SND_PCI_QUIRK(0x103c, 0x83ef, "HP MP9 G4 Retail System AMS", 1),
+ 	SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
+ 	SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
+ 	SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
+diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
+index 0b33a00771450..82dcea2b78000 100644
+--- a/sound/pci/hda/patch_realtek.c
++++ b/sound/pci/hda/patch_realtek.c
+@@ -10360,6 +10360,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
+ 	SND_PCI_QUIRK(0x8086, 0x3038, "Intel NUC 13", ALC295_FIXUP_CHROME_BOOK),
+ 	SND_PCI_QUIRK(0xf111, 0x0001, "Framework Laptop", ALC295_FIXUP_FRAMEWORK_LAPTOP_MIC_NO_PRESENCE),
+ 	SND_PCI_QUIRK(0xf111, 0x0006, "Framework Laptop", ALC295_FIXUP_FRAMEWORK_LAPTOP_MIC_NO_PRESENCE),
++	SND_PCI_QUIRK(0xf111, 0x0009, "Framework Laptop", ALC295_FIXUP_FRAMEWORK_LAPTOP_MIC_NO_PRESENCE),
+ 
+ #if 0
+ 	/* Below is a quirk table taken from the old code.
+diff --git a/sound/soc/amd/yc/acp6x-mach.c b/sound/soc/amd/yc/acp6x-mach.c
+index 36dddf230c2c4..d597e59863ee3 100644
+--- a/sound/soc/amd/yc/acp6x-mach.c
++++ b/sound/soc/amd/yc/acp6x-mach.c
+@@ -409,6 +409,13 @@ static const struct dmi_system_id yc_acp_quirk_table[] = {
+ 			DMI_MATCH(DMI_BOARD_NAME, "8A43"),
+ 		}
+ 	},
++	{
++		.driver_data = &acp6x_card,
++		.matches = {
++			DMI_MATCH(DMI_BOARD_VENDOR, "HP"),
++			DMI_MATCH(DMI_BOARD_NAME, "8A44"),
++		}
++	},
+ 	{
+ 		.driver_data = &acp6x_card,
+ 		.matches = {
+diff --git a/sound/soc/codecs/wcd938x-sdw.c b/sound/soc/codecs/wcd938x-sdw.c
+index a1f04010da95f..132c1d24f8f6e 100644
+--- a/sound/soc/codecs/wcd938x-sdw.c
++++ b/sound/soc/codecs/wcd938x-sdw.c
+@@ -1252,12 +1252,12 @@ static int wcd9380_probe(struct sdw_slave *pdev,
+ 	pdev->prop.lane_control_support = true;
+ 	pdev->prop.simple_clk_stop_capable = true;
+ 	if (wcd->is_tx) {
+-		pdev->prop.source_ports = GENMASK(WCD938X_MAX_SWR_PORTS, 0);
++		pdev->prop.source_ports = GENMASK(WCD938X_MAX_SWR_PORTS - 1, 0);
+ 		pdev->prop.src_dpn_prop = wcd938x_dpn_prop;
+ 		wcd->ch_info = &wcd938x_sdw_tx_ch_info[0];
+ 		pdev->prop.wake_capable = true;
+ 	} else {
+-		pdev->prop.sink_ports = GENMASK(WCD938X_MAX_SWR_PORTS, 0);
++		pdev->prop.sink_ports = GENMASK(WCD938X_MAX_SWR_PORTS - 1, 0);
+ 		pdev->prop.sink_dpn_prop = wcd938x_dpn_prop;
+ 		wcd->ch_info = &wcd938x_sdw_rx_ch_info[0];
+ 	}
+diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c
+index 1253695bebd86..53b828f681020 100644
+--- a/sound/soc/codecs/wsa881x.c
++++ b/sound/soc/codecs/wsa881x.c
+@@ -1152,7 +1152,7 @@ static int wsa881x_probe(struct sdw_slave *pdev,
+ 	wsa881x->sconfig.frame_rate = 48000;
+ 	wsa881x->sconfig.direction = SDW_DATA_DIR_RX;
+ 	wsa881x->sconfig.type = SDW_STREAM_PDM;
+-	pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0);
++	pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS - 1, 0);
+ 	pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
+ 	pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
+ 	pdev->prop.clk_stop_mode1 = true;
+diff --git a/sound/soc/codecs/wsa883x.c b/sound/soc/codecs/wsa883x.c
+index a2e86ef7d18f5..2169d93989841 100644
+--- a/sound/soc/codecs/wsa883x.c
++++ b/sound/soc/codecs/wsa883x.c
+@@ -1399,7 +1399,15 @@ static int wsa883x_probe(struct sdw_slave *pdev,
+ 	wsa883x->sconfig.direction = SDW_DATA_DIR_RX;
+ 	wsa883x->sconfig.type = SDW_STREAM_PDM;
+ 
+-	pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS, 0);
++	/**
++	 * Port map index starts with 0, however the data port for this codec
++	 * are from index 1
++	 */
++	if (of_property_read_u32_array(dev->of_node, "qcom,port-mapping", &pdev->m_port_map[1],
++					WSA883X_MAX_SWR_PORTS))
++		dev_dbg(dev, "Static Port mapping not specified\n");
++
++	pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS - 1, 0);
+ 	pdev->prop.simple_clk_stop_capable = true;
+ 	pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
+ 	pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
+diff --git a/sound/soc/codecs/wsa884x.c b/sound/soc/codecs/wsa884x.c
+index 993d76b18b536..1cd52fab7b40d 100644
+--- a/sound/soc/codecs/wsa884x.c
++++ b/sound/soc/codecs/wsa884x.c
+@@ -1858,7 +1858,15 @@ static int wsa884x_probe(struct sdw_slave *pdev,
+ 	wsa884x->sconfig.direction = SDW_DATA_DIR_RX;
+ 	wsa884x->sconfig.type = SDW_STREAM_PDM;
+ 
+-	pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS, 0);
++	/**
++	 * Port map index starts with 0, however the data port for this codec
++	 * are from index 1
++	 */
++	if (of_property_read_u32_array(dev->of_node, "qcom,port-mapping", &pdev->m_port_map[1],
++					WSA884X_MAX_SWR_PORTS))
++		dev_dbg(dev, "Static Port mapping not specified\n");
++
++	pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS - 1, 0);
+ 	pdev->prop.simple_clk_stop_capable = true;
+ 	pdev->prop.sink_dpn_prop = wsa884x_sink_dpn_prop;
+ 	pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
+diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c
+index 94b169a5493b5..5218e40aeb1bb 100644
+--- a/sound/soc/meson/axg-fifo.c
++++ b/sound/soc/meson/axg-fifo.c
+@@ -207,25 +207,18 @@ static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
+ 	status = FIELD_GET(STATUS1_INT_STS, status);
+ 	axg_fifo_ack_irq(fifo, status);
+ 
+-	/* Use the thread to call period elapsed on nonatomic links */
+-	if (status & FIFO_INT_COUNT_REPEAT)
+-		return IRQ_WAKE_THREAD;
++	if (status & ~FIFO_INT_COUNT_REPEAT)
++		dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n",
++			status);
+ 
+-	dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n",
+-		status);
++	if (status & FIFO_INT_COUNT_REPEAT) {
++		snd_pcm_period_elapsed(ss);
++		return IRQ_HANDLED;
++	}
+ 
+ 	return IRQ_NONE;
+ }
+ 
+-static irqreturn_t axg_fifo_pcm_irq_block_thread(int irq, void *dev_id)
+-{
+-	struct snd_pcm_substream *ss = dev_id;
+-
+-	snd_pcm_period_elapsed(ss);
+-
+-	return IRQ_HANDLED;
+-}
+-
+ int axg_fifo_pcm_open(struct snd_soc_component *component,
+ 		      struct snd_pcm_substream *ss)
+ {
+@@ -251,8 +244,9 @@ int axg_fifo_pcm_open(struct snd_soc_component *component,
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = request_threaded_irq(fifo->irq, axg_fifo_pcm_irq_block,
+-				   axg_fifo_pcm_irq_block_thread,
++	/* Use the threaded irq handler only with non-atomic links */
++	ret = request_threaded_irq(fifo->irq, NULL,
++				   axg_fifo_pcm_irq_block,
+ 				   IRQF_ONESHOT, dev_name(dev), ss);
+ 	if (ret)
+ 		return ret;
+diff --git a/sound/soc/sof/mediatek/mt8195/mt8195.c b/sound/soc/sof/mediatek/mt8195/mt8195.c
+index 7d6a568556ea4..b5b4ea854da4b 100644
+--- a/sound/soc/sof/mediatek/mt8195/mt8195.c
++++ b/sound/soc/sof/mediatek/mt8195/mt8195.c
+@@ -624,7 +624,7 @@ static struct snd_sof_dsp_ops sof_mt8195_ops = {
+ static struct snd_sof_of_mach sof_mt8195_machs[] = {
+ 	{
+ 		.compatible = "google,tomato",
+-		.sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682-dts.tplg"
++		.sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682.tplg"
+ 	}, {
+ 		.compatible = "mediatek,mt8195",
+ 		.sof_tplg_filename = "sof-mt8195.tplg"
+diff --git a/sound/soc/sti/sti_uniperif.c b/sound/soc/sti/sti_uniperif.c
+index 2c21a86421e66..cc9a8122b9bc2 100644
+--- a/sound/soc/sti/sti_uniperif.c
++++ b/sound/soc/sti/sti_uniperif.c
+@@ -352,7 +352,7 @@ static int sti_uniperiph_resume(struct snd_soc_component *component)
+ 	return ret;
+ }
+ 
+-static int sti_uniperiph_dai_probe(struct snd_soc_dai *dai)
++int sti_uniperiph_dai_probe(struct snd_soc_dai *dai)
+ {
+ 	struct sti_uniperiph_data *priv = snd_soc_dai_get_drvdata(dai);
+ 	struct sti_uniperiph_dai *dai_data = &priv->dai_data;
+diff --git a/sound/soc/sti/uniperif.h b/sound/soc/sti/uniperif.h
+index 2a5de328501c1..74e51f0ff85c8 100644
+--- a/sound/soc/sti/uniperif.h
++++ b/sound/soc/sti/uniperif.h
+@@ -1380,6 +1380,7 @@ int uni_reader_init(struct platform_device *pdev,
+ 		    struct uniperif *reader);
+ 
+ /* common */
++int sti_uniperiph_dai_probe(struct snd_soc_dai *dai);
+ int sti_uniperiph_dai_set_fmt(struct snd_soc_dai *dai,
+ 			      unsigned int fmt);
+ 
+diff --git a/sound/soc/sti/uniperif_player.c b/sound/soc/sti/uniperif_player.c
+index dd9013c476649..6d1ce030963c6 100644
+--- a/sound/soc/sti/uniperif_player.c
++++ b/sound/soc/sti/uniperif_player.c
+@@ -1038,6 +1038,7 @@ static const struct snd_soc_dai_ops uni_player_dai_ops = {
+ 		.startup = uni_player_startup,
+ 		.shutdown = uni_player_shutdown,
+ 		.prepare = uni_player_prepare,
++		.probe = sti_uniperiph_dai_probe,
+ 		.trigger = uni_player_trigger,
+ 		.hw_params = sti_uniperiph_dai_hw_params,
+ 		.set_fmt = sti_uniperiph_dai_set_fmt,
+diff --git a/sound/soc/sti/uniperif_reader.c b/sound/soc/sti/uniperif_reader.c
+index 065c5f0d1f5f0..05ea2b794eb92 100644
+--- a/sound/soc/sti/uniperif_reader.c
++++ b/sound/soc/sti/uniperif_reader.c
+@@ -401,6 +401,7 @@ static const struct snd_soc_dai_ops uni_reader_dai_ops = {
+ 		.startup = uni_reader_startup,
+ 		.shutdown = uni_reader_shutdown,
+ 		.prepare = uni_reader_prepare,
++		.probe = sti_uniperiph_dai_probe,
+ 		.trigger = uni_reader_trigger,
+ 		.hw_params = sti_uniperiph_dai_hw_params,
+ 		.set_fmt = sti_uniperiph_dai_set_fmt,
+diff --git a/sound/usb/line6/driver.c b/sound/usb/line6/driver.c
+index f4437015d43a7..9df49a880b750 100644
+--- a/sound/usb/line6/driver.c
++++ b/sound/usb/line6/driver.c
+@@ -286,12 +286,14 @@ static void line6_data_received(struct urb *urb)
+ {
+ 	struct usb_line6 *line6 = (struct usb_line6 *)urb->context;
+ 	struct midi_buffer *mb = &line6->line6midi->midibuf_in;
++	unsigned long flags;
+ 	int done;
+ 
+ 	if (urb->status == -ESHUTDOWN)
+ 		return;
+ 
+ 	if (line6->properties->capabilities & LINE6_CAP_CONTROL_MIDI) {
++		spin_lock_irqsave(&line6->line6midi->lock, flags);
+ 		done =
+ 			line6_midibuf_write(mb, urb->transfer_buffer, urb->actual_length);
+ 
+@@ -300,12 +302,15 @@ static void line6_data_received(struct urb *urb)
+ 			dev_dbg(line6->ifcdev, "%d %d buffer overflow - message skipped\n",
+ 				done, urb->actual_length);
+ 		}
++		spin_unlock_irqrestore(&line6->line6midi->lock, flags);
+ 
+ 		for (;;) {
++			spin_lock_irqsave(&line6->line6midi->lock, flags);
+ 			done =
+ 				line6_midibuf_read(mb, line6->buffer_message,
+ 						   LINE6_MIDI_MESSAGE_MAXLEN,
+ 						   LINE6_MIDIBUF_READ_RX);
++			spin_unlock_irqrestore(&line6->line6midi->lock, flags);
+ 
+ 			if (done <= 0)
+ 				break;
+diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h
+index 5d72dc8441cbb..af1b8cf5a9883 100644
+--- a/sound/usb/quirks-table.h
++++ b/sound/usb/quirks-table.h
+@@ -2594,6 +2594,10 @@ YAMAHA_DEVICE(0x7010, "UB99"),
+ 	}
+ },
+ 
++/* Stanton ScratchAmp */
++{ USB_DEVICE(0x103d, 0x0100) },
++{ USB_DEVICE(0x103d, 0x0101) },
++
+ /* Novation EMS devices */
+ {
+ 	USB_DEVICE_VENDOR_SPEC(0x1235, 0x0001),
+diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h
+index 5f6f84837a490..329d41f8c9237 100644
+--- a/tools/arch/arm64/include/asm/cputype.h
++++ b/tools/arch/arm64/include/asm/cputype.h
+@@ -84,6 +84,9 @@
+ #define ARM_CPU_PART_CORTEX_X2		0xD48
+ #define ARM_CPU_PART_NEOVERSE_N2	0xD49
+ #define ARM_CPU_PART_CORTEX_A78C	0xD4B
++#define ARM_CPU_PART_NEOVERSE_V2	0xD4F
++#define ARM_CPU_PART_CORTEX_X4		0xD82
++#define ARM_CPU_PART_NEOVERSE_V3	0xD84
+ 
+ #define APM_CPU_PART_POTENZA		0x000
+ 
+@@ -153,6 +156,9 @@
+ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
+ #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
+ #define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
++#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
++#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
++#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
+ #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
+ #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
+ #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
+diff --git a/tools/testing/selftests/bpf/prog_tests/send_signal.c b/tools/testing/selftests/bpf/prog_tests/send_signal.c
+index b15b343ebb6b1..9adcda7f1fedc 100644
+--- a/tools/testing/selftests/bpf/prog_tests/send_signal.c
++++ b/tools/testing/selftests/bpf/prog_tests/send_signal.c
+@@ -156,7 +156,8 @@ static void test_send_signal_tracepoint(bool signal_thread)
+ static void test_send_signal_perf(bool signal_thread)
+ {
+ 	struct perf_event_attr attr = {
+-		.sample_period = 1,
++		.freq = 1,
++		.sample_freq = 1000,
+ 		.type = PERF_TYPE_SOFTWARE,
+ 		.config = PERF_COUNT_SW_CPU_CLOCK,
+ 	};
+diff --git a/tools/testing/selftests/mm/Makefile b/tools/testing/selftests/mm/Makefile
+index 292359a542429..8b2b9bb8bad10 100644
+--- a/tools/testing/selftests/mm/Makefile
++++ b/tools/testing/selftests/mm/Makefile
+@@ -101,7 +101,7 @@ endif
+ 
+ endif
+ 
+-ifneq (,$(filter $(ARCH),arm64 ia64 mips64 parisc64 powerpc riscv64 s390x sparc64 x86_64))
++ifneq (,$(filter $(ARCH),arm64 ia64 mips64 parisc64 powerpc riscv64 s390x sparc64 x86_64 s390))
+ TEST_GEN_FILES += va_high_addr_switch
+ TEST_GEN_FILES += virtual_address_range
+ TEST_GEN_FILES += write_to_hugetlbfs
+diff --git a/tools/testing/selftests/net/mptcp/mptcp_join.sh b/tools/testing/selftests/net/mptcp/mptcp_join.sh
+index a2dae2a3a93e0..b16b8278c4cea 100755
+--- a/tools/testing/selftests/net/mptcp/mptcp_join.sh
++++ b/tools/testing/selftests/net/mptcp/mptcp_join.sh
+@@ -812,7 +812,7 @@ pm_nl_check_endpoint()
+ 	done
+ 
+ 	if [ -z "$id" ]; then
+-		test_fail "bad test - missing endpoint id"
++		fail_test "bad test - missing endpoint id"
+ 		return
+ 	fi
+ 
+@@ -1559,18 +1559,28 @@ chk_add_nr()
+ 	local add_nr=$1
+ 	local echo_nr=$2
+ 	local port_nr=${3:-0}
+-	local syn_nr=${4:-$port_nr}
+-	local syn_ack_nr=${5:-$port_nr}
+-	local ack_nr=${6:-$port_nr}
+-	local mis_syn_nr=${7:-0}
+-	local mis_ack_nr=${8:-0}
++	local ns_invert=${4:-""}
++	local syn_nr=$port_nr
++	local syn_ack_nr=$port_nr
++	local ack_nr=$port_nr
++	local mis_syn_nr=0
++	local mis_ack_nr=0
++	local ns_tx=$ns1
++	local ns_rx=$ns2
++	local extra_msg=""
+ 	local count
+ 	local timeout
+ 
+-	timeout=$(ip netns exec $ns1 sysctl -n net.mptcp.add_addr_timeout)
++	if [[ $ns_invert = "invert" ]]; then
++		ns_tx=$ns2
++		ns_rx=$ns1
++		extra_msg="invert"
++	fi
++
++	timeout=$(ip netns exec ${ns_tx} sysctl -n net.mptcp.add_addr_timeout)
+ 
+ 	print_check "add"
+-	count=$(mptcp_lib_get_counter ${ns2} "MPTcpExtAddAddr")
++	count=$(mptcp_lib_get_counter ${ns_rx} "MPTcpExtAddAddr")
+ 	if [ -z "$count" ]; then
+ 		print_skip
+ 	# if the test configured a short timeout tolerate greater then expected
+@@ -1582,7 +1592,7 @@ chk_add_nr()
+ 	fi
+ 
+ 	print_check "echo"
+-	count=$(mptcp_lib_get_counter ${ns1} "MPTcpExtEchoAdd")
++	count=$(mptcp_lib_get_counter ${ns_tx} "MPTcpExtEchoAdd")
+ 	if [ -z "$count" ]; then
+ 		print_skip
+ 	elif [ "$count" != "$echo_nr" ]; then
+@@ -1593,7 +1603,7 @@ chk_add_nr()
+ 
+ 	if [ $port_nr -gt 0 ]; then
+ 		print_check "pt"
+-		count=$(mptcp_lib_get_counter ${ns2} "MPTcpExtPortAdd")
++		count=$(mptcp_lib_get_counter ${ns_rx} "MPTcpExtPortAdd")
+ 		if [ -z "$count" ]; then
+ 			print_skip
+ 		elif [ "$count" != "$port_nr" ]; then
+@@ -1603,7 +1613,7 @@ chk_add_nr()
+ 		fi
+ 
+ 		print_check "syn"
+-		count=$(mptcp_lib_get_counter ${ns1} "MPTcpExtMPJoinPortSynRx")
++		count=$(mptcp_lib_get_counter ${ns_tx} "MPTcpExtMPJoinPortSynRx")
+ 		if [ -z "$count" ]; then
+ 			print_skip
+ 		elif [ "$count" != "$syn_nr" ]; then
+@@ -1614,7 +1624,7 @@ chk_add_nr()
+ 		fi
+ 
+ 		print_check "synack"
+-		count=$(mptcp_lib_get_counter ${ns2} "MPTcpExtMPJoinPortSynAckRx")
++		count=$(mptcp_lib_get_counter ${ns_rx} "MPTcpExtMPJoinPortSynAckRx")
+ 		if [ -z "$count" ]; then
+ 			print_skip
+ 		elif [ "$count" != "$syn_ack_nr" ]; then
+@@ -1625,7 +1635,7 @@ chk_add_nr()
+ 		fi
+ 
+ 		print_check "ack"
+-		count=$(mptcp_lib_get_counter ${ns1} "MPTcpExtMPJoinPortAckRx")
++		count=$(mptcp_lib_get_counter ${ns_tx} "MPTcpExtMPJoinPortAckRx")
+ 		if [ -z "$count" ]; then
+ 			print_skip
+ 		elif [ "$count" != "$ack_nr" ]; then
+@@ -1636,7 +1646,7 @@ chk_add_nr()
+ 		fi
+ 
+ 		print_check "syn"
+-		count=$(mptcp_lib_get_counter ${ns1} "MPTcpExtMismatchPortSynRx")
++		count=$(mptcp_lib_get_counter ${ns_tx} "MPTcpExtMismatchPortSynRx")
+ 		if [ -z "$count" ]; then
+ 			print_skip
+ 		elif [ "$count" != "$mis_syn_nr" ]; then
+@@ -1647,7 +1657,7 @@ chk_add_nr()
+ 		fi
+ 
+ 		print_check "ack"
+-		count=$(mptcp_lib_get_counter ${ns1} "MPTcpExtMismatchPortAckRx")
++		count=$(mptcp_lib_get_counter ${ns_tx} "MPTcpExtMismatchPortAckRx")
+ 		if [ -z "$count" ]; then
+ 			print_skip
+ 		elif [ "$count" != "$mis_ack_nr" ]; then
+@@ -1657,6 +1667,8 @@ chk_add_nr()
+ 			print_ok
+ 		fi
+ 	fi
++
++	print_info "$extra_msg"
+ }
+ 
+ chk_add_tx_nr()
+@@ -2121,6 +2133,21 @@ signal_address_tests()
+ 		chk_add_nr 1 1
+ 	fi
+ 
++	# uncommon: subflow and signal flags on the same endpoint
++	# or because the user wrongly picked both, but still expects the client
++	# to create additional subflows
++	if reset "subflow and signal together"; then
++		pm_nl_set_limits $ns1 0 2
++		pm_nl_set_limits $ns2 0 2
++		pm_nl_add_endpoint $ns2 10.0.3.2 flags signal,subflow
++		run_tests $ns1 $ns2 10.0.1.1
++		chk_join_nr 1 1 1
++		chk_add_nr 1 1 0 invert  # only initiated by ns2
++		chk_add_nr 0 0 0         # none initiated by ns1
++		chk_rst_nr 0 0 invert    # no RST sent by the client
++		chk_rst_nr 0 0           # no RST sent by the server
++	fi
++
+ 	# accept and use add_addr with additional subflows
+ 	if reset "multiple subflows and signal"; then
+ 		pm_nl_set_limits $ns1 0 3
+diff --git a/tools/testing/selftests/net/mptcp/simult_flows.sh b/tools/testing/selftests/net/mptcp/simult_flows.sh
+index be97a7ed09503..f24bd2bf08311 100755
+--- a/tools/testing/selftests/net/mptcp/simult_flows.sh
++++ b/tools/testing/selftests/net/mptcp/simult_flows.sh
+@@ -262,7 +262,7 @@ run_test()
+ 	do_transfer $small $large $time
+ 	lret=$?
+ 	mptcp_lib_result_code "${lret}" "${msg}"
+-	if [ $lret -ne 0 ] && ! mptcp_lib_subtest_is_flaky; then
++	if [ $lret -ne 0 ]; then
+ 		ret=$lret
+ 		[ $bail -eq 0 ] || exit $ret
+ 	fi
+@@ -272,7 +272,7 @@ run_test()
+ 	do_transfer $large $small $time
+ 	lret=$?
+ 	mptcp_lib_result_code "${lret}" "${msg}"
+-	if [ $lret -ne 0 ] && ! mptcp_lib_subtest_is_flaky; then
++	if [ $lret -ne 0 ]; then
+ 		ret=$lret
+ 		[ $bail -eq 0 ] || exit $ret
+ 	fi
+@@ -305,7 +305,7 @@ run_test 10 10 0 0 "balanced bwidth"
+ run_test 10 10 1 25 "balanced bwidth with unbalanced delay"
+ 
+ # we still need some additional infrastructure to pass the following test-cases
+-MPTCP_LIB_SUBTEST_FLAKY=1 run_test 10 3 0 0 "unbalanced bwidth"
++run_test 10 3 0 0 "unbalanced bwidth"
+ run_test 10 3 1 25 "unbalanced bwidth with unbalanced delay"
+ run_test 10 3 25 1 "unbalanced bwidth with opposed, unbalanced delay"
+ 
+diff --git a/tools/testing/selftests/rcutorture/bin/torture.sh b/tools/testing/selftests/rcutorture/bin/torture.sh
+index 12b50a4a881ac..89a82f6f140ef 100755
+--- a/tools/testing/selftests/rcutorture/bin/torture.sh
++++ b/tools/testing/selftests/rcutorture/bin/torture.sh
+@@ -567,7 +567,7 @@ then
+ 	torture_bootargs="rcupdate.rcu_cpu_stall_suppress_at_boot=1 torture.disable_onoff_at_boot rcupdate.rcu_task_stall_timeout=30000 tsc=watchdog"
+ 	torture_set "clocksourcewd-1" tools/testing/selftests/rcutorture/bin/kvm.sh --allcpus --duration 45s --configs TREE03 --kconfig "CONFIG_TEST_CLOCKSOURCE_WATCHDOG=y" --trust-make
+ 
+-	torture_bootargs="rcupdate.rcu_cpu_stall_suppress_at_boot=1 torture.disable_onoff_at_boot rcupdate.rcu_task_stall_timeout=30000 clocksource.max_cswd_read_retries=1 tsc=watchdog"
++	torture_bootargs="rcupdate.rcu_cpu_stall_suppress_at_boot=1 torture.disable_onoff_at_boot rcupdate.rcu_task_stall_timeout=30000 tsc=watchdog"
+ 	torture_set "clocksourcewd-2" tools/testing/selftests/rcutorture/bin/kvm.sh --allcpus --duration 45s --configs TREE03 --kconfig "CONFIG_TEST_CLOCKSOURCE_WATCHDOG=y" --trust-make
+ 
+ 	# In case our work is already done...
diff --git a/patch/kernel/archive/odroidxu4-6.6/patch-6.6.46-47.patch b/patch/kernel/archive/odroidxu4-6.6/patch-6.6.46-47.patch
new file mode 100644
index 000000000000..830bd4b9a097
--- /dev/null
+++ b/patch/kernel/archive/odroidxu4-6.6/patch-6.6.46-47.patch
@@ -0,0 +1,4211 @@
+diff --git a/Documentation/bpf/map_lpm_trie.rst b/Documentation/bpf/map_lpm_trie.rst
+index 74d64a30f50073..f9cd579496c9ce 100644
+--- a/Documentation/bpf/map_lpm_trie.rst
++++ b/Documentation/bpf/map_lpm_trie.rst
+@@ -17,7 +17,7 @@ significant byte.
+ 
+ LPM tries may be created with a maximum prefix length that is a multiple
+ of 8, in the range from 8 to 2048. The key used for lookup and update
+-operations is a ``struct bpf_lpm_trie_key``, extended by
++operations is a ``struct bpf_lpm_trie_key_u8``, extended by
+ ``max_prefixlen/8`` bytes.
+ 
+ - For IPv4 addresses the data length is 4 bytes
+diff --git a/Documentation/mm/page_table_check.rst b/Documentation/mm/page_table_check.rst
+index c12838ce6b8de2..c59f22eb6a0f9a 100644
+--- a/Documentation/mm/page_table_check.rst
++++ b/Documentation/mm/page_table_check.rst
+@@ -14,7 +14,7 @@ Page table check performs extra verifications at the time when new pages become
+ accessible from the userspace by getting their page table entries (PTEs PMDs
+ etc.) added into the table.
+ 
+-In case of detected corruption, the kernel is crashed. There is a small
++In case of most detected corruption, the kernel is crashed. There is a small
+ performance and memory overhead associated with the page table check. Therefore,
+ it is disabled by default, but can be optionally enabled on systems where the
+ extra hardening outweighs the performance costs. Also, because page table check
+@@ -22,6 +22,13 @@ is synchronous, it can help with debugging double map memory corruption issues,
+ by crashing kernel at the time wrong mapping occurs instead of later which is
+ often the case with memory corruptions bugs.
+ 
++It can also be used to do page table entry checks over various flags, dump
++warnings when illegal combinations of entry flags are detected.  Currently,
++userfaultfd is the only user of such to sanity check wr-protect bit against
++any writable flags.  Illegal flag combinations will not directly cause data
++corruption in this case immediately, but that will cause read-only data to
++be writable, leading to corrupt when the page content is later modified.
++
+ Double mapping detection logic
+ ==============================
+ 
+diff --git a/Makefile b/Makefile
+index 77de99984c2f18..6b967e135c80f0 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1,7 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ VERSION = 6
+ PATCHLEVEL = 6
+-SUBLEVEL = 46
++SUBLEVEL = 47
+ EXTRAVERSION =
+ NAME = Hurr durr I'ma ninja sloth
+ 
+diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
+index 15aa9bad1c280b..ca0bf0b92ca09e 100644
+--- a/arch/arm64/kvm/hyp/pgtable.c
++++ b/arch/arm64/kvm/hyp/pgtable.c
+@@ -523,7 +523,7 @@ static int hyp_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx,
+ 
+ 		kvm_clear_pte(ctx->ptep);
+ 		dsb(ishst);
+-		__tlbi_level(vae2is, __TLBI_VADDR(ctx->addr, 0), ctx->level);
++		__tlbi_level(vae2is, __TLBI_VADDR(ctx->addr, 0), 0);
+ 	} else {
+ 		if (ctx->end - ctx->addr < granule)
+ 			return -EINVAL;
+@@ -861,9 +861,13 @@ static void stage2_unmap_put_pte(const struct kvm_pgtable_visit_ctx *ctx,
+ 	if (kvm_pte_valid(ctx->old)) {
+ 		kvm_clear_pte(ctx->ptep);
+ 
+-		if (!stage2_unmap_defer_tlb_flush(pgt))
+-			kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu,
+-					ctx->addr, ctx->level);
++		if (kvm_pte_table(ctx->old, ctx->level)) {
++			kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu, ctx->addr,
++				     0);
++		} else if (!stage2_unmap_defer_tlb_flush(pgt)) {
++			kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu, ctx->addr,
++				     ctx->level);
++		}
+ 	}
+ 
+ 	mm_ops->put_page(ctx->ptep);
+diff --git a/arch/loongarch/include/uapi/asm/unistd.h b/arch/loongarch/include/uapi/asm/unistd.h
+index fcb668984f0336..b344b1f917153b 100644
+--- a/arch/loongarch/include/uapi/asm/unistd.h
++++ b/arch/loongarch/include/uapi/asm/unistd.h
+@@ -1,4 +1,5 @@
+ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
++#define __ARCH_WANT_NEW_STAT
+ #define __ARCH_WANT_SYS_CLONE
+ #define __ARCH_WANT_SYS_CLONE3
+ 
+diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
+index e02b179ec65989..d03fe4fb41f43c 100644
+--- a/arch/x86/include/asm/pgtable.h
++++ b/arch/x86/include/asm/pgtable.h
+@@ -387,23 +387,7 @@ static inline pte_t pte_wrprotect(pte_t pte)
+ #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
+ static inline int pte_uffd_wp(pte_t pte)
+ {
+-	bool wp = pte_flags(pte) & _PAGE_UFFD_WP;
+-
+-#ifdef CONFIG_DEBUG_VM
+-	/*
+-	 * Having write bit for wr-protect-marked present ptes is fatal,
+-	 * because it means the uffd-wp bit will be ignored and write will
+-	 * just go through.
+-	 *
+-	 * Use any chance of pgtable walking to verify this (e.g., when
+-	 * page swapped out or being migrated for all purposes). It means
+-	 * something is already wrong.  Tell the admin even before the
+-	 * process crashes. We also nail it with wrong pgtable setup.
+-	 */
+-	WARN_ON_ONCE(wp && pte_write(pte));
+-#endif
+-
+-	return wp;
++	return pte_flags(pte) & _PAGE_UFFD_WP;
+ }
+ 
+ static inline pte_t pte_mkuffd_wp(pte_t pte)
+diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
+index 77dbd516a05463..277bf0e8ed0918 100644
+--- a/drivers/ata/libata-scsi.c
++++ b/drivers/ata/libata-scsi.c
+@@ -941,8 +941,19 @@ static void ata_gen_passthru_sense(struct ata_queued_cmd *qc)
+ 				   &sense_key, &asc, &ascq);
+ 		ata_scsi_set_sense(qc->dev, cmd, sense_key, asc, ascq);
+ 	} else {
+-		/* ATA PASS-THROUGH INFORMATION AVAILABLE */
+-		ata_scsi_set_sense(qc->dev, cmd, RECOVERED_ERROR, 0, 0x1D);
++		/*
++		 * ATA PASS-THROUGH INFORMATION AVAILABLE
++		 *
++		 * Note: we are supposed to call ata_scsi_set_sense(), which
++		 * respects the D_SENSE bit, instead of unconditionally
++		 * generating the sense data in descriptor format. However,
++		 * because hdparm, hddtemp, and udisks incorrectly assume sense
++		 * data in descriptor format, without even looking at the
++		 * RESPONSE CODE field in the returned sense data (to see which
++		 * format the returned sense data is in), we are stuck with
++		 * being bug compatible with older kernels.
++		 */
++		scsi_build_sense(cmd, 1, RECOVERED_ERROR, 0, 0x1D);
+ 	}
+ }
+ 
+diff --git a/drivers/isdn/mISDN/socket.c b/drivers/isdn/mISDN/socket.c
+index 2776ca5fc33f39..b215b28cad7b76 100644
+--- a/drivers/isdn/mISDN/socket.c
++++ b/drivers/isdn/mISDN/socket.c
+@@ -401,23 +401,23 @@ data_sock_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg)
+ }
+ 
+ static int data_sock_setsockopt(struct socket *sock, int level, int optname,
+-				sockptr_t optval, unsigned int len)
++				sockptr_t optval, unsigned int optlen)
+ {
+ 	struct sock *sk = sock->sk;
+ 	int err = 0, opt = 0;
+ 
+ 	if (*debug & DEBUG_SOCKET)
+ 		printk(KERN_DEBUG "%s(%p, %d, %x, optval, %d)\n", __func__, sock,
+-		       level, optname, len);
++		       level, optname, optlen);
+ 
+ 	lock_sock(sk);
+ 
+ 	switch (optname) {
+ 	case MISDN_TIME_STAMP:
+-		if (copy_from_sockptr(&opt, optval, sizeof(int))) {
+-			err = -EFAULT;
++		err = copy_safe_from_sockptr(&opt, sizeof(opt),
++					     optval, optlen);
++		if (err)
+ 			break;
+-		}
+ 
+ 		if (opt)
+ 			_pms(sk)->cmask |= MISDN_TIME_STAMP;
+diff --git a/drivers/media/usb/dvb-usb/dvb-usb-init.c b/drivers/media/usb/dvb-usb/dvb-usb-init.c
+index 22d83ac18eb735..fbf58012becdf2 100644
+--- a/drivers/media/usb/dvb-usb/dvb-usb-init.c
++++ b/drivers/media/usb/dvb-usb/dvb-usb-init.c
+@@ -23,40 +23,11 @@ static int dvb_usb_force_pid_filter_usage;
+ module_param_named(force_pid_filter_usage, dvb_usb_force_pid_filter_usage, int, 0444);
+ MODULE_PARM_DESC(force_pid_filter_usage, "force all dvb-usb-devices to use a PID filter, if any (default: 0).");
+ 
+-static int dvb_usb_check_bulk_endpoint(struct dvb_usb_device *d, u8 endpoint)
+-{
+-	if (endpoint) {
+-		int ret;
+-
+-		ret = usb_pipe_type_check(d->udev, usb_sndbulkpipe(d->udev, endpoint));
+-		if (ret)
+-			return ret;
+-		ret = usb_pipe_type_check(d->udev, usb_rcvbulkpipe(d->udev, endpoint));
+-		if (ret)
+-			return ret;
+-	}
+-	return 0;
+-}
+-
+-static void dvb_usb_clear_halt(struct dvb_usb_device *d, u8 endpoint)
+-{
+-	if (endpoint) {
+-		usb_clear_halt(d->udev, usb_sndbulkpipe(d->udev, endpoint));
+-		usb_clear_halt(d->udev, usb_rcvbulkpipe(d->udev, endpoint));
+-	}
+-}
+-
+ static int dvb_usb_adapter_init(struct dvb_usb_device *d, short *adapter_nrs)
+ {
+ 	struct dvb_usb_adapter *adap;
+ 	int ret, n, o;
+ 
+-	ret = dvb_usb_check_bulk_endpoint(d, d->props.generic_bulk_ctrl_endpoint);
+-	if (ret)
+-		return ret;
+-	ret = dvb_usb_check_bulk_endpoint(d, d->props.generic_bulk_ctrl_endpoint_response);
+-	if (ret)
+-		return ret;
+ 	for (n = 0; n < d->props.num_adapters; n++) {
+ 		adap = &d->adapter[n];
+ 		adap->dev = d;
+@@ -132,8 +103,10 @@ static int dvb_usb_adapter_init(struct dvb_usb_device *d, short *adapter_nrs)
+ 	 * when reloading the driver w/o replugging the device
+ 	 * sometimes a timeout occurs, this helps
+ 	 */
+-	dvb_usb_clear_halt(d, d->props.generic_bulk_ctrl_endpoint);
+-	dvb_usb_clear_halt(d, d->props.generic_bulk_ctrl_endpoint_response);
++	if (d->props.generic_bulk_ctrl_endpoint != 0) {
++		usb_clear_halt(d->udev, usb_sndbulkpipe(d->udev, d->props.generic_bulk_ctrl_endpoint));
++		usb_clear_halt(d->udev, usb_rcvbulkpipe(d->udev, d->props.generic_bulk_ctrl_endpoint));
++	}
+ 
+ 	return 0;
+ 
+diff --git a/drivers/net/ppp/pppoe.c b/drivers/net/ppp/pppoe.c
+index ba8b6bd8233cad..96cca4ee470a4b 100644
+--- a/drivers/net/ppp/pppoe.c
++++ b/drivers/net/ppp/pppoe.c
+@@ -1007,26 +1007,21 @@ static int pppoe_recvmsg(struct socket *sock, struct msghdr *m,
+ 	struct sk_buff *skb;
+ 	int error = 0;
+ 
+-	if (sk->sk_state & PPPOX_BOUND) {
+-		error = -EIO;
+-		goto end;
+-	}
++	if (sk->sk_state & PPPOX_BOUND)
++		return -EIO;
+ 
+ 	skb = skb_recv_datagram(sk, flags, &error);
+-	if (error < 0)
+-		goto end;
++	if (!skb)
++		return error;
+ 
+-	if (skb) {
+-		total_len = min_t(size_t, total_len, skb->len);
+-		error = skb_copy_datagram_msg(skb, 0, m, total_len);
+-		if (error == 0) {
+-			consume_skb(skb);
+-			return total_len;
+-		}
++	total_len = min_t(size_t, total_len, skb->len);
++	error = skb_copy_datagram_msg(skb, 0, m, total_len);
++	if (error == 0) {
++		consume_skb(skb);
++		return total_len;
+ 	}
+ 
+ 	kfree_skb(skb);
+-end:
+ 	return error;
+ }
+ 
+diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
+index 0fc7aa78b2e5b9..2c3f55877a1134 100644
+--- a/drivers/nvme/host/pci.c
++++ b/drivers/nvme/host/pci.c
+@@ -2931,6 +2931,13 @@ static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
+ 			return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
+ 	}
+ 
++	/*
++	 * NVMe SSD drops off the PCIe bus after system idle
++	 * for 10 hours on a Lenovo N60z board.
++	 */
++	if (dmi_match(DMI_BOARD_NAME, "LXKT-ZXEG-N6"))
++		return NVME_QUIRK_NO_APST;
++
+ 	return 0;
+ }
+ 
+diff --git a/fs/binfmt_flat.c b/fs/binfmt_flat.c
+index c26545d71d39a3..cd6d5bbb4b9df5 100644
+--- a/fs/binfmt_flat.c
++++ b/fs/binfmt_flat.c
+@@ -72,8 +72,10 @@
+ 
+ #ifdef CONFIG_BINFMT_FLAT_NO_DATA_START_OFFSET
+ #define DATA_START_OFFSET_WORDS		(0)
++#define MAX_SHARED_LIBS_UPDATE		(0)
+ #else
+ #define DATA_START_OFFSET_WORDS		(MAX_SHARED_LIBS)
++#define MAX_SHARED_LIBS_UPDATE		(MAX_SHARED_LIBS)
+ #endif
+ 
+ struct lib_info {
+@@ -880,7 +882,7 @@ static int load_flat_binary(struct linux_binprm *bprm)
+ 		return res;
+ 
+ 	/* Update data segment pointers for all libraries */
+-	for (i = 0; i < MAX_SHARED_LIBS; i++) {
++	for (i = 0; i < MAX_SHARED_LIBS_UPDATE; i++) {
+ 		if (!libinfo.lib_list[i].loaded)
+ 			continue;
+ 		for (j = 0; j < MAX_SHARED_LIBS; j++) {
+diff --git a/fs/buffer.c b/fs/buffer.c
+index 12e9a71c693d74..ecd8b47507ff80 100644
+--- a/fs/buffer.c
++++ b/fs/buffer.c
+@@ -2179,6 +2179,8 @@ static void __block_commit_write(struct folio *folio, size_t from, size_t to)
+ 	struct buffer_head *bh, *head;
+ 
+ 	bh = head = folio_buffers(folio);
++	if (!bh)
++		return;
+ 	blocksize = bh->b_size;
+ 
+ 	block_start = 0;
+diff --git a/fs/cramfs/inode.c b/fs/cramfs/inode.c
+index 5ee7d7bbb361ce..2fbf97077ce910 100644
+--- a/fs/cramfs/inode.c
++++ b/fs/cramfs/inode.c
+@@ -495,7 +495,7 @@ static void cramfs_kill_sb(struct super_block *sb)
+ 		sb->s_mtd = NULL;
+ 	} else if (IS_ENABLED(CONFIG_CRAMFS_BLOCKDEV) && sb->s_bdev) {
+ 		sync_blockdev(sb->s_bdev);
+-		blkdev_put(sb->s_bdev, sb);
++		bdev_release(sb->s_bdev_handle);
+ 	}
+ 	kfree(sbi);
+ }
+diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c
+index d36b3963c0bf3c..aa59788a61e6e4 100644
+--- a/fs/erofs/decompressor.c
++++ b/fs/erofs/decompressor.c
+@@ -248,15 +248,9 @@ static int z_erofs_lz4_decompress_mem(struct z_erofs_lz4_decompress_ctx *ctx,
+ 	if (ret != rq->outputsize) {
+ 		erofs_err(rq->sb, "failed to decompress %d in[%u, %u] out[%u]",
+ 			  ret, rq->inputsize, inputmargin, rq->outputsize);
+-
+-		print_hex_dump(KERN_DEBUG, "[ in]: ", DUMP_PREFIX_OFFSET,
+-			       16, 1, src + inputmargin, rq->inputsize, true);
+-		print_hex_dump(KERN_DEBUG, "[out]: ", DUMP_PREFIX_OFFSET,
+-			       16, 1, out, rq->outputsize, true);
+-
+ 		if (ret >= 0)
+ 			memset(out + ret, 0, rq->outputsize - ret);
+-		ret = -EIO;
++		ret = -EFSCORRUPTED;
+ 	} else {
+ 		ret = 0;
+ 	}
+diff --git a/fs/exec.c b/fs/exec.c
+index 89a9017af7e86f..1cbbef281f8cfe 100644
+--- a/fs/exec.c
++++ b/fs/exec.c
+@@ -1609,6 +1609,7 @@ static void bprm_fill_uid(struct linux_binprm *bprm, struct file *file)
+ 	unsigned int mode;
+ 	vfsuid_t vfsuid;
+ 	vfsgid_t vfsgid;
++	int err;
+ 
+ 	if (!mnt_may_suid(file->f_path.mnt))
+ 		return;
+@@ -1625,12 +1626,17 @@ static void bprm_fill_uid(struct linux_binprm *bprm, struct file *file)
+ 	/* Be careful if suid/sgid is set */
+ 	inode_lock(inode);
+ 
+-	/* reload atomically mode/uid/gid now that lock held */
++	/* Atomically reload and check mode/uid/gid now that lock held. */
+ 	mode = inode->i_mode;
+ 	vfsuid = i_uid_into_vfsuid(idmap, inode);
+ 	vfsgid = i_gid_into_vfsgid(idmap, inode);
++	err = inode_permission(idmap, inode, MAY_EXEC);
+ 	inode_unlock(inode);
+ 
++	/* Did the exec bit vanish out from under us? Give up. */
++	if (err)
++		return;
++
+ 	/* We ignore suid/sgid if there are no mappings for them in the ns */
+ 	if (!vfsuid_has_mapping(bprm->cred->user_ns, vfsuid) ||
+ 	    !vfsgid_has_mapping(bprm->cred->user_ns, vfsgid))
+diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c
+index cef119a2476bb4..a4ffd1acac6514 100644
+--- a/fs/ext4/inode.c
++++ b/fs/ext4/inode.c
+@@ -2966,23 +2966,29 @@ static int ext4_da_should_update_i_disksize(struct folio *folio,
+ 
+ static int ext4_da_do_write_end(struct address_space *mapping,
+ 			loff_t pos, unsigned len, unsigned copied,
+-			struct page *page)
++			struct folio *folio)
+ {
+ 	struct inode *inode = mapping->host;
+ 	loff_t old_size = inode->i_size;
+ 	bool disksize_changed = false;
+ 	loff_t new_i_size;
+ 
++	if (unlikely(!folio_buffers(folio))) {
++		folio_unlock(folio);
++		folio_put(folio);
++		return -EIO;
++	}
+ 	/*
+ 	 * block_write_end() will mark the inode as dirty with I_DIRTY_PAGES
+ 	 * flag, which all that's needed to trigger page writeback.
+ 	 */
+-	copied = block_write_end(NULL, mapping, pos, len, copied, page, NULL);
++	copied = block_write_end(NULL, mapping, pos, len, copied,
++			&folio->page, NULL);
+ 	new_i_size = pos + copied;
+ 
+ 	/*
+-	 * It's important to update i_size while still holding page lock,
+-	 * because page writeout could otherwise come in and zero beyond
++	 * It's important to update i_size while still holding folio lock,
++	 * because folio writeout could otherwise come in and zero beyond
+ 	 * i_size.
+ 	 *
+ 	 * Since we are holding inode lock, we are sure i_disksize <=
+@@ -3000,14 +3006,14 @@ static int ext4_da_do_write_end(struct address_space *mapping,
+ 
+ 		i_size_write(inode, new_i_size);
+ 		end = (new_i_size - 1) & (PAGE_SIZE - 1);
+-		if (copied && ext4_da_should_update_i_disksize(page_folio(page), end)) {
++		if (copied && ext4_da_should_update_i_disksize(folio, end)) {
+ 			ext4_update_i_disksize(inode, new_i_size);
+ 			disksize_changed = true;
+ 		}
+ 	}
+ 
+-	unlock_page(page);
+-	put_page(page);
++	folio_unlock(folio);
++	folio_put(folio);
+ 
+ 	if (old_size < pos)
+ 		pagecache_isize_extended(inode, old_size, pos);
+@@ -3046,10 +3052,10 @@ static int ext4_da_write_end(struct file *file,
+ 		return ext4_write_inline_data_end(inode, pos, len, copied,
+ 						  folio);
+ 
+-	if (unlikely(copied < len) && !PageUptodate(page))
++	if (unlikely(copied < len) && !folio_test_uptodate(folio))
+ 		copied = 0;
+ 
+-	return ext4_da_do_write_end(mapping, pos, len, copied, &folio->page);
++	return ext4_da_do_write_end(mapping, pos, len, copied, folio);
+ }
+ 
+ /*
+diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c
+index c58cbe9f7809c1..c368ff671d7739 100644
+--- a/fs/ext4/xattr.c
++++ b/fs/ext4/xattr.c
+@@ -1571,46 +1571,49 @@ ext4_xattr_inode_cache_find(struct inode *inode, const void *value,
+ /*
+  * Add value of the EA in an inode.
+  */
+-static int ext4_xattr_inode_lookup_create(handle_t *handle, struct inode *inode,
+-					  const void *value, size_t value_len,
+-					  struct inode **ret_inode)
++static struct inode *ext4_xattr_inode_lookup_create(handle_t *handle,
++		struct inode *inode, const void *value, size_t value_len)
+ {
+ 	struct inode *ea_inode;
+ 	u32 hash;
+ 	int err;
+ 
++	/* Account inode & space to quota even if sharing... */
++	err = ext4_xattr_inode_alloc_quota(inode, value_len);
++	if (err)
++		return ERR_PTR(err);
++
+ 	hash = ext4_xattr_inode_hash(EXT4_SB(inode->i_sb), value, value_len);
+ 	ea_inode = ext4_xattr_inode_cache_find(inode, value, value_len, hash);
+ 	if (ea_inode) {
+ 		err = ext4_xattr_inode_inc_ref(handle, ea_inode);
+-		if (err) {
+-			iput(ea_inode);
+-			return err;
+-		}
+-
+-		*ret_inode = ea_inode;
+-		return 0;
++		if (err)
++			goto out_err;
++		return ea_inode;
+ 	}
+ 
+ 	/* Create an inode for the EA value */
+ 	ea_inode = ext4_xattr_inode_create(handle, inode, hash);
+-	if (IS_ERR(ea_inode))
+-		return PTR_ERR(ea_inode);
++	if (IS_ERR(ea_inode)) {
++		ext4_xattr_inode_free_quota(inode, NULL, value_len);
++		return ea_inode;
++	}
+ 
+ 	err = ext4_xattr_inode_write(handle, ea_inode, value, value_len);
+ 	if (err) {
+ 		if (ext4_xattr_inode_dec_ref(handle, ea_inode))
+ 			ext4_warning_inode(ea_inode, "cleanup dec ref error %d", err);
+-		iput(ea_inode);
+-		return err;
++		goto out_err;
+ 	}
+ 
+ 	if (EA_INODE_CACHE(inode))
+ 		mb_cache_entry_create(EA_INODE_CACHE(inode), GFP_NOFS, hash,
+ 				      ea_inode->i_ino, true /* reusable */);
+-
+-	*ret_inode = ea_inode;
+-	return 0;
++	return ea_inode;
++out_err:
++	iput(ea_inode);
++	ext4_xattr_inode_free_quota(inode, NULL, value_len);
++	return ERR_PTR(err);
+ }
+ 
+ /*
+@@ -1622,6 +1625,7 @@ static int ext4_xattr_inode_lookup_create(handle_t *handle, struct inode *inode,
+ static int ext4_xattr_set_entry(struct ext4_xattr_info *i,
+ 				struct ext4_xattr_search *s,
+ 				handle_t *handle, struct inode *inode,
++				struct inode *new_ea_inode,
+ 				bool is_block)
+ {
+ 	struct ext4_xattr_entry *last, *next;
+@@ -1629,7 +1633,6 @@ static int ext4_xattr_set_entry(struct ext4_xattr_info *i,
+ 	size_t min_offs = s->end - s->base, name_len = strlen(i->name);
+ 	int in_inode = i->in_inode;
+ 	struct inode *old_ea_inode = NULL;
+-	struct inode *new_ea_inode = NULL;
+ 	size_t old_size, new_size;
+ 	int ret;
+ 
+@@ -1714,43 +1717,11 @@ static int ext4_xattr_set_entry(struct ext4_xattr_info *i,
+ 			old_ea_inode = NULL;
+ 			goto out;
+ 		}
+-	}
+-	if (i->value && in_inode) {
+-		WARN_ON_ONCE(!i->value_len);
+-
+-		ret = ext4_xattr_inode_alloc_quota(inode, i->value_len);
+-		if (ret)
+-			goto out;
+-
+-		ret = ext4_xattr_inode_lookup_create(handle, inode, i->value,
+-						     i->value_len,
+-						     &new_ea_inode);
+-		if (ret) {
+-			new_ea_inode = NULL;
+-			ext4_xattr_inode_free_quota(inode, NULL, i->value_len);
+-			goto out;
+-		}
+-	}
+ 
+-	if (old_ea_inode) {
+ 		/* We are ready to release ref count on the old_ea_inode. */
+ 		ret = ext4_xattr_inode_dec_ref(handle, old_ea_inode);
+-		if (ret) {
+-			/* Release newly required ref count on new_ea_inode. */
+-			if (new_ea_inode) {
+-				int err;
+-
+-				err = ext4_xattr_inode_dec_ref(handle,
+-							       new_ea_inode);
+-				if (err)
+-					ext4_warning_inode(new_ea_inode,
+-						  "dec ref new_ea_inode err=%d",
+-						  err);
+-				ext4_xattr_inode_free_quota(inode, new_ea_inode,
+-							    i->value_len);
+-			}
++		if (ret)
+ 			goto out;
+-		}
+ 
+ 		ext4_xattr_inode_free_quota(inode, old_ea_inode,
+ 					    le32_to_cpu(here->e_value_size));
+@@ -1874,7 +1845,6 @@ static int ext4_xattr_set_entry(struct ext4_xattr_info *i,
+ 	ret = 0;
+ out:
+ 	iput(old_ea_inode);
+-	iput(new_ea_inode);
+ 	return ret;
+ }
+ 
+@@ -1937,9 +1907,21 @@ ext4_xattr_block_set(handle_t *handle, struct inode *inode,
+ 	size_t old_ea_inode_quota = 0;
+ 	unsigned int ea_ino;
+ 
+-
+ #define header(x) ((struct ext4_xattr_header *)(x))
+ 
++	/* If we need EA inode, prepare it before locking the buffer */
++	if (i->value && i->in_inode) {
++		WARN_ON_ONCE(!i->value_len);
++
++		ea_inode = ext4_xattr_inode_lookup_create(handle, inode,
++					i->value, i->value_len);
++		if (IS_ERR(ea_inode)) {
++			error = PTR_ERR(ea_inode);
++			ea_inode = NULL;
++			goto cleanup;
++		}
++	}
++
+ 	if (s->base) {
+ 		int offset = (char *)s->here - bs->bh->b_data;
+ 
+@@ -1948,6 +1930,7 @@ ext4_xattr_block_set(handle_t *handle, struct inode *inode,
+ 						      EXT4_JTR_NONE);
+ 		if (error)
+ 			goto cleanup;
++
+ 		lock_buffer(bs->bh);
+ 
+ 		if (header(s->base)->h_refcount == cpu_to_le32(1)) {
+@@ -1974,7 +1957,7 @@ ext4_xattr_block_set(handle_t *handle, struct inode *inode,
+ 			}
+ 			ea_bdebug(bs->bh, "modifying in-place");
+ 			error = ext4_xattr_set_entry(i, s, handle, inode,
+-						     true /* is_block */);
++					     ea_inode, true /* is_block */);
+ 			ext4_xattr_block_csum_set(inode, bs->bh);
+ 			unlock_buffer(bs->bh);
+ 			if (error == -EFSCORRUPTED)
+@@ -2042,29 +2025,13 @@ ext4_xattr_block_set(handle_t *handle, struct inode *inode,
+ 		s->end = s->base + sb->s_blocksize;
+ 	}
+ 
+-	error = ext4_xattr_set_entry(i, s, handle, inode, true /* is_block */);
++	error = ext4_xattr_set_entry(i, s, handle, inode, ea_inode,
++				     true /* is_block */);
+ 	if (error == -EFSCORRUPTED)
+ 		goto bad_block;
+ 	if (error)
+ 		goto cleanup;
+ 
+-	if (i->value && s->here->e_value_inum) {
+-		/*
+-		 * A ref count on ea_inode has been taken as part of the call to
+-		 * ext4_xattr_set_entry() above. We would like to drop this
+-		 * extra ref but we have to wait until the xattr block is
+-		 * initialized and has its own ref count on the ea_inode.
+-		 */
+-		ea_ino = le32_to_cpu(s->here->e_value_inum);
+-		error = ext4_xattr_inode_iget(inode, ea_ino,
+-					      le32_to_cpu(s->here->e_hash),
+-					      &ea_inode);
+-		if (error) {
+-			ea_inode = NULL;
+-			goto cleanup;
+-		}
+-	}
+-
+ inserted:
+ 	if (!IS_LAST_ENTRY(s->first)) {
+ 		new_bh = ext4_xattr_block_cache_find(inode, header(s->base),
+@@ -2217,17 +2184,16 @@ ext4_xattr_block_set(handle_t *handle, struct inode *inode,
+ 
+ cleanup:
+ 	if (ea_inode) {
+-		int error2;
+-
+-		error2 = ext4_xattr_inode_dec_ref(handle, ea_inode);
+-		if (error2)
+-			ext4_warning_inode(ea_inode, "dec ref error=%d",
+-					   error2);
++		if (error) {
++			int error2;
+ 
+-		/* If there was an error, revert the quota charge. */
+-		if (error)
++			error2 = ext4_xattr_inode_dec_ref(handle, ea_inode);
++			if (error2)
++				ext4_warning_inode(ea_inode, "dec ref error=%d",
++						   error2);
+ 			ext4_xattr_inode_free_quota(inode, ea_inode,
+ 						    i_size_read(ea_inode));
++		}
+ 		iput(ea_inode);
+ 	}
+ 	if (ce)
+@@ -2285,14 +2251,38 @@ int ext4_xattr_ibody_set(handle_t *handle, struct inode *inode,
+ {
+ 	struct ext4_xattr_ibody_header *header;
+ 	struct ext4_xattr_search *s = &is->s;
++	struct inode *ea_inode = NULL;
+ 	int error;
+ 
+ 	if (!EXT4_INODE_HAS_XATTR_SPACE(inode))
+ 		return -ENOSPC;
+ 
+-	error = ext4_xattr_set_entry(i, s, handle, inode, false /* is_block */);
+-	if (error)
++	/* If we need EA inode, prepare it before locking the buffer */
++	if (i->value && i->in_inode) {
++		WARN_ON_ONCE(!i->value_len);
++
++		ea_inode = ext4_xattr_inode_lookup_create(handle, inode,
++					i->value, i->value_len);
++		if (IS_ERR(ea_inode))
++			return PTR_ERR(ea_inode);
++	}
++	error = ext4_xattr_set_entry(i, s, handle, inode, ea_inode,
++				     false /* is_block */);
++	if (error) {
++		if (ea_inode) {
++			int error2;
++
++			error2 = ext4_xattr_inode_dec_ref(handle, ea_inode);
++			if (error2)
++				ext4_warning_inode(ea_inode, "dec ref error=%d",
++						   error2);
++
++			ext4_xattr_inode_free_quota(inode, ea_inode,
++						    i_size_read(ea_inode));
++			iput(ea_inode);
++		}
+ 		return error;
++	}
+ 	header = IHDR(inode, ext4_raw_inode(&is->iloc));
+ 	if (!IS_LAST_ENTRY(s->first)) {
+ 		header->h_magic = cpu_to_le32(EXT4_XATTR_MAGIC);
+@@ -2301,6 +2291,7 @@ int ext4_xattr_ibody_set(handle_t *handle, struct inode *inode,
+ 		header->h_magic = cpu_to_le32(0);
+ 		ext4_clear_inode_state(inode, EXT4_STATE_XATTR);
+ 	}
++	iput(ea_inode);
+ 	return 0;
+ }
+ 
+diff --git a/fs/f2fs/extent_cache.c b/fs/f2fs/extent_cache.c
+index ad8dfac73bd446..6a9a470345bfc7 100644
+--- a/fs/f2fs/extent_cache.c
++++ b/fs/f2fs/extent_cache.c
+@@ -19,34 +19,24 @@
+ #include "node.h"
+ #include <trace/events/f2fs.h>
+ 
+-bool sanity_check_extent_cache(struct inode *inode)
++bool sanity_check_extent_cache(struct inode *inode, struct page *ipage)
+ {
+ 	struct f2fs_sb_info *sbi = F2FS_I_SB(inode);
+-	struct f2fs_inode_info *fi = F2FS_I(inode);
+-	struct extent_tree *et = fi->extent_tree[EX_READ];
+-	struct extent_info *ei;
+-
+-	if (!et)
+-		return true;
++	struct f2fs_extent *i_ext = &F2FS_INODE(ipage)->i_ext;
++	struct extent_info ei;
+ 
+-	ei = &et->largest;
+-	if (!ei->len)
+-		return true;
++	get_read_extent_info(&ei, i_ext);
+ 
+-	/* Let's drop, if checkpoint got corrupted. */
+-	if (is_set_ckpt_flags(sbi, CP_ERROR_FLAG)) {
+-		ei->len = 0;
+-		et->largest_updated = true;
++	if (!ei.len)
+ 		return true;
+-	}
+ 
+-	if (!f2fs_is_valid_blkaddr(sbi, ei->blk, DATA_GENERIC_ENHANCE) ||
+-	    !f2fs_is_valid_blkaddr(sbi, ei->blk + ei->len - 1,
++	if (!f2fs_is_valid_blkaddr(sbi, ei.blk, DATA_GENERIC_ENHANCE) ||
++	    !f2fs_is_valid_blkaddr(sbi, ei.blk + ei.len - 1,
+ 					DATA_GENERIC_ENHANCE)) {
+ 		set_sbi_flag(sbi, SBI_NEED_FSCK);
+ 		f2fs_warn(sbi, "%s: inode (ino=%lx) extent info [%u, %u, %u] is incorrect, run fsck to fix",
+ 			  __func__, inode->i_ino,
+-			  ei->blk, ei->fofs, ei->len);
++			  ei.blk, ei.fofs, ei.len);
+ 		return false;
+ 	}
+ 	return true;
+@@ -395,24 +385,22 @@ void f2fs_init_read_extent_tree(struct inode *inode, struct page *ipage)
+ 
+ 	if (!__may_extent_tree(inode, EX_READ)) {
+ 		/* drop largest read extent */
+-		if (i_ext && i_ext->len) {
++		if (i_ext->len) {
+ 			f2fs_wait_on_page_writeback(ipage, NODE, true, true);
+ 			i_ext->len = 0;
+ 			set_page_dirty(ipage);
+ 		}
+-		goto out;
++		set_inode_flag(inode, FI_NO_EXTENT);
++		return;
+ 	}
+ 
+ 	et = __grab_extent_tree(inode, EX_READ);
+ 
+-	if (!i_ext || !i_ext->len)
+-		goto out;
+-
+ 	get_read_extent_info(&ei, i_ext);
+ 
+ 	write_lock(&et->lock);
+-	if (atomic_read(&et->node_cnt))
+-		goto unlock_out;
++	if (atomic_read(&et->node_cnt) || !ei.len)
++		goto skip;
+ 
+ 	en = __attach_extent_node(sbi, et, &ei, NULL,
+ 				&et->root.rb_root.rb_node, true);
+@@ -424,11 +412,13 @@ void f2fs_init_read_extent_tree(struct inode *inode, struct page *ipage)
+ 		list_add_tail(&en->list, &eti->extent_list);
+ 		spin_unlock(&eti->extent_lock);
+ 	}
+-unlock_out:
++skip:
++	/* Let's drop, if checkpoint got corrupted. */
++	if (f2fs_cp_error(sbi)) {
++		et->largest.len = 0;
++		et->largest_updated = true;
++	}
+ 	write_unlock(&et->lock);
+-out:
+-	if (!F2FS_I(inode)->extent_tree[EX_READ])
+-		set_inode_flag(inode, FI_NO_EXTENT);
+ }
+ 
+ void f2fs_init_age_extent_tree(struct inode *inode)
+diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h
+index 19490dd8321943..00eff023cd9d63 100644
+--- a/fs/f2fs/f2fs.h
++++ b/fs/f2fs/f2fs.h
+@@ -4189,7 +4189,7 @@ void f2fs_leave_shrinker(struct f2fs_sb_info *sbi);
+ /*
+  * extent_cache.c
+  */
+-bool sanity_check_extent_cache(struct inode *inode);
++bool sanity_check_extent_cache(struct inode *inode, struct page *ipage);
+ void f2fs_init_extent_tree(struct inode *inode);
+ void f2fs_drop_extent_tree(struct inode *inode);
+ void f2fs_destroy_extent_node(struct inode *inode);
+diff --git a/fs/f2fs/gc.c b/fs/f2fs/gc.c
+index afb7c88ba06b2c..888c301ffe8f4c 100644
+--- a/fs/f2fs/gc.c
++++ b/fs/f2fs/gc.c
+@@ -1563,6 +1563,16 @@ static int gc_data_segment(struct f2fs_sb_info *sbi, struct f2fs_summary *sum,
+ 				continue;
+ 			}
+ 
++			if (f2fs_has_inline_data(inode)) {
++				iput(inode);
++				set_sbi_flag(sbi, SBI_NEED_FSCK);
++				f2fs_err_ratelimited(sbi,
++					"inode %lx has both inline_data flag and "
++					"data block, nid=%u, ofs_in_node=%u",
++					inode->i_ino, dni.nid, ofs_in_node);
++				continue;
++			}
++
+ 			err = f2fs_gc_pinned_control(inode, gc_type, segno);
+ 			if (err == -EAGAIN) {
+ 				iput(inode);
+diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c
+index 0172f4e503061d..26e857fee631d9 100644
+--- a/fs/f2fs/inode.c
++++ b/fs/f2fs/inode.c
+@@ -511,16 +511,16 @@ static int do_read_inode(struct inode *inode)
+ 
+ 	init_idisk_time(inode);
+ 
+-	/* Need all the flag bits */
+-	f2fs_init_read_extent_tree(inode, node_page);
+-	f2fs_init_age_extent_tree(inode);
+-
+-	if (!sanity_check_extent_cache(inode)) {
++	if (!sanity_check_extent_cache(inode, node_page)) {
+ 		f2fs_put_page(node_page, 1);
+ 		f2fs_handle_error(sbi, ERROR_CORRUPTED_INODE);
+ 		return -EFSCORRUPTED;
+ 	}
+ 
++	/* Need all the flag bits */
++	f2fs_init_read_extent_tree(inode, node_page);
++	f2fs_init_age_extent_tree(inode);
++
+ 	f2fs_put_page(node_page, 1);
+ 
+ 	stat_inc_inline_xattr(inode);
+diff --git a/fs/fhandle.c b/fs/fhandle.c
+index 99dcf07cfecfe1..c361d7ff1b88dd 100644
+--- a/fs/fhandle.c
++++ b/fs/fhandle.c
+@@ -40,7 +40,7 @@ static long do_sys_name_to_handle(const struct path *path,
+ 	if (f_handle.handle_bytes > MAX_HANDLE_SZ)
+ 		return -EINVAL;
+ 
+-	handle = kzalloc(sizeof(struct file_handle) + f_handle.handle_bytes,
++	handle = kzalloc(struct_size(handle, f_handle, f_handle.handle_bytes),
+ 			 GFP_KERNEL);
+ 	if (!handle)
+ 		return -ENOMEM;
+@@ -75,7 +75,7 @@ static long do_sys_name_to_handle(const struct path *path,
+ 	/* copy the mount id */
+ 	if (put_user(real_mount(path->mnt)->mnt_id, mnt_id) ||
+ 	    copy_to_user(ufh, handle,
+-			 sizeof(struct file_handle) + handle_bytes))
++			 struct_size(handle, f_handle, handle_bytes)))
+ 		retval = -EFAULT;
+ 	kfree(handle);
+ 	return retval;
+@@ -196,7 +196,7 @@ static int handle_to_path(int mountdirfd, struct file_handle __user *ufh,
+ 		retval = -EINVAL;
+ 		goto out_err;
+ 	}
+-	handle = kmalloc(sizeof(struct file_handle) + f_handle.handle_bytes,
++	handle = kmalloc(struct_size(handle, f_handle, f_handle.handle_bytes),
+ 			 GFP_KERNEL);
+ 	if (!handle) {
+ 		retval = -ENOMEM;
+diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c
+index cb3cda1390adb1..5713994328cbcb 100644
+--- a/fs/jfs/jfs_dmap.c
++++ b/fs/jfs/jfs_dmap.c
+@@ -1626,6 +1626,8 @@ s64 dbDiscardAG(struct inode *ip, int agno, s64 minlen)
+ 		} else if (rc == -ENOSPC) {
+ 			/* search for next smaller log2 block */
+ 			l2nb = BLKSTOL2(nblocks) - 1;
++			if (unlikely(l2nb < 0))
++				break;
+ 			nblocks = 1LL << l2nb;
+ 		} else {
+ 			/* Trim any already allocated blocks */
+diff --git a/fs/jfs/jfs_dtree.c b/fs/jfs/jfs_dtree.c
+index 031d8f570f581f..5d3127ca68a42d 100644
+--- a/fs/jfs/jfs_dtree.c
++++ b/fs/jfs/jfs_dtree.c
+@@ -834,6 +834,8 @@ int dtInsert(tid_t tid, struct inode *ip,
+ 	 * the full page.
+ 	 */
+ 	DT_GETSEARCH(ip, btstack->top, bn, mp, p, index);
++	if (p->header.freelist == 0)
++		return -EINVAL;
+ 
+ 	/*
+ 	 *	insert entry for new key
+diff --git a/fs/jfs/jfs_logmgr.c b/fs/jfs/jfs_logmgr.c
+index e855b8fde76ce1..cb6d1fda66a702 100644
+--- a/fs/jfs/jfs_logmgr.c
++++ b/fs/jfs/jfs_logmgr.c
+@@ -1058,7 +1058,7 @@ void jfs_syncpt(struct jfs_log *log, int hard_sync)
+ int lmLogOpen(struct super_block *sb)
+ {
+ 	int rc;
+-	struct block_device *bdev;
++	struct bdev_handle *bdev_handle;
+ 	struct jfs_log *log;
+ 	struct jfs_sb_info *sbi = JFS_SBI(sb);
+ 
+@@ -1070,7 +1070,7 @@ int lmLogOpen(struct super_block *sb)
+ 
+ 	mutex_lock(&jfs_log_mutex);
+ 	list_for_each_entry(log, &jfs_external_logs, journal_list) {
+-		if (log->bdev->bd_dev == sbi->logdev) {
++		if (log->bdev_handle->bdev->bd_dev == sbi->logdev) {
+ 			if (!uuid_equal(&log->uuid, &sbi->loguuid)) {
+ 				jfs_warn("wrong uuid on JFS journal");
+ 				mutex_unlock(&jfs_log_mutex);
+@@ -1100,14 +1100,14 @@ int lmLogOpen(struct super_block *sb)
+ 	 * file systems to log may have n-to-1 relationship;
+ 	 */
+ 
+-	bdev = blkdev_get_by_dev(sbi->logdev, BLK_OPEN_READ | BLK_OPEN_WRITE,
+-				 log, NULL);
+-	if (IS_ERR(bdev)) {
+-		rc = PTR_ERR(bdev);
++	bdev_handle = bdev_open_by_dev(sbi->logdev,
++			BLK_OPEN_READ | BLK_OPEN_WRITE, log, NULL);
++	if (IS_ERR(bdev_handle)) {
++		rc = PTR_ERR(bdev_handle);
+ 		goto free;
+ 	}
+ 
+-	log->bdev = bdev;
++	log->bdev_handle = bdev_handle;
+ 	uuid_copy(&log->uuid, &sbi->loguuid);
+ 
+ 	/*
+@@ -1141,7 +1141,7 @@ int lmLogOpen(struct super_block *sb)
+ 	lbmLogShutdown(log);
+ 
+       close:		/* close external log device */
+-	blkdev_put(bdev, log);
++	bdev_release(bdev_handle);
+ 
+       free:		/* free log descriptor */
+ 	mutex_unlock(&jfs_log_mutex);
+@@ -1162,7 +1162,7 @@ static int open_inline_log(struct super_block *sb)
+ 	init_waitqueue_head(&log->syncwait);
+ 
+ 	set_bit(log_INLINELOG, &log->flag);
+-	log->bdev = sb->s_bdev;
++	log->bdev_handle = sb->s_bdev_handle;
+ 	log->base = addressPXD(&JFS_SBI(sb)->logpxd);
+ 	log->size = lengthPXD(&JFS_SBI(sb)->logpxd) >>
+ 	    (L2LOGPSIZE - sb->s_blocksize_bits);
+@@ -1436,7 +1436,7 @@ int lmLogClose(struct super_block *sb)
+ {
+ 	struct jfs_sb_info *sbi = JFS_SBI(sb);
+ 	struct jfs_log *log = sbi->log;
+-	struct block_device *bdev;
++	struct bdev_handle *bdev_handle;
+ 	int rc = 0;
+ 
+ 	jfs_info("lmLogClose: log:0x%p", log);
+@@ -1482,10 +1482,10 @@ int lmLogClose(struct super_block *sb)
+ 	 *	external log as separate logical volume
+ 	 */
+ 	list_del(&log->journal_list);
+-	bdev = log->bdev;
++	bdev_handle = log->bdev_handle;
+ 	rc = lmLogShutdown(log);
+ 
+-	blkdev_put(bdev, log);
++	bdev_release(bdev_handle);
+ 
+ 	kfree(log);
+ 
+@@ -1972,7 +1972,7 @@ static int lbmRead(struct jfs_log * log, int pn, struct lbuf ** bpp)
+ 
+ 	bp->l_flag |= lbmREAD;
+ 
+-	bio = bio_alloc(log->bdev, 1, REQ_OP_READ, GFP_NOFS);
++	bio = bio_alloc(log->bdev_handle->bdev, 1, REQ_OP_READ, GFP_NOFS);
+ 	bio->bi_iter.bi_sector = bp->l_blkno << (log->l2bsize - 9);
+ 	__bio_add_page(bio, bp->l_page, LOGPSIZE, bp->l_offset);
+ 	BUG_ON(bio->bi_iter.bi_size != LOGPSIZE);
+@@ -2110,10 +2110,15 @@ static void lbmStartIO(struct lbuf * bp)
+ {
+ 	struct bio *bio;
+ 	struct jfs_log *log = bp->l_log;
++	struct block_device *bdev = NULL;
+ 
+ 	jfs_info("lbmStartIO");
+ 
+-	bio = bio_alloc(log->bdev, 1, REQ_OP_WRITE | REQ_SYNC, GFP_NOFS);
++	if (!log->no_integrity)
++		bdev = log->bdev_handle->bdev;
++
++	bio = bio_alloc(bdev, 1, REQ_OP_WRITE | REQ_SYNC,
++			GFP_NOFS);
+ 	bio->bi_iter.bi_sector = bp->l_blkno << (log->l2bsize - 9);
+ 	__bio_add_page(bio, bp->l_page, LOGPSIZE, bp->l_offset);
+ 	BUG_ON(bio->bi_iter.bi_size != LOGPSIZE);
+diff --git a/fs/jfs/jfs_logmgr.h b/fs/jfs/jfs_logmgr.h
+index 805877ce502044..84aa2d25390743 100644
+--- a/fs/jfs/jfs_logmgr.h
++++ b/fs/jfs/jfs_logmgr.h
+@@ -356,7 +356,7 @@ struct jfs_log {
+ 				 *    before writing syncpt.
+ 				 */
+ 	struct list_head journal_list; /* Global list */
+-	struct block_device *bdev; /* 4: log lv pointer */
++	struct bdev_handle *bdev_handle; /* 4: log lv pointer */
+ 	int serial;		/* 4: log mount serial number */
+ 
+ 	s64 base;		/* @8: log extent address (inline log ) */
+diff --git a/fs/jfs/jfs_mount.c b/fs/jfs/jfs_mount.c
+index 631b8bd3e43849..9b5c6a20b30c83 100644
+--- a/fs/jfs/jfs_mount.c
++++ b/fs/jfs/jfs_mount.c
+@@ -430,7 +430,8 @@ int updateSuper(struct super_block *sb, uint state)
+ 
+ 	if (state == FM_MOUNT) {
+ 		/* record log's dev_t and mount serial number */
+-		j_sb->s_logdev = cpu_to_le32(new_encode_dev(sbi->log->bdev->bd_dev));
++		j_sb->s_logdev = cpu_to_le32(
++			new_encode_dev(sbi->log->bdev_handle->bdev->bd_dev));
+ 		j_sb->s_logserial = cpu_to_le32(sbi->log->serial);
+ 	} else if (state == FM_CLEAN) {
+ 		/*
+diff --git a/fs/lockd/svc.c b/fs/lockd/svc.c
+index 6579948070a482..a62331487ebf16 100644
+--- a/fs/lockd/svc.c
++++ b/fs/lockd/svc.c
+@@ -712,8 +712,6 @@ static const struct svc_version *nlmsvc_version[] = {
+ #endif
+ };
+ 
+-static struct svc_stat		nlmsvc_stats;
+-
+ #define NLM_NRVERS	ARRAY_SIZE(nlmsvc_version)
+ static struct svc_program	nlmsvc_program = {
+ 	.pg_prog		= NLM_PROGRAM,		/* program number */
+@@ -721,7 +719,6 @@ static struct svc_program	nlmsvc_program = {
+ 	.pg_vers		= nlmsvc_version,	/* version table */
+ 	.pg_name		= "lockd",		/* service name */
+ 	.pg_class		= "nfsd",		/* share authentication with nfsd */
+-	.pg_stats		= &nlmsvc_stats,	/* stats table */
+ 	.pg_authenticate	= &lockd_authenticate,	/* export authentication */
+ 	.pg_init_request	= svc_generic_init_request,
+ 	.pg_rpcbind_set		= svc_generic_rpcbind_set,
+diff --git a/fs/nfs/callback.c b/fs/nfs/callback.c
+index 466ebf1d41b2b7..869c88978899c0 100644
+--- a/fs/nfs/callback.c
++++ b/fs/nfs/callback.c
+@@ -399,15 +399,12 @@ static const struct svc_version *nfs4_callback_version[] = {
+ 	[4] = &nfs4_callback_version4,
+ };
+ 
+-static struct svc_stat nfs4_callback_stats;
+-
+ static struct svc_program nfs4_callback_program = {
+ 	.pg_prog = NFS4_CALLBACK,			/* RPC service number */
+ 	.pg_nvers = ARRAY_SIZE(nfs4_callback_version),	/* Number of entries */
+ 	.pg_vers = nfs4_callback_version,		/* version table */
+ 	.pg_name = "NFSv4 callback",			/* service name */
+ 	.pg_class = "nfs",				/* authentication class */
+-	.pg_stats = &nfs4_callback_stats,
+ 	.pg_authenticate = nfs_callback_authenticate,
+ 	.pg_init_request = svc_generic_init_request,
+ 	.pg_rpcbind_set	= svc_generic_rpcbind_set,
+diff --git a/fs/nfsd/cache.h b/fs/nfsd/cache.h
+index 4cbe0434cbb8ce..66a05fefae98ea 100644
+--- a/fs/nfsd/cache.h
++++ b/fs/nfsd/cache.h
+@@ -80,8 +80,6 @@ enum {
+ 
+ int	nfsd_drc_slab_create(void);
+ void	nfsd_drc_slab_free(void);
+-int	nfsd_net_reply_cache_init(struct nfsd_net *nn);
+-void	nfsd_net_reply_cache_destroy(struct nfsd_net *nn);
+ int	nfsd_reply_cache_init(struct nfsd_net *);
+ void	nfsd_reply_cache_shutdown(struct nfsd_net *);
+ int	nfsd_cache_lookup(struct svc_rqst *rqstp, unsigned int start,
+diff --git a/fs/nfsd/export.c b/fs/nfsd/export.c
+index 11a0eaa2f91407..b7da17e530077e 100644
+--- a/fs/nfsd/export.c
++++ b/fs/nfsd/export.c
+@@ -339,12 +339,16 @@ static int export_stats_init(struct export_stats *stats)
+ 
+ static void export_stats_reset(struct export_stats *stats)
+ {
+-	nfsd_percpu_counters_reset(stats->counter, EXP_STATS_COUNTERS_NUM);
++	if (stats)
++		nfsd_percpu_counters_reset(stats->counter,
++					   EXP_STATS_COUNTERS_NUM);
+ }
+ 
+ static void export_stats_destroy(struct export_stats *stats)
+ {
+-	nfsd_percpu_counters_destroy(stats->counter, EXP_STATS_COUNTERS_NUM);
++	if (stats)
++		nfsd_percpu_counters_destroy(stats->counter,
++					     EXP_STATS_COUNTERS_NUM);
+ }
+ 
+ static void svc_export_put(struct kref *ref)
+@@ -353,7 +357,8 @@ static void svc_export_put(struct kref *ref)
+ 	path_put(&exp->ex_path);
+ 	auth_domain_put(exp->ex_client);
+ 	nfsd4_fslocs_free(&exp->ex_fslocs);
+-	export_stats_destroy(&exp->ex_stats);
++	export_stats_destroy(exp->ex_stats);
++	kfree(exp->ex_stats);
+ 	kfree(exp->ex_uuid);
+ 	kfree_rcu(exp, ex_rcu);
+ }
+@@ -767,13 +772,15 @@ static int svc_export_show(struct seq_file *m,
+ 	seq_putc(m, '\t');
+ 	seq_escape(m, exp->ex_client->name, " \t\n\\");
+ 	if (export_stats) {
+-		seq_printf(m, "\t%lld\n", exp->ex_stats.start_time);
++		struct percpu_counter *counter = exp->ex_stats->counter;
++
++		seq_printf(m, "\t%lld\n", exp->ex_stats->start_time);
+ 		seq_printf(m, "\tfh_stale: %lld\n",
+-			   percpu_counter_sum_positive(&exp->ex_stats.counter[EXP_STATS_FH_STALE]));
++			   percpu_counter_sum_positive(&counter[EXP_STATS_FH_STALE]));
+ 		seq_printf(m, "\tio_read: %lld\n",
+-			   percpu_counter_sum_positive(&exp->ex_stats.counter[EXP_STATS_IO_READ]));
++			   percpu_counter_sum_positive(&counter[EXP_STATS_IO_READ]));
+ 		seq_printf(m, "\tio_write: %lld\n",
+-			   percpu_counter_sum_positive(&exp->ex_stats.counter[EXP_STATS_IO_WRITE]));
++			   percpu_counter_sum_positive(&counter[EXP_STATS_IO_WRITE]));
+ 		seq_putc(m, '\n');
+ 		return 0;
+ 	}
+@@ -819,7 +826,7 @@ static void svc_export_init(struct cache_head *cnew, struct cache_head *citem)
+ 	new->ex_layout_types = 0;
+ 	new->ex_uuid = NULL;
+ 	new->cd = item->cd;
+-	export_stats_reset(&new->ex_stats);
++	export_stats_reset(new->ex_stats);
+ }
+ 
+ static void export_update(struct cache_head *cnew, struct cache_head *citem)
+@@ -856,7 +863,14 @@ static struct cache_head *svc_export_alloc(void)
+ 	if (!i)
+ 		return NULL;
+ 
+-	if (export_stats_init(&i->ex_stats)) {
++	i->ex_stats = kmalloc(sizeof(*(i->ex_stats)), GFP_KERNEL);
++	if (!i->ex_stats) {
++		kfree(i);
++		return NULL;
++	}
++
++	if (export_stats_init(i->ex_stats)) {
++		kfree(i->ex_stats);
+ 		kfree(i);
+ 		return NULL;
+ 	}
+diff --git a/fs/nfsd/export.h b/fs/nfsd/export.h
+index 2df8ae25aad302..ca9dc230ae3d0b 100644
+--- a/fs/nfsd/export.h
++++ b/fs/nfsd/export.h
+@@ -64,10 +64,10 @@ struct svc_export {
+ 	struct cache_head	h;
+ 	struct auth_domain *	ex_client;
+ 	int			ex_flags;
++	int			ex_fsid;
+ 	struct path		ex_path;
+ 	kuid_t			ex_anon_uid;
+ 	kgid_t			ex_anon_gid;
+-	int			ex_fsid;
+ 	unsigned char *		ex_uuid; /* 16 byte fsid */
+ 	struct nfsd4_fs_locations ex_fslocs;
+ 	uint32_t		ex_nflavors;
+@@ -76,8 +76,8 @@ struct svc_export {
+ 	struct nfsd4_deviceid_map *ex_devid_map;
+ 	struct cache_detail	*cd;
+ 	struct rcu_head		ex_rcu;
+-	struct export_stats	ex_stats;
+ 	unsigned long		ex_xprtsec_modes;
++	struct export_stats	*ex_stats;
+ };
+ 
+ /* an "export key" (expkey) maps a filehandlefragement to an
+diff --git a/fs/nfsd/netns.h b/fs/nfsd/netns.h
+index ec49b200b79762..9bfca3dda63d33 100644
+--- a/fs/nfsd/netns.h
++++ b/fs/nfsd/netns.h
+@@ -11,8 +11,10 @@
+ #include <net/net_namespace.h>
+ #include <net/netns/generic.h>
+ #include <linux/filelock.h>
++#include <linux/nfs4.h>
+ #include <linux/percpu_counter.h>
+ #include <linux/siphash.h>
++#include <linux/sunrpc/stats.h>
+ 
+ /* Hash tables for nfs4_clientid state */
+ #define CLIENT_HASH_BITS                 4
+@@ -26,10 +28,22 @@ struct nfsd4_client_tracking_ops;
+ 
+ enum {
+ 	/* cache misses due only to checksum comparison failures */
+-	NFSD_NET_PAYLOAD_MISSES,
++	NFSD_STATS_PAYLOAD_MISSES,
+ 	/* amount of memory (in bytes) currently consumed by the DRC */
+-	NFSD_NET_DRC_MEM_USAGE,
+-	NFSD_NET_COUNTERS_NUM
++	NFSD_STATS_DRC_MEM_USAGE,
++	NFSD_STATS_RC_HITS,		/* repcache hits */
++	NFSD_STATS_RC_MISSES,		/* repcache misses */
++	NFSD_STATS_RC_NOCACHE,		/* uncached reqs */
++	NFSD_STATS_FH_STALE,		/* FH stale error */
++	NFSD_STATS_IO_READ,		/* bytes returned to read requests */
++	NFSD_STATS_IO_WRITE,		/* bytes passed in write requests */
++#ifdef CONFIG_NFSD_V4
++	NFSD_STATS_FIRST_NFS4_OP,	/* count of individual nfsv4 operations */
++	NFSD_STATS_LAST_NFS4_OP = NFSD_STATS_FIRST_NFS4_OP + LAST_NFS4_OP,
++#define NFSD_STATS_NFS4_OP(op)	(NFSD_STATS_FIRST_NFS4_OP + (op))
++	NFSD_STATS_WDELEG_GETATTR,	/* count of getattr conflict with wdeleg */
++#endif
++	NFSD_STATS_COUNTERS_NUM
+ };
+ 
+ /*
+@@ -169,7 +183,10 @@ struct nfsd_net {
+ 	atomic_t                 num_drc_entries;
+ 
+ 	/* Per-netns stats counters */
+-	struct percpu_counter    counter[NFSD_NET_COUNTERS_NUM];
++	struct percpu_counter    counter[NFSD_STATS_COUNTERS_NUM];
++
++	/* sunrpc svc stats */
++	struct svc_stat          nfsd_svcstats;
+ 
+ 	/* longest hash chain seen */
+ 	unsigned int             longest_chain;
+diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c
+index 451026f9986b61..ae0057c54ef4ed 100644
+--- a/fs/nfsd/nfs4proc.c
++++ b/fs/nfsd/nfs4proc.c
+@@ -2478,10 +2478,10 @@ nfsd4_proc_null(struct svc_rqst *rqstp)
+ 	return rpc_success;
+ }
+ 
+-static inline void nfsd4_increment_op_stats(u32 opnum)
++static inline void nfsd4_increment_op_stats(struct nfsd_net *nn, u32 opnum)
+ {
+ 	if (opnum >= FIRST_NFS4_OP && opnum <= LAST_NFS4_OP)
+-		percpu_counter_inc(&nfsdstats.counter[NFSD_STATS_NFS4_OP(opnum)]);
++		percpu_counter_inc(&nn->counter[NFSD_STATS_NFS4_OP(opnum)]);
+ }
+ 
+ static const struct nfsd4_operation nfsd4_ops[];
+@@ -2756,7 +2756,7 @@ nfsd4_proc_compound(struct svc_rqst *rqstp)
+ 					   status, nfsd4_op_name(op->opnum));
+ 
+ 		nfsd4_cstate_clear_replay(cstate);
+-		nfsd4_increment_op_stats(op->opnum);
++		nfsd4_increment_op_stats(nn, op->opnum);
+ 	}
+ 
+ 	fh_put(current_fh);
+diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c
+index c7e52d980cd75f..cdad1eaa4a3180 100644
+--- a/fs/nfsd/nfs4state.c
++++ b/fs/nfsd/nfs4state.c
+@@ -8422,6 +8422,7 @@ __be32
+ nfsd4_deleg_getattr_conflict(struct svc_rqst *rqstp, struct inode *inode)
+ {
+ 	__be32 status;
++	struct nfsd_net *nn = net_generic(SVC_NET(rqstp), nfsd_net_id);
+ 	struct file_lock_context *ctx;
+ 	struct file_lock *fl;
+ 	struct nfs4_delegation *dp;
+@@ -8451,7 +8452,7 @@ nfsd4_deleg_getattr_conflict(struct svc_rqst *rqstp, struct inode *inode)
+ 			}
+ break_lease:
+ 			spin_unlock(&ctx->flc_lock);
+-			nfsd_stats_wdeleg_getattr_inc();
++			nfsd_stats_wdeleg_getattr_inc(nn);
+ 			status = nfserrno(nfsd_open_break_lease(inode, NFSD_MAY_READ));
+ 			if (status != nfserr_jukebox ||
+ 					!nfsd_wait_for_delegreturn(rqstp, inode))
+diff --git a/fs/nfsd/nfscache.c b/fs/nfsd/nfscache.c
+index 6cd36af2f97e10..c52132ecb339d5 100644
+--- a/fs/nfsd/nfscache.c
++++ b/fs/nfsd/nfscache.c
+@@ -176,27 +176,6 @@ void nfsd_drc_slab_free(void)
+ 	kmem_cache_destroy(drc_slab);
+ }
+ 
+-/**
+- * nfsd_net_reply_cache_init - per net namespace reply cache set-up
+- * @nn: nfsd_net being initialized
+- *
+- * Returns zero on succes; otherwise a negative errno is returned.
+- */
+-int nfsd_net_reply_cache_init(struct nfsd_net *nn)
+-{
+-	return nfsd_percpu_counters_init(nn->counter, NFSD_NET_COUNTERS_NUM);
+-}
+-
+-/**
+- * nfsd_net_reply_cache_destroy - per net namespace reply cache tear-down
+- * @nn: nfsd_net being freed
+- *
+- */
+-void nfsd_net_reply_cache_destroy(struct nfsd_net *nn)
+-{
+-	nfsd_percpu_counters_destroy(nn->counter, NFSD_NET_COUNTERS_NUM);
+-}
+-
+ int nfsd_reply_cache_init(struct nfsd_net *nn)
+ {
+ 	unsigned int hashsize;
+@@ -502,7 +481,7 @@ nfsd_cache_insert(struct nfsd_drc_bucket *b, struct nfsd_cacherep *key,
+ int nfsd_cache_lookup(struct svc_rqst *rqstp, unsigned int start,
+ 		      unsigned int len, struct nfsd_cacherep **cacherep)
+ {
+-	struct nfsd_net		*nn;
++	struct nfsd_net		*nn = net_generic(SVC_NET(rqstp), nfsd_net_id);
+ 	struct nfsd_cacherep	*rp, *found;
+ 	__wsum			csum;
+ 	struct nfsd_drc_bucket	*b;
+@@ -512,7 +491,7 @@ int nfsd_cache_lookup(struct svc_rqst *rqstp, unsigned int start,
+ 	int rtn = RC_DOIT;
+ 
+ 	if (type == RC_NOCACHE) {
+-		nfsd_stats_rc_nocache_inc();
++		nfsd_stats_rc_nocache_inc(nn);
+ 		goto out;
+ 	}
+ 
+@@ -522,7 +501,6 @@ int nfsd_cache_lookup(struct svc_rqst *rqstp, unsigned int start,
+ 	 * Since the common case is a cache miss followed by an insert,
+ 	 * preallocate an entry.
+ 	 */
+-	nn = net_generic(SVC_NET(rqstp), nfsd_net_id);
+ 	rp = nfsd_cacherep_alloc(rqstp, csum, nn);
+ 	if (!rp)
+ 		goto out;
+@@ -540,7 +518,7 @@ int nfsd_cache_lookup(struct svc_rqst *rqstp, unsigned int start,
+ 	freed = nfsd_cacherep_dispose(&dispose);
+ 	trace_nfsd_drc_gc(nn, freed);
+ 
+-	nfsd_stats_rc_misses_inc();
++	nfsd_stats_rc_misses_inc(nn);
+ 	atomic_inc(&nn->num_drc_entries);
+ 	nfsd_stats_drc_mem_usage_add(nn, sizeof(*rp));
+ 	goto out;
+@@ -548,7 +526,7 @@ int nfsd_cache_lookup(struct svc_rqst *rqstp, unsigned int start,
+ found_entry:
+ 	/* We found a matching entry which is either in progress or done. */
+ 	nfsd_reply_cache_free_locked(NULL, rp, nn);
+-	nfsd_stats_rc_hits_inc();
++	nfsd_stats_rc_hits_inc(nn);
+ 	rtn = RC_DROPIT;
+ 	rp = found;
+ 
+@@ -690,15 +668,15 @@ int nfsd_reply_cache_stats_show(struct seq_file *m, void *v)
+ 		   atomic_read(&nn->num_drc_entries));
+ 	seq_printf(m, "hash buckets:          %u\n", 1 << nn->maskbits);
+ 	seq_printf(m, "mem usage:             %lld\n",
+-		   percpu_counter_sum_positive(&nn->counter[NFSD_NET_DRC_MEM_USAGE]));
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_DRC_MEM_USAGE]));
+ 	seq_printf(m, "cache hits:            %lld\n",
+-		   percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_RC_HITS]));
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_RC_HITS]));
+ 	seq_printf(m, "cache misses:          %lld\n",
+-		   percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_RC_MISSES]));
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_RC_MISSES]));
+ 	seq_printf(m, "not cached:            %lld\n",
+-		   percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_RC_NOCACHE]));
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_RC_NOCACHE]));
+ 	seq_printf(m, "payload misses:        %lld\n",
+-		   percpu_counter_sum_positive(&nn->counter[NFSD_NET_PAYLOAD_MISSES]));
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_PAYLOAD_MISSES]));
+ 	seq_printf(m, "longest chain len:     %u\n", nn->longest_chain);
+ 	seq_printf(m, "cachesize at longest:  %u\n", nn->longest_chain_cachesize);
+ 	return 0;
+diff --git a/fs/nfsd/nfsctl.c b/fs/nfsd/nfsctl.c
+index a13e81e450718a..887035b7446763 100644
+--- a/fs/nfsd/nfsctl.c
++++ b/fs/nfsd/nfsctl.c
+@@ -1524,14 +1524,17 @@ static __net_init int nfsd_net_init(struct net *net)
+ 	retval = nfsd_idmap_init(net);
+ 	if (retval)
+ 		goto out_idmap_error;
+-	retval = nfsd_net_reply_cache_init(nn);
++	retval = nfsd_stat_counters_init(nn);
+ 	if (retval)
+ 		goto out_repcache_error;
++	memset(&nn->nfsd_svcstats, 0, sizeof(nn->nfsd_svcstats));
++	nn->nfsd_svcstats.program = &nfsd_program;
+ 	nn->nfsd_versions = NULL;
+ 	nn->nfsd4_minorversions = NULL;
+ 	nfsd4_init_leases_net(nn);
+ 	get_random_bytes(&nn->siphash_key, sizeof(nn->siphash_key));
+ 	seqlock_init(&nn->writeverf_lock);
++	nfsd_proc_stat_init(net);
+ 
+ 	return 0;
+ 
+@@ -1552,7 +1555,8 @@ static __net_exit void nfsd_net_exit(struct net *net)
+ {
+ 	struct nfsd_net *nn = net_generic(net, nfsd_net_id);
+ 
+-	nfsd_net_reply_cache_destroy(nn);
++	nfsd_proc_stat_shutdown(net);
++	nfsd_stat_counters_destroy(nn);
+ 	nfsd_idmap_shutdown(net);
+ 	nfsd_export_shutdown(net);
+ 	nfsd_netns_free_versions(nn);
+@@ -1575,12 +1579,9 @@ static int __init init_nfsd(void)
+ 	retval = nfsd4_init_pnfs();
+ 	if (retval)
+ 		goto out_free_slabs;
+-	retval = nfsd_stat_init();	/* Statistics */
+-	if (retval)
+-		goto out_free_pnfs;
+ 	retval = nfsd_drc_slab_create();
+ 	if (retval)
+-		goto out_free_stat;
++		goto out_free_pnfs;
+ 	nfsd_lockd_init();	/* lockd->nfsd callbacks */
+ 	retval = create_proc_exports_entry();
+ 	if (retval)
+@@ -1610,8 +1611,6 @@ static int __init init_nfsd(void)
+ out_free_lockd:
+ 	nfsd_lockd_shutdown();
+ 	nfsd_drc_slab_free();
+-out_free_stat:
+-	nfsd_stat_shutdown();
+ out_free_pnfs:
+ 	nfsd4_exit_pnfs();
+ out_free_slabs:
+@@ -1628,7 +1627,6 @@ static void __exit exit_nfsd(void)
+ 	nfsd_drc_slab_free();
+ 	remove_proc_entry("fs/nfs/exports", NULL);
+ 	remove_proc_entry("fs/nfs", NULL);
+-	nfsd_stat_shutdown();
+ 	nfsd_lockd_shutdown();
+ 	nfsd4_free_slabs();
+ 	nfsd4_exit_pnfs();
+diff --git a/fs/nfsd/nfsd.h b/fs/nfsd/nfsd.h
+index fe846a360ae18d..d05bd2b811f377 100644
+--- a/fs/nfsd/nfsd.h
++++ b/fs/nfsd/nfsd.h
+@@ -69,6 +69,7 @@ extern struct mutex		nfsd_mutex;
+ extern spinlock_t		nfsd_drc_lock;
+ extern unsigned long		nfsd_drc_max_mem;
+ extern unsigned long		nfsd_drc_mem_used;
++extern atomic_t			nfsd_th_cnt;		/* number of available threads */
+ 
+ extern const struct seq_operations nfs_exports_op;
+ 
+diff --git a/fs/nfsd/nfsfh.c b/fs/nfsd/nfsfh.c
+index 937be276bb6b48..c2495d98c18928 100644
+--- a/fs/nfsd/nfsfh.c
++++ b/fs/nfsd/nfsfh.c
+@@ -327,6 +327,7 @@ static __be32 nfsd_set_fh_dentry(struct svc_rqst *rqstp, struct svc_fh *fhp)
+ __be32
+ fh_verify(struct svc_rqst *rqstp, struct svc_fh *fhp, umode_t type, int access)
+ {
++	struct nfsd_net *nn = net_generic(SVC_NET(rqstp), nfsd_net_id);
+ 	struct svc_export *exp = NULL;
+ 	struct dentry	*dentry;
+ 	__be32		error;
+@@ -395,7 +396,7 @@ fh_verify(struct svc_rqst *rqstp, struct svc_fh *fhp, umode_t type, int access)
+ out:
+ 	trace_nfsd_fh_verify_err(rqstp, fhp, type, access, error);
+ 	if (error == nfserr_stale)
+-		nfsd_stats_fh_stale_inc(exp);
++		nfsd_stats_fh_stale_inc(nn, exp);
+ 	return error;
+ }
+ 
+diff --git a/fs/nfsd/nfssvc.c b/fs/nfsd/nfssvc.c
+index 7ef6af908faacb..7911c4b3b5d355 100644
+--- a/fs/nfsd/nfssvc.c
++++ b/fs/nfsd/nfssvc.c
+@@ -34,6 +34,7 @@
+ 
+ #define NFSDDBG_FACILITY	NFSDDBG_SVC
+ 
++atomic_t			nfsd_th_cnt = ATOMIC_INIT(0);
+ extern struct svc_program	nfsd_program;
+ static int			nfsd(void *vrqstp);
+ #if defined(CONFIG_NFSD_V2_ACL) || defined(CONFIG_NFSD_V3_ACL)
+@@ -89,7 +90,6 @@ unsigned long	nfsd_drc_max_mem;
+ unsigned long	nfsd_drc_mem_used;
+ 
+ #if defined(CONFIG_NFSD_V2_ACL) || defined(CONFIG_NFSD_V3_ACL)
+-static struct svc_stat	nfsd_acl_svcstats;
+ static const struct svc_version *nfsd_acl_version[] = {
+ # if defined(CONFIG_NFSD_V2_ACL)
+ 	[2] = &nfsd_acl_version2,
+@@ -108,15 +108,11 @@ static struct svc_program	nfsd_acl_program = {
+ 	.pg_vers		= nfsd_acl_version,
+ 	.pg_name		= "nfsacl",
+ 	.pg_class		= "nfsd",
+-	.pg_stats		= &nfsd_acl_svcstats,
+ 	.pg_authenticate	= &svc_set_client,
+ 	.pg_init_request	= nfsd_acl_init_request,
+ 	.pg_rpcbind_set		= nfsd_acl_rpcbind_set,
+ };
+ 
+-static struct svc_stat	nfsd_acl_svcstats = {
+-	.program	= &nfsd_acl_program,
+-};
+ #endif /* defined(CONFIG_NFSD_V2_ACL) || defined(CONFIG_NFSD_V3_ACL) */
+ 
+ static const struct svc_version *nfsd_version[] = {
+@@ -141,7 +137,6 @@ struct svc_program		nfsd_program = {
+ 	.pg_vers		= nfsd_version,		/* version table */
+ 	.pg_name		= "nfsd",		/* program name */
+ 	.pg_class		= "nfsd",		/* authentication class */
+-	.pg_stats		= &nfsd_svcstats,	/* version table */
+ 	.pg_authenticate	= &svc_set_client,	/* export authentication */
+ 	.pg_init_request	= nfsd_init_request,
+ 	.pg_rpcbind_set		= nfsd_rpcbind_set,
+@@ -675,7 +670,8 @@ int nfsd_create_serv(struct net *net)
+ 	if (nfsd_max_blksize == 0)
+ 		nfsd_max_blksize = nfsd_get_default_max_blksize();
+ 	nfsd_reset_versions(nn);
+-	serv = svc_create_pooled(&nfsd_program, nfsd_max_blksize, nfsd);
++	serv = svc_create_pooled(&nfsd_program, &nn->nfsd_svcstats,
++				 nfsd_max_blksize, nfsd);
+ 	if (serv == NULL)
+ 		return -ENOMEM;
+ 
+@@ -950,7 +946,7 @@ nfsd(void *vrqstp)
+ 
+ 	current->fs->umask = 0;
+ 
+-	atomic_inc(&nfsdstats.th_cnt);
++	atomic_inc(&nfsd_th_cnt);
+ 
+ 	set_freezable();
+ 
+@@ -964,7 +960,7 @@ nfsd(void *vrqstp)
+ 		svc_recv(rqstp);
+ 	}
+ 
+-	atomic_dec(&nfsdstats.th_cnt);
++	atomic_dec(&nfsd_th_cnt);
+ 
+ out:
+ 	/* Release the thread */
+diff --git a/fs/nfsd/stats.c b/fs/nfsd/stats.c
+index 63797635e1c328..9f606fa08bd4b8 100644
+--- a/fs/nfsd/stats.c
++++ b/fs/nfsd/stats.c
+@@ -27,25 +27,22 @@
+ 
+ #include "nfsd.h"
+ 
+-struct nfsd_stats	nfsdstats;
+-struct svc_stat		nfsd_svcstats = {
+-	.program	= &nfsd_program,
+-};
+-
+ static int nfsd_show(struct seq_file *seq, void *v)
+ {
++	struct net *net = pde_data(file_inode(seq->file));
++	struct nfsd_net *nn = net_generic(net, nfsd_net_id);
+ 	int i;
+ 
+ 	seq_printf(seq, "rc %lld %lld %lld\nfh %lld 0 0 0 0\nio %lld %lld\n",
+-		   percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_RC_HITS]),
+-		   percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_RC_MISSES]),
+-		   percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_RC_NOCACHE]),
+-		   percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_FH_STALE]),
+-		   percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_IO_READ]),
+-		   percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_IO_WRITE]));
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_RC_HITS]),
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_RC_MISSES]),
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_RC_NOCACHE]),
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_FH_STALE]),
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_IO_READ]),
++		   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_IO_WRITE]));
+ 
+ 	/* thread usage: */
+-	seq_printf(seq, "th %u 0", atomic_read(&nfsdstats.th_cnt));
++	seq_printf(seq, "th %u 0", atomic_read(&nfsd_th_cnt));
+ 
+ 	/* deprecated thread usage histogram stats */
+ 	for (i = 0; i < 10; i++)
+@@ -55,7 +52,7 @@ static int nfsd_show(struct seq_file *seq, void *v)
+ 	seq_puts(seq, "\nra 0 0 0 0 0 0 0 0 0 0 0 0\n");
+ 
+ 	/* show my rpc info */
+-	svc_seq_show(seq, &nfsd_svcstats);
++	svc_seq_show(seq, &nn->nfsd_svcstats);
+ 
+ #ifdef CONFIG_NFSD_V4
+ 	/* Show count for individual nfsv4 operations */
+@@ -63,10 +60,10 @@ static int nfsd_show(struct seq_file *seq, void *v)
+ 	seq_printf(seq,"proc4ops %u", LAST_NFS4_OP + 1);
+ 	for (i = 0; i <= LAST_NFS4_OP; i++) {
+ 		seq_printf(seq, " %lld",
+-			   percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_NFS4_OP(i)]));
++			   percpu_counter_sum_positive(&nn->counter[NFSD_STATS_NFS4_OP(i)]));
+ 	}
+ 	seq_printf(seq, "\nwdeleg_getattr %lld",
+-		percpu_counter_sum_positive(&nfsdstats.counter[NFSD_STATS_WDELEG_GETATTR]));
++		percpu_counter_sum_positive(&nn->counter[NFSD_STATS_WDELEG_GETATTR]));
+ 
+ 	seq_putc(seq, '\n');
+ #endif
+@@ -76,7 +73,7 @@ static int nfsd_show(struct seq_file *seq, void *v)
+ 
+ DEFINE_PROC_SHOW_ATTRIBUTE(nfsd);
+ 
+-int nfsd_percpu_counters_init(struct percpu_counter counters[], int num)
++int nfsd_percpu_counters_init(struct percpu_counter *counters, int num)
+ {
+ 	int i, err = 0;
+ 
+@@ -108,31 +105,24 @@ void nfsd_percpu_counters_destroy(struct percpu_counter counters[], int num)
+ 		percpu_counter_destroy(&counters[i]);
+ }
+ 
+-static int nfsd_stat_counters_init(void)
++int nfsd_stat_counters_init(struct nfsd_net *nn)
+ {
+-	return nfsd_percpu_counters_init(nfsdstats.counter, NFSD_STATS_COUNTERS_NUM);
++	return nfsd_percpu_counters_init(nn->counter, NFSD_STATS_COUNTERS_NUM);
+ }
+ 
+-static void nfsd_stat_counters_destroy(void)
++void nfsd_stat_counters_destroy(struct nfsd_net *nn)
+ {
+-	nfsd_percpu_counters_destroy(nfsdstats.counter, NFSD_STATS_COUNTERS_NUM);
++	nfsd_percpu_counters_destroy(nn->counter, NFSD_STATS_COUNTERS_NUM);
+ }
+ 
+-int nfsd_stat_init(void)
++void nfsd_proc_stat_init(struct net *net)
+ {
+-	int err;
+-
+-	err = nfsd_stat_counters_init();
+-	if (err)
+-		return err;
++	struct nfsd_net *nn = net_generic(net, nfsd_net_id);
+ 
+-	svc_proc_register(&init_net, &nfsd_svcstats, &nfsd_proc_ops);
+-
+-	return 0;
++	svc_proc_register(net, &nn->nfsd_svcstats, &nfsd_proc_ops);
+ }
+ 
+-void nfsd_stat_shutdown(void)
++void nfsd_proc_stat_shutdown(struct net *net)
+ {
+-	nfsd_stat_counters_destroy();
+-	svc_proc_unregister(&init_net, "nfsd");
++	svc_proc_unregister(net, "nfsd");
+ }
+diff --git a/fs/nfsd/stats.h b/fs/nfsd/stats.h
+index cf5524e7ca0623..d2753e975dfd34 100644
+--- a/fs/nfsd/stats.h
++++ b/fs/nfsd/stats.h
+@@ -10,94 +10,72 @@
+ #include <uapi/linux/nfsd/stats.h>
+ #include <linux/percpu_counter.h>
+ 
+-
+-enum {
+-	NFSD_STATS_RC_HITS,		/* repcache hits */
+-	NFSD_STATS_RC_MISSES,		/* repcache misses */
+-	NFSD_STATS_RC_NOCACHE,		/* uncached reqs */
+-	NFSD_STATS_FH_STALE,		/* FH stale error */
+-	NFSD_STATS_IO_READ,		/* bytes returned to read requests */
+-	NFSD_STATS_IO_WRITE,		/* bytes passed in write requests */
+-#ifdef CONFIG_NFSD_V4
+-	NFSD_STATS_FIRST_NFS4_OP,	/* count of individual nfsv4 operations */
+-	NFSD_STATS_LAST_NFS4_OP = NFSD_STATS_FIRST_NFS4_OP + LAST_NFS4_OP,
+-#define NFSD_STATS_NFS4_OP(op)	(NFSD_STATS_FIRST_NFS4_OP + (op))
+-	NFSD_STATS_WDELEG_GETATTR,	/* count of getattr conflict with wdeleg */
+-#endif
+-	NFSD_STATS_COUNTERS_NUM
+-};
+-
+-struct nfsd_stats {
+-	struct percpu_counter	counter[NFSD_STATS_COUNTERS_NUM];
+-
+-	atomic_t	th_cnt;		/* number of available threads */
+-};
+-
+-extern struct nfsd_stats	nfsdstats;
+-
+-extern struct svc_stat		nfsd_svcstats;
+-
+-int nfsd_percpu_counters_init(struct percpu_counter counters[], int num);
+-void nfsd_percpu_counters_reset(struct percpu_counter counters[], int num);
+-void nfsd_percpu_counters_destroy(struct percpu_counter counters[], int num);
+-int nfsd_stat_init(void);
+-void nfsd_stat_shutdown(void);
+-
+-static inline void nfsd_stats_rc_hits_inc(void)
++int nfsd_percpu_counters_init(struct percpu_counter *counters, int num);
++void nfsd_percpu_counters_reset(struct percpu_counter *counters, int num);
++void nfsd_percpu_counters_destroy(struct percpu_counter *counters, int num);
++int nfsd_stat_counters_init(struct nfsd_net *nn);
++void nfsd_stat_counters_destroy(struct nfsd_net *nn);
++void nfsd_proc_stat_init(struct net *net);
++void nfsd_proc_stat_shutdown(struct net *net);
++
++static inline void nfsd_stats_rc_hits_inc(struct nfsd_net *nn)
+ {
+-	percpu_counter_inc(&nfsdstats.counter[NFSD_STATS_RC_HITS]);
++	percpu_counter_inc(&nn->counter[NFSD_STATS_RC_HITS]);
+ }
+ 
+-static inline void nfsd_stats_rc_misses_inc(void)
++static inline void nfsd_stats_rc_misses_inc(struct nfsd_net *nn)
+ {
+-	percpu_counter_inc(&nfsdstats.counter[NFSD_STATS_RC_MISSES]);
++	percpu_counter_inc(&nn->counter[NFSD_STATS_RC_MISSES]);
+ }
+ 
+-static inline void nfsd_stats_rc_nocache_inc(void)
++static inline void nfsd_stats_rc_nocache_inc(struct nfsd_net *nn)
+ {
+-	percpu_counter_inc(&nfsdstats.counter[NFSD_STATS_RC_NOCACHE]);
++	percpu_counter_inc(&nn->counter[NFSD_STATS_RC_NOCACHE]);
+ }
+ 
+-static inline void nfsd_stats_fh_stale_inc(struct svc_export *exp)
++static inline void nfsd_stats_fh_stale_inc(struct nfsd_net *nn,
++					   struct svc_export *exp)
+ {
+-	percpu_counter_inc(&nfsdstats.counter[NFSD_STATS_FH_STALE]);
+-	if (exp)
+-		percpu_counter_inc(&exp->ex_stats.counter[EXP_STATS_FH_STALE]);
++	percpu_counter_inc(&nn->counter[NFSD_STATS_FH_STALE]);
++	if (exp && exp->ex_stats)
++		percpu_counter_inc(&exp->ex_stats->counter[EXP_STATS_FH_STALE]);
+ }
+ 
+-static inline void nfsd_stats_io_read_add(struct svc_export *exp, s64 amount)
++static inline void nfsd_stats_io_read_add(struct nfsd_net *nn,
++					  struct svc_export *exp, s64 amount)
+ {
+-	percpu_counter_add(&nfsdstats.counter[NFSD_STATS_IO_READ], amount);
+-	if (exp)
+-		percpu_counter_add(&exp->ex_stats.counter[EXP_STATS_IO_READ], amount);
++	percpu_counter_add(&nn->counter[NFSD_STATS_IO_READ], amount);
++	if (exp && exp->ex_stats)
++		percpu_counter_add(&exp->ex_stats->counter[EXP_STATS_IO_READ], amount);
+ }
+ 
+-static inline void nfsd_stats_io_write_add(struct svc_export *exp, s64 amount)
++static inline void nfsd_stats_io_write_add(struct nfsd_net *nn,
++					   struct svc_export *exp, s64 amount)
+ {
+-	percpu_counter_add(&nfsdstats.counter[NFSD_STATS_IO_WRITE], amount);
+-	if (exp)
+-		percpu_counter_add(&exp->ex_stats.counter[EXP_STATS_IO_WRITE], amount);
++	percpu_counter_add(&nn->counter[NFSD_STATS_IO_WRITE], amount);
++	if (exp && exp->ex_stats)
++		percpu_counter_add(&exp->ex_stats->counter[EXP_STATS_IO_WRITE], amount);
+ }
+ 
+ static inline void nfsd_stats_payload_misses_inc(struct nfsd_net *nn)
+ {
+-	percpu_counter_inc(&nn->counter[NFSD_NET_PAYLOAD_MISSES]);
++	percpu_counter_inc(&nn->counter[NFSD_STATS_PAYLOAD_MISSES]);
+ }
+ 
+ static inline void nfsd_stats_drc_mem_usage_add(struct nfsd_net *nn, s64 amount)
+ {
+-	percpu_counter_add(&nn->counter[NFSD_NET_DRC_MEM_USAGE], amount);
++	percpu_counter_add(&nn->counter[NFSD_STATS_DRC_MEM_USAGE], amount);
+ }
+ 
+ static inline void nfsd_stats_drc_mem_usage_sub(struct nfsd_net *nn, s64 amount)
+ {
+-	percpu_counter_sub(&nn->counter[NFSD_NET_DRC_MEM_USAGE], amount);
++	percpu_counter_sub(&nn->counter[NFSD_STATS_DRC_MEM_USAGE], amount);
+ }
+ 
+ #ifdef CONFIG_NFSD_V4
+-static inline void nfsd_stats_wdeleg_getattr_inc(void)
++static inline void nfsd_stats_wdeleg_getattr_inc(struct nfsd_net *nn)
+ {
+-	percpu_counter_inc(&nfsdstats.counter[NFSD_STATS_WDELEG_GETATTR]);
++	percpu_counter_inc(&nn->counter[NFSD_STATS_WDELEG_GETATTR]);
+ }
+ #endif
+ #endif /* _NFSD_STATS_H */
+diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c
+index d0fdf70ab20d36..1f2a5b22b6498e 100644
+--- a/fs/nfsd/vfs.c
++++ b/fs/nfsd/vfs.c
+@@ -985,7 +985,9 @@ static __be32 nfsd_finish_read(struct svc_rqst *rqstp, struct svc_fh *fhp,
+ 			       unsigned long *count, u32 *eof, ssize_t host_err)
+ {
+ 	if (host_err >= 0) {
+-		nfsd_stats_io_read_add(fhp->fh_export, host_err);
++		struct nfsd_net *nn = net_generic(SVC_NET(rqstp), nfsd_net_id);
++
++		nfsd_stats_io_read_add(nn, fhp->fh_export, host_err);
+ 		*eof = nfsd_eof_on_read(file, offset, host_err, *count);
+ 		*count = host_err;
+ 		fsnotify_access(file);
+@@ -1168,7 +1170,7 @@ nfsd_vfs_write(struct svc_rqst *rqstp, struct svc_fh *fhp, struct nfsd_file *nf,
+ 		goto out_nfserr;
+ 	}
+ 	*cnt = host_err;
+-	nfsd_stats_io_write_add(exp, *cnt);
++	nfsd_stats_io_write_add(nn, exp, *cnt);
+ 	fsnotify_modify(file);
+ 	host_err = filemap_check_wb_err(file->f_mapping, since);
+ 	if (host_err < 0)
+diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
+index 424865dfca74ba..45b687aff700be 100644
+--- a/fs/ntfs3/frecord.c
++++ b/fs/ntfs3/frecord.c
+@@ -1896,6 +1896,47 @@ enum REPARSE_SIGN ni_parse_reparse(struct ntfs_inode *ni, struct ATTRIB *attr,
+ 	return REPARSE_LINK;
+ }
+ 
++/*
++ * fiemap_fill_next_extent_k - a copy of fiemap_fill_next_extent
++ * but it accepts kernel address for fi_extents_start
++ */
++static int fiemap_fill_next_extent_k(struct fiemap_extent_info *fieinfo,
++				     u64 logical, u64 phys, u64 len, u32 flags)
++{
++	struct fiemap_extent extent;
++	struct fiemap_extent __user *dest = fieinfo->fi_extents_start;
++
++	/* only count the extents */
++	if (fieinfo->fi_extents_max == 0) {
++		fieinfo->fi_extents_mapped++;
++		return (flags & FIEMAP_EXTENT_LAST) ? 1 : 0;
++	}
++
++	if (fieinfo->fi_extents_mapped >= fieinfo->fi_extents_max)
++		return 1;
++
++	if (flags & FIEMAP_EXTENT_DELALLOC)
++		flags |= FIEMAP_EXTENT_UNKNOWN;
++	if (flags & FIEMAP_EXTENT_DATA_ENCRYPTED)
++		flags |= FIEMAP_EXTENT_ENCODED;
++	if (flags & (FIEMAP_EXTENT_DATA_TAIL | FIEMAP_EXTENT_DATA_INLINE))
++		flags |= FIEMAP_EXTENT_NOT_ALIGNED;
++
++	memset(&extent, 0, sizeof(extent));
++	extent.fe_logical = logical;
++	extent.fe_physical = phys;
++	extent.fe_length = len;
++	extent.fe_flags = flags;
++
++	dest += fieinfo->fi_extents_mapped;
++	memcpy(dest, &extent, sizeof(extent));
++
++	fieinfo->fi_extents_mapped++;
++	if (fieinfo->fi_extents_mapped == fieinfo->fi_extents_max)
++		return 1;
++	return (flags & FIEMAP_EXTENT_LAST) ? 1 : 0;
++}
++
+ /*
+  * ni_fiemap - Helper for file_fiemap().
+  *
+@@ -1906,6 +1947,8 @@ int ni_fiemap(struct ntfs_inode *ni, struct fiemap_extent_info *fieinfo,
+ 	      __u64 vbo, __u64 len)
+ {
+ 	int err = 0;
++	struct fiemap_extent __user *fe_u = fieinfo->fi_extents_start;
++	struct fiemap_extent *fe_k = NULL;
+ 	struct ntfs_sb_info *sbi = ni->mi.sbi;
+ 	u8 cluster_bits = sbi->cluster_bits;
+ 	struct runs_tree *run;
+@@ -1953,6 +1996,18 @@ int ni_fiemap(struct ntfs_inode *ni, struct fiemap_extent_info *fieinfo,
+ 		goto out;
+ 	}
+ 
++	/*
++	 * To avoid lock problems replace pointer to user memory by pointer to kernel memory.
++	 */
++	fe_k = kmalloc_array(fieinfo->fi_extents_max,
++			     sizeof(struct fiemap_extent),
++			     GFP_NOFS | __GFP_ZERO);
++	if (!fe_k) {
++		err = -ENOMEM;
++		goto out;
++	}
++	fieinfo->fi_extents_start = fe_k;
++
+ 	end = vbo + len;
+ 	alloc_size = le64_to_cpu(attr->nres.alloc_size);
+ 	if (end > alloc_size)
+@@ -2041,8 +2096,9 @@ int ni_fiemap(struct ntfs_inode *ni, struct fiemap_extent_info *fieinfo,
+ 			if (vbo + dlen >= end)
+ 				flags |= FIEMAP_EXTENT_LAST;
+ 
+-			err = fiemap_fill_next_extent(fieinfo, vbo, lbo, dlen,
+-						      flags);
++			err = fiemap_fill_next_extent_k(fieinfo, vbo, lbo, dlen,
++							flags);
++
+ 			if (err < 0)
+ 				break;
+ 			if (err == 1) {
+@@ -2062,7 +2118,8 @@ int ni_fiemap(struct ntfs_inode *ni, struct fiemap_extent_info *fieinfo,
+ 		if (vbo + bytes >= end)
+ 			flags |= FIEMAP_EXTENT_LAST;
+ 
+-		err = fiemap_fill_next_extent(fieinfo, vbo, lbo, bytes, flags);
++		err = fiemap_fill_next_extent_k(fieinfo, vbo, lbo, bytes,
++						flags);
+ 		if (err < 0)
+ 			break;
+ 		if (err == 1) {
+@@ -2075,7 +2132,19 @@ int ni_fiemap(struct ntfs_inode *ni, struct fiemap_extent_info *fieinfo,
+ 
+ 	up_read(run_lock);
+ 
++	/*
++	 * Copy to user memory out of lock
++	 */
++	if (copy_to_user(fe_u, fe_k,
++			 fieinfo->fi_extents_max *
++				 sizeof(struct fiemap_extent))) {
++		err = -EFAULT;
++	}
++
+ out:
++	/* Restore original pointer. */
++	fieinfo->fi_extents_start = fe_u;
++	kfree(fe_k);
+ 	return err;
+ }
+ 
+diff --git a/fs/quota/quota_tree.c b/fs/quota/quota_tree.c
+index 0f1493e0f6d059..254f6359b287fa 100644
+--- a/fs/quota/quota_tree.c
++++ b/fs/quota/quota_tree.c
+@@ -21,6 +21,12 @@ MODULE_AUTHOR("Jan Kara");
+ MODULE_DESCRIPTION("Quota trie support");
+ MODULE_LICENSE("GPL");
+ 
++/*
++ * Maximum quota tree depth we support. Only to limit recursion when working
++ * with the tree.
++ */
++#define MAX_QTREE_DEPTH 6
++
+ #define __QUOTA_QT_PARANOIA
+ 
+ static int __get_index(struct qtree_mem_dqinfo *info, qid_t id, int depth)
+@@ -327,27 +333,36 @@ static uint find_free_dqentry(struct qtree_mem_dqinfo *info,
+ 
+ /* Insert reference to structure into the trie */
+ static int do_insert_tree(struct qtree_mem_dqinfo *info, struct dquot *dquot,
+-			  uint *treeblk, int depth)
++			  uint *blks, int depth)
+ {
+ 	char *buf = kmalloc(info->dqi_usable_bs, GFP_NOFS);
+ 	int ret = 0, newson = 0, newact = 0;
+ 	__le32 *ref;
+ 	uint newblk;
++	int i;
+ 
+ 	if (!buf)
+ 		return -ENOMEM;
+-	if (!*treeblk) {
++	if (!blks[depth]) {
+ 		ret = get_free_dqblk(info);
+ 		if (ret < 0)
+ 			goto out_buf;
+-		*treeblk = ret;
++		for (i = 0; i < depth; i++)
++			if (ret == blks[i]) {
++				quota_error(dquot->dq_sb,
++					"Free block already used in tree: block %u",
++					ret);
++				ret = -EIO;
++				goto out_buf;
++			}
++		blks[depth] = ret;
+ 		memset(buf, 0, info->dqi_usable_bs);
+ 		newact = 1;
+ 	} else {
+-		ret = read_blk(info, *treeblk, buf);
++		ret = read_blk(info, blks[depth], buf);
+ 		if (ret < 0) {
+ 			quota_error(dquot->dq_sb, "Can't read tree quota "
+-				    "block %u", *treeblk);
++				    "block %u", blks[depth]);
+ 			goto out_buf;
+ 		}
+ 	}
+@@ -357,8 +372,20 @@ static int do_insert_tree(struct qtree_mem_dqinfo *info, struct dquot *dquot,
+ 			     info->dqi_blocks - 1);
+ 	if (ret)
+ 		goto out_buf;
+-	if (!newblk)
++	if (!newblk) {
+ 		newson = 1;
++	} else {
++		for (i = 0; i <= depth; i++)
++			if (newblk == blks[i]) {
++				quota_error(dquot->dq_sb,
++					"Cycle in quota tree detected: block %u index %u",
++					blks[depth],
++					get_index(info, dquot->dq_id, depth));
++				ret = -EIO;
++				goto out_buf;
++			}
++	}
++	blks[depth + 1] = newblk;
+ 	if (depth == info->dqi_qtree_depth - 1) {
+ #ifdef __QUOTA_QT_PARANOIA
+ 		if (newblk) {
+@@ -370,16 +397,16 @@ static int do_insert_tree(struct qtree_mem_dqinfo *info, struct dquot *dquot,
+ 			goto out_buf;
+ 		}
+ #endif
+-		newblk = find_free_dqentry(info, dquot, &ret);
++		blks[depth + 1] = find_free_dqentry(info, dquot, &ret);
+ 	} else {
+-		ret = do_insert_tree(info, dquot, &newblk, depth+1);
++		ret = do_insert_tree(info, dquot, blks, depth + 1);
+ 	}
+ 	if (newson && ret >= 0) {
+ 		ref[get_index(info, dquot->dq_id, depth)] =
+-							cpu_to_le32(newblk);
+-		ret = write_blk(info, *treeblk, buf);
++						cpu_to_le32(blks[depth + 1]);
++		ret = write_blk(info, blks[depth], buf);
+ 	} else if (newact && ret < 0) {
+-		put_free_dqblk(info, buf, *treeblk);
++		put_free_dqblk(info, buf, blks[depth]);
+ 	}
+ out_buf:
+ 	kfree(buf);
+@@ -390,7 +417,7 @@ static int do_insert_tree(struct qtree_mem_dqinfo *info, struct dquot *dquot,
+ static inline int dq_insert_tree(struct qtree_mem_dqinfo *info,
+ 				 struct dquot *dquot)
+ {
+-	int tmp = QT_TREEOFF;
++	uint blks[MAX_QTREE_DEPTH] = { QT_TREEOFF };
+ 
+ #ifdef __QUOTA_QT_PARANOIA
+ 	if (info->dqi_blocks <= QT_TREEOFF) {
+@@ -398,7 +425,11 @@ static inline int dq_insert_tree(struct qtree_mem_dqinfo *info,
+ 		return -EIO;
+ 	}
+ #endif
+-	return do_insert_tree(info, dquot, &tmp, 0);
++	if (info->dqi_qtree_depth >= MAX_QTREE_DEPTH) {
++		quota_error(dquot->dq_sb, "Quota tree depth too big!");
++		return -EIO;
++	}
++	return do_insert_tree(info, dquot, blks, 0);
+ }
+ 
+ /*
+@@ -511,19 +542,20 @@ static int free_dqentry(struct qtree_mem_dqinfo *info, struct dquot *dquot,
+ 
+ /* Remove reference to dquot from tree */
+ static int remove_tree(struct qtree_mem_dqinfo *info, struct dquot *dquot,
+-		       uint *blk, int depth)
++		       uint *blks, int depth)
+ {
+ 	char *buf = kmalloc(info->dqi_usable_bs, GFP_NOFS);
+ 	int ret = 0;
+ 	uint newblk;
+ 	__le32 *ref = (__le32 *)buf;
++	int i;
+ 
+ 	if (!buf)
+ 		return -ENOMEM;
+-	ret = read_blk(info, *blk, buf);
++	ret = read_blk(info, blks[depth], buf);
+ 	if (ret < 0) {
+ 		quota_error(dquot->dq_sb, "Can't read quota data block %u",
+-			    *blk);
++			    blks[depth]);
+ 		goto out_buf;
+ 	}
+ 	newblk = le32_to_cpu(ref[get_index(info, dquot->dq_id, depth)]);
+@@ -532,29 +564,38 @@ static int remove_tree(struct qtree_mem_dqinfo *info, struct dquot *dquot,
+ 	if (ret)
+ 		goto out_buf;
+ 
++	for (i = 0; i <= depth; i++)
++		if (newblk == blks[i]) {
++			quota_error(dquot->dq_sb,
++				"Cycle in quota tree detected: block %u index %u",
++				blks[depth],
++				get_index(info, dquot->dq_id, depth));
++			ret = -EIO;
++			goto out_buf;
++		}
+ 	if (depth == info->dqi_qtree_depth - 1) {
+ 		ret = free_dqentry(info, dquot, newblk);
+-		newblk = 0;
++		blks[depth + 1] = 0;
+ 	} else {
+-		ret = remove_tree(info, dquot, &newblk, depth+1);
++		blks[depth + 1] = newblk;
++		ret = remove_tree(info, dquot, blks, depth + 1);
+ 	}
+-	if (ret >= 0 && !newblk) {
+-		int i;
++	if (ret >= 0 && !blks[depth + 1]) {
+ 		ref[get_index(info, dquot->dq_id, depth)] = cpu_to_le32(0);
+ 		/* Block got empty? */
+ 		for (i = 0; i < (info->dqi_usable_bs >> 2) && !ref[i]; i++)
+ 			;
+ 		/* Don't put the root block into the free block list */
+ 		if (i == (info->dqi_usable_bs >> 2)
+-		    && *blk != QT_TREEOFF) {
+-			put_free_dqblk(info, buf, *blk);
+-			*blk = 0;
++		    && blks[depth] != QT_TREEOFF) {
++			put_free_dqblk(info, buf, blks[depth]);
++			blks[depth] = 0;
+ 		} else {
+-			ret = write_blk(info, *blk, buf);
++			ret = write_blk(info, blks[depth], buf);
+ 			if (ret < 0)
+ 				quota_error(dquot->dq_sb,
+ 					    "Can't write quota tree block %u",
+-					    *blk);
++					    blks[depth]);
+ 		}
+ 	}
+ out_buf:
+@@ -565,11 +606,15 @@ static int remove_tree(struct qtree_mem_dqinfo *info, struct dquot *dquot,
+ /* Delete dquot from tree */
+ int qtree_delete_dquot(struct qtree_mem_dqinfo *info, struct dquot *dquot)
+ {
+-	uint tmp = QT_TREEOFF;
++	uint blks[MAX_QTREE_DEPTH] = { QT_TREEOFF };
+ 
+ 	if (!dquot->dq_off)	/* Even not allocated? */
+ 		return 0;
+-	return remove_tree(info, dquot, &tmp, 0);
++	if (info->dqi_qtree_depth >= MAX_QTREE_DEPTH) {
++		quota_error(dquot->dq_sb, "Quota tree depth too big!");
++		return -EIO;
++	}
++	return remove_tree(info, dquot, blks, 0);
+ }
+ EXPORT_SYMBOL(qtree_delete_dquot);
+ 
+@@ -613,18 +658,20 @@ static loff_t find_block_dqentry(struct qtree_mem_dqinfo *info,
+ 
+ /* Find entry for given id in the tree */
+ static loff_t find_tree_dqentry(struct qtree_mem_dqinfo *info,
+-				struct dquot *dquot, uint blk, int depth)
++				struct dquot *dquot, uint *blks, int depth)
+ {
+ 	char *buf = kmalloc(info->dqi_usable_bs, GFP_NOFS);
+ 	loff_t ret = 0;
+ 	__le32 *ref = (__le32 *)buf;
++	uint blk;
++	int i;
+ 
+ 	if (!buf)
+ 		return -ENOMEM;
+-	ret = read_blk(info, blk, buf);
++	ret = read_blk(info, blks[depth], buf);
+ 	if (ret < 0) {
+ 		quota_error(dquot->dq_sb, "Can't read quota tree block %u",
+-			    blk);
++			    blks[depth]);
+ 		goto out_buf;
+ 	}
+ 	ret = 0;
+@@ -636,8 +683,19 @@ static loff_t find_tree_dqentry(struct qtree_mem_dqinfo *info,
+ 	if (ret)
+ 		goto out_buf;
+ 
++	/* Check for cycles in the tree */
++	for (i = 0; i <= depth; i++)
++		if (blk == blks[i]) {
++			quota_error(dquot->dq_sb,
++				"Cycle in quota tree detected: block %u index %u",
++				blks[depth],
++				get_index(info, dquot->dq_id, depth));
++			ret = -EIO;
++			goto out_buf;
++		}
++	blks[depth + 1] = blk;
+ 	if (depth < info->dqi_qtree_depth - 1)
+-		ret = find_tree_dqentry(info, dquot, blk, depth+1);
++		ret = find_tree_dqentry(info, dquot, blks, depth + 1);
+ 	else
+ 		ret = find_block_dqentry(info, dquot, blk);
+ out_buf:
+@@ -649,7 +707,13 @@ static loff_t find_tree_dqentry(struct qtree_mem_dqinfo *info,
+ static inline loff_t find_dqentry(struct qtree_mem_dqinfo *info,
+ 				  struct dquot *dquot)
+ {
+-	return find_tree_dqentry(info, dquot, QT_TREEOFF, 0);
++	uint blks[MAX_QTREE_DEPTH] = { QT_TREEOFF };
++
++	if (info->dqi_qtree_depth >= MAX_QTREE_DEPTH) {
++		quota_error(dquot->dq_sb, "Quota tree depth too big!");
++		return -EIO;
++	}
++	return find_tree_dqentry(info, dquot, blks, 0);
+ }
+ 
+ int qtree_read_dquot(struct qtree_mem_dqinfo *info, struct dquot *dquot)
+diff --git a/fs/quota/quota_v2.c b/fs/quota/quota_v2.c
+index ae99e7b88205b2..7978ab671e0c6a 100644
+--- a/fs/quota/quota_v2.c
++++ b/fs/quota/quota_v2.c
+@@ -166,14 +166,17 @@ static int v2_read_file_info(struct super_block *sb, int type)
+ 		    i_size_read(sb_dqopt(sb)->files[type]));
+ 		goto out_free;
+ 	}
+-	if (qinfo->dqi_free_blk >= qinfo->dqi_blocks) {
+-		quota_error(sb, "Free block number too big (%u >= %u).",
+-			    qinfo->dqi_free_blk, qinfo->dqi_blocks);
++	if (qinfo->dqi_free_blk && (qinfo->dqi_free_blk <= QT_TREEOFF ||
++	    qinfo->dqi_free_blk >= qinfo->dqi_blocks)) {
++		quota_error(sb, "Free block number %u out of range (%u, %u).",
++			    qinfo->dqi_free_blk, QT_TREEOFF, qinfo->dqi_blocks);
+ 		goto out_free;
+ 	}
+-	if (qinfo->dqi_free_entry >= qinfo->dqi_blocks) {
+-		quota_error(sb, "Block with free entry too big (%u >= %u).",
+-			    qinfo->dqi_free_entry, qinfo->dqi_blocks);
++	if (qinfo->dqi_free_entry && (qinfo->dqi_free_entry <= QT_TREEOFF ||
++	    qinfo->dqi_free_entry >= qinfo->dqi_blocks)) {
++		quota_error(sb, "Block with free entry %u out of range (%u, %u).",
++			    qinfo->dqi_free_entry, QT_TREEOFF,
++			    qinfo->dqi_blocks);
+ 		goto out_free;
+ 	}
+ 	ret = 0;
+diff --git a/fs/reiserfs/stree.c b/fs/reiserfs/stree.c
+index 3676e02a0232a4..4ab8cab6ea6147 100644
+--- a/fs/reiserfs/stree.c
++++ b/fs/reiserfs/stree.c
+@@ -1407,7 +1407,7 @@ void reiserfs_delete_solid_item(struct reiserfs_transaction_handle *th,
+ 	INITIALIZE_PATH(path);
+ 	int item_len = 0;
+ 	int tb_init = 0;
+-	struct cpu_key cpu_key;
++	struct cpu_key cpu_key = {};
+ 	int retval;
+ 	int quota_cut_bytes = 0;
+ 
+diff --git a/fs/romfs/super.c b/fs/romfs/super.c
+index 5c35f6c760377e..b1bdfbc211c3c0 100644
+--- a/fs/romfs/super.c
++++ b/fs/romfs/super.c
+@@ -593,7 +593,7 @@ static void romfs_kill_sb(struct super_block *sb)
+ #ifdef CONFIG_ROMFS_ON_BLOCK
+ 	if (sb->s_bdev) {
+ 		sync_blockdev(sb->s_bdev);
+-		blkdev_put(sb->s_bdev, sb);
++		bdev_release(sb->s_bdev_handle);
+ 	}
+ #endif
+ }
+diff --git a/fs/squashfs/block.c b/fs/squashfs/block.c
+index 581ce951933901..2dc730800f448d 100644
+--- a/fs/squashfs/block.c
++++ b/fs/squashfs/block.c
+@@ -321,7 +321,7 @@ int squashfs_read_data(struct super_block *sb, u64 index, int length,
+ 		TRACE("Block @ 0x%llx, %scompressed size %d\n", index - 2,
+ 		      compressed ? "" : "un", length);
+ 	}
+-	if (length < 0 || length > output->length ||
++	if (length <= 0 || length > output->length ||
+ 			(index + length) > msblk->bytes_used) {
+ 		res = -EIO;
+ 		goto out;
+diff --git a/fs/squashfs/file.c b/fs/squashfs/file.c
+index 8ba8c4c5077078..e8df6430444b01 100644
+--- a/fs/squashfs/file.c
++++ b/fs/squashfs/file.c
+@@ -544,7 +544,8 @@ static void squashfs_readahead(struct readahead_control *ractl)
+ 	struct squashfs_page_actor *actor;
+ 	unsigned int nr_pages = 0;
+ 	struct page **pages;
+-	int i, file_end = i_size_read(inode) >> msblk->block_log;
++	int i;
++	loff_t file_end = i_size_read(inode) >> msblk->block_log;
+ 	unsigned int max_pages = 1UL << shift;
+ 
+ 	readahead_expand(ractl, start, (len | mask) + 1);
+diff --git a/fs/squashfs/file_direct.c b/fs/squashfs/file_direct.c
+index f1ccad519e28cc..763a3f7a75f6dd 100644
+--- a/fs/squashfs/file_direct.c
++++ b/fs/squashfs/file_direct.c
+@@ -26,10 +26,10 @@ int squashfs_readpage_block(struct page *target_page, u64 block, int bsize,
+ 	struct inode *inode = target_page->mapping->host;
+ 	struct squashfs_sb_info *msblk = inode->i_sb->s_fs_info;
+ 
+-	int file_end = (i_size_read(inode) - 1) >> PAGE_SHIFT;
++	loff_t file_end = (i_size_read(inode) - 1) >> PAGE_SHIFT;
+ 	int mask = (1 << (msblk->block_log - PAGE_SHIFT)) - 1;
+-	int start_index = target_page->index & ~mask;
+-	int end_index = start_index | mask;
++	loff_t start_index = target_page->index & ~mask;
++	loff_t end_index = start_index | mask;
+ 	int i, n, pages, bytes, res = -ENOMEM;
+ 	struct page **page;
+ 	struct squashfs_page_actor *actor;
+diff --git a/fs/super.c b/fs/super.c
+index 576abb1ff0403d..b142e71eb8dfdd 100644
+--- a/fs/super.c
++++ b/fs/super.c
+@@ -1490,14 +1490,16 @@ int setup_bdev_super(struct super_block *sb, int sb_flags,
+ 		struct fs_context *fc)
+ {
+ 	blk_mode_t mode = sb_open_mode(sb_flags);
++	struct bdev_handle *bdev_handle;
+ 	struct block_device *bdev;
+ 
+-	bdev = blkdev_get_by_dev(sb->s_dev, mode, sb, &fs_holder_ops);
+-	if (IS_ERR(bdev)) {
++	bdev_handle = bdev_open_by_dev(sb->s_dev, mode, sb, &fs_holder_ops);
++	if (IS_ERR(bdev_handle)) {
+ 		if (fc)
+ 			errorf(fc, "%s: Can't open blockdev", fc->source);
+-		return PTR_ERR(bdev);
++		return PTR_ERR(bdev_handle);
+ 	}
++	bdev = bdev_handle->bdev;
+ 
+ 	/*
+ 	 * This really should be in blkdev_get_by_dev, but right now can't due
+@@ -1505,7 +1507,7 @@ int setup_bdev_super(struct super_block *sb, int sb_flags,
+ 	 * writable from userspace even for a read-only block device.
+ 	 */
+ 	if ((mode & BLK_OPEN_WRITE) && bdev_read_only(bdev)) {
+-		blkdev_put(bdev, sb);
++		bdev_release(bdev_handle);
+ 		return -EACCES;
+ 	}
+ 
+@@ -1521,10 +1523,11 @@ int setup_bdev_super(struct super_block *sb, int sb_flags,
+ 		mutex_unlock(&bdev->bd_fsfreeze_mutex);
+ 		if (fc)
+ 			warnf(fc, "%pg: Can't mount, blockdev is frozen", bdev);
+-		blkdev_put(bdev, sb);
++		bdev_release(bdev_handle);
+ 		return -EBUSY;
+ 	}
+ 	spin_lock(&sb_lock);
++	sb->s_bdev_handle = bdev_handle;
+ 	sb->s_bdev = bdev;
+ 	sb->s_bdi = bdi_get(bdev->bd_disk->bdi);
+ 	if (bdev_stable_writes(bdev))
+@@ -1657,7 +1660,7 @@ void kill_block_super(struct super_block *sb)
+ 	generic_shutdown_super(sb);
+ 	if (bdev) {
+ 		sync_blockdev(bdev);
+-		blkdev_put(bdev, sb);
++		bdev_release(sb->s_bdev_handle);
+ 	}
+ }
+ 
+diff --git a/include/linux/cgroup-defs.h b/include/linux/cgroup-defs.h
+index 265da00a1a8b1b..6eefe5153a6ff7 100644
+--- a/include/linux/cgroup-defs.h
++++ b/include/linux/cgroup-defs.h
+@@ -543,6 +543,10 @@ struct cgroup_root {
+ 	/* Unique id for this hierarchy. */
+ 	int hierarchy_id;
+ 
++	/* A list running through the active hierarchies */
++	struct list_head root_list;
++	struct rcu_head rcu;	/* Must be near the top */
++
+ 	/*
+ 	 * The root cgroup. The containing cgroup_root will be destroyed on its
+ 	 * release. cgrp->ancestors[0] will be used overflowing into the
+@@ -556,9 +560,6 @@ struct cgroup_root {
+ 	/* Number of cgroups in the hierarchy, used only for /proc/cgroups */
+ 	atomic_t nr_cgrps;
+ 
+-	/* A list running through the active hierarchies */
+-	struct list_head root_list;
+-
+ 	/* Hierarchy-specific flags */
+ 	unsigned int flags;
+ 
+diff --git a/include/linux/fs.h b/include/linux/fs.h
+index 56dce38c478627..43e640fb4a7f77 100644
+--- a/include/linux/fs.h
++++ b/include/linux/fs.h
+@@ -1036,7 +1036,7 @@ struct file_handle {
+ 	__u32 handle_bytes;
+ 	int handle_type;
+ 	/* file identifier */
+-	unsigned char f_handle[];
++	unsigned char f_handle[] __counted_by(handle_bytes);
+ };
+ 
+ static inline struct file *get_file(struct file *f)
+@@ -1223,6 +1223,7 @@ struct super_block {
+ 	struct hlist_bl_head	s_roots;	/* alternate root dentries for NFS */
+ 	struct list_head	s_mounts;	/* list of mounts; _not_ for fs use */
+ 	struct block_device	*s_bdev;
++	struct bdev_handle	*s_bdev_handle;
+ 	struct backing_dev_info *s_bdi;
+ 	struct mtd_info		*s_mtd;
+ 	struct hlist_node	s_instances;
+diff --git a/include/linux/sockptr.h b/include/linux/sockptr.h
+index bae5e2369b4f7a..1c1a5d926b1713 100644
+--- a/include/linux/sockptr.h
++++ b/include/linux/sockptr.h
+@@ -50,11 +50,36 @@ static inline int copy_from_sockptr_offset(void *dst, sockptr_t src,
+ 	return 0;
+ }
+ 
++/* Deprecated.
++ * This is unsafe, unless caller checked user provided optlen.
++ * Prefer copy_safe_from_sockptr() instead.
++ */
+ static inline int copy_from_sockptr(void *dst, sockptr_t src, size_t size)
+ {
+ 	return copy_from_sockptr_offset(dst, src, 0, size);
+ }
+ 
++/**
++ * copy_safe_from_sockptr: copy a struct from sockptr
++ * @dst:   Destination address, in kernel space. This buffer must be @ksize
++ *         bytes long.
++ * @ksize: Size of @dst struct.
++ * @optval: Source address. (in user or kernel space)
++ * @optlen: Size of @optval data.
++ *
++ * Returns:
++ *  * -EINVAL: @optlen < @ksize
++ *  * -EFAULT: access to userspace failed.
++ *  * 0 : @ksize bytes were copied
++ */
++static inline int copy_safe_from_sockptr(void *dst, size_t ksize,
++					 sockptr_t optval, unsigned int optlen)
++{
++	if (optlen < ksize)
++		return -EINVAL;
++	return copy_from_sockptr(dst, optval, ksize);
++}
++
+ static inline int copy_to_sockptr_offset(sockptr_t dst, size_t offset,
+ 		const void *src, size_t size)
+ {
+diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h
+index dbf5b21feafe48..3d8b215f32d5b0 100644
+--- a/include/linux/sunrpc/svc.h
++++ b/include/linux/sunrpc/svc.h
+@@ -336,7 +336,6 @@ struct svc_program {
+ 	const struct svc_version **pg_vers;	/* version array */
+ 	char *			pg_name;	/* service name */
+ 	char *			pg_class;	/* class name: services sharing authentication */
+-	struct svc_stat *	pg_stats;	/* rpc statistics */
+ 	enum svc_auth_status	(*pg_authenticate)(struct svc_rqst *rqstp);
+ 	__be32			(*pg_init_request)(struct svc_rqst *,
+ 						   const struct svc_program *,
+@@ -408,7 +407,9 @@ bool		   svc_rqst_replace_page(struct svc_rqst *rqstp,
+ void		   svc_rqst_release_pages(struct svc_rqst *rqstp);
+ void		   svc_rqst_free(struct svc_rqst *);
+ void		   svc_exit_thread(struct svc_rqst *);
+-struct svc_serv *  svc_create_pooled(struct svc_program *, unsigned int,
++struct svc_serv *  svc_create_pooled(struct svc_program *prog,
++				     struct svc_stat *stats,
++				     unsigned int bufsize,
+ 				     int (*threadfn)(void *data));
+ int		   svc_set_num_threads(struct svc_serv *, struct svc_pool *, int);
+ int		   svc_pool_stats_open(struct svc_serv *serv, struct file *file);
+diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h
+index fb09fd1767f289..ba6e346c8d669a 100644
+--- a/include/uapi/linux/bpf.h
++++ b/include/uapi/linux/bpf.h
+@@ -77,12 +77,29 @@ struct bpf_insn {
+ 	__s32	imm;		/* signed immediate constant */
+ };
+ 
+-/* Key of an a BPF_MAP_TYPE_LPM_TRIE entry */
++/* Deprecated: use struct bpf_lpm_trie_key_u8 (when the "data" member is needed for
++ * byte access) or struct bpf_lpm_trie_key_hdr (when using an alternative type for
++ * the trailing flexible array member) instead.
++ */
+ struct bpf_lpm_trie_key {
+ 	__u32	prefixlen;	/* up to 32 for AF_INET, 128 for AF_INET6 */
+ 	__u8	data[0];	/* Arbitrary size */
+ };
+ 
++/* Header for bpf_lpm_trie_key structs */
++struct bpf_lpm_trie_key_hdr {
++	__u32	prefixlen;
++};
++
++/* Key of an a BPF_MAP_TYPE_LPM_TRIE entry, with trailing byte array. */
++struct bpf_lpm_trie_key_u8 {
++	union {
++		struct bpf_lpm_trie_key_hdr	hdr;
++		__u32				prefixlen;
++	};
++	__u8	data[];		/* Arbitrary size */
++};
++
+ struct bpf_cgroup_storage_key {
+ 	__u64	cgroup_inode_id;	/* cgroup inode id */
+ 	__u32	attach_type;		/* program attach type (enum bpf_attach_type) */
+diff --git a/kernel/bpf/lpm_trie.c b/kernel/bpf/lpm_trie.c
+index b32be680da6cdc..d0febf07051edf 100644
+--- a/kernel/bpf/lpm_trie.c
++++ b/kernel/bpf/lpm_trie.c
+@@ -164,13 +164,13 @@ static inline int extract_bit(const u8 *data, size_t index)
+  */
+ static size_t longest_prefix_match(const struct lpm_trie *trie,
+ 				   const struct lpm_trie_node *node,
+-				   const struct bpf_lpm_trie_key *key)
++				   const struct bpf_lpm_trie_key_u8 *key)
+ {
+ 	u32 limit = min(node->prefixlen, key->prefixlen);
+ 	u32 prefixlen = 0, i = 0;
+ 
+ 	BUILD_BUG_ON(offsetof(struct lpm_trie_node, data) % sizeof(u32));
+-	BUILD_BUG_ON(offsetof(struct bpf_lpm_trie_key, data) % sizeof(u32));
++	BUILD_BUG_ON(offsetof(struct bpf_lpm_trie_key_u8, data) % sizeof(u32));
+ 
+ #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) && defined(CONFIG_64BIT)
+ 
+@@ -229,7 +229,7 @@ static void *trie_lookup_elem(struct bpf_map *map, void *_key)
+ {
+ 	struct lpm_trie *trie = container_of(map, struct lpm_trie, map);
+ 	struct lpm_trie_node *node, *found = NULL;
+-	struct bpf_lpm_trie_key *key = _key;
++	struct bpf_lpm_trie_key_u8 *key = _key;
+ 
+ 	if (key->prefixlen > trie->max_prefixlen)
+ 		return NULL;
+@@ -308,8 +308,9 @@ static long trie_update_elem(struct bpf_map *map,
+ {
+ 	struct lpm_trie *trie = container_of(map, struct lpm_trie, map);
+ 	struct lpm_trie_node *node, *im_node = NULL, *new_node = NULL;
++	struct lpm_trie_node *free_node = NULL;
+ 	struct lpm_trie_node __rcu **slot;
+-	struct bpf_lpm_trie_key *key = _key;
++	struct bpf_lpm_trie_key_u8 *key = _key;
+ 	unsigned long irq_flags;
+ 	unsigned int next_bit;
+ 	size_t matchlen = 0;
+@@ -382,7 +383,7 @@ static long trie_update_elem(struct bpf_map *map,
+ 			trie->n_entries--;
+ 
+ 		rcu_assign_pointer(*slot, new_node);
+-		kfree_rcu(node, rcu);
++		free_node = node;
+ 
+ 		goto out;
+ 	}
+@@ -429,6 +430,7 @@ static long trie_update_elem(struct bpf_map *map,
+ 	}
+ 
+ 	spin_unlock_irqrestore(&trie->lock, irq_flags);
++	kfree_rcu(free_node, rcu);
+ 
+ 	return ret;
+ }
+@@ -437,7 +439,8 @@ static long trie_update_elem(struct bpf_map *map,
+ static long trie_delete_elem(struct bpf_map *map, void *_key)
+ {
+ 	struct lpm_trie *trie = container_of(map, struct lpm_trie, map);
+-	struct bpf_lpm_trie_key *key = _key;
++	struct lpm_trie_node *free_node = NULL, *free_parent = NULL;
++	struct bpf_lpm_trie_key_u8 *key = _key;
+ 	struct lpm_trie_node __rcu **trim, **trim2;
+ 	struct lpm_trie_node *node, *parent;
+ 	unsigned long irq_flags;
+@@ -506,8 +509,8 @@ static long trie_delete_elem(struct bpf_map *map, void *_key)
+ 		else
+ 			rcu_assign_pointer(
+ 				*trim2, rcu_access_pointer(parent->child[0]));
+-		kfree_rcu(parent, rcu);
+-		kfree_rcu(node, rcu);
++		free_parent = parent;
++		free_node = node;
+ 		goto out;
+ 	}
+ 
+@@ -521,10 +524,12 @@ static long trie_delete_elem(struct bpf_map *map, void *_key)
+ 		rcu_assign_pointer(*trim, rcu_access_pointer(node->child[1]));
+ 	else
+ 		RCU_INIT_POINTER(*trim, NULL);
+-	kfree_rcu(node, rcu);
++	free_node = node;
+ 
+ out:
+ 	spin_unlock_irqrestore(&trie->lock, irq_flags);
++	kfree_rcu(free_parent, rcu);
++	kfree_rcu(free_node, rcu);
+ 
+ 	return ret;
+ }
+@@ -536,7 +541,7 @@ static long trie_delete_elem(struct bpf_map *map, void *_key)
+ 				 sizeof(struct lpm_trie_node))
+ #define LPM_VAL_SIZE_MIN	1
+ 
+-#define LPM_KEY_SIZE(X)		(sizeof(struct bpf_lpm_trie_key) + (X))
++#define LPM_KEY_SIZE(X)		(sizeof(struct bpf_lpm_trie_key_u8) + (X))
+ #define LPM_KEY_SIZE_MAX	LPM_KEY_SIZE(LPM_DATA_SIZE_MAX)
+ #define LPM_KEY_SIZE_MIN	LPM_KEY_SIZE(LPM_DATA_SIZE_MIN)
+ 
+@@ -565,7 +570,7 @@ static struct bpf_map *trie_alloc(union bpf_attr *attr)
+ 	/* copy mandatory map attributes */
+ 	bpf_map_init_from_attr(&trie->map, attr);
+ 	trie->data_size = attr->key_size -
+-			  offsetof(struct bpf_lpm_trie_key, data);
++			  offsetof(struct bpf_lpm_trie_key_u8, data);
+ 	trie->max_prefixlen = trie->data_size * 8;
+ 
+ 	spin_lock_init(&trie->lock);
+@@ -616,7 +621,7 @@ static int trie_get_next_key(struct bpf_map *map, void *_key, void *_next_key)
+ {
+ 	struct lpm_trie_node *node, *next_node = NULL, *parent, *search_root;
+ 	struct lpm_trie *trie = container_of(map, struct lpm_trie, map);
+-	struct bpf_lpm_trie_key *key = _key, *next_key = _next_key;
++	struct bpf_lpm_trie_key_u8 *key = _key, *next_key = _next_key;
+ 	struct lpm_trie_node **node_stack = NULL;
+ 	int err = 0, stack_ptr = -1;
+ 	unsigned int next_bit;
+@@ -703,7 +708,7 @@ static int trie_get_next_key(struct bpf_map *map, void *_key, void *_next_key)
+ 	}
+ do_copy:
+ 	next_key->prefixlen = next_node->prefixlen;
+-	memcpy((void *)next_key + offsetof(struct bpf_lpm_trie_key, data),
++	memcpy((void *)next_key + offsetof(struct bpf_lpm_trie_key_u8, data),
+ 	       next_node->data, trie->data_size);
+ free_stack:
+ 	kfree(node_stack);
+@@ -715,7 +720,7 @@ static int trie_check_btf(const struct bpf_map *map,
+ 			  const struct btf_type *key_type,
+ 			  const struct btf_type *value_type)
+ {
+-	/* Keys must have struct bpf_lpm_trie_key embedded. */
++	/* Keys must have struct bpf_lpm_trie_key_u8 embedded. */
+ 	return BTF_INFO_KIND(key_type->info) != BTF_KIND_STRUCT ?
+ 	       -EINVAL : 0;
+ }
+diff --git a/kernel/cgroup/cgroup-internal.h b/kernel/cgroup/cgroup-internal.h
+index c56071f150f2ae..5e17f01ced9fd2 100644
+--- a/kernel/cgroup/cgroup-internal.h
++++ b/kernel/cgroup/cgroup-internal.h
+@@ -170,7 +170,8 @@ extern struct list_head cgroup_roots;
+ 
+ /* iterate across the hierarchies */
+ #define for_each_root(root)						\
+-	list_for_each_entry((root), &cgroup_roots, root_list)
++	list_for_each_entry_rcu((root), &cgroup_roots, root_list,	\
++				lockdep_is_held(&cgroup_mutex))
+ 
+ /**
+  * for_each_subsys - iterate all enabled cgroup subsystems
+diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c
+index 094f513319259d..d872fff901073f 100644
+--- a/kernel/cgroup/cgroup.c
++++ b/kernel/cgroup/cgroup.c
+@@ -1313,7 +1313,7 @@ static void cgroup_exit_root_id(struct cgroup_root *root)
+ 
+ void cgroup_free_root(struct cgroup_root *root)
+ {
+-	kfree(root);
++	kfree_rcu(root, rcu);
+ }
+ 
+ static void cgroup_destroy_root(struct cgroup_root *root)
+@@ -1346,7 +1346,7 @@ static void cgroup_destroy_root(struct cgroup_root *root)
+ 	spin_unlock_irq(&css_set_lock);
+ 
+ 	if (!list_empty(&root->root_list)) {
+-		list_del(&root->root_list);
++		list_del_rcu(&root->root_list);
+ 		cgroup_root_count--;
+ 	}
+ 
+@@ -1386,7 +1386,15 @@ static inline struct cgroup *__cset_cgroup_from_root(struct css_set *cset,
+ 		}
+ 	}
+ 
+-	BUG_ON(!res_cgroup);
++	/*
++	 * If cgroup_mutex is not held, the cgrp_cset_link will be freed
++	 * before we remove the cgroup root from the root_list. Consequently,
++	 * when accessing a cgroup root, the cset_link may have already been
++	 * freed, resulting in a NULL res_cgroup. However, by holding the
++	 * cgroup_mutex, we ensure that res_cgroup can't be NULL.
++	 * If we don't hold cgroup_mutex in the caller, we must do the NULL
++	 * check.
++	 */
+ 	return res_cgroup;
+ }
+ 
+@@ -1445,7 +1453,6 @@ static struct cgroup *current_cgns_cgroup_dfl(void)
+ static struct cgroup *cset_cgroup_from_root(struct css_set *cset,
+ 					    struct cgroup_root *root)
+ {
+-	lockdep_assert_held(&cgroup_mutex);
+ 	lockdep_assert_held(&css_set_lock);
+ 
+ 	return __cset_cgroup_from_root(cset, root);
+@@ -1453,7 +1460,9 @@ static struct cgroup *cset_cgroup_from_root(struct css_set *cset,
+ 
+ /*
+  * Return the cgroup for "task" from the given hierarchy. Must be
+- * called with cgroup_mutex and css_set_lock held.
++ * called with css_set_lock held to prevent task's groups from being modified.
++ * Must be called with either cgroup_mutex or rcu read lock to prevent the
++ * cgroup root from being destroyed.
+  */
+ struct cgroup *task_cgroup_from_root(struct task_struct *task,
+ 				     struct cgroup_root *root)
+@@ -2014,7 +2023,7 @@ void init_cgroup_root(struct cgroup_fs_context *ctx)
+ 	struct cgroup_root *root = ctx->root;
+ 	struct cgroup *cgrp = &root->cgrp;
+ 
+-	INIT_LIST_HEAD(&root->root_list);
++	INIT_LIST_HEAD_RCU(&root->root_list);
+ 	atomic_set(&root->nr_cgrps, 1);
+ 	cgrp->root = root;
+ 	init_cgroup_housekeeping(cgrp);
+@@ -2097,7 +2106,7 @@ int cgroup_setup_root(struct cgroup_root *root, u16 ss_mask)
+ 	 * care of subsystems' refcounts, which are explicitly dropped in
+ 	 * the failure exit path.
+ 	 */
+-	list_add(&root->root_list, &cgroup_roots);
++	list_add_rcu(&root->root_list, &cgroup_roots);
+ 	cgroup_root_count++;
+ 
+ 	/*
+diff --git a/kernel/irq/cpuhotplug.c b/kernel/irq/cpuhotplug.c
+index 5ecd072a34fe72..eb86283901565b 100644
+--- a/kernel/irq/cpuhotplug.c
++++ b/kernel/irq/cpuhotplug.c
+@@ -130,6 +130,22 @@ static bool migrate_one_irq(struct irq_desc *desc)
+ 	 * CPU.
+ 	 */
+ 	err = irq_do_set_affinity(d, affinity, false);
++
++	/*
++	 * If there are online CPUs in the affinity mask, but they have no
++	 * vectors left to make the migration work, try to break the
++	 * affinity by migrating to any online CPU.
++	 */
++	if (err == -ENOSPC && !irqd_affinity_is_managed(d) && affinity != cpu_online_mask) {
++		pr_debug("IRQ%u: set affinity failed for %*pbl, re-try with online CPUs\n",
++			 d->irq, cpumask_pr_args(affinity));
++
++		affinity = cpu_online_mask;
++		brokeaff = true;
++
++		err = irq_do_set_affinity(d, affinity, false);
++	}
++
+ 	if (err) {
+ 		pr_warn_ratelimited("IRQ%u: set affinity failed(%d).\n",
+ 				    d->irq, err);
+@@ -195,10 +211,15 @@ static void irq_restore_affinity_of_irq(struct irq_desc *desc, unsigned int cpu)
+ 	    !irq_data_get_irq_chip(data) || !cpumask_test_cpu(cpu, affinity))
+ 		return;
+ 
+-	if (irqd_is_managed_and_shutdown(data)) {
+-		irq_startup(desc, IRQ_RESEND, IRQ_START_COND);
++	/*
++	 * Don't restore suspended interrupts here when a system comes back
++	 * from S3. They are reenabled via resume_device_irqs().
++	 */
++	if (desc->istate & IRQS_SUSPENDED)
+ 		return;
+-	}
++
++	if (irqd_is_managed_and_shutdown(data))
++		irq_startup(desc, IRQ_RESEND, IRQ_START_COND);
+ 
+ 	/*
+ 	 * If the interrupt can only be directed to a single target
+diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
+index a054cd5ec08bce..8a936c1ffad390 100644
+--- a/kernel/irq/manage.c
++++ b/kernel/irq/manage.c
+@@ -796,10 +796,14 @@ void __enable_irq(struct irq_desc *desc)
+ 		irq_settings_set_noprobe(desc);
+ 		/*
+ 		 * Call irq_startup() not irq_enable() here because the
+-		 * interrupt might be marked NOAUTOEN. So irq_startup()
+-		 * needs to be invoked when it gets enabled the first
+-		 * time. If it was already started up, then irq_startup()
+-		 * will invoke irq_enable() under the hood.
++		 * interrupt might be marked NOAUTOEN so irq_startup()
++		 * needs to be invoked when it gets enabled the first time.
++		 * This is also required when __enable_irq() is invoked for
++		 * a managed and shutdown interrupt from the S3 resume
++		 * path.
++		 *
++		 * If it was already started up, then irq_startup() will
++		 * invoke irq_enable() under the hood.
+ 		 */
+ 		irq_startup(desc, IRQ_RESEND, IRQ_START_FORCE);
+ 		break;
+diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
+index 13f0d11927074a..68af76ca8bc992 100644
+--- a/mm/debug_vm_pgtable.c
++++ b/mm/debug_vm_pgtable.c
+@@ -39,22 +39,7 @@
+  * Please refer Documentation/mm/arch_pgtable_helpers.rst for the semantics
+  * expectations that are being validated here. All future changes in here
+  * or the documentation need to be in sync.
+- *
+- * On s390 platform, the lower 4 bits are used to identify given page table
+- * entry type. But these bits might affect the ability to clear entries with
+- * pxx_clear() because of how dynamic page table folding works on s390. So
+- * while loading up the entries do not change the lower 4 bits. It does not
+- * have affect any other platform. Also avoid the 62nd bit on ppc64 that is
+- * used to mark a pte entry.
+  */
+-#define S390_SKIP_MASK		GENMASK(3, 0)
+-#if __BITS_PER_LONG == 64
+-#define PPC64_SKIP_MASK		GENMASK(62, 62)
+-#else
+-#define PPC64_SKIP_MASK		0x0
+-#endif
+-#define ARCH_SKIP_MASK (S390_SKIP_MASK | PPC64_SKIP_MASK)
+-#define RANDOM_ORVALUE (GENMASK(BITS_PER_LONG - 1, 0) & ~ARCH_SKIP_MASK)
+ #define RANDOM_NZVALUE	GENMASK(7, 0)
+ 
+ struct pgtable_debug_args {
+@@ -510,8 +495,7 @@ static void __init pud_clear_tests(struct pgtable_debug_args *args)
+ 		return;
+ 
+ 	pr_debug("Validating PUD clear\n");
+-	pud = __pud(pud_val(pud) | RANDOM_ORVALUE);
+-	WRITE_ONCE(*args->pudp, pud);
++	WARN_ON(pud_none(pud));
+ 	pud_clear(args->pudp);
+ 	pud = READ_ONCE(*args->pudp);
+ 	WARN_ON(!pud_none(pud));
+@@ -547,8 +531,7 @@ static void __init p4d_clear_tests(struct pgtable_debug_args *args)
+ 		return;
+ 
+ 	pr_debug("Validating P4D clear\n");
+-	p4d = __p4d(p4d_val(p4d) | RANDOM_ORVALUE);
+-	WRITE_ONCE(*args->p4dp, p4d);
++	WARN_ON(p4d_none(p4d));
+ 	p4d_clear(args->p4dp);
+ 	p4d = READ_ONCE(*args->p4dp);
+ 	WARN_ON(!p4d_none(p4d));
+@@ -581,8 +564,7 @@ static void __init pgd_clear_tests(struct pgtable_debug_args *args)
+ 		return;
+ 
+ 	pr_debug("Validating PGD clear\n");
+-	pgd = __pgd(pgd_val(pgd) | RANDOM_ORVALUE);
+-	WRITE_ONCE(*args->pgdp, pgd);
++	WARN_ON(pgd_none(pgd));
+ 	pgd_clear(args->pgdp);
+ 	pgd = READ_ONCE(*args->pgdp);
+ 	WARN_ON(!pgd_none(pgd));
+@@ -633,10 +615,8 @@ static void __init pte_clear_tests(struct pgtable_debug_args *args)
+ 	if (WARN_ON(!args->ptep))
+ 		return;
+ 
+-#ifndef CONFIG_RISCV
+-	pte = __pte(pte_val(pte) | RANDOM_ORVALUE);
+-#endif
+ 	set_pte_at(args->mm, args->vaddr, args->ptep, pte);
++	WARN_ON(pte_none(pte));
+ 	flush_dcache_page(page);
+ 	barrier();
+ 	ptep_clear(args->mm, args->vaddr, args->ptep);
+@@ -649,8 +629,7 @@ static void __init pmd_clear_tests(struct pgtable_debug_args *args)
+ 	pmd_t pmd = READ_ONCE(*args->pmdp);
+ 
+ 	pr_debug("Validating PMD clear\n");
+-	pmd = __pmd(pmd_val(pmd) | RANDOM_ORVALUE);
+-	WRITE_ONCE(*args->pmdp, pmd);
++	WARN_ON(pmd_none(pmd));
+ 	pmd_clear(args->pmdp);
+ 	pmd = READ_ONCE(*args->pmdp);
+ 	WARN_ON(!pmd_none(pmd));
+diff --git a/mm/gup.c b/mm/gup.c
+index f50fe2219a13b6..fdd75384160d8d 100644
+--- a/mm/gup.c
++++ b/mm/gup.c
+@@ -97,95 +97,6 @@ static inline struct folio *try_get_folio(struct page *page, int refs)
+ 	return folio;
+ }
+ 
+-/**
+- * try_grab_folio() - Attempt to get or pin a folio.
+- * @page:  pointer to page to be grabbed
+- * @refs:  the value to (effectively) add to the folio's refcount
+- * @flags: gup flags: these are the FOLL_* flag values.
+- *
+- * "grab" names in this file mean, "look at flags to decide whether to use
+- * FOLL_PIN or FOLL_GET behavior, when incrementing the folio's refcount.
+- *
+- * Either FOLL_PIN or FOLL_GET (or neither) must be set, but not both at the
+- * same time. (That's true throughout the get_user_pages*() and
+- * pin_user_pages*() APIs.) Cases:
+- *
+- *    FOLL_GET: folio's refcount will be incremented by @refs.
+- *
+- *    FOLL_PIN on large folios: folio's refcount will be incremented by
+- *    @refs, and its pincount will be incremented by @refs.
+- *
+- *    FOLL_PIN on single-page folios: folio's refcount will be incremented by
+- *    @refs * GUP_PIN_COUNTING_BIAS.
+- *
+- * Return: The folio containing @page (with refcount appropriately
+- * incremented) for success, or NULL upon failure. If neither FOLL_GET
+- * nor FOLL_PIN was set, that's considered failure, and furthermore,
+- * a likely bug in the caller, so a warning is also emitted.
+- */
+-struct folio *try_grab_folio(struct page *page, int refs, unsigned int flags)
+-{
+-	struct folio *folio;
+-
+-	if (WARN_ON_ONCE((flags & (FOLL_GET | FOLL_PIN)) == 0))
+-		return NULL;
+-
+-	if (unlikely(!(flags & FOLL_PCI_P2PDMA) && is_pci_p2pdma_page(page)))
+-		return NULL;
+-
+-	if (flags & FOLL_GET)
+-		return try_get_folio(page, refs);
+-
+-	/* FOLL_PIN is set */
+-
+-	/*
+-	 * Don't take a pin on the zero page - it's not going anywhere
+-	 * and it is used in a *lot* of places.
+-	 */
+-	if (is_zero_page(page))
+-		return page_folio(page);
+-
+-	folio = try_get_folio(page, refs);
+-	if (!folio)
+-		return NULL;
+-
+-	/*
+-	 * Can't do FOLL_LONGTERM + FOLL_PIN gup fast path if not in a
+-	 * right zone, so fail and let the caller fall back to the slow
+-	 * path.
+-	 */
+-	if (unlikely((flags & FOLL_LONGTERM) &&
+-		     !folio_is_longterm_pinnable(folio))) {
+-		if (!put_devmap_managed_page_refs(&folio->page, refs))
+-			folio_put_refs(folio, refs);
+-		return NULL;
+-	}
+-
+-	/*
+-	 * When pinning a large folio, use an exact count to track it.
+-	 *
+-	 * However, be sure to *also* increment the normal folio
+-	 * refcount field at least once, so that the folio really
+-	 * is pinned.  That's why the refcount from the earlier
+-	 * try_get_folio() is left intact.
+-	 */
+-	if (folio_test_large(folio))
+-		atomic_add(refs, &folio->_pincount);
+-	else
+-		folio_ref_add(folio,
+-				refs * (GUP_PIN_COUNTING_BIAS - 1));
+-	/*
+-	 * Adjust the pincount before re-checking the PTE for changes.
+-	 * This is essentially a smp_mb() and is paired with a memory
+-	 * barrier in page_try_share_anon_rmap().
+-	 */
+-	smp_mb__after_atomic();
+-
+-	node_stat_mod_folio(folio, NR_FOLL_PIN_ACQUIRED, refs);
+-
+-	return folio;
+-}
+-
+ static void gup_put_folio(struct folio *folio, int refs, unsigned int flags)
+ {
+ 	if (flags & FOLL_PIN) {
+@@ -203,58 +114,59 @@ static void gup_put_folio(struct folio *folio, int refs, unsigned int flags)
+ }
+ 
+ /**
+- * try_grab_page() - elevate a page's refcount by a flag-dependent amount
+- * @page:    pointer to page to be grabbed
+- * @flags:   gup flags: these are the FOLL_* flag values.
++ * try_grab_folio() - add a folio's refcount by a flag-dependent amount
++ * @folio:    pointer to folio to be grabbed
++ * @refs:     the value to (effectively) add to the folio's refcount
++ * @flags:    gup flags: these are the FOLL_* flag values
+  *
+  * This might not do anything at all, depending on the flags argument.
+  *
+  * "grab" names in this file mean, "look at flags to decide whether to use
+- * FOLL_PIN or FOLL_GET behavior, when incrementing the page's refcount.
++ * FOLL_PIN or FOLL_GET behavior, when incrementing the folio's refcount.
+  *
+  * Either FOLL_PIN or FOLL_GET (or neither) may be set, but not both at the same
+- * time. Cases: please see the try_grab_folio() documentation, with
+- * "refs=1".
++ * time.
+  *
+  * Return: 0 for success, or if no action was required (if neither FOLL_PIN
+  * nor FOLL_GET was set, nothing is done). A negative error code for failure:
+  *
+- *   -ENOMEM		FOLL_GET or FOLL_PIN was set, but the page could not
++ *   -ENOMEM		FOLL_GET or FOLL_PIN was set, but the folio could not
+  *			be grabbed.
++ *
++ * It is called when we have a stable reference for the folio, typically in
++ * GUP slow path.
+  */
+-int __must_check try_grab_page(struct page *page, unsigned int flags)
++int __must_check try_grab_folio(struct folio *folio, int refs,
++				unsigned int flags)
+ {
+-	struct folio *folio = page_folio(page);
+-
+ 	if (WARN_ON_ONCE(folio_ref_count(folio) <= 0))
+ 		return -ENOMEM;
+ 
+-	if (unlikely(!(flags & FOLL_PCI_P2PDMA) && is_pci_p2pdma_page(page)))
++	if (unlikely(!(flags & FOLL_PCI_P2PDMA) && is_pci_p2pdma_page(&folio->page)))
+ 		return -EREMOTEIO;
+ 
+ 	if (flags & FOLL_GET)
+-		folio_ref_inc(folio);
++		folio_ref_add(folio, refs);
+ 	else if (flags & FOLL_PIN) {
+ 		/*
+ 		 * Don't take a pin on the zero page - it's not going anywhere
+ 		 * and it is used in a *lot* of places.
+ 		 */
+-		if (is_zero_page(page))
++		if (is_zero_folio(folio))
+ 			return 0;
+ 
+ 		/*
+-		 * Similar to try_grab_folio(): be sure to *also*
+-		 * increment the normal page refcount field at least once,
++		 * Increment the normal page refcount field at least once,
+ 		 * so that the page really is pinned.
+ 		 */
+ 		if (folio_test_large(folio)) {
+-			folio_ref_add(folio, 1);
+-			atomic_add(1, &folio->_pincount);
++			folio_ref_add(folio, refs);
++			atomic_add(refs, &folio->_pincount);
+ 		} else {
+-			folio_ref_add(folio, GUP_PIN_COUNTING_BIAS);
++			folio_ref_add(folio, refs * GUP_PIN_COUNTING_BIAS);
+ 		}
+ 
+-		node_stat_mod_folio(folio, NR_FOLL_PIN_ACQUIRED, 1);
++		node_stat_mod_folio(folio, NR_FOLL_PIN_ACQUIRED, refs);
+ 	}
+ 
+ 	return 0;
+@@ -647,8 +559,8 @@ static struct page *follow_page_pte(struct vm_area_struct *vma,
+ 	VM_BUG_ON_PAGE((flags & FOLL_PIN) && PageAnon(page) &&
+ 		       !PageAnonExclusive(page), page);
+ 
+-	/* try_grab_page() does nothing unless FOLL_GET or FOLL_PIN is set. */
+-	ret = try_grab_page(page, flags);
++	/* try_grab_folio() does nothing unless FOLL_GET or FOLL_PIN is set. */
++	ret = try_grab_folio(page_folio(page), 1, flags);
+ 	if (unlikely(ret)) {
+ 		page = ERR_PTR(ret);
+ 		goto out;
+@@ -899,7 +811,7 @@ static int get_gate_page(struct mm_struct *mm, unsigned long address,
+ 			goto unmap;
+ 		*page = pte_page(entry);
+ 	}
+-	ret = try_grab_page(*page, gup_flags);
++	ret = try_grab_folio(page_folio(*page), 1, gup_flags);
+ 	if (unlikely(ret))
+ 		goto unmap;
+ out:
+@@ -1302,20 +1214,19 @@ static long __get_user_pages(struct mm_struct *mm,
+ 			 * pages.
+ 			 */
+ 			if (page_increm > 1) {
+-				struct folio *folio;
++				struct folio *folio = page_folio(page);
+ 
+ 				/*
+ 				 * Since we already hold refcount on the
+ 				 * large folio, this should never fail.
+ 				 */
+-				folio = try_grab_folio(page, page_increm - 1,
+-						       foll_flags);
+-				if (WARN_ON_ONCE(!folio)) {
++				if (try_grab_folio(folio, page_increm - 1,
++						       foll_flags)) {
+ 					/*
+ 					 * Release the 1st page ref if the
+ 					 * folio is problematic, fail hard.
+ 					 */
+-					gup_put_folio(page_folio(page), 1,
++					gup_put_folio(folio, 1,
+ 						      foll_flags);
+ 					ret = -EFAULT;
+ 					goto out;
+@@ -2541,6 +2452,102 @@ static void __maybe_unused undo_dev_pagemap(int *nr, int nr_start,
+ 	}
+ }
+ 
++/**
++ * try_grab_folio_fast() - Attempt to get or pin a folio in fast path.
++ * @page:  pointer to page to be grabbed
++ * @refs:  the value to (effectively) add to the folio's refcount
++ * @flags: gup flags: these are the FOLL_* flag values.
++ *
++ * "grab" names in this file mean, "look at flags to decide whether to use
++ * FOLL_PIN or FOLL_GET behavior, when incrementing the folio's refcount.
++ *
++ * Either FOLL_PIN or FOLL_GET (or neither) must be set, but not both at the
++ * same time. (That's true throughout the get_user_pages*() and
++ * pin_user_pages*() APIs.) Cases:
++ *
++ *    FOLL_GET: folio's refcount will be incremented by @refs.
++ *
++ *    FOLL_PIN on large folios: folio's refcount will be incremented by
++ *    @refs, and its pincount will be incremented by @refs.
++ *
++ *    FOLL_PIN on single-page folios: folio's refcount will be incremented by
++ *    @refs * GUP_PIN_COUNTING_BIAS.
++ *
++ * Return: The folio containing @page (with refcount appropriately
++ * incremented) for success, or NULL upon failure. If neither FOLL_GET
++ * nor FOLL_PIN was set, that's considered failure, and furthermore,
++ * a likely bug in the caller, so a warning is also emitted.
++ *
++ * It uses add ref unless zero to elevate the folio refcount and must be called
++ * in fast path only.
++ */
++static struct folio *try_grab_folio_fast(struct page *page, int refs,
++					 unsigned int flags)
++{
++	struct folio *folio;
++
++	/* Raise warn if it is not called in fast GUP */
++	VM_WARN_ON_ONCE(!irqs_disabled());
++
++	if (WARN_ON_ONCE((flags & (FOLL_GET | FOLL_PIN)) == 0))
++		return NULL;
++
++	if (unlikely(!(flags & FOLL_PCI_P2PDMA) && is_pci_p2pdma_page(page)))
++		return NULL;
++
++	if (flags & FOLL_GET)
++		return try_get_folio(page, refs);
++
++	/* FOLL_PIN is set */
++
++	/*
++	 * Don't take a pin on the zero page - it's not going anywhere
++	 * and it is used in a *lot* of places.
++	 */
++	if (is_zero_page(page))
++		return page_folio(page);
++
++	folio = try_get_folio(page, refs);
++	if (!folio)
++		return NULL;
++
++	/*
++	 * Can't do FOLL_LONGTERM + FOLL_PIN gup fast path if not in a
++	 * right zone, so fail and let the caller fall back to the slow
++	 * path.
++	 */
++	if (unlikely((flags & FOLL_LONGTERM) &&
++		     !folio_is_longterm_pinnable(folio))) {
++		if (!put_devmap_managed_page_refs(&folio->page, refs))
++			folio_put_refs(folio, refs);
++		return NULL;
++	}
++
++	/*
++	 * When pinning a large folio, use an exact count to track it.
++	 *
++	 * However, be sure to *also* increment the normal folio
++	 * refcount field at least once, so that the folio really
++	 * is pinned.  That's why the refcount from the earlier
++	 * try_get_folio() is left intact.
++	 */
++	if (folio_test_large(folio))
++		atomic_add(refs, &folio->_pincount);
++	else
++		folio_ref_add(folio,
++				refs * (GUP_PIN_COUNTING_BIAS - 1));
++	/*
++	 * Adjust the pincount before re-checking the PTE for changes.
++	 * This is essentially a smp_mb() and is paired with a memory
++	 * barrier in folio_try_share_anon_rmap_*().
++	 */
++	smp_mb__after_atomic();
++
++	node_stat_mod_folio(folio, NR_FOLL_PIN_ACQUIRED, refs);
++
++	return folio;
++}
++
+ #ifdef CONFIG_ARCH_HAS_PTE_SPECIAL
+ /*
+  * Fast-gup relies on pte change detection to avoid concurrent pgtable
+@@ -2605,7 +2612,7 @@ static int gup_pte_range(pmd_t pmd, pmd_t *pmdp, unsigned long addr,
+ 		VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
+ 		page = pte_page(pte);
+ 
+-		folio = try_grab_folio(page, 1, flags);
++		folio = try_grab_folio_fast(page, 1, flags);
+ 		if (!folio)
+ 			goto pte_unmap;
+ 
+@@ -2699,7 +2706,7 @@ static int __gup_device_huge(unsigned long pfn, unsigned long addr,
+ 
+ 		SetPageReferenced(page);
+ 		pages[*nr] = page;
+-		if (unlikely(try_grab_page(page, flags))) {
++		if (unlikely(try_grab_folio(page_folio(page), 1, flags))) {
+ 			undo_dev_pagemap(nr, nr_start, flags, pages);
+ 			break;
+ 		}
+@@ -2808,7 +2815,7 @@ static int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
+ 	page = nth_page(pte_page(pte), (addr & (sz - 1)) >> PAGE_SHIFT);
+ 	refs = record_subpages(page, addr, end, pages + *nr);
+ 
+-	folio = try_grab_folio(page, refs, flags);
++	folio = try_grab_folio_fast(page, refs, flags);
+ 	if (!folio)
+ 		return 0;
+ 
+@@ -2879,7 +2886,7 @@ static int gup_huge_pmd(pmd_t orig, pmd_t *pmdp, unsigned long addr,
+ 	page = nth_page(pmd_page(orig), (addr & ~PMD_MASK) >> PAGE_SHIFT);
+ 	refs = record_subpages(page, addr, end, pages + *nr);
+ 
+-	folio = try_grab_folio(page, refs, flags);
++	folio = try_grab_folio_fast(page, refs, flags);
+ 	if (!folio)
+ 		return 0;
+ 
+@@ -2923,7 +2930,7 @@ static int gup_huge_pud(pud_t orig, pud_t *pudp, unsigned long addr,
+ 	page = nth_page(pud_page(orig), (addr & ~PUD_MASK) >> PAGE_SHIFT);
+ 	refs = record_subpages(page, addr, end, pages + *nr);
+ 
+-	folio = try_grab_folio(page, refs, flags);
++	folio = try_grab_folio_fast(page, refs, flags);
+ 	if (!folio)
+ 		return 0;
+ 
+@@ -2963,7 +2970,7 @@ static int gup_huge_pgd(pgd_t orig, pgd_t *pgdp, unsigned long addr,
+ 	page = nth_page(pgd_page(orig), (addr & ~PGDIR_MASK) >> PAGE_SHIFT);
+ 	refs = record_subpages(page, addr, end, pages + *nr);
+ 
+-	folio = try_grab_folio(page, refs, flags);
++	folio = try_grab_folio_fast(page, refs, flags);
+ 	if (!folio)
+ 		return 0;
+ 
+diff --git a/mm/huge_memory.c b/mm/huge_memory.c
+index 7ac2877e76629b..f2816c9a1f3ec8 100644
+--- a/mm/huge_memory.c
++++ b/mm/huge_memory.c
+@@ -1056,7 +1056,7 @@ struct page *follow_devmap_pmd(struct vm_area_struct *vma, unsigned long addr,
+ 	if (!*pgmap)
+ 		return ERR_PTR(-EFAULT);
+ 	page = pfn_to_page(pfn);
+-	ret = try_grab_page(page, flags);
++	ret = try_grab_folio(page_folio(page), 1, flags);
+ 	if (ret)
+ 		page = ERR_PTR(ret);
+ 
+@@ -1214,7 +1214,7 @@ struct page *follow_devmap_pud(struct vm_area_struct *vma, unsigned long addr,
+ 		return ERR_PTR(-EFAULT);
+ 	page = pfn_to_page(pfn);
+ 
+-	ret = try_grab_page(page, flags);
++	ret = try_grab_folio(page_folio(page), 1, flags);
+ 	if (ret)
+ 		page = ERR_PTR(ret);
+ 
+@@ -1475,7 +1475,7 @@ struct page *follow_trans_huge_pmd(struct vm_area_struct *vma,
+ 	VM_BUG_ON_PAGE((flags & FOLL_PIN) && PageAnon(page) &&
+ 			!PageAnonExclusive(page), page);
+ 
+-	ret = try_grab_page(page, flags);
++	ret = try_grab_folio(page_folio(page), 1, flags);
+ 	if (ret)
+ 		return ERR_PTR(ret);
+ 
+diff --git a/mm/hugetlb.c b/mm/hugetlb.c
+index fb7a531fce7174..0acb04c3e95291 100644
+--- a/mm/hugetlb.c
++++ b/mm/hugetlb.c
+@@ -6532,7 +6532,7 @@ struct page *hugetlb_follow_page_mask(struct vm_area_struct *vma,
+ 		 * try_grab_page() should always be able to get the page here,
+ 		 * because we hold the ptl lock and have verified pte_present().
+ 		 */
+-		ret = try_grab_page(page, flags);
++		ret = try_grab_folio(page_folio(page), 1, flags);
+ 
+ 		if (WARN_ON_ONCE(ret)) {
+ 			page = ERR_PTR(ret);
+diff --git a/mm/internal.h b/mm/internal.h
+index abed947f784b7b..ef8d787a510c5c 100644
+--- a/mm/internal.h
++++ b/mm/internal.h
+@@ -938,8 +938,8 @@ int migrate_device_coherent_page(struct page *page);
+ /*
+  * mm/gup.c
+  */
+-struct folio *try_grab_folio(struct page *page, int refs, unsigned int flags);
+-int __must_check try_grab_page(struct page *page, unsigned int flags);
++int __must_check try_grab_folio(struct folio *folio, int refs,
++				unsigned int flags);
+ 
+ /*
+  * mm/huge_memory.c
+diff --git a/mm/page_table_check.c b/mm/page_table_check.c
+index 6363f93a47c691..509c6ef8de400e 100644
+--- a/mm/page_table_check.c
++++ b/mm/page_table_check.c
+@@ -7,6 +7,8 @@
+ #include <linux/kstrtox.h>
+ #include <linux/mm.h>
+ #include <linux/page_table_check.h>
++#include <linux/swap.h>
++#include <linux/swapops.h>
+ 
+ #undef pr_fmt
+ #define pr_fmt(fmt)	"page_table_check: " fmt
+@@ -191,6 +193,22 @@ void __page_table_check_pud_clear(struct mm_struct *mm, pud_t pud)
+ }
+ EXPORT_SYMBOL(__page_table_check_pud_clear);
+ 
++/* Whether the swap entry cached writable information */
++static inline bool swap_cached_writable(swp_entry_t entry)
++{
++	return is_writable_device_exclusive_entry(entry) ||
++	    is_writable_device_private_entry(entry) ||
++	    is_writable_migration_entry(entry);
++}
++
++static inline void page_table_check_pte_flags(pte_t pte)
++{
++	if (pte_present(pte) && pte_uffd_wp(pte))
++		WARN_ON_ONCE(pte_write(pte));
++	else if (is_swap_pte(pte) && pte_swp_uffd_wp(pte))
++		WARN_ON_ONCE(swap_cached_writable(pte_to_swp_entry(pte)));
++}
++
+ void __page_table_check_ptes_set(struct mm_struct *mm, pte_t *ptep, pte_t pte,
+ 		unsigned int nr)
+ {
+@@ -199,6 +217,8 @@ void __page_table_check_ptes_set(struct mm_struct *mm, pte_t *ptep, pte_t pte,
+ 	if (&init_mm == mm)
+ 		return;
+ 
++	page_table_check_pte_flags(pte);
++
+ 	for (i = 0; i < nr; i++)
+ 		__page_table_check_pte_clear(mm, ptep_get(ptep + i));
+ 	if (pte_user_accessible_page(pte))
+@@ -206,11 +226,21 @@ void __page_table_check_ptes_set(struct mm_struct *mm, pte_t *ptep, pte_t pte,
+ }
+ EXPORT_SYMBOL(__page_table_check_ptes_set);
+ 
++static inline void page_table_check_pmd_flags(pmd_t pmd)
++{
++	if (pmd_present(pmd) && pmd_uffd_wp(pmd))
++		WARN_ON_ONCE(pmd_write(pmd));
++	else if (is_swap_pmd(pmd) && pmd_swp_uffd_wp(pmd))
++		WARN_ON_ONCE(swap_cached_writable(pmd_to_swp_entry(pmd)));
++}
++
+ void __page_table_check_pmd_set(struct mm_struct *mm, pmd_t *pmdp, pmd_t pmd)
+ {
+ 	if (&init_mm == mm)
+ 		return;
+ 
++	page_table_check_pmd_flags(pmd);
++
+ 	__page_table_check_pmd_clear(mm, *pmdp);
+ 	if (pmd_user_accessible_page(pmd)) {
+ 		page_table_check_set(pmd_pfn(pmd), PMD_SIZE >> PAGE_SHIFT,
+diff --git a/net/bluetooth/rfcomm/sock.c b/net/bluetooth/rfcomm/sock.c
+index b54e8a530f55a1..29aa07e9db9d71 100644
+--- a/net/bluetooth/rfcomm/sock.c
++++ b/net/bluetooth/rfcomm/sock.c
+@@ -629,7 +629,7 @@ static int rfcomm_sock_setsockopt_old(struct socket *sock, int optname,
+ 
+ 	switch (optname) {
+ 	case RFCOMM_LM:
+-		if (copy_from_sockptr(&opt, optval, sizeof(u32))) {
++		if (bt_copy_from_sockptr(&opt, sizeof(opt), optval, optlen)) {
+ 			err = -EFAULT;
+ 			break;
+ 		}
+@@ -664,7 +664,6 @@ static int rfcomm_sock_setsockopt(struct socket *sock, int level, int optname,
+ 	struct sock *sk = sock->sk;
+ 	struct bt_security sec;
+ 	int err = 0;
+-	size_t len;
+ 	u32 opt;
+ 
+ 	BT_DBG("sk %p", sk);
+@@ -686,11 +685,9 @@ static int rfcomm_sock_setsockopt(struct socket *sock, int level, int optname,
+ 
+ 		sec.level = BT_SECURITY_LOW;
+ 
+-		len = min_t(unsigned int, sizeof(sec), optlen);
+-		if (copy_from_sockptr(&sec, optval, len)) {
+-			err = -EFAULT;
++		err = bt_copy_from_sockptr(&sec, sizeof(sec), optval, optlen);
++		if (err)
+ 			break;
+-		}
+ 
+ 		if (sec.level > BT_SECURITY_HIGH) {
+ 			err = -EINVAL;
+@@ -706,10 +703,9 @@ static int rfcomm_sock_setsockopt(struct socket *sock, int level, int optname,
+ 			break;
+ 		}
+ 
+-		if (copy_from_sockptr(&opt, optval, sizeof(u32))) {
+-			err = -EFAULT;
++		err = bt_copy_from_sockptr(&opt, sizeof(opt), optval, optlen);
++		if (err)
+ 			break;
+-		}
+ 
+ 		if (opt)
+ 			set_bit(BT_SK_DEFER_SETUP, &bt_sk(sk)->flags);
+diff --git a/net/core/filter.c b/net/core/filter.c
+index 8cb44cd29967bb..be313928d272c6 100644
+--- a/net/core/filter.c
++++ b/net/core/filter.c
+@@ -2271,12 +2271,12 @@ static int __bpf_redirect_neigh_v6(struct sk_buff *skb, struct net_device *dev,
+ 
+ 	err = bpf_out_neigh_v6(net, skb, dev, nh);
+ 	if (unlikely(net_xmit_eval(err)))
+-		dev->stats.tx_errors++;
++		DEV_STATS_INC(dev, tx_errors);
+ 	else
+ 		ret = NET_XMIT_SUCCESS;
+ 	goto out_xmit;
+ out_drop:
+-	dev->stats.tx_errors++;
++	DEV_STATS_INC(dev, tx_errors);
+ 	kfree_skb(skb);
+ out_xmit:
+ 	return ret;
+@@ -2378,12 +2378,12 @@ static int __bpf_redirect_neigh_v4(struct sk_buff *skb, struct net_device *dev,
+ 
+ 	err = bpf_out_neigh_v4(net, skb, dev, nh);
+ 	if (unlikely(net_xmit_eval(err)))
+-		dev->stats.tx_errors++;
++		DEV_STATS_INC(dev, tx_errors);
+ 	else
+ 		ret = NET_XMIT_SUCCESS;
+ 	goto out_xmit;
+ out_drop:
+-	dev->stats.tx_errors++;
++	DEV_STATS_INC(dev, tx_errors);
+ 	kfree_skb(skb);
+ out_xmit:
+ 	return ret;
+diff --git a/net/ipv4/fou_core.c b/net/ipv4/fou_core.c
+index 0c41076e31edad..b38b82ae903de0 100644
+--- a/net/ipv4/fou_core.c
++++ b/net/ipv4/fou_core.c
+@@ -433,7 +433,7 @@ static struct sk_buff *gue_gro_receive(struct sock *sk,
+ 
+ 	offloads = NAPI_GRO_CB(skb)->is_ipv6 ? inet6_offloads : inet_offloads;
+ 	ops = rcu_dereference(offloads[proto]);
+-	if (WARN_ON_ONCE(!ops || !ops->callbacks.gro_receive))
++	if (!ops || !ops->callbacks.gro_receive)
+ 		goto out;
+ 
+ 	pp = call_gro_receive(ops->callbacks.gro_receive, head, skb);
+diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c
+index b71f94a5932ac0..e0883ba709b0bf 100644
+--- a/net/ipv4/tcp_metrics.c
++++ b/net/ipv4/tcp_metrics.c
+@@ -899,11 +899,13 @@ static void tcp_metrics_flush_all(struct net *net)
+ 	unsigned int row;
+ 
+ 	for (row = 0; row < max_rows; row++, hb++) {
+-		struct tcp_metrics_block __rcu **pp;
++		struct tcp_metrics_block __rcu **pp = &hb->chain;
+ 		bool match;
+ 
++		if (!rcu_access_pointer(*pp))
++			continue;
++
+ 		spin_lock_bh(&tcp_metrics_lock);
+-		pp = &hb->chain;
+ 		for (tm = deref_locked(*pp); tm; tm = deref_locked(*pp)) {
+ 			match = net ? net_eq(tm_net(tm), net) :
+ 				!refcount_read(&tm_net(tm)->ns.count);
+@@ -915,6 +917,7 @@ static void tcp_metrics_flush_all(struct net *net)
+ 			}
+ 		}
+ 		spin_unlock_bh(&tcp_metrics_lock);
++		cond_resched();
+ 	}
+ }
+ 
+diff --git a/net/mac80211/iface.c b/net/mac80211/iface.c
+index 6e3bfb46af44d3..52b048807feae5 100644
+--- a/net/mac80211/iface.c
++++ b/net/mac80211/iface.c
+@@ -251,9 +251,9 @@ static int ieee80211_can_powered_addr_change(struct ieee80211_sub_if_data *sdata
+ 	return ret;
+ }
+ 
+-static int ieee80211_change_mac(struct net_device *dev, void *addr)
++static int _ieee80211_change_mac(struct ieee80211_sub_if_data *sdata,
++				 void *addr)
+ {
+-	struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev);
+ 	struct ieee80211_local *local = sdata->local;
+ 	struct sockaddr *sa = addr;
+ 	bool check_dup = true;
+@@ -278,7 +278,7 @@ static int ieee80211_change_mac(struct net_device *dev, void *addr)
+ 
+ 	if (live)
+ 		drv_remove_interface(local, sdata);
+-	ret = eth_mac_addr(dev, sa);
++	ret = eth_mac_addr(sdata->dev, sa);
+ 
+ 	if (ret == 0) {
+ 		memcpy(sdata->vif.addr, sa->sa_data, ETH_ALEN);
+@@ -294,6 +294,27 @@ static int ieee80211_change_mac(struct net_device *dev, void *addr)
+ 	return ret;
+ }
+ 
++static int ieee80211_change_mac(struct net_device *dev, void *addr)
++{
++	struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev);
++	struct ieee80211_local *local = sdata->local;
++	int ret;
++
++	/*
++	 * This happens during unregistration if there's a bond device
++	 * active (maybe other cases?) and we must get removed from it.
++	 * But we really don't care anymore if it's not registered now.
++	 */
++	if (!dev->ieee80211_ptr->registered)
++		return 0;
++
++	wiphy_lock(local->hw.wiphy);
++	ret = _ieee80211_change_mac(sdata, addr);
++	wiphy_unlock(local->hw.wiphy);
++
++	return ret;
++}
++
+ static inline int identical_mac_addr_allowed(int type1, int type2)
+ {
+ 	return type1 == NL80211_IFTYPE_MONITOR ||
+diff --git a/net/nfc/llcp_sock.c b/net/nfc/llcp_sock.c
+index 819157bbb5a2c6..d5344563e525c9 100644
+--- a/net/nfc/llcp_sock.c
++++ b/net/nfc/llcp_sock.c
+@@ -252,10 +252,10 @@ static int nfc_llcp_setsockopt(struct socket *sock, int level, int optname,
+ 			break;
+ 		}
+ 
+-		if (copy_from_sockptr(&opt, optval, sizeof(u32))) {
+-			err = -EFAULT;
++		err = copy_safe_from_sockptr(&opt, sizeof(opt),
++					     optval, optlen);
++		if (err)
+ 			break;
+-		}
+ 
+ 		if (opt > LLCP_MAX_RW) {
+ 			err = -EINVAL;
+@@ -274,10 +274,10 @@ static int nfc_llcp_setsockopt(struct socket *sock, int level, int optname,
+ 			break;
+ 		}
+ 
+-		if (copy_from_sockptr(&opt, optval, sizeof(u32))) {
+-			err = -EFAULT;
++		err = copy_safe_from_sockptr(&opt, sizeof(opt),
++					     optval, optlen);
++		if (err)
+ 			break;
+-		}
+ 
+ 		if (opt > LLCP_MAX_MIUX) {
+ 			err = -EINVAL;
+diff --git a/net/rds/recv.c b/net/rds/recv.c
+index c71b923764fd7c..5627f80013f8b1 100644
+--- a/net/rds/recv.c
++++ b/net/rds/recv.c
+@@ -425,6 +425,7 @@ static int rds_still_queued(struct rds_sock *rs, struct rds_incoming *inc,
+ 	struct sock *sk = rds_rs_to_sk(rs);
+ 	int ret = 0;
+ 	unsigned long flags;
++	struct rds_incoming *to_drop = NULL;
+ 
+ 	write_lock_irqsave(&rs->rs_recv_lock, flags);
+ 	if (!list_empty(&inc->i_item)) {
+@@ -435,11 +436,14 @@ static int rds_still_queued(struct rds_sock *rs, struct rds_incoming *inc,
+ 					      -be32_to_cpu(inc->i_hdr.h_len),
+ 					      inc->i_hdr.h_dport);
+ 			list_del_init(&inc->i_item);
+-			rds_inc_put(inc);
++			to_drop = inc;
+ 		}
+ 	}
+ 	write_unlock_irqrestore(&rs->rs_recv_lock, flags);
+ 
++	if (to_drop)
++		rds_inc_put(to_drop);
++
+ 	rdsdebug("inc %p rs %p still %d dropped %d\n", inc, rs, ret, drop);
+ 	return ret;
+ }
+@@ -758,16 +762,21 @@ void rds_clear_recv_queue(struct rds_sock *rs)
+ 	struct sock *sk = rds_rs_to_sk(rs);
+ 	struct rds_incoming *inc, *tmp;
+ 	unsigned long flags;
++	LIST_HEAD(to_drop);
+ 
+ 	write_lock_irqsave(&rs->rs_recv_lock, flags);
+ 	list_for_each_entry_safe(inc, tmp, &rs->rs_recv_queue, i_item) {
+ 		rds_recv_rcvbuf_delta(rs, sk, inc->i_conn->c_lcong,
+ 				      -be32_to_cpu(inc->i_hdr.h_len),
+ 				      inc->i_hdr.h_dport);
++		list_move(&inc->i_item, &to_drop);
++	}
++	write_unlock_irqrestore(&rs->rs_recv_lock, flags);
++
++	list_for_each_entry_safe(inc, tmp, &to_drop, i_item) {
+ 		list_del_init(&inc->i_item);
+ 		rds_inc_put(inc);
+ 	}
+-	write_unlock_irqrestore(&rs->rs_recv_lock, flags);
+ }
+ 
+ /*
+diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
+index 4023c955036b12..6ab9359c1706f1 100644
+--- a/net/sched/sch_generic.c
++++ b/net/sched/sch_generic.c
+@@ -522,8 +522,9 @@ static void dev_watchdog(struct timer_list *t)
+ 
+ 			if (unlikely(timedout_ms)) {
+ 				trace_net_dev_xmit_timeout(dev, i);
+-				WARN_ONCE(1, "NETDEV WATCHDOG: %s (%s): transmit queue %u timed out %u ms\n",
+-					  dev->name, netdev_drivername(dev), i, timedout_ms);
++				netdev_crit(dev, "NETDEV WATCHDOG: CPU: %d: transmit queue %u timed out %u ms\n",
++					    raw_smp_processor_id(),
++					    i, timedout_ms);
+ 				netif_freeze_queues(dev);
+ 				dev->netdev_ops->ndo_tx_timeout(dev, i);
+ 				netif_unfreeze_queues(dev);
+diff --git a/net/sctp/inqueue.c b/net/sctp/inqueue.c
+index 7182c5a450fb5b..5c165218180588 100644
+--- a/net/sctp/inqueue.c
++++ b/net/sctp/inqueue.c
+@@ -38,6 +38,14 @@ void sctp_inq_init(struct sctp_inq *queue)
+ 	INIT_WORK(&queue->immediate, NULL);
+ }
+ 
++/* Properly release the chunk which is being worked on. */
++static inline void sctp_inq_chunk_free(struct sctp_chunk *chunk)
++{
++	if (chunk->head_skb)
++		chunk->skb = chunk->head_skb;
++	sctp_chunk_free(chunk);
++}
++
+ /* Release the memory associated with an SCTP inqueue.  */
+ void sctp_inq_free(struct sctp_inq *queue)
+ {
+@@ -53,7 +61,7 @@ void sctp_inq_free(struct sctp_inq *queue)
+ 	 * free it as well.
+ 	 */
+ 	if (queue->in_progress) {
+-		sctp_chunk_free(queue->in_progress);
++		sctp_inq_chunk_free(queue->in_progress);
+ 		queue->in_progress = NULL;
+ 	}
+ }
+@@ -130,9 +138,7 @@ struct sctp_chunk *sctp_inq_pop(struct sctp_inq *queue)
+ 				goto new_skb;
+ 			}
+ 
+-			if (chunk->head_skb)
+-				chunk->skb = chunk->head_skb;
+-			sctp_chunk_free(chunk);
++			sctp_inq_chunk_free(chunk);
+ 			chunk = queue->in_progress = NULL;
+ 		} else {
+ 			/* Nothing to do. Next chunk in the packet, please. */
+diff --git a/net/sunrpc/stats.c b/net/sunrpc/stats.c
+index 65fc1297c6dfa4..383860cb1d5b0f 100644
+--- a/net/sunrpc/stats.c
++++ b/net/sunrpc/stats.c
+@@ -314,7 +314,7 @@ EXPORT_SYMBOL_GPL(rpc_proc_unregister);
+ struct proc_dir_entry *
+ svc_proc_register(struct net *net, struct svc_stat *statp, const struct proc_ops *proc_ops)
+ {
+-	return do_register(net, statp->program->pg_name, statp, proc_ops);
++	return do_register(net, statp->program->pg_name, net, proc_ops);
+ }
+ EXPORT_SYMBOL_GPL(svc_proc_register);
+ 
+diff --git a/net/sunrpc/svc.c b/net/sunrpc/svc.c
+index 691499d1d2315c..029c49065016ac 100644
+--- a/net/sunrpc/svc.c
++++ b/net/sunrpc/svc.c
+@@ -453,8 +453,8 @@ __svc_init_bc(struct svc_serv *serv)
+  * Create an RPC service
+  */
+ static struct svc_serv *
+-__svc_create(struct svc_program *prog, unsigned int bufsize, int npools,
+-	     int (*threadfn)(void *data))
++__svc_create(struct svc_program *prog, struct svc_stat *stats,
++	     unsigned int bufsize, int npools, int (*threadfn)(void *data))
+ {
+ 	struct svc_serv	*serv;
+ 	unsigned int vers;
+@@ -466,7 +466,7 @@ __svc_create(struct svc_program *prog, unsigned int bufsize, int npools,
+ 	serv->sv_name      = prog->pg_name;
+ 	serv->sv_program   = prog;
+ 	kref_init(&serv->sv_refcnt);
+-	serv->sv_stats     = prog->pg_stats;
++	serv->sv_stats     = stats;
+ 	if (bufsize > RPCSVC_MAXPAYLOAD)
+ 		bufsize = RPCSVC_MAXPAYLOAD;
+ 	serv->sv_max_payload = bufsize? bufsize : 4096;
+@@ -532,26 +532,28 @@ __svc_create(struct svc_program *prog, unsigned int bufsize, int npools,
+ struct svc_serv *svc_create(struct svc_program *prog, unsigned int bufsize,
+ 			    int (*threadfn)(void *data))
+ {
+-	return __svc_create(prog, bufsize, 1, threadfn);
++	return __svc_create(prog, NULL, bufsize, 1, threadfn);
+ }
+ EXPORT_SYMBOL_GPL(svc_create);
+ 
+ /**
+  * svc_create_pooled - Create an RPC service with pooled threads
+  * @prog: the RPC program the new service will handle
++ * @stats: the stats struct if desired
+  * @bufsize: maximum message size for @prog
+  * @threadfn: a function to service RPC requests for @prog
+  *
+  * Returns an instantiated struct svc_serv object or NULL.
+  */
+ struct svc_serv *svc_create_pooled(struct svc_program *prog,
++				   struct svc_stat *stats,
+ 				   unsigned int bufsize,
+ 				   int (*threadfn)(void *data))
+ {
+ 	struct svc_serv *serv;
+ 	unsigned int npools = svc_pool_map_get();
+ 
+-	serv = __svc_create(prog, bufsize, npools, threadfn);
++	serv = __svc_create(prog, stats, bufsize, npools, threadfn);
+ 	if (!serv)
+ 		goto out_err;
+ 	return serv;
+@@ -1377,7 +1379,8 @@ svc_process_common(struct svc_rqst *rqstp)
+ 		goto err_bad_proc;
+ 
+ 	/* Syntactic check complete */
+-	serv->sv_stats->rpccnt++;
++	if (serv->sv_stats)
++		serv->sv_stats->rpccnt++;
+ 	trace_svc_process(rqstp, progp->pg_name);
+ 
+ 	aoffset = xdr_stream_pos(xdr);
+@@ -1429,7 +1432,8 @@ svc_process_common(struct svc_rqst *rqstp)
+ 	goto close_xprt;
+ 
+ err_bad_rpc:
+-	serv->sv_stats->rpcbadfmt++;
++	if (serv->sv_stats)
++		serv->sv_stats->rpcbadfmt++;
+ 	xdr_stream_encode_u32(xdr, RPC_MSG_DENIED);
+ 	xdr_stream_encode_u32(xdr, RPC_MISMATCH);
+ 	/* Only RPCv2 supported */
+@@ -1440,7 +1444,8 @@ svc_process_common(struct svc_rqst *rqstp)
+ err_bad_auth:
+ 	dprintk("svc: authentication failed (%d)\n",
+ 		be32_to_cpu(rqstp->rq_auth_stat));
+-	serv->sv_stats->rpcbadauth++;
++	if (serv->sv_stats)
++		serv->sv_stats->rpcbadauth++;
+ 	/* Restore write pointer to location of reply status: */
+ 	xdr_truncate_encode(xdr, XDR_UNIT * 2);
+ 	xdr_stream_encode_u32(xdr, RPC_MSG_DENIED);
+@@ -1450,7 +1455,8 @@ svc_process_common(struct svc_rqst *rqstp)
+ 
+ err_bad_prog:
+ 	dprintk("svc: unknown program %d\n", rqstp->rq_prog);
+-	serv->sv_stats->rpcbadfmt++;
++	if (serv->sv_stats)
++		serv->sv_stats->rpcbadfmt++;
+ 	*rqstp->rq_accept_statp = rpc_prog_unavail;
+ 	goto sendit;
+ 
+@@ -1458,7 +1464,8 @@ svc_process_common(struct svc_rqst *rqstp)
+ 	svc_printk(rqstp, "unknown version (%d for prog %d, %s)\n",
+ 		       rqstp->rq_vers, rqstp->rq_prog, progp->pg_name);
+ 
+-	serv->sv_stats->rpcbadfmt++;
++	if (serv->sv_stats)
++		serv->sv_stats->rpcbadfmt++;
+ 	*rqstp->rq_accept_statp = rpc_prog_mismatch;
+ 
+ 	/*
+@@ -1472,19 +1479,22 @@ svc_process_common(struct svc_rqst *rqstp)
+ err_bad_proc:
+ 	svc_printk(rqstp, "unknown procedure (%d)\n", rqstp->rq_proc);
+ 
+-	serv->sv_stats->rpcbadfmt++;
++	if (serv->sv_stats)
++		serv->sv_stats->rpcbadfmt++;
+ 	*rqstp->rq_accept_statp = rpc_proc_unavail;
+ 	goto sendit;
+ 
+ err_garbage_args:
+ 	svc_printk(rqstp, "failed to decode RPC header\n");
+ 
+-	serv->sv_stats->rpcbadfmt++;
++	if (serv->sv_stats)
++		serv->sv_stats->rpcbadfmt++;
+ 	*rqstp->rq_accept_statp = rpc_garbage_args;
+ 	goto sendit;
+ 
+ err_system_err:
+-	serv->sv_stats->rpcbadfmt++;
++	if (serv->sv_stats)
++		serv->sv_stats->rpcbadfmt++;
+ 	*rqstp->rq_accept_statp = rpc_system_err;
+ 	goto sendit;
+ }
+@@ -1536,7 +1546,8 @@ void svc_process(struct svc_rqst *rqstp)
+ out_baddir:
+ 	svc_printk(rqstp, "bad direction 0x%08x, dropping request\n",
+ 		   be32_to_cpu(*p));
+-	rqstp->rq_server->sv_stats->rpcbadfmt++;
++	if (rqstp->rq_server->sv_stats)
++		rqstp->rq_server->sv_stats->rpcbadfmt++;
+ out_drop:
+ 	svc_drop(rqstp);
+ }
+diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
+index be5c42d6ffbeab..2b2dc46dc701f9 100644
+--- a/net/wireless/nl80211.c
++++ b/net/wireless/nl80211.c
+@@ -468,6 +468,10 @@ static struct netlink_range_validation nl80211_punct_bitmap_range = {
+ 	.max = 0xffff,
+ };
+ 
++static struct netlink_range_validation q_range = {
++	.max = INT_MAX,
++};
++
+ static const struct nla_policy nl80211_policy[NUM_NL80211_ATTR] = {
+ 	[0] = { .strict_start_type = NL80211_ATTR_HE_OBSS_PD },
+ 	[NL80211_ATTR_WIPHY] = { .type = NLA_U32 },
+@@ -750,7 +754,7 @@ static const struct nla_policy nl80211_policy[NUM_NL80211_ATTR] = {
+ 
+ 	[NL80211_ATTR_TXQ_LIMIT] = { .type = NLA_U32 },
+ 	[NL80211_ATTR_TXQ_MEMORY_LIMIT] = { .type = NLA_U32 },
+-	[NL80211_ATTR_TXQ_QUANTUM] = { .type = NLA_U32 },
++	[NL80211_ATTR_TXQ_QUANTUM] = NLA_POLICY_FULL_RANGE(NLA_U32, &q_range),
+ 	[NL80211_ATTR_HE_CAPABILITY] =
+ 		NLA_POLICY_VALIDATE_FN(NLA_BINARY, validate_he_capa,
+ 				       NL80211_HE_MAX_CAPABILITY_LEN),
+diff --git a/samples/bpf/map_perf_test_user.c b/samples/bpf/map_perf_test_user.c
+index d2fbcf963cdf6d..07ff471ed6aee0 100644
+--- a/samples/bpf/map_perf_test_user.c
++++ b/samples/bpf/map_perf_test_user.c
+@@ -370,7 +370,7 @@ static void run_perf_test(int tasks)
+ 
+ static void fill_lpm_trie(void)
+ {
+-	struct bpf_lpm_trie_key *key;
++	struct bpf_lpm_trie_key_u8 *key;
+ 	unsigned long value = 0;
+ 	unsigned int i;
+ 	int r;
+diff --git a/samples/bpf/xdp_router_ipv4_user.c b/samples/bpf/xdp_router_ipv4_user.c
+index 9d41db09c4800f..266fdd0b025dc6 100644
+--- a/samples/bpf/xdp_router_ipv4_user.c
++++ b/samples/bpf/xdp_router_ipv4_user.c
+@@ -91,7 +91,7 @@ static int recv_msg(struct sockaddr_nl sock_addr, int sock)
+ static void read_route(struct nlmsghdr *nh, int nll)
+ {
+ 	char dsts[24], gws[24], ifs[16], dsts_len[24], metrics[24];
+-	struct bpf_lpm_trie_key *prefix_key;
++	struct bpf_lpm_trie_key_u8 *prefix_key;
+ 	struct rtattr *rt_attr;
+ 	struct rtmsg *rt_msg;
+ 	int rtm_family;
+diff --git a/sound/soc/soc-topology.c b/sound/soc/soc-topology.c
+index 8b58a7864703ee..7e8fca0b066280 100644
+--- a/sound/soc/soc-topology.c
++++ b/sound/soc/soc-topology.c
+@@ -1021,6 +1021,7 @@ static int soc_tplg_dapm_graph_elems_load(struct soc_tplg *tplg,
+ 	struct snd_soc_tplg_hdr *hdr)
+ {
+ 	struct snd_soc_dapm_context *dapm = &tplg->comp->dapm;
++	const size_t maxlen = SNDRV_CTL_ELEM_ID_NAME_MAXLEN;
+ 	struct snd_soc_tplg_dapm_graph_elem *elem;
+ 	struct snd_soc_dapm_route *route;
+ 	int count, i;
+@@ -1044,39 +1045,22 @@ static int soc_tplg_dapm_graph_elems_load(struct soc_tplg *tplg,
+ 		tplg->pos += sizeof(struct snd_soc_tplg_dapm_graph_elem);
+ 
+ 		/* validate routes */
+-		if (strnlen(elem->source, SNDRV_CTL_ELEM_ID_NAME_MAXLEN) ==
+-			    SNDRV_CTL_ELEM_ID_NAME_MAXLEN) {
+-			ret = -EINVAL;
+-			break;
+-		}
+-		if (strnlen(elem->sink, SNDRV_CTL_ELEM_ID_NAME_MAXLEN) ==
+-			    SNDRV_CTL_ELEM_ID_NAME_MAXLEN) {
+-			ret = -EINVAL;
+-			break;
+-		}
+-		if (strnlen(elem->control, SNDRV_CTL_ELEM_ID_NAME_MAXLEN) ==
+-			    SNDRV_CTL_ELEM_ID_NAME_MAXLEN) {
++		if ((strnlen(elem->source, maxlen) == maxlen) ||
++		    (strnlen(elem->sink, maxlen) == maxlen) ||
++		    (strnlen(elem->control, maxlen) == maxlen)) {
+ 			ret = -EINVAL;
+ 			break;
+ 		}
+ 
+-		route->source = devm_kmemdup(tplg->dev, elem->source,
+-					     min(strlen(elem->source),
+-						 SNDRV_CTL_ELEM_ID_NAME_MAXLEN),
+-					     GFP_KERNEL);
+-		route->sink = devm_kmemdup(tplg->dev, elem->sink,
+-					   min(strlen(elem->sink), SNDRV_CTL_ELEM_ID_NAME_MAXLEN),
+-					   GFP_KERNEL);
++		route->source = devm_kstrdup(tplg->dev, elem->source, GFP_KERNEL);
++		route->sink = devm_kstrdup(tplg->dev, elem->sink, GFP_KERNEL);
+ 		if (!route->source || !route->sink) {
+ 			ret = -ENOMEM;
+ 			break;
+ 		}
+ 
+-		if (strnlen(elem->control, SNDRV_CTL_ELEM_ID_NAME_MAXLEN) != 0) {
+-			route->control = devm_kmemdup(tplg->dev, elem->control,
+-						      min(strlen(elem->control),
+-							  SNDRV_CTL_ELEM_ID_NAME_MAXLEN),
+-						      GFP_KERNEL);
++		if (strnlen(elem->control, maxlen) != 0) {
++			route->control = devm_kstrdup(tplg->dev, elem->control, GFP_KERNEL);
+ 			if (!route->control) {
+ 				ret = -ENOMEM;
+ 				break;
+diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c
+index d1bdb0b93bda0c..8cc2d4937f3403 100644
+--- a/sound/usb/mixer.c
++++ b/sound/usb/mixer.c
+@@ -2021,6 +2021,13 @@ static int parse_audio_feature_unit(struct mixer_build *state, int unitid,
+ 		bmaControls = ftr->bmaControls;
+ 	}
+ 
++	if (channels > 32) {
++		usb_audio_info(state->chip,
++			       "usbmixer: too many channels (%d) in unit %d\n",
++			       channels, unitid);
++		return -EINVAL;
++	}
++
+ 	/* parse the source unit */
+ 	err = parse_audio_unit(state, hdr->bSourceID);
+ 	if (err < 0)
+diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h
+index fb09fd1767f289..ba6e346c8d669a 100644
+--- a/tools/include/uapi/linux/bpf.h
++++ b/tools/include/uapi/linux/bpf.h
+@@ -77,12 +77,29 @@ struct bpf_insn {
+ 	__s32	imm;		/* signed immediate constant */
+ };
+ 
+-/* Key of an a BPF_MAP_TYPE_LPM_TRIE entry */
++/* Deprecated: use struct bpf_lpm_trie_key_u8 (when the "data" member is needed for
++ * byte access) or struct bpf_lpm_trie_key_hdr (when using an alternative type for
++ * the trailing flexible array member) instead.
++ */
+ struct bpf_lpm_trie_key {
+ 	__u32	prefixlen;	/* up to 32 for AF_INET, 128 for AF_INET6 */
+ 	__u8	data[0];	/* Arbitrary size */
+ };
+ 
++/* Header for bpf_lpm_trie_key structs */
++struct bpf_lpm_trie_key_hdr {
++	__u32	prefixlen;
++};
++
++/* Key of an a BPF_MAP_TYPE_LPM_TRIE entry, with trailing byte array. */
++struct bpf_lpm_trie_key_u8 {
++	union {
++		struct bpf_lpm_trie_key_hdr	hdr;
++		__u32				prefixlen;
++	};
++	__u8	data[];		/* Arbitrary size */
++};
++
+ struct bpf_cgroup_storage_key {
+ 	__u64	cgroup_inode_id;	/* cgroup inode id */
+ 	__u32	attach_type;		/* program attach type (enum bpf_attach_type) */
+diff --git a/tools/testing/selftests/bpf/progs/map_ptr_kern.c b/tools/testing/selftests/bpf/progs/map_ptr_kern.c
+index 3325da17ec81af..efaf622c28ddec 100644
+--- a/tools/testing/selftests/bpf/progs/map_ptr_kern.c
++++ b/tools/testing/selftests/bpf/progs/map_ptr_kern.c
+@@ -316,7 +316,7 @@ struct lpm_trie {
+ } __attribute__((preserve_access_index));
+ 
+ struct lpm_key {
+-	struct bpf_lpm_trie_key trie_key;
++	struct bpf_lpm_trie_key_hdr trie_key;
+ 	__u32 data;
+ };
+ 
+diff --git a/tools/testing/selftests/bpf/test_lpm_map.c b/tools/testing/selftests/bpf/test_lpm_map.c
+index c028d621c744da..d98c72dc563eaf 100644
+--- a/tools/testing/selftests/bpf/test_lpm_map.c
++++ b/tools/testing/selftests/bpf/test_lpm_map.c
+@@ -211,7 +211,7 @@ static void test_lpm_map(int keysize)
+ 	volatile size_t n_matches, n_matches_after_delete;
+ 	size_t i, j, n_nodes, n_lookups;
+ 	struct tlpm_node *t, *list = NULL;
+-	struct bpf_lpm_trie_key *key;
++	struct bpf_lpm_trie_key_u8 *key;
+ 	uint8_t *data, *value;
+ 	int r, map;
+ 
+@@ -331,8 +331,8 @@ static void test_lpm_map(int keysize)
+ static void test_lpm_ipaddr(void)
+ {
+ 	LIBBPF_OPTS(bpf_map_create_opts, opts, .map_flags = BPF_F_NO_PREALLOC);
+-	struct bpf_lpm_trie_key *key_ipv4;
+-	struct bpf_lpm_trie_key *key_ipv6;
++	struct bpf_lpm_trie_key_u8 *key_ipv4;
++	struct bpf_lpm_trie_key_u8 *key_ipv6;
+ 	size_t key_size_ipv4;
+ 	size_t key_size_ipv6;
+ 	int map_fd_ipv4;
+@@ -423,7 +423,7 @@ static void test_lpm_ipaddr(void)
+ static void test_lpm_delete(void)
+ {
+ 	LIBBPF_OPTS(bpf_map_create_opts, opts, .map_flags = BPF_F_NO_PREALLOC);
+-	struct bpf_lpm_trie_key *key;
++	struct bpf_lpm_trie_key_u8 *key;
+ 	size_t key_size;
+ 	int map_fd;
+ 	__u64 value;
+@@ -532,7 +532,7 @@ static void test_lpm_delete(void)
+ static void test_lpm_get_next_key(void)
+ {
+ 	LIBBPF_OPTS(bpf_map_create_opts, opts, .map_flags = BPF_F_NO_PREALLOC);
+-	struct bpf_lpm_trie_key *key_p, *next_key_p;
++	struct bpf_lpm_trie_key_u8 *key_p, *next_key_p;
+ 	size_t key_size;
+ 	__u32 value = 0;
+ 	int map_fd;
+@@ -693,9 +693,9 @@ static void *lpm_test_command(void *arg)
+ {
+ 	int i, j, ret, iter, key_size;
+ 	struct lpm_mt_test_info *info = arg;
+-	struct bpf_lpm_trie_key *key_p;
++	struct bpf_lpm_trie_key_u8 *key_p;
+ 
+-	key_size = sizeof(struct bpf_lpm_trie_key) + sizeof(__u32);
++	key_size = sizeof(*key_p) + sizeof(__u32);
+ 	key_p = alloca(key_size);
+ 	for (iter = 0; iter < info->iter; iter++)
+ 		for (i = 0; i < MAX_TEST_KEYS; i++) {
+@@ -717,7 +717,7 @@ static void *lpm_test_command(void *arg)
+ 				ret = bpf_map_lookup_elem(info->map_fd, key_p, &value);
+ 				assert(ret == 0 || errno == ENOENT);
+ 			} else {
+-				struct bpf_lpm_trie_key *next_key_p = alloca(key_size);
++				struct bpf_lpm_trie_key_u8 *next_key_p = alloca(key_size);
+ 				ret = bpf_map_get_next_key(info->map_fd, key_p, next_key_p);
+ 				assert(ret == 0 || errno == ENOENT || errno == ENOMEM);
+ 			}
+@@ -752,7 +752,7 @@ static void test_lpm_multi_thread(void)
+ 
+ 	/* create a trie */
+ 	value_size = sizeof(__u32);
+-	key_size = sizeof(struct bpf_lpm_trie_key) + value_size;
++	key_size = sizeof(struct bpf_lpm_trie_key_hdr) + value_size;
+ 	map_fd = bpf_map_create(BPF_MAP_TYPE_LPM_TRIE, NULL, key_size, value_size, 100, &opts);
+ 
+ 	/* create 4 threads to test update, delete, lookup and get_next_key */
+diff --git a/tools/testing/selftests/net/tls.c b/tools/testing/selftests/net/tls.c
+index ad993ab3ac1819..bc36c91c4480f5 100644
+--- a/tools/testing/selftests/net/tls.c
++++ b/tools/testing/selftests/net/tls.c
+@@ -707,6 +707,20 @@ TEST_F(tls, splice_from_pipe)
+ 	EXPECT_EQ(memcmp(mem_send, mem_recv, send_len), 0);
+ }
+ 
++TEST_F(tls, splice_more)
++{
++	unsigned int f = SPLICE_F_NONBLOCK | SPLICE_F_MORE | SPLICE_F_GIFT;
++	int send_len = TLS_PAYLOAD_MAX_LEN;
++	char mem_send[TLS_PAYLOAD_MAX_LEN];
++	int i, send_pipe = 1;
++	int p[2];
++
++	ASSERT_GE(pipe(p), 0);
++	EXPECT_GE(write(p[1], mem_send, send_len), 0);
++	for (i = 0; i < 32; i++)
++		EXPECT_EQ(splice(p[0], NULL, self->fd, NULL, send_pipe, f), 1);
++}
++
+ TEST_F(tls, splice_from_pipe2)
+ {
+ 	int send_len = 16000;
diff --git a/patch/kernel/archive/rockchip-6.10/0000.patching_config.yaml b/patch/kernel/archive/rockchip-6.10/0000.patching_config.yaml
new file mode 100644
index 000000000000..04f7f87716b0
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/0000.patching_config.yaml
@@ -0,0 +1,35 @@
+config:
+  # Just some info stuff; not used by the patching scripts
+  name: rockchip-6.10
+  kind: kernel
+  type: mainline # or: vendor
+  branch: linux-6.10.y
+  last-known-good-tag: v6.10
+  maintainers:
+    - { github: paolo.sabatino, name: Paolo Sabatino, email: paolo.sabatino@gmail.com, armbian-forum: jock }
+
+  # .dts files in these directories will be copied as-is to the build tree; later ones overwrite earlier ones.
+  # This is meant to provide a way to "add a board DTS" without having to null-patch them in.
+  dts-directories:
+    - { source: "dt", target: "arch/arm/boot/dts/rockchip" }
+
+  # every file in these directories will be copied as-is to the build tree; later ones overwrite earlier ones
+  # This is meant as a way to have overlays, bare, in a directory, without having to null-patch them in.
+  # @TODO need a solution to auto-Makefile the overlays as well
+  overlay-directories:
+    - { source: "overlay", target: "arch/arm/boot/dts/rockchip/overlay" }
+
+  # the Makefile in each of these directories will be magically patched to include the dts files copied
+  #  or patched-in; overlay subdir will be included "-y" if it exists.
+  # No more Makefile patching needed, yay!
+  auto-patch-dt-makefile:
+    - { directory: "arch/arm/boot/dts/rockchip", config-var: "CONFIG_ARCH_ROCKCHIP" }
+
+  # configuration for when applying patches to git / auto-rewriting patches (development cycle helpers)
+  patches-to-git:
+    do-not-commit-files:
+      - "MAINTAINERS" # constant churn, drop them. sorry.
+      - "Documentation/devicetree/bindings/arm/rockchip.yaml" # constant churn, conflicts on every bump, drop it. sorry.
+    do-not-commit-regexes: # Python-style regexes
+      - "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9]+)/Makefile$" # ignore DT Makefile patches, we've an auto-patcher now
+
diff --git a/patch/kernel/archive/rockchip-6.10/armbian.series b/patch/kernel/archive/rockchip-6.10/armbian.series
new file mode 100644
index 000000000000..afd8f3b90306
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/armbian.series
@@ -0,0 +1,53 @@
+# Series from patches.armbian/
+	patches.armbian/bt-broadcom-serdev-workaround.patch
+	patches.armbian/clk-rk322x-composite-mmc-clk.patch
+	patches.armbian/clk-rockchip-max-frac-divider.patch
+	patches.armbian/driver-rk322x-audio-codec.patch
+	patches.armbian/driver-rk3288-gpiomem.patch
+	patches.armbian/driver-tinkerboard-alc4040-codec.patch
+	patches.armbian/drm-rk322x-plane-overlay.patch
+	patches.armbian/drm-rk322x-yuv-10bit-modes.patch
+	patches.armbian/drm-rockchip-hardware-cursor.patch
+	patches.armbian/dts-miqi-fan.patch
+	patches.armbian/dts-miqi-hevc-rga.patch
+	patches.armbian/dts-miqi-mali-gpu.patch
+	patches.armbian/dts-miqi-regulator-fix.patch
+	patches.armbian/dts-rk322x-iep-node.patch
+	patches.armbian/dts-rk322x-pinctrl-nand.patch
+	patches.armbian/dts-rk3288-disable-serial-dma.patch
+	patches.armbian/dts-rk3288-fix-mmc-aliases.patch
+	patches.armbian/dts-rk3288-gpu-500mhz-opp.patch
+	patches.armbian/dts-rk3288-pinctrl-spi2.patch
+	patches.armbian/dts-rk3288-thermal-rearrange-zones.patch
+	patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch
+	patches.armbian/dts-tinkerboard-bt-uart-pins.patch
+	patches.armbian/dts-tinkerboard-hevc-rga.patch
+	patches.armbian/dts-tinkerboard-sdio-wifi.patch
+	patches.armbian/dts-tinkerboard-sdmmc-properties.patch
+	patches.armbian/dts-tinkerboard-spi-interface.patch
+	patches.armbian/dts-veyron-flag-cache-flush.patch
+	patches.armbian/general-add-overlay-compilation-support.patch
+	patches.armbian/general-add-overlay-configfs.patch
+	patches.armbian/general-add-restart-handler-for-act8846.patch
+	patches.armbian/general-dwc2-fix-wait-peripheral.patch
+	patches.armbian/general-dwc2-fix-wait-time.patch
+	patches.armbian/general-dwc2-nak-gadget.patch
+	patches.armbian/general-fix-reboot-from-kwiboo.patch
+	patches.armbian/general-linux-export-mm-trace-rss-stats.patch
+	patches.armbian/general-rk322x-gpio-ir-driver.patch
+	patches.armbian/general-rockchip-various-fixes.patch
+	patches.armbian/ir-keymap-rk322x-box.patch
+	patches.armbian/ir-keymap-xt-q8l-v10.patch
+	patches.armbian/misc-tinkerboard-spi-interface.patch
+	patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch
+	patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch
+	patches.armbian/rk322x-dmc-driver-02-sip-constants.patch
+	patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch
+	patches.armbian/rk322x-dmc-driver-04-driver.patch
+	patches.armbian/rk322x-dwc2-no-clock-gating.patch
+	patches.armbian/rk322x-usb-reset-props.patch
+	patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch
+	patches.armbian/wifi-brcmfmac-add-bcm43342.patch
+	patches.armbian/wifi-brcmfmac-ap6330-firmware.patch
+	patches.armbian/wifi-driver-esp8089.patch
+	patches.armbian/wifi-driver-ssv6051.patch
diff --git a/patch/kernel/archive/rockchip-6.10/dt/rk322x-box.dts b/patch/kernel/archive/rockchip-6.10/dt/rk322x-box.dts
new file mode 100644
index 000000000000..ddc25ec77f7f
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/dt/rk322x-box.dts
@@ -0,0 +1,782 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk322x.dtsi"
+
+/ {
+
+	model = "Generic RK322x Tv Box board";
+	compatible = "rockchip,rk3229";
+
+	/*
+	 * No need to reserve memory manually as long as u-boot v2020.10 and
+	 * OPTEE autoconfigure the reserved zones
+	*/
+	/delete-node/ reserved-memory;
+
+	/*
+	 * We rebuild the cpu-opp-table by ourselves
+	 */
+	/delete-node/ opp-table-0;
+
+	/*
+	 * Rebuild the thermal zones and cooling maps ourselved
+	 */
+	/delete-node/ thermal-zones;
+
+	/*
+	 * 	Include the mmc devices into aliases table
+	 */
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdio;
+		mmc2 = &emmc;
+	};
+
+	analog-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "analog";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&codec>;
+		};
+	};
+
+	chosen {
+		bootargs = "earlyprintk=uart8250,mmio32,0x11030000";
+	};
+
+	cpu0_opp_table: opp-table-0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <975000>;
+			clock-latency-ns = <40000>;
+			opp-suspend;
+		};
+
+		opp-816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1000000>;
+		};
+
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1175000>;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1275000>;
+		};
+
+	};
+
+	gpio_leds: gpio-leds {
+
+		compatible = "gpio-leds";
+
+		/*
+		* Working led, available on all boards
+		*/
+		working {
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+			label = "working";
+			default-state = "on";
+			linux,default-trigger = "timer";
+			pinctrl-names = "default";
+			pinctrl-0 = <&gpio_led_working>;
+		};
+
+	};
+
+	gpio_keys: gpio-keys {
+
+		compatible = "gpio-keys";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+	};
+
+	ir_receiver: ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&ir_int>;
+		pinctrl-names = "default";
+		status = "okay";
+		linux,rc-map-name = "rc-rk322x-tvbox";
+	};
+
+	rockchip_ir_receiver: rockchip-ir-receiver {
+		compatible = "rockchip-ir-receiver";
+		reg = <0x110b0030 0x10>;
+		gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
+		clocks = <&cru PCLK_PWM>;
+		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+		linux,rc-map-name = "rc-rk322x-tvbox";
+		pinctrl-names = "default", "suspend";
+		pinctrl-0 = <&ir_int>;
+		pinctrl-1 = <&pwm3_pin>;
+		pwm-id = <3>;
+		shutdown-is-virtual-poweroff;
+		wakeup-source;
+		status = "disabled";
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
+	};
+
+
+	spdif_out: spdif-out {
+		status = "okay";
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	spdif-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	vcc_sys: vcc-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_host: vcc-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc_host";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vccio_1v8: vccio-1v8-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vccio_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vccio_3v3: vccio-3v3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vccio_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_otg: vcc-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&otg_vbus_drv>;
+		regulator-name = "vcc_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-name = "vcc_phy";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vccio_1v8>;
+	};
+
+	vdd_arm: vdd-arm-regulator {
+		compatible = "pwm-regulator";
+		pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_arm";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_log: vdd-log-regulator {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <1000>; /* milliseconds */
+			polling-delay = <5000>; /* milliseconds */
+
+			thermal-sensors = <&tsadc 0>;
+
+			trips {
+				cpu_alert0: cpu_alert0 {
+					temperature = <90000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+				cpu_alert1: cpu_alert1 {
+					temperature = <95000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+				cpu_crit: cpu_crit {
+					temperature = <105000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+
+				cpu_throttle_low: map-cpu-throttle-low {
+					trip = <&cpu_alert0>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT 1>,
+						<&cpu1 THERMAL_NO_LIMIT 1>,
+						<&cpu2 THERMAL_NO_LIMIT 1>,
+						<&cpu3 THERMAL_NO_LIMIT 1>;
+				};
+
+				cpu_throttle_high: map-cpu-throttle-high {
+					trip = <&cpu_alert1>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				gpu_throttle_low: map-gpu-throttle-low {
+					trip = <&cpu_alert0>;
+					cooling-device =
+						<&gpu THERMAL_NO_LIMIT 1>;
+				};
+
+				gpu_throttle_high: map-gpu-throttle-high {
+					trip = <&cpu_alert1>;
+					cooling-device =
+						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				dmc_throttle_low: map-dmc-throttle-low {
+					trip = <&cpu_alert0>;
+					cooling-device = <&dmc THERMAL_NO_LIMIT 1>;
+				};
+
+				dmc_throttle_high: map-dmc-throttle-high {
+					trip = <&cpu_alert1>;
+					cooling-device = <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+			};
+		};
+	};
+
+};
+
+&codec {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cru {
+	assigned-clocks = <&cru PLL_GPLL>, <&cru ARMCLK>,
+			  <&cru PLL_CPLL>, <&cru ACLK_PERI>,
+			  <&cru HCLK_PERI>, <&cru PCLK_PERI>,
+			  <&cru ACLK_CPU>, <&cru HCLK_CPU>,
+			  <&cru PCLK_CPU>, <&cru ACLK_VOP>;
+
+	assigned-clock-rates = <1200000000>, <816000000>,
+				<500000000>, <150000000>,
+				<150000000>, <75000000>,
+				<150000000>, <150000000>,
+				<75000000>, <400000000>;
+};
+
+&dmc {
+	logic-supply = <&vdd_log>;
+};
+
+&emmc {
+	cap-mmc-highspeed;
+	keep-power-in-suspend;
+	non-removable;
+	status = "okay";
+	/delete-property/ mmc-ddr-1_8v;
+	/delete-property/ pinctrl-names;
+	/delete-property/ pinctrl-0;
+	/delete-property/ rockchip,default-sample-phase;
+	rockchip,default-sample-phase = <90>;
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC_SRC>;
+	assigned-clock-rates = <50000000>;
+	clock_in_out = "output";
+	phy-handle = <&phy>;
+	phy-mode = "rmii";
+	phy-supply = <&vcc_phy>;
+	tx_delay = <0x26>;
+	rx_delay = <0x11>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy: phy@0 {
+			compatible = "ethernet-phy-id1234.d400",
+			             "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			clocks = <&cru SCLK_MAC_PHY>;
+			phy-is-integrated;
+			resets = <&cru SRST_MACPHY>;
+		};
+	};
+};
+
+&gpu {
+	assigned-clocks = <&cru ACLK_GPU>;
+	assigned-clock-rates = <300000000>;
+	mali-supply = <&vdd_log>;
+};
+
+&gpu_opp_table {
+	opp-400000000 {
+		opp-hz = /bits/ 64 <400000000>;
+		opp-microvolt = <1100000 1000000 1200000>;
+	};
+};
+
+&io_domains {
+	vccio1-supply = <&vccio_3v3>;
+	vccio2-supply = <&vccio_1v8>;
+	vccio4-supply = <&vccio_3v3>;
+	status = "okay";
+};
+
+&nfc {
+
+	status = "disabled";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/delete-property/ pinctrl-names;
+	/delete-property/ pinctrl-0;
+
+	nand@0 {
+		reg = <0>;
+		label = "rk-nand";
+		nand-bus-width = <8>;
+		nand-ecc-mode = "hw";
+		nand-ecc-step-size = <1024>;
+		nand-ecc-strength = <60>;
+		nand-is-boot-medium;
+		rockchip,boot-blks = <8>;
+		rockchip,boot-ecc-strength = <60>;
+	};
+
+};
+
+&iep {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&hdmi_phy {
+	status = "okay";
+};
+
+&i2s0 {
+	status = "okay";
+};
+
+&i2s1 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+/** Integration to pin controller */
+&pinctrl {
+
+	pcfg_pull_up_12ma: pcfg-pull-up-12ma {
+		drive-strength = <12>;
+		bias-pull-up;
+	};
+
+	pcfg_pull_down_12ma: pcfg-pull-down-12ma {
+		drive-strength = <12>;
+		bias-pull-down;
+	};
+
+	pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+		drive-strength = <12>;
+		bias-disable;
+	};
+
+	pcfg_pull_up_8ma: pcfg-pull-up-8ma {
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	pcfg_pull_down_8ma: pcfg-pull-down-8ma {
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+
+	pcfg_pull_none_8ma: pcfg-pull-none-8ma {
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	pcfg_pull_down_2ma: pcfg-pull-down-2ma {
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	pcfg_pull_none_2ma: pcfg-pull-none-2ma {
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	/*
+	* Some rk322x electrical schemes report this kind of pull-up/down
+	* pin configurations. We set them here, but we don't use it in this
+	* device tree. These instead are useful for overlays, because they seem
+	* to increase stability on at least one board I got here
+	*/
+	sdmmc {
+		sdmmc_clk: sdmmc-clk {
+			rockchip,pins = <1 16 1 &pcfg_pull_down>;
+		};
+
+		sdmmc_cmd: sdmmc-cmd {
+			rockchip,pins = <1 15 1 &pcfg_pull_up>;
+		};
+
+		sdmmc_bus4: sdmmc-bus4 {
+			rockchip,pins = <1 18 1 &pcfg_pull_up>,
+					<1 19 1 &pcfg_pull_up>,
+					<1 20 1 &pcfg_pull_up>,
+					<1 21 1 &pcfg_pull_up>;
+		};
+	};
+
+	/*
+	* Same as above, decreasing strength of SDIO pins seems to be benefical
+	* to stability
+	*/
+	sdio {
+		sdio_clk: sdio-clk {
+			rockchip,pins = <3 0 1 &pcfg_pull_down_2ma>;
+		};
+
+		sdio_cmd: sdio-cmd {
+			rockchip,pins = <3 1 1 &pcfg_pull_up_2ma>;
+		};
+
+		sdio_bus4: sdio-bus4 {
+			rockchip,pins = <3 2 1 &pcfg_pull_up_2ma>,
+					<3 3 1 &pcfg_pull_up_2ma>,
+					<3 4 1 &pcfg_pull_up_2ma>,
+					<3 5 1 &pcfg_pull_up_2ma>;
+		};
+	};
+
+	/*
+	* Same drill as above, electrical schemes also report this pull-up/down
+	* configurations.
+	*/
+	emmc {
+		emmc_clk: emmc-clk {
+			rockchip,pins = <2 7 2 &pcfg_pull_up>;
+		};
+
+		emmc_cmd: emmc-cmd {
+			rockchip,pins = <1 22 2 &pcfg_pull_up>;
+		};
+
+		emmc_bus8: emmc-bus8 {
+			rockchip,pins = <1 24 2 &pcfg_pull_up>,
+					<1 25 2 &pcfg_pull_up>,
+					<1 26 2 &pcfg_pull_up>,
+					<1 27 2 &pcfg_pull_up>,
+					<1 28 2 &pcfg_pull_up>,
+					<1 29 2 &pcfg_pull_up>,
+					<1 30 2 &pcfg_pull_up>,
+					<1 31 2 &pcfg_pull_up>;
+		};
+
+		emmc_pwr: emmc-pwr {
+			rockchip,pins = <2 RK_PA5 2 &pcfg_pull_down>;
+		};
+
+		emmc_rst: emmc-rst {
+			rockchip,pins = <1 RK_PC7 2 &pcfg_pull_up>;
+		};
+
+	};
+
+	gpio-items {
+		gpio_led_working: gpio-led-working {
+			rockchip,pins =  <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pwm1 {
+		pwm1_pin_pull_down: pwm1-pin-pull-down {
+			rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>;
+		};
+	};
+
+	pwm2 {
+		pwm2_pin_pull_up: pwm2-pin-pull-up {
+			rockchip,pins = <1 RK_PB4 2 &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		otg_vbus_drv: otg-vbus-drv {
+			rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart11_xfer &uart11_rts &uart11_cts>;
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+	u2phy0_host: host-port {
+		phy-supply = <&vcc_host>;
+	};
+
+	u2phy0_otg: otg-port {
+		phy-supply = <&vcc_otg>;
+	};
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy0_host {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+	u2phy1_host: host-port {
+		phy-supply = <&vcc_host>;
+	};
+
+	u2phy1_otg: otg-port {
+		phy-supply = <&vcc_otg>;
+	};
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&u2phy1_host {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host2_ehci {
+	status = "okay";
+};
+
+&usb_host2_ohci {
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&sdio {
+	mmc-pwrseq = <&sdio_pwrseq>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	non-removable;
+	no-sd;
+	status = "okay";
+};
+
+&sdmmc {
+	cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
+	cd-debounce-delay-ms = <500>;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	no-sdio;
+	status = "okay";
+};
+
+&spdif {
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,grf = <&grf>;
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <1>;
+	rockchip,hw-tshut-temp = <110000>;
+
+	/* delete the pinctrl-* properties because, on mainline kernel, they (in particular "default")
+	   change the GPIO configuration of the associated PIN. On most boards that pin is not connected
+	   so it does not do anything, but some other boards (X96-Mini) have that pin connected to
+	   a reset pin of the soc or whatever, thus changing the configuration of the pin at boot
+	   causes them to bootloop.
+	   We don't really need these ones though, because since hw-tshut-mode is set to 0, the CRU
+	   unit of the SoC does the reboot*/
+	/delete-property/ pinctrl-names;
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-1;
+	/delete-property/ pinctrl-2;
+
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP>;
+	assigned-clock-parents = <&cru SCLK_HDMI_PHY>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip-6.10/dt/rk3288-xt-q8l-v10.dts b/patch/kernel/archive/rockchip-6.10/dt/rk3288-xt-q8l-v10.dts
new file mode 100644
index 000000000000..b715818fe691
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/dt/rk3288-xt-q8l-v10.dts
@@ -0,0 +1,1128 @@
+/*
+ * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
+ * 					   2018 Paolo Sabatino <paolo.sabatino@gm**l.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3288.dtsi"
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "XT-Q8L-V10-RK3288";
+	compatible = "generic,xt-q8l-v10-rk3288", "rockchip,rk3288";
+
+	memory@0 {
+		reg = <0x0 0x0 0x0 0x80000000>;
+		device_type = "memory";
+	};
+
+	/*
+	 * Peripheral from original q8 device tree, currently no references
+	 * for drivers in linux kernel.
+	rockchip-hsadc@ff080000 {
+		compatible = "rockchip-hsadc";
+		reg = <0xff080000 0x4000>;
+		interrupts = <0x0 0x1f 0x4>;
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x9a>;
+		clocks = <0x79 0x7 0x8 0x39>;
+		clock-names = "hclk_hsadc", "clk_hsadc_out", "clk_hsadc_ext";
+		dmas = <0x9b 0x0>;
+		dma-names = "data";
+		status = "disabled";
+	};
+	*/
+
+	ext_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+	};
+
+	bt_xtal: bluetooth-xtal-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <37400000>;
+		clock-output-names = "txco";
+	};
+
+	/*
+	 * Handle the IR receiver using the gpio-ir-receiver kernel module.
+	 * This works flawlessy, the original xt-q8l-v10 remote uses a NEC
+	 * protocol and the keymap rc-xt-q8l-v10 has to be compiled in the
+	 * kernel for the remote to work as an input device
+	 */
+	ir: ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_int>;
+		linux,rc-map-name = "rc-xt-q8l-v10";
+		wakeup-source;
+	};
+
+	keys: gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwr_key>;
+
+		button@0 {
+			gpio-key,wakeup = <1>;
+			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+			label = "GPIO Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+			debounce-interval = <100>;
+		};
+
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		power {
+			/*
+				Power led is active high, but we set it here active low
+				so while there is mass storage access it turns red and
+				when it is idle is blue
+			*/
+			gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+			label = "power";
+			linux,default-trigger = "mmc0";
+			pinctrl-names = "default";
+			pinctrl-0 = <&power_led>;
+		};
+
+	};
+
+	vcc_sys: vsys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwr>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_flash: flash-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_flash";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		/*gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
+		states = <1800000 0>,
+				 <3300000 1>;
+				 */
+		vin-supply = <&vcc_io>;
+		startup-delay-us = <100000>;
+	};
+
+	vcc_host_5v: usb-host-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc_host_5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		enable-active-high;
+		vin-supply = <&vcc_sys>;
+	};
+
+
+	vcc_otg_5v: usb-otg-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc_otg_5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		enable-active-high;
+		vin-supply = <&vcc_sys>;
+	};
+
+	/*
+	 * Required power sequence to properly enable the wireless/bluetooth
+	 * module connected to sdio0
+	 */
+	sdio0_pwrseq: sdio0_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
+		post-power-on-delay-ms = <100>;
+	};
+
+	/*
+	 * Not really needed, and also break some eMMC configuraions
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		pinctrl-0 = <&emmc_reset>;
+		pinctrl-names = "default";
+		reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
+	};
+	*/
+
+	/*
+	 * Sound taken from tinkerboard device tree, adapted to q8.
+	 */
+	soundcard-hdmi {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "DW-I2S-HDMI";
+		simple-audio-card,mclk-fs = <512>;
+
+		simple-audio-card,codec {
+			sound-dai = <&hdmi>;
+		};
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s>;
+		};
+	};
+
+	soundcard-spdif {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+		simple-audio-card,dai-link@1 {
+
+			cpu {
+				sound-dai = <&spdif>;
+			};
+
+			codec {
+				sound-dai = <&spdif_out>;
+			};
+
+		};
+	};
+
+	spdif_out: spdif-out {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+};
+
+
+&io_domains {
+	status = "okay";
+
+	audio-supply = <&vcca_33>;
+	bb-supply = <&vcc_io>;
+	dvp-supply = <&vcc_18>;
+	flash0-supply = <&vcc_flash>;
+	flash1-supply = <&vcc_lan>;
+	gpio30-supply = <&vcc_io>;
+	gpio1830-supply = <&vcc_io>;
+	lcdc-supply = <&vcc_io>;
+	sdcard-supply = <&vccio_sd>;
+	wifi-supply = <&vcc_18>;
+};
+
+&cpu0 {
+	cpu0-supply = <&vdd_cpu>;
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 1000000>;
+	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	status = "ok";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c5>;
+	status = "ok";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "ok";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "ok";
+
+	vdd_cpu: syr827@40 {
+		compatible = "silergy,syr827";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x40>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-ramp-delay = <8000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x41>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-ramp-delay = <8000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		interrupt-parent = <&gpio0>;
+		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int>;
+	};
+
+	act8846: act8846@5a {
+		compatible = "active-semi,act8846";
+		reg = <0x5a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_vsel>;
+		system-power-controller;
+
+		vp1-supply = <&vcc_sys>;
+		vp2-supply = <&vcc_sys>;
+		vp3-supply = <&vcc_sys>;
+		vp4-supply = <&vcc_sys>;
+		inl1-supply = <&vcc_sys>;
+		inl2-supply = <&vcc_sys>;
+		inl3-supply = <&vcc_20>;
+		wakeup-source;
+
+		regulators {
+
+			/*
+			 * Regulator controlling DDR memory - always on
+			 */
+			vcc_ddr: REG1 {
+				regulator-name = "vcc_ddr";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+				/*
+				 * Broken in kernel 5.4
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+				*/
+			};
+
+			/*
+			 * Regulator controlling various IO functions of the rk3288.
+			 * Always on
+			 */
+			vcc_io: REG2 {
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				/*
+				 * Broken in kernel 5.4
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+				*/
+			};
+
+			/*
+			 * Regulator controlling various board logic.
+			 * Always on.
+			 * rk3288 electrical datasheet says it should have variable
+			 * voltage depending upon dvfs
+			 */
+			vdd_log: REG3 {
+				regulator-name = "vdd_log";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+				/*
+				 * Broken in kernel 5.4
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+				*/
+			};
+
+			/*
+			 * No reference for this on electrical datasheet. Maybe this
+			 * is vcc_18? Maybe this is vcc18_flash on electrical datasheet.
+			 * So far we disable it.
+			 */
+			vcc_20: REG4 {
+				regulator-name = "vcc_20";
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-always-on;
+				/*
+				 * Broken in kernel 5.4
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+				*/
+			};
+
+			/*
+			 * This regulator controls SDIO. Electrical datasheet says
+			 * this regulator can be operated between 1.8 and 3.3 volts
+			 */
+			vccio_sd: REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				/*
+				 * Broken in kernel 5.4
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+				*/
+			};
+
+			/*
+			 * Controlling HDMI and LCD controller on rk3288. 1.0 volts
+			 * by reference
+			 */
+			vdd10_lcd: REG6 {
+				regulator-name = "vdd10_lcd";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				/*
+				 * Broken in kernel 5.4
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+				*/
+			};
+
+			/*
+			 * From the rk3288 electrical datasheet, this regulator powers
+			 * the rk1000 chip, which is absent in our device, but it
+			 * is also supplying bluetooth, so we enable it.
+			 */
+			vcca_18: REG7 {
+				regulator-name = "vcca_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+
+				/*
+					The regulator can be set off in suspend, but kernel 5.4 modifications
+					to enable suspend for ACT8865 device break the ACT8846
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+				*/
+			};
+
+			/*
+			 * This regulator controls, among other things, the SPDIF
+			 * interface, so we enable it
+			 */
+			vcca_33: REG8 {
+				regulator-name = "vcca_33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on; // Turn this on to get SPDIF!
+
+				/*
+					The regulator can be set off in suspend, but kernel 5.4 modifications
+					to enable suspend for ACT8865 device break the ACT8846
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+				*/
+			};
+
+			/*
+			 * LAN regulator
+			 */
+			vcc_lan: REG9 {
+				regulator-name = "vcc_lan";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				/*
+				 * 	Broken in kernel 5.4
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+				*/
+			};
+
+			/*
+			 * Regulator controlling PMU, USB PHY and rk3288 PLLs.
+			 * 1.0 volts by reference
+			 */
+			vdd_10: REG10 {
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+
+				/*
+				 * Broken in kernel 5.4
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+				*/
+			};
+
+			/*
+			 * Regulator controlling Wifi over SDIO, SARADC and USB PHY.
+			 * Better turn this on
+			 */
+			vccio_wl: vcc_18: REG11 {
+				regulator-name = "vcc_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+
+				/*
+				 * Broken in kernel 5.4
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+				*/
+			};
+
+			/*
+			 * Not clear: apparently this controls HDMI and LCD controller
+			 * on rk3368 devices.
+			 * 1.8 volts by reference
+			 */
+			vcc18_lcd: REG12 {
+				regulator-name = "vcc18_lcd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+
+				/*
+					The regulator can be set off in suspend, but kernel 5.4 modifications
+					to enable suspend for ACT8865 device break the ACT8846
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+				*/
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "disabled";
+};
+
+&i2c2 {
+	status = "disabled";
+};
+
+&i2c4 {
+
+	/*
+	 * Here should go the RK1000 audio codec parts, but seems that
+	 * there is no driver in linux kernel at the moment, so we can't
+	 * describe it.
+	 * Also, most important, there is no RK1000 on our board :)
+	 * Datasheet is available here:
+	 * http://dl.radxa.com/rock/docs/hw/ds/RK1000-S%20DATASHEET%20V14.pdf
+	 */
+	status = "disabled";
+
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&pinctrl {
+
+	/*
+		These two lines here, these must be commented out! Otherwise for some reason the kernel
+		does not see the boot device anymore and will stay stuck in initramfs!
+		On the contrary, these are required by u-boot to keep the power holding so the device does not
+		automatically turns off after a small timeout
+	*/
+	/*pinctrl-names = "default";*/
+	/*pinctrl-0 = <&pwr_hold>;*/
+
+	pcfg_output_high: pcfg-output-high {
+		output-high;
+	};
+
+	pcfg_output_low: pcfg-output-low {
+		output-low;
+	};
+
+	pcfg_wl: pcfg-wl {
+		bias-pull-up;
+		drive-strength = <8>;
+	};
+
+	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+		bias-pull-up;
+		drive-strength = <8>;
+	};
+
+	pcfg_pull_none_8ma: pcfg-pull-none-8ma {
+		bias-disable;
+		drive-strength = <8>;
+	};
+
+	pcfg_wl_clk: pcfg-wl-clk {
+		bias-disable;
+		drive-strength = <12>;
+	};
+
+	pcfg_wl_int: pcfg-wl-int {
+		bias-pull-up;
+	};
+
+	act8846 {
+
+		/*
+		 * Original q8 device tree says:
+		 *  - gpio0 11 HIGH -> power hold
+		 *  - gpio7 1 LOW -> possibly pmic-vsel, we don't care
+		 */
+		pmic_vsel: pmic-vsel {
+			rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+
+		pwr_hold: pwr-hold {
+			rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gmac {
+		phy_int: phy-int {
+			rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_pmeb: phy-pmeb {
+			rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rst: phy-rst {
+			rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	hym8563 {
+		rtc_int: rtc-int {
+			rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	keys {
+		pwr_key: pwr-key {
+			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		power_led: power-led {
+			rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdmmc {
+
+		/*
+		 * Copied from firefly board definition to give more drive to
+		 * the sdmmc pins. The Q8 seems to be quite able to drive
+		 * ultra high speed uSD cards, so we give a bit more energy
+		 * to the gpio pins
+		 */
+		sdmmc_bus4: sdmmc-bus4 {
+			rockchip,pins = <6 16 1 &pcfg_pull_up_drv_8ma>,
+					<6 17 1 &pcfg_pull_up_drv_8ma>,
+					<6 18 1 &pcfg_pull_up_drv_8ma>,
+					<6 19 1 &pcfg_pull_up_drv_8ma>;
+		};
+
+		sdmmc_clk: sdmmc-clk {
+			rockchip,pins = <6 20 1 &pcfg_pull_none_8ma>;
+		};
+
+		sdmmc_cmd: sdmmc-cmd {
+			rockchip,pins = <6 21 1 &pcfg_pull_up_drv_8ma>;
+		};
+
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+	usb_host1 {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+	usb_otg {
+		otg_vbus_drv: otg-vbus-drv {
+			rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio0 {
+		wifi_enable_h: wifienable-h {
+			rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+
+	};
+
+
+	bluetooth {
+
+		uart0_rts_gpio: uart0-rts-gpio {
+			rockchip,pins = <4 19 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_reset_l: bt-reset-l {
+			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		bt_wake_h: bt-wake-h {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_h: bt-host-wake-h {
+			rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+	emmc {
+
+		emmc_reset: emmc-reset {
+			rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+};
+
+&saradc {
+	vref-supply = <&vcc_18>;
+	status = "okay";
+};
+
+&emmc {
+
+	/*
+	 * eMMC is a 52Mhz DDR device on q8 devices, so set it here.
+	 * Setting default-sample-rate to 180 degrees is very important,
+	 * otherwise the eMMC is not stable and may not be able to negotiate
+	 * the right clock.
+	 * Despite the code already seems to use 180 degree phase when
+	 * MMC + 8bit bus is set, we need to set default phase here too.
+	 *
+	 * Huge hint came from this patch:
+	 * https://patchwork.kernel.org/patch/11129183/
+	 *
+	 */
+	broken-cd;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+
+	disable-wp;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+
+	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc_flash>;
+
+	mmc-ddr-1_8v;
+	rockchip,default-sample-phase = <180>;
+
+	status = "okay";
+};
+
+&sdmmc {
+	supports-sd;
+
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio6 RK_PC6 GPIO_ACTIVE_LOW>;
+	cd-debounce-delay-ms = <500>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+
+	status = "okay";
+};
+
+&sdio0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	bus-width = <4>;
+	mmc-pwrseq = <&sdio0_pwrseq>;
+
+	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc_18>; // This must be the same as in io_domains,
+		// otherwise the mmc1 device won't be detected properly
+
+	// clock-frequency = <50000000>;
+	// max-frequency = <50000000>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>;
+
+	cap-sdio-irq;
+	no-mmc;
+	no-sd;
+	cap-sd-highspeed; // required, otherwise does not work!
+	supports-sdio;
+	non-removable;
+
+	keep-power-in-suspend;
+	disable-wp;
+
+
+	status = "okay";
+
+	brcmf: bcrmf@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&gpio4>;
+		interrupts = <RK_PD6 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wake";
+		status = "okay";
+	};
+
+	//sd-uhs-sdr104; // required to be disabled, otherwise the device get
+		// detected, but there is no communication
+
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,grf = <&grf>;
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+/*
+ * These dmas described here for uarts are present in original q8 board
+ * dts, so I replicate them here because documentation says that serial
+ * ports can have dmas.
+ * note:
+ *  - uart0 is the serial port connected to the bluetooth module
+ *  - uart2 is the onboard serial port
+ *
+ * As ok kernel 4.19 DMA for serial ports is disabled because it makes
+ * the ports unusable
+ *
+ */
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer>, <&uart0_rts>, <&uart0_cts>;
+
+// 	dmas = <&dmac_peri 1 &dmac_peri 2>;
+// 	dma-names = "tx", "rx";
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4330-bt";
+		max-speed = <4000000>;
+
+		shutdown-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+		//interrupt-parent = <&gpio4>;
+		//interrupt-names = "host-wakeup";
+		//interrupts = <RK_PD7 IRQ_TYPE_EDGE_FALLING>;
+		clock-names = "lpo", "txco";
+		clocks = <&hym8563>, <&bt_xtal>;
+ 		vddio-supply = <&vcca_18>;
+ 		vbat-supply = <&vcca_18>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_enable_h>, <&bt_wake_h>, <&bt_host_wake_h>, <&bt_reset_l>;
+		brcm,bt-pcm-int-params = [01 02 00 01 01];
+		status = "okay";
+	};
+
+};
+
+&uart1 {
+	//dmas = <&dmac_peri 3 &dmac_peri 4>;
+	//dma-names = "tx", "rx";
+	status = "okay";
+};
+
+&uart2 {
+	//dmas = <&dmac_bus_s 4 &dmac_bus_s 5>;
+	//dma-names = "tx", "rx";
+	status = "okay";
+};
+
+&uart3 {
+	//dmas = <&dmac_peri 7 &dmac_peri 8>;
+	//dma-names = "tx", "rx";
+	status = "okay";
+};
+
+&uart4 {
+	//dmas = <&dmac_peri 9 &dmac_peri 10>;
+	//dma-names = "tx", "rx";
+	status = "disabled";
+};
+
+/*
+ * Here usbphy* should have their proper reset lines described in rk3288.dtsi
+ * Describing resets for usb phy is important because otherwise the USB
+ * port gets stuck in case it goes into autosuspend: plugging any device
+ * when the port is autosuspended will actually kill the port itself and
+ * require a power cycle.
+ * This is required for the usbphy1 phy, nonetheless it is a good idea to
+ * specify the proper resources for all the phys though.
+ * The reference patch which works in conjuction with the reset lines:
+ * https://patchwork.kernel.org/patch/9469811/
+ *
+ */
+&usbphy {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	reg = <0x0 0xff500000 0x0 0x20000>;
+	status = "disable";
+};
+
+&usb_host1 {
+	vbus-supply = <&vcc_host_5v>;
+	status = "okay";
+};
+
+&usb_otg {
+	vbus-supply = <&vcc_otg_5v>;
+	status = "okay";
+};
+
+/*
+ * Enable VPU services and complete the relative IOMMU configurations
+ */
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&vpu_mmu {
+	status = "okay";
+};
+
+&hevc {
+	status = "okay";
+};
+
+&hevc_mmu {
+	status = "okay";
+};
+
+&rga {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
+
+// i2s bus is present on q8 device, enable it
+&i2s {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+// spdif is present on q8 device, enable it
+&spdif {
+	status = "okay";
+};
+
+/*
+ * Redefine some thermals to give a bit more headroom (+5°C)
+ */
+&cpu_alert0 {
+	temperature = <75000>;
+};
+
+&cpu_alert1 {
+	temperature = <80000>;
+};
+
+&gpu_alert0 {
+	temperature = <75000>;
+};
+
+/*
+ * Retouch the operating points for higher frequencies to reduce
+ * the voltage required
+ */
+&cpu_opp_table {
+	opp-1512000000 {
+		opp-microvolt = <1250000>;
+	};
+
+	opp-1608000000 {
+		opp-microvolt = <1300000>;
+	};
+
+	/*
+		Remove the overclocking/turbo frequencies
+	*/
+	/delete-node/ opp@1704000000;
+	/delete-node/ opp@1800000000;
+	/delete-node/ opp@1896000000;
+	/delete-node/ opp@1920000000;
+	/delete-node/ opp@1992000000;
+	/delete-node/ opp@2016000000;
+	/delete-node/ opp@2040000000;
+	/delete-node/ opp@2064000000;
+	/delete-node/ opp@2088000000;
+	/delete-node/ opp@2112000000;
+	/delete-node/ opp@2136000000;
+	/delete-node/ opp@2160000000;
+	/delete-node/ opp@2184000000;
+	/delete-node/ opp@2208000000;
+
+
+};
+
+&gpu_opp_table {
+
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <1150000>;
+	};
+
+	opp-600000000 {
+		status = "disabled";
+	};
+
+};
+
+
+&gpiomem {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip-6.10/kernel-6.8-tools-cgroup-makefile.patch b/patch/kernel/archive/rockchip-6.10/kernel-6.8-tools-cgroup-makefile.patch
new file mode 100644
index 000000000000..068fe83689d6
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/kernel-6.8-tools-cgroup-makefile.patch
@@ -0,0 +1,17 @@
+diff --git a/tools/cgroup/Makefile b/tools/cgroup/Makefile
+new file mode 100644
+index 000000000000..ffca068e4a76
+--- /dev/null
++++ b/tools/cgroup/Makefile
+@@ -0,0 +1,11 @@
++# SPDX-License-Identifier: GPL-2.0
++# Makefile for cgroup tools
++
++CFLAGS = -Wall -Wextra
++
++all: cgroup_event_listener
++%: %.c
++	$(CC) $(CFLAGS) -o $@ $^
++
++clean:
++	$(RM) cgroup_event_listener
diff --git a/patch/kernel/archive/rockchip-6.10/libreelec.series b/patch/kernel/archive/rockchip-6.10/libreelec.series
new file mode 100644
index 000000000000..6d4878166c87
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/libreelec.series
@@ -0,0 +1,9 @@
+# Series from patches.libreelec/
+	patches.libreelec/linux-0002-rockchip-from-list.patch
+	patches.libreelec/linux-0011-v4l2-from-list.patch
+	patches.libreelec/linux-1000-drm-rockchip.patch
+	patches.libreelec/linux-1001-v4l2-rockchip.patch
+	patches.libreelec/linux-1002-for-libreelec.patch
+	patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch
+	patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch
+	patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/Makefile b/patch/kernel/archive/rockchip-6.10/overlay/Makefile
new file mode 100644
index 000000000000..9aa0bda64de5
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/Makefile
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0
+dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
+	rockchip-ds1307.dtbo    \
+	rockchip-i2c1.dtbo      \
+	rockchip-i2c4.dtbo      \
+	rockchip-spi0.dtbo      \
+	rockchip-spi2.dtbo      \
+	rockchip-spidev0.dtbo   \
+	rockchip-spidev2.dtbo   \
+	rockchip-uart1.dtbo     \
+	rockchip-uart2.dtbo     \
+	rockchip-uart3.dtbo     \
+	rockchip-uart4.dtbo     \
+	rockchip-w1-gpio.dtbo   \
+	rk322x-emmc.dtbo	\
+	rk322x-emmc-pins.dtbo	\
+	rk322x-emmc-ddr-ph45.dtbo \
+	rk322x-emmc-ddr-ph180.dtbo \
+	rk322x-emmc-hs200.dtbo	\
+	rk322x-nand.dtbo	\
+	rk322x-led-conf-default.dtbo \
+	rk322x-led-conf1.dtbo	\
+	rk322x-led-conf2.dtbo	\
+	rk322x-led-conf3.dtbo   \
+	rk322x-led-conf4.dtbo   \
+	rk322x-led-conf5.dtbo   \
+	rk322x-led-conf6.dtbo	\
+	rk322x-led-conf7.dtbo	\
+	rk322x-led-conf8.dtbo   \
+	rk322x-cpu-hs.dtbo	\
+	rk322x-cpu-hs-lv.dtbo	\
+	rk322x-wlan-alt-wiring.dtbo \
+	rk322x-cpu-stability.dtbo \
+	rk322x-ir-wakeup.dtbo \
+	rk322x-ddr3-330.dtbo \
+	rk322x-ddr3-528.dtbo \
+	rk322x-ddr3-660.dtbo \
+	rk322x-ddr3-800.dtbo \
+	rk322x-bt-8723cs.dtbo \
+	rk322x-usb-otg-peripheral.dtbo
+
+
+scr-$(CONFIG_ARCH_ROCKCHIP) += \
+       rk322x-fixup.scr \
+       rockchip-fixup.scr
+
+dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \
+       README.rk322x-overlays \
+       README.rockchip-overlays
+
+dtb-y += $(dtbo-y) $(scr-y) $(dtbotxt-y)
+
+clean-files    := *.dtbo *.scr
+
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/README.rk322x-overlays b/patch/kernel/archive/rockchip-6.10/overlay/README.rk322x-overlays
new file mode 100644
index 000000000000..1d36d171746f
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/README.rk322x-overlays
@@ -0,0 +1,98 @@
+This document describes overlays provided in the kernel packages
+For generic Armbian overlays documentation please see
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
+
+### Platform:
+
+rk322x (Rockchip)
+
+### Provided overlays:
+
+- rk322x-cpu-hs
+- rk322x-cpu-stability
+- rk322x-emmc*
+- rk322x-nand
+- rk322x-emmc-nand
+- rk322x-led-conf*
+- rk322x-wlan-alt-wiring
+- rk322x-ddr3-*
+- rk322x-bt-*
+- rk322x-usb-otg-peripheral
+- rk322x-ir-wakeup
+
+### Overlay details:
+
+### rk322x-cpu-hs
+
+Activates higher CPU speed (up to 1.4ghz) for rk3228b/rk3229 boxes
+
+### rk322x-cpu-stability
+
+Increases the voltage of the lowest operating point to increase stability
+on some boards which have power regulation issues. Also adds a settling
+time to allow power regulator stabilize voltage.
+
+### emmc*
+
+rk322x-emmc activates onboard emmc device node and deactivates the
+nand controller.
+rk322x-emmc-pins sets the pin controller default pull up/down
+configuration, not all boards are happy with this overlay, so your
+mileage may vary and may want to not use it.
+rk322x-emmc-ddr-ph45/ph180 sets the emmc ddr mode. First overlay
+sets the default phase clock shifting to 45 degrees, the second
+overlay to 180 degrees. They are alternative, choose the one that
+makes your emmc perform better.
+rk322x-emmc-hs200 enables the hs200 mode. It is preferable to
+ddr mode because it is more stable, but old emmc parts don't
+support it.
+
+### nand
+
+Activates onboard nand device node and deactivates the emmc controller.
+Also sets up the pin controller default pull up/down configuration
+
+### rk322x-led-conf*
+
+Each device tree of this kind provides a different known wiring configuration
+(ie: gpio and active low/high) of the onboard leds. Each board manufacturer
+usually choose a different GPIO for the auxiliary led, but the main "working"
+led is always wired to the same gpio (although it may be active high or low)
+led-conf1 is commonly found in boards made by Chiptrip manufacturer
+led-conf2 is found in other boards with R329Q and MXQ_RK3229 marking
+led-conf3 is found in boards with R28-MXQ marking
+led-conf4 is found on boards with T066 marking
+led-conf5 is found on boards with IPB900 marking from AEMS PVT
+led-conf6 is found on boards with MXQ_PRO_V72 and similar markings, possibly
+with eMCP module.
+led-conf7 is found on boards with R29_MXQ, R2B_MXQ and H20 markings
+led-conf8 is specific for H20_221_V1.71 boards, but may work on other variants
+
+### rk322x-alt-wiring
+
+Some boards have different SDIO wiring setup for wifi chips. This overlay
+enables the different pin controller wiring and power enable
+
+### rk322x-ddr3-*
+
+Enable DRAM memory controller and sets the speed to the given speed bin.
+The DRAM memory controller reclocking only works with DDR3/LPDDR3, if
+you enable one of these overlays on boards with DDR2 memory the system
+will not boot anymore
+
+### rk322x-bt-*
+
+Overlays that enable bluetooth devices. Most common bluetooth chips are
+realtek ones.
+rk322x-bt-8723cs: enable this overlay for 8723cs and 8703bs wifi/bluetooth
+
+### rk322x-usb-otg-peripheral
+
+Set the OTG USB port to peripheral mode to be used as USB slave instead
+of USB host
+
+### rk322x-ir-wakeup
+
+Enable the rockchip-ir-driver in place of the standard gpio-ir-receiver.
+The rockchip-specific driver exploits the Trust OS and Virtual Poweroff mode
+to allow power up via remote controller power button.
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/README.rockchip-overlays b/patch/kernel/archive/rockchip-6.10/overlay/README.rockchip-overlays
new file mode 100644
index 000000000000..df4559ca2623
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/README.rockchip-overlays
@@ -0,0 +1,78 @@
+This document describes overlays provided in the kernel packages
+For generic Armbian overlays documentation please see
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
+
+### Platform:
+
+rockchip (Rockchip)
+
+### Provided overlays:
+
+- ds1307
+- i2c1
+- i2c4
+- spi0
+- spi2
+- spidev0
+- spidev2
+- uart1
+- uart2
+- uart3
+- uart4
+- w1-gpio
+
+### Overlay details:
+
+### ds1307
+
+Activates ds1307 rtc on i2c1
+
+### i2c1
+
+Activate i2c1
+
+### i2c4
+
+Activate i2c4
+
+### spi0
+
+Activate spi0
+conflicts with uart4
+
+### spi2
+
+Activate spi2
+
+### spidev0
+
+Activate spidev on spi0
+Depends on spi0
+
+### spidev2
+
+Activate spidev on spi2
+depends on spi2
+
+### uart1
+
+Activate uart1
+
+### uart2
+
+Activate uart2
+
+### uart3
+
+Activate uart3
+
+### uart4
+
+Activate uart4
+Conflicts with spi0
+
+### w1-gpio
+
+Activates 1-wire gpio master on GPIO0 17
+
+
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-bt-8723cs.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-bt-8723cs.dtso
new file mode 100644
index 000000000000..48bb04f779fa
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-bt-8723cs.dtso
@@ -0,0 +1,19 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&uart1 {
+    pinctrl-0 = <&uart11_xfer>, <&uart11_rts>, <&uart11_cts>;
+    pinctrl-names = "default";
+    uart-has-rtscts;
+    status = "okay";
+    bluetooth {
+        compatible = "realtek,rtl8723cs-bt";
+        enable-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
+        device-wake-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>;
+        host-wake-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
+    };
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-cpu-hs-lv.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-cpu-hs-lv.dtso
new file mode 100644
index 000000000000..5f7d2dcf42d0
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-cpu-hs-lv.dtso
@@ -0,0 +1,68 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&cpu0_opp_table>;
+		__overlay__ {
+			opp-600000000 {
+				opp-microvolt = <950000 950000 1275000>;
+			};
+			opp-816000000 {
+				opp-microvolt = <950000 950000 1275000>;
+			};
+			opp-1008000000 {
+				opp-microvolt = <1000000 1000000 1275000>;
+			};
+			opp-1200000000 {
+				opp-microvolt = <1100000 1100000 1275000>;
+			};
+			opp-1296000000 {
+				opp-hz = /bits/ 64 <1296000000>;
+				opp-microvolt = <1150000 1150000 1275000>;
+			};
+			opp-1392000000 {
+				opp-hz = /bits/ 64 <1392000000>;
+				opp-microvolt = <1225000 1225000 1275000>;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&gpu_opp_table>;
+		__overlay__ {
+			opp-200000000 {
+				opp-microvolt = <1050000 1050000 1200000>;
+			};
+			opp-300000000 {
+				opp-microvolt = <1050000 1050000 1200000>;
+			};
+			opp-400000000 {
+				opp-microvolt = <1050000 1050000 1200000>;
+			};
+			opp-500000000 {
+				opp-microvolt = <1050000 1050000 1200000>;
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&dmc_opp_table>;
+		__overlay__ {
+			opp-330000000 {
+				opp-microvolt = <1050000 1050000 1200000>;
+			};
+			opp-534000000 {
+				opp-microvolt = <1050000 1050000 1200000>;
+			};
+			opp-660000000 {
+				opp-microvolt = <1050000 1050000 1200000>;
+			};
+			opp-786000000 {
+				opp-microvolt = <1100000 1050000 1200000>;
+			};
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-cpu-hs.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-cpu-hs.dtso
new file mode 100644
index 000000000000..1c2fc79e1ccf
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-cpu-hs.dtso
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&cpu0_opp_table>;
+		__overlay__ {
+
+			opp-1296000000 {
+				opp-hz = /bits/ 64 <1296000000>;
+				opp-microvolt = <1325000 1325000 1400000>;
+			};
+			opp-1392000000 {
+				opp-hz = /bits/ 64 <1392000000>;
+				opp-microvolt = <1350000 1350000 1400000>;
+			};
+			/*
+			opp-1464000000 {
+				opp-hz = /bits/ 64 <1464000000>;
+				opp-microvolt = <1400000 1400000 1400000>;
+			};
+			*/
+
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-cpu-stability.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-cpu-stability.dtso
new file mode 100644
index 000000000000..f434af9268fb
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-cpu-stability.dtso
@@ -0,0 +1,52 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	/*
+		Device tree overlay that tries to overcome issues on power regulators (expecially ARM
+		power regulator) increasing lowest voltage and adding settling time to allow voltage
+		stabilization
+	*/
+
+	fragment@0 {
+		target = <&cpu0_opp_table>;
+		__overlay__ {
+
+			/*
+				Increase 600 and 800 Mhz operating points voltage to decrease the range
+				between minimum and maximum voltages
+			*/
+			opp-600000000 {
+				opp-hz = /bits/ 64 <600000000>;
+				opp-microvolt = <1100000>;
+			};
+
+			opp-816000000 {
+				opp-hz = /bits/ 64 <816000000>;
+				opp-microvolt = <1100000>;
+			};
+
+		};
+	};
+
+	fragment@1 {
+		target = <&vdd_arm>;
+		__overlay__ {
+
+			regulator-ramp-delay = <300>; // 30 uV/us, so 0.3v transition settling time is 1ms
+
+		};
+	};
+
+	fragment@2 {
+		target = <&vdd_log>;
+		__overlay__ {
+
+			regulator-ramp-delay = <600>; // 600 uV/us, so 0,3v transition settling time is 0.5ms
+
+		};
+
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-330.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-330.dtso
new file mode 100644
index 000000000000..78145548ed7c
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-330.dtso
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&dmc>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&dmc_opp_table>;
+		__overlay__ {
+			opp-534000000 {
+				status = "disabled";
+			};
+			opp-660000000 {
+				status = "disabled";
+			};
+			opp-786000000 {
+				status = "disabled";
+			};
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-528.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-528.dtso
new file mode 100644
index 000000000000..dbbd222dd8df
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-528.dtso
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&dmc>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&dmc_opp_table>;
+		__overlay__ {
+			opp-534000000 {
+				status = "okay";
+			};
+			opp-660000000 {
+				status = "disabled";
+			};
+			opp-786000000 {
+				status = "disabled";
+			};
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-660.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-660.dtso
new file mode 100644
index 000000000000..65b707515bfb
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-660.dtso
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&dmc>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&dmc_opp_table>;
+		__overlay__ {
+			opp-534000000 {
+				status = "okay";
+			};
+			opp-660000000 {
+				status = "okay";
+			};
+			opp-786000000 {
+				status = "disabled";
+			};
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-800.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-800.dtso
new file mode 100644
index 000000000000..7d11453adf9d
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ddr3-800.dtso
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&dmc>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&dmc_opp_table>;
+		__overlay__ {
+			opp-534000000 {
+				status = "okay";
+			};
+			opp-660000000 {
+				status = "okay";
+			};
+			opp-786000000 {
+				status = "okay";
+			};
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-ddr-ph180.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-ddr-ph180.dtso
new file mode 100644
index 000000000000..4ba0afb8a3a4
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-ddr-ph180.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&emmc>;
+		__overlay__ {
+			mmc-ddr-1_8v;
+			rockchip,default-sample-phase = <180>;
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-ddr-ph45.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-ddr-ph45.dtso
new file mode 100644
index 000000000000..73104525de57
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-ddr-ph45.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&emmc>;
+		__overlay__ {
+			mmc-ddr-1_8v;
+			rockchip,default-sample-phase = <45>;
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-hs200.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-hs200.dtso
new file mode 100644
index 000000000000..6ea81f5e74b0
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-hs200.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&emmc>;
+		__overlay__ {
+			mmc-hs200-1_8v;
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-pins.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-pins.dtso
new file mode 100644
index 000000000000..9b918e3172fd
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc-pins.dtso
@@ -0,0 +1,34 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&{/} {
+
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
+	};
+
+	sdmmc_pwrseq: sdmmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
+	};
+
+};
+
+&emmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr &emmc_rst>;
+	mmc-pwrseq = <&emmc_pwrseq>;
+};
+
+&sdmmc {
+	mmc-pwrseq = <&sdmmc_pwrseq>;
+};
+
+&nfc {
+	status = "disabled";
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc.dtso
new file mode 100644
index 000000000000..0a59ee30e5ee
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-emmc.dtso
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&emmc>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&nfc>;
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-fixup.scr-cmd b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-fixup.scr-cmd
new file mode 100644
index 000000000000..d4c39e20a3a2
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-fixup.scr-cmd
@@ -0,0 +1,4 @@
+# overlays fixup script
+# implements (or rather substitutes) overlay arguments functionality
+# using u-boot scripting, environment variables and "fdt" command
+
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ir-wakeup.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ir-wakeup.dtso
new file mode 100644
index 000000000000..f479a1e28d8e
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-ir-wakeup.dtso
@@ -0,0 +1,16 @@
+/dts-v1/;
+/plugin/;
+
+/*
+ * Disable regular gpio-ir-receiver and enable
+ * rockchip-ir-receiver driver; also enables virtual
+ * poweroff on shutdown to allow restart with power key
+ * on remote controller
+ */
+&ir_receiver {
+	status = "disabled";
+};
+
+&rockchip_ir_receiver {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf-default.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf-default.dtso
new file mode 100644
index 000000000000..7e4b35e333e7
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf-default.dtso
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+	fragment@0 {
+		target-path = "/gpio-leds";
+		__overlay__ {
+
+			working {
+				gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "none";
+			};
+
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf1.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf1.dtso
new file mode 100644
index 000000000000..7c76621c410d
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf1.dtso
@@ -0,0 +1,64 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+	fragment@0 {
+		target-path = "/gpio-leds";
+		__overlay__ {
+
+			working {
+				gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "none";
+			};
+
+			auxiliary {
+				gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+				label = "auxiliary";
+				linux,default-trigger = "mmc2";
+				default-state = "off";
+				pinctrl-names = "default";
+				pinctrl-0 = <&gpio_led_aux>;
+			};
+
+		};
+	};
+
+	fragment@1 {
+		target-path = "/pinctrl/gpio-items";
+		__overlay__ {
+
+			gpio_led_aux: gpio-led-aux {
+				rockchip,pins =  <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
+			reset_key: reset-key {
+				rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+			};
+
+		};
+	};
+
+	fragment@2 {
+		target = <&gpio_keys>;
+		__overlay__ {
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&reset_key>;
+
+			reset {
+				gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+				label = "reset";
+				linux,code = <KEY_RESTART>;
+				debounce-interval = <200>;
+				wakeup-source;
+			};
+
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf2.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf2.dtso
new file mode 100644
index 000000000000..79892261647c
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf2.dtso
@@ -0,0 +1,64 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+	fragment@0 {
+		target-path = "/gpio-leds";
+		__overlay__ {
+
+			working {
+				gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
+				linux,default-trigger = "none";
+			};
+
+			auxiliary {
+				gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+				label = "auxiliary";
+				linux,default-trigger = "mmc2";
+				default-state = "off";
+				pinctrl-names = "default";
+				pinctrl-0 = <&gpio_led_aux>;
+			};
+
+		};
+	};
+
+	fragment@1 {
+		target-path = "/pinctrl/gpio-items";
+		__overlay__ {
+
+			gpio_led_aux: gpio-led-aux {
+				rockchip,pins =  <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
+			reset_key: reset-key {
+				rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+			};
+
+		};
+	};
+
+	fragment@2 {
+		target = <&gpio_keys>;
+		__overlay__ {
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&reset_key>;
+
+			reset {
+				gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+				label = "reset";
+				linux,code = <KEY_RESTART>;
+				debounce-interval = <200>;
+				wakeup-source;
+			};
+
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf3.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf3.dtso
new file mode 100644
index 000000000000..9ec6d2ed0114
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf3.dtso
@@ -0,0 +1,64 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+	fragment@0 {
+		target-path = "/gpio-leds";
+		__overlay__ {
+
+			working {
+				gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "none";
+			};
+
+			auxiliary {
+				gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+				label = "auxiliary";
+				linux,default-trigger = "mmc2";
+				default-state = "off";
+				pinctrl-names = "default";
+				pinctrl-0 = <&gpio_led_aux>;
+			};
+
+		};
+	};
+
+	fragment@1 {
+		target-path = "/pinctrl/gpio-items";
+		__overlay__ {
+
+			gpio_led_aux: gpio-led-aux {
+				rockchip,pins =  <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
+			reset_key: reset-key {
+				rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+			};
+
+		};
+	};
+
+	fragment@2 {
+		target = <&gpio_keys>;
+		__overlay__ {
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&reset_key>;
+
+			reset {
+				gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+				label = "reset";
+				linux,code = <KEY_RESTART>;
+				debounce-interval = <200>;
+				wakeup-source;
+			};
+
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf4.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf4.dtso
new file mode 100644
index 000000000000..6c2ca95e6351
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf4.dtso
@@ -0,0 +1,96 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+	fragment@0 {
+		target-path = "/gpio-leds";
+		__overlay__ {
+
+			working {
+				gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "none";
+			};
+
+			auxiliary {
+				gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
+				label = "auxiliary";
+				linux,default-trigger = "mmc2";
+				default-state = "off";
+				pinctrl-names = "default";
+				pinctrl-0 = <&gpio_led_aux>;
+			};
+
+		};
+	};
+
+	fragment@1 {
+		target-path = "/pinctrl/gpio-items";
+		__overlay__ {
+
+			gpio_led_working: gpio-led-working {
+				rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
+			gpio_led_aux: gpio-led-aux {
+				rockchip,pins =  <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
+		};
+	};
+
+	fragment@2 {
+		target = <&gpio_keys>;
+		__overlay__ {
+
+			reset {
+				gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+				label = "reset";
+				linux,code = <KEY_RESTART>;
+				debounce-interval = <200>;
+				wakeup-source;
+			};
+
+		};
+	};
+
+	fragment@3 {
+		target = <&sdio_pwrseq>;
+		__overlay__ {
+
+			reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; /* GPIO2_D3 */
+
+		};
+
+	};
+
+	fragment@4 {
+		target = <&wifi_enable_h>;
+		__overlay__ {
+
+			rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+
+		};
+
+	};
+
+	fragment@5 {
+		target = <&sdio>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			wifi@1 {
+				compatible = "esp,esp8089";
+				reg = <1>;
+				esp,crystal-26M-en = <0>;
+			};
+
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf5.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf5.dtso
new file mode 100644
index 000000000000..5173872d116f
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf5.dtso
@@ -0,0 +1,97 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/*
+ * gpio configuration for AEMS IPB900 boards
+ *
+ * - enables working and auxiliary leds
+ * - fixes low strength on sdio pins for wifi
+ */
+
+/ {
+
+	fragment@0 {
+		target-path = "/gpio-leds";
+		__overlay__ {
+
+			working {
+				gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+				linux,default-trigger = "none";
+			};
+
+			auxiliary {
+				gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
+				label = "auxiliary";
+				linux,default-trigger = "mmc2";
+				default-state = "off";
+				pinctrl-names = "default";
+				pinctrl-0 = <&gpio_led_aux>;
+			};
+
+		};
+	};
+
+	fragment@1 {
+		target-path = "/pinctrl/gpio-items";
+		__overlay__ {
+
+			gpio_led_aux: gpio-led-aux {
+				rockchip,pins =  <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
+			reset_key: reset-key {
+				rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+			};
+
+		};
+	};
+
+	fragment@2 {
+		target = <&gpio_keys>;
+		__overlay__ {
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&reset_key>;
+
+			reset {
+				gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+				label = "reset";
+				linux,code = <KEY_RESTART>;
+				debounce-interval = <200>;
+				wakeup-source;
+			};
+
+		};
+	};
+
+	fragment@3 {
+		target = <&sdio_bus4>;
+		__overlay__ {
+			rockchip,pins = <3 2 1 &pcfg_pull_none_8ma>,
+					<3 3 1 &pcfg_pull_none_8ma>,
+					<3 4 1 &pcfg_pull_none_8ma>,
+					<3 5 1 &pcfg_pull_none_8ma>;
+		};
+
+	};
+
+	fragment@4 {
+		target = <&sdio_clk>;
+		__overlay__ {
+			rockchip,pins = <3 0 1 &pcfg_pull_none_8ma>;
+		};
+	};
+
+	fragment@5 {
+		target = <&sdio_cmd>;
+		__overlay__ {
+			rockchip,pins = <3 1 1 &pcfg_pull_none_8ma>;
+		};
+	};
+
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf6.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf6.dtso
new file mode 100644
index 000000000000..f7169eb5f29e
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf6.dtso
@@ -0,0 +1,96 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/*
+ * gpio configuration for MXQ_PRO eMCP boards
+ *
+ * - fixes low strength on sdio pins for wifi
+ * - correct gpio pins for wifi
+ * - set emmc pins and default phase shift
+ */
+
+/ {
+
+	fragment@0 {
+		target-path = "/pinctrl/gpio-items";
+		__overlay__ {
+
+			reset_key: reset-key {
+				rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+			};
+
+		};
+	};
+
+	fragment@1 {
+		target = <&gpio_keys>;
+		__overlay__ {
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&reset_key>;
+
+			reset {
+				gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+				label = "reset";
+				linux,code = <KEY_RESTART>;
+				debounce-interval = <200>;
+				wakeup-source;
+			};
+		
+		};
+	};
+
+	fragment@2 {
+		target = <&sdio_bus4>;
+		__overlay__ {
+			rockchip,pins = <3 2 1 &pcfg_pull_up>,
+					<3 3 1 &pcfg_pull_up>,
+					<3 4 1 &pcfg_pull_up>,
+					<3 5 1 &pcfg_pull_up>;
+		};
+
+	};
+
+	fragment@3 {
+		target = <&sdio_clk>;
+		__overlay__ {
+			rockchip,pins = <3 0 1 &pcfg_pull_none>;
+		};
+	};
+
+	fragment@4 {
+		target = <&sdio_cmd>;
+		__overlay__ {
+			rockchip,pins = <3 1 1 &pcfg_pull_up>;
+		};
+	};
+
+	fragment@5 {
+		target = <&sdio_pwrseq>;
+		__overlay__ {
+			post-power-on-delay-ms = <300>;
+			power-off-delay-us = <200000>;
+			reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	fragment@6 {
+		target = <&sdio>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			wifi@1 {
+				compatible = "esp,esp8089";
+				reg = <1>;
+				esp,crystal-26M-en = <1>;
+			};
+
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf7.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf7.dtso
new file mode 100644
index 000000000000..e37c3ab004ee
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf7.dtso
@@ -0,0 +1,180 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/*
+ * gpio configuration for R29_MXQ boards
+ *
+ */
+
+&{/gpio-leds} {
+
+	working {
+		gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+		linux,default-trigger = "none";
+		pinctrl-0 = <&gpio_led_working>;
+	};
+
+	auxiliary {
+		gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+		label = "auxiliary";
+		linux,default-trigger = "mmc2";
+		default-state = "off";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_led_auxiliary>;
+	};
+
+};
+
+&{/pinctrl/gpio-items} {
+
+	gpio_led_working: gpio-led-working {
+		rockchip,pins =  <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+	};
+
+	gpio_led_auxiliary: gpio-led-auxiliary {
+		rockchip,pins =  <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+	};
+
+	gpio_led_ethlink: gpio-led-ethlink{
+		rockchip,pins =  <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+	};
+
+	gpio_led_ethled: gpio-led-ethled{
+		rockchip,pins =  <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+	};
+
+	reset_key: reset-key {
+		rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+	};
+
+};
+
+&gpio_keys {
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&reset_key>;
+
+	reset {
+		gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+		label = "reset";
+		linux,code = <KEY_RESTART>;
+		debounce-interval = <200>;
+		wakeup-source;
+	};
+
+};
+
+&emmc {
+
+	rockchip,default-sample-phase = <112>;
+	bus-width = <8>;
+	clock-frequency = <125000000>;
+	max-frequency = <125000000>;
+
+};
+
+&vdd_arm {
+
+	compatible = "regulator-fixed";
+	regulator-name = "vdd_arm";
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-always-on;
+	regulator-boot-on;
+	vin-supply = <&vcc_sys>;
+
+};
+
+&vdd_log {
+
+	compatible = "regulator-fixed";
+	regulator-name = "vdd_log";
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-always-on;
+	regulator-boot-on;
+	vin-supply = <&vcc_sys>;
+
+};
+
+/*
+ * R29, R2B ad H20 boards require a GPIO to be turned low to enable HDMI output, we simulate it
+ * here as a regulator that must be always on.
+ * Also these boards don't have the necessary power regulators for CPU and Logic.
+ * R29 and R2B have a single power regulator fixed to 1.2v, hence the CPU can't go over 1.0 ghz
+ */
+&{/} {
+
+	vdd_hdmi_phy: vdd-hdmi-phy-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmi_phy_enable>;
+		regulator-name = "vdd-hdmi-phy";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	cpu_opp_table_r29: cpu-opp-table-r29 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1200000>;
+			clock-latency-ns = <40000>;
+			opp-suspend;
+		};
+
+		opp-816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1200000>;
+		};
+
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1200000>;
+		};
+
+	};
+
+};
+
+&pinctrl {
+
+	hdmi-phy {
+		hdmi_phy_enable: hdmi-phy-enable {
+			rockchip,pins =  <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+};
+
+&pwm1 {
+	status = "disabled";
+};
+
+&pwm2 {
+	status = "disabled";
+};
+
+&cpu0 {
+	operating-points-v2 = <&cpu_opp_table_r29>;
+};
+
+&cpu1 {
+	operating-points-v2 = <&cpu_opp_table_r29>;
+};
+
+&cpu2 {
+	operating-points-v2 = <&cpu_opp_table_r29>;
+};
+
+&cpu3 {
+	operating-points-v2 = <&cpu_opp_table_r29>;
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf8.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf8.dtso
new file mode 100644
index 000000000000..b1be4e41077a
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-led-conf8.dtso
@@ -0,0 +1,109 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/*
+ * gpio configuration for H20_221_V1.71 boards
+ *
+ */
+
+&{/gpio-leds} {
+
+	working {
+		gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+		linux,default-trigger = "none";
+		pinctrl-0 = <&gpio_led_working>;
+	};
+
+	auxiliary {
+		gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+		label = "auxiliary";
+		linux,default-trigger = "mmc2";
+		default-state = "off";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_led_auxiliary>;
+	};
+
+};
+
+&{/pinctrl/gpio-items} {
+
+	gpio_led_working: gpio-led-working {
+		rockchip,pins =  <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+	};
+
+	gpio_led_auxiliary: gpio-led-auxiliary {
+		rockchip,pins =  <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+	};
+
+	gpio_led_ethlink: gpio-led-ethlink{
+		rockchip,pins =  <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+	};
+
+	gpio_led_ethled: gpio-led-ethled{
+		rockchip,pins =  <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+	};
+
+	reset_key: reset-key {
+		rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+	};
+
+};
+
+&gpio_keys {
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&reset_key>;
+
+	reset {
+		gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+		label = "reset";
+		linux,code = <KEY_RESTART>;
+		debounce-interval = <200>;
+		wakeup-source;
+	};
+
+};
+
+&emmc {
+
+	rockchip,default-sample-phase = <112>;
+	bus-width = <8>;
+	clock-frequency = <125000000>;
+	max-frequency = <125000000>;
+
+};
+
+/*
+ * R29, R2B ad H20 boards require a GPIO to be turned low to enable HDMI output, we simulate it
+ * here as a regulator that must be always on.
+ * Also these boards don't have the necessary power regulators for CPU and Logic.
+ * R29 and R2B have a single power regulator fixed to 1.2v, hence the CPU can't go over 1.0 ghz
+ */
+&{/} {
+
+	vdd_hdmi_phy: vdd-hdmi-phy-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmi_phy_enable>;
+		regulator-name = "vdd-hdmi-phy";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+};
+
+&pinctrl {
+
+	hdmi-phy {
+		hdmi_phy_enable: hdmi-phy-enable {
+			rockchip,pins =  <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-nand.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-nand.dtso
new file mode 100644
index 000000000000..2a939ab492c8
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-nand.dtso
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&nfc>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&flash_cs0 &flash_cs1 &flash_cs2 &flash_cs3 &flash_rdy &flash_ale &flash_cle &flash_wrn &flash_bus8 &flash_dqs &flash_wp>;
+			pinctrl-names = "default";
+		};
+	};
+
+	fragment@1 {
+		target = <&emmc>;
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-usb-otg-peripheral.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-usb-otg-peripheral.dtso
new file mode 100644
index 000000000000..01e03d816c1d
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-usb-otg-peripheral.dtso
@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+/*
+ * change OTG USB port mode to "peripheral"
+ *
+ */
+
+&usb_otg {
+	dr_mode = "peripheral";
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rk322x-wlan-alt-wiring.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-wlan-alt-wiring.dtso
new file mode 100644
index 000000000000..f04c9ac166be
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rk322x-wlan-alt-wiring.dtso
@@ -0,0 +1,67 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+	fragment@0 {
+		target = <&pinctrl>;
+		__overlay__ {
+
+			pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
+				bias-disable;
+				drive-strength = <0x04>;
+			};
+
+			pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
+				bias-pull-up;
+				drive-strength = <0x04>;
+			};
+
+			sdio {
+				sdio_clk: sdio-clk {
+					rockchip,pins = <1 0 1 &pcfg_pull_none_drv_4ma>;
+				};
+
+				sdio_cmd: sdio-cmd {
+					rockchip,pins = <0 3 2 &pcfg_pull_up_drv_4ma>;
+				};
+
+				sdio_bus4: sdio-bus4 {
+					rockchip,pins = <1 1 1 &pcfg_pull_up_drv_4ma>,
+							<1 2 1 &pcfg_pull_up_drv_4ma>,
+							<1 4 1 &pcfg_pull_up_drv_4ma>,
+							<1 5 1 &pcfg_pull_up_drv_4ma>;
+				};
+			};
+
+		};
+
+	};
+
+	fragment@1 {
+		target = <&sdio_pwrseq>;
+		__overlay__ {
+			reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	fragment@2 {
+		target = <&wifi_enable_h>;
+		__overlay__ {
+			rockchip,pins = <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	fragment@3 {
+		target = <&sdio>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
+		};
+
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-ds1307.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-ds1307.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..937c261aecb88dda45e04b491b7e7337455b3dce
GIT binary patch
literal 485
zcmZ8dOHRWu5S>t1AXEfM900mu(JD<VLDf|jY<h~wwcW&uQ%AOo2xs9?T!JN60A}J;
z35+zJ&wG9|_Q&}93n2OgfEC7fj1TD7=vU}u8|;ga{yC$r8ewd?*6@-Ss-D_%xmckb
zUffxhS90&udCMm5Df-0^8sS-HUZmBm$uc4w@f*Sh^&Np|k#Na!{**qp>VbbrfM8lP
zHw`c~daW7eMOU9;OialdjAX}oBuDd329CSArrH|q`rYmkPvibk@nHY>-)^LZ8awrR
zs5^;v-Yxc@2O4Y7Y%cve{7}EcIX6|!yxM9BfdUgIgq6<CxYXLg#Hlyg<yPk4Jo5(!
Pb;0%mFImq)EqDUICu>!=

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-ds1307.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-ds1307.dtso
new file mode 100644
index 000000000000..ab7d648c2aa5
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-ds1307.dtso
@@ -0,0 +1,23 @@
+/* 	Definitions for ds1307
+*	From ASUS: https://github.com/TinkerBoard/debian_kernel/commits/develop/arch/arm/boot/dts/overlays/ds1307-overlay.dts
+*/
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+		target = <&i2c1>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			rtc: ds1307@68 {
+				compatible = "dallas,ds1307";
+				reg = <0x68>;
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-fixup.scr-cmd b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-fixup.scr-cmd
new file mode 100644
index 000000000000..d4c39e20a3a2
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-fixup.scr-cmd
@@ -0,0 +1,4 @@
+# overlays fixup script
+# implements (or rather substitutes) overlay arguments functionality
+# using u-boot scripting, environment variables and "fdt" command
+
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-i2c1.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-i2c1.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..fd1b3d988f6d737cd0ed7d3ee0bccf85574e1152
GIT binary patch
literal 262
zcmcb>`|m9S10x#)1A_$+zW`zlAQl8-0U!neIUwEuW}y;{P%bl&2CFT~PtH!x$Slw)
z$~HE#02#-?m{ydSo|~Fi;$Q$)4N}Vj#N7XZ03;tDpI??*l#^H)9}iLhl4k{Cq5SN`
zN{|2$FhMa;ZCYkUX+beWDOjy2P)<@GVTn~qVo`c(i50{)gkH|%{M>@XlFX!>R0fC=
RhT@XMlG0*^OrvB&1_1ePE@A)x

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-i2c1.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-i2c1.dtso
new file mode 100644
index 000000000000..f09f85e42cba
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-i2c1.dtso
@@ -0,0 +1,16 @@
+/* 	Definitions for i2c1
+*/
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+		target = <&i2c1>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-i2c4.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-i2c4.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..aa2836e20269ccec3d71ac5b9dd1f4b011b4ec1a
GIT binary patch
literal 262
zcmcb>`|m9S10x#)1A_$+zW`zlAQl8-0U!neIUwEuW}y;{P%bl&2CFT~PtH!x$Slw)
z$~HE#02#-?m{ydSo|~Fi;$Q$)4N}Vj#N7XZ03;tDpI??*l#^H)9}iLhl4k{Cq5SN`
zN{|2$FhMa;ZCYkUX+beWDOjy2P)<@GVTn~qVo`c(i50{)gkH|%{M>@XlFX!>R0fC=
RhT@XMlG0*^OrvBI1_1eVE@c1!

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-i2c4.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-i2c4.dtso
new file mode 100644
index 000000000000..5b43b85045fb
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-i2c4.dtso
@@ -0,0 +1,16 @@
+/* 	Definitions for i2c4
+*/
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+		target = <&i2c4>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spi0.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spi0.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..060d23bcebaf469a4b9b3069172300779f3a23dd
GIT binary patch
literal 262
zcmcb>`|m9S10x#)1A_$+zW`zlAQl8-0U!neIUwEuW}y;{P%bl&2CFT~PtH!x$Slw)
z$~HE#02#-?m{ydSo|~Fi;$Q$)4N}Vj#N7XZ03;tDpI??*l#^H)9}iLhl4k{Cq5SN`
zN{|2$FhMa;ZCYkUX+beWDOjy2P)<@GVTn~qVo`c(i50{)gkH|%{M>@XlFX!>R0fC=
RhT@XMlG0*^;(|;A1_1h~F0TLp

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spi0.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spi0.dtso
new file mode 100644
index 000000000000..d2dfcd6220e3
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spi0.dtso
@@ -0,0 +1,16 @@
+/* 	Definitions for spi0
+*/
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+		target = <&spi0>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spi2.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spi2.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..7bedbcbee8695eba83dac21dd5be5e93977b23e7
GIT binary patch
literal 262
zcmcb>`|m9S10x#)1A_$+zW`zlAQl8-0U!neIUwEuW}y;{P%bl&2CFT~PtH!x$Slw)
z$~HE#02#-?m{ydSo|~Fi;$Q$)4N}Vj#N7XZ03;tDpI??*l#^H)9}iLhl4k{Cq5SN`
zN{|2$FhMa;ZCYkUX+beWDOjy2P)<@GVTn~qVo`c(i50{)gkH|%{M>@XlFX!>R0fC=
RhT@XMlG0*^;(|;g1_1i3F0lXr

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spi2.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spi2.dtso
new file mode 100644
index 000000000000..2cd50ae4b9d1
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spi2.dtso
@@ -0,0 +1,16 @@
+/* 	Definitions for spi2
+*/
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+		target = <&spi2>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spidev0.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spidev0.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..2423a6ca4de16215567d477b22b6265ac2d627a4
GIT binary patch
literal 572
zcmb7Ay-ve05WWN$5JCb34}iKb5YfU?RSZb1Y%JX@<2b36Uu>spn0O!_hKFE9VrBsD
z>=??}lg{_^eRrRHulrx`0P!^dOaY=djA!VF=m+RzbL_wP^xqo|)fPs_)r}~`Lbd0*
zxVoI;IvmV2&nsEmo3UdPcN=~08;x+rnx)hw?-?UPz>f%9t4|3;i%hFhxg556{xJc+
z+DKql)rHj54*L=+&_X?lKR=$=>RZf%-VWw>O~HGNWHEZsow&|sx?wN<dsAJ~cKVEE
zYSp#IpUM5>1hM;zzXQ)K*SWMae`!BQv%8|HT5i=tDZx`<#M4wuV-g|D(!j{5CpqL=
d=72X$D!xiGEgw5si{5oayWn6fx1FJS3_sXVVlV&z

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spidev0.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spidev0.dtso
new file mode 100644
index 000000000000..728cde523510
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spidev0.dtso
@@ -0,0 +1,35 @@
+/* Definition for SPI0 Spidev
+ * spi port for Tinker Board
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+
+		target = <&spi0>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			spidev@0 {
+				compatible = "rockchip,spi_tinker";
+				reg = <0>;
+				spi-max-frequency = <50000000>;
+				spi-cpha = <1>;
+				status = "okay";
+			};
+
+			spidev@1 {
+				compatible = "rockchip,spi_tinker";
+				reg = <1>;
+				spi-max-frequency = <50000000>;
+				spi-cpha = <1>;
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spidev2.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spidev2.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..65f6860c6d78836ce11e2933599e826dc459dae4
GIT binary patch
literal 572
zcmb7Ay-ve05WWN$5JCb34}iKb5JAgQRSZb1Y%JX@<2b36Uu>spn0O!_hKFE9VrBsD
z>=??}lg{_^eRrRHulrx`0P!^dOaY=djA!VF=m+RzbL_wP^xqo|)fPs_)r}~`Lbd0*
zxSC9H9S&xi=asDO&81@#cN=~08;x+rnx)hw?-?UPz>f%9t4|3;i%hFhxg556{xJc+
z+DKql)rHj54*L=+&_X?qKR=$=>RZf%-VWw>O~HGNWHEZs9lOqEx?wN<dsAJ~cKVEE
zYSp#IpUM5>1hM;zzXQ)K*SWMae`!BQv%8|HT5i=tDZx`<#M4wuV-g|D(!j{5CpqL=
d=72X$D!xiGEgw5si{5oayWn6fx1FJS0zcSPVln^#

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spidev2.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spidev2.dtso
new file mode 100644
index 000000000000..262bb61d9590
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-spidev2.dtso
@@ -0,0 +1,35 @@
+/* Definition for SPI2 Spidev
+ * spi port for Tinker Board
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+
+		target = <&spi2>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			spidev@0 {
+				compatible = "rockchip,spi_tinker";
+				reg = <0>;
+				spi-max-frequency = <50000000>;
+				spi-cpha = <1>;
+				status = "okay";
+			};
+
+			spidev@1 {
+				compatible = "rockchip,spi_tinker";
+				reg = <1>;
+				spi-max-frequency = <50000000>;
+				spi-cpha = <1>;
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart1.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart1.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..0b820aa447eca40ed0a6d5321fc4033e30d9963e
GIT binary patch
literal 263
zcmcb>`|m9S10y>F1A_$+zW`zlAQl8-0U!nec_7{ZW}y;{P%bl&2CFT~PtH!x$Slw)
z$~HE#02#-?m{ydSo|~Fi;$Q$)4N}Vj#N7XZ03;tDpI??*l#^H)9}iLhl4k{Cq5SN`
zN{|2$FhMa;ZCYkUX+beWDOjy2P)<@GVTn~qVo`c(i50{)gkH|%{M>@XlFX!>R0fC=
ShT@XMlG0*^(!`<?Lk0jWT`wX4

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart1.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart1.dtso
new file mode 100644
index 000000000000..8604ff90d2a1
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart1.dtso
@@ -0,0 +1,16 @@
+/* 	Definitions for uart1
+*/
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+		target = <&uart1>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart2.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart2.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..3e57168c2ed4dbbe08b9a1d39df9dfe55b9badfb
GIT binary patch
literal 263
zcmcb>`|m9S10y>F1A_$+zW`zlAQl8-0U!nec_7{ZW}y;{P%bl&2CFT~PtH!x$Slw)
z$~HE#02#-?m{ydSo|~Fi;$Q$)4N}Vj#N7XZ03;tDpI??*l#^H)9}iLhl4k{Cq5SN`
zN{|2$FhMa;ZCYkUX+beWDOjy2P)<@GVTn~qVo`c(i50{)gkH|%{M>@XlFX!>R0fC=
ShT@XMlG0*^(!`<?BL)C0UoRs7

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart2.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart2.dtso
new file mode 100644
index 000000000000..a57873d560b6
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart2.dtso
@@ -0,0 +1,16 @@
+/* 	Definitions for uart2
+*/
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+		target = <&uart2>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart3.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart3.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..d171ece89929fa9341ad19261559b59d1ca4f9cf
GIT binary patch
literal 263
zcmcb>`|m9S10y>F1A_$+zW`zlAQl8-0U!nec_7{ZW}y;{P%bl&2CFT~PtH!x$Slw)
z$~HE#02#-?m{ydSo|~Fi;$Q$)4N}Vj#N7XZ03;tDpI??*l#^H)9}iLhl4k{Cq5SN`
zN{|2$FhMa;ZCYkUX+beWDOjy2P)<@GVTn~qVo`c(i50{)gkH|%{M>@XlFX!>R0fC=
ShT@XMlG0*^(!`<?V+H^$VJ{>A

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart3.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart3.dtso
new file mode 100644
index 000000000000..d1b77ffbf31b
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart3.dtso
@@ -0,0 +1,16 @@
+/* 	Definitions for uart3
+*/
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+		target = <&uart3>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart4.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart4.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..795fdebae94b3e1539f524396b129e2cb5bb514b
GIT binary patch
literal 263
zcmcb>`|m9S10y>F1A_$+zW`zlAQl8-0U!nec_7{ZW}y;{P%bl&2CFT~PtH!x$Slw)
z$~HE#02#-?m{ydSo|~Fi;$Q$)4N}Vj#N7XZ03;tDpI??*l#^H)9}iLhl4k{Cq5SN`
zN{|2$FhMa;ZCYkUX+beWDOjy2P)<@GVTn~qVo`c(i50{)gkH|%{M>@XlFX!>R0fC=
ShT@XMlG0*^(!`<?69xb*V=pBD

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart4.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart4.dtso
new file mode 100644
index 000000000000..13fd8f4eca92
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-uart4.dtso
@@ -0,0 +1,16 @@
+/* 	Definitions for uart4
+*/
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3288";
+
+	fragment@0 {
+		target = <&uart4>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-w1-gpio.dtbo b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-w1-gpio.dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..6bbc114521d84f9b257d602be5f843e9274d8186
GIT binary patch
literal 487
zcmah_+e*YR5S@AfMFoBGU04vcba#DO3WDH=lx#O`LoW$QYVH5{LH>nL{(^d@?RtB0
z;B;nAP9|sia`OI06uc7A3i%oN5;y}+0geao)mZ-e22;0-JZP;>%d}AD#+J9s6~^IW
zW<_4h#^28eHEVZ(qiAR;ND}=hZ6*37VJ6Ux?39(0oLGOr2i+pfjnZ6hx$}+8L|geS
zcZ_28fk0;e9IV|3u5~GTCJ@Z+0ZV{)U_V>HkL&BTuH5K{wHH7feJ>LI@ErZ|%X2Uz
zQ%|j#Mhx#=fxr8AM$9X^c>Gmgo(@x88{yTulH`TWr4P{-WK@%STZN6NrK900IWK(c
O$P}X4K;A6|eomhcOJ7a^

literal 0
HcmV?d00001

diff --git a/patch/kernel/archive/rockchip-6.10/overlay/rockchip-w1-gpio.dtso b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-w1-gpio.dtso
new file mode 100644
index 000000000000..cc1f50a91bb7
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/overlay/rockchip-w1-gpio.dtso
@@ -0,0 +1,23 @@
+/* 1-Wire GPIO
+*  From ASUS: https://github.com/TinkerBoard/debian_kernel/blob/develop/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts
+*
+*
+*/
+
+/dts-v1/;
+/plugin/;
+
+/ {
+    compatible = "rockchip,rk3288";
+    fragment@0 {
+        target-path = "/";
+        __overlay__ {
+            w1: onewire@0 {
+                compatible = "w1-gpio";
+                pinctrl-names = "default";
+                gpios = <&gpio0 17 0>;
+                status = "okay";
+            };
+        };
+    };
+};
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/bt-broadcom-serdev-workaround.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/bt-broadcom-serdev-workaround.patch
new file mode 100644
index 000000000000..8f641846c338
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/bt-broadcom-serdev-workaround.patch
@@ -0,0 +1,27 @@
+From e5c9702bd2ffd09e48c118ab40c2764590af7929 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 1 May 2021 12:41:14 +0000
+Subject: [PATCH] Workaround to make several broadcom bluetooth serdev devices
+ work even without proper MAC address
+
+---
+ drivers/bluetooth/btbcm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c
+index 1b9743b7f..b274f1cdd 100644
+--- a/drivers/bluetooth/btbcm.c
++++ b/drivers/bluetooth/btbcm.c
+@@ -129,7 +129,7 @@ int btbcm_check_bdaddr(struct hci_dev *hdev)
+ 		if (btbcm_set_bdaddr_from_efi(hdev) != 0) {
+ 			bt_dev_info(hdev, "BCM: Using default device address (%pMR)",
+ 				    &bda->bdaddr);
+-			set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks);
++			//set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks);
+ 		}
+ 	}
+ 
+
+-- 
+2.25.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/clk-rk322x-composite-mmc-clk.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/clk-rk322x-composite-mmc-clk.patch
new file mode 100644
index 000000000000..1c889e35852b
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/clk-rk322x-composite-mmc-clk.patch
@@ -0,0 +1,38 @@
+From 9e105544fcb63f8f79b199d1b194a36a354519b3 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 2 Apr 2023 10:53:07 +0000
+Subject: [PATCH 2/2] rk322x: better handle mmc/sdio clocks
+
+---
+ drivers/clk/rockchip/clk-rk3228.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 996f8bfee..0f690dd84 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -371,17 +371,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 			RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ 			RK2928_CLKGATE_CON(2), 11, GFLAGS),
+ 
+-	COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
++	COMPOSITE_DIV_OFFSET(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
+ 			RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
++			RK2928_CLKSEL_CON(12), 0, 8, DFLAGS,
+ 			RK2928_CLKGATE_CON(2), 13, GFLAGS),
+-	DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
+-			RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
+ 
+-	COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
++	COMPOSITE_DIV_OFFSET(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
+ 			RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
++			RK2928_CLKSEL_CON(12), 8, 8, DFLAGS,
+ 			RK2928_CLKGATE_CON(2), 14, GFLAGS),
+-	DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
+-			RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
+ 
+ 	/*
+ 	 * Clock-Architecture Diagram 2
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/clk-rockchip-max-frac-divider.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/clk-rockchip-max-frac-divider.patch
new file mode 100644
index 000000000000..dc81f8cd31f2
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/clk-rockchip-max-frac-divider.patch
@@ -0,0 +1,1536 @@
+From 2e1f975bbfd3ff9e50889ce8fd8d737b7f2d2c9d Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Wed, 20 Dec 2023 18:29:52 +0100
+Subject: [PATCH] rockchip fracmux limit support
+
+---
+ drivers/clk/rockchip/clk-pll.c    | 236 ++++++++++++++++++++++++++++--
+ drivers/clk/rockchip/clk-px30.c   |  29 ++--
+ drivers/clk/rockchip/clk-rk3036.c |  13 +-
+ drivers/clk/rockchip/clk-rk3128.c |  15 +-
+ drivers/clk/rockchip/clk-rk3188.c |  24 +--
+ drivers/clk/rockchip/clk-rk3228.c |  18 ++-
+ drivers/clk/rockchip/clk-rk3288.c |  19 ++-
+ drivers/clk/rockchip/clk-rk3308.c |  46 +++---
+ drivers/clk/rockchip/clk-rk3328.c |  17 ++-
+ drivers/clk/rockchip/clk-rk3368.c |  17 ++-
+ drivers/clk/rockchip/clk-rk3399.c |  32 ++--
+ drivers/clk/rockchip/clk-rv1108.c |  14 +-
+ drivers/clk/rockchip/clk.c        |  31 +++-
+ drivers/clk/rockchip/clk.h        |  27 +++-
+ include/linux/clk-provider.h      |   2 +
+ 15 files changed, 416 insertions(+), 124 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
+index 6e5e502be44a..906b813382d9 100644
+--- a/drivers/clk/rockchip/clk-pll.c
++++ b/drivers/clk/rockchip/clk-pll.c
+@@ -15,6 +15,7 @@
+ #include <linux/iopoll.h>
+ #include <linux/regmap.h>
+ #include <linux/clk.h>
++#include <linux/gcd.h>
+ #include "clk.h"
+ 
+ #define PLL_MODE_MASK		0x3
+@@ -47,6 +48,198 @@ struct rockchip_clk_pll {
+ #define to_rockchip_clk_pll_nb(nb) \
+ 			container_of(nb, struct rockchip_clk_pll, clk_nb)
+ 
++#define MHZ			(1000UL * 1000UL)
++#define KHZ			(1000UL)
++
++/* CLK_PLL_TYPE_RK3066_AUTO type ops */
++#define PLL_FREF_MIN		(269 * KHZ)
++#define PLL_FREF_MAX		(2200 * MHZ)
++
++#define PLL_FVCO_MIN		(440 * MHZ)
++#define PLL_FVCO_MAX		(2200 * MHZ)
++
++#define PLL_FOUT_MIN		(27500 * KHZ)
++#define PLL_FOUT_MAX		(2200 * MHZ)
++
++#define PLL_NF_MAX		(4096)
++#define PLL_NR_MAX		(64)
++#define PLL_NO_MAX		(16)
++
++/* CLK_PLL_TYPE_RK3036/3366/3399_AUTO type ops */
++#define MIN_FOUTVCO_FREQ	(800 * MHZ)
++#define MAX_FOUTVCO_FREQ	(2000 * MHZ)
++
++static struct rockchip_pll_rate_table auto_table;
++
++static struct rockchip_pll_rate_table *rk_pll_rate_table_get(void)
++{
++	return &auto_table;
++}
++
++static int rockchip_pll_clk_set_postdiv(unsigned long fout_hz,
++					u32 *postdiv1,
++					u32 *postdiv2,
++					u32 *foutvco)
++{
++	unsigned long freq;
++
++	if (fout_hz < MIN_FOUTVCO_FREQ) {
++		for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
++			for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
++				freq = fout_hz * (*postdiv1) * (*postdiv2);
++				if (freq >= MIN_FOUTVCO_FREQ &&
++				    freq <= MAX_FOUTVCO_FREQ) {
++					*foutvco = freq;
++					return 0;
++				}
++			}
++		}
++		pr_err("CANNOT FIND postdiv1/2 to make fout in range from 800M to 2000M,fout = %lu\n",
++		       fout_hz);
++	} else {
++		*postdiv1 = 1;
++		*postdiv2 = 1;
++	}
++	return 0;
++}
++
++static struct rockchip_pll_rate_table *
++rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
++			     unsigned long fin_hz,
++			     unsigned long fout_hz)
++{
++	struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
++	/* FIXME set postdiv1/2 always 1*/
++	u32 foutvco = fout_hz;
++	u64 fin_64, frac_64;
++	u32 f_frac, postdiv1, postdiv2;
++	unsigned long clk_gcd = 0;
++
++	if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
++		return NULL;
++
++	rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco);
++	rate_table->postdiv1 = postdiv1;
++	rate_table->postdiv2 = postdiv2;
++	rate_table->dsmpd = 1;
++
++	if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
++		fin_hz /= MHZ;
++		foutvco /= MHZ;
++		clk_gcd = gcd(fin_hz, foutvco);
++		rate_table->refdiv = fin_hz / clk_gcd;
++		rate_table->fbdiv = foutvco / clk_gcd;
++
++		rate_table->frac = 0;
++
++		pr_debug("fin = %lu, fout = %lu, clk_gcd = %lu, refdiv = %u, fbdiv = %u, postdiv1 = %u, postdiv2 = %u, frac = %u\n",
++			 fin_hz, fout_hz, clk_gcd, rate_table->refdiv,
++			 rate_table->fbdiv, rate_table->postdiv1,
++			 rate_table->postdiv2, rate_table->frac);
++	} else {
++		pr_debug("frac div running, fin_hz = %lu, fout_hz = %lu, fin_INT_mhz = %lu, fout_INT_mhz = %lu\n",
++			 fin_hz, fout_hz,
++			 fin_hz / MHZ * MHZ,
++			 fout_hz / MHZ * MHZ);
++		pr_debug("frac get postdiv1 = %u,  postdiv2 = %u, foutvco = %u\n",
++			 rate_table->postdiv1, rate_table->postdiv2, foutvco);
++		clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
++		rate_table->refdiv = fin_hz / MHZ / clk_gcd;
++		rate_table->fbdiv = foutvco / MHZ / clk_gcd;
++		pr_debug("frac get refdiv = %u,  fbdiv = %u\n",
++			 rate_table->refdiv, rate_table->fbdiv);
++
++		rate_table->frac = 0;
++
++		f_frac = (foutvco % MHZ);
++		fin_64 = fin_hz;
++		do_div(fin_64, (u64)rate_table->refdiv);
++		frac_64 = (u64)f_frac << 24;
++		do_div(frac_64, fin_64);
++		rate_table->frac = (u32)frac_64;
++		if (rate_table->frac > 0)
++			rate_table->dsmpd = 0;
++		pr_debug("frac = %x\n", rate_table->frac);
++	}
++	return rate_table;
++}
++
++static struct rockchip_pll_rate_table *
++rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
++				    unsigned long fin_hz,
++				    unsigned long fout_hz)
++{
++	struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
++	u32 nr, nf, no, nonr;
++	u32 nr_out, nf_out, no_out;
++	u32 n;
++	u32 numerator, denominator;
++	u64 fref, fvco, fout;
++	unsigned long clk_gcd = 0;
++
++	nr_out = PLL_NR_MAX + 1;
++	no_out = 0;
++	nf_out = 0;
++
++	if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
++		return NULL;
++
++	clk_gcd = gcd(fin_hz, fout_hz);
++
++	numerator = fout_hz / clk_gcd;
++	denominator = fin_hz / clk_gcd;
++
++	for (n = 1;; n++) {
++		nf = numerator * n;
++		nonr = denominator * n;
++		if (nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
++			break;
++
++		for (no = 1; no <= PLL_NO_MAX; no++) {
++			if (!(no == 1 || !(no % 2)))
++				continue;
++
++			if (nonr % no)
++				continue;
++			nr = nonr / no;
++
++			if (nr > PLL_NR_MAX)
++				continue;
++
++			fref = fin_hz / nr;
++			if (fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
++				continue;
++
++			fvco = fref * nf;
++			if (fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
++				continue;
++
++			fout = fvco / no;
++			if (fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
++				continue;
++
++			/* select the best from all available PLL settings */
++			if ((no > no_out) ||
++			    ((no == no_out) && (nr < nr_out))) {
++				nr_out = nr;
++				nf_out = nf;
++				no_out = no;
++			}
++		}
++	}
++
++	/* output the best PLL setting */
++	if ((nr_out <= PLL_NR_MAX) && (no_out > 0)) {
++		rate_table->nr = nr_out;
++		rate_table->nf = nf_out;
++		rate_table->no = no_out;
++	} else {
++		return NULL;
++	}
++
++	return rate_table;
++}
++
+ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
+ 			    struct rockchip_clk_pll *pll, unsigned long rate)
+ {
+@@ -58,24 +251,16 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
+ 			return &rate_table[i];
+ 	}
+ 
+-	return NULL;
++	if (pll->type == pll_rk3066)
++		return rockchip_rk3066_pll_clk_set_by_auto(pll, 24 * MHZ, rate);
++	else
++		return rockchip_pll_clk_set_by_auto(pll, 24 * MHZ, rate);
+ }
+ 
+ static long rockchip_pll_round_rate(struct clk_hw *hw,
+ 			    unsigned long drate, unsigned long *prate)
+ {
+-	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+-	const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
+-	int i;
+-
+-	/* Assumming rate_table is in descending order */
+-	for (i = 0; i < pll->rate_count; i++) {
+-		if (drate >= rate_table[i].rate)
+-			return rate_table[i].rate;
+-	}
+-
+-	/* return minimum supported value */
+-	return rate_table[i - 1].rate;
++	return drate;
+ }
+ 
+ /*
+@@ -165,7 +350,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
+ {
+ 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+ 	struct rockchip_pll_rate_table cur;
+-	u64 rate64 = prate;
++	u64 rate64 = prate, frac_rate64 = prate;
+ 
+ 	rockchip_rk3036_pll_get_params(pll, &cur);
+ 
+@@ -174,7 +359,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
+ 
+ 	if (cur.dsmpd == 0) {
+ 		/* fractional mode */
+-		u64 frac_rate64 = prate * cur.frac;
++		frac_rate64 *= cur.frac;
+ 
+ 		do_div(frac_rate64, cur.refdiv);
+ 		rate64 += frac_rate64 >> 24;
+@@ -210,6 +395,11 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
+ 		rate_change_remuxed = 1;
+ 	}
+ 
++	/* set pll power down */
++	writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
++			     RK3036_PLLCON1_PWRDOWN, 0),
++	       pll->reg_base + RK3036_PLLCON(1));
++
+ 	/* update pll values */
+ 	writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
+ 					  RK3036_PLLCON0_FBDIV_SHIFT) |
+@@ -231,6 +421,11 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
+ 	pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
+ 	writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
+ 
++	/* set pll power up */
++	writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
++	       pll->reg_base + RK3036_PLLCON(1));
++	udelay(1);
++
+ 	/* wait for the pll to lock */
+ 	ret = rockchip_rk3036_pll_wait_lock(pll);
+ 	if (ret) {
+@@ -692,6 +887,11 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
+ 		rate_change_remuxed = 1;
+ 	}
+ 
++	/* set pll power down */
++	writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
++			     RK3399_PLLCON3_PWRDOWN, 0),
++	       pll->reg_base + RK3399_PLLCON(3));
++
+ 	/* update pll values */
+ 	writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
+ 						  RK3399_PLLCON0_FBDIV_SHIFT),
+@@ -715,6 +915,12 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
+ 					    RK3399_PLLCON3_DSMPD_SHIFT),
+ 		       pll->reg_base + RK3399_PLLCON(3));
+ 
++	/* set pll power up */
++	writel(HIWORD_UPDATE(0,
++			     RK3399_PLLCON3_PWRDOWN, 0),
++	       pll->reg_base + RK3399_PLLCON(3));
++	udelay(1);
++
+ 	/* wait for the pll to lock */
+ 	ret = rockchip_rk3399_pll_wait_lock(pll);
+ 	if (ret) {
+diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c
+index b58619eb412b..8274f344b6b5 100644
+--- a/drivers/clk/rockchip/clk-px30.c
++++ b/drivers/clk/rockchip/clk-px30.c
+@@ -13,6 +13,7 @@
+ #include "clk.h"
+ 
+ #define PX30_GRF_SOC_STATUS0		0x480
++#define PX30_FRAC_MAX_PRATE		600000000
+ 
+ enum px30_plls {
+ 	apll, dpll, cpll, npll, apll_b_h, apll_b_l,
+@@ -425,7 +426,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(6), 0,
+ 			PX30_CLKGATE_CON(2), 3, GFLAGS,
+-			&px30_dclk_vopb_fracmux),
++			&px30_dclk_vopb_fracmux, 0),
+ 	GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
+ 			PX30_CLKGATE_CON(2), 4, GFLAGS),
+ 	COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
+@@ -434,7 +435,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(9), 0,
+ 			PX30_CLKGATE_CON(2), 7, GFLAGS,
+-			&px30_dclk_vopl_fracmux),
++			&px30_dclk_vopl_fracmux, 0),
+ 	GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
+ 			PX30_CLKGATE_CON(2), 8, GFLAGS),
+ 
+@@ -592,7 +593,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(27), 0,
+ 			PX30_CLKGATE_CON(9), 10, GFLAGS,
+-			&px30_pdm_fracmux),
++			&px30_pdm_fracmux, PX30_FRAC_MAX_PRATE),
+ 	GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
+ 			PX30_CLKGATE_CON(9), 11, GFLAGS),
+ 
+@@ -602,7 +603,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(29), 0,
+ 			PX30_CLKGATE_CON(9), 13, GFLAGS,
+-			&px30_i2s0_tx_fracmux),
++			&px30_i2s0_tx_fracmux, PX30_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
+ 			PX30_CLKGATE_CON(9), 14, GFLAGS),
+@@ -618,7 +619,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(59), 0,
+ 			PX30_CLKGATE_CON(17), 1, GFLAGS,
+-			&px30_i2s0_rx_fracmux),
++			&px30_i2s0_rx_fracmux, PX30_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
+ 			PX30_CLKGATE_CON(17), 2, GFLAGS),
+@@ -634,7 +635,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(31), 0,
+ 			PX30_CLKGATE_CON(10), 1, GFLAGS,
+-			&px30_i2s1_fracmux),
++			&px30_i2s1_fracmux, PX30_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
+ 			PX30_CLKGATE_CON(10), 2, GFLAGS),
+ 	COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0,
+@@ -649,7 +650,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(33), 0,
+ 			PX30_CLKGATE_CON(10), 5, GFLAGS,
+-			&px30_i2s2_fracmux),
++			&px30_i2s2_fracmux, PX30_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
+ 			PX30_CLKGATE_CON(10), 6, GFLAGS),
+ 	COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0,
+@@ -667,7 +668,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(36), 0,
+ 			PX30_CLKGATE_CON(10), 14, GFLAGS,
+-			&px30_uart1_fracmux),
++			&px30_uart1_fracmux, PX30_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
+ 			PX30_CLKGATE_CON(10), 15, GFLAGS),
+ 
+@@ -680,7 +681,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(39), 0,
+ 			PX30_CLKGATE_CON(11), 2, GFLAGS,
+-			&px30_uart2_fracmux),
++			&px30_uart2_fracmux, PX30_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
+ 			PX30_CLKGATE_CON(11), 3, GFLAGS),
+ 
+@@ -693,7 +694,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(42), 0,
+ 			PX30_CLKGATE_CON(11), 6, GFLAGS,
+-			&px30_uart3_fracmux),
++			&px30_uart3_fracmux, PX30_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
+ 			PX30_CLKGATE_CON(11), 7, GFLAGS),
+ 
+@@ -706,7 +707,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(45), 0,
+ 			PX30_CLKGATE_CON(11), 10, GFLAGS,
+-			&px30_uart4_fracmux),
++			&px30_uart4_fracmux, PX30_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
+ 			PX30_CLKGATE_CON(11), 11, GFLAGS),
+ 
+@@ -719,7 +720,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
+ 			PX30_CLKSEL_CON(48), 0,
+ 			PX30_CLKGATE_CON(11), 14, GFLAGS,
+-			&px30_uart5_fracmux),
++			&px30_uart5_fracmux, PX30_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
+ 			PX30_CLKGATE_CON(11), 15, GFLAGS),
+ 
+@@ -919,7 +920,7 @@ static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
+ 			PX30_PMU_CLKSEL_CON(1), 0,
+ 			PX30_PMU_CLKGATE_CON(0), 13, GFLAGS,
+-			&px30_rtc32k_pmu_fracmux),
++			&px30_rtc32k_pmu_fracmux, 0),
+ 
+ 	COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
+ 			PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
+@@ -941,7 +942,7 @@ static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
+ 			PX30_PMU_CLKSEL_CON(5), 0,
+ 			PX30_PMU_CLKGATE_CON(1), 2, GFLAGS,
+-			&px30_uart0_pmu_fracmux),
++			&px30_uart0_pmu_fracmux, PX30_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
+ 			PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),
+ 
+diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
+index d644bc155ec6..1f86bb6bb1bb 100644
+--- a/drivers/clk/rockchip/clk-rk3036.c
++++ b/drivers/clk/rockchip/clk-rk3036.c
+@@ -16,6 +16,9 @@
+ #include "clk.h"
+ 
+ #define RK3036_GRF_SOC_STATUS0	0x14c
++#define RK3036_UART_FRAC_MAX_PRATE	600000000
++#define RK3036_I2S_FRAC_MAX_PRATE	600000000
++#define RK3036_SPDIF_FRAC_MAX_PRATE	600000000
+ 
+ enum rk3036_plls {
+ 	apll, dpll, gpll,
+@@ -250,15 +253,15 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(17), 0,
+ 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
+-			&rk3036_uart0_fracmux),
++			&rk3036_uart0_fracmux, RK3036_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(18), 0,
+ 			RK2928_CLKGATE_CON(1), 11, GFLAGS,
+-			&rk3036_uart1_fracmux),
++			&rk3036_uart1_fracmux, RK3036_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(19), 0,
+ 			RK2928_CLKGATE_CON(1), 13, GFLAGS,
+-			&rk3036_uart2_fracmux),
++			&rk3036_uart2_fracmux, RK3036_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0,
+ 			RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
+@@ -311,7 +314,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(7), 0,
+ 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
+-			&rk3036_i2s_fracmux),
++			&rk3036_i2s_fracmux, RK3036_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
+ 			RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
+ 			RK2928_CLKGATE_CON(0), 13, GFLAGS),
+@@ -324,7 +327,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
+ 			RK2928_CLKSEL_CON(9), 0,
+ 			RK2928_CLKGATE_CON(2), 12, GFLAGS,
+-			&rk3036_spdif_fracmux),
++			&rk3036_spdif_fracmux, RK3036_SPDIF_FRAC_MAX_PRATE),
+ 
+ 	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
+ 			RK2928_CLKGATE_CON(1), 5, GFLAGS),
+diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
+index aa53797dbfc1..0cc478d74d17 100644
+--- a/drivers/clk/rockchip/clk-rk3128.c
++++ b/drivers/clk/rockchip/clk-rk3128.c
+@@ -13,6 +13,9 @@
+ #include "clk.h"
+ 
+ #define RK3128_GRF_SOC_STATUS0	0x14c
++#define RK3128_UART_FRAC_MAX_PRATE	600000000
++#define RK3128_I2S_FRAC_MAX_PRATE	600000000
++#define RK3128_SPDIF_FRAC_MAX_PRATE	600000000
+ 
+ enum rk3128_plls {
+ 	apll, dpll, cpll, gpll,
+@@ -360,7 +363,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(8), 0,
+ 			RK2928_CLKGATE_CON(4), 5, GFLAGS,
+-			&rk3128_i2s0_fracmux),
++			&rk3128_i2s0_fracmux, RK3128_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKGATE_CON(4), 6, GFLAGS),
+ 
+@@ -370,7 +373,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(7), 0,
+ 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
+-			&rk3128_i2s1_fracmux),
++			&rk3128_i2s1_fracmux, RK3128_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKGATE_CON(0), 14, GFLAGS),
+ 	COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
+@@ -383,7 +386,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(20), 0,
+ 			RK2928_CLKGATE_CON(2), 12, GFLAGS,
+-			&rk3128_spdif_fracmux),
++			&rk3128_spdif_fracmux, RK3128_SPDIF_FRAC_MAX_PRATE),
+ 
+ 	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
+ 			RK2928_CLKGATE_CON(1), 3, GFLAGS),
+@@ -420,15 +423,15 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(17), 0,
+ 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
+-			&rk3128_uart0_fracmux),
++			&rk3128_uart0_fracmux, RK3128_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(18), 0,
+ 			RK2928_CLKGATE_CON(1), 11, GFLAGS,
+-			&rk3128_uart1_fracmux),
++			&rk3128_uart1_fracmux, RK3128_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(19), 0,
+ 			RK2928_CLKGATE_CON(1), 13, GFLAGS,
+-			&rk3128_uart2_fracmux),
++			&rk3128_uart2_fracmux, RK3128_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
+ 			RK2928_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
+diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
+index 9c8af4d1dae0..42c517409818 100644
+--- a/drivers/clk/rockchip/clk-rk3188.c
++++ b/drivers/clk/rockchip/clk-rk3188.c
+@@ -14,6 +14,10 @@
+ 
+ #define RK3066_GRF_SOC_STATUS	0x15c
+ #define RK3188_GRF_SOC_STATUS	0xac
++#define RK3188_UART_FRAC_MAX_PRATE	600000000
++#define RK3188_I2S_FRAC_MAX_PRATE	600000000
++#define RK3188_SPDIF_FRAC_MAX_PRATE	600000000
++#define RK3188_HSADC_FRAC_MAX_PRATE	300000000
+ 
+ enum rk3188_plls {
+ 	apll, cpll, dpll, gpll,
+@@ -365,7 +369,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0,
+ 			RK2928_CLKSEL_CON(23), 0,
+ 			RK2928_CLKGATE_CON(2), 7, GFLAGS,
+-			&common_hsadc_out_fracmux),
++			&common_hsadc_out_fracmux, RK3188_HSADC_FRAC_MAX_PRATE),
+ 	INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
+ 			RK2928_CLKSEL_CON(22), 7, IFLAGS),
+ 
+@@ -379,7 +383,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(9), 0,
+ 			RK2928_CLKGATE_CON(0), 14, GFLAGS,
+-			&common_spdif_fracmux),
++			&common_spdif_fracmux, RK3188_SPDIF_FRAC_MAX_PRATE),
+ 
+ 	/*
+ 	 * Clock-Architecture Diagram 4
+@@ -413,28 +417,28 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(17), 0,
+ 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
+-			&common_uart0_fracmux),
++			&common_uart0_fracmux, RK3188_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
+ 			RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
+ 			RK2928_CLKGATE_CON(1), 10, GFLAGS),
+ 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(18), 0,
+ 			RK2928_CLKGATE_CON(1), 11, GFLAGS,
+-			&common_uart1_fracmux),
++			&common_uart1_fracmux, RK3188_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
+ 			RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
+ 			RK2928_CLKGATE_CON(1), 12, GFLAGS),
+ 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(19), 0,
+ 			RK2928_CLKGATE_CON(1), 13, GFLAGS,
+-			&common_uart2_fracmux),
++			&common_uart2_fracmux, RK3188_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
+ 			RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
+ 			RK2928_CLKGATE_CON(1), 14, GFLAGS),
+ 	COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(20), 0,
+ 			RK2928_CLKGATE_CON(1), 15, GFLAGS,
+-			&common_uart3_fracmux),
++			&common_uart3_fracmux, RK3188_UART_FRAC_MAX_PRATE),
+ 
+ 	GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
+ 
+@@ -619,21 +623,21 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(6), 0,
+ 			RK2928_CLKGATE_CON(0), 8, GFLAGS,
+-			&rk3066a_i2s0_fracmux),
++			&rk3066a_i2s0_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
+ 			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
+ 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
+ 	COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(7), 0,
+ 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
+-			&rk3066a_i2s1_fracmux),
++			&rk3066a_i2s1_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
+ 			RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
+ 			RK2928_CLKGATE_CON(0), 11, GFLAGS),
+ 	COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(8), 0,
+ 			RK2928_CLKGATE_CON(0), 12, GFLAGS,
+-			&rk3066a_i2s2_fracmux),
++			&rk3066a_i2s2_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
+ 
+ 	GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
+ 	GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
+@@ -728,7 +732,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(7), 0,
+ 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
+-			&rk3188_i2s0_fracmux),
++			&rk3188_i2s0_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
+ 
+ 	GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
+ 	GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index a24a35553e13..5dda8c9c9dad 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -15,6 +15,10 @@
+ 
+ #define RK3228_GRF_SOC_STATUS0	0x480
+ 
++#define RK3228_UART_FRAC_MAX_PRATE	600000000
++#define RK3228_SPDIF_FRAC_MAX_PRATE	600000000
++#define RK3228_I2S_FRAC_MAX_PRATE	600000000
++
+ enum rk3228_plls {
+ 	apll, dpll, cpll, gpll,
+ };
+@@ -420,7 +424,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(8), 0,
+ 			RK2928_CLKGATE_CON(0), 4, GFLAGS,
+-			&rk3228_i2s0_fracmux),
++			&rk3228_i2s0_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKGATE_CON(0), 5, GFLAGS),
+ 
+@@ -430,7 +434,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(7), 0,
+ 			RK2928_CLKGATE_CON(0), 11, GFLAGS,
+-			&rk3228_i2s1_fracmux),
++			&rk3228_i2s1_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKGATE_CON(0), 14, GFLAGS),
+ 	COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
+@@ -443,7 +447,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(30), 0,
+ 			RK2928_CLKGATE_CON(0), 8, GFLAGS,
+-			&rk3228_i2s2_fracmux),
++			&rk3228_i2s2_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
+ 
+@@ -453,7 +457,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(20), 0,
+ 			RK2928_CLKGATE_CON(2), 12, GFLAGS,
+-			&rk3228_spdif_fracmux),
++			&rk3228_spdif_fracmux, RK3228_SPDIF_FRAC_MAX_PRATE),
+ 
+ 	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
+ 			RK2928_CLKGATE_CON(1), 3, GFLAGS),
+@@ -488,15 +492,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(17), 0,
+ 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
+-			&rk3228_uart0_fracmux),
++			&rk3228_uart0_fracmux, RK3228_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(18), 0,
+ 			RK2928_CLKGATE_CON(1), 11, GFLAGS,
+-			&rk3228_uart1_fracmux),
++			&rk3228_uart1_fracmux, RK3228_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(19), 0,
+ 			RK2928_CLKGATE_CON(1), 13, GFLAGS,
+-			&rk3228_uart2_fracmux),
++			&rk3228_uart2_fracmux, RK3228_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
+ 			RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
+diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
+index baa5aebd3277..b72d3d230747 100644
+--- a/drivers/clk/rockchip/clk-rk3288.c
++++ b/drivers/clk/rockchip/clk-rk3288.c
+@@ -14,6 +14,9 @@
+ 
+ #define RK3288_GRF_SOC_CON(x)	(0x244 + x * 4)
+ #define RK3288_GRF_SOC_STATUS1	0x284
++#define RK3288_UART_FRAC_MAX_PRATE	600000000
++#define RK3288_I2S_FRAC_MAX_PRATE	600000000
++#define RK3288_SPDIF_FRAC_MAX_PRATE	600000000
+ 
+ enum rk3288_variant {
+ 	RK3288_CRU,
+@@ -363,7 +366,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
+ 			RK3288_CLKSEL_CON(8), 0,
+ 			RK3288_CLKGATE_CON(4), 2, GFLAGS,
+-			&rk3288_i2s_fracmux),
++			&rk3288_i2s_fracmux, RK3288_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
+ 			RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
+ 			RK3288_CLKGATE_CON(4), 0, GFLAGS),
+@@ -378,7 +381,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
+ 			RK3288_CLKSEL_CON(9), 0,
+ 			RK3288_CLKGATE_CON(4), 5, GFLAGS,
+-			&rk3288_spdif_fracmux),
++			&rk3288_spdif_fracmux, RK3288_SPDIF_FRAC_MAX_PRATE),
+ 	GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
+ 			RK3288_CLKGATE_CON(4), 6, GFLAGS),
+ 	COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
+@@ -387,7 +390,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
+ 			RK3288_CLKSEL_CON(41), 0,
+ 			RK3288_CLKGATE_CON(4), 8, GFLAGS,
+-			&rk3288_spdif_8ch_fracmux),
++			&rk3288_spdif_8ch_fracmux, RK3288_SPDIF_FRAC_MAX_PRATE),
+ 	GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
+ 			RK3288_CLKGATE_CON(4), 9, GFLAGS),
+ 
+@@ -588,7 +591,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+ 			RK3288_CLKSEL_CON(17), 0,
+ 			RK3288_CLKGATE_CON(1), 9, GFLAGS,
+-			&rk3288_uart0_fracmux),
++			&rk3288_uart0_fracmux, RK3288_UART_FRAC_MAX_PRATE),
+ 	MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
+ 			RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
+ 	COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
+@@ -597,28 +600,28 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
+ 			RK3288_CLKSEL_CON(18), 0,
+ 			RK3288_CLKGATE_CON(1), 11, GFLAGS,
+-			&rk3288_uart1_fracmux),
++			&rk3288_uart1_fracmux, RK3288_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
+ 			RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
+ 			RK3288_CLKGATE_CON(1), 12, GFLAGS),
+ 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
+ 			RK3288_CLKSEL_CON(19), 0,
+ 			RK3288_CLKGATE_CON(1), 13, GFLAGS,
+-			&rk3288_uart2_fracmux),
++			&rk3288_uart2_fracmux, RK3288_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
+ 			RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
+ 			RK3288_CLKGATE_CON(1), 14, GFLAGS),
+ 	COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
+ 			RK3288_CLKSEL_CON(20), 0,
+ 			RK3288_CLKGATE_CON(1), 15, GFLAGS,
+-			&rk3288_uart3_fracmux),
++			&rk3288_uart3_fracmux, RK3288_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
+ 			RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
+ 			RK3288_CLKGATE_CON(2), 12, GFLAGS),
+ 	COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
+ 			RK3288_CLKSEL_CON(7), 0,
+ 			RK3288_CLKGATE_CON(2), 13, GFLAGS,
+-			&rk3288_uart4_fracmux),
++			&rk3288_uart4_fracmux, RK3288_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
+ 			RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
+diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c
+index db3396c3e6e9..bd8e6b564132 100644
+--- a/drivers/clk/rockchip/clk-rk3308.c
++++ b/drivers/clk/rockchip/clk-rk3308.c
+@@ -13,6 +13,12 @@
+ #include "clk.h"
+ 
+ #define RK3308_GRF_SOC_STATUS0		0x380
++#define RK3308_VOP_FRAC_MAX_PRATE	270000000
++#define RK3308B_VOP_FRAC_MAX_PRATE	800000000
++#define RK3308_UART_FRAC_MAX_PRATE	800000000
++#define RK3308_PDM_FRAC_MAX_PRATE	800000000
++#define RK3308_SPDIF_FRAC_MAX_PRATE	800000000
++#define RK3308_I2S_FRAC_MAX_PRATE	800000000
+ 
+ enum rk3308_plls {
+ 	apll, dpll, vpll0, vpll1,
+@@ -333,7 +339,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(12), 0,
+ 			RK3308_CLKGATE_CON(1), 11, GFLAGS,
+-			&rk3308_uart0_fracmux),
++			&rk3308_uart0_fracmux, RK3308_UART_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
+ 			RK3308_CLKGATE_CON(1), 12, GFLAGS),
+ 
+@@ -343,7 +349,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(15), 0,
+ 			RK3308_CLKGATE_CON(1), 15, GFLAGS,
+-			&rk3308_uart1_fracmux),
++			&rk3308_uart1_fracmux, RK3308_UART_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
+ 			RK3308_CLKGATE_CON(2), 0, GFLAGS),
+ 
+@@ -353,7 +359,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(18), 0,
+ 			RK3308_CLKGATE_CON(2), 3, GFLAGS,
+-			&rk3308_uart2_fracmux),
++			&rk3308_uart2_fracmux, RK3308_UART_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKGATE_CON(2), 4, GFLAGS),
+ 
+@@ -363,7 +369,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(21), 0,
+ 			RK3308_CLKGATE_CON(2), 7, GFLAGS,
+-			&rk3308_uart3_fracmux),
++			&rk3308_uart3_fracmux, RK3308_UART_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
+ 			RK3308_CLKGATE_CON(2), 8, GFLAGS),
+ 
+@@ -373,7 +379,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(24), 0,
+ 			RK3308_CLKGATE_CON(2), 11, GFLAGS,
+-			&rk3308_uart4_fracmux),
++			&rk3308_uart4_fracmux, RK3308_UART_FRAC_MAX_PRATE),
+ 	GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
+ 			RK3308_CLKGATE_CON(2), 12, GFLAGS),
+ 
+@@ -453,7 +459,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(9), 0,
+ 			RK3308_CLKGATE_CON(1), 7, GFLAGS,
+-			&rk3308_dclk_vop_fracmux),
++			&rk3308_dclk_vop_fracmux, RK3308B_VOP_FRAC_MAX_PRATE),
+ 	GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
+ 			RK3308_CLKGATE_CON(1), 8, GFLAGS),
+ 
+@@ -584,7 +590,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
+ 			RK3308_CLKSEL_CON(3), 0,
+ 			RK3308_CLKGATE_CON(4), 3, GFLAGS,
+-			&rk3308_rtc32k_fracmux),
++			&rk3308_rtc32k_fracmux, 0),
+ 	MUX(0, "clk_rtc32k_div_src", mux_vpll0_vpll1_p, 0,
+ 			RK3308_CLKSEL_CON(2), 10, 1, MFLAGS),
+ 	COMPOSITE_NOMUX(0, "clk_rtc32k_div", "clk_rtc32k_div_src", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
+@@ -634,7 +640,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(47), 0,
+ 			RK3308_CLKGATE_CON(10), 4, GFLAGS,
+-			&rk3308_pdm_fracmux),
++			&rk3308_pdm_fracmux, RK3308_PDM_FRAC_MAX_PRATE),
+ 	GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
+ 			RK3308_CLKGATE_CON(10), 5, GFLAGS),
+ 
+@@ -644,7 +650,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(53), 0,
+ 			RK3308_CLKGATE_CON(10), 13, GFLAGS,
+-			&rk3308_i2s0_8ch_tx_fracmux),
++			&rk3308_i2s0_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(52), 12, 1, MFLAGS,
+ 			RK3308_CLKGATE_CON(10), 14, GFLAGS),
+@@ -658,7 +664,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(55), 0,
+ 			RK3308_CLKGATE_CON(11), 1, GFLAGS,
+-			&rk3308_i2s0_8ch_rx_fracmux),
++			&rk3308_i2s0_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(54), 12, 1, MFLAGS,
+ 			RK3308_CLKGATE_CON(11), 2, GFLAGS),
+@@ -671,7 +677,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(57), 0,
+ 			RK3308_CLKGATE_CON(11), 5, GFLAGS,
+-			&rk3308_i2s1_8ch_tx_fracmux),
++			&rk3308_i2s1_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", mux_i2s1_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(56), 12, 1, MFLAGS,
+ 			RK3308_CLKGATE_CON(11), 6, GFLAGS),
+@@ -685,7 +691,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(59), 0,
+ 			RK3308_CLKGATE_CON(11), 9, GFLAGS,
+-			&rk3308_i2s1_8ch_rx_fracmux),
++			&rk3308_i2s1_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", mux_i2s1_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(58), 12, 1, MFLAGS,
+ 			RK3308_CLKGATE_CON(11), 10, GFLAGS),
+@@ -698,7 +704,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_tx_frac", "clk_i2s2_8ch_tx_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(61), 0,
+ 			RK3308_CLKGATE_CON(11), 13, GFLAGS,
+-			&rk3308_i2s2_8ch_tx_fracmux),
++			&rk3308_i2s2_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S2_8CH_TX, "clk_i2s2_8ch_tx", mux_i2s2_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(60), 12, 1, MFLAGS,
+ 			RK3308_CLKGATE_CON(11), 14, GFLAGS),
+@@ -712,7 +718,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_rx_frac", "clk_i2s2_8ch_rx_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(63), 0,
+ 			RK3308_CLKGATE_CON(12), 1, GFLAGS,
+-			&rk3308_i2s2_8ch_rx_fracmux),
++			&rk3308_i2s2_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S2_8CH_RX, "clk_i2s2_8ch_rx", mux_i2s2_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(62), 12, 1, MFLAGS,
+ 			RK3308_CLKGATE_CON(12), 2, GFLAGS),
+@@ -725,7 +731,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_tx_frac", "clk_i2s3_8ch_tx_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(65), 0,
+ 			RK3308_CLKGATE_CON(12), 5, GFLAGS,
+-			&rk3308_i2s3_8ch_tx_fracmux),
++			&rk3308_i2s3_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S3_8CH_TX, "clk_i2s3_8ch_tx", mux_i2s3_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(64), 12, 1, MFLAGS,
+ 			RK3308_CLKGATE_CON(12), 6, GFLAGS),
+@@ -739,7 +745,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_rx_frac", "clk_i2s3_8ch_rx_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(67), 0,
+ 			RK3308_CLKGATE_CON(12), 9, GFLAGS,
+-			&rk3308_i2s3_8ch_rx_fracmux),
++			&rk3308_i2s3_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S3_8CH_RX, "clk_i2s3_8ch_rx", mux_i2s3_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(66), 12, 1, MFLAGS,
+ 			RK3308_CLKGATE_CON(12), 10, GFLAGS),
+@@ -752,7 +758,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(69), 0,
+ 			RK3308_CLKGATE_CON(12), 13, GFLAGS,
+-			&rk3308_i2s0_2ch_fracmux),
++			&rk3308_i2s0_2ch_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S0_2CH, "clk_i2s0_2ch", "clk_i2s0_2ch_mux", 0,
+ 			RK3308_CLKGATE_CON(12), 14, GFLAGS),
+ 	COMPOSITE_NODIV(SCLK_I2S0_2CH_OUT, "clk_i2s0_2ch_out", mux_i2s0_2ch_out_p, CLK_SET_RATE_PARENT,
+@@ -765,7 +771,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(71), 0,
+ 			RK3308_CLKGATE_CON(13), 1, GFLAGS,
+-			&rk3308_i2s1_2ch_fracmux),
++			&rk3308_i2s1_2ch_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
+ 			RK3308_CLKGATE_CON(13), 2, GFLAGS),
+ 	COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
+@@ -783,7 +789,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_spdif_tx_frac", "clk_spdif_tx_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(49), 0,
+ 			RK3308_CLKGATE_CON(10), 7, GFLAGS,
+-			&rk3308_spdif_tx_fracmux),
++			&rk3308_spdif_tx_fracmux, RK3308_SPDIF_FRAC_MAX_PRATE),
+ 	GATE(SCLK_SPDIF_TX, "clk_spdif_tx", "clk_spdif_tx_mux", 0,
+ 			RK3308_CLKGATE_CON(10), 8, GFLAGS),
+ 
+@@ -798,7 +804,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_spdif_rx_frac", "clk_spdif_rx_src", CLK_SET_RATE_PARENT,
+ 			RK3308_CLKSEL_CON(51), 0,
+ 			RK3308_CLKGATE_CON(10), 10, GFLAGS,
+-			&rk3308_spdif_rx_fracmux),
++			&rk3308_spdif_rx_fracmux, RK3308_SPDIF_FRAC_MAX_PRATE),
+ 	GATE(SCLK_SPDIF_RX, "clk_spdif_rx", "clk_spdif_rx_mux", 0,
+ 			RK3308_CLKGATE_CON(10), 11, GFLAGS),
+ 
+diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
+index 267ab54937d3..483456f4da93 100644
+--- a/drivers/clk/rockchip/clk-rk3328.c
++++ b/drivers/clk/rockchip/clk-rk3328.c
+@@ -16,6 +16,9 @@
+ #define RK3328_GRF_SOC_STATUS0		0x480
+ #define RK3328_GRF_MAC_CON1		0x904
+ #define RK3328_GRF_MAC_CON2		0x908
++#define RK3328_I2S_FRAC_MAX_PRATE       600000000
++#define RK3328_UART_FRAC_MAX_PRATE	600000000
++#define RK3328_SPDIF_FRAC_MAX_PRATE	600000000
+ 
+ enum rk3328_plls {
+ 	apll, dpll, cpll, gpll, npll,
+@@ -373,7 +376,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
+ 			RK3328_CLKSEL_CON(7), 0,
+ 			RK3328_CLKGATE_CON(1), 2, GFLAGS,
+-			&rk3328_i2s0_fracmux),
++			&rk3328_i2s0_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
+ 			RK3328_CLKGATE_CON(1), 3, GFLAGS),
+ 
+@@ -383,7 +386,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
+ 			RK3328_CLKSEL_CON(9), 0,
+ 			RK3328_CLKGATE_CON(1), 5, GFLAGS,
+-			&rk3328_i2s1_fracmux),
++			&rk3328_i2s1_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
+ 			RK3328_CLKGATE_CON(1), 6, GFLAGS),
+ 	COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
+@@ -396,7 +399,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
+ 			RK3328_CLKSEL_CON(11), 0,
+ 			RK3328_CLKGATE_CON(1), 9, GFLAGS,
+-			&rk3328_i2s2_fracmux),
++			&rk3328_i2s2_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
+ 			RK3328_CLKGATE_CON(1), 10, GFLAGS),
+ 	COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0,
+@@ -409,7 +412,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
+ 			RK3328_CLKSEL_CON(13), 0,
+ 			RK3328_CLKGATE_CON(1), 13, GFLAGS,
+-			&rk3328_spdif_fracmux),
++			&rk3328_spdif_fracmux, RK3328_SPDIF_FRAC_MAX_PRATE),
+ 
+ 	/* PD_UART */
+ 	COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0,
+@@ -424,15 +427,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
+ 			RK3328_CLKSEL_CON(15), 0,
+ 			RK3328_CLKGATE_CON(1), 15, GFLAGS,
+-			&rk3328_uart0_fracmux),
++			&rk3328_uart0_fracmux, RK3328_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
+ 			RK3328_CLKSEL_CON(17), 0,
+ 			RK3328_CLKGATE_CON(2), 1, GFLAGS,
+-			&rk3328_uart1_fracmux),
++			&rk3328_uart1_fracmux, RK3328_UART_FRAC_MAX_PRATE),
+ 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
+ 			RK3328_CLKSEL_CON(19), 0,
+ 			RK3328_CLKGATE_CON(2), 3, GFLAGS,
+-			&rk3328_uart2_fracmux),
++			&rk3328_uart2_fracmux, RK3328_UART_FRAC_MAX_PRATE),
+ 
+ 	/*
+ 	 * Clock-Architecture Diagram 4
+diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
+index 2c50cc2cc6db..8d5960f58cb2 100644
+--- a/drivers/clk/rockchip/clk-rk3368.c
++++ b/drivers/clk/rockchip/clk-rk3368.c
+@@ -12,6 +12,9 @@
+ #include "clk.h"
+ 
+ #define RK3368_GRF_SOC_STATUS0	0x480
++#define RK3368_I2S_FRAC_MAX_PRATE       600000000
++#define RK3368_UART_FRAC_MAX_PRATE	600000000
++#define RK3368_SPDIF_FRAC_MAX_PRATE	600000000
+ 
+ enum rk3368_plls {
+ 	apllb, aplll, dpll, cpll, gpll, npll,
+@@ -370,7 +373,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
+ 			  RK3368_CLKSEL_CON(28), 0,
+ 			  RK3368_CLKGATE_CON(6), 2, GFLAGS,
+-			  &rk3368_i2s_8ch_fracmux),
++			  &rk3368_i2s_8ch_fracmux, RK3368_I2S_FRAC_MAX_PRATE),
+ 	COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
+ 			RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
+ 			RK3368_CLKGATE_CON(6), 0, GFLAGS),
+@@ -382,7 +385,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
+ 			  RK3368_CLKSEL_CON(32), 0,
+ 			  RK3368_CLKGATE_CON(6), 5, GFLAGS,
+-			  &rk3368_spdif_8ch_fracmux),
++			  &rk3368_spdif_8ch_fracmux, RK3368_SPDIF_FRAC_MAX_PRATE),
+ 	GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
+ 	     RK3368_CLKGATE_CON(6), 6, GFLAGS),
+ 	COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
+@@ -391,7 +394,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
+ 			  RK3368_CLKSEL_CON(54), 0,
+ 			  RK3368_CLKGATE_CON(5), 14, GFLAGS,
+-			  &rk3368_i2s_2ch_fracmux),
++			  &rk3368_i2s_2ch_fracmux, RK3368_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
+ 	     RK3368_CLKGATE_CON(5), 15, GFLAGS),
+ 
+@@ -592,7 +595,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+ 			  RK3368_CLKSEL_CON(34), 0,
+ 			  RK3368_CLKGATE_CON(2), 1, GFLAGS,
+-			  &rk3368_uart0_fracmux),
++			  &rk3368_uart0_fracmux, RK3368_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
+ 			RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
+@@ -600,7 +603,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
+ 			  RK3368_CLKSEL_CON(36), 0,
+ 			  RK3368_CLKGATE_CON(2), 3, GFLAGS,
+-			  &rk3368_uart1_fracmux),
++			  &rk3368_uart1_fracmux, RK3368_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
+ 			RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
+@@ -608,7 +611,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
+ 			  RK3368_CLKSEL_CON(40), 0,
+ 			  RK3368_CLKGATE_CON(2), 7, GFLAGS,
+-			  &rk3368_uart3_fracmux),
++			  &rk3368_uart3_fracmux, RK3368_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
+ 			RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
+@@ -616,7 +619,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
+ 			  RK3368_CLKSEL_CON(42), 0,
+ 			  RK3368_CLKGATE_CON(2), 9, GFLAGS,
+-			  &rk3368_uart4_fracmux),
++			  &rk3368_uart4_fracmux, RK3368_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
+ 			RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
+diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
+index 9ebd6c451b3d..16dc6d498971 100644
+--- a/drivers/clk/rockchip/clk-rk3399.c
++++ b/drivers/clk/rockchip/clk-rk3399.c
+@@ -15,6 +15,12 @@
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include "clk.h"
+ 
++#define RK3399_I2S_FRAC_MAX_PRATE       800000000
++#define RK3399_UART_FRAC_MAX_PRATE	800000000
++#define RK3399_SPDIF_FRAC_MAX_PRATE	600000000
++#define RK3399_VOP_FRAC_MAX_PRATE	600000000
++#define RK3399_WIFI_FRAC_MAX_PRATE	600000000
++
+ enum rk3399_plls {
+ 	lpll, bpll, dpll, cpll, gpll, npll, vpll,
+ };
+@@ -586,7 +592,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0,
+ 			RK3399_CLKSEL_CON(99), 0,
+ 			RK3399_CLKGATE_CON(8), 14, GFLAGS,
+-			&rk3399_spdif_fracmux),
++			&rk3399_spdif_fracmux, RK3399_SPDIF_FRAC_MAX_PRATE),
+ 	GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
+ 			RK3399_CLKGATE_CON(8), 15, GFLAGS),
+ 
+@@ -600,7 +606,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
+ 			RK3399_CLKSEL_CON(96), 0,
+ 			RK3399_CLKGATE_CON(8), 4, GFLAGS,
+-			&rk3399_i2s0_fracmux),
++			&rk3399_i2s0_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
+ 			RK3399_CLKGATE_CON(8), 5, GFLAGS),
+ 
+@@ -610,7 +616,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
+ 			RK3399_CLKSEL_CON(97), 0,
+ 			RK3399_CLKGATE_CON(8), 7, GFLAGS,
+-			&rk3399_i2s1_fracmux),
++			&rk3399_i2s1_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
+ 			RK3399_CLKGATE_CON(8), 8, GFLAGS),
+ 
+@@ -620,7 +626,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
+ 			RK3399_CLKSEL_CON(98), 0,
+ 			RK3399_CLKGATE_CON(8), 10, GFLAGS,
+-			&rk3399_i2s2_fracmux),
++			&rk3399_i2s2_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
+ 	GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
+ 			RK3399_CLKGATE_CON(8), 11, GFLAGS),
+ 
+@@ -639,7 +645,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0,
+ 			RK3399_CLKSEL_CON(100), 0,
+ 			RK3399_CLKGATE_CON(9), 1, GFLAGS,
+-			&rk3399_uart0_fracmux),
++			&rk3399_uart0_fracmux, RK3399_UART_FRAC_MAX_PRATE),
+ 
+ 	MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
+ 			RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
+@@ -649,7 +655,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0,
+ 			RK3399_CLKSEL_CON(101), 0,
+ 			RK3399_CLKGATE_CON(9), 3, GFLAGS,
+-			&rk3399_uart1_fracmux),
++			&rk3399_uart1_fracmux, RK3399_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
+ 			RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
+@@ -657,7 +663,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0,
+ 			RK3399_CLKSEL_CON(102), 0,
+ 			RK3399_CLKGATE_CON(9), 5, GFLAGS,
+-			&rk3399_uart2_fracmux),
++			&rk3399_uart2_fracmux, RK3399_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
+ 			RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
+@@ -665,7 +671,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0,
+ 			RK3399_CLKSEL_CON(103), 0,
+ 			RK3399_CLKGATE_CON(9), 7, GFLAGS,
+-			&rk3399_uart3_fracmux),
++			&rk3399_uart3_fracmux, RK3399_UART_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
+ 			RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
+@@ -1168,7 +1174,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 
+ 	COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
+ 			RK3399_CLKSEL_CON(106), 0,
+-			&rk3399_dclk_vop0_fracmux),
++			&rk3399_dclk_vop0_fracmux, RK3399_VOP_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,
+ 			RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
+@@ -1198,7 +1204,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 
+ 	COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
+ 			RK3399_CLKSEL_CON(107), 0,
+-			&rk3399_dclk_vop1_fracmux),
++			&rk3399_dclk_vop1_fracmux, RK3399_VOP_FRAC_MAX_PRATE),
+ 
+ 	COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
+ 			RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
+@@ -1315,7 +1321,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 			RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
+ 	COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
+ 			RK3399_CLKSEL_CON(105), 0,
+-			RK3399_CLKGATE_CON(13), 9, GFLAGS),
++			RK3399_CLKGATE_CON(13), 9, GFLAGS, 0),
+ 
+ 	DIV(0, "clk_test_24m", "xin24m", 0,
+ 			RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
+@@ -1420,7 +1426,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
+ 
+ 	COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0,
+ 			RK3399_PMU_CLKSEL_CON(7), 0,
+-			&rk3399_pmuclk_wifi_fracmux),
++			&rk3399_pmuclk_wifi_fracmux, RK3399_WIFI_FRAC_MAX_PRATE),
+ 
+ 	MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
+ 			RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
+@@ -1449,7 +1455,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0,
+ 			RK3399_PMU_CLKSEL_CON(6), 0,
+ 			RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
+-			&rk3399_uart4_pmu_fracmux),
++			&rk3399_uart4_pmu_fracmux, RK3399_UART_FRAC_MAX_PRATE),
+ 
+ 	DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
+ 			RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
+diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
+index 5f49af3c970a..95c89800a87a 100644
+--- a/drivers/clk/rockchip/clk-rv1108.c
++++ b/drivers/clk/rockchip/clk-rv1108.c
+@@ -14,6 +14,8 @@
+ #include "clk.h"
+ 
+ #define RV1108_GRF_SOC_STATUS0	0x480
++#define RV1108_I2S_FRAC_MAX_RATE	600000000
++#define RV1108_UART_FRAC_MAX_RATE	600000000
+ 
+ enum rv1108_plls {
+ 	apll, dpll, gpll,
+@@ -504,7 +506,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
+ 			RV1108_CLKSEL_CON(8), 0,
+ 			RV1108_CLKGATE_CON(2), 1, GFLAGS,
+-			&rv1108_i2s0_fracmux),
++			&rv1108_i2s0_fracmux, RV1108_I2S_FRAC_MAX_RATE),
+ 	GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
+ 			RV1108_CLKGATE_CON(2), 2, GFLAGS),
+ 	COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0,
+@@ -517,7 +519,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
+ 			RK2928_CLKSEL_CON(9), 0,
+ 			RK2928_CLKGATE_CON(2), 5, GFLAGS,
+-			&rv1108_i2s1_fracmux),
++			&rv1108_i2s1_fracmux, RV1108_I2S_FRAC_MAX_RATE),
+ 	GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
+ 			RV1108_CLKGATE_CON(2), 6, GFLAGS),
+ 
+@@ -527,7 +529,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
+ 			RV1108_CLKSEL_CON(10), 0,
+ 			RV1108_CLKGATE_CON(2), 9, GFLAGS,
+-			&rv1108_i2s2_fracmux),
++			&rv1108_i2s2_fracmux, RV1108_I2S_FRAC_MAX_RATE),
+ 	GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
+ 			RV1108_CLKGATE_CON(2), 10, GFLAGS),
+ 
+@@ -593,15 +595,15 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
+ 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+ 			RV1108_CLKSEL_CON(16), 0,
+ 			RV1108_CLKGATE_CON(3), 2, GFLAGS,
+-			&rv1108_uart0_fracmux),
++			&rv1108_uart0_fracmux, RV1108_UART_FRAC_MAX_RATE),
+ 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
+ 			RV1108_CLKSEL_CON(17), 0,
+ 			RV1108_CLKGATE_CON(3), 4, GFLAGS,
+-			&rv1108_uart1_fracmux),
++			&rv1108_uart1_fracmux, RV1108_UART_FRAC_MAX_RATE),
+ 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
+ 			RV1108_CLKSEL_CON(18), 0,
+ 			RV1108_CLKGATE_CON(3), 6, GFLAGS,
+-			&rv1108_uart2_fracmux),
++			&rv1108_uart2_fracmux, RV1108_UART_FRAC_MAX_RATE),
+ 	GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
+ 			RV1108_CLKGATE_CON(13), 10, GFLAGS),
+ 	GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
+diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
+index e63d4f20b479..74ab9f25834a 100644
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -204,7 +219,7 @@ static struct clk *rockchip_clk_register_frac_branch(
+ 		void __iomem *base, int muxdiv_offset, u8 div_flags,
+ 		int gate_offset, u8 gate_shift, u8 gate_flags,
+ 		unsigned long flags, struct rockchip_clk_branch *child,
+-		spinlock_t *lock)
++		unsigned long max_prate, spinlock_t *lock)
+ {
+ 	struct clk_hw *hw;
+ 	struct rockchip_clk_frac *frac;
+@@ -245,6 +260,7 @@ static struct clk *rockchip_clk_register_frac_branch(
+ 	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
+ 	div->lock = lock;
+ 	div->approximation = rockchip_fractional_approximation;
++	div->max_prate = max_prate;
+ 	div_ops = &clk_fractional_divider_ops;
+ 
+ 	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+@@ -383,6 +399,8 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+ 
+ 	ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
+ 						   "rockchip,grf");
++	ctx->pmugrf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
++						   "rockchip,pmugrf");
+ 
+ 	return ctx;
+ 
+@@ -471,6 +489,13 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ 				list->mux_shift, list->mux_width,
+ 				list->mux_flags);
+ 			break;
++		case branch_muxpmugrf:
++			clk = rockchip_clk_register_muxgrf(list->name,
++				list->parent_names, list->num_parents,
++				flags, ctx->pmugrf, list->muxdiv_offset,
++				list->mux_shift, list->mux_width,
++				list->mux_flags);
++			break;
+ 		case branch_divider:
+ 			if (list->div_table)
+ 				clk = clk_register_divider_table(NULL,
+@@ -494,7 +519,7 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ 				list->div_flags,
+ 				list->gate_offset, list->gate_shift,
+ 				list->gate_flags, flags, list->child,
+-				&ctx->lock);
++				list->max_prate, &ctx->lock);
+ 			break;
+ 		case branch_half_divider:
+ 			clk = rockchip_clk_register_halfdiv(list->name,
+diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
+index ee01739e4a7c..38403e03cd1e 100644
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -285,6 +285,7 @@ struct rockchip_clk_provider {
+ 	struct clk_onecell_data clk_data;
+ 	struct device_node *cru_node;
+ 	struct regmap *grf;
++	struct regmap *pmugrf;
+ 	spinlock_t lock;
+ };
+ 
+@@ -446,6 +447,7 @@ enum rockchip_clk_branch_type {
+ 	branch_composite,
+ 	branch_mux,
+ 	branch_muxgrf,
++	branch_muxpmugrf,
+ 	branch_divider,
+ 	branch_fraction_divider,
+ 	branch_gate,
+@@ -477,6 +479,7 @@ struct rockchip_clk_branch {
+ 	u8				gate_shift;
+ 	u8				gate_flags;
+ 	struct rockchip_clk_branch	*child;
++	unsigned long			max_prate;
+ };
+ 
+ #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
+@@ -616,7 +619,7 @@ struct rockchip_clk_branch {
+ 		.gate_offset	= -1,				\
+ 	}
+ 
+-#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
++#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf, prate)\
+ 	{							\
+ 		.id		= _id,				\
+ 		.branch_type	= branch_fraction_divider,	\
+@@ -631,9 +634,10 @@ struct rockchip_clk_branch {
+ 		.gate_offset	= go,				\
+ 		.gate_shift	= gs,				\
+ 		.gate_flags	= gf,				\
++		.max_prate	= prate,			\
+ 	}
+ 
+-#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
++#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch, prate) \
+ 	{							\
+ 		.id		= _id,				\
+ 		.branch_type	= branch_fraction_divider,	\
+@@ -649,9 +653,10 @@ struct rockchip_clk_branch {
+ 		.gate_shift	= gs,				\
+ 		.gate_flags	= gf,				\
+ 		.child		= ch,				\
++		.max_prate	= prate,			\
+ 	}
+ 
+-#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
++#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch, prate) \
+ 	{							\
+ 		.id		= _id,				\
+ 		.branch_type	= branch_fraction_divider,	\
+@@ -665,6 +670,7 @@ struct rockchip_clk_branch {
+ 		.div_flags	= df,				\
+ 		.gate_offset	= -1,				\
+ 		.child		= ch,				\
++		.max_prate	= prate,			\
+ 	}
+ 
+ #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw,	\
+@@ -731,6 +737,21 @@ struct rockchip_clk_branch {
+ 		.gate_offset	= -1,				\
+ 	}
+ 
++#define MUXPMUGRF(_id, cname, pnames, f, o, s, w, mf)		\
++	{							\
++		.id		= _id,				\
++		.branch_type	= branch_muxpmugrf,		\
++		.name		= cname,			\
++		.parent_names	= pnames,			\
++		.num_parents	= ARRAY_SIZE(pnames),		\
++		.flags		= f,				\
++		.muxdiv_offset	= o,				\
++		.mux_shift	= s,				\
++		.mux_width	= w,				\
++		.mux_flags	= mf,				\
++		.gate_offset	= -1,				\
++	}
++
+ #define DIV(_id, cname, pname, f, o, s, w, df)			\
+ 	{							\
+ 		.id		= _id,				\
+diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
+index 15e336281d1f..ca7e21d0251f 100644
+--- a/include/linux/clk-provider.h
++++ b/include/linux/clk-provider.h
+@@ -1109,6 +1109,7 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
+  * @mwidth:	width of the numerator bit field
+  * @nshift:	shift to the denominator bit field
+  * @nwidth:	width of the denominator bit field
++ * @max_parent:	the maximum frequency of fractional divider parent clock
+  * @approximation: clk driver's callback for calculating the divider clock
+  * @lock:	register lock
+  *
+@@ -1139,6 +1140,7 @@ struct clk_fractional_divider {
+ 	u8		nwidth;
+ 	u32		nmask;
+ 	u8		flags;
++	unsigned long	max_prate;
+ 	void		(*approximation)(struct clk_hw *hw,
+ 				unsigned long rate, unsigned long *parent_rate,
+ 				unsigned long *m, unsigned long *n);
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/driver-rk322x-audio-codec.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/driver-rk322x-audio-codec.patch
new file mode 100644
index 000000000000..b202614fd797
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/driver-rk322x-audio-codec.patch
@@ -0,0 +1,914 @@
+From 50a8db983c682918cd2efe02ede48db93892d52a Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 20 Jul 2024 13:51:55 +0200
+Subject: [PATCH] rk3228: add analog audio codec
+
+---
+ .../bindings/sound/rockchip,rk3228-codec.txt  |  22 +
+ arch/arm/boot/dts/rockchip/rk322x.dtsi        |   9 +
+ drivers/clk/rockchip/clk-rk3228.c             |   2 +-
+ include/dt-bindings/clock/rk3228-cru.h        |   1 +
+ sound/soc/codecs/Kconfig                      |   6 +
+ sound/soc/codecs/Makefile                     |   2 +
+ sound/soc/codecs/rk3228_codec.c               | 545 ++++++++++++++++++
+ sound/soc/codecs/rk3228_codec.h               | 218 +++++++
+ 8 files changed, 804 insertions(+), 1 deletion(-)
+ create mode 100644 Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
+ create mode 100644 sound/soc/codecs/rk3228_codec.c
+ create mode 100644 sound/soc/codecs/rk3228_codec.h
+
+diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
+new file mode 100644
+index 000000000000..9191a8593380
+--- /dev/null
++++ b/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
+@@ -0,0 +1,22 @@
++* Rockchip Rk3228 internal codec
++
++Required properties:
++
++- compatible: "rockchip,rk3228-codec"
++- reg: physical base address of the controller and length of memory mapped
++  region.
++- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
++- clock-names: a list of clock names, one for each entry in clocks.
++- spk-en-gpio: speaker enable gpio.
++- spk-depop-time-ms: speaker depop time msec.
++
++Example for rk3228 internal codec:
++
++codec: codec@12010000 {
++	compatible = "rockchip,rk3228-codec";
++	reg = <0x12010000 0x1000>;
++	clocks =  <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
++	clock-names = "mclk", "pclk", "sclk";
++	spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
++	status = "disabled";
++};
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index cc5a5e609f04..d13dc979a67e 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -249,6 +249,15 @@ i2s1: i2s1@100b0000 {
+ 		status = "disabled";
+ 	};
+ 
++	codec: codec@12010000 {
++		compatible = "rockchip,rk3228-codec";
++		reg = <0x12010000 0x1000>;
++		clocks =  <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
++		clock-names = "mclk", "pclk", "sclk";
++		spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
++		status = "disabled";
++	};
++
+ 	i2s0: i2s0@100c0000 {
+ 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ 		reg = <0x100c0000 0x4000>;
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 0db8a97007f2..0f690dd84650 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -603,7 +603,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
+ 
+ 	GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
+-	GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
++	GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
+ 	GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
+ 	GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
+ 	GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
+diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
+index 911824731866..9162f9132657 100644
+--- a/include/dt-bindings/clock/rk3228-cru.h
++++ b/include/dt-bindings/clock/rk3228-cru.h
+@@ -116,6 +116,7 @@
+ #define PCLK_HDMI_CTRL		364
+ #define PCLK_HDMI_PHY		365
+ #define PCLK_GMAC		367
++#define PCLK_ACODECPHY		368
+ 
+ /* hclk gates */
+ #define HCLK_I2S0_8CH		442
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index 4afc43d3f71f..183a69249160 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -182,6 +182,7 @@ config SND_SOC_ALL_CODECS
+ 	imply SND_SOC_PCM6240
+ 	imply SND_SOC_PEB2466
+ 	imply SND_SOC_RK3308
++	imply SND_SOC_RK3228
+ 	imply SND_SOC_RK3328
+ 	imply SND_SOC_RK817
+ 	imply SND_SOC_RT274
+@@ -1457,6 +1458,11 @@ config SND_SOC_RK3308
+ 	  It has 8 24-bit ADCs and 2 24-bit DACs. The maximum supported
+ 	  sampling rate is 192 kHz.
+ 
++config SND_SOC_RK3228
++	tristate "Rockchip RK3228 audio CODEC"
++	depends on ARCH_ROCKCHIP || COMPILE_TEST
++	select REGMAP_MMIO
++
+ config SND_SOC_RK3328
+ 	tristate "Rockchip RK3328 audio CODEC"
+ 	depends on ARCH_ROCKCHIP || COMPILE_TEST
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index b4df22186e25..454179eb7b73 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -207,6 +207,7 @@ snd-soc-pcm512x-spi-y := pcm512x-spi.o
+ snd-soc-pcm6240-y := pcm6240.o
+ snd-soc-peb2466-y := peb2466.o
+ snd-soc-rk3308-y := rk3308_codec.o
++snd-soc-rk3228-y := rk3228_codec.o
+ snd-soc-rk3328-y := rk3328_codec.o
+ snd-soc-rk817-y := rk817_codec.o
+ snd-soc-rl6231-y := rl6231.o
+@@ -599,6 +600,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_SPI)	+= snd-soc-pcm512x-spi.o
+ obj-$(CONFIG_SND_SOC_PCM6240)	+= snd-soc-pcm6240.o
+ obj-$(CONFIG_SND_SOC_PEB2466)	+= snd-soc-peb2466.o
+ obj-$(CONFIG_SND_SOC_RK3308)	+= snd-soc-rk3308.o
++obj-$(CONFIG_SND_SOC_RK3228)	+= snd-soc-rk3228.o
+ obj-$(CONFIG_SND_SOC_RK3328)	+= snd-soc-rk3328.o
+ obj-$(CONFIG_SND_SOC_RK817)	+= snd-soc-rk817.o
+ obj-$(CONFIG_SND_SOC_RL6231)	+= snd-soc-rl6231.o
+diff --git a/sound/soc/codecs/rk3228_codec.c b/sound/soc/codecs/rk3228_codec.c
+new file mode 100644
+index 000000000000..197e7e2e0d8b
+--- /dev/null
++++ b/sound/soc/codecs/rk3228_codec.c
+@@ -0,0 +1,545 @@
++// SPDX-License-Identifier: GPL-2.0
++//
++// rk3228_codec.c  --  rk3228 ALSA Soc Audio driver
++//
++// Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/regmap.h>
++#include <sound/pcm_params.h>
++#include <sound/dmaengine_pcm.h>
++#include "rk3228_codec.h"
++
++/*
++ * volume setting
++ * 0: -39dB
++ * 26: 0dB
++ * 31: 6dB
++ * Step: 1.5dB
++ */
++#define OUT_VOLUME	(0x18)
++#define INITIAL_FREQ	(11289600)
++
++struct rk3228_codec_priv {
++	struct regmap *regmap;
++	struct clk *mclk;
++	struct clk *pclk;
++	struct clk *sclk;
++	struct gpio_desc *spk_en_gpio;
++	int spk_depop_time; /* msec */
++};
++
++static const struct reg_default rk3228_codec_reg_defaults[] = {
++	{ CODEC_RESET, 0x03 },
++	{ DAC_INIT_CTRL1, 0x00 },
++	{ DAC_INIT_CTRL2, 0x50 },
++	{ DAC_INIT_CTRL3, 0x0e },
++	{ DAC_PRECHARGE_CTRL, 0x01 },
++	{ DAC_PWR_CTRL, 0x00 },
++	{ DAC_CLK_CTRL, 0x00 },
++	{ HPMIX_CTRL, 0x00 },
++	{ HPOUT_CTRL, 0x00 },
++	{ HPOUTL_GAIN_CTRL, 0x00 },
++	{ HPOUTR_GAIN_CTRL, 0x00 },
++	{ HPOUT_POP_CTRL, 0x11 },
++};
++
++static int rk3228_codec_reset(struct snd_soc_component *component)
++{
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++
++	regmap_write(rk3228->regmap, CODEC_RESET, 0);
++	mdelay(10);
++	regmap_write(rk3228->regmap, CODEC_RESET, 0x03);
++
++	return 0;
++}
++
++static int rk3228_set_dai_fmt(struct snd_soc_dai *dai,
++			      unsigned int fmt)
++{
++	struct snd_soc_component *component = dai->component;
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++	unsigned int val = 0;
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBS_CFS:
++		val |= PIN_DIRECTION_IN | DAC_I2S_MODE_SLAVE;
++		break;
++	case SND_SOC_DAIFMT_CBM_CFM:
++		val |= PIN_DIRECTION_OUT | DAC_I2S_MODE_MASTER;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL1,
++			   PIN_DIRECTION_MASK | DAC_I2S_MODE_MASK, val);
++
++	val = 0;
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_DSP_A:
++	case SND_SOC_DAIFMT_DSP_B:
++		val |= DAC_MODE_PCM;
++		break;
++	case SND_SOC_DAIFMT_I2S:
++		val |= DAC_MODE_I2S;
++		break;
++	case SND_SOC_DAIFMT_RIGHT_J:
++		val |= DAC_MODE_RJM;
++		break;
++	case SND_SOC_DAIFMT_LEFT_J:
++		val |= DAC_MODE_LJM;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL2,
++			   DAC_MODE_MASK, val);
++	return 0;
++}
++
++static void rk3228_analog_output(struct rk3228_codec_priv *rk3228, int mute)
++{
++	if (rk3228->spk_en_gpio)
++		gpiod_set_value(rk3228->spk_en_gpio, mute);
++}
++
++static int rk3228_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
++{
++	struct snd_soc_component *component = dai->component;
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++	unsigned int val = 0;
++
++	if (direction != SNDRV_PCM_STREAM_PLAYBACK)
++		return 0;
++
++	if (mute)
++		val = HPOUTL_MUTE | HPOUTR_MUTE;
++	else
++		val = HPOUTL_UNMUTE | HPOUTR_UNMUTE;
++
++	regmap_update_bits(rk3228->regmap, HPOUT_CTRL,
++			   HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK, val);
++	return 0;
++}
++
++static int rk3228_codec_power_on(struct snd_soc_component *component, int wait_ms)
++{
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_PRECHARGE);
++	mdelay(10);
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_CURRENT_ALL_MASK,
++			   DAC_CHARGE_CURRENT_ALL_ON);
++
++	mdelay(wait_ms);
++
++	return 0;
++}
++
++static int rk3228_codec_power_off(struct snd_soc_component *component, int wait_ms)
++{
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_DISCHARGE);
++	mdelay(10);
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_CURRENT_ALL_MASK,
++			   DAC_CHARGE_CURRENT_ALL_ON);
++
++	mdelay(wait_ms);
++
++	return 0;
++}
++
++static struct rk3228_reg_msk_val playback_open_list[] = {
++	{ DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_ON },
++	{ DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
++	  DACL_PATH_REFV_ON | DACR_PATH_REFV_ON },
++	{ DAC_PWR_CTRL, HPOUTL_ZERO_CROSSING_ON | HPOUTR_ZERO_CROSSING_ON,
++	  HPOUTL_ZERO_CROSSING_ON | HPOUTR_ZERO_CROSSING_ON },
++	{ HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
++	  HPOUTR_POP_WORK | HPOUTL_POP_WORK },
++	{ HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_EN | HPMIXR_EN },
++	{ HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
++	  HPMIXL_INIT_EN | HPMIXR_INIT_EN },
++	{ HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_EN | HPOUTR_EN },
++	{ HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
++	  HPOUTL_INIT_EN | HPOUTR_INIT_EN },
++	{ DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
++	  DACL_REFV_ON | DACR_REFV_ON },
++	{ DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
++	  DACL_CLK_ON | DACR_CLK_ON },
++	{ DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_ON | DACR_ON },
++	{ DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
++	  DACL_INIT_ON | DACR_INIT_ON },
++	{ DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
++	  DACL_SELECT | DACR_SELECT },
++	{ HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
++	  HPMIXL_INIT2_EN | HPMIXR_INIT2_EN },
++	{ HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
++	  HPOUTL_UNMUTE | HPOUTR_UNMUTE },
++};
++
++#define PLAYBACK_OPEN_LIST_LEN ARRAY_SIZE(playback_open_list)
++
++static int rk3228_codec_open_playback(struct snd_soc_component *component)
++{
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++	int i = 0;
++
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_CURRENT_ALL_MASK,
++			   DAC_CHARGE_CURRENT_I);
++
++	for (i = 0; i < PLAYBACK_OPEN_LIST_LEN; i++) {
++		regmap_update_bits(rk3228->regmap,
++				   playback_open_list[i].reg,
++				   playback_open_list[i].msk,
++				   playback_open_list[i].val);
++		mdelay(1);
++	}
++
++	msleep(rk3228->spk_depop_time);
++	rk3228_analog_output(rk3228, 1);
++
++	regmap_update_bits(rk3228->regmap, HPOUTL_GAIN_CTRL,
++			   HPOUTL_GAIN_MASK, OUT_VOLUME);
++	regmap_update_bits(rk3228->regmap, HPOUTR_GAIN_CTRL,
++			   HPOUTR_GAIN_MASK, OUT_VOLUME);
++	return 0;
++}
++
++static struct rk3228_reg_msk_val playback_close_list[] = {
++	{ HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
++	  HPMIXL_INIT2_DIS | HPMIXR_INIT2_DIS },
++	{ DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
++	  DACL_DESELECT | DACR_DESELECT },
++	{ HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
++	  HPOUTL_MUTE | HPOUTR_MUTE },
++	{ HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
++	  HPOUTL_INIT_DIS | HPOUTR_INIT_DIS },
++	{ HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_DIS | HPOUTR_DIS },
++	{ HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_DIS | HPMIXR_DIS },
++	{ DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_OFF | DACR_OFF },
++	{ DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
++	  DACL_CLK_OFF | DACR_CLK_OFF },
++	{ DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
++	  DACL_REFV_OFF | DACR_REFV_OFF },
++	{ HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
++	  HPOUTR_POP_XCHARGE | HPOUTL_POP_XCHARGE },
++	{ DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
++	  DACL_PATH_REFV_OFF | DACR_PATH_REFV_OFF },
++	{ DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_OFF },
++	{ HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
++	  HPMIXL_INIT_DIS | HPMIXR_INIT_DIS },
++	{ DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
++	  DACL_INIT_OFF | DACR_INIT_OFF },
++};
++
++#define PLAYBACK_CLOSE_LIST_LEN ARRAY_SIZE(playback_close_list)
++
++static int rk3228_codec_close_playback(struct snd_soc_component *component)
++{
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++	int i = 0;
++
++	rk3228_analog_output(rk3228, 0);
++
++	regmap_update_bits(rk3228->regmap, HPOUTL_GAIN_CTRL,
++			   HPOUTL_GAIN_MASK, 0);
++	regmap_update_bits(rk3228->regmap, HPOUTR_GAIN_CTRL,
++			   HPOUTR_GAIN_MASK, 0);
++
++	for (i = 0; i < PLAYBACK_CLOSE_LIST_LEN; i++) {
++		regmap_update_bits(rk3228->regmap,
++				   playback_close_list[i].reg,
++				   playback_close_list[i].msk,
++				   playback_close_list[i].val);
++		mdelay(1);
++	}
++
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_CURRENT_ALL_MASK,
++			   DAC_CHARGE_CURRENT_I);
++	return 0;
++}
++
++static int rk3228_hw_params(struct snd_pcm_substream *substream,
++			    struct snd_pcm_hw_params *params,
++			    struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++	unsigned int val = 0;
++
++	switch (params_format(params)) {
++	case SNDRV_PCM_FORMAT_S16_LE:
++		val |= DAC_VDL_16BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S20_3LE:
++		val |= DAC_VDL_20BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S24_LE:
++		val |= DAC_VDL_24BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S32_LE:
++		val |= DAC_VDL_32BITS;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL2, DAC_VDL_MASK, val);
++	val = DAC_WL_32BITS | DAC_RST_DIS;
++	regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL3,
++			   DAC_WL_MASK | DAC_RST_MASK, val);
++
++	return 0;
++}
++
++static int rk3228_pcm_startup(struct snd_pcm_substream *substream,
++			      struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++
++	return rk3228_codec_open_playback(component);
++}
++
++static void rk3228_pcm_shutdown(struct snd_pcm_substream *substream,
++				struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++
++	rk3228_codec_close_playback(component);
++}
++
++static struct snd_soc_dai_ops rk3228_dai_ops = {
++	.hw_params = rk3228_hw_params,
++	.set_fmt = rk3228_set_dai_fmt,
++	.mute_stream = rk3228_mute_stream,
++	.startup = rk3228_pcm_startup,
++	.shutdown = rk3228_pcm_shutdown,
++};
++
++static struct snd_soc_dai_driver rk3228_dai[] = {
++	{
++		.name = "rk3228-hifi",
++		.id = RK3228_HIFI,
++		.playback = {
++			.stream_name = "HIFI Playback",
++			.channels_min = 1,
++			.channels_max = 2,
++			.rates = SNDRV_PCM_RATE_8000_96000,
++			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++				    SNDRV_PCM_FMTBIT_S20_3LE |
++				    SNDRV_PCM_FMTBIT_S24_LE |
++				    SNDRV_PCM_FMTBIT_S32_LE),
++		},
++		/*.capture = {
++			.stream_name = "HIFI Capture",
++			.channels_min = 2,
++			.channels_max = 8,
++			.rates = SNDRV_PCM_RATE_8000_96000,
++			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++				    SNDRV_PCM_FMTBIT_S20_3LE |
++				    SNDRV_PCM_FMTBIT_S24_LE |
++				    SNDRV_PCM_FMTBIT_S32_LE),
++		},*/
++		.ops = &rk3228_dai_ops,
++	},
++};
++
++static int rk3228_codec_probe(struct snd_soc_component *component)
++{
++	rk3228_codec_reset(component);
++	rk3228_codec_power_on(component, 0);
++
++	return 0;
++}
++
++static void rk3228_codec_remove(struct snd_soc_component *component)
++{
++	rk3228_codec_close_playback(component);
++	rk3228_codec_power_off(component, 0);
++}
++
++static struct snd_soc_component_driver soc_codec_dev_rk3228 = {
++	.probe = rk3228_codec_probe,
++	.remove = rk3228_codec_remove,
++};
++
++static bool rk3228_codec_write_read_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case CODEC_RESET:
++	case DAC_INIT_CTRL1:
++	case DAC_INIT_CTRL2:
++	case DAC_INIT_CTRL3:
++	case DAC_PRECHARGE_CTRL:
++	case DAC_PWR_CTRL:
++	case DAC_CLK_CTRL:
++	case HPMIX_CTRL:
++	case DAC_SELECT:
++	case HPOUT_CTRL:
++	case HPOUTL_GAIN_CTRL:
++	case HPOUTR_GAIN_CTRL:
++	case HPOUT_POP_CTRL:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static bool rk3228_codec_volatile_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case CODEC_RESET:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static const struct regmap_config rk3228_codec_regmap_config = {
++	.reg_bits = 32,
++	.reg_stride = 4,
++	.val_bits = 32,
++	.max_register = HPOUT_POP_CTRL,
++	.writeable_reg = rk3228_codec_write_read_reg,
++	.readable_reg = rk3228_codec_write_read_reg,
++	.volatile_reg = rk3228_codec_volatile_reg,
++	.reg_defaults = rk3228_codec_reg_defaults,
++	.num_reg_defaults = ARRAY_SIZE(rk3228_codec_reg_defaults),
++	.cache_type = REGCACHE_FLAT,
++};
++
++#ifdef CONFIG_OF
++static const struct of_device_id rk3228codec_of_match[] = {
++	{ .compatible = "rockchip,rk3228-codec", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, rk3228codec_of_match);
++#endif
++
++static int rk3228_platform_probe(struct platform_device *pdev)
++{
++	struct device_node *rk3228_np = pdev->dev.of_node;
++	struct rk3228_codec_priv *rk3228;
++	struct resource *res;
++	void __iomem *base;
++	int ret = 0;
++
++	rk3228 = devm_kzalloc(&pdev->dev, sizeof(*rk3228), GFP_KERNEL);
++	if (!rk3228)
++		return -ENOMEM;
++
++	rk3228->mclk = devm_clk_get(&pdev->dev, "mclk");
++	if (PTR_ERR(rk3228->mclk) == -EPROBE_DEFER)
++		return -EPROBE_DEFER;
++
++	rk3228->pclk = devm_clk_get(&pdev->dev, "pclk");
++	if (IS_ERR(rk3228->pclk))
++		return PTR_ERR(rk3228->pclk);
++
++	rk3228->sclk = devm_clk_get(&pdev->dev, "sclk");
++	if (IS_ERR(rk3228->sclk))
++		return PTR_ERR(rk3228->sclk);
++
++	rk3228->spk_en_gpio = devm_gpiod_get_optional(&pdev->dev,
++						      "spk-en",
++						      GPIOD_OUT_LOW);
++	if (IS_ERR(rk3228->spk_en_gpio))
++		return PTR_ERR(rk3228->spk_en_gpio);
++
++	ret = of_property_read_u32(rk3228_np, "spk-depop-time-ms",
++				   &rk3228->spk_depop_time);
++	if (ret < 0) {
++		dev_info(&pdev->dev, "spk_depop_time use default value.\n");
++		rk3228->spk_depop_time = 100;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	ret = clk_prepare_enable(rk3228->mclk);
++	if (ret)
++		return ret;
++
++	ret = clk_prepare_enable(rk3228->pclk);
++	if (ret < 0)
++		goto err_pclk;
++
++	ret = clk_prepare_enable(rk3228->sclk);
++	if (ret)
++		goto err_sclk;
++
++	clk_set_rate(rk3228->sclk, INITIAL_FREQ);
++
++	rk3228->regmap = devm_regmap_init_mmio(&pdev->dev, base,
++					       &rk3228_codec_regmap_config);
++	if (IS_ERR(rk3228->regmap)) {
++		ret = PTR_ERR(rk3228->regmap);
++		goto err_clk;
++	}
++
++	platform_set_drvdata(pdev, rk3228);
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk3228,
++					      rk3228_dai, ARRAY_SIZE(rk3228_dai));
++	if (!ret)
++		return 0;
++
++err_clk:
++	clk_disable_unprepare(rk3228->sclk);
++err_sclk:
++	clk_disable_unprepare(rk3228->pclk);
++err_pclk:
++	clk_disable_unprepare(rk3228->mclk);
++
++	return ret;
++}
++
++static int rk3228_platform_remove(struct platform_device *pdev)
++{
++	struct rk3228_codec_priv *rk3228 = platform_get_drvdata(pdev);
++
++	if (!IS_ERR(rk3228->mclk))
++		clk_disable_unprepare(rk3228->mclk);
++
++	if (!IS_ERR(rk3228->pclk))
++		clk_disable_unprepare(rk3228->pclk);
++
++	if (!IS_ERR(rk3228->sclk))
++		clk_disable_unprepare(rk3228->sclk);
++
++	return 0;
++}
++
++static struct platform_driver rk3228_codec_driver = {
++	.driver = {
++		   .name = "rk3228-codec",
++		   .of_match_table = of_match_ptr(rk3228codec_of_match),
++	},
++	.probe = rk3228_platform_probe,
++	.remove = rk3228_platform_remove,
++};
++module_platform_driver(rk3228_codec_driver);
++
++MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
++MODULE_DESCRIPTION("ASoC rk3228 codec driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/sound/soc/codecs/rk3228_codec.h b/sound/soc/codecs/rk3228_codec.h
+new file mode 100644
+index 000000000000..7283d0ba86e8
+--- /dev/null
++++ b/sound/soc/codecs/rk3228_codec.h
+@@ -0,0 +1,218 @@
++/*
++ * rk3228_codec.h  --  rk3228 ALSA Soc Audio driver
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++#ifndef _RK3228_CODEC_H
++#define _RK3228_CODEC_H
++
++/* codec register */
++#define CODEC_RESET			(0x00 << 2)
++#define DAC_INIT_CTRL1			(0x03 << 2)
++#define DAC_INIT_CTRL2			(0x04 << 2)
++#define DAC_INIT_CTRL3			(0x05 << 2)
++#define DAC_PRECHARGE_CTRL		(0x22 << 2)
++#define DAC_PWR_CTRL			(0x23 << 2)
++#define DAC_CLK_CTRL			(0x24 << 2)
++#define HPMIX_CTRL			(0x25 << 2)
++#define DAC_SELECT			(0x26 << 2)
++#define HPOUT_CTRL			(0x27 << 2)
++#define HPOUTL_GAIN_CTRL		(0x28 << 2)
++#define HPOUTR_GAIN_CTRL		(0x29 << 2)
++#define HPOUT_POP_CTRL			(0x2a << 2)
++
++/* REG00: CODEC_RESET */
++#define PWR_RST_BYPASS_DIS		BIT(6)
++#define PWR_RST_BYPASS_EN		BIT(6)
++#define DIG_CORE_RST			(0 << 1)
++#define DIG_CORE_WORK			BIT(1)
++#define SYS_RST				(0)
++#define SYS_WORK			BIT(0)
++
++/* REG03: DAC_INIT_CTRL1 */
++#define PIN_DIRECTION_MASK		BIT(5)
++#define PIN_DIRECTION_IN		(0 << 5)
++#define PIN_DIRECTION_OUT		BIT(5)
++#define DAC_I2S_MODE_MASK		BIT(4)
++#define DAC_I2S_MODE_SLAVE		(0 << 4)
++#define DAC_I2S_MODE_MASTER		BIT(4)
++
++/* REG04: DAC_INIT_CTRL2 */
++#define DAC_I2S_LRP_MASK		BIT(7)
++#define DAC_I2S_LRP_NORMAL		(0 << 7)
++#define DAC_I2S_LRP_REVERSAL		BIT(7)
++#define DAC_VDL_MASK			(3 << 5)
++#define DAC_VDL_16BITS			(0 << 5)
++#define DAC_VDL_20BITS			BIT(5)
++#define DAC_VDL_24BITS			(2 << 5)
++#define DAC_VDL_32BITS			(3 << 5)
++#define DAC_MODE_MASK			(3 << 3)
++#define DAC_MODE_RJM			(0 << 3)
++#define DAC_MODE_LJM			BIT(3)
++#define DAC_MODE_I2S			(2 << 3)
++#define DAC_MODE_PCM			(3 << 3)
++#define DAC_LR_SWAP_MASK		BIT(2)
++#define DAC_LR_SWAP_DIS			(0 << 2)
++#define DAC_LR_SWAP_EN			BIT(2)
++
++/* REG05: DAC_INIT_CTRL3 */
++#define DAC_WL_MASK			(3 << 2)
++#define DAC_WL_16BITS			(0 << 2)
++#define DAC_WL_20BITS			BIT(2)
++#define DAC_WL_24BITS			(2 << 2)
++#define DAC_WL_32BITS			(3 << 2)
++#define DAC_RST_MASK			BIT(1)
++#define DAC_RST_EN			(0 << 1)
++#define DAC_RST_DIS			BIT(1)
++#define DAC_BCP_MASK			BIT(0)
++#define DAC_BCP_NORMAL			(0 << 0)
++#define DAC_BCP_REVERSAL		BIT(0)
++
++/* REG22: DAC_PRECHARGE_CTRL */
++#define DAC_CHARGE_PRECHARGE		BIT(7)
++#define DAC_CHARGE_DISCHARGE		(0 << 7)
++#define DAC_CHARGE_XCHARGE_MASK		BIT(7)
++#define DAC_CHARGE_CURRENT_64I		BIT(6)
++#define DAC_CHARGE_CURRENT_64I_MASK	BIT(6)
++#define DAC_CHARGE_CURRENT_32I		BIT(5)
++#define DAC_CHARGE_CURRENT_32I_MASK	BIT(5)
++#define DAC_CHARGE_CURRENT_16I		BIT(4)
++#define DAC_CHARGE_CURRENT_16I_MASK	BIT(4)
++#define DAC_CHARGE_CURRENT_08I		BIT(3)
++#define DAC_CHARGE_CURRENT_08I_MASK	BIT(3)
++#define DAC_CHARGE_CURRENT_04I		BIT(2)
++#define DAC_CHARGE_CURRENT_04I_MASK	BIT(2)
++#define DAC_CHARGE_CURRENT_02I		BIT(1)
++#define DAC_CHARGE_CURRENT_02I_MASK	BIT(1)
++#define DAC_CHARGE_CURRENT_I		BIT(0)
++#define DAC_CHARGE_CURRENT_I_MASK	BIT(0)
++#define DAC_CHARGE_CURRENT_ALL_MASK	(0x7f)
++#define DAC_CHARGE_CURRENT_ALL_OFF	(0x0)
++#define DAC_CHARGE_CURRENT_ALL_ON	(0x7f)
++
++/* REG23: DAC_PWR_CTRL */
++#define DAC_PWR_OFF			(0 << 6)
++#define DAC_PWR_ON			BIT(6)
++#define DAC_PWR_MASK			BIT(6)
++#define DACL_PATH_REFV_OFF		(0 << 5)
++#define DACL_PATH_REFV_ON		BIT(5)
++#define DACL_PATH_REFV_MASK		BIT(5)
++#define HPOUTL_ZERO_CROSSING_OFF	(0 << 4)
++#define HPOUTL_ZERO_CROSSING_ON		BIT(4)
++#define DACR_PATH_REFV_OFF		(0 << 1)
++#define DACR_PATH_REFV_ON		BIT(1)
++#define DACR_PATH_REFV_MASK		BIT(1)
++#define HPOUTR_ZERO_CROSSING_OFF	(0 << 0)
++#define HPOUTR_ZERO_CROSSING_ON		BIT(0)
++
++/* REG24: DAC_CLK_CTRL */
++#define DACL_REFV_OFF			(0 << 7)
++#define DACL_REFV_ON			BIT(7)
++#define DACL_REFV_MASK			BIT(7)
++#define DACL_CLK_OFF			(0 << 6)
++#define DACL_CLK_ON			BIT(6)
++#define DACL_CLK_MASK			BIT(6)
++#define DACL_OFF			(0 << 5)
++#define DACL_ON				BIT(5)
++#define DACL_MASK			BIT(5)
++#define DACL_INIT_OFF			(0 << 4)
++#define DACL_INIT_ON			BIT(4)
++#define DACL_INIT_MASK			BIT(4)
++#define DACR_REFV_OFF			(0 << 3)
++#define DACR_REFV_ON			BIT(3)
++#define DACR_REFV_MASK			BIT(3)
++#define DACR_CLK_OFF			(0 << 2)
++#define DACR_CLK_ON			BIT(2)
++#define DACR_CLK_MASK			BIT(2)
++#define DACR_OFF			(0 << 1)
++#define DACR_ON				BIT(1)
++#define DACR_MASK			BIT(1)
++#define DACR_INIT_OFF			(0 << 0)
++#define DACR_INIT_ON			BIT(0)
++#define DACR_INIT_MASK			BIT(0)
++
++/* REG25: HPMIX_CTRL*/
++#define HPMIXL_DIS			(0 << 6)
++#define HPMIXL_EN			BIT(6)
++#define HPMIXL_MASK			BIT(6)
++#define HPMIXL_INIT_DIS			(0 << 5)
++#define HPMIXL_INIT_EN			BIT(5)
++#define HPMIXL_INIT_MASK		BIT(5)
++#define HPMIXL_INIT2_DIS		(0 << 4)
++#define HPMIXL_INIT2_EN			BIT(4)
++#define HPMIXL_INIT2_MASK		BIT(4)
++#define HPMIXR_DIS			(0 << 2)
++#define HPMIXR_EN			BIT(2)
++#define HPMIXR_MASK			BIT(2)
++#define HPMIXR_INIT_DIS			(0 << 1)
++#define HPMIXR_INIT_EN			BIT(1)
++#define HPMIXR_INIT_MASK		BIT(1)
++#define HPMIXR_INIT2_DIS		(0 << 0)
++#define HPMIXR_INIT2_EN			BIT(0)
++#define HPMIXR_INIT2_MASK		BIT(0)
++
++/* REG26: DAC_SELECT */
++#define DACL_SELECT			BIT(4)
++#define DACL_SELECT_MASK		BIT(4)
++#define DACL_DESELECT			(0 << 4)
++#define DACR_SELECT			BIT(0)
++#define DACR_SELECT_MASK		BIT(0)
++#define DACR_DESELECT			(0 << 0)
++
++/* REG27: HPOUT_CTRL */
++#define HPOUTL_DIS			(0 << 7)
++#define HPOUTL_EN			BIT(7)
++#define HPOUTL_MASK			BIT(7)
++#define HPOUTL_INIT_DIS			(0 << 6)
++#define HPOUTL_INIT_EN			BIT(6)
++#define HPOUTL_INIT_MASK		BIT(6)
++#define HPOUTL_MUTE			(0 << 5)
++#define HPOUTL_UNMUTE			BIT(5)
++#define HPOUTL_MUTE_MASK		BIT(5)
++#define HPOUTR_DIS			(0 << 4)
++#define HPOUTR_EN			BIT(4)
++#define HPOUTR_MASK			BIT(4)
++#define HPOUTR_INIT_DIS			(0 << 3)
++#define HPOUTR_INIT_EN			BIT(3)
++#define HPOUTR_INIT_MASK		BIT(3)
++#define HPOUTR_MUTE			(0 << 2)
++#define HPOUTR_UNMUTE			BIT(2)
++#define HPOUTR_MUTE_MASK		BIT(2)
++
++/* REG28: HPOUTL_GAIN_CTRL */
++#define HPOUTL_GAIN_MASK		(0X1f << 0)
++
++/* REG29: HPOUTR_GAIN_CTRL */
++#define HPOUTR_GAIN_MASK		(0X1f << 0)
++
++/* REG2a: HPOUT_POP_CTRL */
++#define HPOUTR_POP_XCHARGE		BIT(4)
++#define HPOUTR_POP_WORK			(2 << 4)
++#define HPOUTR_POP_MASK			(3 << 4)
++#define HPOUTL_POP_XCHARGE		BIT(0)
++#define HPOUTL_POP_WORK			(2 << 0)
++#define HPOUTL_POP_MASK			(3 << 0)
++
++#define RK3228_HIFI			(0)
++
++struct rk3228_reg_msk_val {
++	unsigned int reg;
++	unsigned int msk;
++	unsigned int val;
++};
++
++#endif
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/driver-rk3288-gpiomem.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/driver-rk3288-gpiomem.patch
new file mode 100644
index 000000000000..b0ab1b22ad9d
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/driver-rk3288-gpiomem.patch
@@ -0,0 +1,395 @@
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+index e5b7ef1a5..f88c913ff 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+@@ -544,3 +544,6 @@
+ &wdt {
+ 	status = "okay";
+ };
++&gpiomem {
++    status = "okay";
++};
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index f3ca55496..14bbcb192 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -1418,6 +1418,12 @@
+ 		interrupts = <GIC_PPI 9 0xf04>;
+ 	};
+
++	gpiomem: rk3288-gpiomem@ff750000 {
++		compatible = "rockchip,rk3288-gpiomem";
++		reg = <0x0 0xff750000 0x0 0x1000>;
++		status = "disabled";
++	};
++
+ 	pinctrl: pinctrl {
+ 		compatible = "rockchip,rk3288-pinctrl";
+ 		rockchip,grf = <&grf>;
+
+diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
+index 3143db5..9c18b74 100644
+--- a/drivers/char/Kconfig
++++ b/drivers/char/Kconfig
+@@ -5,6 +5,7 @@
+ menu "Character devices"
+
+ source "drivers/tty/Kconfig"
++source "drivers/char/rockchip/Kconfig"
+
+ config DEVMEM
+ 	bool "/dev/mem virtual device support"
+diff --git a/drivers/char/Makefile b/drivers/char/Makefile
+index 264eb398f..9fd5f240b 100644
+--- a/drivers/char/Makefile
++++ b/drivers/char/Makefile
+@@ -43,6 +43,8 @@ obj-$(CONFIG_TCG_TPM)		+= tpm/
+
+ obj-$(CONFIG_PS3_FLASH)		+= ps3flash.o
+
++obj-$(CONFIG_ARCH_ROCKCHIP)    += rockchip/
++
+ obj-$(CONFIG_XILLYBUS_CLASS)	+= xillybus/
+ obj-$(CONFIG_POWERNV_OP_PANEL)	+= powernv-op-panel.o
+ obj-$(CONFIG_ADI)		+= adi.o
+diff --git a/drivers/char/rockchip/Kconfig b/drivers/char/rockchip/Kconfig
+new file mode 100644
+index 0000000..6e97486
+--- /dev/null
++++ b/drivers/char/rockchip/Kconfig
+@@ -0,0 +1,16 @@
++#
++# Broadcom char driver config
++#
++
++menuconfig RK_CHAR_DRIVERS
++	bool "Rockchip Char Drivers"
++	help
++	  Rockchip's char drivers
++
++config RK3288_DEVGPIOMEM
++	tristate "/dev/gpiomem rootless GPIO access via mmap() on the RK3288"
++	default y
++	help
++		Provides users with root-free access to the GPIO registers
++		on the 3288. Calling mmap(/dev/gpiomem) will map the GPIO
++		register page to the user's pointer.
+\ No newline at end of file
+diff --git a/drivers/char/rockchip/Makefile b/drivers/char/rockchip/Makefile
+new file mode 100644
+index 0000000..2287ec2
+--- /dev/null
++++ b/drivers/char/rockchip/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_RK3288_DEVGPIOMEM)+= rk3288-gpiomem.o
+\ No newline at end of file
+diff --git a/drivers/char/rockchip/rk3288-gpiomem.c b/drivers/char/rockchip/rk3288-gpiomem.c
+new file mode 100644
+index 0000000..984471c
+--- /dev/null
++++ b/drivers/char/rockchip/rk3288-gpiomem.c
+@@ -0,0 +1,303 @@
++/**
++ * GPIO memory device driver
++ *
++ * Creates a chardev /dev/gpiomem which will provide user access to
++ * the rk3288's GPIO registers when it is mmap()'d.
++ * No longer need root for user GPIO access, but without relaxing permissions
++ * on /dev/mem.
++ *
++ * Written by Luke Wren <luke@raspberrypi.org>
++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions, and the following disclaimer,
++ *    without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ *    to endorse or promote products derived from this software without
++ *    specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/mm.h>
++#include <linux/slab.h>
++#include <linux/cdev.h>
++#include <linux/pagemap.h>
++#include <linux/io.h>
++
++#define DEVICE_NAME "rk3288-gpiomem"
++#define DRIVER_NAME "gpiomem-rk3288"
++#define DEVICE_MINOR 0
++
++struct rk3288_gpiomem_instance {
++	unsigned long gpio_regs_phys;
++	struct device *dev;
++};
++
++static struct cdev rk3288_gpiomem_cdev;
++static dev_t rk3288_gpiomem_devid;
++static struct class *rk3288_gpiomem_class;
++static struct device *rk3288_gpiomem_dev;
++static struct rk3288_gpiomem_instance *inst;
++
++
++/****************************************************************************
++*
++*   GPIO mem chardev file ops
++*
++***************************************************************************/
++
++static int rk3288_gpiomem_open(struct inode *inode, struct file *file)
++{
++	int dev = iminor(inode);
++	int ret = 0;
++
++	if (dev != DEVICE_MINOR) {
++		dev_err(inst->dev, "Unknown minor device: %d", dev);
++		ret = -ENXIO;
++	}
++	return ret;
++}
++
++static int rk3288_gpiomem_release(struct inode *inode, struct file *file)
++{
++	int dev = iminor(inode);
++	int ret = 0;
++
++	if (dev != DEVICE_MINOR) {
++		dev_err(inst->dev, "Unknown minor device %d", dev);
++		ret = -ENXIO;
++	}
++	return ret;
++}
++
++static const struct vm_operations_struct rk3288_gpiomem_vm_ops = {
++#ifdef CONFIG_HAVE_IOREMAP_PROT
++	.access = generic_access_phys
++#endif
++};
++static int address_is_allowed(unsigned long pfn, unsigned long size)
++{
++    unsigned long address = pfn << PAGE_SHIFT;
++
++    dev_info(inst->dev, "address_is_allowed.pfn: 0x%08lx", address);
++
++    switch(address) {
++
++        case 0xff750000:
++        case 0xff760000:
++        case 0xff780000:
++        case 0xff790000:
++        case 0xff7a0000:
++        case 0xff7b0000:
++        case 0xff7c0000:
++        case 0xff7d0000:
++        case 0xff7e0000:
++        case 0xff7f0000:
++        case 0xff7f2000:
++        case 0xff770000:
++        case 0xff730000:
++        case 0xff680000:
++            dev_info(inst->dev, "address_is_allowed.return 1");
++            return 1;
++            break;
++        default :
++            dev_info(inst->dev, "address_is_allowed.return 0");
++	        return 0;
++    }
++}
++
++static int rk3288_gpiomem_mmap(struct file *file, struct vm_area_struct *vma)
++{
++
++    size_t size;
++
++	size = vma->vm_end - vma->vm_start;
++
++
++	if (!address_is_allowed(vma->vm_pgoff, size))
++		return -EPERM;
++
++	vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_pgoff,
++						 size,
++						 vma->vm_page_prot);
++
++	vma->vm_ops =  &rk3288_gpiomem_vm_ops;
++
++	/* Remap-pfn-range will mark the range VM_IO */
++	if (remap_pfn_range(vma,
++			    vma->vm_start,
++			    vma->vm_pgoff,
++			    size,
++			    vma->vm_page_prot)) {
++		return -EAGAIN;
++	}
++
++	return 0;
++}
++
++static const struct file_operations
++rk3288_gpiomem_fops = {
++	.owner = THIS_MODULE,
++	.open = rk3288_gpiomem_open,
++	.release = rk3288_gpiomem_release,
++	.mmap = rk3288_gpiomem_mmap,
++};
++
++static int rk3288_gpiomem_dev_uevent(const struct device *dev, struct kobj_uevent_env *env)
++{
++    add_uevent_var(env, "DEVMODE=%#o", 0666);
++    return 0;
++}
++
++ /****************************************************************************
++*
++*   Probe and remove functions
++*
++***************************************************************************/
++
++
++static int rk3288_gpiomem_probe(struct platform_device *pdev)
++{
++	int err;
++	void *ptr_err;
++	struct device *dev = &pdev->dev;
++	struct resource *ioresource;
++
++	/* Allocate buffers and instance data */
++
++	inst = kzalloc(sizeof(struct rk3288_gpiomem_instance), GFP_KERNEL);
++
++	if (!inst) {
++		err = -ENOMEM;
++		goto failed_inst_alloc;
++	}
++
++	inst->dev = dev;
++
++	ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (ioresource) {
++		inst->gpio_regs_phys = ioresource->start;
++	} else {
++		dev_err(inst->dev, "failed to get IO resource");
++		err = -ENOENT;
++		goto failed_get_resource;
++	}
++
++	/* Create character device entries */
++
++	err = alloc_chrdev_region(&rk3288_gpiomem_devid,
++				  DEVICE_MINOR, 1, DEVICE_NAME);
++	if (err != 0) {
++		dev_err(inst->dev, "unable to allocate device number");
++		goto failed_alloc_chrdev;
++	}
++	cdev_init(&rk3288_gpiomem_cdev, &rk3288_gpiomem_fops);
++	rk3288_gpiomem_cdev.owner = THIS_MODULE;
++	err = cdev_add(&rk3288_gpiomem_cdev, rk3288_gpiomem_devid, 1);
++	if (err != 0) {
++		dev_err(inst->dev, "unable to register device");
++		goto failed_cdev_add;
++	}
++
++	/* Create sysfs entries */
++
++	rk3288_gpiomem_class = class_create(DEVICE_NAME);
++	ptr_err = rk3288_gpiomem_class;
++	if (IS_ERR(ptr_err))
++		goto failed_class_create;
++	rk3288_gpiomem_class->dev_uevent = rk3288_gpiomem_dev_uevent;
++	rk3288_gpiomem_dev = device_create(rk3288_gpiomem_class, NULL,
++					rk3288_gpiomem_devid, NULL,
++					"gpiomem");
++	ptr_err = rk3288_gpiomem_dev;
++	if (IS_ERR(ptr_err))
++		goto failed_device_create;
++
++	dev_info(inst->dev, "Initialised: Registers at 0x%08lx",
++		inst->gpio_regs_phys);
++
++	return 0;
++
++failed_device_create:
++	class_destroy(rk3288_gpiomem_class);
++failed_class_create:
++	cdev_del(&rk3288_gpiomem_cdev);
++	err = PTR_ERR(ptr_err);
++failed_cdev_add:
++	unregister_chrdev_region(rk3288_gpiomem_devid, 1);
++failed_alloc_chrdev:
++failed_get_resource:
++	kfree(inst);
++failed_inst_alloc:
++	dev_err(inst->dev, "could not load rk3288_gpiomem");
++	return err;
++}
++
++static int rk3288_gpiomem_remove(struct platform_device *pdev)
++{
++	struct device *dev = inst->dev;
++
++	kfree(inst);
++	device_destroy(rk3288_gpiomem_class, rk3288_gpiomem_devid);
++	class_destroy(rk3288_gpiomem_class);
++	cdev_del(&rk3288_gpiomem_cdev);
++	unregister_chrdev_region(rk3288_gpiomem_devid, 1);
++
++	dev_info(dev, "GPIO mem driver removed - OK");
++	return 0;
++}
++
++ /****************************************************************************
++*
++*   Register the driver with device tree
++*
++***************************************************************************/
++
++static const struct of_device_id rk3288_gpiomem_of_match[] = {
++	{.compatible = "rockchip,rk3288-gpiomem",},
++	{ /* sentinel */ },
++};
++
++MODULE_DEVICE_TABLE(of, rk3288_gpiomem_of_match);
++
++static struct platform_driver rk3288_gpiomem_driver = {
++	.probe = rk3288_gpiomem_probe,
++	.remove = rk3288_gpiomem_remove,
++	.driver = {
++		   .name = DRIVER_NAME,
++		   .owner = THIS_MODULE,
++		   .of_match_table = rk3288_gpiomem_of_match,
++		   },
++};
++
++module_platform_driver(rk3288_gpiomem_driver);
++
++MODULE_ALIAS("platform:gpiomem-rk3288");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("gpiomem driver for accessing GPIO from userspace");
++MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
+\ No newline at end of file
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/driver-tinkerboard-alc4040-codec.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/driver-tinkerboard-alc4040-codec.patch
new file mode 100644
index 000000000000..f85f24fb7adc
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/driver-tinkerboard-alc4040-codec.patch
@@ -0,0 +1,19 @@
+diff --git a/sound/usb/card.c b/sound/usb/card.c
+index 2bfe4e80a..cea93aaf5 100644
+--- a/sound/usb/card.c
++++ b/sound/usb/card.c
+@@ -382,6 +382,14 @@ static void usb_audio_make_shortname(struct usb_device *dev,
+ 	}
+ 
+ 	strim(card->shortname);
++
++	/* Tinker Board ALC4040 CODEC	*/
++
++	if(USB_ID_VENDOR(chip->usb_id) == 0x0bda &&
++		USB_ID_PRODUCT(chip->usb_id) == 0x481a) {
++			strlcat(card->shortname, " OnBoard", sizeof(card->shortname));
++	}
++	
+ }
+ 
+ static void usb_audio_make_longname(struct usb_device *dev,
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/drm-rk322x-plane-overlay.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/drm-rk322x-plane-overlay.patch
new file mode 100644
index 000000000000..15319a894f38
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/drm-rk322x-plane-overlay.patch
@@ -0,0 +1,66 @@
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index 73d24c6bbf05..d4ac6e161ef2 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -614,6 +614,44 @@ static const struct vop_common rk3288_common = {
+ 	.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
+ };
+ 
++static const struct vop_win_phy rk3228_win0_data = {
++	.scl = &rk3288_win_full_scl,
++	.data_formats = formats_win_full,
++	.nformats = ARRAY_SIZE(formats_win_full),
++	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
++	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
++	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
++	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
++	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
++	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
++	.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
++	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
++	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
++	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
++	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
++	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
++	.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
++};
++
++static const struct vop_win_phy rk3228_win1_data = {
++	.scl = &rk3288_win_full_scl,
++	.data_formats = formats_win_lite,
++	.nformats = ARRAY_SIZE(formats_win_lite),
++	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
++	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
++	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
++	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
++	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
++	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
++	.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
++	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
++	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
++	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
++	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
++	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
++	.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
++};
++
+ /*
+  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
+  * special support to get alpha blending working.  For now, just use overlay
+@@ -864,10 +902,10 @@ static const struct vop_data rk3399_vop_lit = {
+ };
+ 
+ static const struct vop_win_data rk3228_vop_win_data[] = {
+-	{ .base = 0x00, .phy = &rk3288_win01_data,
++	{ .base = 0x00, .phy = &rk3228_win0_data,
+ 	  .type = DRM_PLANE_TYPE_PRIMARY },
+-	{ .base = 0x40, .phy = &rk3288_win01_data,
+-	  .type = DRM_PLANE_TYPE_CURSOR },
++	{ .base = 0x40, .phy = &rk3228_win1_data,
++	  .type = DRM_PLANE_TYPE_OVERLAY },
+ };
+ 
+ static const struct vop_data rk3228_vop = {
+-- 
+2.17.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/drm-rk322x-yuv-10bit-modes.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/drm-rk322x-yuv-10bit-modes.patch
new file mode 100644
index 000000000000..acd738f00d04
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/drm-rk322x-yuv-10bit-modes.patch
@@ -0,0 +1,44 @@
+From 2d42546642fa4299d88fa4ae414fa1ab205dad70 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 11 Sep 2021 17:38:48 +0000
+Subject: [PATCH] rk322x: enable YUV modes for win1, 10-bit for win0/win1
+
+---
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index 70930b410..3fd00b323 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -719,10 +719,11 @@ static const struct vop_common rk3288_common = {
+ 
+ static const struct vop_win_phy rk3228_win0_data = {
+ 	.scl = &rk3288_win_full_scl,
+-	.data_formats = formats_win_full,
+-	.nformats = ARRAY_SIZE(formats_win_full),
++	.data_formats = formats_win_full_10,
++	.nformats = ARRAY_SIZE(formats_win_full_10),
+ 	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
+ 	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
++	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
+ 	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
+ 	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
+ 	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
+@@ -738,10 +739,11 @@ static const struct vop_win_phy rk3228_win0_data = {
+ 
+ static const struct vop_win_phy rk3228_win1_data = {
+ 	.scl = &rk3288_win_full_scl,
+-	.data_formats = formats_win_lite,
+-	.nformats = ARRAY_SIZE(formats_win_lite),
++	.data_formats = formats_win_full_10,
++	.nformats = ARRAY_SIZE(formats_win_full_10),
+ 	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
+ 	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
++	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
+ 	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
+ 	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
+ 	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
+-- 
+2.25.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/drm-rockchip-hardware-cursor.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/drm-rockchip-hardware-cursor.patch
new file mode 100644
index 000000000000..863a70aaa42e
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/drm-rockchip-hardware-cursor.patch
@@ -0,0 +1,358 @@
+From ff9a0ab9d920d4a855b4be9912a57ac65e8906e2 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Fri, 10 Sep 2021 14:10:18 +0000
+Subject: [PATCH] drm rockchip hardware cursor
+
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 218 +++++++++++++++++++-
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   3 +
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  19 +-
+ 3 files changed, 238 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index 83a926c0a..b0832320e 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1160,6 +1160,207 @@ static void vop_plane_atomic_async_update(struct drm_plane *plane,
+ 	}
+ }
+ 
++static void vop_cursor_atomic_update(struct drm_plane *plane,
++		struct drm_atomic_state *state)
++{
++
++	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
++									   plane);
++	struct drm_crtc *crtc = new_state->crtc;
++	struct vop_win *vop_win = to_vop_win(plane);
++	const struct vop_win_data *win = vop_win->data;
++	struct vop *vop = to_vop(new_state->crtc);
++	struct drm_framebuffer *fb = new_state->fb;
++	unsigned int actual_w, actual_h;
++	unsigned int dsp_stx, dsp_sty;
++	uint32_t dsp_st;
++	struct drm_rect *src = &new_state->src;
++	struct drm_rect *dest = &new_state->dst;
++	struct drm_gem_object *obj;
++	struct rockchip_gem_object *rk_obj;
++	dma_addr_t dma_addr;
++	uint32_t val;
++	bool rb_swap;
++	int win_index = VOP_WIN_TO_INDEX(vop_win);
++	int format;
++
++	/*
++	 * can't update plane when vop is disabled.
++	 */
++	if (WARN_ON(!crtc))
++		return;
++
++	if (WARN_ON(!vop->is_enabled))
++		return;
++
++	if (!new_state->visible) {
++		vop_plane_atomic_disable(plane, state);
++		return;
++	}
++
++	obj = fb->obj[0];
++	rk_obj = to_rockchip_obj(obj);
++
++// 	actual_w = drm_rect_width(src) >> 16;
++// 	actual_h = drm_rect_height(src) >> 16;
++
++	dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
++	dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
++	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
++
++	dma_addr = rk_obj->dma_addr;
++
++	/*
++	 * For y-mirroring we need to move address
++	 * to the beginning of the last line.
++	 */
++// 	if (new_state->rotation & DRM_MODE_REFLECT_Y)
++// 		dma_addr += (actual_h - 1) * fb->pitches[0];
++
++	spin_lock(&vop->reg_lock);
++
++	if (!(vop->win_enabled & BIT(win_index))) {
++
++		format = vop_convert_format(fb->format->format);
++
++		VOP_WIN_SET(vop, win, format, format);
++
++// 		if (win->phy->scl)
++// 			scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
++// 					drm_rect_width(dest), drm_rect_height(dest),
++// 					fb->format);
++
++		rb_swap = has_rb_swapped(vop->data->version, fb->format->format);
++		VOP_WIN_SET(vop, win, rb_swap, rb_swap);
++
++		/*
++		* Blending win0 with the background color doesn't seem to work
++		* correctly. We only get the background color, no matter the contents
++		* of the win0 framebuffer.  However, blending pre-multiplied color
++		* with the default opaque black default background color is a no-op,
++		* so we can just disable blending to get the correct result.
++		*/
++		if (fb->format->has_alpha && win_index > 0) {
++			VOP_WIN_SET(vop, win, dst_alpha_ctl,
++				DST_FACTOR_M0(ALPHA_SRC_INVERSE));
++			val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
++				SRC_ALPHA_M0(ALPHA_STRAIGHT) |
++				SRC_BLEND_M0(ALPHA_PER_PIX) |
++				SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
++				SRC_FACTOR_M0(ALPHA_ONE);
++			VOP_WIN_SET(vop, win, src_alpha_ctl, val);
++
++			VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
++			VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
++			VOP_WIN_SET(vop, win, alpha_en, 1);
++		} else {
++			VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
++			VOP_WIN_SET(vop, win, alpha_en, 0);
++		}
++
++		// 32x32 = 0, 64x64 = 1, 96x96 = 2, 128x128 = 3
++		VOP_WIN_SET(vop, win, hwc_size, (new_state->crtc_w >> 5) - 1);
++
++		VOP_WIN_SET(vop, win, enable, 1);
++		vop->win_enabled |= BIT(win_index);
++
++	}
++
++	VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
++	VOP_WIN_SET(vop, win, dsp_st, dsp_st);
++
++	spin_unlock(&vop->reg_lock);
++
++}
++
++static void vop_cursor_atomic_async_update(struct drm_plane *plane,
++					  struct drm_atomic_state *state)
++{
++
++	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
++									   plane);
++	struct vop *vop = to_vop(plane->state->crtc);
++	struct drm_framebuffer *old_fb = plane->state->fb;
++
++	plane->state->crtc_x = new_state->crtc_x;
++	plane->state->crtc_y = new_state->crtc_y;
++	plane->state->crtc_h = new_state->crtc_h;
++	plane->state->crtc_w = new_state->crtc_w;
++	plane->state->src_x = new_state->src_x;
++	plane->state->src_y = new_state->src_y;
++	plane->state->src_h = new_state->src_h;
++	plane->state->src_w = new_state->src_w;
++	swap(plane->state->fb, new_state->fb);
++
++	if (vop->is_enabled) {
++		vop_cursor_atomic_update(plane, state);
++		spin_lock(&vop->reg_lock);
++		vop_cfg_done(vop);
++		spin_unlock(&vop->reg_lock);
++
++		/*
++		 * A scanout can still be occurring, so we can't drop the
++		 * reference to the old framebuffer. To solve this we get a
++		 * reference to old_fb and set a worker to release it later.
++		 * FIXME: if we perform 500 async_update calls before the
++		 * vblank, then we can have 500 different framebuffers waiting
++		 * to be released.
++		 */
++		if (old_fb && plane->state->fb != old_fb) {
++			drm_framebuffer_get(old_fb);
++			WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
++			drm_flip_work_queue(&vop->fb_unref_work, old_fb);
++			set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
++		}
++	}
++
++}
++
++static int vop_cursor_atomic_check(struct drm_plane *plane,
++			   struct drm_atomic_state *state)
++{
++	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
++										 plane);
++	struct drm_crtc *crtc = new_plane_state->crtc;
++	struct drm_crtc_state *crtc_state;
++	struct drm_framebuffer *fb = new_plane_state->fb;
++	int ret;
++
++	if (!crtc || WARN_ON(!fb))
++		return 0;
++
++	crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
++	if (WARN_ON(!crtc_state))
++		return -EINVAL;
++
++	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
++						  DRM_PLANE_NO_SCALING, DRM_PLANE_NO_SCALING,
++						  true, true);
++
++	if (ret)
++		return ret;
++
++	if (!new_plane_state->visible)
++		return 0;
++
++	ret = vop_convert_format(fb->format->format);
++	if (ret < 0)
++		return ret;
++
++	if (new_plane_state->crtc_w != new_plane_state->crtc_h)
++		return -EINVAL;
++
++	if (new_plane_state->crtc_w != 0 &&
++	    new_plane_state->crtc_w != 32 &&
++	    new_plane_state->crtc_w != 64 &&
++	    new_plane_state->crtc_w != 96 &&
++	    new_plane_state->crtc_w != 128)
++		return -EINVAL;
++
++	return 0;
++
++}
++
+ static const struct drm_plane_helper_funcs plane_helper_funcs = {
+ 	.atomic_check = vop_plane_atomic_check,
+ 	.atomic_update = vop_plane_atomic_update,
+@@ -1169,6 +1370,15 @@ static const struct drm_plane_helper_funcs plane_helper_funcs = {
+ 	.prepare_fb = drm_gem_plane_helper_prepare_fb,
+ };
+ 
++static const struct drm_plane_helper_funcs cursor_plane_helper_funcs = {
++	.atomic_check = vop_cursor_atomic_check,
++	.atomic_update = vop_cursor_atomic_update,
++	.atomic_disable = vop_plane_atomic_disable,
++	.atomic_async_check = vop_plane_atomic_async_check,
++	.atomic_async_update = vop_cursor_atomic_async_update,
++	.prepare_fb = drm_gem_plane_helper_prepare_fb,
++};
++
+ static const struct drm_plane_funcs vop_plane_funcs = {
+ 	.update_plane	= drm_atomic_helper_update_plane,
+ 	.disable_plane	= drm_atomic_helper_disable_plane,
+@@ -1956,6 +2166,7 @@ static int vop_create_crtc(struct vop *vop)
+ 	struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
+ 	struct drm_crtc *crtc = &vop->crtc;
+ 	struct device_node *port;
++	const struct drm_plane_helper_funcs *helper_funcs;
+ 	int ret;
+ 	int i;
+ 
+@@ -1976,7 +2187,12 @@ static int vop_create_crtc(struct vop *vop)
+ 		}
+ 
+ 		plane = &vop_win->base;
+-		drm_plane_helper_add(plane, &plane_helper_funcs);
++		helper_funcs = &plane_helper_funcs;
++
++		if ((plane->type == DRM_PLANE_TYPE_CURSOR) && (vop_data->feature & VOP_FEATURE_SPECIAL_CURSOR_PLANE))
++			helper_funcs = &cursor_plane_helper_funcs;
++
++		drm_plane_helper_add(plane, helper_funcs);
+ 		vop_plane_add_properties(plane, i, win_data, vop_data);
+ 		if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+ 			primary = plane;
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+index a997578e1..42dc299d9 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+@@ -190,6 +190,8 @@ struct vop_win_phy {
+ 	struct vop_reg alpha_mode;
+ 	struct vop_reg alpha_en;
+ 	struct vop_reg channel;
++
++	struct vop_reg hwc_size;
+ };
+ 
+ struct vop_win_yuv2yuv_data {
+@@ -225,6 +227,7 @@ struct vop_data {
+ 
+ #define VOP_FEATURE_OUTPUT_RGB10	BIT(0)
+ #define VOP_FEATURE_INTERNAL_RGB	BIT(1)
++#define VOP_FEATURE_SPECIAL_CURSOR_PLANE BIT(2)
+ 	u64 feature;
+ };
+ 
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index ab0a78097..70930b410 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -665,6 +665,19 @@ static const struct vop_win_phy rk3288_win23_data = {
+ 	.dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
+ };
+ 
++static const struct vop_win_phy rk3288_cursor_data = {
++	.data_formats = formats_win_lite,
++	.nformats = ARRAY_SIZE(formats_win_lite),
++	.enable = VOP_REG(RK3288_HWC_CTRL0, 0x1, 0),
++	.format = VOP_REG(RK3288_HWC_CTRL0, 0x7, 1),
++	.rb_swap = VOP_REG(RK3288_HWC_CTRL0, 0x1, 12),
++	.dsp_st = VOP_REG(RK3288_HWC_DSP_ST, 0x1fff1fff, 0),
++	.yrgb_mst = VOP_REG(RK3288_HWC_MST, 0xffffffff, 0),
++	.src_alpha_ctl = VOP_REG(RK3288_HWC_SRC_ALPHA_CTRL, 0xff, 0),
++	.dst_alpha_ctl = VOP_REG(RK3288_HWC_DST_ALPHA_CTRL, 0xff, 0),
++	.hwc_size = VOP_REG(RK3288_HWC_CTRL0, 0x3, 5),
++};
++
+ static const struct vop_modeset rk3288_modeset = {
+ 	.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
+ 	.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
+@@ -756,6 +769,8 @@ static const struct vop_win_data rk3288_vop_win_data[] = {
+ 	{ .base = 0x00, .phy = &rk3288_win23_data,
+ 	  .type = DRM_PLANE_TYPE_OVERLAY },
+ 	{ .base = 0x50, .phy = &rk3288_win23_data,
++	  .type = DRM_PLANE_TYPE_OVERLAY },
++	{ .base = 0x00, .phy = &rk3288_cursor_data,
+ 	  .type = DRM_PLANE_TYPE_CURSOR },
+ };
+ 
+@@ -1132,11 +1132,13 @@ static const struct vop_win_data rk3228_vop_win_data[] = {
+ 	  .type = DRM_PLANE_TYPE_PRIMARY },
+ 	{ .base = 0x40, .phy = &rk3228_win1_data,
+ 	  .type = DRM_PLANE_TYPE_OVERLAY },
++	{ .base = 0x00, .phy = &rk3288_cursor_data,
++	  .type = DRM_PLANE_TYPE_CURSOR },
+ };
+ 
+ static const struct vop_data rk3228_vop = {
+ 	.version = VOP_VERSION(3, 7),
+-	.feature = VOP_FEATURE_OUTPUT_RGB10,
++	.feature = VOP_FEATURE_OUTPUT_RGB10 | VOP_FEATURE_SPECIAL_CURSOR_PLANE,
+ 	.intr = &rk3366_vop_intr,
+ 	.common = &rk3288_common,
+ 	.modeset = &rk3288_modeset,
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index 04e30bdc8a0e..26a246a0fe1d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -809,7 +809,7 @@ static const struct vop_intr rk3288_vop_intr = {
+ 
+ static const struct vop_data rk3288_vop_big = {
+ 	.version = VOP_VERSION(3, 1),
+-	.feature = VOP_FEATURE_OUTPUT_RGB10,
++	.feature = VOP_FEATURE_OUTPUT_RGB10 | VOP_FEATURE_SPECIAL_CURSOR_PLANE,
+ 	.intr = &rk3288_vop_intr,
+ 	.common = &rk3288_common,
+ 	.modeset = &rk3288_modeset,
+@@ -827,7 +827,7 @@ static const struct vop_data rk3288_vop_big = {
+ 
+ static const struct vop_data rk3288_vop_lit = {
+ 	.version = VOP_VERSION(3, 1),
+-	.feature = VOP_FEATURE_OUTPUT_RGB10,
++	.feature = VOP_FEATURE_OUTPUT_RGB10 | VOP_FEATURE_SPECIAL_CURSOR_PLANE,
+ 	.max_output = { 2560, 1600 },
+ 	.intr = &rk3288_vop_intr,
+ 	.common = &rk3288_common,
+
+-- 
+2.25.1
+
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-fan.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-fan.patch
new file mode 100644
index 000000000000..b4b05a4abee1
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-fan.patch
@@ -0,0 +1,45 @@
+From c27e445527e949f3ef46d5326066196969c17d23 Mon Sep 17 00:00:00 2001
+From: Myy <myy@miouyouyou.fr>
+Date: Sun, 12 Mar 2017 19:43:15 +0000
+Subject: [PATCH 06/28] ARM: dts: rockchip: add the MiQi board's fan definition
+
+The MiQi board is sold with an enclosure in which a fan is connected
+to the second LED output, and configured by default in "heartbeat"
+mode so that it rotates slowly and increases when the CPU load
+increases, ensuring appropriate cooling by default. This LED output
+is called "Fan" in the original kernel and connected to GPIO18
+(gpiochip 0, pin 18). Here we called it "miqi:green:fan" to stay
+consistent with the kernel's naming conventions.
+
+It's worth noting that without this patch the fan doesn't work at
+all, risking to make the board overheat.
+
+Fixes: 162718c (v4.7)
+Cc: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Willy Tarreau <w@1wt.eu>
+
+Signed-off-by: Myy <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+index a1c3cdaa..0e383595 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
++++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+@@ -67,6 +67,13 @@
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
++		fan {
++			gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
++			label = "miqi:green:fan";
++			linux,default-trigger = "heartbeat";
++		};
++
++
+ 		work_led: led-0 {
+ 			gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
+ 			label = "miqi:green:user";
+-- 
+2.11.0
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-hevc-rga.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-hevc-rga.patch
new file mode 100644
index 000000000000..f1d54b97c3c3
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-hevc-rga.patch
@@ -0,0 +1,42 @@
+From 2fdd826a704ef70df42d92b38ad88ef869c3729b Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 18 Sep 2021 12:32:05 +0000
+Subject: [PATCH 2/2] rockchip: enable hevc, hevc_mmu and rga nodes for miqi
+
+---
+ arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+index 94bc76099..68eb766f0 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
++++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+@@ -162,6 +162,14 @@ &hdmi {
+ 	status = "okay";
+ };
+ 
++&hevc {
++	status = "okay";
++};
++
++&hevc_mmu {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	clock-frequency = <400000>;
+ 	status = "okay";
+@@ -405,6 +413,10 @@ host_vbus_drv: host-vbus-drv {
+ 	};
+ };
+ 
++&rga {
++	status = "okay";
++};
++
+ &saradc {
+ 	vref-supply = <&vcc_18>;
+ 	status = "okay";
+-- 
+2.30.2
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-mali-gpu.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-mali-gpu.patch
new file mode 100644
index 000000000000..6a07886e7326
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-mali-gpu.patch
@@ -0,0 +1,35 @@
+From 604ea7fc311af2b3a41e7fe3b4fbde0ee03dfb9c Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Thu, 19 Oct 2017 21:09:50 +0200
+Subject: [PATCH 04/28] dts: rk3288: miqi: Enabling the Mali GPU node
+
+Why is the MiQi the only one left without a working mali GPU node ?
+
+Seriously, is there a rk3288 chipset WITHOUT a mali GPU ? Couldn't
+they enable it once in the DTSI, instead of defining it as "disabled"
+and enabling it in every DTS file ?
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+index 4d923aa6..3cd60674 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
++++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+@@ -149,6 +149,11 @@
+ 	status = "ok";
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
+ &hdmi {
+ 	ddc-i2c-bus = <&i2c5>;
+ 	status = "okay";
+-- 
+2.11.0
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-regulator-fix.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-regulator-fix.patch
new file mode 100644
index 000000000000..01c66a95fa32
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-miqi-regulator-fix.patch
@@ -0,0 +1,45 @@
+From 89e5763110ca77d68a4be00cd97a638adc2401d5 Mon Sep 17 00:00:00 2001
+From: Willy Tarreau <w@1wt.eu>
+Date: Tue, 2 Aug 2016 08:31:00 +0200
+Subject: [PATCH 05/28] ARM: dts: rockchip: fix the regulator's voltage range
+ on MiQi board
+
+The board declared too narrow a voltage range for the CPU and GPU
+regulators, preventing it from using the full CPU frequency range.
+The regulators support 712500 to 1500000 microvolts.
+
+Signed-off-by: Willy Tarreau <w@1wt.eu>
+(cherry picked from commit 95330e63a9295a2632cee8cce5db80677f01857a)
+---
+ arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+index 3cd60674..a1c3cdaa 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
++++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+@@ -168,8 +168,8 @@
+ 		fcs,suspend-voltage-selector = <1>;
+ 		reg = <0x40>;
+ 		regulator-name = "vdd_cpu";
+-		regulator-min-microvolt = <850000>;
+-		regulator-max-microvolt = <1350000>;
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
+ 		regulator-always-on;
+ 		regulator-boot-on;
+ 		regulator-enable-ramp-delay = <300>;
+@@ -182,8 +182,8 @@
+ 		fcs,suspend-voltage-selector = <1>;
+ 		reg = <0x41>;
+ 		regulator-name = "vdd_gpu";
+-		regulator-min-microvolt = <850000>;
+-		regulator-max-microvolt = <1350000>;
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
+ 		regulator-always-on;
+ 		vin-supply = <&vcc_sys>;
+ 	};
+-- 
+2.11.0
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk322x-iep-node.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk322x-iep-node.patch
new file mode 100644
index 000000000000..994f01e8ea29
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk322x-iep-node.patch
@@ -0,0 +1,34 @@
+From adecdd57a0155e0d96af2c84cc4fa52309fbb535 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Thu, 9 Sep 2021 19:14:08 +0000
+Subject: [PATCH] add iep node for rk322x
+
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 0ae753c1d..271e7835f 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -834,6 +834,17 @@ rga: rga@20060000 {
+ 		reset-names = "core", "axi", "ahb";
+ 	};
+ 
++	iep: iep@20070000 {
++		compatible = "rockchip,rk3228-iep";
++		reg = <0x20070000 0x800>;
++		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++		clock-names = "axi", "ahb";
++		iommus = <&iep_mmu>;
++		power-domains = <&power RK3228_PD_VIO>;
++		status = "disabled";
++	};
++
+ 	iep_mmu: iommu@20070800 {
+ 		compatible = "rockchip,iommu";
+ 		reg = <0x20070800 0x100>;
+-- 
+2.25.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk322x-pinctrl-nand.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk322x-pinctrl-nand.patch
new file mode 100644
index 000000000000..6c6ab33ff04e
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk322x-pinctrl-nand.patch
@@ -0,0 +1,93 @@
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 48e6e8d44..1dfd27f9f 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -712,6 +712,22 @@ emmc: mmc@30020000 {
+ 		status = "disabled";
+ 	};
+ 
++	nfc: nand-controller@30030000 {
++                compatible = "rockchip,rk3228-nfc", "rockchip,rk2928-nfc";
++                reg = <0x30030000 0x4000>;
++                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++                clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
++                clock-names = "nfc", "ahb";
++                assigned-clocks = <&cru SCLK_NANDC>;
++                assigned-clock-rates = <150000000>;
++
++                pinctrl-names = "default";
++                pinctrl-0 = <&flash_cs0 &flash_rdy &flash_ale &flash_cle
++                        &flash_wrn &flash_rdn &flash_bus8>;
++                status = "disabled";
++
++        };
++
+ 	usb_otg: usb@30040000 {
+ 		compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
+ 			     "snps,dwc2";
+@@ -950,6 +966,65 @@ emmc_bus8: emmc-bus8 {
+ 			};
+ 		};
+ 
++		flash {
++
++                        flash_cs0: flash-cs0 {
++                                rockchip,pins = <2 RK_PA6 1 &pcfg_pull_up>;
++                        };
++
++                        flash_cs1: flash-cs1 {
++                                rockchip,pins = <0 RK_PC7 1 &pcfg_pull_up>;
++                        };
++
++                        flash_cs2: flash-cs2 {
++                                rockchip,pins = <1 RK_PC6 1 &pcfg_pull_up>;
++                        };
++
++                        flash_cs3: flash-cs3 {
++                                rockchip,pins = <1 RK_PC7 1 &pcfg_pull_up>;
++                        };
++
++                        flash_rdy: flash-rdy {
++                                rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>;
++                        };
++
++                        flash_ale: flash-ale {
++                                rockchip,pins = <2 RK_PA0 1 &pcfg_pull_down>;
++                        };
++
++                        flash_cle: flash-cle {
++                                rockchip,pins = <2 RK_PA1 1 &pcfg_pull_down>;
++                        };
++
++                        flash_wrn: flash-wrn {
++	                        rockchip,pins = <2 RK_PA2 1 &pcfg_pull_up>;
++                        };
++
++                        flash_rdn: flash-rdn {
++                                rockchip,pins = <2 RK_PA3 1 &pcfg_pull_up>;
++                        };
++
++			flash_bus8: flash-bus8 {
++                                rockchip,pins = <1 RK_PD0 1 &pcfg_pull_up>,
++                                                <1 RK_PD1 1 &pcfg_pull_up>,
++                                                <1 RK_PD2 1 &pcfg_pull_up>,
++                                                <1 RK_PD3 1 &pcfg_pull_up>,
++                                                <1 RK_PD4 1 &pcfg_pull_up>,
++                                                <1 RK_PD5 1 &pcfg_pull_up>,
++                                                <1 RK_PD6 1 &pcfg_pull_up>,
++                                                <1 RK_PD7 1 &pcfg_pull_up>;
++                        };
++
++                        flash_dqs: flash-dqs {
++                                rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up>;
++                        };
++
++                        flash_wp: flash-wp {
++                                rockchip,pins = <2 RK_PA5 1 &pcfg_pull_down>;
++                        };
++
++                };
++
+ 		gmac {
+ 			rgmii_pins: rgmii-pins {
+ 				rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-disable-serial-dma.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-disable-serial-dma.patch
new file mode 100644
index 000000000000..b54cf9d59060
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-disable-serial-dma.patch
@@ -0,0 +1,40 @@
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index 0cd88774d..07681f1f0 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -420,8 +420,6 @@
+ 		reg-io-width = <4>;
+ 		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ 		clock-names = "baudclk", "apb_pclk";
+-		dmas = <&dmac_peri 1>, <&dmac_peri 2>;
+-		dma-names = "tx", "rx";
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&uart0_xfer>;
+ 		status = "disabled";
+@@ -435,8 +433,6 @@
+ 		reg-io-width = <4>;
+ 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ 		clock-names = "baudclk", "apb_pclk";
+-		dmas = <&dmac_peri 3>, <&dmac_peri 4>;
+-		dma-names = "tx", "rx";
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&uart1_xfer>;
+ 		status = "disabled";
+@@ -463,8 +459,6 @@
+ 		reg-io-width = <4>;
+ 		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ 		clock-names = "baudclk", "apb_pclk";
+-		dmas = <&dmac_peri 7>, <&dmac_peri 8>;
+-		dma-names = "tx", "rx";
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&uart3_xfer>;
+ 		status = "disabled";
+@@ -478,8 +472,6 @@
+ 		reg-io-width = <4>;
+ 		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ 		clock-names = "baudclk", "apb_pclk";
+-		dmas = <&dmac_peri 9>, <&dmac_peri 10>;
+-		dma-names = "tx", "rx";
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&uart4_xfer>;
+ 		status = "disabled";
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-fix-mmc-aliases.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-fix-mmc-aliases.patch
new file mode 100644
index 000000000000..dede52866679
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-fix-mmc-aliases.patch
@@ -0,0 +1,20 @@
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index 511ca864c1b2..d7ecb6b4de40 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -25,10 +25,10 @@ aliases {
+ 		i2c3 = &i2c3;
+ 		i2c4 = &i2c4;
+ 		i2c5 = &i2c5;
+-		mshc0 = &emmc;
+-		mshc1 = &sdmmc;
+-		mshc2 = &sdio0;
+-		mshc3 = &sdio1;
++		mmc0 = &sdmmc;
++		mmc1 = &sdio0;
++		mmc2 = &emmc;
++		mmc3 = &sdio1;
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
+ 		serial2 = &uart2;
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch
new file mode 100644
index 000000000000..6a91d9226c56
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch
@@ -0,0 +1,42 @@
+From 73258d32daf3a661281bb5c77c5e2e06c7ff714e Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Fri, 3 Jul 2020 02:02:18 +0200
+Subject: [PATCH] arm: dtsi: rk3288: add GPU 500 Mhz OPP again
+
+Undoing the very bizarre mainline kernel patch,
+75481833c6dbab4c29d15452f6b4337c16f5407b
+which main purpose is to sync some 3.14 kernels hacks to
+mainline kernels, for reasons that only matter for a few Chromebooks,
+and shove it down the throat of every RK3288 user.
+
+If you need to avoid the GPU going to 500 Mhz on Chromebooks,
+remove the OPP entry inside the DTS that actually matters to RK3288
+Chromebooks.
+
+Meanwhile, the 600 Mhz operating point can prove to be unstable on
+some RK3288 boards, while 500 Mhz works fine.
+https://forum.armbian.com/topic/13515-panfrost-on-rk3288-and-gpu-on-600mhz-problems/
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rockchip/rk3288.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index a66412547..ef7457f79 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -1312,6 +1312,10 @@ opp-400000000 {
+ 			opp-hz = /bits/ 64 <400000000>;
+ 			opp-microvolt = <1100000>;
+ 		};
++		opp-500000000 {
++			opp-hz = /bits/ 64 <500000000>;
++			opp-microvolt = <1200000>;
++		};
+ 		opp-600000000 {
+ 			opp-hz = /bits/ 64 <600000000>;
+ 			opp-microvolt = <1250000>;
+-- 
+2.27.0
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-pinctrl-spi2.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-pinctrl-spi2.patch
new file mode 100644
index 000000000000..f34e8fa8e417
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-pinctrl-spi2.patch
@@ -0,0 +1,31 @@
+From 062488e4b8fd552c01e1104b3bc91a6f7ffe6c41 Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Thu, 19 Oct 2017 21:24:47 +0200
+Subject: [PATCH 10/28] RK3288: DTSI: rk3288.dtsi: Add missing SPI2 pinctrl
+
+The spi2_cs1 pin reference is missing in the spi2 first pin control
+definition.
+
+This patch is taken from the patches provided by the ARMbian team.
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rockchip/rk3288.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index 5b789528..9ed532cc 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -334,7 +334,7 @@
+ 		dma-names = "tx", "rx";
+ 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
++		pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0 &spi2_cs1>;
+ 		reg = <0x0 0xff130000 0x0 0x1000>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-- 
+2.11.0
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch
new file mode 100644
index 000000000000..c9ae49db37cf
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch
@@ -0,0 +1,32 @@
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index bc3601a..37ae378 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -467,13 +467,6 @@
+ 	};
+ 
+ 	thermal-zones {
+-		reserve_thermal: reserve-thermal {
+-			polling-delay-passive = <1000>; /* milliseconds */
+-			polling-delay = <5000>; /* milliseconds */
+-
+-			thermal-sensors = <&tsadc 0>;
+-		};
+-
+ 		cpu_thermal: cpu-thermal {
+ 			polling-delay-passive = <100>; /* milliseconds */
+ 			polling-delay = <5000>; /* milliseconds */
+@@ -539,6 +532,13 @@
+ 				};
+ 			};
+ 		};
++
++		reserve_thermal: reserve-thermal {
++			polling-delay-passive = <1000>; /* milliseconds */
++			polling-delay = <5000>; /* milliseconds */
++
++			thermal-sensors = <&tsadc 0>;
++		};
+ 	};
+ 
+ 	tsadc: tsadc@ff280000 {
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch
new file mode 100644
index 000000000000..e56921406c2d
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch
@@ -0,0 +1,34 @@
+From 87313f95f809fc34f499c1ceff1b95cd4efa0f3f Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 22 Mar 2022 22:02:46 +0000
+Subject: [PATCH] rockchip: add tinkerboard bluetooth
+
+---
+ arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+index ff2c6de3216..23acfdecee7 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+@@ -510,6 +510,17 @@ &tsadc {
+ 
+ &uart0 {
+ 	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
++	uart-has-rtscts;
++
++	bluetooth {
++		compatible = "realtek,rtl8723bs-bt";
++		enable-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
++		device-wake-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
++		host-wake-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
++	};
++
+ };
+ 
+ &uart1 {
+-- 
+2.30.2
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-bt-uart-pins.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-bt-uart-pins.patch
new file mode 100644
index 000000000000..50da0ecae05d
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-bt-uart-pins.patch
@@ -0,0 +1,62 @@
+From 2c2e60256f2cbb2fce50a6317f85b1500efd1a6c Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Mon, 5 Nov 2018 22:03:26 +0100
+Subject: [PATCH] ARM: DTS: rk3288-tinker: Setup the Bluetooth UART pins
+
+The most essential being the RTS pin, which is clearly needed to
+upload the initial configuration into the Realtek Bluetooth
+chip, and make the Bluetooth chip work.
+
+Now, the Bluetooth chip also needs 3 other GPIOS to be enabled.
+I'll see how I do that through the DTS file in a near future.
+
+The 3 GPIOS being :
+Bluetooth Reset : <&gpio4 29 GPIO_ACTIVE_HIGH>
+Bluetooth Wake  : <&gpio4 26 GPIO_ACTIVE_HIGH>
+Bluetooth Wake_Host_IRQ : <&gpio4 31 GPIO_ACTIVE_HIGH>
+
+These are currently setup manually, through scripts. But it seems that
+GPIO handling through /sys entries might not be possible in the long
+term, the replacement being libgpio.
+Anyway, if you're interesting in enabling the Bluetooth GPIO by hand,
+here are the commands :
+
+cd /sys/class/gpio &&
+echo 146 > export &&
+echo 149 > export &&
+echo 151 > export &&
+echo high > gpio146/direction &&
+echo high > gpio149/direction &&
+echo high > gpio151/direction
+
+Resetting the chip is done like this :
+
+echo "Resetting the Bluetooth chip"
+cd /sys/class/gpio/gpio149 &&
+echo 0 > value &&
+sleep 1 &&
+echo 1 > value &&
+sleep 1
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rockchip/rk3288-tinker.dts | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
+index d4df13bed..b92e59c1e 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
++++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
+@@ -73,3 +73,9 @@
+ 	status = "okay";
+ 	supports-sdio;
+ };
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
++};
++
+-- 
+2.16.4
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-hevc-rga.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-hevc-rga.patch
new file mode 100644
index 000000000000..a5175c9e5b61
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-hevc-rga.patch
@@ -0,0 +1,43 @@
+From 0bcc81848ec1fb34fee9d3c7eb1550495cc8efc9 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 18 Sep 2021 12:31:19 +0000
+Subject: [PATCH 1/2] rockchip: enable hevc, hevc_mmu and rga nodes for
+ tinkerboard (both)
+
+---
+ arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+index aa36aedf9..ff2c6de32 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+@@ -150,6 +150,14 @@ &hdmi {
+ 	status = "okay";
+ };
+ 
++&hevc {
++	status = "okay";
++};
++
++&hevc_mmu {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	clock-frequency = <400000>;
+ 	status = "okay";
+@@ -449,6 +457,10 @@ &pwm0 {
+ 	status = "okay";
+ };
+ 
++&rga {
++	status = "okay";
++};
++
+ &saradc {
+ 	vref-supply = <&vcc18_ldo1>;
+ 	status = "okay";
+-- 
+2.30.2
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-sdio-wifi.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-sdio-wifi.patch
new file mode 100644
index 000000000000..85974972be0a
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-sdio-wifi.patch
@@ -0,0 +1,98 @@
+From d5d5c53173c484a13cda62a537cbf75a5df4b0e4 Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Mon, 5 Nov 2018 21:58:56 +0100
+Subject: [PATCH] ARM: DTS: rk3288-tinker: Enabling SDIO and Wifi
+
+Adding the appropriate nodes in order to exploit the WiFi capabilities
+of the board.
+Since these capabilities are provided through SDIO, and the SDIO
+nodes were not defined, these were added too.
+
+These seems to depend on each other so they are added in one big
+patch.
+
+Split if necessary.
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rockchip/rk3288-tinker.dts | 62 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 62 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
+index 1e43527aa..d4df13bed 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
++++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
+@@ -6,8 +6,70 @@
+ /dts-v1/;
+ 
+ #include "rk3288-tinker.dtsi"
++#include <dt-bindings/clock/rockchip,rk808.h>
+ 
+ / {
+ 	model = "Rockchip RK3288 Asus Tinker Board";
+ 	compatible = "asus,rk3288-tinker", "rockchip,rk3288";
++
++	/* This is essential to get SDIO devices working.
++	   The Wifi depends on SDIO ! */
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk808 RK808_CLKOUT1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
++
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
++		reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>;
++	};
++
++	wireless-wlan {
++		compatible = "wlan-platdata";
++		rockchip,grf = <&grf>;
++		sdio_vref = <1800>;
++		status = "okay";
++		wifi_chip_type = "8723bs";
++		WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
++	};
++};
++
++&io_domains {
++	wifi-supply = <&vcc_18>;
++};
++
++&pinctrl {
++	sdio-pwrseq {
++		wifi_enable_h: wifienable-h {
++			rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		chip_enable_h: chip-enable-h {
++			rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&sdio0 {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	clock-frequency = <50000000>;
++	clock-freq-min-max = <200000 50000000>;
++	disable-wp;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	num-slots = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
++	sd-uhs-sdr104;
++	status = "okay";
++	supports-sdio;
+ };
+-- 
+2.16.4
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-sdmmc-properties.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-sdmmc-properties.patch
new file mode 100644
index 000000000000..5486d60188c1
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-sdmmc-properties.patch
@@ -0,0 +1,33 @@
+From 487db7cefc9861fdaf30579c378a98f0360690ae Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Mon, 5 Nov 2018 20:27:14 +0100
+Subject: [PATCH] ARM: DTSI: rk3288-tinker: Defining SDMMC properties
+
+I never knew if these properties were required to fix the dreaded
+reboot issue...
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+index dd1090728..8edd6f681 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+@@ -436,7 +436,12 @@
+ 	disable-wp;			/* wp not hooked up */
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
++	sd-uhs-sdr12;
++	sd-uhs-sdr25;
++	sd-uhs-sdr50;
++	sd-uhs-sdr104;
+ 	status = "okay";
++	supports-sd;
+ 	vmmc-supply = <&vcc33_sd>;
+ 	vqmmc-supply = <&vccio_sd>;
+ };
+-- 
+2.16.4
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-spi-interface.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-spi-interface.patch
new file mode 100644
index 000000000000..db2b09b1595c
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-tinkerboard-spi-interface.patch
@@ -0,0 +1,50 @@
+From b24b8f83e150811ad54ee2a4843e44cd1421fafa Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Mon, 5 Nov 2018 22:15:14 +0100
+Subject: [PATCH] ARM: DTS: rk3288-tinker: Defining the SPI interface
+
+Taken from, and tested by @TonyMac32 .
+
+Well, the original one was tested by him but I had to adapt the
+registers definitions to the new 64-bits LPAE-compliant syntax.
+
+Therefore that *might* break, along with a few other patches.
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rockchip/rk3288-tinker.dts | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
+index 96d05fc6b..17bfea298 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
++++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
+@@ -99,6 +99,25 @@
+ 	supports-sdio;
+ };
+ 
++&spi2 {
++	max-freq = <50000000>;
++	status = "okay";
++
++	spidev@0 {
++		compatible = "rockchip,spi_tinker";
++		reg = <0x0 0>;
++		spi-max-frequency = <50000000>;
++		spi-cpha = <1>;
++	};
++
++	spidev@1 {
++		compatible = "rockchip,spi_tinker";
++		reg = <0x1>;
++		spi-max-frequency = <50000000>;
++		spi-cpha = <1>;
++	};
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
+-- 
+2.16.4
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-veyron-flag-cache-flush.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-veyron-flag-cache-flush.patch
new file mode 100644
index 000000000000..89cb36c0a24c
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/dts-veyron-flag-cache-flush.patch
@@ -0,0 +1,32 @@
+From 9177b30ab083dbda2bede3b3d61ef71ad4b1ffe0 Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Thu, 1 Nov 2018 21:31:26 +0100
+Subject: [PATCH 2/2] arm: dts: veyron: Added a flag to disable cache flush
+ during reset
+
+Flushing the MMC cache of ASUS Chromebooks during initialization or
+"recovery" generates 10 minutes hangup, according to @SolidHal.
+
+This is an adaptation of @SolidHal, in order to pinpoint the fix to
+Veyron Chromebooks, and avoiding issues other RK3288 boards.
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi
+index 2075120cf..fa4951fd7 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi
+@@ -123,6 +123,7 @@
+ 	mmc-hs200-1_8v;
+ 	mmc-pwrseq = <&emmc_pwrseq>;
+ 	non-removable;
++	no-recovery-cache-flush;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ };
+-- 
+2.16.4
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/general-add-overlay-compilation-support.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-add-overlay-compilation-support.patch
new file mode 100644
index 000000000000..3a0c05e60cab
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-add-overlay-compilation-support.patch
@@ -0,0 +1,64 @@
+From a8f9689004d59f0a454ce8cb06bf1556971c1bad Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 20 Jul 2024 13:58:49 +0200
+Subject: [PATCH] compile .scr and install overlays in right path
+
+---
+ scripts/Makefile.dtbinst | 13 ++++++++++++-
+ scripts/Makefile.lib     |  8 +++++++-
+ 2 files changed, 19 insertions(+), 2 deletions(-)
+
+diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
+index 9d920419a62c..9144a1b7c909 100644
+--- a/scripts/Makefile.dtbinst
++++ b/scripts/Makefile.dtbinst
+@@ -33,7 +33,18 @@ endef
+ 
+ $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d))))
+ 
+-dtbs := $(notdir $(dtbs))
++# Very convoluted way to flatten all the device tree
++# directories, but keep the "/overlay/" directory
++
++# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip)
++topmost_dir = $(firstword $(subst /, ,$(dtbs)))
++# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir"
++dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs)))
++# collect the non-overlay dtbs
++dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs))
++# compose the dtbs variable flattening all the non-overlays entries
++# and appending the overlays entries
++dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays)
+ 
+ endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL
+ 
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 9f06f6aaf7fc..67a7b73b6688 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -394,15 +394,21 @@ quiet_cmd_wrap_S_dtb = WRAP    $@
+ 		echo '.balign STRUCT_ALIGNMENT';					\
+ 	} > $@
+ 
++quiet_cmd_scr = MKIMAGE $@
++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
++
+ $(obj)/%.dtb.S: $(obj)/%.dtb FORCE
+ 	$(call if_changed,wrap_S_dtb)
+ 
+ $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE
+ 	$(call if_changed,wrap_S_dtb)
+ 
++$(obj)/%.scr: $(src)/%.scr-cmd FORCE
++	$(call if_changed,scr)
++
+ quiet_cmd_dtc = DTC     $@
+ cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+-	$(DTC) -o $@ -b 0 \
++	$(DTC) -@ -o $@ -b 0 \
+ 		$(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \
+ 		-d $(depfile).dtc.tmp $(dtc-tmp) ; \
+ 	cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/general-add-overlay-configfs.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-add-overlay-configfs.patch
new file mode 100644
index 000000000000..0aa88542fc4a
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-add-overlay-configfs.patch
@@ -0,0 +1,358 @@
+--- /dev/null
++++ b/Documentation/devicetree/configfs-overlays.txt
+@@ -0,0 +1,31 @@
++Howto use the configfs overlay interface.
++
++A device-tree configfs entry is created in /config/device-tree/overlays
++and and it is manipulated using standard file system I/O.
++Note that this is a debug level interface, for use by developers and
++not necessarily something accessed by normal users due to the
++security implications of having direct access to the kernel's device tree.
++
++* To create an overlay you mkdir the directory:
++
++	# mkdir /config/device-tree/overlays/foo
++
++* Either you echo the overlay firmware file to the path property file.
++
++	# echo foo.dtbo >/config/device-tree/overlays/foo/path
++
++* Or you cat the contents of the overlay to the dtbo file
++
++	# cat foo.dtbo >/config/device-tree/overlays/foo/dtbo
++
++The overlay file will be applied, and devices will be created/destroyed
++as required.
++
++To remove it simply rmdir the directory.
++
++	# rmdir /config/device-tree/overlays/foo
++
++The rationalle of the dual interface (firmware & direct copy) is that each is
++better suited to different use patterns. The firmware interface is what's
++intended to be used by hardware managers in the kernel, while the copy interface
++make sense for developers (since it avoids problems with namespaces).
+diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
+index 37c2ccbefecdc..d3fc81a40c0e7 100644
+--- a/drivers/of/Kconfig
++++ b/drivers/of/Kconfig
+@@ -103,4 +103,11 @@ config OF_OVERLAY
+ config OF_NUMA
+ 	bool
+ 
++config OF_CONFIGFS
++	bool "Device Tree Overlay ConfigFS interface"
++	select CONFIGFS_FS
++	select OF_OVERLAY
++	help
++	  Enable a simple user-space driven DT overlay interface.
++
+ endif # OF
+diff --git a/drivers/of/Makefile b/drivers/of/Makefile
+index 663a4af0cccd5..b00a95adf5199 100644
+--- a/drivers/of/Makefile
++++ b/drivers/of/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-y = base.o device.o platform.o property.o
+ obj-$(CONFIG_OF_KOBJ) += kobj.o
++obj-$(CONFIG_OF_CONFIGFS) += configfs.o
+ obj-$(CONFIG_OF_DYNAMIC) += dynamic.o
+ obj-$(CONFIG_OF_FLATTREE) += fdt.o
+ obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o
+diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c
+new file mode 100644
+index 000000000..5dd509e8f
+--- /dev/null
++++ b/drivers/of/configfs.c
+@@ -0,0 +1,290 @@
++/*
++ * Configfs entries for device-tree
++ *
++ * Copyright (C) 2013 - Pantelis Antoniou <panto@antoniou-consulting.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ */
++#include <linux/ctype.h>
++#include <linux/cpu.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_fdt.h>
++#include <linux/spinlock.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/configfs.h>
++#include <linux/types.h>
++#include <linux/stat.h>
++#include <linux/limits.h>
++#include <linux/file.h>
++#include <linux/vmalloc.h>
++#include <linux/firmware.h>
++#include <linux/sizes.h>
++
++#include "of_private.h"
++
++struct cfs_overlay_item {
++	struct config_item	item;
++
++	char			path[PATH_MAX];
++
++	const struct firmware	*fw;
++	struct device_node	*overlay;
++	int			ov_id;
++
++	void			*dtbo;
++	int			dtbo_size;
++};
++
++static int create_overlay(struct cfs_overlay_item *overlay, void *blob, u32 blob_size)
++{
++	int err;
++
++	err = of_overlay_fdt_apply(blob, blob_size, &overlay->ov_id, NULL);
++	if (err < 0) {
++		pr_err("%s: Failed to create overlay (err=%d)\n",
++				__func__, err);
++		goto out_err;
++	}
++
++out_err:
++	return err;
++}
++
++static inline struct cfs_overlay_item *to_cfs_overlay_item(
++		struct config_item *item)
++{
++	return item ? container_of(item, struct cfs_overlay_item, item) : NULL;
++}
++
++static ssize_t cfs_overlay_item_path_show(struct config_item *item,
++		char *page)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	return sprintf(page, "%s\n", overlay->path);
++}
++
++static ssize_t cfs_overlay_item_path_store(struct config_item *item,
++		const char *page, size_t count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	const char *p = page;
++	char *s;
++	int err;
++
++	/* if it's set do not allow changes */
++	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
++		return -EPERM;
++
++	/* copy to path buffer (and make sure it's always zero terminated */
++	count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p);
++	overlay->path[sizeof(overlay->path) - 1] = '\0';
++
++	/* strip trailing newlines */
++	s = overlay->path + strlen(overlay->path);
++	while (s > overlay->path && *--s == '\n')
++		*s = '\0';
++
++	pr_debug("%s: path is '%s'\n", __func__, overlay->path);
++
++	err = request_firmware(&overlay->fw, overlay->path, NULL);
++	if (err != 0)
++		goto out_err;
++
++	err = create_overlay(overlay, (void *)overlay->fw->data, overlay->fw->size);
++	if (err != 0)
++		goto out_err;
++
++	return count;
++
++out_err:
++
++	release_firmware(overlay->fw);
++	overlay->fw = NULL;
++
++	overlay->path[0] = '\0';
++	return err;
++}
++
++static ssize_t cfs_overlay_item_status_show(struct config_item *item,
++		char *page)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	return sprintf(page, "%s\n",
++			overlay->ov_id >= 0 ? "applied" : "unapplied");
++}
++
++CONFIGFS_ATTR(cfs_overlay_item_, path);
++CONFIGFS_ATTR_RO(cfs_overlay_item_, status);
++
++static struct configfs_attribute *cfs_overlay_attrs[] = {
++	&cfs_overlay_item_attr_path,
++	&cfs_overlay_item_attr_status,
++	NULL,
++};
++
++ssize_t cfs_overlay_item_dtbo_read(struct config_item *item,
++		void *buf, size_t max_count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	pr_debug("%s: buf=%p max_count=%zu\n", __func__,
++			buf, max_count);
++
++	if (overlay->dtbo == NULL)
++		return 0;
++
++	/* copy if buffer provided */
++	if (buf != NULL) {
++		/* the buffer must be large enough */
++		if (overlay->dtbo_size > max_count)
++			return -ENOSPC;
++
++		memcpy(buf, overlay->dtbo, overlay->dtbo_size);
++	}
++
++	return overlay->dtbo_size;
++}
++
++ssize_t cfs_overlay_item_dtbo_write(struct config_item *item,
++		const void *buf, size_t count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	int err;
++
++	/* if it's set do not allow changes */
++	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
++		return -EPERM;
++
++	/* copy the contents */
++	overlay->dtbo = kmemdup(buf, count, GFP_KERNEL);
++	if (overlay->dtbo == NULL)
++		return -ENOMEM;
++
++	overlay->dtbo_size = count;
++
++	err = create_overlay(overlay, overlay->dtbo, overlay->dtbo_size);
++	if (err != 0)
++		goto out_err;
++
++	return count;
++
++out_err:
++	kfree(overlay->dtbo);
++	overlay->dtbo = NULL;
++	overlay->dtbo_size = 0;
++
++	return err;
++}
++
++CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M);
++
++static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = {
++	&cfs_overlay_item_attr_dtbo,
++	NULL,
++};
++
++static void cfs_overlay_release(struct config_item *item)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	if (overlay->ov_id >= 0)
++		of_overlay_remove(&overlay->ov_id);
++	if (overlay->fw)
++		release_firmware(overlay->fw);
++	/* kfree with NULL is safe */
++	kfree(overlay->dtbo);
++	kfree(overlay);
++}
++
++static struct configfs_item_operations cfs_overlay_item_ops = {
++	.release	= cfs_overlay_release,
++};
++
++static struct config_item_type cfs_overlay_type = {
++	.ct_item_ops	= &cfs_overlay_item_ops,
++	.ct_attrs	= cfs_overlay_attrs,
++	.ct_bin_attrs	= cfs_overlay_bin_attrs,
++	.ct_owner	= THIS_MODULE,
++};
++
++static struct config_item *cfs_overlay_group_make_item(
++		struct config_group *group, const char *name)
++{
++	struct cfs_overlay_item *overlay;
++
++	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
++	if (!overlay)
++		return ERR_PTR(-ENOMEM);
++	overlay->ov_id = -1;
++
++	config_item_init_type_name(&overlay->item, name, &cfs_overlay_type);
++	return &overlay->item;
++}
++
++static void cfs_overlay_group_drop_item(struct config_group *group,
++		struct config_item *item)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	config_item_put(&overlay->item);
++}
++
++static struct configfs_group_operations overlays_ops = {
++	.make_item	= cfs_overlay_group_make_item,
++	.drop_item	= cfs_overlay_group_drop_item,
++};
++
++static struct config_item_type overlays_type = {
++	.ct_group_ops   = &overlays_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++static struct configfs_group_operations of_cfs_ops = {
++	/* empty - we don't allow anything to be created */
++};
++
++static struct config_item_type of_cfs_type = {
++	.ct_group_ops   = &of_cfs_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++struct config_group of_cfs_overlay_group;
++
++static struct configfs_subsystem of_cfs_subsys = {
++	.su_group = {
++		.cg_item = {
++			.ci_namebuf = "device-tree",
++			.ci_type = &of_cfs_type,
++		},
++	},
++	.su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex),
++};
++
++static int __init of_cfs_init(void)
++{
++	int ret;
++
++	pr_info("%s\n", __func__);
++
++	config_group_init(&of_cfs_subsys.su_group);
++	config_group_init_type_name(&of_cfs_overlay_group, "overlays",
++			&overlays_type);
++	configfs_add_default_group(&of_cfs_overlay_group,
++			&of_cfs_subsys.su_group);
++
++	ret = configfs_register_subsystem(&of_cfs_subsys);
++	if (ret != 0) {
++		pr_err("%s: failed to register subsys\n", __func__);
++		goto out;
++	}
++	pr_info("%s: OK\n", __func__);
++out:
++	return ret;
++}
++late_initcall(of_cfs_init);
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/general-add-restart-handler-for-act8846.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-add-restart-handler-for-act8846.patch
new file mode 100644
index 000000000000..055ba8eeee68
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-add-restart-handler-for-act8846.patch
@@ -0,0 +1,71 @@
+From 7f2d6a02498ce3fa7771893072e81b31f9bd64b2 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Fri, 24 Mar 2023 17:15:16 +0000
+Subject: [PATCH] register act8846 restart handler for SIPC function
+
+---
+ drivers/regulator/act8865-regulator.c | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/drivers/regulator/act8865-regulator.c b/drivers/regulator/act8865-regulator.c
+index 53f2c75cd..e45ad8430 100644
+--- a/drivers/regulator/act8865-regulator.c
++++ b/drivers/regulator/act8865-regulator.c
+@@ -20,6 +20,7 @@
+ #include <linux/regulator/of_regulator.h>
+ #include <linux/regmap.h>
+ #include <dt-bindings/regulator/active-semi,8865-regulator.h>
++#include <linux/reboot.h>
+ 
+ /*
+  * ACT8600 Global Register Map.
+@@ -141,6 +142,8 @@
+ #define	ACT8865_VOLTAGE_NUM	64
+ #define ACT8600_SUDCDC_VOLTAGE_NUM	256
+ 
++#define ACT8846_SIPC_MASK 0x01
++
+ struct act8865 {
+ 	struct regmap *regmap;
+ 	int off_reg;
+@@ -582,6 +585,22 @@ static void act8865_power_off(void)
+ 	while (1);
+ }
+ 
++static int act8846_power_cycle(struct notifier_block *this,
++		unsigned long code, void *unused)
++{
++	struct act8865 *act8846;
++
++	act8846 = i2c_get_clientdata(act8865_i2c_client);
++	regmap_write(act8846->regmap, ACT8846_GLB_OFF_CTRL, ACT8846_SIPC_MASK);
++
++	return NOTIFY_DONE;
++}
++
++static struct notifier_block act8846_restart_handler = {
++	.notifier_call = act8846_power_cycle,
++	.priority = 129,
++};
++
+ static int act8600_charger_get_status(struct regmap *map)
+ {
+ 	unsigned int val;
+@@ -733,6 +752,14 @@ static int act8865_pmic_probe(struct i2c_client *client)
+ 		} else {
+ 			dev_err(dev, "Failed to set poweroff capability, already defined\n");
+ 		}
++
++		if (type == ACT8846) {
++			act8865_i2c_client = client;
++			ret = register_restart_handler(&act8846_restart_handler);
++			if (ret)
++				pr_err("%s: cannot register restart handler, %d\n",
++					__func__, ret);
++		}
+ 	}
+ 
+ 	/* Finally register devices */
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/general-dwc2-fix-wait-peripheral.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-dwc2-fix-wait-peripheral.patch
new file mode 100644
index 000000000000..9a5c933fdf8e
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-dwc2-fix-wait-peripheral.patch
@@ -0,0 +1,26 @@
+From e477f1546f2739e9ea053d677f421e01a9babff4 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 2 Mar 2024 21:56:44 +0100
+Subject: [PATCH] dwc2: add fixes for rk322x peripheral mode
+
+---
+ drivers/usb/dwc2/core.c | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
+index 5635e4d7ec88..0a3d387a497a 100644
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -532,6 +532,9 @@ void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
+ 	gusbcfg |= set;
+ 	dwc2_writel(hsotg, gusbcfg, GUSBCFG);
+ 
++	/* On some rockchip platforms, this fixes hang on reset in peripheral mode */
++	msleep(10);
++
+ 	dwc2_wait_for_mode(hsotg, host);
+ 	return;
+ }
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/general-dwc2-fix-wait-time.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-dwc2-fix-wait-time.patch
new file mode 100644
index 000000000000..f8517ac54733
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-dwc2-fix-wait-time.patch
@@ -0,0 +1,56 @@
+From ee7c3ab6b5a4d284a04f110792508a7f8decd7f7 Mon Sep 17 00:00:00 2001
+From: William Wu <william.wu@rock-chips.com>
+Date: Tue, 6 Dec 2022 14:45:54 +0800
+Subject: [PATCH] usb: dwc2: fix waiting time for host only mode
+
+The current code uses 50ms sleep to wait for host only
+mode, the delay time is not enough for some Rockchip
+platforms (e.g RK3036G EVB1).
+
+Test on RK3036G EVB1, the dwc2 host only controller reg
+GOTGCTL.ConIDSts = 1'b1 (device mode) if only wait for
+50ms. And the host fails to detect usb2 device with the
+following error log:
+
+usb usb2-port1: connect-debounce failed
+
+This patch checks the GOTGCTL.ConIDSts for host only
+mode and increases the maximum waiting time to 200ms.
+
+Signed-off-by: William Wu <william.wu@rock-chips.com>
+Change-Id: Ie28299934aba09907ea08f5fd3b34bf2fb35822e
+---
+ drivers/usb/dwc2/core.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
+index 15911ac7582b4..cbd5f1142f35e 100644
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -656,14 +656,24 @@ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
+  */
+ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
+ {
++	u32 count = 0;
++
+ 	switch (hsotg->dr_mode) {
+ 	case USB_DR_MODE_HOST:
+ 		/*
+ 		 * NOTE: This is required for some rockchip soc based
+ 		 * platforms on their host-only dwc2.
+ 		 */
+-		if (!dwc2_hw_is_otg(hsotg))
+-			msleep(50);
++		if (!dwc2_hw_is_otg(hsotg)) {
++			while (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_CONID_B) {
++				msleep(20);
++				if (++count > 10)
++					break;
++			}
++			if (count > 10)
++				dev_err(hsotg->dev,
++					"Waiting for Host Mode timed out");
++		}
+ 
+ 		break;
+ 	case USB_DR_MODE_PERIPHERAL:
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/general-dwc2-nak-gadget.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-dwc2-nak-gadget.patch
new file mode 100644
index 000000000000..1162a96d9301
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-dwc2-nak-gadget.patch
@@ -0,0 +1,88 @@
+From 15b317ff84dc09faa47995b1d973d96a6172fa4c Mon Sep 17 00:00:00 2001
+From: William Wu <william.wu@rock-chips.com>
+Date: Thu, 15 Dec 2022 14:19:28 +0800
+Subject: [PATCH] usb: dwc2: gadget: Disable nak interrupt when get first isoc
+ in token
+
+The dwc2 driver use the nak interrupt for the starting point
+of isoc-in transfer. The first nak interrupt for isoc-in means
+that in token has arrived and the dwc2 driver can obtain the
+(micro) frame of the token to set the even/odd (micro) frame
+field of DIEPCTL.
+
+However, on some platforms (e.g Rockchip rk3308) which don't
+support the "OTG_MULTI_PROC_INTRPT", it means that all device
+endpoints share the same nak mask and interrupt. If the nak
+interrupt is always enabled, it may trigger nak interrupt storm
+by other endpoints except the isoc-in endpoint. So we disable
+the nak interrupt when get first isoc in token if the feature
+"OTG_MULTI_PROC_INTRPT" isn't enabled.
+
+Signed-off-by: William Wu <william.wu@rock-chips.com>
+Change-Id: I99c71a5e0d7903346fd8f71619b6736c3181c0ec
+---
+ drivers/usb/dwc2/gadget.c | 37 +++++++++++++++++++++++++++++++++++--
+ 1 file changed, 35 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
+index e1dc4735a99c..0e185ef474ac 100644
+--- a/drivers/usb/dwc2/gadget.c
++++ b/drivers/usb/dwc2/gadget.c
+@@ -1402,6 +1402,8 @@ static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
+ 	return 0;
+ }
+ 
++static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep);
++
+ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
+ 			       gfp_t gfp_flags)
+ {
+@@ -1518,6 +1520,20 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
+ 
+ 		if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
+ 			dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
++	} else if (hs_ep->isochronous && hs_ep->dir_in && !hs_ep->req &&
++		   !(dwc2_readl(hs, GHWCFG2) & GHWCFG2_MULTI_PROC_INT)) {
++		/* Update current frame number value. */
++		hs->frame_number = dwc2_hsotg_read_frameno(hs);
++		while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
++			dwc2_gadget_incr_frame_num(hs_ep);
++			/* Update current frame number value once more as it
++			 * changes here.
++			 */
++			hs->frame_number = dwc2_hsotg_read_frameno(hs);
++		}
++
++		if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
++			dwc2_gadget_start_next_request(hs_ep);
+ 	}
+ 	return 0;
+ }
+@@ -2989,8 +3005,25 @@ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
+ 
+ 		hs_ep->target_frame = hsotg->frame_number;
+ 		if (hs_ep->interval > 1) {
+-			u32 ctrl = dwc2_readl(hsotg,
+-					      DIEPCTL(hs_ep->index));
++			u32 mask;
++			u32 ctrl;
++
++			/*
++			 * Disable nak interrupt when we have got the first
++			 * isoc in token. This can avoid nak interrupt storm
++			 * on the Rockchip platforms which don't support the
++			 * "OTG_MULTI_PROC_INTRPT", and all device endpoints
++			 * share the same nak mask and interrupt.
++			 */
++			if (!(dwc2_readl(hsotg, GHWCFG2) &
++			    GHWCFG2_MULTI_PROC_INT)) {
++				mask = dwc2_readl(hsotg, DIEPMSK);
++				mask &= ~DIEPMSK_NAKMSK;
++				dwc2_writel(hsotg, mask, DIEPMSK);
++			}
++
++			ctrl = dwc2_readl(hsotg,
++					  DIEPCTL(hs_ep->index));
+ 			if (hs_ep->target_frame & 0x1)
+ 				ctrl |= DXEPCTL_SETODDFR;
+ 			else
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/general-fix-reboot-from-kwiboo.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-fix-reboot-from-kwiboo.patch
new file mode 100644
index 000000000000..088b7ebe8b06
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-fix-reboot-from-kwiboo.patch
@@ -0,0 +1,19 @@
+diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
+index 5bd58b95d..48ebe081f 100644
+--- a/drivers/mmc/core/core.c
++++ b/drivers/mmc/core/core.c
+@@ -1684,6 +1684,14 @@ void mmc_power_off(struct mmc_host *host)
+ 	if (host->ios.power_mode == MMC_POWER_OFF)
+ 		return;
+ 
++        mmc_set_initial_signal_voltage(host);
++
++        /*
++         * This delay should be sufficient to allow the power supply
++         * to reach the minimum voltage.
++         */
++        mmc_delay(host->ios.power_delay_ms);
++
+ 	mmc_pwrseq_power_off(host);
+ 
+ 	host->ios.clock = 0;
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/general-linux-export-mm-trace-rss-stats.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-linux-export-mm-trace-rss-stats.patch
new file mode 100644
index 000000000000..45c975a46cc8
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-linux-export-mm-trace-rss-stats.patch
@@ -0,0 +1,24 @@
+From 6408e6688b18e5c712c711110d196a4e95f3f870 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Thu, 9 Sep 2021 16:37:28 +0000
+Subject: [PATCH 2/4] 01-linux-1000-export-mm_trace_rss_stat
+
+---
+ mm/memory.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/mm/memory.c b/mm/memory.c
+index 25fc46e87..7ef0adaa5 100644
+--- a/mm/memory.c
++++ b/mm/memory.c
+@@ -171,6 +171,7 @@ void mm_trace_rss_stat(struct mm_struct *mm, int member, long count)
+ {
+ 	trace_rss_stat(mm, member, count);
+ }
++EXPORT_SYMBOL(mm_trace_rss_stat);
+ 
+ #if defined(SPLIT_RSS_COUNTING)
+ 
+-- 
+2.25.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/general-rk322x-gpio-ir-driver.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-rk322x-gpio-ir-driver.patch
new file mode 100644
index 000000000000..0c5ddf94bd4f
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-rk322x-gpio-ir-driver.patch
@@ -0,0 +1,786 @@
+From 13498feb91614d59ebece61d0c278e31529bb8c8 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 10 Oct 2023 21:54:51 +0200
+Subject: [PATCH] rockchip gpio IR driver
+
+---
+ drivers/media/rc/Kconfig       |  11 +
+ drivers/media/rc/Makefile      |   1 +
+ drivers/media/rc/rockchip-ir.c | 723 +++++++++++++++++++++++++++++++++
+ 3 files changed, 735 insertions(+)
+ create mode 100644 drivers/media/rc/rockchip-ir.c
+
+diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
+index 2afe67ffa285..0fd671f5873c 100644
+--- a/drivers/media/rc/Kconfig
++++ b/drivers/media/rc/Kconfig
+@@ -338,6 +338,16 @@ config IR_REDRAT3
+ 	   To compile this driver as a module, choose M here: the
+ 	   module will be called redrat3.
+ 
++config IR_ROCKCHIP_CIR
++	tristate "Rockchip GPIO IR receiver"
++	depends on (OF && GPIOLIB) || COMPILE_TEST
++	help
++	   Say Y here if you want to use the Rockchip IR receiver with
++	   virtual poweroff features provided by rockchip Trust OS
++
++	   To compile this driver as a module, choose M here: the
++	   module will be called rockchip-ir
++
+ config IR_SERIAL
+ 	tristate "Homebrew Serial Port Receiver"
+ 	depends on HAS_IOPORT
+diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
+index 2bca6f7f07bc..2ec037f8b939 100644
+--- a/drivers/media/rc/Makefile
++++ b/drivers/media/rc/Makefile
+@@ -43,6 +43,7 @@ obj-$(CONFIG_IR_MTK) += mtk-cir.o
+ obj-$(CONFIG_IR_NUVOTON) += nuvoton-cir.o
+ obj-$(CONFIG_IR_PWM_TX) += pwm-ir-tx.o
+ obj-$(CONFIG_IR_REDRAT3) += redrat3.o
++obj-$(CONFIG_IR_ROCKCHIP_CIR) += rockchip-ir.o
+ obj-$(CONFIG_IR_SERIAL) += serial_ir.o
+ obj-$(CONFIG_IR_SPI) += ir-spi.o
+ obj-$(CONFIG_IR_STREAMZAP) += streamzap.o
+diff --git a/drivers/media/rc/rockchip-ir.c b/drivers/media/rc/rockchip-ir.c
+new file mode 100644
+index 000000000000..43ade8c4adce
+--- /dev/null
++++ b/drivers/media/rc/rockchip-ir.c
+@@ -0,0 +1,733 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
++*/
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/gpio/consumer.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_qos.h>
++#include <linux/irq.h>
++#include <linux/arm-smccc.h>
++#include <linux/clk.h>
++#include <linux/reboot.h>
++#include <uapi/linux/psci.h>
++#include <media/rc-core.h>
++#include <soc/rockchip/rockchip_sip.h>
++
++#define ROCKCHIP_IR_DEVICE_NAME	"rockchip_ir_recv"
++
++#ifdef CONFIG_64BIT
++#define PSCI_FN_NATIVE(version, name)	PSCI_##version##_FN64_##name
++#else
++#define PSCI_FN_NATIVE(version, name)	PSCI_##version##_FN_##name
++#endif
++
++/*
++* SIP/TEE constants for remote calls
++*/
++#define SIP_REMOTECTL_CFG				0x8200000b
++#define SIP_SUSPEND_MODE		0x82000003
++#define SIP_REMOTECTL_CFG		0x8200000b
++#define SUSPEND_MODE_CONFIG	0x01
++#define WKUP_SOURCE_CONFIG		0x02
++#define PWM_REGULATOR_CONFIG	0x03
++#define GPIO_POWER_CONFIG		0x04
++#define SUSPEND_DEBUG_ENABLE	0x05
++#define APIOS_SUSPEND_CONFIG	0x06
++#define VIRTUAL_POWEROFF		0x07
++
++#define REMOTECTL_SET_IRQ				0xf0
++#define REMOTECTL_SET_PWM_CH			0xf1
++#define REMOTECTL_SET_PWRKEY			0xf2
++#define REMOTECTL_GET_WAKEUP_STATE		0xf3
++#define REMOTECTL_ENABLE				0xf4
++#define REMOTECTL_PWRKEY_WAKEUP			0xdeadbeaf /* wakeup state */
++
++/*
++* PWM Registers
++* Each PWM has its own control registers
++*/
++#define PWM_REG_CNTR	0x00  /* Counter Register */
++#define PWM_REG_HPR		0x04  /* Period Register */
++#define PWM_REG_LPR		0x08  /* Duty Cycle Register */
++#define PWM_REG_CTRL	0x0c  /* Control Register */
++
++/*
++* PWM General registers
++* Registers shared among PWMs
++*/
++#define PWM_REG_INT_EN  0x44
++
++/*REG_CTRL bits definitions*/
++#define PWM_ENABLE		(1 << 0)
++#define PWM_DISABLE		(0 << 0)
++
++/*operation mode*/
++#define PWM_MODE_ONESHOT		(0x00 << 1)
++#define PWM_MODE_CONTINUMOUS	(0x01 << 1)
++#define PWM_MODE_CAPTURE		(0x02 << 1)
++
++/* Channel interrupt enable bit */
++#define PWM_CH_INT_ENABLE(n)		BIT(n)
++
++enum pwm_div {
++	PWM_DIV1	= (0x0 << 12),
++	PWM_DIV2	= (0x1 << 12),
++	PWM_DIV4	= (0x2 << 12),
++	PWM_DIV8	= (0x3 << 12),
++	PWM_DIV16	= (0x4 << 12),
++	PWM_DIV32	= (0x5 << 12),
++	PWM_DIV64	= (0x6 << 12),
++	PWM_DIV128	= (0x7 << 12),
++};
++
++#define PWM_INT_ENABLE		1
++#define PWM_INT_DISABLE		0
++
++struct rockchip_rc_dev {
++	struct rc_dev *rcdev;
++	struct gpio_desc *gpiod;
++	int irq;
++	struct device *pmdev;
++	struct pm_qos_request qos;
++	void __iomem *pwm_base;
++	int pwm_wake_irq;
++	int pwm_id;
++	bool use_shutdown_handler; // if true, installs a shutdown handler and triggers virtual poweroff
++	bool use_suspend_handler; // if true, virtual poweroff is used as suspend mode otherwise use as regular suspend
++	struct pinctrl *pinctrl;
++	struct pinctrl_state *pinctrl_state_default;
++	struct pinctrl_state *pinctrl_state_suspend;
++};
++
++static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
++												unsigned long arg0,
++												unsigned long arg1,
++												unsigned long arg2)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
++	
++	return res;
++}
++
++int sip_smc_remotectl_config(u32 func, u32 data)
++{
++	struct arm_smccc_res res;
++	
++	res = __invoke_sip_fn_smc(SIP_REMOTECTL_CFG, func, data, 0);
++	
++	return res.a0;
++}
++
++int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
++{
++	struct arm_smccc_res res;
++
++	res = __invoke_sip_fn_smc(SIP_SUSPEND_MODE, ctrl, config1, config2);
++	return res.a0;
++}
++
++int sip_smc_virtual_poweroff(void)
++{
++	struct arm_smccc_res res;
++
++	res = __invoke_sip_fn_smc(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND), 0, 0, 0);
++	return res.a0;
++}
++
++static irqreturn_t rockchip_ir_recv_irq(int irq, void *dev_id)
++{
++	int val;
++	struct rockchip_rc_dev *gpio_dev = dev_id;
++	struct device *pmdev = gpio_dev->pmdev;
++
++	/*
++	* For some cpuidle systems, not all:
++	* Respond to interrupt taking more latency when cpu in idle.
++	* Invoke asynchronous pm runtime get from interrupt context,
++	* this may introduce a millisecond delay to call resume callback,
++	* where to disable cpuilde.
++	*
++	* Two issues lead to fail to decode first frame, one is latency to
++	* respond to interrupt, another is delay introduced by async api.
++	*/
++	if (pmdev)
++		pm_runtime_get(pmdev);
++
++	val = gpiod_get_value(gpio_dev->gpiod);
++	if (val >= 0)
++		ir_raw_event_store_edge(gpio_dev->rcdev, val == 1);
++
++	if (pmdev) {
++		pm_runtime_mark_last_busy(pmdev);
++		pm_runtime_put_autosuspend(pmdev);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static void rockchip_pwm_int_ctrl(struct rockchip_rc_dev *gpio_dev, bool enable)
++{
++	
++	void __iomem *pwm_base = gpio_dev->pwm_base;
++	struct device *dev = &gpio_dev->rcdev->dev;
++	int pwm_id = gpio_dev->pwm_id;
++	
++	void __iomem *reg_int_ctrl;
++	int val;
++	
++	reg_int_ctrl= pwm_base - (0x10 * pwm_id) + PWM_REG_INT_EN;
++
++	val = readl_relaxed(reg_int_ctrl);
++	
++	if (enable) {
++		val |= PWM_CH_INT_ENABLE(pwm_id);
++		dev_info(dev, "PWM interrupt enabled, register value %x\n", val);
++	} else {
++		val &= ~PWM_CH_INT_ENABLE(pwm_id);
++		dev_info(dev, "PWM interrupt disabled, register value %x\n", val);
++	}
++	
++	writel_relaxed(val, reg_int_ctrl);
++	
++}
++
++static int rockchip_pwm_hw_init(struct rockchip_rc_dev *gpio_dev)
++{
++	
++	void __iomem *pwm_base = gpio_dev->pwm_base;
++	int val;
++
++	//1. disabled pwm
++	val = readl_relaxed(pwm_base + PWM_REG_CTRL);
++	val = (val & 0xFFFFFFFE) | PWM_DISABLE;
++	writel_relaxed(val, pwm_base + PWM_REG_CTRL);
++	
++	//2. capture mode
++	val = readl_relaxed(pwm_base + PWM_REG_CTRL);
++	val = (val & 0xFFFFFFF9) | PWM_MODE_CAPTURE;
++	writel_relaxed(val, pwm_base + PWM_REG_CTRL);
++	
++	//set clk div, clk div to 64
++	val = readl_relaxed(pwm_base + PWM_REG_CTRL);
++	val = (val & 0xFF0001FF) | PWM_DIV64;
++	writel_relaxed(val, pwm_base + PWM_REG_CTRL);
++	
++	//4. enabled pwm int
++	rockchip_pwm_int_ctrl(gpio_dev, true);
++	
++	//5. enabled pwm
++	val = readl_relaxed(pwm_base + PWM_REG_CTRL);
++	val = (val & 0xFFFFFFFE) | PWM_ENABLE;
++	writel_relaxed(val, pwm_base + PWM_REG_CTRL);
++	
++	return 0;
++	
++}
++
++static int rockchip_pwm_hw_stop(struct rockchip_rc_dev *gpio_dev)
++{
++	
++	void __iomem *pwm_base = gpio_dev->pwm_base;
++	int val;
++	
++	//disable pwm interrupt
++	rockchip_pwm_int_ctrl(gpio_dev, false);
++
++	//disable pwm
++	val = readl_relaxed(pwm_base + PWM_REG_CTRL);
++	val = (val & 0xFFFFFFFE) | PWM_DISABLE;
++	writel_relaxed(val, pwm_base + PWM_REG_CTRL);
++	
++	return 0;
++	
++}
++
++static int rockchip_pwm_sip_wakeup_init(struct rockchip_rc_dev *gpio_dev)
++{
++	
++	struct device *dev = &gpio_dev->rcdev->dev;
++	
++	struct irq_data *irq_data;
++	long hwirq;
++	int ret;
++
++	irq_data = irq_get_irq_data(gpio_dev->pwm_wake_irq);
++	if (!irq_data) {
++		dev_err(dev, "could not get irq data\n");
++		return -1;
++	}
++	
++	hwirq = irq_data->hwirq;
++	dev_info(dev, "use hwirq %ld, pwm chip id %d for PWM SIP wakeup\n", hwirq, gpio_dev->pwm_id);
++	
++	ret = 0;
++	
++	ret |= sip_smc_remotectl_config(REMOTECTL_SET_IRQ, (int)hwirq);
++	ret |= sip_smc_remotectl_config(REMOTECTL_SET_PWM_CH, gpio_dev->pwm_id);
++	ret |= sip_smc_remotectl_config(REMOTECTL_ENABLE, 1);
++	
++	if (ret) {
++		dev_err(dev, "SIP remote controller mode, TEE does not support feature\n");
++		return ret;
++	}
++	
++	sip_smc_set_suspend_mode(SUSPEND_MODE_CONFIG, 0x10042, 0);
++	sip_smc_set_suspend_mode(WKUP_SOURCE_CONFIG, 0x0, 0);
++	sip_smc_set_suspend_mode(PWM_REGULATOR_CONFIG, 0x0, 0);
++	//sip_smc_set_suspend_mode(GPIO_POWER_CONFIG, i, gpio_temp[i]);
++	sip_smc_set_suspend_mode(SUSPEND_DEBUG_ENABLE, 0x1, 0);
++	sip_smc_set_suspend_mode(APIOS_SUSPEND_CONFIG, 0x0, 0);
++	sip_smc_set_suspend_mode(VIRTUAL_POWEROFF, 0, 1);
++	
++	dev_info(dev, "TEE remote controller wakeup installed\n");
++	
++	return 0;
++	
++}
++
++static int rockchip_ir_recv_remove(struct platform_device *pdev)
++{
++	struct rockchip_rc_dev *gpio_dev = platform_get_drvdata(pdev);
++	struct device *pmdev = gpio_dev->pmdev;
++
++	if (pmdev) {
++		pm_runtime_get_sync(pmdev);
++		cpu_latency_qos_remove_request(&gpio_dev->qos);
++
++		pm_runtime_disable(pmdev);
++		pm_runtime_put_noidle(pmdev);
++		pm_runtime_set_suspended(pmdev);
++	}
++	
++	// Disable the remote controller handling of the Trust OS
++	sip_smc_remotectl_config(REMOTECTL_ENABLE, 0);
++	
++	// Disable the virtual poweroff of the Trust OS
++	sip_smc_set_suspend_mode(VIRTUAL_POWEROFF, 0, 0);	
++
++	return 0;
++}
++
++static int rockchip_ir_register_power_key(struct device *dev)
++{
++	
++	struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
++	
++	struct rc_map *key_map;
++	struct rc_map_table *key;
++	int idx, key_scancode, rev_scancode;
++	int tee_scancode;
++	
++	key_map = &gpio_dev->rcdev->rc_map;
++	
++	dev_info(dev, "remote key table %s, key map of %d items\n", key_map->name, key_map->len);
++	
++	for (idx = 0; idx < key_map->len; idx++) {
++		
++		key = &key_map->scan[idx];
++		
++		if (key->keycode != KEY_POWER)
++			continue;
++
++		key_scancode = key->scancode;
++		rev_scancode = ~key_scancode;
++
++		// If key_scancode has higher 16 bits set to 0, then the scancode is NEC protocol, otherwise it is NECX/NEC32
++		if ((key_scancode & 0xffff) == key_scancode)
++			tee_scancode = (key_scancode & 0xff00) | ((rev_scancode & 0xff00) << 8); // NEC protocol
++		else
++			tee_scancode = ((key_scancode & 0xff0000) >> 8) | ((key_scancode & 0xff00) << 8); // NECX/NEC32 protocol
++
++		tee_scancode |= rev_scancode & 0xff;
++		tee_scancode <<= 8;
++	
++		sip_smc_remotectl_config(REMOTECTL_SET_PWRKEY, tee_scancode);
++		
++		dev_info(dev, "registered scancode %08x (SIP: %8x)\n", key_scancode, tee_scancode);
++		
++	}
++	
++	return 0;
++	
++}
++
++static int rockchip_ir_recv_suspend_prepare(struct device *dev)
++{
++	struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
++	int ret;
++	
++	dev_info(dev, "initialize rockchip SIP virtual poweroff\n");
++	ret = rockchip_pwm_sip_wakeup_init(gpio_dev);
++	
++	if (ret)
++		return ret;
++	
++	rockchip_ir_register_power_key(dev);
++	
++	disable_irq(gpio_dev->irq);
++	dev_info(dev, "GPIO IRQ disabled\n");
++
++	ret = pinctrl_select_state(gpio_dev->pinctrl, gpio_dev->pinctrl_state_suspend);
++	if (ret) {
++		dev_err(dev, "unable to set pin in PWM mode\n");
++		return ret;
++	}
++	
++	dev_info(dev, "set pin configuration to PWM mode\n");
++	
++	rockchip_pwm_hw_init(gpio_dev);
++	dev_info(dev, "started pin PWM mode\n");
++	
++	return 0;
++	
++}
++
++#ifdef CONFIG_PM
++static int rockchip_ir_recv_suspend(struct device *dev)
++{
++	struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
++	
++	/*
++	 * if property suspend-is-virtual-poweroff is set, we can disable
++	 * the regular gpio wakeup and enable the PWM mode for the Trust OS
++	 * to take control and react to remote control.
++	 * If the property is not set, we instead enable the wake up for the
++	 * regular gpio.
++	 */
++	if (gpio_dev->use_suspend_handler) {
++		
++		rockchip_ir_recv_suspend_prepare(dev);
++		
++	} else {
++		
++		if (device_may_wakeup(dev))
++			enable_irq_wake(gpio_dev->irq);
++		else
++			disable_irq(gpio_dev->irq);
++		
++	}
++
++	return 0;
++}
++
++static int rockchip_ir_recv_resume(struct device *dev)
++{
++	struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
++	int ret;
++	
++	/*
++	 * In case suspend-is-virtual-poweroff property is set,
++	 * restore the pin from PWM mode to regular GPIO configuration
++	 * and stop the PWM function.
++	 * Otherwise, just enable the regular GPIO irq
++	 */
++	if (gpio_dev->use_suspend_handler) {
++	
++		rockchip_pwm_hw_stop(gpio_dev);
++		dev_info(dev, "stopped pin PWM mode\n");
++		
++		ret = pinctrl_select_state(gpio_dev->pinctrl, gpio_dev->pinctrl_state_default);
++		if (ret) {
++			dev_err(dev, "unable to restore pin in GPIO mode\n");
++			return ret;
++		}
++		dev_info(dev, "restored pin configuration di GPIO\n");
++		
++		enable_irq(gpio_dev->irq);
++		dev_info(dev, "restored GPIO IRQ\n");
++		
++	} else {
++		
++		if (device_may_wakeup(dev))
++			disable_irq_wake(gpio_dev->irq);
++		else
++			enable_irq(gpio_dev->irq);
++	
++	}
++
++	return 0;
++}
++
++static void rockchip_ir_recv_shutdown(struct platform_device *pdev)
++{
++	
++	struct device *dev = &pdev->dev;
++	struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
++	
++	if (gpio_dev->use_shutdown_handler)
++		rockchip_ir_recv_suspend_prepare(dev);
++	
++	return;
++	
++}
++
++static int rockchip_ir_recv_sys_off(struct sys_off_data *data)
++{
++	
++	sip_smc_virtual_poweroff();
++	
++	return 0;
++	
++}
++
++static int rockchip_ir_recv_init_sip(void)
++{
++	struct arm_smccc_res res;
++	
++	arm_smccc_smc(ROCKCHIP_SIP_SIP_VERSION, ROCKCHIP_SIP_IMPLEMENT_V2, SECURE_REG_WR, 0, 0, 0, 0, 0, &res);
++	
++	if (res.a0)
++		return 0;
++		
++	return res.a1;
++	
++}
++
++static int rockchip_ir_recv_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct rockchip_rc_dev *gpio_dev;
++	struct rc_dev *rcdev;
++	struct clk *clk;
++	struct clk *p_clk;
++	struct resource *res;
++	u32 period = 0;
++	int rc;
++	int ret;
++	int pwm_wake_irq;
++	int clocks;
++
++	if (!np)
++		return -ENODEV;
++
++	gpio_dev = devm_kzalloc(dev, sizeof(*gpio_dev), GFP_KERNEL);
++	if (!gpio_dev)
++		return -ENOMEM;
++
++	gpio_dev->gpiod = devm_gpiod_get(dev, NULL, GPIOD_IN);
++	if (IS_ERR(gpio_dev->gpiod)) {
++		rc = PTR_ERR(gpio_dev->gpiod);
++		/* Just try again if this happens */
++		if (rc != -EPROBE_DEFER)
++			dev_err(dev, "error getting gpio (%d)\n", rc);
++		return rc;
++	}
++	gpio_dev->irq = gpiod_to_irq(gpio_dev->gpiod);
++	if (gpio_dev->irq < 0)
++		return gpio_dev->irq;
++
++	rcdev = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
++	if (!rcdev)
++		return -ENOMEM;
++
++	rcdev->priv = gpio_dev;
++	rcdev->device_name = ROCKCHIP_IR_DEVICE_NAME;
++	rcdev->input_phys = ROCKCHIP_IR_DEVICE_NAME "/input0";
++	rcdev->input_id.bustype = BUS_HOST;
++	rcdev->input_id.vendor = 0x0001;
++	rcdev->input_id.product = 0x0001;
++	rcdev->input_id.version = 0x0100;
++	rcdev->dev.parent = dev;
++	rcdev->driver_name = KBUILD_MODNAME;
++	rcdev->min_timeout = 1;
++	rcdev->timeout = IR_DEFAULT_TIMEOUT;
++	rcdev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
++	rcdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
++	rcdev->map_name = of_get_property(np, "linux,rc-map-name", NULL);
++	if (!rcdev->map_name)
++		rcdev->map_name = RC_MAP_EMPTY;
++
++	gpio_dev->rcdev = rcdev;
++	if (of_property_read_bool(np, "wakeup-source")) {
++		
++		ret = device_init_wakeup(dev, true);
++		
++		if (ret)
++			dev_err(dev, "could not init wakeup device\n");
++		
++	}
++
++	rc = devm_rc_register_device(dev, rcdev);
++	if (rc < 0) {
++		dev_err(dev, "failed to register rc device (%d)\n", rc);
++		return rc;
++	}
++
++	of_property_read_u32(np, "linux,autosuspend-period", &period);
++	if (period) {
++		gpio_dev->pmdev = dev;
++		pm_runtime_set_autosuspend_delay(dev, period);
++		pm_runtime_use_autosuspend(dev);
++		pm_runtime_set_suspended(dev);
++		pm_runtime_enable(dev);
++	}
++	
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(dev, "no memory resources defined\n");
++		return -ENODEV;
++	}
++	
++	gpio_dev->pwm_base = devm_ioremap_resource(dev, res);
++	if (IS_ERR(gpio_dev->pwm_base))
++		return PTR_ERR(gpio_dev->pwm_base);
++	
++	clocks = of_property_count_strings(np, "clock-names");
++	if (clocks == 2) {
++		clk = devm_clk_get(dev, "pwm");
++		p_clk = devm_clk_get(dev, "pclk");
++	} else {
++		clk = devm_clk_get(dev, NULL);
++		p_clk = clk;
++	}
++	
++	if (IS_ERR(clk)) {
++		ret = PTR_ERR(clk);
++		if (ret != -EPROBE_DEFER)
++			dev_err(dev, "Can't get bus clock: %d\n", ret);
++		return ret;
++	}
++	
++	if (IS_ERR(p_clk)) {
++		ret = PTR_ERR(p_clk);
++		if (ret != -EPROBE_DEFER)
++			dev_err(dev, "Can't get peripheral clock: %d\n", ret);
++		return ret;
++	}
++	
++	ret = clk_prepare_enable(clk);
++	if (ret) {
++		dev_err(dev, "Can't enable bus clk: %d\n", ret);
++		return ret;
++	}
++	
++	ret = clk_prepare_enable(p_clk);
++	if (ret) {
++		dev_err(dev, "Can't enable peripheral clk: %d\n", ret);
++		goto error_clk;
++	}
++	
++	pwm_wake_irq = platform_get_irq(pdev, 0);
++	if (pwm_wake_irq < 0) {
++		dev_err(&pdev->dev, "cannot find PWM wake interrupt\n");
++		goto error_pclk;
++	}
++	
++	gpio_dev->pwm_wake_irq = pwm_wake_irq;
++	ret = enable_irq_wake(pwm_wake_irq);
++	if (ret) {
++		dev_err(dev, "could not enable IRQ wakeup\n");
++	}
++	
++	ret = of_property_read_u32(np, "pwm-id", &gpio_dev->pwm_id);
++	if (ret) {
++		dev_err(dev, "missing pwm-id property\n");
++		goto error_pclk;
++	}
++	
++	if (gpio_dev->pwm_id > 3) {
++		dev_err(dev, "invalid pwm-id property\n");
++		goto error_pclk;
++	}
++	
++	gpio_dev->use_shutdown_handler = of_property_read_bool(np, "shutdown-is-virtual-poweroff");
++	gpio_dev->use_suspend_handler = of_property_read_bool(np, "suspend-is-virtual-poweroff");
++	
++	gpio_dev->pinctrl = devm_pinctrl_get(dev);
++	if (IS_ERR(gpio_dev->pinctrl)) {
++		dev_err(dev, "Unable to get pinctrl\n");
++		goto error_pclk;
++	}
++	
++	gpio_dev->pinctrl_state_default = pinctrl_lookup_state(gpio_dev->pinctrl, "default");
++	if (IS_ERR(gpio_dev->pinctrl_state_default)) {
++		dev_err(dev, "Unable to get default pinctrl state\n");
++		goto error_pclk;
++	}
++	
++	gpio_dev->pinctrl_state_suspend = pinctrl_lookup_state(gpio_dev->pinctrl, "suspend");
++	if (IS_ERR(gpio_dev->pinctrl_state_suspend)) {
++		dev_err(dev, "Unable to get suspend pinctrl state\n");
++		goto error_pclk;
++	}
++	
++	platform_set_drvdata(pdev, gpio_dev);
++
++	ret = devm_request_irq(dev, gpio_dev->irq, rockchip_ir_recv_irq,
++				IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
++				"gpio-ir-recv-irq", gpio_dev);
++	if (ret) {
++		dev_err(dev, "Can't request GPIO interrupt\n");
++		goto error_pclk;
++	}
++	
++	if (gpio_dev->use_shutdown_handler) {
++		
++		ret = devm_register_sys_off_handler(dev, SYS_OFF_MODE_POWER_OFF, 
++			SYS_OFF_PRIO_FIRMWARE, rockchip_ir_recv_sys_off, NULL);
++		
++		if (ret)
++			dev_err(dev, "could not register sys_off handler\n");
++		
++	}
++	
++	ret = rockchip_ir_recv_init_sip();
++	if (!ret) {
++		dev_err(dev, "Unable to initialize Rockchip SIP v2, virtual poweroff unavailable\n");
++		gpio_dev->use_shutdown_handler = false;
++		gpio_dev->use_suspend_handler = false;
++	} else {
++		dev_info(dev, "rockchip SIP initialized, version 0x%x\n", ret);
++	}
++		
++	return 0;
++
++error_pclk:
++	clk_unprepare(p_clk);	
++error_clk:
++	clk_unprepare(clk);
++	
++	return -ENODEV;
++	
++}
++
++static const struct dev_pm_ops rockchip_ir_recv_pm_ops = {
++	.suspend        = rockchip_ir_recv_suspend,
++	.resume         = rockchip_ir_recv_resume,
++};
++#endif
++
++static const struct of_device_id rockchip_ir_recv_of_match[] = {
++	{ .compatible = "rockchip-ir-receiver", },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, rockchip_ir_recv_of_match);
++
++static struct platform_driver rockchip_ir_recv_driver = {
++	.probe  = rockchip_ir_recv_probe,
++	.remove = rockchip_ir_recv_remove,
++	.shutdown = rockchip_ir_recv_shutdown,
++	.driver = {
++		.name   = KBUILD_MODNAME,
++		.of_match_table = of_match_ptr(rockchip_ir_recv_of_match),
++#ifdef CONFIG_PM
++		.pm	= &rockchip_ir_recv_pm_ops,
++#endif
++	},
++};
++module_platform_driver(rockchip_ir_recv_driver);
++
++MODULE_DESCRIPTION("Rockchip IR Receiver driver");
++MODULE_LICENSE("GPL v2");
+
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/general-rockchip-various-fixes.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-rockchip-various-fixes.patch
new file mode 100644
index 000000000000..206f44442540
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/general-rockchip-various-fixes.patch
@@ -0,0 +1,770 @@
+From 92a42b2df843c0f6c2937dc6bdbfe72332c9e557 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Thu, 9 Sep 2021 16:46:33 +0000
+Subject: [PATCH 3/4] 01-linux-1000-rockchip-wip
+
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi                 | 101 +++++++++++++++++-
+ arch/arm/boot/dts/rockchip/rk3xxx.dtsi                 |   2 +
+ drivers/clk/rockchip/clk-rk3228.c             |  61 ++++-------
+ drivers/net/ethernet/arc/emac.h               |  14 +++
+ drivers/net/ethernet/arc/emac_main.c          |  81 ++++++++++++--
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c |  38 ++++++-
+ drivers/pmdomain/rockchip/pm-domains.c             |  23 ++++
+ drivers/usb/dwc2/core.c                       |   2 +-
+ 8 files changed, 266 insertions(+), 56 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 831561fc1814..24e963b01d87 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -19,6 +19,7 @@ aliases {
+ 		gpio1 = &gpio1;
+ 		gpio2 = &gpio2;
+ 		gpio3 = &gpio3;
++		ethernet0 = &gmac;
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
+ 		serial2 = &uart2;
+@@ -105,6 +106,22 @@ arm-pmu {
+ 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ 	};
+ 
++	hdmi_sound: hdmi-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "hdmi-sound";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		status = "disabled";
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s0>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++	};
++
+ 	psci {
+ 		compatible = "arm,psci-1.0", "arm,psci-0.2";
+ 		method = "smc";
+@@ -132,6 +149,17 @@ display_subsystem: display-subsystem {
+ 		ports = <&vop_out>;
+ 	};
+ 
++	crypto: cypto-controller@100a0000 {
++		compatible = "rockchip,rk3288-crypto";
++		reg = <0x100a0000 0x4000>;
++		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru HCLK_M_CRYPTO>, <&cru HCLK_S_CRYPTO>,
++		<&cru SCLK_CRYPTO>, <&cru ACLK_DMAC>;
++		clock-names = "aclk", "hclk", "sclk", "apb_pclk";
++		resets = <&cru SRST_CRYPTO>;
++		reset-names = "crypto-rst";
++	};
++
+ 	i2s1: i2s1@100b0000 {
+ 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ 		reg = <0x100b0000 0x4000>;
+@@ -142,6 +170,7 @@ i2s1: i2s1@100b0000 {
+ 		dma-names = "tx", "rx";
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&i2s1_bus>;
++		#sound-dai-cells = <0>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -153,6 +182,7 @@ i2s0: i2s0@100c0000 {
+ 		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
+ 		dmas = <&pdma 11>, <&pdma 12>;
+ 		dma-names = "tx", "rx";
++		#sound-dai-cells = <0>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -166,6 +196,7 @@ spdif: spdif@100d0000 {
+ 		dma-names = "tx";
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&spdif_tx>;
++		#sound-dai-cells = <0>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -337,7 +368,7 @@ uart2: serial@11030000 {
+ 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ 		clock-names = "baudclk", "apb_pclk";
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&uart2_xfer>;
++		pinctrl-0 = <&uart21_xfer>;
+ 		reg-shift = <2>;
+ 		reg-io-width = <4>;
+ 		status = "disabled";
+@@ -358,6 +389,10 @@ efuse_id: id@7 {
+ 		cpu_leakage: cpu_leakage@17 {
+ 			reg = <0x17 0x1>;
+ 		};
++		hdmi_phy_flag: hdmi-phy-flag@1d {
++			reg = <0x1d 0x1>;
++			bits = <1 1>;
++		};
+ 	};
+ 
+ 	i2c0: i2c@11050000 {
+@@ -554,6 +589,11 @@ map1 {
+ 						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ 						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ 				};
++				map2 {
++					trip = <&cpu_alert1>;
++					cooling-device =
++						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
+ 			};
+ 		};
+ 	};
+@@ -584,6 +624,8 @@ hdmi_phy: hdmi-phy@12030000 {
+ 		clock-names = "sysclk", "refoclk", "refpclk";
+ 		#clock-cells = <0>;
+ 		clock-output-names = "hdmiphy_phy";
++		nvmem-cells = <&hdmi_phy_flag>;
++		nvmem-cell-names = "hdmi-phy-flag";
+ 		#phy-cells = <0>;
+ 		status = "disabled";
+ 	};
+@@ -607,7 +649,27 @@ gpu: gpu@20000000 {
+ 		clock-names = "bus", "core";
+ 		power-domains = <&power RK3228_PD_GPU>;
+ 		resets = <&cru SRST_GPU_A>;
+-		status = "disabled";
++		operating-points-v2 = <&gpu_opp_table>;
++		#cooling-cells = <2>; /* min followed by max */
++	};
++
++	gpu_opp_table: opp-table2 {
++		compatible = "operating-points-v2";
++
++		opp-200000000 {
++			opp-hz = /bits/ 64 <200000000>;
++			opp-microvolt = <1050000>;
++		};
++
++		opp-300000000 {
++			opp-hz = /bits/ 64 <300000000>;
++			opp-microvolt = <1050000>;
++		};
++
++		opp-500000000 {
++			opp-hz = /bits/ 64 <500000000>;
++			opp-microvolt = <1150000>;
++		};
+ 	};
+ 
+ 	vpu: video-codec@20020000 {
+@@ -727,6 +789,7 @@ hdmi: hdmi@200a0000 {
+ 		phys = <&hdmi_phy>;
+ 		phy-names = "hdmi";
+ 		rockchip,grf = <&grf>;
++		#sound-dai-cells = <0>;
+ 		status = "disabled";
+ 
+ 		ports {
+@@ -748,9 +811,13 @@ sdmmc: mmc@30000000 {
+ 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++		bus-width = <4>;
+ 		fifo-depth = <0x100>;
++		max-frequency = <150000000>;
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
++		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_pwr>;
++		resets = <&cru SRST_SDMMC>;
++		reset-names = "reset";
+ 		status = "disabled";
+ 	};
+ 
+@@ -760,10 +827,14 @@ sdio: mmc@30010000 {
+ 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
++		bus-width = <4>;
+ 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ 		fifo-depth = <0x100>;
++		max-frequency = <150000000>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
++		resets = <&cru SRST_SDIO>;
++		reset-names = "reset";
+ 		status = "disabled";
+ 	};
+ 
+@@ -771,14 +842,13 @@ emmc: mmc@30020000 {
+ 		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
+ 		reg = <0x30020000 0x4000>;
+ 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+-		clock-frequency = <37500000>;
+-		max-frequency = <37500000>;
+ 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ 		bus-width = <8>;
+ 		rockchip,default-sample-phase = <158>;
+ 		fifo-depth = <0x100>;
++		max-frequency = <150000000>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ 		resets = <&cru SRST_EMMC>;
+@@ -1029,6 +1099,10 @@ sdmmc_bus4: sdmmc-bus4 {
+ 						<1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
+ 						<1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
+ 			};
++
++			sdmmc_pwr: sdmmc-pwr {
++				rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
++			};
+ 		};
+ 
+ 		sdio {
+@@ -1261,13 +1335,30 @@ uart1_xfer: uart1-xfer {
+ 						<1 RK_PB2 1 &pcfg_pull_none>;
+ 			};
+ 
++			uart11_xfer: uart11-xfer {
++				rockchip,pins = <3 RK_PB6 1 &pcfg_pull_up>,
++						<3 RK_PB5 1 &pcfg_pull_none>;
++			};
++
+ 			uart1_cts: uart1-cts {
+ 				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
+ 			};
+ 
++			uart11_cts: uart11-cts {
++				rockchip,pins = <3 RK_PA7 1 &pcfg_pull_none>;
++			};
++
+ 			uart1_rts: uart1-rts {
+ 				rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
+ 			};
++
++			uart11_rts: uart11-rts {
++				rockchip,pins = <3 RK_PA6 1 &pcfg_pull_none>;
++			};
++
++			uart11_rts_gpio: uart11-rts-gpio {
++				rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++			};
+ 		};
+ 
+ 		uart2 {
+diff --git a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
+index 616a828e0..f233b7a77 100644
+--- a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
+@@ -64,6 +64,8 @@ L2: cache-controller@10138000 {
+ 		reg = <0x10138000 0x1000>;
+ 		cache-unified;
+ 		cache-level = <2>;
++		prefetch-data = <1>;
++		prefetch-instr = <1>;
+ 	};
+ 
+ 	scu@1013c000 {
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index aca1a483a..7250adc64 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -135,24 +135,22 @@ static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
+ 
+ PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };
+ 
+-PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr", "apll_ddr" };
++PNAME(mux_ddrphy_p)		= { "dpll", "gpll", "apll" };
+ PNAME(mux_armclk_p)		= { "apll_core", "gpll_core", "dpll_core" };
+ PNAME(mux_usb480m_phy_p)	= { "usb480m_phy0", "usb480m_phy1" };
+ PNAME(mux_usb480m_p)		= { "usb480m_phy", "xin24m" };
+ PNAME(mux_hdmiphy_p)		= { "hdmiphy_phy", "xin24m" };
+-PNAME(mux_aclk_cpu_src_p)	= { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
+ 
+ PNAME(mux_pll_src_4plls_p)	= { "cpll", "gpll", "hdmiphy", "usb480m" };
+ PNAME(mux_pll_src_3plls_p)	= { "cpll", "gpll", "hdmiphy" };
+ PNAME(mux_pll_src_2plls_p)	= { "cpll", "gpll" };
+ PNAME(mux_sclk_hdmi_cec_p)	= { "cpll", "gpll", "xin24m" };
+-PNAME(mux_aclk_peri_src_p)	= { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
+ PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "xin24m", "usb480m" };
+ PNAME(mux_pll_src_cpll_gpll_usb480m_p)	= { "cpll", "gpll", "usb480m" };
+ 
+ PNAME(mux_sclk_rga_p)		= { "gpll", "cpll", "sclk_rga_src" };
+ 
+-PNAME(mux_sclk_vop_src_p)	= { "gpll_vop", "cpll_vop" };
++PNAME(mux_sclk_vop_src_p)	= { "gpll", "cpll" };
+ PNAME(mux_dclk_vop_p)		= { "hdmiphy", "sclk_vop_pre" };
+ 
+ PNAME(mux_i2s0_p)		= { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
+@@ -221,27 +219,23 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 			RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
+ 
+ 	/* PD_DDR */
+-	GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
++	COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
++			RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+ 			RK2928_CLKGATE_CON(0), 2, GFLAGS),
+-	GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(0), 2, GFLAGS),
+-	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(0), 2, GFLAGS),
+-	COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+-			RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
++	GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED,
+ 			RK2928_CLKGATE_CON(7), 1, GFLAGS),
+-	GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
++	FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
+ 			RK2928_CLKGATE_CON(8), 5, GFLAGS),
+-	FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
++	FACTOR_GATE(0, "ddrphy", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
+ 			RK2928_CLKGATE_CON(7), 0, GFLAGS),
+ 
+ 	/* PD_CORE */
+-	GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(0), 6, GFLAGS),
+ 	GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
+ 			RK2928_CLKGATE_CON(0), 6, GFLAGS),
+ 	GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
+ 			RK2928_CLKGATE_CON(0), 6, GFLAGS),
++	GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
++			RK2928_CLKGATE_CON(0), 6, GFLAGS),
+ 	COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
+ 			RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ 			RK2928_CLKGATE_CON(4), 1, GFLAGS),
+@@ -258,14 +252,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 			RK2928_MISC_CON, 15, 1, MFLAGS),
+ 
+ 	/* PD_BUS */
+-	GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
++	COMPOSITE(0, "aclk_cpu_src", mux_pll_src_3plls_p, 0,
++			RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
+ 			RK2928_CLKGATE_CON(0), 1, GFLAGS),
+-	GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(0), 1, GFLAGS),
+-	GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(0), 1, GFLAGS),
+-	COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
+-			RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
+ 	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
+ 			RK2928_CLKGATE_CON(6), 0, GFLAGS),
+ 	COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
+@@ -338,14 +327,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 			RK2928_CLKGATE_CON(3), 8, GFLAGS),
+ 
+ 	/* PD_PERI */
+-	GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(2), 0, GFLAGS),
+-	GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
++	COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
++			RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS,
+ 			RK2928_CLKGATE_CON(2), 0, GFLAGS),
+-	GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(2), 0, GFLAGS),
+-	COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
+-			RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
+ 	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
+ 			RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
+ 			RK2928_CLKGATE_CON(5), 2, GFLAGS),
+@@ -380,7 +364,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 			RK2928_CLKGATE_CON(10), 12, GFLAGS),
+ 
+ 	COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
+-			RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
++			RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ 			RK2928_CLKGATE_CON(2), 15, GFLAGS),
+ 
+ 	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
+@@ -403,12 +387,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	 * Clock-Architecture Diagram 2
+ 	 */
+ 
+-	GATE(0, "gpll_vop", "gpll", 0,
+-			RK2928_CLKGATE_CON(3), 1, GFLAGS),
+-	GATE(0, "cpll_vop", "cpll", 0,
++	COMPOSITE_NODIV(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
++			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS,
+ 			RK2928_CLKGATE_CON(3), 1, GFLAGS),
+-	MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
+-			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
+ 	DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,
+ 			RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
+ 	DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
+@@ -640,13 +621,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 
+ 	/* PD_MMC */
+ 	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
+-	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
++	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
+ 
+ 	MMC(SCLK_SDIO_DRV,     "sdio_drv",     "sclk_sdio",  RK3228_SDIO_CON0,  1),
+-	MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3228_SDIO_CON1,  0),
++	MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3228_SDIO_CON1,  1),
+ 
+ 	MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3228_EMMC_CON0,  1),
+-	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  0),
++	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  1),
+ };
+ 
+ static const char *const rk3228_critical_clocks[] __initconst = {
+@@ -661,6 +642,7 @@ static const char *const rk3228_critical_clocks[] __initconst = {
+ 	"aclk_vop_noc",
+ 	"aclk_hdcp_noc",
+ 	"hclk_vio_ahb_arbi",
++	"hclk_vio_h2p",
+ 	"hclk_vio_noc",
+ 	"hclk_vop_noc",
+ 	"hclk_host0_arb",
+@@ -678,10 +660,13 @@ static const char *const rk3228_critical_clocks[] __initconst = {
+ 	"pclk_ddrphy",
+ 	"pclk_acodecphy",
+ 	"pclk_phy_noc",
++	"pclk_vio_h2p",
+ 	"aclk_vpu_noc",
+ 	"aclk_rkvdec_noc",
++	"aclk_rkvdec",
+ 	"hclk_vpu_noc",
+ 	"hclk_rkvdec_noc",
++	"hclk_rkvdec",
+ };
+ 
+ static void __init rk3228_clk_init(struct device_node *np)
+diff --git a/drivers/net/ethernet/arc/emac.h b/drivers/net/ethernet/arc/emac.h
+index d820ae03a..0ac87288b 100644
+--- a/drivers/net/ethernet/arc/emac.h
++++ b/drivers/net/ethernet/arc/emac.h
+@@ -91,6 +91,20 @@ struct arc_emac_bd {
+ #define RX_RING_SZ	(RX_BD_NUM * sizeof(struct arc_emac_bd))
+ #define TX_RING_SZ	(TX_BD_NUM * sizeof(struct arc_emac_bd))
+ 
++/* PHY fixups */
++#define RTL_8201F_PHY_ID  		0x001cc816
++
++#define RTL_8201F_PG_SELECT_REG 	0x1f
++#define RTL_8201F_PG4_EEE_REG		0x10
++#define RTL_8201F_PG4_EEE_RX_QUIET_EN		BIT(8)
++#define RTL_8201F_PG4_EEE_TX_QUIET_EN		BIT(9)
++#define RTL_8201F_PG4_EEE_NWAY_EN		BIT(12)
++#define RTL_8201F_PG4_EEE_10M_CAP		BIT(13)
++#define RTL_8201F_PG7_RMSR_REG		0x10
++#define RTL_8201F_PG7_RMSR_CLK_DIR_IN		BIT(12)
++#define RTL_8201F_PG0_PSMR_REG		0x18
++#define RTL_8201F_PG0_PSMR_PWRSVE_EN		BIT(15)
++
+ /**
+  * struct buffer_state - Stores Rx/Tx buffer state.
+  * @sk_buff:	Pointer to socket buffer.
+diff --git a/drivers/net/ethernet/arc/emac_main.c b/drivers/net/ethernet/arc/emac_main.c
+index 67b8113a2..40332a976 100644
+--- a/drivers/net/ethernet/arc/emac_main.c
++++ b/drivers/net/ethernet/arc/emac_main.c
+@@ -140,7 +140,7 @@ static void arc_emac_tx_clean(struct net_device *ndev)
+ 			stats->tx_bytes += skb->len;
+ 		}
+ 
+-		dma_unmap_single(&ndev->dev, dma_unmap_addr(tx_buff, addr),
++		dma_unmap_single(ndev->dev.parent, dma_unmap_addr(tx_buff, addr),
+ 				 dma_unmap_len(tx_buff, len), DMA_TO_DEVICE);
+ 
+ 		/* return the sk_buff to system */
+@@ -223,9 +223,9 @@ static int arc_emac_rx(struct net_device *ndev, int budget)
+ 			continue;
+ 		}
+ 
+-		addr = dma_map_single(&ndev->dev, (void *)skb->data,
++		addr = dma_map_single(ndev->dev.parent, (void *)skb->data,
+ 				      EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
+-		if (dma_mapping_error(&ndev->dev, addr)) {
++		if (dma_mapping_error(ndev->dev.parent, addr)) {
+ 			if (net_ratelimit())
+ 				netdev_err(ndev, "cannot map dma buffer\n");
+ 			dev_kfree_skb(skb);
+@@ -237,7 +237,7 @@ static int arc_emac_rx(struct net_device *ndev, int budget)
+ 		}
+ 
+ 		/* unmap previosly mapped skb */
+-		dma_unmap_single(&ndev->dev, dma_unmap_addr(rx_buff, addr),
++		dma_unmap_single(ndev->dev.parent, dma_unmap_addr(rx_buff, addr),
+ 				 dma_unmap_len(rx_buff, len), DMA_FROM_DEVICE);
+ 
+ 		pktlen = info & LEN_MASK;
+@@ -445,9 +445,9 @@ static int arc_emac_open(struct net_device *ndev)
+ 		if (unlikely(!rx_buff->skb))
+ 			return -ENOMEM;
+ 
+-		addr = dma_map_single(&ndev->dev, (void *)rx_buff->skb->data,
++		addr = dma_map_single(ndev->dev.parent, (void *)rx_buff->skb->data,
+ 				      EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
+-		if (dma_mapping_error(&ndev->dev, addr)) {
++		if (dma_mapping_error(ndev->dev.parent, addr)) {
+ 			netdev_err(ndev, "cannot dma map\n");
+ 			dev_kfree_skb(rx_buff->skb);
+ 			return -ENOMEM;
+@@ -555,7 +555,7 @@ static void arc_free_tx_queue(struct net_device *ndev)
+ 		struct buffer_state *tx_buff = &priv->tx_buff[i];
+ 
+ 		if (tx_buff->skb) {
+-			dma_unmap_single(&ndev->dev,
++			dma_unmap_single(ndev->dev.parent,
+ 					 dma_unmap_addr(tx_buff, addr),
+ 					 dma_unmap_len(tx_buff, len),
+ 					 DMA_TO_DEVICE);
+@@ -586,7 +586,7 @@ static void arc_free_rx_queue(struct net_device *ndev)
+ 		struct buffer_state *rx_buff = &priv->rx_buff[i];
+ 
+ 		if (rx_buff->skb) {
+-			dma_unmap_single(&ndev->dev,
++			dma_unmap_single(ndev->dev.parent,
+ 					 dma_unmap_addr(rx_buff, addr),
+ 					 dma_unmap_len(rx_buff, len),
+ 					 DMA_FROM_DEVICE);
+@@ -692,10 +692,10 @@ static netdev_tx_t arc_emac_tx(struct sk_buff *skb, struct net_device *ndev)
+ 		return NETDEV_TX_BUSY;
+ 	}
+ 
+-	addr = dma_map_single(&ndev->dev, (void *)skb->data, len,
++	addr = dma_map_single(ndev->dev.parent, (void *)skb->data, len,
+ 			      DMA_TO_DEVICE);
+ 
+-	if (unlikely(dma_mapping_error(&ndev->dev, addr))) {
++	if (unlikely(dma_mapping_error(ndev->dev.parent, addr))) {
+ 		stats->tx_dropped++;
+ 		stats->tx_errors++;
+ 		dev_kfree_skb_any(skb);
+@@ -850,6 +850,62 @@ static const struct net_device_ops arc_emac_netdev_ops = {
+ #endif
+ };
+ 
++/**
++ * arc_emac_rtl8201f_phy_fixup
++ * @phydev: Pointer to phy_device structure.
++ *
++ * This function registers a fixup in case RTL8201F's phy
++ * clockout is used as reference for the mac interface
++ * and disable EEE, since emac can't handle it
++ */
++static int arc_emac_rtl8201f_phy_fixup(struct phy_device *phydev)
++{
++	unsigned int reg, curr_pg;
++	int err = 0;
++
++	curr_pg = phy_read(phydev, RTL_8201F_PG_SELECT_REG);
++	err = phy_write(phydev, RTL_8201F_PG_SELECT_REG, 4);
++	if (err)
++		goto out_err;
++	mdelay(10);
++
++	/* disable EEE */
++	reg = phy_read(phydev, RTL_8201F_PG4_EEE_REG);
++	reg &=  ~RTL_8201F_PG4_EEE_RX_QUIET_EN &
++		~RTL_8201F_PG4_EEE_TX_QUIET_EN &
++		~RTL_8201F_PG4_EEE_NWAY_EN &
++		~RTL_8201F_PG4_EEE_10M_CAP;
++	err = phy_write(phydev, RTL_8201F_PG4_EEE_REG, reg);
++	if (err)
++		goto out_err;
++
++	if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
++		err = phy_write(phydev, RTL_8201F_PG_SELECT_REG, 7);
++		if (err)
++			goto out_err;
++		mdelay(10);
++
++		reg = phy_read(phydev, RTL_8201F_PG7_RMSR_REG);
++		err = phy_write(phydev, RTL_8201F_PG_SELECT_REG, 0);
++		if (err)
++			goto out_err;
++		mdelay(10);
++
++		if (!(reg & RTL_8201F_PG7_RMSR_CLK_DIR_IN)) {
++			/* disable powersave if phy's clock output is used */
++			reg = phy_read(phydev, RTL_8201F_PG0_PSMR_REG);
++			reg &= ~RTL_8201F_PG0_PSMR_PWRSVE_EN & 0xffff;
++			err = phy_write(phydev, RTL_8201F_PG0_PSMR_REG, reg);
++		}
++	}
++
++out_err:
++	phy_write(phydev, RTL_8201F_PG_SELECT_REG, curr_pg);
++	mdelay(10);
++
++	return err;
++};
++
+ int arc_emac_probe(struct net_device *ndev, int interface)
+ {
+ 	struct device *dev = ndev->dev.parent;
+@@ -970,6 +1026,11 @@ int arc_emac_probe(struct net_device *ndev, int interface)
+ 		goto out_clken;
+ 	}
+ 
++	err = phy_register_fixup_for_uid(RTL_8201F_PHY_ID, 0xfffff0,
++					 arc_emac_rtl8201f_phy_fixup);
++	if (err)
++		dev_warn(dev, "Cannot register PHY board fixup.\n");
++
+ 	phydev = of_phy_connect(ndev, phy_node, arc_emac_adjust_link, 0,
+ 				interface);
+ 	if (!phydev) {
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index 1889e78e1..6209f51b3 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -237,6 +237,9 @@ struct inno_hdmi_phy {
+ 	struct clk *refoclk;
+ 	struct clk *refpclk;
+ 
++	/* phy_flag flag */
++	bool phy_flag;
++
+ 	/* platform data */
+ 	const struct inno_hdmi_phy_drv_data *plat_data;
+ 	int chip_version;
+@@ -471,6 +474,7 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
+ static const struct post_pll_config post_pll_cfg_table[] = {
+ 	{33750000,  1, 40, 8, 1},
+ 	{33750000,  1, 80, 8, 2},
++	{33750000,  1, 10, 2, 4},
+ 	{74250000,  1, 40, 8, 1},
+ 	{74250000, 18, 80, 8, 2},
+ 	{148500000, 2, 40, 4, 3},
+@@ -621,8 +625,11 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
+ 		return -EINVAL;
+ 
+ 	for (; cfg->tmdsclock != 0; cfg++)
+-		if (tmdsclock <= cfg->tmdsclock &&
+-		    cfg->version & inno->chip_version)
++		if (((!inno->phy_flag || tmdsclock > 33750000)
++		     && tmdsclock <= cfg->tmdsclock
++		     && cfg->version & inno->chip_version) ||
++		    (inno->phy_flag && tmdsclock <= 33750000
++		     && cfg->version & 4))
+ 			break;
+ 
+ 	for (; phy_cfg->tmdsclock != 0; phy_cfg++)
+@@ -1033,6 +1040,10 @@ static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
+ 
+ static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
+ {
++	struct nvmem_cell *cell;
++	unsigned char *efuse_buf;
++	size_t len;
++
+ 	/*
+ 	 * Use phy internal register control
+ 	 * rxsense/poweron/pllpd/pdataen signal.
+@@ -1047,7 +1058,28 @@ static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
+ 	inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
+ 			 RK3228_POST_PLL_CTRL_MANUAL);
+ 
++
+ 	inno->chip_version = 1;
++	inno->phy_flag = false;
++
++	cell = nvmem_cell_get(inno->dev, "hdmi-phy-flag");
++	if (IS_ERR(cell)) {
++		if (PTR_ERR(cell) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++
++		return 0;
++	}
++
++	efuse_buf = nvmem_cell_read(cell, &len);
++	nvmem_cell_put(cell);
++
++	if (IS_ERR(efuse_buf))
++		return 0;
++	if (len == 1)
++		inno->phy_flag = (efuse_buf[0] & BIT(1)) ? true : false;
++	kfree(efuse_buf);
++
++	dev_info(inno->dev, "phy_flag is: %d\n", inno->phy_flag);
+ 
+ 	return 0;
+ }
+@@ -1147,6 +1179,8 @@ static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
+ 
+ 	/* try to read the chip-version */
+ 	inno->chip_version = 1;
++	inno->phy_flag = false;
++
+ 	cell = nvmem_cell_get(inno->dev, "cpu-version");
+ 	if (IS_ERR(cell)) {
+ 		if (PTR_ERR(cell) == -EPROBE_DEFER)
+diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
+index fddb4022c..9583c76b4 100644
+--- a/drivers/pmdomain/rockchip/pm-domains.c
++++ b/drivers/pmdomain/rockchip/pm-domains.c
+@@ -73,6 +73,7 @@ struct rockchip_pm_domain {
+ 	struct regmap **qos_regmap;
+ 	u32 *qos_save_regs[MAX_QOS_REGS_NUM];
+ 	int num_clks;
++	bool is_ignore_pwr;
+ 	struct clk_bulk_data *clks;
+ };
+ 
+@@ -361,6 +362,9 @@ static int rockchip_pd_power_on(struct generic_pm_domain *domain)
+ {
+ 	struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
+ 
++	if (pd->is_ignore_pwr)
++		return 0;
++
+ 	return rockchip_pd_power(pd, true);
+ }
+ 
+@@ -368,6 +372,9 @@ static int rockchip_pd_power_off(struct generic_pm_domain *domain)
+ {
+ 	struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
+ 
++	if (pd->is_ignore_pwr)
++		return 0;
++
+ 	return rockchip_pd_power(pd, false);
+ }
+ 
+@@ -447,6 +454,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ 	pd->info = pd_info;
+ 	pd->pmu = pmu;
+ 
++	if (!pd_info->pwr_mask)
++		pd->is_ignore_pwr = true;
++
+ 	pd->num_clks = of_clk_get_parent_count(node);
+ 	if (pd->num_clks > 0) {
+ 		pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
+@@ -600,6 +610,7 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
+ {
+ 	struct device_node *np;
+ 	struct generic_pm_domain *child_domain, *parent_domain;
++	struct rockchip_pm_domain *child_pd, *parent_pd;
+ 	int error;
+ 
+ 	for_each_child_of_node(parent, np) {
+@@ -640,6 +651,18 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
+ 				parent_domain->name, child_domain->name);
+ 		}
+ 
++		/*
++		 * If child_pd doesn't do idle request or power on/off,
++		 * parent_pd may fail to do power on/off, so if parent_pd
++		 * need to power on/off, child_pd can't ignore to do idle
++		 * request and power on/off.
++		 */
++		child_pd = to_rockchip_pd(child_domain);
++		parent_pd = to_rockchip_pd(parent_domain);
++		if (!parent_pd->is_ignore_pwr)
++			child_pd->is_ignore_pwr = false;
++
++
+ 		rockchip_pm_add_subdomain(pmu, np);
+ 	}
+ 
+-- 
+2.25.1
+
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/ir-keymap-rk322x-box.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/ir-keymap-rk322x-box.patch
new file mode 100644
index 000000000000..2c10b95bc042
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/ir-keymap-rk322x-box.patch
@@ -0,0 +1,119 @@
+From f14539f8d08328ae5aad165a4deea25c7d6b09bf Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Mon, 25 Apr 2022 13:25:09 +0000
+Subject: [PATCH] add generic rk322x tv box remote controller keymap
+
+---
+ drivers/media/rc/keymaps/Makefile          |  1 +
+ drivers/media/rc/keymaps/rc-rk322x-tvbox.c | 74 ++++++++++++++++++++++
+ include/media/rc-map.h                     |  1 +
+ 3 files changed, 77 insertions(+)
+ create mode 100644 drivers/media/rc/keymaps/rc-rk322x-tvbox.c
+
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index 5fe5c9e1a46..1aa49b78a65 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -99,6 +99,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
+ 			rc-rc6-mce.o \
+ 			rc-real-audio-220-32-keys.o \
+ 			rc-reddo.o \
++			rc-rk322x-tvbox.o \
+ 			rc-snapstream-firefly.o \
+ 			rc-streamzap.o \
+ 			rc-tanix-tx3mini.o \
+diff --git a/drivers/media/rc/keymaps/rc-rk322x-tvbox.c b/drivers/media/rc/keymaps/rc-rk322x-tvbox.c
+new file mode 100644
+index 00000000000..91e24ee52ee
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-rk322x-tvbox.c
+@@ -0,0 +1,74 @@
++// SPDX-License-Identifier: GPL-2.0+
++// rc-rk322x-tvbox.c - Keytable for rk322x generic tv box remote controller
++//
++// keymap imported from ir-keymaps.c
++//
++// Copyright (c) 2022 Paolo Sabatino
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++/*
++
++*/
++
++static struct rc_map_table rk322x_tvbox[] = {
++
++	{ 0x40400d, KEY_ENTER },
++	{ 0x40404d, KEY_POWER },
++	{ 0x40401e, KEY_PREVIOUSSONG },
++	{ 0x40401f, KEY_NEXTSONG },
++	{ 0x404001, KEY_1 },
++	{ 0x404002, KEY_2 },
++	{ 0x404003, KEY_3 },
++	{ 0x404004, KEY_4 },
++	{ 0x404005, KEY_5 },
++	{ 0x404006, KEY_6 },
++	{ 0x404007, KEY_7 },
++	{ 0x404008, KEY_8 },
++	{ 0x404009, KEY_9 },
++	{ 0x404000, KEY_0 },
++	{ 0x40400c, KEY_BACKSPACE },
++	{ 0x404044, KEY_F6 },
++	{ 0x40401a, KEY_HOME },
++	{ 0x404042, KEY_BACK },
++	{ 0x404045, KEY_MENU },
++	{ 0x40400f, KEY_TEXT },
++	{ 0x404010, KEY_LEFT },
++	{ 0x404011, KEY_RIGHT },
++	{ 0x40400e, KEY_DOWN },
++	{ 0x40400b, KEY_UP },
++	{ 0x40401c, KEY_VOLUMEDOWN },
++	{ 0x404043, KEY_MUTE },
++	{ 0x404015, KEY_VOLUMEUP },
++	{ 0x404053, KEY_F1 },
++	{ 0x40405b, KEY_F2 },
++	{ 0x404057, KEY_F3 },
++	{ 0x404054, KEY_F4 },
++
++};
++
++static struct rc_map_list rk322x_tvbox_map = {
++	.map = {
++		.scan     = rk322x_tvbox,
++		.size     = ARRAY_SIZE(rk322x_tvbox),
++		.rc_proto = RC_PROTO_NEC,	/* Legacy IR type */
++		.name     = RC_MAP_RK322X_TVBOX,
++	}
++};
++
++static int __init init_rc_map_rk322x_tvbox(void)
++{
++	return rc_map_register(&rk322x_tvbox_map);
++}
++
++static void __exit exit_rc_map_rk322x_tvbox(void)
++{
++	rc_map_unregister(&rk322x_tvbox_map);
++}
++
++module_init(init_rc_map_rk322x_tvbox)
++module_exit(exit_rc_map_rk322x_tvbox)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Paolo Sabatino");
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index 793b54342df..35aba84be9f 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -310,6 +310,7 @@ struct rc_map *rc_map_get(const char *name);
+ #define RC_MAP_RC6_MCE                   "rc-rc6-mce"
+ #define RC_MAP_REAL_AUDIO_220_32_KEYS    "rc-real-audio-220-32-keys"
+ #define RC_MAP_REDDO                     "rc-reddo"
++#define RC_MAP_RK322X_TVBOX              "rc-rk322x-tvbox"
+ #define RC_MAP_SNAPSTREAM_FIREFLY        "rc-snapstream-firefly"
+ #define RC_MAP_STREAMZAP                 "rc-streamzap"
+ #define RC_MAP_SU3000                    "rc-su3000"
+-- 
+2.30.2
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/ir-keymap-xt-q8l-v10.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/ir-keymap-xt-q8l-v10.patch
new file mode 100644
index 000000000000..eb4faa632591
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/ir-keymap-xt-q8l-v10.patch
@@ -0,0 +1,118 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Fri, 10 Jun 2022 15:59:15 +0000
+Subject: add xt-q8l-v10 keymap and makefile
+
+---
+ drivers/media/rc/keymaps/Makefile        |  1 +
+ drivers/media/rc/keymaps/rc-xt-q8l-v10.c | 76 ++++++++++
+ include/media/rc-map.h                   |  1 +
+ 3 files changed, 78 insertions(+)
+
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index f513ff5caf4e..198ef8bc2614 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -136,4 +136,5 @@ obj-$(CONFIG_RC_MAP) += \
+ 			rc-x96max.o \
+ 			rc-xbox-360.o \
+ 			rc-xbox-dvd.o \
++			rc-xt-q8l-v10.o \
+ 			rc-zx-irdec.o
+diff --git a/drivers/media/rc/keymaps/rc-xt-q8l-v10.c b/drivers/media/rc/keymaps/rc-xt-q8l-v10.c
+new file mode 100644
+index 000000000000..19c7d9ec8325
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-xt-q8l-v10.c
+@@ -0,0 +1,76 @@
++// SPDX-License-Identifier: GPL-2.0+
++// rc-xt-q8l-v10.c - Keytable for xt-q8l-v10 tv box remote controller
++//
++// keymap imported from ir-keymaps.c
++//
++// Copyright (c) 2018 Paolo Sabatino
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++/*
++
++*/
++
++static struct rc_map_table xt_q8l_v10[] = {
++	
++	{ 0xcc1d11, KEY_ENTER },
++	{ 0xcc1d00, KEY_POWER },
++	{ 0xcc1d15, KEY_PLAYPAUSE },
++	{ 0xcc1d16, KEY_STOP },
++	{ 0xcc1d06, KEY_PREVIOUSSONG },
++	{ 0xcc1d0a, KEY_NEXTSONG },
++	{ 0xcc1d41, KEY_1 },
++	{ 0xcc1d45, KEY_2 },
++	{ 0xcc1d4d, KEY_3 },
++	{ 0xcc1d42, KEY_4 },
++	{ 0xcc1d46, KEY_5 },
++	{ 0xcc1d4e, KEY_6 },
++	{ 0xcc1d43, KEY_7 },
++	{ 0xcc1d47, KEY_8 },
++	{ 0xcc1d4f, KEY_9 },
++	{ 0xcc1d49, KEY_0 },
++	{ 0xcc1d4a, KEY_BACKSPACE },
++	{ 0xcc1d48, KEY_F6 },
++	{ 0xcc1d03, KEY_HOME },
++	{ 0xcc1d0f, KEY_BACK },
++	{ 0xcc1d40, KEY_MENU },
++	{ 0xcc1d4c, KEY_TEXT },
++	{ 0xcc1d10, KEY_LEFT },
++	{ 0xcc1d12, KEY_RIGHT },
++	{ 0xcc1d44, KEY_DOWN },
++	{ 0xcc1d07, KEY_UP },
++	{ 0xcc1d02, KEY_VOLUMEDOWN },
++	{ 0xcc1d0c, KEY_MUTE },
++	{ 0xcc1d0e, KEY_VOLUMEUP },
++	{ 0xcc1d01, KEY_F1 },
++	{ 0xcc1d05, KEY_F2 },
++	{ 0xcc1d09, KEY_F3 },
++	{ 0xcc1d0d, KEY_F4 },
++	
++};
++
++static struct rc_map_list xt_q8l_v10_map = {
++	.map = {
++		.scan     = xt_q8l_v10,
++		.size     = ARRAY_SIZE(xt_q8l_v10),
++		.rc_proto = RC_PROTO_NEC,	/* Legacy IR type */
++		.name     = RC_MAP_XT_Q8L_V10,
++	}
++};
++
++static int __init init_rc_map_xt_q8l_v10(void)
++{
++	return rc_map_register(&xt_q8l_v10_map);
++}
++
++static void __exit exit_rc_map_xt_q8l_v10(void)
++{
++	rc_map_unregister(&xt_q8l_v10_map);
++}
++
++module_init(init_rc_map_xt_q8l_v10)
++module_exit(exit_rc_map_xt_q8l_v10)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Paolo Sabatino");
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index 793b54342dff..ef7f3710eafe 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -343,6 +343,7 @@ struct rc_map *rc_map_get(const char *name);
+ #define RC_MAP_X96MAX                    "rc-x96max"
+ #define RC_MAP_XBOX_360                  "rc-xbox-360"
+ #define RC_MAP_XBOX_DVD                  "rc-xbox-dvd"
++#define RC_MAP_XT_Q8L_V10                "rc-xt-q8l-v10"
+ #define RC_MAP_ZX_IRDEC                  "rc-zx-irdec"
+ 
+ /*
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/misc-tinkerboard-spi-interface.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/misc-tinkerboard-spi-interface.patch
new file mode 100644
index 000000000000..f3a1f6b83963
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/misc-tinkerboard-spi-interface.patch
@@ -0,0 +1,20 @@
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index 5a038c667401..5dd1acf7f12a 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -713,6 +713,7 @@ static const struct spi_device_id spidev_spi_ids[] = {
+ 	{ .name = "spi-authenta" },
+ 	{ .name = "em3581" },
+ 	{ .name = "si3210" },
++	{ .name = "spi_tinker" },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(spi, spidev_spi_ids);
+@@ -741,6 +742,7 @@ static const struct of_device_id spidev_dt_ids[] = {
+ 	{ .compatible = "semtech,sx1301", .data = &spidev_of_check },
+ 	{ .compatible = "silabs,em3581", .data = &spidev_of_check },
+ 	{ .compatible = "silabs,si3210", .data = &spidev_of_check },
++	{ .compatible = "rockchip,spi_tinker", .data = &spidev_of_check },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, spidev_dt_ids);
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch
new file mode 100644
index 000000000000..77385b14be1e
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch
@@ -0,0 +1,116 @@
+From 302cd9b8a9f1f8a7735fabea3b9a7645dc40f9cc Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Sun, 7 Jan 2018 01:52:44 +0100
+Subject: [PATCH] drivers: mmc: dw-mci-rockchip: Handle ASUS Tinkerboard reboot
+
+On ASUS Tinkerboard systems, if the SDMMC hardware is shutdown before
+rebooting, the system will be dead, as the SDMMC is the only way to
+boot anything, and the hardware doesn't power up the SDMMC hardware
+automatically when rebooting.
+
+So, when using an ASUS Tinkerboard system, a new reboot handler is
+installed. This reboot handler takes care of powering the SDMMC
+hardware again before restarting the system, resolving the issue.
+
+The code was inspired by the pwrseq_emmc.c, which seems to overcome
+similar effects with eMMC hardware.
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
+---
+ drivers/mmc/host/dw_mmc-rockchip.c | 66 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 66 insertions(+)
+
+diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
+index a3f1c2b30..7eac1f221 100644
+--- a/drivers/mmc/host/dw_mmc-rockchip.c
++++ b/drivers/mmc/host/dw_mmc-rockchip.c
+@@ -16,6 +16,11 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/slab.h>
+ 
++#include <linux/regulator/consumer.h>
++#include <linux/reboot.h>
++#include <linux/delay.h>
++#include "../core/core.h"
++
+ #include "dw_mmc.h"
+ #include "dw_mmc-pltfm.h"
+ 
+@@ -334,6 +339,66 @@ static const struct of_device_id dw_mci_rockchip_match[] = {
+ };
+ MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
+ 
++struct dw_mci_rockchip_broken_boards_data {
++	struct notifier_block reset_nb;
++	struct platform_device *pdev;
++};
++
++/* This reboot handler handles cases where disabling the SDMMC on
++ * reboot will cause the hardware to be unable to start correctly
++ * after rebooting.
++ * 
++ * This happens with Tinkerboard systems...
++ */
++static int dw_mci_rockchip_broken_boards_reset_nb(
++	struct notifier_block *this,
++	unsigned long mode, void *cmd)
++{
++	struct dw_mci_rockchip_broken_boards_data const *data =
++		container_of(this,
++			struct dw_mci_rockchip_broken_boards_data,
++			reset_nb);
++	struct dw_mci *host = platform_get_drvdata(data->pdev);
++	struct mmc_host *mmc = host->slot->mmc;
++
++	printk(KERN_ERR "Meow.\n");
++
++	mmc_power_off(mmc);
++
++	mdelay(20);
++
++	if (!IS_ERR(mmc->supply.vmmc))
++		regulator_enable(mmc->supply.vmmc);
++
++	if (!IS_ERR(mmc->supply.vqmmc))
++		regulator_set_voltage(mmc->supply.vqmmc, 3000000, 3300000);
++
++	printk(KERN_ERR "woeM.\n");
++
++	return NOTIFY_DONE;
++}
++
++static void dw_mci_rockchip_register_broken_boards_reboot_handler(
++	struct platform_device *pdev)
++{
++	struct dw_mci_rockchip_broken_boards_data *data;
++
++	if (!of_machine_is_compatible("asus,rk3288-tinker"))
++		return;
++
++	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++
++	if (!data)
++		return;
++
++	data->reset_nb.notifier_call =
++		dw_mci_rockchip_broken_boards_reset_nb;
++	data->reset_nb.priority = 255;
++	register_restart_handler(&data->reset_nb);
++
++	data->pdev = pdev;
++}
++
+ static int dw_mci_rockchip_probe(struct platform_device *pdev)
+ {
+ 	const struct dw_mci_drv_data *drv_data;
+@@ -361,6 +426,7 @@ static int dw_mci_rockchip_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	pm_runtime_put_autosuspend(&pdev->dev);
++	dw_mci_rockchip_register_broken_boards_reboot_handler(pdev);
+ 
+ 	return 0;
+ }
+-- 
+2.14.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch
new file mode 100644
index 000000000000..ed7158039f5c
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch
@@ -0,0 +1,234 @@
+From e039790fb29227f646e91e6d7ec7c3e89c584243 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 6 Jul 2021 14:21:52 +0000
+Subject: [PATCH 1/5] rk3228/rk3328: fix ddr clock gate, add SIP v2 calls
+
+---
+ drivers/clk/rockchip/clk-ddr.c    | 130 ++++++++++++++++++++++++++++++
+ drivers/clk/rockchip/clk-rk3228.c |  14 ++--
+ drivers/clk/rockchip/clk-rk3328.c |   7 +-
+ drivers/clk/rockchip/clk.h        |   3 +-
+ 4 files changed, 143 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
+index 86718c54e..b16b3795f 100644
+--- a/drivers/clk/rockchip/clk-ddr.c
++++ b/drivers/clk/rockchip/clk-ddr.c
+@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = {
+ 	.get_parent = rockchip_ddrclk_get_parent,
+ };
+ 
++/* See v4.4/include/dt-bindings/display/rk_fb.h */
++#define SCREEN_NULL			0
++#define SCREEN_HDMI			6
++
++static inline int rk_drm_get_lcdc_type(void)
++{
++	return SCREEN_NULL;
++}
++
++struct share_params {
++	u32 hz;
++	u32 lcdc_type;
++	u32 vop;
++	u32 vop_dclk_mode;
++	u32 sr_idle_en;
++	u32 addr_mcu_el3;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag1;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag0;
++	u32 complt_hwirq;
++	 /* if need, add parameter after */
++};
++
++struct rockchip_ddrclk_data {
++	u32 inited_flag;
++	void __iomem *share_memory;
++};
++
++static struct rockchip_ddrclk_data ddr_data;
++
++static void rockchip_ddrclk_data_init(void)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
++		      1, SHARE_PAGE_TYPE_DDR, 0,
++		      0, 0, 0, 0, &res);
++
++	if (!res.a0) {
++		ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
++		ddr_data.inited_flag = 1;
++	}
++}
++
++static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
++					   unsigned long drate,
++					   unsigned long prate)
++{
++	struct share_params *p;
++	struct arm_smccc_res res;
++
++	if (!ddr_data.inited_flag)
++		rockchip_ddrclk_data_init();
++
++	p = (struct share_params *)ddr_data.share_memory;
++
++	p->hz = drate;
++	p->lcdc_type = rk_drm_get_lcdc_type();
++	p->wait_flag1 = 1;
++	p->wait_flag0 = 1;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0,
++		      ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
++		      0, 0, 0, 0, &res);
++
++	if ((int)res.a1 == -6) {
++		pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
++		/* TODO: rockchip_dmcfreq_wait_complete(); */
++	}
++
++	return res.a0;
++}
++
++static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
++			(struct clk_hw *hw, unsigned long parent_rate)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0,
++		      ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
++		      0, 0, 0, 0, &res);
++	if (!res.a0)
++		return res.a1;
++	else
++		return 0;
++}
++
++static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
++					      unsigned long rate,
++					      unsigned long *prate)
++{
++	struct share_params *p;
++	struct arm_smccc_res res;
++
++	if (!ddr_data.inited_flag)
++		rockchip_ddrclk_data_init();
++
++	p = (struct share_params *)ddr_data.share_memory;
++
++	p->hz = rate;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0,
++		      ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
++		      0, 0, 0, 0, &res);
++	if (!res.a0)
++		return res.a1;
++	else
++		return 0;
++}
++
++static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
++	.recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
++	.set_rate = rockchip_ddrclk_sip_set_rate_v2,
++	.round_rate = rockchip_ddrclk_sip_round_rate_v2,
++	.get_parent = rockchip_ddrclk_get_parent,
++};
++
+ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+ 					 const char *const *parent_names,
+ 					 u8 num_parents, int mux_offset,
+@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+ 	case ROCKCHIP_DDRCLK_SIP:
+ 		init.ops = &rockchip_ddrclk_sip_ops;
+ 		break;
++	case ROCKCHIP_DDRCLK_SIP_V2:
++		init.ops = &rockchip_ddrclk_sip_ops_v2;
++		break;
+ 	default:
+ 		pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
+ 		kfree(ddrclk);
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 1f9176a5c..96393aa16 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -218,9 +218,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 			RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
+ 
+ 	/* PD_DDR */
+-	COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+-			RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+-			RK2928_CLKGATE_CON(0), 2, GFLAGS),
++	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
++			RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
++			ROCKCHIP_DDRCLK_SIP_V2),
+ 	GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED,
+ 			RK2928_CLKGATE_CON(7), 1, GFLAGS),
+ 	FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
+@@ -576,8 +576,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
+ 	GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
+ 
+-	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
+-	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
++	GATE(0, "pclk_ddr_upctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
++	GATE(0, "pclk_ddr_mon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
+ 	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
+ 
+ 	GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
+@@ -652,8 +652,8 @@ static const char *const rk3228_critical_clocks[] __initconst = {
+ 	"sclk_initmem_mbist",
+ 	"aclk_initmem",
+ 	"hclk_rom",
+-	"pclk_ddrupctl",
+-	"pclk_ddrmon",
++	"pclk_ddr_upctl",
++	"pclk_ddr_mon",
+ 	"pclk_msch_noc",
+ 	"pclk_stimer",
+ 	"pclk_ddrphy",
+diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
+index cc18dbc18..5fdd611bb 100644
+--- a/drivers/clk/rockchip/clk-rk3328.c
++++ b/drivers/clk/rockchip/clk-rk3328.c
+@@ -317,9 +317,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
+ 			RK3328_CLKGATE_CON(14), 1, GFLAGS),
+ 
+ 	/* PD_DDR */
+-	COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+-			RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+-			RK3328_CLKGATE_CON(0), 4, GFLAGS),
++	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
++			RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
++			ROCKCHIP_DDRCLK_SIP_V2),
++
+ 	GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
+ 			RK3328_CLKGATE_CON(18), 6, GFLAGS),
+ 	GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
+diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
+index ae059b774..fdaa81ebb 100644
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -363,7 +363,8 @@ struct clk *rockchip_clk_register_mmc(const char *name,
+  * DDRCLK flags, including method of setting the rate
+  * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
+  */
+-#define ROCKCHIP_DDRCLK_SIP		BIT(0)
++#define ROCKCHIP_DDRCLK_SIP		0x01
++#define ROCKCHIP_DDRCLK_SIP_V2		0x03
+ 
+ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+ 					 const char *const *parent_names,
+-- 
+2.25.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch
new file mode 100644
index 000000000000..efeaace36252
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch
@@ -0,0 +1,67 @@
+From 95358ea4a4434ad4af5545b3f762508e4f015fc3 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 6 Jul 2021 14:23:36 +0000
+Subject: [PATCH 2/5] rk3228/rk3328: add ddr clock and SIP related constants
+ and defines
+
+---
+ include/dt-bindings/clock/rk3228-cru.h |  1 +
+ include/soc/rockchip/rockchip_sip.h    | 24 ++++++++++++++++++++++++
+ 2 files changed, 25 insertions(+)
+
+diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
+index de550ea56..911824731 100644
+--- a/include/dt-bindings/clock/rk3228-cru.h
++++ b/include/dt-bindings/clock/rk3228-cru.h
+@@ -15,6 +15,7 @@
+ #define ARMCLK			5
+ 
+ /* sclk gates (special clocks) */
++#define SCLK_DDRCLK		64
+ #define SCLK_SPI0		65
+ #define SCLK_NANDC		67
+ #define SCLK_SDMMC		68
+diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h
+index c46a9ae2a..34e653751 100644
+--- a/include/soc/rockchip/rockchip_sip.h
++++ b/include/soc/rockchip/rockchip_sip.h
+@@ -6,6 +6,7 @@
+ #ifndef __SOC_ROCKCHIP_SIP_H
+ #define __SOC_ROCKCHIP_SIP_H
+ 
++#define ROCKCHIP_SIP_ATF_VERSION		0x82000001
+ #define ROCKCHIP_SIP_DRAM_FREQ			0x82000008
+ #define ROCKCHIP_SIP_CONFIG_DRAM_INIT		0x00
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE	0x01
+@@ -16,5 +17,28 @@
+ #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ	0x06
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM	0x07
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD	0x08
++#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION	0x08
++#define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE  0x09
++#define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL    0x0a
++#define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG          0x0b
++
++#define ROCKCHIP_SIP_SHARE_MEM			0x82000009
++#define ROCKCHIP_SIP_SIP_VERSION		0x8200000a
++
++/* Rockchip Sip version */
++#define ROCKCHIP_SIP_IMPLEMENT_V1                (1)
++#define ROCKCHIP_SIP_IMPLEMENT_V2                (2)
++
++/* SIP_ACCESS_REG: read or write */
++#define SECURE_REG_RD			0x0
++#define SECURE_REG_WR			0x1
++
++/* Share mem page types */
++typedef enum {
++    SHARE_PAGE_TYPE_INVALID = 0,
++    SHARE_PAGE_TYPE_UARTDBG,
++    SHARE_PAGE_TYPE_DDR,
++    SHARE_PAGE_TYPE_MAX,
++} share_page_type_t;
+ 
+ #endif
+-- 
+2.25.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch
new file mode 100644
index 000000000000..b1b3aa8a5b14
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch
@@ -0,0 +1,199 @@
+From de9678fab28f23bdc3969cdea397f4057d42ba5a Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Thu, 11 Jan 2024 20:42:48 +0100
+Subject: [PATCH] add rk3228/rk3328 to rockchip dfi driver
+
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi |  7 +++
+ drivers/devfreq/event/rockchip-dfi.c   | 77 +++++++++++++++++++++++---
+ include/soc/rockchip/rk3228_grf.h      | 14 +++++
+ include/soc/rockchip/rk3328_grf.h      | 14 +++++
+ 4 files changed, 105 insertions(+), 7 deletions(-)
+ create mode 100644 include/soc/rockchip/rk3228_grf.h
+ create mode 100644 include/soc/rockchip/rk3328_grf.h
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 571626d879f8..e87096b97610 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -208,6 +208,13 @@ xin24m: oscillator {
+ 		#clock-cells = <0>;
+ 	};
+ 
++	dfi: dfi@11210000 {
++		reg = <0x11210000 0x400>;
++		compatible = "rockchip,rk3228-dfi";
++		rockchip,grf = <&grf>;
++		status = "okay";
++	};
++
+ 	display_subsystem: display-subsystem {
+ 		compatible = "rockchip,display-subsystem";
+ 		ports = <&vop_out>;
+diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
+index e2a1e4463b6f..fba3a958b352 100644
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -24,6 +24,8 @@
+ #include <linux/perf_event.h>
+ 
+ #include <soc/rockchip/rockchip_grf.h>
++#include <soc/rockchip/rk3228_grf.h>
++#include <soc/rockchip/rk3328_grf.h>
+ #include <soc/rockchip/rk3399_grf.h>
+ #include <soc/rockchip/rk3568_grf.h>
+ #include <soc/rockchip/rk3588_grf.h>
+@@ -99,6 +101,7 @@ struct rockchip_dfi {
+ 
+ 	struct device *dev;
+ 	void __iomem *regs;
++	struct regmap *regmap_grf;
+ 	struct regmap *regmap_pmu;
+ 	struct clk *clk;
+ 	int usecount;
+@@ -669,6 +672,46 @@ static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
+ }
+ #endif
+ 
++static int rk3228_dfi_init(struct rockchip_dfi *dfi)
++{
++	u32 val;
++
++	regmap_read(dfi->regmap_grf, RK3228_GRF_OS_REG2, &val);
++	dfi->ddr_type = FIELD_GET(RK3228_GRF_OS_REG2_DDRTYPE, val);
++
++	dfi->channel_mask = GENMASK(0, 0);
++	dfi->max_channels = 1;
++
++	dfi->buswidth[0] = 2;  // 16 bit bus width
++
++	dfi->ddrmon_stride = 0x0;  // single channel controller
++	dfi->ddrmon_ctrl_single = true;
++
++	dfi->clk = NULL;
++
++	return 0;
++}
++
++static int rk3328_dfi_init(struct rockchip_dfi *dfi)
++{
++	u32 val;
++
++	regmap_read(dfi->regmap_grf, RK3328_GRF_OS_REG2, &val);
++	dfi->ddr_type = FIELD_GET(RK3328_GRF_OS_REG2_DDRTYPE, val);
++
++	dfi->channel_mask = GENMASK(0, 0);
++	dfi->max_channels = 1;
++
++	dfi->buswidth[0] = 2;  // 16 bit bus width
++
++	dfi->ddrmon_stride = 0x0;  // single channel controller
++	dfi->ddrmon_ctrl_single = true;
++
++	dfi->clk = NULL;
++
++	return 0;
++}
++
+ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
+ {
+ 	struct regmap *regmap_pmu = dfi->regmap_pmu;
+@@ -757,6 +800,8 @@ static int rk3588_dfi_init(struct rockchip_dfi *dfi)
+ };
+ 
+ static const struct of_device_id rockchip_dfi_id_match[] = {
++	{ .compatible = "rockchip,rk3228-dfi", .data = rk3228_dfi_init },
++	{ .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
+ 	{ .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
+ 	{ .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
+ 	{ .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
+@@ -786,14 +831,30 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
+ 	if (IS_ERR(dfi->regs))
+ 		return PTR_ERR(dfi->regs);
+ 
+-	node = of_parse_phandle(np, "rockchip,pmu", 0);
+-	if (!node)
+-		return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
++	if (soc_init == rk3228_dfi_init ||
++	    soc_init == rk3328_dfi_init) {
++		node = of_parse_phandle(np, "rockchip,grf", 0);
++		if (!node)
++			return dev_err_probe(&pdev->dev, -ENODEV, "Can't find grf registers");
+ 
+-	dfi->regmap_pmu = syscon_node_to_regmap(node);
+-	of_node_put(node);
+-	if (IS_ERR(dfi->regmap_pmu))
+-		return PTR_ERR(dfi->regmap_pmu);
++		dfi->regmap_grf = syscon_node_to_regmap(node);
++		of_node_put(node);
++		if (IS_ERR(dfi->regmap_grf))
++			return PTR_ERR(dfi->regmap_grf);
++	}
++
++	if (soc_init == rk3399_dfi_init ||
++	    soc_init == rk3568_dfi_init ||
++	    soc_init == rk3588_dfi_init) {
++		node = of_parse_phandle(np, "rockchip,pmu", 0);
++		if (!node)
++			return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
++
++		dfi->regmap_pmu = syscon_node_to_regmap(node);
++		of_node_put(node);
++		if (IS_ERR(dfi->regmap_pmu))
++			return PTR_ERR(dfi->regmap_pmu);
++	}
+ 
+ 	dfi->dev = dev;
+ 	mutex_init(&dfi->mutex);
+@@ -818,6 +879,8 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
++	dev_notice(dfi->dev, "dfi initialized, dram type: 0x%x, channels: %d\n", dfi->ddr_type, dfi->max_channels);
++
+ 	platform_set_drvdata(pdev, dfi);
+ 
+ 	return 0;
+diff --git a/include/soc/rockchip/rk3228_grf.h b/include/soc/rockchip/rk3228_grf.h
+new file mode 100644
+index 000000000000..e37406814fad
+--- /dev/null
++++ b/include/soc/rockchip/rk3228_grf.h
+@@ -0,0 +1,14 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Rockchip General Register Files definitions for RK3228
++ *
++ * Author: Paolo Sabatino <paolo.sabatino@gmail.com>
++ */
++
++#ifndef __SOC_RK3228_GRF_H
++#define __SOC_RK3228_GRF_H
++
++#define RK3228_GRF_OS_REG2		0x5d0
++#define RK3228_GRF_OS_REG2_DDRTYPE	GENMASK(15, 13)
++
++#endif
+diff --git a/include/soc/rockchip/rk3328_grf.h b/include/soc/rockchip/rk3328_grf.h
+new file mode 100644
+index 000000000000..bf6d209be7e6
+--- /dev/null
++++ b/include/soc/rockchip/rk3328_grf.h
+@@ -0,0 +1,14 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Rockchip General Register Files definitions for RK3328
++ *
++ * Author: Paolo Sabatino <paolo.sabatino@gmail.com>
++ */
++
++#ifndef __SOC_RK3328_GRF_H
++#define __SOC_RK3328_GRF_H
++
++#define RK3328_GRF_OS_REG2		0x5d0
++#define RK3328_GRF_OS_REG2_DDRTYPE	GENMASK(15, 13)
++
++#endif
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-04-driver.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-04-driver.patch
new file mode 100644
index 000000000000..3dfa3754e56d
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dmc-driver-04-driver.patch
@@ -0,0 +1,1155 @@
+From 8529e1141bf84ff4e0120eeb42e45a59c8e666c7 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Wed, 27 Dec 2023 15:29:29 +0100
+Subject: [PATCH] rockchip: add rk3228 dmc driver
+
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi       |  70 +-
+ drivers/devfreq/Kconfig                      |  12 +
+ drivers/devfreq/Makefile                     |   1 +
+ drivers/devfreq/rk3228_dmc.c                 | 696 +++++++++++++++++++
+ include/dt-bindings/clock/rockchip-ddr.h     |  63 ++
+ include/dt-bindings/memory/rockchip,rk322x.h |  90 +++
+ 6 files changed, 929 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/devfreq/rk3228_dmc.c
+ create mode 100644 include/dt-bindings/clock/rockchip-ddr.h
+ create mode 100644 include/dt-bindings/memory/rockchip,rk322x.h
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 41374aff62c8..c9d71a776587 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -7,6 +7,8 @@
+ #include <dt-bindings/clock/rk3228-cru.h>
+ #include <dt-bindings/thermal/thermal.h>
+ #include <dt-bindings/power/rk3228-power.h>
++#include <dt-bindings/clock/rockchip-ddr.h>
++#include <dt-bindings/memory/rockchip,rk322x.h>
+ 
+ / {
+ 	#address-cells = <1>;
+@@ -104,6 +106,68 @@ dfi: dfi@11210000 {
+ 		status = "okay";
+ 	};
+ 
++	dmc: dmc@11200000 {
++		compatible = "rockchip,rk3228-dmc", "rockchip,rk322x-dram";
++		reg = <0x11200000 0x400>;
++		clocks = <&cru SCLK_DDRCLK>;
++		clock-names = "ddr_sclk";
++		operating-points-v2 = <&dmc_opp_table>;
++		rockchip,dram_timing = <&dram_timing>;
++		rockchip,grf = <&grf>;
++		devfreq-events = <&dfi>;
++		upthreshold = <15>;
++		downdifferential = <10>;
++		#cooling-cells = <2>;
++		status = "disabled";
++	};
++
++	dmc_opp_table: dmc-opp-table {
++		compatible = "operating-points-v2";
++
++		opp-330000000 {
++			opp-hz = /bits/ 64 <330000000>;
++			opp-microvolt = <1050000 1000000 1200000>;
++		};
++		opp-534000000 {
++			opp-hz = /bits/ 64 <534000000>;
++			opp-microvolt = <1050000 1000000 1200000>;
++		};
++		opp-660000000 {
++			opp-hz = /bits/ 64 <660000000>;
++			opp-microvolt = <1100000 1000000 1200000>;
++		};
++		opp-786000000 {
++			opp-hz = /bits/ 64 <786000000>;
++			opp-microvolt = <1150000 1000000 1200000>;
++			status = "disabled";
++		};
++	};
++
++	dram_timing: dram-timing {
++		compatible = "rockchip,dram-timing";
++		dram_spd_bin = <DDR3_DEFAULT>;
++		sr_idle = <0x18>;
++		pd_idle = <0x20>;
++		dram_dll_disb_freq = <300>;
++		phy_dll_disb_freq = <400>;
++		dram_odt_disb_freq = <333>;
++		phy_odt_disb_freq = <333>;
++		ddr3_drv = <DDR3_DS_40ohm>;
++		ddr3_odt = <DDR3_ODT_120ohm>;
++		lpddr3_drv = <LP3_DS_34ohm>;
++		lpddr3_odt = <LP3_ODT_240ohm>;
++		lpddr2_drv = <LP2_DS_34ohm>;
++		/* lpddr2 not supported odt */
++		phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_45ohm>;
++		phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_45ohm>;
++		phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_34ohm>;
++		phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
++		phy_lp23_clk_drv = <PHY_LP23_RON_RTT_43ohm>;
++		phy_lp23_cmd_drv = <PHY_LP23_RON_RTT_34ohm>;
++		phy_lp23_dqs_drv = <PHY_LP23_RON_RTT_34ohm>;
++		phy_lp3_odt = <PHY_LP23_RON_RTT_240ohm>;
++	};
++
+ 	arm-pmu {
+ 		compatible = "arm,cortex-a7-pmu";
+ 		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+@@ -676,17 +740,17 @@ gpu_opp_table: opp-table2 {
+ 
+ 		opp-200000000 {
+ 			opp-hz = /bits/ 64 <200000000>;
+-			opp-microvolt = <1050000>;
++			opp-microvolt = <1050000 1000000 1200000>;
+ 		};
+ 
+ 		opp-300000000 {
+ 			opp-hz = /bits/ 64 <300000000>;
+-			opp-microvolt = <1050000>;
++			opp-microvolt = <1050000 1000000 1200000>;
+ 		};
+ 
+ 		opp-500000000 {
+ 			opp-hz = /bits/ 64 <500000000>;
+-			opp-microvolt = <1150000>;
++			opp-microvolt = <1150000 1000000 1200000>;
+ 		};
+ 	};
+ 
+diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
+index 3c4862a752b5..066be239a16a 100644
+--- a/drivers/devfreq/Kconfig
++++ b/drivers/devfreq/Kconfig
+@@ -129,6 +129,18 @@ config ARM_MEDIATEK_CCI_DEVFREQ
+ 	  buck voltages and update a proper CCI frequency. Use the notification
+ 	  to get the regulator status.
+ 
++config ARM_RK3228_DMC_DEVFREQ
++	tristate "ARM RK3228 DMC DEVFREQ Driver"
++	depends on ARCH_ROCKCHIP
++	select DEVFREQ_EVENT_ROCKCHIP_DFI
++	select DEVFREQ_GOV_SIMPLE_ONDEMAND
++	select PM_DEVFREQ_EVENT
++	select PM_OPP
++	help
++	  This adds the DEVFREQ driver for the RK3228 DMC(Dynamic Memory Controller).
++	  It sets the frequency for the memory controller and reads the usage counts
++	  from hardware.
++
+ config ARM_RK3399_DMC_DEVFREQ
+ 	tristate "ARM RK3399 DMC DEVFREQ Driver"
+ 	depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
+diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
+index bf40d04928d0..059712bfe5f5 100644
+--- a/drivers/devfreq/Makefile
++++ b/drivers/devfreq/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ)	+= imx-bus.o
+ obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ)	+= imx8m-ddrc.o
+ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ)	+= mtk-cci-devfreq.o
+ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)	+= rk3399_dmc.o
++obj-$(CONFIG_ARM_RK3228_DMC_DEVFREQ)	+= rk3228_dmc.o
+ obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)	+= sun8i-a33-mbus.o
+ obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra30-devfreq.o
+ 
+diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h
+new file mode 100644
+index 000000000000..b065432e7793
+--- /dev/null
++++ b/include/dt-bindings/clock/rockchip-ddr.h
+@@ -0,0 +1,63 @@
++/*
++ *
++ * Copyright (C) 2017 ROCKCHIP, Inc.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
++#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
++
++#define DDR2_DEFAULT	(0)
++
++#define DDR3_800D	(0)	/* 5-5-5 */
++#define DDR3_800E	(1)	/* 6-6-6 */
++#define DDR3_1066E	(2)	/* 6-6-6 */
++#define DDR3_1066F	(3)	/* 7-7-7 */
++#define DDR3_1066G	(4)	/* 8-8-8 */
++#define DDR3_1333F	(5)	/* 7-7-7 */
++#define DDR3_1333G	(6)	/* 8-8-8 */
++#define DDR3_1333H	(7)	/* 9-9-9 */
++#define DDR3_1333J	(8)	/* 10-10-10 */
++#define DDR3_1600G	(9)	/* 8-8-8 */
++#define DDR3_1600H	(10)	/* 9-9-9 */
++#define DDR3_1600J	(11)	/* 10-10-10 */
++#define DDR3_1600K	(12)	/* 11-11-11 */
++#define DDR3_1866J	(13)	/* 10-10-10 */
++#define DDR3_1866K	(14)	/* 11-11-11 */
++#define DDR3_1866L	(15)	/* 12-12-12 */
++#define DDR3_1866M	(16)	/* 13-13-13 */
++#define DDR3_2133K	(17)	/* 11-11-11 */
++#define DDR3_2133L	(18)	/* 12-12-12 */
++#define DDR3_2133M	(19)	/* 13-13-13 */
++#define DDR3_2133N	(20)	/* 14-14-14 */
++#define DDR3_DEFAULT	(21)
++#define DDR_DDR2	(22)
++#define DDR_LPDDR	(23)
++#define DDR_LPDDR2	(24)
++
++#define DDR4_1600J	(0)	/* 10-10-10 */
++#define DDR4_1600K	(1)	/* 11-11-11 */
++#define DDR4_1600L	(2)	/* 12-12-12 */
++#define DDR4_1866L	(3)	/* 12-12-12 */
++#define DDR4_1866M	(4)	/* 13-13-13 */
++#define DDR4_1866N	(5)	/* 14-14-14 */
++#define DDR4_2133N	(6)	/* 14-14-14 */
++#define DDR4_2133P	(7)	/* 15-15-15 */
++#define DDR4_2133R	(8)	/* 16-16-16 */
++#define DDR4_2400P	(9)	/* 15-15-15 */
++#define DDR4_2400R	(10)	/* 16-16-16 */
++#define DDR4_2400U	(11)	/* 18-18-18 */
++#define DDR4_DEFAULT	(12)
++
++#define PAUSE_CPU_STACK_SIZE	16
++
++#endif
+diff --git a/include/dt-bindings/memory/rockchip,rk322x.h b/include/dt-bindings/memory/rockchip,rk322x.h
+new file mode 100644
+index 000000000000..1ab3317d700e
+--- /dev/null
++++ b/include/dt-bindings/memory/rockchip,rk322x.h
+@@ -0,0 +1,90 @@
++/*
++ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H
++#define _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H
++
++#define DDR3_DS_34ohm		(1 << 1)
++#define DDR3_DS_40ohm		(0x0)
++
++#define LP2_DS_34ohm		(0x1)
++#define LP2_DS_40ohm		(0x2)
++#define LP2_DS_48ohm		(0x3)
++#define LP2_DS_60ohm		(0x4)
++#define LP2_DS_68_6ohm		(0x5)/* optional */
++#define LP2_DS_80ohm		(0x6)
++#define LP2_DS_120ohm		(0x7)/* optional */
++
++#define LP3_DS_34ohm		(0x1)
++#define LP3_DS_40ohm		(0x2)
++#define LP3_DS_48ohm		(0x3)
++#define LP3_DS_60ohm		(0x4)
++#define LP3_DS_80ohm		(0x6)
++#define LP3_DS_34D_40U		(0x9)
++#define LP3_DS_40D_48U		(0xa)
++#define LP3_DS_34D_48U		(0xb)
++
++#define DDR3_ODT_DIS		(0)
++#define DDR3_ODT_40ohm		((1 << 2) | (1 << 6))
++#define DDR3_ODT_60ohm		(1 << 2)
++#define DDR3_ODT_120ohm		(1 << 6)
++
++#define LP3_ODT_DIS		(0)
++#define LP3_ODT_60ohm		(1)
++#define LP3_ODT_120ohm		(2)
++#define LP3_ODT_240ohm		(3)
++
++#define PHY_DDR3_RON_RTT_DISABLE	(0)
++#define PHY_DDR3_RON_RTT_451ohm		(1)
++#define PHY_DDR3_RON_RTT_225ohm		(2)
++#define PHY_DDR3_RON_RTT_150ohm		(3)
++#define PHY_DDR3_RON_RTT_112ohm		(4)
++#define PHY_DDR3_RON_RTT_90ohm		(5)
++#define PHY_DDR3_RON_RTT_75ohm		(6)
++#define PHY_DDR3_RON_RTT_64ohm		(7)
++#define PHY_DDR3_RON_RTT_56ohm		(16)
++#define PHY_DDR3_RON_RTT_50ohm		(17)
++#define PHY_DDR3_RON_RTT_45ohm		(18)
++#define PHY_DDR3_RON_RTT_41ohm		(19)
++#define PHY_DDR3_RON_RTT_37ohm		(20)
++#define PHY_DDR3_RON_RTT_34ohm		(21)
++#define PHY_DDR3_RON_RTT_33ohm		(22)
++#define PHY_DDR3_RON_RTT_30ohm		(23)
++#define PHY_DDR3_RON_RTT_28ohm		(24)
++#define PHY_DDR3_RON_RTT_26ohm		(25)
++#define PHY_DDR3_RON_RTT_25ohm		(26)
++#define PHY_DDR3_RON_RTT_23ohm		(27)
++#define PHY_DDR3_RON_RTT_22ohm		(28)
++#define PHY_DDR3_RON_RTT_21ohm		(29)
++#define PHY_DDR3_RON_RTT_20ohm		(30)
++#define PHY_DDR3_RON_RTT_19ohm		(31)
++
++#define PHY_LP23_RON_RTT_DISABLE	(0)
++#define PHY_LP23_RON_RTT_480ohm		(1)
++#define PHY_LP23_RON_RTT_240ohm		(2)
++#define PHY_LP23_RON_RTT_160ohm		(3)
++#define PHY_LP23_RON_RTT_120ohm		(4)
++#define PHY_LP23_RON_RTT_96ohm		(5)
++#define PHY_LP23_RON_RTT_80ohm		(6)
++#define PHY_LP23_RON_RTT_68ohm		(7)
++#define PHY_LP23_RON_RTT_60ohm		(16)
++#define PHY_LP23_RON_RTT_53ohm		(17)
++#define PHY_LP23_RON_RTT_48ohm		(18)
++#define PHY_LP23_RON_RTT_43ohm		(19)
++#define PHY_LP23_RON_RTT_40ohm		(20)
++#define PHY_LP23_RON_RTT_37ohm		(21)
++#define PHY_LP23_RON_RTT_34ohm		(22)
++#define PHY_LP23_RON_RTT_32ohm		(23)
++#define PHY_LP23_RON_RTT_30ohm		(24)
++#define PHY_LP23_RON_RTT_28ohm		(25)
++#define PHY_LP23_RON_RTT_26ohm		(26)
++#define PHY_LP23_RON_RTT_25ohm		(27)
++#define PHY_LP23_RON_RTT_24ohm		(28)
++#define PHY_LP23_RON_RTT_22ohm		(29)
++#define PHY_LP23_RON_RTT_21ohm		(30)
++#define PHY_LP23_RON_RTT_20ohm		(31)
++
++#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H */
+diff --git a/drivers/devfreq/rk3228_dmc.c b/drivers/devfreq/rk3228_dmc.c
+new file mode 100644
+index 000000000000..1dbf53043f69
+--- /dev/null
++++ b/drivers/devfreq/rk3228_dmc.c
+@@ -0,0 +1,827 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
++ * Author: Lin Huang <hl@rock-chips.com>
++ */
++
++#include <linux/arm-smccc.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/devfreq.h>
++#include <linux/devfreq-event.h>
++#include <linux/devfreq_cooling.h>
++#include <linux/interrupt.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_opp.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++#include <linux/rwsem.h>
++#include <linux/suspend.h>
++
++#include <soc/rockchip/rockchip_sip.h>
++
++#define DTS_PAR_OFFSET		(4096)
++
++#define RK3228_GRF_OS_REG2	0x5d0
++#define DDR_PCTL_MCFG		0x80
++#define DDR_PCTL_TCL		0xe8
++#define DDR_PCTL_TRAS		0xf0
++#define DDR_PCTL_TRCD		0xf8
++#define DDR_PCTL_TRP		0xdc
++
++/* MCFG */
++#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT	24
++#define PD_IDLE_SHIFT			8
++#define MDDR_EN				(2 << 22)
++#define LPDDR2_EN			(3 << 22)
++#define LPDDR3_EN			(1 << 22)
++#define DDR2_EN				(0 << 5)
++#define DDR3_EN				(1 << 5)
++#define LPDDR2_S2			(0 << 6)
++#define LPDDR2_S4			(1 << 6)
++#define MDDR_LPDDR2_BL_2		(0 << 20)
++#define MDDR_LPDDR2_BL_4		(1 << 20)
++#define MDDR_LPDDR2_BL_8		(2 << 20)
++#define MDDR_LPDDR2_BL_16		(3 << 20)
++#define DDR2_DDR3_BL_4			0
++#define DDR2_DDR3_BL_8			1
++#define TFAW_SHIFT			18
++#define PD_EXIT_SLOW			(0 << 17)
++#define PD_EXIT_FAST			(1 << 17)
++#define PD_TYPE_SHIFT			16
++#define BURSTLENGTH_SHIFT		20
++
++#define MCFG_CR_2T_BIT(x)		((x & (1 << 3)) >> 3)
++#define MCFG_DDR_MASK			0x60
++#define MCFG_DDR_SHIFT			5
++#define MCFG_LPDDR_MASK			0xC00000
++#define MCFG_LPDDR_SHIFT		22
++
++#define MCFG_LPDDR2_S2			0x0
++#define MCFG_DDR3			0x1
++#define MCFG_LPDDR2_S4			0x2
++
++#define READ_DRAMTYPE_INFO(n)	(((n) >> 13) & 0x7)
++
++enum {
++	DDR4 = 0,
++	DDR2 = 2,
++	DDR3 = 3,
++	LPDDR2 = 5,
++	LPDDR3 = 6,
++	LPDDR4 = 7,
++	UNUSED = 0xFF
++};
++
++struct share_params {
++	u32 hz;
++	u32 lcdc_type;
++	u32 vop;
++	u32 vop_dclk_mode;
++	u32 sr_idle_en;
++	u32 addr_mcu_el3;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag1;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag0;
++	u32 complt_hwirq;
++	/* if need, add parameter after */
++};
++
++static struct share_params *ddr_psci_param = NULL;
++
++static const char * const rk3228_dts_timing[] = {
++	"dram_spd_bin",
++	"sr_idle",
++	"pd_idle",
++	"dram_dll_disb_freq",
++	"phy_dll_disb_freq",
++	"dram_odt_disb_freq",
++	"phy_odt_disb_freq",
++	"ddr3_drv",
++	"ddr3_odt",
++	"lpddr3_drv",
++	"lpddr3_odt",
++	"lpddr2_drv",
++	"phy_ddr3_clk_drv",
++	"phy_ddr3_cmd_drv",
++	"phy_ddr3_dqs_drv",
++	"phy_ddr3_odt",
++	"phy_lp23_clk_drv",
++	"phy_lp23_cmd_drv",
++	"phy_lp23_dqs_drv",
++	"phy_lp3_odt"
++};
++
++struct rk3228_ddr_dts_config_timing {
++	u32 dram_spd_bin;
++	u32 sr_idle;
++	u32 pd_idle;
++	u32 dram_dll_dis_freq;
++	u32 phy_dll_dis_freq;
++	u32 dram_odt_dis_freq;
++	u32 phy_odt_dis_freq;
++	u32 ddr3_drv;
++	u32 ddr3_odt;
++	u32 lpddr3_drv;
++	u32 lpddr3_odt;
++	u32 lpddr2_drv;
++	u32 phy_ddr3_clk_drv;
++	u32 phy_ddr3_cmd_drv;
++	u32 phy_ddr3_dqs_drv;
++	u32 phy_ddr3_odt;
++	u32 phy_lp23_clk_drv;
++	u32 phy_lp23_cmd_drv;
++	u32 phy_lp23_dqs_drv;
++	u32 phy_lp3_odt;
++};
++
++struct rk3228_devfreq {
++	struct devfreq *devfreq;
++	struct thermal_cooling_device *cooling;
++};
++
++struct rk3228_dmc {
++	struct device *dev;
++	void __iomem *iomem;
++
++	int rate;
++	struct devfreq_simple_ondemand_data ondemand_data;
++	struct devfreq_event_dev *edev;
++	struct clk *dmc_clk;
++	struct rk3228_devfreq devfreq;
++	u32 load;
++
++	uint32_t dram_type;
++
++	//struct mutex lock;
++
++	int (*set_auto_self_refresh)(u32 en);
++};
++
++static uint32_t of_get_rk3228_timings(struct device *dev,
++				      struct device_node *np, uint32_t *timing)
++{
++	struct device_node *np_tim;
++	uint32_t offset;
++	int ret = 0;
++	u32 idx;
++
++	// first 4kb page is reserved for interface parameters, we calculate an offset
++	// after which the timing parameters start
++	offset = DTS_PAR_OFFSET / sizeof(uint32_t);
++
++	np_tim = of_parse_phandle(np, "rockchip,dram_timing", 0);
++
++	if (!np_tim) {
++		ret = -EINVAL;
++		goto end;
++	}
++
++	for (idx = 0; idx < ARRAY_SIZE(rk3228_dts_timing); idx++)
++		ret |= of_property_read_u32(np_tim, rk3228_dts_timing[idx], &timing[offset + idx]);
++
++end:
++	if (ret)
++		dev_err(dev, "of_get_ddr_timings: fail\n");
++
++	of_node_put(np_tim);
++
++	return ret;
++
++}
++
++static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
++{
++	struct arm_smccc_res res;
++
++	ddr_psci_param->sr_idle_en = en;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR,
++		      0, 0, 0, 0, &res);
++
++	return res.a0;
++}
++
++static int rk3228_dmc_init_sip(void)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(ROCKCHIP_SIP_SIP_VERSION, ROCKCHIP_SIP_IMPLEMENT_V2, SECURE_REG_WR, 0, 0, 0, 0, 0, &res);
++
++	if (res.a0)
++		return 0;
++
++	return res.a1;
++
++}
++
++static int rk3228_dmc_target(struct device *dev, unsigned long *freq,
++				 u32 flags)
++{
++
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++	struct dev_pm_opp *opp;
++	int err;
++
++	opp = devfreq_recommended_opp(dev, freq, flags);
++	if (IS_ERR(opp))
++		return PTR_ERR(opp);
++	dev_pm_opp_put(opp);
++
++	err = dev_pm_opp_set_rate(dev, *freq);
++	if (err)
++		return err;
++
++	rdev->rate = *freq;
++
++	return 0;
++
++}
++
++static int rk3228_dmc_get_dev_status(struct device *dev,
++					 struct devfreq_dev_status *stat)
++{
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++	struct devfreq_event_data edata;
++	int ret = 0;
++
++	ret = devfreq_event_get_event(rdev->edev, &edata);
++	if (ret < 0)
++		return ret;
++
++	stat->current_frequency = rdev->rate;
++	stat->busy_time = edata.load_count;
++	stat->total_time = edata.total_count;
++	rdev->load = (edata.load_count * 100) / edata.total_count;
++
++	return ret;
++}
++
++static int rk3228_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
++{
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++
++	*freq = rdev->rate;
++
++	return 0;
++}
++
++static struct devfreq_dev_profile rk3228_devfreq_profile = {
++	.polling_ms	= 50,
++	.target		= rk3228_dmc_target,
++	.get_dev_status	= rk3228_dmc_get_dev_status,
++	.get_cur_freq	= rk3228_dmc_get_cur_freq,
++};
++
++void rk3228_devfreq_fini(struct rk3228_dmc *rdev)
++{
++	struct rk3228_devfreq *devfreq = &rdev->devfreq;
++
++	if (devfreq->cooling) {
++		devfreq_cooling_unregister(devfreq->cooling);
++		devfreq->cooling = NULL;
++	}
++
++	if (devfreq->devfreq) {
++		devm_devfreq_remove_device(rdev->dev, devfreq->devfreq);
++		devfreq->devfreq = NULL;
++	}
++
++}
++
++int rk3228_devfreq_init(struct rk3228_dmc *rdev)
++{
++	struct thermal_cooling_device *cooling;
++	struct device *dev = rdev->dev;
++	struct devfreq *devfreq;
++	struct rk3228_devfreq *rdevfreq = &rdev->devfreq;
++	const char *regulator_names[] = { "logic", NULL };
++
++	struct dev_pm_opp *opp;
++	unsigned long cur_freq;
++	int ret;
++
++	if (!device_property_present(dev, "operating-points-v2"))
++		/* Optional, continue without devfreq */
++		return 0;
++
++	ret = devm_pm_opp_set_clkname(dev, "ddr_sclk");
++	if (ret)
++		goto err_fini;
++
++	ret = devm_pm_opp_set_regulators(dev, regulator_names);
++
++	/* Continue if the optional regulator is missing */
++	if (ret && ret != -ENODEV)
++		goto err_fini;
++
++	ret = devm_pm_opp_of_add_table(dev);
++	if (ret)
++		goto err_fini;
++
++	cur_freq = 0;
++
++	opp = devfreq_recommended_opp(dev, &cur_freq, 0);
++	if (IS_ERR(opp)) {
++		ret = PTR_ERR(opp);
++		goto err_fini;
++	}
++
++	rk3228_devfreq_profile.initial_freq = cur_freq;
++	dev_pm_opp_put(opp);
++
++	rdev->ondemand_data.upthreshold = 30;
++	rdev->ondemand_data.downdifferential = 5;
++
++	devfreq = devm_devfreq_add_device(dev, &rk3228_devfreq_profile,
++					  DEVFREQ_GOV_SIMPLE_ONDEMAND, &rdev->ondemand_data);
++	if (IS_ERR(devfreq)) {
++		dev_err(dev, "Couldn't initialize GPU devfreq\n");
++		ret = PTR_ERR(devfreq);
++		goto err_fini;
++	}
++
++	rdevfreq->devfreq = devfreq;
++
++	cooling = of_devfreq_cooling_register(dev->of_node, devfreq);
++	if (IS_ERR(cooling))
++		dev_warn(dev, "Failed to register cooling device\n");
++	else
++		rdevfreq->cooling = cooling;
++
++	return 0;
++
++err_fini:
++	rk3228_devfreq_fini(rdev);
++	return ret;
++}
++
++static int rk3228_dmc_init(struct platform_device *pdev,
++			   struct rk3228_dmc *rdev)
++{
++	struct arm_smccc_res res;
++	u32 page_num;
++
++	// Count of pages to request to trust os, in pages of 4kb
++	page_num = DIV_ROUND_UP(sizeof(struct rk3228_ddr_dts_config_timing), PAGE_SIZE) + 1;
++
++	dev_dbg(&pdev->dev, "trying to allocate %d pages\n", page_num);
++
++	// Do request to trust OS. res.a0 contains error code, res.a1 the *physical*
++	// initial location of pages
++	arm_smccc_smc(
++		ROCKCHIP_SIP_SHARE_MEM,
++		page_num, SHARE_PAGE_TYPE_DDR, 0,
++		0, 0, 0, 0, &res
++	);
++
++	if (res.a0) {
++		dev_err(&pdev->dev, "no ATF memory for init\n");
++		return -ENOMEM;
++	}
++
++	dev_dbg(&pdev->dev, "allocated %d shared memory pages\n", page_num);
++
++	// Remap the physical location to kernel space using ioremap
++	ddr_psci_param = (struct share_params *)ioremap(res.a1, page_num << PAGE_SHIFT);
++
++	if (of_get_rk3228_timings(&pdev->dev, pdev->dev.of_node,
++				  (uint32_t *)ddr_psci_param))
++		return -ENOMEM;
++
++	// Reset Hz value
++	ddr_psci_param->hz = 0;
++
++	arm_smccc_smc(
++		ROCKCHIP_SIP_DRAM_FREQ,
++		SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT,
++		0, 0, 0, 0, &res
++	);
++
++	if (res.a0) {
++		dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
++			res.a0);
++		return -EINVAL;
++	}
++
++	dev_notice(&pdev->dev, "TEE DRAM configuration initialized\n");
++
++	rdev->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
++
++	return 0;
++
++}
++
++static __maybe_unused int rk3228_dmc_suspend(struct device *dev)
++{
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++	int ret = 0;
++
++	ret = devfreq_event_disable_edev(rdev->edev);
++	if (ret < 0) {
++		dev_err(dev, "failed to disable the devfreq-event devices\n");
++		return ret;
++	}
++
++	ret = devfreq_suspend_device(rdev->devfreq.devfreq);
++	if (ret < 0) {
++		dev_err(dev, "failed to suspend the devfreq devices\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static __maybe_unused int rk3228_dmc_resume(struct device *dev)
++{
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++	int ret = 0;
++
++	ret = devfreq_event_enable_edev(rdev->edev);
++	if (ret < 0) {
++		dev_err(dev, "failed to enable the devfreq-event devices\n");
++		return ret;
++	}
++
++	ret = devfreq_resume_device(rdev->devfreq.devfreq);
++	if (ret < 0) {
++		dev_err(dev, "failed to resume the devfreq devices\n");
++		return ret;
++	}
++	return ret;
++}
++
++static uint32_t rk3228_get_dram_type(struct device *dev, struct device_node *node_grf, struct rk3228_dmc *data)
++{
++
++	struct regmap *regmap_grf;
++	uint32_t dram_type;
++	uint32_t val;
++
++	dram_type = UNUSED;
++
++	regmap_grf = syscon_node_to_regmap(node_grf);
++
++	if (IS_ERR(regmap_grf)) {
++		dev_err(dev, "Cannot map rockchip,grf\n");
++		goto err;
++	}
++
++	regmap_read(regmap_grf, RK3228_GRF_OS_REG2, &val);
++	dram_type = READ_DRAMTYPE_INFO(val);
++
++err:
++
++	return dram_type;
++
++}
++
++static SIMPLE_DEV_PM_OPS(rk3228_dmc_pm, rk3228_dmc_suspend,
++			 rk3228_dmc_resume);
++
++static int rk3328_dmc_print_info(struct rk3228_dmc *rdev)
++{
++
++	u32 tcl;
++	u32 tras;
++	u32 trp;
++	u32 trcd;
++
++	u32 mcfg;
++	// u32 reg_ddr_type1;
++	// u32 reg_ddr_type2;
++
++	u32 cr;
++
++	const char * const cr_types[] = {
++		"1T",
++		"2T"
++	};
++
++
++	tcl = readl(rdev->iomem + DDR_PCTL_TCL) & 0xf;
++	tras = readl(rdev->iomem + DDR_PCTL_TRAS) & 0x3f;
++	trp = readl(rdev->iomem + DDR_PCTL_TRP) & 0xf;
++	trcd = readl(rdev->iomem + DDR_PCTL_TRCD) & 0xf;
++
++	mcfg = readl(rdev->iomem + DDR_PCTL_MCFG);
++
++	cr = MCFG_CR_2T_BIT(mcfg);
++
++	dev_info(rdev->dev,
++		"Memory timings (tCL, tRCD, tRP, tRAS): CL%d-%d-%d-%d command rate: %s (mcfg register: 0x%x)\n",
++		tcl, trcd, trp, tras, cr_types[cr], mcfg);
++
++	return 0;
++
++}
++
++/**
++ * Callback to return the current load on DRAM in percentage exported via sysfs; see DEVICE_ATTR_RO(SYSFS_LOAD)
++ */
++#define SYSFS_LOAD	load
++static ssize_t load_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++
++	int ret;
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++
++	mutex_lock(&rdev->devfreq.devfreq->lock);
++
++	ret = sysfs_emit(buf, "%u", rdev->load);
++
++	mutex_unlock(&rdev->devfreq.devfreq->lock);
++
++	return ret;
++
++}
++static DEVICE_ATTR_RO(SYSFS_LOAD);
++
++#define SYSFS_UPTHRESHOLD upthreshold
++static ssize_t upthreshold_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++
++	int ret;
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++
++	mutex_lock(&rdev->devfreq.devfreq->lock);
++
++	ret = sysfs_emit(buf, "%u", rdev->ondemand_data.upthreshold);
++
++	mutex_unlock(&rdev->devfreq.devfreq->lock);
++
++	return ret;
++
++}
++
++static ssize_t upthreshold_store(struct device *dev, struct device_attribute *attr,
++				 const char *buf, size_t count)
++{
++
++	int ret;
++	u32 upthreshold;
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++
++	mutex_lock(&rdev->devfreq.devfreq->lock);
++
++	ret = kstrtouint(buf, 0, &upthreshold);
++
++	if (ret < 0)
++		goto out;
++
++	if (upthreshold > 100) {
++		ret = -EINVAL;
++		goto out;
++	}
++
++	rdev->ondemand_data.upthreshold = upthreshold;
++
++	ret = count;
++
++out:
++	mutex_unlock(&rdev->devfreq.devfreq->lock);
++
++	return ret;
++
++}
++static DEVICE_ATTR_RW(SYSFS_UPTHRESHOLD);
++
++#define SYSFS_DOWNDIFFERENTIAL downdifferential
++static ssize_t downdifferential_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++
++	int ret;
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++
++	mutex_lock(&rdev->devfreq.devfreq->lock);
++
++	ret = sysfs_emit(buf, "%u", rdev->ondemand_data.downdifferential);
++
++	mutex_unlock(&rdev->devfreq.devfreq->lock);
++
++	return ret;
++
++}
++
++static ssize_t downdifferential_store(struct device *dev, struct device_attribute *attr,
++				 const char *buf, size_t count)
++{
++
++	int ret;
++	u32 downdifferential;
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++
++	mutex_lock(&rdev->devfreq.devfreq->lock);
++
++	ret = kstrtouint(buf, 0, &downdifferential);
++
++	if (ret < 0)
++		goto out;
++
++	if (downdifferential > 100) {
++		ret = -EINVAL;
++		goto out;
++	}
++
++	rdev->ondemand_data.downdifferential = downdifferential;
++
++	ret = count;
++
++out:
++	mutex_unlock(&rdev->devfreq.devfreq->lock);
++
++	return ret;
++
++}
++static DEVICE_ATTR_RW(SYSFS_DOWNDIFFERENTIAL);
++
++static int rk3228_dmc_sysfs_create(struct device *dev)
++{
++
++	int ret;
++
++	ret = device_create_file(dev, &dev_attr_SYSFS_LOAD);
++	if (ret < 0)
++		goto out;
++
++	ret = device_create_file(dev, &dev_attr_SYSFS_UPTHRESHOLD);
++	if (ret < 0)
++		goto out;
++
++	ret = device_create_file(dev, &dev_attr_SYSFS_DOWNDIFFERENTIAL);
++	if (ret < 0)
++		goto out;
++
++out:
++	return ret;
++
++}
++
++static void rk3228_dmc_sysfs_remove(struct device *dev)
++{
++
++	device_remove_file(dev, &dev_attr_SYSFS_LOAD);
++	device_remove_file(dev, &dev_attr_SYSFS_UPTHRESHOLD);
++	device_remove_file(dev, &dev_attr_SYSFS_DOWNDIFFERENTIAL);
++
++}
++
++
++static int rk3228_dmc_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = pdev->dev.of_node;
++	struct rk3228_dmc *data;
++	struct device_node *node_grf;
++	int ret;
++
++	ret = rk3228_dmc_init_sip();
++	if (ret == 0) {
++		dev_err(dev, "Rockchip SIP initialization failed\n");
++		return -ENODEV;
++	}
++
++	dev_info(dev, "Rockchip SIP initialized, version %x\n", ret);
++
++	data = devm_kzalloc(dev, sizeof(struct rk3228_dmc), GFP_KERNEL);
++	if (!data)
++		return -ENOMEM;
++
++	data->dmc_clk = devm_clk_get(dev, "ddr_sclk");
++	if (IS_ERR(data->dmc_clk)) {
++		if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++
++		dev_err(dev, "Cannot get the clk dmc_clk\n");
++		return PTR_ERR(data->dmc_clk);
++	}
++
++	data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
++	if (IS_ERR(data->edev))
++		return -EPROBE_DEFER;
++
++	data->iomem = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(data->iomem)) {
++		dev_err(dev, "fail to ioremap iomem\n");
++		ret = PTR_ERR(data->iomem);
++		return ret;
++	}
++
++	data->dev = dev;
++
++	rk3328_dmc_print_info(data);
++
++	node_grf = of_parse_phandle(np, "rockchip,grf", 0);
++	if (node_grf) {
++
++		data->dram_type = rk3228_get_dram_type(dev, node_grf, data);
++
++		if (data->dram_type == LPDDR2) {
++			dev_warn(dev, "detected LPDDR2 memory\n");
++		} else if (data->dram_type == DDR2) {
++			dev_warn(dev, "detected DDR2 memory\n");
++		} else if (data->dram_type == DDR3) {
++			dev_info(dev, "detected DDR3 memory\n");
++		} else if (data->dram_type == LPDDR3) {
++			dev_info(dev, "detected LPDDR3 memory\n");
++		} else if (data->dram_type == DDR4) {
++			dev_info(dev, "detected DDR4 memory\n");
++		} else if (data->dram_type == LPDDR4) {
++			dev_info(dev, "detected LPDDR4 memory\n");
++		} else if (data->dram_type == UNUSED) {
++			dev_info(dev, "memory type not detected\n");
++		} else {
++			dev_info(dev, "unknown memory type: 0x%x\n", data->dram_type);
++		}
++
++	} else {
++
++		dev_warn(dev, "Cannot get rockchip,grf\n");
++		data->dram_type = UNUSED;
++
++	}
++
++	if (data->dram_type == DDR3 ||
++		data->dram_type == LPDDR3 ||
++		data->dram_type == DDR4 ||
++		data->dram_type == LPDDR4) {
++
++		ret = devfreq_event_enable_edev(data->edev);
++		if (ret < 0) {
++			dev_err(dev, "failed to enable devfreq-event devices\n");
++			return ret;
++		}
++
++		ret = rk3228_dmc_init(pdev, data);
++		if (ret)
++			return ret;
++
++		ret = rk3228_devfreq_init(data);
++		if (ret)
++			return ret;
++
++	} else {
++
++		dev_warn(dev, "detected memory type does not support clock scaling\n");
++
++	}
++
++	platform_set_drvdata(pdev, data);
++
++	ret = rk3228_dmc_sysfs_create(dev);
++	if (ret < 0)
++		dev_err(dev, "could not create sysfs interface files, ret=%d\n", ret);
++
++	return 0;
++
++}
++
++static int rk3228_dmc_remove(struct platform_device *pdev)
++{
++	struct rk3228_dmc *rdev = dev_get_drvdata(&pdev->dev);
++
++	rk3228_dmc_sysfs_remove(&pdev->dev);
++
++	/*
++	 * Before remove the opp table we need to unregister the opp notifier.
++	 */
++	rk3228_devfreq_fini(rdev);
++
++	if (ddr_psci_param)
++		iounmap(ddr_psci_param);
++
++	return 0;
++}
++
++static const struct of_device_id rk3228_dmc_of_match[] = {
++	{ .compatible = "rockchip,rk3228-dmc" },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, rk3228_dmc_of_match);
++
++static struct platform_driver rk3228_dmc_driver = {
++	.probe	= rk3228_dmc_probe,
++	.remove = rk3228_dmc_remove,
++	.driver = {
++		.name	= "rk3228-dmc",
++		.pm	= &rk3228_dmc_pm,
++		.of_match_table = rk3228_dmc_of_match,
++	},
++};
++module_platform_driver(rk3228_dmc_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
++MODULE_AUTHOR("Paolo Sabatino <paolo.sabatino@gmail.com>");
++MODULE_DESCRIPTION("RK3228 dmcfreq driver with devfreq framework");
+-- 
+2.34.1
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dwc2-no-clock-gating.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dwc2-no-clock-gating.patch
new file mode 100644
index 000000000000..1059c68868b2
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-dwc2-no-clock-gating.patch
@@ -0,0 +1,27 @@
+diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
+index 93f52e371cdd..fb135f62cf26 100644
+--- a/drivers/usb/dwc2/params.c
++++ b/drivers/usb/dwc2/params.c
+@@ -132,6 +132,14 @@ static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
+ 	p->hird_threshold_en = false;
+ }
+ 
++static void dwc2_set_rk3228_params(struct dwc2_hsotg *hsotg)
++{
++	struct dwc2_core_params *p = &hsotg->params;
++
++	dwc2_set_rk_params(hsotg);
++	p->no_clock_gating = true;
++}
++
+ static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
+ {
+ 	struct dwc2_core_params *p = &hsotg->params;
+@@ -277,6 +285,7 @@ const struct of_device_id dwc2_of_match_table[] = {
+ 	{ .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
+ 	{ .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
+ 	{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
++	{ .compatible = "rockchip,rk3228-usb", .data = dwc2_set_rk3228_params },
+ 	{ .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
+ 	{ .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
+ 	{ .compatible = "snps,dwc2" },
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-usb-reset-props.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-usb-reset-props.patch
new file mode 100644
index 000000000000..81deaa758e18
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/rk322x-usb-reset-props.patch
@@ -0,0 +1,75 @@
+From 6668d12fd4a628299ffbf89794b6f7f67416e3fa Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 4 May 2024 15:12:43 +0200
+Subject: [PATCH] add reset props to usb otg/ehci ports
+
+usb resets are needed in case u-boot does its own reset
+of the devices, otherwise ports are left in a
+non-functional state. Also fixes occasional missing
+device detection on the OTG port.
+
+In any case, when reset are present, the iddig filter
+wait time always times out, so we comment it as it
+looks unnecessary (the port works fine, the device is
+always detected also in case of timeout)
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi | 8 ++++++++
+ drivers/usb/dwc2/core.c                | 2 +-
+ 2 files changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 03d9baddcbab..17c5f0a8fcf3 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -807,6 +807,8 @@ usb_otg: usb@30040000 {
+ 		g-tx-fifo-size = <256 128 128 64 32 16>;
+ 		phys = <&u2phy0_otg>;
+ 		phy-names = "usb2-phy";
++		resets = <&cru SRST_USBOTG>;
++		reset-names = "dwc2";
+ 		status = "disabled";
+ 	};
+ 
+@@ -817,6 +819,8 @@ usb_host0_ehci: usb@30080000 {
+ 		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
+ 		phys = <&u2phy0_host>;
+ 		phy-names = "usb";
++		resets = <&cru SRST_USBHOST0>;
++		reset-names = "ehci";
+ 		status = "disabled";
+ 	};
+ 
+@@ -837,6 +841,8 @@ usb_host1_ehci: usb@300c0000 {
+ 		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
+ 		phys = <&u2phy1_otg>;
+ 		phy-names = "usb";
++		resets = <&cru SRST_USBHOST1>;
++		reset-names = "ehci";
+ 		status = "disabled";
+ 	};
+ 
+@@ -857,6 +863,8 @@ usb_host2_ehci: usb@30100000 {
+ 		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+ 		phys = <&u2phy1_host>;
+ 		phy-names = "usb";
++		resets = <&cru SRST_USBHOST2>;
++		reset-names = "ehci";
+ 		status = "disabled";
+ 	};
+ 
+diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
+index 5635e4d7ec88..1e20aabc2033 100644
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -413,7 +413,7 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
+ 
+ 		if (!(gotgctl & GOTGCTL_CONID_B) ||
+ 		    (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
+-			wait_for_host_mode = true;
++			wait_for_host_mode = false;
+ 		}
+ 	}
+ 
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch
new file mode 100644
index 000000000000..17b44a5f331f
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch
@@ -0,0 +1,102 @@
+FROM: Solidhal <hal@halemmerich.com>
+
+This patch reverses commit 2b721118b7821107757eb1d37af4b60e877b27e7, as can bee seen here:
+https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2b721118b7821107757eb1d37af4b60e877b27e7
+
+This commit caused issues on veyron speedy with ath9k and dwc2 drivers. Any ath9k device (ar9271) 
+would intermittently work, most of the time ending in errors as can bee seen here:
+https://github.com/SolidHal/PrawnOS/issues/38
+This commit fixes that issue.
+This is only a temporary work around while a permenant fix is found, as this commit seems to only cause issues
+with dwc2
+
+
+diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
+index 3f563e02d..903851481 100644
+--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
++++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
+@@ -118,10 +118,10 @@ static int hif_usb_send_regout(struct hif_device_usb *hif_dev,
+ 	cmd->skb = skb;
+ 	cmd->hif_dev = hif_dev;
+ 
+-	usb_fill_int_urb(urb, hif_dev->udev,
+-			 usb_sndintpipe(hif_dev->udev, USB_REG_OUT_PIPE),
++	usb_fill_bulk_urb(urb, hif_dev->udev,
++			 usb_sndbulkpipe(hif_dev->udev, USB_REG_OUT_PIPE),
+ 			 skb->data, skb->len,
+-			 hif_usb_regout_cb, cmd, 1);
++			 hif_usb_regout_cb, cmd);
+ 
+ 	usb_anchor_urb(urb, &hif_dev->regout_submitted);
+ 	ret = usb_submit_urb(urb, GFP_KERNEL);
+@@ -735,11 +735,11 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
+ 
+ 		rx_buf->skb = skb;
+ 
+-		usb_fill_int_urb(urb, hif_dev->udev,
+-				 usb_rcvintpipe(hif_dev->udev,
++		usb_fill_bulk_urb(urb, hif_dev->udev,
++				 usb_rcvbulkpipe(hif_dev->udev,
+ 						 USB_REG_IN_PIPE),
+ 				 skb->data, MAX_REG_IN_BUF_SIZE,
+-				 ath9k_hif_usb_reg_in_cb, rx_buf, 1);
++				 ath9k_hif_usb_reg_in_cb, rx_buf);
+ 	}
+ 
+ resubmit:
+@@ -944,11 +944,11 @@ static int ath9k_hif_usb_alloc_reg_in_urbs(struct hif_device_usb *hif_dev)
+ 		rx_buf->hif_dev = hif_dev;
+ 		rx_buf->skb = skb;
+ 
+-		usb_fill_int_urb(urb, hif_dev->udev,
+-				  usb_rcvintpipe(hif_dev->udev,
++		usb_fill_bulk_urb(urb, hif_dev->udev,
++				  usb_rcvbulkpipe(hif_dev->udev,
+ 						  USB_REG_IN_PIPE),
+ 				  skb->data, MAX_REG_IN_BUF_SIZE,
+-				  ath9k_hif_usb_reg_in_cb, rx_buf, 1);
++				  ath9k_hif_usb_reg_in_cb, skb);
+ 
+ 		/* Anchor URB */
+ 		usb_anchor_urb(urb, &hif_dev->reg_in_submitted);
+@@ -1069,7 +1069,9 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
+ 
+ static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
+ {
+-	int ret;
++	struct usb_host_interface *alt = &hif_dev->interface->altsetting[0];
++	struct usb_endpoint_descriptor *endp;
++	int ret, idx;
+ 
+ 	ret = ath9k_hif_usb_download_fw(hif_dev);
+ 	if (ret) {
+@@ -1079,6 +1081,20 @@ static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
+ 		return ret;
+ 	}
+ 
++	/* On downloading the firmware to the target, the USB descriptor of EP4
++	 * is 'patched' to change the type of the endpoint to Bulk. This will
++	 * bring down CPU usage during the scan period.
++	 */
++	for (idx = 0; idx < alt->desc.bNumEndpoints; idx++) {
++		endp = &alt->endpoint[idx].desc;
++		if ((endp->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
++				== USB_ENDPOINT_XFER_INT) {
++			endp->bmAttributes &= ~USB_ENDPOINT_XFERTYPE_MASK;
++			endp->bmAttributes |= USB_ENDPOINT_XFER_BULK;
++			endp->bInterval = 0;
++		}
++	}
++
+ 	/* Alloc URBs */
+ 	ret = ath9k_hif_usb_alloc_urbs(hif_dev);
+ 	if (ret) {
+@@ -1353,7 +1369,7 @@ static void ath9k_hif_usb_reboot(struct usb_device *udev)
+ 	if (!buf)
+ 		return;
+ 
+-	ret = usb_interrupt_msg(udev, usb_sndintpipe(udev, USB_REG_OUT_PIPE),
++	ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, USB_REG_OUT_PIPE),
+ 			   buf, 4, NULL, USB_MSG_TIMEOUT);
+ 	if (ret)
+ 		dev_err(&udev->dev, "ath9k_htc: USB reboot failed\n");
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-brcmfmac-add-bcm43342.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-brcmfmac-add-bcm43342.patch
new file mode 100644
index 000000000000..e0307dc9c54b
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-brcmfmac-add-bcm43342.patch
@@ -0,0 +1,45 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Thu, 10 Feb 2022 21:30:54 +0000
+Subject: add broadcom bcm43342 chip id
+
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c       | 2 ++
+ drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h | 1 +
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+index 6b38d9de71af..6a603d045103 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+@@ -609,6 +609,7 @@ BRCMF_FW_DEF(4329, "brcmfmac4329-sdio");
+ BRCMF_FW_DEF(4330, "brcmfmac4330-sdio");
+ BRCMF_FW_DEF(4334, "brcmfmac4334-sdio");
+ BRCMF_FW_DEF(43340, "brcmfmac43340-sdio");
++BRCMF_FW_DEF(43342, "brcmfmac43342-sdio");
+ BRCMF_FW_DEF(4335, "brcmfmac4335-sdio");
+ BRCMF_FW_DEF(43362, "brcmfmac43362-sdio");
+ BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
+@@ -642,6 +643,7 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
+ 	BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
++	BRCMF_FW_ENTRY(BRCM_CC_43342_CHIP_ID, 0xFFFFFFFF, 43342),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
+diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+index 44684bf1b9ac..bcf48de78d53 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
++++ b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+@@ -27,6 +27,7 @@
+ #define BRCM_CC_4334_CHIP_ID		0x4334
+ #define BRCM_CC_43340_CHIP_ID		43340
+ #define BRCM_CC_43341_CHIP_ID		43341
++#define BRCM_CC_43342_CHIP_ID		43342
+ #define BRCM_CC_43362_CHIP_ID		43362
+ #define BRCM_CC_4335_CHIP_ID		0x4335
+ #define BRCM_CC_4339_CHIP_ID		0x4339
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch
new file mode 100644
index 000000000000..affb86e4e7e6
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch
@@ -0,0 +1,23 @@
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+index a907d7b06..ec71996c7 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+@@ -619,13 +619,17 @@ BRCMF_FW_DEF(4354, "brcmfmac4354-sdio");
+ BRCMF_FW_DEF(4356, "brcmfmac4356-sdio");
+ BRCMF_FW_DEF(4373, "brcmfmac4373-sdio");
+ 
++/* AMPAK */
++BRCMF_FW_DEF(AP6330, "brcmfmac-ap6330-sdio");
++
+ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
+ 	BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
+-	BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
++	BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFEF, 4330),
++	BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0x10, AP6330),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-driver-esp8089.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-driver-esp8089.patch
new file mode 100644
index 000000000000..d76d3aed6a87
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-driver-esp8089.patch
@@ -0,0 +1,10931 @@
+From 2d6165af6e9d5ed5026cdf250536c0a00d84fd75 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 1 Oct 2022 12:43:53 +0000
+Subject: [PATCH] add esp8089 kernel driver
+
+---
+ drivers/net/wireless/Kconfig                  |    1 +
+ drivers/net/wireless/Makefile                 |    1 +
+ drivers/net/wireless/esp8089/.gitignore       |    7 +
+ drivers/net/wireless/esp8089/Kconfig          |   13 +
+ drivers/net/wireless/esp8089/LICENSE          |  340 +++
+ drivers/net/wireless/esp8089/Makefile         |    7 +
+ drivers/net/wireless/esp8089/Makefile.old     |   99 +
+ drivers/net/wireless/esp8089/README.md        |   31 +
+ drivers/net/wireless/esp8089/esp_ctrl.c       |  801 ++++++
+ drivers/net/wireless/esp8089/esp_ctrl.h       |   58 +
+ drivers/net/wireless/esp8089/esp_debug.c      |  297 ++
+ drivers/net/wireless/esp8089/esp_debug.h      |  101 +
+ drivers/net/wireless/esp8089/esp_ext.c        |  542 ++++
+ drivers/net/wireless/esp8089/esp_ext.h        |  100 +
+ drivers/net/wireless/esp8089/esp_file.c       |  258 ++
+ drivers/net/wireless/esp8089/esp_file.h       |   43 +
+ drivers/net/wireless/esp8089/esp_init_data.h  |    7 +
+ drivers/net/wireless/esp8089/esp_io.c         |  639 +++++
+ drivers/net/wireless/esp8089/esp_mac80211.c   | 1727 ++++++++++++
+ drivers/net/wireless/esp8089/esp_mac80211.h   |   38 +
+ drivers/net/wireless/esp8089/esp_main.c       |  263 ++
+ drivers/net/wireless/esp8089/esp_path.h       |    6 +
+ drivers/net/wireless/esp8089/esp_pub.h        |  222 ++
+ drivers/net/wireless/esp8089/esp_sif.h        |  207 ++
+ drivers/net/wireless/esp8089/esp_sip.c        | 2418 +++++++++++++++++
+ drivers/net/wireless/esp8089/esp_sip.h        |  171 ++
+ drivers/net/wireless/esp8089/esp_utils.c      |  262 ++
+ drivers/net/wireless/esp8089/esp_utils.h      |   41 +
+ drivers/net/wireless/esp8089/esp_version.h    |    1 +
+ drivers/net/wireless/esp8089/esp_wl.h         |   63 +
+ drivers/net/wireless/esp8089/esp_wmac.h       |   92 +
+ .../wireless/esp8089/firmware/LICENSE-2.0.txt |  203 ++
+ drivers/net/wireless/esp8089/sdio_sif_esp.c   |  811 ++++++
+ drivers/net/wireless/esp8089/sip2_common.h    |  475 ++++
+ .../net/wireless/esp8089/slc_host_register.h  |  271 ++
+ 35 files changed, 10616 insertions(+)
+ create mode 100644 drivers/net/wireless/esp8089/.gitignore
+ create mode 100644 drivers/net/wireless/esp8089/Kconfig
+ create mode 100644 drivers/net/wireless/esp8089/LICENSE
+ create mode 100644 drivers/net/wireless/esp8089/Makefile
+ create mode 100644 drivers/net/wireless/esp8089/Makefile.old
+ create mode 100644 drivers/net/wireless/esp8089/README.md
+ create mode 100644 drivers/net/wireless/esp8089/esp_ctrl.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_ctrl.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_debug.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_debug.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_ext.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_ext.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_file.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_file.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_init_data.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_io.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_mac80211.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_mac80211.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_main.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_path.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_pub.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_sif.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_sip.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_sip.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_utils.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_utils.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_version.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_wl.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_wmac.h
+ create mode 100644 drivers/net/wireless/esp8089/firmware/LICENSE-2.0.txt
+ create mode 100644 drivers/net/wireless/esp8089/sdio_sif_esp.c
+ create mode 100644 drivers/net/wireless/esp8089/sip2_common.h
+ create mode 100644 drivers/net/wireless/esp8089/slc_host_register.h
+
+diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
+index cb1c15012dd0..de5e37846397 100644
+--- a/drivers/net/wireless/Kconfig
++++ b/drivers/net/wireless/Kconfig
+@@ -37,6 +37,7 @@ source "drivers/net/wireless/st/Kconfig"
+ source "drivers/net/wireless/ti/Kconfig"
+ source "drivers/net/wireless/zydas/Kconfig"
+ source "drivers/net/wireless/quantenna/Kconfig"
++source "drivers/net/wireless/esp8089/Kconfig"
+ 
+ config PCMCIA_RAYCS
+ 	tristate "Aviator/Raytheon 2.4GHz wireless support"
+diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
+index a61cf6c90343..92ffd2cef51c 100644
+--- a/drivers/net/wireless/Makefile
++++ b/drivers/net/wireless/Makefile
+@@ -22,6 +22,7 @@ obj-$(CONFIG_WLAN_VENDOR_SILABS) += silabs/
+ obj-$(CONFIG_WLAN_VENDOR_ST) += st/
+ obj-$(CONFIG_WLAN_VENDOR_TI) += ti/
+ obj-$(CONFIG_WLAN_VENDOR_ZYDAS) += zydas/
++obj-$(CONFIG_ESP8089) += esp8089/
+ 
+ # 16-bit wireless PCMCIA client drivers
+ obj-$(CONFIG_PCMCIA_RAYCS)	+= ray_cs.o
+diff --git a/drivers/net/wireless/esp8089/.gitignore b/drivers/net/wireless/esp8089/.gitignore
+new file mode 100644
+index 000000000000..eae6529085d0
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/.gitignore
+@@ -0,0 +1,7 @@
++*.cmd
++*.o
++Module.symvers
++modules.order
++.tmp_versions
++*.ko
++*.mod.c
+diff --git a/drivers/net/wireless/esp8089/Kconfig b/drivers/net/wireless/esp8089/Kconfig
+new file mode 100644
+index 000000000000..8db1fc54712d
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/Kconfig
+@@ -0,0 +1,13 @@
++config ESP8089
++	tristate "Espressif ESP8089 SDIO WiFi"
++	depends on MAC80211
++	help
++	  ESP8089 is a low-budget 2.4GHz WiFi chip by Espressif, used in many
++	  cheap tablets with Allwinner or Rockchip SoC
++
++config ESP8089_DEBUG_FS
++	bool "Enable DebugFS support for ESP8089"
++	depends on ESP8089
++	default y
++	help
++	  DebugFS support for ESP8089
+diff --git a/drivers/net/wireless/esp8089/LICENSE b/drivers/net/wireless/esp8089/LICENSE
+new file mode 100644
+index 000000000000..d6a93266f748
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/LICENSE
+@@ -0,0 +1,340 @@
++GNU GENERAL PUBLIC LICENSE
++                       Version 2, June 1991
++
++ Copyright (C) 1989, 1991 Free Software Foundation, Inc., <http://fsf.org/>
++ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
++ Everyone is permitted to copy and distribute verbatim copies
++ of this license document, but changing it is not allowed.
++
++                            Preamble
++
++  The licenses for most software are designed to take away your
++freedom to share and change it.  By contrast, the GNU General Public
++License is intended to guarantee your freedom to share and change free
++software--to make sure the software is free for all its users.  This
++General Public License applies to most of the Free Software
++Foundation's software and to any other program whose authors commit to
++using it.  (Some other Free Software Foundation software is covered by
++the GNU Lesser General Public License instead.)  You can apply it to
++your programs, too.
++
++  When we speak of free software, we are referring to freedom, not
++price.  Our General Public Licenses are designed to make sure that you
++have the freedom to distribute copies of free software (and charge for
++this service if you wish), that you receive source code or can get it
++if you want it, that you can change the software or use pieces of it
++in new free programs; and that you know you can do these things.
++
++  To protect your rights, we need to make restrictions that forbid
++anyone to deny you these rights or to ask you to surrender the rights.
++These restrictions translate to certain responsibilities for you if you
++distribute copies of the software, or if you modify it.
++
++  For example, if you distribute copies of such a program, whether
++gratis or for a fee, you must give the recipients all the rights that
++you have.  You must make sure that they, too, receive or can get the
++source code.  And you must show them these terms so they know their
++rights.
++
++  We protect your rights with two steps: (1) copyright the software, and
++(2) offer you this license which gives you legal permission to copy,
++distribute and/or modify the software.
++
++  Also, for each author's protection and ours, we want to make certain
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++   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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++library.  If this is what you want to do, use the GNU Lesser General
++Public License instead of this License.
++
+diff --git a/drivers/net/wireless/esp8089/Makefile b/drivers/net/wireless/esp8089/Makefile
+new file mode 100644
+index 000000000000..36decfd20ecd
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/Makefile
+@@ -0,0 +1,7 @@
++MODULE_NAME = esp8089
++
++$(MODULE_NAME)-y := esp_debug.o sdio_sif_esp.o esp_io.o \
++    esp_file.o esp_main.o esp_sip.o esp_ext.o esp_ctrl.o \
++    esp_mac80211.o esp_debug.o esp_utils.o
++
++obj-$(CONFIG_ESP8089) := esp8089.o
+diff --git a/drivers/net/wireless/esp8089/Makefile.old b/drivers/net/wireless/esp8089/Makefile.old
+new file mode 100644
+index 000000000000..b7b1a47b159c
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/Makefile.old
+@@ -0,0 +1,99 @@
++MODNAME = esp8089
++
++# By default, we try to compile the modules for the currently running
++# kernel.  But it's the first approximation, as we will re-read the
++# version from the kernel sources.
++KVERS_UNAME ?= $(shell uname -r)
++
++# KBUILD is the path to the Linux kernel build tree.  It is usually the
++# same as the kernel source tree, except when the kernel was compiled in
++# a separate directory.
++KBUILD ?= $(shell readlink -f /lib/modules/$(KVERS_UNAME)/build)
++
++ifeq (,$(KBUILD))
++$(error Kernel build tree not found - please set KBUILD to configured kernel)
++endif
++
++KCONFIG := $(KBUILD)/.config
++ifeq (,$(wildcard $(KCONFIG)))
++$(error No .config found in $(KBUILD), please set KBUILD to configured kernel)
++endif
++
++ifneq (,$(wildcard $(KBUILD)/include/linux/version.h))
++ifneq (,$(wildcard $(KBUILD)/include/generated/uapi/linux/version.h))
++$(error Multiple copies of version.h found, please clean your build tree)
++endif
++endif
++
++# Kernel Makefile doesn't always know the exact kernel version, so we
++# get it from the kernel headers instead and pass it to make.
++VERSION_H := $(KBUILD)/include/generated/utsrelease.h
++ifeq (,$(wildcard $(VERSION_H)))
++VERSION_H := $(KBUILD)/include/linux/utsrelease.h
++endif
++ifeq (,$(wildcard $(VERSION_H)))
++VERSION_H := $(KBUILD)/include/linux/version.h
++endif
++ifeq (,$(wildcard $(VERSION_H)))
++$(error Please run 'make modules_prepare' in $(KBUILD))
++endif
++
++KVERS := $(shell sed -ne 's/"//g;s/^\#define UTS_RELEASE //p' $(VERSION_H))
++
++ifeq (,$(KVERS))
++$(error Cannot find UTS_RELEASE in $(VERSION_H), please report)
++endif
++
++INST_DIR = /lib/modules/$(KVERS)/misc
++
++SRC_DIR=$(shell pwd)
++
++include $(KCONFIG)
++
++EXTRA_CFLAGS += -DCONFIG_ESP8089_DEBUG_FS
++
++OBJS = esp_debug.o sdio_sif_esp.o esp_io.o \
++    esp_file.o esp_main.o esp_sip.o esp_ext.o esp_ctrl.o \
++    esp_mac80211.o esp_debug.o esp_utils.o esp_pm.o 
++
++all: config_check modules
++
++MODULE := $(MODNAME).ko
++obj-m := $(MODNAME).o
++
++$(MODNAME)-objs := $(OBJS)
++
++config_check:
++	@if [ -z "$(CONFIG_WIRELESS_EXT)$(CONFIG_NET_RADIO)" ]; then \
++		echo; echo; \
++		echo "*** WARNING: This kernel lacks wireless extensions."; \
++		echo "Wireless drivers will not work properly."; \
++		echo; echo; \
++	fi
++
++modules:
++	$(MAKE) -C $(KBUILD) M=$(SRC_DIR)
++
++$(MODULE):
++	$(MAKE) modules
++
++clean:
++	rm -f *.o *.ko .*.cmd *.mod.c *.symvers modules.order
++	rm -rf .tmp_versions
++
++install: config_check $(MODULE)
++	@/sbin/modinfo $(MODULE) | grep -q "^vermagic: *$(KVERS) " || \
++		{ echo "$(MODULE)" is not for Linux $(KVERS); exit 1; }
++	mkdir -p -m 755 $(DESTDIR)$(INST_DIR)
++	install -m 0644 $(MODULE) $(DESTDIR)$(INST_DIR)
++ifndef DESTDIR
++	-/sbin/depmod -a $(KVERS)
++endif
++
++uninstall:
++	rm -f $(DESTDIR)$(INST_DIR)/$(MODULE)
++ifndef DESTDIR
++	-/sbin/depmod -a $(KVERS)
++endif
++
++.PHONY: all modules clean install config_check
+diff --git a/drivers/net/wireless/esp8089/README.md b/drivers/net/wireless/esp8089/README.md
+new file mode 100644
+index 000000000000..56b40db272f3
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/README.md
+@@ -0,0 +1,31 @@
++esp8089
++======
++
++ESP8089 Linux driver
++
++v1.9 imported from the Rockchip Linux kernel github repo
++
++Modified to build as a standalone module for SDIO devices.
++
++
++
++
++Building:
++
++ make
++
++Using:
++
++Must load mac80211.ko first if not baked in.
++
++ sudo modprobe esp8089.ko
++
++If you get a wlan interface, but scanning shows no networks try using:
++
++ sudo modprobe esp8089.ko config=crystal_26M_en=1
++
++or:
++
++ sudo modprobe esp8089.ko config=crystal_26M_en=2
++
++To load the module.
+diff --git a/drivers/net/wireless/esp8089/esp_ctrl.c b/drivers/net/wireless/esp8089/esp_ctrl.c
+new file mode 100644
+index 000000000000..a19d2437dd82
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_ctrl.c
+@@ -0,0 +1,801 @@
++/*
++ * Copyright (c) 2009 - 2014 Espressif System.
++ *
++ * SIP ctrl packet parse and pack
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <net/mac80211.h>
++#include <net/cfg80211.h>
++#include <linux/skbuff.h>
++#include <linux/bitops.h>
++#include <linux/firmware.h>
++
++#include "esp_pub.h"
++#include "esp_sip.h"
++#include "esp_ctrl.h"
++#include "esp_sif.h"
++#include "esp_debug.h"
++#include "esp_wmac.h"
++#include "esp_utils.h"
++#include "esp_wl.h"
++#include "esp_file.h"
++#include "esp_path.h"
++#ifdef TEST_MODE
++#include "testmode.h"
++#endif				/* TEST_MODE */
++#include "esp_version.h"
++
++extern struct completion *gl_bootup_cplx;
++
++static void esp_tx_ba_session_op(struct esp_sip *sip,
++				 struct esp_node *node,
++				 trc_ampdu_state_t state, u8 tid)
++{
++	struct esp_tx_tid *txtid;
++
++	txtid = &node->tid[tid];
++	if (state == TRC_TX_AMPDU_STOPPED) {
++		if (txtid->state == ESP_TID_STATE_OPERATIONAL) {
++			esp_dbg(ESP_DBG_TXAMPDU,
++				"%s tid %d TXAMPDU GOT STOP EVT\n",
++				__func__, tid);
++
++			spin_lock_bh(&sip->epub->tx_ampdu_lock);
++			txtid->state = ESP_TID_STATE_WAIT_STOP;
++			spin_unlock_bh(&sip->epub->tx_ampdu_lock);
++			ieee80211_stop_tx_ba_session(node->sta, (u16) tid);
++		} else {
++			esp_dbg(ESP_DBG_TXAMPDU,
++				"%s tid %d TXAMPDU GOT STOP EVT IN WRONG STATE %d\n",
++				__func__, tid, txtid->state);
++		}
++	} else if (state == TRC_TX_AMPDU_OPERATIONAL) {
++		if (txtid->state == ESP_TID_STATE_STOP) {
++			esp_dbg(ESP_DBG_TXAMPDU,
++				"%s tid %d TXAMPDU GOT OPERATIONAL\n",
++				__func__, tid);
++
++			spin_lock_bh(&sip->epub->tx_ampdu_lock);
++			txtid->state = ESP_TID_STATE_TRIGGER;
++			spin_unlock_bh(&sip->epub->tx_ampdu_lock);
++			ieee80211_start_tx_ba_session(node->sta, (u16) tid,
++						      0);
++
++		} else if (txtid->state == ESP_TID_STATE_OPERATIONAL) {
++			sip_send_ampdu_action(sip->epub,
++					      SIP_AMPDU_TX_OPERATIONAL,
++					      node->sta->addr, tid,
++					      node->ifidx, 0);
++		} else {
++			esp_dbg(ESP_DBG_TXAMPDU,
++				"%s tid %d TXAMPDU GOT OPERATIONAL EVT IN WRONG STATE %d\n",
++				__func__, tid, txtid->state);
++		}
++	}
++}
++
++int sip_parse_events(struct esp_sip *sip, u8 * buf)
++{
++	struct sip_hdr *hdr = (struct sip_hdr *) buf;
++
++	switch (hdr->c_evtid) {
++	case SIP_EVT_TARGET_ON:{
++			/* use rx work queue to send... */
++			if (atomic_read(&sip->state) == SIP_PREPARE_BOOT
++			    || atomic_read(&sip->state) == SIP_BOOT) {
++				atomic_set(&sip->state, SIP_SEND_INIT);
++				queue_work(sip->epub->esp_wkq,
++					   &sip->rx_process_work);
++			} else {
++				esp_dbg(ESP_DBG_ERROR,
++					"%s boot during wrong state %d\n",
++					__func__,
++					atomic_read(&sip->state));
++			}
++			break;
++		}
++
++	case SIP_EVT_BOOTUP:{
++			struct sip_evt_bootup2 *bootup_evt =
++			    (struct sip_evt_bootup2 *) (buf +
++							SIP_CTRL_HDR_LEN);
++			if (sip->rawbuf)
++				kfree(sip->rawbuf);
++
++			sip_post_init(sip, bootup_evt);
++
++			if (gl_bootup_cplx)
++				complete(gl_bootup_cplx);
++
++			break;
++		}
++	case SIP_EVT_RESETTING:{
++			sip->epub->wait_reset = 1;
++			if (gl_bootup_cplx)
++				complete(gl_bootup_cplx);
++			break;
++		}
++	case SIP_EVT_SLEEP:{
++			//atomic_set(&sip->epub->ps.state, ESP_PM_ON);
++			break;
++		}
++	case SIP_EVT_TXIDLE:{
++			//struct sip_evt_txidle *txidle = (struct sip_evt_txidle *)(buf + SIP_CTRL_HDR_LEN);
++			//sip_txdone_clear(sip, txidle->last_seq);
++			break;
++		}
++
++	case SIP_EVT_SCAN_RESULT:{
++			struct sip_evt_scan_report *report =
++			    (struct sip_evt_scan_report *) (buf +
++							    SIP_CTRL_HDR_LEN);
++			if (atomic_read(&sip->epub->wl.off)) {
++				esp_dbg(ESP_DBG_ERROR,
++					"%s scan result while wlan off\n",
++					__func__);
++				return 0;
++			}
++			sip_scandone_process(sip, report);
++
++			break;
++		}
++
++	case SIP_EVT_ROC:{
++			struct sip_evt_roc *report =
++			    (struct sip_evt_roc *) (buf +
++						    SIP_CTRL_HDR_LEN);
++			esp_rocdone_process(sip->epub->hw, report);
++			break;
++		}
++
++
++#ifdef ESP_RX_COPYBACK_TEST
++
++	case SIP_EVT_COPYBACK:{
++			u32 len = hdr->len - SIP_CTRL_HDR_LEN;
++
++			esp_dbg(ESP_DBG_TRACE,
++				"%s copyback len %d   seq %u\n", __func__,
++				len, hdr->seq);
++
++			memcpy(copyback_buf + copyback_offset,
++			       pkt->buf + SIP_CTRL_HDR_LEN, len);
++			copyback_offset += len;
++
++			//show_buf(pkt->buf, 256);
++
++			//how about totlen % 256 == 0??
++			if (hdr->hdr.len < 256) {
++				kfree(copyback_buf);
++			}
++		}
++		break;
++#endif				/* ESP_RX_COPYBACK_TEST */
++	case SIP_EVT_CREDIT_RPT:
++		break;
++
++#ifdef TEST_MODE
++	case SIP_EVT_WAKEUP:{
++			u8 check_str[12];
++			struct sip_evt_wakeup *wakeup_evt =
++			    (struct sip_evt_wakeup *) (buf +
++						       SIP_CTRL_HDR_LEN);
++			sprintf((char *) &check_str, "%d",
++				wakeup_evt->check_data);
++			esp_test_cmd_event(TEST_CMD_WAKEUP,
++					   (char *) &check_str);
++			break;
++		}
++
++	case SIP_EVT_DEBUG:{
++			u8 check_str[640];
++			sip_parse_event_debug(sip->epub, buf, check_str);
++			esp_dbg(ESP_DBG_TRACE, "%s", check_str);
++			esp_test_cmd_event(TEST_CMD_DEBUG,
++					   (char *) &check_str);
++			break;
++		}
++
++	case SIP_EVT_LOOPBACK:{
++			u8 check_str[12];
++			struct sip_evt_loopback *loopback_evt =
++			    (struct sip_evt_loopback *) (buf +
++							 SIP_CTRL_HDR_LEN);
++			esp_dbg(ESP_DBG_LOG, "%s loopback len %d seq %u\n",
++				__func__, hdr->len, hdr->seq);
++
++			if (loopback_evt->pack_id != get_loopback_id()) {
++				sprintf((char *) &check_str,
++					"seq id error %d, expect %d",
++					loopback_evt->pack_id,
++					get_loopback_id());
++				esp_test_cmd_event(TEST_CMD_LOOPBACK,
++						   (char *) &check_str);
++			}
++
++			if ((loopback_evt->pack_id + 1) <
++			    get_loopback_num()) {
++				inc_loopback_id();
++				sip_send_loopback_mblk(sip,
++						       loopback_evt->txlen,
++						       loopback_evt->rxlen,
++						       get_loopback_id());
++			} else {
++				sprintf((char *) &check_str, "test over!");
++				esp_test_cmd_event(TEST_CMD_LOOPBACK,
++						   (char *) &check_str);
++			}
++			break;
++		}
++#endif				/*TEST_MODE */
++
++	case SIP_EVT_SNPRINTF_TO_HOST:{
++			u8 *p =
++			    (buf + sizeof(struct sip_hdr) + sizeof(u16));
++			u16 *len = (u16 *) (buf + sizeof(struct sip_hdr));
++			char test_res_str[560];
++			sprintf(test_res_str,
++				"esp_host:%llx\nesp_target: %.*s",
++				DRIVER_VER, *len, p);
++
++			esp_dbg(ESP_DBG_TRACE, "%s\n", test_res_str);
++			if (*len
++			    && sip->epub->sdio_state ==
++			    ESP_SDIO_STATE_FIRST_INIT) {
++				char filename[256];
++				if (mod_eagle_path_get() == NULL)
++					sprintf(filename, "%s/%s", FWPATH,
++						"test_results");
++				else
++					sprintf(filename, "%s/%s",
++						mod_eagle_path_get(),
++						"test_results");
++				esp_dbg(ESP_DBG_TRACE,
++					"SNPRINTF TO HOST: %s\n",
++					test_res_str);
++			}
++			break;
++		}
++	case SIP_EVT_TRC_AMPDU:{
++			struct sip_evt_trc_ampdu *ep =
++			    (struct sip_evt_trc_ampdu *) (buf +
++							  SIP_CTRL_HDR_LEN);
++			struct esp_node *node = NULL;
++			int i = 0;
++
++			if (atomic_read(&sip->epub->wl.off)) {
++				esp_dbg(ESP_DBG_ERROR,
++					"%s scan result while wlan off\n",
++					__func__);
++				return 0;
++			}
++
++			node = esp_get_node_by_addr(sip->epub, ep->addr);
++			if (node == NULL)
++				break;
++			for (i = 0; i < 8; i++) {
++				if (ep->tid & (1 << i)) {
++					esp_tx_ba_session_op(sip, node,
++							     ep->state, i);
++				}
++			}
++			break;
++		}
++
++#ifdef TEST_MODE
++	case SIP_EVT_EP:{
++			char *ep = (char *) (buf + SIP_CTRL_HDR_LEN);
++			static int counter = 0;
++
++			esp_dbg(ESP_ATE, "%s EVT_EP \n\n", __func__);
++			if (counter++ < 2) {
++				esp_dbg(ESP_ATE, "ATE: %s \n", ep);
++			}
++
++			esp_test_ate_done_cb(ep);
++
++			break;
++		}
++#endif				/*TEST_MODE */
++
++	case SIP_EVT_INIT_EP:{
++			char *ep = (char *) (buf + SIP_CTRL_HDR_LEN);
++			esp_dbg(ESP_ATE, "Phy Init: %s \n", ep);
++			break;
++		}
++
++	case SIP_EVT_NOISEFLOOR:{
++			struct sip_evt_noisefloor *ep =
++			    (struct sip_evt_noisefloor *) (buf +
++							   SIP_CTRL_HDR_LEN);
++			atomic_set(&sip->noise_floor, ep->noise_floor);
++			break;
++		}
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++#include "esp_init_data.h"
++
++void sip_send_chip_init(struct esp_sip *sip)
++{
++	size_t size = 0;
++	size = sizeof(esp_init_data);
++
++	esp_conf_upload_second(esp_init_data, size);
++
++	atomic_sub(1, &sip->tx_credits);
++
++	sip_send_cmd(sip, SIP_CMD_INIT, size, (void *) esp_init_data);
++
++}
++
++int sip_send_config(struct esp_pub *epub, struct ieee80211_conf *conf)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_config *configcmd;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_config) +
++				 sizeof(struct sip_hdr), SIP_CMD_CONFIG);
++	if (!skb)
++		return -EINVAL;
++	esp_dbg(ESP_DBG_TRACE, "%s config center freq %d\n", __func__,
++		conf->chandef.chan->center_freq);
++	configcmd =
++	    (struct sip_cmd_config *) (skb->data + sizeof(struct sip_hdr));
++	configcmd->center_freq = conf->chandef.chan->center_freq;
++	configcmd->duration = 0;
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_bss_info_update(struct esp_pub *epub, struct esp_vif *evif,
++			     u8 * bssid, int assoc)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_bss_info_update *bsscmd;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_bss_info_update) +
++				 sizeof(struct sip_hdr),
++				 SIP_CMD_BSS_INFO_UPDATE);
++	if (!skb)
++		return -EINVAL;
++
++	bsscmd =
++	    (struct sip_cmd_bss_info_update *) (skb->data +
++						sizeof(struct sip_hdr));
++	if (assoc == 2) {	//hack for softAP mode
++		bsscmd->beacon_int = evif->beacon_interval;
++	} else if (assoc == 1) {
++		set_bit(ESP_WL_FLAG_CONNECT, &epub->wl.flags);
++	} else {
++		clear_bit(ESP_WL_FLAG_CONNECT, &epub->wl.flags);
++	}
++	bsscmd->bssid_no = evif->index;
++	bsscmd->isassoc = assoc;
++	bsscmd->beacon_int = evif->beacon_interval;
++	memcpy(bsscmd->bssid, bssid, ETH_ALEN);
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_wmm_params(struct esp_pub *epub, u8 aci,
++			const struct ieee80211_tx_queue_params *params)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_set_wmm_params *bsscmd;
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_set_wmm_params) +
++				 sizeof(struct sip_hdr),
++				 SIP_CMD_SET_WMM_PARAM);
++	if (!skb)
++		return -EINVAL;
++
++	bsscmd =
++	    (struct sip_cmd_set_wmm_params *) (skb->data +
++					       sizeof(struct sip_hdr));
++	bsscmd->aci = aci;
++	bsscmd->aifs = params->aifs;
++	bsscmd->txop_us = params->txop * 32;
++
++	bsscmd->ecw_min = 32 - __builtin_clz(params->cw_min);
++	bsscmd->ecw_max = 32 - __builtin_clz(params->cw_max);
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_ampdu_action(struct esp_pub *epub, u8 action_num,
++			  const u8 * addr, u16 tid, u16 ssn, u8 buf_size)
++{
++	int index = 0;
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_ampdu_action *action;
++	if (action_num == SIP_AMPDU_RX_START) {
++		index = esp_get_empty_rxampdu(epub, addr, tid);
++	} else if (action_num == SIP_AMPDU_RX_STOP) {
++		index = esp_get_exist_rxampdu(epub, addr, tid);
++	}
++	if (index < 0)
++		return -EACCES;
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_ampdu_action) +
++				 sizeof(struct sip_hdr),
++				 SIP_CMD_AMPDU_ACTION);
++	if (!skb)
++		return -EINVAL;
++
++	action =
++	    (struct sip_cmd_ampdu_action *) (skb->data +
++					     sizeof(struct sip_hdr));
++	action->action = action_num;
++	//for TX, it means interface index
++	action->index = ssn;
++
++	switch (action_num) {
++	case SIP_AMPDU_RX_START:
++		action->ssn = ssn;
++		// fall through
++	case SIP_AMPDU_RX_STOP:
++		action->index = index;
++		// fall through
++	case SIP_AMPDU_TX_OPERATIONAL:
++	case SIP_AMPDU_TX_STOP:
++		action->win_size = buf_size;
++		action->tid = tid;
++		memcpy(action->addr, addr, ETH_ALEN);
++		break;
++	}
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++#ifdef HW_SCAN
++/*send cmd to target, if aborted is true, inform target stop scan, report scan complete imediately
++  return 1: complete over, 0: success, still have next scan, -1: hardware failure
++  */
++int sip_send_scan(struct esp_pub *epub)
++{
++	struct cfg80211_scan_request *scan_req = epub->wl.scan_req;
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_scan *scancmd;
++	u8 *ptr = NULL;
++	int i;
++	u8 append_len, ssid_len;
++
++	ESSERT(scan_req != NULL);
++	ssid_len = scan_req->n_ssids == 0 ? 0 :
++	    (scan_req->n_ssids ==
++	     1 ? scan_req->ssids->ssid_len : scan_req->ssids->ssid_len +
++	     (scan_req->ssids + 1)->ssid_len);
++	append_len = ssid_len + scan_req->n_channels + scan_req->ie_len;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_scan) +
++				 sizeof(struct sip_hdr) + append_len,
++				 SIP_CMD_SCAN);
++
++	if (!skb)
++		return -EINVAL;
++
++	ptr = skb->data;
++	scancmd = (struct sip_cmd_scan *) (ptr + sizeof(struct sip_hdr));
++	ptr += sizeof(struct sip_hdr);
++
++	scancmd->aborted = false;
++
++	if (scancmd->aborted == false) {
++		ptr += sizeof(struct sip_cmd_scan);
++		if (scan_req->n_ssids <= 0
++		    || (scan_req->n_ssids == 1 && ssid_len == 0)) {
++			scancmd->ssid_len = 0;
++		} else {
++			scancmd->ssid_len = ssid_len;
++			if (scan_req->ssids->ssid_len == ssid_len)
++				memcpy(ptr, scan_req->ssids->ssid,
++				       scancmd->ssid_len);
++			else
++				memcpy(ptr, (scan_req->ssids + 1)->ssid,
++				       scancmd->ssid_len);
++		}
++
++		ptr += scancmd->ssid_len;
++		scancmd->n_channels = scan_req->n_channels;
++		for (i = 0; i < scan_req->n_channels; i++)
++			ptr[i] = scan_req->channels[i]->hw_value;
++
++		ptr += scancmd->n_channels;
++		if (scan_req->ie_len && scan_req->ie != NULL) {
++			scancmd->ie_len = scan_req->ie_len;
++			memcpy(ptr, scan_req->ie, scan_req->ie_len);
++		} else {
++			scancmd->ie_len = 0;
++		}
++		//add a flag that support two ssids,
++		if (scan_req->n_ssids > 1)
++			scancmd->ssid_len |= 0x80;
++
++	}
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++#endif
++
++int sip_send_suspend_config(struct esp_pub *epub, u8 suspend)
++{
++	struct sip_cmd_suspend *cmd = NULL;
++	struct sk_buff *skb = NULL;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_suspend) +
++				 sizeof(struct sip_hdr), SIP_CMD_SUSPEND);
++
++	if (!skb)
++		return -EINVAL;
++
++	cmd =
++	    (struct sip_cmd_suspend *) (skb->data +
++					sizeof(struct sip_hdr));
++	cmd->suspend = suspend;
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_ps_config(struct esp_pub *epub, struct esp_ps *ps)
++{
++	struct sip_cmd_ps *pscmd = NULL;
++	struct sk_buff *skb = NULL;
++	struct sip_hdr *shdr = NULL;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_ps) +
++				 sizeof(struct sip_hdr), SIP_CMD_PS);
++
++	if (!skb)
++		return -EINVAL;
++
++
++	shdr = (struct sip_hdr *) skb->data;
++	pscmd = (struct sip_cmd_ps *) (skb->data + sizeof(struct sip_hdr));
++
++	pscmd->dtim_period = ps->dtim_period;
++	pscmd->max_sleep_period = ps->max_sleep_period;
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++void sip_scandone_process(struct esp_sip *sip,
++			  struct sip_evt_scan_report *scan_report)
++{
++	struct esp_pub *epub = sip->epub;
++
++	esp_dbg(ESP_DBG_TRACE, "eagle hw scan report\n");
++
++	if (epub->wl.scan_req) {
++		hw_scan_done(epub, scan_report->aborted);
++		epub->wl.scan_req = NULL;
++	}
++}
++
++int sip_send_setkey(struct esp_pub *epub, u8 bssid_no, u8 * peer_addr,
++		    struct ieee80211_key_conf *key, u8 isvalid)
++{
++	struct sip_cmd_setkey *setkeycmd;
++	struct sk_buff *skb = NULL;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_setkey) +
++				 sizeof(struct sip_hdr), SIP_CMD_SETKEY);
++
++	if (!skb)
++		return -EINVAL;
++
++	setkeycmd =
++	    (struct sip_cmd_setkey *) (skb->data + sizeof(struct sip_hdr));
++
++	if (peer_addr) {
++		memcpy(setkeycmd->addr, peer_addr, ETH_ALEN);
++	} else {
++		memset(setkeycmd->addr, 0, ETH_ALEN);
++	}
++
++	setkeycmd->bssid_no = bssid_no;
++	setkeycmd->hw_key_idx = key->hw_key_idx;
++
++	if (isvalid) {
++		setkeycmd->alg = esp_cipher2alg(key->cipher);
++		setkeycmd->keyidx = key->keyidx;
++		setkeycmd->keylen = key->keylen;
++		if (key->cipher == WLAN_CIPHER_SUITE_TKIP) {
++			memcpy(setkeycmd->key, key->key, 16);
++			memcpy(setkeycmd->key + 16, key->key + 24, 8);
++			memcpy(setkeycmd->key + 24, key->key + 16, 8);
++		} else {
++			memcpy(setkeycmd->key, key->key, key->keylen);
++		}
++
++		setkeycmd->flags = 1;
++	} else {
++		setkeycmd->flags = 0;
++	}
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++#ifdef FPGA_LOOPBACK
++#define LOOPBACK_PKT_LEN 200
++int sip_send_loopback_cmd_mblk(struct esp_sip *sip)
++{
++	int cnt, ret;
++
++	for (cnt = 0; cnt < 4; cnt++) {
++		if (0 !=
++		    (ret =
++		     sip_send_loopback_mblk(sip, LOOPBACK_PKT_LEN,
++					    LOOPBACK_PKT_LEN, 0)))
++			return ret;
++	}
++	return 0;
++}
++#endif				/* FPGA_LOOPBACK */
++
++int sip_send_loopback_mblk(struct esp_sip *sip, int txpacket_len,
++			   int rxpacket_len, int packet_id)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_loopback *cmd;
++	u8 *ptr = NULL;
++	int i, ret;
++
++	//send 100 loopback pkt
++	if (txpacket_len)
++		skb =
++		    sip_alloc_ctrl_skbuf(sip,
++					 sizeof(struct sip_cmd_loopback) +
++					 sizeof(struct sip_hdr) +
++					 txpacket_len, SIP_CMD_LOOPBACK);
++	else
++		skb =
++		    sip_alloc_ctrl_skbuf(sip,
++					 sizeof(struct sip_cmd_loopback) +
++					 sizeof(struct sip_hdr),
++					 SIP_CMD_LOOPBACK);
++
++	if (!skb)
++		return -ENOMEM;
++
++	ptr = skb->data;
++	cmd = (struct sip_cmd_loopback *) (ptr + sizeof(struct sip_hdr));
++	ptr += sizeof(struct sip_hdr);
++	cmd->txlen = txpacket_len;
++	cmd->rxlen = rxpacket_len;
++	cmd->pack_id = packet_id;
++
++	if (txpacket_len) {
++		ptr += sizeof(struct sip_cmd_loopback);
++		/* fill up pkt payload */
++		for (i = 0; i < txpacket_len; i++) {
++			ptr[i] = i;
++		}
++	}
++
++	ret = sip_cmd_enqueue(sip, skb, ENQUEUE_PRIOR_TAIL);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++//remain_on_channel
++int sip_send_roc(struct esp_pub *epub, u16 center_freq, u16 duration)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_config *configcmd;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_config) +
++				 sizeof(struct sip_hdr), SIP_CMD_CONFIG);
++	if (!skb)
++		return -EINVAL;
++
++	configcmd =
++	    (struct sip_cmd_config *) (skb->data + sizeof(struct sip_hdr));
++	configcmd->center_freq = center_freq;
++	configcmd->duration = duration;
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_set_sta(struct esp_pub *epub, u8 ifidx, u8 set,
++		     struct ieee80211_sta *sta, struct ieee80211_vif *vif,
++		     u8 index)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_setsta *setstacmd;
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_setsta) +
++				 sizeof(struct sip_hdr), SIP_CMD_SETSTA);
++	if (!skb)
++		return -EINVAL;
++
++	setstacmd =
++	    (struct sip_cmd_setsta *) (skb->data + sizeof(struct sip_hdr));
++	setstacmd->ifidx = ifidx;
++	setstacmd->index = index;
++	setstacmd->set = set;
++	if (sta->aid == 0)
++		setstacmd->aid = vif->cfg.aid;
++	else
++		setstacmd->aid = sta->aid;
++	memcpy(setstacmd->mac, sta->addr, ETH_ALEN);
++	if (set) {
++		if (sta->deflink.ht_cap.ht_supported) {
++			if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20)
++				setstacmd->phymode =
++				    ESP_IEEE80211_T_HT20_S;
++			else
++				setstacmd->phymode =
++				    ESP_IEEE80211_T_HT20_L;
++			setstacmd->ampdu_factor = sta->deflink.ht_cap.ampdu_factor;
++			setstacmd->ampdu_density =
++			    sta->deflink.ht_cap.ampdu_density;
++		} else {
++			if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & (~(u32)
++							       CONF_HW_BIT_RATE_11B_MASK))
++			{
++				setstacmd->phymode = ESP_IEEE80211_T_OFDM;
++			} else {
++				setstacmd->phymode = ESP_IEEE80211_T_CCK;
++			}
++		}
++	}
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_recalc_credit(struct esp_pub *epub)
++{
++	struct sk_buff *skb = NULL;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip, 0 + sizeof(struct sip_hdr),
++				 SIP_CMD_RECALC_CREDIT);
++	if (!skb)
++		return -ENOMEM;
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_HEAD);
++}
++
++int sip_cmd(struct esp_pub *epub, enum sip_cmd_id cmd_id, u8 * cmd_buf,
++	    u8 cmd_len)
++{
++	struct sk_buff *skb = NULL;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 cmd_len + sizeof(struct sip_hdr), cmd_id);
++	if (!skb)
++		return -ENOMEM;
++
++	memcpy(skb->data + sizeof(struct sip_hdr), cmd_buf, cmd_len);
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
+diff --git a/drivers/net/wireless/esp8089/esp_ctrl.h b/drivers/net/wireless/esp8089/esp_ctrl.h
+new file mode 100644
+index 000000000000..29c18caa9ede
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_ctrl.h
+@@ -0,0 +1,58 @@
++/*
++ *  Copyright (c) 2009- 2014 Espressif System.
++ *
++ *  SIP ctrl packet parse and pack
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#ifndef _ESP_CTRL_H_
++#define _ESP_CTRL_H_
++
++int sip_send_loopback_mblk(struct esp_sip *sip, int txpacket_len,
++			   int rxpacket_len, int packet_id);
++
++int sip_send_config(struct esp_pub *epub, struct ieee80211_conf *conf);
++
++int sip_send_setkey(struct esp_pub *epub, u8 bssid_no, u8 * peer_addr,
++		    struct ieee80211_key_conf *key, u8 isvalid);
++
++int sip_send_scan(struct esp_pub *epub);
++
++void sip_scandone_process(struct esp_sip *sip,
++			  struct sip_evt_scan_report *scan_report);
++
++int sip_send_bss_info_update(struct esp_pub *epub, struct esp_vif *evif,
++			     u8 * bssid, int assoc);
++
++int sip_send_wmm_params(struct esp_pub *epub, u8 aci,
++			const struct ieee80211_tx_queue_params *params);
++
++int sip_send_ampdu_action(struct esp_pub *epub, u8 action_num,
++			  const u8 * addr, u16 tid, u16 ssn, u8 buf_size);
++
++int sip_send_roc(struct esp_pub *epub, u16 center_freq, u16 duration);
++
++int sip_send_set_sta(struct esp_pub *epub, u8 ifidx, u8 set,
++		     struct ieee80211_sta *sta, struct ieee80211_vif *vif,
++		     u8 index);
++
++int sip_send_suspend_config(struct esp_pub *epub, u8 suspend);
++
++int sip_send_ps_config(struct esp_pub *epub, struct esp_ps *ps);
++
++int sip_parse_events(struct esp_sip *sip, u8 * buf);
++
++int sip_send_recalc_credit(struct esp_pub *epub);
++
++int sip_cmd(struct esp_pub *epub, enum sip_cmd_id cmd_id, u8 * cmd_buf,
++	    u8 cmd_len);
++
++#endif				/* _ESP_CTRL_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_debug.c b/drivers/net/wireless/esp8089/esp_debug.c
+new file mode 100644
+index 000000000000..5ce8fd2ebd6b
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_debug.c
+@@ -0,0 +1,297 @@
++/*
++ * Copyright (c) 2011-2014 Espressif System.
++ *
++ * esp debug interface
++ *  - debugfs
++ *  - debug level control
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/types.h>
++#include <linux/kernel.h>
++
++#include <net/mac80211.h>
++#include "sip2_common.h"
++
++#include "esp_debug.h"
++
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_ESP8089_DEBUG_FS)
++
++static struct dentry *esp_debugfs_root = NULL;
++
++static int esp_debugfs_open(struct inode *inode, struct file *filp)
++{
++	filp->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t esp_debugfs_read(struct file *filp, char __user * buffer,
++				size_t count, loff_t * ppos)
++{
++	if (*ppos >= 32)
++		return 0;
++	if (*ppos + count > 32)
++		count = 32 - *ppos;
++
++	if (copy_to_user(buffer, filp->private_data + *ppos, count))
++		return -EFAULT;
++
++	*ppos += count;
++
++	return count;
++}
++
++static ssize_t esp_debugfs_write(struct file *filp,
++				 const char __user * buffer, size_t count,
++				 loff_t * ppos)
++{
++	if (*ppos >= 32)
++		return 0;
++	if (*ppos + count > 32)
++		count = 32 - *ppos;
++
++	if (copy_from_user(filp->private_data + *ppos, buffer, count))
++		return -EFAULT;
++
++	*ppos += count;
++
++	return count;
++}
++
++struct file_operations esp_debugfs_fops = {
++	.owner = THIS_MODULE,
++	.open = esp_debugfs_open,
++	.read = esp_debugfs_read,
++	.write = esp_debugfs_write,
++};
++
++
++void esp_dump_var(const char *name, struct dentry *parent,
++			    void *value, esp_type type)
++{
++	umode_t mode = 0644;
++
++	if (!esp_debugfs_root)
++		return;
++
++	if (!parent)
++		parent = esp_debugfs_root;
++
++	switch (type) {
++	case ESP_U8:
++		debugfs_create_u8(name, mode, parent, (u8 *) value);
++		break;
++	case ESP_U16:
++		debugfs_create_u16(name, mode, parent, (u16 *) value);
++		break;
++	case ESP_U32:
++		debugfs_create_u32(name, mode, parent, (u32 *) value);
++		break;
++	case ESP_U64:
++		debugfs_create_u64(name, mode, parent, (u64 *) value);
++		break;
++	case ESP_BOOL:
++		debugfs_create_bool(name, mode, parent,
++					 (bool *) value);
++		break;
++	default:		//32
++		debugfs_create_u32(name, mode, parent, (u32 *) value);
++	}
++
++	return;
++
++}
++
++void esp_dump_array(const char *name, struct dentry *parent,
++			      struct debugfs_blob_wrapper *blob)
++{
++	umode_t mode = 0644;
++
++	if (!esp_debugfs_root)
++		return;
++
++	if (!parent)
++		parent = esp_debugfs_root;
++
++	debugfs_create_blob(name, mode, parent, blob);
++
++}
++
++void esp_dump(const char *name, struct dentry *parent,
++			void *data, int size)
++{
++	umode_t mode = 0644;
++
++	if (!esp_debugfs_root)
++		return;
++
++	if (!parent)
++		parent = esp_debugfs_root;
++
++	debugfs_create_file(name, mode, parent, data,
++				 &esp_debugfs_fops);
++
++}
++
++struct dentry *esp_debugfs_add_sub_dir(const char *name)
++{
++	struct dentry *sub_dir = NULL;
++
++	sub_dir = debugfs_create_dir(name, esp_debugfs_root);
++
++	if (!sub_dir)
++		goto Fail;
++
++	return sub_dir;
++
++      Fail:
++	debugfs_remove_recursive(esp_debugfs_root);
++	esp_debugfs_root = NULL;
++	esp_dbg(ESP_DBG_ERROR,
++		"%s failed, debugfs root removed; dir name: %s\n",
++		__FUNCTION__, name);
++	return NULL;
++
++}
++
++int esp_debugfs_init(void)
++{
++	esp_dbg(ESP_DBG, "esp debugfs init\n");
++	esp_debugfs_root = debugfs_create_dir("esp_debug", NULL);
++
++	if (!esp_debugfs_root || IS_ERR_OR_NULL(esp_debugfs_root)) {
++		return -ENOENT;
++	}
++
++	return 0;
++}
++
++void esp_debugfs_exit(void)
++{
++	esp_dbg(ESP_DBG, "esp debugfs exit");
++
++	debugfs_remove_recursive(esp_debugfs_root);
++
++	return;
++}
++
++#else
++
++inline struct dentry *esp_dump_var(const char *name, struct dentry *parent,
++				   void *value, esp_type type)
++{
++	return NULL;
++}
++
++inline struct dentry *esp_dump_array(const char *name,
++				     struct dentry *parent,
++				     struct debugfs_blob_wrapper *blob)
++{
++	return NULL;
++}
++
++inline struct dentry *esp_dump(const char *name, struct dentry *parent,
++			       void *data, int size)
++{
++	return NULL;
++}
++
++struct dentry *esp_debugfs_add_sub_dir(const char *name)
++{
++	return NULL;
++}
++
++inline int esp_debugfs_init(void)
++{
++	return -EPERM;
++}
++
++inline void esp_debugfs_exit(void)
++{
++
++}
++
++#endif
++
++
++void show_buf(u8 * buf, u32 len)
++{
++//      print_hex_dump(KERN_DEBUG, "",  DUMP_PREFIX_OFFSET, 16, 1, buf, len, true);
++#if 1
++	int i = 0, j;
++
++	printk(KERN_INFO "\n++++++++++++++++show rbuf+++++++++++++++\n");
++	for (i = 0; i < (len / 16); i++) {
++		j = i * 16;
++		printk(KERN_INFO
++		       "0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x \n",
++		       buf[j], buf[j + 1], buf[j + 2], buf[j + 3],
++		       buf[j + 4], buf[j + 5], buf[j + 6], buf[j + 7],
++		       buf[j + 8], buf[j + 9], buf[j + 10], buf[j + 11],
++		       buf[j + 12], buf[j + 13], buf[j + 14], buf[j + 15]);
++	}
++	printk(KERN_INFO "\n++++++++++++++++++++++++++++++++++++++++\n");
++#endif				//0000
++}
++
++#ifdef HOST_RC
++static u8 get_cnt(u32 cnt_store, int idx)
++{
++	int shift = idx << 2;
++
++	return (u8) ((cnt_store >> shift) & 0xf);
++}
++
++void esp_show_rcstatus(struct sip_rc_status *rcstatus)
++{
++	int i;
++	char msg[82];
++	char rcstr[16];
++	u32 cnt_store = rcstatus->rc_cnt_store;
++
++	memset(msg, 0, sizeof(msg));
++	memset(rcstr, 0, sizeof(rcstr));
++
++	printk(KERN_INFO "rcstatus map 0x%08x cntStore 0x%08x\n",
++	       rcstatus->rc_map, rcstatus->rc_cnt_store);
++
++	for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
++		if (rcstatus->rc_map & BIT(i)) {
++			sprintf(rcstr, "rcIdx %d, cnt %d ", i,
++				get_cnt(cnt_store, i));
++			strcat(msg, rcstr);
++		}
++	}
++	printk(KERN_INFO "%s \n", msg);
++}
++
++void esp_show_tx_rates(struct ieee80211_tx_rate *rates)
++{
++	int i;
++	char msg[128];
++	char rcstr[32];
++
++	memset(msg, 0, sizeof(msg));
++	memset(rcstr, 0, sizeof(rcstr));
++
++	for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
++		if (rates->idx != -1) {
++			sprintf(rcstr, "Idx %d, cnt %d, flag %02x ",
++				rates->idx, rates->count, rates->flags);
++			strcat(msg, rcstr);
++		}
++		rates++;
++	}
++	strcat(msg, "\n");
++	printk(KERN_INFO "%s \n", msg);
++}
++#endif				/* HOST_RC */
+diff --git a/drivers/net/wireless/esp8089/esp_debug.h b/drivers/net/wireless/esp8089/esp_debug.h
+new file mode 100644
+index 000000000000..bab695d34bfb
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_debug.h
+@@ -0,0 +1,101 @@
++/*
++ * Copyright (c) 2011-2014 Espressif System.
++ *
++ * esp debug
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _DEBUG_H_
++
++#ifdef ASSERT_PANIC
++#define ESSERT(v) BUG_ON(!(v))
++#else
++#define ESSERT(v) if(!(v)) printk("ESSERT:%s %d\n", __FILE__, __LINE__)
++#endif
++
++
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <asm/uaccess.h>
++
++typedef enum esp_type {
++	ESP_BOOL,
++	ESP_U8,
++	ESP_U16,
++	ESP_U32,
++	ESP_U64
++} esp_type;
++
++void esp_dump_var(const char *name, struct dentry *parent,
++			    void *value, esp_type type);
++
++void esp_dump_array(const char *name, struct dentry *parent,
++			      struct debugfs_blob_wrapper *blob);
++
++void esp_dump(const char *name, struct dentry *parent,
++			void *data, int size);
++
++struct dentry *esp_debugfs_add_sub_dir(const char *name);
++
++int esp_debugfs_init(void);
++
++void esp_debugfs_exit(void);
++
++enum {
++	ESP_DBG_ERROR = BIT(0),
++	ESP_DBG_TRACE = BIT(1),
++	ESP_DBG_LOG = BIT(2),
++	ESP_DBG = BIT(3),
++	ESP_SHOW = BIT(4),
++	ESP_DBG_TXAMPDU = BIT(5),
++	ESP_DBG_OP = BIT(6),
++	ESP_DBG_PS = BIT(7),
++	ESP_ATE = BIT(8),
++	ESP_DBG_ALL = 0xffffffff
++};
++
++extern unsigned int esp_msg_level;
++
++#ifdef ESP_ANDROID_LOGGER
++extern bool log_off;
++#endif				/* ESP_ANDROID_LOGGER */
++
++#ifdef ESP_ANDROID_LOGGER
++#include "esp_file.h"
++#define esp_dbg(mask, fmt, args...) do {                  \
++        if (esp_msg_level & mask)   			  \
++	{						  \
++		if (log_off)      		          \
++			printk(fmt, ##args);              \
++		else 					              \
++            		logger_write(4, "esp_wifi", fmt, ##args);     \
++	}							      \
++    } while (0)
++#else
++#define esp_dbg(mask, fmt, args...) do {                  \
++        if (esp_msg_level & mask)                         \
++            printk("esp8089: " fmt, ##args);                          \
++    } while (0)
++#endif				/* ESP_ANDROID_LOGGER */
++
++void show_buf(u8 * buf, u32 len);
++
++#ifdef HOST_RC
++struct sip_rc_status;
++struct ieee80211_tx_rate;
++
++void esp_show_rcstatus(struct sip_rc_status *rcstatus);
++
++void esp_show_tx_rates(struct ieee80211_tx_rate *rates);
++#endif				/* HOST_RC */
++
++#endif				/* _DEBUG_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_ext.c b/drivers/net/wireless/esp8089/esp_ext.c
+new file mode 100644
+index 000000000000..541f27a6853f
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_ext.c
+@@ -0,0 +1,542 @@
++/*
++ * Copyright (c) 2010 -2013 Espressif System.
++ *
++ *   extended gpio
++ *    - interface for other driver or kernel
++ *    - gpio control
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifdef USE_EXT_GPIO
++
++#include <net/cfg80211.h>
++#include <linux/skbuff.h>
++#include <linux/bitops.h>
++#include <linux/version.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sd.h>
++#include <linux/completion.h>
++
++#include "esp_ext.h"
++#include "esp_debug.h"
++#include "esp_sip.h"
++#include "esp_sif.h"
++
++#ifdef EXT_GPIO_OPS
++extern void register_ext_gpio_ops(struct esp_ext_gpio_ops *ops);
++extern void unregister_ext_gpio_ops(void);
++
++static struct esp_ext_gpio_ops ext_gpio_ops = {
++	.gpio_request = ext_gpio_request,	/* gpio_request gpio_no from 0x0 to 0xf */
++	.gpio_release = ext_gpio_release,	/* gpio_release */
++	.gpio_set_mode = ext_gpio_set_mode,	/* gpio_set_mode, data is irq_func of irq_mode , default level of output_mode */
++	.gpio_get_mode = ext_gpio_get_mode,	/* gpio_get_mode, current mode */
++	.gpio_set_state = ext_gpio_set_output_state,	/* only output state, high level or low level */
++	.gpio_get_state = ext_gpio_get_state,	/* current state */
++	.irq_ack = ext_irq_ack,	/* ack interrupt */
++};
++
++
++#endif
++
++static struct esp_pub *ext_epub = NULL;
++
++static u16 intr_mask_reg = 0x0000;
++struct workqueue_struct *ext_irq_wkq = NULL;
++struct work_struct ext_irq_work;
++static struct mutex ext_mutex_lock;
++
++static struct ext_gpio_info gpio_list[EXT_GPIO_MAX_NUM] = {
++	{0, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{1, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{2, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{3, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{4, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{5, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{6, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{7, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{8, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{9, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{10, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{11, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{12, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{13, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{14, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{15, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++};
++
++static struct pending_intr_list_info esp_pending_intr_list = {
++	.start_pos = 0,
++	.end_pos = 0,
++	.curr_num = 0,
++};
++
++u16 ext_gpio_get_int_mask_reg(void)
++{
++	return intr_mask_reg;
++}
++
++int ext_gpio_request(int gpio_no)
++{
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_ERROR, "%s esp state is not ok\n",
++			__func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		return -ERANGE;
++	}
++
++	if (gpio_list[gpio_no].gpio_mode != EXT_GPIO_MODE_DISABLE) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR,
++			"%s gpio is already in used by other\n", __func__);
++		return -EPERM;
++	} else {
++		gpio_list[gpio_no].gpio_mode = EXT_GPIO_MODE_MAX;
++		mutex_unlock(&ext_mutex_lock);
++		return 0;
++	}
++}
++
++EXPORT_SYMBOL(ext_gpio_request);
++
++int ext_gpio_release(int gpio_no)
++{
++	int ret;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_ERROR, "%s esp state is not ok\n",
++			__func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		return -ERANGE;
++	}
++	sif_lock_bus(ext_epub);
++	ret =
++	    sif_config_gpio_mode(ext_epub, (u8) gpio_no,
++				 EXT_GPIO_MODE_DISABLE);
++	sif_unlock_bus(ext_epub);
++	if (ret) {
++		esp_dbg(ESP_DBG_ERROR, "%s gpio release error\n",
++			__func__);
++		mutex_unlock(&ext_mutex_lock);
++		return ret;
++	}
++
++	gpio_list[gpio_no].gpio_mode = EXT_GPIO_MODE_DISABLE;
++	gpio_list[gpio_no].gpio_state = EXT_GPIO_STATE_IDLE;
++	gpio_list[gpio_no].irq_handler = NULL;
++	intr_mask_reg &= ~(1 << gpio_no);
++
++	mutex_unlock(&ext_mutex_lock);
++
++	return 0;
++}
++
++EXPORT_SYMBOL(ext_gpio_release);
++
++int ext_gpio_set_mode(int gpio_no, int mode, void *data)
++{
++	u8 gpio_mode;
++	int ret;
++	struct ext_gpio_info backup_info;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_LOG, "%s esp state is not ok\n", __func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		return -ERANGE;
++	}
++
++	if (gpio_list[gpio_no].gpio_mode == EXT_GPIO_MODE_DISABLE) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR,
++			"%s gpio is not in occupy, please request gpio\n",
++			__func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	if (mode <= EXT_GPIO_MODE_OOB || mode >= EXT_GPIO_MODE_MAX) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s gpio mode unknown\n", __func__);
++		return -EOPNOTSUPP;
++	}
++
++	memcpy(&backup_info, &gpio_list[gpio_no],
++	       sizeof(struct ext_gpio_info));
++
++	gpio_list[gpio_no].gpio_mode = mode;
++	gpio_mode = (u8) mode;
++
++	switch (mode) {
++	case EXT_GPIO_MODE_INTR_POSEDGE:
++	case EXT_GPIO_MODE_INTR_NEGEDGE:
++	case EXT_GPIO_MODE_INTR_LOLEVEL:
++	case EXT_GPIO_MODE_INTR_HILEVEL:
++		if (!data) {
++			memcpy(&gpio_list[gpio_no], &backup_info,
++			       sizeof(struct ext_gpio_info));
++			esp_dbg(ESP_DBG_ERROR, "%s irq_handler is NULL\n",
++				__func__);
++			mutex_unlock(&ext_mutex_lock);
++			return -EINVAL;
++		}
++		gpio_list[gpio_no].irq_handler = (ext_irq_handler_t) data;
++		intr_mask_reg |= (1 << gpio_no);
++		break;
++	case EXT_GPIO_MODE_OUTPUT:
++		if (!data) {
++			memcpy(&gpio_list[gpio_no], &backup_info,
++			       sizeof(struct ext_gpio_info));
++			esp_dbg(ESP_DBG_ERROR,
++				"%s output default value is NULL\n",
++				__func__);
++			mutex_unlock(&ext_mutex_lock);
++			return -EINVAL;
++		}
++		*(int *) data = (*(int *) data == 0 ? 0 : 1);
++		gpio_mode = (u8) (((*(int *) data) << 4) | gpio_mode);
++	default:
++		gpio_list[gpio_no].irq_handler = NULL;
++		intr_mask_reg &= ~(1 << gpio_no);
++		break;
++	}
++
++	sif_lock_bus(ext_epub);
++	ret = sif_config_gpio_mode(ext_epub, (u8) gpio_no, gpio_mode);
++	sif_unlock_bus(ext_epub);
++	if (ret) {
++		memcpy(&gpio_list[gpio_no], &backup_info,
++		       sizeof(struct ext_gpio_info));
++		esp_dbg(ESP_DBG_ERROR, "%s gpio set error\n", __func__);
++		mutex_unlock(&ext_mutex_lock);
++		return ret;
++	}
++
++	mutex_unlock(&ext_mutex_lock);
++	return 0;
++}
++
++EXPORT_SYMBOL(ext_gpio_set_mode);
++
++int ext_gpio_get_mode(int gpio_no)
++{
++	int gpio_mode;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_LOG, "%s esp state is not ok\n", __func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		mutex_unlock(&ext_mutex_lock);
++		return -ERANGE;
++	}
++
++	gpio_mode = gpio_list[gpio_no].gpio_mode;
++
++	mutex_unlock(&ext_mutex_lock);
++
++	return gpio_mode;
++}
++
++EXPORT_SYMBOL(ext_gpio_get_mode);
++
++
++int ext_gpio_set_output_state(int gpio_no, int state)
++{
++	int ret;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_LOG, "%s esp state is not ok\n", __func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		return -ERANGE;
++	}
++
++	if (gpio_list[gpio_no].gpio_mode != EXT_GPIO_MODE_OUTPUT) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR,
++			"%s gpio is not in output state, please request gpio or set output state\n",
++			__func__);
++		return -EOPNOTSUPP;
++	}
++
++	if (state != EXT_GPIO_STATE_LOW && state != EXT_GPIO_STATE_HIGH) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s gpio state unknown\n",
++			__func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	sif_lock_bus(ext_epub);
++	ret =
++	    sif_set_gpio_output(ext_epub, 1 << gpio_no, state << gpio_no);
++	sif_unlock_bus(ext_epub);
++	if (ret) {
++		esp_dbg(ESP_DBG_ERROR, "%s gpio state set error\n",
++			__func__);
++		mutex_unlock(&ext_mutex_lock);
++		return ret;
++	}
++	gpio_list[gpio_no].gpio_state = state;
++
++	mutex_unlock(&ext_mutex_lock);
++
++	return 0;
++}
++
++EXPORT_SYMBOL(ext_gpio_set_output_state);
++
++int ext_gpio_get_state(int gpio_no)
++{
++	int ret;
++	u16 state;
++	u16 mask;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_LOG, "%s esp state is not ok\n", __func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		mutex_unlock(&ext_mutex_lock);
++		return -ERANGE;
++	}
++
++	if (gpio_list[gpio_no].gpio_mode == EXT_GPIO_MODE_OUTPUT) {
++		state = gpio_list[gpio_no].gpio_state;
++	} else if (gpio_list[gpio_no].gpio_mode == EXT_GPIO_MODE_INPUT) {
++		sif_lock_bus(ext_epub);
++		ret = sif_get_gpio_input(ext_epub, &mask, &state);
++		sif_unlock_bus(ext_epub);
++		if (ret) {
++			esp_dbg(ESP_DBG_ERROR,
++				"%s get gpio_input state error\n",
++				__func__);
++			mutex_unlock(&ext_mutex_lock);
++			return ret;
++		}
++	} else {
++		esp_dbg(ESP_DBG_ERROR,
++			"%s gpio_state is not input or output\n",
++			__func__);
++		mutex_unlock(&ext_mutex_lock);
++		return -EOPNOTSUPP;
++	}
++	mutex_unlock(&ext_mutex_lock);
++
++	return (state & (1 << gpio_no)) ? 1 : 0;
++}
++
++EXPORT_SYMBOL(ext_gpio_get_state);
++
++int ext_irq_ack(int gpio_no)
++{
++	int ret;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_LOG, "%s esp state is not ok\n", __func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		mutex_unlock(&ext_mutex_lock);
++		return -ERANGE;
++	}
++
++	if (gpio_list[gpio_no].gpio_mode != EXT_GPIO_MODE_INTR_POSEDGE
++	    && gpio_list[gpio_no].gpio_mode != EXT_GPIO_MODE_INTR_NEGEDGE
++	    && gpio_list[gpio_no].gpio_mode != EXT_GPIO_MODE_INTR_LOLEVEL
++	    && gpio_list[gpio_no].gpio_mode !=
++	    EXT_GPIO_MODE_INTR_HILEVEL) {
++		esp_dbg(ESP_DBG_ERROR, "%s gpio mode is not intr mode\n",
++			__func__);
++		mutex_unlock(&ext_mutex_lock);
++		return -ENOTRECOVERABLE;
++	}
++
++	sif_lock_bus(ext_epub);
++	ret = sif_set_gpio_output(ext_epub, 0x00, 1 << gpio_no);
++	sif_unlock_bus(ext_epub);
++	if (ret) {
++		esp_dbg(ESP_DBG_ERROR, "%s gpio intr ack error\n",
++			__func__);
++		mutex_unlock(&ext_mutex_lock);
++		return ret;
++	}
++
++	mutex_unlock(&ext_mutex_lock);
++	return 0;
++}
++
++EXPORT_SYMBOL(ext_irq_ack);
++
++void show_status(void)
++{
++	int i = 0;
++	for (i = 0; i < MAX_PENDING_INTR_LIST; i++)
++		esp_dbg(ESP_DBG_ERROR, "status[%d] = [0x%04x]\n", i,
++			esp_pending_intr_list.pending_intr_list[i]);
++
++	esp_dbg(ESP_DBG_ERROR, "start_pos[%d]\n",
++		esp_pending_intr_list.start_pos);
++	esp_dbg(ESP_DBG_ERROR, "end_pos[%d]\n",
++		esp_pending_intr_list.end_pos);
++	esp_dbg(ESP_DBG_ERROR, "curr_num[%d]\n",
++		esp_pending_intr_list.curr_num);
++
++}
++void esp_tx_work(struct work_struct *work)
++{
++	int i;
++	u16 tmp_intr_status_reg;
++
++	esp_dbg(ESP_DBG_TRACE, "%s enter\n", __func__);
++
++	spin_lock(&esp_pending_intr_list.spin_lock);
++
++	tmp_intr_status_reg =
++	    esp_pending_intr_list.pending_intr_list[esp_pending_intr_list.
++						    start_pos];
++
++	esp_pending_intr_list.pending_intr_list[esp_pending_intr_list.
++						start_pos] = 0x0000;
++	esp_pending_intr_list.start_pos =
++	    (esp_pending_intr_list.start_pos + 1) % MAX_PENDING_INTR_LIST;
++	esp_pending_intr_list.curr_num--;
++
++	spin_unlock(&esp_pending_intr_list.spin_lock);
++
++	for (i = 0; i < EXT_GPIO_MAX_NUM; i++) {
++		if (tmp_intr_status_reg & (1 << i)
++		    && (gpio_list[i].irq_handler))
++			gpio_list[i].irq_handler();
++	}
++
++	spin_lock(&esp_pending_intr_list.spin_lock);
++	if (esp_pending_intr_list.curr_num > 0)
++		queue_work(ext_irq_wkq, &ext_irq_work);
++	spin_unlock(&esp_pending_intr_list.spin_lock);
++}
++
++void ext_gpio_int_process(u16 value)
++{
++	if (value == 0x00)
++		return;
++
++	esp_dbg(ESP_DBG_TRACE, "%s enter\n", __func__);
++
++	/* intr cycle queue is full, wait */
++	while (esp_pending_intr_list.curr_num >= MAX_PENDING_INTR_LIST) {
++		udelay(1);
++	}
++
++	spin_lock(&esp_pending_intr_list.spin_lock);
++
++	esp_pending_intr_list.pending_intr_list[esp_pending_intr_list.
++						end_pos] = value;
++	esp_pending_intr_list.end_pos =
++	    (esp_pending_intr_list.end_pos + 1) % MAX_PENDING_INTR_LIST;
++	esp_pending_intr_list.curr_num++;
++
++	queue_work(ext_irq_wkq, &ext_irq_work);
++
++	spin_unlock(&esp_pending_intr_list.spin_lock);
++}
++
++int ext_gpio_init(struct esp_pub *epub)
++{
++	esp_dbg(ESP_DBG_ERROR, "%s enter\n", __func__);
++
++	ext_irq_wkq = create_singlethread_workqueue("esp_ext_irq_wkq");
++	if (ext_irq_wkq == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "%s create workqueue error\n",
++			__func__);
++		return -EACCES;
++	}
++
++	INIT_WORK(&ext_irq_work, esp_tx_work);
++	mutex_init(&ext_mutex_lock);
++
++	ext_epub = epub;
++
++	if (ext_epub == NULL)
++		return -EINVAL;
++
++#ifdef EXT_GPIO_OPS
++	register_ext_gpio_ops(&ext_gpio_ops);
++#endif
++
++	return 0;
++}
++
++void ext_gpio_deinit(void)
++{
++	esp_dbg(ESP_DBG_ERROR, "%s enter\n", __func__);
++
++#ifdef EXT_GPIO_OPS
++	unregister_ext_gpio_ops();
++#endif
++	ext_epub = NULL;
++	cancel_work_sync(&ext_irq_work);
++
++	if (ext_irq_wkq)
++		destroy_workqueue(ext_irq_wkq);
++
++}
++
++#endif				/* USE_EXT_GPIO */
+diff --git a/drivers/net/wireless/esp8089/esp_ext.h b/drivers/net/wireless/esp8089/esp_ext.h
+new file mode 100644
+index 000000000000..0eeba4d22111
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_ext.h
+@@ -0,0 +1,100 @@
++#ifdef USE_EXT_GPIO
++
++#ifndef _ESP_EXT_H_
++#define _ESP_EXT_H_
++
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include "esp_sip.h"
++
++#define MAX_PENDING_INTR_LIST 16
++
++#ifdef EXT_GPIO_OPS
++typedef struct esp_ext_gpio_ops {
++	int (*gpio_request) (int gpio_no);	/* gpio_request gpio_no from 0x0 to 0xf */
++	int (*gpio_release) (int gpio_no);	/* gpio_release */
++	int (*gpio_set_mode) (int gpio_no, int mode, void *data);	/* gpio_set_mode, data is irq_func of irq_mode , default level of output_mode */
++	int (*gpio_get_mode) (int gpio_no);	/* gpio_get_mode, current mode */
++	int (*gpio_set_state) (int gpio_no, int state);	/* only output state, high level or low level */
++	int (*gpio_get_state) (int gpio_no);	/* current state */
++	int (*irq_ack) (int gpio_no);	/* ack interrupt */
++} esp_ext_gpio_ops_t;
++#endif
++
++typedef enum EXT_GPIO_NO {
++	EXT_GPIO_GPIO0 = 0,
++	EXT_GPIO_U0TXD,
++	EXT_GPIO_GPIO2,
++	EXT_GPIO_U0RXD,
++	EXT_GPIO_GPIO4,
++	EXT_GPIO_GPIO5,
++	EXT_GPIO_SD_CLK,
++	EXT_GPIO_SD_DATA0,
++	EXT_GPIO_SD_DATA1,
++	EXT_GPIO_SD_DATA2,
++	EXT_GPIO_SD_DATA3,
++	EXT_GPIO_SD_CMD,
++	EXT_GPIO_MTDI,
++	EXT_GPIO_MTCK,
++	EXT_GPIO_MTMS,
++	EXT_GPIO_MTDO,
++	EXT_GPIO_MAX_NUM
++} EXT_GPIO_NO_T;
++
++typedef enum EXT_GPIO_MODE {	//dir           def     pullup  mode    wake
++	EXT_GPIO_MODE_OOB = 0,	//output        1       0       n/a     n/a
++	EXT_GPIO_MODE_OUTPUT,	//output        /       0       n/a     n/a
++	EXT_GPIO_MODE_DISABLE,	//input         n/a     0       DIS     n/a
++	EXT_GPIO_MODE_INTR_POSEDGE,	//input         n/a     0       POS     1
++	EXT_GPIO_MODE_INTR_NEGEDGE,	//input         n/a     1       NEG     1
++	EXT_GPIO_MODE_INPUT,	//input         n/a     0       ANY     1
++	EXT_GPIO_MODE_INTR_LOLEVEL,	//input         n/a     1       LOW     1
++	EXT_GPIO_MODE_INTR_HILEVEL,	//input         n/a     0       HIGH    1
++	EXT_GPIO_MODE_MAX,
++} EXT_GPIO_MODE_T;
++
++typedef enum EXT_GPIO_STATE {
++	EXT_GPIO_STATE_LOW,
++	EXT_GPIO_STATE_HIGH,
++	EXT_GPIO_STATE_IDLE
++} EXT_GPIO_STATE_T;
++
++typedef irqreturn_t(*ext_irq_handler_t) (void);
++
++struct ext_gpio_info {
++	int gpio_no;
++	int gpio_mode;
++	int gpio_state;
++	ext_irq_handler_t irq_handler;
++};
++
++struct pending_intr_list_info {
++	u16 pending_intr_list[MAX_PENDING_INTR_LIST];
++	int start_pos;
++	int end_pos;
++	int curr_num;
++	spinlock_t spin_lock;
++};
++
++u16 ext_gpio_get_int_mask_reg(void);
++
++/* for extern user start */
++int ext_gpio_request(int gpio_no);
++int ext_gpio_release(int gpio_no);
++
++int ext_gpio_set_mode(int gpio_no, int mode, void *data);
++int ext_gpio_get_mode(int gpio_no);
++
++int ext_gpio_set_output_state(int gpio_no, int state);
++int ext_gpio_get_state(int gpio_no);
++
++int ext_irq_ack(int gpio_no);
++/* for extern user end */
++
++void ext_gpio_int_process(u16 value);
++
++int ext_gpio_init(struct esp_pub *epub);
++void ext_gpio_deinit(void);
++#endif				/* _ESP_EXT_H_ */
++
++#endif				/* USE_EXT_GPIO */
+diff --git a/drivers/net/wireless/esp8089/esp_file.c b/drivers/net/wireless/esp8089/esp_file.c
+new file mode 100644
+index 000000000000..ea702f010eec
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_file.c
+@@ -0,0 +1,258 @@
++/*
++ * Copyright (c) 2010 -2014 Espressif System.
++ *
++ *   file operation in kernel space
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/fs.h>
++#include <linux/vmalloc.h>
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/moduleparam.h>
++#include <linux/firmware.h>
++#include <linux/netdevice.h>
++#include <linux/aio.h>
++#include <linux/property.h>
++#include <linux/of.h>
++#include "esp_file.h"
++#include "esp_debug.h"
++#include "esp_sif.h"
++
++static int mod_parm_crystal = -1;
++module_param_named(crystal, mod_parm_crystal, int, 0444);
++MODULE_PARM_DESC(crystal, "crystal frequency: 0=40MHz, 1=26MHz, 2=24MHz");
++
++struct esp_init_table_elem esp_init_table[MAX_ATTR_NUM] = {
++	/*
++	 * Crystal type:
++	 * 0: 40MHz (default)
++	 * 1: 26MHz (ESP8266 ESP-12F)
++	 * 2: 24MHz
++	 */
++	{"crystal_26M_en", 48, 0},
++	/*
++	 * Output crystal clock to pin:
++	 * 0: None
++	 * 1: GPIO1
++	 * 2: URXD0
++	 */
++	{"test_xtal", 49, 0},
++	/*
++	 * Host SDIO mode:
++	 * 0: Auto by pin strapping
++	 * 1: SDIO data output on negative edges (SDIO v1.1)
++	 * 2: SDIO data output on positive edges (SDIO v2.0)
++	 */
++	{"sdio_configure", 50, 2},
++	/*
++	 * WiFi/Bluetooth co-existence with BK3515A BT chip
++	 * 0: None
++	 * 1: GPIO0->WLAN_ACTIVE, MTMS->BT_ACTIVE, MTDI->BT_PRIORITY,
++	 *    U0TXD->ANT_SEL_BT, U0RXD->ANT_SEL_WIFI
++	 */
++	{"bt_configure", 51, 0},
++	/*
++	 * Antenna selection:
++	 * 0: Antenna is for WiFi
++	 * 1: Antenna is for Bluetooth
++	 */
++	{"bt_protocol", 52, 0},
++	/*
++	 * Dual antenna configuration mode:
++	 * 0: None
++	 * 1: U0RXD + XPD_DCDC
++	 * 2: U0RXD + GPIO0
++	 * 3: U0RXD + U0TXD
++	 */
++	{"dual_ant_configure", 53, 0},
++	/*
++	 * Firmware debugging output pin:
++	 * 0: None
++	 * 1: UART TX on GPIO2
++	 * 2: UART TX on U0TXD
++	 */
++	{"test_uart_configure", 54, 2},
++	/*
++	 * Whether to share crystal clock with BT (in sleep mode):
++	 * 0: no
++	 * 1: always on
++	 * 2: automatically on according to XPD_DCDC
++	 */
++	{"share_xtal", 55, 0},
++	/*
++	 * Allow chip to be woken up during sleep on pin:
++	 * 0: None
++	 * 1: XPD_DCDC
++	 * 2: GPIO0
++	 * 3: Both XPD_DCDC and GPIO0
++	 */
++	{"gpio_wake", 56, 0},
++	{"no_auto_sleep", 57, 0},
++	{"speed_suspend", 58, 0},
++	{"attr11", -1, -1},
++	{"attr12", -1, -1},
++	{"attr13", -1, -1},
++	{"attr14", -1, -1},
++	{"attr15", -1, -1},
++	//attr that is not send to target
++	/*
++	 * Allow chip to be reset by GPIO pin:
++	 * 0: no
++	 * 1: yes
++	 */
++	{"ext_rst", -1, 0},
++	{"wakeup_gpio", -1, 12},
++	{"ate_test", -1, 0},
++	{"attr19", -1, -1},
++	{"attr20", -1, -1},
++	{"attr21", -1, -1},
++	{"attr22", -1, -1},
++	{"attr23", -1, -1},
++};
++
++/*
++ * Export part of the configuration related to first initiliazition to the esp8089
++ */
++void esp_conf_upload_first(void)
++{
++	int i;
++
++	for (i = 0; i < MAX_ATTR_NUM; i++) {
++		if (esp_init_table[i].value < 0)
++			continue;
++
++		if (!strcmp(esp_init_table[i].attr, "share_xtal"))
++			sif_record_bt_config(esp_init_table[i].value);
++		else if (!strcmp(esp_init_table[i].attr, "ext_rst"))
++			sif_record_rst_config(esp_init_table[i].value);
++		else if (!strcmp(esp_init_table[i].attr, "wakeup_gpio"))
++			sif_record_wakeup_gpio_config(esp_init_table[i].value);
++		else if (!strcmp(esp_init_table[i].attr, "ate_test"))
++			sif_record_ate_config(esp_init_table[i].value);
++	}
++}
++
++/*
++ * Export part of the configuration related to second initiliazition
++ */
++void esp_conf_upload_second(u8 * init_data_buf, int buf_size)
++{
++	int i;
++
++	for (i = 0; i < MAX_FIX_ATTR_NUM; i++) {
++		if (esp_init_table[i].offset > -1
++		    && esp_init_table[i].offset < buf_size
++		    && esp_init_table[i].value > -1) {
++			*(u8 *) (init_data_buf +
++				 esp_init_table[i].offset) =
++			    esp_init_table[i].value;
++		} else if (esp_init_table[i].offset > buf_size) {
++			esp_dbg(ESP_DBG_ERROR,
++				"%s: offset[%d] longer than init_data_buf len[%d] Ignore\n",
++				__FUNCTION__, esp_init_table[i].offset,
++				buf_size);
++		}
++	}
++
++}
++
++
++void esp_conf_init(struct device *dev)
++{
++
++	struct device_node *np = dev->of_node;
++
++	if (np) {
++
++		u32 value;
++
++		if (!of_property_read_u32(np, "esp,crystal-26M-en", &value))
++			esp_conf_set_attr("crystal_26M_en", value);
++
++		if (!of_property_read_u32(np, "esp,sdio-configure", &value))
++			esp_conf_set_attr("sdio_configure", value);
++
++		if (of_property_read_bool(np, "esp,shared-xtal"))
++			esp_conf_set_attr("share_xtal", 1);
++
++		if (!of_property_read_u32(np, "esp,gpio-wake", &value))
++			esp_conf_set_attr("gpio_wake", value);
++
++		if (!of_property_read_u32(np, "esp,wakeup-gpio", &value))
++			esp_conf_set_attr("wakeup_gpio", value);
++
++		if (of_property_read_bool(np, "esp,configure-dual-antenna"))
++			esp_conf_set_attr("dual_ant_configure", 1);
++
++		if (of_property_read_bool(np, "esp,no-auto-sleep"))
++			esp_conf_set_attr("no_auto_sleep", 1);
++
++		if (of_property_read_bool(np, "esp,test-xtal"))
++			esp_conf_set_attr("test_xtal", 1);
++
++		if (of_property_read_bool(np, "esp,bt-configure"))
++			esp_conf_set_attr("bt_configure", 1);
++
++		if (!of_property_read_u32(np, "esp,bt-protocol", &value))
++			esp_conf_set_attr("bt_protocol", value);
++
++		if (of_property_read_bool(np, "esp,test-uart-configure"))
++			esp_conf_set_attr("test_uart_configure", 1);
++
++		if (of_property_read_bool(np, "esp,speed-suspend"))
++			esp_conf_set_attr("speed_suspend", 1);
++
++		if (of_property_read_bool(np, "esp,ate-test"))
++			esp_conf_set_attr("ate_test", 1);
++
++		if (!of_property_read_u32(np, "esp,ext-rst", &value))
++			esp_conf_set_attr("ext_rst", value);
++
++	}
++
++	if (mod_parm_crystal >= 0 && mod_parm_crystal <= 2)
++		esp_conf_set_attr("crystal_26M_en", mod_parm_crystal);
++
++
++	esp_conf_show_attrs();
++
++}
++
++int esp_conf_set_attr(char *name, u8 value) {
++
++	int i;
++
++	for (i = 0; i < MAX_ATTR_NUM; i++) {
++
++		if (strcmp(esp_init_table[i].attr, name) == 0) {
++			esp_dbg(ESP_DBG, "set config: %s value: %d", name, value);
++			esp_init_table[i].value = value;
++			return 0;
++		}
++
++	}
++
++	return -1;
++
++}
++
++void esp_conf_show_attrs(void)
++{
++	int i;
++	for (i = 0; i < MAX_ATTR_NUM; i++)
++		if (esp_init_table[i].offset > -1)
++			esp_dbg(ESP_SHOW, "config parm:%s (id:%d), value: %d\n",
++				esp_init_table[i].attr,
++				esp_init_table[i].offset,
++				esp_init_table[i].value);
++}
+diff --git a/drivers/net/wireless/esp8089/esp_file.h b/drivers/net/wireless/esp8089/esp_file.h
+new file mode 100644
+index 000000000000..5ba39c626baa
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_file.h
+@@ -0,0 +1,43 @@
++/*
++ * Copyright (c) 2010 -2014 Espressif System.
++ *
++ *   file operation in kernel space
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_FILE_H_
++#define _ESP_FILE_H_
++
++#include <linux/version.h>
++#include <linux/firmware.h>
++
++#define E_ROUND_UP(x, y)  ((((x) + ((y) - 1)) / (y)) * (y))
++
++#define CONF_ATTR_LEN 24
++#define CONF_VAL_LEN 3
++#define MAX_ATTR_NUM 24
++#define MAX_FIX_ATTR_NUM 16
++#define MAX_BUF_LEN ((CONF_ATTR_LEN + CONF_VAL_LEN + 2) * MAX_ATTR_NUM + 2)
++
++struct esp_init_table_elem {
++	char attr[CONF_ATTR_LEN];
++	int offset;
++	short value;
++};
++
++void esp_conf_init(struct device *dev);
++void esp_conf_upload_first(void);
++void esp_conf_upload_second(u8 * init_data_buf, int buf_size);
++int esp_conf_set_attr(char *name, u8 value);
++void esp_conf_show_attrs(void);
++
++#endif				/* _ESP_FILE_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_init_data.h b/drivers/net/wireless/esp8089/esp_init_data.h
+new file mode 100644
+index 000000000000..16f451affd1e
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_init_data.h
+@@ -0,0 +1,7 @@
++static char esp_init_data[] =
++    { 0x5, 0x0, 4, 2, 5, 5, 5, 2, 5, 0, 4, 5, 5, 4, 5, 5, 4, -2, -3, -1,
++-16, -16, -16, -32, -32, -32, 204, 1, 0xff, 0xff, 0, 0, 0, 0, 82, 78, 74, 68, 64, 56, 0,
++0, 1, 1, 2, 3, 4, 5, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 240, 10, 0x0, 0x0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0 };
+diff --git a/drivers/net/wireless/esp8089/esp_io.c b/drivers/net/wireless/esp8089/esp_io.c
+new file mode 100644
+index 000000000000..6c5c01aad4e5
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_io.c
+@@ -0,0 +1,639 @@
++/*
++ * Copyright (c) 2009 - 2014 Espressif System.
++ *   IO interface 
++ *    - sdio/spi common i/f driver
++ *    - target sdio hal
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/mmc/sdio_func.h>
++#include "esp_sif.h"
++#include "slc_host_register.h"
++#include "esp_debug.h"
++
++#ifdef SIF_DEBUG_DSR_DUMP_REG
++static void dump_slc_regs(struct slc_host_regs *regs);
++#endif				/* SIF_DEBUG_DSR_DUMP_REG */
++
++int esp_common_read(struct esp_pub *epub, u8 * buf, u32 len, int sync,
++		    bool noround)
++{
++	if (sync) {
++		return sif_lldesc_read_sync(epub, buf, len);
++	} else {
++		return sif_lldesc_read_raw(epub, buf, len, noround);
++	}
++}
++
++
++int esp_common_write(struct esp_pub *epub, u8 * buf, u32 len, int sync)
++{
++	if (sync) {
++		return sif_lldesc_write_sync(epub, buf, len);
++	} else {
++		return sif_lldesc_write_raw(epub, buf, len);
++	}
++}
++
++
++int esp_common_read_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++			      u32 len, int sync)
++{
++	if (sync) {
++		return sif_io_sync(epub, addr, buf, len,
++				   SIF_FROM_DEVICE | SIF_SYNC |
++				   SIF_BYTE_BASIS | SIF_INC_ADDR);
++	} else {
++		return sif_io_raw(epub, addr, buf, len,
++				  SIF_FROM_DEVICE | SIF_BYTE_BASIS |
++				  SIF_INC_ADDR);
++	}
++
++}
++
++
++int esp_common_write_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++			       u32 len, int sync)
++{
++	if (sync) {
++		return sif_io_sync(epub, addr, buf, len,
++				   SIF_TO_DEVICE | SIF_SYNC |
++				   SIF_BYTE_BASIS | SIF_INC_ADDR);
++	} else {
++		return sif_io_raw(epub, addr, buf, len,
++				  SIF_TO_DEVICE | SIF_BYTE_BASIS |
++				  SIF_INC_ADDR);
++	}
++}
++
++int esp_common_readbyte_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++				  int sync)
++{
++	if (sync) {
++		int res;
++		sif_lock_bus(epub);
++		*buf = sdio_io_readb(epub, addr, &res);
++		sif_unlock_bus(epub);
++		return res;
++	} else {
++		int res;
++		*buf = sdio_io_readb(epub, addr, &res);
++		return res;
++	}
++
++}
++
++
++
++int esp_common_writebyte_with_addr(struct esp_pub *epub, u32 addr, u8 buf,
++				   int sync)
++{
++	if (sync) {
++		int res;
++		sif_lock_bus(epub);
++		sdio_io_writeb(epub, buf, addr, &res);
++		sif_unlock_bus(epub);
++		return res;
++	} else {
++		int res;
++		sdio_io_writeb(epub, buf, addr, &res);
++		return res;
++	}
++}
++
++int sif_read_reg_window(struct esp_pub *epub, unsigned int reg_addr,
++			u8 * value)
++{
++	u8 *p_tbuf = NULL;
++	int ret = 0;
++	int retry = 20;
++
++	reg_addr >>= 2;
++	if (reg_addr > 0x1f)
++		return -1;
++
++	p_tbuf = kzalloc(4, GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++
++	p_tbuf[0] = 0x80 | (reg_addr & 0x1f);
++
++	ret =
++	    esp_common_write_with_addr(epub, SLC_HOST_WIN_CMD, p_tbuf, 1,
++				       ESP_SIF_NOSYNC);
++
++	if (ret == 0) {
++		do {
++			if (retry < 20)
++				mdelay(10);
++			retry--;
++			ret =
++			    esp_common_read_with_addr(epub,
++						      SLC_HOST_STATE_W0,
++						      p_tbuf, 4,
++						      ESP_SIF_NOSYNC);
++		} while (retry > 0 && ret != 0);
++	}
++
++	if (ret == 0)
++		memcpy(value, p_tbuf, 4);
++
++	kfree(p_tbuf);
++	return ret;
++}
++
++int sif_write_reg_window(struct esp_pub *epub, unsigned int reg_addr,
++			 u8 * value)
++{
++	u8 *p_tbuf = NULL;
++	int ret = 0;
++
++	reg_addr >>= 2;
++	if (reg_addr > 0x1f)
++		return -1;
++
++	p_tbuf = kzalloc(8, GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++	memcpy(p_tbuf, value, 4);
++	p_tbuf[4] = 0xc0 | (reg_addr & 0x1f);
++
++	ret =
++	    esp_common_write_with_addr(epub, SLC_HOST_CONF_W5, p_tbuf, 5,
++				       ESP_SIF_NOSYNC);
++
++	kfree(p_tbuf);
++	return ret;
++}
++
++int sif_ack_target_read_err(struct esp_pub *epub)
++{
++	u32 value[1];
++	int ret;
++
++	ret = sif_read_reg_window(epub, SLC_RX_LINK, (u8 *) value);
++	if (ret)
++		return ret;
++	value[0] |= SLC_RXLINK_START;
++	ret = sif_write_reg_window(epub, SLC_RX_LINK, (u8 *) value);
++	return ret;
++}
++
++int sif_had_io_enable(struct esp_pub *epub)
++{
++	u32 *p_tbuf = NULL;
++	int ret;
++
++	p_tbuf = kzalloc(sizeof(u32), GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++
++	*p_tbuf =
++	    SLC_TXEOF_ENA | (0x4 << SLC_FIFO_MAP_ENA_S) | SLC_TX_DUMMY_MODE
++	    | SLC_HDA_MAP_128K | (0xFE << SLC_TX_PUSH_IDLE_NUM_S);
++	ret = sif_write_reg_window(epub, SLC_BRIDGE_CONF, (u8 *) p_tbuf);
++
++	if (ret)
++		goto _err;
++
++	*p_tbuf = 0x30;
++	ret =
++	    esp_common_write_with_addr((epub), SLC_HOST_CONF_W4 + 1,
++				       (u8 *) p_tbuf, 1, ESP_SIF_NOSYNC);
++
++	if (ret)
++		goto _err;
++	//set w3 0
++	*p_tbuf = 0x1;
++	ret =
++	    esp_common_write_with_addr((epub), SLC_HOST_CONF_W3,
++				       (u8 *) p_tbuf, 1, ESP_SIF_NOSYNC);
++
++      _err:
++	kfree(p_tbuf);
++	return ret;
++}
++
++typedef enum _SDIO_INTR_MODE {
++	SDIO_INTR_IB = 0,
++	SDIO_INTR_OOB_TOGGLE,
++	SDIO_INTR_OOB_HIGH_LEVEL,
++	SDIO_INTR_OOB_LOW_LEVEL,
++} SDIO_INTR_MODE;
++
++#define GEN_GPIO_SEL(_gpio_num, _sel_func, _intr_mode, _offset) (((_offset)<< 9 ) |((_intr_mode) << 7)|((_sel_func) << 4)|(_gpio_num))
++//bit[3:0] = gpio num, 2
++//bit[6:4] = gpio sel func, 0
++//bit[8:7] = gpio intr mode, SDIO_INTR_OOB_TOGGLE
++//bit[15:9] = register offset, 0x38
++
++u16 gpio_sel_sets[17] = {
++	GEN_GPIO_SEL(0, 0, SDIO_INTR_OOB_TOGGLE, 0x34),	//GPIO0
++	GEN_GPIO_SEL(1, 3, SDIO_INTR_OOB_TOGGLE, 0x18),	//U0TXD
++	GEN_GPIO_SEL(2, 0, SDIO_INTR_OOB_TOGGLE, 0x38),	//GPIO2
++	GEN_GPIO_SEL(3, 3, SDIO_INTR_OOB_TOGGLE, 0x14),	//U0RXD
++	GEN_GPIO_SEL(4, 0, SDIO_INTR_OOB_TOGGLE, 0x3C),	//GPIO4
++	GEN_GPIO_SEL(5, 0, SDIO_INTR_OOB_TOGGLE, 0x40),	//GPIO5
++	GEN_GPIO_SEL(6, 3, SDIO_INTR_OOB_TOGGLE, 0x1C),	//SD_CLK
++	GEN_GPIO_SEL(7, 3, SDIO_INTR_OOB_TOGGLE, 0x20),	//SD_DATA0
++	GEN_GPIO_SEL(8, 3, SDIO_INTR_OOB_TOGGLE, 0x24),	//SD_DATA1
++	GEN_GPIO_SEL(9, 3, SDIO_INTR_OOB_TOGGLE, 0x28),	//SD_DATA2
++	GEN_GPIO_SEL(10, 3, SDIO_INTR_OOB_TOGGLE, 0x2C),	//SD_DATA3
++	GEN_GPIO_SEL(11, 3, SDIO_INTR_OOB_TOGGLE, 0x30),	//SD_CMD
++	GEN_GPIO_SEL(12, 3, SDIO_INTR_OOB_TOGGLE, 0x04),	//MTDI
++	GEN_GPIO_SEL(13, 3, SDIO_INTR_OOB_TOGGLE, 0x08),	//MTCK
++	GEN_GPIO_SEL(14, 3, SDIO_INTR_OOB_TOGGLE, 0x0C),	//MTMS
++	GEN_GPIO_SEL(15, 3, SDIO_INTR_OOB_TOGGLE, 0x10),	//MTDO
++	//pls do not change sel before, if you want to change intr mode,change the one blow
++	//GEN_GPIO_SEL(2, 0, SDIO_INTR_OOB_TOGGLE, 0x38)
++	GEN_GPIO_SEL(2, 0, SDIO_INTR_OOB_LOW_LEVEL, 0x38)
++};
++
++#if defined(USE_EXT_GPIO)
++u16 gpio_forbidden = 0;
++#endif
++
++int sif_interrupt_target(struct esp_pub *epub, u8 index)
++{
++	u8 low_byte = BIT(index);
++	return esp_common_writebyte_with_addr(epub, SLC_HOST_CONF_W4 + 2,
++					      low_byte, ESP_SIF_NOSYNC);
++
++}
++
++#ifdef USE_EXT_GPIO
++int sif_config_gpio_mode(struct esp_pub *epub, u8 gpio_num, u8 gpio_mode)
++{
++	u32 *p_tbuf = NULL;
++	int err;
++
++	if ((BIT(gpio_num) & gpio_forbidden) || gpio_num > 15)
++		return -EINVAL;
++
++	p_tbuf = kzalloc(sizeof(u32), GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++	*p_tbuf = (gpio_mode << 16) | gpio_sel_sets[gpio_num];
++	err =
++	    esp_common_write_with_addr(epub, SLC_HOST_CONF_W1,
++				       (u8 *) p_tbuf, sizeof(u32),
++				       ESP_SIF_NOSYNC);
++	kfree(p_tbuf);
++	if (err)
++		return err;
++
++	return sif_interrupt_target(epub, 4);
++}
++
++int sif_set_gpio_output(struct esp_pub *epub, u16 mask, u16 value)
++{
++	u32 *p_tbuf = NULL;
++	int err;
++
++	mask &= ~gpio_forbidden;
++	p_tbuf = kzalloc(sizeof(u32), GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++	*p_tbuf = (mask << 16) | value;
++	err =
++	    esp_common_write_with_addr(epub, SLC_HOST_CONF_W2,
++				       (u8 *) p_tbuf, sizeof(u32),
++				       ESP_SIF_NOSYNC);
++	kfree(p_tbuf);
++	if (err)
++		return err;
++
++	return sif_interrupt_target(epub, 5);
++}
++
++int sif_get_gpio_intr(struct esp_pub *epub, u16 intr_mask, u16 * value)
++{
++	u32 *p_tbuf = NULL;
++	int err;
++
++	p_tbuf = kzalloc(sizeof(u32), GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++	*p_tbuf = 0;
++	err =
++	    esp_common_read_with_addr(epub, SLC_HOST_CONF_W3,
++				      (u8 *) p_tbuf, sizeof(u32),
++				      ESP_SIF_NOSYNC);
++	if (err) {
++		kfree(p_tbuf);
++		return err;
++	}
++
++	*value = *p_tbuf & intr_mask;
++	kfree(p_tbuf);
++	if (*value == 0)
++		return 0;
++	return sif_interrupt_target(epub, 6);
++}
++
++int sif_get_gpio_input(struct esp_pub *epub, u16 * mask, u16 * value)
++{
++	u32 *p_tbuf = NULL;
++	int err;
++
++	err = sif_interrupt_target(epub, 3);
++	if (err)
++		return err;
++
++	udelay(20);
++	p_tbuf = kzalloc(sizeof(u32), GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++	*p_tbuf = 0;
++	err =
++	    esp_common_read_with_addr(epub, SLC_HOST_CONF_W3,
++				      (u8 *) p_tbuf, sizeof(u32),
++				      ESP_SIF_NOSYNC);
++	if (err) {
++		kfree(p_tbuf);
++		return err;
++	}
++
++	*mask = *p_tbuf >> 16;
++	*value = *p_tbuf & *mask;
++	kfree(p_tbuf);
++
++	return 0;
++}
++#endif
++
++void check_target_id(struct esp_pub *epub)
++{
++	u32 date;
++	int err = 0;
++	int i;
++
++	EPUB_CTRL_CHECK(epub, _err);
++
++	sif_lock_bus(epub);
++
++	for (i = 0; i < 4; i++) {
++		err =
++		    esp_common_readbyte_with_addr(epub, SLC_HOST_DATE + i,
++						  (u8 *) & date + i,
++						  ESP_SIF_NOSYNC);
++		err =
++		    esp_common_readbyte_with_addr(epub, SLC_HOST_ID + i,
++						  (u8 *) &
++						  EPUB_TO_CTRL(epub)->
++						  target_id + i,
++						  ESP_SIF_NOSYNC);
++	}
++
++	sif_unlock_bus(epub);
++
++	esp_dbg(ESP_DBG_LOG, "\n\n \t\t SLC data 0x%08x, ID 0x%08x\n\n",
++		date, EPUB_TO_CTRL(epub)->target_id);
++
++	switch (EPUB_TO_CTRL(epub)->target_id) {
++	case 0x100:
++		EPUB_TO_CTRL(epub)->slc_window_end_addr = 0x20000;
++		break;
++	case 0x600:
++		EPUB_TO_CTRL(epub)->slc_window_end_addr = 0x20000 - 0x800;
++
++		do {
++			u16 gpio_sel;
++			u8 low_byte = 0;
++			u8 high_byte = 0;
++			u8 byte2 = 0;
++			u8 byte3 = 0;
++#ifdef USE_OOB_INTR
++			gpio_sel = gpio_sel_sets[16];
++			low_byte = gpio_sel;
++			high_byte = gpio_sel >> 8;
++#ifdef USE_EXT_GPIO
++			gpio_forbidden |= BIT(gpio_sel & 0xf);
++#endif				/* USE_EXT_GPIO */
++#endif				/* USE_OOB_INTR */
++
++			if (sif_get_bt_config() == 1
++			    && sif_get_rst_config() != 1) {
++				u8 gpio_num = sif_get_wakeup_gpio_config();
++				gpio_sel = gpio_sel_sets[gpio_num];
++				byte2 = gpio_sel;
++				byte3 = gpio_sel >> 8;
++#ifdef USE_EXT_GPIO
++				gpio_forbidden |= BIT(gpio_num);
++#endif
++			}
++			sif_lock_bus(epub);
++			err =
++			    esp_common_writebyte_with_addr(epub,
++							   SLC_HOST_CONF_W1,
++							   low_byte,
++							   ESP_SIF_NOSYNC);
++			err =
++			    esp_common_writebyte_with_addr(epub,
++							   SLC_HOST_CONF_W1
++							   + 1, high_byte,
++							   ESP_SIF_NOSYNC);
++			err =
++			    esp_common_writebyte_with_addr(epub,
++							   SLC_HOST_CONF_W1
++							   + 2, byte2,
++							   ESP_SIF_NOSYNC);
++			err =
++			    esp_common_writebyte_with_addr(epub,
++							   SLC_HOST_CONF_W1
++							   + 3, byte3,
++							   ESP_SIF_NOSYNC);
++			sif_unlock_bus(epub);
++		} while (0);
++		break;
++	default:
++		EPUB_TO_CTRL(epub)->slc_window_end_addr = 0x20000;
++		break;
++	}
++      _err:
++	return;
++}
++
++u32 sif_get_blksz(struct esp_pub * epub)
++{
++	EPUB_CTRL_CHECK(epub, _err);
++
++	return EPUB_TO_CTRL(epub)->slc_blk_sz;
++      _err:
++	return 512;
++}
++
++u32 sif_get_target_id(struct esp_pub * epub)
++{
++	EPUB_CTRL_CHECK(epub, _err);
++
++	return EPUB_TO_CTRL(epub)->target_id;
++      _err:
++	return 0x600;
++}
++
++void sif_dsr(struct sdio_func *func)
++{
++	struct esp_sdio_ctrl *sctrl = sdio_get_drvdata(func);
++	static int dsr_cnt = 0, real_intr_cnt = 0, bogus_intr_cnt = 0;
++	struct slc_host_regs *regs = &(sctrl->slc_regs);
++	esp_dbg(ESP_DBG_TRACE, " %s enter %d \n", __func__, dsr_cnt++);
++
++	sdio_release_host(sctrl->func);
++
++
++	sif_lock_bus(sctrl->epub);
++
++
++	do {
++		int ret = 0;
++
++		memset(regs, 0x0, sizeof(struct slc_host_regs));
++
++		ret =
++		    esp_common_read_with_addr(sctrl->epub,
++					      REG_SLC_HOST_BASE + 8,
++					      (u8 *) regs,
++					      sizeof(struct slc_host_regs),
++					      ESP_SIF_NOSYNC);
++
++		if ((regs->intr_raw & SLC_HOST_RX_ST) && (ret == 0)) {
++			esp_dbg(ESP_DBG_TRACE, "%s eal intr cnt: %d",
++				__func__, ++real_intr_cnt);
++
++			esp_dsr(sctrl->epub);
++
++		} else {
++			sif_unlock_bus(sctrl->epub);
++
++			esp_dbg(ESP_DBG_TRACE, "%s bogus_intr_cnt %d\n",
++				__func__, ++bogus_intr_cnt);
++		}
++
++#ifdef SIF_DEBUG_DSR_DUMP_REG
++		dump_slc_regs(regs);
++#endif				/* SIF_DEBUG_DUMP_DSR */
++
++	} while (0);
++
++	sdio_claim_host(func);
++
++	atomic_set(&sctrl->irq_handling, 0);
++}
++
++
++struct slc_host_regs *sif_get_regs(struct esp_pub *epub)
++{
++	EPUB_CTRL_CHECK(epub, _err);
++
++	return &EPUB_TO_CTRL(epub)->slc_regs;
++      _err:
++	return NULL;
++}
++
++void sif_disable_target_interrupt(struct esp_pub *epub)
++{
++	EPUB_FUNC_CHECK(epub, _exit);
++	sif_lock_bus(epub);
++#ifdef HOST_RESET_BUG
++	mdelay(10);
++#endif
++	memset(EPUB_TO_CTRL(epub)->dma_buffer, 0x00, sizeof(u32));
++	esp_common_write_with_addr(epub, SLC_HOST_INT_ENA,
++				   EPUB_TO_CTRL(epub)->dma_buffer,
++				   sizeof(u32), ESP_SIF_NOSYNC);
++#ifdef HOST_RESET_BUG
++	mdelay(10);
++#endif
++
++	sif_unlock_bus(epub);
++
++	mdelay(1);
++
++	sif_lock_bus(epub);
++	sif_interrupt_target(epub, 7);
++	sif_unlock_bus(epub);
++      _exit:
++	return;
++}
++
++#ifdef SIF_DEBUG_DSR_DUMP_REG
++static void dump_slc_regs(struct slc_host_regs *regs)
++{
++	esp_dbg(ESP_DBG_TRACE, "\n\n ------- %s --------------\n",
++		__func__);
++
++	esp_dbg(ESP_DBG_TRACE, " \
++                        intr_raw 0x%08X \t \n  \
++                        state_w0 0x%08X \t state_w1 0x%08X \n  \
++                        config_w0 0x%08X \t config_w1 0x%08X \n \
++                        intr_status 0x%08X \t config_w2 0x%08X \n \
++                        config_w3 0x%08X \t config_w4 0x%08X \n \
++                        token_wdata 0x%08X \t intr_clear 0x%08X \n \
++                        intr_enable 0x%08X \n\n", regs->intr_raw, regs->state_w0, regs->state_w1, regs->config_w0, regs->config_w1, regs->intr_status, regs->config_w2, regs->config_w3, regs->config_w4, regs->token_wdata, regs->intr_clear, regs->intr_enable);
++}
++#endif				/* SIF_DEBUG_DSR_DUMP_REG */
++
++static int bt_config = 0;
++void sif_record_bt_config(int value)
++{
++	bt_config = value;
++}
++
++int sif_get_bt_config(void)
++{
++	return bt_config;
++}
++
++static int rst_config = 0;
++void sif_record_rst_config(int value)
++{
++	rst_config = value;
++}
++
++int sif_get_rst_config(void)
++{
++	return rst_config;
++}
++
++static int ate_test = 0;
++void sif_record_ate_config(int value)
++{
++	ate_test = value;
++}
++
++int sif_get_ate_config(void)
++{
++	return ate_test;
++}
++
++static int retry_reset = 0;
++void sif_record_retry_config(void)
++{
++	retry_reset = 1;
++}
++
++int sif_get_retry_config(void)
++{
++	return retry_reset;
++}
++
++static int wakeup_gpio = 12;
++void sif_record_wakeup_gpio_config(int value)
++{
++	wakeup_gpio = value;
++}
++
++int sif_get_wakeup_gpio_config(void)
++{
++	return wakeup_gpio;
++}
+diff --git a/drivers/net/wireless/esp8089/esp_mac80211.c b/drivers/net/wireless/esp8089/esp_mac80211.c
+new file mode 100644
+index 000000000000..14186365fdd4
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_mac80211.c
+@@ -0,0 +1,1728 @@
++/*
++ * Copyright (c) 2011-2014 Espressif System.
++ *
++ *     MAC80211 support module
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/etherdevice.h>
++#include <linux/workqueue.h>
++#include <linux/nl80211.h>
++#include <linux/ieee80211.h>
++#include <linux/slab.h>
++#include <net/cfg80211.h>
++#include <net/mac80211.h>
++#include <linux/version.h>
++#include <net/regulatory.h>
++#include "esp_pub.h"
++#include "esp_sip.h"
++#include "esp_ctrl.h"
++#include "esp_sif.h"
++#include "esp_debug.h"
++#include "esp_wl.h"
++#include "esp_utils.h"
++
++#define ESP_IEEE80211_DBG esp_dbg
++
++#define GET_NEXT_SEQ(seq) (((seq) +1) & 0x0fff)
++
++static u8 esp_mac_addr[ETH_ALEN * 2];
++static u8 getaddr_index(u8 * addr, struct esp_pub *epub);
++
++static
++void
++esp_op_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
++	  struct sk_buff *skb)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_LOG, "%s enter\n", __func__);
++	if (!mod_support_no_txampdu() &&
++	    cfg80211_get_chandef_type(&epub->hw->conf.chandef) !=
++	    NL80211_CHAN_NO_HT) {
++		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++		struct ieee80211_hdr *wh =
++		    (struct ieee80211_hdr *) skb->data;
++		if (ieee80211_is_data_qos(wh->frame_control)) {
++			if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
++				u8 tidno =
++				    ieee80211_get_qos_ctl(wh)[0] &
++				    IEEE80211_QOS_CTL_TID_MASK;
++				struct esp_node *node =
++				    esp_get_node_by_addr(epub, wh->addr1);
++				{
++					struct esp_tx_tid *tid =
++					    &node->tid[tidno];
++					//record ssn
++					spin_lock_bh(&epub->tx_ampdu_lock);
++					tid->ssn =
++					    GET_NEXT_SEQ(le16_to_cpu
++							 (wh->
++							  seq_ctrl) >> 4);
++					ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++							  "tidno:%u,ssn:%u\n",
++							  tidno, tid->ssn);
++					spin_unlock_bh(&epub->
++						       tx_ampdu_lock);
++				}
++			} else {
++				ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++						  "tx ampdu pkt, sn:%u, %u\n",
++						  le16_to_cpu(wh->
++							      seq_ctrl) >>
++						  4, skb->len);
++			}
++		}
++	}
++#ifdef GEN_ERR_CHECKSUM
++	esp_gen_err_checksum(skb);
++#endif
++
++	sip_tx_data_pkt_enqueue(epub, skb);
++	if (epub)
++		ieee80211_queue_work(hw, &epub->tx_work);
++}
++
++static int esp_op_start(struct ieee80211_hw *hw)
++{
++	struct esp_pub *epub;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s\n", __func__);
++
++	if (!hw) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR, "%s no hw!\n", __func__);
++		return -EINVAL;
++	}
++
++	epub = (struct esp_pub *) hw->priv;
++
++	if (!epub) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR, "%s no epub!\n",
++				  __func__);
++		return EINVAL;
++	}
++	/*add rfkill poll function */
++
++	atomic_set(&epub->wl.off, 0);
++	wiphy_rfkill_start_polling(hw->wiphy);
++	return 0;
++}
++
++static void esp_op_stop(struct ieee80211_hw *hw)
++{
++	struct esp_pub *epub;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s\n", __func__);
++
++	if (!hw) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR, "%s no hw!\n", __func__);
++		return;
++	}
++
++	epub = (struct esp_pub *) hw->priv;
++
++	if (!epub) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR, "%s no epub!\n",
++				  __func__);
++		return;
++	}
++
++	atomic_set(&epub->wl.off, 1);
++
++#ifdef HOST_RESET_BUG
++	mdelay(200);
++#endif
++
++	if (epub->wl.scan_req) {
++		hw_scan_done(epub, true);
++		epub->wl.scan_req = NULL;
++		//msleep(2);
++	}
++}
++
++#ifdef CONFIG_PM
++static int esp_op_suspend(struct ieee80211_hw *hw,
++			  struct cfg80211_wowlan *wowlan)
++{
++	esp_dbg(ESP_DBG_OP, "%s\n", __func__);
++
++	return 0;
++}
++
++static int esp_op_resume(struct ieee80211_hw *hw)
++{
++	esp_dbg(ESP_DBG_OP, "%s\n", __func__);
++
++	return 0;
++}
++#endif				//CONFIG_PM
++
++static int esp_op_add_interface(struct ieee80211_hw *hw,
++				struct ieee80211_vif *vif)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	struct sip_cmd_setvif svif;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter: type %d, addr %pM\n",
++			  __func__, vif->type, vif->addr);
++
++	memset(&svif, 0, sizeof(struct sip_cmd_setvif));
++	memcpy(svif.mac, vif->addr, ETH_ALEN);
++	evif->index = svif.index = getaddr_index(vif->addr, epub);
++	evif->epub = epub;
++	epub->vif = vif;
++	svif.set = 1;
++	if ((1 << svif.index) & epub->vif_slot) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "%s interface %d already used\n",
++				  __func__, svif.index);
++		return -EOPNOTSUPP;
++	}
++	epub->vif_slot |= 1 << svif.index;
++
++	if (svif.index == ESP_PUB_MAX_VIF) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "%s only support MAX %d interface\n",
++				  __func__, ESP_PUB_MAX_VIF);
++		return -EOPNOTSUPP;
++	}
++
++	switch (vif->type) {
++	case NL80211_IFTYPE_STATION:
++		//if (svif.index == 1)
++		//      vif->type = NL80211_IFTYPE_UNSPECIFIED;
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s STA \n", __func__);
++		svif.op_mode = 0;
++		svif.is_p2p = 0;
++		break;
++	case NL80211_IFTYPE_AP:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s AP \n", __func__);
++		svif.op_mode = 1;
++		svif.is_p2p = 0;
++		break;
++	case NL80211_IFTYPE_P2P_CLIENT:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s P2P_CLIENT \n", __func__);
++		svif.op_mode = 0;
++		svif.is_p2p = 1;
++		break;
++	case NL80211_IFTYPE_P2P_GO:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s P2P_GO \n", __func__);
++		svif.op_mode = 1;
++		svif.is_p2p = 1;
++		break;
++	case NL80211_IFTYPE_UNSPECIFIED:
++	case NL80211_IFTYPE_ADHOC:
++	case NL80211_IFTYPE_AP_VLAN:
++	case NL80211_IFTYPE_WDS:
++	case NL80211_IFTYPE_MONITOR:
++	default:
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "%s does NOT support type %d\n",
++				  __func__, vif->type);
++		return -EOPNOTSUPP;
++	}
++
++	sip_cmd(epub, SIP_CMD_SETVIF, (u8 *) & svif,
++		sizeof(struct sip_cmd_setvif));
++	return 0;
++}
++
++static int esp_op_change_interface(struct ieee80211_hw *hw,
++				   struct ieee80211_vif *vif,
++				   enum nl80211_iftype new_type, bool p2p)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	struct sip_cmd_setvif svif;
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter,change to if:%d \n",
++			  __func__, new_type);
++
++	if (new_type == NL80211_IFTYPE_AP) {
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter,change to AP \n",
++				  __func__);
++	}
++
++	if (vif->type != new_type) {
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s type from %d to %d\n",
++				  __func__, vif->type, new_type);
++	}
++
++	memset(&svif, 0, sizeof(struct sip_cmd_setvif));
++	memcpy(svif.mac, vif->addr, ETH_ALEN);
++	svif.index = evif->index;
++	svif.set = 2;
++
++	switch (new_type) {
++	case NL80211_IFTYPE_STATION:
++		svif.op_mode = 0;
++		svif.is_p2p = p2p;
++		break;
++	case NL80211_IFTYPE_AP:
++		svif.op_mode = 1;
++		svif.is_p2p = p2p;
++		break;
++	case NL80211_IFTYPE_P2P_CLIENT:
++		svif.op_mode = 0;
++		svif.is_p2p = 1;
++		break;
++	case NL80211_IFTYPE_P2P_GO:
++		svif.op_mode = 1;
++		svif.is_p2p = 1;
++		break;
++	case NL80211_IFTYPE_UNSPECIFIED:
++	case NL80211_IFTYPE_ADHOC:
++	case NL80211_IFTYPE_AP_VLAN:
++	case NL80211_IFTYPE_WDS:
++	case NL80211_IFTYPE_MONITOR:
++	default:
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "%s does NOT support type %d\n",
++				  __func__, vif->type);
++		return -EOPNOTSUPP;
++	}
++	sip_cmd(epub, SIP_CMD_SETVIF, (u8 *) & svif,
++		sizeof(struct sip_cmd_setvif));
++	return 0;
++}
++
++static void esp_op_remove_interface(struct ieee80211_hw *hw,
++				    struct ieee80211_vif *vif)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	struct sip_cmd_setvif svif;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  "%s enter, vif addr %pM, beacon enable %x\n",
++			  __func__, vif->addr,
++			  vif->bss_conf.enable_beacon);
++
++	memset(&svif, 0, sizeof(struct sip_cmd_setvif));
++	svif.index = evif->index;
++	epub->vif_slot &= ~(1 << svif.index);
++
++	if (evif->ap_up) {
++		evif->beacon_interval = 0;
++		del_timer_sync(&evif->beacon_timer);
++		evif->ap_up = false;
++	}
++	epub->vif = NULL;
++	evif->epub = NULL;
++
++	sip_cmd(epub, SIP_CMD_SETVIF, (u8 *) & svif,
++		sizeof(struct sip_cmd_setvif));
++
++	/* clean up tx/rx queue */
++
++}
++
++#define BEACON_TIM_SAVE_MAX 20
++u8 beacon_tim_saved[BEACON_TIM_SAVE_MAX];
++int beacon_tim_count;
++static void beacon_tim_init(void)
++{
++	memset(beacon_tim_saved, 0, BEACON_TIM_SAVE_MAX);
++	beacon_tim_count = 0;
++}
++
++static u8 beacon_tim_save(u8 this_tim)
++{
++	u8 all_tim = 0;
++	int i;
++	beacon_tim_saved[beacon_tim_count] = this_tim;
++	if (++beacon_tim_count >= BEACON_TIM_SAVE_MAX)
++		beacon_tim_count = 0;
++	for (i = 0; i < BEACON_TIM_SAVE_MAX; i++)
++		all_tim |= beacon_tim_saved[i];
++	return all_tim;
++}
++
++static bool beacon_tim_alter(struct sk_buff *beacon)
++{
++	u8 *p, *tim_end;
++	u8 tim_count;
++	int len;
++	int remain_len;
++	struct ieee80211_mgmt *mgmt;
++
++	if (beacon == NULL)
++		return false;
++
++	mgmt = (struct ieee80211_mgmt *) ((u8 *) beacon->data);
++
++	remain_len =
++	    beacon->len - ((u8 *) mgmt->u.beacon.variable - (u8 *) mgmt +
++			   12);
++	p = mgmt->u.beacon.variable;
++
++	while (remain_len > 0) {
++		len = *(++p);
++		if (*p == WLAN_EID_TIM) {	// tim field
++			tim_end = p + len;
++			tim_count = *(++p);
++			p += 2;
++			//multicast
++			if (tim_count == 0)
++				*p |= 0x1;
++			if ((*p & 0xfe) == 0 && tim_end >= p + 1) {	// we only support 8 sta in this case
++				p++;
++				*p = beacon_tim_save(*p);
++			}
++			return tim_count == 0;
++		}
++		p += (len + 1);
++		remain_len -= (2 + len);
++	}
++
++	return false;
++}
++
++unsigned long init_jiffies;
++unsigned long cycle_beacon_count;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++static void drv_handle_beacon(struct timer_list *t)
++#else
++static void drv_handle_beacon(unsigned long data)
++#endif
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	struct esp_vif *evif = from_timer(evif, t, beacon_timer);
++	struct ieee80211_vif *vif = evif->epub->vif;
++#else
++	struct ieee80211_vif *vif = (struct ieee80211_vif *) data;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++#endif
++	struct sk_buff *beacon;
++	struct sk_buff *skb;
++	static int dbgcnt = 0;
++	bool tim_reach = false;
++
++	if (evif->epub == NULL)
++		return;
++
++	mdelay(2400 * (cycle_beacon_count % 25) % 10000 / 1000);
++
++	beacon = ieee80211_beacon_get(evif->epub->hw, vif, 0);
++
++	tim_reach = beacon_tim_alter(beacon);
++
++	if (beacon && !(dbgcnt++ % 600)) {
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, " beacon length:%d,fc:0x%x\n",
++				  beacon->len,
++				  ((struct ieee80211_mgmt *) (beacon->
++							      data))->
++				  frame_control);
++
++	}
++
++	if (beacon)
++		sip_tx_data_pkt_enqueue(evif->epub, beacon);
++
++	if (cycle_beacon_count++ == 100) {
++		init_jiffies = jiffies;
++		cycle_beacon_count -= 100;
++	}
++	mod_timer(&evif->beacon_timer,
++		  init_jiffies +
++		  msecs_to_jiffies(cycle_beacon_count *
++				   vif->bss_conf.beacon_int * 1024 /
++				   1000));
++	//FIXME:the packets must be sent at home channel
++	//send buffer mcast frames
++	if (tim_reach) {
++		skb = ieee80211_get_buffered_bc(evif->epub->hw, vif);
++		while (skb) {
++			sip_tx_data_pkt_enqueue(evif->epub, skb);
++			skb =
++			    ieee80211_get_buffered_bc(evif->epub->hw, vif);
++		}
++	}
++}
++
++static void init_beacon_timer(struct ieee80211_vif *vif)
++{
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, " %s enter: beacon interval %x\n",
++			  __func__, evif->beacon_interval);
++
++	beacon_tim_init();
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	timer_setup(&evif->beacon_timer, drv_handle_beacon, 0);
++#else
++	init_timer(&evif->beacon_timer);	//TBD, not init here...
++	evif->beacon_timer.data = (unsigned long) vif;
++	evif->beacon_timer.function = drv_handle_beacon;
++#endif
++	cycle_beacon_count = 1;
++	init_jiffies = jiffies;
++	evif->beacon_timer.expires =
++	    init_jiffies +
++	    msecs_to_jiffies(cycle_beacon_count *
++			     vif->bss_conf.beacon_int * 1024 / 1000);
++	add_timer(&evif->beacon_timer);
++}
++
++static int esp_op_config(struct ieee80211_hw *hw, u32 changed)
++{
++	//struct ieee80211_conf *conf = &hw->conf;
++
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter 0x%08x\n", __func__,
++			  changed);
++
++	if (changed &
++	    (IEEE80211_CONF_CHANGE_CHANNEL | IEEE80211_CONF_CHANGE_IDLE)) {
++		sip_send_config(epub, &hw->conf);
++	}
++
++	return 0;
++}
++
++static void esp_op_bss_info_changed(struct ieee80211_hw *hw,
++				    struct ieee80211_vif *vif,
++				    struct ieee80211_bss_conf *info,
++				    u64 changed)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++
++	// ieee80211_bss_conf(include/net/mac80211.h) is included in ieee80211_sub_if_data(net/mac80211/ieee80211_i.h) , does bssid=ieee80211_if_ap's ssid ?
++	// in 2.6.27, ieee80211_sub_if_data has ieee80211_bss_conf while in 2.6.32 ieee80211_sub_if_data don't have ieee80211_bss_conf
++	// in 2.6.27, ieee80211_bss_conf->enable_beacon don't exist, does it mean it support beacon always?
++	// ESP_IEEE80211_DBG(ESP_DBG_OP, " %s enter: vif addr %pM, changed %x, assoc %x, bssid %pM\n", __func__, vif->addr, changed, vif->cfg.assoc, info->bssid);
++	// sdata->u.sta.bssid
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  " %s enter: changed %llx, assoc %x, bssid %pM\n",
++			  __func__, changed, vif->cfg.assoc, info->bssid);
++
++	if (vif->type == NL80211_IFTYPE_STATION) {
++		if ((changed & BSS_CHANGED_BSSID) ||
++		    ((changed & BSS_CHANGED_ASSOC) && (vif->cfg.assoc))) {
++			ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++					  " %s STA change bssid or assoc\n",
++					  __func__);
++			evif->beacon_interval = vif->cfg.aid;
++			memcpy(epub->wl.bssid, (u8 *) info->bssid,
++			       ETH_ALEN);
++			sip_send_bss_info_update(epub, evif,
++						 (u8 *) info->bssid,
++						 vif->cfg.assoc);
++		} else if ((changed & BSS_CHANGED_ASSOC) && (!vif->cfg.assoc)) {
++			ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++					  " %s STA change disassoc\n",
++					  __func__);
++			evif->beacon_interval = 0;
++			memset(epub->wl.bssid, 0, ETH_ALEN);
++			sip_send_bss_info_update(epub, evif,
++						 (u8 *) info->bssid,
++						 vif->cfg.assoc);
++		} else {
++			ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++					  "%s wrong mode of STA mode\n",
++					  __func__);
++		}
++	} else if (vif->type == NL80211_IFTYPE_AP) {
++		if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
++		    (changed & BSS_CHANGED_BEACON_INT)) {
++			ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++					  " %s AP change enable %d, interval is %d, bssid %pM\n",
++					  __func__, info->enable_beacon,
++					  info->beacon_int, info->bssid);
++			if (info->enable_beacon && evif->ap_up != true) {
++				evif->beacon_interval = info->beacon_int;
++				init_beacon_timer(vif);
++				sip_send_bss_info_update(epub, evif,
++							 (u8 *) info->
++							 bssid, 2);
++				evif->ap_up = true;
++			} else if (!info->enable_beacon && evif->ap_up &&
++				!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
++			    ) {
++				ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++						  " %s AP disable beacon, interval is %d\n",
++						  __func__,
++						  info->beacon_int);
++				evif->beacon_interval = 0;
++				del_timer_sync(&evif->beacon_timer);
++				sip_send_bss_info_update(epub, evif,
++							 (u8 *) info->
++							 bssid, 2);
++				evif->ap_up = false;
++			}
++		}
++	} else {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "%s op mode unspecified\n", __func__);
++	}
++}
++
++
++static u64 esp_op_prepare_multicast(struct ieee80211_hw *hw,
++				    struct netdev_hw_addr_list *mc_list)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	return 0;
++}
++
++static void esp_op_configure_filter(struct ieee80211_hw *hw,
++				    unsigned int changed_flags,
++				    unsigned int *total_flags,
++				    u64 multicast)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	epub->rx_filter = 0;
++
++	if (*total_flags & FIF_ALLMULTI)
++		epub->rx_filter |= FIF_ALLMULTI;
++
++	*total_flags = epub->rx_filter;
++}
++
++static int esp_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
++			  struct ieee80211_vif *vif,
++			  struct ieee80211_sta *sta,
++			  struct ieee80211_key_conf *key)
++{
++	u8 i;
++	int ret;
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	u8 ifidx = evif->index;
++	u8 *peer_addr, isvalid;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  "%s enter, flags = %x keyindx = %x cmd = %x mac = %pM cipher = %x\n",
++			  __func__, key->flags, key->keyidx, cmd,
++			  vif->addr, key->cipher);
++
++	key->flags = key->flags | IEEE80211_KEY_FLAG_GENERATE_IV;
++
++	if (sta) {
++		if (memcmp(sta->addr, epub->wl.bssid, ETH_ALEN))
++			peer_addr = sta->addr;
++		else
++			peer_addr = epub->wl.bssid;
++	} else {
++		peer_addr = epub->wl.bssid;
++	}
++	isvalid = (cmd == SET_KEY) ? 1 : 0;
++
++	if ((key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
++	    || (key->cipher == WLAN_CIPHER_SUITE_WEP40
++		|| key->cipher == WLAN_CIPHER_SUITE_WEP104)) {
++		if (isvalid) {
++			for (i = 0; i < 19; i++) {
++				if (epub->hi_map[i].flag == 0) {
++					epub->hi_map[i].flag = 1;
++					key->hw_key_idx = i + 6;
++					memcpy(epub->hi_map[i].mac,
++					       peer_addr, ETH_ALEN);
++					break;
++				}
++			}
++		} else {
++			u8 index = key->hw_key_idx - 6;
++			epub->hi_map[index].flag = 0;
++			memset(epub->hi_map[index].mac, 0, ETH_ALEN);
++		}
++	} else {
++		if (isvalid) {
++			for (i = 0; i < 2; i++)
++				if (epub->low_map[ifidx][i].flag == 0) {
++					epub->low_map[ifidx][i].flag = 1;
++					key->hw_key_idx =
++					    i + ifidx * 2 + 2;
++					memcpy(epub->low_map[ifidx][i].mac,
++					       peer_addr, ETH_ALEN);
++					break;
++				}
++		} else {
++			u8 index = key->hw_key_idx - 2 - ifidx * 2;
++			epub->low_map[ifidx][index].flag = 0;
++			memset(epub->low_map[ifidx][index].mac, 0,
++			       ETH_ALEN);
++		}
++		//key->hw_key_idx = key->keyidx + ifidx * 2 + 1;
++	}
++
++	if (key->hw_key_idx >= 6) {
++		/*send sub_scan task to target */
++		//epub->wl.ptk = (cmd==SET_KEY) ? key : NULL;
++		if (isvalid)
++			atomic_inc(&epub->wl.ptk_cnt);
++		else
++			atomic_dec(&epub->wl.ptk_cnt);
++		if (key->cipher == WLAN_CIPHER_SUITE_WEP40
++		    || key->cipher == WLAN_CIPHER_SUITE_WEP104) {
++			if (isvalid)
++				atomic_inc(&epub->wl.gtk_cnt);
++			else
++				atomic_dec(&epub->wl.gtk_cnt);
++		}
++	} else {
++		/*send sub_scan task to target */
++		if (isvalid)
++			atomic_inc(&epub->wl.gtk_cnt);
++		else
++			atomic_dec(&epub->wl.gtk_cnt);
++
++		if ((key->cipher == WLAN_CIPHER_SUITE_WEP40
++		     || key->cipher == WLAN_CIPHER_SUITE_WEP104)) {
++			if (isvalid)
++				atomic_inc(&epub->wl.ptk_cnt);
++			else
++				atomic_dec(&epub->wl.ptk_cnt);
++			//epub->wl.ptk = (cmd==SET_KEY) ? key : NULL;
++		}
++	}
++
++	ret = sip_send_setkey(epub, ifidx, peer_addr, key, isvalid);
++
++	if ((key->cipher == WLAN_CIPHER_SUITE_TKIP
++	     || key->cipher == WLAN_CIPHER_SUITE_TKIP)) {
++		if (ret == 0)
++			atomic_set(&epub->wl.tkip_key_set, 1);
++	}
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s exit\n", __func__);
++	return ret;
++}
++
++static void esp_op_update_tkip_key(struct ieee80211_hw *hw,
++				   struct ieee80211_vif *vif,
++				   struct ieee80211_key_conf *conf,
++				   struct ieee80211_sta *sta,
++				   u32 iv32, u16 * phase1key)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++}
++
++void hw_scan_done(struct esp_pub *epub, bool aborted)
++{
++	cancel_delayed_work_sync(&epub->scan_timeout_work);
++
++	ESSERT(epub->wl.scan_req != NULL);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++	{
++		struct cfg80211_scan_info info = {
++			.aborted = aborted,
++		};
++
++		ieee80211_scan_completed(epub->hw, &info);
++	}
++#else
++	ieee80211_scan_completed(epub->hw, aborted);
++#endif
++	if (test_and_clear_bit(ESP_WL_FLAG_STOP_TXQ, &epub->wl.flags)) {
++		sip_trigger_txq_process(epub->sip);
++	}
++}
++
++static void hw_scan_timeout_report(struct work_struct *work)
++{
++	struct esp_pub *epub =
++	    container_of(work, struct esp_pub, scan_timeout_work.work);
++	bool aborted;
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "eagle hw scan done\n");
++
++	if (test_and_clear_bit(ESP_WL_FLAG_STOP_TXQ, &epub->wl.flags)) {
++		sip_trigger_txq_process(epub->sip);
++	}
++	/*check if normally complete or aborted like timeout/hw error */
++	aborted = (epub->wl.scan_req) ? true : false;
++
++	if (aborted == true) {
++		epub->wl.scan_req = NULL;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++	{
++		struct cfg80211_scan_info info = {
++			.aborted = aborted,
++		};
++
++		ieee80211_scan_completed(epub->hw, &info);
++	}
++#else
++	ieee80211_scan_completed(epub->hw, aborted);
++#endif
++}
++
++static int esp_op_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	return 0;
++}
++
++static int esp_node_attach(struct ieee80211_hw *hw, u8 ifidx,
++			   struct ieee80211_sta *sta)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_node *node;
++	u8 tidno;
++	struct esp_tx_tid *tid;
++	int i;
++
++	spin_lock_bh(&epub->tx_ampdu_lock);
++
++	if (hweight32(epub->enodes_maps[ifidx]) < ESP_PUB_MAX_STA
++	    && (i = ffz(epub->enodes_map)) < ESP_PUB_MAX_STA + 1) {
++		epub->enodes_map |= (1 << i);
++		epub->enodes_maps[ifidx] |= (1 << i);
++		node = (struct esp_node *) sta->drv_priv;
++		epub->enodes[i] = node;
++		node->sta = sta;
++		node->ifidx = ifidx;
++		node->index = i;
++
++		for (tidno = 0, tid = &node->tid[tidno];
++		     tidno < WME_NUM_TID; tidno++) {
++			tid->ssn = 0;
++			tid->cnt = 0;
++			tid->state = ESP_TID_STATE_INIT;
++		}
++
++
++	} else {
++		i = -1;
++	}
++
++	spin_unlock_bh(&epub->tx_ampdu_lock);
++	return i;
++}
++
++static int esp_node_detach(struct ieee80211_hw *hw, u8 ifidx,
++			   struct ieee80211_sta *sta)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	u32 map;
++	int i;
++	struct esp_node *node = NULL;
++
++	spin_lock_bh(&epub->tx_ampdu_lock);
++	map = epub->enodes_maps[ifidx];
++	while (map != 0) {
++		i = ffs(map) - 1;
++		if (epub->enodes[i]->sta == sta) {
++			epub->enodes[i]->sta = NULL;
++			node = epub->enodes[i];
++			epub->enodes[i] = NULL;
++			epub->enodes_map &= ~(1 << i);
++			epub->enodes_maps[ifidx] &= ~(1 << i);
++
++			spin_unlock_bh(&epub->tx_ampdu_lock);
++			return i;
++		}
++		map &= ~(1 << i);
++	}
++
++	spin_unlock_bh(&epub->tx_ampdu_lock);
++	return -1;
++}
++
++struct esp_node *esp_get_node_by_addr(struct esp_pub *epub,
++				      const u8 * addr)
++{
++	int i;
++	u32 map;
++	struct esp_node *node = NULL;
++	if (addr == NULL)
++		return NULL;
++	spin_lock_bh(&epub->tx_ampdu_lock);
++	map = epub->enodes_map;
++	while (map != 0) {
++		i = ffs(map) - 1;
++		if (i < 0) {
++			spin_unlock_bh(&epub->tx_ampdu_lock);
++			return NULL;
++		}
++		map &= ~(1 << i);
++		if (memcmp(epub->enodes[i]->sta->addr, addr, ETH_ALEN) ==
++		    0) {
++			node = epub->enodes[i];
++			break;
++		}
++	}
++
++	spin_unlock_bh(&epub->tx_ampdu_lock);
++	return node;
++}
++
++struct esp_node *esp_get_node_by_index(struct esp_pub *epub, u8 index)
++{
++	u32 map;
++	struct esp_node *node = NULL;
++
++	if (epub == NULL)
++		return NULL;
++
++	spin_lock_bh(&epub->tx_ampdu_lock);
++	map = epub->enodes_map;
++	if (map & BIT(index)) {
++		node = epub->enodes[index];
++	} else {
++		spin_unlock_bh(&epub->tx_ampdu_lock);
++		return NULL;
++	}
++
++	spin_unlock_bh(&epub->tx_ampdu_lock);
++	return node;
++}
++
++int esp_get_empty_rxampdu(struct esp_pub *epub, const u8 * addr, u8 tid)
++{
++	int index = -1;
++	if (addr == NULL)
++		return index;
++	spin_lock_bh(&epub->rx_ampdu_lock);
++	if ((index = ffz(epub->rxampdu_map)) < ESP_PUB_MAX_RXAMPDU) {
++		epub->rxampdu_map |= BIT(index);
++		epub->rxampdu_node[index] =
++		    esp_get_node_by_addr(epub, addr);
++		epub->rxampdu_tid[index] = tid;
++	} else {
++		index = -1;
++	}
++	spin_unlock_bh(&epub->rx_ampdu_lock);
++	return index;
++}
++
++int esp_get_exist_rxampdu(struct esp_pub *epub, const u8 * addr, u8 tid)
++{
++	u8 map;
++	int index = -1;
++	int i;
++	if (addr == NULL)
++		return index;
++	spin_lock_bh(&epub->rx_ampdu_lock);
++	map = epub->rxampdu_map;
++	while (map != 0) {
++		i = ffs(map) - 1;
++		if (i < 0) {
++			spin_unlock_bh(&epub->rx_ampdu_lock);
++			return index;
++		}
++		map &= ~BIT(i);
++		if (epub->rxampdu_tid[i] == tid &&
++		    memcmp(epub->rxampdu_node[i]->sta->addr, addr,
++			   ETH_ALEN) == 0) {
++			index = i;
++			break;
++		}
++	}
++
++	epub->rxampdu_map &= ~BIT(index);
++	spin_unlock_bh(&epub->rx_ampdu_lock);
++	return index;
++
++}
++
++static int esp_op_sta_add(struct ieee80211_hw *hw,
++			  struct ieee80211_vif *vif,
++			  struct ieee80211_sta *sta)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	int index;
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  "%s enter, vif addr %pM, sta addr %pM\n",
++			  __func__, vif->addr, sta->addr);
++	index = esp_node_attach(hw, evif->index, sta);
++
++	if (index < 0)
++		return -1;
++	sip_send_set_sta(epub, evif->index, 1, sta, vif, (u8) index);
++	return 0;
++}
++
++static int esp_op_sta_remove(struct ieee80211_hw *hw,
++			     struct ieee80211_vif *vif,
++			     struct ieee80211_sta *sta)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	int index;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  "%s enter, vif addr %pM, sta addr %pM\n",
++			  __func__, vif->addr, sta->addr);
++
++	//remove a connect in target
++	index = esp_node_detach(hw, evif->index, sta);
++	sip_send_set_sta(epub, evif->index, 0, sta, vif, (u8) index);
++
++	return 0;
++}
++
++
++static void esp_op_sta_notify(struct ieee80211_hw *hw,
++			      struct ieee80211_vif *vif,
++			      enum sta_notify_cmd cmd,
++			      struct ieee80211_sta *sta)
++{
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	switch (cmd) {
++	case STA_NOTIFY_SLEEP:
++		break;
++
++	case STA_NOTIFY_AWAKE:
++		break;
++
++	default:
++		break;
++	}
++}
++
++
++static int esp_op_conf_tx(struct ieee80211_hw *hw,
++			  struct ieee80211_vif *vif,
++			  u32 link_id, u16 queue,
++			  const struct ieee80211_tx_queue_params *params)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++	return sip_send_wmm_params(epub, queue, params);
++}
++
++static u64 esp_op_get_tsf(struct ieee80211_hw *hw,
++			  struct ieee80211_vif *vif)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	return 0;
++}
++
++static void esp_op_set_tsf(struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, u64 tsf)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++}
++
++static void esp_op_reset_tsf(struct ieee80211_hw *hw,
++			     struct ieee80211_vif *vif)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++}
++
++static void esp_op_rfkill_poll(struct ieee80211_hw *hw)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	wiphy_rfkill_set_hw_state(hw->wiphy,
++				  test_bit(ESP_WL_FLAG_RFKILL,
++					   &epub->wl.
++					   flags) ? true : false);
++}
++
++#ifdef HW_SCAN
++static int esp_op_hw_scan(struct ieee80211_hw *hw,
++			  struct ieee80211_vif *vif,
++			  struct cfg80211_scan_request *req)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	int i, ret;
++	bool scan_often = true;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s\n", __func__);
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "scan, %d\n", req->n_ssids);
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "scan, len 1:%d,ssid 1:%s\n",
++			  req->ssids->ssid_len,
++			  req->ssids->ssid_len ==
++			  0 ? "" : (char *) req->ssids->ssid);
++	if (req->n_ssids > 1)
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++				  "scan, len 2:%d,ssid 2:%s\n",
++				  (req->ssids + 1)->ssid_len,
++				  (req->ssids + 1)->ssid_len ==
++				  0 ? "" : (char *) (req->ssids +
++						     1)->ssid);
++
++	/*scan_request is keep allocate untill scan_done,record it
++	   to split request into multi sdio_cmd */
++	if (atomic_read(&epub->wl.off)) {
++		esp_dbg(ESP_DBG_ERROR, "%s scan but wl off \n", __func__);
++		return -EPERM;
++	}
++
++	if (req->n_ssids > 1) {
++		struct cfg80211_ssid *ssid2 = req->ssids + 1;
++		if ((req->ssids->ssid_len > 0 && ssid2->ssid_len > 0)
++		    || req->n_ssids > 2) {
++			ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++					  "scan ssid num: %d, ssid1:%s, ssid2:%s,not support\n",
++					  req->n_ssids,
++					  req->ssids->ssid_len ==
++					  0 ? "" : (char *) req->ssids->
++					  ssid,
++					  ssid2->ssid_len ==
++					  0 ? "" : (char *) ssid2->ssid);
++			return -EINVAL;
++		}
++	}
++
++	epub->wl.scan_req = req;
++
++	for (i = 0; i < req->n_channels; i++)
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "eagle hw_scan freq %d\n",
++				  req->channels[i]->center_freq);
++#if 0
++	for (i = 0; i < req->n_ssids; i++) {
++		if (req->ssids->ssid_len > 0) {
++			req->ssids->ssid[req->ssids->ssid_len] = '\0';
++			ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++					  "scan_ssid %d:%s\n", i,
++					  req->ssids->ssid);
++		}
++	}
++#endif
++
++	/*in connect state, suspend tx data */
++	if (epub->sip->support_bgscan &&
++	    test_bit(ESP_WL_FLAG_CONNECT, &epub->wl.flags) &&
++	    req->n_channels > 0) {
++
++		scan_often = epub->scan_permit_valid
++		    && time_before(jiffies, epub->scan_permit);
++		epub->scan_permit_valid = true;
++
++		if (!scan_often) {
++/*                        epub->scan_permit = jiffies + msecs_to_jiffies(900);
++                        set_bit(ESP_WL_FLAG_STOP_TXQ, &epub->wl.flags);
++                        if (atomic_read(&epub->txq_stopped) == false) {
++                                atomic_set(&epub->txq_stopped, true);
++                                ieee80211_stop_queues(hw);
++                        }
++*/
++		} else {
++			ESP_IEEE80211_DBG(ESP_DBG_LOG, "scan too often\n");
++			return -EACCES;
++		}
++	} else {
++		scan_often = false;
++	}
++
++	/*send sub_scan task to target */
++	ret = sip_send_scan(epub);
++
++	if (ret) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "fail to send scan_cmd\n");
++		return ret;
++	} else {
++		if (!scan_often) {
++			epub->scan_permit =
++			    jiffies + msecs_to_jiffies(900);
++			set_bit(ESP_WL_FLAG_STOP_TXQ, &epub->wl.flags);
++			if (atomic_read(&epub->txq_stopped) == false) {
++				atomic_set(&epub->txq_stopped, true);
++				ieee80211_stop_queues(hw);
++			}
++			/*force scan complete in case target fail to report in time */
++			ieee80211_queue_delayed_work(hw,
++						     &epub->
++						     scan_timeout_work,
++						     req->n_channels * HZ /
++						     4);
++		}
++	}
++
++	return 0;
++}
++
++static int esp_op_remain_on_channel(struct ieee80211_hw *hw,
++				    struct ieee80211_channel *chan,
++				    enum nl80211_channel_type channel_type,
++				    int duration)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  "%s enter, center_freq = %d duration = %d\n",
++			  __func__, chan->center_freq, duration);
++	sip_send_roc(epub, chan->center_freq, duration);
++	return 0;
++}
++
++static int esp_op_cancel_remain_on_channel(struct ieee80211_hw *hw)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter \n", __func__);
++	epub->roc_flags = 0;	// to disable roc state
++	sip_send_roc(epub, 0, 0);
++	return 0;
++}
++#endif
++
++void esp_rocdone_process(struct ieee80211_hw *hw,
++			 struct sip_evt_roc *report)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter, state = %d is_ok = %d\n",
++			  __func__, report->state, report->is_ok);
++
++	//roc process begin 
++	if ((report->state == 1) && (report->is_ok == 1)) {
++		epub->roc_flags = 1;	//flags in roc state, to fix channel, not change
++		ieee80211_ready_on_channel(hw);
++	} else if ((report->state == 0) && (report->is_ok == 1))	//roc process timeout
++	{
++		epub->roc_flags = 0;	// to disable roc state
++		ieee80211_remain_on_channel_expired(hw);
++	}
++}
++
++static int esp_op_set_bitrate_mask(struct ieee80211_hw *hw,
++				   struct ieee80211_vif *vif,
++				   const struct cfg80211_bitrate_mask
++				   *mask)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter \n", __func__);
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s vif->macaddr[%pM], mask[%d]\n",
++			  __func__, vif->addr, mask->control[0].legacy);
++
++	return 0;
++}
++
++static void esp_op_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
++		  u32 queues, bool drop)
++{
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter \n", __func__);
++	do {
++
++		struct esp_pub *epub = (struct esp_pub *) hw->priv;
++		unsigned long time = jiffies + msecs_to_jiffies(15);
++		while (atomic_read(&epub->sip->tx_data_pkt_queued)) {
++			if (!time_before(jiffies, time)) {
++				break;
++			}
++			if (sif_get_ate_config() == 0) {
++				ieee80211_queue_work(epub->hw,
++						     &epub->tx_work);
++			} else {
++				queue_work(epub->esp_wkq, &epub->tx_work);
++			}
++			//sip_txq_process(epub);
++		}
++		mdelay(10);
++
++	} while (0);
++}
++
++static int esp_op_ampdu_action(struct ieee80211_hw *hw,
++			       struct ieee80211_vif *vif,
++			       struct ieee80211_ampdu_params *params)
++{
++	int ret = -EOPNOTSUPP;
++	enum ieee80211_ampdu_mlme_action action = params->action;
++	struct ieee80211_sta *sta = params->sta;
++	u16 tid = params->tid;
++	u16 *ssn = &params->ssn;
++	u8 buf_size = params->buf_size;
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_node *node = (struct esp_node *) sta->drv_priv;
++	struct esp_tx_tid *tid_info = &node->tid[tid];
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter \n", __func__);
++	switch (action) {
++	case IEEE80211_AMPDU_TX_START:
++		if (mod_support_no_txampdu() ||
++		    cfg80211_get_chandef_type(&epub->hw->conf.chandef) ==
++		    NL80211_CHAN_NO_HT || !sta->deflink.ht_cap.ht_supported)
++			return ret;
++
++		//if (vif->p2p || vif->type != NL80211_IFTYPE_STATION)
++		//      return ret;
++
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++				  "%s TX START, addr:%pM,tid:%u,state:%d\n",
++				  __func__, sta->addr, tid,
++				  tid_info->state);
++		spin_lock_bh(&epub->tx_ampdu_lock);
++		ESSERT(tid_info->state == ESP_TID_STATE_TRIGGER);
++		*ssn = tid_info->ssn;
++		tid_info->state = ESP_TID_STATE_PROGRESS;
++
++		ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
++		spin_unlock_bh(&epub->tx_ampdu_lock);
++		ret = 0;
++		break;
++	case IEEE80211_AMPDU_TX_STOP_CONT:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++				  "%s TX STOP, addr:%pM,tid:%u,state:%d\n",
++				  __func__, sta->addr, tid,
++				  tid_info->state);
++		spin_lock_bh(&epub->tx_ampdu_lock);
++		if (tid_info->state == ESP_TID_STATE_WAIT_STOP)
++			tid_info->state = ESP_TID_STATE_STOP;
++		else
++			tid_info->state = ESP_TID_STATE_INIT;
++		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
++		spin_unlock_bh(&epub->tx_ampdu_lock);
++		ret =
++		    sip_send_ampdu_action(epub, SIP_AMPDU_TX_STOP,
++					  sta->addr, tid, node->ifidx, 0);
++		break;
++	case IEEE80211_AMPDU_TX_STOP_FLUSH:
++	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
++		if (tid_info->state == ESP_TID_STATE_WAIT_STOP)
++			tid_info->state = ESP_TID_STATE_STOP;
++		else
++			tid_info->state = ESP_TID_STATE_INIT;
++		ret =
++		    sip_send_ampdu_action(epub, SIP_AMPDU_TX_STOP,
++					  sta->addr, tid, node->ifidx, 0);
++		break;
++	case IEEE80211_AMPDU_TX_OPERATIONAL:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++				  "%s TX OPERATION, addr:%pM,tid:%u,state:%d\n",
++				  __func__, sta->addr, tid,
++				  tid_info->state);
++		spin_lock_bh(&epub->tx_ampdu_lock);
++
++		if (tid_info->state != ESP_TID_STATE_PROGRESS) {
++			if (tid_info->state == ESP_TID_STATE_INIT) {
++				printk(KERN_ERR "%s WIFI RESET, IGNORE\n",
++				       __func__);
++				spin_unlock_bh(&epub->tx_ampdu_lock);
++				return -ENETRESET;
++			} else {
++				ESSERT(0);
++			}
++		}
++
++		tid_info->state = ESP_TID_STATE_OPERATIONAL;
++		spin_unlock_bh(&epub->tx_ampdu_lock);
++		ret =
++		    sip_send_ampdu_action(epub, SIP_AMPDU_TX_OPERATIONAL,
++					  sta->addr, tid, node->ifidx,
++					  buf_size);
++		break;
++	case IEEE80211_AMPDU_RX_START:
++		if (mod_support_no_rxampdu() ||
++		    cfg80211_get_chandef_type(&epub->hw->conf.chandef) ==
++		    NL80211_CHAN_NO_HT || !sta->deflink.ht_cap.ht_supported)
++			return ret;
++
++		if ((vif->p2p && false)
++		    || (vif->type != NL80211_IFTYPE_STATION && false)
++		    )
++			return ret;
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++				  "%s RX START %pM tid %u %u\n", __func__,
++				  sta->addr, tid, *ssn);
++		ret =
++		    sip_send_ampdu_action(epub, SIP_AMPDU_RX_START,
++					  sta->addr, tid, *ssn, 64);
++		break;
++	case IEEE80211_AMPDU_RX_STOP:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s RX STOP %pM tid %u\n",
++				  __func__, sta->addr, tid);
++		ret =
++		    sip_send_ampdu_action(epub, SIP_AMPDU_RX_STOP,
++					  sta->addr, tid, 0, 0);
++		break;
++	default:
++		break;
++	}
++	return ret;
++}
++
++static void esp_tx_work(struct work_struct *work)
++{
++	struct esp_pub *epub = container_of(work, struct esp_pub, tx_work);
++
++	mutex_lock(&epub->tx_mtx);
++	sip_txq_process(epub);
++	mutex_unlock(&epub->tx_mtx);
++}
++
++static const struct ieee80211_ops esp_mac80211_ops = {
++	.tx = esp_op_tx,
++	.start = esp_op_start,
++	.stop = esp_op_stop,
++#ifdef CONFIG_PM
++	.suspend = esp_op_suspend,
++	.resume = esp_op_resume,
++#endif
++	.add_interface = esp_op_add_interface,
++	.remove_interface = esp_op_remove_interface,
++	.config = esp_op_config,
++
++	.bss_info_changed = esp_op_bss_info_changed,
++	.prepare_multicast = esp_op_prepare_multicast,
++	.configure_filter = esp_op_configure_filter,
++	.set_key = esp_op_set_key,
++	.update_tkip_key = esp_op_update_tkip_key,
++	//.sched_scan_start = esp_op_sched_scan_start,
++	//.sched_scan_stop = esp_op_sched_scan_stop,
++	.set_rts_threshold = esp_op_set_rts_threshold,
++	.sta_notify = esp_op_sta_notify,
++	.conf_tx = esp_op_conf_tx,
++	.change_interface = esp_op_change_interface,
++	.get_tsf = esp_op_get_tsf,
++	.set_tsf = esp_op_set_tsf,
++	.reset_tsf = esp_op_reset_tsf,
++	.rfkill_poll = esp_op_rfkill_poll,
++#ifdef HW_SCAN
++	.hw_scan = esp_op_hw_scan,
++	.remain_on_channel = esp_op_remain_on_channel,
++	.cancel_remain_on_channel = esp_op_cancel_remain_on_channel,
++#endif
++	.ampdu_action = esp_op_ampdu_action,
++	//.get_survey = esp_op_get_survey,
++	.sta_add = esp_op_sta_add,
++	.sta_remove = esp_op_sta_remove,
++#ifdef CONFIG_NL80211_TESTMODE
++	//CFG80211_TESTMODE_CMD(esp_op_tm_cmd)
++#endif
++	.set_bitrate_mask = esp_op_set_bitrate_mask,
++	.flush = esp_op_flush,
++	.wake_tx_queue = ieee80211_handle_wake_tx_queue,
++};
++
++struct esp_pub *esp_pub_alloc_mac80211(struct device *dev)
++{
++	struct ieee80211_hw *hw;
++	struct esp_pub *epub;
++	int ret = 0;
++
++	hw = ieee80211_alloc_hw(sizeof(struct esp_pub), &esp_mac80211_ops);
++
++	if (hw == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "ieee80211 can't alloc hw!\n");
++		ret = -ENOMEM;
++		return ERR_PTR(ret);
++	}
++	hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
++
++	epub = hw->priv;
++	memset(epub, 0, sizeof(*epub));
++	epub->hw = hw;
++	SET_IEEE80211_DEV(hw, dev);
++	epub->dev = dev;
++
++	skb_queue_head_init(&epub->txq);
++	skb_queue_head_init(&epub->txdoneq);
++	skb_queue_head_init(&epub->rxq);
++
++	spin_lock_init(&epub->tx_ampdu_lock);
++	spin_lock_init(&epub->rx_ampdu_lock);
++	spin_lock_init(&epub->tx_lock);
++	mutex_init(&epub->tx_mtx);
++	spin_lock_init(&epub->rx_lock);
++
++	INIT_WORK(&epub->tx_work, esp_tx_work);
++
++	//epub->esp_wkq = create_freezable_workqueue("esp_wkq"); 
++	epub->esp_wkq = create_singlethread_workqueue("esp_wkq");
++
++	if (epub->esp_wkq == NULL) {
++		ret = -ENOMEM;
++		return ERR_PTR(ret);
++	}
++	epub->scan_permit_valid = false;
++	INIT_DELAYED_WORK(&epub->scan_timeout_work,
++			  hw_scan_timeout_report);
++
++	return epub;
++}
++
++
++int esp_pub_dealloc_mac80211(struct esp_pub *epub)
++{
++	set_bit(ESP_WL_FLAG_RFKILL, &epub->wl.flags);
++
++	destroy_workqueue(epub->esp_wkq);
++	mutex_destroy(&epub->tx_mtx);
++
++#ifdef ESP_NO_MAC80211
++	free_netdev(epub->net_dev);
++	wiphy_free(epub->wdev->wiphy);
++	kfree(epub->wdev);
++#else
++	if (epub->hw) {
++		ieee80211_free_hw(epub->hw);
++	}
++#endif
++
++	return 0;
++}
++
++#if 0
++static int esp_reg_notifier(struct wiphy *wiphy,
++			    struct regulatory_request *request)
++{
++	struct ieee80211_supported_band *sband;
++	struct ieee80211_channel *ch;
++	int i;
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter %d\n", __func__,
++			  request->initiator);
++
++	//TBD
++}
++#endif
++
++/* 2G band channels */
++static struct ieee80211_channel esp_channels_2ghz[] = {
++	{.hw_value = 1,.center_freq = 2412,.max_power = 25},
++	{.hw_value = 2,.center_freq = 2417,.max_power = 25},
++	{.hw_value = 3,.center_freq = 2422,.max_power = 25},
++	{.hw_value = 4,.center_freq = 2427,.max_power = 25},
++	{.hw_value = 5,.center_freq = 2432,.max_power = 25},
++	{.hw_value = 6,.center_freq = 2437,.max_power = 25},
++	{.hw_value = 7,.center_freq = 2442,.max_power = 25},
++	{.hw_value = 8,.center_freq = 2447,.max_power = 25},
++	{.hw_value = 9,.center_freq = 2452,.max_power = 25},
++	{.hw_value = 10,.center_freq = 2457,.max_power = 25},
++	{.hw_value = 11,.center_freq = 2462,.max_power = 25},
++	{.hw_value = 12,.center_freq = 2467,.max_power = 25},
++	{.hw_value = 13,.center_freq = 2472,.max_power = 25},
++	//{ .hw_value = 14, .center_freq = 2484, .max_power = 25 },
++};
++
++/* 11G rate */
++static struct ieee80211_rate esp_rates_2ghz[] = {
++	{
++	 .bitrate = 10,
++	 .hw_value = CONF_HW_BIT_RATE_1MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_1MBPS,
++	 },
++	{
++	 .bitrate = 20,
++	 .hw_value = CONF_HW_BIT_RATE_2MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_2MBPS,
++	 .flags = IEEE80211_RATE_SHORT_PREAMBLE},
++	{
++	 .bitrate = 55,
++	 .hw_value = CONF_HW_BIT_RATE_5_5MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_5_5MBPS,
++	 .flags = IEEE80211_RATE_SHORT_PREAMBLE},
++	{
++	 .bitrate = 110,
++	 .hw_value = CONF_HW_BIT_RATE_11MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_11MBPS,
++	 .flags = IEEE80211_RATE_SHORT_PREAMBLE},
++	{
++	 .bitrate = 60,
++	 .hw_value = CONF_HW_BIT_RATE_6MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_6MBPS,
++	 },
++	{
++	 .bitrate = 90,
++	 .hw_value = CONF_HW_BIT_RATE_9MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_9MBPS,
++	 },
++	{
++	 .bitrate = 120,
++	 .hw_value = CONF_HW_BIT_RATE_12MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_12MBPS,
++	 },
++	{
++	 .bitrate = 180,
++	 .hw_value = CONF_HW_BIT_RATE_18MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_18MBPS,
++	 },
++	{
++	 .bitrate = 240,
++	 .hw_value = CONF_HW_BIT_RATE_24MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_24MBPS,
++	 },
++	{
++	 .bitrate = 360,
++	 .hw_value = CONF_HW_BIT_RATE_36MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_36MBPS,
++	 },
++	{
++	 .bitrate = 480,
++	 .hw_value = CONF_HW_BIT_RATE_48MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_48MBPS,
++	 },
++	{
++	 .bitrate = 540,
++	 .hw_value = CONF_HW_BIT_RATE_54MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_54MBPS,
++	 },
++};
++
++static void esp_pub_init_mac80211(struct esp_pub *epub)
++{
++	struct ieee80211_hw *hw = epub->hw;
++
++	static const u32 cipher_suites[] = {
++		WLAN_CIPHER_SUITE_WEP40,
++		WLAN_CIPHER_SUITE_WEP104,
++		WLAN_CIPHER_SUITE_TKIP,
++		WLAN_CIPHER_SUITE_CCMP,
++	};
++
++	hw->max_listen_interval = 10;
++
++	ieee80211_hw_set(hw, SIGNAL_DBM);
++	ieee80211_hw_set(hw, HAS_RATE_CONTROL);
++	ieee80211_hw_set(hw, SUPPORTS_PS);
++	ieee80211_hw_set(hw, AMPDU_AGGREGATION);
++	ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
++	//IEEE80211_HW_PS_NULLFUNC_STACK |   
++	//IEEE80211_HW_CONNECTION_MONITOR |
++	//IEEE80211_HW_BEACON_FILTER |
++	//IEEE80211_HW_AMPDU_AGGREGATION |
++	//IEEE80211_HW_REPORTS_TX_ACK_STATUS;
++	hw->max_rx_aggregation_subframes = 0x40;
++	hw->max_tx_aggregation_subframes = 0x40;
++
++	hw->wiphy->cipher_suites = cipher_suites;
++	hw->wiphy->n_cipher_suites = ARRAY_SIZE(cipher_suites);
++	hw->wiphy->max_scan_ie_len =
++	    epub->sip->tx_blksz - sizeof(struct sip_hdr) -
++	    sizeof(struct sip_cmd_scan);
++
++	/* ONLY station for now, support P2P soon... */
++	hw->wiphy->interface_modes =
++	    BIT(NL80211_IFTYPE_P2P_GO) |
++	    BIT(NL80211_IFTYPE_P2P_CLIENT) |
++	    BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
++
++	hw->wiphy->max_scan_ssids = 2;
++	//hw->wiphy->max_sched_scan_ssids = 16;
++	//hw->wiphy->max_match_sets = 16;
++
++	hw->wiphy->max_remain_on_channel_duration = 5000;
++
++	atomic_set(&epub->wl.off, 1);
++
++	epub->wl.sbands[NL80211_BAND_2GHZ].band = NL80211_BAND_2GHZ;
++	epub->wl.sbands[NL80211_BAND_2GHZ].channels = esp_channels_2ghz;
++	epub->wl.sbands[NL80211_BAND_2GHZ].bitrates = esp_rates_2ghz;
++	epub->wl.sbands[NL80211_BAND_2GHZ].n_channels =
++	    ARRAY_SIZE(esp_channels_2ghz);
++	epub->wl.sbands[NL80211_BAND_2GHZ].n_bitrates =
++	    ARRAY_SIZE(esp_rates_2ghz);
++	/*add to support 11n */
++	epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.ht_supported = true;
++	epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.cap = 0x116C;	//IEEE80211_HT_CAP_RX_STBC; //IEEE80211_HT_CAP_SGI_20;
++	epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.ampdu_factor =
++	    IEEE80211_HT_MAX_AMPDU_16K;
++	epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.ampdu_density =
++	    IEEE80211_HT_MPDU_DENSITY_NONE;
++	memset(&epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.mcs, 0,
++	       sizeof(epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.mcs));
++	epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.mcs.rx_mask[0] = 0xff;
++	//epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.mcs.rx_highest = 7;
++	//epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
++
++	/* BAND_5GHZ TBD */
++
++	hw->wiphy->bands[NL80211_BAND_2GHZ] =
++	    &epub->wl.sbands[NL80211_BAND_2GHZ];
++	/* BAND_5GHZ TBD */
++
++	/*no fragment */
++	hw->wiphy->frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD;
++
++	/* handle AC queue in f/w */
++	hw->queues = 4;
++	hw->max_rates = 4;
++	//hw->wiphy->reg_notifier = esp_reg_notify;
++
++	hw->vif_data_size = sizeof(struct esp_vif);
++	hw->sta_data_size = sizeof(struct esp_node);
++
++	//hw->max_rx_aggregation_subframes = 8;
++}
++
++int esp_register_mac80211(struct esp_pub *epub)
++{
++	int ret = 0;
++	u8 *wlan_addr;
++	u8 *p2p_addr;
++	int idx;
++
++	esp_pub_init_mac80211(epub);
++
++	epub->hw->wiphy->addresses = (struct mac_address *) esp_mac_addr;
++	memcpy(&epub->hw->wiphy->addresses[0], epub->mac_addr, ETH_ALEN);
++	memcpy(&epub->hw->wiphy->addresses[1], epub->mac_addr, ETH_ALEN);
++	wlan_addr = (u8 *) & epub->hw->wiphy->addresses[0];
++	p2p_addr = (u8 *) & epub->hw->wiphy->addresses[1];
++
++	for (idx = 0; idx < 64; idx++) {
++		p2p_addr[0] = wlan_addr[0] | 0x02;
++		p2p_addr[0] ^= idx << 2;
++		if (strncmp(p2p_addr, wlan_addr, 6) != 0)
++			break;
++	}
++
++	epub->hw->wiphy->n_addresses = 2;
++
++	ret = ieee80211_register_hw(epub->hw);
++
++	if (ret < 0) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "unable to register mac80211 hw: %d\n",
++				  ret);
++		return ret;
++	} else {
++#ifdef MAC80211_NO_CHANGE
++		rtnl_lock();
++		if (epub->hw->wiphy->interface_modes &
++		    (BIT(NL80211_IFTYPE_P2P_GO) |
++		     BIT(NL80211_IFTYPE_P2P_CLIENT))) {
++			ret =
++			    ieee80211_if_add(hw_to_local(epub->hw),
++					     "p2p%d", NULL,
++					     NL80211_IFTYPE_STATION, NULL);
++			if (ret)
++				wiphy_warn(epub->hw->wiphy,
++					   "Failed to add default virtual iface\n");
++		}
++
++		rtnl_unlock();
++#endif
++	}
++
++	set_bit(ESP_WL_FLAG_HW_REGISTERED, &epub->wl.flags);
++
++	return ret;
++}
++
++static u8 getaddr_index(u8 * addr, struct esp_pub *epub)
++{
++	int i;
++	for (i = 0; i < ESP_PUB_MAX_VIF; i++)
++		if (memcmp
++		    (addr, (u8 *) & epub->hw->wiphy->addresses[i],
++		     ETH_ALEN) == 0)
++			return i;
++	return ESP_PUB_MAX_VIF;
++}
+diff --git a/drivers/net/wireless/esp8089/esp_mac80211.h b/drivers/net/wireless/esp8089/esp_mac80211.h
+new file mode 100644
+index 000000000000..699b27dcadd1
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_mac80211.h
+@@ -0,0 +1,38 @@
++/*
++ * Copyright (c) 2011-2014 Espressif System.
++ *
++ *     MAC80211 support module
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#ifndef _ESP_MAC80211_H_
++#define _ESP_MAC80211_H_
++
++struct esp_80211_wmm_ac_param {
++	u8 aci_aifsn;		/* AIFSN, ACM, ACI */
++	u8 cw;			/* ECWmin, ECWmax (CW = 2^ECW - 1) */
++	u16 txop_limit;
++};
++
++struct esp_80211_wmm_param_element {
++	/* Element ID： 221 (0xdd); length: 24 */
++	/* required fields for WMM version 1 */
++	u8 oui[3];		/* 00:50:f2 */
++	u8 oui_type;		/* 2 */
++	u8 oui_subtype;		/* 1 */
++	u8 version;		/* 1 for WMM version 1.0 */
++	u8 qos_info;		/* AP/STA specif QoS info */
++	u8 reserved;		/* 0 */
++	struct esp_80211_wmm_ac_param ac[4];	/* AC_BE, AC_BK, AC_VI, AC_VO */
++};
++
++
++#endif				/* _ESP_MAC80211_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_main.c b/drivers/net/wireless/esp8089/esp_main.c
+new file mode 100644
+index 000000000000..404e0d7a6f54
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_main.c
+@@ -0,0 +1,263 @@
++/*
++ * Copyright (c) 2010 - 2014 Espressif System.
++ *
++ * main routine
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/rtnetlink.h>
++#include <linux/firmware.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <net/cfg80211.h>
++#include <net/mac80211.h>
++#include <linux/time.h>
++#include <linux/moduleparam.h>
++
++#include "esp_pub.h"
++#include "esp_sip.h"
++#include "esp_sif.h"
++#include "esp_debug.h"
++#include "esp_file.h"
++#include "esp_wl.h"
++
++struct completion *gl_bootup_cplx = NULL;
++
++#ifndef FPGA_DEBUG
++static int esp_download_fw(struct esp_pub *epub);
++#endif				/* !FGPA_DEBUG */
++
++static int modparam_no_txampdu = 0;
++static int modparam_no_rxampdu = 0;
++module_param_named(no_txampdu, modparam_no_txampdu, int, 0444);
++MODULE_PARM_DESC(no_txampdu, "Disable tx ampdu.");
++module_param_named(no_rxampdu, modparam_no_rxampdu, int, 0444);
++MODULE_PARM_DESC(no_rxampdu, "Disable rx ampdu.");
++
++static char *modparam_eagle_path = "/lib/firmware";
++module_param_named(eagle_path, modparam_eagle_path, charp, 0444);
++MODULE_PARM_DESC(eagle_path, "eagle path");
++
++bool mod_support_no_txampdu()
++{
++	return modparam_no_txampdu;
++}
++
++bool mod_support_no_rxampdu()
++{
++	return modparam_no_rxampdu;
++}
++
++void mod_support_no_txampdu_set(bool value)
++{
++	modparam_no_txampdu = value;
++}
++
++char *mod_eagle_path_get(void)
++{
++	if (modparam_eagle_path[0] == '\0')
++		return NULL;
++
++	return modparam_eagle_path;
++}
++
++int esp_pub_init_all(struct esp_pub *epub)
++{
++	int ret = 0;
++
++	/* completion for bootup event poll */
++	DECLARE_COMPLETION_ONSTACK(complete);
++	atomic_set(&epub->ps.state, ESP_PM_OFF);
++	if (epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT) {
++		epub->sip = sip_attach(epub);
++		if (epub->sip == NULL) {
++			printk(KERN_ERR "%s sip alloc failed\n", __func__);
++			return -ENOMEM;
++		}
++
++		esp_dump_var("esp_msg_level", NULL, &esp_msg_level,
++			     ESP_U32);
++
++#ifdef ESP_ANDROID_LOGGER
++		esp_dump_var("log_off", NULL, &log_off, ESP_U32);
++#endif				/* ESP_ANDROID_LOGGER */
++	} else {
++		atomic_set(&epub->sip->state, SIP_PREPARE_BOOT);
++		atomic_set(&epub->sip->tx_credits, 0);
++	}
++
++	epub->sip->to_host_seq = 0;
++
++#ifdef TEST_MODE
++	if (sif_get_ate_config() != 0 && sif_get_ate_config() != 1
++	    && sif_get_ate_config() != 6) {
++		esp_test_init(epub);
++		return -1;
++	}
++#endif
++
++#ifndef FPGA_DEBUG
++	ret = esp_download_fw(epub);
++#ifdef TEST_MODE
++	if (sif_get_ate_config() == 6) {
++		sif_enable_irq(epub);
++		mdelay(500);
++		sif_disable_irq(epub);
++		mdelay(1000);
++		esp_test_init(epub);
++		return -1;
++	}
++#endif
++	if (ret) {
++		esp_dbg(ESP_DBG_ERROR, "download firmware failed\n");
++		return ret;
++	}
++
++	esp_dbg(ESP_DBG_TRACE, "download firmware OK \n");
++#else
++	sip_send_bootup(epub->sip);
++#endif				/* FPGA_DEBUG */
++
++	gl_bootup_cplx = &complete;
++	epub->wait_reset = 0;
++	sif_enable_irq(epub);
++
++	if (epub->sdio_state == ESP_SDIO_STATE_SECOND_INIT
++	    || sif_get_ate_config() == 1) {
++		ret = sip_poll_bootup_event(epub->sip);
++	} else {
++		ret = sip_poll_resetting_event(epub->sip);
++		if (ret == 0) {
++			sif_lock_bus(epub);
++			sif_interrupt_target(epub, 7);
++			sif_unlock_bus(epub);
++		}
++
++	}
++
++	gl_bootup_cplx = NULL;
++
++	if (sif_get_ate_config() == 1)
++		ret = -EOPNOTSUPP;
++
++	return ret;
++}
++
++void esp_dsr(struct esp_pub *epub)
++{
++	sip_rx(epub);
++}
++
++
++struct esp_fw_hdr {
++	u8 magic;
++	u8 blocks;
++	u8 pad[2];
++	u32 entry_addr;
++} __packed;
++
++struct esp_fw_blk_hdr {
++	u32 load_addr;
++	u32 data_len;
++} __packed;
++
++#define ESP_FW_NAME1 "eagle_fw_ate_config_v19.bin"
++#define ESP_FW_NAME2 "eagle_fw_first_init_v19.bin"
++#define ESP_FW_NAME3 "eagle_fw_second_init_v19.bin"
++
++#ifndef FPGA_DEBUG
++static int esp_download_fw(struct esp_pub *epub)
++{
++	const struct firmware *fw_entry;
++	u8 *fw_buf = NULL;
++	u32 offset = 0;
++	int ret = 0;
++	u8 blocks;
++	struct esp_fw_hdr *fhdr;
++	struct esp_fw_blk_hdr *bhdr = NULL;
++	struct sip_cmd_bootup bootcmd;
++	char *esp_fw_name;
++
++	if (sif_get_ate_config() == 1) {
++		esp_fw_name = ESP_FW_NAME3;
++	} else {
++		esp_fw_name =
++		    epub->sdio_state ==
++		    ESP_SDIO_STATE_FIRST_INIT ? ESP_FW_NAME1 :
++		    ESP_FW_NAME2;
++	}
++	ret = request_firmware(&fw_entry, esp_fw_name, epub->dev);
++
++	if (ret)
++		return ret;
++
++	fw_buf = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
++
++	release_firmware(fw_entry);
++
++	if (fw_buf == NULL) {
++		return -ENOMEM;
++	}
++
++	fhdr = (struct esp_fw_hdr *) fw_buf;
++
++	if (fhdr->magic != 0xE9) {
++		esp_dbg(ESP_DBG_ERROR, "%s wrong magic! \n", __func__);
++		goto _err;
++	}
++
++	blocks = fhdr->blocks;
++	offset += sizeof(struct esp_fw_hdr);
++
++	while (blocks) {
++
++		bhdr = (struct esp_fw_blk_hdr *) (&fw_buf[offset]);
++		offset += sizeof(struct esp_fw_blk_hdr);
++
++		ret =
++		    sip_write_memory(epub->sip, bhdr->load_addr,
++				     &fw_buf[offset], bhdr->data_len);
++
++		if (ret) {
++			esp_dbg(ESP_DBG_ERROR,
++				"%s Failed to write fw, err: %d\n",
++				__func__, ret);
++			goto _err;
++		}
++
++		blocks--;
++		offset += bhdr->data_len;
++	}
++
++	/* TODO: last byte should be the checksum and skip checksum for now */
++
++	bootcmd.boot_addr = fhdr->entry_addr;
++	ret =
++	    sip_send_cmd(epub->sip, SIP_CMD_BOOTUP,
++			 sizeof(struct sip_cmd_bootup), &bootcmd);
++
++	if (ret)
++		goto _err;
++
++      _err:
++	kfree(fw_buf);
++
++	return ret;
++
++}
++
++MODULE_FIRMWARE(ESP_FW_NAME1);
++MODULE_FIRMWARE(ESP_FW_NAME2);
++MODULE_FIRMWARE(ESP_FW_NAME3);
++#endif				/* !FPGA_DEBUG */
+diff --git a/drivers/net/wireless/esp8089/esp_path.h b/drivers/net/wireless/esp8089/esp_path.h
+new file mode 100644
+index 000000000000..1ceb14bc3b15
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_path.h
+@@ -0,0 +1,6 @@
++#ifndef _ESP_PATH_H_
++#define _ESP_PATH_H_
++#define FWPATH "/lib/firmware"
++//module_param_string(fwpath, fwpath, sizeof(fwpath), 0644);
++
++#endif				/* _ESP_PATH_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_pub.h b/drivers/net/wireless/esp8089/esp_pub.h
+new file mode 100644
+index 000000000000..0d3ad3655cf4
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_pub.h
+@@ -0,0 +1,222 @@
++/*
++ * Copyright (c) 2011-2014 Espressif System.
++ *
++ *   wlan device header file
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_PUB_H_
++#define _ESP_PUB_H_
++
++#include <linux/etherdevice.h>
++#include <linux/rtnetlink.h>
++#include <linux/firmware.h>
++#include <linux/sched.h>
++#include <net/mac80211.h>
++#include <net/cfg80211.h>
++#include <linux/version.h>
++#include "sip2_common.h"
++
++enum esp_sdio_state {
++	ESP_SDIO_STATE_FIRST_INIT,
++	ESP_SDIO_STATE_FIRST_NORMAL_EXIT,
++	ESP_SDIO_STATE_FIRST_ERROR_EXIT,
++	ESP_SDIO_STATE_SECOND_INIT,
++	ESP_SDIO_STATE_SECOND_ERROR_EXIT,
++};
++
++enum esp_tid_state {
++	ESP_TID_STATE_INIT,
++	ESP_TID_STATE_TRIGGER,
++	ESP_TID_STATE_PROGRESS,
++	ESP_TID_STATE_OPERATIONAL,
++	ESP_TID_STATE_WAIT_STOP,
++	ESP_TID_STATE_STOP,
++};
++
++struct esp_tx_tid {
++	u8 state;
++	u8 cnt;
++	u16 ssn;
++};
++
++#define WME_NUM_TID 16
++struct esp_node {
++	struct esp_tx_tid tid[WME_NUM_TID];
++	struct ieee80211_sta *sta;
++	u8 ifidx;
++	u8 index;
++};
++
++#define WME_AC_BE 2
++#define WME_AC_BK 3
++#define WME_AC_VI 1
++#define WME_AC_VO 0
++
++struct llc_snap_hdr {
++	u8 dsap;
++	u8 ssap;
++	u8 cntl;
++	u8 org_code[3];
++	__be16 eth_type;
++} __packed;
++
++struct esp_vif {
++	struct esp_pub *epub;
++	u8 index;
++	u32 beacon_interval;
++	bool ap_up;
++	struct timer_list beacon_timer;
++};
++
++/* WLAN related, mostly... */
++/*struct hw_scan_timeout {
++        struct delayed_work w;
++        struct ieee80211_hw *hw;
++};*/
++
++typedef struct esp_wl {
++	u8 bssid[ETH_ALEN];
++	u8 req_bssid[ETH_ALEN];
++
++	//struct hw_scan_timeout *hsd;
++	struct cfg80211_scan_request *scan_req;
++	atomic_t ptk_cnt;
++	atomic_t gtk_cnt;
++	atomic_t tkip_key_set;
++
++	/* so far only 2G band */
++	struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
++
++	unsigned long flags;
++	atomic_t off;
++} esp_wl_t;
++
++typedef struct esp_hw_idx_map {
++	u8 mac[ETH_ALEN];
++	u8 flag;
++} esp_hw_idx_map_t;
++
++#define ESP_WL_FLAG_RFKILL                	BIT(0)
++#define ESP_WL_FLAG_HW_REGISTERED   		BIT(1)
++#define ESP_WL_FLAG_CONNECT              		BIT(2)
++#define ESP_WL_FLAG_STOP_TXQ          		BIT(3)
++
++#define ESP_PUB_MAX_VIF		2
++#define ESP_PUB_MAX_STA		16	//for one interface
++#define ESP_PUB_MAX_RXAMPDU	8	//for all interfaces
++
++enum {
++	ESP_PM_OFF = 0,
++	ESP_PM_TURNING_ON,
++	ESP_PM_ON,
++	ESP_PM_TURNING_OFF,	/* Do NOT change the order */
++};
++
++struct esp_ps {
++	u32 dtim_period;
++	u32 max_sleep_period;
++	unsigned long last_config_time;
++	atomic_t state;
++	bool nulldata_pm_on;
++};
++
++struct esp_mac_prefix {
++	u8 mac_index;
++	u8 mac_addr_prefix[3];
++};
++
++struct esp_pub {
++	struct device *dev;
++#ifdef ESP_NO_MAC80211
++	struct net_device *net_dev;
++	struct wireless_dev *wdev;
++	struct net_device_stats *net_stats;
++#else
++	struct ieee80211_hw *hw;
++	struct ieee80211_vif *vif;
++	u8 vif_slot;
++#endif				/* ESP_MAC80211 */
++
++	void *sif;		/* serial interface control block, e.g. sdio */
++	enum esp_sdio_state sdio_state;
++	struct esp_sip *sip;
++	struct esp_wl wl;
++	struct esp_hw_idx_map hi_map[19];
++	struct esp_hw_idx_map low_map[ESP_PUB_MAX_VIF][2];
++	//u32 flags; //flags to represent rfkill switch,start
++	u8 roc_flags;		//0: not in remain on channel state, 1: in roc state
++
++	struct work_struct tx_work;	/* attach to ieee80211 workqueue */
++	/* latest mac80211 has multiple tx queue, but we stick with single queue now */
++	spinlock_t rx_lock;
++	spinlock_t tx_ampdu_lock;
++	spinlock_t rx_ampdu_lock;
++	spinlock_t tx_lock;
++	struct mutex tx_mtx;
++	struct sk_buff_head txq;
++	atomic_t txq_stopped;
++
++	struct work_struct sendup_work;	/* attach to ieee80211 workqueue */
++	struct sk_buff_head txdoneq;
++	struct sk_buff_head rxq;
++
++	struct workqueue_struct *esp_wkq;
++
++	//u8 bssid[ETH_ALEN];
++	u8 mac_addr[ETH_ALEN];
++
++	u32 rx_filter;
++	unsigned long scan_permit;
++	bool scan_permit_valid;
++	struct delayed_work scan_timeout_work;
++	u32 enodes_map;
++	u8 rxampdu_map;
++	u32 enodes_maps[ESP_PUB_MAX_VIF];
++	struct esp_node *enodes[ESP_PUB_MAX_STA + 1];
++	struct esp_node *rxampdu_node[ESP_PUB_MAX_RXAMPDU];
++	u8 rxampdu_tid[ESP_PUB_MAX_RXAMPDU];
++	struct esp_ps ps;
++	int enable_int;
++	int wait_reset;
++};
++
++typedef struct esp_pub esp_pub_t;
++
++struct esp_pub *esp_pub_alloc_mac80211(struct device *dev);
++int esp_pub_dealloc_mac80211(struct esp_pub *epub);
++int esp_register_mac80211(struct esp_pub *epub);
++
++int esp_pub_init_all(struct esp_pub *epub);
++
++char *mod_eagle_path_get(void);
++
++void esp_dsr(struct esp_pub *epub);
++void hw_scan_done(struct esp_pub *epub, bool aborted);
++void esp_rocdone_process(struct ieee80211_hw *hw,
++			 struct sip_evt_roc *report);
++
++void esp_ps_config(struct esp_pub *epub, struct esp_ps *ps, bool on);
++
++struct esp_node *esp_get_node_by_addr(struct esp_pub *epub,
++				      const u8 * addr);
++struct esp_node *esp_get_node_by_index(struct esp_pub *epub, u8 index);
++int esp_get_empty_rxampdu(struct esp_pub *epub, const u8 * addr, u8 tid);
++int esp_get_exist_rxampdu(struct esp_pub *epub, const u8 * addr, u8 tid);
++
++#ifdef TEST_MODE
++int test_init_netlink(struct esp_sip *sip);
++void test_exit_netlink(void);
++void esp_test_cmd_event(u32 cmd_type, char *reply_info);
++void esp_test_init(struct esp_pub *epub);
++#endif
++#endif				/* _ESP_PUB_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_sif.h b/drivers/net/wireless/esp8089/esp_sif.h
+new file mode 100644
+index 000000000000..2d49f2bc8035
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_sif.h
+@@ -0,0 +1,207 @@
++/*
++ * Copyright (c) 2011 - 2014 Espressif System.
++ *
++ *   Serial I/F wrapper layer for eagle WLAN device,
++ *    abstraction of buses like SDIO/SIP, and provides
++ *    flow control for tx/rx layer
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_SIF_H_
++#define _ESP_SIF_H_
++
++#include "esp_pub.h"
++#include <linux/mmc/host.h>
++#include <linux/spi/spi.h>
++
++/*
++ *  H/W SLC module definitions
++ */
++
++#define SIF_SLC_BLOCK_SIZE                512
++
++
++/* S/W struct mapping to slc registers */
++typedef struct slc_host_regs {
++	/* do NOT read token_rdata
++	 *
++	 u32 pf_data;
++	 u32 token_rdata;
++	 */
++	u32 intr_raw;
++	u32 state_w0;
++	u32 state_w1;
++	u32 config_w0;
++	u32 config_w1;
++	u32 intr_status;
++	u32 config_w2;
++	u32 config_w3;
++	u32 config_w4;
++	u32 token_wdata;
++	u32 intr_clear;
++	u32 intr_enable;
++} sif_slc_reg_t;
++
++
++enum io_sync_type {
++	ESP_SIF_NOSYNC = 0,
++	ESP_SIF_SYNC,
++};
++
++typedef struct esp_sdio_ctrl {
++	struct sdio_func *func;
++	struct esp_pub *epub;
++
++
++	struct list_head free_req;
++
++	u8 *dma_buffer;
++
++	spinlock_t scat_lock;
++	struct list_head scat_req;
++
++	bool off;
++	atomic_t irq_handling;
++	const struct sdio_device_id *id;
++	u32 slc_blk_sz;
++	u32 target_id;
++	u32 slc_window_end_addr;
++
++	struct slc_host_regs slc_regs;
++	atomic_t irq_installed;
++
++} esp_sdio_ctrl_t;
++
++#define SIF_TO_DEVICE                    0x1
++#define SIF_FROM_DEVICE                    0x2
++
++#define SIF_SYNC             0x00000010
++#define SIF_ASYNC           0x00000020
++
++#define SIF_BYTE_BASIS              0x00000040
++#define SIF_BLOCK_BASIS             0x00000080
++
++#define SIF_FIXED_ADDR           0x00000100
++#define SIF_INC_ADDR     0x00000200
++
++#define EPUB_CTRL_CHECK(_epub, _go_err) do{\
++	if (_epub == NULL) {\
++		ESSERT(0);\
++		goto _go_err;\
++	}\
++	if ((_epub)->sif == NULL) {\
++		ESSERT(0);\
++		goto _go_err;\
++	}\
++}while(0)
++
++#define EPUB_FUNC_CHECK(_epub, _go_err) do{\
++	if (_epub == NULL) {\
++		ESSERT(0);\
++		goto _go_err;\
++	}\
++	if ((_epub)->sif == NULL) {\
++		ESSERT(0);\
++		goto _go_err;\
++	}\
++	if (((struct esp_sdio_ctrl *)(_epub)->sif)->func == NULL) {\
++		ESSERT(0);\
++		goto _go_err;\
++	}\
++}while(0)
++
++#define EPUB_TO_CTRL(_epub) (((struct esp_sdio_ctrl *)(_epub)->sif))
++
++#define EPUB_TO_FUNC(_epub) (((struct esp_sdio_ctrl *)(_epub)->sif)->func)
++
++void sdio_io_writeb(struct esp_pub *epub, u8 value, int addr, int *res);
++u8 sdio_io_readb(struct esp_pub *epub, int addr, int *res);
++
++
++void sif_enable_irq(struct esp_pub *epub);
++void sif_disable_irq(struct esp_pub *epub);
++void sif_disable_target_interrupt(struct esp_pub *epub);
++
++u32 sif_get_blksz(struct esp_pub *epub);
++u32 sif_get_target_id(struct esp_pub *epub);
++
++void sif_dsr(struct sdio_func *func);
++int sif_io_raw(struct esp_pub *epub, u32 addr, u8 * buf, u32 len,
++	       u32 flag);
++int sif_io_sync(struct esp_pub *epub, u32 addr, u8 * buf, u32 len,
++		u32 flag);
++int sif_io_async(struct esp_pub *epub, u32 addr, u8 * buf, u32 len,
++		 u32 flag, void *context);
++int sif_lldesc_read_sync(struct esp_pub *epub, u8 * buf, u32 len);
++int sif_lldesc_write_sync(struct esp_pub *epub, u8 * buf, u32 len);
++int sif_lldesc_read_raw(struct esp_pub *epub, u8 * buf, u32 len,
++			bool noround);
++int sif_lldesc_write_raw(struct esp_pub *epub, u8 * buf, u32 len);
++
++int sif_platform_get_irq_no(void);
++int sif_platform_is_irq_occur(void);
++void sif_platform_irq_clear(void);
++void sif_platform_irq_mask(int enable_mask);
++int sif_platform_irq_init(void);
++void sif_platform_irq_deinit(void);
++
++int esp_common_read(struct esp_pub *epub, u8 * buf, u32 len, int sync,
++		    bool noround);
++int esp_common_write(struct esp_pub *epub, u8 * buf, u32 len, int sync);
++int esp_common_read_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++			      u32 len, int sync);
++int esp_common_write_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++			       u32 len, int sync);
++
++int esp_common_readbyte_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++				  int sync);
++int esp_common_writebyte_with_addr(struct esp_pub *epub, u32 addr, u8 buf,
++				   int sync);
++
++int sif_read_reg_window(struct esp_pub *epub, unsigned int reg_addr,
++			unsigned char *value);
++int sif_write_reg_window(struct esp_pub *epub, unsigned int reg_addr,
++			 unsigned char *value);
++int sif_ack_target_read_err(struct esp_pub *epub);
++int sif_had_io_enable(struct esp_pub *epub);
++
++struct slc_host_regs *sif_get_regs(struct esp_pub *epub);
++
++void sif_lock_bus(struct esp_pub *epub);
++void sif_unlock_bus(struct esp_pub *epub);
++
++int sif_interrupt_target(struct esp_pub *epub, u8 index);
++#ifdef USE_EXT_GPIO
++int sif_config_gpio_mode(struct esp_pub *epub, u8 gpio_num, u8 gpio_mode);
++int sif_set_gpio_output(struct esp_pub *epub, u16 mask, u16 value);
++int sif_get_gpio_intr(struct esp_pub *epub, u16 intr_mask, u16 * value);
++int sif_get_gpio_input(struct esp_pub *epub, u16 * mask, u16 * value);
++#endif
++
++void check_target_id(struct esp_pub *epub);
++
++void sif_record_bt_config(int value);
++int sif_get_bt_config(void);
++void sif_record_rst_config(int value);
++int sif_get_rst_config(void);
++void sif_record_ate_config(int value);
++int sif_get_ate_config(void);
++void sif_record_retry_config(void);
++int sif_get_retry_config(void);
++void sif_record_wakeup_gpio_config(int value);
++int sif_get_wakeup_gpio_config(void);
++
++#define sif_reg_read_sync(epub, addr, buf, len) sif_io_sync((epub), (addr), (buf), (len), SIF_FROM_DEVICE | SIF_BYTE_BASIS | SIF_INC_ADDR)
++
++#define sif_reg_write_sync(epub, addr, buf, len) sif_io_sync((epub), (addr), (buf), (len), SIF_TO_DEVICE | SIF_BYTE_BASIS | SIF_INC_ADDR)
++
++#endif				/* _ESP_SIF_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_sip.c b/drivers/net/wireless/esp8089/esp_sip.c
+new file mode 100644
+index 000000000000..6602a1e22ab1
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_sip.c
+@@ -0,0 +1,2420 @@
++/*
++ * Copyright (c) 2009 - 2014 Espressif System.
++ *
++ * Serial Interconnctor Protocol
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/ieee80211.h>
++#include <net/mac80211.h>
++#include <net/cfg80211.h>
++#include <linux/skbuff.h>
++#include <linux/bitops.h>
++#include <linux/version.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sd.h>
++#include <linux/completion.h>
++#include <linux/timer.h>
++
++#include "esp_mac80211.h"
++#include "esp_pub.h"
++#include "esp_sip.h"
++#include "esp_ctrl.h"
++#include "esp_sif.h"
++#include "esp_debug.h"
++#include "slc_host_register.h"
++#include "esp_wmac.h"
++#include "esp_utils.h"
++
++#ifdef USE_EXT_GPIO
++#include "esp_ext.h"
++#endif				/* USE_EXT_GPIO */
++
++extern struct completion *gl_bootup_cplx;
++
++static int old_signal = -35;
++static int avg_signal = 0;
++static int signal_loop = 0;
++
++struct esp_mac_prefix esp_mac_prefix_table[] = {
++	{0, {0x18, 0xfe, 0x34}},
++	{1, {0xac, 0xd0, 0x74}},
++	{255, {0x18, 0xfe, 0x34}},
++};
++
++#define SIGNAL_COUNT  300
++
++#define TID_TO_AC(_tid) ((_tid)== 0||((_tid)==3)?WME_AC_BE:((_tid)<3)?WME_AC_BK:((_tid)<6)?WME_AC_VI:WME_AC_VO)
++
++#ifdef SIP_DEBUG
++#define esp_sip_dbg esp_dbg
++struct sip_trace {
++	u32 tx_data;
++	u32 tx_cmd;
++	u32 rx_data;
++	u32 rx_evt;
++	u32 rx_tx_status;
++	u32 tx_out_of_credit;
++	u32 tx_one_shot_overflow;
++};
++static struct sip_trace str;
++#define STRACE_TX_DATA_INC() (str.tx_data++)
++#define STRACE_TX_CMD_INC()  (str.tx_cmd++)
++#define STRACE_RX_DATA_INC() (str.rx_data++)
++#define STRACE_RX_EVENT_INC() (str.rx_evt++)
++#define STRACE_RX_TXSTATUS_INC() (str.rx_tx_status++)
++#define STRACE_TX_OUT_OF_CREDIT_INC() (str.tx_out_of_credit++)
++#define STRACE_TX_ONE_SHOT_INC() (str.tx_one_shot_overflow++)
++#define STRACE_SHOW(sip)
++#else
++#define esp_sip_dbg(...)
++#define STRACE_TX_DATA_INC()
++#define STRACE_TX_CMD_INC()
++#define STRACE_RX_DATA_INC()
++#define STRACE_RX_EVENT_INC()
++#define STRACE_RX_TXSTATUS_INC()
++#define STRACE_TX_OUT_OF_CREDIT_INC()
++#define STRACE_TX_ONE_SHOT_INC()
++#define STRACE_SHOW(sip)
++#endif				/* SIP_DEBUG */
++
++#define SIP_STOP_QUEUE_THRESHOLD 48
++#define SIP_RESUME_QUEUE_THRESHOLD  12
++
++#define SIP_MIN_DATA_PKT_LEN    (sizeof(struct esp_mac_rx_ctrl) + 24)	//24 is min 80211hdr
++
++#ifdef ESP_PREALLOC
++extern struct sk_buff *esp_get_sip_skb(int size);
++extern void esp_put_sip_skb(struct sk_buff **skb);
++
++extern u8 *esp_get_tx_aggr_buf(void);
++extern void esp_put_tx_aggr_buf(u8 ** p);
++
++#endif
++
++static void sip_recalc_credit_init(struct esp_sip *sip);
++
++static int sip_recalc_credit_claim(struct esp_sip *sip, int force);
++
++static void sip_recalc_credit_release(struct esp_sip *sip);
++
++static struct sip_pkt *sip_get_ctrl_buf(struct esp_sip *sip,
++					SIP_BUF_TYPE bftype);
++
++static void sip_reclaim_ctrl_buf(struct esp_sip *sip, struct sip_pkt *pkt,
++				 SIP_BUF_TYPE bftype);
++
++static void sip_free_init_ctrl_buf(struct esp_sip *sip);
++
++static int sip_pack_pkt(struct esp_sip *sip, struct sk_buff *skb,
++			int *pm_state);
++
++static struct esp_mac_rx_ctrl *sip_parse_normal_mac_ctrl(struct sk_buff
++							 *skb,
++							 int *pkt_len_enc,
++							 int *buf_len,
++							 int *pulled_len);
++
++static struct sk_buff *sip_parse_data_rx_info(struct esp_sip *sip,
++					      struct sk_buff *skb,
++					      int pkt_len_enc, int buf_len,
++					      struct esp_mac_rx_ctrl
++					      *mac_ctrl, int *pulled_len);
++
++static inline void sip_rx_pkt_enqueue(struct esp_sip *sip,
++				      struct sk_buff *skb);
++
++static void sip_after_write_pkts(struct esp_sip *sip);
++
++static void sip_update_tx_credits(struct esp_sip *sip,
++				  u16 recycled_credits);
++
++//static void sip_trigger_txq_process(struct esp_sip *sip);
++
++static bool sip_rx_pkt_process(struct esp_sip *sip, struct sk_buff *skb);
++
++static void sip_tx_status_report(struct esp_sip *sip, struct sk_buff *skb,
++				 struct ieee80211_tx_info *tx_info,
++				 bool success);
++
++#ifdef FPGA_TXDATA
++int sip_send_tx_data(struct esp_sip *sip);
++#endif				/* FPGA_TXDATA */
++
++#ifdef FPGA_LOOPBACK
++int sip_send_loopback_cmd_mblk(struct esp_sip *sip);
++#endif				/* FPGA_LOOPBACK */
++
++static bool check_ac_tid(u8 * pkt, u8 ac, u8 tid)
++{
++	struct ieee80211_hdr *wh = (struct ieee80211_hdr *) pkt;
++#ifdef TID_DEBUG
++	u16 real_tid = 0;
++#endif				//TID_DEBUG
++
++	if (ieee80211_is_data_qos(wh->frame_control)) {
++#ifdef TID_DEBUG
++		real_tid =
++		    *ieee80211_get_qos_ctl(wh) &
++		    IEEE80211_QOS_CTL_TID_MASK;
++
++		esp_sip_dbg(ESP_SHOW, "ac:%u, tid:%u, tid in pkt:%u\n", ac,
++			    tid, real_tid);
++		if (tid != real_tid) {
++			esp_sip_dbg(ESP_DBG_ERROR,
++				    "111 ac:%u, tid:%u, tid in pkt:%u\n",
++				    ac, tid, real_tid);
++		}
++		if (TID_TO_AC(tid) != ac) {
++			esp_sip_dbg(ESP_DBG_ERROR,
++				    "222 ac:%u, tid:%u, tid in pkt:%u\n",
++				    ac, tid, real_tid);
++		}
++#endif				/* TID_DEBUG */
++	} else if (ieee80211_is_mgmt(wh->frame_control)) {
++#ifdef TID_DEBUG
++		esp_sip_dbg(ESP_SHOW, "ac:%u, tid:%u\n", ac, tid);
++		if (tid != 7 || ac != WME_AC_VO) {
++			esp_sip_dbg(ESP_DBG_ERROR, "333 ac:%u, tid:%u\n",
++				    ac, tid);
++		}
++#endif				/* TID_DEBUG */
++	} else {
++		if (ieee80211_is_ctl(wh->frame_control)) {
++#ifdef TID_DEBUG
++			esp_sip_dbg(ESP_SHOW,
++				    "%s is ctrl pkt fc 0x%04x ac:%u, tid:%u, tid in pkt:%u\n",
++				    __func__, wh->frame_control, ac, tid,
++				    real_tid);
++#endif				/* TID_DEBUG */
++		} else {
++			if (tid != 0 || ac != WME_AC_BE) {
++				//show_buf(pkt, 24);
++				esp_sip_dbg(ESP_DBG_LOG,
++					    "444 ac:%u, tid:%u \n", ac,
++					    tid);
++				if (tid == 7 && ac == WME_AC_VO)
++					return false;
++			}
++			return true;	//hack to modify non-qos null data.
++
++		}
++	}
++
++	return false;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++static void sip_recalc_credit_timeout(struct timer_list *t)
++#else
++static void sip_recalc_credit_timeout(unsigned long data)
++#endif
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	struct esp_sip *sip = from_timer(sip, t, credit_timer);
++#else
++	struct esp_sip *sip = (struct esp_sip *) data;
++#endif
++
++	esp_dbg(ESP_DBG_ERROR, "rct");
++
++	sip_recalc_credit_claim(sip, 1);	/* recalc again */
++}
++
++static void sip_recalc_credit_init(struct esp_sip *sip)
++{
++	atomic_set(&sip->credit_status, RECALC_CREDIT_DISABLE);	//set it disable
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	timer_setup(&sip->credit_timer, sip_recalc_credit_timeout, 0);
++#else
++	init_timer(&sip->credit_timer);
++	sip->credit_timer.data = (unsigned long) sip;
++	sip->credit_timer.function = sip_recalc_credit_timeout;
++#endif
++}
++
++static int sip_recalc_credit_claim(struct esp_sip *sip, int force)
++{
++	int ret;
++
++	if (atomic_read(&sip->credit_status) == RECALC_CREDIT_ENABLE
++	    && force == 0)
++		return 1;
++
++	atomic_set(&sip->credit_status, RECALC_CREDIT_ENABLE);
++	ret = sip_send_recalc_credit(sip->epub);
++	if (ret) {
++		esp_dbg(ESP_DBG_ERROR, "%s error %d", __func__, ret);
++		return ret;
++	}
++	/*setup a timer for handle the abs_credit not receive */
++	mod_timer(&sip->credit_timer, jiffies + msecs_to_jiffies(2000));
++
++	esp_dbg(ESP_SHOW, "rcc");
++
++	return ret;
++}
++
++static void sip_recalc_credit_release(struct esp_sip *sip)
++{
++	esp_dbg(ESP_SHOW, "rcr");
++
++	if (atomic_read(&sip->credit_status) == RECALC_CREDIT_ENABLE) {
++		atomic_set(&sip->credit_status, RECALC_CREDIT_DISABLE);
++		del_timer_sync(&sip->credit_timer);
++	} else
++		esp_dbg(ESP_SHOW, "maybe bogus credit");
++}
++
++static void sip_update_tx_credits(struct esp_sip *sip,
++				  u16 recycled_credits)
++{
++	esp_sip_dbg(ESP_DBG_TRACE, "%s:before add, credits is %d\n",
++		    __func__, atomic_read(&sip->tx_credits));
++
++	if (recycled_credits & 0x800) {
++		atomic_set(&sip->tx_credits, (recycled_credits & 0x7ff));
++		sip_recalc_credit_release(sip);
++	} else
++		atomic_add(recycled_credits, &sip->tx_credits);
++
++	esp_sip_dbg(ESP_DBG_TRACE, "%s:after add %d, credits is %d\n",
++		    __func__, recycled_credits,
++		    atomic_read(&sip->tx_credits));
++}
++
++void sip_trigger_txq_process(struct esp_sip *sip)
++{
++	if (atomic_read(&sip->tx_credits) <= sip->credit_to_reserve + SIP_CTRL_CREDIT_RESERVE	//no credits, do nothing
++	    || atomic_read(&sip->credit_status) == RECALC_CREDIT_ENABLE)
++		return;
++
++	if (sip_queue_may_resume(sip)) {
++		/* wakeup upper queue only if we have sufficient credits */
++		esp_sip_dbg(ESP_DBG_TRACE, "%s wakeup ieee80211 txq \n",
++			    __func__);
++		atomic_set(&sip->epub->txq_stopped, false);
++		ieee80211_wake_queues(sip->epub->hw);
++	} else if (atomic_read(&sip->epub->txq_stopped)) {
++		esp_sip_dbg(ESP_DBG_TRACE,
++			    "%s can't wake txq, credits: %d \n", __func__,
++			    atomic_read(&sip->tx_credits));
++	}
++
++	if (!skb_queue_empty(&sip->epub->txq)) {
++		/* try to send out pkt already in sip queue once we have credits */
++		esp_sip_dbg(ESP_DBG_TRACE, "%s resume sip txq \n",
++			    __func__);
++
++#if !defined(FPGA_TXDATA)
++		if (sif_get_ate_config() == 0) {
++			ieee80211_queue_work(sip->epub->hw,
++					     &sip->epub->tx_work);
++		} else {
++			queue_work(sip->epub->esp_wkq,
++				   &sip->epub->tx_work);
++		}
++#else
++		queue_work(sip->epub->esp_wkq, &sip->epub->tx_work);
++#endif
++	}
++}
++
++static bool sip_ampdu_occupy_buf(struct esp_sip *sip,
++				 struct esp_rx_ampdu_len *ampdu_len)
++{
++	return (ampdu_len->substate == 0
++		|| esp_wmac_rxsec_error(ampdu_len->substate)
++		|| (sip->dump_rpbm_err
++		    && ampdu_len->substate == RX_RPBM_ERR));
++}
++
++static bool sip_rx_pkt_process(struct esp_sip *sip, struct sk_buff *skb)
++{
++#define DO_NOT_COPY false
++#define DO_COPY true
++
++	struct sip_hdr *hdr = NULL;
++	struct sk_buff *rskb = NULL;
++	int remains_len = 0;
++	int first_pkt_len = 0;
++	u8 *bufptr = NULL;
++	int ret = 0;
++	bool trigger_rxq = false;
++
++	if (skb == NULL) {
++		esp_sip_dbg(ESP_DBG_ERROR, "%s NULL SKB!!!!!!!! \n",
++			    __func__);
++		return trigger_rxq;
++	}
++
++	hdr = (struct sip_hdr *) skb->data;
++	bufptr = skb->data;
++
++
++	esp_sip_dbg(ESP_DBG_TRACE, "%s Hcredits 0x%08x, realCredits %d\n",
++		    __func__, hdr->h_credits,
++		    hdr->h_credits & SIP_CREDITS_MASK);
++	if (hdr->h_credits & SIP_CREDITS_MASK) {
++		sip_update_tx_credits(sip,
++				      hdr->h_credits & SIP_CREDITS_MASK);
++	}
++
++	hdr->h_credits &= ~SIP_CREDITS_MASK;	/* clean credits in sip_hdr, prevent over-add */
++
++	esp_sip_dbg(ESP_DBG_TRACE, "%s credits %d\n", __func__,
++		    hdr->h_credits);
++
++	/*
++	 * first pkt's length is stored in  recycled_credits first 20 bits
++	 * config w3 [31:12]
++	 * repair hdr->len of first pkt
++	 */
++	remains_len = hdr->len;
++	first_pkt_len = hdr->h_credits >> 12;
++	hdr->len = first_pkt_len;
++
++	esp_dbg(ESP_DBG_TRACE, "%s first_pkt_len %d, whole pkt len %d \n",
++		__func__, first_pkt_len, remains_len);
++	if (first_pkt_len > remains_len) {
++		sip_recalc_credit_claim(sip, 0);
++		esp_dbg(ESP_DBG_ERROR,
++			"first_pkt_len %d, whole pkt len %d\n",
++			first_pkt_len, remains_len);
++		show_buf((u8 *) hdr, first_pkt_len);
++		ESSERT(0);
++		goto _exit;
++	}
++
++	/*
++	 * pkts handling, including the first pkt, should alloc new skb for each data pkt.
++	 * free the original whole skb after parsing is done.
++	 */
++	while (remains_len) {
++		if (remains_len < sizeof(struct sip_hdr)) {
++			sip_recalc_credit_claim(sip, 0);
++			ESSERT(0);
++			show_buf((u8 *) hdr, 512);
++			goto _exit;
++		}
++
++		hdr = (struct sip_hdr *) bufptr;
++		if (hdr->len <= 0) {
++			sip_recalc_credit_claim(sip, 0);
++			show_buf((u8 *) hdr, 512);
++			ESSERT(0);
++			goto _exit;
++		}
++
++		if ((hdr->len & 3) != 0) {
++			sip_recalc_credit_claim(sip, 0);
++			show_buf((u8 *) hdr, 512);
++			ESSERT(0);
++			goto _exit;
++		}
++		if (unlikely(hdr->seq != sip->rxseq++)) {
++			sip_recalc_credit_claim(sip, 0);
++			esp_dbg(ESP_DBG_ERROR,
++				"%s seq mismatch! got %u, expect %u\n",
++				__func__, hdr->seq, sip->rxseq - 1);
++			sip->rxseq = hdr->seq + 1;
++			show_buf(bufptr, 32);
++			ESSERT(0);
++		}
++
++		if (SIP_HDR_IS_CTRL(hdr)) {
++			STRACE_RX_EVENT_INC();
++			esp_sip_dbg(ESP_DBG_TRACE, "seq %u \n", hdr->seq);
++
++			ret = sip_parse_events(sip, bufptr);
++
++			skb_pull(skb, hdr->len);
++
++		} else if (SIP_HDR_IS_DATA(hdr)) {
++			struct esp_mac_rx_ctrl *mac_ctrl = NULL;
++			int pkt_len_enc = 0, buf_len = 0, pulled_len = 0;
++
++			STRACE_RX_DATA_INC();
++			esp_sip_dbg(ESP_DBG_TRACE, "seq %u \n", hdr->seq);
++			mac_ctrl =
++			    sip_parse_normal_mac_ctrl(skb, &pkt_len_enc,
++						      &buf_len,
++						      &pulled_len);
++			rskb =
++			    sip_parse_data_rx_info(sip, skb, pkt_len_enc,
++						   buf_len, mac_ctrl,
++						   &pulled_len);
++
++			if (rskb == NULL)
++				goto _move_on;
++
++			if (likely(atomic_read(&sip->epub->wl.off) == 0)) {
++#ifdef RX_CHECKSUM_TEST
++				esp_rx_checksum_test(rskb);
++#endif
++				local_bh_disable();
++				ieee80211_rx(sip->epub->hw, rskb);
++				local_bh_enable();
++			} else {
++				/* still need go thro parsing as skb_pull should invoke */
++				kfree_skb(rskb);
++			}
++		} else if (SIP_HDR_IS_AMPDU(hdr)) {
++			struct esp_mac_rx_ctrl *mac_ctrl = NULL;
++			struct esp_mac_rx_ctrl new_mac_ctrl;
++			struct esp_rx_ampdu_len *ampdu_len;
++			int pkt_num;
++			int pulled_len = 0;
++			static int pkt_dropped = 0;
++			static int pkt_total = 0;
++			bool have_rxabort = false;
++			bool have_goodpkt = false;
++			static u8 frame_head[16];
++			static u8 frame_buf_ttl = 0;
++
++			ampdu_len =
++			    (struct esp_rx_ampdu_len *) (skb->data +
++							 hdr->len /
++							 sip->rx_blksz *
++							 sip->rx_blksz);
++			esp_sip_dbg(ESP_DBG_TRACE,
++				    "%s rx ampdu total len %u\n", __func__,
++				    hdr->len);
++			if (skb->data != (u8 *) hdr) {
++				printk("%p %p\n", skb->data, hdr);
++				show_buf(skb->data, 512);
++				show_buf((u8 *) hdr, 512);
++				ESSERT(0);
++				goto _exit;
++			}
++			mac_ctrl =
++			    sip_parse_normal_mac_ctrl(skb, NULL, NULL,
++						      &pulled_len);
++			memcpy(&new_mac_ctrl, mac_ctrl,
++			       sizeof(struct esp_mac_rx_ctrl));
++			mac_ctrl = &new_mac_ctrl;
++			pkt_num = mac_ctrl->ampdu_cnt;
++			esp_sip_dbg(ESP_DBG_TRACE,
++				    "%s %d rx ampdu %u pkts, %d pkts dumped, first len %u\n",
++				    __func__, __LINE__,
++				    (unsigned
++				     int) ((hdr->len % sip->rx_blksz) /
++					   sizeof(struct
++						  esp_rx_ampdu_len)),
++				    pkt_num,
++				    (unsigned int) ampdu_len->sublen);
++
++			pkt_total += mac_ctrl->ampdu_cnt;
++			//esp_sip_dbg(ESP_DBG_ERROR, "%s ampdu dropped %d/%d\n", __func__, pkt_dropped, pkt_total);
++			while (pkt_num > 0) {
++				esp_sip_dbg(ESP_DBG_TRACE,
++					    "%s %d ampdu sub state %02x,\n",
++					    __func__, __LINE__,
++					    ampdu_len->substate);
++
++				if (sip_ampdu_occupy_buf(sip, ampdu_len)) {	//pkt is dumped
++
++					rskb =
++					    sip_parse_data_rx_info(sip,
++								   skb,
++								   ampdu_len->
++								   sublen -
++								   FCS_LEN,
++								   0,
++								   mac_ctrl,
++								   &pulled_len);
++					if (!rskb) {
++						ESSERT(0);
++						goto _exit;
++					}
++
++					if (likely
++					    (atomic_read
++					     (&sip->epub->wl.off) == 0)
++					    && (ampdu_len->substate == 0
++						|| ampdu_len->substate ==
++						RX_TKIPMIC_ERR
++						|| (sip->sendup_rpbm_pkt
++						    && ampdu_len->
++						    substate ==
++						    RX_RPBM_ERR))
++					    && (sip->rxabort_fixed
++						|| !have_rxabort)) {
++						if (!have_goodpkt) {
++							have_goodpkt =
++							    true;
++							memcpy(frame_head,
++							       rskb->data,
++							       16);
++							frame_head[1] &=
++							    ~0x80;
++							frame_buf_ttl = 3;
++						}
++#ifdef RX_CHECKSUM_TEST
++						esp_rx_checksum_test(rskb);
++#endif
++						local_bh_disable();
++						ieee80211_rx(sip->epub->hw,
++							     rskb);
++						local_bh_enable();
++
++					} else {
++						kfree_skb(rskb);
++					}
++				} else {
++					if (ampdu_len->substate ==
++					    RX_ABORT) {
++						u8 *a;
++						have_rxabort = true;
++						esp_sip_dbg(ESP_DBG_TRACE,
++							    "rx abort %d %d\n",
++							    frame_buf_ttl,
++							    pkt_num);
++						if (frame_buf_ttl
++						    && !sip->
++						    rxabort_fixed) {
++							struct
++							    esp_rx_ampdu_len
++							    *next_good_ampdu_len
++							    =
++							    ampdu_len + 1;
++							a = frame_head;
++							esp_sip_dbg
++							    (ESP_DBG_TRACE,
++							     "frame:%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
++							     a[0], a[1],
++							     a[2], a[3],
++							     a[4], a[5],
++							     a[6], a[7],
++							     a[8], a[9],
++							     a[10], a[11],
++							     a[12], a[13],
++							     a[14], a[15]);
++							while
++							    (!sip_ampdu_occupy_buf
++							     (sip,
++							      next_good_ampdu_len))
++							{
++								if (next_good_ampdu_len > ampdu_len + pkt_num - 1)
++									break;
++								next_good_ampdu_len++;
++
++							}
++							if (next_good_ampdu_len <= ampdu_len + pkt_num - 1) {
++								bool b0,
++								    b10,
++								    b11;
++								a = skb->
++								    data;
++								esp_sip_dbg
++								    (ESP_DBG_TRACE,
++								     "buf:%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
++								     a[0],
++								     a[1],
++								     a[2],
++								     a[3],
++								     a[4],
++								     a[5],
++								     a[6],
++								     a[7],
++								     a[8],
++								     a[9],
++								     a[10],
++								     a[11],
++								     a[12],
++								     a[13],
++								     a[14],
++								     a
++								     [15]);
++								b0 = memcmp
++								    (frame_head
++								     + 4,
++								     skb->
++								     data +
++								     4,
++								     12) ==
++								    0;
++								b10 =
++								    memcmp
++								    (frame_head
++								     + 10,
++								     skb->
++								     data,
++								     6) ==
++								    0;
++								b11 =
++								    memcpy
++								    (frame_head
++								     + 11,
++								     skb->
++								     data,
++								     5) ==
++								    0;
++								esp_sip_dbg
++								    (ESP_DBG_TRACE,
++								     "com %d %d %d\n",
++								     b0,
++								     b10,
++								     b11);
++								if (b0
++								    && !b10
++								    &&
++								    !b11) {
++									have_rxabort
++									    =
++									    false;
++									esp_sip_dbg
++									    (ESP_DBG_TRACE,
++									     "repair 0\n");
++								} else
++								    if (!b0
++									&&
++									b10
++									&&
++									!b11)
++								{
++									skb_push
++									    (skb,
++									     10);
++									memcpy
++									    (skb->
++									     data,
++									     frame_head,
++									     10);
++									have_rxabort
++									    =
++									    false;
++									pulled_len
++									    -=
++									    10;
++									esp_sip_dbg
++									    (ESP_DBG_TRACE,
++									     "repair 10\n");
++								} else
++								    if (!b0
++									&&
++									!b10
++									&&
++									b11)
++								{
++									skb_push
++									    (skb,
++									     11);
++									memcpy
++									    (skb->
++									     data,
++									     frame_head,
++									     11);
++									have_rxabort
++									    =
++									    false;
++									pulled_len
++									    -=
++									    11;
++									esp_sip_dbg
++									    (ESP_DBG_TRACE,
++									     "repair 11\n");
++								}
++							}
++						}
++					}
++					pkt_dropped++;
++					esp_sip_dbg(ESP_DBG_LOG,
++						    "%s ampdu dropped %d/%d\n",
++						    __func__, pkt_dropped,
++						    pkt_total);
++				}
++				pkt_num--;
++				ampdu_len++;
++			}
++			if (frame_buf_ttl)
++				frame_buf_ttl--;
++			skb_pull(skb, hdr->len - pulled_len);
++		} else {
++			esp_sip_dbg(ESP_DBG_ERROR, "%s %d unknown type\n",
++				    __func__, __LINE__);
++		}
++
++	      _move_on:
++		if (hdr->len < remains_len) {
++			remains_len -= hdr->len;
++		} else {
++			break;
++		}
++		bufptr += hdr->len;
++	}
++
++      _exit:
++#ifdef ESP_PREALLOC
++	esp_put_sip_skb(&skb);
++#else
++	kfree_skb(skb);
++#endif
++
++	return trigger_rxq;
++
++#undef DO_NOT_COPY
++#undef DO_COPY
++}
++
++static void _sip_rxq_process(struct esp_sip *sip)
++{
++	struct sk_buff *skb = NULL;
++	bool sendup = false;
++
++	while ((skb = skb_dequeue(&sip->rxq))) {
++		if (sip_rx_pkt_process(sip, skb))
++			sendup = true;
++	}
++	if (sendup) {
++		queue_work(sip->epub->esp_wkq, &sip->epub->sendup_work);
++	}
++
++	/* probably tx_credit is updated, try txq */
++	sip_trigger_txq_process(sip);
++}
++
++static void sip_rxq_process(struct work_struct *work)
++{
++	struct esp_sip *sip =
++	    container_of(work, struct esp_sip, rx_process_work);
++	if (sip == NULL) {
++		ESSERT(0);
++		return;
++	}
++
++	if (unlikely(atomic_read(&sip->state) == SIP_SEND_INIT)) {
++		sip_send_chip_init(sip);
++		atomic_set(&sip->state, SIP_WAIT_BOOTUP);
++		return;
++	}
++
++	mutex_lock(&sip->rx_mtx);
++	_sip_rxq_process(sip);
++	mutex_unlock(&sip->rx_mtx);
++}
++
++static inline void sip_rx_pkt_enqueue(struct esp_sip *sip,
++				      struct sk_buff *skb)
++{
++	skb_queue_tail(&sip->rxq, skb);
++}
++
++static inline struct sk_buff *sip_rx_pkt_dequeue(struct esp_sip *sip)
++{
++	return skb_dequeue(&sip->rxq);
++}
++
++static u32 sip_rx_count = 0;
++void sip_debug_show(struct esp_sip *sip)
++{
++	esp_sip_dbg(ESP_DBG_ERROR, "txq left %d %d\n",
++		    skb_queue_len(&sip->epub->txq),
++		    atomic_read(&sip->tx_data_pkt_queued));
++	esp_sip_dbg(ESP_DBG_ERROR, "tx queues stop ? %d\n",
++		    atomic_read(&sip->epub->txq_stopped));
++	esp_sip_dbg(ESP_DBG_ERROR, "txq stop?  %d\n",
++		    test_bit(ESP_WL_FLAG_STOP_TXQ, &sip->epub->wl.flags));
++	esp_sip_dbg(ESP_DBG_ERROR, "tx credit %d\n",
++		    atomic_read(&sip->tx_credits));
++	esp_sip_dbg(ESP_DBG_ERROR, "rx collect %d\n", sip_rx_count);
++	sip_rx_count = 0;
++}
++
++int sip_rx(struct esp_pub *epub)
++{
++	struct sip_hdr *shdr = NULL;
++	struct esp_sip *sip = epub->sip;
++	int err = 0;
++	struct sk_buff *first_skb = NULL;
++	u8 *rx_buf = NULL;
++	u32 rx_blksz;
++	struct sk_buff *rx_skb = NULL;
++
++	u32 first_sz;
++
++	first_sz = sif_get_regs(epub)->config_w0;
++
++	if (likely(sif_get_ate_config() != 1)) {
++		do {
++			u8 raw_seq = sif_get_regs(epub)->intr_raw & 0xff;
++
++			if (raw_seq != sip->to_host_seq) {
++				if (raw_seq == sip->to_host_seq + 1) {	/* when last read pkt crc err, this situation may occur, but raw_seq mustn't < to_host_Seq */
++					sip->to_host_seq = raw_seq;
++					esp_dbg(ESP_DBG_TRACE,
++						"warn: to_host_seq reg 0x%02x, seq 0x%02x",
++						raw_seq, sip->to_host_seq);
++					break;
++				}
++				esp_dbg(ESP_DBG_ERROR,
++					"err: to_host_seq reg 0x%02x, seq 0x%02x",
++					raw_seq, sip->to_host_seq);
++				goto _err;
++			}
++		} while (0);
++	}
++	esp_sip_dbg(ESP_DBG_LOG, "%s enter\n", __func__);
++
++
++	/* first read one block out, if we luck enough, that's it
++	 *
++	 *  To make design as simple as possible, we allocate skb(s)
++	 *  separately for each sif read operation to avoid global
++	 *  read_buf_pointe access.  It coule be optimized late.
++	 */
++	rx_blksz = sif_get_blksz(epub);
++#ifdef ESP_PREALLOC
++	first_skb = esp_get_sip_skb(roundup(first_sz, rx_blksz));
++#else
++	first_skb =
++	    __dev_alloc_skb(roundup(first_sz, rx_blksz), GFP_KERNEL);
++#endif				/* ESP_PREALLOC */
++
++	if (first_skb == NULL) {
++		sif_unlock_bus(epub);
++		esp_sip_dbg(ESP_DBG_ERROR, "%s first no memory \n",
++			    __func__);
++		goto _err;
++	}
++
++	rx_buf = skb_put(first_skb, first_sz);
++	esp_sip_dbg(ESP_DBG_LOG, "%s rx_buf ptr %p, first_sz %d\n",
++		    __func__, rx_buf, first_sz);
++
++
++#ifdef USE_EXT_GPIO
++	do {
++		int err2 = 0;
++		u16 value = 0;
++		u16 intr_mask = ext_gpio_get_int_mask_reg();
++		if (!intr_mask)
++			break;
++		value = sif_get_regs(epub)->config_w3 & intr_mask;
++		if (value) {
++			err2 = sif_interrupt_target(epub, 6);
++			esp_sip_dbg(ESP_DBG, "write gpio\n");
++		}
++
++		if (!err2 && value) {
++			esp_sip_dbg(ESP_DBG_TRACE,
++				    "%s intr_mask[0x%04x] value[0x%04x]\n",
++				    __func__, intr_mask, value);
++			ext_gpio_int_process(value);
++		}
++	} while (0);
++#endif
++
++	err =
++	    esp_common_read(epub, rx_buf, first_sz, ESP_SIF_NOSYNC, false);
++	sip_rx_count++;
++	if (unlikely(err)) {
++		esp_dbg(ESP_DBG_ERROR, " %s first read err %d %d\n",
++			__func__, err, sif_get_regs(epub)->config_w0);
++#ifdef ESP_PREALLOC
++		esp_put_sip_skb(&first_skb);
++#else
++		kfree_skb(first_skb);
++#endif				/* ESP_PREALLOC */
++		sif_unlock_bus(epub);
++		goto _err;
++	}
++
++	shdr = (struct sip_hdr *) rx_buf;
++	if (SIP_HDR_IS_CTRL(shdr) && (shdr->c_evtid == SIP_EVT_SLEEP)) {
++		atomic_set(&sip->epub->ps.state, ESP_PM_ON);
++		esp_dbg(ESP_DBG_TRACE, "s\n");
++	}
++
++	if (likely(sif_get_ate_config() != 1)) {
++		sip->to_host_seq++;
++	}
++
++	if ((shdr->len & 3) != 0) {
++		esp_sip_dbg(ESP_DBG_ERROR, "%s shdr->len[%d] error\n",
++			    __func__, shdr->len);
++#ifdef ESP_PREALLOC
++		esp_put_sip_skb(&first_skb);
++#else
++		kfree_skb(first_skb);
++#endif				/* ESP_PREALLOC */
++		sif_unlock_bus(epub);
++		err = -EIO;
++		goto _err;
++	}
++	if (shdr->len != first_sz) {
++		esp_sip_dbg(ESP_DBG_ERROR,
++			    "%s shdr->len[%d]  first_size[%d] error\n",
++			    __func__, shdr->len, first_sz);
++#ifdef ESP_PREALLOC
++		esp_put_sip_skb(&first_skb);
++#else
++		kfree_skb(first_skb);
++#endif				/* ESP_PREALLOC */
++		sif_unlock_bus(epub);
++		err = -EIO;
++		goto _err;
++	} else {
++		sif_unlock_bus(epub);
++		skb_trim(first_skb, shdr->len);
++		esp_dbg(ESP_DBG_TRACE, " %s first_skb only\n", __func__);
++
++		rx_skb = first_skb;
++	}
++
++	if (atomic_read(&sip->state) == SIP_STOP) {
++#ifdef ESP_PREALLOC
++		esp_put_sip_skb(&rx_skb);
++#else
++		kfree_skb(rx_skb);
++#endif				/* ESP_PREALLOC */
++		esp_sip_dbg(ESP_DBG_ERROR, "%s when sip stopped\n",
++			    __func__);
++		return 0;
++	}
++
++	sip_rx_pkt_enqueue(sip, rx_skb);
++	queue_work(sip->epub->esp_wkq, &sip->rx_process_work);
++
++      _err:
++	return err;
++}
++
++int sip_post_init(struct esp_sip *sip, struct sip_evt_bootup2 *bevt)
++{
++	struct esp_pub *epub;
++
++	u8 mac_id = bevt->mac_addr[0];
++	int mac_index = 0;
++	int i = 0;
++
++	if (sip == NULL) {
++		ESSERT(0);
++		return -EINVAL;
++	}
++
++	epub = sip->epub;
++
++
++	sip->tx_aggr_write_ptr = sip->tx_aggr_buf;
++
++	sip->tx_blksz = bevt->tx_blksz;
++	sip->rx_blksz = bevt->rx_blksz;
++	sip->credit_to_reserve = bevt->credit_to_reserve;
++
++	sip->dump_rpbm_err = (bevt->options & SIP_DUMP_RPBM_ERR);
++	sip->rxabort_fixed = (bevt->options & SIP_RXABORT_FIXED);
++	sip->support_bgscan = (bevt->options & SIP_SUPPORT_BGSCAN);
++
++	sip->sendup_rpbm_pkt = sip->dump_rpbm_err && false;
++
++	/* print out MAC addr... */
++	memcpy(epub->mac_addr, bevt->mac_addr, ETH_ALEN);
++	for (i = 0;
++	     i <
++	     sizeof(esp_mac_prefix_table) / sizeof(struct esp_mac_prefix);
++	     i++) {
++		if (esp_mac_prefix_table[i].mac_index == mac_id) {
++			mac_index = i;
++			break;
++		}
++	}
++
++	epub->mac_addr[0] =
++	    esp_mac_prefix_table[mac_index].mac_addr_prefix[0];
++	epub->mac_addr[1] =
++	    esp_mac_prefix_table[mac_index].mac_addr_prefix[1];
++	epub->mac_addr[2] =
++	    esp_mac_prefix_table[mac_index].mac_addr_prefix[2];
++
++#ifdef SELF_MAC
++	epub->mac_addr[0] = 0xff;
++	epub->mac_addr[1] = 0xff;
++	epub->mac_addr[2] = 0xff;
++#endif
++	atomic_set(&sip->noise_floor, bevt->noise_floor);
++
++	sip_recalc_credit_init(sip);
++
++	esp_sip_dbg(ESP_DBG_TRACE,
++		    "%s tx_blksz %d rx_blksz %d mac addr %pM\n", __func__,
++		    sip->tx_blksz, sip->rx_blksz, epub->mac_addr);
++
++	return 0;
++}
++
++/* write pkts in aggr buf to target memory */
++static void sip_write_pkts(struct esp_sip *sip, int pm_state)
++{
++	int tx_aggr_len = 0;
++	struct sip_hdr *first_shdr = NULL;
++	int err = 0;
++
++	tx_aggr_len = sip->tx_aggr_write_ptr - sip->tx_aggr_buf;
++	if (tx_aggr_len < sizeof(struct sip_hdr)) {
++		printk("%s tx_aggr_len %d \n", __func__, tx_aggr_len);
++		ESSERT(0);
++		return;
++	}
++	if ((tx_aggr_len & 0x3) != 0) {
++		ESSERT(0);
++		return;
++	}
++
++	first_shdr = (struct sip_hdr *) sip->tx_aggr_buf;
++
++	if (atomic_read(&sip->tx_credits) <= SIP_CREDITS_LOW_THRESHOLD) {
++		first_shdr->fc[1] |= SIP_HDR_F_NEED_CRDT_RPT;
++	}
++
++	/* still use lock bus instead of sif_lldesc_write_sync since we want to protect several global varibles assignments */
++	sif_lock_bus(sip->epub);
++
++	err =
++	    esp_common_write(sip->epub, sip->tx_aggr_buf, tx_aggr_len,
++			     ESP_SIF_NOSYNC);
++
++	sip->tx_aggr_write_ptr = sip->tx_aggr_buf;
++	sip->tx_tot_len = 0;
++
++	sif_unlock_bus(sip->epub);
++
++	if (err)
++		esp_sip_dbg(ESP_DBG_ERROR, "func %s err!!!!!!!!!: %d\n",
++			    __func__, err);
++
++}
++
++/* setup sip header and tx info, copy pkt into aggr buf */
++static int sip_pack_pkt(struct esp_sip *sip, struct sk_buff *skb,
++			int *pm_state)
++{
++	struct ieee80211_tx_info *itx_info;
++	struct sip_hdr *shdr;
++	u32 tx_len = 0, offset = 0;
++	bool is_data = true;
++
++	itx_info = IEEE80211_SKB_CB(skb);
++
++	if (itx_info->flags == 0xffffffff) {
++		shdr = (struct sip_hdr *) skb->data;
++		is_data = false;
++		tx_len = skb->len;
++	} else {
++		struct ieee80211_hdr *wh =
++		    (struct ieee80211_hdr *) skb->data;
++		struct esp_vif *evif =
++		    (struct esp_vif *) itx_info->control.vif->drv_priv;
++		u8 sta_index;
++		struct esp_node *node;
++		/* update sip header */
++		shdr = (struct sip_hdr *) sip->tx_aggr_write_ptr;
++
++		shdr->fc[0] = 0;
++		shdr->fc[1] = 0;
++
++		if ((itx_info->flags & IEEE80211_TX_CTL_AMPDU)
++		    && (true || esp_is_ip_pkt(skb)))
++			SIP_HDR_SET_TYPE(shdr->fc[0], SIP_DATA_AMPDU);
++		else
++			SIP_HDR_SET_TYPE(shdr->fc[0], SIP_DATA);
++
++		if (evif->epub == NULL) {
++			sip_tx_status_report(sip, skb, itx_info, false);
++			atomic_dec(&sip->tx_data_pkt_queued);
++			return -EINVAL;
++		}
++
++		/* make room for encrypted pkt */
++		if (itx_info->control.hw_key) {
++			int alg =
++			    esp_cipher2alg(itx_info->control.hw_key->
++					   cipher);
++			if (unlikely(alg == -1)) {
++				sip_tx_status_report(sip, skb, itx_info,
++						     false);
++				atomic_dec(&sip->tx_data_pkt_queued);
++				return -1;
++			} else {
++				shdr->d_enc_flag = alg + 1;
++			}
++
++			shdr->d_hw_kid =
++			    itx_info->control.hw_key->hw_key_idx | (evif->
++								    index
++								    << 7);
++		} else {
++			shdr->d_enc_flag = 0;
++			shdr->d_hw_kid = (evif->index << 7 | evif->index);
++		}
++
++		/* update sip tx info */
++		node = esp_get_node_by_addr(sip->epub, wh->addr1);
++		if (node != NULL)
++			sta_index = node->index;
++		else
++			sta_index = ESP_PUB_MAX_STA + 1;
++		SIP_HDR_SET_IFIDX(shdr->fc[0],
++				  evif->index << 3 | sta_index);
++		shdr->d_p2p = itx_info->control.vif->p2p;
++		if (evif->index == 1)
++			shdr->d_p2p = 1;
++		shdr->d_ac = skb_get_queue_mapping(skb);
++		shdr->d_tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
++		wh = (struct ieee80211_hdr *) skb->data;
++		if (ieee80211_is_mgmt(wh->frame_control)) {
++			/* addba/delba/bar may use different tid/ac */
++			if (shdr->d_ac == WME_AC_VO) {
++				shdr->d_tid = 7;
++			}
++			if (ieee80211_is_beacon(wh->frame_control)) {
++				shdr->d_tid = 8;
++				shdr->d_ac = 4;
++			}
++		}
++		if (check_ac_tid(skb->data, shdr->d_ac, shdr->d_tid)) {
++			shdr->d_ac = WME_AC_BE;
++			shdr->d_tid = 0;
++		}
++
++
++		/* make sure data is start at 4 bytes aligned addr. */
++		offset = roundup(sizeof(struct sip_hdr), 4);
++
++#ifdef HOST_RC
++		esp_sip_dbg(ESP_DBG_TRACE, "%s offset0 %d \n", __func__,
++			    offset);
++		memcpy(sip->tx_aggr_write_ptr + offset,
++		       (void *) &itx_info->control,
++		       sizeof(struct sip_tx_rc));
++
++		offset += roundup(sizeof(struct sip_tx_rc), 4);
++		esp_show_tx_rates(&itx_info->control.rates[0]);
++
++#endif				/* HOST_RC */
++
++		if (SIP_HDR_IS_AMPDU(shdr)) {
++			memset(sip->tx_aggr_write_ptr + offset, 0,
++			       sizeof(struct esp_tx_ampdu_entry));
++			offset +=
++			    roundup(sizeof(struct esp_tx_ampdu_entry), 4);
++		}
++
++		tx_len = offset + skb->len;
++		shdr->len = tx_len;	/* actual len */
++
++		esp_sip_dbg(ESP_DBG_TRACE,
++			    "%s offset %d skblen %d txlen %d\n", __func__,
++			    offset, skb->len, tx_len);
++
++	}
++
++	shdr->seq = sip->txseq++;
++	//esp_sip_dbg(ESP_DBG_ERROR, "%s seq %u, %u %u\n", __func__, shdr->seq, SIP_HDR_GET_TYPE(shdr->fc[0]),shdr->c_cmdid);
++
++	/* copy skb to aggr buf */
++	memcpy(sip->tx_aggr_write_ptr + offset, skb->data, skb->len);
++
++	if (is_data) {
++		spin_lock_bh(&sip->epub->tx_lock);
++		sip->txdataseq = shdr->seq;
++		spin_unlock_bh(&sip->epub->tx_lock);
++		/* fake a tx_status and report to mac80211 stack to speed up tx, may affect
++		 *  1) rate control (now it's all in target, so should be OK)
++		 *  2) ps mode, mac80211 want to check ACK of ps/nulldata to see if AP is awake
++		 *  3) BAR, mac80211 do BAR by checking ACK
++		 */
++		/*
++		 *  XXX: need to adjust for 11n, e.g. report tx_status according to BA received in target
++		 *
++		 */
++		sip_tx_status_report(sip, skb, itx_info, true);
++		atomic_dec(&sip->tx_data_pkt_queued);
++
++		STRACE_TX_DATA_INC();
++	} else {
++		/* check pm state here */
++
++		/* no need to hold ctrl skb */
++		sip_free_ctrl_skbuff(sip, skb);
++		STRACE_TX_CMD_INC();
++	}
++
++	/* TBD: roundup here or whole aggr-buf */
++	tx_len = roundup(tx_len, sip->tx_blksz);
++
++	sip->tx_aggr_write_ptr += tx_len;
++	sip->tx_tot_len += tx_len;
++
++	return 0;
++}
++
++#ifdef HOST_RC
++static void sip_set_tx_rate_status(struct sip_rc_status *rcstatus,
++				   struct ieee80211_tx_rate *irates)
++{
++	int i;
++	u8 shift = 0;
++	u32 cnt = 0;
++
++	for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
++		if (rcstatus->rc_map & BIT(i)) {
++			shift = i << 2;
++			cnt =
++			    (rcstatus->
++			     rc_cnt_store >> shift) & RC_CNT_MASK;
++			irates[i].idx = i;
++			irates[i].count = (u8) cnt;
++		} else {
++			irates[i].idx = -1;
++			irates[i].count = 0;
++		}
++	}
++
++	esp_show_rcstatus(rcstatus);
++	esp_show_tx_rates(irates);
++}
++#endif				/* HOST_RC */
++
++static void sip_tx_status_report(struct esp_sip *sip, struct sk_buff *skb,
++				 struct ieee80211_tx_info *tx_info,
++				 bool success)
++{
++	if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
++		if (likely(success))
++			tx_info->flags |= IEEE80211_TX_STAT_ACK;
++		else
++			tx_info->flags &= ~IEEE80211_TX_STAT_ACK;
++
++		/* manipulate rate status... */
++		tx_info->status.rates[0].idx = 11;
++		tx_info->status.rates[0].count = 1;
++		tx_info->status.rates[0].flags = 0;
++		tx_info->status.rates[1].idx = -1;
++
++	} else {
++		tx_info->flags |=
++		    IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_STAT_ACK;
++		tx_info->status.ampdu_len = 1;
++		tx_info->status.ampdu_ack_len = 1;
++
++		/* manipulate rate status... */
++		tx_info->status.rates[0].idx = 7;
++		tx_info->status.rates[0].count = 1;
++		tx_info->status.rates[0].flags =
++		    IEEE80211_TX_RC_MCS | IEEE80211_TX_RC_SHORT_GI;
++		tx_info->status.rates[1].idx = -1;
++
++	}
++
++	if (tx_info->flags & IEEE80211_TX_STAT_AMPDU)
++		esp_sip_dbg(ESP_DBG_TRACE, "%s ampdu status! \n",
++			    __func__);
++
++	if (!mod_support_no_txampdu() &&
++	    cfg80211_get_chandef_type(&sip->epub->hw->conf.chandef) !=
++	    NL80211_CHAN_NO_HT) {
++		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++		struct ieee80211_hdr *wh =
++		    (struct ieee80211_hdr *) skb->data;
++		if (ieee80211_is_data_qos(wh->frame_control)) {
++			if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
++				u8 tidno =
++				    ieee80211_get_qos_ctl(wh)[0] &
++				    IEEE80211_QOS_CTL_TID_MASK;
++				struct esp_node *node;
++				struct esp_tx_tid *tid;
++				struct ieee80211_sta *sta;
++
++				node =
++				    esp_get_node_by_addr(sip->epub,
++							 wh->addr1);
++				if (node == NULL)
++					goto _exit;
++				if (node->sta == NULL)
++					goto _exit;
++				sta = node->sta;
++				tid = &node->tid[tidno];
++				spin_lock_bh(&sip->epub->tx_ampdu_lock);
++				//start session
++				if (tid == NULL) {
++					spin_unlock_bh(&sip->epub->
++						       tx_ampdu_lock);
++					ESSERT(0);
++					goto _exit;
++				}
++				if ((tid->state == ESP_TID_STATE_INIT) &&
++				    (TID_TO_AC(tidno) != WME_AC_VO)
++				    && tid->cnt >= 10) {
++					tid->state = ESP_TID_STATE_TRIGGER;
++					esp_sip_dbg(ESP_DBG_ERROR,
++						    "start tx ba session,addr:%pM,tid:%u\n",
++						    wh->addr1, tidno);
++					spin_unlock_bh(&sip->epub->
++						       tx_ampdu_lock);
++					ieee80211_start_tx_ba_session(sta,
++								      tidno,
++								      0);
++				} else {
++					if (tid->state ==
++					    ESP_TID_STATE_INIT)
++						tid->cnt++;
++					else
++						tid->cnt = 0;
++					spin_unlock_bh(&sip->epub->
++						       tx_ampdu_lock);
++				}
++			}
++		}
++	}
++      _exit:
++	ieee80211_tx_status_skb(sip->epub->hw, skb);
++}
++
++/*
++ *  NB: this routine should be locked when calling
++ */
++void sip_txq_process(struct esp_pub *epub)
++{
++	struct sk_buff *skb;
++	struct esp_sip *sip = epub->sip;
++	u32 pkt_len = 0, tx_len = 0;
++	int blknum = 0;
++	bool queued_back = false;
++	bool out_of_credits = false;
++	struct ieee80211_tx_info *itx_info;
++	int pm_state = 0;
++
++	while ((skb = skb_dequeue(&epub->txq))) {
++
++		/* cmd skb->len does not include sip_hdr too */
++		pkt_len = skb->len;
++		itx_info = IEEE80211_SKB_CB(skb);
++		if (itx_info->flags != 0xffffffff) {
++			pkt_len += roundup(sizeof(struct sip_hdr), 4);
++			if ((itx_info->flags & IEEE80211_TX_CTL_AMPDU)
++			    && (true || esp_is_ip_pkt(skb)))
++				pkt_len +=
++				    roundup(sizeof
++					    (struct esp_tx_ampdu_entry),
++					    4);
++		}
++
++		/* current design simply requires every sip_hdr must be at the begin of mblk, that definitely
++		 * need to be optimized, e.g. calulate remain length in the previous mblk, if it larger than
++		 * certain threshold (e.g, whole pkt or > 50% of pkt or 2 x sizeof(struct sip_hdr), append pkt
++		 * to the previous mblk.  This might be done in sip_pack_pkt()
++		 */
++		pkt_len = roundup(pkt_len, sip->tx_blksz);
++		blknum = pkt_len / sip->tx_blksz;
++		esp_dbg(ESP_DBG_TRACE,
++			"%s skb_len %d pkt_len %d blknum %d\n", __func__,
++			skb->len, pkt_len, blknum);
++
++		if (unlikely(atomic_read(&sip->credit_status) == RECALC_CREDIT_ENABLE)) {	/* need recalc credit */
++			struct sip_hdr *hdr = (struct sip_hdr *) skb->data;
++			itx_info = IEEE80211_SKB_CB(skb);
++			if (!(itx_info->flags == 0xffffffff && SIP_HDR_GET_TYPE(hdr->fc[0]) == SIP_CTRL && hdr->c_cmdid == SIP_CMD_RECALC_CREDIT && blknum <= atomic_read(&sip->tx_credits) - sip->credit_to_reserve)) {	/* except cmd recalc credit */
++				esp_dbg(ESP_DBG_ERROR,
++					"%s recalc credits!\n", __func__);
++				STRACE_TX_OUT_OF_CREDIT_INC();
++				queued_back = true;
++				out_of_credits = true;
++				break;
++			}
++		} else {	/* normal situation */
++			if (unlikely
++			    (blknum >
++			     (atomic_read(&sip->tx_credits) -
++			      sip->credit_to_reserve -
++			      SIP_CTRL_CREDIT_RESERVE))) {
++				itx_info = IEEE80211_SKB_CB(skb);
++				if (itx_info->flags == 0xffffffff) {	/* priv ctrl pkt */
++					if (blknum >
++					    atomic_read(&sip->tx_credits) -
++					    sip->credit_to_reserve) {
++						esp_dbg(ESP_DBG_TRACE,
++							"%s cmd pkt out of credits!\n",
++							__func__);
++						STRACE_TX_OUT_OF_CREDIT_INC
++						    ();
++						queued_back = true;
++						out_of_credits = true;
++						break;
++					}
++				} else {
++					esp_dbg(ESP_DBG_TRACE,
++						"%s out of credits!\n",
++						__func__);
++					STRACE_TX_OUT_OF_CREDIT_INC();
++					queued_back = true;
++					out_of_credits = true;
++					break;
++				}
++			}
++		}
++		tx_len += pkt_len;
++		if (tx_len >= SIP_TX_AGGR_BUF_SIZE) {
++			/* do we need to have limitation likemax 8 pkts in a row? */
++			esp_dbg(ESP_DBG_TRACE,
++				"%s too much pkts in one shot!\n",
++				__func__);
++			STRACE_TX_ONE_SHOT_INC();
++			tx_len -= pkt_len;
++			queued_back = true;
++			break;
++		}
++
++		if (sip_pack_pkt(sip, skb, &pm_state) != 0) {
++			/* wrong pkt, won't send to target */
++			tx_len -= pkt_len;
++			continue;
++		}
++
++		esp_sip_dbg(ESP_DBG_TRACE,
++			    "%s:before sub, credits is %d\n", __func__,
++			    atomic_read(&sip->tx_credits));
++		atomic_sub(blknum, &sip->tx_credits);
++		esp_sip_dbg(ESP_DBG_TRACE,
++			    "%s:after sub %d,credits remains %d\n",
++			    __func__, blknum,
++			    atomic_read(&sip->tx_credits));
++
++	}
++
++	if (queued_back) {
++		skb_queue_head(&epub->txq, skb);
++	}
++
++	if (atomic_read(&sip->state) == SIP_STOP
++#ifdef HOST_RESET_BUG
++	    || atomic_read(&epub->wl.off) == 1
++#endif
++	    ) {
++		queued_back = 1;
++		tx_len = 0;
++		sip_after_write_pkts(sip);
++	}
++
++	if (tx_len) {
++
++		sip_write_pkts(sip, pm_state);
++
++		sip_after_write_pkts(sip);
++	}
++
++	if (queued_back && !out_of_credits) {
++
++		/* skb pending, do async process again */
++		sip_trigger_txq_process(sip);
++	}
++}
++
++static void sip_after_write_pkts(struct esp_sip *sip)
++{
++
++}
++
++#ifndef NO_WMM_DUMMY
++static struct esp_80211_wmm_param_element esp_wmm_param = {
++	.oui = {0x00, 0x50, 0xf2},
++	.oui_type = 0x02,
++	.oui_subtype = 0x01,
++	.version = 0x01,
++	.qos_info = 0x00,
++	.reserved = 0x00,
++	.ac = {
++	       {
++		.aci_aifsn = 0x03,
++		.cw = 0xa4,
++		.txop_limit = 0x0000,
++		},
++	       {
++		.aci_aifsn = 0x27,
++		.cw = 0xa4,
++		.txop_limit = 0x0000,
++		},
++	       {
++		.aci_aifsn = 0x42,
++		.cw = 0x43,
++		.txop_limit = 0x005e,
++		},
++	       {
++		.aci_aifsn = 0x62,
++		.cw = 0x32,
++		.txop_limit = 0x002f,
++		},
++	       },
++};
++
++static int esp_add_wmm(struct sk_buff *skb)
++{
++	u8 *p;
++	int flag = 0;
++	int remain_len;
++	int base_len;
++	int len;
++	struct ieee80211_mgmt *mgmt;
++	struct ieee80211_hdr *wh;
++
++	if (!skb)
++		return -1;
++
++	wh = (struct ieee80211_hdr *) skb->data;
++	mgmt = (struct ieee80211_mgmt *) ((u8 *) skb->data);
++
++	if (ieee80211_is_assoc_resp(wh->frame_control)) {
++		p = mgmt->u.assoc_resp.variable;
++		base_len =
++		    (u8 *) mgmt->u.assoc_resp.variable - (u8 *) mgmt;
++	} else if (ieee80211_is_reassoc_resp(wh->frame_control)) {
++		p = mgmt->u.reassoc_resp.variable;
++		base_len =
++		    (u8 *) mgmt->u.reassoc_resp.variable - (u8 *) mgmt;
++	} else if (ieee80211_is_probe_resp(wh->frame_control)) {
++		p = mgmt->u.probe_resp.variable;
++		base_len =
++		    (u8 *) mgmt->u.probe_resp.variable - (u8 *) mgmt;
++	} else if (ieee80211_is_beacon(wh->frame_control)) {
++		p = mgmt->u.beacon.variable;
++		base_len = (u8 *) mgmt->u.beacon.variable - (u8 *) mgmt;
++	} else
++		return 1;
++
++
++	remain_len = skb->len - base_len;
++
++	while (remain_len > 0) {
++		if (*p == 0xdd && *(p + 5) == 0x02)	//wmm type
++			return 0;
++		else if (*p == 0x2d)	//has ht cap
++			flag = 1;
++
++		len = *(++p);
++		p += (len + 1);
++		remain_len -= (len + 2);
++	}
++
++	if (remain_len < 0) {
++		esp_dbg(ESP_DBG_TRACE,
++			"%s remain_len %d, skb->len %d, base_len %d, flag %d",
++			__func__, remain_len, skb->len, base_len, flag);
++		return -2;
++	}
++
++	if (flag == 1) {
++		skb_put(skb, 2 + sizeof(esp_wmm_param));
++
++		memset(p, 0xdd, sizeof(u8));
++		memset(p + 1, sizeof(esp_wmm_param), sizeof(u8));
++		memcpy(p + 2, &esp_wmm_param, sizeof(esp_wmm_param));
++
++		esp_dbg(ESP_DBG_TRACE, "esp_wmm_param");
++	}
++
++	return 0;
++}
++#endif				/* NO_WMM_DUMMY */
++
++/*  parse mac_rx_ctrl and return length */
++static int sip_parse_mac_rx_info(struct esp_sip *sip,
++				 struct esp_mac_rx_ctrl *mac_ctrl,
++				 struct sk_buff *skb)
++{
++	struct ieee80211_rx_status *rx_status = NULL;
++	struct ieee80211_hdr *hdr;
++
++	rx_status = IEEE80211_SKB_RXCB(skb);
++	rx_status->freq = esp_ieee2mhz(mac_ctrl->channel);
++
++	rx_status->signal = mac_ctrl->rssi + mac_ctrl->noise_floor;	/* snr actually, need to offset noise floor e.g. -85 */
++
++	hdr = (struct ieee80211_hdr *) skb->data;
++	if (mac_ctrl->damatch0 == 1 && mac_ctrl->bssidmatch0 == 1	/*match bssid and da, but beacon package contain other bssid */
++	    && strncmp(hdr->addr2, sip->epub->wl.bssid, ETH_ALEN) == 0) {	/* force match addr2 */
++		if (++signal_loop >= SIGNAL_COUNT) {
++			avg_signal += rx_status->signal;
++			avg_signal /= SIGNAL_COUNT;
++			old_signal = rx_status->signal = (avg_signal + 5);
++			signal_loop = 0;
++			avg_signal = 0;
++		} else {
++			avg_signal += rx_status->signal;
++			rx_status->signal = old_signal;
++		}
++	}
++
++	rx_status->antenna = 0;	/* one antenna for now */
++	rx_status->band = NL80211_BAND_2GHZ;
++	rx_status->flag = RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
++	if (mac_ctrl->sig_mode) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++		rx_status->encoding = RX_ENC_HT;
++#else
++		rx_status->flag |= RX_FLAG_HT;
++#endif
++		rx_status->rate_idx = mac_ctrl->MCS;
++		if (mac_ctrl->SGI)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
++#else
++			rx_status->flag |= RX_FLAG_SHORT_GI;
++#endif
++	} else {
++		rx_status->rate_idx = esp_wmac_rate2idx(mac_ctrl->rate);
++	}
++	if (mac_ctrl->rxend_state == RX_FCS_ERR)
++		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
++
++	/* Mic error frame flag */
++	if (mac_ctrl->rxend_state == RX_TKIPMIC_ERR
++	    || mac_ctrl->rxend_state == RX_CCMPMIC_ERR) {
++		if (atomic_read(&sip->epub->wl.tkip_key_set) == 1) {
++			rx_status->flag |= RX_FLAG_MMIC_ERROR;
++			atomic_set(&sip->epub->wl.tkip_key_set, 0);
++			printk("mic err\n");
++		} else {
++			printk("mic err discard\n");
++		}
++	}
++	//esp_dbg(ESP_DBG_LOG, "%s freq: %u; signal: %d;  rate_idx %d; flag: %d \n", __func__, rx_status->freq, rx_status->signal, rx_status->rate_idx, rx_status->flag);
++
++	do {
++		struct ieee80211_hdr *wh =
++		    (struct ieee80211_hdr *) ((u8 *) skb->data);
++
++#ifndef NO_WMM_DUMMY
++		if (ieee80211_is_mgmt(wh->frame_control))
++			esp_add_wmm(skb);
++#endif
++
++		/* some kernel e.g. 3.0.8 wrongly handles non-encrypted pkt like eapol */
++		if (ieee80211_is_data(wh->frame_control)) {
++			if (!ieee80211_has_protected(wh->frame_control)) {
++				esp_sip_dbg(ESP_DBG_TRACE,
++					    "%s kiv_war, add iv_stripped flag \n",
++					    __func__);
++				rx_status->flag |= RX_FLAG_IV_STRIPPED;
++			} else {
++				if ((atomic_read(&sip->epub->wl.ptk_cnt) ==
++				     0 && !(wh->addr1[0] & 0x1))
++				    || (atomic_read(&sip->epub->wl.gtk_cnt)
++					== 0 && (wh->addr1[0] & 0x1))) {
++					esp_dbg(ESP_DBG_TRACE,
++						"%s ==kiv_war, got bogus enc pkt==\n",
++						__func__);
++					rx_status->flag |=
++					    RX_FLAG_IV_STRIPPED;
++					//show_buf(skb->data, 32);
++				}
++
++				esp_sip_dbg(ESP_DBG_TRACE,
++					    "%s kiv_war, got enc pkt \n",
++					    __func__);
++			}
++		}
++	} while (0);
++
++	return 0;
++}
++
++static struct esp_mac_rx_ctrl *sip_parse_normal_mac_ctrl(struct sk_buff
++							 *skb,
++							 int *pkt_len_enc,
++							 int *buf_len,
++							 int *pulled_len)
++{
++	struct esp_mac_rx_ctrl *mac_ctrl = NULL;
++	struct sip_hdr *hdr = (struct sip_hdr *) skb->data;
++	int len_in_hdr = hdr->len;
++
++	ESSERT(skb != NULL);
++	ESSERT(skb->len > SIP_MIN_DATA_PKT_LEN);
++
++	skb_pull(skb, sizeof(struct sip_hdr));
++	*pulled_len += sizeof(struct sip_hdr);
++	mac_ctrl = (struct esp_mac_rx_ctrl *) skb->data;
++	if (!mac_ctrl->Aggregation) {
++		ESSERT(pkt_len_enc != NULL);
++		ESSERT(buf_len != NULL);
++		*pkt_len_enc =
++		    (mac_ctrl->sig_mode ? mac_ctrl->HT_length : mac_ctrl->
++		     legacy_length) - FCS_LEN;
++		*buf_len =
++		    len_in_hdr - sizeof(struct sip_hdr) -
++		    sizeof(struct esp_mac_rx_ctrl);
++	}
++	skb_pull(skb, sizeof(struct esp_mac_rx_ctrl));
++	*pulled_len += sizeof(struct esp_mac_rx_ctrl);
++
++	return mac_ctrl;
++}
++
++/*
++ * for one MPDU (including subframe in AMPDU)
++ *
++ */
++static struct sk_buff *sip_parse_data_rx_info(struct esp_sip *sip,
++					      struct sk_buff *skb,
++					      int pkt_len_enc, int buf_len,
++					      struct esp_mac_rx_ctrl
++					      *mac_ctrl, int *pulled_len)
++{
++	/*
++	 *   | mac_rx_ctrl | real_data_payload | ampdu_entries |
++	 */
++	//without enc
++	int pkt_len = 0;
++	struct sk_buff *rskb = NULL;
++	int ret;
++
++	if (mac_ctrl->Aggregation) {
++		struct ieee80211_hdr *wh =
++		    (struct ieee80211_hdr *) skb->data;
++		pkt_len = pkt_len_enc;
++		if (ieee80211_has_protected(wh->frame_control))	//ampdu, it is CCMP enc
++			pkt_len -= 8;
++		buf_len = roundup(pkt_len, 4);
++	} else
++		pkt_len = buf_len - 3 + ((pkt_len_enc - 1) & 0x3);
++	esp_dbg(ESP_DBG_TRACE,
++		"%s pkt_len %u, pkt_len_enc %u!, delta %d \n", __func__,
++		pkt_len, pkt_len_enc, pkt_len_enc - pkt_len);
++	do {
++#ifndef NO_WMM_DUMMY
++		rskb =
++		    __dev_alloc_skb(pkt_len_enc + sizeof(esp_wmm_param) +
++				    2, GFP_ATOMIC);
++#else
++		rskb = __dev_alloc_skb(pkt_len_enc, GFP_ATOMIC);
++#endif				/* NO_WMM_DUMMY */
++		if (unlikely(rskb == NULL)) {
++			esp_sip_dbg(ESP_DBG_ERROR, "%s no mem for rskb\n",
++				    __func__);
++			return NULL;
++		}
++		skb_put(rskb, pkt_len_enc);
++	} while (0);
++
++	do {
++		memcpy(rskb->data, skb->data, pkt_len);
++		if (pkt_len_enc > pkt_len) {
++			memset(rskb->data + pkt_len, 0,
++			       pkt_len_enc - pkt_len);
++		}
++		/* strip out current pkt, move to the next one */
++		skb_pull(skb, buf_len);
++		*pulled_len += buf_len;
++	} while (0);
++
++	ret = sip_parse_mac_rx_info(sip, mac_ctrl, rskb);
++	if (ret == -1 && !mac_ctrl->Aggregation) {
++		kfree_skb(rskb);
++		return NULL;
++	}
++
++	esp_dbg(ESP_DBG_LOG,
++		"%s after pull headers, skb->len %d rskb->len %d \n",
++		__func__, skb->len, rskb->len);
++
++	return rskb;
++}
++
++struct esp_sip *sip_attach(struct esp_pub *epub)
++{
++	struct esp_sip *sip = NULL;
++	struct sip_pkt *pkt = NULL;
++	int i;
++#ifndef ESP_PREALLOC
++	int po = 0;
++#endif
++
++	sip = kzalloc(sizeof(struct esp_sip), GFP_KERNEL);
++	if (sip == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "no mem for sip! \n");
++		goto _err_sip;
++	}
++#ifdef ESP_PREALLOC
++	sip->tx_aggr_buf = (u8 *) esp_get_tx_aggr_buf();
++#else
++	po = get_order(SIP_TX_AGGR_BUF_SIZE);
++	sip->tx_aggr_buf = (u8 *) __get_free_pages(GFP_ATOMIC, po);
++#endif
++	if (sip->tx_aggr_buf == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "no mem for tx_aggr_buf! \n");
++		goto _err_aggr;
++	}
++
++	spin_lock_init(&sip->lock);
++
++	INIT_LIST_HEAD(&sip->free_ctrl_txbuf);
++	INIT_LIST_HEAD(&sip->free_ctrl_rxbuf);
++
++	for (i = 0; i < SIP_CTRL_BUF_N; i++) {
++		pkt = kzalloc(sizeof(struct sip_pkt), GFP_KERNEL);
++
++		if (!pkt)
++			goto _err_pkt;
++
++		pkt->buf_begin = kzalloc(SIP_CTRL_BUF_SZ, GFP_KERNEL);
++
++		if (pkt->buf_begin == NULL) {
++			kfree(pkt);
++			pkt = NULL;
++			goto _err_pkt;
++		}
++
++		pkt->buf_len = SIP_CTRL_BUF_SZ;
++		pkt->buf = pkt->buf_begin;
++
++		if (i < SIP_CTRL_TXBUF_N) {
++			list_add_tail(&pkt->list, &sip->free_ctrl_txbuf);
++		} else {
++			list_add_tail(&pkt->list, &sip->free_ctrl_rxbuf);
++		}
++	}
++
++	mutex_init(&sip->rx_mtx);
++	skb_queue_head_init(&sip->rxq);
++	INIT_WORK(&sip->rx_process_work, sip_rxq_process);
++
++	sip->epub = epub;
++	atomic_set(&sip->noise_floor, -96);
++
++	atomic_set(&sip->state, SIP_INIT);
++	atomic_set(&sip->tx_credits, 0);
++
++	if (sip->rawbuf == NULL) {
++		sip->rawbuf = kzalloc(SIP_BOOT_BUF_SIZE, GFP_KERNEL);
++		if (sip->rawbuf == NULL) {
++			esp_dbg(ESP_DBG_ERROR, "no mem for rawbuf! \n");
++			goto _err_pkt;
++		}
++	}
++
++	atomic_set(&sip->state, SIP_PREPARE_BOOT);
++
++	return sip;
++
++      _err_pkt:
++	sip_free_init_ctrl_buf(sip);
++
++	if (sip->tx_aggr_buf) {
++#ifdef ESP_PREALLOC
++		esp_put_tx_aggr_buf(&sip->tx_aggr_buf);
++#else
++		po = get_order(SIP_TX_AGGR_BUF_SIZE);
++		free_pages((unsigned long) sip->tx_aggr_buf, po);
++		sip->tx_aggr_buf = NULL;
++#endif
++	}
++      _err_aggr:
++	if (sip) {
++		kfree(sip);
++		sip = NULL;
++	}
++      _err_sip:
++	return NULL;
++
++}
++
++static void sip_free_init_ctrl_buf(struct esp_sip *sip)
++{
++	struct sip_pkt *pkt, *tpkt;
++
++	list_for_each_entry_safe(pkt, tpkt, &sip->free_ctrl_txbuf, list) {
++		list_del(&pkt->list);
++		kfree(pkt->buf_begin);
++		kfree(pkt);
++	}
++
++	list_for_each_entry_safe(pkt, tpkt, &sip->free_ctrl_rxbuf, list) {
++		list_del(&pkt->list);
++		kfree(pkt->buf_begin);
++		kfree(pkt);
++	}
++}
++
++void sip_detach(struct esp_sip *sip)
++{
++#ifndef ESP_PREALLOC
++	int po;
++#endif
++	if (sip == NULL)
++		return;
++
++	esp_dbg(ESP_DBG_TRACE, "sip_detach: sip_free_init_ctrl_buf()");
++	sip_free_init_ctrl_buf(sip);
++
++	if (atomic_read(&sip->state) == SIP_RUN) {
++
++		sif_disable_target_interrupt(sip->epub);
++
++		atomic_set(&sip->state, SIP_STOP);
++
++		/* disable irq here */
++		sif_disable_irq(sip->epub);
++		cancel_work_sync(&sip->rx_process_work);
++
++		skb_queue_purge(&sip->rxq);
++		mutex_destroy(&sip->rx_mtx);
++		cancel_work(&sip->epub->sendup_work); // Must be non-sync
++		skb_queue_purge(&sip->epub->rxq);
++
++#ifdef ESP_NO_MAC80211
++		unregister_netdev(sip->epub->net_dev);
++		wiphy_unregister(sip->epub->wdev->wiphy);
++#else
++		if (test_and_clear_bit
++		    (ESP_WL_FLAG_HW_REGISTERED, &sip->epub->wl.flags)) {
++			ieee80211_unregister_hw(sip->epub->hw);
++		}
++#endif
++
++		/* cancel all worker/timer */
++		cancel_work_sync(&sip->epub->tx_work);
++		skb_queue_purge(&sip->epub->txq);
++		skb_queue_purge(&sip->epub->txdoneq);
++
++#ifdef ESP_PREALLOC
++		esp_put_tx_aggr_buf(&sip->tx_aggr_buf);
++#else
++		po = get_order(SIP_TX_AGGR_BUF_SIZE);
++		free_pages((unsigned long) sip->tx_aggr_buf, po);
++		sip->tx_aggr_buf = NULL;
++#endif
++
++		atomic_set(&sip->state, SIP_INIT);
++	} else if (atomic_read(&sip->state) >= SIP_BOOT
++		   && atomic_read(&sip->state) <= SIP_WAIT_BOOTUP) {
++
++		sif_disable_target_interrupt(sip->epub);
++		atomic_set(&sip->state, SIP_STOP);
++
++		sif_disable_irq(sip->epub);
++
++		if (sip->rawbuf)
++			kfree(sip->rawbuf);
++
++		if (atomic_read(&sip->state) == SIP_SEND_INIT) {
++			cancel_work_sync(&sip->rx_process_work);
++			skb_queue_purge(&sip->rxq);
++			mutex_destroy(&sip->rx_mtx);
++			cancel_work_sync(&sip->epub->sendup_work);
++			skb_queue_purge(&sip->epub->rxq);
++		}
++#ifdef ESP_NO_MAC80211
++		unregister_netdev(sip->epub->net_dev);
++		wiphy_unregister(sip->epub->wdev->wiphy);
++#else
++		if (test_and_clear_bit
++		    (ESP_WL_FLAG_HW_REGISTERED, &sip->epub->wl.flags)) {
++			ieee80211_unregister_hw(sip->epub->hw);
++		}
++#endif
++		atomic_set(&sip->state, SIP_INIT);
++	} else
++		esp_dbg(ESP_DBG_ERROR, "%s wrong state %d\n", __func__,
++			atomic_read(&sip->state));
++
++	kfree(sip);
++}
++
++int sip_write_memory(struct esp_sip *sip, u32 addr, u8 * buf, u16 len)
++{
++	struct sip_cmd_write_memory *cmd;
++	struct sip_hdr *chdr;
++	u16 remains, hdrs, bufsize;
++	u32 loadaddr;
++	u8 *src;
++	int err = 0;
++	u32 *t = NULL;
++
++	if (sip == NULL || sip->rawbuf == NULL) {
++		ESSERT(sip != NULL);
++		ESSERT(sip->rawbuf != NULL);
++		return -EINVAL;
++	}
++
++	memset(sip->rawbuf, 0, SIP_BOOT_BUF_SIZE);
++
++	chdr = (struct sip_hdr *) sip->rawbuf;
++	SIP_HDR_SET_TYPE(chdr->fc[0], SIP_CTRL);
++	chdr->c_cmdid = SIP_CMD_WRITE_MEMORY;
++
++	remains = len;
++	hdrs =
++	    sizeof(struct sip_hdr) + sizeof(struct sip_cmd_write_memory);
++
++	while (remains) {
++		src = &buf[len - remains];
++		loadaddr = addr + (len - remains);
++
++		if (remains < (SIP_BOOT_BUF_SIZE - hdrs)) {
++			/* aligned with 4 bytes */
++			bufsize = roundup(remains, 4);
++			memset(sip->rawbuf + hdrs, 0, bufsize);
++			remains = 0;
++		} else {
++			bufsize = SIP_BOOT_BUF_SIZE - hdrs;
++			remains -= bufsize;
++		}
++
++		chdr->len = bufsize + hdrs;
++		chdr->seq = sip->txseq++;
++		cmd =
++		    (struct sip_cmd_write_memory *) (sip->rawbuf +
++						     SIP_CTRL_HDR_LEN);
++		cmd->len = bufsize;
++		cmd->addr = loadaddr;
++		memcpy(sip->rawbuf + hdrs, src, bufsize);
++
++		t = (u32 *) sip->rawbuf;
++		esp_dbg(ESP_DBG_TRACE,
++			"%s t0: 0x%08x t1: 0x%08x t2:0x%08x loadaddr 0x%08x \n",
++			__func__, t[0], t[1], t[2], loadaddr);
++
++		err =
++		    esp_common_write(sip->epub, sip->rawbuf, chdr->len,
++				     ESP_SIF_SYNC);
++
++		if (err) {
++			esp_dbg(ESP_DBG_ERROR, "%s send buffer failed\n",
++				__func__);
++			return err;
++		}
++		// 1ms is enough, in fact on dell-d430, need not delay at all.
++		mdelay(1);
++
++	}
++
++	return err;
++}
++
++int sip_send_cmd(struct esp_sip *sip, int cid, u32 cmdlen, void *cmd)
++{
++	struct sip_hdr *chdr;
++	struct sip_pkt *pkt = NULL;
++	int ret = 0;
++
++	pkt = sip_get_ctrl_buf(sip, SIP_TX_CTRL_BUF);
++
++	if (pkt == NULL)
++		return -ENOMEM;
++
++	chdr = (struct sip_hdr *) pkt->buf_begin;
++	chdr->len = SIP_CTRL_HDR_LEN + cmdlen;
++	chdr->seq = sip->txseq++;
++	chdr->c_cmdid = cid;
++
++
++	if (cmd) {
++		memset(pkt->buf, 0, cmdlen);
++		memcpy(pkt->buf, (u8 *) cmd, cmdlen);
++	}
++
++	esp_dbg(ESP_DBG_TRACE, "cid %d, len %u, seq %u \n", chdr->c_cmdid,
++		chdr->len, chdr->seq);
++
++	esp_dbg(ESP_DBG_TRACE, "c1 0x%08x   c2 0x%08x\n",
++		*(u32 *) & pkt->buf[0], *(u32 *) & pkt->buf[4]);
++
++	ret =
++	    esp_common_write(sip->epub, pkt->buf_begin, chdr->len,
++			     ESP_SIF_SYNC);
++
++	if (ret)
++		esp_dbg(ESP_DBG_ERROR, "%s send cmd %d failed \n",
++			__func__, cid);
++
++	sip_reclaim_ctrl_buf(sip, pkt, SIP_TX_CTRL_BUF);
++
++	/*
++	 *  Hack here: reset tx/rx seq before target ram code is up...
++	 */
++	if (cid == SIP_CMD_BOOTUP) {
++		sip->rxseq = 0;
++		sip->txseq = 0;
++		sip->txdataseq = 0;
++	}
++
++	return ret;
++}
++
++struct sk_buff *sip_alloc_ctrl_skbuf(struct esp_sip *sip, u16 len, u32 cid)
++{
++	struct sip_hdr *si = NULL;
++	struct ieee80211_tx_info *ti = NULL;
++	struct sk_buff *skb = NULL;
++
++	ESSERT(len <= sip->tx_blksz);
++
++	/* no need to reserve space for net stack */
++	skb = __dev_alloc_skb(len, GFP_KERNEL);
++
++	if (skb == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "no skb for ctrl !\n");
++		return NULL;
++	}
++
++	skb->len = len;
++
++	ti = IEEE80211_SKB_CB(skb);
++	/* set tx_info flags to 0xffffffff to indicate sip_ctrl pkt */
++	ti->flags = 0xffffffff;
++	si = (struct sip_hdr *) skb->data;
++	memset(si, 0, sizeof(struct sip_hdr));
++	SIP_HDR_SET_TYPE(si->fc[0], SIP_CTRL);
++	si->len = len;
++	si->c_cmdid = cid;
++
++	return skb;
++}
++
++void sip_free_ctrl_skbuff(struct esp_sip *sip, struct sk_buff *skb)
++{
++	memset(IEEE80211_SKB_CB(skb), 0, sizeof(struct ieee80211_tx_info));
++	kfree_skb(skb);
++}
++
++static struct sip_pkt *sip_get_ctrl_buf(struct esp_sip *sip,
++					SIP_BUF_TYPE bftype)
++{
++	struct sip_pkt *pkt = NULL;
++	struct list_head *bflist;
++	struct sip_hdr *chdr;
++
++	bflist =
++	    (bftype ==
++	     SIP_TX_CTRL_BUF) ? &sip->free_ctrl_txbuf : &sip->
++	    free_ctrl_rxbuf;
++
++	spin_lock_bh(&sip->lock);
++
++	if (list_empty(bflist)) {
++		spin_unlock_bh(&sip->lock);
++		return NULL;
++	}
++
++	pkt = list_first_entry(bflist, struct sip_pkt, list);
++	list_del(&pkt->list);
++	spin_unlock_bh(&sip->lock);
++
++	if (bftype == SIP_TX_CTRL_BUF) {
++		chdr = (struct sip_hdr *) pkt->buf_begin;
++		SIP_HDR_SET_TYPE(chdr->fc[0], SIP_CTRL);
++		pkt->buf = pkt->buf_begin + SIP_CTRL_HDR_LEN;
++	} else {
++		pkt->buf = pkt->buf_begin;
++	}
++
++	return pkt;
++}
++
++static void
++sip_reclaim_ctrl_buf(struct esp_sip *sip, struct sip_pkt *pkt,
++		     SIP_BUF_TYPE bftype)
++{
++	struct list_head *bflist = NULL;
++
++	if (bftype == SIP_TX_CTRL_BUF)
++		bflist = &sip->free_ctrl_txbuf;
++	else if (bftype == SIP_RX_CTRL_BUF)
++		bflist = &sip->free_ctrl_rxbuf;
++	else
++		return;
++
++	pkt->buf = pkt->buf_begin;
++
++	spin_lock_bh(&sip->lock);
++	list_add_tail(&pkt->list, bflist);
++	spin_unlock_bh(&sip->lock);
++}
++
++int sip_poll_bootup_event(struct esp_sip *sip)
++{
++	int ret = 0;
++
++	esp_dbg(ESP_DBG_TRACE, "polling bootup event... \n");
++
++	if (gl_bootup_cplx)
++		ret = wait_for_completion_timeout(gl_bootup_cplx, 2 * HZ);
++
++	esp_dbg(ESP_DBG_TRACE, "******time remain****** = [%d]\n", ret);
++	if (ret <= 0) {
++		esp_dbg(ESP_DBG_ERROR, "bootup event timeout\n");
++		return -ETIMEDOUT;
++	}
++
++	if (sif_get_ate_config() == 0) {
++		ret = esp_register_mac80211(sip->epub);
++	}
++#ifdef TEST_MODE
++	ret = test_init_netlink(sip);
++	if (ret < 0) {
++		esp_sip_dbg(ESP_DBG_TRACE,
++			    "esp_sdio: failed initializing netlink\n");
++		return ret;
++	}
++#endif
++
++	atomic_set(&sip->state, SIP_RUN);
++	esp_dbg(ESP_DBG_TRACE, "target booted up\n");
++
++	return ret;
++}
++
++int sip_poll_resetting_event(struct esp_sip *sip)
++{
++	int ret = 0;
++
++	esp_dbg(ESP_DBG_TRACE, "polling resetting event... \n");
++
++	if (gl_bootup_cplx)
++		ret = wait_for_completion_timeout(gl_bootup_cplx, 10 * HZ);
++
++	esp_dbg(ESP_DBG_TRACE, "******time remain****** = [%d]\n", ret);
++	if (ret <= 0) {
++		esp_dbg(ESP_DBG_ERROR, "resetting event timeout\n");
++		return -ETIMEDOUT;
++	}
++
++	esp_dbg(ESP_DBG_TRACE, "target resetting %d %p\n", ret,
++		gl_bootup_cplx);
++
++	return 0;
++}
++
++
++#ifdef FPGA_DEBUG
++
++/* bogus bootup cmd for FPGA debugging */
++int sip_send_bootup(struct esp_sip *sip)
++{
++	int ret;
++	struct sip_cmd_bootup bootcmd;
++
++	esp_dbg(ESP_DBG_LOG, "sending bootup\n");
++
++	bootcmd.boot_addr = 0;
++	ret =
++	    sip_send_cmd(sip, SIP_CMD_BOOTUP,
++			 sizeof(struct sip_cmd_bootup), &bootcmd);
++
++	return ret;
++}
++
++#endif				/* FPGA_DEBUG */
++
++bool sip_queue_need_stop(struct esp_sip * sip)
++{
++	return atomic_read(&sip->tx_data_pkt_queued) >=
++	    SIP_STOP_QUEUE_THRESHOLD || (atomic_read(&sip->tx_credits) < 8
++					 && atomic_read(&sip->
++							tx_data_pkt_queued)
++					 >=
++					 SIP_STOP_QUEUE_THRESHOLD / 4 * 3);
++}
++
++bool sip_queue_may_resume(struct esp_sip * sip)
++{
++	return atomic_read(&sip->epub->txq_stopped)
++	    && !test_bit(ESP_WL_FLAG_STOP_TXQ, &sip->epub->wl.flags)
++	    && ((atomic_read(&sip->tx_credits) >= 16
++		 && atomic_read(&sip->tx_data_pkt_queued) <
++		 SIP_RESUME_QUEUE_THRESHOLD * 2)
++		|| atomic_read(&sip->tx_data_pkt_queued) <
++		SIP_RESUME_QUEUE_THRESHOLD);
++}
++
++int sip_cmd_enqueue(struct esp_sip *sip, struct sk_buff *skb, int prior)
++{
++	if (!sip || !sip->epub) {
++		esp_dbg(ESP_DBG_ERROR, "func %s, sip->epub->txq is NULL\n",
++			__func__);
++		return -EINVAL;
++	}
++
++	if (!skb) {
++		esp_dbg(ESP_DBG_ERROR, "func %s, skb is NULL\n", __func__);
++		return -EINVAL;
++	}
++
++	if (prior == ENQUEUE_PRIOR_HEAD)
++		skb_queue_head(&sip->epub->txq, skb);
++	else
++		skb_queue_tail(&sip->epub->txq, skb);
++
++	if (sif_get_ate_config() == 0) {
++		ieee80211_queue_work(sip->epub->hw, &sip->epub->tx_work);
++	} else {
++		queue_work(sip->epub->esp_wkq, &sip->epub->tx_work);
++	}
++	return 0;
++}
++
++void sip_tx_data_pkt_enqueue(struct esp_pub *epub, struct sk_buff *skb)
++{
++	if (!epub || !epub->sip) {
++		if (!epub)
++			esp_dbg(ESP_DBG_ERROR, "func %s, epub is NULL\n",
++				__func__);
++		else
++			esp_dbg(ESP_DBG_ERROR,
++				"func %s, epub->sip is NULL\n", __func__);
++
++		return;
++	}
++	if (!skb) {
++		esp_dbg(ESP_DBG_ERROR, "func %s, skb is NULL\n", __func__);
++		return;
++	}
++	skb_queue_tail(&epub->txq, skb);
++	atomic_inc(&epub->sip->tx_data_pkt_queued);
++	if (sip_queue_need_stop(epub->sip)) {
++		if (epub->hw) {
++			ieee80211_stop_queues(epub->hw);
++			atomic_set(&epub->txq_stopped, true);
++		}
++
++	}
++}
++
++#ifdef FPGA_TXDATA
++int sip_send_tx_data(struct esp_sip *sip)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_bss_info_update *bsscmd;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_bss_info_update),
++				 SIP_CMD_BSS_INFO_UPDATE);
++	if (!skb)
++		return -EINVAL;
++
++	bsscmd =
++	    (struct sip_cmd_bss_info_update *) (skb->data +
++						sizeof(struct
++						       sip_tx_info));
++	bsscmd->isassoc = (assoc == true) ? 1 : 0;
++	memcpy(bsscmd->bssid, bssid, ETH_ALEN);
++	STRACE_SHOW(epub->sip);
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++#endif				/* FPGA_TXDATA */
+diff --git a/drivers/net/wireless/esp8089/esp_sip.h b/drivers/net/wireless/esp8089/esp_sip.h
+new file mode 100644
+index 000000000000..95cc42989b2c
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_sip.h
+@@ -0,0 +1,171 @@
++/*
++ *  Copyright (c) 2009- 2014 Espressif System.
++ *
++ *    Serial Interconnctor Protocol
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_SIP_H
++#define _ESP_SIP_H
++
++#include "sip2_common.h"
++
++#define SIP_CTRL_CREDIT_RESERVE      2
++
++#define SIP_PKT_MAX_LEN (1024*16)
++
++/* 16KB on normal X86 system, should check before porting to orhters */
++
++#define SIP_TX_AGGR_BUF_SIZE (4 * PAGE_SIZE)
++#define SIP_RX_AGGR_BUF_SIZE (4 * PAGE_SIZE)
++
++struct sk_buff;
++
++struct sip_pkt {
++	struct list_head list;
++
++	u8 *buf_begin;
++	u32 buf_len;
++	u8 *buf;
++};
++
++typedef enum RECALC_CREDIT_STATE {
++	RECALC_CREDIT_DISABLE = 0,
++	RECALC_CREDIT_ENABLE = 1,
++} RECALC_CREDIT_STATE;
++
++typedef enum ENQUEUE_PRIOR {
++	ENQUEUE_PRIOR_TAIL = 0,
++	ENQUEUE_PRIOR_HEAD,
++} ENQUEUE_PRIOR;
++
++typedef enum SIP_STATE {
++	SIP_INIT = 0,
++	SIP_PREPARE_BOOT,
++	SIP_BOOT,
++	SIP_SEND_INIT,
++	SIP_WAIT_BOOTUP,
++	SIP_RUN,
++	SIP_SUSPEND,
++	SIP_STOP
++} SIP_STATE;
++
++enum sip_notifier {
++	SIP_TX_DONE = 1,
++	SIP_RX_DONE = 2,
++};
++
++#define SIP_CREDITS_LOW_THRESHOLD  64	//i.e. 4k
++
++struct esp_sip {
++	struct list_head free_ctrl_txbuf;
++	struct list_head free_ctrl_rxbuf;
++
++	u32 rxseq;		/* sip pkt seq, should match target side */
++	u32 txseq;
++	u32 txdataseq;
++
++	u8 to_host_seq;
++
++	atomic_t state;
++	spinlock_t lock;
++	atomic_t tx_credits;
++
++	atomic_t tx_ask_credit_update;
++
++	u8 *rawbuf;		/* used in boot stage, free once chip is fully up */
++	u8 *tx_aggr_buf;
++	u8 *tx_aggr_write_ptr;	/* update after insertion of each pkt */
++	u8 *tx_aggr_lastpkt_ptr;
++
++	struct mutex rx_mtx;
++	struct sk_buff_head rxq;
++	struct work_struct rx_process_work;
++
++	u16 tx_blksz;
++	u16 rx_blksz;
++
++	bool dump_rpbm_err;
++	bool sendup_rpbm_pkt;
++	bool rxabort_fixed;
++	bool support_bgscan;
++	u8 credit_to_reserve;
++
++	atomic_t credit_status;
++	struct timer_list credit_timer;
++
++	atomic_t noise_floor;
++
++	u32 tx_tot_len;		/* total len for one transaction */
++	u32 rx_tot_len;
++
++	atomic_t rx_handling;
++	atomic_t tx_data_pkt_queued;
++
++	atomic_t data_tx_stopped;
++	atomic_t tx_stopped;
++
++	struct esp_pub *epub;
++};
++
++int sip_rx(struct esp_pub *epub);
++//int sip_download_fw(struct esp_sip *sip, u32 load_addr, u32 boot_addr);
++
++
++int sip_write_memory(struct esp_sip *, u32 addr, u8 * buf, u16 len);
++
++void sip_credit_process(struct esp_pub *, u8 credits);
++
++int sip_send_cmd(struct esp_sip *sip, int cid, u32 cmdlen, void *cmd);
++
++struct esp_sip *sip_attach(struct esp_pub *);
++
++int sip_post_init(struct esp_sip *sip, struct sip_evt_bootup2 *bevt);
++
++void sip_detach(struct esp_sip *sip);
++
++void sip_txq_process(struct esp_pub *epub);
++
++struct sk_buff *sip_alloc_ctrl_skbuf(struct esp_sip *sip, u16 len,
++				     u32 cid);
++
++void sip_free_ctrl_skbuff(struct esp_sip *sip, struct sk_buff *skb);
++
++bool sip_queue_need_stop(struct esp_sip *sip);
++bool sip_queue_may_resume(struct esp_sip *sip);
++bool sip_tx_data_need_stop(struct esp_sip *sip);
++bool sip_tx_data_may_resume(struct esp_sip *sip);
++
++void sip_tx_data_pkt_enqueue(struct esp_pub *epub, struct sk_buff *skb);
++void sip_rx_data_pkt_enqueue(struct esp_pub *epub, struct sk_buff *skb);
++
++int sip_cmd_enqueue(struct esp_sip *sip, struct sk_buff *skb, int prior);
++
++int sip_poll_bootup_event(struct esp_sip *sip);
++
++int sip_poll_resetting_event(struct esp_sip *sip);
++
++void sip_trigger_txq_process(struct esp_sip *sip);
++
++void sip_send_chip_init(struct esp_sip *sip);
++
++bool mod_support_no_txampdu(void);
++
++bool mod_support_no_rxampdu(void);
++
++void mod_support_no_txampdu_set(bool value);
++
++#ifdef FPGA_DEBUG
++int sip_send_bootup(struct esp_sip *sip);
++#endif				/* FPGA_DEBUG */
++void sip_debug_show(struct esp_sip *sip);
++#endif
+diff --git a/drivers/net/wireless/esp8089/esp_utils.c b/drivers/net/wireless/esp8089/esp_utils.c
+new file mode 100644
+index 000000000000..8b188de79b2c
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_utils.c
+@@ -0,0 +1,262 @@
++/*
++ * Copyright (c) 2009 - 2014 Espressif System.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include "linux/types.h"
++#include "linux/kernel.h"
++#include <linux/ieee80211.h>
++#include <net/mac80211.h>
++#include <linux/skbuff.h>
++
++#include <net/tcp.h>
++#include <linux/ip.h>
++#include <asm/checksum.h>
++
++#include "esp_pub.h"
++#include "esp_utils.h"
++#include "esp_wmac.h"
++#include "esp_debug.h"
++
++/*
++ * Convert IEEE channel number to MHz frequency.
++ */
++u32 esp_ieee2mhz(u8 chan)
++{
++	if (chan == 14)
++		return 2484;
++
++	if (chan < 14)
++		return 2407 + chan * 5;
++	else
++		return 2512 + ((chan - 15) * 20);
++	//TODO, add 5GHz
++}
++
++enum {
++	ESP_RATE_1_LONG = 0x0,
++	ESP_RATE_2_LONG = 0x1,
++	ESP_RATE_2_SHORT = 0x5,
++	ESP_RATE_5_SHORT = 0x6,
++	ESP_RATE_5_LONG = 0x2,
++	ESP_RATE_11_SHORT = 0x7,
++	ESP_RATE_11_LONG = 0x3,
++	ESP_RATE_6 = 0xb,
++	ESP_RATE_9 = 0xf,
++	ESP_RATE_12 = 0xa,
++	ESP_RATE_18 = 0xe,
++	ESP_RATE_24 = 0x9,
++	ESP_RATE_36 = 0xd,
++	ESP_RATE_48 = 0x8,
++	ESP_RATE_54 = 0xc,
++	/*        ESP_RATE_MCS0 =0x10,
++	   ESP_RATE_MCS1 =0x11,
++	   ESP_RATE_MCS2 =0x12,
++	   ESP_RATE_MCS3 =0x13,
++	   ESP_RATE_MCS4 =0x14,
++	   ESP_RATE_MCS5 =0x15,
++	   ESP_RATE_MCS6 =0x16,
++	   ESP_RATE_MCS7 =0x17,
++	 */
++};
++
++static u8 esp_rate_table[20] = {
++	ESP_RATE_1_LONG,
++	ESP_RATE_2_SHORT,
++	ESP_RATE_5_SHORT,
++	ESP_RATE_11_SHORT,
++	ESP_RATE_6,
++	ESP_RATE_9,
++	ESP_RATE_12,
++	ESP_RATE_18,
++	ESP_RATE_24,
++	ESP_RATE_36,
++	ESP_RATE_48,
++	ESP_RATE_54,
++	/*      ESP_RATE_MCS0,
++	   ESP_RATE_MCS1,
++	   ESP_RATE_MCS2,
++	   ESP_RATE_MCS3,
++	   ESP_RATE_MCS4,
++	   ESP_RATE_MCS5,
++	   ESP_RATE_MCS6,
++	   ESP_RATE_MCS7,
++	 */
++};
++
++s8 esp_wmac_rate2idx(u8 rate)
++{
++	int i;
++
++	if (rate == ESP_RATE_2_LONG)
++		return 1;
++	if (rate == ESP_RATE_5_LONG)
++		return 2;
++	if (rate == ESP_RATE_11_LONG)
++		return 3;
++
++	for (i = 0; i < 20; i++) {
++		if (rate == esp_rate_table[i])
++			return i;
++	}
++
++	esp_dbg(ESP_DBG_ERROR, "%s unknown rate 0x%02x \n", __func__,
++		rate);
++
++	return 0;
++}
++
++bool esp_wmac_rxsec_error(u8 error)
++{
++	return (error >= RX_SECOV_ERR && error <= RX_SECFIFO_TIMEOUT)
++	    || (error >= RX_WEPICV_ERR && error <= RX_WAPIMIC_ERR);
++}
++
++int esp_cipher2alg(int cipher)
++{
++	if (cipher == WLAN_CIPHER_SUITE_TKIP)
++		return ALG_TKIP;
++
++	if (cipher == WLAN_CIPHER_SUITE_CCMP)
++		return ALG_CCMP;
++
++	if (cipher == WLAN_CIPHER_SUITE_WEP40
++	    || cipher == WLAN_CIPHER_SUITE_WEP104)
++		return ALG_WEP;
++
++	if (cipher == WLAN_CIPHER_SUITE_AES_CMAC)
++		return ALG_AES_CMAC;
++
++	//printk("%s wrong cipher 0x%x!\n",__func__,cipher);
++
++	return -1;
++}
++
++#ifdef RX_CHECKSUM_TEST
++atomic_t g_iv_len;
++void esp_rx_checksum_test(struct sk_buff *skb)
++{
++	static u32 ip_err = 0;
++	static u32 tcp_err = 0;
++	struct ieee80211_hdr *pwh = (struct ieee80211_hdr *) skb->data;
++	int hdrlen = ieee80211_hdrlen(pwh->frame_control);
++
++	if (ieee80211_has_protected(pwh->frame_control))
++		hdrlen += atomic_read(&g_iv_len);
++
++	if (ieee80211_is_data(pwh->frame_control)) {
++		struct llc_snap_hdr *llc =
++		    (struct llc_snap_hdr *) (skb->data + hdrlen);
++		if (ntohs(llc->eth_type) == ETH_P_IP) {
++			int llclen = sizeof(struct llc_snap_hdr);
++			struct iphdr *iph =
++			    (struct iphdr *) (skb->data + hdrlen + llclen);
++			__sum16 csum_bak = iph->check;
++
++			iph->check = 0;
++			iph->check = ip_fast_csum(iph, iph->ihl);
++			if (iph->check != csum_bak) {
++				esp_dbg(ESP_DBG_ERROR,
++					"total ip checksum error %d\n",
++					++ip_err);
++			}
++			iph->check = csum_bak;
++
++			if (iph->protocol == 0x06) {
++				struct tcphdr *tcph =
++				    (struct tcphdr *) (skb->data + hdrlen +
++						       llclen +
++						       iph->ihl * 4);
++				int datalen =
++				    skb->len - (hdrlen + llclen +
++						iph->ihl * 4);
++				csum_bak = tcph->check;
++
++				tcph->check = 0;
++				tcph->check =
++				    tcp_v4_check(datalen, iph->saddr,
++						 iph->daddr,
++						 csum_partial((char *)
++							      tcph,
++							      datalen, 0));
++				if (tcph->check != csum_bak) {
++					esp_dbg(ESP_DBG_ERROR,
++						"total tcp checksum error %d\n",
++						++tcp_err);
++				}
++				tcph->check = csum_bak;
++			}
++		}
++	}
++}
++
++#endif
++
++#ifdef GEN_ERR_CHECKSUM
++
++void esp_gen_err_checksum(struct sk_buff *skb)
++{
++	static u32 tx_seq = 0;
++	if ((tx_seq++ % 16) == 0) {
++		struct ieee80211_hdr *hdr =
++		    (struct ieee80211_hdr *) skb->data;
++		int hdrlen = ieee80211_hdrlen(hdr->frame_control);
++
++		if (ieee80211_has_protected(pwh->frame_control))
++			hdrlen +=
++			    IEEE80211_SKB_CB(skb)->control.hw_key->iv_len;
++
++		struct llc_snap_hdr *llc =
++		    (struct llc_snap_hdr *) (skb->data + hdrlen);
++		if (ntohs(llc->eth_type) == ETH_P_IP) {
++			int llclen = sizeof(struct llc_snap_hdr);
++			struct iphdr *iph =
++			    (struct iphdr *) (skb->data + hdrlen + llclen);
++
++			iph->check = ~iph->check;
++
++			if (iph->protocol == 0x06) {
++				struct tcphdr *tcph =
++				    (struct tcphdr *) (skb->data + hdrlen +
++						       llclen +
++						       iph->ihl * 4);
++				tcph->check = ~tcph->check;
++			}
++		}
++	}
++}
++#endif
++
++bool esp_is_ip_pkt(struct sk_buff *skb)
++{
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
++	int hdrlen;
++	struct llc_snap_hdr *llc;
++
++	if (!ieee80211_is_data(hdr->frame_control))
++		return false;
++
++	hdrlen = ieee80211_hdrlen(hdr->frame_control);
++	if (ieee80211_has_protected(hdr->frame_control))
++		hdrlen += IEEE80211_SKB_CB(skb)->control.hw_key->iv_len;
++#ifdef RX_CHECKSUM_TEST
++	atomic_set(&g_iv_len,
++		   IEEE80211_SKB_CB(skb)->control.hw_key->iv_len);
++#endif
++	if (skb->len < hdrlen + sizeof(struct llc_snap_hdr))
++		return false;
++	llc = (struct llc_snap_hdr *) (skb->data + hdrlen);
++	if (ntohs(llc->eth_type) != ETH_P_IP)
++		return false;
++	else
++		return true;
++}
+diff --git a/drivers/net/wireless/esp8089/esp_utils.h b/drivers/net/wireless/esp8089/esp_utils.h
+new file mode 100644
+index 000000000000..ed16d9ca0a65
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_utils.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright (c) 2011-2012 Espressif System.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_UTILS_H_
++#define _ESP_UTILS_H_
++
++#include "linux/types.h"
++#include <linux/version.h>
++
++#ifndef BIT
++#define BIT(x) (0x1 << (x))
++#endif
++
++u32 esp_ieee2mhz(u8 chan);
++
++enum ieee80211_key_alg {
++	ALG_WEP,
++	ALG_TKIP,
++	ALG_CCMP,
++	ALG_AES_CMAC
++};
++
++int esp_cipher2alg(int cipher);
++
++void esp_rx_checksum_test(struct sk_buff *skb);
++void esp_gen_err_checksum(struct sk_buff *skb);
++
++bool esp_is_ip_pkt(struct sk_buff *skb);
++
++#endif
+diff --git a/drivers/net/wireless/esp8089/esp_version.h b/drivers/net/wireless/esp8089/esp_version.h
+new file mode 100644
+index 000000000000..481d98841fc2
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_version.h
+@@ -0,0 +1 @@
++#define DRIVER_VER 0xbdf5087c3debll
+diff --git a/drivers/net/wireless/esp8089/esp_wl.h b/drivers/net/wireless/esp8089/esp_wl.h
+new file mode 100644
+index 000000000000..e3e62a83d505
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_wl.h
+@@ -0,0 +1,63 @@
++#ifndef _ESP_WL_H_
++#define _ESP_WL_H_
++
++//#define MAX_PROBED_SSID_INDEX 9
++
++
++enum {
++	CONF_HW_BIT_RATE_1MBPS = BIT(0),
++	CONF_HW_BIT_RATE_2MBPS = BIT(1),
++	CONF_HW_BIT_RATE_5_5MBPS = BIT(2),
++	CONF_HW_BIT_RATE_11MBPS = BIT(3),
++	CONF_HW_BIT_RATE_6MBPS = BIT(4),
++	CONF_HW_BIT_RATE_9MBPS = BIT(5),
++	CONF_HW_BIT_RATE_12MBPS = BIT(6),
++	CONF_HW_BIT_RATE_18MBPS = BIT(7),
++	CONF_HW_BIT_RATE_22MBPS = BIT(8),
++	CONF_HW_BIT_RATE_24MBPS = BIT(9),
++	CONF_HW_BIT_RATE_36MBPS = BIT(10),
++	CONF_HW_BIT_RATE_48MBPS = BIT(11),
++	CONF_HW_BIT_RATE_54MBPS = BIT(12),
++	CONF_HW_BIT_RATE_11B_MASK =
++	    (CONF_HW_BIT_RATE_1MBPS | CONF_HW_BIT_RATE_2MBPS |
++	     CONF_HW_BIT_RATE_5_5MBPS | CONF_HW_BIT_RATE_11MBPS),
++};
++
++#if 0
++enum {
++	CONF_HW_RATE_INDEX_1MBPS = 0,
++	CONF_HW_RATE_INDEX_2MBPS = 1,
++	CONF_HW_RATE_INDEX_5_5MBPS = 2,
++	CONF_HW_RATE_INDEX_6MBPS = 3,
++	CONF_HW_RATE_INDEX_9MBPS = 4,
++	CONF_HW_RATE_INDEX_11MBPS = 5,
++	CONF_HW_RATE_INDEX_12MBPS = 6,
++	CONF_HW_RATE_INDEX_18MBPS = 7,
++	CONF_HW_RATE_INDEX_22MBPS = 8,
++	CONF_HW_RATE_INDEX_24MBPS = 9,
++	CONF_HW_RATE_INDEX_36MBPS = 10,
++	CONF_HW_RATE_INDEX_48MBPS = 11,
++	CONF_HW_RATE_INDEX_54MBPS = 12,
++	CONF_HW_RATE_INDEX_MAX,
++};
++
++enum {
++	CONF_HW_RXTX_RATE_54 = 0,
++	CONF_HW_RXTX_RATE_48,
++	CONF_HW_RXTX_RATE_36,
++	CONF_HW_RXTX_RATE_24,
++	CONF_HW_RXTX_RATE_22,
++	CONF_HW_RXTX_RATE_18,
++	CONF_HW_RXTX_RATE_12,
++	CONF_HW_RXTX_RATE_11,
++	CONF_HW_RXTX_RATE_9,
++	CONF_HW_RXTX_RATE_6,
++	CONF_HW_RXTX_RATE_5_5,
++	CONF_HW_RXTX_RATE_2,
++	CONF_HW_RXTX_RATE_1,
++	CONF_HW_RXTX_RATE_MAX,
++	CONF_HW_RXTX_RATE_UNSUPPORTED = 0xff
++};
++#endif
++
++#endif				/* _ESP_WL_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_wmac.h b/drivers/net/wireless/esp8089/esp_wmac.h
+new file mode 100644
+index 000000000000..72d13cbfc0e5
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_wmac.h
+@@ -0,0 +1,92 @@
++/*
++ * Copyright (c) 2011-2012 Espressif System.
++ *
++ *   MAC header
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_WMAC_H_
++#define _ESP_WMAC_H_
++
++struct esp_mac_rx_ctrl {
++	signed rssi:8;
++	unsigned rate:4;
++	unsigned is_group:1;
++	unsigned:1;
++	unsigned sig_mode:2;
++	unsigned legacy_length:12;
++	unsigned damatch0:1;
++	unsigned damatch1:1;
++	unsigned bssidmatch0:1;
++	unsigned bssidmatch1:1;
++	unsigned MCS:7;
++	unsigned CWB:1;
++	unsigned HT_length:16;
++	unsigned Smoothing:1;
++	unsigned Not_Sounding:1;
++	unsigned:1;
++	unsigned Aggregation:1;
++	unsigned STBC:2;
++	unsigned FEC_CODING:1;
++	unsigned SGI:1;
++	unsigned rxend_state:8;
++	unsigned ampdu_cnt:8;
++	unsigned channel:4;
++	unsigned:4;
++	signed noise_floor:8;
++};
++
++struct esp_rx_ampdu_len {
++	unsigned substate:8;
++	unsigned sublen:12;
++	unsigned:12;
++};
++
++struct esp_tx_ampdu_entry {
++	u32 sub_len:12, dili_num:7,:1, null_byte:2, data:1, enc:1, seq:8;
++};
++
++//rxend_state flags
++#define RX_PYH_ERR_MIN 0x42
++#define RX_AGC_ERR_MIN 0x42
++#define RX_AGC_ERR_MAX 0x47
++#define RX_OFDM_ERR_MIN 0x50
++#define RX_OFDM_ERR_MAX 0x58
++#define RX_CCK_ERR_MIN 0x59
++#define RX_CCK_ERR_MAX 0x5F
++#define RX_ABORT 0x80
++#define RX_SF_ERR 0x40
++#define RX_FCS_ERR 0x41
++#define RX_AHBOV_ERR 0xC0
++#define RX_BUFOV_ERR 0xC1
++#define RX_BUFINV_ERR 0xC2
++#define RX_AMPDUSF_ERR 0xC3
++#define RX_AMPDUBUFOV_ERR 0xC4
++#define RX_MACBBFIFOOV_ERR 0xC5
++#define RX_RPBM_ERR 0xC6
++#define RX_BTFORCE_ERR 0xC7
++#define RX_SECOV_ERR 0xE1
++#define RX_SECPROT_ERR0 0xE2
++#define RX_SECPROT_ERR1 0xE3
++#define RX_SECKEY_ERR 0xE4
++#define RX_SECCRLEN_ERR 0xE5
++#define RX_SECFIFO_TIMEOUT 0xE6
++#define RX_WEPICV_ERR 0xF0
++#define RX_TKIPICV_ERR 0xF4
++#define RX_TKIPMIC_ERR 0xF5
++#define RX_CCMPMIC_ERR 0xF8
++#define RX_WAPIMIC_ERR 0xFC
++
++s8 esp_wmac_rate2idx(u8 rate);
++bool esp_wmac_rxsec_error(u8 error);
++
++#endif				/* _ESP_WMAC_H_ */
+diff --git a/drivers/net/wireless/esp8089/firmware/LICENSE-2.0.txt b/drivers/net/wireless/esp8089/firmware/LICENSE-2.0.txt
+new file mode 100644
+index 000000000000..0dd35c82a001
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/firmware/LICENSE-2.0.txt
+@@ -0,0 +1,203 @@
++The esp8089 firmware files are licensed under the Apache License, Version 2.0:
++
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++                           Version 2.0, January 2004
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+diff --git a/drivers/net/wireless/esp8089/sdio_sif_esp.c b/drivers/net/wireless/esp8089/sdio_sif_esp.c
+new file mode 100644
+index 000000000000..2bd2c63f5388
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/sdio_sif_esp.c
+@@ -0,0 +1,824 @@
++/*
++ * Copyright (c) 2010 -2013 Espressif System.
++ *
++ *   sdio serial i/f driver
++ *    - sdio device control routines
++ *    - sync/async DMA/PIO read/write
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#include <linux/mmc/card.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/core.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sd.h>
++#include <linux/module.h>
++#include <net/mac80211.h>
++#include <linux/time.h>
++#include <linux/pm.h>
++#include <linux/delay.h>
++
++#include "esp_pub.h"
++#include "esp_sif.h"
++#include "esp_sip.h"
++#include "esp_debug.h"
++#include "slc_host_register.h"
++#include "esp_version.h"
++#include "esp_ctrl.h"
++#include "esp_file.h"
++#ifdef USE_EXT_GPIO
++#include "esp_ext.h"
++#endif				/* USE_EXT_GPIO */
++
++#define MANUFACTURER_ID_EAGLE_BASE        0x1110
++#define MANUFACTURER_ID_EAGLE_BASE_MASK     0xFF00
++#define MANUFACTURER_CODE                  0x6666
++
++static const struct sdio_device_id esp_sdio_devices[] = {
++	{SDIO_DEVICE
++	 (MANUFACTURER_CODE, (MANUFACTURER_ID_EAGLE_BASE | 0x1))},
++	{},
++};
++
++static const struct of_device_id esp_of_match_table[] = {
++        { .compatible = "esp,esp8089", .data = NULL},
++        { }
++};
++
++static int /*__init*/ esp_sdio_init(void);
++static void /*__exit*/ esp_sdio_exit(void);
++
++
++#define ESP_DMA_IBUFSZ   2048
++
++//unsigned int esp_msg_level = 0;
++unsigned int esp_msg_level = ESP_DBG_ERROR | ESP_SHOW;
++
++struct esp_sdio_ctrl *sif_sctrl = NULL;
++
++#ifdef ESP_ANDROID_LOGGER
++bool log_off = false;
++#endif				/* ESP_ANDROID_LOGGER */
++
++static int esdio_power_off(struct esp_sdio_ctrl *sctrl);
++static int esdio_power_on(struct esp_sdio_ctrl *sctrl);
++
++void sif_set_clock(struct sdio_func *func, int clk);
++
++void sif_lock_bus(struct esp_pub *epub)
++{
++	EPUB_FUNC_CHECK(epub, _exit);
++
++	sdio_claim_host(EPUB_TO_FUNC(epub));
++      _exit:
++	return;
++}
++
++void sif_unlock_bus(struct esp_pub *epub)
++{
++	EPUB_FUNC_CHECK(epub, _exit);
++
++	sdio_release_host(EPUB_TO_FUNC(epub));
++      _exit:
++	return;
++}
++
++static inline bool bad_buf(u8 * buf)
++{
++	return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf);
++}
++
++u8 sdio_io_readb(struct esp_pub *epub, int addr, int *res)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	struct sdio_func *func = NULL;
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++	func = sctrl->func;
++
++	if (func->num == 0)
++		return sdio_f0_readb(func, addr, res);
++	else
++		return sdio_readb(func, addr, res);
++}
++
++void sdio_io_writeb(struct esp_pub *epub, u8 value, int addr, int *res)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	struct sdio_func *func = NULL;
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++	func = sctrl->func;
++
++	if (func->num == 0)
++		sdio_f0_writeb(func, value, addr, res);
++	else
++		sdio_writeb(func, value, addr, res);
++}
++
++int sif_io_raw(struct esp_pub *epub, u32 addr, u8 * buf, u32 len, u32 flag)
++{
++	int err = 0;
++	u8 *ibuf = NULL;
++	bool need_ibuf = false;
++	struct esp_sdio_ctrl *sctrl = NULL;
++	struct sdio_func *func = NULL;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		err = -EINVAL;
++		goto _exit;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++	func = sctrl->func;
++	if (func == NULL) {
++		ESSERT(0);
++		err = -EINVAL;
++		goto _exit;
++	}
++
++	if (bad_buf(buf)) {
++		esp_dbg(ESP_DBG_TRACE, "%s dst 0x%08x, len %d badbuf\n",
++			__func__, addr, len);
++		need_ibuf = true;
++		ibuf = sctrl->dma_buffer;
++	} else {
++		ibuf = buf;
++	}
++
++	if (flag & SIF_BLOCK_BASIS) {
++		/* round up for block data transcation */
++	}
++
++	if (flag & SIF_TO_DEVICE) {
++
++		if (need_ibuf)
++			memcpy(ibuf, buf, len);
++
++		if (flag & SIF_FIXED_ADDR)
++			err = sdio_writesb(func, addr, ibuf, len);
++		else if (flag & SIF_INC_ADDR) {
++			err = sdio_memcpy_toio(func, addr, ibuf, len);
++		}
++	} else if (flag & SIF_FROM_DEVICE) {
++
++		if (flag & SIF_FIXED_ADDR)
++			err = sdio_readsb(func, ibuf, addr, len);
++		else if (flag & SIF_INC_ADDR) {
++			err = sdio_memcpy_fromio(func, ibuf, addr, len);
++		}
++
++
++		if (!err && need_ibuf)
++			memcpy(buf, ibuf, len);
++	}
++
++      _exit:
++	return err;
++}
++
++int sif_io_sync(struct esp_pub *epub, u32 addr, u8 * buf, u32 len,
++		u32 flag)
++{
++	int err = 0;
++	u8 *ibuf = NULL;
++	bool need_ibuf = false;
++	struct esp_sdio_ctrl *sctrl = NULL;
++	struct sdio_func *func = NULL;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		err = -EINVAL;
++		goto _exit;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++	func = sctrl->func;
++	if (func == NULL) {
++		ESSERT(0);
++		err = -EINVAL;
++		goto _exit;
++	}
++
++	if (bad_buf(buf)) {
++		esp_dbg(ESP_DBG_TRACE, "%s dst 0x%08x, len %d badbuf\n",
++			__func__, addr, len);
++		need_ibuf = true;
++		ibuf = sctrl->dma_buffer;
++	} else {
++		ibuf = buf;
++	}
++
++	if (flag & SIF_BLOCK_BASIS) {
++		/* round up for block data transcation */
++	}
++
++	if (flag & SIF_TO_DEVICE) {
++
++		esp_dbg(ESP_DBG_TRACE, "%s to addr 0x%08x, len %d \n",
++			__func__, addr, len);
++		if (need_ibuf)
++			memcpy(ibuf, buf, len);
++
++		sdio_claim_host(func);
++
++		if (flag & SIF_FIXED_ADDR)
++			err = sdio_writesb(func, addr, ibuf, len);
++		else if (flag & SIF_INC_ADDR) {
++			err = sdio_memcpy_toio(func, addr, ibuf, len);
++		}
++		sdio_release_host(func);
++	} else if (flag & SIF_FROM_DEVICE) {
++
++		esp_dbg(ESP_DBG_TRACE, "%s from addr 0x%08x, len %d \n",
++			__func__, addr, len);
++
++		sdio_claim_host(func);
++
++		if (flag & SIF_FIXED_ADDR)
++			err = sdio_readsb(func, ibuf, addr, len);
++		else if (flag & SIF_INC_ADDR) {
++			err = sdio_memcpy_fromio(func, ibuf, addr, len);
++		}
++
++		sdio_release_host(func);
++
++		if (!err && need_ibuf)
++			memcpy(buf, ibuf, len);
++	}
++
++      _exit:
++	return err;
++}
++
++int sif_lldesc_read_sync(struct esp_pub *epub, u8 * buf, u32 len)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	u32 read_len;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		return -EINVAL;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++
++	switch (sctrl->target_id) {
++	case 0x100:
++		read_len = len;
++		break;
++	case 0x600:
++		read_len = roundup(len, sctrl->slc_blk_sz);
++		break;
++	default:
++		read_len = len;
++		break;
++	}
++
++	return sif_io_sync((epub),
++			   (sctrl->slc_window_end_addr - 2 - (len)), (buf),
++			   (read_len),
++			   SIF_FROM_DEVICE | SIF_BYTE_BASIS |
++			   SIF_INC_ADDR);
++}
++
++int sif_lldesc_write_sync(struct esp_pub *epub, u8 * buf, u32 len)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	u32 write_len;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		return -EINVAL;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++
++	switch (sctrl->target_id) {
++	case 0x100:
++		write_len = len;
++		break;
++	case 0x600:
++		write_len = roundup(len, sctrl->slc_blk_sz);
++		break;
++	default:
++		write_len = len;
++		break;
++	}
++
++	return sif_io_sync((epub), (sctrl->slc_window_end_addr - (len)),
++			   (buf), (write_len),
++			   SIF_TO_DEVICE | SIF_BYTE_BASIS | SIF_INC_ADDR);
++}
++
++int sif_lldesc_read_raw(struct esp_pub *epub, u8 * buf, u32 len,
++			bool noround)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	u32 read_len;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		return -EINVAL;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++
++	switch (sctrl->target_id) {
++	case 0x100:
++		read_len = len;
++		break;
++	case 0x600:
++		if (!noround)
++			read_len = roundup(len, sctrl->slc_blk_sz);
++		else
++			read_len = len;
++		break;
++	default:
++		read_len = len;
++		break;
++	}
++
++	return sif_io_raw((epub), (sctrl->slc_window_end_addr - 2 - (len)),
++			  (buf), (read_len),
++			  SIF_FROM_DEVICE | SIF_BYTE_BASIS | SIF_INC_ADDR);
++}
++
++int sif_lldesc_write_raw(struct esp_pub *epub, u8 * buf, u32 len)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	u32 write_len;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		return -EINVAL;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++
++	switch (sctrl->target_id) {
++	case 0x100:
++		write_len = len;
++		break;
++	case 0x600:
++		write_len = roundup(len, sctrl->slc_blk_sz);
++		break;
++	default:
++		write_len = len;
++		break;
++	}
++	return sif_io_raw((epub), (sctrl->slc_window_end_addr - (len)),
++			  (buf), (write_len),
++			  SIF_TO_DEVICE | SIF_BYTE_BASIS | SIF_INC_ADDR);
++
++}
++
++static int esdio_power_on(struct esp_sdio_ctrl *sctrl)
++{
++	int err = 0;
++
++	if (sctrl->off == false)
++		return err;
++
++	sdio_claim_host(sctrl->func);
++	err = sdio_enable_func(sctrl->func);
++
++	if (err) {
++		esp_dbg(ESP_DBG_ERROR, "Unable to enable sdio func: %d\n",
++			err);
++		sdio_release_host(sctrl->func);
++		return err;
++	}
++
++	sdio_release_host(sctrl->func);
++
++	/* ensure device is up */
++	msleep(5);
++
++	sctrl->off = false;
++
++	return err;
++}
++
++static int esdio_power_off(struct esp_sdio_ctrl *sctrl)
++{
++	int err;
++
++	if (sctrl->off)
++		return 0;
++
++	sdio_claim_host(sctrl->func);
++	err = sdio_disable_func(sctrl->func);
++	sdio_release_host(sctrl->func);
++
++	if (err)
++		return err;
++
++	sctrl->off = true;
++
++	return err;
++}
++
++void sif_enable_irq(struct esp_pub *epub)
++{
++	int err;
++	struct esp_sdio_ctrl *sctrl = NULL;
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++
++	sdio_claim_host(sctrl->func);
++
++	err = sdio_claim_irq(sctrl->func, sif_dsr);
++
++	if (err)
++		esp_dbg(ESP_DBG_ERROR, "sif %s failed\n", __func__);
++
++	atomic_set(&epub->sip->state, SIP_BOOT);
++
++	atomic_set(&sctrl->irq_installed, 1);
++
++	sdio_release_host(sctrl->func);
++}
++
++void sif_disable_irq(struct esp_pub *epub)
++{
++	struct esp_sdio_ctrl *sctrl = (struct esp_sdio_ctrl *) epub->sif;
++	int i = 0;
++
++	if (atomic_read(&sctrl->irq_installed) == 0)
++		return;
++
++	sdio_claim_host(sctrl->func);
++
++	while (atomic_read(&sctrl->irq_handling)) {
++		sdio_release_host(sctrl->func);
++		schedule_timeout(HZ / 100);
++		sdio_claim_host(sctrl->func);
++		if (i++ >= 400) {
++			esp_dbg(ESP_DBG_ERROR, "%s force to stop irq\n",
++				__func__);
++			break;
++		}
++	}
++
++	/* Ignore errors, we don't always use an irq. */
++	sdio_release_irq(sctrl->func);
++
++	atomic_set(&sctrl->irq_installed, 0);
++
++	sdio_release_host(sctrl->func);
++
++}
++
++void sif_set_clock(struct sdio_func *func, int clk)
++{
++	struct mmc_host *host = NULL;
++	struct mmc_card *card = NULL;
++
++	card = func->card;
++	host = card->host;
++
++	sdio_claim_host(func);
++
++	//currently only set clock
++	host->ios.clock = clk * 1000000;
++
++	esp_dbg(ESP_SHOW, "%s clock is %u\n", __func__, host->ios.clock);
++	if (host->ios.clock > host->f_max) {
++		host->ios.clock = host->f_max;
++	}
++	host->ops->set_ios(host, &host->ios);
++
++	mdelay(2);
++
++	sdio_release_host(func);
++}
++
++static int esp_sdio_probe(struct sdio_func *func,
++			  const struct sdio_device_id *id);
++static void esp_sdio_remove(struct sdio_func *func);
++
++static int esp_sdio_probe(struct sdio_func *func,
++			  const struct sdio_device_id *id)
++{
++	int err = 0;
++	struct esp_pub *epub = NULL;
++	struct esp_sdio_ctrl *sctrl;
++
++	esp_dbg(ESP_DBG_TRACE,
++		"sdio_func_num: 0x%X, vendor id: 0x%X, dev id: 0x%X, block size: 0x%X/0x%X\n",
++		func->num, func->vendor, func->device, func->max_blksize,
++		func->cur_blksize);
++
++	if (sif_sctrl == NULL) {
++
++		esp_conf_init(&func->dev);
++
++		esp_conf_upload_first();
++
++		sctrl = kzalloc(sizeof(struct esp_sdio_ctrl), GFP_KERNEL);
++
++		if (sctrl == NULL) {
++			return -ENOMEM;
++		}
++
++		/* temp buffer reserved for un-dma-able request */
++		sctrl->dma_buffer = kzalloc(ESP_DMA_IBUFSZ, GFP_KERNEL);
++
++		if (sctrl->dma_buffer == NULL) {
++			err = -ENOMEM;
++			goto _err_last;
++		}
++		sif_sctrl = sctrl;
++		sctrl->slc_blk_sz = SIF_SLC_BLOCK_SIZE;
++
++		epub = esp_pub_alloc_mac80211(&func->dev);
++
++		if (epub == NULL) {
++			esp_dbg(ESP_DBG_ERROR, "no mem for epub \n");
++			err = -ENOMEM;
++			goto _err_dma;
++		}
++		epub->sif = (void *) sctrl;
++		epub->sdio_state = ESP_SDIO_STATE_FIRST_INIT;
++		sctrl->epub = epub;
++
++#ifdef USE_EXT_GPIO
++		if (sif_get_ate_config() == 0) {
++			err = ext_gpio_init(epub);
++			if (err) {
++				esp_dbg(ESP_DBG_ERROR,
++					"ext_irq_work_init failed %d\n",
++					err);
++				goto _err_epub;
++			}
++		}
++#endif
++
++	} else {
++		sctrl = sif_sctrl;
++		sif_sctrl = NULL;
++		epub = sctrl->epub;
++		epub->sdio_state = ESP_SDIO_STATE_SECOND_INIT;
++		SET_IEEE80211_DEV(epub->hw, &func->dev);
++		epub->dev = &func->dev;
++	}
++
++	sctrl->func = func;
++	sdio_set_drvdata(func, sctrl);
++
++	sctrl->id = id;
++	sctrl->off = true;
++
++	/* give us some time to enable, in ms */
++	func->enable_timeout = 100;
++
++	err = esdio_power_on(sctrl);
++	esp_dbg(ESP_DBG_TRACE, " %s >> power_on err %d \n", __func__, err);
++
++	if (err) {
++		if (epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT)
++			goto _err_ext_gpio;
++		else
++			goto _err_second_init;
++	}
++	check_target_id(epub);
++
++	sdio_claim_host(func);
++
++	err = sdio_set_block_size(func, sctrl->slc_blk_sz);
++
++	if (err) {
++		esp_dbg(ESP_DBG_ERROR,
++			"Set sdio block size %d failed: %d)\n",
++			sctrl->slc_blk_sz, err);
++		sdio_release_host(func);
++		if (epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT)
++			goto _err_off;
++		else
++			goto _err_second_init;
++	}
++
++	sdio_release_host(func);
++
++#ifdef LOWER_CLK
++	/* fix clock for dongle */
++	sif_set_clock(func, 23);
++#endif				//LOWER_CLK
++
++	err = esp_pub_init_all(epub);
++
++	if (err) {
++		esp_dbg(ESP_DBG_ERROR, "esp_init_all failed: %d\n", err);
++		if (epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT) {
++			err = 0;
++			goto _err_first_init;
++		}
++		if (epub->sdio_state == ESP_SDIO_STATE_SECOND_INIT)
++			goto _err_second_init;
++	}
++
++	esp_dbg(ESP_DBG_TRACE, " %s return  %d\n", __func__, err);
++	if (epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT) {
++		esp_dbg(ESP_DBG_TRACE, "first normal exit\n");
++		epub->sdio_state = ESP_SDIO_STATE_FIRST_NORMAL_EXIT;
++		/* Rescan the esp8089 after loading the initial firmware */
++		sdio_claim_host(func);
++		mmc_sw_reset(func->card);
++		sdio_release_host(func);
++		msleep(10);
++	}
++
++	return err;
++
++      _err_off:
++	esdio_power_off(sctrl);
++      _err_ext_gpio:
++#ifdef USE_EXT_GPIO
++	if (sif_get_ate_config() == 0)
++		ext_gpio_deinit();
++      _err_epub:
++#endif
++	esp_pub_dealloc_mac80211(epub);
++      _err_dma:
++	kfree(sctrl->dma_buffer);
++      _err_last:
++	kfree(sctrl);
++      _err_first_init:
++	if (epub && epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT) {
++		esp_dbg(ESP_DBG_ERROR, "first error exit\n");
++		epub->sdio_state = ESP_SDIO_STATE_FIRST_ERROR_EXIT;
++	}
++	return err;
++      _err_second_init:
++	epub->sdio_state = ESP_SDIO_STATE_SECOND_ERROR_EXIT;
++	esp_sdio_remove(func);
++	return err;
++}
++
++static void esp_sdio_remove(struct sdio_func *func)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	struct esp_pub *epub = NULL;
++
++	esp_dbg(ESP_DBG_TRACE, "%s enter\n", __func__);
++
++	sctrl = sdio_get_drvdata(func);
++
++	if (sctrl == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "%s no sctrl\n", __func__);
++		return;
++	}
++
++	do {
++		epub = sctrl->epub;
++		if (epub == NULL) {
++			esp_dbg(ESP_DBG_ERROR, "%s epub null\n", __func__);
++			break;
++		}
++		if (epub->sdio_state != ESP_SDIO_STATE_FIRST_NORMAL_EXIT) {
++			if (epub->sip) {
++				sip_detach(epub->sip);
++				epub->sip = NULL;
++				esp_dbg(ESP_DBG_TRACE,
++					"%s sip detached \n", __func__);
++			}
++#ifdef USE_EXT_GPIO
++			if (sif_get_ate_config() == 0)
++				ext_gpio_deinit();
++#endif
++		} else {
++			//sif_disable_target_interrupt(epub);
++			atomic_set(&epub->sip->state, SIP_STOP);
++			sif_disable_irq(epub);
++		}
++
++		if (epub->sdio_state != ESP_SDIO_STATE_FIRST_NORMAL_EXIT) {
++			esp_pub_dealloc_mac80211(epub);
++			esp_dbg(ESP_DBG_TRACE, "%s dealloc mac80211 \n",
++				__func__);
++
++			if (sctrl->dma_buffer) {
++				kfree(sctrl->dma_buffer);
++				sctrl->dma_buffer = NULL;
++				esp_dbg(ESP_DBG_TRACE,
++					"%s free dma_buffer \n", __func__);
++			}
++
++			kfree(sctrl);
++		}
++
++	} while (0);
++
++	sdio_set_drvdata(func, NULL);
++
++	/*
++	 * Reset on sdio remove to leave the hardware in cold state,
++	 * so a new module insertion will be possible
++	 */
++	if (epub->sdio_state == ESP_SDIO_STATE_SECOND_INIT) {
++		sdio_claim_host(func);
++		mmc_hw_reset(func->card);
++		sdio_release_host(func);
++		mdelay(10);
++	}
++
++	esp_dbg(ESP_DBG_TRACE, "eagle sdio remove complete\n");
++}
++
++static int esp_sdio_suspend(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	struct esp_sdio_ctrl *sctrl = sdio_get_drvdata(func);
++	struct esp_pub *epub = sctrl->epub;
++
++	printk("%s", __func__);
++	atomic_set(&epub->ps.state, ESP_PM_ON);
++
++	do {
++		u32 sdio_flags = 0;
++		int ret = 0;
++		sdio_flags = sdio_get_host_pm_caps(func);
++
++		if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
++			printk
++			    ("%s can't keep power while host is suspended\n",
++			     __func__);
++		}
++
++		/* keep power while host suspended */
++		ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
++		if (ret) {
++			printk("%s error while trying to keep power\n",
++			       __func__);
++		}
++	} while (0);
++
++
++	return 0;
++
++}
++
++static int esp_sdio_resume(struct device *dev)
++{
++	esp_dbg(ESP_DBG_ERROR, "%s", __func__);
++
++	return 0;
++}
++
++static const struct dev_pm_ops esp_sdio_pm_ops = {
++	.suspend = esp_sdio_suspend,
++	.resume = esp_sdio_resume,
++};
++
++static struct sdio_driver esp_sdio_driver = {
++	.name = "eagle_sdio",
++	.id_table = esp_sdio_devices,
++	.probe = esp_sdio_probe,
++	.remove = esp_sdio_remove,
++	.drv = {
++		.pm = &esp_sdio_pm_ops,
++		.of_match_table = esp_of_match_table,
++	},
++};
++
++static int /*__init*/ esp_sdio_init(void)
++{
++
++	esp_debugfs_init();
++	sdio_register_driver(&esp_sdio_driver);
++
++	msleep(1000);
++
++	sdio_unregister_driver(&esp_sdio_driver);
++	msleep(100);
++	sdio_register_driver(&esp_sdio_driver);
++
++	return 0;
++}
++
++static void /*__exit*/ esp_sdio_exit(void)
++{
++	sdio_unregister_driver(&esp_sdio_driver);
++	esp_debugfs_exit();
++}
++
++MODULE_DEVICE_TABLE(sdio, esp_sdio_devices);
++MODULE_DEVICE_TABLE(of, esp_of_match_table);
++MODULE_AUTHOR("Espressif System");
++MODULE_DESCRIPTION
++    ("Driver for SDIO interconnected eagle low-power WLAN devices");
++MODULE_LICENSE("GPL");
++
++module_init(esp_sdio_init);
++module_exit(esp_sdio_exit);
+diff --git a/drivers/net/wireless/esp8089/sip2_common.h b/drivers/net/wireless/esp8089/sip2_common.h
+new file mode 100644
+index 000000000000..d46e87589b0b
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/sip2_common.h
+@@ -0,0 +1,475 @@
++/*
++ *  Copyright (c) 2010 - 2014 Espressif System.
++ *
++ *   Common definitions of Serial Interconnctor Protocol
++ *
++ *   little endian
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _SIP2_COMMON_H
++#define _SIP2_COMMON_H
++
++#ifdef __ets__
++#include "utils.h"
++#endif /*__ets__*/
++
++/* max 16 types */
++typedef enum {
++	SIP_CTRL = 0,
++	SIP_DATA,
++	SIP_DATA_AMPDU
++} SIP_TYPE;
++
++typedef enum {
++	SIP_TX_CTRL_BUF = 0,	/* from host */
++	SIP_RX_CTRL_BUF,	/* to host */
++	SIP_TX_DATA_BUF,	/* from host */
++	SIP_RX_DATA_BUF		/* to host */
++} SIP_BUF_TYPE;
++
++enum sip_cmd_id {
++	SIP_CMD_GET_VER = 0,
++	SIP_CMD_WRITE_MEMORY,	//1 ROM code
++	SIP_CMD_READ_MEMORY,	//2
++	SIP_CMD_WRITE_REG,	//3 ROM code
++	SIP_CMD_READ_REG,	//4
++	SIP_CMD_BOOTUP,		//5 ROM code
++	SIP_CMD_COPYBACK,	//6
++	SIP_CMD_INIT,		//7
++	SIP_CMD_SCAN,		//8
++	SIP_CMD_SETKEY,		//9
++	SIP_CMD_CONFIG,		//10
++	SIP_CMD_BSS_INFO_UPDATE,	//11
++	SIP_CMD_LOOPBACK,	//12  ROM code
++	//do not add cmd before this line
++	SIP_CMD_SET_WMM_PARAM,
++	SIP_CMD_AMPDU_ACTION,
++	SIP_CMD_HB_REQ,		//15
++	SIP_CMD_RESET_MAC,	//16
++	SIP_CMD_PRE_DOWN,	//17
++	SIP_CMD_SLEEP,		/* for sleep testing */
++	SIP_CMD_WAKEUP,		/* for sleep testing */
++	SIP_CMD_DEBUG,		/* for general testing */
++	SIP_CMD_GET_FW_VER,	/* get fw rev. */
++	SIP_CMD_SETVIF,
++	SIP_CMD_SETSTA,
++	SIP_CMD_PS,
++	SIP_CMD_ATE,
++	SIP_CMD_SUSPEND,
++	SIP_CMD_RECALC_CREDIT,
++	SIP_CMD_MAX,
++};
++
++enum {
++	SIP_EVT_TARGET_ON = 0,	//
++	SIP_EVT_BOOTUP,		//1 in ROM code
++	SIP_EVT_COPYBACK,	//2
++	SIP_EVT_SCAN_RESULT,	//3
++	SIP_EVT_TX_STATUS,	//4
++	SIP_EVT_CREDIT_RPT,	//5, in ROM code
++	SIP_EVT_ERROR,		//6
++	SIP_EVT_LOOPBACK,	//7, in ROM code
++	SIP_EVT_SNPRINTF_TO_HOST,	//8  in ROM code
++	//do not add evt before this line
++	SIP_EVT_HB_ACK,		//9
++	SIP_EVT_RESET_MAC_ACK,	//10
++	SIP_EVT_WAKEUP,		//11        /* for sleep testing */
++	SIP_EVT_DEBUG,		//12          /* for general testing */
++	SIP_EVT_PRINT_TO_HOST,	//13
++	SIP_EVT_TRC_AMPDU,	//14
++	SIP_EVT_ROC,		//15
++	SIP_EVT_RESETTING,
++	SIP_EVT_ATE,
++	SIP_EVT_EP,
++	SIP_EVT_INIT_EP,
++	SIP_EVT_SLEEP,
++	SIP_EVT_TXIDLE,
++	SIP_EVT_NOISEFLOOR,
++	SIP_EVT_MAX
++};
++
++#define SIP_IFIDX_MASK 0xf0
++#define SIP_IFIDX_S 4
++#define SIP_TYPE_MASK 0x0f
++#define SIP_TYPE_S 0
++
++#define SIP_HDR_GET_IFIDX(fc0) (((fc0) & SIP_IFIDX_MASK) >> SIP_IFIDX_S)
++#define SIP_HDR_SET_IFIDX(fc0, ifidx) ( (fc0) = ((fc0) & ~SIP_IFIDX_MASK) | ((ifidx) << SIP_IFIDX_S & SIP_IFIDX_MASK) )
++#define SIP_HDR_GET_TYPE(fc0) ((fc0) & SIP_TYPE_MASK )
++/* assume type field is cleared */
++#define SIP_HDR_SET_TYPE(fc0, type) ((fc0) = ((fc0) & ~ SIP_TYPE_MASK) | ((type) & SIP_TYPE_MASK))
++
++/* sip 2.0, not hybrid header so far */
++#define SIP_HDR_IS_CTRL(hdr) (SIP_HDR_GET_TYPE((hdr)->fc[0]) == SIP_CTRL)
++#define SIP_HDR_IS_DATA(hdr) (SIP_HDR_GET_TYPE((hdr)->fc[0]) == SIP_DATA)
++#define SIP_HDR_IS_AMPDU(hdr) (SIP_HDR_GET_TYPE((hdr)->fc[0]) == SIP_DATA_AMPDU)
++
++/* fc[1] flags, only for data pkt. Ctrl pkts use fc[1] as eventID */
++#define SIP_HDR_SET_FLAGS(hdr, flags) ((hdr)->fc[1] |= (flags))
++#define SIP_HDR_F_MORE_PKT 0x1
++#define SIP_HDR_F_NEED_CRDT_RPT 0x2
++#define SIP_HDR_F_SYNC 0x4
++#define SIP_HDR_F_SYNC_RESET 0x8
++#define SIP_HDR_F_PM_TURNING_ON 0x10
++#define SIP_HDR_F_PM_TURNING_OFF 0x20
++
++#define SIP_HDR_NEED_CREDIT_UPDATE(hdr) ((hdr)->fc[1] & SIP_HDR_F_NEED_CRDT_RPT)
++#define SIP_HDR_IS_MORE_PKT(hdr) ((hdr)->fc[1] & SIP_HDR_F_MORE_PKT)
++#define SIP_HDR_IS_CRDT_RPT(hdr) ((hdr)->fc[1] & SIP_HDR_F_CRDT_RPT)
++#define SIP_HDR_IS_SYNC(hdr) ((hdr)->fc[1] & SIP_HDR_F_SYNC)
++#define SIP_HDR_IS_SYNC_RESET(hdr) ((hdr)->fc[1] & SIP_HDR_F_SYNC_RESET)
++#define SIP_HDR_IS_SYNC_PKT(hdr) (SIP_HDR_IS_SYNC(hdr) | SIP_HDR_IS_SYNC_RESET(hdr))
++#define SIP_HDR_SET_SYNC(hdr) SIP_HDR_SET_FLAGS((hdr), SIP_HDR_F_SYNC)
++#define SIP_HDR_SET_SYNC_RESET(hdr) SIP_HDR_SET_FLAGS((hdr), SIP_HDR_F_SYNC_RESET)
++#define SIP_HDR_SET_MORE_PKT(hdr) SIP_HDR_SET_FLAGS((hdr), SIP_HDR_F_MORE_PKT)
++#define SIP_HDR_SET_PM_TURNING_ON(hdr) SIP_HDR_SET_FLAGS((hdr), SIP_HDR_F_PM_TURNING_ON)
++#define SIP_HDR_IS_PM_TURNING_ON(hdr) ((hdr)->fc[1] & SIP_HDR_F_PM_TURNING_ON)
++#define SIP_HDR_SET_PM_TURNING_OFF(hdr) SIP_HDR_SET_FLAGS((hdr), SIP_HDR_F_PM_TURNING_OFF)
++#define SIP_HDR_IS_PM_TURNING_OFF(hdr) ((hdr)->fc[1] & SIP_HDR_F_PM_TURNING_OFF)
++
++/*
++ * fc[0]: first 4bit: ifidx; last 4bit: type
++ * fc[1]: flags
++ *
++ *   Don't touch the header definitons
++ */
++struct sip_hdr_min {
++	u8 fc[2];
++	__le16 len;
++} __packed;
++
++/* not more than 4byte long */
++struct sip_tx_data_info {
++	u8 tid;
++	u8 ac;
++	u8 p2p:1, enc_flag:7;
++	u8 hw_kid;
++} __packed;
++
++/* NB: this structure should be not more than 4byte !! */
++struct sip_tx_info {
++	union {
++		u32 cmdid;
++		struct sip_tx_data_info dinfo;
++	} u;
++} __packed;
++
++struct sip_hdr {
++	u8 fc[2];		//fc[0]: type and ifidx ; fc[1] is eventID if the first ctrl pkt in the chain. data pkt still can use fc[1] to set flag
++	__le16 len;
++	union {
++		volatile u32 recycled_credits;	/* last 12bits is credits, first 20 bits is actual length of the first pkt in the chain */
++		struct sip_tx_info tx_info;
++	} u;
++	u32 seq;
++} __packed;
++
++#define h_credits u.recycled_credits
++#define c_evtid fc[1]
++#define c_cmdid u.tx_info.u.cmdid
++#define d_ac u.tx_info.u.dinfo.ac
++#define d_tid  u.tx_info.u.dinfo.tid
++#define d_p2p   u.tx_info.u.dinfo.p2p
++#define d_enc_flag u.tx_info.u.dinfo.enc_flag
++#define d_hw_kid   u.tx_info.u.dinfo.hw_kid
++
++#define SIP_CREDITS_MASK  0xfff	/* last 12 bits */
++
++#ifdef HOST_RC
++
++#define RC_CNT_MASK 0xf
++
++struct sip_rc_status {
++	u32 rc_map;
++	union {
++		u32 rc_cnt1:4, rc_cnt2:4, rc_cnt3:4, rc_cnt4:4, rc_cnt5:4;
++
++		u32 rc_cnt_store;
++	};
++};
++
++/* copy from mac80211.h */
++struct sip_tx_rc {
++	struct ieee80211_tx_rate rates[IEEE80211_TX_MAX_RATES];
++	s8 rts_cts_rate_idx;
++};
++#endif				/* HOST_RC */
++
++#define SIP_HDR_MIN_LEN 4
++#define SIP_HDR_LEN		sizeof(struct sip_hdr)
++#define SIP_CTRL_HDR_LEN 	SIP_HDR_LEN	/* same as sip_hdr in sip2 design */
++#define SIP_BOOT_BUF_SIZE 256
++#define SIP_CTRL_BUF_SZ 256	/* too much?? */
++#define SIP_CTRL_BUF_N 6
++#define SIP_CTRL_TXBUF_N 2
++#define SIP_CTRL_RXBUF_N 4
++
++/* WAR for mblk */
++#define SIP_RX_ADDR_PREFIX_MASK 0xfc000000
++#define SIP_RX_ADDR_SHIFT 6	/* [31:5],  shift 6 bits */
++
++struct sip_cmd_write_memory {
++	u32 addr;
++	u32 len;
++} __packed;
++
++struct sip_cmd_read_memory {
++	u32 addr;
++	u32 len;
++} __packed;
++
++struct sip_cmd_write_reg {
++	u32 addr;
++	u32 val;
++} __packed;
++
++struct sip_cmd_bootup {
++	u32 boot_addr;
++} __packed;
++
++struct sip_cmd_loopback {
++	u32 txlen;		//host to target packet len, 0 means no txpacket
++	u32 rxlen;		//target to host packet len, 0 means no rxpacket
++	u32 pack_id;		//sequence of packet
++} __packed;
++
++struct sip_evt_loopback {
++	u32 txlen;		//host to target packet len, 0 means no txpacket
++	u32 rxlen;		//target to host packet len, 0 means no rxpacket
++	u32 pack_id;		//sequence of packet
++} __packed;
++
++struct sip_cmd_copyback {
++	u32 addr;
++	u32 len;
++} __packed;
++
++struct sip_cmd_scan {
++//        u8  ssid[32];
++	u8 ssid_len;
++//        u8 hw_channel[14];
++	u8 n_channels;
++	u8 ie_len;
++	u8 aborted;
++} __packed;			// ie[] append at the end
++
++
++#ifndef ETH_ALEN
++#define ETH_ALEN 6
++#endif				/* ETH_ALEN */
++
++struct sip_cmd_setkey {
++	u8 bssid_no;
++	u8 addr[ETH_ALEN];
++	u8 alg;
++	u8 keyidx;
++	u8 hw_key_idx;
++	u8 flags;
++	u8 keylen;
++	u8 key[32];
++} __packed;
++
++struct sip_cmd_config {
++	u16 center_freq;
++	u16 duration;
++} __packed;
++
++struct sip_cmd_bss_info_update {
++	u8 bssid[ETH_ALEN];
++	u16 isassoc;
++	u32 beacon_int;
++	u8 bssid_no;
++} __packed;
++
++struct sip_evt_bootup {
++	u16 tx_blksz;
++	u8 mac_addr[ETH_ALEN];
++	/* anything else ? */
++} __packed;
++
++struct sip_cmd_setvif {
++	u8 index;
++	u8 mac[ETH_ALEN];
++	u8 set;
++	u8 op_mode;
++	u8 is_p2p;
++} __packed;
++
++enum esp_ieee80211_phytype {
++	ESP_IEEE80211_T_CCK = 0,
++	ESP_IEEE80211_T_OFDM = 1,
++	ESP_IEEE80211_T_HT20_L = 2,
++	ESP_IEEE80211_T_HT20_S = 3,
++};
++
++struct sip_cmd_setsta {
++	u8 ifidx;
++	u8 index;
++	u8 set;
++	u8 phymode;
++	u8 mac[ETH_ALEN];
++	u16 aid;
++	u8 ampdu_factor;
++	u8 ampdu_density;
++	u16 resv;
++} __packed;
++
++struct sip_cmd_ps {
++	u8 dtim_period;
++	u8 max_sleep_period;
++	u8 on;
++	u8 resv;
++} __packed;
++
++struct sip_cmd_suspend {
++	u8 suspend;
++	u8 resv[3];
++} __packed;
++
++#define SIP_DUMP_RPBM_ERR	BIT(0)
++#define SIP_RXABORT_FIXED	BIT(1)
++#define SIP_SUPPORT_BGSCAN	BIT(2)
++struct sip_evt_bootup2 {
++	u16 tx_blksz;
++	u8 mac_addr[ETH_ALEN];
++	u16 rx_blksz;
++	u8 credit_to_reserve;
++	u8 options;
++	s16 noise_floor;
++	u8 resv[2];
++	/* anything else ? */
++} __packed;
++
++typedef enum {
++	TRC_TX_AMPDU_STOPPED = 1,
++	TRC_TX_AMPDU_OPERATIONAL,
++	TRC_TX_AMPDU_WAIT_STOP,
++	TRC_TX_AMPDU_WAIT_OPERATIONAL,
++	TRC_TX_AMPDU_START,
++} trc_ampdu_state_t;
++
++struct sip_evt_trc_ampdu {
++	u8 state;
++	u8 tid;
++	u8 addr[ETH_ALEN];
++} __packed;
++
++struct sip_cmd_set_wmm_params {
++	u8 aci;
++	u8 aifs;
++	u8 ecw_min;
++	u8 ecw_max;
++	u16 txop_us;
++} __packed;
++
++#define SIP_AMPDU_RX_START 0
++#define SIP_AMPDU_RX_STOP 1
++#define SIP_AMPDU_TX_OPERATIONAL 2
++#define SIP_AMPDU_TX_STOP 3
++struct sip_cmd_ampdu_action {
++	u8 action;
++	u8 index;
++	u8 tid;
++	u8 win_size;
++	u16 ssn;
++	u8 addr[ETH_ALEN];
++} __packed;
++
++#define SIP_TX_ST_OK 0
++#define SIP_TX_ST_NOEB 1
++#define SIP_TX_ST_ACKTO 2
++#define SIP_TX_ST_ENCERR 3
++
++//NB: sip_tx_status must be 4 bytes aligned
++struct sip_tx_status {
++	u32 sip_seq;
++#ifdef HOST_RC
++	struct sip_rc_status rcstatus;
++#endif				/* HOST_RC */
++	u8 errno;		/* success or failure code */
++	u8 rate_index;
++	char ack_signal;
++	u8 pad;
++} __packed;
++
++struct sip_evt_tx_report {
++	u32 pkts;
++	struct sip_tx_status status[0];
++} __packed;
++
++struct sip_evt_tx_mblk {
++	u32 mblk_map;
++} __packed;
++
++struct sip_evt_scan_report {
++	u16 scan_id;
++	u16 aborted;
++} __packed;
++
++struct sip_evt_roc {
++	u16 state;		//start:1, end :0
++	u16 is_ok;
++} __packed;
++
++struct sip_evt_txidle {
++	u32 last_seq;
++} __packed;
++
++struct sip_evt_noisefloor {
++	s16 noise_floor;
++	u16 pad;
++} __packed;
++/*
++ *  for mblk direct memory access, no need for sip_hdr. tx: first 2k for contrl msg,
++ *  rest of 14k for data.  rx, same.
++ */
++#ifdef TEST_MODE
++
++struct sip_cmd_sleep {
++	u32 sleep_mode;
++	u32 sleep_tm_ms;
++	u32 wakeup_tm_ms;	//zero: after receive bcn, then sleep, nozero: delay nozero ms to sleep
++	u32 sleep_times;	//zero: always sleep, nozero: after nozero number sleep/wakeup, then end up sleep
++} __packed;
++
++struct sip_cmd_wakeup {
++	u32 check_data;		//0:copy to event
++} __packed;
++
++struct sip_evt_wakeup {
++	u32 check_data;
++} __packed;
++
++//general debug command
++struct sip_cmd_debug {
++	u32 cmd_type;
++	u32 para_num;
++	u32 para[10];
++} __packed;
++
++struct sip_evt_debug {
++	u16 len;
++	u32 results[12];
++	u16 pad;
++} __packed;
++
++struct sip_cmd_ate {
++	//u8  len;
++	u8 cmdstr[0];
++} __packed;
++
++
++
++#endif				//ifdef TEST_MODE
++
++#endif				/* _SIP_COMMON_H_ */
+diff --git a/drivers/net/wireless/esp8089/slc_host_register.h b/drivers/net/wireless/esp8089/slc_host_register.h
+new file mode 100644
+index 000000000000..2cdb2c856d15
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/slc_host_register.h
+@@ -0,0 +1,271 @@
++//Generated at 2012-10-23 20:11:08
++/*
++ *  Copyright (c) 2011 Espressif System
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef SLC_HOST_REGISTER_H_INCLUDED
++#define SLC_HOST_REGISTER_H_INCLUDED
++
++/* #define REG_SLC_HOST_BASE  0x00000000 */
++/* skip the token1, since reading it will clean the credit */
++#define REG_SLC_HOST_BASE  0x00000000
++#define REG_SLC_BASE  0x00000000
++
++
++#define SLC_HOST_PF                          (REG_SLC_HOST_BASE + 0x0)
++#define SLC_HOST_TOKEN_RDATA                 (REG_SLC_HOST_BASE + 0x4)
++#define SLC_HOST_RX_PF_EOF 0x0000000F
++#define SLC_HOST_RX_PF_EOF_S                 28
++#define SLC_HOST_TOKEN1 0x00000FFF
++#define SLC_HOST_TOKEN1_S 16
++#define SLC_HOST_RX_PF_VALID (BIT(15))
++#define SLC_HOST_TOKEN0               0x00000FFF
++#define SLC_HOST_TOKEN0_S 0
++
++#define SLC_HOST_TOKEN0_MASK SLC_HOST_TOKEN0
++
++#define SLC_HOST_INT_RAW                     (REG_SLC_HOST_BASE + 0x8)
++#define SLC_HOST_EXT_BIT3_INT_RAW (BIT(22))
++#define SLC_HOST_EXT_BIT2_INT_RAW (BIT(21))
++#define SLC_HOST_EXT_BIT1_INT_RAW (BIT(20))
++#define SLC_HOST_RXFIFO_NOT_EMPTY_INT_RAW (BIT(19))
++#define SLC_HOST_RX_PF_VALID_INT_RAW (BIT(18))
++#define SLC_HOST_TX_OVF_INT_RAW (BIT(17))
++#define SLC_HOST_RX_UDF_INT_RAW (BIT(16))
++#define SLC_HOST_TX_START_INT_RAW (BIT(15))
++#define SLC_HOST_RX_START_INT_RAW (BIT(14))
++#define SLC_HOST_RX_EOF_INT_RAW (BIT(13))
++#define SLC_HOST_RX_SOF_INT_RAW (BIT(12))
++#define SLC_HOST_TOKEN1_0TO1_INT_RAW (BIT(11))
++#define SLC_HOST_TOKEN0_0TO1_INT_RAW (BIT(10))
++#define SLC_HOST_TOKEN1_1TO0_INT_RAW (BIT(9))
++#define SLC_HOST_TOKEN0_1TO0_INT_RAW (BIT(8))
++#define SLC_HOST_TOHOST_BIT7_INT_RAW (BIT(7))
++#define SLC_HOST_TOHOST_BIT6_INT_RAW (BIT(6))
++#define SLC_HOST_TOHOST_BIT5_INT_RAW (BIT(5))
++#define SLC_HOST_TOHOST_BIT4_INT_RAW (BIT(4))
++#define SLC_HOST_TOHOST_BIT3_INT_RAW (BIT(3))
++#define SLC_HOST_TOHOST_BIT2_INT_RAW (BIT(2))
++#define SLC_HOST_TOHOST_BIT1_INT_RAW (BIT(1))
++#define SLC_HOST_TOHOST_BIT0_INT_RAW (BIT(0))
++
++#define SLC_HOST_STATE_W0                    (REG_SLC_HOST_BASE + 0xC)
++#define SLC_HOST_STATE3 0x000000FF
++#define SLC_HOST_STATE3_S 24
++#define SLC_HOST_STATE2 0x000000FF
++#define SLC_HOST_STATE2_S 16
++#define SLC_HOST_STATE1 0x000000FF
++#define SLC_HOST_STATE1_S 8
++#define SLC_HOST_STATE0 0x000000FF
++#define SLC_HOST_STATE0_S 0
++
++#define SLC_HOST_STATE_W1                    (REG_SLC_HOST_BASE + 0x10)
++#define SLC_HOST_STATE7 0x000000FF
++#define SLC_HOST_STATE7_S 24
++#define SLC_HOST_STATE6 0x000000FF
++#define SLC_HOST_STATE6_S 16
++#define SLC_HOST_STATE5 0x000000FF
++#define SLC_HOST_STATE5_S 8
++#define SLC_HOST_STATE4 0x000000FF
++#define SLC_HOST_STATE4_S 0
++
++#define SLC_HOST_CONF_W0                     (REG_SLC_HOST_BASE + 0x14)
++#define SLC_HOST_CONF3 0x000000FF
++#define SLC_HOST_CONF3_S 24
++#define SLC_HOST_CONF2 0x000000FF
++#define SLC_HOST_CONF2_S 16
++#define SLC_HOST_CONF1 0x000000FF
++#define SLC_HOST_CONF1_S 8
++#define SLC_HOST_CONF0 0x000000FF
++#define SLC_HOST_CONF0_S 0
++
++#define SLC_HOST_CONF_W1                     (REG_SLC_HOST_BASE + 0x18)
++#define SLC_HOST_CONF7 0x000000FF
++#define SLC_HOST_CONF7_S 24
++#define SLC_HOST_CONF6 0x000000FF
++#define SLC_HOST_CONF6_S 16
++#define SLC_HOST_CONF5 0x000000FF
++#define SLC_HOST_CONF5_S 8
++#define SLC_HOST_CONF4 0x000000FF
++#define SLC_HOST_CONF4_S 0
++
++#define SLC_HOST_INT_ST                      (REG_SLC_HOST_BASE + 0x1C)
++#define SLC_HOST_RX_ST (BIT(23))
++#define SLC_HOST_EXT_BIT3_INT_ST (BIT(22))
++#define SLC_HOST_EXT_BIT2_INT_ST (BIT(21))
++#define SLC_HOST_EXT_BIT1_INT_ST (BIT(20))
++#define SLC_HOST_RXFIFO_NOT_EMPTY_INT_ST (BIT(19))
++#define SLC_HOST_RX_PF_VALID_INT_ST (BIT(18))
++#define SLC_HOST_TX_OVF_INT_ST (BIT(17))
++#define SLC_HOST_RX_UDF_INT_ST (BIT(16))
++#define SLC_HOST_TX_START_INT_ST (BIT(15))
++#define SLC_HOST_RX_START_INT_ST (BIT(14))
++#define SLC_HOST_RX_EOF_INT_ST (BIT(13))
++#define SLC_HOST_RX_SOF_INT_ST (BIT(12))
++#define SLC_HOST_TOKEN1_0TO1_INT_ST (BIT(11))
++#define SLC_HOST_TOKEN0_0TO1_INT_ST (BIT(10))
++#define SLC_HOST_TOKEN1_1TO0_INT_ST (BIT(9))
++#define SLC_HOST_TOKEN0_1TO0_INT_ST (BIT(8))
++#define SLC_HOST_TOHOST_BIT7_INT_ST (BIT(7))
++#define SLC_HOST_TOHOST_BIT6_INT_ST (BIT(6))
++#define SLC_HOST_TOHOST_BIT5_INT_ST (BIT(5))
++#define SLC_HOST_TOHOST_BIT4_INT_ST (BIT(4))
++#define SLC_HOST_TOHOST_BIT3_INT_ST (BIT(3))
++#define SLC_HOST_TOHOST_BIT2_INT_ST (BIT(2))
++#define SLC_HOST_TOHOST_BIT1_INT_ST (BIT(1))
++#define SLC_HOST_TOHOST_BIT0_INT_ST (BIT(0))
++
++#define SLC_HOST_CONF_W2                     (REG_SLC_HOST_BASE + 0x20)
++#define SLC_HOST_CONF11 0x000000FF
++#define SLC_HOST_CONF11_S 24
++#define SLC_HOST_CONF10 0x000000FF
++#define SLC_HOST_CONF10_S 16
++#define SLC_HOST_CONF9 0x000000FF
++#define SLC_HOST_CONF9_S 8
++#define SLC_HOST_CONF8 0x000000FF
++#define SLC_HOST_CONF8_S 0
++
++#define SLC_HOST_CONF_W3                     (REG_SLC_HOST_BASE + 0x24)
++#define SLC_HOST_CONF15 0x000000FF
++#define SLC_HOST_CONF15_S 24
++#define SLC_HOST_CONF14 0x000000FF
++#define SLC_HOST_CONF14_S 16
++#define SLC_HOST_CONF13 0x000000FF
++#define SLC_HOST_CONF13_S 8
++#define SLC_HOST_CONF12 0x000000FF
++#define SLC_HOST_CONF12_S 0
++
++#define SLC_HOST_GEN_TXDONE_INT  BIT(16)
++#define SLC_HOST_GEN_RXDONE_INT  BIT(17)
++
++#define SLC_HOST_CONF_W4                     (REG_SLC_HOST_BASE + 0x28)
++#define SLC_HOST_CONF19 0x000000FF
++#define SLC_HOST_CONF19_S 24
++#define SLC_HOST_CONF18 0x000000FF
++#define SLC_HOST_CONF18_S 16
++#define SLC_HOST_CONF17 0x000000FF
++#define SLC_HOST_CONF17_S 8
++#define SLC_HOST_CONF16 0x000000FF
++#define SLC_HOST_CONF16_S 0
++
++#define SLC_HOST_TOKEN_WDATA                 (REG_SLC_HOST_BASE + 0x2C)
++#define SLC_HOST_TOKEN1_WD 0x00000FFF
++#define SLC_HOST_TOKEN1_WD_S 16
++#define SLC_HOST_TOKEN0_WD 0x00000FFF
++#define SLC_HOST_TOKEN0_WD_S 0
++
++#define SLC_HOST_INT_CLR                     (REG_SLC_HOST_BASE + 0x30)
++#define SLC_HOST_TOKEN1_WR (BIT(31))
++#define SLC_HOST_TOKEN0_WR (BIT(30))
++#define SLC_HOST_TOKEN1_DEC (BIT(29))
++#define SLC_HOST_TOKEN0_DEC (BIT(28))
++#define SLC_HOST_EXT_BIT3_INT_CLR (BIT(22))
++#define SLC_HOST_EXT_BIT2_INT_CLR (BIT(21))
++#define SLC_HOST_EXT_BIT1_INT_CLR (BIT(20))
++#define SLC_HOST_EXT_BIT0_INT_CLR (BIT(19))
++#define SLC_HOST_RX_PF_VALID_INT_CLR (BIT(18))
++#define SLC_HOST_TX_OVF_INT_CLR (BIT(17))
++#define SLC_HOST_RX_UDF_INT_CLR (BIT(16))
++#define SLC_HOST_TX_START_INT_CLR (BIT(15))
++#define SLC_HOST_RX_START_INT_CLR (BIT(14))
++#define SLC_HOST_RX_EOF_INT_CLR (BIT(13))
++#define SLC_HOST_RX_SOF_INT_CLR (BIT(12))
++#define SLC_HOST_TOKEN1_0TO1_INT_CLR (BIT(11))
++#define SLC_HOST_TOKEN0_0TO1_INT_CLR (BIT(10))
++#define SLC_HOST_TOKEN1_1TO0_INT_CLR (BIT(9))
++#define SLC_HOST_TOKEN0_1TO0_INT_CLR (BIT(8))
++#define SLC_HOST_TOHOST_BIT7_INT_CLR (BIT(7))
++#define SLC_HOST_TOHOST_BIT6_INT_CLR (BIT(6))
++#define SLC_HOST_TOHOST_BIT5_INT_CLR (BIT(5))
++#define SLC_HOST_TOHOST_BIT4_INT_CLR (BIT(4))
++#define SLC_HOST_TOHOST_BIT3_INT_CLR (BIT(3))
++#define SLC_HOST_TOHOST_BIT2_INT_CLR (BIT(2))
++#define SLC_HOST_TOHOST_BIT1_INT_CLR (BIT(1))
++#define SLC_HOST_TOHOST_BIT0_INT_CLR (BIT(0))
++
++#define SLC_HOST_INT_ENA                     (REG_SLC_HOST_BASE + 0x34)
++#define SLC_HOST_EXT_BIT3_INT_ENA (BIT(22))
++#define SLC_HOST_EXT_BIT2_INT_ENA (BIT(21))
++#define SLC_HOST_EXT_BIT1_INT_ENA (BIT(20))
++#define SLC_HOST_EXT_BIT0_INT_ENA (BIT(19))
++#define SLC_HOST_RX_PF_VALID_INT_ENA (BIT(18))
++#define SLC_HOST_TX_OVF_INT_ENA (BIT(17))
++#define SLC_HOST_RX_UDF_INT_ENA (BIT(16))
++#define SLC_HOST_TX_START_INT_ENA (BIT(15))
++#define SLC_HOST_RX_START_INT_ENA (BIT(14))
++#define SLC_HOST_RX_EOF_INT_ENA (BIT(13))
++#define SLC_HOST_RX_SOF_INT_ENA (BIT(12))
++#define SLC_HOST_TOKEN1_0TO1_INT_ENA (BIT(11))
++#define SLC_HOST_TOKEN0_0TO1_INT_ENA (BIT(10))
++#define SLC_HOST_TOKEN1_1TO0_INT_ENA (BIT(9))
++#define SLC_HOST_TOKEN0_1TO0_INT_ENA (BIT(8))
++#define SLC_HOST_TOHOST_BIT7_INT_ENA (BIT(7))
++#define SLC_HOST_TOHOST_BIT6_INT_ENA (BIT(6))
++#define SLC_HOST_TOHOST_BIT5_INT_ENA (BIT(5))
++#define SLC_HOST_TOHOST_BIT4_INT_ENA (BIT(4))
++#define SLC_HOST_TOHOST_BIT3_INT_ENA (BIT(3))
++#define SLC_HOST_TOHOST_BIT2_INT_ENA (BIT(2))
++#define SLC_HOST_TOHOST_BIT1_INT_ENA (BIT(1))
++#define SLC_HOST_TOHOST_BIT0_INT_ENA (BIT(0))
++
++#define SLC_HOST_CONF_W5                     (REG_SLC_HOST_BASE + 0x3C)
++#define SLC_HOST_CONF23 0x000000FF
++#define SLC_HOST_CONF23_S 24
++#define SLC_HOST_CONF22 0x000000FF
++#define SLC_HOST_CONF22_S 16
++#define SLC_HOST_CONF21 0x000000FF
++#define SLC_HOST_CONF21_S 8
++#define SLC_HOST_CONF20 0x000000FF
++#define SLC_HOST_CONF20_S 0
++
++#define SLC_HOST_WIN_CMD                     (REG_SLC_HOST_BASE + 0x40)
++
++
++#define SLC_HOST_DATE                         (REG_SLC_HOST_BASE + 0x78)
++#define SLC_HOST_ID                           (REG_SLC_HOST_BASE + 0x7C)
++
++#define SLC_ADDR_WINDOW_CLEAR_MASK   (~(0xf<<12))
++#define SLC_FROM_HOST_ADDR_WINDOW  (0x1<<12)
++#define SLC_TO_HOST_ADDR_WINDOW    (0x3<<12)
++
++#define SLC_SET_FROM_HOST_ADDR_WINDOW(v)   do { \
++        (v) &= 0xffff;    \
++	(v) &= SLC_ADDR_WINDOW_CLEAR_MASK; \
++	(v) |= SLC_FROM_HOST_ADDR_WINDOW; \
++} while (0);
++
++#define SLC_SET_TO_HOST_ADDR_WINDOW(v)   do { \
++        (v) &= 0xffff;    \
++	(v) &= SLC_ADDR_WINDOW_CLEAR_MASK; \
++	(v) |= SLC_TO_HOST_ADDR_WINDOW; \
++} while (0);
++
++#define SLC_INT_ENA                     	(REG_SLC_BASE + 0xC)
++#define SLC_RX_EOF_INT_ENA BIT(17)
++#define SLC_FRHOST_BIT2_INT_ENA BIT(2)
++
++#define SLC_RX_LINK                     	(REG_SLC_BASE + 0x24)
++#define SLC_RXLINK_START BIT(29)
++
++#define SLC_BRIDGE_CONF                     	(REG_SLC_BASE + 0x44)
++#define SLC_TX_PUSH_IDLE_NUM 0xFFFF
++#define SLC_TX_PUSH_IDLE_NUM_S 16
++#define SLC_HDA_MAP_128K BIT(13)
++#define SLC_TX_DUMMY_MODE BIT(12)
++#define SLC_FIFO_MAP_ENA 0x0000000F
++#define SLC_FIFO_MAP_ENA_S 8
++#define SLC_TXEOF_ENA 0x0000003F
++#define SLC_TXEOF_ENA_S
++
++
++#endif				// SLC_HOST_REGISTER_H_INCLUDED
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-driver-ssv6051.patch b/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-driver-ssv6051.patch
new file mode 100644
index 000000000000..ed72e2aa1320
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.armbian/wifi-driver-ssv6051.patch
@@ -0,0 +1,49482 @@
+From 3f30a652fb3e6ead83f65312d0240d5c9ea8c340 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Wed, 2 Nov 2022 15:40:06 +0000
+Subject: [PATCH] add ssv6xxx wifi driver
+
+---
+ drivers/net/wireless/Kconfig                  |     1 +
+ drivers/net/wireless/Makefile                 |     1 +
+ drivers/net/wireless/ssv6051/Kconfig          |    11 +
+ drivers/net/wireless/ssv6051/Makefile         |    26 +
+ drivers/net/wireless/ssv6051/Makefile.bak     |   107 +
+ .../ssv6051/firmware/ssv6051-wifi.cfg         |    91 +
+ drivers/net/wireless/ssv6051/hci/hctrl.h      |   178 +
+ drivers/net/wireless/ssv6051/hci/ssv_hci.c    |   967 +
+ drivers/net/wireless/ssv6051/hci/ssv_hci.h    |    77 +
+ drivers/net/wireless/ssv6051/hwif/hwif.h      |    84 +
+ drivers/net/wireless/ssv6051/hwif/sdio/sdio.c |  1254 ++
+ .../net/wireless/ssv6051/hwif/sdio/sdio_def.h |    80 +
+ drivers/net/wireless/ssv6051/include/cabrio.h |    28 +
+ .../net/wireless/ssv6051/include/ssv6200.h    |    76 +
+ .../wireless/ssv6051/include/ssv6200_aux.h    | 18221 ++++++++++++++++
+ .../wireless/ssv6051/include/ssv6200_common.h |   452 +
+ .../ssv6051/include/ssv6200_configuration.h   |   317 +
+ .../wireless/ssv6051/include/ssv6200_reg.h    |  9694 ++++++++
+ .../ssv6051/include/ssv6200_reg_sim.h         |   176 +
+ .../net/wireless/ssv6051/include/ssv_cfg.h    |    60 +
+ .../ssv6051/include/ssv_firmware_version.h    |    25 +
+ .../wireless/ssv6051/include/ssv_version.h    |    12 +
+ .../net/wireless/ssv6051/platform-config.mak  |    97 +
+ drivers/net/wireless/ssv6051/rules.mak        |    19 +
+ drivers/net/wireless/ssv6051/smac/ampdu.c     |  2111 ++
+ drivers/net/wireless/ssv6051/smac/ampdu.h     |   215 +
+ drivers/net/wireless/ssv6051/smac/ap.c        |   598 +
+ drivers/net/wireless/ssv6051/smac/ap.h        |    41 +
+ drivers/net/wireless/ssv6051/smac/dev.c       |  3880 ++++
+ drivers/net/wireless/ssv6051/smac/dev.h       |   445 +
+ drivers/net/wireless/ssv6051/smac/dev_tbl.h   |   141 +
+ drivers/net/wireless/ssv6051/smac/drv_comm.h  |    61 +
+ drivers/net/wireless/ssv6051/smac/efuse.c     |   334 +
+ drivers/net/wireless/ssv6051/smac/efuse.h     |    40 +
+ drivers/net/wireless/ssv6051/smac/init.c      |  1347 ++
+ drivers/net/wireless/ssv6051/smac/init.h      |    23 +
+ drivers/net/wireless/ssv6051/smac/lib.c       |    33 +
+ drivers/net/wireless/ssv6051/smac/lib.h       |    23 +
+ .../net/wireless/ssv6051/smac/linux_80211.h   |    24 +
+ drivers/net/wireless/ssv6051/smac/p2p.c       |   305 +
+ drivers/net/wireless/ssv6051/smac/p2p.h       |    58 +
+ drivers/net/wireless/ssv6051/smac/sar.c       |   208 +
+ drivers/net/wireless/ssv6051/smac/sar.h       |    63 +
+ drivers/net/wireless/ssv6051/smac/sec.h       |    52 +
+ drivers/net/wireless/ssv6051/smac/smartlink.c |   340 +
+ .../wireless/ssv6051/smac/ssv6xxx_debugfs.c   |   223 +
+ .../wireless/ssv6051/smac/ssv6xxx_debugfs.h   |    27 +
+ .../net/wireless/ssv6051/smac/ssv_cfgvendor.c |  1384 ++
+ .../net/wireless/ssv6051/smac/ssv_cfgvendor.h |   247 +
+ drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c |   546 +
+ drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h |    31 +
+ drivers/net/wireless/ssv6051/smac/ssv_pm.c    |    19 +
+ drivers/net/wireless/ssv6051/smac/ssv_pm.h    |    20 +
+ drivers/net/wireless/ssv6051/smac/ssv_rc.c    |  1716 ++
+ drivers/net/wireless/ssv6051/smac/ssv_rc.h    |    50 +
+ .../net/wireless/ssv6051/smac/ssv_rc_common.h |   175 +
+ .../wireless/ssv6051/ssv6051-generic-wlan.c   |    76 +
+ .../net/wireless/ssv6051/ssvdevice/ssv_cmd.c  |  1765 ++
+ .../net/wireless/ssv6051/ssvdevice/ssv_cmd.h  |    50 +
+ .../wireless/ssv6051/ssvdevice/ssvdevice.c    |   256 +
+ 60 files changed, 48983 insertions(+)
+ create mode 100644 drivers/net/wireless/ssv6051/Kconfig
+ create mode 100644 drivers/net/wireless/ssv6051/Makefile
+ create mode 100644 drivers/net/wireless/ssv6051/Makefile.bak
+ create mode 100644 drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
+ create mode 100644 drivers/net/wireless/ssv6051/hci/hctrl.h
+ create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.c
+ create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.h
+ create mode 100644 drivers/net/wireless/ssv6051/hwif/hwif.h
+ create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
+ create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/cabrio.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_aux.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_common.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv_cfg.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv_version.h
+ create mode 100644 drivers/net/wireless/ssv6051/platform-config.mak
+ create mode 100644 drivers/net/wireless/ssv6051/rules.mak
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ap.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ap.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/dev.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/dev.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/dev_tbl.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/drv_comm.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/init.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/init.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/lib.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/lib.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/linux_80211.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/sar.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/sar.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/sec.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/smartlink.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
+ create mode 100644 drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
+ create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
+ create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
+ create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
+
+diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
+index de5e37846397..aa2cac9abdd3 100644
+--- a/drivers/net/wireless/Kconfig
++++ b/drivers/net/wireless/Kconfig
+@@ -18,6 +18,7 @@ menuconfig WLAN
+ 
+ if WLAN
+ 
++source "drivers/net/wireless/ssv6051/Kconfig"
+ source "drivers/net/wireless/admtek/Kconfig"
+ source "drivers/net/wireless/ath/Kconfig"
+ source "drivers/net/wireless/atmel/Kconfig"
+diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
+index 92ffd2cef51c..8b56a42e97a6 100644
+--- a/drivers/net/wireless/Makefile
++++ b/drivers/net/wireless/Makefile
+@@ -3,6 +3,7 @@
+ # Makefile for the Linux Wireless network device drivers.
+ #
+ 
++obj-$(CONFIG_SSV6051) += ssv6051/
+ obj-$(CONFIG_WLAN_VENDOR_ADMTEK) += admtek/
+ obj-$(CONFIG_WLAN_VENDOR_ATH) += ath/
+ obj-$(CONFIG_WLAN_VENDOR_ATMEL) += atmel/
+diff --git a/drivers/net/wireless/ssv6051/Kconfig b/drivers/net/wireless/ssv6051/Kconfig
+new file mode 100644
+index 000000000000..7706ad52ed7b
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/Kconfig
+@@ -0,0 +1,11 @@
++# SPDX-License-Identifier: GPL-2.0-only
++config SSV6051
++        tristate "South Silicon Valley (ssv) 6051 family WLAN support"
++	depends on MAC80211
++	depends on (MMC = y)
++        default n
++	select FW_LOADER
++        help
++		Enable South Silicon Valley (SSV) 6051 family support.
++
++
+diff --git a/drivers/net/wireless/ssv6051/Makefile b/drivers/net/wireless/ssv6051/Makefile
+new file mode 100644
+index 000000000000..985d730f3d50
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/Makefile
+@@ -0,0 +1,26 @@
++# SPDX-License-Identifier: ISC
++
++include $(src)/platform-config.mak
++
++ccflags-y += \
++	-I $(srctree)/$(src) \
++        -I $(srctree)/$(src)/include
++
++obj-$(CONFIG_SSV6051) += ssv6051.o
++ssv6051-objs += \
++	ssv6051-generic-wlan.o \
++	ssvdevice/ssvdevice.o \
++	ssvdevice/ssv_cmd.o \
++	hci/ssv_hci.o \
++	smac/init.o \
++	smac/dev.o \
++	smac/ssv_rc.o \
++	smac/ssv_ht_rc.o \
++	smac/ap.o \
++	smac/ampdu.o \
++	smac/efuse.o \
++	smac/ssv_pm.o \
++	smac/sar.o \
++	smac/ssv_cfgvendor.o \
++	hwif/sdio/sdio.o
++
+diff --git a/drivers/net/wireless/ssv6051/Makefile.bak b/drivers/net/wireless/ssv6051/Makefile.bak
+new file mode 100644
+index 000000000000..2733fa4dd3b7
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/Makefile.bak
+@@ -0,0 +1,107 @@
++KMODULE_NAME=ssv6051
++
++KBUILD_TOP := $(PWD)
++
++ifeq ($(KERNELRELEASE),)
++
++KVERS_UNAME ?= $(shell uname -r)
++KVERS_ARCH ?= $(shell arch)
++
++KBUILD ?= $(shell readlink -f /lib/modules/$(KVERS_UNAME)/build)
++
++ifeq (,$(KBUILD))
++$(error kernel build tree not found - set KBUILD to configured kernel)
++endif
++
++#KCONFIG := $(KBUILD)/config
++#ifeq (,$(wildcard $(KCONFIG)))
++#$(error No .config found in $(KBUILD), set KBUILD to configured kernel)
++#endif
++
++ifneq (,$(wildcard $(KBUILD)/include/linux/version.h))
++ifneq (,$(wildcard $(KBUILD)/include/generated/uapi/linux/version.h))
++$(error Multiple copied of version.h found, clean build tree)
++endif
++endif
++
++# Kernel Makefile doesn't always know the exact kernel version, so we
++# get it from the kernel headers instead and pass it to make.
++VERSION_H := $(KBUILD)/include/generated/utsrelease.h
++ifeq (,$(wildcard $(VERSION_H)))
++VERSION_H := $(KBUILD)/include/linux/utsrelease.h
++endif
++ifeq (,$(wildcard $(VERSION_H)))
++VERSION_H := $(KBUILD)/include/linux/version.h
++endif
++ifeq (,$(wildcard $(VERSION_H)))
++$(error Please run 'make modules_prepare' in $(KBUILD))
++endif
++
++KVERS := $(shell sed -ne 's/"//g;s/^\#define UTS_RELEASE //p' $(VERSION_H))
++
++ifeq (,$(KVERS))
++$(error Cannot find UTS_RELEASE in $(VERSION_H), please report)
++endif
++
++INST_DIR = /lib/modules/$(KVERS)/misc
++
++#include $(KCONFIG)
++
++endif
++
++include $(KBUILD_TOP)/platform-config.mak
++
++EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include #-Wno-error=missing-attributes
++DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
++
++OBJS := ssvdevice/ssvdevice.c \
++	ssvdevice/ssv_cmd.c \
++	hci/ssv_hci.c \
++	smac/init.c \
++	smac/dev.c \
++	smac/ssv_rc.c \
++	smac/ssv_ht_rc.c \
++	smac/ap.c \
++	smac/ampdu.c \
++	smac/efuse.c \
++	smac/ssv_pm.c \
++	smac/sar.c \
++	hwif/sdio/sdio.c \
++	ssv6051-generic-wlan.c
++
++ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
++OBJS +=	smac/ssv6xxx_debugfs.c
++endif
++
++ifeq ($(findstring -DCONFIG_SSV_VENDOR_EXT_SUPPORT, $(ccflags-y)), -DCONFIG_SSV_VENDOR_EXT_SUPPORT)
++OBJS +=	smac/ssv_cfgvendor.c
++endif
++
++ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
++OBJS += smac/smartlink.c
++endif
++
++$(KMODULE_NAME)-y += $(ASMS:.S=.o)
++$(KMODULE_NAME)-y += $(OBJS:.c=.o)
++
++obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
++
++all: modules
++
++modules:
++	ARCH=arm $(MAKE) -C $(KBUILD) M=$(KBUILD_TOP)
++
++clean:
++	find -type f -iname '*.o' -exec rm {} \;
++	find -type f -iname '*.o.cmd' -exec rm {} \;
++	rm -f *.o *.ko .*.cmd *.mod.c *.symvers modules.order
++	rm -rf .tmp_versions
++
++install: modules
++	mkdir -p -m 755 $(DESTDIR)$(INST_DIR)
++	install -m 0644 $(KMODULE_NAME).ko $(DESTDIR)$(INST_DIR)
++ifndef DESTDIR
++	-/sbin/depmod -a $(KVERS)
++endif
++
++.PHONY: all modules clean install
+diff --git a/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
+new file mode 100644
+index 000000000000..c072960f6dea
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
+@@ -0,0 +1,91 @@
++############################################################
++# ROCKCHIP RK3X28 & RK322X
++# WIFI-CONFIGURATION
++##################################################
++
++##################################################
++# Firmware setting
++# Priority.1 insmod parameter "cfgfirmwarepath"
++# Priority.2 firmware_path
++# Priority.3 default firmware
++##################################################
++firmware_path = /vendor/etc/firmware/
++
++############################################################
++# MAC address
++#
++# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
++#
++# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
++#
++# Priority 3. From insert module parameter
++#
++# Priority 4. From external file path
++#   path only support some special charater "_" ":" "/" "." "-"
++#
++# Priority 5. Default[Software mode]
++#
++#   0. => 00:33:33:33:33:33
++#   1. => Always random
++#   2. => First random and write to file[Default path mac_output_path]
++#
++############################################################
++ignore_efuse_mac = 0
++#mac_address_path = /xxxx/xxxx
++mac_address_mode = 2
++mac_output_path = /data/wifimac
++
++##################################################
++# Hardware setting
++#
++#volt regulator(DCDC-0 LDO-1)
++#
++##################################################
++xtal_clock = 24
++volt_regulator = 1
++
++##################################################
++# Default channel after wifi on
++# value range: [1 ~ 14]
++##################################################
++def_chan = 6
++##################################################
++# Hardware Capability Settings:
++##################################################
++hw_cap_ht = on
++hw_cap_gf = off
++hw_cap_2ghz = on
++hw_cap_5ghz = off
++hw_cap_security = on
++hw_cap_sgi_20 = on
++hw_cap_sgi_40 = off
++hw_cap_ap = on
++hw_cap_p2p = on
++hw_cap_ampdu_rx = on
++hw_cap_ampdu_tx = on
++use_wpa2_only = 1
++##################################################
++# TX power level setting [0-14]
++# The larger the number the smaller the TX power
++# 0 - The maximum power
++# 1 level = -0.5db
++#
++# 6051Z .. 4 or 4
++# 6051Q .. 2 or 5
++# 6051P .. 0 or 0
++#
++##################################################
++#wifi_tx_gain_level_b = 2
++#wifi_tx_gain_level_gn = 5
++################################################
++# Signal strength control
++# rssi control
++#rssi_ctl = 10
++
++
++##################################################
++# Import extenal configuration(UP to 64 groups)
++# example:
++#    register = CE010010:91919191
++#    register = 00CC0010:00091919
++##################################################
+diff --git a/drivers/net/wireless/ssv6051/hci/hctrl.h b/drivers/net/wireless/ssv6051/hci/hctrl.h
+new file mode 100644
+index 000000000000..95218c8040e7
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hci/hctrl.h
+@@ -0,0 +1,178 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _HCTRL_H_
++#define _HCTRL_H_
++#define MAX_FRAME_SIZE 4096
++#define SSV6XXX_INT_RX 0x00000001
++#define SSV6XXX_INT_TX 0x00000002
++#define SSV6XXX_INT_SOC 0x00000004
++#define SSV6XXX_INT_LOW_EDCA_0 0x00000008
++#define SSV6XXX_INT_LOW_EDCA_1 0x00000010
++#define SSV6XXX_INT_LOW_EDCA_2 0x00000020
++#define SSV6XXX_INT_LOW_EDCA_3 0x00000040
++#define SSV6XXX_INT_RESOURCE_LOW 0x00000080
++#define IFDEV(_ct) ((_ct)->shi->dev)
++#define IFOPS(_ct) ((_ct)->shi->if_ops)
++#define HCI_REG_READ(_ct,_adr,_val) IFOPS(_ct)->readreg(IFDEV(_ct), _adr, _val)
++#define HCI_REG_WRITE(_ct,_adr,_val) IFOPS(_ct)->writereg(IFDEV(_ct), _adr, _val)
++#define HCI_REG_SET_BITS(_ct,_reg,_set,_clr) \
++{ \
++    u32 _regval; \
++    if(HCI_REG_READ(_ct, _reg, &_regval)); \
++    _regval &= ~(_clr); \
++    _regval |= (_set); \
++    if(HCI_REG_WRITE(_ct, _reg, _regval)); \
++}
++#define IF_SEND(_ct,_bf,_len,_qid) IFOPS(_ct)->write(IFDEV(_ct), _bf, _len, _qid)
++#define IF_RECV(ct,bf,len) IFOPS(ct)->read(IFDEV(ct), bf, len)
++#define HCI_LOAD_FW(ct,_bf,open) IFOPS(ct)->load_fw(IFDEV(ct), _bf, open)
++#define HCI_IFC_RESET(ct) IFOPS(ct)->interface_reset(IFDEV(ct))
++struct ssv6xxx_hci_ctrl {
++	struct ssv6xxx_hci_info *shi;
++	spinlock_t int_lock;
++	u32 int_status;
++	u32 int_mask;
++	struct mutex txq_mask_lock;
++	u32 txq_mask;
++	struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];
++	struct mutex hci_mutex;
++	bool hci_start;
++	struct sk_buff *rx_buf;
++	u32 rx_pkt;
++	struct workqueue_struct *hci_work_queue;
++	struct work_struct hci_rx_work;
++	struct work_struct hci_tx_work;
++	u32 read_rs0_info_fail;
++	u32 read_rs1_info_fail;
++	u32 rx_work_running;
++	u32 isr_running;
++	u32 xmit_running;
++	u32 isr_summary_eable;
++	u32 isr_routine_time;
++	u32 isr_tx_time;
++	u32 isr_rx_time;
++	u32 isr_idle_time;
++	u32 isr_rx_idle_time;
++	u32 isr_miss_cnt;
++	unsigned long prev_isr_jiffes;
++	unsigned long prev_rx_isr_jiffes;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++	u32 isr_mib_enable;
++	u32 isr_mib_reset;
++	long long isr_total_time;
++	long long isr_tx_io_time;
++	long long isr_rx_io_time;
++	u32 isr_rx_io_count;
++	u32 isr_tx_io_count;
++	long long isr_rx_proc_time;
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++	bool irq_enable;
++	u32 irq_count;
++	u32 invalid_irq_count;
++	u32 tx_irq_count;
++	u32 real_tx_irq_count;
++	u32 rx_irq_count;
++	u32 irq_rx_pkt_count;
++	u32 irq_tx_pkt_count;
++#endif
++#endif
++};
++struct ssv6xxx_hci_txq_info {
++	u32 tx_use_page:8;
++	u32 tx_use_id:6;
++	u32 txq0_size:4;
++	u32 txq1_size:4;
++	u32 txq2_size:5;
++	u32 txq3_size:5;
++};
++struct ssv6xxx_hci_txq_info2 {
++	u32 tx_use_page:9;
++	u32 tx_use_id:8;
++	u32 txq4_size:4;
++	u32 rsvd:11;
++};
++struct ssv6xxx_hw_resource {
++	u32 free_tx_page;
++	u32 free_tx_id;
++	int max_tx_frame[SSV_HW_TXQ_NUM];
++};
++static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl,
++					    irq_handler_t irq_handler)
++{
++	if (hctrl->shi->if_ops->irq_request)
++		hctrl->shi->if_ops->irq_request(IFDEV(hctrl), irq_handler,
++						hctrl);
++}
++
++static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->irq_enable)
++		hctrl->shi->if_ops->irq_enable(IFDEV(hctrl));
++}
++
++static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->irq_disable)
++		hctrl->shi->if_ops->irq_disable(IFDEV(hctrl), false);
++}
++
++static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl,
++					     int *status)
++{
++	if (hctrl->shi->if_ops->irq_getstatus)
++		return hctrl->shi->if_ops->irq_getstatus(IFDEV(hctrl), status);
++	return 0;
++}
++
++static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl,
++					    int mask)
++{
++	if (hctrl->shi->if_ops->irq_setmask)
++		hctrl->shi->if_ops->irq_setmask(IFDEV(hctrl), mask);
++}
++
++static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->irq_trigger)
++		hctrl->shi->if_ops->irq_trigger(IFDEV(hctrl));
++}
++
++static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->pmu_wakeup)
++		hctrl->shi->if_ops->pmu_wakeup(IFDEV(hctrl));
++}
++
++static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl,
++					  u32 addr, u8 * data, u32 size)
++{
++	if (hctrl->shi->if_ops->write_sram)
++		return hctrl->shi->if_ops->write_sram(IFDEV(hctrl), addr, data,
++						      size);
++	return 0;
++}
++
++#define HCI_IRQ_REQUEST(ct,hdle) ssv6xxx_hwif_irq_request(ct, hdle)
++#define HCI_IRQ_ENABLE(ct) ssv6xxx_hwif_irq_enable(ct)
++#define HCI_IRQ_DISABLE(ct) ssv6xxx_hwif_irq_disable(ct)
++#define HCI_IRQ_STATUS(ct,sts) ssv6xxx_hwif_irq_getstatus(ct, sts)
++#define HCI_IRQ_SET_MASK(ct,mk) ssv6xxx_hwif_irq_setmask(ct, mk)
++#define HCI_IRQ_TRIGGER(ct) ssv6xxx_hwif_irq_trigger(ct)
++#define HCI_PMU_WAKEUP(ct) ssv6xxx_hwif_pmu_wakeup(ct)
++#define HCI_SRAM_WRITE(_ct,_adr,_dat,_size) ssv6xxx_hwif_write_sram(_ct, _adr, _dat, _size);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.c b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
+new file mode 100644
+index 000000000000..9fedbeb55754
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
+@@ -0,0 +1,967 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/jiffies.h>
++#include <ssv6200.h>
++#include "hctrl.h"
++
++static struct ssv6xxx_hci_ctrl *ctrl_hci = NULL;
++
++struct sk_buff *ssv_skb_alloc(s32 len)
++{
++	struct sk_buff *skb;
++	skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
++	if (skb != NULL) {
++		skb_reserve(skb, SSV_SKB_info_size);
++	}
++	return skb;
++}
++
++void ssv_skb_free(struct sk_buff *skb)
++{
++	dev_kfree_skb_any(skb);
++}
++
++static int ssv6xxx_hci_irq_enable(void)
++{
++	HCI_IRQ_SET_MASK(ctrl_hci, ~(ctrl_hci->int_mask));
++	HCI_IRQ_ENABLE(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_irq_disable(void)
++{
++	HCI_IRQ_SET_MASK(ctrl_hci, 0xffffffff);
++	HCI_IRQ_DISABLE(ctrl_hci);
++	return 0;
++}
++
++static void ssv6xxx_hci_irq_register(u32 irq_mask)
++{
++	unsigned long flags;
++	u32 regval;
++	mutex_lock(&ctrl_hci->hci_mutex);
++	spin_lock_irqsave(&ctrl_hci->int_lock, flags);
++	ctrl_hci->int_mask |= irq_mask;
++	regval = ~ctrl_hci->int_mask;
++	spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++	smp_mb();
++	HCI_IRQ_SET_MASK(ctrl_hci, regval);
++	mutex_unlock(&ctrl_hci->hci_mutex);
++}
++
++static inline u32 ssv6xxx_hci_get_int_bitno(int txqid)
++{
++	if (txqid == SSV_HW_TXQ_NUM - 1)
++		return 1;
++	else
++		return txqid + 3;
++}
++
++static int ssv6xxx_hci_start(void)
++{
++	ssv6xxx_hci_irq_enable();
++	ctrl_hci->hci_start = true;
++	HCI_IRQ_TRIGGER(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_stop(void)
++{
++	ssv6xxx_hci_irq_disable();
++	ctrl_hci->hci_start = false;
++	return 0;
++}
++
++static int ssv6xxx_hci_read_word(u32 addr, u32 * regval)
++{
++	int ret = HCI_REG_READ(ctrl_hci, addr, regval);
++	return ret;
++}
++
++static int ssv6xxx_hci_write_word(u32 addr, u32 regval)
++{
++	return HCI_REG_WRITE(ctrl_hci, addr, regval);
++}
++
++static int ssv6xxx_hci_load_fw(u8 * firmware_name, u8 openfile)
++{
++	return HCI_LOAD_FW(ctrl_hci, firmware_name, openfile);
++}
++
++static int ssv6xxx_hci_write_sram(u32 addr, u8 * data, u32 size)
++{
++	return HCI_SRAM_WRITE(ctrl_hci, addr, data, size);
++}
++
++static int ssv6xxx_hci_pmu_wakeup(void)
++{
++	HCI_PMU_WAKEUP(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_interface_reset(void)
++{
++	HCI_IFC_RESET(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_send_cmd(struct sk_buff *skb)
++{
++	int ret;
++	ret = IF_SEND(ctrl_hci, (void *)skb->data, skb->len, 0);
++
++	if (ret < 0)
++		pr_warn("ssv6xxx_hci_send_cmd failed, ret=%d\n", ret);
++
++	return ret;
++}
++
++static int ssv6xxx_hci_enqueue(struct sk_buff *skb, int txqid, u32 tx_flags)
++{
++	struct ssv_hw_txq *hw_txq;
++	unsigned long flags;
++	u32 status;
++	int qlen = 0;
++	BUG_ON(txqid >= SSV_HW_TXQ_NUM || txqid < 0);
++	if (txqid >= SSV_HW_TXQ_NUM || txqid < 0)
++		return -1;
++	hw_txq = &ctrl_hci->hw_txq[txqid];
++	hw_txq->tx_flags = tx_flags;
++	if (tx_flags & HCI_FLAGS_ENQUEUE_HEAD)
++		skb_queue_head(&hw_txq->qhead, skb);
++	else
++		skb_queue_tail(&hw_txq->qhead, skb);
++	qlen = (int)skb_queue_len(&hw_txq->qhead);
++	if (!(tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
++		if (skb_queue_len(&hw_txq->qhead) >= hw_txq->max_qsize) {
++			ctrl_hci->shi->hci_tx_flow_ctrl_cb(ctrl_hci->
++							   shi->tx_fctrl_cb_args,
++							   hw_txq->txq_no, true,
++							   2000);
++		}
++	}
++
++	mutex_lock(&ctrl_hci->hci_mutex);
++	spin_lock_irqsave(&ctrl_hci->int_lock, flags);
++	status = ctrl_hci->int_mask;
++
++	if ((ctrl_hci->int_mask & SSV6XXX_INT_RESOURCE_LOW) == 0) {
++		if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) {
++			u32 regval;
++			ctrl_hci->int_mask |= SSV6XXX_INT_RESOURCE_LOW;
++			regval = ~ctrl_hci->int_mask;
++			spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++			HCI_IRQ_SET_MASK(ctrl_hci, regval);
++			mutex_unlock(&ctrl_hci->hci_mutex);
++		} else {
++			ctrl_hci->int_status |= SSV6XXX_INT_RESOURCE_LOW;
++			smp_mb();
++			spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++			mutex_unlock(&ctrl_hci->hci_mutex);
++			ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci->
++							     shi->dev);
++		}
++	} else {
++		spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++		mutex_unlock(&ctrl_hci->hci_mutex);
++	}
++
++	return qlen;
++}
++
++static bool ssv6xxx_hci_is_txq_empty(int txqid)
++{
++	struct ssv_hw_txq *hw_txq;
++	BUG_ON(txqid >= SSV_HW_TXQ_NUM);
++	if (txqid >= SSV_HW_TXQ_NUM)
++		return false;
++	hw_txq = &ctrl_hci->hw_txq[txqid];
++	if (skb_queue_len(&hw_txq->qhead) <= 0)
++		return true;
++	return false;
++}
++
++static int ssv6xxx_hci_txq_flush(u32 txq_mask)
++{
++	struct ssv_hw_txq *hw_txq;
++	struct sk_buff *skb = NULL;
++	int txqid;
++	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++		if ((txq_mask & (1 << txqid)) != 0)
++			continue;
++		hw_txq = &ctrl_hci->hw_txq[txqid];
++		while ((skb = skb_dequeue(&hw_txq->qhead))) {
++			ctrl_hci->shi->hci_tx_buf_free_cb(skb,
++							  ctrl_hci->
++							  shi->tx_buf_free_args);
++		}
++	}
++	return 0;
++}
++
++static int ssv6xxx_hci_txq_flush_by_sta(int aid)
++{
++	return 0;
++}
++
++static int ssv6xxx_hci_txq_pause(u32 txq_mask)
++{
++	struct ssv_hw_txq *hw_txq;
++	int txqid;
++	mutex_lock(&ctrl_hci->txq_mask_lock);
++	ctrl_hci->txq_mask |= (txq_mask & 0x1F);
++	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++		if ((ctrl_hci->txq_mask & (1 << txqid)) == 0)
++			continue;
++		hw_txq = &ctrl_hci->hw_txq[txqid];
++		hw_txq->paused = true;
++	}
++	HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
++			 (ctrl_hci->txq_mask << 16), (0x1F << 16));
++	mutex_unlock(&ctrl_hci->txq_mask_lock);
++	return 0;
++}
++
++static int ssv6xxx_hci_txq_resume(u32 txq_mask)
++{
++	struct ssv_hw_txq *hw_txq;
++	int txqid;
++	mutex_lock(&ctrl_hci->txq_mask_lock);
++	ctrl_hci->txq_mask &= ~(txq_mask & 0x1F);
++	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++		if ((ctrl_hci->txq_mask & (1 << txqid)) != 0)
++			continue;
++		hw_txq = &ctrl_hci->hw_txq[txqid];
++		hw_txq->paused = false;
++	}
++	HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
++			 (ctrl_hci->txq_mask << 16), (0x1F << 16));
++	mutex_unlock(&ctrl_hci->txq_mask_lock);
++	return 0;
++}
++
++static int ssv6xxx_hci_xmit(struct ssv_hw_txq *hw_txq, int max_count,
++			    struct ssv6xxx_hw_resource *phw_resource)
++{
++	struct sk_buff_head tx_cb_list;
++	struct sk_buff *skb = NULL;
++	int tx_count, ret, page_count;
++	struct ssv6200_tx_desc *tx_desc = NULL;
++	ctrl_hci->xmit_running = 1;
++	skb_queue_head_init(&tx_cb_list);
++	for (tx_count = 0; tx_count < max_count; tx_count++) {
++		if (ctrl_hci->hci_start == false) {
++			pr_debug("ssv6xxx_hci_xmit - hci_start = false\n");
++			goto xmit_out;
++		}
++		skb = skb_dequeue(&hw_txq->qhead);
++		if (!skb) {
++			pr_debug("ssv6xxx_hci_xmit - queue empty\n");
++			goto xmit_out;
++		}
++		page_count = (skb->len + SSV6200_ALLOC_RSVD);
++		if (page_count & HW_MMU_PAGE_MASK)
++			page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
++		else
++			page_count = page_count >> HW_MMU_PAGE_SHIFT;
++		if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
++			pr_err("Asking page %d(%d) exceeds resource limit %d.\n",
++			       page_count, skb->len,
++			       (SSV6200_PAGE_TX_THRESHOLD / 2));
++		if ((phw_resource->free_tx_page < page_count)
++		    || (phw_resource->free_tx_id <= 0)
++		    || (phw_resource->max_tx_frame[hw_txq->txq_no] <= 0)) {
++			skb_queue_head(&hw_txq->qhead, skb);
++			break;
++		}
++		phw_resource->free_tx_page -= page_count;
++		phw_resource->free_tx_id--;
++		phw_resource->max_tx_frame[hw_txq->txq_no]--;
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++
++		if (ctrl_hci->shi->hci_skb_update_cb != NULL
++		    && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
++			ctrl_hci->shi->hci_skb_update_cb(skb,
++							 ctrl_hci->
++							 shi->skb_update_args);
++		}
++
++		ret =
++		    IF_SEND(ctrl_hci, (void *)skb->data, skb->len,
++			    hw_txq->txq_no);
++		if (ret < 0) {
++			pr_err("ssv6xxx_hci_xmit failure\n");
++			skb_queue_head(&hw_txq->qhead, skb);
++			break;
++		}
++		if (tx_desc->reason != ID_TRAP_SW_TXTPUT)
++			skb_queue_tail(&tx_cb_list, skb);
++		else
++			ssv_skb_free(skb);
++		hw_txq->tx_pkt++;
++
++		if (!(hw_txq->tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
++			if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) {
++				ctrl_hci->shi->
++				    hci_tx_flow_ctrl_cb
++				    (ctrl_hci->shi->tx_fctrl_cb_args,
++				     hw_txq->txq_no, false, 2000);
++			}
++		}
++	}
++ xmit_out:
++	if (ctrl_hci->shi->hci_tx_cb && tx_desc
++	    && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
++		ctrl_hci->shi->hci_tx_cb(&tx_cb_list,
++					 ctrl_hci->shi->tx_cb_args);
++	}
++	ctrl_hci->xmit_running = 0;
++	return tx_count;
++}
++
++static int ssv6xxx_hci_tx_handler(void *dev, int max_count)
++{
++	struct ssv6xxx_hci_txq_info txq_info;
++	struct ssv6xxx_hci_txq_info2 txq_info2;
++	struct ssv6xxx_hw_resource hw_resource;
++	struct ssv_hw_txq *hw_txq = dev;
++	int ret, tx_count = 0;
++	max_count = skb_queue_len(&hw_txq->qhead);
++	if (max_count == 0)
++		return 0;
++	if (hw_txq->txq_no == 4) {
++		ret =
++		    HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2,
++				 (u32 *) & txq_info2);
++		if (ret < 0) {
++			ctrl_hci->read_rs1_info_fail++;
++			return 0;
++		}
++		//BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page);
++		//BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_id);
++		if (SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page)
++			return 0;
++		if (SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_page)
++			return 0;
++		hw_resource.free_tx_page =
++		    SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
++		hw_resource.free_tx_id =
++		    SSV6200_ID_TX_THRESHOLD - txq_info2.tx_use_id;
++		hw_resource.max_tx_frame[4] =
++		    SSV6200_ID_MANAGER_QUEUE - txq_info2.txq4_size;
++	} else {
++		ret =
++		    HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO,
++				 (u32 *) & txq_info);
++		if (ret < 0) {
++			ctrl_hci->read_rs0_info_fail++;
++			return 0;
++		}
++		//BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page);
++		//BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_id);
++		if (SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page)
++			return 0;
++		if (SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_page)
++			return 0;
++		hw_resource.free_tx_page =
++		    SSV6200_PAGE_TX_THRESHOLD - txq_info.tx_use_page;
++		hw_resource.free_tx_id =
++		    SSV6200_ID_TX_THRESHOLD - txq_info.tx_use_id;
++		hw_resource.max_tx_frame[0] =
++		    SSV6200_ID_AC_BK_OUT_QUEUE - txq_info.txq0_size;
++		hw_resource.max_tx_frame[1] =
++		    SSV6200_ID_AC_BE_OUT_QUEUE - txq_info.txq1_size;
++		hw_resource.max_tx_frame[2] =
++		    SSV6200_ID_AC_VI_OUT_QUEUE - txq_info.txq2_size;
++		hw_resource.max_tx_frame[3] =
++		    SSV6200_ID_AC_VO_OUT_QUEUE - txq_info.txq3_size;
++		BUG_ON(hw_resource.max_tx_frame[3] < 0);
++		BUG_ON(hw_resource.max_tx_frame[2] < 0);
++		BUG_ON(hw_resource.max_tx_frame[1] < 0);
++		BUG_ON(hw_resource.max_tx_frame[0] < 0);
++	}
++	{
++		tx_count = ssv6xxx_hci_xmit(hw_txq, max_count, &hw_resource);
++	}
++	if ((ctrl_hci->shi->hci_tx_q_empty_cb != NULL)
++	    && (skb_queue_len(&hw_txq->qhead) == 0)) {
++		ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no,
++						 ctrl_hci->
++						 shi->tx_q_empty_args);
++	}
++	return tx_count;
++}
++
++void ssv6xxx_hci_tx_work(struct work_struct *work)
++{
++	ssv6xxx_hci_irq_register(SSV6XXX_INT_RESOURCE_LOW);
++}
++
++static int _do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
++{
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	struct sk_buff_head rx_list;
++#endif
++	struct sk_buff *rx_mpdu;
++	int rx_cnt, ret = 0;
++	size_t dlen;
++	u32 status = isr_status;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
++	struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	skb_queue_head_init(&rx_list);
++#endif
++	for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&rx_io_start_time);
++#endif
++		ret = IF_RECV(hctl, hctl->rx_buf->data, &dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&rx_io_end_time);
++#endif
++		if (ret < 0 || dlen <= 0) {
++			pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
++			       __FUNCTION__, ret, (int)dlen);
++			if (ret != -84 || dlen > MAX_FRAME_SIZE)
++				break;
++		}
++		rx_mpdu = hctl->rx_buf;
++		hctl->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++		if (hctl->rx_buf == NULL) {
++			pr_err("RX buffer allocation failure!\n");
++			hctl->rx_buf = rx_mpdu;
++			break;
++		}
++		hctl->rx_pkt++;
++		skb_put(rx_mpdu, dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&rx_proc_start_time);
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++		__skb_queue_tail(&rx_list, rx_mpdu);
++#else
++		hctl->shi->hci_rx_cb(rx_mpdu, hctl->shi->rx_cb_args);
++#endif
++		HCI_IRQ_STATUS(hctl, &status);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable) {
++			getnstimeofday(&rx_proc_end_time);
++			hctl->isr_rx_io_count++;
++			rx_io_diff_time =
++			    timespec_sub(rx_io_end_time, rx_io_start_time);
++			hctl->isr_rx_io_time +=
++			    timespec_to_ns(&rx_io_diff_time);
++			rx_proc_diff_time =
++			    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++			hctl->isr_rx_proc_time +=
++			    timespec_to_ns(&rx_proc_diff_time);
++		}
++#endif
++	}
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (hctl->isr_mib_enable)
++		getnstimeofday(&rx_proc_start_time);
++#endif
++	hctl->shi->hci_rx_cb(&rx_list, hctl->shi->rx_cb_args);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (hctl->isr_mib_enable) {
++		getnstimeofday(&rx_proc_end_time);
++		rx_proc_diff_time =
++		    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++		hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
++	}
++#endif
++#endif
++	return ret;
++}
++
++static void ssv6xxx_hci_rx_work(struct work_struct *work)
++{
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	struct sk_buff_head rx_list;
++#endif
++	struct sk_buff *rx_mpdu;
++	int rx_cnt, ret;
++	size_t dlen;
++	u32 status;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
++	struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
++#endif
++	ctrl_hci->rx_work_running = 1;
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	skb_queue_head_init(&rx_list);
++#endif
++	status = SSV6XXX_INT_RX;
++	for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable)
++			getnstimeofday(&rx_io_start_time);
++#endif
++		ret = IF_RECV(ctrl_hci, ctrl_hci->rx_buf->data, &dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable)
++			getnstimeofday(&rx_io_end_time);
++#endif
++		if (ret < 0 || dlen <= 0) {
++			pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
++			       __FUNCTION__, ret, (int)dlen);
++			if (ret != -84 || dlen > MAX_FRAME_SIZE)
++				break;
++		}
++		rx_mpdu = ctrl_hci->rx_buf;
++		ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++		if (ctrl_hci->rx_buf == NULL) {
++			pr_err("RX buffer allocation failure!\n");
++			ctrl_hci->rx_buf = rx_mpdu;
++			break;
++		}
++		ctrl_hci->rx_pkt++;
++		skb_put(rx_mpdu, dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable)
++			getnstimeofday(&rx_proc_start_time);
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++		__skb_queue_tail(&rx_list, rx_mpdu);
++#else
++		ctrl_hci->shi->hci_rx_cb(rx_mpdu, ctrl_hci->shi->rx_cb_args);
++#endif
++		HCI_IRQ_STATUS(ctrl_hci, &status);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable) {
++			getnstimeofday(&rx_proc_end_time);
++			ctrl_hci->isr_rx_io_count++;
++			rx_io_diff_time =
++			    timespec_sub(rx_io_end_time, rx_io_start_time);
++			ctrl_hci->isr_rx_io_time +=
++			    timespec_to_ns(&rx_io_diff_time);
++			rx_proc_diff_time =
++			    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++			ctrl_hci->isr_rx_proc_time +=
++			    timespec_to_ns(&rx_proc_diff_time);
++		}
++#endif
++	}
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (ctrl_hci->isr_mib_enable)
++		getnstimeofday(&rx_proc_start_time);
++#endif
++	ctrl_hci->shi->hci_rx_cb(&rx_list, ctrl_hci->shi->rx_cb_args);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (ctrl_hci->isr_mib_enable) {
++		getnstimeofday(&rx_proc_end_time);
++		rx_proc_diff_time =
++		    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++		ctrl_hci->isr_rx_proc_time +=
++		    timespec_to_ns(&rx_proc_diff_time);
++	}
++#endif
++#endif
++	ctrl_hci->rx_work_running = 0;
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++static void ssv6xxx_isr_mib_reset(void)
++{
++	ctrl_hci->isr_mib_reset = 0;
++	ctrl_hci->isr_total_time = 0;
++	ctrl_hci->isr_rx_io_time = 0;
++	ctrl_hci->isr_tx_io_time = 0;
++	ctrl_hci->isr_rx_io_count = 0;
++	ctrl_hci->isr_tx_io_count = 0;
++	ctrl_hci->isr_rx_proc_time = 0;
++}
++
++static int hw_txq_len_open(struct inode *inode, struct file *filp)
++{
++	filp->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t hw_txq_len_read(struct file *filp, char __user * buffer,
++			       size_t count, loff_t * ppos)
++{
++	ssize_t ret;
++	struct ssv6xxx_hci_ctrl *hctl =
++	    (struct ssv6xxx_hci_ctrl *)filp->private_data;
++	char *summary_buf = kzalloc(1024, GFP_KERNEL);
++	char *prn_ptr = summary_buf;
++	int prt_size;
++	int buf_size = 1024;
++	int i = 0;
++	if (!summary_buf)
++		return -ENOMEM;
++	for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
++		prt_size =
++		    snprintf(prn_ptr, buf_size, "\n\rhw_txq%d_len: %d", i,
++			     skb_queue_len(&hctl->hw_txq[i].qhead));
++		prn_ptr += prt_size;
++		buf_size -= prt_size;
++	}
++	buf_size = 1024 - buf_size;
++	ret =
++	    simple_read_from_buffer(buffer, count, ppos, summary_buf, buf_size);
++	kfree(summary_buf);
++	return ret;
++}
++
++struct file_operations hw_txq_len_fops = {
++	.owner = THIS_MODULE,
++	.open = hw_txq_len_open,
++	.read = hw_txq_len_read,
++};
++
++bool ssv6xxx_hci_init_debugfs(struct dentry *dev_deugfs_dir)
++{
++	ctrl_hci->debugfs_dir = debugfs_create_dir("hci", dev_deugfs_dir);
++	if (ctrl_hci->debugfs_dir == NULL) {
++		dev_err(ctrl_hci->shi->dev,
++			"Failed to create HCI debugfs directory.\n");
++		return false;
++	}
++	debugfs_create_u32("TXQ_mask", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->txq_mask);
++	debugfs_create_u32("hci_isr_mib_enable", 00644, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_mib_enable);
++	debugfs_create_u32("hci_isr_mib_reset", 00644, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_mib_reset);
++	debugfs_create_u64("isr_total_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_total_time);
++	debugfs_create_u64("tx_io_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_tx_io_time);
++	debugfs_create_u64("rx_io_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_rx_io_time);
++	debugfs_create_u32("tx_io_count", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_tx_io_count);
++	debugfs_create_u32("rx_io_count", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_rx_io_count);
++	debugfs_create_u64("rx_proc_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_rx_proc_time);
++	debugfs_create_file("hw_txq_len", 00444, ctrl_hci->debugfs_dir,
++			    ctrl_hci, &hw_txq_len_fops);
++	return true;
++}
++
++void ssv6xxx_hci_deinit_debugfs(void)
++{
++	if (ctrl_hci->debugfs_dir == NULL)
++		return;
++	ctrl_hci->debugfs_dir = NULL;
++}
++#endif
++static int _isr_do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
++{
++	int status;
++	u32 before = jiffies;
++
++	if (hctl->isr_summary_eable && hctl->prev_rx_isr_jiffes) {
++		if (hctl->isr_rx_idle_time) {
++			hctl->isr_rx_idle_time +=
++			    (jiffies - hctl->prev_rx_isr_jiffes);
++			hctl->isr_rx_idle_time = hctl->isr_rx_idle_time >> 1;
++		} else {
++			hctl->isr_rx_idle_time +=
++			    (jiffies - hctl->prev_rx_isr_jiffes);
++		}
++	}
++	status = _do_rx(hctl, isr_status);
++	if (hctl->isr_summary_eable) {
++		if (hctl->isr_rx_time) {
++			hctl->isr_rx_time += (jiffies - before);
++			hctl->isr_rx_time = hctl->isr_rx_time >> 1;
++		} else {
++			hctl->isr_rx_time += (jiffies - before);
++		}
++		hctl->prev_rx_isr_jiffes = jiffies;
++	}
++	return status;
++}
++
++static int _do_tx(struct ssv6xxx_hci_ctrl *hctl, u32 status)
++{
++	int q_num;
++	int tx_count = 0;
++	u32 to_disable_int = 1;
++	unsigned long flags;
++	struct ssv_hw_txq *hw_txq;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time;
++#endif
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++	if ((!(status & SSV6XXX_INT_RX)) && htcl->irq_enable)
++		hctl->tx_irq_count++;
++#endif
++	if ((status & SSV6XXX_INT_RESOURCE_LOW) == 0)
++		return 0;
++	for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
++		u32 before = jiffies;
++		hw_txq = &hctl->hw_txq[q_num];
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&tx_io_start_time);
++#endif
++		tx_count += ssv6xxx_hci_tx_handler(hw_txq, 999);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable) {
++			getnstimeofday(&tx_io_end_time);
++			tx_io_diff_time =
++			    timespec_sub(tx_io_end_time, tx_io_start_time);
++			hctl->isr_tx_io_time +=
++			    timespec_to_ns(&tx_io_diff_time);
++		}
++#endif
++		if (hctl->isr_summary_eable) {
++			if (hctl->isr_tx_time) {
++				hctl->isr_tx_time += (jiffies - before);
++				hctl->isr_tx_time = hctl->isr_tx_time >> 1;
++			} else {
++				hctl->isr_tx_time += (jiffies - before);
++			}
++		}
++	}
++	mutex_lock(&hctl->hci_mutex);
++	spin_lock_irqsave(&hctl->int_lock, flags);
++	for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
++		hw_txq = &hctl->hw_txq[q_num];
++		if (skb_queue_len(&hw_txq->qhead) > 0) {
++			to_disable_int = 0;
++			break;
++		}
++	}
++	if (to_disable_int) {
++		u32 reg_val;
++		hctl->int_mask &= ~(SSV6XXX_INT_RESOURCE_LOW | SSV6XXX_INT_TX);
++		reg_val = ~hctl->int_mask;
++		spin_unlock_irqrestore(&hctl->int_lock, flags);
++		HCI_IRQ_SET_MASK(hctl, reg_val);
++	} else {
++		spin_unlock_irqrestore(&hctl->int_lock, flags);
++	}
++	mutex_unlock(&hctl->hci_mutex);
++	return tx_count;
++}
++
++irqreturn_t ssv6xxx_hci_isr(int irq, void *args)
++{
++	struct ssv6xxx_hci_ctrl *hctl = args;
++	u32 status;
++	unsigned long flags;
++	int ret = IRQ_HANDLED;
++	bool dbg_isr_miss = true;
++	if (ctrl_hci->isr_summary_eable && ctrl_hci->prev_isr_jiffes) {
++		if (ctrl_hci->isr_idle_time) {
++			ctrl_hci->isr_idle_time +=
++			    (jiffies - ctrl_hci->prev_isr_jiffes);
++			ctrl_hci->isr_idle_time = ctrl_hci->isr_idle_time >> 1;
++		} else {
++			ctrl_hci->isr_idle_time +=
++			    (jiffies - ctrl_hci->prev_isr_jiffes);
++		}
++	}
++	BUG_ON(!args);
++	do {
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		struct timespec start_time, end_time, diff_time;
++		if (hctl->isr_mib_reset)
++			ssv6xxx_isr_mib_reset();
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&start_time);
++#endif
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++		if (ctrl_hci->irq_enable)
++			ctrl_hci->irq_count++;
++#endif
++		mutex_lock(&hctl->hci_mutex);
++		if (hctl->int_status) {
++			u32 regval;
++			spin_lock_irqsave(&hctl->int_lock, flags);
++			hctl->int_mask |= hctl->int_status;
++			hctl->int_status = 0;
++			regval = ~ctrl_hci->int_mask;
++			smp_mb();
++			spin_unlock_irqrestore(&hctl->int_lock, flags);
++			HCI_IRQ_SET_MASK(hctl, regval);
++		}
++		ret = HCI_IRQ_STATUS(hctl, &status);
++		if ((ret < 0) || ((status & hctl->int_mask) == 0)) {
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++			if (ctrl_hci->irq_enable)
++				ctrl_hci->invalid_irq_count++;
++#endif
++			mutex_unlock(&hctl->hci_mutex);
++			ret = IRQ_NONE;
++			break;
++		}
++		spin_lock_irqsave(&hctl->int_lock, flags);
++		status &= hctl->int_mask;
++		spin_unlock_irqrestore(&hctl->int_lock, flags);
++		mutex_unlock(&hctl->hci_mutex);
++		ctrl_hci->isr_running = 1;
++		if (status & SSV6XXX_INT_RX) {
++			ret = _isr_do_rx(hctl, status);
++			if (ret < 0) {
++				ret = IRQ_NONE;
++				break;
++			}
++			dbg_isr_miss = false;
++		}
++		if (_do_tx(hctl, status)) {
++			dbg_isr_miss = false;
++		}
++		ctrl_hci->isr_running = 0;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable) {
++			getnstimeofday(&end_time);
++			diff_time = timespec_sub(end_time, start_time);
++			ctrl_hci->isr_total_time += timespec_to_ns(&diff_time);
++		}
++#endif
++	} while (1);
++	if (ctrl_hci->isr_summary_eable) {
++		if (dbg_isr_miss)
++			ctrl_hci->isr_miss_cnt++;
++		ctrl_hci->prev_isr_jiffes = jiffies;
++	}
++	return ret;
++}
++
++static struct ssv6xxx_hci_ops hci_ops = {
++	.hci_start = ssv6xxx_hci_start,
++	.hci_stop = ssv6xxx_hci_stop,
++	.hci_read_word = ssv6xxx_hci_read_word,
++	.hci_write_word = ssv6xxx_hci_write_word,
++	.hci_tx = ssv6xxx_hci_enqueue,
++	.hci_tx_pause = ssv6xxx_hci_txq_pause,
++	.hci_tx_resume = ssv6xxx_hci_txq_resume,
++	.hci_txq_flush = ssv6xxx_hci_txq_flush,
++	.hci_txq_flush_by_sta = ssv6xxx_hci_txq_flush_by_sta,
++	.hci_txq_empty = ssv6xxx_hci_is_txq_empty,
++	.hci_load_fw = ssv6xxx_hci_load_fw,
++	.hci_pmu_wakeup = ssv6xxx_hci_pmu_wakeup,
++	.hci_send_cmd = ssv6xxx_hci_send_cmd,
++	.hci_write_sram = ssv6xxx_hci_write_sram,
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	.hci_init_debugfs = ssv6xxx_hci_init_debugfs,
++	.hci_deinit_debugfs = ssv6xxx_hci_deinit_debugfs,
++#endif
++	.hci_interface_reset = ssv6xxx_hci_interface_reset,
++};
++
++int ssv6xxx_hci_deregister(void)
++{
++	u32 regval;
++	pr_debug("%s(): \n", __FUNCTION__);
++	if (ctrl_hci->shi == NULL)
++		return -1;
++	regval = 1;
++	ssv6xxx_hci_irq_disable();
++	flush_workqueue(ctrl_hci->hci_work_queue);
++	destroy_workqueue(ctrl_hci->hci_work_queue);
++	ctrl_hci->shi = NULL;
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_hci_deregister);
++int ssv6xxx_hci_register(struct ssv6xxx_hci_info *shi)
++{
++	int i;
++	if (shi == NULL || ctrl_hci->shi)
++		return -1;
++	shi->hci_ops = &hci_ops;
++	ctrl_hci->shi = shi;
++	ctrl_hci->txq_mask = 0;
++	mutex_init(&ctrl_hci->txq_mask_lock);
++	mutex_init(&ctrl_hci->hci_mutex);
++	spin_lock_init(&ctrl_hci->int_lock);
++
++	for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
++		memset(&ctrl_hci->hw_txq[i], 0, sizeof(struct ssv_hw_txq));
++		skb_queue_head_init(&ctrl_hci->hw_txq[i].qhead);
++		ctrl_hci->hw_txq[i].txq_no = (u32) i;
++		ctrl_hci->hw_txq[i].max_qsize = SSV_HW_TXQ_MAX_SIZE;
++		ctrl_hci->hw_txq[i].resum_thres = SSV_HW_TXQ_RESUME_THRES;
++	}
++	ctrl_hci->hci_work_queue =
++	    create_singlethread_workqueue("ssv6xxx_hci_wq");
++	INIT_WORK(&ctrl_hci->hci_rx_work, ssv6xxx_hci_rx_work);
++	INIT_WORK(&ctrl_hci->hci_tx_work, ssv6xxx_hci_tx_work);
++	ctrl_hci->int_mask = SSV6XXX_INT_RX | SSV6XXX_INT_RESOURCE_LOW;
++	ctrl_hci->int_status = 0;
++	HCI_IRQ_SET_MASK(ctrl_hci, 0xFFFFFFFF);
++	ssv6xxx_hci_irq_disable();
++	HCI_IRQ_REQUEST(ctrl_hci, ssv6xxx_hci_isr);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ctrl_hci->debugfs_dir = NULL;
++	ctrl_hci->isr_mib_enable = false;
++	ctrl_hci->isr_mib_reset = 0;
++	ctrl_hci->isr_total_time = 0;
++	ctrl_hci->isr_rx_io_time = 0;
++	ctrl_hci->isr_tx_io_time = 0;
++	ctrl_hci->isr_rx_io_count = 0;
++	ctrl_hci->isr_tx_io_count = 0;
++	ctrl_hci->isr_rx_proc_time = 0;
++#endif
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_hci_register);
++int ssv6xxx_hci_init(void)
++{
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
++#endif
++	ctrl_hci = kzalloc(sizeof(*ctrl_hci), GFP_KERNEL);
++	if (ctrl_hci == NULL)
++		return -ENOMEM;
++	memset((void *)ctrl_hci, 0, sizeof(*ctrl_hci));
++	ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++	if (ctrl_hci->rx_buf == NULL) {
++		kfree(ctrl_hci);
++		return -ENOMEM;
++	}
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	ssv_dbg_ctrl_hci = ctrl_hci;
++#endif
++	return 0;
++}
++
++void ssv6xxx_hci_exit(void)
++{
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
++#endif
++	kfree(ctrl_hci);
++	ctrl_hci = NULL;
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	ssv_dbg_ctrl_hci = NULL;
++#endif
++}
++
++EXPORT_SYMBOL(ssv6xxx_hci_init);
++EXPORT_SYMBOL(ssv6xxx_hci_exit);
+diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.h b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
+new file mode 100644
+index 000000000000..dd166c607d5d
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
+@@ -0,0 +1,77 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_HCI_H_
++#define _SSV_HCI_H_
++#define SSV_HW_TXQ_NUM 5
++#define SSV_HW_TXQ_MAX_SIZE 64
++#define SSV_HW_TXQ_RESUME_THRES ((SSV_HW_TXQ_MAX_SIZE >> 2) *3)
++#define HCI_FLAGS_ENQUEUE_HEAD 0x00000001
++#define HCI_FLAGS_NO_FLOWCTRL 0x00000002
++struct ssv_hw_txq {
++	u32 txq_no;
++	struct sk_buff_head qhead;
++	int max_qsize;
++	int resum_thres;
++	bool paused;
++	u32 tx_pkt;
++	u32 tx_flags;
++};
++struct ssv6xxx_hci_ops {
++	int (*hci_start)(void);
++	int (*hci_stop)(void);
++	int (*hci_read_word)(u32 addr, u32 * regval);
++	int (*hci_write_word)(u32 addr, u32 regval);
++	int (*hci_load_fw)(u8 * firmware_name, u8 openfile);
++	int (*hci_tx)(struct sk_buff *, int, u32);
++	int (*hci_tx_pause)(u32 txq_mask);
++	int (*hci_tx_resume)(u32 txq_mask);
++	int (*hci_txq_flush)(u32 txq_mask);
++	int (*hci_txq_flush_by_sta)(int aid);
++	bool (*hci_txq_empty)(int txqid);
++	int (*hci_pmu_wakeup)(void);
++	int (*hci_send_cmd)(struct sk_buff *);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	bool (*hci_init_debugfs)(struct dentry * dev_deugfs_dir);
++	void (*hci_deinit_debugfs)(void);
++#endif
++	int (*hci_write_sram)(u32 addr, u8 * data, u32 size);
++	int (*hci_interface_reset)(void);
++};
++struct ssv6xxx_hci_info {
++	struct device *dev;
++	struct ssv6xxx_hwif_ops *if_ops;
++	struct ssv6xxx_hci_ops *hci_ops;
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	int (*hci_rx_cb)(struct sk_buff_head *, void *);
++#else
++	int (*hci_rx_cb)(struct sk_buff *, void *);
++#endif
++	void *rx_cb_args;
++	void (*hci_tx_cb)(struct sk_buff_head *, void *);
++	void *tx_cb_args;
++	int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug);
++	void *tx_fctrl_cb_args;
++	void (*hci_tx_buf_free_cb)(struct sk_buff *, void *);
++	void *tx_buf_free_args;
++	void (*hci_skb_update_cb)(struct sk_buff *, void *);
++	void *skb_update_args;
++	void (*hci_tx_q_empty_cb)(u32 txq_no, void *);
++	void *tx_q_empty_args;
++};
++int ssv6xxx_hci_deregister(void);
++int ssv6xxx_hci_register(struct ssv6xxx_hci_info *);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/hwif/hwif.h b/drivers/net/wireless/ssv6051/hwif/hwif.h
+new file mode 100644
+index 000000000000..6b5263d157d8
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hwif/hwif.h
+@@ -0,0 +1,84 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _LINUX_SSVCABRIO_PLATFORM_H
++#define _LINUX_SSVCABRIO_PLATFORM_H 
++#include <linux/mmc/host.h>
++#include <hwif/sdio/sdio_def.h>
++#define SSVCABRIO_PLAT_EEP_MAX_WORDS 2048
++#define SSV_REG_WRITE(dev,reg,val) \
++        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
++#define SSV_REG_READ(dev,reg,buf) \
++        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
++#if 0
++#define SSV_REG_WRITE(sh,reg,val) \
++        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
++#define SSV_REG_READ(sh,reg,buf) \
++        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
++#define SSV_REG_CONFIRM(sh,reg,val) \
++{ \
++    u32 regval; \
++    SSV_REG_READ(sh, reg, &regval); \
++    if (regval != (val)) { \
++        printk("[0x%08x]: 0x%08x!=0x%08x\n",\
++        (reg), (val), regval); \
++        return -1; \
++    } \
++}
++#define SSV_REG_SET_BITS(sh,reg,set,clr) \
++{ \
++    u32 reg_val; \
++    SSV_REG_READ(sh, reg, &reg_val); \
++    reg_val &= ~(clr); \
++    reg_val |= (set); \
++    SSV_REG_WRITE(sh, reg, reg_val); \
++}
++#endif
++struct ssv6xxx_hwif_ops {
++    int __must_check (*read)(struct device *child, void *buf,size_t *size);
++    int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num);
++    int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf);
++    int __must_check (*writereg)(struct device *child, u32 addr, u32 buf);
++    int (*trigger_tx_rx)(struct device *child);
++    int (*irq_getmask)(struct device *child, u32 *mask);
++    void (*irq_setmask)(struct device *child,int mask);
++    void (*irq_enable)(struct device *child);
++    void (*irq_disable)(struct device *child,bool iswaitirq);
++    int (*irq_getstatus)(struct device *child,int *status);
++    void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev);
++    void (*irq_trigger)(struct device *child);
++    void (*pmu_wakeup)(struct device *child);
++    int __must_check (*load_fw)(struct device *child, u8 *firmware_name, u8 openfile);
++    int (*cmd52_read)(struct device *child, u32 addr, u32 *value);
++    int (*cmd52_write)(struct device *child, u32 addr, u32 value);
++    bool (*support_scatter)(struct device *child);
++    int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req);
++    bool (*is_ready)(struct device *child);
++    int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size);
++    void (*interface_reset)(struct device *child);
++};
++struct ssv6xxx_if_debug {
++    struct device *dev;
++    struct platform_device *pdev;
++};
++struct ssv6xxx_platform_data {
++    atomic_t irq_handling;
++    bool is_enabled;
++    unsigned short vendor;
++    unsigned short device;
++    struct ssv6xxx_hwif_ops *ops;
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
+new file mode 100644
+index 000000000000..273777cd0485
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
+@@ -0,0 +1,1254 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/vmalloc.h>
++#include <linux/platform_device.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/host.h>
++#include "sdio_def.h"
++#include <linux/pm_runtime.h>
++#include <linux/version.h>
++#include <linux/firmware.h>
++#include <linux/reboot.h>
++#include <ssv6200.h>
++#include <linux/skbuff.h>
++
++#define LOW_SPEED_SDIO_CLOCK (25000000)
++#define HIGH_SPEED_SDIO_CLOCK (37500000)
++#define MAX_RX_FRAME_SIZE 0x900
++#define SSV_VENDOR_ID 0x3030
++#define SSV_CABRIO_DEVID 0x3030
++#define ENABLE_FW_SELF_CHECK 1
++#define FW_BLOCK_SIZE 0x8000
++#define CHECKSUM_BLOCK_SIZE 1024
++#define FW_CHECKSUM_INIT (0x12345678)
++#define FW_STATUS_REG ADR_TX_SEG
++#define FW_STATUS_MASK (0x00FF0000)
++
++#define ret_if_not_ready(value) \
++    do { \
++    if ((wlan_data.is_enabled == false) || \
++        (glue == NULL) || (glue->dev_ready == false)) { \
++        pr_warn("ret_if_not_ready() called when not ready"); \
++        return value; }\
++    } while(0)
++
++static int ssv6xxx_sdio_trigger_pmu(struct device *dev);
++static void ssv6xxx_sdio_reset(struct device *child);
++
++static void ssv6xxx_high_sdio_clk(struct sdio_func *func);
++static void ssv6xxx_low_sdio_clk(struct sdio_func *func);
++extern void *ssv6xxx_ifdebug_info[];
++extern int ssv_devicetype;
++extern void ssv6xxx_deinit_prepare(void);
++
++static struct ssv6xxx_platform_data wlan_data;
++
++static int ssv6xxx_sdio_status = 0;
++u32 sdio_sr_bhvr = SUSPEND_RESUME_0;
++EXPORT_SYMBOL(sdio_sr_bhvr);
++
++u32 shutdown_flags = SSV_SYS_REBOOT;
++
++struct ssv6xxx_sdio_glue {
++	struct device *dev;
++	struct platform_device *core;
++	struct sk_buff *dma_skb;
++#ifdef CONFIG_PM
++	struct sk_buff *cmd_skb;
++#endif
++	unsigned int ioport_data;
++	unsigned int ioport_reg;
++	irq_handler_t irq_handler;
++	void *irq_dev;
++	bool dev_ready;
++};
++
++static const struct sdio_device_id ssv6xxx_sdio_devices[] = {
++	{SDIO_DEVICE(SSV_VENDOR_ID, SSV_CABRIO_DEVID)},
++	{}
++};
++
++MODULE_DEVICE_TABLE(sdio, ssv6xxx_sdio_devices);
++
++static bool ssv6xxx_is_ready(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++
++	ret_if_not_ready(false);
++
++	return true;
++}
++
++static int ssv6xxx_sdio_cmd52_read(struct device *child, u32 addr, u32 * value)
++{
++	int ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++	ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    *value = sdio_readb(func, addr, &ret);
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int ssv6xxx_sdio_cmd52_write(struct device *child, u32 addr, u32 value)
++{
++	int ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready(-1);
++
++	func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    sdio_writeb(func, value, addr, &ret);
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int __must_check
++ssv6xxx_sdio_read_reg(struct device *child, u32 addr, u32 * buf)
++{
++	int ret;
++
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	u32 data;
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++
++    sdio_claim_host(func);
++
++    data = addr;
++
++    sdio_writel(func, addr, glue->ioport_reg, &ret);
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read reg write address failed (%d)\n", ret);
++        goto io_err;
++    }
++
++    data = sdio_readl(func, glue->ioport_reg, &ret);
++
++    if (unlikely(ret)) {
++        *buf = 0xffffffff;
++        dev_err(child->parent, "sdio read reg from I/O failed (%d)\n", ret);
++        goto io_err;
++    }
++
++    *buf = data;
++
++io_err:
++    sdio_release_host(func);
++
++	return ret;
++}
++
++#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
++static int ssv6xxx_sdio_trigger_tx_rx(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	struct mmc_host *host;
++
++	if (glue == NULL)
++		return -1;
++
++	func = dev_to_sdio_func(glue->dev);
++	host = func->card->host;
++	mmc_signal_sdio_irq(host);
++
++	return 0;
++
++}
++#endif
++
++static int __must_check
++ssv6xxx_sdio_write_reg(struct device *child, u32 addr, u32 buf)
++{
++	int ret;
++
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    u32 data[2];
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++
++    sdio_claim_host(func);
++    data[0] = addr;
++    data[1] = buf;
++
++    ret = sdio_memcpy_toio(func, glue->ioport_reg, data, sizeof(data));
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int
++ssv6xxx_sdio_write_sram(struct device *child, u32 addr, u8 * data, u32 size)
++{
++	int ret = 0;
++	struct ssv6xxx_sdio_glue *glue;
++	struct sdio_func *func = NULL;
++	glue = dev_get_drvdata(child->parent);
++
++    ret_if_not_ready(-1);
++
++	func = dev_to_sdio_func(glue->dev);
++	sdio_claim_host(func);
++
++    ret |= ssv6xxx_sdio_write_reg(child, 0xc0000860, addr);
++    if (unlikely(ret))
++        goto out;
++
++    sdio_writeb(func, 0x2, REG_Fn1_STATUS, &ret);
++    if (unlikely(ret))
++        goto out;
++
++    ret = sdio_memcpy_toio(func, glue->ioport_data, data, size);
++    if (unlikely(ret))
++        goto out;
++
++    sdio_writeb(func, 0, REG_Fn1_STATUS, &ret);
++    if (unlikely(ret))
++        goto out;
++
++out:
++	sdio_release_host(func);
++	return ret;
++
++}
++
++struct file *ssv6xxx_open_firmware(char *user_mainfw)
++{
++	struct file *fp;
++	fp = filp_open(user_mainfw, O_RDONLY, 0);
++
++	if (IS_ERR(fp))
++		fp = NULL;
++
++	return fp;
++}
++
++int ssv6xxx_read_fw_block(char *buf, int len, struct file *fp)
++{
++
++	int read;
++	loff_t pos;
++
++	pos = fp->f_pos;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
++	read = kernel_read(fp, (void *)buf, len, &pos);
++#else
++	read = kernel_read(fp, pos, buf, len);
++#endif
++
++	if (read > 0)
++		fp->f_pos += read;
++
++	return read;
++
++}
++
++void ssv6xxx_close_firmware(struct file *fp)
++{
++	if (fp)
++		filp_close(fp, NULL);
++}
++
++static int
++ssv6xxx_sdio_upload_firmware(struct device *child, const u8 *firmware, u32 firmware_length)
++{
++	int ret;
++    u32 clk_en;
++	u32 word_count, i;
++    u32 block_size;
++	u8 *buffer;
++	u32 sram_ptr = 0;
++	u32 block_count = 0;
++    u32 firmware_ptr = 0;
++
++	u32 checksum = FW_CHECKSUM_INIT;
++	u32 fw_checksum, fw_blkcnt;
++
++	struct ssv6xxx_sdio_glue *glue;
++
++	glue = dev_get_drvdata(child->parent);
++
++    if ((wlan_data.is_enabled == false) &&
++        (glue == NULL) &&
++        (glue->dev_ready == false))
++        goto out;
++
++    buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL);
++    if (buffer == NULL) {
++        dev_err(child, "Failed to allocate buffer for firmware.\n");
++        ret = -ENOMEM;
++        goto out;
++    }
++
++    dev_dbg(child, "preparing registers and clock for firmware upload\n");
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x0);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_BOOT, 0x01);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_read_reg(child, ADR_PLATFORM_CLOCK_ENABLE, &clk_en);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_PLATFORM_CLOCK_ENABLE, clk_en | (1 << 2));
++    if (unlikely(ret))
++        goto out;
++
++    dev_dbg(child, "begin writing firmware\n");
++
++    while (firmware_length > 0) {
++
++        memset(buffer, 0xA5, FW_BLOCK_SIZE);
++
++        block_size = firmware_length;
++        if (block_size > FW_BLOCK_SIZE)
++            block_size = FW_BLOCK_SIZE;
++
++        memcpy(buffer, &firmware[firmware_ptr], block_size);
++
++        firmware_ptr += block_size;
++        firmware_length -= block_size;
++
++        /*
++         * Uploading to chip sram and checksumming happens in chunks of CHECKSUM_BLOCK_SIZE,
++         * so we round the block size accordingly and use that valueù
++         */
++        block_size = DIV_ROUND_UP(block_size, CHECKSUM_BLOCK_SIZE) * CHECKSUM_BLOCK_SIZE;
++        ret = ssv6xxx_sdio_write_sram(child, sram_ptr, (u8 *)buffer, block_size);
++
++        if (ret) {
++            dev_err(child, "firmware upload failed\n");
++            goto out;
++        }
++
++        sram_ptr += block_size;
++
++        word_count = block_size / sizeof(u32);
++        for (i = 0; i < word_count; i++)
++            checksum += ((u32 *)buffer)[i];
++
++    }
++
++    checksum = ((checksum >> 24) +
++                (checksum >> 16) +
++                (checksum >> 8) +
++                checksum) & 0x0FF;
++    checksum <<= 16;
++
++    block_count = DIV_ROUND_UP(sram_ptr, CHECKSUM_BLOCK_SIZE);
++    ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (block_count << 16));
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_blkcnt);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x1);
++    if (unlikely(ret))
++        goto out;
++
++    dev_info(child, "firmware upload complete (wrote %d blocks, verified %d blocks)\n", block_count, fw_blkcnt >> 16);
++
++    msleep(50);
++
++    ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_checksum);
++    fw_checksum = fw_checksum & FW_STATUS_MASK;
++
++    if (fw_checksum == checksum) {
++        dev_dbg(child, "firmware check ok, checksum=0x%x\n", checksum);
++        ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (~checksum & FW_STATUS_MASK));
++        if (unlikely(ret))
++            dev_warn(child, "could not clear checksum condition");
++    } else {
++        dev_err(child, "firmware checksum mismatch, local=0x%x, sram=0x%x\n", checksum, fw_checksum);
++    }
++
++    msleep(50);
++
++    ret = 0;
++
++ out:
++
++	if (buffer)
++		kfree(buffer);
++
++	return ret;
++
++}
++
++static int
++ssv6xxx_sdio_load_firmware(struct device *child, u8 *firmware_name, u8 openfile)
++{
++
++    int ret;
++    const struct firmware *firmware = NULL;
++    struct sdio_func *func;
++   	struct ssv6xxx_sdio_glue *glue;
++
++    glue = dev_get_drvdata(child->parent);
++
++    ret = request_firmware(&firmware, firmware_name, glue->dev);
++
++    if (ret) {
++        dev_err(child, "could not find firmware file %s, err=%d\n", firmware_name, ret);
++        goto out;
++    }
++
++    ret = ssv6xxx_sdio_upload_firmware(child, firmware->data, firmware->size);
++
++    if (ret) {
++        dev_err(child, "could not upload firmware to device, err=%d\n", ret);
++        goto out;
++    }
++
++    if (glue != NULL) {
++		func = dev_to_sdio_func(glue->dev);
++		ssv6xxx_high_sdio_clk(func);
++	}
++
++out:
++    if (firmware != NULL)
++        release_firmware(firmware);
++
++    return ret;
++
++}
++
++static int ssv6xxx_sdio_irq_getstatus(struct device *child, int *status)
++{
++	int ret = (-1);
++	struct ssv6xxx_sdio_glue *glue;
++	struct sdio_func *func;
++	glue = dev_get_drvdata(child->parent);
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    *status = sdio_readb(func, REG_INT_STATUS, &ret);
++    sdio_release_host(func);
++
++    return ret;
++
++}
++
++static int __must_check
++ssv6xxx_sdio_read(struct device *child, void *buf, size_t *size)
++{
++
++	int ret;
++    u32 data_size;
++
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++
++    data_size = sdio_readb(func, REG_CARD_PKT_LEN_0, &ret);
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read high byte len failed, ret=%d\n", ret);
++        goto out;
++    }
++
++    data_size = data_size | (sdio_readb(func, REG_CARD_PKT_LEN_1, &ret) << 0x8);
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read low len failed ret[%d]\n", ret);
++        goto out;
++    }
++
++    ret = sdio_memcpy_fromio(func, buf, glue->ioport_data, sdio_align_size(func, data_size));
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read failed size ret[%d]\n", ret);
++        goto out;
++    }
++    
++    *size = data_size;
++
++out:
++
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int __must_check
++ssv6xxx_sdio_write(struct device *child, void *buf, size_t len, u8 queue_num)
++{
++	int ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	void *ptr;
++
++    ret_if_not_ready(-1);
++
++#ifdef CONFIG_ARM64
++    if (((u64) buf) & 3) {
++#else
++    if (((u32) buf) & 3) {
++#endif
++        memcpy(glue->dma_skb->data, buf, len);
++        ptr = glue->dma_skb->data;
++    } else
++        ptr = buf;
++
++    func = dev_to_sdio_func(glue->dev);
++
++    sdio_claim_host(func);
++
++    len = sdio_align_size(func, len);
++    ret = sdio_memcpy_toio(func, glue->ioport_data, ptr, len);
++
++    if (unlikely(ret))
++        dev_err(glue->dev, "sdio write failed, ret=%d\n", ret);
++
++    sdio_release_host(func);
++
++    return ret;
++
++}
++
++static void ssv6xxx_sdio_irq_handler(struct sdio_func *func)
++{
++	int status;
++	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++
++    ret_if_not_ready();
++
++    if (glue->irq_handler == NULL)
++        return;
++
++    atomic_set(&pwlan_data->irq_handling, 1);
++    sdio_release_host(func);
++    if (glue->irq_handler != NULL)
++        status = glue->irq_handler(0, glue->irq_dev);
++    sdio_claim_host(func);
++    atomic_set(&pwlan_data->irq_handling, 0);
++
++}
++
++static void ssv6xxx_sdio_irq_setmask(struct device *child, int mask)
++{
++	int err_ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready();
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    sdio_writeb(func, mask, REG_INT_MASK, &err_ret);
++    sdio_release_host(func);
++
++}
++
++static void ssv6xxx_sdio_irq_trigger(struct device *child)
++{
++	int err_ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready();
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    sdio_writeb(func, 0x2, REG_INT_TRIGGER, &err_ret);
++    sdio_release_host(func);
++
++}
++
++static int ssv6xxx_sdio_irq_getmask(struct device *child, u32 * mask)
++{
++	u8 imask = 0;
++	int ret = (-1);
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    imask = sdio_readb(func, REG_INT_MASK, &ret);
++    *mask = imask;
++    sdio_release_host(func);
++
++	return ret;
++
++}
++
++static void ssv6xxx_sdio_irq_enable(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	int ret;
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++	if ((pwlan_data->is_enabled == false)
++	    || (glue == NULL) || (glue->dev_ready == false))
++		return;
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    ret = sdio_claim_irq(func, ssv6xxx_sdio_irq_handler);
++    if (ret)
++        dev_err(child->parent, "Failed to claim sdio irq: %d\n",
++            ret);
++    sdio_release_host(func);
++
++	dev_dbg(child, "ssv6xxx_sdio_irq_enable\n");
++
++}
++
++static void ssv6xxx_sdio_irq_disable(struct device *child, bool iswaitirq)
++{
++	struct ssv6xxx_sdio_glue *glue = NULL;
++	struct sdio_func *func;
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++	int ret;
++
++	dev_dbg(child, "ssv6xxx_sdio_irq_disable\n");
++
++	if ((wlan_data.is_enabled == false) || (child->parent == NULL))
++		return;
++
++	glue = dev_get_drvdata(child->parent);
++
++
++	if ((glue == NULL) || (glue->dev_ready == false)
++	    || (glue->dev == NULL))
++		return;
++
++    func = dev_to_sdio_func(glue->dev);
++
++    if (func == NULL) {
++        dev_dbg(child, "sdio func == NULL\n");
++        return;
++    }
++
++    sdio_claim_host(func);
++    while (atomic_read(&pwlan_data->irq_handling)) {
++        sdio_release_host(func);
++        schedule_timeout(HZ / 10);
++        sdio_claim_host(func);
++    }
++    ret = sdio_release_irq(func);
++
++    if (ret)
++        dev_err(child->parent,
++            "Failed to release sdio irq: %d\n", ret);
++
++    sdio_release_host(func);
++
++}
++
++static void
++ssv6xxx_sdio_irq_request(struct device *child, irq_handler_t irq_handler,
++			 void *irq_dev)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	bool isIrqEn = false;
++
++    ret_if_not_ready();
++
++    func = dev_to_sdio_func(glue->dev);
++    glue->irq_handler = irq_handler;
++    glue->irq_dev = irq_dev;
++    if (isIrqEn) {
++        ssv6xxx_sdio_irq_enable(child);
++    }
++
++}
++
++static void
++ssv6xxx_sdio_read_parameter(struct sdio_func *func,
++			    struct ssv6xxx_sdio_glue *glue)
++{
++	int err_ret;
++	sdio_claim_host(func);
++	glue->ioport_data = 0;
++	glue->ioport_data =
++	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret)
++				<< (8 * 0));
++	glue->ioport_data =
++	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret)
++				<< (8 * 1));
++	glue->ioport_data =
++	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret)
++				<< (8 * 2));
++	glue->ioport_reg = 0;
++	glue->ioport_reg =
++	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) <<
++			       (8 * 0));
++	glue->ioport_reg =
++	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) <<
++			       (8 * 1));
++	glue->ioport_reg =
++	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) <<
++			       (8 * 2));
++	dev_dbg(&func->dev, "ioport_data=0x%x ioport_reg=0x%x\n",
++		glue->ioport_data, glue->ioport_reg);
++	err_ret = sdio_set_block_size(func, CONFIG_PLATFORM_SDIO_BLOCK_SIZE);
++	if (err_ret != 0) {
++		dev_warn(&func->dev, "SDIO setting SDIO_DEF_BLOCK_SIZE fail!!\n");
++	}
++	sdio_writeb(func, CONFIG_PLATFORM_SDIO_OUTPUT_TIMING,
++		    REG_OUTPUT_TIMING_REG, &err_ret);
++	sdio_writeb(func, 0x00, REG_Fn1_STATUS, &err_ret);
++	sdio_release_host(func);
++}
++
++static void ssv6xxx_do_sdio_wakeup(struct sdio_func *func)
++{
++	int err_ret;
++	if (func != NULL) {
++		sdio_claim_host(func);
++		sdio_writeb(func, 0x01, REG_PMU_WAKEUP, &err_ret);
++		mdelay(10);
++		sdio_writeb(func, 0x00, REG_PMU_WAKEUP, &err_ret);
++		sdio_release_host(func);
++	}
++}
++
++static void ssv6xxx_sdio_pmu_wakeup(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	if (glue != NULL) {
++		func = dev_to_sdio_func(glue->dev);
++		ssv6xxx_do_sdio_wakeup(func);
++	}
++}
++
++static bool ssv6xxx_sdio_support_scatter(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    if (!glue) {
++        dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
++        return false;
++    }
++
++    func = dev_to_sdio_func(glue->dev);
++
++    if (func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
++        dev_err(child->parent,
++            "host controller only supports scatter of :%d entries, driver need: %d\n",
++            func->card->host->max_segs,
++            MAX_SCATTER_ENTRIES_PER_REQ);
++        return false;
++    }
++
++    return true;
++
++}
++
++static void
++ssv6xxx_sdio_setup_scat_data(struct sdio_scatter_req *scat_req,
++			     struct mmc_data *data)
++{
++	struct scatterlist *sg;
++	int i;
++	data->blksz = SDIO_DEF_BLOCK_SIZE;
++	data->blocks = scat_req->len / SDIO_DEF_BLOCK_SIZE;
++	pr_debug
++	    ("scatter: (%s)  (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
++	     (scat_req->req & SDIO_WRITE) ? "WR" : "RD", data->blksz,
++	     data->blocks, scat_req->len, scat_req->scat_entries);
++	data->flags =
++	    (scat_req->req & SDIO_WRITE) ? MMC_DATA_WRITE : MMC_DATA_READ;
++	sg = scat_req->sgentries;
++	sg_init_table(sg, scat_req->scat_entries);
++	for (i = 0; i < scat_req->scat_entries; i++, sg++) {
++		pr_debug("%d: addr:0x%p, len:%d\n",
++		       i, scat_req->scat_list[i].buf,
++		       scat_req->scat_list[i].len);
++		sg_set_buf(sg, scat_req->scat_list[i].buf,
++			   scat_req->scat_list[i].len);
++	}
++	data->sg = scat_req->sgentries;
++	data->sg_len = scat_req->scat_entries;
++}
++
++static inline void
++ssv6xxx_sdio_set_cmd53_arg(u32 * arg, u8 rw, u8 func,
++			   u8 mode, u8 opcode, u32 addr, u16 blksz)
++{
++	*arg = (((rw & 1) << 31) |
++		((func & 0x7) << 28) |
++		((mode & 1) << 27) |
++		((opcode & 1) << 26) | ((addr & 0x1FFFF) << 9) | (blksz &
++								  0x1FF));
++}
++
++static int
++ssv6xxx_sdio_rw_scatter(struct device *child, struct sdio_scatter_req *scat_req)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	struct mmc_request mmc_req;
++	struct mmc_command cmd;
++	struct mmc_data data;
++	u8 opcode, rw;
++	int status = 1;
++
++    if (!glue) {
++        dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
++        return 1;
++    }
++
++    func = dev_to_sdio_func(glue->dev);
++    memset(&mmc_req, 0, sizeof(struct mmc_request));
++    memset(&cmd, 0, sizeof(struct mmc_command));
++    memset(&data, 0, sizeof(struct mmc_data));
++    ssv6xxx_sdio_setup_scat_data(scat_req, &data);
++    opcode = 0;
++    rw = (scat_req->req & SDIO_WRITE) ? CMD53_ARG_WRITE :
++        CMD53_ARG_READ;
++    ssv6xxx_sdio_set_cmd53_arg(&cmd.arg, rw, func->num,
++                    CMD53_ARG_BLOCK_BASIS, opcode,
++                    glue->ioport_data, data.blocks);
++    cmd.opcode = SD_IO_RW_EXTENDED;
++    cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
++    mmc_req.cmd = &cmd;
++    mmc_req.data = &data;
++    mmc_set_data_timeout(&data, func->card);
++    mmc_wait_for_req(func->card->host, &mmc_req);
++
++    status = cmd.error ? cmd.error : data.error;
++
++    if (cmd.error)
++        return cmd.error;
++
++    if (data.error)
++        return data.error;
++
++    return status;
++
++}
++
++static void ssv6xxx_set_sdio_clk(struct sdio_func *func, u32 sdio_hz)
++{
++	struct mmc_host *host;
++	host = func->card->host;
++	if (sdio_hz < host->f_min)
++		sdio_hz = host->f_min;
++	else if (sdio_hz > host->f_max)
++		sdio_hz = host->f_max;
++	dev_dbg(&func->dev, "%s:set sdio clk %dHz\n", __FUNCTION__, sdio_hz);
++	sdio_claim_host(func);
++	host->ios.clock = sdio_hz;
++	host->ops->set_ios(host, &host->ios);
++	mdelay(20);
++	sdio_release_host(func);
++}
++
++static void ssv6xxx_low_sdio_clk(struct sdio_func *func)
++{
++	ssv6xxx_set_sdio_clk(func, LOW_SPEED_SDIO_CLOCK);
++}
++
++static void ssv6xxx_high_sdio_clk(struct sdio_func *func)
++{
++#ifndef SDIO_USE_SLOW_CLOCK
++	ssv6xxx_set_sdio_clk(func, HIGH_SPEED_SDIO_CLOCK);
++#endif
++}
++
++static struct ssv6xxx_hwif_ops sdio_ops = {
++	.read = ssv6xxx_sdio_read,
++	.write = ssv6xxx_sdio_write,
++	.readreg = ssv6xxx_sdio_read_reg,
++	.writereg = ssv6xxx_sdio_write_reg,
++#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
++	.trigger_tx_rx = ssv6xxx_sdio_trigger_tx_rx,
++#endif
++	.irq_getmask = ssv6xxx_sdio_irq_getmask,
++	.irq_setmask = ssv6xxx_sdio_irq_setmask,
++	.irq_enable = ssv6xxx_sdio_irq_enable,
++	.irq_disable = ssv6xxx_sdio_irq_disable,
++	.irq_getstatus = ssv6xxx_sdio_irq_getstatus,
++	.irq_request = ssv6xxx_sdio_irq_request,
++	.irq_trigger = ssv6xxx_sdio_irq_trigger,
++	.pmu_wakeup = ssv6xxx_sdio_pmu_wakeup,
++	.load_fw = ssv6xxx_sdio_load_firmware,
++	.cmd52_read = ssv6xxx_sdio_cmd52_read,
++	.cmd52_write = ssv6xxx_sdio_cmd52_write,
++	.support_scatter = ssv6xxx_sdio_support_scatter,
++	.rw_scatter = ssv6xxx_sdio_rw_scatter,
++	.is_ready = ssv6xxx_is_ready,
++	.write_sram = ssv6xxx_sdio_write_sram,
++	.interface_reset = ssv6xxx_sdio_reset,
++};
++
++static int
++ssv6xxx_sdio_power_on(struct ssv6xxx_platform_data *pdata,
++		      struct sdio_func *func)
++{
++	int ret = 0;
++	if (pdata->is_enabled == true)
++		return 0;
++
++	dev_dbg(&func->dev, "ssv6xxx_sdio_power_on\n");
++
++	sdio_claim_host(func);
++	ret = sdio_enable_func(func);
++	sdio_release_host(func);
++
++	if (ret) {
++		dev_err(&func->dev, "Unable to enable sdio func: %d)\n", ret);
++		return ret;
++	}
++
++	msleep(10);
++	pdata->is_enabled = true;
++
++	return ret;
++}
++
++static int
++ssv6xxx_sdio_power_off(struct ssv6xxx_platform_data *pdata,
++		       struct sdio_func *func)
++{
++	int ret;
++	if (pdata->is_enabled == false)
++		return 0;
++	dev_dbg(&func->dev, "ssv6xxx_sdio_power_off\n");
++	sdio_claim_host(func);
++	ret = sdio_disable_func(func);
++	sdio_release_host(func);
++	if (ret)
++		return ret;
++	pdata->is_enabled = false;
++	return ret;
++}
++
++int ssv6xxx_get_dev_status(void)
++{
++	return ssv6xxx_sdio_status;
++}
++
++EXPORT_SYMBOL(ssv6xxx_get_dev_status);
++
++static int
++ssv6xxx_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id)
++{
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++	struct ssv6xxx_sdio_glue *glue;
++	int ret;
++	const char *chip_family = "ssv6200";
++
++	if (ssv_devicetype != 0) {
++		dev_info(&func->dev, "Not using SSV6200 normal SDIO driver.\n");
++		return -ENODEV;
++	}
++
++	if (func->num != 0x01)
++		return -ENODEV;
++
++	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
++
++	if (!glue) {
++		dev_err(&func->dev, "can't allocate glue\n");
++		return -ENOMEM;
++	}
++
++	ssv6xxx_sdio_status = 1;
++	ssv6xxx_low_sdio_clk(func);
++
++	glue->dma_skb = __dev_alloc_skb(SDIO_DMA_BUFFER_LEN, GFP_KERNEL);
++
++#ifdef CONFIG_PM
++	glue->cmd_skb = __dev_alloc_skb(SDIO_COMMAND_BUFFER_LEN, GFP_KERNEL);
++#endif
++	memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data));
++	atomic_set(&pwlan_data->irq_handling, 0);
++	glue->dev = &func->dev;
++	func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
++	func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
++	glue->dev_ready = true;
++	pwlan_data->vendor = func->vendor;
++	pwlan_data->device = func->device;
++	dev_info(glue->dev, "device id: %x:%x\n", pwlan_data->vendor,
++		pwlan_data->device);
++	pwlan_data->ops = &sdio_ops;
++	sdio_set_drvdata(func, glue);
++#ifdef CONFIG_PM
++	ssv6xxx_do_sdio_wakeup(func);
++#endif
++	ssv6xxx_sdio_power_on(pwlan_data, func);
++	ssv6xxx_sdio_read_parameter(func, glue);
++	glue->core = platform_device_alloc(chip_family, -1);
++
++	if (!glue->core) {
++		dev_err(glue->dev, "can't allocate platform_device");
++		ret = -ENOMEM;
++		goto out_free_glue;
++	}
++
++	glue->core->dev.parent = &func->dev;
++
++	ret = platform_device_add_data(glue->core, pwlan_data,
++				       sizeof(*pwlan_data));
++
++	if (ret) {
++		dev_err(glue->dev, "can't add platform data\n");
++		goto out_dev_put;
++	}
++
++	ret = platform_device_add(glue->core);
++
++	if (ret) {
++		dev_err(glue->dev, "can't add platform device\n");
++		goto out_dev_put;
++	}
++
++	ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
++
++	ssv6xxx_ifdebug_info[0] = (void *)&glue->core->dev;
++	ssv6xxx_ifdebug_info[1] = (void *)glue->core;
++	ssv6xxx_ifdebug_info[2] = (void *)&sdio_ops;
++	return 0;
++
++ out_dev_put:
++	platform_device_put(glue->core);
++ out_free_glue:
++	kfree(glue);
++
++	return ret;
++
++}
++
++static void ssv6xxx_sdio_remove(struct sdio_func *func)
++{
++	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++
++	dev_dbg(&func->dev, "ssv6xxx_sdio_remove enter\n");
++
++	ssv6xxx_sdio_status = 0;
++
++	if (glue) {
++		dev_dbg(&func->dev, "ssv6xxx_sdio_remove - ssv6xxx_sdio_irq_disable\n");
++		ssv6xxx_sdio_irq_disable(&glue->core->dev, false);
++		glue->dev_ready = false;
++		ssv6xxx_low_sdio_clk(func);
++
++		if (glue->dma_skb != NULL)
++			dev_kfree_skb(glue->dma_skb);
++
++		dev_dbg(&func->dev, "ssv6xxx_sdio_remove - disable mask\n");
++		ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
++#ifdef CONFIG_PM
++		ssv6xxx_sdio_trigger_pmu(glue->dev);
++		if (glue->cmd_skb != NULL)
++			dev_kfree_skb(glue->cmd_skb);
++#endif
++		ssv6xxx_sdio_power_off(pwlan_data, func);
++		dev_dbg(&func->dev, "platform_device_del \n");
++		platform_device_del(glue->core);
++		dev_dbg(&func->dev, "platform_device_put \n");
++		platform_device_put(glue->core);
++		kfree(glue);
++	}
++
++	sdio_set_drvdata(func, NULL);
++	dev_dbg(&func->dev, "ssv6xxx_sdio_remove leave\n");
++
++}
++
++static int ssv6xxx_sdio_trigger_pmu(struct device *dev)
++{
++
++	int ret = 0;
++
++#ifdef CONFIG_PM
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
++	struct cfg_host_cmd *host_cmd;
++	int writesize;
++	void *tempPointer;
++
++	if (ssv6xxx_sdio_write_reg
++	    (dev, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
++	if (ssv6xxx_sdio_write_reg
++	    (dev, ADR_RX_FLOW_DATA, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
++	if (ssv6xxx_sdio_write_reg
++	    (dev, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
++
++	host_cmd = (struct cfg_host_cmd *)glue->cmd_skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->RSVD0 = 0;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
++	host_cmd->len = sizeof(struct cfg_host_cmd);
++
++	host_cmd->dummy = 0;
++
++	{
++		tempPointer = glue->cmd_skb->data;
++		sdio_claim_host(func);
++		writesize = sdio_align_size(func, sizeof(struct cfg_host_cmd));
++		do {
++			ret =
++			    sdio_memcpy_toio(func, glue->ioport_data,
++					     tempPointer, writesize);
++			if (ret == -EILSEQ || ret == -ETIMEDOUT) {
++				ret = -1;
++				break;
++			} else {
++				if (ret)
++					dev_err(glue->dev,
++						"Unexpected return value ret=[%d]\n",
++						ret);
++			}
++		}
++		while (ret == -EILSEQ || ret == -ETIMEDOUT);
++		sdio_release_host(func);
++		if (ret)
++			dev_err(glue->dev, "sdio write failed (%d)\n", ret);
++	}
++
++#endif
++
++	return ret;
++
++}
++
++static void ssv6xxx_sdio_reset(struct device *child)
++{
++
++#ifdef CONFIG_PM
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func = dev_to_sdio_func(glue->dev);
++	dev_dbg(child, "%s\n", __FUNCTION__);
++	if (glue == NULL || glue->dev == NULL || func == NULL)
++		return;
++	ssv6xxx_sdio_trigger_pmu(glue->dev);
++	ssv6xxx_do_sdio_wakeup(func);
++#endif
++
++	return;
++
++}
++
++#ifdef CONFIG_PM
++static int ssv6xxx_sdio_suspend(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	mmc_pm_flag_t flags = sdio_get_host_pm_caps(func);
++	{
++		int ret = 0;
++		dev_info(dev, "%s: suspend: PM flags = 0x%x\n",
++			 sdio_func_id(func), flags);
++		ssv6xxx_low_sdio_clk(func);
++		ret = ssv6xxx_sdio_trigger_pmu(dev);
++		if (ret)
++			dev_warn(dev, "ssv6xxx_sdio_trigger_pmu fail!!\n");
++		if (!(flags & MMC_PM_KEEP_POWER)) {
++			dev_err(dev,
++				"%s: cannot remain alive while host is suspended\n",
++				sdio_func_id(func));
++		}
++		ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
++		if (ret)
++			return ret;
++		mdelay(10);
++		return ret;
++	}
++}
++
++static int ssv6xxx_sdio_resume(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	{
++		dev_dbg(dev, "ssv6xxx_sdio_resume\n");
++		{
++			ssv6xxx_do_sdio_wakeup(func);
++			mdelay(10);
++			ssv6xxx_high_sdio_clk(func);
++			mdelay(10);
++		}
++	}
++	return 0;
++}
++
++static const struct dev_pm_ops ssv6xxx_sdio_pm_ops = {
++	.suspend = ssv6xxx_sdio_suspend,
++	.resume = ssv6xxx_sdio_resume,
++};
++#endif
++
++struct sdio_driver ssv6xxx_sdio_driver = {
++	.name = "ssv6051",
++	.id_table = ssv6xxx_sdio_devices,
++	.probe = ssv6xxx_sdio_probe,
++	.remove = ssv6xxx_sdio_remove,
++#ifdef CONFIG_PM
++	.drv = {
++		.pm = &ssv6xxx_sdio_pm_ops,
++		},
++#endif
++};
++
++EXPORT_SYMBOL(ssv6xxx_sdio_driver);
++
++int ssv6xxx_sdio_init(void)
++{
++	return sdio_register_driver(&ssv6xxx_sdio_driver);
++}
++
++void ssv6xxx_sdio_exit(void)
++{
++	pr_info("ssv6xxx_sdio_exit\n");
++	sdio_unregister_driver(&ssv6xxx_sdio_driver);
++}
++
++EXPORT_SYMBOL(ssv6xxx_sdio_init);
++EXPORT_SYMBOL(ssv6xxx_sdio_exit);
+diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
+new file mode 100644
+index 000000000000..57aefd3bf9fa
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SDIO_DEF_H_
++#define _SDIO_DEF_H_
++#include <linux/scatterlist.h>
++#define BASE_SDIO 0
++#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00)
++#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01)
++#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02)
++#define REG_INT_MASK (BASE_SDIO + 0x04)
++#define REG_INT_STATUS (BASE_SDIO + 0x08)
++#define REG_INT_TRIGGER (BASE_SDIO + 0x09)
++#define REG_Fn1_STATUS (BASE_SDIO + 0x0c)
++#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10)
++#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11)
++#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12)
++#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13)
++#define REG_CARD_RCA_0 (BASE_SDIO + 0x20)
++#define REG_CARD_RCA_1 (BASE_SDIO + 0x21)
++#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24)
++#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25)
++#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55)
++#define REG_PMU_WAKEUP (BASE_SDIO + 0x67)
++#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70)
++#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71)
++#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72)
++#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98)
++#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99)
++#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a)
++#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c)
++#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d)
++#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e)
++#define SDIO_DEF_BLOCK_SIZE 0x80
++#if (SDIO_DEF_BLOCK_SIZE % 8)
++#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
++#endif
++#define SDIO_DEF_OUTPUT_TIMING 0
++#define SDIO_DEF_BLOCK_MODE_THRD 128
++#if (SDIO_DEF_BLOCK_MODE_THRD % 8)
++#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
++#endif
++#define SDIO_DEF_FORCE_BLOCK_MODE 0
++#define MAX_SCATTER_ENTRIES_PER_REQ 8
++struct sdio_scatter_item {
++	u8 *buf;
++	int len;
++};
++struct sdio_scatter_req {
++	u32 req;
++	u32 len;
++	int scat_entries;
++	struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];
++	struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
++};
++#define SDIO_READ 0x00000001
++#define SDIO_WRITE 0x00000002
++#define CMD53_ARG_READ 0
++#define CMD53_ARG_WRITE 1
++#define CMD53_ARG_BLOCK_BASIS 1
++#define CMD53_ARG_FIXED_ADDRESS 0
++#define CMD53_ARG_INCR_ADDRESS 1
++#define SDIO_DMA_BUFFER_LEN 2048
++#ifdef CONFIG_PM
++#define SDIO_COMMAND_BUFFER_LEN 256
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/cabrio.h b/drivers/net/wireless/ssv6051/include/cabrio.h
+new file mode 100644
+index 000000000000..0b1327865c6b
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/cabrio.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef CABRIO_H
++#define CABRIO_H
++#define SSV_VENDOR_ID 0x3030
++#define SSV_CABRIO_DEVID 0x3030
++#define SSV_SUBVENDOR_ID_NOG 0x0e11
++#define SSV_SUBVENDOR_ID_NEW_A 0x7065
++#define SSV_CABRIO_MAGIC 0x19641014
++#define SSV_AMPDU_LIMIT_MAX (64 * 1024 - 1)
++#define SSV_DEFAULT_NOISE_FLOOR -95
++#define SSVCABRIO_RSSI_BAD -128
++#define SSVCABRIO_NUM_CHANNELS 38
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200.h b/drivers/net/wireless/ssv6051/include/ssv6200.h
+new file mode 100644
+index 000000000000..22eaceaf285d
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200.h
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV6200_H_
++#define _SSV6200_H_
++#include <linux/device.h>
++#include <linux/interrupt.h>
++#include <net/mac80211.h>
++#ifdef ECLIPSE
++#include <ssv_mod_conf.h>
++#endif
++#include <ssv6200_reg.h>
++#include <ssv6200_aux.h>
++#include <hwif/hwif.h>
++#include <hci/ssv_hci.h>
++#include "ssv6200_common.h"
++#define SSV6200_TOTAL_ID 128
++#ifndef HUW_DRV
++#define SSV6200_ID_TX_THRESHOLD 19
++#define SSV6200_ID_RX_THRESHOLD 60
++#define SSV6200_PAGE_TX_THRESHOLD 115
++#define SSV6200_PAGE_RX_THRESHOLD 115
++#define SSV6XXX_AMPDU_DIVIDER (2)
++#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6XXX_AMPDU_DIVIDER))
++#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
++#else
++#undef SSV6200_ID_TX_THRESHOLD
++#undef SSV6200_ID_RX_THRESHOLD
++#undef SSV6200_PAGE_TX_THRESHOLD
++#undef SSV6200_PAGE_RX_THRESHOLD
++#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
++#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
++#define SSV6200_ID_TX_THRESHOLD 31
++#define SSV6200_ID_RX_THRESHOLD 31
++#define SSV6200_PAGE_TX_THRESHOLD 61
++#define SSV6200_PAGE_RX_THRESHOLD 61
++#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
++#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
++#endif
++#define SSV6200_ID_NUMBER (128)
++#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
++#define SSV6200_ID_AC_RESERVED 1
++#define SSV6200_ID_AC_BK_OUT_QUEUE 8
++#define SSV6200_ID_AC_BE_OUT_QUEUE 15
++#define SSV6200_ID_AC_VI_OUT_QUEUE 16
++#define SSV6200_ID_AC_VO_OUT_QUEUE 16
++#define SSV6200_ID_MANAGER_QUEUE 8
++#define HW_MMU_PAGE_SHIFT 0x8
++#define HW_MMU_PAGE_MASK 0xff
++#define SSV6200_BT_PRI_SMP_TIME 0
++#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0)
++#define SSV6200_WLAN_REMAIN_TIME 0
++#define BT_2WIRE_EN_MSK 0x00000400
++struct txResourceControl {
++	u32 txUsePage:8;
++	u32 txUseID:6;
++	u32 edca0:4;
++	u32 edca1:4;
++	u32 edca2:5;
++	u32 edca3:5;
++};
++#include <ssv_cfg.h>
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_aux.h b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
+new file mode 100644
+index 000000000000..03ec3f07d330
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
+@@ -0,0 +1,18221 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define MCU_ENABLE_MSK 0x00000001
++#define MCU_ENABLE_I_MSK 0xfffffffe
++#define MCU_ENABLE_SFT 0
++#define MCU_ENABLE_HI 0
++#define MCU_ENABLE_SZ 1
++#define MAC_SW_RST_MSK 0x00000002
++#define MAC_SW_RST_I_MSK 0xfffffffd
++#define MAC_SW_RST_SFT 1
++#define MAC_SW_RST_HI 1
++#define MAC_SW_RST_SZ 1
++#define MCU_SW_RST_MSK 0x00000004
++#define MCU_SW_RST_I_MSK 0xfffffffb
++#define MCU_SW_RST_SFT 2
++#define MCU_SW_RST_HI 2
++#define MCU_SW_RST_SZ 1
++#define SDIO_SW_RST_MSK 0x00000008
++#define SDIO_SW_RST_I_MSK 0xfffffff7
++#define SDIO_SW_RST_SFT 3
++#define SDIO_SW_RST_HI 3
++#define SDIO_SW_RST_SZ 1
++#define SPI_SLV_SW_RST_MSK 0x00000010
++#define SPI_SLV_SW_RST_I_MSK 0xffffffef
++#define SPI_SLV_SW_RST_SFT 4
++#define SPI_SLV_SW_RST_HI 4
++#define SPI_SLV_SW_RST_SZ 1
++#define UART_SW_RST_MSK 0x00000020
++#define UART_SW_RST_I_MSK 0xffffffdf
++#define UART_SW_RST_SFT 5
++#define UART_SW_RST_HI 5
++#define UART_SW_RST_SZ 1
++#define DMA_SW_RST_MSK 0x00000040
++#define DMA_SW_RST_I_MSK 0xffffffbf
++#define DMA_SW_RST_SFT 6
++#define DMA_SW_RST_HI 6
++#define DMA_SW_RST_SZ 1
++#define WDT_SW_RST_MSK 0x00000080
++#define WDT_SW_RST_I_MSK 0xffffff7f
++#define WDT_SW_RST_SFT 7
++#define WDT_SW_RST_HI 7
++#define WDT_SW_RST_SZ 1
++#define I2C_SLV_SW_RST_MSK 0x00000100
++#define I2C_SLV_SW_RST_I_MSK 0xfffffeff
++#define I2C_SLV_SW_RST_SFT 8
++#define I2C_SLV_SW_RST_HI 8
++#define I2C_SLV_SW_RST_SZ 1
++#define INT_CTL_SW_RST_MSK 0x00000200
++#define INT_CTL_SW_RST_I_MSK 0xfffffdff
++#define INT_CTL_SW_RST_SFT 9
++#define INT_CTL_SW_RST_HI 9
++#define INT_CTL_SW_RST_SZ 1
++#define BTCX_SW_RST_MSK 0x00000400
++#define BTCX_SW_RST_I_MSK 0xfffffbff
++#define BTCX_SW_RST_SFT 10
++#define BTCX_SW_RST_HI 10
++#define BTCX_SW_RST_SZ 1
++#define GPIO_SW_RST_MSK 0x00000800
++#define GPIO_SW_RST_I_MSK 0xfffff7ff
++#define GPIO_SW_RST_SFT 11
++#define GPIO_SW_RST_HI 11
++#define GPIO_SW_RST_SZ 1
++#define US0TMR_SW_RST_MSK 0x00001000
++#define US0TMR_SW_RST_I_MSK 0xffffefff
++#define US0TMR_SW_RST_SFT 12
++#define US0TMR_SW_RST_HI 12
++#define US0TMR_SW_RST_SZ 1
++#define US1TMR_SW_RST_MSK 0x00002000
++#define US1TMR_SW_RST_I_MSK 0xffffdfff
++#define US1TMR_SW_RST_SFT 13
++#define US1TMR_SW_RST_HI 13
++#define US1TMR_SW_RST_SZ 1
++#define US2TMR_SW_RST_MSK 0x00004000
++#define US2TMR_SW_RST_I_MSK 0xffffbfff
++#define US2TMR_SW_RST_SFT 14
++#define US2TMR_SW_RST_HI 14
++#define US2TMR_SW_RST_SZ 1
++#define US3TMR_SW_RST_MSK 0x00008000
++#define US3TMR_SW_RST_I_MSK 0xffff7fff
++#define US3TMR_SW_RST_SFT 15
++#define US3TMR_SW_RST_HI 15
++#define US3TMR_SW_RST_SZ 1
++#define MS0TMR_SW_RST_MSK 0x00010000
++#define MS0TMR_SW_RST_I_MSK 0xfffeffff
++#define MS0TMR_SW_RST_SFT 16
++#define MS0TMR_SW_RST_HI 16
++#define MS0TMR_SW_RST_SZ 1
++#define MS1TMR_SW_RST_MSK 0x00020000
++#define MS1TMR_SW_RST_I_MSK 0xfffdffff
++#define MS1TMR_SW_RST_SFT 17
++#define MS1TMR_SW_RST_HI 17
++#define MS1TMR_SW_RST_SZ 1
++#define MS2TMR_SW_RST_MSK 0x00040000
++#define MS2TMR_SW_RST_I_MSK 0xfffbffff
++#define MS2TMR_SW_RST_SFT 18
++#define MS2TMR_SW_RST_HI 18
++#define MS2TMR_SW_RST_SZ 1
++#define MS3TMR_SW_RST_MSK 0x00080000
++#define MS3TMR_SW_RST_I_MSK 0xfff7ffff
++#define MS3TMR_SW_RST_SFT 19
++#define MS3TMR_SW_RST_HI 19
++#define MS3TMR_SW_RST_SZ 1
++#define RF_BB_SW_RST_MSK 0x00100000
++#define RF_BB_SW_RST_I_MSK 0xffefffff
++#define RF_BB_SW_RST_SFT 20
++#define RF_BB_SW_RST_HI 20
++#define RF_BB_SW_RST_SZ 1
++#define SYS_ALL_RST_MSK 0x00200000
++#define SYS_ALL_RST_I_MSK 0xffdfffff
++#define SYS_ALL_RST_SFT 21
++#define SYS_ALL_RST_HI 21
++#define SYS_ALL_RST_SZ 1
++#define DAT_UART_SW_RST_MSK 0x00400000
++#define DAT_UART_SW_RST_I_MSK 0xffbfffff
++#define DAT_UART_SW_RST_SFT 22
++#define DAT_UART_SW_RST_HI 22
++#define DAT_UART_SW_RST_SZ 1
++#define I2C_MST_SW_RST_MSK 0x00800000
++#define I2C_MST_SW_RST_I_MSK 0xff7fffff
++#define I2C_MST_SW_RST_SFT 23
++#define I2C_MST_SW_RST_HI 23
++#define I2C_MST_SW_RST_SZ 1
++#define RG_REBOOT_MSK 0x00000001
++#define RG_REBOOT_I_MSK 0xfffffffe
++#define RG_REBOOT_SFT 0
++#define RG_REBOOT_HI 0
++#define RG_REBOOT_SZ 1
++#define TRAP_IMG_FLS_MSK 0x00010000
++#define TRAP_IMG_FLS_I_MSK 0xfffeffff
++#define TRAP_IMG_FLS_SFT 16
++#define TRAP_IMG_FLS_HI 16
++#define TRAP_IMG_FLS_SZ 1
++#define TRAP_REBOOT_MSK 0x00020000
++#define TRAP_REBOOT_I_MSK 0xfffdffff
++#define TRAP_REBOOT_SFT 17
++#define TRAP_REBOOT_HI 17
++#define TRAP_REBOOT_SZ 1
++#define TRAP_BOOT_FLS_MSK 0x00040000
++#define TRAP_BOOT_FLS_I_MSK 0xfffbffff
++#define TRAP_BOOT_FLS_SFT 18
++#define TRAP_BOOT_FLS_HI 18
++#define TRAP_BOOT_FLS_SZ 1
++#define CHIP_ID_31_0_MSK 0xffffffff
++#define CHIP_ID_31_0_I_MSK 0x00000000
++#define CHIP_ID_31_0_SFT 0
++#define CHIP_ID_31_0_HI 31
++#define CHIP_ID_31_0_SZ 32
++#define CHIP_ID_63_32_MSK 0xffffffff
++#define CHIP_ID_63_32_I_MSK 0x00000000
++#define CHIP_ID_63_32_SFT 0
++#define CHIP_ID_63_32_HI 31
++#define CHIP_ID_63_32_SZ 32
++#define CHIP_ID_95_64_MSK 0xffffffff
++#define CHIP_ID_95_64_I_MSK 0x00000000
++#define CHIP_ID_95_64_SFT 0
++#define CHIP_ID_95_64_HI 31
++#define CHIP_ID_95_64_SZ 32
++#define CHIP_ID_127_96_MSK 0xffffffff
++#define CHIP_ID_127_96_I_MSK 0x00000000
++#define CHIP_ID_127_96_SFT 0
++#define CHIP_ID_127_96_HI 31
++#define CHIP_ID_127_96_SZ 32
++#define CK_SEL_1_0_MSK 0x00000003
++#define CK_SEL_1_0_I_MSK 0xfffffffc
++#define CK_SEL_1_0_SFT 0
++#define CK_SEL_1_0_HI 1
++#define CK_SEL_1_0_SZ 2
++#define CK_SEL_2_MSK 0x00000004
++#define CK_SEL_2_I_MSK 0xfffffffb
++#define CK_SEL_2_SFT 2
++#define CK_SEL_2_HI 2
++#define CK_SEL_2_SZ 1
++#define SYS_CLK_EN_MSK 0x00000001
++#define SYS_CLK_EN_I_MSK 0xfffffffe
++#define SYS_CLK_EN_SFT 0
++#define SYS_CLK_EN_HI 0
++#define SYS_CLK_EN_SZ 1
++#define MAC_CLK_EN_MSK 0x00000002
++#define MAC_CLK_EN_I_MSK 0xfffffffd
++#define MAC_CLK_EN_SFT 1
++#define MAC_CLK_EN_HI 1
++#define MAC_CLK_EN_SZ 1
++#define MCU_CLK_EN_MSK 0x00000004
++#define MCU_CLK_EN_I_MSK 0xfffffffb
++#define MCU_CLK_EN_SFT 2
++#define MCU_CLK_EN_HI 2
++#define MCU_CLK_EN_SZ 1
++#define SDIO_CLK_EN_MSK 0x00000008
++#define SDIO_CLK_EN_I_MSK 0xfffffff7
++#define SDIO_CLK_EN_SFT 3
++#define SDIO_CLK_EN_HI 3
++#define SDIO_CLK_EN_SZ 1
++#define SPI_SLV_CLK_EN_MSK 0x00000010
++#define SPI_SLV_CLK_EN_I_MSK 0xffffffef
++#define SPI_SLV_CLK_EN_SFT 4
++#define SPI_SLV_CLK_EN_HI 4
++#define SPI_SLV_CLK_EN_SZ 1
++#define UART_CLK_EN_MSK 0x00000020
++#define UART_CLK_EN_I_MSK 0xffffffdf
++#define UART_CLK_EN_SFT 5
++#define UART_CLK_EN_HI 5
++#define UART_CLK_EN_SZ 1
++#define DMA_CLK_EN_MSK 0x00000040
++#define DMA_CLK_EN_I_MSK 0xffffffbf
++#define DMA_CLK_EN_SFT 6
++#define DMA_CLK_EN_HI 6
++#define DMA_CLK_EN_SZ 1
++#define WDT_CLK_EN_MSK 0x00000080
++#define WDT_CLK_EN_I_MSK 0xffffff7f
++#define WDT_CLK_EN_SFT 7
++#define WDT_CLK_EN_HI 7
++#define WDT_CLK_EN_SZ 1
++#define I2C_SLV_CLK_EN_MSK 0x00000100
++#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff
++#define I2C_SLV_CLK_EN_SFT 8
++#define I2C_SLV_CLK_EN_HI 8
++#define I2C_SLV_CLK_EN_SZ 1
++#define INT_CTL_CLK_EN_MSK 0x00000200
++#define INT_CTL_CLK_EN_I_MSK 0xfffffdff
++#define INT_CTL_CLK_EN_SFT 9
++#define INT_CTL_CLK_EN_HI 9
++#define INT_CTL_CLK_EN_SZ 1
++#define BTCX_CLK_EN_MSK 0x00000400
++#define BTCX_CLK_EN_I_MSK 0xfffffbff
++#define BTCX_CLK_EN_SFT 10
++#define BTCX_CLK_EN_HI 10
++#define BTCX_CLK_EN_SZ 1
++#define GPIO_CLK_EN_MSK 0x00000800
++#define GPIO_CLK_EN_I_MSK 0xfffff7ff
++#define GPIO_CLK_EN_SFT 11
++#define GPIO_CLK_EN_HI 11
++#define GPIO_CLK_EN_SZ 1
++#define US0TMR_CLK_EN_MSK 0x00001000
++#define US0TMR_CLK_EN_I_MSK 0xffffefff
++#define US0TMR_CLK_EN_SFT 12
++#define US0TMR_CLK_EN_HI 12
++#define US0TMR_CLK_EN_SZ 1
++#define US1TMR_CLK_EN_MSK 0x00002000
++#define US1TMR_CLK_EN_I_MSK 0xffffdfff
++#define US1TMR_CLK_EN_SFT 13
++#define US1TMR_CLK_EN_HI 13
++#define US1TMR_CLK_EN_SZ 1
++#define US2TMR_CLK_EN_MSK 0x00004000
++#define US2TMR_CLK_EN_I_MSK 0xffffbfff
++#define US2TMR_CLK_EN_SFT 14
++#define US2TMR_CLK_EN_HI 14
++#define US2TMR_CLK_EN_SZ 1
++#define US3TMR_CLK_EN_MSK 0x00008000
++#define US3TMR_CLK_EN_I_MSK 0xffff7fff
++#define US3TMR_CLK_EN_SFT 15
++#define US3TMR_CLK_EN_HI 15
++#define US3TMR_CLK_EN_SZ 1
++#define MS0TMR_CLK_EN_MSK 0x00010000
++#define MS0TMR_CLK_EN_I_MSK 0xfffeffff
++#define MS0TMR_CLK_EN_SFT 16
++#define MS0TMR_CLK_EN_HI 16
++#define MS0TMR_CLK_EN_SZ 1
++#define MS1TMR_CLK_EN_MSK 0x00020000
++#define MS1TMR_CLK_EN_I_MSK 0xfffdffff
++#define MS1TMR_CLK_EN_SFT 17
++#define MS1TMR_CLK_EN_HI 17
++#define MS1TMR_CLK_EN_SZ 1
++#define MS2TMR_CLK_EN_MSK 0x00040000
++#define MS2TMR_CLK_EN_I_MSK 0xfffbffff
++#define MS2TMR_CLK_EN_SFT 18
++#define MS2TMR_CLK_EN_HI 18
++#define MS2TMR_CLK_EN_SZ 1
++#define MS3TMR_CLK_EN_MSK 0x00080000
++#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff
++#define MS3TMR_CLK_EN_SFT 19
++#define MS3TMR_CLK_EN_HI 19
++#define MS3TMR_CLK_EN_SZ 1
++#define BIST_CLK_EN_MSK 0x00100000
++#define BIST_CLK_EN_I_MSK 0xffefffff
++#define BIST_CLK_EN_SFT 20
++#define BIST_CLK_EN_HI 20
++#define BIST_CLK_EN_SZ 1
++#define I2C_MST_CLK_EN_MSK 0x00800000
++#define I2C_MST_CLK_EN_I_MSK 0xff7fffff
++#define I2C_MST_CLK_EN_SFT 23
++#define I2C_MST_CLK_EN_HI 23
++#define I2C_MST_CLK_EN_SZ 1
++#define BTCX_CSR_CLK_EN_MSK 0x00000400
++#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff
++#define BTCX_CSR_CLK_EN_SFT 10
++#define BTCX_CSR_CLK_EN_HI 10
++#define BTCX_CSR_CLK_EN_SZ 1
++#define MCU_DBG_SEL_MSK 0x0000003f
++#define MCU_DBG_SEL_I_MSK 0xffffffc0
++#define MCU_DBG_SEL_SFT 0
++#define MCU_DBG_SEL_HI 5
++#define MCU_DBG_SEL_SZ 6
++#define MCU_STOP_NOGRANT_MSK 0x00000100
++#define MCU_STOP_NOGRANT_I_MSK 0xfffffeff
++#define MCU_STOP_NOGRANT_SFT 8
++#define MCU_STOP_NOGRANT_HI 8
++#define MCU_STOP_NOGRANT_SZ 1
++#define MCU_STOP_ANYTIME_MSK 0x00000200
++#define MCU_STOP_ANYTIME_I_MSK 0xfffffdff
++#define MCU_STOP_ANYTIME_SFT 9
++#define MCU_STOP_ANYTIME_HI 9
++#define MCU_STOP_ANYTIME_SZ 1
++#define MCU_DBG_DATA_MSK 0xffffffff
++#define MCU_DBG_DATA_I_MSK 0x00000000
++#define MCU_DBG_DATA_SFT 0
++#define MCU_DBG_DATA_HI 31
++#define MCU_DBG_DATA_SZ 32
++#define AHB_SW_RST_MSK 0x00000001
++#define AHB_SW_RST_I_MSK 0xfffffffe
++#define AHB_SW_RST_SFT 0
++#define AHB_SW_RST_HI 0
++#define AHB_SW_RST_SZ 1
++#define AHB_ERR_RST_MSK 0x00000002
++#define AHB_ERR_RST_I_MSK 0xfffffffd
++#define AHB_ERR_RST_SFT 1
++#define AHB_ERR_RST_HI 1
++#define AHB_ERR_RST_SZ 1
++#define REG_AHB_DEBUG_MX_MSK 0x00000030
++#define REG_AHB_DEBUG_MX_I_MSK 0xffffffcf
++#define REG_AHB_DEBUG_MX_SFT 4
++#define REG_AHB_DEBUG_MX_HI 5
++#define REG_AHB_DEBUG_MX_SZ 2
++#define REG_PKT_W_NBRT_MSK 0x00000100
++#define REG_PKT_W_NBRT_I_MSK 0xfffffeff
++#define REG_PKT_W_NBRT_SFT 8
++#define REG_PKT_W_NBRT_HI 8
++#define REG_PKT_W_NBRT_SZ 1
++#define REG_PKT_R_NBRT_MSK 0x00000200
++#define REG_PKT_R_NBRT_I_MSK 0xfffffdff
++#define REG_PKT_R_NBRT_SFT 9
++#define REG_PKT_R_NBRT_HI 9
++#define REG_PKT_R_NBRT_SZ 1
++#define IQ_SRAM_SEL_0_MSK 0x00001000
++#define IQ_SRAM_SEL_0_I_MSK 0xffffefff
++#define IQ_SRAM_SEL_0_SFT 12
++#define IQ_SRAM_SEL_0_HI 12
++#define IQ_SRAM_SEL_0_SZ 1
++#define IQ_SRAM_SEL_1_MSK 0x00002000
++#define IQ_SRAM_SEL_1_I_MSK 0xffffdfff
++#define IQ_SRAM_SEL_1_SFT 13
++#define IQ_SRAM_SEL_1_HI 13
++#define IQ_SRAM_SEL_1_SZ 1
++#define IQ_SRAM_SEL_2_MSK 0x00004000
++#define IQ_SRAM_SEL_2_I_MSK 0xffffbfff
++#define IQ_SRAM_SEL_2_SFT 14
++#define IQ_SRAM_SEL_2_HI 14
++#define IQ_SRAM_SEL_2_SZ 1
++#define AHB_STATUS_MSK 0xffff0000
++#define AHB_STATUS_I_MSK 0x0000ffff
++#define AHB_STATUS_SFT 16
++#define AHB_STATUS_HI 31
++#define AHB_STATUS_SZ 16
++#define PARALLEL_DR_MSK 0x00000001
++#define PARALLEL_DR_I_MSK 0xfffffffe
++#define PARALLEL_DR_SFT 0
++#define PARALLEL_DR_HI 0
++#define PARALLEL_DR_SZ 1
++#define MBRUN_MSK 0x00000010
++#define MBRUN_I_MSK 0xffffffef
++#define MBRUN_SFT 4
++#define MBRUN_HI 4
++#define MBRUN_SZ 1
++#define SHIFT_DR_MSK 0x00000100
++#define SHIFT_DR_I_MSK 0xfffffeff
++#define SHIFT_DR_SFT 8
++#define SHIFT_DR_HI 8
++#define SHIFT_DR_SZ 1
++#define MODE_REG_SI_MSK 0x00000200
++#define MODE_REG_SI_I_MSK 0xfffffdff
++#define MODE_REG_SI_SFT 9
++#define MODE_REG_SI_HI 9
++#define MODE_REG_SI_SZ 1
++#define SIMULATION_MODE_MSK 0x00000400
++#define SIMULATION_MODE_I_MSK 0xfffffbff
++#define SIMULATION_MODE_SFT 10
++#define SIMULATION_MODE_HI 10
++#define SIMULATION_MODE_SZ 1
++#define DBIST_MODE_MSK 0x00000800
++#define DBIST_MODE_I_MSK 0xfffff7ff
++#define DBIST_MODE_SFT 11
++#define DBIST_MODE_HI 11
++#define DBIST_MODE_SZ 1
++#define MODE_REG_IN_MSK 0x001fffff
++#define MODE_REG_IN_I_MSK 0xffe00000
++#define MODE_REG_IN_SFT 0
++#define MODE_REG_IN_HI 20
++#define MODE_REG_IN_SZ 21
++#define MODE_REG_OUT_MCU_MSK 0x001fffff
++#define MODE_REG_OUT_MCU_I_MSK 0xffe00000
++#define MODE_REG_OUT_MCU_SFT 0
++#define MODE_REG_OUT_MCU_HI 20
++#define MODE_REG_OUT_MCU_SZ 21
++#define MODE_REG_SO_MCU_MSK 0x80000000
++#define MODE_REG_SO_MCU_I_MSK 0x7fffffff
++#define MODE_REG_SO_MCU_SFT 31
++#define MODE_REG_SO_MCU_HI 31
++#define MODE_REG_SO_MCU_SZ 1
++#define MONITOR_BUS_MCU_31_0_MSK 0xffffffff
++#define MONITOR_BUS_MCU_31_0_I_MSK 0x00000000
++#define MONITOR_BUS_MCU_31_0_SFT 0
++#define MONITOR_BUS_MCU_31_0_HI 31
++#define MONITOR_BUS_MCU_31_0_SZ 32
++#define MONITOR_BUS_MCU_33_32_MSK 0x00000003
++#define MONITOR_BUS_MCU_33_32_I_MSK 0xfffffffc
++#define MONITOR_BUS_MCU_33_32_SFT 0
++#define MONITOR_BUS_MCU_33_32_HI 1
++#define MONITOR_BUS_MCU_33_32_SZ 2
++#define TB_ADR_SEL_MSK 0x0000ffff
++#define TB_ADR_SEL_I_MSK 0xffff0000
++#define TB_ADR_SEL_SFT 0
++#define TB_ADR_SEL_HI 15
++#define TB_ADR_SEL_SZ 16
++#define TB_CS_MSK 0x80000000
++#define TB_CS_I_MSK 0x7fffffff
++#define TB_CS_SFT 31
++#define TB_CS_HI 31
++#define TB_CS_SZ 1
++#define TB_RDATA_MSK 0xffffffff
++#define TB_RDATA_I_MSK 0x00000000
++#define TB_RDATA_SFT 0
++#define TB_RDATA_HI 31
++#define TB_RDATA_SZ 32
++#define UART_W2B_EN_MSK 0x00000001
++#define UART_W2B_EN_I_MSK 0xfffffffe
++#define UART_W2B_EN_SFT 0
++#define UART_W2B_EN_HI 0
++#define UART_W2B_EN_SZ 1
++#define DATA_UART_W2B_EN_MSK 0x00000010
++#define DATA_UART_W2B_EN_I_MSK 0xffffffef
++#define DATA_UART_W2B_EN_SFT 4
++#define DATA_UART_W2B_EN_HI 4
++#define DATA_UART_W2B_EN_SZ 1
++#define AHB_ILL_ADDR_MSK 0xffffffff
++#define AHB_ILL_ADDR_I_MSK 0x00000000
++#define AHB_ILL_ADDR_SFT 0
++#define AHB_ILL_ADDR_HI 31
++#define AHB_ILL_ADDR_SZ 32
++#define AHB_FEN_ADDR_MSK 0xffffffff
++#define AHB_FEN_ADDR_I_MSK 0x00000000
++#define AHB_FEN_ADDR_SFT 0
++#define AHB_FEN_ADDR_HI 31
++#define AHB_FEN_ADDR_SZ 32
++#define ILL_ADDR_CLR_MSK 0x00000001
++#define ILL_ADDR_CLR_I_MSK 0xfffffffe
++#define ILL_ADDR_CLR_SFT 0
++#define ILL_ADDR_CLR_HI 0
++#define ILL_ADDR_CLR_SZ 1
++#define FENCE_HIT_CLR_MSK 0x00000002
++#define FENCE_HIT_CLR_I_MSK 0xfffffffd
++#define FENCE_HIT_CLR_SFT 1
++#define FENCE_HIT_CLR_HI 1
++#define FENCE_HIT_CLR_SZ 1
++#define ILL_ADDR_INT_MSK 0x00000010
++#define ILL_ADDR_INT_I_MSK 0xffffffef
++#define ILL_ADDR_INT_SFT 4
++#define ILL_ADDR_INT_HI 4
++#define ILL_ADDR_INT_SZ 1
++#define FENCE_HIT_INT_MSK 0x00000020
++#define FENCE_HIT_INT_I_MSK 0xffffffdf
++#define FENCE_HIT_INT_SFT 5
++#define FENCE_HIT_INT_HI 5
++#define FENCE_HIT_INT_SZ 1
++#define PWM_INI_VALUE_P_A_MSK 0x000000ff
++#define PWM_INI_VALUE_P_A_I_MSK 0xffffff00
++#define PWM_INI_VALUE_P_A_SFT 0
++#define PWM_INI_VALUE_P_A_HI 7
++#define PWM_INI_VALUE_P_A_SZ 8
++#define PWM_INI_VALUE_N_A_MSK 0x0000ff00
++#define PWM_INI_VALUE_N_A_I_MSK 0xffff00ff
++#define PWM_INI_VALUE_N_A_SFT 8
++#define PWM_INI_VALUE_N_A_HI 15
++#define PWM_INI_VALUE_N_A_SZ 8
++#define PWM_POST_SCALER_A_MSK 0x000f0000
++#define PWM_POST_SCALER_A_I_MSK 0xfff0ffff
++#define PWM_POST_SCALER_A_SFT 16
++#define PWM_POST_SCALER_A_HI 19
++#define PWM_POST_SCALER_A_SZ 4
++#define PWM_ALWAYSON_A_MSK 0x20000000
++#define PWM_ALWAYSON_A_I_MSK 0xdfffffff
++#define PWM_ALWAYSON_A_SFT 29
++#define PWM_ALWAYSON_A_HI 29
++#define PWM_ALWAYSON_A_SZ 1
++#define PWM_INVERT_A_MSK 0x40000000
++#define PWM_INVERT_A_I_MSK 0xbfffffff
++#define PWM_INVERT_A_SFT 30
++#define PWM_INVERT_A_HI 30
++#define PWM_INVERT_A_SZ 1
++#define PWM_ENABLE_A_MSK 0x80000000
++#define PWM_ENABLE_A_I_MSK 0x7fffffff
++#define PWM_ENABLE_A_SFT 31
++#define PWM_ENABLE_A_HI 31
++#define PWM_ENABLE_A_SZ 1
++#define PWM_INI_VALUE_P_B_MSK 0x000000ff
++#define PWM_INI_VALUE_P_B_I_MSK 0xffffff00
++#define PWM_INI_VALUE_P_B_SFT 0
++#define PWM_INI_VALUE_P_B_HI 7
++#define PWM_INI_VALUE_P_B_SZ 8
++#define PWM_INI_VALUE_N_B_MSK 0x0000ff00
++#define PWM_INI_VALUE_N_B_I_MSK 0xffff00ff
++#define PWM_INI_VALUE_N_B_SFT 8
++#define PWM_INI_VALUE_N_B_HI 15
++#define PWM_INI_VALUE_N_B_SZ 8
++#define PWM_POST_SCALER_B_MSK 0x000f0000
++#define PWM_POST_SCALER_B_I_MSK 0xfff0ffff
++#define PWM_POST_SCALER_B_SFT 16
++#define PWM_POST_SCALER_B_HI 19
++#define PWM_POST_SCALER_B_SZ 4
++#define PWM_ALWAYSON_B_MSK 0x20000000
++#define PWM_ALWAYSON_B_I_MSK 0xdfffffff
++#define PWM_ALWAYSON_B_SFT 29
++#define PWM_ALWAYSON_B_HI 29
++#define PWM_ALWAYSON_B_SZ 1
++#define PWM_INVERT_B_MSK 0x40000000
++#define PWM_INVERT_B_I_MSK 0xbfffffff
++#define PWM_INVERT_B_SFT 30
++#define PWM_INVERT_B_HI 30
++#define PWM_INVERT_B_SZ 1
++#define PWM_ENABLE_B_MSK 0x80000000
++#define PWM_ENABLE_B_I_MSK 0x7fffffff
++#define PWM_ENABLE_B_SFT 31
++#define PWM_ENABLE_B_HI 31
++#define PWM_ENABLE_B_SZ 1
++#define HBUSREQ_LOCK_MSK 0x00001fff
++#define HBUSREQ_LOCK_I_MSK 0xffffe000
++#define HBUSREQ_LOCK_SFT 0
++#define HBUSREQ_LOCK_HI 12
++#define HBUSREQ_LOCK_SZ 13
++#define HBURST_LOCK_MSK 0x00001fff
++#define HBURST_LOCK_I_MSK 0xffffe000
++#define HBURST_LOCK_SFT 0
++#define HBURST_LOCK_HI 12
++#define HBURST_LOCK_SZ 13
++#define PRESCALER_USTIMER_MSK 0x000001ff
++#define PRESCALER_USTIMER_I_MSK 0xfffffe00
++#define PRESCALER_USTIMER_SFT 0
++#define PRESCALER_USTIMER_HI 8
++#define PRESCALER_USTIMER_SZ 9
++#define MODE_REG_IN_MMU_MSK 0x0000ffff
++#define MODE_REG_IN_MMU_I_MSK 0xffff0000
++#define MODE_REG_IN_MMU_SFT 0
++#define MODE_REG_IN_MMU_HI 15
++#define MODE_REG_IN_MMU_SZ 16
++#define MODE_REG_OUT_MMU_MSK 0x0000ffff
++#define MODE_REG_OUT_MMU_I_MSK 0xffff0000
++#define MODE_REG_OUT_MMU_SFT 0
++#define MODE_REG_OUT_MMU_HI 15
++#define MODE_REG_OUT_MMU_SZ 16
++#define MODE_REG_SO_MMU_MSK 0x80000000
++#define MODE_REG_SO_MMU_I_MSK 0x7fffffff
++#define MODE_REG_SO_MMU_SFT 31
++#define MODE_REG_SO_MMU_HI 31
++#define MODE_REG_SO_MMU_SZ 1
++#define MONITOR_BUS_MMU_MSK 0x0007ffff
++#define MONITOR_BUS_MMU_I_MSK 0xfff80000
++#define MONITOR_BUS_MMU_SFT 0
++#define MONITOR_BUS_MMU_HI 18
++#define MONITOR_BUS_MMU_SZ 19
++#define TEST_MODE0_MSK 0x00000001
++#define TEST_MODE0_I_MSK 0xfffffffe
++#define TEST_MODE0_SFT 0
++#define TEST_MODE0_HI 0
++#define TEST_MODE0_SZ 1
++#define TEST_MODE1_MSK 0x00000002
++#define TEST_MODE1_I_MSK 0xfffffffd
++#define TEST_MODE1_SFT 1
++#define TEST_MODE1_HI 1
++#define TEST_MODE1_SZ 1
++#define TEST_MODE2_MSK 0x00000004
++#define TEST_MODE2_I_MSK 0xfffffffb
++#define TEST_MODE2_SFT 2
++#define TEST_MODE2_HI 2
++#define TEST_MODE2_SZ 1
++#define TEST_MODE3_MSK 0x00000008
++#define TEST_MODE3_I_MSK 0xfffffff7
++#define TEST_MODE3_SFT 3
++#define TEST_MODE3_HI 3
++#define TEST_MODE3_SZ 1
++#define TEST_MODE4_MSK 0x00000010
++#define TEST_MODE4_I_MSK 0xffffffef
++#define TEST_MODE4_SFT 4
++#define TEST_MODE4_HI 4
++#define TEST_MODE4_SZ 1
++#define TEST_MODE_ALL_MSK 0x00000020
++#define TEST_MODE_ALL_I_MSK 0xffffffdf
++#define TEST_MODE_ALL_SFT 5
++#define TEST_MODE_ALL_HI 5
++#define TEST_MODE_ALL_SZ 1
++#define WDT_INIT_MSK 0x00000001
++#define WDT_INIT_I_MSK 0xfffffffe
++#define WDT_INIT_SFT 0
++#define WDT_INIT_HI 0
++#define WDT_INIT_SZ 1
++#define SD_HOST_INIT_MSK 0x00000002
++#define SD_HOST_INIT_I_MSK 0xfffffffd
++#define SD_HOST_INIT_SFT 1
++#define SD_HOST_INIT_HI 1
++#define SD_HOST_INIT_SZ 1
++#define ALLOW_SD_RESET_MSK 0x00000001
++#define ALLOW_SD_RESET_I_MSK 0xfffffffe
++#define ALLOW_SD_RESET_SFT 0
++#define ALLOW_SD_RESET_HI 0
++#define ALLOW_SD_RESET_SZ 1
++#define UART_NRTS_MSK 0x00000001
++#define UART_NRTS_I_MSK 0xfffffffe
++#define UART_NRTS_SFT 0
++#define UART_NRTS_HI 0
++#define UART_NRTS_SZ 1
++#define UART_NCTS_MSK 0x00000002
++#define UART_NCTS_I_MSK 0xfffffffd
++#define UART_NCTS_SFT 1
++#define UART_NCTS_HI 1
++#define UART_NCTS_SZ 1
++#define TU0_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU0_TM_INIT_VALUE_SFT 0
++#define TU0_TM_INIT_VALUE_HI 15
++#define TU0_TM_INIT_VALUE_SZ 16
++#define TU0_TM_MODE_MSK 0x00010000
++#define TU0_TM_MODE_I_MSK 0xfffeffff
++#define TU0_TM_MODE_SFT 16
++#define TU0_TM_MODE_HI 16
++#define TU0_TM_MODE_SZ 1
++#define TU0_TM_INT_STS_DONE_MSK 0x00020000
++#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU0_TM_INT_STS_DONE_SFT 17
++#define TU0_TM_INT_STS_DONE_HI 17
++#define TU0_TM_INT_STS_DONE_SZ 1
++#define TU0_TM_INT_MASK_MSK 0x00040000
++#define TU0_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU0_TM_INT_MASK_SFT 18
++#define TU0_TM_INT_MASK_HI 18
++#define TU0_TM_INT_MASK_SZ 1
++#define TU0_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU0_TM_CUR_VALUE_SFT 0
++#define TU0_TM_CUR_VALUE_HI 15
++#define TU0_TM_CUR_VALUE_SZ 16
++#define TU1_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU1_TM_INIT_VALUE_SFT 0
++#define TU1_TM_INIT_VALUE_HI 15
++#define TU1_TM_INIT_VALUE_SZ 16
++#define TU1_TM_MODE_MSK 0x00010000
++#define TU1_TM_MODE_I_MSK 0xfffeffff
++#define TU1_TM_MODE_SFT 16
++#define TU1_TM_MODE_HI 16
++#define TU1_TM_MODE_SZ 1
++#define TU1_TM_INT_STS_DONE_MSK 0x00020000
++#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU1_TM_INT_STS_DONE_SFT 17
++#define TU1_TM_INT_STS_DONE_HI 17
++#define TU1_TM_INT_STS_DONE_SZ 1
++#define TU1_TM_INT_MASK_MSK 0x00040000
++#define TU1_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU1_TM_INT_MASK_SFT 18
++#define TU1_TM_INT_MASK_HI 18
++#define TU1_TM_INT_MASK_SZ 1
++#define TU1_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU1_TM_CUR_VALUE_SFT 0
++#define TU1_TM_CUR_VALUE_HI 15
++#define TU1_TM_CUR_VALUE_SZ 16
++#define TU2_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU2_TM_INIT_VALUE_SFT 0
++#define TU2_TM_INIT_VALUE_HI 15
++#define TU2_TM_INIT_VALUE_SZ 16
++#define TU2_TM_MODE_MSK 0x00010000
++#define TU2_TM_MODE_I_MSK 0xfffeffff
++#define TU2_TM_MODE_SFT 16
++#define TU2_TM_MODE_HI 16
++#define TU2_TM_MODE_SZ 1
++#define TU2_TM_INT_STS_DONE_MSK 0x00020000
++#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU2_TM_INT_STS_DONE_SFT 17
++#define TU2_TM_INT_STS_DONE_HI 17
++#define TU2_TM_INT_STS_DONE_SZ 1
++#define TU2_TM_INT_MASK_MSK 0x00040000
++#define TU2_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU2_TM_INT_MASK_SFT 18
++#define TU2_TM_INT_MASK_HI 18
++#define TU2_TM_INT_MASK_SZ 1
++#define TU2_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU2_TM_CUR_VALUE_SFT 0
++#define TU2_TM_CUR_VALUE_HI 15
++#define TU2_TM_CUR_VALUE_SZ 16
++#define TU3_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU3_TM_INIT_VALUE_SFT 0
++#define TU3_TM_INIT_VALUE_HI 15
++#define TU3_TM_INIT_VALUE_SZ 16
++#define TU3_TM_MODE_MSK 0x00010000
++#define TU3_TM_MODE_I_MSK 0xfffeffff
++#define TU3_TM_MODE_SFT 16
++#define TU3_TM_MODE_HI 16
++#define TU3_TM_MODE_SZ 1
++#define TU3_TM_INT_STS_DONE_MSK 0x00020000
++#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU3_TM_INT_STS_DONE_SFT 17
++#define TU3_TM_INT_STS_DONE_HI 17
++#define TU3_TM_INT_STS_DONE_SZ 1
++#define TU3_TM_INT_MASK_MSK 0x00040000
++#define TU3_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU3_TM_INT_MASK_SFT 18
++#define TU3_TM_INT_MASK_HI 18
++#define TU3_TM_INT_MASK_SZ 1
++#define TU3_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU3_TM_CUR_VALUE_SFT 0
++#define TU3_TM_CUR_VALUE_HI 15
++#define TU3_TM_CUR_VALUE_SZ 16
++#define TM0_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM0_TM_INIT_VALUE_SFT 0
++#define TM0_TM_INIT_VALUE_HI 15
++#define TM0_TM_INIT_VALUE_SZ 16
++#define TM0_TM_MODE_MSK 0x00010000
++#define TM0_TM_MODE_I_MSK 0xfffeffff
++#define TM0_TM_MODE_SFT 16
++#define TM0_TM_MODE_HI 16
++#define TM0_TM_MODE_SZ 1
++#define TM0_TM_INT_STS_DONE_MSK 0x00020000
++#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM0_TM_INT_STS_DONE_SFT 17
++#define TM0_TM_INT_STS_DONE_HI 17
++#define TM0_TM_INT_STS_DONE_SZ 1
++#define TM0_TM_INT_MASK_MSK 0x00040000
++#define TM0_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM0_TM_INT_MASK_SFT 18
++#define TM0_TM_INT_MASK_HI 18
++#define TM0_TM_INT_MASK_SZ 1
++#define TM0_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM0_TM_CUR_VALUE_SFT 0
++#define TM0_TM_CUR_VALUE_HI 15
++#define TM0_TM_CUR_VALUE_SZ 16
++#define TM1_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM1_TM_INIT_VALUE_SFT 0
++#define TM1_TM_INIT_VALUE_HI 15
++#define TM1_TM_INIT_VALUE_SZ 16
++#define TM1_TM_MODE_MSK 0x00010000
++#define TM1_TM_MODE_I_MSK 0xfffeffff
++#define TM1_TM_MODE_SFT 16
++#define TM1_TM_MODE_HI 16
++#define TM1_TM_MODE_SZ 1
++#define TM1_TM_INT_STS_DONE_MSK 0x00020000
++#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM1_TM_INT_STS_DONE_SFT 17
++#define TM1_TM_INT_STS_DONE_HI 17
++#define TM1_TM_INT_STS_DONE_SZ 1
++#define TM1_TM_INT_MASK_MSK 0x00040000
++#define TM1_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM1_TM_INT_MASK_SFT 18
++#define TM1_TM_INT_MASK_HI 18
++#define TM1_TM_INT_MASK_SZ 1
++#define TM1_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM1_TM_CUR_VALUE_SFT 0
++#define TM1_TM_CUR_VALUE_HI 15
++#define TM1_TM_CUR_VALUE_SZ 16
++#define TM2_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM2_TM_INIT_VALUE_SFT 0
++#define TM2_TM_INIT_VALUE_HI 15
++#define TM2_TM_INIT_VALUE_SZ 16
++#define TM2_TM_MODE_MSK 0x00010000
++#define TM2_TM_MODE_I_MSK 0xfffeffff
++#define TM2_TM_MODE_SFT 16
++#define TM2_TM_MODE_HI 16
++#define TM2_TM_MODE_SZ 1
++#define TM2_TM_INT_STS_DONE_MSK 0x00020000
++#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM2_TM_INT_STS_DONE_SFT 17
++#define TM2_TM_INT_STS_DONE_HI 17
++#define TM2_TM_INT_STS_DONE_SZ 1
++#define TM2_TM_INT_MASK_MSK 0x00040000
++#define TM2_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM2_TM_INT_MASK_SFT 18
++#define TM2_TM_INT_MASK_HI 18
++#define TM2_TM_INT_MASK_SZ 1
++#define TM2_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM2_TM_CUR_VALUE_SFT 0
++#define TM2_TM_CUR_VALUE_HI 15
++#define TM2_TM_CUR_VALUE_SZ 16
++#define TM3_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM3_TM_INIT_VALUE_SFT 0
++#define TM3_TM_INIT_VALUE_HI 15
++#define TM3_TM_INIT_VALUE_SZ 16
++#define TM3_TM_MODE_MSK 0x00010000
++#define TM3_TM_MODE_I_MSK 0xfffeffff
++#define TM3_TM_MODE_SFT 16
++#define TM3_TM_MODE_HI 16
++#define TM3_TM_MODE_SZ 1
++#define TM3_TM_INT_STS_DONE_MSK 0x00020000
++#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM3_TM_INT_STS_DONE_SFT 17
++#define TM3_TM_INT_STS_DONE_HI 17
++#define TM3_TM_INT_STS_DONE_SZ 1
++#define TM3_TM_INT_MASK_MSK 0x00040000
++#define TM3_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM3_TM_INT_MASK_SFT 18
++#define TM3_TM_INT_MASK_HI 18
++#define TM3_TM_INT_MASK_SZ 1
++#define TM3_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM3_TM_CUR_VALUE_SFT 0
++#define TM3_TM_CUR_VALUE_HI 15
++#define TM3_TM_CUR_VALUE_SZ 16
++#define MCU_WDT_TIME_CNT_MSK 0x0000ffff
++#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000
++#define MCU_WDT_TIME_CNT_SFT 0
++#define MCU_WDT_TIME_CNT_HI 15
++#define MCU_WDT_TIME_CNT_SZ 16
++#define MCU_WDT_STATUS_MSK 0x00020000
++#define MCU_WDT_STATUS_I_MSK 0xfffdffff
++#define MCU_WDT_STATUS_SFT 17
++#define MCU_WDT_STATUS_HI 17
++#define MCU_WDT_STATUS_SZ 1
++#define MCU_WDOG_ENA_MSK 0x80000000
++#define MCU_WDOG_ENA_I_MSK 0x7fffffff
++#define MCU_WDOG_ENA_SFT 31
++#define MCU_WDOG_ENA_HI 31
++#define MCU_WDOG_ENA_SZ 1
++#define SYS_WDT_TIME_CNT_MSK 0x0000ffff
++#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000
++#define SYS_WDT_TIME_CNT_SFT 0
++#define SYS_WDT_TIME_CNT_HI 15
++#define SYS_WDT_TIME_CNT_SZ 16
++#define SYS_WDT_STATUS_MSK 0x00020000
++#define SYS_WDT_STATUS_I_MSK 0xfffdffff
++#define SYS_WDT_STATUS_SFT 17
++#define SYS_WDT_STATUS_HI 17
++#define SYS_WDT_STATUS_SZ 1
++#define SYS_WDOG_ENA_MSK 0x80000000
++#define SYS_WDOG_ENA_I_MSK 0x7fffffff
++#define SYS_WDOG_ENA_SFT 31
++#define SYS_WDOG_ENA_HI 31
++#define SYS_WDOG_ENA_SZ 1
++#define XLNA_EN_O_OE_MSK 0x00000001
++#define XLNA_EN_O_OE_I_MSK 0xfffffffe
++#define XLNA_EN_O_OE_SFT 0
++#define XLNA_EN_O_OE_HI 0
++#define XLNA_EN_O_OE_SZ 1
++#define XLNA_EN_O_PE_MSK 0x00000002
++#define XLNA_EN_O_PE_I_MSK 0xfffffffd
++#define XLNA_EN_O_PE_SFT 1
++#define XLNA_EN_O_PE_HI 1
++#define XLNA_EN_O_PE_SZ 1
++#define PAD6_IE_MSK 0x00000008
++#define PAD6_IE_I_MSK 0xfffffff7
++#define PAD6_IE_SFT 3
++#define PAD6_IE_HI 3
++#define PAD6_IE_SZ 1
++#define PAD6_SEL_I_MSK 0x00000030
++#define PAD6_SEL_I_I_MSK 0xffffffcf
++#define PAD6_SEL_I_SFT 4
++#define PAD6_SEL_I_HI 5
++#define PAD6_SEL_I_SZ 2
++#define PAD6_OD_MSK 0x00000100
++#define PAD6_OD_I_MSK 0xfffffeff
++#define PAD6_OD_SFT 8
++#define PAD6_OD_HI 8
++#define PAD6_OD_SZ 1
++#define PAD6_SEL_O_MSK 0x00001000
++#define PAD6_SEL_O_I_MSK 0xffffefff
++#define PAD6_SEL_O_SFT 12
++#define PAD6_SEL_O_HI 12
++#define PAD6_SEL_O_SZ 1
++#define XLNA_EN_O_C_MSK 0x10000000
++#define XLNA_EN_O_C_I_MSK 0xefffffff
++#define XLNA_EN_O_C_SFT 28
++#define XLNA_EN_O_C_HI 28
++#define XLNA_EN_O_C_SZ 1
++#define WIFI_TX_SW_O_OE_MSK 0x00000001
++#define WIFI_TX_SW_O_OE_I_MSK 0xfffffffe
++#define WIFI_TX_SW_O_OE_SFT 0
++#define WIFI_TX_SW_O_OE_HI 0
++#define WIFI_TX_SW_O_OE_SZ 1
++#define WIFI_TX_SW_O_PE_MSK 0x00000002
++#define WIFI_TX_SW_O_PE_I_MSK 0xfffffffd
++#define WIFI_TX_SW_O_PE_SFT 1
++#define WIFI_TX_SW_O_PE_HI 1
++#define WIFI_TX_SW_O_PE_SZ 1
++#define PAD7_IE_MSK 0x00000008
++#define PAD7_IE_I_MSK 0xfffffff7
++#define PAD7_IE_SFT 3
++#define PAD7_IE_HI 3
++#define PAD7_IE_SZ 1
++#define PAD7_SEL_I_MSK 0x00000030
++#define PAD7_SEL_I_I_MSK 0xffffffcf
++#define PAD7_SEL_I_SFT 4
++#define PAD7_SEL_I_HI 5
++#define PAD7_SEL_I_SZ 2
++#define PAD7_OD_MSK 0x00000100
++#define PAD7_OD_I_MSK 0xfffffeff
++#define PAD7_OD_SFT 8
++#define PAD7_OD_HI 8
++#define PAD7_OD_SZ 1
++#define PAD7_SEL_O_MSK 0x00001000
++#define PAD7_SEL_O_I_MSK 0xffffefff
++#define PAD7_SEL_O_SFT 12
++#define PAD7_SEL_O_HI 12
++#define PAD7_SEL_O_SZ 1
++#define WIFI_TX_SW_O_C_MSK 0x10000000
++#define WIFI_TX_SW_O_C_I_MSK 0xefffffff
++#define WIFI_TX_SW_O_C_SFT 28
++#define WIFI_TX_SW_O_C_HI 28
++#define WIFI_TX_SW_O_C_SZ 1
++#define WIFI_RX_SW_O_OE_MSK 0x00000001
++#define WIFI_RX_SW_O_OE_I_MSK 0xfffffffe
++#define WIFI_RX_SW_O_OE_SFT 0
++#define WIFI_RX_SW_O_OE_HI 0
++#define WIFI_RX_SW_O_OE_SZ 1
++#define WIFI_RX_SW_O_PE_MSK 0x00000002
++#define WIFI_RX_SW_O_PE_I_MSK 0xfffffffd
++#define WIFI_RX_SW_O_PE_SFT 1
++#define WIFI_RX_SW_O_PE_HI 1
++#define WIFI_RX_SW_O_PE_SZ 1
++#define PAD8_IE_MSK 0x00000008
++#define PAD8_IE_I_MSK 0xfffffff7
++#define PAD8_IE_SFT 3
++#define PAD8_IE_HI 3
++#define PAD8_IE_SZ 1
++#define PAD8_SEL_I_MSK 0x00000030
++#define PAD8_SEL_I_I_MSK 0xffffffcf
++#define PAD8_SEL_I_SFT 4
++#define PAD8_SEL_I_HI 5
++#define PAD8_SEL_I_SZ 2
++#define PAD8_OD_MSK 0x00000100
++#define PAD8_OD_I_MSK 0xfffffeff
++#define PAD8_OD_SFT 8
++#define PAD8_OD_HI 8
++#define PAD8_OD_SZ 1
++#define WIFI_RX_SW_O_C_MSK 0x10000000
++#define WIFI_RX_SW_O_C_I_MSK 0xefffffff
++#define WIFI_RX_SW_O_C_SFT 28
++#define WIFI_RX_SW_O_C_HI 28
++#define WIFI_RX_SW_O_C_SZ 1
++#define BT_SW_O_OE_MSK 0x00000001
++#define BT_SW_O_OE_I_MSK 0xfffffffe
++#define BT_SW_O_OE_SFT 0
++#define BT_SW_O_OE_HI 0
++#define BT_SW_O_OE_SZ 1
++#define BT_SW_O_PE_MSK 0x00000002
++#define BT_SW_O_PE_I_MSK 0xfffffffd
++#define BT_SW_O_PE_SFT 1
++#define BT_SW_O_PE_HI 1
++#define BT_SW_O_PE_SZ 1
++#define PAD9_IE_MSK 0x00000008
++#define PAD9_IE_I_MSK 0xfffffff7
++#define PAD9_IE_SFT 3
++#define PAD9_IE_HI 3
++#define PAD9_IE_SZ 1
++#define PAD9_SEL_I_MSK 0x00000030
++#define PAD9_SEL_I_I_MSK 0xffffffcf
++#define PAD9_SEL_I_SFT 4
++#define PAD9_SEL_I_HI 5
++#define PAD9_SEL_I_SZ 2
++#define PAD9_OD_MSK 0x00000100
++#define PAD9_OD_I_MSK 0xfffffeff
++#define PAD9_OD_SFT 8
++#define PAD9_OD_HI 8
++#define PAD9_OD_SZ 1
++#define PAD9_SEL_O_MSK 0x00001000
++#define PAD9_SEL_O_I_MSK 0xffffefff
++#define PAD9_SEL_O_SFT 12
++#define PAD9_SEL_O_HI 12
++#define PAD9_SEL_O_SZ 1
++#define BT_SW_O_C_MSK 0x10000000
++#define BT_SW_O_C_I_MSK 0xefffffff
++#define BT_SW_O_C_SFT 28
++#define BT_SW_O_C_HI 28
++#define BT_SW_O_C_SZ 1
++#define XPA_EN_O_OE_MSK 0x00000001
++#define XPA_EN_O_OE_I_MSK 0xfffffffe
++#define XPA_EN_O_OE_SFT 0
++#define XPA_EN_O_OE_HI 0
++#define XPA_EN_O_OE_SZ 1
++#define XPA_EN_O_PE_MSK 0x00000002
++#define XPA_EN_O_PE_I_MSK 0xfffffffd
++#define XPA_EN_O_PE_SFT 1
++#define XPA_EN_O_PE_HI 1
++#define XPA_EN_O_PE_SZ 1
++#define PAD11_IE_MSK 0x00000008
++#define PAD11_IE_I_MSK 0xfffffff7
++#define PAD11_IE_SFT 3
++#define PAD11_IE_HI 3
++#define PAD11_IE_SZ 1
++#define PAD11_SEL_I_MSK 0x00000030
++#define PAD11_SEL_I_I_MSK 0xffffffcf
++#define PAD11_SEL_I_SFT 4
++#define PAD11_SEL_I_HI 5
++#define PAD11_SEL_I_SZ 2
++#define PAD11_OD_MSK 0x00000100
++#define PAD11_OD_I_MSK 0xfffffeff
++#define PAD11_OD_SFT 8
++#define PAD11_OD_HI 8
++#define PAD11_OD_SZ 1
++#define PAD11_SEL_O_MSK 0x00001000
++#define PAD11_SEL_O_I_MSK 0xffffefff
++#define PAD11_SEL_O_SFT 12
++#define PAD11_SEL_O_HI 12
++#define PAD11_SEL_O_SZ 1
++#define XPA_EN_O_C_MSK 0x10000000
++#define XPA_EN_O_C_I_MSK 0xefffffff
++#define XPA_EN_O_C_SFT 28
++#define XPA_EN_O_C_HI 28
++#define XPA_EN_O_C_SZ 1
++#define PAD15_OE_MSK 0x00000001
++#define PAD15_OE_I_MSK 0xfffffffe
++#define PAD15_OE_SFT 0
++#define PAD15_OE_HI 0
++#define PAD15_OE_SZ 1
++#define PAD15_PE_MSK 0x00000002
++#define PAD15_PE_I_MSK 0xfffffffd
++#define PAD15_PE_SFT 1
++#define PAD15_PE_HI 1
++#define PAD15_PE_SZ 1
++#define PAD15_DS_MSK 0x00000004
++#define PAD15_DS_I_MSK 0xfffffffb
++#define PAD15_DS_SFT 2
++#define PAD15_DS_HI 2
++#define PAD15_DS_SZ 1
++#define PAD15_IE_MSK 0x00000008
++#define PAD15_IE_I_MSK 0xfffffff7
++#define PAD15_IE_SFT 3
++#define PAD15_IE_HI 3
++#define PAD15_IE_SZ 1
++#define PAD15_SEL_I_MSK 0x00000030
++#define PAD15_SEL_I_I_MSK 0xffffffcf
++#define PAD15_SEL_I_SFT 4
++#define PAD15_SEL_I_HI 5
++#define PAD15_SEL_I_SZ 2
++#define PAD15_OD_MSK 0x00000100
++#define PAD15_OD_I_MSK 0xfffffeff
++#define PAD15_OD_SFT 8
++#define PAD15_OD_HI 8
++#define PAD15_OD_SZ 1
++#define PAD15_SEL_O_MSK 0x00001000
++#define PAD15_SEL_O_I_MSK 0xffffefff
++#define PAD15_SEL_O_SFT 12
++#define PAD15_SEL_O_HI 12
++#define PAD15_SEL_O_SZ 1
++#define TEST_1_ID_MSK 0x10000000
++#define TEST_1_ID_I_MSK 0xefffffff
++#define TEST_1_ID_SFT 28
++#define TEST_1_ID_HI 28
++#define TEST_1_ID_SZ 1
++#define PAD16_OE_MSK 0x00000001
++#define PAD16_OE_I_MSK 0xfffffffe
++#define PAD16_OE_SFT 0
++#define PAD16_OE_HI 0
++#define PAD16_OE_SZ 1
++#define PAD16_PE_MSK 0x00000002
++#define PAD16_PE_I_MSK 0xfffffffd
++#define PAD16_PE_SFT 1
++#define PAD16_PE_HI 1
++#define PAD16_PE_SZ 1
++#define PAD16_DS_MSK 0x00000004
++#define PAD16_DS_I_MSK 0xfffffffb
++#define PAD16_DS_SFT 2
++#define PAD16_DS_HI 2
++#define PAD16_DS_SZ 1
++#define PAD16_IE_MSK 0x00000008
++#define PAD16_IE_I_MSK 0xfffffff7
++#define PAD16_IE_SFT 3
++#define PAD16_IE_HI 3
++#define PAD16_IE_SZ 1
++#define PAD16_SEL_I_MSK 0x00000030
++#define PAD16_SEL_I_I_MSK 0xffffffcf
++#define PAD16_SEL_I_SFT 4
++#define PAD16_SEL_I_HI 5
++#define PAD16_SEL_I_SZ 2
++#define PAD16_OD_MSK 0x00000100
++#define PAD16_OD_I_MSK 0xfffffeff
++#define PAD16_OD_SFT 8
++#define PAD16_OD_HI 8
++#define PAD16_OD_SZ 1
++#define PAD16_SEL_O_MSK 0x00001000
++#define PAD16_SEL_O_I_MSK 0xffffefff
++#define PAD16_SEL_O_SFT 12
++#define PAD16_SEL_O_HI 12
++#define PAD16_SEL_O_SZ 1
++#define TEST_2_ID_MSK 0x10000000
++#define TEST_2_ID_I_MSK 0xefffffff
++#define TEST_2_ID_SFT 28
++#define TEST_2_ID_HI 28
++#define TEST_2_ID_SZ 1
++#define PAD17_OE_MSK 0x00000001
++#define PAD17_OE_I_MSK 0xfffffffe
++#define PAD17_OE_SFT 0
++#define PAD17_OE_HI 0
++#define PAD17_OE_SZ 1
++#define PAD17_PE_MSK 0x00000002
++#define PAD17_PE_I_MSK 0xfffffffd
++#define PAD17_PE_SFT 1
++#define PAD17_PE_HI 1
++#define PAD17_PE_SZ 1
++#define PAD17_DS_MSK 0x00000004
++#define PAD17_DS_I_MSK 0xfffffffb
++#define PAD17_DS_SFT 2
++#define PAD17_DS_HI 2
++#define PAD17_DS_SZ 1
++#define PAD17_IE_MSK 0x00000008
++#define PAD17_IE_I_MSK 0xfffffff7
++#define PAD17_IE_SFT 3
++#define PAD17_IE_HI 3
++#define PAD17_IE_SZ 1
++#define PAD17_SEL_I_MSK 0x00000030
++#define PAD17_SEL_I_I_MSK 0xffffffcf
++#define PAD17_SEL_I_SFT 4
++#define PAD17_SEL_I_HI 5
++#define PAD17_SEL_I_SZ 2
++#define PAD17_OD_MSK 0x00000100
++#define PAD17_OD_I_MSK 0xfffffeff
++#define PAD17_OD_SFT 8
++#define PAD17_OD_HI 8
++#define PAD17_OD_SZ 1
++#define PAD17_SEL_O_MSK 0x00001000
++#define PAD17_SEL_O_I_MSK 0xffffefff
++#define PAD17_SEL_O_SFT 12
++#define PAD17_SEL_O_HI 12
++#define PAD17_SEL_O_SZ 1
++#define TEST_3_ID_MSK 0x10000000
++#define TEST_3_ID_I_MSK 0xefffffff
++#define TEST_3_ID_SFT 28
++#define TEST_3_ID_HI 28
++#define TEST_3_ID_SZ 1
++#define PAD18_OE_MSK 0x00000001
++#define PAD18_OE_I_MSK 0xfffffffe
++#define PAD18_OE_SFT 0
++#define PAD18_OE_HI 0
++#define PAD18_OE_SZ 1
++#define PAD18_PE_MSK 0x00000002
++#define PAD18_PE_I_MSK 0xfffffffd
++#define PAD18_PE_SFT 1
++#define PAD18_PE_HI 1
++#define PAD18_PE_SZ 1
++#define PAD18_DS_MSK 0x00000004
++#define PAD18_DS_I_MSK 0xfffffffb
++#define PAD18_DS_SFT 2
++#define PAD18_DS_HI 2
++#define PAD18_DS_SZ 1
++#define PAD18_IE_MSK 0x00000008
++#define PAD18_IE_I_MSK 0xfffffff7
++#define PAD18_IE_SFT 3
++#define PAD18_IE_HI 3
++#define PAD18_IE_SZ 1
++#define PAD18_SEL_I_MSK 0x00000030
++#define PAD18_SEL_I_I_MSK 0xffffffcf
++#define PAD18_SEL_I_SFT 4
++#define PAD18_SEL_I_HI 5
++#define PAD18_SEL_I_SZ 2
++#define PAD18_OD_MSK 0x00000100
++#define PAD18_OD_I_MSK 0xfffffeff
++#define PAD18_OD_SFT 8
++#define PAD18_OD_HI 8
++#define PAD18_OD_SZ 1
++#define PAD18_SEL_O_MSK 0x00003000
++#define PAD18_SEL_O_I_MSK 0xffffcfff
++#define PAD18_SEL_O_SFT 12
++#define PAD18_SEL_O_HI 13
++#define PAD18_SEL_O_SZ 2
++#define TEST_4_ID_MSK 0x10000000
++#define TEST_4_ID_I_MSK 0xefffffff
++#define TEST_4_ID_SFT 28
++#define TEST_4_ID_HI 28
++#define TEST_4_ID_SZ 1
++#define PAD19_OE_MSK 0x00000001
++#define PAD19_OE_I_MSK 0xfffffffe
++#define PAD19_OE_SFT 0
++#define PAD19_OE_HI 0
++#define PAD19_OE_SZ 1
++#define PAD19_PE_MSK 0x00000002
++#define PAD19_PE_I_MSK 0xfffffffd
++#define PAD19_PE_SFT 1
++#define PAD19_PE_HI 1
++#define PAD19_PE_SZ 1
++#define PAD19_DS_MSK 0x00000004
++#define PAD19_DS_I_MSK 0xfffffffb
++#define PAD19_DS_SFT 2
++#define PAD19_DS_HI 2
++#define PAD19_DS_SZ 1
++#define PAD19_IE_MSK 0x00000008
++#define PAD19_IE_I_MSK 0xfffffff7
++#define PAD19_IE_SFT 3
++#define PAD19_IE_HI 3
++#define PAD19_IE_SZ 1
++#define PAD19_SEL_I_MSK 0x00000030
++#define PAD19_SEL_I_I_MSK 0xffffffcf
++#define PAD19_SEL_I_SFT 4
++#define PAD19_SEL_I_HI 5
++#define PAD19_SEL_I_SZ 2
++#define PAD19_OD_MSK 0x00000100
++#define PAD19_OD_I_MSK 0xfffffeff
++#define PAD19_OD_SFT 8
++#define PAD19_OD_HI 8
++#define PAD19_OD_SZ 1
++#define PAD19_SEL_O_MSK 0x00007000
++#define PAD19_SEL_O_I_MSK 0xffff8fff
++#define PAD19_SEL_O_SFT 12
++#define PAD19_SEL_O_HI 14
++#define PAD19_SEL_O_SZ 3
++#define SHORT_TO_20_ID_MSK 0x10000000
++#define SHORT_TO_20_ID_I_MSK 0xefffffff
++#define SHORT_TO_20_ID_SFT 28
++#define SHORT_TO_20_ID_HI 28
++#define SHORT_TO_20_ID_SZ 1
++#define PAD20_OE_MSK 0x00000001
++#define PAD20_OE_I_MSK 0xfffffffe
++#define PAD20_OE_SFT 0
++#define PAD20_OE_HI 0
++#define PAD20_OE_SZ 1
++#define PAD20_PE_MSK 0x00000002
++#define PAD20_PE_I_MSK 0xfffffffd
++#define PAD20_PE_SFT 1
++#define PAD20_PE_HI 1
++#define PAD20_PE_SZ 1
++#define PAD20_DS_MSK 0x00000004
++#define PAD20_DS_I_MSK 0xfffffffb
++#define PAD20_DS_SFT 2
++#define PAD20_DS_HI 2
++#define PAD20_DS_SZ 1
++#define PAD20_IE_MSK 0x00000008
++#define PAD20_IE_I_MSK 0xfffffff7
++#define PAD20_IE_SFT 3
++#define PAD20_IE_HI 3
++#define PAD20_IE_SZ 1
++#define PAD20_SEL_I_MSK 0x000000f0
++#define PAD20_SEL_I_I_MSK 0xffffff0f
++#define PAD20_SEL_I_SFT 4
++#define PAD20_SEL_I_HI 7
++#define PAD20_SEL_I_SZ 4
++#define PAD20_OD_MSK 0x00000100
++#define PAD20_OD_I_MSK 0xfffffeff
++#define PAD20_OD_SFT 8
++#define PAD20_OD_HI 8
++#define PAD20_OD_SZ 1
++#define PAD20_SEL_O_MSK 0x00003000
++#define PAD20_SEL_O_I_MSK 0xffffcfff
++#define PAD20_SEL_O_SFT 12
++#define PAD20_SEL_O_HI 13
++#define PAD20_SEL_O_SZ 2
++#define STRAP0_MSK 0x08000000
++#define STRAP0_I_MSK 0xf7ffffff
++#define STRAP0_SFT 27
++#define STRAP0_HI 27
++#define STRAP0_SZ 1
++#define GPIO_TEST_1_ID_MSK 0x10000000
++#define GPIO_TEST_1_ID_I_MSK 0xefffffff
++#define GPIO_TEST_1_ID_SFT 28
++#define GPIO_TEST_1_ID_HI 28
++#define GPIO_TEST_1_ID_SZ 1
++#define PAD21_OE_MSK 0x00000001
++#define PAD21_OE_I_MSK 0xfffffffe
++#define PAD21_OE_SFT 0
++#define PAD21_OE_HI 0
++#define PAD21_OE_SZ 1
++#define PAD21_PE_MSK 0x00000002
++#define PAD21_PE_I_MSK 0xfffffffd
++#define PAD21_PE_SFT 1
++#define PAD21_PE_HI 1
++#define PAD21_PE_SZ 1
++#define PAD21_DS_MSK 0x00000004
++#define PAD21_DS_I_MSK 0xfffffffb
++#define PAD21_DS_SFT 2
++#define PAD21_DS_HI 2
++#define PAD21_DS_SZ 1
++#define PAD21_IE_MSK 0x00000008
++#define PAD21_IE_I_MSK 0xfffffff7
++#define PAD21_IE_SFT 3
++#define PAD21_IE_HI 3
++#define PAD21_IE_SZ 1
++#define PAD21_SEL_I_MSK 0x00000070
++#define PAD21_SEL_I_I_MSK 0xffffff8f
++#define PAD21_SEL_I_SFT 4
++#define PAD21_SEL_I_HI 6
++#define PAD21_SEL_I_SZ 3
++#define PAD21_OD_MSK 0x00000100
++#define PAD21_OD_I_MSK 0xfffffeff
++#define PAD21_OD_SFT 8
++#define PAD21_OD_HI 8
++#define PAD21_OD_SZ 1
++#define PAD21_SEL_O_MSK 0x00003000
++#define PAD21_SEL_O_I_MSK 0xffffcfff
++#define PAD21_SEL_O_SFT 12
++#define PAD21_SEL_O_HI 13
++#define PAD21_SEL_O_SZ 2
++#define STRAP3_MSK 0x08000000
++#define STRAP3_I_MSK 0xf7ffffff
++#define STRAP3_SFT 27
++#define STRAP3_HI 27
++#define STRAP3_SZ 1
++#define GPIO_TEST_2_ID_MSK 0x10000000
++#define GPIO_TEST_2_ID_I_MSK 0xefffffff
++#define GPIO_TEST_2_ID_SFT 28
++#define GPIO_TEST_2_ID_HI 28
++#define GPIO_TEST_2_ID_SZ 1
++#define PAD22_OE_MSK 0x00000001
++#define PAD22_OE_I_MSK 0xfffffffe
++#define PAD22_OE_SFT 0
++#define PAD22_OE_HI 0
++#define PAD22_OE_SZ 1
++#define PAD22_PE_MSK 0x00000002
++#define PAD22_PE_I_MSK 0xfffffffd
++#define PAD22_PE_SFT 1
++#define PAD22_PE_HI 1
++#define PAD22_PE_SZ 1
++#define PAD22_DS_MSK 0x00000004
++#define PAD22_DS_I_MSK 0xfffffffb
++#define PAD22_DS_SFT 2
++#define PAD22_DS_HI 2
++#define PAD22_DS_SZ 1
++#define PAD22_IE_MSK 0x00000008
++#define PAD22_IE_I_MSK 0xfffffff7
++#define PAD22_IE_SFT 3
++#define PAD22_IE_HI 3
++#define PAD22_IE_SZ 1
++#define PAD22_SEL_I_MSK 0x00000070
++#define PAD22_SEL_I_I_MSK 0xffffff8f
++#define PAD22_SEL_I_SFT 4
++#define PAD22_SEL_I_HI 6
++#define PAD22_SEL_I_SZ 3
++#define PAD22_OD_MSK 0x00000100
++#define PAD22_OD_I_MSK 0xfffffeff
++#define PAD22_OD_SFT 8
++#define PAD22_OD_HI 8
++#define PAD22_OD_SZ 1
++#define PAD22_SEL_O_MSK 0x00007000
++#define PAD22_SEL_O_I_MSK 0xffff8fff
++#define PAD22_SEL_O_SFT 12
++#define PAD22_SEL_O_HI 14
++#define PAD22_SEL_O_SZ 3
++#define PAD22_SEL_OE_MSK 0x00100000
++#define PAD22_SEL_OE_I_MSK 0xffefffff
++#define PAD22_SEL_OE_SFT 20
++#define PAD22_SEL_OE_HI 20
++#define PAD22_SEL_OE_SZ 1
++#define GPIO_TEST_3_ID_MSK 0x10000000
++#define GPIO_TEST_3_ID_I_MSK 0xefffffff
++#define GPIO_TEST_3_ID_SFT 28
++#define GPIO_TEST_3_ID_HI 28
++#define GPIO_TEST_3_ID_SZ 1
++#define PAD24_OE_MSK 0x00000001
++#define PAD24_OE_I_MSK 0xfffffffe
++#define PAD24_OE_SFT 0
++#define PAD24_OE_HI 0
++#define PAD24_OE_SZ 1
++#define PAD24_PE_MSK 0x00000002
++#define PAD24_PE_I_MSK 0xfffffffd
++#define PAD24_PE_SFT 1
++#define PAD24_PE_HI 1
++#define PAD24_PE_SZ 1
++#define PAD24_DS_MSK 0x00000004
++#define PAD24_DS_I_MSK 0xfffffffb
++#define PAD24_DS_SFT 2
++#define PAD24_DS_HI 2
++#define PAD24_DS_SZ 1
++#define PAD24_IE_MSK 0x00000008
++#define PAD24_IE_I_MSK 0xfffffff7
++#define PAD24_IE_SFT 3
++#define PAD24_IE_HI 3
++#define PAD24_IE_SZ 1
++#define PAD24_SEL_I_MSK 0x00000030
++#define PAD24_SEL_I_I_MSK 0xffffffcf
++#define PAD24_SEL_I_SFT 4
++#define PAD24_SEL_I_HI 5
++#define PAD24_SEL_I_SZ 2
++#define PAD24_OD_MSK 0x00000100
++#define PAD24_OD_I_MSK 0xfffffeff
++#define PAD24_OD_SFT 8
++#define PAD24_OD_HI 8
++#define PAD24_OD_SZ 1
++#define PAD24_SEL_O_MSK 0x00007000
++#define PAD24_SEL_O_I_MSK 0xffff8fff
++#define PAD24_SEL_O_SFT 12
++#define PAD24_SEL_O_HI 14
++#define PAD24_SEL_O_SZ 3
++#define GPIO_TEST_4_ID_MSK 0x10000000
++#define GPIO_TEST_4_ID_I_MSK 0xefffffff
++#define GPIO_TEST_4_ID_SFT 28
++#define GPIO_TEST_4_ID_HI 28
++#define GPIO_TEST_4_ID_SZ 1
++#define PAD25_OE_MSK 0x00000001
++#define PAD25_OE_I_MSK 0xfffffffe
++#define PAD25_OE_SFT 0
++#define PAD25_OE_HI 0
++#define PAD25_OE_SZ 1
++#define PAD25_PE_MSK 0x00000002
++#define PAD25_PE_I_MSK 0xfffffffd
++#define PAD25_PE_SFT 1
++#define PAD25_PE_HI 1
++#define PAD25_PE_SZ 1
++#define PAD25_DS_MSK 0x00000004
++#define PAD25_DS_I_MSK 0xfffffffb
++#define PAD25_DS_SFT 2
++#define PAD25_DS_HI 2
++#define PAD25_DS_SZ 1
++#define PAD25_IE_MSK 0x00000008
++#define PAD25_IE_I_MSK 0xfffffff7
++#define PAD25_IE_SFT 3
++#define PAD25_IE_HI 3
++#define PAD25_IE_SZ 1
++#define PAD25_SEL_I_MSK 0x00000070
++#define PAD25_SEL_I_I_MSK 0xffffff8f
++#define PAD25_SEL_I_SFT 4
++#define PAD25_SEL_I_HI 6
++#define PAD25_SEL_I_SZ 3
++#define PAD25_OD_MSK 0x00000100
++#define PAD25_OD_I_MSK 0xfffffeff
++#define PAD25_OD_SFT 8
++#define PAD25_OD_HI 8
++#define PAD25_OD_SZ 1
++#define PAD25_SEL_O_MSK 0x00007000
++#define PAD25_SEL_O_I_MSK 0xffff8fff
++#define PAD25_SEL_O_SFT 12
++#define PAD25_SEL_O_HI 14
++#define PAD25_SEL_O_SZ 3
++#define PAD25_SEL_OE_MSK 0x00100000
++#define PAD25_SEL_OE_I_MSK 0xffefffff
++#define PAD25_SEL_OE_SFT 20
++#define PAD25_SEL_OE_HI 20
++#define PAD25_SEL_OE_SZ 1
++#define STRAP1_MSK 0x08000000
++#define STRAP1_I_MSK 0xf7ffffff
++#define STRAP1_SFT 27
++#define STRAP1_HI 27
++#define STRAP1_SZ 1
++#define GPIO_1_ID_MSK 0x10000000
++#define GPIO_1_ID_I_MSK 0xefffffff
++#define GPIO_1_ID_SFT 28
++#define GPIO_1_ID_HI 28
++#define GPIO_1_ID_SZ 1
++#define PAD27_OE_MSK 0x00000001
++#define PAD27_OE_I_MSK 0xfffffffe
++#define PAD27_OE_SFT 0
++#define PAD27_OE_HI 0
++#define PAD27_OE_SZ 1
++#define PAD27_PE_MSK 0x00000002
++#define PAD27_PE_I_MSK 0xfffffffd
++#define PAD27_PE_SFT 1
++#define PAD27_PE_HI 1
++#define PAD27_PE_SZ 1
++#define PAD27_DS_MSK 0x00000004
++#define PAD27_DS_I_MSK 0xfffffffb
++#define PAD27_DS_SFT 2
++#define PAD27_DS_HI 2
++#define PAD27_DS_SZ 1
++#define PAD27_IE_MSK 0x00000008
++#define PAD27_IE_I_MSK 0xfffffff7
++#define PAD27_IE_SFT 3
++#define PAD27_IE_HI 3
++#define PAD27_IE_SZ 1
++#define PAD27_SEL_I_MSK 0x00000070
++#define PAD27_SEL_I_I_MSK 0xffffff8f
++#define PAD27_SEL_I_SFT 4
++#define PAD27_SEL_I_HI 6
++#define PAD27_SEL_I_SZ 3
++#define PAD27_OD_MSK 0x00000100
++#define PAD27_OD_I_MSK 0xfffffeff
++#define PAD27_OD_SFT 8
++#define PAD27_OD_HI 8
++#define PAD27_OD_SZ 1
++#define PAD27_SEL_O_MSK 0x00007000
++#define PAD27_SEL_O_I_MSK 0xffff8fff
++#define PAD27_SEL_O_SFT 12
++#define PAD27_SEL_O_HI 14
++#define PAD27_SEL_O_SZ 3
++#define GPIO_2_ID_MSK 0x10000000
++#define GPIO_2_ID_I_MSK 0xefffffff
++#define GPIO_2_ID_SFT 28
++#define GPIO_2_ID_HI 28
++#define GPIO_2_ID_SZ 1
++#define PAD28_OE_MSK 0x00000001
++#define PAD28_OE_I_MSK 0xfffffffe
++#define PAD28_OE_SFT 0
++#define PAD28_OE_HI 0
++#define PAD28_OE_SZ 1
++#define PAD28_PE_MSK 0x00000002
++#define PAD28_PE_I_MSK 0xfffffffd
++#define PAD28_PE_SFT 1
++#define PAD28_PE_HI 1
++#define PAD28_PE_SZ 1
++#define PAD28_DS_MSK 0x00000004
++#define PAD28_DS_I_MSK 0xfffffffb
++#define PAD28_DS_SFT 2
++#define PAD28_DS_HI 2
++#define PAD28_DS_SZ 1
++#define PAD28_IE_MSK 0x00000008
++#define PAD28_IE_I_MSK 0xfffffff7
++#define PAD28_IE_SFT 3
++#define PAD28_IE_HI 3
++#define PAD28_IE_SZ 1
++#define PAD28_SEL_I_MSK 0x00000070
++#define PAD28_SEL_I_I_MSK 0xffffff8f
++#define PAD28_SEL_I_SFT 4
++#define PAD28_SEL_I_HI 6
++#define PAD28_SEL_I_SZ 3
++#define PAD28_OD_MSK 0x00000100
++#define PAD28_OD_I_MSK 0xfffffeff
++#define PAD28_OD_SFT 8
++#define PAD28_OD_HI 8
++#define PAD28_OD_SZ 1
++#define PAD28_SEL_O_MSK 0x0000f000
++#define PAD28_SEL_O_I_MSK 0xffff0fff
++#define PAD28_SEL_O_SFT 12
++#define PAD28_SEL_O_HI 15
++#define PAD28_SEL_O_SZ 4
++#define PAD28_SEL_OE_MSK 0x00100000
++#define PAD28_SEL_OE_I_MSK 0xffefffff
++#define PAD28_SEL_OE_SFT 20
++#define PAD28_SEL_OE_HI 20
++#define PAD28_SEL_OE_SZ 1
++#define GPIO_3_ID_MSK 0x10000000
++#define GPIO_3_ID_I_MSK 0xefffffff
++#define GPIO_3_ID_SFT 28
++#define GPIO_3_ID_HI 28
++#define GPIO_3_ID_SZ 1
++#define PAD29_OE_MSK 0x00000001
++#define PAD29_OE_I_MSK 0xfffffffe
++#define PAD29_OE_SFT 0
++#define PAD29_OE_HI 0
++#define PAD29_OE_SZ 1
++#define PAD29_PE_MSK 0x00000002
++#define PAD29_PE_I_MSK 0xfffffffd
++#define PAD29_PE_SFT 1
++#define PAD29_PE_HI 1
++#define PAD29_PE_SZ 1
++#define PAD29_DS_MSK 0x00000004
++#define PAD29_DS_I_MSK 0xfffffffb
++#define PAD29_DS_SFT 2
++#define PAD29_DS_HI 2
++#define PAD29_DS_SZ 1
++#define PAD29_IE_MSK 0x00000008
++#define PAD29_IE_I_MSK 0xfffffff7
++#define PAD29_IE_SFT 3
++#define PAD29_IE_HI 3
++#define PAD29_IE_SZ 1
++#define PAD29_SEL_I_MSK 0x00000070
++#define PAD29_SEL_I_I_MSK 0xffffff8f
++#define PAD29_SEL_I_SFT 4
++#define PAD29_SEL_I_HI 6
++#define PAD29_SEL_I_SZ 3
++#define PAD29_OD_MSK 0x00000100
++#define PAD29_OD_I_MSK 0xfffffeff
++#define PAD29_OD_SFT 8
++#define PAD29_OD_HI 8
++#define PAD29_OD_SZ 1
++#define PAD29_SEL_O_MSK 0x00007000
++#define PAD29_SEL_O_I_MSK 0xffff8fff
++#define PAD29_SEL_O_SFT 12
++#define PAD29_SEL_O_HI 14
++#define PAD29_SEL_O_SZ 3
++#define GPIO_TEST_5_ID_MSK 0x10000000
++#define GPIO_TEST_5_ID_I_MSK 0xefffffff
++#define GPIO_TEST_5_ID_SFT 28
++#define GPIO_TEST_5_ID_HI 28
++#define GPIO_TEST_5_ID_SZ 1
++#define PAD30_OE_MSK 0x00000001
++#define PAD30_OE_I_MSK 0xfffffffe
++#define PAD30_OE_SFT 0
++#define PAD30_OE_HI 0
++#define PAD30_OE_SZ 1
++#define PAD30_PE_MSK 0x00000002
++#define PAD30_PE_I_MSK 0xfffffffd
++#define PAD30_PE_SFT 1
++#define PAD30_PE_HI 1
++#define PAD30_PE_SZ 1
++#define PAD30_DS_MSK 0x00000004
++#define PAD30_DS_I_MSK 0xfffffffb
++#define PAD30_DS_SFT 2
++#define PAD30_DS_HI 2
++#define PAD30_DS_SZ 1
++#define PAD30_IE_MSK 0x00000008
++#define PAD30_IE_I_MSK 0xfffffff7
++#define PAD30_IE_SFT 3
++#define PAD30_IE_HI 3
++#define PAD30_IE_SZ 1
++#define PAD30_SEL_I_MSK 0x00000030
++#define PAD30_SEL_I_I_MSK 0xffffffcf
++#define PAD30_SEL_I_SFT 4
++#define PAD30_SEL_I_HI 5
++#define PAD30_SEL_I_SZ 2
++#define PAD30_OD_MSK 0x00000100
++#define PAD30_OD_I_MSK 0xfffffeff
++#define PAD30_OD_SFT 8
++#define PAD30_OD_HI 8
++#define PAD30_OD_SZ 1
++#define PAD30_SEL_O_MSK 0x00003000
++#define PAD30_SEL_O_I_MSK 0xffffcfff
++#define PAD30_SEL_O_SFT 12
++#define PAD30_SEL_O_HI 13
++#define PAD30_SEL_O_SZ 2
++#define TEST_6_ID_MSK 0x10000000
++#define TEST_6_ID_I_MSK 0xefffffff
++#define TEST_6_ID_SFT 28
++#define TEST_6_ID_HI 28
++#define TEST_6_ID_SZ 1
++#define PAD31_OE_MSK 0x00000001
++#define PAD31_OE_I_MSK 0xfffffffe
++#define PAD31_OE_SFT 0
++#define PAD31_OE_HI 0
++#define PAD31_OE_SZ 1
++#define PAD31_PE_MSK 0x00000002
++#define PAD31_PE_I_MSK 0xfffffffd
++#define PAD31_PE_SFT 1
++#define PAD31_PE_HI 1
++#define PAD31_PE_SZ 1
++#define PAD31_DS_MSK 0x00000004
++#define PAD31_DS_I_MSK 0xfffffffb
++#define PAD31_DS_SFT 2
++#define PAD31_DS_HI 2
++#define PAD31_DS_SZ 1
++#define PAD31_IE_MSK 0x00000008
++#define PAD31_IE_I_MSK 0xfffffff7
++#define PAD31_IE_SFT 3
++#define PAD31_IE_HI 3
++#define PAD31_IE_SZ 1
++#define PAD31_SEL_I_MSK 0x00000030
++#define PAD31_SEL_I_I_MSK 0xffffffcf
++#define PAD31_SEL_I_SFT 4
++#define PAD31_SEL_I_HI 5
++#define PAD31_SEL_I_SZ 2
++#define PAD31_OD_MSK 0x00000100
++#define PAD31_OD_I_MSK 0xfffffeff
++#define PAD31_OD_SFT 8
++#define PAD31_OD_HI 8
++#define PAD31_OD_SZ 1
++#define PAD31_SEL_O_MSK 0x00003000
++#define PAD31_SEL_O_I_MSK 0xffffcfff
++#define PAD31_SEL_O_SFT 12
++#define PAD31_SEL_O_HI 13
++#define PAD31_SEL_O_SZ 2
++#define TEST_7_ID_MSK 0x10000000
++#define TEST_7_ID_I_MSK 0xefffffff
++#define TEST_7_ID_SFT 28
++#define TEST_7_ID_HI 28
++#define TEST_7_ID_SZ 1
++#define PAD32_OE_MSK 0x00000001
++#define PAD32_OE_I_MSK 0xfffffffe
++#define PAD32_OE_SFT 0
++#define PAD32_OE_HI 0
++#define PAD32_OE_SZ 1
++#define PAD32_PE_MSK 0x00000002
++#define PAD32_PE_I_MSK 0xfffffffd
++#define PAD32_PE_SFT 1
++#define PAD32_PE_HI 1
++#define PAD32_PE_SZ 1
++#define PAD32_DS_MSK 0x00000004
++#define PAD32_DS_I_MSK 0xfffffffb
++#define PAD32_DS_SFT 2
++#define PAD32_DS_HI 2
++#define PAD32_DS_SZ 1
++#define PAD32_IE_MSK 0x00000008
++#define PAD32_IE_I_MSK 0xfffffff7
++#define PAD32_IE_SFT 3
++#define PAD32_IE_HI 3
++#define PAD32_IE_SZ 1
++#define PAD32_SEL_I_MSK 0x00000030
++#define PAD32_SEL_I_I_MSK 0xffffffcf
++#define PAD32_SEL_I_SFT 4
++#define PAD32_SEL_I_HI 5
++#define PAD32_SEL_I_SZ 2
++#define PAD32_OD_MSK 0x00000100
++#define PAD32_OD_I_MSK 0xfffffeff
++#define PAD32_OD_SFT 8
++#define PAD32_OD_HI 8
++#define PAD32_OD_SZ 1
++#define PAD32_SEL_O_MSK 0x00003000
++#define PAD32_SEL_O_I_MSK 0xffffcfff
++#define PAD32_SEL_O_SFT 12
++#define PAD32_SEL_O_HI 13
++#define PAD32_SEL_O_SZ 2
++#define TEST_8_ID_MSK 0x10000000
++#define TEST_8_ID_I_MSK 0xefffffff
++#define TEST_8_ID_SFT 28
++#define TEST_8_ID_HI 28
++#define TEST_8_ID_SZ 1
++#define PAD33_OE_MSK 0x00000001
++#define PAD33_OE_I_MSK 0xfffffffe
++#define PAD33_OE_SFT 0
++#define PAD33_OE_HI 0
++#define PAD33_OE_SZ 1
++#define PAD33_PE_MSK 0x00000002
++#define PAD33_PE_I_MSK 0xfffffffd
++#define PAD33_PE_SFT 1
++#define PAD33_PE_HI 1
++#define PAD33_PE_SZ 1
++#define PAD33_DS_MSK 0x00000004
++#define PAD33_DS_I_MSK 0xfffffffb
++#define PAD33_DS_SFT 2
++#define PAD33_DS_HI 2
++#define PAD33_DS_SZ 1
++#define PAD33_IE_MSK 0x00000008
++#define PAD33_IE_I_MSK 0xfffffff7
++#define PAD33_IE_SFT 3
++#define PAD33_IE_HI 3
++#define PAD33_IE_SZ 1
++#define PAD33_SEL_I_MSK 0x00000030
++#define PAD33_SEL_I_I_MSK 0xffffffcf
++#define PAD33_SEL_I_SFT 4
++#define PAD33_SEL_I_HI 5
++#define PAD33_SEL_I_SZ 2
++#define PAD33_OD_MSK 0x00000100
++#define PAD33_OD_I_MSK 0xfffffeff
++#define PAD33_OD_SFT 8
++#define PAD33_OD_HI 8
++#define PAD33_OD_SZ 1
++#define PAD33_SEL_O_MSK 0x00003000
++#define PAD33_SEL_O_I_MSK 0xffffcfff
++#define PAD33_SEL_O_SFT 12
++#define PAD33_SEL_O_HI 13
++#define PAD33_SEL_O_SZ 2
++#define TEST_9_ID_MSK 0x10000000
++#define TEST_9_ID_I_MSK 0xefffffff
++#define TEST_9_ID_SFT 28
++#define TEST_9_ID_HI 28
++#define TEST_9_ID_SZ 1
++#define PAD34_OE_MSK 0x00000001
++#define PAD34_OE_I_MSK 0xfffffffe
++#define PAD34_OE_SFT 0
++#define PAD34_OE_HI 0
++#define PAD34_OE_SZ 1
++#define PAD34_PE_MSK 0x00000002
++#define PAD34_PE_I_MSK 0xfffffffd
++#define PAD34_PE_SFT 1
++#define PAD34_PE_HI 1
++#define PAD34_PE_SZ 1
++#define PAD34_DS_MSK 0x00000004
++#define PAD34_DS_I_MSK 0xfffffffb
++#define PAD34_DS_SFT 2
++#define PAD34_DS_HI 2
++#define PAD34_DS_SZ 1
++#define PAD34_IE_MSK 0x00000008
++#define PAD34_IE_I_MSK 0xfffffff7
++#define PAD34_IE_SFT 3
++#define PAD34_IE_HI 3
++#define PAD34_IE_SZ 1
++#define PAD34_SEL_I_MSK 0x00000030
++#define PAD34_SEL_I_I_MSK 0xffffffcf
++#define PAD34_SEL_I_SFT 4
++#define PAD34_SEL_I_HI 5
++#define PAD34_SEL_I_SZ 2
++#define PAD34_OD_MSK 0x00000100
++#define PAD34_OD_I_MSK 0xfffffeff
++#define PAD34_OD_SFT 8
++#define PAD34_OD_HI 8
++#define PAD34_OD_SZ 1
++#define PAD34_SEL_O_MSK 0x00003000
++#define PAD34_SEL_O_I_MSK 0xffffcfff
++#define PAD34_SEL_O_SFT 12
++#define PAD34_SEL_O_HI 13
++#define PAD34_SEL_O_SZ 2
++#define TEST_10_ID_MSK 0x10000000
++#define TEST_10_ID_I_MSK 0xefffffff
++#define TEST_10_ID_SFT 28
++#define TEST_10_ID_HI 28
++#define TEST_10_ID_SZ 1
++#define PAD42_OE_MSK 0x00000001
++#define PAD42_OE_I_MSK 0xfffffffe
++#define PAD42_OE_SFT 0
++#define PAD42_OE_HI 0
++#define PAD42_OE_SZ 1
++#define PAD42_PE_MSK 0x00000002
++#define PAD42_PE_I_MSK 0xfffffffd
++#define PAD42_PE_SFT 1
++#define PAD42_PE_HI 1
++#define PAD42_PE_SZ 1
++#define PAD42_DS_MSK 0x00000004
++#define PAD42_DS_I_MSK 0xfffffffb
++#define PAD42_DS_SFT 2
++#define PAD42_DS_HI 2
++#define PAD42_DS_SZ 1
++#define PAD42_IE_MSK 0x00000008
++#define PAD42_IE_I_MSK 0xfffffff7
++#define PAD42_IE_SFT 3
++#define PAD42_IE_HI 3
++#define PAD42_IE_SZ 1
++#define PAD42_SEL_I_MSK 0x00000030
++#define PAD42_SEL_I_I_MSK 0xffffffcf
++#define PAD42_SEL_I_SFT 4
++#define PAD42_SEL_I_HI 5
++#define PAD42_SEL_I_SZ 2
++#define PAD42_OD_MSK 0x00000100
++#define PAD42_OD_I_MSK 0xfffffeff
++#define PAD42_OD_SFT 8
++#define PAD42_OD_HI 8
++#define PAD42_OD_SZ 1
++#define PAD42_SEL_O_MSK 0x00001000
++#define PAD42_SEL_O_I_MSK 0xffffefff
++#define PAD42_SEL_O_SFT 12
++#define PAD42_SEL_O_HI 12
++#define PAD42_SEL_O_SZ 1
++#define TEST_11_ID_MSK 0x10000000
++#define TEST_11_ID_I_MSK 0xefffffff
++#define TEST_11_ID_SFT 28
++#define TEST_11_ID_HI 28
++#define TEST_11_ID_SZ 1
++#define PAD43_OE_MSK 0x00000001
++#define PAD43_OE_I_MSK 0xfffffffe
++#define PAD43_OE_SFT 0
++#define PAD43_OE_HI 0
++#define PAD43_OE_SZ 1
++#define PAD43_PE_MSK 0x00000002
++#define PAD43_PE_I_MSK 0xfffffffd
++#define PAD43_PE_SFT 1
++#define PAD43_PE_HI 1
++#define PAD43_PE_SZ 1
++#define PAD43_DS_MSK 0x00000004
++#define PAD43_DS_I_MSK 0xfffffffb
++#define PAD43_DS_SFT 2
++#define PAD43_DS_HI 2
++#define PAD43_DS_SZ 1
++#define PAD43_IE_MSK 0x00000008
++#define PAD43_IE_I_MSK 0xfffffff7
++#define PAD43_IE_SFT 3
++#define PAD43_IE_HI 3
++#define PAD43_IE_SZ 1
++#define PAD43_SEL_I_MSK 0x00000030
++#define PAD43_SEL_I_I_MSK 0xffffffcf
++#define PAD43_SEL_I_SFT 4
++#define PAD43_SEL_I_HI 5
++#define PAD43_SEL_I_SZ 2
++#define PAD43_OD_MSK 0x00000100
++#define PAD43_OD_I_MSK 0xfffffeff
++#define PAD43_OD_SFT 8
++#define PAD43_OD_HI 8
++#define PAD43_OD_SZ 1
++#define PAD43_SEL_O_MSK 0x00001000
++#define PAD43_SEL_O_I_MSK 0xffffefff
++#define PAD43_SEL_O_SFT 12
++#define PAD43_SEL_O_HI 12
++#define PAD43_SEL_O_SZ 1
++#define TEST_12_ID_MSK 0x10000000
++#define TEST_12_ID_I_MSK 0xefffffff
++#define TEST_12_ID_SFT 28
++#define TEST_12_ID_HI 28
++#define TEST_12_ID_SZ 1
++#define PAD44_OE_MSK 0x00000001
++#define PAD44_OE_I_MSK 0xfffffffe
++#define PAD44_OE_SFT 0
++#define PAD44_OE_HI 0
++#define PAD44_OE_SZ 1
++#define PAD44_PE_MSK 0x00000002
++#define PAD44_PE_I_MSK 0xfffffffd
++#define PAD44_PE_SFT 1
++#define PAD44_PE_HI 1
++#define PAD44_PE_SZ 1
++#define PAD44_DS_MSK 0x00000004
++#define PAD44_DS_I_MSK 0xfffffffb
++#define PAD44_DS_SFT 2
++#define PAD44_DS_HI 2
++#define PAD44_DS_SZ 1
++#define PAD44_IE_MSK 0x00000008
++#define PAD44_IE_I_MSK 0xfffffff7
++#define PAD44_IE_SFT 3
++#define PAD44_IE_HI 3
++#define PAD44_IE_SZ 1
++#define PAD44_SEL_I_MSK 0x00000030
++#define PAD44_SEL_I_I_MSK 0xffffffcf
++#define PAD44_SEL_I_SFT 4
++#define PAD44_SEL_I_HI 5
++#define PAD44_SEL_I_SZ 2
++#define PAD44_OD_MSK 0x00000100
++#define PAD44_OD_I_MSK 0xfffffeff
++#define PAD44_OD_SFT 8
++#define PAD44_OD_HI 8
++#define PAD44_OD_SZ 1
++#define PAD44_SEL_O_MSK 0x00003000
++#define PAD44_SEL_O_I_MSK 0xffffcfff
++#define PAD44_SEL_O_SFT 12
++#define PAD44_SEL_O_HI 13
++#define PAD44_SEL_O_SZ 2
++#define TEST_13_ID_MSK 0x10000000
++#define TEST_13_ID_I_MSK 0xefffffff
++#define TEST_13_ID_SFT 28
++#define TEST_13_ID_HI 28
++#define TEST_13_ID_SZ 1
++#define PAD45_OE_MSK 0x00000001
++#define PAD45_OE_I_MSK 0xfffffffe
++#define PAD45_OE_SFT 0
++#define PAD45_OE_HI 0
++#define PAD45_OE_SZ 1
++#define PAD45_PE_MSK 0x00000002
++#define PAD45_PE_I_MSK 0xfffffffd
++#define PAD45_PE_SFT 1
++#define PAD45_PE_HI 1
++#define PAD45_PE_SZ 1
++#define PAD45_DS_MSK 0x00000004
++#define PAD45_DS_I_MSK 0xfffffffb
++#define PAD45_DS_SFT 2
++#define PAD45_DS_HI 2
++#define PAD45_DS_SZ 1
++#define PAD45_IE_MSK 0x00000008
++#define PAD45_IE_I_MSK 0xfffffff7
++#define PAD45_IE_SFT 3
++#define PAD45_IE_HI 3
++#define PAD45_IE_SZ 1
++#define PAD45_SEL_I_MSK 0x00000030
++#define PAD45_SEL_I_I_MSK 0xffffffcf
++#define PAD45_SEL_I_SFT 4
++#define PAD45_SEL_I_HI 5
++#define PAD45_SEL_I_SZ 2
++#define PAD45_OD_MSK 0x00000100
++#define PAD45_OD_I_MSK 0xfffffeff
++#define PAD45_OD_SFT 8
++#define PAD45_OD_HI 8
++#define PAD45_OD_SZ 1
++#define PAD45_SEL_O_MSK 0x00003000
++#define PAD45_SEL_O_I_MSK 0xffffcfff
++#define PAD45_SEL_O_SFT 12
++#define PAD45_SEL_O_HI 13
++#define PAD45_SEL_O_SZ 2
++#define TEST_14_ID_MSK 0x10000000
++#define TEST_14_ID_I_MSK 0xefffffff
++#define TEST_14_ID_SFT 28
++#define TEST_14_ID_HI 28
++#define TEST_14_ID_SZ 1
++#define PAD46_OE_MSK 0x00000001
++#define PAD46_OE_I_MSK 0xfffffffe
++#define PAD46_OE_SFT 0
++#define PAD46_OE_HI 0
++#define PAD46_OE_SZ 1
++#define PAD46_PE_MSK 0x00000002
++#define PAD46_PE_I_MSK 0xfffffffd
++#define PAD46_PE_SFT 1
++#define PAD46_PE_HI 1
++#define PAD46_PE_SZ 1
++#define PAD46_DS_MSK 0x00000004
++#define PAD46_DS_I_MSK 0xfffffffb
++#define PAD46_DS_SFT 2
++#define PAD46_DS_HI 2
++#define PAD46_DS_SZ 1
++#define PAD46_IE_MSK 0x00000008
++#define PAD46_IE_I_MSK 0xfffffff7
++#define PAD46_IE_SFT 3
++#define PAD46_IE_HI 3
++#define PAD46_IE_SZ 1
++#define PAD46_SEL_I_MSK 0x00000030
++#define PAD46_SEL_I_I_MSK 0xffffffcf
++#define PAD46_SEL_I_SFT 4
++#define PAD46_SEL_I_HI 5
++#define PAD46_SEL_I_SZ 2
++#define PAD46_OD_MSK 0x00000100
++#define PAD46_OD_I_MSK 0xfffffeff
++#define PAD46_OD_SFT 8
++#define PAD46_OD_HI 8
++#define PAD46_OD_SZ 1
++#define PAD46_SEL_O_MSK 0x00003000
++#define PAD46_SEL_O_I_MSK 0xffffcfff
++#define PAD46_SEL_O_SFT 12
++#define PAD46_SEL_O_HI 13
++#define PAD46_SEL_O_SZ 2
++#define TEST_15_ID_MSK 0x10000000
++#define TEST_15_ID_I_MSK 0xefffffff
++#define TEST_15_ID_SFT 28
++#define TEST_15_ID_HI 28
++#define TEST_15_ID_SZ 1
++#define PAD47_OE_MSK 0x00000001
++#define PAD47_OE_I_MSK 0xfffffffe
++#define PAD47_OE_SFT 0
++#define PAD47_OE_HI 0
++#define PAD47_OE_SZ 1
++#define PAD47_PE_MSK 0x00000002
++#define PAD47_PE_I_MSK 0xfffffffd
++#define PAD47_PE_SFT 1
++#define PAD47_PE_HI 1
++#define PAD47_PE_SZ 1
++#define PAD47_DS_MSK 0x00000004
++#define PAD47_DS_I_MSK 0xfffffffb
++#define PAD47_DS_SFT 2
++#define PAD47_DS_HI 2
++#define PAD47_DS_SZ 1
++#define PAD47_SEL_I_MSK 0x00000030
++#define PAD47_SEL_I_I_MSK 0xffffffcf
++#define PAD47_SEL_I_SFT 4
++#define PAD47_SEL_I_HI 5
++#define PAD47_SEL_I_SZ 2
++#define PAD47_OD_MSK 0x00000100
++#define PAD47_OD_I_MSK 0xfffffeff
++#define PAD47_OD_SFT 8
++#define PAD47_OD_HI 8
++#define PAD47_OD_SZ 1
++#define PAD47_SEL_O_MSK 0x00003000
++#define PAD47_SEL_O_I_MSK 0xffffcfff
++#define PAD47_SEL_O_SFT 12
++#define PAD47_SEL_O_HI 13
++#define PAD47_SEL_O_SZ 2
++#define PAD47_SEL_OE_MSK 0x00100000
++#define PAD47_SEL_OE_I_MSK 0xffefffff
++#define PAD47_SEL_OE_SFT 20
++#define PAD47_SEL_OE_HI 20
++#define PAD47_SEL_OE_SZ 1
++#define GPIO_9_ID_MSK 0x10000000
++#define GPIO_9_ID_I_MSK 0xefffffff
++#define GPIO_9_ID_SFT 28
++#define GPIO_9_ID_HI 28
++#define GPIO_9_ID_SZ 1
++#define PAD48_OE_MSK 0x00000001
++#define PAD48_OE_I_MSK 0xfffffffe
++#define PAD48_OE_SFT 0
++#define PAD48_OE_HI 0
++#define PAD48_OE_SZ 1
++#define PAD48_PE_MSK 0x00000002
++#define PAD48_PE_I_MSK 0xfffffffd
++#define PAD48_PE_SFT 1
++#define PAD48_PE_HI 1
++#define PAD48_PE_SZ 1
++#define PAD48_DS_MSK 0x00000004
++#define PAD48_DS_I_MSK 0xfffffffb
++#define PAD48_DS_SFT 2
++#define PAD48_DS_HI 2
++#define PAD48_DS_SZ 1
++#define PAD48_IE_MSK 0x00000008
++#define PAD48_IE_I_MSK 0xfffffff7
++#define PAD48_IE_SFT 3
++#define PAD48_IE_HI 3
++#define PAD48_IE_SZ 1
++#define PAD48_SEL_I_MSK 0x00000070
++#define PAD48_SEL_I_I_MSK 0xffffff8f
++#define PAD48_SEL_I_SFT 4
++#define PAD48_SEL_I_HI 6
++#define PAD48_SEL_I_SZ 3
++#define PAD48_OD_MSK 0x00000100
++#define PAD48_OD_I_MSK 0xfffffeff
++#define PAD48_OD_SFT 8
++#define PAD48_OD_HI 8
++#define PAD48_OD_SZ 1
++#define PAD48_PE_SEL_MSK 0x00000800
++#define PAD48_PE_SEL_I_MSK 0xfffff7ff
++#define PAD48_PE_SEL_SFT 11
++#define PAD48_PE_SEL_HI 11
++#define PAD48_PE_SEL_SZ 1
++#define PAD48_SEL_O_MSK 0x00003000
++#define PAD48_SEL_O_I_MSK 0xffffcfff
++#define PAD48_SEL_O_SFT 12
++#define PAD48_SEL_O_HI 13
++#define PAD48_SEL_O_SZ 2
++#define PAD48_SEL_OE_MSK 0x00100000
++#define PAD48_SEL_OE_I_MSK 0xffefffff
++#define PAD48_SEL_OE_SFT 20
++#define PAD48_SEL_OE_HI 20
++#define PAD48_SEL_OE_SZ 1
++#define GPIO_10_ID_MSK 0x10000000
++#define GPIO_10_ID_I_MSK 0xefffffff
++#define GPIO_10_ID_SFT 28
++#define GPIO_10_ID_HI 28
++#define GPIO_10_ID_SZ 1
++#define PAD49_OE_MSK 0x00000001
++#define PAD49_OE_I_MSK 0xfffffffe
++#define PAD49_OE_SFT 0
++#define PAD49_OE_HI 0
++#define PAD49_OE_SZ 1
++#define PAD49_PE_MSK 0x00000002
++#define PAD49_PE_I_MSK 0xfffffffd
++#define PAD49_PE_SFT 1
++#define PAD49_PE_HI 1
++#define PAD49_PE_SZ 1
++#define PAD49_DS_MSK 0x00000004
++#define PAD49_DS_I_MSK 0xfffffffb
++#define PAD49_DS_SFT 2
++#define PAD49_DS_HI 2
++#define PAD49_DS_SZ 1
++#define PAD49_IE_MSK 0x00000008
++#define PAD49_IE_I_MSK 0xfffffff7
++#define PAD49_IE_SFT 3
++#define PAD49_IE_HI 3
++#define PAD49_IE_SZ 1
++#define PAD49_SEL_I_MSK 0x00000070
++#define PAD49_SEL_I_I_MSK 0xffffff8f
++#define PAD49_SEL_I_SFT 4
++#define PAD49_SEL_I_HI 6
++#define PAD49_SEL_I_SZ 3
++#define PAD49_OD_MSK 0x00000100
++#define PAD49_OD_I_MSK 0xfffffeff
++#define PAD49_OD_SFT 8
++#define PAD49_OD_HI 8
++#define PAD49_OD_SZ 1
++#define PAD49_SEL_O_MSK 0x00003000
++#define PAD49_SEL_O_I_MSK 0xffffcfff
++#define PAD49_SEL_O_SFT 12
++#define PAD49_SEL_O_HI 13
++#define PAD49_SEL_O_SZ 2
++#define PAD49_SEL_OE_MSK 0x00100000
++#define PAD49_SEL_OE_I_MSK 0xffefffff
++#define PAD49_SEL_OE_SFT 20
++#define PAD49_SEL_OE_HI 20
++#define PAD49_SEL_OE_SZ 1
++#define GPIO_11_ID_MSK 0x10000000
++#define GPIO_11_ID_I_MSK 0xefffffff
++#define GPIO_11_ID_SFT 28
++#define GPIO_11_ID_HI 28
++#define GPIO_11_ID_SZ 1
++#define PAD50_OE_MSK 0x00000001
++#define PAD50_OE_I_MSK 0xfffffffe
++#define PAD50_OE_SFT 0
++#define PAD50_OE_HI 0
++#define PAD50_OE_SZ 1
++#define PAD50_PE_MSK 0x00000002
++#define PAD50_PE_I_MSK 0xfffffffd
++#define PAD50_PE_SFT 1
++#define PAD50_PE_HI 1
++#define PAD50_PE_SZ 1
++#define PAD50_DS_MSK 0x00000004
++#define PAD50_DS_I_MSK 0xfffffffb
++#define PAD50_DS_SFT 2
++#define PAD50_DS_HI 2
++#define PAD50_DS_SZ 1
++#define PAD50_IE_MSK 0x00000008
++#define PAD50_IE_I_MSK 0xfffffff7
++#define PAD50_IE_SFT 3
++#define PAD50_IE_HI 3
++#define PAD50_IE_SZ 1
++#define PAD50_SEL_I_MSK 0x00000070
++#define PAD50_SEL_I_I_MSK 0xffffff8f
++#define PAD50_SEL_I_SFT 4
++#define PAD50_SEL_I_HI 6
++#define PAD50_SEL_I_SZ 3
++#define PAD50_OD_MSK 0x00000100
++#define PAD50_OD_I_MSK 0xfffffeff
++#define PAD50_OD_SFT 8
++#define PAD50_OD_HI 8
++#define PAD50_OD_SZ 1
++#define PAD50_SEL_O_MSK 0x00003000
++#define PAD50_SEL_O_I_MSK 0xffffcfff
++#define PAD50_SEL_O_SFT 12
++#define PAD50_SEL_O_HI 13
++#define PAD50_SEL_O_SZ 2
++#define PAD50_SEL_OE_MSK 0x00100000
++#define PAD50_SEL_OE_I_MSK 0xffefffff
++#define PAD50_SEL_OE_SFT 20
++#define PAD50_SEL_OE_HI 20
++#define PAD50_SEL_OE_SZ 1
++#define GPIO_12_ID_MSK 0x10000000
++#define GPIO_12_ID_I_MSK 0xefffffff
++#define GPIO_12_ID_SFT 28
++#define GPIO_12_ID_HI 28
++#define GPIO_12_ID_SZ 1
++#define PAD51_OE_MSK 0x00000001
++#define PAD51_OE_I_MSK 0xfffffffe
++#define PAD51_OE_SFT 0
++#define PAD51_OE_HI 0
++#define PAD51_OE_SZ 1
++#define PAD51_PE_MSK 0x00000002
++#define PAD51_PE_I_MSK 0xfffffffd
++#define PAD51_PE_SFT 1
++#define PAD51_PE_HI 1
++#define PAD51_PE_SZ 1
++#define PAD51_DS_MSK 0x00000004
++#define PAD51_DS_I_MSK 0xfffffffb
++#define PAD51_DS_SFT 2
++#define PAD51_DS_HI 2
++#define PAD51_DS_SZ 1
++#define PAD51_IE_MSK 0x00000008
++#define PAD51_IE_I_MSK 0xfffffff7
++#define PAD51_IE_SFT 3
++#define PAD51_IE_HI 3
++#define PAD51_IE_SZ 1
++#define PAD51_SEL_I_MSK 0x00000030
++#define PAD51_SEL_I_I_MSK 0xffffffcf
++#define PAD51_SEL_I_SFT 4
++#define PAD51_SEL_I_HI 5
++#define PAD51_SEL_I_SZ 2
++#define PAD51_OD_MSK 0x00000100
++#define PAD51_OD_I_MSK 0xfffffeff
++#define PAD51_OD_SFT 8
++#define PAD51_OD_HI 8
++#define PAD51_OD_SZ 1
++#define PAD51_SEL_O_MSK 0x00001000
++#define PAD51_SEL_O_I_MSK 0xffffefff
++#define PAD51_SEL_O_SFT 12
++#define PAD51_SEL_O_HI 12
++#define PAD51_SEL_O_SZ 1
++#define PAD51_SEL_OE_MSK 0x00100000
++#define PAD51_SEL_OE_I_MSK 0xffefffff
++#define PAD51_SEL_OE_SFT 20
++#define PAD51_SEL_OE_HI 20
++#define PAD51_SEL_OE_SZ 1
++#define GPIO_13_ID_MSK 0x10000000
++#define GPIO_13_ID_I_MSK 0xefffffff
++#define GPIO_13_ID_SFT 28
++#define GPIO_13_ID_HI 28
++#define GPIO_13_ID_SZ 1
++#define PAD52_OE_MSK 0x00000001
++#define PAD52_OE_I_MSK 0xfffffffe
++#define PAD52_OE_SFT 0
++#define PAD52_OE_HI 0
++#define PAD52_OE_SZ 1
++#define PAD52_PE_MSK 0x00000002
++#define PAD52_PE_I_MSK 0xfffffffd
++#define PAD52_PE_SFT 1
++#define PAD52_PE_HI 1
++#define PAD52_PE_SZ 1
++#define PAD52_DS_MSK 0x00000004
++#define PAD52_DS_I_MSK 0xfffffffb
++#define PAD52_DS_SFT 2
++#define PAD52_DS_HI 2
++#define PAD52_DS_SZ 1
++#define PAD52_SEL_I_MSK 0x00000030
++#define PAD52_SEL_I_I_MSK 0xffffffcf
++#define PAD52_SEL_I_SFT 4
++#define PAD52_SEL_I_HI 5
++#define PAD52_SEL_I_SZ 2
++#define PAD52_OD_MSK 0x00000100
++#define PAD52_OD_I_MSK 0xfffffeff
++#define PAD52_OD_SFT 8
++#define PAD52_OD_HI 8
++#define PAD52_OD_SZ 1
++#define PAD52_SEL_O_MSK 0x00001000
++#define PAD52_SEL_O_I_MSK 0xffffefff
++#define PAD52_SEL_O_SFT 12
++#define PAD52_SEL_O_HI 12
++#define PAD52_SEL_O_SZ 1
++#define PAD52_SEL_OE_MSK 0x00100000
++#define PAD52_SEL_OE_I_MSK 0xffefffff
++#define PAD52_SEL_OE_SFT 20
++#define PAD52_SEL_OE_HI 20
++#define PAD52_SEL_OE_SZ 1
++#define GPIO_14_ID_MSK 0x10000000
++#define GPIO_14_ID_I_MSK 0xefffffff
++#define GPIO_14_ID_SFT 28
++#define GPIO_14_ID_HI 28
++#define GPIO_14_ID_SZ 1
++#define PAD53_OE_MSK 0x00000001
++#define PAD53_OE_I_MSK 0xfffffffe
++#define PAD53_OE_SFT 0
++#define PAD53_OE_HI 0
++#define PAD53_OE_SZ 1
++#define PAD53_PE_MSK 0x00000002
++#define PAD53_PE_I_MSK 0xfffffffd
++#define PAD53_PE_SFT 1
++#define PAD53_PE_HI 1
++#define PAD53_PE_SZ 1
++#define PAD53_DS_MSK 0x00000004
++#define PAD53_DS_I_MSK 0xfffffffb
++#define PAD53_DS_SFT 2
++#define PAD53_DS_HI 2
++#define PAD53_DS_SZ 1
++#define PAD53_IE_MSK 0x00000008
++#define PAD53_IE_I_MSK 0xfffffff7
++#define PAD53_IE_SFT 3
++#define PAD53_IE_HI 3
++#define PAD53_IE_SZ 1
++#define PAD53_SEL_I_MSK 0x00000030
++#define PAD53_SEL_I_I_MSK 0xffffffcf
++#define PAD53_SEL_I_SFT 4
++#define PAD53_SEL_I_HI 5
++#define PAD53_SEL_I_SZ 2
++#define PAD53_OD_MSK 0x00000100
++#define PAD53_OD_I_MSK 0xfffffeff
++#define PAD53_OD_SFT 8
++#define PAD53_OD_HI 8
++#define PAD53_OD_SZ 1
++#define PAD53_SEL_O_MSK 0x00001000
++#define PAD53_SEL_O_I_MSK 0xffffefff
++#define PAD53_SEL_O_SFT 12
++#define PAD53_SEL_O_HI 12
++#define PAD53_SEL_O_SZ 1
++#define JTAG_TMS_ID_MSK 0x10000000
++#define JTAG_TMS_ID_I_MSK 0xefffffff
++#define JTAG_TMS_ID_SFT 28
++#define JTAG_TMS_ID_HI 28
++#define JTAG_TMS_ID_SZ 1
++#define PAD54_OE_MSK 0x00000001
++#define PAD54_OE_I_MSK 0xfffffffe
++#define PAD54_OE_SFT 0
++#define PAD54_OE_HI 0
++#define PAD54_OE_SZ 1
++#define PAD54_PE_MSK 0x00000002
++#define PAD54_PE_I_MSK 0xfffffffd
++#define PAD54_PE_SFT 1
++#define PAD54_PE_HI 1
++#define PAD54_PE_SZ 1
++#define PAD54_DS_MSK 0x00000004
++#define PAD54_DS_I_MSK 0xfffffffb
++#define PAD54_DS_SFT 2
++#define PAD54_DS_HI 2
++#define PAD54_DS_SZ 1
++#define PAD54_OD_MSK 0x00000100
++#define PAD54_OD_I_MSK 0xfffffeff
++#define PAD54_OD_SFT 8
++#define PAD54_OD_HI 8
++#define PAD54_OD_SZ 1
++#define PAD54_SEL_O_MSK 0x00003000
++#define PAD54_SEL_O_I_MSK 0xffffcfff
++#define PAD54_SEL_O_SFT 12
++#define PAD54_SEL_O_HI 13
++#define PAD54_SEL_O_SZ 2
++#define JTAG_TCK_ID_MSK 0x10000000
++#define JTAG_TCK_ID_I_MSK 0xefffffff
++#define JTAG_TCK_ID_SFT 28
++#define JTAG_TCK_ID_HI 28
++#define JTAG_TCK_ID_SZ 1
++#define PAD56_PE_MSK 0x00000002
++#define PAD56_PE_I_MSK 0xfffffffd
++#define PAD56_PE_SFT 1
++#define PAD56_PE_HI 1
++#define PAD56_PE_SZ 1
++#define PAD56_DS_MSK 0x00000004
++#define PAD56_DS_I_MSK 0xfffffffb
++#define PAD56_DS_SFT 2
++#define PAD56_DS_HI 2
++#define PAD56_DS_SZ 1
++#define PAD56_SEL_I_MSK 0x00000010
++#define PAD56_SEL_I_I_MSK 0xffffffef
++#define PAD56_SEL_I_SFT 4
++#define PAD56_SEL_I_HI 4
++#define PAD56_SEL_I_SZ 1
++#define PAD56_OD_MSK 0x00000100
++#define PAD56_OD_I_MSK 0xfffffeff
++#define PAD56_OD_SFT 8
++#define PAD56_OD_HI 8
++#define PAD56_OD_SZ 1
++#define JTAG_TDI_ID_MSK 0x10000000
++#define JTAG_TDI_ID_I_MSK 0xefffffff
++#define JTAG_TDI_ID_SFT 28
++#define JTAG_TDI_ID_HI 28
++#define JTAG_TDI_ID_SZ 1
++#define PAD57_OE_MSK 0x00000001
++#define PAD57_OE_I_MSK 0xfffffffe
++#define PAD57_OE_SFT 0
++#define PAD57_OE_HI 0
++#define PAD57_OE_SZ 1
++#define PAD57_PE_MSK 0x00000002
++#define PAD57_PE_I_MSK 0xfffffffd
++#define PAD57_PE_SFT 1
++#define PAD57_PE_HI 1
++#define PAD57_PE_SZ 1
++#define PAD57_DS_MSK 0x00000004
++#define PAD57_DS_I_MSK 0xfffffffb
++#define PAD57_DS_SFT 2
++#define PAD57_DS_HI 2
++#define PAD57_DS_SZ 1
++#define PAD57_IE_MSK 0x00000008
++#define PAD57_IE_I_MSK 0xfffffff7
++#define PAD57_IE_SFT 3
++#define PAD57_IE_HI 3
++#define PAD57_IE_SZ 1
++#define PAD57_SEL_I_MSK 0x00000030
++#define PAD57_SEL_I_I_MSK 0xffffffcf
++#define PAD57_SEL_I_SFT 4
++#define PAD57_SEL_I_HI 5
++#define PAD57_SEL_I_SZ 2
++#define PAD57_OD_MSK 0x00000100
++#define PAD57_OD_I_MSK 0xfffffeff
++#define PAD57_OD_SFT 8
++#define PAD57_OD_HI 8
++#define PAD57_OD_SZ 1
++#define PAD57_SEL_O_MSK 0x00003000
++#define PAD57_SEL_O_I_MSK 0xffffcfff
++#define PAD57_SEL_O_SFT 12
++#define PAD57_SEL_O_HI 13
++#define PAD57_SEL_O_SZ 2
++#define PAD57_SEL_OE_MSK 0x00100000
++#define PAD57_SEL_OE_I_MSK 0xffefffff
++#define PAD57_SEL_OE_SFT 20
++#define PAD57_SEL_OE_HI 20
++#define PAD57_SEL_OE_SZ 1
++#define JTAG_TDO_ID_MSK 0x10000000
++#define JTAG_TDO_ID_I_MSK 0xefffffff
++#define JTAG_TDO_ID_SFT 28
++#define JTAG_TDO_ID_HI 28
++#define JTAG_TDO_ID_SZ 1
++#define PAD58_OE_MSK 0x00000001
++#define PAD58_OE_I_MSK 0xfffffffe
++#define PAD58_OE_SFT 0
++#define PAD58_OE_HI 0
++#define PAD58_OE_SZ 1
++#define PAD58_PE_MSK 0x00000002
++#define PAD58_PE_I_MSK 0xfffffffd
++#define PAD58_PE_SFT 1
++#define PAD58_PE_HI 1
++#define PAD58_PE_SZ 1
++#define PAD58_DS_MSK 0x00000004
++#define PAD58_DS_I_MSK 0xfffffffb
++#define PAD58_DS_SFT 2
++#define PAD58_DS_HI 2
++#define PAD58_DS_SZ 1
++#define PAD58_IE_MSK 0x00000008
++#define PAD58_IE_I_MSK 0xfffffff7
++#define PAD58_IE_SFT 3
++#define PAD58_IE_HI 3
++#define PAD58_IE_SZ 1
++#define PAD58_SEL_I_MSK 0x00000030
++#define PAD58_SEL_I_I_MSK 0xffffffcf
++#define PAD58_SEL_I_SFT 4
++#define PAD58_SEL_I_HI 5
++#define PAD58_SEL_I_SZ 2
++#define PAD58_OD_MSK 0x00000100
++#define PAD58_OD_I_MSK 0xfffffeff
++#define PAD58_OD_SFT 8
++#define PAD58_OD_HI 8
++#define PAD58_OD_SZ 1
++#define PAD58_SEL_O_MSK 0x00001000
++#define PAD58_SEL_O_I_MSK 0xffffefff
++#define PAD58_SEL_O_SFT 12
++#define PAD58_SEL_O_HI 12
++#define PAD58_SEL_O_SZ 1
++#define TEST_16_ID_MSK 0x10000000
++#define TEST_16_ID_I_MSK 0xefffffff
++#define TEST_16_ID_SFT 28
++#define TEST_16_ID_HI 28
++#define TEST_16_ID_SZ 1
++#define PAD59_OE_MSK 0x00000001
++#define PAD59_OE_I_MSK 0xfffffffe
++#define PAD59_OE_SFT 0
++#define PAD59_OE_HI 0
++#define PAD59_OE_SZ 1
++#define PAD59_PE_MSK 0x00000002
++#define PAD59_PE_I_MSK 0xfffffffd
++#define PAD59_PE_SFT 1
++#define PAD59_PE_HI 1
++#define PAD59_PE_SZ 1
++#define PAD59_DS_MSK 0x00000004
++#define PAD59_DS_I_MSK 0xfffffffb
++#define PAD59_DS_SFT 2
++#define PAD59_DS_HI 2
++#define PAD59_DS_SZ 1
++#define PAD59_IE_MSK 0x00000008
++#define PAD59_IE_I_MSK 0xfffffff7
++#define PAD59_IE_SFT 3
++#define PAD59_IE_HI 3
++#define PAD59_IE_SZ 1
++#define PAD59_SEL_I_MSK 0x00000030
++#define PAD59_SEL_I_I_MSK 0xffffffcf
++#define PAD59_SEL_I_SFT 4
++#define PAD59_SEL_I_HI 5
++#define PAD59_SEL_I_SZ 2
++#define PAD59_OD_MSK 0x00000100
++#define PAD59_OD_I_MSK 0xfffffeff
++#define PAD59_OD_SFT 8
++#define PAD59_OD_HI 8
++#define PAD59_OD_SZ 1
++#define PAD59_SEL_O_MSK 0x00001000
++#define PAD59_SEL_O_I_MSK 0xffffefff
++#define PAD59_SEL_O_SFT 12
++#define PAD59_SEL_O_HI 12
++#define PAD59_SEL_O_SZ 1
++#define TEST_17_ID_MSK 0x10000000
++#define TEST_17_ID_I_MSK 0xefffffff
++#define TEST_17_ID_SFT 28
++#define TEST_17_ID_HI 28
++#define TEST_17_ID_SZ 1
++#define PAD60_OE_MSK 0x00000001
++#define PAD60_OE_I_MSK 0xfffffffe
++#define PAD60_OE_SFT 0
++#define PAD60_OE_HI 0
++#define PAD60_OE_SZ 1
++#define PAD60_PE_MSK 0x00000002
++#define PAD60_PE_I_MSK 0xfffffffd
++#define PAD60_PE_SFT 1
++#define PAD60_PE_HI 1
++#define PAD60_PE_SZ 1
++#define PAD60_DS_MSK 0x00000004
++#define PAD60_DS_I_MSK 0xfffffffb
++#define PAD60_DS_SFT 2
++#define PAD60_DS_HI 2
++#define PAD60_DS_SZ 1
++#define PAD60_IE_MSK 0x00000008
++#define PAD60_IE_I_MSK 0xfffffff7
++#define PAD60_IE_SFT 3
++#define PAD60_IE_HI 3
++#define PAD60_IE_SZ 1
++#define PAD60_SEL_I_MSK 0x00000030
++#define PAD60_SEL_I_I_MSK 0xffffffcf
++#define PAD60_SEL_I_SFT 4
++#define PAD60_SEL_I_HI 5
++#define PAD60_SEL_I_SZ 2
++#define PAD60_OD_MSK 0x00000100
++#define PAD60_OD_I_MSK 0xfffffeff
++#define PAD60_OD_SFT 8
++#define PAD60_OD_HI 8
++#define PAD60_OD_SZ 1
++#define PAD60_SEL_O_MSK 0x00001000
++#define PAD60_SEL_O_I_MSK 0xffffefff
++#define PAD60_SEL_O_SFT 12
++#define PAD60_SEL_O_HI 12
++#define PAD60_SEL_O_SZ 1
++#define TEST_18_ID_MSK 0x10000000
++#define TEST_18_ID_I_MSK 0xefffffff
++#define TEST_18_ID_SFT 28
++#define TEST_18_ID_HI 28
++#define TEST_18_ID_SZ 1
++#define PAD61_OE_MSK 0x00000001
++#define PAD61_OE_I_MSK 0xfffffffe
++#define PAD61_OE_SFT 0
++#define PAD61_OE_HI 0
++#define PAD61_OE_SZ 1
++#define PAD61_PE_MSK 0x00000002
++#define PAD61_PE_I_MSK 0xfffffffd
++#define PAD61_PE_SFT 1
++#define PAD61_PE_HI 1
++#define PAD61_PE_SZ 1
++#define PAD61_DS_MSK 0x00000004
++#define PAD61_DS_I_MSK 0xfffffffb
++#define PAD61_DS_SFT 2
++#define PAD61_DS_HI 2
++#define PAD61_DS_SZ 1
++#define PAD61_IE_MSK 0x00000008
++#define PAD61_IE_I_MSK 0xfffffff7
++#define PAD61_IE_SFT 3
++#define PAD61_IE_HI 3
++#define PAD61_IE_SZ 1
++#define PAD61_SEL_I_MSK 0x00000010
++#define PAD61_SEL_I_I_MSK 0xffffffef
++#define PAD61_SEL_I_SFT 4
++#define PAD61_SEL_I_HI 4
++#define PAD61_SEL_I_SZ 1
++#define PAD61_OD_MSK 0x00000100
++#define PAD61_OD_I_MSK 0xfffffeff
++#define PAD61_OD_SFT 8
++#define PAD61_OD_HI 8
++#define PAD61_OD_SZ 1
++#define PAD61_SEL_O_MSK 0x00003000
++#define PAD61_SEL_O_I_MSK 0xffffcfff
++#define PAD61_SEL_O_SFT 12
++#define PAD61_SEL_O_HI 13
++#define PAD61_SEL_O_SZ 2
++#define TEST_19_ID_MSK 0x10000000
++#define TEST_19_ID_I_MSK 0xefffffff
++#define TEST_19_ID_SFT 28
++#define TEST_19_ID_HI 28
++#define TEST_19_ID_SZ 1
++#define PAD62_OE_MSK 0x00000001
++#define PAD62_OE_I_MSK 0xfffffffe
++#define PAD62_OE_SFT 0
++#define PAD62_OE_HI 0
++#define PAD62_OE_SZ 1
++#define PAD62_PE_MSK 0x00000002
++#define PAD62_PE_I_MSK 0xfffffffd
++#define PAD62_PE_SFT 1
++#define PAD62_PE_HI 1
++#define PAD62_PE_SZ 1
++#define PAD62_DS_MSK 0x00000004
++#define PAD62_DS_I_MSK 0xfffffffb
++#define PAD62_DS_SFT 2
++#define PAD62_DS_HI 2
++#define PAD62_DS_SZ 1
++#define PAD62_IE_MSK 0x00000008
++#define PAD62_IE_I_MSK 0xfffffff7
++#define PAD62_IE_SFT 3
++#define PAD62_IE_HI 3
++#define PAD62_IE_SZ 1
++#define PAD62_SEL_I_MSK 0x00000010
++#define PAD62_SEL_I_I_MSK 0xffffffef
++#define PAD62_SEL_I_SFT 4
++#define PAD62_SEL_I_HI 4
++#define PAD62_SEL_I_SZ 1
++#define PAD62_OD_MSK 0x00000100
++#define PAD62_OD_I_MSK 0xfffffeff
++#define PAD62_OD_SFT 8
++#define PAD62_OD_HI 8
++#define PAD62_OD_SZ 1
++#define PAD62_SEL_O_MSK 0x00001000
++#define PAD62_SEL_O_I_MSK 0xffffefff
++#define PAD62_SEL_O_SFT 12
++#define PAD62_SEL_O_HI 12
++#define PAD62_SEL_O_SZ 1
++#define TEST_20_ID_MSK 0x10000000
++#define TEST_20_ID_I_MSK 0xefffffff
++#define TEST_20_ID_SFT 28
++#define TEST_20_ID_HI 28
++#define TEST_20_ID_SZ 1
++#define PAD64_OE_MSK 0x00000001
++#define PAD64_OE_I_MSK 0xfffffffe
++#define PAD64_OE_SFT 0
++#define PAD64_OE_HI 0
++#define PAD64_OE_SZ 1
++#define PAD64_PE_MSK 0x00000002
++#define PAD64_PE_I_MSK 0xfffffffd
++#define PAD64_PE_SFT 1
++#define PAD64_PE_HI 1
++#define PAD64_PE_SZ 1
++#define PAD64_DS_MSK 0x00000004
++#define PAD64_DS_I_MSK 0xfffffffb
++#define PAD64_DS_SFT 2
++#define PAD64_DS_HI 2
++#define PAD64_DS_SZ 1
++#define PAD64_IE_MSK 0x00000008
++#define PAD64_IE_I_MSK 0xfffffff7
++#define PAD64_IE_SFT 3
++#define PAD64_IE_HI 3
++#define PAD64_IE_SZ 1
++#define PAD64_SEL_I_MSK 0x00000070
++#define PAD64_SEL_I_I_MSK 0xffffff8f
++#define PAD64_SEL_I_SFT 4
++#define PAD64_SEL_I_HI 6
++#define PAD64_SEL_I_SZ 3
++#define PAD64_OD_MSK 0x00000100
++#define PAD64_OD_I_MSK 0xfffffeff
++#define PAD64_OD_SFT 8
++#define PAD64_OD_HI 8
++#define PAD64_OD_SZ 1
++#define PAD64_SEL_O_MSK 0x00003000
++#define PAD64_SEL_O_I_MSK 0xffffcfff
++#define PAD64_SEL_O_SFT 12
++#define PAD64_SEL_O_HI 13
++#define PAD64_SEL_O_SZ 2
++#define PAD64_SEL_OE_MSK 0x00100000
++#define PAD64_SEL_OE_I_MSK 0xffefffff
++#define PAD64_SEL_OE_SFT 20
++#define PAD64_SEL_OE_HI 20
++#define PAD64_SEL_OE_SZ 1
++#define GPIO_15_IP_ID_MSK 0x10000000
++#define GPIO_15_IP_ID_I_MSK 0xefffffff
++#define GPIO_15_IP_ID_SFT 28
++#define GPIO_15_IP_ID_HI 28
++#define GPIO_15_IP_ID_SZ 1
++#define PAD65_OE_MSK 0x00000001
++#define PAD65_OE_I_MSK 0xfffffffe
++#define PAD65_OE_SFT 0
++#define PAD65_OE_HI 0
++#define PAD65_OE_SZ 1
++#define PAD65_PE_MSK 0x00000002
++#define PAD65_PE_I_MSK 0xfffffffd
++#define PAD65_PE_SFT 1
++#define PAD65_PE_HI 1
++#define PAD65_PE_SZ 1
++#define PAD65_DS_MSK 0x00000004
++#define PAD65_DS_I_MSK 0xfffffffb
++#define PAD65_DS_SFT 2
++#define PAD65_DS_HI 2
++#define PAD65_DS_SZ 1
++#define PAD65_IE_MSK 0x00000008
++#define PAD65_IE_I_MSK 0xfffffff7
++#define PAD65_IE_SFT 3
++#define PAD65_IE_HI 3
++#define PAD65_IE_SZ 1
++#define PAD65_SEL_I_MSK 0x00000070
++#define PAD65_SEL_I_I_MSK 0xffffff8f
++#define PAD65_SEL_I_SFT 4
++#define PAD65_SEL_I_HI 6
++#define PAD65_SEL_I_SZ 3
++#define PAD65_OD_MSK 0x00000100
++#define PAD65_OD_I_MSK 0xfffffeff
++#define PAD65_OD_SFT 8
++#define PAD65_OD_HI 8
++#define PAD65_OD_SZ 1
++#define PAD65_SEL_O_MSK 0x00001000
++#define PAD65_SEL_O_I_MSK 0xffffefff
++#define PAD65_SEL_O_SFT 12
++#define PAD65_SEL_O_HI 12
++#define PAD65_SEL_O_SZ 1
++#define GPIO_TEST_7_IN_ID_MSK 0x10000000
++#define GPIO_TEST_7_IN_ID_I_MSK 0xefffffff
++#define GPIO_TEST_7_IN_ID_SFT 28
++#define GPIO_TEST_7_IN_ID_HI 28
++#define GPIO_TEST_7_IN_ID_SZ 1
++#define PAD66_OE_MSK 0x00000001
++#define PAD66_OE_I_MSK 0xfffffffe
++#define PAD66_OE_SFT 0
++#define PAD66_OE_HI 0
++#define PAD66_OE_SZ 1
++#define PAD66_PE_MSK 0x00000002
++#define PAD66_PE_I_MSK 0xfffffffd
++#define PAD66_PE_SFT 1
++#define PAD66_PE_HI 1
++#define PAD66_PE_SZ 1
++#define PAD66_DS_MSK 0x00000004
++#define PAD66_DS_I_MSK 0xfffffffb
++#define PAD66_DS_SFT 2
++#define PAD66_DS_HI 2
++#define PAD66_DS_SZ 1
++#define PAD66_IE_MSK 0x00000008
++#define PAD66_IE_I_MSK 0xfffffff7
++#define PAD66_IE_SFT 3
++#define PAD66_IE_HI 3
++#define PAD66_IE_SZ 1
++#define PAD66_SEL_I_MSK 0x00000030
++#define PAD66_SEL_I_I_MSK 0xffffffcf
++#define PAD66_SEL_I_SFT 4
++#define PAD66_SEL_I_HI 5
++#define PAD66_SEL_I_SZ 2
++#define PAD66_OD_MSK 0x00000100
++#define PAD66_OD_I_MSK 0xfffffeff
++#define PAD66_OD_SFT 8
++#define PAD66_OD_HI 8
++#define PAD66_OD_SZ 1
++#define PAD66_SEL_O_MSK 0x00003000
++#define PAD66_SEL_O_I_MSK 0xffffcfff
++#define PAD66_SEL_O_SFT 12
++#define PAD66_SEL_O_HI 13
++#define PAD66_SEL_O_SZ 2
++#define GPIO_17_QP_ID_MSK 0x10000000
++#define GPIO_17_QP_ID_I_MSK 0xefffffff
++#define GPIO_17_QP_ID_SFT 28
++#define GPIO_17_QP_ID_HI 28
++#define GPIO_17_QP_ID_SZ 1
++#define PAD68_OE_MSK 0x00000001
++#define PAD68_OE_I_MSK 0xfffffffe
++#define PAD68_OE_SFT 0
++#define PAD68_OE_HI 0
++#define PAD68_OE_SZ 1
++#define PAD68_PE_MSK 0x00000002
++#define PAD68_PE_I_MSK 0xfffffffd
++#define PAD68_PE_SFT 1
++#define PAD68_PE_HI 1
++#define PAD68_PE_SZ 1
++#define PAD68_DS_MSK 0x00000004
++#define PAD68_DS_I_MSK 0xfffffffb
++#define PAD68_DS_SFT 2
++#define PAD68_DS_HI 2
++#define PAD68_DS_SZ 1
++#define PAD68_IE_MSK 0x00000008
++#define PAD68_IE_I_MSK 0xfffffff7
++#define PAD68_IE_SFT 3
++#define PAD68_IE_HI 3
++#define PAD68_IE_SZ 1
++#define PAD68_OD_MSK 0x00000100
++#define PAD68_OD_I_MSK 0xfffffeff
++#define PAD68_OD_SFT 8
++#define PAD68_OD_HI 8
++#define PAD68_OD_SZ 1
++#define PAD68_SEL_O_MSK 0x00001000
++#define PAD68_SEL_O_I_MSK 0xffffefff
++#define PAD68_SEL_O_SFT 12
++#define PAD68_SEL_O_HI 12
++#define PAD68_SEL_O_SZ 1
++#define GPIO_19_ID_MSK 0x10000000
++#define GPIO_19_ID_I_MSK 0xefffffff
++#define GPIO_19_ID_SFT 28
++#define GPIO_19_ID_HI 28
++#define GPIO_19_ID_SZ 1
++#define PAD67_OE_MSK 0x00000001
++#define PAD67_OE_I_MSK 0xfffffffe
++#define PAD67_OE_SFT 0
++#define PAD67_OE_HI 0
++#define PAD67_OE_SZ 1
++#define PAD67_PE_MSK 0x00000002
++#define PAD67_PE_I_MSK 0xfffffffd
++#define PAD67_PE_SFT 1
++#define PAD67_PE_HI 1
++#define PAD67_PE_SZ 1
++#define PAD67_DS_MSK 0x00000004
++#define PAD67_DS_I_MSK 0xfffffffb
++#define PAD67_DS_SFT 2
++#define PAD67_DS_HI 2
++#define PAD67_DS_SZ 1
++#define PAD67_IE_MSK 0x00000008
++#define PAD67_IE_I_MSK 0xfffffff7
++#define PAD67_IE_SFT 3
++#define PAD67_IE_HI 3
++#define PAD67_IE_SZ 1
++#define PAD67_SEL_I_MSK 0x00000070
++#define PAD67_SEL_I_I_MSK 0xffffff8f
++#define PAD67_SEL_I_SFT 4
++#define PAD67_SEL_I_HI 6
++#define PAD67_SEL_I_SZ 3
++#define PAD67_OD_MSK 0x00000100
++#define PAD67_OD_I_MSK 0xfffffeff
++#define PAD67_OD_SFT 8
++#define PAD67_OD_HI 8
++#define PAD67_OD_SZ 1
++#define PAD67_SEL_O_MSK 0x00003000
++#define PAD67_SEL_O_I_MSK 0xffffcfff
++#define PAD67_SEL_O_SFT 12
++#define PAD67_SEL_O_HI 13
++#define PAD67_SEL_O_SZ 2
++#define GPIO_TEST_8_QN_ID_MSK 0x10000000
++#define GPIO_TEST_8_QN_ID_I_MSK 0xefffffff
++#define GPIO_TEST_8_QN_ID_SFT 28
++#define GPIO_TEST_8_QN_ID_HI 28
++#define GPIO_TEST_8_QN_ID_SZ 1
++#define PAD69_OE_MSK 0x00000001
++#define PAD69_OE_I_MSK 0xfffffffe
++#define PAD69_OE_SFT 0
++#define PAD69_OE_HI 0
++#define PAD69_OE_SZ 1
++#define PAD69_PE_MSK 0x00000002
++#define PAD69_PE_I_MSK 0xfffffffd
++#define PAD69_PE_SFT 1
++#define PAD69_PE_HI 1
++#define PAD69_PE_SZ 1
++#define PAD69_DS_MSK 0x00000004
++#define PAD69_DS_I_MSK 0xfffffffb
++#define PAD69_DS_SFT 2
++#define PAD69_DS_HI 2
++#define PAD69_DS_SZ 1
++#define PAD69_IE_MSK 0x00000008
++#define PAD69_IE_I_MSK 0xfffffff7
++#define PAD69_IE_SFT 3
++#define PAD69_IE_HI 3
++#define PAD69_IE_SZ 1
++#define PAD69_SEL_I_MSK 0x00000030
++#define PAD69_SEL_I_I_MSK 0xffffffcf
++#define PAD69_SEL_I_SFT 4
++#define PAD69_SEL_I_HI 5
++#define PAD69_SEL_I_SZ 2
++#define PAD69_OD_MSK 0x00000100
++#define PAD69_OD_I_MSK 0xfffffeff
++#define PAD69_OD_SFT 8
++#define PAD69_OD_HI 8
++#define PAD69_OD_SZ 1
++#define PAD69_SEL_O_MSK 0x00001000
++#define PAD69_SEL_O_I_MSK 0xffffefff
++#define PAD69_SEL_O_SFT 12
++#define PAD69_SEL_O_HI 12
++#define PAD69_SEL_O_SZ 1
++#define STRAP2_MSK 0x08000000
++#define STRAP2_I_MSK 0xf7ffffff
++#define STRAP2_SFT 27
++#define STRAP2_HI 27
++#define STRAP2_SZ 1
++#define GPIO_20_ID_MSK 0x10000000
++#define GPIO_20_ID_I_MSK 0xefffffff
++#define GPIO_20_ID_SFT 28
++#define GPIO_20_ID_HI 28
++#define GPIO_20_ID_SZ 1
++#define PAD70_OE_MSK 0x00000001
++#define PAD70_OE_I_MSK 0xfffffffe
++#define PAD70_OE_SFT 0
++#define PAD70_OE_HI 0
++#define PAD70_OE_SZ 1
++#define PAD70_PE_MSK 0x00000002
++#define PAD70_PE_I_MSK 0xfffffffd
++#define PAD70_PE_SFT 1
++#define PAD70_PE_HI 1
++#define PAD70_PE_SZ 1
++#define PAD70_DS_MSK 0x00000004
++#define PAD70_DS_I_MSK 0xfffffffb
++#define PAD70_DS_SFT 2
++#define PAD70_DS_HI 2
++#define PAD70_DS_SZ 1
++#define PAD70_IE_MSK 0x00000008
++#define PAD70_IE_I_MSK 0xfffffff7
++#define PAD70_IE_SFT 3
++#define PAD70_IE_HI 3
++#define PAD70_IE_SZ 1
++#define PAD70_SEL_I_MSK 0x00000030
++#define PAD70_SEL_I_I_MSK 0xffffffcf
++#define PAD70_SEL_I_SFT 4
++#define PAD70_SEL_I_HI 5
++#define PAD70_SEL_I_SZ 2
++#define PAD70_OD_MSK 0x00000100
++#define PAD70_OD_I_MSK 0xfffffeff
++#define PAD70_OD_SFT 8
++#define PAD70_OD_HI 8
++#define PAD70_OD_SZ 1
++#define PAD70_SEL_O_MSK 0x00007000
++#define PAD70_SEL_O_I_MSK 0xffff8fff
++#define PAD70_SEL_O_SFT 12
++#define PAD70_SEL_O_HI 14
++#define PAD70_SEL_O_SZ 3
++#define GPIO_21_ID_MSK 0x10000000
++#define GPIO_21_ID_I_MSK 0xefffffff
++#define GPIO_21_ID_SFT 28
++#define GPIO_21_ID_HI 28
++#define GPIO_21_ID_SZ 1
++#define PAD231_OE_MSK 0x00000001
++#define PAD231_OE_I_MSK 0xfffffffe
++#define PAD231_OE_SFT 0
++#define PAD231_OE_HI 0
++#define PAD231_OE_SZ 1
++#define PAD231_PE_MSK 0x00000002
++#define PAD231_PE_I_MSK 0xfffffffd
++#define PAD231_PE_SFT 1
++#define PAD231_PE_HI 1
++#define PAD231_PE_SZ 1
++#define PAD231_DS_MSK 0x00000004
++#define PAD231_DS_I_MSK 0xfffffffb
++#define PAD231_DS_SFT 2
++#define PAD231_DS_HI 2
++#define PAD231_DS_SZ 1
++#define PAD231_IE_MSK 0x00000008
++#define PAD231_IE_I_MSK 0xfffffff7
++#define PAD231_IE_SFT 3
++#define PAD231_IE_HI 3
++#define PAD231_IE_SZ 1
++#define PAD231_OD_MSK 0x00000100
++#define PAD231_OD_I_MSK 0xfffffeff
++#define PAD231_OD_SFT 8
++#define PAD231_OD_HI 8
++#define PAD231_OD_SZ 1
++#define PIN_40_OR_56_ID_MSK 0x10000000
++#define PIN_40_OR_56_ID_I_MSK 0xefffffff
++#define PIN_40_OR_56_ID_SFT 28
++#define PIN_40_OR_56_ID_HI 28
++#define PIN_40_OR_56_ID_SZ 1
++#define MP_PHY2RX_DATA__0_SEL_MSK 0x00000001
++#define MP_PHY2RX_DATA__0_SEL_I_MSK 0xfffffffe
++#define MP_PHY2RX_DATA__0_SEL_SFT 0
++#define MP_PHY2RX_DATA__0_SEL_HI 0
++#define MP_PHY2RX_DATA__0_SEL_SZ 1
++#define MP_PHY2RX_DATA__1_SEL_MSK 0x00000002
++#define MP_PHY2RX_DATA__1_SEL_I_MSK 0xfffffffd
++#define MP_PHY2RX_DATA__1_SEL_SFT 1
++#define MP_PHY2RX_DATA__1_SEL_HI 1
++#define MP_PHY2RX_DATA__1_SEL_SZ 1
++#define MP_TX_FF_RPTR__1_SEL_MSK 0x00000004
++#define MP_TX_FF_RPTR__1_SEL_I_MSK 0xfffffffb
++#define MP_TX_FF_RPTR__1_SEL_SFT 2
++#define MP_TX_FF_RPTR__1_SEL_HI 2
++#define MP_TX_FF_RPTR__1_SEL_SZ 1
++#define MP_RX_FF_WPTR__2_SEL_MSK 0x00000008
++#define MP_RX_FF_WPTR__2_SEL_I_MSK 0xfffffff7
++#define MP_RX_FF_WPTR__2_SEL_SFT 3
++#define MP_RX_FF_WPTR__2_SEL_HI 3
++#define MP_RX_FF_WPTR__2_SEL_SZ 1
++#define MP_RX_FF_WPTR__1_SEL_MSK 0x00000010
++#define MP_RX_FF_WPTR__1_SEL_I_MSK 0xffffffef
++#define MP_RX_FF_WPTR__1_SEL_SFT 4
++#define MP_RX_FF_WPTR__1_SEL_HI 4
++#define MP_RX_FF_WPTR__1_SEL_SZ 1
++#define MP_RX_FF_WPTR__0_SEL_MSK 0x00000020
++#define MP_RX_FF_WPTR__0_SEL_I_MSK 0xffffffdf
++#define MP_RX_FF_WPTR__0_SEL_SFT 5
++#define MP_RX_FF_WPTR__0_SEL_HI 5
++#define MP_RX_FF_WPTR__0_SEL_SZ 1
++#define MP_PHY2RX_DATA__2_SEL_MSK 0x00000040
++#define MP_PHY2RX_DATA__2_SEL_I_MSK 0xffffffbf
++#define MP_PHY2RX_DATA__2_SEL_SFT 6
++#define MP_PHY2RX_DATA__2_SEL_HI 6
++#define MP_PHY2RX_DATA__2_SEL_SZ 1
++#define MP_PHY2RX_DATA__4_SEL_MSK 0x00000080
++#define MP_PHY2RX_DATA__4_SEL_I_MSK 0xffffff7f
++#define MP_PHY2RX_DATA__4_SEL_SFT 7
++#define MP_PHY2RX_DATA__4_SEL_HI 7
++#define MP_PHY2RX_DATA__4_SEL_SZ 1
++#define I2CM_SDA_ID_SEL_MSK 0x00000300
++#define I2CM_SDA_ID_SEL_I_MSK 0xfffffcff
++#define I2CM_SDA_ID_SEL_SFT 8
++#define I2CM_SDA_ID_SEL_HI 9
++#define I2CM_SDA_ID_SEL_SZ 2
++#define CRYSTAL_OUT_REQ_SEL_MSK 0x00000400
++#define CRYSTAL_OUT_REQ_SEL_I_MSK 0xfffffbff
++#define CRYSTAL_OUT_REQ_SEL_SFT 10
++#define CRYSTAL_OUT_REQ_SEL_HI 10
++#define CRYSTAL_OUT_REQ_SEL_SZ 1
++#define MP_PHY2RX_DATA__5_SEL_MSK 0x00000800
++#define MP_PHY2RX_DATA__5_SEL_I_MSK 0xfffff7ff
++#define MP_PHY2RX_DATA__5_SEL_SFT 11
++#define MP_PHY2RX_DATA__5_SEL_HI 11
++#define MP_PHY2RX_DATA__5_SEL_SZ 1
++#define MP_PHY2RX_DATA__3_SEL_MSK 0x00001000
++#define MP_PHY2RX_DATA__3_SEL_I_MSK 0xffffefff
++#define MP_PHY2RX_DATA__3_SEL_SFT 12
++#define MP_PHY2RX_DATA__3_SEL_HI 12
++#define MP_PHY2RX_DATA__3_SEL_SZ 1
++#define UART_RXD_SEL_MSK 0x00006000
++#define UART_RXD_SEL_I_MSK 0xffff9fff
++#define UART_RXD_SEL_SFT 13
++#define UART_RXD_SEL_HI 14
++#define UART_RXD_SEL_SZ 2
++#define MP_PHY2RX_DATA__6_SEL_MSK 0x00008000
++#define MP_PHY2RX_DATA__6_SEL_I_MSK 0xffff7fff
++#define MP_PHY2RX_DATA__6_SEL_SFT 15
++#define MP_PHY2RX_DATA__6_SEL_HI 15
++#define MP_PHY2RX_DATA__6_SEL_SZ 1
++#define DAT_UART_NCTS_SEL_MSK 0x00010000
++#define DAT_UART_NCTS_SEL_I_MSK 0xfffeffff
++#define DAT_UART_NCTS_SEL_SFT 16
++#define DAT_UART_NCTS_SEL_HI 16
++#define DAT_UART_NCTS_SEL_SZ 1
++#define GPIO_LOG_STOP_SEL_MSK 0x000e0000
++#define GPIO_LOG_STOP_SEL_I_MSK 0xfff1ffff
++#define GPIO_LOG_STOP_SEL_SFT 17
++#define GPIO_LOG_STOP_SEL_HI 19
++#define GPIO_LOG_STOP_SEL_SZ 3
++#define MP_TX_FF_RPTR__0_SEL_MSK 0x00100000
++#define MP_TX_FF_RPTR__0_SEL_I_MSK 0xffefffff
++#define MP_TX_FF_RPTR__0_SEL_SFT 20
++#define MP_TX_FF_RPTR__0_SEL_HI 20
++#define MP_TX_FF_RPTR__0_SEL_SZ 1
++#define MP_PHY_RX_WRST_N_SEL_MSK 0x00200000
++#define MP_PHY_RX_WRST_N_SEL_I_MSK 0xffdfffff
++#define MP_PHY_RX_WRST_N_SEL_SFT 21
++#define MP_PHY_RX_WRST_N_SEL_HI 21
++#define MP_PHY_RX_WRST_N_SEL_SZ 1
++#define EXT_32K_SEL_MSK 0x00c00000
++#define EXT_32K_SEL_I_MSK 0xff3fffff
++#define EXT_32K_SEL_SFT 22
++#define EXT_32K_SEL_HI 23
++#define EXT_32K_SEL_SZ 2
++#define MP_PHY2RX_DATA__7_SEL_MSK 0x01000000
++#define MP_PHY2RX_DATA__7_SEL_I_MSK 0xfeffffff
++#define MP_PHY2RX_DATA__7_SEL_SFT 24
++#define MP_PHY2RX_DATA__7_SEL_HI 24
++#define MP_PHY2RX_DATA__7_SEL_SZ 1
++#define MP_TX_FF_RPTR__2_SEL_MSK 0x02000000
++#define MP_TX_FF_RPTR__2_SEL_I_MSK 0xfdffffff
++#define MP_TX_FF_RPTR__2_SEL_SFT 25
++#define MP_TX_FF_RPTR__2_SEL_HI 25
++#define MP_TX_FF_RPTR__2_SEL_SZ 1
++#define PMUINT_WAKE_SEL_MSK 0x1c000000
++#define PMUINT_WAKE_SEL_I_MSK 0xe3ffffff
++#define PMUINT_WAKE_SEL_SFT 26
++#define PMUINT_WAKE_SEL_HI 28
++#define PMUINT_WAKE_SEL_SZ 3
++#define I2CM_SCL_ID_SEL_MSK 0x20000000
++#define I2CM_SCL_ID_SEL_I_MSK 0xdfffffff
++#define I2CM_SCL_ID_SEL_SFT 29
++#define I2CM_SCL_ID_SEL_HI 29
++#define I2CM_SCL_ID_SEL_SZ 1
++#define MP_MRX_RX_EN_SEL_MSK 0x40000000
++#define MP_MRX_RX_EN_SEL_I_MSK 0xbfffffff
++#define MP_MRX_RX_EN_SEL_SFT 30
++#define MP_MRX_RX_EN_SEL_HI 30
++#define MP_MRX_RX_EN_SEL_SZ 1
++#define DAT_UART_RXD_SEL_0_MSK 0x80000000
++#define DAT_UART_RXD_SEL_0_I_MSK 0x7fffffff
++#define DAT_UART_RXD_SEL_0_SFT 31
++#define DAT_UART_RXD_SEL_0_HI 31
++#define DAT_UART_RXD_SEL_0_SZ 1
++#define DAT_UART_RXD_SEL_1_MSK 0x00000001
++#define DAT_UART_RXD_SEL_1_I_MSK 0xfffffffe
++#define DAT_UART_RXD_SEL_1_SFT 0
++#define DAT_UART_RXD_SEL_1_HI 0
++#define DAT_UART_RXD_SEL_1_SZ 1
++#define SPI_DI_SEL_MSK 0x00000002
++#define SPI_DI_SEL_I_MSK 0xfffffffd
++#define SPI_DI_SEL_SFT 1
++#define SPI_DI_SEL_HI 1
++#define SPI_DI_SEL_SZ 1
++#define IO_PORT_REG_MSK 0x0001ffff
++#define IO_PORT_REG_I_MSK 0xfffe0000
++#define IO_PORT_REG_SFT 0
++#define IO_PORT_REG_HI 16
++#define IO_PORT_REG_SZ 17
++#define MASK_RX_INT_MSK 0x00000001
++#define MASK_RX_INT_I_MSK 0xfffffffe
++#define MASK_RX_INT_SFT 0
++#define MASK_RX_INT_HI 0
++#define MASK_RX_INT_SZ 1
++#define MASK_TX_INT_MSK 0x00000002
++#define MASK_TX_INT_I_MSK 0xfffffffd
++#define MASK_TX_INT_SFT 1
++#define MASK_TX_INT_HI 1
++#define MASK_TX_INT_SZ 1
++#define MASK_SOC_SYSTEM_INT_MSK 0x00000004
++#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb
++#define MASK_SOC_SYSTEM_INT_SFT 2
++#define MASK_SOC_SYSTEM_INT_HI 2
++#define MASK_SOC_SYSTEM_INT_SZ 1
++#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008
++#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7
++#define EDCA0_LOW_THR_INT_MASK_SFT 3
++#define EDCA0_LOW_THR_INT_MASK_HI 3
++#define EDCA0_LOW_THR_INT_MASK_SZ 1
++#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010
++#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef
++#define EDCA1_LOW_THR_INT_MASK_SFT 4
++#define EDCA1_LOW_THR_INT_MASK_HI 4
++#define EDCA1_LOW_THR_INT_MASK_SZ 1
++#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020
++#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf
++#define EDCA2_LOW_THR_INT_MASK_SFT 5
++#define EDCA2_LOW_THR_INT_MASK_HI 5
++#define EDCA2_LOW_THR_INT_MASK_SZ 1
++#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040
++#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf
++#define EDCA3_LOW_THR_INT_MASK_SFT 6
++#define EDCA3_LOW_THR_INT_MASK_HI 6
++#define EDCA3_LOW_THR_INT_MASK_SZ 1
++#define TX_LIMIT_INT_MASK_MSK 0x00000080
++#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f
++#define TX_LIMIT_INT_MASK_SFT 7
++#define TX_LIMIT_INT_MASK_HI 7
++#define TX_LIMIT_INT_MASK_SZ 1
++#define RX_INT_MSK 0x00000001
++#define RX_INT_I_MSK 0xfffffffe
++#define RX_INT_SFT 0
++#define RX_INT_HI 0
++#define RX_INT_SZ 1
++#define TX_COMPLETE_INT_MSK 0x00000002
++#define TX_COMPLETE_INT_I_MSK 0xfffffffd
++#define TX_COMPLETE_INT_SFT 1
++#define TX_COMPLETE_INT_HI 1
++#define TX_COMPLETE_INT_SZ 1
++#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004
++#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb
++#define SOC_SYSTEM_INT_STATUS_SFT 2
++#define SOC_SYSTEM_INT_STATUS_HI 2
++#define SOC_SYSTEM_INT_STATUS_SZ 1
++#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008
++#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7
++#define EDCA0_LOW_THR_INT_STS_SFT 3
++#define EDCA0_LOW_THR_INT_STS_HI 3
++#define EDCA0_LOW_THR_INT_STS_SZ 1
++#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010
++#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef
++#define EDCA1_LOW_THR_INT_STS_SFT 4
++#define EDCA1_LOW_THR_INT_STS_HI 4
++#define EDCA1_LOW_THR_INT_STS_SZ 1
++#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020
++#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf
++#define EDCA2_LOW_THR_INT_STS_SFT 5
++#define EDCA2_LOW_THR_INT_STS_HI 5
++#define EDCA2_LOW_THR_INT_STS_SZ 1
++#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040
++#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf
++#define EDCA3_LOW_THR_INT_STS_SFT 6
++#define EDCA3_LOW_THR_INT_STS_HI 6
++#define EDCA3_LOW_THR_INT_STS_SZ 1
++#define TX_LIMIT_INT_STS_MSK 0x00000080
++#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f
++#define TX_LIMIT_INT_STS_SFT 7
++#define TX_LIMIT_INT_STS_HI 7
++#define TX_LIMIT_INT_STS_SZ 1
++#define HOST_TRIGGERED_RX_INT_MSK 0x00000100
++#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff
++#define HOST_TRIGGERED_RX_INT_SFT 8
++#define HOST_TRIGGERED_RX_INT_HI 8
++#define HOST_TRIGGERED_RX_INT_SZ 1
++#define HOST_TRIGGERED_TX_INT_MSK 0x00000200
++#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff
++#define HOST_TRIGGERED_TX_INT_SFT 9
++#define HOST_TRIGGERED_TX_INT_HI 9
++#define HOST_TRIGGERED_TX_INT_SZ 1
++#define SOC_TRIGGER_RX_INT_MSK 0x00000400
++#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff
++#define SOC_TRIGGER_RX_INT_SFT 10
++#define SOC_TRIGGER_RX_INT_HI 10
++#define SOC_TRIGGER_RX_INT_SZ 1
++#define SOC_TRIGGER_TX_INT_MSK 0x00000800
++#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff
++#define SOC_TRIGGER_TX_INT_SFT 11
++#define SOC_TRIGGER_TX_INT_HI 11
++#define SOC_TRIGGER_TX_INT_SZ 1
++#define RDY_FOR_TX_RX_MSK 0x00000001
++#define RDY_FOR_TX_RX_I_MSK 0xfffffffe
++#define RDY_FOR_TX_RX_SFT 0
++#define RDY_FOR_TX_RX_HI 0
++#define RDY_FOR_TX_RX_SZ 1
++#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002
++#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd
++#define RDY_FOR_FW_DOWNLOAD_SFT 1
++#define RDY_FOR_FW_DOWNLOAD_HI 1
++#define RDY_FOR_FW_DOWNLOAD_SZ 1
++#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004
++#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb
++#define ILLEGAL_CMD_RESP_OPTION_SFT 2
++#define ILLEGAL_CMD_RESP_OPTION_HI 2
++#define ILLEGAL_CMD_RESP_OPTION_SZ 1
++#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008
++#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7
++#define SDIO_TRX_DATA_SEQUENCE_SFT 3
++#define SDIO_TRX_DATA_SEQUENCE_HI 3
++#define SDIO_TRX_DATA_SEQUENCE_SZ 1
++#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010
++#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef
++#define GPIO_INT_TRIGGER_OPTION_SFT 4
++#define GPIO_INT_TRIGGER_OPTION_HI 4
++#define GPIO_INT_TRIGGER_OPTION_SZ 1
++#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060
++#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f
++#define TRIGGER_FUNCTION_SETTING_SFT 5
++#define TRIGGER_FUNCTION_SETTING_HI 6
++#define TRIGGER_FUNCTION_SETTING_SZ 2
++#define CMD52_ABORT_RESPONSE_MSK 0x00000080
++#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f
++#define CMD52_ABORT_RESPONSE_SFT 7
++#define CMD52_ABORT_RESPONSE_HI 7
++#define CMD52_ABORT_RESPONSE_SZ 1
++#define RX_PACKET_LENGTH_MSK 0x0000ffff
++#define RX_PACKET_LENGTH_I_MSK 0xffff0000
++#define RX_PACKET_LENGTH_SFT 0
++#define RX_PACKET_LENGTH_HI 15
++#define RX_PACKET_LENGTH_SZ 16
++#define CARD_FW_DL_STATUS_MSK 0x00ff0000
++#define CARD_FW_DL_STATUS_I_MSK 0xff00ffff
++#define CARD_FW_DL_STATUS_SFT 16
++#define CARD_FW_DL_STATUS_HI 23
++#define CARD_FW_DL_STATUS_SZ 8
++#define TX_RX_LOOP_BACK_TEST_MSK 0x01000000
++#define TX_RX_LOOP_BACK_TEST_I_MSK 0xfeffffff
++#define TX_RX_LOOP_BACK_TEST_SFT 24
++#define TX_RX_LOOP_BACK_TEST_HI 24
++#define TX_RX_LOOP_BACK_TEST_SZ 1
++#define SDIO_LOOP_BACK_TEST_MSK 0x02000000
++#define SDIO_LOOP_BACK_TEST_I_MSK 0xfdffffff
++#define SDIO_LOOP_BACK_TEST_SFT 25
++#define SDIO_LOOP_BACK_TEST_HI 25
++#define SDIO_LOOP_BACK_TEST_SZ 1
++#define CMD52_ABORT_ACTIVE_MSK 0x10000000
++#define CMD52_ABORT_ACTIVE_I_MSK 0xefffffff
++#define CMD52_ABORT_ACTIVE_SFT 28
++#define CMD52_ABORT_ACTIVE_HI 28
++#define CMD52_ABORT_ACTIVE_SZ 1
++#define CMD52_RESET_ACTIVE_MSK 0x20000000
++#define CMD52_RESET_ACTIVE_I_MSK 0xdfffffff
++#define CMD52_RESET_ACTIVE_SFT 29
++#define CMD52_RESET_ACTIVE_HI 29
++#define CMD52_RESET_ACTIVE_SZ 1
++#define SDIO_PARTIAL_RESET_ACTIVE_MSK 0x40000000
++#define SDIO_PARTIAL_RESET_ACTIVE_I_MSK 0xbfffffff
++#define SDIO_PARTIAL_RESET_ACTIVE_SFT 30
++#define SDIO_PARTIAL_RESET_ACTIVE_HI 30
++#define SDIO_PARTIAL_RESET_ACTIVE_SZ 1
++#define SDIO_ALL_RESE_ACTIVE_MSK 0x80000000
++#define SDIO_ALL_RESE_ACTIVE_I_MSK 0x7fffffff
++#define SDIO_ALL_RESE_ACTIVE_SFT 31
++#define SDIO_ALL_RESE_ACTIVE_HI 31
++#define SDIO_ALL_RESE_ACTIVE_SZ 1
++#define RX_PACKET_LENGTH2_MSK 0x0000ffff
++#define RX_PACKET_LENGTH2_I_MSK 0xffff0000
++#define RX_PACKET_LENGTH2_SFT 0
++#define RX_PACKET_LENGTH2_HI 15
++#define RX_PACKET_LENGTH2_SZ 16
++#define RX_INT1_MSK 0x00010000
++#define RX_INT1_I_MSK 0xfffeffff
++#define RX_INT1_SFT 16
++#define RX_INT1_HI 16
++#define RX_INT1_SZ 1
++#define TX_DONE_MSK 0x00020000
++#define TX_DONE_I_MSK 0xfffdffff
++#define TX_DONE_SFT 17
++#define TX_DONE_HI 17
++#define TX_DONE_SZ 1
++#define HCI_TRX_FINISH_MSK 0x00040000
++#define HCI_TRX_FINISH_I_MSK 0xfffbffff
++#define HCI_TRX_FINISH_SFT 18
++#define HCI_TRX_FINISH_HI 18
++#define HCI_TRX_FINISH_SZ 1
++#define ALLOCATE_STATUS_MSK 0x00080000
++#define ALLOCATE_STATUS_I_MSK 0xfff7ffff
++#define ALLOCATE_STATUS_SFT 19
++#define ALLOCATE_STATUS_HI 19
++#define ALLOCATE_STATUS_SZ 1
++#define HCI_INPUT_FF_CNT_MSK 0x00f00000
++#define HCI_INPUT_FF_CNT_I_MSK 0xff0fffff
++#define HCI_INPUT_FF_CNT_SFT 20
++#define HCI_INPUT_FF_CNT_HI 23
++#define HCI_INPUT_FF_CNT_SZ 4
++#define HCI_OUTPUT_FF_CNT_MSK 0x1f000000
++#define HCI_OUTPUT_FF_CNT_I_MSK 0xe0ffffff
++#define HCI_OUTPUT_FF_CNT_SFT 24
++#define HCI_OUTPUT_FF_CNT_HI 28
++#define HCI_OUTPUT_FF_CNT_SZ 5
++#define AHB_HANG4_MSK 0x20000000
++#define AHB_HANG4_I_MSK 0xdfffffff
++#define AHB_HANG4_SFT 29
++#define AHB_HANG4_HI 29
++#define AHB_HANG4_SZ 1
++#define HCI_IN_QUE_EMPTY_MSK 0x40000000
++#define HCI_IN_QUE_EMPTY_I_MSK 0xbfffffff
++#define HCI_IN_QUE_EMPTY_SFT 30
++#define HCI_IN_QUE_EMPTY_HI 30
++#define HCI_IN_QUE_EMPTY_SZ 1
++#define SYSTEM_INT_MSK 0x80000000
++#define SYSTEM_INT_I_MSK 0x7fffffff
++#define SYSTEM_INT_SFT 31
++#define SYSTEM_INT_HI 31
++#define SYSTEM_INT_SZ 1
++#define CARD_RCA_REG_MSK 0x0000ffff
++#define CARD_RCA_REG_I_MSK 0xffff0000
++#define CARD_RCA_REG_SFT 0
++#define CARD_RCA_REG_HI 15
++#define CARD_RCA_REG_SZ 16
++#define SDIO_FIFO_WR_THLD_REG_MSK 0x000001ff
++#define SDIO_FIFO_WR_THLD_REG_I_MSK 0xfffffe00
++#define SDIO_FIFO_WR_THLD_REG_SFT 0
++#define SDIO_FIFO_WR_THLD_REG_HI 8
++#define SDIO_FIFO_WR_THLD_REG_SZ 9
++#define SDIO_FIFO_WR_LIMIT_REG_MSK 0x000001ff
++#define SDIO_FIFO_WR_LIMIT_REG_I_MSK 0xfffffe00
++#define SDIO_FIFO_WR_LIMIT_REG_SFT 0
++#define SDIO_FIFO_WR_LIMIT_REG_HI 8
++#define SDIO_FIFO_WR_LIMIT_REG_SZ 9
++#define SDIO_TX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
++#define SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
++#define SDIO_TX_DATA_BATCH_SIZE_REG_SFT 0
++#define SDIO_TX_DATA_BATCH_SIZE_REG_HI 8
++#define SDIO_TX_DATA_BATCH_SIZE_REG_SZ 9
++#define SDIO_THLD_FOR_CMD53RD_REG_MSK 0x000001ff
++#define SDIO_THLD_FOR_CMD53RD_REG_I_MSK 0xfffffe00
++#define SDIO_THLD_FOR_CMD53RD_REG_SFT 0
++#define SDIO_THLD_FOR_CMD53RD_REG_HI 8
++#define SDIO_THLD_FOR_CMD53RD_REG_SZ 9
++#define SDIO_RX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
++#define SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
++#define SDIO_RX_DATA_BATCH_SIZE_REG_SFT 0
++#define SDIO_RX_DATA_BATCH_SIZE_REG_HI 8
++#define SDIO_RX_DATA_BATCH_SIZE_REG_SZ 9
++#define START_BYTE_VALUE_MSK 0x000000ff
++#define START_BYTE_VALUE_I_MSK 0xffffff00
++#define START_BYTE_VALUE_SFT 0
++#define START_BYTE_VALUE_HI 7
++#define START_BYTE_VALUE_SZ 8
++#define END_BYTE_VALUE_MSK 0x0000ff00
++#define END_BYTE_VALUE_I_MSK 0xffff00ff
++#define END_BYTE_VALUE_SFT 8
++#define END_BYTE_VALUE_HI 15
++#define END_BYTE_VALUE_SZ 8
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8
++#define SDIO_LAST_CMD_INDEX_REG_MSK 0x0000003f
++#define SDIO_LAST_CMD_INDEX_REG_I_MSK 0xffffffc0
++#define SDIO_LAST_CMD_INDEX_REG_SFT 0
++#define SDIO_LAST_CMD_INDEX_REG_HI 5
++#define SDIO_LAST_CMD_INDEX_REG_SZ 6
++#define SDIO_LAST_CMD_CRC_REG_MSK 0x00007f00
++#define SDIO_LAST_CMD_CRC_REG_I_MSK 0xffff80ff
++#define SDIO_LAST_CMD_CRC_REG_SFT 8
++#define SDIO_LAST_CMD_CRC_REG_HI 14
++#define SDIO_LAST_CMD_CRC_REG_SZ 7
++#define SDIO_LAST_CMD_ARG_REG_MSK 0xffffffff
++#define SDIO_LAST_CMD_ARG_REG_I_MSK 0x00000000
++#define SDIO_LAST_CMD_ARG_REG_SFT 0
++#define SDIO_LAST_CMD_ARG_REG_HI 31
++#define SDIO_LAST_CMD_ARG_REG_SZ 32
++#define SDIO_BUS_STATE_REG_MSK 0x0000001f
++#define SDIO_BUS_STATE_REG_I_MSK 0xffffffe0
++#define SDIO_BUS_STATE_REG_SFT 0
++#define SDIO_BUS_STATE_REG_HI 4
++#define SDIO_BUS_STATE_REG_SZ 5
++#define SDIO_BUSY_LONG_CNT_MSK 0xffff0000
++#define SDIO_BUSY_LONG_CNT_I_MSK 0x0000ffff
++#define SDIO_BUSY_LONG_CNT_SFT 16
++#define SDIO_BUSY_LONG_CNT_HI 31
++#define SDIO_BUSY_LONG_CNT_SZ 16
++#define SDIO_CARD_STATUS_REG_MSK 0xffffffff
++#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000
++#define SDIO_CARD_STATUS_REG_SFT 0
++#define SDIO_CARD_STATUS_REG_HI 31
++#define SDIO_CARD_STATUS_REG_SZ 32
++#define R5_RESPONSE_FLAG_MSK 0x000000ff
++#define R5_RESPONSE_FLAG_I_MSK 0xffffff00
++#define R5_RESPONSE_FLAG_SFT 0
++#define R5_RESPONSE_FLAG_HI 7
++#define R5_RESPONSE_FLAG_SZ 8
++#define RESP_OUT_EDGE_MSK 0x00000100
++#define RESP_OUT_EDGE_I_MSK 0xfffffeff
++#define RESP_OUT_EDGE_SFT 8
++#define RESP_OUT_EDGE_HI 8
++#define RESP_OUT_EDGE_SZ 1
++#define DAT_OUT_EDGE_MSK 0x00000200
++#define DAT_OUT_EDGE_I_MSK 0xfffffdff
++#define DAT_OUT_EDGE_SFT 9
++#define DAT_OUT_EDGE_HI 9
++#define DAT_OUT_EDGE_SZ 1
++#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000
++#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff
++#define MCU_TO_SDIO_INFO_MASK_SFT 16
++#define MCU_TO_SDIO_INFO_MASK_HI 16
++#define MCU_TO_SDIO_INFO_MASK_SZ 1
++#define INT_THROUGH_PIN_MSK 0x00020000
++#define INT_THROUGH_PIN_I_MSK 0xfffdffff
++#define INT_THROUGH_PIN_SFT 17
++#define INT_THROUGH_PIN_HI 17
++#define INT_THROUGH_PIN_SZ 1
++#define WRITE_DATA_MSK 0x000000ff
++#define WRITE_DATA_I_MSK 0xffffff00
++#define WRITE_DATA_SFT 0
++#define WRITE_DATA_HI 7
++#define WRITE_DATA_SZ 8
++#define WRITE_ADDRESS_MSK 0x0000ff00
++#define WRITE_ADDRESS_I_MSK 0xffff00ff
++#define WRITE_ADDRESS_SFT 8
++#define WRITE_ADDRESS_HI 15
++#define WRITE_ADDRESS_SZ 8
++#define READ_DATA_MSK 0x00ff0000
++#define READ_DATA_I_MSK 0xff00ffff
++#define READ_DATA_SFT 16
++#define READ_DATA_HI 23
++#define READ_DATA_SZ 8
++#define READ_ADDRESS_MSK 0xff000000
++#define READ_ADDRESS_I_MSK 0x00ffffff
++#define READ_ADDRESS_SFT 24
++#define READ_ADDRESS_HI 31
++#define READ_ADDRESS_SZ 8
++#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff
++#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000
++#define FN1_DMA_START_ADDR_REG_SFT 0
++#define FN1_DMA_START_ADDR_REG_HI 31
++#define FN1_DMA_START_ADDR_REG_SZ 32
++#define SDIO_TO_MCU_INFO_MSK 0x000000ff
++#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00
++#define SDIO_TO_MCU_INFO_SFT 0
++#define SDIO_TO_MCU_INFO_HI 7
++#define SDIO_TO_MCU_INFO_SZ 8
++#define SDIO_PARTIAL_RESET_MSK 0x00000100
++#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff
++#define SDIO_PARTIAL_RESET_SFT 8
++#define SDIO_PARTIAL_RESET_HI 8
++#define SDIO_PARTIAL_RESET_SZ 1
++#define SDIO_ALL_RESET_MSK 0x00000200
++#define SDIO_ALL_RESET_I_MSK 0xfffffdff
++#define SDIO_ALL_RESET_SFT 9
++#define SDIO_ALL_RESET_HI 9
++#define SDIO_ALL_RESET_SZ 1
++#define PERI_MAC_ALL_RESET_MSK 0x00000400
++#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff
++#define PERI_MAC_ALL_RESET_SFT 10
++#define PERI_MAC_ALL_RESET_HI 10
++#define PERI_MAC_ALL_RESET_SZ 1
++#define MAC_ALL_RESET_MSK 0x00000800
++#define MAC_ALL_RESET_I_MSK 0xfffff7ff
++#define MAC_ALL_RESET_SFT 11
++#define MAC_ALL_RESET_HI 11
++#define MAC_ALL_RESET_SZ 1
++#define AHB_BRIDGE_RESET_MSK 0x00001000
++#define AHB_BRIDGE_RESET_I_MSK 0xffffefff
++#define AHB_BRIDGE_RESET_SFT 12
++#define AHB_BRIDGE_RESET_HI 12
++#define AHB_BRIDGE_RESET_SZ 1
++#define IO_REG_PORT_REG_MSK 0x0001ffff
++#define IO_REG_PORT_REG_I_MSK 0xfffe0000
++#define IO_REG_PORT_REG_SFT 0
++#define IO_REG_PORT_REG_HI 16
++#define IO_REG_PORT_REG_SZ 17
++#define SDIO_FIFO_EMPTY_CNT_MSK 0x0000ffff
++#define SDIO_FIFO_EMPTY_CNT_I_MSK 0xffff0000
++#define SDIO_FIFO_EMPTY_CNT_SFT 0
++#define SDIO_FIFO_EMPTY_CNT_HI 15
++#define SDIO_FIFO_EMPTY_CNT_SZ 16
++#define SDIO_FIFO_FULL_CNT_MSK 0xffff0000
++#define SDIO_FIFO_FULL_CNT_I_MSK 0x0000ffff
++#define SDIO_FIFO_FULL_CNT_SFT 16
++#define SDIO_FIFO_FULL_CNT_HI 31
++#define SDIO_FIFO_FULL_CNT_SZ 16
++#define SDIO_CRC7_ERROR_CNT_MSK 0x0000ffff
++#define SDIO_CRC7_ERROR_CNT_I_MSK 0xffff0000
++#define SDIO_CRC7_ERROR_CNT_SFT 0
++#define SDIO_CRC7_ERROR_CNT_HI 15
++#define SDIO_CRC7_ERROR_CNT_SZ 16
++#define SDIO_CRC16_ERROR_CNT_MSK 0xffff0000
++#define SDIO_CRC16_ERROR_CNT_I_MSK 0x0000ffff
++#define SDIO_CRC16_ERROR_CNT_SFT 16
++#define SDIO_CRC16_ERROR_CNT_HI 31
++#define SDIO_CRC16_ERROR_CNT_SZ 16
++#define SDIO_RD_BLOCK_CNT_MSK 0x000001ff
++#define SDIO_RD_BLOCK_CNT_I_MSK 0xfffffe00
++#define SDIO_RD_BLOCK_CNT_SFT 0
++#define SDIO_RD_BLOCK_CNT_HI 8
++#define SDIO_RD_BLOCK_CNT_SZ 9
++#define SDIO_WR_BLOCK_CNT_MSK 0x01ff0000
++#define SDIO_WR_BLOCK_CNT_I_MSK 0xfe00ffff
++#define SDIO_WR_BLOCK_CNT_SFT 16
++#define SDIO_WR_BLOCK_CNT_HI 24
++#define SDIO_WR_BLOCK_CNT_SZ 9
++#define CMD52_RD_ABORT_CNT_MSK 0x000f0000
++#define CMD52_RD_ABORT_CNT_I_MSK 0xfff0ffff
++#define CMD52_RD_ABORT_CNT_SFT 16
++#define CMD52_RD_ABORT_CNT_HI 19
++#define CMD52_RD_ABORT_CNT_SZ 4
++#define CMD52_WR_ABORT_CNT_MSK 0x00f00000
++#define CMD52_WR_ABORT_CNT_I_MSK 0xff0fffff
++#define CMD52_WR_ABORT_CNT_SFT 20
++#define CMD52_WR_ABORT_CNT_HI 23
++#define CMD52_WR_ABORT_CNT_SZ 4
++#define SDIO_FIFO_WR_PTR_REG_MSK 0x000000ff
++#define SDIO_FIFO_WR_PTR_REG_I_MSK 0xffffff00
++#define SDIO_FIFO_WR_PTR_REG_SFT 0
++#define SDIO_FIFO_WR_PTR_REG_HI 7
++#define SDIO_FIFO_WR_PTR_REG_SZ 8
++#define SDIO_FIFO_RD_PTR_REG_MSK 0x0000ff00
++#define SDIO_FIFO_RD_PTR_REG_I_MSK 0xffff00ff
++#define SDIO_FIFO_RD_PTR_REG_SFT 8
++#define SDIO_FIFO_RD_PTR_REG_HI 15
++#define SDIO_FIFO_RD_PTR_REG_SZ 8
++#define SDIO_READ_DATA_CTRL_MSK 0x00010000
++#define SDIO_READ_DATA_CTRL_I_MSK 0xfffeffff
++#define SDIO_READ_DATA_CTRL_SFT 16
++#define SDIO_READ_DATA_CTRL_HI 16
++#define SDIO_READ_DATA_CTRL_SZ 1
++#define TX_SIZE_BEFORE_SHIFT_MSK 0x000000ff
++#define TX_SIZE_BEFORE_SHIFT_I_MSK 0xffffff00
++#define TX_SIZE_BEFORE_SHIFT_SFT 0
++#define TX_SIZE_BEFORE_SHIFT_HI 7
++#define TX_SIZE_BEFORE_SHIFT_SZ 8
++#define TX_SIZE_SHIFT_BITS_MSK 0x00000700
++#define TX_SIZE_SHIFT_BITS_I_MSK 0xfffff8ff
++#define TX_SIZE_SHIFT_BITS_SFT 8
++#define TX_SIZE_SHIFT_BITS_HI 10
++#define TX_SIZE_SHIFT_BITS_SZ 3
++#define SDIO_TX_ALLOC_STATE_MSK 0x00001000
++#define SDIO_TX_ALLOC_STATE_I_MSK 0xffffefff
++#define SDIO_TX_ALLOC_STATE_SFT 12
++#define SDIO_TX_ALLOC_STATE_HI 12
++#define SDIO_TX_ALLOC_STATE_SZ 1
++#define ALLOCATE_STATUS2_MSK 0x00010000
++#define ALLOCATE_STATUS2_I_MSK 0xfffeffff
++#define ALLOCATE_STATUS2_SFT 16
++#define ALLOCATE_STATUS2_HI 16
++#define ALLOCATE_STATUS2_SZ 1
++#define NO_ALLOCATE_SEND_ERROR_MSK 0x00020000
++#define NO_ALLOCATE_SEND_ERROR_I_MSK 0xfffdffff
++#define NO_ALLOCATE_SEND_ERROR_SFT 17
++#define NO_ALLOCATE_SEND_ERROR_HI 17
++#define NO_ALLOCATE_SEND_ERROR_SZ 1
++#define DOUBLE_ALLOCATE_ERROR_MSK 0x00040000
++#define DOUBLE_ALLOCATE_ERROR_I_MSK 0xfffbffff
++#define DOUBLE_ALLOCATE_ERROR_SFT 18
++#define DOUBLE_ALLOCATE_ERROR_HI 18
++#define DOUBLE_ALLOCATE_ERROR_SZ 1
++#define TX_DONE_STATUS_MSK 0x00080000
++#define TX_DONE_STATUS_I_MSK 0xfff7ffff
++#define TX_DONE_STATUS_SFT 19
++#define TX_DONE_STATUS_HI 19
++#define TX_DONE_STATUS_SZ 1
++#define AHB_HANG2_MSK 0x00100000
++#define AHB_HANG2_I_MSK 0xffefffff
++#define AHB_HANG2_SFT 20
++#define AHB_HANG2_HI 20
++#define AHB_HANG2_SZ 1
++#define HCI_TRX_FINISH2_MSK 0x00200000
++#define HCI_TRX_FINISH2_I_MSK 0xffdfffff
++#define HCI_TRX_FINISH2_SFT 21
++#define HCI_TRX_FINISH2_HI 21
++#define HCI_TRX_FINISH2_SZ 1
++#define INTR_RX_MSK 0x00400000
++#define INTR_RX_I_MSK 0xffbfffff
++#define INTR_RX_SFT 22
++#define INTR_RX_HI 22
++#define INTR_RX_SZ 1
++#define HCI_INPUT_QUEUE_FULL_MSK 0x00800000
++#define HCI_INPUT_QUEUE_FULL_I_MSK 0xff7fffff
++#define HCI_INPUT_QUEUE_FULL_SFT 23
++#define HCI_INPUT_QUEUE_FULL_HI 23
++#define HCI_INPUT_QUEUE_FULL_SZ 1
++#define ALLOCATESTATUS_MSK 0x00000001
++#define ALLOCATESTATUS_I_MSK 0xfffffffe
++#define ALLOCATESTATUS_SFT 0
++#define ALLOCATESTATUS_HI 0
++#define ALLOCATESTATUS_SZ 1
++#define HCI_TRX_FINISH3_MSK 0x00000002
++#define HCI_TRX_FINISH3_I_MSK 0xfffffffd
++#define HCI_TRX_FINISH3_SFT 1
++#define HCI_TRX_FINISH3_HI 1
++#define HCI_TRX_FINISH3_SZ 1
++#define HCI_IN_QUE_EMPTY2_MSK 0x00000004
++#define HCI_IN_QUE_EMPTY2_I_MSK 0xfffffffb
++#define HCI_IN_QUE_EMPTY2_SFT 2
++#define HCI_IN_QUE_EMPTY2_HI 2
++#define HCI_IN_QUE_EMPTY2_SZ 1
++#define MTX_MNG_UPTHOLD_INT_MSK 0x00000008
++#define MTX_MNG_UPTHOLD_INT_I_MSK 0xfffffff7
++#define MTX_MNG_UPTHOLD_INT_SFT 3
++#define MTX_MNG_UPTHOLD_INT_HI 3
++#define MTX_MNG_UPTHOLD_INT_SZ 1
++#define EDCA0_UPTHOLD_INT_MSK 0x00000010
++#define EDCA0_UPTHOLD_INT_I_MSK 0xffffffef
++#define EDCA0_UPTHOLD_INT_SFT 4
++#define EDCA0_UPTHOLD_INT_HI 4
++#define EDCA0_UPTHOLD_INT_SZ 1
++#define EDCA1_UPTHOLD_INT_MSK 0x00000020
++#define EDCA1_UPTHOLD_INT_I_MSK 0xffffffdf
++#define EDCA1_UPTHOLD_INT_SFT 5
++#define EDCA1_UPTHOLD_INT_HI 5
++#define EDCA1_UPTHOLD_INT_SZ 1
++#define EDCA2_UPTHOLD_INT_MSK 0x00000040
++#define EDCA2_UPTHOLD_INT_I_MSK 0xffffffbf
++#define EDCA2_UPTHOLD_INT_SFT 6
++#define EDCA2_UPTHOLD_INT_HI 6
++#define EDCA2_UPTHOLD_INT_SZ 1
++#define EDCA3_UPTHOLD_INT_MSK 0x00000080
++#define EDCA3_UPTHOLD_INT_I_MSK 0xffffff7f
++#define EDCA3_UPTHOLD_INT_SFT 7
++#define EDCA3_UPTHOLD_INT_HI 7
++#define EDCA3_UPTHOLD_INT_SZ 1
++#define TX_PAGE_REMAIN2_MSK 0x0000ff00
++#define TX_PAGE_REMAIN2_I_MSK 0xffff00ff
++#define TX_PAGE_REMAIN2_SFT 8
++#define TX_PAGE_REMAIN2_HI 15
++#define TX_PAGE_REMAIN2_SZ 8
++#define TX_ID_REMAIN3_MSK 0x007f0000
++#define TX_ID_REMAIN3_I_MSK 0xff80ffff
++#define TX_ID_REMAIN3_SFT 16
++#define TX_ID_REMAIN3_HI 22
++#define TX_ID_REMAIN3_SZ 7
++#define HCI_OUTPUT_FF_CNT_0_MSK 0x00800000
++#define HCI_OUTPUT_FF_CNT_0_I_MSK 0xff7fffff
++#define HCI_OUTPUT_FF_CNT_0_SFT 23
++#define HCI_OUTPUT_FF_CNT_0_HI 23
++#define HCI_OUTPUT_FF_CNT_0_SZ 1
++#define HCI_OUTPUT_FF_CNT2_MSK 0x0f000000
++#define HCI_OUTPUT_FF_CNT2_I_MSK 0xf0ffffff
++#define HCI_OUTPUT_FF_CNT2_SFT 24
++#define HCI_OUTPUT_FF_CNT2_HI 27
++#define HCI_OUTPUT_FF_CNT2_SZ 4
++#define HCI_INPUT_FF_CNT2_MSK 0xf0000000
++#define HCI_INPUT_FF_CNT2_I_MSK 0x0fffffff
++#define HCI_INPUT_FF_CNT2_SFT 28
++#define HCI_INPUT_FF_CNT2_HI 31
++#define HCI_INPUT_FF_CNT2_SZ 4
++#define F1_BLOCK_SIZE_0_REG_MSK 0x00000fff
++#define F1_BLOCK_SIZE_0_REG_I_MSK 0xfffff000
++#define F1_BLOCK_SIZE_0_REG_SFT 0
++#define F1_BLOCK_SIZE_0_REG_HI 11
++#define F1_BLOCK_SIZE_0_REG_SZ 12
++#define START_BYTE_VALUE2_MSK 0x000000ff
++#define START_BYTE_VALUE2_I_MSK 0xffffff00
++#define START_BYTE_VALUE2_SFT 0
++#define START_BYTE_VALUE2_HI 7
++#define START_BYTE_VALUE2_SZ 8
++#define COMMAND_COUNTER_MSK 0x0000ff00
++#define COMMAND_COUNTER_I_MSK 0xffff00ff
++#define COMMAND_COUNTER_SFT 8
++#define COMMAND_COUNTER_HI 15
++#define COMMAND_COUNTER_SZ 8
++#define CMD_LOG_PART1_MSK 0xffff0000
++#define CMD_LOG_PART1_I_MSK 0x0000ffff
++#define CMD_LOG_PART1_SFT 16
++#define CMD_LOG_PART1_HI 31
++#define CMD_LOG_PART1_SZ 16
++#define CMD_LOG_PART2_MSK 0x00ffffff
++#define CMD_LOG_PART2_I_MSK 0xff000000
++#define CMD_LOG_PART2_SFT 0
++#define CMD_LOG_PART2_HI 23
++#define CMD_LOG_PART2_SZ 24
++#define END_BYTE_VALUE2_MSK 0xff000000
++#define END_BYTE_VALUE2_I_MSK 0x00ffffff
++#define END_BYTE_VALUE2_SFT 24
++#define END_BYTE_VALUE2_HI 31
++#define END_BYTE_VALUE2_SZ 8
++#define RX_PACKET_LENGTH3_MSK 0x0000ffff
++#define RX_PACKET_LENGTH3_I_MSK 0xffff0000
++#define RX_PACKET_LENGTH3_SFT 0
++#define RX_PACKET_LENGTH3_HI 15
++#define RX_PACKET_LENGTH3_SZ 16
++#define RX_INT3_MSK 0x00010000
++#define RX_INT3_I_MSK 0xfffeffff
++#define RX_INT3_SFT 16
++#define RX_INT3_HI 16
++#define RX_INT3_SZ 1
++#define TX_ID_REMAIN2_MSK 0x00fe0000
++#define TX_ID_REMAIN2_I_MSK 0xff01ffff
++#define TX_ID_REMAIN2_SFT 17
++#define TX_ID_REMAIN2_HI 23
++#define TX_ID_REMAIN2_SZ 7
++#define TX_PAGE_REMAIN3_MSK 0xff000000
++#define TX_PAGE_REMAIN3_I_MSK 0x00ffffff
++#define TX_PAGE_REMAIN3_SFT 24
++#define TX_PAGE_REMAIN3_HI 31
++#define TX_PAGE_REMAIN3_SZ 8
++#define CCCR_00H_REG_MSK 0x000000ff
++#define CCCR_00H_REG_I_MSK 0xffffff00
++#define CCCR_00H_REG_SFT 0
++#define CCCR_00H_REG_HI 7
++#define CCCR_00H_REG_SZ 8
++#define CCCR_02H_REG_MSK 0x00ff0000
++#define CCCR_02H_REG_I_MSK 0xff00ffff
++#define CCCR_02H_REG_SFT 16
++#define CCCR_02H_REG_HI 23
++#define CCCR_02H_REG_SZ 8
++#define CCCR_03H_REG_MSK 0xff000000
++#define CCCR_03H_REG_I_MSK 0x00ffffff
++#define CCCR_03H_REG_SFT 24
++#define CCCR_03H_REG_HI 31
++#define CCCR_03H_REG_SZ 8
++#define CCCR_04H_REG_MSK 0x000000ff
++#define CCCR_04H_REG_I_MSK 0xffffff00
++#define CCCR_04H_REG_SFT 0
++#define CCCR_04H_REG_HI 7
++#define CCCR_04H_REG_SZ 8
++#define CCCR_05H_REG_MSK 0x0000ff00
++#define CCCR_05H_REG_I_MSK 0xffff00ff
++#define CCCR_05H_REG_SFT 8
++#define CCCR_05H_REG_HI 15
++#define CCCR_05H_REG_SZ 8
++#define CCCR_06H_REG_MSK 0x000f0000
++#define CCCR_06H_REG_I_MSK 0xfff0ffff
++#define CCCR_06H_REG_SFT 16
++#define CCCR_06H_REG_HI 19
++#define CCCR_06H_REG_SZ 4
++#define CCCR_07H_REG_MSK 0xff000000
++#define CCCR_07H_REG_I_MSK 0x00ffffff
++#define CCCR_07H_REG_SFT 24
++#define CCCR_07H_REG_HI 31
++#define CCCR_07H_REG_SZ 8
++#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001
++#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe
++#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0
++#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0
++#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1
++#define SUPPORT_READ_WAIT_MSK 0x00000004
++#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb
++#define SUPPORT_READ_WAIT_SFT 2
++#define SUPPORT_READ_WAIT_HI 2
++#define SUPPORT_READ_WAIT_SZ 1
++#define SUPPORT_BUS_CONTROL_MSK 0x00000008
++#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7
++#define SUPPORT_BUS_CONTROL_SFT 3
++#define SUPPORT_BUS_CONTROL_HI 3
++#define SUPPORT_BUS_CONTROL_SZ 1
++#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010
++#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef
++#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4
++#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4
++#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1
++#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020
++#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf
++#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5
++#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5
++#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1
++#define LOW_SPEED_CARD_MSK 0x00000040
++#define LOW_SPEED_CARD_I_MSK 0xffffffbf
++#define LOW_SPEED_CARD_SFT 6
++#define LOW_SPEED_CARD_HI 6
++#define LOW_SPEED_CARD_SZ 1
++#define LOW_SPEED_CARD_4BIT_MSK 0x00000080
++#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f
++#define LOW_SPEED_CARD_4BIT_SFT 7
++#define LOW_SPEED_CARD_4BIT_HI 7
++#define LOW_SPEED_CARD_4BIT_SZ 1
++#define COMMON_CIS_PONTER_MSK 0x01ffff00
++#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff
++#define COMMON_CIS_PONTER_SFT 8
++#define COMMON_CIS_PONTER_HI 24
++#define COMMON_CIS_PONTER_SZ 17
++#define SUPPORT_HIGH_SPEED_MSK 0x01000000
++#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff
++#define SUPPORT_HIGH_SPEED_SFT 24
++#define SUPPORT_HIGH_SPEED_HI 24
++#define SUPPORT_HIGH_SPEED_SZ 1
++#define BSS_MSK 0x0e000000
++#define BSS_I_MSK 0xf1ffffff
++#define BSS_SFT 25
++#define BSS_HI 27
++#define BSS_SZ 3
++#define FBR_100H_REG_MSK 0x0000000f
++#define FBR_100H_REG_I_MSK 0xfffffff0
++#define FBR_100H_REG_SFT 0
++#define FBR_100H_REG_HI 3
++#define FBR_100H_REG_SZ 4
++#define CSASUPPORT_MSK 0x00000040
++#define CSASUPPORT_I_MSK 0xffffffbf
++#define CSASUPPORT_SFT 6
++#define CSASUPPORT_HI 6
++#define CSASUPPORT_SZ 1
++#define ENABLECSA_MSK 0x00000080
++#define ENABLECSA_I_MSK 0xffffff7f
++#define ENABLECSA_SFT 7
++#define ENABLECSA_HI 7
++#define ENABLECSA_SZ 1
++#define FBR_101H_REG_MSK 0x0000ff00
++#define FBR_101H_REG_I_MSK 0xffff00ff
++#define FBR_101H_REG_SFT 8
++#define FBR_101H_REG_HI 15
++#define FBR_101H_REG_SZ 8
++#define FBR_109H_REG_MSK 0x01ffff00
++#define FBR_109H_REG_I_MSK 0xfe0000ff
++#define FBR_109H_REG_SFT 8
++#define FBR_109H_REG_HI 24
++#define FBR_109H_REG_SZ 17
++#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_31_0_SFT 0
++#define F0_CIS_CONTENT_REG_31_0_HI 31
++#define F0_CIS_CONTENT_REG_31_0_SZ 32
++#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_63_32_SFT 0
++#define F0_CIS_CONTENT_REG_63_32_HI 31
++#define F0_CIS_CONTENT_REG_63_32_SZ 32
++#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_95_64_SFT 0
++#define F0_CIS_CONTENT_REG_95_64_HI 31
++#define F0_CIS_CONTENT_REG_95_64_SZ 32
++#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_127_96_SFT 0
++#define F0_CIS_CONTENT_REG_127_96_HI 31
++#define F0_CIS_CONTENT_REG_127_96_SZ 32
++#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_159_128_SFT 0
++#define F0_CIS_CONTENT_REG_159_128_HI 31
++#define F0_CIS_CONTENT_REG_159_128_SZ 32
++#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_191_160_SFT 0
++#define F0_CIS_CONTENT_REG_191_160_HI 31
++#define F0_CIS_CONTENT_REG_191_160_SZ 32
++#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_223_192_SFT 0
++#define F0_CIS_CONTENT_REG_223_192_HI 31
++#define F0_CIS_CONTENT_REG_223_192_SZ 32
++#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_255_224_SFT 0
++#define F0_CIS_CONTENT_REG_255_224_HI 31
++#define F0_CIS_CONTENT_REG_255_224_SZ 32
++#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_287_256_SFT 0
++#define F0_CIS_CONTENT_REG_287_256_HI 31
++#define F0_CIS_CONTENT_REG_287_256_SZ 32
++#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_319_288_SFT 0
++#define F0_CIS_CONTENT_REG_319_288_HI 31
++#define F0_CIS_CONTENT_REG_319_288_SZ 32
++#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_351_320_SFT 0
++#define F0_CIS_CONTENT_REG_351_320_HI 31
++#define F0_CIS_CONTENT_REG_351_320_SZ 32
++#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_383_352_SFT 0
++#define F0_CIS_CONTENT_REG_383_352_HI 31
++#define F0_CIS_CONTENT_REG_383_352_SZ 32
++#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_415_384_SFT 0
++#define F0_CIS_CONTENT_REG_415_384_HI 31
++#define F0_CIS_CONTENT_REG_415_384_SZ 32
++#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_447_416_SFT 0
++#define F0_CIS_CONTENT_REG_447_416_HI 31
++#define F0_CIS_CONTENT_REG_447_416_SZ 32
++#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_479_448_SFT 0
++#define F0_CIS_CONTENT_REG_479_448_HI 31
++#define F0_CIS_CONTENT_REG_479_448_SZ 32
++#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_511_480_SFT 0
++#define F0_CIS_CONTENT_REG_511_480_HI 31
++#define F0_CIS_CONTENT_REG_511_480_SZ 32
++#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_31_0_SFT 0
++#define F1_CIS_CONTENT_REG_31_0_HI 31
++#define F1_CIS_CONTENT_REG_31_0_SZ 32
++#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_63_32_SFT 0
++#define F1_CIS_CONTENT_REG_63_32_HI 31
++#define F1_CIS_CONTENT_REG_63_32_SZ 32
++#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_95_64_SFT 0
++#define F1_CIS_CONTENT_REG_95_64_HI 31
++#define F1_CIS_CONTENT_REG_95_64_SZ 32
++#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_127_96_SFT 0
++#define F1_CIS_CONTENT_REG_127_96_HI 31
++#define F1_CIS_CONTENT_REG_127_96_SZ 32
++#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_159_128_SFT 0
++#define F1_CIS_CONTENT_REG_159_128_HI 31
++#define F1_CIS_CONTENT_REG_159_128_SZ 32
++#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_191_160_SFT 0
++#define F1_CIS_CONTENT_REG_191_160_HI 31
++#define F1_CIS_CONTENT_REG_191_160_SZ 32
++#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_223_192_SFT 0
++#define F1_CIS_CONTENT_REG_223_192_HI 31
++#define F1_CIS_CONTENT_REG_223_192_SZ 32
++#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_255_224_SFT 0
++#define F1_CIS_CONTENT_REG_255_224_HI 31
++#define F1_CIS_CONTENT_REG_255_224_SZ 32
++#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_287_256_SFT 0
++#define F1_CIS_CONTENT_REG_287_256_HI 31
++#define F1_CIS_CONTENT_REG_287_256_SZ 32
++#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_319_288_SFT 0
++#define F1_CIS_CONTENT_REG_319_288_HI 31
++#define F1_CIS_CONTENT_REG_319_288_SZ 32
++#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_351_320_SFT 0
++#define F1_CIS_CONTENT_REG_351_320_HI 31
++#define F1_CIS_CONTENT_REG_351_320_SZ 32
++#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_383_352_SFT 0
++#define F1_CIS_CONTENT_REG_383_352_HI 31
++#define F1_CIS_CONTENT_REG_383_352_SZ 32
++#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_415_384_SFT 0
++#define F1_CIS_CONTENT_REG_415_384_HI 31
++#define F1_CIS_CONTENT_REG_415_384_SZ 32
++#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_447_416_SFT 0
++#define F1_CIS_CONTENT_REG_447_416_HI 31
++#define F1_CIS_CONTENT_REG_447_416_SZ 32
++#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_479_448_SFT 0
++#define F1_CIS_CONTENT_REG_479_448_HI 31
++#define F1_CIS_CONTENT_REG_479_448_SZ 32
++#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_511_480_SFT 0
++#define F1_CIS_CONTENT_REG_511_480_HI 31
++#define F1_CIS_CONTENT_REG_511_480_SZ 32
++#define SPI_MODE_MSK 0xffffffff
++#define SPI_MODE_I_MSK 0x00000000
++#define SPI_MODE_SFT 0
++#define SPI_MODE_HI 31
++#define SPI_MODE_SZ 32
++#define RX_QUOTA_MSK 0x0000ffff
++#define RX_QUOTA_I_MSK 0xffff0000
++#define RX_QUOTA_SFT 0
++#define RX_QUOTA_HI 15
++#define RX_QUOTA_SZ 16
++#define CONDI_NUM_MSK 0x000000ff
++#define CONDI_NUM_I_MSK 0xffffff00
++#define CONDI_NUM_SFT 0
++#define CONDI_NUM_HI 7
++#define CONDI_NUM_SZ 8
++#define HOST_PATH_MSK 0x00000001
++#define HOST_PATH_I_MSK 0xfffffffe
++#define HOST_PATH_SFT 0
++#define HOST_PATH_HI 0
++#define HOST_PATH_SZ 1
++#define TX_SEG_MSK 0xffffffff
++#define TX_SEG_I_MSK 0x00000000
++#define TX_SEG_SFT 0
++#define TX_SEG_HI 31
++#define TX_SEG_SZ 32
++#define BRST_MODE_MSK 0x00000001
++#define BRST_MODE_I_MSK 0xfffffffe
++#define BRST_MODE_SFT 0
++#define BRST_MODE_HI 0
++#define BRST_MODE_SZ 1
++#define CLK_WIDTH_MSK 0x0000ffff
++#define CLK_WIDTH_I_MSK 0xffff0000
++#define CLK_WIDTH_SFT 0
++#define CLK_WIDTH_HI 15
++#define CLK_WIDTH_SZ 16
++#define CSN_INTER_MSK 0xffff0000
++#define CSN_INTER_I_MSK 0x0000ffff
++#define CSN_INTER_SFT 16
++#define CSN_INTER_HI 31
++#define CSN_INTER_SZ 16
++#define BACK_DLY_MSK 0x0000ffff
++#define BACK_DLY_I_MSK 0xffff0000
++#define BACK_DLY_SFT 0
++#define BACK_DLY_HI 15
++#define BACK_DLY_SZ 16
++#define FRONT_DLY_MSK 0xffff0000
++#define FRONT_DLY_I_MSK 0x0000ffff
++#define FRONT_DLY_SFT 16
++#define FRONT_DLY_HI 31
++#define FRONT_DLY_SZ 16
++#define RX_FIFO_FAIL_MSK 0x00000002
++#define RX_FIFO_FAIL_I_MSK 0xfffffffd
++#define RX_FIFO_FAIL_SFT 1
++#define RX_FIFO_FAIL_HI 1
++#define RX_FIFO_FAIL_SZ 1
++#define RX_HOST_FAIL_MSK 0x00000004
++#define RX_HOST_FAIL_I_MSK 0xfffffffb
++#define RX_HOST_FAIL_SFT 2
++#define RX_HOST_FAIL_HI 2
++#define RX_HOST_FAIL_SZ 1
++#define TX_FIFO_FAIL_MSK 0x00000008
++#define TX_FIFO_FAIL_I_MSK 0xfffffff7
++#define TX_FIFO_FAIL_SFT 3
++#define TX_FIFO_FAIL_HI 3
++#define TX_FIFO_FAIL_SZ 1
++#define TX_HOST_FAIL_MSK 0x00000010
++#define TX_HOST_FAIL_I_MSK 0xffffffef
++#define TX_HOST_FAIL_SFT 4
++#define TX_HOST_FAIL_HI 4
++#define TX_HOST_FAIL_SZ 1
++#define SPI_DOUBLE_ALLOC_MSK 0x00000020
++#define SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
++#define SPI_DOUBLE_ALLOC_SFT 5
++#define SPI_DOUBLE_ALLOC_HI 5
++#define SPI_DOUBLE_ALLOC_SZ 1
++#define SPI_TX_NO_ALLOC_MSK 0x00000040
++#define SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
++#define SPI_TX_NO_ALLOC_SFT 6
++#define SPI_TX_NO_ALLOC_HI 6
++#define SPI_TX_NO_ALLOC_SZ 1
++#define RDATA_RDY_MSK 0x00000080
++#define RDATA_RDY_I_MSK 0xffffff7f
++#define RDATA_RDY_SFT 7
++#define RDATA_RDY_HI 7
++#define RDATA_RDY_SZ 1
++#define SPI_ALLOC_STATUS_MSK 0x00000100
++#define SPI_ALLOC_STATUS_I_MSK 0xfffffeff
++#define SPI_ALLOC_STATUS_SFT 8
++#define SPI_ALLOC_STATUS_HI 8
++#define SPI_ALLOC_STATUS_SZ 1
++#define SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
++#define SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
++#define SPI_DBG_WR_FIFO_FULL_SFT 9
++#define SPI_DBG_WR_FIFO_FULL_HI 9
++#define SPI_DBG_WR_FIFO_FULL_SZ 1
++#define RX_LEN_MSK 0xffff0000
++#define RX_LEN_I_MSK 0x0000ffff
++#define RX_LEN_SFT 16
++#define RX_LEN_HI 31
++#define RX_LEN_SZ 16
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
++#define SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
++#define SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
++#define SPI_HOST_TX_ALLOC_PKBUF_SFT 8
++#define SPI_HOST_TX_ALLOC_PKBUF_HI 8
++#define SPI_HOST_TX_ALLOC_PKBUF_SZ 1
++#define SPI_TX_ALLOC_SIZE_MSK 0x000000ff
++#define SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
++#define SPI_TX_ALLOC_SIZE_SFT 0
++#define SPI_TX_ALLOC_SIZE_HI 7
++#define SPI_TX_ALLOC_SIZE_SZ 8
++#define RD_DAT_CNT_MSK 0x0000ffff
++#define RD_DAT_CNT_I_MSK 0xffff0000
++#define RD_DAT_CNT_SFT 0
++#define RD_DAT_CNT_HI 15
++#define RD_DAT_CNT_SZ 16
++#define RD_STS_CNT_MSK 0xffff0000
++#define RD_STS_CNT_I_MSK 0x0000ffff
++#define RD_STS_CNT_SFT 16
++#define RD_STS_CNT_HI 31
++#define RD_STS_CNT_SZ 16
++#define JUDGE_CNT_MSK 0x0000ffff
++#define JUDGE_CNT_I_MSK 0xffff0000
++#define JUDGE_CNT_SFT 0
++#define JUDGE_CNT_HI 15
++#define JUDGE_CNT_SZ 16
++#define RD_STS_CNT_CLR_MSK 0x00010000
++#define RD_STS_CNT_CLR_I_MSK 0xfffeffff
++#define RD_STS_CNT_CLR_SFT 16
++#define RD_STS_CNT_CLR_HI 16
++#define RD_STS_CNT_CLR_SZ 1
++#define RD_DAT_CNT_CLR_MSK 0x00020000
++#define RD_DAT_CNT_CLR_I_MSK 0xfffdffff
++#define RD_DAT_CNT_CLR_SFT 17
++#define RD_DAT_CNT_CLR_HI 17
++#define RD_DAT_CNT_CLR_SZ 1
++#define JUDGE_CNT_CLR_MSK 0x00040000
++#define JUDGE_CNT_CLR_I_MSK 0xfffbffff
++#define JUDGE_CNT_CLR_SFT 18
++#define JUDGE_CNT_CLR_HI 18
++#define JUDGE_CNT_CLR_SZ 1
++#define TX_DONE_CNT_MSK 0x0000ffff
++#define TX_DONE_CNT_I_MSK 0xffff0000
++#define TX_DONE_CNT_SFT 0
++#define TX_DONE_CNT_HI 15
++#define TX_DONE_CNT_SZ 16
++#define TX_DISCARD_CNT_MSK 0xffff0000
++#define TX_DISCARD_CNT_I_MSK 0x0000ffff
++#define TX_DISCARD_CNT_SFT 16
++#define TX_DISCARD_CNT_HI 31
++#define TX_DISCARD_CNT_SZ 16
++#define TX_SET_CNT_MSK 0x0000ffff
++#define TX_SET_CNT_I_MSK 0xffff0000
++#define TX_SET_CNT_SFT 0
++#define TX_SET_CNT_HI 15
++#define TX_SET_CNT_SZ 16
++#define TX_DISCARD_CNT_CLR_MSK 0x00010000
++#define TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
++#define TX_DISCARD_CNT_CLR_SFT 16
++#define TX_DISCARD_CNT_CLR_HI 16
++#define TX_DISCARD_CNT_CLR_SZ 1
++#define TX_DONE_CNT_CLR_MSK 0x00020000
++#define TX_DONE_CNT_CLR_I_MSK 0xfffdffff
++#define TX_DONE_CNT_CLR_SFT 17
++#define TX_DONE_CNT_CLR_HI 17
++#define TX_DONE_CNT_CLR_SZ 1
++#define TX_SET_CNT_CLR_MSK 0x00040000
++#define TX_SET_CNT_CLR_I_MSK 0xfffbffff
++#define TX_SET_CNT_CLR_SFT 18
++#define TX_SET_CNT_CLR_HI 18
++#define TX_SET_CNT_CLR_SZ 1
++#define DAT_MODE_OFF_MSK 0x00080000
++#define DAT_MODE_OFF_I_MSK 0xfff7ffff
++#define DAT_MODE_OFF_SFT 19
++#define DAT_MODE_OFF_HI 19
++#define DAT_MODE_OFF_SZ 1
++#define TX_FIFO_RESIDUE_MSK 0x00700000
++#define TX_FIFO_RESIDUE_I_MSK 0xff8fffff
++#define TX_FIFO_RESIDUE_SFT 20
++#define TX_FIFO_RESIDUE_HI 22
++#define TX_FIFO_RESIDUE_SZ 3
++#define RX_FIFO_RESIDUE_MSK 0x07000000
++#define RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
++#define RX_FIFO_RESIDUE_SFT 24
++#define RX_FIFO_RESIDUE_HI 26
++#define RX_FIFO_RESIDUE_SZ 3
++#define RX_RDY_MSK 0x00000001
++#define RX_RDY_I_MSK 0xfffffffe
++#define RX_RDY_SFT 0
++#define RX_RDY_HI 0
++#define RX_RDY_SZ 1
++#define SDIO_SYS_INT_MSK 0x00000004
++#define SDIO_SYS_INT_I_MSK 0xfffffffb
++#define SDIO_SYS_INT_SFT 2
++#define SDIO_SYS_INT_HI 2
++#define SDIO_SYS_INT_SZ 1
++#define EDCA0_LOWTHOLD_INT_MSK 0x00000008
++#define EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
++#define EDCA0_LOWTHOLD_INT_SFT 3
++#define EDCA0_LOWTHOLD_INT_HI 3
++#define EDCA0_LOWTHOLD_INT_SZ 1
++#define EDCA1_LOWTHOLD_INT_MSK 0x00000010
++#define EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
++#define EDCA1_LOWTHOLD_INT_SFT 4
++#define EDCA1_LOWTHOLD_INT_HI 4
++#define EDCA1_LOWTHOLD_INT_SZ 1
++#define EDCA2_LOWTHOLD_INT_MSK 0x00000020
++#define EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
++#define EDCA2_LOWTHOLD_INT_SFT 5
++#define EDCA2_LOWTHOLD_INT_HI 5
++#define EDCA2_LOWTHOLD_INT_SZ 1
++#define EDCA3_LOWTHOLD_INT_MSK 0x00000040
++#define EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
++#define EDCA3_LOWTHOLD_INT_SFT 6
++#define EDCA3_LOWTHOLD_INT_HI 6
++#define EDCA3_LOWTHOLD_INT_SZ 1
++#define TX_LIMIT_INT_IN_MSK 0x00000080
++#define TX_LIMIT_INT_IN_I_MSK 0xffffff7f
++#define TX_LIMIT_INT_IN_SFT 7
++#define TX_LIMIT_INT_IN_HI 7
++#define TX_LIMIT_INT_IN_SZ 1
++#define SPI_FN1_MSK 0x00007f00
++#define SPI_FN1_I_MSK 0xffff80ff
++#define SPI_FN1_SFT 8
++#define SPI_FN1_HI 14
++#define SPI_FN1_SZ 7
++#define SPI_CLK_EN_INT_MSK 0x00008000
++#define SPI_CLK_EN_INT_I_MSK 0xffff7fff
++#define SPI_CLK_EN_INT_SFT 15
++#define SPI_CLK_EN_INT_HI 15
++#define SPI_CLK_EN_INT_SZ 1
++#define SPI_HOST_MASK_MSK 0x00ff0000
++#define SPI_HOST_MASK_I_MSK 0xff00ffff
++#define SPI_HOST_MASK_SFT 16
++#define SPI_HOST_MASK_HI 23
++#define SPI_HOST_MASK_SZ 8
++#define I2CM_INT_WDONE_MSK 0x00000001
++#define I2CM_INT_WDONE_I_MSK 0xfffffffe
++#define I2CM_INT_WDONE_SFT 0
++#define I2CM_INT_WDONE_HI 0
++#define I2CM_INT_WDONE_SZ 1
++#define I2CM_INT_RDONE_MSK 0x00000002
++#define I2CM_INT_RDONE_I_MSK 0xfffffffd
++#define I2CM_INT_RDONE_SFT 1
++#define I2CM_INT_RDONE_HI 1
++#define I2CM_INT_RDONE_SZ 1
++#define I2CM_IDLE_MSK 0x00000004
++#define I2CM_IDLE_I_MSK 0xfffffffb
++#define I2CM_IDLE_SFT 2
++#define I2CM_IDLE_HI 2
++#define I2CM_IDLE_SZ 1
++#define I2CM_INT_MISMATCH_MSK 0x00000008
++#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7
++#define I2CM_INT_MISMATCH_SFT 3
++#define I2CM_INT_MISMATCH_HI 3
++#define I2CM_INT_MISMATCH_SZ 1
++#define I2CM_PSCL_MSK 0x00003ff0
++#define I2CM_PSCL_I_MSK 0xffffc00f
++#define I2CM_PSCL_SFT 4
++#define I2CM_PSCL_HI 13
++#define I2CM_PSCL_SZ 10
++#define I2CM_MANUAL_MODE_MSK 0x00010000
++#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff
++#define I2CM_MANUAL_MODE_SFT 16
++#define I2CM_MANUAL_MODE_HI 16
++#define I2CM_MANUAL_MODE_SZ 1
++#define I2CM_INT_WDATA_NEED_MSK 0x00020000
++#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff
++#define I2CM_INT_WDATA_NEED_SFT 17
++#define I2CM_INT_WDATA_NEED_HI 17
++#define I2CM_INT_WDATA_NEED_SZ 1
++#define I2CM_INT_RDATA_NEED_MSK 0x00040000
++#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff
++#define I2CM_INT_RDATA_NEED_SFT 18
++#define I2CM_INT_RDATA_NEED_HI 18
++#define I2CM_INT_RDATA_NEED_SZ 1
++#define I2CM_DEV_A_MSK 0x000003ff
++#define I2CM_DEV_A_I_MSK 0xfffffc00
++#define I2CM_DEV_A_SFT 0
++#define I2CM_DEV_A_HI 9
++#define I2CM_DEV_A_SZ 10
++#define I2CM_DEV_A10B_MSK 0x00004000
++#define I2CM_DEV_A10B_I_MSK 0xffffbfff
++#define I2CM_DEV_A10B_SFT 14
++#define I2CM_DEV_A10B_HI 14
++#define I2CM_DEV_A10B_SZ 1
++#define I2CM_RX_MSK 0x00008000
++#define I2CM_RX_I_MSK 0xffff7fff
++#define I2CM_RX_SFT 15
++#define I2CM_RX_HI 15
++#define I2CM_RX_SZ 1
++#define I2CM_LEN_MSK 0x0000ffff
++#define I2CM_LEN_I_MSK 0xffff0000
++#define I2CM_LEN_SFT 0
++#define I2CM_LEN_HI 15
++#define I2CM_LEN_SZ 16
++#define I2CM_T_LEFT_MSK 0x00070000
++#define I2CM_T_LEFT_I_MSK 0xfff8ffff
++#define I2CM_T_LEFT_SFT 16
++#define I2CM_T_LEFT_HI 18
++#define I2CM_T_LEFT_SZ 3
++#define I2CM_R_GET_MSK 0x07000000
++#define I2CM_R_GET_I_MSK 0xf8ffffff
++#define I2CM_R_GET_SFT 24
++#define I2CM_R_GET_HI 26
++#define I2CM_R_GET_SZ 3
++#define I2CM_WDAT_MSK 0xffffffff
++#define I2CM_WDAT_I_MSK 0x00000000
++#define I2CM_WDAT_SFT 0
++#define I2CM_WDAT_HI 31
++#define I2CM_WDAT_SZ 32
++#define I2CM_RDAT_MSK 0xffffffff
++#define I2CM_RDAT_I_MSK 0x00000000
++#define I2CM_RDAT_SFT 0
++#define I2CM_RDAT_HI 31
++#define I2CM_RDAT_SZ 32
++#define I2CM_SR_LEN_MSK 0x0000ffff
++#define I2CM_SR_LEN_I_MSK 0xffff0000
++#define I2CM_SR_LEN_SFT 0
++#define I2CM_SR_LEN_HI 15
++#define I2CM_SR_LEN_SZ 16
++#define I2CM_SR_RX_MSK 0x00010000
++#define I2CM_SR_RX_I_MSK 0xfffeffff
++#define I2CM_SR_RX_SFT 16
++#define I2CM_SR_RX_HI 16
++#define I2CM_SR_RX_SZ 1
++#define I2CM_REPEAT_START_MSK 0x00020000
++#define I2CM_REPEAT_START_I_MSK 0xfffdffff
++#define I2CM_REPEAT_START_SFT 17
++#define I2CM_REPEAT_START_HI 17
++#define I2CM_REPEAT_START_SZ 1
++#define UART_DATA_MSK 0x000000ff
++#define UART_DATA_I_MSK 0xffffff00
++#define UART_DATA_SFT 0
++#define UART_DATA_HI 7
++#define UART_DATA_SZ 8
++#define DATA_RDY_IE_MSK 0x00000001
++#define DATA_RDY_IE_I_MSK 0xfffffffe
++#define DATA_RDY_IE_SFT 0
++#define DATA_RDY_IE_HI 0
++#define DATA_RDY_IE_SZ 1
++#define THR_EMPTY_IE_MSK 0x00000002
++#define THR_EMPTY_IE_I_MSK 0xfffffffd
++#define THR_EMPTY_IE_SFT 1
++#define THR_EMPTY_IE_HI 1
++#define THR_EMPTY_IE_SZ 1
++#define RX_LINESTS_IE_MSK 0x00000004
++#define RX_LINESTS_IE_I_MSK 0xfffffffb
++#define RX_LINESTS_IE_SFT 2
++#define RX_LINESTS_IE_HI 2
++#define RX_LINESTS_IE_SZ 1
++#define MDM_STS_IE_MSK 0x00000008
++#define MDM_STS_IE_I_MSK 0xfffffff7
++#define MDM_STS_IE_SFT 3
++#define MDM_STS_IE_HI 3
++#define MDM_STS_IE_SZ 1
++#define DMA_RXEND_IE_MSK 0x00000040
++#define DMA_RXEND_IE_I_MSK 0xffffffbf
++#define DMA_RXEND_IE_SFT 6
++#define DMA_RXEND_IE_HI 6
++#define DMA_RXEND_IE_SZ 1
++#define DMA_TXEND_IE_MSK 0x00000080
++#define DMA_TXEND_IE_I_MSK 0xffffff7f
++#define DMA_TXEND_IE_SFT 7
++#define DMA_TXEND_IE_HI 7
++#define DMA_TXEND_IE_SZ 1
++#define FIFO_EN_MSK 0x00000001
++#define FIFO_EN_I_MSK 0xfffffffe
++#define FIFO_EN_SFT 0
++#define FIFO_EN_HI 0
++#define FIFO_EN_SZ 1
++#define RXFIFO_RST_MSK 0x00000002
++#define RXFIFO_RST_I_MSK 0xfffffffd
++#define RXFIFO_RST_SFT 1
++#define RXFIFO_RST_HI 1
++#define RXFIFO_RST_SZ 1
++#define TXFIFO_RST_MSK 0x00000004
++#define TXFIFO_RST_I_MSK 0xfffffffb
++#define TXFIFO_RST_SFT 2
++#define TXFIFO_RST_HI 2
++#define TXFIFO_RST_SZ 1
++#define DMA_MODE_MSK 0x00000008
++#define DMA_MODE_I_MSK 0xfffffff7
++#define DMA_MODE_SFT 3
++#define DMA_MODE_HI 3
++#define DMA_MODE_SZ 1
++#define EN_AUTO_RTS_MSK 0x00000010
++#define EN_AUTO_RTS_I_MSK 0xffffffef
++#define EN_AUTO_RTS_SFT 4
++#define EN_AUTO_RTS_HI 4
++#define EN_AUTO_RTS_SZ 1
++#define EN_AUTO_CTS_MSK 0x00000020
++#define EN_AUTO_CTS_I_MSK 0xffffffdf
++#define EN_AUTO_CTS_SFT 5
++#define EN_AUTO_CTS_HI 5
++#define EN_AUTO_CTS_SZ 1
++#define RXFIFO_TRGLVL_MSK 0x000000c0
++#define RXFIFO_TRGLVL_I_MSK 0xffffff3f
++#define RXFIFO_TRGLVL_SFT 6
++#define RXFIFO_TRGLVL_HI 7
++#define RXFIFO_TRGLVL_SZ 2
++#define WORD_LEN_MSK 0x00000003
++#define WORD_LEN_I_MSK 0xfffffffc
++#define WORD_LEN_SFT 0
++#define WORD_LEN_HI 1
++#define WORD_LEN_SZ 2
++#define STOP_BIT_MSK 0x00000004
++#define STOP_BIT_I_MSK 0xfffffffb
++#define STOP_BIT_SFT 2
++#define STOP_BIT_HI 2
++#define STOP_BIT_SZ 1
++#define PARITY_EN_MSK 0x00000008
++#define PARITY_EN_I_MSK 0xfffffff7
++#define PARITY_EN_SFT 3
++#define PARITY_EN_HI 3
++#define PARITY_EN_SZ 1
++#define EVEN_PARITY_MSK 0x00000010
++#define EVEN_PARITY_I_MSK 0xffffffef
++#define EVEN_PARITY_SFT 4
++#define EVEN_PARITY_HI 4
++#define EVEN_PARITY_SZ 1
++#define FORCE_PARITY_MSK 0x00000020
++#define FORCE_PARITY_I_MSK 0xffffffdf
++#define FORCE_PARITY_SFT 5
++#define FORCE_PARITY_HI 5
++#define FORCE_PARITY_SZ 1
++#define SET_BREAK_MSK 0x00000040
++#define SET_BREAK_I_MSK 0xffffffbf
++#define SET_BREAK_SFT 6
++#define SET_BREAK_HI 6
++#define SET_BREAK_SZ 1
++#define DLAB_MSK 0x00000080
++#define DLAB_I_MSK 0xffffff7f
++#define DLAB_SFT 7
++#define DLAB_HI 7
++#define DLAB_SZ 1
++#define DTR_MSK 0x00000001
++#define DTR_I_MSK 0xfffffffe
++#define DTR_SFT 0
++#define DTR_HI 0
++#define DTR_SZ 1
++#define RTS_MSK 0x00000002
++#define RTS_I_MSK 0xfffffffd
++#define RTS_SFT 1
++#define RTS_HI 1
++#define RTS_SZ 1
++#define OUT_1_MSK 0x00000004
++#define OUT_1_I_MSK 0xfffffffb
++#define OUT_1_SFT 2
++#define OUT_1_HI 2
++#define OUT_1_SZ 1
++#define OUT_2_MSK 0x00000008
++#define OUT_2_I_MSK 0xfffffff7
++#define OUT_2_SFT 3
++#define OUT_2_HI 3
++#define OUT_2_SZ 1
++#define LOOP_BACK_MSK 0x00000010
++#define LOOP_BACK_I_MSK 0xffffffef
++#define LOOP_BACK_SFT 4
++#define LOOP_BACK_HI 4
++#define LOOP_BACK_SZ 1
++#define DATA_RDY_MSK 0x00000001
++#define DATA_RDY_I_MSK 0xfffffffe
++#define DATA_RDY_SFT 0
++#define DATA_RDY_HI 0
++#define DATA_RDY_SZ 1
++#define OVERRUN_ERR_MSK 0x00000002
++#define OVERRUN_ERR_I_MSK 0xfffffffd
++#define OVERRUN_ERR_SFT 1
++#define OVERRUN_ERR_HI 1
++#define OVERRUN_ERR_SZ 1
++#define PARITY_ERR_MSK 0x00000004
++#define PARITY_ERR_I_MSK 0xfffffffb
++#define PARITY_ERR_SFT 2
++#define PARITY_ERR_HI 2
++#define PARITY_ERR_SZ 1
++#define FRAMING_ERR_MSK 0x00000008
++#define FRAMING_ERR_I_MSK 0xfffffff7
++#define FRAMING_ERR_SFT 3
++#define FRAMING_ERR_HI 3
++#define FRAMING_ERR_SZ 1
++#define BREAK_INT_MSK 0x00000010
++#define BREAK_INT_I_MSK 0xffffffef
++#define BREAK_INT_SFT 4
++#define BREAK_INT_HI 4
++#define BREAK_INT_SZ 1
++#define THR_EMPTY_MSK 0x00000020
++#define THR_EMPTY_I_MSK 0xffffffdf
++#define THR_EMPTY_SFT 5
++#define THR_EMPTY_HI 5
++#define THR_EMPTY_SZ 1
++#define TX_EMPTY_MSK 0x00000040
++#define TX_EMPTY_I_MSK 0xffffffbf
++#define TX_EMPTY_SFT 6
++#define TX_EMPTY_HI 6
++#define TX_EMPTY_SZ 1
++#define FIFODATA_ERR_MSK 0x00000080
++#define FIFODATA_ERR_I_MSK 0xffffff7f
++#define FIFODATA_ERR_SFT 7
++#define FIFODATA_ERR_HI 7
++#define FIFODATA_ERR_SZ 1
++#define DELTA_CTS_MSK 0x00000001
++#define DELTA_CTS_I_MSK 0xfffffffe
++#define DELTA_CTS_SFT 0
++#define DELTA_CTS_HI 0
++#define DELTA_CTS_SZ 1
++#define DELTA_DSR_MSK 0x00000002
++#define DELTA_DSR_I_MSK 0xfffffffd
++#define DELTA_DSR_SFT 1
++#define DELTA_DSR_HI 1
++#define DELTA_DSR_SZ 1
++#define TRAILEDGE_RI_MSK 0x00000004
++#define TRAILEDGE_RI_I_MSK 0xfffffffb
++#define TRAILEDGE_RI_SFT 2
++#define TRAILEDGE_RI_HI 2
++#define TRAILEDGE_RI_SZ 1
++#define DELTA_CD_MSK 0x00000008
++#define DELTA_CD_I_MSK 0xfffffff7
++#define DELTA_CD_SFT 3
++#define DELTA_CD_HI 3
++#define DELTA_CD_SZ 1
++#define CTS_MSK 0x00000010
++#define CTS_I_MSK 0xffffffef
++#define CTS_SFT 4
++#define CTS_HI 4
++#define CTS_SZ 1
++#define DSR_MSK 0x00000020
++#define DSR_I_MSK 0xffffffdf
++#define DSR_SFT 5
++#define DSR_HI 5
++#define DSR_SZ 1
++#define RI_MSK 0x00000040
++#define RI_I_MSK 0xffffffbf
++#define RI_SFT 6
++#define RI_HI 6
++#define RI_SZ 1
++#define CD_MSK 0x00000080
++#define CD_I_MSK 0xffffff7f
++#define CD_SFT 7
++#define CD_HI 7
++#define CD_SZ 1
++#define BRDC_DIV_MSK 0x0000ffff
++#define BRDC_DIV_I_MSK 0xffff0000
++#define BRDC_DIV_SFT 0
++#define BRDC_DIV_HI 15
++#define BRDC_DIV_SZ 16
++#define RTHR_L_MSK 0x0000000f
++#define RTHR_L_I_MSK 0xfffffff0
++#define RTHR_L_SFT 0
++#define RTHR_L_HI 3
++#define RTHR_L_SZ 4
++#define RTHR_H_MSK 0x000000f0
++#define RTHR_H_I_MSK 0xffffff0f
++#define RTHR_H_SFT 4
++#define RTHR_H_HI 7
++#define RTHR_H_SZ 4
++#define INT_IDCODE_MSK 0x0000000f
++#define INT_IDCODE_I_MSK 0xfffffff0
++#define INT_IDCODE_SFT 0
++#define INT_IDCODE_HI 3
++#define INT_IDCODE_SZ 4
++#define FIFOS_ENABLED_MSK 0x000000c0
++#define FIFOS_ENABLED_I_MSK 0xffffff3f
++#define FIFOS_ENABLED_SFT 6
++#define FIFOS_ENABLED_HI 7
++#define FIFOS_ENABLED_SZ 2
++#define DAT_UART_DATA_MSK 0x000000ff
++#define DAT_UART_DATA_I_MSK 0xffffff00
++#define DAT_UART_DATA_SFT 0
++#define DAT_UART_DATA_HI 7
++#define DAT_UART_DATA_SZ 8
++#define DAT_DATA_RDY_IE_MSK 0x00000001
++#define DAT_DATA_RDY_IE_I_MSK 0xfffffffe
++#define DAT_DATA_RDY_IE_SFT 0
++#define DAT_DATA_RDY_IE_HI 0
++#define DAT_DATA_RDY_IE_SZ 1
++#define DAT_THR_EMPTY_IE_MSK 0x00000002
++#define DAT_THR_EMPTY_IE_I_MSK 0xfffffffd
++#define DAT_THR_EMPTY_IE_SFT 1
++#define DAT_THR_EMPTY_IE_HI 1
++#define DAT_THR_EMPTY_IE_SZ 1
++#define DAT_RX_LINESTS_IE_MSK 0x00000004
++#define DAT_RX_LINESTS_IE_I_MSK 0xfffffffb
++#define DAT_RX_LINESTS_IE_SFT 2
++#define DAT_RX_LINESTS_IE_HI 2
++#define DAT_RX_LINESTS_IE_SZ 1
++#define DAT_MDM_STS_IE_MSK 0x00000008
++#define DAT_MDM_STS_IE_I_MSK 0xfffffff7
++#define DAT_MDM_STS_IE_SFT 3
++#define DAT_MDM_STS_IE_HI 3
++#define DAT_MDM_STS_IE_SZ 1
++#define DAT_DMA_RXEND_IE_MSK 0x00000040
++#define DAT_DMA_RXEND_IE_I_MSK 0xffffffbf
++#define DAT_DMA_RXEND_IE_SFT 6
++#define DAT_DMA_RXEND_IE_HI 6
++#define DAT_DMA_RXEND_IE_SZ 1
++#define DAT_DMA_TXEND_IE_MSK 0x00000080
++#define DAT_DMA_TXEND_IE_I_MSK 0xffffff7f
++#define DAT_DMA_TXEND_IE_SFT 7
++#define DAT_DMA_TXEND_IE_HI 7
++#define DAT_DMA_TXEND_IE_SZ 1
++#define DAT_FIFO_EN_MSK 0x00000001
++#define DAT_FIFO_EN_I_MSK 0xfffffffe
++#define DAT_FIFO_EN_SFT 0
++#define DAT_FIFO_EN_HI 0
++#define DAT_FIFO_EN_SZ 1
++#define DAT_RXFIFO_RST_MSK 0x00000002
++#define DAT_RXFIFO_RST_I_MSK 0xfffffffd
++#define DAT_RXFIFO_RST_SFT 1
++#define DAT_RXFIFO_RST_HI 1
++#define DAT_RXFIFO_RST_SZ 1
++#define DAT_TXFIFO_RST_MSK 0x00000004
++#define DAT_TXFIFO_RST_I_MSK 0xfffffffb
++#define DAT_TXFIFO_RST_SFT 2
++#define DAT_TXFIFO_RST_HI 2
++#define DAT_TXFIFO_RST_SZ 1
++#define DAT_DMA_MODE_MSK 0x00000008
++#define DAT_DMA_MODE_I_MSK 0xfffffff7
++#define DAT_DMA_MODE_SFT 3
++#define DAT_DMA_MODE_HI 3
++#define DAT_DMA_MODE_SZ 1
++#define DAT_EN_AUTO_RTS_MSK 0x00000010
++#define DAT_EN_AUTO_RTS_I_MSK 0xffffffef
++#define DAT_EN_AUTO_RTS_SFT 4
++#define DAT_EN_AUTO_RTS_HI 4
++#define DAT_EN_AUTO_RTS_SZ 1
++#define DAT_EN_AUTO_CTS_MSK 0x00000020
++#define DAT_EN_AUTO_CTS_I_MSK 0xffffffdf
++#define DAT_EN_AUTO_CTS_SFT 5
++#define DAT_EN_AUTO_CTS_HI 5
++#define DAT_EN_AUTO_CTS_SZ 1
++#define DAT_RXFIFO_TRGLVL_MSK 0x000000c0
++#define DAT_RXFIFO_TRGLVL_I_MSK 0xffffff3f
++#define DAT_RXFIFO_TRGLVL_SFT 6
++#define DAT_RXFIFO_TRGLVL_HI 7
++#define DAT_RXFIFO_TRGLVL_SZ 2
++#define DAT_WORD_LEN_MSK 0x00000003
++#define DAT_WORD_LEN_I_MSK 0xfffffffc
++#define DAT_WORD_LEN_SFT 0
++#define DAT_WORD_LEN_HI 1
++#define DAT_WORD_LEN_SZ 2
++#define DAT_STOP_BIT_MSK 0x00000004
++#define DAT_STOP_BIT_I_MSK 0xfffffffb
++#define DAT_STOP_BIT_SFT 2
++#define DAT_STOP_BIT_HI 2
++#define DAT_STOP_BIT_SZ 1
++#define DAT_PARITY_EN_MSK 0x00000008
++#define DAT_PARITY_EN_I_MSK 0xfffffff7
++#define DAT_PARITY_EN_SFT 3
++#define DAT_PARITY_EN_HI 3
++#define DAT_PARITY_EN_SZ 1
++#define DAT_EVEN_PARITY_MSK 0x00000010
++#define DAT_EVEN_PARITY_I_MSK 0xffffffef
++#define DAT_EVEN_PARITY_SFT 4
++#define DAT_EVEN_PARITY_HI 4
++#define DAT_EVEN_PARITY_SZ 1
++#define DAT_FORCE_PARITY_MSK 0x00000020
++#define DAT_FORCE_PARITY_I_MSK 0xffffffdf
++#define DAT_FORCE_PARITY_SFT 5
++#define DAT_FORCE_PARITY_HI 5
++#define DAT_FORCE_PARITY_SZ 1
++#define DAT_SET_BREAK_MSK 0x00000040
++#define DAT_SET_BREAK_I_MSK 0xffffffbf
++#define DAT_SET_BREAK_SFT 6
++#define DAT_SET_BREAK_HI 6
++#define DAT_SET_BREAK_SZ 1
++#define DAT_DLAB_MSK 0x00000080
++#define DAT_DLAB_I_MSK 0xffffff7f
++#define DAT_DLAB_SFT 7
++#define DAT_DLAB_HI 7
++#define DAT_DLAB_SZ 1
++#define DAT_DTR_MSK 0x00000001
++#define DAT_DTR_I_MSK 0xfffffffe
++#define DAT_DTR_SFT 0
++#define DAT_DTR_HI 0
++#define DAT_DTR_SZ 1
++#define DAT_RTS_MSK 0x00000002
++#define DAT_RTS_I_MSK 0xfffffffd
++#define DAT_RTS_SFT 1
++#define DAT_RTS_HI 1
++#define DAT_RTS_SZ 1
++#define DAT_OUT_1_MSK 0x00000004
++#define DAT_OUT_1_I_MSK 0xfffffffb
++#define DAT_OUT_1_SFT 2
++#define DAT_OUT_1_HI 2
++#define DAT_OUT_1_SZ 1
++#define DAT_OUT_2_MSK 0x00000008
++#define DAT_OUT_2_I_MSK 0xfffffff7
++#define DAT_OUT_2_SFT 3
++#define DAT_OUT_2_HI 3
++#define DAT_OUT_2_SZ 1
++#define DAT_LOOP_BACK_MSK 0x00000010
++#define DAT_LOOP_BACK_I_MSK 0xffffffef
++#define DAT_LOOP_BACK_SFT 4
++#define DAT_LOOP_BACK_HI 4
++#define DAT_LOOP_BACK_SZ 1
++#define DAT_DATA_RDY_MSK 0x00000001
++#define DAT_DATA_RDY_I_MSK 0xfffffffe
++#define DAT_DATA_RDY_SFT 0
++#define DAT_DATA_RDY_HI 0
++#define DAT_DATA_RDY_SZ 1
++#define DAT_OVERRUN_ERR_MSK 0x00000002
++#define DAT_OVERRUN_ERR_I_MSK 0xfffffffd
++#define DAT_OVERRUN_ERR_SFT 1
++#define DAT_OVERRUN_ERR_HI 1
++#define DAT_OVERRUN_ERR_SZ 1
++#define DAT_PARITY_ERR_MSK 0x00000004
++#define DAT_PARITY_ERR_I_MSK 0xfffffffb
++#define DAT_PARITY_ERR_SFT 2
++#define DAT_PARITY_ERR_HI 2
++#define DAT_PARITY_ERR_SZ 1
++#define DAT_FRAMING_ERR_MSK 0x00000008
++#define DAT_FRAMING_ERR_I_MSK 0xfffffff7
++#define DAT_FRAMING_ERR_SFT 3
++#define DAT_FRAMING_ERR_HI 3
++#define DAT_FRAMING_ERR_SZ 1
++#define DAT_BREAK_INT_MSK 0x00000010
++#define DAT_BREAK_INT_I_MSK 0xffffffef
++#define DAT_BREAK_INT_SFT 4
++#define DAT_BREAK_INT_HI 4
++#define DAT_BREAK_INT_SZ 1
++#define DAT_THR_EMPTY_MSK 0x00000020
++#define DAT_THR_EMPTY_I_MSK 0xffffffdf
++#define DAT_THR_EMPTY_SFT 5
++#define DAT_THR_EMPTY_HI 5
++#define DAT_THR_EMPTY_SZ 1
++#define DAT_TX_EMPTY_MSK 0x00000040
++#define DAT_TX_EMPTY_I_MSK 0xffffffbf
++#define DAT_TX_EMPTY_SFT 6
++#define DAT_TX_EMPTY_HI 6
++#define DAT_TX_EMPTY_SZ 1
++#define DAT_FIFODATA_ERR_MSK 0x00000080
++#define DAT_FIFODATA_ERR_I_MSK 0xffffff7f
++#define DAT_FIFODATA_ERR_SFT 7
++#define DAT_FIFODATA_ERR_HI 7
++#define DAT_FIFODATA_ERR_SZ 1
++#define DAT_DELTA_CTS_MSK 0x00000001
++#define DAT_DELTA_CTS_I_MSK 0xfffffffe
++#define DAT_DELTA_CTS_SFT 0
++#define DAT_DELTA_CTS_HI 0
++#define DAT_DELTA_CTS_SZ 1
++#define DAT_DELTA_DSR_MSK 0x00000002
++#define DAT_DELTA_DSR_I_MSK 0xfffffffd
++#define DAT_DELTA_DSR_SFT 1
++#define DAT_DELTA_DSR_HI 1
++#define DAT_DELTA_DSR_SZ 1
++#define DAT_TRAILEDGE_RI_MSK 0x00000004
++#define DAT_TRAILEDGE_RI_I_MSK 0xfffffffb
++#define DAT_TRAILEDGE_RI_SFT 2
++#define DAT_TRAILEDGE_RI_HI 2
++#define DAT_TRAILEDGE_RI_SZ 1
++#define DAT_DELTA_CD_MSK 0x00000008
++#define DAT_DELTA_CD_I_MSK 0xfffffff7
++#define DAT_DELTA_CD_SFT 3
++#define DAT_DELTA_CD_HI 3
++#define DAT_DELTA_CD_SZ 1
++#define DAT_CTS_MSK 0x00000010
++#define DAT_CTS_I_MSK 0xffffffef
++#define DAT_CTS_SFT 4
++#define DAT_CTS_HI 4
++#define DAT_CTS_SZ 1
++#define DAT_DSR_MSK 0x00000020
++#define DAT_DSR_I_MSK 0xffffffdf
++#define DAT_DSR_SFT 5
++#define DAT_DSR_HI 5
++#define DAT_DSR_SZ 1
++#define DAT_RI_MSK 0x00000040
++#define DAT_RI_I_MSK 0xffffffbf
++#define DAT_RI_SFT 6
++#define DAT_RI_HI 6
++#define DAT_RI_SZ 1
++#define DAT_CD_MSK 0x00000080
++#define DAT_CD_I_MSK 0xffffff7f
++#define DAT_CD_SFT 7
++#define DAT_CD_HI 7
++#define DAT_CD_SZ 1
++#define DAT_BRDC_DIV_MSK 0x0000ffff
++#define DAT_BRDC_DIV_I_MSK 0xffff0000
++#define DAT_BRDC_DIV_SFT 0
++#define DAT_BRDC_DIV_HI 15
++#define DAT_BRDC_DIV_SZ 16
++#define DAT_RTHR_L_MSK 0x0000000f
++#define DAT_RTHR_L_I_MSK 0xfffffff0
++#define DAT_RTHR_L_SFT 0
++#define DAT_RTHR_L_HI 3
++#define DAT_RTHR_L_SZ 4
++#define DAT_RTHR_H_MSK 0x000000f0
++#define DAT_RTHR_H_I_MSK 0xffffff0f
++#define DAT_RTHR_H_SFT 4
++#define DAT_RTHR_H_HI 7
++#define DAT_RTHR_H_SZ 4
++#define DAT_INT_IDCODE_MSK 0x0000000f
++#define DAT_INT_IDCODE_I_MSK 0xfffffff0
++#define DAT_INT_IDCODE_SFT 0
++#define DAT_INT_IDCODE_HI 3
++#define DAT_INT_IDCODE_SZ 4
++#define DAT_FIFOS_ENABLED_MSK 0x000000c0
++#define DAT_FIFOS_ENABLED_I_MSK 0xffffff3f
++#define DAT_FIFOS_ENABLED_SFT 6
++#define DAT_FIFOS_ENABLED_HI 7
++#define DAT_FIFOS_ENABLED_SZ 2
++#define MASK_TOP_MSK 0xffffffff
++#define MASK_TOP_I_MSK 0x00000000
++#define MASK_TOP_SFT 0
++#define MASK_TOP_HI 31
++#define MASK_TOP_SZ 32
++#define INT_MODE_MSK 0xffffffff
++#define INT_MODE_I_MSK 0x00000000
++#define INT_MODE_SFT 0
++#define INT_MODE_HI 31
++#define INT_MODE_SZ 32
++#define IRQ_PHY_0_MSK 0x00000001
++#define IRQ_PHY_0_I_MSK 0xfffffffe
++#define IRQ_PHY_0_SFT 0
++#define IRQ_PHY_0_HI 0
++#define IRQ_PHY_0_SZ 1
++#define IRQ_PHY_1_MSK 0x00000002
++#define IRQ_PHY_1_I_MSK 0xfffffffd
++#define IRQ_PHY_1_SFT 1
++#define IRQ_PHY_1_HI 1
++#define IRQ_PHY_1_SZ 1
++#define IRQ_SDIO_MSK 0x00000004
++#define IRQ_SDIO_I_MSK 0xfffffffb
++#define IRQ_SDIO_SFT 2
++#define IRQ_SDIO_HI 2
++#define IRQ_SDIO_SZ 1
++#define IRQ_BEACON_DONE_MSK 0x00000008
++#define IRQ_BEACON_DONE_I_MSK 0xfffffff7
++#define IRQ_BEACON_DONE_SFT 3
++#define IRQ_BEACON_DONE_HI 3
++#define IRQ_BEACON_DONE_SZ 1
++#define IRQ_BEACON_MSK 0x00000010
++#define IRQ_BEACON_I_MSK 0xffffffef
++#define IRQ_BEACON_SFT 4
++#define IRQ_BEACON_HI 4
++#define IRQ_BEACON_SZ 1
++#define IRQ_PRE_BEACON_MSK 0x00000020
++#define IRQ_PRE_BEACON_I_MSK 0xffffffdf
++#define IRQ_PRE_BEACON_SFT 5
++#define IRQ_PRE_BEACON_HI 5
++#define IRQ_PRE_BEACON_SZ 1
++#define IRQ_EDCA0_TX_DONE_MSK 0x00000040
++#define IRQ_EDCA0_TX_DONE_I_MSK 0xffffffbf
++#define IRQ_EDCA0_TX_DONE_SFT 6
++#define IRQ_EDCA0_TX_DONE_HI 6
++#define IRQ_EDCA0_TX_DONE_SZ 1
++#define IRQ_EDCA1_TX_DONE_MSK 0x00000080
++#define IRQ_EDCA1_TX_DONE_I_MSK 0xffffff7f
++#define IRQ_EDCA1_TX_DONE_SFT 7
++#define IRQ_EDCA1_TX_DONE_HI 7
++#define IRQ_EDCA1_TX_DONE_SZ 1
++#define IRQ_EDCA2_TX_DONE_MSK 0x00000100
++#define IRQ_EDCA2_TX_DONE_I_MSK 0xfffffeff
++#define IRQ_EDCA2_TX_DONE_SFT 8
++#define IRQ_EDCA2_TX_DONE_HI 8
++#define IRQ_EDCA2_TX_DONE_SZ 1
++#define IRQ_EDCA3_TX_DONE_MSK 0x00000200
++#define IRQ_EDCA3_TX_DONE_I_MSK 0xfffffdff
++#define IRQ_EDCA3_TX_DONE_SFT 9
++#define IRQ_EDCA3_TX_DONE_HI 9
++#define IRQ_EDCA3_TX_DONE_SZ 1
++#define IRQ_EDCA4_TX_DONE_MSK 0x00000400
++#define IRQ_EDCA4_TX_DONE_I_MSK 0xfffffbff
++#define IRQ_EDCA4_TX_DONE_SFT 10
++#define IRQ_EDCA4_TX_DONE_HI 10
++#define IRQ_EDCA4_TX_DONE_SZ 1
++#define IRQ_BEACON_DTIM_MSK 0x00001000
++#define IRQ_BEACON_DTIM_I_MSK 0xffffefff
++#define IRQ_BEACON_DTIM_SFT 12
++#define IRQ_BEACON_DTIM_HI 12
++#define IRQ_BEACON_DTIM_SZ 1
++#define IRQ_EDCA0_LOWTHOLD_INT_MSK 0x00002000
++#define IRQ_EDCA0_LOWTHOLD_INT_I_MSK 0xffffdfff
++#define IRQ_EDCA0_LOWTHOLD_INT_SFT 13
++#define IRQ_EDCA0_LOWTHOLD_INT_HI 13
++#define IRQ_EDCA0_LOWTHOLD_INT_SZ 1
++#define IRQ_EDCA1_LOWTHOLD_INT_MSK 0x00004000
++#define IRQ_EDCA1_LOWTHOLD_INT_I_MSK 0xffffbfff
++#define IRQ_EDCA1_LOWTHOLD_INT_SFT 14
++#define IRQ_EDCA1_LOWTHOLD_INT_HI 14
++#define IRQ_EDCA1_LOWTHOLD_INT_SZ 1
++#define IRQ_EDCA2_LOWTHOLD_INT_MSK 0x00008000
++#define IRQ_EDCA2_LOWTHOLD_INT_I_MSK 0xffff7fff
++#define IRQ_EDCA2_LOWTHOLD_INT_SFT 15
++#define IRQ_EDCA2_LOWTHOLD_INT_HI 15
++#define IRQ_EDCA2_LOWTHOLD_INT_SZ 1
++#define IRQ_EDCA3_LOWTHOLD_INT_MSK 0x00010000
++#define IRQ_EDCA3_LOWTHOLD_INT_I_MSK 0xfffeffff
++#define IRQ_EDCA3_LOWTHOLD_INT_SFT 16
++#define IRQ_EDCA3_LOWTHOLD_INT_HI 16
++#define IRQ_EDCA3_LOWTHOLD_INT_SZ 1
++#define IRQ_FENCE_HIT_INT_MSK 0x00020000
++#define IRQ_FENCE_HIT_INT_I_MSK 0xfffdffff
++#define IRQ_FENCE_HIT_INT_SFT 17
++#define IRQ_FENCE_HIT_INT_HI 17
++#define IRQ_FENCE_HIT_INT_SZ 1
++#define IRQ_ILL_ADDR_INT_MSK 0x00040000
++#define IRQ_ILL_ADDR_INT_I_MSK 0xfffbffff
++#define IRQ_ILL_ADDR_INT_SFT 18
++#define IRQ_ILL_ADDR_INT_HI 18
++#define IRQ_ILL_ADDR_INT_SZ 1
++#define IRQ_MBOX_MSK 0x00080000
++#define IRQ_MBOX_I_MSK 0xfff7ffff
++#define IRQ_MBOX_SFT 19
++#define IRQ_MBOX_HI 19
++#define IRQ_MBOX_SZ 1
++#define IRQ_US_TIMER0_MSK 0x00100000
++#define IRQ_US_TIMER0_I_MSK 0xffefffff
++#define IRQ_US_TIMER0_SFT 20
++#define IRQ_US_TIMER0_HI 20
++#define IRQ_US_TIMER0_SZ 1
++#define IRQ_US_TIMER1_MSK 0x00200000
++#define IRQ_US_TIMER1_I_MSK 0xffdfffff
++#define IRQ_US_TIMER1_SFT 21
++#define IRQ_US_TIMER1_HI 21
++#define IRQ_US_TIMER1_SZ 1
++#define IRQ_US_TIMER2_MSK 0x00400000
++#define IRQ_US_TIMER2_I_MSK 0xffbfffff
++#define IRQ_US_TIMER2_SFT 22
++#define IRQ_US_TIMER2_HI 22
++#define IRQ_US_TIMER2_SZ 1
++#define IRQ_US_TIMER3_MSK 0x00800000
++#define IRQ_US_TIMER3_I_MSK 0xff7fffff
++#define IRQ_US_TIMER3_SFT 23
++#define IRQ_US_TIMER3_HI 23
++#define IRQ_US_TIMER3_SZ 1
++#define IRQ_MS_TIMER0_MSK 0x01000000
++#define IRQ_MS_TIMER0_I_MSK 0xfeffffff
++#define IRQ_MS_TIMER0_SFT 24
++#define IRQ_MS_TIMER0_HI 24
++#define IRQ_MS_TIMER0_SZ 1
++#define IRQ_MS_TIMER1_MSK 0x02000000
++#define IRQ_MS_TIMER1_I_MSK 0xfdffffff
++#define IRQ_MS_TIMER1_SFT 25
++#define IRQ_MS_TIMER1_HI 25
++#define IRQ_MS_TIMER1_SZ 1
++#define IRQ_MS_TIMER2_MSK 0x04000000
++#define IRQ_MS_TIMER2_I_MSK 0xfbffffff
++#define IRQ_MS_TIMER2_SFT 26
++#define IRQ_MS_TIMER2_HI 26
++#define IRQ_MS_TIMER2_SZ 1
++#define IRQ_MS_TIMER3_MSK 0x08000000
++#define IRQ_MS_TIMER3_I_MSK 0xf7ffffff
++#define IRQ_MS_TIMER3_SFT 27
++#define IRQ_MS_TIMER3_HI 27
++#define IRQ_MS_TIMER3_SZ 1
++#define IRQ_TX_LIMIT_INT_MSK 0x10000000
++#define IRQ_TX_LIMIT_INT_I_MSK 0xefffffff
++#define IRQ_TX_LIMIT_INT_SFT 28
++#define IRQ_TX_LIMIT_INT_HI 28
++#define IRQ_TX_LIMIT_INT_SZ 1
++#define IRQ_DMA0_MSK 0x20000000
++#define IRQ_DMA0_I_MSK 0xdfffffff
++#define IRQ_DMA0_SFT 29
++#define IRQ_DMA0_HI 29
++#define IRQ_DMA0_SZ 1
++#define IRQ_CO_DMA_MSK 0x40000000
++#define IRQ_CO_DMA_I_MSK 0xbfffffff
++#define IRQ_CO_DMA_SFT 30
++#define IRQ_CO_DMA_HI 30
++#define IRQ_CO_DMA_SZ 1
++#define IRQ_PERI_GROUP_MSK 0x80000000
++#define IRQ_PERI_GROUP_I_MSK 0x7fffffff
++#define IRQ_PERI_GROUP_SFT 31
++#define IRQ_PERI_GROUP_HI 31
++#define IRQ_PERI_GROUP_SZ 1
++#define FIQ_STATUS_MSK 0xffffffff
++#define FIQ_STATUS_I_MSK 0x00000000
++#define FIQ_STATUS_SFT 0
++#define FIQ_STATUS_HI 31
++#define FIQ_STATUS_SZ 32
++#define IRQ_RAW_MSK 0xffffffff
++#define IRQ_RAW_I_MSK 0x00000000
++#define IRQ_RAW_SFT 0
++#define IRQ_RAW_HI 31
++#define IRQ_RAW_SZ 32
++#define FIQ_RAW_MSK 0xffffffff
++#define FIQ_RAW_I_MSK 0x00000000
++#define FIQ_RAW_SFT 0
++#define FIQ_RAW_HI 31
++#define FIQ_RAW_SZ 32
++#define INT_PERI_MASK_MSK 0xffffffff
++#define INT_PERI_MASK_I_MSK 0x00000000
++#define INT_PERI_MASK_SFT 0
++#define INT_PERI_MASK_HI 31
++#define INT_PERI_MASK_SZ 32
++#define PERI_RTC_MSK 0x00000001
++#define PERI_RTC_I_MSK 0xfffffffe
++#define PERI_RTC_SFT 0
++#define PERI_RTC_HI 0
++#define PERI_RTC_SZ 1
++#define IRQ_UART0_TX_MSK 0x00000002
++#define IRQ_UART0_TX_I_MSK 0xfffffffd
++#define IRQ_UART0_TX_SFT 1
++#define IRQ_UART0_TX_HI 1
++#define IRQ_UART0_TX_SZ 1
++#define IRQ_UART0_RX_MSK 0x00000004
++#define IRQ_UART0_RX_I_MSK 0xfffffffb
++#define IRQ_UART0_RX_SFT 2
++#define IRQ_UART0_RX_HI 2
++#define IRQ_UART0_RX_SZ 1
++#define PERI_GPI_2_MSK 0x00000008
++#define PERI_GPI_2_I_MSK 0xfffffff7
++#define PERI_GPI_2_SFT 3
++#define PERI_GPI_2_HI 3
++#define PERI_GPI_2_SZ 1
++#define IRQ_SPI_IPC_MSK 0x00000010
++#define IRQ_SPI_IPC_I_MSK 0xffffffef
++#define IRQ_SPI_IPC_SFT 4
++#define IRQ_SPI_IPC_HI 4
++#define IRQ_SPI_IPC_SZ 1
++#define PERI_GPI_1_0_MSK 0x00000060
++#define PERI_GPI_1_0_I_MSK 0xffffff9f
++#define PERI_GPI_1_0_SFT 5
++#define PERI_GPI_1_0_HI 6
++#define PERI_GPI_1_0_SZ 2
++#define SCRT_INT_1_MSK 0x00000080
++#define SCRT_INT_1_I_MSK 0xffffff7f
++#define SCRT_INT_1_SFT 7
++#define SCRT_INT_1_HI 7
++#define SCRT_INT_1_SZ 1
++#define MMU_ALC_ERR_MSK 0x00000100
++#define MMU_ALC_ERR_I_MSK 0xfffffeff
++#define MMU_ALC_ERR_SFT 8
++#define MMU_ALC_ERR_HI 8
++#define MMU_ALC_ERR_SZ 1
++#define MMU_RLS_ERR_MSK 0x00000200
++#define MMU_RLS_ERR_I_MSK 0xfffffdff
++#define MMU_RLS_ERR_SFT 9
++#define MMU_RLS_ERR_HI 9
++#define MMU_RLS_ERR_SZ 1
++#define ID_MNG_INT_1_MSK 0x00000400
++#define ID_MNG_INT_1_I_MSK 0xfffffbff
++#define ID_MNG_INT_1_SFT 10
++#define ID_MNG_INT_1_HI 10
++#define ID_MNG_INT_1_SZ 1
++#define MBOX_INT_1_MSK 0x00000800
++#define MBOX_INT_1_I_MSK 0xfffff7ff
++#define MBOX_INT_1_SFT 11
++#define MBOX_INT_1_HI 11
++#define MBOX_INT_1_SZ 1
++#define MBOX_INT_2_MSK 0x00001000
++#define MBOX_INT_2_I_MSK 0xffffefff
++#define MBOX_INT_2_SFT 12
++#define MBOX_INT_2_HI 12
++#define MBOX_INT_2_SZ 1
++#define MBOX_INT_3_MSK 0x00002000
++#define MBOX_INT_3_I_MSK 0xffffdfff
++#define MBOX_INT_3_SFT 13
++#define MBOX_INT_3_HI 13
++#define MBOX_INT_3_SZ 1
++#define HCI_INT_1_MSK 0x00004000
++#define HCI_INT_1_I_MSK 0xffffbfff
++#define HCI_INT_1_SFT 14
++#define HCI_INT_1_HI 14
++#define HCI_INT_1_SZ 1
++#define UART_RX_TIMEOUT_MSK 0x00008000
++#define UART_RX_TIMEOUT_I_MSK 0xffff7fff
++#define UART_RX_TIMEOUT_SFT 15
++#define UART_RX_TIMEOUT_HI 15
++#define UART_RX_TIMEOUT_SZ 1
++#define UART_MULTI_IRQ_MSK 0x00010000
++#define UART_MULTI_IRQ_I_MSK 0xfffeffff
++#define UART_MULTI_IRQ_SFT 16
++#define UART_MULTI_IRQ_HI 16
++#define UART_MULTI_IRQ_SZ 1
++#define ID_MNG_INT_2_MSK 0x00020000
++#define ID_MNG_INT_2_I_MSK 0xfffdffff
++#define ID_MNG_INT_2_SFT 17
++#define ID_MNG_INT_2_HI 17
++#define ID_MNG_INT_2_SZ 1
++#define DMN_NOHIT_INT_MSK 0x00040000
++#define DMN_NOHIT_INT_I_MSK 0xfffbffff
++#define DMN_NOHIT_INT_SFT 18
++#define DMN_NOHIT_INT_HI 18
++#define DMN_NOHIT_INT_SZ 1
++#define ID_THOLD_RX_MSK 0x00080000
++#define ID_THOLD_RX_I_MSK 0xfff7ffff
++#define ID_THOLD_RX_SFT 19
++#define ID_THOLD_RX_HI 19
++#define ID_THOLD_RX_SZ 1
++#define ID_THOLD_TX_MSK 0x00100000
++#define ID_THOLD_TX_I_MSK 0xffefffff
++#define ID_THOLD_TX_SFT 20
++#define ID_THOLD_TX_HI 20
++#define ID_THOLD_TX_SZ 1
++#define ID_DOUBLE_RLS_MSK 0x00200000
++#define ID_DOUBLE_RLS_I_MSK 0xffdfffff
++#define ID_DOUBLE_RLS_SFT 21
++#define ID_DOUBLE_RLS_HI 21
++#define ID_DOUBLE_RLS_SZ 1
++#define RX_ID_LEN_THOLD_MSK 0x00400000
++#define RX_ID_LEN_THOLD_I_MSK 0xffbfffff
++#define RX_ID_LEN_THOLD_SFT 22
++#define RX_ID_LEN_THOLD_HI 22
++#define RX_ID_LEN_THOLD_SZ 1
++#define TX_ID_LEN_THOLD_MSK 0x00800000
++#define TX_ID_LEN_THOLD_I_MSK 0xff7fffff
++#define TX_ID_LEN_THOLD_SFT 23
++#define TX_ID_LEN_THOLD_HI 23
++#define TX_ID_LEN_THOLD_SZ 1
++#define ALL_ID_LEN_THOLD_MSK 0x01000000
++#define ALL_ID_LEN_THOLD_I_MSK 0xfeffffff
++#define ALL_ID_LEN_THOLD_SFT 24
++#define ALL_ID_LEN_THOLD_HI 24
++#define ALL_ID_LEN_THOLD_SZ 1
++#define DMN_MCU_INT_MSK 0x02000000
++#define DMN_MCU_INT_I_MSK 0xfdffffff
++#define DMN_MCU_INT_SFT 25
++#define DMN_MCU_INT_HI 25
++#define DMN_MCU_INT_SZ 1
++#define IRQ_DAT_UART_TX_MSK 0x04000000
++#define IRQ_DAT_UART_TX_I_MSK 0xfbffffff
++#define IRQ_DAT_UART_TX_SFT 26
++#define IRQ_DAT_UART_TX_HI 26
++#define IRQ_DAT_UART_TX_SZ 1
++#define IRQ_DAT_UART_RX_MSK 0x08000000
++#define IRQ_DAT_UART_RX_I_MSK 0xf7ffffff
++#define IRQ_DAT_UART_RX_SFT 27
++#define IRQ_DAT_UART_RX_HI 27
++#define IRQ_DAT_UART_RX_SZ 1
++#define DAT_UART_RX_TIMEOUT_MSK 0x10000000
++#define DAT_UART_RX_TIMEOUT_I_MSK 0xefffffff
++#define DAT_UART_RX_TIMEOUT_SFT 28
++#define DAT_UART_RX_TIMEOUT_HI 28
++#define DAT_UART_RX_TIMEOUT_SZ 1
++#define DAT_UART_MULTI_IRQ_MSK 0x20000000
++#define DAT_UART_MULTI_IRQ_I_MSK 0xdfffffff
++#define DAT_UART_MULTI_IRQ_SFT 29
++#define DAT_UART_MULTI_IRQ_HI 29
++#define DAT_UART_MULTI_IRQ_SZ 1
++#define ALR_ABT_NOCHG_INT_IRQ_MSK 0x40000000
++#define ALR_ABT_NOCHG_INT_IRQ_I_MSK 0xbfffffff
++#define ALR_ABT_NOCHG_INT_IRQ_SFT 30
++#define ALR_ABT_NOCHG_INT_IRQ_HI 30
++#define ALR_ABT_NOCHG_INT_IRQ_SZ 1
++#define TBLNEQ_MNGPKT_INT_IRQ_MSK 0x80000000
++#define TBLNEQ_MNGPKT_INT_IRQ_I_MSK 0x7fffffff
++#define TBLNEQ_MNGPKT_INT_IRQ_SFT 31
++#define TBLNEQ_MNGPKT_INT_IRQ_HI 31
++#define TBLNEQ_MNGPKT_INT_IRQ_SZ 1
++#define INTR_PERI_RAW_MSK 0xffffffff
++#define INTR_PERI_RAW_I_MSK 0x00000000
++#define INTR_PERI_RAW_SFT 0
++#define INTR_PERI_RAW_HI 31
++#define INTR_PERI_RAW_SZ 32
++#define INTR_GPI00_CFG_MSK 0x00000003
++#define INTR_GPI00_CFG_I_MSK 0xfffffffc
++#define INTR_GPI00_CFG_SFT 0
++#define INTR_GPI00_CFG_HI 1
++#define INTR_GPI00_CFG_SZ 2
++#define INTR_GPI01_CFG_MSK 0x0000000c
++#define INTR_GPI01_CFG_I_MSK 0xfffffff3
++#define INTR_GPI01_CFG_SFT 2
++#define INTR_GPI01_CFG_HI 3
++#define INTR_GPI01_CFG_SZ 2
++#define SYS_RST_INT_MSK 0x00000001
++#define SYS_RST_INT_I_MSK 0xfffffffe
++#define SYS_RST_INT_SFT 0
++#define SYS_RST_INT_HI 0
++#define SYS_RST_INT_SZ 1
++#define SPI_IPC_ADDR_MSK 0xffffffff
++#define SPI_IPC_ADDR_I_MSK 0x00000000
++#define SPI_IPC_ADDR_SFT 0
++#define SPI_IPC_ADDR_HI 31
++#define SPI_IPC_ADDR_SZ 32
++#define SD_MASK_TOP_MSK 0xffffffff
++#define SD_MASK_TOP_I_MSK 0x00000000
++#define SD_MASK_TOP_SFT 0
++#define SD_MASK_TOP_HI 31
++#define SD_MASK_TOP_SZ 32
++#define IRQ_PHY_0_SD_MSK 0x00000001
++#define IRQ_PHY_0_SD_I_MSK 0xfffffffe
++#define IRQ_PHY_0_SD_SFT 0
++#define IRQ_PHY_0_SD_HI 0
++#define IRQ_PHY_0_SD_SZ 1
++#define IRQ_PHY_1_SD_MSK 0x00000002
++#define IRQ_PHY_1_SD_I_MSK 0xfffffffd
++#define IRQ_PHY_1_SD_SFT 1
++#define IRQ_PHY_1_SD_HI 1
++#define IRQ_PHY_1_SD_SZ 1
++#define IRQ_SDIO_SD_MSK 0x00000004
++#define IRQ_SDIO_SD_I_MSK 0xfffffffb
++#define IRQ_SDIO_SD_SFT 2
++#define IRQ_SDIO_SD_HI 2
++#define IRQ_SDIO_SD_SZ 1
++#define IRQ_BEACON_DONE_SD_MSK 0x00000008
++#define IRQ_BEACON_DONE_SD_I_MSK 0xfffffff7
++#define IRQ_BEACON_DONE_SD_SFT 3
++#define IRQ_BEACON_DONE_SD_HI 3
++#define IRQ_BEACON_DONE_SD_SZ 1
++#define IRQ_BEACON_SD_MSK 0x00000010
++#define IRQ_BEACON_SD_I_MSK 0xffffffef
++#define IRQ_BEACON_SD_SFT 4
++#define IRQ_BEACON_SD_HI 4
++#define IRQ_BEACON_SD_SZ 1
++#define IRQ_PRE_BEACON_SD_MSK 0x00000020
++#define IRQ_PRE_BEACON_SD_I_MSK 0xffffffdf
++#define IRQ_PRE_BEACON_SD_SFT 5
++#define IRQ_PRE_BEACON_SD_HI 5
++#define IRQ_PRE_BEACON_SD_SZ 1
++#define IRQ_EDCA0_TX_DONE_SD_MSK 0x00000040
++#define IRQ_EDCA0_TX_DONE_SD_I_MSK 0xffffffbf
++#define IRQ_EDCA0_TX_DONE_SD_SFT 6
++#define IRQ_EDCA0_TX_DONE_SD_HI 6
++#define IRQ_EDCA0_TX_DONE_SD_SZ 1
++#define IRQ_EDCA1_TX_DONE_SD_MSK 0x00000080
++#define IRQ_EDCA1_TX_DONE_SD_I_MSK 0xffffff7f
++#define IRQ_EDCA1_TX_DONE_SD_SFT 7
++#define IRQ_EDCA1_TX_DONE_SD_HI 7
++#define IRQ_EDCA1_TX_DONE_SD_SZ 1
++#define IRQ_EDCA2_TX_DONE_SD_MSK 0x00000100
++#define IRQ_EDCA2_TX_DONE_SD_I_MSK 0xfffffeff
++#define IRQ_EDCA2_TX_DONE_SD_SFT 8
++#define IRQ_EDCA2_TX_DONE_SD_HI 8
++#define IRQ_EDCA2_TX_DONE_SD_SZ 1
++#define IRQ_EDCA3_TX_DONE_SD_MSK 0x00000200
++#define IRQ_EDCA3_TX_DONE_SD_I_MSK 0xfffffdff
++#define IRQ_EDCA3_TX_DONE_SD_SFT 9
++#define IRQ_EDCA3_TX_DONE_SD_HI 9
++#define IRQ_EDCA3_TX_DONE_SD_SZ 1
++#define IRQ_EDCA4_TX_DONE_SD_MSK 0x00000400
++#define IRQ_EDCA4_TX_DONE_SD_I_MSK 0xfffffbff
++#define IRQ_EDCA4_TX_DONE_SD_SFT 10
++#define IRQ_EDCA4_TX_DONE_SD_HI 10
++#define IRQ_EDCA4_TX_DONE_SD_SZ 1
++#define IRQ_BEACON_DTIM_SD_MSK 0x00001000
++#define IRQ_BEACON_DTIM_SD_I_MSK 0xffffefff
++#define IRQ_BEACON_DTIM_SD_SFT 12
++#define IRQ_BEACON_DTIM_SD_HI 12
++#define IRQ_BEACON_DTIM_SD_SZ 1
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_MSK 0x00002000
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK 0xffffdfff
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_SFT 13
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_HI 13
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_MSK 0x00004000
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK 0xffffbfff
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_SFT 14
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_HI 14
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_MSK 0x00008000
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK 0xffff7fff
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_SFT 15
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_HI 15
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_MSK 0x00010000
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK 0xfffeffff
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_SFT 16
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_HI 16
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_FENCE_HIT_INT_SD_MSK 0x00020000
++#define IRQ_FENCE_HIT_INT_SD_I_MSK 0xfffdffff
++#define IRQ_FENCE_HIT_INT_SD_SFT 17
++#define IRQ_FENCE_HIT_INT_SD_HI 17
++#define IRQ_FENCE_HIT_INT_SD_SZ 1
++#define IRQ_ILL_ADDR_INT_SD_MSK 0x00040000
++#define IRQ_ILL_ADDR_INT_SD_I_MSK 0xfffbffff
++#define IRQ_ILL_ADDR_INT_SD_SFT 18
++#define IRQ_ILL_ADDR_INT_SD_HI 18
++#define IRQ_ILL_ADDR_INT_SD_SZ 1
++#define IRQ_MBOX_SD_MSK 0x00080000
++#define IRQ_MBOX_SD_I_MSK 0xfff7ffff
++#define IRQ_MBOX_SD_SFT 19
++#define IRQ_MBOX_SD_HI 19
++#define IRQ_MBOX_SD_SZ 1
++#define IRQ_US_TIMER0_SD_MSK 0x00100000
++#define IRQ_US_TIMER0_SD_I_MSK 0xffefffff
++#define IRQ_US_TIMER0_SD_SFT 20
++#define IRQ_US_TIMER0_SD_HI 20
++#define IRQ_US_TIMER0_SD_SZ 1
++#define IRQ_US_TIMER1_SD_MSK 0x00200000
++#define IRQ_US_TIMER1_SD_I_MSK 0xffdfffff
++#define IRQ_US_TIMER1_SD_SFT 21
++#define IRQ_US_TIMER1_SD_HI 21
++#define IRQ_US_TIMER1_SD_SZ 1
++#define IRQ_US_TIMER2_SD_MSK 0x00400000
++#define IRQ_US_TIMER2_SD_I_MSK 0xffbfffff
++#define IRQ_US_TIMER2_SD_SFT 22
++#define IRQ_US_TIMER2_SD_HI 22
++#define IRQ_US_TIMER2_SD_SZ 1
++#define IRQ_US_TIMER3_SD_MSK 0x00800000
++#define IRQ_US_TIMER3_SD_I_MSK 0xff7fffff
++#define IRQ_US_TIMER3_SD_SFT 23
++#define IRQ_US_TIMER3_SD_HI 23
++#define IRQ_US_TIMER3_SD_SZ 1
++#define IRQ_MS_TIMER0_SD_MSK 0x01000000
++#define IRQ_MS_TIMER0_SD_I_MSK 0xfeffffff
++#define IRQ_MS_TIMER0_SD_SFT 24
++#define IRQ_MS_TIMER0_SD_HI 24
++#define IRQ_MS_TIMER0_SD_SZ 1
++#define IRQ_MS_TIMER1_SD_MSK 0x02000000
++#define IRQ_MS_TIMER1_SD_I_MSK 0xfdffffff
++#define IRQ_MS_TIMER1_SD_SFT 25
++#define IRQ_MS_TIMER1_SD_HI 25
++#define IRQ_MS_TIMER1_SD_SZ 1
++#define IRQ_MS_TIMER2_SD_MSK 0x04000000
++#define IRQ_MS_TIMER2_SD_I_MSK 0xfbffffff
++#define IRQ_MS_TIMER2_SD_SFT 26
++#define IRQ_MS_TIMER2_SD_HI 26
++#define IRQ_MS_TIMER2_SD_SZ 1
++#define IRQ_MS_TIMER3_SD_MSK 0x08000000
++#define IRQ_MS_TIMER3_SD_I_MSK 0xf7ffffff
++#define IRQ_MS_TIMER3_SD_SFT 27
++#define IRQ_MS_TIMER3_SD_HI 27
++#define IRQ_MS_TIMER3_SD_SZ 1
++#define IRQ_TX_LIMIT_INT_SD_MSK 0x10000000
++#define IRQ_TX_LIMIT_INT_SD_I_MSK 0xefffffff
++#define IRQ_TX_LIMIT_INT_SD_SFT 28
++#define IRQ_TX_LIMIT_INT_SD_HI 28
++#define IRQ_TX_LIMIT_INT_SD_SZ 1
++#define IRQ_DMA0_SD_MSK 0x20000000
++#define IRQ_DMA0_SD_I_MSK 0xdfffffff
++#define IRQ_DMA0_SD_SFT 29
++#define IRQ_DMA0_SD_HI 29
++#define IRQ_DMA0_SD_SZ 1
++#define IRQ_CO_DMA_SD_MSK 0x40000000
++#define IRQ_CO_DMA_SD_I_MSK 0xbfffffff
++#define IRQ_CO_DMA_SD_SFT 30
++#define IRQ_CO_DMA_SD_HI 30
++#define IRQ_CO_DMA_SD_SZ 1
++#define IRQ_PERI_GROUP_SD_MSK 0x80000000
++#define IRQ_PERI_GROUP_SD_I_MSK 0x7fffffff
++#define IRQ_PERI_GROUP_SD_SFT 31
++#define IRQ_PERI_GROUP_SD_HI 31
++#define IRQ_PERI_GROUP_SD_SZ 1
++#define INT_PERI_MASK_SD_MSK 0xffffffff
++#define INT_PERI_MASK_SD_I_MSK 0x00000000
++#define INT_PERI_MASK_SD_SFT 0
++#define INT_PERI_MASK_SD_HI 31
++#define INT_PERI_MASK_SD_SZ 32
++#define PERI_RTC_SD_MSK 0x00000001
++#define PERI_RTC_SD_I_MSK 0xfffffffe
++#define PERI_RTC_SD_SFT 0
++#define PERI_RTC_SD_HI 0
++#define PERI_RTC_SD_SZ 1
++#define IRQ_UART0_TX_SD_MSK 0x00000002
++#define IRQ_UART0_TX_SD_I_MSK 0xfffffffd
++#define IRQ_UART0_TX_SD_SFT 1
++#define IRQ_UART0_TX_SD_HI 1
++#define IRQ_UART0_TX_SD_SZ 1
++#define IRQ_UART0_RX_SD_MSK 0x00000004
++#define IRQ_UART0_RX_SD_I_MSK 0xfffffffb
++#define IRQ_UART0_RX_SD_SFT 2
++#define IRQ_UART0_RX_SD_HI 2
++#define IRQ_UART0_RX_SD_SZ 1
++#define PERI_GPI_SD_2_MSK 0x00000008
++#define PERI_GPI_SD_2_I_MSK 0xfffffff7
++#define PERI_GPI_SD_2_SFT 3
++#define PERI_GPI_SD_2_HI 3
++#define PERI_GPI_SD_2_SZ 1
++#define IRQ_SPI_IPC_SD_MSK 0x00000010
++#define IRQ_SPI_IPC_SD_I_MSK 0xffffffef
++#define IRQ_SPI_IPC_SD_SFT 4
++#define IRQ_SPI_IPC_SD_HI 4
++#define IRQ_SPI_IPC_SD_SZ 1
++#define PERI_GPI_SD_1_0_MSK 0x00000060
++#define PERI_GPI_SD_1_0_I_MSK 0xffffff9f
++#define PERI_GPI_SD_1_0_SFT 5
++#define PERI_GPI_SD_1_0_HI 6
++#define PERI_GPI_SD_1_0_SZ 2
++#define SCRT_INT_1_SD_MSK 0x00000080
++#define SCRT_INT_1_SD_I_MSK 0xffffff7f
++#define SCRT_INT_1_SD_SFT 7
++#define SCRT_INT_1_SD_HI 7
++#define SCRT_INT_1_SD_SZ 1
++#define MMU_ALC_ERR_SD_MSK 0x00000100
++#define MMU_ALC_ERR_SD_I_MSK 0xfffffeff
++#define MMU_ALC_ERR_SD_SFT 8
++#define MMU_ALC_ERR_SD_HI 8
++#define MMU_ALC_ERR_SD_SZ 1
++#define MMU_RLS_ERR_SD_MSK 0x00000200
++#define MMU_RLS_ERR_SD_I_MSK 0xfffffdff
++#define MMU_RLS_ERR_SD_SFT 9
++#define MMU_RLS_ERR_SD_HI 9
++#define MMU_RLS_ERR_SD_SZ 1
++#define ID_MNG_INT_1_SD_MSK 0x00000400
++#define ID_MNG_INT_1_SD_I_MSK 0xfffffbff
++#define ID_MNG_INT_1_SD_SFT 10
++#define ID_MNG_INT_1_SD_HI 10
++#define ID_MNG_INT_1_SD_SZ 1
++#define MBOX_INT_1_SD_MSK 0x00000800
++#define MBOX_INT_1_SD_I_MSK 0xfffff7ff
++#define MBOX_INT_1_SD_SFT 11
++#define MBOX_INT_1_SD_HI 11
++#define MBOX_INT_1_SD_SZ 1
++#define MBOX_INT_2_SD_MSK 0x00001000
++#define MBOX_INT_2_SD_I_MSK 0xffffefff
++#define MBOX_INT_2_SD_SFT 12
++#define MBOX_INT_2_SD_HI 12
++#define MBOX_INT_2_SD_SZ 1
++#define MBOX_INT_3_SD_MSK 0x00002000
++#define MBOX_INT_3_SD_I_MSK 0xffffdfff
++#define MBOX_INT_3_SD_SFT 13
++#define MBOX_INT_3_SD_HI 13
++#define MBOX_INT_3_SD_SZ 1
++#define HCI_INT_1_SD_MSK 0x00004000
++#define HCI_INT_1_SD_I_MSK 0xffffbfff
++#define HCI_INT_1_SD_SFT 14
++#define HCI_INT_1_SD_HI 14
++#define HCI_INT_1_SD_SZ 1
++#define UART_RX_TIMEOUT_SD_MSK 0x00008000
++#define UART_RX_TIMEOUT_SD_I_MSK 0xffff7fff
++#define UART_RX_TIMEOUT_SD_SFT 15
++#define UART_RX_TIMEOUT_SD_HI 15
++#define UART_RX_TIMEOUT_SD_SZ 1
++#define UART_MULTI_IRQ_SD_MSK 0x00010000
++#define UART_MULTI_IRQ_SD_I_MSK 0xfffeffff
++#define UART_MULTI_IRQ_SD_SFT 16
++#define UART_MULTI_IRQ_SD_HI 16
++#define UART_MULTI_IRQ_SD_SZ 1
++#define ID_MNG_INT_2_SD_MSK 0x00020000
++#define ID_MNG_INT_2_SD_I_MSK 0xfffdffff
++#define ID_MNG_INT_2_SD_SFT 17
++#define ID_MNG_INT_2_SD_HI 17
++#define ID_MNG_INT_2_SD_SZ 1
++#define DMN_NOHIT_INT_SD_MSK 0x00040000
++#define DMN_NOHIT_INT_SD_I_MSK 0xfffbffff
++#define DMN_NOHIT_INT_SD_SFT 18
++#define DMN_NOHIT_INT_SD_HI 18
++#define DMN_NOHIT_INT_SD_SZ 1
++#define ID_THOLD_RX_SD_MSK 0x00080000
++#define ID_THOLD_RX_SD_I_MSK 0xfff7ffff
++#define ID_THOLD_RX_SD_SFT 19
++#define ID_THOLD_RX_SD_HI 19
++#define ID_THOLD_RX_SD_SZ 1
++#define ID_THOLD_TX_SD_MSK 0x00100000
++#define ID_THOLD_TX_SD_I_MSK 0xffefffff
++#define ID_THOLD_TX_SD_SFT 20
++#define ID_THOLD_TX_SD_HI 20
++#define ID_THOLD_TX_SD_SZ 1
++#define ID_DOUBLE_RLS_SD_MSK 0x00200000
++#define ID_DOUBLE_RLS_SD_I_MSK 0xffdfffff
++#define ID_DOUBLE_RLS_SD_SFT 21
++#define ID_DOUBLE_RLS_SD_HI 21
++#define ID_DOUBLE_RLS_SD_SZ 1
++#define RX_ID_LEN_THOLD_SD_MSK 0x00400000
++#define RX_ID_LEN_THOLD_SD_I_MSK 0xffbfffff
++#define RX_ID_LEN_THOLD_SD_SFT 22
++#define RX_ID_LEN_THOLD_SD_HI 22
++#define RX_ID_LEN_THOLD_SD_SZ 1
++#define TX_ID_LEN_THOLD_SD_MSK 0x00800000
++#define TX_ID_LEN_THOLD_SD_I_MSK 0xff7fffff
++#define TX_ID_LEN_THOLD_SD_SFT 23
++#define TX_ID_LEN_THOLD_SD_HI 23
++#define TX_ID_LEN_THOLD_SD_SZ 1
++#define ALL_ID_LEN_THOLD_SD_MSK 0x01000000
++#define ALL_ID_LEN_THOLD_SD_I_MSK 0xfeffffff
++#define ALL_ID_LEN_THOLD_SD_SFT 24
++#define ALL_ID_LEN_THOLD_SD_HI 24
++#define ALL_ID_LEN_THOLD_SD_SZ 1
++#define DMN_MCU_INT_SD_MSK 0x02000000
++#define DMN_MCU_INT_SD_I_MSK 0xfdffffff
++#define DMN_MCU_INT_SD_SFT 25
++#define DMN_MCU_INT_SD_HI 25
++#define DMN_MCU_INT_SD_SZ 1
++#define IRQ_DAT_UART_TX_SD_MSK 0x04000000
++#define IRQ_DAT_UART_TX_SD_I_MSK 0xfbffffff
++#define IRQ_DAT_UART_TX_SD_SFT 26
++#define IRQ_DAT_UART_TX_SD_HI 26
++#define IRQ_DAT_UART_TX_SD_SZ 1
++#define IRQ_DAT_UART_RX_SD_MSK 0x08000000
++#define IRQ_DAT_UART_RX_SD_I_MSK 0xf7ffffff
++#define IRQ_DAT_UART_RX_SD_SFT 27
++#define IRQ_DAT_UART_RX_SD_HI 27
++#define IRQ_DAT_UART_RX_SD_SZ 1
++#define DAT_UART_RX_TIMEOUT_SD_MSK 0x10000000
++#define DAT_UART_RX_TIMEOUT_SD_I_MSK 0xefffffff
++#define DAT_UART_RX_TIMEOUT_SD_SFT 28
++#define DAT_UART_RX_TIMEOUT_SD_HI 28
++#define DAT_UART_RX_TIMEOUT_SD_SZ 1
++#define DAT_UART_MULTI_IRQ_SD_MSK 0x20000000
++#define DAT_UART_MULTI_IRQ_SD_I_MSK 0xdfffffff
++#define DAT_UART_MULTI_IRQ_SD_SFT 29
++#define DAT_UART_MULTI_IRQ_SD_HI 29
++#define DAT_UART_MULTI_IRQ_SD_SZ 1
++#define ALR_ABT_NOCHG_INT_IRQ_SD_MSK 0x40000000
++#define ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK 0xbfffffff
++#define ALR_ABT_NOCHG_INT_IRQ_SD_SFT 30
++#define ALR_ABT_NOCHG_INT_IRQ_SD_HI 30
++#define ALR_ABT_NOCHG_INT_IRQ_SD_SZ 1
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_MSK 0x80000000
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK 0x7fffffff
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_SFT 31
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_HI 31
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_SZ 1
++#define DBG_SPI_MODE_MSK 0xffffffff
++#define DBG_SPI_MODE_I_MSK 0x00000000
++#define DBG_SPI_MODE_SFT 0
++#define DBG_SPI_MODE_HI 31
++#define DBG_SPI_MODE_SZ 32
++#define DBG_RX_QUOTA_MSK 0x0000ffff
++#define DBG_RX_QUOTA_I_MSK 0xffff0000
++#define DBG_RX_QUOTA_SFT 0
++#define DBG_RX_QUOTA_HI 15
++#define DBG_RX_QUOTA_SZ 16
++#define DBG_CONDI_NUM_MSK 0x000000ff
++#define DBG_CONDI_NUM_I_MSK 0xffffff00
++#define DBG_CONDI_NUM_SFT 0
++#define DBG_CONDI_NUM_HI 7
++#define DBG_CONDI_NUM_SZ 8
++#define DBG_HOST_PATH_MSK 0x00000001
++#define DBG_HOST_PATH_I_MSK 0xfffffffe
++#define DBG_HOST_PATH_SFT 0
++#define DBG_HOST_PATH_HI 0
++#define DBG_HOST_PATH_SZ 1
++#define DBG_TX_SEG_MSK 0xffffffff
++#define DBG_TX_SEG_I_MSK 0x00000000
++#define DBG_TX_SEG_SFT 0
++#define DBG_TX_SEG_HI 31
++#define DBG_TX_SEG_SZ 32
++#define DBG_BRST_MODE_MSK 0x00000001
++#define DBG_BRST_MODE_I_MSK 0xfffffffe
++#define DBG_BRST_MODE_SFT 0
++#define DBG_BRST_MODE_HI 0
++#define DBG_BRST_MODE_SZ 1
++#define DBG_CLK_WIDTH_MSK 0x0000ffff
++#define DBG_CLK_WIDTH_I_MSK 0xffff0000
++#define DBG_CLK_WIDTH_SFT 0
++#define DBG_CLK_WIDTH_HI 15
++#define DBG_CLK_WIDTH_SZ 16
++#define DBG_CSN_INTER_MSK 0xffff0000
++#define DBG_CSN_INTER_I_MSK 0x0000ffff
++#define DBG_CSN_INTER_SFT 16
++#define DBG_CSN_INTER_HI 31
++#define DBG_CSN_INTER_SZ 16
++#define DBG_BACK_DLY_MSK 0x0000ffff
++#define DBG_BACK_DLY_I_MSK 0xffff0000
++#define DBG_BACK_DLY_SFT 0
++#define DBG_BACK_DLY_HI 15
++#define DBG_BACK_DLY_SZ 16
++#define DBG_FRONT_DLY_MSK 0xffff0000
++#define DBG_FRONT_DLY_I_MSK 0x0000ffff
++#define DBG_FRONT_DLY_SFT 16
++#define DBG_FRONT_DLY_HI 31
++#define DBG_FRONT_DLY_SZ 16
++#define DBG_RX_FIFO_FAIL_MSK 0x00000002
++#define DBG_RX_FIFO_FAIL_I_MSK 0xfffffffd
++#define DBG_RX_FIFO_FAIL_SFT 1
++#define DBG_RX_FIFO_FAIL_HI 1
++#define DBG_RX_FIFO_FAIL_SZ 1
++#define DBG_RX_HOST_FAIL_MSK 0x00000004
++#define DBG_RX_HOST_FAIL_I_MSK 0xfffffffb
++#define DBG_RX_HOST_FAIL_SFT 2
++#define DBG_RX_HOST_FAIL_HI 2
++#define DBG_RX_HOST_FAIL_SZ 1
++#define DBG_TX_FIFO_FAIL_MSK 0x00000008
++#define DBG_TX_FIFO_FAIL_I_MSK 0xfffffff7
++#define DBG_TX_FIFO_FAIL_SFT 3
++#define DBG_TX_FIFO_FAIL_HI 3
++#define DBG_TX_FIFO_FAIL_SZ 1
++#define DBG_TX_HOST_FAIL_MSK 0x00000010
++#define DBG_TX_HOST_FAIL_I_MSK 0xffffffef
++#define DBG_TX_HOST_FAIL_SFT 4
++#define DBG_TX_HOST_FAIL_HI 4
++#define DBG_TX_HOST_FAIL_SZ 1
++#define DBG_SPI_DOUBLE_ALLOC_MSK 0x00000020
++#define DBG_SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
++#define DBG_SPI_DOUBLE_ALLOC_SFT 5
++#define DBG_SPI_DOUBLE_ALLOC_HI 5
++#define DBG_SPI_DOUBLE_ALLOC_SZ 1
++#define DBG_SPI_TX_NO_ALLOC_MSK 0x00000040
++#define DBG_SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
++#define DBG_SPI_TX_NO_ALLOC_SFT 6
++#define DBG_SPI_TX_NO_ALLOC_HI 6
++#define DBG_SPI_TX_NO_ALLOC_SZ 1
++#define DBG_RDATA_RDY_MSK 0x00000080
++#define DBG_RDATA_RDY_I_MSK 0xffffff7f
++#define DBG_RDATA_RDY_SFT 7
++#define DBG_RDATA_RDY_HI 7
++#define DBG_RDATA_RDY_SZ 1
++#define DBG_SPI_ALLOC_STATUS_MSK 0x00000100
++#define DBG_SPI_ALLOC_STATUS_I_MSK 0xfffffeff
++#define DBG_SPI_ALLOC_STATUS_SFT 8
++#define DBG_SPI_ALLOC_STATUS_HI 8
++#define DBG_SPI_ALLOC_STATUS_SZ 1
++#define DBG_SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
++#define DBG_SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
++#define DBG_SPI_DBG_WR_FIFO_FULL_SFT 9
++#define DBG_SPI_DBG_WR_FIFO_FULL_HI 9
++#define DBG_SPI_DBG_WR_FIFO_FULL_SZ 1
++#define DBG_RX_LEN_MSK 0xffff0000
++#define DBG_RX_LEN_I_MSK 0x0000ffff
++#define DBG_RX_LEN_SFT 16
++#define DBG_RX_LEN_HI 31
++#define DBG_RX_LEN_SZ 16
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT 8
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_HI 8
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ 1
++#define DBG_SPI_TX_ALLOC_SIZE_MSK 0x000000ff
++#define DBG_SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
++#define DBG_SPI_TX_ALLOC_SIZE_SFT 0
++#define DBG_SPI_TX_ALLOC_SIZE_HI 7
++#define DBG_SPI_TX_ALLOC_SIZE_SZ 8
++#define DBG_RD_DAT_CNT_MSK 0x0000ffff
++#define DBG_RD_DAT_CNT_I_MSK 0xffff0000
++#define DBG_RD_DAT_CNT_SFT 0
++#define DBG_RD_DAT_CNT_HI 15
++#define DBG_RD_DAT_CNT_SZ 16
++#define DBG_RD_STS_CNT_MSK 0xffff0000
++#define DBG_RD_STS_CNT_I_MSK 0x0000ffff
++#define DBG_RD_STS_CNT_SFT 16
++#define DBG_RD_STS_CNT_HI 31
++#define DBG_RD_STS_CNT_SZ 16
++#define DBG_JUDGE_CNT_MSK 0x0000ffff
++#define DBG_JUDGE_CNT_I_MSK 0xffff0000
++#define DBG_JUDGE_CNT_SFT 0
++#define DBG_JUDGE_CNT_HI 15
++#define DBG_JUDGE_CNT_SZ 16
++#define DBG_RD_STS_CNT_CLR_MSK 0x00010000
++#define DBG_RD_STS_CNT_CLR_I_MSK 0xfffeffff
++#define DBG_RD_STS_CNT_CLR_SFT 16
++#define DBG_RD_STS_CNT_CLR_HI 16
++#define DBG_RD_STS_CNT_CLR_SZ 1
++#define DBG_RD_DAT_CNT_CLR_MSK 0x00020000
++#define DBG_RD_DAT_CNT_CLR_I_MSK 0xfffdffff
++#define DBG_RD_DAT_CNT_CLR_SFT 17
++#define DBG_RD_DAT_CNT_CLR_HI 17
++#define DBG_RD_DAT_CNT_CLR_SZ 1
++#define DBG_JUDGE_CNT_CLR_MSK 0x00040000
++#define DBG_JUDGE_CNT_CLR_I_MSK 0xfffbffff
++#define DBG_JUDGE_CNT_CLR_SFT 18
++#define DBG_JUDGE_CNT_CLR_HI 18
++#define DBG_JUDGE_CNT_CLR_SZ 1
++#define DBG_TX_DONE_CNT_MSK 0x0000ffff
++#define DBG_TX_DONE_CNT_I_MSK 0xffff0000
++#define DBG_TX_DONE_CNT_SFT 0
++#define DBG_TX_DONE_CNT_HI 15
++#define DBG_TX_DONE_CNT_SZ 16
++#define DBG_TX_DISCARD_CNT_MSK 0xffff0000
++#define DBG_TX_DISCARD_CNT_I_MSK 0x0000ffff
++#define DBG_TX_DISCARD_CNT_SFT 16
++#define DBG_TX_DISCARD_CNT_HI 31
++#define DBG_TX_DISCARD_CNT_SZ 16
++#define DBG_TX_SET_CNT_MSK 0x0000ffff
++#define DBG_TX_SET_CNT_I_MSK 0xffff0000
++#define DBG_TX_SET_CNT_SFT 0
++#define DBG_TX_SET_CNT_HI 15
++#define DBG_TX_SET_CNT_SZ 16
++#define DBG_TX_DISCARD_CNT_CLR_MSK 0x00010000
++#define DBG_TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
++#define DBG_TX_DISCARD_CNT_CLR_SFT 16
++#define DBG_TX_DISCARD_CNT_CLR_HI 16
++#define DBG_TX_DISCARD_CNT_CLR_SZ 1
++#define DBG_TX_DONE_CNT_CLR_MSK 0x00020000
++#define DBG_TX_DONE_CNT_CLR_I_MSK 0xfffdffff
++#define DBG_TX_DONE_CNT_CLR_SFT 17
++#define DBG_TX_DONE_CNT_CLR_HI 17
++#define DBG_TX_DONE_CNT_CLR_SZ 1
++#define DBG_TX_SET_CNT_CLR_MSK 0x00040000
++#define DBG_TX_SET_CNT_CLR_I_MSK 0xfffbffff
++#define DBG_TX_SET_CNT_CLR_SFT 18
++#define DBG_TX_SET_CNT_CLR_HI 18
++#define DBG_TX_SET_CNT_CLR_SZ 1
++#define DBG_DAT_MODE_OFF_MSK 0x00080000
++#define DBG_DAT_MODE_OFF_I_MSK 0xfff7ffff
++#define DBG_DAT_MODE_OFF_SFT 19
++#define DBG_DAT_MODE_OFF_HI 19
++#define DBG_DAT_MODE_OFF_SZ 1
++#define DBG_TX_FIFO_RESIDUE_MSK 0x00700000
++#define DBG_TX_FIFO_RESIDUE_I_MSK 0xff8fffff
++#define DBG_TX_FIFO_RESIDUE_SFT 20
++#define DBG_TX_FIFO_RESIDUE_HI 22
++#define DBG_TX_FIFO_RESIDUE_SZ 3
++#define DBG_RX_FIFO_RESIDUE_MSK 0x07000000
++#define DBG_RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
++#define DBG_RX_FIFO_RESIDUE_SFT 24
++#define DBG_RX_FIFO_RESIDUE_HI 26
++#define DBG_RX_FIFO_RESIDUE_SZ 3
++#define DBG_RX_RDY_MSK 0x00000001
++#define DBG_RX_RDY_I_MSK 0xfffffffe
++#define DBG_RX_RDY_SFT 0
++#define DBG_RX_RDY_HI 0
++#define DBG_RX_RDY_SZ 1
++#define DBG_SDIO_SYS_INT_MSK 0x00000004
++#define DBG_SDIO_SYS_INT_I_MSK 0xfffffffb
++#define DBG_SDIO_SYS_INT_SFT 2
++#define DBG_SDIO_SYS_INT_HI 2
++#define DBG_SDIO_SYS_INT_SZ 1
++#define DBG_EDCA0_LOWTHOLD_INT_MSK 0x00000008
++#define DBG_EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
++#define DBG_EDCA0_LOWTHOLD_INT_SFT 3
++#define DBG_EDCA0_LOWTHOLD_INT_HI 3
++#define DBG_EDCA0_LOWTHOLD_INT_SZ 1
++#define DBG_EDCA1_LOWTHOLD_INT_MSK 0x00000010
++#define DBG_EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
++#define DBG_EDCA1_LOWTHOLD_INT_SFT 4
++#define DBG_EDCA1_LOWTHOLD_INT_HI 4
++#define DBG_EDCA1_LOWTHOLD_INT_SZ 1
++#define DBG_EDCA2_LOWTHOLD_INT_MSK 0x00000020
++#define DBG_EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
++#define DBG_EDCA2_LOWTHOLD_INT_SFT 5
++#define DBG_EDCA2_LOWTHOLD_INT_HI 5
++#define DBG_EDCA2_LOWTHOLD_INT_SZ 1
++#define DBG_EDCA3_LOWTHOLD_INT_MSK 0x00000040
++#define DBG_EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
++#define DBG_EDCA3_LOWTHOLD_INT_SFT 6
++#define DBG_EDCA3_LOWTHOLD_INT_HI 6
++#define DBG_EDCA3_LOWTHOLD_INT_SZ 1
++#define DBG_TX_LIMIT_INT_IN_MSK 0x00000080
++#define DBG_TX_LIMIT_INT_IN_I_MSK 0xffffff7f
++#define DBG_TX_LIMIT_INT_IN_SFT 7
++#define DBG_TX_LIMIT_INT_IN_HI 7
++#define DBG_TX_LIMIT_INT_IN_SZ 1
++#define DBG_SPI_FN1_MSK 0x00007f00
++#define DBG_SPI_FN1_I_MSK 0xffff80ff
++#define DBG_SPI_FN1_SFT 8
++#define DBG_SPI_FN1_HI 14
++#define DBG_SPI_FN1_SZ 7
++#define DBG_SPI_CLK_EN_INT_MSK 0x00008000
++#define DBG_SPI_CLK_EN_INT_I_MSK 0xffff7fff
++#define DBG_SPI_CLK_EN_INT_SFT 15
++#define DBG_SPI_CLK_EN_INT_HI 15
++#define DBG_SPI_CLK_EN_INT_SZ 1
++#define DBG_SPI_HOST_MASK_MSK 0x00ff0000
++#define DBG_SPI_HOST_MASK_I_MSK 0xff00ffff
++#define DBG_SPI_HOST_MASK_SFT 16
++#define DBG_SPI_HOST_MASK_HI 23
++#define DBG_SPI_HOST_MASK_SZ 8
++#define BOOT_ADDR_MSK 0x00ffffff
++#define BOOT_ADDR_I_MSK 0xff000000
++#define BOOT_ADDR_SFT 0
++#define BOOT_ADDR_HI 23
++#define BOOT_ADDR_SZ 24
++#define CHECK_SUM_FAIL_MSK 0x80000000
++#define CHECK_SUM_FAIL_I_MSK 0x7fffffff
++#define CHECK_SUM_FAIL_SFT 31
++#define CHECK_SUM_FAIL_HI 31
++#define CHECK_SUM_FAIL_SZ 1
++#define VERIFY_DATA_MSK 0xffffffff
++#define VERIFY_DATA_I_MSK 0x00000000
++#define VERIFY_DATA_SFT 0
++#define VERIFY_DATA_HI 31
++#define VERIFY_DATA_SZ 32
++#define FLASH_ADDR_MSK 0x00ffffff
++#define FLASH_ADDR_I_MSK 0xff000000
++#define FLASH_ADDR_SFT 0
++#define FLASH_ADDR_HI 23
++#define FLASH_ADDR_SZ 24
++#define FLASH_CMD_CLR_MSK 0x10000000
++#define FLASH_CMD_CLR_I_MSK 0xefffffff
++#define FLASH_CMD_CLR_SFT 28
++#define FLASH_CMD_CLR_HI 28
++#define FLASH_CMD_CLR_SZ 1
++#define FLASH_DMA_CLR_MSK 0x20000000
++#define FLASH_DMA_CLR_I_MSK 0xdfffffff
++#define FLASH_DMA_CLR_SFT 29
++#define FLASH_DMA_CLR_HI 29
++#define FLASH_DMA_CLR_SZ 1
++#define DMA_EN_MSK 0x40000000
++#define DMA_EN_I_MSK 0xbfffffff
++#define DMA_EN_SFT 30
++#define DMA_EN_HI 30
++#define DMA_EN_SZ 1
++#define DMA_BUSY_MSK 0x80000000
++#define DMA_BUSY_I_MSK 0x7fffffff
++#define DMA_BUSY_SFT 31
++#define DMA_BUSY_HI 31
++#define DMA_BUSY_SZ 1
++#define SRAM_ADDR_MSK 0xffffffff
++#define SRAM_ADDR_I_MSK 0x00000000
++#define SRAM_ADDR_SFT 0
++#define SRAM_ADDR_HI 31
++#define SRAM_ADDR_SZ 32
++#define FLASH_DMA_LEN_MSK 0xffffffff
++#define FLASH_DMA_LEN_I_MSK 0x00000000
++#define FLASH_DMA_LEN_SFT 0
++#define FLASH_DMA_LEN_HI 31
++#define FLASH_DMA_LEN_SZ 32
++#define FLASH_FRONT_DLY_MSK 0x0000ffff
++#define FLASH_FRONT_DLY_I_MSK 0xffff0000
++#define FLASH_FRONT_DLY_SFT 0
++#define FLASH_FRONT_DLY_HI 15
++#define FLASH_FRONT_DLY_SZ 16
++#define FLASH_BACK_DLY_MSK 0xffff0000
++#define FLASH_BACK_DLY_I_MSK 0x0000ffff
++#define FLASH_BACK_DLY_SFT 16
++#define FLASH_BACK_DLY_HI 31
++#define FLASH_BACK_DLY_SZ 16
++#define FLASH_CLK_WIDTH_MSK 0x0000ffff
++#define FLASH_CLK_WIDTH_I_MSK 0xffff0000
++#define FLASH_CLK_WIDTH_SFT 0
++#define FLASH_CLK_WIDTH_HI 15
++#define FLASH_CLK_WIDTH_SZ 16
++#define SPI_BUSY_MSK 0x00010000
++#define SPI_BUSY_I_MSK 0xfffeffff
++#define SPI_BUSY_SFT 16
++#define SPI_BUSY_HI 16
++#define SPI_BUSY_SZ 1
++#define FLS_REMAP_MSK 0x00020000
++#define FLS_REMAP_I_MSK 0xfffdffff
++#define FLS_REMAP_SFT 17
++#define FLS_REMAP_HI 17
++#define FLS_REMAP_SZ 1
++#define PBUS_SWP_MSK 0x00040000
++#define PBUS_SWP_I_MSK 0xfffbffff
++#define PBUS_SWP_SFT 18
++#define PBUS_SWP_HI 18
++#define PBUS_SWP_SZ 1
++#define BIT_MODE1_MSK 0x00080000
++#define BIT_MODE1_I_MSK 0xfff7ffff
++#define BIT_MODE1_SFT 19
++#define BIT_MODE1_HI 19
++#define BIT_MODE1_SZ 1
++#define BIT_MODE2_MSK 0x00100000
++#define BIT_MODE2_I_MSK 0xffefffff
++#define BIT_MODE2_SFT 20
++#define BIT_MODE2_HI 20
++#define BIT_MODE2_SZ 1
++#define BIT_MODE4_MSK 0x00200000
++#define BIT_MODE4_I_MSK 0xffdfffff
++#define BIT_MODE4_SFT 21
++#define BIT_MODE4_HI 21
++#define BIT_MODE4_SZ 1
++#define BOOT_CHECK_SUM_MSK 0xffffffff
++#define BOOT_CHECK_SUM_I_MSK 0x00000000
++#define BOOT_CHECK_SUM_SFT 0
++#define BOOT_CHECK_SUM_HI 31
++#define BOOT_CHECK_SUM_SZ 32
++#define CHECK_SUM_TAG_MSK 0xffffffff
++#define CHECK_SUM_TAG_I_MSK 0x00000000
++#define CHECK_SUM_TAG_SFT 0
++#define CHECK_SUM_TAG_HI 31
++#define CHECK_SUM_TAG_SZ 32
++#define CMD_LEN_MSK 0x0000ffff
++#define CMD_LEN_I_MSK 0xffff0000
++#define CMD_LEN_SFT 0
++#define CMD_LEN_HI 15
++#define CMD_LEN_SZ 16
++#define CMD_ADDR_MSK 0xffffffff
++#define CMD_ADDR_I_MSK 0x00000000
++#define CMD_ADDR_SFT 0
++#define CMD_ADDR_HI 31
++#define CMD_ADDR_SZ 32
++#define DMA_ADR_SRC_MSK 0xffffffff
++#define DMA_ADR_SRC_I_MSK 0x00000000
++#define DMA_ADR_SRC_SFT 0
++#define DMA_ADR_SRC_HI 31
++#define DMA_ADR_SRC_SZ 32
++#define DMA_ADR_DST_MSK 0xffffffff
++#define DMA_ADR_DST_I_MSK 0x00000000
++#define DMA_ADR_DST_SFT 0
++#define DMA_ADR_DST_HI 31
++#define DMA_ADR_DST_SZ 32
++#define DMA_SRC_SIZE_MSK 0x00000007
++#define DMA_SRC_SIZE_I_MSK 0xfffffff8
++#define DMA_SRC_SIZE_SFT 0
++#define DMA_SRC_SIZE_HI 2
++#define DMA_SRC_SIZE_SZ 3
++#define DMA_SRC_INC_MSK 0x00000008
++#define DMA_SRC_INC_I_MSK 0xfffffff7
++#define DMA_SRC_INC_SFT 3
++#define DMA_SRC_INC_HI 3
++#define DMA_SRC_INC_SZ 1
++#define DMA_DST_SIZE_MSK 0x00000070
++#define DMA_DST_SIZE_I_MSK 0xffffff8f
++#define DMA_DST_SIZE_SFT 4
++#define DMA_DST_SIZE_HI 6
++#define DMA_DST_SIZE_SZ 3
++#define DMA_DST_INC_MSK 0x00000080
++#define DMA_DST_INC_I_MSK 0xffffff7f
++#define DMA_DST_INC_SFT 7
++#define DMA_DST_INC_HI 7
++#define DMA_DST_INC_SZ 1
++#define DMA_FAST_FILL_MSK 0x00000100
++#define DMA_FAST_FILL_I_MSK 0xfffffeff
++#define DMA_FAST_FILL_SFT 8
++#define DMA_FAST_FILL_HI 8
++#define DMA_FAST_FILL_SZ 1
++#define DMA_SDIO_KICK_MSK 0x00001000
++#define DMA_SDIO_KICK_I_MSK 0xffffefff
++#define DMA_SDIO_KICK_SFT 12
++#define DMA_SDIO_KICK_HI 12
++#define DMA_SDIO_KICK_SZ 1
++#define DMA_BADR_EN_MSK 0x00002000
++#define DMA_BADR_EN_I_MSK 0xffffdfff
++#define DMA_BADR_EN_SFT 13
++#define DMA_BADR_EN_HI 13
++#define DMA_BADR_EN_SZ 1
++#define DMA_LEN_MSK 0xffff0000
++#define DMA_LEN_I_MSK 0x0000ffff
++#define DMA_LEN_SFT 16
++#define DMA_LEN_HI 31
++#define DMA_LEN_SZ 16
++#define DMA_INT_MASK_MSK 0x00000001
++#define DMA_INT_MASK_I_MSK 0xfffffffe
++#define DMA_INT_MASK_SFT 0
++#define DMA_INT_MASK_HI 0
++#define DMA_INT_MASK_SZ 1
++#define DMA_STS_MSK 0x00000100
++#define DMA_STS_I_MSK 0xfffffeff
++#define DMA_STS_SFT 8
++#define DMA_STS_HI 8
++#define DMA_STS_SZ 1
++#define DMA_FINISH_MSK 0x80000000
++#define DMA_FINISH_I_MSK 0x7fffffff
++#define DMA_FINISH_SFT 31
++#define DMA_FINISH_HI 31
++#define DMA_FINISH_SZ 1
++#define DMA_CONST_MSK 0xffffffff
++#define DMA_CONST_I_MSK 0x00000000
++#define DMA_CONST_SFT 0
++#define DMA_CONST_HI 31
++#define DMA_CONST_SZ 32
++#define SLEEP_WAKE_CNT_MSK 0x00ffffff
++#define SLEEP_WAKE_CNT_I_MSK 0xff000000
++#define SLEEP_WAKE_CNT_SFT 0
++#define SLEEP_WAKE_CNT_HI 23
++#define SLEEP_WAKE_CNT_SZ 24
++#define RG_DLDO_LEVEL_MSK 0x07000000
++#define RG_DLDO_LEVEL_I_MSK 0xf8ffffff
++#define RG_DLDO_LEVEL_SFT 24
++#define RG_DLDO_LEVEL_HI 26
++#define RG_DLDO_LEVEL_SZ 3
++#define RG_DLDO_BOOST_IQ_MSK 0x08000000
++#define RG_DLDO_BOOST_IQ_I_MSK 0xf7ffffff
++#define RG_DLDO_BOOST_IQ_SFT 27
++#define RG_DLDO_BOOST_IQ_HI 27
++#define RG_DLDO_BOOST_IQ_SZ 1
++#define RG_BUCK_LEVEL_MSK 0x70000000
++#define RG_BUCK_LEVEL_I_MSK 0x8fffffff
++#define RG_BUCK_LEVEL_SFT 28
++#define RG_BUCK_LEVEL_HI 30
++#define RG_BUCK_LEVEL_SZ 3
++#define RG_BUCK_VREF_SEL_MSK 0x80000000
++#define RG_BUCK_VREF_SEL_I_MSK 0x7fffffff
++#define RG_BUCK_VREF_SEL_SFT 31
++#define RG_BUCK_VREF_SEL_HI 31
++#define RG_BUCK_VREF_SEL_SZ 1
++#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x000003ff
++#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xfffffc00
++#define RG_RTC_OSC_RES_SW_MANUAL_SFT 0
++#define RG_RTC_OSC_RES_SW_MANUAL_HI 9
++#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10
++#define RG_RTC_OSC_RES_SW_MSK 0x03ff0000
++#define RG_RTC_OSC_RES_SW_I_MSK 0xfc00ffff
++#define RG_RTC_OSC_RES_SW_SFT 16
++#define RG_RTC_OSC_RES_SW_HI 25
++#define RG_RTC_OSC_RES_SW_SZ 10
++#define RTC_OSC_CAL_RES_RDY_MSK 0x80000000
++#define RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff
++#define RTC_OSC_CAL_RES_RDY_SFT 31
++#define RTC_OSC_CAL_RES_RDY_HI 31
++#define RTC_OSC_CAL_RES_RDY_SZ 1
++#define RG_DCDC_MODE_MSK 0x00000001
++#define RG_DCDC_MODE_I_MSK 0xfffffffe
++#define RG_DCDC_MODE_SFT 0
++#define RG_DCDC_MODE_HI 0
++#define RG_DCDC_MODE_SZ 1
++#define RG_BUCK_EN_PSM_MSK 0x00000010
++#define RG_BUCK_EN_PSM_I_MSK 0xffffffef
++#define RG_BUCK_EN_PSM_SFT 4
++#define RG_BUCK_EN_PSM_HI 4
++#define RG_BUCK_EN_PSM_SZ 1
++#define RG_BUCK_PSM_VTH_MSK 0x00000100
++#define RG_BUCK_PSM_VTH_I_MSK 0xfffffeff
++#define RG_BUCK_PSM_VTH_SFT 8
++#define RG_BUCK_PSM_VTH_HI 8
++#define RG_BUCK_PSM_VTH_SZ 1
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00001000
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xffffefff
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 12
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 12
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
++#define RG_RTC_RDY_DEGLITCH_TIMER_MSK 0x00006000
++#define RG_RTC_RDY_DEGLITCH_TIMER_I_MSK 0xffff9fff
++#define RG_RTC_RDY_DEGLITCH_TIMER_SFT 13
++#define RG_RTC_RDY_DEGLITCH_TIMER_HI 14
++#define RG_RTC_RDY_DEGLITCH_TIMER_SZ 2
++#define RTC_CAL_ENA_MSK 0x00010000
++#define RTC_CAL_ENA_I_MSK 0xfffeffff
++#define RTC_CAL_ENA_SFT 16
++#define RTC_CAL_ENA_HI 16
++#define RTC_CAL_ENA_SZ 1
++#define PMU_WAKE_TRIG_EVENT_MSK 0x00000003
++#define PMU_WAKE_TRIG_EVENT_I_MSK 0xfffffffc
++#define PMU_WAKE_TRIG_EVENT_SFT 0
++#define PMU_WAKE_TRIG_EVENT_HI 1
++#define PMU_WAKE_TRIG_EVENT_SZ 2
++#define DIGI_TOP_POR_MASK_MSK 0x00000010
++#define DIGI_TOP_POR_MASK_I_MSK 0xffffffef
++#define DIGI_TOP_POR_MASK_SFT 4
++#define DIGI_TOP_POR_MASK_HI 4
++#define DIGI_TOP_POR_MASK_SZ 1
++#define PMU_ENTER_SLEEP_MODE_MSK 0x00000100
++#define PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffeff
++#define PMU_ENTER_SLEEP_MODE_SFT 8
++#define PMU_ENTER_SLEEP_MODE_HI 8
++#define PMU_ENTER_SLEEP_MODE_SZ 1
++#define RG_RTC_DUMMIES_MSK 0xffff0000
++#define RG_RTC_DUMMIES_I_MSK 0x0000ffff
++#define RG_RTC_DUMMIES_SFT 16
++#define RG_RTC_DUMMIES_HI 31
++#define RG_RTC_DUMMIES_SZ 16
++#define RTC_EN_MSK 0x00000001
++#define RTC_EN_I_MSK 0xfffffffe
++#define RTC_EN_SFT 0
++#define RTC_EN_HI 0
++#define RTC_EN_SZ 1
++#define RTC_SRC_MSK 0x00000002
++#define RTC_SRC_I_MSK 0xfffffffd
++#define RTC_SRC_SFT 1
++#define RTC_SRC_HI 1
++#define RTC_SRC_SZ 1
++#define RTC_TICK_CNT_MSK 0x7fff0000
++#define RTC_TICK_CNT_I_MSK 0x8000ffff
++#define RTC_TICK_CNT_SFT 16
++#define RTC_TICK_CNT_HI 30
++#define RTC_TICK_CNT_SZ 15
++#define RTC_INT_SEC_MASK_MSK 0x00000001
++#define RTC_INT_SEC_MASK_I_MSK 0xfffffffe
++#define RTC_INT_SEC_MASK_SFT 0
++#define RTC_INT_SEC_MASK_HI 0
++#define RTC_INT_SEC_MASK_SZ 1
++#define RTC_INT_ALARM_MASK_MSK 0x00000002
++#define RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
++#define RTC_INT_ALARM_MASK_SFT 1
++#define RTC_INT_ALARM_MASK_HI 1
++#define RTC_INT_ALARM_MASK_SZ 1
++#define RTC_INT_SEC_MSK 0x00010000
++#define RTC_INT_SEC_I_MSK 0xfffeffff
++#define RTC_INT_SEC_SFT 16
++#define RTC_INT_SEC_HI 16
++#define RTC_INT_SEC_SZ 1
++#define RTC_INT_ALARM_MSK 0x00020000
++#define RTC_INT_ALARM_I_MSK 0xfffdffff
++#define RTC_INT_ALARM_SFT 17
++#define RTC_INT_ALARM_HI 17
++#define RTC_INT_ALARM_SZ 1
++#define RTC_SEC_START_CNT_MSK 0xffffffff
++#define RTC_SEC_START_CNT_I_MSK 0x00000000
++#define RTC_SEC_START_CNT_SFT 0
++#define RTC_SEC_START_CNT_HI 31
++#define RTC_SEC_START_CNT_SZ 32
++#define RTC_SEC_CNT_MSK 0xffffffff
++#define RTC_SEC_CNT_I_MSK 0x00000000
++#define RTC_SEC_CNT_SFT 0
++#define RTC_SEC_CNT_HI 31
++#define RTC_SEC_CNT_SZ 32
++#define RTC_SEC_ALARM_VALUE_MSK 0xffffffff
++#define RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
++#define RTC_SEC_ALARM_VALUE_SFT 0
++#define RTC_SEC_ALARM_VALUE_HI 31
++#define RTC_SEC_ALARM_VALUE_SZ 32
++#define D2_DMA_ADR_SRC_MSK 0xffffffff
++#define D2_DMA_ADR_SRC_I_MSK 0x00000000
++#define D2_DMA_ADR_SRC_SFT 0
++#define D2_DMA_ADR_SRC_HI 31
++#define D2_DMA_ADR_SRC_SZ 32
++#define D2_DMA_ADR_DST_MSK 0xffffffff
++#define D2_DMA_ADR_DST_I_MSK 0x00000000
++#define D2_DMA_ADR_DST_SFT 0
++#define D2_DMA_ADR_DST_HI 31
++#define D2_DMA_ADR_DST_SZ 32
++#define D2_DMA_SRC_SIZE_MSK 0x00000007
++#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8
++#define D2_DMA_SRC_SIZE_SFT 0
++#define D2_DMA_SRC_SIZE_HI 2
++#define D2_DMA_SRC_SIZE_SZ 3
++#define D2_DMA_SRC_INC_MSK 0x00000008
++#define D2_DMA_SRC_INC_I_MSK 0xfffffff7
++#define D2_DMA_SRC_INC_SFT 3
++#define D2_DMA_SRC_INC_HI 3
++#define D2_DMA_SRC_INC_SZ 1
++#define D2_DMA_DST_SIZE_MSK 0x00000070
++#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f
++#define D2_DMA_DST_SIZE_SFT 4
++#define D2_DMA_DST_SIZE_HI 6
++#define D2_DMA_DST_SIZE_SZ 3
++#define D2_DMA_DST_INC_MSK 0x00000080
++#define D2_DMA_DST_INC_I_MSK 0xffffff7f
++#define D2_DMA_DST_INC_SFT 7
++#define D2_DMA_DST_INC_HI 7
++#define D2_DMA_DST_INC_SZ 1
++#define D2_DMA_FAST_FILL_MSK 0x00000100
++#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff
++#define D2_DMA_FAST_FILL_SFT 8
++#define D2_DMA_FAST_FILL_HI 8
++#define D2_DMA_FAST_FILL_SZ 1
++#define D2_DMA_SDIO_KICK_MSK 0x00001000
++#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff
++#define D2_DMA_SDIO_KICK_SFT 12
++#define D2_DMA_SDIO_KICK_HI 12
++#define D2_DMA_SDIO_KICK_SZ 1
++#define D2_DMA_BADR_EN_MSK 0x00002000
++#define D2_DMA_BADR_EN_I_MSK 0xffffdfff
++#define D2_DMA_BADR_EN_SFT 13
++#define D2_DMA_BADR_EN_HI 13
++#define D2_DMA_BADR_EN_SZ 1
++#define D2_DMA_LEN_MSK 0xffff0000
++#define D2_DMA_LEN_I_MSK 0x0000ffff
++#define D2_DMA_LEN_SFT 16
++#define D2_DMA_LEN_HI 31
++#define D2_DMA_LEN_SZ 16
++#define D2_DMA_INT_MASK_MSK 0x00000001
++#define D2_DMA_INT_MASK_I_MSK 0xfffffffe
++#define D2_DMA_INT_MASK_SFT 0
++#define D2_DMA_INT_MASK_HI 0
++#define D2_DMA_INT_MASK_SZ 1
++#define D2_DMA_STS_MSK 0x00000100
++#define D2_DMA_STS_I_MSK 0xfffffeff
++#define D2_DMA_STS_SFT 8
++#define D2_DMA_STS_HI 8
++#define D2_DMA_STS_SZ 1
++#define D2_DMA_FINISH_MSK 0x80000000
++#define D2_DMA_FINISH_I_MSK 0x7fffffff
++#define D2_DMA_FINISH_SFT 31
++#define D2_DMA_FINISH_HI 31
++#define D2_DMA_FINISH_SZ 1
++#define D2_DMA_CONST_MSK 0xffffffff
++#define D2_DMA_CONST_I_MSK 0x00000000
++#define D2_DMA_CONST_SFT 0
++#define D2_DMA_CONST_HI 31
++#define D2_DMA_CONST_SZ 32
++#define TRAP_UNKNOWN_TYPE_MSK 0x00000001
++#define TRAP_UNKNOWN_TYPE_I_MSK 0xfffffffe
++#define TRAP_UNKNOWN_TYPE_SFT 0
++#define TRAP_UNKNOWN_TYPE_HI 0
++#define TRAP_UNKNOWN_TYPE_SZ 1
++#define TX_ON_DEMAND_ENA_MSK 0x00000002
++#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd
++#define TX_ON_DEMAND_ENA_SFT 1
++#define TX_ON_DEMAND_ENA_HI 1
++#define TX_ON_DEMAND_ENA_SZ 1
++#define RX_2_HOST_MSK 0x00000004
++#define RX_2_HOST_I_MSK 0xfffffffb
++#define RX_2_HOST_SFT 2
++#define RX_2_HOST_HI 2
++#define RX_2_HOST_SZ 1
++#define AUTO_SEQNO_MSK 0x00000008
++#define AUTO_SEQNO_I_MSK 0xfffffff7
++#define AUTO_SEQNO_SFT 3
++#define AUTO_SEQNO_HI 3
++#define AUTO_SEQNO_SZ 1
++#define BYPASSS_TX_PARSER_ENCAP_MSK 0x00000010
++#define BYPASSS_TX_PARSER_ENCAP_I_MSK 0xffffffef
++#define BYPASSS_TX_PARSER_ENCAP_SFT 4
++#define BYPASSS_TX_PARSER_ENCAP_HI 4
++#define BYPASSS_TX_PARSER_ENCAP_SZ 1
++#define HDR_STRIP_MSK 0x00000020
++#define HDR_STRIP_I_MSK 0xffffffdf
++#define HDR_STRIP_SFT 5
++#define HDR_STRIP_HI 5
++#define HDR_STRIP_SZ 1
++#define ERP_PROTECT_MSK 0x000000c0
++#define ERP_PROTECT_I_MSK 0xffffff3f
++#define ERP_PROTECT_SFT 6
++#define ERP_PROTECT_HI 7
++#define ERP_PROTECT_SZ 2
++#define PRO_VER_MSK 0x00000300
++#define PRO_VER_I_MSK 0xfffffcff
++#define PRO_VER_SFT 8
++#define PRO_VER_HI 9
++#define PRO_VER_SZ 2
++#define TXQ_ID0_MSK 0x00007000
++#define TXQ_ID0_I_MSK 0xffff8fff
++#define TXQ_ID0_SFT 12
++#define TXQ_ID0_HI 14
++#define TXQ_ID0_SZ 3
++#define TXQ_ID1_MSK 0x00070000
++#define TXQ_ID1_I_MSK 0xfff8ffff
++#define TXQ_ID1_SFT 16
++#define TXQ_ID1_HI 18
++#define TXQ_ID1_SZ 3
++#define TX_ETHER_TRAP_EN_MSK 0x00100000
++#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff
++#define TX_ETHER_TRAP_EN_SFT 20
++#define TX_ETHER_TRAP_EN_HI 20
++#define TX_ETHER_TRAP_EN_SZ 1
++#define RX_ETHER_TRAP_EN_MSK 0x00200000
++#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff
++#define RX_ETHER_TRAP_EN_SFT 21
++#define RX_ETHER_TRAP_EN_HI 21
++#define RX_ETHER_TRAP_EN_SZ 1
++#define RX_NULL_TRAP_EN_MSK 0x00400000
++#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff
++#define RX_NULL_TRAP_EN_SFT 22
++#define RX_NULL_TRAP_EN_HI 22
++#define RX_NULL_TRAP_EN_SZ 1
++#define RX_GET_TX_QUEUE_EN_MSK 0x02000000
++#define RX_GET_TX_QUEUE_EN_I_MSK 0xfdffffff
++#define RX_GET_TX_QUEUE_EN_SFT 25
++#define RX_GET_TX_QUEUE_EN_HI 25
++#define RX_GET_TX_QUEUE_EN_SZ 1
++#define HCI_INQ_SEL_MSK 0x04000000
++#define HCI_INQ_SEL_I_MSK 0xfbffffff
++#define HCI_INQ_SEL_SFT 26
++#define HCI_INQ_SEL_HI 26
++#define HCI_INQ_SEL_SZ 1
++#define TRX_DEBUG_CNT_ENA_MSK 0x10000000
++#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff
++#define TRX_DEBUG_CNT_ENA_SFT 28
++#define TRX_DEBUG_CNT_ENA_HI 28
++#define TRX_DEBUG_CNT_ENA_SZ 1
++#define WAKE_SOON_WITH_SCK_MSK 0x00000001
++#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe
++#define WAKE_SOON_WITH_SCK_SFT 0
++#define WAKE_SOON_WITH_SCK_HI 0
++#define WAKE_SOON_WITH_SCK_SZ 1
++#define TX_FLOW_CTRL_MSK 0x0000ffff
++#define TX_FLOW_CTRL_I_MSK 0xffff0000
++#define TX_FLOW_CTRL_SFT 0
++#define TX_FLOW_CTRL_HI 15
++#define TX_FLOW_CTRL_SZ 16
++#define TX_FLOW_MGMT_MSK 0xffff0000
++#define TX_FLOW_MGMT_I_MSK 0x0000ffff
++#define TX_FLOW_MGMT_SFT 16
++#define TX_FLOW_MGMT_HI 31
++#define TX_FLOW_MGMT_SZ 16
++#define TX_FLOW_DATA_MSK 0xffffffff
++#define TX_FLOW_DATA_I_MSK 0x00000000
++#define TX_FLOW_DATA_SFT 0
++#define TX_FLOW_DATA_HI 31
++#define TX_FLOW_DATA_SZ 32
++#define DOT11RTSTHRESHOLD_MSK 0xffff0000
++#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff
++#define DOT11RTSTHRESHOLD_SFT 16
++#define DOT11RTSTHRESHOLD_HI 31
++#define DOT11RTSTHRESHOLD_SZ 16
++#define TXF_ID_MSK 0x0000003f
++#define TXF_ID_I_MSK 0xffffffc0
++#define TXF_ID_SFT 0
++#define TXF_ID_HI 5
++#define TXF_ID_SZ 6
++#define SEQ_CTRL_MSK 0x0000ffff
++#define SEQ_CTRL_I_MSK 0xffff0000
++#define SEQ_CTRL_SFT 0
++#define SEQ_CTRL_HI 15
++#define SEQ_CTRL_SZ 16
++#define TX_PBOFFSET_MSK 0x000000ff
++#define TX_PBOFFSET_I_MSK 0xffffff00
++#define TX_PBOFFSET_SFT 0
++#define TX_PBOFFSET_HI 7
++#define TX_PBOFFSET_SZ 8
++#define TX_INFO_SIZE_MSK 0x0000ff00
++#define TX_INFO_SIZE_I_MSK 0xffff00ff
++#define TX_INFO_SIZE_SFT 8
++#define TX_INFO_SIZE_HI 15
++#define TX_INFO_SIZE_SZ 8
++#define RX_INFO_SIZE_MSK 0x00ff0000
++#define RX_INFO_SIZE_I_MSK 0xff00ffff
++#define RX_INFO_SIZE_SFT 16
++#define RX_INFO_SIZE_HI 23
++#define RX_INFO_SIZE_SZ 8
++#define RX_LAST_PHY_SIZE_MSK 0xff000000
++#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff
++#define RX_LAST_PHY_SIZE_SFT 24
++#define RX_LAST_PHY_SIZE_HI 31
++#define RX_LAST_PHY_SIZE_SZ 8
++#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f
++#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0
++#define TX_INFO_CLEAR_SIZE_SFT 0
++#define TX_INFO_CLEAR_SIZE_HI 5
++#define TX_INFO_CLEAR_SIZE_SZ 6
++#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100
++#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff
++#define TX_INFO_CLEAR_ENABLE_SFT 8
++#define TX_INFO_CLEAR_ENABLE_HI 8
++#define TX_INFO_CLEAR_ENABLE_SZ 1
++#define TXTRAP_ETHTYPE1_MSK 0x0000ffff
++#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000
++#define TXTRAP_ETHTYPE1_SFT 0
++#define TXTRAP_ETHTYPE1_HI 15
++#define TXTRAP_ETHTYPE1_SZ 16
++#define TXTRAP_ETHTYPE0_MSK 0xffff0000
++#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff
++#define TXTRAP_ETHTYPE0_SFT 16
++#define TXTRAP_ETHTYPE0_HI 31
++#define TXTRAP_ETHTYPE0_SZ 16
++#define RXTRAP_ETHTYPE1_MSK 0x0000ffff
++#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000
++#define RXTRAP_ETHTYPE1_SFT 0
++#define RXTRAP_ETHTYPE1_HI 15
++#define RXTRAP_ETHTYPE1_SZ 16
++#define RXTRAP_ETHTYPE0_MSK 0xffff0000
++#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff
++#define RXTRAP_ETHTYPE0_SFT 16
++#define RXTRAP_ETHTYPE0_HI 31
++#define RXTRAP_ETHTYPE0_SZ 16
++#define TX_PKT_COUNTER_MSK 0xffffffff
++#define TX_PKT_COUNTER_I_MSK 0x00000000
++#define TX_PKT_COUNTER_SFT 0
++#define TX_PKT_COUNTER_HI 31
++#define TX_PKT_COUNTER_SZ 32
++#define RX_PKT_COUNTER_MSK 0xffffffff
++#define RX_PKT_COUNTER_I_MSK 0x00000000
++#define RX_PKT_COUNTER_SFT 0
++#define RX_PKT_COUNTER_HI 31
++#define RX_PKT_COUNTER_SZ 32
++#define HOST_CMD_COUNTER_MSK 0x000000ff
++#define HOST_CMD_COUNTER_I_MSK 0xffffff00
++#define HOST_CMD_COUNTER_SFT 0
++#define HOST_CMD_COUNTER_HI 7
++#define HOST_CMD_COUNTER_SZ 8
++#define HOST_EVENT_COUNTER_MSK 0x000000ff
++#define HOST_EVENT_COUNTER_I_MSK 0xffffff00
++#define HOST_EVENT_COUNTER_SFT 0
++#define HOST_EVENT_COUNTER_HI 7
++#define HOST_EVENT_COUNTER_SZ 8
++#define TX_PKT_DROP_COUNTER_MSK 0x000000ff
++#define TX_PKT_DROP_COUNTER_I_MSK 0xffffff00
++#define TX_PKT_DROP_COUNTER_SFT 0
++#define TX_PKT_DROP_COUNTER_HI 7
++#define TX_PKT_DROP_COUNTER_SZ 8
++#define RX_PKT_DROP_COUNTER_MSK 0x000000ff
++#define RX_PKT_DROP_COUNTER_I_MSK 0xffffff00
++#define RX_PKT_DROP_COUNTER_SFT 0
++#define RX_PKT_DROP_COUNTER_HI 7
++#define RX_PKT_DROP_COUNTER_SZ 8
++#define TX_PKT_TRAP_COUNTER_MSK 0x000000ff
++#define TX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
++#define TX_PKT_TRAP_COUNTER_SFT 0
++#define TX_PKT_TRAP_COUNTER_HI 7
++#define TX_PKT_TRAP_COUNTER_SZ 8
++#define RX_PKT_TRAP_COUNTER_MSK 0x000000ff
++#define RX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
++#define RX_PKT_TRAP_COUNTER_SFT 0
++#define RX_PKT_TRAP_COUNTER_HI 7
++#define RX_PKT_TRAP_COUNTER_SZ 8
++#define HOST_TX_FAIL_COUNTER_MSK 0x000000ff
++#define HOST_TX_FAIL_COUNTER_I_MSK 0xffffff00
++#define HOST_TX_FAIL_COUNTER_SFT 0
++#define HOST_TX_FAIL_COUNTER_HI 7
++#define HOST_TX_FAIL_COUNTER_SZ 8
++#define HOST_RX_FAIL_COUNTER_MSK 0x000000ff
++#define HOST_RX_FAIL_COUNTER_I_MSK 0xffffff00
++#define HOST_RX_FAIL_COUNTER_SFT 0
++#define HOST_RX_FAIL_COUNTER_HI 7
++#define HOST_RX_FAIL_COUNTER_SZ 8
++#define HCI_STATE_MONITOR_MSK 0xffffffff
++#define HCI_STATE_MONITOR_I_MSK 0x00000000
++#define HCI_STATE_MONITOR_SFT 0
++#define HCI_STATE_MONITOR_HI 31
++#define HCI_STATE_MONITOR_SZ 32
++#define HCI_ST_TIMEOUT_MONITOR_MSK 0xffffffff
++#define HCI_ST_TIMEOUT_MONITOR_I_MSK 0x00000000
++#define HCI_ST_TIMEOUT_MONITOR_SFT 0
++#define HCI_ST_TIMEOUT_MONITOR_HI 31
++#define HCI_ST_TIMEOUT_MONITOR_SZ 32
++#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff
++#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000
++#define TX_ON_DEMAND_LENGTH_SFT 0
++#define TX_ON_DEMAND_LENGTH_HI 31
++#define TX_ON_DEMAND_LENGTH_SZ 32
++#define HCI_MONITOR_REG1_MSK 0xffffffff
++#define HCI_MONITOR_REG1_I_MSK 0x00000000
++#define HCI_MONITOR_REG1_SFT 0
++#define HCI_MONITOR_REG1_HI 31
++#define HCI_MONITOR_REG1_SZ 32
++#define HCI_MONITOR_REG2_MSK 0xffffffff
++#define HCI_MONITOR_REG2_I_MSK 0x00000000
++#define HCI_MONITOR_REG2_SFT 0
++#define HCI_MONITOR_REG2_HI 31
++#define HCI_MONITOR_REG2_SZ 32
++#define HCI_TX_ALLOC_TIME_31_0_MSK 0xffffffff
++#define HCI_TX_ALLOC_TIME_31_0_I_MSK 0x00000000
++#define HCI_TX_ALLOC_TIME_31_0_SFT 0
++#define HCI_TX_ALLOC_TIME_31_0_HI 31
++#define HCI_TX_ALLOC_TIME_31_0_SZ 32
++#define HCI_TX_ALLOC_TIME_47_32_MSK 0x0000ffff
++#define HCI_TX_ALLOC_TIME_47_32_I_MSK 0xffff0000
++#define HCI_TX_ALLOC_TIME_47_32_SFT 0
++#define HCI_TX_ALLOC_TIME_47_32_HI 15
++#define HCI_TX_ALLOC_TIME_47_32_SZ 16
++#define HCI_MB_MAX_CNT_MSK 0x00ff0000
++#define HCI_MB_MAX_CNT_I_MSK 0xff00ffff
++#define HCI_MB_MAX_CNT_SFT 16
++#define HCI_MB_MAX_CNT_HI 23
++#define HCI_MB_MAX_CNT_SZ 8
++#define HCI_TX_ALLOC_CNT_31_0_MSK 0xffffffff
++#define HCI_TX_ALLOC_CNT_31_0_I_MSK 0x00000000
++#define HCI_TX_ALLOC_CNT_31_0_SFT 0
++#define HCI_TX_ALLOC_CNT_31_0_HI 31
++#define HCI_TX_ALLOC_CNT_31_0_SZ 32
++#define HCI_TX_ALLOC_CNT_47_32_MSK 0x0000ffff
++#define HCI_TX_ALLOC_CNT_47_32_I_MSK 0xffff0000
++#define HCI_TX_ALLOC_CNT_47_32_SFT 0
++#define HCI_TX_ALLOC_CNT_47_32_HI 15
++#define HCI_TX_ALLOC_CNT_47_32_SZ 16
++#define HCI_PROC_CNT_MSK 0x00ff0000
++#define HCI_PROC_CNT_I_MSK 0xff00ffff
++#define HCI_PROC_CNT_SFT 16
++#define HCI_PROC_CNT_HI 23
++#define HCI_PROC_CNT_SZ 8
++#define SDIO_TRANS_CNT_MSK 0xff000000
++#define SDIO_TRANS_CNT_I_MSK 0x00ffffff
++#define SDIO_TRANS_CNT_SFT 24
++#define SDIO_TRANS_CNT_HI 31
++#define SDIO_TRANS_CNT_SZ 8
++#define SDIO_TX_INVALID_CNT_31_0_MSK 0xffffffff
++#define SDIO_TX_INVALID_CNT_31_0_I_MSK 0x00000000
++#define SDIO_TX_INVALID_CNT_31_0_SFT 0
++#define SDIO_TX_INVALID_CNT_31_0_HI 31
++#define SDIO_TX_INVALID_CNT_31_0_SZ 32
++#define SDIO_TX_INVALID_CNT_47_32_MSK 0x0000ffff
++#define SDIO_TX_INVALID_CNT_47_32_I_MSK 0xffff0000
++#define SDIO_TX_INVALID_CNT_47_32_SFT 0
++#define SDIO_TX_INVALID_CNT_47_32_HI 15
++#define SDIO_TX_INVALID_CNT_47_32_SZ 16
++#define CS_START_ADDR_MSK 0x0000ffff
++#define CS_START_ADDR_I_MSK 0xffff0000
++#define CS_START_ADDR_SFT 0
++#define CS_START_ADDR_HI 15
++#define CS_START_ADDR_SZ 16
++#define CS_PKT_ID_MSK 0x007f0000
++#define CS_PKT_ID_I_MSK 0xff80ffff
++#define CS_PKT_ID_SFT 16
++#define CS_PKT_ID_HI 22
++#define CS_PKT_ID_SZ 7
++#define ADD_LEN_MSK 0x0000ffff
++#define ADD_LEN_I_MSK 0xffff0000
++#define ADD_LEN_SFT 0
++#define ADD_LEN_HI 15
++#define ADD_LEN_SZ 16
++#define CS_ADDER_EN_MSK 0x00000001
++#define CS_ADDER_EN_I_MSK 0xfffffffe
++#define CS_ADDER_EN_SFT 0
++#define CS_ADDER_EN_HI 0
++#define CS_ADDER_EN_SZ 1
++#define PSEUDO_MSK 0x00000002
++#define PSEUDO_I_MSK 0xfffffffd
++#define PSEUDO_SFT 1
++#define PSEUDO_HI 1
++#define PSEUDO_SZ 1
++#define CALCULATE_MSK 0xffffffff
++#define CALCULATE_I_MSK 0x00000000
++#define CALCULATE_SFT 0
++#define CALCULATE_HI 31
++#define CALCULATE_SZ 32
++#define L4_LEN_MSK 0x0000ffff
++#define L4_LEN_I_MSK 0xffff0000
++#define L4_LEN_SFT 0
++#define L4_LEN_HI 15
++#define L4_LEN_SZ 16
++#define L4_PROTOL_MSK 0x00ff0000
++#define L4_PROTOL_I_MSK 0xff00ffff
++#define L4_PROTOL_SFT 16
++#define L4_PROTOL_HI 23
++#define L4_PROTOL_SZ 8
++#define CHECK_SUM_MSK 0x0000ffff
++#define CHECK_SUM_I_MSK 0xffff0000
++#define CHECK_SUM_SFT 0
++#define CHECK_SUM_HI 15
++#define CHECK_SUM_SZ 16
++#define RAND_EN_MSK 0x00000001
++#define RAND_EN_I_MSK 0xfffffffe
++#define RAND_EN_SFT 0
++#define RAND_EN_HI 0
++#define RAND_EN_SZ 1
++#define RAND_NUM_MSK 0xffffffff
++#define RAND_NUM_I_MSK 0x00000000
++#define RAND_NUM_SFT 0
++#define RAND_NUM_HI 31
++#define RAND_NUM_SZ 32
++#define MUL_OP1_MSK 0xffffffff
++#define MUL_OP1_I_MSK 0x00000000
++#define MUL_OP1_SFT 0
++#define MUL_OP1_HI 31
++#define MUL_OP1_SZ 32
++#define MUL_OP2_MSK 0xffffffff
++#define MUL_OP2_I_MSK 0x00000000
++#define MUL_OP2_SFT 0
++#define MUL_OP2_HI 31
++#define MUL_OP2_SZ 32
++#define MUL_ANS0_MSK 0xffffffff
++#define MUL_ANS0_I_MSK 0x00000000
++#define MUL_ANS0_SFT 0
++#define MUL_ANS0_HI 31
++#define MUL_ANS0_SZ 32
++#define MUL_ANS1_MSK 0xffffffff
++#define MUL_ANS1_I_MSK 0x00000000
++#define MUL_ANS1_SFT 0
++#define MUL_ANS1_HI 31
++#define MUL_ANS1_SZ 32
++#define RD_ADDR_MSK 0x0000ffff
++#define RD_ADDR_I_MSK 0xffff0000
++#define RD_ADDR_SFT 0
++#define RD_ADDR_HI 15
++#define RD_ADDR_SZ 16
++#define RD_ID_MSK 0x007f0000
++#define RD_ID_I_MSK 0xff80ffff
++#define RD_ID_SFT 16
++#define RD_ID_HI 22
++#define RD_ID_SZ 7
++#define WR_ADDR_MSK 0x0000ffff
++#define WR_ADDR_I_MSK 0xffff0000
++#define WR_ADDR_SFT 0
++#define WR_ADDR_HI 15
++#define WR_ADDR_SZ 16
++#define WR_ID_MSK 0x007f0000
++#define WR_ID_I_MSK 0xff80ffff
++#define WR_ID_SFT 16
++#define WR_ID_HI 22
++#define WR_ID_SZ 7
++#define LEN_MSK 0x0000ffff
++#define LEN_I_MSK 0xffff0000
++#define LEN_SFT 0
++#define LEN_HI 15
++#define LEN_SZ 16
++#define CLR_MSK 0x00000001
++#define CLR_I_MSK 0xfffffffe
++#define CLR_SFT 0
++#define CLR_HI 0
++#define CLR_SZ 1
++#define PHY_MODE_MSK 0x00000003
++#define PHY_MODE_I_MSK 0xfffffffc
++#define PHY_MODE_SFT 0
++#define PHY_MODE_HI 1
++#define PHY_MODE_SZ 2
++#define SHRT_PREAM_MSK 0x00000004
++#define SHRT_PREAM_I_MSK 0xfffffffb
++#define SHRT_PREAM_SFT 2
++#define SHRT_PREAM_HI 2
++#define SHRT_PREAM_SZ 1
++#define SHRT_GI_MSK 0x00000008
++#define SHRT_GI_I_MSK 0xfffffff7
++#define SHRT_GI_SFT 3
++#define SHRT_GI_HI 3
++#define SHRT_GI_SZ 1
++#define DATA_RATE_MSK 0x000007f0
++#define DATA_RATE_I_MSK 0xfffff80f
++#define DATA_RATE_SFT 4
++#define DATA_RATE_HI 10
++#define DATA_RATE_SZ 7
++#define MCS_MSK 0x00007000
++#define MCS_I_MSK 0xffff8fff
++#define MCS_SFT 12
++#define MCS_HI 14
++#define MCS_SZ 3
++#define FRAME_LEN_MSK 0xffff0000
++#define FRAME_LEN_I_MSK 0x0000ffff
++#define FRAME_LEN_SFT 16
++#define FRAME_LEN_HI 31
++#define FRAME_LEN_SZ 16
++#define DURATION_MSK 0x0000ffff
++#define DURATION_I_MSK 0xffff0000
++#define DURATION_SFT 0
++#define DURATION_HI 15
++#define DURATION_SZ 16
++#define SHA_DST_ADDR_MSK 0xffffffff
++#define SHA_DST_ADDR_I_MSK 0x00000000
++#define SHA_DST_ADDR_SFT 0
++#define SHA_DST_ADDR_HI 31
++#define SHA_DST_ADDR_SZ 32
++#define SHA_SRC_ADDR_MSK 0xffffffff
++#define SHA_SRC_ADDR_I_MSK 0x00000000
++#define SHA_SRC_ADDR_SFT 0
++#define SHA_SRC_ADDR_HI 31
++#define SHA_SRC_ADDR_SZ 32
++#define SHA_BUSY_MSK 0x00000001
++#define SHA_BUSY_I_MSK 0xfffffffe
++#define SHA_BUSY_SFT 0
++#define SHA_BUSY_HI 0
++#define SHA_BUSY_SZ 1
++#define SHA_ENDIAN_MSK 0x00000002
++#define SHA_ENDIAN_I_MSK 0xfffffffd
++#define SHA_ENDIAN_SFT 1
++#define SHA_ENDIAN_HI 1
++#define SHA_ENDIAN_SZ 1
++#define EFS_CLKFREQ_MSK 0x00000fff
++#define EFS_CLKFREQ_I_MSK 0xfffff000
++#define EFS_CLKFREQ_SFT 0
++#define EFS_CLKFREQ_HI 11
++#define EFS_CLKFREQ_SZ 12
++#define LOW_ACTIVE_MSK 0x00010000
++#define LOW_ACTIVE_I_MSK 0xfffeffff
++#define LOW_ACTIVE_SFT 16
++#define LOW_ACTIVE_HI 16
++#define LOW_ACTIVE_SZ 1
++#define EFS_CLKFREQ_RD_MSK 0x0ff00000
++#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff
++#define EFS_CLKFREQ_RD_SFT 20
++#define EFS_CLKFREQ_RD_HI 27
++#define EFS_CLKFREQ_RD_SZ 8
++#define EFS_PRE_RD_MSK 0xf0000000
++#define EFS_PRE_RD_I_MSK 0x0fffffff
++#define EFS_PRE_RD_SFT 28
++#define EFS_PRE_RD_HI 31
++#define EFS_PRE_RD_SZ 4
++#define EFS_LDO_ON_MSK 0x0000ffff
++#define EFS_LDO_ON_I_MSK 0xffff0000
++#define EFS_LDO_ON_SFT 0
++#define EFS_LDO_ON_HI 15
++#define EFS_LDO_ON_SZ 16
++#define EFS_LDO_OFF_MSK 0xffff0000
++#define EFS_LDO_OFF_I_MSK 0x0000ffff
++#define EFS_LDO_OFF_SFT 16
++#define EFS_LDO_OFF_HI 31
++#define EFS_LDO_OFF_SZ 16
++#define EFS_RDATA_0_MSK 0xffffffff
++#define EFS_RDATA_0_I_MSK 0x00000000
++#define EFS_RDATA_0_SFT 0
++#define EFS_RDATA_0_HI 31
++#define EFS_RDATA_0_SZ 32
++#define EFS_WDATA_0_MSK 0xffffffff
++#define EFS_WDATA_0_I_MSK 0x00000000
++#define EFS_WDATA_0_SFT 0
++#define EFS_WDATA_0_HI 31
++#define EFS_WDATA_0_SZ 32
++#define EFS_RDATA_1_MSK 0xffffffff
++#define EFS_RDATA_1_I_MSK 0x00000000
++#define EFS_RDATA_1_SFT 0
++#define EFS_RDATA_1_HI 31
++#define EFS_RDATA_1_SZ 32
++#define EFS_WDATA_1_MSK 0xffffffff
++#define EFS_WDATA_1_I_MSK 0x00000000
++#define EFS_WDATA_1_SFT 0
++#define EFS_WDATA_1_HI 31
++#define EFS_WDATA_1_SZ 32
++#define EFS_RDATA_2_MSK 0xffffffff
++#define EFS_RDATA_2_I_MSK 0x00000000
++#define EFS_RDATA_2_SFT 0
++#define EFS_RDATA_2_HI 31
++#define EFS_RDATA_2_SZ 32
++#define EFS_WDATA_2_MSK 0xffffffff
++#define EFS_WDATA_2_I_MSK 0x00000000
++#define EFS_WDATA_2_SFT 0
++#define EFS_WDATA_2_HI 31
++#define EFS_WDATA_2_SZ 32
++#define EFS_RDATA_3_MSK 0xffffffff
++#define EFS_RDATA_3_I_MSK 0x00000000
++#define EFS_RDATA_3_SFT 0
++#define EFS_RDATA_3_HI 31
++#define EFS_RDATA_3_SZ 32
++#define EFS_WDATA_3_MSK 0xffffffff
++#define EFS_WDATA_3_I_MSK 0x00000000
++#define EFS_WDATA_3_SFT 0
++#define EFS_WDATA_3_HI 31
++#define EFS_WDATA_3_SZ 32
++#define EFS_RDATA_4_MSK 0xffffffff
++#define EFS_RDATA_4_I_MSK 0x00000000
++#define EFS_RDATA_4_SFT 0
++#define EFS_RDATA_4_HI 31
++#define EFS_RDATA_4_SZ 32
++#define EFS_WDATA_4_MSK 0xffffffff
++#define EFS_WDATA_4_I_MSK 0x00000000
++#define EFS_WDATA_4_SFT 0
++#define EFS_WDATA_4_HI 31
++#define EFS_WDATA_4_SZ 32
++#define EFS_RDATA_5_MSK 0xffffffff
++#define EFS_RDATA_5_I_MSK 0x00000000
++#define EFS_RDATA_5_SFT 0
++#define EFS_RDATA_5_HI 31
++#define EFS_RDATA_5_SZ 32
++#define EFS_WDATA_5_MSK 0xffffffff
++#define EFS_WDATA_5_I_MSK 0x00000000
++#define EFS_WDATA_5_SFT 0
++#define EFS_WDATA_5_HI 31
++#define EFS_WDATA_5_SZ 32
++#define EFS_RDATA_6_MSK 0xffffffff
++#define EFS_RDATA_6_I_MSK 0x00000000
++#define EFS_RDATA_6_SFT 0
++#define EFS_RDATA_6_HI 31
++#define EFS_RDATA_6_SZ 32
++#define EFS_WDATA_6_MSK 0xffffffff
++#define EFS_WDATA_6_I_MSK 0x00000000
++#define EFS_WDATA_6_SFT 0
++#define EFS_WDATA_6_HI 31
++#define EFS_WDATA_6_SZ 32
++#define EFS_RDATA_7_MSK 0xffffffff
++#define EFS_RDATA_7_I_MSK 0x00000000
++#define EFS_RDATA_7_SFT 0
++#define EFS_RDATA_7_HI 31
++#define EFS_RDATA_7_SZ 32
++#define EFS_WDATA_7_MSK 0xffffffff
++#define EFS_WDATA_7_I_MSK 0x00000000
++#define EFS_WDATA_7_SFT 0
++#define EFS_WDATA_7_HI 31
++#define EFS_WDATA_7_SZ 32
++#define EFS_SPI_RD0_EN_MSK 0x00000001
++#define EFS_SPI_RD0_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD0_EN_SFT 0
++#define EFS_SPI_RD0_EN_HI 0
++#define EFS_SPI_RD0_EN_SZ 1
++#define EFS_SPI_RD1_EN_MSK 0x00000001
++#define EFS_SPI_RD1_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD1_EN_SFT 0
++#define EFS_SPI_RD1_EN_HI 0
++#define EFS_SPI_RD1_EN_SZ 1
++#define EFS_SPI_RD2_EN_MSK 0x00000001
++#define EFS_SPI_RD2_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD2_EN_SFT 0
++#define EFS_SPI_RD2_EN_HI 0
++#define EFS_SPI_RD2_EN_SZ 1
++#define EFS_SPI_RD3_EN_MSK 0x00000001
++#define EFS_SPI_RD3_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD3_EN_SFT 0
++#define EFS_SPI_RD3_EN_HI 0
++#define EFS_SPI_RD3_EN_SZ 1
++#define EFS_SPI_RD4_EN_MSK 0x00000001
++#define EFS_SPI_RD4_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD4_EN_SFT 0
++#define EFS_SPI_RD4_EN_HI 0
++#define EFS_SPI_RD4_EN_SZ 1
++#define EFS_SPI_RD5_EN_MSK 0x00000001
++#define EFS_SPI_RD5_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD5_EN_SFT 0
++#define EFS_SPI_RD5_EN_HI 0
++#define EFS_SPI_RD5_EN_SZ 1
++#define EFS_SPI_RD6_EN_MSK 0x00000001
++#define EFS_SPI_RD6_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD6_EN_SFT 0
++#define EFS_SPI_RD6_EN_HI 0
++#define EFS_SPI_RD6_EN_SZ 1
++#define EFS_SPI_RD7_EN_MSK 0x00000001
++#define EFS_SPI_RD7_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD7_EN_SFT 0
++#define EFS_SPI_RD7_EN_HI 0
++#define EFS_SPI_RD7_EN_SZ 1
++#define EFS_SPI_RBUSY_MSK 0x00000001
++#define EFS_SPI_RBUSY_I_MSK 0xfffffffe
++#define EFS_SPI_RBUSY_SFT 0
++#define EFS_SPI_RBUSY_HI 0
++#define EFS_SPI_RBUSY_SZ 1
++#define EFS_SPI_RDATA_0_MSK 0xffffffff
++#define EFS_SPI_RDATA_0_I_MSK 0x00000000
++#define EFS_SPI_RDATA_0_SFT 0
++#define EFS_SPI_RDATA_0_HI 31
++#define EFS_SPI_RDATA_0_SZ 32
++#define EFS_SPI_RDATA_1_MSK 0xffffffff
++#define EFS_SPI_RDATA_1_I_MSK 0x00000000
++#define EFS_SPI_RDATA_1_SFT 0
++#define EFS_SPI_RDATA_1_HI 31
++#define EFS_SPI_RDATA_1_SZ 32
++#define EFS_SPI_RDATA_2_MSK 0xffffffff
++#define EFS_SPI_RDATA_2_I_MSK 0x00000000
++#define EFS_SPI_RDATA_2_SFT 0
++#define EFS_SPI_RDATA_2_HI 31
++#define EFS_SPI_RDATA_2_SZ 32
++#define EFS_SPI_RDATA_3_MSK 0xffffffff
++#define EFS_SPI_RDATA_3_I_MSK 0x00000000
++#define EFS_SPI_RDATA_3_SFT 0
++#define EFS_SPI_RDATA_3_HI 31
++#define EFS_SPI_RDATA_3_SZ 32
++#define EFS_SPI_RDATA_4_MSK 0xffffffff
++#define EFS_SPI_RDATA_4_I_MSK 0x00000000
++#define EFS_SPI_RDATA_4_SFT 0
++#define EFS_SPI_RDATA_4_HI 31
++#define EFS_SPI_RDATA_4_SZ 32
++#define EFS_SPI_RDATA_5_MSK 0xffffffff
++#define EFS_SPI_RDATA_5_I_MSK 0x00000000
++#define EFS_SPI_RDATA_5_SFT 0
++#define EFS_SPI_RDATA_5_HI 31
++#define EFS_SPI_RDATA_5_SZ 32
++#define EFS_SPI_RDATA_6_MSK 0xffffffff
++#define EFS_SPI_RDATA_6_I_MSK 0x00000000
++#define EFS_SPI_RDATA_6_SFT 0
++#define EFS_SPI_RDATA_6_HI 31
++#define EFS_SPI_RDATA_6_SZ 32
++#define EFS_SPI_RDATA_7_MSK 0xffffffff
++#define EFS_SPI_RDATA_7_I_MSK 0x00000000
++#define EFS_SPI_RDATA_7_SFT 0
++#define EFS_SPI_RDATA_7_HI 31
++#define EFS_SPI_RDATA_7_SZ 32
++#define GET_RK_MSK 0x00000001
++#define GET_RK_I_MSK 0xfffffffe
++#define GET_RK_SFT 0
++#define GET_RK_HI 0
++#define GET_RK_SZ 1
++#define FORCE_GET_RK_MSK 0x00000002
++#define FORCE_GET_RK_I_MSK 0xfffffffd
++#define FORCE_GET_RK_SFT 1
++#define FORCE_GET_RK_HI 1
++#define FORCE_GET_RK_SZ 1
++#define SMS4_DESCRY_EN_MSK 0x00000010
++#define SMS4_DESCRY_EN_I_MSK 0xffffffef
++#define SMS4_DESCRY_EN_SFT 4
++#define SMS4_DESCRY_EN_HI 4
++#define SMS4_DESCRY_EN_SZ 1
++#define DEC_DOUT_MSB_MSK 0x00000001
++#define DEC_DOUT_MSB_I_MSK 0xfffffffe
++#define DEC_DOUT_MSB_SFT 0
++#define DEC_DOUT_MSB_HI 0
++#define DEC_DOUT_MSB_SZ 1
++#define DEC_DIN_MSB_MSK 0x00000002
++#define DEC_DIN_MSB_I_MSK 0xfffffffd
++#define DEC_DIN_MSB_SFT 1
++#define DEC_DIN_MSB_HI 1
++#define DEC_DIN_MSB_SZ 1
++#define ENC_DOUT_MSB_MSK 0x00000004
++#define ENC_DOUT_MSB_I_MSK 0xfffffffb
++#define ENC_DOUT_MSB_SFT 2
++#define ENC_DOUT_MSB_HI 2
++#define ENC_DOUT_MSB_SZ 1
++#define ENC_DIN_MSB_MSK 0x00000008
++#define ENC_DIN_MSB_I_MSK 0xfffffff7
++#define ENC_DIN_MSB_SFT 3
++#define ENC_DIN_MSB_HI 3
++#define ENC_DIN_MSB_SZ 1
++#define KEY_DIN_MSB_MSK 0x00000010
++#define KEY_DIN_MSB_I_MSK 0xffffffef
++#define KEY_DIN_MSB_SFT 4
++#define KEY_DIN_MSB_HI 4
++#define KEY_DIN_MSB_SZ 1
++#define SMS4_CBC_EN_MSK 0x00000001
++#define SMS4_CBC_EN_I_MSK 0xfffffffe
++#define SMS4_CBC_EN_SFT 0
++#define SMS4_CBC_EN_HI 0
++#define SMS4_CBC_EN_SZ 1
++#define SMS4_CFB_EN_MSK 0x00000002
++#define SMS4_CFB_EN_I_MSK 0xfffffffd
++#define SMS4_CFB_EN_SFT 1
++#define SMS4_CFB_EN_HI 1
++#define SMS4_CFB_EN_SZ 1
++#define SMS4_OFB_EN_MSK 0x00000004
++#define SMS4_OFB_EN_I_MSK 0xfffffffb
++#define SMS4_OFB_EN_SFT 2
++#define SMS4_OFB_EN_HI 2
++#define SMS4_OFB_EN_SZ 1
++#define SMS4_START_TRIG_MSK 0x00000001
++#define SMS4_START_TRIG_I_MSK 0xfffffffe
++#define SMS4_START_TRIG_SFT 0
++#define SMS4_START_TRIG_HI 0
++#define SMS4_START_TRIG_SZ 1
++#define SMS4_BUSY_MSK 0x00000001
++#define SMS4_BUSY_I_MSK 0xfffffffe
++#define SMS4_BUSY_SFT 0
++#define SMS4_BUSY_HI 0
++#define SMS4_BUSY_SZ 1
++#define SMS4_DONE_MSK 0x00000001
++#define SMS4_DONE_I_MSK 0xfffffffe
++#define SMS4_DONE_SFT 0
++#define SMS4_DONE_HI 0
++#define SMS4_DONE_SZ 1
++#define SMS4_DATAIN_0_MSK 0xffffffff
++#define SMS4_DATAIN_0_I_MSK 0x00000000
++#define SMS4_DATAIN_0_SFT 0
++#define SMS4_DATAIN_0_HI 31
++#define SMS4_DATAIN_0_SZ 32
++#define SMS4_DATAIN_1_MSK 0xffffffff
++#define SMS4_DATAIN_1_I_MSK 0x00000000
++#define SMS4_DATAIN_1_SFT 0
++#define SMS4_DATAIN_1_HI 31
++#define SMS4_DATAIN_1_SZ 32
++#define SMS4_DATAIN_2_MSK 0xffffffff
++#define SMS4_DATAIN_2_I_MSK 0x00000000
++#define SMS4_DATAIN_2_SFT 0
++#define SMS4_DATAIN_2_HI 31
++#define SMS4_DATAIN_2_SZ 32
++#define SMS4_DATAIN_3_MSK 0xffffffff
++#define SMS4_DATAIN_3_I_MSK 0x00000000
++#define SMS4_DATAIN_3_SFT 0
++#define SMS4_DATAIN_3_HI 31
++#define SMS4_DATAIN_3_SZ 32
++#define SMS4_DATAOUT_0_MSK 0xffffffff
++#define SMS4_DATAOUT_0_I_MSK 0x00000000
++#define SMS4_DATAOUT_0_SFT 0
++#define SMS4_DATAOUT_0_HI 31
++#define SMS4_DATAOUT_0_SZ 32
++#define SMS4_DATAOUT_1_MSK 0xffffffff
++#define SMS4_DATAOUT_1_I_MSK 0x00000000
++#define SMS4_DATAOUT_1_SFT 0
++#define SMS4_DATAOUT_1_HI 31
++#define SMS4_DATAOUT_1_SZ 32
++#define SMS4_DATAOUT_2_MSK 0xffffffff
++#define SMS4_DATAOUT_2_I_MSK 0x00000000
++#define SMS4_DATAOUT_2_SFT 0
++#define SMS4_DATAOUT_2_HI 31
++#define SMS4_DATAOUT_2_SZ 32
++#define SMS4_DATAOUT_3_MSK 0xffffffff
++#define SMS4_DATAOUT_3_I_MSK 0x00000000
++#define SMS4_DATAOUT_3_SFT 0
++#define SMS4_DATAOUT_3_HI 31
++#define SMS4_DATAOUT_3_SZ 32
++#define SMS4_KEY_0_MSK 0xffffffff
++#define SMS4_KEY_0_I_MSK 0x00000000
++#define SMS4_KEY_0_SFT 0
++#define SMS4_KEY_0_HI 31
++#define SMS4_KEY_0_SZ 32
++#define SMS4_KEY_1_MSK 0xffffffff
++#define SMS4_KEY_1_I_MSK 0x00000000
++#define SMS4_KEY_1_SFT 0
++#define SMS4_KEY_1_HI 31
++#define SMS4_KEY_1_SZ 32
++#define SMS4_KEY_2_MSK 0xffffffff
++#define SMS4_KEY_2_I_MSK 0x00000000
++#define SMS4_KEY_2_SFT 0
++#define SMS4_KEY_2_HI 31
++#define SMS4_KEY_2_SZ 32
++#define SMS4_KEY_3_MSK 0xffffffff
++#define SMS4_KEY_3_I_MSK 0x00000000
++#define SMS4_KEY_3_SFT 0
++#define SMS4_KEY_3_HI 31
++#define SMS4_KEY_3_SZ 32
++#define SMS4_MODE_IV0_MSK 0xffffffff
++#define SMS4_MODE_IV0_I_MSK 0x00000000
++#define SMS4_MODE_IV0_SFT 0
++#define SMS4_MODE_IV0_HI 31
++#define SMS4_MODE_IV0_SZ 32
++#define SMS4_MODE_IV1_MSK 0xffffffff
++#define SMS4_MODE_IV1_I_MSK 0x00000000
++#define SMS4_MODE_IV1_SFT 0
++#define SMS4_MODE_IV1_HI 31
++#define SMS4_MODE_IV1_SZ 32
++#define SMS4_MODE_IV2_MSK 0xffffffff
++#define SMS4_MODE_IV2_I_MSK 0x00000000
++#define SMS4_MODE_IV2_SFT 0
++#define SMS4_MODE_IV2_HI 31
++#define SMS4_MODE_IV2_SZ 32
++#define SMS4_MODE_IV3_MSK 0xffffffff
++#define SMS4_MODE_IV3_I_MSK 0x00000000
++#define SMS4_MODE_IV3_SFT 0
++#define SMS4_MODE_IV3_HI 31
++#define SMS4_MODE_IV3_SZ 32
++#define SMS4_OFB_ENC0_MSK 0xffffffff
++#define SMS4_OFB_ENC0_I_MSK 0x00000000
++#define SMS4_OFB_ENC0_SFT 0
++#define SMS4_OFB_ENC0_HI 31
++#define SMS4_OFB_ENC0_SZ 32
++#define SMS4_OFB_ENC1_MSK 0xffffffff
++#define SMS4_OFB_ENC1_I_MSK 0x00000000
++#define SMS4_OFB_ENC1_SFT 0
++#define SMS4_OFB_ENC1_HI 31
++#define SMS4_OFB_ENC1_SZ 32
++#define SMS4_OFB_ENC2_MSK 0xffffffff
++#define SMS4_OFB_ENC2_I_MSK 0x00000000
++#define SMS4_OFB_ENC2_SFT 0
++#define SMS4_OFB_ENC2_HI 31
++#define SMS4_OFB_ENC2_SZ 32
++#define SMS4_OFB_ENC3_MSK 0xffffffff
++#define SMS4_OFB_ENC3_I_MSK 0x00000000
++#define SMS4_OFB_ENC3_SFT 0
++#define SMS4_OFB_ENC3_HI 31
++#define SMS4_OFB_ENC3_SZ 32
++#define MRX_MCAST_TB0_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB0_31_0_SFT 0
++#define MRX_MCAST_TB0_31_0_HI 31
++#define MRX_MCAST_TB0_31_0_SZ 32
++#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB0_47_32_SFT 0
++#define MRX_MCAST_TB0_47_32_HI 15
++#define MRX_MCAST_TB0_47_32_SZ 16
++#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK0_31_0_SFT 0
++#define MRX_MCAST_MASK0_31_0_HI 31
++#define MRX_MCAST_MASK0_31_0_SZ 32
++#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK0_47_32_SFT 0
++#define MRX_MCAST_MASK0_47_32_HI 15
++#define MRX_MCAST_MASK0_47_32_SZ 16
++#define MRX_MCAST_CTRL_0_MSK 0x00000003
++#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_0_SFT 0
++#define MRX_MCAST_CTRL_0_HI 1
++#define MRX_MCAST_CTRL_0_SZ 2
++#define MRX_MCAST_TB1_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB1_31_0_SFT 0
++#define MRX_MCAST_TB1_31_0_HI 31
++#define MRX_MCAST_TB1_31_0_SZ 32
++#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB1_47_32_SFT 0
++#define MRX_MCAST_TB1_47_32_HI 15
++#define MRX_MCAST_TB1_47_32_SZ 16
++#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK1_31_0_SFT 0
++#define MRX_MCAST_MASK1_31_0_HI 31
++#define MRX_MCAST_MASK1_31_0_SZ 32
++#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK1_47_32_SFT 0
++#define MRX_MCAST_MASK1_47_32_HI 15
++#define MRX_MCAST_MASK1_47_32_SZ 16
++#define MRX_MCAST_CTRL_1_MSK 0x00000003
++#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_1_SFT 0
++#define MRX_MCAST_CTRL_1_HI 1
++#define MRX_MCAST_CTRL_1_SZ 2
++#define MRX_MCAST_TB2_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB2_31_0_SFT 0
++#define MRX_MCAST_TB2_31_0_HI 31
++#define MRX_MCAST_TB2_31_0_SZ 32
++#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB2_47_32_SFT 0
++#define MRX_MCAST_TB2_47_32_HI 15
++#define MRX_MCAST_TB2_47_32_SZ 16
++#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK2_31_0_SFT 0
++#define MRX_MCAST_MASK2_31_0_HI 31
++#define MRX_MCAST_MASK2_31_0_SZ 32
++#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK2_47_32_SFT 0
++#define MRX_MCAST_MASK2_47_32_HI 15
++#define MRX_MCAST_MASK2_47_32_SZ 16
++#define MRX_MCAST_CTRL_2_MSK 0x00000003
++#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_2_SFT 0
++#define MRX_MCAST_CTRL_2_HI 1
++#define MRX_MCAST_CTRL_2_SZ 2
++#define MRX_MCAST_TB3_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB3_31_0_SFT 0
++#define MRX_MCAST_TB3_31_0_HI 31
++#define MRX_MCAST_TB3_31_0_SZ 32
++#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB3_47_32_SFT 0
++#define MRX_MCAST_TB3_47_32_HI 15
++#define MRX_MCAST_TB3_47_32_SZ 16
++#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK3_31_0_SFT 0
++#define MRX_MCAST_MASK3_31_0_HI 31
++#define MRX_MCAST_MASK3_31_0_SZ 32
++#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK3_47_32_SFT 0
++#define MRX_MCAST_MASK3_47_32_HI 15
++#define MRX_MCAST_MASK3_47_32_SZ 16
++#define MRX_MCAST_CTRL_3_MSK 0x00000003
++#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_3_SFT 0
++#define MRX_MCAST_CTRL_3_HI 1
++#define MRX_MCAST_CTRL_3_SZ 2
++#define MRX_PHY_INFO_MSK 0xffffffff
++#define MRX_PHY_INFO_I_MSK 0x00000000
++#define MRX_PHY_INFO_SFT 0
++#define MRX_PHY_INFO_HI 31
++#define MRX_PHY_INFO_SZ 32
++#define DBG_BA_TYPE_MSK 0x0000003f
++#define DBG_BA_TYPE_I_MSK 0xffffffc0
++#define DBG_BA_TYPE_SFT 0
++#define DBG_BA_TYPE_HI 5
++#define DBG_BA_TYPE_SZ 6
++#define DBG_BA_SEQ_MSK 0x000fff00
++#define DBG_BA_SEQ_I_MSK 0xfff000ff
++#define DBG_BA_SEQ_SFT 8
++#define DBG_BA_SEQ_HI 19
++#define DBG_BA_SEQ_SZ 12
++#define MRX_FLT_TB0_MSK 0x00007fff
++#define MRX_FLT_TB0_I_MSK 0xffff8000
++#define MRX_FLT_TB0_SFT 0
++#define MRX_FLT_TB0_HI 14
++#define MRX_FLT_TB0_SZ 15
++#define MRX_FLT_TB1_MSK 0x00007fff
++#define MRX_FLT_TB1_I_MSK 0xffff8000
++#define MRX_FLT_TB1_SFT 0
++#define MRX_FLT_TB1_HI 14
++#define MRX_FLT_TB1_SZ 15
++#define MRX_FLT_TB2_MSK 0x00007fff
++#define MRX_FLT_TB2_I_MSK 0xffff8000
++#define MRX_FLT_TB2_SFT 0
++#define MRX_FLT_TB2_HI 14
++#define MRX_FLT_TB2_SZ 15
++#define MRX_FLT_TB3_MSK 0x00007fff
++#define MRX_FLT_TB3_I_MSK 0xffff8000
++#define MRX_FLT_TB3_SFT 0
++#define MRX_FLT_TB3_HI 14
++#define MRX_FLT_TB3_SZ 15
++#define MRX_FLT_TB4_MSK 0x00007fff
++#define MRX_FLT_TB4_I_MSK 0xffff8000
++#define MRX_FLT_TB4_SFT 0
++#define MRX_FLT_TB4_HI 14
++#define MRX_FLT_TB4_SZ 15
++#define MRX_FLT_TB5_MSK 0x00007fff
++#define MRX_FLT_TB5_I_MSK 0xffff8000
++#define MRX_FLT_TB5_SFT 0
++#define MRX_FLT_TB5_HI 14
++#define MRX_FLT_TB5_SZ 15
++#define MRX_FLT_TB6_MSK 0x00007fff
++#define MRX_FLT_TB6_I_MSK 0xffff8000
++#define MRX_FLT_TB6_SFT 0
++#define MRX_FLT_TB6_HI 14
++#define MRX_FLT_TB6_SZ 15
++#define MRX_FLT_TB7_MSK 0x00007fff
++#define MRX_FLT_TB7_I_MSK 0xffff8000
++#define MRX_FLT_TB7_SFT 0
++#define MRX_FLT_TB7_HI 14
++#define MRX_FLT_TB7_SZ 15
++#define MRX_FLT_TB8_MSK 0x00007fff
++#define MRX_FLT_TB8_I_MSK 0xffff8000
++#define MRX_FLT_TB8_SFT 0
++#define MRX_FLT_TB8_HI 14
++#define MRX_FLT_TB8_SZ 15
++#define MRX_FLT_TB9_MSK 0x00007fff
++#define MRX_FLT_TB9_I_MSK 0xffff8000
++#define MRX_FLT_TB9_SFT 0
++#define MRX_FLT_TB9_HI 14
++#define MRX_FLT_TB9_SZ 15
++#define MRX_FLT_TB10_MSK 0x00007fff
++#define MRX_FLT_TB10_I_MSK 0xffff8000
++#define MRX_FLT_TB10_SFT 0
++#define MRX_FLT_TB10_HI 14
++#define MRX_FLT_TB10_SZ 15
++#define MRX_FLT_TB11_MSK 0x00007fff
++#define MRX_FLT_TB11_I_MSK 0xffff8000
++#define MRX_FLT_TB11_SFT 0
++#define MRX_FLT_TB11_HI 14
++#define MRX_FLT_TB11_SZ 15
++#define MRX_FLT_TB12_MSK 0x00007fff
++#define MRX_FLT_TB12_I_MSK 0xffff8000
++#define MRX_FLT_TB12_SFT 0
++#define MRX_FLT_TB12_HI 14
++#define MRX_FLT_TB12_SZ 15
++#define MRX_FLT_TB13_MSK 0x00007fff
++#define MRX_FLT_TB13_I_MSK 0xffff8000
++#define MRX_FLT_TB13_SFT 0
++#define MRX_FLT_TB13_HI 14
++#define MRX_FLT_TB13_SZ 15
++#define MRX_FLT_TB14_MSK 0x00007fff
++#define MRX_FLT_TB14_I_MSK 0xffff8000
++#define MRX_FLT_TB14_SFT 0
++#define MRX_FLT_TB14_HI 14
++#define MRX_FLT_TB14_SZ 15
++#define MRX_FLT_TB15_MSK 0x00007fff
++#define MRX_FLT_TB15_I_MSK 0xffff8000
++#define MRX_FLT_TB15_SFT 0
++#define MRX_FLT_TB15_HI 14
++#define MRX_FLT_TB15_SZ 15
++#define MRX_FLT_EN0_MSK 0x0000ffff
++#define MRX_FLT_EN0_I_MSK 0xffff0000
++#define MRX_FLT_EN0_SFT 0
++#define MRX_FLT_EN0_HI 15
++#define MRX_FLT_EN0_SZ 16
++#define MRX_FLT_EN1_MSK 0x0000ffff
++#define MRX_FLT_EN1_I_MSK 0xffff0000
++#define MRX_FLT_EN1_SFT 0
++#define MRX_FLT_EN1_HI 15
++#define MRX_FLT_EN1_SZ 16
++#define MRX_FLT_EN2_MSK 0x0000ffff
++#define MRX_FLT_EN2_I_MSK 0xffff0000
++#define MRX_FLT_EN2_SFT 0
++#define MRX_FLT_EN2_HI 15
++#define MRX_FLT_EN2_SZ 16
++#define MRX_FLT_EN3_MSK 0x0000ffff
++#define MRX_FLT_EN3_I_MSK 0xffff0000
++#define MRX_FLT_EN3_SFT 0
++#define MRX_FLT_EN3_HI 15
++#define MRX_FLT_EN3_SZ 16
++#define MRX_FLT_EN4_MSK 0x0000ffff
++#define MRX_FLT_EN4_I_MSK 0xffff0000
++#define MRX_FLT_EN4_SFT 0
++#define MRX_FLT_EN4_HI 15
++#define MRX_FLT_EN4_SZ 16
++#define MRX_FLT_EN5_MSK 0x0000ffff
++#define MRX_FLT_EN5_I_MSK 0xffff0000
++#define MRX_FLT_EN5_SFT 0
++#define MRX_FLT_EN5_HI 15
++#define MRX_FLT_EN5_SZ 16
++#define MRX_FLT_EN6_MSK 0x0000ffff
++#define MRX_FLT_EN6_I_MSK 0xffff0000
++#define MRX_FLT_EN6_SFT 0
++#define MRX_FLT_EN6_HI 15
++#define MRX_FLT_EN6_SZ 16
++#define MRX_FLT_EN7_MSK 0x0000ffff
++#define MRX_FLT_EN7_I_MSK 0xffff0000
++#define MRX_FLT_EN7_SFT 0
++#define MRX_FLT_EN7_HI 15
++#define MRX_FLT_EN7_SZ 16
++#define MRX_FLT_EN8_MSK 0x0000ffff
++#define MRX_FLT_EN8_I_MSK 0xffff0000
++#define MRX_FLT_EN8_SFT 0
++#define MRX_FLT_EN8_HI 15
++#define MRX_FLT_EN8_SZ 16
++#define MRX_LEN_FLT_MSK 0x0000ffff
++#define MRX_LEN_FLT_I_MSK 0xffff0000
++#define MRX_LEN_FLT_SFT 0
++#define MRX_LEN_FLT_HI 15
++#define MRX_LEN_FLT_SZ 16
++#define RX_FLOW_DATA_MSK 0xffffffff
++#define RX_FLOW_DATA_I_MSK 0x00000000
++#define RX_FLOW_DATA_SFT 0
++#define RX_FLOW_DATA_HI 31
++#define RX_FLOW_DATA_SZ 32
++#define RX_FLOW_MNG_MSK 0x0000ffff
++#define RX_FLOW_MNG_I_MSK 0xffff0000
++#define RX_FLOW_MNG_SFT 0
++#define RX_FLOW_MNG_HI 15
++#define RX_FLOW_MNG_SZ 16
++#define RX_FLOW_CTRL_MSK 0x0000ffff
++#define RX_FLOW_CTRL_I_MSK 0xffff0000
++#define RX_FLOW_CTRL_SFT 0
++#define RX_FLOW_CTRL_HI 15
++#define RX_FLOW_CTRL_SZ 16
++#define MRX_STP_EN_MSK 0x00000001
++#define MRX_STP_EN_I_MSK 0xfffffffe
++#define MRX_STP_EN_SFT 0
++#define MRX_STP_EN_HI 0
++#define MRX_STP_EN_SZ 1
++#define MRX_STP_OFST_MSK 0x0000ff00
++#define MRX_STP_OFST_I_MSK 0xffff00ff
++#define MRX_STP_OFST_SFT 8
++#define MRX_STP_OFST_HI 15
++#define MRX_STP_OFST_SZ 8
++#define DBG_FF_FULL_MSK 0x0000ffff
++#define DBG_FF_FULL_I_MSK 0xffff0000
++#define DBG_FF_FULL_SFT 0
++#define DBG_FF_FULL_HI 15
++#define DBG_FF_FULL_SZ 16
++#define DBG_FF_FULL_CLR_MSK 0x80000000
++#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff
++#define DBG_FF_FULL_CLR_SFT 31
++#define DBG_FF_FULL_CLR_HI 31
++#define DBG_FF_FULL_CLR_SZ 1
++#define DBG_WFF_FULL_MSK 0x0000ffff
++#define DBG_WFF_FULL_I_MSK 0xffff0000
++#define DBG_WFF_FULL_SFT 0
++#define DBG_WFF_FULL_HI 15
++#define DBG_WFF_FULL_SZ 16
++#define DBG_WFF_FULL_CLR_MSK 0x80000000
++#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff
++#define DBG_WFF_FULL_CLR_SFT 31
++#define DBG_WFF_FULL_CLR_HI 31
++#define DBG_WFF_FULL_CLR_SZ 1
++#define DBG_MB_FULL_MSK 0x0000ffff
++#define DBG_MB_FULL_I_MSK 0xffff0000
++#define DBG_MB_FULL_SFT 0
++#define DBG_MB_FULL_HI 15
++#define DBG_MB_FULL_SZ 16
++#define DBG_MB_FULL_CLR_MSK 0x80000000
++#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff
++#define DBG_MB_FULL_CLR_SFT 31
++#define DBG_MB_FULL_CLR_HI 31
++#define DBG_MB_FULL_CLR_SZ 1
++#define BA_CTRL_MSK 0x00000003
++#define BA_CTRL_I_MSK 0xfffffffc
++#define BA_CTRL_SFT 0
++#define BA_CTRL_HI 1
++#define BA_CTRL_SZ 2
++#define BA_DBG_EN_MSK 0x00000004
++#define BA_DBG_EN_I_MSK 0xfffffffb
++#define BA_DBG_EN_SFT 2
++#define BA_DBG_EN_HI 2
++#define BA_DBG_EN_SZ 1
++#define BA_AGRE_EN_MSK 0x00000008
++#define BA_AGRE_EN_I_MSK 0xfffffff7
++#define BA_AGRE_EN_SFT 3
++#define BA_AGRE_EN_HI 3
++#define BA_AGRE_EN_SZ 1
++#define BA_TA_31_0_MSK 0xffffffff
++#define BA_TA_31_0_I_MSK 0x00000000
++#define BA_TA_31_0_SFT 0
++#define BA_TA_31_0_HI 31
++#define BA_TA_31_0_SZ 32
++#define BA_TA_47_32_MSK 0x0000ffff
++#define BA_TA_47_32_I_MSK 0xffff0000
++#define BA_TA_47_32_SFT 0
++#define BA_TA_47_32_HI 15
++#define BA_TA_47_32_SZ 16
++#define BA_TID_MSK 0x0000000f
++#define BA_TID_I_MSK 0xfffffff0
++#define BA_TID_SFT 0
++#define BA_TID_HI 3
++#define BA_TID_SZ 4
++#define BA_ST_SEQ_MSK 0x00000fff
++#define BA_ST_SEQ_I_MSK 0xfffff000
++#define BA_ST_SEQ_SFT 0
++#define BA_ST_SEQ_HI 11
++#define BA_ST_SEQ_SZ 12
++#define BA_SB0_MSK 0xffffffff
++#define BA_SB0_I_MSK 0x00000000
++#define BA_SB0_SFT 0
++#define BA_SB0_HI 31
++#define BA_SB0_SZ 32
++#define BA_SB1_MSK 0xffffffff
++#define BA_SB1_I_MSK 0x00000000
++#define BA_SB1_SFT 0
++#define BA_SB1_HI 31
++#define BA_SB1_SZ 32
++#define MRX_WD_MSK 0x0001ffff
++#define MRX_WD_I_MSK 0xfffe0000
++#define MRX_WD_SFT 0
++#define MRX_WD_HI 16
++#define MRX_WD_SZ 17
++#define ACK_GEN_EN_MSK 0x00000001
++#define ACK_GEN_EN_I_MSK 0xfffffffe
++#define ACK_GEN_EN_SFT 0
++#define ACK_GEN_EN_HI 0
++#define ACK_GEN_EN_SZ 1
++#define BA_GEN_EN_MSK 0x00000002
++#define BA_GEN_EN_I_MSK 0xfffffffd
++#define BA_GEN_EN_SFT 1
++#define BA_GEN_EN_HI 1
++#define BA_GEN_EN_SZ 1
++#define ACK_GEN_DUR_MSK 0x0000ffff
++#define ACK_GEN_DUR_I_MSK 0xffff0000
++#define ACK_GEN_DUR_SFT 0
++#define ACK_GEN_DUR_HI 15
++#define ACK_GEN_DUR_SZ 16
++#define ACK_GEN_INFO_MSK 0x003f0000
++#define ACK_GEN_INFO_I_MSK 0xffc0ffff
++#define ACK_GEN_INFO_SFT 16
++#define ACK_GEN_INFO_HI 21
++#define ACK_GEN_INFO_SZ 6
++#define ACK_GEN_RA_31_0_MSK 0xffffffff
++#define ACK_GEN_RA_31_0_I_MSK 0x00000000
++#define ACK_GEN_RA_31_0_SFT 0
++#define ACK_GEN_RA_31_0_HI 31
++#define ACK_GEN_RA_31_0_SZ 32
++#define ACK_GEN_RA_47_32_MSK 0x0000ffff
++#define ACK_GEN_RA_47_32_I_MSK 0xffff0000
++#define ACK_GEN_RA_47_32_SFT 0
++#define ACK_GEN_RA_47_32_HI 15
++#define ACK_GEN_RA_47_32_SZ 16
++#define MIB_LEN_FAIL_MSK 0x0000ffff
++#define MIB_LEN_FAIL_I_MSK 0xffff0000
++#define MIB_LEN_FAIL_SFT 0
++#define MIB_LEN_FAIL_HI 15
++#define MIB_LEN_FAIL_SZ 16
++#define TRAP_HW_ID_MSK 0x0000000f
++#define TRAP_HW_ID_I_MSK 0xfffffff0
++#define TRAP_HW_ID_SFT 0
++#define TRAP_HW_ID_HI 3
++#define TRAP_HW_ID_SZ 4
++#define ID_IN_USE_MSK 0x000000ff
++#define ID_IN_USE_I_MSK 0xffffff00
++#define ID_IN_USE_SFT 0
++#define ID_IN_USE_HI 7
++#define ID_IN_USE_SZ 8
++#define MRX_ERR_MSK 0xffffffff
++#define MRX_ERR_I_MSK 0x00000000
++#define MRX_ERR_SFT 0
++#define MRX_ERR_HI 31
++#define MRX_ERR_SZ 32
++#define W0_T0_SEQ_MSK 0x0000ffff
++#define W0_T0_SEQ_I_MSK 0xffff0000
++#define W0_T0_SEQ_SFT 0
++#define W0_T0_SEQ_HI 15
++#define W0_T0_SEQ_SZ 16
++#define W0_T1_SEQ_MSK 0x0000ffff
++#define W0_T1_SEQ_I_MSK 0xffff0000
++#define W0_T1_SEQ_SFT 0
++#define W0_T1_SEQ_HI 15
++#define W0_T1_SEQ_SZ 16
++#define W0_T2_SEQ_MSK 0x0000ffff
++#define W0_T2_SEQ_I_MSK 0xffff0000
++#define W0_T2_SEQ_SFT 0
++#define W0_T2_SEQ_HI 15
++#define W0_T2_SEQ_SZ 16
++#define W0_T3_SEQ_MSK 0x0000ffff
++#define W0_T3_SEQ_I_MSK 0xffff0000
++#define W0_T3_SEQ_SFT 0
++#define W0_T3_SEQ_HI 15
++#define W0_T3_SEQ_SZ 16
++#define W0_T4_SEQ_MSK 0x0000ffff
++#define W0_T4_SEQ_I_MSK 0xffff0000
++#define W0_T4_SEQ_SFT 0
++#define W0_T4_SEQ_HI 15
++#define W0_T4_SEQ_SZ 16
++#define W0_T5_SEQ_MSK 0x0000ffff
++#define W0_T5_SEQ_I_MSK 0xffff0000
++#define W0_T5_SEQ_SFT 0
++#define W0_T5_SEQ_HI 15
++#define W0_T5_SEQ_SZ 16
++#define W0_T6_SEQ_MSK 0x0000ffff
++#define W0_T6_SEQ_I_MSK 0xffff0000
++#define W0_T6_SEQ_SFT 0
++#define W0_T6_SEQ_HI 15
++#define W0_T6_SEQ_SZ 16
++#define W0_T7_SEQ_MSK 0x0000ffff
++#define W0_T7_SEQ_I_MSK 0xffff0000
++#define W0_T7_SEQ_SFT 0
++#define W0_T7_SEQ_HI 15
++#define W0_T7_SEQ_SZ 16
++#define W1_T0_SEQ_MSK 0x0000ffff
++#define W1_T0_SEQ_I_MSK 0xffff0000
++#define W1_T0_SEQ_SFT 0
++#define W1_T0_SEQ_HI 15
++#define W1_T0_SEQ_SZ 16
++#define W1_T1_SEQ_MSK 0x0000ffff
++#define W1_T1_SEQ_I_MSK 0xffff0000
++#define W1_T1_SEQ_SFT 0
++#define W1_T1_SEQ_HI 15
++#define W1_T1_SEQ_SZ 16
++#define W1_T2_SEQ_MSK 0x0000ffff
++#define W1_T2_SEQ_I_MSK 0xffff0000
++#define W1_T2_SEQ_SFT 0
++#define W1_T2_SEQ_HI 15
++#define W1_T2_SEQ_SZ 16
++#define W1_T3_SEQ_MSK 0x0000ffff
++#define W1_T3_SEQ_I_MSK 0xffff0000
++#define W1_T3_SEQ_SFT 0
++#define W1_T3_SEQ_HI 15
++#define W1_T3_SEQ_SZ 16
++#define W1_T4_SEQ_MSK 0x0000ffff
++#define W1_T4_SEQ_I_MSK 0xffff0000
++#define W1_T4_SEQ_SFT 0
++#define W1_T4_SEQ_HI 15
++#define W1_T4_SEQ_SZ 16
++#define W1_T5_SEQ_MSK 0x0000ffff
++#define W1_T5_SEQ_I_MSK 0xffff0000
++#define W1_T5_SEQ_SFT 0
++#define W1_T5_SEQ_HI 15
++#define W1_T5_SEQ_SZ 16
++#define W1_T6_SEQ_MSK 0x0000ffff
++#define W1_T6_SEQ_I_MSK 0xffff0000
++#define W1_T6_SEQ_SFT 0
++#define W1_T6_SEQ_HI 15
++#define W1_T6_SEQ_SZ 16
++#define W1_T7_SEQ_MSK 0x0000ffff
++#define W1_T7_SEQ_I_MSK 0xffff0000
++#define W1_T7_SEQ_SFT 0
++#define W1_T7_SEQ_HI 15
++#define W1_T7_SEQ_SZ 16
++#define ADDR1A_SEL_MSK 0x00000003
++#define ADDR1A_SEL_I_MSK 0xfffffffc
++#define ADDR1A_SEL_SFT 0
++#define ADDR1A_SEL_HI 1
++#define ADDR1A_SEL_SZ 2
++#define ADDR2A_SEL_MSK 0x0000000c
++#define ADDR2A_SEL_I_MSK 0xfffffff3
++#define ADDR2A_SEL_SFT 2
++#define ADDR2A_SEL_HI 3
++#define ADDR2A_SEL_SZ 2
++#define ADDR3A_SEL_MSK 0x00000030
++#define ADDR3A_SEL_I_MSK 0xffffffcf
++#define ADDR3A_SEL_SFT 4
++#define ADDR3A_SEL_HI 5
++#define ADDR3A_SEL_SZ 2
++#define ADDR1B_SEL_MSK 0x000000c0
++#define ADDR1B_SEL_I_MSK 0xffffff3f
++#define ADDR1B_SEL_SFT 6
++#define ADDR1B_SEL_HI 7
++#define ADDR1B_SEL_SZ 2
++#define ADDR2B_SEL_MSK 0x00000300
++#define ADDR2B_SEL_I_MSK 0xfffffcff
++#define ADDR2B_SEL_SFT 8
++#define ADDR2B_SEL_HI 9
++#define ADDR2B_SEL_SZ 2
++#define ADDR3B_SEL_MSK 0x00000c00
++#define ADDR3B_SEL_I_MSK 0xfffff3ff
++#define ADDR3B_SEL_SFT 10
++#define ADDR3B_SEL_HI 11
++#define ADDR3B_SEL_SZ 2
++#define ADDR3C_SEL_MSK 0x00003000
++#define ADDR3C_SEL_I_MSK 0xffffcfff
++#define ADDR3C_SEL_SFT 12
++#define ADDR3C_SEL_HI 13
++#define ADDR3C_SEL_SZ 2
++#define FRM_CTRL_MSK 0x0000003f
++#define FRM_CTRL_I_MSK 0xffffffc0
++#define FRM_CTRL_SFT 0
++#define FRM_CTRL_HI 5
++#define FRM_CTRL_SZ 6
++#define CSR_PHY_INFO_MSK 0x00007fff
++#define CSR_PHY_INFO_I_MSK 0xffff8000
++#define CSR_PHY_INFO_SFT 0
++#define CSR_PHY_INFO_HI 14
++#define CSR_PHY_INFO_SZ 15
++#define AMPDU_SIG_MSK 0x000000ff
++#define AMPDU_SIG_I_MSK 0xffffff00
++#define AMPDU_SIG_SFT 0
++#define AMPDU_SIG_HI 7
++#define AMPDU_SIG_SZ 8
++#define MIB_AMPDU_MSK 0xffffffff
++#define MIB_AMPDU_I_MSK 0x00000000
++#define MIB_AMPDU_SFT 0
++#define MIB_AMPDU_HI 31
++#define MIB_AMPDU_SZ 32
++#define LEN_FLT_MSK 0x0000ffff
++#define LEN_FLT_I_MSK 0xffff0000
++#define LEN_FLT_SFT 0
++#define LEN_FLT_HI 15
++#define LEN_FLT_SZ 16
++#define MIB_DELIMITER_MSK 0x0000ffff
++#define MIB_DELIMITER_I_MSK 0xffff0000
++#define MIB_DELIMITER_SFT 0
++#define MIB_DELIMITER_HI 15
++#define MIB_DELIMITER_SZ 16
++#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000
++#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
++#define MTX_INT_Q0_Q_EMPTY_SFT 16
++#define MTX_INT_Q0_Q_EMPTY_HI 16
++#define MTX_INT_Q0_Q_EMPTY_SZ 1
++#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
++#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
++#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17
++#define MTX_INT_Q0_TXOP_RUNOUT_HI 17
++#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000
++#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
++#define MTX_INT_Q1_Q_EMPTY_SFT 18
++#define MTX_INT_Q1_Q_EMPTY_HI 18
++#define MTX_INT_Q1_Q_EMPTY_SZ 1
++#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
++#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
++#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19
++#define MTX_INT_Q1_TXOP_RUNOUT_HI 19
++#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000
++#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
++#define MTX_INT_Q2_Q_EMPTY_SFT 20
++#define MTX_INT_Q2_Q_EMPTY_HI 20
++#define MTX_INT_Q2_Q_EMPTY_SZ 1
++#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
++#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
++#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21
++#define MTX_INT_Q2_TXOP_RUNOUT_HI 21
++#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000
++#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
++#define MTX_INT_Q3_Q_EMPTY_SFT 22
++#define MTX_INT_Q3_Q_EMPTY_HI 22
++#define MTX_INT_Q3_Q_EMPTY_SZ 1
++#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
++#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
++#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23
++#define MTX_INT_Q3_TXOP_RUNOUT_HI 23
++#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000
++#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
++#define MTX_INT_Q4_Q_EMPTY_SFT 24
++#define MTX_INT_Q4_Q_EMPTY_HI 24
++#define MTX_INT_Q4_Q_EMPTY_SZ 1
++#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
++#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
++#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25
++#define MTX_INT_Q4_TXOP_RUNOUT_HI 25
++#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000
++#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
++#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16
++#define MTX_EN_INT_Q0_Q_EMPTY_HI 16
++#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000
++#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
++#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18
++#define MTX_EN_INT_Q1_Q_EMPTY_HI 18
++#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000
++#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
++#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20
++#define MTX_EN_INT_Q2_Q_EMPTY_HI 20
++#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000
++#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
++#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22
++#define MTX_EN_INT_Q3_Q_EMPTY_HI 22
++#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000
++#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
++#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24
++#define MTX_EN_INT_Q4_Q_EMPTY_HI 24
++#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1
++#define MTX_MTX2PHY_SLOW_MSK 0x00000001
++#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe
++#define MTX_MTX2PHY_SLOW_SFT 0
++#define MTX_MTX2PHY_SLOW_HI 0
++#define MTX_MTX2PHY_SLOW_SZ 1
++#define MTX_M2M_SLOW_PRD_MSK 0x0000000e
++#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1
++#define MTX_M2M_SLOW_PRD_SFT 1
++#define MTX_M2M_SLOW_PRD_HI 3
++#define MTX_M2M_SLOW_PRD_SZ 3
++#define MTX_AMPDU_CRC_AUTO_MSK 0x00000020
++#define MTX_AMPDU_CRC_AUTO_I_MSK 0xffffffdf
++#define MTX_AMPDU_CRC_AUTO_SFT 5
++#define MTX_AMPDU_CRC_AUTO_HI 5
++#define MTX_AMPDU_CRC_AUTO_SZ 1
++#define MTX_FAST_RSP_MODE_MSK 0x00000040
++#define MTX_FAST_RSP_MODE_I_MSK 0xffffffbf
++#define MTX_FAST_RSP_MODE_SFT 6
++#define MTX_FAST_RSP_MODE_HI 6
++#define MTX_FAST_RSP_MODE_SZ 1
++#define MTX_RAW_DATA_MODE_MSK 0x00000080
++#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f
++#define MTX_RAW_DATA_MODE_SFT 7
++#define MTX_RAW_DATA_MODE_HI 7
++#define MTX_RAW_DATA_MODE_SZ 1
++#define MTX_ACK_DUR0_MSK 0x00000100
++#define MTX_ACK_DUR0_I_MSK 0xfffffeff
++#define MTX_ACK_DUR0_SFT 8
++#define MTX_ACK_DUR0_HI 8
++#define MTX_ACK_DUR0_SZ 1
++#define MTX_TSF_AUTO_BCN_MSK 0x00000400
++#define MTX_TSF_AUTO_BCN_I_MSK 0xfffffbff
++#define MTX_TSF_AUTO_BCN_SFT 10
++#define MTX_TSF_AUTO_BCN_HI 10
++#define MTX_TSF_AUTO_BCN_SZ 1
++#define MTX_TSF_AUTO_MISC_MSK 0x00000800
++#define MTX_TSF_AUTO_MISC_I_MSK 0xfffff7ff
++#define MTX_TSF_AUTO_MISC_SFT 11
++#define MTX_TSF_AUTO_MISC_HI 11
++#define MTX_TSF_AUTO_MISC_SZ 1
++#define MTX_FORCE_CS_IDLE_MSK 0x00001000
++#define MTX_FORCE_CS_IDLE_I_MSK 0xffffefff
++#define MTX_FORCE_CS_IDLE_SFT 12
++#define MTX_FORCE_CS_IDLE_HI 12
++#define MTX_FORCE_CS_IDLE_SZ 1
++#define MTX_FORCE_BKF_RXEN0_MSK 0x00002000
++#define MTX_FORCE_BKF_RXEN0_I_MSK 0xffffdfff
++#define MTX_FORCE_BKF_RXEN0_SFT 13
++#define MTX_FORCE_BKF_RXEN0_HI 13
++#define MTX_FORCE_BKF_RXEN0_SZ 1
++#define MTX_FORCE_DMA_RXEN0_MSK 0x00004000
++#define MTX_FORCE_DMA_RXEN0_I_MSK 0xffffbfff
++#define MTX_FORCE_DMA_RXEN0_SFT 14
++#define MTX_FORCE_DMA_RXEN0_HI 14
++#define MTX_FORCE_DMA_RXEN0_SZ 1
++#define MTX_FORCE_RXEN0_MSK 0x00008000
++#define MTX_FORCE_RXEN0_I_MSK 0xffff7fff
++#define MTX_FORCE_RXEN0_SFT 15
++#define MTX_FORCE_RXEN0_HI 15
++#define MTX_FORCE_RXEN0_SZ 1
++#define MTX_HALT_Q_MB_MSK 0x003f0000
++#define MTX_HALT_Q_MB_I_MSK 0xffc0ffff
++#define MTX_HALT_Q_MB_SFT 16
++#define MTX_HALT_Q_MB_HI 21
++#define MTX_HALT_Q_MB_SZ 6
++#define MTX_CTS_SET_DIF_MSK 0x00400000
++#define MTX_CTS_SET_DIF_I_MSK 0xffbfffff
++#define MTX_CTS_SET_DIF_SFT 22
++#define MTX_CTS_SET_DIF_HI 22
++#define MTX_CTS_SET_DIF_SZ 1
++#define MTX_AMPDU_SET_DIF_MSK 0x00800000
++#define MTX_AMPDU_SET_DIF_I_MSK 0xff7fffff
++#define MTX_AMPDU_SET_DIF_SFT 23
++#define MTX_AMPDU_SET_DIF_HI 23
++#define MTX_AMPDU_SET_DIF_SZ 1
++#define MTX_EDCCA_TOUT_MSK 0x000003ff
++#define MTX_EDCCA_TOUT_I_MSK 0xfffffc00
++#define MTX_EDCCA_TOUT_SFT 0
++#define MTX_EDCCA_TOUT_HI 9
++#define MTX_EDCCA_TOUT_SZ 10
++#define MTX_INT_BCN_MSK 0x00000002
++#define MTX_INT_BCN_I_MSK 0xfffffffd
++#define MTX_INT_BCN_SFT 1
++#define MTX_INT_BCN_HI 1
++#define MTX_INT_BCN_SZ 1
++#define MTX_INT_DTIM_MSK 0x00000008
++#define MTX_INT_DTIM_I_MSK 0xfffffff7
++#define MTX_INT_DTIM_SFT 3
++#define MTX_INT_DTIM_HI 3
++#define MTX_INT_DTIM_SZ 1
++#define MTX_EN_INT_BCN_MSK 0x00000002
++#define MTX_EN_INT_BCN_I_MSK 0xfffffffd
++#define MTX_EN_INT_BCN_SFT 1
++#define MTX_EN_INT_BCN_HI 1
++#define MTX_EN_INT_BCN_SZ 1
++#define MTX_EN_INT_DTIM_MSK 0x00000008
++#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7
++#define MTX_EN_INT_DTIM_SFT 3
++#define MTX_EN_INT_DTIM_HI 3
++#define MTX_EN_INT_DTIM_SZ 1
++#define MTX_BCN_TIMER_EN_MSK 0x00000001
++#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe
++#define MTX_BCN_TIMER_EN_SFT 0
++#define MTX_BCN_TIMER_EN_HI 0
++#define MTX_BCN_TIMER_EN_SZ 1
++#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002
++#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd
++#define MTX_TIME_STAMP_AUTO_FILL_SFT 1
++#define MTX_TIME_STAMP_AUTO_FILL_HI 1
++#define MTX_TIME_STAMP_AUTO_FILL_SZ 1
++#define MTX_TSF_TIMER_EN_MSK 0x00000020
++#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf
++#define MTX_TSF_TIMER_EN_SFT 5
++#define MTX_TSF_TIMER_EN_HI 5
++#define MTX_TSF_TIMER_EN_SZ 1
++#define MTX_HALT_MNG_UNTIL_DTIM_MSK 0x00000040
++#define MTX_HALT_MNG_UNTIL_DTIM_I_MSK 0xffffffbf
++#define MTX_HALT_MNG_UNTIL_DTIM_SFT 6
++#define MTX_HALT_MNG_UNTIL_DTIM_HI 6
++#define MTX_HALT_MNG_UNTIL_DTIM_SZ 1
++#define MTX_INT_DTIM_NUM_MSK 0x0000ff00
++#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff
++#define MTX_INT_DTIM_NUM_SFT 8
++#define MTX_INT_DTIM_NUM_HI 15
++#define MTX_INT_DTIM_NUM_SZ 8
++#define MTX_AUTO_FLUSH_Q4_MSK 0x00010000
++#define MTX_AUTO_FLUSH_Q4_I_MSK 0xfffeffff
++#define MTX_AUTO_FLUSH_Q4_SFT 16
++#define MTX_AUTO_FLUSH_Q4_HI 16
++#define MTX_AUTO_FLUSH_Q4_SZ 1
++#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001
++#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe
++#define MTX_BCN_PKTID_CH_LOCK_SFT 0
++#define MTX_BCN_PKTID_CH_LOCK_HI 0
++#define MTX_BCN_PKTID_CH_LOCK_SZ 1
++#define MTX_BCN_CFG_VLD_MSK 0x00000006
++#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9
++#define MTX_BCN_CFG_VLD_SFT 1
++#define MTX_BCN_CFG_VLD_HI 2
++#define MTX_BCN_CFG_VLD_SZ 2
++#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008
++#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7
++#define MTX_AUTO_BCN_ONGOING_SFT 3
++#define MTX_AUTO_BCN_ONGOING_HI 3
++#define MTX_AUTO_BCN_ONGOING_SZ 1
++#define MTX_BCN_TIMER_MSK 0xffff0000
++#define MTX_BCN_TIMER_I_MSK 0x0000ffff
++#define MTX_BCN_TIMER_SFT 16
++#define MTX_BCN_TIMER_HI 31
++#define MTX_BCN_TIMER_SZ 16
++#define MTX_BCN_PERIOD_MSK 0x0000ffff
++#define MTX_BCN_PERIOD_I_MSK 0xffff0000
++#define MTX_BCN_PERIOD_SFT 0
++#define MTX_BCN_PERIOD_HI 15
++#define MTX_BCN_PERIOD_SZ 16
++#define MTX_DTIM_NUM_MSK 0xff000000
++#define MTX_DTIM_NUM_I_MSK 0x00ffffff
++#define MTX_DTIM_NUM_SFT 24
++#define MTX_DTIM_NUM_HI 31
++#define MTX_DTIM_NUM_SZ 8
++#define MTX_BCN_TSF_L_MSK 0xffffffff
++#define MTX_BCN_TSF_L_I_MSK 0x00000000
++#define MTX_BCN_TSF_L_SFT 0
++#define MTX_BCN_TSF_L_HI 31
++#define MTX_BCN_TSF_L_SZ 32
++#define MTX_BCN_TSF_U_MSK 0xffffffff
++#define MTX_BCN_TSF_U_I_MSK 0x00000000
++#define MTX_BCN_TSF_U_SFT 0
++#define MTX_BCN_TSF_U_HI 31
++#define MTX_BCN_TSF_U_SZ 32
++#define MTX_BCN_PKT_ID0_MSK 0x0000007f
++#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80
++#define MTX_BCN_PKT_ID0_SFT 0
++#define MTX_BCN_PKT_ID0_HI 6
++#define MTX_BCN_PKT_ID0_SZ 7
++#define MTX_DTIM_OFST0_MSK 0x03ff0000
++#define MTX_DTIM_OFST0_I_MSK 0xfc00ffff
++#define MTX_DTIM_OFST0_SFT 16
++#define MTX_DTIM_OFST0_HI 25
++#define MTX_DTIM_OFST0_SZ 10
++#define MTX_BCN_PKT_ID1_MSK 0x0000007f
++#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80
++#define MTX_BCN_PKT_ID1_SFT 0
++#define MTX_BCN_PKT_ID1_HI 6
++#define MTX_BCN_PKT_ID1_SZ 7
++#define MTX_DTIM_OFST1_MSK 0x03ff0000
++#define MTX_DTIM_OFST1_I_MSK 0xfc00ffff
++#define MTX_DTIM_OFST1_SFT 16
++#define MTX_DTIM_OFST1_HI 25
++#define MTX_DTIM_OFST1_SZ 10
++#define MTX_CCA_MSK 0x00000001
++#define MTX_CCA_I_MSK 0xfffffffe
++#define MTX_CCA_SFT 0
++#define MTX_CCA_HI 0
++#define MTX_CCA_SZ 1
++#define MRX_CCA_MSK 0x00000002
++#define MRX_CCA_I_MSK 0xfffffffd
++#define MRX_CCA_SFT 1
++#define MRX_CCA_HI 1
++#define MRX_CCA_SZ 1
++#define MTX_DMA_FSM_MSK 0x0000001c
++#define MTX_DMA_FSM_I_MSK 0xffffffe3
++#define MTX_DMA_FSM_SFT 2
++#define MTX_DMA_FSM_HI 4
++#define MTX_DMA_FSM_SZ 3
++#define CH_ST_FSM_MSK 0x000000e0
++#define CH_ST_FSM_I_MSK 0xffffff1f
++#define CH_ST_FSM_SFT 5
++#define CH_ST_FSM_HI 7
++#define CH_ST_FSM_SZ 3
++#define MTX_GNT_LOCK_MSK 0x00000100
++#define MTX_GNT_LOCK_I_MSK 0xfffffeff
++#define MTX_GNT_LOCK_SFT 8
++#define MTX_GNT_LOCK_HI 8
++#define MTX_GNT_LOCK_SZ 1
++#define MTX_DMA_REQ_MSK 0x00000200
++#define MTX_DMA_REQ_I_MSK 0xfffffdff
++#define MTX_DMA_REQ_SFT 9
++#define MTX_DMA_REQ_HI 9
++#define MTX_DMA_REQ_SZ 1
++#define MTX_Q_REQ_MSK 0x00000400
++#define MTX_Q_REQ_I_MSK 0xfffffbff
++#define MTX_Q_REQ_SFT 10
++#define MTX_Q_REQ_HI 10
++#define MTX_Q_REQ_SZ 1
++#define MTX_TX_EN_MSK 0x00000800
++#define MTX_TX_EN_I_MSK 0xfffff7ff
++#define MTX_TX_EN_SFT 11
++#define MTX_TX_EN_HI 11
++#define MTX_TX_EN_SZ 1
++#define MRX_RX_EN_MSK 0x00001000
++#define MRX_RX_EN_I_MSK 0xffffefff
++#define MRX_RX_EN_SFT 12
++#define MRX_RX_EN_HI 12
++#define MRX_RX_EN_SZ 1
++#define DBG_PRTC_PRD_MSK 0x00002000
++#define DBG_PRTC_PRD_I_MSK 0xffffdfff
++#define DBG_PRTC_PRD_SFT 13
++#define DBG_PRTC_PRD_HI 13
++#define DBG_PRTC_PRD_SZ 1
++#define DBG_DMA_RDY_MSK 0x00004000
++#define DBG_DMA_RDY_I_MSK 0xffffbfff
++#define DBG_DMA_RDY_SFT 14
++#define DBG_DMA_RDY_HI 14
++#define DBG_DMA_RDY_SZ 1
++#define DBG_WAIT_RSP_MSK 0x00008000
++#define DBG_WAIT_RSP_I_MSK 0xffff7fff
++#define DBG_WAIT_RSP_SFT 15
++#define DBG_WAIT_RSP_HI 15
++#define DBG_WAIT_RSP_SZ 1
++#define DBG_CFRM_BUSY_MSK 0x00010000
++#define DBG_CFRM_BUSY_I_MSK 0xfffeffff
++#define DBG_CFRM_BUSY_SFT 16
++#define DBG_CFRM_BUSY_HI 16
++#define DBG_CFRM_BUSY_SZ 1
++#define DBG_RST_MSK 0x00000001
++#define DBG_RST_I_MSK 0xfffffffe
++#define DBG_RST_SFT 0
++#define DBG_RST_HI 0
++#define DBG_RST_SZ 1
++#define DBG_MODE_MSK 0x00000002
++#define DBG_MODE_I_MSK 0xfffffffd
++#define DBG_MODE_SFT 1
++#define DBG_MODE_HI 1
++#define DBG_MODE_SZ 1
++#define MB_REQ_DUR_MSK 0x0000ffff
++#define MB_REQ_DUR_I_MSK 0xffff0000
++#define MB_REQ_DUR_SFT 0
++#define MB_REQ_DUR_HI 15
++#define MB_REQ_DUR_SZ 16
++#define RX_EN_DUR_MSK 0xffff0000
++#define RX_EN_DUR_I_MSK 0x0000ffff
++#define RX_EN_DUR_SFT 16
++#define RX_EN_DUR_HI 31
++#define RX_EN_DUR_SZ 16
++#define RX_CS_DUR_MSK 0x0000ffff
++#define RX_CS_DUR_I_MSK 0xffff0000
++#define RX_CS_DUR_SFT 0
++#define RX_CS_DUR_HI 15
++#define RX_CS_DUR_SZ 16
++#define TX_CCA_DUR_MSK 0xffff0000
++#define TX_CCA_DUR_I_MSK 0x0000ffff
++#define TX_CCA_DUR_SFT 16
++#define TX_CCA_DUR_HI 31
++#define TX_CCA_DUR_SZ 16
++#define Q_REQ_DUR_MSK 0x0000ffff
++#define Q_REQ_DUR_I_MSK 0xffff0000
++#define Q_REQ_DUR_SFT 0
++#define Q_REQ_DUR_HI 15
++#define Q_REQ_DUR_SZ 16
++#define CH_STA0_DUR_MSK 0xffff0000
++#define CH_STA0_DUR_I_MSK 0x0000ffff
++#define CH_STA0_DUR_SFT 16
++#define CH_STA0_DUR_HI 31
++#define CH_STA0_DUR_SZ 16
++#define MTX_DUR_RSP_TOUT_B_MSK 0x000000ff
++#define MTX_DUR_RSP_TOUT_B_I_MSK 0xffffff00
++#define MTX_DUR_RSP_TOUT_B_SFT 0
++#define MTX_DUR_RSP_TOUT_B_HI 7
++#define MTX_DUR_RSP_TOUT_B_SZ 8
++#define MTX_DUR_RSP_TOUT_G_MSK 0x0000ff00
++#define MTX_DUR_RSP_TOUT_G_I_MSK 0xffff00ff
++#define MTX_DUR_RSP_TOUT_G_SFT 8
++#define MTX_DUR_RSP_TOUT_G_HI 15
++#define MTX_DUR_RSP_TOUT_G_SZ 8
++#define MTX_DUR_RSP_SIFS_MSK 0x000000ff
++#define MTX_DUR_RSP_SIFS_I_MSK 0xffffff00
++#define MTX_DUR_RSP_SIFS_SFT 0
++#define MTX_DUR_RSP_SIFS_HI 7
++#define MTX_DUR_RSP_SIFS_SZ 8
++#define MTX_DUR_BURST_SIFS_MSK 0x0000ff00
++#define MTX_DUR_BURST_SIFS_I_MSK 0xffff00ff
++#define MTX_DUR_BURST_SIFS_SFT 8
++#define MTX_DUR_BURST_SIFS_HI 15
++#define MTX_DUR_BURST_SIFS_SZ 8
++#define MTX_DUR_SLOT_MSK 0x003f0000
++#define MTX_DUR_SLOT_I_MSK 0xffc0ffff
++#define MTX_DUR_SLOT_SFT 16
++#define MTX_DUR_SLOT_HI 21
++#define MTX_DUR_SLOT_SZ 6
++#define MTX_DUR_RSP_EIFS_MSK 0xffc00000
++#define MTX_DUR_RSP_EIFS_I_MSK 0x003fffff
++#define MTX_DUR_RSP_EIFS_SFT 22
++#define MTX_DUR_RSP_EIFS_HI 31
++#define MTX_DUR_RSP_EIFS_SZ 10
++#define MTX_DUR_RSP_SIFS_G_MSK 0x000000ff
++#define MTX_DUR_RSP_SIFS_G_I_MSK 0xffffff00
++#define MTX_DUR_RSP_SIFS_G_SFT 0
++#define MTX_DUR_RSP_SIFS_G_HI 7
++#define MTX_DUR_RSP_SIFS_G_SZ 8
++#define MTX_DUR_BURST_SIFS_G_MSK 0x0000ff00
++#define MTX_DUR_BURST_SIFS_G_I_MSK 0xffff00ff
++#define MTX_DUR_BURST_SIFS_G_SFT 8
++#define MTX_DUR_BURST_SIFS_G_HI 15
++#define MTX_DUR_BURST_SIFS_G_SZ 8
++#define MTX_DUR_SLOT_G_MSK 0x003f0000
++#define MTX_DUR_SLOT_G_I_MSK 0xffc0ffff
++#define MTX_DUR_SLOT_G_SFT 16
++#define MTX_DUR_SLOT_G_HI 21
++#define MTX_DUR_SLOT_G_SZ 6
++#define MTX_DUR_RSP_EIFS_G_MSK 0xffc00000
++#define MTX_DUR_RSP_EIFS_G_I_MSK 0x003fffff
++#define MTX_DUR_RSP_EIFS_G_SFT 22
++#define MTX_DUR_RSP_EIFS_G_HI 31
++#define MTX_DUR_RSP_EIFS_G_SZ 10
++#define CH_STA1_DUR_MSK 0x0000ffff
++#define CH_STA1_DUR_I_MSK 0xffff0000
++#define CH_STA1_DUR_SFT 0
++#define CH_STA1_DUR_HI 15
++#define CH_STA1_DUR_SZ 16
++#define CH_STA2_DUR_MSK 0xffff0000
++#define CH_STA2_DUR_I_MSK 0x0000ffff
++#define CH_STA2_DUR_SFT 16
++#define CH_STA2_DUR_HI 31
++#define CH_STA2_DUR_SZ 16
++#define MTX_NAV_MSK 0x0000ffff
++#define MTX_NAV_I_MSK 0xffff0000
++#define MTX_NAV_SFT 0
++#define MTX_NAV_HI 15
++#define MTX_NAV_SZ 16
++#define MTX_MIB_CNT0_MSK 0x3fffffff
++#define MTX_MIB_CNT0_I_MSK 0xc0000000
++#define MTX_MIB_CNT0_SFT 0
++#define MTX_MIB_CNT0_HI 29
++#define MTX_MIB_CNT0_SZ 30
++#define MTX_MIB_EN0_MSK 0x40000000
++#define MTX_MIB_EN0_I_MSK 0xbfffffff
++#define MTX_MIB_EN0_SFT 30
++#define MTX_MIB_EN0_HI 30
++#define MTX_MIB_EN0_SZ 1
++#define MTX_MIB_CNT1_MSK 0x3fffffff
++#define MTX_MIB_CNT1_I_MSK 0xc0000000
++#define MTX_MIB_CNT1_SFT 0
++#define MTX_MIB_CNT1_HI 29
++#define MTX_MIB_CNT1_SZ 30
++#define MTX_MIB_EN1_MSK 0x40000000
++#define MTX_MIB_EN1_I_MSK 0xbfffffff
++#define MTX_MIB_EN1_SFT 30
++#define MTX_MIB_EN1_HI 30
++#define MTX_MIB_EN1_SZ 1
++#define CH_STA3_DUR_MSK 0x0000ffff
++#define CH_STA3_DUR_I_MSK 0xffff0000
++#define CH_STA3_DUR_SFT 0
++#define CH_STA3_DUR_HI 15
++#define CH_STA3_DUR_SZ 16
++#define CH_STA4_DUR_MSK 0xffff0000
++#define CH_STA4_DUR_I_MSK 0x0000ffff
++#define CH_STA4_DUR_SFT 16
++#define CH_STA4_DUR_HI 31
++#define CH_STA4_DUR_SZ 16
++#define TXQ0_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ0_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ0_MTX_Q_PRE_LD_SFT 1
++#define TXQ0_MTX_Q_PRE_LD_HI 1
++#define TXQ0_MTX_Q_PRE_LD_SZ 1
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ0_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ0_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ0_MTX_Q_RND_MODE_SFT 6
++#define TXQ0_MTX_Q_RND_MODE_HI 7
++#define TXQ0_MTX_Q_RND_MODE_SZ 2
++#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ0_MTX_Q_AIFSN_SFT 0
++#define TXQ0_MTX_Q_AIFSN_HI 3
++#define TXQ0_MTX_Q_AIFSN_SZ 4
++#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ0_MTX_Q_ECWMIN_SFT 8
++#define TXQ0_MTX_Q_ECWMIN_HI 11
++#define TXQ0_MTX_Q_ECWMIN_SZ 4
++#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ0_MTX_Q_ECWMAX_SFT 12
++#define TXQ0_MTX_Q_ECWMAX_HI 15
++#define TXQ0_MTX_Q_ECWMAX_SZ 4
++#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ0_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ0_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ0_MTX_Q_BKF_CNT_SFT 0
++#define TXQ0_MTX_Q_BKF_CNT_HI 15
++#define TXQ0_MTX_Q_BKF_CNT_SZ 16
++#define TXQ0_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ0_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ0_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ0_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ0_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ0_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ0_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ0_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ0_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ0_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ0_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ0_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ0_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ0_MTX_Q_ID_MAP_L_HI 31
++#define TXQ0_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ0_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ0_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ0_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ0_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ0_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ0_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ0_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ0_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ0_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ0_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ1_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ1_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ1_MTX_Q_PRE_LD_SFT 1
++#define TXQ1_MTX_Q_PRE_LD_HI 1
++#define TXQ1_MTX_Q_PRE_LD_SZ 1
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ1_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ1_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ1_MTX_Q_RND_MODE_SFT 6
++#define TXQ1_MTX_Q_RND_MODE_HI 7
++#define TXQ1_MTX_Q_RND_MODE_SZ 2
++#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ1_MTX_Q_AIFSN_SFT 0
++#define TXQ1_MTX_Q_AIFSN_HI 3
++#define TXQ1_MTX_Q_AIFSN_SZ 4
++#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ1_MTX_Q_ECWMIN_SFT 8
++#define TXQ1_MTX_Q_ECWMIN_HI 11
++#define TXQ1_MTX_Q_ECWMIN_SZ 4
++#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ1_MTX_Q_ECWMAX_SFT 12
++#define TXQ1_MTX_Q_ECWMAX_HI 15
++#define TXQ1_MTX_Q_ECWMAX_SZ 4
++#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ1_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ1_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ1_MTX_Q_BKF_CNT_SFT 0
++#define TXQ1_MTX_Q_BKF_CNT_HI 15
++#define TXQ1_MTX_Q_BKF_CNT_SZ 16
++#define TXQ1_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ1_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ1_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ1_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ1_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ1_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ1_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ1_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ1_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ1_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ1_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ1_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ1_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ1_MTX_Q_ID_MAP_L_HI 31
++#define TXQ1_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ1_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ1_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ1_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ1_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ1_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ1_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ1_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ1_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ1_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ1_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ2_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ2_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ2_MTX_Q_PRE_LD_SFT 1
++#define TXQ2_MTX_Q_PRE_LD_HI 1
++#define TXQ2_MTX_Q_PRE_LD_SZ 1
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ2_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ2_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ2_MTX_Q_RND_MODE_SFT 6
++#define TXQ2_MTX_Q_RND_MODE_HI 7
++#define TXQ2_MTX_Q_RND_MODE_SZ 2
++#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ2_MTX_Q_AIFSN_SFT 0
++#define TXQ2_MTX_Q_AIFSN_HI 3
++#define TXQ2_MTX_Q_AIFSN_SZ 4
++#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ2_MTX_Q_ECWMIN_SFT 8
++#define TXQ2_MTX_Q_ECWMIN_HI 11
++#define TXQ2_MTX_Q_ECWMIN_SZ 4
++#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ2_MTX_Q_ECWMAX_SFT 12
++#define TXQ2_MTX_Q_ECWMAX_HI 15
++#define TXQ2_MTX_Q_ECWMAX_SZ 4
++#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ2_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ2_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ2_MTX_Q_BKF_CNT_SFT 0
++#define TXQ2_MTX_Q_BKF_CNT_HI 15
++#define TXQ2_MTX_Q_BKF_CNT_SZ 16
++#define TXQ2_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ2_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ2_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ2_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ2_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ2_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ2_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ2_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ2_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ2_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ2_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ2_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ2_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ2_MTX_Q_ID_MAP_L_HI 31
++#define TXQ2_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ2_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ2_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ2_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ2_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ2_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ2_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ2_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ2_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ2_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ2_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ3_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ3_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ3_MTX_Q_PRE_LD_SFT 1
++#define TXQ3_MTX_Q_PRE_LD_HI 1
++#define TXQ3_MTX_Q_PRE_LD_SZ 1
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ3_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ3_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ3_MTX_Q_RND_MODE_SFT 6
++#define TXQ3_MTX_Q_RND_MODE_HI 7
++#define TXQ3_MTX_Q_RND_MODE_SZ 2
++#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ3_MTX_Q_AIFSN_SFT 0
++#define TXQ3_MTX_Q_AIFSN_HI 3
++#define TXQ3_MTX_Q_AIFSN_SZ 4
++#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ3_MTX_Q_ECWMIN_SFT 8
++#define TXQ3_MTX_Q_ECWMIN_HI 11
++#define TXQ3_MTX_Q_ECWMIN_SZ 4
++#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ3_MTX_Q_ECWMAX_SFT 12
++#define TXQ3_MTX_Q_ECWMAX_HI 15
++#define TXQ3_MTX_Q_ECWMAX_SZ 4
++#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ3_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ3_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ3_MTX_Q_BKF_CNT_SFT 0
++#define TXQ3_MTX_Q_BKF_CNT_HI 15
++#define TXQ3_MTX_Q_BKF_CNT_SZ 16
++#define TXQ3_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ3_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ3_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ3_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ3_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ3_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ3_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ3_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ3_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ3_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ3_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ3_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ3_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ3_MTX_Q_ID_MAP_L_HI 31
++#define TXQ3_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ3_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ3_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ3_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ3_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ3_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ3_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ3_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ3_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ3_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ3_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ4_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ4_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ4_MTX_Q_PRE_LD_SFT 1
++#define TXQ4_MTX_Q_PRE_LD_HI 1
++#define TXQ4_MTX_Q_PRE_LD_SZ 1
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ4_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ4_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ4_MTX_Q_RND_MODE_SFT 6
++#define TXQ4_MTX_Q_RND_MODE_HI 7
++#define TXQ4_MTX_Q_RND_MODE_SZ 2
++#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ4_MTX_Q_AIFSN_SFT 0
++#define TXQ4_MTX_Q_AIFSN_HI 3
++#define TXQ4_MTX_Q_AIFSN_SZ 4
++#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ4_MTX_Q_ECWMIN_SFT 8
++#define TXQ4_MTX_Q_ECWMIN_HI 11
++#define TXQ4_MTX_Q_ECWMIN_SZ 4
++#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ4_MTX_Q_ECWMAX_SFT 12
++#define TXQ4_MTX_Q_ECWMAX_HI 15
++#define TXQ4_MTX_Q_ECWMAX_SZ 4
++#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ4_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ4_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ4_MTX_Q_BKF_CNT_SFT 0
++#define TXQ4_MTX_Q_BKF_CNT_HI 15
++#define TXQ4_MTX_Q_BKF_CNT_SZ 16
++#define TXQ4_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ4_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ4_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ4_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ4_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ4_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ4_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ4_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ4_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ4_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ4_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ4_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ4_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ4_MTX_Q_ID_MAP_L_HI 31
++#define TXQ4_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ4_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ4_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ4_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ4_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ4_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ4_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ4_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ4_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ4_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ4_MTX_Q_TXOP_OV_THD_SZ 16
++#define VALID0_MSK 0x00000001
++#define VALID0_I_MSK 0xfffffffe
++#define VALID0_SFT 0
++#define VALID0_HI 0
++#define VALID0_SZ 1
++#define PEER_QOS_EN0_MSK 0x00000002
++#define PEER_QOS_EN0_I_MSK 0xfffffffd
++#define PEER_QOS_EN0_SFT 1
++#define PEER_QOS_EN0_HI 1
++#define PEER_QOS_EN0_SZ 1
++#define PEER_OP_MODE0_MSK 0x0000000c
++#define PEER_OP_MODE0_I_MSK 0xfffffff3
++#define PEER_OP_MODE0_SFT 2
++#define PEER_OP_MODE0_HI 3
++#define PEER_OP_MODE0_SZ 2
++#define PEER_HT_MODE0_MSK 0x00000030
++#define PEER_HT_MODE0_I_MSK 0xffffffcf
++#define PEER_HT_MODE0_SFT 4
++#define PEER_HT_MODE0_HI 5
++#define PEER_HT_MODE0_SZ 2
++#define PEER_MAC0_31_0_MSK 0xffffffff
++#define PEER_MAC0_31_0_I_MSK 0x00000000
++#define PEER_MAC0_31_0_SFT 0
++#define PEER_MAC0_31_0_HI 31
++#define PEER_MAC0_31_0_SZ 32
++#define PEER_MAC0_47_32_MSK 0x0000ffff
++#define PEER_MAC0_47_32_I_MSK 0xffff0000
++#define PEER_MAC0_47_32_SFT 0
++#define PEER_MAC0_47_32_HI 15
++#define PEER_MAC0_47_32_SZ 16
++#define TX_ACK_POLICY_0_0_MSK 0x00000003
++#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_0_SFT 0
++#define TX_ACK_POLICY_0_0_HI 1
++#define TX_ACK_POLICY_0_0_SZ 2
++#define TX_SEQ_CTRL_0_0_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_0_SFT 0
++#define TX_SEQ_CTRL_0_0_HI 11
++#define TX_SEQ_CTRL_0_0_SZ 12
++#define TX_ACK_POLICY_0_1_MSK 0x00000003
++#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_1_SFT 0
++#define TX_ACK_POLICY_0_1_HI 1
++#define TX_ACK_POLICY_0_1_SZ 2
++#define TX_SEQ_CTRL_0_1_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_1_SFT 0
++#define TX_SEQ_CTRL_0_1_HI 11
++#define TX_SEQ_CTRL_0_1_SZ 12
++#define TX_ACK_POLICY_0_2_MSK 0x00000003
++#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_2_SFT 0
++#define TX_ACK_POLICY_0_2_HI 1
++#define TX_ACK_POLICY_0_2_SZ 2
++#define TX_SEQ_CTRL_0_2_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_2_SFT 0
++#define TX_SEQ_CTRL_0_2_HI 11
++#define TX_SEQ_CTRL_0_2_SZ 12
++#define TX_ACK_POLICY_0_3_MSK 0x00000003
++#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_3_SFT 0
++#define TX_ACK_POLICY_0_3_HI 1
++#define TX_ACK_POLICY_0_3_SZ 2
++#define TX_SEQ_CTRL_0_3_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_3_SFT 0
++#define TX_SEQ_CTRL_0_3_HI 11
++#define TX_SEQ_CTRL_0_3_SZ 12
++#define TX_ACK_POLICY_0_4_MSK 0x00000003
++#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_4_SFT 0
++#define TX_ACK_POLICY_0_4_HI 1
++#define TX_ACK_POLICY_0_4_SZ 2
++#define TX_SEQ_CTRL_0_4_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_4_SFT 0
++#define TX_SEQ_CTRL_0_4_HI 11
++#define TX_SEQ_CTRL_0_4_SZ 12
++#define TX_ACK_POLICY_0_5_MSK 0x00000003
++#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_5_SFT 0
++#define TX_ACK_POLICY_0_5_HI 1
++#define TX_ACK_POLICY_0_5_SZ 2
++#define TX_SEQ_CTRL_0_5_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_5_SFT 0
++#define TX_SEQ_CTRL_0_5_HI 11
++#define TX_SEQ_CTRL_0_5_SZ 12
++#define TX_ACK_POLICY_0_6_MSK 0x00000003
++#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_6_SFT 0
++#define TX_ACK_POLICY_0_6_HI 1
++#define TX_ACK_POLICY_0_6_SZ 2
++#define TX_SEQ_CTRL_0_6_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_6_SFT 0
++#define TX_SEQ_CTRL_0_6_HI 11
++#define TX_SEQ_CTRL_0_6_SZ 12
++#define TX_ACK_POLICY_0_7_MSK 0x00000003
++#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_7_SFT 0
++#define TX_ACK_POLICY_0_7_HI 1
++#define TX_ACK_POLICY_0_7_SZ 2
++#define TX_SEQ_CTRL_0_7_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_7_SFT 0
++#define TX_SEQ_CTRL_0_7_HI 11
++#define TX_SEQ_CTRL_0_7_SZ 12
++#define VALID1_MSK 0x00000001
++#define VALID1_I_MSK 0xfffffffe
++#define VALID1_SFT 0
++#define VALID1_HI 0
++#define VALID1_SZ 1
++#define PEER_QOS_EN1_MSK 0x00000002
++#define PEER_QOS_EN1_I_MSK 0xfffffffd
++#define PEER_QOS_EN1_SFT 1
++#define PEER_QOS_EN1_HI 1
++#define PEER_QOS_EN1_SZ 1
++#define PEER_OP_MODE1_MSK 0x0000000c
++#define PEER_OP_MODE1_I_MSK 0xfffffff3
++#define PEER_OP_MODE1_SFT 2
++#define PEER_OP_MODE1_HI 3
++#define PEER_OP_MODE1_SZ 2
++#define PEER_HT_MODE1_MSK 0x00000030
++#define PEER_HT_MODE1_I_MSK 0xffffffcf
++#define PEER_HT_MODE1_SFT 4
++#define PEER_HT_MODE1_HI 5
++#define PEER_HT_MODE1_SZ 2
++#define PEER_MAC1_31_0_MSK 0xffffffff
++#define PEER_MAC1_31_0_I_MSK 0x00000000
++#define PEER_MAC1_31_0_SFT 0
++#define PEER_MAC1_31_0_HI 31
++#define PEER_MAC1_31_0_SZ 32
++#define PEER_MAC1_47_32_MSK 0x0000ffff
++#define PEER_MAC1_47_32_I_MSK 0xffff0000
++#define PEER_MAC1_47_32_SFT 0
++#define PEER_MAC1_47_32_HI 15
++#define PEER_MAC1_47_32_SZ 16
++#define TX_ACK_POLICY_1_0_MSK 0x00000003
++#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_0_SFT 0
++#define TX_ACK_POLICY_1_0_HI 1
++#define TX_ACK_POLICY_1_0_SZ 2
++#define TX_SEQ_CTRL_1_0_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_0_SFT 0
++#define TX_SEQ_CTRL_1_0_HI 11
++#define TX_SEQ_CTRL_1_0_SZ 12
++#define TX_ACK_POLICY_1_1_MSK 0x00000003
++#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_1_SFT 0
++#define TX_ACK_POLICY_1_1_HI 1
++#define TX_ACK_POLICY_1_1_SZ 2
++#define TX_SEQ_CTRL_1_1_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_1_SFT 0
++#define TX_SEQ_CTRL_1_1_HI 11
++#define TX_SEQ_CTRL_1_1_SZ 12
++#define TX_ACK_POLICY_1_2_MSK 0x00000003
++#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_2_SFT 0
++#define TX_ACK_POLICY_1_2_HI 1
++#define TX_ACK_POLICY_1_2_SZ 2
++#define TX_SEQ_CTRL_1_2_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_2_SFT 0
++#define TX_SEQ_CTRL_1_2_HI 11
++#define TX_SEQ_CTRL_1_2_SZ 12
++#define TX_ACK_POLICY_1_3_MSK 0x00000003
++#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_3_SFT 0
++#define TX_ACK_POLICY_1_3_HI 1
++#define TX_ACK_POLICY_1_3_SZ 2
++#define TX_SEQ_CTRL_1_3_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_3_SFT 0
++#define TX_SEQ_CTRL_1_3_HI 11
++#define TX_SEQ_CTRL_1_3_SZ 12
++#define TX_ACK_POLICY_1_4_MSK 0x00000003
++#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_4_SFT 0
++#define TX_ACK_POLICY_1_4_HI 1
++#define TX_ACK_POLICY_1_4_SZ 2
++#define TX_SEQ_CTRL_1_4_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_4_SFT 0
++#define TX_SEQ_CTRL_1_4_HI 11
++#define TX_SEQ_CTRL_1_4_SZ 12
++#define TX_ACK_POLICY_1_5_MSK 0x00000003
++#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_5_SFT 0
++#define TX_ACK_POLICY_1_5_HI 1
++#define TX_ACK_POLICY_1_5_SZ 2
++#define TX_SEQ_CTRL_1_5_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_5_SFT 0
++#define TX_SEQ_CTRL_1_5_HI 11
++#define TX_SEQ_CTRL_1_5_SZ 12
++#define TX_ACK_POLICY_1_6_MSK 0x00000003
++#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_6_SFT 0
++#define TX_ACK_POLICY_1_6_HI 1
++#define TX_ACK_POLICY_1_6_SZ 2
++#define TX_SEQ_CTRL_1_6_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_6_SFT 0
++#define TX_SEQ_CTRL_1_6_HI 11
++#define TX_SEQ_CTRL_1_6_SZ 12
++#define TX_ACK_POLICY_1_7_MSK 0x00000003
++#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_7_SFT 0
++#define TX_ACK_POLICY_1_7_HI 1
++#define TX_ACK_POLICY_1_7_SZ 2
++#define TX_SEQ_CTRL_1_7_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_7_SFT 0
++#define TX_SEQ_CTRL_1_7_HI 11
++#define TX_SEQ_CTRL_1_7_SZ 12
++#define INFO0_MSK 0xffffffff
++#define INFO0_I_MSK 0x00000000
++#define INFO0_SFT 0
++#define INFO0_HI 31
++#define INFO0_SZ 32
++#define INFO1_MSK 0xffffffff
++#define INFO1_I_MSK 0x00000000
++#define INFO1_SFT 0
++#define INFO1_HI 31
++#define INFO1_SZ 32
++#define INFO2_MSK 0xffffffff
++#define INFO2_I_MSK 0x00000000
++#define INFO2_SFT 0
++#define INFO2_HI 31
++#define INFO2_SZ 32
++#define INFO3_MSK 0xffffffff
++#define INFO3_I_MSK 0x00000000
++#define INFO3_SFT 0
++#define INFO3_HI 31
++#define INFO3_SZ 32
++#define INFO4_MSK 0xffffffff
++#define INFO4_I_MSK 0x00000000
++#define INFO4_SFT 0
++#define INFO4_HI 31
++#define INFO4_SZ 32
++#define INFO5_MSK 0xffffffff
++#define INFO5_I_MSK 0x00000000
++#define INFO5_SFT 0
++#define INFO5_HI 31
++#define INFO5_SZ 32
++#define INFO6_MSK 0xffffffff
++#define INFO6_I_MSK 0x00000000
++#define INFO6_SFT 0
++#define INFO6_HI 31
++#define INFO6_SZ 32
++#define INFO7_MSK 0xffffffff
++#define INFO7_I_MSK 0x00000000
++#define INFO7_SFT 0
++#define INFO7_HI 31
++#define INFO7_SZ 32
++#define INFO8_MSK 0xffffffff
++#define INFO8_I_MSK 0x00000000
++#define INFO8_SFT 0
++#define INFO8_HI 31
++#define INFO8_SZ 32
++#define INFO9_MSK 0xffffffff
++#define INFO9_I_MSK 0x00000000
++#define INFO9_SFT 0
++#define INFO9_HI 31
++#define INFO9_SZ 32
++#define INFO10_MSK 0xffffffff
++#define INFO10_I_MSK 0x00000000
++#define INFO10_SFT 0
++#define INFO10_HI 31
++#define INFO10_SZ 32
++#define INFO11_MSK 0xffffffff
++#define INFO11_I_MSK 0x00000000
++#define INFO11_SFT 0
++#define INFO11_HI 31
++#define INFO11_SZ 32
++#define INFO12_MSK 0xffffffff
++#define INFO12_I_MSK 0x00000000
++#define INFO12_SFT 0
++#define INFO12_HI 31
++#define INFO12_SZ 32
++#define INFO13_MSK 0xffffffff
++#define INFO13_I_MSK 0x00000000
++#define INFO13_SFT 0
++#define INFO13_HI 31
++#define INFO13_SZ 32
++#define INFO14_MSK 0xffffffff
++#define INFO14_I_MSK 0x00000000
++#define INFO14_SFT 0
++#define INFO14_HI 31
++#define INFO14_SZ 32
++#define INFO15_MSK 0xffffffff
++#define INFO15_I_MSK 0x00000000
++#define INFO15_SFT 0
++#define INFO15_HI 31
++#define INFO15_SZ 32
++#define INFO16_MSK 0xffffffff
++#define INFO16_I_MSK 0x00000000
++#define INFO16_SFT 0
++#define INFO16_HI 31
++#define INFO16_SZ 32
++#define INFO17_MSK 0xffffffff
++#define INFO17_I_MSK 0x00000000
++#define INFO17_SFT 0
++#define INFO17_HI 31
++#define INFO17_SZ 32
++#define INFO18_MSK 0xffffffff
++#define INFO18_I_MSK 0x00000000
++#define INFO18_SFT 0
++#define INFO18_HI 31
++#define INFO18_SZ 32
++#define INFO19_MSK 0xffffffff
++#define INFO19_I_MSK 0x00000000
++#define INFO19_SFT 0
++#define INFO19_HI 31
++#define INFO19_SZ 32
++#define INFO20_MSK 0xffffffff
++#define INFO20_I_MSK 0x00000000
++#define INFO20_SFT 0
++#define INFO20_HI 31
++#define INFO20_SZ 32
++#define INFO21_MSK 0xffffffff
++#define INFO21_I_MSK 0x00000000
++#define INFO21_SFT 0
++#define INFO21_HI 31
++#define INFO21_SZ 32
++#define INFO22_MSK 0xffffffff
++#define INFO22_I_MSK 0x00000000
++#define INFO22_SFT 0
++#define INFO22_HI 31
++#define INFO22_SZ 32
++#define INFO23_MSK 0xffffffff
++#define INFO23_I_MSK 0x00000000
++#define INFO23_SFT 0
++#define INFO23_HI 31
++#define INFO23_SZ 32
++#define INFO24_MSK 0xffffffff
++#define INFO24_I_MSK 0x00000000
++#define INFO24_SFT 0
++#define INFO24_HI 31
++#define INFO24_SZ 32
++#define INFO25_MSK 0xffffffff
++#define INFO25_I_MSK 0x00000000
++#define INFO25_SFT 0
++#define INFO25_HI 31
++#define INFO25_SZ 32
++#define INFO26_MSK 0xffffffff
++#define INFO26_I_MSK 0x00000000
++#define INFO26_SFT 0
++#define INFO26_HI 31
++#define INFO26_SZ 32
++#define INFO27_MSK 0xffffffff
++#define INFO27_I_MSK 0x00000000
++#define INFO27_SFT 0
++#define INFO27_HI 31
++#define INFO27_SZ 32
++#define INFO28_MSK 0xffffffff
++#define INFO28_I_MSK 0x00000000
++#define INFO28_SFT 0
++#define INFO28_HI 31
++#define INFO28_SZ 32
++#define INFO29_MSK 0xffffffff
++#define INFO29_I_MSK 0x00000000
++#define INFO29_SFT 0
++#define INFO29_HI 31
++#define INFO29_SZ 32
++#define INFO30_MSK 0xffffffff
++#define INFO30_I_MSK 0x00000000
++#define INFO30_SFT 0
++#define INFO30_HI 31
++#define INFO30_SZ 32
++#define INFO31_MSK 0xffffffff
++#define INFO31_I_MSK 0x00000000
++#define INFO31_SFT 0
++#define INFO31_HI 31
++#define INFO31_SZ 32
++#define INFO32_MSK 0xffffffff
++#define INFO32_I_MSK 0x00000000
++#define INFO32_SFT 0
++#define INFO32_HI 31
++#define INFO32_SZ 32
++#define INFO33_MSK 0xffffffff
++#define INFO33_I_MSK 0x00000000
++#define INFO33_SFT 0
++#define INFO33_HI 31
++#define INFO33_SZ 32
++#define INFO34_MSK 0xffffffff
++#define INFO34_I_MSK 0x00000000
++#define INFO34_SFT 0
++#define INFO34_HI 31
++#define INFO34_SZ 32
++#define INFO35_MSK 0xffffffff
++#define INFO35_I_MSK 0x00000000
++#define INFO35_SFT 0
++#define INFO35_HI 31
++#define INFO35_SZ 32
++#define INFO36_MSK 0xffffffff
++#define INFO36_I_MSK 0x00000000
++#define INFO36_SFT 0
++#define INFO36_HI 31
++#define INFO36_SZ 32
++#define INFO37_MSK 0xffffffff
++#define INFO37_I_MSK 0x00000000
++#define INFO37_SFT 0
++#define INFO37_HI 31
++#define INFO37_SZ 32
++#define INFO38_MSK 0xffffffff
++#define INFO38_I_MSK 0x00000000
++#define INFO38_SFT 0
++#define INFO38_HI 31
++#define INFO38_SZ 32
++#define INFO_MASK_MSK 0xffffffff
++#define INFO_MASK_I_MSK 0x00000000
++#define INFO_MASK_SFT 0
++#define INFO_MASK_HI 31
++#define INFO_MASK_SZ 32
++#define INFO_DEF_RATE_MSK 0x0000003f
++#define INFO_DEF_RATE_I_MSK 0xffffffc0
++#define INFO_DEF_RATE_SFT 0
++#define INFO_DEF_RATE_HI 5
++#define INFO_DEF_RATE_SZ 6
++#define INFO_MRX_OFFSET_MSK 0x000f0000
++#define INFO_MRX_OFFSET_I_MSK 0xfff0ffff
++#define INFO_MRX_OFFSET_SFT 16
++#define INFO_MRX_OFFSET_HI 19
++#define INFO_MRX_OFFSET_SZ 4
++#define BCAST_RATEUNKNOW_MSK 0x3f000000
++#define BCAST_RATEUNKNOW_I_MSK 0xc0ffffff
++#define BCAST_RATEUNKNOW_SFT 24
++#define BCAST_RATEUNKNOW_HI 29
++#define BCAST_RATEUNKNOW_SZ 6
++#define INFO_IDX_TBL_ADDR_MSK 0xffffffff
++#define INFO_IDX_TBL_ADDR_I_MSK 0x00000000
++#define INFO_IDX_TBL_ADDR_SFT 0
++#define INFO_IDX_TBL_ADDR_HI 31
++#define INFO_IDX_TBL_ADDR_SZ 32
++#define INFO_LEN_TBL_ADDR_MSK 0xffffffff
++#define INFO_LEN_TBL_ADDR_I_MSK 0x00000000
++#define INFO_LEN_TBL_ADDR_SFT 0
++#define INFO_LEN_TBL_ADDR_HI 31
++#define INFO_LEN_TBL_ADDR_SZ 32
++#define IC_TAG_31_0_MSK 0xffffffff
++#define IC_TAG_31_0_I_MSK 0x00000000
++#define IC_TAG_31_0_SFT 0
++#define IC_TAG_31_0_HI 31
++#define IC_TAG_31_0_SZ 32
++#define IC_TAG_63_32_MSK 0xffffffff
++#define IC_TAG_63_32_I_MSK 0x00000000
++#define IC_TAG_63_32_SFT 0
++#define IC_TAG_63_32_HI 31
++#define IC_TAG_63_32_SZ 32
++#define CH1_PRI_MSK 0x00000003
++#define CH1_PRI_I_MSK 0xfffffffc
++#define CH1_PRI_SFT 0
++#define CH1_PRI_HI 1
++#define CH1_PRI_SZ 2
++#define CH2_PRI_MSK 0x00000300
++#define CH2_PRI_I_MSK 0xfffffcff
++#define CH2_PRI_SFT 8
++#define CH2_PRI_HI 9
++#define CH2_PRI_SZ 2
++#define CH3_PRI_MSK 0x00030000
++#define CH3_PRI_I_MSK 0xfffcffff
++#define CH3_PRI_SFT 16
++#define CH3_PRI_HI 17
++#define CH3_PRI_SZ 2
++#define RG_MAC_LPBK_MSK 0x00000001
++#define RG_MAC_LPBK_I_MSK 0xfffffffe
++#define RG_MAC_LPBK_SFT 0
++#define RG_MAC_LPBK_HI 0
++#define RG_MAC_LPBK_SZ 1
++#define RG_MAC_M2M_MSK 0x00000002
++#define RG_MAC_M2M_I_MSK 0xfffffffd
++#define RG_MAC_M2M_SFT 1
++#define RG_MAC_M2M_HI 1
++#define RG_MAC_M2M_SZ 1
++#define RG_PHY_LPBK_MSK 0x00000004
++#define RG_PHY_LPBK_I_MSK 0xfffffffb
++#define RG_PHY_LPBK_SFT 2
++#define RG_PHY_LPBK_HI 2
++#define RG_PHY_LPBK_SZ 1
++#define RG_LPBK_RX_EN_MSK 0x00000008
++#define RG_LPBK_RX_EN_I_MSK 0xfffffff7
++#define RG_LPBK_RX_EN_SFT 3
++#define RG_LPBK_RX_EN_HI 3
++#define RG_LPBK_RX_EN_SZ 1
++#define EXT_MAC_MODE_MSK 0x00000010
++#define EXT_MAC_MODE_I_MSK 0xffffffef
++#define EXT_MAC_MODE_SFT 4
++#define EXT_MAC_MODE_HI 4
++#define EXT_MAC_MODE_SZ 1
++#define EXT_PHY_MODE_MSK 0x00000020
++#define EXT_PHY_MODE_I_MSK 0xffffffdf
++#define EXT_PHY_MODE_SFT 5
++#define EXT_PHY_MODE_HI 5
++#define EXT_PHY_MODE_SZ 1
++#define ASIC_TAG_MSK 0xff000000
++#define ASIC_TAG_I_MSK 0x00ffffff
++#define ASIC_TAG_SFT 24
++#define ASIC_TAG_HI 31
++#define ASIC_TAG_SZ 8
++#define HCI_SW_RST_MSK 0x00000001
++#define HCI_SW_RST_I_MSK 0xfffffffe
++#define HCI_SW_RST_SFT 0
++#define HCI_SW_RST_HI 0
++#define HCI_SW_RST_SZ 1
++#define CO_PROC_SW_RST_MSK 0x00000002
++#define CO_PROC_SW_RST_I_MSK 0xfffffffd
++#define CO_PROC_SW_RST_SFT 1
++#define CO_PROC_SW_RST_HI 1
++#define CO_PROC_SW_RST_SZ 1
++#define MTX_MISC_SW_RST_MSK 0x00000008
++#define MTX_MISC_SW_RST_I_MSK 0xfffffff7
++#define MTX_MISC_SW_RST_SFT 3
++#define MTX_MISC_SW_RST_HI 3
++#define MTX_MISC_SW_RST_SZ 1
++#define MTX_QUE_SW_RST_MSK 0x00000010
++#define MTX_QUE_SW_RST_I_MSK 0xffffffef
++#define MTX_QUE_SW_RST_SFT 4
++#define MTX_QUE_SW_RST_HI 4
++#define MTX_QUE_SW_RST_SZ 1
++#define MTX_CHST_SW_RST_MSK 0x00000020
++#define MTX_CHST_SW_RST_I_MSK 0xffffffdf
++#define MTX_CHST_SW_RST_SFT 5
++#define MTX_CHST_SW_RST_HI 5
++#define MTX_CHST_SW_RST_SZ 1
++#define MTX_BCN_SW_RST_MSK 0x00000040
++#define MTX_BCN_SW_RST_I_MSK 0xffffffbf
++#define MTX_BCN_SW_RST_SFT 6
++#define MTX_BCN_SW_RST_HI 6
++#define MTX_BCN_SW_RST_SZ 1
++#define MRX_SW_RST_MSK 0x00000080
++#define MRX_SW_RST_I_MSK 0xffffff7f
++#define MRX_SW_RST_SFT 7
++#define MRX_SW_RST_HI 7
++#define MRX_SW_RST_SZ 1
++#define AMPDU_SW_RST_MSK 0x00000100
++#define AMPDU_SW_RST_I_MSK 0xfffffeff
++#define AMPDU_SW_RST_SFT 8
++#define AMPDU_SW_RST_HI 8
++#define AMPDU_SW_RST_SZ 1
++#define MMU_SW_RST_MSK 0x00000200
++#define MMU_SW_RST_I_MSK 0xfffffdff
++#define MMU_SW_RST_SFT 9
++#define MMU_SW_RST_HI 9
++#define MMU_SW_RST_SZ 1
++#define ID_MNG_SW_RST_MSK 0x00000800
++#define ID_MNG_SW_RST_I_MSK 0xfffff7ff
++#define ID_MNG_SW_RST_SFT 11
++#define ID_MNG_SW_RST_HI 11
++#define ID_MNG_SW_RST_SZ 1
++#define MBOX_SW_RST_MSK 0x00001000
++#define MBOX_SW_RST_I_MSK 0xffffefff
++#define MBOX_SW_RST_SFT 12
++#define MBOX_SW_RST_HI 12
++#define MBOX_SW_RST_SZ 1
++#define SCRT_SW_RST_MSK 0x00002000
++#define SCRT_SW_RST_I_MSK 0xffffdfff
++#define SCRT_SW_RST_SFT 13
++#define SCRT_SW_RST_HI 13
++#define SCRT_SW_RST_SZ 1
++#define MIC_SW_RST_MSK 0x00004000
++#define MIC_SW_RST_I_MSK 0xffffbfff
++#define MIC_SW_RST_SFT 14
++#define MIC_SW_RST_HI 14
++#define MIC_SW_RST_SZ 1
++#define CO_PROC_ENG_RST_MSK 0x00000002
++#define CO_PROC_ENG_RST_I_MSK 0xfffffffd
++#define CO_PROC_ENG_RST_SFT 1
++#define CO_PROC_ENG_RST_HI 1
++#define CO_PROC_ENG_RST_SZ 1
++#define MTX_MISC_ENG_RST_MSK 0x00000008
++#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7
++#define MTX_MISC_ENG_RST_SFT 3
++#define MTX_MISC_ENG_RST_HI 3
++#define MTX_MISC_ENG_RST_SZ 1
++#define MTX_QUE_ENG_RST_MSK 0x00000010
++#define MTX_QUE_ENG_RST_I_MSK 0xffffffef
++#define MTX_QUE_ENG_RST_SFT 4
++#define MTX_QUE_ENG_RST_HI 4
++#define MTX_QUE_ENG_RST_SZ 1
++#define MTX_CHST_ENG_RST_MSK 0x00000020
++#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf
++#define MTX_CHST_ENG_RST_SFT 5
++#define MTX_CHST_ENG_RST_HI 5
++#define MTX_CHST_ENG_RST_SZ 1
++#define MTX_BCN_ENG_RST_MSK 0x00000040
++#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf
++#define MTX_BCN_ENG_RST_SFT 6
++#define MTX_BCN_ENG_RST_HI 6
++#define MTX_BCN_ENG_RST_SZ 1
++#define MRX_ENG_RST_MSK 0x00000080
++#define MRX_ENG_RST_I_MSK 0xffffff7f
++#define MRX_ENG_RST_SFT 7
++#define MRX_ENG_RST_HI 7
++#define MRX_ENG_RST_SZ 1
++#define AMPDU_ENG_RST_MSK 0x00000100
++#define AMPDU_ENG_RST_I_MSK 0xfffffeff
++#define AMPDU_ENG_RST_SFT 8
++#define AMPDU_ENG_RST_HI 8
++#define AMPDU_ENG_RST_SZ 1
++#define ID_MNG_ENG_RST_MSK 0x00004000
++#define ID_MNG_ENG_RST_I_MSK 0xffffbfff
++#define ID_MNG_ENG_RST_SFT 14
++#define ID_MNG_ENG_RST_HI 14
++#define ID_MNG_ENG_RST_SZ 1
++#define MBOX_ENG_RST_MSK 0x00008000
++#define MBOX_ENG_RST_I_MSK 0xffff7fff
++#define MBOX_ENG_RST_SFT 15
++#define MBOX_ENG_RST_HI 15
++#define MBOX_ENG_RST_SZ 1
++#define SCRT_ENG_RST_MSK 0x00010000
++#define SCRT_ENG_RST_I_MSK 0xfffeffff
++#define SCRT_ENG_RST_SFT 16
++#define SCRT_ENG_RST_HI 16
++#define SCRT_ENG_RST_SZ 1
++#define MIC_ENG_RST_MSK 0x00020000
++#define MIC_ENG_RST_I_MSK 0xfffdffff
++#define MIC_ENG_RST_SFT 17
++#define MIC_ENG_RST_HI 17
++#define MIC_ENG_RST_SZ 1
++#define CO_PROC_CSR_RST_MSK 0x00000002
++#define CO_PROC_CSR_RST_I_MSK 0xfffffffd
++#define CO_PROC_CSR_RST_SFT 1
++#define CO_PROC_CSR_RST_HI 1
++#define CO_PROC_CSR_RST_SZ 1
++#define MTX_MISC_CSR_RST_MSK 0x00000008
++#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7
++#define MTX_MISC_CSR_RST_SFT 3
++#define MTX_MISC_CSR_RST_HI 3
++#define MTX_MISC_CSR_RST_SZ 1
++#define MTX_QUE0_CSR_RST_MSK 0x00000010
++#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef
++#define MTX_QUE0_CSR_RST_SFT 4
++#define MTX_QUE0_CSR_RST_HI 4
++#define MTX_QUE0_CSR_RST_SZ 1
++#define MTX_QUE1_CSR_RST_MSK 0x00000020
++#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf
++#define MTX_QUE1_CSR_RST_SFT 5
++#define MTX_QUE1_CSR_RST_HI 5
++#define MTX_QUE1_CSR_RST_SZ 1
++#define MTX_QUE2_CSR_RST_MSK 0x00000040
++#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf
++#define MTX_QUE2_CSR_RST_SFT 6
++#define MTX_QUE2_CSR_RST_HI 6
++#define MTX_QUE2_CSR_RST_SZ 1
++#define MTX_QUE3_CSR_RST_MSK 0x00000080
++#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f
++#define MTX_QUE3_CSR_RST_SFT 7
++#define MTX_QUE3_CSR_RST_HI 7
++#define MTX_QUE3_CSR_RST_SZ 1
++#define MTX_QUE4_CSR_RST_MSK 0x00000100
++#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff
++#define MTX_QUE4_CSR_RST_SFT 8
++#define MTX_QUE4_CSR_RST_HI 8
++#define MTX_QUE4_CSR_RST_SZ 1
++#define MTX_QUE5_CSR_RST_MSK 0x00000200
++#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff
++#define MTX_QUE5_CSR_RST_SFT 9
++#define MTX_QUE5_CSR_RST_HI 9
++#define MTX_QUE5_CSR_RST_SZ 1
++#define MRX_CSR_RST_MSK 0x00000400
++#define MRX_CSR_RST_I_MSK 0xfffffbff
++#define MRX_CSR_RST_SFT 10
++#define MRX_CSR_RST_HI 10
++#define MRX_CSR_RST_SZ 1
++#define AMPDU_CSR_RST_MSK 0x00000800
++#define AMPDU_CSR_RST_I_MSK 0xfffff7ff
++#define AMPDU_CSR_RST_SFT 11
++#define AMPDU_CSR_RST_HI 11
++#define AMPDU_CSR_RST_SZ 1
++#define SCRT_CSR_RST_MSK 0x00002000
++#define SCRT_CSR_RST_I_MSK 0xffffdfff
++#define SCRT_CSR_RST_SFT 13
++#define SCRT_CSR_RST_HI 13
++#define SCRT_CSR_RST_SZ 1
++#define ID_MNG_CSR_RST_MSK 0x00004000
++#define ID_MNG_CSR_RST_I_MSK 0xffffbfff
++#define ID_MNG_CSR_RST_SFT 14
++#define ID_MNG_CSR_RST_HI 14
++#define ID_MNG_CSR_RST_SZ 1
++#define MBOX_CSR_RST_MSK 0x00008000
++#define MBOX_CSR_RST_I_MSK 0xffff7fff
++#define MBOX_CSR_RST_SFT 15
++#define MBOX_CSR_RST_HI 15
++#define MBOX_CSR_RST_SZ 1
++#define HCI_CLK_EN_MSK 0x00000001
++#define HCI_CLK_EN_I_MSK 0xfffffffe
++#define HCI_CLK_EN_SFT 0
++#define HCI_CLK_EN_HI 0
++#define HCI_CLK_EN_SZ 1
++#define CO_PROC_CLK_EN_MSK 0x00000002
++#define CO_PROC_CLK_EN_I_MSK 0xfffffffd
++#define CO_PROC_CLK_EN_SFT 1
++#define CO_PROC_CLK_EN_HI 1
++#define CO_PROC_CLK_EN_SZ 1
++#define MTX_MISC_CLK_EN_MSK 0x00000008
++#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7
++#define MTX_MISC_CLK_EN_SFT 3
++#define MTX_MISC_CLK_EN_HI 3
++#define MTX_MISC_CLK_EN_SZ 1
++#define MTX_QUE_CLK_EN_MSK 0x00000010
++#define MTX_QUE_CLK_EN_I_MSK 0xffffffef
++#define MTX_QUE_CLK_EN_SFT 4
++#define MTX_QUE_CLK_EN_HI 4
++#define MTX_QUE_CLK_EN_SZ 1
++#define MRX_CLK_EN_MSK 0x00000020
++#define MRX_CLK_EN_I_MSK 0xffffffdf
++#define MRX_CLK_EN_SFT 5
++#define MRX_CLK_EN_HI 5
++#define MRX_CLK_EN_SZ 1
++#define AMPDU_CLK_EN_MSK 0x00000040
++#define AMPDU_CLK_EN_I_MSK 0xffffffbf
++#define AMPDU_CLK_EN_SFT 6
++#define AMPDU_CLK_EN_HI 6
++#define AMPDU_CLK_EN_SZ 1
++#define MMU_CLK_EN_MSK 0x00000080
++#define MMU_CLK_EN_I_MSK 0xffffff7f
++#define MMU_CLK_EN_SFT 7
++#define MMU_CLK_EN_HI 7
++#define MMU_CLK_EN_SZ 1
++#define ID_MNG_CLK_EN_MSK 0x00000200
++#define ID_MNG_CLK_EN_I_MSK 0xfffffdff
++#define ID_MNG_CLK_EN_SFT 9
++#define ID_MNG_CLK_EN_HI 9
++#define ID_MNG_CLK_EN_SZ 1
++#define MBOX_CLK_EN_MSK 0x00000400
++#define MBOX_CLK_EN_I_MSK 0xfffffbff
++#define MBOX_CLK_EN_SFT 10
++#define MBOX_CLK_EN_HI 10
++#define MBOX_CLK_EN_SZ 1
++#define SCRT_CLK_EN_MSK 0x00000800
++#define SCRT_CLK_EN_I_MSK 0xfffff7ff
++#define SCRT_CLK_EN_SFT 11
++#define SCRT_CLK_EN_HI 11
++#define SCRT_CLK_EN_SZ 1
++#define MIC_CLK_EN_MSK 0x00001000
++#define MIC_CLK_EN_I_MSK 0xffffefff
++#define MIC_CLK_EN_SFT 12
++#define MIC_CLK_EN_HI 12
++#define MIC_CLK_EN_SZ 1
++#define MIB_CLK_EN_MSK 0x00002000
++#define MIB_CLK_EN_I_MSK 0xffffdfff
++#define MIB_CLK_EN_SFT 13
++#define MIB_CLK_EN_HI 13
++#define MIB_CLK_EN_SZ 1
++#define HCI_ENG_CLK_EN_MSK 0x00000001
++#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe
++#define HCI_ENG_CLK_EN_SFT 0
++#define HCI_ENG_CLK_EN_HI 0
++#define HCI_ENG_CLK_EN_SZ 1
++#define CO_PROC_ENG_CLK_EN_MSK 0x00000002
++#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd
++#define CO_PROC_ENG_CLK_EN_SFT 1
++#define CO_PROC_ENG_CLK_EN_HI 1
++#define CO_PROC_ENG_CLK_EN_SZ 1
++#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008
++#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7
++#define MTX_MISC_ENG_CLK_EN_SFT 3
++#define MTX_MISC_ENG_CLK_EN_HI 3
++#define MTX_MISC_ENG_CLK_EN_SZ 1
++#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010
++#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef
++#define MTX_QUE_ENG_CLK_EN_SFT 4
++#define MTX_QUE_ENG_CLK_EN_HI 4
++#define MTX_QUE_ENG_CLK_EN_SZ 1
++#define MRX_ENG_CLK_EN_MSK 0x00000020
++#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf
++#define MRX_ENG_CLK_EN_SFT 5
++#define MRX_ENG_CLK_EN_HI 5
++#define MRX_ENG_CLK_EN_SZ 1
++#define AMPDU_ENG_CLK_EN_MSK 0x00000040
++#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf
++#define AMPDU_ENG_CLK_EN_SFT 6
++#define AMPDU_ENG_CLK_EN_HI 6
++#define AMPDU_ENG_CLK_EN_SZ 1
++#define ID_MNG_ENG_CLK_EN_MSK 0x00001000
++#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff
++#define ID_MNG_ENG_CLK_EN_SFT 12
++#define ID_MNG_ENG_CLK_EN_HI 12
++#define ID_MNG_ENG_CLK_EN_SZ 1
++#define MBOX_ENG_CLK_EN_MSK 0x00002000
++#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff
++#define MBOX_ENG_CLK_EN_SFT 13
++#define MBOX_ENG_CLK_EN_HI 13
++#define MBOX_ENG_CLK_EN_SZ 1
++#define SCRT_ENG_CLK_EN_MSK 0x00004000
++#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff
++#define SCRT_ENG_CLK_EN_SFT 14
++#define SCRT_ENG_CLK_EN_HI 14
++#define SCRT_ENG_CLK_EN_SZ 1
++#define MIC_ENG_CLK_EN_MSK 0x00008000
++#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff
++#define MIC_ENG_CLK_EN_SFT 15
++#define MIC_ENG_CLK_EN_HI 15
++#define MIC_ENG_CLK_EN_SZ 1
++#define CO_PROC_CSR_CLK_EN_MSK 0x00000002
++#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd
++#define CO_PROC_CSR_CLK_EN_SFT 1
++#define CO_PROC_CSR_CLK_EN_HI 1
++#define CO_PROC_CSR_CLK_EN_SZ 1
++#define MRX_CSR_CLK_EN_MSK 0x00000400
++#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff
++#define MRX_CSR_CLK_EN_SFT 10
++#define MRX_CSR_CLK_EN_HI 10
++#define MRX_CSR_CLK_EN_SZ 1
++#define AMPDU_CSR_CLK_EN_MSK 0x00000800
++#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff
++#define AMPDU_CSR_CLK_EN_SFT 11
++#define AMPDU_CSR_CLK_EN_HI 11
++#define AMPDU_CSR_CLK_EN_SZ 1
++#define SCRT_CSR_CLK_EN_MSK 0x00002000
++#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff
++#define SCRT_CSR_CLK_EN_SFT 13
++#define SCRT_CSR_CLK_EN_HI 13
++#define SCRT_CSR_CLK_EN_SZ 1
++#define ID_MNG_CSR_CLK_EN_MSK 0x00004000
++#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff
++#define ID_MNG_CSR_CLK_EN_SFT 14
++#define ID_MNG_CSR_CLK_EN_HI 14
++#define ID_MNG_CSR_CLK_EN_SZ 1
++#define MBOX_CSR_CLK_EN_MSK 0x00008000
++#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff
++#define MBOX_CSR_CLK_EN_SFT 15
++#define MBOX_CSR_CLK_EN_HI 15
++#define MBOX_CSR_CLK_EN_SZ 1
++#define OP_MODE_MSK 0x00000003
++#define OP_MODE_I_MSK 0xfffffffc
++#define OP_MODE_SFT 0
++#define OP_MODE_HI 1
++#define OP_MODE_SZ 2
++#define HT_MODE_MSK 0x0000000c
++#define HT_MODE_I_MSK 0xfffffff3
++#define HT_MODE_SFT 2
++#define HT_MODE_HI 3
++#define HT_MODE_SZ 2
++#define QOS_EN_MSK 0x00000010
++#define QOS_EN_I_MSK 0xffffffef
++#define QOS_EN_SFT 4
++#define QOS_EN_HI 4
++#define QOS_EN_SZ 1
++#define PB_OFFSET_MSK 0x0000ff00
++#define PB_OFFSET_I_MSK 0xffff00ff
++#define PB_OFFSET_SFT 8
++#define PB_OFFSET_HI 15
++#define PB_OFFSET_SZ 8
++#define SNIFFER_MODE_MSK 0x00010000
++#define SNIFFER_MODE_I_MSK 0xfffeffff
++#define SNIFFER_MODE_SFT 16
++#define SNIFFER_MODE_HI 16
++#define SNIFFER_MODE_SZ 1
++#define DUP_FLT_MSK 0x00020000
++#define DUP_FLT_I_MSK 0xfffdffff
++#define DUP_FLT_SFT 17
++#define DUP_FLT_HI 17
++#define DUP_FLT_SZ 1
++#define TX_PKT_RSVD_MSK 0x001c0000
++#define TX_PKT_RSVD_I_MSK 0xffe3ffff
++#define TX_PKT_RSVD_SFT 18
++#define TX_PKT_RSVD_HI 20
++#define TX_PKT_RSVD_SZ 3
++#define AMPDU_SNIFFER_MSK 0x00200000
++#define AMPDU_SNIFFER_I_MSK 0xffdfffff
++#define AMPDU_SNIFFER_SFT 21
++#define AMPDU_SNIFFER_HI 21
++#define AMPDU_SNIFFER_SZ 1
++#define REASON_TRAP0_MSK 0xffffffff
++#define REASON_TRAP0_I_MSK 0x00000000
++#define REASON_TRAP0_SFT 0
++#define REASON_TRAP0_HI 31
++#define REASON_TRAP0_SZ 32
++#define REASON_TRAP1_MSK 0xffffffff
++#define REASON_TRAP1_I_MSK 0x00000000
++#define REASON_TRAP1_SFT 0
++#define REASON_TRAP1_HI 31
++#define REASON_TRAP1_SZ 32
++#define BSSID_31_0_MSK 0xffffffff
++#define BSSID_31_0_I_MSK 0x00000000
++#define BSSID_31_0_SFT 0
++#define BSSID_31_0_HI 31
++#define BSSID_31_0_SZ 32
++#define BSSID_47_32_MSK 0x0000ffff
++#define BSSID_47_32_I_MSK 0xffff0000
++#define BSSID_47_32_SFT 0
++#define BSSID_47_32_HI 15
++#define BSSID_47_32_SZ 16
++#define SCRT_STATE_MSK 0x0000000f
++#define SCRT_STATE_I_MSK 0xfffffff0
++#define SCRT_STATE_SFT 0
++#define SCRT_STATE_HI 3
++#define SCRT_STATE_SZ 4
++#define STA_MAC_31_0_MSK 0xffffffff
++#define STA_MAC_31_0_I_MSK 0x00000000
++#define STA_MAC_31_0_SFT 0
++#define STA_MAC_31_0_HI 31
++#define STA_MAC_31_0_SZ 32
++#define STA_MAC_47_32_MSK 0x0000ffff
++#define STA_MAC_47_32_I_MSK 0xffff0000
++#define STA_MAC_47_32_SFT 0
++#define STA_MAC_47_32_HI 15
++#define STA_MAC_47_32_SZ 16
++#define PAIR_SCRT_MSK 0x00000007
++#define PAIR_SCRT_I_MSK 0xfffffff8
++#define PAIR_SCRT_SFT 0
++#define PAIR_SCRT_HI 2
++#define PAIR_SCRT_SZ 3
++#define GRP_SCRT_MSK 0x00000038
++#define GRP_SCRT_I_MSK 0xffffffc7
++#define GRP_SCRT_SFT 3
++#define GRP_SCRT_HI 5
++#define GRP_SCRT_SZ 3
++#define SCRT_PKT_ID_MSK 0x00001fc0
++#define SCRT_PKT_ID_I_MSK 0xffffe03f
++#define SCRT_PKT_ID_SFT 6
++#define SCRT_PKT_ID_HI 12
++#define SCRT_PKT_ID_SZ 7
++#define SCRT_RPLY_IGNORE_MSK 0x00010000
++#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff
++#define SCRT_RPLY_IGNORE_SFT 16
++#define SCRT_RPLY_IGNORE_HI 16
++#define SCRT_RPLY_IGNORE_SZ 1
++#define COEXIST_EN_MSK 0x00000001
++#define COEXIST_EN_I_MSK 0xfffffffe
++#define COEXIST_EN_SFT 0
++#define COEXIST_EN_HI 0
++#define COEXIST_EN_SZ 1
++#define WIRE_MODE_MSK 0x0000000e
++#define WIRE_MODE_I_MSK 0xfffffff1
++#define WIRE_MODE_SFT 1
++#define WIRE_MODE_HI 3
++#define WIRE_MODE_SZ 3
++#define WL_RX_PRI_MSK 0x00000010
++#define WL_RX_PRI_I_MSK 0xffffffef
++#define WL_RX_PRI_SFT 4
++#define WL_RX_PRI_HI 4
++#define WL_RX_PRI_SZ 1
++#define WL_TX_PRI_MSK 0x00000020
++#define WL_TX_PRI_I_MSK 0xffffffdf
++#define WL_TX_PRI_SFT 5
++#define WL_TX_PRI_HI 5
++#define WL_TX_PRI_SZ 1
++#define GURAN_USE_EN_MSK 0x00000100
++#define GURAN_USE_EN_I_MSK 0xfffffeff
++#define GURAN_USE_EN_SFT 8
++#define GURAN_USE_EN_HI 8
++#define GURAN_USE_EN_SZ 1
++#define GURAN_USE_CTRL_MSK 0x00000200
++#define GURAN_USE_CTRL_I_MSK 0xfffffdff
++#define GURAN_USE_CTRL_SFT 9
++#define GURAN_USE_CTRL_HI 9
++#define GURAN_USE_CTRL_SZ 1
++#define BEACON_TIMEOUT_EN_MSK 0x00000400
++#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff
++#define BEACON_TIMEOUT_EN_SFT 10
++#define BEACON_TIMEOUT_EN_HI 10
++#define BEACON_TIMEOUT_EN_SZ 1
++#define WLAN_ACT_POL_MSK 0x00000800
++#define WLAN_ACT_POL_I_MSK 0xfffff7ff
++#define WLAN_ACT_POL_SFT 11
++#define WLAN_ACT_POL_HI 11
++#define WLAN_ACT_POL_SZ 1
++#define DUAL_ANT_EN_MSK 0x00001000
++#define DUAL_ANT_EN_I_MSK 0xffffefff
++#define DUAL_ANT_EN_SFT 12
++#define DUAL_ANT_EN_HI 12
++#define DUAL_ANT_EN_SZ 1
++#define TRSW_PHY_POL_MSK 0x00010000
++#define TRSW_PHY_POL_I_MSK 0xfffeffff
++#define TRSW_PHY_POL_SFT 16
++#define TRSW_PHY_POL_HI 16
++#define TRSW_PHY_POL_SZ 1
++#define WIFI_TX_SW_POL_MSK 0x00020000
++#define WIFI_TX_SW_POL_I_MSK 0xfffdffff
++#define WIFI_TX_SW_POL_SFT 17
++#define WIFI_TX_SW_POL_HI 17
++#define WIFI_TX_SW_POL_SZ 1
++#define WIFI_RX_SW_POL_MSK 0x00040000
++#define WIFI_RX_SW_POL_I_MSK 0xfffbffff
++#define WIFI_RX_SW_POL_SFT 18
++#define WIFI_RX_SW_POL_HI 18
++#define WIFI_RX_SW_POL_SZ 1
++#define BT_SW_POL_MSK 0x00080000
++#define BT_SW_POL_I_MSK 0xfff7ffff
++#define BT_SW_POL_SFT 19
++#define BT_SW_POL_HI 19
++#define BT_SW_POL_SZ 1
++#define BT_PRI_SMP_TIME_MSK 0x000000ff
++#define BT_PRI_SMP_TIME_I_MSK 0xffffff00
++#define BT_PRI_SMP_TIME_SFT 0
++#define BT_PRI_SMP_TIME_HI 7
++#define BT_PRI_SMP_TIME_SZ 8
++#define BT_STA_SMP_TIME_MSK 0x0000ff00
++#define BT_STA_SMP_TIME_I_MSK 0xffff00ff
++#define BT_STA_SMP_TIME_SFT 8
++#define BT_STA_SMP_TIME_HI 15
++#define BT_STA_SMP_TIME_SZ 8
++#define BEACON_TIMEOUT_MSK 0x00ff0000
++#define BEACON_TIMEOUT_I_MSK 0xff00ffff
++#define BEACON_TIMEOUT_SFT 16
++#define BEACON_TIMEOUT_HI 23
++#define BEACON_TIMEOUT_SZ 8
++#define WLAN_REMAIN_TIME_MSK 0xff000000
++#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff
++#define WLAN_REMAIN_TIME_SFT 24
++#define WLAN_REMAIN_TIME_HI 31
++#define WLAN_REMAIN_TIME_SZ 8
++#define SW_MANUAL_EN_MSK 0x00000001
++#define SW_MANUAL_EN_I_MSK 0xfffffffe
++#define SW_MANUAL_EN_SFT 0
++#define SW_MANUAL_EN_HI 0
++#define SW_MANUAL_EN_SZ 1
++#define SW_WL_TX_MSK 0x00000002
++#define SW_WL_TX_I_MSK 0xfffffffd
++#define SW_WL_TX_SFT 1
++#define SW_WL_TX_HI 1
++#define SW_WL_TX_SZ 1
++#define SW_WL_RX_MSK 0x00000004
++#define SW_WL_RX_I_MSK 0xfffffffb
++#define SW_WL_RX_SFT 2
++#define SW_WL_RX_HI 2
++#define SW_WL_RX_SZ 1
++#define SW_BT_TRX_MSK 0x00000008
++#define SW_BT_TRX_I_MSK 0xfffffff7
++#define SW_BT_TRX_SFT 3
++#define SW_BT_TRX_HI 3
++#define SW_BT_TRX_SZ 1
++#define BT_TXBAR_MANUAL_EN_MSK 0x00000010
++#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef
++#define BT_TXBAR_MANUAL_EN_SFT 4
++#define BT_TXBAR_MANUAL_EN_HI 4
++#define BT_TXBAR_MANUAL_EN_SZ 1
++#define BT_TXBAR_SET_MSK 0x00000020
++#define BT_TXBAR_SET_I_MSK 0xffffffdf
++#define BT_TXBAR_SET_SFT 5
++#define BT_TXBAR_SET_HI 5
++#define BT_TXBAR_SET_SZ 1
++#define BT_BUSY_MANUAL_EN_MSK 0x00000100
++#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff
++#define BT_BUSY_MANUAL_EN_SFT 8
++#define BT_BUSY_MANUAL_EN_HI 8
++#define BT_BUSY_MANUAL_EN_SZ 1
++#define BT_BUSY_SET_MSK 0x00000200
++#define BT_BUSY_SET_I_MSK 0xfffffdff
++#define BT_BUSY_SET_SFT 9
++#define BT_BUSY_SET_HI 9
++#define BT_BUSY_SET_SZ 1
++#define G0_PKT_CLS_MIB_EN_MSK 0x00000004
++#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb
++#define G0_PKT_CLS_MIB_EN_SFT 2
++#define G0_PKT_CLS_MIB_EN_HI 2
++#define G0_PKT_CLS_MIB_EN_SZ 1
++#define G0_PKT_CLS_ONGOING_MSK 0x00000008
++#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7
++#define G0_PKT_CLS_ONGOING_SFT 3
++#define G0_PKT_CLS_ONGOING_HI 3
++#define G0_PKT_CLS_ONGOING_SZ 1
++#define G1_PKT_CLS_MIB_EN_MSK 0x00000010
++#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef
++#define G1_PKT_CLS_MIB_EN_SFT 4
++#define G1_PKT_CLS_MIB_EN_HI 4
++#define G1_PKT_CLS_MIB_EN_SZ 1
++#define G1_PKT_CLS_ONGOING_MSK 0x00000020
++#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf
++#define G1_PKT_CLS_ONGOING_SFT 5
++#define G1_PKT_CLS_ONGOING_HI 5
++#define G1_PKT_CLS_ONGOING_SZ 1
++#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040
++#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf
++#define Q0_PKT_CLS_MIB_EN_SFT 6
++#define Q0_PKT_CLS_MIB_EN_HI 6
++#define Q0_PKT_CLS_MIB_EN_SZ 1
++#define Q0_PKT_CLS_ONGOING_MSK 0x00000080
++#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f
++#define Q0_PKT_CLS_ONGOING_SFT 7
++#define Q0_PKT_CLS_ONGOING_HI 7
++#define Q0_PKT_CLS_ONGOING_SZ 1
++#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100
++#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff
++#define Q1_PKT_CLS_MIB_EN_SFT 8
++#define Q1_PKT_CLS_MIB_EN_HI 8
++#define Q1_PKT_CLS_MIB_EN_SZ 1
++#define Q1_PKT_CLS_ONGOING_MSK 0x00000200
++#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff
++#define Q1_PKT_CLS_ONGOING_SFT 9
++#define Q1_PKT_CLS_ONGOING_HI 9
++#define Q1_PKT_CLS_ONGOING_SZ 1
++#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400
++#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff
++#define Q2_PKT_CLS_MIB_EN_SFT 10
++#define Q2_PKT_CLS_MIB_EN_HI 10
++#define Q2_PKT_CLS_MIB_EN_SZ 1
++#define Q2_PKT_CLS_ONGOING_MSK 0x00000800
++#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff
++#define Q2_PKT_CLS_ONGOING_SFT 11
++#define Q2_PKT_CLS_ONGOING_HI 11
++#define Q2_PKT_CLS_ONGOING_SZ 1
++#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000
++#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff
++#define Q3_PKT_CLS_MIB_EN_SFT 12
++#define Q3_PKT_CLS_MIB_EN_HI 12
++#define Q3_PKT_CLS_MIB_EN_SZ 1
++#define Q3_PKT_CLS_ONGOING_MSK 0x00002000
++#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff
++#define Q3_PKT_CLS_ONGOING_SFT 13
++#define Q3_PKT_CLS_ONGOING_HI 13
++#define Q3_PKT_CLS_ONGOING_SZ 1
++#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000
++#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff
++#define SCRT_PKT_CLS_MIB_EN_SFT 14
++#define SCRT_PKT_CLS_MIB_EN_HI 14
++#define SCRT_PKT_CLS_MIB_EN_SZ 1
++#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000
++#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff
++#define SCRT_PKT_CLS_ONGOING_SFT 15
++#define SCRT_PKT_CLS_ONGOING_HI 15
++#define SCRT_PKT_CLS_ONGOING_SZ 1
++#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000
++#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff
++#define MISC_PKT_CLS_MIB_EN_SFT 16
++#define MISC_PKT_CLS_MIB_EN_HI 16
++#define MISC_PKT_CLS_MIB_EN_SZ 1
++#define MISC_PKT_CLS_ONGOING_MSK 0x00020000
++#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff
++#define MISC_PKT_CLS_ONGOING_SFT 17
++#define MISC_PKT_CLS_ONGOING_HI 17
++#define MISC_PKT_CLS_ONGOING_SZ 1
++#define MTX_WSID0_SUCC_MSK 0x0000ffff
++#define MTX_WSID0_SUCC_I_MSK 0xffff0000
++#define MTX_WSID0_SUCC_SFT 0
++#define MTX_WSID0_SUCC_HI 15
++#define MTX_WSID0_SUCC_SZ 16
++#define MTX_WSID0_FRM_MSK 0x0000ffff
++#define MTX_WSID0_FRM_I_MSK 0xffff0000
++#define MTX_WSID0_FRM_SFT 0
++#define MTX_WSID0_FRM_HI 15
++#define MTX_WSID0_FRM_SZ 16
++#define MTX_WSID0_RETRY_MSK 0x0000ffff
++#define MTX_WSID0_RETRY_I_MSK 0xffff0000
++#define MTX_WSID0_RETRY_SFT 0
++#define MTX_WSID0_RETRY_HI 15
++#define MTX_WSID0_RETRY_SZ 16
++#define MTX_WSID0_TOTAL_MSK 0x0000ffff
++#define MTX_WSID0_TOTAL_I_MSK 0xffff0000
++#define MTX_WSID0_TOTAL_SFT 0
++#define MTX_WSID0_TOTAL_HI 15
++#define MTX_WSID0_TOTAL_SZ 16
++#define MTX_GRP_MSK 0x000fffff
++#define MTX_GRP_I_MSK 0xfff00000
++#define MTX_GRP_SFT 0
++#define MTX_GRP_HI 19
++#define MTX_GRP_SZ 20
++#define MTX_FAIL_MSK 0x0000ffff
++#define MTX_FAIL_I_MSK 0xffff0000
++#define MTX_FAIL_SFT 0
++#define MTX_FAIL_HI 15
++#define MTX_FAIL_SZ 16
++#define MTX_RETRY_MSK 0x000fffff
++#define MTX_RETRY_I_MSK 0xfff00000
++#define MTX_RETRY_SFT 0
++#define MTX_RETRY_HI 19
++#define MTX_RETRY_SZ 20
++#define MTX_MULTI_RETRY_MSK 0x000fffff
++#define MTX_MULTI_RETRY_I_MSK 0xfff00000
++#define MTX_MULTI_RETRY_SFT 0
++#define MTX_MULTI_RETRY_HI 19
++#define MTX_MULTI_RETRY_SZ 20
++#define MTX_RTS_SUCC_MSK 0x0000ffff
++#define MTX_RTS_SUCC_I_MSK 0xffff0000
++#define MTX_RTS_SUCC_SFT 0
++#define MTX_RTS_SUCC_HI 15
++#define MTX_RTS_SUCC_SZ 16
++#define MTX_RTS_FAIL_MSK 0x0000ffff
++#define MTX_RTS_FAIL_I_MSK 0xffff0000
++#define MTX_RTS_FAIL_SFT 0
++#define MTX_RTS_FAIL_HI 15
++#define MTX_RTS_FAIL_SZ 16
++#define MTX_ACK_FAIL_MSK 0x0000ffff
++#define MTX_ACK_FAIL_I_MSK 0xffff0000
++#define MTX_ACK_FAIL_SFT 0
++#define MTX_ACK_FAIL_HI 15
++#define MTX_ACK_FAIL_SZ 16
++#define MTX_FRM_MSK 0x000fffff
++#define MTX_FRM_I_MSK 0xfff00000
++#define MTX_FRM_SFT 0
++#define MTX_FRM_HI 19
++#define MTX_FRM_SZ 20
++#define MTX_ACK_TX_MSK 0x0000ffff
++#define MTX_ACK_TX_I_MSK 0xffff0000
++#define MTX_ACK_TX_SFT 0
++#define MTX_ACK_TX_HI 15
++#define MTX_ACK_TX_SZ 16
++#define MTX_CTS_TX_MSK 0x0000ffff
++#define MTX_CTS_TX_I_MSK 0xffff0000
++#define MTX_CTS_TX_SFT 0
++#define MTX_CTS_TX_HI 15
++#define MTX_CTS_TX_SZ 16
++#define MRX_DUP_MSK 0x0000ffff
++#define MRX_DUP_I_MSK 0xffff0000
++#define MRX_DUP_SFT 0
++#define MRX_DUP_HI 15
++#define MRX_DUP_SZ 16
++#define MRX_FRG_MSK 0x000fffff
++#define MRX_FRG_I_MSK 0xfff00000
++#define MRX_FRG_SFT 0
++#define MRX_FRG_HI 19
++#define MRX_FRG_SZ 20
++#define MRX_GRP_MSK 0x000fffff
++#define MRX_GRP_I_MSK 0xfff00000
++#define MRX_GRP_SFT 0
++#define MRX_GRP_HI 19
++#define MRX_GRP_SZ 20
++#define MRX_FCS_ERR_MSK 0x0000ffff
++#define MRX_FCS_ERR_I_MSK 0xffff0000
++#define MRX_FCS_ERR_SFT 0
++#define MRX_FCS_ERR_HI 15
++#define MRX_FCS_ERR_SZ 16
++#define MRX_FCS_SUC_MSK 0x0000ffff
++#define MRX_FCS_SUC_I_MSK 0xffff0000
++#define MRX_FCS_SUC_SFT 0
++#define MRX_FCS_SUC_HI 15
++#define MRX_FCS_SUC_SZ 16
++#define MRX_MISS_MSK 0x0000ffff
++#define MRX_MISS_I_MSK 0xffff0000
++#define MRX_MISS_SFT 0
++#define MRX_MISS_HI 15
++#define MRX_MISS_SZ 16
++#define MRX_ALC_FAIL_MSK 0x0000ffff
++#define MRX_ALC_FAIL_I_MSK 0xffff0000
++#define MRX_ALC_FAIL_SFT 0
++#define MRX_ALC_FAIL_HI 15
++#define MRX_ALC_FAIL_SZ 16
++#define MRX_DAT_NTF_MSK 0x0000ffff
++#define MRX_DAT_NTF_I_MSK 0xffff0000
++#define MRX_DAT_NTF_SFT 0
++#define MRX_DAT_NTF_HI 15
++#define MRX_DAT_NTF_SZ 16
++#define MRX_RTS_NTF_MSK 0x0000ffff
++#define MRX_RTS_NTF_I_MSK 0xffff0000
++#define MRX_RTS_NTF_SFT 0
++#define MRX_RTS_NTF_HI 15
++#define MRX_RTS_NTF_SZ 16
++#define MRX_CTS_NTF_MSK 0x0000ffff
++#define MRX_CTS_NTF_I_MSK 0xffff0000
++#define MRX_CTS_NTF_SFT 0
++#define MRX_CTS_NTF_HI 15
++#define MRX_CTS_NTF_SZ 16
++#define MRX_ACK_NTF_MSK 0x0000ffff
++#define MRX_ACK_NTF_I_MSK 0xffff0000
++#define MRX_ACK_NTF_SFT 0
++#define MRX_ACK_NTF_HI 15
++#define MRX_ACK_NTF_SZ 16
++#define MRX_BA_NTF_MSK 0x0000ffff
++#define MRX_BA_NTF_I_MSK 0xffff0000
++#define MRX_BA_NTF_SFT 0
++#define MRX_BA_NTF_HI 15
++#define MRX_BA_NTF_SZ 16
++#define MRX_DATA_NTF_MSK 0x0000ffff
++#define MRX_DATA_NTF_I_MSK 0xffff0000
++#define MRX_DATA_NTF_SFT 0
++#define MRX_DATA_NTF_HI 15
++#define MRX_DATA_NTF_SZ 16
++#define MRX_MNG_NTF_MSK 0x0000ffff
++#define MRX_MNG_NTF_I_MSK 0xffff0000
++#define MRX_MNG_NTF_SFT 0
++#define MRX_MNG_NTF_HI 15
++#define MRX_MNG_NTF_SZ 16
++#define MRX_DAT_CRC_NTF_MSK 0x0000ffff
++#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000
++#define MRX_DAT_CRC_NTF_SFT 0
++#define MRX_DAT_CRC_NTF_HI 15
++#define MRX_DAT_CRC_NTF_SZ 16
++#define MRX_BAR_NTF_MSK 0x0000ffff
++#define MRX_BAR_NTF_I_MSK 0xffff0000
++#define MRX_BAR_NTF_SFT 0
++#define MRX_BAR_NTF_HI 15
++#define MRX_BAR_NTF_SZ 16
++#define MRX_MB_MISS_MSK 0x0000ffff
++#define MRX_MB_MISS_I_MSK 0xffff0000
++#define MRX_MB_MISS_SFT 0
++#define MRX_MB_MISS_HI 15
++#define MRX_MB_MISS_SZ 16
++#define MRX_NIDLE_MISS_MSK 0x0000ffff
++#define MRX_NIDLE_MISS_I_MSK 0xffff0000
++#define MRX_NIDLE_MISS_SFT 0
++#define MRX_NIDLE_MISS_HI 15
++#define MRX_NIDLE_MISS_SZ 16
++#define MRX_CSR_NTF_MSK 0x0000ffff
++#define MRX_CSR_NTF_I_MSK 0xffff0000
++#define MRX_CSR_NTF_SFT 0
++#define MRX_CSR_NTF_HI 15
++#define MRX_CSR_NTF_SZ 16
++#define DBG_Q0_SUCC_MSK 0x0000ffff
++#define DBG_Q0_SUCC_I_MSK 0xffff0000
++#define DBG_Q0_SUCC_SFT 0
++#define DBG_Q0_SUCC_HI 15
++#define DBG_Q0_SUCC_SZ 16
++#define DBG_Q0_FAIL_MSK 0x0000ffff
++#define DBG_Q0_FAIL_I_MSK 0xffff0000
++#define DBG_Q0_FAIL_SFT 0
++#define DBG_Q0_FAIL_HI 15
++#define DBG_Q0_FAIL_SZ 16
++#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q0_ACK_SUCC_SFT 0
++#define DBG_Q0_ACK_SUCC_HI 15
++#define DBG_Q0_ACK_SUCC_SZ 16
++#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q0_ACK_FAIL_SFT 0
++#define DBG_Q0_ACK_FAIL_HI 15
++#define DBG_Q0_ACK_FAIL_SZ 16
++#define DBG_Q1_SUCC_MSK 0x0000ffff
++#define DBG_Q1_SUCC_I_MSK 0xffff0000
++#define DBG_Q1_SUCC_SFT 0
++#define DBG_Q1_SUCC_HI 15
++#define DBG_Q1_SUCC_SZ 16
++#define DBG_Q1_FAIL_MSK 0x0000ffff
++#define DBG_Q1_FAIL_I_MSK 0xffff0000
++#define DBG_Q1_FAIL_SFT 0
++#define DBG_Q1_FAIL_HI 15
++#define DBG_Q1_FAIL_SZ 16
++#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q1_ACK_SUCC_SFT 0
++#define DBG_Q1_ACK_SUCC_HI 15
++#define DBG_Q1_ACK_SUCC_SZ 16
++#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q1_ACK_FAIL_SFT 0
++#define DBG_Q1_ACK_FAIL_HI 15
++#define DBG_Q1_ACK_FAIL_SZ 16
++#define DBG_Q2_SUCC_MSK 0x0000ffff
++#define DBG_Q2_SUCC_I_MSK 0xffff0000
++#define DBG_Q2_SUCC_SFT 0
++#define DBG_Q2_SUCC_HI 15
++#define DBG_Q2_SUCC_SZ 16
++#define DBG_Q2_FAIL_MSK 0x0000ffff
++#define DBG_Q2_FAIL_I_MSK 0xffff0000
++#define DBG_Q2_FAIL_SFT 0
++#define DBG_Q2_FAIL_HI 15
++#define DBG_Q2_FAIL_SZ 16
++#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q2_ACK_SUCC_SFT 0
++#define DBG_Q2_ACK_SUCC_HI 15
++#define DBG_Q2_ACK_SUCC_SZ 16
++#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q2_ACK_FAIL_SFT 0
++#define DBG_Q2_ACK_FAIL_HI 15
++#define DBG_Q2_ACK_FAIL_SZ 16
++#define DBG_Q3_SUCC_MSK 0x0000ffff
++#define DBG_Q3_SUCC_I_MSK 0xffff0000
++#define DBG_Q3_SUCC_SFT 0
++#define DBG_Q3_SUCC_HI 15
++#define DBG_Q3_SUCC_SZ 16
++#define DBG_Q3_FAIL_MSK 0x0000ffff
++#define DBG_Q3_FAIL_I_MSK 0xffff0000
++#define DBG_Q3_FAIL_SFT 0
++#define DBG_Q3_FAIL_HI 15
++#define DBG_Q3_FAIL_SZ 16
++#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q3_ACK_SUCC_SFT 0
++#define DBG_Q3_ACK_SUCC_HI 15
++#define DBG_Q3_ACK_SUCC_SZ 16
++#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q3_ACK_FAIL_SFT 0
++#define DBG_Q3_ACK_FAIL_HI 15
++#define DBG_Q3_ACK_FAIL_SZ 16
++#define SCRT_TKIP_CERR_MSK 0x000fffff
++#define SCRT_TKIP_CERR_I_MSK 0xfff00000
++#define SCRT_TKIP_CERR_SFT 0
++#define SCRT_TKIP_CERR_HI 19
++#define SCRT_TKIP_CERR_SZ 20
++#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff
++#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000
++#define SCRT_TKIP_MIC_ERR_SFT 0
++#define SCRT_TKIP_MIC_ERR_HI 19
++#define SCRT_TKIP_MIC_ERR_SZ 20
++#define SCRT_TKIP_RPLY_MSK 0x000fffff
++#define SCRT_TKIP_RPLY_I_MSK 0xfff00000
++#define SCRT_TKIP_RPLY_SFT 0
++#define SCRT_TKIP_RPLY_HI 19
++#define SCRT_TKIP_RPLY_SZ 20
++#define SCRT_CCMP_RPLY_MSK 0x000fffff
++#define SCRT_CCMP_RPLY_I_MSK 0xfff00000
++#define SCRT_CCMP_RPLY_SFT 0
++#define SCRT_CCMP_RPLY_HI 19
++#define SCRT_CCMP_RPLY_SZ 20
++#define SCRT_CCMP_CERR_MSK 0x000fffff
++#define SCRT_CCMP_CERR_I_MSK 0xfff00000
++#define SCRT_CCMP_CERR_SFT 0
++#define SCRT_CCMP_CERR_HI 19
++#define SCRT_CCMP_CERR_SZ 20
++#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff
++#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000
++#define DBG_LEN_CRC_FAIL_SFT 0
++#define DBG_LEN_CRC_FAIL_HI 15
++#define DBG_LEN_CRC_FAIL_SZ 16
++#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff
++#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000
++#define DBG_LEN_ALC_FAIL_SFT 0
++#define DBG_LEN_ALC_FAIL_HI 15
++#define DBG_LEN_ALC_FAIL_SZ 16
++#define DBG_AMPDU_PASS_MSK 0x0000ffff
++#define DBG_AMPDU_PASS_I_MSK 0xffff0000
++#define DBG_AMPDU_PASS_SFT 0
++#define DBG_AMPDU_PASS_HI 15
++#define DBG_AMPDU_PASS_SZ 16
++#define DBG_AMPDU_FAIL_MSK 0x0000ffff
++#define DBG_AMPDU_FAIL_I_MSK 0xffff0000
++#define DBG_AMPDU_FAIL_SFT 0
++#define DBG_AMPDU_FAIL_HI 15
++#define DBG_AMPDU_FAIL_SZ 16
++#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff
++#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000
++#define RXID_ALC_CNT_FAIL_SFT 0
++#define RXID_ALC_CNT_FAIL_HI 15
++#define RXID_ALC_CNT_FAIL_SZ 16
++#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff
++#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000
++#define RXID_ALC_LEN_FAIL_SFT 0
++#define RXID_ALC_LEN_FAIL_HI 15
++#define RXID_ALC_LEN_FAIL_SZ 16
++#define CBR_RG_EN_MANUAL_MSK 0x00000001
++#define CBR_RG_EN_MANUAL_I_MSK 0xfffffffe
++#define CBR_RG_EN_MANUAL_SFT 0
++#define CBR_RG_EN_MANUAL_HI 0
++#define CBR_RG_EN_MANUAL_SZ 1
++#define CBR_RG_TX_EN_MSK 0x00000002
++#define CBR_RG_TX_EN_I_MSK 0xfffffffd
++#define CBR_RG_TX_EN_SFT 1
++#define CBR_RG_TX_EN_HI 1
++#define CBR_RG_TX_EN_SZ 1
++#define CBR_RG_TX_PA_EN_MSK 0x00000004
++#define CBR_RG_TX_PA_EN_I_MSK 0xfffffffb
++#define CBR_RG_TX_PA_EN_SFT 2
++#define CBR_RG_TX_PA_EN_HI 2
++#define CBR_RG_TX_PA_EN_SZ 1
++#define CBR_RG_TX_DAC_EN_MSK 0x00000008
++#define CBR_RG_TX_DAC_EN_I_MSK 0xfffffff7
++#define CBR_RG_TX_DAC_EN_SFT 3
++#define CBR_RG_TX_DAC_EN_HI 3
++#define CBR_RG_TX_DAC_EN_SZ 1
++#define CBR_RG_RX_AGC_MSK 0x00000010
++#define CBR_RG_RX_AGC_I_MSK 0xffffffef
++#define CBR_RG_RX_AGC_SFT 4
++#define CBR_RG_RX_AGC_HI 4
++#define CBR_RG_RX_AGC_SZ 1
++#define CBR_RG_RX_GAIN_MANUAL_MSK 0x00000020
++#define CBR_RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
++#define CBR_RG_RX_GAIN_MANUAL_SFT 5
++#define CBR_RG_RX_GAIN_MANUAL_HI 5
++#define CBR_RG_RX_GAIN_MANUAL_SZ 1
++#define CBR_RG_RFG_MSK 0x000000c0
++#define CBR_RG_RFG_I_MSK 0xffffff3f
++#define CBR_RG_RFG_SFT 6
++#define CBR_RG_RFG_HI 7
++#define CBR_RG_RFG_SZ 2
++#define CBR_RG_PGAG_MSK 0x00000f00
++#define CBR_RG_PGAG_I_MSK 0xfffff0ff
++#define CBR_RG_PGAG_SFT 8
++#define CBR_RG_PGAG_HI 11
++#define CBR_RG_PGAG_SZ 4
++#define CBR_RG_MODE_MSK 0x00003000
++#define CBR_RG_MODE_I_MSK 0xffffcfff
++#define CBR_RG_MODE_SFT 12
++#define CBR_RG_MODE_HI 13
++#define CBR_RG_MODE_SZ 2
++#define CBR_RG_EN_TX_TRSW_MSK 0x00004000
++#define CBR_RG_EN_TX_TRSW_I_MSK 0xffffbfff
++#define CBR_RG_EN_TX_TRSW_SFT 14
++#define CBR_RG_EN_TX_TRSW_HI 14
++#define CBR_RG_EN_TX_TRSW_SZ 1
++#define CBR_RG_EN_SX_MSK 0x00008000
++#define CBR_RG_EN_SX_I_MSK 0xffff7fff
++#define CBR_RG_EN_SX_SFT 15
++#define CBR_RG_EN_SX_HI 15
++#define CBR_RG_EN_SX_SZ 1
++#define CBR_RG_EN_RX_LNA_MSK 0x00010000
++#define CBR_RG_EN_RX_LNA_I_MSK 0xfffeffff
++#define CBR_RG_EN_RX_LNA_SFT 16
++#define CBR_RG_EN_RX_LNA_HI 16
++#define CBR_RG_EN_RX_LNA_SZ 1
++#define CBR_RG_EN_RX_MIXER_MSK 0x00020000
++#define CBR_RG_EN_RX_MIXER_I_MSK 0xfffdffff
++#define CBR_RG_EN_RX_MIXER_SFT 17
++#define CBR_RG_EN_RX_MIXER_HI 17
++#define CBR_RG_EN_RX_MIXER_SZ 1
++#define CBR_RG_EN_RX_DIV2_MSK 0x00040000
++#define CBR_RG_EN_RX_DIV2_I_MSK 0xfffbffff
++#define CBR_RG_EN_RX_DIV2_SFT 18
++#define CBR_RG_EN_RX_DIV2_HI 18
++#define CBR_RG_EN_RX_DIV2_SZ 1
++#define CBR_RG_EN_RX_LOBUF_MSK 0x00080000
++#define CBR_RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
++#define CBR_RG_EN_RX_LOBUF_SFT 19
++#define CBR_RG_EN_RX_LOBUF_HI 19
++#define CBR_RG_EN_RX_LOBUF_SZ 1
++#define CBR_RG_EN_RX_TZ_MSK 0x00100000
++#define CBR_RG_EN_RX_TZ_I_MSK 0xffefffff
++#define CBR_RG_EN_RX_TZ_SFT 20
++#define CBR_RG_EN_RX_TZ_HI 20
++#define CBR_RG_EN_RX_TZ_SZ 1
++#define CBR_RG_EN_RX_FILTER_MSK 0x00200000
++#define CBR_RG_EN_RX_FILTER_I_MSK 0xffdfffff
++#define CBR_RG_EN_RX_FILTER_SFT 21
++#define CBR_RG_EN_RX_FILTER_HI 21
++#define CBR_RG_EN_RX_FILTER_SZ 1
++#define CBR_RG_EN_RX_HPF_MSK 0x00400000
++#define CBR_RG_EN_RX_HPF_I_MSK 0xffbfffff
++#define CBR_RG_EN_RX_HPF_SFT 22
++#define CBR_RG_EN_RX_HPF_HI 22
++#define CBR_RG_EN_RX_HPF_SZ 1
++#define CBR_RG_EN_RX_RSSI_MSK 0x00800000
++#define CBR_RG_EN_RX_RSSI_I_MSK 0xff7fffff
++#define CBR_RG_EN_RX_RSSI_SFT 23
++#define CBR_RG_EN_RX_RSSI_HI 23
++#define CBR_RG_EN_RX_RSSI_SZ 1
++#define CBR_RG_EN_ADC_MSK 0x01000000
++#define CBR_RG_EN_ADC_I_MSK 0xfeffffff
++#define CBR_RG_EN_ADC_SFT 24
++#define CBR_RG_EN_ADC_HI 24
++#define CBR_RG_EN_ADC_SZ 1
++#define CBR_RG_EN_TX_MOD_MSK 0x02000000
++#define CBR_RG_EN_TX_MOD_I_MSK 0xfdffffff
++#define CBR_RG_EN_TX_MOD_SFT 25
++#define CBR_RG_EN_TX_MOD_HI 25
++#define CBR_RG_EN_TX_MOD_SZ 1
++#define CBR_RG_EN_TX_DIV2_MSK 0x04000000
++#define CBR_RG_EN_TX_DIV2_I_MSK 0xfbffffff
++#define CBR_RG_EN_TX_DIV2_SFT 26
++#define CBR_RG_EN_TX_DIV2_HI 26
++#define CBR_RG_EN_TX_DIV2_SZ 1
++#define CBR_RG_EN_TX_DIV2_BUF_MSK 0x08000000
++#define CBR_RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
++#define CBR_RG_EN_TX_DIV2_BUF_SFT 27
++#define CBR_RG_EN_TX_DIV2_BUF_HI 27
++#define CBR_RG_EN_TX_DIV2_BUF_SZ 1
++#define CBR_RG_EN_TX_LOBF_MSK 0x10000000
++#define CBR_RG_EN_TX_LOBF_I_MSK 0xefffffff
++#define CBR_RG_EN_TX_LOBF_SFT 28
++#define CBR_RG_EN_TX_LOBF_HI 28
++#define CBR_RG_EN_TX_LOBF_SZ 1
++#define CBR_RG_EN_RX_LOBF_MSK 0x20000000
++#define CBR_RG_EN_RX_LOBF_I_MSK 0xdfffffff
++#define CBR_RG_EN_RX_LOBF_SFT 29
++#define CBR_RG_EN_RX_LOBF_HI 29
++#define CBR_RG_EN_RX_LOBF_SZ 1
++#define CBR_RG_SEL_DPLL_CLK_MSK 0x40000000
++#define CBR_RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
++#define CBR_RG_SEL_DPLL_CLK_SFT 30
++#define CBR_RG_SEL_DPLL_CLK_HI 30
++#define CBR_RG_SEL_DPLL_CLK_SZ 1
++#define CBR_RG_EN_TX_DPD_MSK 0x00000001
++#define CBR_RG_EN_TX_DPD_I_MSK 0xfffffffe
++#define CBR_RG_EN_TX_DPD_SFT 0
++#define CBR_RG_EN_TX_DPD_HI 0
++#define CBR_RG_EN_TX_DPD_SZ 1
++#define CBR_RG_EN_TX_TSSI_MSK 0x00000002
++#define CBR_RG_EN_TX_TSSI_I_MSK 0xfffffffd
++#define CBR_RG_EN_TX_TSSI_SFT 1
++#define CBR_RG_EN_TX_TSSI_HI 1
++#define CBR_RG_EN_TX_TSSI_SZ 1
++#define CBR_RG_EN_RX_IQCAL_MSK 0x00000004
++#define CBR_RG_EN_RX_IQCAL_I_MSK 0xfffffffb
++#define CBR_RG_EN_RX_IQCAL_SFT 2
++#define CBR_RG_EN_RX_IQCAL_HI 2
++#define CBR_RG_EN_RX_IQCAL_SZ 1
++#define CBR_RG_EN_TX_DAC_CAL_MSK 0x00000008
++#define CBR_RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
++#define CBR_RG_EN_TX_DAC_CAL_SFT 3
++#define CBR_RG_EN_TX_DAC_CAL_HI 3
++#define CBR_RG_EN_TX_DAC_CAL_SZ 1
++#define CBR_RG_EN_TX_SELF_MIXER_MSK 0x00000010
++#define CBR_RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
++#define CBR_RG_EN_TX_SELF_MIXER_SFT 4
++#define CBR_RG_EN_TX_SELF_MIXER_HI 4
++#define CBR_RG_EN_TX_SELF_MIXER_SZ 1
++#define CBR_RG_EN_TX_DAC_OUT_MSK 0x00000020
++#define CBR_RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
++#define CBR_RG_EN_TX_DAC_OUT_SFT 5
++#define CBR_RG_EN_TX_DAC_OUT_HI 5
++#define CBR_RG_EN_TX_DAC_OUT_SZ 1
++#define CBR_RG_EN_LDO_RX_FE_MSK 0x00000040
++#define CBR_RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
++#define CBR_RG_EN_LDO_RX_FE_SFT 6
++#define CBR_RG_EN_LDO_RX_FE_HI 6
++#define CBR_RG_EN_LDO_RX_FE_SZ 1
++#define CBR_RG_EN_LDO_ABB_MSK 0x00000080
++#define CBR_RG_EN_LDO_ABB_I_MSK 0xffffff7f
++#define CBR_RG_EN_LDO_ABB_SFT 7
++#define CBR_RG_EN_LDO_ABB_HI 7
++#define CBR_RG_EN_LDO_ABB_SZ 1
++#define CBR_RG_EN_LDO_AFE_MSK 0x00000100
++#define CBR_RG_EN_LDO_AFE_I_MSK 0xfffffeff
++#define CBR_RG_EN_LDO_AFE_SFT 8
++#define CBR_RG_EN_LDO_AFE_HI 8
++#define CBR_RG_EN_LDO_AFE_SZ 1
++#define CBR_RG_EN_SX_CHPLDO_MSK 0x00000200
++#define CBR_RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
++#define CBR_RG_EN_SX_CHPLDO_SFT 9
++#define CBR_RG_EN_SX_CHPLDO_HI 9
++#define CBR_RG_EN_SX_CHPLDO_SZ 1
++#define CBR_RG_EN_SX_LOBFLDO_MSK 0x00000400
++#define CBR_RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
++#define CBR_RG_EN_SX_LOBFLDO_SFT 10
++#define CBR_RG_EN_SX_LOBFLDO_HI 10
++#define CBR_RG_EN_SX_LOBFLDO_SZ 1
++#define CBR_RG_EN_IREF_RX_MSK 0x00000800
++#define CBR_RG_EN_IREF_RX_I_MSK 0xfffff7ff
++#define CBR_RG_EN_IREF_RX_SFT 11
++#define CBR_RG_EN_IREF_RX_HI 11
++#define CBR_RG_EN_IREF_RX_SZ 1
++#define CBR_RG_DCDC_MODE_MSK 0x00001000
++#define CBR_RG_DCDC_MODE_I_MSK 0xffffefff
++#define CBR_RG_DCDC_MODE_SFT 12
++#define CBR_RG_DCDC_MODE_HI 12
++#define CBR_RG_DCDC_MODE_SZ 1
++#define CBR_RG_LDO_LEVEL_RX_FE_MSK 0x00000007
++#define CBR_RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
++#define CBR_RG_LDO_LEVEL_RX_FE_SFT 0
++#define CBR_RG_LDO_LEVEL_RX_FE_HI 2
++#define CBR_RG_LDO_LEVEL_RX_FE_SZ 3
++#define CBR_RG_LDO_LEVEL_ABB_MSK 0x00000038
++#define CBR_RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
++#define CBR_RG_LDO_LEVEL_ABB_SFT 3
++#define CBR_RG_LDO_LEVEL_ABB_HI 5
++#define CBR_RG_LDO_LEVEL_ABB_SZ 3
++#define CBR_RG_LDO_LEVEL_AFE_MSK 0x000001c0
++#define CBR_RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
++#define CBR_RG_LDO_LEVEL_AFE_SFT 6
++#define CBR_RG_LDO_LEVEL_AFE_HI 8
++#define CBR_RG_LDO_LEVEL_AFE_SZ 3
++#define CBR_RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
++#define CBR_RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
++#define CBR_RG_SX_LDO_CHP_LEVEL_SFT 9
++#define CBR_RG_SX_LDO_CHP_LEVEL_HI 11
++#define CBR_RG_SX_LDO_CHP_LEVEL_SZ 3
++#define CBR_RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
++#define CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
++#define CBR_RG_SX_LDO_LOBF_LEVEL_SFT 12
++#define CBR_RG_SX_LDO_LOBF_LEVEL_HI 14
++#define CBR_RG_SX_LDO_LOBF_LEVEL_SZ 3
++#define CBR_RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
++#define CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
++#define CBR_RG_SX_LDO_XOSC_LEVEL_SFT 15
++#define CBR_RG_SX_LDO_XOSC_LEVEL_HI 17
++#define CBR_RG_SX_LDO_XOSC_LEVEL_SZ 3
++#define CBR_RG_DP_LDO_LEVEL_MSK 0x001c0000
++#define CBR_RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
++#define CBR_RG_DP_LDO_LEVEL_SFT 18
++#define CBR_RG_DP_LDO_LEVEL_HI 20
++#define CBR_RG_DP_LDO_LEVEL_SZ 3
++#define CBR_RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
++#define CBR_RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
++#define CBR_RG_SX_LDO_VCO_LEVEL_SFT 21
++#define CBR_RG_SX_LDO_VCO_LEVEL_HI 23
++#define CBR_RG_SX_LDO_VCO_LEVEL_SZ 3
++#define CBR_RG_TX_LDO_TX_LEVEL_MSK 0x07000000
++#define CBR_RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
++#define CBR_RG_TX_LDO_TX_LEVEL_SFT 24
++#define CBR_RG_TX_LDO_TX_LEVEL_HI 26
++#define CBR_RG_TX_LDO_TX_LEVEL_SZ 3
++#define CBR_RG_BUCK_LEVEL_MSK 0x38000000
++#define CBR_RG_BUCK_LEVEL_I_MSK 0xc7ffffff
++#define CBR_RG_BUCK_LEVEL_SFT 27
++#define CBR_RG_BUCK_LEVEL_HI 29
++#define CBR_RG_BUCK_LEVEL_SZ 3
++#define CBR_RG_EN_RX_PADSW_MSK 0x00000001
++#define CBR_RG_EN_RX_PADSW_I_MSK 0xfffffffe
++#define CBR_RG_EN_RX_PADSW_SFT 0
++#define CBR_RG_EN_RX_PADSW_HI 0
++#define CBR_RG_EN_RX_PADSW_SZ 1
++#define CBR_RG_EN_RX_TESTNODE_MSK 0x00000002
++#define CBR_RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
++#define CBR_RG_EN_RX_TESTNODE_SFT 1
++#define CBR_RG_EN_RX_TESTNODE_HI 1
++#define CBR_RG_EN_RX_TESTNODE_SZ 1
++#define CBR_RG_RX_ABBCFIX_MSK 0x00000004
++#define CBR_RG_RX_ABBCFIX_I_MSK 0xfffffffb
++#define CBR_RG_RX_ABBCFIX_SFT 2
++#define CBR_RG_RX_ABBCFIX_HI 2
++#define CBR_RG_RX_ABBCFIX_SZ 1
++#define CBR_RG_RX_ABBCTUNE_MSK 0x000001f8
++#define CBR_RG_RX_ABBCTUNE_I_MSK 0xfffffe07
++#define CBR_RG_RX_ABBCTUNE_SFT 3
++#define CBR_RG_RX_ABBCTUNE_HI 8
++#define CBR_RG_RX_ABBCTUNE_SZ 6
++#define CBR_RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
++#define CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
++#define CBR_RG_RX_ABBOUT_TRI_STATE_SFT 9
++#define CBR_RG_RX_ABBOUT_TRI_STATE_HI 9
++#define CBR_RG_RX_ABBOUT_TRI_STATE_SZ 1
++#define CBR_RG_RX_ABB_N_MODE_MSK 0x00000400
++#define CBR_RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
++#define CBR_RG_RX_ABB_N_MODE_SFT 10
++#define CBR_RG_RX_ABB_N_MODE_HI 10
++#define CBR_RG_RX_ABB_N_MODE_SZ 1
++#define CBR_RG_RX_EN_LOOPA_MSK 0x00000800
++#define CBR_RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
++#define CBR_RG_RX_EN_LOOPA_SFT 11
++#define CBR_RG_RX_EN_LOOPA_HI 11
++#define CBR_RG_RX_EN_LOOPA_SZ 1
++#define CBR_RG_RX_FILTERI1ST_MSK 0x00003000
++#define CBR_RG_RX_FILTERI1ST_I_MSK 0xffffcfff
++#define CBR_RG_RX_FILTERI1ST_SFT 12
++#define CBR_RG_RX_FILTERI1ST_HI 13
++#define CBR_RG_RX_FILTERI1ST_SZ 2
++#define CBR_RG_RX_FILTERI2ND_MSK 0x0000c000
++#define CBR_RG_RX_FILTERI2ND_I_MSK 0xffff3fff
++#define CBR_RG_RX_FILTERI2ND_SFT 14
++#define CBR_RG_RX_FILTERI2ND_HI 15
++#define CBR_RG_RX_FILTERI2ND_SZ 2
++#define CBR_RG_RX_FILTERI3RD_MSK 0x00030000
++#define CBR_RG_RX_FILTERI3RD_I_MSK 0xfffcffff
++#define CBR_RG_RX_FILTERI3RD_SFT 16
++#define CBR_RG_RX_FILTERI3RD_HI 17
++#define CBR_RG_RX_FILTERI3RD_SZ 2
++#define CBR_RG_RX_FILTERI_COURSE_MSK 0x000c0000
++#define CBR_RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
++#define CBR_RG_RX_FILTERI_COURSE_SFT 18
++#define CBR_RG_RX_FILTERI_COURSE_HI 19
++#define CBR_RG_RX_FILTERI_COURSE_SZ 2
++#define CBR_RG_RX_FILTERVCM_MSK 0x00300000
++#define CBR_RG_RX_FILTERVCM_I_MSK 0xffcfffff
++#define CBR_RG_RX_FILTERVCM_SFT 20
++#define CBR_RG_RX_FILTERVCM_HI 21
++#define CBR_RG_RX_FILTERVCM_SZ 2
++#define CBR_RG_RX_HPF3M_MSK 0x00400000
++#define CBR_RG_RX_HPF3M_I_MSK 0xffbfffff
++#define CBR_RG_RX_HPF3M_SFT 22
++#define CBR_RG_RX_HPF3M_HI 22
++#define CBR_RG_RX_HPF3M_SZ 1
++#define CBR_RG_RX_HPF300K_MSK 0x00800000
++#define CBR_RG_RX_HPF300K_I_MSK 0xff7fffff
++#define CBR_RG_RX_HPF300K_SFT 23
++#define CBR_RG_RX_HPF300K_HI 23
++#define CBR_RG_RX_HPF300K_SZ 1
++#define CBR_RG_RX_HPFI_MSK 0x03000000
++#define CBR_RG_RX_HPFI_I_MSK 0xfcffffff
++#define CBR_RG_RX_HPFI_SFT 24
++#define CBR_RG_RX_HPFI_HI 25
++#define CBR_RG_RX_HPFI_SZ 2
++#define CBR_RG_RX_HPF_FINALCORNER_MSK 0x0c000000
++#define CBR_RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
++#define CBR_RG_RX_HPF_FINALCORNER_SFT 26
++#define CBR_RG_RX_HPF_FINALCORNER_HI 27
++#define CBR_RG_RX_HPF_FINALCORNER_SZ 2
++#define CBR_RG_RX_HPF_SETTLE1_C_MSK 0x30000000
++#define CBR_RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
++#define CBR_RG_RX_HPF_SETTLE1_C_SFT 28
++#define CBR_RG_RX_HPF_SETTLE1_C_HI 29
++#define CBR_RG_RX_HPF_SETTLE1_C_SZ 2
++#define CBR_RG_RX_HPF_SETTLE1_R_MSK 0x00000003
++#define CBR_RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
++#define CBR_RG_RX_HPF_SETTLE1_R_SFT 0
++#define CBR_RG_RX_HPF_SETTLE1_R_HI 1
++#define CBR_RG_RX_HPF_SETTLE1_R_SZ 2
++#define CBR_RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
++#define CBR_RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
++#define CBR_RG_RX_HPF_SETTLE2_C_SFT 2
++#define CBR_RG_RX_HPF_SETTLE2_C_HI 3
++#define CBR_RG_RX_HPF_SETTLE2_C_SZ 2
++#define CBR_RG_RX_HPF_SETTLE2_R_MSK 0x00000030
++#define CBR_RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
++#define CBR_RG_RX_HPF_SETTLE2_R_SFT 4
++#define CBR_RG_RX_HPF_SETTLE2_R_HI 5
++#define CBR_RG_RX_HPF_SETTLE2_R_SZ 2
++#define CBR_RG_RX_HPF_VCMCON2_MSK 0x000000c0
++#define CBR_RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
++#define CBR_RG_RX_HPF_VCMCON2_SFT 6
++#define CBR_RG_RX_HPF_VCMCON2_HI 7
++#define CBR_RG_RX_HPF_VCMCON2_SZ 2
++#define CBR_RG_RX_HPF_VCMCON_MSK 0x00000300
++#define CBR_RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
++#define CBR_RG_RX_HPF_VCMCON_SFT 8
++#define CBR_RG_RX_HPF_VCMCON_HI 9
++#define CBR_RG_RX_HPF_VCMCON_SZ 2
++#define CBR_RG_RX_OUTVCM_MSK 0x00000c00
++#define CBR_RG_RX_OUTVCM_I_MSK 0xfffff3ff
++#define CBR_RG_RX_OUTVCM_SFT 10
++#define CBR_RG_RX_OUTVCM_HI 11
++#define CBR_RG_RX_OUTVCM_SZ 2
++#define CBR_RG_RX_TZI_MSK 0x00003000
++#define CBR_RG_RX_TZI_I_MSK 0xffffcfff
++#define CBR_RG_RX_TZI_SFT 12
++#define CBR_RG_RX_TZI_HI 13
++#define CBR_RG_RX_TZI_SZ 2
++#define CBR_RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
++#define CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
++#define CBR_RG_RX_TZ_OUT_TRISTATE_SFT 14
++#define CBR_RG_RX_TZ_OUT_TRISTATE_HI 14
++#define CBR_RG_RX_TZ_OUT_TRISTATE_SZ 1
++#define CBR_RG_RX_TZ_VCM_MSK 0x00018000
++#define CBR_RG_RX_TZ_VCM_I_MSK 0xfffe7fff
++#define CBR_RG_RX_TZ_VCM_SFT 15
++#define CBR_RG_RX_TZ_VCM_HI 16
++#define CBR_RG_RX_TZ_VCM_SZ 2
++#define CBR_RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
++#define CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
++#define CBR_RG_EN_RX_RSSI_TESTNODE_SFT 17
++#define CBR_RG_EN_RX_RSSI_TESTNODE_HI 19
++#define CBR_RG_EN_RX_RSSI_TESTNODE_SZ 3
++#define CBR_RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
++#define CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
++#define CBR_RG_RX_ADCRSSI_CLKSEL_SFT 20
++#define CBR_RG_RX_ADCRSSI_CLKSEL_HI 20
++#define CBR_RG_RX_ADCRSSI_CLKSEL_SZ 1
++#define CBR_RG_RX_ADCRSSI_VCM_MSK 0x00600000
++#define CBR_RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
++#define CBR_RG_RX_ADCRSSI_VCM_SFT 21
++#define CBR_RG_RX_ADCRSSI_VCM_HI 22
++#define CBR_RG_RX_ADCRSSI_VCM_SZ 2
++#define CBR_RG_RX_REC_LPFCORNER_MSK 0x01800000
++#define CBR_RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
++#define CBR_RG_RX_REC_LPFCORNER_SFT 23
++#define CBR_RG_RX_REC_LPFCORNER_HI 24
++#define CBR_RG_RX_REC_LPFCORNER_SZ 2
++#define CBR_RG_RSSI_CLOCK_GATING_MSK 0x02000000
++#define CBR_RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
++#define CBR_RG_RSSI_CLOCK_GATING_SFT 25
++#define CBR_RG_RSSI_CLOCK_GATING_HI 25
++#define CBR_RG_RSSI_CLOCK_GATING_SZ 1
++#define CBR_RG_TXPGA_CAPSW_MSK 0x00000003
++#define CBR_RG_TXPGA_CAPSW_I_MSK 0xfffffffc
++#define CBR_RG_TXPGA_CAPSW_SFT 0
++#define CBR_RG_TXPGA_CAPSW_HI 1
++#define CBR_RG_TXPGA_CAPSW_SZ 2
++#define CBR_RG_TXPGA_MAIN_MSK 0x000000fc
++#define CBR_RG_TXPGA_MAIN_I_MSK 0xffffff03
++#define CBR_RG_TXPGA_MAIN_SFT 2
++#define CBR_RG_TXPGA_MAIN_HI 7
++#define CBR_RG_TXPGA_MAIN_SZ 6
++#define CBR_RG_TXPGA_STEER_MSK 0x00003f00
++#define CBR_RG_TXPGA_STEER_I_MSK 0xffffc0ff
++#define CBR_RG_TXPGA_STEER_SFT 8
++#define CBR_RG_TXPGA_STEER_HI 13
++#define CBR_RG_TXPGA_STEER_SZ 6
++#define CBR_RG_TXMOD_GMCELL_MSK 0x0000c000
++#define CBR_RG_TXMOD_GMCELL_I_MSK 0xffff3fff
++#define CBR_RG_TXMOD_GMCELL_SFT 14
++#define CBR_RG_TXMOD_GMCELL_HI 15
++#define CBR_RG_TXMOD_GMCELL_SZ 2
++#define CBR_RG_TXLPF_GMCELL_MSK 0x00030000
++#define CBR_RG_TXLPF_GMCELL_I_MSK 0xfffcffff
++#define CBR_RG_TXLPF_GMCELL_SFT 16
++#define CBR_RG_TXLPF_GMCELL_HI 17
++#define CBR_RG_TXLPF_GMCELL_SZ 2
++#define CBR_RG_PACELL_EN_MSK 0x001c0000
++#define CBR_RG_PACELL_EN_I_MSK 0xffe3ffff
++#define CBR_RG_PACELL_EN_SFT 18
++#define CBR_RG_PACELL_EN_HI 20
++#define CBR_RG_PACELL_EN_SZ 3
++#define CBR_RG_PABIAS_CTRL_MSK 0x01e00000
++#define CBR_RG_PABIAS_CTRL_I_MSK 0xfe1fffff
++#define CBR_RG_PABIAS_CTRL_SFT 21
++#define CBR_RG_PABIAS_CTRL_HI 24
++#define CBR_RG_PABIAS_CTRL_SZ 4
++#define CBR_RG_PABIAS_AB_MSK 0x02000000
++#define CBR_RG_PABIAS_AB_I_MSK 0xfdffffff
++#define CBR_RG_PABIAS_AB_SFT 25
++#define CBR_RG_PABIAS_AB_HI 25
++#define CBR_RG_PABIAS_AB_SZ 1
++#define CBR_RG_TX_DIV_VSET_MSK 0x0c000000
++#define CBR_RG_TX_DIV_VSET_I_MSK 0xf3ffffff
++#define CBR_RG_TX_DIV_VSET_SFT 26
++#define CBR_RG_TX_DIV_VSET_HI 27
++#define CBR_RG_TX_DIV_VSET_SZ 2
++#define CBR_RG_TX_LOBUF_VSET_MSK 0x30000000
++#define CBR_RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
++#define CBR_RG_TX_LOBUF_VSET_SFT 28
++#define CBR_RG_TX_LOBUF_VSET_HI 29
++#define CBR_RG_TX_LOBUF_VSET_SZ 2
++#define CBR_RG_RX_SQDC_MSK 0x00000007
++#define CBR_RG_RX_SQDC_I_MSK 0xfffffff8
++#define CBR_RG_RX_SQDC_SFT 0
++#define CBR_RG_RX_SQDC_HI 2
++#define CBR_RG_RX_SQDC_SZ 3
++#define CBR_RG_RX_DIV2_CORE_MSK 0x00000018
++#define CBR_RG_RX_DIV2_CORE_I_MSK 0xffffffe7
++#define CBR_RG_RX_DIV2_CORE_SFT 3
++#define CBR_RG_RX_DIV2_CORE_HI 4
++#define CBR_RG_RX_DIV2_CORE_SZ 2
++#define CBR_RG_RX_LOBUF_MSK 0x00000060
++#define CBR_RG_RX_LOBUF_I_MSK 0xffffff9f
++#define CBR_RG_RX_LOBUF_SFT 5
++#define CBR_RG_RX_LOBUF_HI 6
++#define CBR_RG_RX_LOBUF_SZ 2
++#define CBR_RG_TX_DPDGM_BIAS_MSK 0x00000780
++#define CBR_RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
++#define CBR_RG_TX_DPDGM_BIAS_SFT 7
++#define CBR_RG_TX_DPDGM_BIAS_HI 10
++#define CBR_RG_TX_DPDGM_BIAS_SZ 4
++#define CBR_RG_TX_DPD_DIV_MSK 0x00007800
++#define CBR_RG_TX_DPD_DIV_I_MSK 0xffff87ff
++#define CBR_RG_TX_DPD_DIV_SFT 11
++#define CBR_RG_TX_DPD_DIV_HI 14
++#define CBR_RG_TX_DPD_DIV_SZ 4
++#define CBR_RG_TX_TSSI_BIAS_MSK 0x00038000
++#define CBR_RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
++#define CBR_RG_TX_TSSI_BIAS_SFT 15
++#define CBR_RG_TX_TSSI_BIAS_HI 17
++#define CBR_RG_TX_TSSI_BIAS_SZ 3
++#define CBR_RG_TX_TSSI_DIV_MSK 0x001c0000
++#define CBR_RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
++#define CBR_RG_TX_TSSI_DIV_SFT 18
++#define CBR_RG_TX_TSSI_DIV_HI 20
++#define CBR_RG_TX_TSSI_DIV_SZ 3
++#define CBR_RG_TX_TSSI_TESTMODE_MSK 0x00200000
++#define CBR_RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
++#define CBR_RG_TX_TSSI_TESTMODE_SFT 21
++#define CBR_RG_TX_TSSI_TESTMODE_HI 21
++#define CBR_RG_TX_TSSI_TESTMODE_SZ 1
++#define CBR_RG_TX_TSSI_TEST_MSK 0x00c00000
++#define CBR_RG_TX_TSSI_TEST_I_MSK 0xff3fffff
++#define CBR_RG_TX_TSSI_TEST_SFT 22
++#define CBR_RG_TX_TSSI_TEST_HI 23
++#define CBR_RG_TX_TSSI_TEST_SZ 2
++#define CBR_RG_RX_HG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_HG_LNA_GC_SFT 0
++#define CBR_RG_RX_HG_LNA_GC_HI 1
++#define CBR_RG_RX_HG_LNA_GC_SZ 2
++#define CBR_RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_HG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_HG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_HG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_HG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_HG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_HG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_HG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_HG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_HG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_HG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_HG_TZ_GC_SFT 14
++#define CBR_RG_RX_HG_TZ_GC_HI 15
++#define CBR_RG_RX_HG_TZ_GC_SZ 2
++#define CBR_RG_RX_HG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_HG_TZ_CAP_SFT 16
++#define CBR_RG_RX_HG_TZ_CAP_HI 18
++#define CBR_RG_RX_HG_TZ_CAP_SZ 3
++#define CBR_RG_RX_MG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_MG_LNA_GC_SFT 0
++#define CBR_RG_RX_MG_LNA_GC_HI 1
++#define CBR_RG_RX_MG_LNA_GC_SZ 2
++#define CBR_RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_MG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_MG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_MG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_MG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_MG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_MG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_MG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_MG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_MG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_MG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_MG_TZ_GC_SFT 14
++#define CBR_RG_RX_MG_TZ_GC_HI 15
++#define CBR_RG_RX_MG_TZ_GC_SZ 2
++#define CBR_RG_RX_MG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_MG_TZ_CAP_SFT 16
++#define CBR_RG_RX_MG_TZ_CAP_HI 18
++#define CBR_RG_RX_MG_TZ_CAP_SZ 3
++#define CBR_RG_RX_LG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_LG_LNA_GC_SFT 0
++#define CBR_RG_RX_LG_LNA_GC_HI 1
++#define CBR_RG_RX_LG_LNA_GC_SZ 2
++#define CBR_RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_LG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_LG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_LG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_LG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_LG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_LG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_LG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_LG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_LG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_LG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_LG_TZ_GC_SFT 14
++#define CBR_RG_RX_LG_TZ_GC_HI 15
++#define CBR_RG_RX_LG_TZ_GC_SZ 2
++#define CBR_RG_RX_LG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_LG_TZ_CAP_SFT 16
++#define CBR_RG_RX_LG_TZ_CAP_HI 18
++#define CBR_RG_RX_LG_TZ_CAP_SZ 3
++#define CBR_RG_RX_ULG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_ULG_LNA_GC_SFT 0
++#define CBR_RG_RX_ULG_LNA_GC_HI 1
++#define CBR_RG_RX_ULG_LNA_GC_SZ 2
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_ULG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_ULG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_ULG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_ULG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_ULG_TZ_GC_SFT 14
++#define CBR_RG_RX_ULG_TZ_GC_HI 15
++#define CBR_RG_RX_ULG_TZ_GC_SZ 2
++#define CBR_RG_RX_ULG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_ULG_TZ_CAP_SFT 16
++#define CBR_RG_RX_ULG_TZ_CAP_HI 18
++#define CBR_RG_RX_ULG_TZ_CAP_SZ 3
++#define CBR_RG_HPF1_FAST_SET_X_MSK 0x00000001
++#define CBR_RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
++#define CBR_RG_HPF1_FAST_SET_X_SFT 0
++#define CBR_RG_HPF1_FAST_SET_X_HI 0
++#define CBR_RG_HPF1_FAST_SET_X_SZ 1
++#define CBR_RG_HPF1_FAST_SET_Y_MSK 0x00000002
++#define CBR_RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
++#define CBR_RG_HPF1_FAST_SET_Y_SFT 1
++#define CBR_RG_HPF1_FAST_SET_Y_HI 1
++#define CBR_RG_HPF1_FAST_SET_Y_SZ 1
++#define CBR_RG_HPF1_FAST_SET_Z_MSK 0x00000004
++#define CBR_RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
++#define CBR_RG_HPF1_FAST_SET_Z_SFT 2
++#define CBR_RG_HPF1_FAST_SET_Z_HI 2
++#define CBR_RG_HPF1_FAST_SET_Z_SZ 1
++#define CBR_RG_HPF_T1A_MSK 0x00000018
++#define CBR_RG_HPF_T1A_I_MSK 0xffffffe7
++#define CBR_RG_HPF_T1A_SFT 3
++#define CBR_RG_HPF_T1A_HI 4
++#define CBR_RG_HPF_T1A_SZ 2
++#define CBR_RG_HPF_T1B_MSK 0x00000060
++#define CBR_RG_HPF_T1B_I_MSK 0xffffff9f
++#define CBR_RG_HPF_T1B_SFT 5
++#define CBR_RG_HPF_T1B_HI 6
++#define CBR_RG_HPF_T1B_SZ 2
++#define CBR_RG_HPF_T1C_MSK 0x00000180
++#define CBR_RG_HPF_T1C_I_MSK 0xfffffe7f
++#define CBR_RG_HPF_T1C_SFT 7
++#define CBR_RG_HPF_T1C_HI 8
++#define CBR_RG_HPF_T1C_SZ 2
++#define CBR_RG_RX_LNA_TRI_SEL_MSK 0x00000600
++#define CBR_RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
++#define CBR_RG_RX_LNA_TRI_SEL_SFT 9
++#define CBR_RG_RX_LNA_TRI_SEL_HI 10
++#define CBR_RG_RX_LNA_TRI_SEL_SZ 2
++#define CBR_RG_RX_LNA_SETTLE_MSK 0x00001800
++#define CBR_RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
++#define CBR_RG_RX_LNA_SETTLE_SFT 11
++#define CBR_RG_RX_LNA_SETTLE_HI 12
++#define CBR_RG_RX_LNA_SETTLE_SZ 2
++#define CBR_RG_ADC_CLKSEL_MSK 0x00000001
++#define CBR_RG_ADC_CLKSEL_I_MSK 0xfffffffe
++#define CBR_RG_ADC_CLKSEL_SFT 0
++#define CBR_RG_ADC_CLKSEL_HI 0
++#define CBR_RG_ADC_CLKSEL_SZ 1
++#define CBR_RG_ADC_DIBIAS_MSK 0x00000006
++#define CBR_RG_ADC_DIBIAS_I_MSK 0xfffffff9
++#define CBR_RG_ADC_DIBIAS_SFT 1
++#define CBR_RG_ADC_DIBIAS_HI 2
++#define CBR_RG_ADC_DIBIAS_SZ 2
++#define CBR_RG_ADC_DIVR_MSK 0x00000008
++#define CBR_RG_ADC_DIVR_I_MSK 0xfffffff7
++#define CBR_RG_ADC_DIVR_SFT 3
++#define CBR_RG_ADC_DIVR_HI 3
++#define CBR_RG_ADC_DIVR_SZ 1
++#define CBR_RG_ADC_DVCMI_MSK 0x00000030
++#define CBR_RG_ADC_DVCMI_I_MSK 0xffffffcf
++#define CBR_RG_ADC_DVCMI_SFT 4
++#define CBR_RG_ADC_DVCMI_HI 5
++#define CBR_RG_ADC_DVCMI_SZ 2
++#define CBR_RG_ADC_SAMSEL_MSK 0x000003c0
++#define CBR_RG_ADC_SAMSEL_I_MSK 0xfffffc3f
++#define CBR_RG_ADC_SAMSEL_SFT 6
++#define CBR_RG_ADC_SAMSEL_HI 9
++#define CBR_RG_ADC_SAMSEL_SZ 4
++#define CBR_RG_ADC_STNBY_MSK 0x00000400
++#define CBR_RG_ADC_STNBY_I_MSK 0xfffffbff
++#define CBR_RG_ADC_STNBY_SFT 10
++#define CBR_RG_ADC_STNBY_HI 10
++#define CBR_RG_ADC_STNBY_SZ 1
++#define CBR_RG_ADC_TESTMODE_MSK 0x00000800
++#define CBR_RG_ADC_TESTMODE_I_MSK 0xfffff7ff
++#define CBR_RG_ADC_TESTMODE_SFT 11
++#define CBR_RG_ADC_TESTMODE_HI 11
++#define CBR_RG_ADC_TESTMODE_SZ 1
++#define CBR_RG_ADC_TSEL_MSK 0x0000f000
++#define CBR_RG_ADC_TSEL_I_MSK 0xffff0fff
++#define CBR_RG_ADC_TSEL_SFT 12
++#define CBR_RG_ADC_TSEL_HI 15
++#define CBR_RG_ADC_TSEL_SZ 4
++#define CBR_RG_ADC_VRSEL_MSK 0x00030000
++#define CBR_RG_ADC_VRSEL_I_MSK 0xfffcffff
++#define CBR_RG_ADC_VRSEL_SFT 16
++#define CBR_RG_ADC_VRSEL_HI 17
++#define CBR_RG_ADC_VRSEL_SZ 2
++#define CBR_RG_DICMP_MSK 0x000c0000
++#define CBR_RG_DICMP_I_MSK 0xfff3ffff
++#define CBR_RG_DICMP_SFT 18
++#define CBR_RG_DICMP_HI 19
++#define CBR_RG_DICMP_SZ 2
++#define CBR_RG_DIOP_MSK 0x00300000
++#define CBR_RG_DIOP_I_MSK 0xffcfffff
++#define CBR_RG_DIOP_SFT 20
++#define CBR_RG_DIOP_HI 21
++#define CBR_RG_DIOP_SZ 2
++#define CBR_RG_DACI1ST_MSK 0x00000003
++#define CBR_RG_DACI1ST_I_MSK 0xfffffffc
++#define CBR_RG_DACI1ST_SFT 0
++#define CBR_RG_DACI1ST_HI 1
++#define CBR_RG_DACI1ST_SZ 2
++#define CBR_RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
++#define CBR_RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
++#define CBR_RG_TX_DACLPF_ICOURSE_SFT 2
++#define CBR_RG_TX_DACLPF_ICOURSE_HI 3
++#define CBR_RG_TX_DACLPF_ICOURSE_SZ 2
++#define CBR_RG_TX_DACLPF_IFINE_MSK 0x00000030
++#define CBR_RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
++#define CBR_RG_TX_DACLPF_IFINE_SFT 4
++#define CBR_RG_TX_DACLPF_IFINE_HI 5
++#define CBR_RG_TX_DACLPF_IFINE_SZ 2
++#define CBR_RG_TX_DACLPF_VCM_MSK 0x000000c0
++#define CBR_RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
++#define CBR_RG_TX_DACLPF_VCM_SFT 6
++#define CBR_RG_TX_DACLPF_VCM_HI 7
++#define CBR_RG_TX_DACLPF_VCM_SZ 2
++#define CBR_RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
++#define CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
++#define CBR_RG_TX_DAC_CKEDGE_SEL_SFT 8
++#define CBR_RG_TX_DAC_CKEDGE_SEL_HI 8
++#define CBR_RG_TX_DAC_CKEDGE_SEL_SZ 1
++#define CBR_RG_TX_DAC_IBIAS_MSK 0x00000600
++#define CBR_RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
++#define CBR_RG_TX_DAC_IBIAS_SFT 9
++#define CBR_RG_TX_DAC_IBIAS_HI 10
++#define CBR_RG_TX_DAC_IBIAS_SZ 2
++#define CBR_RG_TX_DAC_OS_MSK 0x00003800
++#define CBR_RG_TX_DAC_OS_I_MSK 0xffffc7ff
++#define CBR_RG_TX_DAC_OS_SFT 11
++#define CBR_RG_TX_DAC_OS_HI 13
++#define CBR_RG_TX_DAC_OS_SZ 3
++#define CBR_RG_TX_DAC_RCAL_MSK 0x0000c000
++#define CBR_RG_TX_DAC_RCAL_I_MSK 0xffff3fff
++#define CBR_RG_TX_DAC_RCAL_SFT 14
++#define CBR_RG_TX_DAC_RCAL_HI 15
++#define CBR_RG_TX_DAC_RCAL_SZ 2
++#define CBR_RG_TX_DAC_TSEL_MSK 0x000f0000
++#define CBR_RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
++#define CBR_RG_TX_DAC_TSEL_SFT 16
++#define CBR_RG_TX_DAC_TSEL_HI 19
++#define CBR_RG_TX_DAC_TSEL_SZ 4
++#define CBR_RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
++#define CBR_RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
++#define CBR_RG_TX_EN_VOLTAGE_IN_SFT 20
++#define CBR_RG_TX_EN_VOLTAGE_IN_HI 20
++#define CBR_RG_TX_EN_VOLTAGE_IN_SZ 1
++#define CBR_RG_TXLPF_BYPASS_MSK 0x00200000
++#define CBR_RG_TXLPF_BYPASS_I_MSK 0xffdfffff
++#define CBR_RG_TXLPF_BYPASS_SFT 21
++#define CBR_RG_TXLPF_BYPASS_HI 21
++#define CBR_RG_TXLPF_BYPASS_SZ 1
++#define CBR_RG_TXLPF_BOOSTI_MSK 0x00400000
++#define CBR_RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
++#define CBR_RG_TXLPF_BOOSTI_SFT 22
++#define CBR_RG_TXLPF_BOOSTI_HI 22
++#define CBR_RG_TXLPF_BOOSTI_SZ 1
++#define CBR_RG_EN_SX_R3_MSK 0x00000001
++#define CBR_RG_EN_SX_R3_I_MSK 0xfffffffe
++#define CBR_RG_EN_SX_R3_SFT 0
++#define CBR_RG_EN_SX_R3_HI 0
++#define CBR_RG_EN_SX_R3_SZ 1
++#define CBR_RG_EN_SX_CH_MSK 0x00000002
++#define CBR_RG_EN_SX_CH_I_MSK 0xfffffffd
++#define CBR_RG_EN_SX_CH_SFT 1
++#define CBR_RG_EN_SX_CH_HI 1
++#define CBR_RG_EN_SX_CH_SZ 1
++#define CBR_RG_EN_SX_CHP_MSK 0x00000004
++#define CBR_RG_EN_SX_CHP_I_MSK 0xfffffffb
++#define CBR_RG_EN_SX_CHP_SFT 2
++#define CBR_RG_EN_SX_CHP_HI 2
++#define CBR_RG_EN_SX_CHP_SZ 1
++#define CBR_RG_EN_SX_DIVCK_MSK 0x00000008
++#define CBR_RG_EN_SX_DIVCK_I_MSK 0xfffffff7
++#define CBR_RG_EN_SX_DIVCK_SFT 3
++#define CBR_RG_EN_SX_DIVCK_HI 3
++#define CBR_RG_EN_SX_DIVCK_SZ 1
++#define CBR_RG_EN_SX_VCOBF_MSK 0x00000010
++#define CBR_RG_EN_SX_VCOBF_I_MSK 0xffffffef
++#define CBR_RG_EN_SX_VCOBF_SFT 4
++#define CBR_RG_EN_SX_VCOBF_HI 4
++#define CBR_RG_EN_SX_VCOBF_SZ 1
++#define CBR_RG_EN_SX_VCO_MSK 0x00000020
++#define CBR_RG_EN_SX_VCO_I_MSK 0xffffffdf
++#define CBR_RG_EN_SX_VCO_SFT 5
++#define CBR_RG_EN_SX_VCO_HI 5
++#define CBR_RG_EN_SX_VCO_SZ 1
++#define CBR_RG_EN_SX_MOD_MSK 0x00000040
++#define CBR_RG_EN_SX_MOD_I_MSK 0xffffffbf
++#define CBR_RG_EN_SX_MOD_SFT 6
++#define CBR_RG_EN_SX_MOD_HI 6
++#define CBR_RG_EN_SX_MOD_SZ 1
++#define CBR_RG_EN_SX_LCK_MSK 0x00000080
++#define CBR_RG_EN_SX_LCK_I_MSK 0xffffff7f
++#define CBR_RG_EN_SX_LCK_SFT 7
++#define CBR_RG_EN_SX_LCK_HI 7
++#define CBR_RG_EN_SX_LCK_SZ 1
++#define CBR_RG_EN_SX_DITHER_MSK 0x00000100
++#define CBR_RG_EN_SX_DITHER_I_MSK 0xfffffeff
++#define CBR_RG_EN_SX_DITHER_SFT 8
++#define CBR_RG_EN_SX_DITHER_HI 8
++#define CBR_RG_EN_SX_DITHER_SZ 1
++#define CBR_RG_EN_SX_DELCAL_MSK 0x00000200
++#define CBR_RG_EN_SX_DELCAL_I_MSK 0xfffffdff
++#define CBR_RG_EN_SX_DELCAL_SFT 9
++#define CBR_RG_EN_SX_DELCAL_HI 9
++#define CBR_RG_EN_SX_DELCAL_SZ 1
++#define CBR_RG_EN_SX_PC_BYPASS_MSK 0x00000400
++#define CBR_RG_EN_SX_PC_BYPASS_I_MSK 0xfffffbff
++#define CBR_RG_EN_SX_PC_BYPASS_SFT 10
++#define CBR_RG_EN_SX_PC_BYPASS_HI 10
++#define CBR_RG_EN_SX_PC_BYPASS_SZ 1
++#define CBR_RG_EN_SX_VT_MON_MSK 0x00000800
++#define CBR_RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
++#define CBR_RG_EN_SX_VT_MON_SFT 11
++#define CBR_RG_EN_SX_VT_MON_HI 11
++#define CBR_RG_EN_SX_VT_MON_SZ 1
++#define CBR_RG_EN_SX_VT_MON_DG_MSK 0x00001000
++#define CBR_RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
++#define CBR_RG_EN_SX_VT_MON_DG_SFT 12
++#define CBR_RG_EN_SX_VT_MON_DG_HI 12
++#define CBR_RG_EN_SX_VT_MON_DG_SZ 1
++#define CBR_RG_EN_SX_DIV_MSK 0x00002000
++#define CBR_RG_EN_SX_DIV_I_MSK 0xffffdfff
++#define CBR_RG_EN_SX_DIV_SFT 13
++#define CBR_RG_EN_SX_DIV_HI 13
++#define CBR_RG_EN_SX_DIV_SZ 1
++#define CBR_RG_EN_SX_LPF_MSK 0x00004000
++#define CBR_RG_EN_SX_LPF_I_MSK 0xffffbfff
++#define CBR_RG_EN_SX_LPF_SFT 14
++#define CBR_RG_EN_SX_LPF_HI 14
++#define CBR_RG_EN_SX_LPF_SZ 1
++#define CBR_RG_SX_RFCTRL_F_MSK 0x00ffffff
++#define CBR_RG_SX_RFCTRL_F_I_MSK 0xff000000
++#define CBR_RG_SX_RFCTRL_F_SFT 0
++#define CBR_RG_SX_RFCTRL_F_HI 23
++#define CBR_RG_SX_RFCTRL_F_SZ 24
++#define CBR_RG_SX_SEL_CP_MSK 0x0f000000
++#define CBR_RG_SX_SEL_CP_I_MSK 0xf0ffffff
++#define CBR_RG_SX_SEL_CP_SFT 24
++#define CBR_RG_SX_SEL_CP_HI 27
++#define CBR_RG_SX_SEL_CP_SZ 4
++#define CBR_RG_SX_SEL_CS_MSK 0xf0000000
++#define CBR_RG_SX_SEL_CS_I_MSK 0x0fffffff
++#define CBR_RG_SX_SEL_CS_SFT 28
++#define CBR_RG_SX_SEL_CS_HI 31
++#define CBR_RG_SX_SEL_CS_SZ 4
++#define CBR_RG_SX_RFCTRL_CH_MSK 0x000007ff
++#define CBR_RG_SX_RFCTRL_CH_I_MSK 0xfffff800
++#define CBR_RG_SX_RFCTRL_CH_SFT 0
++#define CBR_RG_SX_RFCTRL_CH_HI 10
++#define CBR_RG_SX_RFCTRL_CH_SZ 11
++#define CBR_RG_SX_SEL_C3_MSK 0x00007800
++#define CBR_RG_SX_SEL_C3_I_MSK 0xffff87ff
++#define CBR_RG_SX_SEL_C3_SFT 11
++#define CBR_RG_SX_SEL_C3_HI 14
++#define CBR_RG_SX_SEL_C3_SZ 4
++#define CBR_RG_SX_SEL_RS_MSK 0x000f8000
++#define CBR_RG_SX_SEL_RS_I_MSK 0xfff07fff
++#define CBR_RG_SX_SEL_RS_SFT 15
++#define CBR_RG_SX_SEL_RS_HI 19
++#define CBR_RG_SX_SEL_RS_SZ 5
++#define CBR_RG_SX_SEL_R3_MSK 0x01f00000
++#define CBR_RG_SX_SEL_R3_I_MSK 0xfe0fffff
++#define CBR_RG_SX_SEL_R3_SFT 20
++#define CBR_RG_SX_SEL_R3_HI 24
++#define CBR_RG_SX_SEL_R3_SZ 5
++#define CBR_RG_SX_SEL_ICHP_MSK 0x0000001f
++#define CBR_RG_SX_SEL_ICHP_I_MSK 0xffffffe0
++#define CBR_RG_SX_SEL_ICHP_SFT 0
++#define CBR_RG_SX_SEL_ICHP_HI 4
++#define CBR_RG_SX_SEL_ICHP_SZ 5
++#define CBR_RG_SX_SEL_PCHP_MSK 0x000003e0
++#define CBR_RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
++#define CBR_RG_SX_SEL_PCHP_SFT 5
++#define CBR_RG_SX_SEL_PCHP_HI 9
++#define CBR_RG_SX_SEL_PCHP_SZ 5
++#define CBR_RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
++#define CBR_RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
++#define CBR_RG_SX_SEL_CHP_REGOP_SFT 10
++#define CBR_RG_SX_SEL_CHP_REGOP_HI 13
++#define CBR_RG_SX_SEL_CHP_REGOP_SZ 4
++#define CBR_RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
++#define CBR_RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
++#define CBR_RG_SX_SEL_CHP_UNIOP_SFT 14
++#define CBR_RG_SX_SEL_CHP_UNIOP_HI 17
++#define CBR_RG_SX_SEL_CHP_UNIOP_SZ 4
++#define CBR_RG_SX_CHP_IOST_POL_MSK 0x00040000
++#define CBR_RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
++#define CBR_RG_SX_CHP_IOST_POL_SFT 18
++#define CBR_RG_SX_CHP_IOST_POL_HI 18
++#define CBR_RG_SX_CHP_IOST_POL_SZ 1
++#define CBR_RG_SX_CHP_IOST_MSK 0x00380000
++#define CBR_RG_SX_CHP_IOST_I_MSK 0xffc7ffff
++#define CBR_RG_SX_CHP_IOST_SFT 19
++#define CBR_RG_SX_CHP_IOST_HI 21
++#define CBR_RG_SX_CHP_IOST_SZ 3
++#define CBR_RG_SX_PFDSEL_MSK 0x00400000
++#define CBR_RG_SX_PFDSEL_I_MSK 0xffbfffff
++#define CBR_RG_SX_PFDSEL_SFT 22
++#define CBR_RG_SX_PFDSEL_HI 22
++#define CBR_RG_SX_PFDSEL_SZ 1
++#define CBR_RG_SX_PFD_SET_MSK 0x00800000
++#define CBR_RG_SX_PFD_SET_I_MSK 0xff7fffff
++#define CBR_RG_SX_PFD_SET_SFT 23
++#define CBR_RG_SX_PFD_SET_HI 23
++#define CBR_RG_SX_PFD_SET_SZ 1
++#define CBR_RG_SX_PFD_SET1_MSK 0x01000000
++#define CBR_RG_SX_PFD_SET1_I_MSK 0xfeffffff
++#define CBR_RG_SX_PFD_SET1_SFT 24
++#define CBR_RG_SX_PFD_SET1_HI 24
++#define CBR_RG_SX_PFD_SET1_SZ 1
++#define CBR_RG_SX_PFD_SET2_MSK 0x02000000
++#define CBR_RG_SX_PFD_SET2_I_MSK 0xfdffffff
++#define CBR_RG_SX_PFD_SET2_SFT 25
++#define CBR_RG_SX_PFD_SET2_HI 25
++#define CBR_RG_SX_PFD_SET2_SZ 1
++#define CBR_RG_SX_VBNCAS_SEL_MSK 0x04000000
++#define CBR_RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
++#define CBR_RG_SX_VBNCAS_SEL_SFT 26
++#define CBR_RG_SX_VBNCAS_SEL_HI 26
++#define CBR_RG_SX_VBNCAS_SEL_SZ 1
++#define CBR_RG_SX_PFD_RST_H_MSK 0x08000000
++#define CBR_RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
++#define CBR_RG_SX_PFD_RST_H_SFT 27
++#define CBR_RG_SX_PFD_RST_H_HI 27
++#define CBR_RG_SX_PFD_RST_H_SZ 1
++#define CBR_RG_SX_PFD_TRUP_MSK 0x10000000
++#define CBR_RG_SX_PFD_TRUP_I_MSK 0xefffffff
++#define CBR_RG_SX_PFD_TRUP_SFT 28
++#define CBR_RG_SX_PFD_TRUP_HI 28
++#define CBR_RG_SX_PFD_TRUP_SZ 1
++#define CBR_RG_SX_PFD_TRDN_MSK 0x20000000
++#define CBR_RG_SX_PFD_TRDN_I_MSK 0xdfffffff
++#define CBR_RG_SX_PFD_TRDN_SFT 29
++#define CBR_RG_SX_PFD_TRDN_HI 29
++#define CBR_RG_SX_PFD_TRDN_SZ 1
++#define CBR_RG_SX_PFD_TRSEL_MSK 0x40000000
++#define CBR_RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
++#define CBR_RG_SX_PFD_TRSEL_SFT 30
++#define CBR_RG_SX_PFD_TRSEL_HI 30
++#define CBR_RG_SX_PFD_TRSEL_SZ 1
++#define CBR_RG_SX_VCOBA_R_MSK 0x00000007
++#define CBR_RG_SX_VCOBA_R_I_MSK 0xfffffff8
++#define CBR_RG_SX_VCOBA_R_SFT 0
++#define CBR_RG_SX_VCOBA_R_HI 2
++#define CBR_RG_SX_VCOBA_R_SZ 3
++#define CBR_RG_SX_VCORSEL_MSK 0x000000f8
++#define CBR_RG_SX_VCORSEL_I_MSK 0xffffff07
++#define CBR_RG_SX_VCORSEL_SFT 3
++#define CBR_RG_SX_VCORSEL_HI 7
++#define CBR_RG_SX_VCORSEL_SZ 5
++#define CBR_RG_SX_VCOCUSEL_MSK 0x00000f00
++#define CBR_RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
++#define CBR_RG_SX_VCOCUSEL_SFT 8
++#define CBR_RG_SX_VCOCUSEL_HI 11
++#define CBR_RG_SX_VCOCUSEL_SZ 4
++#define CBR_RG_SX_RXBFSEL_MSK 0x0000f000
++#define CBR_RG_SX_RXBFSEL_I_MSK 0xffff0fff
++#define CBR_RG_SX_RXBFSEL_SFT 12
++#define CBR_RG_SX_RXBFSEL_HI 15
++#define CBR_RG_SX_RXBFSEL_SZ 4
++#define CBR_RG_SX_TXBFSEL_MSK 0x000f0000
++#define CBR_RG_SX_TXBFSEL_I_MSK 0xfff0ffff
++#define CBR_RG_SX_TXBFSEL_SFT 16
++#define CBR_RG_SX_TXBFSEL_HI 19
++#define CBR_RG_SX_TXBFSEL_SZ 4
++#define CBR_RG_SX_VCOBFSEL_MSK 0x00f00000
++#define CBR_RG_SX_VCOBFSEL_I_MSK 0xff0fffff
++#define CBR_RG_SX_VCOBFSEL_SFT 20
++#define CBR_RG_SX_VCOBFSEL_HI 23
++#define CBR_RG_SX_VCOBFSEL_SZ 4
++#define CBR_RG_SX_DIVBFSEL_MSK 0x0f000000
++#define CBR_RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
++#define CBR_RG_SX_DIVBFSEL_SFT 24
++#define CBR_RG_SX_DIVBFSEL_HI 27
++#define CBR_RG_SX_DIVBFSEL_SZ 4
++#define CBR_RG_SX_GNDR_SEL_MSK 0xf0000000
++#define CBR_RG_SX_GNDR_SEL_I_MSK 0x0fffffff
++#define CBR_RG_SX_GNDR_SEL_SFT 28
++#define CBR_RG_SX_GNDR_SEL_HI 31
++#define CBR_RG_SX_GNDR_SEL_SZ 4
++#define CBR_RG_SX_DITHER_WEIGHT_MSK 0x00000003
++#define CBR_RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
++#define CBR_RG_SX_DITHER_WEIGHT_SFT 0
++#define CBR_RG_SX_DITHER_WEIGHT_HI 1
++#define CBR_RG_SX_DITHER_WEIGHT_SZ 2
++#define CBR_RG_SX_MOD_ERRCMP_MSK 0x0000000c
++#define CBR_RG_SX_MOD_ERRCMP_I_MSK 0xfffffff3
++#define CBR_RG_SX_MOD_ERRCMP_SFT 2
++#define CBR_RG_SX_MOD_ERRCMP_HI 3
++#define CBR_RG_SX_MOD_ERRCMP_SZ 2
++#define CBR_RG_SX_MOD_ORDER_MSK 0x00000030
++#define CBR_RG_SX_MOD_ORDER_I_MSK 0xffffffcf
++#define CBR_RG_SX_MOD_ORDER_SFT 4
++#define CBR_RG_SX_MOD_ORDER_HI 5
++#define CBR_RG_SX_MOD_ORDER_SZ 2
++#define CBR_RG_SX_SDM_D1_MSK 0x00000040
++#define CBR_RG_SX_SDM_D1_I_MSK 0xffffffbf
++#define CBR_RG_SX_SDM_D1_SFT 6
++#define CBR_RG_SX_SDM_D1_HI 6
++#define CBR_RG_SX_SDM_D1_SZ 1
++#define CBR_RG_SX_SDM_D2_MSK 0x00000080
++#define CBR_RG_SX_SDM_D2_I_MSK 0xffffff7f
++#define CBR_RG_SX_SDM_D2_SFT 7
++#define CBR_RG_SX_SDM_D2_HI 7
++#define CBR_RG_SX_SDM_D2_SZ 1
++#define CBR_RG_SDM_PASS_MSK 0x00000100
++#define CBR_RG_SDM_PASS_I_MSK 0xfffffeff
++#define CBR_RG_SDM_PASS_SFT 8
++#define CBR_RG_SDM_PASS_HI 8
++#define CBR_RG_SDM_PASS_SZ 1
++#define CBR_RG_SX_RST_H_DIV_MSK 0x00000200
++#define CBR_RG_SX_RST_H_DIV_I_MSK 0xfffffdff
++#define CBR_RG_SX_RST_H_DIV_SFT 9
++#define CBR_RG_SX_RST_H_DIV_HI 9
++#define CBR_RG_SX_RST_H_DIV_SZ 1
++#define CBR_RG_SX_SDM_EDGE_MSK 0x00000400
++#define CBR_RG_SX_SDM_EDGE_I_MSK 0xfffffbff
++#define CBR_RG_SX_SDM_EDGE_SFT 10
++#define CBR_RG_SX_SDM_EDGE_HI 10
++#define CBR_RG_SX_SDM_EDGE_SZ 1
++#define CBR_RG_SX_XO_GM_MSK 0x00001800
++#define CBR_RG_SX_XO_GM_I_MSK 0xffffe7ff
++#define CBR_RG_SX_XO_GM_SFT 11
++#define CBR_RG_SX_XO_GM_HI 12
++#define CBR_RG_SX_XO_GM_SZ 2
++#define CBR_RG_SX_REFBYTWO_MSK 0x00002000
++#define CBR_RG_SX_REFBYTWO_I_MSK 0xffffdfff
++#define CBR_RG_SX_REFBYTWO_SFT 13
++#define CBR_RG_SX_REFBYTWO_HI 13
++#define CBR_RG_SX_REFBYTWO_SZ 1
++#define CBR_RG_SX_XO_SWCAP_MSK 0x0003c000
++#define CBR_RG_SX_XO_SWCAP_I_MSK 0xfffc3fff
++#define CBR_RG_SX_XO_SWCAP_SFT 14
++#define CBR_RG_SX_XO_SWCAP_HI 17
++#define CBR_RG_SX_XO_SWCAP_SZ 4
++#define CBR_RG_SX_SDMLUT_INV_MSK 0x00040000
++#define CBR_RG_SX_SDMLUT_INV_I_MSK 0xfffbffff
++#define CBR_RG_SX_SDMLUT_INV_SFT 18
++#define CBR_RG_SX_SDMLUT_INV_HI 18
++#define CBR_RG_SX_SDMLUT_INV_SZ 1
++#define CBR_RG_SX_LCKEN_MSK 0x00080000
++#define CBR_RG_SX_LCKEN_I_MSK 0xfff7ffff
++#define CBR_RG_SX_LCKEN_SFT 19
++#define CBR_RG_SX_LCKEN_HI 19
++#define CBR_RG_SX_LCKEN_SZ 1
++#define CBR_RG_SX_PREVDD_MSK 0x00f00000
++#define CBR_RG_SX_PREVDD_I_MSK 0xff0fffff
++#define CBR_RG_SX_PREVDD_SFT 20
++#define CBR_RG_SX_PREVDD_HI 23
++#define CBR_RG_SX_PREVDD_SZ 4
++#define CBR_RG_SX_PSCONTERVDD_MSK 0x0f000000
++#define CBR_RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
++#define CBR_RG_SX_PSCONTERVDD_SFT 24
++#define CBR_RG_SX_PSCONTERVDD_HI 27
++#define CBR_RG_SX_PSCONTERVDD_SZ 4
++#define CBR_RG_SX_MOD_ERR_DELAY_MSK 0x30000000
++#define CBR_RG_SX_MOD_ERR_DELAY_I_MSK 0xcfffffff
++#define CBR_RG_SX_MOD_ERR_DELAY_SFT 28
++#define CBR_RG_SX_MOD_ERR_DELAY_HI 29
++#define CBR_RG_SX_MOD_ERR_DELAY_SZ 2
++#define CBR_RG_SX_MODDB_MSK 0x40000000
++#define CBR_RG_SX_MODDB_I_MSK 0xbfffffff
++#define CBR_RG_SX_MODDB_SFT 30
++#define CBR_RG_SX_MODDB_HI 30
++#define CBR_RG_SX_MODDB_SZ 1
++#define CBR_RG_SX_CV_CURVE_SEL_MSK 0x00000003
++#define CBR_RG_SX_CV_CURVE_SEL_I_MSK 0xfffffffc
++#define CBR_RG_SX_CV_CURVE_SEL_SFT 0
++#define CBR_RG_SX_CV_CURVE_SEL_HI 1
++#define CBR_RG_SX_CV_CURVE_SEL_SZ 2
++#define CBR_RG_SX_SEL_DELAY_MSK 0x0000007c
++#define CBR_RG_SX_SEL_DELAY_I_MSK 0xffffff83
++#define CBR_RG_SX_SEL_DELAY_SFT 2
++#define CBR_RG_SX_SEL_DELAY_HI 6
++#define CBR_RG_SX_SEL_DELAY_SZ 5
++#define CBR_RG_SX_REF_CYCLE_MSK 0x00000780
++#define CBR_RG_SX_REF_CYCLE_I_MSK 0xfffff87f
++#define CBR_RG_SX_REF_CYCLE_SFT 7
++#define CBR_RG_SX_REF_CYCLE_HI 10
++#define CBR_RG_SX_REF_CYCLE_SZ 4
++#define CBR_RG_SX_VCOBY16_MSK 0x00000800
++#define CBR_RG_SX_VCOBY16_I_MSK 0xfffff7ff
++#define CBR_RG_SX_VCOBY16_SFT 11
++#define CBR_RG_SX_VCOBY16_HI 11
++#define CBR_RG_SX_VCOBY16_SZ 1
++#define CBR_RG_SX_VCOBY32_MSK 0x00001000
++#define CBR_RG_SX_VCOBY32_I_MSK 0xffffefff
++#define CBR_RG_SX_VCOBY32_SFT 12
++#define CBR_RG_SX_VCOBY32_HI 12
++#define CBR_RG_SX_VCOBY32_SZ 1
++#define CBR_RG_SX_PH_MSK 0x00002000
++#define CBR_RG_SX_PH_I_MSK 0xffffdfff
++#define CBR_RG_SX_PH_SFT 13
++#define CBR_RG_SX_PH_HI 13
++#define CBR_RG_SX_PH_SZ 1
++#define CBR_RG_SX_PL_MSK 0x00004000
++#define CBR_RG_SX_PL_I_MSK 0xffffbfff
++#define CBR_RG_SX_PL_SFT 14
++#define CBR_RG_SX_PL_HI 14
++#define CBR_RG_SX_PL_SZ 1
++#define CBR_RG_SX_VT_MON_MODE_MSK 0x00000001
++#define CBR_RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
++#define CBR_RG_SX_VT_MON_MODE_SFT 0
++#define CBR_RG_SX_VT_MON_MODE_HI 0
++#define CBR_RG_SX_VT_MON_MODE_SZ 1
++#define CBR_RG_SX_VT_TH_HI_MSK 0x00000006
++#define CBR_RG_SX_VT_TH_HI_I_MSK 0xfffffff9
++#define CBR_RG_SX_VT_TH_HI_SFT 1
++#define CBR_RG_SX_VT_TH_HI_HI 2
++#define CBR_RG_SX_VT_TH_HI_SZ 2
++#define CBR_RG_SX_VT_TH_LO_MSK 0x00000018
++#define CBR_RG_SX_VT_TH_LO_I_MSK 0xffffffe7
++#define CBR_RG_SX_VT_TH_LO_SFT 3
++#define CBR_RG_SX_VT_TH_LO_HI 4
++#define CBR_RG_SX_VT_TH_LO_SZ 2
++#define CBR_RG_SX_VT_SET_MSK 0x00000020
++#define CBR_RG_SX_VT_SET_I_MSK 0xffffffdf
++#define CBR_RG_SX_VT_SET_SFT 5
++#define CBR_RG_SX_VT_SET_HI 5
++#define CBR_RG_SX_VT_SET_SZ 1
++#define CBR_RG_SX_VT_MON_TMR_MSK 0x00007fc0
++#define CBR_RG_SX_VT_MON_TMR_I_MSK 0xffff803f
++#define CBR_RG_SX_VT_MON_TMR_SFT 6
++#define CBR_RG_SX_VT_MON_TMR_HI 14
++#define CBR_RG_SX_VT_MON_TMR_SZ 9
++#define CBR_RG_IDEAL_CYCLE_MSK 0x0fff8000
++#define CBR_RG_IDEAL_CYCLE_I_MSK 0xf0007fff
++#define CBR_RG_IDEAL_CYCLE_SFT 15
++#define CBR_RG_IDEAL_CYCLE_HI 27
++#define CBR_RG_IDEAL_CYCLE_SZ 13
++#define CBR_RG_EN_DP_VT_MON_MSK 0x00000001
++#define CBR_RG_EN_DP_VT_MON_I_MSK 0xfffffffe
++#define CBR_RG_EN_DP_VT_MON_SFT 0
++#define CBR_RG_EN_DP_VT_MON_HI 0
++#define CBR_RG_EN_DP_VT_MON_SZ 1
++#define CBR_RG_DP_VT_TH_HI_MSK 0x00000006
++#define CBR_RG_DP_VT_TH_HI_I_MSK 0xfffffff9
++#define CBR_RG_DP_VT_TH_HI_SFT 1
++#define CBR_RG_DP_VT_TH_HI_HI 2
++#define CBR_RG_DP_VT_TH_HI_SZ 2
++#define CBR_RG_DP_VT_TH_LO_MSK 0x00000018
++#define CBR_RG_DP_VT_TH_LO_I_MSK 0xffffffe7
++#define CBR_RG_DP_VT_TH_LO_SFT 3
++#define CBR_RG_DP_VT_TH_LO_HI 4
++#define CBR_RG_DP_VT_TH_LO_SZ 2
++#define CBR_RG_DP_VT_MON_TMR_MSK 0x00003fe0
++#define CBR_RG_DP_VT_MON_TMR_I_MSK 0xffffc01f
++#define CBR_RG_DP_VT_MON_TMR_SFT 5
++#define CBR_RG_DP_VT_MON_TMR_HI 13
++#define CBR_RG_DP_VT_MON_TMR_SZ 9
++#define CBR_RG_DP_CK320BY2_MSK 0x00004000
++#define CBR_RG_DP_CK320BY2_I_MSK 0xffffbfff
++#define CBR_RG_DP_CK320BY2_SFT 14
++#define CBR_RG_DP_CK320BY2_HI 14
++#define CBR_RG_DP_CK320BY2_SZ 1
++#define CBR_RG_SX_DELCTRL_MSK 0x001f8000
++#define CBR_RG_SX_DELCTRL_I_MSK 0xffe07fff
++#define CBR_RG_SX_DELCTRL_SFT 15
++#define CBR_RG_SX_DELCTRL_HI 20
++#define CBR_RG_SX_DELCTRL_SZ 6
++#define CBR_RG_DP_OD_TEST_MSK 0x00200000
++#define CBR_RG_DP_OD_TEST_I_MSK 0xffdfffff
++#define CBR_RG_DP_OD_TEST_SFT 21
++#define CBR_RG_DP_OD_TEST_HI 21
++#define CBR_RG_DP_OD_TEST_SZ 1
++#define CBR_RG_DP_BBPLL_BP_MSK 0x00000001
++#define CBR_RG_DP_BBPLL_BP_I_MSK 0xfffffffe
++#define CBR_RG_DP_BBPLL_BP_SFT 0
++#define CBR_RG_DP_BBPLL_BP_HI 0
++#define CBR_RG_DP_BBPLL_BP_SZ 1
++#define CBR_RG_DP_BBPLL_ICP_MSK 0x00000006
++#define CBR_RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
++#define CBR_RG_DP_BBPLL_ICP_SFT 1
++#define CBR_RG_DP_BBPLL_ICP_HI 2
++#define CBR_RG_DP_BBPLL_ICP_SZ 2
++#define CBR_RG_DP_BBPLL_IDUAL_MSK 0x00000018
++#define CBR_RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
++#define CBR_RG_DP_BBPLL_IDUAL_SFT 3
++#define CBR_RG_DP_BBPLL_IDUAL_HI 4
++#define CBR_RG_DP_BBPLL_IDUAL_SZ 2
++#define CBR_RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
++#define CBR_RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
++#define CBR_RG_DP_BBPLL_OD_TEST_SFT 5
++#define CBR_RG_DP_BBPLL_OD_TEST_HI 8
++#define CBR_RG_DP_BBPLL_OD_TEST_SZ 4
++#define CBR_RG_DP_BBPLL_PD_MSK 0x00000200
++#define CBR_RG_DP_BBPLL_PD_I_MSK 0xfffffdff
++#define CBR_RG_DP_BBPLL_PD_SFT 9
++#define CBR_RG_DP_BBPLL_PD_HI 9
++#define CBR_RG_DP_BBPLL_PD_SZ 1
++#define CBR_RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
++#define CBR_RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
++#define CBR_RG_DP_BBPLL_TESTSEL_SFT 10
++#define CBR_RG_DP_BBPLL_TESTSEL_HI 12
++#define CBR_RG_DP_BBPLL_TESTSEL_SZ 3
++#define CBR_RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
++#define CBR_RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
++#define CBR_RG_DP_BBPLL_PFD_DLY_SFT 13
++#define CBR_RG_DP_BBPLL_PFD_DLY_HI 14
++#define CBR_RG_DP_BBPLL_PFD_DLY_SZ 2
++#define CBR_RG_DP_RP_MSK 0x00038000
++#define CBR_RG_DP_RP_I_MSK 0xfffc7fff
++#define CBR_RG_DP_RP_SFT 15
++#define CBR_RG_DP_RP_HI 17
++#define CBR_RG_DP_RP_SZ 3
++#define CBR_RG_DP_RHP_MSK 0x000c0000
++#define CBR_RG_DP_RHP_I_MSK 0xfff3ffff
++#define CBR_RG_DP_RHP_SFT 18
++#define CBR_RG_DP_RHP_HI 19
++#define CBR_RG_DP_RHP_SZ 2
++#define CBR_RG_DP_DR3_MSK 0x00700000
++#define CBR_RG_DP_DR3_I_MSK 0xff8fffff
++#define CBR_RG_DP_DR3_SFT 20
++#define CBR_RG_DP_DR3_HI 22
++#define CBR_RG_DP_DR3_SZ 3
++#define CBR_RG_DP_DCP_MSK 0x07800000
++#define CBR_RG_DP_DCP_I_MSK 0xf87fffff
++#define CBR_RG_DP_DCP_SFT 23
++#define CBR_RG_DP_DCP_HI 26
++#define CBR_RG_DP_DCP_SZ 4
++#define CBR_RG_DP_DCS_MSK 0x78000000
++#define CBR_RG_DP_DCS_I_MSK 0x87ffffff
++#define CBR_RG_DP_DCS_SFT 27
++#define CBR_RG_DP_DCS_HI 30
++#define CBR_RG_DP_DCS_SZ 4
++#define CBR_RG_DP_FBDIV_MSK 0x00000fff
++#define CBR_RG_DP_FBDIV_I_MSK 0xfffff000
++#define CBR_RG_DP_FBDIV_SFT 0
++#define CBR_RG_DP_FBDIV_HI 11
++#define CBR_RG_DP_FBDIV_SZ 12
++#define CBR_RG_DP_FODIV_MSK 0x003ff000
++#define CBR_RG_DP_FODIV_I_MSK 0xffc00fff
++#define CBR_RG_DP_FODIV_SFT 12
++#define CBR_RG_DP_FODIV_HI 21
++#define CBR_RG_DP_FODIV_SZ 10
++#define CBR_RG_DP_REFDIV_MSK 0xffc00000
++#define CBR_RG_DP_REFDIV_I_MSK 0x003fffff
++#define CBR_RG_DP_REFDIV_SFT 22
++#define CBR_RG_DP_REFDIV_HI 31
++#define CBR_RG_DP_REFDIV_SZ 10
++#define CBR_RG_IDACAI_PGAG15_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG15_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG15_SFT 0
++#define CBR_RG_IDACAI_PGAG15_HI 5
++#define CBR_RG_IDACAI_PGAG15_SZ 6
++#define CBR_RG_IDACAQ_PGAG15_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG15_SFT 6
++#define CBR_RG_IDACAQ_PGAG15_HI 11
++#define CBR_RG_IDACAQ_PGAG15_SZ 6
++#define CBR_RG_IDACAI_PGAG14_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG14_SFT 12
++#define CBR_RG_IDACAI_PGAG14_HI 17
++#define CBR_RG_IDACAI_PGAG14_SZ 6
++#define CBR_RG_IDACAQ_PGAG14_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG14_SFT 18
++#define CBR_RG_IDACAQ_PGAG14_HI 23
++#define CBR_RG_IDACAQ_PGAG14_SZ 6
++#define CBR_RG_IDACAI_PGAG13_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG13_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG13_SFT 0
++#define CBR_RG_IDACAI_PGAG13_HI 5
++#define CBR_RG_IDACAI_PGAG13_SZ 6
++#define CBR_RG_IDACAQ_PGAG13_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG13_SFT 6
++#define CBR_RG_IDACAQ_PGAG13_HI 11
++#define CBR_RG_IDACAQ_PGAG13_SZ 6
++#define CBR_RG_IDACAI_PGAG12_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG12_SFT 12
++#define CBR_RG_IDACAI_PGAG12_HI 17
++#define CBR_RG_IDACAI_PGAG12_SZ 6
++#define CBR_RG_IDACAQ_PGAG12_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG12_SFT 18
++#define CBR_RG_IDACAQ_PGAG12_HI 23
++#define CBR_RG_IDACAQ_PGAG12_SZ 6
++#define CBR_RG_IDACAI_PGAG11_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG11_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG11_SFT 0
++#define CBR_RG_IDACAI_PGAG11_HI 5
++#define CBR_RG_IDACAI_PGAG11_SZ 6
++#define CBR_RG_IDACAQ_PGAG11_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG11_SFT 6
++#define CBR_RG_IDACAQ_PGAG11_HI 11
++#define CBR_RG_IDACAQ_PGAG11_SZ 6
++#define CBR_RG_IDACAI_PGAG10_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG10_SFT 12
++#define CBR_RG_IDACAI_PGAG10_HI 17
++#define CBR_RG_IDACAI_PGAG10_SZ 6
++#define CBR_RG_IDACAQ_PGAG10_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG10_SFT 18
++#define CBR_RG_IDACAQ_PGAG10_HI 23
++#define CBR_RG_IDACAQ_PGAG10_SZ 6
++#define CBR_RG_IDACAI_PGAG9_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG9_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG9_SFT 0
++#define CBR_RG_IDACAI_PGAG9_HI 5
++#define CBR_RG_IDACAI_PGAG9_SZ 6
++#define CBR_RG_IDACAQ_PGAG9_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG9_SFT 6
++#define CBR_RG_IDACAQ_PGAG9_HI 11
++#define CBR_RG_IDACAQ_PGAG9_SZ 6
++#define CBR_RG_IDACAI_PGAG8_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG8_SFT 12
++#define CBR_RG_IDACAI_PGAG8_HI 17
++#define CBR_RG_IDACAI_PGAG8_SZ 6
++#define CBR_RG_IDACAQ_PGAG8_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG8_SFT 18
++#define CBR_RG_IDACAQ_PGAG8_HI 23
++#define CBR_RG_IDACAQ_PGAG8_SZ 6
++#define CBR_RG_IDACAI_PGAG7_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG7_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG7_SFT 0
++#define CBR_RG_IDACAI_PGAG7_HI 5
++#define CBR_RG_IDACAI_PGAG7_SZ 6
++#define CBR_RG_IDACAQ_PGAG7_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG7_SFT 6
++#define CBR_RG_IDACAQ_PGAG7_HI 11
++#define CBR_RG_IDACAQ_PGAG7_SZ 6
++#define CBR_RG_IDACAI_PGAG6_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG6_SFT 12
++#define CBR_RG_IDACAI_PGAG6_HI 17
++#define CBR_RG_IDACAI_PGAG6_SZ 6
++#define CBR_RG_IDACAQ_PGAG6_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG6_SFT 18
++#define CBR_RG_IDACAQ_PGAG6_HI 23
++#define CBR_RG_IDACAQ_PGAG6_SZ 6
++#define CBR_RG_IDACAI_PGAG5_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG5_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG5_SFT 0
++#define CBR_RG_IDACAI_PGAG5_HI 5
++#define CBR_RG_IDACAI_PGAG5_SZ 6
++#define CBR_RG_IDACAQ_PGAG5_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG5_SFT 6
++#define CBR_RG_IDACAQ_PGAG5_HI 11
++#define CBR_RG_IDACAQ_PGAG5_SZ 6
++#define CBR_RG_IDACAI_PGAG4_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG4_SFT 12
++#define CBR_RG_IDACAI_PGAG4_HI 17
++#define CBR_RG_IDACAI_PGAG4_SZ 6
++#define CBR_RG_IDACAQ_PGAG4_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG4_SFT 18
++#define CBR_RG_IDACAQ_PGAG4_HI 23
++#define CBR_RG_IDACAQ_PGAG4_SZ 6
++#define CBR_RG_IDACAI_PGAG3_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG3_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG3_SFT 0
++#define CBR_RG_IDACAI_PGAG3_HI 5
++#define CBR_RG_IDACAI_PGAG3_SZ 6
++#define CBR_RG_IDACAQ_PGAG3_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG3_SFT 6
++#define CBR_RG_IDACAQ_PGAG3_HI 11
++#define CBR_RG_IDACAQ_PGAG3_SZ 6
++#define CBR_RG_IDACAI_PGAG2_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG2_SFT 12
++#define CBR_RG_IDACAI_PGAG2_HI 17
++#define CBR_RG_IDACAI_PGAG2_SZ 6
++#define CBR_RG_IDACAQ_PGAG2_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG2_SFT 18
++#define CBR_RG_IDACAQ_PGAG2_HI 23
++#define CBR_RG_IDACAQ_PGAG2_SZ 6
++#define CBR_RG_IDACAI_PGAG1_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG1_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG1_SFT 0
++#define CBR_RG_IDACAI_PGAG1_HI 5
++#define CBR_RG_IDACAI_PGAG1_SZ 6
++#define CBR_RG_IDACAQ_PGAG1_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG1_SFT 6
++#define CBR_RG_IDACAQ_PGAG1_HI 11
++#define CBR_RG_IDACAQ_PGAG1_SZ 6
++#define CBR_RG_IDACAI_PGAG0_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG0_SFT 12
++#define CBR_RG_IDACAI_PGAG0_HI 17
++#define CBR_RG_IDACAI_PGAG0_SZ 6
++#define CBR_RG_IDACAQ_PGAG0_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG0_SFT 18
++#define CBR_RG_IDACAQ_PGAG0_HI 23
++#define CBR_RG_IDACAQ_PGAG0_SZ 6
++#define CBR_RG_EN_RCAL_MSK 0x00000001
++#define CBR_RG_EN_RCAL_I_MSK 0xfffffffe
++#define CBR_RG_EN_RCAL_SFT 0
++#define CBR_RG_EN_RCAL_HI 0
++#define CBR_RG_EN_RCAL_SZ 1
++#define CBR_RG_RCAL_SPD_MSK 0x00000002
++#define CBR_RG_RCAL_SPD_I_MSK 0xfffffffd
++#define CBR_RG_RCAL_SPD_SFT 1
++#define CBR_RG_RCAL_SPD_HI 1
++#define CBR_RG_RCAL_SPD_SZ 1
++#define CBR_RG_RCAL_TMR_MSK 0x000001fc
++#define CBR_RG_RCAL_TMR_I_MSK 0xfffffe03
++#define CBR_RG_RCAL_TMR_SFT 2
++#define CBR_RG_RCAL_TMR_HI 8
++#define CBR_RG_RCAL_TMR_SZ 7
++#define CBR_RG_RCAL_CODE_CWR_MSK 0x00000200
++#define CBR_RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
++#define CBR_RG_RCAL_CODE_CWR_SFT 9
++#define CBR_RG_RCAL_CODE_CWR_HI 9
++#define CBR_RG_RCAL_CODE_CWR_SZ 1
++#define CBR_RG_RCAL_CODE_CWD_MSK 0x00007c00
++#define CBR_RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
++#define CBR_RG_RCAL_CODE_CWD_SFT 10
++#define CBR_RG_RCAL_CODE_CWD_HI 14
++#define CBR_RG_RCAL_CODE_CWD_SZ 5
++#define CBR_RG_SX_SUB_SEL_CWR_MSK 0x00000001
++#define CBR_RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
++#define CBR_RG_SX_SUB_SEL_CWR_SFT 0
++#define CBR_RG_SX_SUB_SEL_CWR_HI 0
++#define CBR_RG_SX_SUB_SEL_CWR_SZ 1
++#define CBR_RG_SX_SUB_SEL_CWD_MSK 0x000000fe
++#define CBR_RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
++#define CBR_RG_SX_SUB_SEL_CWD_SFT 1
++#define CBR_RG_SX_SUB_SEL_CWD_HI 7
++#define CBR_RG_SX_SUB_SEL_CWD_SZ 7
++#define CBR_RG_DP_BBPLL_BS_CWR_MSK 0x00000100
++#define CBR_RG_DP_BBPLL_BS_CWR_I_MSK 0xfffffeff
++#define CBR_RG_DP_BBPLL_BS_CWR_SFT 8
++#define CBR_RG_DP_BBPLL_BS_CWR_HI 8
++#define CBR_RG_DP_BBPLL_BS_CWR_SZ 1
++#define CBR_RG_DP_BBPLL_BS_CWD_MSK 0x00007e00
++#define CBR_RG_DP_BBPLL_BS_CWD_I_MSK 0xffff81ff
++#define CBR_RG_DP_BBPLL_BS_CWD_SFT 9
++#define CBR_RG_DP_BBPLL_BS_CWD_HI 14
++#define CBR_RG_DP_BBPLL_BS_CWD_SZ 6
++#define CBR_RCAL_RDY_MSK 0x00000001
++#define CBR_RCAL_RDY_I_MSK 0xfffffffe
++#define CBR_RCAL_RDY_SFT 0
++#define CBR_RCAL_RDY_HI 0
++#define CBR_RCAL_RDY_SZ 1
++#define CBR_DA_LCK_RDY_MSK 0x00000002
++#define CBR_DA_LCK_RDY_I_MSK 0xfffffffd
++#define CBR_DA_LCK_RDY_SFT 1
++#define CBR_DA_LCK_RDY_HI 1
++#define CBR_DA_LCK_RDY_SZ 1
++#define CBR_VT_MON_RDY_MSK 0x00000004
++#define CBR_VT_MON_RDY_I_MSK 0xfffffffb
++#define CBR_VT_MON_RDY_SFT 2
++#define CBR_VT_MON_RDY_HI 2
++#define CBR_VT_MON_RDY_SZ 1
++#define CBR_DP_VT_MON_RDY_MSK 0x00000008
++#define CBR_DP_VT_MON_RDY_I_MSK 0xfffffff7
++#define CBR_DP_VT_MON_RDY_SFT 3
++#define CBR_DP_VT_MON_RDY_HI 3
++#define CBR_DP_VT_MON_RDY_SZ 1
++#define CBR_CH_RDY_MSK 0x00000010
++#define CBR_CH_RDY_I_MSK 0xffffffef
++#define CBR_CH_RDY_SFT 4
++#define CBR_CH_RDY_HI 4
++#define CBR_CH_RDY_SZ 1
++#define CBR_DA_R_CODE_LUT_MSK 0x000007c0
++#define CBR_DA_R_CODE_LUT_I_MSK 0xfffff83f
++#define CBR_DA_R_CODE_LUT_SFT 6
++#define CBR_DA_R_CODE_LUT_HI 10
++#define CBR_DA_R_CODE_LUT_SZ 5
++#define CBR_AD_SX_VT_MON_Q_MSK 0x00001800
++#define CBR_AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
++#define CBR_AD_SX_VT_MON_Q_SFT 11
++#define CBR_AD_SX_VT_MON_Q_HI 12
++#define CBR_AD_SX_VT_MON_Q_SZ 2
++#define CBR_AD_DP_VT_MON_Q_MSK 0x00006000
++#define CBR_AD_DP_VT_MON_Q_I_MSK 0xffff9fff
++#define CBR_AD_DP_VT_MON_Q_SFT 13
++#define CBR_AD_DP_VT_MON_Q_HI 14
++#define CBR_AD_DP_VT_MON_Q_SZ 2
++#define CBR_DA_R_CAL_CODE_MSK 0x0000001f
++#define CBR_DA_R_CAL_CODE_I_MSK 0xffffffe0
++#define CBR_DA_R_CAL_CODE_SFT 0
++#define CBR_DA_R_CAL_CODE_HI 4
++#define CBR_DA_R_CAL_CODE_SZ 5
++#define CBR_DA_SX_SUB_SEL_MSK 0x00000fe0
++#define CBR_DA_SX_SUB_SEL_I_MSK 0xfffff01f
++#define CBR_DA_SX_SUB_SEL_SFT 5
++#define CBR_DA_SX_SUB_SEL_HI 11
++#define CBR_DA_SX_SUB_SEL_SZ 7
++#define CBR_DA_DP_BBPLL_BS_MSK 0x0003f000
++#define CBR_DA_DP_BBPLL_BS_I_MSK 0xfffc0fff
++#define CBR_DA_DP_BBPLL_BS_SFT 12
++#define CBR_DA_DP_BBPLL_BS_HI 17
++#define CBR_DA_DP_BBPLL_BS_SZ 6
++#define CBR_TX_EN_MSK 0x00000001
++#define CBR_TX_EN_I_MSK 0xfffffffe
++#define CBR_TX_EN_SFT 0
++#define CBR_TX_EN_HI 0
++#define CBR_TX_EN_SZ 1
++#define CBR_TX_CNT_RST_MSK 0x00000002
++#define CBR_TX_CNT_RST_I_MSK 0xfffffffd
++#define CBR_TX_CNT_RST_SFT 1
++#define CBR_TX_CNT_RST_HI 1
++#define CBR_TX_CNT_RST_SZ 1
++#define CBR_IFS_TIME_MSK 0x000000fc
++#define CBR_IFS_TIME_I_MSK 0xffffff03
++#define CBR_IFS_TIME_SFT 2
++#define CBR_IFS_TIME_HI 7
++#define CBR_IFS_TIME_SZ 6
++#define CBR_LENGTH_TARGET_MSK 0x000fff00
++#define CBR_LENGTH_TARGET_I_MSK 0xfff000ff
++#define CBR_LENGTH_TARGET_SFT 8
++#define CBR_LENGTH_TARGET_HI 19
++#define CBR_LENGTH_TARGET_SZ 12
++#define CBR_TX_CNT_TARGET_MSK 0xff000000
++#define CBR_TX_CNT_TARGET_I_MSK 0x00ffffff
++#define CBR_TX_CNT_TARGET_SFT 24
++#define CBR_TX_CNT_TARGET_HI 31
++#define CBR_TX_CNT_TARGET_SZ 8
++#define CBR_TC_CNT_TARGET_MSK 0x00ffffff
++#define CBR_TC_CNT_TARGET_I_MSK 0xff000000
++#define CBR_TC_CNT_TARGET_SFT 0
++#define CBR_TC_CNT_TARGET_HI 23
++#define CBR_TC_CNT_TARGET_SZ 24
++#define CBR_PLCP_PSDU_DATA_MEM_MSK 0x000000ff
++#define CBR_PLCP_PSDU_DATA_MEM_I_MSK 0xffffff00
++#define CBR_PLCP_PSDU_DATA_MEM_SFT 0
++#define CBR_PLCP_PSDU_DATA_MEM_HI 7
++#define CBR_PLCP_PSDU_DATA_MEM_SZ 8
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK 0x00000100
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK 0xfffffeff
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT 8
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_HI 8
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ 1
++#define CBR_PLCP_BYTE_LENGTH_MSK 0x001ffe00
++#define CBR_PLCP_BYTE_LENGTH_I_MSK 0xffe001ff
++#define CBR_PLCP_BYTE_LENGTH_SFT 9
++#define CBR_PLCP_BYTE_LENGTH_HI 20
++#define CBR_PLCP_BYTE_LENGTH_SZ 12
++#define CBR_PLCP_PSDU_RATE_MSK 0x00600000
++#define CBR_PLCP_PSDU_RATE_I_MSK 0xff9fffff
++#define CBR_PLCP_PSDU_RATE_SFT 21
++#define CBR_PLCP_PSDU_RATE_HI 22
++#define CBR_PLCP_PSDU_RATE_SZ 2
++#define CBR_TAIL_TIME_MSK 0x1f800000
++#define CBR_TAIL_TIME_I_MSK 0xe07fffff
++#define CBR_TAIL_TIME_SFT 23
++#define CBR_TAIL_TIME_HI 28
++#define CBR_TAIL_TIME_SZ 6
++#define CBR_RG_O_PAD_PD_MSK 0x00000001
++#define CBR_RG_O_PAD_PD_I_MSK 0xfffffffe
++#define CBR_RG_O_PAD_PD_SFT 0
++#define CBR_RG_O_PAD_PD_HI 0
++#define CBR_RG_O_PAD_PD_SZ 1
++#define CBR_RG_I_PAD_PD_MSK 0x00000002
++#define CBR_RG_I_PAD_PD_I_MSK 0xfffffffd
++#define CBR_RG_I_PAD_PD_SFT 1
++#define CBR_RG_I_PAD_PD_HI 1
++#define CBR_RG_I_PAD_PD_SZ 1
++#define CBR_SEL_ADCKP_INV_MSK 0x00000004
++#define CBR_SEL_ADCKP_INV_I_MSK 0xfffffffb
++#define CBR_SEL_ADCKP_INV_SFT 2
++#define CBR_SEL_ADCKP_INV_HI 2
++#define CBR_SEL_ADCKP_INV_SZ 1
++#define CBR_RG_PAD_DS_MSK 0x00000008
++#define CBR_RG_PAD_DS_I_MSK 0xfffffff7
++#define CBR_RG_PAD_DS_SFT 3
++#define CBR_RG_PAD_DS_HI 3
++#define CBR_RG_PAD_DS_SZ 1
++#define CBR_SEL_ADCKP_MUX_MSK 0x00000010
++#define CBR_SEL_ADCKP_MUX_I_MSK 0xffffffef
++#define CBR_SEL_ADCKP_MUX_SFT 4
++#define CBR_SEL_ADCKP_MUX_HI 4
++#define CBR_SEL_ADCKP_MUX_SZ 1
++#define CBR_RG_PAD_DS_CLK_MSK 0x00000020
++#define CBR_RG_PAD_DS_CLK_I_MSK 0xffffffdf
++#define CBR_RG_PAD_DS_CLK_SFT 5
++#define CBR_RG_PAD_DS_CLK_HI 5
++#define CBR_RG_PAD_DS_CLK_SZ 1
++#define CBR_INTP_SEL_MSK 0x00000200
++#define CBR_INTP_SEL_I_MSK 0xfffffdff
++#define CBR_INTP_SEL_SFT 9
++#define CBR_INTP_SEL_HI 9
++#define CBR_INTP_SEL_SZ 1
++#define CBR_IQ_SWP_MSK 0x00000400
++#define CBR_IQ_SWP_I_MSK 0xfffffbff
++#define CBR_IQ_SWP_SFT 10
++#define CBR_IQ_SWP_HI 10
++#define CBR_IQ_SWP_SZ 1
++#define CBR_RG_EN_EXT_DA_MSK 0x00000800
++#define CBR_RG_EN_EXT_DA_I_MSK 0xfffff7ff
++#define CBR_RG_EN_EXT_DA_SFT 11
++#define CBR_RG_EN_EXT_DA_HI 11
++#define CBR_RG_EN_EXT_DA_SZ 1
++#define CBR_RG_DIS_DA_OFFSET_MSK 0x00001000
++#define CBR_RG_DIS_DA_OFFSET_I_MSK 0xffffefff
++#define CBR_RG_DIS_DA_OFFSET_SFT 12
++#define CBR_RG_DIS_DA_OFFSET_HI 12
++#define CBR_RG_DIS_DA_OFFSET_SZ 1
++#define CBR_DBG_SEL_MSK 0x000f0000
++#define CBR_DBG_SEL_I_MSK 0xfff0ffff
++#define CBR_DBG_SEL_SFT 16
++#define CBR_DBG_SEL_HI 19
++#define CBR_DBG_SEL_SZ 4
++#define CBR_DBG_EN_MSK 0x00100000
++#define CBR_DBG_EN_I_MSK 0xffefffff
++#define CBR_DBG_EN_SFT 20
++#define CBR_DBG_EN_HI 20
++#define CBR_DBG_EN_SZ 1
++#define CBR_RG_PKT_GEN_TX_CNT_MSK 0xffffffff
++#define CBR_RG_PKT_GEN_TX_CNT_I_MSK 0x00000000
++#define CBR_RG_PKT_GEN_TX_CNT_SFT 0
++#define CBR_RG_PKT_GEN_TX_CNT_HI 31
++#define CBR_RG_PKT_GEN_TX_CNT_SZ 32
++#define CBR_TP_SEL_MSK 0x0000001f
++#define CBR_TP_SEL_I_MSK 0xffffffe0
++#define CBR_TP_SEL_SFT 0
++#define CBR_TP_SEL_HI 4
++#define CBR_TP_SEL_SZ 5
++#define CBR_IDEAL_IQ_EN_MSK 0x00000020
++#define CBR_IDEAL_IQ_EN_I_MSK 0xffffffdf
++#define CBR_IDEAL_IQ_EN_SFT 5
++#define CBR_IDEAL_IQ_EN_HI 5
++#define CBR_IDEAL_IQ_EN_SZ 1
++#define CBR_DATA_OUT_SEL_MSK 0x000001c0
++#define CBR_DATA_OUT_SEL_I_MSK 0xfffffe3f
++#define CBR_DATA_OUT_SEL_SFT 6
++#define CBR_DATA_OUT_SEL_HI 8
++#define CBR_DATA_OUT_SEL_SZ 3
++#define CBR_TWO_TONE_EN_MSK 0x00000200
++#define CBR_TWO_TONE_EN_I_MSK 0xfffffdff
++#define CBR_TWO_TONE_EN_SFT 9
++#define CBR_TWO_TONE_EN_HI 9
++#define CBR_TWO_TONE_EN_SZ 1
++#define CBR_FREQ_SEL_MSK 0x00ff0000
++#define CBR_FREQ_SEL_I_MSK 0xff00ffff
++#define CBR_FREQ_SEL_SFT 16
++#define CBR_FREQ_SEL_HI 23
++#define CBR_FREQ_SEL_SZ 8
++#define CBR_IQ_SCALE_MSK 0xff000000
++#define CBR_IQ_SCALE_I_MSK 0x00ffffff
++#define CBR_IQ_SCALE_SFT 24
++#define CBR_IQ_SCALE_HI 31
++#define CBR_IQ_SCALE_SZ 8
++#define CPU_QUE_POP_MSK 0x00000001
++#define CPU_QUE_POP_I_MSK 0xfffffffe
++#define CPU_QUE_POP_SFT 0
++#define CPU_QUE_POP_HI 0
++#define CPU_QUE_POP_SZ 1
++#define CPU_INT_MSK 0x00000004
++#define CPU_INT_I_MSK 0xfffffffb
++#define CPU_INT_SFT 2
++#define CPU_INT_HI 2
++#define CPU_INT_SZ 1
++#define CPU_ID_TB0_MSK 0xffffffff
++#define CPU_ID_TB0_I_MSK 0x00000000
++#define CPU_ID_TB0_SFT 0
++#define CPU_ID_TB0_HI 31
++#define CPU_ID_TB0_SZ 32
++#define CPU_ID_TB1_MSK 0xffffffff
++#define CPU_ID_TB1_I_MSK 0x00000000
++#define CPU_ID_TB1_SFT 0
++#define CPU_ID_TB1_HI 31
++#define CPU_ID_TB1_SZ 32
++#define HW_PKTID_MSK 0x000007ff
++#define HW_PKTID_I_MSK 0xfffff800
++#define HW_PKTID_SFT 0
++#define HW_PKTID_HI 10
++#define HW_PKTID_SZ 11
++#define CH0_INT_ADDR_MSK 0xffffffff
++#define CH0_INT_ADDR_I_MSK 0x00000000
++#define CH0_INT_ADDR_SFT 0
++#define CH0_INT_ADDR_HI 31
++#define CH0_INT_ADDR_SZ 32
++#define PRI_HW_PKTID_MSK 0x000007ff
++#define PRI_HW_PKTID_I_MSK 0xfffff800
++#define PRI_HW_PKTID_SFT 0
++#define PRI_HW_PKTID_HI 10
++#define PRI_HW_PKTID_SZ 11
++#define CH0_FULL_MSK 0x00000001
++#define CH0_FULL_I_MSK 0xfffffffe
++#define CH0_FULL_SFT 0
++#define CH0_FULL_HI 0
++#define CH0_FULL_SZ 1
++#define FF0_EMPTY_MSK 0x00000002
++#define FF0_EMPTY_I_MSK 0xfffffffd
++#define FF0_EMPTY_SFT 1
++#define FF0_EMPTY_HI 1
++#define FF0_EMPTY_SZ 1
++#define RLS_BUSY_MSK 0x00000200
++#define RLS_BUSY_I_MSK 0xfffffdff
++#define RLS_BUSY_SFT 9
++#define RLS_BUSY_HI 9
++#define RLS_BUSY_SZ 1
++#define RLS_COUNT_CLR_MSK 0x00000400
++#define RLS_COUNT_CLR_I_MSK 0xfffffbff
++#define RLS_COUNT_CLR_SFT 10
++#define RLS_COUNT_CLR_HI 10
++#define RLS_COUNT_CLR_SZ 1
++#define RTN_COUNT_CLR_MSK 0x00000800
++#define RTN_COUNT_CLR_I_MSK 0xfffff7ff
++#define RTN_COUNT_CLR_SFT 11
++#define RTN_COUNT_CLR_HI 11
++#define RTN_COUNT_CLR_SZ 1
++#define RLS_COUNT_MSK 0x00ff0000
++#define RLS_COUNT_I_MSK 0xff00ffff
++#define RLS_COUNT_SFT 16
++#define RLS_COUNT_HI 23
++#define RLS_COUNT_SZ 8
++#define RTN_COUNT_MSK 0xff000000
++#define RTN_COUNT_I_MSK 0x00ffffff
++#define RTN_COUNT_SFT 24
++#define RTN_COUNT_HI 31
++#define RTN_COUNT_SZ 8
++#define FF0_CNT_MSK 0x0000001f
++#define FF0_CNT_I_MSK 0xffffffe0
++#define FF0_CNT_SFT 0
++#define FF0_CNT_HI 4
++#define FF0_CNT_SZ 5
++#define FF1_CNT_MSK 0x000001e0
++#define FF1_CNT_I_MSK 0xfffffe1f
++#define FF1_CNT_SFT 5
++#define FF1_CNT_HI 8
++#define FF1_CNT_SZ 4
++#define FF3_CNT_MSK 0x00003800
++#define FF3_CNT_I_MSK 0xffffc7ff
++#define FF3_CNT_SFT 11
++#define FF3_CNT_HI 13
++#define FF3_CNT_SZ 3
++#define FF5_CNT_MSK 0x000e0000
++#define FF5_CNT_I_MSK 0xfff1ffff
++#define FF5_CNT_SFT 17
++#define FF5_CNT_HI 19
++#define FF5_CNT_SZ 3
++#define FF6_CNT_MSK 0x00700000
++#define FF6_CNT_I_MSK 0xff8fffff
++#define FF6_CNT_SFT 20
++#define FF6_CNT_HI 22
++#define FF6_CNT_SZ 3
++#define FF7_CNT_MSK 0x03800000
++#define FF7_CNT_I_MSK 0xfc7fffff
++#define FF7_CNT_SFT 23
++#define FF7_CNT_HI 25
++#define FF7_CNT_SZ 3
++#define FF8_CNT_MSK 0x1c000000
++#define FF8_CNT_I_MSK 0xe3ffffff
++#define FF8_CNT_SFT 26
++#define FF8_CNT_HI 28
++#define FF8_CNT_SZ 3
++#define FF9_CNT_MSK 0xe0000000
++#define FF9_CNT_I_MSK 0x1fffffff
++#define FF9_CNT_SFT 29
++#define FF9_CNT_HI 31
++#define FF9_CNT_SZ 3
++#define FF10_CNT_MSK 0x00000007
++#define FF10_CNT_I_MSK 0xfffffff8
++#define FF10_CNT_SFT 0
++#define FF10_CNT_HI 2
++#define FF10_CNT_SZ 3
++#define FF11_CNT_MSK 0x00000038
++#define FF11_CNT_I_MSK 0xffffffc7
++#define FF11_CNT_SFT 3
++#define FF11_CNT_HI 5
++#define FF11_CNT_SZ 3
++#define FF12_CNT_MSK 0x000001c0
++#define FF12_CNT_I_MSK 0xfffffe3f
++#define FF12_CNT_SFT 6
++#define FF12_CNT_HI 8
++#define FF12_CNT_SZ 3
++#define FF13_CNT_MSK 0x00000600
++#define FF13_CNT_I_MSK 0xfffff9ff
++#define FF13_CNT_SFT 9
++#define FF13_CNT_HI 10
++#define FF13_CNT_SZ 2
++#define FF14_CNT_MSK 0x00001800
++#define FF14_CNT_I_MSK 0xffffe7ff
++#define FF14_CNT_SFT 11
++#define FF14_CNT_HI 12
++#define FF14_CNT_SZ 2
++#define FF15_CNT_MSK 0x00006000
++#define FF15_CNT_I_MSK 0xffff9fff
++#define FF15_CNT_SFT 13
++#define FF15_CNT_HI 14
++#define FF15_CNT_SZ 2
++#define FF4_CNT_MSK 0x000f8000
++#define FF4_CNT_I_MSK 0xfff07fff
++#define FF4_CNT_SFT 15
++#define FF4_CNT_HI 19
++#define FF4_CNT_SZ 5
++#define FF2_CNT_MSK 0x00700000
++#define FF2_CNT_I_MSK 0xff8fffff
++#define FF2_CNT_SFT 20
++#define FF2_CNT_HI 22
++#define FF2_CNT_SZ 3
++#define CH1_FULL_MSK 0x00000002
++#define CH1_FULL_I_MSK 0xfffffffd
++#define CH1_FULL_SFT 1
++#define CH1_FULL_HI 1
++#define CH1_FULL_SZ 1
++#define CH2_FULL_MSK 0x00000004
++#define CH2_FULL_I_MSK 0xfffffffb
++#define CH2_FULL_SFT 2
++#define CH2_FULL_HI 2
++#define CH2_FULL_SZ 1
++#define CH3_FULL_MSK 0x00000008
++#define CH3_FULL_I_MSK 0xfffffff7
++#define CH3_FULL_SFT 3
++#define CH3_FULL_HI 3
++#define CH3_FULL_SZ 1
++#define CH4_FULL_MSK 0x00000010
++#define CH4_FULL_I_MSK 0xffffffef
++#define CH4_FULL_SFT 4
++#define CH4_FULL_HI 4
++#define CH4_FULL_SZ 1
++#define CH5_FULL_MSK 0x00000020
++#define CH5_FULL_I_MSK 0xffffffdf
++#define CH5_FULL_SFT 5
++#define CH5_FULL_HI 5
++#define CH5_FULL_SZ 1
++#define CH6_FULL_MSK 0x00000040
++#define CH6_FULL_I_MSK 0xffffffbf
++#define CH6_FULL_SFT 6
++#define CH6_FULL_HI 6
++#define CH6_FULL_SZ 1
++#define CH7_FULL_MSK 0x00000080
++#define CH7_FULL_I_MSK 0xffffff7f
++#define CH7_FULL_SFT 7
++#define CH7_FULL_HI 7
++#define CH7_FULL_SZ 1
++#define CH8_FULL_MSK 0x00000100
++#define CH8_FULL_I_MSK 0xfffffeff
++#define CH8_FULL_SFT 8
++#define CH8_FULL_HI 8
++#define CH8_FULL_SZ 1
++#define CH9_FULL_MSK 0x00000200
++#define CH9_FULL_I_MSK 0xfffffdff
++#define CH9_FULL_SFT 9
++#define CH9_FULL_HI 9
++#define CH9_FULL_SZ 1
++#define CH10_FULL_MSK 0x00000400
++#define CH10_FULL_I_MSK 0xfffffbff
++#define CH10_FULL_SFT 10
++#define CH10_FULL_HI 10
++#define CH10_FULL_SZ 1
++#define CH11_FULL_MSK 0x00000800
++#define CH11_FULL_I_MSK 0xfffff7ff
++#define CH11_FULL_SFT 11
++#define CH11_FULL_HI 11
++#define CH11_FULL_SZ 1
++#define CH12_FULL_MSK 0x00001000
++#define CH12_FULL_I_MSK 0xffffefff
++#define CH12_FULL_SFT 12
++#define CH12_FULL_HI 12
++#define CH12_FULL_SZ 1
++#define CH13_FULL_MSK 0x00002000
++#define CH13_FULL_I_MSK 0xffffdfff
++#define CH13_FULL_SFT 13
++#define CH13_FULL_HI 13
++#define CH13_FULL_SZ 1
++#define CH14_FULL_MSK 0x00004000
++#define CH14_FULL_I_MSK 0xffffbfff
++#define CH14_FULL_SFT 14
++#define CH14_FULL_HI 14
++#define CH14_FULL_SZ 1
++#define CH15_FULL_MSK 0x00008000
++#define CH15_FULL_I_MSK 0xffff7fff
++#define CH15_FULL_SFT 15
++#define CH15_FULL_HI 15
++#define CH15_FULL_SZ 1
++#define HALT_CH0_MSK 0x00000001
++#define HALT_CH0_I_MSK 0xfffffffe
++#define HALT_CH0_SFT 0
++#define HALT_CH0_HI 0
++#define HALT_CH0_SZ 1
++#define HALT_CH1_MSK 0x00000002
++#define HALT_CH1_I_MSK 0xfffffffd
++#define HALT_CH1_SFT 1
++#define HALT_CH1_HI 1
++#define HALT_CH1_SZ 1
++#define HALT_CH2_MSK 0x00000004
++#define HALT_CH2_I_MSK 0xfffffffb
++#define HALT_CH2_SFT 2
++#define HALT_CH2_HI 2
++#define HALT_CH2_SZ 1
++#define HALT_CH3_MSK 0x00000008
++#define HALT_CH3_I_MSK 0xfffffff7
++#define HALT_CH3_SFT 3
++#define HALT_CH3_HI 3
++#define HALT_CH3_SZ 1
++#define HALT_CH4_MSK 0x00000010
++#define HALT_CH4_I_MSK 0xffffffef
++#define HALT_CH4_SFT 4
++#define HALT_CH4_HI 4
++#define HALT_CH4_SZ 1
++#define HALT_CH5_MSK 0x00000020
++#define HALT_CH5_I_MSK 0xffffffdf
++#define HALT_CH5_SFT 5
++#define HALT_CH5_HI 5
++#define HALT_CH5_SZ 1
++#define HALT_CH6_MSK 0x00000040
++#define HALT_CH6_I_MSK 0xffffffbf
++#define HALT_CH6_SFT 6
++#define HALT_CH6_HI 6
++#define HALT_CH6_SZ 1
++#define HALT_CH7_MSK 0x00000080
++#define HALT_CH7_I_MSK 0xffffff7f
++#define HALT_CH7_SFT 7
++#define HALT_CH7_HI 7
++#define HALT_CH7_SZ 1
++#define HALT_CH8_MSK 0x00000100
++#define HALT_CH8_I_MSK 0xfffffeff
++#define HALT_CH8_SFT 8
++#define HALT_CH8_HI 8
++#define HALT_CH8_SZ 1
++#define HALT_CH9_MSK 0x00000200
++#define HALT_CH9_I_MSK 0xfffffdff
++#define HALT_CH9_SFT 9
++#define HALT_CH9_HI 9
++#define HALT_CH9_SZ 1
++#define HALT_CH10_MSK 0x00000400
++#define HALT_CH10_I_MSK 0xfffffbff
++#define HALT_CH10_SFT 10
++#define HALT_CH10_HI 10
++#define HALT_CH10_SZ 1
++#define HALT_CH11_MSK 0x00000800
++#define HALT_CH11_I_MSK 0xfffff7ff
++#define HALT_CH11_SFT 11
++#define HALT_CH11_HI 11
++#define HALT_CH11_SZ 1
++#define HALT_CH12_MSK 0x00001000
++#define HALT_CH12_I_MSK 0xffffefff
++#define HALT_CH12_SFT 12
++#define HALT_CH12_HI 12
++#define HALT_CH12_SZ 1
++#define HALT_CH13_MSK 0x00002000
++#define HALT_CH13_I_MSK 0xffffdfff
++#define HALT_CH13_SFT 13
++#define HALT_CH13_HI 13
++#define HALT_CH13_SZ 1
++#define HALT_CH14_MSK 0x00004000
++#define HALT_CH14_I_MSK 0xffffbfff
++#define HALT_CH14_SFT 14
++#define HALT_CH14_HI 14
++#define HALT_CH14_SZ 1
++#define HALT_CH15_MSK 0x00008000
++#define HALT_CH15_I_MSK 0xffff7fff
++#define HALT_CH15_SFT 15
++#define HALT_CH15_HI 15
++#define HALT_CH15_SZ 1
++#define STOP_MBOX_MSK 0x00010000
++#define STOP_MBOX_I_MSK 0xfffeffff
++#define STOP_MBOX_SFT 16
++#define STOP_MBOX_HI 16
++#define STOP_MBOX_SZ 1
++#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000
++#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff
++#define MB_ERR_AUTO_HALT_EN_SFT 20
++#define MB_ERR_AUTO_HALT_EN_HI 20
++#define MB_ERR_AUTO_HALT_EN_SZ 1
++#define MB_EXCEPT_CLR_MSK 0x00200000
++#define MB_EXCEPT_CLR_I_MSK 0xffdfffff
++#define MB_EXCEPT_CLR_SFT 21
++#define MB_EXCEPT_CLR_HI 21
++#define MB_EXCEPT_CLR_SZ 1
++#define MB_EXCEPT_CASE_MSK 0xff000000
++#define MB_EXCEPT_CASE_I_MSK 0x00ffffff
++#define MB_EXCEPT_CASE_SFT 24
++#define MB_EXCEPT_CASE_HI 31
++#define MB_EXCEPT_CASE_SZ 8
++#define MB_DBG_TIME_STEP_MSK 0x0000ffff
++#define MB_DBG_TIME_STEP_I_MSK 0xffff0000
++#define MB_DBG_TIME_STEP_SFT 0
++#define MB_DBG_TIME_STEP_HI 15
++#define MB_DBG_TIME_STEP_SZ 16
++#define DBG_TYPE_MSK 0x00030000
++#define DBG_TYPE_I_MSK 0xfffcffff
++#define DBG_TYPE_SFT 16
++#define DBG_TYPE_HI 17
++#define DBG_TYPE_SZ 2
++#define MB_DBG_CLR_MSK 0x00040000
++#define MB_DBG_CLR_I_MSK 0xfffbffff
++#define MB_DBG_CLR_SFT 18
++#define MB_DBG_CLR_HI 18
++#define MB_DBG_CLR_SZ 1
++#define DBG_ALC_LOG_EN_MSK 0x00080000
++#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff
++#define DBG_ALC_LOG_EN_SFT 19
++#define DBG_ALC_LOG_EN_HI 19
++#define DBG_ALC_LOG_EN_SZ 1
++#define MB_DBG_COUNTER_EN_MSK 0x01000000
++#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff
++#define MB_DBG_COUNTER_EN_SFT 24
++#define MB_DBG_COUNTER_EN_HI 24
++#define MB_DBG_COUNTER_EN_SZ 1
++#define MB_DBG_EN_MSK 0x80000000
++#define MB_DBG_EN_I_MSK 0x7fffffff
++#define MB_DBG_EN_SFT 31
++#define MB_DBG_EN_HI 31
++#define MB_DBG_EN_SZ 1
++#define MB_DBG_RECORD_CNT_MSK 0x0000ffff
++#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000
++#define MB_DBG_RECORD_CNT_SFT 0
++#define MB_DBG_RECORD_CNT_HI 15
++#define MB_DBG_RECORD_CNT_SZ 16
++#define MB_DBG_LENGTH_MSK 0xffff0000
++#define MB_DBG_LENGTH_I_MSK 0x0000ffff
++#define MB_DBG_LENGTH_SFT 16
++#define MB_DBG_LENGTH_HI 31
++#define MB_DBG_LENGTH_SZ 16
++#define MB_DBG_CFG_ADDR_MSK 0xffffffff
++#define MB_DBG_CFG_ADDR_I_MSK 0x00000000
++#define MB_DBG_CFG_ADDR_SFT 0
++#define MB_DBG_CFG_ADDR_HI 31
++#define MB_DBG_CFG_ADDR_SZ 32
++#define DBG_HWID0_WR_EN_MSK 0x00000001
++#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe
++#define DBG_HWID0_WR_EN_SFT 0
++#define DBG_HWID0_WR_EN_HI 0
++#define DBG_HWID0_WR_EN_SZ 1
++#define DBG_HWID1_WR_EN_MSK 0x00000002
++#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd
++#define DBG_HWID1_WR_EN_SFT 1
++#define DBG_HWID1_WR_EN_HI 1
++#define DBG_HWID1_WR_EN_SZ 1
++#define DBG_HWID2_WR_EN_MSK 0x00000004
++#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb
++#define DBG_HWID2_WR_EN_SFT 2
++#define DBG_HWID2_WR_EN_HI 2
++#define DBG_HWID2_WR_EN_SZ 1
++#define DBG_HWID3_WR_EN_MSK 0x00000008
++#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7
++#define DBG_HWID3_WR_EN_SFT 3
++#define DBG_HWID3_WR_EN_HI 3
++#define DBG_HWID3_WR_EN_SZ 1
++#define DBG_HWID4_WR_EN_MSK 0x00000010
++#define DBG_HWID4_WR_EN_I_MSK 0xffffffef
++#define DBG_HWID4_WR_EN_SFT 4
++#define DBG_HWID4_WR_EN_HI 4
++#define DBG_HWID4_WR_EN_SZ 1
++#define DBG_HWID5_WR_EN_MSK 0x00000020
++#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf
++#define DBG_HWID5_WR_EN_SFT 5
++#define DBG_HWID5_WR_EN_HI 5
++#define DBG_HWID5_WR_EN_SZ 1
++#define DBG_HWID6_WR_EN_MSK 0x00000040
++#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf
++#define DBG_HWID6_WR_EN_SFT 6
++#define DBG_HWID6_WR_EN_HI 6
++#define DBG_HWID6_WR_EN_SZ 1
++#define DBG_HWID7_WR_EN_MSK 0x00000080
++#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f
++#define DBG_HWID7_WR_EN_SFT 7
++#define DBG_HWID7_WR_EN_HI 7
++#define DBG_HWID7_WR_EN_SZ 1
++#define DBG_HWID8_WR_EN_MSK 0x00000100
++#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff
++#define DBG_HWID8_WR_EN_SFT 8
++#define DBG_HWID8_WR_EN_HI 8
++#define DBG_HWID8_WR_EN_SZ 1
++#define DBG_HWID9_WR_EN_MSK 0x00000200
++#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff
++#define DBG_HWID9_WR_EN_SFT 9
++#define DBG_HWID9_WR_EN_HI 9
++#define DBG_HWID9_WR_EN_SZ 1
++#define DBG_HWID10_WR_EN_MSK 0x00000400
++#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff
++#define DBG_HWID10_WR_EN_SFT 10
++#define DBG_HWID10_WR_EN_HI 10
++#define DBG_HWID10_WR_EN_SZ 1
++#define DBG_HWID11_WR_EN_MSK 0x00000800
++#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff
++#define DBG_HWID11_WR_EN_SFT 11
++#define DBG_HWID11_WR_EN_HI 11
++#define DBG_HWID11_WR_EN_SZ 1
++#define DBG_HWID12_WR_EN_MSK 0x00001000
++#define DBG_HWID12_WR_EN_I_MSK 0xffffefff
++#define DBG_HWID12_WR_EN_SFT 12
++#define DBG_HWID12_WR_EN_HI 12
++#define DBG_HWID12_WR_EN_SZ 1
++#define DBG_HWID13_WR_EN_MSK 0x00002000
++#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff
++#define DBG_HWID13_WR_EN_SFT 13
++#define DBG_HWID13_WR_EN_HI 13
++#define DBG_HWID13_WR_EN_SZ 1
++#define DBG_HWID14_WR_EN_MSK 0x00004000
++#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff
++#define DBG_HWID14_WR_EN_SFT 14
++#define DBG_HWID14_WR_EN_HI 14
++#define DBG_HWID14_WR_EN_SZ 1
++#define DBG_HWID15_WR_EN_MSK 0x00008000
++#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff
++#define DBG_HWID15_WR_EN_SFT 15
++#define DBG_HWID15_WR_EN_HI 15
++#define DBG_HWID15_WR_EN_SZ 1
++#define DBG_HWID0_RD_EN_MSK 0x00010000
++#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff
++#define DBG_HWID0_RD_EN_SFT 16
++#define DBG_HWID0_RD_EN_HI 16
++#define DBG_HWID0_RD_EN_SZ 1
++#define DBG_HWID1_RD_EN_MSK 0x00020000
++#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff
++#define DBG_HWID1_RD_EN_SFT 17
++#define DBG_HWID1_RD_EN_HI 17
++#define DBG_HWID1_RD_EN_SZ 1
++#define DBG_HWID2_RD_EN_MSK 0x00040000
++#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff
++#define DBG_HWID2_RD_EN_SFT 18
++#define DBG_HWID2_RD_EN_HI 18
++#define DBG_HWID2_RD_EN_SZ 1
++#define DBG_HWID3_RD_EN_MSK 0x00080000
++#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff
++#define DBG_HWID3_RD_EN_SFT 19
++#define DBG_HWID3_RD_EN_HI 19
++#define DBG_HWID3_RD_EN_SZ 1
++#define DBG_HWID4_RD_EN_MSK 0x00100000
++#define DBG_HWID4_RD_EN_I_MSK 0xffefffff
++#define DBG_HWID4_RD_EN_SFT 20
++#define DBG_HWID4_RD_EN_HI 20
++#define DBG_HWID4_RD_EN_SZ 1
++#define DBG_HWID5_RD_EN_MSK 0x00200000
++#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff
++#define DBG_HWID5_RD_EN_SFT 21
++#define DBG_HWID5_RD_EN_HI 21
++#define DBG_HWID5_RD_EN_SZ 1
++#define DBG_HWID6_RD_EN_MSK 0x00400000
++#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff
++#define DBG_HWID6_RD_EN_SFT 22
++#define DBG_HWID6_RD_EN_HI 22
++#define DBG_HWID6_RD_EN_SZ 1
++#define DBG_HWID7_RD_EN_MSK 0x00800000
++#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff
++#define DBG_HWID7_RD_EN_SFT 23
++#define DBG_HWID7_RD_EN_HI 23
++#define DBG_HWID7_RD_EN_SZ 1
++#define DBG_HWID8_RD_EN_MSK 0x01000000
++#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff
++#define DBG_HWID8_RD_EN_SFT 24
++#define DBG_HWID8_RD_EN_HI 24
++#define DBG_HWID8_RD_EN_SZ 1
++#define DBG_HWID9_RD_EN_MSK 0x02000000
++#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff
++#define DBG_HWID9_RD_EN_SFT 25
++#define DBG_HWID9_RD_EN_HI 25
++#define DBG_HWID9_RD_EN_SZ 1
++#define DBG_HWID10_RD_EN_MSK 0x04000000
++#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff
++#define DBG_HWID10_RD_EN_SFT 26
++#define DBG_HWID10_RD_EN_HI 26
++#define DBG_HWID10_RD_EN_SZ 1
++#define DBG_HWID11_RD_EN_MSK 0x08000000
++#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff
++#define DBG_HWID11_RD_EN_SFT 27
++#define DBG_HWID11_RD_EN_HI 27
++#define DBG_HWID11_RD_EN_SZ 1
++#define DBG_HWID12_RD_EN_MSK 0x10000000
++#define DBG_HWID12_RD_EN_I_MSK 0xefffffff
++#define DBG_HWID12_RD_EN_SFT 28
++#define DBG_HWID12_RD_EN_HI 28
++#define DBG_HWID12_RD_EN_SZ 1
++#define DBG_HWID13_RD_EN_MSK 0x20000000
++#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff
++#define DBG_HWID13_RD_EN_SFT 29
++#define DBG_HWID13_RD_EN_HI 29
++#define DBG_HWID13_RD_EN_SZ 1
++#define DBG_HWID14_RD_EN_MSK 0x40000000
++#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff
++#define DBG_HWID14_RD_EN_SFT 30
++#define DBG_HWID14_RD_EN_HI 30
++#define DBG_HWID14_RD_EN_SZ 1
++#define DBG_HWID15_RD_EN_MSK 0x80000000
++#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff
++#define DBG_HWID15_RD_EN_SFT 31
++#define DBG_HWID15_RD_EN_HI 31
++#define DBG_HWID15_RD_EN_SZ 1
++#define MB_OUT_QUEUE_EN_MSK 0x00000002
++#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd
++#define MB_OUT_QUEUE_EN_SFT 1
++#define MB_OUT_QUEUE_EN_HI 1
++#define MB_OUT_QUEUE_EN_SZ 1
++#define CH0_QUEUE_FLUSH_MSK 0x00000001
++#define CH0_QUEUE_FLUSH_I_MSK 0xfffffffe
++#define CH0_QUEUE_FLUSH_SFT 0
++#define CH0_QUEUE_FLUSH_HI 0
++#define CH0_QUEUE_FLUSH_SZ 1
++#define CH1_QUEUE_FLUSH_MSK 0x00000002
++#define CH1_QUEUE_FLUSH_I_MSK 0xfffffffd
++#define CH1_QUEUE_FLUSH_SFT 1
++#define CH1_QUEUE_FLUSH_HI 1
++#define CH1_QUEUE_FLUSH_SZ 1
++#define CH2_QUEUE_FLUSH_MSK 0x00000004
++#define CH2_QUEUE_FLUSH_I_MSK 0xfffffffb
++#define CH2_QUEUE_FLUSH_SFT 2
++#define CH2_QUEUE_FLUSH_HI 2
++#define CH2_QUEUE_FLUSH_SZ 1
++#define CH3_QUEUE_FLUSH_MSK 0x00000008
++#define CH3_QUEUE_FLUSH_I_MSK 0xfffffff7
++#define CH3_QUEUE_FLUSH_SFT 3
++#define CH3_QUEUE_FLUSH_HI 3
++#define CH3_QUEUE_FLUSH_SZ 1
++#define CH4_QUEUE_FLUSH_MSK 0x00000010
++#define CH4_QUEUE_FLUSH_I_MSK 0xffffffef
++#define CH4_QUEUE_FLUSH_SFT 4
++#define CH4_QUEUE_FLUSH_HI 4
++#define CH4_QUEUE_FLUSH_SZ 1
++#define CH5_QUEUE_FLUSH_MSK 0x00000020
++#define CH5_QUEUE_FLUSH_I_MSK 0xffffffdf
++#define CH5_QUEUE_FLUSH_SFT 5
++#define CH5_QUEUE_FLUSH_HI 5
++#define CH5_QUEUE_FLUSH_SZ 1
++#define CH6_QUEUE_FLUSH_MSK 0x00000040
++#define CH6_QUEUE_FLUSH_I_MSK 0xffffffbf
++#define CH6_QUEUE_FLUSH_SFT 6
++#define CH6_QUEUE_FLUSH_HI 6
++#define CH6_QUEUE_FLUSH_SZ 1
++#define CH7_QUEUE_FLUSH_MSK 0x00000080
++#define CH7_QUEUE_FLUSH_I_MSK 0xffffff7f
++#define CH7_QUEUE_FLUSH_SFT 7
++#define CH7_QUEUE_FLUSH_HI 7
++#define CH7_QUEUE_FLUSH_SZ 1
++#define CH8_QUEUE_FLUSH_MSK 0x00000100
++#define CH8_QUEUE_FLUSH_I_MSK 0xfffffeff
++#define CH8_QUEUE_FLUSH_SFT 8
++#define CH8_QUEUE_FLUSH_HI 8
++#define CH8_QUEUE_FLUSH_SZ 1
++#define CH9_QUEUE_FLUSH_MSK 0x00000200
++#define CH9_QUEUE_FLUSH_I_MSK 0xfffffdff
++#define CH9_QUEUE_FLUSH_SFT 9
++#define CH9_QUEUE_FLUSH_HI 9
++#define CH9_QUEUE_FLUSH_SZ 1
++#define CH10_QUEUE_FLUSH_MSK 0x00000400
++#define CH10_QUEUE_FLUSH_I_MSK 0xfffffbff
++#define CH10_QUEUE_FLUSH_SFT 10
++#define CH10_QUEUE_FLUSH_HI 10
++#define CH10_QUEUE_FLUSH_SZ 1
++#define CH11_QUEUE_FLUSH_MSK 0x00000800
++#define CH11_QUEUE_FLUSH_I_MSK 0xfffff7ff
++#define CH11_QUEUE_FLUSH_SFT 11
++#define CH11_QUEUE_FLUSH_HI 11
++#define CH11_QUEUE_FLUSH_SZ 1
++#define CH12_QUEUE_FLUSH_MSK 0x00001000
++#define CH12_QUEUE_FLUSH_I_MSK 0xffffefff
++#define CH12_QUEUE_FLUSH_SFT 12
++#define CH12_QUEUE_FLUSH_HI 12
++#define CH12_QUEUE_FLUSH_SZ 1
++#define CH13_QUEUE_FLUSH_MSK 0x00002000
++#define CH13_QUEUE_FLUSH_I_MSK 0xffffdfff
++#define CH13_QUEUE_FLUSH_SFT 13
++#define CH13_QUEUE_FLUSH_HI 13
++#define CH13_QUEUE_FLUSH_SZ 1
++#define CH14_QUEUE_FLUSH_MSK 0x00004000
++#define CH14_QUEUE_FLUSH_I_MSK 0xffffbfff
++#define CH14_QUEUE_FLUSH_SFT 14
++#define CH14_QUEUE_FLUSH_HI 14
++#define CH14_QUEUE_FLUSH_SZ 1
++#define CH15_QUEUE_FLUSH_MSK 0x00008000
++#define CH15_QUEUE_FLUSH_I_MSK 0xffff7fff
++#define CH15_QUEUE_FLUSH_SFT 15
++#define CH15_QUEUE_FLUSH_HI 15
++#define CH15_QUEUE_FLUSH_SZ 1
++#define FFO0_CNT_MSK 0x0000001f
++#define FFO0_CNT_I_MSK 0xffffffe0
++#define FFO0_CNT_SFT 0
++#define FFO0_CNT_HI 4
++#define FFO0_CNT_SZ 5
++#define FFO1_CNT_MSK 0x000003e0
++#define FFO1_CNT_I_MSK 0xfffffc1f
++#define FFO1_CNT_SFT 5
++#define FFO1_CNT_HI 9
++#define FFO1_CNT_SZ 5
++#define FFO2_CNT_MSK 0x00000c00
++#define FFO2_CNT_I_MSK 0xfffff3ff
++#define FFO2_CNT_SFT 10
++#define FFO2_CNT_HI 11
++#define FFO2_CNT_SZ 2
++#define FFO3_CNT_MSK 0x000f8000
++#define FFO3_CNT_I_MSK 0xfff07fff
++#define FFO3_CNT_SFT 15
++#define FFO3_CNT_HI 19
++#define FFO3_CNT_SZ 5
++#define FFO4_CNT_MSK 0x00300000
++#define FFO4_CNT_I_MSK 0xffcfffff
++#define FFO4_CNT_SFT 20
++#define FFO4_CNT_HI 21
++#define FFO4_CNT_SZ 2
++#define FFO5_CNT_MSK 0x0e000000
++#define FFO5_CNT_I_MSK 0xf1ffffff
++#define FFO5_CNT_SFT 25
++#define FFO5_CNT_HI 27
++#define FFO5_CNT_SZ 3
++#define FFO6_CNT_MSK 0x0000000f
++#define FFO6_CNT_I_MSK 0xfffffff0
++#define FFO6_CNT_SFT 0
++#define FFO6_CNT_HI 3
++#define FFO6_CNT_SZ 4
++#define FFO7_CNT_MSK 0x000003e0
++#define FFO7_CNT_I_MSK 0xfffffc1f
++#define FFO7_CNT_SFT 5
++#define FFO7_CNT_HI 9
++#define FFO7_CNT_SZ 5
++#define FFO8_CNT_MSK 0x00007c00
++#define FFO8_CNT_I_MSK 0xffff83ff
++#define FFO8_CNT_SFT 10
++#define FFO8_CNT_HI 14
++#define FFO8_CNT_SZ 5
++#define FFO9_CNT_MSK 0x000f8000
++#define FFO9_CNT_I_MSK 0xfff07fff
++#define FFO9_CNT_SFT 15
++#define FFO9_CNT_HI 19
++#define FFO9_CNT_SZ 5
++#define FFO10_CNT_MSK 0x00f00000
++#define FFO10_CNT_I_MSK 0xff0fffff
++#define FFO10_CNT_SFT 20
++#define FFO10_CNT_HI 23
++#define FFO10_CNT_SZ 4
++#define FFO11_CNT_MSK 0x3e000000
++#define FFO11_CNT_I_MSK 0xc1ffffff
++#define FFO11_CNT_SFT 25
++#define FFO11_CNT_HI 29
++#define FFO11_CNT_SZ 5
++#define FFO12_CNT_MSK 0x00000007
++#define FFO12_CNT_I_MSK 0xfffffff8
++#define FFO12_CNT_SFT 0
++#define FFO12_CNT_HI 2
++#define FFO12_CNT_SZ 3
++#define FFO13_CNT_MSK 0x00000060
++#define FFO13_CNT_I_MSK 0xffffff9f
++#define FFO13_CNT_SFT 5
++#define FFO13_CNT_HI 6
++#define FFO13_CNT_SZ 2
++#define FFO14_CNT_MSK 0x00000c00
++#define FFO14_CNT_I_MSK 0xfffff3ff
++#define FFO14_CNT_SFT 10
++#define FFO14_CNT_HI 11
++#define FFO14_CNT_SZ 2
++#define FFO15_CNT_MSK 0x001f8000
++#define FFO15_CNT_I_MSK 0xffe07fff
++#define FFO15_CNT_SFT 15
++#define FFO15_CNT_HI 20
++#define FFO15_CNT_SZ 6
++#define CH0_FFO_FULL_MSK 0x00000001
++#define CH0_FFO_FULL_I_MSK 0xfffffffe
++#define CH0_FFO_FULL_SFT 0
++#define CH0_FFO_FULL_HI 0
++#define CH0_FFO_FULL_SZ 1
++#define CH1_FFO_FULL_MSK 0x00000002
++#define CH1_FFO_FULL_I_MSK 0xfffffffd
++#define CH1_FFO_FULL_SFT 1
++#define CH1_FFO_FULL_HI 1
++#define CH1_FFO_FULL_SZ 1
++#define CH2_FFO_FULL_MSK 0x00000004
++#define CH2_FFO_FULL_I_MSK 0xfffffffb
++#define CH2_FFO_FULL_SFT 2
++#define CH2_FFO_FULL_HI 2
++#define CH2_FFO_FULL_SZ 1
++#define CH3_FFO_FULL_MSK 0x00000008
++#define CH3_FFO_FULL_I_MSK 0xfffffff7
++#define CH3_FFO_FULL_SFT 3
++#define CH3_FFO_FULL_HI 3
++#define CH3_FFO_FULL_SZ 1
++#define CH4_FFO_FULL_MSK 0x00000010
++#define CH4_FFO_FULL_I_MSK 0xffffffef
++#define CH4_FFO_FULL_SFT 4
++#define CH4_FFO_FULL_HI 4
++#define CH4_FFO_FULL_SZ 1
++#define CH5_FFO_FULL_MSK 0x00000020
++#define CH5_FFO_FULL_I_MSK 0xffffffdf
++#define CH5_FFO_FULL_SFT 5
++#define CH5_FFO_FULL_HI 5
++#define CH5_FFO_FULL_SZ 1
++#define CH6_FFO_FULL_MSK 0x00000040
++#define CH6_FFO_FULL_I_MSK 0xffffffbf
++#define CH6_FFO_FULL_SFT 6
++#define CH6_FFO_FULL_HI 6
++#define CH6_FFO_FULL_SZ 1
++#define CH7_FFO_FULL_MSK 0x00000080
++#define CH7_FFO_FULL_I_MSK 0xffffff7f
++#define CH7_FFO_FULL_SFT 7
++#define CH7_FFO_FULL_HI 7
++#define CH7_FFO_FULL_SZ 1
++#define CH8_FFO_FULL_MSK 0x00000100
++#define CH8_FFO_FULL_I_MSK 0xfffffeff
++#define CH8_FFO_FULL_SFT 8
++#define CH8_FFO_FULL_HI 8
++#define CH8_FFO_FULL_SZ 1
++#define CH9_FFO_FULL_MSK 0x00000200
++#define CH9_FFO_FULL_I_MSK 0xfffffdff
++#define CH9_FFO_FULL_SFT 9
++#define CH9_FFO_FULL_HI 9
++#define CH9_FFO_FULL_SZ 1
++#define CH10_FFO_FULL_MSK 0x00000400
++#define CH10_FFO_FULL_I_MSK 0xfffffbff
++#define CH10_FFO_FULL_SFT 10
++#define CH10_FFO_FULL_HI 10
++#define CH10_FFO_FULL_SZ 1
++#define CH11_FFO_FULL_MSK 0x00000800
++#define CH11_FFO_FULL_I_MSK 0xfffff7ff
++#define CH11_FFO_FULL_SFT 11
++#define CH11_FFO_FULL_HI 11
++#define CH11_FFO_FULL_SZ 1
++#define CH12_FFO_FULL_MSK 0x00001000
++#define CH12_FFO_FULL_I_MSK 0xffffefff
++#define CH12_FFO_FULL_SFT 12
++#define CH12_FFO_FULL_HI 12
++#define CH12_FFO_FULL_SZ 1
++#define CH13_FFO_FULL_MSK 0x00002000
++#define CH13_FFO_FULL_I_MSK 0xffffdfff
++#define CH13_FFO_FULL_SFT 13
++#define CH13_FFO_FULL_HI 13
++#define CH13_FFO_FULL_SZ 1
++#define CH14_FFO_FULL_MSK 0x00004000
++#define CH14_FFO_FULL_I_MSK 0xffffbfff
++#define CH14_FFO_FULL_SFT 14
++#define CH14_FFO_FULL_HI 14
++#define CH14_FFO_FULL_SZ 1
++#define CH15_FFO_FULL_MSK 0x00008000
++#define CH15_FFO_FULL_I_MSK 0xffff7fff
++#define CH15_FFO_FULL_SFT 15
++#define CH15_FFO_FULL_HI 15
++#define CH15_FFO_FULL_SZ 1
++#define CH0_LOWTHOLD_INT_MSK 0x00000001
++#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe
++#define CH0_LOWTHOLD_INT_SFT 0
++#define CH0_LOWTHOLD_INT_HI 0
++#define CH0_LOWTHOLD_INT_SZ 1
++#define CH1_LOWTHOLD_INT_MSK 0x00000002
++#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd
++#define CH1_LOWTHOLD_INT_SFT 1
++#define CH1_LOWTHOLD_INT_HI 1
++#define CH1_LOWTHOLD_INT_SZ 1
++#define CH2_LOWTHOLD_INT_MSK 0x00000004
++#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb
++#define CH2_LOWTHOLD_INT_SFT 2
++#define CH2_LOWTHOLD_INT_HI 2
++#define CH2_LOWTHOLD_INT_SZ 1
++#define CH3_LOWTHOLD_INT_MSK 0x00000008
++#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7
++#define CH3_LOWTHOLD_INT_SFT 3
++#define CH3_LOWTHOLD_INT_HI 3
++#define CH3_LOWTHOLD_INT_SZ 1
++#define CH4_LOWTHOLD_INT_MSK 0x00000010
++#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef
++#define CH4_LOWTHOLD_INT_SFT 4
++#define CH4_LOWTHOLD_INT_HI 4
++#define CH4_LOWTHOLD_INT_SZ 1
++#define CH5_LOWTHOLD_INT_MSK 0x00000020
++#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf
++#define CH5_LOWTHOLD_INT_SFT 5
++#define CH5_LOWTHOLD_INT_HI 5
++#define CH5_LOWTHOLD_INT_SZ 1
++#define CH6_LOWTHOLD_INT_MSK 0x00000040
++#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf
++#define CH6_LOWTHOLD_INT_SFT 6
++#define CH6_LOWTHOLD_INT_HI 6
++#define CH6_LOWTHOLD_INT_SZ 1
++#define CH7_LOWTHOLD_INT_MSK 0x00000080
++#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f
++#define CH7_LOWTHOLD_INT_SFT 7
++#define CH7_LOWTHOLD_INT_HI 7
++#define CH7_LOWTHOLD_INT_SZ 1
++#define CH8_LOWTHOLD_INT_MSK 0x00000100
++#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff
++#define CH8_LOWTHOLD_INT_SFT 8
++#define CH8_LOWTHOLD_INT_HI 8
++#define CH8_LOWTHOLD_INT_SZ 1
++#define CH9_LOWTHOLD_INT_MSK 0x00000200
++#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff
++#define CH9_LOWTHOLD_INT_SFT 9
++#define CH9_LOWTHOLD_INT_HI 9
++#define CH9_LOWTHOLD_INT_SZ 1
++#define CH10_LOWTHOLD_INT_MSK 0x00000400
++#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff
++#define CH10_LOWTHOLD_INT_SFT 10
++#define CH10_LOWTHOLD_INT_HI 10
++#define CH10_LOWTHOLD_INT_SZ 1
++#define CH11_LOWTHOLD_INT_MSK 0x00000800
++#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff
++#define CH11_LOWTHOLD_INT_SFT 11
++#define CH11_LOWTHOLD_INT_HI 11
++#define CH11_LOWTHOLD_INT_SZ 1
++#define CH12_LOWTHOLD_INT_MSK 0x00001000
++#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff
++#define CH12_LOWTHOLD_INT_SFT 12
++#define CH12_LOWTHOLD_INT_HI 12
++#define CH12_LOWTHOLD_INT_SZ 1
++#define CH13_LOWTHOLD_INT_MSK 0x00002000
++#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff
++#define CH13_LOWTHOLD_INT_SFT 13
++#define CH13_LOWTHOLD_INT_HI 13
++#define CH13_LOWTHOLD_INT_SZ 1
++#define CH14_LOWTHOLD_INT_MSK 0x00004000
++#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff
++#define CH14_LOWTHOLD_INT_SFT 14
++#define CH14_LOWTHOLD_INT_HI 14
++#define CH14_LOWTHOLD_INT_SZ 1
++#define CH15_LOWTHOLD_INT_MSK 0x00008000
++#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff
++#define CH15_LOWTHOLD_INT_SFT 15
++#define CH15_LOWTHOLD_INT_HI 15
++#define CH15_LOWTHOLD_INT_SZ 1
++#define MB_LOW_THOLD_EN_MSK 0x80000000
++#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff
++#define MB_LOW_THOLD_EN_SFT 31
++#define MB_LOW_THOLD_EN_HI 31
++#define MB_LOW_THOLD_EN_SZ 1
++#define CH0_LOWTHOLD_MSK 0x0000001f
++#define CH0_LOWTHOLD_I_MSK 0xffffffe0
++#define CH0_LOWTHOLD_SFT 0
++#define CH0_LOWTHOLD_HI 4
++#define CH0_LOWTHOLD_SZ 5
++#define CH1_LOWTHOLD_MSK 0x00001f00
++#define CH1_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH1_LOWTHOLD_SFT 8
++#define CH1_LOWTHOLD_HI 12
++#define CH1_LOWTHOLD_SZ 5
++#define CH2_LOWTHOLD_MSK 0x001f0000
++#define CH2_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH2_LOWTHOLD_SFT 16
++#define CH2_LOWTHOLD_HI 20
++#define CH2_LOWTHOLD_SZ 5
++#define CH3_LOWTHOLD_MSK 0x1f000000
++#define CH3_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH3_LOWTHOLD_SFT 24
++#define CH3_LOWTHOLD_HI 28
++#define CH3_LOWTHOLD_SZ 5
++#define CH4_LOWTHOLD_MSK 0x0000001f
++#define CH4_LOWTHOLD_I_MSK 0xffffffe0
++#define CH4_LOWTHOLD_SFT 0
++#define CH4_LOWTHOLD_HI 4
++#define CH4_LOWTHOLD_SZ 5
++#define CH5_LOWTHOLD_MSK 0x00001f00
++#define CH5_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH5_LOWTHOLD_SFT 8
++#define CH5_LOWTHOLD_HI 12
++#define CH5_LOWTHOLD_SZ 5
++#define CH6_LOWTHOLD_MSK 0x001f0000
++#define CH6_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH6_LOWTHOLD_SFT 16
++#define CH6_LOWTHOLD_HI 20
++#define CH6_LOWTHOLD_SZ 5
++#define CH7_LOWTHOLD_MSK 0x1f000000
++#define CH7_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH7_LOWTHOLD_SFT 24
++#define CH7_LOWTHOLD_HI 28
++#define CH7_LOWTHOLD_SZ 5
++#define CH8_LOWTHOLD_MSK 0x0000001f
++#define CH8_LOWTHOLD_I_MSK 0xffffffe0
++#define CH8_LOWTHOLD_SFT 0
++#define CH8_LOWTHOLD_HI 4
++#define CH8_LOWTHOLD_SZ 5
++#define CH9_LOWTHOLD_MSK 0x00001f00
++#define CH9_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH9_LOWTHOLD_SFT 8
++#define CH9_LOWTHOLD_HI 12
++#define CH9_LOWTHOLD_SZ 5
++#define CH10_LOWTHOLD_MSK 0x001f0000
++#define CH10_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH10_LOWTHOLD_SFT 16
++#define CH10_LOWTHOLD_HI 20
++#define CH10_LOWTHOLD_SZ 5
++#define CH11_LOWTHOLD_MSK 0x1f000000
++#define CH11_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH11_LOWTHOLD_SFT 24
++#define CH11_LOWTHOLD_HI 28
++#define CH11_LOWTHOLD_SZ 5
++#define CH12_LOWTHOLD_MSK 0x0000001f
++#define CH12_LOWTHOLD_I_MSK 0xffffffe0
++#define CH12_LOWTHOLD_SFT 0
++#define CH12_LOWTHOLD_HI 4
++#define CH12_LOWTHOLD_SZ 5
++#define CH13_LOWTHOLD_MSK 0x00001f00
++#define CH13_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH13_LOWTHOLD_SFT 8
++#define CH13_LOWTHOLD_HI 12
++#define CH13_LOWTHOLD_SZ 5
++#define CH14_LOWTHOLD_MSK 0x001f0000
++#define CH14_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH14_LOWTHOLD_SFT 16
++#define CH14_LOWTHOLD_HI 20
++#define CH14_LOWTHOLD_SZ 5
++#define CH15_LOWTHOLD_MSK 0x1f000000
++#define CH15_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH15_LOWTHOLD_SFT 24
++#define CH15_LOWTHOLD_HI 28
++#define CH15_LOWTHOLD_SZ 5
++#define TRASH_TIMEOUT_EN_MSK 0x00000001
++#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe
++#define TRASH_TIMEOUT_EN_SFT 0
++#define TRASH_TIMEOUT_EN_HI 0
++#define TRASH_TIMEOUT_EN_SZ 1
++#define TRASH_CAN_INT_MSK 0x00000002
++#define TRASH_CAN_INT_I_MSK 0xfffffffd
++#define TRASH_CAN_INT_SFT 1
++#define TRASH_CAN_INT_HI 1
++#define TRASH_CAN_INT_SZ 1
++#define TRASH_INT_ID_MSK 0x000007f0
++#define TRASH_INT_ID_I_MSK 0xfffff80f
++#define TRASH_INT_ID_SFT 4
++#define TRASH_INT_ID_HI 10
++#define TRASH_INT_ID_SZ 7
++#define TRASH_TIMEOUT_MSK 0x03ff0000
++#define TRASH_TIMEOUT_I_MSK 0xfc00ffff
++#define TRASH_TIMEOUT_SFT 16
++#define TRASH_TIMEOUT_HI 25
++#define TRASH_TIMEOUT_SZ 10
++#define CH0_WRFF_FLUSH_MSK 0x00000001
++#define CH0_WRFF_FLUSH_I_MSK 0xfffffffe
++#define CH0_WRFF_FLUSH_SFT 0
++#define CH0_WRFF_FLUSH_HI 0
++#define CH0_WRFF_FLUSH_SZ 1
++#define CH1_WRFF_FLUSH_MSK 0x00000002
++#define CH1_WRFF_FLUSH_I_MSK 0xfffffffd
++#define CH1_WRFF_FLUSH_SFT 1
++#define CH1_WRFF_FLUSH_HI 1
++#define CH1_WRFF_FLUSH_SZ 1
++#define CH2_WRFF_FLUSH_MSK 0x00000004
++#define CH2_WRFF_FLUSH_I_MSK 0xfffffffb
++#define CH2_WRFF_FLUSH_SFT 2
++#define CH2_WRFF_FLUSH_HI 2
++#define CH2_WRFF_FLUSH_SZ 1
++#define CH3_WRFF_FLUSH_MSK 0x00000008
++#define CH3_WRFF_FLUSH_I_MSK 0xfffffff7
++#define CH3_WRFF_FLUSH_SFT 3
++#define CH3_WRFF_FLUSH_HI 3
++#define CH3_WRFF_FLUSH_SZ 1
++#define CH4_WRFF_FLUSH_MSK 0x00000010
++#define CH4_WRFF_FLUSH_I_MSK 0xffffffef
++#define CH4_WRFF_FLUSH_SFT 4
++#define CH4_WRFF_FLUSH_HI 4
++#define CH4_WRFF_FLUSH_SZ 1
++#define CH5_WRFF_FLUSH_MSK 0x00000020
++#define CH5_WRFF_FLUSH_I_MSK 0xffffffdf
++#define CH5_WRFF_FLUSH_SFT 5
++#define CH5_WRFF_FLUSH_HI 5
++#define CH5_WRFF_FLUSH_SZ 1
++#define CH6_WRFF_FLUSH_MSK 0x00000040
++#define CH6_WRFF_FLUSH_I_MSK 0xffffffbf
++#define CH6_WRFF_FLUSH_SFT 6
++#define CH6_WRFF_FLUSH_HI 6
++#define CH6_WRFF_FLUSH_SZ 1
++#define CH7_WRFF_FLUSH_MSK 0x00000080
++#define CH7_WRFF_FLUSH_I_MSK 0xffffff7f
++#define CH7_WRFF_FLUSH_SFT 7
++#define CH7_WRFF_FLUSH_HI 7
++#define CH7_WRFF_FLUSH_SZ 1
++#define CH8_WRFF_FLUSH_MSK 0x00000100
++#define CH8_WRFF_FLUSH_I_MSK 0xfffffeff
++#define CH8_WRFF_FLUSH_SFT 8
++#define CH8_WRFF_FLUSH_HI 8
++#define CH8_WRFF_FLUSH_SZ 1
++#define CH9_WRFF_FLUSH_MSK 0x00000200
++#define CH9_WRFF_FLUSH_I_MSK 0xfffffdff
++#define CH9_WRFF_FLUSH_SFT 9
++#define CH9_WRFF_FLUSH_HI 9
++#define CH9_WRFF_FLUSH_SZ 1
++#define CH10_WRFF_FLUSH_MSK 0x00000400
++#define CH10_WRFF_FLUSH_I_MSK 0xfffffbff
++#define CH10_WRFF_FLUSH_SFT 10
++#define CH10_WRFF_FLUSH_HI 10
++#define CH10_WRFF_FLUSH_SZ 1
++#define CH11_WRFF_FLUSH_MSK 0x00000800
++#define CH11_WRFF_FLUSH_I_MSK 0xfffff7ff
++#define CH11_WRFF_FLUSH_SFT 11
++#define CH11_WRFF_FLUSH_HI 11
++#define CH11_WRFF_FLUSH_SZ 1
++#define CH12_WRFF_FLUSH_MSK 0x00001000
++#define CH12_WRFF_FLUSH_I_MSK 0xffffefff
++#define CH12_WRFF_FLUSH_SFT 12
++#define CH12_WRFF_FLUSH_HI 12
++#define CH12_WRFF_FLUSH_SZ 1
++#define CH13_WRFF_FLUSH_MSK 0x00002000
++#define CH13_WRFF_FLUSH_I_MSK 0xffffdfff
++#define CH13_WRFF_FLUSH_SFT 13
++#define CH13_WRFF_FLUSH_HI 13
++#define CH13_WRFF_FLUSH_SZ 1
++#define CH14_WRFF_FLUSH_MSK 0x00004000
++#define CH14_WRFF_FLUSH_I_MSK 0xffffbfff
++#define CH14_WRFF_FLUSH_SFT 14
++#define CH14_WRFF_FLUSH_HI 14
++#define CH14_WRFF_FLUSH_SZ 1
++#define CPU_ID_TB2_MSK 0xffffffff
++#define CPU_ID_TB2_I_MSK 0x00000000
++#define CPU_ID_TB2_SFT 0
++#define CPU_ID_TB2_HI 31
++#define CPU_ID_TB2_SZ 32
++#define CPU_ID_TB3_MSK 0xffffffff
++#define CPU_ID_TB3_I_MSK 0x00000000
++#define CPU_ID_TB3_SFT 0
++#define CPU_ID_TB3_HI 31
++#define CPU_ID_TB3_SZ 32
++#define IQ_LOG_EN_MSK 0x00000001
++#define IQ_LOG_EN_I_MSK 0xfffffffe
++#define IQ_LOG_EN_SFT 0
++#define IQ_LOG_EN_HI 0
++#define IQ_LOG_EN_SZ 1
++#define IQ_LOG_STOP_MODE_MSK 0x00000001
++#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe
++#define IQ_LOG_STOP_MODE_SFT 0
++#define IQ_LOG_STOP_MODE_HI 0
++#define IQ_LOG_STOP_MODE_SZ 1
++#define GPIO_STOP_EN_MSK 0x00000010
++#define GPIO_STOP_EN_I_MSK 0xffffffef
++#define GPIO_STOP_EN_SFT 4
++#define GPIO_STOP_EN_HI 4
++#define GPIO_STOP_EN_SZ 1
++#define GPIO_STOP_POL_MSK 0x00000020
++#define GPIO_STOP_POL_I_MSK 0xffffffdf
++#define GPIO_STOP_POL_SFT 5
++#define GPIO_STOP_POL_HI 5
++#define GPIO_STOP_POL_SZ 1
++#define IQ_LOG_TIMER_MSK 0xffff0000
++#define IQ_LOG_TIMER_I_MSK 0x0000ffff
++#define IQ_LOG_TIMER_SFT 16
++#define IQ_LOG_TIMER_HI 31
++#define IQ_LOG_TIMER_SZ 16
++#define IQ_LOG_LEN_MSK 0x0000ffff
++#define IQ_LOG_LEN_I_MSK 0xffff0000
++#define IQ_LOG_LEN_SFT 0
++#define IQ_LOG_LEN_HI 15
++#define IQ_LOG_LEN_SZ 16
++#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff
++#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000
++#define IQ_LOG_TAIL_ADR_SFT 0
++#define IQ_LOG_TAIL_ADR_HI 15
++#define IQ_LOG_TAIL_ADR_SZ 16
++#define ALC_LENG_MSK 0x0003ffff
++#define ALC_LENG_I_MSK 0xfffc0000
++#define ALC_LENG_SFT 0
++#define ALC_LENG_HI 17
++#define ALC_LENG_SZ 18
++#define CH0_DYN_PRI_MSK 0x00300000
++#define CH0_DYN_PRI_I_MSK 0xffcfffff
++#define CH0_DYN_PRI_SFT 20
++#define CH0_DYN_PRI_HI 21
++#define CH0_DYN_PRI_SZ 2
++#define MCU_PKTID_MSK 0xffffffff
++#define MCU_PKTID_I_MSK 0x00000000
++#define MCU_PKTID_SFT 0
++#define MCU_PKTID_HI 31
++#define MCU_PKTID_SZ 32
++#define CH0_STA_PRI_MSK 0x00000003
++#define CH0_STA_PRI_I_MSK 0xfffffffc
++#define CH0_STA_PRI_SFT 0
++#define CH0_STA_PRI_HI 1
++#define CH0_STA_PRI_SZ 2
++#define CH1_STA_PRI_MSK 0x00000030
++#define CH1_STA_PRI_I_MSK 0xffffffcf
++#define CH1_STA_PRI_SFT 4
++#define CH1_STA_PRI_HI 5
++#define CH1_STA_PRI_SZ 2
++#define CH2_STA_PRI_MSK 0x00000300
++#define CH2_STA_PRI_I_MSK 0xfffffcff
++#define CH2_STA_PRI_SFT 8
++#define CH2_STA_PRI_HI 9
++#define CH2_STA_PRI_SZ 2
++#define CH3_STA_PRI_MSK 0x00003000
++#define CH3_STA_PRI_I_MSK 0xffffcfff
++#define CH3_STA_PRI_SFT 12
++#define CH3_STA_PRI_HI 13
++#define CH3_STA_PRI_SZ 2
++#define ID_TB0_MSK 0xffffffff
++#define ID_TB0_I_MSK 0x00000000
++#define ID_TB0_SFT 0
++#define ID_TB0_HI 31
++#define ID_TB0_SZ 32
++#define ID_TB1_MSK 0xffffffff
++#define ID_TB1_I_MSK 0x00000000
++#define ID_TB1_SFT 0
++#define ID_TB1_HI 31
++#define ID_TB1_SZ 32
++#define ID_MNG_HALT_MSK 0x00000010
++#define ID_MNG_HALT_I_MSK 0xffffffef
++#define ID_MNG_HALT_SFT 4
++#define ID_MNG_HALT_HI 4
++#define ID_MNG_HALT_SZ 1
++#define ID_MNG_ERR_HALT_EN_MSK 0x00000020
++#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf
++#define ID_MNG_ERR_HALT_EN_SFT 5
++#define ID_MNG_ERR_HALT_EN_HI 5
++#define ID_MNG_ERR_HALT_EN_SZ 1
++#define ID_EXCEPT_FLG_CLR_MSK 0x00000040
++#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf
++#define ID_EXCEPT_FLG_CLR_SFT 6
++#define ID_EXCEPT_FLG_CLR_HI 6
++#define ID_EXCEPT_FLG_CLR_SZ 1
++#define ID_EXCEPT_FLG_MSK 0x00000080
++#define ID_EXCEPT_FLG_I_MSK 0xffffff7f
++#define ID_EXCEPT_FLG_SFT 7
++#define ID_EXCEPT_FLG_HI 7
++#define ID_EXCEPT_FLG_SZ 1
++#define ID_FULL_MSK 0x00000001
++#define ID_FULL_I_MSK 0xfffffffe
++#define ID_FULL_SFT 0
++#define ID_FULL_HI 0
++#define ID_FULL_SZ 1
++#define ID_MNG_BUSY_MSK 0x00000002
++#define ID_MNG_BUSY_I_MSK 0xfffffffd
++#define ID_MNG_BUSY_SFT 1
++#define ID_MNG_BUSY_HI 1
++#define ID_MNG_BUSY_SZ 1
++#define REQ_LOCK_MSK 0x00000004
++#define REQ_LOCK_I_MSK 0xfffffffb
++#define REQ_LOCK_SFT 2
++#define REQ_LOCK_HI 2
++#define REQ_LOCK_SZ 1
++#define CH0_REQ_LOCK_MSK 0x00000010
++#define CH0_REQ_LOCK_I_MSK 0xffffffef
++#define CH0_REQ_LOCK_SFT 4
++#define CH0_REQ_LOCK_HI 4
++#define CH0_REQ_LOCK_SZ 1
++#define CH1_REQ_LOCK_MSK 0x00000020
++#define CH1_REQ_LOCK_I_MSK 0xffffffdf
++#define CH1_REQ_LOCK_SFT 5
++#define CH1_REQ_LOCK_HI 5
++#define CH1_REQ_LOCK_SZ 1
++#define CH2_REQ_LOCK_MSK 0x00000040
++#define CH2_REQ_LOCK_I_MSK 0xffffffbf
++#define CH2_REQ_LOCK_SFT 6
++#define CH2_REQ_LOCK_HI 6
++#define CH2_REQ_LOCK_SZ 1
++#define CH3_REQ_LOCK_MSK 0x00000080
++#define CH3_REQ_LOCK_I_MSK 0xffffff7f
++#define CH3_REQ_LOCK_SFT 7
++#define CH3_REQ_LOCK_HI 7
++#define CH3_REQ_LOCK_SZ 1
++#define REQ_LOCK_INT_EN_MSK 0x00000100
++#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff
++#define REQ_LOCK_INT_EN_SFT 8
++#define REQ_LOCK_INT_EN_HI 8
++#define REQ_LOCK_INT_EN_SZ 1
++#define REQ_LOCK_INT_MSK 0x00000200
++#define REQ_LOCK_INT_I_MSK 0xfffffdff
++#define REQ_LOCK_INT_SFT 9
++#define REQ_LOCK_INT_HI 9
++#define REQ_LOCK_INT_SZ 1
++#define MCU_ALC_READY_MSK 0x00000001
++#define MCU_ALC_READY_I_MSK 0xfffffffe
++#define MCU_ALC_READY_SFT 0
++#define MCU_ALC_READY_HI 0
++#define MCU_ALC_READY_SZ 1
++#define ALC_FAIL_MSK 0x00000002
++#define ALC_FAIL_I_MSK 0xfffffffd
++#define ALC_FAIL_SFT 1
++#define ALC_FAIL_HI 1
++#define ALC_FAIL_SZ 1
++#define ALC_BUSY_MSK 0x00000004
++#define ALC_BUSY_I_MSK 0xfffffffb
++#define ALC_BUSY_SFT 2
++#define ALC_BUSY_HI 2
++#define ALC_BUSY_SZ 1
++#define CH0_NVLD_MSK 0x00000010
++#define CH0_NVLD_I_MSK 0xffffffef
++#define CH0_NVLD_SFT 4
++#define CH0_NVLD_HI 4
++#define CH0_NVLD_SZ 1
++#define CH1_NVLD_MSK 0x00000020
++#define CH1_NVLD_I_MSK 0xffffffdf
++#define CH1_NVLD_SFT 5
++#define CH1_NVLD_HI 5
++#define CH1_NVLD_SZ 1
++#define CH2_NVLD_MSK 0x00000040
++#define CH2_NVLD_I_MSK 0xffffffbf
++#define CH2_NVLD_SFT 6
++#define CH2_NVLD_HI 6
++#define CH2_NVLD_SZ 1
++#define CH3_NVLD_MSK 0x00000080
++#define CH3_NVLD_I_MSK 0xffffff7f
++#define CH3_NVLD_SFT 7
++#define CH3_NVLD_HI 7
++#define CH3_NVLD_SZ 1
++#define ALC_INT_ID_MSK 0x00007f00
++#define ALC_INT_ID_I_MSK 0xffff80ff
++#define ALC_INT_ID_SFT 8
++#define ALC_INT_ID_HI 14
++#define ALC_INT_ID_SZ 7
++#define ALC_TIMEOUT_MSK 0x03ff0000
++#define ALC_TIMEOUT_I_MSK 0xfc00ffff
++#define ALC_TIMEOUT_SFT 16
++#define ALC_TIMEOUT_HI 25
++#define ALC_TIMEOUT_SZ 10
++#define ALC_TIMEOUT_INT_EN_MSK 0x40000000
++#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff
++#define ALC_TIMEOUT_INT_EN_SFT 30
++#define ALC_TIMEOUT_INT_EN_HI 30
++#define ALC_TIMEOUT_INT_EN_SZ 1
++#define ALC_TIMEOUT_INT_MSK 0x80000000
++#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff
++#define ALC_TIMEOUT_INT_SFT 31
++#define ALC_TIMEOUT_INT_HI 31
++#define ALC_TIMEOUT_INT_SZ 1
++#define TX_ID_COUNT_MSK 0x000000ff
++#define TX_ID_COUNT_I_MSK 0xffffff00
++#define TX_ID_COUNT_SFT 0
++#define TX_ID_COUNT_HI 7
++#define TX_ID_COUNT_SZ 8
++#define RX_ID_COUNT_MSK 0x0000ff00
++#define RX_ID_COUNT_I_MSK 0xffff00ff
++#define RX_ID_COUNT_SFT 8
++#define RX_ID_COUNT_HI 15
++#define RX_ID_COUNT_SZ 8
++#define TX_ID_THOLD_MSK 0x000000ff
++#define TX_ID_THOLD_I_MSK 0xffffff00
++#define TX_ID_THOLD_SFT 0
++#define TX_ID_THOLD_HI 7
++#define TX_ID_THOLD_SZ 8
++#define RX_ID_THOLD_MSK 0x0000ff00
++#define RX_ID_THOLD_I_MSK 0xffff00ff
++#define RX_ID_THOLD_SFT 8
++#define RX_ID_THOLD_HI 15
++#define RX_ID_THOLD_SZ 8
++#define ID_THOLD_RX_INT_MSK 0x00010000
++#define ID_THOLD_RX_INT_I_MSK 0xfffeffff
++#define ID_THOLD_RX_INT_SFT 16
++#define ID_THOLD_RX_INT_HI 16
++#define ID_THOLD_RX_INT_SZ 1
++#define RX_INT_CH_MSK 0x000e0000
++#define RX_INT_CH_I_MSK 0xfff1ffff
++#define RX_INT_CH_SFT 17
++#define RX_INT_CH_HI 19
++#define RX_INT_CH_SZ 3
++#define ID_THOLD_TX_INT_MSK 0x00100000
++#define ID_THOLD_TX_INT_I_MSK 0xffefffff
++#define ID_THOLD_TX_INT_SFT 20
++#define ID_THOLD_TX_INT_HI 20
++#define ID_THOLD_TX_INT_SZ 1
++#define TX_INT_CH_MSK 0x00e00000
++#define TX_INT_CH_I_MSK 0xff1fffff
++#define TX_INT_CH_SFT 21
++#define TX_INT_CH_HI 23
++#define TX_INT_CH_SZ 3
++#define ID_THOLD_INT_EN_MSK 0x01000000
++#define ID_THOLD_INT_EN_I_MSK 0xfeffffff
++#define ID_THOLD_INT_EN_SFT 24
++#define ID_THOLD_INT_EN_HI 24
++#define ID_THOLD_INT_EN_SZ 1
++#define TX_ID_TB0_MSK 0xffffffff
++#define TX_ID_TB0_I_MSK 0x00000000
++#define TX_ID_TB0_SFT 0
++#define TX_ID_TB0_HI 31
++#define TX_ID_TB0_SZ 32
++#define TX_ID_TB1_MSK 0xffffffff
++#define TX_ID_TB1_I_MSK 0x00000000
++#define TX_ID_TB1_SFT 0
++#define TX_ID_TB1_HI 31
++#define TX_ID_TB1_SZ 32
++#define RX_ID_TB0_MSK 0xffffffff
++#define RX_ID_TB0_I_MSK 0x00000000
++#define RX_ID_TB0_SFT 0
++#define RX_ID_TB0_HI 31
++#define RX_ID_TB0_SZ 32
++#define RX_ID_TB1_MSK 0xffffffff
++#define RX_ID_TB1_I_MSK 0x00000000
++#define RX_ID_TB1_SFT 0
++#define RX_ID_TB1_HI 31
++#define RX_ID_TB1_SZ 32
++#define DOUBLE_RLS_INT_EN_MSK 0x00000001
++#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe
++#define DOUBLE_RLS_INT_EN_SFT 0
++#define DOUBLE_RLS_INT_EN_HI 0
++#define DOUBLE_RLS_INT_EN_SZ 1
++#define ID_DOUBLE_RLS_INT_MSK 0x00000002
++#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd
++#define ID_DOUBLE_RLS_INT_SFT 1
++#define ID_DOUBLE_RLS_INT_HI 1
++#define ID_DOUBLE_RLS_INT_SZ 1
++#define DOUBLE_RLS_ID_MSK 0x00007f00
++#define DOUBLE_RLS_ID_I_MSK 0xffff80ff
++#define DOUBLE_RLS_ID_SFT 8
++#define DOUBLE_RLS_ID_HI 14
++#define DOUBLE_RLS_ID_SZ 7
++#define ID_LEN_THOLD_INT_EN_MSK 0x00000001
++#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe
++#define ID_LEN_THOLD_INT_EN_SFT 0
++#define ID_LEN_THOLD_INT_EN_HI 0
++#define ID_LEN_THOLD_INT_EN_SZ 1
++#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002
++#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd
++#define ALL_ID_LEN_THOLD_INT_SFT 1
++#define ALL_ID_LEN_THOLD_INT_HI 1
++#define ALL_ID_LEN_THOLD_INT_SZ 1
++#define TX_ID_LEN_THOLD_INT_MSK 0x00000004
++#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb
++#define TX_ID_LEN_THOLD_INT_SFT 2
++#define TX_ID_LEN_THOLD_INT_HI 2
++#define TX_ID_LEN_THOLD_INT_SZ 1
++#define RX_ID_LEN_THOLD_INT_MSK 0x00000008
++#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7
++#define RX_ID_LEN_THOLD_INT_SFT 3
++#define RX_ID_LEN_THOLD_INT_HI 3
++#define RX_ID_LEN_THOLD_INT_SZ 1
++#define ID_TX_LEN_THOLD_MSK 0x00001ff0
++#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f
++#define ID_TX_LEN_THOLD_SFT 4
++#define ID_TX_LEN_THOLD_HI 12
++#define ID_TX_LEN_THOLD_SZ 9
++#define ID_RX_LEN_THOLD_MSK 0x003fe000
++#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff
++#define ID_RX_LEN_THOLD_SFT 13
++#define ID_RX_LEN_THOLD_HI 21
++#define ID_RX_LEN_THOLD_SZ 9
++#define ID_LEN_THOLD_MSK 0x7fc00000
++#define ID_LEN_THOLD_I_MSK 0x803fffff
++#define ID_LEN_THOLD_SFT 22
++#define ID_LEN_THOLD_HI 30
++#define ID_LEN_THOLD_SZ 9
++#define ALL_ID_ALC_LEN_MSK 0x000001ff
++#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00
++#define ALL_ID_ALC_LEN_SFT 0
++#define ALL_ID_ALC_LEN_HI 8
++#define ALL_ID_ALC_LEN_SZ 9
++#define TX_ID_ALC_LEN_MSK 0x0003fe00
++#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff
++#define TX_ID_ALC_LEN_SFT 9
++#define TX_ID_ALC_LEN_HI 17
++#define TX_ID_ALC_LEN_SZ 9
++#define RX_ID_ALC_LEN_MSK 0x07fc0000
++#define RX_ID_ALC_LEN_I_MSK 0xf803ffff
++#define RX_ID_ALC_LEN_SFT 18
++#define RX_ID_ALC_LEN_HI 26
++#define RX_ID_ALC_LEN_SZ 9
++#define CH_ARB_EN_MSK 0x00000001
++#define CH_ARB_EN_I_MSK 0xfffffffe
++#define CH_ARB_EN_SFT 0
++#define CH_ARB_EN_HI 0
++#define CH_ARB_EN_SZ 1
++#define CH_PRI1_MSK 0x00000030
++#define CH_PRI1_I_MSK 0xffffffcf
++#define CH_PRI1_SFT 4
++#define CH_PRI1_HI 5
++#define CH_PRI1_SZ 2
++#define CH_PRI2_MSK 0x00000300
++#define CH_PRI2_I_MSK 0xfffffcff
++#define CH_PRI2_SFT 8
++#define CH_PRI2_HI 9
++#define CH_PRI2_SZ 2
++#define CH_PRI3_MSK 0x00003000
++#define CH_PRI3_I_MSK 0xffffcfff
++#define CH_PRI3_SFT 12
++#define CH_PRI3_HI 13
++#define CH_PRI3_SZ 2
++#define CH_PRI4_MSK 0x00030000
++#define CH_PRI4_I_MSK 0xfffcffff
++#define CH_PRI4_SFT 16
++#define CH_PRI4_HI 17
++#define CH_PRI4_SZ 2
++#define TX_ID_REMAIN_MSK 0x0000007f
++#define TX_ID_REMAIN_I_MSK 0xffffff80
++#define TX_ID_REMAIN_SFT 0
++#define TX_ID_REMAIN_HI 6
++#define TX_ID_REMAIN_SZ 7
++#define TX_PAGE_REMAIN_MSK 0x0001ff00
++#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff
++#define TX_PAGE_REMAIN_SFT 8
++#define TX_PAGE_REMAIN_HI 16
++#define TX_PAGE_REMAIN_SZ 9
++#define ID_PAGE_MAX_SIZE_MSK 0x000001ff
++#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00
++#define ID_PAGE_MAX_SIZE_SFT 0
++#define ID_PAGE_MAX_SIZE_HI 8
++#define ID_PAGE_MAX_SIZE_SZ 9
++#define TX_PAGE_LIMIT_MSK 0x000001ff
++#define TX_PAGE_LIMIT_I_MSK 0xfffffe00
++#define TX_PAGE_LIMIT_SFT 0
++#define TX_PAGE_LIMIT_HI 8
++#define TX_PAGE_LIMIT_SZ 9
++#define TX_COUNT_LIMIT_MSK 0x00ff0000
++#define TX_COUNT_LIMIT_I_MSK 0xff00ffff
++#define TX_COUNT_LIMIT_SFT 16
++#define TX_COUNT_LIMIT_HI 23
++#define TX_COUNT_LIMIT_SZ 8
++#define TX_LIMIT_INT_MSK 0x40000000
++#define TX_LIMIT_INT_I_MSK 0xbfffffff
++#define TX_LIMIT_INT_SFT 30
++#define TX_LIMIT_INT_HI 30
++#define TX_LIMIT_INT_SZ 1
++#define TX_LIMIT_INT_EN_MSK 0x80000000
++#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff
++#define TX_LIMIT_INT_EN_SFT 31
++#define TX_LIMIT_INT_EN_HI 31
++#define TX_LIMIT_INT_EN_SZ 1
++#define TX_PAGE_USE_7_0_MSK 0x000000ff
++#define TX_PAGE_USE_7_0_I_MSK 0xffffff00
++#define TX_PAGE_USE_7_0_SFT 0
++#define TX_PAGE_USE_7_0_HI 7
++#define TX_PAGE_USE_7_0_SZ 8
++#define TX_ID_USE_5_0_MSK 0x00003f00
++#define TX_ID_USE_5_0_I_MSK 0xffffc0ff
++#define TX_ID_USE_5_0_SFT 8
++#define TX_ID_USE_5_0_HI 13
++#define TX_ID_USE_5_0_SZ 6
++#define EDCA0_FFO_CNT_MSK 0x0003c000
++#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff
++#define EDCA0_FFO_CNT_SFT 14
++#define EDCA0_FFO_CNT_HI 17
++#define EDCA0_FFO_CNT_SZ 4
++#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000
++#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff
++#define EDCA1_FFO_CNT_3_0_SFT 18
++#define EDCA1_FFO_CNT_3_0_HI 21
++#define EDCA1_FFO_CNT_3_0_SZ 4
++#define EDCA2_FFO_CNT_MSK 0x07c00000
++#define EDCA2_FFO_CNT_I_MSK 0xf83fffff
++#define EDCA2_FFO_CNT_SFT 22
++#define EDCA2_FFO_CNT_HI 26
++#define EDCA2_FFO_CNT_SZ 5
++#define EDCA3_FFO_CNT_MSK 0xf8000000
++#define EDCA3_FFO_CNT_I_MSK 0x07ffffff
++#define EDCA3_FFO_CNT_SFT 27
++#define EDCA3_FFO_CNT_HI 31
++#define EDCA3_FFO_CNT_SZ 5
++#define ID_TB2_MSK 0xffffffff
++#define ID_TB2_I_MSK 0x00000000
++#define ID_TB2_SFT 0
++#define ID_TB2_HI 31
++#define ID_TB2_SZ 32
++#define ID_TB3_MSK 0xffffffff
++#define ID_TB3_I_MSK 0x00000000
++#define ID_TB3_SFT 0
++#define ID_TB3_HI 31
++#define ID_TB3_SZ 32
++#define TX_ID_TB2_MSK 0xffffffff
++#define TX_ID_TB2_I_MSK 0x00000000
++#define TX_ID_TB2_SFT 0
++#define TX_ID_TB2_HI 31
++#define TX_ID_TB2_SZ 32
++#define TX_ID_TB3_MSK 0xffffffff
++#define TX_ID_TB3_I_MSK 0x00000000
++#define TX_ID_TB3_SFT 0
++#define TX_ID_TB3_HI 31
++#define TX_ID_TB3_SZ 32
++#define RX_ID_TB2_MSK 0xffffffff
++#define RX_ID_TB2_I_MSK 0x00000000
++#define RX_ID_TB2_SFT 0
++#define RX_ID_TB2_HI 31
++#define RX_ID_TB2_SZ 32
++#define RX_ID_TB3_MSK 0xffffffff
++#define RX_ID_TB3_I_MSK 0x00000000
++#define RX_ID_TB3_SFT 0
++#define RX_ID_TB3_HI 31
++#define RX_ID_TB3_SZ 32
++#define TX_PAGE_USE2_MSK 0x000001ff
++#define TX_PAGE_USE2_I_MSK 0xfffffe00
++#define TX_PAGE_USE2_SFT 0
++#define TX_PAGE_USE2_HI 8
++#define TX_PAGE_USE2_SZ 9
++#define TX_ID_USE2_MSK 0x0001fe00
++#define TX_ID_USE2_I_MSK 0xfffe01ff
++#define TX_ID_USE2_SFT 9
++#define TX_ID_USE2_HI 16
++#define TX_ID_USE2_SZ 8
++#define EDCA4_FFO_CNT_MSK 0x001e0000
++#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff
++#define EDCA4_FFO_CNT_SFT 17
++#define EDCA4_FFO_CNT_HI 20
++#define EDCA4_FFO_CNT_SZ 4
++#define TX_PAGE_USE3_MSK 0x000001ff
++#define TX_PAGE_USE3_I_MSK 0xfffffe00
++#define TX_PAGE_USE3_SFT 0
++#define TX_PAGE_USE3_HI 8
++#define TX_PAGE_USE3_SZ 9
++#define TX_ID_USE3_MSK 0x0001fe00
++#define TX_ID_USE3_I_MSK 0xfffe01ff
++#define TX_ID_USE3_SFT 9
++#define TX_ID_USE3_HI 16
++#define TX_ID_USE3_SZ 8
++#define EDCA1_FFO_CNT2_MSK 0x03e00000
++#define EDCA1_FFO_CNT2_I_MSK 0xfc1fffff
++#define EDCA1_FFO_CNT2_SFT 21
++#define EDCA1_FFO_CNT2_HI 25
++#define EDCA1_FFO_CNT2_SZ 5
++#define EDCA4_FFO_CNT2_MSK 0x3c000000
++#define EDCA4_FFO_CNT2_I_MSK 0xc3ffffff
++#define EDCA4_FFO_CNT2_SFT 26
++#define EDCA4_FFO_CNT2_HI 29
++#define EDCA4_FFO_CNT2_SZ 4
++#define TX_PAGE_USE4_MSK 0x000001ff
++#define TX_PAGE_USE4_I_MSK 0xfffffe00
++#define TX_PAGE_USE4_SFT 0
++#define TX_PAGE_USE4_HI 8
++#define TX_PAGE_USE4_SZ 9
++#define TX_ID_USE4_MSK 0x0001fe00
++#define TX_ID_USE4_I_MSK 0xfffe01ff
++#define TX_ID_USE4_SFT 9
++#define TX_ID_USE4_HI 16
++#define TX_ID_USE4_SZ 8
++#define EDCA2_FFO_CNT2_MSK 0x003e0000
++#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff
++#define EDCA2_FFO_CNT2_SFT 17
++#define EDCA2_FFO_CNT2_HI 21
++#define EDCA2_FFO_CNT2_SZ 5
++#define EDCA3_FFO_CNT2_MSK 0x07c00000
++#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff
++#define EDCA3_FFO_CNT2_SFT 22
++#define EDCA3_FFO_CNT2_HI 26
++#define EDCA3_FFO_CNT2_SZ 5
++#define TX_ID_IFO_LEN_MSK 0x000001ff
++#define TX_ID_IFO_LEN_I_MSK 0xfffffe00
++#define TX_ID_IFO_LEN_SFT 0
++#define TX_ID_IFO_LEN_HI 8
++#define TX_ID_IFO_LEN_SZ 9
++#define RX_ID_IFO_LEN_MSK 0x01ff0000
++#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff
++#define RX_ID_IFO_LEN_SFT 16
++#define RX_ID_IFO_LEN_HI 24
++#define RX_ID_IFO_LEN_SZ 9
++#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff
++#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00
++#define MAX_ALL_ALC_ID_CNT_SFT 0
++#define MAX_ALL_ALC_ID_CNT_HI 7
++#define MAX_ALL_ALC_ID_CNT_SZ 8
++#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00
++#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff
++#define MAX_TX_ALC_ID_CNT_SFT 8
++#define MAX_TX_ALC_ID_CNT_HI 15
++#define MAX_TX_ALC_ID_CNT_SZ 8
++#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000
++#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff
++#define MAX_RX_ALC_ID_CNT_SFT 16
++#define MAX_RX_ALC_ID_CNT_HI 23
++#define MAX_RX_ALC_ID_CNT_SZ 8
++#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff
++#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00
++#define MAX_ALL_ID_ALC_LEN_SFT 0
++#define MAX_ALL_ID_ALC_LEN_HI 8
++#define MAX_ALL_ID_ALC_LEN_SZ 9
++#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00
++#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff
++#define MAX_TX_ID_ALC_LEN_SFT 9
++#define MAX_TX_ID_ALC_LEN_HI 17
++#define MAX_TX_ID_ALC_LEN_SZ 9
++#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000
++#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff
++#define MAX_RX_ID_ALC_LEN_SFT 18
++#define MAX_RX_ID_ALC_LEN_HI 26
++#define MAX_RX_ID_ALC_LEN_SZ 9
++#define RG_PMDLBK_MSK 0x00000001
++#define RG_PMDLBK_I_MSK 0xfffffffe
++#define RG_PMDLBK_SFT 0
++#define RG_PMDLBK_HI 0
++#define RG_PMDLBK_SZ 1
++#define RG_RDYACK_SEL_MSK 0x00000006
++#define RG_RDYACK_SEL_I_MSK 0xfffffff9
++#define RG_RDYACK_SEL_SFT 1
++#define RG_RDYACK_SEL_HI 2
++#define RG_RDYACK_SEL_SZ 2
++#define RG_ADEDGE_SEL_MSK 0x00000008
++#define RG_ADEDGE_SEL_I_MSK 0xfffffff7
++#define RG_ADEDGE_SEL_SFT 3
++#define RG_ADEDGE_SEL_HI 3
++#define RG_ADEDGE_SEL_SZ 1
++#define RG_SIGN_SWAP_MSK 0x00000010
++#define RG_SIGN_SWAP_I_MSK 0xffffffef
++#define RG_SIGN_SWAP_SFT 4
++#define RG_SIGN_SWAP_HI 4
++#define RG_SIGN_SWAP_SZ 1
++#define RG_IQ_SWAP_MSK 0x00000020
++#define RG_IQ_SWAP_I_MSK 0xffffffdf
++#define RG_IQ_SWAP_SFT 5
++#define RG_IQ_SWAP_HI 5
++#define RG_IQ_SWAP_SZ 1
++#define RG_Q_INV_MSK 0x00000040
++#define RG_Q_INV_I_MSK 0xffffffbf
++#define RG_Q_INV_SFT 6
++#define RG_Q_INV_HI 6
++#define RG_Q_INV_SZ 1
++#define RG_I_INV_MSK 0x00000080
++#define RG_I_INV_I_MSK 0xffffff7f
++#define RG_I_INV_SFT 7
++#define RG_I_INV_HI 7
++#define RG_I_INV_SZ 1
++#define RG_BYPASS_ACI_MSK 0x00000100
++#define RG_BYPASS_ACI_I_MSK 0xfffffeff
++#define RG_BYPASS_ACI_SFT 8
++#define RG_BYPASS_ACI_HI 8
++#define RG_BYPASS_ACI_SZ 1
++#define RG_LBK_ANA_PATH_MSK 0x00000200
++#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff
++#define RG_LBK_ANA_PATH_SFT 9
++#define RG_LBK_ANA_PATH_HI 9
++#define RG_LBK_ANA_PATH_SZ 1
++#define RG_SPECTRUM_LEAKY_FACTOR_MSK 0x00000c00
++#define RG_SPECTRUM_LEAKY_FACTOR_I_MSK 0xfffff3ff
++#define RG_SPECTRUM_LEAKY_FACTOR_SFT 10
++#define RG_SPECTRUM_LEAKY_FACTOR_HI 11
++#define RG_SPECTRUM_LEAKY_FACTOR_SZ 2
++#define RG_SPECTRUM_BW_MSK 0x00003000
++#define RG_SPECTRUM_BW_I_MSK 0xffffcfff
++#define RG_SPECTRUM_BW_SFT 12
++#define RG_SPECTRUM_BW_HI 13
++#define RG_SPECTRUM_BW_SZ 2
++#define RG_SPECTRUM_FREQ_MANUAL_MSK 0x00004000
++#define RG_SPECTRUM_FREQ_MANUAL_I_MSK 0xffffbfff
++#define RG_SPECTRUM_FREQ_MANUAL_SFT 14
++#define RG_SPECTRUM_FREQ_MANUAL_HI 14
++#define RG_SPECTRUM_FREQ_MANUAL_SZ 1
++#define RG_SPECTRUM_EN_MSK 0x00008000
++#define RG_SPECTRUM_EN_I_MSK 0xffff7fff
++#define RG_SPECTRUM_EN_SFT 15
++#define RG_SPECTRUM_EN_HI 15
++#define RG_SPECTRUM_EN_SZ 1
++#define RG_TXPWRLVL_SET_MSK 0x00ff0000
++#define RG_TXPWRLVL_SET_I_MSK 0xff00ffff
++#define RG_TXPWRLVL_SET_SFT 16
++#define RG_TXPWRLVL_SET_HI 23
++#define RG_TXPWRLVL_SET_SZ 8
++#define RG_TXPWRLVL_SEL_MSK 0x01000000
++#define RG_TXPWRLVL_SEL_I_MSK 0xfeffffff
++#define RG_TXPWRLVL_SEL_SFT 24
++#define RG_TXPWRLVL_SEL_HI 24
++#define RG_TXPWRLVL_SEL_SZ 1
++#define RG_RF_BB_CLK_SEL_MSK 0x80000000
++#define RG_RF_BB_CLK_SEL_I_MSK 0x7fffffff
++#define RG_RF_BB_CLK_SEL_SFT 31
++#define RG_RF_BB_CLK_SEL_HI 31
++#define RG_RF_BB_CLK_SEL_SZ 1
++#define RG_PHY_MD_EN_MSK 0x00000001
++#define RG_PHY_MD_EN_I_MSK 0xfffffffe
++#define RG_PHY_MD_EN_SFT 0
++#define RG_PHY_MD_EN_HI 0
++#define RG_PHY_MD_EN_SZ 1
++#define RG_PHYRX_MD_EN_MSK 0x00000002
++#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd
++#define RG_PHYRX_MD_EN_SFT 1
++#define RG_PHYRX_MD_EN_HI 1
++#define RG_PHYRX_MD_EN_SZ 1
++#define RG_PHYTX_MD_EN_MSK 0x00000004
++#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb
++#define RG_PHYTX_MD_EN_SFT 2
++#define RG_PHYTX_MD_EN_HI 2
++#define RG_PHYTX_MD_EN_SZ 1
++#define RG_PHY11GN_MD_EN_MSK 0x00000008
++#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7
++#define RG_PHY11GN_MD_EN_SFT 3
++#define RG_PHY11GN_MD_EN_HI 3
++#define RG_PHY11GN_MD_EN_SZ 1
++#define RG_PHY11B_MD_EN_MSK 0x00000010
++#define RG_PHY11B_MD_EN_I_MSK 0xffffffef
++#define RG_PHY11B_MD_EN_SFT 4
++#define RG_PHY11B_MD_EN_HI 4
++#define RG_PHY11B_MD_EN_SZ 1
++#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020
++#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf
++#define RG_PHYRXFIFO_MD_EN_SFT 5
++#define RG_PHYRXFIFO_MD_EN_HI 5
++#define RG_PHYRXFIFO_MD_EN_SZ 1
++#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040
++#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf
++#define RG_PHYTXFIFO_MD_EN_SFT 6
++#define RG_PHYTXFIFO_MD_EN_HI 6
++#define RG_PHYTXFIFO_MD_EN_SZ 1
++#define RG_PHY11BGN_MD_EN_MSK 0x00000100
++#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff
++#define RG_PHY11BGN_MD_EN_SFT 8
++#define RG_PHY11BGN_MD_EN_HI 8
++#define RG_PHY11BGN_MD_EN_SZ 1
++#define RG_FORCE_11GN_EN_MSK 0x00001000
++#define RG_FORCE_11GN_EN_I_MSK 0xffffefff
++#define RG_FORCE_11GN_EN_SFT 12
++#define RG_FORCE_11GN_EN_HI 12
++#define RG_FORCE_11GN_EN_SZ 1
++#define RG_FORCE_11B_EN_MSK 0x00002000
++#define RG_FORCE_11B_EN_I_MSK 0xffffdfff
++#define RG_FORCE_11B_EN_SFT 13
++#define RG_FORCE_11B_EN_HI 13
++#define RG_FORCE_11B_EN_SZ 1
++#define RG_FFT_MEM_CLK_EN_RX_MSK 0x00004000
++#define RG_FFT_MEM_CLK_EN_RX_I_MSK 0xffffbfff
++#define RG_FFT_MEM_CLK_EN_RX_SFT 14
++#define RG_FFT_MEM_CLK_EN_RX_HI 14
++#define RG_FFT_MEM_CLK_EN_RX_SZ 1
++#define RG_FFT_MEM_CLK_EN_TX_MSK 0x00008000
++#define RG_FFT_MEM_CLK_EN_TX_I_MSK 0xffff7fff
++#define RG_FFT_MEM_CLK_EN_TX_SFT 15
++#define RG_FFT_MEM_CLK_EN_TX_HI 15
++#define RG_FFT_MEM_CLK_EN_TX_SZ 1
++#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000
++#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff
++#define RG_PHY_IQ_TRIG_SEL_SFT 16
++#define RG_PHY_IQ_TRIG_SEL_HI 19
++#define RG_PHY_IQ_TRIG_SEL_SZ 4
++#define RG_SPECTRUM_FREQ_MSK 0x3ff00000
++#define RG_SPECTRUM_FREQ_I_MSK 0xc00fffff
++#define RG_SPECTRUM_FREQ_SFT 20
++#define RG_SPECTRUM_FREQ_HI 29
++#define RG_SPECTRUM_FREQ_SZ 10
++#define SVN_VERSION_MSK 0xffffffff
++#define SVN_VERSION_I_MSK 0x00000000
++#define SVN_VERSION_SFT 0
++#define SVN_VERSION_HI 31
++#define SVN_VERSION_SZ 32
++#define RG_LENGTH_MSK 0x0000ffff
++#define RG_LENGTH_I_MSK 0xffff0000
++#define RG_LENGTH_SFT 0
++#define RG_LENGTH_HI 15
++#define RG_LENGTH_SZ 16
++#define RG_PKT_MODE_MSK 0x00070000
++#define RG_PKT_MODE_I_MSK 0xfff8ffff
++#define RG_PKT_MODE_SFT 16
++#define RG_PKT_MODE_HI 18
++#define RG_PKT_MODE_SZ 3
++#define RG_CH_BW_MSK 0x00380000
++#define RG_CH_BW_I_MSK 0xffc7ffff
++#define RG_CH_BW_SFT 19
++#define RG_CH_BW_HI 21
++#define RG_CH_BW_SZ 3
++#define RG_PRM_MSK 0x00400000
++#define RG_PRM_I_MSK 0xffbfffff
++#define RG_PRM_SFT 22
++#define RG_PRM_HI 22
++#define RG_PRM_SZ 1
++#define RG_SHORTGI_MSK 0x00800000
++#define RG_SHORTGI_I_MSK 0xff7fffff
++#define RG_SHORTGI_SFT 23
++#define RG_SHORTGI_HI 23
++#define RG_SHORTGI_SZ 1
++#define RG_RATE_MSK 0x7f000000
++#define RG_RATE_I_MSK 0x80ffffff
++#define RG_RATE_SFT 24
++#define RG_RATE_HI 30
++#define RG_RATE_SZ 7
++#define RG_L_LENGTH_MSK 0x00000fff
++#define RG_L_LENGTH_I_MSK 0xfffff000
++#define RG_L_LENGTH_SFT 0
++#define RG_L_LENGTH_HI 11
++#define RG_L_LENGTH_SZ 12
++#define RG_L_RATE_MSK 0x00007000
++#define RG_L_RATE_I_MSK 0xffff8fff
++#define RG_L_RATE_SFT 12
++#define RG_L_RATE_HI 14
++#define RG_L_RATE_SZ 3
++#define RG_SERVICE_MSK 0xffff0000
++#define RG_SERVICE_I_MSK 0x0000ffff
++#define RG_SERVICE_SFT 16
++#define RG_SERVICE_HI 31
++#define RG_SERVICE_SZ 16
++#define RG_SMOOTHING_MSK 0x00000001
++#define RG_SMOOTHING_I_MSK 0xfffffffe
++#define RG_SMOOTHING_SFT 0
++#define RG_SMOOTHING_HI 0
++#define RG_SMOOTHING_SZ 1
++#define RG_NO_SOUND_MSK 0x00000002
++#define RG_NO_SOUND_I_MSK 0xfffffffd
++#define RG_NO_SOUND_SFT 1
++#define RG_NO_SOUND_HI 1
++#define RG_NO_SOUND_SZ 1
++#define RG_AGGREGATE_MSK 0x00000004
++#define RG_AGGREGATE_I_MSK 0xfffffffb
++#define RG_AGGREGATE_SFT 2
++#define RG_AGGREGATE_HI 2
++#define RG_AGGREGATE_SZ 1
++#define RG_STBC_MSK 0x00000018
++#define RG_STBC_I_MSK 0xffffffe7
++#define RG_STBC_SFT 3
++#define RG_STBC_HI 4
++#define RG_STBC_SZ 2
++#define RG_FEC_MSK 0x00000020
++#define RG_FEC_I_MSK 0xffffffdf
++#define RG_FEC_SFT 5
++#define RG_FEC_HI 5
++#define RG_FEC_SZ 1
++#define RG_N_ESS_MSK 0x000000c0
++#define RG_N_ESS_I_MSK 0xffffff3f
++#define RG_N_ESS_SFT 6
++#define RG_N_ESS_HI 7
++#define RG_N_ESS_SZ 2
++#define RG_TXPWRLVL_MSK 0x0000ff00
++#define RG_TXPWRLVL_I_MSK 0xffff00ff
++#define RG_TXPWRLVL_SFT 8
++#define RG_TXPWRLVL_HI 15
++#define RG_TXPWRLVL_SZ 8
++#define RG_TX_START_MSK 0x00000001
++#define RG_TX_START_I_MSK 0xfffffffe
++#define RG_TX_START_SFT 0
++#define RG_TX_START_HI 0
++#define RG_TX_START_SZ 1
++#define RG_IFS_TIME_MSK 0x000000fc
++#define RG_IFS_TIME_I_MSK 0xffffff03
++#define RG_IFS_TIME_SFT 2
++#define RG_IFS_TIME_HI 7
++#define RG_IFS_TIME_SZ 6
++#define RG_CONTINUOUS_DATA_MSK 0x00000100
++#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff
++#define RG_CONTINUOUS_DATA_SFT 8
++#define RG_CONTINUOUS_DATA_HI 8
++#define RG_CONTINUOUS_DATA_SZ 1
++#define RG_DATA_SEL_MSK 0x00000600
++#define RG_DATA_SEL_I_MSK 0xfffff9ff
++#define RG_DATA_SEL_SFT 9
++#define RG_DATA_SEL_HI 10
++#define RG_DATA_SEL_SZ 2
++#define RG_TX_D_MSK 0x00ff0000
++#define RG_TX_D_I_MSK 0xff00ffff
++#define RG_TX_D_SFT 16
++#define RG_TX_D_HI 23
++#define RG_TX_D_SZ 8
++#define RG_TX_CNT_TARGET_MSK 0xffffffff
++#define RG_TX_CNT_TARGET_I_MSK 0x00000000
++#define RG_TX_CNT_TARGET_SFT 0
++#define RG_TX_CNT_TARGET_HI 31
++#define RG_TX_CNT_TARGET_SZ 32
++#define RG_FFT_IFFT_MODE_MSK 0x000000c0
++#define RG_FFT_IFFT_MODE_I_MSK 0xffffff3f
++#define RG_FFT_IFFT_MODE_SFT 6
++#define RG_FFT_IFFT_MODE_HI 7
++#define RG_FFT_IFFT_MODE_SZ 2
++#define RG_DAC_DBG_MODE_MSK 0x00000100
++#define RG_DAC_DBG_MODE_I_MSK 0xfffffeff
++#define RG_DAC_DBG_MODE_SFT 8
++#define RG_DAC_DBG_MODE_HI 8
++#define RG_DAC_DBG_MODE_SZ 1
++#define RG_DAC_SGN_SWAP_MSK 0x00000200
++#define RG_DAC_SGN_SWAP_I_MSK 0xfffffdff
++#define RG_DAC_SGN_SWAP_SFT 9
++#define RG_DAC_SGN_SWAP_HI 9
++#define RG_DAC_SGN_SWAP_SZ 1
++#define RG_TXD_SEL_MSK 0x00000c00
++#define RG_TXD_SEL_I_MSK 0xfffff3ff
++#define RG_TXD_SEL_SFT 10
++#define RG_TXD_SEL_HI 11
++#define RG_TXD_SEL_SZ 2
++#define RG_UP8X_MSK 0x00ff0000
++#define RG_UP8X_I_MSK 0xff00ffff
++#define RG_UP8X_SFT 16
++#define RG_UP8X_HI 23
++#define RG_UP8X_SZ 8
++#define RG_IQ_DC_BYP_MSK 0x01000000
++#define RG_IQ_DC_BYP_I_MSK 0xfeffffff
++#define RG_IQ_DC_BYP_SFT 24
++#define RG_IQ_DC_BYP_HI 24
++#define RG_IQ_DC_BYP_SZ 1
++#define RG_IQ_DC_LEAKY_FACTOR_MSK 0x30000000
++#define RG_IQ_DC_LEAKY_FACTOR_I_MSK 0xcfffffff
++#define RG_IQ_DC_LEAKY_FACTOR_SFT 28
++#define RG_IQ_DC_LEAKY_FACTOR_HI 29
++#define RG_IQ_DC_LEAKY_FACTOR_SZ 2
++#define RG_DAC_DCEN_MSK 0x00000001
++#define RG_DAC_DCEN_I_MSK 0xfffffffe
++#define RG_DAC_DCEN_SFT 0
++#define RG_DAC_DCEN_HI 0
++#define RG_DAC_DCEN_SZ 1
++#define RG_DAC_DCQ_MSK 0x00003ff0
++#define RG_DAC_DCQ_I_MSK 0xffffc00f
++#define RG_DAC_DCQ_SFT 4
++#define RG_DAC_DCQ_HI 13
++#define RG_DAC_DCQ_SZ 10
++#define RG_DAC_DCI_MSK 0x03ff0000
++#define RG_DAC_DCI_I_MSK 0xfc00ffff
++#define RG_DAC_DCI_SFT 16
++#define RG_DAC_DCI_HI 25
++#define RG_DAC_DCI_SZ 10
++#define RG_PGA_REFDB_SAT_MSK 0x0000007f
++#define RG_PGA_REFDB_SAT_I_MSK 0xffffff80
++#define RG_PGA_REFDB_SAT_SFT 0
++#define RG_PGA_REFDB_SAT_HI 6
++#define RG_PGA_REFDB_SAT_SZ 7
++#define RG_PGA_REFDB_TOP_MSK 0x00007f00
++#define RG_PGA_REFDB_TOP_I_MSK 0xffff80ff
++#define RG_PGA_REFDB_TOP_SFT 8
++#define RG_PGA_REFDB_TOP_HI 14
++#define RG_PGA_REFDB_TOP_SZ 7
++#define RG_PGA_REF_UND_MSK 0x03ff0000
++#define RG_PGA_REF_UND_I_MSK 0xfc00ffff
++#define RG_PGA_REF_UND_SFT 16
++#define RG_PGA_REF_UND_HI 25
++#define RG_PGA_REF_UND_SZ 10
++#define RG_RF_REF_SAT_MSK 0xf0000000
++#define RG_RF_REF_SAT_I_MSK 0x0fffffff
++#define RG_RF_REF_SAT_SFT 28
++#define RG_RF_REF_SAT_HI 31
++#define RG_RF_REF_SAT_SZ 4
++#define RG_PGAGC_SET_MSK 0x0000000f
++#define RG_PGAGC_SET_I_MSK 0xfffffff0
++#define RG_PGAGC_SET_SFT 0
++#define RG_PGAGC_SET_HI 3
++#define RG_PGAGC_SET_SZ 4
++#define RG_PGAGC_OW_MSK 0x00000010
++#define RG_PGAGC_OW_I_MSK 0xffffffef
++#define RG_PGAGC_OW_SFT 4
++#define RG_PGAGC_OW_HI 4
++#define RG_PGAGC_OW_SZ 1
++#define RG_RFGC_SET_MSK 0x00000060
++#define RG_RFGC_SET_I_MSK 0xffffff9f
++#define RG_RFGC_SET_SFT 5
++#define RG_RFGC_SET_HI 6
++#define RG_RFGC_SET_SZ 2
++#define RG_RFGC_OW_MSK 0x00000080
++#define RG_RFGC_OW_I_MSK 0xffffff7f
++#define RG_RFGC_OW_SFT 7
++#define RG_RFGC_OW_HI 7
++#define RG_RFGC_OW_SZ 1
++#define RG_WAIT_T_RXAGC_MSK 0x00003f00
++#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff
++#define RG_WAIT_T_RXAGC_SFT 8
++#define RG_WAIT_T_RXAGC_HI 13
++#define RG_WAIT_T_RXAGC_SZ 6
++#define RG_RXAGC_SET_MSK 0x00004000
++#define RG_RXAGC_SET_I_MSK 0xffffbfff
++#define RG_RXAGC_SET_SFT 14
++#define RG_RXAGC_SET_HI 14
++#define RG_RXAGC_SET_SZ 1
++#define RG_RXAGC_OW_MSK 0x00008000
++#define RG_RXAGC_OW_I_MSK 0xffff7fff
++#define RG_RXAGC_OW_SFT 15
++#define RG_RXAGC_OW_HI 15
++#define RG_RXAGC_OW_SZ 1
++#define RG_WAIT_T_FINAL_MSK 0x003f0000
++#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff
++#define RG_WAIT_T_FINAL_SFT 16
++#define RG_WAIT_T_FINAL_HI 21
++#define RG_WAIT_T_FINAL_SZ 6
++#define RG_WAIT_T_MSK 0x3f000000
++#define RG_WAIT_T_I_MSK 0xc0ffffff
++#define RG_WAIT_T_SFT 24
++#define RG_WAIT_T_HI 29
++#define RG_WAIT_T_SZ 6
++#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f
++#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0
++#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0
++#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3
++#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4
++#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0
++#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f
++#define RG_LG_PGA_UND_PGA_GAIN_SFT 4
++#define RG_LG_PGA_UND_PGA_GAIN_HI 7
++#define RG_LG_PGA_UND_PGA_GAIN_SZ 4
++#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00
++#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff
++#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8
++#define RG_LG_PGA_SAT_PGA_GAIN_HI 11
++#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4
++#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000
++#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff
++#define RG_LG_RF_SAT_PGA_GAIN_SFT 12
++#define RG_LG_RF_SAT_PGA_GAIN_HI 15
++#define RG_LG_RF_SAT_PGA_GAIN_SZ 4
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4
++#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000
++#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff
++#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20
++#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23
++#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4
++#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000
++#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff
++#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24
++#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27
++#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4
++#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000
++#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff
++#define RG_HG_RF_SAT_PGA_GAIN_SFT 28
++#define RG_HG_RF_SAT_PGA_GAIN_HI 31
++#define RG_HG_RF_SAT_PGA_GAIN_SZ 4
++#define RG_MG_PGA_JB_TH_MSK 0x0000000f
++#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0
++#define RG_MG_PGA_JB_TH_SFT 0
++#define RG_MG_PGA_JB_TH_HI 3
++#define RG_MG_PGA_JB_TH_SZ 4
++#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000
++#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff
++#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16
++#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20
++#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5
++#define RG_WR_RFGC_INIT_SET_MSK 0x00600000
++#define RG_WR_RFGC_INIT_SET_I_MSK 0xff9fffff
++#define RG_WR_RFGC_INIT_SET_SFT 21
++#define RG_WR_RFGC_INIT_SET_HI 22
++#define RG_WR_RFGC_INIT_SET_SZ 2
++#define RG_WR_RFGC_INIT_EN_MSK 0x00800000
++#define RG_WR_RFGC_INIT_EN_I_MSK 0xff7fffff
++#define RG_WR_RFGC_INIT_EN_SFT 23
++#define RG_WR_RFGC_INIT_EN_HI 23
++#define RG_WR_RFGC_INIT_EN_SZ 1
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5
++#define RG_AGC_THRESHOLD_MSK 0x00003fff
++#define RG_AGC_THRESHOLD_I_MSK 0xffffc000
++#define RG_AGC_THRESHOLD_SFT 0
++#define RG_AGC_THRESHOLD_HI 13
++#define RG_AGC_THRESHOLD_SZ 14
++#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000
++#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff
++#define RG_ACI_POINT_CNT_LMT_11B_SFT 16
++#define RG_ACI_POINT_CNT_LMT_11B_HI 22
++#define RG_ACI_POINT_CNT_LMT_11B_SZ 7
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2
++#define RG_WR_ACI_GAIN_INI_SEL_11B_MSK 0x000000ff
++#define RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK 0xffffff00
++#define RG_WR_ACI_GAIN_INI_SEL_11B_SFT 0
++#define RG_WR_ACI_GAIN_INI_SEL_11B_HI 7
++#define RG_WR_ACI_GAIN_INI_SEL_11B_SZ 8
++#define RG_WR_ACI_GAIN_SEL_11B_MSK 0x0000ff00
++#define RG_WR_ACI_GAIN_SEL_11B_I_MSK 0xffff00ff
++#define RG_WR_ACI_GAIN_SEL_11B_SFT 8
++#define RG_WR_ACI_GAIN_SEL_11B_HI 15
++#define RG_WR_ACI_GAIN_SEL_11B_SZ 8
++#define RG_ACI_DAGC_SET_VALUE_11B_MSK 0x007f0000
++#define RG_ACI_DAGC_SET_VALUE_11B_I_MSK 0xff80ffff
++#define RG_ACI_DAGC_SET_VALUE_11B_SFT 16
++#define RG_ACI_DAGC_SET_VALUE_11B_HI 22
++#define RG_ACI_DAGC_SET_VALUE_11B_SZ 7
++#define RG_WR_ACI_GAIN_OW_11B_MSK 0x80000000
++#define RG_WR_ACI_GAIN_OW_11B_I_MSK 0x7fffffff
++#define RG_WR_ACI_GAIN_OW_11B_SFT 31
++#define RG_WR_ACI_GAIN_OW_11B_HI 31
++#define RG_WR_ACI_GAIN_OW_11B_SZ 1
++#define RG_ACI_POINT_CNT_LMT_11GN_MSK 0x000000ff
++#define RG_ACI_POINT_CNT_LMT_11GN_I_MSK 0xffffff00
++#define RG_ACI_POINT_CNT_LMT_11GN_SFT 0
++#define RG_ACI_POINT_CNT_LMT_11GN_HI 7
++#define RG_ACI_POINT_CNT_LMT_11GN_SZ 8
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK 0x00000300
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK 0xfffffcff
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT 8
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI 9
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ 2
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8
++#define RG_ACI_DAGC_SET_VALUE_11GN_MSK 0x0000007f
++#define RG_ACI_DAGC_SET_VALUE_11GN_I_MSK 0xffffff80
++#define RG_ACI_DAGC_SET_VALUE_11GN_SFT 0
++#define RG_ACI_DAGC_SET_VALUE_11GN_HI 6
++#define RG_ACI_DAGC_SET_VALUE_11GN_SZ 7
++#define RG_ACI_GAIN_INI_VAL_11GN_MSK 0x0000ff00
++#define RG_ACI_GAIN_INI_VAL_11GN_I_MSK 0xffff00ff
++#define RG_ACI_GAIN_INI_VAL_11GN_SFT 8
++#define RG_ACI_GAIN_INI_VAL_11GN_HI 15
++#define RG_ACI_GAIN_INI_VAL_11GN_SZ 8
++#define RG_ACI_GAIN_OW_VAL_11GN_MSK 0x00ff0000
++#define RG_ACI_GAIN_OW_VAL_11GN_I_MSK 0xff00ffff
++#define RG_ACI_GAIN_OW_VAL_11GN_SFT 16
++#define RG_ACI_GAIN_OW_VAL_11GN_HI 23
++#define RG_ACI_GAIN_OW_VAL_11GN_SZ 8
++#define RG_ACI_GAIN_OW_11GN_MSK 0x80000000
++#define RG_ACI_GAIN_OW_11GN_I_MSK 0x7fffffff
++#define RG_ACI_GAIN_OW_11GN_SFT 31
++#define RG_ACI_GAIN_OW_11GN_HI 31
++#define RG_ACI_GAIN_OW_11GN_SZ 1
++#define RO_CCA_PWR_MA_11GN_MSK 0x0000007f
++#define RO_CCA_PWR_MA_11GN_I_MSK 0xffffff80
++#define RO_CCA_PWR_MA_11GN_SFT 0
++#define RO_CCA_PWR_MA_11GN_HI 6
++#define RO_CCA_PWR_MA_11GN_SZ 7
++#define RO_ED_STATE_MSK 0x00008000
++#define RO_ED_STATE_I_MSK 0xffff7fff
++#define RO_ED_STATE_SFT 15
++#define RO_ED_STATE_HI 15
++#define RO_ED_STATE_SZ 1
++#define RO_CCA_PWR_MA_11B_MSK 0x007f0000
++#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff
++#define RO_CCA_PWR_MA_11B_SFT 16
++#define RO_CCA_PWR_MA_11B_HI 22
++#define RO_CCA_PWR_MA_11B_SZ 7
++#define RO_PGA_PWR_FF1_MSK 0x00003fff
++#define RO_PGA_PWR_FF1_I_MSK 0xffffc000
++#define RO_PGA_PWR_FF1_SFT 0
++#define RO_PGA_PWR_FF1_HI 13
++#define RO_PGA_PWR_FF1_SZ 14
++#define RO_RF_PWR_FF1_MSK 0x000f0000
++#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff
++#define RO_RF_PWR_FF1_SFT 16
++#define RO_RF_PWR_FF1_HI 19
++#define RO_RF_PWR_FF1_SZ 4
++#define RO_PGAGC_FF1_MSK 0x0f000000
++#define RO_PGAGC_FF1_I_MSK 0xf0ffffff
++#define RO_PGAGC_FF1_SFT 24
++#define RO_PGAGC_FF1_HI 27
++#define RO_PGAGC_FF1_SZ 4
++#define RO_RFGC_FF1_MSK 0x30000000
++#define RO_RFGC_FF1_I_MSK 0xcfffffff
++#define RO_RFGC_FF1_SFT 28
++#define RO_RFGC_FF1_HI 29
++#define RO_RFGC_FF1_SZ 2
++#define RO_PGA_PWR_FF2_MSK 0x00003fff
++#define RO_PGA_PWR_FF2_I_MSK 0xffffc000
++#define RO_PGA_PWR_FF2_SFT 0
++#define RO_PGA_PWR_FF2_HI 13
++#define RO_PGA_PWR_FF2_SZ 14
++#define RO_RF_PWR_FF2_MSK 0x000f0000
++#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff
++#define RO_RF_PWR_FF2_SFT 16
++#define RO_RF_PWR_FF2_HI 19
++#define RO_RF_PWR_FF2_SZ 4
++#define RO_PGAGC_FF2_MSK 0x0f000000
++#define RO_PGAGC_FF2_I_MSK 0xf0ffffff
++#define RO_PGAGC_FF2_SFT 24
++#define RO_PGAGC_FF2_HI 27
++#define RO_PGAGC_FF2_SZ 4
++#define RO_RFGC_FF2_MSK 0x30000000
++#define RO_RFGC_FF2_I_MSK 0xcfffffff
++#define RO_RFGC_FF2_SFT 28
++#define RO_RFGC_FF2_HI 29
++#define RO_RFGC_FF2_SZ 2
++#define RO_PGA_PWR_FF3_MSK 0x00003fff
++#define RO_PGA_PWR_FF3_I_MSK 0xffffc000
++#define RO_PGA_PWR_FF3_SFT 0
++#define RO_PGA_PWR_FF3_HI 13
++#define RO_PGA_PWR_FF3_SZ 14
++#define RO_RF_PWR_FF3_MSK 0x000f0000
++#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff
++#define RO_RF_PWR_FF3_SFT 16
++#define RO_RF_PWR_FF3_HI 19
++#define RO_RF_PWR_FF3_SZ 4
++#define RO_PGAGC_FF3_MSK 0x0f000000
++#define RO_PGAGC_FF3_I_MSK 0xf0ffffff
++#define RO_PGAGC_FF3_SFT 24
++#define RO_PGAGC_FF3_HI 27
++#define RO_PGAGC_FF3_SZ 4
++#define RO_RFGC_FF3_MSK 0x30000000
++#define RO_RFGC_FF3_I_MSK 0xcfffffff
++#define RO_RFGC_FF3_SFT 28
++#define RO_RFGC_FF3_HI 29
++#define RO_RFGC_FF3_SZ 2
++#define RG_TX_DES_RATE_MSK 0x0000001f
++#define RG_TX_DES_RATE_I_MSK 0xffffffe0
++#define RG_TX_DES_RATE_SFT 0
++#define RG_TX_DES_RATE_HI 4
++#define RG_TX_DES_RATE_SZ 5
++#define RG_TX_DES_MODE_MSK 0x00001f00
++#define RG_TX_DES_MODE_I_MSK 0xffffe0ff
++#define RG_TX_DES_MODE_SFT 8
++#define RG_TX_DES_MODE_HI 12
++#define RG_TX_DES_MODE_SZ 5
++#define RG_TX_DES_LEN_LO_MSK 0x001f0000
++#define RG_TX_DES_LEN_LO_I_MSK 0xffe0ffff
++#define RG_TX_DES_LEN_LO_SFT 16
++#define RG_TX_DES_LEN_LO_HI 20
++#define RG_TX_DES_LEN_LO_SZ 5
++#define RG_TX_DES_LEN_UP_MSK 0x1f000000
++#define RG_TX_DES_LEN_UP_I_MSK 0xe0ffffff
++#define RG_TX_DES_LEN_UP_SFT 24
++#define RG_TX_DES_LEN_UP_HI 28
++#define RG_TX_DES_LEN_UP_SZ 5
++#define RG_TX_DES_SRVC_UP_MSK 0x0000001f
++#define RG_TX_DES_SRVC_UP_I_MSK 0xffffffe0
++#define RG_TX_DES_SRVC_UP_SFT 0
++#define RG_TX_DES_SRVC_UP_HI 4
++#define RG_TX_DES_SRVC_UP_SZ 5
++#define RG_TX_DES_L_LEN_LO_MSK 0x00001f00
++#define RG_TX_DES_L_LEN_LO_I_MSK 0xffffe0ff
++#define RG_TX_DES_L_LEN_LO_SFT 8
++#define RG_TX_DES_L_LEN_LO_HI 12
++#define RG_TX_DES_L_LEN_LO_SZ 5
++#define RG_TX_DES_L_LEN_UP_MSK 0x001f0000
++#define RG_TX_DES_L_LEN_UP_I_MSK 0xffe0ffff
++#define RG_TX_DES_L_LEN_UP_SFT 16
++#define RG_TX_DES_L_LEN_UP_HI 20
++#define RG_TX_DES_L_LEN_UP_SZ 5
++#define RG_TX_DES_TYPE_MSK 0x1f000000
++#define RG_TX_DES_TYPE_I_MSK 0xe0ffffff
++#define RG_TX_DES_TYPE_SFT 24
++#define RG_TX_DES_TYPE_HI 28
++#define RG_TX_DES_TYPE_SZ 5
++#define RG_TX_DES_L_LEN_UP_COMB_MSK 0x00000001
++#define RG_TX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
++#define RG_TX_DES_L_LEN_UP_COMB_SFT 0
++#define RG_TX_DES_L_LEN_UP_COMB_HI 0
++#define RG_TX_DES_L_LEN_UP_COMB_SZ 1
++#define RG_TX_DES_TYPE_COMB_MSK 0x00000010
++#define RG_TX_DES_TYPE_COMB_I_MSK 0xffffffef
++#define RG_TX_DES_TYPE_COMB_SFT 4
++#define RG_TX_DES_TYPE_COMB_HI 4
++#define RG_TX_DES_TYPE_COMB_SZ 1
++#define RG_TX_DES_RATE_COMB_MSK 0x00000100
++#define RG_TX_DES_RATE_COMB_I_MSK 0xfffffeff
++#define RG_TX_DES_RATE_COMB_SFT 8
++#define RG_TX_DES_RATE_COMB_HI 8
++#define RG_TX_DES_RATE_COMB_SZ 1
++#define RG_TX_DES_MODE_COMB_MSK 0x00001000
++#define RG_TX_DES_MODE_COMB_I_MSK 0xffffefff
++#define RG_TX_DES_MODE_COMB_SFT 12
++#define RG_TX_DES_MODE_COMB_HI 12
++#define RG_TX_DES_MODE_COMB_SZ 1
++#define RG_TX_DES_PWRLVL_MSK 0x001f0000
++#define RG_TX_DES_PWRLVL_I_MSK 0xffe0ffff
++#define RG_TX_DES_PWRLVL_SFT 16
++#define RG_TX_DES_PWRLVL_HI 20
++#define RG_TX_DES_PWRLVL_SZ 5
++#define RG_TX_DES_SRVC_LO_MSK 0x1f000000
++#define RG_TX_DES_SRVC_LO_I_MSK 0xe0ffffff
++#define RG_TX_DES_SRVC_LO_SFT 24
++#define RG_TX_DES_SRVC_LO_HI 28
++#define RG_TX_DES_SRVC_LO_SZ 5
++#define RG_RX_DES_RATE_MSK 0x0000003f
++#define RG_RX_DES_RATE_I_MSK 0xffffffc0
++#define RG_RX_DES_RATE_SFT 0
++#define RG_RX_DES_RATE_HI 5
++#define RG_RX_DES_RATE_SZ 6
++#define RG_RX_DES_MODE_MSK 0x00003f00
++#define RG_RX_DES_MODE_I_MSK 0xffffc0ff
++#define RG_RX_DES_MODE_SFT 8
++#define RG_RX_DES_MODE_HI 13
++#define RG_RX_DES_MODE_SZ 6
++#define RG_RX_DES_LEN_LO_MSK 0x003f0000
++#define RG_RX_DES_LEN_LO_I_MSK 0xffc0ffff
++#define RG_RX_DES_LEN_LO_SFT 16
++#define RG_RX_DES_LEN_LO_HI 21
++#define RG_RX_DES_LEN_LO_SZ 6
++#define RG_RX_DES_LEN_UP_MSK 0x3f000000
++#define RG_RX_DES_LEN_UP_I_MSK 0xc0ffffff
++#define RG_RX_DES_LEN_UP_SFT 24
++#define RG_RX_DES_LEN_UP_HI 29
++#define RG_RX_DES_LEN_UP_SZ 6
++#define RG_RX_DES_SRVC_UP_MSK 0x0000003f
++#define RG_RX_DES_SRVC_UP_I_MSK 0xffffffc0
++#define RG_RX_DES_SRVC_UP_SFT 0
++#define RG_RX_DES_SRVC_UP_HI 5
++#define RG_RX_DES_SRVC_UP_SZ 6
++#define RG_RX_DES_L_LEN_LO_MSK 0x00003f00
++#define RG_RX_DES_L_LEN_LO_I_MSK 0xffffc0ff
++#define RG_RX_DES_L_LEN_LO_SFT 8
++#define RG_RX_DES_L_LEN_LO_HI 13
++#define RG_RX_DES_L_LEN_LO_SZ 6
++#define RG_RX_DES_L_LEN_UP_MSK 0x003f0000
++#define RG_RX_DES_L_LEN_UP_I_MSK 0xffc0ffff
++#define RG_RX_DES_L_LEN_UP_SFT 16
++#define RG_RX_DES_L_LEN_UP_HI 21
++#define RG_RX_DES_L_LEN_UP_SZ 6
++#define RG_RX_DES_TYPE_MSK 0x3f000000
++#define RG_RX_DES_TYPE_I_MSK 0xc0ffffff
++#define RG_RX_DES_TYPE_SFT 24
++#define RG_RX_DES_TYPE_HI 29
++#define RG_RX_DES_TYPE_SZ 6
++#define RG_RX_DES_L_LEN_UP_COMB_MSK 0x00000001
++#define RG_RX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
++#define RG_RX_DES_L_LEN_UP_COMB_SFT 0
++#define RG_RX_DES_L_LEN_UP_COMB_HI 0
++#define RG_RX_DES_L_LEN_UP_COMB_SZ 1
++#define RG_RX_DES_TYPE_COMB_MSK 0x00000010
++#define RG_RX_DES_TYPE_COMB_I_MSK 0xffffffef
++#define RG_RX_DES_TYPE_COMB_SFT 4
++#define RG_RX_DES_TYPE_COMB_HI 4
++#define RG_RX_DES_TYPE_COMB_SZ 1
++#define RG_RX_DES_RATE_COMB_MSK 0x00000100
++#define RG_RX_DES_RATE_COMB_I_MSK 0xfffffeff
++#define RG_RX_DES_RATE_COMB_SFT 8
++#define RG_RX_DES_RATE_COMB_HI 8
++#define RG_RX_DES_RATE_COMB_SZ 1
++#define RG_RX_DES_MODE_COMB_MSK 0x00001000
++#define RG_RX_DES_MODE_COMB_I_MSK 0xffffefff
++#define RG_RX_DES_MODE_COMB_SFT 12
++#define RG_RX_DES_MODE_COMB_HI 12
++#define RG_RX_DES_MODE_COMB_SZ 1
++#define RG_RX_DES_SNR_MSK 0x000f0000
++#define RG_RX_DES_SNR_I_MSK 0xfff0ffff
++#define RG_RX_DES_SNR_SFT 16
++#define RG_RX_DES_SNR_HI 19
++#define RG_RX_DES_SNR_SZ 4
++#define RG_RX_DES_RCPI_MSK 0x00f00000
++#define RG_RX_DES_RCPI_I_MSK 0xff0fffff
++#define RG_RX_DES_RCPI_SFT 20
++#define RG_RX_DES_RCPI_HI 23
++#define RG_RX_DES_RCPI_SZ 4
++#define RG_RX_DES_SRVC_LO_MSK 0x3f000000
++#define RG_RX_DES_SRVC_LO_I_MSK 0xc0ffffff
++#define RG_RX_DES_SRVC_LO_SFT 24
++#define RG_RX_DES_SRVC_LO_HI 29
++#define RG_RX_DES_SRVC_LO_SZ 6
++#define RO_TX_DES_EXCP_RATE_CNT_MSK 0x000000ff
++#define RO_TX_DES_EXCP_RATE_CNT_I_MSK 0xffffff00
++#define RO_TX_DES_EXCP_RATE_CNT_SFT 0
++#define RO_TX_DES_EXCP_RATE_CNT_HI 7
++#define RO_TX_DES_EXCP_RATE_CNT_SZ 8
++#define RO_TX_DES_EXCP_CH_BW_CNT_MSK 0x0000ff00
++#define RO_TX_DES_EXCP_CH_BW_CNT_I_MSK 0xffff00ff
++#define RO_TX_DES_EXCP_CH_BW_CNT_SFT 8
++#define RO_TX_DES_EXCP_CH_BW_CNT_HI 15
++#define RO_TX_DES_EXCP_CH_BW_CNT_SZ 8
++#define RO_TX_DES_EXCP_MODE_CNT_MSK 0x00ff0000
++#define RO_TX_DES_EXCP_MODE_CNT_I_MSK 0xff00ffff
++#define RO_TX_DES_EXCP_MODE_CNT_SFT 16
++#define RO_TX_DES_EXCP_MODE_CNT_HI 23
++#define RO_TX_DES_EXCP_MODE_CNT_SZ 8
++#define RG_TX_DES_EXCP_RATE_DEFAULT_MSK 0x07000000
++#define RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK 0xf8ffffff
++#define RG_TX_DES_EXCP_RATE_DEFAULT_SFT 24
++#define RG_TX_DES_EXCP_RATE_DEFAULT_HI 26
++#define RG_TX_DES_EXCP_RATE_DEFAULT_SZ 3
++#define RG_TX_DES_EXCP_MODE_DEFAULT_MSK 0x70000000
++#define RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK 0x8fffffff
++#define RG_TX_DES_EXCP_MODE_DEFAULT_SFT 28
++#define RG_TX_DES_EXCP_MODE_DEFAULT_HI 30
++#define RG_TX_DES_EXCP_MODE_DEFAULT_SZ 3
++#define RG_TX_DES_EXCP_CLR_MSK 0x80000000
++#define RG_TX_DES_EXCP_CLR_I_MSK 0x7fffffff
++#define RG_TX_DES_EXCP_CLR_SFT 31
++#define RG_TX_DES_EXCP_CLR_HI 31
++#define RG_TX_DES_EXCP_CLR_SZ 1
++#define RG_TX_DES_ACK_WIDTH_MSK 0x00000001
++#define RG_TX_DES_ACK_WIDTH_I_MSK 0xfffffffe
++#define RG_TX_DES_ACK_WIDTH_SFT 0
++#define RG_TX_DES_ACK_WIDTH_HI 0
++#define RG_TX_DES_ACK_WIDTH_SZ 1
++#define RG_TX_DES_ACK_PRD_MSK 0x0000000e
++#define RG_TX_DES_ACK_PRD_I_MSK 0xfffffff1
++#define RG_TX_DES_ACK_PRD_SFT 1
++#define RG_TX_DES_ACK_PRD_HI 3
++#define RG_TX_DES_ACK_PRD_SZ 3
++#define RG_RX_DES_SNR_GN_MSK 0x003f0000
++#define RG_RX_DES_SNR_GN_I_MSK 0xffc0ffff
++#define RG_RX_DES_SNR_GN_SFT 16
++#define RG_RX_DES_SNR_GN_HI 21
++#define RG_RX_DES_SNR_GN_SZ 6
++#define RG_RX_DES_RCPI_GN_MSK 0x3f000000
++#define RG_RX_DES_RCPI_GN_I_MSK 0xc0ffffff
++#define RG_RX_DES_RCPI_GN_SFT 24
++#define RG_RX_DES_RCPI_GN_HI 29
++#define RG_RX_DES_RCPI_GN_SZ 6
++#define RG_TST_TBUS_SEL_MSK 0x0000000f
++#define RG_TST_TBUS_SEL_I_MSK 0xfffffff0
++#define RG_TST_TBUS_SEL_SFT 0
++#define RG_TST_TBUS_SEL_HI 3
++#define RG_TST_TBUS_SEL_SZ 4
++#define RG_RSSI_OFFSET_MSK 0x00ff0000
++#define RG_RSSI_OFFSET_I_MSK 0xff00ffff
++#define RG_RSSI_OFFSET_SFT 16
++#define RG_RSSI_OFFSET_HI 23
++#define RG_RSSI_OFFSET_SZ 8
++#define RG_RSSI_INV_MSK 0x01000000
++#define RG_RSSI_INV_I_MSK 0xfeffffff
++#define RG_RSSI_INV_SFT 24
++#define RG_RSSI_INV_HI 24
++#define RG_RSSI_INV_SZ 1
++#define RG_TST_ADC_ON_MSK 0x40000000
++#define RG_TST_ADC_ON_I_MSK 0xbfffffff
++#define RG_TST_ADC_ON_SFT 30
++#define RG_TST_ADC_ON_HI 30
++#define RG_TST_ADC_ON_SZ 1
++#define RG_TST_EXT_GAIN_MSK 0x80000000
++#define RG_TST_EXT_GAIN_I_MSK 0x7fffffff
++#define RG_TST_EXT_GAIN_SFT 31
++#define RG_TST_EXT_GAIN_HI 31
++#define RG_TST_EXT_GAIN_SZ 1
++#define RG_DAC_Q_SET_MSK 0x000003ff
++#define RG_DAC_Q_SET_I_MSK 0xfffffc00
++#define RG_DAC_Q_SET_SFT 0
++#define RG_DAC_Q_SET_HI 9
++#define RG_DAC_Q_SET_SZ 10
++#define RG_DAC_I_SET_MSK 0x003ff000
++#define RG_DAC_I_SET_I_MSK 0xffc00fff
++#define RG_DAC_I_SET_SFT 12
++#define RG_DAC_I_SET_HI 21
++#define RG_DAC_I_SET_SZ 10
++#define RG_DAC_EN_MAN_MSK 0x10000000
++#define RG_DAC_EN_MAN_I_MSK 0xefffffff
++#define RG_DAC_EN_MAN_SFT 28
++#define RG_DAC_EN_MAN_HI 28
++#define RG_DAC_EN_MAN_SZ 1
++#define RG_IQC_FFT_EN_MSK 0x20000000
++#define RG_IQC_FFT_EN_I_MSK 0xdfffffff
++#define RG_IQC_FFT_EN_SFT 29
++#define RG_IQC_FFT_EN_HI 29
++#define RG_IQC_FFT_EN_SZ 1
++#define RG_DAC_MAN_Q_EN_MSK 0x40000000
++#define RG_DAC_MAN_Q_EN_I_MSK 0xbfffffff
++#define RG_DAC_MAN_Q_EN_SFT 30
++#define RG_DAC_MAN_Q_EN_HI 30
++#define RG_DAC_MAN_Q_EN_SZ 1
++#define RG_DAC_MAN_I_EN_MSK 0x80000000
++#define RG_DAC_MAN_I_EN_I_MSK 0x7fffffff
++#define RG_DAC_MAN_I_EN_SFT 31
++#define RG_DAC_MAN_I_EN_HI 31
++#define RG_DAC_MAN_I_EN_SZ 1
++#define RO_MRX_EN_CNT_MSK 0x0000ffff
++#define RO_MRX_EN_CNT_I_MSK 0xffff0000
++#define RO_MRX_EN_CNT_SFT 0
++#define RO_MRX_EN_CNT_HI 15
++#define RO_MRX_EN_CNT_SZ 16
++#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000
++#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff
++#define RG_MRX_EN_CNT_RST_N_SFT 31
++#define RG_MRX_EN_CNT_RST_N_HI 31
++#define RG_MRX_EN_CNT_RST_N_SZ 1
++#define RG_PA_RISE_TIME_MSK 0x000000ff
++#define RG_PA_RISE_TIME_I_MSK 0xffffff00
++#define RG_PA_RISE_TIME_SFT 0
++#define RG_PA_RISE_TIME_HI 7
++#define RG_PA_RISE_TIME_SZ 8
++#define RG_RFTX_RISE_TIME_MSK 0x0000ff00
++#define RG_RFTX_RISE_TIME_I_MSK 0xffff00ff
++#define RG_RFTX_RISE_TIME_SFT 8
++#define RG_RFTX_RISE_TIME_HI 15
++#define RG_RFTX_RISE_TIME_SZ 8
++#define RG_DAC_RISE_TIME_MSK 0x00ff0000
++#define RG_DAC_RISE_TIME_I_MSK 0xff00ffff
++#define RG_DAC_RISE_TIME_SFT 16
++#define RG_DAC_RISE_TIME_HI 23
++#define RG_DAC_RISE_TIME_SZ 8
++#define RG_SW_RISE_TIME_MSK 0xff000000
++#define RG_SW_RISE_TIME_I_MSK 0x00ffffff
++#define RG_SW_RISE_TIME_SFT 24
++#define RG_SW_RISE_TIME_HI 31
++#define RG_SW_RISE_TIME_SZ 8
++#define RG_PA_FALL_TIME_MSK 0x000000ff
++#define RG_PA_FALL_TIME_I_MSK 0xffffff00
++#define RG_PA_FALL_TIME_SFT 0
++#define RG_PA_FALL_TIME_HI 7
++#define RG_PA_FALL_TIME_SZ 8
++#define RG_RFTX_FALL_TIME_MSK 0x0000ff00
++#define RG_RFTX_FALL_TIME_I_MSK 0xffff00ff
++#define RG_RFTX_FALL_TIME_SFT 8
++#define RG_RFTX_FALL_TIME_HI 15
++#define RG_RFTX_FALL_TIME_SZ 8
++#define RG_DAC_FALL_TIME_MSK 0x00ff0000
++#define RG_DAC_FALL_TIME_I_MSK 0xff00ffff
++#define RG_DAC_FALL_TIME_SFT 16
++#define RG_DAC_FALL_TIME_HI 23
++#define RG_DAC_FALL_TIME_SZ 8
++#define RG_SW_FALL_TIME_MSK 0xff000000
++#define RG_SW_FALL_TIME_I_MSK 0x00ffffff
++#define RG_SW_FALL_TIME_SFT 24
++#define RG_SW_FALL_TIME_HI 31
++#define RG_SW_FALL_TIME_SZ 8
++#define RG_ANT_SW_0_MSK 0x00000007
++#define RG_ANT_SW_0_I_MSK 0xfffffff8
++#define RG_ANT_SW_0_SFT 0
++#define RG_ANT_SW_0_HI 2
++#define RG_ANT_SW_0_SZ 3
++#define RG_ANT_SW_1_MSK 0x00000038
++#define RG_ANT_SW_1_I_MSK 0xffffffc7
++#define RG_ANT_SW_1_SFT 3
++#define RG_ANT_SW_1_HI 5
++#define RG_ANT_SW_1_SZ 3
++#define RG_MTX_LEN_LOWER_TH_0_MSK 0x00001fff
++#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffffe000
++#define RG_MTX_LEN_LOWER_TH_0_SFT 0
++#define RG_MTX_LEN_LOWER_TH_0_HI 12
++#define RG_MTX_LEN_LOWER_TH_0_SZ 13
++#define RG_MTX_LEN_UPPER_TH_0_MSK 0x1fff0000
++#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
++#define RG_MTX_LEN_UPPER_TH_0_SFT 16
++#define RG_MTX_LEN_UPPER_TH_0_HI 28
++#define RG_MTX_LEN_UPPER_TH_0_SZ 13
++#define RG_MTX_LEN_CNT_EN_0_MSK 0x80000000
++#define RG_MTX_LEN_CNT_EN_0_I_MSK 0x7fffffff
++#define RG_MTX_LEN_CNT_EN_0_SFT 31
++#define RG_MTX_LEN_CNT_EN_0_HI 31
++#define RG_MTX_LEN_CNT_EN_0_SZ 1
++#define RG_MTX_LEN_LOWER_TH_1_MSK 0x00001fff
++#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffffe000
++#define RG_MTX_LEN_LOWER_TH_1_SFT 0
++#define RG_MTX_LEN_LOWER_TH_1_HI 12
++#define RG_MTX_LEN_LOWER_TH_1_SZ 13
++#define RG_MTX_LEN_UPPER_TH_1_MSK 0x1fff0000
++#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
++#define RG_MTX_LEN_UPPER_TH_1_SFT 16
++#define RG_MTX_LEN_UPPER_TH_1_HI 28
++#define RG_MTX_LEN_UPPER_TH_1_SZ 13
++#define RG_MTX_LEN_CNT_EN_1_MSK 0x80000000
++#define RG_MTX_LEN_CNT_EN_1_I_MSK 0x7fffffff
++#define RG_MTX_LEN_CNT_EN_1_SFT 31
++#define RG_MTX_LEN_CNT_EN_1_HI 31
++#define RG_MTX_LEN_CNT_EN_1_SZ 1
++#define RG_MRX_LEN_LOWER_TH_0_MSK 0x00001fff
++#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffffe000
++#define RG_MRX_LEN_LOWER_TH_0_SFT 0
++#define RG_MRX_LEN_LOWER_TH_0_HI 12
++#define RG_MRX_LEN_LOWER_TH_0_SZ 13
++#define RG_MRX_LEN_UPPER_TH_0_MSK 0x1fff0000
++#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
++#define RG_MRX_LEN_UPPER_TH_0_SFT 16
++#define RG_MRX_LEN_UPPER_TH_0_HI 28
++#define RG_MRX_LEN_UPPER_TH_0_SZ 13
++#define RG_MRX_LEN_CNT_EN_0_MSK 0x80000000
++#define RG_MRX_LEN_CNT_EN_0_I_MSK 0x7fffffff
++#define RG_MRX_LEN_CNT_EN_0_SFT 31
++#define RG_MRX_LEN_CNT_EN_0_HI 31
++#define RG_MRX_LEN_CNT_EN_0_SZ 1
++#define RG_MRX_LEN_LOWER_TH_1_MSK 0x00001fff
++#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffffe000
++#define RG_MRX_LEN_LOWER_TH_1_SFT 0
++#define RG_MRX_LEN_LOWER_TH_1_HI 12
++#define RG_MRX_LEN_LOWER_TH_1_SZ 13
++#define RG_MRX_LEN_UPPER_TH_1_MSK 0x1fff0000
++#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
++#define RG_MRX_LEN_UPPER_TH_1_SFT 16
++#define RG_MRX_LEN_UPPER_TH_1_HI 28
++#define RG_MRX_LEN_UPPER_TH_1_SZ 13
++#define RG_MRX_LEN_CNT_EN_1_MSK 0x80000000
++#define RG_MRX_LEN_CNT_EN_1_I_MSK 0x7fffffff
++#define RG_MRX_LEN_CNT_EN_1_SFT 31
++#define RG_MRX_LEN_CNT_EN_1_HI 31
++#define RG_MRX_LEN_CNT_EN_1_SZ 1
++#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff
++#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000
++#define RO_MTX_LEN_CNT_1_SFT 0
++#define RO_MTX_LEN_CNT_1_HI 15
++#define RO_MTX_LEN_CNT_1_SZ 16
++#define RO_MTX_LEN_CNT_0_MSK 0xffff0000
++#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff
++#define RO_MTX_LEN_CNT_0_SFT 16
++#define RO_MTX_LEN_CNT_0_HI 31
++#define RO_MTX_LEN_CNT_0_SZ 16
++#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff
++#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000
++#define RO_MRX_LEN_CNT_1_SFT 0
++#define RO_MRX_LEN_CNT_1_HI 15
++#define RO_MRX_LEN_CNT_1_SZ 16
++#define RO_MRX_LEN_CNT_0_MSK 0xffff0000
++#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff
++#define RO_MRX_LEN_CNT_0_SFT 16
++#define RO_MRX_LEN_CNT_0_HI 31
++#define RO_MRX_LEN_CNT_0_SZ 16
++#define RG_MODE_REG_IN_16_MSK 0x0000ffff
++#define RG_MODE_REG_IN_16_I_MSK 0xffff0000
++#define RG_MODE_REG_IN_16_SFT 0
++#define RG_MODE_REG_IN_16_HI 15
++#define RG_MODE_REG_IN_16_SZ 16
++#define RG_PARALLEL_DR_16_MSK 0x00100000
++#define RG_PARALLEL_DR_16_I_MSK 0xffefffff
++#define RG_PARALLEL_DR_16_SFT 20
++#define RG_PARALLEL_DR_16_HI 20
++#define RG_PARALLEL_DR_16_SZ 1
++#define RG_MBRUN_16_MSK 0x01000000
++#define RG_MBRUN_16_I_MSK 0xfeffffff
++#define RG_MBRUN_16_SFT 24
++#define RG_MBRUN_16_HI 24
++#define RG_MBRUN_16_SZ 1
++#define RG_SHIFT_DR_16_MSK 0x10000000
++#define RG_SHIFT_DR_16_I_MSK 0xefffffff
++#define RG_SHIFT_DR_16_SFT 28
++#define RG_SHIFT_DR_16_HI 28
++#define RG_SHIFT_DR_16_SZ 1
++#define RG_MODE_REG_SI_16_MSK 0x20000000
++#define RG_MODE_REG_SI_16_I_MSK 0xdfffffff
++#define RG_MODE_REG_SI_16_SFT 29
++#define RG_MODE_REG_SI_16_HI 29
++#define RG_MODE_REG_SI_16_SZ 1
++#define RG_SIMULATION_MODE_16_MSK 0x40000000
++#define RG_SIMULATION_MODE_16_I_MSK 0xbfffffff
++#define RG_SIMULATION_MODE_16_SFT 30
++#define RG_SIMULATION_MODE_16_HI 30
++#define RG_SIMULATION_MODE_16_SZ 1
++#define RG_DBIST_MODE_16_MSK 0x80000000
++#define RG_DBIST_MODE_16_I_MSK 0x7fffffff
++#define RG_DBIST_MODE_16_SFT 31
++#define RG_DBIST_MODE_16_HI 31
++#define RG_DBIST_MODE_16_SZ 1
++#define RO_MODE_REG_OUT_16_MSK 0x0000ffff
++#define RO_MODE_REG_OUT_16_I_MSK 0xffff0000
++#define RO_MODE_REG_OUT_16_SFT 0
++#define RO_MODE_REG_OUT_16_HI 15
++#define RO_MODE_REG_OUT_16_SZ 16
++#define RO_MODE_REG_SO_16_MSK 0x01000000
++#define RO_MODE_REG_SO_16_I_MSK 0xfeffffff
++#define RO_MODE_REG_SO_16_SFT 24
++#define RO_MODE_REG_SO_16_HI 24
++#define RO_MODE_REG_SO_16_SZ 1
++#define RO_MONITOR_BUS_16_MSK 0x0007ffff
++#define RO_MONITOR_BUS_16_I_MSK 0xfff80000
++#define RO_MONITOR_BUS_16_SFT 0
++#define RO_MONITOR_BUS_16_HI 18
++#define RO_MONITOR_BUS_16_SZ 19
++#define RG_MRX_TYPE_1_MSK 0x000000ff
++#define RG_MRX_TYPE_1_I_MSK 0xffffff00
++#define RG_MRX_TYPE_1_SFT 0
++#define RG_MRX_TYPE_1_HI 7
++#define RG_MRX_TYPE_1_SZ 8
++#define RG_MRX_TYPE_0_MSK 0x0000ff00
++#define RG_MRX_TYPE_0_I_MSK 0xffff00ff
++#define RG_MRX_TYPE_0_SFT 8
++#define RG_MRX_TYPE_0_HI 15
++#define RG_MRX_TYPE_0_SZ 8
++#define RG_MTX_TYPE_1_MSK 0x00ff0000
++#define RG_MTX_TYPE_1_I_MSK 0xff00ffff
++#define RG_MTX_TYPE_1_SFT 16
++#define RG_MTX_TYPE_1_HI 23
++#define RG_MTX_TYPE_1_SZ 8
++#define RG_MTX_TYPE_0_MSK 0xff000000
++#define RG_MTX_TYPE_0_I_MSK 0x00ffffff
++#define RG_MTX_TYPE_0_SFT 24
++#define RG_MTX_TYPE_0_HI 31
++#define RG_MTX_TYPE_0_SZ 8
++#define RO_MTX_TYPE_CNT_1_MSK 0x0000ffff
++#define RO_MTX_TYPE_CNT_1_I_MSK 0xffff0000
++#define RO_MTX_TYPE_CNT_1_SFT 0
++#define RO_MTX_TYPE_CNT_1_HI 15
++#define RO_MTX_TYPE_CNT_1_SZ 16
++#define RO_MTX_TYPE_CNT_0_MSK 0xffff0000
++#define RO_MTX_TYPE_CNT_0_I_MSK 0x0000ffff
++#define RO_MTX_TYPE_CNT_0_SFT 16
++#define RO_MTX_TYPE_CNT_0_HI 31
++#define RO_MTX_TYPE_CNT_0_SZ 16
++#define RO_MRX_TYPE_CNT_1_MSK 0x0000ffff
++#define RO_MRX_TYPE_CNT_1_I_MSK 0xffff0000
++#define RO_MRX_TYPE_CNT_1_SFT 0
++#define RO_MRX_TYPE_CNT_1_HI 15
++#define RO_MRX_TYPE_CNT_1_SZ 16
++#define RO_MRX_TYPE_CNT_0_MSK 0xffff0000
++#define RO_MRX_TYPE_CNT_0_I_MSK 0x0000ffff
++#define RO_MRX_TYPE_CNT_0_SFT 16
++#define RO_MRX_TYPE_CNT_0_HI 31
++#define RO_MRX_TYPE_CNT_0_SZ 16
++#define RG_HB_COEF0_MSK 0x00000fff
++#define RG_HB_COEF0_I_MSK 0xfffff000
++#define RG_HB_COEF0_SFT 0
++#define RG_HB_COEF0_HI 11
++#define RG_HB_COEF0_SZ 12
++#define RG_HB_COEF1_MSK 0x0fff0000
++#define RG_HB_COEF1_I_MSK 0xf000ffff
++#define RG_HB_COEF1_SFT 16
++#define RG_HB_COEF1_HI 27
++#define RG_HB_COEF1_SZ 12
++#define RG_HB_COEF2_MSK 0x00000fff
++#define RG_HB_COEF2_I_MSK 0xfffff000
++#define RG_HB_COEF2_SFT 0
++#define RG_HB_COEF2_HI 11
++#define RG_HB_COEF2_SZ 12
++#define RG_HB_COEF3_MSK 0x0fff0000
++#define RG_HB_COEF3_I_MSK 0xf000ffff
++#define RG_HB_COEF3_SFT 16
++#define RG_HB_COEF3_HI 27
++#define RG_HB_COEF3_SZ 12
++#define RG_HB_COEF4_MSK 0x00000fff
++#define RG_HB_COEF4_I_MSK 0xfffff000
++#define RG_HB_COEF4_SFT 0
++#define RG_HB_COEF4_HI 11
++#define RG_HB_COEF4_SZ 12
++#define RO_TBUS_O_MSK 0x000fffff
++#define RO_TBUS_O_I_MSK 0xfff00000
++#define RO_TBUS_O_SFT 0
++#define RO_TBUS_O_HI 19
++#define RO_TBUS_O_SZ 20
++#define RG_LPF4_00_MSK 0x00001fff
++#define RG_LPF4_00_I_MSK 0xffffe000
++#define RG_LPF4_00_SFT 0
++#define RG_LPF4_00_HI 12
++#define RG_LPF4_00_SZ 13
++#define RG_LPF4_01_MSK 0x00001fff
++#define RG_LPF4_01_I_MSK 0xffffe000
++#define RG_LPF4_01_SFT 0
++#define RG_LPF4_01_HI 12
++#define RG_LPF4_01_SZ 13
++#define RG_LPF4_02_MSK 0x00001fff
++#define RG_LPF4_02_I_MSK 0xffffe000
++#define RG_LPF4_02_SFT 0
++#define RG_LPF4_02_HI 12
++#define RG_LPF4_02_SZ 13
++#define RG_LPF4_03_MSK 0x00001fff
++#define RG_LPF4_03_I_MSK 0xffffe000
++#define RG_LPF4_03_SFT 0
++#define RG_LPF4_03_HI 12
++#define RG_LPF4_03_SZ 13
++#define RG_LPF4_04_MSK 0x00001fff
++#define RG_LPF4_04_I_MSK 0xffffe000
++#define RG_LPF4_04_SFT 0
++#define RG_LPF4_04_HI 12
++#define RG_LPF4_04_SZ 13
++#define RG_LPF4_05_MSK 0x00001fff
++#define RG_LPF4_05_I_MSK 0xffffe000
++#define RG_LPF4_05_SFT 0
++#define RG_LPF4_05_HI 12
++#define RG_LPF4_05_SZ 13
++#define RG_LPF4_06_MSK 0x00001fff
++#define RG_LPF4_06_I_MSK 0xffffe000
++#define RG_LPF4_06_SFT 0
++#define RG_LPF4_06_HI 12
++#define RG_LPF4_06_SZ 13
++#define RG_LPF4_07_MSK 0x00001fff
++#define RG_LPF4_07_I_MSK 0xffffe000
++#define RG_LPF4_07_SFT 0
++#define RG_LPF4_07_HI 12
++#define RG_LPF4_07_SZ 13
++#define RG_LPF4_08_MSK 0x00001fff
++#define RG_LPF4_08_I_MSK 0xffffe000
++#define RG_LPF4_08_SFT 0
++#define RG_LPF4_08_HI 12
++#define RG_LPF4_08_SZ 13
++#define RG_LPF4_09_MSK 0x00001fff
++#define RG_LPF4_09_I_MSK 0xffffe000
++#define RG_LPF4_09_SFT 0
++#define RG_LPF4_09_HI 12
++#define RG_LPF4_09_SZ 13
++#define RG_LPF4_10_MSK 0x00001fff
++#define RG_LPF4_10_I_MSK 0xffffe000
++#define RG_LPF4_10_SFT 0
++#define RG_LPF4_10_HI 12
++#define RG_LPF4_10_SZ 13
++#define RG_LPF4_11_MSK 0x00001fff
++#define RG_LPF4_11_I_MSK 0xffffe000
++#define RG_LPF4_11_SFT 0
++#define RG_LPF4_11_HI 12
++#define RG_LPF4_11_SZ 13
++#define RG_LPF4_12_MSK 0x00001fff
++#define RG_LPF4_12_I_MSK 0xffffe000
++#define RG_LPF4_12_SFT 0
++#define RG_LPF4_12_HI 12
++#define RG_LPF4_12_SZ 13
++#define RG_LPF4_13_MSK 0x00001fff
++#define RG_LPF4_13_I_MSK 0xffffe000
++#define RG_LPF4_13_SFT 0
++#define RG_LPF4_13_HI 12
++#define RG_LPF4_13_SZ 13
++#define RG_LPF4_14_MSK 0x00001fff
++#define RG_LPF4_14_I_MSK 0xffffe000
++#define RG_LPF4_14_SFT 0
++#define RG_LPF4_14_HI 12
++#define RG_LPF4_14_SZ 13
++#define RG_LPF4_15_MSK 0x00001fff
++#define RG_LPF4_15_I_MSK 0xffffe000
++#define RG_LPF4_15_SFT 0
++#define RG_LPF4_15_HI 12
++#define RG_LPF4_15_SZ 13
++#define RG_LPF4_16_MSK 0x00001fff
++#define RG_LPF4_16_I_MSK 0xffffe000
++#define RG_LPF4_16_SFT 0
++#define RG_LPF4_16_HI 12
++#define RG_LPF4_16_SZ 13
++#define RG_LPF4_17_MSK 0x00001fff
++#define RG_LPF4_17_I_MSK 0xffffe000
++#define RG_LPF4_17_SFT 0
++#define RG_LPF4_17_HI 12
++#define RG_LPF4_17_SZ 13
++#define RG_LPF4_18_MSK 0x00001fff
++#define RG_LPF4_18_I_MSK 0xffffe000
++#define RG_LPF4_18_SFT 0
++#define RG_LPF4_18_HI 12
++#define RG_LPF4_18_SZ 13
++#define RG_LPF4_19_MSK 0x00001fff
++#define RG_LPF4_19_I_MSK 0xffffe000
++#define RG_LPF4_19_SFT 0
++#define RG_LPF4_19_HI 12
++#define RG_LPF4_19_SZ 13
++#define RG_LPF4_20_MSK 0x00001fff
++#define RG_LPF4_20_I_MSK 0xffffe000
++#define RG_LPF4_20_SFT 0
++#define RG_LPF4_20_HI 12
++#define RG_LPF4_20_SZ 13
++#define RG_LPF4_21_MSK 0x00001fff
++#define RG_LPF4_21_I_MSK 0xffffe000
++#define RG_LPF4_21_SFT 0
++#define RG_LPF4_21_HI 12
++#define RG_LPF4_21_SZ 13
++#define RG_LPF4_22_MSK 0x00001fff
++#define RG_LPF4_22_I_MSK 0xffffe000
++#define RG_LPF4_22_SFT 0
++#define RG_LPF4_22_HI 12
++#define RG_LPF4_22_SZ 13
++#define RG_LPF4_23_MSK 0x00001fff
++#define RG_LPF4_23_I_MSK 0xffffe000
++#define RG_LPF4_23_SFT 0
++#define RG_LPF4_23_HI 12
++#define RG_LPF4_23_SZ 13
++#define RG_LPF4_24_MSK 0x00001fff
++#define RG_LPF4_24_I_MSK 0xffffe000
++#define RG_LPF4_24_SFT 0
++#define RG_LPF4_24_HI 12
++#define RG_LPF4_24_SZ 13
++#define RG_LPF4_25_MSK 0x00001fff
++#define RG_LPF4_25_I_MSK 0xffffe000
++#define RG_LPF4_25_SFT 0
++#define RG_LPF4_25_HI 12
++#define RG_LPF4_25_SZ 13
++#define RG_LPF4_26_MSK 0x00001fff
++#define RG_LPF4_26_I_MSK 0xffffe000
++#define RG_LPF4_26_SFT 0
++#define RG_LPF4_26_HI 12
++#define RG_LPF4_26_SZ 13
++#define RG_LPF4_27_MSK 0x00001fff
++#define RG_LPF4_27_I_MSK 0xffffe000
++#define RG_LPF4_27_SFT 0
++#define RG_LPF4_27_HI 12
++#define RG_LPF4_27_SZ 13
++#define RG_LPF4_28_MSK 0x00001fff
++#define RG_LPF4_28_I_MSK 0xffffe000
++#define RG_LPF4_28_SFT 0
++#define RG_LPF4_28_HI 12
++#define RG_LPF4_28_SZ 13
++#define RG_LPF4_29_MSK 0x00001fff
++#define RG_LPF4_29_I_MSK 0xffffe000
++#define RG_LPF4_29_SFT 0
++#define RG_LPF4_29_HI 12
++#define RG_LPF4_29_SZ 13
++#define RG_LPF4_30_MSK 0x00001fff
++#define RG_LPF4_30_I_MSK 0xffffe000
++#define RG_LPF4_30_SFT 0
++#define RG_LPF4_30_HI 12
++#define RG_LPF4_30_SZ 13
++#define RG_LPF4_31_MSK 0x00001fff
++#define RG_LPF4_31_I_MSK 0xffffe000
++#define RG_LPF4_31_SFT 0
++#define RG_LPF4_31_HI 12
++#define RG_LPF4_31_SZ 13
++#define RG_LPF4_32_MSK 0x00001fff
++#define RG_LPF4_32_I_MSK 0xffffe000
++#define RG_LPF4_32_SFT 0
++#define RG_LPF4_32_HI 12
++#define RG_LPF4_32_SZ 13
++#define RG_LPF4_33_MSK 0x00001fff
++#define RG_LPF4_33_I_MSK 0xffffe000
++#define RG_LPF4_33_SFT 0
++#define RG_LPF4_33_HI 12
++#define RG_LPF4_33_SZ 13
++#define RG_LPF4_34_MSK 0x00001fff
++#define RG_LPF4_34_I_MSK 0xffffe000
++#define RG_LPF4_34_SFT 0
++#define RG_LPF4_34_HI 12
++#define RG_LPF4_34_SZ 13
++#define RG_LPF4_35_MSK 0x00001fff
++#define RG_LPF4_35_I_MSK 0xffffe000
++#define RG_LPF4_35_SFT 0
++#define RG_LPF4_35_HI 12
++#define RG_LPF4_35_SZ 13
++#define RG_LPF4_36_MSK 0x00001fff
++#define RG_LPF4_36_I_MSK 0xffffe000
++#define RG_LPF4_36_SFT 0
++#define RG_LPF4_36_HI 12
++#define RG_LPF4_36_SZ 13
++#define RG_LPF4_37_MSK 0x00001fff
++#define RG_LPF4_37_I_MSK 0xffffe000
++#define RG_LPF4_37_SFT 0
++#define RG_LPF4_37_HI 12
++#define RG_LPF4_37_SZ 13
++#define RG_LPF4_38_MSK 0x00001fff
++#define RG_LPF4_38_I_MSK 0xffffe000
++#define RG_LPF4_38_SFT 0
++#define RG_LPF4_38_HI 12
++#define RG_LPF4_38_SZ 13
++#define RG_LPF4_39_MSK 0x00001fff
++#define RG_LPF4_39_I_MSK 0xffffe000
++#define RG_LPF4_39_SFT 0
++#define RG_LPF4_39_HI 12
++#define RG_LPF4_39_SZ 13
++#define RG_LPF4_40_MSK 0x00001fff
++#define RG_LPF4_40_I_MSK 0xffffe000
++#define RG_LPF4_40_SFT 0
++#define RG_LPF4_40_HI 12
++#define RG_LPF4_40_SZ 13
++#define RG_BP_SMB_MSK 0x00002000
++#define RG_BP_SMB_I_MSK 0xffffdfff
++#define RG_BP_SMB_SFT 13
++#define RG_BP_SMB_HI 13
++#define RG_BP_SMB_SZ 1
++#define RG_EN_SRVC_MSK 0x00004000
++#define RG_EN_SRVC_I_MSK 0xffffbfff
++#define RG_EN_SRVC_SFT 14
++#define RG_EN_SRVC_HI 14
++#define RG_EN_SRVC_SZ 1
++#define RG_DES_SPD_MSK 0x00030000
++#define RG_DES_SPD_I_MSK 0xfffcffff
++#define RG_DES_SPD_SFT 16
++#define RG_DES_SPD_HI 17
++#define RG_DES_SPD_SZ 2
++#define RG_BB_11B_RISE_TIME_MSK 0x000000ff
++#define RG_BB_11B_RISE_TIME_I_MSK 0xffffff00
++#define RG_BB_11B_RISE_TIME_SFT 0
++#define RG_BB_11B_RISE_TIME_HI 7
++#define RG_BB_11B_RISE_TIME_SZ 8
++#define RG_BB_11B_FALL_TIME_MSK 0x0000ff00
++#define RG_BB_11B_FALL_TIME_I_MSK 0xffff00ff
++#define RG_BB_11B_FALL_TIME_SFT 8
++#define RG_BB_11B_FALL_TIME_HI 15
++#define RG_BB_11B_FALL_TIME_SZ 8
++#define RG_WR_TX_EN_CNT_RST_N_MSK 0x00000001
++#define RG_WR_TX_EN_CNT_RST_N_I_MSK 0xfffffffe
++#define RG_WR_TX_EN_CNT_RST_N_SFT 0
++#define RG_WR_TX_EN_CNT_RST_N_HI 0
++#define RG_WR_TX_EN_CNT_RST_N_SZ 1
++#define RO_TX_EN_CNT_MSK 0x0000ffff
++#define RO_TX_EN_CNT_I_MSK 0xffff0000
++#define RO_TX_EN_CNT_SFT 0
++#define RO_TX_EN_CNT_HI 15
++#define RO_TX_EN_CNT_SZ 16
++#define RO_TX_CNT_MSK 0xffffffff
++#define RO_TX_CNT_I_MSK 0x00000000
++#define RO_TX_CNT_SFT 0
++#define RO_TX_CNT_HI 31
++#define RO_TX_CNT_SZ 32
++#define RG_POS_DES_11B_L_EXT_MSK 0x0000000f
++#define RG_POS_DES_11B_L_EXT_I_MSK 0xfffffff0
++#define RG_POS_DES_11B_L_EXT_SFT 0
++#define RG_POS_DES_11B_L_EXT_HI 3
++#define RG_POS_DES_11B_L_EXT_SZ 4
++#define RG_PRE_DES_11B_DLY_MSK 0x000000f0
++#define RG_PRE_DES_11B_DLY_I_MSK 0xffffff0f
++#define RG_PRE_DES_11B_DLY_SFT 4
++#define RG_PRE_DES_11B_DLY_HI 7
++#define RG_PRE_DES_11B_DLY_SZ 4
++#define RG_CNT_CCA_LMT_MSK 0x000f0000
++#define RG_CNT_CCA_LMT_I_MSK 0xfff0ffff
++#define RG_CNT_CCA_LMT_SFT 16
++#define RG_CNT_CCA_LMT_HI 19
++#define RG_CNT_CCA_LMT_SZ 4
++#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000
++#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff
++#define RG_BYPASS_DESCRAMBLER_SFT 29
++#define RG_BYPASS_DESCRAMBLER_HI 29
++#define RG_BYPASS_DESCRAMBLER_SZ 1
++#define RG_BYPASS_AGC_MSK 0x80000000
++#define RG_BYPASS_AGC_I_MSK 0x7fffffff
++#define RG_BYPASS_AGC_SFT 31
++#define RG_BYPASS_AGC_HI 31
++#define RG_BYPASS_AGC_SZ 1
++#define RG_CCA_BIT_CNT_LMT_RX_MSK 0x000000f0
++#define RG_CCA_BIT_CNT_LMT_RX_I_MSK 0xffffff0f
++#define RG_CCA_BIT_CNT_LMT_RX_SFT 4
++#define RG_CCA_BIT_CNT_LMT_RX_HI 7
++#define RG_CCA_BIT_CNT_LMT_RX_SZ 4
++#define RG_CCA_SCALE_BF_MSK 0x007f0000
++#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff
++#define RG_CCA_SCALE_BF_SFT 16
++#define RG_CCA_SCALE_BF_HI 22
++#define RG_CCA_SCALE_BF_SZ 7
++#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000
++#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff
++#define RG_PEAK_IDX_CNT_SEL_SFT 28
++#define RG_PEAK_IDX_CNT_SEL_HI 29
++#define RG_PEAK_IDX_CNT_SEL_SZ 2
++#define RG_TR_KI_T2_MSK 0x00000007
++#define RG_TR_KI_T2_I_MSK 0xfffffff8
++#define RG_TR_KI_T2_SFT 0
++#define RG_TR_KI_T2_HI 2
++#define RG_TR_KI_T2_SZ 3
++#define RG_TR_KP_T2_MSK 0x00000070
++#define RG_TR_KP_T2_I_MSK 0xffffff8f
++#define RG_TR_KP_T2_SFT 4
++#define RG_TR_KP_T2_HI 6
++#define RG_TR_KP_T2_SZ 3
++#define RG_TR_KI_T1_MSK 0x00000700
++#define RG_TR_KI_T1_I_MSK 0xfffff8ff
++#define RG_TR_KI_T1_SFT 8
++#define RG_TR_KI_T1_HI 10
++#define RG_TR_KI_T1_SZ 3
++#define RG_TR_KP_T1_MSK 0x00007000
++#define RG_TR_KP_T1_I_MSK 0xffff8fff
++#define RG_TR_KP_T1_SFT 12
++#define RG_TR_KP_T1_HI 14
++#define RG_TR_KP_T1_SZ 3
++#define RG_CR_KI_T1_MSK 0x00070000
++#define RG_CR_KI_T1_I_MSK 0xfff8ffff
++#define RG_CR_KI_T1_SFT 16
++#define RG_CR_KI_T1_HI 18
++#define RG_CR_KI_T1_SZ 3
++#define RG_CR_KP_T1_MSK 0x00700000
++#define RG_CR_KP_T1_I_MSK 0xff8fffff
++#define RG_CR_KP_T1_SFT 20
++#define RG_CR_KP_T1_HI 22
++#define RG_CR_KP_T1_SZ 3
++#define RG_CHIP_CNT_SLICER_MSK 0x0000001f
++#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0
++#define RG_CHIP_CNT_SLICER_SFT 0
++#define RG_CHIP_CNT_SLICER_HI 4
++#define RG_CHIP_CNT_SLICER_SZ 5
++#define RG_CE_T4_CNT_LMT_MSK 0x0000ff00
++#define RG_CE_T4_CNT_LMT_I_MSK 0xffff00ff
++#define RG_CE_T4_CNT_LMT_SFT 8
++#define RG_CE_T4_CNT_LMT_HI 15
++#define RG_CE_T4_CNT_LMT_SZ 8
++#define RG_CE_T3_CNT_LMT_MSK 0x00ff0000
++#define RG_CE_T3_CNT_LMT_I_MSK 0xff00ffff
++#define RG_CE_T3_CNT_LMT_SFT 16
++#define RG_CE_T3_CNT_LMT_HI 23
++#define RG_CE_T3_CNT_LMT_SZ 8
++#define RG_CE_T2_CNT_LMT_MSK 0xff000000
++#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff
++#define RG_CE_T2_CNT_LMT_SFT 24
++#define RG_CE_T2_CNT_LMT_HI 31
++#define RG_CE_T2_CNT_LMT_SZ 8
++#define RG_CE_MU_T1_MSK 0x00000007
++#define RG_CE_MU_T1_I_MSK 0xfffffff8
++#define RG_CE_MU_T1_SFT 0
++#define RG_CE_MU_T1_HI 2
++#define RG_CE_MU_T1_SZ 3
++#define RG_CE_DLY_SEL_MSK 0x003f0000
++#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff
++#define RG_CE_DLY_SEL_SFT 16
++#define RG_CE_DLY_SEL_HI 21
++#define RG_CE_DLY_SEL_SZ 6
++#define RG_CE_MU_T8_MSK 0x00000007
++#define RG_CE_MU_T8_I_MSK 0xfffffff8
++#define RG_CE_MU_T8_SFT 0
++#define RG_CE_MU_T8_HI 2
++#define RG_CE_MU_T8_SZ 3
++#define RG_CE_MU_T7_MSK 0x00000070
++#define RG_CE_MU_T7_I_MSK 0xffffff8f
++#define RG_CE_MU_T7_SFT 4
++#define RG_CE_MU_T7_HI 6
++#define RG_CE_MU_T7_SZ 3
++#define RG_CE_MU_T6_MSK 0x00000700
++#define RG_CE_MU_T6_I_MSK 0xfffff8ff
++#define RG_CE_MU_T6_SFT 8
++#define RG_CE_MU_T6_HI 10
++#define RG_CE_MU_T6_SZ 3
++#define RG_CE_MU_T5_MSK 0x00007000
++#define RG_CE_MU_T5_I_MSK 0xffff8fff
++#define RG_CE_MU_T5_SFT 12
++#define RG_CE_MU_T5_HI 14
++#define RG_CE_MU_T5_SZ 3
++#define RG_CE_MU_T4_MSK 0x00070000
++#define RG_CE_MU_T4_I_MSK 0xfff8ffff
++#define RG_CE_MU_T4_SFT 16
++#define RG_CE_MU_T4_HI 18
++#define RG_CE_MU_T4_SZ 3
++#define RG_CE_MU_T3_MSK 0x00700000
++#define RG_CE_MU_T3_I_MSK 0xff8fffff
++#define RG_CE_MU_T3_SFT 20
++#define RG_CE_MU_T3_HI 22
++#define RG_CE_MU_T3_SZ 3
++#define RG_CE_MU_T2_MSK 0x07000000
++#define RG_CE_MU_T2_I_MSK 0xf8ffffff
++#define RG_CE_MU_T2_SFT 24
++#define RG_CE_MU_T2_HI 26
++#define RG_CE_MU_T2_SZ 3
++#define RG_EQ_MU_FB_T2_MSK 0x0000000f
++#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0
++#define RG_EQ_MU_FB_T2_SFT 0
++#define RG_EQ_MU_FB_T2_HI 3
++#define RG_EQ_MU_FB_T2_SZ 4
++#define RG_EQ_MU_FF_T2_MSK 0x000000f0
++#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f
++#define RG_EQ_MU_FF_T2_SFT 4
++#define RG_EQ_MU_FF_T2_HI 7
++#define RG_EQ_MU_FF_T2_SZ 4
++#define RG_EQ_MU_FB_T1_MSK 0x000f0000
++#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff
++#define RG_EQ_MU_FB_T1_SFT 16
++#define RG_EQ_MU_FB_T1_HI 19
++#define RG_EQ_MU_FB_T1_SZ 4
++#define RG_EQ_MU_FF_T1_MSK 0x00f00000
++#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff
++#define RG_EQ_MU_FF_T1_SFT 20
++#define RG_EQ_MU_FF_T1_HI 23
++#define RG_EQ_MU_FF_T1_SZ 4
++#define RG_EQ_MU_FB_T4_MSK 0x0000000f
++#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0
++#define RG_EQ_MU_FB_T4_SFT 0
++#define RG_EQ_MU_FB_T4_HI 3
++#define RG_EQ_MU_FB_T4_SZ 4
++#define RG_EQ_MU_FF_T4_MSK 0x000000f0
++#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f
++#define RG_EQ_MU_FF_T4_SFT 4
++#define RG_EQ_MU_FF_T4_HI 7
++#define RG_EQ_MU_FF_T4_SZ 4
++#define RG_EQ_MU_FB_T3_MSK 0x000f0000
++#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff
++#define RG_EQ_MU_FB_T3_SFT 16
++#define RG_EQ_MU_FB_T3_HI 19
++#define RG_EQ_MU_FB_T3_SZ 4
++#define RG_EQ_MU_FF_T3_MSK 0x00f00000
++#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff
++#define RG_EQ_MU_FF_T3_SFT 20
++#define RG_EQ_MU_FF_T3_HI 23
++#define RG_EQ_MU_FF_T3_SZ 4
++#define RG_EQ_KI_T2_MSK 0x00000700
++#define RG_EQ_KI_T2_I_MSK 0xfffff8ff
++#define RG_EQ_KI_T2_SFT 8
++#define RG_EQ_KI_T2_HI 10
++#define RG_EQ_KI_T2_SZ 3
++#define RG_EQ_KP_T2_MSK 0x00007000
++#define RG_EQ_KP_T2_I_MSK 0xffff8fff
++#define RG_EQ_KP_T2_SFT 12
++#define RG_EQ_KP_T2_HI 14
++#define RG_EQ_KP_T2_SZ 3
++#define RG_EQ_KI_T1_MSK 0x00070000
++#define RG_EQ_KI_T1_I_MSK 0xfff8ffff
++#define RG_EQ_KI_T1_SFT 16
++#define RG_EQ_KI_T1_HI 18
++#define RG_EQ_KI_T1_SZ 3
++#define RG_EQ_KP_T1_MSK 0x00700000
++#define RG_EQ_KP_T1_I_MSK 0xff8fffff
++#define RG_EQ_KP_T1_SFT 20
++#define RG_EQ_KP_T1_HI 22
++#define RG_EQ_KP_T1_SZ 3
++#define RG_TR_LPF_RATE_MSK 0x003fffff
++#define RG_TR_LPF_RATE_I_MSK 0xffc00000
++#define RG_TR_LPF_RATE_SFT 0
++#define RG_TR_LPF_RATE_HI 21
++#define RG_TR_LPF_RATE_SZ 22
++#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f
++#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80
++#define RG_CE_BIT_CNT_LMT_SFT 0
++#define RG_CE_BIT_CNT_LMT_HI 6
++#define RG_CE_BIT_CNT_LMT_SZ 7
++#define RG_CE_CH_MAIN_SET_MSK 0x00000080
++#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f
++#define RG_CE_CH_MAIN_SET_SFT 7
++#define RG_CE_CH_MAIN_SET_HI 7
++#define RG_CE_CH_MAIN_SET_SZ 1
++#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00
++#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff
++#define RG_TC_BIT_CNT_LMT_SFT 8
++#define RG_TC_BIT_CNT_LMT_HI 14
++#define RG_TC_BIT_CNT_LMT_SZ 7
++#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000
++#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff
++#define RG_CR_BIT_CNT_LMT_SFT 16
++#define RG_CR_BIT_CNT_LMT_HI 22
++#define RG_CR_BIT_CNT_LMT_SZ 7
++#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000
++#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff
++#define RG_TR_BIT_CNT_LMT_SFT 24
++#define RG_TR_BIT_CNT_LMT_HI 30
++#define RG_TR_BIT_CNT_LMT_SZ 7
++#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001
++#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe
++#define RG_EQ_MAIN_TAP_MAN_SFT 0
++#define RG_EQ_MAIN_TAP_MAN_HI 0
++#define RG_EQ_MAIN_TAP_MAN_SZ 1
++#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000
++#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff
++#define RG_EQ_MAIN_TAP_COEF_SFT 16
++#define RG_EQ_MAIN_TAP_COEF_HI 26
++#define RG_EQ_MAIN_TAP_COEF_SZ 11
++#define RG_PWRON_DLY_TH_11B_MSK 0x000000ff
++#define RG_PWRON_DLY_TH_11B_I_MSK 0xffffff00
++#define RG_PWRON_DLY_TH_11B_SFT 0
++#define RG_PWRON_DLY_TH_11B_HI 7
++#define RG_PWRON_DLY_TH_11B_SZ 8
++#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000
++#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff
++#define RG_SFD_BIT_CNT_LMT_SFT 16
++#define RG_SFD_BIT_CNT_LMT_HI 23
++#define RG_SFD_BIT_CNT_LMT_SZ 8
++#define RG_CCA_PWR_TH_RX_MSK 0x00007fff
++#define RG_CCA_PWR_TH_RX_I_MSK 0xffff8000
++#define RG_CCA_PWR_TH_RX_SFT 0
++#define RG_CCA_PWR_TH_RX_HI 14
++#define RG_CCA_PWR_TH_RX_SZ 15
++#define RG_CCA_PWR_CNT_TH_MSK 0x001f0000
++#define RG_CCA_PWR_CNT_TH_I_MSK 0xffe0ffff
++#define RG_CCA_PWR_CNT_TH_SFT 16
++#define RG_CCA_PWR_CNT_TH_HI 20
++#define RG_CCA_PWR_CNT_TH_SZ 5
++#define B_FREQ_OS_MSK 0x000007ff
++#define B_FREQ_OS_I_MSK 0xfffff800
++#define B_FREQ_OS_SFT 0
++#define B_FREQ_OS_HI 10
++#define B_FREQ_OS_SZ 11
++#define B_SNR_MSK 0x0000007f
++#define B_SNR_I_MSK 0xffffff80
++#define B_SNR_SFT 0
++#define B_SNR_HI 6
++#define B_SNR_SZ 7
++#define B_RCPI_MSK 0x007f0000
++#define B_RCPI_I_MSK 0xff80ffff
++#define B_RCPI_SFT 16
++#define B_RCPI_HI 22
++#define B_RCPI_SZ 7
++#define CRC_CNT_MSK 0x0000ffff
++#define CRC_CNT_I_MSK 0xffff0000
++#define CRC_CNT_SFT 0
++#define CRC_CNT_HI 15
++#define CRC_CNT_SZ 16
++#define SFD_CNT_MSK 0xffff0000
++#define SFD_CNT_I_MSK 0x0000ffff
++#define SFD_CNT_SFT 16
++#define SFD_CNT_HI 31
++#define SFD_CNT_SZ 16
++#define B_PACKET_ERR_CNT_MSK 0x0000ffff
++#define B_PACKET_ERR_CNT_I_MSK 0xffff0000
++#define B_PACKET_ERR_CNT_SFT 0
++#define B_PACKET_ERR_CNT_HI 15
++#define B_PACKET_ERR_CNT_SZ 16
++#define PACKET_ERR_MSK 0x00010000
++#define PACKET_ERR_I_MSK 0xfffeffff
++#define PACKET_ERR_SFT 16
++#define PACKET_ERR_HI 16
++#define PACKET_ERR_SZ 1
++#define B_PACKET_CNT_MSK 0x0000ffff
++#define B_PACKET_CNT_I_MSK 0xffff0000
++#define B_PACKET_CNT_SFT 0
++#define B_PACKET_CNT_HI 15
++#define B_PACKET_CNT_SZ 16
++#define B_CCA_CNT_MSK 0xffff0000
++#define B_CCA_CNT_I_MSK 0x0000ffff
++#define B_CCA_CNT_SFT 16
++#define B_CCA_CNT_HI 31
++#define B_CCA_CNT_SZ 16
++#define B_LENGTH_FIELD_MSK 0x0000ffff
++#define B_LENGTH_FIELD_I_MSK 0xffff0000
++#define B_LENGTH_FIELD_SFT 0
++#define B_LENGTH_FIELD_HI 15
++#define B_LENGTH_FIELD_SZ 16
++#define SFD_FIELD_MSK 0xffff0000
++#define SFD_FIELD_I_MSK 0x0000ffff
++#define SFD_FIELD_SFT 16
++#define SFD_FIELD_HI 31
++#define SFD_FIELD_SZ 16
++#define SIGNAL_FIELD_MSK 0x000000ff
++#define SIGNAL_FIELD_I_MSK 0xffffff00
++#define SIGNAL_FIELD_SFT 0
++#define SIGNAL_FIELD_HI 7
++#define SIGNAL_FIELD_SZ 8
++#define B_SERVICE_FIELD_MSK 0x0000ff00
++#define B_SERVICE_FIELD_I_MSK 0xffff00ff
++#define B_SERVICE_FIELD_SFT 8
++#define B_SERVICE_FIELD_HI 15
++#define B_SERVICE_FIELD_SZ 8
++#define CRC_CORRECT_MSK 0x00010000
++#define CRC_CORRECT_I_MSK 0xfffeffff
++#define CRC_CORRECT_SFT 16
++#define CRC_CORRECT_HI 16
++#define CRC_CORRECT_SZ 1
++#define DEBUG_SEL_MSK 0x0000000f
++#define DEBUG_SEL_I_MSK 0xfffffff0
++#define DEBUG_SEL_SFT 0
++#define DEBUG_SEL_HI 3
++#define DEBUG_SEL_SZ 4
++#define RG_PACKET_STAT_EN_11B_MSK 0x00100000
++#define RG_PACKET_STAT_EN_11B_I_MSK 0xffefffff
++#define RG_PACKET_STAT_EN_11B_SFT 20
++#define RG_PACKET_STAT_EN_11B_HI 20
++#define RG_PACKET_STAT_EN_11B_SZ 1
++#define RG_BIT_REVERSE_MSK 0x00200000
++#define RG_BIT_REVERSE_I_MSK 0xffdfffff
++#define RG_BIT_REVERSE_SFT 21
++#define RG_BIT_REVERSE_HI 21
++#define RG_BIT_REVERSE_SZ 1
++#define RX_PHY_11B_SOFT_RST_N_MSK 0x00000001
++#define RX_PHY_11B_SOFT_RST_N_I_MSK 0xfffffffe
++#define RX_PHY_11B_SOFT_RST_N_SFT 0
++#define RX_PHY_11B_SOFT_RST_N_HI 0
++#define RX_PHY_11B_SOFT_RST_N_SZ 1
++#define RG_CE_BYPASS_TAP_MSK 0x000000f0
++#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f
++#define RG_CE_BYPASS_TAP_SFT 4
++#define RG_CE_BYPASS_TAP_HI 7
++#define RG_CE_BYPASS_TAP_SZ 4
++#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00
++#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff
++#define RG_EQ_BYPASS_FBW_TAP_SFT 8
++#define RG_EQ_BYPASS_FBW_TAP_HI 11
++#define RG_EQ_BYPASS_FBW_TAP_SZ 4
++#define RG_BB_11GN_RISE_TIME_MSK 0x000000ff
++#define RG_BB_11GN_RISE_TIME_I_MSK 0xffffff00
++#define RG_BB_11GN_RISE_TIME_SFT 0
++#define RG_BB_11GN_RISE_TIME_HI 7
++#define RG_BB_11GN_RISE_TIME_SZ 8
++#define RG_BB_11GN_FALL_TIME_MSK 0x0000ff00
++#define RG_BB_11GN_FALL_TIME_I_MSK 0xffff00ff
++#define RG_BB_11GN_FALL_TIME_SFT 8
++#define RG_BB_11GN_FALL_TIME_HI 15
++#define RG_BB_11GN_FALL_TIME_SZ 8
++#define RG_HTCARR52_FFT_SCALE_MSK 0x000003ff
++#define RG_HTCARR52_FFT_SCALE_I_MSK 0xfffffc00
++#define RG_HTCARR52_FFT_SCALE_SFT 0
++#define RG_HTCARR52_FFT_SCALE_HI 9
++#define RG_HTCARR52_FFT_SCALE_SZ 10
++#define RG_HTCARR56_FFT_SCALE_MSK 0x003ff000
++#define RG_HTCARR56_FFT_SCALE_I_MSK 0xffc00fff
++#define RG_HTCARR56_FFT_SCALE_SFT 12
++#define RG_HTCARR56_FFT_SCALE_HI 21
++#define RG_HTCARR56_FFT_SCALE_SZ 10
++#define RG_PACKET_STAT_EN_MSK 0x00800000
++#define RG_PACKET_STAT_EN_I_MSK 0xff7fffff
++#define RG_PACKET_STAT_EN_SFT 23
++#define RG_PACKET_STAT_EN_HI 23
++#define RG_PACKET_STAT_EN_SZ 1
++#define RG_SMB_DEF_MSK 0x7f000000
++#define RG_SMB_DEF_I_MSK 0x80ffffff
++#define RG_SMB_DEF_SFT 24
++#define RG_SMB_DEF_HI 30
++#define RG_SMB_DEF_SZ 7
++#define RG_CONTINUOUS_DATA_11GN_MSK 0x80000000
++#define RG_CONTINUOUS_DATA_11GN_I_MSK 0x7fffffff
++#define RG_CONTINUOUS_DATA_11GN_SFT 31
++#define RG_CONTINUOUS_DATA_11GN_HI 31
++#define RG_CONTINUOUS_DATA_11GN_SZ 1
++#define RO_TX_CNT_R_MSK 0xffffffff
++#define RO_TX_CNT_R_I_MSK 0x00000000
++#define RO_TX_CNT_R_SFT 0
++#define RO_TX_CNT_R_HI 31
++#define RO_TX_CNT_R_SZ 32
++#define RO_PACKET_ERR_CNT_MSK 0x0000ffff
++#define RO_PACKET_ERR_CNT_I_MSK 0xffff0000
++#define RO_PACKET_ERR_CNT_SFT 0
++#define RO_PACKET_ERR_CNT_HI 15
++#define RO_PACKET_ERR_CNT_SZ 16
++#define RG_POS_DES_11GN_L_EXT_MSK 0x0000000f
++#define RG_POS_DES_11GN_L_EXT_I_MSK 0xfffffff0
++#define RG_POS_DES_11GN_L_EXT_SFT 0
++#define RG_POS_DES_11GN_L_EXT_HI 3
++#define RG_POS_DES_11GN_L_EXT_SZ 4
++#define RG_PRE_DES_11GN_DLY_MSK 0x000000f0
++#define RG_PRE_DES_11GN_DLY_I_MSK 0xffffff0f
++#define RG_PRE_DES_11GN_DLY_SFT 4
++#define RG_PRE_DES_11GN_DLY_HI 7
++#define RG_PRE_DES_11GN_DLY_SZ 4
++#define RG_TR_LPF_KI_G_T1_MSK 0x0000000f
++#define RG_TR_LPF_KI_G_T1_I_MSK 0xfffffff0
++#define RG_TR_LPF_KI_G_T1_SFT 0
++#define RG_TR_LPF_KI_G_T1_HI 3
++#define RG_TR_LPF_KI_G_T1_SZ 4
++#define RG_TR_LPF_KP_G_T1_MSK 0x000000f0
++#define RG_TR_LPF_KP_G_T1_I_MSK 0xffffff0f
++#define RG_TR_LPF_KP_G_T1_SFT 4
++#define RG_TR_LPF_KP_G_T1_HI 7
++#define RG_TR_LPF_KP_G_T1_SZ 4
++#define RG_TR_CNT_T1_MSK 0x0000ff00
++#define RG_TR_CNT_T1_I_MSK 0xffff00ff
++#define RG_TR_CNT_T1_SFT 8
++#define RG_TR_CNT_T1_HI 15
++#define RG_TR_CNT_T1_SZ 8
++#define RG_TR_LPF_KI_G_T0_MSK 0x000f0000
++#define RG_TR_LPF_KI_G_T0_I_MSK 0xfff0ffff
++#define RG_TR_LPF_KI_G_T0_SFT 16
++#define RG_TR_LPF_KI_G_T0_HI 19
++#define RG_TR_LPF_KI_G_T0_SZ 4
++#define RG_TR_LPF_KP_G_T0_MSK 0x00f00000
++#define RG_TR_LPF_KP_G_T0_I_MSK 0xff0fffff
++#define RG_TR_LPF_KP_G_T0_SFT 20
++#define RG_TR_LPF_KP_G_T0_HI 23
++#define RG_TR_LPF_KP_G_T0_SZ 4
++#define RG_TR_CNT_T0_MSK 0xff000000
++#define RG_TR_CNT_T0_I_MSK 0x00ffffff
++#define RG_TR_CNT_T0_SFT 24
++#define RG_TR_CNT_T0_HI 31
++#define RG_TR_CNT_T0_SZ 8
++#define RG_TR_LPF_KI_G_T2_MSK 0x0000000f
++#define RG_TR_LPF_KI_G_T2_I_MSK 0xfffffff0
++#define RG_TR_LPF_KI_G_T2_SFT 0
++#define RG_TR_LPF_KI_G_T2_HI 3
++#define RG_TR_LPF_KI_G_T2_SZ 4
++#define RG_TR_LPF_KP_G_T2_MSK 0x000000f0
++#define RG_TR_LPF_KP_G_T2_I_MSK 0xffffff0f
++#define RG_TR_LPF_KP_G_T2_SFT 4
++#define RG_TR_LPF_KP_G_T2_HI 7
++#define RG_TR_LPF_KP_G_T2_SZ 4
++#define RG_TR_CNT_T2_MSK 0x0000ff00
++#define RG_TR_CNT_T2_I_MSK 0xffff00ff
++#define RG_TR_CNT_T2_SFT 8
++#define RG_TR_CNT_T2_HI 15
++#define RG_TR_CNT_T2_SZ 8
++#define RG_TR_LPF_KI_G_MSK 0x0000000f
++#define RG_TR_LPF_KI_G_I_MSK 0xfffffff0
++#define RG_TR_LPF_KI_G_SFT 0
++#define RG_TR_LPF_KI_G_HI 3
++#define RG_TR_LPF_KI_G_SZ 4
++#define RG_TR_LPF_KP_G_MSK 0x000000f0
++#define RG_TR_LPF_KP_G_I_MSK 0xffffff0f
++#define RG_TR_LPF_KP_G_SFT 4
++#define RG_TR_LPF_KP_G_HI 7
++#define RG_TR_LPF_KP_G_SZ 4
++#define RG_TR_LPF_RATE_G_MSK 0x3fffff00
++#define RG_TR_LPF_RATE_G_I_MSK 0xc00000ff
++#define RG_TR_LPF_RATE_G_SFT 8
++#define RG_TR_LPF_RATE_G_HI 29
++#define RG_TR_LPF_RATE_G_SZ 22
++#define RG_CR_LPF_KI_G_MSK 0x00000007
++#define RG_CR_LPF_KI_G_I_MSK 0xfffffff8
++#define RG_CR_LPF_KI_G_SFT 0
++#define RG_CR_LPF_KI_G_HI 2
++#define RG_CR_LPF_KI_G_SZ 3
++#define RG_SYM_BOUND_CNT_MSK 0x00007f00
++#define RG_SYM_BOUND_CNT_I_MSK 0xffff80ff
++#define RG_SYM_BOUND_CNT_SFT 8
++#define RG_SYM_BOUND_CNT_HI 14
++#define RG_SYM_BOUND_CNT_SZ 7
++#define RG_XSCOR32_RATIO_MSK 0x007f0000
++#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff
++#define RG_XSCOR32_RATIO_SFT 16
++#define RG_XSCOR32_RATIO_HI 22
++#define RG_XSCOR32_RATIO_SZ 7
++#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000
++#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff
++#define RG_ATCOR64_CNT_LMT_SFT 24
++#define RG_ATCOR64_CNT_LMT_HI 30
++#define RG_ATCOR64_CNT_LMT_SZ 7
++#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00
++#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff
++#define RG_ATCOR16_CNT_LMT2_SFT 8
++#define RG_ATCOR16_CNT_LMT2_HI 14
++#define RG_ATCOR16_CNT_LMT2_SZ 7
++#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000
++#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff
++#define RG_ATCOR16_CNT_LMT1_SFT 16
++#define RG_ATCOR16_CNT_LMT1_HI 22
++#define RG_ATCOR16_CNT_LMT1_SZ 7
++#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000
++#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff
++#define RG_ATCOR16_RATIO_SB_SFT 24
++#define RG_ATCOR16_RATIO_SB_HI 30
++#define RG_ATCOR16_RATIO_SB_SZ 7
++#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000
++#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff
++#define RG_XSCOR64_CNT_LMT2_SFT 16
++#define RG_XSCOR64_CNT_LMT2_HI 22
++#define RG_XSCOR64_CNT_LMT2_SZ 7
++#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000
++#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff
++#define RG_XSCOR64_CNT_LMT1_SFT 24
++#define RG_XSCOR64_CNT_LMT1_HI 30
++#define RG_XSCOR64_CNT_LMT1_SZ 7
++#define RG_RX_FFT_SCALE_MSK 0x000003ff
++#define RG_RX_FFT_SCALE_I_MSK 0xfffffc00
++#define RG_RX_FFT_SCALE_SFT 0
++#define RG_RX_FFT_SCALE_HI 9
++#define RG_RX_FFT_SCALE_SZ 10
++#define RG_VITERBI_AB_SWAP_MSK 0x00010000
++#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff
++#define RG_VITERBI_AB_SWAP_SFT 16
++#define RG_VITERBI_AB_SWAP_HI 16
++#define RG_VITERBI_AB_SWAP_SZ 1
++#define RG_ATCOR16_CNT_TH_MSK 0x0f000000
++#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff
++#define RG_ATCOR16_CNT_TH_SFT 24
++#define RG_ATCOR16_CNT_TH_HI 27
++#define RG_ATCOR16_CNT_TH_SZ 4
++#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff
++#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00
++#define RG_NORMSQUARE_LOW_SNR_7_SFT 0
++#define RG_NORMSQUARE_LOW_SNR_7_HI 7
++#define RG_NORMSQUARE_LOW_SNR_7_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00
++#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff
++#define RG_NORMSQUARE_LOW_SNR_6_SFT 8
++#define RG_NORMSQUARE_LOW_SNR_6_HI 15
++#define RG_NORMSQUARE_LOW_SNR_6_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000
++#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff
++#define RG_NORMSQUARE_LOW_SNR_5_SFT 16
++#define RG_NORMSQUARE_LOW_SNR_5_HI 23
++#define RG_NORMSQUARE_LOW_SNR_5_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000
++#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_LOW_SNR_4_SFT 24
++#define RG_NORMSQUARE_LOW_SNR_4_HI 31
++#define RG_NORMSQUARE_LOW_SNR_4_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000
++#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_LOW_SNR_8_SFT 24
++#define RG_NORMSQUARE_LOW_SNR_8_HI 31
++#define RG_NORMSQUARE_LOW_SNR_8_SZ 8
++#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff
++#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00
++#define RG_NORMSQUARE_SNR_3_SFT 0
++#define RG_NORMSQUARE_SNR_3_HI 7
++#define RG_NORMSQUARE_SNR_3_SZ 8
++#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00
++#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff
++#define RG_NORMSQUARE_SNR_2_SFT 8
++#define RG_NORMSQUARE_SNR_2_HI 15
++#define RG_NORMSQUARE_SNR_2_SZ 8
++#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000
++#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff
++#define RG_NORMSQUARE_SNR_1_SFT 16
++#define RG_NORMSQUARE_SNR_1_HI 23
++#define RG_NORMSQUARE_SNR_1_SZ 8
++#define RG_NORMSQUARE_SNR_0_MSK 0xff000000
++#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_SNR_0_SFT 24
++#define RG_NORMSQUARE_SNR_0_HI 31
++#define RG_NORMSQUARE_SNR_0_SZ 8
++#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff
++#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00
++#define RG_NORMSQUARE_SNR_7_SFT 0
++#define RG_NORMSQUARE_SNR_7_HI 7
++#define RG_NORMSQUARE_SNR_7_SZ 8
++#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00
++#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff
++#define RG_NORMSQUARE_SNR_6_SFT 8
++#define RG_NORMSQUARE_SNR_6_HI 15
++#define RG_NORMSQUARE_SNR_6_SZ 8
++#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000
++#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff
++#define RG_NORMSQUARE_SNR_5_SFT 16
++#define RG_NORMSQUARE_SNR_5_HI 23
++#define RG_NORMSQUARE_SNR_5_SZ 8
++#define RG_NORMSQUARE_SNR_4_MSK 0xff000000
++#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_SNR_4_SFT 24
++#define RG_NORMSQUARE_SNR_4_HI 31
++#define RG_NORMSQUARE_SNR_4_SZ 8
++#define RG_NORMSQUARE_SNR_8_MSK 0xff000000
++#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_SNR_8_SFT 24
++#define RG_NORMSQUARE_SNR_8_HI 31
++#define RG_NORMSQUARE_SNR_8_SZ 8
++#define RG_SNR_TH_64QAM_MSK 0x0000007f
++#define RG_SNR_TH_64QAM_I_MSK 0xffffff80
++#define RG_SNR_TH_64QAM_SFT 0
++#define RG_SNR_TH_64QAM_HI 6
++#define RG_SNR_TH_64QAM_SZ 7
++#define RG_SNR_TH_16QAM_MSK 0x00007f00
++#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff
++#define RG_SNR_TH_16QAM_SFT 8
++#define RG_SNR_TH_16QAM_HI 14
++#define RG_SNR_TH_16QAM_SZ 7
++#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f
++#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80
++#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0
++#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6
++#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7
++#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00
++#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff
++#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8
++#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14
++#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7
++#define RG_SYM_BOUND_METHOD_MSK 0x00030000
++#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff
++#define RG_SYM_BOUND_METHOD_SFT 16
++#define RG_SYM_BOUND_METHOD_HI 17
++#define RG_SYM_BOUND_METHOD_SZ 2
++#define RG_PWRON_DLY_TH_11GN_MSK 0x000000ff
++#define RG_PWRON_DLY_TH_11GN_I_MSK 0xffffff00
++#define RG_PWRON_DLY_TH_11GN_SFT 0
++#define RG_PWRON_DLY_TH_11GN_HI 7
++#define RG_PWRON_DLY_TH_11GN_SZ 8
++#define RG_SB_START_CNT_MSK 0x00007f00
++#define RG_SB_START_CNT_I_MSK 0xffff80ff
++#define RG_SB_START_CNT_SFT 8
++#define RG_SB_START_CNT_HI 14
++#define RG_SB_START_CNT_SZ 7
++#define RG_POW16_CNT_TH_MSK 0x000000f0
++#define RG_POW16_CNT_TH_I_MSK 0xffffff0f
++#define RG_POW16_CNT_TH_SFT 4
++#define RG_POW16_CNT_TH_HI 7
++#define RG_POW16_CNT_TH_SZ 4
++#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700
++#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff
++#define RG_POW16_SHORT_CNT_LMT_SFT 8
++#define RG_POW16_SHORT_CNT_LMT_HI 10
++#define RG_POW16_SHORT_CNT_LMT_SZ 3
++#define RG_POW16_TH_L_MSK 0x7f000000
++#define RG_POW16_TH_L_I_MSK 0x80ffffff
++#define RG_POW16_TH_L_SFT 24
++#define RG_POW16_TH_L_HI 30
++#define RG_POW16_TH_L_SZ 7
++#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007
++#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8
++#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0
++#define RG_XSCOR16_SHORT_CNT_LMT_HI 2
++#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3
++#define RG_XSCOR16_RATIO_MSK 0x00007f00
++#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff
++#define RG_XSCOR16_RATIO_SFT 8
++#define RG_XSCOR16_RATIO_HI 14
++#define RG_XSCOR16_RATIO_SZ 7
++#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000
++#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff
++#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16
++#define RG_ATCOR16_SHORT_CNT_LMT_HI 18
++#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3
++#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000
++#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff
++#define RG_ATCOR16_RATIO_CCD_SFT 24
++#define RG_ATCOR16_RATIO_CCD_HI 30
++#define RG_ATCOR16_RATIO_CCD_SZ 7
++#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f
++#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80
++#define RG_ATCOR64_ACC_LMT_SFT 0
++#define RG_ATCOR64_ACC_LMT_HI 6
++#define RG_ATCOR64_ACC_LMT_SZ 7
++#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000
++#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff
++#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16
++#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18
++#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3
++#define RG_VITERBI_TB_BITS_MSK 0xff000000
++#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff
++#define RG_VITERBI_TB_BITS_SFT 24
++#define RG_VITERBI_TB_BITS_HI 31
++#define RG_VITERBI_TB_BITS_SZ 8
++#define RG_CR_CNT_UPDATE_MSK 0x000000ff
++#define RG_CR_CNT_UPDATE_I_MSK 0xffffff00
++#define RG_CR_CNT_UPDATE_SFT 0
++#define RG_CR_CNT_UPDATE_HI 7
++#define RG_CR_CNT_UPDATE_SZ 8
++#define RG_TR_CNT_UPDATE_MSK 0x00ff0000
++#define RG_TR_CNT_UPDATE_I_MSK 0xff00ffff
++#define RG_TR_CNT_UPDATE_SFT 16
++#define RG_TR_CNT_UPDATE_HI 23
++#define RG_TR_CNT_UPDATE_SZ 8
++#define RG_BYPASS_CPE_MA_MSK 0x00000010
++#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef
++#define RG_BYPASS_CPE_MA_SFT 4
++#define RG_BYPASS_CPE_MA_HI 4
++#define RG_BYPASS_CPE_MA_SZ 1
++#define RG_PILOT_BNDRY_SHIFT_MSK 0x00000700
++#define RG_PILOT_BNDRY_SHIFT_I_MSK 0xfffff8ff
++#define RG_PILOT_BNDRY_SHIFT_SFT 8
++#define RG_PILOT_BNDRY_SHIFT_HI 10
++#define RG_PILOT_BNDRY_SHIFT_SZ 3
++#define RG_EQ_SHORT_GI_SHIFT_MSK 0x00007000
++#define RG_EQ_SHORT_GI_SHIFT_I_MSK 0xffff8fff
++#define RG_EQ_SHORT_GI_SHIFT_SFT 12
++#define RG_EQ_SHORT_GI_SHIFT_HI 14
++#define RG_EQ_SHORT_GI_SHIFT_SZ 3
++#define RG_FFT_WDW_SHORT_SHIFT_MSK 0x00070000
++#define RG_FFT_WDW_SHORT_SHIFT_I_MSK 0xfff8ffff
++#define RG_FFT_WDW_SHORT_SHIFT_SFT 16
++#define RG_FFT_WDW_SHORT_SHIFT_HI 18
++#define RG_FFT_WDW_SHORT_SHIFT_SZ 3
++#define RG_CHSMTH_COEF_MSK 0x00030000
++#define RG_CHSMTH_COEF_I_MSK 0xfffcffff
++#define RG_CHSMTH_COEF_SFT 16
++#define RG_CHSMTH_COEF_HI 17
++#define RG_CHSMTH_COEF_SZ 2
++#define RG_CHSMTH_EN_MSK 0x00040000
++#define RG_CHSMTH_EN_I_MSK 0xfffbffff
++#define RG_CHSMTH_EN_SFT 18
++#define RG_CHSMTH_EN_HI 18
++#define RG_CHSMTH_EN_SZ 1
++#define RG_CHEST_DD_FACTOR_MSK 0x07000000
++#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff
++#define RG_CHEST_DD_FACTOR_SFT 24
++#define RG_CHEST_DD_FACTOR_HI 26
++#define RG_CHEST_DD_FACTOR_SZ 3
++#define RG_CH_UPDATE_MSK 0x80000000
++#define RG_CH_UPDATE_I_MSK 0x7fffffff
++#define RG_CH_UPDATE_SFT 31
++#define RG_CH_UPDATE_HI 31
++#define RG_CH_UPDATE_SZ 1
++#define RG_FMT_DET_MM_TH_MSK 0x000000ff
++#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00
++#define RG_FMT_DET_MM_TH_SFT 0
++#define RG_FMT_DET_MM_TH_HI 7
++#define RG_FMT_DET_MM_TH_SZ 8
++#define RG_FMT_DET_GF_TH_MSK 0x0000ff00
++#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff
++#define RG_FMT_DET_GF_TH_SFT 8
++#define RG_FMT_DET_GF_TH_HI 15
++#define RG_FMT_DET_GF_TH_SZ 8
++#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000
++#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff
++#define RG_DO_NOT_CHECK_L_RATE_SFT 25
++#define RG_DO_NOT_CHECK_L_RATE_HI 25
++#define RG_DO_NOT_CHECK_L_RATE_SZ 1
++#define RG_FMT_DET_LENGTH_TH_MSK 0x0000ffff
++#define RG_FMT_DET_LENGTH_TH_I_MSK 0xffff0000
++#define RG_FMT_DET_LENGTH_TH_SFT 0
++#define RG_FMT_DET_LENGTH_TH_HI 15
++#define RG_FMT_DET_LENGTH_TH_SZ 16
++#define RG_L_LENGTH_MAX_MSK 0xffff0000
++#define RG_L_LENGTH_MAX_I_MSK 0x0000ffff
++#define RG_L_LENGTH_MAX_SFT 16
++#define RG_L_LENGTH_MAX_HI 31
++#define RG_L_LENGTH_MAX_SZ 16
++#define RG_TX_TIME_EXT_MSK 0x000000ff
++#define RG_TX_TIME_EXT_I_MSK 0xffffff00
++#define RG_TX_TIME_EXT_SFT 0
++#define RG_TX_TIME_EXT_HI 7
++#define RG_TX_TIME_EXT_SZ 8
++#define RG_MAC_DES_SPACE_MSK 0x00f00000
++#define RG_MAC_DES_SPACE_I_MSK 0xff0fffff
++#define RG_MAC_DES_SPACE_SFT 20
++#define RG_MAC_DES_SPACE_HI 23
++#define RG_MAC_DES_SPACE_SZ 4
++#define RG_TR_LPF_STBC_GF_KI_G_MSK 0x0000000f
++#define RG_TR_LPF_STBC_GF_KI_G_I_MSK 0xfffffff0
++#define RG_TR_LPF_STBC_GF_KI_G_SFT 0
++#define RG_TR_LPF_STBC_GF_KI_G_HI 3
++#define RG_TR_LPF_STBC_GF_KI_G_SZ 4
++#define RG_TR_LPF_STBC_GF_KP_G_MSK 0x000000f0
++#define RG_TR_LPF_STBC_GF_KP_G_I_MSK 0xffffff0f
++#define RG_TR_LPF_STBC_GF_KP_G_SFT 4
++#define RG_TR_LPF_STBC_GF_KP_G_HI 7
++#define RG_TR_LPF_STBC_GF_KP_G_SZ 4
++#define RG_TR_LPF_STBC_MF_KI_G_MSK 0x00000f00
++#define RG_TR_LPF_STBC_MF_KI_G_I_MSK 0xfffff0ff
++#define RG_TR_LPF_STBC_MF_KI_G_SFT 8
++#define RG_TR_LPF_STBC_MF_KI_G_HI 11
++#define RG_TR_LPF_STBC_MF_KI_G_SZ 4
++#define RG_TR_LPF_STBC_MF_KP_G_MSK 0x0000f000
++#define RG_TR_LPF_STBC_MF_KP_G_I_MSK 0xffff0fff
++#define RG_TR_LPF_STBC_MF_KP_G_SFT 12
++#define RG_TR_LPF_STBC_MF_KP_G_HI 15
++#define RG_TR_LPF_STBC_MF_KP_G_SZ 4
++#define RG_MODE_REG_IN_80_MSK 0x0001ffff
++#define RG_MODE_REG_IN_80_I_MSK 0xfffe0000
++#define RG_MODE_REG_IN_80_SFT 0
++#define RG_MODE_REG_IN_80_HI 16
++#define RG_MODE_REG_IN_80_SZ 17
++#define RG_PARALLEL_DR_80_MSK 0x00100000
++#define RG_PARALLEL_DR_80_I_MSK 0xffefffff
++#define RG_PARALLEL_DR_80_SFT 20
++#define RG_PARALLEL_DR_80_HI 20
++#define RG_PARALLEL_DR_80_SZ 1
++#define RG_MBRUN_80_MSK 0x01000000
++#define RG_MBRUN_80_I_MSK 0xfeffffff
++#define RG_MBRUN_80_SFT 24
++#define RG_MBRUN_80_HI 24
++#define RG_MBRUN_80_SZ 1
++#define RG_SHIFT_DR_80_MSK 0x10000000
++#define RG_SHIFT_DR_80_I_MSK 0xefffffff
++#define RG_SHIFT_DR_80_SFT 28
++#define RG_SHIFT_DR_80_HI 28
++#define RG_SHIFT_DR_80_SZ 1
++#define RG_MODE_REG_SI_80_MSK 0x20000000
++#define RG_MODE_REG_SI_80_I_MSK 0xdfffffff
++#define RG_MODE_REG_SI_80_SFT 29
++#define RG_MODE_REG_SI_80_HI 29
++#define RG_MODE_REG_SI_80_SZ 1
++#define RG_SIMULATION_MODE_80_MSK 0x40000000
++#define RG_SIMULATION_MODE_80_I_MSK 0xbfffffff
++#define RG_SIMULATION_MODE_80_SFT 30
++#define RG_SIMULATION_MODE_80_HI 30
++#define RG_SIMULATION_MODE_80_SZ 1
++#define RG_DBIST_MODE_80_MSK 0x80000000
++#define RG_DBIST_MODE_80_I_MSK 0x7fffffff
++#define RG_DBIST_MODE_80_SFT 31
++#define RG_DBIST_MODE_80_HI 31
++#define RG_DBIST_MODE_80_SZ 1
++#define RG_MODE_REG_IN_64_MSK 0x0000ffff
++#define RG_MODE_REG_IN_64_I_MSK 0xffff0000
++#define RG_MODE_REG_IN_64_SFT 0
++#define RG_MODE_REG_IN_64_HI 15
++#define RG_MODE_REG_IN_64_SZ 16
++#define RG_PARALLEL_DR_64_MSK 0x00100000
++#define RG_PARALLEL_DR_64_I_MSK 0xffefffff
++#define RG_PARALLEL_DR_64_SFT 20
++#define RG_PARALLEL_DR_64_HI 20
++#define RG_PARALLEL_DR_64_SZ 1
++#define RG_MBRUN_64_MSK 0x01000000
++#define RG_MBRUN_64_I_MSK 0xfeffffff
++#define RG_MBRUN_64_SFT 24
++#define RG_MBRUN_64_HI 24
++#define RG_MBRUN_64_SZ 1
++#define RG_SHIFT_DR_64_MSK 0x10000000
++#define RG_SHIFT_DR_64_I_MSK 0xefffffff
++#define RG_SHIFT_DR_64_SFT 28
++#define RG_SHIFT_DR_64_HI 28
++#define RG_SHIFT_DR_64_SZ 1
++#define RG_MODE_REG_SI_64_MSK 0x20000000
++#define RG_MODE_REG_SI_64_I_MSK 0xdfffffff
++#define RG_MODE_REG_SI_64_SFT 29
++#define RG_MODE_REG_SI_64_HI 29
++#define RG_MODE_REG_SI_64_SZ 1
++#define RG_SIMULATION_MODE_64_MSK 0x40000000
++#define RG_SIMULATION_MODE_64_I_MSK 0xbfffffff
++#define RG_SIMULATION_MODE_64_SFT 30
++#define RG_SIMULATION_MODE_64_HI 30
++#define RG_SIMULATION_MODE_64_SZ 1
++#define RG_DBIST_MODE_64_MSK 0x80000000
++#define RG_DBIST_MODE_64_I_MSK 0x7fffffff
++#define RG_DBIST_MODE_64_SFT 31
++#define RG_DBIST_MODE_64_HI 31
++#define RG_DBIST_MODE_64_SZ 1
++#define RO_MODE_REG_OUT_80_MSK 0x0001ffff
++#define RO_MODE_REG_OUT_80_I_MSK 0xfffe0000
++#define RO_MODE_REG_OUT_80_SFT 0
++#define RO_MODE_REG_OUT_80_HI 16
++#define RO_MODE_REG_OUT_80_SZ 17
++#define RO_MODE_REG_SO_80_MSK 0x01000000
++#define RO_MODE_REG_SO_80_I_MSK 0xfeffffff
++#define RO_MODE_REG_SO_80_SFT 24
++#define RO_MODE_REG_SO_80_HI 24
++#define RO_MODE_REG_SO_80_SZ 1
++#define RO_MONITOR_BUS_80_MSK 0x003fffff
++#define RO_MONITOR_BUS_80_I_MSK 0xffc00000
++#define RO_MONITOR_BUS_80_SFT 0
++#define RO_MONITOR_BUS_80_HI 21
++#define RO_MONITOR_BUS_80_SZ 22
++#define RO_MODE_REG_OUT_64_MSK 0x0000ffff
++#define RO_MODE_REG_OUT_64_I_MSK 0xffff0000
++#define RO_MODE_REG_OUT_64_SFT 0
++#define RO_MODE_REG_OUT_64_HI 15
++#define RO_MODE_REG_OUT_64_SZ 16
++#define RO_MODE_REG_SO_64_MSK 0x01000000
++#define RO_MODE_REG_SO_64_I_MSK 0xfeffffff
++#define RO_MODE_REG_SO_64_SFT 24
++#define RO_MODE_REG_SO_64_HI 24
++#define RO_MODE_REG_SO_64_SZ 1
++#define RO_MONITOR_BUS_64_MSK 0x0007ffff
++#define RO_MONITOR_BUS_64_I_MSK 0xfff80000
++#define RO_MONITOR_BUS_64_SFT 0
++#define RO_MONITOR_BUS_64_HI 18
++#define RO_MONITOR_BUS_64_SZ 19
++#define RO_SPECTRUM_DATA_MSK 0xffffffff
++#define RO_SPECTRUM_DATA_I_MSK 0x00000000
++#define RO_SPECTRUM_DATA_SFT 0
++#define RO_SPECTRUM_DATA_HI 31
++#define RO_SPECTRUM_DATA_SZ 32
++#define GN_SNR_MSK 0x0000007f
++#define GN_SNR_I_MSK 0xffffff80
++#define GN_SNR_SFT 0
++#define GN_SNR_HI 6
++#define GN_SNR_SZ 7
++#define GN_NOISE_PWR_MSK 0x00007f00
++#define GN_NOISE_PWR_I_MSK 0xffff80ff
++#define GN_NOISE_PWR_SFT 8
++#define GN_NOISE_PWR_HI 14
++#define GN_NOISE_PWR_SZ 7
++#define GN_RCPI_MSK 0x007f0000
++#define GN_RCPI_I_MSK 0xff80ffff
++#define GN_RCPI_SFT 16
++#define GN_RCPI_HI 22
++#define GN_RCPI_SZ 7
++#define GN_SIGNAL_PWR_MSK 0x7f000000
++#define GN_SIGNAL_PWR_I_MSK 0x80ffffff
++#define GN_SIGNAL_PWR_SFT 24
++#define GN_SIGNAL_PWR_HI 30
++#define GN_SIGNAL_PWR_SZ 7
++#define RO_FREQ_OS_LTS_MSK 0x00007fff
++#define RO_FREQ_OS_LTS_I_MSK 0xffff8000
++#define RO_FREQ_OS_LTS_SFT 0
++#define RO_FREQ_OS_LTS_HI 14
++#define RO_FREQ_OS_LTS_SZ 15
++#define CSTATE_MSK 0x000f0000
++#define CSTATE_I_MSK 0xfff0ffff
++#define CSTATE_SFT 16
++#define CSTATE_HI 19
++#define CSTATE_SZ 4
++#define SIGNAL_FIELD0_MSK 0x00ffffff
++#define SIGNAL_FIELD0_I_MSK 0xff000000
++#define SIGNAL_FIELD0_SFT 0
++#define SIGNAL_FIELD0_HI 23
++#define SIGNAL_FIELD0_SZ 24
++#define SIGNAL_FIELD1_MSK 0x00ffffff
++#define SIGNAL_FIELD1_I_MSK 0xff000000
++#define SIGNAL_FIELD1_SFT 0
++#define SIGNAL_FIELD1_HI 23
++#define SIGNAL_FIELD1_SZ 24
++#define GN_PACKET_ERR_CNT_MSK 0x0000ffff
++#define GN_PACKET_ERR_CNT_I_MSK 0xffff0000
++#define GN_PACKET_ERR_CNT_SFT 0
++#define GN_PACKET_ERR_CNT_HI 15
++#define GN_PACKET_ERR_CNT_SZ 16
++#define GN_PACKET_CNT_MSK 0x0000ffff
++#define GN_PACKET_CNT_I_MSK 0xffff0000
++#define GN_PACKET_CNT_SFT 0
++#define GN_PACKET_CNT_HI 15
++#define GN_PACKET_CNT_SZ 16
++#define GN_CCA_CNT_MSK 0xffff0000
++#define GN_CCA_CNT_I_MSK 0x0000ffff
++#define GN_CCA_CNT_SFT 16
++#define GN_CCA_CNT_HI 31
++#define GN_CCA_CNT_SZ 16
++#define GN_LENGTH_FIELD_MSK 0x0000ffff
++#define GN_LENGTH_FIELD_I_MSK 0xffff0000
++#define GN_LENGTH_FIELD_SFT 0
++#define GN_LENGTH_FIELD_HI 15
++#define GN_LENGTH_FIELD_SZ 16
++#define GN_SERVICE_FIELD_MSK 0xffff0000
++#define GN_SERVICE_FIELD_I_MSK 0x0000ffff
++#define GN_SERVICE_FIELD_SFT 16
++#define GN_SERVICE_FIELD_HI 31
++#define GN_SERVICE_FIELD_SZ 16
++#define RO_HT_MCS_40M_MSK 0x0000007f
++#define RO_HT_MCS_40M_I_MSK 0xffffff80
++#define RO_HT_MCS_40M_SFT 0
++#define RO_HT_MCS_40M_HI 6
++#define RO_HT_MCS_40M_SZ 7
++#define RO_L_RATE_40M_MSK 0x00003f00
++#define RO_L_RATE_40M_I_MSK 0xffffc0ff
++#define RO_L_RATE_40M_SFT 8
++#define RO_L_RATE_40M_HI 13
++#define RO_L_RATE_40M_SZ 6
++#define RG_DAGC_CNT_TH_MSK 0x00000003
++#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc
++#define RG_DAGC_CNT_TH_SFT 0
++#define RG_DAGC_CNT_TH_HI 1
++#define RG_DAGC_CNT_TH_SZ 2
++#define RG_PACKET_STAT_EN_11GN_MSK 0x00100000
++#define RG_PACKET_STAT_EN_11GN_I_MSK 0xffefffff
++#define RG_PACKET_STAT_EN_11GN_SFT 20
++#define RG_PACKET_STAT_EN_11GN_HI 20
++#define RG_PACKET_STAT_EN_11GN_SZ 1
++#define RX_PHY_11GN_SOFT_RST_N_MSK 0x00000001
++#define RX_PHY_11GN_SOFT_RST_N_I_MSK 0xfffffffe
++#define RX_PHY_11GN_SOFT_RST_N_SFT 0
++#define RX_PHY_11GN_SOFT_RST_N_HI 0
++#define RX_PHY_11GN_SOFT_RST_N_SZ 1
++#define RG_RIFS_EN_MSK 0x00000002
++#define RG_RIFS_EN_I_MSK 0xfffffffd
++#define RG_RIFS_EN_SFT 1
++#define RG_RIFS_EN_HI 1
++#define RG_RIFS_EN_SZ 1
++#define RG_STBC_EN_MSK 0x00000004
++#define RG_STBC_EN_I_MSK 0xfffffffb
++#define RG_STBC_EN_SFT 2
++#define RG_STBC_EN_HI 2
++#define RG_STBC_EN_SZ 1
++#define RG_COR_SEL_MSK 0x00000008
++#define RG_COR_SEL_I_MSK 0xfffffff7
++#define RG_COR_SEL_SFT 3
++#define RG_COR_SEL_HI 3
++#define RG_COR_SEL_SZ 1
++#define RG_INI_PHASE_MSK 0x00000030
++#define RG_INI_PHASE_I_MSK 0xffffffcf
++#define RG_INI_PHASE_SFT 4
++#define RG_INI_PHASE_HI 5
++#define RG_INI_PHASE_SZ 2
++#define RG_HT_LTF_SEL_EQ_MSK 0x00000040
++#define RG_HT_LTF_SEL_EQ_I_MSK 0xffffffbf
++#define RG_HT_LTF_SEL_EQ_SFT 6
++#define RG_HT_LTF_SEL_EQ_HI 6
++#define RG_HT_LTF_SEL_EQ_SZ 1
++#define RG_HT_LTF_SEL_PILOT_MSK 0x00000080
++#define RG_HT_LTF_SEL_PILOT_I_MSK 0xffffff7f
++#define RG_HT_LTF_SEL_PILOT_SFT 7
++#define RG_HT_LTF_SEL_PILOT_HI 7
++#define RG_HT_LTF_SEL_PILOT_SZ 1
++#define RG_CCA_PWR_SEL_MSK 0x00000200
++#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff
++#define RG_CCA_PWR_SEL_SFT 9
++#define RG_CCA_PWR_SEL_HI 9
++#define RG_CCA_PWR_SEL_SZ 1
++#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400
++#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff
++#define RG_CCA_XSCOR_PWR_SEL_SFT 10
++#define RG_CCA_XSCOR_PWR_SEL_HI 10
++#define RG_CCA_XSCOR_PWR_SEL_SZ 1
++#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800
++#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff
++#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11
++#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11
++#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1
++#define RG_DEBUG_SEL_MSK 0x0000f000
++#define RG_DEBUG_SEL_I_MSK 0xffff0fff
++#define RG_DEBUG_SEL_SFT 12
++#define RG_DEBUG_SEL_HI 15
++#define RG_DEBUG_SEL_SZ 4
++#define RG_POST_CLK_EN_MSK 0x00010000
++#define RG_POST_CLK_EN_I_MSK 0xfffeffff
++#define RG_POST_CLK_EN_SFT 16
++#define RG_POST_CLK_EN_HI 16
++#define RG_POST_CLK_EN_SZ 1
++#define IQCAL_RF_TX_EN_MSK 0x00000001
++#define IQCAL_RF_TX_EN_I_MSK 0xfffffffe
++#define IQCAL_RF_TX_EN_SFT 0
++#define IQCAL_RF_TX_EN_HI 0
++#define IQCAL_RF_TX_EN_SZ 1
++#define IQCAL_RF_TX_PA_EN_MSK 0x00000002
++#define IQCAL_RF_TX_PA_EN_I_MSK 0xfffffffd
++#define IQCAL_RF_TX_PA_EN_SFT 1
++#define IQCAL_RF_TX_PA_EN_HI 1
++#define IQCAL_RF_TX_PA_EN_SZ 1
++#define IQCAL_RF_TX_DAC_EN_MSK 0x00000004
++#define IQCAL_RF_TX_DAC_EN_I_MSK 0xfffffffb
++#define IQCAL_RF_TX_DAC_EN_SFT 2
++#define IQCAL_RF_TX_DAC_EN_HI 2
++#define IQCAL_RF_TX_DAC_EN_SZ 1
++#define IQCAL_RF_RX_AGC_MSK 0x00000008
++#define IQCAL_RF_RX_AGC_I_MSK 0xfffffff7
++#define IQCAL_RF_RX_AGC_SFT 3
++#define IQCAL_RF_RX_AGC_HI 3
++#define IQCAL_RF_RX_AGC_SZ 1
++#define IQCAL_RF_PGAG_MSK 0x00000f00
++#define IQCAL_RF_PGAG_I_MSK 0xfffff0ff
++#define IQCAL_RF_PGAG_SFT 8
++#define IQCAL_RF_PGAG_HI 11
++#define IQCAL_RF_PGAG_SZ 4
++#define IQCAL_RF_RFG_MSK 0x00003000
++#define IQCAL_RF_RFG_I_MSK 0xffffcfff
++#define IQCAL_RF_RFG_SFT 12
++#define IQCAL_RF_RFG_HI 13
++#define IQCAL_RF_RFG_SZ 2
++#define RG_TONEGEN_FREQ_MSK 0x007f0000
++#define RG_TONEGEN_FREQ_I_MSK 0xff80ffff
++#define RG_TONEGEN_FREQ_SFT 16
++#define RG_TONEGEN_FREQ_HI 22
++#define RG_TONEGEN_FREQ_SZ 7
++#define RG_TONEGEN_EN_MSK 0x00800000
++#define RG_TONEGEN_EN_I_MSK 0xff7fffff
++#define RG_TONEGEN_EN_SFT 23
++#define RG_TONEGEN_EN_HI 23
++#define RG_TONEGEN_EN_SZ 1
++#define RG_TONEGEN_INIT_PH_MSK 0x7f000000
++#define RG_TONEGEN_INIT_PH_I_MSK 0x80ffffff
++#define RG_TONEGEN_INIT_PH_SFT 24
++#define RG_TONEGEN_INIT_PH_HI 30
++#define RG_TONEGEN_INIT_PH_SZ 7
++#define RG_TONEGEN2_FREQ_MSK 0x0000007f
++#define RG_TONEGEN2_FREQ_I_MSK 0xffffff80
++#define RG_TONEGEN2_FREQ_SFT 0
++#define RG_TONEGEN2_FREQ_HI 6
++#define RG_TONEGEN2_FREQ_SZ 7
++#define RG_TONEGEN2_EN_MSK 0x00000080
++#define RG_TONEGEN2_EN_I_MSK 0xffffff7f
++#define RG_TONEGEN2_EN_SFT 7
++#define RG_TONEGEN2_EN_HI 7
++#define RG_TONEGEN2_EN_SZ 1
++#define RG_TONEGEN2_SCALE_MSK 0x0000ff00
++#define RG_TONEGEN2_SCALE_I_MSK 0xffff00ff
++#define RG_TONEGEN2_SCALE_SFT 8
++#define RG_TONEGEN2_SCALE_HI 15
++#define RG_TONEGEN2_SCALE_SZ 8
++#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff
++#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00
++#define RG_TXIQ_CLP_THD_I_SFT 0
++#define RG_TXIQ_CLP_THD_I_HI 9
++#define RG_TXIQ_CLP_THD_I_SZ 10
++#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000
++#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff
++#define RG_TXIQ_CLP_THD_Q_SFT 16
++#define RG_TXIQ_CLP_THD_Q_HI 25
++#define RG_TXIQ_CLP_THD_Q_SZ 10
++#define RG_TX_I_SCALE_MSK 0x000000ff
++#define RG_TX_I_SCALE_I_MSK 0xffffff00
++#define RG_TX_I_SCALE_SFT 0
++#define RG_TX_I_SCALE_HI 7
++#define RG_TX_I_SCALE_SZ 8
++#define RG_TX_Q_SCALE_MSK 0x0000ff00
++#define RG_TX_Q_SCALE_I_MSK 0xffff00ff
++#define RG_TX_Q_SCALE_SFT 8
++#define RG_TX_Q_SCALE_HI 15
++#define RG_TX_Q_SCALE_SZ 8
++#define RG_TX_IQ_SWP_MSK 0x00010000
++#define RG_TX_IQ_SWP_I_MSK 0xfffeffff
++#define RG_TX_IQ_SWP_SFT 16
++#define RG_TX_IQ_SWP_HI 16
++#define RG_TX_IQ_SWP_SZ 1
++#define RG_TX_SGN_OUT_MSK 0x00020000
++#define RG_TX_SGN_OUT_I_MSK 0xfffdffff
++#define RG_TX_SGN_OUT_SFT 17
++#define RG_TX_SGN_OUT_HI 17
++#define RG_TX_SGN_OUT_SZ 1
++#define RG_TXIQ_EMU_IDX_MSK 0x003c0000
++#define RG_TXIQ_EMU_IDX_I_MSK 0xffc3ffff
++#define RG_TXIQ_EMU_IDX_SFT 18
++#define RG_TXIQ_EMU_IDX_HI 21
++#define RG_TXIQ_EMU_IDX_SZ 4
++#define RG_TX_IQ_SRC_MSK 0x03000000
++#define RG_TX_IQ_SRC_I_MSK 0xfcffffff
++#define RG_TX_IQ_SRC_SFT 24
++#define RG_TX_IQ_SRC_HI 25
++#define RG_TX_IQ_SRC_SZ 2
++#define RG_TX_I_DC_MSK 0x000003ff
++#define RG_TX_I_DC_I_MSK 0xfffffc00
++#define RG_TX_I_DC_SFT 0
++#define RG_TX_I_DC_HI 9
++#define RG_TX_I_DC_SZ 10
++#define RG_TX_Q_DC_MSK 0x03ff0000
++#define RG_TX_Q_DC_I_MSK 0xfc00ffff
++#define RG_TX_Q_DC_SFT 16
++#define RG_TX_Q_DC_HI 25
++#define RG_TX_Q_DC_SZ 10
++#define RG_TX_IQ_THETA_MSK 0x0000001f
++#define RG_TX_IQ_THETA_I_MSK 0xffffffe0
++#define RG_TX_IQ_THETA_SFT 0
++#define RG_TX_IQ_THETA_HI 4
++#define RG_TX_IQ_THETA_SZ 5
++#define RG_TX_IQ_ALPHA_MSK 0x00001f00
++#define RG_TX_IQ_ALPHA_I_MSK 0xffffe0ff
++#define RG_TX_IQ_ALPHA_SFT 8
++#define RG_TX_IQ_ALPHA_HI 12
++#define RG_TX_IQ_ALPHA_SZ 5
++#define RG_TXIQ_NOSHRINK_MSK 0x00002000
++#define RG_TXIQ_NOSHRINK_I_MSK 0xffffdfff
++#define RG_TXIQ_NOSHRINK_SFT 13
++#define RG_TXIQ_NOSHRINK_HI 13
++#define RG_TXIQ_NOSHRINK_SZ 1
++#define RG_TX_I_OFFSET_MSK 0x00ff0000
++#define RG_TX_I_OFFSET_I_MSK 0xff00ffff
++#define RG_TX_I_OFFSET_SFT 16
++#define RG_TX_I_OFFSET_HI 23
++#define RG_TX_I_OFFSET_SZ 8
++#define RG_TX_Q_OFFSET_MSK 0xff000000
++#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff
++#define RG_TX_Q_OFFSET_SFT 24
++#define RG_TX_Q_OFFSET_HI 31
++#define RG_TX_Q_OFFSET_SZ 8
++#define RG_RX_IQ_THETA_MSK 0x0000001f
++#define RG_RX_IQ_THETA_I_MSK 0xffffffe0
++#define RG_RX_IQ_THETA_SFT 0
++#define RG_RX_IQ_THETA_HI 4
++#define RG_RX_IQ_THETA_SZ 5
++#define RG_RX_IQ_ALPHA_MSK 0x00001f00
++#define RG_RX_IQ_ALPHA_I_MSK 0xffffe0ff
++#define RG_RX_IQ_ALPHA_SFT 8
++#define RG_RX_IQ_ALPHA_HI 12
++#define RG_RX_IQ_ALPHA_SZ 5
++#define RG_RXIQ_NOSHRINK_MSK 0x00002000
++#define RG_RXIQ_NOSHRINK_I_MSK 0xffffdfff
++#define RG_RXIQ_NOSHRINK_SFT 13
++#define RG_RXIQ_NOSHRINK_HI 13
++#define RG_RXIQ_NOSHRINK_SZ 1
++#define RG_MA_DPTH_MSK 0x0000000f
++#define RG_MA_DPTH_I_MSK 0xfffffff0
++#define RG_MA_DPTH_SFT 0
++#define RG_MA_DPTH_HI 3
++#define RG_MA_DPTH_SZ 4
++#define RG_INTG_PH_MSK 0x000003f0
++#define RG_INTG_PH_I_MSK 0xfffffc0f
++#define RG_INTG_PH_SFT 4
++#define RG_INTG_PH_HI 9
++#define RG_INTG_PH_SZ 6
++#define RG_INTG_PRD_MSK 0x00001c00
++#define RG_INTG_PRD_I_MSK 0xffffe3ff
++#define RG_INTG_PRD_SFT 10
++#define RG_INTG_PRD_HI 12
++#define RG_INTG_PRD_SZ 3
++#define RG_INTG_MU_MSK 0x00006000
++#define RG_INTG_MU_I_MSK 0xffff9fff
++#define RG_INTG_MU_SFT 13
++#define RG_INTG_MU_HI 14
++#define RG_INTG_MU_SZ 2
++#define RG_IQCAL_SPRM_SELQ_MSK 0x00010000
++#define RG_IQCAL_SPRM_SELQ_I_MSK 0xfffeffff
++#define RG_IQCAL_SPRM_SELQ_SFT 16
++#define RG_IQCAL_SPRM_SELQ_HI 16
++#define RG_IQCAL_SPRM_SELQ_SZ 1
++#define RG_IQCAL_SPRM_EN_MSK 0x00020000
++#define RG_IQCAL_SPRM_EN_I_MSK 0xfffdffff
++#define RG_IQCAL_SPRM_EN_SFT 17
++#define RG_IQCAL_SPRM_EN_HI 17
++#define RG_IQCAL_SPRM_EN_SZ 1
++#define RG_IQCAL_SPRM_FREQ_MSK 0x00fc0000
++#define RG_IQCAL_SPRM_FREQ_I_MSK 0xff03ffff
++#define RG_IQCAL_SPRM_FREQ_SFT 18
++#define RG_IQCAL_SPRM_FREQ_HI 23
++#define RG_IQCAL_SPRM_FREQ_SZ 6
++#define RG_IQCAL_IQCOL_EN_MSK 0x01000000
++#define RG_IQCAL_IQCOL_EN_I_MSK 0xfeffffff
++#define RG_IQCAL_IQCOL_EN_SFT 24
++#define RG_IQCAL_IQCOL_EN_HI 24
++#define RG_IQCAL_IQCOL_EN_SZ 1
++#define RG_IQCAL_ALPHA_ESTM_EN_MSK 0x02000000
++#define RG_IQCAL_ALPHA_ESTM_EN_I_MSK 0xfdffffff
++#define RG_IQCAL_ALPHA_ESTM_EN_SFT 25
++#define RG_IQCAL_ALPHA_ESTM_EN_HI 25
++#define RG_IQCAL_ALPHA_ESTM_EN_SZ 1
++#define RG_IQCAL_DC_EN_MSK 0x04000000
++#define RG_IQCAL_DC_EN_I_MSK 0xfbffffff
++#define RG_IQCAL_DC_EN_SFT 26
++#define RG_IQCAL_DC_EN_HI 26
++#define RG_IQCAL_DC_EN_SZ 1
++#define RG_PHEST_STBY_MSK 0x08000000
++#define RG_PHEST_STBY_I_MSK 0xf7ffffff
++#define RG_PHEST_STBY_SFT 27
++#define RG_PHEST_STBY_HI 27
++#define RG_PHEST_STBY_SZ 1
++#define RG_PHEST_EN_MSK 0x10000000
++#define RG_PHEST_EN_I_MSK 0xefffffff
++#define RG_PHEST_EN_SFT 28
++#define RG_PHEST_EN_HI 28
++#define RG_PHEST_EN_SZ 1
++#define RG_GP_DIV_EN_MSK 0x20000000
++#define RG_GP_DIV_EN_I_MSK 0xdfffffff
++#define RG_GP_DIV_EN_SFT 29
++#define RG_GP_DIV_EN_HI 29
++#define RG_GP_DIV_EN_SZ 1
++#define RG_DPD_GAIN_EST_EN_MSK 0x40000000
++#define RG_DPD_GAIN_EST_EN_I_MSK 0xbfffffff
++#define RG_DPD_GAIN_EST_EN_SFT 30
++#define RG_DPD_GAIN_EST_EN_HI 30
++#define RG_DPD_GAIN_EST_EN_SZ 1
++#define RG_IQCAL_MULT_OP0_MSK 0x000003ff
++#define RG_IQCAL_MULT_OP0_I_MSK 0xfffffc00
++#define RG_IQCAL_MULT_OP0_SFT 0
++#define RG_IQCAL_MULT_OP0_HI 9
++#define RG_IQCAL_MULT_OP0_SZ 10
++#define RG_IQCAL_MULT_OP1_MSK 0x03ff0000
++#define RG_IQCAL_MULT_OP1_I_MSK 0xfc00ffff
++#define RG_IQCAL_MULT_OP1_SFT 16
++#define RG_IQCAL_MULT_OP1_HI 25
++#define RG_IQCAL_MULT_OP1_SZ 10
++#define RO_IQCAL_O_MSK 0x000fffff
++#define RO_IQCAL_O_I_MSK 0xfff00000
++#define RO_IQCAL_O_SFT 0
++#define RO_IQCAL_O_HI 19
++#define RO_IQCAL_O_SZ 20
++#define RO_IQCAL_SPRM_RDY_MSK 0x00100000
++#define RO_IQCAL_SPRM_RDY_I_MSK 0xffefffff
++#define RO_IQCAL_SPRM_RDY_SFT 20
++#define RO_IQCAL_SPRM_RDY_HI 20
++#define RO_IQCAL_SPRM_RDY_SZ 1
++#define RO_IQCAL_IQCOL_RDY_MSK 0x00200000
++#define RO_IQCAL_IQCOL_RDY_I_MSK 0xffdfffff
++#define RO_IQCAL_IQCOL_RDY_SFT 21
++#define RO_IQCAL_IQCOL_RDY_HI 21
++#define RO_IQCAL_IQCOL_RDY_SZ 1
++#define RO_IQCAL_ALPHA_ESTM_RDY_MSK 0x00400000
++#define RO_IQCAL_ALPHA_ESTM_RDY_I_MSK 0xffbfffff
++#define RO_IQCAL_ALPHA_ESTM_RDY_SFT 22
++#define RO_IQCAL_ALPHA_ESTM_RDY_HI 22
++#define RO_IQCAL_ALPHA_ESTM_RDY_SZ 1
++#define RO_IQCAL_DC_RDY_MSK 0x00800000
++#define RO_IQCAL_DC_RDY_I_MSK 0xff7fffff
++#define RO_IQCAL_DC_RDY_SFT 23
++#define RO_IQCAL_DC_RDY_HI 23
++#define RO_IQCAL_DC_RDY_SZ 1
++#define RO_IQCAL_MULT_RDY_MSK 0x01000000
++#define RO_IQCAL_MULT_RDY_I_MSK 0xfeffffff
++#define RO_IQCAL_MULT_RDY_SFT 24
++#define RO_IQCAL_MULT_RDY_HI 24
++#define RO_IQCAL_MULT_RDY_SZ 1
++#define RO_FFT_ENRG_RDY_MSK 0x02000000
++#define RO_FFT_ENRG_RDY_I_MSK 0xfdffffff
++#define RO_FFT_ENRG_RDY_SFT 25
++#define RO_FFT_ENRG_RDY_HI 25
++#define RO_FFT_ENRG_RDY_SZ 1
++#define RO_PHEST_RDY_MSK 0x04000000
++#define RO_PHEST_RDY_I_MSK 0xfbffffff
++#define RO_PHEST_RDY_SFT 26
++#define RO_PHEST_RDY_HI 26
++#define RO_PHEST_RDY_SZ 1
++#define RO_GP_DIV_RDY_MSK 0x08000000
++#define RO_GP_DIV_RDY_I_MSK 0xf7ffffff
++#define RO_GP_DIV_RDY_SFT 27
++#define RO_GP_DIV_RDY_HI 27
++#define RO_GP_DIV_RDY_SZ 1
++#define RO_GAIN_EST_RDY_MSK 0x10000000
++#define RO_GAIN_EST_RDY_I_MSK 0xefffffff
++#define RO_GAIN_EST_RDY_SFT 28
++#define RO_GAIN_EST_RDY_HI 28
++#define RO_GAIN_EST_RDY_SZ 1
++#define RO_AMP_O_MSK 0x000001ff
++#define RO_AMP_O_I_MSK 0xfffffe00
++#define RO_AMP_O_SFT 0
++#define RO_AMP_O_HI 8
++#define RO_AMP_O_SZ 9
++#define RG_RX_I_SCALE_MSK 0x000000ff
++#define RG_RX_I_SCALE_I_MSK 0xffffff00
++#define RG_RX_I_SCALE_SFT 0
++#define RG_RX_I_SCALE_HI 7
++#define RG_RX_I_SCALE_SZ 8
++#define RG_RX_Q_SCALE_MSK 0x0000ff00
++#define RG_RX_Q_SCALE_I_MSK 0xffff00ff
++#define RG_RX_Q_SCALE_SFT 8
++#define RG_RX_Q_SCALE_HI 15
++#define RG_RX_Q_SCALE_SZ 8
++#define RG_RX_I_OFFSET_MSK 0x00ff0000
++#define RG_RX_I_OFFSET_I_MSK 0xff00ffff
++#define RG_RX_I_OFFSET_SFT 16
++#define RG_RX_I_OFFSET_HI 23
++#define RG_RX_I_OFFSET_SZ 8
++#define RG_RX_Q_OFFSET_MSK 0xff000000
++#define RG_RX_Q_OFFSET_I_MSK 0x00ffffff
++#define RG_RX_Q_OFFSET_SFT 24
++#define RG_RX_Q_OFFSET_HI 31
++#define RG_RX_Q_OFFSET_SZ 8
++#define RG_RX_IQ_SWP_MSK 0x00000001
++#define RG_RX_IQ_SWP_I_MSK 0xfffffffe
++#define RG_RX_IQ_SWP_SFT 0
++#define RG_RX_IQ_SWP_HI 0
++#define RG_RX_IQ_SWP_SZ 1
++#define RG_RX_SGN_IN_MSK 0x00000002
++#define RG_RX_SGN_IN_I_MSK 0xfffffffd
++#define RG_RX_SGN_IN_SFT 1
++#define RG_RX_SGN_IN_HI 1
++#define RG_RX_SGN_IN_SZ 1
++#define RG_RX_IQ_SRC_MSK 0x0000000c
++#define RG_RX_IQ_SRC_I_MSK 0xfffffff3
++#define RG_RX_IQ_SRC_SFT 2
++#define RG_RX_IQ_SRC_HI 3
++#define RG_RX_IQ_SRC_SZ 2
++#define RG_ACI_GAIN_MSK 0x00000ff0
++#define RG_ACI_GAIN_I_MSK 0xfffff00f
++#define RG_ACI_GAIN_SFT 4
++#define RG_ACI_GAIN_HI 11
++#define RG_ACI_GAIN_SZ 8
++#define RG_FFT_EN_MSK 0x00001000
++#define RG_FFT_EN_I_MSK 0xffffefff
++#define RG_FFT_EN_SFT 12
++#define RG_FFT_EN_HI 12
++#define RG_FFT_EN_SZ 1
++#define RG_FFT_MOD_MSK 0x00002000
++#define RG_FFT_MOD_I_MSK 0xffffdfff
++#define RG_FFT_MOD_SFT 13
++#define RG_FFT_MOD_HI 13
++#define RG_FFT_MOD_SZ 1
++#define RG_FFT_SCALE_MSK 0x00ffc000
++#define RG_FFT_SCALE_I_MSK 0xff003fff
++#define RG_FFT_SCALE_SFT 14
++#define RG_FFT_SCALE_HI 23
++#define RG_FFT_SCALE_SZ 10
++#define RG_FFT_ENRG_FREQ_MSK 0x3f000000
++#define RG_FFT_ENRG_FREQ_I_MSK 0xc0ffffff
++#define RG_FFT_ENRG_FREQ_SFT 24
++#define RG_FFT_ENRG_FREQ_HI 29
++#define RG_FFT_ENRG_FREQ_SZ 6
++#define RG_FPGA_80M_PH_UP_MSK 0x40000000
++#define RG_FPGA_80M_PH_UP_I_MSK 0xbfffffff
++#define RG_FPGA_80M_PH_UP_SFT 30
++#define RG_FPGA_80M_PH_UP_HI 30
++#define RG_FPGA_80M_PH_UP_SZ 1
++#define RG_FPGA_80M_PH_STP_MSK 0x80000000
++#define RG_FPGA_80M_PH_STP_I_MSK 0x7fffffff
++#define RG_FPGA_80M_PH_STP_SFT 31
++#define RG_FPGA_80M_PH_STP_HI 31
++#define RG_FPGA_80M_PH_STP_SZ 1
++#define RG_ADC2LA_SEL_MSK 0x00000001
++#define RG_ADC2LA_SEL_I_MSK 0xfffffffe
++#define RG_ADC2LA_SEL_SFT 0
++#define RG_ADC2LA_SEL_HI 0
++#define RG_ADC2LA_SEL_SZ 1
++#define RG_ADC2LA_CLKPH_MSK 0x00000002
++#define RG_ADC2LA_CLKPH_I_MSK 0xfffffffd
++#define RG_ADC2LA_CLKPH_SFT 1
++#define RG_ADC2LA_CLKPH_HI 1
++#define RG_ADC2LA_CLKPH_SZ 1
++#define RG_RXIQ_EMU_IDX_MSK 0x0000000f
++#define RG_RXIQ_EMU_IDX_I_MSK 0xfffffff0
++#define RG_RXIQ_EMU_IDX_SFT 0
++#define RG_RXIQ_EMU_IDX_HI 3
++#define RG_RXIQ_EMU_IDX_SZ 4
++#define RG_IQCAL_BP_ACI_MSK 0x00000010
++#define RG_IQCAL_BP_ACI_I_MSK 0xffffffef
++#define RG_IQCAL_BP_ACI_SFT 4
++#define RG_IQCAL_BP_ACI_HI 4
++#define RG_IQCAL_BP_ACI_SZ 1
++#define RG_DPD_AM_EN_MSK 0x00000001
++#define RG_DPD_AM_EN_I_MSK 0xfffffffe
++#define RG_DPD_AM_EN_SFT 0
++#define RG_DPD_AM_EN_HI 0
++#define RG_DPD_AM_EN_SZ 1
++#define RG_DPD_PM_EN_MSK 0x00000002
++#define RG_DPD_PM_EN_I_MSK 0xfffffffd
++#define RG_DPD_PM_EN_SFT 1
++#define RG_DPD_PM_EN_HI 1
++#define RG_DPD_PM_EN_SZ 1
++#define RG_DPD_PM_AMSEL_MSK 0x00000004
++#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb
++#define RG_DPD_PM_AMSEL_SFT 2
++#define RG_DPD_PM_AMSEL_HI 2
++#define RG_DPD_PM_AMSEL_SZ 1
++#define RG_DPD_020_GAIN_MSK 0x000003ff
++#define RG_DPD_020_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_020_GAIN_SFT 0
++#define RG_DPD_020_GAIN_HI 9
++#define RG_DPD_020_GAIN_SZ 10
++#define RG_DPD_040_GAIN_MSK 0x03ff0000
++#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_040_GAIN_SFT 16
++#define RG_DPD_040_GAIN_HI 25
++#define RG_DPD_040_GAIN_SZ 10
++#define RG_DPD_060_GAIN_MSK 0x000003ff
++#define RG_DPD_060_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_060_GAIN_SFT 0
++#define RG_DPD_060_GAIN_HI 9
++#define RG_DPD_060_GAIN_SZ 10
++#define RG_DPD_080_GAIN_MSK 0x03ff0000
++#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_080_GAIN_SFT 16
++#define RG_DPD_080_GAIN_HI 25
++#define RG_DPD_080_GAIN_SZ 10
++#define RG_DPD_0A0_GAIN_MSK 0x000003ff
++#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_0A0_GAIN_SFT 0
++#define RG_DPD_0A0_GAIN_HI 9
++#define RG_DPD_0A0_GAIN_SZ 10
++#define RG_DPD_0C0_GAIN_MSK 0x03ff0000
++#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_0C0_GAIN_SFT 16
++#define RG_DPD_0C0_GAIN_HI 25
++#define RG_DPD_0C0_GAIN_SZ 10
++#define RG_DPD_0D0_GAIN_MSK 0x000003ff
++#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_0D0_GAIN_SFT 0
++#define RG_DPD_0D0_GAIN_HI 9
++#define RG_DPD_0D0_GAIN_SZ 10
++#define RG_DPD_0E0_GAIN_MSK 0x03ff0000
++#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_0E0_GAIN_SFT 16
++#define RG_DPD_0E0_GAIN_HI 25
++#define RG_DPD_0E0_GAIN_SZ 10
++#define RG_DPD_0F0_GAIN_MSK 0x000003ff
++#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_0F0_GAIN_SFT 0
++#define RG_DPD_0F0_GAIN_HI 9
++#define RG_DPD_0F0_GAIN_SZ 10
++#define RG_DPD_100_GAIN_MSK 0x03ff0000
++#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_100_GAIN_SFT 16
++#define RG_DPD_100_GAIN_HI 25
++#define RG_DPD_100_GAIN_SZ 10
++#define RG_DPD_110_GAIN_MSK 0x000003ff
++#define RG_DPD_110_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_110_GAIN_SFT 0
++#define RG_DPD_110_GAIN_HI 9
++#define RG_DPD_110_GAIN_SZ 10
++#define RG_DPD_120_GAIN_MSK 0x03ff0000
++#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_120_GAIN_SFT 16
++#define RG_DPD_120_GAIN_HI 25
++#define RG_DPD_120_GAIN_SZ 10
++#define RG_DPD_130_GAIN_MSK 0x000003ff
++#define RG_DPD_130_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_130_GAIN_SFT 0
++#define RG_DPD_130_GAIN_HI 9
++#define RG_DPD_130_GAIN_SZ 10
++#define RG_DPD_140_GAIN_MSK 0x03ff0000
++#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_140_GAIN_SFT 16
++#define RG_DPD_140_GAIN_HI 25
++#define RG_DPD_140_GAIN_SZ 10
++#define RG_DPD_150_GAIN_MSK 0x000003ff
++#define RG_DPD_150_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_150_GAIN_SFT 0
++#define RG_DPD_150_GAIN_HI 9
++#define RG_DPD_150_GAIN_SZ 10
++#define RG_DPD_160_GAIN_MSK 0x03ff0000
++#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_160_GAIN_SFT 16
++#define RG_DPD_160_GAIN_HI 25
++#define RG_DPD_160_GAIN_SZ 10
++#define RG_DPD_170_GAIN_MSK 0x000003ff
++#define RG_DPD_170_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_170_GAIN_SFT 0
++#define RG_DPD_170_GAIN_HI 9
++#define RG_DPD_170_GAIN_SZ 10
++#define RG_DPD_180_GAIN_MSK 0x03ff0000
++#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_180_GAIN_SFT 16
++#define RG_DPD_180_GAIN_HI 25
++#define RG_DPD_180_GAIN_SZ 10
++#define RG_DPD_190_GAIN_MSK 0x000003ff
++#define RG_DPD_190_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_190_GAIN_SFT 0
++#define RG_DPD_190_GAIN_HI 9
++#define RG_DPD_190_GAIN_SZ 10
++#define RG_DPD_1A0_GAIN_MSK 0x03ff0000
++#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_1A0_GAIN_SFT 16
++#define RG_DPD_1A0_GAIN_HI 25
++#define RG_DPD_1A0_GAIN_SZ 10
++#define RG_DPD_1B0_GAIN_MSK 0x000003ff
++#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_1B0_GAIN_SFT 0
++#define RG_DPD_1B0_GAIN_HI 9
++#define RG_DPD_1B0_GAIN_SZ 10
++#define RG_DPD_1C0_GAIN_MSK 0x03ff0000
++#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_1C0_GAIN_SFT 16
++#define RG_DPD_1C0_GAIN_HI 25
++#define RG_DPD_1C0_GAIN_SZ 10
++#define RG_DPD_1D0_GAIN_MSK 0x000003ff
++#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_1D0_GAIN_SFT 0
++#define RG_DPD_1D0_GAIN_HI 9
++#define RG_DPD_1D0_GAIN_SZ 10
++#define RG_DPD_1E0_GAIN_MSK 0x03ff0000
++#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_1E0_GAIN_SFT 16
++#define RG_DPD_1E0_GAIN_HI 25
++#define RG_DPD_1E0_GAIN_SZ 10
++#define RG_DPD_1F0_GAIN_MSK 0x000003ff
++#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_1F0_GAIN_SFT 0
++#define RG_DPD_1F0_GAIN_HI 9
++#define RG_DPD_1F0_GAIN_SZ 10
++#define RG_DPD_200_GAIN_MSK 0x03ff0000
++#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_200_GAIN_SFT 16
++#define RG_DPD_200_GAIN_HI 25
++#define RG_DPD_200_GAIN_SZ 10
++#define RG_DPD_020_PH_MSK 0x00001fff
++#define RG_DPD_020_PH_I_MSK 0xffffe000
++#define RG_DPD_020_PH_SFT 0
++#define RG_DPD_020_PH_HI 12
++#define RG_DPD_020_PH_SZ 13
++#define RG_DPD_040_PH_MSK 0x1fff0000
++#define RG_DPD_040_PH_I_MSK 0xe000ffff
++#define RG_DPD_040_PH_SFT 16
++#define RG_DPD_040_PH_HI 28
++#define RG_DPD_040_PH_SZ 13
++#define RG_DPD_060_PH_MSK 0x00001fff
++#define RG_DPD_060_PH_I_MSK 0xffffe000
++#define RG_DPD_060_PH_SFT 0
++#define RG_DPD_060_PH_HI 12
++#define RG_DPD_060_PH_SZ 13
++#define RG_DPD_080_PH_MSK 0x1fff0000
++#define RG_DPD_080_PH_I_MSK 0xe000ffff
++#define RG_DPD_080_PH_SFT 16
++#define RG_DPD_080_PH_HI 28
++#define RG_DPD_080_PH_SZ 13
++#define RG_DPD_0A0_PH_MSK 0x00001fff
++#define RG_DPD_0A0_PH_I_MSK 0xffffe000
++#define RG_DPD_0A0_PH_SFT 0
++#define RG_DPD_0A0_PH_HI 12
++#define RG_DPD_0A0_PH_SZ 13
++#define RG_DPD_0C0_PH_MSK 0x1fff0000
++#define RG_DPD_0C0_PH_I_MSK 0xe000ffff
++#define RG_DPD_0C0_PH_SFT 16
++#define RG_DPD_0C0_PH_HI 28
++#define RG_DPD_0C0_PH_SZ 13
++#define RG_DPD_0D0_PH_MSK 0x00001fff
++#define RG_DPD_0D0_PH_I_MSK 0xffffe000
++#define RG_DPD_0D0_PH_SFT 0
++#define RG_DPD_0D0_PH_HI 12
++#define RG_DPD_0D0_PH_SZ 13
++#define RG_DPD_0E0_PH_MSK 0x1fff0000
++#define RG_DPD_0E0_PH_I_MSK 0xe000ffff
++#define RG_DPD_0E0_PH_SFT 16
++#define RG_DPD_0E0_PH_HI 28
++#define RG_DPD_0E0_PH_SZ 13
++#define RG_DPD_0F0_PH_MSK 0x00001fff
++#define RG_DPD_0F0_PH_I_MSK 0xffffe000
++#define RG_DPD_0F0_PH_SFT 0
++#define RG_DPD_0F0_PH_HI 12
++#define RG_DPD_0F0_PH_SZ 13
++#define RG_DPD_100_PH_MSK 0x1fff0000
++#define RG_DPD_100_PH_I_MSK 0xe000ffff
++#define RG_DPD_100_PH_SFT 16
++#define RG_DPD_100_PH_HI 28
++#define RG_DPD_100_PH_SZ 13
++#define RG_DPD_110_PH_MSK 0x00001fff
++#define RG_DPD_110_PH_I_MSK 0xffffe000
++#define RG_DPD_110_PH_SFT 0
++#define RG_DPD_110_PH_HI 12
++#define RG_DPD_110_PH_SZ 13
++#define RG_DPD_120_PH_MSK 0x1fff0000
++#define RG_DPD_120_PH_I_MSK 0xe000ffff
++#define RG_DPD_120_PH_SFT 16
++#define RG_DPD_120_PH_HI 28
++#define RG_DPD_120_PH_SZ 13
++#define RG_DPD_130_PH_MSK 0x00001fff
++#define RG_DPD_130_PH_I_MSK 0xffffe000
++#define RG_DPD_130_PH_SFT 0
++#define RG_DPD_130_PH_HI 12
++#define RG_DPD_130_PH_SZ 13
++#define RG_DPD_140_PH_MSK 0x1fff0000
++#define RG_DPD_140_PH_I_MSK 0xe000ffff
++#define RG_DPD_140_PH_SFT 16
++#define RG_DPD_140_PH_HI 28
++#define RG_DPD_140_PH_SZ 13
++#define RG_DPD_150_PH_MSK 0x00001fff
++#define RG_DPD_150_PH_I_MSK 0xffffe000
++#define RG_DPD_150_PH_SFT 0
++#define RG_DPD_150_PH_HI 12
++#define RG_DPD_150_PH_SZ 13
++#define RG_DPD_160_PH_MSK 0x1fff0000
++#define RG_DPD_160_PH_I_MSK 0xe000ffff
++#define RG_DPD_160_PH_SFT 16
++#define RG_DPD_160_PH_HI 28
++#define RG_DPD_160_PH_SZ 13
++#define RG_DPD_170_PH_MSK 0x00001fff
++#define RG_DPD_170_PH_I_MSK 0xffffe000
++#define RG_DPD_170_PH_SFT 0
++#define RG_DPD_170_PH_HI 12
++#define RG_DPD_170_PH_SZ 13
++#define RG_DPD_180_PH_MSK 0x1fff0000
++#define RG_DPD_180_PH_I_MSK 0xe000ffff
++#define RG_DPD_180_PH_SFT 16
++#define RG_DPD_180_PH_HI 28
++#define RG_DPD_180_PH_SZ 13
++#define RG_DPD_190_PH_MSK 0x00001fff
++#define RG_DPD_190_PH_I_MSK 0xffffe000
++#define RG_DPD_190_PH_SFT 0
++#define RG_DPD_190_PH_HI 12
++#define RG_DPD_190_PH_SZ 13
++#define RG_DPD_1A0_PH_MSK 0x1fff0000
++#define RG_DPD_1A0_PH_I_MSK 0xe000ffff
++#define RG_DPD_1A0_PH_SFT 16
++#define RG_DPD_1A0_PH_HI 28
++#define RG_DPD_1A0_PH_SZ 13
++#define RG_DPD_1B0_PH_MSK 0x00001fff
++#define RG_DPD_1B0_PH_I_MSK 0xffffe000
++#define RG_DPD_1B0_PH_SFT 0
++#define RG_DPD_1B0_PH_HI 12
++#define RG_DPD_1B0_PH_SZ 13
++#define RG_DPD_1C0_PH_MSK 0x1fff0000
++#define RG_DPD_1C0_PH_I_MSK 0xe000ffff
++#define RG_DPD_1C0_PH_SFT 16
++#define RG_DPD_1C0_PH_HI 28
++#define RG_DPD_1C0_PH_SZ 13
++#define RG_DPD_1D0_PH_MSK 0x00001fff
++#define RG_DPD_1D0_PH_I_MSK 0xffffe000
++#define RG_DPD_1D0_PH_SFT 0
++#define RG_DPD_1D0_PH_HI 12
++#define RG_DPD_1D0_PH_SZ 13
++#define RG_DPD_1E0_PH_MSK 0x1fff0000
++#define RG_DPD_1E0_PH_I_MSK 0xe000ffff
++#define RG_DPD_1E0_PH_SFT 16
++#define RG_DPD_1E0_PH_HI 28
++#define RG_DPD_1E0_PH_SZ 13
++#define RG_DPD_1F0_PH_MSK 0x00001fff
++#define RG_DPD_1F0_PH_I_MSK 0xffffe000
++#define RG_DPD_1F0_PH_SFT 0
++#define RG_DPD_1F0_PH_HI 12
++#define RG_DPD_1F0_PH_SZ 13
++#define RG_DPD_200_PH_MSK 0x1fff0000
++#define RG_DPD_200_PH_I_MSK 0xe000ffff
++#define RG_DPD_200_PH_SFT 16
++#define RG_DPD_200_PH_HI 28
++#define RG_DPD_200_PH_SZ 13
++#define RG_DPD_GAIN_EST_Y0_MSK 0x000001ff
++#define RG_DPD_GAIN_EST_Y0_I_MSK 0xfffffe00
++#define RG_DPD_GAIN_EST_Y0_SFT 0
++#define RG_DPD_GAIN_EST_Y0_HI 8
++#define RG_DPD_GAIN_EST_Y0_SZ 9
++#define RG_DPD_GAIN_EST_Y1_MSK 0x01ff0000
++#define RG_DPD_GAIN_EST_Y1_I_MSK 0xfe00ffff
++#define RG_DPD_GAIN_EST_Y1_SFT 16
++#define RG_DPD_GAIN_EST_Y1_HI 24
++#define RG_DPD_GAIN_EST_Y1_SZ 9
++#define RG_DPD_LOOP_GAIN_MSK 0x000003ff
++#define RG_DPD_LOOP_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_LOOP_GAIN_SFT 0
++#define RG_DPD_LOOP_GAIN_HI 9
++#define RG_DPD_LOOP_GAIN_SZ 10
++#define RG_DPD_GAIN_EST_X0_MSK 0x000001ff
++#define RG_DPD_GAIN_EST_X0_I_MSK 0xfffffe00
++#define RG_DPD_GAIN_EST_X0_SFT 0
++#define RG_DPD_GAIN_EST_X0_HI 8
++#define RG_DPD_GAIN_EST_X0_SZ 9
++#define RO_DPD_GAIN_MSK 0x03ff0000
++#define RO_DPD_GAIN_I_MSK 0xfc00ffff
++#define RO_DPD_GAIN_SFT 16
++#define RO_DPD_GAIN_HI 25
++#define RO_DPD_GAIN_SZ 10
++#define TX_SCALE_11B_MSK 0x000000ff
++#define TX_SCALE_11B_I_MSK 0xffffff00
++#define TX_SCALE_11B_SFT 0
++#define TX_SCALE_11B_HI 7
++#define TX_SCALE_11B_SZ 8
++#define TX_SCALE_11B_P0D5_MSK 0x0000ff00
++#define TX_SCALE_11B_P0D5_I_MSK 0xffff00ff
++#define TX_SCALE_11B_P0D5_SFT 8
++#define TX_SCALE_11B_P0D5_HI 15
++#define TX_SCALE_11B_P0D5_SZ 8
++#define TX_SCALE_11G_MSK 0x00ff0000
++#define TX_SCALE_11G_I_MSK 0xff00ffff
++#define TX_SCALE_11G_SFT 16
++#define TX_SCALE_11G_HI 23
++#define TX_SCALE_11G_SZ 8
++#define TX_SCALE_11G_P0D5_MSK 0xff000000
++#define TX_SCALE_11G_P0D5_I_MSK 0x00ffffff
++#define TX_SCALE_11G_P0D5_SFT 24
++#define TX_SCALE_11G_P0D5_HI 31
++#define TX_SCALE_11G_P0D5_SZ 8
++#define RG_EN_MANUAL_MSK 0x00000001
++#define RG_EN_MANUAL_I_MSK 0xfffffffe
++#define RG_EN_MANUAL_SFT 0
++#define RG_EN_MANUAL_HI 0
++#define RG_EN_MANUAL_SZ 1
++#define RG_TX_EN_MSK 0x00000002
++#define RG_TX_EN_I_MSK 0xfffffffd
++#define RG_TX_EN_SFT 1
++#define RG_TX_EN_HI 1
++#define RG_TX_EN_SZ 1
++#define RG_TX_PA_EN_MSK 0x00000004
++#define RG_TX_PA_EN_I_MSK 0xfffffffb
++#define RG_TX_PA_EN_SFT 2
++#define RG_TX_PA_EN_HI 2
++#define RG_TX_PA_EN_SZ 1
++#define RG_TX_DAC_EN_MSK 0x00000008
++#define RG_TX_DAC_EN_I_MSK 0xfffffff7
++#define RG_TX_DAC_EN_SFT 3
++#define RG_TX_DAC_EN_HI 3
++#define RG_TX_DAC_EN_SZ 1
++#define RG_RX_AGC_MSK 0x00000010
++#define RG_RX_AGC_I_MSK 0xffffffef
++#define RG_RX_AGC_SFT 4
++#define RG_RX_AGC_HI 4
++#define RG_RX_AGC_SZ 1
++#define RG_RX_GAIN_MANUAL_MSK 0x00000020
++#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
++#define RG_RX_GAIN_MANUAL_SFT 5
++#define RG_RX_GAIN_MANUAL_HI 5
++#define RG_RX_GAIN_MANUAL_SZ 1
++#define RG_RFG_MSK 0x000000c0
++#define RG_RFG_I_MSK 0xffffff3f
++#define RG_RFG_SFT 6
++#define RG_RFG_HI 7
++#define RG_RFG_SZ 2
++#define RG_PGAG_MSK 0x00000f00
++#define RG_PGAG_I_MSK 0xfffff0ff
++#define RG_PGAG_SFT 8
++#define RG_PGAG_HI 11
++#define RG_PGAG_SZ 4
++#define RG_MODE_MSK 0x00003000
++#define RG_MODE_I_MSK 0xffffcfff
++#define RG_MODE_SFT 12
++#define RG_MODE_HI 13
++#define RG_MODE_SZ 2
++#define RG_EN_TX_TRSW_MSK 0x00004000
++#define RG_EN_TX_TRSW_I_MSK 0xffffbfff
++#define RG_EN_TX_TRSW_SFT 14
++#define RG_EN_TX_TRSW_HI 14
++#define RG_EN_TX_TRSW_SZ 1
++#define RG_EN_SX_MSK 0x00008000
++#define RG_EN_SX_I_MSK 0xffff7fff
++#define RG_EN_SX_SFT 15
++#define RG_EN_SX_HI 15
++#define RG_EN_SX_SZ 1
++#define RG_EN_RX_LNA_MSK 0x00010000
++#define RG_EN_RX_LNA_I_MSK 0xfffeffff
++#define RG_EN_RX_LNA_SFT 16
++#define RG_EN_RX_LNA_HI 16
++#define RG_EN_RX_LNA_SZ 1
++#define RG_EN_RX_MIXER_MSK 0x00020000
++#define RG_EN_RX_MIXER_I_MSK 0xfffdffff
++#define RG_EN_RX_MIXER_SFT 17
++#define RG_EN_RX_MIXER_HI 17
++#define RG_EN_RX_MIXER_SZ 1
++#define RG_EN_RX_DIV2_MSK 0x00040000
++#define RG_EN_RX_DIV2_I_MSK 0xfffbffff
++#define RG_EN_RX_DIV2_SFT 18
++#define RG_EN_RX_DIV2_HI 18
++#define RG_EN_RX_DIV2_SZ 1
++#define RG_EN_RX_LOBUF_MSK 0x00080000
++#define RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
++#define RG_EN_RX_LOBUF_SFT 19
++#define RG_EN_RX_LOBUF_HI 19
++#define RG_EN_RX_LOBUF_SZ 1
++#define RG_EN_RX_TZ_MSK 0x00100000
++#define RG_EN_RX_TZ_I_MSK 0xffefffff
++#define RG_EN_RX_TZ_SFT 20
++#define RG_EN_RX_TZ_HI 20
++#define RG_EN_RX_TZ_SZ 1
++#define RG_EN_RX_FILTER_MSK 0x00200000
++#define RG_EN_RX_FILTER_I_MSK 0xffdfffff
++#define RG_EN_RX_FILTER_SFT 21
++#define RG_EN_RX_FILTER_HI 21
++#define RG_EN_RX_FILTER_SZ 1
++#define RG_EN_RX_HPF_MSK 0x00400000
++#define RG_EN_RX_HPF_I_MSK 0xffbfffff
++#define RG_EN_RX_HPF_SFT 22
++#define RG_EN_RX_HPF_HI 22
++#define RG_EN_RX_HPF_SZ 1
++#define RG_EN_RX_RSSI_MSK 0x00800000
++#define RG_EN_RX_RSSI_I_MSK 0xff7fffff
++#define RG_EN_RX_RSSI_SFT 23
++#define RG_EN_RX_RSSI_HI 23
++#define RG_EN_RX_RSSI_SZ 1
++#define RG_EN_ADC_MSK 0x01000000
++#define RG_EN_ADC_I_MSK 0xfeffffff
++#define RG_EN_ADC_SFT 24
++#define RG_EN_ADC_HI 24
++#define RG_EN_ADC_SZ 1
++#define RG_EN_TX_MOD_MSK 0x02000000
++#define RG_EN_TX_MOD_I_MSK 0xfdffffff
++#define RG_EN_TX_MOD_SFT 25
++#define RG_EN_TX_MOD_HI 25
++#define RG_EN_TX_MOD_SZ 1
++#define RG_EN_TX_DIV2_MSK 0x04000000
++#define RG_EN_TX_DIV2_I_MSK 0xfbffffff
++#define RG_EN_TX_DIV2_SFT 26
++#define RG_EN_TX_DIV2_HI 26
++#define RG_EN_TX_DIV2_SZ 1
++#define RG_EN_TX_DIV2_BUF_MSK 0x08000000
++#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
++#define RG_EN_TX_DIV2_BUF_SFT 27
++#define RG_EN_TX_DIV2_BUF_HI 27
++#define RG_EN_TX_DIV2_BUF_SZ 1
++#define RG_EN_TX_LOBF_MSK 0x10000000
++#define RG_EN_TX_LOBF_I_MSK 0xefffffff
++#define RG_EN_TX_LOBF_SFT 28
++#define RG_EN_TX_LOBF_HI 28
++#define RG_EN_TX_LOBF_SZ 1
++#define RG_EN_RX_LOBF_MSK 0x20000000
++#define RG_EN_RX_LOBF_I_MSK 0xdfffffff
++#define RG_EN_RX_LOBF_SFT 29
++#define RG_EN_RX_LOBF_HI 29
++#define RG_EN_RX_LOBF_SZ 1
++#define RG_SEL_DPLL_CLK_MSK 0x40000000
++#define RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
++#define RG_SEL_DPLL_CLK_SFT 30
++#define RG_SEL_DPLL_CLK_HI 30
++#define RG_SEL_DPLL_CLK_SZ 1
++#define RG_EN_CLK_960MBY13_UART_MSK 0x80000000
++#define RG_EN_CLK_960MBY13_UART_I_MSK 0x7fffffff
++#define RG_EN_CLK_960MBY13_UART_SFT 31
++#define RG_EN_CLK_960MBY13_UART_HI 31
++#define RG_EN_CLK_960MBY13_UART_SZ 1
++#define RG_EN_TX_DPD_MSK 0x00000001
++#define RG_EN_TX_DPD_I_MSK 0xfffffffe
++#define RG_EN_TX_DPD_SFT 0
++#define RG_EN_TX_DPD_HI 0
++#define RG_EN_TX_DPD_SZ 1
++#define RG_EN_TX_TSSI_MSK 0x00000002
++#define RG_EN_TX_TSSI_I_MSK 0xfffffffd
++#define RG_EN_TX_TSSI_SFT 1
++#define RG_EN_TX_TSSI_HI 1
++#define RG_EN_TX_TSSI_SZ 1
++#define RG_EN_RX_IQCAL_MSK 0x00000004
++#define RG_EN_RX_IQCAL_I_MSK 0xfffffffb
++#define RG_EN_RX_IQCAL_SFT 2
++#define RG_EN_RX_IQCAL_HI 2
++#define RG_EN_RX_IQCAL_SZ 1
++#define RG_EN_TX_DAC_CAL_MSK 0x00000008
++#define RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
++#define RG_EN_TX_DAC_CAL_SFT 3
++#define RG_EN_TX_DAC_CAL_HI 3
++#define RG_EN_TX_DAC_CAL_SZ 1
++#define RG_EN_TX_SELF_MIXER_MSK 0x00000010
++#define RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
++#define RG_EN_TX_SELF_MIXER_SFT 4
++#define RG_EN_TX_SELF_MIXER_HI 4
++#define RG_EN_TX_SELF_MIXER_SZ 1
++#define RG_EN_TX_DAC_OUT_MSK 0x00000020
++#define RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
++#define RG_EN_TX_DAC_OUT_SFT 5
++#define RG_EN_TX_DAC_OUT_HI 5
++#define RG_EN_TX_DAC_OUT_SZ 1
++#define RG_EN_LDO_RX_FE_MSK 0x00000040
++#define RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
++#define RG_EN_LDO_RX_FE_SFT 6
++#define RG_EN_LDO_RX_FE_HI 6
++#define RG_EN_LDO_RX_FE_SZ 1
++#define RG_EN_LDO_ABB_MSK 0x00000080
++#define RG_EN_LDO_ABB_I_MSK 0xffffff7f
++#define RG_EN_LDO_ABB_SFT 7
++#define RG_EN_LDO_ABB_HI 7
++#define RG_EN_LDO_ABB_SZ 1
++#define RG_EN_LDO_AFE_MSK 0x00000100
++#define RG_EN_LDO_AFE_I_MSK 0xfffffeff
++#define RG_EN_LDO_AFE_SFT 8
++#define RG_EN_LDO_AFE_HI 8
++#define RG_EN_LDO_AFE_SZ 1
++#define RG_EN_SX_CHPLDO_MSK 0x00000200
++#define RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
++#define RG_EN_SX_CHPLDO_SFT 9
++#define RG_EN_SX_CHPLDO_HI 9
++#define RG_EN_SX_CHPLDO_SZ 1
++#define RG_EN_SX_LOBFLDO_MSK 0x00000400
++#define RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
++#define RG_EN_SX_LOBFLDO_SFT 10
++#define RG_EN_SX_LOBFLDO_HI 10
++#define RG_EN_SX_LOBFLDO_SZ 1
++#define RG_EN_IREF_RX_MSK 0x00000800
++#define RG_EN_IREF_RX_I_MSK 0xfffff7ff
++#define RG_EN_IREF_RX_SFT 11
++#define RG_EN_IREF_RX_HI 11
++#define RG_EN_IREF_RX_SZ 1
++#define RG_EN_TX_DAC_VOUT_MSK 0x00002000
++#define RG_EN_TX_DAC_VOUT_I_MSK 0xffffdfff
++#define RG_EN_TX_DAC_VOUT_SFT 13
++#define RG_EN_TX_DAC_VOUT_HI 13
++#define RG_EN_TX_DAC_VOUT_SZ 1
++#define RG_EN_SX_LCK_BIN_MSK 0x00004000
++#define RG_EN_SX_LCK_BIN_I_MSK 0xffffbfff
++#define RG_EN_SX_LCK_BIN_SFT 14
++#define RG_EN_SX_LCK_BIN_HI 14
++#define RG_EN_SX_LCK_BIN_SZ 1
++#define RG_RTC_CAL_MODE_MSK 0x00010000
++#define RG_RTC_CAL_MODE_I_MSK 0xfffeffff
++#define RG_RTC_CAL_MODE_SFT 16
++#define RG_RTC_CAL_MODE_HI 16
++#define RG_RTC_CAL_MODE_SZ 1
++#define RG_EN_IQPAD_IOSW_MSK 0x00020000
++#define RG_EN_IQPAD_IOSW_I_MSK 0xfffdffff
++#define RG_EN_IQPAD_IOSW_SFT 17
++#define RG_EN_IQPAD_IOSW_HI 17
++#define RG_EN_IQPAD_IOSW_SZ 1
++#define RG_EN_TESTPAD_IOSW_MSK 0x00040000
++#define RG_EN_TESTPAD_IOSW_I_MSK 0xfffbffff
++#define RG_EN_TESTPAD_IOSW_SFT 18
++#define RG_EN_TESTPAD_IOSW_HI 18
++#define RG_EN_TESTPAD_IOSW_SZ 1
++#define RG_EN_TRXBF_BYPASS_MSK 0x00080000
++#define RG_EN_TRXBF_BYPASS_I_MSK 0xfff7ffff
++#define RG_EN_TRXBF_BYPASS_SFT 19
++#define RG_EN_TRXBF_BYPASS_HI 19
++#define RG_EN_TRXBF_BYPASS_SZ 1
++#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007
++#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
++#define RG_LDO_LEVEL_RX_FE_SFT 0
++#define RG_LDO_LEVEL_RX_FE_HI 2
++#define RG_LDO_LEVEL_RX_FE_SZ 3
++#define RG_LDO_LEVEL_ABB_MSK 0x00000038
++#define RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
++#define RG_LDO_LEVEL_ABB_SFT 3
++#define RG_LDO_LEVEL_ABB_HI 5
++#define RG_LDO_LEVEL_ABB_SZ 3
++#define RG_LDO_LEVEL_AFE_MSK 0x000001c0
++#define RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
++#define RG_LDO_LEVEL_AFE_SFT 6
++#define RG_LDO_LEVEL_AFE_HI 8
++#define RG_LDO_LEVEL_AFE_SZ 3
++#define RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
++#define RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
++#define RG_SX_LDO_CHP_LEVEL_SFT 9
++#define RG_SX_LDO_CHP_LEVEL_HI 11
++#define RG_SX_LDO_CHP_LEVEL_SZ 3
++#define RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
++#define RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
++#define RG_SX_LDO_LOBF_LEVEL_SFT 12
++#define RG_SX_LDO_LOBF_LEVEL_HI 14
++#define RG_SX_LDO_LOBF_LEVEL_SZ 3
++#define RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
++#define RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
++#define RG_SX_LDO_XOSC_LEVEL_SFT 15
++#define RG_SX_LDO_XOSC_LEVEL_HI 17
++#define RG_SX_LDO_XOSC_LEVEL_SZ 3
++#define RG_DP_LDO_LEVEL_MSK 0x001c0000
++#define RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
++#define RG_DP_LDO_LEVEL_SFT 18
++#define RG_DP_LDO_LEVEL_HI 20
++#define RG_DP_LDO_LEVEL_SZ 3
++#define RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
++#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
++#define RG_SX_LDO_VCO_LEVEL_SFT 21
++#define RG_SX_LDO_VCO_LEVEL_HI 23
++#define RG_SX_LDO_VCO_LEVEL_SZ 3
++#define RG_TX_LDO_TX_LEVEL_MSK 0x07000000
++#define RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
++#define RG_TX_LDO_TX_LEVEL_SFT 24
++#define RG_TX_LDO_TX_LEVEL_HI 26
++#define RG_TX_LDO_TX_LEVEL_SZ 3
++#define RG_EN_RX_PADSW_MSK 0x00000001
++#define RG_EN_RX_PADSW_I_MSK 0xfffffffe
++#define RG_EN_RX_PADSW_SFT 0
++#define RG_EN_RX_PADSW_HI 0
++#define RG_EN_RX_PADSW_SZ 1
++#define RG_EN_RX_TESTNODE_MSK 0x00000002
++#define RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
++#define RG_EN_RX_TESTNODE_SFT 1
++#define RG_EN_RX_TESTNODE_HI 1
++#define RG_EN_RX_TESTNODE_SZ 1
++#define RG_RX_ABBCFIX_MSK 0x00000004
++#define RG_RX_ABBCFIX_I_MSK 0xfffffffb
++#define RG_RX_ABBCFIX_SFT 2
++#define RG_RX_ABBCFIX_HI 2
++#define RG_RX_ABBCFIX_SZ 1
++#define RG_RX_ABBCTUNE_MSK 0x000001f8
++#define RG_RX_ABBCTUNE_I_MSK 0xfffffe07
++#define RG_RX_ABBCTUNE_SFT 3
++#define RG_RX_ABBCTUNE_HI 8
++#define RG_RX_ABBCTUNE_SZ 6
++#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
++#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
++#define RG_RX_ABBOUT_TRI_STATE_SFT 9
++#define RG_RX_ABBOUT_TRI_STATE_HI 9
++#define RG_RX_ABBOUT_TRI_STATE_SZ 1
++#define RG_RX_ABB_N_MODE_MSK 0x00000400
++#define RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
++#define RG_RX_ABB_N_MODE_SFT 10
++#define RG_RX_ABB_N_MODE_HI 10
++#define RG_RX_ABB_N_MODE_SZ 1
++#define RG_RX_EN_LOOPA_MSK 0x00000800
++#define RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
++#define RG_RX_EN_LOOPA_SFT 11
++#define RG_RX_EN_LOOPA_HI 11
++#define RG_RX_EN_LOOPA_SZ 1
++#define RG_RX_FILTERI1ST_MSK 0x00003000
++#define RG_RX_FILTERI1ST_I_MSK 0xffffcfff
++#define RG_RX_FILTERI1ST_SFT 12
++#define RG_RX_FILTERI1ST_HI 13
++#define RG_RX_FILTERI1ST_SZ 2
++#define RG_RX_FILTERI2ND_MSK 0x0000c000
++#define RG_RX_FILTERI2ND_I_MSK 0xffff3fff
++#define RG_RX_FILTERI2ND_SFT 14
++#define RG_RX_FILTERI2ND_HI 15
++#define RG_RX_FILTERI2ND_SZ 2
++#define RG_RX_FILTERI3RD_MSK 0x00030000
++#define RG_RX_FILTERI3RD_I_MSK 0xfffcffff
++#define RG_RX_FILTERI3RD_SFT 16
++#define RG_RX_FILTERI3RD_HI 17
++#define RG_RX_FILTERI3RD_SZ 2
++#define RG_RX_FILTERI_COURSE_MSK 0x000c0000
++#define RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
++#define RG_RX_FILTERI_COURSE_SFT 18
++#define RG_RX_FILTERI_COURSE_HI 19
++#define RG_RX_FILTERI_COURSE_SZ 2
++#define RG_RX_FILTERVCM_MSK 0x00300000
++#define RG_RX_FILTERVCM_I_MSK 0xffcfffff
++#define RG_RX_FILTERVCM_SFT 20
++#define RG_RX_FILTERVCM_HI 21
++#define RG_RX_FILTERVCM_SZ 2
++#define RG_RX_HPF3M_MSK 0x00400000
++#define RG_RX_HPF3M_I_MSK 0xffbfffff
++#define RG_RX_HPF3M_SFT 22
++#define RG_RX_HPF3M_HI 22
++#define RG_RX_HPF3M_SZ 1
++#define RG_RX_HPF300K_MSK 0x00800000
++#define RG_RX_HPF300K_I_MSK 0xff7fffff
++#define RG_RX_HPF300K_SFT 23
++#define RG_RX_HPF300K_HI 23
++#define RG_RX_HPF300K_SZ 1
++#define RG_RX_HPFI_MSK 0x03000000
++#define RG_RX_HPFI_I_MSK 0xfcffffff
++#define RG_RX_HPFI_SFT 24
++#define RG_RX_HPFI_HI 25
++#define RG_RX_HPFI_SZ 2
++#define RG_RX_HPF_FINALCORNER_MSK 0x0c000000
++#define RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
++#define RG_RX_HPF_FINALCORNER_SFT 26
++#define RG_RX_HPF_FINALCORNER_HI 27
++#define RG_RX_HPF_FINALCORNER_SZ 2
++#define RG_RX_HPF_SETTLE1_C_MSK 0x30000000
++#define RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
++#define RG_RX_HPF_SETTLE1_C_SFT 28
++#define RG_RX_HPF_SETTLE1_C_HI 29
++#define RG_RX_HPF_SETTLE1_C_SZ 2
++#define RG_RX_HPF_SETTLE1_R_MSK 0x00000003
++#define RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
++#define RG_RX_HPF_SETTLE1_R_SFT 0
++#define RG_RX_HPF_SETTLE1_R_HI 1
++#define RG_RX_HPF_SETTLE1_R_SZ 2
++#define RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
++#define RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
++#define RG_RX_HPF_SETTLE2_C_SFT 2
++#define RG_RX_HPF_SETTLE2_C_HI 3
++#define RG_RX_HPF_SETTLE2_C_SZ 2
++#define RG_RX_HPF_SETTLE2_R_MSK 0x00000030
++#define RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
++#define RG_RX_HPF_SETTLE2_R_SFT 4
++#define RG_RX_HPF_SETTLE2_R_HI 5
++#define RG_RX_HPF_SETTLE2_R_SZ 2
++#define RG_RX_HPF_VCMCON2_MSK 0x000000c0
++#define RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
++#define RG_RX_HPF_VCMCON2_SFT 6
++#define RG_RX_HPF_VCMCON2_HI 7
++#define RG_RX_HPF_VCMCON2_SZ 2
++#define RG_RX_HPF_VCMCON_MSK 0x00000300
++#define RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
++#define RG_RX_HPF_VCMCON_SFT 8
++#define RG_RX_HPF_VCMCON_HI 9
++#define RG_RX_HPF_VCMCON_SZ 2
++#define RG_RX_OUTVCM_MSK 0x00000c00
++#define RG_RX_OUTVCM_I_MSK 0xfffff3ff
++#define RG_RX_OUTVCM_SFT 10
++#define RG_RX_OUTVCM_HI 11
++#define RG_RX_OUTVCM_SZ 2
++#define RG_RX_TZI_MSK 0x00003000
++#define RG_RX_TZI_I_MSK 0xffffcfff
++#define RG_RX_TZI_SFT 12
++#define RG_RX_TZI_HI 13
++#define RG_RX_TZI_SZ 2
++#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
++#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
++#define RG_RX_TZ_OUT_TRISTATE_SFT 14
++#define RG_RX_TZ_OUT_TRISTATE_HI 14
++#define RG_RX_TZ_OUT_TRISTATE_SZ 1
++#define RG_RX_TZ_VCM_MSK 0x00018000
++#define RG_RX_TZ_VCM_I_MSK 0xfffe7fff
++#define RG_RX_TZ_VCM_SFT 15
++#define RG_RX_TZ_VCM_HI 16
++#define RG_RX_TZ_VCM_SZ 2
++#define RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
++#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
++#define RG_EN_RX_RSSI_TESTNODE_SFT 17
++#define RG_EN_RX_RSSI_TESTNODE_HI 19
++#define RG_EN_RX_RSSI_TESTNODE_SZ 3
++#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
++#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
++#define RG_RX_ADCRSSI_CLKSEL_SFT 20
++#define RG_RX_ADCRSSI_CLKSEL_HI 20
++#define RG_RX_ADCRSSI_CLKSEL_SZ 1
++#define RG_RX_ADCRSSI_VCM_MSK 0x00600000
++#define RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
++#define RG_RX_ADCRSSI_VCM_SFT 21
++#define RG_RX_ADCRSSI_VCM_HI 22
++#define RG_RX_ADCRSSI_VCM_SZ 2
++#define RG_RX_REC_LPFCORNER_MSK 0x01800000
++#define RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
++#define RG_RX_REC_LPFCORNER_SFT 23
++#define RG_RX_REC_LPFCORNER_HI 24
++#define RG_RX_REC_LPFCORNER_SZ 2
++#define RG_RSSI_CLOCK_GATING_MSK 0x02000000
++#define RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
++#define RG_RSSI_CLOCK_GATING_SFT 25
++#define RG_RSSI_CLOCK_GATING_HI 25
++#define RG_RSSI_CLOCK_GATING_SZ 1
++#define RG_TXPGA_CAPSW_MSK 0x00000003
++#define RG_TXPGA_CAPSW_I_MSK 0xfffffffc
++#define RG_TXPGA_CAPSW_SFT 0
++#define RG_TXPGA_CAPSW_HI 1
++#define RG_TXPGA_CAPSW_SZ 2
++#define RG_TXPGA_MAIN_MSK 0x000000fc
++#define RG_TXPGA_MAIN_I_MSK 0xffffff03
++#define RG_TXPGA_MAIN_SFT 2
++#define RG_TXPGA_MAIN_HI 7
++#define RG_TXPGA_MAIN_SZ 6
++#define RG_TXPGA_STEER_MSK 0x00003f00
++#define RG_TXPGA_STEER_I_MSK 0xffffc0ff
++#define RG_TXPGA_STEER_SFT 8
++#define RG_TXPGA_STEER_HI 13
++#define RG_TXPGA_STEER_SZ 6
++#define RG_TXMOD_GMCELL_MSK 0x0000c000
++#define RG_TXMOD_GMCELL_I_MSK 0xffff3fff
++#define RG_TXMOD_GMCELL_SFT 14
++#define RG_TXMOD_GMCELL_HI 15
++#define RG_TXMOD_GMCELL_SZ 2
++#define RG_TXLPF_GMCELL_MSK 0x00030000
++#define RG_TXLPF_GMCELL_I_MSK 0xfffcffff
++#define RG_TXLPF_GMCELL_SFT 16
++#define RG_TXLPF_GMCELL_HI 17
++#define RG_TXLPF_GMCELL_SZ 2
++#define RG_PACELL_EN_MSK 0x001c0000
++#define RG_PACELL_EN_I_MSK 0xffe3ffff
++#define RG_PACELL_EN_SFT 18
++#define RG_PACELL_EN_HI 20
++#define RG_PACELL_EN_SZ 3
++#define RG_PABIAS_CTRL_MSK 0x01e00000
++#define RG_PABIAS_CTRL_I_MSK 0xfe1fffff
++#define RG_PABIAS_CTRL_SFT 21
++#define RG_PABIAS_CTRL_HI 24
++#define RG_PABIAS_CTRL_SZ 4
++#define RG_TX_DIV_VSET_MSK 0x0c000000
++#define RG_TX_DIV_VSET_I_MSK 0xf3ffffff
++#define RG_TX_DIV_VSET_SFT 26
++#define RG_TX_DIV_VSET_HI 27
++#define RG_TX_DIV_VSET_SZ 2
++#define RG_TX_LOBUF_VSET_MSK 0x30000000
++#define RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
++#define RG_TX_LOBUF_VSET_SFT 28
++#define RG_TX_LOBUF_VSET_HI 29
++#define RG_TX_LOBUF_VSET_SZ 2
++#define RG_RX_SQDC_MSK 0x00000007
++#define RG_RX_SQDC_I_MSK 0xfffffff8
++#define RG_RX_SQDC_SFT 0
++#define RG_RX_SQDC_HI 2
++#define RG_RX_SQDC_SZ 3
++#define RG_RX_DIV2_CORE_MSK 0x00000018
++#define RG_RX_DIV2_CORE_I_MSK 0xffffffe7
++#define RG_RX_DIV2_CORE_SFT 3
++#define RG_RX_DIV2_CORE_HI 4
++#define RG_RX_DIV2_CORE_SZ 2
++#define RG_RX_LOBUF_MSK 0x00000060
++#define RG_RX_LOBUF_I_MSK 0xffffff9f
++#define RG_RX_LOBUF_SFT 5
++#define RG_RX_LOBUF_HI 6
++#define RG_RX_LOBUF_SZ 2
++#define RG_TX_DPDGM_BIAS_MSK 0x00000780
++#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
++#define RG_TX_DPDGM_BIAS_SFT 7
++#define RG_TX_DPDGM_BIAS_HI 10
++#define RG_TX_DPDGM_BIAS_SZ 4
++#define RG_TX_DPD_DIV_MSK 0x00007800
++#define RG_TX_DPD_DIV_I_MSK 0xffff87ff
++#define RG_TX_DPD_DIV_SFT 11
++#define RG_TX_DPD_DIV_HI 14
++#define RG_TX_DPD_DIV_SZ 4
++#define RG_TX_TSSI_BIAS_MSK 0x00038000
++#define RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
++#define RG_TX_TSSI_BIAS_SFT 15
++#define RG_TX_TSSI_BIAS_HI 17
++#define RG_TX_TSSI_BIAS_SZ 3
++#define RG_TX_TSSI_DIV_MSK 0x001c0000
++#define RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
++#define RG_TX_TSSI_DIV_SFT 18
++#define RG_TX_TSSI_DIV_HI 20
++#define RG_TX_TSSI_DIV_SZ 3
++#define RG_TX_TSSI_TESTMODE_MSK 0x00200000
++#define RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
++#define RG_TX_TSSI_TESTMODE_SFT 21
++#define RG_TX_TSSI_TESTMODE_HI 21
++#define RG_TX_TSSI_TESTMODE_SZ 1
++#define RG_TX_TSSI_TEST_MSK 0x00c00000
++#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff
++#define RG_TX_TSSI_TEST_SFT 22
++#define RG_TX_TSSI_TEST_HI 23
++#define RG_TX_TSSI_TEST_SZ 2
++#define RG_PACASCODE_CTRL_MSK 0x07000000
++#define RG_PACASCODE_CTRL_I_MSK 0xf8ffffff
++#define RG_PACASCODE_CTRL_SFT 24
++#define RG_PACASCODE_CTRL_HI 26
++#define RG_PACASCODE_CTRL_SZ 3
++#define RG_RX_HG_LNA_GC_MSK 0x00000003
++#define RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_HG_LNA_GC_SFT 0
++#define RG_RX_HG_LNA_GC_HI 1
++#define RG_RX_HG_LNA_GC_SZ 2
++#define RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_HG_LNAHGN_BIAS_SFT 2
++#define RG_RX_HG_LNAHGN_BIAS_HI 5
++#define RG_RX_HG_LNAHGN_BIAS_SZ 4
++#define RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_HG_LNAHGP_BIAS_SFT 6
++#define RG_RX_HG_LNAHGP_BIAS_HI 9
++#define RG_RX_HG_LNAHGP_BIAS_SZ 4
++#define RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_HG_LNALG_BIAS_SFT 10
++#define RG_RX_HG_LNALG_BIAS_HI 13
++#define RG_RX_HG_LNALG_BIAS_SZ 4
++#define RG_RX_HG_TZ_GC_MSK 0x0000c000
++#define RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_HG_TZ_GC_SFT 14
++#define RG_RX_HG_TZ_GC_HI 15
++#define RG_RX_HG_TZ_GC_SZ 2
++#define RG_RX_HG_TZ_CAP_MSK 0x00070000
++#define RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_HG_TZ_CAP_SFT 16
++#define RG_RX_HG_TZ_CAP_HI 18
++#define RG_RX_HG_TZ_CAP_SZ 3
++#define RG_RX_MG_LNA_GC_MSK 0x00000003
++#define RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_MG_LNA_GC_SFT 0
++#define RG_RX_MG_LNA_GC_HI 1
++#define RG_RX_MG_LNA_GC_SZ 2
++#define RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_MG_LNAHGN_BIAS_SFT 2
++#define RG_RX_MG_LNAHGN_BIAS_HI 5
++#define RG_RX_MG_LNAHGN_BIAS_SZ 4
++#define RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_MG_LNAHGP_BIAS_SFT 6
++#define RG_RX_MG_LNAHGP_BIAS_HI 9
++#define RG_RX_MG_LNAHGP_BIAS_SZ 4
++#define RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_MG_LNALG_BIAS_SFT 10
++#define RG_RX_MG_LNALG_BIAS_HI 13
++#define RG_RX_MG_LNALG_BIAS_SZ 4
++#define RG_RX_MG_TZ_GC_MSK 0x0000c000
++#define RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_MG_TZ_GC_SFT 14
++#define RG_RX_MG_TZ_GC_HI 15
++#define RG_RX_MG_TZ_GC_SZ 2
++#define RG_RX_MG_TZ_CAP_MSK 0x00070000
++#define RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_MG_TZ_CAP_SFT 16
++#define RG_RX_MG_TZ_CAP_HI 18
++#define RG_RX_MG_TZ_CAP_SZ 3
++#define RG_RX_LG_LNA_GC_MSK 0x00000003
++#define RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_LG_LNA_GC_SFT 0
++#define RG_RX_LG_LNA_GC_HI 1
++#define RG_RX_LG_LNA_GC_SZ 2
++#define RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_LG_LNAHGN_BIAS_SFT 2
++#define RG_RX_LG_LNAHGN_BIAS_HI 5
++#define RG_RX_LG_LNAHGN_BIAS_SZ 4
++#define RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_LG_LNAHGP_BIAS_SFT 6
++#define RG_RX_LG_LNAHGP_BIAS_HI 9
++#define RG_RX_LG_LNAHGP_BIAS_SZ 4
++#define RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_LG_LNALG_BIAS_SFT 10
++#define RG_RX_LG_LNALG_BIAS_HI 13
++#define RG_RX_LG_LNALG_BIAS_SZ 4
++#define RG_RX_LG_TZ_GC_MSK 0x0000c000
++#define RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_LG_TZ_GC_SFT 14
++#define RG_RX_LG_TZ_GC_HI 15
++#define RG_RX_LG_TZ_GC_SZ 2
++#define RG_RX_LG_TZ_CAP_MSK 0x00070000
++#define RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_LG_TZ_CAP_SFT 16
++#define RG_RX_LG_TZ_CAP_HI 18
++#define RG_RX_LG_TZ_CAP_SZ 3
++#define RG_RX_ULG_LNA_GC_MSK 0x00000003
++#define RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_ULG_LNA_GC_SFT 0
++#define RG_RX_ULG_LNA_GC_HI 1
++#define RG_RX_ULG_LNA_GC_SZ 2
++#define RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_ULG_LNAHGN_BIAS_SFT 2
++#define RG_RX_ULG_LNAHGN_BIAS_HI 5
++#define RG_RX_ULG_LNAHGN_BIAS_SZ 4
++#define RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_ULG_LNAHGP_BIAS_SFT 6
++#define RG_RX_ULG_LNAHGP_BIAS_HI 9
++#define RG_RX_ULG_LNAHGP_BIAS_SZ 4
++#define RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_ULG_LNALG_BIAS_SFT 10
++#define RG_RX_ULG_LNALG_BIAS_HI 13
++#define RG_RX_ULG_LNALG_BIAS_SZ 4
++#define RG_RX_ULG_TZ_GC_MSK 0x0000c000
++#define RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_ULG_TZ_GC_SFT 14
++#define RG_RX_ULG_TZ_GC_HI 15
++#define RG_RX_ULG_TZ_GC_SZ 2
++#define RG_RX_ULG_TZ_CAP_MSK 0x00070000
++#define RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_ULG_TZ_CAP_SFT 16
++#define RG_RX_ULG_TZ_CAP_HI 18
++#define RG_RX_ULG_TZ_CAP_SZ 3
++#define RG_HPF1_FAST_SET_X_MSK 0x00000001
++#define RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
++#define RG_HPF1_FAST_SET_X_SFT 0
++#define RG_HPF1_FAST_SET_X_HI 0
++#define RG_HPF1_FAST_SET_X_SZ 1
++#define RG_HPF1_FAST_SET_Y_MSK 0x00000002
++#define RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
++#define RG_HPF1_FAST_SET_Y_SFT 1
++#define RG_HPF1_FAST_SET_Y_HI 1
++#define RG_HPF1_FAST_SET_Y_SZ 1
++#define RG_HPF1_FAST_SET_Z_MSK 0x00000004
++#define RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
++#define RG_HPF1_FAST_SET_Z_SFT 2
++#define RG_HPF1_FAST_SET_Z_HI 2
++#define RG_HPF1_FAST_SET_Z_SZ 1
++#define RG_HPF_T1A_MSK 0x00000018
++#define RG_HPF_T1A_I_MSK 0xffffffe7
++#define RG_HPF_T1A_SFT 3
++#define RG_HPF_T1A_HI 4
++#define RG_HPF_T1A_SZ 2
++#define RG_HPF_T1B_MSK 0x00000060
++#define RG_HPF_T1B_I_MSK 0xffffff9f
++#define RG_HPF_T1B_SFT 5
++#define RG_HPF_T1B_HI 6
++#define RG_HPF_T1B_SZ 2
++#define RG_HPF_T1C_MSK 0x00000180
++#define RG_HPF_T1C_I_MSK 0xfffffe7f
++#define RG_HPF_T1C_SFT 7
++#define RG_HPF_T1C_HI 8
++#define RG_HPF_T1C_SZ 2
++#define RG_RX_LNA_TRI_SEL_MSK 0x00000600
++#define RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
++#define RG_RX_LNA_TRI_SEL_SFT 9
++#define RG_RX_LNA_TRI_SEL_HI 10
++#define RG_RX_LNA_TRI_SEL_SZ 2
++#define RG_RX_LNA_SETTLE_MSK 0x00001800
++#define RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
++#define RG_RX_LNA_SETTLE_SFT 11
++#define RG_RX_LNA_SETTLE_HI 12
++#define RG_RX_LNA_SETTLE_SZ 2
++#define RG_TXGAIN_PHYCTRL_MSK 0x00002000
++#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffdfff
++#define RG_TXGAIN_PHYCTRL_SFT 13
++#define RG_TXGAIN_PHYCTRL_HI 13
++#define RG_TXGAIN_PHYCTRL_SZ 1
++#define RG_TX_GAIN_MSK 0x003fc000
++#define RG_TX_GAIN_I_MSK 0xffc03fff
++#define RG_TX_GAIN_SFT 14
++#define RG_TX_GAIN_HI 21
++#define RG_TX_GAIN_SZ 8
++#define RG_TXGAIN_MANUAL_MSK 0x00400000
++#define RG_TXGAIN_MANUAL_I_MSK 0xffbfffff
++#define RG_TXGAIN_MANUAL_SFT 22
++#define RG_TXGAIN_MANUAL_HI 22
++#define RG_TXGAIN_MANUAL_SZ 1
++#define RG_TX_GAIN_OFFSET_MSK 0x07800000
++#define RG_TX_GAIN_OFFSET_I_MSK 0xf87fffff
++#define RG_TX_GAIN_OFFSET_SFT 23
++#define RG_TX_GAIN_OFFSET_HI 26
++#define RG_TX_GAIN_OFFSET_SZ 4
++#define RG_ADC_CLKSEL_MSK 0x00000001
++#define RG_ADC_CLKSEL_I_MSK 0xfffffffe
++#define RG_ADC_CLKSEL_SFT 0
++#define RG_ADC_CLKSEL_HI 0
++#define RG_ADC_CLKSEL_SZ 1
++#define RG_ADC_DIBIAS_MSK 0x00000006
++#define RG_ADC_DIBIAS_I_MSK 0xfffffff9
++#define RG_ADC_DIBIAS_SFT 1
++#define RG_ADC_DIBIAS_HI 2
++#define RG_ADC_DIBIAS_SZ 2
++#define RG_ADC_DIVR_MSK 0x00000008
++#define RG_ADC_DIVR_I_MSK 0xfffffff7
++#define RG_ADC_DIVR_SFT 3
++#define RG_ADC_DIVR_HI 3
++#define RG_ADC_DIVR_SZ 1
++#define RG_ADC_DVCMI_MSK 0x00000030
++#define RG_ADC_DVCMI_I_MSK 0xffffffcf
++#define RG_ADC_DVCMI_SFT 4
++#define RG_ADC_DVCMI_HI 5
++#define RG_ADC_DVCMI_SZ 2
++#define RG_ADC_SAMSEL_MSK 0x000003c0
++#define RG_ADC_SAMSEL_I_MSK 0xfffffc3f
++#define RG_ADC_SAMSEL_SFT 6
++#define RG_ADC_SAMSEL_HI 9
++#define RG_ADC_SAMSEL_SZ 4
++#define RG_ADC_STNBY_MSK 0x00000400
++#define RG_ADC_STNBY_I_MSK 0xfffffbff
++#define RG_ADC_STNBY_SFT 10
++#define RG_ADC_STNBY_HI 10
++#define RG_ADC_STNBY_SZ 1
++#define RG_ADC_TESTMODE_MSK 0x00000800
++#define RG_ADC_TESTMODE_I_MSK 0xfffff7ff
++#define RG_ADC_TESTMODE_SFT 11
++#define RG_ADC_TESTMODE_HI 11
++#define RG_ADC_TESTMODE_SZ 1
++#define RG_ADC_TSEL_MSK 0x0000f000
++#define RG_ADC_TSEL_I_MSK 0xffff0fff
++#define RG_ADC_TSEL_SFT 12
++#define RG_ADC_TSEL_HI 15
++#define RG_ADC_TSEL_SZ 4
++#define RG_ADC_VRSEL_MSK 0x00030000
++#define RG_ADC_VRSEL_I_MSK 0xfffcffff
++#define RG_ADC_VRSEL_SFT 16
++#define RG_ADC_VRSEL_HI 17
++#define RG_ADC_VRSEL_SZ 2
++#define RG_DICMP_MSK 0x000c0000
++#define RG_DICMP_I_MSK 0xfff3ffff
++#define RG_DICMP_SFT 18
++#define RG_DICMP_HI 19
++#define RG_DICMP_SZ 2
++#define RG_DIOP_MSK 0x00300000
++#define RG_DIOP_I_MSK 0xffcfffff
++#define RG_DIOP_SFT 20
++#define RG_DIOP_HI 21
++#define RG_DIOP_SZ 2
++#define RG_SARADC_VRSEL_MSK 0x00c00000
++#define RG_SARADC_VRSEL_I_MSK 0xff3fffff
++#define RG_SARADC_VRSEL_SFT 22
++#define RG_SARADC_VRSEL_HI 23
++#define RG_SARADC_VRSEL_SZ 2
++#define RG_EN_SAR_TEST_MSK 0x03000000
++#define RG_EN_SAR_TEST_I_MSK 0xfcffffff
++#define RG_EN_SAR_TEST_SFT 24
++#define RG_EN_SAR_TEST_HI 25
++#define RG_EN_SAR_TEST_SZ 2
++#define RG_SARADC_THERMAL_MSK 0x04000000
++#define RG_SARADC_THERMAL_I_MSK 0xfbffffff
++#define RG_SARADC_THERMAL_SFT 26
++#define RG_SARADC_THERMAL_HI 26
++#define RG_SARADC_THERMAL_SZ 1
++#define RG_SARADC_TSSI_MSK 0x08000000
++#define RG_SARADC_TSSI_I_MSK 0xf7ffffff
++#define RG_SARADC_TSSI_SFT 27
++#define RG_SARADC_TSSI_HI 27
++#define RG_SARADC_TSSI_SZ 1
++#define RG_CLK_SAR_SEL_MSK 0x30000000
++#define RG_CLK_SAR_SEL_I_MSK 0xcfffffff
++#define RG_CLK_SAR_SEL_SFT 28
++#define RG_CLK_SAR_SEL_HI 29
++#define RG_CLK_SAR_SEL_SZ 2
++#define RG_EN_SARADC_MSK 0x40000000
++#define RG_EN_SARADC_I_MSK 0xbfffffff
++#define RG_EN_SARADC_SFT 30
++#define RG_EN_SARADC_HI 30
++#define RG_EN_SARADC_SZ 1
++#define RG_DACI1ST_MSK 0x00000003
++#define RG_DACI1ST_I_MSK 0xfffffffc
++#define RG_DACI1ST_SFT 0
++#define RG_DACI1ST_HI 1
++#define RG_DACI1ST_SZ 2
++#define RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
++#define RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
++#define RG_TX_DACLPF_ICOURSE_SFT 2
++#define RG_TX_DACLPF_ICOURSE_HI 3
++#define RG_TX_DACLPF_ICOURSE_SZ 2
++#define RG_TX_DACLPF_IFINE_MSK 0x00000030
++#define RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
++#define RG_TX_DACLPF_IFINE_SFT 4
++#define RG_TX_DACLPF_IFINE_HI 5
++#define RG_TX_DACLPF_IFINE_SZ 2
++#define RG_TX_DACLPF_VCM_MSK 0x000000c0
++#define RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
++#define RG_TX_DACLPF_VCM_SFT 6
++#define RG_TX_DACLPF_VCM_HI 7
++#define RG_TX_DACLPF_VCM_SZ 2
++#define RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
++#define RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
++#define RG_TX_DAC_CKEDGE_SEL_SFT 8
++#define RG_TX_DAC_CKEDGE_SEL_HI 8
++#define RG_TX_DAC_CKEDGE_SEL_SZ 1
++#define RG_TX_DAC_IBIAS_MSK 0x00000600
++#define RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
++#define RG_TX_DAC_IBIAS_SFT 9
++#define RG_TX_DAC_IBIAS_HI 10
++#define RG_TX_DAC_IBIAS_SZ 2
++#define RG_TX_DAC_OS_MSK 0x00003800
++#define RG_TX_DAC_OS_I_MSK 0xffffc7ff
++#define RG_TX_DAC_OS_SFT 11
++#define RG_TX_DAC_OS_HI 13
++#define RG_TX_DAC_OS_SZ 3
++#define RG_TX_DAC_RCAL_MSK 0x0000c000
++#define RG_TX_DAC_RCAL_I_MSK 0xffff3fff
++#define RG_TX_DAC_RCAL_SFT 14
++#define RG_TX_DAC_RCAL_HI 15
++#define RG_TX_DAC_RCAL_SZ 2
++#define RG_TX_DAC_TSEL_MSK 0x000f0000
++#define RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
++#define RG_TX_DAC_TSEL_SFT 16
++#define RG_TX_DAC_TSEL_HI 19
++#define RG_TX_DAC_TSEL_SZ 4
++#define RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
++#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
++#define RG_TX_EN_VOLTAGE_IN_SFT 20
++#define RG_TX_EN_VOLTAGE_IN_HI 20
++#define RG_TX_EN_VOLTAGE_IN_SZ 1
++#define RG_TXLPF_BYPASS_MSK 0x00200000
++#define RG_TXLPF_BYPASS_I_MSK 0xffdfffff
++#define RG_TXLPF_BYPASS_SFT 21
++#define RG_TXLPF_BYPASS_HI 21
++#define RG_TXLPF_BYPASS_SZ 1
++#define RG_TXLPF_BOOSTI_MSK 0x00400000
++#define RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
++#define RG_TXLPF_BOOSTI_SFT 22
++#define RG_TXLPF_BOOSTI_HI 22
++#define RG_TXLPF_BOOSTI_SZ 1
++#define RG_TX_DAC_IOFFSET_MSK 0x07800000
++#define RG_TX_DAC_IOFFSET_I_MSK 0xf87fffff
++#define RG_TX_DAC_IOFFSET_SFT 23
++#define RG_TX_DAC_IOFFSET_HI 26
++#define RG_TX_DAC_IOFFSET_SZ 4
++#define RG_TX_DAC_QOFFSET_MSK 0x78000000
++#define RG_TX_DAC_QOFFSET_I_MSK 0x87ffffff
++#define RG_TX_DAC_QOFFSET_SFT 27
++#define RG_TX_DAC_QOFFSET_HI 30
++#define RG_TX_DAC_QOFFSET_SZ 4
++#define RG_EN_SX_R3_MSK 0x00000001
++#define RG_EN_SX_R3_I_MSK 0xfffffffe
++#define RG_EN_SX_R3_SFT 0
++#define RG_EN_SX_R3_HI 0
++#define RG_EN_SX_R3_SZ 1
++#define RG_EN_SX_CH_MSK 0x00000002
++#define RG_EN_SX_CH_I_MSK 0xfffffffd
++#define RG_EN_SX_CH_SFT 1
++#define RG_EN_SX_CH_HI 1
++#define RG_EN_SX_CH_SZ 1
++#define RG_EN_SX_CHP_MSK 0x00000004
++#define RG_EN_SX_CHP_I_MSK 0xfffffffb
++#define RG_EN_SX_CHP_SFT 2
++#define RG_EN_SX_CHP_HI 2
++#define RG_EN_SX_CHP_SZ 1
++#define RG_EN_SX_DIVCK_MSK 0x00000008
++#define RG_EN_SX_DIVCK_I_MSK 0xfffffff7
++#define RG_EN_SX_DIVCK_SFT 3
++#define RG_EN_SX_DIVCK_HI 3
++#define RG_EN_SX_DIVCK_SZ 1
++#define RG_EN_SX_VCOBF_MSK 0x00000010
++#define RG_EN_SX_VCOBF_I_MSK 0xffffffef
++#define RG_EN_SX_VCOBF_SFT 4
++#define RG_EN_SX_VCOBF_HI 4
++#define RG_EN_SX_VCOBF_SZ 1
++#define RG_EN_SX_VCO_MSK 0x00000020
++#define RG_EN_SX_VCO_I_MSK 0xffffffdf
++#define RG_EN_SX_VCO_SFT 5
++#define RG_EN_SX_VCO_HI 5
++#define RG_EN_SX_VCO_SZ 1
++#define RG_EN_SX_MOD_MSK 0x00000040
++#define RG_EN_SX_MOD_I_MSK 0xffffffbf
++#define RG_EN_SX_MOD_SFT 6
++#define RG_EN_SX_MOD_HI 6
++#define RG_EN_SX_MOD_SZ 1
++#define RG_EN_SX_DITHER_MSK 0x00000100
++#define RG_EN_SX_DITHER_I_MSK 0xfffffeff
++#define RG_EN_SX_DITHER_SFT 8
++#define RG_EN_SX_DITHER_HI 8
++#define RG_EN_SX_DITHER_SZ 1
++#define RG_EN_SX_VT_MON_MSK 0x00000800
++#define RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
++#define RG_EN_SX_VT_MON_SFT 11
++#define RG_EN_SX_VT_MON_HI 11
++#define RG_EN_SX_VT_MON_SZ 1
++#define RG_EN_SX_VT_MON_DG_MSK 0x00001000
++#define RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
++#define RG_EN_SX_VT_MON_DG_SFT 12
++#define RG_EN_SX_VT_MON_DG_HI 12
++#define RG_EN_SX_VT_MON_DG_SZ 1
++#define RG_EN_SX_DIV_MSK 0x00002000
++#define RG_EN_SX_DIV_I_MSK 0xffffdfff
++#define RG_EN_SX_DIV_SFT 13
++#define RG_EN_SX_DIV_HI 13
++#define RG_EN_SX_DIV_SZ 1
++#define RG_EN_SX_LPF_MSK 0x00004000
++#define RG_EN_SX_LPF_I_MSK 0xffffbfff
++#define RG_EN_SX_LPF_SFT 14
++#define RG_EN_SX_LPF_HI 14
++#define RG_EN_SX_LPF_SZ 1
++#define RG_EN_DPL_MOD_MSK 0x00008000
++#define RG_EN_DPL_MOD_I_MSK 0xffff7fff
++#define RG_EN_DPL_MOD_SFT 15
++#define RG_EN_DPL_MOD_HI 15
++#define RG_EN_DPL_MOD_SZ 1
++#define RG_DPL_MOD_ORDER_MSK 0x00030000
++#define RG_DPL_MOD_ORDER_I_MSK 0xfffcffff
++#define RG_DPL_MOD_ORDER_SFT 16
++#define RG_DPL_MOD_ORDER_HI 17
++#define RG_DPL_MOD_ORDER_SZ 2
++#define RG_SX_RFCTRL_F_MSK 0x00ffffff
++#define RG_SX_RFCTRL_F_I_MSK 0xff000000
++#define RG_SX_RFCTRL_F_SFT 0
++#define RG_SX_RFCTRL_F_HI 23
++#define RG_SX_RFCTRL_F_SZ 24
++#define RG_SX_SEL_CP_MSK 0x0f000000
++#define RG_SX_SEL_CP_I_MSK 0xf0ffffff
++#define RG_SX_SEL_CP_SFT 24
++#define RG_SX_SEL_CP_HI 27
++#define RG_SX_SEL_CP_SZ 4
++#define RG_SX_SEL_CS_MSK 0xf0000000
++#define RG_SX_SEL_CS_I_MSK 0x0fffffff
++#define RG_SX_SEL_CS_SFT 28
++#define RG_SX_SEL_CS_HI 31
++#define RG_SX_SEL_CS_SZ 4
++#define RG_SX_RFCTRL_CH_MSK 0x000007ff
++#define RG_SX_RFCTRL_CH_I_MSK 0xfffff800
++#define RG_SX_RFCTRL_CH_SFT 0
++#define RG_SX_RFCTRL_CH_HI 10
++#define RG_SX_RFCTRL_CH_SZ 11
++#define RG_SX_SEL_C3_MSK 0x00007800
++#define RG_SX_SEL_C3_I_MSK 0xffff87ff
++#define RG_SX_SEL_C3_SFT 11
++#define RG_SX_SEL_C3_HI 14
++#define RG_SX_SEL_C3_SZ 4
++#define RG_SX_SEL_RS_MSK 0x000f8000
++#define RG_SX_SEL_RS_I_MSK 0xfff07fff
++#define RG_SX_SEL_RS_SFT 15
++#define RG_SX_SEL_RS_HI 19
++#define RG_SX_SEL_RS_SZ 5
++#define RG_SX_SEL_R3_MSK 0x01f00000
++#define RG_SX_SEL_R3_I_MSK 0xfe0fffff
++#define RG_SX_SEL_R3_SFT 20
++#define RG_SX_SEL_R3_HI 24
++#define RG_SX_SEL_R3_SZ 5
++#define RG_SX_SEL_ICHP_MSK 0x0000001f
++#define RG_SX_SEL_ICHP_I_MSK 0xffffffe0
++#define RG_SX_SEL_ICHP_SFT 0
++#define RG_SX_SEL_ICHP_HI 4
++#define RG_SX_SEL_ICHP_SZ 5
++#define RG_SX_SEL_PCHP_MSK 0x000003e0
++#define RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
++#define RG_SX_SEL_PCHP_SFT 5
++#define RG_SX_SEL_PCHP_HI 9
++#define RG_SX_SEL_PCHP_SZ 5
++#define RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
++#define RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
++#define RG_SX_SEL_CHP_REGOP_SFT 10
++#define RG_SX_SEL_CHP_REGOP_HI 13
++#define RG_SX_SEL_CHP_REGOP_SZ 4
++#define RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
++#define RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
++#define RG_SX_SEL_CHP_UNIOP_SFT 14
++#define RG_SX_SEL_CHP_UNIOP_HI 17
++#define RG_SX_SEL_CHP_UNIOP_SZ 4
++#define RG_SX_CHP_IOST_POL_MSK 0x00040000
++#define RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
++#define RG_SX_CHP_IOST_POL_SFT 18
++#define RG_SX_CHP_IOST_POL_HI 18
++#define RG_SX_CHP_IOST_POL_SZ 1
++#define RG_SX_CHP_IOST_MSK 0x00380000
++#define RG_SX_CHP_IOST_I_MSK 0xffc7ffff
++#define RG_SX_CHP_IOST_SFT 19
++#define RG_SX_CHP_IOST_HI 21
++#define RG_SX_CHP_IOST_SZ 3
++#define RG_SX_PFDSEL_MSK 0x00400000
++#define RG_SX_PFDSEL_I_MSK 0xffbfffff
++#define RG_SX_PFDSEL_SFT 22
++#define RG_SX_PFDSEL_HI 22
++#define RG_SX_PFDSEL_SZ 1
++#define RG_SX_PFD_SET_MSK 0x00800000
++#define RG_SX_PFD_SET_I_MSK 0xff7fffff
++#define RG_SX_PFD_SET_SFT 23
++#define RG_SX_PFD_SET_HI 23
++#define RG_SX_PFD_SET_SZ 1
++#define RG_SX_PFD_SET1_MSK 0x01000000
++#define RG_SX_PFD_SET1_I_MSK 0xfeffffff
++#define RG_SX_PFD_SET1_SFT 24
++#define RG_SX_PFD_SET1_HI 24
++#define RG_SX_PFD_SET1_SZ 1
++#define RG_SX_PFD_SET2_MSK 0x02000000
++#define RG_SX_PFD_SET2_I_MSK 0xfdffffff
++#define RG_SX_PFD_SET2_SFT 25
++#define RG_SX_PFD_SET2_HI 25
++#define RG_SX_PFD_SET2_SZ 1
++#define RG_SX_VBNCAS_SEL_MSK 0x04000000
++#define RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
++#define RG_SX_VBNCAS_SEL_SFT 26
++#define RG_SX_VBNCAS_SEL_HI 26
++#define RG_SX_VBNCAS_SEL_SZ 1
++#define RG_SX_PFD_RST_H_MSK 0x08000000
++#define RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
++#define RG_SX_PFD_RST_H_SFT 27
++#define RG_SX_PFD_RST_H_HI 27
++#define RG_SX_PFD_RST_H_SZ 1
++#define RG_SX_PFD_TRUP_MSK 0x10000000
++#define RG_SX_PFD_TRUP_I_MSK 0xefffffff
++#define RG_SX_PFD_TRUP_SFT 28
++#define RG_SX_PFD_TRUP_HI 28
++#define RG_SX_PFD_TRUP_SZ 1
++#define RG_SX_PFD_TRDN_MSK 0x20000000
++#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff
++#define RG_SX_PFD_TRDN_SFT 29
++#define RG_SX_PFD_TRDN_HI 29
++#define RG_SX_PFD_TRDN_SZ 1
++#define RG_SX_PFD_TRSEL_MSK 0x40000000
++#define RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
++#define RG_SX_PFD_TRSEL_SFT 30
++#define RG_SX_PFD_TRSEL_HI 30
++#define RG_SX_PFD_TRSEL_SZ 1
++#define RG_SX_VCOBA_R_MSK 0x00000007
++#define RG_SX_VCOBA_R_I_MSK 0xfffffff8
++#define RG_SX_VCOBA_R_SFT 0
++#define RG_SX_VCOBA_R_HI 2
++#define RG_SX_VCOBA_R_SZ 3
++#define RG_SX_VCORSEL_MSK 0x000000f8
++#define RG_SX_VCORSEL_I_MSK 0xffffff07
++#define RG_SX_VCORSEL_SFT 3
++#define RG_SX_VCORSEL_HI 7
++#define RG_SX_VCORSEL_SZ 5
++#define RG_SX_VCOCUSEL_MSK 0x00000f00
++#define RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
++#define RG_SX_VCOCUSEL_SFT 8
++#define RG_SX_VCOCUSEL_HI 11
++#define RG_SX_VCOCUSEL_SZ 4
++#define RG_SX_RXBFSEL_MSK 0x0000f000
++#define RG_SX_RXBFSEL_I_MSK 0xffff0fff
++#define RG_SX_RXBFSEL_SFT 12
++#define RG_SX_RXBFSEL_HI 15
++#define RG_SX_RXBFSEL_SZ 4
++#define RG_SX_TXBFSEL_MSK 0x000f0000
++#define RG_SX_TXBFSEL_I_MSK 0xfff0ffff
++#define RG_SX_TXBFSEL_SFT 16
++#define RG_SX_TXBFSEL_HI 19
++#define RG_SX_TXBFSEL_SZ 4
++#define RG_SX_VCOBFSEL_MSK 0x00f00000
++#define RG_SX_VCOBFSEL_I_MSK 0xff0fffff
++#define RG_SX_VCOBFSEL_SFT 20
++#define RG_SX_VCOBFSEL_HI 23
++#define RG_SX_VCOBFSEL_SZ 4
++#define RG_SX_DIVBFSEL_MSK 0x0f000000
++#define RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
++#define RG_SX_DIVBFSEL_SFT 24
++#define RG_SX_DIVBFSEL_HI 27
++#define RG_SX_DIVBFSEL_SZ 4
++#define RG_SX_GNDR_SEL_MSK 0xf0000000
++#define RG_SX_GNDR_SEL_I_MSK 0x0fffffff
++#define RG_SX_GNDR_SEL_SFT 28
++#define RG_SX_GNDR_SEL_HI 31
++#define RG_SX_GNDR_SEL_SZ 4
++#define RG_SX_DITHER_WEIGHT_MSK 0x00000003
++#define RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
++#define RG_SX_DITHER_WEIGHT_SFT 0
++#define RG_SX_DITHER_WEIGHT_HI 1
++#define RG_SX_DITHER_WEIGHT_SZ 2
++#define RG_SX_MOD_ORDER_MSK 0x00000030
++#define RG_SX_MOD_ORDER_I_MSK 0xffffffcf
++#define RG_SX_MOD_ORDER_SFT 4
++#define RG_SX_MOD_ORDER_HI 5
++#define RG_SX_MOD_ORDER_SZ 2
++#define RG_SX_RST_H_DIV_MSK 0x00000200
++#define RG_SX_RST_H_DIV_I_MSK 0xfffffdff
++#define RG_SX_RST_H_DIV_SFT 9
++#define RG_SX_RST_H_DIV_HI 9
++#define RG_SX_RST_H_DIV_SZ 1
++#define RG_SX_SDM_EDGE_MSK 0x00000400
++#define RG_SX_SDM_EDGE_I_MSK 0xfffffbff
++#define RG_SX_SDM_EDGE_SFT 10
++#define RG_SX_SDM_EDGE_HI 10
++#define RG_SX_SDM_EDGE_SZ 1
++#define RG_SX_XO_GM_MSK 0x00001800
++#define RG_SX_XO_GM_I_MSK 0xffffe7ff
++#define RG_SX_XO_GM_SFT 11
++#define RG_SX_XO_GM_HI 12
++#define RG_SX_XO_GM_SZ 2
++#define RG_SX_REFBYTWO_MSK 0x00002000
++#define RG_SX_REFBYTWO_I_MSK 0xffffdfff
++#define RG_SX_REFBYTWO_SFT 13
++#define RG_SX_REFBYTWO_HI 13
++#define RG_SX_REFBYTWO_SZ 1
++#define RG_SX_LCKEN_MSK 0x00080000
++#define RG_SX_LCKEN_I_MSK 0xfff7ffff
++#define RG_SX_LCKEN_SFT 19
++#define RG_SX_LCKEN_HI 19
++#define RG_SX_LCKEN_SZ 1
++#define RG_SX_PREVDD_MSK 0x00f00000
++#define RG_SX_PREVDD_I_MSK 0xff0fffff
++#define RG_SX_PREVDD_SFT 20
++#define RG_SX_PREVDD_HI 23
++#define RG_SX_PREVDD_SZ 4
++#define RG_SX_PSCONTERVDD_MSK 0x0f000000
++#define RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
++#define RG_SX_PSCONTERVDD_SFT 24
++#define RG_SX_PSCONTERVDD_HI 27
++#define RG_SX_PSCONTERVDD_SZ 4
++#define RG_SX_PH_MSK 0x00002000
++#define RG_SX_PH_I_MSK 0xffffdfff
++#define RG_SX_PH_SFT 13
++#define RG_SX_PH_HI 13
++#define RG_SX_PH_SZ 1
++#define RG_SX_PL_MSK 0x00004000
++#define RG_SX_PL_I_MSK 0xffffbfff
++#define RG_SX_PL_SFT 14
++#define RG_SX_PL_HI 14
++#define RG_SX_PL_SZ 1
++#define RG_XOSC_CBANK_XO_MSK 0x00078000
++#define RG_XOSC_CBANK_XO_I_MSK 0xfff87fff
++#define RG_XOSC_CBANK_XO_SFT 15
++#define RG_XOSC_CBANK_XO_HI 18
++#define RG_XOSC_CBANK_XO_SZ 4
++#define RG_XOSC_CBANK_XI_MSK 0x00780000
++#define RG_XOSC_CBANK_XI_I_MSK 0xff87ffff
++#define RG_XOSC_CBANK_XI_SFT 19
++#define RG_XOSC_CBANK_XI_HI 22
++#define RG_XOSC_CBANK_XI_SZ 4
++#define RG_SX_VT_MON_MODE_MSK 0x00000001
++#define RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
++#define RG_SX_VT_MON_MODE_SFT 0
++#define RG_SX_VT_MON_MODE_HI 0
++#define RG_SX_VT_MON_MODE_SZ 1
++#define RG_SX_VT_TH_HI_MSK 0x00000006
++#define RG_SX_VT_TH_HI_I_MSK 0xfffffff9
++#define RG_SX_VT_TH_HI_SFT 1
++#define RG_SX_VT_TH_HI_HI 2
++#define RG_SX_VT_TH_HI_SZ 2
++#define RG_SX_VT_TH_LO_MSK 0x00000018
++#define RG_SX_VT_TH_LO_I_MSK 0xffffffe7
++#define RG_SX_VT_TH_LO_SFT 3
++#define RG_SX_VT_TH_LO_HI 4
++#define RG_SX_VT_TH_LO_SZ 2
++#define RG_SX_VT_SET_MSK 0x00000020
++#define RG_SX_VT_SET_I_MSK 0xffffffdf
++#define RG_SX_VT_SET_SFT 5
++#define RG_SX_VT_SET_HI 5
++#define RG_SX_VT_SET_SZ 1
++#define RG_SX_VT_MON_TMR_MSK 0x00007fc0
++#define RG_SX_VT_MON_TMR_I_MSK 0xffff803f
++#define RG_SX_VT_MON_TMR_SFT 6
++#define RG_SX_VT_MON_TMR_HI 14
++#define RG_SX_VT_MON_TMR_SZ 9
++#define RG_EN_DP_VT_MON_MSK 0x00000001
++#define RG_EN_DP_VT_MON_I_MSK 0xfffffffe
++#define RG_EN_DP_VT_MON_SFT 0
++#define RG_EN_DP_VT_MON_HI 0
++#define RG_EN_DP_VT_MON_SZ 1
++#define RG_DP_VT_TH_HI_MSK 0x00000006
++#define RG_DP_VT_TH_HI_I_MSK 0xfffffff9
++#define RG_DP_VT_TH_HI_SFT 1
++#define RG_DP_VT_TH_HI_HI 2
++#define RG_DP_VT_TH_HI_SZ 2
++#define RG_DP_VT_TH_LO_MSK 0x00000018
++#define RG_DP_VT_TH_LO_I_MSK 0xffffffe7
++#define RG_DP_VT_TH_LO_SFT 3
++#define RG_DP_VT_TH_LO_HI 4
++#define RG_DP_VT_TH_LO_SZ 2
++#define RG_DP_CK320BY2_MSK 0x00004000
++#define RG_DP_CK320BY2_I_MSK 0xffffbfff
++#define RG_DP_CK320BY2_SFT 14
++#define RG_DP_CK320BY2_HI 14
++#define RG_DP_CK320BY2_SZ 1
++#define RG_DP_OD_TEST_MSK 0x00200000
++#define RG_DP_OD_TEST_I_MSK 0xffdfffff
++#define RG_DP_OD_TEST_SFT 21
++#define RG_DP_OD_TEST_HI 21
++#define RG_DP_OD_TEST_SZ 1
++#define RG_DP_BBPLL_BP_MSK 0x00000001
++#define RG_DP_BBPLL_BP_I_MSK 0xfffffffe
++#define RG_DP_BBPLL_BP_SFT 0
++#define RG_DP_BBPLL_BP_HI 0
++#define RG_DP_BBPLL_BP_SZ 1
++#define RG_DP_BBPLL_ICP_MSK 0x00000006
++#define RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
++#define RG_DP_BBPLL_ICP_SFT 1
++#define RG_DP_BBPLL_ICP_HI 2
++#define RG_DP_BBPLL_ICP_SZ 2
++#define RG_DP_BBPLL_IDUAL_MSK 0x00000018
++#define RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
++#define RG_DP_BBPLL_IDUAL_SFT 3
++#define RG_DP_BBPLL_IDUAL_HI 4
++#define RG_DP_BBPLL_IDUAL_SZ 2
++#define RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
++#define RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
++#define RG_DP_BBPLL_OD_TEST_SFT 5
++#define RG_DP_BBPLL_OD_TEST_HI 8
++#define RG_DP_BBPLL_OD_TEST_SZ 4
++#define RG_DP_BBPLL_PD_MSK 0x00000200
++#define RG_DP_BBPLL_PD_I_MSK 0xfffffdff
++#define RG_DP_BBPLL_PD_SFT 9
++#define RG_DP_BBPLL_PD_HI 9
++#define RG_DP_BBPLL_PD_SZ 1
++#define RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
++#define RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
++#define RG_DP_BBPLL_TESTSEL_SFT 10
++#define RG_DP_BBPLL_TESTSEL_HI 12
++#define RG_DP_BBPLL_TESTSEL_SZ 3
++#define RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
++#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
++#define RG_DP_BBPLL_PFD_DLY_SFT 13
++#define RG_DP_BBPLL_PFD_DLY_HI 14
++#define RG_DP_BBPLL_PFD_DLY_SZ 2
++#define RG_DP_RP_MSK 0x00038000
++#define RG_DP_RP_I_MSK 0xfffc7fff
++#define RG_DP_RP_SFT 15
++#define RG_DP_RP_HI 17
++#define RG_DP_RP_SZ 3
++#define RG_DP_RHP_MSK 0x000c0000
++#define RG_DP_RHP_I_MSK 0xfff3ffff
++#define RG_DP_RHP_SFT 18
++#define RG_DP_RHP_HI 19
++#define RG_DP_RHP_SZ 2
++#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000
++#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
++#define RG_DP_BBPLL_SDM_EDGE_SFT 31
++#define RG_DP_BBPLL_SDM_EDGE_HI 31
++#define RG_DP_BBPLL_SDM_EDGE_SZ 1
++#define RG_DP_FODIV_MSK 0x0007f000
++#define RG_DP_FODIV_I_MSK 0xfff80fff
++#define RG_DP_FODIV_SFT 12
++#define RG_DP_FODIV_HI 18
++#define RG_DP_FODIV_SZ 7
++#define RG_DP_REFDIV_MSK 0x1fc00000
++#define RG_DP_REFDIV_I_MSK 0xe03fffff
++#define RG_DP_REFDIV_SFT 22
++#define RG_DP_REFDIV_HI 28
++#define RG_DP_REFDIV_SZ 7
++#define RG_IDACAI_PGAG15_MSK 0x0000003f
++#define RG_IDACAI_PGAG15_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG15_SFT 0
++#define RG_IDACAI_PGAG15_HI 5
++#define RG_IDACAI_PGAG15_SZ 6
++#define RG_IDACAQ_PGAG15_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG15_SFT 6
++#define RG_IDACAQ_PGAG15_HI 11
++#define RG_IDACAQ_PGAG15_SZ 6
++#define RG_IDACAI_PGAG14_MSK 0x0003f000
++#define RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG14_SFT 12
++#define RG_IDACAI_PGAG14_HI 17
++#define RG_IDACAI_PGAG14_SZ 6
++#define RG_IDACAQ_PGAG14_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG14_SFT 18
++#define RG_IDACAQ_PGAG14_HI 23
++#define RG_IDACAQ_PGAG14_SZ 6
++#define RG_DP_BBPLL_BS_MSK 0x3f000000
++#define RG_DP_BBPLL_BS_I_MSK 0xc0ffffff
++#define RG_DP_BBPLL_BS_SFT 24
++#define RG_DP_BBPLL_BS_HI 29
++#define RG_DP_BBPLL_BS_SZ 6
++#define RG_IDACAI_PGAG13_MSK 0x0000003f
++#define RG_IDACAI_PGAG13_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG13_SFT 0
++#define RG_IDACAI_PGAG13_HI 5
++#define RG_IDACAI_PGAG13_SZ 6
++#define RG_IDACAQ_PGAG13_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG13_SFT 6
++#define RG_IDACAQ_PGAG13_HI 11
++#define RG_IDACAQ_PGAG13_SZ 6
++#define RG_IDACAI_PGAG12_MSK 0x0003f000
++#define RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG12_SFT 12
++#define RG_IDACAI_PGAG12_HI 17
++#define RG_IDACAI_PGAG12_SZ 6
++#define RG_IDACAQ_PGAG12_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG12_SFT 18
++#define RG_IDACAQ_PGAG12_HI 23
++#define RG_IDACAQ_PGAG12_SZ 6
++#define RG_IDACAI_PGAG11_MSK 0x0000003f
++#define RG_IDACAI_PGAG11_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG11_SFT 0
++#define RG_IDACAI_PGAG11_HI 5
++#define RG_IDACAI_PGAG11_SZ 6
++#define RG_IDACAQ_PGAG11_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG11_SFT 6
++#define RG_IDACAQ_PGAG11_HI 11
++#define RG_IDACAQ_PGAG11_SZ 6
++#define RG_IDACAI_PGAG10_MSK 0x0003f000
++#define RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG10_SFT 12
++#define RG_IDACAI_PGAG10_HI 17
++#define RG_IDACAI_PGAG10_SZ 6
++#define RG_IDACAQ_PGAG10_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG10_SFT 18
++#define RG_IDACAQ_PGAG10_HI 23
++#define RG_IDACAQ_PGAG10_SZ 6
++#define RG_IDACAI_PGAG9_MSK 0x0000003f
++#define RG_IDACAI_PGAG9_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG9_SFT 0
++#define RG_IDACAI_PGAG9_HI 5
++#define RG_IDACAI_PGAG9_SZ 6
++#define RG_IDACAQ_PGAG9_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG9_SFT 6
++#define RG_IDACAQ_PGAG9_HI 11
++#define RG_IDACAQ_PGAG9_SZ 6
++#define RG_IDACAI_PGAG8_MSK 0x0003f000
++#define RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG8_SFT 12
++#define RG_IDACAI_PGAG8_HI 17
++#define RG_IDACAI_PGAG8_SZ 6
++#define RG_IDACAQ_PGAG8_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG8_SFT 18
++#define RG_IDACAQ_PGAG8_HI 23
++#define RG_IDACAQ_PGAG8_SZ 6
++#define RG_IDACAI_PGAG7_MSK 0x0000003f
++#define RG_IDACAI_PGAG7_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG7_SFT 0
++#define RG_IDACAI_PGAG7_HI 5
++#define RG_IDACAI_PGAG7_SZ 6
++#define RG_IDACAQ_PGAG7_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG7_SFT 6
++#define RG_IDACAQ_PGAG7_HI 11
++#define RG_IDACAQ_PGAG7_SZ 6
++#define RG_IDACAI_PGAG6_MSK 0x0003f000
++#define RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG6_SFT 12
++#define RG_IDACAI_PGAG6_HI 17
++#define RG_IDACAI_PGAG6_SZ 6
++#define RG_IDACAQ_PGAG6_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG6_SFT 18
++#define RG_IDACAQ_PGAG6_HI 23
++#define RG_IDACAQ_PGAG6_SZ 6
++#define RG_IDACAI_PGAG5_MSK 0x0000003f
++#define RG_IDACAI_PGAG5_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG5_SFT 0
++#define RG_IDACAI_PGAG5_HI 5
++#define RG_IDACAI_PGAG5_SZ 6
++#define RG_IDACAQ_PGAG5_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG5_SFT 6
++#define RG_IDACAQ_PGAG5_HI 11
++#define RG_IDACAQ_PGAG5_SZ 6
++#define RG_IDACAI_PGAG4_MSK 0x0003f000
++#define RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG4_SFT 12
++#define RG_IDACAI_PGAG4_HI 17
++#define RG_IDACAI_PGAG4_SZ 6
++#define RG_IDACAQ_PGAG4_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG4_SFT 18
++#define RG_IDACAQ_PGAG4_HI 23
++#define RG_IDACAQ_PGAG4_SZ 6
++#define RG_IDACAI_PGAG3_MSK 0x0000003f
++#define RG_IDACAI_PGAG3_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG3_SFT 0
++#define RG_IDACAI_PGAG3_HI 5
++#define RG_IDACAI_PGAG3_SZ 6
++#define RG_IDACAQ_PGAG3_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG3_SFT 6
++#define RG_IDACAQ_PGAG3_HI 11
++#define RG_IDACAQ_PGAG3_SZ 6
++#define RG_IDACAI_PGAG2_MSK 0x0003f000
++#define RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG2_SFT 12
++#define RG_IDACAI_PGAG2_HI 17
++#define RG_IDACAI_PGAG2_SZ 6
++#define RG_IDACAQ_PGAG2_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG2_SFT 18
++#define RG_IDACAQ_PGAG2_HI 23
++#define RG_IDACAQ_PGAG2_SZ 6
++#define RG_IDACAI_PGAG1_MSK 0x0000003f
++#define RG_IDACAI_PGAG1_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG1_SFT 0
++#define RG_IDACAI_PGAG1_HI 5
++#define RG_IDACAI_PGAG1_SZ 6
++#define RG_IDACAQ_PGAG1_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG1_SFT 6
++#define RG_IDACAQ_PGAG1_HI 11
++#define RG_IDACAQ_PGAG1_SZ 6
++#define RG_IDACAI_PGAG0_MSK 0x0003f000
++#define RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG0_SFT 12
++#define RG_IDACAI_PGAG0_HI 17
++#define RG_IDACAI_PGAG0_SZ 6
++#define RG_IDACAQ_PGAG0_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG0_SFT 18
++#define RG_IDACAQ_PGAG0_HI 23
++#define RG_IDACAQ_PGAG0_SZ 6
++#define RG_EN_RCAL_MSK 0x00000001
++#define RG_EN_RCAL_I_MSK 0xfffffffe
++#define RG_EN_RCAL_SFT 0
++#define RG_EN_RCAL_HI 0
++#define RG_EN_RCAL_SZ 1
++#define RG_RCAL_SPD_MSK 0x00000002
++#define RG_RCAL_SPD_I_MSK 0xfffffffd
++#define RG_RCAL_SPD_SFT 1
++#define RG_RCAL_SPD_HI 1
++#define RG_RCAL_SPD_SZ 1
++#define RG_RCAL_TMR_MSK 0x000001fc
++#define RG_RCAL_TMR_I_MSK 0xfffffe03
++#define RG_RCAL_TMR_SFT 2
++#define RG_RCAL_TMR_HI 8
++#define RG_RCAL_TMR_SZ 7
++#define RG_RCAL_CODE_CWR_MSK 0x00000200
++#define RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
++#define RG_RCAL_CODE_CWR_SFT 9
++#define RG_RCAL_CODE_CWR_HI 9
++#define RG_RCAL_CODE_CWR_SZ 1
++#define RG_RCAL_CODE_CWD_MSK 0x00007c00
++#define RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
++#define RG_RCAL_CODE_CWD_SFT 10
++#define RG_RCAL_CODE_CWD_HI 14
++#define RG_RCAL_CODE_CWD_SZ 5
++#define RG_SX_SUB_SEL_CWR_MSK 0x00000001
++#define RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
++#define RG_SX_SUB_SEL_CWR_SFT 0
++#define RG_SX_SUB_SEL_CWR_HI 0
++#define RG_SX_SUB_SEL_CWR_SZ 1
++#define RG_SX_SUB_SEL_CWD_MSK 0x000000fe
++#define RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
++#define RG_SX_SUB_SEL_CWD_SFT 1
++#define RG_SX_SUB_SEL_CWD_HI 7
++#define RG_SX_SUB_SEL_CWD_SZ 7
++#define RG_SX_LCK_BIN_OFFSET_MSK 0x00078000
++#define RG_SX_LCK_BIN_OFFSET_I_MSK 0xfff87fff
++#define RG_SX_LCK_BIN_OFFSET_SFT 15
++#define RG_SX_LCK_BIN_OFFSET_HI 18
++#define RG_SX_LCK_BIN_OFFSET_SZ 4
++#define RG_SX_LCK_BIN_PRECISION_MSK 0x00080000
++#define RG_SX_LCK_BIN_PRECISION_I_MSK 0xfff7ffff
++#define RG_SX_LCK_BIN_PRECISION_SFT 19
++#define RG_SX_LCK_BIN_PRECISION_HI 19
++#define RG_SX_LCK_BIN_PRECISION_SZ 1
++#define RG_SX_LOCK_EN_N_MSK 0x00100000
++#define RG_SX_LOCK_EN_N_I_MSK 0xffefffff
++#define RG_SX_LOCK_EN_N_SFT 20
++#define RG_SX_LOCK_EN_N_HI 20
++#define RG_SX_LOCK_EN_N_SZ 1
++#define RG_SX_LOCK_MANUAL_MSK 0x00200000
++#define RG_SX_LOCK_MANUAL_I_MSK 0xffdfffff
++#define RG_SX_LOCK_MANUAL_SFT 21
++#define RG_SX_LOCK_MANUAL_HI 21
++#define RG_SX_LOCK_MANUAL_SZ 1
++#define RG_SX_SUB_MANUAL_MSK 0x00400000
++#define RG_SX_SUB_MANUAL_I_MSK 0xffbfffff
++#define RG_SX_SUB_MANUAL_SFT 22
++#define RG_SX_SUB_MANUAL_HI 22
++#define RG_SX_SUB_MANUAL_SZ 1
++#define RG_SX_SUB_SEL_MSK 0x3f800000
++#define RG_SX_SUB_SEL_I_MSK 0xc07fffff
++#define RG_SX_SUB_SEL_SFT 23
++#define RG_SX_SUB_SEL_HI 29
++#define RG_SX_SUB_SEL_SZ 7
++#define RG_SX_MUX_SEL_VTH_BINL_MSK 0x40000000
++#define RG_SX_MUX_SEL_VTH_BINL_I_MSK 0xbfffffff
++#define RG_SX_MUX_SEL_VTH_BINL_SFT 30
++#define RG_SX_MUX_SEL_VTH_BINL_HI 30
++#define RG_SX_MUX_SEL_VTH_BINL_SZ 1
++#define RG_TRX_DUMMMY_MSK 0xffffffff
++#define RG_TRX_DUMMMY_I_MSK 0x00000000
++#define RG_TRX_DUMMMY_SFT 0
++#define RG_TRX_DUMMMY_HI 31
++#define RG_TRX_DUMMMY_SZ 32
++#define RG_SX_DUMMMY_MSK 0xffffffff
++#define RG_SX_DUMMMY_I_MSK 0x00000000
++#define RG_SX_DUMMMY_SFT 0
++#define RG_SX_DUMMMY_HI 31
++#define RG_SX_DUMMMY_SZ 32
++#define RCAL_RDY_MSK 0x00000001
++#define RCAL_RDY_I_MSK 0xfffffffe
++#define RCAL_RDY_SFT 0
++#define RCAL_RDY_HI 0
++#define RCAL_RDY_SZ 1
++#define LCK_BIN_RDY_MSK 0x00000002
++#define LCK_BIN_RDY_I_MSK 0xfffffffd
++#define LCK_BIN_RDY_SFT 1
++#define LCK_BIN_RDY_HI 1
++#define LCK_BIN_RDY_SZ 1
++#define VT_MON_RDY_MSK 0x00000004
++#define VT_MON_RDY_I_MSK 0xfffffffb
++#define VT_MON_RDY_SFT 2
++#define VT_MON_RDY_HI 2
++#define VT_MON_RDY_SZ 1
++#define DA_R_CODE_LUT_MSK 0x000007c0
++#define DA_R_CODE_LUT_I_MSK 0xfffff83f
++#define DA_R_CODE_LUT_SFT 6
++#define DA_R_CODE_LUT_HI 10
++#define DA_R_CODE_LUT_SZ 5
++#define AD_SX_VT_MON_Q_MSK 0x00001800
++#define AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
++#define AD_SX_VT_MON_Q_SFT 11
++#define AD_SX_VT_MON_Q_HI 12
++#define AD_SX_VT_MON_Q_SZ 2
++#define AD_DP_VT_MON_Q_MSK 0x00006000
++#define AD_DP_VT_MON_Q_I_MSK 0xffff9fff
++#define AD_DP_VT_MON_Q_SFT 13
++#define AD_DP_VT_MON_Q_HI 14
++#define AD_DP_VT_MON_Q_SZ 2
++#define RTC_CAL_RDY_MSK 0x00008000
++#define RTC_CAL_RDY_I_MSK 0xffff7fff
++#define RTC_CAL_RDY_SFT 15
++#define RTC_CAL_RDY_HI 15
++#define RTC_CAL_RDY_SZ 1
++#define RG_SARADC_BIT_MSK 0x003f0000
++#define RG_SARADC_BIT_I_MSK 0xffc0ffff
++#define RG_SARADC_BIT_SFT 16
++#define RG_SARADC_BIT_HI 21
++#define RG_SARADC_BIT_SZ 6
++#define SAR_ADC_FSM_RDY_MSK 0x00400000
++#define SAR_ADC_FSM_RDY_I_MSK 0xffbfffff
++#define SAR_ADC_FSM_RDY_SFT 22
++#define SAR_ADC_FSM_RDY_HI 22
++#define SAR_ADC_FSM_RDY_SZ 1
++#define AD_CIRCUIT_VERSION_MSK 0x07800000
++#define AD_CIRCUIT_VERSION_I_MSK 0xf87fffff
++#define AD_CIRCUIT_VERSION_SFT 23
++#define AD_CIRCUIT_VERSION_HI 26
++#define AD_CIRCUIT_VERSION_SZ 4
++#define DA_R_CAL_CODE_MSK 0x0000001f
++#define DA_R_CAL_CODE_I_MSK 0xffffffe0
++#define DA_R_CAL_CODE_SFT 0
++#define DA_R_CAL_CODE_HI 4
++#define DA_R_CAL_CODE_SZ 5
++#define DA_SX_SUB_SEL_MSK 0x00000fe0
++#define DA_SX_SUB_SEL_I_MSK 0xfffff01f
++#define DA_SX_SUB_SEL_SFT 5
++#define DA_SX_SUB_SEL_HI 11
++#define DA_SX_SUB_SEL_SZ 7
++#define RG_DPL_RFCTRL_CH_MSK 0x000007ff
++#define RG_DPL_RFCTRL_CH_I_MSK 0xfffff800
++#define RG_DPL_RFCTRL_CH_SFT 0
++#define RG_DPL_RFCTRL_CH_HI 10
++#define RG_DPL_RFCTRL_CH_SZ 11
++#define RG_RSSIADC_RO_BIT_MSK 0x00007800
++#define RG_RSSIADC_RO_BIT_I_MSK 0xffff87ff
++#define RG_RSSIADC_RO_BIT_SFT 11
++#define RG_RSSIADC_RO_BIT_HI 14
++#define RG_RSSIADC_RO_BIT_SZ 4
++#define RG_RX_ADC_I_RO_BIT_MSK 0x007f8000
++#define RG_RX_ADC_I_RO_BIT_I_MSK 0xff807fff
++#define RG_RX_ADC_I_RO_BIT_SFT 15
++#define RG_RX_ADC_I_RO_BIT_HI 22
++#define RG_RX_ADC_I_RO_BIT_SZ 8
++#define RG_RX_ADC_Q_RO_BIT_MSK 0x7f800000
++#define RG_RX_ADC_Q_RO_BIT_I_MSK 0x807fffff
++#define RG_RX_ADC_Q_RO_BIT_SFT 23
++#define RG_RX_ADC_Q_RO_BIT_HI 30
++#define RG_RX_ADC_Q_RO_BIT_SZ 8
++#define RG_DPL_RFCTRL_F_MSK 0x00ffffff
++#define RG_DPL_RFCTRL_F_I_MSK 0xff000000
++#define RG_DPL_RFCTRL_F_SFT 0
++#define RG_DPL_RFCTRL_F_HI 23
++#define RG_DPL_RFCTRL_F_SZ 24
++#define RG_SX_TARGET_CNT_MSK 0x00001fff
++#define RG_SX_TARGET_CNT_I_MSK 0xffffe000
++#define RG_SX_TARGET_CNT_SFT 0
++#define RG_SX_TARGET_CNT_HI 12
++#define RG_SX_TARGET_CNT_SZ 13
++#define RG_RTC_OFFSET_MSK 0x000000ff
++#define RG_RTC_OFFSET_I_MSK 0xffffff00
++#define RG_RTC_OFFSET_SFT 0
++#define RG_RTC_OFFSET_HI 7
++#define RG_RTC_OFFSET_SZ 8
++#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
++#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
++#define RG_RTC_CAL_TARGET_COUNT_SFT 8
++#define RG_RTC_CAL_TARGET_COUNT_HI 19
++#define RG_RTC_CAL_TARGET_COUNT_SZ 12
++#define RG_RF_D_REG_MSK 0x0000ffff
++#define RG_RF_D_REG_I_MSK 0xffff0000
++#define RG_RF_D_REG_SFT 0
++#define RG_RF_D_REG_HI 15
++#define RG_RF_D_REG_SZ 16
++#define DIRECT_MODE_MSK 0x00000001
++#define DIRECT_MODE_I_MSK 0xfffffffe
++#define DIRECT_MODE_SFT 0
++#define DIRECT_MODE_HI 0
++#define DIRECT_MODE_SZ 1
++#define TAG_INTERLEAVE_MD_MSK 0x00000002
++#define TAG_INTERLEAVE_MD_I_MSK 0xfffffffd
++#define TAG_INTERLEAVE_MD_SFT 1
++#define TAG_INTERLEAVE_MD_HI 1
++#define TAG_INTERLEAVE_MD_SZ 1
++#define DIS_DEMAND_MSK 0x00000004
++#define DIS_DEMAND_I_MSK 0xfffffffb
++#define DIS_DEMAND_SFT 2
++#define DIS_DEMAND_HI 2
++#define DIS_DEMAND_SZ 1
++#define SAME_ID_ALLOC_MD_MSK 0x00000008
++#define SAME_ID_ALLOC_MD_I_MSK 0xfffffff7
++#define SAME_ID_ALLOC_MD_SFT 3
++#define SAME_ID_ALLOC_MD_HI 3
++#define SAME_ID_ALLOC_MD_SZ 1
++#define HS_ACCESS_MD_MSK 0x00000010
++#define HS_ACCESS_MD_I_MSK 0xffffffef
++#define HS_ACCESS_MD_SFT 4
++#define HS_ACCESS_MD_HI 4
++#define HS_ACCESS_MD_SZ 1
++#define SRAM_ACCESS_MD_MSK 0x00000020
++#define SRAM_ACCESS_MD_I_MSK 0xffffffdf
++#define SRAM_ACCESS_MD_SFT 5
++#define SRAM_ACCESS_MD_HI 5
++#define SRAM_ACCESS_MD_SZ 1
++#define NOHIT_RPASS_MD_MSK 0x00000040
++#define NOHIT_RPASS_MD_I_MSK 0xffffffbf
++#define NOHIT_RPASS_MD_SFT 6
++#define NOHIT_RPASS_MD_HI 6
++#define NOHIT_RPASS_MD_SZ 1
++#define DMN_FLAG_CLR_MSK 0x00000080
++#define DMN_FLAG_CLR_I_MSK 0xffffff7f
++#define DMN_FLAG_CLR_SFT 7
++#define DMN_FLAG_CLR_HI 7
++#define DMN_FLAG_CLR_SZ 1
++#define ERR_SW_RST_N_MSK 0x00000100
++#define ERR_SW_RST_N_I_MSK 0xfffffeff
++#define ERR_SW_RST_N_SFT 8
++#define ERR_SW_RST_N_HI 8
++#define ERR_SW_RST_N_SZ 1
++#define ALR_SW_RST_N_MSK 0x00000200
++#define ALR_SW_RST_N_I_MSK 0xfffffdff
++#define ALR_SW_RST_N_SFT 9
++#define ALR_SW_RST_N_HI 9
++#define ALR_SW_RST_N_SZ 1
++#define MCH_SW_RST_N_MSK 0x00000400
++#define MCH_SW_RST_N_I_MSK 0xfffffbff
++#define MCH_SW_RST_N_SFT 10
++#define MCH_SW_RST_N_HI 10
++#define MCH_SW_RST_N_SZ 1
++#define TAG_SW_RST_N_MSK 0x00000800
++#define TAG_SW_RST_N_I_MSK 0xfffff7ff
++#define TAG_SW_RST_N_SFT 11
++#define TAG_SW_RST_N_HI 11
++#define TAG_SW_RST_N_SZ 1
++#define ABT_SW_RST_N_MSK 0x00001000
++#define ABT_SW_RST_N_I_MSK 0xffffefff
++#define ABT_SW_RST_N_SFT 12
++#define ABT_SW_RST_N_HI 12
++#define ABT_SW_RST_N_SZ 1
++#define MMU_VER_MSK 0x0000e000
++#define MMU_VER_I_MSK 0xffff1fff
++#define MMU_VER_SFT 13
++#define MMU_VER_HI 15
++#define MMU_VER_SZ 3
++#define MMU_SHARE_MCU_MSK 0x00ff0000
++#define MMU_SHARE_MCU_I_MSK 0xff00ffff
++#define MMU_SHARE_MCU_SFT 16
++#define MMU_SHARE_MCU_HI 23
++#define MMU_SHARE_MCU_SZ 8
++#define HS_WR_MSK 0x00000001
++#define HS_WR_I_MSK 0xfffffffe
++#define HS_WR_SFT 0
++#define HS_WR_HI 0
++#define HS_WR_SZ 1
++#define HS_FLAG_MSK 0x00000010
++#define HS_FLAG_I_MSK 0xffffffef
++#define HS_FLAG_SFT 4
++#define HS_FLAG_HI 4
++#define HS_FLAG_SZ 1
++#define HS_ID_MSK 0x00007f00
++#define HS_ID_I_MSK 0xffff80ff
++#define HS_ID_SFT 8
++#define HS_ID_HI 14
++#define HS_ID_SZ 7
++#define HS_CHANNEL_MSK 0x000f0000
++#define HS_CHANNEL_I_MSK 0xfff0ffff
++#define HS_CHANNEL_SFT 16
++#define HS_CHANNEL_HI 19
++#define HS_CHANNEL_SZ 4
++#define HS_PAGE_MSK 0x00f00000
++#define HS_PAGE_I_MSK 0xff0fffff
++#define HS_PAGE_SFT 20
++#define HS_PAGE_HI 23
++#define HS_PAGE_SZ 4
++#define HS_DATA_MSK 0xff000000
++#define HS_DATA_I_MSK 0x00ffffff
++#define HS_DATA_SFT 24
++#define HS_DATA_HI 31
++#define HS_DATA_SZ 8
++#define CPU_POR0_MSK 0x0000000f
++#define CPU_POR0_I_MSK 0xfffffff0
++#define CPU_POR0_SFT 0
++#define CPU_POR0_HI 3
++#define CPU_POR0_SZ 4
++#define CPU_POR1_MSK 0x000000f0
++#define CPU_POR1_I_MSK 0xffffff0f
++#define CPU_POR1_SFT 4
++#define CPU_POR1_HI 7
++#define CPU_POR1_SZ 4
++#define CPU_POR2_MSK 0x00000f00
++#define CPU_POR2_I_MSK 0xfffff0ff
++#define CPU_POR2_SFT 8
++#define CPU_POR2_HI 11
++#define CPU_POR2_SZ 4
++#define CPU_POR3_MSK 0x0000f000
++#define CPU_POR3_I_MSK 0xffff0fff
++#define CPU_POR3_SFT 12
++#define CPU_POR3_HI 15
++#define CPU_POR3_SZ 4
++#define CPU_POR4_MSK 0x000f0000
++#define CPU_POR4_I_MSK 0xfff0ffff
++#define CPU_POR4_SFT 16
++#define CPU_POR4_HI 19
++#define CPU_POR4_SZ 4
++#define CPU_POR5_MSK 0x00f00000
++#define CPU_POR5_I_MSK 0xff0fffff
++#define CPU_POR5_SFT 20
++#define CPU_POR5_HI 23
++#define CPU_POR5_SZ 4
++#define CPU_POR6_MSK 0x0f000000
++#define CPU_POR6_I_MSK 0xf0ffffff
++#define CPU_POR6_SFT 24
++#define CPU_POR6_HI 27
++#define CPU_POR6_SZ 4
++#define CPU_POR7_MSK 0xf0000000
++#define CPU_POR7_I_MSK 0x0fffffff
++#define CPU_POR7_SFT 28
++#define CPU_POR7_HI 31
++#define CPU_POR7_SZ 4
++#define CPU_POR8_MSK 0x0000000f
++#define CPU_POR8_I_MSK 0xfffffff0
++#define CPU_POR8_SFT 0
++#define CPU_POR8_HI 3
++#define CPU_POR8_SZ 4
++#define CPU_POR9_MSK 0x000000f0
++#define CPU_POR9_I_MSK 0xffffff0f
++#define CPU_POR9_SFT 4
++#define CPU_POR9_HI 7
++#define CPU_POR9_SZ 4
++#define CPU_PORA_MSK 0x00000f00
++#define CPU_PORA_I_MSK 0xfffff0ff
++#define CPU_PORA_SFT 8
++#define CPU_PORA_HI 11
++#define CPU_PORA_SZ 4
++#define CPU_PORB_MSK 0x0000f000
++#define CPU_PORB_I_MSK 0xffff0fff
++#define CPU_PORB_SFT 12
++#define CPU_PORB_HI 15
++#define CPU_PORB_SZ 4
++#define CPU_PORC_MSK 0x000f0000
++#define CPU_PORC_I_MSK 0xfff0ffff
++#define CPU_PORC_SFT 16
++#define CPU_PORC_HI 19
++#define CPU_PORC_SZ 4
++#define CPU_PORD_MSK 0x00f00000
++#define CPU_PORD_I_MSK 0xff0fffff
++#define CPU_PORD_SFT 20
++#define CPU_PORD_HI 23
++#define CPU_PORD_SZ 4
++#define CPU_PORE_MSK 0x0f000000
++#define CPU_PORE_I_MSK 0xf0ffffff
++#define CPU_PORE_SFT 24
++#define CPU_PORE_HI 27
++#define CPU_PORE_SZ 4
++#define CPU_PORF_MSK 0xf0000000
++#define CPU_PORF_I_MSK 0x0fffffff
++#define CPU_PORF_SFT 28
++#define CPU_PORF_HI 31
++#define CPU_PORF_SZ 4
++#define ACC_WR_LEN_MSK 0x0000003f
++#define ACC_WR_LEN_I_MSK 0xffffffc0
++#define ACC_WR_LEN_SFT 0
++#define ACC_WR_LEN_HI 5
++#define ACC_WR_LEN_SZ 6
++#define ACC_RD_LEN_MSK 0x00003f00
++#define ACC_RD_LEN_I_MSK 0xffffc0ff
++#define ACC_RD_LEN_SFT 8
++#define ACC_RD_LEN_HI 13
++#define ACC_RD_LEN_SZ 6
++#define REQ_NACK_CLR_MSK 0x00008000
++#define REQ_NACK_CLR_I_MSK 0xffff7fff
++#define REQ_NACK_CLR_SFT 15
++#define REQ_NACK_CLR_HI 15
++#define REQ_NACK_CLR_SZ 1
++#define NACK_FLAG_BUS_MSK 0xffff0000
++#define NACK_FLAG_BUS_I_MSK 0x0000ffff
++#define NACK_FLAG_BUS_SFT 16
++#define NACK_FLAG_BUS_HI 31
++#define NACK_FLAG_BUS_SZ 16
++#define DMN_R_PASS_MSK 0x0000ffff
++#define DMN_R_PASS_I_MSK 0xffff0000
++#define DMN_R_PASS_SFT 0
++#define DMN_R_PASS_HI 15
++#define DMN_R_PASS_SZ 16
++#define PARA_ALC_RLS_MSK 0x00010000
++#define PARA_ALC_RLS_I_MSK 0xfffeffff
++#define PARA_ALC_RLS_SFT 16
++#define PARA_ALC_RLS_HI 16
++#define PARA_ALC_RLS_SZ 1
++#define REQ_PORNS_CHGEN_MSK 0x01000000
++#define REQ_PORNS_CHGEN_I_MSK 0xfeffffff
++#define REQ_PORNS_CHGEN_SFT 24
++#define REQ_PORNS_CHGEN_HI 24
++#define REQ_PORNS_CHGEN_SZ 1
++#define ALC_ABT_ID_MSK 0x0000007f
++#define ALC_ABT_ID_I_MSK 0xffffff80
++#define ALC_ABT_ID_SFT 0
++#define ALC_ABT_ID_HI 6
++#define ALC_ABT_ID_SZ 7
++#define ALC_ABT_INT_MSK 0x00008000
++#define ALC_ABT_INT_I_MSK 0xffff7fff
++#define ALC_ABT_INT_SFT 15
++#define ALC_ABT_INT_HI 15
++#define ALC_ABT_INT_SZ 1
++#define RLS_ABT_ID_MSK 0x007f0000
++#define RLS_ABT_ID_I_MSK 0xff80ffff
++#define RLS_ABT_ID_SFT 16
++#define RLS_ABT_ID_HI 22
++#define RLS_ABT_ID_SZ 7
++#define RLS_ABT_INT_MSK 0x80000000
++#define RLS_ABT_INT_I_MSK 0x7fffffff
++#define RLS_ABT_INT_SFT 31
++#define RLS_ABT_INT_HI 31
++#define RLS_ABT_INT_SZ 1
++#define DEBUG_CTL_MSK 0x000000ff
++#define DEBUG_CTL_I_MSK 0xffffff00
++#define DEBUG_CTL_SFT 0
++#define DEBUG_CTL_HI 7
++#define DEBUG_CTL_SZ 8
++#define DEBUG_H16_MSK 0x00000100
++#define DEBUG_H16_I_MSK 0xfffffeff
++#define DEBUG_H16_SFT 8
++#define DEBUG_H16_HI 8
++#define DEBUG_H16_SZ 1
++#define DEBUG_OUT_MSK 0xffffffff
++#define DEBUG_OUT_I_MSK 0x00000000
++#define DEBUG_OUT_SFT 0
++#define DEBUG_OUT_HI 31
++#define DEBUG_OUT_SZ 32
++#define ALC_ERR_MSK 0x00000001
++#define ALC_ERR_I_MSK 0xfffffffe
++#define ALC_ERR_SFT 0
++#define ALC_ERR_HI 0
++#define ALC_ERR_SZ 1
++#define RLS_ERR_MSK 0x00000002
++#define RLS_ERR_I_MSK 0xfffffffd
++#define RLS_ERR_SFT 1
++#define RLS_ERR_HI 1
++#define RLS_ERR_SZ 1
++#define AL_STATE_MSK 0x00000700
++#define AL_STATE_I_MSK 0xfffff8ff
++#define AL_STATE_SFT 8
++#define AL_STATE_HI 10
++#define AL_STATE_SZ 3
++#define RL_STATE_MSK 0x00007000
++#define RL_STATE_I_MSK 0xffff8fff
++#define RL_STATE_SFT 12
++#define RL_STATE_HI 14
++#define RL_STATE_SZ 3
++#define ALC_ERR_ID_MSK 0x007f0000
++#define ALC_ERR_ID_I_MSK 0xff80ffff
++#define ALC_ERR_ID_SFT 16
++#define ALC_ERR_ID_HI 22
++#define ALC_ERR_ID_SZ 7
++#define RLS_ERR_ID_MSK 0x7f000000
++#define RLS_ERR_ID_I_MSK 0x80ffffff
++#define RLS_ERR_ID_SFT 24
++#define RLS_ERR_ID_HI 30
++#define RLS_ERR_ID_SZ 7
++#define DMN_NOHIT_FLAG_MSK 0x00000001
++#define DMN_NOHIT_FLAG_I_MSK 0xfffffffe
++#define DMN_NOHIT_FLAG_SFT 0
++#define DMN_NOHIT_FLAG_HI 0
++#define DMN_NOHIT_FLAG_SZ 1
++#define DMN_FLAG_MSK 0x00000002
++#define DMN_FLAG_I_MSK 0xfffffffd
++#define DMN_FLAG_SFT 1
++#define DMN_FLAG_HI 1
++#define DMN_FLAG_SZ 1
++#define DMN_WR_MSK 0x00000008
++#define DMN_WR_I_MSK 0xfffffff7
++#define DMN_WR_SFT 3
++#define DMN_WR_HI 3
++#define DMN_WR_SZ 1
++#define DMN_PORT_MSK 0x000000f0
++#define DMN_PORT_I_MSK 0xffffff0f
++#define DMN_PORT_SFT 4
++#define DMN_PORT_HI 7
++#define DMN_PORT_SZ 4
++#define DMN_NHIT_ID_MSK 0x00007f00
++#define DMN_NHIT_ID_I_MSK 0xffff80ff
++#define DMN_NHIT_ID_SFT 8
++#define DMN_NHIT_ID_HI 14
++#define DMN_NHIT_ID_SZ 7
++#define DMN_NHIT_ADDR_MSK 0xffff0000
++#define DMN_NHIT_ADDR_I_MSK 0x0000ffff
++#define DMN_NHIT_ADDR_SFT 16
++#define DMN_NHIT_ADDR_HI 31
++#define DMN_NHIT_ADDR_SZ 16
++#define TX_MOUNT_MSK 0x000000ff
++#define TX_MOUNT_I_MSK 0xffffff00
++#define TX_MOUNT_SFT 0
++#define TX_MOUNT_HI 7
++#define TX_MOUNT_SZ 8
++#define RX_MOUNT_MSK 0x0000ff00
++#define RX_MOUNT_I_MSK 0xffff00ff
++#define RX_MOUNT_SFT 8
++#define RX_MOUNT_HI 15
++#define RX_MOUNT_SZ 8
++#define AVA_TAG_MSK 0x01ff0000
++#define AVA_TAG_I_MSK 0xfe00ffff
++#define AVA_TAG_SFT 16
++#define AVA_TAG_HI 24
++#define AVA_TAG_SZ 9
++#define PKTBUF_FULL_MSK 0x80000000
++#define PKTBUF_FULL_I_MSK 0x7fffffff
++#define PKTBUF_FULL_SFT 31
++#define PKTBUF_FULL_HI 31
++#define PKTBUF_FULL_SZ 1
++#define DMN_NOHIT_MCU_MSK 0x00000001
++#define DMN_NOHIT_MCU_I_MSK 0xfffffffe
++#define DMN_NOHIT_MCU_SFT 0
++#define DMN_NOHIT_MCU_HI 0
++#define DMN_NOHIT_MCU_SZ 1
++#define DMN_MCU_FLAG_MSK 0x00000002
++#define DMN_MCU_FLAG_I_MSK 0xfffffffd
++#define DMN_MCU_FLAG_SFT 1
++#define DMN_MCU_FLAG_HI 1
++#define DMN_MCU_FLAG_SZ 1
++#define DMN_MCU_WR_MSK 0x00000008
++#define DMN_MCU_WR_I_MSK 0xfffffff7
++#define DMN_MCU_WR_SFT 3
++#define DMN_MCU_WR_HI 3
++#define DMN_MCU_WR_SZ 1
++#define DMN_MCU_PORT_MSK 0x000000f0
++#define DMN_MCU_PORT_I_MSK 0xffffff0f
++#define DMN_MCU_PORT_SFT 4
++#define DMN_MCU_PORT_HI 7
++#define DMN_MCU_PORT_SZ 4
++#define DMN_MCU_ID_MSK 0x00007f00
++#define DMN_MCU_ID_I_MSK 0xffff80ff
++#define DMN_MCU_ID_SFT 8
++#define DMN_MCU_ID_HI 14
++#define DMN_MCU_ID_SZ 7
++#define DMN_MCU_ADDR_MSK 0xffff0000
++#define DMN_MCU_ADDR_I_MSK 0x0000ffff
++#define DMN_MCU_ADDR_SFT 16
++#define DMN_MCU_ADDR_HI 31
++#define DMN_MCU_ADDR_SZ 16
++#define MB_IDTBL_31_0_MSK 0xffffffff
++#define MB_IDTBL_31_0_I_MSK 0x00000000
++#define MB_IDTBL_31_0_SFT 0
++#define MB_IDTBL_31_0_HI 31
++#define MB_IDTBL_31_0_SZ 32
++#define MB_IDTBL_63_32_MSK 0xffffffff
++#define MB_IDTBL_63_32_I_MSK 0x00000000
++#define MB_IDTBL_63_32_SFT 0
++#define MB_IDTBL_63_32_HI 31
++#define MB_IDTBL_63_32_SZ 32
++#define MB_IDTBL_95_64_MSK 0xffffffff
++#define MB_IDTBL_95_64_I_MSK 0x00000000
++#define MB_IDTBL_95_64_SFT 0
++#define MB_IDTBL_95_64_HI 31
++#define MB_IDTBL_95_64_SZ 32
++#define MB_IDTBL_127_96_MSK 0xffffffff
++#define MB_IDTBL_127_96_I_MSK 0x00000000
++#define MB_IDTBL_127_96_SFT 0
++#define MB_IDTBL_127_96_HI 31
++#define MB_IDTBL_127_96_SZ 32
++#define PKT_IDTBL_31_0_MSK 0xffffffff
++#define PKT_IDTBL_31_0_I_MSK 0x00000000
++#define PKT_IDTBL_31_0_SFT 0
++#define PKT_IDTBL_31_0_HI 31
++#define PKT_IDTBL_31_0_SZ 32
++#define PKT_IDTBL_63_32_MSK 0xffffffff
++#define PKT_IDTBL_63_32_I_MSK 0x00000000
++#define PKT_IDTBL_63_32_SFT 0
++#define PKT_IDTBL_63_32_HI 31
++#define PKT_IDTBL_63_32_SZ 32
++#define PKT_IDTBL_95_64_MSK 0xffffffff
++#define PKT_IDTBL_95_64_I_MSK 0x00000000
++#define PKT_IDTBL_95_64_SFT 0
++#define PKT_IDTBL_95_64_HI 31
++#define PKT_IDTBL_95_64_SZ 32
++#define PKT_IDTBL_127_96_MSK 0xffffffff
++#define PKT_IDTBL_127_96_I_MSK 0x00000000
++#define PKT_IDTBL_127_96_SFT 0
++#define PKT_IDTBL_127_96_HI 31
++#define PKT_IDTBL_127_96_SZ 32
++#define DMN_IDTBL_31_0_MSK 0xffffffff
++#define DMN_IDTBL_31_0_I_MSK 0x00000000
++#define DMN_IDTBL_31_0_SFT 0
++#define DMN_IDTBL_31_0_HI 31
++#define DMN_IDTBL_31_0_SZ 32
++#define DMN_IDTBL_63_32_MSK 0xffffffff
++#define DMN_IDTBL_63_32_I_MSK 0x00000000
++#define DMN_IDTBL_63_32_SFT 0
++#define DMN_IDTBL_63_32_HI 31
++#define DMN_IDTBL_63_32_SZ 32
++#define DMN_IDTBL_95_64_MSK 0xffffffff
++#define DMN_IDTBL_95_64_I_MSK 0x00000000
++#define DMN_IDTBL_95_64_SFT 0
++#define DMN_IDTBL_95_64_HI 31
++#define DMN_IDTBL_95_64_SZ 32
++#define DMN_IDTBL_127_96_MSK 0xffffffff
++#define DMN_IDTBL_127_96_I_MSK 0x00000000
++#define DMN_IDTBL_127_96_SFT 0
++#define DMN_IDTBL_127_96_HI 31
++#define DMN_IDTBL_127_96_SZ 32
++#define NEQ_MB_ID_31_0_MSK 0xffffffff
++#define NEQ_MB_ID_31_0_I_MSK 0x00000000
++#define NEQ_MB_ID_31_0_SFT 0
++#define NEQ_MB_ID_31_0_HI 31
++#define NEQ_MB_ID_31_0_SZ 32
++#define NEQ_MB_ID_63_32_MSK 0xffffffff
++#define NEQ_MB_ID_63_32_I_MSK 0x00000000
++#define NEQ_MB_ID_63_32_SFT 0
++#define NEQ_MB_ID_63_32_HI 31
++#define NEQ_MB_ID_63_32_SZ 32
++#define NEQ_MB_ID_95_64_MSK 0xffffffff
++#define NEQ_MB_ID_95_64_I_MSK 0x00000000
++#define NEQ_MB_ID_95_64_SFT 0
++#define NEQ_MB_ID_95_64_HI 31
++#define NEQ_MB_ID_95_64_SZ 32
++#define NEQ_MB_ID_127_96_MSK 0xffffffff
++#define NEQ_MB_ID_127_96_I_MSK 0x00000000
++#define NEQ_MB_ID_127_96_SFT 0
++#define NEQ_MB_ID_127_96_HI 31
++#define NEQ_MB_ID_127_96_SZ 32
++#define NEQ_PKT_ID_31_0_MSK 0xffffffff
++#define NEQ_PKT_ID_31_0_I_MSK 0x00000000
++#define NEQ_PKT_ID_31_0_SFT 0
++#define NEQ_PKT_ID_31_0_HI 31
++#define NEQ_PKT_ID_31_0_SZ 32
++#define NEQ_PKT_ID_63_32_MSK 0xffffffff
++#define NEQ_PKT_ID_63_32_I_MSK 0x00000000
++#define NEQ_PKT_ID_63_32_SFT 0
++#define NEQ_PKT_ID_63_32_HI 31
++#define NEQ_PKT_ID_63_32_SZ 32
++#define NEQ_PKT_ID_95_64_MSK 0xffffffff
++#define NEQ_PKT_ID_95_64_I_MSK 0x00000000
++#define NEQ_PKT_ID_95_64_SFT 0
++#define NEQ_PKT_ID_95_64_HI 31
++#define NEQ_PKT_ID_95_64_SZ 32
++#define NEQ_PKT_ID_127_96_MSK 0xffffffff
++#define NEQ_PKT_ID_127_96_I_MSK 0x00000000
++#define NEQ_PKT_ID_127_96_SFT 0
++#define NEQ_PKT_ID_127_96_HI 31
++#define NEQ_PKT_ID_127_96_SZ 32
++#define ALC_NOCHG_ID_MSK 0x0000007f
++#define ALC_NOCHG_ID_I_MSK 0xffffff80
++#define ALC_NOCHG_ID_SFT 0
++#define ALC_NOCHG_ID_HI 6
++#define ALC_NOCHG_ID_SZ 7
++#define ALC_NOCHG_INT_MSK 0x00008000
++#define ALC_NOCHG_INT_I_MSK 0xffff7fff
++#define ALC_NOCHG_INT_SFT 15
++#define ALC_NOCHG_INT_HI 15
++#define ALC_NOCHG_INT_SZ 1
++#define NEQ_PKT_FLAG_MSK 0x00010000
++#define NEQ_PKT_FLAG_I_MSK 0xfffeffff
++#define NEQ_PKT_FLAG_SFT 16
++#define NEQ_PKT_FLAG_HI 16
++#define NEQ_PKT_FLAG_SZ 1
++#define NEQ_MB_FLAG_MSK 0x01000000
++#define NEQ_MB_FLAG_I_MSK 0xfeffffff
++#define NEQ_MB_FLAG_SFT 24
++#define NEQ_MB_FLAG_HI 24
++#define NEQ_MB_FLAG_SZ 1
++#define SRAM_TAG_0_MSK 0x0000ffff
++#define SRAM_TAG_0_I_MSK 0xffff0000
++#define SRAM_TAG_0_SFT 0
++#define SRAM_TAG_0_HI 15
++#define SRAM_TAG_0_SZ 16
++#define SRAM_TAG_1_MSK 0xffff0000
++#define SRAM_TAG_1_I_MSK 0x0000ffff
++#define SRAM_TAG_1_SFT 16
++#define SRAM_TAG_1_HI 31
++#define SRAM_TAG_1_SZ 16
++#define SRAM_TAG_2_MSK 0x0000ffff
++#define SRAM_TAG_2_I_MSK 0xffff0000
++#define SRAM_TAG_2_SFT 0
++#define SRAM_TAG_2_HI 15
++#define SRAM_TAG_2_SZ 16
++#define SRAM_TAG_3_MSK 0xffff0000
++#define SRAM_TAG_3_I_MSK 0x0000ffff
++#define SRAM_TAG_3_SFT 16
++#define SRAM_TAG_3_HI 31
++#define SRAM_TAG_3_SZ 16
++#define SRAM_TAG_4_MSK 0x0000ffff
++#define SRAM_TAG_4_I_MSK 0xffff0000
++#define SRAM_TAG_4_SFT 0
++#define SRAM_TAG_4_HI 15
++#define SRAM_TAG_4_SZ 16
++#define SRAM_TAG_5_MSK 0xffff0000
++#define SRAM_TAG_5_I_MSK 0x0000ffff
++#define SRAM_TAG_5_SFT 16
++#define SRAM_TAG_5_HI 31
++#define SRAM_TAG_5_SZ 16
++#define SRAM_TAG_6_MSK 0x0000ffff
++#define SRAM_TAG_6_I_MSK 0xffff0000
++#define SRAM_TAG_6_SFT 0
++#define SRAM_TAG_6_HI 15
++#define SRAM_TAG_6_SZ 16
++#define SRAM_TAG_7_MSK 0xffff0000
++#define SRAM_TAG_7_I_MSK 0x0000ffff
++#define SRAM_TAG_7_SFT 16
++#define SRAM_TAG_7_HI 31
++#define SRAM_TAG_7_SZ 16
++#define SRAM_TAG_8_MSK 0x0000ffff
++#define SRAM_TAG_8_I_MSK 0xffff0000
++#define SRAM_TAG_8_SFT 0
++#define SRAM_TAG_8_HI 15
++#define SRAM_TAG_8_SZ 16
++#define SRAM_TAG_9_MSK 0xffff0000
++#define SRAM_TAG_9_I_MSK 0x0000ffff
++#define SRAM_TAG_9_SFT 16
++#define SRAM_TAG_9_HI 31
++#define SRAM_TAG_9_SZ 16
++#define SRAM_TAG_10_MSK 0x0000ffff
++#define SRAM_TAG_10_I_MSK 0xffff0000
++#define SRAM_TAG_10_SFT 0
++#define SRAM_TAG_10_HI 15
++#define SRAM_TAG_10_SZ 16
++#define SRAM_TAG_11_MSK 0xffff0000
++#define SRAM_TAG_11_I_MSK 0x0000ffff
++#define SRAM_TAG_11_SFT 16
++#define SRAM_TAG_11_HI 31
++#define SRAM_TAG_11_SZ 16
++#define SRAM_TAG_12_MSK 0x0000ffff
++#define SRAM_TAG_12_I_MSK 0xffff0000
++#define SRAM_TAG_12_SFT 0
++#define SRAM_TAG_12_HI 15
++#define SRAM_TAG_12_SZ 16
++#define SRAM_TAG_13_MSK 0xffff0000
++#define SRAM_TAG_13_I_MSK 0x0000ffff
++#define SRAM_TAG_13_SFT 16
++#define SRAM_TAG_13_HI 31
++#define SRAM_TAG_13_SZ 16
++#define SRAM_TAG_14_MSK 0x0000ffff
++#define SRAM_TAG_14_I_MSK 0xffff0000
++#define SRAM_TAG_14_SFT 0
++#define SRAM_TAG_14_HI 15
++#define SRAM_TAG_14_SZ 16
++#define SRAM_TAG_15_MSK 0xffff0000
++#define SRAM_TAG_15_I_MSK 0x0000ffff
++#define SRAM_TAG_15_SFT 16
++#define SRAM_TAG_15_HI 31
++#define SRAM_TAG_15_SZ 16
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_common.h b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
+new file mode 100644
+index 000000000000..e6d30f3714f7
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
+@@ -0,0 +1,452 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV6200_COMMON_H_
++#define _SSV6200_COMMON_H_
++#define FW_VERSION_REG ADR_TX_SEG
++#define M_ENG_CPU 0x00
++#define M_ENG_HWHCI 0x01
++#define M_ENG_EMPTY 0x02
++#define M_ENG_ENCRYPT 0x03
++#define M_ENG_MACRX 0x04
++#define M_ENG_MIC 0x05
++#define M_ENG_TX_EDCA0 0x06
++#define M_ENG_TX_EDCA1 0x07
++#define M_ENG_TX_EDCA2 0x08
++#define M_ENG_TX_EDCA3 0x09
++#define M_ENG_TX_MNG 0x0A
++#define M_ENG_ENCRYPT_SEC 0x0B
++#define M_ENG_MIC_SEC 0x0C
++#define M_ENG_RESERVED_1 0x0D
++#define M_ENG_RESERVED_2 0x0E
++#define M_ENG_TRASH_CAN 0x0F
++#define M_ENG_MAX (M_ENG_TRASH_CAN+1)
++#define M_CPU_HWENG 0x00
++#define M_CPU_TXL34CS 0x01
++#define M_CPU_RXL34CS 0x02
++#define M_CPU_DEFRAG 0x03
++#define M_CPU_EDCATX 0x04
++#define M_CPU_RXDATA 0x05
++#define M_CPU_RXMGMT 0x06
++#define M_CPU_RXCTRL 0x07
++#define M_CPU_FRAG 0x08
++#define M_CPU_TXTPUT 0x09
++#ifndef ID_TRAP_SW_TXTPUT
++#define ID_TRAP_SW_TXTPUT 50
++#endif
++#define M0_TXREQ 0
++#define M1_TXREQ 1
++#define M2_TXREQ 2
++#define M0_RXEVENT 3
++#define M2_RXEVENT 4
++#define HOST_CMD 5
++#define HOST_EVENT 6
++#define TEST_CMD 7
++#define SSV6XXX_RX_DESC_LEN \
++        (sizeof(struct ssv6200_rx_desc) + \
++         sizeof(struct ssv6200_rxphy_info))
++#define SSV6XXX_TX_DESC_LEN \
++        (sizeof(struct ssv6200_tx_desc) + 0)
++#define TXPB_OFFSET 80
++#define RXPB_OFFSET 80
++#define SSV6200_TX_PKT_RSVD_SETTING 0x3
++#define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16
++#define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD
++#define SSV62XX_TX_MAX_RATES 3
++
++enum ssv6xxx_sr_bhvr {
++	SUSPEND_RESUME_0,
++	SUSPEND_RESUME_1,
++	SUSPEND_RESUME_MAX
++};
++
++enum ssv6xxx_reboot_bhvr {
++	SSV_SYS_REBOOT = 1,
++	SSV_SYS_HALF,
++	SSV_SYS_POWER_OFF
++};
++
++struct fw_rc_retry_params {
++	u32 count:4;
++	u32 drate:6;
++	u32 crate:6;
++	u32 rts_cts_nav:16;
++	u32 frame_consume_time:10;
++	u32 dl_length:12;
++	u32 RSVD:10;
++} __attribute__((packed));
++struct ssv6200_tx_desc {
++	u32 len:16;
++	u32 c_type:3;
++	u32 f80211:1;
++	u32 qos:1;
++	u32 ht:1;
++	u32 use_4addr:1;
++	u32 RSVD_0:3;
++	u32 bc_que:1;
++	u32 security:1;
++	u32 more_data:1;
++	u32 stype_b5b4:2;
++	u32 extra_info:1;
++	u32 fCmd;
++	u32 hdr_offset:8;
++	u32 frag:1;
++	u32 unicast:1;
++	u32 hdr_len:6;
++	u32 tx_report:1;
++	u32 tx_burst:1;
++	u32 ack_policy:2;
++	u32 aggregation:1;
++	u32 RSVD_1:3;
++	u32 do_rts_cts:2;
++	u32 reason:6;
++	u32 payload_offset:8;
++	u32 RSVD_4:7;
++	u32 RSVD_2:1;
++	u32 fCmdIdx:3;
++	u32 wsid:4;
++	u32 txq_idx:3;
++	u32 TxF_ID:6;
++	u32 rts_cts_nav:16;
++	u32 frame_consume_time:10;
++	u32 crate_idx:6;
++	u32 drate_idx:6;
++	u32 dl_length:12;
++	u32 RSVD_3:14;
++	u32 RESERVED[8];
++	struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];
++};
++struct ssv6200_rx_desc {
++	u32 len:16;
++	u32 c_type:3;
++	u32 f80211:1;
++	u32 qos:1;
++	u32 ht:1;
++	u32 use_4addr:1;
++	u32 l3cs_err:1;
++	u32 l4cs_err:1;
++	u32 align2:1;
++	u32 RSVD_0:2;
++	u32 psm:1;
++	u32 stype_b5b4:2;
++	u32 extra_info:1;
++	u32 edca0_used:4;
++	u32 edca1_used:5;
++	u32 edca2_used:5;
++	u32 edca3_used:5;
++	u32 mng_used:4;
++	u32 tx_page_used:9;
++	u32 hdr_offset:8;
++	u32 frag:1;
++	u32 unicast:1;
++	u32 hdr_len:6;
++	u32 RxResult:8;
++	u32 wildcard_bssid:1;
++	u32 RSVD_1:1;
++	u32 reason:6;
++	u32 payload_offset:8;
++	u32 tx_id_used:8;
++	u32 fCmdIdx:3;
++	u32 wsid:4;
++	u32 RSVD_3:3;
++	u32 rate_idx:6;
++};
++struct ssv6200_rxphy_info {
++	u32 len:16;
++	u32 rsvd0:16;
++	u32 mode:3;
++	u32 ch_bw:3;
++	u32 preamble:1;
++	u32 ht_short_gi:1;
++	u32 rate:7;
++	u32 rsvd1:1;
++	u32 smoothing:1;
++	u32 no_sounding:1;
++	u32 aggregate:1;
++	u32 stbc:2;
++	u32 fec:1;
++	u32 n_ess:2;
++	u32 rsvd2:8;
++	u32 l_length:12;
++	u32 l_rate:3;
++	u32 rsvd3:17;
++	u32 rsvd4;
++	u32 rpci:8;
++	u32 snr:8;
++	u32 service:16;
++};
++struct ssv6200_rxphy_info_padding {
++	u32 rpci:8;
++	u32 snr:8;
++	u32 RSVD:16;
++};
++struct ssv6200_txphy_info {
++	u32 rsvd[7];
++};
++#ifdef CONFIG_P2P_NOA
++struct ssv6xxx_p2p_noa_param {
++	u32 duration;
++	u32 interval;
++	u32 start_time;
++	u32 enable:8;
++	u32 count:8;
++	u8 addr[6];
++	u8 vif_id;
++} __attribute__((packed));
++#endif
++typedef struct cfg_host_cmd {
++	u32 len:16;
++	u32 c_type:3;
++	u32 RSVD0:5;
++	u32 h_cmd:8;
++	u32 cmd_seq_no;
++	union {
++		u32 dummy;
++		u8 dat8[0];
++		u16 dat16[0];
++		u32 dat32[0];
++	};
++} HDR_HostCmd;
++#define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U)
++struct sdio_rxtput_cfg {
++	u32 size_per_frame;
++	u32 total_frames;
++};
++typedef enum {
++	SSV6XXX_HOST_CMD_START = 0,
++	SSV6XXX_HOST_CMD_LOG,
++	SSV6XXX_HOST_CMD_PS,
++	SSV6XXX_HOST_CMD_INIT_CALI,
++	SSV6XXX_HOST_CMD_RX_TPUT,
++	SSV6XXX_HOST_CMD_TX_TPUT,
++	SSV6XXX_HOST_CMD_WATCHDOG_START,
++	SSV6XXX_HOST_CMD_WATCHDOG_STOP,
++	SSV6XXX_HOST_CMD_WSID_OP,
++#ifdef CONFIG_P2P_NOA
++	SSV6XXX_HOST_CMD_SET_NOA,
++#endif
++	SSV6XXX_HOST_SOC_CMD_MAXID,
++} ssv6xxx_host_cmd_id;
++#define SSV_NUM_HW_STA 2
++typedef struct cfg_host_event {
++	u32 len:16;
++	u32 c_type:3;
++	u32 RSVD0:5;
++	u32 h_event:8;
++	u32 evt_seq_no;
++	u8 dat[0];
++} HDR_HostEvent;
++typedef enum {
++#ifdef USE_CMD_RESP
++	SOC_EVT_CMD_RESP,
++	SOC_EVT_SCAN_RESULT,
++	SOC_EVT_DEAUTH,
++#else
++	SOC_EVT_GET_REG_RESP,
++#endif
++	SOC_EVT_NO_BA,
++	SOC_EVT_RC_MPDU_REPORT,
++	SOC_EVT_RC_AMPDU_REPORT,
++	SOC_EVT_LOG,
++#ifdef CONFIG_P2P_NOA
++	SOC_EVT_NOA,
++#endif
++	SOC_EVT_USER_END,
++	SOC_EVT_SDIO_TEST_COMMAND,
++	SOC_EVT_RESET_HOST,
++	SOC_EVT_SDIO_TXTPUT_RESULT,
++	SOC_EVT_WATCHDOG_TRIGGER,
++	SOC_EVT_TXLOOPBK_RESULT,
++	SOC_EVT_MAXID,
++} ssv6xxx_soc_event;
++#ifdef CONFIG_P2P_NOA
++typedef enum {
++	SSV6XXX_NOA_START = 0,
++	SSV6XXX_NOA_STOP,
++} ssv6xxx_host_noa_event;
++struct ssv62xx_noa_evt {
++	u8 evt_id;
++	u8 vif;
++} __attribute__((packed));
++#endif
++typedef enum {
++	SSV6XXX_RC_COUNTER_CLEAR = 1,
++	SSV6XXX_RC_REPORT,
++} ssv6xxx_host_rate_control_event;
++#define MAX_AGGR_NUM (24)
++struct ssv62xx_tx_rate {
++	s8 data_rate;
++	u8 count;
++} __attribute__((packed));
++struct ampdu_ba_notify_data {
++	u8 wsid;
++	struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];
++	u16 seq_no[MAX_AGGR_NUM];
++} __attribute__((packed));
++struct firmware_rate_control_report_data {
++	u8 wsid;
++	struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];
++	u16 ampdu_len;
++	u16 ampdu_ack_len;
++	int ack_signal;
++} __attribute__((packed));
++#define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES)
++#define SSV_RC_RATE_MAX 39
++enum SSV6XXX_WSID_OPS {
++	SSV6XXX_WSID_OPS_ADD,
++	SSV6XXX_WSID_OPS_DEL,
++	SSV6XXX_WSID_OPS_RESETALL,
++	SSV6XXX_WSID_OPS_ENABLE_CAPS,
++	SSV6XXX_WSID_OPS_DISABLE_CAPS,
++	SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE,
++	SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE,
++	SSV6XXX_WSID_OPS_MAX
++};
++enum SSV6XXX_WSID_SEC {
++	SSV6XXX_WSID_SEC_NONE = 0,
++	SSV6XXX_WSID_SEC_PAIRWISE = 1 << 0,
++	SSV6XXX_WSID_SEC_GROUP = 1 << 1,
++};
++enum SSV6XXX_WSID_SEC_TYPE {
++	SSV6XXX_WSID_SEC_SW,
++	SSV6XXX_WSID_SEC_HW,
++	SSV6XXX_WSID_SEC_TYPE_MAX
++};
++enum SSV6XXX_RETURN_STATE {
++	SSV6XXX_STATE_OK,
++	SSV6XXX_STATE_NG,
++	SSV6XXX_STATE_MAX
++};
++struct ssv6xxx_wsid_params {
++	u8 cmd;
++	u8 wsid_idx;
++	u8 target_wsid[6];
++	u8 hw_security;
++};
++struct ssv6xxx_iqk_cfg {
++	u32 cfg_xtal:8;
++	u32 cfg_pa:8;
++	u32 cfg_pabias_ctrl:8;
++	u32 cfg_pacascode_ctrl:8;
++	u32 cfg_tssi_trgt:8;
++	u32 cfg_tssi_div:8;
++	u32 cfg_def_tx_scale_11b:8;
++	u32 cfg_def_tx_scale_11b_p0d5:8;
++	u32 cfg_def_tx_scale_11g:8;
++	u32 cfg_def_tx_scale_11g_p0d5:8;
++	u32 cmd_sel;
++	union {
++		u32 fx_sel;
++		u32 argv;
++	};
++	u32 phy_tbl_size;
++	u32 rf_tbl_size;
++};
++#define PHY_SETTING_SIZE sizeof(phy_setting)
++struct ssv6xxx_ch_cfg {
++	u32 reg_addr;
++	u32 ch1_12_value;
++	u32 ch13_14_value;
++};
++#define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg))
++#define RF_SETTING_SIZE (sizeof(asic_rf_setting))
++#define MAX_PHY_SETTING_TABLE_SIZE 1920
++#define MAX_RF_SETTING_TABLE_SIZE 512
++typedef enum {
++	SSV6XXX_VOLT_DCDC_CONVERT = 0,
++	SSV6XXX_VOLT_LDO_CONVERT,
++} ssv6xxx_cfg_volt;
++typedef enum {
++	SSV6XXX_VOLT_33V = 0,
++	SSV6XXX_VOLT_42V,
++} ssv6xxx_cfg_volt_value;
++typedef enum {
++	SSV6XXX_IQK_CFG_XTAL_26M = 0,
++	SSV6XXX_IQK_CFG_XTAL_40M,
++	SSV6XXX_IQK_CFG_XTAL_24M,
++	SSV6XXX_IQK_CFG_XTAL_MAX,
++} ssv6xxx_iqk_cfg_xtal;
++typedef enum {
++	SSV6XXX_IQK_CFG_PA_DEF = 0,
++	SSV6XXX_IQK_CFG_PA_LI_MPB,
++	SSV6XXX_IQK_CFG_PA_LI_EVB,
++	SSV6XXX_IQK_CFG_PA_HP,
++} ssv6xxx_iqk_cfg_pa;
++typedef enum {
++	SSV6XXX_IQK_CMD_INIT_CALI = 0,
++	SSV6XXX_IQK_CMD_RTBL_LOAD,
++	SSV6XXX_IQK_CMD_RTBL_LOAD_DEF,
++	SSV6XXX_IQK_CMD_RTBL_RESET,
++	SSV6XXX_IQK_CMD_RTBL_SET,
++	SSV6XXX_IQK_CMD_RTBL_EXPORT,
++	SSV6XXX_IQK_CMD_TK_EVM,
++	SSV6XXX_IQK_CMD_TK_TONE,
++	SSV6XXX_IQK_CMD_TK_CHCH,
++} ssv6xxx_iqk_cmd_sel;
++#define SSV6XXX_IQK_TEMPERATURE 0x00000004
++#define SSV6XXX_IQK_RXDC 0x00000008
++#define SSV6XXX_IQK_RXRC 0x00000010
++#define SSV6XXX_IQK_TXDC 0x00000020
++#define SSV6XXX_IQK_TXIQ 0x00000040
++#define SSV6XXX_IQK_RXIQ 0x00000080
++#define SSV6XXX_IQK_TSSI 0x00000100
++#define SSV6XXX_IQK_PAPD 0x00000200
++typedef struct ssv_cabrio_reg_st {
++	u32 address;
++	u32 data;
++} ssv_cabrio_reg;
++typedef enum __PBuf_Type_E {
++	NOTYPE_BUF = 0,
++	TX_BUF = 1,
++	RX_BUF = 2
++} PBuf_Type_E;
++struct SKB_info_st {
++	struct ieee80211_sta *sta;
++	u16 mpdu_retry_counter;
++	unsigned long aggr_timestamp;
++	u16 ampdu_tx_status;
++	u16 ampdu_tx_final_retry_count;
++	u16 lowest_rate;
++	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++	ktime_t timestamp;
++#endif
++};
++typedef struct SKB_info_st SKB_info;
++typedef struct SKB_info_st *p_SKB_info;
++#define SSV_SKB_info_size (sizeof(struct SKB_info_st))
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++#define SKB_DURATION_TIMEOUT_MS 100
++enum ssv_debug_skb_timestamp {
++	SKB_DURATION_STAGE_TX_ENQ,
++	SKB_DURATION_STAGE_TO_SDIO,
++	SKB_DURATION_STAGE_IN_HWQ,
++	SKB_DURATION_STAGE_END
++};
++#endif
++#define SSV6051Q_P1 0x00000000
++#define SSV6051Q_P2 0x70000000
++#define SSV6051Z 0x71000000
++#define SSV6051Q 0x73000000
++#define SSV6051P 0x75000000
++struct ssv6xxx_tx_loopback {
++	u32 reg;
++	u32 val;
++	u32 restore_val;
++	u8 restore;
++	u8 delay_ms;
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
+new file mode 100644
+index 000000000000..0327393de3f5
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
+@@ -0,0 +1,317 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++static ssv_cabrio_reg phy_setting[] = {
++	{0xce0071bc, 0x565B565B},
++	{0xce000008, 0x0000006a},
++	{0xce00000c, 0x00000064},
++	{0xce000010, 0x00007FFF},
++	{0xce000014, 0x00000003},
++	{0xce000018, 0x0055003C},
++	{0xce00001c, 0x00000064},
++	{0xce000020, 0x20000000},
++	{0xce00002c, 0x00000000},
++	{0xce000030, 0x80046072},
++	{0xce000034, 0x1f300f6f},
++	{0xce000038, 0x660F36D0},
++	{0xce00003c, 0x106C0004},
++	{0xce000040, 0x01601400},
++	{0xce000044, 0x00600008},
++	{0xce000048, 0xff000160},
++	{0xce00004c, 0x00000840},
++	{0xce000060, 0x01000405},
++	{0xce000064, 0x06090813},
++	{0xce000068, 0x12070000},
++	{0xce00006c, 0x01000405},
++	{0xce000070, 0x06090813},
++	{0xce000074, 0x12010000},
++	{0xce000078, 0x00000000},
++	{0xce00007c, 0x10110003},
++	{0xce000080, 0x0110000F},
++	{0xce000084, 0x00000000},
++	{0xce000088, 0x00000000},
++	{0xce000094, 0x01012425},
++	{0xce000098, 0x01010101},
++	{0xce00009c, 0x00000011},
++	{0xce0000a0, 0x1fff0000},
++	{0xce0000a4, 0x1fff0000},
++	{0xce0000a8, 0x1fff0000},
++	{0xce0000ac, 0x1fff0000},
++	{0xce0000b8, 0x0000fe3e},
++	{0xce0000fc, 0xffffffff},
++	{0xce000108, 0x0ead04f5},
++	{0xce00010c, 0x0fd60080},
++	{0xce000110, 0x00000009},
++	{0xce0010a4, 0x0000002c},
++	{0xce0010b4, 0x00003001},
++	{0xce0010d4, 0x00000001},
++	{0xce002000, 0x00000044},
++	{0xce002004, 0x00040000},
++	{0xce002008, 0x20300050},
++	{0xce00200c, 0x00003467},
++	{0xce002010, 0x00430000},
++	{0xce002014, 0x20304015},
++	{0xce002018, 0x00390005},
++	{0xce00201c, 0x05555555},
++	{0xce002020, 0x00570057},
++	{0xce002024, 0x00570057},
++	{0xce002028, 0x00236700},
++	{0xce00202c, 0x000d1746},
++	{0xce002030, 0x05061787},
++	{0xce002034, 0x07800000},
++	{0xce00209c, 0x00900008},
++	{0xce0020a0, 0x00000000},
++	{0xce0023f8, 0x00000000},
++	{0xce0023fc, 0x00000001},
++	{0xce0030a4, 0x00001901},
++	{0xce0030b8, 0x5d08908e},
++	{0xce004000, 0x00000044},
++	{0xce004004, 0x00750075},
++	{0xce004008, 0x00000075},
++	{0xce00400c, 0x10000075},
++	{0xce004010, 0x3F384905},
++	{0xce004014, 0x40182000},
++	{0xce004018, 0x20600000},
++	{0xce00401c, 0x0C010120},
++	{0xce004020, 0x50505050},
++	{0xce004024, 0x50000000},
++	{0xce004028, 0x50505050},
++	{0xce00402c, 0x506070A0},
++	{0xce004030, 0xF0000000},
++	{0xce004034, 0x00002424},
++	{0xce004038, 0x00001420},
++	{0xce00409c, 0x0000300A},
++	{0xce0040c0, 0x20000280},
++	{0xce0040c4, 0x30023002},
++	{0xce0040c8, 0x0000003a},
++	{0xce004130, 0x40000000},
++	{0xce004164, 0x009C007E},
++	{0xce004180, 0x00044400},
++	{0xce004188, 0x82000000},
++	{0xce004190, 0x00000000},
++	{0xce004194, 0xffffffff},
++	{0xce004380, 0x00700010},
++	{0xce004384, 0x00007575},
++	{0xce004388, 0x0001fe3e},
++	{0xce00438c, 0x0000fe3e},
++	{0xce0043f8, 0x00000001},
++	{0xce007000, 0x00000000},
++	{0xce007004, 0x00008000},
++	{0xce007008, 0x00000000},
++	{0xce00700c, 0x00000000},
++	{0xce007010, 0x00000000},
++	{0xce007014, 0x00000000},
++	{0xce007018, 0x00000000},
++	{0xce00701c, 0x00000000},
++	{0xce007020, 0x00000000},
++	{0xce007024, 0x00000000},
++	{0xce007028, 0x00000000},
++	{0xce00702c, 0x00000000},
++	{0xce007030, 0x00000000},
++	{0xce007034, 0x00000000},
++	{0xce007038, 0x00000000},
++	{0xce00703c, 0x00000000},
++	{0xce007040, 0x02000200},
++	{0xce007048, 0x00000000},
++	{0xce00704c, 0x00000000},
++	{0xce007050, 0x00000000},
++	{0xce007054, 0x00000000},
++	{0xce007058, 0x000028ff},
++	{0xce00705c, 0x00000000},
++	{0xce007060, 0x00000000},
++	{0xce007064, 0x00000000},
++	{0xce007068, 0x00000000},
++	{0xce00706c, 0x00000202},
++	{0xce007070, 0x80ffc200},
++	{0xce007074, 0x00000000},
++	{0xce007078, 0x00000000},
++	{0xce00707c, 0x00000000},
++	{0xce007080, 0x00000000},
++	{0xce007084, 0x00000000},
++	{0xce007088, 0x00000000},
++	{0xce00708c, 0x00000000},
++	{0xce007090, 0x00000000},
++	{0xce007094, 0x00000000},
++	{0xce007098, 0x00000000},
++	{0xce00709c, 0x00000000},
++	{0xce0070a0, 0x00000000},
++	{0xce0070a4, 0x00000000},
++	{0xce0070a8, 0x00000000},
++	{0xce0070ac, 0x00000000},
++	{0xce0070b0, 0x00000000},
++	{0xce0070b4, 0x00000000},
++	{0xce0070b8, 0x00000000},
++	{0xce0070bc, 0x00000000},
++	{0xce0070c0, 0x00000000},
++	{0xce0070c4, 0x00000000},
++	{0xce0070c8, 0x00000000},
++	{0xce0070cc, 0x00000000},
++	{0xce0070d0, 0x00000000},
++	{0xce0070d4, 0x00000000},
++	{0xce0070d8, 0x00000000},
++	{0xce0070dc, 0x00000000},
++	{0xce0070e0, 0x00000000},
++	{0xce0070e4, 0x00000000},
++	{0xce0070e8, 0x00000000},
++	{0xce0070ec, 0x00000000},
++	{0xce0070f0, 0x00000000},
++	{0xce0070f4, 0x00000000},
++	{0xce0070f8, 0x00000000},
++	{0xce0070fc, 0x00000000},
++	{0xce007100, 0x00000000},
++	{0xce007104, 0x00000000},
++	{0xce007108, 0x00000000},
++	{0xce00710c, 0x00000000},
++	{0xce007110, 0x00000000},
++	{0xce007114, 0x00000000},
++	{0xce007118, 0x00000000},
++	{0xce00711c, 0x00000000},
++	{0xce007120, 0x02000200},
++	{0xce007124, 0x02000200},
++	{0xce007128, 0x02000200},
++	{0xce00712c, 0x02000200},
++	{0xce007130, 0x02000200},
++	{0xce007134, 0x02000200},
++	{0xce007138, 0x02000200},
++	{0xce00713c, 0x02000200},
++	{0xce007140, 0x02000200},
++	{0xce007144, 0x02000200},
++	{0xce007148, 0x02000200},
++	{0xce00714c, 0x02000200},
++	{0xce007150, 0x02000200},
++	{0xce007154, 0x02000200},
++	{0xce007158, 0x00000000},
++	{0xce00715c, 0x00000000},
++	{0xce007160, 0x00000000},
++	{0xce007164, 0x00000000},
++	{0xce007168, 0x00000000},
++	{0xce00716c, 0x00000000},
++	{0xce007170, 0x00000000},
++	{0xce007174, 0x00000000},
++	{0xce007178, 0x00000000},
++	{0xce00717c, 0x00000000},
++	{0xce007180, 0x00000000},
++	{0xce007184, 0x00000000},
++	{0xce007188, 0x00000000},
++	{0xce00718c, 0x00000000},
++	{0xce007190, 0x00000000},
++	{0xce007194, 0x00000000},
++	{0xce007198, 0x00000000},
++	{0xce00719c, 0x00000000},
++	{0xce0071a0, 0x00000000},
++	{0xce0071a4, 0x00000000},
++	{0xce0071a8, 0x00000000},
++	{0xce0071ac, 0x00000000},
++	{0xce0071b0, 0x00000000},
++	{0xce0071b4, 0x00000100},
++	{0xce0071b8, 0x00000000},
++	{0xce0071c0, 0x00000000},
++	{0xce0071c4, 0x00000000},
++	{0xce0071c8, 0x00000000},
++	{0xce0071cc, 0x00000000},
++	{0xce0071d0, 0x00000000},
++	{0xce0071d4, 0x00000000},
++	{0xce0071d8, 0x00000000},
++	{0xce0071dc, 0x00000000},
++	{0xce0071e0, 0x00000000},
++	{0xce0071e4, 0x00000000},
++	{0xce0071e8, 0x00000000},
++	{0xce0071ec, 0x00000000},
++	{0xce0071f0, 0x00000000},
++	{0xce0071f4, 0x00000000},
++	{0xce0071f8, 0x00000000},
++	{0xce0071fc, 0x00000000},
++	{0xce0043fc, 0x000104E5},
++	{0xce007044, 0x00028080},
++	{0xce000000, 0x80000016},
++};
++
++static const u32 wifi_tx_gain[] = {
++	0x79807980,
++	0x72797279,
++	0x6C726C72,
++	0x666C666C,
++	0x60666066,
++	0x5B605B60,
++	0x565B565B,
++	0x51565156,
++	0x4C514C51,
++	0x484C484C,
++	0x44484448,
++	0x40444044,
++	0x3C403C40,
++	0x3A3D3A3D,
++	0x36393639,
++};
++
++static ssv_cabrio_reg asic_rf_setting[] = {
++	{0xCE010038, 0x0003E07C},
++	{0xCE010060, 0x00406000},
++	{0xCE01009C, 0x00000024},
++	{0xCE0100A0, 0x00EC4CC5},
++	{0xCE010000, 0x40002000},
++	{0xCE010004, 0x00020FC0},
++	{0xCE010008, 0x000DF69B},
++	{0xCE010014, 0x3D3E84FE},
++	{0xCE010018, 0x01457D79},
++	{0xCE01001C, 0x000103A7},
++	{0xCE010020, 0x000103A6},
++	{0xCE01002C, 0x00032CA8},
++	{0xCE010048, 0xFCCCCF27},
++	{0xCE010050, 0x00444000},
++	{0xCE01000C, 0x151558C5},
++	{0xCE010010, 0x01011A88},
++	{0xCE010024, 0x00012001},
++	{0xCE010028, 0x00036000},
++	{0xCE010030, 0x20EA0224},
++	{0xCE010034, 0x44000755},
++	{0xCE01003C, 0x55D89D8A},
++	{0xCE010040, 0x005508BB},
++	{0xCE010044, 0x07C08BFF},
++	{0xCE01004C, 0x07700830},
++	{0xCE010054, 0x00007FF4},
++	{0xCE010058, 0x0000000E},
++	{0xCE01005C, 0x00088018},
++	{0xCE010064, 0x08820820},
++	{0xCE010068, 0x00820820},
++	{0xCE01006C, 0x00820820},
++	{0xCE010070, 0x00820820},
++	{0xCE010074, 0x00820820},
++	{0xCE010078, 0x00820820},
++	{0xCE01007C, 0x00820820},
++	{0xCE010080, 0x00820820},
++	{0xCE010084, 0x00004080},
++	{0xCE010088, 0x200800FE},
++	{0xCE01008C, 0xAAAAAAAA},
++	{0xCE010090, 0xAAAAAAAA},
++	{0xCE010094, 0x0000A487},
++	{0xCE010098, 0x0000070E},
++	{0xCE0100A4, 0x00000F43},
++	{0xCE0100A8, 0x00098900},
++	{0xCE0100AC, 0x00000000},
++	{0xC00003AC, 0x00000000},
++	{0xC00003B0, 0x00000000},
++	{0xC00003B4, 0x00000000},
++	{0xC00003BC, 0x00000000},
++	{0xC0001D00, 0x5E000040},
++	{0xC0001D04, 0x015D015D},
++	{0xC0001D08, 0x00000001},
++	{0xC0001D0C, 0x55550000},
++	{0xC0001D20, 0x7FFF0000},
++	{0xC0001D24, 0x00000003},
++	{0xC0001D28, 0x00000000},
++	{0xC0001D2C, 0x00000000},
++};
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
+new file mode 100644
+index 000000000000..d4a99b25d61f
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
+@@ -0,0 +1,9694 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define SYS_REG_BASE 0xc0000000
++#define WBOOT_REG_BASE 0xc0000100
++#define TU0_US_REG_BASE 0xc0000200
++#define TU1_US_REG_BASE 0xc0000210
++#define TU2_US_REG_BASE 0xc0000220
++#define TU3_US_REG_BASE 0xc0000230
++#define TM0_MS_REG_BASE 0xc0000240
++#define TM1_MS_REG_BASE 0xc0000250
++#define TM2_MS_REG_BASE 0xc0000260
++#define TM3_MS_REG_BASE 0xc0000270
++#define MCU_WDT_REG_BASE 0xc0000280
++#define SYS_WDT_REG_BASE 0xc0000284
++#define GPIO_REG_BASE 0xc0000300
++#define SD_REG_BASE 0xc0000800
++#define SPI_REG_BASE 0xc0000a00
++#define CSR_I2C_MST_BASE 0xc0000b00
++#define UART_REG_BASE 0xc0000c00
++#define DAT_UART_REG_BASE 0xc0000d00
++#define INT_REG_BASE 0xc0000e00
++#define DBG_SPI_REG_BASE 0xc0000f00
++#define FLASH_SPI_REG_BASE 0xc0001000
++#define DMA_REG_BASE 0xc0001c00
++#define CSR_PMU_BASE 0xc0001d00
++#define CSR_RTC_BASE 0xc0001d20
++#define RTC_RAM_BASE 0xc0001d80
++#define D2_DMA_REG_BASE 0xc0001e00
++#define HCI_REG_BASE 0xc1000000
++#define CO_REG_BASE 0xc2000000
++#define EFS_REG_BASE 0xc2000100
++#define SMS4_REG_BASE 0xc3000000
++#define MRX_REG_BASE 0xc6000000
++#define AMPDU_REG_BASE 0xc6001000
++#define MT_REG_CSR_BASE 0xc6002000
++#define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100
++#define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200
++#define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300
++#define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400
++#define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500
++#define HIF_INFO_BASE 0xca000000
++#define PHY_RATE_INFO_BASE 0xca000200
++#define MAC_GLB_SET_BASE 0xca000300
++#define BTCX_REG_BASE 0xca000400
++#define MIB_REG_BASE 0xca000800
++#define CBR_A_REG_BASE 0xcb000000
++#define MB_REG_BASE 0xcd000000
++#define ID_MNG_REG_BASE 0xcd010000
++#define CSR_PHY_BASE 0xce000000
++#define CSR_RF_BASE 0xce010000
++#define MMU_REG_BASE 0xcf000000
++#define SYS_REG_BANK_SIZE 0x000000b4
++#define WBOOT_REG_BANK_SIZE 0x0000000c
++#define TU0_US_REG_BANK_SIZE 0x00000010
++#define TU1_US_REG_BANK_SIZE 0x00000010
++#define TU2_US_REG_BANK_SIZE 0x00000010
++#define TU3_US_REG_BANK_SIZE 0x00000010
++#define TM0_MS_REG_BANK_SIZE 0x00000010
++#define TM1_MS_REG_BANK_SIZE 0x00000010
++#define TM2_MS_REG_BANK_SIZE 0x00000010
++#define TM3_MS_REG_BANK_SIZE 0x00000010
++#define MCU_WDT_REG_BANK_SIZE 0x00000004
++#define SYS_WDT_REG_BANK_SIZE 0x00000004
++#define GPIO_REG_BANK_SIZE 0x000000d4
++#define SD_REG_BANK_SIZE 0x00000180
++#define SPI_REG_BANK_SIZE 0x00000040
++#define CSR_I2C_MST_BANK_SIZE 0x00000018
++#define UART_REG_BANK_SIZE 0x00000028
++#define DAT_UART_REG_BANK_SIZE 0x00000028
++#define INT_REG_BANK_SIZE 0x0000004c
++#define DBG_SPI_REG_BANK_SIZE 0x00000040
++#define FLASH_SPI_REG_BANK_SIZE 0x0000002c
++#define DMA_REG_BANK_SIZE 0x00000014
++#define CSR_PMU_BANK_SIZE 0x00000100
++#define CSR_RTC_BANK_SIZE 0x000000e0
++#define RTC_RAM_BANK_SIZE 0x00000080
++#define D2_DMA_REG_BANK_SIZE 0x00000014
++#define HCI_REG_BANK_SIZE 0x000000cc
++#define CO_REG_BANK_SIZE 0x000000ac
++#define EFS_REG_BANK_SIZE 0x0000006c
++#define SMS4_REG_BANK_SIZE 0x00000070
++#define MRX_REG_BANK_SIZE 0x00000198
++#define AMPDU_REG_BANK_SIZE 0x00000014
++#define MT_REG_CSR_BANK_SIZE 0x00000100
++#define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define HIF_INFO_BANK_SIZE 0x0000009c
++#define PHY_RATE_INFO_BANK_SIZE 0x000000b8
++#define MAC_GLB_SET_BANK_SIZE 0x0000003c
++#define BTCX_REG_BANK_SIZE 0x0000000c
++#define MIB_REG_BANK_SIZE 0x00000480
++#define CBR_A_REG_BANK_SIZE 0x001203fc
++#define MB_REG_BANK_SIZE 0x000000a0
++#define ID_MNG_REG_BANK_SIZE 0x00000084
++#define CSR_PHY_BANK_SIZE 0x000071c0
++#define CSR_RF_BANK_SIZE 0x000000b0
++#define MMU_REG_BANK_SIZE 0x000000c0
++#define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000)
++#define ADR_BOOT (SYS_REG_BASE+0x00000004)
++#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
++#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
++#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
++#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
++#define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018)
++#define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c)
++#define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020)
++#define ADR_MCU_DBG_SEL (SYS_REG_BASE+0x00000024)
++#define ADR_MCU_DBG_DATA (SYS_REG_BASE+0x00000028)
++#define ADR_AHB_BRG_STATUS (SYS_REG_BASE+0x0000002c)
++#define ADR_BIST_BIST_CTRL (SYS_REG_BASE+0x00000030)
++#define ADR_BIST_MODE_REG_IN (SYS_REG_BASE+0x00000034)
++#define ADR_BIST_MODE_REG_OUT (SYS_REG_BASE+0x00000038)
++#define ADR_BIST_MONITOR_BUS_LSB (SYS_REG_BASE+0x0000003c)
++#define ADR_BIST_MONITOR_BUS_MSB (SYS_REG_BASE+0x00000040)
++#define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044)
++#define ADR_TB_RDATA (SYS_REG_BASE+0x00000048)
++#define ADR_UART_W2B (SYS_REG_BASE+0x0000004c)
++#define ADR_AHB_ILL_ADDR (SYS_REG_BASE+0x00000050)
++#define ADR_AHB_FEN_ADDR (SYS_REG_BASE+0x00000054)
++#define ADR_AHB_ILLFEN_STATUS (SYS_REG_BASE+0x00000058)
++#define ADR_PWM_A (SYS_REG_BASE+0x00000080)
++#define ADR_PWM_B (SYS_REG_BASE+0x00000084)
++#define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090)
++#define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094)
++#define ADR_PRESCALER_USTIMER (SYS_REG_BASE+0x000000a0)
++#define ADR_BIST_MODE_REG_IN_MMU (SYS_REG_BASE+0x000000a4)
++#define ADR_BIST_MODE_REG_OUT_MMU (SYS_REG_BASE+0x000000a8)
++#define ADR_BIST_MONITOR_BUS_MMU (SYS_REG_BASE+0x000000ac)
++#define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0)
++#define ADR_BOOT_INFO (WBOOT_REG_BASE+0x00000000)
++#define ADR_SD_INIT_CFG (WBOOT_REG_BASE+0x00000004)
++#define ADR_SPARE_UART_INFO (WBOOT_REG_BASE+0x00000008)
++#define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000)
++#define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004)
++#define ADR_TU0_DUMMY_BIT_0 (TU0_US_REG_BASE+0x00000008)
++#define ADR_TU0_DUMMY_BIT_1 (TU0_US_REG_BASE+0x0000000c)
++#define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000)
++#define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004)
++#define ADR_TU1_DUMMY_BIT_0 (TU1_US_REG_BASE+0x00000008)
++#define ADR_TU1_DUMMY_BIT_1 (TU1_US_REG_BASE+0x0000000c)
++#define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000)
++#define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004)
++#define ADR_TU2_DUMMY_BIT_0 (TU2_US_REG_BASE+0x00000008)
++#define ADR_TU2_DUMMY_BIT_1 (TU2_US_REG_BASE+0x0000000c)
++#define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000)
++#define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004)
++#define ADR_TU3_DUMMY_BIT_0 (TU3_US_REG_BASE+0x00000008)
++#define ADR_TU3_DUMMY_BIT_1 (TU3_US_REG_BASE+0x0000000c)
++#define ADR_TM0_MILISECOND_TIMER (TM0_MS_REG_BASE+0x00000000)
++#define ADR_TM0_CURRENT_MILISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004)
++#define ADR_TM0_DUMMY_BIT_0 (TM0_MS_REG_BASE+0x00000008)
++#define ADR_TM0_DUMMY_BIT_1 (TM0_MS_REG_BASE+0x0000000c)
++#define ADR_TM1_MILISECOND_TIMER (TM1_MS_REG_BASE+0x00000000)
++#define ADR_TM1_CURRENT_MILISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004)
++#define ADR_TM1_DUMMY_BIT_0 (TM1_MS_REG_BASE+0x00000008)
++#define ADR_TM1_DUMMY_BIT_1 (TM1_MS_REG_BASE+0x0000000c)
++#define ADR_TM2_MILISECOND_TIMER (TM2_MS_REG_BASE+0x00000000)
++#define ADR_TM2_CURRENT_MILISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004)
++#define ADR_TM2_DUMMY_BIT_0 (TM2_MS_REG_BASE+0x00000008)
++#define ADR_TM2_DUMMY_BIT_1 (TM2_MS_REG_BASE+0x0000000c)
++#define ADR_TM3_MILISECOND_TIMER (TM3_MS_REG_BASE+0x00000000)
++#define ADR_TM3_CURRENT_MILISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004)
++#define ADR_TM3_DUMMY_BIT_0 (TM3_MS_REG_BASE+0x00000008)
++#define ADR_TM3_DUMMY_BIT_1 (TM3_MS_REG_BASE+0x0000000c)
++#define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000)
++#define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000)
++#define ADR_PAD6 (GPIO_REG_BASE+0x00000000)
++#define ADR_PAD7 (GPIO_REG_BASE+0x00000004)
++#define ADR_PAD8 (GPIO_REG_BASE+0x00000008)
++#define ADR_PAD9 (GPIO_REG_BASE+0x0000000c)
++#define ADR_PAD11 (GPIO_REG_BASE+0x00000010)
++#define ADR_PAD15 (GPIO_REG_BASE+0x00000014)
++#define ADR_PAD16 (GPIO_REG_BASE+0x00000018)
++#define ADR_PAD17 (GPIO_REG_BASE+0x0000001c)
++#define ADR_PAD18 (GPIO_REG_BASE+0x00000020)
++#define ADR_PAD19 (GPIO_REG_BASE+0x00000024)
++#define ADR_PAD20 (GPIO_REG_BASE+0x00000028)
++#define ADR_PAD21 (GPIO_REG_BASE+0x0000002c)
++#define ADR_PAD22 (GPIO_REG_BASE+0x00000030)
++#define ADR_PAD24 (GPIO_REG_BASE+0x00000034)
++#define ADR_PAD25 (GPIO_REG_BASE+0x00000038)
++#define ADR_PAD27 (GPIO_REG_BASE+0x0000003c)
++#define ADR_PAD28 (GPIO_REG_BASE+0x00000040)
++#define ADR_PAD29 (GPIO_REG_BASE+0x00000044)
++#define ADR_PAD30 (GPIO_REG_BASE+0x00000048)
++#define ADR_PAD31 (GPIO_REG_BASE+0x0000004c)
++#define ADR_PAD32 (GPIO_REG_BASE+0x00000050)
++#define ADR_PAD33 (GPIO_REG_BASE+0x00000054)
++#define ADR_PAD34 (GPIO_REG_BASE+0x00000058)
++#define ADR_PAD42 (GPIO_REG_BASE+0x0000005c)
++#define ADR_PAD43 (GPIO_REG_BASE+0x00000060)
++#define ADR_PAD44 (GPIO_REG_BASE+0x00000064)
++#define ADR_PAD45 (GPIO_REG_BASE+0x00000068)
++#define ADR_PAD46 (GPIO_REG_BASE+0x0000006c)
++#define ADR_PAD47 (GPIO_REG_BASE+0x00000070)
++#define ADR_PAD48 (GPIO_REG_BASE+0x00000074)
++#define ADR_PAD49 (GPIO_REG_BASE+0x00000078)
++#define ADR_PAD50 (GPIO_REG_BASE+0x0000007c)
++#define ADR_PAD51 (GPIO_REG_BASE+0x00000080)
++#define ADR_PAD52 (GPIO_REG_BASE+0x00000084)
++#define ADR_PAD53 (GPIO_REG_BASE+0x00000088)
++#define ADR_PAD54 (GPIO_REG_BASE+0x0000008c)
++#define ADR_PAD56 (GPIO_REG_BASE+0x00000090)
++#define ADR_PAD57 (GPIO_REG_BASE+0x00000094)
++#define ADR_PAD58 (GPIO_REG_BASE+0x00000098)
++#define ADR_PAD59 (GPIO_REG_BASE+0x0000009c)
++#define ADR_PAD60 (GPIO_REG_BASE+0x000000a0)
++#define ADR_PAD61 (GPIO_REG_BASE+0x000000a4)
++#define ADR_PAD62 (GPIO_REG_BASE+0x000000a8)
++#define ADR_PAD64 (GPIO_REG_BASE+0x000000ac)
++#define ADR_PAD65 (GPIO_REG_BASE+0x000000b0)
++#define ADR_PAD66 (GPIO_REG_BASE+0x000000b4)
++#define ADR_PAD68 (GPIO_REG_BASE+0x000000b8)
++#define ADR_PAD67 (GPIO_REG_BASE+0x000000bc)
++#define ADR_PAD69 (GPIO_REG_BASE+0x000000c0)
++#define ADR_PAD70 (GPIO_REG_BASE+0x000000c4)
++#define ADR_PAD231 (GPIO_REG_BASE+0x000000c8)
++#define ADR_PIN_SEL_0 (GPIO_REG_BASE+0x000000cc)
++#define ADR_PIN_SEL_1 (GPIO_REG_BASE+0x000000d0)
++#define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000)
++#define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004)
++#define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008)
++#define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c)
++#define ADR_CARD_PKT_STATUS_TEST (SD_REG_BASE+0x00000010)
++#define ADR_SYSTEM_INFORMATION_REG (SD_REG_BASE+0x0000001c)
++#define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020)
++#define ADR_SDIO_FIFO_WR_THLD_REG (SD_REG_BASE+0x00000024)
++#define ADR_SDIO_FIFO_WR_LIMIT_REG (SD_REG_BASE+0x00000028)
++#define ADR_SDIO_TX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x0000002c)
++#define ADR_SDIO_THLD_FOR_CMD53RD_REG (SD_REG_BASE+0x00000030)
++#define ADR_SDIO_RX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x00000034)
++#define ADR_SDIO_LOG_START_END_DATA_REG (SD_REG_BASE+0x00000038)
++#define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040)
++#define ADR_SDIO_LAST_CMD_INDEX_CRC_REG (SD_REG_BASE+0x00000044)
++#define ADR_SDIO_LAST_CMD_ARG_REG (SD_REG_BASE+0x00000048)
++#define ADR_SDIO_BUS_STATE_DEBUG_MONITOR (SD_REG_BASE+0x0000004c)
++#define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050)
++#define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054)
++#define ADR_CMD52_DATA_FOR_LAST_TIME (SD_REG_BASE+0x0000005c)
++#define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060)
++#define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064)
++#define ADR_IO_REG_PORT_REG (SD_REG_BASE+0x00000070)
++#define ADR_SDIO_FIFO_ERROR_CNT (SD_REG_BASE+0x0000007c)
++#define ADR_SDIO_CRC7_CRC16_ERROR_REG (SD_REG_BASE+0x00000080)
++#define ADR_SDIO_BLOCK_CNT_INFO (SD_REG_BASE+0x00000084)
++#define ADR_RX_DATA_CMD52_ABORT_COUNT (SD_REG_BASE+0x0000008c)
++#define ADR_FIFO_PTR_READ_BLOCK_CNT (SD_REG_BASE+0x00000090)
++#define ADR_TX_TIME_OUT_READ_CTRL (SD_REG_BASE+0x00000094)
++#define ADR_SDIO_TX_ALLOC_REG (SD_REG_BASE+0x00000098)
++#define ADR_SDIO_TX_INFORM (SD_REG_BASE+0x0000009c)
++#define ADR_F1_BLOCK_SIZE_0_REG (SD_REG_BASE+0x000000a0)
++#define ADR_SDIO_COMMAND_LOG_DATA_31_0 (SD_REG_BASE+0x000000b0)
++#define ADR_SDIO_COMMAND_LOG_DATA_63_32 (SD_REG_BASE+0x000000b4)
++#define ADR_SYSTEM_INFORMATION_REGISTER (SD_REG_BASE+0x000000bc)
++#define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0)
++#define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4)
++#define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8)
++#define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0)
++#define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0)
++#define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8)
++#define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100)
++#define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104)
++#define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108)
++#define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c)
++#define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110)
++#define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114)
++#define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118)
++#define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c)
++#define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120)
++#define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124)
++#define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128)
++#define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c)
++#define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130)
++#define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134)
++#define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138)
++#define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c)
++#define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140)
++#define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144)
++#define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148)
++#define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c)
++#define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150)
++#define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154)
++#define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158)
++#define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c)
++#define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160)
++#define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164)
++#define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168)
++#define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c)
++#define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170)
++#define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174)
++#define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178)
++#define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c)
++#define ADR_SPI_MODE (SPI_REG_BASE+0x00000000)
++#define ADR_RX_QUOTA (SPI_REG_BASE+0x00000004)
++#define ADR_CONDITION_NUMBER (SPI_REG_BASE+0x00000008)
++#define ADR_HOST_PATH (SPI_REG_BASE+0x0000000c)
++#define ADR_TX_SEG (SPI_REG_BASE+0x00000010)
++#define ADR_DEBUG_BURST_MODE (SPI_REG_BASE+0x00000014)
++#define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018)
++#define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c)
++#define ADR_SPI_STS (SPI_REG_BASE+0x00000020)
++#define ADR_TX_ALLOC_SET (SPI_REG_BASE+0x00000024)
++#define ADR_TX_ALLOC (SPI_REG_BASE+0x00000028)
++#define ADR_DBG_CNT (SPI_REG_BASE+0x0000002c)
++#define ADR_DBG_CNT2 (SPI_REG_BASE+0x00000030)
++#define ADR_DBG_CNT3 (SPI_REG_BASE+0x00000034)
++#define ADR_DBG_CNT4 (SPI_REG_BASE+0x00000038)
++#define ADR_INT_TAG (SPI_REG_BASE+0x0000003c)
++#define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000000)
++#define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000004)
++#define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x00000008)
++#define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x0000000c)
++#define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000010)
++#define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000014)
++#define ADR_UART_DATA (UART_REG_BASE+0x00000000)
++#define ADR_UART_IER (UART_REG_BASE+0x00000004)
++#define ADR_UART_FCR (UART_REG_BASE+0x00000008)
++#define ADR_UART_LCR (UART_REG_BASE+0x0000000c)
++#define ADR_UART_MCR (UART_REG_BASE+0x00000010)
++#define ADR_UART_LSR (UART_REG_BASE+0x00000014)
++#define ADR_UART_MSR (UART_REG_BASE+0x00000018)
++#define ADR_UART_SPR (UART_REG_BASE+0x0000001c)
++#define ADR_UART_RTHR (UART_REG_BASE+0x00000020)
++#define ADR_UART_ISR (UART_REG_BASE+0x00000024)
++#define ADR_DAT_UART_DATA (DAT_UART_REG_BASE+0x00000000)
++#define ADR_DAT_UART_IER (DAT_UART_REG_BASE+0x00000004)
++#define ADR_DAT_UART_FCR (DAT_UART_REG_BASE+0x00000008)
++#define ADR_DAT_UART_LCR (DAT_UART_REG_BASE+0x0000000c)
++#define ADR_DAT_UART_MCR (DAT_UART_REG_BASE+0x00000010)
++#define ADR_DAT_UART_LSR (DAT_UART_REG_BASE+0x00000014)
++#define ADR_DAT_UART_MSR (DAT_UART_REG_BASE+0x00000018)
++#define ADR_DAT_UART_SPR (DAT_UART_REG_BASE+0x0000001c)
++#define ADR_DAT_UART_RTHR (DAT_UART_REG_BASE+0x00000020)
++#define ADR_DAT_UART_ISR (DAT_UART_REG_BASE+0x00000024)
++#define ADR_INT_MASK (INT_REG_BASE+0x00000000)
++#define ADR_INT_MODE (INT_REG_BASE+0x00000004)
++#define ADR_INT_IRQ_STS (INT_REG_BASE+0x00000008)
++#define ADR_INT_FIQ_STS (INT_REG_BASE+0x0000000c)
++#define ADR_INT_IRQ_RAW (INT_REG_BASE+0x00000010)
++#define ADR_INT_FIQ_RAW (INT_REG_BASE+0x00000014)
++#define ADR_INT_PERI_MASK (INT_REG_BASE+0x00000018)
++#define ADR_INT_PERI_STS (INT_REG_BASE+0x0000001c)
++#define ADR_INT_PERI_RAW (INT_REG_BASE+0x00000020)
++#define ADR_INT_GPI_CFG (INT_REG_BASE+0x00000024)
++#define ADR_SYS_INT_FOR_HOST (INT_REG_BASE+0x00000028)
++#define ADR_SPI_IPC (INT_REG_BASE+0x00000034)
++#define ADR_SDIO_IPC (INT_REG_BASE+0x00000038)
++#define ADR_SDIO_MASK (INT_REG_BASE+0x0000003c)
++#define ADR_SDIO_IRQ_STS (INT_REG_BASE+0x00000040)
++#define ADR_SD_PERI_MASK (INT_REG_BASE+0x00000044)
++#define ADR_SD_PERI_STS (INT_REG_BASE+0x00000048)
++#define ADR_DBG_SPI_MODE (DBG_SPI_REG_BASE+0x00000000)
++#define ADR_DBG_RX_QUOTA (DBG_SPI_REG_BASE+0x00000004)
++#define ADR_DBG_CONDITION_NUMBER (DBG_SPI_REG_BASE+0x00000008)
++#define ADR_DBG_HOST_PATH (DBG_SPI_REG_BASE+0x0000000c)
++#define ADR_DBG_TX_SEG (DBG_SPI_REG_BASE+0x00000010)
++#define ADR_DBG_DEBUG_BURST_MODE (DBG_SPI_REG_BASE+0x00000014)
++#define ADR_DBG_SPI_TO_PHY_PARAM1 (DBG_SPI_REG_BASE+0x00000018)
++#define ADR_DBG_SPI_TO_PHY_PARAM2 (DBG_SPI_REG_BASE+0x0000001c)
++#define ADR_DBG_SPI_STS (DBG_SPI_REG_BASE+0x00000020)
++#define ADR_DBG_TX_ALLOC_SET (DBG_SPI_REG_BASE+0x00000024)
++#define ADR_DBG_TX_ALLOC (DBG_SPI_REG_BASE+0x00000028)
++#define ADR_DBG_DBG_CNT (DBG_SPI_REG_BASE+0x0000002c)
++#define ADR_DBG_DBG_CNT2 (DBG_SPI_REG_BASE+0x00000030)
++#define ADR_DBG_DBG_CNT3 (DBG_SPI_REG_BASE+0x00000034)
++#define ADR_DBG_DBG_CNT4 (DBG_SPI_REG_BASE+0x00000038)
++#define ADR_DBG_INT_TAG (DBG_SPI_REG_BASE+0x0000003c)
++#define ADR_BOOT_ADDR (FLASH_SPI_REG_BASE+0x00000000)
++#define ADR_VERIFY_DATA (FLASH_SPI_REG_BASE+0x00000004)
++#define ADR_FLASH_ADDR (FLASH_SPI_REG_BASE+0x00000008)
++#define ADR_SRAM_ADDR (FLASH_SPI_REG_BASE+0x0000000c)
++#define ADR_LEN (FLASH_SPI_REG_BASE+0x00000010)
++#define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000014)
++#define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x00000018)
++#define ADR_CHECK_SUM_RESULT (FLASH_SPI_REG_BASE+0x0000001c)
++#define ADR_CHECK_SUM_IN_FILE (FLASH_SPI_REG_BASE+0x00000020)
++#define ADR_COMMAND_LEN (FLASH_SPI_REG_BASE+0x00000024)
++#define ADR_COMMAND_ADDR (FLASH_SPI_REG_BASE+0x00000028)
++#define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000)
++#define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004)
++#define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008)
++#define ADR_DMA_INT (DMA_REG_BASE+0x0000000c)
++#define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010)
++#define ADR_PMU_0 (CSR_PMU_BASE+0x00000000)
++#define ADR_PMU_1 (CSR_PMU_BASE+0x00000004)
++#define ADR_PMU_2 (CSR_PMU_BASE+0x00000008)
++#define ADR_PMU_3 (CSR_PMU_BASE+0x0000000c)
++#define ADR_RTC_1 (CSR_RTC_BASE+0x00000000)
++#define ADR_RTC_2 (CSR_RTC_BASE+0x00000004)
++#define ADR_RTC_3W (CSR_RTC_BASE+0x00000008)
++#define ADR_RTC_3R (CSR_RTC_BASE+0x00000008)
++#define ADR_RTC_4 (CSR_RTC_BASE+0x0000000c)
++#define ADR_RTC_RAM (RTC_RAM_BASE+0x00000000)
++#define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000)
++#define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004)
++#define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008)
++#define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c)
++#define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010)
++#define ADR_CONTROL (HCI_REG_BASE+0x00000000)
++#define ADR_SDIO_WAKE_MODE (HCI_REG_BASE+0x00000004)
++#define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008)
++#define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c)
++#define ADR_THREASHOLD (HCI_REG_BASE+0x00000018)
++#define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020)
++#define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028)
++#define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030)
++#define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034)
++#define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050)
++#define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054)
++#define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060)
++#define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064)
++#define ADR_PACKET_COUNTER_INFO_0 (HCI_REG_BASE+0x00000070)
++#define ADR_PACKET_COUNTER_INFO_1 (HCI_REG_BASE+0x00000074)
++#define ADR_PACKET_COUNTER_INFO_2 (HCI_REG_BASE+0x00000078)
++#define ADR_PACKET_COUNTER_INFO_3 (HCI_REG_BASE+0x0000007c)
++#define ADR_PACKET_COUNTER_INFO_4 (HCI_REG_BASE+0x00000080)
++#define ADR_PACKET_COUNTER_INFO_5 (HCI_REG_BASE+0x00000084)
++#define ADR_PACKET_COUNTER_INFO_6 (HCI_REG_BASE+0x00000088)
++#define ADR_PACKET_COUNTER_INFO_7 (HCI_REG_BASE+0x0000008c)
++#define ADR_SDIO_TX_RX_FAIL_COUNTER_0 (HCI_REG_BASE+0x00000090)
++#define ADR_SDIO_TX_RX_FAIL_COUNTER_1 (HCI_REG_BASE+0x00000094)
++#define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a0)
++#define ADR_HCI_STATE_DEBUG_MODE_1 (HCI_REG_BASE+0x000000a4)
++#define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000a8)
++#define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000ac)
++#define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b0)
++#define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000b4)
++#define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000b8)
++#define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000bc)
++#define ADR_HCI_STATE_DEBUG_MODE_8 (HCI_REG_BASE+0x000000c0)
++#define ADR_HCI_STATE_DEBUG_MODE_9 (HCI_REG_BASE+0x000000c4)
++#define ADR_HCI_STATE_DEBUG_MODE_10 (HCI_REG_BASE+0x000000c8)
++#define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000)
++#define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004)
++#define ADR_CS_CMD (CO_REG_BASE+0x00000008)
++#define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c)
++#define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010)
++#define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014)
++#define ADR_RAND_EN (CO_REG_BASE+0x00000018)
++#define ADR_RAND_NUM (CO_REG_BASE+0x0000001c)
++#define ADR_MUL_OP1 (CO_REG_BASE+0x00000060)
++#define ADR_MUL_OP2 (CO_REG_BASE+0x00000064)
++#define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068)
++#define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c)
++#define ADR_DMA_RDATA (CO_REG_BASE+0x00000070)
++#define ADR_DMA_WDATA (CO_REG_BASE+0x00000074)
++#define ADR_DMA_LEN (CO_REG_BASE+0x00000078)
++#define ADR_DMA_CLR (CO_REG_BASE+0x0000007c)
++#define ADR_NAV_DATA (CO_REG_BASE+0x00000080)
++#define ADR_CO_NAV (CO_REG_BASE+0x00000084)
++#define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0)
++#define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4)
++#define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8)
++#define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000)
++#define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004)
++#define ADR_EFUSE_AHB_RDATA_0 (EFS_REG_BASE+0x00000008)
++#define ADR_EFUSE_WDATA_0 (EFS_REG_BASE+0x00000008)
++#define ADR_EFUSE_AHB_RDATA_1 (EFS_REG_BASE+0x0000000c)
++#define ADR_EFUSE_WDATA_1 (EFS_REG_BASE+0x0000000c)
++#define ADR_EFUSE_AHB_RDATA_2 (EFS_REG_BASE+0x00000010)
++#define ADR_EFUSE_WDATA_2 (EFS_REG_BASE+0x00000010)
++#define ADR_EFUSE_AHB_RDATA_3 (EFS_REG_BASE+0x00000014)
++#define ADR_EFUSE_WDATA_3 (EFS_REG_BASE+0x00000014)
++#define ADR_EFUSE_AHB_RDATA_4 (EFS_REG_BASE+0x00000018)
++#define ADR_EFUSE_WDATA_4 (EFS_REG_BASE+0x00000018)
++#define ADR_EFUSE_AHB_RDATA_5 (EFS_REG_BASE+0x0000001c)
++#define ADR_EFUSE_WDATA_5 (EFS_REG_BASE+0x0000001c)
++#define ADR_EFUSE_AHB_RDATA_6 (EFS_REG_BASE+0x00000020)
++#define ADR_EFUSE_WDATA_6 (EFS_REG_BASE+0x00000020)
++#define ADR_EFUSE_AHB_RDATA_7 (EFS_REG_BASE+0x00000024)
++#define ADR_EFUSE_WDATA_7 (EFS_REG_BASE+0x00000024)
++#define ADR_EFUSE_SPI_RD0_EN (EFS_REG_BASE+0x00000028)
++#define ADR_EFUSE_SPI_RD1_EN (EFS_REG_BASE+0x0000002c)
++#define ADR_EFUSE_SPI_RD2_EN (EFS_REG_BASE+0x00000030)
++#define ADR_EFUSE_SPI_RD3_EN (EFS_REG_BASE+0x00000034)
++#define ADR_EFUSE_SPI_RD4_EN (EFS_REG_BASE+0x00000038)
++#define ADR_EFUSE_SPI_RD5_EN (EFS_REG_BASE+0x0000003c)
++#define ADR_EFUSE_SPI_RD6_EN (EFS_REG_BASE+0x00000040)
++#define ADR_EFUSE_SPI_RD7_EN (EFS_REG_BASE+0x00000044)
++#define ADR_EFUSE_SPI_BUSY (EFS_REG_BASE+0x00000048)
++#define ADR_EFUSE_SPI_RDATA_0 (EFS_REG_BASE+0x0000004c)
++#define ADR_EFUSE_SPI_RDATA_1 (EFS_REG_BASE+0x00000050)
++#define ADR_EFUSE_SPI_RDATA_2 (EFS_REG_BASE+0x00000054)
++#define ADR_EFUSE_SPI_RDATA_3 (EFS_REG_BASE+0x00000058)
++#define ADR_EFUSE_SPI_RDATA_4 (EFS_REG_BASE+0x0000005c)
++#define ADR_EFUSE_SPI_RDATA_5 (EFS_REG_BASE+0x00000060)
++#define ADR_EFUSE_SPI_RDATA_6 (EFS_REG_BASE+0x00000064)
++#define ADR_EFUSE_SPI_RDATA_7 (EFS_REG_BASE+0x00000068)
++#define ADR_SMS4_CFG1 (SMS4_REG_BASE+0x00000000)
++#define ADR_SMS4_CFG2 (SMS4_REG_BASE+0x00000004)
++#define ADR_SMS4_MODE1 (SMS4_REG_BASE+0x00000008)
++#define ADR_SMS4_TRIG (SMS4_REG_BASE+0x00000010)
++#define ADR_SMS4_STATUS1 (SMS4_REG_BASE+0x00000014)
++#define ADR_SMS4_STATUS2 (SMS4_REG_BASE+0x00000018)
++#define ADR_SMS4_DATA_IN0 (SMS4_REG_BASE+0x00000020)
++#define ADR_SMS4_DATA_IN1 (SMS4_REG_BASE+0x00000024)
++#define ADR_SMS4_DATA_IN2 (SMS4_REG_BASE+0x00000028)
++#define ADR_SMS4_DATA_IN3 (SMS4_REG_BASE+0x0000002c)
++#define ADR_SMS4_DATA_OUT0 (SMS4_REG_BASE+0x00000030)
++#define ADR_SMS4_DATA_OUT1 (SMS4_REG_BASE+0x00000034)
++#define ADR_SMS4_DATA_OUT2 (SMS4_REG_BASE+0x00000038)
++#define ADR_SMS4_DATA_OUT3 (SMS4_REG_BASE+0x0000003c)
++#define ADR_SMS4_KEY_0 (SMS4_REG_BASE+0x00000040)
++#define ADR_SMS4_KEY_1 (SMS4_REG_BASE+0x00000044)
++#define ADR_SMS4_KEY_2 (SMS4_REG_BASE+0x00000048)
++#define ADR_SMS4_KEY_3 (SMS4_REG_BASE+0x0000004c)
++#define ADR_SMS4_MODE_IV0 (SMS4_REG_BASE+0x00000050)
++#define ADR_SMS4_MODE_IV1 (SMS4_REG_BASE+0x00000054)
++#define ADR_SMS4_MODE_IV2 (SMS4_REG_BASE+0x00000058)
++#define ADR_SMS4_MODE_IV3 (SMS4_REG_BASE+0x0000005c)
++#define ADR_SMS4_OFB_ENC0 (SMS4_REG_BASE+0x00000060)
++#define ADR_SMS4_OFB_ENC1 (SMS4_REG_BASE+0x00000064)
++#define ADR_SMS4_OFB_ENC2 (SMS4_REG_BASE+0x00000068)
++#define ADR_SMS4_OFB_ENC3 (SMS4_REG_BASE+0x0000006c)
++#define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000)
++#define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004)
++#define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008)
++#define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c)
++#define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010)
++#define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014)
++#define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018)
++#define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c)
++#define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020)
++#define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024)
++#define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028)
++#define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c)
++#define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030)
++#define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034)
++#define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038)
++#define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c)
++#define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040)
++#define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044)
++#define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048)
++#define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c)
++#define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050)
++#define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054)
++#define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070)
++#define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074)
++#define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078)
++#define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c)
++#define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080)
++#define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084)
++#define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088)
++#define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c)
++#define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090)
++#define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094)
++#define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098)
++#define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c)
++#define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0)
++#define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4)
++#define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8)
++#define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac)
++#define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0)
++#define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4)
++#define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8)
++#define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc)
++#define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0)
++#define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4)
++#define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8)
++#define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc)
++#define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0)
++#define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4)
++#define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0)
++#define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4)
++#define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8)
++#define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec)
++#define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0)
++#define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4)
++#define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8)
++#define ADR_BA_CTRL (MRX_REG_BASE+0x00000100)
++#define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104)
++#define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108)
++#define ADR_BA_TID (MRX_REG_BASE+0x0000010c)
++#define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110)
++#define ADR_BA_SB0 (MRX_REG_BASE+0x00000114)
++#define ADR_BA_SB1 (MRX_REG_BASE+0x00000118)
++#define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c)
++#define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120)
++#define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124)
++#define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128)
++#define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c)
++#define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130)
++#define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134)
++#define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138)
++#define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c)
++#define ADR_WSID0_TID0_RX_SEQ (MRX_REG_BASE+0x00000140)
++#define ADR_WSID0_TID1_RX_SEQ (MRX_REG_BASE+0x00000144)
++#define ADR_WSID0_TID2_RX_SEQ (MRX_REG_BASE+0x00000148)
++#define ADR_WSID0_TID3_RX_SEQ (MRX_REG_BASE+0x0000014c)
++#define ADR_WSID0_TID4_RX_SEQ (MRX_REG_BASE+0x00000150)
++#define ADR_WSID0_TID5_RX_SEQ (MRX_REG_BASE+0x00000154)
++#define ADR_WSID0_TID6_RX_SEQ (MRX_REG_BASE+0x00000158)
++#define ADR_WSID0_TID7_RX_SEQ (MRX_REG_BASE+0x0000015c)
++#define ADR_WSID1_TID0_RX_SEQ (MRX_REG_BASE+0x00000170)
++#define ADR_WSID1_TID1_RX_SEQ (MRX_REG_BASE+0x00000174)
++#define ADR_WSID1_TID2_RX_SEQ (MRX_REG_BASE+0x00000178)
++#define ADR_WSID1_TID3_RX_SEQ (MRX_REG_BASE+0x0000017c)
++#define ADR_WSID1_TID4_RX_SEQ (MRX_REG_BASE+0x00000180)
++#define ADR_WSID1_TID5_RX_SEQ (MRX_REG_BASE+0x00000184)
++#define ADR_WSID1_TID6_RX_SEQ (MRX_REG_BASE+0x00000188)
++#define ADR_WSID1_TID7_RX_SEQ (MRX_REG_BASE+0x0000018c)
++#define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000190)
++#define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000194)
++#define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000)
++#define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004)
++#define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008)
++#define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c)
++#define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010)
++#define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000)
++#define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004)
++#define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008)
++#define ADR_MTX_EDCCA_TOUT (MT_REG_CSR_BASE+0x00000010)
++#define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0)
++#define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4)
++#define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8)
++#define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac)
++#define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0)
++#define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4)
++#define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8)
++#define ADR_MTX_BCN_CFG0 (MT_REG_CSR_BASE+0x000000bc)
++#define ADR_MTX_BCN_CFG1 (MT_REG_CSR_BASE+0x000000c0)
++#define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc)
++#define ADR_MTX_DBG_CTRL (MT_REG_CSR_BASE+0x000000d0)
++#define ADR_MTX_DBG_DAT0 (MT_REG_CSR_BASE+0x000000d4)
++#define ADR_MTX_DBG_DAT1 (MT_REG_CSR_BASE+0x000000d8)
++#define ADR_MTX_DBG_DAT2 (MT_REG_CSR_BASE+0x000000dc)
++#define ADR_MTX_DUR_TOUT (MT_REG_CSR_BASE+0x000000e0)
++#define ADR_MTX_DUR_IFS (MT_REG_CSR_BASE+0x000000e4)
++#define ADR_MTX_DUR_SIFS_G (MT_REG_CSR_BASE+0x000000e8)
++#define ADR_MTX_DBG_DAT3 (MT_REG_CSR_BASE+0x000000ec)
++#define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0)
++#define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x000000f4)
++#define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x000000f8)
++#define ADR_MTX_DBG_DAT4 (MT_REG_CSR_BASE+0x000000fc)
++#define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ0_MTX_Q_BKF_CNT (TXQ0_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ0_MTX_Q_RC_LIMIT (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ0_MTX_Q_ID_MAP_L (TXQ0_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ0_MTX_Q_TXOP_CH_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ0_MTX_Q_TXOP_OV_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ1_MTX_Q_BKF_CNT (TXQ1_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ1_MTX_Q_RC_LIMIT (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ1_MTX_Q_ID_MAP_L (TXQ1_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ1_MTX_Q_TXOP_CH_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ1_MTX_Q_TXOP_OV_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ2_MTX_Q_BKF_CNT (TXQ2_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ2_MTX_Q_RC_LIMIT (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ2_MTX_Q_ID_MAP_L (TXQ2_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ2_MTX_Q_TXOP_CH_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ2_MTX_Q_TXOP_OV_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ3_MTX_Q_BKF_CNT (TXQ3_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ3_MTX_Q_RC_LIMIT (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ3_MTX_Q_ID_MAP_L (TXQ3_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ3_MTX_Q_TXOP_CH_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ3_MTX_Q_TXOP_OV_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ4_MTX_Q_BKF_CNT (TXQ4_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ4_MTX_Q_RC_LIMIT (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ4_MTX_Q_ID_MAP_L (TXQ4_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ4_MTX_Q_TXOP_CH_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ4_MTX_Q_TXOP_OV_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_WSID0 (HIF_INFO_BASE+0x00000000)
++#define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004)
++#define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008)
++#define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c)
++#define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010)
++#define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014)
++#define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018)
++#define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c)
++#define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020)
++#define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024)
++#define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028)
++#define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c)
++#define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030)
++#define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034)
++#define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038)
++#define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c)
++#define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040)
++#define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044)
++#define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048)
++#define ADR_WSID1 (HIF_INFO_BASE+0x00000050)
++#define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054)
++#define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058)
++#define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c)
++#define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060)
++#define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064)
++#define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068)
++#define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c)
++#define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070)
++#define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074)
++#define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078)
++#define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c)
++#define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080)
++#define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084)
++#define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088)
++#define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c)
++#define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090)
++#define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094)
++#define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098)
++#define ADR_INFO0 (PHY_RATE_INFO_BASE+0x00000000)
++#define ADR_INFO1 (PHY_RATE_INFO_BASE+0x00000004)
++#define ADR_INFO2 (PHY_RATE_INFO_BASE+0x00000008)
++#define ADR_INFO3 (PHY_RATE_INFO_BASE+0x0000000c)
++#define ADR_INFO4 (PHY_RATE_INFO_BASE+0x00000010)
++#define ADR_INFO5 (PHY_RATE_INFO_BASE+0x00000014)
++#define ADR_INFO6 (PHY_RATE_INFO_BASE+0x00000018)
++#define ADR_INFO7 (PHY_RATE_INFO_BASE+0x0000001c)
++#define ADR_INFO8 (PHY_RATE_INFO_BASE+0x00000020)
++#define ADR_INFO9 (PHY_RATE_INFO_BASE+0x00000024)
++#define ADR_INFO10 (PHY_RATE_INFO_BASE+0x00000028)
++#define ADR_INFO11 (PHY_RATE_INFO_BASE+0x0000002c)
++#define ADR_INFO12 (PHY_RATE_INFO_BASE+0x00000030)
++#define ADR_INFO13 (PHY_RATE_INFO_BASE+0x00000034)
++#define ADR_INFO14 (PHY_RATE_INFO_BASE+0x00000038)
++#define ADR_INFO15 (PHY_RATE_INFO_BASE+0x0000003c)
++#define ADR_INFO16 (PHY_RATE_INFO_BASE+0x00000040)
++#define ADR_INFO17 (PHY_RATE_INFO_BASE+0x00000044)
++#define ADR_INFO18 (PHY_RATE_INFO_BASE+0x00000048)
++#define ADR_INFO19 (PHY_RATE_INFO_BASE+0x0000004c)
++#define ADR_INFO20 (PHY_RATE_INFO_BASE+0x00000050)
++#define ADR_INFO21 (PHY_RATE_INFO_BASE+0x00000054)
++#define ADR_INFO22 (PHY_RATE_INFO_BASE+0x00000058)
++#define ADR_INFO23 (PHY_RATE_INFO_BASE+0x0000005c)
++#define ADR_INFO24 (PHY_RATE_INFO_BASE+0x00000060)
++#define ADR_INFO25 (PHY_RATE_INFO_BASE+0x00000064)
++#define ADR_INFO26 (PHY_RATE_INFO_BASE+0x00000068)
++#define ADR_INFO27 (PHY_RATE_INFO_BASE+0x0000006c)
++#define ADR_INFO28 (PHY_RATE_INFO_BASE+0x00000070)
++#define ADR_INFO29 (PHY_RATE_INFO_BASE+0x00000074)
++#define ADR_INFO30 (PHY_RATE_INFO_BASE+0x00000078)
++#define ADR_INFO31 (PHY_RATE_INFO_BASE+0x0000007c)
++#define ADR_INFO32 (PHY_RATE_INFO_BASE+0x00000080)
++#define ADR_INFO33 (PHY_RATE_INFO_BASE+0x00000084)
++#define ADR_INFO34 (PHY_RATE_INFO_BASE+0x00000088)
++#define ADR_INFO35 (PHY_RATE_INFO_BASE+0x0000008c)
++#define ADR_INFO36 (PHY_RATE_INFO_BASE+0x00000090)
++#define ADR_INFO37 (PHY_RATE_INFO_BASE+0x00000094)
++#define ADR_INFO38 (PHY_RATE_INFO_BASE+0x00000098)
++#define ADR_INFO_MASK (PHY_RATE_INFO_BASE+0x0000009c)
++#define ADR_INFO_RATE_OFFSET (PHY_RATE_INFO_BASE+0x000000a0)
++#define ADR_INFO_IDX_ADDR (PHY_RATE_INFO_BASE+0x000000a4)
++#define ADR_INFO_LEN_ADDR (PHY_RATE_INFO_BASE+0x000000a8)
++#define ADR_IC_TIME_TAG_0 (PHY_RATE_INFO_BASE+0x000000ac)
++#define ADR_IC_TIME_TAG_1 (PHY_RATE_INFO_BASE+0x000000b0)
++#define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x000000b4)
++#define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000)
++#define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004)
++#define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008)
++#define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c)
++#define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010)
++#define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014)
++#define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018)
++#define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c)
++#define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020)
++#define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024)
++#define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028)
++#define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c)
++#define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000002c)
++#define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030)
++#define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034)
++#define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038)
++#define ADR_BTCX0 (BTCX_REG_BASE+0x00000000)
++#define ADR_BTCX1 (BTCX_REG_BASE+0x00000004)
++#define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008)
++#define ADR_MIB_EN (MIB_REG_BASE+0x00000000)
++#define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118)
++#define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128)
++#define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138)
++#define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148)
++#define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c)
++#define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170)
++#define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174)
++#define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178)
++#define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c)
++#define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180)
++#define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184)
++#define ADR_MTX_FRM (MIB_REG_BASE+0x00000188)
++#define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c)
++#define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190)
++#define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194)
++#define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198)
++#define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c)
++#define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0)
++#define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4)
++#define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8)
++#define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac)
++#define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0)
++#define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4)
++#define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8)
++#define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc)
++#define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0)
++#define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4)
++#define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8)
++#define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc)
++#define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0)
++#define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4)
++#define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8)
++#define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc)
++#define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218)
++#define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c)
++#define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220)
++#define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224)
++#define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268)
++#define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c)
++#define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270)
++#define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274)
++#define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318)
++#define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c)
++#define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320)
++#define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324)
++#define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368)
++#define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c)
++#define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370)
++#define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374)
++#define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418)
++#define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c)
++#define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420)
++#define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424)
++#define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428)
++#define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468)
++#define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c)
++#define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470)
++#define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474)
++#define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478)
++#define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c)
++#define ADR_CBR_HARD_WIRE_PIN_REGISTER (CBR_A_REG_BASE+0x00110000)
++#define ADR_CBR_MANUAL_ENABLE_REGISTER (CBR_A_REG_BASE+0x00110004)
++#define ADR_CBR_LDO_REGISTER (CBR_A_REG_BASE+0x00110008)
++#define ADR_CBR_ABB_REGISTER_1 (CBR_A_REG_BASE+0x0011000c)
++#define ADR_CBR_ABB_REGISTER_2 (CBR_A_REG_BASE+0x00110010)
++#define ADR_CBR_TX_FE_REGISTER (CBR_A_REG_BASE+0x00110014)
++#define ADR_CBR_RX_FE_REGISTER_1 (CBR_A_REG_BASE+0x00110018)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1 (CBR_A_REG_BASE+0x0011001c)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2 (CBR_A_REG_BASE+0x00110020)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3 (CBR_A_REG_BASE+0x00110024)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4 (CBR_A_REG_BASE+0x00110028)
++#define ADR_CBR_RX_FSM_REGISTER (CBR_A_REG_BASE+0x0011002c)
++#define ADR_CBR_RX_ADC_REGISTER (CBR_A_REG_BASE+0x00110030)
++#define ADR_CBR_TX_DAC_REGISTER (CBR_A_REG_BASE+0x00110034)
++#define ADR_CBR_SX_ENABLE_RGISTER (CBR_A_REG_BASE+0x00110038)
++#define ADR_CBR_SYN_RGISTER_1 (CBR_A_REG_BASE+0x0011003c)
++#define ADR_CBR_SYN_RGISTER_2 (CBR_A_REG_BASE+0x00110040)
++#define ADR_CBR_SYN_PFD_CHP (CBR_A_REG_BASE+0x00110044)
++#define ADR_CBR_SYN_VCO_LOBF (CBR_A_REG_BASE+0x00110048)
++#define ADR_CBR_SYN_DIV_SDM_XOSC (CBR_A_REG_BASE+0x0011004c)
++#define ADR_CBR_SYN_LCK1 (CBR_A_REG_BASE+0x00110050)
++#define ADR_CBR_SYN_LCK2 (CBR_A_REG_BASE+0x00110054)
++#define ADR_CBR_DPLL_VCO_REGISTER (CBR_A_REG_BASE+0x00110058)
++#define ADR_CBR_DPLL_CP_PFD_REGISTER (CBR_A_REG_BASE+0x0011005c)
++#define ADR_CBR_DPLL_DIVIDER_REGISTER (CBR_A_REG_BASE+0x00110060)
++#define ADR_CBR_DCOC_IDAC_REGISTER1 (CBR_A_REG_BASE+0x00110064)
++#define ADR_CBR_DCOC_IDAC_REGISTER2 (CBR_A_REG_BASE+0x00110068)
++#define ADR_CBR_DCOC_IDAC_REGISTER3 (CBR_A_REG_BASE+0x0011006c)
++#define ADR_CBR_DCOC_IDAC_REGISTER4 (CBR_A_REG_BASE+0x00110070)
++#define ADR_CBR_DCOC_IDAC_REGISTER5 (CBR_A_REG_BASE+0x00110074)
++#define ADR_CBR_DCOC_IDAC_REGISTER6 (CBR_A_REG_BASE+0x00110078)
++#define ADR_CBR_DCOC_IDAC_REGISTER7 (CBR_A_REG_BASE+0x0011007c)
++#define ADR_CBR_DCOC_IDAC_REGISTER8 (CBR_A_REG_BASE+0x00110080)
++#define ADR_CBR_RCAL_REGISTER (CBR_A_REG_BASE+0x00110084)
++#define ADR_CBR_MANUAL_REGISTER (CBR_A_REG_BASE+0x00110088)
++#define ADR_CBR_TRX_DUMMY_REGISTER (CBR_A_REG_BASE+0x0011008c)
++#define ADR_CBR_SX_DUMMY_REGISTER (CBR_A_REG_BASE+0x00110090)
++#define ADR_CBR_READ_ONLY_FLAGS_1 (CBR_A_REG_BASE+0x00110094)
++#define ADR_CBR_READ_ONLY_FLAGS_2 (CBR_A_REG_BASE+0x00110098)
++#define ADR_CBR_RG_PKT_GEN_0 (CBR_A_REG_BASE+0x00120080)
++#define ADR_CBR_RG_PKT_GEN_1 (CBR_A_REG_BASE+0x00120084)
++#define ADR_CBR_RG_PKT_GEN_2 (CBR_A_REG_BASE+0x00120088)
++#define ADR_CBR_RG_INTEGRATION (CBR_A_REG_BASE+0x00120090)
++#define ADR_CBR_RG_PKT_GEN_TXCNT (CBR_A_REG_BASE+0x00120094)
++#define ADR_CBR_PATTERN_GEN (CBR_A_REG_BASE+0x001203f8)
++#define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004)
++#define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008)
++#define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c)
++#define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010)
++#define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010)
++#define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014)
++#define ADR_MCU_STATUS (MB_REG_BASE+0x00000018)
++#define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c)
++#define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020)
++#define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024)
++#define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c)
++#define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030)
++#define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034)
++#define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038)
++#define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c)
++#define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040)
++#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044)
++#define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048)
++#define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c)
++#define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050)
++#define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054)
++#define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c)
++#define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070)
++#define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074)
++#define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078)
++#define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c)
++#define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080)
++#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084)
++#define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088)
++#define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c)
++#define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090)
++#define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094)
++#define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098)
++#define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c)
++#define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000)
++#define ADR_GETID (ID_MNG_REG_BASE+0x00000000)
++#define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004)
++#define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008)
++#define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c)
++#define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010)
++#define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014)
++#define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018)
++#define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c)
++#define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020)
++#define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024)
++#define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028)
++#define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c)
++#define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030)
++#define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034)
++#define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038)
++#define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c)
++#define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040)
++#define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044)
++#define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048)
++#define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c)
++#define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050)
++#define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054)
++#define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058)
++#define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c)
++#define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060)
++#define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064)
++#define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068)
++#define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c)
++#define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070)
++#define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074)
++#define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078)
++#define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c)
++#define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080)
++#define ADR_PHY_EN_0 (CSR_PHY_BASE+0x00000000)
++#define ADR_PHY_EN_1 (CSR_PHY_BASE+0x00000004)
++#define ADR_SVN_VERSION_REG (CSR_PHY_BASE+0x00000008)
++#define ADR_PHY_PKT_GEN_0 (CSR_PHY_BASE+0x0000000c)
++#define ADR_PHY_PKT_GEN_1 (CSR_PHY_BASE+0x00000010)
++#define ADR_PHY_PKT_GEN_2 (CSR_PHY_BASE+0x00000014)
++#define ADR_PHY_PKT_GEN_3 (CSR_PHY_BASE+0x00000018)
++#define ADR_PHY_PKT_GEN_4 (CSR_PHY_BASE+0x0000001c)
++#define ADR_PHY_REG_00 (CSR_PHY_BASE+0x00000020)
++#define ADR_PHY_REG_01 (CSR_PHY_BASE+0x0000002c)
++#define ADR_PHY_REG_02_AGC (CSR_PHY_BASE+0x00000030)
++#define ADR_PHY_REG_03_AGC (CSR_PHY_BASE+0x00000034)
++#define ADR_PHY_REG_04_AGC (CSR_PHY_BASE+0x00000038)
++#define ADR_PHY_REG_05_AGC (CSR_PHY_BASE+0x0000003c)
++#define ADR_PHY_REG_06_11B_DAGC (CSR_PHY_BASE+0x00000040)
++#define ADR_PHY_REG_07_11B_DAGC (CSR_PHY_BASE+0x00000044)
++#define ADR_PHY_REG_08_11GN_DAGC (CSR_PHY_BASE+0x00000048)
++#define ADR_PHY_REG_09_11GN_DAGC (CSR_PHY_BASE+0x0000004c)
++#define ADR_PHY_READ_REG_00_DIG_PWR (CSR_PHY_BASE+0x00000050)
++#define ADR_PHY_READ_REG_01_RF_GAIN_PWR (CSR_PHY_BASE+0x00000054)
++#define ADR_PHY_READ_REG_02_RF_GAIN_PWR (CSR_PHY_BASE+0x00000058)
++#define ADR_PHY_READ_REG_03_RF_GAIN_PWR (CSR_PHY_BASE+0x0000005c)
++#define ADR_PHY_REG_10_TX_DES (CSR_PHY_BASE+0x00000060)
++#define ADR_PHY_REG_11_TX_DES (CSR_PHY_BASE+0x00000064)
++#define ADR_PHY_REG_12_TX_DES (CSR_PHY_BASE+0x00000068)
++#define ADR_PHY_REG_13_RX_DES (CSR_PHY_BASE+0x0000006c)
++#define ADR_PHY_REG_14_RX_DES (CSR_PHY_BASE+0x00000070)
++#define ADR_PHY_REG_15_RX_DES (CSR_PHY_BASE+0x00000074)
++#define ADR_PHY_REG_16_TX_DES_EXCP (CSR_PHY_BASE+0x00000078)
++#define ADR_PHY_REG_17_TX_DES_EXCP (CSR_PHY_BASE+0x0000007c)
++#define ADR_PHY_REG_18_RSSI_SNR (CSR_PHY_BASE+0x00000080)
++#define ADR_PHY_REG_19_DAC_MANUAL (CSR_PHY_BASE+0x00000084)
++#define ADR_PHY_REG_20_MRX_CNT (CSR_PHY_BASE+0x00000088)
++#define ADR_PHY_REG_21_TRX_RAMP (CSR_PHY_BASE+0x00000094)
++#define ADR_PHY_REG_22_TRX_RAMP (CSR_PHY_BASE+0x00000098)
++#define ADR_PHY_REG_23_ANT (CSR_PHY_BASE+0x0000009c)
++#define ADR_PHY_REG_24_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a0)
++#define ADR_PHY_REG_25_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a4)
++#define ADR_PHY_REG_26_MRX_LEN_CNT (CSR_PHY_BASE+0x000000a8)
++#define ADR_PHY_REG_27_MRX_LEN_CNT (CSR_PHY_BASE+0x000000ac)
++#define ADR_PHY_READ_REG_04 (CSR_PHY_BASE+0x000000b0)
++#define ADR_PHY_READ_REG_05 (CSR_PHY_BASE+0x000000b4)
++#define ADR_PHY_REG_28_BIST (CSR_PHY_BASE+0x000000b8)
++#define ADR_PHY_READ_REG_06_BIST (CSR_PHY_BASE+0x000000d8)
++#define ADR_PHY_READ_REG_07_BIST (CSR_PHY_BASE+0x000000f0)
++#define ADR_PHY_REG_29_MTRX_MAC (CSR_PHY_BASE+0x000000fc)
++#define ADR_PHY_READ_REG_08_MTRX_MAC (CSR_PHY_BASE+0x00000100)
++#define ADR_PHY_READ_REG_09_MTRX_MAC (CSR_PHY_BASE+0x00000104)
++#define ADR_PHY_REG_30_TX_UP_FIL (CSR_PHY_BASE+0x00000108)
++#define ADR_PHY_REG_31_TX_UP_FIL (CSR_PHY_BASE+0x0000010c)
++#define ADR_PHY_REG_32_TX_UP_FIL (CSR_PHY_BASE+0x00000110)
++#define ADR_PHY_READ_TBUS (CSR_PHY_BASE+0x000003fc)
++#define ADR_TX_11B_FIL_COEF_00 (CSR_PHY_BASE+0x00001000)
++#define ADR_TX_11B_FIL_COEF_01 (CSR_PHY_BASE+0x00001004)
++#define ADR_TX_11B_FIL_COEF_02 (CSR_PHY_BASE+0x00001008)
++#define ADR_TX_11B_FIL_COEF_03 (CSR_PHY_BASE+0x0000100c)
++#define ADR_TX_11B_FIL_COEF_04 (CSR_PHY_BASE+0x00001010)
++#define ADR_TX_11B_FIL_COEF_05 (CSR_PHY_BASE+0x00001014)
++#define ADR_TX_11B_FIL_COEF_06 (CSR_PHY_BASE+0x00001018)
++#define ADR_TX_11B_FIL_COEF_07 (CSR_PHY_BASE+0x0000101c)
++#define ADR_TX_11B_FIL_COEF_08 (CSR_PHY_BASE+0x00001020)
++#define ADR_TX_11B_FIL_COEF_09 (CSR_PHY_BASE+0x00001024)
++#define ADR_TX_11B_FIL_COEF_10 (CSR_PHY_BASE+0x00001028)
++#define ADR_TX_11B_FIL_COEF_11 (CSR_PHY_BASE+0x0000102c)
++#define ADR_TX_11B_FIL_COEF_12 (CSR_PHY_BASE+0x00001030)
++#define ADR_TX_11B_FIL_COEF_13 (CSR_PHY_BASE+0x00001034)
++#define ADR_TX_11B_FIL_COEF_14 (CSR_PHY_BASE+0x00001038)
++#define ADR_TX_11B_FIL_COEF_15 (CSR_PHY_BASE+0x0000103c)
++#define ADR_TX_11B_FIL_COEF_16 (CSR_PHY_BASE+0x00001040)
++#define ADR_TX_11B_FIL_COEF_17 (CSR_PHY_BASE+0x00001044)
++#define ADR_TX_11B_FIL_COEF_18 (CSR_PHY_BASE+0x00001048)
++#define ADR_TX_11B_FIL_COEF_19 (CSR_PHY_BASE+0x0000104c)
++#define ADR_TX_11B_FIL_COEF_20 (CSR_PHY_BASE+0x00001050)
++#define ADR_TX_11B_FIL_COEF_21 (CSR_PHY_BASE+0x00001054)
++#define ADR_TX_11B_FIL_COEF_22 (CSR_PHY_BASE+0x00001058)
++#define ADR_TX_11B_FIL_COEF_23 (CSR_PHY_BASE+0x0000105c)
++#define ADR_TX_11B_FIL_COEF_24 (CSR_PHY_BASE+0x00001060)
++#define ADR_TX_11B_FIL_COEF_25 (CSR_PHY_BASE+0x00001064)
++#define ADR_TX_11B_FIL_COEF_26 (CSR_PHY_BASE+0x00001068)
++#define ADR_TX_11B_FIL_COEF_27 (CSR_PHY_BASE+0x0000106c)
++#define ADR_TX_11B_FIL_COEF_28 (CSR_PHY_BASE+0x00001070)
++#define ADR_TX_11B_FIL_COEF_29 (CSR_PHY_BASE+0x00001074)
++#define ADR_TX_11B_FIL_COEF_30 (CSR_PHY_BASE+0x00001078)
++#define ADR_TX_11B_FIL_COEF_31 (CSR_PHY_BASE+0x0000107c)
++#define ADR_TX_11B_FIL_COEF_32 (CSR_PHY_BASE+0x00001080)
++#define ADR_TX_11B_FIL_COEF_33 (CSR_PHY_BASE+0x00001084)
++#define ADR_TX_11B_FIL_COEF_34 (CSR_PHY_BASE+0x00001088)
++#define ADR_TX_11B_FIL_COEF_35 (CSR_PHY_BASE+0x0000108c)
++#define ADR_TX_11B_FIL_COEF_36 (CSR_PHY_BASE+0x00001090)
++#define ADR_TX_11B_FIL_COEF_37 (CSR_PHY_BASE+0x00001094)
++#define ADR_TX_11B_FIL_COEF_38 (CSR_PHY_BASE+0x00001098)
++#define ADR_TX_11B_FIL_COEF_39 (CSR_PHY_BASE+0x0000109c)
++#define ADR_TX_11B_FIL_COEF_40 (CSR_PHY_BASE+0x000010a0)
++#define ADR_TX_11B_PLCP (CSR_PHY_BASE+0x000010a4)
++#define ADR_TX_11B_RAMP (CSR_PHY_BASE+0x000010b4)
++#define ADR_TX_11B_EN_CNT_RST_N (CSR_PHY_BASE+0x000010d4)
++#define ADR_TX_11B_EN_CNT (CSR_PHY_BASE+0x000010d8)
++#define ADR_TX_11B_PKT_GEN_CNT (CSR_PHY_BASE+0x00001c00)
++#define ADR_RX_11B_DES_DLY (CSR_PHY_BASE+0x00002000)
++#define ADR_RX_11B_CCA_0 (CSR_PHY_BASE+0x00002004)
++#define ADR_RX_11B_CCA_1 (CSR_PHY_BASE+0x00002008)
++#define ADR_RX_11B_TR_KP_KI_0 (CSR_PHY_BASE+0x0000200c)
++#define ADR_RX_11B_TR_KP_KI_1 (CSR_PHY_BASE+0x00002010)
++#define ADR_RX_11B_CE_CNT_THRESHOLD (CSR_PHY_BASE+0x00002014)
++#define ADR_RX_11B_CE_MU_0 (CSR_PHY_BASE+0x00002018)
++#define ADR_RX_11B_CE_MU_1 (CSR_PHY_BASE+0x0000201c)
++#define ADR_RX_11B_EQ_MU_0 (CSR_PHY_BASE+0x00002020)
++#define ADR_RX_11B_EQ_MU_1 (CSR_PHY_BASE+0x00002024)
++#define ADR_RX_11B_EQ_CR_KP_KI (CSR_PHY_BASE+0x00002028)
++#define ADR_RX_11B_LPF_RATE (CSR_PHY_BASE+0x0000202c)
++#define ADR_RX_11B_CIT_CNT_THRESHOLD (CSR_PHY_BASE+0x00002030)
++#define ADR_RX_11B_EQ_CH_MAIN_TAP (CSR_PHY_BASE+0x00002034)
++#define ADR_RX_11B_SEARCH_CNT_TH (CSR_PHY_BASE+0x0000209c)
++#define ADR_RX_11B_CCA_CONTROL (CSR_PHY_BASE+0x000020a0)
++#define ADR_RX_11B_FREQUENCY_OFFSET (CSR_PHY_BASE+0x000023d4)
++#define ADR_RX_11B_SNR_RSSI (CSR_PHY_BASE+0x000023d8)
++#define ADR_RX_11B_SFD_CRC_CNT (CSR_PHY_BASE+0x000023e4)
++#define ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT (CSR_PHY_BASE+0x000023e8)
++#define ADR_RX_11B_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000023ec)
++#define ADR_RX_11B_SFD_FILED_0 (CSR_PHY_BASE+0x000023f0)
++#define ADR_RX_11B_SFD_FIELD_1 (CSR_PHY_BASE+0x000023f4)
++#define ADR_RX_11B_PKT_STAT_EN (CSR_PHY_BASE+0x000023f8)
++#define ADR_RX_11B_SOFT_RST (CSR_PHY_BASE+0x000023fc)
++#define ADR_TX_11GN_RAMP (CSR_PHY_BASE+0x000030a4)
++#define ADR_TX_11GN_PLCP (CSR_PHY_BASE+0x000030b8)
++#define ADR_TX_11GN_PKT_GEN_CNT (CSR_PHY_BASE+0x00003c00)
++#define ADR_TX_11GN_PLCP_CRC_ERR_CNT (CSR_PHY_BASE+0x00003c08)
++#define ADR_RX_11GN_DES_DLY (CSR_PHY_BASE+0x00004000)
++#define ADR_RX_11GN_TR_0 (CSR_PHY_BASE+0x00004004)
++#define ADR_RX_11GN_TR_1 (CSR_PHY_BASE+0x00004008)
++#define ADR_RX_11GN_TR_2 (CSR_PHY_BASE+0x0000400c)
++#define ADR_RX_11GN_CCA_0 (CSR_PHY_BASE+0x00004010)
++#define ADR_RX_11GN_CCA_1 (CSR_PHY_BASE+0x00004014)
++#define ADR_RX_11GN_CCA_2 (CSR_PHY_BASE+0x00004018)
++#define ADR_RX_11GN_CCA_FFT_SCALE (CSR_PHY_BASE+0x0000401c)
++#define ADR_RX_11GN_SOFT_DEMAP_0 (CSR_PHY_BASE+0x00004020)
++#define ADR_RX_11GN_SOFT_DEMAP_1 (CSR_PHY_BASE+0x00004024)
++#define ADR_RX_11GN_SOFT_DEMAP_2 (CSR_PHY_BASE+0x00004028)
++#define ADR_RX_11GN_SOFT_DEMAP_3 (CSR_PHY_BASE+0x0000402c)
++#define ADR_RX_11GN_SOFT_DEMAP_4 (CSR_PHY_BASE+0x00004030)
++#define ADR_RX_11GN_SOFT_DEMAP_5 (CSR_PHY_BASE+0x00004034)
++#define ADR_RX_11GN_SYM_BOUND_0 (CSR_PHY_BASE+0x00004038)
++#define ADR_RX_11GN_SYM_BOUND_1 (CSR_PHY_BASE+0x0000409c)
++#define ADR_RX_11GN_CCA_PWR (CSR_PHY_BASE+0x000040c0)
++#define ADR_RX_11GN_CCA_CNT (CSR_PHY_BASE+0x000040c4)
++#define ADR_RX_11GN_CCA_ATCOR_RE_CHECK (CSR_PHY_BASE+0x000040c8)
++#define ADR_RX_11GN_VTB_TB (CSR_PHY_BASE+0x00004130)
++#define ADR_RX_11GN_ERR_UPDATE (CSR_PHY_BASE+0x00004164)
++#define ADR_RX_11GN_SHORT_GI (CSR_PHY_BASE+0x00004180)
++#define ADR_RX_11GN_CHANNEL_UPDATE (CSR_PHY_BASE+0x00004188)
++#define ADR_RX_11GN_PKT_FORMAT_0 (CSR_PHY_BASE+0x00004190)
++#define ADR_RX_11GN_PKT_FORMAT_1 (CSR_PHY_BASE+0x00004194)
++#define ADR_RX_11GN_TX_TIME (CSR_PHY_BASE+0x00004380)
++#define ADR_RX_11GN_STBC_TR_KP_KI (CSR_PHY_BASE+0x00004384)
++#define ADR_RX_11GN_BIST_0 (CSR_PHY_BASE+0x00004388)
++#define ADR_RX_11GN_BIST_1 (CSR_PHY_BASE+0x0000438c)
++#define ADR_RX_11GN_BIST_2 (CSR_PHY_BASE+0x000043c0)
++#define ADR_RX_11GN_BIST_3 (CSR_PHY_BASE+0x000043c4)
++#define ADR_RX_11GN_BIST_4 (CSR_PHY_BASE+0x000043c8)
++#define ADR_RX_11GN_BIST_5 (CSR_PHY_BASE+0x000043cc)
++#define ADR_RX_11GN_SPECTRUM_ANALYZER (CSR_PHY_BASE+0x000043d4)
++#define ADR_RX_11GN_READ_0 (CSR_PHY_BASE+0x000043d8)
++#define ADR_RX_11GN_FREQ_OFFSET (CSR_PHY_BASE+0x000043dc)
++#define ADR_RX_11GN_SIGNAL_FIELD_0 (CSR_PHY_BASE+0x000043e0)
++#define ADR_RX_11GN_SIGNAL_FIELD_1 (CSR_PHY_BASE+0x000043e4)
++#define ADR_RX_11GN_PKT_ERR_CNT (CSR_PHY_BASE+0x000043e8)
++#define ADR_RX_11GN_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000043ec)
++#define ADR_RX_11GN_SERVICE_LENGTH_FIELD (CSR_PHY_BASE+0x000043f0)
++#define ADR_RX_11GN_RATE (CSR_PHY_BASE+0x000043f4)
++#define ADR_RX_11GN_STAT_EN (CSR_PHY_BASE+0x000043f8)
++#define ADR_RX_11GN_SOFT_RST (CSR_PHY_BASE+0x000043fc)
++#define ADR_RF_CONTROL_0 (CSR_PHY_BASE+0x00007000)
++#define ADR_RF_CONTROL_1 (CSR_PHY_BASE+0x00007004)
++#define ADR_TX_IQ_CONTROL_0 (CSR_PHY_BASE+0x00007040)
++#define ADR_TX_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007044)
++#define ADR_TX_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007048)
++#define ADR_TX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x0000704c)
++#define ADR_RX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x00007050)
++#define ADR_RX_OBSERVATION_CIRCUIT_0 (CSR_PHY_BASE+0x00007058)
++#define ADR_RX_OBSERVATION_CIRCUIT_1 (CSR_PHY_BASE+0x0000705c)
++#define ADR_RX_OBSERVATION_CIRCUIT_2 (CSR_PHY_BASE+0x00007060)
++#define ADR_RX_OBSERVATION_CIRCUIT_3 (CSR_PHY_BASE+0x00007064)
++#define ADR_RF_IQ_CONTROL_0 (CSR_PHY_BASE+0x0000706c)
++#define ADR_RF_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007070)
++#define ADR_RF_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007074)
++#define ADR_RF_IQ_CONTROL_3 (CSR_PHY_BASE+0x00007078)
++#define ADR_DPD_CONTROL (CSR_PHY_BASE+0x0000711c)
++#define ADR_DPD_GAIN_TABLE_0 (CSR_PHY_BASE+0x00007120)
++#define ADR_DPD_GAIN_TABLE_1 (CSR_PHY_BASE+0x00007124)
++#define ADR_DPD_GAIN_TABLE_2 (CSR_PHY_BASE+0x00007128)
++#define ADR_DPD_GAIN_TABLE_3 (CSR_PHY_BASE+0x00007130)
++#define ADR_DPD_GAIN_TABLE_4 (CSR_PHY_BASE+0x00007134)
++#define ADR_DPD_GAIN_TABLE_5 (CSR_PHY_BASE+0x00007138)
++#define ADR_DPD_GAIN_TABLE_6 (CSR_PHY_BASE+0x0000713c)
++#define ADR_DPD_GAIN_TABLE_7 (CSR_PHY_BASE+0x00007140)
++#define ADR_DPD_GAIN_TABLE_8 (CSR_PHY_BASE+0x00007144)
++#define ADR_DPD_GAIN_TABLE_9 (CSR_PHY_BASE+0x00007148)
++#define ADR_DPD_GAIN_TABLE_A (CSR_PHY_BASE+0x0000714c)
++#define ADR_DPD_GAIN_TABLE_B (CSR_PHY_BASE+0x00007150)
++#define ADR_DPD_GAIN_TABLE_C (CSR_PHY_BASE+0x00007154)
++#define ADR_DPD_PH_TABLE_0 (CSR_PHY_BASE+0x00007170)
++#define ADR_DPD_PH_TABLE_1 (CSR_PHY_BASE+0x00007174)
++#define ADR_DPD_PH_TABLE_2 (CSR_PHY_BASE+0x00007178)
++#define ADR_DPD_PH_TABLE_3 (CSR_PHY_BASE+0x00007180)
++#define ADR_DPD_PH_TABLE_4 (CSR_PHY_BASE+0x00007184)
++#define ADR_DPD_PH_TABLE_5 (CSR_PHY_BASE+0x00007188)
++#define ADR_DPD_PH_TABLE_6 (CSR_PHY_BASE+0x0000718c)
++#define ADR_DPD_PH_TABLE_7 (CSR_PHY_BASE+0x00007190)
++#define ADR_DPD_PH_TABLE_8 (CSR_PHY_BASE+0x00007194)
++#define ADR_DPD_PH_TABLE_9 (CSR_PHY_BASE+0x00007198)
++#define ADR_DPD_PH_TABLE_A (CSR_PHY_BASE+0x0000719c)
++#define ADR_DPD_PH_TABLE_B (CSR_PHY_BASE+0x000071a0)
++#define ADR_DPD_PH_TABLE_C (CSR_PHY_BASE+0x000071a4)
++#define ADR_DPD_GAIN_ESTIMATION_0 (CSR_PHY_BASE+0x000071b0)
++#define ADR_DPD_GAIN_ESTIMATION_1 (CSR_PHY_BASE+0x000071b4)
++#define ADR_DPD_GAIN_ESTIMATION_2 (CSR_PHY_BASE+0x000071b8)
++#define ADR_TX_GAIN_FACTOR (CSR_PHY_BASE+0x000071bc)
++#define ADR_HARD_WIRE_PIN_REGISTER (CSR_RF_BASE+0x00000000)
++#define ADR_MANUAL_ENABLE_REGISTER (CSR_RF_BASE+0x00000004)
++#define ADR_LDO_REGISTER (CSR_RF_BASE+0x00000008)
++#define ADR_ABB_REGISTER_1 (CSR_RF_BASE+0x0000000c)
++#define ADR_ABB_REGISTER_2 (CSR_RF_BASE+0x00000010)
++#define ADR_TX_FE_REGISTER (CSR_RF_BASE+0x00000014)
++#define ADR_RX_FE_REGISTER_1 (CSR_RF_BASE+0x00000018)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_1 (CSR_RF_BASE+0x0000001c)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_2 (CSR_RF_BASE+0x00000020)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_3 (CSR_RF_BASE+0x00000024)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_4 (CSR_RF_BASE+0x00000028)
++#define ADR_RX_TX_FSM_REGISTER (CSR_RF_BASE+0x0000002c)
++#define ADR_RX_ADC_REGISTER (CSR_RF_BASE+0x00000030)
++#define ADR_TX_DAC_REGISTER (CSR_RF_BASE+0x00000034)
++#define ADR_SX_ENABLE_REGISTER (CSR_RF_BASE+0x00000038)
++#define ADR_SYN_REGISTER_1 (CSR_RF_BASE+0x0000003c)
++#define ADR_SYN_REGISTER_2 (CSR_RF_BASE+0x00000040)
++#define ADR_SYN_PFD_CHP (CSR_RF_BASE+0x00000044)
++#define ADR_SYN_VCO_LOBF (CSR_RF_BASE+0x00000048)
++#define ADR_SYN_DIV_SDM_XOSC (CSR_RF_BASE+0x0000004c)
++#define ADR_SYN_KVCO_XO_FINE_TUNE_CBANK (CSR_RF_BASE+0x00000050)
++#define ADR_SYN_LCK_VT (CSR_RF_BASE+0x00000054)
++#define ADR_DPLL_VCO_REGISTER (CSR_RF_BASE+0x00000058)
++#define ADR_DPLL_CP_PFD_REGISTER (CSR_RF_BASE+0x0000005c)
++#define ADR_DPLL_DIVIDER_REGISTER (CSR_RF_BASE+0x00000060)
++#define ADR_DCOC_IDAC_REGISTER1 (CSR_RF_BASE+0x00000064)
++#define ADR_DCOC_IDAC_REGISTER2 (CSR_RF_BASE+0x00000068)
++#define ADR_DCOC_IDAC_REGISTER3 (CSR_RF_BASE+0x0000006c)
++#define ADR_DCOC_IDAC_REGISTER4 (CSR_RF_BASE+0x00000070)
++#define ADR_DCOC_IDAC_REGISTER5 (CSR_RF_BASE+0x00000074)
++#define ADR_DCOC_IDAC_REGISTER6 (CSR_RF_BASE+0x00000078)
++#define ADR_DCOC_IDAC_REGISTER7 (CSR_RF_BASE+0x0000007c)
++#define ADR_DCOC_IDAC_REGISTER8 (CSR_RF_BASE+0x00000080)
++#define ADR_RCAL_REGISTER (CSR_RF_BASE+0x00000084)
++#define ADR_SX_LCK_BIN_REGISTERS_I (CSR_RF_BASE+0x00000088)
++#define ADR_TRX_DUMMY_REGISTER (CSR_RF_BASE+0x0000008c)
++#define ADR_SX_DUMMY_REGISTER (CSR_RF_BASE+0x00000090)
++#define ADR_READ_ONLY_FLAGS_1 (CSR_RF_BASE+0x00000094)
++#define ADR_READ_ONLY_FLAGS_2 (CSR_RF_BASE+0x00000098)
++#define ADR_DPLL_FB_DIVIDER_REGISTERS_I (CSR_RF_BASE+0x0000009c)
++#define ADR_DPLL_FB_DIVIDER_REGISTERS_II (CSR_RF_BASE+0x000000a0)
++#define ADR_SX_LCK_BIN_REGISTERS_II (CSR_RF_BASE+0x000000a4)
++#define ADR_RC_OSC_32K_CAL_REGISTERS (CSR_RF_BASE+0x000000a8)
++#define ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER (CSR_RF_BASE+0x000000ac)
++#define ADR_MMU_CTRL (MMU_REG_BASE+0x00000000)
++#define ADR_HS_CTRL (MMU_REG_BASE+0x00000004)
++#define ADR_CPU_POR0_7 (MMU_REG_BASE+0x00000008)
++#define ADR_CPU_POR8_F (MMU_REG_BASE+0x0000000c)
++#define ADR_REG_LEN_CTRL (MMU_REG_BASE+0x00000010)
++#define ADR_DMN_READ_BYPASS (MMU_REG_BASE+0x00000014)
++#define ADR_ALC_RLS_ABORT (MMU_REG_BASE+0x00000018)
++#define ADR_DEBUG_CTL (MMU_REG_BASE+0x00000020)
++#define ADR_DEBUG_OUT (MMU_REG_BASE+0x00000024)
++#define ADR_MMU_STATUS (MMU_REG_BASE+0x00000028)
++#define ADR_DMN_STATUS (MMU_REG_BASE+0x0000002c)
++#define ADR_TAG_STATUS (MMU_REG_BASE+0x00000030)
++#define ADR_DMN_MCU_STATUS (MMU_REG_BASE+0x00000034)
++#define ADR_MB_IDTBL_0_STATUS (MMU_REG_BASE+0x00000040)
++#define ADR_MB_IDTBL_1_STATUS (MMU_REG_BASE+0x00000044)
++#define ADR_MB_IDTBL_2_STATUS (MMU_REG_BASE+0x00000048)
++#define ADR_MB_IDTBL_3_STATUS (MMU_REG_BASE+0x0000004c)
++#define ADR_PKT_IDTBL_0_STATUS (MMU_REG_BASE+0x00000050)
++#define ADR_PKT_IDTBL_1_STATUS (MMU_REG_BASE+0x00000054)
++#define ADR_PKT_IDTBL_2_STATUS (MMU_REG_BASE+0x00000058)
++#define ADR_PKT_IDTBL_3_STATUS (MMU_REG_BASE+0x0000005c)
++#define ADR_DMN_IDTBL_0_STATUS (MMU_REG_BASE+0x00000060)
++#define ADR_DMN_IDTBL_1_STATUS (MMU_REG_BASE+0x00000064)
++#define ADR_DMN_IDTBL_2_STATUS (MMU_REG_BASE+0x00000068)
++#define ADR_DMN_IDTBL_3_STATUS (MMU_REG_BASE+0x0000006c)
++#define ADR_MB_NEQID_0_STATUS (MMU_REG_BASE+0x00000070)
++#define ADR_MB_NEQID_1_STATUS (MMU_REG_BASE+0x00000074)
++#define ADR_MB_NEQID_2_STATUS (MMU_REG_BASE+0x00000078)
++#define ADR_MB_NEQID_3_STATUS (MMU_REG_BASE+0x0000007c)
++#define ADR_PKT_NEQID_0_STATUS (MMU_REG_BASE+0x00000080)
++#define ADR_PKT_NEQID_1_STATUS (MMU_REG_BASE+0x00000084)
++#define ADR_PKT_NEQID_2_STATUS (MMU_REG_BASE+0x00000088)
++#define ADR_PKT_NEQID_3_STATUS (MMU_REG_BASE+0x0000008c)
++#define ADR_ALC_NOCHG_ID_STATUS (MMU_REG_BASE+0x00000090)
++#define ADR_TAG_SRAM0_F_STATUS_0 (MMU_REG_BASE+0x000000a0)
++#define ADR_TAG_SRAM0_F_STATUS_1 (MMU_REG_BASE+0x000000a4)
++#define ADR_TAG_SRAM0_F_STATUS_2 (MMU_REG_BASE+0x000000a8)
++#define ADR_TAG_SRAM0_F_STATUS_3 (MMU_REG_BASE+0x000000ac)
++#define ADR_TAG_SRAM0_F_STATUS_4 (MMU_REG_BASE+0x000000b0)
++#define ADR_TAG_SRAM0_F_STATUS_5 (MMU_REG_BASE+0x000000b4)
++#define ADR_TAG_SRAM0_F_STATUS_6 (MMU_REG_BASE+0x000000b8)
++#define ADR_TAG_SRAM0_F_STATUS_7 (MMU_REG_BASE+0x000000bc)
++#define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0)
++#define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1)
++#define GET_MCU_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2)
++#define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3)
++#define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4)
++#define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5)
++#define GET_DMA_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000040 ) >> 6)
++#define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7)
++#define GET_I2C_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000100 ) >> 8)
++#define GET_INT_CTL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000200 ) >> 9)
++#define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10)
++#define GET_GPIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000800 ) >> 11)
++#define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12)
++#define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13)
++#define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14)
++#define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15)
++#define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16)
++#define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17)
++#define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18)
++#define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19)
++#define GET_RF_BB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20)
++#define GET_SYS_ALL_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21)
++#define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22)
++#define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23)
++#define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0)
++#define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16)
++#define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17)
++#define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18)
++#define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0)
++#define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0)
++#define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0)
++#define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0)
++#define GET_CK_SEL_1_0 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000003 ) >> 0)
++#define GET_CK_SEL_2 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000004 ) >> 2)
++#define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
++#define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MCU_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2)
++#define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
++#define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
++#define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
++#define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
++#define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
++#define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8)
++#define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
++#define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_GPIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
++#define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
++#define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
++#define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
++#define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16)
++#define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17)
++#define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18)
++#define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19)
++#define GET_BIST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20)
++#define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23)
++#define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_MCU_DBG_SEL (((REG32(ADR_MCU_DBG_SEL)) & 0x0000003f ) >> 0)
++#define GET_MCU_STOP_NOGRANT (((REG32(ADR_MCU_DBG_SEL)) & 0x00000100 ) >> 8)
++#define GET_MCU_STOP_ANYTIME (((REG32(ADR_MCU_DBG_SEL)) & 0x00000200 ) >> 9)
++#define GET_MCU_DBG_DATA (((REG32(ADR_MCU_DBG_DATA)) & 0xffffffff ) >> 0)
++#define GET_AHB_SW_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000001 ) >> 0)
++#define GET_AHB_ERR_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000002 ) >> 1)
++#define GET_REG_AHB_DEBUG_MX (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000030 ) >> 4)
++#define GET_REG_PKT_W_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000100 ) >> 8)
++#define GET_REG_PKT_R_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000200 ) >> 9)
++#define GET_IQ_SRAM_SEL_0 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00001000 ) >> 12)
++#define GET_IQ_SRAM_SEL_1 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00002000 ) >> 13)
++#define GET_IQ_SRAM_SEL_2 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00004000 ) >> 14)
++#define GET_AHB_STATUS (((REG32(ADR_AHB_BRG_STATUS)) & 0xffff0000 ) >> 16)
++#define GET_PARALLEL_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000001 ) >> 0)
++#define GET_MBRUN (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000010 ) >> 4)
++#define GET_SHIFT_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000100 ) >> 8)
++#define GET_MODE_REG_SI (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000200 ) >> 9)
++#define GET_SIMULATION_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000400 ) >> 10)
++#define GET_DBIST_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000800 ) >> 11)
++#define GET_MODE_REG_IN (((REG32(ADR_BIST_MODE_REG_IN)) & 0x001fffff ) >> 0)
++#define GET_MODE_REG_OUT_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x001fffff ) >> 0)
++#define GET_MODE_REG_SO_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x80000000 ) >> 31)
++#define GET_MONITOR_BUS_MCU_31_0 (((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0xffffffff ) >> 0)
++#define GET_MONITOR_BUS_MCU_33_32 (((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0x00000003 ) >> 0)
++#define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0)
++#define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31)
++#define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0)
++#define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0)
++#define GET_DATA_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000010 ) >> 4)
++#define GET_AHB_ILL_ADDR (((REG32(ADR_AHB_ILL_ADDR)) & 0xffffffff ) >> 0)
++#define GET_AHB_FEN_ADDR (((REG32(ADR_AHB_FEN_ADDR)) & 0xffffffff ) >> 0)
++#define GET_ILL_ADDR_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000001 ) >> 0)
++#define GET_FENCE_HIT_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000002 ) >> 1)
++#define GET_ILL_ADDR_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000010 ) >> 4)
++#define GET_FENCE_HIT_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000020 ) >> 5)
++#define GET_PWM_INI_VALUE_P_A (((REG32(ADR_PWM_A)) & 0x000000ff ) >> 0)
++#define GET_PWM_INI_VALUE_N_A (((REG32(ADR_PWM_A)) & 0x0000ff00 ) >> 8)
++#define GET_PWM_POST_SCALER_A (((REG32(ADR_PWM_A)) & 0x000f0000 ) >> 16)
++#define GET_PWM_ALWAYSON_A (((REG32(ADR_PWM_A)) & 0x20000000 ) >> 29)
++#define GET_PWM_INVERT_A (((REG32(ADR_PWM_A)) & 0x40000000 ) >> 30)
++#define GET_PWM_ENABLE_A (((REG32(ADR_PWM_A)) & 0x80000000 ) >> 31)
++#define GET_PWM_INI_VALUE_P_B (((REG32(ADR_PWM_B)) & 0x000000ff ) >> 0)
++#define GET_PWM_INI_VALUE_N_B (((REG32(ADR_PWM_B)) & 0x0000ff00 ) >> 8)
++#define GET_PWM_POST_SCALER_B (((REG32(ADR_PWM_B)) & 0x000f0000 ) >> 16)
++#define GET_PWM_ALWAYSON_B (((REG32(ADR_PWM_B)) & 0x20000000 ) >> 29)
++#define GET_PWM_INVERT_B (((REG32(ADR_PWM_B)) & 0x40000000 ) >> 30)
++#define GET_PWM_ENABLE_B (((REG32(ADR_PWM_B)) & 0x80000000 ) >> 31)
++#define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0)
++#define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0)
++#define GET_PRESCALER_USTIMER (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0)
++#define GET_MODE_REG_IN_MMU (((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0x0000ffff ) >> 0)
++#define GET_MODE_REG_OUT_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x0000ffff ) >> 0)
++#define GET_MODE_REG_SO_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x80000000 ) >> 31)
++#define GET_MONITOR_BUS_MMU (((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0x0007ffff ) >> 0)
++#define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0)
++#define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1)
++#define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2)
++#define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3)
++#define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4)
++#define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5)
++#define GET_WDT_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0)
++#define GET_SD_HOST_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1)
++#define GET_ALLOW_SD_RESET (((REG32(ADR_SD_INIT_CFG)) & 0x00000001 ) >> 0)
++#define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0)
++#define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1)
++#define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0)
++#define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x00020000 ) >> 17)
++#define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31)
++#define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0)
++#define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x00020000 ) >> 17)
++#define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31)
++#define GET_XLNA_EN_O_OE (((REG32(ADR_PAD6)) & 0x00000001 ) >> 0)
++#define GET_XLNA_EN_O_PE (((REG32(ADR_PAD6)) & 0x00000002 ) >> 1)
++#define GET_PAD6_IE (((REG32(ADR_PAD6)) & 0x00000008 ) >> 3)
++#define GET_PAD6_SEL_I (((REG32(ADR_PAD6)) & 0x00000030 ) >> 4)
++#define GET_PAD6_OD (((REG32(ADR_PAD6)) & 0x00000100 ) >> 8)
++#define GET_PAD6_SEL_O (((REG32(ADR_PAD6)) & 0x00001000 ) >> 12)
++#define GET_XLNA_EN_O_C (((REG32(ADR_PAD6)) & 0x10000000 ) >> 28)
++#define GET_WIFI_TX_SW_O_OE (((REG32(ADR_PAD7)) & 0x00000001 ) >> 0)
++#define GET_WIFI_TX_SW_O_PE (((REG32(ADR_PAD7)) & 0x00000002 ) >> 1)
++#define GET_PAD7_IE (((REG32(ADR_PAD7)) & 0x00000008 ) >> 3)
++#define GET_PAD7_SEL_I (((REG32(ADR_PAD7)) & 0x00000030 ) >> 4)
++#define GET_PAD7_OD (((REG32(ADR_PAD7)) & 0x00000100 ) >> 8)
++#define GET_PAD7_SEL_O (((REG32(ADR_PAD7)) & 0x00001000 ) >> 12)
++#define GET_WIFI_TX_SW_O_C (((REG32(ADR_PAD7)) & 0x10000000 ) >> 28)
++#define GET_WIFI_RX_SW_O_OE (((REG32(ADR_PAD8)) & 0x00000001 ) >> 0)
++#define GET_WIFI_RX_SW_O_PE (((REG32(ADR_PAD8)) & 0x00000002 ) >> 1)
++#define GET_PAD8_IE (((REG32(ADR_PAD8)) & 0x00000008 ) >> 3)
++#define GET_PAD8_SEL_I (((REG32(ADR_PAD8)) & 0x00000030 ) >> 4)
++#define GET_PAD8_OD (((REG32(ADR_PAD8)) & 0x00000100 ) >> 8)
++#define GET_WIFI_RX_SW_O_C (((REG32(ADR_PAD8)) & 0x10000000 ) >> 28)
++#define GET_BT_SW_O_OE (((REG32(ADR_PAD9)) & 0x00000001 ) >> 0)
++#define GET_BT_SW_O_PE (((REG32(ADR_PAD9)) & 0x00000002 ) >> 1)
++#define GET_PAD9_IE (((REG32(ADR_PAD9)) & 0x00000008 ) >> 3)
++#define GET_PAD9_SEL_I (((REG32(ADR_PAD9)) & 0x00000030 ) >> 4)
++#define GET_PAD9_OD (((REG32(ADR_PAD9)) & 0x00000100 ) >> 8)
++#define GET_PAD9_SEL_O (((REG32(ADR_PAD9)) & 0x00001000 ) >> 12)
++#define GET_BT_SW_O_C (((REG32(ADR_PAD9)) & 0x10000000 ) >> 28)
++#define GET_XPA_EN_O_OE (((REG32(ADR_PAD11)) & 0x00000001 ) >> 0)
++#define GET_XPA_EN_O_PE (((REG32(ADR_PAD11)) & 0x00000002 ) >> 1)
++#define GET_PAD11_IE (((REG32(ADR_PAD11)) & 0x00000008 ) >> 3)
++#define GET_PAD11_SEL_I (((REG32(ADR_PAD11)) & 0x00000030 ) >> 4)
++#define GET_PAD11_OD (((REG32(ADR_PAD11)) & 0x00000100 ) >> 8)
++#define GET_PAD11_SEL_O (((REG32(ADR_PAD11)) & 0x00001000 ) >> 12)
++#define GET_XPA_EN_O_C (((REG32(ADR_PAD11)) & 0x10000000 ) >> 28)
++#define GET_PAD15_OE (((REG32(ADR_PAD15)) & 0x00000001 ) >> 0)
++#define GET_PAD15_PE (((REG32(ADR_PAD15)) & 0x00000002 ) >> 1)
++#define GET_PAD15_DS (((REG32(ADR_PAD15)) & 0x00000004 ) >> 2)
++#define GET_PAD15_IE (((REG32(ADR_PAD15)) & 0x00000008 ) >> 3)
++#define GET_PAD15_SEL_I (((REG32(ADR_PAD15)) & 0x00000030 ) >> 4)
++#define GET_PAD15_OD (((REG32(ADR_PAD15)) & 0x00000100 ) >> 8)
++#define GET_PAD15_SEL_O (((REG32(ADR_PAD15)) & 0x00001000 ) >> 12)
++#define GET_TEST_1_ID (((REG32(ADR_PAD15)) & 0x10000000 ) >> 28)
++#define GET_PAD16_OE (((REG32(ADR_PAD16)) & 0x00000001 ) >> 0)
++#define GET_PAD16_PE (((REG32(ADR_PAD16)) & 0x00000002 ) >> 1)
++#define GET_PAD16_DS (((REG32(ADR_PAD16)) & 0x00000004 ) >> 2)
++#define GET_PAD16_IE (((REG32(ADR_PAD16)) & 0x00000008 ) >> 3)
++#define GET_PAD16_SEL_I (((REG32(ADR_PAD16)) & 0x00000030 ) >> 4)
++#define GET_PAD16_OD (((REG32(ADR_PAD16)) & 0x00000100 ) >> 8)
++#define GET_PAD16_SEL_O (((REG32(ADR_PAD16)) & 0x00001000 ) >> 12)
++#define GET_TEST_2_ID (((REG32(ADR_PAD16)) & 0x10000000 ) >> 28)
++#define GET_PAD17_OE (((REG32(ADR_PAD17)) & 0x00000001 ) >> 0)
++#define GET_PAD17_PE (((REG32(ADR_PAD17)) & 0x00000002 ) >> 1)
++#define GET_PAD17_DS (((REG32(ADR_PAD17)) & 0x00000004 ) >> 2)
++#define GET_PAD17_IE (((REG32(ADR_PAD17)) & 0x00000008 ) >> 3)
++#define GET_PAD17_SEL_I (((REG32(ADR_PAD17)) & 0x00000030 ) >> 4)
++#define GET_PAD17_OD (((REG32(ADR_PAD17)) & 0x00000100 ) >> 8)
++#define GET_PAD17_SEL_O (((REG32(ADR_PAD17)) & 0x00001000 ) >> 12)
++#define GET_TEST_3_ID (((REG32(ADR_PAD17)) & 0x10000000 ) >> 28)
++#define GET_PAD18_OE (((REG32(ADR_PAD18)) & 0x00000001 ) >> 0)
++#define GET_PAD18_PE (((REG32(ADR_PAD18)) & 0x00000002 ) >> 1)
++#define GET_PAD18_DS (((REG32(ADR_PAD18)) & 0x00000004 ) >> 2)
++#define GET_PAD18_IE (((REG32(ADR_PAD18)) & 0x00000008 ) >> 3)
++#define GET_PAD18_SEL_I (((REG32(ADR_PAD18)) & 0x00000030 ) >> 4)
++#define GET_PAD18_OD (((REG32(ADR_PAD18)) & 0x00000100 ) >> 8)
++#define GET_PAD18_SEL_O (((REG32(ADR_PAD18)) & 0x00003000 ) >> 12)
++#define GET_TEST_4_ID (((REG32(ADR_PAD18)) & 0x10000000 ) >> 28)
++#define GET_PAD19_OE (((REG32(ADR_PAD19)) & 0x00000001 ) >> 0)
++#define GET_PAD19_PE (((REG32(ADR_PAD19)) & 0x00000002 ) >> 1)
++#define GET_PAD19_DS (((REG32(ADR_PAD19)) & 0x00000004 ) >> 2)
++#define GET_PAD19_IE (((REG32(ADR_PAD19)) & 0x00000008 ) >> 3)
++#define GET_PAD19_SEL_I (((REG32(ADR_PAD19)) & 0x00000030 ) >> 4)
++#define GET_PAD19_OD (((REG32(ADR_PAD19)) & 0x00000100 ) >> 8)
++#define GET_PAD19_SEL_O (((REG32(ADR_PAD19)) & 0x00007000 ) >> 12)
++#define GET_SHORT_TO_20_ID (((REG32(ADR_PAD19)) & 0x10000000 ) >> 28)
++#define GET_PAD20_OE (((REG32(ADR_PAD20)) & 0x00000001 ) >> 0)
++#define GET_PAD20_PE (((REG32(ADR_PAD20)) & 0x00000002 ) >> 1)
++#define GET_PAD20_DS (((REG32(ADR_PAD20)) & 0x00000004 ) >> 2)
++#define GET_PAD20_IE (((REG32(ADR_PAD20)) & 0x00000008 ) >> 3)
++#define GET_PAD20_SEL_I (((REG32(ADR_PAD20)) & 0x000000f0 ) >> 4)
++#define GET_PAD20_OD (((REG32(ADR_PAD20)) & 0x00000100 ) >> 8)
++#define GET_PAD20_SEL_O (((REG32(ADR_PAD20)) & 0x00003000 ) >> 12)
++#define GET_STRAP0 (((REG32(ADR_PAD20)) & 0x08000000 ) >> 27)
++#define GET_GPIO_TEST_1_ID (((REG32(ADR_PAD20)) & 0x10000000 ) >> 28)
++#define GET_PAD21_OE (((REG32(ADR_PAD21)) & 0x00000001 ) >> 0)
++#define GET_PAD21_PE (((REG32(ADR_PAD21)) & 0x00000002 ) >> 1)
++#define GET_PAD21_DS (((REG32(ADR_PAD21)) & 0x00000004 ) >> 2)
++#define GET_PAD21_IE (((REG32(ADR_PAD21)) & 0x00000008 ) >> 3)
++#define GET_PAD21_SEL_I (((REG32(ADR_PAD21)) & 0x00000070 ) >> 4)
++#define GET_PAD21_OD (((REG32(ADR_PAD21)) & 0x00000100 ) >> 8)
++#define GET_PAD21_SEL_O (((REG32(ADR_PAD21)) & 0x00003000 ) >> 12)
++#define GET_STRAP3 (((REG32(ADR_PAD21)) & 0x08000000 ) >> 27)
++#define GET_GPIO_TEST_2_ID (((REG32(ADR_PAD21)) & 0x10000000 ) >> 28)
++#define GET_PAD22_OE (((REG32(ADR_PAD22)) & 0x00000001 ) >> 0)
++#define GET_PAD22_PE (((REG32(ADR_PAD22)) & 0x00000002 ) >> 1)
++#define GET_PAD22_DS (((REG32(ADR_PAD22)) & 0x00000004 ) >> 2)
++#define GET_PAD22_IE (((REG32(ADR_PAD22)) & 0x00000008 ) >> 3)
++#define GET_PAD22_SEL_I (((REG32(ADR_PAD22)) & 0x00000070 ) >> 4)
++#define GET_PAD22_OD (((REG32(ADR_PAD22)) & 0x00000100 ) >> 8)
++#define GET_PAD22_SEL_O (((REG32(ADR_PAD22)) & 0x00007000 ) >> 12)
++#define GET_PAD22_SEL_OE (((REG32(ADR_PAD22)) & 0x00100000 ) >> 20)
++#define GET_GPIO_TEST_3_ID (((REG32(ADR_PAD22)) & 0x10000000 ) >> 28)
++#define GET_PAD24_OE (((REG32(ADR_PAD24)) & 0x00000001 ) >> 0)
++#define GET_PAD24_PE (((REG32(ADR_PAD24)) & 0x00000002 ) >> 1)
++#define GET_PAD24_DS (((REG32(ADR_PAD24)) & 0x00000004 ) >> 2)
++#define GET_PAD24_IE (((REG32(ADR_PAD24)) & 0x00000008 ) >> 3)
++#define GET_PAD24_SEL_I (((REG32(ADR_PAD24)) & 0x00000030 ) >> 4)
++#define GET_PAD24_OD (((REG32(ADR_PAD24)) & 0x00000100 ) >> 8)
++#define GET_PAD24_SEL_O (((REG32(ADR_PAD24)) & 0x00007000 ) >> 12)
++#define GET_GPIO_TEST_4_ID (((REG32(ADR_PAD24)) & 0x10000000 ) >> 28)
++#define GET_PAD25_OE (((REG32(ADR_PAD25)) & 0x00000001 ) >> 0)
++#define GET_PAD25_PE (((REG32(ADR_PAD25)) & 0x00000002 ) >> 1)
++#define GET_PAD25_DS (((REG32(ADR_PAD25)) & 0x00000004 ) >> 2)
++#define GET_PAD25_IE (((REG32(ADR_PAD25)) & 0x00000008 ) >> 3)
++#define GET_PAD25_SEL_I (((REG32(ADR_PAD25)) & 0x00000070 ) >> 4)
++#define GET_PAD25_OD (((REG32(ADR_PAD25)) & 0x00000100 ) >> 8)
++#define GET_PAD25_SEL_O (((REG32(ADR_PAD25)) & 0x00007000 ) >> 12)
++#define GET_PAD25_SEL_OE (((REG32(ADR_PAD25)) & 0x00100000 ) >> 20)
++#define GET_STRAP1 (((REG32(ADR_PAD25)) & 0x08000000 ) >> 27)
++#define GET_GPIO_1_ID (((REG32(ADR_PAD25)) & 0x10000000 ) >> 28)
++#define GET_PAD27_OE (((REG32(ADR_PAD27)) & 0x00000001 ) >> 0)
++#define GET_PAD27_PE (((REG32(ADR_PAD27)) & 0x00000002 ) >> 1)
++#define GET_PAD27_DS (((REG32(ADR_PAD27)) & 0x00000004 ) >> 2)
++#define GET_PAD27_IE (((REG32(ADR_PAD27)) & 0x00000008 ) >> 3)
++#define GET_PAD27_SEL_I (((REG32(ADR_PAD27)) & 0x00000070 ) >> 4)
++#define GET_PAD27_OD (((REG32(ADR_PAD27)) & 0x00000100 ) >> 8)
++#define GET_PAD27_SEL_O (((REG32(ADR_PAD27)) & 0x00007000 ) >> 12)
++#define GET_GPIO_2_ID (((REG32(ADR_PAD27)) & 0x10000000 ) >> 28)
++#define GET_PAD28_OE (((REG32(ADR_PAD28)) & 0x00000001 ) >> 0)
++#define GET_PAD28_PE (((REG32(ADR_PAD28)) & 0x00000002 ) >> 1)
++#define GET_PAD28_DS (((REG32(ADR_PAD28)) & 0x00000004 ) >> 2)
++#define GET_PAD28_IE (((REG32(ADR_PAD28)) & 0x00000008 ) >> 3)
++#define GET_PAD28_SEL_I (((REG32(ADR_PAD28)) & 0x00000070 ) >> 4)
++#define GET_PAD28_OD (((REG32(ADR_PAD28)) & 0x00000100 ) >> 8)
++#define GET_PAD28_SEL_O (((REG32(ADR_PAD28)) & 0x0000f000 ) >> 12)
++#define GET_PAD28_SEL_OE (((REG32(ADR_PAD28)) & 0x00100000 ) >> 20)
++#define GET_GPIO_3_ID (((REG32(ADR_PAD28)) & 0x10000000 ) >> 28)
++#define GET_PAD29_OE (((REG32(ADR_PAD29)) & 0x00000001 ) >> 0)
++#define GET_PAD29_PE (((REG32(ADR_PAD29)) & 0x00000002 ) >> 1)
++#define GET_PAD29_DS (((REG32(ADR_PAD29)) & 0x00000004 ) >> 2)
++#define GET_PAD29_IE (((REG32(ADR_PAD29)) & 0x00000008 ) >> 3)
++#define GET_PAD29_SEL_I (((REG32(ADR_PAD29)) & 0x00000070 ) >> 4)
++#define GET_PAD29_OD (((REG32(ADR_PAD29)) & 0x00000100 ) >> 8)
++#define GET_PAD29_SEL_O (((REG32(ADR_PAD29)) & 0x00007000 ) >> 12)
++#define GET_GPIO_TEST_5_ID (((REG32(ADR_PAD29)) & 0x10000000 ) >> 28)
++#define GET_PAD30_OE (((REG32(ADR_PAD30)) & 0x00000001 ) >> 0)
++#define GET_PAD30_PE (((REG32(ADR_PAD30)) & 0x00000002 ) >> 1)
++#define GET_PAD30_DS (((REG32(ADR_PAD30)) & 0x00000004 ) >> 2)
++#define GET_PAD30_IE (((REG32(ADR_PAD30)) & 0x00000008 ) >> 3)
++#define GET_PAD30_SEL_I (((REG32(ADR_PAD30)) & 0x00000030 ) >> 4)
++#define GET_PAD30_OD (((REG32(ADR_PAD30)) & 0x00000100 ) >> 8)
++#define GET_PAD30_SEL_O (((REG32(ADR_PAD30)) & 0x00003000 ) >> 12)
++#define GET_TEST_6_ID (((REG32(ADR_PAD30)) & 0x10000000 ) >> 28)
++#define GET_PAD31_OE (((REG32(ADR_PAD31)) & 0x00000001 ) >> 0)
++#define GET_PAD31_PE (((REG32(ADR_PAD31)) & 0x00000002 ) >> 1)
++#define GET_PAD31_DS (((REG32(ADR_PAD31)) & 0x00000004 ) >> 2)
++#define GET_PAD31_IE (((REG32(ADR_PAD31)) & 0x00000008 ) >> 3)
++#define GET_PAD31_SEL_I (((REG32(ADR_PAD31)) & 0x00000030 ) >> 4)
++#define GET_PAD31_OD (((REG32(ADR_PAD31)) & 0x00000100 ) >> 8)
++#define GET_PAD31_SEL_O (((REG32(ADR_PAD31)) & 0x00003000 ) >> 12)
++#define GET_TEST_7_ID (((REG32(ADR_PAD31)) & 0x10000000 ) >> 28)
++#define GET_PAD32_OE (((REG32(ADR_PAD32)) & 0x00000001 ) >> 0)
++#define GET_PAD32_PE (((REG32(ADR_PAD32)) & 0x00000002 ) >> 1)
++#define GET_PAD32_DS (((REG32(ADR_PAD32)) & 0x00000004 ) >> 2)
++#define GET_PAD32_IE (((REG32(ADR_PAD32)) & 0x00000008 ) >> 3)
++#define GET_PAD32_SEL_I (((REG32(ADR_PAD32)) & 0x00000030 ) >> 4)
++#define GET_PAD32_OD (((REG32(ADR_PAD32)) & 0x00000100 ) >> 8)
++#define GET_PAD32_SEL_O (((REG32(ADR_PAD32)) & 0x00003000 ) >> 12)
++#define GET_TEST_8_ID (((REG32(ADR_PAD32)) & 0x10000000 ) >> 28)
++#define GET_PAD33_OE (((REG32(ADR_PAD33)) & 0x00000001 ) >> 0)
++#define GET_PAD33_PE (((REG32(ADR_PAD33)) & 0x00000002 ) >> 1)
++#define GET_PAD33_DS (((REG32(ADR_PAD33)) & 0x00000004 ) >> 2)
++#define GET_PAD33_IE (((REG32(ADR_PAD33)) & 0x00000008 ) >> 3)
++#define GET_PAD33_SEL_I (((REG32(ADR_PAD33)) & 0x00000030 ) >> 4)
++#define GET_PAD33_OD (((REG32(ADR_PAD33)) & 0x00000100 ) >> 8)
++#define GET_PAD33_SEL_O (((REG32(ADR_PAD33)) & 0x00003000 ) >> 12)
++#define GET_TEST_9_ID (((REG32(ADR_PAD33)) & 0x10000000 ) >> 28)
++#define GET_PAD34_OE (((REG32(ADR_PAD34)) & 0x00000001 ) >> 0)
++#define GET_PAD34_PE (((REG32(ADR_PAD34)) & 0x00000002 ) >> 1)
++#define GET_PAD34_DS (((REG32(ADR_PAD34)) & 0x00000004 ) >> 2)
++#define GET_PAD34_IE (((REG32(ADR_PAD34)) & 0x00000008 ) >> 3)
++#define GET_PAD34_SEL_I (((REG32(ADR_PAD34)) & 0x00000030 ) >> 4)
++#define GET_PAD34_OD (((REG32(ADR_PAD34)) & 0x00000100 ) >> 8)
++#define GET_PAD34_SEL_O (((REG32(ADR_PAD34)) & 0x00003000 ) >> 12)
++#define GET_TEST_10_ID (((REG32(ADR_PAD34)) & 0x10000000 ) >> 28)
++#define GET_PAD42_OE (((REG32(ADR_PAD42)) & 0x00000001 ) >> 0)
++#define GET_PAD42_PE (((REG32(ADR_PAD42)) & 0x00000002 ) >> 1)
++#define GET_PAD42_DS (((REG32(ADR_PAD42)) & 0x00000004 ) >> 2)
++#define GET_PAD42_IE (((REG32(ADR_PAD42)) & 0x00000008 ) >> 3)
++#define GET_PAD42_SEL_I (((REG32(ADR_PAD42)) & 0x00000030 ) >> 4)
++#define GET_PAD42_OD (((REG32(ADR_PAD42)) & 0x00000100 ) >> 8)
++#define GET_PAD42_SEL_O (((REG32(ADR_PAD42)) & 0x00001000 ) >> 12)
++#define GET_TEST_11_ID (((REG32(ADR_PAD42)) & 0x10000000 ) >> 28)
++#define GET_PAD43_OE (((REG32(ADR_PAD43)) & 0x00000001 ) >> 0)
++#define GET_PAD43_PE (((REG32(ADR_PAD43)) & 0x00000002 ) >> 1)
++#define GET_PAD43_DS (((REG32(ADR_PAD43)) & 0x00000004 ) >> 2)
++#define GET_PAD43_IE (((REG32(ADR_PAD43)) & 0x00000008 ) >> 3)
++#define GET_PAD43_SEL_I (((REG32(ADR_PAD43)) & 0x00000030 ) >> 4)
++#define GET_PAD43_OD (((REG32(ADR_PAD43)) & 0x00000100 ) >> 8)
++#define GET_PAD43_SEL_O (((REG32(ADR_PAD43)) & 0x00001000 ) >> 12)
++#define GET_TEST_12_ID (((REG32(ADR_PAD43)) & 0x10000000 ) >> 28)
++#define GET_PAD44_OE (((REG32(ADR_PAD44)) & 0x00000001 ) >> 0)
++#define GET_PAD44_PE (((REG32(ADR_PAD44)) & 0x00000002 ) >> 1)
++#define GET_PAD44_DS (((REG32(ADR_PAD44)) & 0x00000004 ) >> 2)
++#define GET_PAD44_IE (((REG32(ADR_PAD44)) & 0x00000008 ) >> 3)
++#define GET_PAD44_SEL_I (((REG32(ADR_PAD44)) & 0x00000030 ) >> 4)
++#define GET_PAD44_OD (((REG32(ADR_PAD44)) & 0x00000100 ) >> 8)
++#define GET_PAD44_SEL_O (((REG32(ADR_PAD44)) & 0x00003000 ) >> 12)
++#define GET_TEST_13_ID (((REG32(ADR_PAD44)) & 0x10000000 ) >> 28)
++#define GET_PAD45_OE (((REG32(ADR_PAD45)) & 0x00000001 ) >> 0)
++#define GET_PAD45_PE (((REG32(ADR_PAD45)) & 0x00000002 ) >> 1)
++#define GET_PAD45_DS (((REG32(ADR_PAD45)) & 0x00000004 ) >> 2)
++#define GET_PAD45_IE (((REG32(ADR_PAD45)) & 0x00000008 ) >> 3)
++#define GET_PAD45_SEL_I (((REG32(ADR_PAD45)) & 0x00000030 ) >> 4)
++#define GET_PAD45_OD (((REG32(ADR_PAD45)) & 0x00000100 ) >> 8)
++#define GET_PAD45_SEL_O (((REG32(ADR_PAD45)) & 0x00003000 ) >> 12)
++#define GET_TEST_14_ID (((REG32(ADR_PAD45)) & 0x10000000 ) >> 28)
++#define GET_PAD46_OE (((REG32(ADR_PAD46)) & 0x00000001 ) >> 0)
++#define GET_PAD46_PE (((REG32(ADR_PAD46)) & 0x00000002 ) >> 1)
++#define GET_PAD46_DS (((REG32(ADR_PAD46)) & 0x00000004 ) >> 2)
++#define GET_PAD46_IE (((REG32(ADR_PAD46)) & 0x00000008 ) >> 3)
++#define GET_PAD46_SEL_I (((REG32(ADR_PAD46)) & 0x00000030 ) >> 4)
++#define GET_PAD46_OD (((REG32(ADR_PAD46)) & 0x00000100 ) >> 8)
++#define GET_PAD46_SEL_O (((REG32(ADR_PAD46)) & 0x00003000 ) >> 12)
++#define GET_TEST_15_ID (((REG32(ADR_PAD46)) & 0x10000000 ) >> 28)
++#define GET_PAD47_OE (((REG32(ADR_PAD47)) & 0x00000001 ) >> 0)
++#define GET_PAD47_PE (((REG32(ADR_PAD47)) & 0x00000002 ) >> 1)
++#define GET_PAD47_DS (((REG32(ADR_PAD47)) & 0x00000004 ) >> 2)
++#define GET_PAD47_SEL_I (((REG32(ADR_PAD47)) & 0x00000030 ) >> 4)
++#define GET_PAD47_OD (((REG32(ADR_PAD47)) & 0x00000100 ) >> 8)
++#define GET_PAD47_SEL_O (((REG32(ADR_PAD47)) & 0x00003000 ) >> 12)
++#define GET_PAD47_SEL_OE (((REG32(ADR_PAD47)) & 0x00100000 ) >> 20)
++#define GET_GPIO_9_ID (((REG32(ADR_PAD47)) & 0x10000000 ) >> 28)
++#define GET_PAD48_OE (((REG32(ADR_PAD48)) & 0x00000001 ) >> 0)
++#define GET_PAD48_PE (((REG32(ADR_PAD48)) & 0x00000002 ) >> 1)
++#define GET_PAD48_DS (((REG32(ADR_PAD48)) & 0x00000004 ) >> 2)
++#define GET_PAD48_IE (((REG32(ADR_PAD48)) & 0x00000008 ) >> 3)
++#define GET_PAD48_SEL_I (((REG32(ADR_PAD48)) & 0x00000070 ) >> 4)
++#define GET_PAD48_OD (((REG32(ADR_PAD48)) & 0x00000100 ) >> 8)
++#define GET_PAD48_PE_SEL (((REG32(ADR_PAD48)) & 0x00000800 ) >> 11)
++#define GET_PAD48_SEL_O (((REG32(ADR_PAD48)) & 0x00003000 ) >> 12)
++#define GET_PAD48_SEL_OE (((REG32(ADR_PAD48)) & 0x00100000 ) >> 20)
++#define GET_GPIO_10_ID (((REG32(ADR_PAD48)) & 0x10000000 ) >> 28)
++#define GET_PAD49_OE (((REG32(ADR_PAD49)) & 0x00000001 ) >> 0)
++#define GET_PAD49_PE (((REG32(ADR_PAD49)) & 0x00000002 ) >> 1)
++#define GET_PAD49_DS (((REG32(ADR_PAD49)) & 0x00000004 ) >> 2)
++#define GET_PAD49_IE (((REG32(ADR_PAD49)) & 0x00000008 ) >> 3)
++#define GET_PAD49_SEL_I (((REG32(ADR_PAD49)) & 0x00000070 ) >> 4)
++#define GET_PAD49_OD (((REG32(ADR_PAD49)) & 0x00000100 ) >> 8)
++#define GET_PAD49_SEL_O (((REG32(ADR_PAD49)) & 0x00003000 ) >> 12)
++#define GET_PAD49_SEL_OE (((REG32(ADR_PAD49)) & 0x00100000 ) >> 20)
++#define GET_GPIO_11_ID (((REG32(ADR_PAD49)) & 0x10000000 ) >> 28)
++#define GET_PAD50_OE (((REG32(ADR_PAD50)) & 0x00000001 ) >> 0)
++#define GET_PAD50_PE (((REG32(ADR_PAD50)) & 0x00000002 ) >> 1)
++#define GET_PAD50_DS (((REG32(ADR_PAD50)) & 0x00000004 ) >> 2)
++#define GET_PAD50_IE (((REG32(ADR_PAD50)) & 0x00000008 ) >> 3)
++#define GET_PAD50_SEL_I (((REG32(ADR_PAD50)) & 0x00000070 ) >> 4)
++#define GET_PAD50_OD (((REG32(ADR_PAD50)) & 0x00000100 ) >> 8)
++#define GET_PAD50_SEL_O (((REG32(ADR_PAD50)) & 0x00003000 ) >> 12)
++#define GET_PAD50_SEL_OE (((REG32(ADR_PAD50)) & 0x00100000 ) >> 20)
++#define GET_GPIO_12_ID (((REG32(ADR_PAD50)) & 0x10000000 ) >> 28)
++#define GET_PAD51_OE (((REG32(ADR_PAD51)) & 0x00000001 ) >> 0)
++#define GET_PAD51_PE (((REG32(ADR_PAD51)) & 0x00000002 ) >> 1)
++#define GET_PAD51_DS (((REG32(ADR_PAD51)) & 0x00000004 ) >> 2)
++#define GET_PAD51_IE (((REG32(ADR_PAD51)) & 0x00000008 ) >> 3)
++#define GET_PAD51_SEL_I (((REG32(ADR_PAD51)) & 0x00000030 ) >> 4)
++#define GET_PAD51_OD (((REG32(ADR_PAD51)) & 0x00000100 ) >> 8)
++#define GET_PAD51_SEL_O (((REG32(ADR_PAD51)) & 0x00001000 ) >> 12)
++#define GET_PAD51_SEL_OE (((REG32(ADR_PAD51)) & 0x00100000 ) >> 20)
++#define GET_GPIO_13_ID (((REG32(ADR_PAD51)) & 0x10000000 ) >> 28)
++#define GET_PAD52_OE (((REG32(ADR_PAD52)) & 0x00000001 ) >> 0)
++#define GET_PAD52_PE (((REG32(ADR_PAD52)) & 0x00000002 ) >> 1)
++#define GET_PAD52_DS (((REG32(ADR_PAD52)) & 0x00000004 ) >> 2)
++#define GET_PAD52_SEL_I (((REG32(ADR_PAD52)) & 0x00000030 ) >> 4)
++#define GET_PAD52_OD (((REG32(ADR_PAD52)) & 0x00000100 ) >> 8)
++#define GET_PAD52_SEL_O (((REG32(ADR_PAD52)) & 0x00001000 ) >> 12)
++#define GET_PAD52_SEL_OE (((REG32(ADR_PAD52)) & 0x00100000 ) >> 20)
++#define GET_GPIO_14_ID (((REG32(ADR_PAD52)) & 0x10000000 ) >> 28)
++#define GET_PAD53_OE (((REG32(ADR_PAD53)) & 0x00000001 ) >> 0)
++#define GET_PAD53_PE (((REG32(ADR_PAD53)) & 0x00000002 ) >> 1)
++#define GET_PAD53_DS (((REG32(ADR_PAD53)) & 0x00000004 ) >> 2)
++#define GET_PAD53_IE (((REG32(ADR_PAD53)) & 0x00000008 ) >> 3)
++#define GET_PAD53_SEL_I (((REG32(ADR_PAD53)) & 0x00000030 ) >> 4)
++#define GET_PAD53_OD (((REG32(ADR_PAD53)) & 0x00000100 ) >> 8)
++#define GET_PAD53_SEL_O (((REG32(ADR_PAD53)) & 0x00001000 ) >> 12)
++#define GET_JTAG_TMS_ID (((REG32(ADR_PAD53)) & 0x10000000 ) >> 28)
++#define GET_PAD54_OE (((REG32(ADR_PAD54)) & 0x00000001 ) >> 0)
++#define GET_PAD54_PE (((REG32(ADR_PAD54)) & 0x00000002 ) >> 1)
++#define GET_PAD54_DS (((REG32(ADR_PAD54)) & 0x00000004 ) >> 2)
++#define GET_PAD54_OD (((REG32(ADR_PAD54)) & 0x00000100 ) >> 8)
++#define GET_PAD54_SEL_O (((REG32(ADR_PAD54)) & 0x00003000 ) >> 12)
++#define GET_JTAG_TCK_ID (((REG32(ADR_PAD54)) & 0x10000000 ) >> 28)
++#define GET_PAD56_PE (((REG32(ADR_PAD56)) & 0x00000002 ) >> 1)
++#define GET_PAD56_DS (((REG32(ADR_PAD56)) & 0x00000004 ) >> 2)
++#define GET_PAD56_SEL_I (((REG32(ADR_PAD56)) & 0x00000010 ) >> 4)
++#define GET_PAD56_OD (((REG32(ADR_PAD56)) & 0x00000100 ) >> 8)
++#define GET_JTAG_TDI_ID (((REG32(ADR_PAD56)) & 0x10000000 ) >> 28)
++#define GET_PAD57_OE (((REG32(ADR_PAD57)) & 0x00000001 ) >> 0)
++#define GET_PAD57_PE (((REG32(ADR_PAD57)) & 0x00000002 ) >> 1)
++#define GET_PAD57_DS (((REG32(ADR_PAD57)) & 0x00000004 ) >> 2)
++#define GET_PAD57_IE (((REG32(ADR_PAD57)) & 0x00000008 ) >> 3)
++#define GET_PAD57_SEL_I (((REG32(ADR_PAD57)) & 0x00000030 ) >> 4)
++#define GET_PAD57_OD (((REG32(ADR_PAD57)) & 0x00000100 ) >> 8)
++#define GET_PAD57_SEL_O (((REG32(ADR_PAD57)) & 0x00003000 ) >> 12)
++#define GET_PAD57_SEL_OE (((REG32(ADR_PAD57)) & 0x00100000 ) >> 20)
++#define GET_JTAG_TDO_ID (((REG32(ADR_PAD57)) & 0x10000000 ) >> 28)
++#define GET_PAD58_OE (((REG32(ADR_PAD58)) & 0x00000001 ) >> 0)
++#define GET_PAD58_PE (((REG32(ADR_PAD58)) & 0x00000002 ) >> 1)
++#define GET_PAD58_DS (((REG32(ADR_PAD58)) & 0x00000004 ) >> 2)
++#define GET_PAD58_IE (((REG32(ADR_PAD58)) & 0x00000008 ) >> 3)
++#define GET_PAD58_SEL_I (((REG32(ADR_PAD58)) & 0x00000030 ) >> 4)
++#define GET_PAD58_OD (((REG32(ADR_PAD58)) & 0x00000100 ) >> 8)
++#define GET_PAD58_SEL_O (((REG32(ADR_PAD58)) & 0x00001000 ) >> 12)
++#define GET_TEST_16_ID (((REG32(ADR_PAD58)) & 0x10000000 ) >> 28)
++#define GET_PAD59_OE (((REG32(ADR_PAD59)) & 0x00000001 ) >> 0)
++#define GET_PAD59_PE (((REG32(ADR_PAD59)) & 0x00000002 ) >> 1)
++#define GET_PAD59_DS (((REG32(ADR_PAD59)) & 0x00000004 ) >> 2)
++#define GET_PAD59_IE (((REG32(ADR_PAD59)) & 0x00000008 ) >> 3)
++#define GET_PAD59_SEL_I (((REG32(ADR_PAD59)) & 0x00000030 ) >> 4)
++#define GET_PAD59_OD (((REG32(ADR_PAD59)) & 0x00000100 ) >> 8)
++#define GET_PAD59_SEL_O (((REG32(ADR_PAD59)) & 0x00001000 ) >> 12)
++#define GET_TEST_17_ID (((REG32(ADR_PAD59)) & 0x10000000 ) >> 28)
++#define GET_PAD60_OE (((REG32(ADR_PAD60)) & 0x00000001 ) >> 0)
++#define GET_PAD60_PE (((REG32(ADR_PAD60)) & 0x00000002 ) >> 1)
++#define GET_PAD60_DS (((REG32(ADR_PAD60)) & 0x00000004 ) >> 2)
++#define GET_PAD60_IE (((REG32(ADR_PAD60)) & 0x00000008 ) >> 3)
++#define GET_PAD60_SEL_I (((REG32(ADR_PAD60)) & 0x00000030 ) >> 4)
++#define GET_PAD60_OD (((REG32(ADR_PAD60)) & 0x00000100 ) >> 8)
++#define GET_PAD60_SEL_O (((REG32(ADR_PAD60)) & 0x00001000 ) >> 12)
++#define GET_TEST_18_ID (((REG32(ADR_PAD60)) & 0x10000000 ) >> 28)
++#define GET_PAD61_OE (((REG32(ADR_PAD61)) & 0x00000001 ) >> 0)
++#define GET_PAD61_PE (((REG32(ADR_PAD61)) & 0x00000002 ) >> 1)
++#define GET_PAD61_DS (((REG32(ADR_PAD61)) & 0x00000004 ) >> 2)
++#define GET_PAD61_IE (((REG32(ADR_PAD61)) & 0x00000008 ) >> 3)
++#define GET_PAD61_SEL_I (((REG32(ADR_PAD61)) & 0x00000010 ) >> 4)
++#define GET_PAD61_OD (((REG32(ADR_PAD61)) & 0x00000100 ) >> 8)
++#define GET_PAD61_SEL_O (((REG32(ADR_PAD61)) & 0x00003000 ) >> 12)
++#define GET_TEST_19_ID (((REG32(ADR_PAD61)) & 0x10000000 ) >> 28)
++#define GET_PAD62_OE (((REG32(ADR_PAD62)) & 0x00000001 ) >> 0)
++#define GET_PAD62_PE (((REG32(ADR_PAD62)) & 0x00000002 ) >> 1)
++#define GET_PAD62_DS (((REG32(ADR_PAD62)) & 0x00000004 ) >> 2)
++#define GET_PAD62_IE (((REG32(ADR_PAD62)) & 0x00000008 ) >> 3)
++#define GET_PAD62_SEL_I (((REG32(ADR_PAD62)) & 0x00000010 ) >> 4)
++#define GET_PAD62_OD (((REG32(ADR_PAD62)) & 0x00000100 ) >> 8)
++#define GET_PAD62_SEL_O (((REG32(ADR_PAD62)) & 0x00001000 ) >> 12)
++#define GET_TEST_20_ID (((REG32(ADR_PAD62)) & 0x10000000 ) >> 28)
++#define GET_PAD64_OE (((REG32(ADR_PAD64)) & 0x00000001 ) >> 0)
++#define GET_PAD64_PE (((REG32(ADR_PAD64)) & 0x00000002 ) >> 1)
++#define GET_PAD64_DS (((REG32(ADR_PAD64)) & 0x00000004 ) >> 2)
++#define GET_PAD64_IE (((REG32(ADR_PAD64)) & 0x00000008 ) >> 3)
++#define GET_PAD64_SEL_I (((REG32(ADR_PAD64)) & 0x00000070 ) >> 4)
++#define GET_PAD64_OD (((REG32(ADR_PAD64)) & 0x00000100 ) >> 8)
++#define GET_PAD64_SEL_O (((REG32(ADR_PAD64)) & 0x00003000 ) >> 12)
++#define GET_PAD64_SEL_OE (((REG32(ADR_PAD64)) & 0x00100000 ) >> 20)
++#define GET_GPIO_15_IP_ID (((REG32(ADR_PAD64)) & 0x10000000 ) >> 28)
++#define GET_PAD65_OE (((REG32(ADR_PAD65)) & 0x00000001 ) >> 0)
++#define GET_PAD65_PE (((REG32(ADR_PAD65)) & 0x00000002 ) >> 1)
++#define GET_PAD65_DS (((REG32(ADR_PAD65)) & 0x00000004 ) >> 2)
++#define GET_PAD65_IE (((REG32(ADR_PAD65)) & 0x00000008 ) >> 3)
++#define GET_PAD65_SEL_I (((REG32(ADR_PAD65)) & 0x00000070 ) >> 4)
++#define GET_PAD65_OD (((REG32(ADR_PAD65)) & 0x00000100 ) >> 8)
++#define GET_PAD65_SEL_O (((REG32(ADR_PAD65)) & 0x00001000 ) >> 12)
++#define GET_GPIO_TEST_7_IN_ID (((REG32(ADR_PAD65)) & 0x10000000 ) >> 28)
++#define GET_PAD66_OE (((REG32(ADR_PAD66)) & 0x00000001 ) >> 0)
++#define GET_PAD66_PE (((REG32(ADR_PAD66)) & 0x00000002 ) >> 1)
++#define GET_PAD66_DS (((REG32(ADR_PAD66)) & 0x00000004 ) >> 2)
++#define GET_PAD66_IE (((REG32(ADR_PAD66)) & 0x00000008 ) >> 3)
++#define GET_PAD66_SEL_I (((REG32(ADR_PAD66)) & 0x00000030 ) >> 4)
++#define GET_PAD66_OD (((REG32(ADR_PAD66)) & 0x00000100 ) >> 8)
++#define GET_PAD66_SEL_O (((REG32(ADR_PAD66)) & 0x00003000 ) >> 12)
++#define GET_GPIO_17_QP_ID (((REG32(ADR_PAD66)) & 0x10000000 ) >> 28)
++#define GET_PAD68_OE (((REG32(ADR_PAD68)) & 0x00000001 ) >> 0)
++#define GET_PAD68_PE (((REG32(ADR_PAD68)) & 0x00000002 ) >> 1)
++#define GET_PAD68_DS (((REG32(ADR_PAD68)) & 0x00000004 ) >> 2)
++#define GET_PAD68_IE (((REG32(ADR_PAD68)) & 0x00000008 ) >> 3)
++#define GET_PAD68_OD (((REG32(ADR_PAD68)) & 0x00000100 ) >> 8)
++#define GET_PAD68_SEL_O (((REG32(ADR_PAD68)) & 0x00001000 ) >> 12)
++#define GET_GPIO_19_ID (((REG32(ADR_PAD68)) & 0x10000000 ) >> 28)
++#define GET_PAD67_OE (((REG32(ADR_PAD67)) & 0x00000001 ) >> 0)
++#define GET_PAD67_PE (((REG32(ADR_PAD67)) & 0x00000002 ) >> 1)
++#define GET_PAD67_DS (((REG32(ADR_PAD67)) & 0x00000004 ) >> 2)
++#define GET_PAD67_IE (((REG32(ADR_PAD67)) & 0x00000008 ) >> 3)
++#define GET_PAD67_SEL_I (((REG32(ADR_PAD67)) & 0x00000070 ) >> 4)
++#define GET_PAD67_OD (((REG32(ADR_PAD67)) & 0x00000100 ) >> 8)
++#define GET_PAD67_SEL_O (((REG32(ADR_PAD67)) & 0x00003000 ) >> 12)
++#define GET_GPIO_TEST_8_QN_ID (((REG32(ADR_PAD67)) & 0x10000000 ) >> 28)
++#define GET_PAD69_OE (((REG32(ADR_PAD69)) & 0x00000001 ) >> 0)
++#define GET_PAD69_PE (((REG32(ADR_PAD69)) & 0x00000002 ) >> 1)
++#define GET_PAD69_DS (((REG32(ADR_PAD69)) & 0x00000004 ) >> 2)
++#define GET_PAD69_IE (((REG32(ADR_PAD69)) & 0x00000008 ) >> 3)
++#define GET_PAD69_SEL_I (((REG32(ADR_PAD69)) & 0x00000030 ) >> 4)
++#define GET_PAD69_OD (((REG32(ADR_PAD69)) & 0x00000100 ) >> 8)
++#define GET_PAD69_SEL_O (((REG32(ADR_PAD69)) & 0x00001000 ) >> 12)
++#define GET_STRAP2 (((REG32(ADR_PAD69)) & 0x08000000 ) >> 27)
++#define GET_GPIO_20_ID (((REG32(ADR_PAD69)) & 0x10000000 ) >> 28)
++#define GET_PAD70_OE (((REG32(ADR_PAD70)) & 0x00000001 ) >> 0)
++#define GET_PAD70_PE (((REG32(ADR_PAD70)) & 0x00000002 ) >> 1)
++#define GET_PAD70_DS (((REG32(ADR_PAD70)) & 0x00000004 ) >> 2)
++#define GET_PAD70_IE (((REG32(ADR_PAD70)) & 0x00000008 ) >> 3)
++#define GET_PAD70_SEL_I (((REG32(ADR_PAD70)) & 0x00000030 ) >> 4)
++#define GET_PAD70_OD (((REG32(ADR_PAD70)) & 0x00000100 ) >> 8)
++#define GET_PAD70_SEL_O (((REG32(ADR_PAD70)) & 0x00007000 ) >> 12)
++#define GET_GPIO_21_ID (((REG32(ADR_PAD70)) & 0x10000000 ) >> 28)
++#define GET_PAD231_OE (((REG32(ADR_PAD231)) & 0x00000001 ) >> 0)
++#define GET_PAD231_PE (((REG32(ADR_PAD231)) & 0x00000002 ) >> 1)
++#define GET_PAD231_DS (((REG32(ADR_PAD231)) & 0x00000004 ) >> 2)
++#define GET_PAD231_IE (((REG32(ADR_PAD231)) & 0x00000008 ) >> 3)
++#define GET_PAD231_OD (((REG32(ADR_PAD231)) & 0x00000100 ) >> 8)
++#define GET_PIN_40_OR_56_ID (((REG32(ADR_PAD231)) & 0x10000000 ) >> 28)
++#define GET_MP_PHY2RX_DATA__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000001 ) >> 0)
++#define GET_MP_PHY2RX_DATA__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000002 ) >> 1)
++#define GET_MP_TX_FF_RPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000004 ) >> 2)
++#define GET_MP_RX_FF_WPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000008 ) >> 3)
++#define GET_MP_RX_FF_WPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000010 ) >> 4)
++#define GET_MP_RX_FF_WPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000020 ) >> 5)
++#define GET_MP_PHY2RX_DATA__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000040 ) >> 6)
++#define GET_MP_PHY2RX_DATA__4_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000080 ) >> 7)
++#define GET_I2CM_SDA_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000300 ) >> 8)
++#define GET_CRYSTAL_OUT_REQ_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000400 ) >> 10)
++#define GET_MP_PHY2RX_DATA__5_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000800 ) >> 11)
++#define GET_MP_PHY2RX_DATA__3_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00001000 ) >> 12)
++#define GET_UART_RXD_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00006000 ) >> 13)
++#define GET_MP_PHY2RX_DATA__6_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00008000 ) >> 15)
++#define GET_DAT_UART_NCTS_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00010000 ) >> 16)
++#define GET_GPIO_LOG_STOP_SEL (((REG32(ADR_PIN_SEL_0)) & 0x000e0000 ) >> 17)
++#define GET_MP_TX_FF_RPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00100000 ) >> 20)
++#define GET_MP_PHY_RX_WRST_N_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00200000 ) >> 21)
++#define GET_EXT_32K_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00c00000 ) >> 22)
++#define GET_MP_PHY2RX_DATA__7_SEL (((REG32(ADR_PIN_SEL_0)) & 0x01000000 ) >> 24)
++#define GET_MP_TX_FF_RPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x02000000 ) >> 25)
++#define GET_PMUINT_WAKE_SEL (((REG32(ADR_PIN_SEL_0)) & 0x1c000000 ) >> 26)
++#define GET_I2CM_SCL_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x20000000 ) >> 29)
++#define GET_MP_MRX_RX_EN_SEL (((REG32(ADR_PIN_SEL_0)) & 0x40000000 ) >> 30)
++#define GET_DAT_UART_RXD_SEL_0 (((REG32(ADR_PIN_SEL_0)) & 0x80000000 ) >> 31)
++#define GET_DAT_UART_RXD_SEL_1 (((REG32(ADR_PIN_SEL_1)) & 0x00000001 ) >> 0)
++#define GET_SPI_DI_SEL (((REG32(ADR_PIN_SEL_1)) & 0x00000002 ) >> 1)
++#define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0)
++#define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0)
++#define GET_MASK_TX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1)
++#define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2)
++#define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3)
++#define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4)
++#define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5)
++#define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6)
++#define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7)
++#define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0)
++#define GET_TX_COMPLETE_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1)
++#define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2)
++#define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3)
++#define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4)
++#define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5)
++#define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6)
++#define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7)
++#define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8)
++#define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9)
++#define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10)
++#define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11)
++#define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0)
++#define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1)
++#define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2)
++#define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3)
++#define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4)
++#define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5)
++#define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7)
++#define GET_RX_PACKET_LENGTH (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x0000ffff ) >> 0)
++#define GET_CARD_FW_DL_STATUS (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x00ff0000 ) >> 16)
++#define GET_TX_RX_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x01000000 ) >> 24)
++#define GET_SDIO_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x02000000 ) >> 25)
++#define GET_CMD52_ABORT_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x10000000 ) >> 28)
++#define GET_CMD52_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x20000000 ) >> 29)
++#define GET_SDIO_PARTIAL_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x40000000 ) >> 30)
++#define GET_SDIO_ALL_RESE_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x80000000 ) >> 31)
++#define GET_RX_PACKET_LENGTH2 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x0000ffff ) >> 0)
++#define GET_RX_INT1 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00010000 ) >> 16)
++#define GET_TX_DONE (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00020000 ) >> 17)
++#define GET_HCI_TRX_FINISH (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00040000 ) >> 18)
++#define GET_ALLOCATE_STATUS (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00080000 ) >> 19)
++#define GET_HCI_INPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00f00000 ) >> 20)
++#define GET_HCI_OUTPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x1f000000 ) >> 24)
++#define GET_AHB_HANG4 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x20000000 ) >> 29)
++#define GET_HCI_IN_QUE_EMPTY (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x40000000 ) >> 30)
++#define GET_SYSTEM_INT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x80000000 ) >> 31)
++#define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0)
++#define GET_SDIO_FIFO_WR_THLD_REG (((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_FIFO_WR_LIMIT_REG (((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_TX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_THLD_FOR_CMD53RD_REG (((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_RX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
++#define GET_START_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x000000ff ) >> 0)
++#define GET_END_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x0000ff00 ) >> 8)
++#define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0)
++#define GET_SDIO_LAST_CMD_INDEX_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x0000003f ) >> 0)
++#define GET_SDIO_LAST_CMD_CRC_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x00007f00 ) >> 8)
++#define GET_SDIO_LAST_CMD_ARG_REG (((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0xffffffff ) >> 0)
++#define GET_SDIO_BUS_STATE_REG (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000001f ) >> 0)
++#define GET_SDIO_BUSY_LONG_CNT (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffff0000 ) >> 16)
++#define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0)
++#define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0)
++#define GET_RESP_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000100 ) >> 8)
++#define GET_DAT_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000200 ) >> 9)
++#define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16)
++#define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17)
++#define GET_WRITE_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x000000ff ) >> 0)
++#define GET_WRITE_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x0000ff00 ) >> 8)
++#define GET_READ_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ff0000 ) >> 16)
++#define GET_READ_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff000000 ) >> 24)
++#define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0)
++#define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0)
++#define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8)
++#define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9)
++#define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10)
++#define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11)
++#define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12)
++#define GET_IO_REG_PORT_REG (((REG32(ADR_IO_REG_PORT_REG)) & 0x0001ffff ) >> 0)
++#define GET_SDIO_FIFO_EMPTY_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_SDIO_FIFO_FULL_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000 ) >> 16)
++#define GET_SDIO_CRC7_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff ) >> 0)
++#define GET_SDIO_CRC16_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000 ) >> 16)
++#define GET_SDIO_RD_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x000001ff ) >> 0)
++#define GET_SDIO_WR_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x01ff0000 ) >> 16)
++#define GET_CMD52_RD_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x000f0000 ) >> 16)
++#define GET_CMD52_WR_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x00f00000 ) >> 20)
++#define GET_SDIO_FIFO_WR_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x000000ff ) >> 0)
++#define GET_SDIO_FIFO_RD_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x0000ff00 ) >> 8)
++#define GET_SDIO_READ_DATA_CTRL (((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0x00010000 ) >> 16)
++#define GET_TX_SIZE_BEFORE_SHIFT (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x000000ff ) >> 0)
++#define GET_TX_SIZE_SHIFT_BITS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00000700 ) >> 8)
++#define GET_SDIO_TX_ALLOC_STATE (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00001000 ) >> 12)
++#define GET_ALLOCATE_STATUS2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00010000 ) >> 16)
++#define GET_NO_ALLOCATE_SEND_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00020000 ) >> 17)
++#define GET_DOUBLE_ALLOCATE_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00040000 ) >> 18)
++#define GET_TX_DONE_STATUS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00080000 ) >> 19)
++#define GET_AHB_HANG2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00100000 ) >> 20)
++#define GET_HCI_TRX_FINISH2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00200000 ) >> 21)
++#define GET_INTR_RX (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00400000 ) >> 22)
++#define GET_HCI_INPUT_QUEUE_FULL (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00800000 ) >> 23)
++#define GET_ALLOCATESTATUS (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000001 ) >> 0)
++#define GET_HCI_TRX_FINISH3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000002 ) >> 1)
++#define GET_HCI_IN_QUE_EMPTY2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000004 ) >> 2)
++#define GET_MTX_MNG_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000008 ) >> 3)
++#define GET_EDCA0_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000010 ) >> 4)
++#define GET_EDCA1_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000020 ) >> 5)
++#define GET_EDCA2_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000040 ) >> 6)
++#define GET_EDCA3_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000080 ) >> 7)
++#define GET_TX_PAGE_REMAIN2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0000ff00 ) >> 8)
++#define GET_TX_ID_REMAIN3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x007f0000 ) >> 16)
++#define GET_HCI_OUTPUT_FF_CNT_0 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00800000 ) >> 23)
++#define GET_HCI_OUTPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0f000000 ) >> 24)
++#define GET_HCI_INPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0xf0000000 ) >> 28)
++#define GET_F1_BLOCK_SIZE_0_REG (((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0x00000fff ) >> 0)
++#define GET_START_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x000000ff ) >> 0)
++#define GET_COMMAND_COUNTER (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ff00 ) >> 8)
++#define GET_CMD_LOG_PART1 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff0000 ) >> 16)
++#define GET_CMD_LOG_PART2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff ) >> 0)
++#define GET_END_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000 ) >> 24)
++#define GET_RX_PACKET_LENGTH3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x0000ffff ) >> 0)
++#define GET_RX_INT3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_TX_ID_REMAIN2 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00fe0000 ) >> 17)
++#define GET_TX_PAGE_REMAIN3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff000000 ) >> 24)
++#define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0)
++#define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16)
++#define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24)
++#define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0)
++#define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8)
++#define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16)
++#define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24)
++#define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0)
++#define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1)
++#define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2)
++#define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3)
++#define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4)
++#define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5)
++#define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6)
++#define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7)
++#define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8)
++#define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24)
++#define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25)
++#define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0)
++#define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6)
++#define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7)
++#define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8)
++#define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8)
++#define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
++#define GET_SPI_MODE (((REG32(ADR_SPI_MODE)) & 0xffffffff ) >> 0)
++#define GET_RX_QUOTA (((REG32(ADR_RX_QUOTA)) & 0x0000ffff ) >> 0)
++#define GET_CONDI_NUM (((REG32(ADR_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
++#define GET_HOST_PATH (((REG32(ADR_HOST_PATH)) & 0x00000001 ) >> 0)
++#define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0)
++#define GET_BRST_MODE (((REG32(ADR_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
++#define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
++#define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
++#define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
++#define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
++#define GET_RX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000002 ) >> 1)
++#define GET_RX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000004 ) >> 2)
++#define GET_TX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000008 ) >> 3)
++#define GET_TX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000010 ) >> 4)
++#define GET_SPI_DOUBLE_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000020 ) >> 5)
++#define GET_SPI_TX_NO_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000040 ) >> 6)
++#define GET_RDATA_RDY (((REG32(ADR_SPI_STS)) & 0x00000080 ) >> 7)
++#define GET_SPI_ALLOC_STATUS (((REG32(ADR_SPI_STS)) & 0x00000100 ) >> 8)
++#define GET_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_SPI_STS)) & 0x00000200 ) >> 9)
++#define GET_RX_LEN (((REG32(ADR_SPI_STS)) & 0xffff0000 ) >> 16)
++#define GET_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
++#define GET_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
++#define GET_SPI_TX_ALLOC_SIZE (((REG32(ADR_TX_ALLOC)) & 0x000000ff ) >> 0)
++#define GET_RD_DAT_CNT (((REG32(ADR_DBG_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RD_STS_CNT (((REG32(ADR_DBG_CNT)) & 0xffff0000 ) >> 16)
++#define GET_JUDGE_CNT (((REG32(ADR_DBG_CNT2)) & 0x0000ffff ) >> 0)
++#define GET_RD_STS_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00010000 ) >> 16)
++#define GET_RD_DAT_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00020000 ) >> 17)
++#define GET_JUDGE_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00040000 ) >> 18)
++#define GET_TX_DONE_CNT (((REG32(ADR_DBG_CNT3)) & 0x0000ffff ) >> 0)
++#define GET_TX_DISCARD_CNT (((REG32(ADR_DBG_CNT3)) & 0xffff0000 ) >> 16)
++#define GET_TX_SET_CNT (((REG32(ADR_DBG_CNT4)) & 0x0000ffff ) >> 0)
++#define GET_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00010000 ) >> 16)
++#define GET_TX_DONE_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00020000 ) >> 17)
++#define GET_TX_SET_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00040000 ) >> 18)
++#define GET_DAT_MODE_OFF (((REG32(ADR_DBG_CNT4)) & 0x00080000 ) >> 19)
++#define GET_TX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x00700000 ) >> 20)
++#define GET_RX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x07000000 ) >> 24)
++#define GET_RX_RDY (((REG32(ADR_INT_TAG)) & 0x00000001 ) >> 0)
++#define GET_SDIO_SYS_INT (((REG32(ADR_INT_TAG)) & 0x00000004 ) >> 2)
++#define GET_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000008 ) >> 3)
++#define GET_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000010 ) >> 4)
++#define GET_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000020 ) >> 5)
++#define GET_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000040 ) >> 6)
++#define GET_TX_LIMIT_INT_IN (((REG32(ADR_INT_TAG)) & 0x00000080 ) >> 7)
++#define GET_SPI_FN1 (((REG32(ADR_INT_TAG)) & 0x00007f00 ) >> 8)
++#define GET_SPI_CLK_EN_INT (((REG32(ADR_INT_TAG)) & 0x00008000 ) >> 15)
++#define GET_SPI_HOST_MASK (((REG32(ADR_INT_TAG)) & 0x00ff0000 ) >> 16)
++#define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0)
++#define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1)
++#define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2)
++#define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3)
++#define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4)
++#define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16)
++#define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17)
++#define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18)
++#define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0)
++#define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14)
++#define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15)
++#define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0)
++#define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16)
++#define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24)
++#define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0)
++#define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0)
++#define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0)
++#define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16)
++#define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17)
++#define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0)
++#define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0)
++#define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1)
++#define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2)
++#define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3)
++#define GET_DMA_RXEND_IE (((REG32(ADR_UART_IER)) & 0x00000040 ) >> 6)
++#define GET_DMA_TXEND_IE (((REG32(ADR_UART_IER)) & 0x00000080 ) >> 7)
++#define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0)
++#define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1)
++#define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2)
++#define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3)
++#define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4)
++#define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5)
++#define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6)
++#define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0)
++#define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2)
++#define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3)
++#define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4)
++#define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5)
++#define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6)
++#define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7)
++#define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0)
++#define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1)
++#define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2)
++#define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3)
++#define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4)
++#define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0)
++#define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1)
++#define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2)
++#define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3)
++#define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4)
++#define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5)
++#define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6)
++#define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7)
++#define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0)
++#define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1)
++#define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2)
++#define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3)
++#define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4)
++#define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5)
++#define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6)
++#define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7)
++#define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0)
++#define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0)
++#define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4)
++#define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0)
++#define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6)
++#define GET_DAT_UART_DATA (((REG32(ADR_DAT_UART_DATA)) & 0x000000ff ) >> 0)
++#define GET_DAT_DATA_RDY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000001 ) >> 0)
++#define GET_DAT_THR_EMPTY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000002 ) >> 1)
++#define GET_DAT_RX_LINESTS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000004 ) >> 2)
++#define GET_DAT_MDM_STS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000008 ) >> 3)
++#define GET_DAT_DMA_RXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000040 ) >> 6)
++#define GET_DAT_DMA_TXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000080 ) >> 7)
++#define GET_DAT_FIFO_EN (((REG32(ADR_DAT_UART_FCR)) & 0x00000001 ) >> 0)
++#define GET_DAT_RXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000002 ) >> 1)
++#define GET_DAT_TXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000004 ) >> 2)
++#define GET_DAT_DMA_MODE (((REG32(ADR_DAT_UART_FCR)) & 0x00000008 ) >> 3)
++#define GET_DAT_EN_AUTO_RTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000010 ) >> 4)
++#define GET_DAT_EN_AUTO_CTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000020 ) >> 5)
++#define GET_DAT_RXFIFO_TRGLVL (((REG32(ADR_DAT_UART_FCR)) & 0x000000c0 ) >> 6)
++#define GET_DAT_WORD_LEN (((REG32(ADR_DAT_UART_LCR)) & 0x00000003 ) >> 0)
++#define GET_DAT_STOP_BIT (((REG32(ADR_DAT_UART_LCR)) & 0x00000004 ) >> 2)
++#define GET_DAT_PARITY_EN (((REG32(ADR_DAT_UART_LCR)) & 0x00000008 ) >> 3)
++#define GET_DAT_EVEN_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000010 ) >> 4)
++#define GET_DAT_FORCE_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000020 ) >> 5)
++#define GET_DAT_SET_BREAK (((REG32(ADR_DAT_UART_LCR)) & 0x00000040 ) >> 6)
++#define GET_DAT_DLAB (((REG32(ADR_DAT_UART_LCR)) & 0x00000080 ) >> 7)
++#define GET_DAT_DTR (((REG32(ADR_DAT_UART_MCR)) & 0x00000001 ) >> 0)
++#define GET_DAT_RTS (((REG32(ADR_DAT_UART_MCR)) & 0x00000002 ) >> 1)
++#define GET_DAT_OUT_1 (((REG32(ADR_DAT_UART_MCR)) & 0x00000004 ) >> 2)
++#define GET_DAT_OUT_2 (((REG32(ADR_DAT_UART_MCR)) & 0x00000008 ) >> 3)
++#define GET_DAT_LOOP_BACK (((REG32(ADR_DAT_UART_MCR)) & 0x00000010 ) >> 4)
++#define GET_DAT_DATA_RDY (((REG32(ADR_DAT_UART_LSR)) & 0x00000001 ) >> 0)
++#define GET_DAT_OVERRUN_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000002 ) >> 1)
++#define GET_DAT_PARITY_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000004 ) >> 2)
++#define GET_DAT_FRAMING_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000008 ) >> 3)
++#define GET_DAT_BREAK_INT (((REG32(ADR_DAT_UART_LSR)) & 0x00000010 ) >> 4)
++#define GET_DAT_THR_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000020 ) >> 5)
++#define GET_DAT_TX_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000040 ) >> 6)
++#define GET_DAT_FIFODATA_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000080 ) >> 7)
++#define GET_DAT_DELTA_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000001 ) >> 0)
++#define GET_DAT_DELTA_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000002 ) >> 1)
++#define GET_DAT_TRAILEDGE_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000004 ) >> 2)
++#define GET_DAT_DELTA_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000008 ) >> 3)
++#define GET_DAT_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000010 ) >> 4)
++#define GET_DAT_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000020 ) >> 5)
++#define GET_DAT_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000040 ) >> 6)
++#define GET_DAT_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000080 ) >> 7)
++#define GET_DAT_BRDC_DIV (((REG32(ADR_DAT_UART_SPR)) & 0x0000ffff ) >> 0)
++#define GET_DAT_RTHR_L (((REG32(ADR_DAT_UART_RTHR)) & 0x0000000f ) >> 0)
++#define GET_DAT_RTHR_H (((REG32(ADR_DAT_UART_RTHR)) & 0x000000f0 ) >> 4)
++#define GET_DAT_INT_IDCODE (((REG32(ADR_DAT_UART_ISR)) & 0x0000000f ) >> 0)
++#define GET_DAT_FIFOS_ENABLED (((REG32(ADR_DAT_UART_ISR)) & 0x000000c0 ) >> 6)
++#define GET_MASK_TOP (((REG32(ADR_INT_MASK)) & 0xffffffff ) >> 0)
++#define GET_INT_MODE (((REG32(ADR_INT_MODE)) & 0xffffffff ) >> 0)
++#define GET_IRQ_PHY_0 (((REG32(ADR_INT_IRQ_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_PHY_1 (((REG32(ADR_INT_IRQ_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_SDIO (((REG32(ADR_INT_IRQ_STS)) & 0x00000004 ) >> 2)
++#define GET_IRQ_BEACON_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000010 ) >> 4)
++#define GET_IRQ_PRE_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000020 ) >> 5)
++#define GET_IRQ_EDCA0_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000040 ) >> 6)
++#define GET_IRQ_EDCA1_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000080 ) >> 7)
++#define GET_IRQ_EDCA2_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000100 ) >> 8)
++#define GET_IRQ_EDCA3_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000200 ) >> 9)
++#define GET_IRQ_EDCA4_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000400 ) >> 10)
++#define GET_IRQ_BEACON_DTIM (((REG32(ADR_INT_IRQ_STS)) & 0x00001000 ) >> 12)
++#define GET_IRQ_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00002000 ) >> 13)
++#define GET_IRQ_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00004000 ) >> 14)
++#define GET_IRQ_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00008000 ) >> 15)
++#define GET_IRQ_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00010000 ) >> 16)
++#define GET_IRQ_FENCE_HIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00020000 ) >> 17)
++#define GET_IRQ_ILL_ADDR_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00040000 ) >> 18)
++#define GET_IRQ_MBOX (((REG32(ADR_INT_IRQ_STS)) & 0x00080000 ) >> 19)
++#define GET_IRQ_US_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x00100000 ) >> 20)
++#define GET_IRQ_US_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x00200000 ) >> 21)
++#define GET_IRQ_US_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x00400000 ) >> 22)
++#define GET_IRQ_US_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x00800000 ) >> 23)
++#define GET_IRQ_MS_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x01000000 ) >> 24)
++#define GET_IRQ_MS_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_MS_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_MS_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x08000000 ) >> 27)
++#define GET_IRQ_TX_LIMIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x10000000 ) >> 28)
++#define GET_IRQ_DMA0 (((REG32(ADR_INT_IRQ_STS)) & 0x20000000 ) >> 29)
++#define GET_IRQ_CO_DMA (((REG32(ADR_INT_IRQ_STS)) & 0x40000000 ) >> 30)
++#define GET_IRQ_PERI_GROUP (((REG32(ADR_INT_IRQ_STS)) & 0x80000000 ) >> 31)
++#define GET_FIQ_STATUS (((REG32(ADR_INT_FIQ_STS)) & 0xffffffff ) >> 0)
++#define GET_IRQ_RAW (((REG32(ADR_INT_IRQ_RAW)) & 0xffffffff ) >> 0)
++#define GET_FIQ_RAW (((REG32(ADR_INT_FIQ_RAW)) & 0xffffffff ) >> 0)
++#define GET_INT_PERI_MASK (((REG32(ADR_INT_PERI_MASK)) & 0xffffffff ) >> 0)
++#define GET_PERI_RTC (((REG32(ADR_INT_PERI_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_UART0_TX (((REG32(ADR_INT_PERI_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_UART0_RX (((REG32(ADR_INT_PERI_STS)) & 0x00000004 ) >> 2)
++#define GET_PERI_GPI_2 (((REG32(ADR_INT_PERI_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_SPI_IPC (((REG32(ADR_INT_PERI_STS)) & 0x00000010 ) >> 4)
++#define GET_PERI_GPI_1_0 (((REG32(ADR_INT_PERI_STS)) & 0x00000060 ) >> 5)
++#define GET_SCRT_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000080 ) >> 7)
++#define GET_MMU_ALC_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000100 ) >> 8)
++#define GET_MMU_RLS_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000200 ) >> 9)
++#define GET_ID_MNG_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000400 ) >> 10)
++#define GET_MBOX_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000800 ) >> 11)
++#define GET_MBOX_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00001000 ) >> 12)
++#define GET_MBOX_INT_3 (((REG32(ADR_INT_PERI_STS)) & 0x00002000 ) >> 13)
++#define GET_HCI_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00004000 ) >> 14)
++#define GET_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x00008000 ) >> 15)
++#define GET_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x00010000 ) >> 16)
++#define GET_ID_MNG_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00020000 ) >> 17)
++#define GET_DMN_NOHIT_INT (((REG32(ADR_INT_PERI_STS)) & 0x00040000 ) >> 18)
++#define GET_ID_THOLD_RX (((REG32(ADR_INT_PERI_STS)) & 0x00080000 ) >> 19)
++#define GET_ID_THOLD_TX (((REG32(ADR_INT_PERI_STS)) & 0x00100000 ) >> 20)
++#define GET_ID_DOUBLE_RLS (((REG32(ADR_INT_PERI_STS)) & 0x00200000 ) >> 21)
++#define GET_RX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00400000 ) >> 22)
++#define GET_TX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00800000 ) >> 23)
++#define GET_ALL_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x01000000 ) >> 24)
++#define GET_DMN_MCU_INT (((REG32(ADR_INT_PERI_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_DAT_UART_TX (((REG32(ADR_INT_PERI_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_DAT_UART_RX (((REG32(ADR_INT_PERI_STS)) & 0x08000000 ) >> 27)
++#define GET_DAT_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x10000000 ) >> 28)
++#define GET_DAT_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x20000000 ) >> 29)
++#define GET_ALR_ABT_NOCHG_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x40000000 ) >> 30)
++#define GET_TBLNEQ_MNGPKT_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x80000000 ) >> 31)
++#define GET_INTR_PERI_RAW (((REG32(ADR_INT_PERI_RAW)) & 0xffffffff ) >> 0)
++#define GET_INTR_GPI00_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x00000003 ) >> 0)
++#define GET_INTR_GPI01_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x0000000c ) >> 2)
++#define GET_SYS_RST_INT (((REG32(ADR_SYS_INT_FOR_HOST)) & 0x00000001 ) >> 0)
++#define GET_SPI_IPC_ADDR (((REG32(ADR_SPI_IPC)) & 0xffffffff ) >> 0)
++#define GET_SD_MASK_TOP (((REG32(ADR_SDIO_MASK)) & 0xffffffff ) >> 0)
++#define GET_IRQ_PHY_0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_PHY_1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_SDIO_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000004 ) >> 2)
++#define GET_IRQ_BEACON_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000010 ) >> 4)
++#define GET_IRQ_PRE_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000020 ) >> 5)
++#define GET_IRQ_EDCA0_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000040 ) >> 6)
++#define GET_IRQ_EDCA1_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000080 ) >> 7)
++#define GET_IRQ_EDCA2_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000100 ) >> 8)
++#define GET_IRQ_EDCA3_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000200 ) >> 9)
++#define GET_IRQ_EDCA4_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000400 ) >> 10)
++#define GET_IRQ_BEACON_DTIM_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00001000 ) >> 12)
++#define GET_IRQ_EDCA0_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00002000 ) >> 13)
++#define GET_IRQ_EDCA1_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00004000 ) >> 14)
++#define GET_IRQ_EDCA2_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00008000 ) >> 15)
++#define GET_IRQ_EDCA3_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00010000 ) >> 16)
++#define GET_IRQ_FENCE_HIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00020000 ) >> 17)
++#define GET_IRQ_ILL_ADDR_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00040000 ) >> 18)
++#define GET_IRQ_MBOX_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00080000 ) >> 19)
++#define GET_IRQ_US_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00100000 ) >> 20)
++#define GET_IRQ_US_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00200000 ) >> 21)
++#define GET_IRQ_US_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00400000 ) >> 22)
++#define GET_IRQ_US_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00800000 ) >> 23)
++#define GET_IRQ_MS_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x01000000 ) >> 24)
++#define GET_IRQ_MS_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_MS_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_MS_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x08000000 ) >> 27)
++#define GET_IRQ_TX_LIMIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x10000000 ) >> 28)
++#define GET_IRQ_DMA0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x20000000 ) >> 29)
++#define GET_IRQ_CO_DMA_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x40000000 ) >> 30)
++#define GET_IRQ_PERI_GROUP_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x80000000 ) >> 31)
++#define GET_INT_PERI_MASK_SD (((REG32(ADR_SD_PERI_MASK)) & 0xffffffff ) >> 0)
++#define GET_PERI_RTC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_UART0_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_UART0_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000004 ) >> 2)
++#define GET_PERI_GPI_SD_2 (((REG32(ADR_SD_PERI_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_SPI_IPC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000010 ) >> 4)
++#define GET_PERI_GPI_SD_1_0 (((REG32(ADR_SD_PERI_STS)) & 0x00000060 ) >> 5)
++#define GET_SCRT_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000080 ) >> 7)
++#define GET_MMU_ALC_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000100 ) >> 8)
++#define GET_MMU_RLS_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000200 ) >> 9)
++#define GET_ID_MNG_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000400 ) >> 10)
++#define GET_MBOX_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000800 ) >> 11)
++#define GET_MBOX_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00001000 ) >> 12)
++#define GET_MBOX_INT_3_SD (((REG32(ADR_SD_PERI_STS)) & 0x00002000 ) >> 13)
++#define GET_HCI_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00004000 ) >> 14)
++#define GET_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00008000 ) >> 15)
++#define GET_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x00010000 ) >> 16)
++#define GET_ID_MNG_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00020000 ) >> 17)
++#define GET_DMN_NOHIT_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00040000 ) >> 18)
++#define GET_ID_THOLD_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00080000 ) >> 19)
++#define GET_ID_THOLD_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00100000 ) >> 20)
++#define GET_ID_DOUBLE_RLS_SD (((REG32(ADR_SD_PERI_STS)) & 0x00200000 ) >> 21)
++#define GET_RX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00400000 ) >> 22)
++#define GET_TX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00800000 ) >> 23)
++#define GET_ALL_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x01000000 ) >> 24)
++#define GET_DMN_MCU_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_DAT_UART_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_DAT_UART_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x08000000 ) >> 27)
++#define GET_DAT_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x10000000 ) >> 28)
++#define GET_DAT_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x20000000 ) >> 29)
++#define GET_ALR_ABT_NOCHG_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x40000000 ) >> 30)
++#define GET_TBLNEQ_MNGPKT_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x80000000 ) >> 31)
++#define GET_DBG_SPI_MODE (((REG32(ADR_DBG_SPI_MODE)) & 0xffffffff ) >> 0)
++#define GET_DBG_RX_QUOTA (((REG32(ADR_DBG_RX_QUOTA)) & 0x0000ffff ) >> 0)
++#define GET_DBG_CONDI_NUM (((REG32(ADR_DBG_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
++#define GET_DBG_HOST_PATH (((REG32(ADR_DBG_HOST_PATH)) & 0x00000001 ) >> 0)
++#define GET_DBG_TX_SEG (((REG32(ADR_DBG_TX_SEG)) & 0xffffffff ) >> 0)
++#define GET_DBG_BRST_MODE (((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
++#define GET_DBG_CLK_WIDTH (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
++#define GET_DBG_CSN_INTER (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
++#define GET_DBG_BACK_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
++#define GET_DBG_FRONT_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
++#define GET_DBG_RX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000002 ) >> 1)
++#define GET_DBG_RX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000004 ) >> 2)
++#define GET_DBG_TX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000008 ) >> 3)
++#define GET_DBG_TX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000010 ) >> 4)
++#define GET_DBG_SPI_DOUBLE_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000020 ) >> 5)
++#define GET_DBG_SPI_TX_NO_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000040 ) >> 6)
++#define GET_DBG_RDATA_RDY (((REG32(ADR_DBG_SPI_STS)) & 0x00000080 ) >> 7)
++#define GET_DBG_SPI_ALLOC_STATUS (((REG32(ADR_DBG_SPI_STS)) & 0x00000100 ) >> 8)
++#define GET_DBG_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_DBG_SPI_STS)) & 0x00000200 ) >> 9)
++#define GET_DBG_RX_LEN (((REG32(ADR_DBG_SPI_STS)) & 0xffff0000 ) >> 16)
++#define GET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
++#define GET_DBG_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
++#define GET_DBG_SPI_TX_ALLOC_SIZE (((REG32(ADR_DBG_TX_ALLOC)) & 0x000000ff ) >> 0)
++#define GET_DBG_RD_DAT_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff ) >> 0)
++#define GET_DBG_RD_STS_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000 ) >> 16)
++#define GET_DBG_JUDGE_CNT (((REG32(ADR_DBG_DBG_CNT2)) & 0x0000ffff ) >> 0)
++#define GET_DBG_RD_STS_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00010000 ) >> 16)
++#define GET_DBG_RD_DAT_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00020000 ) >> 17)
++#define GET_DBG_JUDGE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00040000 ) >> 18)
++#define GET_DBG_TX_DONE_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff ) >> 0)
++#define GET_DBG_TX_DISCARD_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000 ) >> 16)
++#define GET_DBG_TX_SET_CNT (((REG32(ADR_DBG_DBG_CNT4)) & 0x0000ffff ) >> 0)
++#define GET_DBG_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00010000 ) >> 16)
++#define GET_DBG_TX_DONE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00020000 ) >> 17)
++#define GET_DBG_TX_SET_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00040000 ) >> 18)
++#define GET_DBG_DAT_MODE_OFF (((REG32(ADR_DBG_DBG_CNT4)) & 0x00080000 ) >> 19)
++#define GET_DBG_TX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x00700000 ) >> 20)
++#define GET_DBG_RX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x07000000 ) >> 24)
++#define GET_DBG_RX_RDY (((REG32(ADR_DBG_INT_TAG)) & 0x00000001 ) >> 0)
++#define GET_DBG_SDIO_SYS_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000004 ) >> 2)
++#define GET_DBG_EDCA0_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000008 ) >> 3)
++#define GET_DBG_EDCA1_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000010 ) >> 4)
++#define GET_DBG_EDCA2_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000020 ) >> 5)
++#define GET_DBG_EDCA3_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000040 ) >> 6)
++#define GET_DBG_TX_LIMIT_INT_IN (((REG32(ADR_DBG_INT_TAG)) & 0x00000080 ) >> 7)
++#define GET_DBG_SPI_FN1 (((REG32(ADR_DBG_INT_TAG)) & 0x00007f00 ) >> 8)
++#define GET_DBG_SPI_CLK_EN_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00008000 ) >> 15)
++#define GET_DBG_SPI_HOST_MASK (((REG32(ADR_DBG_INT_TAG)) & 0x00ff0000 ) >> 16)
++#define GET_BOOT_ADDR (((REG32(ADR_BOOT_ADDR)) & 0x00ffffff ) >> 0)
++#define GET_CHECK_SUM_FAIL (((REG32(ADR_BOOT_ADDR)) & 0x80000000 ) >> 31)
++#define GET_VERIFY_DATA (((REG32(ADR_VERIFY_DATA)) & 0xffffffff ) >> 0)
++#define GET_FLASH_ADDR (((REG32(ADR_FLASH_ADDR)) & 0x00ffffff ) >> 0)
++#define GET_FLASH_CMD_CLR (((REG32(ADR_FLASH_ADDR)) & 0x10000000 ) >> 28)
++#define GET_FLASH_DMA_CLR (((REG32(ADR_FLASH_ADDR)) & 0x20000000 ) >> 29)
++#define GET_DMA_EN (((REG32(ADR_FLASH_ADDR)) & 0x40000000 ) >> 30)
++#define GET_DMA_BUSY (((REG32(ADR_FLASH_ADDR)) & 0x80000000 ) >> 31)
++#define GET_SRAM_ADDR (((REG32(ADR_SRAM_ADDR)) & 0xffffffff ) >> 0)
++#define GET_FLASH_DMA_LEN (((REG32(ADR_LEN)) & 0xffffffff ) >> 0)
++#define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000ffff ) >> 0)
++#define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0xffff0000 ) >> 16)
++#define GET_FLASH_CLK_WIDTH (((REG32(ADR_SPI_PARAM2)) & 0x0000ffff ) >> 0)
++#define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00010000 ) >> 16)
++#define GET_FLS_REMAP (((REG32(ADR_SPI_PARAM2)) & 0x00020000 ) >> 17)
++#define GET_PBUS_SWP (((REG32(ADR_SPI_PARAM2)) & 0x00040000 ) >> 18)
++#define GET_BIT_MODE1 (((REG32(ADR_SPI_PARAM2)) & 0x00080000 ) >> 19)
++#define GET_BIT_MODE2 (((REG32(ADR_SPI_PARAM2)) & 0x00100000 ) >> 20)
++#define GET_BIT_MODE4 (((REG32(ADR_SPI_PARAM2)) & 0x00200000 ) >> 21)
++#define GET_BOOT_CHECK_SUM (((REG32(ADR_CHECK_SUM_RESULT)) & 0xffffffff ) >> 0)
++#define GET_CHECK_SUM_TAG (((REG32(ADR_CHECK_SUM_IN_FILE)) & 0xffffffff ) >> 0)
++#define GET_CMD_LEN (((REG32(ADR_COMMAND_LEN)) & 0x0000ffff ) >> 0)
++#define GET_CMD_ADDR (((REG32(ADR_COMMAND_ADDR)) & 0xffffffff ) >> 0)
++#define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
++#define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0)
++#define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0)
++#define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3)
++#define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4)
++#define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7)
++#define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8)
++#define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12)
++#define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13)
++#define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16)
++#define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0)
++#define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8)
++#define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31)
++#define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
++#define GET_SLEEP_WAKE_CNT (((REG32(ADR_PMU_0)) & 0x00ffffff ) >> 0)
++#define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_0)) & 0x07000000 ) >> 24)
++#define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_0)) & 0x08000000 ) >> 27)
++#define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_0)) & 0x70000000 ) >> 28)
++#define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_0)) & 0x80000000 ) >> 31)
++#define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_1)) & 0x000003ff ) >> 0)
++#define GET_RG_RTC_OSC_RES_SW (((REG32(ADR_PMU_1)) & 0x03ff0000 ) >> 16)
++#define GET_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_1)) & 0x80000000 ) >> 31)
++#define GET_RG_DCDC_MODE (((REG32(ADR_PMU_2)) & 0x00000001 ) >> 0)
++#define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_2)) & 0x00000010 ) >> 4)
++#define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_2)) & 0x00000100 ) >> 8)
++#define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_2)) & 0x00001000 ) >> 12)
++#define GET_RG_RTC_RDY_DEGLITCH_TIMER (((REG32(ADR_PMU_2)) & 0x00006000 ) >> 13)
++#define GET_RTC_CAL_ENA (((REG32(ADR_PMU_2)) & 0x00010000 ) >> 16)
++#define GET_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_3)) & 0x00000003 ) >> 0)
++#define GET_DIGI_TOP_POR_MASK (((REG32(ADR_PMU_3)) & 0x00000010 ) >> 4)
++#define GET_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_3)) & 0x00000100 ) >> 8)
++#define GET_RG_RTC_DUMMIES (((REG32(ADR_PMU_3)) & 0xffff0000 ) >> 16)
++#define GET_RTC_EN (((REG32(ADR_RTC_1)) & 0x00000001 ) >> 0)
++#define GET_RTC_SRC (((REG32(ADR_RTC_1)) & 0x00000002 ) >> 1)
++#define GET_RTC_TICK_CNT (((REG32(ADR_RTC_1)) & 0x7fff0000 ) >> 16)
++#define GET_RTC_INT_SEC_MASK (((REG32(ADR_RTC_2)) & 0x00000001 ) >> 0)
++#define GET_RTC_INT_ALARM_MASK (((REG32(ADR_RTC_2)) & 0x00000002 ) >> 1)
++#define GET_RTC_INT_SEC (((REG32(ADR_RTC_2)) & 0x00010000 ) >> 16)
++#define GET_RTC_INT_ALARM (((REG32(ADR_RTC_2)) & 0x00020000 ) >> 17)
++#define GET_RTC_SEC_START_CNT (((REG32(ADR_RTC_3W)) & 0xffffffff ) >> 0)
++#define GET_RTC_SEC_CNT (((REG32(ADR_RTC_3R)) & 0xffffffff ) >> 0)
++#define GET_RTC_SEC_ALARM_VALUE (((REG32(ADR_RTC_4)) & 0xffffffff ) >> 0)
++#define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
++#define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0)
++#define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0)
++#define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3)
++#define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4)
++#define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7)
++#define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8)
++#define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12)
++#define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13)
++#define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16)
++#define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0)
++#define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8)
++#define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31)
++#define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
++#define GET_TRAP_UNKNOWN_TYPE (((REG32(ADR_CONTROL)) & 0x00000001 ) >> 0)
++#define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1)
++#define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2)
++#define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3)
++#define GET_BYPASSS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4)
++#define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5)
++#define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6)
++#define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8)
++#define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12)
++#define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16)
++#define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20)
++#define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21)
++#define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22)
++#define GET_RX_GET_TX_QUEUE_EN (((REG32(ADR_CONTROL)) & 0x02000000 ) >> 25)
++#define GET_HCI_INQ_SEL (((REG32(ADR_CONTROL)) & 0x04000000 ) >> 26)
++#define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28)
++#define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_WAKE_MODE)) & 0x00000001 ) >> 0)
++#define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0)
++#define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16)
++#define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0)
++#define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THREASHOLD)) & 0xffff0000 ) >> 16)
++#define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0)
++#define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0)
++#define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0)
++#define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8)
++#define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16)
++#define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24)
++#define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0)
++#define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8)
++#define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
++#define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
++#define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
++#define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
++#define GET_TX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0xffffffff ) >> 0)
++#define GET_RX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0xffffffff ) >> 0)
++#define GET_HOST_CMD_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0x000000ff ) >> 0)
++#define GET_HOST_EVENT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0x000000ff ) >> 0)
++#define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0x000000ff ) >> 0)
++#define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0x000000ff ) >> 0)
++#define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0x000000ff ) >> 0)
++#define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0x000000ff ) >> 0)
++#define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0x000000ff ) >> 0)
++#define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0x000000ff ) >> 0)
++#define GET_HCI_STATE_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0)
++#define GET_HCI_ST_TIMEOUT_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0xffffffff ) >> 0)
++#define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0)
++#define GET_HCI_MONITOR_REG1 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0)
++#define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0)
++#define GET_HCI_TX_ALLOC_TIME_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0)
++#define GET_HCI_TX_ALLOC_TIME_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x0000ffff ) >> 0)
++#define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x00ff0000 ) >> 16)
++#define GET_HCI_TX_ALLOC_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0xffffffff ) >> 0)
++#define GET_HCI_TX_ALLOC_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x0000ffff ) >> 0)
++#define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ff0000 ) >> 16)
++#define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff000000 ) >> 24)
++#define GET_SDIO_TX_INVALID_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0xffffffff ) >> 0)
++#define GET_SDIO_TX_INVALID_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0x0000ffff ) >> 0)
++#define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0)
++#define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16)
++#define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0)
++#define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0)
++#define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1)
++#define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0)
++#define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0)
++#define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16)
++#define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0)
++#define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0)
++#define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0)
++#define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0)
++#define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0)
++#define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0)
++#define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0)
++#define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0)
++#define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16)
++#define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0)
++#define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16)
++#define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0)
++#define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0)
++#define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0)
++#define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2)
++#define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3)
++#define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4)
++#define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12)
++#define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16)
++#define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0)
++#define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0)
++#define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0)
++#define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0)
++#define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1)
++#define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0)
++#define GET_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16)
++#define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20)
++#define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28)
++#define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0)
++#define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16)
++#define GET_EFS_RDATA_0 (((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_0 (((REG32(ADR_EFUSE_WDATA_0)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_1 (((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_1 (((REG32(ADR_EFUSE_WDATA_1)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_2 (((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_2 (((REG32(ADR_EFUSE_WDATA_2)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_3 (((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_3 (((REG32(ADR_EFUSE_WDATA_3)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_4 (((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_4 (((REG32(ADR_EFUSE_WDATA_4)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_5 (((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_5 (((REG32(ADR_EFUSE_WDATA_5)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_6 (((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_6 (((REG32(ADR_EFUSE_WDATA_6)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_7 (((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_7 (((REG32(ADR_EFUSE_WDATA_7)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RD0_EN (((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD1_EN (((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD2_EN (((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD3_EN (((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD4_EN (((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD5_EN (((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD6_EN (((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD7_EN (((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RBUSY (((REG32(ADR_EFUSE_SPI_BUSY)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RDATA_0 (((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_1 (((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_2 (((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_3 (((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_4 (((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_5 (((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_6 (((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_7 (((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0xffffffff ) >> 0)
++#define GET_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000001 ) >> 0)
++#define GET_FORCE_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000002 ) >> 1)
++#define GET_SMS4_DESCRY_EN (((REG32(ADR_SMS4_CFG1)) & 0x00000010 ) >> 4)
++#define GET_DEC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000001 ) >> 0)
++#define GET_DEC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000002 ) >> 1)
++#define GET_ENC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000004 ) >> 2)
++#define GET_ENC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000008 ) >> 3)
++#define GET_KEY_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000010 ) >> 4)
++#define GET_SMS4_CBC_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000001 ) >> 0)
++#define GET_SMS4_CFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000002 ) >> 1)
++#define GET_SMS4_OFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000004 ) >> 2)
++#define GET_SMS4_START_TRIG (((REG32(ADR_SMS4_TRIG)) & 0x00000001 ) >> 0)
++#define GET_SMS4_BUSY (((REG32(ADR_SMS4_STATUS1)) & 0x00000001 ) >> 0)
++#define GET_SMS4_DONE (((REG32(ADR_SMS4_STATUS2)) & 0x00000001 ) >> 0)
++#define GET_SMS4_DATAIN_0 (((REG32(ADR_SMS4_DATA_IN0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAIN_1 (((REG32(ADR_SMS4_DATA_IN1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAIN_2 (((REG32(ADR_SMS4_DATA_IN2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAIN_3 (((REG32(ADR_SMS4_DATA_IN3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_0 (((REG32(ADR_SMS4_DATA_OUT0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_1 (((REG32(ADR_SMS4_DATA_OUT1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_2 (((REG32(ADR_SMS4_DATA_OUT2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_3 (((REG32(ADR_SMS4_DATA_OUT3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_0 (((REG32(ADR_SMS4_KEY_0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_1 (((REG32(ADR_SMS4_KEY_1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_2 (((REG32(ADR_SMS4_KEY_2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_3 (((REG32(ADR_SMS4_KEY_3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV0 (((REG32(ADR_SMS4_MODE_IV0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV1 (((REG32(ADR_SMS4_MODE_IV1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV2 (((REG32(ADR_SMS4_MODE_IV2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV3 (((REG32(ADR_SMS4_MODE_IV3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC0 (((REG32(ADR_SMS4_OFB_ENC0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC1 (((REG32(ADR_SMS4_OFB_ENC1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC2 (((REG32(ADR_SMS4_OFB_ENC2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC3 (((REG32(ADR_SMS4_OFB_ENC3)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0)
++#define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0)
++#define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0)
++#define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0)
++#define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0)
++#define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0)
++#define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8)
++#define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0)
++#define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0)
++#define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0)
++#define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0)
++#define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0)
++#define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0)
++#define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8)
++#define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31)
++#define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31)
++#define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31)
++#define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0)
++#define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2)
++#define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3)
++#define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0)
++#define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0)
++#define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0)
++#define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0)
++#define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0)
++#define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0)
++#define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0)
++#define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0)
++#define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1)
++#define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0)
++#define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x003f0000 ) >> 16)
++#define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0)
++#define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0)
++#define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0)
++#define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0)
++#define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0)
++#define GET_W0_T0_SEQ (((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T1_SEQ (((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T2_SEQ (((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T3_SEQ (((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T4_SEQ (((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T5_SEQ (((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T6_SEQ (((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T7_SEQ (((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T0_SEQ (((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T1_SEQ (((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T2_SEQ (((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T3_SEQ (((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T4_SEQ (((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T5_SEQ (((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T6_SEQ (((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T7_SEQ (((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0)
++#define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2)
++#define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4)
++#define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6)
++#define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8)
++#define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10)
++#define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12)
++#define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0)
++#define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0)
++#define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0)
++#define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0)
++#define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0)
++#define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0)
++#define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16)
++#define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17)
++#define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18)
++#define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19)
++#define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20)
++#define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21)
++#define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22)
++#define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23)
++#define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24)
++#define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25)
++#define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16)
++#define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17)
++#define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18)
++#define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19)
++#define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20)
++#define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21)
++#define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22)
++#define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23)
++#define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24)
++#define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25)
++#define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0)
++#define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1)
++#define GET_MTX_AMPDU_CRC_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_MTX_FAST_RSP_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6)
++#define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7)
++#define GET_MTX_ACK_DUR0 (((REG32(ADR_MTX_MISC_EN)) & 0x00000100 ) >> 8)
++#define GET_MTX_TSF_AUTO_BCN (((REG32(ADR_MTX_MISC_EN)) & 0x00000400 ) >> 10)
++#define GET_MTX_TSF_AUTO_MISC (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11)
++#define GET_MTX_FORCE_CS_IDLE (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12)
++#define GET_MTX_FORCE_BKF_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13)
++#define GET_MTX_FORCE_DMA_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14)
++#define GET_MTX_FORCE_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15)
++#define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x003f0000 ) >> 16)
++#define GET_MTX_CTS_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00400000 ) >> 22)
++#define GET_MTX_AMPDU_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00800000 ) >> 23)
++#define GET_MTX_EDCCA_TOUT (((REG32(ADR_MTX_EDCCA_TOUT)) & 0x000003ff ) >> 0)
++#define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000002 ) >> 1)
++#define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000008 ) >> 3)
++#define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1)
++#define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3)
++#define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0)
++#define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1)
++#define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5)
++#define GET_MTX_HALT_MNG_UNTIL_DTIM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000040 ) >> 6)
++#define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_AUTO_FLUSH_Q4 (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16)
++#define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0)
++#define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1)
++#define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3)
++#define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16)
++#define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0)
++#define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_PRD)) & 0xff000000 ) >> 24)
++#define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0)
++#define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0)
++#define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x0000007f ) >> 0)
++#define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x03ff0000 ) >> 16)
++#define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x0000007f ) >> 0)
++#define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x03ff0000 ) >> 16)
++#define GET_MTX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000001 ) >> 0)
++#define GET_MRX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000002 ) >> 1)
++#define GET_MTX_DMA_FSM (((REG32(ADR_MTX_STATUS)) & 0x0000001c ) >> 2)
++#define GET_CH_ST_FSM (((REG32(ADR_MTX_STATUS)) & 0x000000e0 ) >> 5)
++#define GET_MTX_GNT_LOCK (((REG32(ADR_MTX_STATUS)) & 0x00000100 ) >> 8)
++#define GET_MTX_DMA_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000200 ) >> 9)
++#define GET_MTX_Q_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000400 ) >> 10)
++#define GET_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00000800 ) >> 11)
++#define GET_MRX_RX_EN (((REG32(ADR_MTX_STATUS)) & 0x00001000 ) >> 12)
++#define GET_DBG_PRTC_PRD (((REG32(ADR_MTX_STATUS)) & 0x00002000 ) >> 13)
++#define GET_DBG_DMA_RDY (((REG32(ADR_MTX_STATUS)) & 0x00004000 ) >> 14)
++#define GET_DBG_WAIT_RSP (((REG32(ADR_MTX_STATUS)) & 0x00008000 ) >> 15)
++#define GET_DBG_CFRM_BUSY (((REG32(ADR_MTX_STATUS)) & 0x00010000 ) >> 16)
++#define GET_DBG_RST (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000001 ) >> 0)
++#define GET_DBG_MODE (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000002 ) >> 1)
++#define GET_MB_REQ_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff ) >> 0)
++#define GET_RX_EN_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000 ) >> 16)
++#define GET_RX_CS_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff ) >> 0)
++#define GET_TX_CCA_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000 ) >> 16)
++#define GET_Q_REQ_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff ) >> 0)
++#define GET_CH_STA0_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000 ) >> 16)
++#define GET_MTX_DUR_RSP_TOUT_B (((REG32(ADR_MTX_DUR_TOUT)) & 0x000000ff ) >> 0)
++#define GET_MTX_DUR_RSP_TOUT_G (((REG32(ADR_MTX_DUR_TOUT)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_DUR_RSP_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x000000ff ) >> 0)
++#define GET_MTX_DUR_BURST_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_DUR_SLOT (((REG32(ADR_MTX_DUR_IFS)) & 0x003f0000 ) >> 16)
++#define GET_MTX_DUR_RSP_EIFS (((REG32(ADR_MTX_DUR_IFS)) & 0xffc00000 ) >> 22)
++#define GET_MTX_DUR_RSP_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x000000ff ) >> 0)
++#define GET_MTX_DUR_BURST_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_DUR_SLOT_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003f0000 ) >> 16)
++#define GET_MTX_DUR_RSP_EIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc00000 ) >> 22)
++#define GET_CH_STA1_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff ) >> 0)
++#define GET_CH_STA2_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000 ) >> 16)
++#define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0)
++#define GET_MTX_MIB_CNT0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x3fffffff ) >> 0)
++#define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30)
++#define GET_MTX_MIB_CNT1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x3fffffff ) >> 0)
++#define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30)
++#define GET_CH_STA3_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff ) >> 0)
++#define GET_CH_STA4_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000 ) >> 16)
++#define GET_TXQ0_MTX_Q_PRE_LD (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ0_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ0_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ0_MTX_Q_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ0_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ0_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ0_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ0_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ0_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ1_MTX_Q_PRE_LD (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ1_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ1_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ1_MTX_Q_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ1_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ1_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ1_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ1_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ1_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ2_MTX_Q_PRE_LD (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ2_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ2_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ2_MTX_Q_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ2_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ2_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ2_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ2_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ2_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ3_MTX_Q_PRE_LD (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ3_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ3_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ3_MTX_Q_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ3_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ3_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ3_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ3_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ3_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ4_MTX_Q_PRE_LD (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ4_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ4_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ4_MTX_Q_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ4_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ4_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ4_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ4_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ4_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0)
++#define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1)
++#define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2)
++#define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4)
++#define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0)
++#define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0)
++#define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0)
++#define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0)
++#define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1)
++#define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2)
++#define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4)
++#define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0)
++#define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0)
++#define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0)
++#define GET_INFO0 (((REG32(ADR_INFO0)) & 0xffffffff ) >> 0)
++#define GET_INFO1 (((REG32(ADR_INFO1)) & 0xffffffff ) >> 0)
++#define GET_INFO2 (((REG32(ADR_INFO2)) & 0xffffffff ) >> 0)
++#define GET_INFO3 (((REG32(ADR_INFO3)) & 0xffffffff ) >> 0)
++#define GET_INFO4 (((REG32(ADR_INFO4)) & 0xffffffff ) >> 0)
++#define GET_INFO5 (((REG32(ADR_INFO5)) & 0xffffffff ) >> 0)
++#define GET_INFO6 (((REG32(ADR_INFO6)) & 0xffffffff ) >> 0)
++#define GET_INFO7 (((REG32(ADR_INFO7)) & 0xffffffff ) >> 0)
++#define GET_INFO8 (((REG32(ADR_INFO8)) & 0xffffffff ) >> 0)
++#define GET_INFO9 (((REG32(ADR_INFO9)) & 0xffffffff ) >> 0)
++#define GET_INFO10 (((REG32(ADR_INFO10)) & 0xffffffff ) >> 0)
++#define GET_INFO11 (((REG32(ADR_INFO11)) & 0xffffffff ) >> 0)
++#define GET_INFO12 (((REG32(ADR_INFO12)) & 0xffffffff ) >> 0)
++#define GET_INFO13 (((REG32(ADR_INFO13)) & 0xffffffff ) >> 0)
++#define GET_INFO14 (((REG32(ADR_INFO14)) & 0xffffffff ) >> 0)
++#define GET_INFO15 (((REG32(ADR_INFO15)) & 0xffffffff ) >> 0)
++#define GET_INFO16 (((REG32(ADR_INFO16)) & 0xffffffff ) >> 0)
++#define GET_INFO17 (((REG32(ADR_INFO17)) & 0xffffffff ) >> 0)
++#define GET_INFO18 (((REG32(ADR_INFO18)) & 0xffffffff ) >> 0)
++#define GET_INFO19 (((REG32(ADR_INFO19)) & 0xffffffff ) >> 0)
++#define GET_INFO20 (((REG32(ADR_INFO20)) & 0xffffffff ) >> 0)
++#define GET_INFO21 (((REG32(ADR_INFO21)) & 0xffffffff ) >> 0)
++#define GET_INFO22 (((REG32(ADR_INFO22)) & 0xffffffff ) >> 0)
++#define GET_INFO23 (((REG32(ADR_INFO23)) & 0xffffffff ) >> 0)
++#define GET_INFO24 (((REG32(ADR_INFO24)) & 0xffffffff ) >> 0)
++#define GET_INFO25 (((REG32(ADR_INFO25)) & 0xffffffff ) >> 0)
++#define GET_INFO26 (((REG32(ADR_INFO26)) & 0xffffffff ) >> 0)
++#define GET_INFO27 (((REG32(ADR_INFO27)) & 0xffffffff ) >> 0)
++#define GET_INFO28 (((REG32(ADR_INFO28)) & 0xffffffff ) >> 0)
++#define GET_INFO29 (((REG32(ADR_INFO29)) & 0xffffffff ) >> 0)
++#define GET_INFO30 (((REG32(ADR_INFO30)) & 0xffffffff ) >> 0)
++#define GET_INFO31 (((REG32(ADR_INFO31)) & 0xffffffff ) >> 0)
++#define GET_INFO32 (((REG32(ADR_INFO32)) & 0xffffffff ) >> 0)
++#define GET_INFO33 (((REG32(ADR_INFO33)) & 0xffffffff ) >> 0)
++#define GET_INFO34 (((REG32(ADR_INFO34)) & 0xffffffff ) >> 0)
++#define GET_INFO35 (((REG32(ADR_INFO35)) & 0xffffffff ) >> 0)
++#define GET_INFO36 (((REG32(ADR_INFO36)) & 0xffffffff ) >> 0)
++#define GET_INFO37 (((REG32(ADR_INFO37)) & 0xffffffff ) >> 0)
++#define GET_INFO38 (((REG32(ADR_INFO38)) & 0xffffffff ) >> 0)
++#define GET_INFO_MASK (((REG32(ADR_INFO_MASK)) & 0xffffffff ) >> 0)
++#define GET_INFO_DEF_RATE (((REG32(ADR_INFO_RATE_OFFSET)) & 0x0000003f ) >> 0)
++#define GET_INFO_MRX_OFFSET (((REG32(ADR_INFO_RATE_OFFSET)) & 0x000f0000 ) >> 16)
++#define GET_BCAST_RATEUNKNOW (((REG32(ADR_INFO_RATE_OFFSET)) & 0x3f000000 ) >> 24)
++#define GET_INFO_IDX_TBL_ADDR (((REG32(ADR_INFO_IDX_ADDR)) & 0xffffffff ) >> 0)
++#define GET_INFO_LEN_TBL_ADDR (((REG32(ADR_INFO_LEN_ADDR)) & 0xffffffff ) >> 0)
++#define GET_IC_TAG_31_0 (((REG32(ADR_IC_TIME_TAG_0)) & 0xffffffff ) >> 0)
++#define GET_IC_TAG_63_32 (((REG32(ADR_IC_TIME_TAG_1)) & 0xffffffff ) >> 0)
++#define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0)
++#define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8)
++#define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16)
++#define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0)
++#define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1)
++#define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2)
++#define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3)
++#define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4)
++#define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5)
++#define GET_ASIC_TAG (((REG32(ADR_MAC_MODE)) & 0xff000000 ) >> 24)
++#define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0)
++#define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
++#define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
++#define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
++#define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
++#define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
++#define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
++#define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
++#define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12)
++#define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
++#define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
++#define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
++#define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
++#define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
++#define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
++#define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
++#define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
++#define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
++#define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16)
++#define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17)
++#define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
++#define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
++#define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
++#define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
++#define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
++#define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
++#define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10)
++#define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
++#define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
++#define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
++#define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
++#define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
++#define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
++#define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
++#define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
++#define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
++#define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
++#define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
++#define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
++#define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
++#define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
++#define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
++#define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
++#define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
++#define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
++#define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
++#define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
++#define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
++#define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
++#define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0)
++#define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2)
++#define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4)
++#define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8)
++#define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16)
++#define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17)
++#define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18)
++#define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21)
++#define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0)
++#define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0)
++#define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0)
++#define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0)
++#define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0)
++#define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0)
++#define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0)
++#define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0)
++#define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3)
++#define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6)
++#define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16)
++#define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0)
++#define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1)
++#define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4)
++#define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5)
++#define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8)
++#define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9)
++#define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10)
++#define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11)
++#define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12)
++#define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16)
++#define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17)
++#define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18)
++#define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19)
++#define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0)
++#define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8)
++#define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16)
++#define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24)
++#define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0)
++#define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1)
++#define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2)
++#define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3)
++#define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4)
++#define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5)
++#define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8)
++#define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9)
++#define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2)
++#define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3)
++#define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4)
++#define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5)
++#define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6)
++#define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7)
++#define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8)
++#define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9)
++#define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10)
++#define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11)
++#define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12)
++#define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13)
++#define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14)
++#define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15)
++#define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16)
++#define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17)
++#define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0)
++#define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0)
++#define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0)
++#define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0)
++#define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0)
++#define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0)
++#define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0)
++#define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0)
++#define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0)
++#define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0)
++#define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0)
++#define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0)
++#define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0)
++#define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0)
++#define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0)
++#define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0)
++#define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0)
++#define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0)
++#define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0)
++#define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0)
++#define GET_CBR_RG_EN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_TX_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_TX_PA_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_TX_DAC_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_RX_AGC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_RX_GAIN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_RFG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_CBR_RG_PGAG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
++#define GET_CBR_RG_MODE (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
++#define GET_CBR_RG_EN_TX_TRSW (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_EN_SX (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
++#define GET_CBR_RG_EN_RX_LNA (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_CBR_RG_EN_RX_MIXER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
++#define GET_CBR_RG_EN_RX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
++#define GET_CBR_RG_EN_RX_LOBUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
++#define GET_CBR_RG_EN_RX_TZ (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_EN_RX_FILTER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_EN_RX_HPF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_EN_RX_RSSI (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
++#define GET_CBR_RG_EN_ADC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
++#define GET_CBR_RG_EN_TX_MOD (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_EN_TX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
++#define GET_CBR_RG_EN_TX_DIV2_BUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
++#define GET_CBR_RG_EN_TX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
++#define GET_CBR_RG_EN_RX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
++#define GET_CBR_RG_SEL_DPLL_CLK (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
++#define GET_CBR_RG_EN_TX_DPD (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_EN_TX_TSSI (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_EN_RX_IQCAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_EN_TX_DAC_CAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_EN_TX_SELF_MIXER (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_EN_TX_DAC_OUT (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_EN_LDO_RX_FE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
++#define GET_CBR_RG_EN_LDO_ABB (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
++#define GET_CBR_RG_EN_LDO_AFE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_EN_SX_CHPLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_EN_SX_LOBFLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_EN_IREF_RX (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_DCDC_MODE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
++#define GET_CBR_RG_LDO_LEVEL_RX_FE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000007 ) >> 0)
++#define GET_CBR_RG_LDO_LEVEL_ABB (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000038 ) >> 3)
++#define GET_CBR_RG_LDO_LEVEL_AFE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
++#define GET_CBR_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
++#define GET_CBR_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00007000 ) >> 12)
++#define GET_CBR_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_CBR_RG_DP_LDO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_CBR_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
++#define GET_CBR_RG_TX_LDO_TX_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x07000000 ) >> 24)
++#define GET_CBR_RG_BUCK_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x38000000 ) >> 27)
++#define GET_CBR_RG_EN_RX_PADSW (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_EN_RX_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_RX_ABBCFIX (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_RX_ABBCTUNE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
++#define GET_CBR_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_RX_ABB_N_MODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_RX_EN_LOOPA (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_RX_FILTERI1ST (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
++#define GET_CBR_RG_RX_FILTERI2ND (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_FILTERI3RD (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
++#define GET_CBR_RG_RX_FILTERI_COURSE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
++#define GET_CBR_RG_RX_FILTERVCM (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
++#define GET_CBR_RG_RX_HPF3M (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_RX_HPF300K (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
++#define GET_CBR_RG_RX_HPFI (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
++#define GET_CBR_RG_RX_HPF_FINALCORNER (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
++#define GET_CBR_RG_RX_HPF_SETTLE1_C (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
++#define GET_CBR_RG_RX_HPF_SETTLE1_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_HPF_SETTLE2_C (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
++#define GET_CBR_RG_RX_HPF_SETTLE2_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_RX_HPF_VCMCON2 (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
++#define GET_CBR_RG_RX_HPF_VCMCON (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
++#define GET_CBR_RG_RX_OUTVCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
++#define GET_CBR_RG_RX_TZI (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
++#define GET_CBR_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_RX_TZ_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
++#define GET_CBR_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
++#define GET_CBR_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_RX_ADCRSSI_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
++#define GET_CBR_RG_RX_REC_LPFCORNER (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
++#define GET_CBR_RG_RSSI_CLOCK_GATING (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_TXPGA_CAPSW (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_TXPGA_MAIN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
++#define GET_CBR_RG_TXPGA_STEER (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
++#define GET_CBR_RG_TXMOD_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_TXLPF_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_CBR_RG_PACELL_EN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_CBR_RG_PABIAS_CTRL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
++#define GET_CBR_RG_PABIAS_AB (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_TX_DIV_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
++#define GET_CBR_RG_TX_LOBUF_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
++#define GET_CBR_RG_RX_SQDC (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
++#define GET_CBR_RG_RX_DIV2_CORE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_RX_LOBUF (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
++#define GET_CBR_RG_TX_DPDGM_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
++#define GET_CBR_RG_TX_DPD_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
++#define GET_CBR_RG_TX_TSSI_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
++#define GET_CBR_RG_TX_TSSI_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
++#define GET_CBR_RG_TX_TSSI_TESTMODE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_TX_TSSI_TEST (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
++#define GET_CBR_RG_RX_HG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_HG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_HG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_HG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_RX_MG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_MG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_MG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_MG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_RX_LG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_LG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_LG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_LG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_RX_ULG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_ULG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_ULG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_HPF1_FAST_SET_X (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_HPF1_FAST_SET_Y (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_HPF1_FAST_SET_Z (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_HPF_T1A (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_HPF_T1B (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000060 ) >> 5)
++#define GET_CBR_RG_HPF_T1C (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000180 ) >> 7)
++#define GET_CBR_RG_RX_LNA_TRI_SEL (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_CBR_RG_RX_LNA_SETTLE (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00001800 ) >> 11)
++#define GET_CBR_RG_ADC_CLKSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_ADC_DIBIAS (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_ADC_DIVR (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_ADC_DVCMI (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_ADC_SAMSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_ADC_STNBY (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_ADC_TESTMODE (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_ADC_TSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
++#define GET_CBR_RG_ADC_VRSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_CBR_RG_DICMP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_CBR_RG_DIOP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
++#define GET_CBR_RG_DACI1ST (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_TX_DACLPF_ICOURSE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
++#define GET_CBR_RG_TX_DACLPF_IFINE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_TX_DACLPF_VCM (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_CBR_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_TX_DAC_IBIAS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_CBR_RG_TX_DAC_OS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
++#define GET_CBR_RG_TX_DAC_RCAL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_TX_DAC_TSEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
++#define GET_CBR_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_TXLPF_BYPASS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_TXLPF_BOOSTI (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_EN_SX_R3 (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_EN_SX_CH (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_EN_SX_CHP (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_EN_SX_DIVCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_EN_SX_VCOBF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_EN_SX_VCO (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_EN_SX_MOD (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000040 ) >> 6)
++#define GET_CBR_RG_EN_SX_LCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000080 ) >> 7)
++#define GET_CBR_RG_EN_SX_DITHER (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_EN_SX_DELCAL (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_EN_SX_PC_BYPASS (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_EN_SX_VT_MON (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_EN_SX_VT_MON_DG (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00001000 ) >> 12)
++#define GET_CBR_RG_EN_SX_DIV (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00002000 ) >> 13)
++#define GET_CBR_RG_EN_SX_LPF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_SX_RFCTRL_F (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x00ffffff ) >> 0)
++#define GET_CBR_RG_SX_SEL_CP (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0f000000 ) >> 24)
++#define GET_CBR_RG_SX_SEL_CS (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0000000 ) >> 28)
++#define GET_CBR_RG_SX_RFCTRL_CH (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000007ff ) >> 0)
++#define GET_CBR_RG_SX_SEL_C3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x00007800 ) >> 11)
++#define GET_CBR_RG_SX_SEL_RS (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000f8000 ) >> 15)
++#define GET_CBR_RG_SX_SEL_R3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x01f00000 ) >> 20)
++#define GET_CBR_RG_SX_SEL_ICHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
++#define GET_CBR_RG_SX_SEL_PCHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
++#define GET_CBR_RG_SX_SEL_CHP_REGOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
++#define GET_CBR_RG_SX_CHP_IOST_POL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
++#define GET_CBR_RG_SX_CHP_IOST (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
++#define GET_CBR_RG_SX_PFDSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_SX_PFD_SET (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
++#define GET_CBR_RG_SX_PFD_SET1 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
++#define GET_CBR_RG_SX_PFD_SET2 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_SX_VBNCAS_SEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
++#define GET_CBR_RG_SX_PFD_RST_H (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
++#define GET_CBR_RG_SX_PFD_TRUP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
++#define GET_CBR_RG_SX_PFD_TRDN (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
++#define GET_CBR_RG_SX_PFD_TRSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
++#define GET_CBR_RG_SX_VCOBA_R (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
++#define GET_CBR_RG_SX_VCORSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
++#define GET_CBR_RG_SX_VCOCUSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
++#define GET_CBR_RG_SX_RXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
++#define GET_CBR_RG_SX_TXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
++#define GET_CBR_RG_SX_VCOBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
++#define GET_CBR_RG_SX_DIVBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
++#define GET_CBR_RG_SX_GNDR_SEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
++#define GET_CBR_RG_SX_DITHER_WEIGHT (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_SX_MOD_ERRCMP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0000000c ) >> 2)
++#define GET_CBR_RG_SX_MOD_ORDER (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_SX_SDM_D1 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000040 ) >> 6)
++#define GET_CBR_RG_SX_SDM_D2 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000080 ) >> 7)
++#define GET_CBR_RG_SDM_PASS (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_SX_RST_H_DIV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_SX_SDM_EDGE (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_SX_XO_GM (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
++#define GET_CBR_RG_SX_REFBYTWO (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
++#define GET_CBR_RG_SX_XO_SWCAP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0003c000 ) >> 14)
++#define GET_CBR_RG_SX_SDMLUT_INV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00040000 ) >> 18)
++#define GET_CBR_RG_SX_LCKEN (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
++#define GET_CBR_RG_SX_PREVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
++#define GET_CBR_RG_SX_PSCONTERVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
++#define GET_CBR_RG_SX_MOD_ERR_DELAY (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x30000000 ) >> 28)
++#define GET_CBR_RG_SX_MODDB (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x40000000 ) >> 30)
++#define GET_CBR_RG_SX_CV_CURVE_SEL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_SX_SEL_DELAY (((REG32(ADR_CBR_SYN_LCK1)) & 0x0000007c ) >> 2)
++#define GET_CBR_RG_SX_REF_CYCLE (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000780 ) >> 7)
++#define GET_CBR_RG_SX_VCOBY16 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_SX_VCOBY32 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00001000 ) >> 12)
++#define GET_CBR_RG_SX_PH (((REG32(ADR_CBR_SYN_LCK1)) & 0x00002000 ) >> 13)
++#define GET_CBR_RG_SX_PL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_SX_VT_MON_MODE (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_SX_VT_TH_HI (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_SX_VT_TH_LO (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_SX_VT_SET (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_SX_VT_MON_TMR (((REG32(ADR_CBR_SYN_LCK2)) & 0x00007fc0 ) >> 6)
++#define GET_CBR_RG_IDEAL_CYCLE (((REG32(ADR_CBR_SYN_LCK2)) & 0x0fff8000 ) >> 15)
++#define GET_CBR_RG_EN_DP_VT_MON (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_DP_VT_TH_HI (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_DP_VT_TH_LO (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_DP_VT_MON_TMR (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00003fe0 ) >> 5)
++#define GET_CBR_RG_DP_CK320BY2 (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_SX_DELCTRL (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x001f8000 ) >> 15)
++#define GET_CBR_RG_DP_OD_TEST (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_DP_BBPLL_BP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_DP_BBPLL_ICP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_DP_BBPLL_IDUAL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_DP_BBPLL_OD_TEST (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
++#define GET_CBR_RG_DP_BBPLL_PD (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_DP_BBPLL_TESTSEL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
++#define GET_CBR_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
++#define GET_CBR_RG_DP_RP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_CBR_RG_DP_RHP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_CBR_RG_DP_DR3 (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00700000 ) >> 20)
++#define GET_CBR_RG_DP_DCP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x07800000 ) >> 23)
++#define GET_CBR_RG_DP_DCS (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x78000000 ) >> 27)
++#define GET_CBR_RG_DP_FBDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x00000fff ) >> 0)
++#define GET_CBR_RG_DP_FODIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003ff000 ) >> 12)
++#define GET_CBR_RG_DP_REFDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00000 ) >> 22)
++#define GET_CBR_RG_IDACAI_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_EN_RCAL (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_RCAL_SPD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_RCAL_TMR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
++#define GET_CBR_RG_RCAL_CODE_CWR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_RCAL_CODE_CWD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
++#define GET_CBR_RG_SX_SUB_SEL_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_SX_SUB_SEL_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x000000fe ) >> 1)
++#define GET_CBR_RG_DP_BBPLL_BS_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_DP_BBPLL_BS_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00007e00 ) >> 9)
++#define GET_CBR_RCAL_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
++#define GET_CBR_DA_LCK_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
++#define GET_CBR_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
++#define GET_CBR_DP_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000008 ) >> 3)
++#define GET_CBR_CH_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000010 ) >> 4)
++#define GET_CBR_DA_R_CODE_LUT (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
++#define GET_CBR_AD_SX_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
++#define GET_CBR_AD_DP_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
++#define GET_CBR_DA_R_CAL_CODE (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
++#define GET_CBR_DA_SX_SUB_SEL (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
++#define GET_CBR_DA_DP_BBPLL_BS (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0003f000 ) >> 12)
++#define GET_CBR_TX_EN (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000001 ) >> 0)
++#define GET_CBR_TX_CNT_RST (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000002 ) >> 1)
++#define GET_CBR_IFS_TIME (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000000fc ) >> 2)
++#define GET_CBR_LENGTH_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000fff00 ) >> 8)
++#define GET_CBR_TX_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xff000000 ) >> 24)
++#define GET_CBR_TC_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0x00ffffff ) >> 0)
++#define GET_CBR_PLCP_PSDU_DATA_MEM (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x000000ff ) >> 0)
++#define GET_CBR_PLCP_PSDU_PREAMBLE_SHORT (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00000100 ) >> 8)
++#define GET_CBR_PLCP_BYTE_LENGTH (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x001ffe00 ) >> 9)
++#define GET_CBR_PLCP_PSDU_RATE (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00600000 ) >> 21)
++#define GET_CBR_TAIL_TIME (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x1f800000 ) >> 23)
++#define GET_CBR_RG_O_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_I_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000002 ) >> 1)
++#define GET_CBR_SEL_ADCKP_INV (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_PAD_DS (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000008 ) >> 3)
++#define GET_CBR_SEL_ADCKP_MUX (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_PAD_DS_CLK (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000020 ) >> 5)
++#define GET_CBR_INTP_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000200 ) >> 9)
++#define GET_CBR_IQ_SWP (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_EN_EXT_DA (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_DIS_DA_OFFSET (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00001000 ) >> 12)
++#define GET_CBR_DBG_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x000f0000 ) >> 16)
++#define GET_CBR_DBG_EN (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_PKT_GEN_TX_CNT (((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0xffffffff ) >> 0)
++#define GET_CBR_TP_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x0000001f ) >> 0)
++#define GET_CBR_IDEAL_IQ_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000020 ) >> 5)
++#define GET_CBR_DATA_OUT_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x000001c0 ) >> 6)
++#define GET_CBR_TWO_TONE_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000200 ) >> 9)
++#define GET_CBR_FREQ_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ff0000 ) >> 16)
++#define GET_CBR_IQ_SCALE (((REG32(ADR_CBR_PATTERN_GEN)) & 0xff000000 ) >> 24)
++#define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0)
++#define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2)
++#define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0)
++#define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0)
++#define GET_HW_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x000007ff ) >> 0)
++#define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0)
++#define GET_PRI_HW_PKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x000007ff ) >> 0)
++#define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0)
++#define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1)
++#define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9)
++#define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10)
++#define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11)
++#define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16)
++#define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24)
++#define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0)
++#define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5)
++#define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11)
++#define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17)
++#define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20)
++#define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23)
++#define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26)
++#define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29)
++#define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0)
++#define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3)
++#define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6)
++#define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000600 ) >> 9)
++#define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00001800 ) >> 11)
++#define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00006000 ) >> 13)
++#define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000f8000 ) >> 15)
++#define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00700000 ) >> 20)
++#define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1)
++#define GET_CH2_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2)
++#define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3)
++#define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4)
++#define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5)
++#define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6)
++#define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7)
++#define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8)
++#define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9)
++#define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10)
++#define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11)
++#define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12)
++#define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13)
++#define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14)
++#define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15)
++#define GET_HALT_CH0 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000001 ) >> 0)
++#define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1)
++#define GET_HALT_CH2 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000004 ) >> 2)
++#define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3)
++#define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4)
++#define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5)
++#define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6)
++#define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7)
++#define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8)
++#define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9)
++#define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10)
++#define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11)
++#define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12)
++#define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13)
++#define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14)
++#define GET_HALT_CH15 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00008000 ) >> 15)
++#define GET_STOP_MBOX (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16)
++#define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20)
++#define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21)
++#define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_CFG)) & 0xff000000 ) >> 24)
++#define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0)
++#define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16)
++#define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18)
++#define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19)
++#define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24)
++#define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31)
++#define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0)
++#define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16)
++#define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0)
++#define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0)
++#define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1)
++#define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2)
++#define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3)
++#define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4)
++#define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5)
++#define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6)
++#define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7)
++#define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8)
++#define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9)
++#define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10)
++#define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11)
++#define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12)
++#define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13)
++#define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14)
++#define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15)
++#define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16)
++#define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17)
++#define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18)
++#define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19)
++#define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20)
++#define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21)
++#define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22)
++#define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23)
++#define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24)
++#define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25)
++#define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26)
++#define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27)
++#define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28)
++#define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29)
++#define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30)
++#define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31)
++#define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1)
++#define GET_CH0_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000001 ) >> 0)
++#define GET_CH1_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000002 ) >> 1)
++#define GET_CH2_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000004 ) >> 2)
++#define GET_CH3_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000008 ) >> 3)
++#define GET_CH4_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000010 ) >> 4)
++#define GET_CH5_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000020 ) >> 5)
++#define GET_CH6_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000040 ) >> 6)
++#define GET_CH7_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000080 ) >> 7)
++#define GET_CH8_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000100 ) >> 8)
++#define GET_CH9_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000200 ) >> 9)
++#define GET_CH10_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000400 ) >> 10)
++#define GET_CH11_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000800 ) >> 11)
++#define GET_CH12_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00001000 ) >> 12)
++#define GET_CH13_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00002000 ) >> 13)
++#define GET_CH14_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00004000 ) >> 14)
++#define GET_CH15_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00008000 ) >> 15)
++#define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0)
++#define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5)
++#define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00000c00 ) >> 10)
++#define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15)
++#define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20)
++#define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25)
++#define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0)
++#define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5)
++#define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10)
++#define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15)
++#define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20)
++#define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25)
++#define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0)
++#define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5)
++#define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000c00 ) >> 10)
++#define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x001f8000 ) >> 15)
++#define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0)
++#define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1)
++#define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2)
++#define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3)
++#define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4)
++#define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5)
++#define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6)
++#define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7)
++#define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8)
++#define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9)
++#define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10)
++#define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11)
++#define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12)
++#define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13)
++#define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14)
++#define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15)
++#define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0)
++#define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1)
++#define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2)
++#define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3)
++#define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4)
++#define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5)
++#define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6)
++#define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7)
++#define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8)
++#define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9)
++#define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10)
++#define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11)
++#define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12)
++#define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13)
++#define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14)
++#define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15)
++#define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31)
++#define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0)
++#define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8)
++#define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16)
++#define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24)
++#define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0)
++#define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8)
++#define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16)
++#define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24)
++#define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0)
++#define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8)
++#define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16)
++#define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24)
++#define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0)
++#define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8)
++#define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16)
++#define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24)
++#define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0)
++#define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1)
++#define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4)
++#define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16)
++#define GET_CH0_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000001 ) >> 0)
++#define GET_CH1_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000002 ) >> 1)
++#define GET_CH2_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000004 ) >> 2)
++#define GET_CH3_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000008 ) >> 3)
++#define GET_CH4_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000010 ) >> 4)
++#define GET_CH5_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000020 ) >> 5)
++#define GET_CH6_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000040 ) >> 6)
++#define GET_CH7_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000080 ) >> 7)
++#define GET_CH8_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000100 ) >> 8)
++#define GET_CH9_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000200 ) >> 9)
++#define GET_CH10_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000400 ) >> 10)
++#define GET_CH11_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000800 ) >> 11)
++#define GET_CH12_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00001000 ) >> 12)
++#define GET_CH13_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00002000 ) >> 13)
++#define GET_CH14_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00004000 ) >> 14)
++#define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0)
++#define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0)
++#define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0)
++#define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0)
++#define GET_GPIO_STOP_EN (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000010 ) >> 4)
++#define GET_GPIO_STOP_POL (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000020 ) >> 5)
++#define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16)
++#define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0)
++#define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0)
++#define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0)
++#define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20)
++#define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0)
++#define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0)
++#define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4)
++#define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8)
++#define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12)
++#define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0)
++#define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0)
++#define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4)
++#define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5)
++#define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6)
++#define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7)
++#define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0)
++#define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1)
++#define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2)
++#define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4)
++#define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5)
++#define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6)
++#define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7)
++#define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8)
++#define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9)
++#define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0)
++#define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1)
++#define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2)
++#define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4)
++#define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5)
++#define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6)
++#define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7)
++#define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8)
++#define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16)
++#define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30)
++#define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31)
++#define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0)
++#define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8)
++#define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0)
++#define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8)
++#define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16)
++#define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17)
++#define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20)
++#define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21)
++#define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24)
++#define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0)
++#define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0)
++#define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0)
++#define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1)
++#define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8)
++#define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0)
++#define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1)
++#define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2)
++#define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3)
++#define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4)
++#define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13)
++#define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22)
++#define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9)
++#define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18)
++#define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0)
++#define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4)
++#define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8)
++#define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12)
++#define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16)
++#define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0)
++#define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8)
++#define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0)
++#define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0)
++#define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16)
++#define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30)
++#define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31)
++#define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0)
++#define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8)
++#define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14)
++#define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18)
++#define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22)
++#define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27)
++#define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0)
++#define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0)
++#define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0)
++#define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0)
++#define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9)
++#define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17)
++#define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9)
++#define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x03e00000 ) >> 21)
++#define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x3c000000 ) >> 26)
++#define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9)
++#define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17)
++#define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22)
++#define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0)
++#define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16)
++#define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0)
++#define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8)
++#define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16)
++#define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0)
++#define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9)
++#define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18)
++#define GET_RG_PMDLBK (((REG32(ADR_PHY_EN_0)) & 0x00000001 ) >> 0)
++#define GET_RG_RDYACK_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000006 ) >> 1)
++#define GET_RG_ADEDGE_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000008 ) >> 3)
++#define GET_RG_SIGN_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000010 ) >> 4)
++#define GET_RG_IQ_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000020 ) >> 5)
++#define GET_RG_Q_INV (((REG32(ADR_PHY_EN_0)) & 0x00000040 ) >> 6)
++#define GET_RG_I_INV (((REG32(ADR_PHY_EN_0)) & 0x00000080 ) >> 7)
++#define GET_RG_BYPASS_ACI (((REG32(ADR_PHY_EN_0)) & 0x00000100 ) >> 8)
++#define GET_RG_LBK_ANA_PATH (((REG32(ADR_PHY_EN_0)) & 0x00000200 ) >> 9)
++#define GET_RG_SPECTRUM_LEAKY_FACTOR (((REG32(ADR_PHY_EN_0)) & 0x00000c00 ) >> 10)
++#define GET_RG_SPECTRUM_BW (((REG32(ADR_PHY_EN_0)) & 0x00003000 ) >> 12)
++#define GET_RG_SPECTRUM_FREQ_MANUAL (((REG32(ADR_PHY_EN_0)) & 0x00004000 ) >> 14)
++#define GET_RG_SPECTRUM_EN (((REG32(ADR_PHY_EN_0)) & 0x00008000 ) >> 15)
++#define GET_RG_TXPWRLVL_SET (((REG32(ADR_PHY_EN_0)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TXPWRLVL_SEL (((REG32(ADR_PHY_EN_0)) & 0x01000000 ) >> 24)
++#define GET_RG_RF_BB_CLK_SEL (((REG32(ADR_PHY_EN_0)) & 0x80000000 ) >> 31)
++#define GET_RG_PHY_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000001 ) >> 0)
++#define GET_RG_PHYRX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000002 ) >> 1)
++#define GET_RG_PHYTX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000004 ) >> 2)
++#define GET_RG_PHY11GN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000008 ) >> 3)
++#define GET_RG_PHY11B_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000010 ) >> 4)
++#define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000020 ) >> 5)
++#define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000040 ) >> 6)
++#define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000100 ) >> 8)
++#define GET_RG_FORCE_11GN_EN (((REG32(ADR_PHY_EN_1)) & 0x00001000 ) >> 12)
++#define GET_RG_FORCE_11B_EN (((REG32(ADR_PHY_EN_1)) & 0x00002000 ) >> 13)
++#define GET_RG_FFT_MEM_CLK_EN_RX (((REG32(ADR_PHY_EN_1)) & 0x00004000 ) >> 14)
++#define GET_RG_FFT_MEM_CLK_EN_TX (((REG32(ADR_PHY_EN_1)) & 0x00008000 ) >> 15)
++#define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_PHY_EN_1)) & 0x000f0000 ) >> 16)
++#define GET_RG_SPECTRUM_FREQ (((REG32(ADR_PHY_EN_1)) & 0x3ff00000 ) >> 20)
++#define GET_SVN_VERSION (((REG32(ADR_SVN_VERSION_REG)) & 0xffffffff ) >> 0)
++#define GET_RG_LENGTH (((REG32(ADR_PHY_PKT_GEN_0)) & 0x0000ffff ) >> 0)
++#define GET_RG_PKT_MODE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00070000 ) >> 16)
++#define GET_RG_CH_BW (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00380000 ) >> 19)
++#define GET_RG_PRM (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00400000 ) >> 22)
++#define GET_RG_SHORTGI (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00800000 ) >> 23)
++#define GET_RG_RATE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x7f000000 ) >> 24)
++#define GET_RG_L_LENGTH (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00000fff ) >> 0)
++#define GET_RG_L_RATE (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00007000 ) >> 12)
++#define GET_RG_SERVICE (((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff0000 ) >> 16)
++#define GET_RG_SMOOTHING (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000001 ) >> 0)
++#define GET_RG_NO_SOUND (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000002 ) >> 1)
++#define GET_RG_AGGREGATE (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000004 ) >> 2)
++#define GET_RG_STBC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000018 ) >> 3)
++#define GET_RG_FEC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000020 ) >> 5)
++#define GET_RG_N_ESS (((REG32(ADR_PHY_PKT_GEN_2)) & 0x000000c0 ) >> 6)
++#define GET_RG_TXPWRLVL (((REG32(ADR_PHY_PKT_GEN_2)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TX_START (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000001 ) >> 0)
++#define GET_RG_IFS_TIME (((REG32(ADR_PHY_PKT_GEN_3)) & 0x000000fc ) >> 2)
++#define GET_RG_CONTINUOUS_DATA (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000100 ) >> 8)
++#define GET_RG_DATA_SEL (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000600 ) >> 9)
++#define GET_RG_TX_D (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TX_CNT_TARGET (((REG32(ADR_PHY_PKT_GEN_4)) & 0xffffffff ) >> 0)
++#define GET_RG_FFT_IFFT_MODE (((REG32(ADR_PHY_REG_00)) & 0x000000c0 ) >> 6)
++#define GET_RG_DAC_DBG_MODE (((REG32(ADR_PHY_REG_00)) & 0x00000100 ) >> 8)
++#define GET_RG_DAC_SGN_SWAP (((REG32(ADR_PHY_REG_00)) & 0x00000200 ) >> 9)
++#define GET_RG_TXD_SEL (((REG32(ADR_PHY_REG_00)) & 0x00000c00 ) >> 10)
++#define GET_RG_UP8X (((REG32(ADR_PHY_REG_00)) & 0x00ff0000 ) >> 16)
++#define GET_RG_IQ_DC_BYP (((REG32(ADR_PHY_REG_00)) & 0x01000000 ) >> 24)
++#define GET_RG_IQ_DC_LEAKY_FACTOR (((REG32(ADR_PHY_REG_00)) & 0x30000000 ) >> 28)
++#define GET_RG_DAC_DCEN (((REG32(ADR_PHY_REG_01)) & 0x00000001 ) >> 0)
++#define GET_RG_DAC_DCQ (((REG32(ADR_PHY_REG_01)) & 0x00003ff0 ) >> 4)
++#define GET_RG_DAC_DCI (((REG32(ADR_PHY_REG_01)) & 0x03ff0000 ) >> 16)
++#define GET_RG_PGA_REFDB_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0x0000007f ) >> 0)
++#define GET_RG_PGA_REFDB_TOP (((REG32(ADR_PHY_REG_02_AGC)) & 0x00007f00 ) >> 8)
++#define GET_RG_PGA_REF_UND (((REG32(ADR_PHY_REG_02_AGC)) & 0x03ff0000 ) >> 16)
++#define GET_RG_RF_REF_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0xf0000000 ) >> 28)
++#define GET_RG_PGAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x0000000f ) >> 0)
++#define GET_RG_PGAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000010 ) >> 4)
++#define GET_RG_RFGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000060 ) >> 5)
++#define GET_RG_RFGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000080 ) >> 7)
++#define GET_RG_WAIT_T_RXAGC (((REG32(ADR_PHY_REG_03_AGC)) & 0x00003f00 ) >> 8)
++#define GET_RG_RXAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00004000 ) >> 14)
++#define GET_RG_RXAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00008000 ) >> 15)
++#define GET_RG_WAIT_T_FINAL (((REG32(ADR_PHY_REG_03_AGC)) & 0x003f0000 ) >> 16)
++#define GET_RG_WAIT_T (((REG32(ADR_PHY_REG_03_AGC)) & 0x3f000000 ) >> 24)
++#define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000000f ) >> 0)
++#define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000000f0 ) >> 4)
++#define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00000f00 ) >> 8)
++#define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000f000 ) >> 12)
++#define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000f0000 ) >> 16)
++#define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00f00000 ) >> 20)
++#define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0f000000 ) >> 24)
++#define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0xf0000000 ) >> 28)
++#define GET_RG_MG_PGA_JB_TH (((REG32(ADR_PHY_REG_05_AGC)) & 0x0000000f ) >> 0)
++#define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x001f0000 ) >> 16)
++#define GET_RG_WR_RFGC_INIT_SET (((REG32(ADR_PHY_REG_05_AGC)) & 0x00600000 ) >> 21)
++#define GET_RG_WR_RFGC_INIT_EN (((REG32(ADR_PHY_REG_05_AGC)) & 0x00800000 ) >> 23)
++#define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x1f000000 ) >> 24)
++#define GET_RG_AGC_THRESHOLD (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x00003fff ) >> 0)
++#define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x007f0000 ) >> 16)
++#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x03000000 ) >> 24)
++#define GET_RG_WR_ACI_GAIN_INI_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x000000ff ) >> 0)
++#define GET_RG_WR_ACI_GAIN_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x0000ff00 ) >> 8)
++#define GET_RG_ACI_DAGC_SET_VALUE_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x007f0000 ) >> 16)
++#define GET_RG_WR_ACI_GAIN_OW_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x80000000 ) >> 31)
++#define GET_RG_ACI_POINT_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x000000ff ) >> 0)
++#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00000300 ) >> 8)
++#define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xff000000 ) >> 24)
++#define GET_RG_ACI_DAGC_SET_VALUE_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000007f ) >> 0)
++#define GET_RG_ACI_GAIN_INI_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000ff00 ) >> 8)
++#define GET_RG_ACI_GAIN_OW_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x00ff0000 ) >> 16)
++#define GET_RG_ACI_GAIN_OW_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x80000000 ) >> 31)
++#define GET_RO_CCA_PWR_MA_11GN (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x0000007f ) >> 0)
++#define GET_RO_ED_STATE (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x00008000 ) >> 15)
++#define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x007f0000 ) >> 16)
++#define GET_RO_PGA_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
++#define GET_RO_RF_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
++#define GET_RO_PGAGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
++#define GET_RO_RFGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
++#define GET_RO_PGA_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
++#define GET_RO_RF_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
++#define GET_RO_PGAGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
++#define GET_RO_RFGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
++#define GET_RO_PGA_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
++#define GET_RO_RF_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
++#define GET_RO_PGAGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
++#define GET_RO_RFGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
++#define GET_RG_TX_DES_RATE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x0000001f ) >> 0)
++#define GET_RG_TX_DES_MODE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x00001f00 ) >> 8)
++#define GET_RG_TX_DES_LEN_LO (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x001f0000 ) >> 16)
++#define GET_RG_TX_DES_LEN_UP (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x1f000000 ) >> 24)
++#define GET_RG_TX_DES_SRVC_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x0000001f ) >> 0)
++#define GET_RG_TX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x00001f00 ) >> 8)
++#define GET_RG_TX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x001f0000 ) >> 16)
++#define GET_RG_TX_DES_TYPE (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x1f000000 ) >> 24)
++#define GET_RG_TX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000001 ) >> 0)
++#define GET_RG_TX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000010 ) >> 4)
++#define GET_RG_TX_DES_RATE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000100 ) >> 8)
++#define GET_RG_TX_DES_MODE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00001000 ) >> 12)
++#define GET_RG_TX_DES_PWRLVL (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x001f0000 ) >> 16)
++#define GET_RG_TX_DES_SRVC_LO (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x1f000000 ) >> 24)
++#define GET_RG_RX_DES_RATE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x0000003f ) >> 0)
++#define GET_RG_RX_DES_MODE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x00003f00 ) >> 8)
++#define GET_RG_RX_DES_LEN_LO (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x003f0000 ) >> 16)
++#define GET_RG_RX_DES_LEN_UP (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x3f000000 ) >> 24)
++#define GET_RG_RX_DES_SRVC_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x0000003f ) >> 0)
++#define GET_RG_RX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x00003f00 ) >> 8)
++#define GET_RG_RX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x003f0000 ) >> 16)
++#define GET_RG_RX_DES_TYPE (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x3f000000 ) >> 24)
++#define GET_RG_RX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000001 ) >> 0)
++#define GET_RG_RX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000010 ) >> 4)
++#define GET_RG_RX_DES_RATE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000100 ) >> 8)
++#define GET_RG_RX_DES_MODE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00001000 ) >> 12)
++#define GET_RG_RX_DES_SNR (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x000f0000 ) >> 16)
++#define GET_RG_RX_DES_RCPI (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00f00000 ) >> 20)
++#define GET_RG_RX_DES_SRVC_LO (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x3f000000 ) >> 24)
++#define GET_RO_TX_DES_EXCP_RATE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x000000ff ) >> 0)
++#define GET_RO_TX_DES_EXCP_CH_BW_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x0000ff00 ) >> 8)
++#define GET_RO_TX_DES_EXCP_MODE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TX_DES_EXCP_RATE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x07000000 ) >> 24)
++#define GET_RG_TX_DES_EXCP_MODE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x70000000 ) >> 28)
++#define GET_RG_TX_DES_EXCP_CLR (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x80000000 ) >> 31)
++#define GET_RG_TX_DES_ACK_WIDTH (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x00000001 ) >> 0)
++#define GET_RG_TX_DES_ACK_PRD (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x0000000e ) >> 1)
++#define GET_RG_RX_DES_SNR_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x003f0000 ) >> 16)
++#define GET_RG_RX_DES_RCPI_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x3f000000 ) >> 24)
++#define GET_RG_TST_TBUS_SEL (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x0000000f ) >> 0)
++#define GET_RG_RSSI_OFFSET (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x00ff0000 ) >> 16)
++#define GET_RG_RSSI_INV (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x01000000 ) >> 24)
++#define GET_RG_TST_ADC_ON (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x40000000 ) >> 30)
++#define GET_RG_TST_EXT_GAIN (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x80000000 ) >> 31)
++#define GET_RG_DAC_Q_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x000003ff ) >> 0)
++#define GET_RG_DAC_I_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x003ff000 ) >> 12)
++#define GET_RG_DAC_EN_MAN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x10000000 ) >> 28)
++#define GET_RG_IQC_FFT_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x20000000 ) >> 29)
++#define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x40000000 ) >> 30)
++#define GET_RG_DAC_MAN_I_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x80000000 ) >> 31)
++#define GET_RO_MRX_EN_CNT (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_PA_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_RFTX_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_DAC_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ff0000 ) >> 16)
++#define GET_RG_SW_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff000000 ) >> 24)
++#define GET_RG_PA_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_RFTX_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_DAC_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ff0000 ) >> 16)
++#define GET_RG_SW_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff000000 ) >> 24)
++#define GET_RG_ANT_SW_0 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000007 ) >> 0)
++#define GET_RG_ANT_SW_1 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000038 ) >> 3)
++#define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MTX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MTX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MRX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MRX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff ) >> 0)
++#define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000 ) >> 16)
++#define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff ) >> 0)
++#define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000 ) >> 16)
++#define GET_RG_MODE_REG_IN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x0000ffff ) >> 0)
++#define GET_RG_PARALLEL_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x00100000 ) >> 20)
++#define GET_RG_MBRUN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x01000000 ) >> 24)
++#define GET_RG_SHIFT_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x10000000 ) >> 28)
++#define GET_RG_MODE_REG_SI_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x20000000 ) >> 29)
++#define GET_RG_SIMULATION_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x40000000 ) >> 30)
++#define GET_RG_DBIST_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x80000000 ) >> 31)
++#define GET_RO_MODE_REG_OUT_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x0000ffff ) >> 0)
++#define GET_RO_MODE_REG_SO_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x01000000 ) >> 24)
++#define GET_RO_MONITOR_BUS_16 (((REG32(ADR_PHY_READ_REG_07_BIST)) & 0x0007ffff ) >> 0)
++#define GET_RG_MRX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x000000ff ) >> 0)
++#define GET_RG_MRX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x0000ff00 ) >> 8)
++#define GET_RG_MTX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ff0000 ) >> 16)
++#define GET_RG_MTX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff000000 ) >> 24)
++#define GET_RO_MTX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff ) >> 0)
++#define GET_RO_MTX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000 ) >> 16)
++#define GET_RO_MRX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff ) >> 0)
++#define GET_RO_MRX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000 ) >> 16)
++#define GET_RG_HB_COEF0 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x00000fff ) >> 0)
++#define GET_RG_HB_COEF1 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
++#define GET_RG_HB_COEF2 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x00000fff ) >> 0)
++#define GET_RG_HB_COEF3 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
++#define GET_RG_HB_COEF4 (((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0x00000fff ) >> 0)
++#define GET_RO_TBUS_O (((REG32(ADR_PHY_READ_TBUS)) & 0x000fffff ) >> 0)
++#define GET_RG_LPF4_00 (((REG32(ADR_TX_11B_FIL_COEF_00)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_01 (((REG32(ADR_TX_11B_FIL_COEF_01)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_02 (((REG32(ADR_TX_11B_FIL_COEF_02)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_03 (((REG32(ADR_TX_11B_FIL_COEF_03)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_04 (((REG32(ADR_TX_11B_FIL_COEF_04)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_05 (((REG32(ADR_TX_11B_FIL_COEF_05)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_06 (((REG32(ADR_TX_11B_FIL_COEF_06)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_07 (((REG32(ADR_TX_11B_FIL_COEF_07)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_08 (((REG32(ADR_TX_11B_FIL_COEF_08)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_09 (((REG32(ADR_TX_11B_FIL_COEF_09)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_10 (((REG32(ADR_TX_11B_FIL_COEF_10)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_11 (((REG32(ADR_TX_11B_FIL_COEF_11)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_12 (((REG32(ADR_TX_11B_FIL_COEF_12)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_13 (((REG32(ADR_TX_11B_FIL_COEF_13)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_14 (((REG32(ADR_TX_11B_FIL_COEF_14)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_15 (((REG32(ADR_TX_11B_FIL_COEF_15)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_16 (((REG32(ADR_TX_11B_FIL_COEF_16)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_17 (((REG32(ADR_TX_11B_FIL_COEF_17)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_18 (((REG32(ADR_TX_11B_FIL_COEF_18)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_19 (((REG32(ADR_TX_11B_FIL_COEF_19)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_20 (((REG32(ADR_TX_11B_FIL_COEF_20)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_21 (((REG32(ADR_TX_11B_FIL_COEF_21)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_22 (((REG32(ADR_TX_11B_FIL_COEF_22)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_23 (((REG32(ADR_TX_11B_FIL_COEF_23)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_24 (((REG32(ADR_TX_11B_FIL_COEF_24)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_25 (((REG32(ADR_TX_11B_FIL_COEF_25)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_26 (((REG32(ADR_TX_11B_FIL_COEF_26)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_27 (((REG32(ADR_TX_11B_FIL_COEF_27)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_28 (((REG32(ADR_TX_11B_FIL_COEF_28)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_29 (((REG32(ADR_TX_11B_FIL_COEF_29)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_30 (((REG32(ADR_TX_11B_FIL_COEF_30)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_31 (((REG32(ADR_TX_11B_FIL_COEF_31)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_32 (((REG32(ADR_TX_11B_FIL_COEF_32)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_33 (((REG32(ADR_TX_11B_FIL_COEF_33)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_34 (((REG32(ADR_TX_11B_FIL_COEF_34)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_35 (((REG32(ADR_TX_11B_FIL_COEF_35)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_36 (((REG32(ADR_TX_11B_FIL_COEF_36)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_37 (((REG32(ADR_TX_11B_FIL_COEF_37)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_38 (((REG32(ADR_TX_11B_FIL_COEF_38)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_39 (((REG32(ADR_TX_11B_FIL_COEF_39)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_40 (((REG32(ADR_TX_11B_FIL_COEF_40)) & 0x00001fff ) >> 0)
++#define GET_RG_BP_SMB (((REG32(ADR_TX_11B_PLCP)) & 0x00002000 ) >> 13)
++#define GET_RG_EN_SRVC (((REG32(ADR_TX_11B_PLCP)) & 0x00004000 ) >> 14)
++#define GET_RG_DES_SPD (((REG32(ADR_TX_11B_PLCP)) & 0x00030000 ) >> 16)
++#define GET_RG_BB_11B_RISE_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_BB_11B_FALL_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_WR_TX_EN_CNT_RST_N (((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0x00000001 ) >> 0)
++#define GET_RO_TX_EN_CNT (((REG32(ADR_TX_11B_EN_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RO_TX_CNT (((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
++#define GET_RG_POS_DES_11B_L_EXT (((REG32(ADR_RX_11B_DES_DLY)) & 0x0000000f ) >> 0)
++#define GET_RG_PRE_DES_11B_DLY (((REG32(ADR_RX_11B_DES_DLY)) & 0x000000f0 ) >> 4)
++#define GET_RG_CNT_CCA_LMT (((REG32(ADR_RX_11B_CCA_0)) & 0x000f0000 ) >> 16)
++#define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_RX_11B_CCA_0)) & 0x20000000 ) >> 29)
++#define GET_RG_BYPASS_AGC (((REG32(ADR_RX_11B_CCA_0)) & 0x80000000 ) >> 31)
++#define GET_RG_CCA_BIT_CNT_LMT_RX (((REG32(ADR_RX_11B_CCA_1)) & 0x000000f0 ) >> 4)
++#define GET_RG_CCA_SCALE_BF (((REG32(ADR_RX_11B_CCA_1)) & 0x007f0000 ) >> 16)
++#define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_RX_11B_CCA_1)) & 0x30000000 ) >> 28)
++#define GET_RG_TR_KI_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000007 ) >> 0)
++#define GET_RG_TR_KP_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000070 ) >> 4)
++#define GET_RG_TR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000700 ) >> 8)
++#define GET_RG_TR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00007000 ) >> 12)
++#define GET_RG_CR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00070000 ) >> 16)
++#define GET_RG_CR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00700000 ) >> 20)
++#define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000001f ) >> 0)
++#define GET_RG_CE_T4_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000ff00 ) >> 8)
++#define GET_RG_CE_T3_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ff0000 ) >> 16)
++#define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff000000 ) >> 24)
++#define GET_RG_CE_MU_T1 (((REG32(ADR_RX_11B_CE_MU_0)) & 0x00000007 ) >> 0)
++#define GET_RG_CE_DLY_SEL (((REG32(ADR_RX_11B_CE_MU_0)) & 0x003f0000 ) >> 16)
++#define GET_RG_CE_MU_T8 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000007 ) >> 0)
++#define GET_RG_CE_MU_T7 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000070 ) >> 4)
++#define GET_RG_CE_MU_T6 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000700 ) >> 8)
++#define GET_RG_CE_MU_T5 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00007000 ) >> 12)
++#define GET_RG_CE_MU_T4 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00070000 ) >> 16)
++#define GET_RG_CE_MU_T3 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00700000 ) >> 20)
++#define GET_RG_CE_MU_T2 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x07000000 ) >> 24)
++#define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x0000000f ) >> 0)
++#define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000000f0 ) >> 4)
++#define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000f0000 ) >> 16)
++#define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x00f00000 ) >> 20)
++#define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x0000000f ) >> 0)
++#define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000000f0 ) >> 4)
++#define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000f0000 ) >> 16)
++#define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x00f00000 ) >> 20)
++#define GET_RG_EQ_KI_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00000700 ) >> 8)
++#define GET_RG_EQ_KP_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00007000 ) >> 12)
++#define GET_RG_EQ_KI_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00070000 ) >> 16)
++#define GET_RG_EQ_KP_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00700000 ) >> 20)
++#define GET_RG_TR_LPF_RATE (((REG32(ADR_RX_11B_LPF_RATE)) & 0x003fffff ) >> 0)
++#define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x0000007f ) >> 0)
++#define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00000080 ) >> 7)
++#define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00007f00 ) >> 8)
++#define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x007f0000 ) >> 16)
++#define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x7f000000 ) >> 24)
++#define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x00000001 ) >> 0)
++#define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x07ff0000 ) >> 16)
++#define GET_RG_PWRON_DLY_TH_11B (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x000000ff ) >> 0)
++#define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x00ff0000 ) >> 16)
++#define GET_RG_CCA_PWR_TH_RX (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x00007fff ) >> 0)
++#define GET_RG_CCA_PWR_CNT_TH (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x001f0000 ) >> 16)
++#define GET_B_FREQ_OS (((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0x000007ff ) >> 0)
++#define GET_B_SNR (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x0000007f ) >> 0)
++#define GET_B_RCPI (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x007f0000 ) >> 16)
++#define GET_CRC_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff ) >> 0)
++#define GET_SFD_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000 ) >> 16)
++#define GET_B_PACKET_ERR_CNT (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_PACKET_ERR (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x00010000 ) >> 16)
++#define GET_B_PACKET_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
++#define GET_B_CCA_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
++#define GET_B_LENGTH_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff ) >> 0)
++#define GET_SFD_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000 ) >> 16)
++#define GET_SIGNAL_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x000000ff ) >> 0)
++#define GET_B_SERVICE_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x0000ff00 ) >> 8)
++#define GET_CRC_CORRECT (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x00010000 ) >> 16)
++#define GET_DEBUG_SEL (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x0000000f ) >> 0)
++#define GET_RG_PACKET_STAT_EN_11B (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00100000 ) >> 20)
++#define GET_RG_BIT_REVERSE (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00200000 ) >> 21)
++#define GET_RX_PHY_11B_SOFT_RST_N (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000001 ) >> 0)
++#define GET_RG_CE_BYPASS_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x000000f0 ) >> 4)
++#define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000f00 ) >> 8)
++#define GET_RG_BB_11GN_RISE_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_BB_11GN_FALL_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_HTCARR52_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x000003ff ) >> 0)
++#define GET_RG_HTCARR56_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x003ff000 ) >> 12)
++#define GET_RG_PACKET_STAT_EN (((REG32(ADR_TX_11GN_PLCP)) & 0x00800000 ) >> 23)
++#define GET_RG_SMB_DEF (((REG32(ADR_TX_11GN_PLCP)) & 0x7f000000 ) >> 24)
++#define GET_RG_CONTINUOUS_DATA_11GN (((REG32(ADR_TX_11GN_PLCP)) & 0x80000000 ) >> 31)
++#define GET_RO_TX_CNT_R (((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
++#define GET_RO_PACKET_ERR_CNT (((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RG_POS_DES_11GN_L_EXT (((REG32(ADR_RX_11GN_DES_DLY)) & 0x0000000f ) >> 0)
++#define GET_RG_PRE_DES_11GN_DLY (((REG32(ADR_RX_11GN_DES_DLY)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_LPF_KI_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_KP_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_CNT_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TR_LPF_KI_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x000f0000 ) >> 16)
++#define GET_RG_TR_LPF_KP_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x00f00000 ) >> 20)
++#define GET_RG_TR_CNT_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0xff000000 ) >> 24)
++#define GET_RG_TR_LPF_KI_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_KP_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_CNT_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TR_LPF_KI_G (((REG32(ADR_RX_11GN_TR_2)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_KP_G (((REG32(ADR_RX_11GN_TR_2)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_LPF_RATE_G (((REG32(ADR_RX_11GN_TR_2)) & 0x3fffff00 ) >> 8)
++#define GET_RG_CR_LPF_KI_G (((REG32(ADR_RX_11GN_CCA_0)) & 0x00000007 ) >> 0)
++#define GET_RG_SYM_BOUND_CNT (((REG32(ADR_RX_11GN_CCA_0)) & 0x00007f00 ) >> 8)
++#define GET_RG_XSCOR32_RATIO (((REG32(ADR_RX_11GN_CCA_0)) & 0x007f0000 ) >> 16)
++#define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_RX_11GN_CCA_0)) & 0x7f000000 ) >> 24)
++#define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_1)) & 0x00007f00 ) >> 8)
++#define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_1)) & 0x007f0000 ) >> 16)
++#define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_RX_11GN_CCA_1)) & 0x7f000000 ) >> 24)
++#define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_2)) & 0x007f0000 ) >> 16)
++#define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_2)) & 0x7f000000 ) >> 24)
++#define GET_RG_RX_FFT_SCALE (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x000003ff ) >> 0)
++#define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x00010000 ) >> 16)
++#define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x0f000000 ) >> 24)
++#define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x000000ff ) >> 0)
++#define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ff0000 ) >> 16)
++#define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x000000ff ) >> 0)
++#define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x0000ff00 ) >> 8)
++#define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ff0000 ) >> 16)
++#define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x000000ff ) >> 0)
++#define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x0000ff00 ) >> 8)
++#define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ff0000 ) >> 16)
++#define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0xff000000 ) >> 24)
++#define GET_RG_SNR_TH_64QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x0000007f ) >> 0)
++#define GET_RG_SNR_TH_16QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x00007f00 ) >> 8)
++#define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x0000007f ) >> 0)
++#define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00007f00 ) >> 8)
++#define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00030000 ) >> 16)
++#define GET_RG_PWRON_DLY_TH_11GN (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x000000ff ) >> 0)
++#define GET_RG_SB_START_CNT (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x00007f00 ) >> 8)
++#define GET_RG_POW16_CNT_TH (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x000000f0 ) >> 4)
++#define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x00000700 ) >> 8)
++#define GET_RG_POW16_TH_L (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x7f000000 ) >> 24)
++#define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00000007 ) >> 0)
++#define GET_RG_XSCOR16_RATIO (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00007f00 ) >> 8)
++#define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00070000 ) >> 16)
++#define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x7f000000 ) >> 24)
++#define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x0000007f ) >> 0)
++#define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x00070000 ) >> 16)
++#define GET_RG_VITERBI_TB_BITS (((REG32(ADR_RX_11GN_VTB_TB)) & 0xff000000 ) >> 24)
++#define GET_RG_CR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x000000ff ) >> 0)
++#define GET_RG_TR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x00ff0000 ) >> 16)
++#define GET_RG_BYPASS_CPE_MA (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000010 ) >> 4)
++#define GET_RG_PILOT_BNDRY_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000700 ) >> 8)
++#define GET_RG_EQ_SHORT_GI_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00007000 ) >> 12)
++#define GET_RG_FFT_WDW_SHORT_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00070000 ) >> 16)
++#define GET_RG_CHSMTH_COEF (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00030000 ) >> 16)
++#define GET_RG_CHSMTH_EN (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00040000 ) >> 18)
++#define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x07000000 ) >> 24)
++#define GET_RG_CH_UPDATE (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x80000000 ) >> 31)
++#define GET_RG_FMT_DET_MM_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x000000ff ) >> 0)
++#define GET_RG_FMT_DET_GF_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x02000000 ) >> 25)
++#define GET_RG_FMT_DET_LENGTH_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff ) >> 0)
++#define GET_RG_L_LENGTH_MAX (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000 ) >> 16)
++#define GET_RG_TX_TIME_EXT (((REG32(ADR_RX_11GN_TX_TIME)) & 0x000000ff ) >> 0)
++#define GET_RG_MAC_DES_SPACE (((REG32(ADR_RX_11GN_TX_TIME)) & 0x00f00000 ) >> 20)
++#define GET_RG_TR_LPF_STBC_GF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_STBC_GF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_LPF_STBC_MF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x00000f00 ) >> 8)
++#define GET_RG_TR_LPF_STBC_MF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000f000 ) >> 12)
++#define GET_RG_MODE_REG_IN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x0001ffff ) >> 0)
++#define GET_RG_PARALLEL_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x00100000 ) >> 20)
++#define GET_RG_MBRUN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x01000000 ) >> 24)
++#define GET_RG_SHIFT_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x10000000 ) >> 28)
++#define GET_RG_MODE_REG_SI_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x20000000 ) >> 29)
++#define GET_RG_SIMULATION_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x40000000 ) >> 30)
++#define GET_RG_DBIST_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x80000000 ) >> 31)
++#define GET_RG_MODE_REG_IN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x0000ffff ) >> 0)
++#define GET_RG_PARALLEL_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x00100000 ) >> 20)
++#define GET_RG_MBRUN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x01000000 ) >> 24)
++#define GET_RG_SHIFT_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x10000000 ) >> 28)
++#define GET_RG_MODE_REG_SI_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x20000000 ) >> 29)
++#define GET_RG_SIMULATION_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x40000000 ) >> 30)
++#define GET_RG_DBIST_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x80000000 ) >> 31)
++#define GET_RO_MODE_REG_OUT_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x0001ffff ) >> 0)
++#define GET_RO_MODE_REG_SO_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x01000000 ) >> 24)
++#define GET_RO_MONITOR_BUS_80 (((REG32(ADR_RX_11GN_BIST_3)) & 0x003fffff ) >> 0)
++#define GET_RO_MODE_REG_OUT_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x0000ffff ) >> 0)
++#define GET_RO_MODE_REG_SO_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x01000000 ) >> 24)
++#define GET_RO_MONITOR_BUS_64 (((REG32(ADR_RX_11GN_BIST_5)) & 0x0007ffff ) >> 0)
++#define GET_RO_SPECTRUM_DATA (((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0xffffffff ) >> 0)
++#define GET_GN_SNR (((REG32(ADR_RX_11GN_READ_0)) & 0x0000007f ) >> 0)
++#define GET_GN_NOISE_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x00007f00 ) >> 8)
++#define GET_GN_RCPI (((REG32(ADR_RX_11GN_READ_0)) & 0x007f0000 ) >> 16)
++#define GET_GN_SIGNAL_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x7f000000 ) >> 24)
++#define GET_RO_FREQ_OS_LTS (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x00007fff ) >> 0)
++#define GET_CSTATE (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x000f0000 ) >> 16)
++#define GET_SIGNAL_FIELD0 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0x00ffffff ) >> 0)
++#define GET_SIGNAL_FIELD1 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0x00ffffff ) >> 0)
++#define GET_GN_PACKET_ERR_CNT (((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_GN_PACKET_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
++#define GET_GN_CCA_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
++#define GET_GN_LENGTH_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff ) >> 0)
++#define GET_GN_SERVICE_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000 ) >> 16)
++#define GET_RO_HT_MCS_40M (((REG32(ADR_RX_11GN_RATE)) & 0x0000007f ) >> 0)
++#define GET_RO_L_RATE_40M (((REG32(ADR_RX_11GN_RATE)) & 0x00003f00 ) >> 8)
++#define GET_RG_DAGC_CNT_TH (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00000003 ) >> 0)
++#define GET_RG_PACKET_STAT_EN_11GN (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00100000 ) >> 20)
++#define GET_RX_PHY_11GN_SOFT_RST_N (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000001 ) >> 0)
++#define GET_RG_RIFS_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000002 ) >> 1)
++#define GET_RG_STBC_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000004 ) >> 2)
++#define GET_RG_COR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000008 ) >> 3)
++#define GET_RG_INI_PHASE (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000030 ) >> 4)
++#define GET_RG_HT_LTF_SEL_EQ (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000040 ) >> 6)
++#define GET_RG_HT_LTF_SEL_PILOT (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000080 ) >> 7)
++#define GET_RG_CCA_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000200 ) >> 9)
++#define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000400 ) >> 10)
++#define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000800 ) >> 11)
++#define GET_RG_DEBUG_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x0000f000 ) >> 12)
++#define GET_RG_POST_CLK_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00010000 ) >> 16)
++#define GET_IQCAL_RF_TX_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000001 ) >> 0)
++#define GET_IQCAL_RF_TX_PA_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000002 ) >> 1)
++#define GET_IQCAL_RF_TX_DAC_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000004 ) >> 2)
++#define GET_IQCAL_RF_RX_AGC (((REG32(ADR_RF_CONTROL_0)) & 0x00000008 ) >> 3)
++#define GET_IQCAL_RF_PGAG (((REG32(ADR_RF_CONTROL_0)) & 0x00000f00 ) >> 8)
++#define GET_IQCAL_RF_RFG (((REG32(ADR_RF_CONTROL_0)) & 0x00003000 ) >> 12)
++#define GET_RG_TONEGEN_FREQ (((REG32(ADR_RF_CONTROL_0)) & 0x007f0000 ) >> 16)
++#define GET_RG_TONEGEN_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00800000 ) >> 23)
++#define GET_RG_TONEGEN_INIT_PH (((REG32(ADR_RF_CONTROL_0)) & 0x7f000000 ) >> 24)
++#define GET_RG_TONEGEN2_FREQ (((REG32(ADR_RF_CONTROL_1)) & 0x0000007f ) >> 0)
++#define GET_RG_TONEGEN2_EN (((REG32(ADR_RF_CONTROL_1)) & 0x00000080 ) >> 7)
++#define GET_RG_TONEGEN2_SCALE (((REG32(ADR_RF_CONTROL_1)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x000003ff ) >> 0)
++#define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x03ff0000 ) >> 16)
++#define GET_RG_TX_I_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x000000ff ) >> 0)
++#define GET_RG_TX_Q_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TX_IQ_SWP (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00010000 ) >> 16)
++#define GET_RG_TX_SGN_OUT (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00020000 ) >> 17)
++#define GET_RG_TXIQ_EMU_IDX (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x003c0000 ) >> 18)
++#define GET_RG_TX_IQ_SRC (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x03000000 ) >> 24)
++#define GET_RG_TX_I_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x000003ff ) >> 0)
++#define GET_RG_TX_Q_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x03ff0000 ) >> 16)
++#define GET_RG_TX_IQ_THETA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
++#define GET_RG_TX_IQ_ALPHA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
++#define GET_RG_TXIQ_NOSHRINK (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
++#define GET_RG_TX_I_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TX_Q_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff000000 ) >> 24)
++#define GET_RG_RX_IQ_THETA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
++#define GET_RG_RX_IQ_ALPHA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
++#define GET_RG_RXIQ_NOSHRINK (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
++#define GET_RG_MA_DPTH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x0000000f ) >> 0)
++#define GET_RG_INTG_PH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x000003f0 ) >> 4)
++#define GET_RG_INTG_PRD (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00001c00 ) >> 10)
++#define GET_RG_INTG_MU (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00006000 ) >> 13)
++#define GET_RG_IQCAL_SPRM_SELQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00010000 ) >> 16)
++#define GET_RG_IQCAL_SPRM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00020000 ) >> 17)
++#define GET_RG_IQCAL_SPRM_FREQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IQCAL_IQCOL_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x01000000 ) >> 24)
++#define GET_RG_IQCAL_ALPHA_ESTM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x02000000 ) >> 25)
++#define GET_RG_IQCAL_DC_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x04000000 ) >> 26)
++#define GET_RG_PHEST_STBY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x08000000 ) >> 27)
++#define GET_RG_PHEST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x10000000 ) >> 28)
++#define GET_RG_GP_DIV_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x20000000 ) >> 29)
++#define GET_RG_DPD_GAIN_EST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x40000000 ) >> 30)
++#define GET_RG_IQCAL_MULT_OP0 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x000003ff ) >> 0)
++#define GET_RG_IQCAL_MULT_OP1 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x03ff0000 ) >> 16)
++#define GET_RO_IQCAL_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x000fffff ) >> 0)
++#define GET_RO_IQCAL_SPRM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00100000 ) >> 20)
++#define GET_RO_IQCAL_IQCOL_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00200000 ) >> 21)
++#define GET_RO_IQCAL_ALPHA_ESTM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00400000 ) >> 22)
++#define GET_RO_IQCAL_DC_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00800000 ) >> 23)
++#define GET_RO_IQCAL_MULT_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x01000000 ) >> 24)
++#define GET_RO_FFT_ENRG_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x02000000 ) >> 25)
++#define GET_RO_PHEST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x04000000 ) >> 26)
++#define GET_RO_GP_DIV_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x08000000 ) >> 27)
++#define GET_RO_GAIN_EST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x10000000 ) >> 28)
++#define GET_RO_AMP_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0x000001ff ) >> 0)
++#define GET_RG_RX_I_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x000000ff ) >> 0)
++#define GET_RG_RX_Q_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_RX_I_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ff0000 ) >> 16)
++#define GET_RG_RX_Q_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff000000 ) >> 24)
++#define GET_RG_RX_IQ_SWP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000001 ) >> 0)
++#define GET_RG_RX_SGN_IN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000002 ) >> 1)
++#define GET_RG_RX_IQ_SRC (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x0000000c ) >> 2)
++#define GET_RG_ACI_GAIN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000ff0 ) >> 4)
++#define GET_RG_FFT_EN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00001000 ) >> 12)
++#define GET_RG_FFT_MOD (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00002000 ) >> 13)
++#define GET_RG_FFT_SCALE (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00ffc000 ) >> 14)
++#define GET_RG_FFT_ENRG_FREQ (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x3f000000 ) >> 24)
++#define GET_RG_FPGA_80M_PH_UP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x40000000 ) >> 30)
++#define GET_RG_FPGA_80M_PH_STP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x80000000 ) >> 31)
++#define GET_RG_ADC2LA_SEL (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000001 ) >> 0)
++#define GET_RG_ADC2LA_CLKPH (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000002 ) >> 1)
++#define GET_RG_RXIQ_EMU_IDX (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x0000000f ) >> 0)
++#define GET_RG_IQCAL_BP_ACI (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x00000010 ) >> 4)
++#define GET_RG_DPD_AM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000001 ) >> 0)
++#define GET_RG_DPD_PM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000002 ) >> 1)
++#define GET_RG_DPD_PM_AMSEL (((REG32(ADR_DPD_CONTROL)) & 0x00000004 ) >> 2)
++#define GET_RG_DPD_020_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_040_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_060_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_080_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_0A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_0C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_0D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_0E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_0F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_100_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_110_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_120_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_130_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_140_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_150_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_160_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_170_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_180_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_190_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_1A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_1B0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_1C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_1D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_1E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_1F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_200_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_020_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_040_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_060_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_080_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_0A0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_0C0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_0D0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_0E0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_0F0_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_100_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_110_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_120_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_130_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_140_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_150_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_160_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_170_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_180_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_190_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_1A0_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_1B0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_1C0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_1D0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_1E0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_1F0_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_200_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_GAIN_EST_Y0 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x000001ff ) >> 0)
++#define GET_RG_DPD_GAIN_EST_Y1 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x01ff0000 ) >> 16)
++#define GET_RG_DPD_LOOP_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_GAIN_EST_X0 (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x000001ff ) >> 0)
++#define GET_RO_DPD_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x03ff0000 ) >> 16)
++#define GET_TX_SCALE_11B (((REG32(ADR_TX_GAIN_FACTOR)) & 0x000000ff ) >> 0)
++#define GET_TX_SCALE_11B_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0x0000ff00 ) >> 8)
++#define GET_TX_SCALE_11G (((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ff0000 ) >> 16)
++#define GET_TX_SCALE_11G_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0xff000000 ) >> 24)
++#define GET_RG_EN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_TX_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_TX_PA_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_TX_DAC_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_RX_AGC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_RG_RFG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_RG_PGAG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
++#define GET_RG_MODE (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
++#define GET_RG_EN_TX_TRSW (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_EN_SX (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
++#define GET_RG_EN_RX_LNA (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_RG_EN_RX_MIXER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
++#define GET_RG_EN_RX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
++#define GET_RG_EN_RX_LOBUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
++#define GET_RG_EN_RX_TZ (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_RG_EN_RX_FILTER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_RG_EN_RX_HPF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_RG_EN_RX_RSSI (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
++#define GET_RG_EN_ADC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
++#define GET_RG_EN_TX_MOD (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
++#define GET_RG_EN_TX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
++#define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
++#define GET_RG_EN_TX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
++#define GET_RG_EN_RX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
++#define GET_RG_SEL_DPLL_CLK (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
++#define GET_RG_EN_CLK_960MBY13_UART (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x80000000 ) >> 31)
++#define GET_RG_EN_TX_DPD (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_EN_TX_TSSI (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_EN_RX_IQCAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_RG_EN_LDO_RX_FE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
++#define GET_RG_EN_LDO_ABB (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
++#define GET_RG_EN_LDO_AFE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_RG_EN_SX_CHPLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_RG_EN_SX_LOBFLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_RG_EN_IREF_RX (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
++#define GET_RG_EN_SX_LCK_BIN (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_RTC_CAL_MODE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_RG_EN_IQPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
++#define GET_RG_EN_TESTPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
++#define GET_RG_EN_TRXBF_BYPASS (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
++#define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_LDO_REGISTER)) & 0x00000007 ) >> 0)
++#define GET_RG_LDO_LEVEL_ABB (((REG32(ADR_LDO_REGISTER)) & 0x00000038 ) >> 3)
++#define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
++#define GET_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
++#define GET_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00007000 ) >> 12)
++#define GET_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_RG_DP_LDO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
++#define GET_RG_TX_LDO_TX_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x07000000 ) >> 24)
++#define GET_RG_EN_RX_PADSW (((REG32(ADR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
++#define GET_RG_EN_RX_TESTNODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
++#define GET_RG_RX_ABBCFIX (((REG32(ADR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
++#define GET_RG_RX_ABBCTUNE (((REG32(ADR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
++#define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
++#define GET_RG_RX_ABB_N_MODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
++#define GET_RG_RX_EN_LOOPA (((REG32(ADR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
++#define GET_RG_RX_FILTERI1ST (((REG32(ADR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
++#define GET_RG_RX_FILTERI2ND (((REG32(ADR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_FILTERI3RD (((REG32(ADR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
++#define GET_RG_RX_FILTERI_COURSE (((REG32(ADR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
++#define GET_RG_RX_FILTERVCM (((REG32(ADR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
++#define GET_RG_RX_HPF3M (((REG32(ADR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
++#define GET_RG_RX_HPF300K (((REG32(ADR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
++#define GET_RG_RX_HPFI (((REG32(ADR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
++#define GET_RG_RX_HPF_FINALCORNER (((REG32(ADR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
++#define GET_RG_RX_HPF_SETTLE1_C (((REG32(ADR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
++#define GET_RG_RX_HPF_SETTLE1_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_HPF_SETTLE2_C (((REG32(ADR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
++#define GET_RG_RX_HPF_SETTLE2_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
++#define GET_RG_RX_HPF_VCMCON2 (((REG32(ADR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
++#define GET_RG_RX_HPF_VCMCON (((REG32(ADR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
++#define GET_RG_RX_OUTVCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
++#define GET_RG_RX_TZI (((REG32(ADR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
++#define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
++#define GET_RG_RX_TZ_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
++#define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
++#define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
++#define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
++#define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
++#define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
++#define GET_RG_TXPGA_CAPSW (((REG32(ADR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_RG_TXPGA_MAIN (((REG32(ADR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
++#define GET_RG_TXPGA_STEER (((REG32(ADR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
++#define GET_RG_TXMOD_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_RG_TXLPF_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_RG_PACELL_EN (((REG32(ADR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_RG_PABIAS_CTRL (((REG32(ADR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
++#define GET_RG_TX_DIV_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
++#define GET_RG_TX_LOBUF_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
++#define GET_RG_RX_SQDC (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
++#define GET_RG_RX_DIV2_CORE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
++#define GET_RG_RX_LOBUF (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
++#define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
++#define GET_RG_TX_DPD_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
++#define GET_RG_TX_TSSI_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
++#define GET_RG_TX_TSSI_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
++#define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
++#define GET_RG_TX_TSSI_TEST (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
++#define GET_RG_PACASCODE_CTRL (((REG32(ADR_RX_FE_REGISTER_1)) & 0x07000000 ) >> 24)
++#define GET_RG_RX_HG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_HG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_HG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_HG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
++#define GET_RG_RX_MG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_MG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_MG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_MG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
++#define GET_RG_RX_LG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_LG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_LG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_LG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
++#define GET_RG_RX_ULG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_ULG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_ULG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
++#define GET_RG_HPF1_FAST_SET_X (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_HPF1_FAST_SET_Y (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_HPF1_FAST_SET_Z (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_HPF_T1A (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_RG_HPF_T1B (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000060 ) >> 5)
++#define GET_RG_HPF_T1C (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000180 ) >> 7)
++#define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_RG_RX_LNA_SETTLE (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00001800 ) >> 11)
++#define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00002000 ) >> 13)
++#define GET_RG_TX_GAIN (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x003fc000 ) >> 14)
++#define GET_RG_TXGAIN_MANUAL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_RG_TX_GAIN_OFFSET (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x07800000 ) >> 23)
++#define GET_RG_ADC_CLKSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_ADC_DIBIAS (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_RG_ADC_DIVR (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_ADC_DVCMI (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_RG_ADC_SAMSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
++#define GET_RG_ADC_STNBY (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_RG_ADC_TESTMODE (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_RG_ADC_TSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
++#define GET_RG_ADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_RG_DICMP (((REG32(ADR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_RG_DIOP (((REG32(ADR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
++#define GET_RG_SARADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00c00000 ) >> 22)
++#define GET_RG_EN_SAR_TEST (((REG32(ADR_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
++#define GET_RG_SARADC_THERMAL (((REG32(ADR_RX_ADC_REGISTER)) & 0x04000000 ) >> 26)
++#define GET_RG_SARADC_TSSI (((REG32(ADR_RX_ADC_REGISTER)) & 0x08000000 ) >> 27)
++#define GET_RG_CLK_SAR_SEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x30000000 ) >> 28)
++#define GET_RG_EN_SARADC (((REG32(ADR_RX_ADC_REGISTER)) & 0x40000000 ) >> 30)
++#define GET_RG_DACI1ST (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_RG_TX_DACLPF_ICOURSE (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
++#define GET_RG_TX_DACLPF_IFINE (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_RG_TX_DACLPF_VCM (((REG32(ADR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_RG_TX_DAC_IBIAS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_RG_TX_DAC_OS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
++#define GET_RG_TX_DAC_RCAL (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_RG_TX_DAC_TSEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
++#define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_RG_TXLPF_BYPASS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_RG_TXLPF_BOOSTI (((REG32(ADR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_RG_TX_DAC_IOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x07800000 ) >> 23)
++#define GET_RG_TX_DAC_QOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x78000000 ) >> 27)
++#define GET_RG_EN_SX_R3 (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_EN_SX_CH (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_EN_SX_CHP (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_EN_SX_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_EN_SX_VCOBF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_RG_EN_SX_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
++#define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_RG_EN_SX_VT_MON (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_RG_EN_SX_VT_MON_DG (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
++#define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
++#define GET_RG_EN_SX_LPF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_EN_DPL_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
++#define GET_RG_DPL_MOD_ORDER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_RG_SX_RFCTRL_F (((REG32(ADR_SYN_REGISTER_1)) & 0x00ffffff ) >> 0)
++#define GET_RG_SX_SEL_CP (((REG32(ADR_SYN_REGISTER_1)) & 0x0f000000 ) >> 24)
++#define GET_RG_SX_SEL_CS (((REG32(ADR_SYN_REGISTER_1)) & 0xf0000000 ) >> 28)
++#define GET_RG_SX_RFCTRL_CH (((REG32(ADR_SYN_REGISTER_2)) & 0x000007ff ) >> 0)
++#define GET_RG_SX_SEL_C3 (((REG32(ADR_SYN_REGISTER_2)) & 0x00007800 ) >> 11)
++#define GET_RG_SX_SEL_RS (((REG32(ADR_SYN_REGISTER_2)) & 0x000f8000 ) >> 15)
++#define GET_RG_SX_SEL_R3 (((REG32(ADR_SYN_REGISTER_2)) & 0x01f00000 ) >> 20)
++#define GET_RG_SX_SEL_ICHP (((REG32(ADR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
++#define GET_RG_SX_SEL_PCHP (((REG32(ADR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
++#define GET_RG_SX_SEL_CHP_REGOP (((REG32(ADR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
++#define GET_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
++#define GET_RG_SX_CHP_IOST_POL (((REG32(ADR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
++#define GET_RG_SX_CHP_IOST (((REG32(ADR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
++#define GET_RG_SX_PFDSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
++#define GET_RG_SX_PFD_SET (((REG32(ADR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
++#define GET_RG_SX_PFD_SET1 (((REG32(ADR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
++#define GET_RG_SX_PFD_SET2 (((REG32(ADR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
++#define GET_RG_SX_VBNCAS_SEL (((REG32(ADR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
++#define GET_RG_SX_PFD_RST_H (((REG32(ADR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
++#define GET_RG_SX_PFD_TRUP (((REG32(ADR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
++#define GET_RG_SX_PFD_TRDN (((REG32(ADR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
++#define GET_RG_SX_PFD_TRSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
++#define GET_RG_SX_VCOBA_R (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
++#define GET_RG_SX_VCORSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
++#define GET_RG_SX_VCOCUSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
++#define GET_RG_SX_RXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
++#define GET_RG_SX_TXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
++#define GET_RG_SX_VCOBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
++#define GET_RG_SX_DIVBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
++#define GET_RG_SX_GNDR_SEL (((REG32(ADR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
++#define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
++#define GET_RG_SX_MOD_ORDER (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
++#define GET_RG_SX_RST_H_DIV (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
++#define GET_RG_SX_SDM_EDGE (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
++#define GET_RG_SX_XO_GM (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
++#define GET_RG_SX_REFBYTWO (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
++#define GET_RG_SX_LCKEN (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
++#define GET_RG_SX_PREVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
++#define GET_RG_SX_PSCONTERVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
++#define GET_RG_SX_PH (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00002000 ) >> 13)
++#define GET_RG_SX_PL (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00004000 ) >> 14)
++#define GET_RG_XOSC_CBANK_XO (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00078000 ) >> 15)
++#define GET_RG_XOSC_CBANK_XI (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00780000 ) >> 19)
++#define GET_RG_SX_VT_MON_MODE (((REG32(ADR_SYN_LCK_VT)) & 0x00000001 ) >> 0)
++#define GET_RG_SX_VT_TH_HI (((REG32(ADR_SYN_LCK_VT)) & 0x00000006 ) >> 1)
++#define GET_RG_SX_VT_TH_LO (((REG32(ADR_SYN_LCK_VT)) & 0x00000018 ) >> 3)
++#define GET_RG_SX_VT_SET (((REG32(ADR_SYN_LCK_VT)) & 0x00000020 ) >> 5)
++#define GET_RG_SX_VT_MON_TMR (((REG32(ADR_SYN_LCK_VT)) & 0x00007fc0 ) >> 6)
++#define GET_RG_EN_DP_VT_MON (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_DP_VT_TH_HI (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_RG_DP_VT_TH_LO (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_RG_DP_CK320BY2 (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_DP_OD_TEST (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_RG_DP_BBPLL_BP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_DP_BBPLL_ICP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_RG_DP_BBPLL_OD_TEST (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
++#define GET_RG_DP_BBPLL_PD (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
++#define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
++#define GET_RG_DP_RP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_RG_DP_RHP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x80000000 ) >> 31)
++#define GET_RG_DP_FODIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x0007f000 ) >> 12)
++#define GET_RG_DP_REFDIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x1fc00000 ) >> 22)
++#define GET_RG_IDACAI_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
++#define GET_RG_DP_BBPLL_BS (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
++#define GET_RG_IDACAI_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
++#define GET_RG_EN_RCAL (((REG32(ADR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_RCAL_SPD (((REG32(ADR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_RCAL_TMR (((REG32(ADR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
++#define GET_RG_RCAL_CODE_CWR (((REG32(ADR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_RG_RCAL_CODE_CWD (((REG32(ADR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
++#define GET_RG_SX_SUB_SEL_CWR (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00000001 ) >> 0)
++#define GET_RG_SX_SUB_SEL_CWD (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x000000fe ) >> 1)
++#define GET_RG_SX_LCK_BIN_OFFSET (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00078000 ) >> 15)
++#define GET_RG_SX_LCK_BIN_PRECISION (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00080000 ) >> 19)
++#define GET_RG_SX_LOCK_EN_N (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00100000 ) >> 20)
++#define GET_RG_SX_LOCK_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00200000 ) >> 21)
++#define GET_RG_SX_SUB_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00400000 ) >> 22)
++#define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x3f800000 ) >> 23)
++#define GET_RG_SX_MUX_SEL_VTH_BINL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x40000000 ) >> 30)
++#define GET_RG_TRX_DUMMMY (((REG32(ADR_TRX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
++#define GET_RG_SX_DUMMMY (((REG32(ADR_SX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
++#define GET_RCAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
++#define GET_LCK_BIN_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
++#define GET_VT_MON_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
++#define GET_DA_R_CODE_LUT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
++#define GET_AD_SX_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
++#define GET_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
++#define GET_RTC_CAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00008000 ) >> 15)
++#define GET_RG_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x003f0000 ) >> 16)
++#define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00400000 ) >> 22)
++#define GET_AD_CIRCUIT_VERSION (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x07800000 ) >> 23)
++#define GET_DA_R_CAL_CODE (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
++#define GET_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
++#define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x000007ff ) >> 0)
++#define GET_RG_RSSIADC_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x00007800 ) >> 11)
++#define GET_RG_RX_ADC_I_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x007f8000 ) >> 15)
++#define GET_RG_RX_ADC_Q_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x7f800000 ) >> 23)
++#define GET_RG_DPL_RFCTRL_F (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0x00ffffff ) >> 0)
++#define GET_RG_SX_TARGET_CNT (((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0x00001fff ) >> 0)
++#define GET_RG_RTC_OFFSET (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000000ff ) >> 0)
++#define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000fff00 ) >> 8)
++#define GET_RG_RF_D_REG (((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0x0000ffff ) >> 0)
++#define GET_DIRECT_MODE (((REG32(ADR_MMU_CTRL)) & 0x00000001 ) >> 0)
++#define GET_TAG_INTERLEAVE_MD (((REG32(ADR_MMU_CTRL)) & 0x00000002 ) >> 1)
++#define GET_DIS_DEMAND (((REG32(ADR_MMU_CTRL)) & 0x00000004 ) >> 2)
++#define GET_SAME_ID_ALLOC_MD (((REG32(ADR_MMU_CTRL)) & 0x00000008 ) >> 3)
++#define GET_HS_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000010 ) >> 4)
++#define GET_SRAM_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000020 ) >> 5)
++#define GET_NOHIT_RPASS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000040 ) >> 6)
++#define GET_DMN_FLAG_CLR (((REG32(ADR_MMU_CTRL)) & 0x00000080 ) >> 7)
++#define GET_ERR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000100 ) >> 8)
++#define GET_ALR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000200 ) >> 9)
++#define GET_MCH_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000400 ) >> 10)
++#define GET_TAG_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000800 ) >> 11)
++#define GET_ABT_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00001000 ) >> 12)
++#define GET_MMU_VER (((REG32(ADR_MMU_CTRL)) & 0x0000e000 ) >> 13)
++#define GET_MMU_SHARE_MCU (((REG32(ADR_MMU_CTRL)) & 0x00ff0000 ) >> 16)
++#define GET_HS_WR (((REG32(ADR_HS_CTRL)) & 0x00000001 ) >> 0)
++#define GET_HS_FLAG (((REG32(ADR_HS_CTRL)) & 0x00000010 ) >> 4)
++#define GET_HS_ID (((REG32(ADR_HS_CTRL)) & 0x00007f00 ) >> 8)
++#define GET_HS_CHANNEL (((REG32(ADR_HS_CTRL)) & 0x000f0000 ) >> 16)
++#define GET_HS_PAGE (((REG32(ADR_HS_CTRL)) & 0x00f00000 ) >> 20)
++#define GET_HS_DATA (((REG32(ADR_HS_CTRL)) & 0xff000000 ) >> 24)
++#define GET_CPU_POR0 (((REG32(ADR_CPU_POR0_7)) & 0x0000000f ) >> 0)
++#define GET_CPU_POR1 (((REG32(ADR_CPU_POR0_7)) & 0x000000f0 ) >> 4)
++#define GET_CPU_POR2 (((REG32(ADR_CPU_POR0_7)) & 0x00000f00 ) >> 8)
++#define GET_CPU_POR3 (((REG32(ADR_CPU_POR0_7)) & 0x0000f000 ) >> 12)
++#define GET_CPU_POR4 (((REG32(ADR_CPU_POR0_7)) & 0x000f0000 ) >> 16)
++#define GET_CPU_POR5 (((REG32(ADR_CPU_POR0_7)) & 0x00f00000 ) >> 20)
++#define GET_CPU_POR6 (((REG32(ADR_CPU_POR0_7)) & 0x0f000000 ) >> 24)
++#define GET_CPU_POR7 (((REG32(ADR_CPU_POR0_7)) & 0xf0000000 ) >> 28)
++#define GET_CPU_POR8 (((REG32(ADR_CPU_POR8_F)) & 0x0000000f ) >> 0)
++#define GET_CPU_POR9 (((REG32(ADR_CPU_POR8_F)) & 0x000000f0 ) >> 4)
++#define GET_CPU_PORA (((REG32(ADR_CPU_POR8_F)) & 0x00000f00 ) >> 8)
++#define GET_CPU_PORB (((REG32(ADR_CPU_POR8_F)) & 0x0000f000 ) >> 12)
++#define GET_CPU_PORC (((REG32(ADR_CPU_POR8_F)) & 0x000f0000 ) >> 16)
++#define GET_CPU_PORD (((REG32(ADR_CPU_POR8_F)) & 0x00f00000 ) >> 20)
++#define GET_CPU_PORE (((REG32(ADR_CPU_POR8_F)) & 0x0f000000 ) >> 24)
++#define GET_CPU_PORF (((REG32(ADR_CPU_POR8_F)) & 0xf0000000 ) >> 28)
++#define GET_ACC_WR_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x0000003f ) >> 0)
++#define GET_ACC_RD_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x00003f00 ) >> 8)
++#define GET_REQ_NACK_CLR (((REG32(ADR_REG_LEN_CTRL)) & 0x00008000 ) >> 15)
++#define GET_NACK_FLAG_BUS (((REG32(ADR_REG_LEN_CTRL)) & 0xffff0000 ) >> 16)
++#define GET_DMN_R_PASS (((REG32(ADR_DMN_READ_BYPASS)) & 0x0000ffff ) >> 0)
++#define GET_PARA_ALC_RLS (((REG32(ADR_DMN_READ_BYPASS)) & 0x00010000 ) >> 16)
++#define GET_REQ_PORNS_CHGEN (((REG32(ADR_DMN_READ_BYPASS)) & 0x01000000 ) >> 24)
++#define GET_ALC_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x0000007f ) >> 0)
++#define GET_ALC_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x00008000 ) >> 15)
++#define GET_RLS_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x007f0000 ) >> 16)
++#define GET_RLS_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x80000000 ) >> 31)
++#define GET_DEBUG_CTL (((REG32(ADR_DEBUG_CTL)) & 0x000000ff ) >> 0)
++#define GET_DEBUG_H16 (((REG32(ADR_DEBUG_CTL)) & 0x00000100 ) >> 8)
++#define GET_DEBUG_OUT (((REG32(ADR_DEBUG_OUT)) & 0xffffffff ) >> 0)
++#define GET_ALC_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000001 ) >> 0)
++#define GET_RLS_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000002 ) >> 1)
++#define GET_AL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00000700 ) >> 8)
++#define GET_RL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00007000 ) >> 12)
++#define GET_ALC_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x007f0000 ) >> 16)
++#define GET_RLS_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x7f000000 ) >> 24)
++#define GET_DMN_NOHIT_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0)
++#define GET_DMN_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1)
++#define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000008 ) >> 3)
++#define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4)
++#define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8)
++#define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0xffff0000 ) >> 16)
++#define GET_TX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x000000ff ) >> 0)
++#define GET_RX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x0000ff00 ) >> 8)
++#define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x01ff0000 ) >> 16)
++#define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x80000000 ) >> 31)
++#define GET_DMN_NOHIT_MCU (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000001 ) >> 0)
++#define GET_DMN_MCU_FLAG (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000002 ) >> 1)
++#define GET_DMN_MCU_WR (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000008 ) >> 3)
++#define GET_DMN_MCU_PORT (((REG32(ADR_DMN_MCU_STATUS)) & 0x000000f0 ) >> 4)
++#define GET_DMN_MCU_ID (((REG32(ADR_DMN_MCU_STATUS)) & 0x00007f00 ) >> 8)
++#define GET_DMN_MCU_ADDR (((REG32(ADR_DMN_MCU_STATUS)) & 0xffff0000 ) >> 16)
++#define GET_MB_IDTBL_31_0 (((REG32(ADR_MB_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_MB_IDTBL_63_32 (((REG32(ADR_MB_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_MB_IDTBL_95_64 (((REG32(ADR_MB_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_MB_IDTBL_127_96 (((REG32(ADR_MB_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_31_0 (((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_63_32 (((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_95_64 (((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_127_96 (((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_31_0 (((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_63_32 (((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_95_64 (((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_127_96 (((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_31_0 (((REG32(ADR_MB_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_63_32 (((REG32(ADR_MB_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_95_64 (((REG32(ADR_MB_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_127_96 (((REG32(ADR_MB_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_31_0 (((REG32(ADR_PKT_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_63_32 (((REG32(ADR_PKT_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_95_64 (((REG32(ADR_PKT_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_127_96 (((REG32(ADR_PKT_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_ALC_NOCHG_ID (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x0000007f ) >> 0)
++#define GET_ALC_NOCHG_INT (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00008000 ) >> 15)
++#define GET_NEQ_PKT_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00010000 ) >> 16)
++#define GET_NEQ_MB_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x01000000 ) >> 24)
++#define GET_SRAM_TAG_0 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_1 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_2 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_3 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_4 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_5 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_6 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_7 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_8 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_9 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_10 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_11 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_12 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_13 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_14 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_15 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000 ) >> 16)
++#define SET_MCU_ENABLE(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 0) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffe))
++#define SET_MAC_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 1) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffd))
++#define SET_MCU_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 2) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffb))
++#define SET_SDIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 3) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffff7))
++#define SET_SPI_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 4) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffef))
++#define SET_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 5) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffdf))
++#define SET_DMA_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 6) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffbf))
++#define SET_WDT_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 7) | ((REG32(ADR_BRG_SW_RST)) & 0xffffff7f))
++#define SET_I2C_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 8) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffeff))
++#define SET_INT_CTL_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 9) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffdff))
++#define SET_BTCX_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 10) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffbff))
++#define SET_GPIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 11) | ((REG32(ADR_BRG_SW_RST)) & 0xfffff7ff))
++#define SET_US0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 12) | ((REG32(ADR_BRG_SW_RST)) & 0xffffefff))
++#define SET_US1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 13) | ((REG32(ADR_BRG_SW_RST)) & 0xffffdfff))
++#define SET_US2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 14) | ((REG32(ADR_BRG_SW_RST)) & 0xffffbfff))
++#define SET_US3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 15) | ((REG32(ADR_BRG_SW_RST)) & 0xffff7fff))
++#define SET_MS0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 16) | ((REG32(ADR_BRG_SW_RST)) & 0xfffeffff))
++#define SET_MS1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 17) | ((REG32(ADR_BRG_SW_RST)) & 0xfffdffff))
++#define SET_MS2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 18) | ((REG32(ADR_BRG_SW_RST)) & 0xfffbffff))
++#define SET_MS3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 19) | ((REG32(ADR_BRG_SW_RST)) & 0xfff7ffff))
++#define SET_RF_BB_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 20) | ((REG32(ADR_BRG_SW_RST)) & 0xffefffff))
++#define SET_SYS_ALL_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 21) | ((REG32(ADR_BRG_SW_RST)) & 0xffdfffff))
++#define SET_DAT_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 22) | ((REG32(ADR_BRG_SW_RST)) & 0xffbfffff))
++#define SET_I2C_MST_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 23) | ((REG32(ADR_BRG_SW_RST)) & 0xff7fffff))
++#define SET_RG_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT)) & 0xfffffffe))
++#define SET_TRAP_IMG_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 16) | ((REG32(ADR_BOOT)) & 0xfffeffff))
++#define SET_TRAP_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 17) | ((REG32(ADR_BOOT)) & 0xfffdffff))
++#define SET_TRAP_BOOT_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 18) | ((REG32(ADR_BOOT)) & 0xfffbffff))
++#define SET_CHIP_ID_31_0(_VAL_) (REG32(ADR_CHIP_ID_0)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_0)) & 0x00000000))
++#define SET_CHIP_ID_63_32(_VAL_) (REG32(ADR_CHIP_ID_1)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_1)) & 0x00000000))
++#define SET_CHIP_ID_95_64(_VAL_) (REG32(ADR_CHIP_ID_2)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_2)) & 0x00000000))
++#define SET_CHIP_ID_127_96(_VAL_) (REG32(ADR_CHIP_ID_3)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_3)) & 0x00000000))
++#define SET_CK_SEL_1_0(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 0) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffc))
++#define SET_CK_SEL_2(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 2) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffb))
++#define SET_SYS_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffe))
++#define SET_MAC_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MCU_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 2) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffb))
++#define SET_SDIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffff7))
++#define SET_SPI_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffef))
++#define SET_UART_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffdf))
++#define SET_DMA_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffbf))
++#define SET_WDT_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffff7f))
++#define SET_I2C_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 8) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffeff))
++#define SET_INT_CTL_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffdff))
++#define SET_BTCX_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_GPIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffff7ff))
++#define SET_US0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffefff))
++#define SET_US1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_US2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffbfff))
++#define SET_US3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffff7fff))
++#define SET_MS0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 16) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffeffff))
++#define SET_MS1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 17) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffdffff))
++#define SET_MS2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 18) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffbffff))
++#define SET_MS3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 19) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfff7ffff))
++#define SET_BIST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 20) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffefffff))
++#define SET_I2C_MST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 23) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xff7fffff))
++#define SET_BTCX_CSR_CLK_EN(_VAL_) (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_MCU_DBG_SEL(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_SEL)) & 0xffffffc0))
++#define SET_MCU_STOP_NOGRANT(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffeff))
++#define SET_MCU_STOP_ANYTIME(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffdff))
++#define SET_MCU_DBG_DATA(_VAL_) (REG32(ADR_MCU_DBG_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_DATA)) & 0x00000000))
++#define SET_AHB_SW_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffe))
++#define SET_AHB_ERR_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffd))
++#define SET_REG_AHB_DEBUG_MX(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffffcf))
++#define SET_REG_PKT_W_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffeff))
++#define SET_REG_PKT_R_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffdff))
++#define SET_IQ_SRAM_SEL_0(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffefff))
++#define SET_IQ_SRAM_SEL_1(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffdfff))
++#define SET_IQ_SRAM_SEL_2(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffbfff))
++#define SET_AHB_STATUS(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_AHB_BRG_STATUS)) & 0x0000ffff))
++#define SET_PARALLEL_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffffe))
++#define SET_MBRUN(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xffffffef))
++#define SET_SHIFT_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffeff))
++#define SET_MODE_REG_SI(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffdff))
++#define SET_SIMULATION_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffbff))
++#define SET_DBIST_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffff7ff))
++#define SET_MODE_REG_IN(_VAL_) (REG32(ADR_BIST_MODE_REG_IN)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN)) & 0xffe00000))
++#define SET_MODE_REG_OUT_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0xffe00000))
++#define SET_MODE_REG_SO_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0x7fffffff))
++#define SET_MONITOR_BUS_MCU_31_0(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0x00000000))
++#define SET_MONITOR_BUS_MCU_33_32(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0xfffffffc))
++#define SET_TB_ADR_SEL(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_TB_ADR_SEL)) & 0xffff0000))
++#define SET_TB_CS(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 31) | ((REG32(ADR_TB_ADR_SEL)) & 0x7fffffff))
++#define SET_TB_RDATA(_VAL_) (REG32(ADR_TB_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_TB_RDATA)) & 0x00000000))
++#define SET_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 0) | ((REG32(ADR_UART_W2B)) & 0xfffffffe))
++#define SET_DATA_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 4) | ((REG32(ADR_UART_W2B)) & 0xffffffef))
++#define SET_AHB_ILL_ADDR(_VAL_) (REG32(ADR_AHB_ILL_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILL_ADDR)) & 0x00000000))
++#define SET_AHB_FEN_ADDR(_VAL_) (REG32(ADR_AHB_FEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_FEN_ADDR)) & 0x00000000))
++#define SET_ILL_ADDR_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffe))
++#define SET_FENCE_HIT_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffd))
++#define SET_ILL_ADDR_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffef))
++#define SET_FENCE_HIT_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffdf))
++#define SET_PWM_INI_VALUE_P_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_A)) & 0xffffff00))
++#define SET_PWM_INI_VALUE_N_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_A)) & 0xffff00ff))
++#define SET_PWM_POST_SCALER_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_A)) & 0xfff0ffff))
++#define SET_PWM_ALWAYSON_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_A)) & 0xdfffffff))
++#define SET_PWM_INVERT_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_A)) & 0xbfffffff))
++#define SET_PWM_ENABLE_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_A)) & 0x7fffffff))
++#define SET_PWM_INI_VALUE_P_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_B)) & 0xffffff00))
++#define SET_PWM_INI_VALUE_N_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_B)) & 0xffff00ff))
++#define SET_PWM_POST_SCALER_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_B)) & 0xfff0ffff))
++#define SET_PWM_ALWAYSON_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_B)) & 0xdfffffff))
++#define SET_PWM_INVERT_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_B)) & 0xbfffffff))
++#define SET_PWM_ENABLE_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_B)) & 0x7fffffff))
++#define SET_HBUSREQ_LOCK(_VAL_) (REG32(ADR_HBUSREQ_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBUSREQ_LOCK)) & 0xffffe000))
++#define SET_HBURST_LOCK(_VAL_) (REG32(ADR_HBURST_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBURST_LOCK)) & 0xffffe000))
++#define SET_PRESCALER_USTIMER(_VAL_) (REG32(ADR_PRESCALER_USTIMER)) = (((_VAL_) << 0) | ((REG32(ADR_PRESCALER_USTIMER)) & 0xfffffe00))
++#define SET_MODE_REG_IN_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0xffff0000))
++#define SET_MODE_REG_OUT_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0xffff0000))
++#define SET_MODE_REG_SO_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x7fffffff))
++#define SET_MONITOR_BUS_MMU(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0xfff80000))
++#define SET_TEST_MODE0(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_TEST_MODE)) & 0xfffffffe))
++#define SET_TEST_MODE1(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_TEST_MODE)) & 0xfffffffd))
++#define SET_TEST_MODE2(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_TEST_MODE)) & 0xfffffffb))
++#define SET_TEST_MODE3(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_TEST_MODE)) & 0xfffffff7))
++#define SET_TEST_MODE4(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_TEST_MODE)) & 0xffffffef))
++#define SET_TEST_MODE_ALL(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_TEST_MODE)) & 0xffffffdf))
++#define SET_WDT_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffe))
++#define SET_SD_HOST_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffd))
++#define SET_ALLOW_SD_RESET(_VAL_) (REG32(ADR_SD_INIT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_SD_INIT_CFG)) & 0xfffffffe))
++#define SET_UART_NRTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffe))
++#define SET_UART_NCTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffd))
++#define SET_TU0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU0_TM_MODE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU0_TM_INT_MASK(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TU1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU1_TM_MODE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU1_TM_INT_MASK(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TU2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU2_TM_MODE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU2_TM_INT_MASK(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TU3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU3_TM_MODE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU3_TM_INT_MASK(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM0_TM_MODE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM0_TM_INT_MASK(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM1_TM_MODE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM1_TM_INT_MASK(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM2_TM_MODE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM2_TM_INT_MASK(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM3_TM_MODE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM3_TM_INT_MASK(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_MCU_WDT_TIME_CNT(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_WDOG_REG)) & 0xffff0000))
++#define SET_MCU_WDT_STATUS(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_MCU_WDOG_REG)) & 0xfffdffff))
++#define SET_MCU_WDOG_ENA(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_MCU_WDOG_REG)) & 0x7fffffff))
++#define SET_SYS_WDT_TIME_CNT(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_WDOG_REG)) & 0xffff0000))
++#define SET_SYS_WDT_STATUS(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYS_WDOG_REG)) & 0xfffdffff))
++#define SET_SYS_WDOG_ENA(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYS_WDOG_REG)) & 0x7fffffff))
++#define SET_XLNA_EN_O_OE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 0) | ((REG32(ADR_PAD6)) & 0xfffffffe))
++#define SET_XLNA_EN_O_PE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 1) | ((REG32(ADR_PAD6)) & 0xfffffffd))
++#define SET_PAD6_IE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 3) | ((REG32(ADR_PAD6)) & 0xfffffff7))
++#define SET_PAD6_SEL_I(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 4) | ((REG32(ADR_PAD6)) & 0xffffffcf))
++#define SET_PAD6_OD(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 8) | ((REG32(ADR_PAD6)) & 0xfffffeff))
++#define SET_PAD6_SEL_O(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 12) | ((REG32(ADR_PAD6)) & 0xffffefff))
++#define SET_XLNA_EN_O_C(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 28) | ((REG32(ADR_PAD6)) & 0xefffffff))
++#define SET_WIFI_TX_SW_O_OE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 0) | ((REG32(ADR_PAD7)) & 0xfffffffe))
++#define SET_WIFI_TX_SW_O_PE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 1) | ((REG32(ADR_PAD7)) & 0xfffffffd))
++#define SET_PAD7_IE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 3) | ((REG32(ADR_PAD7)) & 0xfffffff7))
++#define SET_PAD7_SEL_I(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 4) | ((REG32(ADR_PAD7)) & 0xffffffcf))
++#define SET_PAD7_OD(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 8) | ((REG32(ADR_PAD7)) & 0xfffffeff))
++#define SET_PAD7_SEL_O(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 12) | ((REG32(ADR_PAD7)) & 0xffffefff))
++#define SET_WIFI_TX_SW_O_C(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 28) | ((REG32(ADR_PAD7)) & 0xefffffff))
++#define SET_WIFI_RX_SW_O_OE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 0) | ((REG32(ADR_PAD8)) & 0xfffffffe))
++#define SET_WIFI_RX_SW_O_PE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 1) | ((REG32(ADR_PAD8)) & 0xfffffffd))
++#define SET_PAD8_IE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 3) | ((REG32(ADR_PAD8)) & 0xfffffff7))
++#define SET_PAD8_SEL_I(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 4) | ((REG32(ADR_PAD8)) & 0xffffffcf))
++#define SET_PAD8_OD(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 8) | ((REG32(ADR_PAD8)) & 0xfffffeff))
++#define SET_WIFI_RX_SW_O_C(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 28) | ((REG32(ADR_PAD8)) & 0xefffffff))
++#define SET_BT_SW_O_OE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 0) | ((REG32(ADR_PAD9)) & 0xfffffffe))
++#define SET_BT_SW_O_PE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 1) | ((REG32(ADR_PAD9)) & 0xfffffffd))
++#define SET_PAD9_IE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 3) | ((REG32(ADR_PAD9)) & 0xfffffff7))
++#define SET_PAD9_SEL_I(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 4) | ((REG32(ADR_PAD9)) & 0xffffffcf))
++#define SET_PAD9_OD(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 8) | ((REG32(ADR_PAD9)) & 0xfffffeff))
++#define SET_PAD9_SEL_O(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 12) | ((REG32(ADR_PAD9)) & 0xffffefff))
++#define SET_BT_SW_O_C(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 28) | ((REG32(ADR_PAD9)) & 0xefffffff))
++#define SET_XPA_EN_O_OE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 0) | ((REG32(ADR_PAD11)) & 0xfffffffe))
++#define SET_XPA_EN_O_PE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 1) | ((REG32(ADR_PAD11)) & 0xfffffffd))
++#define SET_PAD11_IE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 3) | ((REG32(ADR_PAD11)) & 0xfffffff7))
++#define SET_PAD11_SEL_I(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 4) | ((REG32(ADR_PAD11)) & 0xffffffcf))
++#define SET_PAD11_OD(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 8) | ((REG32(ADR_PAD11)) & 0xfffffeff))
++#define SET_PAD11_SEL_O(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 12) | ((REG32(ADR_PAD11)) & 0xffffefff))
++#define SET_XPA_EN_O_C(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 28) | ((REG32(ADR_PAD11)) & 0xefffffff))
++#define SET_PAD15_OE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 0) | ((REG32(ADR_PAD15)) & 0xfffffffe))
++#define SET_PAD15_PE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 1) | ((REG32(ADR_PAD15)) & 0xfffffffd))
++#define SET_PAD15_DS(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 2) | ((REG32(ADR_PAD15)) & 0xfffffffb))
++#define SET_PAD15_IE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 3) | ((REG32(ADR_PAD15)) & 0xfffffff7))
++#define SET_PAD15_SEL_I(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 4) | ((REG32(ADR_PAD15)) & 0xffffffcf))
++#define SET_PAD15_OD(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 8) | ((REG32(ADR_PAD15)) & 0xfffffeff))
++#define SET_PAD15_SEL_O(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 12) | ((REG32(ADR_PAD15)) & 0xffffefff))
++#define SET_TEST_1_ID(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 28) | ((REG32(ADR_PAD15)) & 0xefffffff))
++#define SET_PAD16_OE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 0) | ((REG32(ADR_PAD16)) & 0xfffffffe))
++#define SET_PAD16_PE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 1) | ((REG32(ADR_PAD16)) & 0xfffffffd))
++#define SET_PAD16_DS(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 2) | ((REG32(ADR_PAD16)) & 0xfffffffb))
++#define SET_PAD16_IE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 3) | ((REG32(ADR_PAD16)) & 0xfffffff7))
++#define SET_PAD16_SEL_I(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 4) | ((REG32(ADR_PAD16)) & 0xffffffcf))
++#define SET_PAD16_OD(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 8) | ((REG32(ADR_PAD16)) & 0xfffffeff))
++#define SET_PAD16_SEL_O(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 12) | ((REG32(ADR_PAD16)) & 0xffffefff))
++#define SET_TEST_2_ID(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 28) | ((REG32(ADR_PAD16)) & 0xefffffff))
++#define SET_PAD17_OE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 0) | ((REG32(ADR_PAD17)) & 0xfffffffe))
++#define SET_PAD17_PE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 1) | ((REG32(ADR_PAD17)) & 0xfffffffd))
++#define SET_PAD17_DS(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 2) | ((REG32(ADR_PAD17)) & 0xfffffffb))
++#define SET_PAD17_IE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 3) | ((REG32(ADR_PAD17)) & 0xfffffff7))
++#define SET_PAD17_SEL_I(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 4) | ((REG32(ADR_PAD17)) & 0xffffffcf))
++#define SET_PAD17_OD(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 8) | ((REG32(ADR_PAD17)) & 0xfffffeff))
++#define SET_PAD17_SEL_O(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 12) | ((REG32(ADR_PAD17)) & 0xffffefff))
++#define SET_TEST_3_ID(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 28) | ((REG32(ADR_PAD17)) & 0xefffffff))
++#define SET_PAD18_OE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 0) | ((REG32(ADR_PAD18)) & 0xfffffffe))
++#define SET_PAD18_PE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 1) | ((REG32(ADR_PAD18)) & 0xfffffffd))
++#define SET_PAD18_DS(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 2) | ((REG32(ADR_PAD18)) & 0xfffffffb))
++#define SET_PAD18_IE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 3) | ((REG32(ADR_PAD18)) & 0xfffffff7))
++#define SET_PAD18_SEL_I(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 4) | ((REG32(ADR_PAD18)) & 0xffffffcf))
++#define SET_PAD18_OD(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 8) | ((REG32(ADR_PAD18)) & 0xfffffeff))
++#define SET_PAD18_SEL_O(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 12) | ((REG32(ADR_PAD18)) & 0xffffcfff))
++#define SET_TEST_4_ID(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 28) | ((REG32(ADR_PAD18)) & 0xefffffff))
++#define SET_PAD19_OE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 0) | ((REG32(ADR_PAD19)) & 0xfffffffe))
++#define SET_PAD19_PE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 1) | ((REG32(ADR_PAD19)) & 0xfffffffd))
++#define SET_PAD19_DS(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 2) | ((REG32(ADR_PAD19)) & 0xfffffffb))
++#define SET_PAD19_IE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 3) | ((REG32(ADR_PAD19)) & 0xfffffff7))
++#define SET_PAD19_SEL_I(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 4) | ((REG32(ADR_PAD19)) & 0xffffffcf))
++#define SET_PAD19_OD(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 8) | ((REG32(ADR_PAD19)) & 0xfffffeff))
++#define SET_PAD19_SEL_O(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 12) | ((REG32(ADR_PAD19)) & 0xffff8fff))
++#define SET_SHORT_TO_20_ID(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 28) | ((REG32(ADR_PAD19)) & 0xefffffff))
++#define SET_PAD20_OE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 0) | ((REG32(ADR_PAD20)) & 0xfffffffe))
++#define SET_PAD20_PE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 1) | ((REG32(ADR_PAD20)) & 0xfffffffd))
++#define SET_PAD20_DS(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 2) | ((REG32(ADR_PAD20)) & 0xfffffffb))
++#define SET_PAD20_IE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 3) | ((REG32(ADR_PAD20)) & 0xfffffff7))
++#define SET_PAD20_SEL_I(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 4) | ((REG32(ADR_PAD20)) & 0xffffff0f))
++#define SET_PAD20_OD(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 8) | ((REG32(ADR_PAD20)) & 0xfffffeff))
++#define SET_PAD20_SEL_O(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 12) | ((REG32(ADR_PAD20)) & 0xffffcfff))
++#define SET_STRAP0(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 27) | ((REG32(ADR_PAD20)) & 0xf7ffffff))
++#define SET_GPIO_TEST_1_ID(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 28) | ((REG32(ADR_PAD20)) & 0xefffffff))
++#define SET_PAD21_OE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 0) | ((REG32(ADR_PAD21)) & 0xfffffffe))
++#define SET_PAD21_PE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 1) | ((REG32(ADR_PAD21)) & 0xfffffffd))
++#define SET_PAD21_DS(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 2) | ((REG32(ADR_PAD21)) & 0xfffffffb))
++#define SET_PAD21_IE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 3) | ((REG32(ADR_PAD21)) & 0xfffffff7))
++#define SET_PAD21_SEL_I(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 4) | ((REG32(ADR_PAD21)) & 0xffffff8f))
++#define SET_PAD21_OD(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 8) | ((REG32(ADR_PAD21)) & 0xfffffeff))
++#define SET_PAD21_SEL_O(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 12) | ((REG32(ADR_PAD21)) & 0xffffcfff))
++#define SET_STRAP3(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 27) | ((REG32(ADR_PAD21)) & 0xf7ffffff))
++#define SET_GPIO_TEST_2_ID(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 28) | ((REG32(ADR_PAD21)) & 0xefffffff))
++#define SET_PAD22_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 0) | ((REG32(ADR_PAD22)) & 0xfffffffe))
++#define SET_PAD22_PE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 1) | ((REG32(ADR_PAD22)) & 0xfffffffd))
++#define SET_PAD22_DS(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 2) | ((REG32(ADR_PAD22)) & 0xfffffffb))
++#define SET_PAD22_IE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 3) | ((REG32(ADR_PAD22)) & 0xfffffff7))
++#define SET_PAD22_SEL_I(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 4) | ((REG32(ADR_PAD22)) & 0xffffff8f))
++#define SET_PAD22_OD(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 8) | ((REG32(ADR_PAD22)) & 0xfffffeff))
++#define SET_PAD22_SEL_O(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 12) | ((REG32(ADR_PAD22)) & 0xffff8fff))
++#define SET_PAD22_SEL_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 20) | ((REG32(ADR_PAD22)) & 0xffefffff))
++#define SET_GPIO_TEST_3_ID(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 28) | ((REG32(ADR_PAD22)) & 0xefffffff))
++#define SET_PAD24_OE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 0) | ((REG32(ADR_PAD24)) & 0xfffffffe))
++#define SET_PAD24_PE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 1) | ((REG32(ADR_PAD24)) & 0xfffffffd))
++#define SET_PAD24_DS(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 2) | ((REG32(ADR_PAD24)) & 0xfffffffb))
++#define SET_PAD24_IE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 3) | ((REG32(ADR_PAD24)) & 0xfffffff7))
++#define SET_PAD24_SEL_I(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 4) | ((REG32(ADR_PAD24)) & 0xffffffcf))
++#define SET_PAD24_OD(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 8) | ((REG32(ADR_PAD24)) & 0xfffffeff))
++#define SET_PAD24_SEL_O(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 12) | ((REG32(ADR_PAD24)) & 0xffff8fff))
++#define SET_GPIO_TEST_4_ID(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 28) | ((REG32(ADR_PAD24)) & 0xefffffff))
++#define SET_PAD25_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 0) | ((REG32(ADR_PAD25)) & 0xfffffffe))
++#define SET_PAD25_PE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 1) | ((REG32(ADR_PAD25)) & 0xfffffffd))
++#define SET_PAD25_DS(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 2) | ((REG32(ADR_PAD25)) & 0xfffffffb))
++#define SET_PAD25_IE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 3) | ((REG32(ADR_PAD25)) & 0xfffffff7))
++#define SET_PAD25_SEL_I(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 4) | ((REG32(ADR_PAD25)) & 0xffffff8f))
++#define SET_PAD25_OD(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 8) | ((REG32(ADR_PAD25)) & 0xfffffeff))
++#define SET_PAD25_SEL_O(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 12) | ((REG32(ADR_PAD25)) & 0xffff8fff))
++#define SET_PAD25_SEL_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 20) | ((REG32(ADR_PAD25)) & 0xffefffff))
++#define SET_STRAP1(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 27) | ((REG32(ADR_PAD25)) & 0xf7ffffff))
++#define SET_GPIO_1_ID(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 28) | ((REG32(ADR_PAD25)) & 0xefffffff))
++#define SET_PAD27_OE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 0) | ((REG32(ADR_PAD27)) & 0xfffffffe))
++#define SET_PAD27_PE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 1) | ((REG32(ADR_PAD27)) & 0xfffffffd))
++#define SET_PAD27_DS(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 2) | ((REG32(ADR_PAD27)) & 0xfffffffb))
++#define SET_PAD27_IE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 3) | ((REG32(ADR_PAD27)) & 0xfffffff7))
++#define SET_PAD27_SEL_I(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 4) | ((REG32(ADR_PAD27)) & 0xffffff8f))
++#define SET_PAD27_OD(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 8) | ((REG32(ADR_PAD27)) & 0xfffffeff))
++#define SET_PAD27_SEL_O(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 12) | ((REG32(ADR_PAD27)) & 0xffff8fff))
++#define SET_GPIO_2_ID(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 28) | ((REG32(ADR_PAD27)) & 0xefffffff))
++#define SET_PAD28_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 0) | ((REG32(ADR_PAD28)) & 0xfffffffe))
++#define SET_PAD28_PE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 1) | ((REG32(ADR_PAD28)) & 0xfffffffd))
++#define SET_PAD28_DS(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 2) | ((REG32(ADR_PAD28)) & 0xfffffffb))
++#define SET_PAD28_IE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 3) | ((REG32(ADR_PAD28)) & 0xfffffff7))
++#define SET_PAD28_SEL_I(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 4) | ((REG32(ADR_PAD28)) & 0xffffff8f))
++#define SET_PAD28_OD(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 8) | ((REG32(ADR_PAD28)) & 0xfffffeff))
++#define SET_PAD28_SEL_O(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 12) | ((REG32(ADR_PAD28)) & 0xffff0fff))
++#define SET_PAD28_SEL_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 20) | ((REG32(ADR_PAD28)) & 0xffefffff))
++#define SET_GPIO_3_ID(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 28) | ((REG32(ADR_PAD28)) & 0xefffffff))
++#define SET_PAD29_OE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 0) | ((REG32(ADR_PAD29)) & 0xfffffffe))
++#define SET_PAD29_PE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 1) | ((REG32(ADR_PAD29)) & 0xfffffffd))
++#define SET_PAD29_DS(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 2) | ((REG32(ADR_PAD29)) & 0xfffffffb))
++#define SET_PAD29_IE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 3) | ((REG32(ADR_PAD29)) & 0xfffffff7))
++#define SET_PAD29_SEL_I(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 4) | ((REG32(ADR_PAD29)) & 0xffffff8f))
++#define SET_PAD29_OD(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 8) | ((REG32(ADR_PAD29)) & 0xfffffeff))
++#define SET_PAD29_SEL_O(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 12) | ((REG32(ADR_PAD29)) & 0xffff8fff))
++#define SET_GPIO_TEST_5_ID(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 28) | ((REG32(ADR_PAD29)) & 0xefffffff))
++#define SET_PAD30_OE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 0) | ((REG32(ADR_PAD30)) & 0xfffffffe))
++#define SET_PAD30_PE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 1) | ((REG32(ADR_PAD30)) & 0xfffffffd))
++#define SET_PAD30_DS(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 2) | ((REG32(ADR_PAD30)) & 0xfffffffb))
++#define SET_PAD30_IE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 3) | ((REG32(ADR_PAD30)) & 0xfffffff7))
++#define SET_PAD30_SEL_I(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 4) | ((REG32(ADR_PAD30)) & 0xffffffcf))
++#define SET_PAD30_OD(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 8) | ((REG32(ADR_PAD30)) & 0xfffffeff))
++#define SET_PAD30_SEL_O(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 12) | ((REG32(ADR_PAD30)) & 0xffffcfff))
++#define SET_TEST_6_ID(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 28) | ((REG32(ADR_PAD30)) & 0xefffffff))
++#define SET_PAD31_OE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 0) | ((REG32(ADR_PAD31)) & 0xfffffffe))
++#define SET_PAD31_PE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 1) | ((REG32(ADR_PAD31)) & 0xfffffffd))
++#define SET_PAD31_DS(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 2) | ((REG32(ADR_PAD31)) & 0xfffffffb))
++#define SET_PAD31_IE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 3) | ((REG32(ADR_PAD31)) & 0xfffffff7))
++#define SET_PAD31_SEL_I(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 4) | ((REG32(ADR_PAD31)) & 0xffffffcf))
++#define SET_PAD31_OD(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 8) | ((REG32(ADR_PAD31)) & 0xfffffeff))
++#define SET_PAD31_SEL_O(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 12) | ((REG32(ADR_PAD31)) & 0xffffcfff))
++#define SET_TEST_7_ID(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 28) | ((REG32(ADR_PAD31)) & 0xefffffff))
++#define SET_PAD32_OE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 0) | ((REG32(ADR_PAD32)) & 0xfffffffe))
++#define SET_PAD32_PE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 1) | ((REG32(ADR_PAD32)) & 0xfffffffd))
++#define SET_PAD32_DS(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 2) | ((REG32(ADR_PAD32)) & 0xfffffffb))
++#define SET_PAD32_IE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 3) | ((REG32(ADR_PAD32)) & 0xfffffff7))
++#define SET_PAD32_SEL_I(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 4) | ((REG32(ADR_PAD32)) & 0xffffffcf))
++#define SET_PAD32_OD(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 8) | ((REG32(ADR_PAD32)) & 0xfffffeff))
++#define SET_PAD32_SEL_O(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 12) | ((REG32(ADR_PAD32)) & 0xffffcfff))
++#define SET_TEST_8_ID(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 28) | ((REG32(ADR_PAD32)) & 0xefffffff))
++#define SET_PAD33_OE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 0) | ((REG32(ADR_PAD33)) & 0xfffffffe))
++#define SET_PAD33_PE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 1) | ((REG32(ADR_PAD33)) & 0xfffffffd))
++#define SET_PAD33_DS(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 2) | ((REG32(ADR_PAD33)) & 0xfffffffb))
++#define SET_PAD33_IE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 3) | ((REG32(ADR_PAD33)) & 0xfffffff7))
++#define SET_PAD33_SEL_I(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 4) | ((REG32(ADR_PAD33)) & 0xffffffcf))
++#define SET_PAD33_OD(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 8) | ((REG32(ADR_PAD33)) & 0xfffffeff))
++#define SET_PAD33_SEL_O(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 12) | ((REG32(ADR_PAD33)) & 0xffffcfff))
++#define SET_TEST_9_ID(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 28) | ((REG32(ADR_PAD33)) & 0xefffffff))
++#define SET_PAD34_OE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 0) | ((REG32(ADR_PAD34)) & 0xfffffffe))
++#define SET_PAD34_PE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 1) | ((REG32(ADR_PAD34)) & 0xfffffffd))
++#define SET_PAD34_DS(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 2) | ((REG32(ADR_PAD34)) & 0xfffffffb))
++#define SET_PAD34_IE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 3) | ((REG32(ADR_PAD34)) & 0xfffffff7))
++#define SET_PAD34_SEL_I(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 4) | ((REG32(ADR_PAD34)) & 0xffffffcf))
++#define SET_PAD34_OD(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 8) | ((REG32(ADR_PAD34)) & 0xfffffeff))
++#define SET_PAD34_SEL_O(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 12) | ((REG32(ADR_PAD34)) & 0xffffcfff))
++#define SET_TEST_10_ID(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 28) | ((REG32(ADR_PAD34)) & 0xefffffff))
++#define SET_PAD42_OE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 0) | ((REG32(ADR_PAD42)) & 0xfffffffe))
++#define SET_PAD42_PE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 1) | ((REG32(ADR_PAD42)) & 0xfffffffd))
++#define SET_PAD42_DS(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 2) | ((REG32(ADR_PAD42)) & 0xfffffffb))
++#define SET_PAD42_IE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 3) | ((REG32(ADR_PAD42)) & 0xfffffff7))
++#define SET_PAD42_SEL_I(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 4) | ((REG32(ADR_PAD42)) & 0xffffffcf))
++#define SET_PAD42_OD(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 8) | ((REG32(ADR_PAD42)) & 0xfffffeff))
++#define SET_PAD42_SEL_O(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 12) | ((REG32(ADR_PAD42)) & 0xffffefff))
++#define SET_TEST_11_ID(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 28) | ((REG32(ADR_PAD42)) & 0xefffffff))
++#define SET_PAD43_OE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 0) | ((REG32(ADR_PAD43)) & 0xfffffffe))
++#define SET_PAD43_PE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 1) | ((REG32(ADR_PAD43)) & 0xfffffffd))
++#define SET_PAD43_DS(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 2) | ((REG32(ADR_PAD43)) & 0xfffffffb))
++#define SET_PAD43_IE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 3) | ((REG32(ADR_PAD43)) & 0xfffffff7))
++#define SET_PAD43_SEL_I(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 4) | ((REG32(ADR_PAD43)) & 0xffffffcf))
++#define SET_PAD43_OD(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 8) | ((REG32(ADR_PAD43)) & 0xfffffeff))
++#define SET_PAD43_SEL_O(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 12) | ((REG32(ADR_PAD43)) & 0xffffefff))
++#define SET_TEST_12_ID(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 28) | ((REG32(ADR_PAD43)) & 0xefffffff))
++#define SET_PAD44_OE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 0) | ((REG32(ADR_PAD44)) & 0xfffffffe))
++#define SET_PAD44_PE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 1) | ((REG32(ADR_PAD44)) & 0xfffffffd))
++#define SET_PAD44_DS(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 2) | ((REG32(ADR_PAD44)) & 0xfffffffb))
++#define SET_PAD44_IE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 3) | ((REG32(ADR_PAD44)) & 0xfffffff7))
++#define SET_PAD44_SEL_I(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 4) | ((REG32(ADR_PAD44)) & 0xffffffcf))
++#define SET_PAD44_OD(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 8) | ((REG32(ADR_PAD44)) & 0xfffffeff))
++#define SET_PAD44_SEL_O(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 12) | ((REG32(ADR_PAD44)) & 0xffffcfff))
++#define SET_TEST_13_ID(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 28) | ((REG32(ADR_PAD44)) & 0xefffffff))
++#define SET_PAD45_OE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 0) | ((REG32(ADR_PAD45)) & 0xfffffffe))
++#define SET_PAD45_PE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 1) | ((REG32(ADR_PAD45)) & 0xfffffffd))
++#define SET_PAD45_DS(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 2) | ((REG32(ADR_PAD45)) & 0xfffffffb))
++#define SET_PAD45_IE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 3) | ((REG32(ADR_PAD45)) & 0xfffffff7))
++#define SET_PAD45_SEL_I(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 4) | ((REG32(ADR_PAD45)) & 0xffffffcf))
++#define SET_PAD45_OD(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 8) | ((REG32(ADR_PAD45)) & 0xfffffeff))
++#define SET_PAD45_SEL_O(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 12) | ((REG32(ADR_PAD45)) & 0xffffcfff))
++#define SET_TEST_14_ID(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 28) | ((REG32(ADR_PAD45)) & 0xefffffff))
++#define SET_PAD46_OE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 0) | ((REG32(ADR_PAD46)) & 0xfffffffe))
++#define SET_PAD46_PE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 1) | ((REG32(ADR_PAD46)) & 0xfffffffd))
++#define SET_PAD46_DS(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 2) | ((REG32(ADR_PAD46)) & 0xfffffffb))
++#define SET_PAD46_IE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 3) | ((REG32(ADR_PAD46)) & 0xfffffff7))
++#define SET_PAD46_SEL_I(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 4) | ((REG32(ADR_PAD46)) & 0xffffffcf))
++#define SET_PAD46_OD(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 8) | ((REG32(ADR_PAD46)) & 0xfffffeff))
++#define SET_PAD46_SEL_O(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 12) | ((REG32(ADR_PAD46)) & 0xffffcfff))
++#define SET_TEST_15_ID(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 28) | ((REG32(ADR_PAD46)) & 0xefffffff))
++#define SET_PAD47_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 0) | ((REG32(ADR_PAD47)) & 0xfffffffe))
++#define SET_PAD47_PE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 1) | ((REG32(ADR_PAD47)) & 0xfffffffd))
++#define SET_PAD47_DS(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 2) | ((REG32(ADR_PAD47)) & 0xfffffffb))
++#define SET_PAD47_SEL_I(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 4) | ((REG32(ADR_PAD47)) & 0xffffffcf))
++#define SET_PAD47_OD(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 8) | ((REG32(ADR_PAD47)) & 0xfffffeff))
++#define SET_PAD47_SEL_O(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 12) | ((REG32(ADR_PAD47)) & 0xffffcfff))
++#define SET_PAD47_SEL_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 20) | ((REG32(ADR_PAD47)) & 0xffefffff))
++#define SET_GPIO_9_ID(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 28) | ((REG32(ADR_PAD47)) & 0xefffffff))
++#define SET_PAD48_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 0) | ((REG32(ADR_PAD48)) & 0xfffffffe))
++#define SET_PAD48_PE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 1) | ((REG32(ADR_PAD48)) & 0xfffffffd))
++#define SET_PAD48_DS(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 2) | ((REG32(ADR_PAD48)) & 0xfffffffb))
++#define SET_PAD48_IE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 3) | ((REG32(ADR_PAD48)) & 0xfffffff7))
++#define SET_PAD48_SEL_I(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 4) | ((REG32(ADR_PAD48)) & 0xffffff8f))
++#define SET_PAD48_OD(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 8) | ((REG32(ADR_PAD48)) & 0xfffffeff))
++#define SET_PAD48_PE_SEL(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 11) | ((REG32(ADR_PAD48)) & 0xfffff7ff))
++#define SET_PAD48_SEL_O(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 12) | ((REG32(ADR_PAD48)) & 0xffffcfff))
++#define SET_PAD48_SEL_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 20) | ((REG32(ADR_PAD48)) & 0xffefffff))
++#define SET_GPIO_10_ID(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 28) | ((REG32(ADR_PAD48)) & 0xefffffff))
++#define SET_PAD49_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 0) | ((REG32(ADR_PAD49)) & 0xfffffffe))
++#define SET_PAD49_PE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 1) | ((REG32(ADR_PAD49)) & 0xfffffffd))
++#define SET_PAD49_DS(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 2) | ((REG32(ADR_PAD49)) & 0xfffffffb))
++#define SET_PAD49_IE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 3) | ((REG32(ADR_PAD49)) & 0xfffffff7))
++#define SET_PAD49_SEL_I(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 4) | ((REG32(ADR_PAD49)) & 0xffffff8f))
++#define SET_PAD49_OD(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 8) | ((REG32(ADR_PAD49)) & 0xfffffeff))
++#define SET_PAD49_SEL_O(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 12) | ((REG32(ADR_PAD49)) & 0xffffcfff))
++#define SET_PAD49_SEL_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 20) | ((REG32(ADR_PAD49)) & 0xffefffff))
++#define SET_GPIO_11_ID(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 28) | ((REG32(ADR_PAD49)) & 0xefffffff))
++#define SET_PAD50_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 0) | ((REG32(ADR_PAD50)) & 0xfffffffe))
++#define SET_PAD50_PE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 1) | ((REG32(ADR_PAD50)) & 0xfffffffd))
++#define SET_PAD50_DS(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 2) | ((REG32(ADR_PAD50)) & 0xfffffffb))
++#define SET_PAD50_IE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 3) | ((REG32(ADR_PAD50)) & 0xfffffff7))
++#define SET_PAD50_SEL_I(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 4) | ((REG32(ADR_PAD50)) & 0xffffff8f))
++#define SET_PAD50_OD(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 8) | ((REG32(ADR_PAD50)) & 0xfffffeff))
++#define SET_PAD50_SEL_O(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 12) | ((REG32(ADR_PAD50)) & 0xffffcfff))
++#define SET_PAD50_SEL_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 20) | ((REG32(ADR_PAD50)) & 0xffefffff))
++#define SET_GPIO_12_ID(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 28) | ((REG32(ADR_PAD50)) & 0xefffffff))
++#define SET_PAD51_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 0) | ((REG32(ADR_PAD51)) & 0xfffffffe))
++#define SET_PAD51_PE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 1) | ((REG32(ADR_PAD51)) & 0xfffffffd))
++#define SET_PAD51_DS(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 2) | ((REG32(ADR_PAD51)) & 0xfffffffb))
++#define SET_PAD51_IE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 3) | ((REG32(ADR_PAD51)) & 0xfffffff7))
++#define SET_PAD51_SEL_I(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 4) | ((REG32(ADR_PAD51)) & 0xffffffcf))
++#define SET_PAD51_OD(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 8) | ((REG32(ADR_PAD51)) & 0xfffffeff))
++#define SET_PAD51_SEL_O(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 12) | ((REG32(ADR_PAD51)) & 0xffffefff))
++#define SET_PAD51_SEL_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 20) | ((REG32(ADR_PAD51)) & 0xffefffff))
++#define SET_GPIO_13_ID(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 28) | ((REG32(ADR_PAD51)) & 0xefffffff))
++#define SET_PAD52_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 0) | ((REG32(ADR_PAD52)) & 0xfffffffe))
++#define SET_PAD52_PE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 1) | ((REG32(ADR_PAD52)) & 0xfffffffd))
++#define SET_PAD52_DS(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 2) | ((REG32(ADR_PAD52)) & 0xfffffffb))
++#define SET_PAD52_SEL_I(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 4) | ((REG32(ADR_PAD52)) & 0xffffffcf))
++#define SET_PAD52_OD(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 8) | ((REG32(ADR_PAD52)) & 0xfffffeff))
++#define SET_PAD52_SEL_O(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 12) | ((REG32(ADR_PAD52)) & 0xffffefff))
++#define SET_PAD52_SEL_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 20) | ((REG32(ADR_PAD52)) & 0xffefffff))
++#define SET_GPIO_14_ID(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 28) | ((REG32(ADR_PAD52)) & 0xefffffff))
++#define SET_PAD53_OE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 0) | ((REG32(ADR_PAD53)) & 0xfffffffe))
++#define SET_PAD53_PE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 1) | ((REG32(ADR_PAD53)) & 0xfffffffd))
++#define SET_PAD53_DS(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 2) | ((REG32(ADR_PAD53)) & 0xfffffffb))
++#define SET_PAD53_IE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 3) | ((REG32(ADR_PAD53)) & 0xfffffff7))
++#define SET_PAD53_SEL_I(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 4) | ((REG32(ADR_PAD53)) & 0xffffffcf))
++#define SET_PAD53_OD(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 8) | ((REG32(ADR_PAD53)) & 0xfffffeff))
++#define SET_PAD53_SEL_O(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 12) | ((REG32(ADR_PAD53)) & 0xffffefff))
++#define SET_JTAG_TMS_ID(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 28) | ((REG32(ADR_PAD53)) & 0xefffffff))
++#define SET_PAD54_OE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 0) | ((REG32(ADR_PAD54)) & 0xfffffffe))
++#define SET_PAD54_PE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 1) | ((REG32(ADR_PAD54)) & 0xfffffffd))
++#define SET_PAD54_DS(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 2) | ((REG32(ADR_PAD54)) & 0xfffffffb))
++#define SET_PAD54_OD(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 8) | ((REG32(ADR_PAD54)) & 0xfffffeff))
++#define SET_PAD54_SEL_O(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 12) | ((REG32(ADR_PAD54)) & 0xffffcfff))
++#define SET_JTAG_TCK_ID(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 28) | ((REG32(ADR_PAD54)) & 0xefffffff))
++#define SET_PAD56_PE(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 1) | ((REG32(ADR_PAD56)) & 0xfffffffd))
++#define SET_PAD56_DS(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 2) | ((REG32(ADR_PAD56)) & 0xfffffffb))
++#define SET_PAD56_SEL_I(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 4) | ((REG32(ADR_PAD56)) & 0xffffffef))
++#define SET_PAD56_OD(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 8) | ((REG32(ADR_PAD56)) & 0xfffffeff))
++#define SET_JTAG_TDI_ID(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 28) | ((REG32(ADR_PAD56)) & 0xefffffff))
++#define SET_PAD57_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 0) | ((REG32(ADR_PAD57)) & 0xfffffffe))
++#define SET_PAD57_PE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 1) | ((REG32(ADR_PAD57)) & 0xfffffffd))
++#define SET_PAD57_DS(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 2) | ((REG32(ADR_PAD57)) & 0xfffffffb))
++#define SET_PAD57_IE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 3) | ((REG32(ADR_PAD57)) & 0xfffffff7))
++#define SET_PAD57_SEL_I(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 4) | ((REG32(ADR_PAD57)) & 0xffffffcf))
++#define SET_PAD57_OD(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 8) | ((REG32(ADR_PAD57)) & 0xfffffeff))
++#define SET_PAD57_SEL_O(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 12) | ((REG32(ADR_PAD57)) & 0xffffcfff))
++#define SET_PAD57_SEL_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 20) | ((REG32(ADR_PAD57)) & 0xffefffff))
++#define SET_JTAG_TDO_ID(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 28) | ((REG32(ADR_PAD57)) & 0xefffffff))
++#define SET_PAD58_OE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 0) | ((REG32(ADR_PAD58)) & 0xfffffffe))
++#define SET_PAD58_PE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 1) | ((REG32(ADR_PAD58)) & 0xfffffffd))
++#define SET_PAD58_DS(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 2) | ((REG32(ADR_PAD58)) & 0xfffffffb))
++#define SET_PAD58_IE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 3) | ((REG32(ADR_PAD58)) & 0xfffffff7))
++#define SET_PAD58_SEL_I(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 4) | ((REG32(ADR_PAD58)) & 0xffffffcf))
++#define SET_PAD58_OD(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 8) | ((REG32(ADR_PAD58)) & 0xfffffeff))
++#define SET_PAD58_SEL_O(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 12) | ((REG32(ADR_PAD58)) & 0xffffefff))
++#define SET_TEST_16_ID(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 28) | ((REG32(ADR_PAD58)) & 0xefffffff))
++#define SET_PAD59_OE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 0) | ((REG32(ADR_PAD59)) & 0xfffffffe))
++#define SET_PAD59_PE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 1) | ((REG32(ADR_PAD59)) & 0xfffffffd))
++#define SET_PAD59_DS(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 2) | ((REG32(ADR_PAD59)) & 0xfffffffb))
++#define SET_PAD59_IE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 3) | ((REG32(ADR_PAD59)) & 0xfffffff7))
++#define SET_PAD59_SEL_I(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 4) | ((REG32(ADR_PAD59)) & 0xffffffcf))
++#define SET_PAD59_OD(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 8) | ((REG32(ADR_PAD59)) & 0xfffffeff))
++#define SET_PAD59_SEL_O(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 12) | ((REG32(ADR_PAD59)) & 0xffffefff))
++#define SET_TEST_17_ID(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 28) | ((REG32(ADR_PAD59)) & 0xefffffff))
++#define SET_PAD60_OE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 0) | ((REG32(ADR_PAD60)) & 0xfffffffe))
++#define SET_PAD60_PE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 1) | ((REG32(ADR_PAD60)) & 0xfffffffd))
++#define SET_PAD60_DS(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 2) | ((REG32(ADR_PAD60)) & 0xfffffffb))
++#define SET_PAD60_IE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 3) | ((REG32(ADR_PAD60)) & 0xfffffff7))
++#define SET_PAD60_SEL_I(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 4) | ((REG32(ADR_PAD60)) & 0xffffffcf))
++#define SET_PAD60_OD(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 8) | ((REG32(ADR_PAD60)) & 0xfffffeff))
++#define SET_PAD60_SEL_O(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 12) | ((REG32(ADR_PAD60)) & 0xffffefff))
++#define SET_TEST_18_ID(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 28) | ((REG32(ADR_PAD60)) & 0xefffffff))
++#define SET_PAD61_OE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 0) | ((REG32(ADR_PAD61)) & 0xfffffffe))
++#define SET_PAD61_PE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 1) | ((REG32(ADR_PAD61)) & 0xfffffffd))
++#define SET_PAD61_DS(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 2) | ((REG32(ADR_PAD61)) & 0xfffffffb))
++#define SET_PAD61_IE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 3) | ((REG32(ADR_PAD61)) & 0xfffffff7))
++#define SET_PAD61_SEL_I(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 4) | ((REG32(ADR_PAD61)) & 0xffffffef))
++#define SET_PAD61_OD(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 8) | ((REG32(ADR_PAD61)) & 0xfffffeff))
++#define SET_PAD61_SEL_O(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 12) | ((REG32(ADR_PAD61)) & 0xffffcfff))
++#define SET_TEST_19_ID(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 28) | ((REG32(ADR_PAD61)) & 0xefffffff))
++#define SET_PAD62_OE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 0) | ((REG32(ADR_PAD62)) & 0xfffffffe))
++#define SET_PAD62_PE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 1) | ((REG32(ADR_PAD62)) & 0xfffffffd))
++#define SET_PAD62_DS(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 2) | ((REG32(ADR_PAD62)) & 0xfffffffb))
++#define SET_PAD62_IE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 3) | ((REG32(ADR_PAD62)) & 0xfffffff7))
++#define SET_PAD62_SEL_I(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 4) | ((REG32(ADR_PAD62)) & 0xffffffef))
++#define SET_PAD62_OD(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 8) | ((REG32(ADR_PAD62)) & 0xfffffeff))
++#define SET_PAD62_SEL_O(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 12) | ((REG32(ADR_PAD62)) & 0xffffefff))
++#define SET_TEST_20_ID(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 28) | ((REG32(ADR_PAD62)) & 0xefffffff))
++#define SET_PAD64_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 0) | ((REG32(ADR_PAD64)) & 0xfffffffe))
++#define SET_PAD64_PE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 1) | ((REG32(ADR_PAD64)) & 0xfffffffd))
++#define SET_PAD64_DS(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 2) | ((REG32(ADR_PAD64)) & 0xfffffffb))
++#define SET_PAD64_IE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 3) | ((REG32(ADR_PAD64)) & 0xfffffff7))
++#define SET_PAD64_SEL_I(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 4) | ((REG32(ADR_PAD64)) & 0xffffff8f))
++#define SET_PAD64_OD(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 8) | ((REG32(ADR_PAD64)) & 0xfffffeff))
++#define SET_PAD64_SEL_O(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 12) | ((REG32(ADR_PAD64)) & 0xffffcfff))
++#define SET_PAD64_SEL_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 20) | ((REG32(ADR_PAD64)) & 0xffefffff))
++#define SET_GPIO_15_IP_ID(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 28) | ((REG32(ADR_PAD64)) & 0xefffffff))
++#define SET_PAD65_OE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 0) | ((REG32(ADR_PAD65)) & 0xfffffffe))
++#define SET_PAD65_PE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 1) | ((REG32(ADR_PAD65)) & 0xfffffffd))
++#define SET_PAD65_DS(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 2) | ((REG32(ADR_PAD65)) & 0xfffffffb))
++#define SET_PAD65_IE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 3) | ((REG32(ADR_PAD65)) & 0xfffffff7))
++#define SET_PAD65_SEL_I(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 4) | ((REG32(ADR_PAD65)) & 0xffffff8f))
++#define SET_PAD65_OD(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 8) | ((REG32(ADR_PAD65)) & 0xfffffeff))
++#define SET_PAD65_SEL_O(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 12) | ((REG32(ADR_PAD65)) & 0xffffefff))
++#define SET_GPIO_TEST_7_IN_ID(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 28) | ((REG32(ADR_PAD65)) & 0xefffffff))
++#define SET_PAD66_OE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 0) | ((REG32(ADR_PAD66)) & 0xfffffffe))
++#define SET_PAD66_PE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 1) | ((REG32(ADR_PAD66)) & 0xfffffffd))
++#define SET_PAD66_DS(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 2) | ((REG32(ADR_PAD66)) & 0xfffffffb))
++#define SET_PAD66_IE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 3) | ((REG32(ADR_PAD66)) & 0xfffffff7))
++#define SET_PAD66_SEL_I(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 4) | ((REG32(ADR_PAD66)) & 0xffffffcf))
++#define SET_PAD66_OD(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 8) | ((REG32(ADR_PAD66)) & 0xfffffeff))
++#define SET_PAD66_SEL_O(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 12) | ((REG32(ADR_PAD66)) & 0xffffcfff))
++#define SET_GPIO_17_QP_ID(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 28) | ((REG32(ADR_PAD66)) & 0xefffffff))
++#define SET_PAD68_OE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 0) | ((REG32(ADR_PAD68)) & 0xfffffffe))
++#define SET_PAD68_PE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 1) | ((REG32(ADR_PAD68)) & 0xfffffffd))
++#define SET_PAD68_DS(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 2) | ((REG32(ADR_PAD68)) & 0xfffffffb))
++#define SET_PAD68_IE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 3) | ((REG32(ADR_PAD68)) & 0xfffffff7))
++#define SET_PAD68_OD(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 8) | ((REG32(ADR_PAD68)) & 0xfffffeff))
++#define SET_PAD68_SEL_O(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 12) | ((REG32(ADR_PAD68)) & 0xffffefff))
++#define SET_GPIO_19_ID(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 28) | ((REG32(ADR_PAD68)) & 0xefffffff))
++#define SET_PAD67_OE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 0) | ((REG32(ADR_PAD67)) & 0xfffffffe))
++#define SET_PAD67_PE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 1) | ((REG32(ADR_PAD67)) & 0xfffffffd))
++#define SET_PAD67_DS(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 2) | ((REG32(ADR_PAD67)) & 0xfffffffb))
++#define SET_PAD67_IE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 3) | ((REG32(ADR_PAD67)) & 0xfffffff7))
++#define SET_PAD67_SEL_I(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 4) | ((REG32(ADR_PAD67)) & 0xffffff8f))
++#define SET_PAD67_OD(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 8) | ((REG32(ADR_PAD67)) & 0xfffffeff))
++#define SET_PAD67_SEL_O(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 12) | ((REG32(ADR_PAD67)) & 0xffffcfff))
++#define SET_GPIO_TEST_8_QN_ID(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 28) | ((REG32(ADR_PAD67)) & 0xefffffff))
++#define SET_PAD69_OE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 0) | ((REG32(ADR_PAD69)) & 0xfffffffe))
++#define SET_PAD69_PE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 1) | ((REG32(ADR_PAD69)) & 0xfffffffd))
++#define SET_PAD69_DS(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 2) | ((REG32(ADR_PAD69)) & 0xfffffffb))
++#define SET_PAD69_IE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 3) | ((REG32(ADR_PAD69)) & 0xfffffff7))
++#define SET_PAD69_SEL_I(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 4) | ((REG32(ADR_PAD69)) & 0xffffffcf))
++#define SET_PAD69_OD(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 8) | ((REG32(ADR_PAD69)) & 0xfffffeff))
++#define SET_PAD69_SEL_O(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 12) | ((REG32(ADR_PAD69)) & 0xffffefff))
++#define SET_STRAP2(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 27) | ((REG32(ADR_PAD69)) & 0xf7ffffff))
++#define SET_GPIO_20_ID(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 28) | ((REG32(ADR_PAD69)) & 0xefffffff))
++#define SET_PAD70_OE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 0) | ((REG32(ADR_PAD70)) & 0xfffffffe))
++#define SET_PAD70_PE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 1) | ((REG32(ADR_PAD70)) & 0xfffffffd))
++#define SET_PAD70_DS(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 2) | ((REG32(ADR_PAD70)) & 0xfffffffb))
++#define SET_PAD70_IE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 3) | ((REG32(ADR_PAD70)) & 0xfffffff7))
++#define SET_PAD70_SEL_I(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 4) | ((REG32(ADR_PAD70)) & 0xffffffcf))
++#define SET_PAD70_OD(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 8) | ((REG32(ADR_PAD70)) & 0xfffffeff))
++#define SET_PAD70_SEL_O(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 12) | ((REG32(ADR_PAD70)) & 0xffff8fff))
++#define SET_GPIO_21_ID(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 28) | ((REG32(ADR_PAD70)) & 0xefffffff))
++#define SET_PAD231_OE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 0) | ((REG32(ADR_PAD231)) & 0xfffffffe))
++#define SET_PAD231_PE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 1) | ((REG32(ADR_PAD231)) & 0xfffffffd))
++#define SET_PAD231_DS(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 2) | ((REG32(ADR_PAD231)) & 0xfffffffb))
++#define SET_PAD231_IE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 3) | ((REG32(ADR_PAD231)) & 0xfffffff7))
++#define SET_PAD231_OD(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 8) | ((REG32(ADR_PAD231)) & 0xfffffeff))
++#define SET_PIN_40_OR_56_ID(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 28) | ((REG32(ADR_PAD231)) & 0xefffffff))
++#define SET_MP_PHY2RX_DATA__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffe))
++#define SET_MP_PHY2RX_DATA__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffd))
++#define SET_MP_TX_FF_RPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 2) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffb))
++#define SET_MP_RX_FF_WPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 3) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffff7))
++#define SET_MP_RX_FF_WPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 4) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffef))
++#define SET_MP_RX_FF_WPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 5) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffdf))
++#define SET_MP_PHY2RX_DATA__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 6) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffbf))
++#define SET_MP_PHY2RX_DATA__4_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 7) | ((REG32(ADR_PIN_SEL_0)) & 0xffffff7f))
++#define SET_I2CM_SDA_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 8) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffcff))
++#define SET_CRYSTAL_OUT_REQ_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 10) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffbff))
++#define SET_MP_PHY2RX_DATA__5_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 11) | ((REG32(ADR_PIN_SEL_0)) & 0xfffff7ff))
++#define SET_MP_PHY2RX_DATA__3_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 12) | ((REG32(ADR_PIN_SEL_0)) & 0xffffefff))
++#define SET_UART_RXD_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 13) | ((REG32(ADR_PIN_SEL_0)) & 0xffff9fff))
++#define SET_MP_PHY2RX_DATA__6_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 15) | ((REG32(ADR_PIN_SEL_0)) & 0xffff7fff))
++#define SET_DAT_UART_NCTS_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 16) | ((REG32(ADR_PIN_SEL_0)) & 0xfffeffff))
++#define SET_GPIO_LOG_STOP_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 17) | ((REG32(ADR_PIN_SEL_0)) & 0xfff1ffff))
++#define SET_MP_TX_FF_RPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 20) | ((REG32(ADR_PIN_SEL_0)) & 0xffefffff))
++#define SET_MP_PHY_RX_WRST_N_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 21) | ((REG32(ADR_PIN_SEL_0)) & 0xffdfffff))
++#define SET_EXT_32K_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 22) | ((REG32(ADR_PIN_SEL_0)) & 0xff3fffff))
++#define SET_MP_PHY2RX_DATA__7_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 24) | ((REG32(ADR_PIN_SEL_0)) & 0xfeffffff))
++#define SET_MP_TX_FF_RPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 25) | ((REG32(ADR_PIN_SEL_0)) & 0xfdffffff))
++#define SET_PMUINT_WAKE_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 26) | ((REG32(ADR_PIN_SEL_0)) & 0xe3ffffff))
++#define SET_I2CM_SCL_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 29) | ((REG32(ADR_PIN_SEL_0)) & 0xdfffffff))
++#define SET_MP_MRX_RX_EN_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 30) | ((REG32(ADR_PIN_SEL_0)) & 0xbfffffff))
++#define SET_DAT_UART_RXD_SEL_0(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 31) | ((REG32(ADR_PIN_SEL_0)) & 0x7fffffff))
++#define SET_DAT_UART_RXD_SEL_1(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffe))
++#define SET_SPI_DI_SEL(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffd))
++#define SET_IO_PORT_REG(_VAL_) (REG32(ADR_IO_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_PORT_REG)) & 0xfffe0000))
++#define SET_MASK_RX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffe))
++#define SET_MASK_TX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffd))
++#define SET_MASK_SOC_SYSTEM_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffb))
++#define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffff7))
++#define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffef))
++#define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffdf))
++#define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffbf))
++#define SET_TX_LIMIT_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_MASK_REG)) & 0xffffff7f))
++#define SET_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffe))
++#define SET_TX_COMPLETE_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffd))
++#define SET_SOC_SYSTEM_INT_STATUS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffb))
++#define SET_EDCA0_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffff7))
++#define SET_EDCA1_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffef))
++#define SET_EDCA2_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffdf))
++#define SET_EDCA3_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffbf))
++#define SET_TX_LIMIT_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffff7f))
++#define SET_HOST_TRIGGERED_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffeff))
++#define SET_HOST_TRIGGERED_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 9) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffdff))
++#define SET_SOC_TRIGGER_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 10) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffbff))
++#define SET_SOC_TRIGGER_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 11) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffff7ff))
++#define SET_RDY_FOR_TX_RX(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffe))
++#define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffd))
++#define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffb))
++#define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffff7))
++#define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffffef))
++#define SET_TRIGGER_FUNCTION_SETTING(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff9f))
++#define SET_CMD52_ABORT_RESPONSE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff7f))
++#define SET_RX_PACKET_LENGTH(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xffff0000))
++#define SET_CARD_FW_DL_STATUS(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 16) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xff00ffff))
++#define SET_TX_RX_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 24) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfeffffff))
++#define SET_SDIO_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 25) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfdffffff))
++#define SET_CMD52_ABORT_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 28) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xefffffff))
++#define SET_CMD52_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 29) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xdfffffff))
++#define SET_SDIO_PARTIAL_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 30) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xbfffffff))
++#define SET_SDIO_ALL_RESE_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 31) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x7fffffff))
++#define SET_RX_PACKET_LENGTH2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xffff0000))
++#define SET_RX_INT1(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffeffff))
++#define SET_TX_DONE(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffdffff))
++#define SET_HCI_TRX_FINISH(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffbffff))
++#define SET_ALLOCATE_STATUS(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfff7ffff))
++#define SET_HCI_INPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xff0fffff))
++#define SET_HCI_OUTPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xe0ffffff))
++#define SET_AHB_HANG4(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 29) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xdfffffff))
++#define SET_HCI_IN_QUE_EMPTY(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 30) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xbfffffff))
++#define SET_SYSTEM_INT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x7fffffff))
++#define SET_CARD_RCA_REG(_VAL_) (REG32(ADR_CARD_RCA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_RCA_REG)) & 0xffff0000))
++#define SET_SDIO_FIFO_WR_THLD_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0xfffffe00))
++#define SET_SDIO_FIFO_WR_LIMIT_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0xfffffe00))
++#define SET_SDIO_TX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
++#define SET_SDIO_THLD_FOR_CMD53RD_REG(_VAL_) (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0xfffffe00))
++#define SET_SDIO_RX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
++#define SET_START_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffffff00))
++#define SET_END_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffff00ff))
++#define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0xffffff00))
++#define SET_SDIO_LAST_CMD_INDEX_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffffffc0))
++#define SET_SDIO_LAST_CMD_CRC_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffff80ff))
++#define SET_SDIO_LAST_CMD_ARG_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0x00000000))
++#define SET_SDIO_BUS_STATE_REG(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffffffe0))
++#define SET_SDIO_BUSY_LONG_CNT(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000ffff))
++#define SET_SDIO_CARD_STATUS_REG(_VAL_) (REG32(ADR_SDIO_CARD_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0x00000000))
++#define SET_R5_RESPONSE_FLAG(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 0) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xffffff00))
++#define SET_RESP_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 8) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffeff))
++#define SET_DAT_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 9) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffdff))
++#define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 16) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffeffff))
++#define SET_INT_THROUGH_PIN(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 17) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffdffff))
++#define SET_WRITE_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffffff00))
++#define SET_WRITE_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 8) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffff00ff))
++#define SET_READ_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff00ffff))
++#define SET_READ_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 24) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ffffff))
++#define SET_FN1_DMA_START_ADDR_REG(_VAL_) (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0x00000000))
++#define SET_SDIO_TO_MCU_INFO(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffff00))
++#define SET_SDIO_PARTIAL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffeff))
++#define SET_SDIO_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffdff))
++#define SET_PERI_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffbff))
++#define SET_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffff7ff))
++#define SET_AHB_BRIDGE_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffefff))
++#define SET_IO_REG_PORT_REG(_VAL_) (REG32(ADR_IO_REG_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_REG_PORT_REG)) & 0xfffe0000))
++#define SET_SDIO_FIFO_EMPTY_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000))
++#define SET_SDIO_FIFO_FULL_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff))
++#define SET_SDIO_CRC7_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000))
++#define SET_SDIO_CRC16_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff))
++#define SET_SDIO_RD_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfffffe00))
++#define SET_SDIO_WR_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfe00ffff))
++#define SET_CMD52_RD_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xfff0ffff))
++#define SET_CMD52_WR_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 20) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xff0fffff))
++#define SET_SDIO_FIFO_WR_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffffff00))
++#define SET_SDIO_FIFO_RD_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffff00ff))
++#define SET_SDIO_READ_DATA_CTRL(_VAL_) (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0xfffeffff))
++#define SET_TX_SIZE_BEFORE_SHIFT(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffff00))
++#define SET_TX_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffff8ff))
++#define SET_SDIO_TX_ALLOC_STATE(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffefff))
++#define SET_ALLOCATE_STATUS2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffeffff))
++#define SET_NO_ALLOCATE_SEND_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffdffff))
++#define SET_DOUBLE_ALLOCATE_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffbffff))
++#define SET_TX_DONE_STATUS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfff7ffff))
++#define SET_AHB_HANG2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffefffff))
++#define SET_HCI_TRX_FINISH2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffdfffff))
++#define SET_INTR_RX(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffbfffff))
++#define SET_HCI_INPUT_QUEUE_FULL(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xff7fffff))
++#define SET_ALLOCATESTATUS(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffe))
++#define SET_HCI_TRX_FINISH3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffd))
++#define SET_HCI_IN_QUE_EMPTY2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffb))
++#define SET_MTX_MNG_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffff7))
++#define SET_EDCA0_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffef))
++#define SET_EDCA1_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffdf))
++#define SET_EDCA2_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffbf))
++#define SET_EDCA3_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffff7f))
++#define SET_TX_PAGE_REMAIN2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffff00ff))
++#define SET_TX_ID_REMAIN3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff80ffff))
++#define SET_HCI_OUTPUT_FF_CNT_0(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff7fffff))
++#define SET_HCI_OUTPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xf0ffffff))
++#define SET_HCI_INPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_TX_INFORM)) & 0x0fffffff))
++#define SET_F1_BLOCK_SIZE_0_REG(_VAL_) (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (((_VAL_) << 0) | ((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0xfffff000))
++#define SET_START_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffffff00))
++#define SET_COMMAND_COUNTER(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff00ff))
++#define SET_CMD_LOG_PART1(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ffff))
++#define SET_CMD_LOG_PART2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000))
++#define SET_END_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff))
++#define SET_RX_PACKET_LENGTH3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xffff0000))
++#define SET_RX_INT3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xfffeffff))
++#define SET_TX_ID_REMAIN2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff01ffff))
++#define SET_TX_PAGE_REMAIN3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00ffffff))
++#define SET_CCCR_00H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_00H_REG)) & 0xffffff00))
++#define SET_CCCR_02H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_00H_REG)) & 0xff00ffff))
++#define SET_CCCR_03H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_00H_REG)) & 0x00ffffff))
++#define SET_CCCR_04H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_04H_REG)) & 0xffffff00))
++#define SET_CCCR_05H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_04H_REG)) & 0xffff00ff))
++#define SET_CCCR_06H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_04H_REG)) & 0xfff0ffff))
++#define SET_CCCR_07H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_04H_REG)) & 0x00ffffff))
++#define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffe))
++#define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 1) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffd))
++#define SET_SUPPORT_READ_WAIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 2) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffb))
++#define SET_SUPPORT_BUS_CONTROL(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 3) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffff7))
++#define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 4) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffef))
++#define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 5) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffdf))
++#define SET_LOW_SPEED_CARD(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffbf))
++#define SET_LOW_SPEED_CARD_4BIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffff7f))
++#define SET_COMMON_CIS_PONTER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_08H_REG)) & 0xfe0000ff))
++#define SET_SUPPORT_HIGH_SPEED(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_13H_REG)) & 0xfeffffff))
++#define SET_BSS(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 25) | ((REG32(ADR_CCCR_13H_REG)) & 0xf1ffffff))
++#define SET_FBR_100H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FBR_100H_REG)) & 0xfffffff0))
++#define SET_CSASUPPORT(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_FBR_100H_REG)) & 0xffffffbf))
++#define SET_ENABLECSA(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FBR_100H_REG)) & 0xffffff7f))
++#define SET_FBR_101H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_100H_REG)) & 0xffff00ff))
++#define SET_FBR_109H_REG(_VAL_) (REG32(ADR_FBR_109H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_109H_REG)) & 0xfe0000ff))
++#define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0x00000000))
++#define SET_SPI_MODE(_VAL_) (REG32(ADR_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_MODE)) & 0x00000000))
++#define SET_RX_QUOTA(_VAL_) (REG32(ADR_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_QUOTA)) & 0xffff0000))
++#define SET_CONDI_NUM(_VAL_) (REG32(ADR_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_CONDITION_NUMBER)) & 0xffffff00))
++#define SET_HOST_PATH(_VAL_) (REG32(ADR_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_HOST_PATH)) & 0xfffffffe))
++#define SET_TX_SEG(_VAL_) (REG32(ADR_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEG)) & 0x00000000))
++#define SET_BRST_MODE(_VAL_) (REG32(ADR_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_BURST_MODE)) & 0xfffffffe))
++#define SET_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000))
++#define SET_CSN_INTER(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
++#define SET_BACK_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000))
++#define SET_FRONT_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
++#define SET_RX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SPI_STS)) & 0xfffffffd))
++#define SET_RX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SPI_STS)) & 0xfffffffb))
++#define SET_TX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SPI_STS)) & 0xfffffff7))
++#define SET_TX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SPI_STS)) & 0xffffffef))
++#define SET_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SPI_STS)) & 0xffffffdf))
++#define SET_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SPI_STS)) & 0xffffffbf))
++#define SET_RDATA_RDY(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SPI_STS)) & 0xffffff7f))
++#define SET_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SPI_STS)) & 0xfffffeff))
++#define SET_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SPI_STS)) & 0xfffffdff))
++#define SET_RX_LEN(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_STS)) & 0x0000ffff))
++#define SET_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffff8))
++#define SET_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffeff))
++#define SET_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC)) & 0xffffff00))
++#define SET_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT)) & 0xffff0000))
++#define SET_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT)) & 0x0000ffff))
++#define SET_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT2)) & 0xffff0000))
++#define SET_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT2)) & 0xfffeffff))
++#define SET_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT2)) & 0xfffdffff))
++#define SET_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT2)) & 0xfffbffff))
++#define SET_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT3)) & 0xffff0000))
++#define SET_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT3)) & 0x0000ffff))
++#define SET_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT4)) & 0xffff0000))
++#define SET_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT4)) & 0xfffeffff))
++#define SET_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT4)) & 0xfffdffff))
++#define SET_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT4)) & 0xfffbffff))
++#define SET_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_CNT4)) & 0xfff7ffff))
++#define SET_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_CNT4)) & 0xff8fffff))
++#define SET_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_CNT4)) & 0xf8ffffff))
++#define SET_RX_RDY(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_TAG)) & 0xfffffffe))
++#define SET_SDIO_SYS_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_TAG)) & 0xfffffffb))
++#define SET_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_TAG)) & 0xfffffff7))
++#define SET_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_TAG)) & 0xffffffef))
++#define SET_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_TAG)) & 0xffffffdf))
++#define SET_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_TAG)) & 0xffffffbf))
++#define SET_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_TAG)) & 0xffffff7f))
++#define SET_SPI_FN1(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_TAG)) & 0xffff80ff))
++#define SET_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_INT_TAG)) & 0xffff7fff))
++#define SET_SPI_HOST_MASK(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_INT_TAG)) & 0xff00ffff))
++#define SET_I2CM_INT_WDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN)) & 0xfffffffe))
++#define SET_I2CM_INT_RDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 1) | ((REG32(ADR_I2CM_EN)) & 0xfffffffd))
++#define SET_I2CM_IDLE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 2) | ((REG32(ADR_I2CM_EN)) & 0xfffffffb))
++#define SET_I2CM_INT_MISMATCH(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 3) | ((REG32(ADR_I2CM_EN)) & 0xfffffff7))
++#define SET_I2CM_PSCL(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 4) | ((REG32(ADR_I2CM_EN)) & 0xffffc00f))
++#define SET_I2CM_MANUAL_MODE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN)) & 0xfffeffff))
++#define SET_I2CM_INT_WDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN)) & 0xfffdffff))
++#define SET_I2CM_INT_RDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 18) | ((REG32(ADR_I2CM_EN)) & 0xfffbffff))
++#define SET_I2CM_DEV_A(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_DEV_A)) & 0xfffffc00))
++#define SET_I2CM_DEV_A10B(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 14) | ((REG32(ADR_I2CM_DEV_A)) & 0xffffbfff))
++#define SET_I2CM_RX(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 15) | ((REG32(ADR_I2CM_DEV_A)) & 0xffff7fff))
++#define SET_I2CM_LEN(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_LEN)) & 0xffff0000))
++#define SET_I2CM_T_LEFT(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_LEN)) & 0xfff8ffff))
++#define SET_I2CM_R_GET(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 24) | ((REG32(ADR_I2CM_LEN)) & 0xf8ffffff))
++#define SET_I2CM_WDAT(_VAL_) (REG32(ADR_I2CM_WDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_WDAT)) & 0x00000000))
++#define SET_I2CM_RDAT(_VAL_) (REG32(ADR_I2CM_RDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_RDAT)) & 0x00000000))
++#define SET_I2CM_SR_LEN(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN_2)) & 0xffff0000))
++#define SET_I2CM_SR_RX(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN_2)) & 0xfffeffff))
++#define SET_I2CM_REPEAT_START(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN_2)) & 0xfffdffff))
++#define SET_UART_DATA(_VAL_) (REG32(ADR_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_UART_DATA)) & 0xffffff00))
++#define SET_DATA_RDY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_UART_IER)) & 0xfffffffe))
++#define SET_THR_EMPTY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_UART_IER)) & 0xfffffffd))
++#define SET_RX_LINESTS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_UART_IER)) & 0xfffffffb))
++#define SET_MDM_STS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_UART_IER)) & 0xfffffff7))
++#define SET_DMA_RXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_UART_IER)) & 0xffffffbf))
++#define SET_DMA_TXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_UART_IER)) & 0xffffff7f))
++#define SET_FIFO_EN(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_FCR)) & 0xfffffffe))
++#define SET_RXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_FCR)) & 0xfffffffd))
++#define SET_TXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_FCR)) & 0xfffffffb))
++#define SET_DMA_MODE(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_FCR)) & 0xfffffff7))
++#define SET_EN_AUTO_RTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_FCR)) & 0xffffffef))
++#define SET_EN_AUTO_CTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_FCR)) & 0xffffffdf))
++#define SET_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_FCR)) & 0xffffff3f))
++#define SET_WORD_LEN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LCR)) & 0xfffffffc))
++#define SET_STOP_BIT(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LCR)) & 0xfffffffb))
++#define SET_PARITY_EN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LCR)) & 0xfffffff7))
++#define SET_EVEN_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LCR)) & 0xffffffef))
++#define SET_FORCE_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LCR)) & 0xffffffdf))
++#define SET_SET_BREAK(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LCR)) & 0xffffffbf))
++#define SET_DLAB(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LCR)) & 0xffffff7f))
++#define SET_DTR(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MCR)) & 0xfffffffe))
++#define SET_RTS(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MCR)) & 0xfffffffd))
++#define SET_OUT_1(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MCR)) & 0xfffffffb))
++#define SET_OUT_2(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MCR)) & 0xfffffff7))
++#define SET_LOOP_BACK(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MCR)) & 0xffffffef))
++#define SET_DATA_RDY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LSR)) & 0xfffffffe))
++#define SET_OVERRUN_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_LSR)) & 0xfffffffd))
++#define SET_PARITY_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LSR)) & 0xfffffffb))
++#define SET_FRAMING_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LSR)) & 0xfffffff7))
++#define SET_BREAK_INT(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LSR)) & 0xffffffef))
++#define SET_THR_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LSR)) & 0xffffffdf))
++#define SET_TX_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LSR)) & 0xffffffbf))
++#define SET_FIFODATA_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LSR)) & 0xffffff7f))
++#define SET_DELTA_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MSR)) & 0xfffffffe))
++#define SET_DELTA_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MSR)) & 0xfffffffd))
++#define SET_TRAILEDGE_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MSR)) & 0xfffffffb))
++#define SET_DELTA_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MSR)) & 0xfffffff7))
++#define SET_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MSR)) & 0xffffffef))
++#define SET_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_MSR)) & 0xffffffdf))
++#define SET_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_MSR)) & 0xffffffbf))
++#define SET_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_MSR)) & 0xffffff7f))
++#define SET_BRDC_DIV(_VAL_) (REG32(ADR_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_SPR)) & 0xffff0000))
++#define SET_RTHR_L(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_RTHR)) & 0xfffffff0))
++#define SET_RTHR_H(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_RTHR)) & 0xffffff0f))
++#define SET_INT_IDCODE(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_ISR)) & 0xfffffff0))
++#define SET_FIFOS_ENABLED(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_ISR)) & 0xffffff3f))
++#define SET_DAT_UART_DATA(_VAL_) (REG32(ADR_DAT_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_DATA)) & 0xffffff00))
++#define SET_DAT_DATA_RDY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffe))
++#define SET_DAT_THR_EMPTY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffd))
++#define SET_DAT_RX_LINESTS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffb))
++#define SET_DAT_MDM_STS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffff7))
++#define SET_DAT_DMA_RXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_IER)) & 0xffffffbf))
++#define SET_DAT_DMA_TXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_IER)) & 0xffffff7f))
++#define SET_DAT_FIFO_EN(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffe))
++#define SET_DAT_RXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffd))
++#define SET_DAT_TXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffb))
++#define SET_DAT_DMA_MODE(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffff7))
++#define SET_DAT_EN_AUTO_RTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffef))
++#define SET_DAT_EN_AUTO_CTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffdf))
++#define SET_DAT_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffff3f))
++#define SET_DAT_WORD_LEN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffc))
++#define SET_DAT_STOP_BIT(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffb))
++#define SET_DAT_PARITY_EN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffff7))
++#define SET_DAT_EVEN_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffef))
++#define SET_DAT_FORCE_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffdf))
++#define SET_DAT_SET_BREAK(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffbf))
++#define SET_DAT_DLAB(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffff7f))
++#define SET_DAT_DTR(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffe))
++#define SET_DAT_RTS(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffd))
++#define SET_DAT_OUT_1(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffb))
++#define SET_DAT_OUT_2(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffff7))
++#define SET_DAT_LOOP_BACK(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MCR)) & 0xffffffef))
++#define SET_DAT_DATA_RDY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffe))
++#define SET_DAT_OVERRUN_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffd))
++#define SET_DAT_PARITY_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffb))
++#define SET_DAT_FRAMING_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffff7))
++#define SET_DAT_BREAK_INT(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffef))
++#define SET_DAT_THR_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffdf))
++#define SET_DAT_TX_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffbf))
++#define SET_DAT_FIFODATA_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffff7f))
++#define SET_DAT_DELTA_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffe))
++#define SET_DAT_DELTA_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffd))
++#define SET_DAT_TRAILEDGE_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffb))
++#define SET_DAT_DELTA_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffff7))
++#define SET_DAT_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffef))
++#define SET_DAT_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffdf))
++#define SET_DAT_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffbf))
++#define SET_DAT_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffff7f))
++#define SET_DAT_BRDC_DIV(_VAL_) (REG32(ADR_DAT_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_SPR)) & 0xffff0000))
++#define SET_DAT_RTHR_L(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_RTHR)) & 0xfffffff0))
++#define SET_DAT_RTHR_H(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_RTHR)) & 0xffffff0f))
++#define SET_DAT_INT_IDCODE(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_ISR)) & 0xfffffff0))
++#define SET_DAT_FIFOS_ENABLED(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_ISR)) & 0xffffff3f))
++#define SET_MASK_TOP(_VAL_) (REG32(ADR_INT_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK)) & 0x00000000))
++#define SET_INT_MODE(_VAL_) (REG32(ADR_INT_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MODE)) & 0x00000000))
++#define SET_IRQ_PHY_0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffe))
++#define SET_IRQ_PHY_1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffd))
++#define SET_IRQ_SDIO(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffb))
++#define SET_IRQ_BEACON_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffff7))
++#define SET_IRQ_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffef))
++#define SET_IRQ_PRE_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffdf))
++#define SET_IRQ_EDCA0_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffbf))
++#define SET_IRQ_EDCA1_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffff7f))
++#define SET_IRQ_EDCA2_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffeff))
++#define SET_IRQ_EDCA3_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffdff))
++#define SET_IRQ_EDCA4_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffbff))
++#define SET_IRQ_BEACON_DTIM(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffefff))
++#define SET_IRQ_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffdfff))
++#define SET_IRQ_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffbfff))
++#define SET_IRQ_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_IRQ_STS)) & 0xffff7fff))
++#define SET_IRQ_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffeffff))
++#define SET_IRQ_FENCE_HIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffdffff))
++#define SET_IRQ_ILL_ADDR_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffbffff))
++#define SET_IRQ_MBOX(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_IRQ_STS)) & 0xfff7ffff))
++#define SET_IRQ_US_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_IRQ_STS)) & 0xffefffff))
++#define SET_IRQ_US_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_IRQ_STS)) & 0xffdfffff))
++#define SET_IRQ_US_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_IRQ_STS)) & 0xffbfffff))
++#define SET_IRQ_US_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_IRQ_STS)) & 0xff7fffff))
++#define SET_IRQ_MS_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_IRQ_STS)) & 0xfeffffff))
++#define SET_IRQ_MS_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_IRQ_STS)) & 0xfdffffff))
++#define SET_IRQ_MS_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_IRQ_STS)) & 0xfbffffff))
++#define SET_IRQ_MS_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_IRQ_STS)) & 0xf7ffffff))
++#define SET_IRQ_TX_LIMIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_IRQ_STS)) & 0xefffffff))
++#define SET_IRQ_DMA0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_IRQ_STS)) & 0xdfffffff))
++#define SET_IRQ_CO_DMA(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_IRQ_STS)) & 0xbfffffff))
++#define SET_IRQ_PERI_GROUP(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_IRQ_STS)) & 0x7fffffff))
++#define SET_FIQ_STATUS(_VAL_) (REG32(ADR_INT_FIQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_STS)) & 0x00000000))
++#define SET_IRQ_RAW(_VAL_) (REG32(ADR_INT_IRQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_RAW)) & 0x00000000))
++#define SET_FIQ_RAW(_VAL_) (REG32(ADR_INT_FIQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_RAW)) & 0x00000000))
++#define SET_INT_PERI_MASK(_VAL_) (REG32(ADR_INT_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_MASK)) & 0x00000000))
++#define SET_PERI_RTC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffe))
++#define SET_IRQ_UART0_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffd))
++#define SET_IRQ_UART0_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffb))
++#define SET_PERI_GPI_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffff7))
++#define SET_IRQ_SPI_IPC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_PERI_STS)) & 0xffffffef))
++#define SET_PERI_GPI_1_0(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff9f))
++#define SET_SCRT_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff7f))
++#define SET_MMU_ALC_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffeff))
++#define SET_MMU_RLS_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffdff))
++#define SET_ID_MNG_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffbff))
++#define SET_MBOX_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_INT_PERI_STS)) & 0xfffff7ff))
++#define SET_MBOX_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_PERI_STS)) & 0xffffefff))
++#define SET_MBOX_INT_3(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_PERI_STS)) & 0xffffdfff))
++#define SET_HCI_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_PERI_STS)) & 0xffffbfff))
++#define SET_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_PERI_STS)) & 0xffff7fff))
++#define SET_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_PERI_STS)) & 0xfffeffff))
++#define SET_ID_MNG_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_PERI_STS)) & 0xfffdffff))
++#define SET_DMN_NOHIT_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_PERI_STS)) & 0xfffbffff))
++#define SET_ID_THOLD_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_PERI_STS)) & 0xfff7ffff))
++#define SET_ID_THOLD_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_PERI_STS)) & 0xffefffff))
++#define SET_ID_DOUBLE_RLS(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_PERI_STS)) & 0xffdfffff))
++#define SET_RX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_PERI_STS)) & 0xffbfffff))
++#define SET_TX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_PERI_STS)) & 0xff7fffff))
++#define SET_ALL_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_PERI_STS)) & 0xfeffffff))
++#define SET_DMN_MCU_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_PERI_STS)) & 0xfdffffff))
++#define SET_IRQ_DAT_UART_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_PERI_STS)) & 0xfbffffff))
++#define SET_IRQ_DAT_UART_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_PERI_STS)) & 0xf7ffffff))
++#define SET_DAT_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_PERI_STS)) & 0xefffffff))
++#define SET_DAT_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_PERI_STS)) & 0xdfffffff))
++#define SET_ALR_ABT_NOCHG_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_PERI_STS)) & 0xbfffffff))
++#define SET_TBLNEQ_MNGPKT_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_PERI_STS)) & 0x7fffffff))
++#define SET_INTR_PERI_RAW(_VAL_) (REG32(ADR_INT_PERI_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_RAW)) & 0x00000000))
++#define SET_INTR_GPI00_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffffc))
++#define SET_INTR_GPI01_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffff3))
++#define SET_SYS_RST_INT(_VAL_) (REG32(ADR_SYS_INT_FOR_HOST)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_INT_FOR_HOST)) & 0xfffffffe))
++#define SET_SPI_IPC_ADDR(_VAL_) (REG32(ADR_SPI_IPC)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_IPC)) & 0x00000000))
++#define SET_SD_MASK_TOP(_VAL_) (REG32(ADR_SDIO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_MASK)) & 0x00000000))
++#define SET_IRQ_PHY_0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffe))
++#define SET_IRQ_PHY_1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffd))
++#define SET_IRQ_SDIO_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffb))
++#define SET_IRQ_BEACON_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffff7))
++#define SET_IRQ_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffef))
++#define SET_IRQ_PRE_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffdf))
++#define SET_IRQ_EDCA0_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffbf))
++#define SET_IRQ_EDCA1_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffff7f))
++#define SET_IRQ_EDCA2_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffeff))
++#define SET_IRQ_EDCA3_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffdff))
++#define SET_IRQ_EDCA4_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffbff))
++#define SET_IRQ_BEACON_DTIM_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffefff))
++#define SET_IRQ_EDCA0_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffdfff))
++#define SET_IRQ_EDCA1_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffbfff))
++#define SET_IRQ_EDCA2_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffff7fff))
++#define SET_IRQ_EDCA3_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffeffff))
++#define SET_IRQ_FENCE_HIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffdffff))
++#define SET_IRQ_ILL_ADDR_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffbffff))
++#define SET_IRQ_MBOX_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfff7ffff))
++#define SET_IRQ_US_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffefffff))
++#define SET_IRQ_US_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffdfffff))
++#define SET_IRQ_US_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffbfffff))
++#define SET_IRQ_US_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xff7fffff))
++#define SET_IRQ_MS_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfeffffff))
++#define SET_IRQ_MS_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfdffffff))
++#define SET_IRQ_MS_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfbffffff))
++#define SET_IRQ_MS_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xf7ffffff))
++#define SET_IRQ_TX_LIMIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xefffffff))
++#define SET_IRQ_DMA0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xdfffffff))
++#define SET_IRQ_CO_DMA_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xbfffffff))
++#define SET_IRQ_PERI_GROUP_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SDIO_IRQ_STS)) & 0x7fffffff))
++#define SET_INT_PERI_MASK_SD(_VAL_) (REG32(ADR_SD_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_MASK)) & 0x00000000))
++#define SET_PERI_RTC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffe))
++#define SET_IRQ_UART0_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffd))
++#define SET_IRQ_UART0_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffb))
++#define SET_PERI_GPI_SD_2(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffff7))
++#define SET_IRQ_SPI_IPC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SD_PERI_STS)) & 0xffffffef))
++#define SET_PERI_GPI_SD_1_0(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff9f))
++#define SET_SCRT_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff7f))
++#define SET_MMU_ALC_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffeff))
++#define SET_MMU_RLS_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffdff))
++#define SET_ID_MNG_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffbff))
++#define SET_MBOX_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_SD_PERI_STS)) & 0xfffff7ff))
++#define SET_MBOX_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SD_PERI_STS)) & 0xffffefff))
++#define SET_MBOX_INT_3_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SD_PERI_STS)) & 0xffffdfff))
++#define SET_HCI_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SD_PERI_STS)) & 0xffffbfff))
++#define SET_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SD_PERI_STS)) & 0xffff7fff))
++#define SET_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SD_PERI_STS)) & 0xfffeffff))
++#define SET_ID_MNG_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SD_PERI_STS)) & 0xfffdffff))
++#define SET_DMN_NOHIT_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SD_PERI_STS)) & 0xfffbffff))
++#define SET_ID_THOLD_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SD_PERI_STS)) & 0xfff7ffff))
++#define SET_ID_THOLD_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SD_PERI_STS)) & 0xffefffff))
++#define SET_ID_DOUBLE_RLS_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SD_PERI_STS)) & 0xffdfffff))
++#define SET_RX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SD_PERI_STS)) & 0xffbfffff))
++#define SET_TX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SD_PERI_STS)) & 0xff7fffff))
++#define SET_ALL_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SD_PERI_STS)) & 0xfeffffff))
++#define SET_DMN_MCU_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SD_PERI_STS)) & 0xfdffffff))
++#define SET_IRQ_DAT_UART_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SD_PERI_STS)) & 0xfbffffff))
++#define SET_IRQ_DAT_UART_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SD_PERI_STS)) & 0xf7ffffff))
++#define SET_DAT_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SD_PERI_STS)) & 0xefffffff))
++#define SET_DAT_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SD_PERI_STS)) & 0xdfffffff))
++#define SET_ALR_ABT_NOCHG_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SD_PERI_STS)) & 0xbfffffff))
++#define SET_TBLNEQ_MNGPKT_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SD_PERI_STS)) & 0x7fffffff))
++#define SET_DBG_SPI_MODE(_VAL_) (REG32(ADR_DBG_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_MODE)) & 0x00000000))
++#define SET_DBG_RX_QUOTA(_VAL_) (REG32(ADR_DBG_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_RX_QUOTA)) & 0xffff0000))
++#define SET_DBG_CONDI_NUM(_VAL_) (REG32(ADR_DBG_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CONDITION_NUMBER)) & 0xffffff00))
++#define SET_DBG_HOST_PATH(_VAL_) (REG32(ADR_DBG_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_HOST_PATH)) & 0xfffffffe))
++#define SET_DBG_TX_SEG(_VAL_) (REG32(ADR_DBG_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_SEG)) & 0x00000000))
++#define SET_DBG_BRST_MODE(_VAL_) (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0xfffffffe))
++#define SET_DBG_CLK_WIDTH(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000))
++#define SET_DBG_CSN_INTER(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
++#define SET_DBG_BACK_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000))
++#define SET_DBG_FRONT_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
++#define SET_DBG_RX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffd))
++#define SET_DBG_RX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffb))
++#define SET_DBG_TX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffff7))
++#define SET_DBG_TX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffef))
++#define SET_DBG_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffdf))
++#define SET_DBG_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffbf))
++#define SET_DBG_RDATA_RDY(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffff7f))
++#define SET_DBG_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffeff))
++#define SET_DBG_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffdff))
++#define SET_DBG_RX_LEN(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_STS)) & 0x0000ffff))
++#define SET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffff8))
++#define SET_DBG_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffeff))
++#define SET_DBG_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_DBG_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC)) & 0xffffff00))
++#define SET_DBG_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000))
++#define SET_DBG_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff))
++#define SET_DBG_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xffff0000))
++#define SET_DBG_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffeffff))
++#define SET_DBG_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffdffff))
++#define SET_DBG_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffbffff))
++#define SET_DBG_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000))
++#define SET_DBG_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff))
++#define SET_DBG_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xffff0000))
++#define SET_DBG_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffeffff))
++#define SET_DBG_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffdffff))
++#define SET_DBG_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffbffff))
++#define SET_DBG_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfff7ffff))
++#define SET_DBG_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xff8fffff))
++#define SET_DBG_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xf8ffffff))
++#define SET_DBG_RX_RDY(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffe))
++#define SET_DBG_SDIO_SYS_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffb))
++#define SET_DBG_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffff7))
++#define SET_DBG_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffef))
++#define SET_DBG_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffdf))
++#define SET_DBG_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffbf))
++#define SET_DBG_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffff7f))
++#define SET_DBG_SPI_FN1(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff80ff))
++#define SET_DBG_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff7fff))
++#define SET_DBG_SPI_HOST_MASK(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_INT_TAG)) & 0xff00ffff))
++#define SET_BOOT_ADDR(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_ADDR)) & 0xff000000))
++#define SET_CHECK_SUM_FAIL(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_BOOT_ADDR)) & 0x7fffffff))
++#define SET_VERIFY_DATA(_VAL_) (REG32(ADR_VERIFY_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_VERIFY_DATA)) & 0x00000000))
++#define SET_FLASH_ADDR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_FLASH_ADDR)) & 0xff000000))
++#define SET_FLASH_CMD_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 28) | ((REG32(ADR_FLASH_ADDR)) & 0xefffffff))
++#define SET_FLASH_DMA_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 29) | ((REG32(ADR_FLASH_ADDR)) & 0xdfffffff))
++#define SET_DMA_EN(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 30) | ((REG32(ADR_FLASH_ADDR)) & 0xbfffffff))
++#define SET_DMA_BUSY(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_FLASH_ADDR)) & 0x7fffffff))
++#define SET_SRAM_ADDR(_VAL_) (REG32(ADR_SRAM_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SRAM_ADDR)) & 0x00000000))
++#define SET_FLASH_DMA_LEN(_VAL_) (REG32(ADR_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_LEN)) & 0x00000000))
++#define SET_FLASH_FRONT_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM)) & 0xffff0000))
++#define SET_FLASH_BACK_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM)) & 0x0000ffff))
++#define SET_FLASH_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM2)) & 0xffff0000))
++#define SET_SPI_BUSY(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM2)) & 0xfffeffff))
++#define SET_FLS_REMAP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 17) | ((REG32(ADR_SPI_PARAM2)) & 0xfffdffff))
++#define SET_PBUS_SWP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 18) | ((REG32(ADR_SPI_PARAM2)) & 0xfffbffff))
++#define SET_BIT_MODE1(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 19) | ((REG32(ADR_SPI_PARAM2)) & 0xfff7ffff))
++#define SET_BIT_MODE2(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 20) | ((REG32(ADR_SPI_PARAM2)) & 0xffefffff))
++#define SET_BIT_MODE4(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 21) | ((REG32(ADR_SPI_PARAM2)) & 0xffdfffff))
++#define SET_BOOT_CHECK_SUM(_VAL_) (REG32(ADR_CHECK_SUM_RESULT)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_RESULT)) & 0x00000000))
++#define SET_CHECK_SUM_TAG(_VAL_) (REG32(ADR_CHECK_SUM_IN_FILE)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_IN_FILE)) & 0x00000000))
++#define SET_CMD_LEN(_VAL_) (REG32(ADR_COMMAND_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_LEN)) & 0xffff0000))
++#define SET_CMD_ADDR(_VAL_) (REG32(ADR_COMMAND_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_ADDR)) & 0x00000000))
++#define SET_DMA_ADR_SRC(_VAL_) (REG32(ADR_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_SRC)) & 0x00000000))
++#define SET_DMA_ADR_DST(_VAL_) (REG32(ADR_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_DST)) & 0x00000000))
++#define SET_DMA_SRC_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff8))
++#define SET_DMA_SRC_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff7))
++#define SET_DMA_DST_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_DMA_CTRL)) & 0xffffff8f))
++#define SET_DMA_DST_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_DMA_CTRL)) & 0xffffff7f))
++#define SET_DMA_FAST_FILL(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_CTRL)) & 0xfffffeff))
++#define SET_DMA_SDIO_KICK(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_DMA_CTRL)) & 0xffffefff))
++#define SET_DMA_BADR_EN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_DMA_CTRL)) & 0xffffdfff))
++#define SET_DMA_LEN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_CTRL)) & 0x0000ffff))
++#define SET_DMA_INT_MASK(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_INT)) & 0xfffffffe))
++#define SET_DMA_STS(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_INT)) & 0xfffffeff))
++#define SET_DMA_FINISH(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_DMA_INT)) & 0x7fffffff))
++#define SET_DMA_CONST(_VAL_) (REG32(ADR_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_FILL_CONST)) & 0x00000000))
++#define SET_SLEEP_WAKE_CNT(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_0)) & 0xff000000))
++#define SET_RG_DLDO_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 24) | ((REG32(ADR_PMU_0)) & 0xf8ffffff))
++#define SET_RG_DLDO_BOOST_IQ(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 27) | ((REG32(ADR_PMU_0)) & 0xf7ffffff))
++#define SET_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 28) | ((REG32(ADR_PMU_0)) & 0x8fffffff))
++#define SET_RG_BUCK_VREF_SEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_0)) & 0x7fffffff))
++#define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_1)) & 0xfffffc00))
++#define SET_RG_RTC_OSC_RES_SW(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_1)) & 0xfc00ffff))
++#define SET_RTC_OSC_CAL_RES_RDY(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_1)) & 0x7fffffff))
++#define SET_RG_DCDC_MODE(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_2)) & 0xfffffffe))
++#define SET_RG_BUCK_EN_PSM(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_2)) & 0xffffffef))
++#define SET_RG_BUCK_PSM_VTH(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_2)) & 0xfffffeff))
++#define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 12) | ((REG32(ADR_PMU_2)) & 0xffffefff))
++#define SET_RG_RTC_RDY_DEGLITCH_TIMER(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 13) | ((REG32(ADR_PMU_2)) & 0xffff9fff))
++#define SET_RTC_CAL_ENA(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_2)) & 0xfffeffff))
++#define SET_PMU_WAKE_TRIG_EVENT(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_3)) & 0xfffffffc))
++#define SET_DIGI_TOP_POR_MASK(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_3)) & 0xffffffef))
++#define SET_PMU_ENTER_SLEEP_MODE(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_3)) & 0xfffffeff))
++#define SET_RG_RTC_DUMMIES(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_3)) & 0x0000ffff))
++#define SET_RTC_EN(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_1)) & 0xfffffffe))
++#define SET_RTC_SRC(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_1)) & 0xfffffffd))
++#define SET_RTC_TICK_CNT(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_1)) & 0x8000ffff))
++#define SET_RTC_INT_SEC_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_2)) & 0xfffffffe))
++#define SET_RTC_INT_ALARM_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_2)) & 0xfffffffd))
++#define SET_RTC_INT_SEC(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_2)) & 0xfffeffff))
++#define SET_RTC_INT_ALARM(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 17) | ((REG32(ADR_RTC_2)) & 0xfffdffff))
++#define SET_RTC_SEC_START_CNT(_VAL_) (REG32(ADR_RTC_3W)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3W)) & 0x00000000))
++#define SET_RTC_SEC_CNT(_VAL_) (REG32(ADR_RTC_3R)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3R)) & 0x00000000))
++#define SET_RTC_SEC_ALARM_VALUE(_VAL_) (REG32(ADR_RTC_4)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_4)) & 0x00000000))
++#define SET_D2_DMA_ADR_SRC(_VAL_) (REG32(ADR_D2_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_SRC)) & 0x00000000))
++#define SET_D2_DMA_ADR_DST(_VAL_) (REG32(ADR_D2_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_DST)) & 0x00000000))
++#define SET_D2_DMA_SRC_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff8))
++#define SET_D2_DMA_SRC_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff7))
++#define SET_D2_DMA_DST_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff8f))
++#define SET_D2_DMA_DST_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff7f))
++#define SET_D2_DMA_FAST_FILL(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffeff))
++#define SET_D2_DMA_SDIO_KICK(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffefff))
++#define SET_D2_DMA_BADR_EN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffdfff))
++#define SET_D2_DMA_LEN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_D2_DMA_CTRL)) & 0x0000ffff))
++#define SET_D2_DMA_INT_MASK(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffffe))
++#define SET_D2_DMA_STS(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffeff))
++#define SET_D2_DMA_FINISH(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_D2_DMA_INT)) & 0x7fffffff))
++#define SET_D2_DMA_CONST(_VAL_) (REG32(ADR_D2_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_FILL_CONST)) & 0x00000000))
++#define SET_TRAP_UNKNOWN_TYPE(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_CONTROL)) & 0xfffffffe))
++#define SET_TX_ON_DEMAND_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_CONTROL)) & 0xfffffffd))
++#define SET_RX_2_HOST(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_CONTROL)) & 0xfffffffb))
++#define SET_AUTO_SEQNO(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 3) | ((REG32(ADR_CONTROL)) & 0xfffffff7))
++#define SET_BYPASSS_TX_PARSER_ENCAP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 4) | ((REG32(ADR_CONTROL)) & 0xffffffef))
++#define SET_HDR_STRIP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 5) | ((REG32(ADR_CONTROL)) & 0xffffffdf))
++#define SET_ERP_PROTECT(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 6) | ((REG32(ADR_CONTROL)) & 0xffffff3f))
++#define SET_PRO_VER(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_CONTROL)) & 0xfffffcff))
++#define SET_TXQ_ID0(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 12) | ((REG32(ADR_CONTROL)) & 0xffff8fff))
++#define SET_TXQ_ID1(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_CONTROL)) & 0xfff8ffff))
++#define SET_TX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 20) | ((REG32(ADR_CONTROL)) & 0xffefffff))
++#define SET_RX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 21) | ((REG32(ADR_CONTROL)) & 0xffdfffff))
++#define SET_RX_NULL_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 22) | ((REG32(ADR_CONTROL)) & 0xffbfffff))
++#define SET_RX_GET_TX_QUEUE_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 25) | ((REG32(ADR_CONTROL)) & 0xfdffffff))
++#define SET_HCI_INQ_SEL(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 26) | ((REG32(ADR_CONTROL)) & 0xfbffffff))
++#define SET_TRX_DEBUG_CNT_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 28) | ((REG32(ADR_CONTROL)) & 0xefffffff))
++#define SET_WAKE_SOON_WITH_SCK(_VAL_) (REG32(ADR_SDIO_WAKE_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_WAKE_MODE)) & 0xfffffffe))
++#define SET_TX_FLOW_CTRL(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_0)) & 0xffff0000))
++#define SET_TX_FLOW_MGMT(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FLOW_0)) & 0x0000ffff))
++#define SET_TX_FLOW_DATA(_VAL_) (REG32(ADR_TX_FLOW_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_1)) & 0x00000000))
++#define SET_DOT11RTSTHRESHOLD(_VAL_) (REG32(ADR_THREASHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_THREASHOLD)) & 0x0000ffff))
++#define SET_TXF_ID(_VAL_) (REG32(ADR_TXFID_INCREASE)) = (((_VAL_) << 0) | ((REG32(ADR_TXFID_INCREASE)) & 0xffffffc0))
++#define SET_SEQ_CTRL(_VAL_) (REG32(ADR_GLOBAL_SEQUENCE)) = (((_VAL_) << 0) | ((REG32(ADR_GLOBAL_SEQUENCE)) & 0xffff0000))
++#define SET_TX_PBOFFSET(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffffff00))
++#define SET_TX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffff00ff))
++#define SET_RX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff00ffff))
++#define SET_RX_LAST_PHY_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ffffff))
++#define SET_TX_INFO_CLEAR_SIZE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xffffffc0))
++#define SET_TX_INFO_CLEAR_ENABLE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xfffffeff))
++#define SET_TXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000))
++#define SET_TXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff))
++#define SET_RXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000))
++#define SET_RXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff))
++#define SET_TX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_0)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0x00000000))
++#define SET_RX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_1)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0x00000000))
++#define SET_HOST_CMD_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_2)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0xffffff00))
++#define SET_HOST_EVENT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_3)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0xffffff00))
++#define SET_TX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_4)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0xffffff00))
++#define SET_RX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_5)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0xffffff00))
++#define SET_TX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_6)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0xffffff00))
++#define SET_RX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_7)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0xffffff00))
++#define SET_HOST_TX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0xffffff00))
++#define SET_HOST_RX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0xffffff00))
++#define SET_HCI_STATE_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0x00000000))
++#define SET_HCI_ST_TIMEOUT_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0x00000000))
++#define SET_TX_ON_DEMAND_LENGTH(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0x00000000))
++#define SET_HCI_MONITOR_REG1(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0x00000000))
++#define SET_HCI_MONITOR_REG2(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0x00000000))
++#define SET_HCI_TX_ALLOC_TIME_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0x00000000))
++#define SET_HCI_TX_ALLOC_TIME_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffff0000))
++#define SET_HCI_MB_MAX_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xff00ffff))
++#define SET_HCI_TX_ALLOC_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00000000))
++#define SET_HCI_TX_ALLOC_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xffff0000))
++#define SET_HCI_PROC_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff00ffff))
++#define SET_SDIO_TRANS_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ffffff))
++#define SET_SDIO_TX_INVALID_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0x00000000))
++#define SET_SDIO_TX_INVALID_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0xffff0000))
++#define SET_CS_START_ADDR(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_CS_START_ADDR)) & 0xffff0000))
++#define SET_CS_PKT_ID(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 16) | ((REG32(ADR_CS_START_ADDR)) & 0xff80ffff))
++#define SET_ADD_LEN(_VAL_) (REG32(ADR_CS_ADD_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_CS_ADD_LEN)) & 0xffff0000))
++#define SET_CS_ADDER_EN(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CMD)) & 0xfffffffe))
++#define SET_PSEUDO(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 1) | ((REG32(ADR_CS_CMD)) & 0xfffffffd))
++#define SET_CALCULATE(_VAL_) (REG32(ADR_CS_INI_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_INI_BUF)) & 0x00000000))
++#define SET_L4_LEN(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xffff0000))
++#define SET_L4_PROTOL(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 16) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xff00ffff))
++#define SET_CHECK_SUM(_VAL_) (REG32(ADR_CS_CHECK_SUM)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CHECK_SUM)) & 0xffff0000))
++#define SET_RAND_EN(_VAL_) (REG32(ADR_RAND_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_EN)) & 0xfffffffe))
++#define SET_RAND_NUM(_VAL_) (REG32(ADR_RAND_NUM)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_NUM)) & 0x00000000))
++#define SET_MUL_OP1(_VAL_) (REG32(ADR_MUL_OP1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP1)) & 0x00000000))
++#define SET_MUL_OP2(_VAL_) (REG32(ADR_MUL_OP2)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP2)) & 0x00000000))
++#define SET_MUL_ANS0(_VAL_) (REG32(ADR_MUL_ANS0)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS0)) & 0x00000000))
++#define SET_MUL_ANS1(_VAL_) (REG32(ADR_MUL_ANS1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS1)) & 0x00000000))
++#define SET_RD_ADDR(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_RDATA)) & 0xffff0000))
++#define SET_RD_ID(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_RDATA)) & 0xff80ffff))
++#define SET_WR_ADDR(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_WDATA)) & 0xffff0000))
++#define SET_WR_ID(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_WDATA)) & 0xff80ffff))
++#define SET_LEN(_VAL_) (REG32(ADR_DMA_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_LEN)) & 0xffff0000))
++#define SET_CLR(_VAL_) (REG32(ADR_DMA_CLR)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CLR)) & 0xfffffffe))
++#define SET_PHY_MODE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_NAV_DATA)) & 0xfffffffc))
++#define SET_SHRT_PREAM(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 2) | ((REG32(ADR_NAV_DATA)) & 0xfffffffb))
++#define SET_SHRT_GI(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 3) | ((REG32(ADR_NAV_DATA)) & 0xfffffff7))
++#define SET_DATA_RATE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 4) | ((REG32(ADR_NAV_DATA)) & 0xfffff80f))
++#define SET_MCS(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 12) | ((REG32(ADR_NAV_DATA)) & 0xffff8fff))
++#define SET_FRAME_LEN(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 16) | ((REG32(ADR_NAV_DATA)) & 0x0000ffff))
++#define SET_DURATION(_VAL_) (REG32(ADR_CO_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_CO_NAV)) & 0xffff0000))
++#define SET_SHA_DST_ADDR(_VAL_) (REG32(ADR_SHA_DST_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_DST_ADDR)) & 0x00000000))
++#define SET_SHA_SRC_ADDR(_VAL_) (REG32(ADR_SHA_SRC_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SRC_ADDR)) & 0x00000000))
++#define SET_SHA_BUSY(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffe))
++#define SET_SHA_ENDIAN(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 1) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffd))
++#define SET_EFS_CLKFREQ(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffff000))
++#define SET_LOW_ACTIVE(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffeffff))
++#define SET_EFS_CLKFREQ_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 20) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf00fffff))
++#define SET_EFS_PRE_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 28) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0fffffff))
++#define SET_EFS_LDO_ON(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000))
++#define SET_EFS_LDO_OFF(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff))
++#define SET_EFS_RDATA_0(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0x00000000))
++#define SET_EFS_WDATA_0(_VAL_) (REG32(ADR_EFUSE_WDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_0)) & 0x00000000))
++#define SET_EFS_RDATA_1(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0x00000000))
++#define SET_EFS_WDATA_1(_VAL_) (REG32(ADR_EFUSE_WDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_1)) & 0x00000000))
++#define SET_EFS_RDATA_2(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0x00000000))
++#define SET_EFS_WDATA_2(_VAL_) (REG32(ADR_EFUSE_WDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_2)) & 0x00000000))
++#define SET_EFS_RDATA_3(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0x00000000))
++#define SET_EFS_WDATA_3(_VAL_) (REG32(ADR_EFUSE_WDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_3)) & 0x00000000))
++#define SET_EFS_RDATA_4(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0x00000000))
++#define SET_EFS_WDATA_4(_VAL_) (REG32(ADR_EFUSE_WDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_4)) & 0x00000000))
++#define SET_EFS_RDATA_5(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0x00000000))
++#define SET_EFS_WDATA_5(_VAL_) (REG32(ADR_EFUSE_WDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_5)) & 0x00000000))
++#define SET_EFS_RDATA_6(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0x00000000))
++#define SET_EFS_WDATA_6(_VAL_) (REG32(ADR_EFUSE_WDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_6)) & 0x00000000))
++#define SET_EFS_RDATA_7(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0x00000000))
++#define SET_EFS_WDATA_7(_VAL_) (REG32(ADR_EFUSE_WDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_7)) & 0x00000000))
++#define SET_EFS_SPI_RD0_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD0_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD1_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD1_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD2_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD2_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD3_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD3_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD4_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD4_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD5_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD5_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD6_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD6_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD7_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD7_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RBUSY(_VAL_) (REG32(ADR_EFUSE_SPI_BUSY)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_BUSY)) & 0xfffffffe))
++#define SET_EFS_SPI_RDATA_0(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_1(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_2(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_3(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_4(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_5(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_6(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_7(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0x00000000))
++#define SET_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffe))
++#define SET_FORCE_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffd))
++#define SET_SMS4_DESCRY_EN(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG1)) & 0xffffffef))
++#define SET_DEC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffe))
++#define SET_DEC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffd))
++#define SET_ENC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffb))
++#define SET_ENC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 3) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffff7))
++#define SET_KEY_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG2)) & 0xffffffef))
++#define SET_SMS4_CBC_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffe))
++#define SET_SMS4_CFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffd))
++#define SET_SMS4_OFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffb))
++#define SET_SMS4_START_TRIG(_VAL_) (REG32(ADR_SMS4_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_TRIG)) & 0xfffffffe))
++#define SET_SMS4_BUSY(_VAL_) (REG32(ADR_SMS4_STATUS1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS1)) & 0xfffffffe))
++#define SET_SMS4_DONE(_VAL_) (REG32(ADR_SMS4_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS2)) & 0xfffffffe))
++#define SET_SMS4_DATAIN_0(_VAL_) (REG32(ADR_SMS4_DATA_IN0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN0)) & 0x00000000))
++#define SET_SMS4_DATAIN_1(_VAL_) (REG32(ADR_SMS4_DATA_IN1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN1)) & 0x00000000))
++#define SET_SMS4_DATAIN_2(_VAL_) (REG32(ADR_SMS4_DATA_IN2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN2)) & 0x00000000))
++#define SET_SMS4_DATAIN_3(_VAL_) (REG32(ADR_SMS4_DATA_IN3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN3)) & 0x00000000))
++#define SET_SMS4_DATAOUT_0(_VAL_) (REG32(ADR_SMS4_DATA_OUT0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT0)) & 0x00000000))
++#define SET_SMS4_DATAOUT_1(_VAL_) (REG32(ADR_SMS4_DATA_OUT1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT1)) & 0x00000000))
++#define SET_SMS4_DATAOUT_2(_VAL_) (REG32(ADR_SMS4_DATA_OUT2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT2)) & 0x00000000))
++#define SET_SMS4_DATAOUT_3(_VAL_) (REG32(ADR_SMS4_DATA_OUT3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT3)) & 0x00000000))
++#define SET_SMS4_KEY_0(_VAL_) (REG32(ADR_SMS4_KEY_0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_0)) & 0x00000000))
++#define SET_SMS4_KEY_1(_VAL_) (REG32(ADR_SMS4_KEY_1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_1)) & 0x00000000))
++#define SET_SMS4_KEY_2(_VAL_) (REG32(ADR_SMS4_KEY_2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_2)) & 0x00000000))
++#define SET_SMS4_KEY_3(_VAL_) (REG32(ADR_SMS4_KEY_3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_3)) & 0x00000000))
++#define SET_SMS4_MODE_IV0(_VAL_) (REG32(ADR_SMS4_MODE_IV0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV0)) & 0x00000000))
++#define SET_SMS4_MODE_IV1(_VAL_) (REG32(ADR_SMS4_MODE_IV1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV1)) & 0x00000000))
++#define SET_SMS4_MODE_IV2(_VAL_) (REG32(ADR_SMS4_MODE_IV2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV2)) & 0x00000000))
++#define SET_SMS4_MODE_IV3(_VAL_) (REG32(ADR_SMS4_MODE_IV3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV3)) & 0x00000000))
++#define SET_SMS4_OFB_ENC0(_VAL_) (REG32(ADR_SMS4_OFB_ENC0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC0)) & 0x00000000))
++#define SET_SMS4_OFB_ENC1(_VAL_) (REG32(ADR_SMS4_OFB_ENC1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC1)) & 0x00000000))
++#define SET_SMS4_OFB_ENC2(_VAL_) (REG32(ADR_SMS4_OFB_ENC2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC2)) & 0x00000000))
++#define SET_SMS4_OFB_ENC3(_VAL_) (REG32(ADR_SMS4_OFB_ENC3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC3)) & 0x00000000))
++#define SET_MRX_MCAST_TB0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_0(_VAL_) (REG32(ADR_MRX_MCAST_CTRL0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL0)) & 0xfffffffc))
++#define SET_MRX_MCAST_TB1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_1(_VAL_) (REG32(ADR_MRX_MCAST_CTRL1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL1)) & 0xfffffffc))
++#define SET_MRX_MCAST_TB2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_2(_VAL_) (REG32(ADR_MRX_MCAST_CTRL2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL2)) & 0xfffffffc))
++#define SET_MRX_MCAST_TB3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_3(_VAL_) (REG32(ADR_MRX_MCAST_CTRL3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL3)) & 0xfffffffc))
++#define SET_MRX_PHY_INFO(_VAL_) (REG32(ADR_MRX_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_PHY_INFO)) & 0x00000000))
++#define SET_DBG_BA_TYPE(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_DBG)) & 0xffffffc0))
++#define SET_DBG_BA_SEQ(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 8) | ((REG32(ADR_MRX_BA_DBG)) & 0xfff000ff))
++#define SET_MRX_FLT_TB0(_VAL_) (REG32(ADR_MRX_FLT_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB0)) & 0xffff8000))
++#define SET_MRX_FLT_TB1(_VAL_) (REG32(ADR_MRX_FLT_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB1)) & 0xffff8000))
++#define SET_MRX_FLT_TB2(_VAL_) (REG32(ADR_MRX_FLT_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB2)) & 0xffff8000))
++#define SET_MRX_FLT_TB3(_VAL_) (REG32(ADR_MRX_FLT_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB3)) & 0xffff8000))
++#define SET_MRX_FLT_TB4(_VAL_) (REG32(ADR_MRX_FLT_TB4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB4)) & 0xffff8000))
++#define SET_MRX_FLT_TB5(_VAL_) (REG32(ADR_MRX_FLT_TB5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB5)) & 0xffff8000))
++#define SET_MRX_FLT_TB6(_VAL_) (REG32(ADR_MRX_FLT_TB6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB6)) & 0xffff8000))
++#define SET_MRX_FLT_TB7(_VAL_) (REG32(ADR_MRX_FLT_TB7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB7)) & 0xffff8000))
++#define SET_MRX_FLT_TB8(_VAL_) (REG32(ADR_MRX_FLT_TB8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB8)) & 0xffff8000))
++#define SET_MRX_FLT_TB9(_VAL_) (REG32(ADR_MRX_FLT_TB9)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB9)) & 0xffff8000))
++#define SET_MRX_FLT_TB10(_VAL_) (REG32(ADR_MRX_FLT_TB10)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB10)) & 0xffff8000))
++#define SET_MRX_FLT_TB11(_VAL_) (REG32(ADR_MRX_FLT_TB11)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB11)) & 0xffff8000))
++#define SET_MRX_FLT_TB12(_VAL_) (REG32(ADR_MRX_FLT_TB12)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB12)) & 0xffff8000))
++#define SET_MRX_FLT_TB13(_VAL_) (REG32(ADR_MRX_FLT_TB13)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB13)) & 0xffff8000))
++#define SET_MRX_FLT_TB14(_VAL_) (REG32(ADR_MRX_FLT_TB14)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB14)) & 0xffff8000))
++#define SET_MRX_FLT_TB15(_VAL_) (REG32(ADR_MRX_FLT_TB15)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB15)) & 0xffff8000))
++#define SET_MRX_FLT_EN0(_VAL_) (REG32(ADR_MRX_FLT_EN0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN0)) & 0xffff0000))
++#define SET_MRX_FLT_EN1(_VAL_) (REG32(ADR_MRX_FLT_EN1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN1)) & 0xffff0000))
++#define SET_MRX_FLT_EN2(_VAL_) (REG32(ADR_MRX_FLT_EN2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN2)) & 0xffff0000))
++#define SET_MRX_FLT_EN3(_VAL_) (REG32(ADR_MRX_FLT_EN3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN3)) & 0xffff0000))
++#define SET_MRX_FLT_EN4(_VAL_) (REG32(ADR_MRX_FLT_EN4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN4)) & 0xffff0000))
++#define SET_MRX_FLT_EN5(_VAL_) (REG32(ADR_MRX_FLT_EN5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN5)) & 0xffff0000))
++#define SET_MRX_FLT_EN6(_VAL_) (REG32(ADR_MRX_FLT_EN6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN6)) & 0xffff0000))
++#define SET_MRX_FLT_EN7(_VAL_) (REG32(ADR_MRX_FLT_EN7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN7)) & 0xffff0000))
++#define SET_MRX_FLT_EN8(_VAL_) (REG32(ADR_MRX_FLT_EN8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN8)) & 0xffff0000))
++#define SET_MRX_LEN_FLT(_VAL_) (REG32(ADR_MRX_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_LEN_FLT)) & 0xffff0000))
++#define SET_RX_FLOW_DATA(_VAL_) (REG32(ADR_RX_FLOW_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_DATA)) & 0x00000000))
++#define SET_RX_FLOW_MNG(_VAL_) (REG32(ADR_RX_FLOW_MNG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_MNG)) & 0xffff0000))
++#define SET_RX_FLOW_CTRL(_VAL_) (REG32(ADR_RX_FLOW_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_CTRL)) & 0xffff0000))
++#define SET_MRX_STP_EN(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xfffffffe))
++#define SET_MRX_STP_OFST(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xffff00ff))
++#define SET_DBG_FF_FULL(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_FF_FULL)) & 0xffff0000))
++#define SET_DBG_FF_FULL_CLR(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_FF_FULL)) & 0x7fffffff))
++#define SET_DBG_WFF_FULL(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_WFF_FULL)) & 0xffff0000))
++#define SET_DBG_WFF_FULL_CLR(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_WFF_FULL)) & 0x7fffffff))
++#define SET_DBG_MB_FULL(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_MB_FULL)) & 0xffff0000))
++#define SET_DBG_MB_FULL_CLR(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_MB_FULL)) & 0x7fffffff))
++#define SET_BA_CTRL(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BA_CTRL)) & 0xfffffffc))
++#define SET_BA_DBG_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_BA_CTRL)) & 0xfffffffb))
++#define SET_BA_AGRE_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_BA_CTRL)) & 0xfffffff7))
++#define SET_BA_TA_31_0(_VAL_) (REG32(ADR_BA_TA_0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_0)) & 0x00000000))
++#define SET_BA_TA_47_32(_VAL_) (REG32(ADR_BA_TA_1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_1)) & 0xffff0000))
++#define SET_BA_TID(_VAL_) (REG32(ADR_BA_TID)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TID)) & 0xfffffff0))
++#define SET_BA_ST_SEQ(_VAL_) (REG32(ADR_BA_ST_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_BA_ST_SEQ)) & 0xfffff000))
++#define SET_BA_SB0(_VAL_) (REG32(ADR_BA_SB0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB0)) & 0x00000000))
++#define SET_BA_SB1(_VAL_) (REG32(ADR_BA_SB1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB1)) & 0x00000000))
++#define SET_MRX_WD(_VAL_) (REG32(ADR_MRX_WATCH_DOG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_WATCH_DOG)) & 0xfffe0000))
++#define SET_ACK_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffe))
++#define SET_BA_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 1) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffd))
++#define SET_ACK_GEN_DUR(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffff0000))
++#define SET_ACK_GEN_INFO(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 16) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffc0ffff))
++#define SET_ACK_GEN_RA_31_0(_VAL_) (REG32(ADR_ACK_GEN_RA_0)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_0)) & 0x00000000))
++#define SET_ACK_GEN_RA_47_32(_VAL_) (REG32(ADR_ACK_GEN_RA_1)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_1)) & 0xffff0000))
++#define SET_MIB_LEN_FAIL(_VAL_) (REG32(ADR_MIB_LEN_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_LEN_FAIL)) & 0xffff0000))
++#define SET_TRAP_HW_ID(_VAL_) (REG32(ADR_TRAP_HW_ID)) = (((_VAL_) << 0) | ((REG32(ADR_TRAP_HW_ID)) & 0xfffffff0))
++#define SET_ID_IN_USE(_VAL_) (REG32(ADR_ID_IN_USE)) = (((_VAL_) << 0) | ((REG32(ADR_ID_IN_USE)) & 0xffffff00))
++#define SET_MRX_ERR(_VAL_) (REG32(ADR_MRX_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ERR)) & 0x00000000))
++#define SET_W0_T0_SEQ(_VAL_) (REG32(ADR_WSID0_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T1_SEQ(_VAL_) (REG32(ADR_WSID0_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T2_SEQ(_VAL_) (REG32(ADR_WSID0_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T3_SEQ(_VAL_) (REG32(ADR_WSID0_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T4_SEQ(_VAL_) (REG32(ADR_WSID0_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T5_SEQ(_VAL_) (REG32(ADR_WSID0_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T6_SEQ(_VAL_) (REG32(ADR_WSID0_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T7_SEQ(_VAL_) (REG32(ADR_WSID0_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T0_SEQ(_VAL_) (REG32(ADR_WSID1_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T1_SEQ(_VAL_) (REG32(ADR_WSID1_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T2_SEQ(_VAL_) (REG32(ADR_WSID1_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T3_SEQ(_VAL_) (REG32(ADR_WSID1_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T4_SEQ(_VAL_) (REG32(ADR_WSID1_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T5_SEQ(_VAL_) (REG32(ADR_WSID1_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T6_SEQ(_VAL_) (REG32(ADR_WSID1_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T7_SEQ(_VAL_) (REG32(ADR_WSID1_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0xffff0000))
++#define SET_ADDR1A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffffc))
++#define SET_ADDR2A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 2) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffff3))
++#define SET_ADDR3A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 4) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffffcf))
++#define SET_ADDR1B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 6) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffff3f))
++#define SET_ADDR2B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffcff))
++#define SET_ADDR3B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 10) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffff3ff))
++#define SET_ADDR3C_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 12) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffcfff))
++#define SET_FRM_CTRL(_VAL_) (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (((_VAL_) << 0) | ((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0xffffffc0))
++#define SET_CSR_PHY_INFO(_VAL_) (REG32(ADR_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_INFO)) & 0xffff8000))
++#define SET_AMPDU_SIG(_VAL_) (REG32(ADR_AMPDU_SIG)) = (((_VAL_) << 0) | ((REG32(ADR_AMPDU_SIG)) & 0xffffff00))
++#define SET_MIB_AMPDU(_VAL_) (REG32(ADR_MIB_AMPDU)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_AMPDU)) & 0x00000000))
++#define SET_LEN_FLT(_VAL_) (REG32(ADR_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_LEN_FLT)) & 0xffff0000))
++#define SET_MIB_DELIMITER(_VAL_) (REG32(ADR_MIB_DELIMITER)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_DELIMITER)) & 0xffff0000))
++#define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_STS)) & 0xfffeffff))
++#define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_STS)) & 0xfffdffff))
++#define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_STS)) & 0xfffbffff))
++#define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_STS)) & 0xfff7ffff))
++#define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_STS)) & 0xffefffff))
++#define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_STS)) & 0xffdfffff))
++#define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_STS)) & 0xffbfffff))
++#define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_STS)) & 0xff7fffff))
++#define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_STS)) & 0xfeffffff))
++#define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_STS)) & 0xfdffffff))
++#define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_EN)) & 0xfffeffff))
++#define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_EN)) & 0xfffdffff))
++#define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_EN)) & 0xfffbffff))
++#define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_EN)) & 0xfff7ffff))
++#define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_EN)) & 0xffefffff))
++#define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_EN)) & 0xffdfffff))
++#define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_EN)) & 0xffbfffff))
++#define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_EN)) & 0xff7fffff))
++#define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_EN)) & 0xfeffffff))
++#define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_EN)) & 0xfdffffff))
++#define SET_MTX_MTX2PHY_SLOW(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffffe))
++#define SET_MTX_M2M_SLOW_PRD(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffff1))
++#define SET_MTX_AMPDU_CRC_AUTO(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffdf))
++#define SET_MTX_FAST_RSP_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffbf))
++#define SET_MTX_RAW_DATA_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffff7f))
++#define SET_MTX_ACK_DUR0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffeff))
++#define SET_MTX_TSF_AUTO_BCN(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffbff))
++#define SET_MTX_TSF_AUTO_MISC(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffff7ff))
++#define SET_MTX_FORCE_CS_IDLE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffefff))
++#define SET_MTX_FORCE_BKF_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffdfff))
++#define SET_MTX_FORCE_DMA_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffbfff))
++#define SET_MTX_FORCE_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_MISC_EN)) & 0xffff7fff))
++#define SET_MTX_HALT_Q_MB(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_MISC_EN)) & 0xffc0ffff))
++#define SET_MTX_CTS_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_MISC_EN)) & 0xffbfffff))
++#define SET_MTX_AMPDU_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_MISC_EN)) & 0xff7fffff))
++#define SET_MTX_EDCCA_TOUT(_VAL_) (REG32(ADR_MTX_EDCCA_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_EDCCA_TOUT)) & 0xfffffc00))
++#define SET_MTX_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffffd))
++#define SET_MTX_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffff7))
++#define SET_MTX_EN_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffffd))
++#define SET_MTX_EN_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffff7))
++#define SET_MTX_BCN_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffe))
++#define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffd))
++#define SET_MTX_TSF_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffdf))
++#define SET_MTX_HALT_MNG_UNTIL_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffbf))
++#define SET_MTX_INT_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffff00ff))
++#define SET_MTX_AUTO_FLUSH_Q4(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffeffff))
++#define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffffe))
++#define SET_MTX_BCN_CFG_VLD(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff9))
++#define SET_MTX_AUTO_BCN_ONGOING(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff7))
++#define SET_MTX_BCN_TIMER(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_MISC)) & 0x0000ffff))
++#define SET_MTX_BCN_PERIOD(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_PRD)) & 0xffff0000))
++#define SET_MTX_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_BCN_PRD)) & 0x00ffffff))
++#define SET_MTX_BCN_TSF_L(_VAL_) (REG32(ADR_MTX_BCN_TSF_L)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_L)) & 0x00000000))
++#define SET_MTX_BCN_TSF_U(_VAL_) (REG32(ADR_MTX_BCN_TSF_U)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_U)) & 0x00000000))
++#define SET_MTX_BCN_PKT_ID0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xffffff80))
++#define SET_MTX_DTIM_OFST0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xfc00ffff))
++#define SET_MTX_BCN_PKT_ID1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xffffff80))
++#define SET_MTX_DTIM_OFST1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xfc00ffff))
++#define SET_MTX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffe))
++#define SET_MRX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffd))
++#define SET_MTX_DMA_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 2) | ((REG32(ADR_MTX_STATUS)) & 0xffffffe3))
++#define SET_CH_ST_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_STATUS)) & 0xffffff1f))
++#define SET_MTX_GNT_LOCK(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_STATUS)) & 0xfffffeff))
++#define SET_MTX_DMA_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MTX_STATUS)) & 0xfffffdff))
++#define SET_MTX_Q_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_STATUS)) & 0xfffffbff))
++#define SET_MTX_TX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_STATUS)) & 0xfffff7ff))
++#define SET_MRX_RX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_STATUS)) & 0xffffefff))
++#define SET_DBG_PRTC_PRD(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_STATUS)) & 0xffffdfff))
++#define SET_DBG_DMA_RDY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_STATUS)) & 0xffffbfff))
++#define SET_DBG_WAIT_RSP(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_STATUS)) & 0xffff7fff))
++#define SET_DBG_CFRM_BUSY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_STATUS)) & 0xfffeffff))
++#define SET_DBG_RST(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffe))
++#define SET_DBG_MODE(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffd))
++#define SET_MB_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000))
++#define SET_RX_EN_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff))
++#define SET_RX_CS_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000))
++#define SET_TX_CCA_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff))
++#define SET_Q_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000))
++#define SET_CH_STA0_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff))
++#define SET_MTX_DUR_RSP_TOUT_B(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffffff00))
++#define SET_MTX_DUR_RSP_TOUT_G(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffff00ff))
++#define SET_MTX_DUR_RSP_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffffff00))
++#define SET_MTX_DUR_BURST_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffff00ff))
++#define SET_MTX_DUR_SLOT(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffc0ffff))
++#define SET_MTX_DUR_RSP_EIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_IFS)) & 0x003fffff))
++#define SET_MTX_DUR_RSP_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffffff00))
++#define SET_MTX_DUR_BURST_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffff00ff))
++#define SET_MTX_DUR_SLOT_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc0ffff))
++#define SET_MTX_DUR_RSP_EIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003fffff))
++#define SET_CH_STA1_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000))
++#define SET_CH_STA2_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff))
++#define SET_MTX_NAV(_VAL_) (REG32(ADR_MTX_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_NAV)) & 0xffff0000))
++#define SET_MTX_MIB_CNT0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xc0000000))
++#define SET_MTX_MIB_EN0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xbfffffff))
++#define SET_MTX_MIB_CNT1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xc0000000))
++#define SET_MTX_MIB_EN1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xbfffffff))
++#define SET_CH_STA3_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000))
++#define SET_CH_STA4_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff))
++#define SET_TXQ0_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ0_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ0_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ0_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ0_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ0_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ0_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ0_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ0_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ0_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ1_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ1_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ1_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ1_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ1_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ1_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ1_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ1_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ1_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ1_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ2_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ2_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ2_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ2_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ2_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ2_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ2_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ2_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ2_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ2_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ3_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ3_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ3_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ3_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ3_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ3_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ3_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ3_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ3_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ3_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ4_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ4_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ4_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ4_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ4_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ4_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ4_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ4_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ4_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ4_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_VALID0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0)) & 0xfffffffe))
++#define SET_PEER_QOS_EN0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 1) | ((REG32(ADR_WSID0)) & 0xfffffffd))
++#define SET_PEER_OP_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 2) | ((REG32(ADR_WSID0)) & 0xfffffff3))
++#define SET_PEER_HT_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 4) | ((REG32(ADR_WSID0)) & 0xffffffcf))
++#define SET_PEER_MAC0_31_0(_VAL_) (REG32(ADR_PEER_MAC0_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_0)) & 0x00000000))
++#define SET_PEER_MAC0_47_32(_VAL_) (REG32(ADR_PEER_MAC0_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_1)) & 0xffff0000))
++#define SET_TX_ACK_POLICY_0_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_0)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_1)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_2)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_3)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_4)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_5)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_6)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_7)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0xfffff000))
++#define SET_VALID1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1)) & 0xfffffffe))
++#define SET_PEER_QOS_EN1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 1) | ((REG32(ADR_WSID1)) & 0xfffffffd))
++#define SET_PEER_OP_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 2) | ((REG32(ADR_WSID1)) & 0xfffffff3))
++#define SET_PEER_HT_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 4) | ((REG32(ADR_WSID1)) & 0xffffffcf))
++#define SET_PEER_MAC1_31_0(_VAL_) (REG32(ADR_PEER_MAC1_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_0)) & 0x00000000))
++#define SET_PEER_MAC1_47_32(_VAL_) (REG32(ADR_PEER_MAC1_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_1)) & 0xffff0000))
++#define SET_TX_ACK_POLICY_1_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_0)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_1)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_2)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_3)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_4)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_5)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_6)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_7)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0xfffff000))
++#define SET_INFO0(_VAL_) (REG32(ADR_INFO0)) = (((_VAL_) << 0) | ((REG32(ADR_INFO0)) & 0x00000000))
++#define SET_INFO1(_VAL_) (REG32(ADR_INFO1)) = (((_VAL_) << 0) | ((REG32(ADR_INFO1)) & 0x00000000))
++#define SET_INFO2(_VAL_) (REG32(ADR_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_INFO2)) & 0x00000000))
++#define SET_INFO3(_VAL_) (REG32(ADR_INFO3)) = (((_VAL_) << 0) | ((REG32(ADR_INFO3)) & 0x00000000))
++#define SET_INFO4(_VAL_) (REG32(ADR_INFO4)) = (((_VAL_) << 0) | ((REG32(ADR_INFO4)) & 0x00000000))
++#define SET_INFO5(_VAL_) (REG32(ADR_INFO5)) = (((_VAL_) << 0) | ((REG32(ADR_INFO5)) & 0x00000000))
++#define SET_INFO6(_VAL_) (REG32(ADR_INFO6)) = (((_VAL_) << 0) | ((REG32(ADR_INFO6)) & 0x00000000))
++#define SET_INFO7(_VAL_) (REG32(ADR_INFO7)) = (((_VAL_) << 0) | ((REG32(ADR_INFO7)) & 0x00000000))
++#define SET_INFO8(_VAL_) (REG32(ADR_INFO8)) = (((_VAL_) << 0) | ((REG32(ADR_INFO8)) & 0x00000000))
++#define SET_INFO9(_VAL_) (REG32(ADR_INFO9)) = (((_VAL_) << 0) | ((REG32(ADR_INFO9)) & 0x00000000))
++#define SET_INFO10(_VAL_) (REG32(ADR_INFO10)) = (((_VAL_) << 0) | ((REG32(ADR_INFO10)) & 0x00000000))
++#define SET_INFO11(_VAL_) (REG32(ADR_INFO11)) = (((_VAL_) << 0) | ((REG32(ADR_INFO11)) & 0x00000000))
++#define SET_INFO12(_VAL_) (REG32(ADR_INFO12)) = (((_VAL_) << 0) | ((REG32(ADR_INFO12)) & 0x00000000))
++#define SET_INFO13(_VAL_) (REG32(ADR_INFO13)) = (((_VAL_) << 0) | ((REG32(ADR_INFO13)) & 0x00000000))
++#define SET_INFO14(_VAL_) (REG32(ADR_INFO14)) = (((_VAL_) << 0) | ((REG32(ADR_INFO14)) & 0x00000000))
++#define SET_INFO15(_VAL_) (REG32(ADR_INFO15)) = (((_VAL_) << 0) | ((REG32(ADR_INFO15)) & 0x00000000))
++#define SET_INFO16(_VAL_) (REG32(ADR_INFO16)) = (((_VAL_) << 0) | ((REG32(ADR_INFO16)) & 0x00000000))
++#define SET_INFO17(_VAL_) (REG32(ADR_INFO17)) = (((_VAL_) << 0) | ((REG32(ADR_INFO17)) & 0x00000000))
++#define SET_INFO18(_VAL_) (REG32(ADR_INFO18)) = (((_VAL_) << 0) | ((REG32(ADR_INFO18)) & 0x00000000))
++#define SET_INFO19(_VAL_) (REG32(ADR_INFO19)) = (((_VAL_) << 0) | ((REG32(ADR_INFO19)) & 0x00000000))
++#define SET_INFO20(_VAL_) (REG32(ADR_INFO20)) = (((_VAL_) << 0) | ((REG32(ADR_INFO20)) & 0x00000000))
++#define SET_INFO21(_VAL_) (REG32(ADR_INFO21)) = (((_VAL_) << 0) | ((REG32(ADR_INFO21)) & 0x00000000))
++#define SET_INFO22(_VAL_) (REG32(ADR_INFO22)) = (((_VAL_) << 0) | ((REG32(ADR_INFO22)) & 0x00000000))
++#define SET_INFO23(_VAL_) (REG32(ADR_INFO23)) = (((_VAL_) << 0) | ((REG32(ADR_INFO23)) & 0x00000000))
++#define SET_INFO24(_VAL_) (REG32(ADR_INFO24)) = (((_VAL_) << 0) | ((REG32(ADR_INFO24)) & 0x00000000))
++#define SET_INFO25(_VAL_) (REG32(ADR_INFO25)) = (((_VAL_) << 0) | ((REG32(ADR_INFO25)) & 0x00000000))
++#define SET_INFO26(_VAL_) (REG32(ADR_INFO26)) = (((_VAL_) << 0) | ((REG32(ADR_INFO26)) & 0x00000000))
++#define SET_INFO27(_VAL_) (REG32(ADR_INFO27)) = (((_VAL_) << 0) | ((REG32(ADR_INFO27)) & 0x00000000))
++#define SET_INFO28(_VAL_) (REG32(ADR_INFO28)) = (((_VAL_) << 0) | ((REG32(ADR_INFO28)) & 0x00000000))
++#define SET_INFO29(_VAL_) (REG32(ADR_INFO29)) = (((_VAL_) << 0) | ((REG32(ADR_INFO29)) & 0x00000000))
++#define SET_INFO30(_VAL_) (REG32(ADR_INFO30)) = (((_VAL_) << 0) | ((REG32(ADR_INFO30)) & 0x00000000))
++#define SET_INFO31(_VAL_) (REG32(ADR_INFO31)) = (((_VAL_) << 0) | ((REG32(ADR_INFO31)) & 0x00000000))
++#define SET_INFO32(_VAL_) (REG32(ADR_INFO32)) = (((_VAL_) << 0) | ((REG32(ADR_INFO32)) & 0x00000000))
++#define SET_INFO33(_VAL_) (REG32(ADR_INFO33)) = (((_VAL_) << 0) | ((REG32(ADR_INFO33)) & 0x00000000))
++#define SET_INFO34(_VAL_) (REG32(ADR_INFO34)) = (((_VAL_) << 0) | ((REG32(ADR_INFO34)) & 0x00000000))
++#define SET_INFO35(_VAL_) (REG32(ADR_INFO35)) = (((_VAL_) << 0) | ((REG32(ADR_INFO35)) & 0x00000000))
++#define SET_INFO36(_VAL_) (REG32(ADR_INFO36)) = (((_VAL_) << 0) | ((REG32(ADR_INFO36)) & 0x00000000))
++#define SET_INFO37(_VAL_) (REG32(ADR_INFO37)) = (((_VAL_) << 0) | ((REG32(ADR_INFO37)) & 0x00000000))
++#define SET_INFO38(_VAL_) (REG32(ADR_INFO38)) = (((_VAL_) << 0) | ((REG32(ADR_INFO38)) & 0x00000000))
++#define SET_INFO_MASK(_VAL_) (REG32(ADR_INFO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_MASK)) & 0x00000000))
++#define SET_INFO_DEF_RATE(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xffffffc0))
++#define SET_INFO_MRX_OFFSET(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xfff0ffff))
++#define SET_BCAST_RATEUNKNOW(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 24) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xc0ffffff))
++#define SET_INFO_IDX_TBL_ADDR(_VAL_) (REG32(ADR_INFO_IDX_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_IDX_ADDR)) & 0x00000000))
++#define SET_INFO_LEN_TBL_ADDR(_VAL_) (REG32(ADR_INFO_LEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_LEN_ADDR)) & 0x00000000))
++#define SET_IC_TAG_31_0(_VAL_) (REG32(ADR_IC_TIME_TAG_0)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_0)) & 0x00000000))
++#define SET_IC_TAG_63_32(_VAL_) (REG32(ADR_IC_TIME_TAG_1)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_1)) & 0x00000000))
++#define SET_CH1_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffffc))
++#define SET_CH2_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 8) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffcff))
++#define SET_CH3_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 16) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffcffff))
++#define SET_RG_MAC_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_MODE)) & 0xfffffffe))
++#define SET_RG_MAC_M2M(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_MODE)) & 0xfffffffd))
++#define SET_RG_PHY_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_MAC_MODE)) & 0xfffffffb))
++#define SET_RG_LPBK_RX_EN(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_MODE)) & 0xfffffff7))
++#define SET_EXT_MAC_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_MODE)) & 0xffffffef))
++#define SET_EXT_PHY_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_MODE)) & 0xffffffdf))
++#define SET_ASIC_TAG(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 24) | ((REG32(ADR_MAC_MODE)) & 0x00ffffff))
++#define SET_HCI_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffe))
++#define SET_CO_PROC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffd))
++#define SET_MTX_MISC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffff7))
++#define SET_MTX_QUE_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffef))
++#define SET_MTX_CHST_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffdf))
++#define SET_MTX_BCN_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffbf))
++#define SET_MRX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffff7f))
++#define SET_AMPDU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffeff))
++#define SET_MMU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffdff))
++#define SET_ID_MNG_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffff7ff))
++#define SET_MBOX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffefff))
++#define SET_SCRT_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffdfff))
++#define SET_MIC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffbfff))
++#define SET_CO_PROC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffffd))
++#define SET_MTX_MISC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffff7))
++#define SET_MTX_QUE_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffef))
++#define SET_MTX_CHST_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffdf))
++#define SET_MTX_BCN_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffbf))
++#define SET_MRX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffff7f))
++#define SET_AMPDU_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffeff))
++#define SET_ID_MNG_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffbfff))
++#define SET_MBOX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffff7fff))
++#define SET_SCRT_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 16) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffeffff))
++#define SET_MIC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 17) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffdffff))
++#define SET_CO_PROC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffffd))
++#define SET_MTX_MISC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffff7))
++#define SET_MTX_QUE0_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffef))
++#define SET_MTX_QUE1_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffdf))
++#define SET_MTX_QUE2_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffbf))
++#define SET_MTX_QUE3_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffff7f))
++#define SET_MTX_QUE4_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffeff))
++#define SET_MTX_QUE5_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffdff))
++#define SET_MRX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffbff))
++#define SET_AMPDU_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffff7ff))
++#define SET_SCRT_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffdfff))
++#define SET_ID_MNG_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffbfff))
++#define SET_MBOX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffff7fff))
++#define SET_HCI_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffe))
++#define SET_CO_PROC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MTX_MISC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffff7))
++#define SET_MTX_QUE_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffef))
++#define SET_MRX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffdf))
++#define SET_AMPDU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffbf))
++#define SET_MMU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffff7f))
++#define SET_ID_MNG_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffdff))
++#define SET_MBOX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_SCRT_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffff7ff))
++#define SET_MIC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffefff))
++#define SET_MIB_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_HCI_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffe))
++#define SET_CO_PROC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MTX_MISC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffff7))
++#define SET_MTX_QUE_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffef))
++#define SET_MRX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffdf))
++#define SET_AMPDU_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffbf))
++#define SET_ID_MNG_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffefff))
++#define SET_MBOX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_SCRT_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffbfff))
++#define SET_MIC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffff7fff))
++#define SET_CO_PROC_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MRX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_AMPDU_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffff7ff))
++#define SET_SCRT_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_ID_MNG_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffbfff))
++#define SET_MBOX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffff7fff))
++#define SET_OP_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 0) | ((REG32(ADR_GLBLE_SET)) & 0xfffffffc))
++#define SET_HT_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 2) | ((REG32(ADR_GLBLE_SET)) & 0xfffffff3))
++#define SET_QOS_EN(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 4) | ((REG32(ADR_GLBLE_SET)) & 0xffffffef))
++#define SET_PB_OFFSET(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 8) | ((REG32(ADR_GLBLE_SET)) & 0xffff00ff))
++#define SET_SNIFFER_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 16) | ((REG32(ADR_GLBLE_SET)) & 0xfffeffff))
++#define SET_DUP_FLT(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 17) | ((REG32(ADR_GLBLE_SET)) & 0xfffdffff))
++#define SET_TX_PKT_RSVD(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 18) | ((REG32(ADR_GLBLE_SET)) & 0xffe3ffff))
++#define SET_AMPDU_SNIFFER(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 21) | ((REG32(ADR_GLBLE_SET)) & 0xffdfffff))
++#define SET_REASON_TRAP0(_VAL_) (REG32(ADR_REASON_TRAP0)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP0)) & 0x00000000))
++#define SET_REASON_TRAP1(_VAL_) (REG32(ADR_REASON_TRAP1)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP1)) & 0x00000000))
++#define SET_BSSID_31_0(_VAL_) (REG32(ADR_BSSID_0)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_0)) & 0x00000000))
++#define SET_BSSID_47_32(_VAL_) (REG32(ADR_BSSID_1)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_1)) & 0xffff0000))
++#define SET_SCRT_STATE(_VAL_) (REG32(ADR_SCRT_STATE)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_STATE)) & 0xfffffff0))
++#define SET_STA_MAC_31_0(_VAL_) (REG32(ADR_STA_MAC_0)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_0)) & 0x00000000))
++#define SET_STA_MAC_47_32(_VAL_) (REG32(ADR_STA_MAC_1)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_1)) & 0xffff0000))
++#define SET_PAIR_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_SET)) & 0xfffffff8))
++#define SET_GRP_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 3) | ((REG32(ADR_SCRT_SET)) & 0xffffffc7))
++#define SET_SCRT_PKT_ID(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 6) | ((REG32(ADR_SCRT_SET)) & 0xffffe03f))
++#define SET_SCRT_RPLY_IGNORE(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 16) | ((REG32(ADR_SCRT_SET)) & 0xfffeffff))
++#define SET_COEXIST_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX0)) & 0xfffffffe))
++#define SET_WIRE_MODE(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 1) | ((REG32(ADR_BTCX0)) & 0xfffffff1))
++#define SET_WL_RX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 4) | ((REG32(ADR_BTCX0)) & 0xffffffef))
++#define SET_WL_TX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 5) | ((REG32(ADR_BTCX0)) & 0xffffffdf))
++#define SET_GURAN_USE_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX0)) & 0xfffffeff))
++#define SET_GURAN_USE_CTRL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 9) | ((REG32(ADR_BTCX0)) & 0xfffffdff))
++#define SET_BEACON_TIMEOUT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 10) | ((REG32(ADR_BTCX0)) & 0xfffffbff))
++#define SET_WLAN_ACT_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 11) | ((REG32(ADR_BTCX0)) & 0xfffff7ff))
++#define SET_DUAL_ANT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 12) | ((REG32(ADR_BTCX0)) & 0xffffefff))
++#define SET_TRSW_PHY_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX0)) & 0xfffeffff))
++#define SET_WIFI_TX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 17) | ((REG32(ADR_BTCX0)) & 0xfffdffff))
++#define SET_WIFI_RX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 18) | ((REG32(ADR_BTCX0)) & 0xfffbffff))
++#define SET_BT_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 19) | ((REG32(ADR_BTCX0)) & 0xfff7ffff))
++#define SET_BT_PRI_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX1)) & 0xffffff00))
++#define SET_BT_STA_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX1)) & 0xffff00ff))
++#define SET_BEACON_TIMEOUT(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX1)) & 0xff00ffff))
++#define SET_WLAN_REMAIN_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 24) | ((REG32(ADR_BTCX1)) & 0x00ffffff))
++#define SET_SW_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffe))
++#define SET_SW_WL_TX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 1) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffd))
++#define SET_SW_WL_RX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 2) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffb))
++#define SET_SW_BT_TRX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 3) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffff7))
++#define SET_BT_TXBAR_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 4) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffef))
++#define SET_BT_TXBAR_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 5) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffdf))
++#define SET_BT_BUSY_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffeff))
++#define SET_BT_BUSY_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 9) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffdff))
++#define SET_G0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 2) | ((REG32(ADR_MIB_EN)) & 0xfffffffb))
++#define SET_G0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 3) | ((REG32(ADR_MIB_EN)) & 0xfffffff7))
++#define SET_G1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 4) | ((REG32(ADR_MIB_EN)) & 0xffffffef))
++#define SET_G1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MIB_EN)) & 0xffffffdf))
++#define SET_Q0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MIB_EN)) & 0xffffffbf))
++#define SET_Q0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MIB_EN)) & 0xffffff7f))
++#define SET_Q1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MIB_EN)) & 0xfffffeff))
++#define SET_Q1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 9) | ((REG32(ADR_MIB_EN)) & 0xfffffdff))
++#define SET_Q2_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MIB_EN)) & 0xfffffbff))
++#define SET_Q2_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MIB_EN)) & 0xfffff7ff))
++#define SET_Q3_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MIB_EN)) & 0xffffefff))
++#define SET_Q3_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MIB_EN)) & 0xffffdfff))
++#define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MIB_EN)) & 0xffffbfff))
++#define SET_SCRT_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MIB_EN)) & 0xffff7fff))
++#define SET_MISC_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MIB_EN)) & 0xfffeffff))
++#define SET_MISC_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MIB_EN)) & 0xfffdffff))
++#define SET_MTX_WSID0_SUCC(_VAL_) (REG32(ADR_MTX_WSID0_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_SUCC)) & 0xffff0000))
++#define SET_MTX_WSID0_FRM(_VAL_) (REG32(ADR_MTX_WSID0_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_FRM)) & 0xffff0000))
++#define SET_MTX_WSID0_RETRY(_VAL_) (REG32(ADR_MTX_WSID0_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_RETRY)) & 0xffff0000))
++#define SET_MTX_WSID0_TOTAL(_VAL_) (REG32(ADR_MTX_WSID0_TOTAL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_TOTAL)) & 0xffff0000))
++#define SET_MTX_GRP(_VAL_) (REG32(ADR_MTX_GROUP)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_GROUP)) & 0xfff00000))
++#define SET_MTX_FAIL(_VAL_) (REG32(ADR_MTX_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FAIL)) & 0xffff0000))
++#define SET_MTX_RETRY(_VAL_) (REG32(ADR_MTX_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RETRY)) & 0xfff00000))
++#define SET_MTX_MULTI_RETRY(_VAL_) (REG32(ADR_MTX_MULTI_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MULTI_RETRY)) & 0xfff00000))
++#define SET_MTX_RTS_SUCC(_VAL_) (REG32(ADR_MTX_RTS_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_SUCCESS)) & 0xffff0000))
++#define SET_MTX_RTS_FAIL(_VAL_) (REG32(ADR_MTX_RTS_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_FAIL)) & 0xffff0000))
++#define SET_MTX_ACK_FAIL(_VAL_) (REG32(ADR_MTX_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_FAIL)) & 0xffff0000))
++#define SET_MTX_FRM(_VAL_) (REG32(ADR_MTX_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FRM)) & 0xfff00000))
++#define SET_MTX_ACK_TX(_VAL_) (REG32(ADR_MTX_ACK_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_TX)) & 0xffff0000))
++#define SET_MTX_CTS_TX(_VAL_) (REG32(ADR_MTX_CTS_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_CTS_TX)) & 0xffff0000))
++#define SET_MRX_DUP(_VAL_) (REG32(ADR_MRX_DUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DUP_FRM)) & 0xffff0000))
++#define SET_MRX_FRG(_VAL_) (REG32(ADR_MRX_FRG_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FRG_FRM)) & 0xfff00000))
++#define SET_MRX_GRP(_VAL_) (REG32(ADR_MRX_GROUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_GROUP_FRM)) & 0xfff00000))
++#define SET_MRX_FCS_ERR(_VAL_) (REG32(ADR_MRX_FCS_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_ERR)) & 0xffff0000))
++#define SET_MRX_FCS_SUC(_VAL_) (REG32(ADR_MRX_FCS_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_SUCC)) & 0xffff0000))
++#define SET_MRX_MISS(_VAL_) (REG32(ADR_MRX_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MISS)) & 0xffff0000))
++#define SET_MRX_ALC_FAIL(_VAL_) (REG32(ADR_MRX_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ALC_FAIL)) & 0xffff0000))
++#define SET_MRX_DAT_NTF(_VAL_) (REG32(ADR_MRX_DAT_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_NTF)) & 0xffff0000))
++#define SET_MRX_RTS_NTF(_VAL_) (REG32(ADR_MRX_RTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_RTS_NTF)) & 0xffff0000))
++#define SET_MRX_CTS_NTF(_VAL_) (REG32(ADR_MRX_CTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CTS_NTF)) & 0xffff0000))
++#define SET_MRX_ACK_NTF(_VAL_) (REG32(ADR_MRX_ACK_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ACK_NTF)) & 0xffff0000))
++#define SET_MRX_BA_NTF(_VAL_) (REG32(ADR_MRX_BA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_NTF)) & 0xffff0000))
++#define SET_MRX_DATA_NTF(_VAL_) (REG32(ADR_MRX_DATA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DATA_NTF)) & 0xffff0000))
++#define SET_MRX_MNG_NTF(_VAL_) (REG32(ADR_MRX_MNG_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MNG_NTF)) & 0xffff0000))
++#define SET_MRX_DAT_CRC_NTF(_VAL_) (REG32(ADR_MRX_DAT_CRC_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_CRC_NTF)) & 0xffff0000))
++#define SET_MRX_BAR_NTF(_VAL_) (REG32(ADR_MRX_BAR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BAR_NTF)) & 0xffff0000))
++#define SET_MRX_MB_MISS(_VAL_) (REG32(ADR_MRX_MB_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MB_MISS)) & 0xffff0000))
++#define SET_MRX_NIDLE_MISS(_VAL_) (REG32(ADR_MRX_NIDLE_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_NIDLE_MISS)) & 0xffff0000))
++#define SET_MRX_CSR_NTF(_VAL_) (REG32(ADR_MRX_CSR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CSR_NTF)) & 0xffff0000))
++#define SET_DBG_Q0_SUCC(_VAL_) (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q0_FAIL(_VAL_) (REG32(ADR_DBG_Q0_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q0_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q0_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q0_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0xffff0000))
++#define SET_DBG_Q1_SUCC(_VAL_) (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q1_FAIL(_VAL_) (REG32(ADR_DBG_Q1_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q1_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q1_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q1_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0xffff0000))
++#define SET_DBG_Q2_SUCC(_VAL_) (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q2_FAIL(_VAL_) (REG32(ADR_DBG_Q2_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q2_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q2_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q2_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0xffff0000))
++#define SET_DBG_Q3_SUCC(_VAL_) (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q3_FAIL(_VAL_) (REG32(ADR_DBG_Q3_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q3_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q3_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q3_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0xffff0000))
++#define SET_SCRT_TKIP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP0)) & 0xfff00000))
++#define SET_SCRT_TKIP_MIC_ERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP1)) & 0xfff00000))
++#define SET_SCRT_TKIP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_TKIP2)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP2)) & 0xfff00000))
++#define SET_SCRT_CCMP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_CCMP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP0)) & 0xfff00000))
++#define SET_SCRT_CCMP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_CCMP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP1)) & 0xfff00000))
++#define SET_DBG_LEN_CRC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_CRC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0xffff0000))
++#define SET_DBG_LEN_ALC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0xffff0000))
++#define SET_DBG_AMPDU_PASS(_VAL_) (REG32(ADR_DBG_AMPDU_PASS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_PASS)) & 0xffff0000))
++#define SET_DBG_AMPDU_FAIL(_VAL_) (REG32(ADR_DBG_AMPDU_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_FAIL)) & 0xffff0000))
++#define SET_RXID_ALC_CNT_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL1)) & 0xffff0000))
++#define SET_RXID_ALC_LEN_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL2)) & 0xffff0000))
++#define SET_CBR_RG_EN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_TX_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_TX_PA_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_TX_DAC_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_RX_AGC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
++#define SET_CBR_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
++#define SET_CBR_RG_RFG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
++#define SET_CBR_RG_PGAG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
++#define SET_CBR_RG_MODE(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
++#define SET_CBR_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
++#define SET_CBR_RG_EN_SX(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
++#define SET_CBR_RG_EN_RX_LNA(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
++#define SET_CBR_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
++#define SET_CBR_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
++#define SET_CBR_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
++#define SET_CBR_RG_EN_RX_TZ(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
++#define SET_CBR_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
++#define SET_CBR_RG_EN_RX_HPF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
++#define SET_CBR_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
++#define SET_CBR_RG_EN_ADC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
++#define SET_CBR_RG_EN_TX_MOD(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
++#define SET_CBR_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
++#define SET_CBR_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
++#define SET_CBR_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
++#define SET_CBR_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
++#define SET_CBR_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
++#define SET_CBR_RG_EN_TX_DPD(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
++#define SET_CBR_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
++#define SET_CBR_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
++#define SET_CBR_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
++#define SET_CBR_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
++#define SET_CBR_RG_EN_IREF_RX(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
++#define SET_CBR_RG_DCDC_MODE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffefff))
++#define SET_CBR_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffff8))
++#define SET_CBR_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffffffc7))
++#define SET_CBR_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffe3f))
++#define SET_CBR_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffff1ff))
++#define SET_CBR_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffff8fff))
++#define SET_CBR_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffc7fff))
++#define SET_CBR_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffe3ffff))
++#define SET_CBR_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xff1fffff))
++#define SET_CBR_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xf8ffffff))
++#define SET_CBR_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xc7ffffff))
++#define SET_CBR_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffe))
++#define SET_CBR_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffd))
++#define SET_CBR_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffb))
++#define SET_CBR_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffe07))
++#define SET_CBR_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffdff))
++#define SET_CBR_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffbff))
++#define SET_CBR_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffff7ff))
++#define SET_CBR_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffffcfff))
++#define SET_CBR_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffff3fff))
++#define SET_CBR_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffcffff))
++#define SET_CBR_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfff3ffff))
++#define SET_CBR_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffcfffff))
++#define SET_CBR_RG_RX_HPF3M(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffbfffff))
++#define SET_CBR_RG_RX_HPF300K(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xff7fffff))
++#define SET_CBR_RG_RX_HPFI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfcffffff))
++#define SET_CBR_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xf3ffffff))
++#define SET_CBR_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xcfffffff))
++#define SET_CBR_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffffc))
++#define SET_CBR_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffff3))
++#define SET_CBR_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffffcf))
++#define SET_CBR_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffff3f))
++#define SET_CBR_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffcff))
++#define SET_CBR_RG_RX_OUTVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffff3ff))
++#define SET_CBR_RG_RX_TZI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffcfff))
++#define SET_CBR_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffbfff))
++#define SET_CBR_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffe7fff))
++#define SET_CBR_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfff1ffff))
++#define SET_CBR_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffefffff))
++#define SET_CBR_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xff9fffff))
++#define SET_CBR_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfe7fffff))
++#define SET_CBR_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfdffffff))
++#define SET_CBR_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffffffc))
++#define SET_CBR_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffff03))
++#define SET_CBR_RG_TXPGA_STEER(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffc0ff))
++#define SET_CBR_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffff3fff))
++#define SET_CBR_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffcffff))
++#define SET_CBR_RG_PACELL_EN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffe3ffff))
++#define SET_CBR_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfe1fffff))
++#define SET_CBR_RG_PABIAS_AB(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfdffffff))
++#define SET_CBR_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xf3ffffff))
++#define SET_CBR_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xcfffffff))
++#define SET_CBR_RG_RX_SQDC(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffffff8))
++#define SET_CBR_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffffe7))
++#define SET_CBR_RG_RX_LOBUF(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffff9f))
++#define SET_CBR_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffff87f))
++#define SET_CBR_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffff87ff))
++#define SET_CBR_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffc7fff))
++#define SET_CBR_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffe3ffff))
++#define SET_CBR_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffdfffff))
++#define SET_CBR_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xff3fffff))
++#define SET_CBR_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
++#define SET_CBR_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
++#define SET_CBR_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
++#define SET_CBR_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
++#define SET_CBR_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
++#define SET_CBR_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
++#define SET_CBR_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
++#define SET_CBR_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
++#define SET_CBR_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
++#define SET_CBR_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
++#define SET_CBR_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
++#define SET_CBR_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
++#define SET_CBR_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
++#define SET_CBR_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
++#define SET_CBR_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
++#define SET_CBR_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
++#define SET_CBR_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_HPF_T1A(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffffe7))
++#define SET_CBR_RG_HPF_T1B(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffff9f))
++#define SET_CBR_RG_HPF_T1C(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffe7f))
++#define SET_CBR_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffff9ff))
++#define SET_CBR_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffe7ff))
++#define SET_CBR_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff9))
++#define SET_CBR_RG_ADC_DIVR(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_ADC_DVCMI(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffffffcf))
++#define SET_CBR_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffc3f))
++#define SET_CBR_RG_ADC_STNBY(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffbff))
++#define SET_CBR_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffff7ff))
++#define SET_CBR_RG_ADC_TSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffff0fff))
++#define SET_CBR_RG_ADC_VRSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffcffff))
++#define SET_CBR_RG_DICMP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfff3ffff))
++#define SET_CBR_RG_DIOP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffcfffff))
++#define SET_CBR_RG_DACI1ST(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffffc))
++#define SET_CBR_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffff3))
++#define SET_CBR_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffffcf))
++#define SET_CBR_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffff3f))
++#define SET_CBR_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffff9ff))
++#define SET_CBR_RG_TX_DAC_OS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffc7ff))
++#define SET_CBR_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffff3fff))
++#define SET_CBR_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfff0ffff))
++#define SET_CBR_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffefffff))
++#define SET_CBR_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffdfffff))
++#define SET_CBR_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffbfffff))
++#define SET_CBR_RG_EN_SX_R3(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_EN_SX_CH(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_EN_SX_CHP(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffef))
++#define SET_CBR_RG_EN_SX_VCO(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffdf))
++#define SET_CBR_RG_EN_SX_MOD(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffbf))
++#define SET_CBR_RG_EN_SX_LCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffff7f))
++#define SET_CBR_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_EN_SX_DELCAL(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_EN_SX_PC_BYPASS(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffbff))
++#define SET_CBR_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffff7ff))
++#define SET_CBR_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffefff))
++#define SET_CBR_RG_EN_SX_DIV(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffdfff))
++#define SET_CBR_RG_EN_SX_LPF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffbfff))
++#define SET_CBR_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xff000000))
++#define SET_CBR_RG_SX_SEL_CP(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0ffffff))
++#define SET_CBR_RG_SX_SEL_CS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0fffffff))
++#define SET_CBR_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfffff800))
++#define SET_CBR_RG_SX_SEL_C3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xffff87ff))
++#define SET_CBR_RG_SX_SEL_RS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfff07fff))
++#define SET_CBR_RG_SX_SEL_R3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfe0fffff))
++#define SET_CBR_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffffe0))
++#define SET_CBR_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffffc1f))
++#define SET_CBR_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffc3ff))
++#define SET_CBR_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffc3fff))
++#define SET_CBR_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffbffff))
++#define SET_CBR_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffc7ffff))
++#define SET_CBR_RG_SX_PFDSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffbfffff))
++#define SET_CBR_RG_SX_PFD_SET(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xff7fffff))
++#define SET_CBR_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfeffffff))
++#define SET_CBR_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfdffffff))
++#define SET_CBR_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfbffffff))
++#define SET_CBR_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xf7ffffff))
++#define SET_CBR_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xefffffff))
++#define SET_CBR_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xdfffffff))
++#define SET_CBR_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xbfffffff))
++#define SET_CBR_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffffff8))
++#define SET_CBR_RG_SX_VCORSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffffff07))
++#define SET_CBR_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffff0ff))
++#define SET_CBR_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffff0fff))
++#define SET_CBR_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfff0ffff))
++#define SET_CBR_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xff0fffff))
++#define SET_CBR_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0ffffff))
++#define SET_CBR_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0fffffff))
++#define SET_CBR_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
++#define SET_CBR_RG_SX_MOD_ERRCMP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffff3))
++#define SET_CBR_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
++#define SET_CBR_RG_SX_SDM_D1(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffbf))
++#define SET_CBR_RG_SX_SDM_D2(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffff7f))
++#define SET_CBR_RG_SDM_PASS(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffeff))
++#define SET_CBR_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
++#define SET_CBR_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
++#define SET_CBR_RG_SX_XO_GM(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
++#define SET_CBR_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
++#define SET_CBR_RG_SX_XO_SWCAP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffc3fff))
++#define SET_CBR_RG_SX_SDMLUT_INV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffbffff))
++#define SET_CBR_RG_SX_LCKEN(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
++#define SET_CBR_RG_SX_PREVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
++#define SET_CBR_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
++#define SET_CBR_RG_SX_MOD_ERR_DELAY(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xcfffffff))
++#define SET_CBR_RG_SX_MODDB(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xbfffffff))
++#define SET_CBR_RG_SX_CV_CURVE_SEL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffffffc))
++#define SET_CBR_RG_SX_SEL_DELAY(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffff83))
++#define SET_CBR_RG_SX_REF_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff87f))
++#define SET_CBR_RG_SX_VCOBY16(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff7ff))
++#define SET_CBR_RG_SX_VCOBY32(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffefff))
++#define SET_CBR_RG_SX_PH(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffdfff))
++#define SET_CBR_RG_SX_PL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffbfff))
++#define SET_CBR_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffffe))
++#define SET_CBR_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffff9))
++#define SET_CBR_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffe7))
++#define SET_CBR_RG_SX_VT_SET(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffdf))
++#define SET_CBR_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffff803f))
++#define SET_CBR_RG_IDEAL_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xf0007fff))
++#define SET_CBR_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffff9))
++#define SET_CBR_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffffe7))
++#define SET_CBR_RG_DP_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffc01f))
++#define SET_CBR_RG_DP_CK320BY2(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffbfff))
++#define SET_CBR_RG_SX_DELCTRL(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffe07fff))
++#define SET_CBR_RG_DP_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffdfffff))
++#define SET_CBR_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
++#define SET_CBR_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
++#define SET_CBR_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
++#define SET_CBR_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
++#define SET_CBR_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
++#define SET_CBR_RG_DP_RP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
++#define SET_CBR_RG_DP_RHP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
++#define SET_CBR_RG_DP_DR3(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xff8fffff))
++#define SET_CBR_RG_DP_DCP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xf87fffff))
++#define SET_CBR_RG_DP_DCS(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x87ffffff))
++#define SET_CBR_RG_DP_FBDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xfffff000))
++#define SET_CBR_RG_DP_FODIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00fff))
++#define SET_CBR_RG_DP_REFDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003fffff))
++#define SET_CBR_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
++#define SET_CBR_RG_EN_RCAL(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_RCAL_SPD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_RCAL_TMR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffe03))
++#define SET_CBR_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xffff83ff))
++#define SET_CBR_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffffff01))
++#define SET_CBR_RG_DP_BBPLL_BS_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_DP_BBPLL_BS_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffff81ff))
++#define SET_CBR_RCAL_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
++#define SET_CBR_DA_LCK_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
++#define SET_CBR_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
++#define SET_CBR_DP_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffff7))
++#define SET_CBR_CH_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffffef))
++#define SET_CBR_DA_R_CODE_LUT(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
++#define SET_CBR_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
++#define SET_CBR_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
++#define SET_CBR_DA_R_CAL_CODE(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
++#define SET_CBR_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
++#define SET_CBR_DA_DP_BBPLL_BS(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffc0fff))
++#define SET_CBR_TX_EN(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffe))
++#define SET_CBR_TX_CNT_RST(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffd))
++#define SET_CBR_IFS_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xffffff03))
++#define SET_CBR_LENGTH_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfff000ff))
++#define SET_CBR_TX_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00ffffff))
++#define SET_CBR_TC_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0xff000000))
++#define SET_CBR_PLCP_PSDU_DATA_MEM(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffffff00))
++#define SET_CBR_PLCP_PSDU_PREAMBLE_SHORT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xfffffeff))
++#define SET_CBR_PLCP_BYTE_LENGTH(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffe001ff))
++#define SET_CBR_PLCP_PSDU_RATE(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xff9fffff))
++#define SET_CBR_TAIL_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xe07fffff))
++#define SET_CBR_RG_O_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffe))
++#define SET_CBR_RG_I_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffd))
++#define SET_CBR_SEL_ADCKP_INV(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffb))
++#define SET_CBR_RG_PAD_DS(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffff7))
++#define SET_CBR_SEL_ADCKP_MUX(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffef))
++#define SET_CBR_RG_PAD_DS_CLK(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffdf))
++#define SET_CBR_INTP_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffdff))
++#define SET_CBR_IQ_SWP(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffbff))
++#define SET_CBR_RG_EN_EXT_DA(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffff7ff))
++#define SET_CBR_RG_DIS_DA_OFFSET(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffefff))
++#define SET_CBR_DBG_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfff0ffff))
++#define SET_CBR_DBG_EN(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffefffff))
++#define SET_CBR_RG_PKT_GEN_TX_CNT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0x00000000))
++#define SET_CBR_TP_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffe0))
++#define SET_CBR_IDEAL_IQ_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffdf))
++#define SET_CBR_DATA_OUT_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffe3f))
++#define SET_CBR_TWO_TONE_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffdff))
++#define SET_CBR_FREQ_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xff00ffff))
++#define SET_CBR_IQ_SCALE(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ffffff))
++#define SET_CPU_QUE_POP(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 0) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffe))
++#define SET_CPU_INT(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 2) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffb))
++#define SET_CPU_ID_TB0(_VAL_) (REG32(ADR_CPU_ID_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB0)) & 0x00000000))
++#define SET_CPU_ID_TB1(_VAL_) (REG32(ADR_CPU_ID_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB1)) & 0x00000000))
++#define SET_HW_PKTID(_VAL_) (REG32(ADR_CH0_TRIG_1)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_1)) & 0xfffff800))
++#define SET_CH0_INT_ADDR(_VAL_) (REG32(ADR_CH0_TRIG_0)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_0)) & 0x00000000))
++#define SET_PRI_HW_PKTID(_VAL_) (REG32(ADR_CH0_PRI_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_PRI_TRIG)) & 0xfffff800))
++#define SET_CH0_FULL(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffe))
++#define SET_FF0_EMPTY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffd))
++#define SET_RLS_BUSY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_STATUS)) & 0xfffffdff))
++#define SET_RLS_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MCU_STATUS)) & 0xfffffbff))
++#define SET_RTN_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MCU_STATUS)) & 0xfffff7ff))
++#define SET_RLS_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MCU_STATUS)) & 0xff00ffff))
++#define SET_RTN_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MCU_STATUS)) & 0x00ffffff))
++#define SET_FF0_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffffe0))
++#define SET_FF1_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfffffe1f))
++#define SET_FF3_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffc7ff))
++#define SET_FF5_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 17) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfff1ffff))
++#define SET_FF6_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xff8fffff))
++#define SET_FF7_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 23) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfc7fffff))
++#define SET_FF8_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 26) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xe3ffffff))
++#define SET_FF9_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 29) | ((REG32(ADR_RD_IN_FFCNT1)) & 0x1fffffff))
++#define SET_FF10_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffff8))
++#define SET_FF11_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 3) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffffc7))
++#define SET_FF12_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 6) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffe3f))
++#define SET_FF13_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 9) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffff9ff))
++#define SET_FF14_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffe7ff))
++#define SET_FF15_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 13) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffff9fff))
++#define SET_FF4_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfff07fff))
++#define SET_FF2_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xff8fffff))
++#define SET_CH1_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffd))
++#define SET_CH2_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffb))
++#define SET_CH3_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffff7))
++#define SET_CH4_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffef))
++#define SET_CH5_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffdf))
++#define SET_CH6_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffbf))
++#define SET_CH7_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffff7f))
++#define SET_CH8_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffeff))
++#define SET_CH9_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffdff))
++#define SET_CH10_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffbff))
++#define SET_CH11_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffff7ff))
++#define SET_CH12_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffefff))
++#define SET_CH13_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffdfff))
++#define SET_CH14_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffbfff))
++#define SET_CH15_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffff7fff))
++#define SET_HALT_CH0(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffe))
++#define SET_HALT_CH1(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffd))
++#define SET_HALT_CH2(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffb))
++#define SET_HALT_CH3(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 3) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffff7))
++#define SET_HALT_CH4(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffef))
++#define SET_HALT_CH5(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffdf))
++#define SET_HALT_CH6(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffbf))
++#define SET_HALT_CH7(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffff7f))
++#define SET_HALT_CH8(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffeff))
++#define SET_HALT_CH9(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 9) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffdff))
++#define SET_HALT_CH10(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 10) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffbff))
++#define SET_HALT_CH11(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 11) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffff7ff))
++#define SET_HALT_CH12(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 12) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffefff))
++#define SET_HALT_CH13(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 13) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffdfff))
++#define SET_HALT_CH14(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 14) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffbfff))
++#define SET_HALT_CH15(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 15) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffff7fff))
++#define SET_STOP_MBOX(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffeffff))
++#define SET_MB_ERR_AUTO_HALT_EN(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 20) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffefffff))
++#define SET_MB_EXCEPT_CLR(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 21) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffdfffff))
++#define SET_MB_EXCEPT_CASE(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 24) | ((REG32(ADR_MBOX_HALT_CFG)) & 0x00ffffff))
++#define SET_MB_DBG_TIME_STEP(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG1)) & 0xffff0000))
++#define SET_DBG_TYPE(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffcffff))
++#define SET_MB_DBG_CLR(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffbffff))
++#define SET_DBG_ALC_LOG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfff7ffff))
++#define SET_MB_DBG_COUNTER_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfeffffff))
++#define SET_MB_DBG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG1)) & 0x7fffffff))
++#define SET_MB_DBG_RECORD_CNT(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000))
++#define SET_MB_DBG_LENGTH(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff))
++#define SET_MB_DBG_CFG_ADDR(_VAL_) (REG32(ADR_MB_DBG_CFG3)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG3)) & 0x00000000))
++#define SET_DBG_HWID0_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffe))
++#define SET_DBG_HWID1_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 1) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffd))
++#define SET_DBG_HWID2_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 2) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffb))
++#define SET_DBG_HWID3_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 3) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffff7))
++#define SET_DBG_HWID4_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 4) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffef))
++#define SET_DBG_HWID5_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 5) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffdf))
++#define SET_DBG_HWID6_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 6) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffbf))
++#define SET_DBG_HWID7_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 7) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffff7f))
++#define SET_DBG_HWID8_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 8) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffeff))
++#define SET_DBG_HWID9_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 9) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffdff))
++#define SET_DBG_HWID10_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 10) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffbff))
++#define SET_DBG_HWID11_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 11) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffff7ff))
++#define SET_DBG_HWID12_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 12) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffefff))
++#define SET_DBG_HWID13_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 13) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffdfff))
++#define SET_DBG_HWID14_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 14) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffbfff))
++#define SET_DBG_HWID15_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 15) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffff7fff))
++#define SET_DBG_HWID0_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffeffff))
++#define SET_DBG_HWID1_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 17) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffdffff))
++#define SET_DBG_HWID2_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffbffff))
++#define SET_DBG_HWID3_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfff7ffff))
++#define SET_DBG_HWID4_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 20) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffefffff))
++#define SET_DBG_HWID5_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 21) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffdfffff))
++#define SET_DBG_HWID6_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 22) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffbfffff))
++#define SET_DBG_HWID7_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 23) | ((REG32(ADR_MB_DBG_CFG4)) & 0xff7fffff))
++#define SET_DBG_HWID8_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfeffffff))
++#define SET_DBG_HWID9_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 25) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfdffffff))
++#define SET_DBG_HWID10_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 26) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfbffffff))
++#define SET_DBG_HWID11_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 27) | ((REG32(ADR_MB_DBG_CFG4)) & 0xf7ffffff))
++#define SET_DBG_HWID12_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 28) | ((REG32(ADR_MB_DBG_CFG4)) & 0xefffffff))
++#define SET_DBG_HWID13_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 29) | ((REG32(ADR_MB_DBG_CFG4)) & 0xdfffffff))
++#define SET_DBG_HWID14_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 30) | ((REG32(ADR_MB_DBG_CFG4)) & 0xbfffffff))
++#define SET_DBG_HWID15_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG4)) & 0x7fffffff))
++#define SET_MB_OUT_QUEUE_EN(_VAL_) (REG32(ADR_MB_OUT_QUEUE_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0xfffffffd))
++#define SET_CH0_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffe))
++#define SET_CH1_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffd))
++#define SET_CH2_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffb))
++#define SET_CH3_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffff7))
++#define SET_CH4_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffef))
++#define SET_CH5_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffdf))
++#define SET_CH6_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffbf))
++#define SET_CH7_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffff7f))
++#define SET_CH8_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffeff))
++#define SET_CH9_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffdff))
++#define SET_CH10_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffbff))
++#define SET_CH11_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffff7ff))
++#define SET_CH12_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffefff))
++#define SET_CH13_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffdfff))
++#define SET_CH14_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffbfff))
++#define SET_CH15_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 15) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffff7fff))
++#define SET_FFO0_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffffffe0))
++#define SET_FFO1_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffffc1f))
++#define SET_FFO2_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffff3ff))
++#define SET_FFO3_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfff07fff))
++#define SET_FFO4_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffcfffff))
++#define SET_FFO5_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xf1ffffff))
++#define SET_FFO6_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffff0))
++#define SET_FFO7_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffc1f))
++#define SET_FFO8_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xffff83ff))
++#define SET_FFO9_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfff07fff))
++#define SET_FFO10_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xff0fffff))
++#define SET_FFO11_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xc1ffffff))
++#define SET_FFO12_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffffff8))
++#define SET_FFO13_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffffff9f))
++#define SET_FFO14_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffff3ff))
++#define SET_FFO15_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffe07fff))
++#define SET_CH0_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffe))
++#define SET_CH1_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffd))
++#define SET_CH2_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffb))
++#define SET_CH3_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffff7))
++#define SET_CH4_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffef))
++#define SET_CH5_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffdf))
++#define SET_CH6_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffbf))
++#define SET_CH7_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffff7f))
++#define SET_CH8_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffeff))
++#define SET_CH9_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffdff))
++#define SET_CH10_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffbff))
++#define SET_CH11_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffff7ff))
++#define SET_CH12_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffefff))
++#define SET_CH13_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffdfff))
++#define SET_CH14_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffbfff))
++#define SET_CH15_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffff7fff))
++#define SET_CH0_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffe))
++#define SET_CH1_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 1) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffd))
++#define SET_CH2_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 2) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffb))
++#define SET_CH3_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 3) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffff7))
++#define SET_CH4_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 4) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffef))
++#define SET_CH5_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 5) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffdf))
++#define SET_CH6_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 6) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffbf))
++#define SET_CH7_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 7) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffff7f))
++#define SET_CH8_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffeff))
++#define SET_CH9_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 9) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffdff))
++#define SET_CH10_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 10) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffbff))
++#define SET_CH11_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 11) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffff7ff))
++#define SET_CH12_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 12) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffefff))
++#define SET_CH13_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 13) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffdfff))
++#define SET_CH14_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 14) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffbfff))
++#define SET_CH15_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 15) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffff7fff))
++#define SET_MB_LOW_THOLD_EN(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 31) | ((REG32(ADR_MB_THRESHOLD6)) & 0x7fffffff))
++#define SET_CH0_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffffe0))
++#define SET_CH1_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffe0ff))
++#define SET_CH2_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffe0ffff))
++#define SET_CH3_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD7)) & 0xe0ffffff))
++#define SET_CH4_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffffe0))
++#define SET_CH5_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffe0ff))
++#define SET_CH6_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffe0ffff))
++#define SET_CH7_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD8)) & 0xe0ffffff))
++#define SET_CH8_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffffe0))
++#define SET_CH9_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffe0ff))
++#define SET_CH10_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffe0ffff))
++#define SET_CH11_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD9)) & 0xe0ffffff))
++#define SET_CH12_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffffe0))
++#define SET_CH13_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffe0ff))
++#define SET_CH14_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffe0ffff))
++#define SET_CH15_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD10)) & 0xe0ffffff))
++#define SET_TRASH_TIMEOUT_EN(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffe))
++#define SET_TRASH_CAN_INT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffd))
++#define SET_TRASH_INT_ID(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffff80f))
++#define SET_TRASH_TIMEOUT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfc00ffff))
++#define SET_CH0_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffe))
++#define SET_CH1_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffd))
++#define SET_CH2_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffb))
++#define SET_CH3_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffff7))
++#define SET_CH4_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffef))
++#define SET_CH5_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffdf))
++#define SET_CH6_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffbf))
++#define SET_CH7_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffff7f))
++#define SET_CH8_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffeff))
++#define SET_CH9_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffdff))
++#define SET_CH10_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffbff))
++#define SET_CH11_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffff7ff))
++#define SET_CH12_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffefff))
++#define SET_CH13_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffdfff))
++#define SET_CH14_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffbfff))
++#define SET_CPU_ID_TB2(_VAL_) (REG32(ADR_CPU_ID_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB2)) & 0x00000000))
++#define SET_CPU_ID_TB3(_VAL_) (REG32(ADR_CPU_ID_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB3)) & 0x00000000))
++#define SET_IQ_LOG_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0xfffffffe))
++#define SET_IQ_LOG_STOP_MODE(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xfffffffe))
++#define SET_GPIO_STOP_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffef))
++#define SET_GPIO_STOP_POL(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffdf))
++#define SET_IQ_LOG_TIMER(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x0000ffff))
++#define SET_IQ_LOG_LEN(_VAL_) (REG32(ADR_PHY_IQ_LOG_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000))
++#define SET_IQ_LOG_TAIL_ADR(_VAL_) (REG32(ADR_PHY_IQ_LOG_PTR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_PTR)) & 0xffff0000))
++#define SET_ALC_LENG(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 0) | ((REG32(ADR_WR_ALC)) & 0xfffc0000))
++#define SET_CH0_DYN_PRI(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 20) | ((REG32(ADR_WR_ALC)) & 0xffcfffff))
++#define SET_MCU_PKTID(_VAL_) (REG32(ADR_GETID)) = (((_VAL_) << 0) | ((REG32(ADR_GETID)) & 0x00000000))
++#define SET_CH0_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffffc))
++#define SET_CH1_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_STA_PRI)) & 0xffffffcf))
++#define SET_CH2_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffcff))
++#define SET_CH3_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_STA_PRI)) & 0xffffcfff))
++#define SET_ID_TB0(_VAL_) (REG32(ADR_RD_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID0)) & 0x00000000))
++#define SET_ID_TB1(_VAL_) (REG32(ADR_RD_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID1)) & 0x00000000))
++#define SET_ID_MNG_HALT(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_CFG)) & 0xffffffef))
++#define SET_ID_MNG_ERR_HALT_EN(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_CFG)) & 0xffffffdf))
++#define SET_ID_EXCEPT_FLG_CLR(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_CFG)) & 0xffffffbf))
++#define SET_ID_EXCEPT_FLG(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_CFG)) & 0xffffff7f))
++#define SET_ID_FULL(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 0) | ((REG32(ADR_IMD_STA)) & 0xfffffffe))
++#define SET_ID_MNG_BUSY(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 1) | ((REG32(ADR_IMD_STA)) & 0xfffffffd))
++#define SET_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 2) | ((REG32(ADR_IMD_STA)) & 0xfffffffb))
++#define SET_CH0_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_STA)) & 0xffffffef))
++#define SET_CH1_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_STA)) & 0xffffffdf))
++#define SET_CH2_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_STA)) & 0xffffffbf))
++#define SET_CH3_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_STA)) & 0xffffff7f))
++#define SET_REQ_LOCK_INT_EN(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 8) | ((REG32(ADR_IMD_STA)) & 0xfffffeff))
++#define SET_REQ_LOCK_INT(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 9) | ((REG32(ADR_IMD_STA)) & 0xfffffdff))
++#define SET_MCU_ALC_READY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_STA)) & 0xfffffffe))
++#define SET_ALC_FAIL(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 1) | ((REG32(ADR_ALC_STA)) & 0xfffffffd))
++#define SET_ALC_BUSY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 2) | ((REG32(ADR_ALC_STA)) & 0xfffffffb))
++#define SET_CH0_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 4) | ((REG32(ADR_ALC_STA)) & 0xffffffef))
++#define SET_CH1_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 5) | ((REG32(ADR_ALC_STA)) & 0xffffffdf))
++#define SET_CH2_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 6) | ((REG32(ADR_ALC_STA)) & 0xffffffbf))
++#define SET_CH3_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 7) | ((REG32(ADR_ALC_STA)) & 0xffffff7f))
++#define SET_ALC_INT_ID(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_STA)) & 0xffff80ff))
++#define SET_ALC_TIMEOUT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_STA)) & 0xfc00ffff))
++#define SET_ALC_TIMEOUT_INT_EN(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 30) | ((REG32(ADR_ALC_STA)) & 0xbfffffff))
++#define SET_ALC_TIMEOUT_INT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_STA)) & 0x7fffffff))
++#define SET_TX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffffff00))
++#define SET_RX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffff00ff))
++#define SET_TX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffffff00))
++#define SET_RX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffff00ff))
++#define SET_ID_THOLD_RX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfffeffff))
++#define SET_RX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 17) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfff1ffff))
++#define SET_ID_THOLD_TX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 20) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffefffff))
++#define SET_TX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 21) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xff1fffff))
++#define SET_ID_THOLD_INT_EN(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfeffffff))
++#define SET_TX_ID_TB0(_VAL_) (REG32(ADR_TX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID0)) & 0x00000000))
++#define SET_TX_ID_TB1(_VAL_) (REG32(ADR_TX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID1)) & 0x00000000))
++#define SET_RX_ID_TB0(_VAL_) (REG32(ADR_RX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID0)) & 0x00000000))
++#define SET_RX_ID_TB1(_VAL_) (REG32(ADR_RX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID1)) & 0x00000000))
++#define SET_DOUBLE_RLS_INT_EN(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 0) | ((REG32(ADR_RTN_STA)) & 0xfffffffe))
++#define SET_ID_DOUBLE_RLS_INT(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 1) | ((REG32(ADR_RTN_STA)) & 0xfffffffd))
++#define SET_DOUBLE_RLS_ID(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 8) | ((REG32(ADR_RTN_STA)) & 0xffff80ff))
++#define SET_ID_LEN_THOLD_INT_EN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffe))
++#define SET_ALL_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 1) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffd))
++#define SET_TX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 2) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffb))
++#define SET_RX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 3) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffff7))
++#define SET_ID_TX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 4) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffffe00f))
++#define SET_ID_RX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 13) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffc01fff))
++#define SET_ID_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 22) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x803fffff))
++#define SET_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffffe00))
++#define SET_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 9) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffc01ff))
++#define SET_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 18) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xf803ffff))
++#define SET_CH_ARB_EN(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffffe))
++#define SET_CH_PRI1(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffffcf))
++#define SET_CH_PRI2(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffcff))
++#define SET_CH_PRI3(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffcfff))
++#define SET_CH_PRI4(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 16) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffcffff))
++#define SET_TX_ID_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xffffff80))
++#define SET_TX_PAGE_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xfffe00ff))
++#define SET_ID_PAGE_MAX_SIZE(_VAL_) (REG32(ADR_ID_INFO_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ID_INFO_STA)) & 0xfffffe00))
++#define SET_TX_PAGE_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xfffffe00))
++#define SET_TX_COUNT_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xff00ffff))
++#define SET_TX_LIMIT_INT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 30) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xbfffffff))
++#define SET_TX_LIMIT_INT_EN(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 31) | ((REG32(ADR_TX_LIMIT_INTR)) & 0x7fffffff))
++#define SET_TX_PAGE_USE_7_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffff00))
++#define SET_TX_ID_USE_5_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffc0ff))
++#define SET_EDCA0_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 14) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xfffc3fff))
++#define SET_EDCA1_FFO_CNT_3_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 18) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffc3ffff))
++#define SET_EDCA2_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xf83fffff))
++#define SET_EDCA3_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 27) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0x07ffffff))
++#define SET_ID_TB2(_VAL_) (REG32(ADR_RD_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID2)) & 0x00000000))
++#define SET_ID_TB3(_VAL_) (REG32(ADR_RD_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID3)) & 0x00000000))
++#define SET_TX_ID_TB2(_VAL_) (REG32(ADR_TX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID2)) & 0x00000000))
++#define SET_TX_ID_TB3(_VAL_) (REG32(ADR_TX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID3)) & 0x00000000))
++#define SET_RX_ID_TB2(_VAL_) (REG32(ADR_RX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID2)) & 0x00000000))
++#define SET_RX_ID_TB3(_VAL_) (REG32(ADR_RX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID3)) & 0x00000000))
++#define SET_TX_PAGE_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffffe00))
++#define SET_TX_ID_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffe01ff))
++#define SET_EDCA4_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xffe1ffff))
++#define SET_TX_PAGE_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffffe00))
++#define SET_TX_ID_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffe01ff))
++#define SET_EDCA1_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 21) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfc1fffff))
++#define SET_EDCA4_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 26) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xc3ffffff))
++#define SET_TX_PAGE_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffffe00))
++#define SET_TX_ID_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffe01ff))
++#define SET_EDCA2_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xffc1ffff))
++#define SET_EDCA3_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xf83fffff))
++#define SET_TX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfffffe00))
++#define SET_RX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfe00ffff))
++#define SET_MAX_ALL_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INFO)) & 0xffffff00))
++#define SET_MAX_TX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_ID_INFO)) & 0xffff00ff))
++#define SET_MAX_RX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_ID_INFO)) & 0xff00ffff))
++#define SET_MAX_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffffe00))
++#define SET_MAX_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 9) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffc01ff))
++#define SET_MAX_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 18) | ((REG32(ADR_ALC_ID_INF1)) & 0xf803ffff))
++#define SET_RG_PMDLBK(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_0)) & 0xfffffffe))
++#define SET_RG_RDYACK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff9))
++#define SET_RG_ADEDGE_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff7))
++#define SET_RG_SIGN_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_0)) & 0xffffffef))
++#define SET_RG_IQ_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_0)) & 0xffffffdf))
++#define SET_RG_Q_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_0)) & 0xffffffbf))
++#define SET_RG_I_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_EN_0)) & 0xffffff7f))
++#define SET_RG_BYPASS_ACI(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_0)) & 0xfffffeff))
++#define SET_RG_LBK_ANA_PATH(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_EN_0)) & 0xfffffdff))
++#define SET_RG_SPECTRUM_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_EN_0)) & 0xfffff3ff))
++#define SET_RG_SPECTRUM_BW(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_0)) & 0xffffcfff))
++#define SET_RG_SPECTRUM_FREQ_MANUAL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_0)) & 0xffffbfff))
++#define SET_RG_SPECTRUM_EN(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_0)) & 0xffff7fff))
++#define SET_RG_TXPWRLVL_SET(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_0)) & 0xff00ffff))
++#define SET_RG_TXPWRLVL_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_EN_0)) & 0xfeffffff))
++#define SET_RG_RF_BB_CLK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_EN_0)) & 0x7fffffff))
++#define SET_RG_PHY_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffe))
++#define SET_RG_PHYRX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffd))
++#define SET_RG_PHYTX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffb))
++#define SET_RG_PHY11GN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_1)) & 0xfffffff7))
++#define SET_RG_PHY11B_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_1)) & 0xffffffef))
++#define SET_RG_PHYRXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_1)) & 0xffffffdf))
++#define SET_RG_PHYTXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_1)) & 0xffffffbf))
++#define SET_RG_PHY11BGN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_1)) & 0xfffffeff))
++#define SET_RG_FORCE_11GN_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_1)) & 0xffffefff))
++#define SET_RG_FORCE_11B_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 13) | ((REG32(ADR_PHY_EN_1)) & 0xffffdfff))
++#define SET_RG_FFT_MEM_CLK_EN_RX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_1)) & 0xffffbfff))
++#define SET_RG_FFT_MEM_CLK_EN_TX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_1)) & 0xffff7fff))
++#define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_1)) & 0xfff0ffff))
++#define SET_RG_SPECTRUM_FREQ(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_EN_1)) & 0xc00fffff))
++#define SET_SVN_VERSION(_VAL_) (REG32(ADR_SVN_VERSION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SVN_VERSION_REG)) & 0x00000000))
++#define SET_RG_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffff0000))
++#define SET_RG_PKT_MODE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xfff8ffff))
++#define SET_RG_CH_BW(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 19) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffc7ffff))
++#define SET_RG_PRM(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 22) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffbfffff))
++#define SET_RG_SHORTGI(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xff7fffff))
++#define SET_RG_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0x80ffffff))
++#define SET_RG_L_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xfffff000))
++#define SET_RG_L_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff8fff))
++#define SET_RG_SERVICE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0x0000ffff))
++#define SET_RG_SMOOTHING(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffe))
++#define SET_RG_NO_SOUND(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffd))
++#define SET_RG_AGGREGATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffb))
++#define SET_RG_STBC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffe7))
++#define SET_RG_FEC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffdf))
++#define SET_RG_N_ESS(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffff3f))
++#define SET_RG_TXPWRLVL(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffff00ff))
++#define SET_RG_TX_START(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffffe))
++#define SET_RG_IFS_TIME(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xffffff03))
++#define SET_RG_CONTINUOUS_DATA(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffeff))
++#define SET_RG_DATA_SEL(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffff9ff))
++#define SET_RG_TX_D(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xff00ffff))
++#define SET_RG_TX_CNT_TARGET(_VAL_) (REG32(ADR_PHY_PKT_GEN_4)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_4)) & 0x00000000))
++#define SET_RG_FFT_IFFT_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_REG_00)) & 0xffffff3f))
++#define SET_RG_DAC_DBG_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_00)) & 0xfffffeff))
++#define SET_RG_DAC_SGN_SWAP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_REG_00)) & 0xfffffdff))
++#define SET_RG_TXD_SEL(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_REG_00)) & 0xfffff3ff))
++#define SET_RG_UP8X(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_00)) & 0xff00ffff))
++#define SET_RG_IQ_DC_BYP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_00)) & 0xfeffffff))
++#define SET_RG_IQ_DC_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_00)) & 0xcfffffff))
++#define SET_RG_DAC_DCEN(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_01)) & 0xfffffffe))
++#define SET_RG_DAC_DCQ(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_01)) & 0xffffc00f))
++#define SET_RG_DAC_DCI(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_01)) & 0xfc00ffff))
++#define SET_RG_PGA_REFDB_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffffff80))
++#define SET_RG_PGA_REFDB_TOP(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffff80ff))
++#define SET_RG_PGA_REF_UND(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xfc00ffff))
++#define SET_RG_RF_REF_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_02_AGC)) & 0x0fffffff))
++#define SET_RG_PGAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xfffffff0))
++#define SET_RG_PGAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffffef))
++#define SET_RG_RFGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff9f))
++#define SET_RG_RFGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff7f))
++#define SET_RG_WAIT_T_RXAGC(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffc0ff))
++#define SET_RG_RXAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffbfff))
++#define SET_RG_RXAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffff7fff))
++#define SET_RG_WAIT_T_FINAL(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffc0ffff))
++#define SET_RG_WAIT_T(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xc0ffffff))
++#define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffffff0))
++#define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffffff0f))
++#define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffff0ff))
++#define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffff0fff))
++#define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfff0ffff))
++#define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xff0fffff))
++#define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xf0ffffff))
++#define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_04_AGC)) & 0x0fffffff))
++#define SET_RG_MG_PGA_JB_TH(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xfffffff0))
++#define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xffe0ffff))
++#define SET_RG_WR_RFGC_INIT_SET(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 21) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff9fffff))
++#define SET_RG_WR_RFGC_INIT_EN(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff7fffff))
++#define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xe0ffffff))
++#define SET_RG_AGC_THRESHOLD(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xffffc000))
++#define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xff80ffff))
++#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xfcffffff))
++#define SET_RG_WR_ACI_GAIN_INI_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffffff00))
++#define SET_RG_WR_ACI_GAIN_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffff00ff))
++#define SET_RG_ACI_DAGC_SET_VALUE_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xff80ffff))
++#define SET_RG_WR_ACI_GAIN_OW_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x7fffffff))
++#define SET_RG_ACI_POINT_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xffffff00))
++#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xfffffcff))
++#define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00ffffff))
++#define SET_RG_ACI_DAGC_SET_VALUE_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffffff80))
++#define SET_RG_ACI_GAIN_INI_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffff00ff))
++#define SET_RG_ACI_GAIN_OW_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xff00ffff))
++#define SET_RG_ACI_GAIN_OW_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x7fffffff))
++#define SET_RO_CCA_PWR_MA_11GN(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffffff80))
++#define SET_RO_ED_STATE(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffff7fff))
++#define SET_RO_CCA_PWR_MA_11B(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xff80ffff))
++#define SET_RO_PGA_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xffffc000))
++#define SET_RO_RF_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xfff0ffff))
++#define SET_RO_PGAGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xf0ffffff))
++#define SET_RO_RFGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xcfffffff))
++#define SET_RO_PGA_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xffffc000))
++#define SET_RO_RF_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xfff0ffff))
++#define SET_RO_PGAGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xf0ffffff))
++#define SET_RO_RFGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xcfffffff))
++#define SET_RO_PGA_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xffffc000))
++#define SET_RO_RF_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xfff0ffff))
++#define SET_RO_PGAGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xf0ffffff))
++#define SET_RO_RFGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xcfffffff))
++#define SET_RG_TX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffffe0))
++#define SET_RG_TX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffe0ff))
++#define SET_RG_TX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffe0ffff))
++#define SET_RG_TX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xe0ffffff))
++#define SET_RG_TX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffffe0))
++#define SET_RG_TX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffe0ff))
++#define SET_RG_TX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffe0ffff))
++#define SET_RG_TX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xe0ffffff))
++#define SET_RG_TX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffffe))
++#define SET_RG_TX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffffef))
++#define SET_RG_TX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffeff))
++#define SET_RG_TX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffefff))
++#define SET_RG_TX_DES_PWRLVL(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffe0ffff))
++#define SET_RG_TX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xe0ffffff))
++#define SET_RG_RX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffffc0))
++#define SET_RG_RX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffc0ff))
++#define SET_RG_RX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffc0ffff))
++#define SET_RG_RX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xc0ffffff))
++#define SET_RG_RX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffffc0))
++#define SET_RG_RX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffc0ff))
++#define SET_RG_RX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffc0ffff))
++#define SET_RG_RX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xc0ffffff))
++#define SET_RG_RX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffffe))
++#define SET_RG_RX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffffef))
++#define SET_RG_RX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffeff))
++#define SET_RG_RX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffefff))
++#define SET_RG_RX_DES_SNR(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfff0ffff))
++#define SET_RG_RX_DES_RCPI(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xff0fffff))
++#define SET_RG_RX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xc0ffffff))
++#define SET_RO_TX_DES_EXCP_RATE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffffff00))
++#define SET_RO_TX_DES_EXCP_CH_BW_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffff00ff))
++#define SET_RO_TX_DES_EXCP_MODE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xff00ffff))
++#define SET_RG_TX_DES_EXCP_RATE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xf8ffffff))
++#define SET_RG_TX_DES_EXCP_MODE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x8fffffff))
++#define SET_RG_TX_DES_EXCP_CLR(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x7fffffff))
++#define SET_RG_TX_DES_ACK_WIDTH(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffffe))
++#define SET_RG_TX_DES_ACK_PRD(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffff1))
++#define SET_RG_RX_DES_SNR_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xffc0ffff))
++#define SET_RG_RX_DES_RCPI_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xc0ffffff))
++#define SET_RG_TST_TBUS_SEL(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfffffff0))
++#define SET_RG_RSSI_OFFSET(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xff00ffff))
++#define SET_RG_RSSI_INV(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfeffffff))
++#define SET_RG_TST_ADC_ON(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xbfffffff))
++#define SET_RG_TST_EXT_GAIN(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x7fffffff))
++#define SET_RG_DAC_Q_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xfffffc00))
++#define SET_RG_DAC_I_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xffc00fff))
++#define SET_RG_DAC_EN_MAN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xefffffff))
++#define SET_RG_IQC_FFT_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xdfffffff))
++#define SET_RG_DAC_MAN_Q_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xbfffffff))
++#define SET_RG_DAC_MAN_I_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x7fffffff))
++#define SET_RO_MRX_EN_CNT(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0xffff0000))
++#define SET_RG_MRX_EN_CNT_RST_N(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x7fffffff))
++#define SET_RG_PA_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffffff00))
++#define SET_RG_RFTX_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffff00ff))
++#define SET_RG_DAC_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff00ffff))
++#define SET_RG_SW_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ffffff))
++#define SET_RG_PA_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffffff00))
++#define SET_RG_RFTX_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffff00ff))
++#define SET_RG_DAC_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff00ffff))
++#define SET_RG_SW_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ffffff))
++#define SET_RG_ANT_SW_0(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xfffffff8))
++#define SET_RG_ANT_SW_1(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xffffffc7))
++#define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MTX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x7fffffff))
++#define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MTX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x7fffffff))
++#define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MRX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x7fffffff))
++#define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MRX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x7fffffff))
++#define SET_RO_MTX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000))
++#define SET_RO_MTX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff))
++#define SET_RO_MRX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000))
++#define SET_RO_MRX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff))
++#define SET_RG_MODE_REG_IN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffff0000))
++#define SET_RG_PARALLEL_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffefffff))
++#define SET_RG_MBRUN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xfeffffff))
++#define SET_RG_SHIFT_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xefffffff))
++#define SET_RG_MODE_REG_SI_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xdfffffff))
++#define SET_RG_SIMULATION_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xbfffffff))
++#define SET_RG_DBIST_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_28_BIST)) & 0x7fffffff))
++#define SET_RO_MODE_REG_OUT_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xffff0000))
++#define SET_RO_MODE_REG_SO_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xfeffffff))
++#define SET_RO_MONITOR_BUS_16(_VAL_) (REG32(ADR_PHY_READ_REG_07_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_07_BIST)) & 0xfff80000))
++#define SET_RG_MRX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffffff00))
++#define SET_RG_MRX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffff00ff))
++#define SET_RG_MTX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff00ffff))
++#define SET_RG_MTX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ffffff))
++#define SET_RO_MTX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000))
++#define SET_RO_MTX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff))
++#define SET_RO_MRX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000))
++#define SET_RO_MRX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff))
++#define SET_RG_HB_COEF0(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xfffff000))
++#define SET_RG_HB_COEF1(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xf000ffff))
++#define SET_RG_HB_COEF2(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xfffff000))
++#define SET_RG_HB_COEF3(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xf000ffff))
++#define SET_RG_HB_COEF4(_VAL_) (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0xfffff000))
++#define SET_RO_TBUS_O(_VAL_) (REG32(ADR_PHY_READ_TBUS)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_TBUS)) & 0xfff00000))
++#define SET_RG_LPF4_00(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_00)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_00)) & 0xffffe000))
++#define SET_RG_LPF4_01(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_01)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_01)) & 0xffffe000))
++#define SET_RG_LPF4_02(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_02)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_02)) & 0xffffe000))
++#define SET_RG_LPF4_03(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_03)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_03)) & 0xffffe000))
++#define SET_RG_LPF4_04(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_04)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_04)) & 0xffffe000))
++#define SET_RG_LPF4_05(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_05)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_05)) & 0xffffe000))
++#define SET_RG_LPF4_06(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_06)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_06)) & 0xffffe000))
++#define SET_RG_LPF4_07(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_07)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_07)) & 0xffffe000))
++#define SET_RG_LPF4_08(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_08)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_08)) & 0xffffe000))
++#define SET_RG_LPF4_09(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_09)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_09)) & 0xffffe000))
++#define SET_RG_LPF4_10(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_10)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_10)) & 0xffffe000))
++#define SET_RG_LPF4_11(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_11)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_11)) & 0xffffe000))
++#define SET_RG_LPF4_12(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_12)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_12)) & 0xffffe000))
++#define SET_RG_LPF4_13(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_13)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_13)) & 0xffffe000))
++#define SET_RG_LPF4_14(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_14)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_14)) & 0xffffe000))
++#define SET_RG_LPF4_15(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_15)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_15)) & 0xffffe000))
++#define SET_RG_LPF4_16(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_16)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_16)) & 0xffffe000))
++#define SET_RG_LPF4_17(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_17)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_17)) & 0xffffe000))
++#define SET_RG_LPF4_18(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_18)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_18)) & 0xffffe000))
++#define SET_RG_LPF4_19(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_19)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_19)) & 0xffffe000))
++#define SET_RG_LPF4_20(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_20)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_20)) & 0xffffe000))
++#define SET_RG_LPF4_21(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_21)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_21)) & 0xffffe000))
++#define SET_RG_LPF4_22(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_22)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_22)) & 0xffffe000))
++#define SET_RG_LPF4_23(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_23)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_23)) & 0xffffe000))
++#define SET_RG_LPF4_24(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_24)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_24)) & 0xffffe000))
++#define SET_RG_LPF4_25(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_25)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_25)) & 0xffffe000))
++#define SET_RG_LPF4_26(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_26)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_26)) & 0xffffe000))
++#define SET_RG_LPF4_27(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_27)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_27)) & 0xffffe000))
++#define SET_RG_LPF4_28(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_28)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_28)) & 0xffffe000))
++#define SET_RG_LPF4_29(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_29)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_29)) & 0xffffe000))
++#define SET_RG_LPF4_30(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_30)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_30)) & 0xffffe000))
++#define SET_RG_LPF4_31(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_31)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_31)) & 0xffffe000))
++#define SET_RG_LPF4_32(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_32)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_32)) & 0xffffe000))
++#define SET_RG_LPF4_33(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_33)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_33)) & 0xffffe000))
++#define SET_RG_LPF4_34(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_34)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_34)) & 0xffffe000))
++#define SET_RG_LPF4_35(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_35)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_35)) & 0xffffe000))
++#define SET_RG_LPF4_36(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_36)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_36)) & 0xffffe000))
++#define SET_RG_LPF4_37(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_37)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_37)) & 0xffffe000))
++#define SET_RG_LPF4_38(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_38)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_38)) & 0xffffe000))
++#define SET_RG_LPF4_39(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_39)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_39)) & 0xffffe000))
++#define SET_RG_LPF4_40(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_40)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_40)) & 0xffffe000))
++#define SET_RG_BP_SMB(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 13) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffdfff))
++#define SET_RG_EN_SRVC(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 14) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffbfff))
++#define SET_RG_DES_SPD(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 16) | ((REG32(ADR_TX_11B_PLCP)) & 0xfffcffff))
++#define SET_RG_BB_11B_RISE_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_RAMP)) & 0xffffff00))
++#define SET_RG_BB_11B_FALL_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11B_RAMP)) & 0xffff00ff))
++#define SET_RG_WR_TX_EN_CNT_RST_N(_VAL_) (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0xfffffffe))
++#define SET_RO_TX_EN_CNT(_VAL_) (REG32(ADR_TX_11B_EN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT)) & 0xffff0000))
++#define SET_RO_TX_CNT(_VAL_) (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0x00000000))
++#define SET_RG_POS_DES_11B_L_EXT(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xfffffff0))
++#define SET_RG_PRE_DES_11B_DLY(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xffffff0f))
++#define SET_RG_CNT_CCA_LMT(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_0)) & 0xfff0ffff))
++#define SET_RG_BYPASS_DESCRAMBLER(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11B_CCA_0)) & 0xdfffffff))
++#define SET_RG_BYPASS_AGC(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11B_CCA_0)) & 0x7fffffff))
++#define SET_RG_CCA_BIT_CNT_LMT_RX(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CCA_1)) & 0xffffff0f))
++#define SET_RG_CCA_SCALE_BF(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_1)) & 0xff80ffff))
++#define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11B_CCA_1)) & 0xcfffffff))
++#define SET_RG_TR_KI_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffffff8))
++#define SET_RG_TR_KP_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffffff8f))
++#define SET_RG_TR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffff8ff))
++#define SET_RG_TR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffff8fff))
++#define SET_RG_CR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xfff8ffff))
++#define SET_RG_CR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xff8fffff))
++#define SET_RG_CHIP_CNT_SLICER(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffffffe0))
++#define SET_RG_CE_T4_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffff00ff))
++#define SET_RG_CE_T3_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff00ffff))
++#define SET_RG_CE_T2_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ffffff))
++#define SET_RG_CE_MU_T1(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xfffffff8))
++#define SET_RG_CE_DLY_SEL(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xffc0ffff))
++#define SET_RG_CE_MU_T8(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffffff8))
++#define SET_RG_CE_MU_T7(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffffff8f))
++#define SET_RG_CE_MU_T6(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffff8ff))
++#define SET_RG_CE_MU_T5(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffff8fff))
++#define SET_RG_CE_MU_T4(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfff8ffff))
++#define SET_RG_CE_MU_T3(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xff8fffff))
++#define SET_RG_CE_MU_T2(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xf8ffffff))
++#define SET_RG_EQ_MU_FB_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfffffff0))
++#define SET_RG_EQ_MU_FF_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xffffff0f))
++#define SET_RG_EQ_MU_FB_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfff0ffff))
++#define SET_RG_EQ_MU_FF_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xff0fffff))
++#define SET_RG_EQ_MU_FB_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfffffff0))
++#define SET_RG_EQ_MU_FF_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xffffff0f))
++#define SET_RG_EQ_MU_FB_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfff0ffff))
++#define SET_RG_EQ_MU_FF_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xff0fffff))
++#define SET_RG_EQ_KI_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfffff8ff))
++#define SET_RG_EQ_KP_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xffff8fff))
++#define SET_RG_EQ_KI_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfff8ffff))
++#define SET_RG_EQ_KP_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xff8fffff))
++#define SET_RG_TR_LPF_RATE(_VAL_) (REG32(ADR_RX_11B_LPF_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_LPF_RATE)) & 0xffc00000))
++#define SET_RG_CE_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff80))
++#define SET_RG_CE_CH_MAIN_SET(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff7f))
++#define SET_RG_TC_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffff80ff))
++#define SET_RG_CR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xff80ffff))
++#define SET_RG_TR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x80ffffff))
++#define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xfffffffe))
++#define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xf800ffff))
++#define SET_RG_PWRON_DLY_TH_11B(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xffffff00))
++#define SET_RG_SFD_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xff00ffff))
++#define SET_RG_CCA_PWR_TH_RX(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffff8000))
++#define SET_RG_CCA_PWR_CNT_TH(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffe0ffff))
++#define SET_B_FREQ_OS(_VAL_) (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0xfffff800))
++#define SET_B_SNR(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xffffff80))
++#define SET_B_RCPI(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xff80ffff))
++#define SET_CRC_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000))
++#define SET_SFD_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff))
++#define SET_B_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xffff0000))
++#define SET_PACKET_ERR(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xfffeffff))
++#define SET_B_PACKET_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
++#define SET_B_CCA_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
++#define SET_B_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000))
++#define SET_SFD_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff))
++#define SET_SIGNAL_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffffff00))
++#define SET_B_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffff00ff))
++#define SET_CRC_CORRECT(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xfffeffff))
++#define SET_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xfffffff0))
++#define SET_RG_PACKET_STAT_EN_11B(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffefffff))
++#define SET_RG_BIT_REVERSE(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffdfffff))
++#define SET_RX_PHY_11B_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffffffe))
++#define SET_RG_CE_BYPASS_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xffffff0f))
++#define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffff0ff))
++#define SET_RG_BB_11GN_RISE_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffffff00))
++#define SET_RG_BB_11GN_FALL_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffff00ff))
++#define SET_RG_HTCARR52_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP)) & 0xfffffc00))
++#define SET_RG_HTCARR56_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 12) | ((REG32(ADR_TX_11GN_PLCP)) & 0xffc00fff))
++#define SET_RG_PACKET_STAT_EN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 23) | ((REG32(ADR_TX_11GN_PLCP)) & 0xff7fffff))
++#define SET_RG_SMB_DEF(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 24) | ((REG32(ADR_TX_11GN_PLCP)) & 0x80ffffff))
++#define SET_RG_CONTINUOUS_DATA_11GN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 31) | ((REG32(ADR_TX_11GN_PLCP)) & 0x7fffffff))
++#define SET_RO_TX_CNT_R(_VAL_) (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0x00000000))
++#define SET_RO_PACKET_ERR_CNT(_VAL_) (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0xffff0000))
++#define SET_RG_POS_DES_11GN_L_EXT(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xfffffff0))
++#define SET_RG_PRE_DES_11GN_DLY(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xffffff0f))
++#define SET_RG_TR_LPF_KI_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfffffff0))
++#define SET_RG_TR_LPF_KP_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffffff0f))
++#define SET_RG_TR_CNT_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffff00ff))
++#define SET_RG_TR_LPF_KI_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfff0ffff))
++#define SET_RG_TR_LPF_KP_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TR_0)) & 0xff0fffff))
++#define SET_RG_TR_CNT_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_TR_0)) & 0x00ffffff))
++#define SET_RG_TR_LPF_KI_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_1)) & 0xfffffff0))
++#define SET_RG_TR_LPF_KP_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffffff0f))
++#define SET_RG_TR_CNT_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffff00ff))
++#define SET_RG_TR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_2)) & 0xfffffff0))
++#define SET_RG_TR_LPF_KP_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_2)) & 0xffffff0f))
++#define SET_RG_TR_LPF_RATE_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_2)) & 0xc00000ff))
++#define SET_RG_CR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xfffffff8))
++#define SET_RG_SYM_BOUND_CNT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xffff80ff))
++#define SET_RG_XSCOR32_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xff80ffff))
++#define SET_RG_ATCOR64_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_0)) & 0x80ffffff))
++#define SET_RG_ATCOR16_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xffff80ff))
++#define SET_RG_ATCOR16_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xff80ffff))
++#define SET_RG_ATCOR16_RATIO_SB(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_1)) & 0x80ffffff))
++#define SET_RG_XSCOR64_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_2)) & 0xff80ffff))
++#define SET_RG_XSCOR64_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_2)) & 0x80ffffff))
++#define SET_RG_RX_FFT_SCALE(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffffc00))
++#define SET_RG_VITERBI_AB_SWAP(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffeffff))
++#define SET_RG_ATCOR16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xf0ffffff))
++#define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffffff00))
++#define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffff00ff))
++#define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff00ffff))
++#define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_SNR_3(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffffff00))
++#define SET_RG_NORMSQUARE_SNR_2(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffff00ff))
++#define SET_RG_NORMSQUARE_SNR_1(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff00ffff))
++#define SET_RG_NORMSQUARE_SNR_0(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffffff00))
++#define SET_RG_NORMSQUARE_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffff00ff))
++#define SET_RG_NORMSQUARE_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff00ffff))
++#define SET_RG_NORMSQUARE_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0x00ffffff))
++#define SET_RG_SNR_TH_64QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffffff80))
++#define SET_RG_SNR_TH_16QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffff80ff))
++#define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffffff80))
++#define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffff80ff))
++#define SET_RG_SYM_BOUND_METHOD(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xfffcffff))
++#define SET_RG_PWRON_DLY_TH_11GN(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffffff00))
++#define SET_RG_SB_START_CNT(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffff80ff))
++#define SET_RG_POW16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xffffff0f))
++#define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xfffff8ff))
++#define SET_RG_POW16_TH_L(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0x80ffffff))
++#define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfffffff8))
++#define SET_RG_XSCOR16_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xffff80ff))
++#define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfff8ffff))
++#define SET_RG_ATCOR16_RATIO_CCD(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0x80ffffff))
++#define SET_RG_ATCOR64_ACC_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xffffff80))
++#define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xfff8ffff))
++#define SET_RG_VITERBI_TB_BITS(_VAL_) (REG32(ADR_RX_11GN_VTB_TB)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_VTB_TB)) & 0x00ffffff))
++#define SET_RG_CR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xffffff00))
++#define SET_RG_TR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xff00ffff))
++#define SET_RG_BYPASS_CPE_MA(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffffffef))
++#define SET_RG_PILOT_BNDRY_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfffff8ff))
++#define SET_RG_EQ_SHORT_GI_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffff8fff))
++#define SET_RG_FFT_WDW_SHORT_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfff8ffff))
++#define SET_RG_CHSMTH_COEF(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffcffff))
++#define SET_RG_CHSMTH_EN(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 18) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffbffff))
++#define SET_RG_CHEST_DD_FACTOR(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xf8ffffff))
++#define SET_RG_CH_UPDATE(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x7fffffff))
++#define SET_RG_FMT_DET_MM_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffffff00))
++#define SET_RG_FMT_DET_GF_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffff00ff))
++#define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xfdffffff))
++#define SET_RG_FMT_DET_LENGTH_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000))
++#define SET_RG_L_LENGTH_MAX(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff))
++#define SET_RG_TX_TIME_EXT(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xffffff00))
++#define SET_RG_MAC_DES_SPACE(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xff0fffff))
++#define SET_RG_TR_LPF_STBC_GF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffffff0))
++#define SET_RG_TR_LPF_STBC_GF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffffff0f))
++#define SET_RG_TR_LPF_STBC_MF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffff0ff))
++#define SET_RG_TR_LPF_STBC_MF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffff0fff))
++#define SET_RG_MODE_REG_IN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfffe0000))
++#define SET_RG_PARALLEL_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xffefffff))
++#define SET_RG_MBRUN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfeffffff))
++#define SET_RG_SHIFT_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xefffffff))
++#define SET_RG_MODE_REG_SI_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xdfffffff))
++#define SET_RG_SIMULATION_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xbfffffff))
++#define SET_RG_DBIST_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_0)) & 0x7fffffff))
++#define SET_RG_MODE_REG_IN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffff0000))
++#define SET_RG_PARALLEL_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffefffff))
++#define SET_RG_MBRUN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xfeffffff))
++#define SET_RG_SHIFT_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xefffffff))
++#define SET_RG_MODE_REG_SI_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xdfffffff))
++#define SET_RG_SIMULATION_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xbfffffff))
++#define SET_RG_DBIST_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_1)) & 0x7fffffff))
++#define SET_RO_MODE_REG_OUT_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfffe0000))
++#define SET_RO_MODE_REG_SO_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfeffffff))
++#define SET_RO_MONITOR_BUS_80(_VAL_) (REG32(ADR_RX_11GN_BIST_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_3)) & 0xffc00000))
++#define SET_RO_MODE_REG_OUT_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xffff0000))
++#define SET_RO_MODE_REG_SO_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xfeffffff))
++#define SET_RO_MONITOR_BUS_64(_VAL_) (REG32(ADR_RX_11GN_BIST_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_5)) & 0xfff80000))
++#define SET_RO_SPECTRUM_DATA(_VAL_) (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0x00000000))
++#define SET_GN_SNR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffffff80))
++#define SET_GN_NOISE_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffff80ff))
++#define SET_GN_RCPI(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_READ_0)) & 0xff80ffff))
++#define SET_GN_SIGNAL_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_READ_0)) & 0x80ffffff))
++#define SET_RO_FREQ_OS_LTS(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xffff8000))
++#define SET_CSTATE(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xfff0ffff))
++#define SET_SIGNAL_FIELD0(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0xff000000))
++#define SET_SIGNAL_FIELD1(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0xff000000))
++#define SET_GN_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0xffff0000))
++#define SET_GN_PACKET_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
++#define SET_GN_CCA_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
++#define SET_GN_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000))
++#define SET_GN_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff))
++#define SET_RO_HT_MCS_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffff80))
++#define SET_RO_L_RATE_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffc0ff))
++#define SET_RG_DAGC_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xfffffffc))
++#define SET_RG_PACKET_STAT_EN_11GN(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xffefffff))
++#define SET_RX_PHY_11GN_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffe))
++#define SET_RG_RIFS_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 1) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffd))
++#define SET_RG_STBC_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 2) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffb))
++#define SET_RG_COR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 3) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffff7))
++#define SET_RG_INI_PHASE(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffcf))
++#define SET_RG_HT_LTF_SEL_EQ(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 6) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffbf))
++#define SET_RG_HT_LTF_SEL_PILOT(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffff7f))
++#define SET_RG_CCA_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 9) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffdff))
++#define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 10) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffbff))
++#define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 11) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffff7ff))
++#define SET_RG_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffff0fff))
++#define SET_RG_POST_CLK_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffeffff))
++#define SET_IQCAL_RF_TX_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffe))
++#define SET_IQCAL_RF_TX_PA_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 1) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffd))
++#define SET_IQCAL_RF_TX_DAC_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 2) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffb))
++#define SET_IQCAL_RF_RX_AGC(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 3) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffff7))
++#define SET_IQCAL_RF_PGAG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffff0ff))
++#define SET_IQCAL_RF_RFG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 12) | ((REG32(ADR_RF_CONTROL_0)) & 0xffffcfff))
++#define SET_RG_TONEGEN_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_CONTROL_0)) & 0xff80ffff))
++#define SET_RG_TONEGEN_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 23) | ((REG32(ADR_RF_CONTROL_0)) & 0xff7fffff))
++#define SET_RG_TONEGEN_INIT_PH(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_CONTROL_0)) & 0x80ffffff))
++#define SET_RG_TONEGEN2_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff80))
++#define SET_RG_TONEGEN2_EN(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 7) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff7f))
++#define SET_RG_TONEGEN2_SCALE(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_1)) & 0xffff00ff))
++#define SET_RG_TXIQ_CLP_THD_I(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfffffc00))
++#define SET_RG_TXIQ_CLP_THD_Q(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfc00ffff))
++#define SET_RG_TX_I_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffffff00))
++#define SET_RG_TX_Q_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffff00ff))
++#define SET_RG_TX_IQ_SWP(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffeffff))
++#define SET_RG_TX_SGN_OUT(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 17) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffdffff))
++#define SET_RG_TXIQ_EMU_IDX(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 18) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffc3ffff))
++#define SET_RG_TX_IQ_SRC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfcffffff))
++#define SET_RG_TX_I_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfffffc00))
++#define SET_RG_TX_Q_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfc00ffff))
++#define SET_RG_TX_IQ_THETA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffffe0))
++#define SET_RG_TX_IQ_ALPHA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffe0ff))
++#define SET_RG_TXIQ_NOSHRINK(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffdfff))
++#define SET_RG_TX_I_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff00ffff))
++#define SET_RG_TX_Q_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 24) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ffffff))
++#define SET_RG_RX_IQ_THETA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffffe0))
++#define SET_RG_RX_IQ_ALPHA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffe0ff))
++#define SET_RG_RXIQ_NOSHRINK(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffdfff))
++#define SET_RG_MA_DPTH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffff0))
++#define SET_RG_INTG_PH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffc0f))
++#define SET_RG_INTG_PRD(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 10) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffffe3ff))
++#define SET_RG_INTG_MU(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 13) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffff9fff))
++#define SET_RG_IQCAL_SPRM_SELQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffeffff))
++#define SET_RG_IQCAL_SPRM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 17) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffdffff))
++#define SET_RG_IQCAL_SPRM_FREQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 18) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xff03ffff))
++#define SET_RG_IQCAL_IQCOL_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfeffffff))
++#define SET_RG_IQCAL_ALPHA_ESTM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfdffffff))
++#define SET_RG_IQCAL_DC_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfbffffff))
++#define SET_RG_PHEST_STBY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xf7ffffff))
++#define SET_RG_PHEST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xefffffff))
++#define SET_RG_GP_DIV_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xdfffffff))
++#define SET_RG_DPD_GAIN_EST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xbfffffff))
++#define SET_RG_IQCAL_MULT_OP0(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfffffc00))
++#define SET_RG_IQCAL_MULT_OP1(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfc00ffff))
++#define SET_RO_IQCAL_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfff00000))
++#define SET_RO_IQCAL_SPRM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 20) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffefffff))
++#define SET_RO_IQCAL_IQCOL_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 21) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffdfffff))
++#define SET_RO_IQCAL_ALPHA_ESTM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 22) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffbfffff))
++#define SET_RO_IQCAL_DC_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 23) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xff7fffff))
++#define SET_RO_IQCAL_MULT_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfeffffff))
++#define SET_RO_FFT_ENRG_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfdffffff))
++#define SET_RO_PHEST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfbffffff))
++#define SET_RO_GP_DIV_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xf7ffffff))
++#define SET_RO_GAIN_EST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xefffffff))
++#define SET_RO_AMP_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0xfffffe00))
++#define SET_RG_RX_I_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffffff00))
++#define SET_RG_RX_Q_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffff00ff))
++#define SET_RG_RX_I_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff00ffff))
++#define SET_RG_RX_Q_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ffffff))
++#define SET_RG_RX_IQ_SWP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffe))
++#define SET_RG_RX_SGN_IN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffd))
++#define SET_RG_RX_IQ_SRC(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 2) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffff3))
++#define SET_RG_ACI_GAIN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffff00f))
++#define SET_RG_FFT_EN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 12) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffefff))
++#define SET_RG_FFT_MOD(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 13) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffdfff))
++#define SET_RG_FFT_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 14) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xff003fff))
++#define SET_RG_FFT_ENRG_FREQ(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xc0ffffff))
++#define SET_RG_FPGA_80M_PH_UP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 30) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xbfffffff))
++#define SET_RG_FPGA_80M_PH_STP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 31) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0x7fffffff))
++#define SET_RG_ADC2LA_SEL(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffe))
++#define SET_RG_ADC2LA_CLKPH(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffd))
++#define SET_RG_RXIQ_EMU_IDX(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xfffffff0))
++#define SET_RG_IQCAL_BP_ACI(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xffffffef))
++#define SET_RG_DPD_AM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffe))
++#define SET_RG_DPD_PM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffd))
++#define SET_RG_DPD_PM_AMSEL(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffb))
++#define SET_RG_DPD_020_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfffffc00))
++#define SET_RG_DPD_040_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfc00ffff))
++#define SET_RG_DPD_060_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfffffc00))
++#define SET_RG_DPD_080_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfc00ffff))
++#define SET_RG_DPD_0A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfffffc00))
++#define SET_RG_DPD_0C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfc00ffff))
++#define SET_RG_DPD_0D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfffffc00))
++#define SET_RG_DPD_0E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfc00ffff))
++#define SET_RG_DPD_0F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfffffc00))
++#define SET_RG_DPD_100_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfc00ffff))
++#define SET_RG_DPD_110_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfffffc00))
++#define SET_RG_DPD_120_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfc00ffff))
++#define SET_RG_DPD_130_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfffffc00))
++#define SET_RG_DPD_140_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfc00ffff))
++#define SET_RG_DPD_150_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfffffc00))
++#define SET_RG_DPD_160_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfc00ffff))
++#define SET_RG_DPD_170_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfffffc00))
++#define SET_RG_DPD_180_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfc00ffff))
++#define SET_RG_DPD_190_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfffffc00))
++#define SET_RG_DPD_1A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfc00ffff))
++#define SET_RG_DPD_1B0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfffffc00))
++#define SET_RG_DPD_1C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfc00ffff))
++#define SET_RG_DPD_1D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfffffc00))
++#define SET_RG_DPD_1E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfc00ffff))
++#define SET_RG_DPD_1F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfffffc00))
++#define SET_RG_DPD_200_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfc00ffff))
++#define SET_RG_DPD_020_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xffffe000))
++#define SET_RG_DPD_040_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xe000ffff))
++#define SET_RG_DPD_060_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xffffe000))
++#define SET_RG_DPD_080_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xe000ffff))
++#define SET_RG_DPD_0A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xffffe000))
++#define SET_RG_DPD_0C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xe000ffff))
++#define SET_RG_DPD_0D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xffffe000))
++#define SET_RG_DPD_0E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xe000ffff))
++#define SET_RG_DPD_0F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xffffe000))
++#define SET_RG_DPD_100_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xe000ffff))
++#define SET_RG_DPD_110_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xffffe000))
++#define SET_RG_DPD_120_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xe000ffff))
++#define SET_RG_DPD_130_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xffffe000))
++#define SET_RG_DPD_140_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xe000ffff))
++#define SET_RG_DPD_150_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xffffe000))
++#define SET_RG_DPD_160_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xe000ffff))
++#define SET_RG_DPD_170_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xffffe000))
++#define SET_RG_DPD_180_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xe000ffff))
++#define SET_RG_DPD_190_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xffffe000))
++#define SET_RG_DPD_1A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xe000ffff))
++#define SET_RG_DPD_1B0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xffffe000))
++#define SET_RG_DPD_1C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xe000ffff))
++#define SET_RG_DPD_1D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xffffe000))
++#define SET_RG_DPD_1E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xe000ffff))
++#define SET_RG_DPD_1F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xffffe000))
++#define SET_RG_DPD_200_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xe000ffff))
++#define SET_RG_DPD_GAIN_EST_Y0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfffffe00))
++#define SET_RG_DPD_GAIN_EST_Y1(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfe00ffff))
++#define SET_RG_DPD_LOOP_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0xfffffc00))
++#define SET_RG_DPD_GAIN_EST_X0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfffffe00))
++#define SET_RO_DPD_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfc00ffff))
++#define SET_TX_SCALE_11B(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffffff00))
++#define SET_TX_SCALE_11B_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 8) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffff00ff))
++#define SET_TX_SCALE_11G(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xff00ffff))
++#define SET_TX_SCALE_11G_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 24) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ffffff))
++#define SET_RG_EN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
++#define SET_RG_TX_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
++#define SET_RG_TX_PA_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
++#define SET_RG_TX_DAC_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
++#define SET_RG_RX_AGC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
++#define SET_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
++#define SET_RG_RFG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
++#define SET_RG_PGAG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
++#define SET_RG_MODE(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
++#define SET_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
++#define SET_RG_EN_SX(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
++#define SET_RG_EN_RX_LNA(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
++#define SET_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
++#define SET_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
++#define SET_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
++#define SET_RG_EN_RX_TZ(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
++#define SET_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
++#define SET_RG_EN_RX_HPF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
++#define SET_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
++#define SET_RG_EN_ADC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
++#define SET_RG_EN_TX_MOD(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
++#define SET_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
++#define SET_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
++#define SET_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
++#define SET_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
++#define SET_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
++#define SET_RG_EN_CLK_960MBY13_UART(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x7fffffff))
++#define SET_RG_EN_TX_DPD(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
++#define SET_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
++#define SET_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
++#define SET_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
++#define SET_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
++#define SET_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
++#define SET_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
++#define SET_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
++#define SET_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
++#define SET_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
++#define SET_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
++#define SET_RG_EN_IREF_RX(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
++#define SET_RG_EN_TX_DAC_VOUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffdfff))
++#define SET_RG_EN_SX_LCK_BIN(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffbfff))
++#define SET_RG_RTC_CAL_MODE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffeffff))
++#define SET_RG_EN_IQPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffdffff))
++#define SET_RG_EN_TESTPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffbffff))
++#define SET_RG_EN_TRXBF_BYPASS(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfff7ffff))
++#define SET_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffff8))
++#define SET_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_LDO_REGISTER)) & 0xffffffc7))
++#define SET_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffe3f))
++#define SET_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_LDO_REGISTER)) & 0xfffff1ff))
++#define SET_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_LDO_REGISTER)) & 0xffff8fff))
++#define SET_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_LDO_REGISTER)) & 0xfffc7fff))
++#define SET_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_LDO_REGISTER)) & 0xffe3ffff))
++#define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_LDO_REGISTER)) & 0xff1fffff))
++#define SET_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_LDO_REGISTER)) & 0xf8ffffff))
++#define SET_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffe))
++#define SET_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffd))
++#define SET_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffb))
++#define SET_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffe07))
++#define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffdff))
++#define SET_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffbff))
++#define SET_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffff7ff))
++#define SET_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffffcfff))
++#define SET_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffff3fff))
++#define SET_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffcffff))
++#define SET_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfff3ffff))
++#define SET_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffcfffff))
++#define SET_RG_RX_HPF3M(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffbfffff))
++#define SET_RG_RX_HPF300K(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_1)) & 0xff7fffff))
++#define SET_RG_RX_HPFI(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfcffffff))
++#define SET_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_ABB_REGISTER_1)) & 0xf3ffffff))
++#define SET_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_ABB_REGISTER_1)) & 0xcfffffff))
++#define SET_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffffc))
++#define SET_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffff3))
++#define SET_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffffcf))
++#define SET_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffff3f))
++#define SET_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffcff))
++#define SET_RG_RX_OUTVCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffff3ff))
++#define SET_RG_RX_TZI(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffcfff))
++#define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffbfff))
++#define SET_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffe7fff))
++#define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfff1ffff))
++#define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffefffff))
++#define SET_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_ABB_REGISTER_2)) & 0xff9fffff))
++#define SET_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfe7fffff))
++#define SET_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfdffffff))
++#define SET_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffffffc))
++#define SET_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffff03))
++#define SET_RG_TXPGA_STEER(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffc0ff))
++#define SET_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffff3fff))
++#define SET_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffcffff))
++#define SET_RG_PACELL_EN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffe3ffff))
++#define SET_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfe1fffff))
++#define SET_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_TX_FE_REGISTER)) & 0xf3ffffff))
++#define SET_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_TX_FE_REGISTER)) & 0xcfffffff))
++#define SET_RG_RX_SQDC(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffffff8))
++#define SET_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffffe7))
++#define SET_RG_RX_LOBUF(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffff9f))
++#define SET_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffff87f))
++#define SET_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffff87ff))
++#define SET_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffc7fff))
++#define SET_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffe3ffff))
++#define SET_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffdfffff))
++#define SET_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xff3fffff))
++#define SET_RG_PACASCODE_CTRL(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xf8ffffff))
++#define SET_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
++#define SET_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
++#define SET_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
++#define SET_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
++#define SET_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
++#define SET_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
++#define SET_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
++#define SET_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
++#define SET_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
++#define SET_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
++#define SET_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
++#define SET_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
++#define SET_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
++#define SET_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
++#define SET_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
++#define SET_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
++#define SET_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
++#define SET_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
++#define SET_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
++#define SET_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
++#define SET_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
++#define SET_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
++#define SET_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
++#define SET_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
++#define SET_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffe))
++#define SET_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffd))
++#define SET_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffb))
++#define SET_RG_HPF_T1A(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffffe7))
++#define SET_RG_HPF_T1B(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffff9f))
++#define SET_RG_HPF_T1C(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffe7f))
++#define SET_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffff9ff))
++#define SET_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffe7ff))
++#define SET_RG_TXGAIN_PHYCTRL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffdfff))
++#define SET_RG_TX_GAIN(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffc03fff))
++#define SET_RG_TXGAIN_MANUAL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffbfffff))
++#define SET_RG_TX_GAIN_OFFSET(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xf87fffff))
++#define SET_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffffe))
++#define SET_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff9))
++#define SET_RG_ADC_DIVR(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff7))
++#define SET_RG_ADC_DVCMI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffffffcf))
++#define SET_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffc3f))
++#define SET_RG_ADC_STNBY(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffbff))
++#define SET_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffff7ff))
++#define SET_RG_ADC_TSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffff0fff))
++#define SET_RG_ADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffcffff))
++#define SET_RG_DICMP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfff3ffff))
++#define SET_RG_DIOP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffcfffff))
++#define SET_RG_SARADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xff3fffff))
++#define SET_RG_EN_SAR_TEST(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfcffffff))
++#define SET_RG_SARADC_THERMAL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfbffffff))
++#define SET_RG_SARADC_TSSI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xf7ffffff))
++#define SET_RG_CLK_SAR_SEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xcfffffff))
++#define SET_RG_EN_SARADC(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xbfffffff))
++#define SET_RG_DACI1ST(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffffc))
++#define SET_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffff3))
++#define SET_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffffcf))
++#define SET_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffff3f))
++#define SET_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffeff))
++#define SET_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffff9ff))
++#define SET_RG_TX_DAC_OS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffc7ff))
++#define SET_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffff3fff))
++#define SET_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfff0ffff))
++#define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffefffff))
++#define SET_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffdfffff))
++#define SET_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffbfffff))
++#define SET_RG_TX_DAC_IOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xf87fffff))
++#define SET_RG_TX_DAC_QOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_TX_DAC_REGISTER)) & 0x87ffffff))
++#define SET_RG_EN_SX_R3(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffe))
++#define SET_RG_EN_SX_CH(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffd))
++#define SET_RG_EN_SX_CHP(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffb))
++#define SET_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffff7))
++#define SET_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffef))
++#define SET_RG_EN_SX_VCO(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffdf))
++#define SET_RG_EN_SX_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffbf))
++#define SET_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffeff))
++#define SET_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffff7ff))
++#define SET_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffefff))
++#define SET_RG_EN_SX_DIV(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffdfff))
++#define SET_RG_EN_SX_LPF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffbfff))
++#define SET_RG_EN_DPL_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffff7fff))
++#define SET_RG_DPL_MOD_ORDER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffcffff))
++#define SET_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_1)) & 0xff000000))
++#define SET_RG_SX_SEL_CP(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_REGISTER_1)) & 0xf0ffffff))
++#define SET_RG_SX_SEL_CS(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_REGISTER_1)) & 0x0fffffff))
++#define SET_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfffff800))
++#define SET_RG_SX_SEL_C3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_REGISTER_2)) & 0xffff87ff))
++#define SET_RG_SX_SEL_RS(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfff07fff))
++#define SET_RG_SX_SEL_R3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfe0fffff))
++#define SET_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffffe0))
++#define SET_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffffc1f))
++#define SET_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffc3ff))
++#define SET_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffc3fff))
++#define SET_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffbffff))
++#define SET_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffc7ffff))
++#define SET_RG_SX_PFDSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffbfffff))
++#define SET_RG_SX_PFD_SET(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_SYN_PFD_CHP)) & 0xff7fffff))
++#define SET_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfeffffff))
++#define SET_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfdffffff))
++#define SET_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfbffffff))
++#define SET_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_SYN_PFD_CHP)) & 0xf7ffffff))
++#define SET_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_PFD_CHP)) & 0xefffffff))
++#define SET_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_SYN_PFD_CHP)) & 0xdfffffff))
++#define SET_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_SYN_PFD_CHP)) & 0xbfffffff))
++#define SET_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffffff8))
++#define SET_RG_SX_VCORSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffffff07))
++#define SET_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffff0ff))
++#define SET_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffff0fff))
++#define SET_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfff0ffff))
++#define SET_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xff0fffff))
++#define SET_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xf0ffffff))
++#define SET_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_VCO_LOBF)) & 0x0fffffff))
++#define SET_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
++#define SET_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
++#define SET_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
++#define SET_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
++#define SET_RG_SX_XO_GM(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
++#define SET_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
++#define SET_RG_SX_LCKEN(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
++#define SET_RG_SX_PREVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
++#define SET_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
++#define SET_RG_SX_PH(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffdfff))
++#define SET_RG_SX_PL(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffbfff))
++#define SET_RG_XOSC_CBANK_XO(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xfff87fff))
++#define SET_RG_XOSC_CBANK_XI(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xff87ffff))
++#define SET_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffffe))
++#define SET_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 1) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffff9))
++#define SET_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffe7))
++#define SET_RG_SX_VT_SET(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffdf))
++#define SET_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 6) | ((REG32(ADR_SYN_LCK_VT)) & 0xffff803f))
++#define SET_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffffe))
++#define SET_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffff9))
++#define SET_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffffe7))
++#define SET_RG_DP_CK320BY2(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffbfff))
++#define SET_RG_DP_OD_TEST(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffdfffff))
++#define SET_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
++#define SET_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
++#define SET_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
++#define SET_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
++#define SET_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
++#define SET_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
++#define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
++#define SET_RG_DP_RP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
++#define SET_RG_DP_RHP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
++#define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x7fffffff))
++#define SET_RG_DP_FODIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xfff80fff))
++#define SET_RG_DP_REFDIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xe03fffff))
++#define SET_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
++#define SET_RG_DP_BBPLL_BS(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 24) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xc0ffffff))
++#define SET_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
++#define SET_RG_EN_RCAL(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffe))
++#define SET_RG_RCAL_SPD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffd))
++#define SET_RG_RCAL_TMR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffe03))
++#define SET_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffdff))
++#define SET_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RCAL_REGISTER)) & 0xffff83ff))
++#define SET_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfffffffe))
++#define SET_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 1) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffffff01))
++#define SET_RG_SX_LCK_BIN_OFFSET(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff87fff))
++#define SET_RG_SX_LCK_BIN_PRECISION(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 19) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff7ffff))
++#define SET_RG_SX_LOCK_EN_N(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 20) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffefffff))
++#define SET_RG_SX_LOCK_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 21) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffdfffff))
++#define SET_RG_SX_SUB_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 22) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffbfffff))
++#define SET_RG_SX_SUB_SEL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xc07fffff))
++#define SET_RG_SX_MUX_SEL_VTH_BINL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 30) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xbfffffff))
++#define SET_RG_TRX_DUMMMY(_VAL_) (REG32(ADR_TRX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_DUMMY_REGISTER)) & 0x00000000))
++#define SET_RG_SX_DUMMMY(_VAL_) (REG32(ADR_SX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_DUMMY_REGISTER)) & 0x00000000))
++#define SET_RCAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
++#define SET_LCK_BIN_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
++#define SET_VT_MON_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
++#define SET_DA_R_CODE_LUT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
++#define SET_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
++#define SET_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
++#define SET_RTC_CAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 15) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff7fff))
++#define SET_RG_SARADC_BIT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 16) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffc0ffff))
++#define SET_SAR_ADC_FSM_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 22) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffbfffff))
++#define SET_AD_CIRCUIT_VERSION(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 23) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xf87fffff))
++#define SET_DA_R_CAL_CODE(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
++#define SET_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
++#define SET_RG_DPL_RFCTRL_CH(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xfffff800))
++#define SET_RG_RSSIADC_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 11) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xffff87ff))
++#define SET_RG_RX_ADC_I_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xff807fff))
++#define SET_RG_RX_ADC_Q_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x807fffff))
++#define SET_RG_DPL_RFCTRL_F(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0xff000000))
++#define SET_RG_SX_TARGET_CNT(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0xffffe000))
++#define SET_RG_RTC_OFFSET(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 0) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xffffff00))
++#define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 8) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xfff000ff))
++#define SET_RG_RF_D_REG(_VAL_) (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0xffff0000))
++#define SET_DIRECT_MODE(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffe))
++#define SET_TAG_INTERLEAVE_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffd))
++#define SET_DIS_DEMAND(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffb))
++#define SET_SAME_ID_ALLOC_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_MMU_CTRL)) & 0xfffffff7))
++#define SET_HS_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_MMU_CTRL)) & 0xffffffef))
++#define SET_SRAM_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 5) | ((REG32(ADR_MMU_CTRL)) & 0xffffffdf))
++#define SET_NOHIT_RPASS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 6) | ((REG32(ADR_MMU_CTRL)) & 0xffffffbf))
++#define SET_DMN_FLAG_CLR(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_MMU_CTRL)) & 0xffffff7f))
++#define SET_ERR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_CTRL)) & 0xfffffeff))
++#define SET_ALR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_MMU_CTRL)) & 0xfffffdff))
++#define SET_MCH_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_MMU_CTRL)) & 0xfffffbff))
++#define SET_TAG_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_MMU_CTRL)) & 0xfffff7ff))
++#define SET_ABT_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_CTRL)) & 0xffffefff))
++#define SET_MMU_VER(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_MMU_CTRL)) & 0xffff1fff))
++#define SET_MMU_SHARE_MCU(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_CTRL)) & 0xff00ffff))
++#define SET_HS_WR(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_HS_CTRL)) & 0xfffffffe))
++#define SET_HS_FLAG(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_HS_CTRL)) & 0xffffffef))
++#define SET_HS_ID(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_HS_CTRL)) & 0xffff80ff))
++#define SET_HS_CHANNEL(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_HS_CTRL)) & 0xfff0ffff))
++#define SET_HS_PAGE(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 20) | ((REG32(ADR_HS_CTRL)) & 0xff0fffff))
++#define SET_HS_DATA(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 24) | ((REG32(ADR_HS_CTRL)) & 0x00ffffff))
++#define SET_CPU_POR0(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR0_7)) & 0xfffffff0))
++#define SET_CPU_POR1(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR0_7)) & 0xffffff0f))
++#define SET_CPU_POR2(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR0_7)) & 0xfffff0ff))
++#define SET_CPU_POR3(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR0_7)) & 0xffff0fff))
++#define SET_CPU_POR4(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR0_7)) & 0xfff0ffff))
++#define SET_CPU_POR5(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR0_7)) & 0xff0fffff))
++#define SET_CPU_POR6(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR0_7)) & 0xf0ffffff))
++#define SET_CPU_POR7(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR0_7)) & 0x0fffffff))
++#define SET_CPU_POR8(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR8_F)) & 0xfffffff0))
++#define SET_CPU_POR9(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR8_F)) & 0xffffff0f))
++#define SET_CPU_PORA(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR8_F)) & 0xfffff0ff))
++#define SET_CPU_PORB(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR8_F)) & 0xffff0fff))
++#define SET_CPU_PORC(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR8_F)) & 0xfff0ffff))
++#define SET_CPU_PORD(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR8_F)) & 0xff0fffff))
++#define SET_CPU_PORE(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR8_F)) & 0xf0ffffff))
++#define SET_CPU_PORF(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR8_F)) & 0x0fffffff))
++#define SET_ACC_WR_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffffc0))
++#define SET_ACC_RD_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffc0ff))
++#define SET_REQ_NACK_CLR(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 15) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffff7fff))
++#define SET_NACK_FLAG_BUS(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_REG_LEN_CTRL)) & 0x0000ffff))
++#define SET_DMN_R_PASS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xffff0000))
++#define SET_PARA_ALC_RLS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfffeffff))
++#define SET_REQ_PORNS_CHGEN(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 24) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfeffffff))
++#define SET_ALC_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffffff80))
++#define SET_ALC_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffff7fff))
++#define SET_RLS_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xff80ffff))
++#define SET_RLS_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_RLS_ABORT)) & 0x7fffffff))
++#define SET_DEBUG_CTL(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_CTL)) & 0xffffff00))
++#define SET_DEBUG_H16(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_DEBUG_CTL)) & 0xfffffeff))
++#define SET_DEBUG_OUT(_VAL_) (REG32(ADR_DEBUG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_OUT)) & 0x00000000))
++#define SET_ALC_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffe))
++#define SET_RLS_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffd))
++#define SET_AL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_STATUS)) & 0xfffff8ff))
++#define SET_RL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_STATUS)) & 0xffff8fff))
++#define SET_ALC_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_STATUS)) & 0xff80ffff))
++#define SET_RLS_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MMU_STATUS)) & 0x80ffffff))
++#define SET_DMN_NOHIT_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffe))
++#define SET_DMN_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffd))
++#define SET_DMN_WR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_STATUS)) & 0xfffffff7))
++#define SET_DMN_PORT(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_STATUS)) & 0xffffff0f))
++#define SET_DMN_NHIT_ID(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_STATUS)) & 0xffff80ff))
++#define SET_DMN_NHIT_ADDR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_STATUS)) & 0x0000ffff))
++#define SET_TX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_STATUS)) & 0xffffff00))
++#define SET_RX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TAG_STATUS)) & 0xffff00ff))
++#define SET_AVA_TAG(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_STATUS)) & 0xfe00ffff))
++#define SET_PKTBUF_FULL(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 31) | ((REG32(ADR_TAG_STATUS)) & 0x7fffffff))
++#define SET_DMN_NOHIT_MCU(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffe))
++#define SET_DMN_MCU_FLAG(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffd))
++#define SET_DMN_MCU_WR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffff7))
++#define SET_DMN_MCU_PORT(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffffff0f))
++#define SET_DMN_MCU_ID(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffff80ff))
++#define SET_DMN_MCU_ADDR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_MCU_STATUS)) & 0x0000ffff))
++#define SET_MB_IDTBL_31_0(_VAL_) (REG32(ADR_MB_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_0_STATUS)) & 0x00000000))
++#define SET_MB_IDTBL_63_32(_VAL_) (REG32(ADR_MB_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_1_STATUS)) & 0x00000000))
++#define SET_MB_IDTBL_95_64(_VAL_) (REG32(ADR_MB_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_2_STATUS)) & 0x00000000))
++#define SET_MB_IDTBL_127_96(_VAL_) (REG32(ADR_MB_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_3_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_31_0(_VAL_) (REG32(ADR_PKT_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_63_32(_VAL_) (REG32(ADR_PKT_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_95_64(_VAL_) (REG32(ADR_PKT_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_127_96(_VAL_) (REG32(ADR_PKT_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_31_0(_VAL_) (REG32(ADR_DMN_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_63_32(_VAL_) (REG32(ADR_DMN_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_95_64(_VAL_) (REG32(ADR_DMN_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_127_96(_VAL_) (REG32(ADR_DMN_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_31_0(_VAL_) (REG32(ADR_MB_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_0_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_63_32(_VAL_) (REG32(ADR_MB_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_1_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_95_64(_VAL_) (REG32(ADR_MB_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_2_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_127_96(_VAL_) (REG32(ADR_MB_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_3_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_31_0(_VAL_) (REG32(ADR_PKT_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_0_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_63_32(_VAL_) (REG32(ADR_PKT_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_1_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_95_64(_VAL_) (REG32(ADR_PKT_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_2_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_127_96(_VAL_) (REG32(ADR_PKT_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_3_STATUS)) & 0x00000000))
++#define SET_ALC_NOCHG_ID(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffffff80))
++#define SET_ALC_NOCHG_INT(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffff7fff))
++#define SET_NEQ_PKT_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfffeffff))
++#define SET_NEQ_MB_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfeffffff))
++#define SET_SRAM_TAG_0(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000))
++#define SET_SRAM_TAG_1(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff))
++#define SET_SRAM_TAG_2(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000))
++#define SET_SRAM_TAG_3(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff))
++#define SET_SRAM_TAG_4(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000))
++#define SET_SRAM_TAG_5(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff))
++#define SET_SRAM_TAG_6(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000))
++#define SET_SRAM_TAG_7(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff))
++#define SET_SRAM_TAG_8(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000))
++#define SET_SRAM_TAG_9(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff))
++#define SET_SRAM_TAG_10(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000))
++#define SET_SRAM_TAG_11(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff))
++#define SET_SRAM_TAG_12(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000))
++#define SET_SRAM_TAG_13(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff))
++#define SET_SRAM_TAG_14(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000))
++#define SET_SRAM_TAG_15(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff))
++#define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000)
++#define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000)
++#define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x31333131)
++#define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x322d3230)
++#define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x32303041)
++#define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636)
++#define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000000)
++#define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x008fffff)
++#define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000400)
++#define DEF_MCU_DBG_SEL() (REG32(ADR_MCU_DBG_SEL)) = (0x00000000)
++#define DEF_MCU_DBG_DATA() (REG32(ADR_MCU_DBG_DATA)) = (0x00000000)
++#define DEF_AHB_BRG_STATUS() (REG32(ADR_AHB_BRG_STATUS)) = (0x00000000)
++#define DEF_BIST_BIST_CTRL() (REG32(ADR_BIST_BIST_CTRL)) = (0x00000000)
++#define DEF_BIST_MODE_REG_IN() (REG32(ADR_BIST_MODE_REG_IN)) = (0x001ffe3e)
++#define DEF_BIST_MODE_REG_OUT() (REG32(ADR_BIST_MODE_REG_OUT)) = (0x00000000)
++#define DEF_BIST_MONITOR_BUS_LSB() (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (0x00000000)
++#define DEF_BIST_MONITOR_BUS_MSB() (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (0x00000000)
++#define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000)
++#define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000)
++#define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000)
++#define DEF_AHB_ILL_ADDR() (REG32(ADR_AHB_ILL_ADDR)) = (0x00000000)
++#define DEF_AHB_FEN_ADDR() (REG32(ADR_AHB_FEN_ADDR)) = (0x00000000)
++#define DEF_AHB_ILLFEN_STATUS() (REG32(ADR_AHB_ILLFEN_STATUS)) = (0x00000000)
++#define DEF_PWM_A() (REG32(ADR_PWM_A)) = (0x400a1010)
++#define DEF_PWM_B() (REG32(ADR_PWM_B)) = (0x400a1010)
++#define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd)
++#define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000)
++#define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028)
++#define DEF_BIST_MODE_REG_IN_MMU() (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (0x0000fe3e)
++#define DEF_BIST_MODE_REG_OUT_MMU() (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (0x00000000)
++#define DEF_BIST_MONITOR_BUS_MMU() (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (0x00000000)
++#define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000)
++#define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000)
++#define DEF_SD_INIT_CFG() (REG32(ADR_SD_INIT_CFG)) = (0x00000000)
++#define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000)
++#define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU0_DUMMY_BIT_0() (REG32(ADR_TU0_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU0_DUMMY_BIT_1() (REG32(ADR_TU0_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU1_DUMMY_BIT_0() (REG32(ADR_TU1_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU1_DUMMY_BIT_1() (REG32(ADR_TU1_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU2_DUMMY_BIT_0() (REG32(ADR_TU2_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU2_DUMMY_BIT_1() (REG32(ADR_TU2_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU3_DUMMY_BIT_0() (REG32(ADR_TU3_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU3_DUMMY_BIT_1() (REG32(ADR_TU3_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM0_MILISECOND_TIMER() (REG32(ADR_TM0_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM0_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM0_DUMMY_BIT_0() (REG32(ADR_TM0_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM0_DUMMY_BIT_1() (REG32(ADR_TM0_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM1_MILISECOND_TIMER() (REG32(ADR_TM1_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM1_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM1_DUMMY_BIT_0() (REG32(ADR_TM1_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM1_DUMMY_BIT_1() (REG32(ADR_TM1_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM2_MILISECOND_TIMER() (REG32(ADR_TM2_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM2_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM2_DUMMY_BIT_0() (REG32(ADR_TM2_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM2_DUMMY_BIT_1() (REG32(ADR_TM2_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM3_MILISECOND_TIMER() (REG32(ADR_TM3_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM3_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM3_DUMMY_BIT_0() (REG32(ADR_TM3_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM3_DUMMY_BIT_1() (REG32(ADR_TM3_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00000000)
++#define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00000000)
++#define DEF_PAD6() (REG32(ADR_PAD6)) = (0x00000008)
++#define DEF_PAD7() (REG32(ADR_PAD7)) = (0x00000008)
++#define DEF_PAD8() (REG32(ADR_PAD8)) = (0x00000008)
++#define DEF_PAD9() (REG32(ADR_PAD9)) = (0x00000008)
++#define DEF_PAD11() (REG32(ADR_PAD11)) = (0x00000008)
++#define DEF_PAD15() (REG32(ADR_PAD15)) = (0x0000000a)
++#define DEF_PAD16() (REG32(ADR_PAD16)) = (0x0000000a)
++#define DEF_PAD17() (REG32(ADR_PAD17)) = (0x0000000a)
++#define DEF_PAD18() (REG32(ADR_PAD18)) = (0x0000000a)
++#define DEF_PAD19() (REG32(ADR_PAD19)) = (0x00007000)
++#define DEF_PAD20() (REG32(ADR_PAD20)) = (0x0000000a)
++#define DEF_PAD21() (REG32(ADR_PAD21)) = (0x0000000a)
++#define DEF_PAD22() (REG32(ADR_PAD22)) = (0x00000009)
++#define DEF_PAD24() (REG32(ADR_PAD24)) = (0x00000008)
++#define DEF_PAD25() (REG32(ADR_PAD25)) = (0x0000000b)
++#define DEF_PAD27() (REG32(ADR_PAD27)) = (0x00000008)
++#define DEF_PAD28() (REG32(ADR_PAD28)) = (0x00000008)
++#define DEF_PAD29() (REG32(ADR_PAD29)) = (0x00000009)
++#define DEF_PAD30() (REG32(ADR_PAD30)) = (0x0000000a)
++#define DEF_PAD31() (REG32(ADR_PAD31)) = (0x0000000a)
++#define DEF_PAD32() (REG32(ADR_PAD32)) = (0x0000000a)
++#define DEF_PAD33() (REG32(ADR_PAD33)) = (0x0000000a)
++#define DEF_PAD34() (REG32(ADR_PAD34)) = (0x0000000a)
++#define DEF_PAD42() (REG32(ADR_PAD42)) = (0x0000000a)
++#define DEF_PAD43() (REG32(ADR_PAD43)) = (0x0000000a)
++#define DEF_PAD44() (REG32(ADR_PAD44)) = (0x0000000a)
++#define DEF_PAD45() (REG32(ADR_PAD45)) = (0x0000000a)
++#define DEF_PAD46() (REG32(ADR_PAD46)) = (0x0000000a)
++#define DEF_PAD47() (REG32(ADR_PAD47)) = (0x00100000)
++#define DEF_PAD48() (REG32(ADR_PAD48)) = (0x00100808)
++#define DEF_PAD49() (REG32(ADR_PAD49)) = (0x00100008)
++#define DEF_PAD50() (REG32(ADR_PAD50)) = (0x00100008)
++#define DEF_PAD51() (REG32(ADR_PAD51)) = (0x00100008)
++#define DEF_PAD52() (REG32(ADR_PAD52)) = (0x00100000)
++#define DEF_PAD53() (REG32(ADR_PAD53)) = (0x0000000a)
++#define DEF_PAD54() (REG32(ADR_PAD54)) = (0x00000000)
++#define DEF_PAD56() (REG32(ADR_PAD56)) = (0x00000000)
++#define DEF_PAD57() (REG32(ADR_PAD57)) = (0x00000008)
++#define DEF_PAD58() (REG32(ADR_PAD58)) = (0x0000000a)
++#define DEF_PAD59() (REG32(ADR_PAD59)) = (0x0000000a)
++#define DEF_PAD60() (REG32(ADR_PAD60)) = (0x0000000a)
++#define DEF_PAD61() (REG32(ADR_PAD61)) = (0x0000000a)
++#define DEF_PAD62() (REG32(ADR_PAD62)) = (0x0000000a)
++#define DEF_PAD64() (REG32(ADR_PAD64)) = (0x00000009)
++#define DEF_PAD65() (REG32(ADR_PAD65)) = (0x00000009)
++#define DEF_PAD66() (REG32(ADR_PAD66)) = (0x00000008)
++#define DEF_PAD68() (REG32(ADR_PAD68)) = (0x00000008)
++#define DEF_PAD67() (REG32(ADR_PAD67)) = (0x00000159)
++#define DEF_PAD69() (REG32(ADR_PAD69)) = (0x0000000b)
++#define DEF_PAD70() (REG32(ADR_PAD70)) = (0x00000008)
++#define DEF_PAD231() (REG32(ADR_PAD231)) = (0x00000008)
++#define DEF_PIN_SEL_0() (REG32(ADR_PIN_SEL_0)) = (0x00000000)
++#define DEF_PIN_SEL_1() (REG32(ADR_PIN_SEL_1)) = (0x00000000)
++#define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000)
++#define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff)
++#define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000)
++#define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000)
++#define DEF_CARD_PKT_STATUS_TEST() (REG32(ADR_CARD_PKT_STATUS_TEST)) = (0x00000000)
++#define DEF_SYSTEM_INFORMATION_REG() (REG32(ADR_SYSTEM_INFORMATION_REG)) = (0x00000000)
++#define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000)
++#define DEF_SDIO_FIFO_WR_THLD_REG() (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (0x00000000)
++#define DEF_SDIO_FIFO_WR_LIMIT_REG() (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (0x00000000)
++#define DEF_SDIO_TX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (0x00000000)
++#define DEF_SDIO_THLD_FOR_CMD53RD_REG() (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (0x00000000)
++#define DEF_SDIO_RX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (0x00000000)
++#define DEF_SDIO_LOG_START_END_DATA_REG() (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (0x00000000)
++#define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000)
++#define DEF_SDIO_LAST_CMD_INDEX_CRC_REG() (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (0x00000000)
++#define DEF_SDIO_LAST_CMD_ARG_REG() (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (0x00000000)
++#define DEF_SDIO_BUS_STATE_DEBUG_MONITOR() (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (0x00000000)
++#define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000)
++#define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00000000)
++#define DEF_CMD52_DATA_FOR_LAST_TIME() (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (0x00000000)
++#define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000)
++#define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000)
++#define DEF_IO_REG_PORT_REG() (REG32(ADR_IO_REG_PORT_REG)) = (0x00010020)
++#define DEF_SDIO_FIFO_ERROR_CNT() (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (0x00000000)
++#define DEF_SDIO_CRC7_CRC16_ERROR_REG() (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (0x00000000)
++#define DEF_SDIO_BLOCK_CNT_INFO() (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (0x00000000)
++#define DEF_RX_DATA_CMD52_ABORT_COUNT() (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (0x00000000)
++#define DEF_FIFO_PTR_READ_BLOCK_CNT() (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (0x00000000)
++#define DEF_TX_TIME_OUT_READ_CTRL() (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (0x00000000)
++#define DEF_SDIO_TX_ALLOC_REG() (REG32(ADR_SDIO_TX_ALLOC_REG)) = (0x00000000)
++#define DEF_SDIO_TX_INFORM() (REG32(ADR_SDIO_TX_INFORM)) = (0x00000000)
++#define DEF_F1_BLOCK_SIZE_0_REG() (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (0x00000000)
++#define DEF_SDIO_COMMAND_LOG_DATA_31_0() (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (0x000000ec)
++#define DEF_SDIO_COMMAND_LOG_DATA_63_32() (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (0xce000000)
++#define DEF_SYSTEM_INFORMATION_REGISTER() (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (0x00000000)
++#define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000)
++#define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000)
++#define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000)
++#define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x00000000)
++#define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000)
++#define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000)
++#define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000)
++#define DEF_RX_QUOTA() (REG32(ADR_RX_QUOTA)) = (0x00000000)
++#define DEF_CONDITION_NUMBER() (REG32(ADR_CONDITION_NUMBER)) = (0x00000004)
++#define DEF_HOST_PATH() (REG32(ADR_HOST_PATH)) = (0x00000001)
++#define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000)
++#define DEF_DEBUG_BURST_MODE() (REG32(ADR_DEBUG_BURST_MODE)) = (0x00000000)
++#define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006)
++#define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e)
++#define DEF_SPI_STS() (REG32(ADR_SPI_STS)) = (0x00000000)
++#define DEF_TX_ALLOC_SET() (REG32(ADR_TX_ALLOC_SET)) = (0x00000000)
++#define DEF_TX_ALLOC() (REG32(ADR_TX_ALLOC)) = (0x00000000)
++#define DEF_DBG_CNT() (REG32(ADR_DBG_CNT)) = (0x00000000)
++#define DEF_DBG_CNT2() (REG32(ADR_DBG_CNT2)) = (0x00000000)
++#define DEF_DBG_CNT3() (REG32(ADR_DBG_CNT3)) = (0x00000000)
++#define DEF_DBG_CNT4() (REG32(ADR_DBG_CNT4)) = (0x00000000)
++#define DEF_INT_TAG() (REG32(ADR_INT_TAG)) = (0x00000000)
++#define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x00000074)
++#define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000)
++#define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000)
++#define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000)
++#define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000)
++#define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000)
++#define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000)
++#define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000)
++#define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001)
++#define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003)
++#define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000)
++#define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000)
++#define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000)
++#define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x00000000)
++#define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8)
++#define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1)
++#define DEF_DAT_UART_DATA() (REG32(ADR_DAT_UART_DATA)) = (0x00000000)
++#define DEF_DAT_UART_IER() (REG32(ADR_DAT_UART_IER)) = (0x00000000)
++#define DEF_DAT_UART_FCR() (REG32(ADR_DAT_UART_FCR)) = (0x00000001)
++#define DEF_DAT_UART_LCR() (REG32(ADR_DAT_UART_LCR)) = (0x00000003)
++#define DEF_DAT_UART_MCR() (REG32(ADR_DAT_UART_MCR)) = (0x00000000)
++#define DEF_DAT_UART_LSR() (REG32(ADR_DAT_UART_LSR)) = (0x00000000)
++#define DEF_DAT_UART_MSR() (REG32(ADR_DAT_UART_MSR)) = (0x00000000)
++#define DEF_DAT_UART_SPR() (REG32(ADR_DAT_UART_SPR)) = (0x00000000)
++#define DEF_DAT_UART_RTHR() (REG32(ADR_DAT_UART_RTHR)) = (0x000000c8)
++#define DEF_DAT_UART_ISR() (REG32(ADR_DAT_UART_ISR)) = (0x000000c1)
++#define DEF_INT_MASK() (REG32(ADR_INT_MASK)) = (0xffffffff)
++#define DEF_INT_MODE() (REG32(ADR_INT_MODE)) = (0x00000000)
++#define DEF_INT_IRQ_STS() (REG32(ADR_INT_IRQ_STS)) = (0x00000000)
++#define DEF_INT_FIQ_STS() (REG32(ADR_INT_FIQ_STS)) = (0x00000000)
++#define DEF_INT_IRQ_RAW() (REG32(ADR_INT_IRQ_RAW)) = (0x00000000)
++#define DEF_INT_FIQ_RAW() (REG32(ADR_INT_FIQ_RAW)) = (0x00000000)
++#define DEF_INT_PERI_MASK() (REG32(ADR_INT_PERI_MASK)) = (0xffffffff)
++#define DEF_INT_PERI_STS() (REG32(ADR_INT_PERI_STS)) = (0x00000000)
++#define DEF_INT_PERI_RAW() (REG32(ADR_INT_PERI_RAW)) = (0x00000000)
++#define DEF_INT_GPI_CFG() (REG32(ADR_INT_GPI_CFG)) = (0x00000000)
++#define DEF_SYS_INT_FOR_HOST() (REG32(ADR_SYS_INT_FOR_HOST)) = (0x00000001)
++#define DEF_SPI_IPC() (REG32(ADR_SPI_IPC)) = (0x00000000)
++#define DEF_SDIO_IPC() (REG32(ADR_SDIO_IPC)) = (0x00000000)
++#define DEF_SDIO_MASK() (REG32(ADR_SDIO_MASK)) = (0xffffffff)
++#define DEF_SDIO_IRQ_STS() (REG32(ADR_SDIO_IRQ_STS)) = (0x00000000)
++#define DEF_SD_PERI_MASK() (REG32(ADR_SD_PERI_MASK)) = (0xffffffff)
++#define DEF_SD_PERI_STS() (REG32(ADR_SD_PERI_STS)) = (0x00000000)
++#define DEF_DBG_SPI_MODE() (REG32(ADR_DBG_SPI_MODE)) = (0x00000000)
++#define DEF_DBG_RX_QUOTA() (REG32(ADR_DBG_RX_QUOTA)) = (0x00000000)
++#define DEF_DBG_CONDITION_NUMBER() (REG32(ADR_DBG_CONDITION_NUMBER)) = (0x00000004)
++#define DEF_DBG_HOST_PATH() (REG32(ADR_DBG_HOST_PATH)) = (0x00000001)
++#define DEF_DBG_TX_SEG() (REG32(ADR_DBG_TX_SEG)) = (0x00000000)
++#define DEF_DBG_DEBUG_BURST_MODE() (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (0x00000000)
++#define DEF_DBG_SPI_TO_PHY_PARAM1() (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (0x000e0006)
++#define DEF_DBG_SPI_TO_PHY_PARAM2() (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (0x000e000e)
++#define DEF_DBG_SPI_STS() (REG32(ADR_DBG_SPI_STS)) = (0x00000000)
++#define DEF_DBG_TX_ALLOC_SET() (REG32(ADR_DBG_TX_ALLOC_SET)) = (0x00000000)
++#define DEF_DBG_TX_ALLOC() (REG32(ADR_DBG_TX_ALLOC)) = (0x00000000)
++#define DEF_DBG_DBG_CNT() (REG32(ADR_DBG_DBG_CNT)) = (0x00000000)
++#define DEF_DBG_DBG_CNT2() (REG32(ADR_DBG_DBG_CNT2)) = (0x00000000)
++#define DEF_DBG_DBG_CNT3() (REG32(ADR_DBG_DBG_CNT3)) = (0x00000000)
++#define DEF_DBG_DBG_CNT4() (REG32(ADR_DBG_DBG_CNT4)) = (0x00000000)
++#define DEF_DBG_INT_TAG() (REG32(ADR_DBG_INT_TAG)) = (0x00000000)
++#define DEF_BOOT_ADDR() (REG32(ADR_BOOT_ADDR)) = (0x00000000)
++#define DEF_VERIFY_DATA() (REG32(ADR_VERIFY_DATA)) = (0x5e11aa11)
++#define DEF_FLASH_ADDR() (REG32(ADR_FLASH_ADDR)) = (0x00000000)
++#define DEF_SRAM_ADDR() (REG32(ADR_SRAM_ADDR)) = (0x00000000)
++#define DEF_LEN() (REG32(ADR_LEN)) = (0x00000000)
++#define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x000f000f)
++#define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00040001)
++#define DEF_CHECK_SUM_RESULT() (REG32(ADR_CHECK_SUM_RESULT)) = (0x00000000)
++#define DEF_CHECK_SUM_IN_FILE() (REG32(ADR_CHECK_SUM_IN_FILE)) = (0x00000000)
++#define DEF_COMMAND_LEN() (REG32(ADR_COMMAND_LEN)) = (0x00000000)
++#define DEF_COMMAND_ADDR() (REG32(ADR_COMMAND_ADDR)) = (0x00000000)
++#define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000)
++#define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000)
++#define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa)
++#define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001)
++#define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000)
++#define DEF_PMU_0() (REG32(ADR_PMU_0)) = (0x0f000040)
++#define DEF_PMU_1() (REG32(ADR_PMU_1)) = (0x015d015d)
++#define DEF_PMU_2() (REG32(ADR_PMU_2)) = (0x00000000)
++#define DEF_PMU_3() (REG32(ADR_PMU_3)) = (0x55550000)
++#define DEF_RTC_1() (REG32(ADR_RTC_1)) = (0x7fff0000)
++#define DEF_RTC_2() (REG32(ADR_RTC_2)) = (0x00000003)
++#define DEF_RTC_3W() (REG32(ADR_RTC_3W)) = (0x00000000)
++#define DEF_RTC_3R() (REG32(ADR_RTC_3R)) = (0x00000000)
++#define DEF_RTC_4() (REG32(ADR_RTC_4)) = (0x00000000)
++#define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000)
++#define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000)
++#define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa)
++#define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001)
++#define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000)
++#define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x02700008)
++#define DEF_SDIO_WAKE_MODE() (REG32(ADR_SDIO_WAKE_MODE)) = (0x00000000)
++#define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000)
++#define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000)
++#define DEF_THREASHOLD() (REG32(ADR_THREASHOLD)) = (0x09000000)
++#define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000)
++#define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000)
++#define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450)
++#define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008)
++#define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000)
++#define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000)
++#define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000)
++#define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_0() (REG32(ADR_PACKET_COUNTER_INFO_0)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_1() (REG32(ADR_PACKET_COUNTER_INFO_1)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_2() (REG32(ADR_PACKET_COUNTER_INFO_2)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_3() (REG32(ADR_PACKET_COUNTER_INFO_3)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_4() (REG32(ADR_PACKET_COUNTER_INFO_4)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_5() (REG32(ADR_PACKET_COUNTER_INFO_5)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_6() (REG32(ADR_PACKET_COUNTER_INFO_6)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_7() (REG32(ADR_PACKET_COUNTER_INFO_7)) = (0x00000000)
++#define DEF_SDIO_TX_RX_FAIL_COUNTER_0() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (0x00000000)
++#define DEF_SDIO_TX_RX_FAIL_COUNTER_1() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_1() (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_8() (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_9() (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_10() (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (0x00000000)
++#define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000)
++#define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000)
++#define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000)
++#define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000)
++#define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000)
++#define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000)
++#define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000)
++#define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000)
++#define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000)
++#define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000)
++#define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000)
++#define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000)
++#define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000)
++#define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000)
++#define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000)
++#define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000)
++#define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000)
++#define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000)
++#define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000)
++#define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000)
++#define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002)
++#define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0)
++#define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002)
++#define DEF_EFUSE_AHB_RDATA_0() (REG32(ADR_EFUSE_AHB_RDATA_0)) = (0x00000000)
++#define DEF_EFUSE_WDATA_0() (REG32(ADR_EFUSE_WDATA_0)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_1() (REG32(ADR_EFUSE_AHB_RDATA_1)) = (0x00000000)
++#define DEF_EFUSE_WDATA_1() (REG32(ADR_EFUSE_WDATA_1)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_2() (REG32(ADR_EFUSE_AHB_RDATA_2)) = (0x00000000)
++#define DEF_EFUSE_WDATA_2() (REG32(ADR_EFUSE_WDATA_2)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_3() (REG32(ADR_EFUSE_AHB_RDATA_3)) = (0x00000000)
++#define DEF_EFUSE_WDATA_3() (REG32(ADR_EFUSE_WDATA_3)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_4() (REG32(ADR_EFUSE_AHB_RDATA_4)) = (0x00000000)
++#define DEF_EFUSE_WDATA_4() (REG32(ADR_EFUSE_WDATA_4)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_5() (REG32(ADR_EFUSE_AHB_RDATA_5)) = (0x00000000)
++#define DEF_EFUSE_WDATA_5() (REG32(ADR_EFUSE_WDATA_5)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_6() (REG32(ADR_EFUSE_AHB_RDATA_6)) = (0x00000000)
++#define DEF_EFUSE_WDATA_6() (REG32(ADR_EFUSE_WDATA_6)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_7() (REG32(ADR_EFUSE_AHB_RDATA_7)) = (0x00000000)
++#define DEF_EFUSE_WDATA_7() (REG32(ADR_EFUSE_WDATA_7)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD0_EN() (REG32(ADR_EFUSE_SPI_RD0_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD1_EN() (REG32(ADR_EFUSE_SPI_RD1_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD2_EN() (REG32(ADR_EFUSE_SPI_RD2_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD3_EN() (REG32(ADR_EFUSE_SPI_RD3_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD4_EN() (REG32(ADR_EFUSE_SPI_RD4_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD5_EN() (REG32(ADR_EFUSE_SPI_RD5_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD6_EN() (REG32(ADR_EFUSE_SPI_RD6_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD7_EN() (REG32(ADR_EFUSE_SPI_RD7_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_BUSY() (REG32(ADR_EFUSE_SPI_BUSY)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_0() (REG32(ADR_EFUSE_SPI_RDATA_0)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_1() (REG32(ADR_EFUSE_SPI_RDATA_1)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_2() (REG32(ADR_EFUSE_SPI_RDATA_2)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_3() (REG32(ADR_EFUSE_SPI_RDATA_3)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_4() (REG32(ADR_EFUSE_SPI_RDATA_4)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_5() (REG32(ADR_EFUSE_SPI_RDATA_5)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_6() (REG32(ADR_EFUSE_SPI_RDATA_6)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_7() (REG32(ADR_EFUSE_SPI_RDATA_7)) = (0x00000000)
++#define DEF_SMS4_CFG1() (REG32(ADR_SMS4_CFG1)) = (0x00000002)
++#define DEF_SMS4_CFG2() (REG32(ADR_SMS4_CFG2)) = (0x00000000)
++#define DEF_SMS4_MODE1() (REG32(ADR_SMS4_MODE1)) = (0x00000000)
++#define DEF_SMS4_TRIG() (REG32(ADR_SMS4_TRIG)) = (0x00000000)
++#define DEF_SMS4_STATUS1() (REG32(ADR_SMS4_STATUS1)) = (0x00000000)
++#define DEF_SMS4_STATUS2() (REG32(ADR_SMS4_STATUS2)) = (0x00000000)
++#define DEF_SMS4_DATA_IN0() (REG32(ADR_SMS4_DATA_IN0)) = (0x00000000)
++#define DEF_SMS4_DATA_IN1() (REG32(ADR_SMS4_DATA_IN1)) = (0x00000000)
++#define DEF_SMS4_DATA_IN2() (REG32(ADR_SMS4_DATA_IN2)) = (0x00000000)
++#define DEF_SMS4_DATA_IN3() (REG32(ADR_SMS4_DATA_IN3)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT0() (REG32(ADR_SMS4_DATA_OUT0)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT1() (REG32(ADR_SMS4_DATA_OUT1)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT2() (REG32(ADR_SMS4_DATA_OUT2)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT3() (REG32(ADR_SMS4_DATA_OUT3)) = (0x00000000)
++#define DEF_SMS4_KEY_0() (REG32(ADR_SMS4_KEY_0)) = (0x00000000)
++#define DEF_SMS4_KEY_1() (REG32(ADR_SMS4_KEY_1)) = (0x00000000)
++#define DEF_SMS4_KEY_2() (REG32(ADR_SMS4_KEY_2)) = (0x00000000)
++#define DEF_SMS4_KEY_3() (REG32(ADR_SMS4_KEY_3)) = (0x00000000)
++#define DEF_SMS4_MODE_IV0() (REG32(ADR_SMS4_MODE_IV0)) = (0x00000000)
++#define DEF_SMS4_MODE_IV1() (REG32(ADR_SMS4_MODE_IV1)) = (0x00000000)
++#define DEF_SMS4_MODE_IV2() (REG32(ADR_SMS4_MODE_IV2)) = (0x00000000)
++#define DEF_SMS4_MODE_IV3() (REG32(ADR_SMS4_MODE_IV3)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC0() (REG32(ADR_SMS4_OFB_ENC0)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC1() (REG32(ADR_SMS4_OFB_ENC1)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC2() (REG32(ADR_SMS4_OFB_ENC2)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC3() (REG32(ADR_SMS4_OFB_ENC3)) = (0x00000000)
++#define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000)
++#define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000)
++#define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000)
++#define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000)
++#define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000)
++#define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5)
++#define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6)
++#define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9)
++#define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1)
++#define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9)
++#define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1)
++#define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe)
++#define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe)
++#define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000)
++#define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000)
++#define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000)
++#define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006)
++#define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001)
++#define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003)
++#define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005)
++#define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007)
++#define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008)
++#define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001)
++#define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808)
++#define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000)
++#define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008)
++#define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e)
++#define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838)
++#define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008)
++#define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008)
++#define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000)
++#define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034)
++#define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004)
++#define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004)
++#define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00)
++#define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000)
++#define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000)
++#define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000)
++#define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008)
++#define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000)
++#define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000)
++#define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000)
++#define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000)
++#define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000)
++#define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000)
++#define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff)
++#define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000)
++#define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000)
++#define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000)
++#define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000)
++#define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000)
++#define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000)
++#define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000)
++#define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000)
++#define DEF_WSID0_TID0_RX_SEQ() (REG32(ADR_WSID0_TID0_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID1_RX_SEQ() (REG32(ADR_WSID0_TID1_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID2_RX_SEQ() (REG32(ADR_WSID0_TID2_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID3_RX_SEQ() (REG32(ADR_WSID0_TID3_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID4_RX_SEQ() (REG32(ADR_WSID0_TID4_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID5_RX_SEQ() (REG32(ADR_WSID0_TID5_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID6_RX_SEQ() (REG32(ADR_WSID0_TID6_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID7_RX_SEQ() (REG32(ADR_WSID0_TID7_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID0_RX_SEQ() (REG32(ADR_WSID1_TID0_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID1_RX_SEQ() (REG32(ADR_WSID1_TID1_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID2_RX_SEQ() (REG32(ADR_WSID1_TID2_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID3_RX_SEQ() (REG32(ADR_WSID1_TID3_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID4_RX_SEQ() (REG32(ADR_WSID1_TID4_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID5_RX_SEQ() (REG32(ADR_WSID1_TID5_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID6_RX_SEQ() (REG32(ADR_WSID1_TID6_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID7_RX_SEQ() (REG32(ADR_WSID1_TID7_RX_SEQ)) = (0x00000000)
++#define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79)
++#define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000)
++#define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000)
++#define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e)
++#define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000)
++#define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000)
++#define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000)
++#define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000)
++#define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000)
++#define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00c00c00)
++#define DEF_MTX_EDCCA_TOUT() (REG32(ADR_MTX_EDCCA_TOUT)) = (0x00000200)
++#define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000)
++#define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000)
++#define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x00000042)
++#define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000)
++#define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064)
++#define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000)
++#define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000)
++#define DEF_MTX_BCN_CFG0() (REG32(ADR_MTX_BCN_CFG0)) = (0x00000000)
++#define DEF_MTX_BCN_CFG1() (REG32(ADR_MTX_BCN_CFG1)) = (0x00000000)
++#define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000)
++#define DEF_MTX_DBG_CTRL() (REG32(ADR_MTX_DBG_CTRL)) = (0x00000000)
++#define DEF_MTX_DBG_DAT0() (REG32(ADR_MTX_DBG_DAT0)) = (0x00000000)
++#define DEF_MTX_DBG_DAT1() (REG32(ADR_MTX_DBG_DAT1)) = (0x00000000)
++#define DEF_MTX_DBG_DAT2() (REG32(ADR_MTX_DBG_DAT2)) = (0x00000000)
++#define DEF_MTX_DUR_TOUT() (REG32(ADR_MTX_DUR_TOUT)) = (0x00002c2c)
++#define DEF_MTX_DUR_IFS() (REG32(ADR_MTX_DUR_IFS)) = (0x12d40a05)
++#define DEF_MTX_DUR_SIFS_G() (REG32(ADR_MTX_DUR_SIFS_G)) = (0x12c90100)
++#define DEF_MTX_DBG_DAT3() (REG32(ADR_MTX_DBG_DAT3)) = (0x00000000)
++#define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000)
++#define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000)
++#define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000)
++#define DEF_MTX_DBG_DAT4() (REG32(ADR_MTX_DBG_DAT4)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ0_MTX_Q_BKF_CNT() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ0_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ1_MTX_Q_BKF_CNT() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ1_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ2_MTX_Q_BKF_CNT() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ2_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ3_MTX_Q_BKF_CNT() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ3_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ4_MTX_Q_BKF_CNT() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ4_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000)
++#define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000)
++#define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000)
++#define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000)
++#define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000)
++#define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000)
++#define DEF_INFO0() (REG32(ADR_INFO0)) = (0x00000000)
++#define DEF_INFO1() (REG32(ADR_INFO1)) = (0x00000100)
++#define DEF_INFO2() (REG32(ADR_INFO2)) = (0x00000200)
++#define DEF_INFO3() (REG32(ADR_INFO3)) = (0x00000300)
++#define DEF_INFO4() (REG32(ADR_INFO4)) = (0x00000140)
++#define DEF_INFO5() (REG32(ADR_INFO5)) = (0x00000240)
++#define DEF_INFO6() (REG32(ADR_INFO6)) = (0x00000340)
++#define DEF_INFO7() (REG32(ADR_INFO7)) = (0x00000001)
++#define DEF_INFO8() (REG32(ADR_INFO8)) = (0x00000101)
++#define DEF_INFO9() (REG32(ADR_INFO9)) = (0x00000201)
++#define DEF_INFO10() (REG32(ADR_INFO10)) = (0x00000301)
++#define DEF_INFO11() (REG32(ADR_INFO11)) = (0x00000401)
++#define DEF_INFO12() (REG32(ADR_INFO12)) = (0x00000501)
++#define DEF_INFO13() (REG32(ADR_INFO13)) = (0x00000601)
++#define DEF_INFO14() (REG32(ADR_INFO14)) = (0x00000701)
++#define DEF_INFO15() (REG32(ADR_INFO15)) = (0x00030002)
++#define DEF_INFO16() (REG32(ADR_INFO16)) = (0x00030102)
++#define DEF_INFO17() (REG32(ADR_INFO17)) = (0x00030202)
++#define DEF_INFO18() (REG32(ADR_INFO18)) = (0x00030302)
++#define DEF_INFO19() (REG32(ADR_INFO19)) = (0x00030402)
++#define DEF_INFO20() (REG32(ADR_INFO20)) = (0x00030502)
++#define DEF_INFO21() (REG32(ADR_INFO21)) = (0x00030602)
++#define DEF_INFO22() (REG32(ADR_INFO22)) = (0x00030702)
++#define DEF_INFO23() (REG32(ADR_INFO23)) = (0x00030082)
++#define DEF_INFO24() (REG32(ADR_INFO24)) = (0x00030182)
++#define DEF_INFO25() (REG32(ADR_INFO25)) = (0x00030282)
++#define DEF_INFO26() (REG32(ADR_INFO26)) = (0x00030382)
++#define DEF_INFO27() (REG32(ADR_INFO27)) = (0x00030482)
++#define DEF_INFO28() (REG32(ADR_INFO28)) = (0x00030582)
++#define DEF_INFO29() (REG32(ADR_INFO29)) = (0x00030682)
++#define DEF_INFO30() (REG32(ADR_INFO30)) = (0x00030782)
++#define DEF_INFO31() (REG32(ADR_INFO31)) = (0x00030042)
++#define DEF_INFO32() (REG32(ADR_INFO32)) = (0x00030142)
++#define DEF_INFO33() (REG32(ADR_INFO33)) = (0x00030242)
++#define DEF_INFO34() (REG32(ADR_INFO34)) = (0x00030342)
++#define DEF_INFO35() (REG32(ADR_INFO35)) = (0x00030442)
++#define DEF_INFO36() (REG32(ADR_INFO36)) = (0x00030542)
++#define DEF_INFO37() (REG32(ADR_INFO37)) = (0x00030642)
++#define DEF_INFO38() (REG32(ADR_INFO38)) = (0x00030742)
++#define DEF_INFO_MASK() (REG32(ADR_INFO_MASK)) = (0x00007fc7)
++#define DEF_INFO_RATE_OFFSET() (REG32(ADR_INFO_RATE_OFFSET)) = (0x00040000)
++#define DEF_INFO_IDX_ADDR() (REG32(ADR_INFO_IDX_ADDR)) = (0x00000000)
++#define DEF_INFO_LEN_ADDR() (REG32(ADR_INFO_LEN_ADDR)) = (0x00000000)
++#define DEF_IC_TIME_TAG_0() (REG32(ADR_IC_TIME_TAG_0)) = (0x00000000)
++#define DEF_IC_TIME_TAG_1() (REG32(ADR_IC_TIME_TAG_1)) = (0x00000000)
++#define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000)
++#define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000)
++#define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000)
++#define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000)
++#define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000)
++#define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb)
++#define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b)
++#define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02)
++#define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000)
++#define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000)
++#define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000)
++#define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000)
++#define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000)
++#define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000)
++#define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000)
++#define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000)
++#define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000)
++#define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006)
++#define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000)
++#define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000)
++#define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000)
++#define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000)
++#define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000)
++#define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000)
++#define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000)
++#define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000)
++#define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000)
++#define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000)
++#define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000)
++#define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000)
++#define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000)
++#define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000)
++#define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000)
++#define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000)
++#define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000)
++#define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000)
++#define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000)
++#define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000)
++#define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000)
++#define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000)
++#define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000)
++#define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000)
++#define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000)
++#define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000)
++#define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000)
++#define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000)
++#define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000)
++#define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000)
++#define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000)
++#define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000)
++#define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000)
++#define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000)
++#define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000)
++#define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000)
++#define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000)
++#define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000)
++#define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000)
++#define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000)
++#define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000)
++#define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000)
++#define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000)
++#define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000)
++#define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000)
++#define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000)
++#define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000)
++#define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000)
++#define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000)
++#define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000)
++#define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000)
++#define DEF_CBR_HARD_WIRE_PIN_REGISTER() (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
++#define DEF_CBR_MANUAL_ENABLE_REGISTER() (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (0x00001fc0)
++#define DEF_CBR_LDO_REGISTER() (REG32(ADR_CBR_LDO_REGISTER)) = (0x2496db1b)
++#define DEF_CBR_ABB_REGISTER_1() (REG32(ADR_CBR_ABB_REGISTER_1)) = (0x151558dd)
++#define DEF_CBR_ABB_REGISTER_2() (REG32(ADR_CBR_ABB_REGISTER_2)) = (0x01011a88)
++#define DEF_CBR_TX_FE_REGISTER() (REG32(ADR_CBR_TX_FE_REGISTER)) = (0x3cbe84fe)
++#define DEF_CBR_RX_FE_REGISTER_1() (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (0x00657579)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
++#define DEF_CBR_RX_FSM_REGISTER() (REG32(ADR_CBR_RX_FSM_REGISTER)) = (0x00000ca8)
++#define DEF_CBR_RX_ADC_REGISTER() (REG32(ADR_CBR_RX_ADC_REGISTER)) = (0x002a0224)
++#define DEF_CBR_TX_DAC_REGISTER() (REG32(ADR_CBR_TX_DAC_REGISTER)) = (0x00002655)
++#define DEF_CBR_SX_ENABLE_RGISTER() (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (0x0000647c)
++#define DEF_CBR_SYN_RGISTER_1() (REG32(ADR_CBR_SYN_RGISTER_1)) = (0xaa800000)
++#define DEF_CBR_SYN_RGISTER_2() (REG32(ADR_CBR_SYN_RGISTER_2)) = (0x00550800)
++#define DEF_CBR_SYN_PFD_CHP() (REG32(ADR_CBR_SYN_PFD_CHP)) = (0x07c0894a)
++#define DEF_CBR_SYN_VCO_LOBF() (REG32(ADR_CBR_SYN_VCO_LOBF)) = (0xfcccca27)
++#define DEF_CBR_SYN_DIV_SDM_XOSC() (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (0x2773c93c)
++#define DEF_CBR_SYN_LCK1() (REG32(ADR_CBR_SYN_LCK1)) = (0x00000a7c)
++#define DEF_CBR_SYN_LCK2() (REG32(ADR_CBR_SYN_LCK2)) = (0x01c67ff4)
++#define DEF_CBR_DPLL_VCO_REGISTER() (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (0x00103014)
++#define DEF_CBR_DPLL_CP_PFD_REGISTER() (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (0x0001848c)
++#define DEF_CBR_DPLL_DIVIDER_REGISTER() (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (0x034061e0)
++#define DEF_CBR_DCOC_IDAC_REGISTER1() (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER2() (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER3() (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER4() (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER5() (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER6() (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER7() (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER8() (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (0x00820820)
++#define DEF_CBR_RCAL_REGISTER() (REG32(ADR_CBR_RCAL_REGISTER)) = (0x00004080)
++#define DEF_CBR_MANUAL_REGISTER() (REG32(ADR_CBR_MANUAL_REGISTER)) = (0x00003e7e)
++#define DEF_CBR_TRX_DUMMY_REGISTER() (REG32(ADR_CBR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_CBR_SX_DUMMY_REGISTER() (REG32(ADR_CBR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_CBR_RG_PKT_GEN_0() (REG32(ADR_CBR_RG_PKT_GEN_0)) = (0x00000000)
++#define DEF_CBR_RG_PKT_GEN_1() (REG32(ADR_CBR_RG_PKT_GEN_1)) = (0x00000000)
++#define DEF_CBR_RG_PKT_GEN_2() (REG32(ADR_CBR_RG_PKT_GEN_2)) = (0x00000000)
++#define DEF_CBR_RG_INTEGRATION() (REG32(ADR_CBR_RG_INTEGRATION)) = (0x00000000)
++#define DEF_CBR_RG_PKT_GEN_TXCNT() (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (0x00000000)
++#define DEF_CBR_PATTERN_GEN() (REG32(ADR_CBR_PATTERN_GEN)) = (0xff000000)
++#define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000)
++#define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000)
++#define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000)
++#define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000)
++#define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000)
++#define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000)
++#define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000)
++#define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000)
++#define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000)
++#define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000)
++#define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000)
++#define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000)
++#define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000)
++#define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000)
++#define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff)
++#define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002)
++#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000)
++#define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000)
++#define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000)
++#define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000)
++#define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000)
++#define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000)
++#define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000)
++#define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000)
++#define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000)
++#define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000)
++#define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001)
++#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000)
++#define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000)
++#define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000)
++#define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000)
++#define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000)
++#define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000)
++#define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000)
++#define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000)
++#define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000)
++#define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213)
++#define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000)
++#define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000)
++#define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000)
++#define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000)
++#define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000)
++#define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000)
++#define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c)
++#define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000)
++#define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000)
++#define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000)
++#define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000)
++#define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001)
++#define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641)
++#define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000)
++#define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201)
++#define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000)
++#define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100)
++#define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000)
++#define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000)
++#define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000)
++#define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000)
++#define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000)
++#define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000)
++#define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000)
++#define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100)
++#define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000)
++#define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000)
++#define DEF_PHY_EN_0() (REG32(ADR_PHY_EN_0)) = (0x00000014)
++#define DEF_PHY_EN_1() (REG32(ADR_PHY_EN_1)) = (0x00000000)
++#define DEF_SVN_VERSION_REG() (REG32(ADR_SVN_VERSION_REG)) = (0x00000000)
++#define DEF_PHY_PKT_GEN_0() (REG32(ADR_PHY_PKT_GEN_0)) = (0x00000064)
++#define DEF_PHY_PKT_GEN_1() (REG32(ADR_PHY_PKT_GEN_1)) = (0x00000fff)
++#define DEF_PHY_PKT_GEN_2() (REG32(ADR_PHY_PKT_GEN_2)) = (0x00000003)
++#define DEF_PHY_PKT_GEN_3() (REG32(ADR_PHY_PKT_GEN_3)) = (0x005a0220)
++#define DEF_PHY_PKT_GEN_4() (REG32(ADR_PHY_PKT_GEN_4)) = (0x00000001)
++#define DEF_PHY_REG_00() (REG32(ADR_PHY_REG_00)) = (0x10000000)
++#define DEF_PHY_REG_01() (REG32(ADR_PHY_REG_01)) = (0x00000000)
++#define DEF_PHY_REG_02_AGC() (REG32(ADR_PHY_REG_02_AGC)) = (0x80046771)
++#define DEF_PHY_REG_03_AGC() (REG32(ADR_PHY_REG_03_AGC)) = (0x1f300f6f)
++#define DEF_PHY_REG_04_AGC() (REG32(ADR_PHY_REG_04_AGC)) = (0x663f36d0)
++#define DEF_PHY_REG_05_AGC() (REG32(ADR_PHY_REG_05_AGC)) = (0x106c0000)
++#define DEF_PHY_REG_06_11B_DAGC() (REG32(ADR_PHY_REG_06_11B_DAGC)) = (0x01603fff)
++#define DEF_PHY_REG_07_11B_DAGC() (REG32(ADR_PHY_REG_07_11B_DAGC)) = (0x00600808)
++#define DEF_PHY_REG_08_11GN_DAGC() (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (0xff000160)
++#define DEF_PHY_REG_09_11GN_DAGC() (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (0x00080840)
++#define DEF_PHY_READ_REG_00_DIG_PWR() (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (0x00000000)
++#define DEF_PHY_READ_REG_01_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (0x00000000)
++#define DEF_PHY_READ_REG_02_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (0x00000000)
++#define DEF_PHY_READ_REG_03_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (0x00000000)
++#define DEF_PHY_REG_10_TX_DES() (REG32(ADR_PHY_REG_10_TX_DES)) = (0x00010405)
++#define DEF_PHY_REG_11_TX_DES() (REG32(ADR_PHY_REG_11_TX_DES)) = (0x06090813)
++#define DEF_PHY_REG_12_TX_DES() (REG32(ADR_PHY_REG_12_TX_DES)) = (0x12070000)
++#define DEF_PHY_REG_13_RX_DES() (REG32(ADR_PHY_REG_13_RX_DES)) = (0x01000405)
++#define DEF_PHY_REG_14_RX_DES() (REG32(ADR_PHY_REG_14_RX_DES)) = (0x06090813)
++#define DEF_PHY_REG_15_RX_DES() (REG32(ADR_PHY_REG_15_RX_DES)) = (0x12010000)
++#define DEF_PHY_REG_16_TX_DES_EXCP() (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (0x00000000)
++#define DEF_PHY_REG_17_TX_DES_EXCP() (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (0x10110000)
++#define DEF_PHY_REG_18_RSSI_SNR() (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (0x00fc000f)
++#define DEF_PHY_REG_19_DAC_MANUAL() (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (0x00000000)
++#define DEF_PHY_REG_20_MRX_CNT() (REG32(ADR_PHY_REG_20_MRX_CNT)) = (0x00000000)
++#define DEF_PHY_REG_21_TRX_RAMP() (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (0x3c012801)
++#define DEF_PHY_REG_22_TRX_RAMP() (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (0x24243724)
++#define DEF_PHY_REG_23_ANT() (REG32(ADR_PHY_REG_23_ANT)) = (0x00000011)
++#define DEF_PHY_REG_24_MTX_LEN_CNT() (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_REG_25_MTX_LEN_CNT() (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_REG_26_MRX_LEN_CNT() (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_REG_27_MRX_LEN_CNT() (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_READ_REG_04() (REG32(ADR_PHY_READ_REG_04)) = (0x00000000)
++#define DEF_PHY_READ_REG_05() (REG32(ADR_PHY_READ_REG_05)) = (0x00000000)
++#define DEF_PHY_REG_28_BIST() (REG32(ADR_PHY_REG_28_BIST)) = (0x0000fe3e)
++#define DEF_PHY_READ_REG_06_BIST() (REG32(ADR_PHY_READ_REG_06_BIST)) = (0x00000000)
++#define DEF_PHY_READ_REG_07_BIST() (REG32(ADR_PHY_READ_REG_07_BIST)) = (0x00000000)
++#define DEF_PHY_REG_29_MTRX_MAC() (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (0xffffffff)
++#define DEF_PHY_READ_REG_08_MTRX_MAC() (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (0x00000000)
++#define DEF_PHY_READ_REG_09_MTRX_MAC() (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (0x00000000)
++#define DEF_PHY_REG_30_TX_UP_FIL() (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (0x0ead04f5)
++#define DEF_PHY_REG_31_TX_UP_FIL() (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (0x0fd60080)
++#define DEF_PHY_REG_32_TX_UP_FIL() (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (0x00000009)
++#define DEF_PHY_READ_TBUS() (REG32(ADR_PHY_READ_TBUS)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_00() (REG32(ADR_TX_11B_FIL_COEF_00)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_01() (REG32(ADR_TX_11B_FIL_COEF_01)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_02() (REG32(ADR_TX_11B_FIL_COEF_02)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_03() (REG32(ADR_TX_11B_FIL_COEF_03)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_04() (REG32(ADR_TX_11B_FIL_COEF_04)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_05() (REG32(ADR_TX_11B_FIL_COEF_05)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_06() (REG32(ADR_TX_11B_FIL_COEF_06)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_07() (REG32(ADR_TX_11B_FIL_COEF_07)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_08() (REG32(ADR_TX_11B_FIL_COEF_08)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_09() (REG32(ADR_TX_11B_FIL_COEF_09)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_10() (REG32(ADR_TX_11B_FIL_COEF_10)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_11() (REG32(ADR_TX_11B_FIL_COEF_11)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_12() (REG32(ADR_TX_11B_FIL_COEF_12)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_13() (REG32(ADR_TX_11B_FIL_COEF_13)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_14() (REG32(ADR_TX_11B_FIL_COEF_14)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_15() (REG32(ADR_TX_11B_FIL_COEF_15)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_16() (REG32(ADR_TX_11B_FIL_COEF_16)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_17() (REG32(ADR_TX_11B_FIL_COEF_17)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_18() (REG32(ADR_TX_11B_FIL_COEF_18)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_19() (REG32(ADR_TX_11B_FIL_COEF_19)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_20() (REG32(ADR_TX_11B_FIL_COEF_20)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_21() (REG32(ADR_TX_11B_FIL_COEF_21)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_22() (REG32(ADR_TX_11B_FIL_COEF_22)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_23() (REG32(ADR_TX_11B_FIL_COEF_23)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_24() (REG32(ADR_TX_11B_FIL_COEF_24)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_25() (REG32(ADR_TX_11B_FIL_COEF_25)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_26() (REG32(ADR_TX_11B_FIL_COEF_26)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_27() (REG32(ADR_TX_11B_FIL_COEF_27)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_28() (REG32(ADR_TX_11B_FIL_COEF_28)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_29() (REG32(ADR_TX_11B_FIL_COEF_29)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_30() (REG32(ADR_TX_11B_FIL_COEF_30)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_31() (REG32(ADR_TX_11B_FIL_COEF_31)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_32() (REG32(ADR_TX_11B_FIL_COEF_32)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_33() (REG32(ADR_TX_11B_FIL_COEF_33)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_34() (REG32(ADR_TX_11B_FIL_COEF_34)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_35() (REG32(ADR_TX_11B_FIL_COEF_35)) = (0x00000005)
++#define DEF_TX_11B_FIL_COEF_36() (REG32(ADR_TX_11B_FIL_COEF_36)) = (0x0000003d)
++#define DEF_TX_11B_FIL_COEF_37() (REG32(ADR_TX_11B_FIL_COEF_37)) = (0x00000162)
++#define DEF_TX_11B_FIL_COEF_38() (REG32(ADR_TX_11B_FIL_COEF_38)) = (0x00000400)
++#define DEF_TX_11B_FIL_COEF_39() (REG32(ADR_TX_11B_FIL_COEF_39)) = (0x00000699)
++#define DEF_TX_11B_FIL_COEF_40() (REG32(ADR_TX_11B_FIL_COEF_40)) = (0x00000787)
++#define DEF_TX_11B_PLCP() (REG32(ADR_TX_11B_PLCP)) = (0x00000000)
++#define DEF_TX_11B_RAMP() (REG32(ADR_TX_11B_RAMP)) = (0x0000403c)
++#define DEF_TX_11B_EN_CNT_RST_N() (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (0x00000001)
++#define DEF_TX_11B_EN_CNT() (REG32(ADR_TX_11B_EN_CNT)) = (0x00000000)
++#define DEF_TX_11B_PKT_GEN_CNT() (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (0x00000000)
++#define DEF_RX_11B_DES_DLY() (REG32(ADR_RX_11B_DES_DLY)) = (0x00000044)
++#define DEF_RX_11B_CCA_0() (REG32(ADR_RX_11B_CCA_0)) = (0x00040000)
++#define DEF_RX_11B_CCA_1() (REG32(ADR_RX_11B_CCA_1)) = (0x00400040)
++#define DEF_RX_11B_TR_KP_KI_0() (REG32(ADR_RX_11B_TR_KP_KI_0)) = (0x00003467)
++#define DEF_RX_11B_TR_KP_KI_1() (REG32(ADR_RX_11B_TR_KP_KI_1)) = (0x00540000)
++#define DEF_RX_11B_CE_CNT_THRESHOLD() (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (0x12243615)
++#define DEF_RX_11B_CE_MU_0() (REG32(ADR_RX_11B_CE_MU_0)) = (0x00390002)
++#define DEF_RX_11B_CE_MU_1() (REG32(ADR_RX_11B_CE_MU_1)) = (0x03456777)
++#define DEF_RX_11B_EQ_MU_0() (REG32(ADR_RX_11B_EQ_MU_0)) = (0x00350046)
++#define DEF_RX_11B_EQ_MU_1() (REG32(ADR_RX_11B_EQ_MU_1)) = (0x00570057)
++#define DEF_RX_11B_EQ_CR_KP_KI() (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (0x00236700)
++#define DEF_RX_11B_LPF_RATE() (REG32(ADR_RX_11B_LPF_RATE)) = (0x000d1746)
++#define DEF_RX_11B_CIT_CNT_THRESHOLD() (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (0x04061787)
++#define DEF_RX_11B_EQ_CH_MAIN_TAP() (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (0x07800000)
++#define DEF_RX_11B_SEARCH_CNT_TH() (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (0x00c0000a)
++#define DEF_RX_11B_CCA_CONTROL() (REG32(ADR_RX_11B_CCA_CONTROL)) = (0x00000000)
++#define DEF_RX_11B_FREQUENCY_OFFSET() (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (0x00000000)
++#define DEF_RX_11B_SNR_RSSI() (REG32(ADR_RX_11B_SNR_RSSI)) = (0x00000000)
++#define DEF_RX_11B_SFD_CRC_CNT() (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (0x00000000)
++#define DEF_RX_11B_PKT_ERR_AND_PKT_ERR_CNT() (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (0x00000000)
++#define DEF_RX_11B_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
++#define DEF_RX_11B_SFD_FILED_0() (REG32(ADR_RX_11B_SFD_FILED_0)) = (0x00000000)
++#define DEF_RX_11B_SFD_FIELD_1() (REG32(ADR_RX_11B_SFD_FIELD_1)) = (0x00000000)
++#define DEF_RX_11B_PKT_STAT_EN() (REG32(ADR_RX_11B_PKT_STAT_EN)) = (0x00100000)
++#define DEF_RX_11B_SOFT_RST() (REG32(ADR_RX_11B_SOFT_RST)) = (0x00000001)
++#define DEF_TX_11GN_RAMP() (REG32(ADR_TX_11GN_RAMP)) = (0x0000233c)
++#define DEF_TX_11GN_PLCP() (REG32(ADR_TX_11GN_PLCP)) = (0x5d08908e)
++#define DEF_TX_11GN_PKT_GEN_CNT() (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (0x00000000)
++#define DEF_TX_11GN_PLCP_CRC_ERR_CNT() (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (0x00000000)
++#define DEF_RX_11GN_DES_DLY() (REG32(ADR_RX_11GN_DES_DLY)) = (0x00000044)
++#define DEF_RX_11GN_TR_0() (REG32(ADR_RX_11GN_TR_0)) = (0x00750075)
++#define DEF_RX_11GN_TR_1() (REG32(ADR_RX_11GN_TR_1)) = (0x00000075)
++#define DEF_RX_11GN_TR_2() (REG32(ADR_RX_11GN_TR_2)) = (0x10000075)
++#define DEF_RX_11GN_CCA_0() (REG32(ADR_RX_11GN_CCA_0)) = (0x38324705)
++#define DEF_RX_11GN_CCA_1() (REG32(ADR_RX_11GN_CCA_1)) = (0x30182000)
++#define DEF_RX_11GN_CCA_2() (REG32(ADR_RX_11GN_CCA_2)) = (0x20600000)
++#define DEF_RX_11GN_CCA_FFT_SCALE() (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (0x0a010100)
++#define DEF_RX_11GN_SOFT_DEMAP_0() (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (0x50505050)
++#define DEF_RX_11GN_SOFT_DEMAP_1() (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (0x50000000)
++#define DEF_RX_11GN_SOFT_DEMAP_2() (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (0x50505050)
++#define DEF_RX_11GN_SOFT_DEMAP_3() (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (0x50505050)
++#define DEF_RX_11GN_SOFT_DEMAP_4() (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (0x50000000)
++#define DEF_RX_11GN_SOFT_DEMAP_5() (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (0x00000000)
++#define DEF_RX_11GN_SYM_BOUND_0() (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (0x00001420)
++#define DEF_RX_11GN_SYM_BOUND_1() (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (0x0000200a)
++#define DEF_RX_11GN_CCA_PWR() (REG32(ADR_RX_11GN_CCA_PWR)) = (0x30000280)
++#define DEF_RX_11GN_CCA_CNT() (REG32(ADR_RX_11GN_CCA_CNT)) = (0x30023002)
++#define DEF_RX_11GN_CCA_ATCOR_RE_CHECK() (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (0x0000003a)
++#define DEF_RX_11GN_VTB_TB() (REG32(ADR_RX_11GN_VTB_TB)) = (0x40000000)
++#define DEF_RX_11GN_ERR_UPDATE() (REG32(ADR_RX_11GN_ERR_UPDATE)) = (0x009e007e)
++#define DEF_RX_11GN_SHORT_GI() (REG32(ADR_RX_11GN_SHORT_GI)) = (0x00044400)
++#define DEF_RX_11GN_CHANNEL_UPDATE() (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (0x82000000)
++#define DEF_RX_11GN_PKT_FORMAT_0() (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (0x02003030)
++#define DEF_RX_11GN_PKT_FORMAT_1() (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (0x092a092a)
++#define DEF_RX_11GN_TX_TIME() (REG32(ADR_RX_11GN_TX_TIME)) = (0x00700010)
++#define DEF_RX_11GN_STBC_TR_KP_KI() (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (0x00007575)
++#define DEF_RX_11GN_BIST_0() (REG32(ADR_RX_11GN_BIST_0)) = (0x0001fe3e)
++#define DEF_RX_11GN_BIST_1() (REG32(ADR_RX_11GN_BIST_1)) = (0x0000fe3e)
++#define DEF_RX_11GN_BIST_2() (REG32(ADR_RX_11GN_BIST_2)) = (0x00000000)
++#define DEF_RX_11GN_BIST_3() (REG32(ADR_RX_11GN_BIST_3)) = (0x00000000)
++#define DEF_RX_11GN_BIST_4() (REG32(ADR_RX_11GN_BIST_4)) = (0x00000000)
++#define DEF_RX_11GN_BIST_5() (REG32(ADR_RX_11GN_BIST_5)) = (0x00000000)
++#define DEF_RX_11GN_SPECTRUM_ANALYZER() (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (0x00000000)
++#define DEF_RX_11GN_READ_0() (REG32(ADR_RX_11GN_READ_0)) = (0x00000000)
++#define DEF_RX_11GN_FREQ_OFFSET() (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (0x00000000)
++#define DEF_RX_11GN_SIGNAL_FIELD_0() (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (0x00000000)
++#define DEF_RX_11GN_SIGNAL_FIELD_1() (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (0x00000000)
++#define DEF_RX_11GN_PKT_ERR_CNT() (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (0x00000000)
++#define DEF_RX_11GN_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
++#define DEF_RX_11GN_SERVICE_LENGTH_FIELD() (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (0x00000000)
++#define DEF_RX_11GN_RATE() (REG32(ADR_RX_11GN_RATE)) = (0x00000000)
++#define DEF_RX_11GN_STAT_EN() (REG32(ADR_RX_11GN_STAT_EN)) = (0x00100001)
++#define DEF_RX_11GN_SOFT_RST() (REG32(ADR_RX_11GN_SOFT_RST)) = (0x00000001)
++#define DEF_RF_CONTROL_0() (REG32(ADR_RF_CONTROL_0)) = (0x00000000)
++#define DEF_RF_CONTROL_1() (REG32(ADR_RF_CONTROL_1)) = (0x00008000)
++#define DEF_TX_IQ_CONTROL_0() (REG32(ADR_TX_IQ_CONTROL_0)) = (0x00200020)
++#define DEF_TX_IQ_CONTROL_1() (REG32(ADR_TX_IQ_CONTROL_1)) = (0x00028080)
++#define DEF_TX_IQ_CONTROL_2() (REG32(ADR_TX_IQ_CONTROL_2)) = (0x00000000)
++#define DEF_TX_COMPENSATION_CONTROL() (REG32(ADR_TX_COMPENSATION_CONTROL)) = (0x00000000)
++#define DEF_RX_COMPENSATION_CONTROL() (REG32(ADR_RX_COMPENSATION_CONTROL)) = (0x00000000)
++#define DEF_RX_OBSERVATION_CIRCUIT_0() (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (0x000028ff)
++#define DEF_RX_OBSERVATION_CIRCUIT_1() (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (0x00000000)
++#define DEF_RX_OBSERVATION_CIRCUIT_2() (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (0x00000000)
++#define DEF_RX_OBSERVATION_CIRCUIT_3() (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (0x00000000)
++#define DEF_RF_IQ_CONTROL_0() (REG32(ADR_RF_IQ_CONTROL_0)) = (0x00000202)
++#define DEF_RF_IQ_CONTROL_1() (REG32(ADR_RF_IQ_CONTROL_1)) = (0x00ffc200)
++#define DEF_RF_IQ_CONTROL_2() (REG32(ADR_RF_IQ_CONTROL_2)) = (0x00000000)
++#define DEF_RF_IQ_CONTROL_3() (REG32(ADR_RF_IQ_CONTROL_3)) = (0x00000000)
++#define DEF_DPD_CONTROL() (REG32(ADR_DPD_CONTROL)) = (0x00000000)
++#define DEF_DPD_GAIN_TABLE_0() (REG32(ADR_DPD_GAIN_TABLE_0)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_1() (REG32(ADR_DPD_GAIN_TABLE_1)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_2() (REG32(ADR_DPD_GAIN_TABLE_2)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_3() (REG32(ADR_DPD_GAIN_TABLE_3)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_4() (REG32(ADR_DPD_GAIN_TABLE_4)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_5() (REG32(ADR_DPD_GAIN_TABLE_5)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_6() (REG32(ADR_DPD_GAIN_TABLE_6)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_7() (REG32(ADR_DPD_GAIN_TABLE_7)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_8() (REG32(ADR_DPD_GAIN_TABLE_8)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_9() (REG32(ADR_DPD_GAIN_TABLE_9)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_A() (REG32(ADR_DPD_GAIN_TABLE_A)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_B() (REG32(ADR_DPD_GAIN_TABLE_B)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_C() (REG32(ADR_DPD_GAIN_TABLE_C)) = (0x02000200)
++#define DEF_DPD_PH_TABLE_0() (REG32(ADR_DPD_PH_TABLE_0)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_1() (REG32(ADR_DPD_PH_TABLE_1)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_2() (REG32(ADR_DPD_PH_TABLE_2)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_3() (REG32(ADR_DPD_PH_TABLE_3)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_4() (REG32(ADR_DPD_PH_TABLE_4)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_5() (REG32(ADR_DPD_PH_TABLE_5)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_6() (REG32(ADR_DPD_PH_TABLE_6)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_7() (REG32(ADR_DPD_PH_TABLE_7)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_8() (REG32(ADR_DPD_PH_TABLE_8)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_9() (REG32(ADR_DPD_PH_TABLE_9)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_A() (REG32(ADR_DPD_PH_TABLE_A)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_B() (REG32(ADR_DPD_PH_TABLE_B)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_C() (REG32(ADR_DPD_PH_TABLE_C)) = (0x00000000)
++#define DEF_DPD_GAIN_ESTIMATION_0() (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (0x00000000)
++#define DEF_DPD_GAIN_ESTIMATION_1() (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (0x00000100)
++#define DEF_DPD_GAIN_ESTIMATION_2() (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (0x00000000)
++#define DEF_TX_GAIN_FACTOR() (REG32(ADR_TX_GAIN_FACTOR)) = (0x80808080)
++#define DEF_HARD_WIRE_PIN_REGISTER() (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
++#define DEF_MANUAL_ENABLE_REGISTER() (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (0x00000fc0)
++#define DEF_LDO_REGISTER() (REG32(ADR_LDO_REGISTER)) = (0x000db71b)
++#define DEF_ABB_REGISTER_1() (REG32(ADR_ABB_REGISTER_1)) = (0x151558dd)
++#define DEF_ABB_REGISTER_2() (REG32(ADR_ABB_REGISTER_2)) = (0x01011a88)
++#define DEF_TX_FE_REGISTER() (REG32(ADR_TX_FE_REGISTER)) = (0x3d3e84fe)
++#define DEF_RX_FE_REGISTER_1() (REG32(ADR_RX_FE_REGISTER_1)) = (0x03457579)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
++#define DEF_RX_TX_FSM_REGISTER() (REG32(ADR_RX_TX_FSM_REGISTER)) = (0x00030ca8)
++#define DEF_RX_ADC_REGISTER() (REG32(ADR_RX_ADC_REGISTER)) = (0x20ea0224)
++#define DEF_TX_DAC_REGISTER() (REG32(ADR_TX_DAC_REGISTER)) = (0x44000655)
++#define DEF_SX_ENABLE_REGISTER() (REG32(ADR_SX_ENABLE_REGISTER)) = (0x0003e07c)
++#define DEF_SYN_REGISTER_1() (REG32(ADR_SYN_REGISTER_1)) = (0xaa800000)
++#define DEF_SYN_REGISTER_2() (REG32(ADR_SYN_REGISTER_2)) = (0x00550800)
++#define DEF_SYN_PFD_CHP() (REG32(ADR_SYN_PFD_CHP)) = (0x07c0894a)
++#define DEF_SYN_VCO_LOBF() (REG32(ADR_SYN_VCO_LOBF)) = (0xfcccca27)
++#define DEF_SYN_DIV_SDM_XOSC() (REG32(ADR_SYN_DIV_SDM_XOSC)) = (0x07700830)
++#define DEF_SYN_KVCO_XO_FINE_TUNE_CBANK() (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (0x00440000)
++#define DEF_SYN_LCK_VT() (REG32(ADR_SYN_LCK_VT)) = (0x00007ff4)
++#define DEF_DPLL_VCO_REGISTER() (REG32(ADR_DPLL_VCO_REGISTER)) = (0x0000000e)
++#define DEF_DPLL_CP_PFD_REGISTER() (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (0x00088008)
++#define DEF_DPLL_DIVIDER_REGISTER() (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (0x00406000)
++#define DEF_DCOC_IDAC_REGISTER1() (REG32(ADR_DCOC_IDAC_REGISTER1)) = (0x08820820)
++#define DEF_DCOC_IDAC_REGISTER2() (REG32(ADR_DCOC_IDAC_REGISTER2)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER3() (REG32(ADR_DCOC_IDAC_REGISTER3)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER4() (REG32(ADR_DCOC_IDAC_REGISTER4)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER5() (REG32(ADR_DCOC_IDAC_REGISTER5)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER6() (REG32(ADR_DCOC_IDAC_REGISTER6)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER7() (REG32(ADR_DCOC_IDAC_REGISTER7)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER8() (REG32(ADR_DCOC_IDAC_REGISTER8)) = (0x00820820)
++#define DEF_RCAL_REGISTER() (REG32(ADR_RCAL_REGISTER)) = (0x00004080)
++#define DEF_SX_LCK_BIN_REGISTERS_I() (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (0x20080080)
++#define DEF_TRX_DUMMY_REGISTER() (REG32(ADR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_SX_DUMMY_REGISTER() (REG32(ADR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_DPLL_FB_DIVIDER_REGISTERS_II() (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (0x00ec2ec5)
++#define DEF_SX_LCK_BIN_REGISTERS_II() (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (0x00000f13)
++#define DEF_RC_OSC_32K_CAL_REGISTERS() (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (0x00098900)
++#define DEF_RF_D_DIGITAL_DEBUG_PORT_REGISTER() (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (0x00000000)
++#define DEF_MMU_CTRL() (REG32(ADR_MMU_CTRL)) = (0x00002042)
++#define DEF_HS_CTRL() (REG32(ADR_HS_CTRL)) = (0x00000000)
++#define DEF_CPU_POR0_7() (REG32(ADR_CPU_POR0_7)) = (0x00000000)
++#define DEF_CPU_POR8_F() (REG32(ADR_CPU_POR8_F)) = (0x00000000)
++#define DEF_REG_LEN_CTRL() (REG32(ADR_REG_LEN_CTRL)) = (0x00000f0f)
++#define DEF_DMN_READ_BYPASS() (REG32(ADR_DMN_READ_BYPASS)) = (0x0000ffff)
++#define DEF_ALC_RLS_ABORT() (REG32(ADR_ALC_RLS_ABORT)) = (0x00000000)
++#define DEF_DEBUG_CTL() (REG32(ADR_DEBUG_CTL)) = (0x00000000)
++#define DEF_DEBUG_OUT() (REG32(ADR_DEBUG_OUT)) = (0x00000000)
++#define DEF_MMU_STATUS() (REG32(ADR_MMU_STATUS)) = (0x00000000)
++#define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00000000)
++#define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000)
++#define DEF_DMN_MCU_STATUS() (REG32(ADR_DMN_MCU_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_0_STATUS() (REG32(ADR_MB_IDTBL_0_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_1_STATUS() (REG32(ADR_MB_IDTBL_1_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_2_STATUS() (REG32(ADR_MB_IDTBL_2_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_3_STATUS() (REG32(ADR_MB_IDTBL_3_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_0_STATUS() (REG32(ADR_PKT_IDTBL_0_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_1_STATUS() (REG32(ADR_PKT_IDTBL_1_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_2_STATUS() (REG32(ADR_PKT_IDTBL_2_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_3_STATUS() (REG32(ADR_PKT_IDTBL_3_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_0_STATUS() (REG32(ADR_DMN_IDTBL_0_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_1_STATUS() (REG32(ADR_DMN_IDTBL_1_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_2_STATUS() (REG32(ADR_DMN_IDTBL_2_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_3_STATUS() (REG32(ADR_DMN_IDTBL_3_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_0_STATUS() (REG32(ADR_MB_NEQID_0_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_1_STATUS() (REG32(ADR_MB_NEQID_1_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_2_STATUS() (REG32(ADR_MB_NEQID_2_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_3_STATUS() (REG32(ADR_MB_NEQID_3_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_0_STATUS() (REG32(ADR_PKT_NEQID_0_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_1_STATUS() (REG32(ADR_PKT_NEQID_1_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_2_STATUS() (REG32(ADR_PKT_NEQID_2_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_3_STATUS() (REG32(ADR_PKT_NEQID_3_STATUS)) = (0x00000000)
++#define DEF_ALC_NOCHG_ID_STATUS() (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_0() (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_1() (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_2() (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_3() (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_4() (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_5() (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_6() (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_7() (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (0x00000000)
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
+new file mode 100644
+index 000000000000..e15a481ba300
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
+@@ -0,0 +1,176 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "ssv6200_reg.h"
++#define BANK_COUNT 49
++static const u32 BASE_BANK_SSV6200[] = {
++	SYS_REG_BASE,
++	WBOOT_REG_BASE,
++	TU0_US_REG_BASE,
++	TU1_US_REG_BASE,
++	TU2_US_REG_BASE,
++	TU3_US_REG_BASE,
++	TM0_MS_REG_BASE,
++	TM1_MS_REG_BASE,
++	TM2_MS_REG_BASE,
++	TM3_MS_REG_BASE,
++	MCU_WDT_REG_BASE,
++	SYS_WDT_REG_BASE,
++	GPIO_REG_BASE,
++	SD_REG_BASE,
++	SPI_REG_BASE,
++	CSR_I2C_MST_BASE,
++	UART_REG_BASE,
++	DAT_UART_REG_BASE,
++	INT_REG_BASE,
++	DBG_SPI_REG_BASE,
++	FLASH_SPI_REG_BASE,
++	DMA_REG_BASE,
++	CSR_PMU_BASE,
++	CSR_RTC_BASE,
++	RTC_RAM_BASE,
++	D2_DMA_REG_BASE,
++	HCI_REG_BASE,
++	CO_REG_BASE,
++	EFS_REG_BASE,
++	SMS4_REG_BASE,
++	MRX_REG_BASE,
++	AMPDU_REG_BASE,
++	MT_REG_CSR_BASE,
++	TXQ0_MT_Q_REG_CSR_BASE,
++	TXQ1_MT_Q_REG_CSR_BASE,
++	TXQ2_MT_Q_REG_CSR_BASE,
++	TXQ3_MT_Q_REG_CSR_BASE,
++	TXQ4_MT_Q_REG_CSR_BASE,
++	HIF_INFO_BASE,
++	PHY_RATE_INFO_BASE,
++	MAC_GLB_SET_BASE,
++	BTCX_REG_BASE,
++	MIB_REG_BASE,
++	CBR_A_REG_BASE,
++	MB_REG_BASE,
++	ID_MNG_REG_BASE,
++	CSR_PHY_BASE,
++	CSR_RF_BASE,
++	MMU_REG_BASE,
++	0x00000000
++};
++
++static const char *STR_BANK_SSV6200[] = {
++	"SYS_REG",
++	"WBOOT_REG",
++	"TU0_US_REG",
++	"TU1_US_REG",
++	"TU2_US_REG",
++	"TU3_US_REG",
++	"TM0_MS_REG",
++	"TM1_MS_REG",
++	"TM2_MS_REG",
++	"TM3_MS_REG",
++	"MCU_WDT_REG",
++	"SYS_WDT_REG",
++	"GPIO_REG",
++	"SD_REG",
++	"SPI_REG",
++	"CSR_I2C_MST",
++	"UART_REG",
++	"DAT_UART_REG",
++	"INT_REG",
++	"DBG_SPI_REG",
++	"FLASH_SPI_REG",
++	"DMA_REG",
++	"CSR_PMU",
++	"CSR_RTC",
++	"RTC_RAM",
++	"D2_DMA_REG",
++	"HCI_REG",
++	"CO_REG",
++	"EFS_REG",
++	"SMS4_REG",
++	"MRX_REG",
++	"AMPDU_REG",
++	"MT_REG_CSR",
++	"TXQ0_MT_Q_REG_CSR",
++	"TXQ1_MT_Q_REG_CSR",
++	"TXQ2_MT_Q_REG_CSR",
++	"TXQ3_MT_Q_REG_CSR",
++	"TXQ4_MT_Q_REG_CSR",
++	"HIF_INFO",
++	"PHY_RATE_INFO",
++	"MAC_GLB_SET",
++	"BTCX_REG",
++	"MIB_REG",
++	"CBR_A_REG",
++	"MB_REG",
++	"ID_MNG_REG",
++	"CSR_PHY",
++	"CSR_RF",
++	"MMU_REG",
++	""
++};
++
++static const u32 SIZE_BANK_SSV6200[] = {
++	SYS_REG_BANK_SIZE,
++	WBOOT_REG_BANK_SIZE,
++	TU0_US_REG_BANK_SIZE,
++	TU1_US_REG_BANK_SIZE,
++	TU2_US_REG_BANK_SIZE,
++	TU3_US_REG_BANK_SIZE,
++	TM0_MS_REG_BANK_SIZE,
++	TM1_MS_REG_BANK_SIZE,
++	TM2_MS_REG_BANK_SIZE,
++	TM3_MS_REG_BANK_SIZE,
++	MCU_WDT_REG_BANK_SIZE,
++	SYS_WDT_REG_BANK_SIZE,
++	GPIO_REG_BANK_SIZE,
++	SD_REG_BANK_SIZE,
++	SPI_REG_BANK_SIZE,
++	CSR_I2C_MST_BANK_SIZE,
++	UART_REG_BANK_SIZE,
++	DAT_UART_REG_BANK_SIZE,
++	INT_REG_BANK_SIZE,
++	DBG_SPI_REG_BANK_SIZE,
++	FLASH_SPI_REG_BANK_SIZE,
++	DMA_REG_BANK_SIZE,
++	CSR_PMU_BANK_SIZE,
++	CSR_RTC_BANK_SIZE,
++	RTC_RAM_BANK_SIZE,
++	D2_DMA_REG_BANK_SIZE,
++	HCI_REG_BANK_SIZE,
++	CO_REG_BANK_SIZE,
++	EFS_REG_BANK_SIZE,
++	SMS4_REG_BANK_SIZE,
++	MRX_REG_BANK_SIZE,
++	AMPDU_REG_BANK_SIZE,
++	MT_REG_CSR_BANK_SIZE,
++	TXQ0_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ1_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ2_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ3_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ4_MT_Q_REG_CSR_BANK_SIZE,
++	HIF_INFO_BANK_SIZE,
++	PHY_RATE_INFO_BANK_SIZE,
++	MAC_GLB_SET_BANK_SIZE,
++	BTCX_REG_BANK_SIZE,
++	MIB_REG_BANK_SIZE,
++	CBR_A_REG_BANK_SIZE,
++	MB_REG_BANK_SIZE,
++	ID_MNG_REG_BANK_SIZE,
++	CSR_PHY_BANK_SIZE,
++	CSR_RF_BANK_SIZE,
++	MMU_REG_BANK_SIZE,
++	0x00000000
++};
+diff --git a/drivers/net/wireless/ssv6051/include/ssv_cfg.h b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
+new file mode 100644
+index 000000000000..79b75619936e
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
+@@ -0,0 +1,60 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_CFG_H_
++#define _SSV_CFG_H_
++#define SSV6200_HW_CAP_HT 0x00000001
++#define SSV6200_HW_CAP_GF 0x00000002
++#define SSV6200_HW_CAP_2GHZ 0x00000004
++#define SSV6200_HW_CAP_5GHZ 0x00000008
++#define SSV6200_HW_CAP_SECURITY 0x00000010
++#define SSV6200_HT_CAP_SGI_20 0x00000020
++#define SSV6200_HT_CAP_SGI_40 0x00000040
++#define SSV6200_HW_CAP_AP 0x00000080
++#define SSV6200_HW_CAP_P2P 0x00000100
++#define SSV6200_HW_CAP_AMPDU_RX 0x00000200
++#define SSV6200_HW_CAP_AMPDU_TX 0x00000400
++#define SSV6200_HW_CAP_TDLS 0x00000800
++#define EXTERNEL_CONFIG_SUPPORT 64
++struct ssv6xxx_cfg {
++	u32 hw_caps;
++	u32 def_chan;
++	u32 crystal_type;
++	u32 volt_regulator;
++	u32 force_chip_identity;
++	u8 maddr[2][6];
++	u32 n_maddr;
++	u32 use_wpa2_only;
++	u32 ignore_reset_in_ap;
++	u32 r_calbration_result;
++	u32 sar_result;
++	u32 crystal_frequency_offset;
++	u32 tx_power_index_1;
++	u32 tx_power_index_2;
++	u32 chip_identity;
++	u32 wifi_tx_gain_level_gn;
++	u32 wifi_tx_gain_level_b;
++	u32 rssi_ctl;
++	u32 sr_bhvr;
++	u32 configuration[EXTERNEL_CONFIG_SUPPORT + 1][2];
++	u8 firmware_path[128];
++	u8 flash_bin_path[128];
++	u8 mac_address_path[128];
++	u8 mac_output_path[128];
++	u32 ignore_efuse_mac;
++	u32 mac_address_mode;
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
+new file mode 100644
+index 000000000000..7fabbe308f9d
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
+@@ -0,0 +1,25 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_FIRMWARE_VERSION_H_
++#define _SSV_FIRMWARE_VERSION_H_
++static u32 ssv_firmware_version = 16380;
++#define SSV_FIRMWARE_URl "http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/6051.Q0.1009.21.000000/ssv6xxx/smac/firmware"
++#define FIRMWARE_COMPILERHOST "ssv-ThinkPad-X230"
++#define FIRMWARE_COMPILERDATE "11-06-2017-09:17:18"
++#define FIRMWARE_COMPILEROS "linux"
++#define FIRMWARE_COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv_version.h b/drivers/net/wireless/ssv6051/include/ssv_version.h
+new file mode 100644
+index 000000000000..99be5354f783
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv_version.h
+@@ -0,0 +1,12 @@
++#ifndef _SSV_VERSION_H_
++#define _SSV_VERSION_H_
++
++static u32 ssv_root_version = 16529;
++
++#define SSV_ROOT_URl "http://192.168.15.30/svn/software/project/release/android/box/rk3x28/6051.Q0.1009.21.400401/ssv6xxx"
++#define COMPILERHOST "icomm-buildserver-T320"
++#define COMPILERDATE "12-08-2017-10:34:54"
++#define COMPILEROS "linux"
++#define COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
++
++#endif
+diff --git a/drivers/net/wireless/ssv6051/platform-config.mak b/drivers/net/wireless/ssv6051/platform-config.mak
+new file mode 100644
+index 000000000000..b1b6f0510d28
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/platform-config.mak
+@@ -0,0 +1,97 @@
++
++ccflags-y += -DCONFIG_SSV6200_CORE
++
++###########################################################################
++# Compiler options                                                        #
++###########################################################################
++
++# Enable -g to help debug. Deassembly from .o to .S would help to track to 
++# the problomatic line from call stack dump.
++#ccflags-y += -g
++ccflags += -Os
++
++############################################################
++# If you change the settings, please change the file synchronization
++# smac\firmware\include\config.h & compiler firmware
++############################################################
++#ccflags-y += -DCONFIG_SSV_CABRIO_A
++ccflags-y += -DCONFIG_SSV_CABRIO_E
++
++#CONFIG_SSV_SUPPORT_BTCX=y
++
++#ccflags-y += -DDEBUG
++ccflags-y += -DCONFIG_SSV6200_CLI_ENABLE
++
++#PADPD
++#ccflags-y += -DCONFIG_SSV_DPD
++
++#ccflags-y += -DCONFIG_SSV_CABRIO_MB_DEBUG
++#ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS
++
++#SDIO
++ccflags-y += -DCONFIG_SSV_TX_LOWTHRESHOLD
++
++ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
++ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
++ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
++#ccflags-y += -DMULTI_THREAD_ENCRYPT
++#ccflags-y += -DKTHREAD_BIND
++#ccflags-y += -DROCKCHIP_WIFI_AUTO_SUPPORT
++ccflags-y += -DCONFIG_SSV_RSSI
++ccflags-y += -DCONFIG_SSV_VENDOR_EXT_SUPPORT
++
++############################################################
++# Rate control update for MPDU.
++############################################################
++ccflags-y += -DRATE_CONTROL_REALTIME_UPDATA
++
++#workaround
++#ccflags-y += -DCONFIG_SSV_CABRIO_EXT_PA
++
++############################################################
++# NOTE:
++#    Only one of the following flags could be turned on.
++# It also turned off the following flags. In this case, 
++# pure software security or pure hardware security is used.
++#
++############################################################
++#ccflags-y += -DCONFIG_SSV_SW_ENCRYPT_HW_DECRYPT
++#ccflags-y += -DCONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
++
++# FOR WFA
++#ccflags-y += -DWIFI_CERTIFIED
++
++#ccflags-y += -DCONFIG_SSV_SDIO_EXT_INT
++
++#######################################################
++ccflags-y += -DCONFIG_SSV6200_HAS_RX_WORKQUEUE
++#ccflags-y += -DUSE_THREAD_RX
++ccflags-y += -DUSE_THREAD_TX
++ccflags-y += -DENABLE_AGGREGATE_IN_TIME
++ccflags-y += -DENABLE_INCREMENTAL_AGGREGATION
++
++# Generic decision table applicable to both AP and STA modes.
++ccflags-y += -DUSE_GENERIC_DECI_TBL
++
++#ccflags-y += -DCONFIG_SSV_WAPI
++
++ccflags-y += -DFW_WSID_WATCH_LIST
++#ccflags-y += -DUSE_BATCH_RX
++#ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT
++
++ccflags-y += -DSSV6200_ECO
++#ccflags-y += -DENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
++ccflags-y += -DHAS_CRYPTO_LOCK
++ccflags-y += -DENABLE_TX_Q_FLOW_CONTROL
++
++#ccflags-y += -DCONFIG_DEBUG_SKB_TIMESTAMP
++
++
++#enable p2p client to parse GO broadcast noa
++#ccflags-y += -DCONFIG_P2P_NOA
++
++#enable rx management frame check
++#ccflags-y += -DCONFIG_RX_MGMT_CHECK
++
++#force SW Broadcast/Multicast decryption
++ccflags-y += -DUSE_MAC80211_DECRYPT_BROADCAST
+\ No newline at end of file
+diff --git a/drivers/net/wireless/ssv6051/rules.mak b/drivers/net/wireless/ssv6051/rules.mak
+new file mode 100644
+index 000000000000..b3262852249c
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/rules.mak
+@@ -0,0 +1,19 @@
++
++
++$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
++obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
++
++
++.PHONY: all clean install
++
++all:
++	@$(MAKE) -C /lib/modules/$(KVERSION)/build \
++		SUBDIRS=$(KBUILD_DIR) CONFIG_DEBUG_SECTION_MISMATCH=y \
++		modules
++
++clean:
++	@$(MAKE) -C /lib/modules/$(KVERSION)/build SUBDIRS=$(KBUILD_DIR) clean
++
++install:
++	@$(MAKE) INSTALL_MOD_DIR=$(DRVPATH) -C /lib/modules/$(KVERSION)/build \
++	        M=$(KBUILD_DIR) modules_install
+diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.c b/drivers/net/wireless/ssv6051/smac/ampdu.c
+new file mode 100644
+index 000000000000..846830f3d209
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ampdu.c
+@@ -0,0 +1,2111 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ap.h"
++#include "sec.h"
++#include "ssv_rc_common.h"
++#include "ssv_ht_rc.h"
++extern struct ieee80211_ops ssv6200_ops;
++
++// Hack: redefine MAX_AMPDU_BUF because buf_size here is a 8-bit char
++// and mainline kernel value is 0x100, which overflows
++#ifdef IEEE80211_MAX_AMPDU_BUF
++#undef IEEE80211_MAX_AMPDU_BUF
++#endif
++#define IEEE80211_MAX_AMPDU_BUF 0x40
++
++#define BA_WAIT_TIMEOUT (800)
++#define AMPDU_BA_FRAME_LEN (68)
++#define ampdu_skb_hdr(skb) ((struct ieee80211_hdr*)((u8*)((skb)->data)+AMPDU_DELIMITER_LEN))
++#define ampdu_skb_ssn(skb) ((ampdu_skb_hdr(skb)->seq_ctrl)>>SSV_SEQ_NUM_SHIFT)
++#define ampdu_hdr_ssn(hdr) ((hdr)->seq_ctrl>>SSV_SEQ_NUM_SHIFT)
++#undef prn_aggr_dbg
++#define prn_aggr_dbg(fmt,...)
++static void void_func(const char *fmt, ...)
++{
++}
++
++#define prn_aggr_err(fmt,...) \
++    do { \
++        void_func(KERN_ERR fmt, ##__VA_ARGS__);\
++    } while (0)
++#define get_tid_aggr_len(agg_len,tid_data) \
++    ({ \
++        u32 agg_max_num = (tid_data)->agg_num_max; \
++        u32 to_agg_len = (agg_len); \
++        (agg_len >= agg_max_num) ? agg_max_num : to_agg_len; \
++    })
++#define INDEX_PKT_BY_SSN(tid,ssn) \
++    ((tid)->aggr_pkts[(ssn) % SSV_AMPDU_BA_WINDOW_SIZE])
++#define NEXT_PKT_SN(sn) \
++    ({ (sn + 1) % SSV_AMPDU_MAX_SSN; })
++#define INC_PKT_SN(sn) \
++    ({ \
++        sn = NEXT_PKT_SN(sn); \
++        sn; \
++    })
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++static ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
++				 char *mib_str, ssize_t length);
++static int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb);
++#endif
++static struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
++					struct AMPDU_TID_st *cur_AMPDU_TID,
++					struct sk_buff_head *retry_queue,
++					u32 max_aggr_len);
++static int _dump_BA_notification(char *buf,
++				 struct ampdu_ba_notify_data *ba_notification);
++static struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
++					struct AMPDU_TID_st *ampdu_tid,
++					u32 len);
++static bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid,
++				struct sk_buff *ampdu_skb, bool retry);
++static void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu);
++static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb);
++static u32 _flush_early_ampdu_q(struct ssv_softc *sc,
++				struct AMPDU_TID_st *ampdu_tid);
++static bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb);
++static void _aggr_ampdu_tx_q(struct ieee80211_hw *hw,
++			     struct AMPDU_TID_st *ampdu_tid);
++static void _queue_early_ampdu(struct ssv_softc *sc,
++			       struct AMPDU_TID_st *ampdu_tid,
++			       struct sk_buff *ampdu_skb);
++static int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb);
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage)
++{
++	unsigned int timeout;
++	SKB_info *mpdu_skb_info;
++	u16 ssn = 0;
++	struct sk_buff *mpdu = NULL;
++	struct ampdu_hdr_st *ampdu_hdr = NULL;
++	ktime_t current_ktime;
++	ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++	ssn = ampdu_hdr->ssn[0];
++	mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
++	if (mpdu == NULL)
++		return 0;
++	mpdu_skb_info = (SKB_info *) (mpdu->head);
++	current_ktime = ktime_get();
++	timeout =
++	    (unsigned int)
++	    ktime_to_ms(ktime_sub(current_ktime, mpdu_skb_info->timestamp));
++	if (timeout > SKB_DURATION_TIMEOUT_MS) {
++		if (stage == SKB_DURATION_STAGE_TO_SDIO)
++			pr_debug("*a_to_sdio: %ums\n", timeout);
++		else if (stage == SKB_DURATION_STAGE_TX_ENQ)
++			pr_debug("*a_to_txenqueue: %ums\n", timeout);
++		else
++			pr_debug("*a_in_hwq: %ums\n", timeout);
++	}
++	return timeout;
++}
++#endif
++static u8 _cal_ampdu_delm_half_crc(u8 value)
++{
++	u32 c32 = value, v32 = value;
++	c32 ^= (v32 >> 1) | (v32 << 7);
++	c32 ^= (v32 >> 2);
++	if (v32 & 2)
++		c32 ^= (0xC0);
++	c32 ^= ((v32 << 4) & 0x30);
++	return (u8) c32;
++}
++
++static u8 _cal_ampdu_delm_crc(u8 * pointer)
++{
++	u8 crc = 0xCF;
++	crc ^= _cal_ampdu_delm_half_crc(*pointer++);
++	crc =
++	    _cal_ampdu_delm_half_crc(crc) ^ _cal_ampdu_delm_half_crc(*pointer);
++	return ~crc;
++}
++
++static bool ssv6200_ampdu_add_delimiter_and_crc32(struct sk_buff *mpdu)
++{
++	p_AMPDU_DELIMITER delimiter_p;
++	struct ieee80211_hdr *mpdu_hdr;
++	int ret;
++	u32 orig_mpdu_len = mpdu->len;
++	u32 pad = (4 - (orig_mpdu_len % 4)) % 4;
++	mpdu_hdr = (struct ieee80211_hdr *)(mpdu->data);
++	mpdu_hdr->duration_id = AMPDU_TX_NAV_MCS_567;
++	ret = skb_padto(mpdu, mpdu->len + (AMPDU_FCS_LEN + pad));
++	if (ret) {
++		pr_err("Failed to extand skb for aggregation\n");
++		return false;
++	}
++	skb_put(mpdu, AMPDU_FCS_LEN + pad);
++	skb_push(mpdu, AMPDU_DELIMITER_LEN);
++	delimiter_p = (p_AMPDU_DELIMITER) mpdu->data;
++	delimiter_p->reserved = 0;
++	delimiter_p->length = orig_mpdu_len + AMPDU_FCS_LEN;
++	delimiter_p->signature = AMPDU_SIGNATURE;
++	delimiter_p->crc = _cal_ampdu_delm_crc((u8 *) (delimiter_p));
++	return true;
++}
++
++static void ssv6200_ampdu_hw_init(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	u32 temp32;
++	SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
++	temp32 |= (0x1 << MTX_AMPDU_CRC_AUTO_SFT);
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_MISC_EN, temp32);
++	SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
++}
++
++bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid, struct sk_buff *ampdu,
++			 bool retry)
++{
++	struct sk_buff **pp_aggr_pkt;
++	struct sk_buff *p_aggr_pkt;
++	unsigned long flags;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++	struct sk_buff *mpdu;
++	u32 first_ssn = SSV_ILLEGAL_SN;
++	u32 old_aggr_pkt_num;
++	u32 old_baw_head;
++	u32 sync_num = skb_queue_len(&ampdu_hdr->mpdu_q);
++	bool ret = true;
++	spin_lock_irqsave(&ampdu_tid->pkt_array_lock, flags);
++	old_baw_head = ampdu_tid->ssv_baw_head;
++	old_aggr_pkt_num = ampdu_tid->aggr_pkt_num;
++	ampdu_tid->mib.ampdu_mib_ampdu_counter += 1;
++	ampdu_tid->mib.ampdu_mib_dist[sync_num] += 1;
++	do {
++		if (!retry) {
++			ampdu_tid->mib.ampdu_mib_mpdu_counter += sync_num;
++			mpdu = skb_peek_tail(&ampdu_hdr->mpdu_q);
++			if (mpdu == NULL) {
++				ret = false;
++				break;
++			} else {
++				u32 ssn = ampdu_skb_ssn(mpdu);
++				p_aggr_pkt = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++				if (p_aggr_pkt != NULL) {
++					char msg[256];
++					u32 sn = ampdu_skb_ssn(mpdu);
++					skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
++						sn = ampdu_skb_ssn(mpdu);
++						sprintf(msg, " %d", sn);
++					}
++					prn_aggr_err("ES %d -> %d (%s)\n",
++						     ssn,
++						     ampdu_skb_ssn(p_aggr_pkt),
++						     msg);
++					ret = false;
++					break;
++				}
++			}
++		} else
++			ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
++		skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
++			u32 ssn = ampdu_skb_ssn(mpdu);
++			SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
++			if (first_ssn == SSV_ILLEGAL_SN)
++				first_ssn = ssn;
++			pp_aggr_pkt = &INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++			p_aggr_pkt = *pp_aggr_pkt;
++			*pp_aggr_pkt = mpdu;
++			if (!retry)
++				ampdu_tid->aggr_pkt_num++;
++			mpdu_skb_info->ampdu_tx_status = AMPDU_ST_AGGREGATED;
++			if (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN) {
++				ampdu_tid->ssv_baw_head = ssn;
++			}
++			if ((p_aggr_pkt != NULL) && (mpdu != p_aggr_pkt))
++				prn_aggr_err("%d -> %d (H%d, N%d, Q%d)\n",
++					     ssn, ampdu_skb_ssn(p_aggr_pkt),
++					     old_baw_head, old_aggr_pkt_num,
++					     sync_num);
++		}
++	} while (0);
++	spin_unlock_irqrestore(&ampdu_tid->pkt_array_lock, flags);
++	{
++		u32 page_count = (ampdu->len + SSV6200_ALLOC_RSVD);
++		if (page_count & HW_MMU_PAGE_MASK)
++			page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
++		else
++			page_count = page_count >> HW_MMU_PAGE_SHIFT;
++		if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
++			pr_err("AMPDU requires pages %d(%d-%d-%d) exceeds resource limit %d.\n",
++			       page_count, ampdu->len, ampdu_hdr->max_size,
++			       ampdu_hdr->size,
++			       (SSV6200_PAGE_TX_THRESHOLD / 2));
++	}
++	return ret;
++}
++
++struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
++				 struct AMPDU_TID_st *ampdu_tid,
++				 struct sk_buff_head *retry_queue,
++				 u32 max_aggr_len)
++{
++	struct sk_buff *retry_mpdu;
++	struct sk_buff *new_ampdu_skb;
++	u32 num_retry_mpdu;
++	u32 temp_i;
++	u32 total_skb_size;
++	unsigned long flags;
++	u16 head_ssn = ampdu_tid->ssv_baw_head;
++	struct ampdu_hdr_st *ampdu_hdr;
++	BUG_ON(head_ssn == SSV_ILLEGAL_SN);
++	num_retry_mpdu = skb_queue_len(retry_queue);
++	if (num_retry_mpdu == 0)
++		return NULL;
++	new_ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, max_aggr_len);
++	if (new_ampdu_skb == 0)
++		return NULL;
++	ampdu_hdr = (struct ampdu_hdr_st *)new_ampdu_skb->head;
++	total_skb_size = 0;
++	spin_lock_irqsave(&retry_queue->lock, flags);
++	for (temp_i = 0; temp_i < ampdu_tid->agg_num_max; temp_i++) {
++		struct ieee80211_hdr *mpdu_hdr;
++		u16 mpdu_sn;
++		u16 diff;
++		u32 new_total_skb_size;
++		retry_mpdu = skb_peek(retry_queue);
++		if (retry_mpdu == NULL) {
++			break;
++		}
++		mpdu_hdr = ampdu_skb_hdr(retry_mpdu);
++		mpdu_sn = ampdu_hdr_ssn(mpdu_hdr);
++		diff = SSV_AMPDU_SN_a_minus_b(head_ssn, mpdu_sn);
++		if ((head_ssn != SSV_ILLEGAL_SN)
++		    && (diff > 0)
++		    && (diff <= ampdu_tid->ssv_baw_size)) {
++			struct SKB_info_st *skb_info;
++			prn_aggr_err("Z. release skb (s %d, h %d, d %d)\n",
++				     mpdu_sn, head_ssn, diff);
++			skb_info = (struct SKB_info_st *)(retry_mpdu->head);
++			skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
++			ampdu_tid->mib.ampdu_mib_discard_counter++;
++			continue;
++		}
++		new_total_skb_size = total_skb_size + retry_mpdu->len;
++		if (new_total_skb_size > ampdu_hdr->max_size)
++			break;
++		total_skb_size = new_total_skb_size;
++		retry_mpdu = __skb_dequeue(retry_queue);
++		_put_mpdu_to_ampdu(new_ampdu_skb, retry_mpdu);
++		ampdu_tid->mib.ampdu_mib_retry_counter++;
++	}
++	ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
++	ampdu_tid->mib.ampdu_mib_dist[temp_i] += 1;
++	spin_unlock_irqrestore(&retry_queue->lock, flags);
++	if (ampdu_hdr->mpdu_num == 0) {
++		dev_kfree_skb_any(new_ampdu_skb);
++		return NULL;
++	}
++	return new_ampdu_skb;
++}
++
++static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
++{
++	struct ssv6200_tx_desc *tx_desc;
++	ssv6xxx_add_txinfo(sc, ampdu_skb);
++	tx_desc = (struct ssv6200_tx_desc *)ampdu_skb->data;
++	tx_desc->tx_report = 1;
++}
++
++void _send_hci_skb(struct ssv_softc *sc, struct sk_buff *skb, u32 tx_flag)
++{
++	struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	int ret = AMPDU_HCI_SEND(sc->sh, skb, tx_desc->txq_idx, tx_flag);
++	if ((tx_desc->txq_idx > 3) && (ret <= 0)) {
++		prn_aggr_err("BUG!! %d %d\n", tx_desc->txq_idx, ret);
++	}
++}
++
++static void ssv6200_ampdu_add_txinfo_and_send_HCI(struct ssv_softc *sc,
++						  struct sk_buff *ampdu_skb,
++						  u32 tx_flag)
++{
++	_add_ampdu_txinfo(sc, ampdu_skb);
++	_send_hci_skb(sc, ampdu_skb, tx_flag);
++}
++
++static void ssv6200_ampdu_send_retry(struct ieee80211_hw *hw,
++				     AMPDU_TID * cur_ampdu_tid,
++				     struct sk_buff_head
++				     *ampdu_skb_retry_queue_p,
++				     bool send_aggr_tx)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct sk_buff *ampdu_retry_skb;
++	u32 ampdu_skb_retry_queue_len;
++	u32 max_agg_len;
++	u16 lowest_rate;
++	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
++	ampdu_skb_retry_queue_len = skb_queue_len(ampdu_skb_retry_queue_p);
++	if (ampdu_skb_retry_queue_len == 0)
++		return;
++	ampdu_retry_skb = skb_peek(ampdu_skb_retry_queue_p);
++	lowest_rate = ssv62xx_ht_rate_update(ampdu_retry_skb, sc, rates);
++	max_agg_len = ampdu_max_transmit_length[lowest_rate];
++	if (max_agg_len > 0) {
++		u32 cur_ampdu_max_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
++		if (max_agg_len >= cur_ampdu_max_size)
++			max_agg_len = cur_ampdu_max_size;
++		while (ampdu_skb_retry_queue_len > 0) {
++			struct sk_buff *retry_mpdu =
++			    skb_peek(ampdu_skb_retry_queue_p);
++			SKB_info *mpdu_skb_info =
++			    (SKB_info *) (retry_mpdu->head);
++			mpdu_skb_info->lowest_rate = lowest_rate;
++			memcpy(mpdu_skb_info->rates, rates, sizeof(rates));
++			ampdu_retry_skb =
++			    _aggr_retry_mpdu(sc, cur_ampdu_tid,
++					     ampdu_skb_retry_queue_p,
++					     max_agg_len);
++			if (ampdu_retry_skb != NULL) {
++				_sync_ampdu_pkt_arr(cur_ampdu_tid,
++						    ampdu_retry_skb, true);
++				ssv6200_ampdu_add_txinfo_and_send_HCI(sc,
++								      ampdu_retry_skb,
++								      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
++			} else {
++				prn_aggr_err("AMPDU retry failed.\n");
++				return;
++			}
++			ampdu_skb_retry_queue_len =
++			    skb_queue_len(ampdu_skb_retry_queue_p);
++		}
++	} else {
++		struct ieee80211_tx_rate rates[IEEE80211_TX_MAX_RATES];
++		struct ieee80211_tx_info *info =
++		    IEEE80211_SKB_CB(ampdu_retry_skb);
++		memcpy(rates, info->control.rates, sizeof(info->control.rates));
++		while ((ampdu_retry_skb =
++			__skb_dequeue_tail(ampdu_skb_retry_queue_p)) != NULL) {
++			struct ieee80211_tx_info *info =
++			    IEEE80211_SKB_CB(ampdu_retry_skb);
++			info->flags &= ~IEEE80211_TX_CTL_AMPDU;
++			memcpy(info->control.rates, rates,
++			       sizeof(info->control.rates));
++			ssv6xxx_update_txinfo(sc, ampdu_retry_skb);
++			_send_hci_skb(sc, ampdu_retry_skb,
++				      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
++		}
++	}
++}
++
++void ssv6200_ampdu_init(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	ssv6200_ampdu_hw_init(hw);
++	sc->tx.ampdu_tx_group_id = 0;
++#ifdef USE_ENCRYPT_WORK
++	INIT_WORK(&sc->ampdu_tx_encry_work, encry_work);
++	INIT_WORK(&sc->sync_hwkey_work, sync_hw_key_work);
++#endif
++}
++
++void ssv6200_ampdu_deinit(struct ieee80211_hw *hw)
++{
++}
++
++void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw)
++{
++	ieee80211_free_txskb(hw, skb);
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++struct mib_dump_data {
++	char *prt_buff;
++	size_t buff_size;
++	size_t prt_len;
++};
++#define AMPDU_TX_MIB_SUMMARY_BUF_SIZE (4096)
++static ssize_t ampdu_tx_mib_summary_read(struct file *file,
++					 char __user * user_buf, size_t count,
++					 loff_t * ppos)
++{
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)file->private_data;
++	char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
++	ssize_t summary_size;
++	ssize_t ret;
++	if (!summary_buf)
++		return -ENOMEM;
++	summary_size = ampdu_tx_mib_dump(ssv_sta_priv, summary_buf,
++					 AMPDU_TX_MIB_SUMMARY_BUF_SIZE);
++	ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
++				      summary_size);
++	kfree(summary_buf);
++	return ret;
++}
++
++static int ampdu_tx_mib_summary_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static const struct file_operations mib_summary_fops = {.read =
++	    ampdu_tx_mib_summary_read,.open = ampdu_tx_mib_summary_open,
++};
++
++static ssize_t ampdu_tx_tid_window_read(struct file *file,
++					char __user * user_buf, size_t count,
++					loff_t * ppos)
++{
++	struct AMPDU_TID_st *ampdu_tid =
++	    (struct AMPDU_TID_st *)file->private_data;
++	char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
++	ssize_t ret;
++	char *prn_ptr = summary_buf;
++	int prt_size;
++	int buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE;
++	int i;
++	struct sk_buff *ba_skb, *tmp_ba_skb;
++	if (!summary_buf)
++		return -ENOMEM;
++	prt_size = snprintf(prn_ptr, buf_size, "\nWMM_TID %d:\n"
++			    "\tWindow:", ampdu_tid->tidno);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i++) {
++		struct sk_buff *skb = ampdu_tid->aggr_pkts[i];
++		if ((i % 8) == 0) {
++			prt_size = snprintf(prn_ptr, buf_size, "\n\t\t");
++			prn_ptr += prt_size;
++			buf_size -= prt_size;
++		}
++		if (skb == NULL)
++			prt_size = snprintf(prn_ptr, buf_size, " %s", "NULL ");
++		else {
++			struct SKB_info_st *skb_info =
++			    (struct SKB_info_st *)(skb->head);
++			const char status_symbol[] = { 'N',
++				'A',
++				'S',
++				'R',
++				'P',
++				'D'
++			};
++			prt_size =
++			    snprintf(prn_ptr, buf_size, " %4d%c",
++				     ampdu_skb_ssn(skb),
++				     ((skb_info->ampdu_tx_status <=
++				       AMPDU_ST_DONE)
++				      ? status_symbol[skb_info->ampdu_tx_status]
++				      : 'X'));
++		}
++		prn_ptr += prt_size;
++		buf_size -= prt_size;
++	}
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\n\tEarly aggregated #: %d\n",
++		     ampdu_tid->early_aggr_skb_num);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\tBAW skb #: %d\n",
++		     ampdu_tid->aggr_pkt_num);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\tBAW head: %d\n",
++		     ampdu_tid->ssv_baw_head);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\tState: %d\n", ampdu_tid->state);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size = snprintf(prn_ptr, buf_size, "\tBA:\n");
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	skb_queue_walk_safe(&ampdu_tid->ba_q, ba_skb, tmp_ba_skb) {
++		prt_size = _dump_ba_skb(prn_ptr, buf_size, ba_skb);
++		prn_ptr += prt_size;
++		buf_size -= prt_size;
++	}
++	buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE - buf_size;
++	ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
++				      buf_size);
++	kfree(summary_buf);
++	return ret;
++}
++
++static int ampdu_tx_tid_window_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static const struct file_operations tid_window_fops = {.read =
++	    ampdu_tx_tid_window_read,.open = ampdu_tx_tid_window_open,
++};
++
++static int ampdu_tx_mib_reset_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t ampdu_tx_mib_reset_read(struct file *file,
++				       char __user * user_buf, size_t count,
++				       loff_t * ppos)
++{
++	char *reset_buf = kzalloc(64, GFP_KERNEL);
++	ssize_t ret;
++	u32 reset_size;
++	if (!reset_buf)
++		return -ENOMEM;
++	reset_size = snprintf(reset_buf, 63, "%d", 0);
++	ret = simple_read_from_buffer(user_buf, count, ppos, reset_buf,
++				      reset_size);
++	kfree(reset_buf);
++	return ret;
++}
++
++static ssize_t ampdu_tx_mib_reset_write(struct file *file,
++					const char __user * buffer,
++					size_t count, loff_t * pos)
++{
++	struct AMPDU_TID_st *ampdu_tid =
++	    (struct AMPDU_TID_st *)file->private_data;
++	memset(&ampdu_tid->mib, 0, sizeof(struct AMPDU_MIB_st));
++	return count;
++}
++
++static const struct file_operations mib_reset_fops
++    = {.read = ampdu_tx_mib_reset_read,
++	.open = ampdu_tx_mib_reset_open,
++	.write = ampdu_tx_mib_reset_write
++};
++
++static void ssv6200_ampdu_tx_init_debugfs(struct ssv_softc *sc,
++					  struct ssv_sta_priv_data
++					  *ssv_sta_priv)
++{
++	struct ssv_sta_info *sta_info = ssv_sta_priv->sta_info;
++	int i;
++	struct dentry *sta_debugfs_dir = sta_info->debugfs_dir;
++	dev_info(sc->dev, "Creating AMPDU TX debugfs.\n");
++	if (sta_debugfs_dir == NULL) {
++		dev_err(sc->dev, "No STA debugfs.\n");
++		return;
++	}
++	debugfs_create_file("ampdu_tx_summary", 00444, sta_debugfs_dir,
++			    ssv_sta_priv, &mib_summary_fops);
++	debugfs_create_u32("total_BA", 00644, sta_debugfs_dir,
++			   &ssv_sta_priv->ampdu_mib_total_BA_counter);
++	for (i = 0; i < WMM_TID_NUM; i++) {
++		char debugfs_name[20];
++		struct dentry *ampdu_tx_debugfs_dir;
++		int j;
++		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
++		struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
++		snprintf(debugfs_name, sizeof(debugfs_name), "ampdu_tx_%d", i);
++		ampdu_tx_debugfs_dir = debugfs_create_dir(debugfs_name,
++							  sta_debugfs_dir);
++		if (ampdu_tx_debugfs_dir == NULL) {
++			dev_err(sc->dev,
++				"Failed to create debugfs for AMPDU TX TID %d: %s\n",
++				i, debugfs_name);
++			continue;
++		}
++		ssv_sta_priv->ampdu_tid[i].debugfs_dir = ampdu_tx_debugfs_dir;
++		debugfs_create_file("baw_status", 00444, ampdu_tx_debugfs_dir,
++				    ampdu_tid, &tid_window_fops);
++		debugfs_create_file("reset", 00644, ampdu_tx_debugfs_dir,
++				    ampdu_tid, &mib_reset_fops);
++		debugfs_create_u32("total", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_ampdu_counter);
++		debugfs_create_u32("retry", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_retry_counter);
++		debugfs_create_u32("aggr_retry", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_aggr_retry_counter);
++		debugfs_create_u32("BAR", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_bar_counter);
++		debugfs_create_u32("Discarded", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_discard_counter);
++		debugfs_create_u32("BA", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_BA_counter);
++		debugfs_create_u32("Pass", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_pass_counter);
++		for (j = 0; j <= SSV_AMPDU_aggr_num_max; j++) {
++			char dist_dbg_name[10];
++			snprintf(dist_dbg_name, sizeof(dist_dbg_name),
++				 "aggr_%d", j);
++			debugfs_create_u32(dist_dbg_name, 00444,
++					   ampdu_tx_debugfs_dir,
++					   &ampdu_mib->ampdu_mib_dist[j]);
++		}
++		skb_queue_head_init(&ssv_sta_priv->ampdu_tid[i].ba_q);
++	}
++}
++#endif
++void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
++			      struct ieee80211_sta *sta)
++{
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	struct ssv_softc *sc;
++	u32 temp_i;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	sc = (struct ssv_softc *)hw->priv;
++	for (temp_i = 0; temp_i < WMM_TID_NUM; temp_i++) {
++		ssv_sta_priv->ampdu_tid[temp_i].sta = sta;
++		ssv_sta_priv->ampdu_tid[temp_i].state = AMPDU_STATE_STOP;
++		spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].
++			       ampdu_skb_tx_queue_lock);
++		spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].pkt_array_lock);
++	}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6200_ampdu_tx_init_debugfs(sc, ssv_sta_priv);
++#endif
++}
++
++void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
++			    struct ieee80211_hw *hw, u16 * ssn)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	struct AMPDU_TID_st *ampdu_tid;
++	int i;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ampdu_tid = &ssv_sta_priv->ampdu_tid[tid];
++	ampdu_tid->ssv_baw_head = SSV_ILLEGAL_SN;
++#ifdef DEBUG_AMPDU_FLUSH
++	pr_debug("Adding %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
++	       sta->addr[0], sta->addr[1], sta->addr[2],
++	       sta->addr[3], sta->addr[4], sta->addr[5],
++	       ampdu_tid->tidno, ampdu_tid);
++	{
++		int j;
++		for (j = 0; j <= MAX_TID; j++) {
++			if (sc->tid[j] == 0)
++				break;
++		}
++		if (j == MAX_TID) {
++			dev_err(sc->dev, "No room for new TID.\n");
++		} else
++			sc->tid[j] = ampdu_tid;
++	}
++#endif
++	list_add_tail_rcu(&ampdu_tid->list, &sc->tx.ampdu_tx_que);
++	skb_queue_head_init(&ampdu_tid->ampdu_skb_tx_queue);
++	skb_queue_head_init(&ampdu_tid->early_aggr_ampdu_q);
++	ampdu_tid->early_aggr_skb_num = 0;
++	skb_queue_head_init(&ampdu_tid->ampdu_skb_wait_encry_queue);
++	skb_queue_head_init(&ampdu_tid->retry_queue);
++	skb_queue_head_init(&ampdu_tid->release_queue);
++	for (i = 0;
++	     i <
++	     (sizeof(ampdu_tid->aggr_pkts) / sizeof(ampdu_tid->aggr_pkts[0]));
++	     i++)
++		ampdu_tid->aggr_pkts[i] = 0;
++	ampdu_tid->aggr_pkt_num = 0;
++	ampdu_tid->cur_ampdu_pkt = _alloc_ampdu_skb(sc, ampdu_tid, 0);
++#ifdef AMPDU_CHECK_SKB_SEQNO
++	ssv_sta_priv->ampdu_tid[tid].last_seqno = (-1);
++#endif
++	ssv_sta_priv->ampdu_mib_total_BA_counter = 0;
++	memset(&ssv_sta_priv->ampdu_tid[tid].mib, 0,
++	       sizeof(struct AMPDU_MIB_st));
++	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_START;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	skb_queue_head_init(&ssv_sta_priv->ampdu_tid[tid].ba_q);
++#endif
++}
++
++void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
++				struct ieee80211_hw *hw, u8 buffer_size)
++{
++    struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ssv_sta_priv->ampdu_tid[tid].tidno = tid;
++	ssv_sta_priv->ampdu_tid[tid].sta = sta;
++	ssv_sta_priv->ampdu_tid[tid].agg_num_max = MAX_AGGR_NUM;
++	if (buffer_size > IEEE80211_MAX_AMPDU_BUF) {
++		buffer_size = IEEE80211_MAX_AMPDU_BUF;
++	}
++	dev_info(sc->dev, "AMPDU buffer_size=%d\n", buffer_size);
++	ssv_sta_priv->ampdu_tid[tid].ssv_baw_size = SSV_AMPDU_WINDOW_SIZE;
++	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_OPERATION;
++}
++
++static void _clear_mpdu_q(struct ieee80211_hw *hw, struct sk_buff_head *q,
++			  bool aggregated_mpdu)
++{
++	struct sk_buff *skb;
++	while (1) {
++		skb = skb_dequeue(q);
++		if (!skb)
++			break;
++		if (aggregated_mpdu)
++			skb_pull(skb, AMPDU_DELIMITER_LEN);
++		ieee80211_tx_status_skb(hw, skb);
++	}
++}
++
++void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
++			   struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	if (ssv_sta_priv->ampdu_tid[tid].state == AMPDU_STATE_STOP)
++		return;
++	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_STOP;
++	dev_dbg(sc->dev, "ssv6200_ampdu_tx_stop\n");
++	if (!list_empty(&sc->tx.ampdu_tx_que)) {
++#ifdef DEBUG_AMPDU_FLUSH
++		{
++			int j;
++			struct AMPDU_TID_st *ampdu_tid =
++			    &ssv_sta_priv->ampdu_tid[tid];
++			for (j = 0; j <= MAX_TID; j++) {
++				if (sc->tid[j] == ampdu_tid)
++					break;
++			}
++			if (j == MAX_TID) {
++				dev_dbg(sc->dev, "No TID found when deleting it.\n");
++			} else
++				sc->tid[j] = NULL;
++			dev_dbg(sc->dev, "Deleting %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
++			       sta->addr[0], sta->addr[1], sta->addr[2],
++			       sta->addr[3], sta->addr[4], sta->addr[5],
++			       ampdu_tid->tidno, ampdu_tid);
++		}
++#endif
++		list_del_rcu(&ssv_sta_priv->ampdu_tid[tid].list);
++	}
++	dev_dbg(sc->dev, "clear tx q len=%d\n",
++	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue));
++	_clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue,
++		      true);
++	dev_dbg(sc->dev, "clear retry q len=%d\n",
++	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].retry_queue));
++	_clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].retry_queue, true);
++#ifdef USE_ENCRYPT_WORK
++	dev_dbg(sc->dev, "clear encrypt q len=%d\n",
++	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].
++			     ampdu_skb_wait_encry_queue));
++	_clear_mpdu_q(sc->hw,
++		      &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_wait_encry_queue,
++		      false);
++#endif
++	if (ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt != NULL) {
++		dev_kfree_skb_any(ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt);
++		ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt = NULL;
++	}
++	ssv6200_tx_flow_control((void *)sc,
++				sc->tx.hw_txqid[ssv_sta_priv->ampdu_tid[tid].
++						ac], false, 1000);
++}
++
++static void ssv6200_ampdu_tx_state_stop_func(struct ssv_softc *sc,
++					     struct ieee80211_sta *sta,
++					     struct sk_buff *skb,
++					     struct AMPDU_TID_st *cur_AMPDU_TID)
++{
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++	u8 *skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
++	u8 tid_no = skb_qos_ctl[0] & 0xf;
++	if ((sta->deflink.ht_cap.ht_supported == true)
++	    && (!!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
++		ieee80211_start_tx_ba_session(sta, tid_no, 0);
++		ampdu_db_log("start ampdu_tx(rc) : tid_no = %d\n", tid_no);
++	}
++}
++
++static void ssv6200_ampdu_tx_state_operation_func(struct ssv_softc *sc,
++						  struct ieee80211_sta *sta,
++						  struct sk_buff *skb,
++						  struct AMPDU_TID_st
++						  *cur_AMPDU_TID)
++{
++}
++
++void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
++				   struct sk_buff *skb)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)priv;
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++	u8 *skb_qos_ctl;
++	u8 tid_no;
++	{
++		skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
++		tid_no = skb_qos_ctl[0] & 0xf;
++		switch (ssv_sta_priv->ampdu_tid[tid_no].state) {
++		case AMPDU_STATE_STOP:
++			ssv6200_ampdu_tx_state_stop_func(sc, sta, skb,
++							 &(ssv_sta_priv->
++							   ampdu_tid[tid_no]));
++			break;
++		case AMPDU_STATE_START:
++			break;
++		case AMPDU_STATE_OPERATION:
++			ssv6200_ampdu_tx_state_operation_func(sc, sta, skb,
++							      &(ssv_sta_priv->
++								ampdu_tid
++								[tid_no]));
++			break;
++		default:
++			break;
++		}
++	}
++}
++
++void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu)
++{
++	bool is_empty_ampdu = (ampdu->len == 0);
++	unsigned char *data_dest;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++	BUG_ON(skb_tailroom(ampdu) < mpdu->len);
++	data_dest = skb_tail_pointer(ampdu);
++	skb_put(ampdu, mpdu->len);
++	if (is_empty_ampdu) {
++		struct ieee80211_tx_info *ampdu_info = IEEE80211_SKB_CB(ampdu);
++		struct ieee80211_tx_info *mpdu_info = IEEE80211_SKB_CB(mpdu);
++		SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
++		u32 max_size_for_rate =
++		    ampdu_max_transmit_length[mpdu_skb_info->lowest_rate];
++		BUG_ON(max_size_for_rate == 0);
++		memcpy(ampdu_info, mpdu_info, sizeof(struct ieee80211_tx_info));
++		skb_set_queue_mapping(ampdu, skb_get_queue_mapping(mpdu));
++		ampdu_hdr->first_sn = ampdu_skb_ssn(mpdu);
++		ampdu_hdr->sta = ((struct SKB_info_st *)mpdu->head)->sta;
++		if (ampdu_hdr->max_size > max_size_for_rate)
++			ampdu_hdr->max_size = max_size_for_rate;
++		memcpy(ampdu_hdr->rates, mpdu_skb_info->rates,
++		       sizeof(ampdu_hdr->rates));
++	}
++	memcpy(data_dest, mpdu->data, mpdu->len);
++	__skb_queue_tail(&ampdu_hdr->mpdu_q, mpdu);
++	ampdu_hdr->ssn[ampdu_hdr->mpdu_num++] = ampdu_skb_ssn(mpdu);
++	ampdu_hdr->size += mpdu->len;
++	BUG_ON(ampdu_hdr->size > ampdu_hdr->max_size);
++}
++
++u32 _flush_early_ampdu_q(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid)
++{
++	u32 flushed_ampdu = 0;
++	unsigned long flags;
++	struct sk_buff_head *early_aggr_ampdu_q =
++	    &ampdu_tid->early_aggr_ampdu_q;
++	spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++	while (skb_queue_len(early_aggr_ampdu_q)) {
++		struct sk_buff *head_ampdu;
++		struct ampdu_hdr_st *head_ampdu_hdr;
++		u32 ampdu_aggr_num;
++		head_ampdu = skb_peek(early_aggr_ampdu_q);
++		head_ampdu_hdr = (struct ampdu_hdr_st *)head_ampdu->head;
++		ampdu_aggr_num = skb_queue_len(&head_ampdu_hdr->mpdu_q);
++		if ((SSV_AMPDU_BA_WINDOW_SIZE - ampdu_tid->aggr_pkt_num)
++		    < ampdu_aggr_num)
++			break;
++		if (_sync_ampdu_pkt_arr(ampdu_tid, head_ampdu, false)) {
++			head_ampdu = __skb_dequeue(early_aggr_ampdu_q);
++			ampdu_tid->early_aggr_skb_num -= ampdu_aggr_num;
++#ifdef SSV_AMPDU_FLOW_CONTROL
++			if (ampdu_tid->early_aggr_skb_num
++			    <= SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND) {
++				ssv6200_tx_flow_control((void *)sc,
++							sc->tx.
++							hw_txqid[ampdu_tid->ac],
++							false, 1000);
++			}
++#endif
++			if ((skb_queue_len(early_aggr_ampdu_q) == 0)
++			    && (ampdu_tid->early_aggr_skb_num > 0)) {
++				dev_warn(sc->dev, "Empty early Q w. %d.\n",
++				       ampdu_tid->early_aggr_skb_num);
++			}
++			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
++					       flags);
++			_send_hci_skb(sc, head_ampdu,
++				      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
++			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++			flushed_ampdu++;
++		} else
++			break;
++	}
++	spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
++	return flushed_ampdu;
++}
++
++volatile int max_aggr_num = 24;
++void _aggr_ampdu_tx_q(struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct sk_buff *ampdu_skb = ampdu_tid->cur_ampdu_pkt;
++	while (skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue)) {
++		u32 aggr_len;
++		struct sk_buff *mpdu_skb;
++		struct ampdu_hdr_st *ampdu_hdr;
++		bool is_aggr_full = false;
++		if (ampdu_skb == NULL) {
++			ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, 0);
++			if (ampdu_skb == NULL)
++				break;
++			ampdu_tid->cur_ampdu_pkt = ampdu_skb;
++		}
++		ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++		aggr_len = skb_queue_len(&ampdu_hdr->mpdu_q);
++		do {
++			struct sk_buff_head *tx_q =
++			    &ampdu_tid->ampdu_skb_tx_queue;
++			unsigned long flags;
++			spin_lock_irqsave(&tx_q->lock, flags);
++			mpdu_skb = skb_peek(&ampdu_tid->ampdu_skb_tx_queue);
++			if (mpdu_skb == NULL) {
++				spin_unlock_irqrestore(&tx_q->lock, flags);
++				break;
++			}
++			if ((mpdu_skb->len + ampdu_hdr->size) >
++			    ampdu_hdr->max_size) {
++				is_aggr_full = true;
++				spin_unlock_irqrestore(&tx_q->lock, flags);
++				break;
++			}
++			mpdu_skb =
++			    __skb_dequeue(&ampdu_tid->ampdu_skb_tx_queue);
++			spin_unlock_irqrestore(&tx_q->lock, flags);
++			_put_mpdu_to_ampdu(ampdu_skb, mpdu_skb);
++		} while (++aggr_len < max_aggr_num);
++		if ((is_aggr_full || (aggr_len >= max_aggr_num))
++		    || ((aggr_len > 0)
++			&& (skb_queue_len(&ampdu_tid->early_aggr_ampdu_q) == 0)
++			&& (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN)
++			&& _is_skb_q_empty(sc, ampdu_skb))) {
++			_add_ampdu_txinfo(sc, ampdu_skb);
++			_queue_early_ampdu(sc, ampdu_tid, ampdu_skb);
++			ampdu_tid->cur_ampdu_pkt = ampdu_skb = NULL;
++		}
++		_flush_early_ampdu_q(sc, ampdu_tid);
++	}
++}
++
++void _queue_early_ampdu(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid,
++			struct sk_buff *ampdu_skb)
++{
++	unsigned long flags;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++	spin_lock_irqsave(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
++	__skb_queue_tail(&ampdu_tid->early_aggr_ampdu_q, ampdu_skb);
++	ampdu_tid->early_aggr_skb_num += skb_queue_len(&ampdu_hdr->mpdu_q);
++#ifdef SSV_AMPDU_FLOW_CONTROL
++	if (ampdu_tid->early_aggr_skb_num >= SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND) {
++		ssv6200_tx_flow_control((void *)sc,
++					sc->tx.hw_txqid[ampdu_tid->ac], true,
++					1000);
++	}
++#endif
++	spin_unlock_irqrestore(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
++}
++
++void _flush_mpdu(struct ssv_softc *sc, struct ieee80211_sta *sta)
++{
++	unsigned long flags;
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	int i;
++	for (i = 0;
++	     i <
++	     (sizeof(ssv_sta_priv->ampdu_tid) /
++	      sizeof(ssv_sta_priv->ampdu_tid[0])); i++) {
++		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
++		struct sk_buff_head *early_aggr_ampdu_q;
++		struct sk_buff *ampdu;
++		struct ampdu_hdr_st *ampdu_hdr;
++		struct sk_buff_head *mpdu_q;
++		struct sk_buff *mpdu;
++		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++			continue;
++		early_aggr_ampdu_q = &ampdu_tid->early_aggr_ampdu_q;
++		spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++		while ((ampdu = __skb_dequeue(early_aggr_ampdu_q)) != NULL) {
++			ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++			mpdu_q = &ampdu_hdr->mpdu_q;
++			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
++					       flags);
++			while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
++				_send_hci_skb(sc, mpdu,
++					      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
++			}
++			ssv6200_ampdu_release_skb(ampdu, sc->hw);
++			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++		}
++		if (ampdu_tid->cur_ampdu_pkt != NULL) {
++			ampdu_hdr =
++			    (struct ampdu_hdr_st *)ampdu_tid->cur_ampdu_pkt->
++			    head;
++			mpdu_q = &ampdu_hdr->mpdu_q;
++			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
++					       flags);
++			while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
++				_send_hci_skb(sc, mpdu,
++					      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
++			}
++			ssv6200_ampdu_release_skb(ampdu_tid->cur_ampdu_pkt,
++						  sc->hw);
++			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++			ampdu_tid->cur_ampdu_pkt = NULL;
++		}
++		spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
++	}
++}
++
++bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++#ifdef REPORT_TX_STATUS_DIRECTLY
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct sk_buff *tx_skb = skb;
++	struct sk_buff *copy_skb = NULL;
++#endif
++	struct SKB_info_st *mpdu_skb_info_p = (SKB_info *) (skb->head);
++	struct ieee80211_sta *sta = mpdu_skb_info_p->sta;
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	u8 tidno;
++	struct AMPDU_TID_st *ampdu_tid;
++	if (sta == NULL) {
++		WARN_ON(1);
++		return false;
++	}
++	tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
++	ampdu_db_log("tidno = %d\n", tidno);
++	ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
++	if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++		return false;
++#ifdef AMPDU_CHECK_SKB_SEQNO
++	{
++		u32 skb_seqno = ((struct ieee80211_hdr *)(skb->data))->seq_ctrl
++		    >> SSV_SEQ_NUM_SHIFT;
++		u32 tid_seqno = ampdu_tid->last_seqno;
++		if ((tid_seqno != (-1))
++		    && (skb_seqno != NEXT_PKT_SN(tid_seqno))) {
++			prn_aggr_err("Non continueous seq no: %d - %d\n",
++				     tid_seqno, skb_seqno);
++			return false;
++		}
++		ampdu_tid->last_seqno = skb_seqno;
++	}
++#endif
++	mpdu_skb_info_p->lowest_rate =
++	    ssv62xx_ht_rate_update(skb, sc, mpdu_skb_info_p->rates);
++	if (ampdu_max_transmit_length[mpdu_skb_info_p->lowest_rate] == 0) {
++		_flush_mpdu(sc, sta);
++		return false;
++	}
++	mpdu_skb_info_p = (SKB_info *) (skb->head);
++	mpdu_skb_info_p->mpdu_retry_counter = 0;
++	mpdu_skb_info_p->ampdu_tx_status = AMPDU_ST_NON_AMPDU;
++	mpdu_skb_info_p->ampdu_tx_final_retry_count = 0;
++	ssv_sta_priv->ampdu_tid[tidno].ac = skb_get_queue_mapping(skb);
++#ifdef REPORT_TX_STATUS_DIRECTLY
++	info->flags |= IEEE80211_TX_STAT_ACK;
++	copy_skb = skb_copy(tx_skb, GFP_ATOMIC);
++	if (!copy_skb) {
++		dev_err(sc->dev, "create TX skb copy failed!\n");
++		return false;
++	}
++	ieee80211_tx_status_skb(sc->hw, tx_skb);
++	skb = copy_skb;
++#endif
++	{
++		bool ret;
++		ret = ssv6200_ampdu_add_delimiter_and_crc32(skb);
++		if (ret == false) {
++			ssv6200_ampdu_release_skb(skb, hw);
++			return false;
++		}
++		skb_queue_tail(&ssv_sta_priv->ampdu_tid[tidno].
++			       ampdu_skb_tx_queue, skb);
++		ssv_sta_priv->ampdu_tid[tidno].timestamp = jiffies;
++	}
++	_aggr_ampdu_tx_q(hw, &ssv_sta_priv->ampdu_tid[tidno]);
++	return true;
++}
++
++u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct AMPDU_TID_st *cur_AMPDU_TID;
++	u32 flushed_ampdu = 0;
++	u32 tid_idx = 0;
++	if (!list_empty(&sc->tx.ampdu_tx_que)) {
++		list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
++					list) {
++			tid_idx++;
++#ifdef DEBUG_AMPDU_FLUSH
++			{
++				int i = 0;
++				for (i = 0; i < MAX_TID; i++)
++					if (sc->tid[i] == cur_AMPDU_TID)
++						break;
++				if (i == MAX_TID) {
++					dev_err(sc->dev, "No matching TID (%d) found! %p\n",
++					       tid_idx, cur_AMPDU_TID);
++					continue;
++				}
++			}
++#endif
++			if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION) {
++				struct ieee80211_sta *sta = cur_AMPDU_TID->sta;
++				struct ssv_sta_priv_data *sta_priv =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++				dev_dbg(sc->dev, "STA %d TID %d is @%d\n",
++					sta_priv->sta_idx, cur_AMPDU_TID->tidno,
++					cur_AMPDU_TID->state);
++				continue;
++			}
++			if ((cur_AMPDU_TID->state == AMPDU_STATE_OPERATION)
++			    &&
++			    (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q)
++			     == 0)
++			    && (cur_AMPDU_TID->cur_ampdu_pkt != NULL)) {
++				struct ampdu_hdr_st *ampdu_hdr =
++				    (struct ampdu_hdr_st *)(cur_AMPDU_TID->
++							    cur_ampdu_pkt->
++							    head);
++				u32 aggr_len =
++				    skb_queue_len(&ampdu_hdr->mpdu_q);
++				if (aggr_len) {
++					struct sk_buff *ampdu_skb =
++					    cur_AMPDU_TID->cur_ampdu_pkt;
++					cur_AMPDU_TID->cur_ampdu_pkt = NULL;
++					_add_ampdu_txinfo(sc, ampdu_skb);
++					_queue_early_ampdu(sc, cur_AMPDU_TID,
++							   ampdu_skb);
++				}
++			}
++			if (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q) >
++			    0)
++				flushed_ampdu +=
++				    _flush_early_ampdu_q(sc, cur_AMPDU_TID);
++		}
++	}
++	return flushed_ampdu;
++}
++
++int _dump_BA_notification(char *buf,
++			  struct ampdu_ba_notify_data *ba_notification)
++{
++	int i;
++	char *orig_buf = buf;
++	for (i = 0; i < MAX_AGGR_NUM; i++) {
++		if (ba_notification->seq_no[i] == (u16) (-1))
++			break;
++		buf += sprintf(buf, " %d", ba_notification->seq_no[i]);
++	}
++	return ((size_t)buf - (size_t)orig_buf);
++}
++
++int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb)
++{
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(ba_skb->data
++							     +
++							     SSV6XXX_RX_DESC_LEN);
++	AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
++	u32 ssn = BA_frame->BA_ssn;
++	struct ampdu_ba_notify_data *ba_notification =
++	    (struct ampdu_ba_notify_data *)(ba_skb->data + ba_skb->len
++					    -
++					    sizeof(struct
++						   ampdu_ba_notify_data));
++	int prt_size;
++	prt_size = snprintf(buf, buf_size, "\n\t\t%04d %08X %08X -",
++			    ssn, BA_frame->BA_sn_bit_map[0],
++			    BA_frame->BA_sn_bit_map[1]);
++	buf_size -= prt_size;
++	buf += prt_size;
++	prt_size = prt_size + _dump_BA_notification(buf, ba_notification);
++	return prt_size;
++}
++
++static bool _ssn_to_bit_idx(u32 start_ssn, u32 mpdu_ssn, u32 * word_idx,
++			    u32 * bit_idx)
++{
++	u32 ret_bit_idx, ret_word_idx = 0;
++	s32 diff = mpdu_ssn - start_ssn;
++	if (diff >= 0) {
++		if (diff >= SSV_AMPDU_BA_WINDOW_SIZE) {
++			return false;
++		}
++		ret_bit_idx = diff;
++	} else {
++		diff = -diff;
++		if (diff <= (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
++			*word_idx = 0;
++			*bit_idx = 0;
++			return false;
++		}
++		ret_bit_idx = SSV_AMPDU_MAX_SSN - diff;
++	}
++	if (ret_bit_idx >= 32) {
++		ret_bit_idx -= 32;
++		ret_word_idx = 1;
++	}
++	*bit_idx = ret_bit_idx;
++	*word_idx = ret_word_idx;
++	return true;
++}
++
++static bool _inc_bit_idx(u32 ssn_1st, u32 ssn_next, u32 * word_idx,
++			 u32 * bit_idx)
++{
++	u32 ret_word_idx = *word_idx, ret_bit_idx = *bit_idx;
++	s32 diff = (s32) ssn_1st - (s32) ssn_next;
++	if (diff > 0) {
++		if (diff < (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
++			prn_aggr_err
++			    ("Irrational SN distance in AMPDU: %d %d.\n",
++			     ssn_1st, ssn_next);
++			return false;
++		}
++		diff = SSV_AMPDU_MAX_SSN - diff;
++	} else {
++		diff = -diff;
++	}
++	if (diff > SSV_AMPDU_MAX_SSN)
++		prn_aggr_err("DF %d - %d = %d\n", ssn_1st, ssn_next, diff);
++	ret_bit_idx += diff;
++	if (ret_bit_idx >= 32) {
++		ret_bit_idx -= 32;
++		ret_word_idx++;
++	}
++	*word_idx = ret_word_idx;
++	*bit_idx = ret_bit_idx;
++	return true;
++}
++
++static void _release_frames(struct AMPDU_TID_st *ampdu_tid)
++{
++	u32 head_ssn, head_ssn_before, last_ssn;
++	struct sk_buff **skb;
++	struct SKB_info_st *skb_info;
++	spin_lock_bh(&ampdu_tid->pkt_array_lock);
++	head_ssn_before = ampdu_tid->ssv_baw_head;
++	if (head_ssn_before >= SSV_AMPDU_MAX_SSN) {
++		spin_unlock_bh(&ampdu_tid->pkt_array_lock);
++		prn_aggr_err("l x.x %d\n", head_ssn_before);
++		return;
++	}
++	head_ssn = ampdu_tid->ssv_baw_head;
++	last_ssn = head_ssn;
++	do {
++		skb = &INDEX_PKT_BY_SSN(ampdu_tid, head_ssn);
++		if (*skb == NULL) {
++			head_ssn = SSV_ILLEGAL_SN;
++			{
++				int i;
++				char sn_str[66 * 5] = "";
++				char *str = sn_str;
++				for (i = 0; i < 64; i++)
++					if (ampdu_tid->aggr_pkts[i] != NULL) {
++						str += sprintf(str, "%d ",
++							       ampdu_skb_ssn
++							       (ampdu_tid->
++								aggr_pkts[i]));
++					}
++				*str = 0;
++				if (str == sn_str) {
++				} else
++					prn_aggr_err("ILL %d %d - %d (%s)\n",
++						     head_ssn_before, last_ssn,
++						     ampdu_tid->aggr_pkt_num,
++						     sn_str);
++			}
++			break;
++		}
++		skb_info = (struct SKB_info_st *)((*skb)->head);
++		if ((skb_info->ampdu_tx_status == AMPDU_ST_DONE)
++		    || (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)) {
++			__skb_queue_tail(&ampdu_tid->release_queue, *skb);
++			*skb = NULL;
++			last_ssn = head_ssn;
++			INC_PKT_SN(head_ssn);
++			ampdu_tid->aggr_pkt_num--;
++			if (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)
++				ampdu_tid->mib.ampdu_mib_discard_counter++;
++		} else {
++			break;
++		}
++	} while (1);
++	ampdu_tid->ssv_baw_head = head_ssn;
++	spin_unlock_bh(&ampdu_tid->pkt_array_lock);
++}
++
++static int _collect_retry_frames(struct AMPDU_TID_st *ampdu_tid)
++{
++	u16 ssn, head_ssn, end_ssn;
++	int num_retry = 0;
++	int timeout_check = 1;
++	unsigned long check_jiffies = jiffies;
++	head_ssn = ampdu_tid->ssv_baw_head;
++	ssn = head_ssn;
++	if (ssn == SSV_ILLEGAL_SN)
++		return 0;
++	end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
++	do {
++		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		struct SKB_info_st *skb_info;
++		int timeout_retry = 0;
++		if (skb == NULL)
++			break;
++		skb_info = (SKB_info *) (skb->head);
++		if (timeout_check
++		    && (skb_info->ampdu_tx_status == AMPDU_ST_SENT)) {
++			unsigned long cur_jiffies = jiffies;
++			unsigned long timeout_jiffies = skb_info->aggr_timestamp
++			    + msecs_to_jiffies(BA_WAIT_TIMEOUT);
++			u32 delta_ms;
++			if (time_before(cur_jiffies, timeout_jiffies)) {
++				timeout_check = 0;
++				continue;
++			}
++			_mark_skb_retry(skb_info, skb);
++			delta_ms =
++			    jiffies_to_msecs(cur_jiffies -
++					     skb_info->aggr_timestamp);
++			prn_aggr_err("t S%d-T%d-%d (%u)\n",
++				     ((struct ssv_sta_priv_data *)skb_info->
++				      sta->drv_priv)->sta_idx, ampdu_tid->tidno,
++				     ssn, delta_ms);
++			if (delta_ms > 1000) {
++				prn_aggr_err("Last checktime %lu - %lu = %u\n",
++					     check_jiffies,
++					     ampdu_tid->timestamp,
++					     jiffies_to_msecs(check_jiffies -
++							      ampdu_tid->
++							      timestamp));
++			}
++			timeout_retry = 1;
++		}
++		if (skb_info->ampdu_tx_status == AMPDU_ST_RETRY) {
++			skb_queue_tail(&ampdu_tid->retry_queue, skb);
++			ampdu_tid->mib.ampdu_mib_retry_counter++;
++			num_retry++;
++		}
++		INC_PKT_SN(ssn);
++	} while (ssn != end_ssn);
++	ampdu_tid->timestamp = check_jiffies;
++	return num_retry;
++}
++
++int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb)
++{
++	if (skb_info->mpdu_retry_counter < SSV_AMPDU_retry_counter_max) {
++		if (skb_info->mpdu_retry_counter == 0) {
++			struct ieee80211_hdr *skb_hdr = ampdu_skb_hdr(skb);
++			skb_hdr->frame_control |=
++			    cpu_to_le16(IEEE80211_FCTL_RETRY);
++		}
++		skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
++		skb_info->mpdu_retry_counter++;
++		return 1;
++	} else {
++		skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
++		prn_aggr_err("p %d\n", ampdu_skb_ssn(skb));
++		return 0;
++	}
++}
++
++static u32 _ba_map_walker(struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,
++			  u32 sn_bit_map[2],
++			  struct ampdu_ba_notify_data *ba_notify_data,
++			  u32 * p_acked_num)
++{
++	int i = 0;
++	u32 ssn = ba_notify_data->seq_no[0];
++	u32 word_idx = (-1), bit_idx = (-1);
++	bool found = _ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx);
++	bool first_found = found;
++	u32 aggr_num = 0;
++	u32 acked_num = 0;
++	if (found && (word_idx >= 2 || bit_idx >= 32))
++		prn_aggr_err("idx error 1: %d %d %d %d\n",
++			     start_ssn, ssn, word_idx, bit_idx);
++	while ((i < MAX_AGGR_NUM) && (ssn < SSV_AMPDU_MAX_SSN)) {
++		u32 cur_ssn;
++		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		u32 skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
++		struct SKB_info_st *skb_info;
++		aggr_num++;
++		if (skb_ssn != ssn) {
++			prn_aggr_err("Unmatched SSN packet: %d - %d - %d\n",
++				     ssn, skb_ssn, start_ssn);
++		} else {
++			skb_info = (struct SKB_info_st *)(skb->head);
++			if (found && (sn_bit_map[word_idx] & (1 << bit_idx))) {
++				if (skb_info->ampdu_tx_status != AMPDU_ST_SENT) {
++					pr_err("BA marks a MPDU of status %d!\n",
++					       skb_info->ampdu_tx_status);
++				}
++				skb_info->ampdu_tx_status = AMPDU_ST_DONE;
++				acked_num++;
++			} else {
++				_mark_skb_retry(skb_info, skb);
++			}
++		}
++		cur_ssn = ssn;
++		if (++i >= MAX_AGGR_NUM)
++			break;
++		ssn = ba_notify_data->seq_no[i];
++		if (ssn >= SSV_AMPDU_MAX_SSN)
++			break;
++		if (first_found) {
++			u32 old_word_idx = word_idx, old_bit_idx = bit_idx;
++			found = _inc_bit_idx(cur_ssn, ssn, &word_idx, &bit_idx);
++			if (found && (word_idx >= 2 || bit_idx >= 32)) {
++				prn_aggr_err
++				    ("idx error 2: %d 0x%08X 0X%08X %d %d (%d %d) (%d %d)\n",
++				     start_ssn, sn_bit_map[1], sn_bit_map[0],
++				     cur_ssn, ssn, word_idx, bit_idx,
++				     old_word_idx, old_bit_idx);
++				found = false;
++			} else if (!found) {
++				char strbuf[256];
++				_dump_BA_notification(strbuf, ba_notify_data);
++				prn_aggr_err("SN out-of-order: %d\n%s\n",
++					     start_ssn, strbuf);
++			}
++		} else {
++			found =
++			    _ssn_to_bit_idx(start_ssn, ssn, &word_idx,
++					    &bit_idx);
++			first_found = found;
++			if (found && (word_idx >= 2 || bit_idx >= 32))
++				prn_aggr_err("idx error 3: %d %d %d %d\n",
++					     cur_ssn, ssn, word_idx, bit_idx);
++		}
++	}
++	_release_frames(ampdu_tid);
++	if (p_acked_num != NULL)
++		*p_acked_num = acked_num;
++	return aggr_num;
++}
++
++static void _flush_release_queue(struct ieee80211_hw *hw,
++				 struct sk_buff_head *release_queue)
++{
++	do {
++		struct sk_buff *ampdu_skb = __skb_dequeue(release_queue);
++		struct ieee80211_tx_info *tx_info;
++		struct SKB_info_st *skb_info;
++		if (ampdu_skb == NULL)
++			break;
++		skb_info = (struct SKB_info_st *)(ampdu_skb->head);
++		skb_pull(ampdu_skb, AMPDU_DELIMITER_LEN);
++		tx_info = IEEE80211_SKB_CB(ampdu_skb);
++		ieee80211_tx_info_clear_status(tx_info);
++		tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
++		if (skb_info->ampdu_tx_status == AMPDU_ST_DONE)
++			tx_info->flags |= IEEE80211_TX_STAT_ACK;
++		tx_info->status.ampdu_len = 1;
++		tx_info->status.ampdu_ack_len = 1;
++#ifdef REPORT_TX_STATUS_DIRECTLY
++		dev_kfree_skb_any(ampdu_skb);
++#else
++#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_TX_DATA)
++		ieee80211_tx_status_skb(hw, ampdu_skb);
++#else
++		ieee80211_tx_status_irqsafe(hw, ampdu_skb);
++#endif
++#endif
++	} while (1);
++}
++
++void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct cfg_host_event *host_event = (struct cfg_host_event *)skb->data;
++	struct ampdu_ba_notify_data *ba_notification =
++	    (struct ampdu_ba_notify_data *)&host_event->dat[0];
++	struct ieee80211_hdr *hdr =
++	    (struct ieee80211_hdr *)(ba_notification + 1);
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_sta *sta = ssv6xxx_find_sta_by_addr(sc, hdr->addr1);
++	u8 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	char seq_str[256];
++	struct AMPDU_TID_st *ampdu_tid;
++	int i;
++	u16 aggr_num = 0;
++	struct firmware_rate_control_report_data *report_data;
++	if (sta == NULL) {
++		prn_aggr_err
++		    ("NO BA for %d to unmatched STA %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
++		     tidno, hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
++		     hdr->addr1[3], hdr->addr1[4], hdr->addr1[5], seq_str);
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	_dump_BA_notification(seq_str, ba_notification);
++	prn_aggr_err("NO BA for %d to %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
++		     tidno, sta->addr[0], sta->addr[1], sta->addr[2],
++		     sta->addr[3], sta->addr[4], sta->addr[5], seq_str);
++	ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
++	if (ampdu_tid->state != AMPDU_STATE_OPERATION) {
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	for (i = 0; i < MAX_AGGR_NUM; i++) {
++		u32 ssn = ba_notification->seq_no[i];
++		struct sk_buff *skb;
++		u32 skb_ssn;
++		struct SKB_info_st *skb_info;
++		if (ssn >= (4096))
++			break;
++		aggr_num++;
++		skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
++		if (skb_ssn != ssn) {
++			prn_aggr_err("Unmatched SSN packet: %d - %d\n", ssn,
++				     skb_ssn);
++			continue;
++		}
++		skb_info = (struct SKB_info_st *)(skb->head);
++		if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
++			if (skb_info->mpdu_retry_counter <
++			    SSV_AMPDU_retry_counter_max) {
++				if (skb_info->mpdu_retry_counter == 0) {
++					struct ieee80211_hdr *skb_hdr =
++					    ampdu_skb_hdr(skb);
++					skb_hdr->frame_control |=
++					    cpu_to_le16(IEEE80211_FCTL_RETRY);
++				}
++				skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
++				skb_info->mpdu_retry_counter++;
++			} else {
++				skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
++				prn_aggr_err("p %d\n", skb_ssn);
++			}
++		} else {
++			prn_aggr_err("S %d %d\n", skb_ssn,
++				     skb_info->ampdu_tx_status);
++		}
++	}
++	_release_frames(ampdu_tid);
++	host_event->h_event = SOC_EVT_RC_AMPDU_REPORT;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
++	report_data->ampdu_len = aggr_num;
++	report_data->ampdu_ack_len = 0;
++	report_data->wsid = ssv_sta_priv->sta_info->hw_wsid;
++	skb_queue_tail(&sc->rc_report_queue, skb);
++	if (sc->rc_sample_sechedule == 0)
++		queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
++}
++
++void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data
++							     +
++							     SSV6XXX_RX_DESC_LEN);
++	AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
++	struct ieee80211_sta *sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	struct ampdu_ba_notify_data *ba_notification;
++	u32 ssn, aggr_num = 0, acked_num = 0;
++	u8 tid_no;
++	u32 sn_bit_map[2];
++	struct firmware_rate_control_report_data *report_data;
++	HDR_HostEvent *host_evt;
++	sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
++	if (sta == NULL) {
++		if (skb->len > AMPDU_BA_FRAME_LEN) {
++			char strbuf[256];
++			struct ampdu_ba_notify_data *ba_notification =
++			    (struct ampdu_ba_notify_data *)(skb->data + skb->len
++							    -
++							    sizeof(struct
++								   ampdu_ba_notify_data));
++			_dump_BA_notification(strbuf, ba_notification);
++			prn_aggr_err
++			    ("BA from not connected STA (%02X-%02X-%02X-%02X-%02X-%02X) (%s)\n",
++			     BA_frame->ta_addr[0], BA_frame->ta_addr[1],
++			     BA_frame->ta_addr[2], BA_frame->ta_addr[3],
++			     BA_frame->ta_addr[4], BA_frame->ta_addr[5],
++			     strbuf);
++		}
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ssn = BA_frame->BA_ssn;
++	sn_bit_map[0] = BA_frame->BA_sn_bit_map[0];
++	sn_bit_map[1] = BA_frame->BA_sn_bit_map[1];
++	tid_no = BA_frame->tid_info;
++	ssv_sta_priv->ampdu_mib_total_BA_counter++;
++	if (ssv_sta_priv->ampdu_tid[tid_no].state == AMPDU_STATE_STOP) {
++		prn_aggr_err
++		    ("ssv6200_ampdu_BA_handler state == AMPDU_STATE_STOP.\n");
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ssv_sta_priv->ampdu_tid[tid_no].mib.ampdu_mib_BA_counter++;
++	if (skb->len <= AMPDU_BA_FRAME_LEN) {
++		prn_aggr_err("b %d\n", ssn);
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ba_notification =
++	    (struct ampdu_ba_notify_data *)(skb->data + skb->len
++					    -
++					    sizeof(struct
++						   ampdu_ba_notify_data));
++	aggr_num =
++	    _ba_map_walker(&(ssv_sta_priv->ampdu_tid[tid_no]), ssn, sn_bit_map,
++			   ba_notification, &acked_num);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (ssv_sta_priv->ampdu_tid[tid_no].debugfs_dir) {
++		struct sk_buff *dup_skb;
++		if (skb_queue_len(&ssv_sta_priv->ampdu_tid[tid_no].ba_q) > 24) {
++			struct sk_buff *ba_skb =
++			    skb_dequeue(&ssv_sta_priv->ampdu_tid[tid_no].ba_q);
++			if (ba_skb)
++				dev_kfree_skb_any(ba_skb);
++		}
++		dup_skb = skb_clone(skb, GFP_ATOMIC);
++		if (dup_skb)
++			skb_queue_tail(&ssv_sta_priv->ampdu_tid[tid_no].ba_q,
++				       dup_skb);
++	}
++#endif
++	skb_trim(skb, skb->len - sizeof(struct ampdu_ba_notify_data));
++	host_evt = (HDR_HostEvent *) skb->data;
++	host_evt->h_event = SOC_EVT_RC_AMPDU_REPORT;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_evt->dat[0];
++	memcpy(report_data, ba_notification,
++	       sizeof(struct firmware_rate_control_report_data));
++	report_data->ampdu_len = aggr_num;
++	report_data->ampdu_ack_len = acked_num;
++#ifdef RATE_CONTROL_HT_PERCENTAGE_TRACE
++	if ((acked_num) && (acked_num != aggr_num)) {
++		int i;
++		for (i = 0; i < SSV62XX_TX_MAX_RATES; i++) {
++			if (report_data->rates[i].data_rate == -1)
++				break;
++			if (report_data->rates[i].count == 0)
++                dev_err(sc->dev, "illegal HT report\n");
++
++			dev_dbg(sc->dev, "i=[%d] rate[%d] count[%d]\n", i,
++			       report_data->rates[i].data_rate,
++			       report_data->rates[i].count);
++		}
++		dev_dbg(sc->dev, "AMPDU percentage = %d%% \n",
++		       acked_num * 100 / aggr_num);
++	} else if (acked_num == 0) {
++		dev_dbg(sc->dev, "AMPDU percentage = 0%% aggr_num=%d acked_num=%d\n",
++		       aggr_num, acked_num);
++	}
++#endif
++	skb_queue_tail(&sc->rc_report_queue, skb);
++	if (sc->rc_sample_sechedule == 0)
++		queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
++}
++
++static void _postprocess_BA(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
++			    void *param)
++{
++	int j;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	if ((sta_info->sta == NULL)
++	    || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
++		return;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	for (j = 0; j < WMM_TID_NUM; j++) {
++		AMPDU_TID *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
++		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++			continue;
++		_collect_retry_frames(ampdu_tid);
++		ssv6200_ampdu_send_retry(sc->hw, ampdu_tid,
++					 &ampdu_tid->retry_queue, true);
++		_flush_early_ampdu_q(sc, ampdu_tid);
++		_flush_release_queue(sc->hw, &ampdu_tid->release_queue);
++	}
++}
++
++void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	ssv6xxx_foreach_sta(sc, _postprocess_BA, NULL);
++}
++
++static void ssv6200_hw_set_rx_ba_session(struct ssv_hw *sh, bool on, u8 * ta,
++					 u16 tid, u16 ssn, u8 buf_size)
++{
++	if (on) {
++		u32 u32ta;
++		u32ta = 0;
++		u32ta |= (ta[0] & 0xff) << (8 * 0);
++		u32ta |= (ta[1] & 0xff) << (8 * 1);
++		u32ta |= (ta[2] & 0xff) << (8 * 2);
++		u32ta |= (ta[3] & 0xff) << (8 * 3);
++		SMAC_REG_WRITE(sh, ADR_BA_TA_0, u32ta);
++		u32ta = 0;
++		u32ta |= (ta[4] & 0xff) << (8 * 0);
++		u32ta |= (ta[5] & 0xff) << (8 * 1);
++		SMAC_REG_WRITE(sh, ADR_BA_TA_1, u32ta);
++		SMAC_REG_WRITE(sh, ADR_BA_TID, tid);
++		SMAC_REG_WRITE(sh, ADR_BA_ST_SEQ, ssn);
++		SMAC_REG_WRITE(sh, ADR_BA_SB0, 0);
++		SMAC_REG_WRITE(sh, ADR_BA_SB1, 0);
++		SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0xb);
++	} else {
++		SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0x0);
++	}
++}
++
++void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work)
++{
++	struct ssv_softc
++	*sc = container_of(work, struct ssv_softc, set_ampdu_rx_add_work);
++	ssv6200_hw_set_rx_ba_session(sc->sh, true, sc->ba_ra_addr, sc->ba_tid,
++				     sc->ba_ssn, 64);
++}
++
++void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work)
++{
++	struct ssv_softc *sc = container_of(work, struct ssv_softc,
++					    set_ampdu_rx_del_work);
++	u8 addr[6] = { 0 };
++	ssv6200_hw_set_rx_ba_session(sc->sh, false, addr, 0, 0, 0);
++}
++
++static void _reset_ampdu_mib(struct ssv_softc *sc,
++			     struct ssv_sta_info *sta_info, void *param)
++{
++	struct ieee80211_sta *sta = sta_info->sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	int i;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	for (i = 0; i < WMM_TID_NUM; i++) {
++		ssv_sta_priv->ampdu_tid[i].ampdu_mib_reset = 1;
++	}
++}
++
++void ssv6xxx_ampdu_mib_reset(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	if (sc == NULL)
++		return;
++	ssv6xxx_foreach_sta(sc, _reset_ampdu_mib, NULL);
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
++			  char *mib_str, ssize_t length)
++{
++	ssize_t buf_size = length;
++	ssize_t prt_size;
++	int j;
++	struct ssv_sta_info *ssv_sta = ssv_sta_priv->sta_info;
++	if (ssv_sta->sta == NULL) {
++		prt_size = snprintf(mib_str, buf_size, "\n    NULL STA.\n");
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		goto mib_dump_exit;
++	}
++	for (j = 0; j < WMM_TID_NUM; j++) {
++		int k;
++		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
++		struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
++		prt_size =
++		    snprintf(mib_str, buf_size, "\n    WMM_TID %d@%d\n", j,
++			     ampdu_tid->state);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++			continue;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        BA window size: %d\n",
++			     ampdu_tid->ssv_baw_size);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        BA window head: %d\n",
++			     ampdu_tid->ssv_baw_head);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Sending aggregated #: %d\n",
++				    ampdu_tid->aggr_pkt_num);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Waiting #: %d\n",
++			     skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue));
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Early aggregated %d\n",
++			     ampdu_tid->early_aggr_skb_num);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        MPDU: %d\n",
++				    ampdu_mib->ampdu_mib_mpdu_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Passed: %d\n",
++				    ampdu_mib->ampdu_mib_pass_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Retry: %d\n",
++				    ampdu_mib->ampdu_mib_retry_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        AMPDU: %d\n",
++				    ampdu_mib->ampdu_mib_ampdu_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Retry AMPDU: %d\n",
++				    ampdu_mib->ampdu_mib_aggr_retry_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        BAR count: %d\n",
++				    ampdu_mib->ampdu_mib_bar_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Discard count: %d\n",
++				    ampdu_mib->ampdu_mib_discard_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        BA count: %d\n",
++				    ampdu_mib->ampdu_mib_BA_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Total BA count: %d\n",
++			     ssv_sta_priv->ampdu_mib_total_BA_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Aggr # count:\n");
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		for (k = 0; k <= SSV_AMPDU_aggr_num_max; k++) {
++			prt_size =
++			    snprintf(mib_str, buf_size, "            %d: %d\n",
++				     k, ampdu_mib->ampdu_mib_dist[k]);
++			mib_str += prt_size;
++			buf_size -= prt_size;
++		}
++	}
++ mib_dump_exit:
++	return (length - buf_size);
++}
++
++static void _dump_ampdu_mib(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
++			    void *param)
++{
++	struct mib_dump_data *dump_data = (struct mib_dump_data *)param;
++	struct ieee80211_sta *sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	ssize_t buf_size;
++	ssize_t prt_size;
++	char *mib_str = dump_data->prt_buff;
++	if (param == NULL)
++		return;
++	buf_size = dump_data->buff_size - 1;
++	sta = sta_info->sta;
++	if ((sta == NULL) || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
++		return;
++	prt_size = snprintf(mib_str, buf_size,
++			    "STA: %02X-%02X-%02X-%02X-%02X-%02X:\n",
++			    sta->addr[0], sta->addr[1], sta->addr[2],
++			    sta->addr[3], sta->addr[4], sta->addr[5]);
++	mib_str += prt_size;
++	buf_size -= prt_size;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	prt_size = ampdu_tx_mib_dump(ssv_sta_priv, mib_str, buf_size);
++	mib_str += prt_size;
++	buf_size -= prt_size;
++	dump_data->prt_len = (dump_data->buff_size - 1 - buf_size);
++	dump_data->prt_buff = mib_str;
++	dump_data->buff_size = buf_size;
++}
++
++ssize_t ssv6xxx_ampdu_mib_dump(struct ieee80211_hw *hw, char *mib_str,
++			       ssize_t length)
++{
++	struct ssv_softc *sc = hw->priv;
++	ssize_t buf_size = length - 1;
++	struct mib_dump_data dump_data = { mib_str, buf_size, 0 };
++	if (sc == NULL)
++		return 0;
++	ssv6xxx_foreach_sta(sc, _dump_ampdu_mib, &dump_data);
++	return dump_data.prt_len;
++}
++#endif
++struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
++				 struct AMPDU_TID_st *ampdu_tid, u32 len)
++{
++	unsigned char *payload_addr;
++	u32 headroom = sc->hw->extra_tx_headroom;
++	u32 offset;
++	u32 cur_max_ampdu_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
++	u32 extra_room = sc->sh->tx_desc_len * 2 + 48;
++	u32 max_physical_len = (len
++				&& ((len + extra_room) < cur_max_ampdu_size))
++	    ? (len + extra_room)
++	    : cur_max_ampdu_size;
++	u32 skb_len = max_physical_len + headroom + 3;
++	struct sk_buff *ampdu_skb = __dev_alloc_skb(skb_len, GFP_KERNEL);
++	struct ampdu_hdr_st *ampdu_hdr;
++	if (ampdu_skb == NULL) {
++		dev_err(sc->dev, "AMPDU allocation of size %d(%d) failed\n",
++			len, skb_len);
++		return NULL;
++	}
++	payload_addr = ampdu_skb->data + headroom - sc->sh->tx_desc_len;
++	offset = ((size_t)payload_addr) % 4U;
++	if (offset) {
++		dev_dbg(sc->dev, "Align AMPDU data %d\n", offset);
++		skb_reserve(ampdu_skb, headroom + 4 - offset);
++	} else
++		skb_reserve(ampdu_skb, headroom);
++	ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++	skb_queue_head_init(&ampdu_hdr->mpdu_q);
++	ampdu_hdr->max_size = max_physical_len - extra_room;
++	ampdu_hdr->size = 0;
++	ampdu_hdr->ampdu_tid = ampdu_tid;
++	memset(ampdu_hdr->ssn, 0xFF, sizeof(ampdu_hdr->ssn));
++	ampdu_hdr->mpdu_num = 0;
++	return ampdu_skb;
++}
++
++bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	u32 ac = skb_get_queue_mapping(skb);
++	u32 hw_txqid = sc->tx.hw_txqid[ac];
++	return AMPDU_HCI_Q_EMPTY(sc->sh, hw_txqid);
++}
++
++static u32 _check_timeout(struct AMPDU_TID_st *ampdu_tid)
++{
++	u16 ssn, head_ssn, end_ssn;
++	unsigned long check_jiffies = jiffies;
++	u32 has_retry = 0;
++	head_ssn = ampdu_tid->ssv_baw_head;
++	ssn = head_ssn;
++	if (ssn == SSV_ILLEGAL_SN)
++		return 0;
++	end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
++	do {
++		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		struct SKB_info_st *skb_info;
++		unsigned long cur_jiffies;
++		unsigned long timeout_jiffies;
++		u32 delta_ms;
++		if (skb == NULL)
++			break;
++		skb_info = (SKB_info *) (skb->head);
++		cur_jiffies = jiffies;
++		timeout_jiffies =
++		    skb_info->aggr_timestamp +
++		    msecs_to_jiffies(BA_WAIT_TIMEOUT);
++		if ((skb_info->ampdu_tx_status != AMPDU_ST_SENT)
++		    || time_before(cur_jiffies, timeout_jiffies))
++			break;
++		delta_ms =
++		    jiffies_to_msecs(cur_jiffies - skb_info->aggr_timestamp);
++		prn_aggr_err("rt S%d-T%d-%d (%u)\n",
++			     ((struct ssv_sta_priv_data *)skb_info->sta->
++			      drv_priv)->sta_idx, ampdu_tid->tidno, ssn,
++			     delta_ms);
++		if (delta_ms > 1000) {
++			prn_aggr_err("Last checktime %lu - %lu = %u\n",
++				     check_jiffies, ampdu_tid->timestamp,
++				     jiffies_to_msecs(check_jiffies -
++						      ampdu_tid->timestamp));
++		}
++		has_retry += _mark_skb_retry(skb_info, skb);
++		INC_PKT_SN(ssn);
++	} while (ssn != end_ssn);
++	ampdu_tid->timestamp = check_jiffies;
++	return has_retry;
++}
++
++void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct AMPDU_TID_st *cur_AMPDU_TID;
++	if (!list_empty(&sc->tx.ampdu_tx_que)) {
++		list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
++					list) {
++			u32 has_retry;
++			if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION)
++				continue;
++			has_retry = _check_timeout(cur_AMPDU_TID);
++			if (has_retry) {
++				_collect_retry_frames(cur_AMPDU_TID);
++				ssv6200_ampdu_send_retry(sc->hw, cur_AMPDU_TID,
++							 &cur_AMPDU_TID->
++							 retry_queue, true);
++			}
++		}
++	}
++}
++
++void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++	struct sk_buff *mpdu;
++	unsigned long cur_jiffies = jiffies;
++	int i;
++	SKB_info *mpdu_skb_info;
++	u16 ssn;
++	if (ampdu_hdr->ampdu_tid->state != AMPDU_STATE_OPERATION)
++		return;
++	spin_lock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
++	for (i = 0; i < ampdu_hdr->mpdu_num; i++) {
++		ssn = ampdu_hdr->ssn[i];
++		mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
++		if (mpdu == NULL) {
++			dev_err(sc->dev, "T%d-%d is a NULL MPDU.\n",
++				ampdu_hdr->ampdu_tid->tidno, ssn);
++			continue;
++		}
++		if (ampdu_skb_ssn(mpdu) != ssn) {
++			dev_err(sc->dev, "T%d-%d does not match %d MPDU.\n",
++				ampdu_hdr->ampdu_tid->tidno, ssn,
++				ampdu_skb_ssn(mpdu));
++			continue;
++		}
++		mpdu_skb_info = (SKB_info *) (mpdu->head);
++		mpdu_skb_info->aggr_timestamp = cur_jiffies;
++		mpdu_skb_info->ampdu_tx_status = AMPDU_ST_SENT;
++	}
++	spin_unlock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.h b/drivers/net/wireless/ssv6051/smac/ampdu.h
+new file mode 100644
+index 000000000000..faa61c4f9297
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ampdu.h
+@@ -0,0 +1,215 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _AMPDU_H_
++#define _AMPDU_H_
++#include <linux/version.h>
++#include <ssv6200_common.h>
++#define Enable_ampdu_debug_log (0)
++#define Enable_AMPDU_Live_Time (0)
++#define Enable_HW_AUTO_CRC_32 (1)
++#define Enable_AMPDU_Rx (1)
++#define Enable_AMPDU_Tx (1)
++#define Enable_AMPDU_FW_Retry (1)
++#define Enable_AMPDU_delay_work (1)
++#define USE_FLUSH_RETRY
++#define USE_AMPDU_TX_STATUS_ARRAY
++#define SSV_AMPDU_FLOW_CONTROL
++#define AMPDU_CHECK_SKB_SEQNO
++#define REPORT_TX_STATUS_DIRECTLY
++#define SSV_AMPDU_aggr_num_max MAX_AGGR_NUM
++#define SSV_AMPDU_seq_num_max (4096)
++#define SSV_AMPDU_retry_counter_max (3)
++#define SSV_AMPDU_tx_group_id_max (64)
++#define SSV_AMPDU_MAX_SSN (4096)
++#define SSV_AMPDU_BA_WINDOW_SIZE (64)
++#define SSV_AMPDU_WINDOW_SIZE (64)
++#define SSV_GET_MAX_AMPDU_SIZE(sh) (((sh)->tx_page_available/(sh)->ampdu_divider) << HW_MMU_PAGE_SHIFT)
++#define SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND (64)
++#define SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND (48)
++#define SSV_AMPDU_timer_period (50)
++#define SSV_AMPDU_TX_TIME_THRESHOLD (50)
++#define SSV_AMPDU_MPDU_LIVE_TIME (SSV_AMPDU_retry_counter_max*8)
++#define SSV_AMPDU_BA_TIME (50)
++#define SSV_ILLEGAL_SN (0xffff)
++#define AMPDU_BUFFER_SIZE (32*1024)
++#define AMPDU_SIGNATURE (0x4E)
++#define AMPDU_DELIMITER_LEN (4)
++#define AMPDU_FCS_LEN (4)
++#define AMPDU_RESERVED_LEN (3)
++#define AMPDU_TX_NAV_MCS_567 (48)
++#define SSV_SEQ_NUM_SHIFT (4)
++#define SSV_RETRY_BIT_SHIFT (11)
++#define IEEE80211_SEQ_SEQ_SHIFT (4)
++#define IEEE80211_AMPDU_BA_LEN (34)
++#define SSV6200_AMPDU_TRIGGER_INDEX 0
++#define SSV_SN_STATUS_Release (0xaa)
++#define SSV_SN_STATUS_Retry (0xbb)
++#define SSV_SN_STATUS_Wait_BA (0xcc)
++#define SSV_SN_STATUS_Discard (0xdd)
++#define AMPDU_HCI_SEND_TAIL_WITH_FLOWCTRL (0)
++#define AMPDU_HCI_SEND_HEAD_WITH_FLOWCTRL (1)
++#define AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL (2)
++#define AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL (3)
++#define SSV_BAR_CTRL_ACK_POLICY_NORMAL (0x0000)
++#define SSV_BAR_CTRL_CBMTID_COMPRESSED_BA (0x0004)
++#define SSV_BAR_CTRL_TID_INFO_SHIFT (12)
++#define AMPDU_STATE_START BIT(0)
++#define AMPDU_STATE_OPERATION BIT(1)
++#define AMPDU_STATE_STOP BIT(2)
++typedef enum {
++	AMPDU_REKEY_PAUSE_STOP = 0,
++	AMPDU_REKEY_PAUSE_START,
++	AMPDU_REKEY_PAUSE_ONGOING,
++	AMPDU_REKEY_PAUSE_DEFER,
++	AMPDU_REKEY_PAUSE_HWKEY_SYNC,
++} AMPDU_REKEY_PAUSE_STATE;
++#define SSV_a_minus_b_in_c(a,b,c) (((a)>=(b))?((a)-(b)):((c)-(b)+(a)))
++#define SSV_AMPDU_SN_a_minus_b(a,b) (SSV_a_minus_b_in_c((a), (b), SSV_AMPDU_seq_num_max))
++#define AMPDU_HCI_SEND(_sh,_sk,_q,_flag) (_sh)->hci.hci_ops->hci_tx((_sk), (_q), (_flag))
++#define AMPDU_HCI_Q_EMPTY(_sh,_q) (_sh)->hci.hci_ops->hci_txq_empty((_q))
++struct ampdu_hdr_st {
++	u32 first_sn;
++	struct sk_buff_head mpdu_q;
++	u32 max_size;
++	u32 size;
++	struct AMPDU_TID_st *ampdu_tid;
++	u16 ssn[MAX_AGGR_NUM];
++	u16 mpdu_num;
++	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
++	struct ieee80211_sta *sta;
++};
++enum AMPDU_TX_STATUS_E {
++	AMPDU_ST_NON_AMPDU,
++	AMPDU_ST_AGGREGATED,
++	AMPDU_ST_SENT,
++	AMPDU_ST_RETRY,
++	AMPDU_ST_DROPPED,
++	AMPDU_ST_DONE,
++};
++typedef struct AMPDU_MIB_st {
++	u32 ampdu_mib_mpdu_counter;
++	u32 ampdu_mib_retry_counter;
++	u32 ampdu_mib_ampdu_counter;
++	u32 ampdu_mib_aggr_retry_counter;
++	u32 ampdu_mib_bar_counter;
++	u32 ampdu_mib_discard_counter;
++	u32 ampdu_mib_total_BA_counter;
++	u32 ampdu_mib_BA_counter;
++	u32 ampdu_mib_pass_counter;
++	u32 ampdu_mib_dist[SSV_AMPDU_aggr_num_max + 1];
++} AMPDU_MIB;
++typedef struct AMPDU_TID_st {
++	struct list_head list;
++	volatile unsigned long timestamp;
++	u32 tidno;
++	u16 ac;
++	struct ieee80211_sta *sta;
++	u16 ssv_baw_size;
++	u8 agg_num_max;
++	u8 state;
++#ifdef AMPDU_CHECK_SKB_SEQNO
++	u32 last_seqno;
++#endif
++	struct sk_buff_head ampdu_skb_tx_queue;
++	spinlock_t ampdu_skb_tx_queue_lock;
++	struct sk_buff_head retry_queue;
++	struct sk_buff_head release_queue;
++	struct sk_buff *aggr_pkts[SSV_AMPDU_BA_WINDOW_SIZE];
++	volatile u32 aggr_pkt_num;
++	volatile u16 ssv_baw_head;
++	spinlock_t pkt_array_lock;
++	struct sk_buff *cur_ampdu_pkt;
++	struct sk_buff_head early_aggr_ampdu_q;
++	u32 early_aggr_skb_num;
++	struct sk_buff_head ampdu_skb_wait_encry_queue;
++	u32 ampdu_mib_reset;
++	struct AMPDU_MIB_st mib;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++	struct sk_buff_head ba_q;
++#endif
++} AMPDU_TID, *p_AMPDU_TID;
++typedef struct AMPDU_DELIMITER_st {
++	u16 reserved:4;
++	u16 length:12;
++	u8 crc;
++	u8 signature;
++} AMPDU_DELIMITER, *p_AMPDU_DELIMITER;
++typedef struct AMPDU_BLOCKACK_st {
++	u16 frame_control;
++	u16 duration;
++	u8 ra_addr[ETH_ALEN];
++	u8 ta_addr[ETH_ALEN];
++	u16 BA_ack_ploicy:1;
++	u16 multi_tid:1;
++	u16 compress_bitmap:1;
++	u16 reserved:9;
++	u16 tid_info:4;
++	u16 BA_fragment_sn:4;
++	u16 BA_ssn:12;
++	u32 BA_sn_bit_map[2];
++} AMPDU_BLOCKACK, *p_AMPDU_BLOCKACK;
++struct ssv_bar {
++	unsigned short frame_control;
++	unsigned short duration;
++	unsigned char ra[6];
++	unsigned char ta[6];
++	unsigned short control;
++	unsigned short start_seq_num;
++} __packed;
++#if Enable_ampdu_debug_log
++#define ampdu_db_log(format, args...) printk("~~~ampdu [%s:%d] "format, __FUNCTION__, __LINE__, ##args)
++#define ampdu_db_log_simple(format, args...) printk(format, ##args)
++#else
++#define ampdu_db_log(...) do {} while (0)
++#define ampdu_db_log_simple(...) do {} while (0)
++#endif
++#if Enable_AMPDU_delay_work
++void ssv6200_ampdu_delayed_work_callback_func(struct work_struct *work);
++#else
++void ssv6200_ampdu_timer_callback_func(unsigned long data);
++#endif
++void ssv6200_ampdu_init(struct ieee80211_hw *hw);
++void ssv6200_ampdu_deinit(struct ieee80211_hw *hw);
++void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw);
++void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
++			    struct ieee80211_hw *hw, u16 * ssn);
++void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
++				struct ieee80211_hw *hw, u8 buffer_size);
++void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
++			   struct ieee80211_hw *hw);
++bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
++u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw);
++void ssv6200_ampdu_timeout_tx(struct ieee80211_hw *hw);
++struct cfg_host_event;
++void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
++void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
++void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
++				   struct sk_buff *skb);
++void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
++			      struct ieee80211_sta *sta);
++void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw);
++void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw);
++void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu);
++extern void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work);
++extern void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work);
++void ssv6xxx_mib_reset(struct ieee80211_hw *hw);
++ssize_t ssv6xxx_mib_dump(struct ieee80211_hw *hw, char *mib_str,
++			 ssize_t length);
++void encry_work(struct work_struct *work);
++void sync_hw_key_work(struct work_struct *work);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ap.c b/drivers/net/wireless/ssv6051/smac/ap.c
+new file mode 100644
+index 000000000000..0f2ba6a31a05
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ap.c
+@@ -0,0 +1,598 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <linux/sched.h>
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "lib.h"
++#include "dev.h"
++#include "ap.h"
++#include "ssv_rc_common.h"
++#include "ssv_rc.h"
++int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
++#define IS_EQUAL(a,b) ( (a) == (b) )
++#define SET_BIT(v,b) ( (v) |= (0x01<<b) )
++#define CLEAR_BIT(v,b) ( (v) &= ~(0x01<<b) )
++#define IS_BIT_SET(v,b) ( (v) & (0x01<<(b) ) )
++#define PBUF_BASE_ADDR 0x80000000
++#define PBUF_ADDR_SHIFT 16
++#define PBUF_MapPkttoID(_PKT) (((u32)_PKT&0x0FFF0000)>>PBUF_ADDR_SHIFT)
++#define PBUF_MapIDtoPkt(_ID) (PBUF_BASE_ADDR|((_ID)<<PBUF_ADDR_SHIFT))
++#define SSV6xxx_BEACON_MAX_ALLOCATE_CNT 10
++#define MTX_BCN_PKTID_CH_LOCK_SHIFT MTX_BCN_PKTID_CH_LOCK_SFT
++#define MTX_BCN_CFG_VLD_SHIFT MTX_BCN_CFG_VLD_SFT
++#define MTX_BCN_CFG_VLD_MASK MTX_BCN_CFG_VLD_MSK
++#define AUTO_BCN_ONGOING_MASK MTX_AUTO_BCN_ONGOING_MSK
++#define AUTO_BCN_ONGOING_SHIFT MTX_AUTO_BCN_ONGOING_SFT
++#define MTX_BCN_TIMER_EN_SHIFT MTX_BCN_TIMER_EN_SFT
++#define MTX_TSF_TIMER_EN_SHIFT MTX_TSF_TIMER_EN_SFT
++#define MTX_HALT_MNG_UNTIL_DTIM_SHIFT MTX_HALT_MNG_UNTIL_DTIM_SFT
++#define MTX_BCN_ENABLE_MASK (MTX_BCN_TIMER_EN_I_MSK)
++#define MTX_BCN_PERIOD_SHIFT MTX_BCN_PERIOD_SFT
++#define MTX_DTIM_NUM_SHIFT MTX_DTIM_NUM_SFT
++#define MTX_DTIM_OFST0 MTX_DTIM_OFST0_SFT
++enum ssv6xxx_beacon_type {
++	SSV6xxx_BEACON_0,
++	SSV6xxx_BEACON_1,
++};
++static const u32 ssv6xxx_beacon_adr[] = {
++	ADR_MTX_BCN_CFG0,
++	ADR_MTX_BCN_CFG1,
++};
++
++void ssv6xxx_beacon_reg_lock(struct ssv_softc *sc, bool block)
++{
++	u32 val;
++	val = block << MTX_BCN_PKTID_CH_LOCK_SHIFT;
++#ifdef BEACON_DEBUG
++	printk("ssv6xxx_beacon_reg_lock   val[0x:%08x]\n ", val);
++#endif
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_MISC, val);
++}
++
++void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
++			     u8 dtim_cnt)
++{
++	u32 val;
++	if (beacon_interval == 0)
++		beacon_interval = 100;
++#ifdef BEACON_DEBUG
++	printk("[A] BSS_CHANGED_BEACON_INT beacon_int[%d] dtim_cnt[%d]\n",
++	       beacon_interval, (dtim_cnt));
++#endif
++	val =
++	    (beacon_interval << MTX_BCN_PERIOD_SHIFT) | (dtim_cnt <<
++							 MTX_DTIM_NUM_SHIFT);
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_PRD, val);
++}
++
++bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable)
++{
++	u32 regval = 0;
++	int ret = 0;
++	if (bEnable && !sc->beacon_usage) {
++		printk
++		    ("[A] Reject to set beacon!!!.        ssv6xxx_beacon_enable bEnable[%d] sc->beacon_usage[%d]\n",
++		     bEnable, sc->beacon_usage);
++		sc->enable_beacon = BEACON_WAITING_ENABLED;
++		return 0;
++	}
++	if ((bEnable && (BEACON_ENABLED & sc->enable_beacon)) ||
++	    (!bEnable && !sc->enable_beacon)) {
++		printk
++		    ("[A] ssv6xxx_beacon_enable bEnable[%d] and sc->enable_beacon[%d] are the same. no need to execute.\n",
++		     bEnable, sc->enable_beacon);
++		if (bEnable) {
++			printk("        Ignore enable beacon cmd!!!!\n");
++			return 0;
++		}
++	}
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
++#endif
++	regval &= MTX_BCN_ENABLE_MASK;
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
++#endif
++	regval |= (bEnable << MTX_BCN_TIMER_EN_SHIFT);
++	ret = SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
++#endif
++	sc->enable_beacon = (bEnable == true) ? BEACON_ENABLED : 0;
++	return ret;
++}
++
++int ssv6xxx_beacon_fill_content(struct ssv_softc *sc, u32 regaddr, u8 * beacon,
++				int size)
++{
++	u32 i, val;
++	u32 *ptr = (u32 *) beacon;
++	size = size / 4;
++	for (i = 0; i < size; i++) {
++		val = (u32) (*(ptr + i));
++#ifdef BEACON_DEBUG
++		printk("[%08x] ", val);
++#endif
++		SMAC_REG_WRITE(sc->sh, regaddr + i * 4, val);
++	}
++#ifdef BEACON_DEBUG
++	printk("\n");
++#endif
++	return 0;
++}
++
++void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc,
++				 struct sk_buff *beacon_skb)
++{
++	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(beacon_skb);
++	struct ssv6200_tx_desc *tx_desc;
++	u16 pb_offset = TXPB_OFFSET;
++	struct ssv_rate_info ssv_rate;
++	skb_push(beacon_skb, pb_offset);
++	tx_desc = (struct ssv6200_tx_desc *)beacon_skb->data;
++	memset(tx_desc, 0, pb_offset);
++	ssv6xxx_rc_hw_rate_idx(sc, tx_info, &ssv_rate);
++	tx_desc->len = beacon_skb->len - pb_offset;
++	tx_desc->c_type = M2_TXREQ;
++	tx_desc->f80211 = 1;
++	tx_desc->ack_policy = 1;
++	tx_desc->hdr_offset = pb_offset;
++	tx_desc->hdr_len = 24;
++	tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
++	tx_desc->crate_idx = ssv_rate.crate_hw_idx;
++	tx_desc->drate_idx = ssv_rate.drate_hw_idx;
++	skb_put(beacon_skb, 4);
++}
++
++inline enum ssv6xxx_beacon_type ssv6xxx_beacon_get_valid_reg(struct ssv_softc
++							     *sc)
++{
++	u32 regval = 0;
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
++	regval &= MTX_BCN_CFG_VLD_MASK;
++	regval = regval >> MTX_BCN_CFG_VLD_SHIFT;
++	if (regval == 0x2 || regval == 0x0)
++		return SSV6xxx_BEACON_0;
++	else if (regval == 0x1)
++		return SSV6xxx_BEACON_1;
++	else
++		printk("=============>ERROR!!drv_bcn_reg_available\n");
++	return SSV6xxx_BEACON_0;
++}
++
++bool ssv6xxx_beacon_set(struct ssv_softc *sc, struct sk_buff *beacon_skb,
++			int dtim_offset)
++{
++	u32 reg_tx_beacon_adr = ADR_MTX_BCN_CFG0;
++	enum ssv6xxx_beacon_type avl_bcn_type = SSV6xxx_BEACON_0;
++	bool ret = true;
++	int val;
++	ssv6xxx_beacon_reg_lock(sc, 1);
++	avl_bcn_type = ssv6xxx_beacon_get_valid_reg(sc);
++	if (avl_bcn_type == SSV6xxx_BEACON_1)
++		reg_tx_beacon_adr = ADR_MTX_BCN_CFG1;
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_set avl_bcn_type[%d]\n", avl_bcn_type);
++#endif
++	do {
++		if (IS_BIT_SET(sc->beacon_usage, avl_bcn_type)) {
++#ifdef BEACON_DEBUG
++			printk
++			    ("[A] beacon has already been set old len[%d] new len[%d]\n",
++			     sc->beacon_info[avl_bcn_type].len,
++			     beacon_skb->len);
++#endif
++			if (sc->beacon_info[avl_bcn_type].len >=
++			    beacon_skb->len) {
++				break;
++			} else {
++				if (false ==
++				    ssv6xxx_pbuf_free(sc,
++						      sc->
++						      beacon_info[avl_bcn_type].
++						      pubf_addr)) {
++#ifdef BEACON_DEBUG
++					printk
++					    ("=============>ERROR!!Intend to allcoate beacon from ASIC fail.\n");
++#endif
++					ret = false;
++					goto out;
++				}
++				CLEAR_BIT(sc->beacon_usage, avl_bcn_type);
++			}
++		}
++		sc->beacon_info[avl_bcn_type].pubf_addr =
++		    ssv6xxx_pbuf_alloc(sc, beacon_skb->len, TX_BUF);
++		sc->beacon_info[avl_bcn_type].len = beacon_skb->len;
++		if (sc->beacon_info[avl_bcn_type].pubf_addr == 0) {
++			ret = false;
++			goto out;
++		}
++		SET_BIT(sc->beacon_usage, avl_bcn_type);
++#ifdef BEACON_DEBUG
++		printk
++		    ("[A] beacon type[%d] usage[%d] allocate new beacon addr[%08x] \n",
++		     avl_bcn_type, sc->beacon_usage,
++		     sc->beacon_info[avl_bcn_type].pubf_addr);
++#endif
++	} while (0);
++	ssv6xxx_beacon_fill_content(sc, sc->beacon_info[avl_bcn_type].pubf_addr,
++				    beacon_skb->data, beacon_skb->len);
++	val =
++	    (PBUF_MapPkttoID(sc->beacon_info[avl_bcn_type].pubf_addr)) |
++	    (dtim_offset << MTX_DTIM_OFST0);
++	SMAC_REG_WRITE(sc->sh, reg_tx_beacon_adr, val);
++#ifdef BEACON_DEBUG
++	printk("[A] update to register reg_tx_beacon_adr[%08x] val[%08x]\n",
++	       reg_tx_beacon_adr, val);
++#endif
++ out:
++	ssv6xxx_beacon_reg_lock(sc, 0);
++	if (sc->beacon_usage && (sc->enable_beacon & BEACON_WAITING_ENABLED)) {
++		printk("[A] enable beacon for BEACON_WAITING_ENABLED flags\n");
++		ssv6xxx_beacon_enable(sc, true);
++	}
++	return ret;
++}
++
++inline bool ssv6xxx_auto_bcn_ongoing(struct ssv_softc *sc)
++{
++	u32 regval;
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
++	return ((AUTO_BCN_ONGOING_MASK & regval) >> AUTO_BCN_ONGOING_SHIFT);
++}
++
++void ssv6xxx_beacon_release(struct ssv_softc *sc)
++{
++	int cnt = 10;
++	printk("[A] ssv6xxx_beacon_release Enter\n");
++	cancel_work_sync(&sc->set_tim_work);
++	do {
++		if (ssv6xxx_auto_bcn_ongoing(sc))
++			ssv6xxx_beacon_enable(sc, false);
++		else
++			break;
++		cnt--;
++		if (cnt <= 0)
++			break;
++	} while (1);
++	if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_0)) {
++		ssv6xxx_pbuf_free(sc,
++				  sc->beacon_info[SSV6xxx_BEACON_0].pubf_addr);
++		CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_0);
++	}
++	if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_1)) {
++		ssv6xxx_pbuf_free(sc,
++				  sc->beacon_info[SSV6xxx_BEACON_1].pubf_addr);
++		CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_1);
++	}
++	sc->enable_beacon = 0;
++	if (sc->beacon_buf) {
++		dev_kfree_skb_any(sc->beacon_buf);
++		sc->beacon_buf = NULL;
++	}
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_release leave\n");
++#endif
++}
++
++void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, bool aid0_bit_set)
++{
++	struct sk_buff *skb;
++	struct sk_buff *old_skb = NULL;
++	u16 tim_offset, tim_length;
++	if (sc == NULL || hw == NULL || vif == NULL) {
++		printk("[Error]........ssv6xxx_beacon_change input error\n");
++		return;
++	}
++	do {
++		skb = ieee80211_beacon_get_tim(hw, vif,
++					       &tim_offset, &tim_length, 0);
++		if (skb == NULL) {
++			printk("[Error]........skb is NULL\n");
++			break;
++		}
++		if (tim_offset && tim_length >= 6) {
++			skb->data[tim_offset + 2] = 0;
++			if (aid0_bit_set)
++				skb->data[tim_offset + 4] |= 1;
++			else
++				skb->data[tim_offset + 4] &= ~1;
++		}
++#ifdef BEACON_DEBUG
++		printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
++		       tim_offset);
++#endif
++		ssv6xxx_beacon_fill_tx_desc(sc, skb);
++#ifdef BEACON_DEBUG
++		printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
++		       tim_offset);
++#endif
++		if (sc->beacon_buf) {
++			if (memcmp
++			    (sc->beacon_buf->data, skb->data,
++			     (skb->len - FCS_LEN)) == 0) {
++				old_skb = skb;
++				break;
++			} else {
++				old_skb = sc->beacon_buf;
++				sc->beacon_buf = skb;
++			}
++		} else {
++			sc->beacon_buf = skb;
++		}
++		tim_offset += 2;
++		if (ssv6xxx_beacon_set(sc, skb, tim_offset)) {
++			u8 dtim_cnt = vif->bss_conf.dtim_period - 1;
++			if (sc->beacon_dtim_cnt != dtim_cnt) {
++				sc->beacon_dtim_cnt = dtim_cnt;
++#ifdef BEACON_DEBUG
++				printk("[A] beacon_dtim_cnt [%d]\n",
++				       sc->beacon_dtim_cnt);
++#endif
++				ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
++							sc->beacon_dtim_cnt);
++			}
++		}
++	} while (0);
++	if (old_skb)
++		dev_kfree_skb_any(old_skb);
++}
++
++void ssv6200_set_tim_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, set_tim_work);
++#ifdef BROADCAST_DEBUG
++	printk("%s() enter\n", __FUNCTION__);
++#endif
++	ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
++#ifdef BROADCAST_DEBUG
++	printk("%s() leave\n", __FUNCTION__);
++#endif
++}
++
++int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq)
++{
++	u32 len;
++	unsigned long flags;
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	len = bcast_txq->cur_qsize;
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++	return len;
++}
++
++struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
++				      u8 * remain_len)
++{
++	struct sk_buff *skb = NULL;
++	unsigned long flags;
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	if (bcast_txq->cur_qsize) {
++		bcast_txq->cur_qsize--;
++		if (remain_len)
++			*remain_len = bcast_txq->cur_qsize;
++		skb = __skb_dequeue(&bcast_txq->qhead);
++	}
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++	return skb;
++}
++
++int ssv6200_bcast_enqueue(struct ssv_softc *sc,
++			  struct ssv6xxx_bcast_txq *bcast_txq,
++			  struct sk_buff *skb)
++{
++	unsigned long flags;
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	if (bcast_txq->cur_qsize >= SSV6200_MAX_BCAST_QUEUE_LEN) {
++		struct sk_buff *old_skb;
++		old_skb = __skb_dequeue(&bcast_txq->qhead);
++		bcast_txq->cur_qsize--;
++		ssv6xxx_txbuf_free_skb(old_skb, (void *)sc);
++		printk("[B] ssv6200_bcast_enqueue - remove oldest queue\n");
++	}
++	__skb_queue_tail(&bcast_txq->qhead, skb);
++	bcast_txq->cur_qsize++;
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++	return bcast_txq->cur_qsize;
++}
++
++void ssv6200_bcast_flush(struct ssv_softc *sc,
++			 struct ssv6xxx_bcast_txq *bcast_txq)
++{
++	struct sk_buff *skb;
++	unsigned long flags;
++#ifdef BCAST_DEBUG
++	printk("ssv6200_bcast_flush\n");
++#endif
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	while (bcast_txq->cur_qsize > 0) {
++		skb = __skb_dequeue(&bcast_txq->qhead);
++		bcast_txq->cur_qsize--;
++		ssv6xxx_txbuf_free_skb(skb, (void *)sc);
++	}
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++}
++
++static int queue_block_cnt = 0;
++void ssv6200_bcast_tx_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, bcast_tx_work.work);
++	struct sk_buff *skb;
++	int i;
++	u8 remain_size;
++	unsigned long flags;
++	bool needtimer = true;
++	long tmo = sc->bcast_interval;
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	do {
++#ifdef BCAST_DEBUG
++		printk
++		    ("[B] bcast_timer: hw_mng_used[%d] HCI_TXQ_EMPTY[%d] bcast_queue_len[%d].....................\n",
++		     sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4),
++		     ssv6200_bcast_queue_len(&sc->bcast_txq));
++#endif
++		if (sc->hw_mng_used != 0 || false == HCI_TXQ_EMPTY(sc->sh, 4)) {
++#ifdef BCAST_DEBUG
++			printk
++			    ("HW queue still have frames insdide. skip this one hw_mng_used[%d] bEmptyTXQ4[%d]\n",
++			     sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4));
++#endif
++			queue_block_cnt++;
++			if (queue_block_cnt > 5) {
++				queue_block_cnt = 0;
++				ssv6200_bcast_flush(sc, &sc->bcast_txq);
++				needtimer = false;
++			}
++			break;
++		}
++		queue_block_cnt = 0;
++		for (i = 0; i < SSV6200_ID_MANAGER_QUEUE; i++) {
++			skb =
++			    ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
++			if (!skb) {
++				needtimer = false;
++				break;
++			}
++			if ((0 != remain_size) &&
++			    (SSV6200_ID_MANAGER_QUEUE - 1) != i) {
++				struct ieee80211_hdr *hdr;
++				struct ssv6200_tx_desc *tx_desc =
++				    (struct ssv6200_tx_desc *)skb->data;
++				hdr =
++				    (struct ieee80211_hdr *)((u8 *) tx_desc +
++							     tx_desc->
++							     hdr_offset);
++				hdr->frame_control |=
++				    cpu_to_le16(IEEE80211_FCTL_MOREDATA);
++			}
++#ifdef BCAST_DEBUG
++			printk("[B] bcast_timer:tx remain_size[%d] i[%d]\n",
++			       remain_size, i);
++#endif
++			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++			if (HCI_SEND(sc->sh, skb, 4) < 0) {
++				printk("bcast_timer send fail!!!!!!! \n");
++				ssv6xxx_txbuf_free_skb(skb, (void *)sc);
++				BUG_ON(1);
++			}
++			spin_lock_irqsave(&sc->ps_state_lock, flags);
++		}
++	} while (0);
++	if (needtimer) {
++#ifdef BCAST_DEBUG
++		printk
++		    ("[B] bcast_timer:need more timer to tx bcast frame time[%d]\n",
++		     sc->bcast_interval);
++#endif
++		queue_delayed_work(sc->config_wq, &sc->bcast_tx_work, tmo);
++	} else {
++#ifdef BCAST_DEBUG
++		printk("[B] bcast_timer: ssv6200_bcast_stop\n");
++#endif
++		ssv6200_bcast_stop(sc);
++	}
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++#ifdef BCAST_DEBUG
++	printk("[B] bcast_timer: leave.....................\n");
++#endif
++}
++
++void ssv6200_bcast_start_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, bcast_start_work);
++#ifdef BCAST_DEBUG
++	printk("[B] ssv6200_bcast_start_work==\n");
++#endif
++	sc->bcast_interval = (sc->beacon_dtim_cnt + 1) *
++	    (sc->beacon_interval + 20) * HZ / 1000;
++	if (!sc->aid0_bit_set) {
++		sc->aid0_bit_set = true;
++		ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
++		queue_delayed_work(sc->config_wq,
++				   &sc->bcast_tx_work, sc->bcast_interval);
++#ifdef BCAST_DEBUG
++		printk("[B] bcast_start_work: Modify timer to DTIM[%d]ms==\n",
++		       (sc->beacon_dtim_cnt + 1) * (sc->beacon_interval + 20));
++#endif
++	}
++}
++
++void ssv6200_bcast_stop_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, bcast_stop_work.work);
++	long tmo = HZ / 100;
++#ifdef BCAST_DEBUG
++	printk("[B] ssv6200_bcast_stop_work\n");
++#endif
++	if (sc->aid0_bit_set) {
++		if (0 == ssv6200_bcast_queue_len(&sc->bcast_txq)) {
++			cancel_delayed_work_sync(&sc->bcast_tx_work);
++			sc->aid0_bit_set = false;
++			ssv6xxx_beacon_change(sc, sc->hw,
++					      sc->ap_vif, sc->aid0_bit_set);
++#ifdef BCAST_DEBUG
++			printk("remove group bit in DTIM\n");
++#endif
++		} else {
++#ifdef BCAST_DEBUG
++			printk
++			    ("bcast_stop_work: bcast queue still have data. just modify timer to 10ms\n");
++#endif
++			queue_delayed_work(sc->config_wq,
++					   &sc->bcast_tx_work, tmo);
++		}
++	}
++}
++
++void ssv6200_bcast_stop(struct ssv_softc *sc)
++{
++	queue_delayed_work(sc->config_wq,
++			   &sc->bcast_stop_work,
++			   sc->beacon_interval * HZ / 1024);
++}
++
++void ssv6200_bcast_start(struct ssv_softc *sc)
++{
++	queue_work(sc->config_wq, &sc->bcast_start_work);
++}
++
++void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif)
++{
++	unsigned long flags;
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	priv_vif->sta_asleep_mask = 0;
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++	cancel_work_sync(&sc->bcast_start_work);
++	cancel_delayed_work_sync(&sc->bcast_stop_work);
++	ssv6200_bcast_flush(sc, &sc->bcast_txq);
++	cancel_delayed_work_sync(&sc->bcast_tx_work);
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ap.h b/drivers/net/wireless/ssv6051/smac/ap.h
+new file mode 100644
+index 000000000000..93b5275715b5
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ap.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _AP_H_
++#define _AP_H_
++#define BEACON_WAITING_ENABLED 1<<0
++#define BEACON_ENABLED 1<<1
++void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, bool aid0_bit_set);
++void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
++			     u8 dtim_cnt);
++bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable);
++void ssv6xxx_beacon_release(struct ssv_softc *sc);
++void ssv6200_set_tim_work(struct work_struct *work);
++void ssv6200_bcast_start_work(struct work_struct *work);
++void ssv6200_bcast_stop_work(struct work_struct *work);
++void ssv6200_bcast_tx_work(struct work_struct *work);
++int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
++struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
++				      u8 * remain_len);
++int ssv6200_bcast_enqueue(struct ssv_softc *sc,
++			  struct ssv6xxx_bcast_txq *bcast_txq,
++			  struct sk_buff *skb);
++void ssv6200_bcast_start(struct ssv_softc *sc);
++void ssv6200_bcast_stop(struct ssv_softc *sc);
++void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/dev.c b/drivers/net/wireless/ssv6051/smac/dev.c
+new file mode 100644
+index 000000000000..214e93fae460
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/dev.c
+@@ -0,0 +1,3881 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <linux/kthread.h>
++#include <linux/ktime.h>
++
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include <hci/hctrl.h>
++#include "linux_80211.h"
++#include "lib.h"
++#include "ssv_rc.h"
++#include "ssv_ht_rc.h"
++#include "dev.h"
++#include "ap.h"
++#include "init.h"
++#include "p2p.h"
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++#include "ssv6xxx_debugfs.h"
++#endif
++struct rssi_res_st rssi_res, *p_rssi_res;
++#define NO_USE_RXQ_LOCK
++#ifndef WLAN_CIPHER_SUITE_SMS4
++#define WLAN_CIPHER_SUITE_SMS4 0x00147201
++#endif
++#define MAX_TX_Q_LEN (64)
++#define LOW_TX_Q_LEN (MAX_TX_Q_LEN/2)
++static u16 bits_per_symbol[][2] = {
++	{26, 54},
++	{52, 108},
++	{78, 162},
++	{104, 216},
++	{156, 324},
++	{208, 432},
++	{234, 486},
++	{260, 540},
++};
++
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
++extern unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage);
++#endif
++struct ssv6xxx_calib_table {
++	u16 channel_id;
++	u32 rf_ctrl_N;
++	u32 rf_ctrl_F;
++	u16 rf_precision_default;
++};
++static void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
++			  spinlock_t * rx_q_lock);
++static u32 _process_tx_done(struct ssv_softc *sc);
++
++void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)args;
++	if (!skb)
++		return;
++	ieee80211_free_txskb(sc->hw, skb);
++}
++
++#define ADDRESS_OFFSET 16
++#define HW_ID_OFFSET 7
++#define CH0_FULL_MASK CH0_FULL_MSK
++#define MAX_FAIL_COUNT 100
++#define MAX_RETRY_COUNT 20
++inline bool ssv6xxx_mcu_input_full(struct ssv_softc *sc)
++{
++	u32 regval = 0;
++	SMAC_REG_READ(sc->sh, ADR_MCU_STATUS, &regval);
++	return CH0_FULL_MASK & regval;
++}
++
++u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type)
++{
++	u32 regval, pad;
++	int cnt = MAX_RETRY_COUNT;
++	int page_cnt =
++	    (size + ((1 << HW_MMU_PAGE_SHIFT) - 1)) >> HW_MMU_PAGE_SHIFT;
++	regval = 0;
++	mutex_lock(&sc->mem_mutex);
++	pad = size % 4;
++	size += pad;
++	do {
++		SMAC_REG_WRITE(sc->sh, ADR_WR_ALC, (size | (type << 16)));
++		SMAC_REG_READ(sc->sh, ADR_WR_ALC, &regval);
++		if (regval == 0) {
++			cnt--;
++			msleep(1);
++		} else
++			break;
++	} while (cnt);
++	if (type == TX_BUF) {
++		sc->sh->tx_page_available -= page_cnt;
++		sc->sh->page_count[PACKET_ADDR_2_ID(regval)] = page_cnt;
++	}
++	mutex_unlock(&sc->mem_mutex);
++	if (regval == 0)
++		dev_err(sc->dev,
++			"Failed to allocate packet buffer of %d bytes in %d type.",
++			size, type);
++	else {
++		dev_dbg(sc->dev,
++			"Allocated %d type packet buffer of size %d (%d) at address %x.\n",
++			type, size, page_cnt, regval);
++	}
++	return regval;
++}
++
++bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr)
++{
++	u32 regval = 0;
++	u16 failCount = 0;
++	u8 *p_tx_page_cnt = &sc->sh->page_count[PACKET_ADDR_2_ID(pbuf_addr)];
++	while (ssv6xxx_mcu_input_full(sc)) {
++		if (failCount++ < 1000)
++			continue;
++		dev_err(sc->dev, "Error in mailbox block after %d iterations\n", failCount);
++		return false;
++	}
++	mutex_lock(&sc->mem_mutex);
++	regval =
++	    ((M_ENG_TRASH_CAN << HW_ID_OFFSET) | (pbuf_addr >> ADDRESS_OFFSET));
++	SMAC_REG_WRITE(sc->sh, ADR_CH0_TRIG_1, regval);
++	if (*p_tx_page_cnt) {
++		sc->sh->tx_page_available += *p_tx_page_cnt;
++		*p_tx_page_cnt = 0;
++	}
++	mutex_unlock(&sc->mem_mutex);
++	return true;
++}
++
++static const struct ssv6xxx_calib_table vt_tbl[SSV6XXX_IQK_CFG_XTAL_MAX][14] = {
++	{
++	 {1, 0xB9, 0x89D89E, 3859},
++	 {2, 0xB9, 0xEC4EC5, 3867},
++	 {3, 0xBA, 0x4EC4EC, 3875},
++	 {4, 0xBA, 0xB13B14, 3883},
++	 {5, 0xBB, 0x13B13B, 3891},
++	 {6, 0xBB, 0x762762, 3899},
++	 {7, 0xBB, 0xD89D8A, 3907},
++	 {8, 0xBC, 0x3B13B1, 3915},
++	 {9, 0xBC, 0x9D89D9, 3923},
++	 {10, 0xBD, 0x000000, 3931},
++	 {11, 0xBD, 0x627627, 3939},
++	 {12, 0xBD, 0xC4EC4F, 3947},
++	 {13, 0xBE, 0x276276, 3955},
++	 {14, 0xBF, 0x13B13B, 3974},
++	 },
++	{
++	 {1, 0xf1, 0x333333, 3859},
++	 {2, 0xf1, 0xB33333, 3867},
++	 {3, 0xf2, 0x333333, 3875},
++	 {4, 0xf2, 0xB33333, 3883},
++	 {5, 0xf3, 0x333333, 3891},
++	 {6, 0xf3, 0xB33333, 3899},
++	 {7, 0xf4, 0x333333, 3907},
++	 {8, 0xf4, 0xB33333, 3915},
++	 {9, 0xf5, 0x333333, 3923},
++	 {10, 0xf5, 0xB33333, 3931},
++	 {11, 0xf6, 0x333333, 3939},
++	 {12, 0xf6, 0xB33333, 3947},
++	 {13, 0xf7, 0x333333, 3955},
++	 {14, 0xf8, 0x666666, 3974},
++	 },
++	{
++	 {1, 0xC9, 0x000000, 3859},
++	 {2, 0xC9, 0x6AAAAB, 3867},
++	 {3, 0xC9, 0xD55555, 3875},
++	 {4, 0xCA, 0x400000, 3883},
++	 {5, 0xCA, 0xAAAAAB, 3891},
++	 {6, 0xCB, 0x155555, 3899},
++	 {7, 0xCB, 0x800000, 3907},
++	 {8, 0xCB, 0xEAAAAB, 3915},
++	 {9, 0xCC, 0x555555, 3923},
++	 {10, 0xCC, 0xC00000, 3931},
++	 {11, 0xCD, 0x2AAAAB, 3939},
++	 {12, 0xCD, 0x955555, 3947},
++	 {13, 0xCE, 0x000000, 3955},
++	 {14, 0xCF, 0x000000, 3974},
++	 }
++};
++
++#define FAIL_MAX 100
++#define RETRY_MAX 20
++int ssv6xxx_set_channel(struct ssv_softc *sc, int ch)
++{
++	struct ssv_hw *sh = sc->sh;
++	int retry_cnt, fail_cnt = 0;
++	u32 regval;
++	int ret = -1;
++	int chidx;
++	bool chidx_vld = 0;
++	dev_dbg(sc->dev, "Setting channel to %d\n", ch);
++	if ((sh->cfg.chip_identity == SSV6051Z)
++	    || (sc->sh->cfg.chip_identity == SSV6051P)) {
++		if ((ch == 13) || (ch == 14)) {
++			if (sh->ipd_channel_touch == 0) {
++				for (chidx = 0; chidx < sh->ch_cfg_size;
++				     chidx++) {
++					SMAC_REG_WRITE(sh,
++						       sh->p_ch_cfg[chidx].
++						       reg_addr,
++						       sh->p_ch_cfg[chidx].
++						       ch13_14_value);
++				}
++				sh->ipd_channel_touch = 1;
++			}
++		} else {
++			if (sh->ipd_channel_touch) {
++				for (chidx = 0; chidx < sh->ch_cfg_size;
++				     chidx++) {
++					SMAC_REG_WRITE(sh,
++						       sh->p_ch_cfg[chidx].
++						       reg_addr,
++						       sh->p_ch_cfg[chidx].
++						       ch1_12_value);
++				}
++				sh->ipd_channel_touch = 0;
++			}
++		}
++	}
++	for (chidx = 0; chidx < 14; chidx++) {
++		if (vt_tbl[sh->cfg.crystal_type][chidx].channel_id == ch) {
++			chidx_vld = 1;
++			break;
++		}
++	}
++	if (chidx_vld == 0) {
++		dev_dbg(sc->dev, "%s(): fail! channel_id not found in vt_tbl\n",
++			__FUNCTION__);
++		goto exit;
++	}
++	if ((ret = ssv6xxx_rf_disable(sc->sh)) != 0)
++		goto exit;
++	do {
++		if ((sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M)
++		    || (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M)) {
++			if ((ret =
++			     SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
++					       (0x00 << 13),
++					       (0x01 << 13))) != 0)
++				break;
++		} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
++			if ((ret =
++			     SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
++					       (0x01 << 13),
++					       (0x01 << 13))) != 0)
++				break;
++		} else {
++			dev_warn(sc->dev, "Illegal crystal setting in ssv6xxx_set_channel\n");
++			BUG_ON(1);
++		}
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
++					     (0x01 << 19), (0x01 << 19))) != 0)
++			break;
++		regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_F;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_1,
++					     (regval << 0),
++					     (0x00ffffff << 0))) != 0)
++			break;
++		regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_N;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_2,
++					     (regval << 0),
++					     (0x07ff << 0))) != 0)
++			break;
++		if ((ret =
++		     SMAC_REG_READ(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
++				   &regval)) != 0)
++			break;
++		regval =
++		    vt_tbl[sh->cfg.crystal_type][chidx].rf_precision_default;
++		if ((ret =
++		     SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_II,
++				       (regval << 0), (0x1fff << 0))) != 0)
++			break;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
++					     (0x00 << 14), (0x01 << 14))) != 0)
++			break;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
++					     (0x01 << 14), (0x01 << 14))) != 0)
++			break;
++		retry_cnt = 0;
++		do {
++			mdelay(1);
++			if ((ret =
++			     SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1,
++					   &regval)) != 0)
++				break;
++			if (regval & 0x00000002) {
++				if ((ret =
++				     SMAC_REG_READ(sc->sh,
++						   ADR_READ_ONLY_FLAGS_2,
++						   &regval)) != 0)
++					break;
++				ret = ssv6xxx_rf_enable(sc->sh);
++				//dev_info(sc->dev, "Lock to channel %d ([0xce010098]=%x)!!\n", vt_tbl[sh->cfg.crystal_type][chidx].channel_id, regval);
++				sc->hw_chan = ch;
++				goto exit;
++			}
++			retry_cnt++;
++		}
++		while (retry_cnt < RETRY_MAX);
++		fail_cnt++;
++		dev_warn(sc->dev, "calibation fail after %d iterations\n", fail_cnt);
++	}
++	while ((fail_cnt < FAIL_MAX) && (ret == 0));
++ exit:
++	if (ch == 14 && regval == 0xff0) {
++		SMAC_IFC_RESET(sc->sh);
++		ssv6xxx_restart_hw(sc);
++	}
++	if (ch <= 7) {
++		if (sh->cfg.tx_power_index_1) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			regval |=
++			    (sh->cfg.tx_power_index_1 << RG_TX_GAIN_OFFSET_SFT);
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		} else if (sh->cfg.tx_power_index_2) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		}
++	} else {
++		if (sh->cfg.tx_power_index_2) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			regval |=
++			    (sh->cfg.tx_power_index_2 << RG_TX_GAIN_OFFSET_SFT);
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		} else if (sh->cfg.tx_power_index_1) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		}
++	}
++	return ret;
++}
++
++#ifdef CONFIG_SSV_SMARTLINK
++int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch)
++{
++	*pch = sc->hw_chan;
++	return 0;
++}
++
++int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept)
++{
++	u32 val = 0;
++	if (accept) {
++		val = 0x2;
++	} else {
++		val = 0x3;
++	}
++	SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB13, val);
++	return 0;
++}
++
++int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept)
++{
++	u32 val = 0;
++	SMAC_REG_READ(sc->sh, ADR_MRX_FLT_TB13, &val);
++	if (val == 0x2) {
++		*paccept = 1;
++	} else {
++		*paccept = 0;
++	}
++	return 0;
++}
++#endif
++int ssv6xxx_rf_enable(struct ssv_hw *sh)
++{
++	return SMAC_REG_SET_BITS(sh, 0xce010000, (0x02 << 12), (0x03 << 12)
++	    );
++}
++
++int ssv6xxx_rf_disable(struct ssv_hw *sh)
++{
++	return SMAC_REG_SET_BITS(sh, 0xce010000, (0x01 << 12), (0x03 << 12)
++	    );
++}
++
++int ssv6xxx_update_decision_table(struct ssv_softc *sc)
++{
++	int i;
++	for (i = 0; i < MAC_DECITBL1_SIZE; i++) {
++		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
++			       sc->mac_deci_tbl[i]);
++		SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
++				 sc->mac_deci_tbl[i]);
++	}
++	for (i = 0; i < MAC_DECITBL2_SIZE; i++) {
++		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
++			       sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
++		SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
++				 sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
++	}
++	return 0;
++}
++
++static int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht)
++{
++#define CTRL_FRAME_INDEX(fc) ((hdr->frame_control-IEEE80211_STYPE_BACK_REQ)>>4)
++	u16 fc, CTRL_FLEN[] = { 16, 16, 16, 16, 10, 10, 16, 16 };
++	int hdr_len = 24;
++	fc = hdr->frame_control;
++	if (ieee80211_is_ctl(fc))
++		hdr_len = CTRL_FLEN[CTRL_FRAME_INDEX(fc)];
++	else if (ieee80211_is_mgmt(fc)) {
++		if (ieee80211_has_order(fc))
++			hdr_len += ((is_ht == 1) ? 4 : 0);
++	} else {
++		if (ieee80211_has_a4(fc))
++			hdr_len += 6;
++		if (ieee80211_is_data_qos(fc)) {
++			hdr_len += 2;
++			if (ieee80211_has_order(hdr->frame_control) &&
++			    is_ht == true)
++				hdr_len += 4;
++		}
++	}
++	return hdr_len;
++}
++
++static u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width,
++			     int half_gi, bool is_gf)
++{
++	u32 nbits, nsymbits, duration, nsymbols;
++	int streams;
++	streams = 1;
++	nbits = (pktlen << 3) + OFDM_PLCP_BITS;
++	nsymbits = bits_per_symbol[rix % 8][width] * streams;
++	nsymbols = (nbits + nsymbits - 1) / nsymbits;
++	if (!half_gi)
++		duration = SYMBOL_TIME(nsymbols);
++	else {
++		if (!is_gf)
++			duration =
++			    DIV_ROUND_UP(SYMBOL_TIME_HALFGI(nsymbols), 4) << 2;
++		else
++			duration = SYMBOL_TIME_HALFGI(nsymbols);
++	}
++	duration +=
++	    L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams) +
++	    HT_SIGNAL_EXT;
++	if (is_gf)
++		duration -= 12;
++	duration += HT_SIFS_TIME;
++	return duration;
++}
++
++static u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps,
++				 u32 frameLen, bool shortPreamble)
++{
++	u32 bits_per_symbol, num_bits, num_symbols;
++	u32 phy_time, tx_time;
++	if (kbps == 0)
++		return 0;
++	switch (phy) {
++	case WLAN_RC_PHY_CCK:
++		phy_time = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
++		if (shortPreamble)
++			phy_time >>= 1;
++		num_bits = frameLen << 3;
++		tx_time = CCK_SIFS_TIME + phy_time + ((num_bits * 1000) / kbps);
++		break;
++	case WLAN_RC_PHY_OFDM:
++		bits_per_symbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
++		num_bits = OFDM_PLCP_BITS + (frameLen << 3);
++		num_symbols = DIV_ROUND_UP(num_bits, bits_per_symbol);
++		tx_time = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
++		    + (num_symbols * OFDM_SYMBOL_TIME);
++		break;
++	default:
++		pr_err("ssv6051: unknown phy %u\n", phy);
++		BUG_ON(1);
++		tx_time = 0;
++		break;
++	}
++	return tx_time;
++}
++
++static u32 ssv6xxx_set_frame_duration(struct ieee80211_tx_info *info,
++				      struct ssv_rate_info *ssv_rate, u16 len,
++				      struct ssv6200_tx_desc *tx_desc,
++				      struct fw_rc_retry_params *rc_params,
++				      struct ssv_softc *sc)
++{
++	struct ieee80211_tx_rate *tx_drate;
++	u32 frame_time = 0, ack_time = 0, rts_cts_nav = 0, frame_consume_time =
++	    0;
++	u32 l_length = 0, drate_kbps = 0, crate_kbps = 0;
++	bool ctrl_short_preamble = false, is_sgi, is_ht40;
++	bool is_ht, is_gf;
++	int d_phy, c_phy, nRCParams, mcsidx;
++	struct ssv_rate_ctrl *ssv_rc = NULL;
++	tx_drate = &info->control.rates[0];
++	is_sgi = !!(tx_drate->flags & IEEE80211_TX_RC_SHORT_GI);
++	is_ht40 = !!(tx_drate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
++	is_ht = !!(tx_drate->flags & IEEE80211_TX_RC_MCS);
++	is_gf = !!(tx_drate->flags & IEEE80211_TX_RC_GREEN_FIELD);
++	if ((info->control.short_preamble) ||
++	    (tx_drate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
++		ctrl_short_preamble = true;
++	pr_debug("mcs = %d, data rate idx=%d\n", tx_drate->idx, tx_drate[3].count);
++	for (nRCParams = 0; (nRCParams < SSV62XX_TX_MAX_RATES); nRCParams++) {
++		if ((rc_params == NULL) || (sc == NULL)) {
++			mcsidx = tx_drate->idx;
++			drate_kbps = ssv_rate->drate_kbps;
++			crate_kbps = ssv_rate->crate_kbps;
++		} else {
++			if (rc_params[nRCParams].count == 0) {
++				break;
++			}
++			ssv_rc = sc->rc;
++			mcsidx =
++			    (rc_params[nRCParams].drate -
++			     SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES;
++			drate_kbps =
++			    ssv_rc->rc_table[rc_params[nRCParams].drate].
++			    rate_kbps;
++			crate_kbps =
++			    ssv_rc->rc_table[rc_params[nRCParams].crate].
++			    rate_kbps;
++		}
++		if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
++			frame_time = ssv6xxx_ht_txtime(mcsidx,
++						       len, is_ht40, is_sgi,
++						       is_gf);
++			d_phy = 0;
++		} else {
++			if ((info->band == INDEX_80211_BAND_2GHZ) &&
++			    !(ssv_rate->d_flags & IEEE80211_RATE_ERP_G))
++				d_phy = WLAN_RC_PHY_CCK;
++			else
++				d_phy = WLAN_RC_PHY_OFDM;
++			frame_time = ssv6xxx_non_ht_txtime(d_phy, drate_kbps,
++							   len,
++							   ctrl_short_preamble);
++		}
++		if ((info->band == INDEX_80211_BAND_2GHZ) &&
++		    !(ssv_rate->c_flags & IEEE80211_RATE_ERP_G))
++			c_phy = WLAN_RC_PHY_CCK;
++		else
++			c_phy = WLAN_RC_PHY_OFDM;
++		if (tx_desc->unicast) {
++			if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++				ack_time = ssv6xxx_non_ht_txtime(c_phy,
++								 crate_kbps,
++								 BA_LEN,
++								 ctrl_short_preamble);
++			} else {
++				ack_time = ssv6xxx_non_ht_txtime(c_phy,
++								 crate_kbps,
++								 ACK_LEN,
++								 ctrl_short_preamble);
++			}
++		}
++		if (tx_desc->do_rts_cts & IEEE80211_TX_RC_USE_RTS_CTS) {
++			rts_cts_nav = frame_time;
++			rts_cts_nav += ack_time;
++			rts_cts_nav += ssv6xxx_non_ht_txtime(c_phy,
++							     crate_kbps,
++							     CTS_LEN,
++							     ctrl_short_preamble);
++			frame_consume_time = rts_cts_nav;
++			frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
++								    crate_kbps,
++								    RTS_LEN,
++								    ctrl_short_preamble);
++		} else if (tx_desc->
++			   do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
++			rts_cts_nav = frame_time;
++			rts_cts_nav += ack_time;
++			frame_consume_time = rts_cts_nav;
++			frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
++								    crate_kbps,
++								    CTS_LEN,
++								    ctrl_short_preamble);
++		} else {;
++		}
++		if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
++			l_length = frame_time - HT_SIFS_TIME;
++			l_length = ((l_length - (HT_SIGNAL_EXT + 20)) + 3) >> 2;
++			l_length += ((l_length << 1) - 3);
++		}
++		if ((rc_params == NULL) || (sc == NULL)) {
++			tx_desc->rts_cts_nav = rts_cts_nav;
++			tx_desc->frame_consume_time =
++			    (frame_consume_time >> 5) + 1;;
++			tx_desc->dl_length = l_length;
++			break;
++		} else {
++			rc_params[nRCParams].rts_cts_nav = rts_cts_nav;
++			rc_params[nRCParams].frame_consume_time =
++			    (frame_consume_time >> 5) + 1;
++			rc_params[nRCParams].dl_length = l_length;
++			if (nRCParams == 0) {
++				tx_desc->drate_idx = rc_params[nRCParams].drate;
++				tx_desc->crate_idx = rc_params[nRCParams].crate;
++				tx_desc->rts_cts_nav =
++				    rc_params[nRCParams].rts_cts_nav;
++				tx_desc->frame_consume_time =
++				    rc_params[nRCParams].frame_consume_time;
++				tx_desc->dl_length =
++				    rc_params[nRCParams].dl_length;
++			}
++		}
++	}
++	return ack_time;
++}
++
++static void ssv6200_hw_set_pair_type(struct ssv_hw *sh, u8 type)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp = (temp & PAIR_SCRT_I_MSK);
++	temp |= (type << PAIR_SCRT_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++	dev_dbg(sh->sc->dev, "==>%s: write cipher type %d into hw\n", __func__, type);
++}
++
++static u32 ssv6200_hw_get_pair_type(struct ssv_hw *sh)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp &= PAIR_SCRT_MSK;
++	temp = (temp >> PAIR_SCRT_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++	dev_dbg(sh->sc->dev, "==>%s: read cipher type %d from hw\n", __func__, temp);
++	return temp;
++}
++
++static void ssv6200_hw_set_group_type(struct ssv_hw *sh, u8 type)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp = temp & GRP_SCRT_I_MSK;
++	temp |= (type << GRP_SCRT_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++	dev_dbg(sh->sc->dev, "Set group key type %d\n", type);
++}
++
++void ssv6xxx_reset_sec_module(struct ssv_softc *sc)
++{
++	ssv6200_hw_set_group_type(sc->sh, ME_NONE);
++	ssv6200_hw_set_pair_type(sc->sh, ME_NONE);
++}
++
++static int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
++				struct ssv_sta_info *sta_info, int sta_idx,
++				int rx_hw_sec, int ops)
++{
++	int ret = 0;
++	int retry_cnt = 20;
++	struct sk_buff *skb = NULL;
++	struct cfg_host_cmd *host_cmd;
++	struct ssv6xxx_wsid_params *ptr;
++	dev_dbg(sc->dev, "cmd=%d for fw wsid list, wsid %d \n", ops, sta_idx);
++	skb =
++	    ssv_skb_alloc(HOST_CMD_HDR_LEN +
++			  sizeof(struct ssv6xxx_wsid_params));
++	if (skb == NULL || sta_info == NULL || sc == NULL)
++		return -1;
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_wsid_params);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_WSID_OP;
++	host_cmd->len = skb->data_len;
++	ptr = (struct ssv6xxx_wsid_params *)host_cmd->dat8;
++	ptr->cmd = ops;
++	ptr->hw_security = rx_hw_sec;
++	if ((ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE)
++	    && (ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE)) {
++		ptr->wsid_idx = (u8) (sta_idx - SSV_NUM_HW_STA);
++	} else {
++		ptr->wsid_idx = (u8) (sta_idx);
++	};
++	memcpy(&ptr->target_wsid, &sta->addr[0], 6);
++	while (((sc->sh->hci.hci_ops->hci_send_cmd(skb)) != 0) && (retry_cnt)) {
++		dev_dbg(sc->dev, "WSID cmd=%d retry=%d!!\n", ops, retry_cnt);
++		retry_cnt--;
++	}
++	dev_dbg(sc->dev, "%s: wsid_idx = %u\n", __FUNCTION__, ptr->wsid_idx);
++	ssv_skb_free(skb);
++	if (ops == SSV6XXX_WSID_OPS_ADD)
++		sta_info->hw_wsid = sta_idx;
++	return ret;
++}
++
++static void hw_crypto_key_clear(struct ieee80211_hw *hw, int index,
++				struct ieee80211_key_conf *key,
++				struct ssv_vif_priv_data *vif_priv,
++				struct ssv_sta_priv_data *sta_priv)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info = NULL;
++	if ((index == 0) && (sta_priv == NULL))
++		return;
++	if ((index < 0) || (index >= 4))
++		return;
++	if (index > 0) {
++		if (vif_priv)
++			vif_priv->group_key_idx = 0;
++		if (sta_priv)
++			sta_priv->group_key_idx = 0;
++	}
++	if (sta_priv) {
++		sta_info = &sc->sta_info[sta_priv->sta_idx];
++		if ((index == 0) && (sta_priv->has_hw_decrypt == true)
++		    && (sta_info->hw_wsid >= SSV_NUM_HW_STA)) {
++			hw_update_watch_wsid(sc, sta_info->sta, sta_info,
++					     sta_priv->sta_idx,
++					     SSV6XXX_WSID_SEC_PAIRWISE,
++					     SSV6XXX_WSID_OPS_DISABLE_CAPS);
++		}
++	}
++	if (vif_priv) {
++		if ((index != 0) && !list_empty(&vif_priv->sta_list)) {
++			struct ssv_sta_priv_data *sta_priv_iter;
++			list_for_each_entry(sta_priv_iter, &vif_priv->sta_list,
++					    list) {
++				if (((sta_priv_iter->sta_info->
++				      s_flags & STA_FLAG_VALID) == 0)
++				    || (sta_priv_iter->sta_info->hw_wsid <
++					SSV_NUM_HW_STA))
++					continue;
++				hw_update_watch_wsid(sc,
++						     sta_priv_iter->sta_info->
++						     sta,
++						     sta_priv_iter->sta_info,
++						     sta_priv_iter->sta_idx,
++						     SSV6XXX_WSID_SEC_GROUP,
++						     SSV6XXX_WSID_OPS_DISABLE_CAPS);
++			}
++		}
++	}
++}
++
++static void _set_wep_sw_crypto_key(struct ssv_softc *sc,
++				   struct ssv_vif_info *vif_info,
++				   struct ssv_sta_info *sta_info, void *param)
++{
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
++	sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
++	sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
++	sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
++}
++
++static void _set_wep_hw_crypto_pair_key(struct ssv_softc *sc,
++					struct ssv_vif_info *vif_info,
++					struct ssv_sta_info *sta_info,
++					void *param)
++{
++	int wsid = sta_info->hw_wsid;
++	struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
++	int address = 0;
++	int *pointer = NULL;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 sec_key_tbl = sec_key_tbl_base;
++	int i;
++	u8 *key = sram_key->sta_key[0].pair.key;
++	u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	if (wsid == (-1))
++		return;
++	sram_key->sta_key[wsid].pair_key_idx = 0;
++	sram_key->sta_key[wsid].group_key_idx = 0;
++	sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
++	sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
++	sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
++	sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
++	if (wsid != 0)
++		memcpy(sram_key->sta_key[wsid].pair.key, key, key_len);
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + wsid * sizeof(struct ssv6xxx_hw_sta_key);
++	address += (0x10000 * wsid);
++	pointer = (int *)&sram_key->sta_key[wsid];
++	for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
++		SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
++}
++
++static void _set_wep_hw_crypto_group_key(struct ssv_softc *sc,
++					 struct ssv_vif_info *vif_info,
++					 struct ssv_sta_info *sta_info,
++					 void *param)
++{
++	int wsid = sta_info->hw_wsid;
++	struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
++	int address = 0;
++	int *pointer = NULL;
++	u32 key_idx = sram_key->sta_key[0].pair_key_idx;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
++	u8 *key = sram_key->group_key[key_idx - 1].key;
++	u32 sec_key_tbl = sec_key_tbl_base;
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	if (wsid == (-1))
++		return;
++	if (wsid != 0) {
++		sram_key->sta_key[wsid].pair_key_idx = key_idx;
++		sram_key->sta_key[wsid].group_key_idx = key_idx;
++		sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
++		sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
++		sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
++		sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
++	}
++	if (wsid != 0)
++		memcpy(sram_key->group_key[key_idx - 1].key, key, key_len);
++	sec_key_tbl += (0x10000 * wsid);
++	address = sec_key_tbl + ((key_idx - 1) * sizeof(struct ssv6xxx_hw_key));
++	pointer = (int *)&sram_key->group_key[key_idx - 1];
++	{
++		int i;
++		for (i = 0; i < (sizeof(struct ssv6xxx_hw_key) / 4); i++)
++			SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
++	}
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
++	pointer = (int *)&sram_key->sta_key[wsid];
++	SMAC_REG_WRITE(sc->sh, address, *(pointer));
++}
++
++static int hw_crypto_key_write_wep(struct ieee80211_hw *hw,
++				   struct ieee80211_key_conf *key,
++				   u8 algorithm, struct ssv_vif_info *vif_info)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
++	if (key->keyidx == 0) {
++		ssv6xxx_foreach_vif_sta(sc, vif_info,
++					_set_wep_hw_crypto_pair_key, sramKey);
++	} else {
++		ssv6xxx_foreach_vif_sta(sc, vif_info,
++					_set_wep_hw_crypto_group_key, sramKey);
++	}
++	return 0;
++}
++
++static void _set_aes_tkip_hw_crypto_group_key(struct ssv_softc *sc,
++					      struct ssv_vif_info *vif_info,
++					      struct ssv_sta_info *sta_info,
++					      void *param)
++{
++	int wsid = sta_info->hw_wsid;
++	int j;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 sec_key_tbl = sec_key_tbl_base;
++	int address = 0;
++	int *pointer = 0;
++	struct ssv6xxx_hw_sec *sramKey = &(vif_info->sramKey);
++	int index = *(u8 *) param;
++	if (wsid == (-1))
++		return;
++	BUG_ON(index == 0);
++	sramKey->sta_key[wsid].group_key_idx = index;
++	sec_key_tbl += (0x10000 * wsid);
++	address = sec_key_tbl + ((index - 1) * sizeof(struct ssv6xxx_hw_key));
++	if (vif_info->vif_priv != NULL)
++		dev_dbg(sc->dev, "Write group key %d to VIF %d to %08X\n",
++			index, vif_info->vif_priv->vif_idx, address);
++	else
++		dev_err(sc->dev, "NULL VIF.\n");
++	pointer = (int *)&sramKey->group_key[index - 1];
++	for (j = 0; j < (sizeof(struct ssv6xxx_hw_key) / 4); j++)
++		SMAC_REG_WRITE(sc->sh, address + (j * 4), *(pointer++));
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
++	pointer = (int *)&sramKey->sta_key[wsid];
++	SMAC_REG_WRITE(sc->sh, address, *(pointer));
++	if (wsid >= SSV_NUM_HW_STA) {
++		hw_update_watch_wsid(sc, sta_info->sta, sta_info,
++				     wsid, SSV6XXX_WSID_SEC_GROUP,
++				     SSV6XXX_WSID_OPS_ENABLE_CAPS);
++	}
++}
++
++static int _write_pairwise_key_to_hw(struct ssv_softc *sc,
++				     int index, u8 algorithm,
++				     const u8 * key, int key_len,
++				     struct ieee80211_key_conf *keyconf,
++				     struct ssv_vif_priv_data *vif_priv,
++				     struct ssv_sta_priv_data *sta_priv)
++{
++	int i;
++	struct ssv6xxx_hw_sec *sramKey;
++	int address = 0;
++	int *pointer = NULL;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 sec_key_tbl;
++	int wsid = (-1);
++	if (sta_priv == NULL) {
++		dev_err(sc->dev, "Set pair-wise key with NULL STA.\n");
++		return -EOPNOTSUPP;
++	}
++	wsid = sta_priv->sta_info->hw_wsid;
++	if ((wsid < 0) || (wsid >= SSV_NUM_STA)) {
++		dev_err(sc->dev, "Set pair-wise key to invalid WSID %d.\n",
++			wsid);
++		return -EOPNOTSUPP;
++	}
++	dev_dbg(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid,
++		key_len);
++	sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
++	sramKey->sta_key[wsid].pair_key_idx = 0;
++	sramKey->sta_key[wsid].group_key_idx = vif_priv->group_key_idx;
++	memcpy(sramKey->sta_key[wsid].pair.key, key, key_len);
++	sec_key_tbl = sec_key_tbl_base;
++	sec_key_tbl += (0x10000 * wsid);
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + wsid * sizeof(struct ssv6xxx_hw_sta_key);
++	pointer = (int *)&sramKey->sta_key[wsid];
++	for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
++		SMAC_REG_WRITE(sc->sh, (address + (i * 4)), *(pointer++));
++	if (wsid >= SSV_NUM_HW_STA) {
++		hw_update_watch_wsid(sc, sta_priv->sta_info->sta,
++				     sta_priv->sta_info, sta_priv->sta_idx,
++				     SSV6XXX_WSID_SEC_PAIRWISE,
++				     SSV6XXX_WSID_OPS_ENABLE_CAPS);
++	}
++	return 0;
++}
++
++static int _write_group_key_to_hw(struct ssv_softc *sc,
++				  int index, u8 algorithm,
++				  const u8 * key, int key_len,
++				  struct ieee80211_key_conf *keyconf,
++				  struct ssv_vif_priv_data *vif_priv,
++				  struct ssv_sta_priv_data *sta_priv)
++{
++	struct ssv6xxx_hw_sec *sramKey;
++	int wsid = sta_priv ? sta_priv->sta_info->hw_wsid : (-1);
++	int ret = 0;
++	if (vif_priv == NULL) {
++		dev_err(sc->dev, "Setting group key to NULL VIF\n");
++		return -EOPNOTSUPP;
++	}
++	dev_dbg(sc->dev,
++		"Setting VIF %d group key %d of length %d to WSID %d.\n",
++		vif_priv->vif_idx, index, key_len, wsid);
++	sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
++	vif_priv->group_key_idx = index;
++	if (sta_priv)
++		sta_priv->group_key_idx = index;
++	memcpy(sramKey->group_key[index - 1].key, key, key_len);
++	WARN_ON(sc->vif_info[vif_priv->vif_idx].vif_priv == NULL);
++	ssv6xxx_foreach_vif_sta(sc, &sc->vif_info[vif_priv->vif_idx],
++				_set_aes_tkip_hw_crypto_group_key, &index);
++	ret = 0;
++	return ret;
++}
++
++static enum SSV_CIPHER_E _prepare_key(struct ieee80211_key_conf *key)
++{
++	enum SSV_CIPHER_E cipher;
++	switch (key->cipher) {
++	case WLAN_CIPHER_SUITE_WEP40:
++		cipher = SSV_CIPHER_WEP40;
++		break;
++	case WLAN_CIPHER_SUITE_WEP104:
++		cipher = SSV_CIPHER_WEP104;
++		break;
++	case WLAN_CIPHER_SUITE_TKIP:
++		key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
++		cipher = SSV_CIPHER_TKIP;
++		break;
++	case WLAN_CIPHER_SUITE_CCMP:
++		key->flags |=
++		    (IEEE80211_KEY_FLAG_SW_MGMT_TX |
++		     IEEE80211_KEY_FLAG_RX_MGMT);
++		cipher = SSV_CIPHER_CCMP;
++		break;
++	default:
++		cipher = SSV_CIPHER_INVALID;
++		break;
++	}
++	return cipher;
++}
++int _set_key_wep(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
++		 struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
++		 struct ieee80211_key_conf *key)
++{
++	int ret = 0;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	struct ssv6xxx_hw_sec *sram_key = &vif_info->sramKey;
++	sram_key->sta_key[0].pair_key_idx = key->keyidx;
++	sram_key->sta_key[0].group_key_idx = key->keyidx;
++	*(u16 *) & sram_key->sta_key[0].reserve[0] = key->keylen;
++	dev_dbg(sc->dev, "Set WEP %02X %02X %02X %02X %02X %02X %02X %02X... (%d %d)\n",
++	       key->key[0], key->key[1], key->key[2], key->key[3], key->key[4],
++	       key->key[5], key->key[6], key->key[7], key->keyidx, key->keylen);
++	if (key->keyidx == 0) {
++		memcpy(sram_key->sta_key[0].pair.key, key->key, key->keylen);
++	} else {
++		memcpy(sram_key->group_key[key->keyidx - 1].key, key->key,
++		       key->keylen);
++	}
++	if (sc->sh->cfg.use_wpa2_only) {
++		dev_warn(sc->dev, "WEP: use WPA2 HW security mode only.\n");
++	}
++	if ((sc->sh->cfg.use_wpa2_only == 0)
++	    && vif_priv->vif_idx == 0) {
++		vif_priv->has_hw_decrypt = true;
++		vif_priv->has_hw_encrypt = true;
++		vif_priv->need_sw_decrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = false;
++		ssv6200_hw_set_pair_type(sc->sh, cipher);
++		ssv6200_hw_set_group_type(sc->sh, cipher);
++		hw_crypto_key_write_wep(sc->hw, key, cipher,
++					&sc->vif_info[vif_priv->vif_idx]);
++	} else {
++		vif_priv->has_hw_decrypt = false;
++		vif_priv->has_hw_encrypt = false;
++		vif_priv->need_sw_decrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = true;
++		ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_sw_crypto_key,
++					NULL);
++		ret = -EOPNOTSUPP;
++	}
++	vif_priv->pair_cipher = vif_priv->group_cipher = cipher;
++	vif_priv->is_security_valid = true;
++	return ret;
++}
++
++static int _set_pairwise_key_tkip_ccmp(struct ssv_softc *sc,
++				       struct ssv_vif_priv_data *vif_priv,
++				       struct ssv_sta_priv_data *sta_priv,
++				       enum SSV_CIPHER_E cipher,
++				       struct ieee80211_key_conf *key)
++{
++	int ret = 0;
++	const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	bool tdls_link = false, tdls_use_sw_cipher = false, tkip_use_sw_cipher =
++	    false;
++	bool use_non_ccmp = false;
++	int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
++	struct ssv_vif_priv_data *another_vif_priv =
++	    (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv;
++	if (sta_priv == NULL) {
++		dev_err(sc->dev,
++			"Setting pairwise TKIP/CCMP key to NULL STA.\n");
++		return -EOPNOTSUPP;
++	}
++	if (sc->sh->cfg.use_wpa2_only) {
++		dev_warn(sc->dev, "Pairwise TKIP/CCMP: use WPA2 HW security mode only.\n");
++	}
++	if (vif_info->if_type == NL80211_IFTYPE_STATION) {
++		struct ssv_sta_priv_data *first_sta_priv =
++		    list_first_entry(&vif_priv->sta_list,
++				     struct ssv_sta_priv_data, list);
++		if (first_sta_priv->sta_idx != sta_priv->sta_idx) {
++			tdls_link = true;
++		}
++		dev_dbg(sc->dev, "first sta idx %d, current sta idx %d\n",
++		       first_sta_priv->sta_idx, sta_priv->sta_idx);
++	}
++	if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
++	    && (sc->sh->cfg.use_wpa2_only == false)) {
++		tdls_use_sw_cipher = true;
++	}
++	if (another_vif_priv != NULL) {
++		if ((another_vif_priv->pair_cipher != SSV_CIPHER_CCMP)
++		    && (another_vif_priv->pair_cipher != SSV_CIPHER_NONE)) {
++			use_non_ccmp = true;
++			dev_dbg(sc->dev, "another vif use none ccmp\n");
++		}
++	}
++	if ((((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP))
++	     || (use_non_ccmp))
++	    && (sc->sh->cfg.use_wpa2_only == 1) && (cipher == SSV_CIPHER_CCMP)) {
++		u32 val;
++		SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
++		if (((val >> 4) & 0xF) != M_ENG_CPU) {
++			SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++				       ((val & 0xf) | (M_ENG_CPU << 4)
++					| (val & 0xfffffff0) << 4));
++			dev_dbg(sc->dev,
++				"orginal Rx_Flow %x , modified flow %x \n", val,
++				((val & 0xf) | (M_ENG_CPU << 4) |
++				 (val & 0xfffffff0) << 4));
++		}
++	}
++	if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
++		tkip_use_sw_cipher = true;
++	}
++	if (tkip_use_sw_cipher == true)
++		dev_info(sc->dev, "Using software TKIP cipher\n");
++	if ((((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false)
++	      && (tkip_use_sw_cipher == false)))
++	    || ((cipher == SSV_CIPHER_CCMP)
++		&& (sc->sh->cfg.use_wpa2_only == 1))) {
++		sta_priv->has_hw_decrypt = true;
++		sta_priv->need_sw_decrypt = false;
++		if ((cipher == SSV_CIPHER_TKIP)
++		    || ((!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX) ||
++			 (sta_priv->sta_info->sta->deflink.ht_cap.ht_supported ==
++			  false))
++			&& (vif_priv->force_sw_encrypt == false))) {
++			dev_dbg(sc->dev,
++				"STA %d uses HW encrypter for pairwise.\n",
++				sta_priv->sta_idx);
++			sta_priv->has_hw_encrypt = true;
++			sta_priv->need_sw_encrypt = false;
++			sta_priv->use_mac80211_decrypt = false;
++			ret = 0;
++		} else {
++			sta_priv->has_hw_encrypt = false;
++			sta_priv->need_sw_encrypt = false;
++			sta_priv->use_mac80211_decrypt = true;
++			ret = -EOPNOTSUPP;
++		}
++	} else {
++		sta_priv->has_hw_encrypt = false;
++		sta_priv->has_hw_decrypt = false;
++		dev_err(sc->dev, "STA %d MAC80211's %s cipher.\n",
++			sta_priv->sta_idx, cipher_name);
++		sta_priv->need_sw_encrypt = false;
++		sta_priv->need_sw_decrypt = false;
++		sta_priv->use_mac80211_decrypt = true;
++		ret = -EOPNOTSUPP;
++	}
++	if (sta_priv->has_hw_encrypt || sta_priv->has_hw_decrypt) {
++		ssv6200_hw_set_pair_type(sc->sh, cipher);
++		_write_pairwise_key_to_hw(sc, key->keyidx, cipher,
++					  key->key, key->keylen, key,
++					  vif_priv, sta_priv);
++	}
++	if ((vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt)
++	    && (vif_priv->group_key_idx > 0)) {
++		_set_aes_tkip_hw_crypto_group_key(sc,
++						  &sc->vif_info[vif_priv->
++								vif_idx],
++						  sta_priv->sta_info,
++						  &vif_priv->group_key_idx);
++	}
++	return ret;
++}
++
++static int _set_group_key_tkip_ccmp(struct ssv_softc *sc,
++				    struct ssv_vif_priv_data *vif_priv,
++				    struct ssv_sta_priv_data *sta_priv,
++				    enum SSV_CIPHER_E cipher,
++				    struct ieee80211_key_conf *key)
++{
++	int ret = 0;
++	const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
++	bool tkip_use_sw_cipher = false;
++	vif_priv->group_cipher = cipher;
++	if (sc->sh->cfg.use_wpa2_only) {
++		dev_warn(sc->dev, "Group TKIP/CCMP: use WPA2 HW security mode only.\n");
++	}
++	if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
++		tkip_use_sw_cipher = true;
++	}
++	if (((vif_priv->vif_idx == 0) && (tkip_use_sw_cipher == false))
++	    || ((cipher == SSV_CIPHER_CCMP)
++		&& (sc->sh->cfg.use_wpa2_only == 1))) {
++		dev_dbg(sc->dev, "VIF %d uses HW %s cipher for group.\n",
++			vif_priv->vif_idx, cipher_name);
++#ifdef USE_MAC80211_DECRYPT_BROADCAST
++		vif_priv->has_hw_decrypt = false;
++		ret = -EOPNOTSUPP;
++#else
++		vif_priv->has_hw_decrypt = true;
++#endif
++		vif_priv->has_hw_encrypt = true;
++		vif_priv->need_sw_decrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = false;
++	} else {
++		vif_priv->has_hw_decrypt = false;
++		vif_priv->has_hw_encrypt = false;
++		dev_err(sc->dev, "VIF %d uses MAC80211's %s cipher.\n",
++			vif_priv->vif_idx, cipher_name);
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = true;
++		ret = -EOPNOTSUPP;
++	}
++	if (vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt) {
++#ifdef USE_MAC80211_DECRYPT_BROADCAST
++		ssv6200_hw_set_group_type(sc->sh, ME_NONE);
++#else
++		ssv6200_hw_set_group_type(sc->sh, cipher);
++#endif
++		key->hw_key_idx = key->keyidx;
++		_write_group_key_to_hw(sc, key->keyidx, cipher,
++				       key->key, key->keylen, key,
++				       vif_priv, sta_priv);
++	}
++	vif_priv->is_security_valid = true;
++	{
++		int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
++		struct ssv_vif_priv_data *another_vif_priv =
++		    (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].
++		    vif_priv;
++		if (another_vif_priv != NULL) {
++			if (((SSV6XXX_USE_SW_DECRYPT(vif_priv)
++			      && SSV6XXX_USE_HW_DECRYPT(another_vif_priv)))
++			    || ((SSV6XXX_USE_HW_DECRYPT(vif_priv)
++				 &&
++				 (SSV6XXX_USE_SW_DECRYPT(another_vif_priv))))) {
++				u32 val;
++				SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
++				if (((val >> 4) & 0xF) != M_ENG_CPU) {
++					SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++						       ((val & 0xf) |
++							(M_ENG_CPU << 4)
++							| (val & 0xfffffff0) <<
++							4));
++					dev_dbg(sc->dev,
++						"orginal Rx_Flow %x , modified flow %x \n",
++						val,
++						((val & 0xf) | (M_ENG_CPU << 4)
++						 | (val & 0xfffffff0) << 4));
++				} else {
++					dev_dbg(sc->dev, " doesn't need to change rx flow\n");
++				}
++			}
++		}
++	}
++	return ret;
++}
++
++static int _set_key_tkip_ccmp(struct ssv_softc *sc,
++			      struct ssv_vif_priv_data *vif_priv,
++			      struct ssv_sta_priv_data *sta_priv,
++			      enum SSV_CIPHER_E cipher,
++			      struct ieee80211_key_conf *key)
++{
++	if (key->keyidx == 0)
++		return _set_pairwise_key_tkip_ccmp(sc, vif_priv, sta_priv,
++						   cipher, key);
++	else
++		return _set_group_key_tkip_ccmp(sc, vif_priv, sta_priv, cipher,
++						key);
++}
++
++static int ssv6200_set_key(struct ieee80211_hw *hw,
++			   enum set_key_cmd cmd,
++			   struct ieee80211_vif *vif,
++			   struct ieee80211_sta *sta,
++			   struct ieee80211_key_conf *key)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	enum SSV_CIPHER_E cipher = SSV_CIPHER_NONE;
++	int sta_idx = (-1);
++	struct ssv_sta_info *sta_info = NULL;
++	struct ssv_sta_priv_data *sta_priv = NULL;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	if (sta) {
++		sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		sta_idx = sta_priv->sta_idx;
++		sta_info = sta_priv->sta_info;
++	}
++	BUG_ON((cmd != SET_KEY) && (cmd != DISABLE_KEY));
++	if (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_SECURITY)) {
++		dev_warn(sc->dev, "HW does not support security.\n");
++		return -EOPNOTSUPP;
++	}
++	if (sta_info && (sta_info->hw_wsid == (-1))) {
++		dev_warn(sc->dev,
++			 "Add STA without HW resource. Use MAC80211's solution.\n");
++		return -EOPNOTSUPP;
++	}
++	cipher = _prepare_key(key);
++	dev_dbg(sc->dev,
++		"Set key VIF %d VIF type %d STA %d algorithm = %d, key->keyidx = %d, cmd = %d\n",
++		vif_priv->vif_idx, vif->type, sta_idx, cipher, key->keyidx,
++		cmd);
++	if (cipher == SSV_CIPHER_INVALID) {
++		dev_warn(sc->dev, "Unsupported cipher type.\n");
++		return -EOPNOTSUPP;
++	}
++	mutex_lock(&sc->mutex);
++	switch (cmd) {
++	case SET_KEY:
++		{
++			switch (cipher) {
++			case SSV_CIPHER_WEP40:
++			case SSV_CIPHER_WEP104:
++				ret =
++				    _set_key_wep(sc, vif_priv, sta_priv, cipher,
++						 key);
++				break;
++			case SSV_CIPHER_TKIP:
++			case SSV_CIPHER_CCMP:
++				ret =
++				    _set_key_tkip_ccmp(sc, vif_priv, sta_priv,
++						       cipher, key);
++				break;
++			default:
++				break;
++			}
++			if (sta) {
++				struct ssv_sta_priv_data *first_sta_priv =
++				    list_first_entry(&vif_priv->sta_list,
++						     struct ssv_sta_priv_data,
++						     list);
++				if (first_sta_priv->sta_idx ==
++				    sta_priv->sta_idx) {
++					vif_priv->pair_cipher = cipher;
++				}
++				if (SSV6200_USE_HW_WSID(sta_idx)) {
++					if (SSV6XXX_USE_SW_DECRYPT(sta_priv)) {
++						u32 cipher_setting;
++						cipher_setting =
++						    ssv6200_hw_get_pair_type
++						    (sc->sh);
++						if (cipher_setting != ME_NONE) {
++							u32 val;
++							SMAC_REG_READ(sc->sh,
++								      ADR_RX_FLOW_DATA,
++								      &val);
++							if (((val >> 4) & 0xF)
++							    != M_ENG_CPU) {
++								SMAC_REG_WRITE
++								    (sc->sh,
++								     ADR_RX_FLOW_DATA,
++								     ((val &
++								       0xf) |
++								      (M_ENG_CPU
++								       << 4)
++								      | (val &
++									 0xfffffff0)
++								      << 4));
++								dev_dbg(sc->dev,
++									"orginal Rx_Flow %x , modified flow %x \n",
++									val,
++									((val &
++									  0xf) |
++									 (M_ENG_CPU
++									  << 4)
++									 | (val
++									    &
++									    0xfffffff0)
++									 << 4));
++							} else {
++								dev_dbg(sc->dev, " doesn't need to change rx flow\n");
++							}
++						}
++					}
++					if (sta_priv->has_hw_decrypt) {
++						hw_update_watch_wsid(sc, sta,
++								     sta_info,
++								     sta_idx,
++								     SSV6XXX_WSID_SEC_HW,
++								     SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
++						dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for pairwise key\n", sta_idx);
++					}
++				}
++			} else {
++				if (vif_info->if_type == NL80211_IFTYPE_STATION) {
++					struct ssv_sta_priv_data *first_sta_priv
++					    =
++					    list_first_entry(&vif_priv->
++							     sta_list,
++							     struct
++							     ssv_sta_priv_data,
++							     list);
++					if (SSV6200_USE_HW_WSID
++					    (first_sta_priv->sta_idx)) {
++						if (vif_priv->has_hw_decrypt) {
++							hw_update_watch_wsid(sc,
++									     sta,
++									     sta_info,
++									     first_sta_priv->
++									     sta_idx,
++									     SSV6XXX_WSID_SEC_HW,
++									     SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
++							dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for group key\n", first_sta_priv->sta_idx);
++						}
++					}
++				}
++			}
++		}
++		break;
++	case DISABLE_KEY:
++		{
++			int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
++			struct ssv_vif_priv_data *another_vif_priv =
++			    (struct ssv_vif_priv_data *)sc->
++			    vif_info[another_vif_idx].vif_priv;
++			if (another_vif_priv != NULL) {
++				struct ssv_vif_info *vif_info =
++				    &sc->vif_info[vif_priv->vif_idx];
++				if (vif_info->if_type != NL80211_IFTYPE_AP) {
++					if ((SSV6XXX_USE_SW_DECRYPT(vif_priv)
++					     &&
++					     SSV6XXX_USE_HW_DECRYPT
++					     (another_vif_priv))
++					    ||
++					    (SSV6XXX_USE_SW_DECRYPT
++					     (another_vif_priv)
++					     &&
++					     SSV6XXX_USE_HW_DECRYPT(vif_priv)))
++					{
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_FLOW_DATA,
++							       M_ENG_MACRX |
++							       (M_ENG_ENCRYPT_SEC
++								<< 4) |
++							       (M_ENG_HWHCI <<
++								8));
++						dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
++					}
++				} else {
++					if (sta == NULL) {
++						if (SSV6XXX_USE_SW_DECRYPT
++						    (another_vif_priv)
++						    &&
++						    SSV6XXX_USE_HW_DECRYPT
++						    (vif_priv)) {
++							SMAC_REG_WRITE(sc->sh,
++								       ADR_RX_FLOW_DATA,
++								       M_ENG_MACRX
++								       |
++								       (M_ENG_ENCRYPT_SEC
++									<< 4) |
++								       (M_ENG_HWHCI
++									<< 8));
++							dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
++						}
++					}
++				}
++			}
++			if (sta == NULL) {
++				vif_priv->group_cipher = ME_NONE;
++				if ((another_vif_priv == NULL)
++				    || ((another_vif_priv != NULL)
++					&&
++					(!SSV6XXX_USE_HW_DECRYPT
++					 (another_vif_priv)))) {
++					ssv6200_hw_set_group_type(sc->sh,
++								  ME_NONE);
++				}
++			} else {
++				struct ssv_vif_info *vif_info =
++				    &sc->vif_info[vif_priv->vif_idx];
++				if ((vif_info->if_type != NL80211_IFTYPE_AP)
++				    && (another_vif_priv == NULL)) {
++					struct ssv_sta_priv_data *first_sta_priv
++					    =
++					    list_first_entry(&vif_priv->
++							     sta_list,
++							     struct
++							     ssv_sta_priv_data,
++							     list);
++					if (sta_priv == first_sta_priv) {
++						ssv6200_hw_set_pair_type(sc->sh,
++									 ME_NONE);
++					}
++				}
++				vif_priv->pair_cipher = ME_NONE;
++			}
++			if ((cipher == ME_TKIP) || (cipher == ME_CCMP)) {
++				dev_dbg(sc->dev, "Clear key %d VIF %d, STA %d\n",
++				       key->keyidx, (vif != NULL),
++				       (sta != NULL));
++				hw_crypto_key_clear(hw, key->keyidx, key,
++						    vif_priv, sta_priv);
++			}
++			{
++				if ((key->keyidx == 0) && (sta_priv != NULL)) {
++					sta_priv->has_hw_decrypt = false;
++					sta_priv->has_hw_encrypt = false;
++					sta_priv->need_sw_encrypt = false;
++					sta_priv->use_mac80211_decrypt = false;
++				}
++				if ((vif_priv->is_security_valid)
++				    && (key->keyidx != 0)) {
++					vif_priv->is_security_valid = false;
++				}
++			}
++			ret = 0;
++		}
++		break;
++	default:
++		ret = -EINVAL;
++	}
++	mutex_unlock(&sc->mutex);
++	if (sta_priv != NULL) {
++		dev_info(sc->dev, "station mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d\n",
++		       (sta_priv->has_hw_encrypt == true),
++		       (sta_priv->has_hw_decrypt == true),
++		       (sta_priv->need_sw_encrypt == true),
++		       (sta_priv->need_sw_decrypt == true));
++	}
++	if (vif_priv) {
++		dev_info
++		    (sc->dev, "vif mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d, mac80211 decrypt: %d, valid:%d\n",
++		     (vif_priv->has_hw_encrypt == true),
++		     (vif_priv->has_hw_decrypt == true),
++		     (vif_priv->need_sw_encrypt == true),
++		     (vif_priv->need_sw_decrypt == true),
++		     (vif_priv->use_mac80211_decrypt == true),
++		     (vif_priv->is_security_valid == true));
++	}
++	if (vif_priv->force_sw_encrypt
++	    || (sta_info && (sta_info->hw_wsid != 1)
++		&& (sta_info->hw_wsid != 0))) {
++		if (vif_priv->force_sw_encrypt == false)
++			vif_priv->force_sw_encrypt = true;
++		ret = -EOPNOTSUPP;
++	}
++	dev_dbg(sc->dev, "SET KEY %d\n", ret);
++	return ret;
++}
++
++u32 _process_tx_done(struct ssv_softc *sc)
++{
++	struct ieee80211_tx_info *tx_info;
++	struct sk_buff *skb;
++	while ((skb = skb_dequeue(&sc->tx_done_q))) {
++		struct ssv6200_tx_desc *tx_desc;
++		tx_info = IEEE80211_SKB_CB(skb);
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		if (tx_desc->c_type > M2_TXREQ) {
++			ssv_skb_free(skb);
++			dev_dbg(sc->dev, "free cmd skb!\n");
++			continue;
++		}
++		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
++			ssv6200_ampdu_release_skb(skb, sc->hw);
++			continue;
++		}
++		skb_pull(skb, SSV6XXX_TX_DESC_LEN);
++		ieee80211_tx_info_clear_status(tx_info);
++		tx_info->flags |= IEEE80211_TX_STAT_ACK;
++		tx_info->status.ack_signal = 100;
++#ifdef REPORT_TX_DONE_IN_IRQ
++		ieee80211_tx_status_irqsafe(sc->hw, skb);
++#else
++		ieee80211_tx_status_skb(sc->hw, skb);
++		if (skb_queue_len(&sc->rx_skb_q))
++			break;
++#endif
++	}
++	return skb_queue_len(&sc->tx_done_q);
++}
++
++#ifdef REPORT_TX_DONE_IN_IRQ
++void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)args;
++	_process_tx_done *(sc);
++}
++#else
++void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)args;
++	struct sk_buff *skb;
++	while ((skb = skb_dequeue(skb_head))) {
++		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++		struct ssv6200_tx_desc *tx_desc;
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		if (tx_desc->c_type > M2_TXREQ) {
++			ssv_skb_free(skb);
++			dev_dbg(sc->dev, "free cmd skb!\n");
++			continue;
++		}
++		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
++			ssv6xxx_ampdu_sent(sc->hw, skb);
++		skb_queue_tail(&sc->tx_done_q, skb);
++	}
++	wake_up_interruptible(&sc->rx_wait_q);
++}
++#endif
++void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args)
++{
++	struct ieee80211_hdr *hdr;
++	struct ssv_softc *sc = args;
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ssv6200_tx_desc *tx_desc;
++	struct ssv_rate_info ssv_rate;
++	u32 nav = 0;
++	int ret = 0;
++	tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	if (tx_desc->c_type > M2_TXREQ)
++		return;
++	if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) {
++		hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_TX_DESC_LEN);
++		if ((ieee80211_is_data_qos(hdr->frame_control)
++		     || ieee80211_is_data(hdr->frame_control))
++		    && (tx_desc->wsid < SSV_RC_MAX_HARDWARE_SUPPORT)) {
++			ret =
++			    ssv6xxx_rc_hw_rate_update_check(skb, sc,
++							    tx_desc->
++							    do_rts_cts);
++			if (ret & RC_FIRMWARE_REPORT_FLAG) {
++				{
++					tx_desc->RSVD_0 = SSV6XXX_RC_REPORT;
++					tx_desc->tx_report = 1;
++				}
++				ret &= 0xf;
++			}
++			if (ret) {
++				ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
++				tx_desc->crate_idx = ssv_rate.crate_hw_idx;
++				tx_desc->drate_idx = ssv_rate.drate_hw_idx;
++				nav =
++				    ssv6xxx_set_frame_duration(info, &ssv_rate,
++							       skb->len +
++							       FCS_LEN, tx_desc,
++							       NULL, NULL);
++				if (tx_desc->tx_burst == 0) {
++					if (tx_desc->ack_policy != 0x01)
++						hdr->duration_id = nav;
++				}
++			}
++		}
++	} else {
++	}
++	return;
++}
++
++void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct ieee80211_hdr *hdr;
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_sta *sta;
++	struct ssv_sta_info *sta_info = NULL;
++	struct ssv_sta_priv_data *ssv_sta_priv = NULL;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
++	struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	struct ieee80211_tx_rate *tx_drate;
++	struct ssv_rate_info ssv_rate;
++	int ac, hw_txqid;
++	u32 nav = 0;
++	if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++		struct ampdu_hdr_st *ampdu_hdr =
++		    (struct ampdu_hdr_st *)skb->head;
++		sta = ampdu_hdr->ampdu_tid->sta;
++		hdr =
++		    (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET +
++					     AMPDU_DELIMITER_LEN);
++	} else {
++		struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++		sta = skb_info->sta;
++		hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET);
++	}
++	if (sta) {
++		ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		sta_info = ssv_sta_priv->sta_info;
++	}
++	if ((!sc->bq4_dtim) &&
++	    (ieee80211_is_mgmt(hdr->frame_control) ||
++	     ieee80211_is_nullfunc(hdr->frame_control) ||
++	     ieee80211_is_qos_nullfunc(hdr->frame_control))) {
++		ac = 4;
++		hw_txqid = 4;
++	} else if ((sc->bq4_dtim) &&
++		   info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
++		hw_txqid = 4;
++		ac = 4;
++	} else {
++		ac = skb_get_queue_mapping(skb);
++		hw_txqid = sc->tx.hw_txqid[ac];
++	}
++	tx_drate = &info->control.rates[0];
++	ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
++	tx_desc->len = skb->len;
++	tx_desc->c_type = M2_TXREQ;
++	tx_desc->f80211 = 1;
++	tx_desc->qos = (ieee80211_is_data_qos(hdr->frame_control)) ? 1 : 0;
++	if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
++		if (ieee80211_is_mgmt(hdr->frame_control) &&
++		    ieee80211_has_order(hdr->frame_control))
++			tx_desc->ht = 1;
++	}
++	tx_desc->use_4addr = (ieee80211_has_a4(hdr->frame_control)) ? 1 : 0;
++	tx_desc->more_data =
++	    (ieee80211_has_morefrags(hdr->frame_control)) ? 1 : 0;
++	tx_desc->stype_b5b4 = (cpu_to_le16(hdr->frame_control) >> 4) & 0x3;
++	tx_desc->frag = (tx_desc->more_data || (hdr->seq_ctrl & 0xf)) ? 1 : 0;
++	tx_desc->unicast = (is_multicast_ether_addr(hdr->addr1)) ? 0 : 1;
++	tx_desc->tx_burst = (tx_desc->frag) ? 1 : 0;
++	tx_desc->wsid = (!sta_info
++			 || (sta_info->hw_wsid < 0)) ? 0x0F : sta_info->hw_wsid;
++	tx_desc->txq_idx = hw_txqid;
++	tx_desc->hdr_offset = TXPB_OFFSET;
++	tx_desc->hdr_len = ssv6xxx_frame_hdrlen(hdr, tx_desc->ht);
++	tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
++	if (info->control.use_rts)
++		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
++	else if (info->control.use_cts_prot)
++		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_CTS_PROTECT;
++	if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT)
++		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
++	if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT) {
++		tx_desc->crate_idx = 0;
++	} else
++		tx_desc->crate_idx = ssv_rate.crate_hw_idx;
++	tx_desc->drate_idx = ssv_rate.drate_hw_idx;
++	if (tx_desc->unicast == 0)
++		tx_desc->ack_policy = 1;
++	else if (tx_desc->qos == 1)
++		tx_desc->ack_policy = (*ieee80211_get_qos_ctl(hdr) & 0x60) >> 5;
++	else if (ieee80211_is_ctl(hdr->frame_control))
++		tx_desc->ack_policy = 1;
++	tx_desc->security = 0;
++	tx_desc->fCmdIdx = 0;
++	tx_desc->fCmd = (hw_txqid + M_ENG_TX_EDCA0);
++	if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++#ifdef AMPDU_HAS_LEADING_FRAME
++		tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_CPU;
++#else
++		tx_desc->RSVD_1 = 1;
++#endif
++		tx_desc->aggregation = 1;
++		tx_desc->ack_policy = 0x01;
++		if ((tx_desc->do_rts_cts == 0)
++		    && ((sc->hw->wiphy->rts_threshold == (-1))
++			|| ((skb->len - sc->sh->tx_desc_len) >
++			    sc->hw->wiphy->rts_threshold))) {
++			tx_drate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
++			tx_desc->do_rts_cts = 1;
++		}
++	}
++	if (ieee80211_has_protected(hdr->frame_control)
++	    && (ieee80211_is_data_qos(hdr->frame_control)
++		|| ieee80211_is_data(hdr->frame_control))) {
++		if ((tx_desc->unicast && ssv_sta_priv
++		     && ssv_sta_priv->has_hw_encrypt)
++		    || (!tx_desc->unicast && vif_priv
++			&& vif_priv->has_hw_encrypt)) {
++			if (!tx_desc->unicast
++			    && !list_empty(&vif_priv->sta_list)) {
++				struct ssv_sta_priv_data *one_sta_priv;
++				int hw_wsid;
++				one_sta_priv =
++				    list_first_entry(&vif_priv->sta_list,
++						     struct ssv_sta_priv_data,
++						     list);
++				hw_wsid = one_sta_priv->sta_info->hw_wsid;
++				if (hw_wsid != (-1)) {
++					tx_desc->wsid = hw_wsid;
++				}
++			}
++			tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_ENCRYPT;
++		} else if (ssv_sta_priv->need_sw_encrypt) {
++		} else {
++		}
++	} else {
++	}
++	tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_HWHCI;
++	if (tx_desc->aggregation == 1) {
++		struct ampdu_hdr_st *ampdu_hdr =
++		    (struct ampdu_hdr_st *)skb->head;
++		memcpy(&tx_desc->rc_params[0], ampdu_hdr->rates,
++		       sizeof(tx_desc->rc_params));
++		nav =
++		    ssv6xxx_set_frame_duration(info, &ssv_rate,
++					       (skb->len + FCS_LEN), tx_desc,
++					       &tx_desc->rc_params[0], sc);
++#ifdef FW_RC_RETRY_DEBUG
++		{
++			dev_dbg
++			    (sc->dev, "[FW_RC]:param[0]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
++			     tx_desc->rc_params[0].drate,
++			     tx_desc->rc_params[0].count,
++			     tx_desc->rc_params[0].crate,
++			     tx_desc->rc_params[0].dl_length,
++			     tx_desc->rc_params[0].frame_consume_time,
++			     tx_desc->rc_params[0].rts_cts_nav);
++			dev_dbg
++			    (sc->dev, "[FW_RC]:param[1]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
++			     tx_desc->rc_params[1].drate,
++			     tx_desc->rc_params[1].count,
++			     tx_desc->rc_params[1].crate,
++			     tx_desc->rc_params[1].dl_length,
++			     tx_desc->rc_params[1].frame_consume_time,
++			     tx_desc->rc_params[1].rts_cts_nav);
++			dev_dbg
++			    (sc->dev, "[FW_RC]:param[2]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
++			     tx_desc->rc_params[2].drate,
++			     tx_desc->rc_params[2].count,
++			     tx_desc->rc_params[2].crate,
++			     tx_desc->rc_params[2].dl_length,
++			     tx_desc->rc_params[2].frame_consume_time,
++			     tx_desc->rc_params[2].rts_cts_nav);
++		}
++#endif
++	} else {
++		nav =
++		    ssv6xxx_set_frame_duration(info, &ssv_rate,
++					       (skb->len + FCS_LEN), tx_desc,
++					       NULL, NULL);
++	}
++	if ((tx_desc->aggregation == 0)) {
++		if (tx_desc->tx_burst == 0) {
++			if (tx_desc->ack_policy != 0x01)
++				hdr->duration_id = nav;
++		} else {
++		}
++	}
++}
++
++void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct ssv6200_tx_desc *tx_desc;
++	skb_push(skb, sc->sh->tx_desc_len);
++	tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	memset((void *)tx_desc, 0, sc->sh->tx_desc_len);
++	ssv6xxx_update_txinfo(sc, skb);
++}
++
++int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_tx_rate *tx_drate;
++	struct ssv_rate_info ssv_rate;
++	tx_drate = &info->control.rates[0];
++	ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
++	return ssv_rate.drate_hw_idx;
++}
++
++static void _ssv6xxx_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_vif *vif = info->control.vif;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++	struct ssv6200_tx_desc *tx_desc;
++	int ret;
++	unsigned long flags;
++	bool send_hci = false;
++	do {
++		if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
++			if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
++				sc->tx.seq_no += 0x10;
++			hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
++			hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
++		}
++		if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++			if (ssv6xxx_get_real_index(sc, skb) <
++			    SSV62XX_RATE_MCS_INDEX) {
++				info->flags &= (~IEEE80211_TX_CTL_AMPDU);
++				goto tx_mpdu;
++			}
++			if (ssv6200_ampdu_tx_handler(hw, skb)) {
++				break;
++			} else {
++				info->flags &= (~IEEE80211_TX_CTL_AMPDU);
++			}
++		}
++ tx_mpdu:
++		ssv6xxx_add_txinfo(sc, skb);
++		if (vif &&
++		    vif->type == NL80211_IFTYPE_AP &&
++		    (sc->bq4_dtim) &&
++		    info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
++			struct ssv_vif_priv_data *priv_vif =
++			    (struct ssv_vif_priv_data *)vif->drv_priv;
++			u8 buffered = 0;
++			spin_lock_irqsave(&sc->ps_state_lock, flags);
++			if (priv_vif->sta_asleep_mask) {
++				buffered =
++				    ssv6200_bcast_enqueue(sc, &sc->bcast_txq,
++							  skb);
++				if (1 == buffered) {
++					dev_dbg(sc->dev, "ssv6200_tx:ssv6200_bcast_start\n");
++					ssv6200_bcast_start(sc);
++				}
++			}
++			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++			if (buffered)
++				break;
++		}
++		if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
++			struct ssv_vif_priv_data *vif_priv =
++			    (struct ssv_vif_priv_data *)vif->drv_priv;
++			dev_dbg(sc->dev, "vif[%d] sc->bq4_dtim[%d]\n",
++				vif_priv->vif_idx, sc->bq4_dtim);
++		}
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		ret = HCI_SEND(sc->sh, skb, tx_desc->txq_idx);
++		send_hci = true;
++	} while (0);
++	if ((skb_queue_len(&sc->tx_skb_q) < LOW_TX_Q_LEN)
++	    ) {
++		if (sc->tx.flow_ctrl_status != 0) {
++			int ac;
++			for (ac = 0; ac < sc->hw->queues; ac++) {
++				if ((sc->tx.flow_ctrl_status & BIT(ac)) == 0)
++					ieee80211_wake_queue(sc->hw, ac);
++			}
++		} else {
++			ieee80211_wake_queues(sc->hw);
++		}
++	}
++}
++
++static void ssv6200_tx(struct ieee80211_hw *hw,
++		       struct ieee80211_tx_control *control,
++		       struct sk_buff *skb)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)hw->priv;
++	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++	skb_info->sta = control ? control->sta : NULL;
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++	skb_info->timestamp = ktime_get();
++#endif
++	skb_queue_tail(&sc->tx_skb_q, skb);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (sc->max_tx_skb_q_len < skb_queue_len(&sc->tx_skb_q))
++		sc->max_tx_skb_q_len = skb_queue_len(&sc->tx_skb_q);
++#endif
++	wake_up_interruptible(&sc->tx_wait_q);
++	do {
++		if (skb_queue_len(&sc->tx_skb_q) >= MAX_TX_Q_LEN)
++			ieee80211_stop_queues(sc->hw);
++	} while (0);
++}
++
++int ssv6xxx_tx_task(void *data)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)data;
++	u32 wait_period = SSV_AMPDU_timer_period / 2;
++	dev_info(sc->dev, "TX Task started\n");
++	while (!kthread_should_stop()) {
++		u32 before_timeout = (-1);
++		set_current_state(TASK_INTERRUPTIBLE);
++		before_timeout = wait_event_interruptible_timeout(sc->tx_wait_q,
++								  (skb_queue_len
++								   (&sc->
++								    tx_skb_q)
++								   ||
++								   kthread_should_stop
++								   ()
++								   || sc->
++								   tx_q_empty),
++								  msecs_to_jiffies
++								  (wait_period));
++		if (kthread_should_stop()) {
++			dev_dbg(sc->dev, "Quit TX task loop...\n");
++			break;
++		}
++		set_current_state(TASK_RUNNING);
++		do {
++			struct sk_buff *tx_skb = skb_dequeue(&sc->tx_skb_q);
++			if (tx_skb == NULL)
++				break;
++			_ssv6xxx_tx(sc->hw, tx_skb);
++		} while (1);
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++		{
++			struct ssv_hw_txq *hw_txq = NULL;
++			struct ieee80211_tx_info *tx_info = NULL;
++			struct sk_buff *skb = NULL;
++			int txqid;
++			unsigned int timeout;
++			u32 status;
++			for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++				hw_txq = &ssv_dbg_ctrl_hci->hw_txq[txqid];
++				skb = skb_peek(&hw_txq->qhead);
++				if (skb != NULL) {
++					tx_info = IEEE80211_SKB_CB(skb);
++					if (tx_info->
++					    flags & IEEE80211_TX_CTL_AMPDU)
++						timeout =
++						    cal_duration_of_ampdu(skb,
++									  SKB_DURATION_STAGE_IN_HWQ);
++					else
++						timeout =
++						    cal_duration_of_mpdu(skb);
++					if (timeout > SKB_DURATION_TIMEOUT_MS) {
++						HCI_IRQ_STATUS(ssv_dbg_ctrl_hci,
++							       &status);
++						dev_dbg(sc->dev, "hci int_mask: %08x\n",
++						       ssv_dbg_ctrl_hci->
++						       int_mask);
++						dev_dbg(sc->dev, "sdio status: %08x\n",
++						       status);
++						dev_dbg(sc->dev, "hwq%d len: %d\n", txqid,
++						       skb_queue_len(&hw_txq->
++								     qhead));
++					}
++				}
++			}
++		}
++#endif
++		if (sc->tx_q_empty || (before_timeout == 0)) {
++			u32 flused_ampdu = ssv6xxx_ampdu_flush(sc->hw);
++			sc->tx_q_empty = false;
++			if (flused_ampdu == 0 && before_timeout == 0) {
++				wait_period *= 2;
++				if (wait_period > 1000)
++					wait_period = 1000;
++			}
++		} else
++			wait_period = SSV_AMPDU_timer_period / 2;
++	}
++	return 0;
++}
++
++int ssv6xxx_rx_task(void *data)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)data;
++	unsigned long wait_period = msecs_to_jiffies(200);
++	unsigned long last_timeout_check_jiffies = jiffies;
++	unsigned long cur_jiffies;
++	dev_info(sc->dev, "RX Task started\n");
++	while (!kthread_should_stop()) {
++		u32 before_timeout = (-1);
++		set_current_state(TASK_INTERRUPTIBLE);
++		before_timeout = wait_event_interruptible_timeout(sc->rx_wait_q,
++								  (skb_queue_len
++								   (&sc->
++								    rx_skb_q)
++								   ||
++								   skb_queue_len
++								   (&sc->
++								    tx_done_q)
++								   ||
++								   kthread_should_stop
++								   ()),
++								  wait_period);
++		if (kthread_should_stop()) {
++			dev_dbg(sc->dev, "Quit RX task loop...\n");
++			break;
++		}
++		set_current_state(TASK_RUNNING);
++		cur_jiffies = jiffies;
++		if ((before_timeout == 0)
++		    || time_before((last_timeout_check_jiffies + wait_period),
++				   cur_jiffies)) {
++			ssv6xxx_ampdu_check_timeout(sc->hw);
++			last_timeout_check_jiffies = cur_jiffies;
++		}
++		if (skb_queue_len(&sc->rx_skb_q))
++			_process_rx_q(sc, &sc->rx_skb_q, NULL);
++		if (skb_queue_len(&sc->tx_done_q))
++			_process_tx_done(sc);
++	}
++	return 0;
++}
++
++struct ssv6xxx_iqk_cfg init_iqk_cfg = {
++	SSV6XXX_IQK_CFG_XTAL_26M,
++#ifdef CONFIG_SSV_DPD
++	SSV6XXX_IQK_CFG_PA_LI_MPB,
++#else
++	SSV6XXX_IQK_CFG_PA_DEF,
++#endif
++	0,
++	0,
++	26,
++	3,
++	0x75,
++	0x75,
++	0x80,
++	0x80,
++	SSV6XXX_IQK_CMD_INIT_CALI,
++	{SSV6XXX_IQK_TEMPERATURE
++	 + SSV6XXX_IQK_RXDC
++	 + SSV6XXX_IQK_RXRC
++	 + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ
++#ifdef CONFIG_SSV_DPD
++	 + SSV6XXX_IQK_PAPD
++#endif
++	 },
++};
++
++static int ssv6200_start(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_hw *sh = sc->sh;
++	struct ieee80211_channel *chan;
++    int ret;
++    
++	mutex_lock(&sc->mutex);
++    ret = ssv6xxx_init_mac(sc->sh);
++	if (ret != 0) {
++		dev_err(sc->dev, "Failed to initialize mac, ret=%d\n", ret);
++		ssv6xxx_deinit_mac(sc);
++		mutex_unlock(&sc->mutex);
++		return -1;
++	}
++#ifdef CONFIG_P2P_NOA
++	ssv6xxx_noa_reset(sc);
++#endif
++	HCI_START(sh);
++	ieee80211_wake_queues(hw);
++	ssv6200_ampdu_init(hw);
++	sc->watchdog_flag = WD_KICKED;
++	mutex_unlock(&sc->mutex);
++	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++#ifdef CONFIG_SSV_SMARTLINK
++	{
++		extern int ksmartlink_init(void);
++		(void)ksmartlink_init();
++	}
++#endif
++    ret = ssv6xxx_do_iq_calib(sc->sh, &init_iqk_cfg);
++    if (ret != 0) {
++        dev_err(sc->dev, "IQ Calibration failed, ret=%d\n", ret);
++        return ret;
++    }
++
++	dev_info(sc->dev, "Calibration successful\n");
++
++	SMAC_REG_WRITE(sc->sh, ADR_PHY_EN_1, 0x217f);
++	if ((sh->cfg.chip_identity == SSV6051Z)
++	    || (sc->sh->cfg.chip_identity == SSV6051P)) {
++		int i;
++		for (i = 0; i < sh->ch_cfg_size; i++) {
++			SMAC_REG_READ(sh, sh->p_ch_cfg[i].reg_addr,
++				      &sh->p_ch_cfg[i].ch1_12_value);
++		}
++	}
++	chan = hw->conf.chandef.chan;
++	sc->cur_channel = chan;
++	dev_dbg(sc->dev, "%s(): current channel: %d,sc->ps_status=%d\n", __FUNCTION__,
++	       sc->cur_channel->hw_value, sc->ps_status);
++	ssv6xxx_set_channel(sc, chan->hw_value);
++	ssv6xxx_rf_enable(sh);
++	return 0;
++}
++
++static void ssv6200_stop(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	u32 count = 0;
++	struct rssi_res_st *rssi_tmp0, *rssi_tmp1;
++	dev_dbg(sc->dev, "%s(): sc->ps_status=%d\n", __FUNCTION__,
++	       sc->ps_status);
++	mutex_lock(&sc->mutex);
++	list_for_each_entry_safe(rssi_tmp0, rssi_tmp1, &rssi_res.rssi_list,
++				 rssi_list) {
++		list_del(&rssi_tmp0->rssi_list);
++		kfree(rssi_tmp0);
++	}
++	ssv6200_ampdu_deinit(hw);
++	ssv6xxx_rf_disable(sc->sh);
++	HCI_STOP(sc->sh);
++#ifndef NO_USE_RXQ_LOCK
++	while (0) {
++#else
++	while (skb_queue_len(&sc->rx.rxq_head)) {
++#endif
++		dev_dbg(sc->dev, "sc->rx.rxq_count=%d\n", sc->rx.rxq_count);
++		count++;
++		if (count > 90000000) {
++			dev_err(sc->dev, "Could not empty RX queue during shutdown\n");
++			break;
++		}
++	}
++	HCI_TXQ_FLUSH(sc->sh, (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2 |
++			       TXQ_EDCA_3 | TXQ_MGMT));
++	if ((sc->ps_status == PWRSV_PREPARE) || (sc->ps_status == PWRSV_ENABLE)) {
++		ssv6xxx_enable_ps(sc);
++		ssv6xxx_rf_enable(sc->sh);
++	}
++	sc->watchdog_flag = WD_SLEEP;
++	mutex_unlock(&sc->mutex);
++	del_timer_sync(&sc->watchdog_timeout);
++#ifdef CONFIG_SSV_SMARTLINK
++	{
++		extern void ksmartlink_exit(void);
++		ksmartlink_exit();
++	}
++#endif
++	dev_dbg(sc->dev, "%s(): leave\n", __FUNCTION__);
++}
++
++void inline ssv62xxx_set_bssid(struct ssv_softc *sc, u8 * bssid)
++{
++	memcpy(sc->bssid, bssid, 6);
++	SMAC_REG_WRITE(sc->sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
++	SMAC_REG_WRITE(sc->sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
++}
++
++struct ssv_vif_priv_data *ssv6xxx_config_vif_res(struct ssv_softc *sc,
++						 struct ieee80211_vif *vif)
++{
++	int i;
++	struct ssv_vif_priv_data *priv_vif;
++	struct ssv_vif_info *vif_info;
++	lockdep_assert_held(&sc->mutex);
++	for (i = 0; i < SSV6200_MAX_VIF; i++) {
++		if (sc->vif_info[i].vif == NULL)
++			break;
++	}
++	BUG_ON(i >= SSV6200_MAX_VIF);
++	dev_dbg(sc->dev, "ssv6xxx_config_vif_res id[%d].\n", i);
++	priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
++	memset(priv_vif, 0, sizeof(struct ssv_vif_priv_data));
++	priv_vif->vif_idx = i;
++	memset(&sc->vif_info[i], 0, sizeof(sc->vif_info[0]));
++	sc->vif_info[i].vif = vif;
++	sc->vif_info[i].vif_priv = priv_vif;
++	INIT_LIST_HEAD(&priv_vif->sta_list);
++	priv_vif->pair_cipher = SSV_CIPHER_NONE;
++	priv_vif->group_cipher = SSV_CIPHER_NONE;
++	priv_vif->has_hw_decrypt = false;
++	priv_vif->has_hw_encrypt = false;
++	priv_vif->need_sw_encrypt = false;
++	priv_vif->need_sw_decrypt = false;
++	priv_vif->use_mac80211_decrypt = false;
++	priv_vif->is_security_valid = false;
++	priv_vif->force_sw_encrypt = (vif->type == NL80211_IFTYPE_AP);
++	vif_info = &sc->vif_info[priv_vif->vif_idx];
++	vif_info->if_type = vif->type;
++	vif_info->vif = vif;
++	return priv_vif;
++}
++
++static int ssv6200_add_interface(struct ieee80211_hw *hw,
++				 struct ieee80211_vif *vif)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	struct ssv_vif_priv_data *vif_priv = NULL;
++	dev_dbg(sc->dev, "[I] %s(): vif->type = %d, NL80211_IFTYPE_AP=%d\n", __FUNCTION__,
++	       vif->type, NL80211_IFTYPE_AP);
++	if ((sc->nvif >= SSV6200_MAX_VIF)
++	    || (((vif->type == NL80211_IFTYPE_AP)
++		 || (vif->p2p))
++		&& (sc->ap_vif != NULL))) {
++		dev_err(sc->dev, "Add interface of type %d (p2p: %d) failed.\n",
++			vif->type, vif->p2p);
++		return -EOPNOTSUPP;
++	}
++	mutex_lock(&sc->mutex);
++	vif_priv = ssv6xxx_config_vif_res(sc, vif);
++	if ((vif_priv->vif_idx == 0) && (vif->p2p == 0)
++	    && (vif->type == NL80211_IFTYPE_AP)) {
++		dev_dbg(sc->dev, "VIF[0] set bssid and config opmode to ap\n");
++		ssv62xxx_set_bssid(sc, sc->sh->cfg.maddr[0]);
++		SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_AP,
++				  OP_MODE_MSK);
++	}
++	if (vif->type == NL80211_IFTYPE_AP) {
++		BUG_ON(sc->ap_vif != NULL);
++		sc->ap_vif = vif;
++		if (!vif->p2p && (vif_priv->vif_idx == 0)) {
++			dev_dbg(sc->dev, "Normal AP mode. Config Q4 to DTIM Q.\n");
++			SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
++					  MTX_HALT_MNG_UNTIL_DTIM_MSK,
++					  MTX_HALT_MNG_UNTIL_DTIM_MSK);
++			sc->bq4_dtim = true;
++		}
++	}
++	sc->nvif++;
++	dev_dbg(sc->dev,
++		"VIF %02x:%02x:%02x:%02x:%02x:%02x of type %d is added.\n",
++		vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
++		vif->addr[4], vif->addr[5], vif->type);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_debugfs_add_interface(sc, vif);
++#endif
++	mutex_unlock(&sc->mutex);
++	return ret;
++}
++
++static void ssv6200_remove_interface(struct ieee80211_hw *hw,
++				     struct ieee80211_vif *vif)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	dev_err(sc->dev,
++		"Removing interface %02x:%02x:%02x:%02x:%02x:%02x. PS=%d\n",
++		vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
++		vif->addr[4], vif->addr[5], sc->ps_status);
++	mutex_lock(&sc->mutex);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_debugfs_remove_interface(sc, vif);
++#endif
++	if (vif->type == NL80211_IFTYPE_AP) {
++		if (sc->bq4_dtim) {
++			sc->bq4_dtim = false;
++			ssv6200_release_bcast_frame_res(sc, vif);
++			SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
++					  0, MTX_HALT_MNG_UNTIL_DTIM_MSK);
++			dev_dbg(sc->dev, "Config Q4 to normal Q \n");
++		}
++		ssv6xxx_beacon_release(sc);
++		sc->ap_vif = NULL;
++	}
++	memset(&sc->vif_info[vif_priv->vif_idx], 0,
++	       sizeof(struct ssv_vif_info));
++	sc->nvif--;
++	mutex_unlock(&sc->mutex);
++}
++
++static int ssv6200_change_interface(struct ieee80211_hw *dev,
++				    struct ieee80211_vif *vif,
++				    enum nl80211_iftype new_type, bool p2p)
++{
++    struct ssv_softc *sc = dev->priv;
++	int ret = 0;
++    
++	dev_dbg(sc->dev, "change_interface new: %d (%d), old: %d (%d)\n", new_type,
++	       p2p, vif->type, vif->p2p);
++
++	if (new_type != vif->type || vif->p2p != p2p) {
++		ssv6200_remove_interface(dev, vif);
++		vif->type = new_type;
++		vif->p2p = p2p;
++		ret = ssv6200_add_interface(dev, vif);
++	}
++
++	return ret;
++}
++
++void ssv6xxx_ps_callback_func(unsigned long data)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)data;
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int retry_cnt = 20;
++#ifdef SSV_WAKEUP_HOST
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++	SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
++		       (sc->mac_deci_tbl[6] | 1));
++#else
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
++#endif
++	skb = ssv_skb_alloc(sizeof(struct cfg_host_cmd));
++	skb->data_len = sizeof(struct cfg_host_cmd);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->RSVD0 = 0;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
++	host_cmd->len = skb->data_len;
++#ifdef SSV_WAKEUP_HOST
++	host_cmd->dummy = sc->ps_aid;
++#else
++	host_cmd->dummy = 0;
++#endif
++	sc->ps_aid = 0;
++	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
++		dev_warn(sc->dev, "PS cmd retry=%d!!\n", retry_cnt);
++		retry_cnt--;
++	}
++	ssv_skb_free(skb);
++	dev_dbg(sc->dev, "SSV6XXX_HOST_CMD_PS,ps_aid = %d,len=%d,tabl=0x%x\n",
++	       host_cmd->dummy, skb->len, (sc->mac_deci_tbl[6] | 1));
++}
++
++void ssv6xxx_enable_ps(struct ssv_softc *sc)
++{
++	sc->ps_status = PWRSV_ENABLE;
++}
++
++void ssv6xxx_disable_ps(struct ssv_softc *sc)
++{
++	sc->ps_status = PWRSV_DISABLE;
++	dev_info(sc->dev, "Power saving disabled\n");
++}
++
++int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int ret = 0;
++	dev_dbg(sh->sc->dev, "ssv6xxx_watchdog_controller %d\n", flag);
++	skb = ssv_skb_alloc(HOST_CMD_HDR_LEN);
++	if (skb == NULL) {
++		dev_warn(sh->sc->dev, "init ssv6xxx_watchdog_controller fail!!!\n");
++		return (-1);
++	}
++	skb->data_len = HOST_CMD_HDR_LEN;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) flag;
++	host_cmd->len = skb->data_len;
++	sh->hci.hci_ops->hci_send_cmd(skb);
++	ssv_skb_free(skb);
++	return ret;
++}
++
++static int ssv6200_config(struct ieee80211_hw *hw, u32 changed)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	mutex_lock(&sc->mutex);
++	if (changed & IEEE80211_CONF_CHANGE_PS) {
++		struct ieee80211_conf *conf = &hw->conf;
++		if (conf->flags & IEEE80211_CONF_PS) {
++			dev_dbg(sc->dev, "Enable IEEE80211_CONF_PS ps_aid=%d\n",
++			       sc->ps_aid);
++		} else {
++			dev_dbg(sc->dev, "Disable IEEE80211_CONF_PS ps_aid=%d\n",
++			       sc->ps_aid);
++		}
++	}
++	if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
++		struct ieee80211_channel *chan;
++		chan = hw->conf.chandef.chan;
++#ifdef CONFIG_P2P_NOA
++		if (sc->p2p_noa.active_noa_vif) {
++			dev_dbg(sc->dev, "NOA operating-active vif[%02x] skip scan\n",
++			       sc->p2p_noa.active_noa_vif);
++			goto out;
++		}
++#endif
++		if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) {
++			if ((sc->ap_vif == NULL)
++			    ||
++			    list_empty(&
++				       ((struct ssv_vif_priv_data *)sc->ap_vif->
++					drv_priv)->sta_list)) {
++				HCI_PAUSE(sc->sh,
++					  (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
++					   | TXQ_EDCA_3 | TXQ_MGMT));
++				sc->sc_flags |= SC_OP_OFFCHAN;
++				ssv6xxx_set_channel(sc, chan->hw_value);
++				sc->hw_chan = chan->hw_value;
++				HCI_RESUME(sc->sh, TXQ_MGMT);
++			} else {
++				dev_dbg(sc->dev,
++					"Off-channel to %d is ignored when AP mode enabled.\n",
++					chan->hw_value);
++			}
++		} else {
++			if ((sc->cur_channel == NULL)
++			    || (sc->sc_flags & SC_OP_OFFCHAN)
++			    || (sc->hw_chan != chan->hw_value)) {
++				HCI_PAUSE(sc->sh,
++					  (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
++					   | TXQ_EDCA_3 | TXQ_MGMT));
++				ssv6xxx_set_channel(sc, chan->hw_value);
++				sc->cur_channel = chan;
++				HCI_RESUME(sc->sh,
++					   (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
++					    | TXQ_EDCA_3 | TXQ_MGMT));
++				sc->sc_flags &= ~SC_OP_OFFCHAN;
++			} else {
++				dev_dbg(sc->dev,
++					"Change to the same channel %d\n",
++					chan->hw_value);
++			}
++		}
++	}
++#ifdef CONFIG_P2P_NOA
++ out:
++#endif
++	mutex_unlock(&sc->mutex);
++	return ret;
++}
++
++#define SUPPORTED_FILTERS \
++    (FIF_ALLMULTI | \
++    FIF_CONTROL | \
++    FIF_PSPOLL | \
++    FIF_OTHER_BSS | \
++    FIF_BCN_PRBRESP_PROMISC | \
++    FIF_PROBE_REQ | \
++    FIF_FCSFAIL)
++static void ssv6200_config_filter(struct ieee80211_hw *hw,
++				  unsigned int changed_flags,
++				  unsigned int *total_flags, u64 multicast)
++{
++	changed_flags &= SUPPORTED_FILTERS;
++	*total_flags &= SUPPORTED_FILTERS;
++}
++
++static void ssv6200_bss_info_changed(struct ieee80211_hw *hw,
++				     struct ieee80211_vif *vif,
++				     struct ieee80211_bss_conf *info,
++				     u64 changed)
++{
++	struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_softc *sc = hw->priv;
++#ifdef CONFIG_P2P_NOA
++	u8 null_address[6] = { 0 };
++#endif
++	mutex_lock(&sc->mutex);
++	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
++		dev_dbg(sc->dev, "BSS Changed use_short_preamble[%d]\n",
++		       info->use_short_preamble);
++		if (info->use_short_preamble)
++			sc->sc_flags |= SC_OP_SHORT_PREAMBLE;
++		else
++			sc->sc_flags &= ~SC_OP_SHORT_PREAMBLE;
++	}
++	if (!priv_vif->vif_idx) {
++		if (changed & BSS_CHANGED_BSSID) {
++#ifdef CONFIG_P2P_NOA
++			struct ssv_vif_priv_data *vif_priv;
++			vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
++#endif
++			ssv62xxx_set_bssid(sc, (u8 *) info->bssid);
++			dev_dbg(sc->dev, "BSS_CHANGED_BSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
++			     info->bssid[0], info->bssid[1], info->bssid[2],
++			     info->bssid[3], info->bssid[4], info->bssid[5]);
++#ifdef CONFIG_P2P_NOA
++			if (memcmp(info->bssid, null_address, 6))
++				ssv6xxx_noa_hdl_bss_change(sc,
++							   MONITOR_NOA_CONF_ADD,
++							   vif_priv->vif_idx);
++			else
++				ssv6xxx_noa_hdl_bss_change(sc,
++							   MONITOR_NOA_CONF_REMOVE,
++							   vif_priv->vif_idx);
++#endif
++		}
++		if (changed & BSS_CHANGED_ERP_SLOT) {
++			u32 regval = 0;
++			dev_dbg(sc->dev, "BSS_CHANGED_ERP_SLOT: use_short_slot[%d]\n",
++			       info->use_short_slot);
++			if (info->use_short_slot) {
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
++				regval = regval & MTX_DUR_SLOT_I_MSK;
++				regval |= 9 << MTX_DUR_SLOT_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
++					      &regval);
++				regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
++				regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
++				regval = regval & MTX_DUR_SLOT_G_I_MSK;
++				regval |= 9 << MTX_DUR_SLOT_G_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
++					       regval);
++			} else {
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
++				regval = regval & MTX_DUR_SLOT_I_MSK;
++				regval |= 20 << MTX_DUR_SLOT_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
++					      &regval);
++				regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
++				regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
++				regval = regval & MTX_DUR_SLOT_G_I_MSK;
++				regval |= 20 << MTX_DUR_SLOT_G_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
++					       regval);
++			}
++		}
++	}
++	if (changed & BSS_CHANGED_HT) {
++		dev_dbg(sc->dev, "BSS_CHANGED_HT: Untreated!!\n");
++	}
++	if (changed & BSS_CHANGED_BASIC_RATES) {
++		dev_dbg(sc->dev, "ssv6xxx_rc_update_basic_rate!!\n");
++		ssv6xxx_rc_update_basic_rate(sc, info->basic_rates);
++	}
++	if (vif->type == NL80211_IFTYPE_STATION) {
++		dev_dbg(sc->dev, "NL80211_IFTYPE_STATION!!\n");
++		if ((changed & BSS_CHANGED_ASSOC) && (vif->p2p == 0)) {
++			sc->isAssoc = vif->cfg.assoc;
++			if (!sc->isAssoc) {
++				sc->channel_center_freq = 0;
++				sc->ps_aid = 0;
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
++#endif
++				SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL,
++					       0x0);
++			} else {
++				struct ieee80211_channel *curchan;
++				curchan = hw->conf.chandef.chan;
++				sc->channel_center_freq = curchan->center_freq;
++				dev_dbg(sc->dev, "info->aid = %d\n", vif->cfg.aid);
++				sc->ps_aid = vif->cfg.aid;
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
++#endif
++			}
++		}
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++		else if ((changed & BSS_CHANGED_ASSOC) && vif->p2p == 1) {
++			if (info->assoc)
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
++			else if (sc->ps_aid != 0)
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
++		}
++#endif
++	}
++	if (vif->type == NL80211_IFTYPE_AP) {
++		if (changed & (BSS_CHANGED_BEACON
++			       | BSS_CHANGED_SSID
++			       | BSS_CHANGED_BSSID | BSS_CHANGED_BASIC_RATES)) {
++#ifdef BROADCAST_DEBUG
++			dev_dbg(sc->dev, "[A] ssv6200_bss_info_changed:beacon changed\n");
++#endif
++			queue_work(sc->config_wq, &sc->set_tim_work);
++		}
++		if (changed & BSS_CHANGED_BEACON_INT) {
++			dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_INT beacon_interval(%d)\n",
++			     info->beacon_int);
++			if (sc->beacon_interval != info->beacon_int) {
++				sc->beacon_interval = info->beacon_int;
++				ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
++							sc->beacon_dtim_cnt);
++			}
++		}
++		if (changed & BSS_CHANGED_BEACON_ENABLED) {
++#ifdef BEACON_DEBUG
++			dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_ENABLED (0x%x)\n",
++			       info->enable_beacon);
++#endif
++			if (0 != ssv6xxx_beacon_enable(sc, info->enable_beacon)) {
++				dev_err(sc->dev, "Beacon enable %d error.\n",
++					info->enable_beacon);
++			}
++		}
++	}
++	mutex_unlock(&sc->mutex);
++	dev_dbg(sc->dev, "[I] %s(): leave\n", __FUNCTION__);
++}
++
++static int ssv6200_sta_add(struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, struct ieee80211_sta *sta)
++{
++	struct ssv_sta_priv_data *sta_priv_dat = NULL;
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info;
++	u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
++	int s, i;
++	u32 reg_wsid_tid0[] = { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
++	u32 reg_wsid_tid7[] = { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
++	unsigned long flags;
++	int ret = 0;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	int fw_sec_caps = SSV6XXX_WSID_SEC_NONE;
++	bool tdls_use_sw_cipher = false, tdls_link = false;
++	dev_dbg(sc->dev, "[I] %s(): vif[%d] ", __FUNCTION__, vif_priv->vif_idx);
++	if (sc->force_triger_reset == true) {
++		vif_priv->sta_asleep_mask = 0;
++		do {
++			spin_lock_irqsave(&sc->ps_state_lock, flags);
++			for (s = 0; s < SSV_NUM_STA; s++, sta_info++) {
++				sta_info = &sc->sta_info[s];
++				if ((sta_info->s_flags & STA_FLAG_VALID)) {
++					if (sta_info->sta == sta) {
++						dev_dbg
++						    (sc->dev, "search stat %02x:%02x:%02x:%02x:%02x:%02x to  wsid=%d\n",
++						     sta->addr[0], sta->addr[1],
++						     sta->addr[2], sta->addr[3],
++						     sta->addr[4], sta->addr[5],
++						     sta_info->hw_wsid);
++						spin_unlock_irqrestore(&sc->
++								       ps_state_lock,
++								       flags);
++						return ret;
++					}
++				}
++			}
++			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++			if (s >= SSV_NUM_STA) {
++				break;
++			}
++		} while (0);
++	}
++	do {
++		spin_lock_irqsave(&sc->ps_state_lock, flags);
++		if (!list_empty(&vif_priv->sta_list)
++		    && vif->type == NL80211_IFTYPE_STATION) {
++			tdls_link = true;
++		}
++		if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_NONE)
++		    && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
++		    && (sc->sh->cfg.use_wpa2_only == false)) {
++			tdls_use_sw_cipher = true;
++		}
++		if (((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false))
++		    || sc->sh->cfg.use_wpa2_only)
++			s = 0;
++		else
++			s = 2;
++		for (; s < SSV_NUM_STA; s++) {
++			sta_info = &sc->sta_info[s];
++			if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
++				sta_info->aid = sta->aid;
++				sta_info->sta = sta;
++				sta_info->vif = vif;
++				sta_info->s_flags = STA_FLAG_VALID;
++				sta_priv_dat =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++				sta_priv_dat->sta_idx = s;
++				sta_priv_dat->sta_info = sta_info;
++				sta_priv_dat->has_hw_encrypt = false;
++				sta_priv_dat->has_hw_decrypt = false;
++				sta_priv_dat->need_sw_decrypt = false;
++				sta_priv_dat->need_sw_encrypt = false;
++				sta_priv_dat->use_mac80211_decrypt = false;
++				if ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
++				    || (vif_priv->pair_cipher ==
++					SSV_CIPHER_WEP104)) {
++					sta_priv_dat->has_hw_encrypt =
++					    vif_priv->has_hw_encrypt;
++					sta_priv_dat->has_hw_decrypt =
++					    vif_priv->has_hw_decrypt;
++					sta_priv_dat->need_sw_encrypt =
++					    vif_priv->need_sw_encrypt;
++					sta_priv_dat->need_sw_decrypt =
++					    vif_priv->need_sw_decrypt;
++				}
++				list_add_tail(&sta_priv_dat->list,
++					      &vif_priv->sta_list);
++				break;
++			}
++		}
++		spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++		if (s >= SSV_NUM_STA) {
++			dev_err(sc->dev,
++				"Number of STA exceeds driver limitation %d\n.",
++				SSV_NUM_STA);
++			ret = -1;
++			break;
++		}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		ssv6xxx_debugfs_add_sta(sc, sta_info);
++#endif
++		sta_info->hw_wsid = -1;
++		if (sta_priv_dat->sta_idx < SSV_NUM_HW_STA) {
++			SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 4,
++				       *((u32 *) & sta->addr[0]));
++			SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 8,
++				       *((u32 *) & sta->addr[4]));
++			SMAC_REG_WRITE(sc->sh, reg_wsid[s], 1);
++			for (i = reg_wsid_tid0[s]; i <= reg_wsid_tid7[s];
++			     i += 4)
++				SMAC_REG_WRITE(sc->sh, i, 0);
++			ssv6xxx_rc_hw_reset(sc, sta_priv_dat->rc_idx, s);
++			sta_info->hw_wsid = sta_priv_dat->sta_idx;
++		} else if ((vif_priv->vif_idx == 0)
++			   || sc->sh->cfg.use_wpa2_only) {
++			sta_info->hw_wsid = sta_priv_dat->sta_idx;
++		}
++		if ((sta_priv_dat->has_hw_encrypt
++		     || sta_priv_dat->has_hw_decrypt)
++		    && ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
++			|| (vif_priv->pair_cipher == SSV_CIPHER_WEP104))) {
++			struct ssv_vif_info *vif_info =
++			    &sc->vif_info[vif_priv->vif_idx];
++			struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
++			_set_wep_hw_crypto_pair_key(sc, vif_info, sta_info,
++						    (void *)sramKey);
++			if (sramKey->sta_key[0].pair_key_idx != 0) {
++				_set_wep_hw_crypto_group_key(sc, vif_info,
++							     sta_info,
++							     (void *)sramKey);
++			}
++		}
++		ssv6200_ampdu_tx_add_sta(hw, sta);
++		if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
++			if (sta_priv_dat->has_hw_decrypt)
++				fw_sec_caps = SSV6XXX_WSID_SEC_PAIRWISE;
++			if (vif_priv->has_hw_decrypt)
++				fw_sec_caps |= SSV6XXX_WSID_SEC_GROUP;
++			hw_update_watch_wsid(sc, sta, sta_info,
++					     sta_priv_dat->sta_idx, fw_sec_caps,
++					     SSV6XXX_WSID_OPS_ADD);
++		} else if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)) {
++			hw_update_watch_wsid(sc, sta, sta_info,
++					     sta_priv_dat->sta_idx,
++					     SSV6XXX_WSID_SEC_SW,
++					     SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
++			hw_update_watch_wsid(sc, sta, sta_info,
++					     sta_priv_dat->sta_idx,
++					     SSV6XXX_WSID_SEC_SW,
++					     SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
++		}
++		dev_dbg
++		    (sc->dev, "Add %02x:%02x:%02x:%02x:%02x:%02x to VIF %d sw_idx=%d, wsid=%d\n",
++		     sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		     sta->addr[4], sta->addr[5], vif_priv->vif_idx,
++		     sta_priv_dat->sta_idx, sta_info->hw_wsid);
++	} while (0);
++	return ret;
++}
++
++void ssv6200_rx_flow_check(struct ssv_sta_priv_data *sta_priv_dat,
++			   struct ssv_softc *sc)
++{
++	if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)
++	    && (sta_priv_dat->need_sw_decrypt)) {
++		int other_hw_wsid = (sta_priv_dat->sta_idx + 1) & 1;
++		struct ssv_sta_info *sta_info = &sc->sta_info[other_hw_wsid];
++		struct ieee80211_sta *sta = sta_info->sta;
++		struct ssv_sta_priv_data *sta_priv =
++		    (struct ssv_sta_priv_data *)sta->drv_priv;
++		mutex_lock(&sc->mutex);
++		if ((sta_info->s_flags == 0)
++		    || ((sta_info->s_flags && STA_FLAG_VALID)
++			&& (sta_priv->has_hw_decrypt))) {
++			SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++				       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
++				       (M_ENG_HWHCI << 8));
++			dev_dbg(sc->dev, "redirect Rx flow for sta %d disconnect\n",
++			       sta_priv_dat->sta_idx);
++		}
++		mutex_unlock(&sc->mutex);
++	}
++}
++
++static int ssv6200_sta_remove(struct ieee80211_hw *hw,
++			      struct ieee80211_vif *vif,
++			      struct ieee80211_sta *sta)
++{
++	u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
++	struct ssv_sta_priv_data *sta_priv_dat =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info = sta_priv_dat->sta_info;
++	unsigned long flags;
++	u32 bit;
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	u8 hw_wsid = -1;
++	BUG_ON(sta_priv_dat->sta_idx >= SSV_NUM_STA);
++	dev_notice(sc->dev,
++		   "Removing STA %d (%02X:%02X:%02X:%02X:%02X:%02X) from VIF %d\n.",
++		   sta_priv_dat->sta_idx, sta->addr[0], sta->addr[1],
++		   sta->addr[2], sta->addr[3], sta->addr[4], sta->addr[5],
++		   priv_vif->vif_idx);
++	ssv6200_rx_flow_check(sta_priv_dat, sc);
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	bit = BIT(sta_priv_dat->sta_idx);
++	priv_vif->sta_asleep_mask &= ~bit;
++	if (sta_info->hw_wsid != -1) {
++		hw_wsid = sta_info->hw_wsid;
++	}
++	if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
++		spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++		hw_update_watch_wsid(sc, sta, sta_info, sta_info->hw_wsid, 0,
++				     SSV6XXX_WSID_OPS_DEL);
++		spin_lock_irqsave(&sc->ps_state_lock, flags);
++	}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	{
++		ssv6xxx_debugfs_remove_sta(sc, sta_info);
++	}
++#endif
++	memset(sta_info, 0, sizeof(*sta_info));
++	sta_priv_dat->sta_idx = -1;
++	list_del(&sta_priv_dat->list);
++	if (list_empty(&priv_vif->sta_list)
++	    && vif->type == NL80211_IFTYPE_STATION) {
++		priv_vif->pair_cipher = 0;
++		priv_vif->group_cipher = 0;
++	}
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++	if ((hw_wsid != -1) && (hw_wsid < SSV_NUM_HW_STA))
++		SMAC_REG_WRITE(sc->sh, reg_wsid[hw_wsid], 0x00);
++	return 0;
++}
++
++static void ssv6200_sta_notify(struct ieee80211_hw *hw,
++			       struct ieee80211_vif *vif,
++			       enum sta_notify_cmd cmd,
++			       struct ieee80211_sta *sta)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_sta_priv_data *sta_priv_dat =
++	    sta != NULL ? (struct ssv_sta_priv_data *)sta->drv_priv : NULL;
++	struct ssv_sta_info *sta_info;
++	u32 bit, prev;
++	unsigned long flags;
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	if (sta_priv_dat != NULL) {
++		bit = BIT(sta_priv_dat->sta_idx);
++		prev = priv_vif->sta_asleep_mask & bit;
++		sta_info = sta_priv_dat->sta_info;
++		switch (cmd) {
++		case STA_NOTIFY_SLEEP:
++			if (!prev) {
++				sta_info->sleeping = true;
++				if ((vif->type == NL80211_IFTYPE_AP)
++				    && sc->bq4_dtim
++				    && !priv_vif->sta_asleep_mask
++				    && ssv6200_bcast_queue_len(&sc->
++							       bcast_txq)) {
++					dev_dbg(sc->dev, "%s(): ssv6200_bcast_start\n", __FUNCTION__);
++					ssv6200_bcast_start(sc);
++				}
++				priv_vif->sta_asleep_mask |= bit;
++			}
++			break;
++		case STA_NOTIFY_AWAKE:
++			if (prev) {
++				sta_info->sleeping = false;
++				priv_vif->sta_asleep_mask &= ~bit;
++			}
++			break;
++		default:
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++}
++
++static u64 ssv6200_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
++{
++	return jiffies * 1000 * 1000 / HZ;
++}
++
++static u64 ssv6200_get_systime_us(void)
++{
++#if LINUX_VERSION_CODE > KERNEL_VERSION(4,19,0)
++	struct timespec64 ts;
++	ktime_get_boottime_ts64(&ts);
++#else
++	struct timespec ts;
++	get_monotonic_boottime(&ts);
++#endif
++	return ((u64) ts.tv_sec * 1000000) + ts.tv_nsec / 1000;
++}
++
++static u32 pre_11b_cca_control;
++static u32 pre_11b_cca_1;
++static void ssv6200_sw_scan_start(struct ieee80211_hw *hw,
++				  struct ieee80211_vif *vif,
++				  const u8 * mac_addr)
++{
++	((struct ssv_softc *)(hw->priv))->bScanning = true;
++	SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh,
++		      ADR_RX_11B_CCA_CONTROL, &pre_11b_cca_control);
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
++		       ADR_RX_11B_CCA_CONTROL, 0x0);
++	SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
++		      &pre_11b_cca_1);
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
++		       RX_11B_CCA_IN_SCAN);
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_MRX_FLT_EN3,
++		       0x0400);
++#endif
++}
++
++static void ssv6200_sw_scan_complete(struct ieee80211_hw *hw,
++				     struct ieee80211_vif *vif)
++{
++
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++	bool is_p2p_assoc;
++#endif
++	((struct ssv_softc *)(hw->priv))->bScanning = false;
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
++		       ADR_RX_11B_CCA_CONTROL, pre_11b_cca_control);
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
++		       pre_11b_cca_1);
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++	is_p2p_assoc =
++	    ((struct ssv_softc *)(hw->priv))->vif_info[1].vif->bss_conf.assoc;
++	if (((struct ssv_softc *)(hw->priv))->ps_aid != 0 && (!is_p2p_assoc))
++		SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
++			       ADR_MRX_FLT_EN3, 0x1000);
++#endif
++}
++
++static int ssv6200_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
++			   bool set)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info = sta
++	    ? ((struct ssv_sta_priv_data *)sta->drv_priv)->sta_info : NULL;
++	if (sta_info && (sta_info->tim_set ^ set)) {
++        dev_dbg(sc->dev, "[I] [A] ssvcabrio_set_tim");
++		sta_info->tim_set = set;
++		queue_work(sc->config_wq, &sc->set_tim_work);
++	}
++	return 0;
++}
++
++static int ssv6200_conf_tx(struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, u32 link_id, u16 queue,
++			   const struct ieee80211_tx_queue_params *params)
++{
++	struct ssv_softc *sc = hw->priv;
++	u32 cw;
++	u8 hw_txqid = sc->tx.hw_txqid[queue];
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	dev_dbg
++	    (sc->dev, "[I] sv6200_conf_tx vif[%d] qos[%d] queue[%d] aifsn[%d] cwmin[%d] cwmax[%d] txop[%d] \n",
++	     priv_vif->vif_idx, vif->bss_conf.qos, queue, params->aifs,
++	     params->cw_min, params->cw_max, params->txop);
++	if (queue > NL80211_TXQ_Q_BK)
++		return 1;
++	if (priv_vif->vif_idx != 0) {
++		dev_warn(sc->dev,
++			 "WMM setting applicable to primary interface only.\n");
++		return 1;
++	}
++	mutex_lock(&sc->mutex);
++	SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET,
++			  (vif->bss_conf.qos << QOS_EN_SFT), QOS_EN_MSK);
++	cw = (params->aifs - 1) & 0xf;
++	cw |= ((ilog2(params->cw_min + 1)) & 0xf) << TXQ1_MTX_Q_ECWMIN_SFT;
++	cw |= ((ilog2(params->cw_max + 1)) & 0xf) << TXQ1_MTX_Q_ECWMAX_SFT;
++	cw |= ((params->txop) & 0xff) << TXQ1_MTX_Q_TXOP_LIMIT_SFT;
++	SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_AIFSN + 0x100 * hw_txqid, cw);
++	mutex_unlock(&sc->mutex);
++	return 0;
++}
++
++static int ssv6200_ampdu_action(struct ieee80211_hw *hw,
++				struct ieee80211_vif *vif,
++				struct ieee80211_ampdu_params *params)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	struct ieee80211_sta *sta = params->sta;
++	enum ieee80211_ampdu_mlme_action action = params->action;
++	u16 tid = params->tid;
++	u16 *ssn = &(params->ssn);
++	u8 buf_size = params->buf_size;
++	if (sta == NULL)
++		return ret;
++#if (!Enable_AMPDU_Rx)
++	if (action == IEEE80211_AMPDU_RX_START
++	    || action == IEEE80211_AMPDU_RX_STOP) {
++		ampdu_db_log("Disable AMPDU_RX for test(1).\n");
++		return -EOPNOTSUPP;
++	}
++#endif
++#if (!Enable_AMPDU_Tx)
++	if (action == IEEE80211_AMPDU_TX_START
++	    || action == IEEE80211_AMPDU_TX_STOP
++	    || action == IEEE80211_AMPDU_TX_OPERATIONAL) {
++		ampdu_db_log("Disable AMPDU_TX for test(1).\n");
++		return -EOPNOTSUPP;
++	}
++#endif
++	if ((action == IEEE80211_AMPDU_RX_START
++	     || action == IEEE80211_AMPDU_RX_STOP)
++	    && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX))) {
++		ampdu_db_log("Disable AMPDU_RX(2).\n");
++		return -EOPNOTSUPP;
++	}
++	if ((action == IEEE80211_AMPDU_TX_START
++	     || action == IEEE80211_AMPDU_TX_STOP_CONT
++	     || action == IEEE80211_AMPDU_TX_STOP_FLUSH
++	     || action == IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
++	     || action == IEEE80211_AMPDU_TX_OPERATIONAL)
++	    && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
++		ampdu_db_log("Disable AMPDU_TX(2).\n");
++		return -EOPNOTSUPP;
++	}
++	switch (action) {
++	case IEEE80211_AMPDU_RX_START:
++#ifdef WIFI_CERTIFIED
++		if (sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS) {
++			ieee80211_stop_rx_ba_session(vif,
++						     (1 << (sc->ba_tid)),
++						     sc->ba_ra_addr);
++			sc->rx_ba_session_count--;
++		}
++#else
++		if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
++		    && (sc->rx_ba_sta != sta)) {
++			ret = -EBUSY;
++			break;
++		} else
++		    if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
++			&& (sc->rx_ba_sta == sta)) {
++			ieee80211_stop_rx_ba_session(vif, (1 << (sc->ba_tid)),
++						     sc->ba_ra_addr);
++			sc->rx_ba_session_count--;
++		}
++#endif
++		dev_dbg(sc->dev, "IEEE80211_AMPDU_RX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		sc->rx_ba_session_count++;
++		sc->rx_ba_sta = sta;
++		sc->ba_tid = tid;
++		sc->ba_ssn = *ssn;
++		memcpy(sc->ba_ra_addr, sta->addr, ETH_ALEN);
++		queue_work(sc->config_wq, &sc->set_ampdu_rx_add_work);
++		break;
++	case IEEE80211_AMPDU_RX_STOP:
++		sc->rx_ba_session_count--;
++		if (sc->rx_ba_session_count == 0)
++			sc->rx_ba_sta = NULL;
++		queue_work(sc->config_wq, &sc->set_ampdu_rx_del_work);
++		break;
++	case IEEE80211_AMPDU_TX_START:
++		dev_dbg(sc->dev, "AMPDU_TX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		ssv6200_ampdu_tx_start(tid, sta, hw, ssn);
++		ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
++		break;
++	case IEEE80211_AMPDU_TX_STOP_CONT:
++	case IEEE80211_AMPDU_TX_STOP_FLUSH:
++	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
++		dev_dbg(sc->dev, "AMPDU_TX_STOP %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		ssv6200_ampdu_tx_stop(tid, sta, hw);
++		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
++		break;
++	case IEEE80211_AMPDU_TX_OPERATIONAL:
++		dev_dbg(sc->dev, "AMPDU_TX_OPERATIONAL %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		ssv6200_ampdu_tx_operation(tid, sta, hw, buf_size);
++		break;
++	default:
++		ret = -EOPNOTSUPP;
++		break;
++	}
++	return ret;
++}
++
++#ifdef CONFIG_PM
++int ssv6xxx_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
++{
++	return 0;
++}
++
++int ssv6xxx_resume(struct ieee80211_hw *hw)
++{
++	return 0;
++}
++#endif
++struct ieee80211_ops ssv6200_ops = {
++	.tx = ssv6200_tx,
++	.start = ssv6200_start,
++	.stop = ssv6200_stop,
++	.add_interface = ssv6200_add_interface,
++	.remove_interface = ssv6200_remove_interface,
++	.change_interface = ssv6200_change_interface,
++	.config = ssv6200_config,
++	.configure_filter = ssv6200_config_filter,
++	.bss_info_changed = ssv6200_bss_info_changed,
++	.sta_add = ssv6200_sta_add,
++	.sta_remove = ssv6200_sta_remove,
++	.sta_notify = ssv6200_sta_notify,
++	.set_key = ssv6200_set_key,
++	.sw_scan_start = ssv6200_sw_scan_start,
++	.sw_scan_complete = ssv6200_sw_scan_complete,
++	.get_tsf = ssv6200_get_tsf,
++	.set_tim = ssv6200_set_tim,
++	.conf_tx = ssv6200_conf_tx,
++	.ampdu_action = ssv6200_ampdu_action,
++	.wake_tx_queue = ieee80211_handle_wake_tx_queue,
++#ifdef CONFIG_PM
++	.suspend = ssv6xxx_suspend,
++	.resume = ssv6xxx_resume,
++#endif
++};
++
++int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug)
++{
++	struct ssv_softc *sc = dev;
++	int ac;
++	BUG_ON(hw_txqid > 4);
++	if (hw_txqid == 4)
++		return 0;
++	ac = sc->tx.ac_txqid[hw_txqid];
++	if (fc_en == false) {
++		if (sc->tx.flow_ctrl_status & (1 << ac)) {
++			ieee80211_wake_queue(sc->hw, ac);
++			sc->tx.flow_ctrl_status &= ~(1 << ac);
++		} else {
++		}
++	} else {
++		if ((sc->tx.flow_ctrl_status & (1 << ac)) == 0) {
++			ieee80211_stop_queue(sc->hw, ac);
++			sc->tx.flow_ctrl_status |= (1 << ac);
++		} else {
++		}
++	}
++	return 0;
++}
++
++void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *cb_data)
++{
++	struct ssv_softc *sc = cb_data;
++	BUG_ON(sc == NULL);
++	sc->tx_q_empty = true;
++	smp_mb();
++	wake_up_interruptible(&sc->tx_wait_q);
++}
++
++struct ssv6xxx_b_cca_control {
++	u32 down_level;
++	u32 upper_level;
++	u32 adjust_cca_control;
++	u32 adjust_cca_1;
++};
++struct ssv6xxx_b_cca_control adjust_cci[] = {
++	{0, 43, 0x00162000, 0x20380050},
++	{40, 48, 0x00161000, 0x20380050},
++	{45, 53, 0x00160800, 0x20380050},
++	{50, 63, 0x00160400, 0x20380050},
++	{60, 68, 0x00160200, 0x20380050},
++	{65, 73, 0x00160100, 0x20380050},
++	{70, 128, 0x00000000, 0x20300050},
++};
++
++#define MAX_CCI_LEVEL 128
++static unsigned long last_jiffies = INITIAL_JIFFIES;
++static s32 size = sizeof(adjust_cci) / sizeof(adjust_cci[0]);
++static u32 current_level = MAX_CCI_LEVEL;
++static u32 current_gate = (sizeof(adjust_cci) / sizeof(adjust_cci[0])) - 1;
++void mitigate_cci(struct ssv_softc *sc, u32 input_level)
++{
++	s32 i;
++	if (input_level > MAX_CCI_LEVEL) {
++		dev_dbg(sc->dev, "mitigate_cci input error[%d]!!\n", input_level);
++		return;
++	}
++	if (time_after(jiffies, last_jiffies + msecs_to_jiffies(3000))) {
++		dev_dbg(sc->dev, "jiffies=%lu, input_level=%d\n", jiffies, input_level);
++		last_jiffies = jiffies;
++		if ((input_level >= adjust_cci[current_gate].down_level)
++		    && (input_level <= adjust_cci[current_gate].upper_level)) {
++			current_level = input_level;
++#ifdef DEBUG_MITIGATE_CCI
++			dev_dbg(sc->dev, "Keep the 0xce0020a0[%x] 0xce002008[%x]!!\n",
++			       adjust_cci[current_gate].adjust_cca_control,
++			       adjust_cci[current_gate].adjust_cca_1);
++#endif
++		} else {
++			if (current_level < input_level) {
++				for (i = 0; i < size; i++) {
++					if (input_level <=
++					    adjust_cci[i].upper_level) {
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].upper_level=%d, value=%08x\n",
++						     current_gate, input_level,
++						     i,
++						     adjust_cci[i].upper_level,
++						     adjust_cci[i].
++						     adjust_cca_control);
++#endif
++						current_level = input_level;
++						current_gate = i;
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_CONTROL,
++							       adjust_cci[i].
++							       adjust_cca_control);
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_1,
++							       adjust_cci[i].
++							       adjust_cca_1);
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
++						     adjust_cci[current_gate].
++						     adjust_cca_control,
++						     adjust_cci[current_gate].
++						     adjust_cca_1);
++#endif
++						return;
++					}
++				}
++			} else {
++				for (i = (size - 1); i >= 0; i--) {
++					if (input_level >=
++					    adjust_cci[i].down_level) {
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].down_level=%d, value=%08x\n",
++						     current_gate, input_level,
++						     i,
++						     adjust_cci[i].down_level,
++						     adjust_cci[i].
++						     adjust_cca_control);
++#endif
++						current_level = input_level;
++						current_gate = i;
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_CONTROL,
++							       adjust_cci[i].
++							       adjust_cca_control);
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_1,
++							       adjust_cci[i].
++							       adjust_cca_1);
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
++						     adjust_cci[current_gate].
++						     adjust_cca_control,
++						     adjust_cci[current_gate].
++						     adjust_cca_1);
++#endif
++						return;
++					}
++				}
++			}
++		}
++	}
++}
++
++#define RSSI_SMOOTHING_SHIFT 5
++#define RSSI_DECIMAL_POINT_SHIFT 6
++static void _proc_data_rx_skb(struct ssv_softc *sc, struct sk_buff *rx_skb)
++{
++	struct ieee80211_rx_status *rxs;
++	struct ieee80211_hdr *hdr;
++	__le16 fc;
++	struct ssv6200_rx_desc *rxdesc;
++	struct ssv6200_rxphy_info_padding *rxphypad;
++	struct ssv6200_rxphy_info *rxphy;
++	struct ieee80211_channel *chan;
++	struct ieee80211_vif *vif = NULL;
++	struct ieee80211_sta *sta = NULL;
++	bool rx_hw_dec = false;
++	bool do_sw_dec = false;
++	struct ssv_sta_priv_data *sta_priv = NULL;
++	struct ssv_vif_priv_data *vif_priv = NULL;
++	SKB_info *skb_info = NULL;
++	u8 is_beacon;
++	u8 is_probe_resp;
++	s32 found = 0;
++#ifdef CONFIG_SSV_SMARTLINK
++	{
++		extern int ksmartlink_smartlink_started(void);
++		void smartlink_nl_send_msg(struct sk_buff *skb);
++		if (unlikely(ksmartlink_smartlink_started())) {
++			skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
++			skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
++			smartlink_nl_send_msg(rx_skb);
++			return;
++		}
++	}
++#endif
++	rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
++	rxphy = (struct ssv6200_rxphy_info *)(rx_skb->data + sizeof(*rxdesc));
++	rxphypad =
++	    (struct ssv6200_rxphy_info_padding *)(rx_skb->data + rx_skb->len -
++						  sizeof(struct
++							 ssv6200_rxphy_info_padding));
++	hdr = (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
++	fc = hdr->frame_control;
++	skb_info = (SKB_info *) rx_skb->head;
++	if (rxdesc->wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
++		if ((ieee80211_is_data(hdr->frame_control))
++		    && (!(ieee80211_is_nullfunc(hdr->frame_control)))) {
++			ssv6xxx_rc_rx_data_handler(sc->hw, rx_skb,
++						   rxdesc->rate_idx);
++		}
++	}
++	rxs = IEEE80211_SKB_RXCB(rx_skb);
++	memset(rxs, 0, sizeof(struct ieee80211_rx_status));
++	ssv6xxx_rc_mac8011_rate_idx(sc, rxdesc->rate_idx, rxs);
++
++	rxs->mactime = *((u32 *) & rx_skb->data[28]);
++	chan = sc->hw->conf.chandef.chan;
++	rxs->band = chan->band;
++	rxs->freq = chan->center_freq;
++	rxs->antenna = 1;
++	is_beacon = ieee80211_is_beacon(hdr->frame_control);
++	is_probe_resp = ieee80211_is_probe_resp(hdr->frame_control);
++	if (is_beacon)		//+++
++	{
++		struct ieee80211_mgmt *mgmt_tmp = NULL;
++		mgmt_tmp =
++		    (struct ieee80211_mgmt *)(rx_skb->data +
++					      SSV6XXX_RX_DESC_LEN);
++		mgmt_tmp->u.beacon.timestamp =
++		    cpu_to_le64(ssv6200_get_systime_us());
++	}
++	if (is_probe_resp) {
++		struct ieee80211_mgmt *mgmt_tmp = NULL;
++		mgmt_tmp =
++		    (struct ieee80211_mgmt *)(rx_skb->data +
++					      SSV6XXX_RX_DESC_LEN);
++		mgmt_tmp->u.probe_resp.timestamp =
++		    cpu_to_le64(ssv6200_get_systime_us());
++	}
++
++	if (rxdesc->rate_idx < SSV62XX_G_RATE_INDEX && rxphypad->RSVD == 0) {
++		if (is_beacon || is_probe_resp) {
++			sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++			if (sta) {
++				sta_priv =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "b_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
++				       hdr->addr2[0], hdr->addr2[1],
++				       hdr->addr2[2], hdr->addr2[3],
++				       hdr->addr2[4], hdr->addr2[5],
++				       rxphypad->rpci, rxphypad->snr);
++#endif
++				if (sta_priv->beacon_rssi) {
++					sta_priv->beacon_rssi =
++					    ((rxphypad->
++					      rpci << RSSI_DECIMAL_POINT_SHIFT)
++					     +
++					     ((sta_priv->
++					       beacon_rssi <<
++					       RSSI_SMOOTHING_SHIFT) -
++					      sta_priv->
++					      beacon_rssi)) >>
++					    RSSI_SMOOTHING_SHIFT;
++					rxphypad->rpci =
++					    (sta_priv->
++					     beacon_rssi >>
++					     RSSI_DECIMAL_POINT_SHIFT);
++				} else
++					sta_priv->beacon_rssi =
++					    (rxphypad->
++					     rpci << RSSI_DECIMAL_POINT_SHIFT);
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphypad->rpci);
++#endif
++				mitigate_cci(sc, rxphypad->rpci);
++			} else {
++				mutex_lock(&sc->mutex);
++				list_for_each_entry(p_rssi_res,
++						    &rssi_res.rssi_list,
++						    rssi_list) {
++					if (!memcmp
++					    (p_rssi_res->bssid, hdr->addr2,
++					     ETH_ALEN)) {
++						{
++							p_rssi_res->rssi =
++							    ((rxphypad->
++							      rpci <<
++							      RSSI_DECIMAL_POINT_SHIFT)
++							     +
++							     ((p_rssi_res->
++							       rssi <<
++							       RSSI_SMOOTHING_SHIFT)
++							      -
++							      p_rssi_res->
++							      rssi)) >>
++							    RSSI_SMOOTHING_SHIFT;
++							rxphypad->rpci =
++							    (p_rssi_res->
++							     rssi >>
++							     RSSI_DECIMAL_POINT_SHIFT);
++						}
++						p_rssi_res->cache_jiffies =
++						    jiffies;
++						found = 1;
++						break;
++					} else {
++						if (p_rssi_res->rssi) {
++							if (time_after
++							    (jiffies,
++							     p_rssi_res->
++							     cache_jiffies +
++							     msecs_to_jiffies
++							     (40000))) {
++								p_rssi_res->
++								    timeout = 1;
++							}
++						}
++					}
++				}
++				if (!found) {
++					p_rssi_res =
++					    kmalloc(sizeof(struct rssi_res_st),
++						    GFP_KERNEL);
++					memcpy(p_rssi_res->bssid, hdr->addr2,
++					       ETH_ALEN);
++					p_rssi_res->cache_jiffies = jiffies;
++					p_rssi_res->rssi =
++					    (rxphypad->
++					     rpci << RSSI_DECIMAL_POINT_SHIFT);
++					p_rssi_res->timeout = 0;
++					INIT_LIST_HEAD(&p_rssi_res->rssi_list);
++					list_add_tail_rcu(&
++							  (p_rssi_res->
++							   rssi_list),
++							  &(rssi_res.
++							    rssi_list));
++				}
++				mutex_unlock(&sc->mutex);
++			}
++			if (rxphypad->rpci > 88)
++				rxphypad->rpci = 88;
++		}
++		if (sc->sh->cfg.rssi_ctl) {
++			rxs->signal = (-rxphypad->rpci) + sc->sh->cfg.rssi_ctl;
++		} else {
++			rxs->signal = (-rxphypad->rpci);
++		}
++	} else if (rxdesc->rate_idx >= SSV62XX_G_RATE_INDEX
++		   && rxphy->service == 0) {
++		if (is_beacon || is_probe_resp) {
++			sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++			if (sta) {
++				sta_priv =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "gn_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
++				     hdr->addr2[0], hdr->addr2[1],
++				     hdr->addr2[2], hdr->addr2[3],
++				     hdr->addr2[4], hdr->addr2[5], rxphy->rpci,
++				     rxphy->snr);
++#endif
++				if (sta_priv->beacon_rssi) {
++					sta_priv->beacon_rssi =
++					    ((rxphy->
++					      rpci << RSSI_DECIMAL_POINT_SHIFT)
++					     +
++					     ((sta_priv->
++					       beacon_rssi <<
++					       RSSI_SMOOTHING_SHIFT) -
++					      sta_priv->
++					      beacon_rssi)) >>
++					    RSSI_SMOOTHING_SHIFT;
++					rxphy->rpci =
++					    (sta_priv->
++					     beacon_rssi >>
++					     RSSI_DECIMAL_POINT_SHIFT);
++				} else
++					sta_priv->beacon_rssi =
++					    (rxphy->
++					     rpci << RSSI_DECIMAL_POINT_SHIFT);
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphy->rpci);
++#endif
++			}
++			if (rxphy->rpci > 88)
++				rxphy->rpci = 88;
++		}
++		if (sc->sh->cfg.rssi_ctl) {
++			rxs->signal = (-rxphy->rpci) + sc->sh->cfg.rssi_ctl;
++		} else {
++			rxs->signal = (-rxphy->rpci);
++		}
++	} else {
++#ifdef SSV_RSSI_DEBUG
++		dev_dbg(sc->dev, "########unicast: %d, b_rssi/snr: %d/%d, gn_rssi/snr: %d/%d, rate:%d###############\n",
++		     rxdesc->unicast, (-rxphy->rpci), rxphy->snr,
++		     (-rxphypad->rpci), rxphypad->snr, rxdesc->rate_idx);
++		dev_dbg(sc->dev, "RSSI, %d, rate_idx, %d\n", rxs->signal,
++		       rxdesc->rate_idx);
++		dev_dbg(sc->dev, "rxdesc->RxResult = %x,rxdesc->wsid = %d\n",
++		       rxdesc->RxResult, rxdesc->wsid);
++#endif
++		sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++		if (sta) {
++			sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++			rxs->signal =
++			    -(sta_priv->
++			      beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
++		}
++#ifdef SSV_RSSI_DEBUG
++		dev_dbg(sc->dev, "Others signal %d\n", rxs->signal);
++#endif
++	}
++//    rxs->flag = RX_FLAG_MACTIME_START;          //+++
++	rxs->rx_flags = 0;
++	if (rxphy->aggregate)
++		rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
++	sc->hw_mng_used = rxdesc->mng_used;
++	if ((ieee80211_is_data(fc) || ieee80211_is_data_qos(fc))
++	    && ieee80211_has_protected(fc)) {
++		sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++		if (sta == NULL)
++			goto drop_rx;
++		sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		vif = sta_priv->sta_info->vif;
++		if (vif == NULL)
++			goto drop_rx;
++		if (is_broadcast_ether_addr(hdr->addr1) || is_multicast_ether_addr(hdr->addr1)) {
++			vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
++			rx_hw_dec = vif_priv->has_hw_decrypt;
++			do_sw_dec = vif_priv->need_sw_decrypt;
++		} else {
++			rx_hw_dec = sta_priv->has_hw_decrypt;
++			do_sw_dec = sta_priv->need_sw_decrypt;
++		}
++	}
++	skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
++	skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
++#ifdef CONFIG_P2P_NOA
++	if (is_beacon)
++		ssv6xxx_noa_detect(sc, hdr, rx_skb->len);
++#endif
++	if (rx_hw_dec || do_sw_dec) {
++		hdr = (struct ieee80211_hdr *)rx_skb->data;
++		rxs = IEEE80211_SKB_RXCB(rx_skb);
++		hdr->frame_control =
++		    hdr->
++		    frame_control & ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED));
++		rxs->flag |= (RX_FLAG_DECRYPTED | RX_FLAG_IV_STRIPPED);
++	}
++#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_RX_DATA)
++	local_bh_disable();
++	ieee80211_rx(sc->hw, rx_skb);
++	local_bh_enable();
++#else
++	ieee80211_rx_irqsafe(sc->hw, rx_skb);
++#endif
++	return;
++ drop_rx:
++	dev_kfree_skb_any(rx_skb);
++}
++
++#ifdef IRQ_PROC_RX_DATA
++static struct sk_buff *_proc_rx_skb(struct ssv_softc *sc,
++				    struct sk_buff *rx_skb)
++{
++	struct ieee80211_hdr *hdr =
++	    (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
++	struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
++	if (ieee80211_is_back(hdr->frame_control)
++	    || (rxdesc->c_type == HOST_EVENT))
++		return rx_skb;
++	_proc_data_rx_skb(sc, rx_skb);
++	return NULL;
++}
++#endif
++void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
++		   spinlock_t * rx_q_lock)
++{
++	struct sk_buff *skb;
++	struct ieee80211_hdr *hdr;
++	struct ssv6200_rx_desc *rxdesc;
++	unsigned long flags = 0;
++#ifdef USE_FLUSH_RETRY
++	bool has_ba_processed = false;
++#endif
++	while (1) {
++		if (rx_q_lock != NULL) {
++			spin_lock_irqsave(rx_q_lock, flags);
++			skb = __skb_dequeue(rx_q);
++		} else
++			skb = skb_dequeue(rx_q);
++		if (!skb) {
++			if (rx_q_lock != NULL)
++				spin_unlock_irqrestore(rx_q_lock, flags);
++			break;
++		}
++		sc->rx.rxq_count--;
++		if (rx_q_lock != NULL)
++			spin_unlock_irqrestore(rx_q_lock, flags);
++		rxdesc = (struct ssv6200_rx_desc *)skb->data;
++		if (rxdesc->c_type == HOST_EVENT) {
++			struct cfg_host_event *h_evt =
++			    (struct cfg_host_event *)rxdesc;
++			if (h_evt->h_event == SOC_EVT_NO_BA) {
++				ssv6200_ampdu_no_BA_handler(sc->hw, skb);
++#ifdef USE_FLUSH_RETRY
++				has_ba_processed = true;
++#endif
++			} else if (h_evt->h_event == SOC_EVT_RC_MPDU_REPORT) {
++				skb_queue_tail(&sc->rc_report_queue, skb);
++				if (sc->rc_sample_sechedule == 0)
++					queue_work(sc->rc_sample_workqueue,
++						   &sc->rc_sample_work);
++			} else if (h_evt->h_event == SOC_EVT_SDIO_TEST_COMMAND) {
++				if (h_evt->evt_seq_no == 0) {
++					dev_dbg(sc->dev, "SOC_EVT_SDIO_TEST_COMMAND\n");
++					sc->sdio_rx_evt_size = h_evt->len;
++					sc->sdio_throughput_timestamp = jiffies;
++				} else {
++					sc->sdio_rx_evt_size += h_evt->len;
++					if (time_after
++					    (jiffies,
++					     sc->sdio_throughput_timestamp +
++					     msecs_to_jiffies(1000))) {
++						dev_dbg(sc->dev, "data[%ld] SDIO RX throughput %ld Kbps\n",
++						     sc->sdio_rx_evt_size,
++						     (sc->
++						      sdio_rx_evt_size << 3) /
++						     jiffies_to_msecs(jiffies -
++								      sc->
++								      sdio_throughput_timestamp));
++						sc->sdio_throughput_timestamp =
++						    jiffies;
++						sc->sdio_rx_evt_size = 0;
++					}
++				}
++				dev_kfree_skb_any(skb);
++			} else if (h_evt->h_event == SOC_EVT_WATCHDOG_TRIGGER) {
++				dev_kfree_skb_any(skb);
++//              if(sc->watchdog_flag != WD_SLEEP)     //+++
++				sc->watchdog_flag = WD_KICKED;
++			} else if (h_evt->h_event == SOC_EVT_RESET_HOST) {
++				dev_kfree_skb_any(skb);
++				if ((sc->ap_vif == NULL)
++				    || !(sc->sh->cfg.ignore_reset_in_ap)) {
++					ssv6xxx_restart_hw(sc);
++				} else {
++					dev_warn(sc->dev,
++						 "Reset event ignored.\n");
++				}
++			}
++#ifdef CONFIG_P2P_NOA
++			else if (h_evt->h_event == SOC_EVT_NOA) {
++				ssv6xxx_process_noa_event(sc, skb);
++				dev_kfree_skb_any(skb);
++			}
++#endif
++			else if (h_evt->h_event == SOC_EVT_SDIO_TXTPUT_RESULT) {
++				dev_dbg(sc->dev, "data SDIO TX throughput %d Kbps\n",
++				       h_evt->evt_seq_no);
++				dev_kfree_skb_any(skb);
++			} else if (h_evt->h_event == SOC_EVT_TXLOOPBK_RESULT) {
++				if (h_evt->evt_seq_no == SSV6XXX_STATE_OK) {
++					dev_dbg(sc->dev, "FW TX LOOPBACK OK\n");
++					sc->iq_cali_done = IQ_CALI_OK;
++				} else {
++					dev_dbg(sc->dev, "FW TX LOOPBACK FAILED\n");
++					sc->iq_cali_done = IQ_CALI_FAILED;
++				}
++				dev_kfree_skb_any(skb);
++				wake_up_interruptible(&sc->fw_wait_q);
++			} else {
++				dev_warn(sc->dev, "Unkown event %d received\n",
++					 h_evt->h_event);
++				dev_kfree_skb_any(skb);
++			}
++			continue;
++		}
++		hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
++		if (ieee80211_is_back(hdr->frame_control)) {
++			ssv6200_ampdu_BA_handler(sc->hw, skb);
++#ifdef USE_FLUSH_RETRY
++			has_ba_processed = true;
++#endif
++			continue;
++		}
++		_proc_data_rx_skb(sc, skb);
++	}
++#ifdef USE_FLUSH_RETRY
++	if (has_ba_processed) {
++		ssv6xxx_ampdu_postprocess_BA(sc->hw);
++	}
++#endif
++}
++
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args)
++#else
++int ssv6200_rx(struct sk_buff *rx_skb, void *args)
++#endif
++{
++	struct ssv_softc *sc = args;
++#ifdef IRQ_PROC_RX_DATA
++	struct sk_buff *skb;
++	skb = _proc_rx_skb(sc, rx_skb);
++	if (skb == NULL)
++		return 0;
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	{
++		unsigned long flags;
++		spin_lock_irqsave(&sc->rx_skb_q.lock, flags);
++		while (skb_queue_len(rx_skb_q))
++			__skb_queue_tail(&sc->rx_skb_q,
++					 __skb_dequeue(rx_skb_q));
++		spin_unlock_irqrestore(&sc->rx_skb_q.lock, flags);
++	}
++#else
++	skb_queue_tail(&sc->rx_skb_q, rx_skb);
++#endif
++	wake_up_interruptible(&sc->rx_wait_q);
++	return 0;
++}
++
++struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
++						 struct sk_buff *skb)
++{
++	struct ieee80211_hdr *hdr =
++	    (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
++	struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)skb->data;;
++	if ((rxdesc->wsid >= 0) && (rxdesc->wsid < SSV_NUM_STA))
++		return sc->sta_info[rxdesc->wsid].sta;
++	else
++		return ssv6xxx_find_sta_by_addr(sc, hdr->addr2);
++}
++
++struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc, u8 addr[6])
++{
++	struct ieee80211_sta *sta;
++	int i;
++	for (i = 0; i < SSV6200_MAX_VIF; i++) {
++		if (sc->vif_info[i].vif == NULL)
++			continue;
++		sta = ieee80211_find_sta(sc->vif_info[i].vif, addr);
++		if (sta != NULL)
++			return sta;
++	}
++	return NULL;
++}
++
++void ssv6xxx_foreach_sta(struct ssv_softc *sc,
++			 void (*sta_func)(struct ssv_softc *,
++					  struct ssv_sta_info *, void *),
++			 void *param)
++{
++	int i;
++	BUG_ON(sta_func == NULL);
++	for (i = 0; i < SSV_NUM_STA; i++) {
++		if ((sc->sta_info[i].s_flags & STA_FLAG_VALID) == 0)
++			continue;
++		(*sta_func) (sc, &sc->sta_info[i], param);
++	}
++}
++
++void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
++			     struct ssv_vif_info *vif_info,
++			     void (*sta_func)(struct ssv_softc *,
++					      struct ssv_vif_info *,
++					      struct ssv_sta_info *,
++					      void *), void *param)
++{
++	struct ssv_vif_priv_data *vif_priv;
++	struct ssv_sta_priv_data *sta_priv_iter;
++	BUG_ON(vif_info == NULL);
++	BUG_ON((size_t)vif_info < 0x30000);
++	vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	BUG_ON((size_t)vif_info->vif < 0x30000);
++	BUG_ON((size_t)vif_priv < 0x30000);
++	list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
++		BUG_ON(sta_priv_iter == NULL);
++		BUG_ON((size_t)sta_priv_iter < 0x30000);
++		BUG_ON(sta_priv_iter->sta_info == NULL);
++		BUG_ON((size_t)sta_priv_iter->sta_info < 0x30000);
++		if ((sta_priv_iter->sta_info->s_flags & STA_FLAG_VALID) == 0)
++			continue;
++		(*sta_func) (sc, vif_info, sta_priv_iter->sta_info, param);
++	}
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
++				     ssize_t length)
++{
++	ssize_t buf_size = length;
++	ssize_t prt_size;
++	prt_size =
++	    snprintf(status_buf, buf_size, "\nSMAC driver queue status:.\n");
++	status_buf += prt_size;
++	buf_size -= prt_size;
++	prt_size = snprintf(status_buf, buf_size, "\tTX queue: %d\n",
++			    skb_queue_len(&sc->tx_skb_q));
++	status_buf += prt_size;
++	buf_size -= prt_size;
++	prt_size = snprintf(status_buf, buf_size, "\tMax TX queue: %d\n",
++			    sc->max_tx_skb_q_len);
++	status_buf += prt_size;
++	buf_size -= prt_size;
++	return (length - buf_size);
++}
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/dev.h b/drivers/net/wireless/ssv6051/smac/dev.h
+new file mode 100644
+index 000000000000..0a6357624b1c
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/dev.h
+@@ -0,0 +1,445 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _DEV_H_
++#define _DEV_H_
++#include <linux/version.h>
++#include <linux/device.h>
++#include <linux/interrupt.h>
++#include <net/mac80211.h>
++#include "ampdu.h"
++#include "ssv_rc_common.h"
++#include "drv_comm.h"
++#include "sec.h"
++#include "p2p.h"
++#include <linux/kthread.h>
++#define SSV6200_MAX_HW_MAC_ADDR 2
++#define SSV6200_MAX_VIF 2
++#define SSV6200_RX_BA_MAX_SESSIONS 1
++#define SSV6200_OPMODE_STA 0
++#define SSV6200_OPMODE_AP 1
++#define SSV6200_OPMODE_IBSS 2
++#define SSV6200_OPMODE_WDS 3
++#define SSV6200_USE_HW_WSID(_sta_idx) ((_sta_idx == 0) || (_sta_idx == 1))
++#define HW_MAX_RATE_TRIES 7
++#define MAC_DECITBL1_SIZE 16
++#define MAC_DECITBL2_SIZE 9
++#define RX_11B_CCA_IN_SCAN 0x20230050
++//#define WATCHDOG_TIMEOUT (10*HZ)
++#define WATCHDOG_TIMEOUT (99999*HZ)
++extern u16 generic_deci_tbl[];
++#define ap_deci_tbl generic_deci_tbl
++#define sta_deci_tbl generic_deci_tbl
++#define HT_SIGNAL_EXT 6
++#define HT_SIFS_TIME 10
++#define BITS_PER_BYTE 8
++#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
++#define ACK_LEN (14)
++#define BA_LEN (32)
++#define RTS_LEN (20)
++#define CTS_LEN (14)
++#define L_STF 8
++#define L_LTF 8
++#define L_SIG 4
++#define HT_SIG 8
++#define HT_STF 4
++#define HT_LTF(_ns) (4 * (_ns))
++#define SYMBOL_TIME(_ns) ((_ns) << 2)
++#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)
++#define CCK_SIFS_TIME 10
++#define CCK_PREAMBLE_BITS 144
++#define CCK_PLCP_BITS 48
++#define OFDM_SIFS_TIME 16
++#define OFDM_PREAMBLE_TIME 20
++#define OFDM_PLCP_BITS 22
++#define OFDM_SYMBOL_TIME 4
++#define WMM_AC_VO 0
++#define WMM_AC_VI 1
++#define WMM_AC_BE 2
++#define WMM_AC_BK 3
++#define WMM_NUM_AC 4
++#define WMM_TID_NUM 8
++#define TXQ_EDCA_0 0x01
++#define TXQ_EDCA_1 0x02
++#define TXQ_EDCA_2 0x04
++#define TXQ_EDCA_3 0x08
++#define TXQ_MGMT 0x10
++#define IS_SSV_HT(dsc) ((dsc)->rate_idx >= 15)
++#define IS_SSV_SHORT_GI(dsc) ((dsc)->rate_idx>=23 && (dsc)->rate_idx<=30)
++#define IS_SSV_HT_GF(dsc) ((dsc)->rate_idx >= 31)
++#define IS_SSV_SHORT_PRE(dsc) ((dsc)->rate_idx>=4 && (dsc)->rate_idx<=14)
++#define SMAC_REG_WRITE(_s,_r,_v) \
++        (_s)->hci.hci_ops->hci_write_word(_r,_v)
++#define SMAC_REG_READ(_s,_r,_v) \
++        (_s)->hci.hci_ops->hci_read_word(_r, _v)
++#define SMAC_LOAD_FW(_s,_r,_v) \
++        (_s)->hci.hci_ops->hci_load_fw(_r, _v)
++#define SMAC_IFC_RESET(_s) (_s)->hci.hci_ops->hci_interface_reset()
++#define SMAC_REG_CONFIRM(_s,_r,_v) \
++{ \
++    u32 _regval; \
++    SMAC_REG_READ(_s, _r, &_regval); \
++    if (_regval != (_v)) { \
++        printk("ERROR!!Please check interface!\n"); \
++        printk("[0x%08x]: 0x%08x!=0x%08x\n", \
++        (_r), (_v), _regval); \
++        printk("SOS!SOS!\n"); \
++        return -1; \
++    } \
++}
++#define SMAC_REG_SET_BITS(_sh,_reg,_set,_clr) \
++({ \
++    int ret; \
++    u32 _regval; \
++    ret = SMAC_REG_READ(_sh, _reg, &_regval); \
++    _regval &= ~(_clr); \
++    _regval |= (_set); \
++    if (ret == 0) \
++        ret = SMAC_REG_WRITE(_sh, _reg, _regval); \
++    ret; \
++})
++#define HCI_START(_sh) \
++    (_sh)->hci.hci_ops->hci_start()
++#define HCI_STOP(_sh) \
++    (_sh)->hci.hci_ops->hci_stop()
++#define HCI_SEND(_sh,_sk,_q) \
++    (_sh)->hci.hci_ops->hci_tx(_sk, _q, 0)
++#define HCI_PAUSE(_sh,_mk) \
++    (_sh)->hci.hci_ops->hci_tx_pause(_mk)
++#define HCI_RESUME(_sh,_mk) \
++    (_sh)->hci.hci_ops->hci_tx_resume(_mk)
++#define HCI_TXQ_FLUSH(_sh,_mk) \
++    (_sh)->hci.hci_ops->hci_txq_flush(_mk)
++#define HCI_TXQ_FLUSH_BY_STA(_sh,_aid) \
++  (_sh)->hci.hci_ops->hci_txq_flush_by_sta(_aid)
++#define HCI_TXQ_EMPTY(_sh,_txqid) \
++  (_sh)->hci.hci_ops->hci_txq_empty(_txqid)
++#define HCI_WAKEUP_PMU(_sh) \
++    (_sh)->hci.hci_ops->hci_pmu_wakeup()
++#define HCI_SEND_CMD(_sh,_sk) \
++        (_sh)->hci.hci_ops->hci_send_cmd(_sk)
++#define SSV6XXX_SET_HW_TABLE(sh_,tbl_) \
++({ \
++    int ret = 0; \
++    u32 i=0; \
++    for(; i<sizeof(tbl_)/sizeof(struct ssv6xxx_dev_table); i++) { \
++        ret = SMAC_REG_WRITE(sh_, tbl_[i].address, tbl_[i].data); \
++        if (ret) break; \
++    } \
++    ret; \
++})
++#define SSV6XXX_USE_HW_DECRYPT(_priv) (_priv->has_hw_decrypt)
++#define SSV6XXX_USE_SW_DECRYPT(_priv) (SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) || SSV6XXX_USE_MAC80211_DECRYPT(_priv))
++#define SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) (_priv->need_sw_decrypt)
++#define SSV6XXX_USE_MAC80211_DECRYPT(_priv) (_priv->use_mac80211_decrypt)
++struct ssv_softc;
++#ifdef CONFIG_P2P_NOA
++struct ssv_p2p_noa;
++#endif
++#define SSV6200_HT_TX_STREAMS 1
++#define SSV6200_HT_RX_STREAMS 1
++#define SSV6200_RX_HIGHEST_RATE 72
++enum PWRSV_STATUS {
++	PWRSV_DISABLE,
++	PWRSV_ENABLE,
++	PWRSV_PREPARE,
++};
++struct rssi_res_st {
++	struct list_head rssi_list;
++	unsigned long cache_jiffies;
++	s32 rssi;
++	s32 timeout;
++	u8 bssid[ETH_ALEN];
++};
++struct ssv_hw {
++	struct ssv_softc *sc;
++	struct ssv6xxx_platform_data *priv;
++	struct ssv6xxx_hci_info hci;
++	char chip_id[24];
++	u64 chip_tag;
++	u32 tx_desc_len;
++	u32 rx_desc_len;
++	u32 rx_pinfo_pad;
++	u32 tx_page_available;
++	u32 ampdu_divider;
++	u8 page_count[SSV6200_ID_NUMBER];
++	u32 hw_buf_ptr[SSV_RC_MAX_STA];
++	u32 hw_sec_key[SSV_RC_MAX_STA];
++	u32 hw_pinfo;
++	struct ssv6xxx_cfg cfg;
++	u32 n_addresses;
++	struct mac_address maddr[SSV6200_MAX_HW_MAC_ADDR];
++	u8 ipd_channel_touch;
++	struct ssv6xxx_ch_cfg *p_ch_cfg;
++	u32 ch_cfg_size;
++};
++struct ssv_tx {
++	u16 seq_no;
++	int hw_txqid[WMM_NUM_AC];
++	int ac_txqid[WMM_NUM_AC];
++	u32 flow_ctrl_status;
++	u32 tx_pkt[SSV_HW_TXQ_NUM];
++	u32 tx_frag[SSV_HW_TXQ_NUM];
++	struct list_head ampdu_tx_que;
++	spinlock_t ampdu_tx_que_lock;
++	u16 ampdu_tx_group_id;
++};
++struct ssv_rx {
++	struct sk_buff *rx_buf;
++	spinlock_t rxq_lock;
++	struct sk_buff_head rxq_head;
++	u32 rxq_count;
++};
++#define SSV6XXX_GET_STA_INFO(_sc,_s) \
++    &(_sc)->sta_info[((struct ssv_sta_priv_data *)((_s)->drv_priv))->sta_idx]
++#define STA_FLAG_VALID 0x00001
++#define STA_FLAG_QOS 0x00002
++#define STA_FLAG_AMPDU 0x00004
++#define STA_FLAG_ENCRYPT 0x00008
++struct ssv_sta_info {
++	u16 aid;
++	u16 s_flags;
++	int hw_wsid;
++	struct ieee80211_sta *sta;
++	struct ieee80211_vif *vif;
++	bool sleeping;
++	bool tim_set;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++#endif
++};
++struct ssv_vif_info {
++	struct ieee80211_vif *vif;
++	struct ssv_vif_priv_data *vif_priv;
++	enum nl80211_iftype if_type;
++	struct ssv6xxx_hw_sec sramKey;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++#endif
++};
++struct ssv_sta_priv_data {
++	int sta_idx;
++	int rc_idx;
++	int rx_data_rate;
++	struct ssv_sta_info *sta_info;
++	struct list_head list;
++	u32 ampdu_mib_total_BA_counter;
++	AMPDU_TID ampdu_tid[WMM_TID_NUM];
++	bool has_hw_encrypt;
++	bool need_sw_encrypt;
++	bool has_hw_decrypt;
++	bool need_sw_decrypt;
++	bool use_mac80211_decrypt;
++	u8 group_key_idx;
++	u32 beacon_rssi;
++};
++struct ssv_vif_priv_data {
++	int vif_idx;
++	struct list_head sta_list;
++	u32 sta_asleep_mask;
++	u32 pair_cipher;
++	u32 group_cipher;
++	bool is_security_valid;
++	bool has_hw_encrypt;
++	bool need_sw_encrypt;
++	bool has_hw_decrypt;
++	bool need_sw_decrypt;
++	bool use_mac80211_decrypt;
++	bool force_sw_encrypt;
++	u8 group_key_idx;
++};
++#define SC_OP_INVALID 0x00000001
++#define SC_OP_HW_RESET 0x00000002
++#define SC_OP_OFFCHAN 0x00000004
++#define SC_OP_FIXED_RATE 0x00000008
++#define SC_OP_SHORT_PREAMBLE 0x00000010
++struct ssv6xxx_beacon_info {
++	u32 pubf_addr;
++	u16 len;
++	u8 tim_offset;
++	u8 tim_cnt;
++};
++#define SSV6200_MAX_BCAST_QUEUE_LEN 16
++struct ssv6xxx_bcast_txq {
++	spinlock_t txq_lock;
++	struct sk_buff_head qhead;
++	int cur_qsize;
++};
++#ifdef DEBUG_AMPDU_FLUSH
++typedef struct AMPDU_TID_st AMPDU_TID;
++#define MAX_TID (24)
++#endif
++struct ssv_softc {
++	struct ieee80211_hw *hw;
++	struct device *dev;
++	u32 restart_counter;
++	bool force_triger_reset;
++	unsigned long sdio_throughput_timestamp;
++	unsigned long sdio_rx_evt_size;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
++	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
++#else
++	struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
++#endif
++	struct ieee80211_channel *cur_channel;
++	u16 hw_chan;
++	struct mutex mutex;
++	struct ssv_hw *sh;
++	struct ssv_tx tx;
++	struct ssv_rx rx;
++	struct ssv_vif_info vif_info[SSV_NUM_VIF];
++	struct ssv_sta_info sta_info[SSV_NUM_STA];
++	struct ieee80211_vif *ap_vif;
++	u8 nvif;
++	u32 sc_flags;
++	void *rc;
++	int max_rate_idx;
++	struct workqueue_struct *rc_sample_workqueue;
++	struct sk_buff_head rc_report_queue;
++	struct work_struct rc_sample_work;
++#ifdef DEBUG_AMPDU_FLUSH
++	struct AMPDU_TID_st *tid[MAX_TID];
++#endif
++	u16 rc_sample_sechedule;
++	u16 *mac_deci_tbl;
++	struct workqueue_struct *config_wq;
++	bool bq4_dtim;
++	struct work_struct set_tim_work;
++	u8 enable_beacon;
++	u8 beacon_interval;
++	u8 beacon_dtim_cnt;
++	u8 beacon_usage;
++	struct ssv6xxx_beacon_info beacon_info[2];
++	struct sk_buff *beacon_buf;
++	struct work_struct bcast_start_work;
++	struct delayed_work bcast_stop_work;
++	struct delayed_work bcast_tx_work;
++	struct delayed_work thermal_monitor_work;
++	struct workqueue_struct *thermal_wq;
++	int is_sar_enabled;
++	bool aid0_bit_set;
++	u8 hw_mng_used;
++	struct ssv6xxx_bcast_txq bcast_txq;
++	int bcast_interval;
++	u8 bssid[6];
++	struct mutex mem_mutex;
++	spinlock_t ps_state_lock;
++	u8 hw_wsid_bit;
++	int rx_ba_session_count;
++	struct ieee80211_sta *rx_ba_sta;
++	u8 rx_ba_bitmap;
++	u8 ba_ra_addr[ETH_ALEN];
++	u16 ba_tid;
++	u16 ba_ssn;
++	struct work_struct set_ampdu_rx_add_work;
++	struct work_struct set_ampdu_rx_del_work;
++	bool isAssoc;
++	u16 channel_center_freq;
++	bool bScanning;
++	int ps_status;
++	u16 ps_aid;
++	u16 tx_wait_q_woken;
++	wait_queue_head_t tx_wait_q;
++	struct sk_buff_head tx_skb_q;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	u32 max_tx_skb_q_len;
++#endif
++	struct task_struct *tx_task;
++	bool tx_q_empty;
++	struct sk_buff_head tx_done_q;
++	u16 rx_wait_q_woken;
++	wait_queue_head_t rx_wait_q;
++	struct sk_buff_head rx_skb_q;
++	struct task_struct *rx_task;
++	bool dbg_rx_frame;
++	bool dbg_tx_frame;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++#endif
++#ifdef CONFIG_P2P_NOA
++	struct ssv_p2p_noa p2p_noa;
++#endif
++	struct timer_list watchdog_timeout;
++	u32 watchdog_flag;
++	wait_queue_head_t fw_wait_q;
++	u32 iq_cali_done;
++	u32 sr_bhvr;
++};
++enum {
++	IQ_CALI_RUNNING,
++	IQ_CALI_OK,
++	IQ_CALI_FAILED
++};
++enum {
++	WD_SLEEP,
++	WD_BARKING,
++	WD_KICKED,
++	WD_MAX
++};
++void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args);
++void ssv6200_rx_process(struct work_struct *work);
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args);
++#else
++int ssv6200_rx(struct sk_buff *rx_skb, void *args);
++#endif
++void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args);
++void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args);
++int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug);
++void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *);
++int ssv6xxx_rf_disable(struct ssv_hw *sh);
++int ssv6xxx_rf_enable(struct ssv_hw *sh);
++int ssv6xxx_set_channel(struct ssv_softc *sc, int ch);
++#ifdef CONFIG_SSV_SMARTLINK
++int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch);
++int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept);
++int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept);
++#endif
++int ssv6xxx_tx_task(void *data);
++int ssv6xxx_rx_task(void *data);
++u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type);
++bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr);
++void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
++void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
++int ssv6xxx_update_decision_table(struct ssv_softc *sc);
++void ssv6xxx_ps_callback_func(unsigned long data);
++void ssv6xxx_enable_ps(struct ssv_softc *sc);
++void ssv6xxx_disable_ps(struct ssv_softc *sc);
++int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag);
++int ssv6xxx_skb_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc);
++int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta,
++			struct ssv_softc *sc);
++void ssv6200_sync_hw_key_sequence(struct ssv_softc *sc,
++				  struct ssv_sta_info *sta_info, bool bWrite);
++struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
++						 struct sk_buff *skb);
++struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc,
++					       u8 addr[6]);
++void ssv6xxx_foreach_sta(struct ssv_softc *sc,
++			 void (*sta_func)(struct ssv_softc *,
++					  struct ssv_sta_info *, void *),
++			 void *param);
++void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
++			     struct ssv_vif_info *vif_info,
++			     void (*sta_func)(struct ssv_softc *,
++					      struct ssv_vif_info *,
++					      struct ssv_sta_info *, void *),
++			     void *param);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
++				     ssize_t buf_size);
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/dev_tbl.h b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
+new file mode 100644
+index 000000000000..5c49d0bde6a6
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
+@@ -0,0 +1,141 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _DEV_TBL_H_
++#define _DEV_TBL_H_
++#include "ssv6200_configuration.h"
++#include "drv_comm.h"
++struct ssv6xxx_dev_table {
++	u32 address;
++	u32 data;
++};
++#define ssv6200_phy_tbl phy_setting
++#define ssv6200_rf_tbl asic_rf_setting
++#define ACTION_DO_NOTHING 0
++#define ACTION_UPDATE_NAV 1
++#define ACTION_RESET_NAV 2
++#define ACTION_SIGNAL_ACK 3
++#define FRAME_ACCEPT 0
++#define FRAME_DROP 1
++#define SET_DEC_TBL(_type,_mask,_action,_drop) \
++    (_type<<9| \
++    _mask <<3| \
++    _action<<1| \
++    _drop)
++u16 generic_deci_tbl[] = {
++	SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP),
++	SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x1a, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT),
++	SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP),
++	0,
++	0,
++	0,
++	SET_DEC_TBL(0x05, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x0b, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x01, 0x3d, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT),
++	SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP),
++	SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP),
++	SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP),
++	SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP),
++	0x2008,
++	0x1001,
++	0x0400,
++	0x0400,
++	0x2000,
++	0x800E,
++	0x0800,
++	0x0B88,
++	0x0800,
++};
++
++#define SET_PHY_INFO(_ctsdur,_ba_rate_idx,_ack_rate_idx,_llength_idx,_llength_enable) \
++         (_ctsdur<<16| \
++         _ba_rate_idx <<10| \
++         _ack_rate_idx<<4| \
++         _llength_idx<<1| \
++         _llength_enable)
++#define SET_PHY_L_LENGTH(_l_ba,_l_rts,_l_cts_ack) (_l_ba<<12|_l_rts<<6 |_l_cts_ack)
++static u32 phy_info_6051z[] = {
++	0x18000000, 0x18000100, 0x18000200, 0x18000300, 0x18000140,
++	0x18000240, 0x18000340, 0x0C000001, 0x0C000101, 0x0C000201,
++	0x0C000301, 0x18000401, 0x18000501, 0x18000601, 0x18000701,
++	0x0C030002, 0x0C030102, 0x0C030202, 0x18030302, 0x18030402,
++	0x18030502, 0x18030602, 0x1C030702, 0x0C030082, 0x0C030182,
++	0x0C030282, 0x18030382, 0x18030482, 0x18030582, 0x18030682,
++	0x1C030782, 0x0C030042, 0x0C030142, 0x0C030242, 0x18030342,
++	0x18030442, 0x18030542, 0x18030642, 0x1C030742
++};
++
++static u32 phy_info_tbl[] = {
++	0x0C000000, 0x0C000100, 0x0C000200, 0x0C000300, 0x0C000140,
++	0x0C000240, 0x0C000340, 0x00000001, 0x00000101, 0x00000201,
++	0x00000301, 0x0C000401, 0x0C000501, 0x0C000601, 0x0C000701,
++	0x00030002, 0x00030102, 0x00030202, 0x0C030302, 0x0C030402,
++	0x0C030502, 0x0C030602, 0x10030702, 0x00030082, 0x00030182,
++	0x00030282, 0x0C030382, 0x0C030482, 0x0C030582, 0x0C030682,
++	0x10030782, 0x00030042, 0x00030142, 0x00030242, 0x0C030342,
++	0x0C030442, 0x0C030542, 0x0C030642, 0x10030742,
++	SET_PHY_INFO(314, 0, 0, 0, 0),
++	SET_PHY_INFO(258, 0, 1, 0, 0),
++	SET_PHY_INFO(223, 0, 1, 0, 0),
++	SET_PHY_INFO(213, 0, 1, 0, 0),
++	SET_PHY_INFO(162, 0, 4, 0, 0),
++	SET_PHY_INFO(127, 0, 4, 0, 0),
++	SET_PHY_INFO(117, 0, 4, 0, 0),
++	SET_PHY_INFO(60, 7, 7, 0, 0),
++	SET_PHY_INFO(52, 7, 7, 0, 0),
++	SET_PHY_INFO(48, 9, 9, 0, 0),
++	SET_PHY_INFO(44, 9, 9, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(40, 11, 11, 0, 0),
++	SET_PHY_INFO(40, 11, 11, 0, 0),
++	SET_PHY_INFO(40, 11, 11, 0, 0),
++	SET_PHY_INFO(76, 7, 7, 0, 1),
++	SET_PHY_INFO(64, 9, 9, 1, 1),
++	SET_PHY_INFO(60, 9, 9, 2, 1),
++	SET_PHY_INFO(60, 11, 11, 3, 1),
++	SET_PHY_INFO(56, 11, 11, 4, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(76, 7, 7, 6, 1),
++	SET_PHY_INFO(64, 9, 9, 1, 1),
++	SET_PHY_INFO(60, 9, 9, 2, 1),
++	SET_PHY_INFO(60, 11, 11, 3, 1),
++	SET_PHY_INFO(56, 11, 11, 4, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(64, 7, 7, 0, 0),
++	SET_PHY_INFO(52, 9, 9, 0, 0),
++	SET_PHY_INFO(48, 9, 9, 0, 0),
++	SET_PHY_INFO(48, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_L_LENGTH(50, 38, 35),
++	SET_PHY_L_LENGTH(35, 29, 26),
++	SET_PHY_L_LENGTH(29, 26, 23),
++	SET_PHY_L_LENGTH(26, 23, 23),
++	SET_PHY_L_LENGTH(23, 23, 20),
++	SET_PHY_L_LENGTH(23, 20, 20),
++	SET_PHY_L_LENGTH(47, 38, 35),
++	SET_PHY_L_LENGTH(0, 0, 0),
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/drv_comm.h b/drivers/net/wireless/ssv6051/smac/drv_comm.h
+new file mode 100644
+index 000000000000..f04fbae004c3
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/drv_comm.h
+@@ -0,0 +1,61 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _DRV_COMM_H_
++#define _DRV_COMM_H_
++#define PHY_INFO_TBL1_SIZE 39
++#define PHY_INFO_TBL2_SIZE 39
++#define PHY_INFO_TBL3_SIZE 8
++#define ampdu_fw_rate_info_status_no_use BIT(0)
++#define ampdu_fw_rate_info_status_in_use BIT(1)
++#define ampdu_fw_rate_info_status_reset BIT(2)
++#define SSV_NUM_STA 8
++#define SSV_NUM_VIF 2
++#define SECURITY_KEY_LEN (32)
++enum SSV_CIPHER_E {
++	SSV_CIPHER_NONE,
++	SSV_CIPHER_WEP40,
++	SSV_CIPHER_WEP104,
++	SSV_CIPHER_TKIP,
++	SSV_CIPHER_CCMP,
++	SSV_CIPHER_SMS4,
++	SSV_CIPHER_INVALID = (-1)
++};
++#define ME_NONE 0
++#define ME_WEP40 1
++#define ME_WEP104 2
++#define ME_TKIP 3
++#define ME_CCMP 4
++#define ME_SMS4 5
++struct ssv6xxx_hw_key {
++	u8 key[SECURITY_KEY_LEN];
++	u32 tx_pn_l;
++	u32 tx_pn_h;
++	u32 rx_pn_l;
++	u32 rx_pn_h;
++} __attribute__((packed));
++struct ssv6xxx_hw_sta_key {
++	u8 pair_key_idx:4;
++	u8 group_key_idx:4;
++	u8 valid;
++	u8 reserve[2];
++	struct ssv6xxx_hw_key pair;
++} __attribute__((packed));
++struct ssv6xxx_hw_sec {
++	struct ssv6xxx_hw_key group_key[3];
++	struct ssv6xxx_hw_sta_key sta_key[8];
++} __attribute__((packed));
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/efuse.c b/drivers/net/wireless/ssv6051/smac/efuse.c
+new file mode 100644
+index 000000000000..9a1f3f5488f2
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/efuse.c
+@@ -0,0 +1,334 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/etherdevice.h>
++#include <ssv6200.h>
++#include "efuse.h"
++
++struct file *openFile(char *path, int flag, int mode)
++{
++	struct file *fp = NULL;
++	fp = filp_open(path, flag, 0);
++	if (IS_ERR(fp))
++		return NULL;
++	else
++		return fp;
++}
++
++int readFile(struct file *fp, char *buf, int readlen)
++{
++	if (fp->f_op && fp->f_op->read)
++		return fp->f_op->read(fp, buf, readlen, &fp->f_pos);
++	else
++		return -1;
++}
++
++int closeFile(struct file *fp)
++{
++	filp_close(fp, NULL);
++	return 0;
++}
++
++void initKernelEnv(void)
++{
++}
++
++void parseMac(char *mac, u_int8_t addr[])
++{
++	long b;
++	int i;
++	for (i = 0; i < 6; i++) {
++		b = simple_strtol(mac + (3 * i), (char **)NULL, 16);
++		addr[i] = (char)b;
++	}
++}
++
++static int readfile_mac(u8 * path, u8 * mac_addr)
++{
++	char buf[128];
++	struct file *fp = NULL;
++	int ret = 0;
++	fp = openFile(path, O_RDONLY, 0);
++	if (fp != NULL) {
++		initKernelEnv();
++		memset(buf, 0, 128);
++		if ((ret = readFile(fp, buf, 128)) > 0) {
++			parseMac(buf, (uint8_t *) mac_addr);
++		} else
++			pr_err("read file error %d=[%s]\n", ret, path);
++		closeFile(fp);
++	} else
++		pr_err("Read open File fail[%s]!!!! \n", path);
++	return ret;
++}
++
++static int write_mac_to_file(u8 * mac_path, u8 * mac_addr)
++{
++	char buf[128];
++	struct file *fp = NULL;
++	int ret = 0, len;
++	fp = openFile(mac_path, O_WRONLY | O_CREAT, 0640);
++	if (fp != NULL) {
++		initKernelEnv();
++		memset(buf, 0, 128);
++		sprintf(buf, "%x:%x:%x:%x:%x:%x", mac_addr[0], mac_addr[1],
++			mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
++		len = strlen(buf) + 1;
++		fp->f_op->write(fp, (char *)buf, len, &fp->f_pos);
++		closeFile(fp);
++	} else
++		pr_err("Write open File fail!!!![%s] \n", mac_path);
++	return ret;
++}
++
++static struct efuse_map SSV_EFUSE_ITEM_TABLE[] = {
++	{4, 0, 0},
++	{4, 8, 0},
++	{4, 8, 0},
++	{4, 48, 0},
++	{4, 8, 0},
++	{4, 8, 0},
++	{4, 8, 0},
++};
++
++static u8 read_efuse(struct ssv_hw *sh, u8 * pbuf)
++{
++	extern struct ssv6xxx_cfg ssv_cfg;
++	u32 val, i;
++	u32 *temp = (u32 *) pbuf;
++	SMAC_REG_WRITE(sh, 0xC0000328, 0x11);
++	SMAC_REG_WRITE(sh, SSV_EFUSE_ID_READ_SWITCH, 0x1);
++	SMAC_REG_READ(sh, SSV_EFUSE_ID_RAW_DATA_BASE, &val);
++	ssv_cfg.chip_identity = val;
++	SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH, 0x1);
++	SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE, &val);
++	if (val == 0x00) {
++		return 0;
++	}
++	for (i = 0; i < (EFUSE_MAX_SECTION_MAP); i++) {
++		SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH + i * 4, 0x1);
++		SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE + i * 4, &val);
++		*temp++ = val;
++	}
++	SMAC_REG_WRITE(sh, 0xC0000328, 0x1800000a);
++	return 1;
++}
++
++static u16 parser_efuse(u8 * pbuf, u8 * mac_addr)
++{
++	u8 *rtemp8, idx = 0;
++	u16 shift = 0, i;
++	u16 efuse_real_content_len = 0;
++	rtemp8 = pbuf;
++	if (*rtemp8 == 0x00) {
++		return efuse_real_content_len;
++	}
++	do {
++		idx = (*(rtemp8) >> shift) & 0xf;
++		switch (idx) {
++		case EFUSE_R_CALIBRATION_RESULT:
++		case EFUSE_CRYSTAL_FREQUENCY_OFFSET:
++		case EFUSE_TX_POWER_INDEX_1:
++		case EFUSE_TX_POWER_INDEX_2:
++		case EFUSE_SAR_RESULT:
++			if (shift) {
++				rtemp8++;
++				SSV_EFUSE_ITEM_TABLE[idx].value =
++				    (u16) ((u8) (*((u16 *) rtemp8)) &
++					   ((1 <<
++					     SSV_EFUSE_ITEM_TABLE
++					     [idx].byte_cnts) - 1));
++			} else {
++				SSV_EFUSE_ITEM_TABLE[idx].value =
++				    (u16) ((u8) (*((u16 *) rtemp8) >> 4) &
++					   ((1 <<
++					     SSV_EFUSE_ITEM_TABLE
++					     [idx].byte_cnts) - 1));
++			}
++			efuse_real_content_len +=
++			    (SSV_EFUSE_ITEM_TABLE[idx].offset +
++			     SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
++			break;
++		case EFUSE_MAC:
++			if (shift) {
++				rtemp8++;
++				memcpy(mac_addr, rtemp8, 6);
++			} else {
++				for (i = 0; i < 6; i++) {
++					mac_addr[i] =
++					    (u16) (*((u16 *) rtemp8) >> 4) &
++					    0xff;
++					rtemp8++;
++				}
++			}
++			efuse_real_content_len +=
++			    (SSV_EFUSE_ITEM_TABLE[idx].offset +
++			     SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
++			break;
++		default:
++			idx = 0;
++			break;
++		}
++		shift = efuse_real_content_len % 8;
++		rtemp8 = &pbuf[efuse_real_content_len / 8];
++	} while (idx != 0);
++	return efuse_real_content_len;
++}
++
++void addr_increase_copy(u8 * dst, u8 * src)
++{
++	u8 *a = (u8 *) dst;
++	const u8 *b = (const u8 *)src;
++	a[0] = b[0];
++	a[1] = b[1];
++	a[2] = b[2];
++	a[3] = b[3];
++	a[4] = b[4];
++	if (b[5] & 0x1)
++		a[5] = b[5] - 1;
++	else
++		a[5] = b[5] + 1;
++}
++
++static u8 key_char2num(u8 ch)
++{
++	if ((ch >= '0') && (ch <= '9'))
++		return ch - '0';
++	else if ((ch >= 'a') && (ch <= 'f'))
++		return ch - 'a' + 10;
++	else if ((ch >= 'A') && (ch <= 'F'))
++		return ch - 'A' + 10;
++	else
++		return 0xff;
++}
++
++u8 key_2char2num(u8 hch, u8 lch)
++{
++	return ((key_char2num(hch) << 4) | key_char2num(lch));
++}
++
++extern struct ssv6xxx_cfg ssv_cfg;
++extern char *ssv_initmac;
++void efuse_read_all_map(struct ssv_hw *sh)
++{
++	u8 mac[ETH_ALEN] = { 0 };
++	int jj, kk;
++	u8 efuse_mapping_table[EFUSE_HWSET_MAX_SIZE / 8];
++#ifndef CONFIG_SSV_RANDOM_MAC
++	u8 pseudo_mac0[ETH_ALEN] = { 0x00, 0x33, 0x33, 0x33, 0x33, 0x33 };
++#endif
++	u8 rom_mac0[ETH_ALEN];
++	memset(rom_mac0, 0x00, ETH_ALEN);
++	memset(efuse_mapping_table, 0x00, EFUSE_HWSET_MAX_SIZE / 8);
++	read_efuse(sh, efuse_mapping_table);
++	parser_efuse(efuse_mapping_table, rom_mac0);
++	ssv_cfg.r_calbration_result =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_R_CALIBRATION_RESULT].value;
++	ssv_cfg.sar_result = (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_SAR_RESULT].value;
++	ssv_cfg.crystal_frequency_offset =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_CRYSTAL_FREQUENCY_OFFSET].value;
++	ssv_cfg.tx_power_index_1 =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_1].value;
++	ssv_cfg.tx_power_index_2 =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_2].value;
++	if (!is_valid_ether_addr(&sh->cfg.maddr[0][0])) {
++		if (!sh->cfg.ignore_efuse_mac) {
++			if (is_valid_ether_addr(rom_mac0)) {
++				dev_info(sh->sc->dev, "Using MAC address from e-fuse\n");
++				memcpy(&sh->cfg.maddr[0][0], rom_mac0,
++				       ETH_ALEN);
++				addr_increase_copy(&sh->cfg.maddr[1][0],
++						   rom_mac0);
++				goto Done;
++			}
++		}
++		if (ssv_initmac != NULL) {
++			for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) {
++				mac[jj] =
++				    key_2char2num(ssv_initmac[kk],
++						  ssv_initmac[kk + 1]);
++			}
++			if (is_valid_ether_addr(mac)) {
++				dev_info(sh->sc->dev, "Using MAC address from module option\n");
++				memcpy(&sh->cfg.maddr[0][0], mac, ETH_ALEN);
++				addr_increase_copy(&sh->cfg.maddr[1][0], mac);
++				goto Done;
++			}
++		}
++		if (sh->cfg.mac_address_path[0] != 0x00) {
++			if ((readfile_mac
++			     (sh->cfg.mac_address_path, &sh->cfg.maddr[0][0]))
++			    && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
++				dev_info
++				    (sh->sc->dev, "Using MAC address from configuration file\n");
++				addr_increase_copy(&sh->cfg.maddr[1][0],
++						   &sh->cfg.maddr[0][0]);
++				goto Done;
++			}
++		}
++		switch (sh->cfg.mac_address_mode) {
++		case 1:
++			get_random_bytes(&sh->cfg.maddr[0][0], ETH_ALEN);
++			sh->cfg.maddr[0][0] = sh->cfg.maddr[0][0] & 0xF0;
++			addr_increase_copy(&sh->cfg.maddr[1][0],
++					   &sh->cfg.maddr[0][0]);
++			break;
++		case 2:
++			if ((readfile_mac
++			     (sh->cfg.mac_output_path, &sh->cfg.maddr[0][0]))
++			    && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
++				addr_increase_copy(&sh->cfg.maddr[1][0],
++						   &sh->cfg.maddr[0][0]);
++			} else {
++				{
++					get_random_bytes(&sh->cfg.maddr[0][0],
++							 ETH_ALEN);
++					sh->cfg.maddr[0][0] =
++					    sh->cfg.maddr[0][0] & 0xF0;
++					addr_increase_copy(&sh->cfg.maddr[1][0],
++							   &sh->
++							   cfg.maddr[0][0]);
++					if (sh->cfg.mac_output_path[0] != 0x00)
++						write_mac_to_file(sh->
++								  cfg.mac_output_path,
++								  &sh->
++								  cfg.maddr[0]
++								  [0]);
++				}
++			}
++			break;
++		default:
++			memcpy(&sh->cfg.maddr[0][0], pseudo_mac0, ETH_ALEN);
++			addr_increase_copy(&sh->cfg.maddr[1][0], pseudo_mac0);
++			break;
++		}
++		dev_info(sh->sc->dev, "MAC address from Software MAC mode[%d]\n",
++			sh->cfg.mac_address_mode);
++	}
++ Done:
++	dev_info(sh->sc->dev, "Chip identity from efuse: %08x\n", ssv_cfg.chip_identity);
++	dev_dbg(sh->sc->dev, "r_calbration_result- %x\n", ssv_cfg.r_calbration_result);
++	dev_dbg(sh->sc->dev, "sar_result- %x\n", ssv_cfg.sar_result);
++	dev_dbg(sh->sc->dev, "crystal_frequency_offset- %x\n",
++		 ssv_cfg.crystal_frequency_offset);
++	dev_dbg(sh->sc->dev, "tx_power_index_1- %x\n", ssv_cfg.tx_power_index_1);
++	dev_dbg(sh->sc->dev, "tx_power_index_2- %x\n", ssv_cfg.tx_power_index_2);
++	dev_dbg(sh->sc->dev, "MAC address - %pM\n", rom_mac0);
++	sh->cfg.crystal_frequency_offset = ssv_cfg.crystal_frequency_offset;
++	sh->cfg.tx_power_index_1 = ssv_cfg.tx_power_index_1;
++	sh->cfg.tx_power_index_2 = ssv_cfg.tx_power_index_2;
++	sh->cfg.chip_identity = ssv_cfg.chip_identity;
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/efuse.h b/drivers/net/wireless/ssv6051/smac/efuse.h
+new file mode 100644
+index 000000000000..c25280c5abad
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/efuse.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_EFUSE_H_
++#define _SSV_EFUSE_H_
++#include "dev.h"
++struct efuse_map {
++	u8 offset;
++	u8 byte_cnts;
++	u16 value;
++};
++enum efuse_data_item {
++	EFUSE_R_CALIBRATION_RESULT = 1,
++	EFUSE_SAR_RESULT,
++	EFUSE_MAC,
++	EFUSE_CRYSTAL_FREQUENCY_OFFSET,
++	EFUSE_TX_POWER_INDEX_1,
++	EFUSE_TX_POWER_INDEX_2
++};
++#define EFUSE_HWSET_MAX_SIZE (256-32)
++#define EFUSE_MAX_SECTION_MAP (EFUSE_HWSET_MAX_SIZE>>5)
++#define SSV_EFUSE_ID_READ_SWITCH 0xC2000128
++#define SSV_EFUSE_ID_RAW_DATA_BASE 0xC200014C
++#define SSV_EFUSE_READ_SWITCH 0xC200012C
++#define SSV_EFUSE_RAW_DATA_BASE 0xC2000150
++void efuse_read_all_map(struct ssv_hw *sh);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/init.c b/drivers/net/wireless/ssv6051/smac/init.c
+new file mode 100644
+index 000000000000..592c52a28381
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/init.c
+@@ -0,0 +1,1347 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/nl80211.h>
++#include <linux/kthread.h>
++#include <linux/etherdevice.h>
++#include <linux/version.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
++#include <crypto/hash.h>
++#else
++#include <linux/crypto.h>
++#endif
++#include <ssv6200.h>
++#include <hci/hctrl.h>
++#include <ssv_firmware_version.h>
++#include "dev_tbl.h"
++#include "dev.h"
++#include "lib.h"
++#include "ssv_rc.h"
++#include "ap.h"
++#include "efuse.h"
++#include "sar.h"
++#include "ssv_cfgvendor.h"
++
++#include "linux_80211.h"
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++#include "ssv6xxx_debugfs.h"
++#endif
++
++#define WIFI_FIRMWARE_NAME "ssv6051-sw.bin"
++static const struct ieee80211_iface_limit ssv6xxx_p2p_limits[] = {
++	{
++	 .max = 2,
++	 .types = BIT(NL80211_IFTYPE_STATION),
++	 },
++	{
++	 .max = 1,
++	 .types = BIT(NL80211_IFTYPE_P2P_GO) |
++	 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_AP),
++	 },
++};
++
++static const struct ieee80211_iface_combination
++ ssv6xxx_iface_combinations_p2p[] = {
++	{.num_different_channels = 1,
++	 .max_interfaces = SSV6200_MAX_VIF,
++	 .beacon_int_infra_match = true,
++	 .limits = ssv6xxx_p2p_limits,
++	 .n_limits = ARRAY_SIZE(ssv6xxx_p2p_limits),
++	 },
++};
++
++#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
++    (((a) & 0xff00ff00) >> 8))
++#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
++#define CHAN2G(_freq,_idx) { \
++    .band = INDEX_80211_BAND_2GHZ, \
++    .center_freq = (_freq), \
++    .hw_value = (_idx), \
++    .max_power = 20, \
++}
++#ifndef WLAN_CIPHER_SUITE_SMS4
++#define WLAN_CIPHER_SUITE_SMS4 0x00147201
++#endif
++#define SHPCHECK(__hw_rate,__flags) \
++    ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate +3 ) : 0)
++#define RATE(_bitrate,_hw_rate,_flags) { \
++    .bitrate = (_bitrate), \
++    .flags = (_flags), \
++    .hw_value = (_hw_rate), \
++    .hw_value_short = SHPCHECK(_hw_rate,_flags) \
++}
++extern struct ssv6xxx_cfg ssv_cfg;
++static const struct ieee80211_channel ssv6200_2ghz_chantable[] = {
++	CHAN2G(2412, 1),
++	CHAN2G(2417, 2),
++	CHAN2G(2422, 3),
++	CHAN2G(2427, 4),
++	CHAN2G(2432, 5),
++	CHAN2G(2437, 6),
++	CHAN2G(2442, 7),
++	CHAN2G(2447, 8),
++	CHAN2G(2452, 9),
++	CHAN2G(2457, 10),
++	CHAN2G(2462, 11),
++	CHAN2G(2467, 12),
++	CHAN2G(2472, 13),
++	CHAN2G(2484, 14),
++};
++
++static struct ieee80211_rate ssv6200_legacy_rates[] = {
++	RATE(10, 0x00, 0),
++	RATE(20, 0x01, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATE(55, 0x02, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATE(110, 0x03, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATE(60, 0x07, 0),
++	RATE(90, 0x08, 0),
++	RATE(120, 0x09, 0),
++	RATE(180, 0x0a, 0),
++	RATE(240, 0x0b, 0),
++	RATE(360, 0x0c, 0),
++	RATE(480, 0x0d, 0),
++	RATE(540, 0x0e, 0),
++};
++
++struct ssv6xxx_ch_cfg ch_cfg_z[] = {
++	{ADR_ABB_REGISTER_1, 0, 0x151559fc},
++	{ADR_LDO_REGISTER, 0, 0x00eb7c1c},
++	{ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
++};
++
++struct ssv6xxx_ch_cfg ch_cfg_p[] = {
++	{ADR_ABB_REGISTER_1, 0, 0x151559fc},
++	{ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
++};
++
++int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int ret = 0;
++	dev_dbg(sh->sc->dev, "# Do init_cali (iq)\n");
++	skb =
++	    ssv_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE +
++			  RF_SETTING_SIZE);
++	if (skb == NULL) {
++		dev_err(sh->sc->dev, "init ssv6xxx_do_iq_calib failure\n");
++		return (-1);
++	}
++	if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
++	    (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
++		dev_warn(sh->sc->dev, "wrong RF or PHY table size\n");
++		WARN_ON(1);
++		return (-1);
++	}
++	skb->data_len =
++	    HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
++	host_cmd->len = skb->data_len;
++	p_cfg->phy_tbl_size = PHY_SETTING_SIZE;
++	p_cfg->rf_tbl_size = RF_SETTING_SIZE;
++	memcpy(host_cmd->dat32, p_cfg, IQK_CFG_LEN);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, ssv6200_rf_tbl,
++	       RF_SETTING_SIZE);
++	sh->hci.hci_ops->hci_send_cmd(skb);
++	ssv_skb_free(skb);
++	{
++		u32 timeout;
++		sh->sc->iq_cali_done = IQ_CALI_RUNNING;
++		set_current_state(TASK_INTERRUPTIBLE);
++		timeout = wait_event_interruptible_timeout(sh->sc->fw_wait_q,
++							   sh->sc->iq_cali_done,
++							   msecs_to_jiffies
++							   (500));
++		set_current_state(TASK_RUNNING);
++		if (timeout == 0)
++			return -ETIME;
++		if (sh->sc->iq_cali_done != IQ_CALI_OK)
++			return (-1);
++	}
++	return ret;
++}
++
++#define HT_CAP_RX_STBC_ONE_STREAM 0x1
++#if defined(CONFIG_PM)
++static const struct wiphy_wowlan_support wowlan_support = {
++#ifdef SSV_WAKEUP_HOST
++	.flags = WIPHY_WOWLAN_ANY,
++#else
++	.flags = WIPHY_WOWLAN_DISCONNECT,
++#endif
++	.n_patterns = 0,
++	.pattern_max_len = 0,
++	.pattern_min_len = 0,
++	.max_pkt_offset = 0,
++};
++#endif
++static void ssv6xxx_set_80211_hw_capab(struct ssv_softc *sc)
++{
++	struct ieee80211_hw *hw = sc->hw;
++	struct ssv_hw *sh = sc->sh;
++	struct ieee80211_sta_ht_cap *ht_info;
++	ieee80211_hw_set(hw, SIGNAL_DBM);
++	hw->rate_control_algorithm = "ssv6xxx_rate_control";
++	//hw->rate_control_algorithm = NULL; // NULL selects default
++	ht_info = &sc->sbands[INDEX_80211_BAND_2GHZ].ht_cap;
++	ampdu_db_log("sh->cfg.hw_caps = 0x%x\n", sh->cfg.hw_caps);
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_HT) {
++		if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX) {
++			ieee80211_hw_set(hw, AMPDU_AGGREGATION);
++			ampdu_db_log("set IEEE80211_HW_AMPDU_AGGREGATION(%d)\n",
++				     ieee80211_hw_check(hw, AMPDU_AGGREGATION));
++		}
++		ht_info->cap = IEEE80211_HT_CAP_SM_PS;
++		if (sh->cfg.hw_caps & SSV6200_HW_CAP_GF) {
++			ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
++			ht_info->cap |=
++			    HT_CAP_RX_STBC_ONE_STREAM <<
++			    IEEE80211_HT_CAP_RX_STBC_SHIFT;
++		}
++		if (sh->cfg.hw_caps & SSV6200_HT_CAP_SGI_20)
++			ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
++		ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_32K;
++		ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
++		memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
++		ht_info->mcs.rx_mask[0] = 0xff;
++		ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
++		ht_info->mcs.rx_highest = cpu_to_le16(SSV6200_RX_HIGHEST_RATE);
++		ht_info->ht_supported = true;
++	}
++	hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
++		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_CLIENT);
++		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_GO);
++		hw->wiphy->iface_combinations = ssv6xxx_iface_combinations_p2p;
++		hw->wiphy->n_iface_combinations =
++		    ARRAY_SIZE(ssv6xxx_iface_combinations_p2p);
++	}
++	hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_AP) {
++		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
++		hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
++	}
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_TDLS) {
++		hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
++		hw->wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
++		dev_info(sc->dev, "TDLS function enabled in sta.cfg\n");
++	}
++	hw->queues = 4;
++	hw->max_rates = 4;
++	hw->max_listen_interval = 1;
++	hw->max_rate_tries = HW_MAX_RATE_TRIES;
++	hw->extra_tx_headroom = TXPB_OFFSET + AMPDU_DELIMITER_LEN;
++	if (sizeof(struct ampdu_hdr_st) > SSV_SKB_info_size)
++		hw->extra_tx_headroom += sizeof(struct ampdu_hdr_st);
++	else
++		hw->extra_tx_headroom += SSV_SKB_info_size;
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
++		hw->wiphy->bands[INDEX_80211_BAND_2GHZ] =
++		    &sc->sbands[INDEX_80211_BAND_2GHZ];
++	}
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)
++#ifdef PREFER_RX
++		hw->max_rx_aggregation_subframes = 64;
++#else
++		hw->max_rx_aggregation_subframes = 16;
++#endif
++	else
++		hw->max_rx_aggregation_subframes = 12;
++	hw->max_tx_aggregation_subframes = 64;
++	hw->sta_data_size = sizeof(struct ssv_sta_priv_data);
++	hw->vif_data_size = sizeof(struct ssv_vif_priv_data);
++	memcpy(sh->maddr[0].addr, &sh->cfg.maddr[0][0], ETH_ALEN);
++	hw->wiphy->addresses = sh->maddr;
++	hw->wiphy->n_addresses = 1;
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
++		int i;
++		for (i = 1; i < SSV6200_MAX_HW_MAC_ADDR; i++) {
++			memcpy(sh->maddr[i].addr, sh->maddr[i - 1].addr,
++			       ETH_ALEN);
++			sh->maddr[i].addr[5]++;
++			hw->wiphy->n_addresses++;
++		}
++	}
++	if (!is_zero_ether_addr(sh->cfg.maddr[1])) {
++		memcpy(sh->maddr[1].addr, sh->cfg.maddr[1], ETH_ALEN);
++		if (hw->wiphy->n_addresses < 2)
++			hw->wiphy->n_addresses = 2;
++	}
++#if defined(CONFIG_PM)
++	hw->wiphy->wowlan = &wowlan_support;
++#endif
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) && defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
++    {
++        int err = 0;
++        struct ssv_softc *softc = (struct ssv_softc *)hw->priv;
++        if (softc)
++        {
++            set_wiphy_dev(hw->wiphy, softc->dev);
++            *((struct ssv_softc **)wiphy_priv(hw->wiphy)) = softc;
++        }
++       	dev_dbg(sc->dev, "Registering Vendor80211\n");
++       	err = ssv_cfgvendor_attach(hw->wiphy);
++       	if (unlikely(err < 0)) {
++       		dev_err(sc->dev, "Couldn not attach vendor commands (%d)\n", err);
++       	}
++    }
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
++}
++
++void ssv6xxx_watchdog_restart_hw(struct ssv_softc *sc)
++{
++	dev_dbg(sc->dev, "%s()\n", __FUNCTION__);
++	sc->restart_counter++;
++	sc->force_triger_reset = true;
++	sc->beacon_info[0].pubf_addr = 0x00;
++	sc->beacon_info[1].pubf_addr = 0x00;
++	ieee80211_restart_hw(sc->hw);
++}
++
++extern struct rssi_res_st rssi_res;
++void ssv6200_watchdog_timeout(struct timer_list *t)
++{
++	static u32 count = 0;
++	struct rssi_res_st *rssi_tmp0 = NULL, *rssi_tmp1 = NULL;
++	struct ssv_softc *sc = from_timer(sc, t, watchdog_timeout);
++	if (sc->watchdog_flag == WD_BARKING) {
++		ssv6xxx_watchdog_restart_hw(sc);
++		mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++		return;
++	}
++	if (sc->watchdog_flag != WD_SLEEP)
++		sc->watchdog_flag = WD_BARKING;
++	count++;
++	if (count == 6) {
++		count = 0;
++		if (list_empty(&rssi_res.rssi_list)) {
++			return;
++		}
++		list_for_each_entry_safe(rssi_tmp0, rssi_tmp1,
++					 &rssi_res.rssi_list, rssi_list) {
++			if (rssi_tmp0->timeout) {
++				list_del_rcu(&rssi_tmp0->rssi_list);
++				kfree(rssi_tmp0);
++			}
++		}
++	}
++	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++	return;
++}
++
++static void ssv6xxx_preload_sw_cipher(void)
++{
++}
++
++static int ssv6xxx_init_softc(struct ssv_softc *sc)
++{
++	void *channels;
++	int ret = 0;
++	sc->sc_flags = SC_OP_INVALID;
++	mutex_init(&sc->mutex);
++	mutex_init(&sc->mem_mutex);
++	sc->config_wq = create_singlethread_workqueue("ssv6xxx_cong_wq");
++	sc->thermal_wq = create_singlethread_workqueue("ssv6xxx_thermal_wq");
++	INIT_DELAYED_WORK(&sc->thermal_monitor_work, thermal_monitor);
++	INIT_WORK(&sc->set_tim_work, ssv6200_set_tim_work);
++	INIT_WORK(&sc->bcast_start_work, ssv6200_bcast_start_work);
++	INIT_DELAYED_WORK(&sc->bcast_stop_work, ssv6200_bcast_stop_work);
++	INIT_DELAYED_WORK(&sc->bcast_tx_work, ssv6200_bcast_tx_work);
++	INIT_WORK(&sc->set_ampdu_rx_add_work, ssv6xxx_set_ampdu_rx_add_work);
++	INIT_WORK(&sc->set_ampdu_rx_del_work, ssv6xxx_set_ampdu_rx_del_work);
++	sc->mac_deci_tbl = sta_deci_tbl;
++	memset((void *)&sc->tx, 0, sizeof(struct ssv_tx));
++	sc->tx.hw_txqid[WMM_AC_VO] = 3;
++	sc->tx.ac_txqid[3] = WMM_AC_VO;
++	sc->tx.hw_txqid[WMM_AC_VI] = 2;
++	sc->tx.ac_txqid[2] = WMM_AC_VI;
++	sc->tx.hw_txqid[WMM_AC_BE] = 1;
++	sc->tx.ac_txqid[1] = WMM_AC_BE;
++	sc->tx.hw_txqid[WMM_AC_BK] = 0;
++	sc->tx.ac_txqid[0] = WMM_AC_BK;
++	INIT_LIST_HEAD(&sc->tx.ampdu_tx_que);
++	spin_lock_init(&sc->tx.ampdu_tx_que_lock);
++	memset((void *)&sc->rx, 0, sizeof(struct ssv_rx));
++	spin_lock_init(&sc->rx.rxq_lock);
++	skb_queue_head_init(&sc->rx.rxq_head);
++	sc->rx.rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++	if (sc->rx.rx_buf == NULL)
++		return -ENOMEM;
++	memset(&sc->bcast_txq, 0, sizeof(struct ssv6xxx_bcast_txq));
++	spin_lock_init(&sc->bcast_txq.txq_lock);
++	skb_queue_head_init(&sc->bcast_txq.qhead);
++	spin_lock_init(&sc->ps_state_lock);
++#ifdef CONFIG_P2P_NOA
++	spin_lock_init(&sc->p2p_noa.p2p_config_lock);
++#endif
++	if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
++		channels = kmemdup(ssv6200_2ghz_chantable,
++				   sizeof(ssv6200_2ghz_chantable), GFP_KERNEL);
++		if (!channels) {
++			kfree(sc->rx.rx_buf);
++			return -ENOMEM;
++		}
++		sc->sbands[INDEX_80211_BAND_2GHZ].channels = channels;
++		sc->sbands[INDEX_80211_BAND_2GHZ].band = INDEX_80211_BAND_2GHZ;
++		sc->sbands[INDEX_80211_BAND_2GHZ].n_channels =
++		    ARRAY_SIZE(ssv6200_2ghz_chantable);
++		sc->sbands[INDEX_80211_BAND_2GHZ].bitrates =
++		    ssv6200_legacy_rates;
++		sc->sbands[INDEX_80211_BAND_2GHZ].n_bitrates =
++		    ARRAY_SIZE(ssv6200_legacy_rates);
++	}
++	sc->cur_channel = NULL;
++	sc->hw_chan = (-1);
++	ssv6xxx_set_80211_hw_capab(sc);
++	ret = ssv6xxx_rate_control_register();
++	if (ret != 0) {
++		dev_warn(sc->dev, "%s(): Failed to register rc algorithm.\n",__FUNCTION__);
++	}
++	init_waitqueue_head(&sc->tx_wait_q);
++	sc->tx_wait_q_woken = 0;
++	skb_queue_head_init(&sc->tx_skb_q);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	sc->max_tx_skb_q_len = 0;
++#endif
++	sc->tx_task = kthread_run(ssv6xxx_tx_task, sc, "ssv6xxx_tx_task");
++	sc->tx_q_empty = false;
++	skb_queue_head_init(&sc->tx_done_q);
++	init_waitqueue_head(&sc->rx_wait_q);
++	sc->rx_wait_q_woken = 0;
++	skb_queue_head_init(&sc->rx_skb_q);
++	sc->rx_task = kthread_run(ssv6xxx_rx_task, sc, "ssv6xxx_rx_task");
++	ssv6xxx_preload_sw_cipher();
++	timer_setup(&sc->watchdog_timeout, ssv6200_watchdog_timeout, 0);
++	init_waitqueue_head(&sc->fw_wait_q);
++	INIT_LIST_HEAD(&rssi_res.rssi_list);
++	rssi_res.rssi = 0;
++	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++	//add_timer(&sc->watchdog_timeout);
++	//if(get_flash_info(sc) == 1)
++	sc->is_sar_enabled = get_flash_info(sc);
++	if (sc->is_sar_enabled)
++		queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
++				   THERMAL_MONITOR_TIME);
++	//schedule_delayed_work(&sc->thermal_monitor_work, THERMAL_MONITOR_TIME);
++	return ret;
++}
++
++static int ssv6xxx_deinit_softc(struct ssv_softc *sc)
++{
++	void *channels;
++	struct sk_buff *skb;
++	u8 remain_size;
++	dev_dbg(sc->dev, "%s():\n", __FUNCTION__);
++	if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
++		channels = sc->sbands[INDEX_80211_BAND_2GHZ].channels;
++		kfree(channels);
++	}
++	ssv_skb_free(sc->rx.rx_buf);
++	sc->rx.rx_buf = NULL;
++	ssv6xxx_rate_control_unregister();
++	cancel_delayed_work_sync(&sc->bcast_tx_work);
++	//ssv6xxx_watchdog_controller(sc->sh ,(u8)SSV6XXX_HOST_CMD_WATCHDOG_STOP);
++	del_timer_sync(&sc->watchdog_timeout);
++	cancel_delayed_work(&sc->thermal_monitor_work);
++	sc->ps_status = PWRSV_PREPARE;
++	flush_workqueue(sc->thermal_wq);
++	destroy_workqueue(sc->thermal_wq);
++	do {
++		skb = ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
++		if (skb)
++			ssv6xxx_txbuf_free_skb(skb, (void *)sc);
++		else
++			break;
++	} while (remain_size);
++	if (sc->tx_task != NULL) {
++		dev_dbg(sc->dev, "Stopping TX task...\n");
++		kthread_stop(sc->tx_task);
++		sc->tx_task = NULL;
++		dev_dbg(sc->dev, "Stopped TX task.\n");
++	}
++	if (sc->rx_task != NULL) {
++		dev_dbg(sc->dev, "Stopping RX task...\n");
++		kthread_stop(sc->rx_task);
++		sc->rx_task = NULL;
++		dev_dbg(sc->dev, "Stopped RX task.\n");
++	}
++	destroy_workqueue(sc->config_wq);
++	return 0;
++}
++
++static void ssv6xxx_hw_set_replay_ignore(struct ssv_hw *sh, u8 ignore)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp = temp & SCRT_RPLY_IGNORE_I_MSK;
++	temp |= (ignore << SCRT_RPLY_IGNORE_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++}
++
++int ssv6xxx_init_mac(struct ssv_hw *sh)
++{
++	struct ssv_softc *sc = sh->sc;
++	int i = 0, ret = 0;
++
++	u32 *ptr, id_len, regval, temp[0x8];
++	char *chip_id = sh->chip_id;
++	SMAC_REG_READ(sh, ADR_IC_TIME_TAG_1, &regval);
++	sh->chip_tag = ((u64) regval << 32);
++	SMAC_REG_READ(sh, ADR_IC_TIME_TAG_0, &regval);
++	sh->chip_tag |= (regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_3, &regval);
++	*((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_2, &regval);
++	*((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_1, &regval);
++	*((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_0, &regval);
++	*((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
++	chip_id[12 + sizeof(u32)] = 0;
++	dev_info(sh->sc->dev, "chip id: %s, tag: %llx\n", chip_id, sh->chip_tag);
++	if (sc->ps_status == PWRSV_ENABLE) {
++		SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
++			       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
++			       (M_ENG_HWHCI << 8));
++		SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++			       M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#if Enable_AMPDU_FW_Retry
++		SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
++			       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI <<
++								 8));
++#else
++		SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
++			       M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#endif
++		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
++			       (sc->mac_deci_tbl[6]));
++		return ret;
++	}
++	SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (0 << RG_PHY_MD_EN_SFT),
++			  RG_PHY_MD_EN_MSK);
++	SMAC_REG_WRITE(sh, ADR_BRG_SW_RST, 1 << MAC_SW_RST_SFT);
++	do {
++		SMAC_REG_READ(sh, ADR_BRG_SW_RST, &regval);
++		i++;
++		if (i > 10000) {
++			dev_err(sh->sc->dev, "MAC reset fail !!!!\n");
++			WARN_ON(1);
++			ret = 1;
++			goto exit;
++		}
++	} while (regval != 0);
++	SMAC_REG_WRITE(sc->sh, ADR_TXQ4_MTX_Q_AIFSN, 0xffff2101);
++	SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC, 0,
++			  MTX_HALT_MNG_UNTIL_DTIM_MSK);
++	SMAC_REG_WRITE(sh, ADR_CONTROL, 0x12000006);
++	SMAC_REG_WRITE(sh, ADR_RX_TIME_STAMP_CFG,
++		       ((28 << MRX_STP_OFST_SFT) | 0x01));
++	SMAC_REG_WRITE(sh, ADR_HCI_TX_RX_INFO_SIZE,
++		       ((u32) (TXPB_OFFSET) << TX_PBOFFSET_SFT) |
++		       ((u32) (sh->tx_desc_len) << TX_INFO_SIZE_SFT) |
++		       ((u32) (sh->rx_desc_len) << RX_INFO_SIZE_SFT) |
++		       ((u32) (sh->rx_pinfo_pad) << RX_LAST_PHY_SIZE_SFT)
++	    );
++	SMAC_REG_READ(sh, ADR_MMU_CTRL, &regval);
++	regval |= (0xff << MMU_SHARE_MCU_SFT);
++	SMAC_REG_WRITE(sh, ADR_MMU_CTRL, regval);
++	SMAC_REG_READ(sh, ADR_MRX_WATCH_DOG, &regval);
++	regval &= 0xfffffff0;
++	SMAC_REG_WRITE(sh, ADR_MRX_WATCH_DOG, regval);
++	SMAC_REG_READ(sh, ADR_TRX_ID_THRESHOLD, &id_len);
++	id_len = (id_len & 0xffff0000) |
++	    (SSV6200_ID_TX_THRESHOLD << TX_ID_THOLD_SFT) |
++	    (SSV6200_ID_RX_THRESHOLD << RX_ID_THOLD_SFT);
++	SMAC_REG_WRITE(sh, ADR_TRX_ID_THRESHOLD, id_len);
++	SMAC_REG_READ(sh, ADR_ID_LEN_THREADSHOLD1, &id_len);
++	id_len = (id_len & 0x0f) |
++	    (SSV6200_PAGE_TX_THRESHOLD << ID_TX_LEN_THOLD_SFT) |
++	    (SSV6200_PAGE_RX_THRESHOLD << ID_RX_LEN_THOLD_SFT);
++	SMAC_REG_WRITE(sh, ADR_ID_LEN_THREADSHOLD1, id_len);
++#ifdef CONFIG_SSV_CABRIO_MB_DEBUG
++	SMAC_REG_READ(sh, ADR_MB_DBG_CFG3, &regval);
++	regval |= (debug_buffer << 0);
++	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG3, regval);
++	SMAC_REG_READ(sh, ADR_MB_DBG_CFG2, &regval);
++	regval |= (DEBUG_SIZE << 16);
++	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG2, regval);
++	SMAC_REG_READ(sh, ADR_MB_DBG_CFG1, &regval);
++	regval |= (1 << MB_DBG_EN_SFT);
++	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG1, regval);
++	SMAC_REG_READ(sh, ADR_MBOX_HALT_CFG, &regval);
++	regval |= (1 << MB_ERR_AUTO_HALT_EN_SFT);
++	SMAC_REG_WRITE(sh, ADR_MBOX_HALT_CFG, regval);
++#endif
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
++	regval |= (1 << MTX_TSF_TIMER_EN_SFT);
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
++	SMAC_REG_WRITE(sh, 0xcd010004, 0x1213);
++	for (i = 0; i < SSV_RC_MAX_STA; i++) {
++		if (i == 0) {
++			sh->hw_buf_ptr[i] =
++			    ssv6xxx_pbuf_alloc(sc,
++					       sizeof(phy_info_tbl) +
++					       sizeof(struct ssv6xxx_hw_sec),
++					       NOTYPE_BUF);
++			if ((sh->hw_buf_ptr[i] >> 28) != 8) {
++				dev_err(sh->sc->dev, "opps allocate pbuf error\n");
++				WARN_ON(1);
++				ret = 1;
++				goto exit;
++			}
++		} else {
++			sh->hw_buf_ptr[i] =
++			    ssv6xxx_pbuf_alloc(sc,
++					       sizeof(struct ssv6xxx_hw_sec),
++					       NOTYPE_BUF);
++			if ((sh->hw_buf_ptr[i] >> 28) != 8) {
++				dev_err(sh->sc->dev, "opps allocate pbuf error\n");
++				WARN_ON(1);
++				ret = 1;
++				goto exit;
++			}
++		}
++	}
++	for (i = 0; i < 0x8; i++) {
++		temp[i] = 0;
++		temp[i] = ssv6xxx_pbuf_alloc(sc, 256, NOTYPE_BUF);
++	}
++	for (i = 0; i < 0x8; i++) {
++		if (temp[i] == 0x800e0000)
++			dev_dbg(sh->sc->dev, "Found 0x800e0000 at position %d\n", i);
++		else
++			ssv6xxx_pbuf_free(sc, temp[i]);
++	}
++	for (i = 0; i < SSV_RC_MAX_STA; i++)
++		sh->hw_sec_key[i] = sh->hw_buf_ptr[i];
++	for (i = 0; i < SSV_RC_MAX_STA; i++) {
++		int x;
++		for (x = 0; x < sizeof(struct ssv6xxx_hw_sec); x += 4) {
++			SMAC_REG_WRITE(sh, sh->hw_sec_key[i] + x, 0);
++		}
++	}
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &regval);
++	regval &= SCRT_PKT_ID_I_MSK;
++	regval |= ((sh->hw_sec_key[0] >> 16) << SCRT_PKT_ID_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, regval);
++	sh->hw_pinfo = sh->hw_sec_key[0] + sizeof(struct ssv6xxx_hw_sec);
++	for (i = 0, ptr = phy_info_tbl; i < PHY_INFO_TBL1_SIZE; i++, ptr++) {
++		SMAC_REG_WRITE(sh, ADR_INFO0 + i * 4, *ptr);
++		SMAC_REG_CONFIRM(sh, ADR_INFO0 + i * 4, *ptr);
++	}
++	for (i = 0; i < PHY_INFO_TBL2_SIZE; i++, ptr++) {
++		SMAC_REG_WRITE(sh, sh->hw_pinfo + i * 4, *ptr);
++		SMAC_REG_CONFIRM(sh, sh->hw_pinfo + i * 4, *ptr);
++	}
++	for (i = 0; i < PHY_INFO_TBL3_SIZE; i++, ptr++) {
++		SMAC_REG_WRITE(sh, sh->hw_pinfo +
++			       (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
++		SMAC_REG_CONFIRM(sh, sh->hw_pinfo +
++				 (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
++	}
++	SMAC_REG_WRITE(sh, ADR_INFO_RATE_OFFSET, 0x00040000);
++	SMAC_REG_WRITE(sh, ADR_INFO_IDX_ADDR, sh->hw_pinfo);
++	SMAC_REG_WRITE(sh, ADR_INFO_LEN_ADDR,
++		       sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
++	dev_dbg(sh->sc->dev, "ADR_INFO_IDX_ADDR[%08x] ADR_INFO_LEN_ADDR[%08x]\n",
++	       sh->hw_pinfo, sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
++	SMAC_REG_WRITE(sh, ADR_GLBLE_SET,
++		       (0 << OP_MODE_SFT) | (0 << SNIFFER_MODE_SFT) | (1 <<
++								       DUP_FLT_SFT)
++		       | (SSV6200_TX_PKT_RSVD_SETTING << TX_PKT_RSVD_SFT) |
++		       ((u32) (RXPB_OFFSET) << PB_OFFSET_SFT)
++	    );
++	SMAC_REG_WRITE(sh, ADR_STA_MAC_0, *((u32 *) & sh->cfg.maddr[0][0]));
++	SMAC_REG_WRITE(sh, ADR_STA_MAC_1, *((u32 *) & sh->cfg.maddr[0][4]));
++	SMAC_REG_WRITE(sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
++	SMAC_REG_WRITE(sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
++	SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_0, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_1, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_0, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_1, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_REASON_TRAP0, 0x7FBC7F87);
++	SMAC_REG_WRITE(sh, ADR_REASON_TRAP1, 0x0000003F);
++	SMAC_REG_WRITE(sh, ADR_TRAP_HW_ID, M_ENG_CPU);
++	SMAC_REG_WRITE(sh, ADR_WSID0, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_WSID1, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
++		       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) | (M_ENG_HWHCI <<
++								 8));
++#if defined(CONFIG_P2P_NOA) || defined(CONFIG_RX_MGMT_CHECK)
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++#else
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#endif
++#if Enable_AMPDU_FW_Retry
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++#else
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#endif
++	ssv6xxx_hw_set_replay_ignore(sh, 1);
++	ssv6xxx_update_decision_table(sc);
++	SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_STA,
++			  OP_MODE_MSK);
++	SMAC_REG_WRITE(sh, ADR_SDIO_MASK, 0xfffe1fff);
++	SMAC_REG_WRITE(sh, ADR_TX_LIMIT_INTR, 0x80000000 |
++		       SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER << 16 |
++		       SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER);
++#ifdef CONFIG_SSV_SUPPORT_BTCX
++	SMAC_REG_WRITE(sh, ADR_BTCX0,
++		       COEXIST_EN_MSK | (WIRE_MODE_SZ << WIRE_MODE_SFT)
++		       | WIFI_TX_SW_POL_MSK | BT_SW_POL_MSK);
++	SMAC_REG_WRITE(sh, ADR_BTCX1,
++		       SSV6200_BT_PRI_SMP_TIME | (SSV6200_BT_STA_SMP_TIME <<
++						  BT_STA_SMP_TIME_SFT)
++		       | (SSV6200_WLAN_REMAIN_TIME << WLAN_REMAIN_TIME_SFT));
++	SMAC_REG_WRITE(sh, ADR_SWITCH_CTL, BT_2WIRE_EN_MSK);
++	SMAC_REG_WRITE(sh, ADR_PAD7, 1);
++	SMAC_REG_WRITE(sh, ADR_PAD8, 0);
++	SMAC_REG_WRITE(sh, ADR_PAD9, 1);
++	SMAC_REG_WRITE(sh, ADR_PAD25, 1);
++	SMAC_REG_WRITE(sh, ADR_PAD27, 8);
++	SMAC_REG_WRITE(sh, ADR_PAD28, 8);
++#endif
++	dev_info(sh->sc->dev, "attempt to load firmware %s\n", WIFI_FIRMWARE_NAME);
++	ret = SMAC_LOAD_FW(sh, WIFI_FIRMWARE_NAME, 0);
++
++	SMAC_REG_READ(sh, FW_VERSION_REG, &regval);
++	if (regval == ssv_firmware_version) {
++		SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (1 << RG_PHY_MD_EN_SFT),
++				  RG_PHY_MD_EN_MSK);
++		dev_info(sh->sc->dev, "Firmware version %d\n", regval);
++	} else {
++		dev_err(sh->sc->dev, "Firmware version not mapping %d\n", regval);
++		ret = -1;
++	}
++	ssv6xxx_watchdog_controller(sh, (u8) SSV6XXX_HOST_CMD_WATCHDOG_START);
++ exit:
++	return ret;
++}
++
++void ssv6xxx_deinit_mac(struct ssv_softc *sc)
++{
++	int i;
++	for (i = 0; i < SSV_RC_MAX_STA; i++) {
++		if (sc->sh->hw_buf_ptr[i])
++			ssv6xxx_pbuf_free(sc, sc->sh->hw_buf_ptr[i]);
++	}
++}
++
++void inline ssv6xxx_deinit_hw(struct ssv_softc *sc)
++{
++	dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
++	ssv6xxx_deinit_mac(sc);
++}
++
++void ssv6xxx_restart_hw(struct ssv_softc *sc)
++{
++	dev_info(sc->dev, "Software MAC reset\n");
++	sc->restart_counter++;
++	sc->force_triger_reset = true;
++	HCI_STOP(sc->sh);
++	SMAC_REG_WRITE(sc->sh, 0xce000004, 0x0);
++	sc->beacon_info[0].pubf_addr = 0x00;
++	sc->beacon_info[1].pubf_addr = 0x00;
++	ieee80211_restart_hw(sc->hw);
++}
++
++extern struct ssv6xxx_iqk_cfg init_iqk_cfg;
++static int ssv6xxx_init_hw(struct ssv_hw *sh)
++{
++	int ret = 0, i = 0, x = 0;
++	u32 regval;
++	sh->tx_desc_len = SSV6XXX_TX_DESC_LEN;
++	sh->rx_desc_len = SSV6XXX_RX_DESC_LEN;
++	sh->rx_pinfo_pad = 0x04;
++	sh->tx_page_available = SSV6200_PAGE_TX_THRESHOLD;
++	sh->ampdu_divider = SSV6XXX_AMPDU_DIVIDER;
++	memset(sh->page_count, 0, sizeof(sh->page_count));
++	if (sh->cfg.force_chip_identity) {
++		dev_info(sh->sc->dev, "Force use external RF setting [%08x]\n",
++		       sh->cfg.force_chip_identity);
++		sh->cfg.chip_identity = sh->cfg.force_chip_identity;
++	}
++	if (sh->cfg.chip_identity == SSV6051Z) {
++		sh->p_ch_cfg = &ch_cfg_z[0];
++		sh->ch_cfg_size =
++		    sizeof(ch_cfg_z) / sizeof(struct ssv6xxx_ch_cfg);
++		memcpy(phy_info_tbl, phy_info_6051z, sizeof(phy_info_6051z));
++	} else if (sh->cfg.chip_identity == SSV6051P) {
++		sh->p_ch_cfg = &ch_cfg_p[0];
++		sh->ch_cfg_size =
++		    sizeof(ch_cfg_p) / sizeof(struct ssv6xxx_ch_cfg);
++	}
++	switch (sh->cfg.chip_identity) {
++	case SSV6051Q_P1:
++	case SSV6051Q_P2:
++	case SSV6051Q:
++		dev_info(sh->sc->dev, "Using SSV6051Q setting\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == 0xCE010008)
++				ssv6200_rf_tbl[i].data = 0x008DF61B;
++			if (ssv6200_rf_tbl[i].address == 0xCE010014)
++				ssv6200_rf_tbl[i].data = 0x3D3E84FE;
++			if (ssv6200_rf_tbl[i].address == 0xCE010018)
++				ssv6200_rf_tbl[i].data = 0x01457D79;
++			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
++				ssv6200_rf_tbl[i].data = 0x000103A7;
++			if (ssv6200_rf_tbl[i].address == 0xCE010020)
++				ssv6200_rf_tbl[i].data = 0x000103A6;
++			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
++				ssv6200_rf_tbl[i].data = 0x00032CA8;
++			if (ssv6200_rf_tbl[i].address == 0xCE010048)
++				ssv6200_rf_tbl[i].data = 0xFCCCCF27;
++			if (ssv6200_rf_tbl[i].address == 0xCE010050)
++				ssv6200_rf_tbl[i].data = 0x0047C000;
++		}
++		break;
++	case SSV6051Z:
++		dev_info(sh->sc->dev, "Using SSV6051Z setting\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == 0xCE010008)
++				ssv6200_rf_tbl[i].data = 0x004D561C;
++			if (ssv6200_rf_tbl[i].address == 0xCE010014)
++				ssv6200_rf_tbl[i].data = 0x3D9E84FE;
++			if (ssv6200_rf_tbl[i].address == 0xCE010018)
++				ssv6200_rf_tbl[i].data = 0x00457D79;
++			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
++				ssv6200_rf_tbl[i].data = 0x000103EB;
++			if (ssv6200_rf_tbl[i].address == 0xCE010020)
++				ssv6200_rf_tbl[i].data = 0x000103EA;
++			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
++				ssv6200_rf_tbl[i].data = 0x00062CA8;
++			if (ssv6200_rf_tbl[i].address == 0xCE010048)
++				ssv6200_rf_tbl[i].data = 0xFCCCCF27;
++			if (ssv6200_rf_tbl[i].address == 0xCE010050)
++				ssv6200_rf_tbl[i].data = 0x0047C000;
++		}
++		break;
++	case SSV6051P:
++		dev_info(sh->sc->dev, "Using SSV6051P setting\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == 0xCE010008)
++				ssv6200_rf_tbl[i].data = 0x008B7C1C;
++			if (ssv6200_rf_tbl[i].address == 0xCE010014)
++				ssv6200_rf_tbl[i].data = 0x3D7E84FE;
++			if (ssv6200_rf_tbl[i].address == 0xCE010018)
++				ssv6200_rf_tbl[i].data = 0x01457D79;
++			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
++				ssv6200_rf_tbl[i].data = 0x000103EB;
++			if (ssv6200_rf_tbl[i].address == 0xCE010020)
++				ssv6200_rf_tbl[i].data = 0x000103EA;
++			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
++				ssv6200_rf_tbl[i].data = 0x00032CA8;
++			if (ssv6200_rf_tbl[i].address == 0xCE010048)
++				ssv6200_rf_tbl[i].data = 0xFCCCCC27;
++			if (ssv6200_rf_tbl[i].address == 0xCE010050)
++				ssv6200_rf_tbl[i].data = 0x0047C000;
++			if (ssv6200_rf_tbl[i].address == 0xC0001D00)
++				ssv6200_rf_tbl[i].data = 0x5E000040;
++		}
++		break;
++	default:
++		dev_err(sh->sc->dev, "No RF setting\n");
++		break;
++	}
++	if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M) {
++		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_26M;
++		dev_info(sh->sc->dev, "Crystal frequency: 26 Mhz\n");
++	} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
++		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_40M;
++		dev_info(sh->sc->dev, "Crystal frequency: 40 Mhz\n");
++	} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M) {
++		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_24M;
++		dev_info(sh->sc->dev, "Crystal frequency: 24 Mhz\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == ADR_SX_ENABLE_REGISTER)
++				ssv6200_rf_tbl[i].data = 0x0003E07C;
++			if (ssv6200_rf_tbl[i].address ==
++			    ADR_DPLL_DIVIDER_REGISTER)
++				ssv6200_rf_tbl[i].data = 0x00406000;
++			if (ssv6200_rf_tbl[i].address ==
++			    ADR_DPLL_FB_DIVIDER_REGISTERS_I)
++				ssv6200_rf_tbl[i].data = 0x00000028;
++			if (ssv6200_rf_tbl[i].address ==
++			    ADR_DPLL_FB_DIVIDER_REGISTERS_II)
++				ssv6200_rf_tbl[i].data = 0x00000000;
++		}
++	} else {
++		dev_warn(sh->sc->dev, "Illegal crystal setting, using default value of 26 Mhz\n");
++	}
++	for (i = 0;
++	     i < sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++	     i++) {
++		if (ssv6200_rf_tbl[i].address ==
++		    ADR_SYN_KVCO_XO_FINE_TUNE_CBANK) {
++			if (sh->cfg.crystal_frequency_offset) {
++				ssv6200_rf_tbl[i].data &=
++				    RG_XOSC_CBANK_XO_I_MSK;
++				ssv6200_rf_tbl[i].data |=
++				    (sh->cfg.
++				     crystal_frequency_offset <<
++				     RG_XOSC_CBANK_XO_SFT);
++			}
++		}
++	}
++	for (i = 0; i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
++	     i++) {
++		if (phy_setting[i].address == ADR_TX_GAIN_FACTOR) {
++			switch (sh->cfg.chip_identity) {
++			case SSV6051Q_P1:
++			case SSV6051Q_P2:
++			case SSV6051Q:
++				dev_dbg(sh->sc->dev, "SSV6051Q setting [0x5B606C72]\n");
++				phy_setting[i].data = 0x5B606C72;
++				break;
++			case SSV6051Z:
++				dev_dbg(sh->sc->dev, "SSV6051Z setting [0x60606060]\n");
++				phy_setting[i].data = 0x60606060;
++				break;
++			case SSV6051P:
++				dev_dbg(sh->sc->dev, "SSV6051P setting [0x6C726C72]\n");
++				phy_setting[i].data = 0x6C726C72;
++				break;
++			default:
++				dev_dbg(sh->sc->dev, "Use default power setting\n");
++				break;
++			}
++			if (sh->cfg.wifi_tx_gain_level_b) {
++				phy_setting[i].data &= 0xffff0000;
++				phy_setting[i].data |=
++				    wifi_tx_gain[sh->cfg.
++						 wifi_tx_gain_level_b] &
++				    0x0000ffff;
++			}
++			if (sh->cfg.wifi_tx_gain_level_gn) {
++				phy_setting[i].data &= 0x0000ffff;
++				phy_setting[i].data |=
++				    wifi_tx_gain[sh->cfg.
++						 wifi_tx_gain_level_gn] &
++				    0xffff0000;
++			}
++			dev_dbg(sh->sc->dev, "TX power setting 0x%x\n", phy_setting[i].data);
++			init_iqk_cfg.cfg_def_tx_scale_11b =
++			    (phy_setting[i].data >> 0) & 0xff;
++			init_iqk_cfg.cfg_def_tx_scale_11b_p0d5 =
++			    (phy_setting[i].data >> 8) & 0xff;
++			init_iqk_cfg.cfg_def_tx_scale_11g =
++			    (phy_setting[i].data >> 16) & 0xff;
++			init_iqk_cfg.cfg_def_tx_scale_11g_p0d5 =
++			    (phy_setting[i].data >> 24) & 0xff;
++			break;
++		}
++	}
++	if (sh->cfg.volt_regulator == SSV6XXX_VOLT_LDO_CONVERT) {
++		dev_info(sh->sc->dev, "Using LDO voltage regulator\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
++				ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
++				ssv6200_rf_tbl[i].data |= 0x00000000;
++			}
++		}
++	} else if (sh->cfg.volt_regulator == SSV6XXX_VOLT_DCDC_CONVERT) {
++		dev_info(sh->sc->dev, "Using DCDC buck regulator\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
++				ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
++				ssv6200_rf_tbl[i].data |= 0x00000001;
++			}
++		}
++	} else {
++		dev_warn(sh->sc->dev, "Illegal regulator setting, using DCDC buck as default\n");
++	}
++	while (ssv_cfg.configuration[x][0]) {
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address ==
++			    ssv_cfg.configuration[x][0]) {
++				ssv6200_rf_tbl[i].data =
++				    ssv_cfg.configuration[x][1];
++				break;
++			}
++		}
++		for (i = 0;
++		     i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (phy_setting[i].address ==
++			    ssv_cfg.configuration[x][0]) {
++				phy_setting[i].data =
++				    ssv_cfg.configuration[x][1];
++				break;
++			}
++		}
++		x++;
++	};
++	if (ret == 0)
++		ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_rf_tbl);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1, 0x00000000);
++	SMAC_REG_READ(sh, ADR_PHY_EN_0, &regval);
++	if (regval & (1 << RG_RF_BB_CLK_SEL_SFT)) {
++		dev_dbg(sh->sc->dev, "already do clock switch\n");
++	} else {
++		dev_dbg(sh->sc->dev, "reset PLL\n");
++		SMAC_REG_READ(sh, ADR_DPLL_CP_PFD_REGISTER, &regval);
++		regval |=
++		    ((1 << RG_DP_BBPLL_PD_SFT) |
++		     (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
++		SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
++		regval &=
++		    ~((1 << RG_DP_BBPLL_PD_SFT) |
++		      (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
++		SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
++		mdelay(10);
++	}
++	if (ret == 0)
++		ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_phy_tbl);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xEAAAAAAA);
++	SMAC_REG_READ(sh, ADR_TRX_DUMMY_REGISTER, &regval);
++	if (regval != 0xEAAAAAAA) {
++		dev_warn(sh->sc->dev, "Unexpected register value\n");
++		WARN_ON(1);
++	}
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PAD53, 0x21);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PAD54, 0x3000);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PIN_SEL_0, 0x4000);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, 0xc0000304, 0x01);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, 0xc0000308, 0x01);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_CLOCK_SELECTION, 0x3);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xAAAAAAAA);
++	if ((ret = ssv6xxx_set_channel(sh->sc, sh->cfg.def_chan)))
++		return ret;
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1,
++				     (RG_PHYRX_MD_EN_MSK | RG_PHYTX_MD_EN_MSK |
++				      RG_PHY11GN_MD_EN_MSK | RG_PHY11B_MD_EN_MSK
++				      | RG_PHYRXFIFO_MD_EN_MSK |
++				      RG_PHYTXFIFO_MD_EN_MSK |
++				      RG_PHY11BGN_MD_EN_MSK));
++	return ret;
++}
++
++static void ssv6xxx_check_mac2(struct ssv_hw *sh)
++{
++	const u8 addr_mask[6] = { 0xfd, 0xff, 0xff, 0xff, 0xff, 0xfc };
++	u8 i;
++	bool invalid = false;
++	for (i = 0; i < 6; i++) {
++		if ((ssv_cfg.maddr[0][i] & addr_mask[i]) !=
++		    (ssv_cfg.maddr[1][i] & addr_mask[i])) {
++			invalid = true;
++			dev_dbg(sh->sc->dev, " i %d , mac1[i] %x, mac2[i] %x, mask %x \n", i,
++			       ssv_cfg.maddr[0][i], ssv_cfg.maddr[1][i],
++			       addr_mask[i]);
++			break;
++		}
++	}
++	if (invalid) {
++		memcpy(&ssv_cfg.maddr[1][0], &ssv_cfg.maddr[0][0], 6);
++		ssv_cfg.maddr[1][5] ^= 0x01;
++		if (ssv_cfg.maddr[1][5] < ssv_cfg.maddr[0][5]) {
++			u8 temp;
++			temp = ssv_cfg.maddr[0][5];
++			ssv_cfg.maddr[0][5] = ssv_cfg.maddr[1][5];
++			ssv_cfg.maddr[1][5] = temp;
++			sh->cfg.maddr[0][5] = ssv_cfg.maddr[0][5];
++		}
++		dev_warn(sh->sc->dev, "MAC 2 address invalid!!\n");
++		dev_warn(sh->sc->dev, "After modification, MAC1 %pM, MAC2 %pM\n",
++		       ssv_cfg.maddr[0], ssv_cfg.maddr[1]);
++	}
++}
++
++static int ssv6xxx_read_configuration(struct ssv_hw *sh)
++{
++	extern u32 sdio_sr_bhvr;
++	if (is_valid_ether_addr(&ssv_cfg.maddr[0][0]))
++		memcpy(&sh->cfg.maddr[0][0], &ssv_cfg.maddr[0][0], ETH_ALEN);
++	if (is_valid_ether_addr(&ssv_cfg.maddr[1][0])) {
++		ssv6xxx_check_mac2(sh);
++		memcpy(&sh->cfg.maddr[1][0], &ssv_cfg.maddr[1][0], ETH_ALEN);
++	}
++	if (ssv_cfg.hw_caps)
++		sh->cfg.hw_caps = ssv_cfg.hw_caps;
++	else
++		sh->cfg.hw_caps = SSV6200_HW_CAP_HT |
++		    SSV6200_HW_CAP_2GHZ |
++		    SSV6200_HW_CAP_SECURITY |
++		    SSV6200_HW_CAP_P2P |
++		    SSV6200_HT_CAP_SGI_20 |
++		    SSV6200_HW_CAP_AMPDU_RX |
++		    SSV6200_HW_CAP_AMPDU_TX | SSV6200_HW_CAP_AP;
++	if (ssv_cfg.def_chan)
++		sh->cfg.def_chan = ssv_cfg.def_chan;
++	else
++		sh->cfg.def_chan = 6;
++	sh->cfg.use_wpa2_only = ssv_cfg.use_wpa2_only;
++	if (ssv_cfg.crystal_type == 26)
++		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_26M;
++	else if (ssv_cfg.crystal_type == 40)
++		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_40M;
++	else if (ssv_cfg.crystal_type == 24)
++		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_24M;
++	else {
++		dev_warn(sh->sc->dev, "Please redefine xtal_clock(wifi.cfg)!!\n");
++		WARN_ON(1);
++		return 1;
++	}
++	if (ssv_cfg.volt_regulator < 2)
++		sh->cfg.volt_regulator = ssv_cfg.volt_regulator;
++	else {
++		dev_warn(sh->sc->dev, "Please redefine volt_regulator(wifi.cfg)!!\n");
++		WARN_ON(1);
++		return 1;
++	}
++	sh->cfg.wifi_tx_gain_level_gn = ssv_cfg.wifi_tx_gain_level_gn;
++	sh->cfg.wifi_tx_gain_level_b = ssv_cfg.wifi_tx_gain_level_b;
++	sh->cfg.rssi_ctl = ssv_cfg.rssi_ctl;
++	sh->cfg.sr_bhvr = ssv_cfg.sr_bhvr;
++	sdio_sr_bhvr = ssv_cfg.sr_bhvr;
++	sh->cfg.force_chip_identity = ssv_cfg.force_chip_identity;
++	strncpy(sh->cfg.firmware_path, ssv_cfg.firmware_path,
++		sizeof(sh->cfg.firmware_path) - 1);
++	strncpy(sh->cfg.flash_bin_path, ssv_cfg.flash_bin_path,
++		sizeof(sh->cfg.flash_bin_path) - 1);
++	strncpy(sh->cfg.mac_address_path, ssv_cfg.mac_address_path,
++		sizeof(sh->cfg.mac_address_path) - 1);
++	strncpy(sh->cfg.mac_output_path, ssv_cfg.mac_output_path,
++		sizeof(sh->cfg.mac_output_path) - 1);
++	sh->cfg.ignore_efuse_mac = ssv_cfg.ignore_efuse_mac;
++	sh->cfg.mac_address_mode = ssv_cfg.mac_address_mode;
++	return 0;
++}
++
++static int ssv6xxx_read_hw_info(struct ssv_softc *sc)
++{
++	struct ssv_hw *sh;
++	sh = kzalloc(sizeof(struct ssv_hw), GFP_KERNEL);
++	if (sh == NULL)
++		return -ENOMEM;
++	memset((void *)sh, 0, sizeof(struct ssv_hw));
++	sc->sh = sh;
++	sh->sc = sc;
++	sh->priv = sc->dev->platform_data;
++	if (ssv6xxx_read_configuration(sh))
++		return -ENOMEM;
++	sh->hci.dev = sc->dev;
++	sh->hci.hci_ops = NULL;
++	sh->hci.hci_rx_cb = ssv6200_rx;
++	sh->hci.rx_cb_args = (void *)sc;
++	sh->hci.hci_tx_cb = ssv6xxx_tx_cb;
++	sh->hci.tx_cb_args = (void *)sc;
++	sh->hci.hci_skb_update_cb = ssv6xxx_tx_rate_update;
++	sh->hci.skb_update_args = (void *)sc;
++	sh->hci.hci_tx_flow_ctrl_cb = ssv6200_tx_flow_control;
++	sh->hci.tx_fctrl_cb_args = (void *)sc;
++	sh->hci.hci_tx_q_empty_cb = ssv6xxx_tx_q_empty_cb;
++	sh->hci.tx_q_empty_args = (void *)sc;
++	sh->hci.if_ops = sh->priv->ops;
++	sh->hci.hci_tx_buf_free_cb = ssv6xxx_txbuf_free_skb;
++	sh->hci.tx_buf_free_args = (void *)sc;
++	return 0;
++}
++
++static int ssv6xxx_init_device(struct ssv_softc *sc, const char *name)
++{
++	struct ieee80211_hw *hw = sc->hw;
++	struct ssv_hw *sh;
++	int error = 0;
++	BUG_ON(!sc->dev->platform_data);
++	if ((error = ssv6xxx_read_hw_info(sc)) != 0) {
++		return error;
++	}
++	sh = sc->sh;
++	if (sh->cfg.hw_caps == 0)
++		return -1;
++	ssv6xxx_hci_register(&sh->hci);
++	efuse_read_all_map(sh);
++	if ((error = ssv6xxx_init_softc(sc)) != 0) {
++		ssv6xxx_deinit_softc(sc);
++		ssv6xxx_hci_deregister();
++		kfree(sh);
++		return error;
++	}
++	if ((error = ssv6xxx_init_hw(sc->sh)) != 0) {
++		ssv6xxx_deinit_hw(sc);
++		ssv6xxx_deinit_softc(sc);
++		ssv6xxx_hci_deregister();
++		kfree(sh);
++		return error;
++	}
++	if ((error = ieee80211_register_hw(hw)) != 0) {
++		dev_err(sc->dev, "Failed to register ieee80211 wireless device. ret=%d.\n", error);
++		ssv6xxx_deinit_hw(sc);
++		ssv6xxx_deinit_softc(sc);
++		ssv6xxx_hci_deregister();
++		kfree(sh);
++		return error;
++	}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_init_debugfs(sc, name);
++#endif
++	return 0;
++}
++
++static void ssv6xxx_deinit_device(struct ssv_softc *sc)
++{
++	dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_deinit_debugfs(sc);
++#endif
++	ssv6xxx_rf_disable(sc->sh);
++	ieee80211_unregister_hw(sc->hw);
++	ssv6xxx_deinit_hw(sc);
++	ssv6xxx_deinit_softc(sc);
++	ssv6xxx_hci_deregister();
++	kfree(sc->sh);
++}
++
++extern struct ieee80211_ops ssv6200_ops;
++int ssv6xxx_dev_probe(struct platform_device *pdev)
++{
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	extern struct ssv_softc *ssv_dbg_sc;
++#endif
++#ifdef CONFIG_SSV_SMARTLINK
++	extern struct ssv_softc *ssv_smartlink_sc;
++#endif
++	struct ssv_softc *softc;
++	struct ieee80211_hw *hw;
++	int ret;
++	if (!pdev->dev.platform_data) {
++		dev_err(&pdev->dev, "no platform data specified!\n");
++		return -EINVAL;
++	}
++	hw = ieee80211_alloc_hw(sizeof(struct ssv_softc), &ssv6200_ops);
++	if (hw == NULL) {
++		dev_err(&pdev->dev, "Could not allocate memory for ieee80211 wireless device\n");
++		return -ENOMEM;
++	}
++	SET_IEEE80211_DEV(hw, &pdev->dev);
++	dev_set_drvdata(&pdev->dev, hw);
++	memset((void *)hw->priv, 0, sizeof(struct ssv_softc));
++	softc = hw->priv;
++	softc->hw = hw;
++	softc->dev = &pdev->dev;
++	//SET_IEEE80211_PERM_ADDR(hw, (const u8 *)&softc->sh->maddr[0]);
++	ret = ssv6xxx_init_device(softc, pdev->name);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to initialize device\n");
++		ieee80211_free_hw(hw);
++		return ret;
++	}
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	ssv_dbg_sc = softc;
++#endif
++#ifdef CONFIG_SSV_SMARTLINK
++	ssv_smartlink_sc = softc;
++#endif
++	wiphy_info(hw->wiphy, "%s\n", "SSV6200 of South Silicon Valley");
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_dev_probe);
++int ssv6xxx_dev_remove(struct platform_device *pdev)
++{
++	struct ieee80211_hw *hw = dev_get_drvdata(&pdev->dev);
++	struct ssv_softc *softc = hw->priv;
++	dev_dbg(&pdev->dev, "ssv6xxx_dev_remove(): pdev=%p, hw=%p\n", pdev, hw);
++	ssv6xxx_deinit_device(softc);
++	dev_dbg(&pdev->dev, "ieee80211_free_hw(): \n");
++	ieee80211_free_hw(hw);
++	dev_info(&pdev->dev, "driver unloaded\n");
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_dev_remove);
++static const struct platform_device_id ssv6xxx_id_table[] = {
++	{
++	 .name = "ssv6200",
++	 .driver_data = 0x00,
++	 },
++	{},
++};
++
++MODULE_DEVICE_TABLE(platform, ssv6xxx_id_table);
++static struct platform_driver ssv6xxx_driver = {
++	.probe = ssv6xxx_dev_probe,
++	.remove = ssv6xxx_dev_remove,
++	.id_table = ssv6xxx_id_table,
++	.driver = {
++		   .name = "SSV WLAN driver",
++		   .owner = THIS_MODULE,
++		   }
++};
++
++int ssv6xxx_init(void)
++{
++	extern void *ssv_dbg_phy_table;
++	extern u32 ssv_dbg_phy_len;
++	extern void *ssv_dbg_rf_table;
++	extern u32 ssv_dbg_rf_len;
++	ssv_dbg_phy_table = (void *)ssv6200_phy_tbl;
++	ssv_dbg_phy_len =
++	    sizeof(ssv6200_phy_tbl) / sizeof(struct ssv6xxx_dev_table);
++	ssv_dbg_rf_table = (void *)ssv6200_rf_tbl;
++	ssv_dbg_rf_len =
++	    sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++	return platform_driver_register(&ssv6xxx_driver);
++}
++
++void ssv6xxx_exit(void)
++{
++	platform_driver_unregister(&ssv6xxx_driver);
++}
++
++EXPORT_SYMBOL(ssv6xxx_init);
++EXPORT_SYMBOL(ssv6xxx_exit);
+diff --git a/drivers/net/wireless/ssv6051/smac/init.h b/drivers/net/wireless/ssv6051/smac/init.h
+new file mode 100644
+index 000000000000..97994d00d4da
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/init.h
+@@ -0,0 +1,23 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _INIT_H_
++#define _INIT_H_
++int ssv6xxx_init_mac(struct ssv_hw *sh);
++int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);
++void ssv6xxx_deinit_mac(struct ssv_softc *sc);
++void ssv6xxx_restart_hw(struct ssv_softc *sc);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/lib.c b/drivers/net/wireless/ssv6051/smac/lib.c
+new file mode 100644
+index 000000000000..ccf0974b0f20
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/lib.c
+@@ -0,0 +1,33 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include "lib.h"
++struct sk_buff *ssv_skb_alloc(s32 len)
++{
++	struct sk_buff *skb;
++	skb = __dev_alloc_skb(len + 128, GFP_KERNEL);
++	if (skb != NULL) {
++		skb_put(skb, 0x20);
++		skb_pull(skb, 0x20);
++	}
++	return skb;
++}
++
++void ssv_skb_free(struct sk_buff *skb)
++{
++	dev_kfree_skb_any(skb);
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/lib.h b/drivers/net/wireless/ssv6051/smac/lib.h
+new file mode 100644
+index 000000000000..266cf7afac95
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/lib.h
+@@ -0,0 +1,23 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _LIB_H_
++#define _LIB_H_
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++struct sk_buff *ssv_skb_alloc(s32 len);
++void ssv_skb_free(struct sk_buff *skb);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/linux_80211.h b/drivers/net/wireless/ssv6051/smac/linux_80211.h
+new file mode 100644
+index 000000000000..e268808e3c93
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/linux_80211.h
+@@ -0,0 +1,24 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _LINUX_80211_H_
++#define _LINUX_80211_H_
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
++#define INDEX_80211_BAND_2GHZ IEEE80211_BAND_2GHZ
++#else
++#define INDEX_80211_BAND_2GHZ NL80211_BAND_2GHZ
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/p2p.c b/drivers/net/wireless/ssv6051/smac/p2p.c
+new file mode 100644
+index 000000000000..60fd8effd6ec
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/p2p.c
+@@ -0,0 +1,305 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include <linux/types.h>
++#include <linux/nl80211.h>
++#include <net/mac80211.h>
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <linux/kthread.h>
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "p2p.h"
++#include "dev.h"
++#include "lib.h"
++#ifdef CONFIG_P2P_NOA
++#define P2P_IE_VENDOR_TYPE 0x506f9a09
++#define P2P_NOA_DETECT_INTERVAL (5 * HZ)
++#ifndef MAC2STR
++#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
++#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
++#define COMPACT_MACSTR "%02x%02x%02x%02x%02x%02x"
++#endif
++void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
++			  struct ssv6xxx_p2p_noa_param *p2p_noa_param);
++static inline u32 WPA_GET_BE32(const u8 * a)
++{
++	return (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3];
++}
++
++static inline u16 WPA_GET_LE16(const u8 * a)
++{
++	return (a[1] << 8) | a[0];
++}
++
++static inline u32 WPA_GET_LE32(const u8 * a)
++{
++	return (a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0];
++}
++
++#define IEEE80211_HDRLEN 24
++enum p2p_attr_id {
++	P2P_ATTR_STATUS = 0,
++	P2P_ATTR_MINOR_REASON_CODE = 1,
++	P2P_ATTR_CAPABILITY = 2,
++	P2P_ATTR_DEVICE_ID = 3,
++	P2P_ATTR_GROUP_OWNER_INTENT = 4,
++	P2P_ATTR_CONFIGURATION_TIMEOUT = 5,
++	P2P_ATTR_LISTEN_CHANNEL = 6,
++	P2P_ATTR_GROUP_BSSID = 7,
++	P2P_ATTR_EXT_LISTEN_TIMING = 8,
++	P2P_ATTR_INTENDED_INTERFACE_ADDR = 9,
++	P2P_ATTR_MANAGEABILITY = 10,
++	P2P_ATTR_CHANNEL_LIST = 11,
++	P2P_ATTR_NOTICE_OF_ABSENCE = 12,
++	P2P_ATTR_DEVICE_INFO = 13,
++	P2P_ATTR_GROUP_INFO = 14,
++	P2P_ATTR_GROUP_ID = 15,
++	P2P_ATTR_INTERFACE = 16,
++	P2P_ATTR_OPERATING_CHANNEL = 17,
++	P2P_ATTR_INVITATION_FLAGS = 18,
++	P2P_ATTR_OOB_GO_NEG_CHANNEL = 19,
++	P2P_ATTR_VENDOR_SPECIFIC = 221
++};
++struct ssv6xxx_p2p_noa_attribute {
++	u8 index;
++	u16 ctwindows_oppps;
++	struct ssv6xxx_p2p_noa_param noa_param;
++};
++extern void _ssv6xxx_hexdump(const char *title, const u8 * buf, size_t len);
++bool p2p_find_noa(const u8 * ies, struct ssv6xxx_p2p_noa_attribute *noa_attr)
++{
++	const u8 *end, *pos, *ie;
++	u32 len;
++	len = ie[1] - 4;
++	pos = ie + 6;
++	end = pos + len;
++	while (pos < end) {
++		u16 attr_len;
++		if (pos + 2 >= end) {
++			return false;
++		}
++		attr_len = WPA_GET_LE16(pos + 1);
++		if (pos + 3 + attr_len > end) {
++			return false;
++		}
++		if (pos[0] != P2P_ATTR_NOTICE_OF_ABSENCE) {
++			pos += 3 + attr_len;
++			continue;
++		}
++		if (attr_len < 15) {
++			printk
++			    ("*********************NOA descriptor does not exist len[%d]\n",
++			     attr_len);
++			break;
++		}
++		if (attr_len > 15)
++			printk("More than one NOA descriptor\n");
++		noa_attr->index = pos[3];
++		noa_attr->ctwindows_oppps = pos[4];
++		noa_attr->noa_param.count = pos[5];
++		noa_attr->noa_param.duration = WPA_GET_LE32(&pos[6]);
++		noa_attr->noa_param.interval = WPA_GET_LE32(&pos[10]);
++		noa_attr->noa_param.start_time = WPA_GET_LE32(&pos[14]);
++		return true;
++	}
++	return false;
++}
++
++bool p2p_get_attribute_noa(const u8 * ies, u32 oui_type,
++			   struct ssv6xxx_p2p_noa_attribute *noa_attr)
++{
++	const u8 *end, *pos, *ie;
++	u32 len;
++	pos = ies;
++	end = ies + ies_len;
++	ie = NULL;
++	while (pos + 1 < end) {
++		if (pos + 2 + pos[1] > end)
++			return false;
++		if (pos[0] == WLAN_EID_VENDOR_SPECIFIC && pos[1] >= 4 &&
++		    WPA_GET_BE32(&pos[2]) == oui_type) {
++			ie = pos;
++			if (p2p_find_noa(ie, 0, noa_attr) == true)
++				return true;
++		}
++		pos += 2 + pos[1];
++	}
++	return false;
++}
++
++void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct cfg_host_event *host_event;
++	struct ssv62xx_noa_evt *noa_evt;
++	host_event = (struct cfg_host_event *)skb->data;
++	noa_evt = (struct ssv62xx_noa_evt *)&host_event->dat[0];
++	switch (noa_evt->evt_id) {
++	case SSV6XXX_NOA_START:
++		sc->p2p_noa.active_noa_vif |= (1 << noa_evt->vif);
++		printk("SSV6XXX_NOA_START===>[%08x]\n",
++		       sc->p2p_noa.active_noa_vif);
++		break;
++	case SSV6XXX_NOA_STOP:
++		sc->p2p_noa.active_noa_vif &= ~(1 << noa_evt->vif);
++		printk("SSV6XXX_NOA_STOP===>[%08x]\n",
++		       sc->p2p_noa.active_noa_vif);
++		break;
++	default:
++		printk("--------->NOA wrong command<---------\n");
++		break;
++	}
++}
++
++void ssv6xxx_noa_reset(struct ssv_softc *sc)
++{
++	unsigned long flags;
++	printk("Reset NOA param...\n");
++	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
++	memset(&sc->p2p_noa.noa_detect, 0,
++	       sizeof(struct ssv_p2p_noa_detect) * SSV_NUM_VIF);
++	sc->p2p_noa.active_noa_vif = 0;
++	sc->p2p_noa.monitor_noa_vif = 0;
++	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
++}
++
++void ssv6xxx_noa_host_stop_noa(struct ssv_softc *sc, u8 vif_id)
++{
++	struct ssv6xxx_p2p_noa_attribute noa_attr;
++	if (sc->p2p_noa.noa_detect[vif_id].p2p_noa_index >= 0) {
++		sc->p2p_noa.noa_detect[vif_id].p2p_noa_index = -1;
++		sc->p2p_noa.active_noa_vif &= ~(1 << vif_id);
++		memset(&sc->p2p_noa.noa_detect[vif_id].noa_param_cmd, 0,
++		       sizeof(struct ssv6xxx_p2p_noa_param));
++		printk("->remove NOA operating vif[%d]\n", vif_id);
++		noa_attr.noa_param.enable = 0;
++		noa_attr.noa_param.vif_id = vif_id;
++		ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
++	}
++}
++
++void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
++			u32 len)
++{
++	int i;
++	unsigned long flags;
++	struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
++	struct ssv6xxx_p2p_noa_attribute noa_attr;
++	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
++	if (sc->p2p_noa.monitor_noa_vif == 0)
++		goto out;
++	for (i = 0; i < SSV_NUM_VIF; i++) {
++		if (sc->p2p_noa.noa_detect[i].noa_addr == NULL)
++			continue;
++		if (memcmp(mgmt->bssid, sc->p2p_noa.noa_detect[i].noa_addr, 6)
++		    != 0)
++			continue;
++		if (sc->p2p_noa.active_noa_vif &&
++		    ((sc->p2p_noa.active_noa_vif & 1 << i) == 0))
++			continue;
++		sc->p2p_noa.noa_detect[i].last_rx = jiffies;
++		if (p2p_get_attribute_noa((const u8 *)mgmt->u.beacon.variable,
++					  len - (IEEE80211_HDRLEN +
++						 sizeof(mgmt->u.beacon)),
++					  P2P_IE_VENDOR_TYPE,
++					  &noa_attr) == false) {
++			continue;
++		}
++		if (sc->p2p_noa.noa_detect[i].p2p_noa_index == noa_attr.index) {
++			goto out;
++		}
++		printk(MACSTR "->set NOA element\n", MAC2STR(mgmt->bssid));
++		sc->p2p_noa.active_noa_vif |= (1 << i);
++		sc->p2p_noa.noa_detect[i].p2p_noa_index = noa_attr.index;
++		memcpy(&sc->p2p_noa.noa_detect[i].noa_param_cmd,
++		       &noa_attr.noa_param,
++		       sizeof(struct ssv6xxx_p2p_noa_param));
++		noa_attr.noa_param.enable = 1;
++		noa_attr.noa_param.vif_id = i;
++		memcpy(noa_attr.noa_param.addr, hdr->addr2, 6);
++		ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
++	}
++ out:
++	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
++}
++
++void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
++				enum ssv6xxx_noa_conf conf, u8 vif_idx)
++{
++	unsigned long flags;
++	if (sc->vif_info[vif_idx].vif->type != NL80211_IFTYPE_STATION ||
++	    sc->vif_info[vif_idx].vif->p2p != true)
++		return;
++	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
++	printk("====>[NOA]ssv6xxx_noa_hdl_bss_change conf[%d] vif_idx[%d]\n",
++	       conf, vif_idx);
++	switch (conf) {
++	case MONITOR_NOA_CONF_ADD:
++		memset(&sc->p2p_noa.noa_detect[vif_idx], 0,
++		       sizeof(struct ssv_p2p_noa_detect));
++		sc->p2p_noa.noa_detect[vif_idx].noa_addr =
++		    sc->vif_info[vif_idx].vif->bss_conf.bssid;
++		sc->p2p_noa.noa_detect[vif_idx].p2p_noa_index = -1;
++		sc->p2p_noa.noa_detect[vif_idx].last_rx = jiffies;
++		sc->p2p_noa.monitor_noa_vif |= 1 << vif_idx;
++		break;
++	case MONITOR_NOA_CONF_REMOVE:
++		sc->p2p_noa.monitor_noa_vif &= ~(1 << vif_idx);
++		sc->p2p_noa.noa_detect[vif_idx].noa_addr = NULL;
++		ssv6xxx_noa_host_stop_noa(sc, vif_idx);
++		break;
++	default:
++		break;
++	}
++	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
++}
++
++void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
++			  struct ssv6xxx_p2p_noa_param *p2p_noa_param)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int retry_cnt = 5;
++	skb =
++	    ssv_skb_alloc(HOST_CMD_HDR_LEN +
++			  sizeof(struct ssv6xxx_p2p_noa_param));
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, p2p_noa_param,
++	       sizeof(struct ssv6xxx_p2p_noa_param));
++	printk
++	    ("Noa cmd NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]vif[%d]\n\n",
++	     p2p_noa_param->enable, p2p_noa_param->interval,
++	     p2p_noa_param->duration, p2p_noa_param->start_time,
++	     p2p_noa_param->count, p2p_noa_param->addr[0],
++	     p2p_noa_param->addr[1], p2p_noa_param->addr[2],
++	     p2p_noa_param->addr[3], p2p_noa_param->addr[4],
++	     p2p_noa_param->addr[5], p2p_noa_param->vif_id);
++	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
++		printk(KERN_INFO "NOA cmd retry=%d!!\n", retry_cnt);
++		retry_cnt--;
++	}
++	ssv_skb_free(skb);
++}
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/p2p.h b/drivers/net/wireless/ssv6051/smac/p2p.h
+new file mode 100644
+index 000000000000..a5bb99c61bb0
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/p2p.h
+@@ -0,0 +1,58 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _P2P_H_
++#define _P2P_H_
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "drv_comm.h"
++#ifdef CONFIG_P2P_NOA
++#define P2P_MAX_NOA_INTERFACE 1
++struct ssv_p2p_noa_detect {
++	const u8 *noa_addr;
++	s16 p2p_noa_index;
++	unsigned long last_rx;
++	struct ssv6xxx_p2p_noa_param noa_param_cmd;
++};
++struct ssv_p2p_noa {
++	spinlock_t p2p_config_lock;
++	struct ssv_p2p_noa_detect noa_detect[SSV_NUM_VIF];
++	u8 active_noa_vif;
++	u8 monitor_noa_vif;
++};
++enum ssv_cmd_state {
++	SSC_CMD_STATE_IDLE,
++	SSC_CMD_STATE_WAIT_RSP,
++};
++struct ssv_cmd_Info {
++	struct sk_buff_head cmd_que;
++	struct sk_buff_head evt_que;
++	enum ssv_cmd_state state;
++};
++enum ssv6xxx_noa_conf {
++	MONITOR_NOA_CONF_ADD,
++	MONITOR_NOA_CONF_REMOVE,
++};
++struct ssv_softc;
++void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
++void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
++				enum ssv6xxx_noa_conf conf, u8 vif_idx);
++void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
++void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
++			u32 len);
++void ssv6xxx_noa_reset(struct ssv_softc *sc);
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/sar.c b/drivers/net/wireless/ssv6051/smac/sar.c
+new file mode 100644
+index 000000000000..44a47a5c7a0f
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/sar.c
+@@ -0,0 +1,208 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200_reg.h>
++#include <ssv6200_aux.h>
++#include <linux/fs.h>
++#include "dev.h"
++#include "sar.h"
++
++WIFI_FLASH_CCFG flash_cfg = {
++	//16bytes
++	0x6051, 0x3009, 0x20170519, 0x1, 0x0, 0x0,
++	{			//16bytes
++	 {0x47c000, 0x47c000, 0x47c000, 0x9, 0x1d, 0x0},
++	 //16bytes
++	 {0x79807980, 0x79807980, 0x79807980, 0x9, 0x1d, 0x0}
++	 }
++};
++
++WIFI_FLASH_CCFG *pflash_cfg;
++
++struct t_sar_info sar_info[] = {
++	{SAR_LVL_INVALID, 0x0047c000, NULL},
++	{SAR_LVL_INVALID, 0x79807980, NULL}
++};
++
++int sar_info_size = sizeof(sar_info) / sizeof(sar_info[0]);
++
++static u8 get_sar_lvl(u32 sar)
++{
++	static u32 prev_sar = 0;
++	int i;
++	u8 changed = 0x0;
++
++	if (sar == prev_sar)
++		return changed;
++
++	pr_debug("[thermal_sar] %d\n", (int)sar);
++
++	for (i = 0; i < sar_info_size; i++) {
++		if (sar_info[i].lvl == SAR_LVL_INVALID) {	//if driver loaded under LT/HT env, it would cause wrong settings at this time.
++			sar_info[i].lvl = SAR_LVL_RT;
++			sar_info[i].value = sar_info[i].p->rt;
++			changed |= BIT(i);
++		} else if (sar_info[i].lvl == SAR_LVL_RT) {
++			if (sar < prev_sar) {
++				if (sar <= (u32) (sar_info[i].p->lt_ts - 2)) {	//we need check if (g_tt_lt - 1) < SAR_MIN
++					sar_info[i].lvl = SAR_LVL_LT;
++					sar_info[i].value = sar_info[i].p->lt;
++					changed |= BIT(i);
++				}
++			} else if (sar > prev_sar) {
++				if (sar >= (u32) (sar_info[i].p->ht_ts + 2)) {	//we need check if (g_tt_lt + 1) > SAR_MAX
++					sar_info[i].lvl = SAR_LVL_HT;
++					sar_info[i].value = sar_info[i].p->ht;
++					changed |= BIT(i);
++				}
++			}
++		} else if (sar_info[i].lvl == SAR_LVL_LT) {
++			if (sar >= (u32) (sar_info[i].p->lt_ts + 2)) {
++				sar_info[i].lvl = SAR_LVL_RT;
++				sar_info[i].value = sar_info[i].p->rt;
++				changed |= BIT(i);
++			}
++		} else if (sar_info[i].lvl == SAR_LVL_HT) {
++			if (sar <= (u32) (sar_info[i].p->ht_ts - 2)) {
++				sar_info[i].lvl = SAR_LVL_RT;
++				sar_info[i].value = sar_info[i].p->rt;
++				changed |= BIT(i);
++			}
++		}
++	}
++	if (changed) {
++		pr_debug("changed: 0x%x\n", changed);
++	}
++	prev_sar = sar;
++	return changed;
++}
++
++void sar_monitor(u32 curr_sar, struct ssv_softc *sc)
++{
++	//static u32 prev_sar_lvl = SAR_LVL_INVALID; //sar = 0, temparature < -25C
++	u8 changed;
++	changed = get_sar_lvl(curr_sar);
++
++	if (changed & BIT(SAR_TXGAIN_INDEX)) {
++		dev_dbg(sc->dev, "TXGAIN: 0x%08x\n", sar_info[SAR_TXGAIN_INDEX].value);
++		SMAC_REG_WRITE(sc->sh, ADR_TX_GAIN_FACTOR,
++			       sar_info[SAR_TXGAIN_INDEX].value);
++	}
++	if (changed & BIT(SAR_XTAL_INDEX)) {
++		dev_dbg(sc->dev, "XTAL: 0x%08x\n", sar_info[SAR_XTAL_INDEX].value);
++		SMAC_REG_WRITE(sc->sh, ADR_SYN_KVCO_XO_FINE_TUNE_CBANK,
++			       sar_info[SAR_XTAL_INDEX].value);
++	}
++}
++
++/*
++    SET_RG_SARADC_THERMAL(1);     //ce010030[26]
++    SET_RG_EN_SARADC(1);          //ce010030[30]
++    while(!GET_SAR_ADC_FSM_RDY);  //ce010094[23]
++    sar_code = GET_RG_SARADC_BIT; //ce010094[21:16]
++    SET_RG_SARADC_THERMAL(0);
++    SET_RG_EN_SARADC(0);
++*/
++void thermal_monitor(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, thermal_monitor_work.work);
++	u32 curr_sar;
++
++	u32 temp;
++	if (sc->ps_status == PWRSV_PREPARE) {
++		dev_dbg(sc->dev, "sar PWRSV_PREPARE\n");
++		return;
++	}
++
++	mutex_lock(&sc->mutex);
++	SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_1, &temp);
++	if (temp == RX_11B_CCA_IN_SCAN) {
++		dev_dbg(sc->dev, "in scan\n");
++		mutex_unlock(&sc->mutex);
++		queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
++				   THERMAL_MONITOR_TIME);
++		return;
++	}
++	SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
++	//printk("ori %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
++			  (1 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (1 << RG_EN_SARADC_SFT),
++			  RG_EN_SARADC_MSK);
++
++	do {
++		msleep(1);
++		SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1, &temp);
++	} while (((temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT) != 1);
++	//printk("SAR_ADC_FSM_RDY_STAT %d\n", (temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT);
++	curr_sar = (temp & RG_SARADC_BIT_MSK) >> RG_SARADC_BIT_SFT;
++	SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
++
++	//printk("new %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
++
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
++			  (0 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (0 << RG_EN_SARADC_SFT),
++			  RG_EN_SARADC_MSK);
++	sar_monitor(curr_sar, sc);
++
++	mutex_unlock(&sc->mutex);
++
++	queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
++			   THERMAL_MONITOR_TIME);
++}
++
++int get_flash_info(struct ssv_softc *sc)
++{
++	struct file *fp = (struct file *)NULL;
++	int i, ret;
++
++	pflash_cfg = &flash_cfg;
++
++	if (sc->sh->cfg.flash_bin_path[0] != 0x00) {
++		fp = filp_open(sc->sh->cfg.flash_bin_path, O_RDONLY, 0);
++		if (IS_ERR(fp) || fp == NULL) {
++			fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
++		}
++	} else {
++		fp = filp_open(DEFAULT_CFG_BIN_NAME, O_RDONLY, 0);
++		if (IS_ERR(fp) || fp == NULL) {
++			fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
++		}
++	}
++	if (IS_ERR(fp) || fp == NULL) {
++		dev_info(sc->dev, "flash_file %s not found, disable sar\n",
++		       DEFAULT_CFG_BIN_NAME);
++		//WARN_ON(1);
++		ret = 0;
++		return ret;
++	}
++
++	fp->f_op->read(fp, (char *)pflash_cfg, sizeof(flash_cfg), &fp->f_pos);
++
++	filp_close(fp, NULL);
++	ret = 1;
++
++	for (i = 0; i < sar_info_size; i++) {
++		sar_info[i].p = &flash_cfg.sar_rlh[i];
++		dev_dbg(sc->dev, "rt = %x, lt = %x, ht = %x\n", sar_info[i].p->rt,
++		       sar_info[i].p->lt, sar_info[i].p->ht);
++		dev_dbg(sc->dev, "lt_ts = %x, ht_ts = %x\n", sar_info[i].p->lt_ts,
++		       sar_info[i].p->ht_ts);
++	}
++	return ret;
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/sar.h b/drivers/net/wireless/ssv6051/smac/sar.h
+new file mode 100644
+index 000000000000..291d58f236eb
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/sar.h
+@@ -0,0 +1,63 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _CFG_H_
++#define _CFG_H_
++#include <linux/kthread.h>
++
++#define SAR_XTAL_INDEX     (0)
++#define SAR_TXGAIN_INDEX    (1)
++#define THERMAL_MONITOR_TIME (10 * HZ)
++#define DEFAULT_CFG_BIN_NAME "/lib/firmware/ssv6051_sar.bin"
++#define SEC_CFG_BIN_NAME "/lib/firmware/ssv6xxx_sar.bin"
++enum {
++	SAR_LVL_LT,
++	SAR_LVL_RT,
++	SAR_LVL_HT,
++	SAR_LVL_INVALID
++};
++
++struct flash_thermal_info {
++	u32 rt;
++	u32 lt;
++	u32 ht;
++	u8 lt_ts;
++	u8 ht_ts;
++	u16 reserve;
++};
++typedef struct t_WIFI_FLASH_CCFG {
++	//16bytes
++	u16 chip_id;
++	u16 sid;
++	u32 date;
++	u16 version;
++	u16 reserve_1;
++	u32 reserve_2;
++	//16bytes
++	struct flash_thermal_info sar_rlh[2];
++} WIFI_FLASH_CCFG;
++
++struct t_sar_info {
++	u32 lvl;
++	u32 value;
++	struct flash_thermal_info *p;
++};
++
++void thermal_monitor(struct work_struct *work);
++int get_flash_info(struct ssv_softc *sc);
++void flash_hexdump(void);
++
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/sec.h b/drivers/net/wireless/ssv6051/smac/sec.h
+new file mode 100644
+index 000000000000..04a0f47c8ce2
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/sec.h
+@@ -0,0 +1,52 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef SEC_H
++#define SEC_H
++#include <linux/types.h>
++#include <linux/ieee80211.h>
++#include <net/mac80211.h>
++#define CCMP_TK_LEN 16
++#define TKIP_KEY_LEN 32
++#define WEP_KEY_LEN 13
++struct ssv_crypto_ops {
++	const char *name;
++	struct list_head list;
++	void *(*init)(int keyidx);
++	void (*deinit)(void *priv);
++	int (*encrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
++	int (*decrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
++	int (*encrypt_msdu)(struct sk_buff * skb, int hdr_len, void *priv);
++	int (*decrypt_msdu)(struct sk_buff * skb, int keyidx, int hdr_len,
++			    void *priv);
++	int (*set_tx_pn)(u8 * seq, void *priv);
++	int (*set_key)(void *key, int len, u8 * seq, void *priv);
++	int (*get_key)(void *key, int len, u8 * seq, void *priv);
++	char *(*print_stats)(char *p, void *priv);
++	unsigned long (*get_flags)(void *priv);
++	unsigned long (*set_flags)(unsigned long flags, void *priv);
++	int extra_mpdu_prefix_len, extra_mpdu_postfix_len;
++	int extra_msdu_prefix_len, extra_msdu_postfix_len;
++};
++struct ssv_crypto_data {
++	struct ssv_crypto_ops *ops;
++	void *priv;
++	rwlock_t lock;
++};
++struct ssv_crypto_ops *get_crypto_ccmp_ops(void);
++struct ssv_crypto_ops *get_crypto_tkip_ops(void);
++struct ssv_crypto_ops *get_crypto_wep_ops(void);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/smartlink.c b/drivers/net/wireless/ssv6051/smac/smartlink.c
+new file mode 100644
+index 000000000000..69e8d5118e09
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/smartlink.c
+@@ -0,0 +1,340 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <net/sock.h>
++#include <linux/socket.h>
++#include <linux/net.h>
++#include <asm/types.h>
++#include <linux/netlink.h>
++#include <linux/skbuff.h>
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "lib.h"
++#include "dev.h"
++#define NETLINK_SMARTLINK (31)
++#define MAX_PAYLOAD (2048)
++static struct sock *nl_sk = NULL;
++struct ssv_softc *ssv_smartlink_sc = NULL;
++EXPORT_SYMBOL(ssv_smartlink_sc);
++u32 ssv_smartlink_status = 0;
++static int _ksmartlink_start_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				       u32 * pOutBufLen)
++{
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	ssv_smartlink_status = 1;
++	*pOutBufLen = 0;
++	return 0;
++}
++
++int ksmartlink_smartlink_started(void)
++{
++	return ssv_smartlink_status;
++}
++
++EXPORT_SYMBOL(ksmartlink_smartlink_started);
++static int _ksmartlink_stop_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				      u32 * pOutBufLen)
++{
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	ssv_smartlink_status = 0;
++	*pOutBufLen = 0;
++	return 0;
++}
++
++static int _ksmartlink_set_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int ch = (int)(*pInBuf);
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_set_channel(sc, ch);
++	mutex_unlock(&sc->mutex);
++	*pOutBufLen = 0;
++ out:
++	return ret;
++}
++
++static int _ksmartlink_get_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int ch = 0;
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_get_channel(sc, &ch);
++	mutex_unlock(&sc->mutex);
++	*pOutBuf = ch;
++	*pOutBufLen = 1;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
++#endif
++ out:
++	return ret;
++}
++
++static int _ksmartlink_set_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int accept = (int)(*pInBuf);
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_set_promisc(sc, accept);
++	mutex_unlock(&sc->mutex);
++	*pOutBufLen = 0;
++ out:
++	return ret;
++}
++
++static int _ksmartlink_get_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int accept = (int)(*pInBuf);
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_get_promisc(sc, &accept);
++	mutex_unlock(&sc->mutex);
++	*pOutBuf = accept;
++	*pOutBufLen = 1;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
++#endif
++ out:
++	return ret;
++}
++
++#define SMARTLINK_CMD_FIXED_LEN (10)
++#define SMARTLINK_CMD_FIXED_TOT_LEN (SMARTLINK_CMD_FIXED_LEN+1)
++#define SMARTLINK_RES_FIXED_LEN (SMARTLINK_CMD_FIXED_LEN)
++#define SMARTLINK_RES_FIXED_TOT_LEN (SMARTLINK_RES_FIXED_LEN+2)
++struct ksmartlink_cmd {
++	char *cmd;
++	int (*process_func)(u8 *, u32, u8 *, u32 *);
++};
++static struct ksmartlink_cmd _ksmartlink_cmd_table[] = {
++	{"startairki", _ksmartlink_start_smartlink},
++	{"stopairkis", _ksmartlink_stop_smartlink},
++	{"setchannel", _ksmartlink_set_channel},
++	{"getchannel", _ksmartlink_get_channel},
++	{"setpromisc", _ksmartlink_set_promisc},
++	{"getpromisc", _ksmartlink_get_promisc},
++};
++
++static u32 _ksmartlink_cmd_table_size =
++    sizeof(_ksmartlink_cmd_table) / sizeof(struct ksmartlink_cmd);
++#ifdef KSMARTLINK_DEBUG
++static void _ksmartlink_hex_dump(u8 * pInBuf, u32 inBufLen)
++{
++	u32 i = 0;
++	printk(KERN_INFO "\nKernel Hex Dump(len=%d):\n", inBufLen);
++	printk(KERN_INFO ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
++	for (i = 0; i < inBufLen; i++) {
++		if ((i) && ((i & 0xf) == 0)) {
++			printk("\n");
++		}
++		printk("%02x ", pInBuf[i]);
++	}
++	printk(KERN_INFO "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
++}
++#endif
++static int _ksmartlink_process_msg(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = 0;
++	u32 i = 0;
++	struct ksmartlink_cmd *pCmd;
++	if (!pInBuf || !pOutBuf || !pOutBufLen) {
++		printk(KERN_ERR "NULL pointer\n");
++		return -1;
++	}
++	for (i = 0; i < _ksmartlink_cmd_table_size; i++) {
++		if (!strncmp
++		    (_ksmartlink_cmd_table[i].cmd, pInBuf,
++		     SMARTLINK_CMD_FIXED_LEN)) {
++			break;
++		}
++	}
++	if (i < _ksmartlink_cmd_table_size) {
++		pCmd = &_ksmartlink_cmd_table[i];
++		if (!pCmd->process_func) {
++			printk(KERN_ERR "CMD %s has NULL process_func\n",
++			       pCmd->cmd);
++			return -3;
++		}
++		ret =
++		    pCmd->process_func(pInBuf + SMARTLINK_CMD_FIXED_LEN,
++				       inBufLen, pOutBuf, pOutBufLen);
++#ifdef CONFIG_SSV_NETLINK_RESPONSE
++		if (ret < 0) {
++			*pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
++		} else {
++			if (*pOutBufLen > 0) {
++				pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
++				pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = *pOutBuf;
++			} else {
++				pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
++				pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = 0;
++			}
++			*pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
++		}
++		memcpy(pOutBuf, pCmd->cmd, SMARTLINK_RES_FIXED_LEN);
++#else
++		(void)pOutBuf;
++		(void)pOutBufLen;
++#endif
++		return 0;
++	} else {
++		printk(KERN_INFO "Unknow CMD or Packet?\n");
++	}
++	return 0;
++}
++static u8 gkBuf[MAX_PAYLOAD] = { 0 };
++
++static int ssv_usr_pid = 0;
++void smartlink_nl_recv_msg(struct sk_buff *skb)
++{
++	struct nlmsghdr *nlh;
++#ifdef CONFIG_SSV_NETLINK_RESPONSE
++	struct sk_buff *skb_out;
++#endif
++	int ret = 0;
++	u8 *pInBuf = NULL;
++	u32 inBufLen = 0;
++	u32 outBufLen = 0;
++	nlh = (struct nlmsghdr *)skb->data;
++	ssv_usr_pid = nlh->nlmsg_pid;
++	pInBuf = (u8 *) nlmsg_data(nlh);
++	inBufLen = nlmsg_len(nlh);
++#ifdef KSMARTLINK_DEBUG
++	_ksmartlink_hex_dump(pInBuf, inBufLen);
++#endif
++	outBufLen = 0;
++	memset(gkBuf, 0, MAX_PAYLOAD);
++	ret = _ksmartlink_process_msg(pInBuf, inBufLen, gkBuf, &outBufLen);
++#ifdef CONFIG_SSV_NETLINK_RESPONSE
++	if (outBufLen == 0) {
++		memcpy(gkBuf, "Nothing", 8);
++		outBufLen = strlen(gkBuf);
++	}
++	skb_out = nlmsg_new(outBufLen, 0);
++	if (!skb_out) {
++		printk(KERN_ERR "Failed to allocate new skb\n");
++		return;
++	}
++	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
++	NETLINK_CB(skb_out).dst_group = 0;
++	memcpy(nlmsg_data(nlh), gkBuf, outBufLen);
++	ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
++	if (ret < 0) {
++		printk(KERN_ERR "Error while sending bak to user\n");
++	}
++#endif
++	return;
++}
++
++void smartlink_nl_send_msg(struct sk_buff *skb)
++{
++	struct nlmsghdr *nlh;
++	struct sk_buff *skb_out;
++	int ret = 0;
++	u8 *pOutBuf = skb->data;
++	u32 outBufLen = skb->len;
++#ifdef KSMARTLINK_DEBUG
++#endif
++	skb_out = nlmsg_new(outBufLen, 0);
++	if (!skb_out) {
++		printk(KERN_ERR "Allocate new skb failed!\n");
++		return;
++	}
++	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
++	NETLINK_CB(skb_out).dst_group = 0;
++	memcpy(nlmsg_data(nlh), pOutBuf, outBufLen);
++	ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
++	if (ret < 0) {
++		printk(KERN_ERR "nlmsg_unicast failed!\n");
++	}
++	kfree_skb(skb);
++	return;
++}
++
++EXPORT_SYMBOL(smartlink_nl_send_msg);
++int ksmartlink_init(void)
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)
++	nl_sk = netlink_kernel_create(&init_net,
++				      NETLINK_SMARTLINK,
++				      0,
++				      smartlink_nl_recv_msg, NULL, THIS_MODULE);
++#else
++	struct netlink_kernel_cfg cfg = {
++		.groups = 0,
++		.input = smartlink_nl_recv_msg,
++	};
++	nl_sk = netlink_kernel_create(&init_net, NETLINK_SMARTLINK, &cfg);
++#endif
++	printk(KERN_INFO "***************SmartLink Init-S**************\n");
++	if (!nl_sk) {
++		printk(KERN_ERR "Error creating socket.\n");
++		return -10;
++	}
++	printk(KERN_INFO "***************SmartLink Init-E**************\n");
++	return 0;
++}
++
++void ksmartlink_exit(void)
++{
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++	if (nl_sk) {
++		netlink_kernel_release(nl_sk);
++		nl_sk = NULL;
++	}
++}
++
++EXPORT_SYMBOL(ksmartlink_init);
++EXPORT_SYMBOL(ksmartlink_exit);
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
+new file mode 100644
+index 000000000000..9be5ea96e7f9
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
+@@ -0,0 +1,223 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ssv6xxx_debugfs.h"
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++#define QUEUE_STATUS_BUF_SIZE (4096)
++static ssize_t queue_status_read(struct file *file,
++				 char __user * user_buf, size_t count,
++				 loff_t * ppos)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)file->private_data;
++	char *status_buf = kzalloc(QUEUE_STATUS_BUF_SIZE, GFP_KERNEL);
++	ssize_t status_size;
++	ssize_t ret;
++	if (!status_buf)
++		return -ENOMEM;
++	status_size = ssv6xxx_tx_queue_status_dump(sc, status_buf,
++						   QUEUE_STATUS_BUF_SIZE);
++	ret = simple_read_from_buffer(user_buf, count, ppos, status_buf,
++				      status_size);
++	kfree(status_buf);
++	return ret;
++}
++
++static int queue_status_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static const struct file_operations queue_status_fops
++    = {.read = queue_status_read,
++	.open = queue_status_open
++};
++#endif
++int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ieee80211_hw *hw = sc->hw;
++	struct dentry *phy_debugfs_dir = hw->wiphy->debugfsdir;
++	struct dentry *drv_debugfs_dir;
++	drv_debugfs_dir = debugfs_create_dir(name, phy_debugfs_dir);
++	if (!drv_debugfs_dir) {
++		dev_err(sc->dev, "Failed to create debugfs.\n");
++		return -ENOMEM;
++	}
++	sc->debugfs_dir = drv_debugfs_dir;
++	sc->sh->hci.hci_ops->hci_init_debugfs(sc->debugfs_dir);
++	debugfs_create_file("queue_status", 00444, drv_debugfs_dir,
++			    sc, &queue_status_fops);
++#endif
++	return 0;
++}
++
++void ssv6xxx_deinit_debugfs(struct ssv_softc *sc)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (!sc->debugfs_dir)
++		return;
++	sc->sh->hci.hci_ops->hci_deinit_debugfs();
++	debugfs_remove_recursive(sc->debugfs_dir);
++	sc->debugfs_dir = NULL;
++#endif
++}
++
++int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
++				  struct ieee80211_vif *vif)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *drv_debugfs_dir = sc->debugfs_dir;
++	struct dentry *vif_debugfs_dir;
++	char vif_addr[18];
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	snprintf(vif_addr, sizeof(vif_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
++		 vif->addr[0], vif->addr[1], vif->addr[2],
++		 vif->addr[3], vif->addr[4], vif->addr[5]);
++	vif_debugfs_dir = debugfs_create_dir(vif_addr, drv_debugfs_dir);
++	if (!vif_debugfs_dir) {
++		dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
++			vif_addr);
++		return -ENOMEM;
++	}
++	sc->debugfs_dir = drv_debugfs_dir;
++	vif_info->debugfs_dir = vif_debugfs_dir;
++#endif
++	return 0;
++}
++
++int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	if ((vif_info->debugfs_dir == NULL) || (sc->debugfs_dir == NULL))
++		return 0;
++	debugfs_remove_recursive(vif_info->debugfs_dir);
++	vif_info->debugfs_dir = NULL;
++#endif
++	return 0;
++}
++
++int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)sta->vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	if ((sc->debugfs_dir == NULL) || (vif_info->debugfs_dir == NULL)
++	    || (sta->debugfs_dir == NULL))
++		return 0;
++	debugfs_remove_recursive(sta->debugfs_dir);
++	sta->debugfs_dir = NULL;
++#endif
++	return 0;
++}
++
++int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)sta->vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	struct dentry *vif_debugfs_dir = vif_info->debugfs_dir;
++	struct dentry *sta_debugfs_dir;
++	char sta_addr[18];
++	if (vif_debugfs_dir == NULL)
++		return 0;
++	snprintf(sta_addr, sizeof(sta_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
++		 sta->sta->addr[0], sta->sta->addr[1], sta->sta->addr[2],
++		 sta->sta->addr[3], sta->sta->addr[4], sta->sta->addr[5]);
++	sta_debugfs_dir = debugfs_create_dir(sta_addr, vif_debugfs_dir);
++	if (!sta_debugfs_dir) {
++		dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
++			sta_addr);
++		return -ENOMEM;
++	}
++	sta->debugfs_dir = sta_debugfs_dir;
++#endif
++	return 0;
++}
++
++#define DEBUGFS_ADD_FILE(name,parent,mode) do { \
++    if (!debugfs_create_file(#name, mode, parent, priv, \
++                 &ssv_dbgfs_##name##_ops)) \
++        goto err; \
++} while (0)
++#define DEBUGFS_ADD_BOOL(name,parent,ptr) do { \
++    struct dentry *__tmp; \
++    __tmp = debugfs_create_bool(#name, S_IWUSR | S_IRUSR, \
++                    parent, ptr); \
++    if (IS_ERR(__tmp) || !__tmp) \
++        goto err; \
++} while (0)
++#define DEBUGFS_ADD_X32(name,parent,ptr) do { \
++    struct dentry *__tmp; \
++    __tmp = debugfs_create_x32(#name, S_IWUSR | S_IRUSR, \
++                   parent, ptr); \
++    if (IS_ERR(__tmp) || !__tmp) \
++        goto err; \
++} while (0)
++#define DEBUGFS_ADD_U32(name,parent,ptr,mode) do { \
++    struct dentry *__tmp; \
++    __tmp = debugfs_create_u32(#name, mode, \
++                   parent, ptr); \
++    if (IS_ERR(__tmp) || !__tmp) \
++        goto err; \
++} while (0)
++#define DEBUGFS_READ_FUNC(name) \
++static ssize_t ssv_dbgfs_##name##_read(struct file *file, \
++                    char __user *user_buf, \
++                    size_t count, loff_t *ppos);
++#define DEBUGFS_WRITE_FUNC(name) \
++static ssize_t ssv_dbgfs_##name##_write(struct file *file, \
++                    const char __user *user_buf, \
++                    size_t count, loff_t *ppos);
++#define DEBUGFS_READ_FILE_OPS(name) \
++    DEBUGFS_READ_FUNC(name); \
++static const struct file_operations ssv_dbgfs_##name##_ops = { \
++    .read = ssv_dbgfs_##name##_read, \
++    .open = ssv_dbgfs_open_file_generic, \
++    .llseek = generic_file_llseek, \
++};
++#define DEBUGFS_WRITE_FILE_OPS(name) \
++    DEBUGFS_WRITE_FUNC(name); \
++static const struct file_operations ssv_dbgfs_##name##_ops = { \
++    .write = ssv_dbgfs_##name##_write, \
++    .open = ssv_dbgfs_open_file_generic, \
++    .llseek = generic_file_llseek, \
++};
++#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
++    DEBUGFS_READ_FUNC(name); \
++    DEBUGFS_WRITE_FUNC(name); \
++static const struct file_operations ssv_dbgfs_##name##_ops = { \
++    .write = ssv_dbgfs_##name##_write, \
++    .read = ssv_dbgfs_##name##_read, \
++    .open = ssv_dbgfs_open_file_generic, \
++    .llseek = generic_file_llseek, \
++};
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
+new file mode 100644
+index 000000000000..39caceadda4a
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __SSV6XXX_DBGFS_H__
++#define __SSV6XXX_DBGFS_H__
++int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name);
++void ssv6xxx_deinit_debugfs(struct ssv_softc *sc);
++int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif);
++int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
++				  struct ieee80211_vif *vif);
++int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
++int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
+new file mode 100644
+index 000000000000..f0135447b1f3
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
+@@ -0,0 +1,1384 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2018 icomm Corporation. All rights reserved.
++ *                                        
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#include "dev.h"
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
++
++#include <linux/kernel.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#include <linux/sched.h>
++#include <linux/etherdevice.h>
++#include <linux/wireless.h>
++#include <linux/ieee80211.h>
++#include <linux/wait.h>
++#include <net/cfg80211.h>
++
++#include <net/rtnetlink.h>
++#include "ssv_cfgvendor.h"
++
++#define wiphy_to_softc(x) (*((struct ssv_softc**)wiphy_priv(x)))
++#define FUNC_NDEV_FMT "%s"
++#define FUNC_NDEV_ARG(ndev) __func__
++
++#define _drv_always_		1
++#define _drv_emerg_			2
++#define _drv_alert_			3
++#define _drv_crit_			4
++#define _drv_err_			5
++#define _drv_warning_		6
++#define _drv_notice_		7
++#define _drv_info_			8
++#define _drv_dump_			9
++#define _drv_debug_			10
++
++struct sk_buff *ssv_cfg80211_vendor_event_alloc(struct wiphy *wiphy, int len,
++						int event_id, gfp_t gfp)
++{
++	struct sk_buff *skb;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
++	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len, event_id, gfp);
++#endif
++	return skb;
++}
++
++#define ssv_cfg80211_vendor_event(skb, gfp) \
++	cfg80211_vendor_event(skb, gfp)
++
++#define ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
++	cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len)
++
++#define ssv_cfg80211_vendor_cmd_reply(skb) \
++	cfg80211_vendor_cmd_reply(skb)
++
++/*
++ * This API is to be used for asynchronous vendor events. This
++ * shouldn't be used in response to a vendor command from its
++ * do_it handler context (instead ssv_cfgvendor_send_cmd_reply should
++ * be used).
++ */
++int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
++				   struct net_device *dev, int event_id,
++				   const void *data, int len)
++{
++	u16 kflags;
++	struct sk_buff *skb;
++
++	kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_event_alloc(wiphy, len, event_id, kflags);
++	if (!skb) {
++		dev_err(&wiphy->dev, "skb alloc failed\n");
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	ssv_cfg80211_vendor_event(skb, kflags);
++
++	return 0;
++}
++
++static int ssv_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
++					struct net_device *dev,
++					const void *data, int len)
++{
++	struct sk_buff *skb;
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
++	if (unlikely(!skb)) {
++		dev_err(&wiphy->dev, "skb alloc failed");
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	return ssv_cfg80211_vendor_cmd_reply(skb);
++}
++
++#define WIFI_FEATURE_INFRA              0x0001	/* Basic infrastructure mode        */
++#define WIFI_FEATURE_INFRA_5G           0x0002	/* Support for 5 GHz Band           */
++#define WIFI_FEATURE_HOTSPOT            0x0004	/* Support for GAS/ANQP             */
++#define WIFI_FEATURE_P2P                0x0008	/* Wifi-Direct                      */
++#define WIFI_FEATURE_SOFT_AP            0x0010	/* Soft AP                          */
++#define WIFI_FEATURE_GSCAN              0x0020	/* Google-Scan APIs                 */
++#define WIFI_FEATURE_NAN                0x0040	/* Neighbor Awareness Networking    */
++#define WIFI_FEATURE_D2D_RTT            0x0080	/* Device-to-device RTT             */
++#define WIFI_FEATURE_D2AP_RTT           0x0100	/* Device-to-AP RTT                 */
++#define WIFI_FEATURE_BATCH_SCAN         0x0200	/* Batched Scan (legacy)            */
++#define WIFI_FEATURE_PNO                0x0400	/* Preferred network offload        */
++#define WIFI_FEATURE_ADDITIONAL_STA     0x0800	/* Support for two STAs             */
++#define WIFI_FEATURE_TDLS               0x1000	/* Tunnel directed link setup       */
++#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000	/* Support for TDLS off channel     */
++#define WIFI_FEATURE_EPR                0x4000	/* Enhanced power reporting         */
++#define WIFI_FEATURE_AP_STA             0x8000	/* Support for AP STA Concurrency   */
++
++#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3
++
++int ssv_dev_get_feature_set(struct net_device *dev)
++{
++	int feature_set = 0;
++
++	feature_set |= WIFI_FEATURE_INFRA;
++
++	feature_set |= WIFI_FEATURE_P2P;
++	feature_set |= WIFI_FEATURE_SOFT_AP;
++
++#if defined(GSCAN_SUPPORT)
++	feature_set |= WIFI_FEATURE_GSCAN;
++#endif
++
++#if defined(RTT_SUPPORT)
++	feature_set |= WIFI_FEATURE_NAN;
++	feature_set |= WIFI_FEATURE_D2D_RTT;
++	feature_set |= WIFI_FEATURE_D2AP_RTT;
++#endif
++
++	return feature_set;
++}
++
++int *ssv_dev_get_feature_set_matrix(struct net_device *dev, int *num)
++{
++	int feature_set_full, mem_needed;
++	int *ret;
++
++	*num = 0;
++	mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;
++	ret =
++	    (int *)kmalloc(mem_needed, in_interrupt()? GFP_ATOMIC : GFP_KERNEL);
++
++	if (!ret) {
++		dev_err(&dev->dev, "failed to allocate %d bytes\n", mem_needed);
++		return ret;
++	}
++
++	feature_set_full = ssv_dev_get_feature_set(dev);
++
++	ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	    (feature_set_full & WIFI_FEATURE_NAN) |
++	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	    (feature_set_full & WIFI_FEATURE_PNO) |
++	    (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
++	    (feature_set_full & WIFI_FEATURE_GSCAN) |
++	    (feature_set_full & WIFI_FEATURE_HOTSPOT) |
++	    (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |
++	    (feature_set_full & WIFI_FEATURE_EPR);
++
++	ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	    /* Not yet verified NAN with P2P */
++	    /* (feature_set_full & WIFI_FEATURE_NAN) | */
++	    (feature_set_full & WIFI_FEATURE_P2P) |
++	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	    (feature_set_full & WIFI_FEATURE_EPR);
++
++	ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	    (feature_set_full & WIFI_FEATURE_NAN) |
++	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	    (feature_set_full & WIFI_FEATURE_TDLS) |
++	    (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |
++	    (feature_set_full & WIFI_FEATURE_EPR);
++	*num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;
++
++	return ret;
++}
++
++#define wdev_to_ndev(wdev) NULL
++
++static int ssv_cfgvendor_get_feature_set(struct wiphy *wiphy,
++					 struct wireless_dev *wdev,
++					 const void *data, int len)
++{
++	int err = 0;
++	int reply;
++
++	reply = ssv_dev_get_feature_set(wdev_to_ndev(wdev));
++
++	err =
++	    ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply,
++					 sizeof(int));
++
++	if (unlikely(err))
++		dev_err(&wiphy->dev, "vendor Command reply failed, ret:%d\n", err);
++
++	return err;
++}
++
++static int ssv_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
++						struct wireless_dev *wdev,
++						const void *data, int len)
++{
++	int err = 0;
++	struct sk_buff *skb;
++	int *reply;
++	int num, mem_needed, i;
++
++	reply = ssv_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num);
++
++	if (!reply) {
++		dev_err(&wiphy->dev, "could not get feature list matrix\n");
++		err = -EINVAL;
++		return err;
++	}
++
++	mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +
++	    ATTRIBUTE_U32_LEN;
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		dev_err(&wiphy->dev, "skb alloc failed\n");
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);
++	for (i = 0; i < num; i++) {
++		nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);
++	}
++
++	err = ssv_cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err))
++		dev_err(&wiphy->dev, "vendor Command reply failed, ret=%d\n", err);
++ exit:
++	kfree((void *)reply);
++	return err;
++}
++
++#if defined(GSCAN_SUPPORT) && 0
++int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++				    struct net_device *dev, void *data, int len,
++				    wl_vendor_event_t event)
++{
++	u16 kflags;
++	const void *ptr;
++	struct sk_buff *skb;
++	int malloc_len, total, iter_cnt_to_send, cnt;
++	gscan_results_cache_t *cache = (gscan_results_cache_t *) data;
++
++	total = len / sizeof(wifi_gscan_result_t);
++	while (total > 0) {
++		malloc_len =
++		    (total * sizeof(wifi_gscan_result_t)) +
++		    VENDOR_DATA_OVERHEAD;
++		if (malloc_len > NLMSG_DEFAULT_SIZE) {
++			malloc_len = NLMSG_DEFAULT_SIZE;
++		}
++		iter_cnt_to_send =
++		    (malloc_len -
++		     VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t);
++		total = total - iter_cnt_to_send;
++
++		kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
++
++		/* Alloc the SKB for vendor_event */
++		skb =
++		    ssv_cfg80211_vendor_event_alloc(wiphy, malloc_len, event,
++						    kflags);
++		if (!skb) {
++			WL_ERR(("skb alloc failed"));
++			return -ENOMEM;
++		}
++
++		while (cache && iter_cnt_to_send) {
++			ptr =
++			    (const void *)&cache->results[cache->tot_consumed];
++
++			if (iter_cnt_to_send <
++			    (cache->tot_count - cache->tot_consumed))
++				cnt = iter_cnt_to_send;
++			else
++				cnt = (cache->tot_count - cache->tot_consumed);
++
++			iter_cnt_to_send -= cnt;
++			cache->tot_consumed += cnt;
++			/* Push the data to the skb */
++			nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
++			if (cache->tot_consumed == cache->tot_count)
++				cache = cache->next;
++
++		}
++
++		ssv_cfg80211_vendor_event(skb, kflags);
++	}
++
++	return 0;
++}
++
++static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
++					       struct wireless_dev *wdev,
++					       const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pno_gscan_capabilities_t *reply = NULL;
++	uint32 reply_len = 0;
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_GET_CAPABILITIES, NULL,
++				      &reply_len);
++	if (!reply) {
++		WL_ERR(("Could not get capabilities\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++					   reply, reply_len);
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++
++	kfree(reply);
++	return err;
++}
++
++static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
++					       struct wireless_dev *wdev,
++					       const void *data, int len)
++{
++	int err = 0, type, band;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	uint16 *reply = NULL;
++	uint32 reply_len = 0, num_channels, mem_needed;
++	struct sk_buff *skb;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_BAND) {
++		band = nla_get_u32(data);
++	} else {
++		return -1;
++	}
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_GET_CHANNEL_LIST, &band,
++				      &reply_len);
++
++	if (!reply) {
++		WL_ERR(("Could not get channel list\n"));
++		err = -EINVAL;
++		return err;
++	}
++	num_channels = reply_len / sizeof(uint32);
++	mem_needed =
++	    reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
++	nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
++
++	err = ssv_cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++ exit:
++	kfree(reply);
++	return err;
++}
++
++static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
++						struct wireless_dev *wdev,
++						const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_results_cache_t *results, *iter;
++	uint32 reply_len, complete = 0, num_results_iter;
++	int32 mem_needed;
++	wifi_gscan_result_t *ptr;
++	uint16 num_scan_ids, num_results;
++	struct sk_buff *skb;
++	struct nlattr *scan_hdr;
++
++	dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
++	dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++	results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++					DHD_PNO_GET_BATCH_RESULTS, NULL,
++					&reply_len);
++
++	if (!results) {
++		WL_ERR(("No results to send %d\n", err));
++		err =
++		    ssv_cfgvendor_send_cmd_reply(wiphy,
++						 bcmcfg_to_prmry_ndev(cfg),
++						 results, 0);
++
++		if (unlikely(err))
++			WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
++							(cfg));
++		return err;
++	}
++	num_scan_ids = reply_len & 0xFFFF;
++	num_results = (reply_len & 0xFFFF0000) >> 16;
++	mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
++	    (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
++	    VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
++
++	if (mem_needed > (int32) NLMSG_DEFAULT_SIZE) {
++		mem_needed = (int32) NLMSG_DEFAULT_SIZE;
++		complete = 0;
++	} else {
++		complete = 1;
++	}
++
++	WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete,
++		  mem_needed, (int)NLMSG_DEFAULT_SIZE));
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
++							(cfg));
++		return -ENOMEM;
++	}
++	iter = results;
++
++	nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete);
++
++	mem_needed =
++	    mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN +
++			  VENDOR_REPLY_OVERHEAD);
++
++	while (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) > 0)) {
++		scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
++		nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
++		num_results_iter =
++		    (mem_needed -
++		     GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t);
++
++		if ((iter->tot_count - iter->tot_consumed) < num_results_iter)
++			num_results_iter = iter->tot_count - iter->tot_consumed;
++
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS,
++			    num_results_iter);
++		if (num_results_iter) {
++			ptr = &iter->results[iter->tot_consumed];
++			iter->tot_consumed += num_results_iter;
++			nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
++				num_results_iter * sizeof(wifi_gscan_result_t),
++				ptr);
++		}
++		nla_nest_end(skb, scan_hdr);
++		mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
++		    (num_results_iter * sizeof(wifi_gscan_result_t));
++		iter = iter->next;
++	}
++
++	dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
++	dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++
++	return ssv_cfg80211_vendor_cmd_reply(skb);
++}
++
++static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy,
++				       struct wireless_dev *wdev,
++				       const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type, tmp = len;
++	int run = 0xFF;
++	int flush = 0;
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
++			run = nla_get_u32(iter);
++		else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
++			flush = nla_get_u32(iter);
++	}
++
++	if (run != 0xFF) {
++		err =
++		    dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run,
++					  flush);
++
++		if (unlikely(err))
++			WL_ERR(("Could not run gscan:%d \n", err));
++		return err;
++	} else {
++		return -1;
++	}
++
++}
++
++static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
++						struct wireless_dev *wdev,
++						const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	bool real_time = FALSE;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
++		real_time = nla_get_u32(data);
++
++		err =
++		    dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev
++							(cfg), real_time);
++
++		if (unlikely(err))
++			WL_ERR(("Could not run gscan:%d \n", err));
++
++	} else {
++		err = -1;
++	}
++
++	return err;
++}
++
++static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy,
++				     struct wireless_dev *wdev,
++				     const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_scan_params_t *scan_param;
++	int j = 0;
++	int type, tmp, tmp1, tmp2, k = 0;
++	const struct nlattr *iter, *iter1, *iter2;
++	struct dhd_pno_gscan_channel_bucket *ch_bucket;
++
++	scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
++	if (!scan_param) {
++		WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
++		err = -EINVAL;
++		return err;
++
++	}
++
++	scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		if (j >= GSCAN_MAX_CH_BUCKETS)
++			break;
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_BASE_PERIOD:
++			scan_param->scan_fr = nla_get_u32(iter) / 1000;
++			break;
++		case GSCAN_ATTRIBUTE_NUM_BUCKETS:
++			scan_param->nchannel_buckets = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_CH_BUCKET_1:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_2:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_3:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_4:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_5:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_6:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_7:
++			nla_for_each_nested(iter1, iter, tmp1) {
++				type = nla_type(iter1);
++				ch_bucket = scan_param->channel_bucket;
++
++				switch (type) {
++				case GSCAN_ATTRIBUTE_BUCKET_ID:
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
++					ch_bucket[j].bucket_freq_multiple =
++					    nla_get_u32(iter1) / 1000;
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
++					ch_bucket[j].num_channels =
++					    nla_get_u32(iter1);
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
++					nla_for_each_nested(iter2, iter1, tmp2) {
++						if (k >=
++						    PFN_SWC_RSSI_WINDOW_MAX)
++							break;
++						ch_bucket[j].chan_list[k] =
++						    nla_get_u32(iter2);
++						k++;
++					}
++					k = 0;
++					break;
++				case GSCAN_ATTRIBUTE_BUCKETS_BAND:
++					ch_bucket[j].band = (uint16)
++					    nla_get_u32(iter1);
++					break;
++				case GSCAN_ATTRIBUTE_REPORT_EVENTS:
++					ch_bucket[j].report_flag = (uint8)
++					    nla_get_u32(iter1);
++					break;
++				}
++			}
++			j++;
++			break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {
++		WL_ERR(("Could not set GSCAN scan cfg\n"));
++		err = -EINVAL;
++	}
++
++	kfree(scan_param);
++	return err;
++
++}
++
++static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
++				    struct wireless_dev *wdev, const void *data,
++				    int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_hotlist_scan_params_t *hotlist_params;
++	int tmp, tmp1, tmp2, type, j = 0, dummy;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0;
++	struct bssid_t *pbssid;
++
++	hotlist_params =
++	    (gscan_hotlist_scan_params_t *) kzalloc(len, GFP_KERNEL);
++	if (!hotlist_params) {
++		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
++		return -1;
++	}
++
++	hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++		case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
++			pbssid = hotlist_params->bssid;
++			nla_for_each_nested(outer, iter, tmp) {
++				nla_for_each_nested(inner, outer, tmp1) {
++					type = nla_type(inner);
++
++					switch (type) {
++					case GSCAN_ATTRIBUTE_BSSID:
++						memcpy(&(pbssid[j].macaddr),
++						       nla_data(inner),
++						       ETHER_ADDR_LEN);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_LOW:
++						pbssid[j].
++						    rssi_reporting_threshold =
++						    (int8) nla_get_u8(inner);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_HIGH:
++						dummy =
++						    (int8) nla_get_u8(inner);
++						break;
++					}
++				}
++				j++;
++			}
++			hotlist_params->nbssid = j;
++			break;
++		case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
++			flush = nla_get_u8(iter);
++			break;
++		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++			hotlist_params->lost_ap_window = nla_get_u32(iter);
++			break;
++		}
++
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_GEOFENCE_SCAN_CFG_ID,
++				      hotlist_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN HOTLIST cfg\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++ exit:
++	kfree(hotlist_params);
++	return err;
++}
++
++static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
++					   struct wireless_dev *wdev,
++					   const void *data, int len)
++{
++	int err = 0, tmp, type;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_batch_params_t batch_param;
++	const struct nlattr *iter;
++
++	batch_param.mscan = batch_param.bestn = 0;
++	batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
++			batch_param.bestn = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
++			batch_param.mscan = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
++			batch_param.buffer_threshold = nla_get_u32(iter);
++			break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param,
++				      0) < 0) {
++		WL_ERR(("Could not set batch cfg\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	return err;
++}
++
++static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy,
++					       struct wireless_dev *wdev,
++					       const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_swc_params_t *significant_params;
++	int tmp, tmp1, tmp2, type, j = 0;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0;
++	wl_pfn_significant_bssid_t *pbssid;
++
++	significant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL);
++	if (!significant_params) {
++		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
++		return -1;
++	}
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:
++			flush = nla_get_u8(iter);
++			break;
++		case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:
++			significant_params->rssi_window = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++			significant_params->lost_ap_window = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_MIN_BREACHING:
++			significant_params->swc_threshold = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:
++			pbssid = significant_params->bssid_elem_list;
++			nla_for_each_nested(outer, iter, tmp) {
++				nla_for_each_nested(inner, outer, tmp1) {
++					switch (nla_type(inner)) {
++					case GSCAN_ATTRIBUTE_BSSID:
++						memcpy(&(pbssid[j].macaddr),
++						       nla_data(inner),
++						       ETHER_ADDR_LEN);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_HIGH:
++						pbssid[j].rssi_high_threshold =
++						    (int8) nla_get_u8(inner);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_LOW:
++						pbssid[j].rssi_low_threshold =
++						    (int8) nla_get_u8(inner);
++						break;
++					}
++				}
++				j++;
++			}
++			break;
++		}
++	}
++	significant_params->nbssid = j;
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_SIGNIFICANT_SCAN_CFG_ID,
++				      significant_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN significant cfg\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++ exit:
++	kfree(significant_params);
++	return err;
++}
++#endif				/* GSCAN_SUPPORT */
++
++#if defined(RTT_SUPPORT) && 0
++void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
++{
++	struct wireless_dev *wdev = (struct wireless_dev *)ctx;
++	struct wiphy *wiphy;
++	struct sk_buff *skb;
++	uint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0;
++	gfp_t kflags;
++	rtt_report_t *rtt_report = NULL;
++	rtt_result_t *rtt_result = NULL;
++	struct list_head *rtt_list;
++	wiphy = wdev->wiphy;
++
++	WL_DBG(("In\n"));
++	/* Push the data to the skb */
++	if (!rtt_data) {
++		WL_ERR(("rtt_data is NULL\n"));
++		goto exit;
++	}
++	rtt_list = (struct list_head *)rtt_data;
++	kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
++	/* Alloc the SKB for vendor_event */
++	skb =
++	    ssv_cfg80211_vendor_event_alloc(wiphy, tot_len,
++					    GOOGLE_RTT_COMPLETE_EVENT, kflags);
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		goto exit;
++	}
++	/* fill in the rtt results on each entry */
++	list_for_each_entry(rtt_result, rtt_list, list) {
++		entry_len = 0;
++		if (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) {
++			entry_len = sizeof(rtt_report_t);
++			rtt_report = kzalloc(entry_len, kflags);
++			if (!rtt_report) {
++				WL_ERR(("rtt_report alloc failed"));
++				goto exit;
++			}
++			rtt_report->addr = rtt_result->peer_mac;
++			rtt_report->num_measurement = 1;	/* ONE SHOT */
++			rtt_report->status = rtt_result->err_code;
++			rtt_report->type =
++			    (rtt_result->TOF_type ==
++			     TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY;
++			rtt_report->peer = rtt_result->target_info->peer;
++			rtt_report->channel = rtt_result->target_info->channel;
++			rtt_report->rssi = rtt_result->avg_rssi;
++			/* tx_rate */
++			rtt_report->tx_rate = rtt_result->tx_rate;
++			/* RTT */
++			rtt_report->rtt = rtt_result->meanrtt;
++			rtt_report->rtt_sd = rtt_result->sdrtt;
++			/* convert to centi meter */
++			if (rtt_result->distance != 0xffffffff)
++				rtt_report->distance =
++				    (rtt_result->distance >> 2) * 25;
++			else	/* invalid distance */
++				rtt_report->distance = -1;
++
++			rtt_report->ts = rtt_result->ts;
++			nla_append(skb, entry_len, rtt_report);
++			kfree(rtt_report);
++		}
++	}
++	ssv_cfg80211_vendor_event(skb, kflags);
++ exit:
++	return;
++}
++
++static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy,
++				       struct wireless_dev *wdev,
++				       const void *data, int len)
++{
++	int err = 0, rem, rem1, rem2, type;
++	rtt_config_params_t rtt_param;
++	rtt_target_info_t *rtt_target = NULL;
++	const struct nlattr *iter, *iter1, *iter2;
++	int8 eabuf[ETHER_ADDR_STR_LEN];
++	int8 chanbuf[CHANSPEC_STR_LEN];
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	WL_DBG(("In\n"));
++	err =
++	    dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev,
++					       wl_cfgvendor_rtt_evt);
++	if (err < 0) {
++		WL_ERR(("failed to register rtt_noti_callback\n"));
++		goto exit;
++	}
++	memset(&rtt_param, 0, sizeof(rtt_param));
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			rtt_param.rtt_target_cnt = nla_get_u8(iter);
++			if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {
++				WL_ERR(("exceed max target count : %d\n",
++					rtt_param.rtt_target_cnt));
++				err = BCME_RANGE;
++			}
++			break;
++		case RTT_ATTRIBUTE_TARGET_INFO:
++			rtt_target = rtt_param.target_info;
++			nla_for_each_nested(iter1, iter, rem1) {
++				nla_for_each_nested(iter2, iter1, rem2) {
++					type = nla_type(iter2);
++					switch (type) {
++					case RTT_ATTRIBUTE_TARGET_MAC:
++						memcpy(&rtt_target->addr,
++						       nla_data(iter2),
++						       ETHER_ADDR_LEN);
++						break;
++					case RTT_ATTRIBUTE_TARGET_TYPE:
++						rtt_target->type =
++						    nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_PEER:
++						rtt_target->peer =
++						    nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_CHAN:
++						memcpy(&rtt_target->channel,
++						       nla_data(iter2),
++						       sizeof(rtt_target->
++							      channel));
++						break;
++					case RTT_ATTRIBUTE_TARGET_MODE:
++						rtt_target->continuous =
++						    nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_INTERVAL:
++						rtt_target->interval =
++						    nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT:
++						rtt_target->measure_cnt =
++						    nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_PKT:
++						rtt_target->ftm_cnt =
++						    nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_RETRY:
++						rtt_target->retry_cnt =
++						    nla_get_u32(iter2);
++					}
++				}
++				/* convert to chanspec value */
++				rtt_target->chanspec =
++				    dhd_rtt_convert_to_chspec(rtt_target->
++							      channel);
++				if (rtt_target->chanspec == 0) {
++					WL_ERR(("Channel is not valid \n"));
++					goto exit;
++				}
++				WL_INFORM(("Target addr %s, Channel : %s for RTT \n", bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf), wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
++				rtt_target++;
++			}
++			break;
++		}
++	}
++	WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
++	if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
++		WL_ERR(("Could not set RTT configuration\n"));
++		err = -EINVAL;
++	}
++ exit:
++	return err;
++}
++
++static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy,
++					  struct wireless_dev *wdev,
++					  const void *data, int len)
++{
++	int err = 0, rem, type, target_cnt = 0;
++	const struct nlattr *iter;
++	struct ether_addr *mac_list = NULL, *mac_addr = NULL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			target_cnt = nla_get_u8(iter);
++			mac_list =
++			    (struct ether_addr *)kzalloc(target_cnt *
++							 ETHER_ADDR_LEN,
++							 GFP_KERNEL);
++			if (mac_list == NULL) {
++				WL_ERR(("failed to allocate mem for mac list\n"));
++				goto exit;
++			}
++			mac_addr = &mac_list[0];
++			break;
++		case RTT_ATTRIBUTE_TARGET_MAC:
++			if (mac_addr)
++				memcpy(mac_addr++, nla_data(iter),
++				       ETHER_ADDR_LEN);
++			else {
++				WL_ERR(("mac_list is NULL\n"));
++				goto exit;
++			}
++			break;
++		}
++		if (dhd_dev_rtt_cancel_cfg
++		    (bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
++			WL_ERR(("Could not cancel RTT configuration\n"));
++			err = -EINVAL;
++			goto exit;
++		}
++	}
++ exit:
++	if (mac_list)
++		kfree(mac_list);
++	return err;
++}
++
++static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy,
++					   struct wireless_dev *wdev,
++					   const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	rtt_capabilities_t capability;
++
++	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		goto exit;
++	}
++	err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++					   &capability, sizeof(capability));
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++	}
++ exit:
++	return err;
++}
++
++#endif				/* RTT_SUPPORT */
++static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy,
++					    struct wireless_dev *wdev,
++					    const void *data, int len)
++{
++	int err = 0;
++	u8 resp[1] = { '\0' };
++
++	dev_dbg(&wiphy->dev, "%s\n", (char *)data);
++	err = ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), resp, 1);
++	if (unlikely(err))
++		dev_err(&wiphy->dev, "vendor Command reply failed, ret=:%d\n", err);
++
++	return err;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
++static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
++	{
++	 {
++	  .vendor_id = OUI_SSV,
++	  .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_priv_string_handler,
++	 .policy = VENDOR_CMD_RAW_DATA},
++#if defined(GSCAN_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_capabilities,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_scan_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_batch_scan_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_initiate_gscan,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_enable_full_scan_result,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_hotlist_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_significant_change_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_batch_results,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_channel_list,
++	 .policy = VENDOR_CMD_RAW_DATA},
++#endif				/* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_set_config,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_cancel_config,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_GETCAPABILITY},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_get_capability,
++	 .policy = VENDOR_CMD_RAW_DATA},
++#endif				/* RTT_SUPPORT */
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set_matrix,
++	 .policy = VENDOR_CMD_RAW_DATA}
++};
++#else
++static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
++	{
++	 {
++	  .vendor_id = OUI_SSV,
++	  .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_priv_string_handler
++	},
++#if defined(GSCAN_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_capabilities
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_scan_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_batch_scan_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_initiate_gscan
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_enable_full_scan_result
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_hotlist_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_significant_change_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_batch_results
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_channel_list
++	},
++#endif				/* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_set_config
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_cancel_config
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_GETCAPABILITY},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_get_capability
++	},
++#endif				/* RTT_SUPPORT */
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set_matrix
++	}
++};
++#endif
++
++static const struct nl80211_vendor_cmd_info ssv_vendor_events[] = {
++	{OUI_SSV, RTK_VENDOR_EVENT_UNSPEC},
++	{OUI_SSV, RTK_VENDOR_EVENT_PRIV_STR},
++#if defined(GSCAN_SUPPORT) && 0
++	{OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT},
++	{OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT},
++	{OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT},
++	{OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT},
++#endif				/* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT},
++#endif				/* RTT_SUPPORT */
++#if defined(GSCAN_SUPPORT) && 0
++	{OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT},
++	{OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT}
++#endif				/* GSCAN_SUPPORT */
++};
++
++int ssv_cfgvendor_attach(struct wiphy *wiphy)
++{
++
++	dev_info(&wiphy->dev, "register SSV cfg80211 vendor cmd(0x%x) interface\n",
++		NL80211_CMD_VENDOR);
++
++	wiphy->vendor_commands = ssv_vendor_cmds;
++	wiphy->n_vendor_commands = ARRAY_SIZE(ssv_vendor_cmds);
++	wiphy->vendor_events = ssv_vendor_events;
++	wiphy->n_vendor_events = ARRAY_SIZE(ssv_vendor_events);
++
++	return 0;
++}
++
++int ssv_cfgvendor_detach(struct wiphy *wiphy)
++{
++	dev_info(&wiphy->dev, "unregister SSV cfg80211 vendor interface\n");
++
++	wiphy->vendor_commands = NULL;
++	wiphy->vendor_events = NULL;
++	wiphy->n_vendor_commands = 0;
++	wiphy->n_vendor_events = 0;
++
++	return 0;
++}
++#endif				/* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT) */
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
+new file mode 100644
+index 000000000000..6d8696fcd220
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
+@@ -0,0 +1,247 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved.
++ *                                        
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#ifndef _RTW_CFGVENDOR_H_
++#define _RTW_CFGVENDOR_H_
++
++#define OUI_SSV		0x00E04C
++#define OUI_GOOGLE	0x001A11
++#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)
++#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN
++#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN
++#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)
++
++#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN
++#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)
++#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN
++#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN
++#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN
++#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)
++#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
++									SCAN_FLAGS_HDR_LEN + \
++							        GSCAN_NUM_RESULTS_HDR_LEN + \
++									GSCAN_RESULTS_HDR_LEN)
++
++#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \
++									VENDOR_SUBCMD_OVERHEAD + \
++									VENDOR_DATA_OVERHEAD)
++typedef enum {
++	/* don't use 0 as a valid subcommand */
++	VENDOR_NL80211_SUBCMD_UNSPECIFIED,
++
++	/* define all vendor startup commands between 0x0 and 0x0FFF */
++	VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
++	VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF,
++
++	/* define all GScan related commands between 0x1000 and 0x10FF */
++	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
++	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF,
++
++	/* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */
++	ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,
++	ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF,
++
++	/* define all RTT related commands between 0x1100 and 0x11FF */
++	ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
++	ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF,
++
++	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
++	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF,
++
++	ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300,
++	ANDROID_NL80211_SUBCMD_TDLS_RANGE_END = 0x13FF,
++	/* This is reserved for future usage */
++
++} ANDROID_VENDOR_SUB_COMMAND;
++
++enum wl_vendor_subcmd {
++	RTK_VENDOR_SCMD_UNSPEC,
++	RTK_VENDOR_SCMD_PRIV_STR,
++	GSCAN_SUBCMD_GET_CAPABILITIES =
++	    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
++	GSCAN_SUBCMD_SET_CONFIG,
++	GSCAN_SUBCMD_SET_SCAN_CONFIG,
++	GSCAN_SUBCMD_ENABLE_GSCAN,
++	GSCAN_SUBCMD_GET_SCAN_RESULTS,
++	GSCAN_SUBCMD_SCAN_RESULTS,
++	GSCAN_SUBCMD_SET_HOTLIST,
++	GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,
++	GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,
++	GSCAN_SUBCMD_GET_CHANNEL_LIST,
++	ANDR_WIFI_SUBCMD_GET_FEATURE_SET,
++	ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,
++	RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
++	RTT_SUBCMD_CANCEL_CONFIG,
++	RTT_SUBCMD_GETCAPABILITY,
++	/* Add more sub commands here */
++	VENDOR_SUBCMD_MAX
++};
++
++enum gscan_attributes {
++	GSCAN_ATTRIBUTE_NUM_BUCKETS = 10,
++	GSCAN_ATTRIBUTE_BASE_PERIOD,
++	GSCAN_ATTRIBUTE_BUCKETS_BAND,
++	GSCAN_ATTRIBUTE_BUCKET_ID,
++	GSCAN_ATTRIBUTE_BUCKET_PERIOD,
++	GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
++	GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
++	GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
++	GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
++	GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
++	GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
++
++	GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,
++	GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
++	GSCAN_ATTRIBUTE_FLUSH_FEATURE,
++	GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
++	GSCAN_ATTRIBUTE_REPORT_EVENTS,
++	/* remaining reserved for additional attributes */
++	GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,
++	GSCAN_ATTRIBUTE_FLUSH_RESULTS,
++	GSCAN_ATTRIBUTE_SCAN_RESULTS,	/* flat array of wifi_scan_result */
++	GSCAN_ATTRIBUTE_SCAN_ID,	/* indicates scan number */
++	GSCAN_ATTRIBUTE_SCAN_FLAGS,	/* indicates if scan was aborted */
++	GSCAN_ATTRIBUTE_AP_FLAGS,	/* flags on significant change event */
++	GSCAN_ATTRIBUTE_NUM_CHANNELS,
++	GSCAN_ATTRIBUTE_CHANNEL_LIST,
++
++	/* remaining reserved for additional attributes */
++
++	GSCAN_ATTRIBUTE_SSID = 40,
++	GSCAN_ATTRIBUTE_BSSID,
++	GSCAN_ATTRIBUTE_CHANNEL,
++	GSCAN_ATTRIBUTE_RSSI,
++	GSCAN_ATTRIBUTE_TIMESTAMP,
++	GSCAN_ATTRIBUTE_RTT,
++	GSCAN_ATTRIBUTE_RTTSD,
++
++	/* remaining reserved for additional attributes */
++
++	GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50,
++	GSCAN_ATTRIBUTE_RSSI_LOW,
++	GSCAN_ATTRIBUTE_RSSI_HIGH,
++	GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
++	GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
++
++	/* remaining reserved for additional attributes */
++	GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60,
++	GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
++	GSCAN_ATTRIBUTE_MIN_BREACHING,
++	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
++	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
++	GSCAN_ATTRIBUTE_MAX
++};
++
++enum gscan_bucket_attributes {
++	GSCAN_ATTRIBUTE_CH_BUCKET_1,
++	GSCAN_ATTRIBUTE_CH_BUCKET_2,
++	GSCAN_ATTRIBUTE_CH_BUCKET_3,
++	GSCAN_ATTRIBUTE_CH_BUCKET_4,
++	GSCAN_ATTRIBUTE_CH_BUCKET_5,
++	GSCAN_ATTRIBUTE_CH_BUCKET_6,
++	GSCAN_ATTRIBUTE_CH_BUCKET_7
++};
++
++enum gscan_ch_attributes {
++	GSCAN_ATTRIBUTE_CH_ID_1,
++	GSCAN_ATTRIBUTE_CH_ID_2,
++	GSCAN_ATTRIBUTE_CH_ID_3,
++	GSCAN_ATTRIBUTE_CH_ID_4,
++	GSCAN_ATTRIBUTE_CH_ID_5,
++	GSCAN_ATTRIBUTE_CH_ID_6,
++	GSCAN_ATTRIBUTE_CH_ID_7
++};
++
++enum rtt_attributes {
++	RTT_ATTRIBUTE_TARGET_CNT,
++	RTT_ATTRIBUTE_TARGET_INFO,
++	RTT_ATTRIBUTE_TARGET_MAC,
++	RTT_ATTRIBUTE_TARGET_TYPE,
++	RTT_ATTRIBUTE_TARGET_PEER,
++	RTT_ATTRIBUTE_TARGET_CHAN,
++	RTT_ATTRIBUTE_TARGET_MODE,
++	RTT_ATTRIBUTE_TARGET_INTERVAL,
++	RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT,
++	RTT_ATTRIBUTE_TARGET_NUM_PKT,
++	RTT_ATTRIBUTE_TARGET_NUM_RETRY
++};
++
++typedef enum wl_vendor_event {
++	RTK_VENDOR_EVENT_UNSPEC,
++	RTK_VENDOR_EVENT_PRIV_STR,
++	GOOGLE_GSCAN_SIGNIFICANT_EVENT,
++	GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT,
++	GOOGLE_GSCAN_BATCH_SCAN_EVENT,
++	GOOGLE_SCAN_FULL_RESULTS_EVENT,
++	GOOGLE_RTT_COMPLETE_EVENT,
++	GOOGLE_SCAN_COMPLETE_EVENT,
++	GOOGLE_GSCAN_GEOFENCE_LOST_EVENT
++} wl_vendor_event_t;
++
++enum andr_wifi_feature_set_attr {
++	ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
++	ANDR_WIFI_ATTRIBUTE_FEATURE_SET
++};
++
++typedef enum wl_vendor_gscan_attribute {
++	ATTR_START_GSCAN,
++	ATTR_STOP_GSCAN,
++	ATTR_SET_SCAN_BATCH_CFG_ID,	/* set batch scan params */
++	ATTR_SET_SCAN_GEOFENCE_CFG_ID,	/* set list of bssids to track */
++	ATTR_SET_SCAN_SIGNIFICANT_CFG_ID,	/* set list of bssids, rssi threshold etc.. */
++	ATTR_SET_SCAN_CFG_ID,	/* set common scan config params here */
++	ATTR_GET_GSCAN_CAPABILITIES_ID,
++	/* Add more sub commands here */
++	ATTR_GSCAN_MAX
++} wl_vendor_gscan_attribute_t;
++
++typedef enum gscan_batch_attribute {
++	ATTR_GSCAN_BATCH_BESTN,
++	ATTR_GSCAN_BATCH_MSCAN,
++	ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
++} gscan_batch_attribute_t;
++
++typedef enum gscan_geofence_attribute {
++	ATTR_GSCAN_NUM_HOTLIST_BSSID,
++	ATTR_GSCAN_HOTLIST_BSSID
++} gscan_geofence_attribute_t;
++
++typedef enum gscan_complete_event {
++	WIFI_SCAN_BUFFER_FULL,
++	WIFI_SCAN_COMPLETE
++} gscan_complete_event_t;
++
++/* Capture the RTK_VENDOR_SUBCMD_PRIV_STRINGS* here */
++#define RTK_VENDOR_SCMD_CAPA	"cap"
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT)
++extern int ssv_cfgvendor_attach(struct wiphy *wiphy);
++extern int ssv_cfgvendor_detach(struct wiphy *wiphy);
++extern int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
++					  struct net_device *dev, int event_id,
++					  const void *data, int len);
++#if defined(GSCAN_SUPPORT) && 0
++extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++					   struct net_device *dev, void *data,
++					   int len, wl_vendor_event_t event);
++#endif
++#endif				/* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
++
++#endif				/* _RTW_CFGVENDOR_H_ */
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
+new file mode 100644
+index 000000000000..fae819c43400
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
+@@ -0,0 +1,546 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ssv_ht_rc.h"
++#include "ssv_rc.h"
++#define SAMPLE_COUNT 4
++#define HT_CW_MIN 15
++#define HT_SEGMENT_SIZE 6000
++#define AVG_PKT_SIZE 12000
++#define SAMPLE_COLUMNS 10
++#define EWMA_LEVEL 75
++#define MCS_NBITS (AVG_PKT_SIZE << 3)
++#define MCS_NSYMS(bps) ((MCS_NBITS + (bps) - 1) / (bps))
++#define MCS_SYMBOL_TIME(sgi,syms) \
++    (sgi ? \
++      ((syms) * 18 + 4) / 5 : \
++      (syms) << 2 \
++    )
++#define MCS_DURATION(streams,sgi,bps) MCS_SYMBOL_TIME(sgi, MCS_NSYMS((streams) * (bps)))
++#define MCS_GROUP(_streams,_sgi,_ht40) { \
++    .duration = { \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 54 : 26), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 108 : 52), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 162 : 78), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 216 : 104), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 324 : 156), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 432 : 208), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 486 : 234), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 540 : 260) \
++    } \
++}
++const struct mcs_group minstrel_mcs_groups_ssv[] = {
++	MCS_GROUP(1, 0, 0),
++	MCS_GROUP(1, 1, 0),
++};
++
++const u16 ampdu_max_transmit_length[RATE_TABLE_SIZE] = {
++	0, 0, 0, 0, 0, 0, 0,
++	0, 0, 0, 0, 0, 0, 0, 0,
++	4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200,
++	5100, 10200, 15400, 20500, 30800, 41100, 46200, 51300,
++	4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200
++};
++
++static u8 sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES];
++static int minstrel_ewma(int old, int new, int weight)
++{
++	return (new * (100 - weight) + old * weight) / 100;
++}
++
++static inline struct minstrel_rate_stats *minstrel_get_ratestats(struct
++								 ssv62xx_ht *mi,
++								 int index)
++{
++	return &mi->groups.rates[index % MCS_GROUP_RATES];
++}
++
++static void minstrel_calc_rate_ewma(struct minstrel_rate_stats *mr)
++{
++	if (unlikely(mr->attempts > 0)) {
++		mr->sample_skipped = 0;
++		mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts);
++		if (!mr->att_hist)
++			mr->probability = mr->cur_prob;
++		else
++			mr->probability = minstrel_ewma(mr->probability,
++							mr->cur_prob,
++							EWMA_LEVEL);
++		mr->att_hist += mr->attempts;
++		mr->succ_hist += mr->success;
++	} else {
++		mr->sample_skipped++;
++	}
++	mr->last_success = mr->success;
++	mr->last_attempts = mr->attempts;
++	mr->success = 0;
++	mr->attempts = 0;
++}
++
++static void minstrel_ht_calc_tp(struct ssv62xx_ht *mi,
++				struct ssv_sta_rc_info *rc_sta, int rate)
++{
++	struct minstrel_rate_stats *mr;
++	unsigned int usecs, group_id;
++	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
++		group_id = 0;
++	else
++		group_id = 1;
++	mr = &mi->groups.rates[rate];
++	if (mr->probability < MINSTREL_FRAC(1, 10)) {
++		mr->cur_tp = 0;
++		return;
++	}
++	usecs = mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
++	usecs += minstrel_mcs_groups_ssv[group_id].duration[rate];
++	mr->cur_tp = MINSTREL_TRUNC((1000000 / usecs) * mr->probability);
++}
++
++static void rate_control_ht_sample(struct ssv62xx_ht *mi,
++				   struct ssv_sta_rc_info *rc_sta)
++{
++	struct minstrel_mcs_group_data *mg;
++	struct minstrel_rate_stats *mr;
++	int cur_prob, cur_prob_tp, cur_tp, cur_tp2;
++	int i, index;
++	if (mi->ampdu_packets > 0) {
++		mi->avg_ampdu_len = minstrel_ewma(mi->avg_ampdu_len,
++						  MINSTREL_FRAC(mi->ampdu_len,
++								mi->
++								ampdu_packets),
++						  EWMA_LEVEL);
++		mi->ampdu_len = 0;
++		mi->ampdu_packets = 0;
++	} else
++		return;
++	mi->sample_slow = 0;
++	mi->sample_count = 0;
++	{
++		cur_prob = 0;
++		cur_prob_tp = 0;
++		cur_tp = 0;
++		cur_tp2 = 0;
++		mg = &mi->groups;
++		mg->max_tp_rate = 0;
++		mg->max_tp_rate2 = 0;
++		mg->max_prob_rate = 0;
++		for (i = 0; i < MCS_GROUP_RATES; i++) {
++			if (!(rc_sta->ht_supp_rates & BIT(i)))
++				continue;
++			mr = &mg->rates[i];
++			index = i;
++			minstrel_calc_rate_ewma(mr);
++			minstrel_ht_calc_tp(mi, rc_sta, i);
++#ifdef RATE_CONTROL_HT_PARAMETER_DEBUG
++			if (mr->cur_prob)
++				pr_debug
++				    ("rate[%d]probability[%08d]cur_prob[%08d]TP[%04d]\n",
++				     i, mr->probability, mr->cur_prob,
++				     mr->cur_tp);
++#endif
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			pr_debug
++			    ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
++			     mg->max_tp_rate, mg->max_tp_rate2,
++			     mg->max_prob_rate);
++			pr_debug("rate[%d]probability[%08d]TP[%d]\n", i,
++			       mr->probability, mr->cur_tp);
++#endif
++			if (!mr->cur_tp)
++				continue;
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			pr_debug("HT--1 mr->cur_tp[%d]cur_prob_tp[%d]\n",
++			       mr->cur_tp, cur_prob_tp);
++#endif
++			if ((mr->cur_tp > cur_prob_tp && mr->probability >
++			     MINSTREL_FRAC(3, 4))
++			    || mr->probability > cur_prob) {
++				mg->max_prob_rate = index;
++				cur_prob = mr->probability;
++				cur_prob_tp = mr->cur_tp;
++			}
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			pr_debug("HT--2 mr->cur_tp[%d]cur_tp[%d]\n", mr->cur_tp,
++			       cur_tp);
++#endif
++			if (mr->cur_tp > cur_tp) {
++				swap(index, mg->max_tp_rate);
++				cur_tp = mr->cur_tp;
++				mr = minstrel_get_ratestats(mi, index);
++			}
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			if (index != i)
++				pr_debug
++				    ("HT--3 index[%d]i[%d]mg->max_tp_rate[%d]\n",
++				     index, i, mg->max_tp_rate);
++#endif
++			if (index >= mg->max_tp_rate)
++				continue;
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			if (index != i)
++				pr_debug("HT--4 mr->cur_tp[%d]cur_tp2[%d]\n",
++				       mr->cur_tp, cur_tp2);
++#endif
++			if (mr->cur_tp > cur_tp2) {
++				mg->max_tp_rate2 = index;
++				cur_tp2 = mr->cur_tp;
++			}
++		}
++	}
++	mi->sample_count = SAMPLE_COUNT;
++	mi->max_tp_rate = mg->max_tp_rate;
++	mi->max_tp_rate2 = mg->max_tp_rate2;
++	mi->max_prob_rate = mg->max_prob_rate;
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++	pr_debug
++	    ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
++	     mi->max_tp_rate, mi->max_tp_rate2, mi->max_prob_rate);
++#endif
++	mi->stats_update = jiffies;
++}
++
++static void minstrel_ht_set_rate(struct ssv62xx_ht *mi,
++				 struct fw_rc_retry_params *rate, int index,
++				 bool sample, bool rtscts,
++				 struct ssv_sta_rc_info *rc_sta,
++				 struct ssv_rate_ctrl *ssv_rc)
++{
++	struct minstrel_rate_stats *mr;
++	mr = minstrel_get_ratestats(mi, index);
++	rate->drate = ssv_rc->rc_table[mr->rc_index].hw_rate_idx;
++	rate->crate = ssv_rc->rc_table[mr->rc_index].ctrl_rate_idx;
++}
++
++static inline int minstrel_get_duration(int index,
++					struct ssv_sta_rc_info *rc_sta)
++{
++	unsigned int group_id;
++	const struct mcs_group *group;
++	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
++		group_id = 0;
++	else
++		group_id = 1;
++	group = &minstrel_mcs_groups_ssv[group_id];
++	return group->duration[index % MCS_GROUP_RATES];
++}
++
++static void minstrel_next_sample_idx(struct ssv62xx_ht *mi)
++{
++	struct minstrel_mcs_group_data *mg;
++	for (;;) {
++		mg = &mi->groups;
++		if (++mg->index >= MCS_GROUP_RATES) {
++			mg->index = 0;
++			if (++mg->column >= ARRAY_SIZE(sample_table))
++				mg->column = 0;
++		}
++		break;
++	}
++}
++
++static int minstrel_get_sample_rate(struct ssv62xx_ht *mi,
++				    struct ssv_sta_rc_info *rc_sta)
++{
++	struct minstrel_rate_stats *mr;
++	struct minstrel_mcs_group_data *mg;
++	int sample_idx = 0;
++	if (mi->sample_wait > 0) {
++		mi->sample_wait--;
++		return -1;
++	}
++	if (!mi->sample_tries)
++		return -1;
++	mi->sample_tries--;
++	mg = &mi->groups;
++	sample_idx = sample_table[mg->column][mg->index];
++	mr = &mg->rates[sample_idx];
++	minstrel_next_sample_idx(mi);
++	if (minstrel_get_duration(sample_idx, rc_sta) >
++	    minstrel_get_duration(mi->max_tp_rate, rc_sta)) {
++		if (mr->sample_skipped < 20) {
++			return -1;
++		}
++		if (mi->sample_slow++ > 2) {
++			return -1;
++		}
++	}
++	return sample_idx;
++}
++
++static void _fill_txinfo_rates(struct ssv_rate_ctrl *ssv_rc,
++			       struct sk_buff *skb,
++			       struct fw_rc_retry_params *ar)
++{
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	info->control.rates[0].idx =
++	    ssv_rc->rc_table[ar[0].drate].dot11_rate_idx;
++	info->control.rates[0].count = 1;
++	info->control.rates[SSV_DRATE_IDX].count = ar[0].drate;
++	info->control.rates[SSV_CRATE_IDX].count = ar[0].crate;
++}
++
++extern const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13];
++s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
++			   struct fw_rc_retry_params *ar)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++	struct ieee80211_sta *sta = skb_info->sta;
++	struct ssv62xx_ht *mi = NULL;
++	int sample_idx;
++	bool sample = false;
++	struct ssv_sta_rc_info *rc_sta;
++	struct ssv_sta_priv_data *sta_priv;
++	struct rc_pid_sta_info *spinfo;
++	int ret = 0;
++	if (sc->sc_flags & SC_OP_FIXED_RATE) {
++		ar[0].count = 3;
++		ar[0].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++		ar[0].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
++		ar[1].count = 2;
++		ar[1].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++		ar[1].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
++		ar[2].count = 2;
++		ar[2].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++		ar[2].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
++		_fill_txinfo_rates(ssv_rc, skb, ar);
++		return ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++	}
++	if (sta == NULL) {
++		dev_err(sc->dev, "Station NULL\n");
++		BUG_ON(1);
++	}
++	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
++	spinfo = &rc_sta->spinfo;
++	if ((rc_sta->rc_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT)
++	    || (rc_sta->rc_wsid < 0)) {
++		struct ssv_sta_priv_data *ssv_sta_priv;
++		int rateidx = 99;
++		ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		{
++			if ((rc_sta->ht_rc_type >= RC_TYPE_HT_SGI_20) &&
++			    (ssv_sta_priv->rx_data_rate <
++			     SSV62XX_RATE_MCS_INDEX)) {
++				if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0]
++				    == 12)
++					rateidx =
++					    (int)rc_sta->pinfo.rinfo[4].
++					    rc_index;
++				else
++					rateidx =
++					    (int)rc_sta->pinfo.rinfo[0].
++					    rc_index;
++			} else {
++				rateidx = (int)ssv_sta_priv->rx_data_rate;
++				rateidx -= SSV62XX_RATE_MCS_INDEX;
++				rateidx %= 8;
++				if (rc_sta->ht_rc_type == RC_TYPE_HT_SGI_20)
++					rateidx += SSV62XX_RATE_MCS_SGI_INDEX;
++				else if (rc_sta->ht_rc_type ==
++					 RC_TYPE_HT_LGI_20)
++					rateidx += SSV62XX_RATE_MCS_LGI_INDEX;
++				else
++					rateidx +=
++					    SSV62XX_RATE_MCS_GREENFIELD_INDEX;
++			}
++		}
++		ar[0].count = 3;
++		ar[2].drate = ar[1].drate = ar[0].drate =
++		    ssv_rc->rc_table[rateidx].hw_rate_idx;
++		ar[2].crate = ar[1].crate = ar[0].crate =
++		    ssv_rc->rc_table[rateidx].ctrl_rate_idx;
++		ar[1].count = 2;
++		ar[2].count = 2;
++		_fill_txinfo_rates(ssv_rc, skb, ar);
++		return rateidx;
++	}
++	mi = &rc_sta->ht;
++	sample_idx = minstrel_get_sample_rate(mi, rc_sta);
++	if (sample_idx >= 0) {
++		sample = true;
++		minstrel_ht_set_rate(mi, &ar[0], sample_idx,
++				     true, false, rc_sta, ssv_rc);
++	} else {
++		minstrel_ht_set_rate(mi, &ar[0], mi->max_tp_rate,
++				     false, false, rc_sta, ssv_rc);
++	}
++	ar[0].count = mi->first_try_count;
++	ret = ar[0].drate;
++	{
++		if (sample_idx >= 0)
++			minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate,
++					     false, false, rc_sta, ssv_rc);
++		else
++			minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate2,
++					     false, true, rc_sta, ssv_rc);
++		ar[1].count = mi->second_try_count;
++		if (ret > ar[1].drate)
++			ret = ar[1].drate;
++		minstrel_ht_set_rate(mi, &ar[2], mi->max_prob_rate,
++				     false, !sample, rc_sta, ssv_rc);
++		ar[2].count = mi->other_try_count;
++		if (ret > ar[2].drate)
++			ret = ar[2].drate;
++	}
++	mi->total_packets++;
++	if (mi->total_packets == ~0) {
++		mi->total_packets = 0;
++		mi->sample_packets = 0;
++	}
++	if (spinfo->real_hw_index < SSV62XX_RATE_MCS_INDEX)
++		return spinfo->real_hw_index;
++	_fill_txinfo_rates(ssv_rc, skb, ar);
++	return ret;
++}
++
++static void init_sample_table(void)
++{
++	int col, i, new_idx;
++	u8 rnd[MCS_GROUP_RATES];
++	memset(sample_table, 0xff, sizeof(sample_table));
++	for (col = 0; col < SAMPLE_COLUMNS; col++) {
++		for (i = 0; i < MCS_GROUP_RATES; i++) {
++			get_random_bytes(rnd, sizeof(rnd));
++			new_idx = (i + rnd[i]) % MCS_GROUP_RATES;
++			while (sample_table[col][new_idx] != 0xff)
++				new_idx = (new_idx + 1) % MCS_GROUP_RATES;
++			sample_table[col][new_idx] = i;
++		}
++	}
++}
++
++void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
++			struct ssv_sta_rc_info *rc_sta)
++{
++	struct ssv62xx_ht *mi = &rc_sta->ht;
++	int ack_dur;
++	int i;
++	unsigned int group_id;
++	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
++		group_id = 0;
++	else
++		group_id = 1;
++	for (i = 0; i < MCS_GROUP_RATES; i++) {
++		pr_debug("[RC]HT duration[%d][%d]\n", i,
++		       minstrel_mcs_groups_ssv[group_id].duration[i]);
++	}
++	init_sample_table();
++	memset(mi, 0, sizeof(*mi));
++	mi->stats_update = jiffies;
++	ack_dur = pide_frame_duration(10, 60, 0, 0);
++	mi->overhead = pide_frame_duration(0, 60, 0, 0) + ack_dur;
++	mi->overhead_rtscts = mi->overhead + 2 * ack_dur;
++	mi->avg_ampdu_len = MINSTREL_FRAC(1, 1);
++	mi->sample_count = 16;
++	mi->sample_wait = 0;
++	mi->sample_tries = 4;
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++	mi->max_tp_rate = MCS_GROUP_RATES - 1;
++	mi->max_tp_rate2 = MCS_GROUP_RATES - 1;
++	mi->max_prob_rate = MCS_GROUP_RATES - 1;
++#endif
++#if (HW_MAX_RATE_TRIES == 7)
++	{
++		mi->first_try_count = 3;
++		mi->second_try_count = 2;
++		mi->other_try_count = 2;
++	}
++#else
++	{
++		mi->first_try_count = 2;
++		mi->second_try_count = 1;
++		mi->other_try_count = 1;
++	}
++#endif
++	for (i = 0; i < MCS_GROUP_RATES; i++) {
++		mi->groups.rates[i].rc_index =
++		    ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][i + 1];
++	}
++}
++
++static bool minstrel_ht_txstat_valid(struct ssv62xx_tx_rate *rate)
++{
++	if (!rate->count)
++		return false;
++	if (rate->data_rate < 0)
++		return false;
++	return true;
++}
++
++void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
++			       struct ssv_sta_rc_info *rc_sta)
++{
++	struct cfg_host_event *host_event;
++	struct firmware_rate_control_report_data *report_data;
++	struct ssv62xx_ht *mi;
++	struct minstrel_rate_stats *rate;
++	bool last = false;
++	int i = 0;
++	u16 report_ampdu_packets = 0;
++	unsigned long period;
++	host_event = (struct cfg_host_event *)skb->data;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
++	if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
++		report_ampdu_packets = 1;
++	} else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
++		report_data->ampdu_len = 1;
++		report_ampdu_packets = report_data->ampdu_len;
++	} else {
++		dev_warn(sc->dev, "rate control report handler got garbage\n");
++		return;
++	}
++	mi = &rc_sta->ht;
++	mi->ampdu_packets += report_ampdu_packets;
++	mi->ampdu_len += report_data->ampdu_len;
++	if (!mi->sample_wait && !mi->sample_tries && mi->sample_count > 0) {
++		mi->sample_wait = 16 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len);
++		mi->sample_tries = 2;
++		mi->sample_count--;
++	}
++	for (i = 0; !last; i++) {
++		last = (i == SSV62XX_TX_MAX_RATES - 1) ||
++		    !minstrel_ht_txstat_valid(&report_data->rates[i + 1]);
++		if (!minstrel_ht_txstat_valid(&report_data->rates[i]))
++			break;
++#ifdef RATE_CONTROL_DEBUG
++		if ((report_data->rates[i].data_rate < SSV62XX_RATE_MCS_INDEX)
++		    || (report_data->rates[i].data_rate >=
++			SSV62XX_RATE_MCS_GREENFIELD_INDEX)) {
++			dev_dbg
++			    (sc->dev, "[RC]ssv6xxx_ht_report_handler get error report rate[%d]\n",
++			     report_data->rates[i].data_rate);
++			break;
++		}
++#endif
++		rate =
++		    &mi->groups.
++		    rates[(report_data->rates[i].data_rate -
++			   SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES];
++		if (last)
++			rate->success += report_data->ampdu_ack_len;
++		rate->attempts +=
++		    report_data->rates[i].count * report_data->ampdu_len;
++	}
++	period = msecs_to_jiffies(SSV_RC_HT_INTERVAL / 2);
++	if (time_after(jiffies, mi->stats_update + period)) {
++		rate_control_ht_sample(mi, rc_sta);
++	}
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
+new file mode 100644
+index 000000000000..275c3356e036
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
+@@ -0,0 +1,31 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_RC_HT_H_
++#define _SSV_RC_HT_H_
++#include "ssv_rc_common.h"
++#define MINSTREL_SCALE 16
++#define MINSTREL_FRAC(val,div) (((val) << MINSTREL_SCALE) / div)
++#define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE)
++#define SSV_RC_HT_INTERVAL 100
++extern const u16 ampdu_max_transmit_length[];
++s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
++			   struct fw_rc_retry_params *ar);
++void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
++			struct ssv_sta_rc_info *rc_sta);
++void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
++			       struct ssv_sta_rc_info *rc_sta);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.c b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
+new file mode 100644
+index 000000000000..fc3be2013f61
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
+@@ -0,0 +1,19 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include "dev.h"
++#include "sar.h"
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.h b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
+new file mode 100644
+index 000000000000..9be260dd904e
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
+@@ -0,0 +1,20 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_PM_H_
++#define _SSV_PM_H_
++#include <linux/version.h>
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
+new file mode 100644
+index 000000000000..9c3574285364
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
+@@ -0,0 +1,1716 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ssv_ht_rc.h"
++#include "ssv_rc.h"
++#include "ssv_rc_common.h"
++static struct ssv_rc_rate ssv_11bgn_rate_table[] = {
++	[0] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 1000,
++	       .dot11_rate_idx = 0,
++	       .ctrl_rate_idx = 0,
++	       .hw_rate_idx = 0,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[1] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 2000,
++	       .dot11_rate_idx = 1,
++	       .ctrl_rate_idx = 1,
++	       .hw_rate_idx = 1,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[2] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 5500,
++	       .dot11_rate_idx = 2,
++	       .ctrl_rate_idx = 1,
++	       .hw_rate_idx = 2,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[3] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 11000,
++	       .dot11_rate_idx = 3,
++	       .ctrl_rate_idx = 1,
++	       .hw_rate_idx = 3,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[4] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 2000,
++	       .dot11_rate_idx = 1,
++	       .ctrl_rate_idx = 4,
++	       .hw_rate_idx = 4,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[5] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 5500,
++	       .dot11_rate_idx = 2,
++	       .ctrl_rate_idx = 4,
++	       .hw_rate_idx = 5,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[6] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 11000,
++	       .dot11_rate_idx = 3,
++	       .ctrl_rate_idx = 4,
++	       .hw_rate_idx = 6,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[7] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_OFDM,
++	       .rate_kbps = 6000,
++	       .dot11_rate_idx = 4,
++	       .ctrl_rate_idx = 7,
++	       .hw_rate_idx = 7,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[8] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_OFDM,
++	       .rate_kbps = 9000,
++	       .dot11_rate_idx = 5,
++	       .ctrl_rate_idx = 7,
++	       .hw_rate_idx = 8,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[9] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_OFDM,
++	       .rate_kbps = 12000,
++	       .dot11_rate_idx = 6,
++	       .ctrl_rate_idx = 9,
++	       .hw_rate_idx = 9,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[10] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 18000,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 10,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[11] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 24000,
++		.dot11_rate_idx = 8,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 11,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[12] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 36000,
++		.dot11_rate_idx = 9,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 12,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[13] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 48000,
++		.dot11_rate_idx = 10,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 13,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[14] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 54000,
++		.dot11_rate_idx = 11,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 14,
++		.arith_shift = 8,
++		.target_pf = 8},
++	[15] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 6500,
++		.dot11_rate_idx = 0,
++		.ctrl_rate_idx = 7,
++		.hw_rate_idx = 15,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[16] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 13000,
++		.dot11_rate_idx = 1,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 16,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[17] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 19500,
++		.dot11_rate_idx = 2,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 17,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[18] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 26000,
++		.dot11_rate_idx = 3,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 18,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[19] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 39000,
++		.dot11_rate_idx = 4,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 19,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[20] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 52000,
++		.dot11_rate_idx = 5,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 20,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[21] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 58500,
++		.dot11_rate_idx = 6,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 21,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[22] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 65000,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 22,
++		.arith_shift = 8,
++		.target_pf = 8},
++	[23] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 7200,
++		.dot11_rate_idx = 0,
++		.ctrl_rate_idx = 7,
++		.hw_rate_idx = 23,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[24] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 14400,
++		.dot11_rate_idx = 1,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 24,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[25] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 21700,
++		.dot11_rate_idx = 2,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 25,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[26] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 28900,
++		.dot11_rate_idx = 3,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 26,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[27] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 43300,
++		.dot11_rate_idx = 4,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 27,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[28] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 57800,
++		.dot11_rate_idx = 5,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 28,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[29] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 65000,
++		.dot11_rate_idx = 6,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 29,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[30] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 72200,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 30,
++		.arith_shift = 8,
++		.target_pf = 8},
++	[31] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 6500,
++		.dot11_rate_idx = 0,
++		.ctrl_rate_idx = 7,
++		.hw_rate_idx = 31,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[32] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 13000,
++		.dot11_rate_idx = 1,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 32,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[33] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 19500,
++		.dot11_rate_idx = 2,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 33,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[34] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 26000,
++		.dot11_rate_idx = 3,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 34,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[35] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 39000,
++		.dot11_rate_idx = 4,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 35,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[36] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 52000,
++		.dot11_rate_idx = 5,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 36,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[37] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 58500,
++		.dot11_rate_idx = 6,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 37,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[38] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 65000,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 38,
++		.arith_shift = 8,
++		.target_pf = 8},
++};
++
++const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13] = {
++	[RC_TYPE_B_ONLY] = {4, 0, 1, 2, 3},
++	[RC_TYPE_LEGACY_GB] = {12, 0, 1, 2, 7, 8, 3, 9, 10, 11, 12, 13, 14},
++	[RC_TYPE_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
++	[RC_TYPE_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
++	[RC_TYPE_HT_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
++	[RC_TYPE_HT_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
++	[RC_TYPE_HT_GF] = {8, 31, 32, 33, 34, 35, 36, 37, 38},
++};
++
++static u32 ssv6xxx_rate_supported(struct ssv_sta_rc_info *rc_sta, u32 index)
++{
++	return (rc_sta->rc_supp_rates & BIT(index));
++}
++
++static u8 ssv6xxx_rate_lowest_index(struct ssv_sta_rc_info *rc_sta)
++{
++	int i;
++	for (i = 0; i < rc_sta->rc_num_rate; i++)
++		if (ssv6xxx_rate_supported(rc_sta, i))
++			return i;
++	return 0;
++}
++
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++static u8 ssv6xxx_rate_highest_index(struct ssv_sta_rc_info *rc_sta)
++{
++	int i;
++	for (i = rc_sta->rc_num_rate - 1; i >= 0; i--)
++		if (ssv6xxx_rate_supported(rc_sta, i))
++			return i;
++	return 0;
++}
++#endif
++static void rate_control_pid_adjust_rate(struct ssv_sta_rc_info *rc_sta,
++					 struct rc_pid_sta_info *spinfo,
++					 int adj, struct rc_pid_rateinfo *rinfo)
++{
++	int cur_sorted, new_sorted, probe, tmp, n_bitrates;
++	int cur = spinfo->txrate_idx;
++	n_bitrates = rc_sta->rc_num_rate;
++	cur_sorted = rinfo[cur].index;
++	new_sorted = cur_sorted + adj;
++	if (new_sorted < 0)
++		new_sorted = rinfo[0].index;
++	else if (new_sorted >= n_bitrates)
++		new_sorted = rinfo[n_bitrates - 1].index;
++	tmp = new_sorted;
++	if (adj < 0) {
++		for (probe = cur_sorted; probe >= new_sorted; probe--)
++			if (rinfo[probe].diff <= rinfo[cur_sorted].diff &&
++			    ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
++				tmp = probe;
++	} else {
++		for (probe = new_sorted + 1; probe < n_bitrates; probe++)
++			if (rinfo[probe].diff <= rinfo[new_sorted].diff &&
++			    ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
++				tmp = probe;
++	}
++	BUG_ON(tmp < 0 || tmp >= n_bitrates);
++	do {
++		if (ssv6xxx_rate_supported(rc_sta, rinfo[tmp].index)) {
++			spinfo->tmp_rate_idx = rinfo[tmp].index;
++			break;
++		}
++		if (adj < 0)
++			tmp--;
++		else
++			tmp++;
++	} while (tmp < n_bitrates && tmp >= 0);
++	spinfo->oldrate = spinfo->txrate_idx;
++	if (spinfo->tmp_rate_idx != spinfo->txrate_idx) {
++		spinfo->monitoring = 1;
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++		pr_debug("Trigger monitor tmp_rate_idx=[%d]\n",
++		       spinfo->tmp_rate_idx);
++#endif
++		spinfo->probe_cnt = MAXPROBES;
++	}
++}
++
++static void rate_control_pid_normalize(struct rc_pid_info *pinfo, int l)
++{
++	int i, norm_offset = RC_PID_NORM_OFFSET;
++	struct rc_pid_rateinfo *r = pinfo->rinfo;
++	if (r[0].diff > norm_offset)
++		r[0].diff -= norm_offset;
++	else if (r[0].diff < -norm_offset)
++		r[0].diff += norm_offset;
++	for (i = 0; i < l - 1; i++)
++		if (r[i + 1].diff > r[i].diff + norm_offset)
++			r[i + 1].diff -= norm_offset;
++		else if (r[i + 1].diff <= r[i].diff)
++			r[i + 1].diff += norm_offset;
++}
++
++#ifdef RATE_CONTROL_DEBUG
++unsigned int txrate_dlr = 0;
++#endif
++static void rate_control_pid_sample(struct ssv_rate_ctrl *ssv_rc,
++				    struct rc_pid_info *pinfo,
++				    struct ssv_sta_rc_info *rc_sta,
++				    struct rc_pid_sta_info *spinfo)
++{
++	struct rc_pid_rateinfo *rinfo = pinfo->rinfo;
++	u8 pf;
++	s32 err_avg;
++	s32 err_prop;
++	s32 err_int;
++	s32 err_der;
++	int adj, i, j, tmp;
++	struct ssv_rc_rate *rc_table;
++	unsigned int dlr;
++	unsigned int perfect_time = 0;
++	unsigned int this_thp, ewma_thp;
++	struct rc_pid_rateinfo *rate;
++	if (!spinfo->monitoring) {
++		if (spinfo->tx_num_xmit == 0)
++			return;
++		spinfo->last_sample = jiffies;
++		pf = spinfo->tx_num_failed * 100 / spinfo->tx_num_xmit;
++		if (pinfo->rinfo[spinfo->txrate_idx].this_attempt > 0) {
++			rate = &pinfo->rinfo[spinfo->txrate_idx];
++			rc_table = &ssv_rc->rc_table[spinfo->txrate_idx];
++			dlr = 100 - rate->this_fail * 100 / rate->this_attempt;
++			perfect_time = rate->perfect_tx_time;
++			if (!perfect_time)
++				perfect_time = 1000000;
++			this_thp = dlr * (1000000 / perfect_time);
++			ewma_thp = rate->throughput;
++			if (ewma_thp == 0)
++				rate->throughput = this_thp;
++			else
++				rate->throughput = (ewma_thp + this_thp) >> 1;
++			rate->attempt += rate->this_attempt;
++			rate->success += rate->this_success;
++			rate->fail += rate->this_fail;
++			spinfo->tx_num_xmit = 0;
++			spinfo->tx_num_failed = 0;
++			rate->this_fail = 0;
++			rate->this_success = 0;
++			rate->this_attempt = 0;
++			if (pinfo->oldrate < 0
++			    || pinfo->oldrate >= rc_sta->rc_num_rate) {
++				WARN_ON(1);
++			}
++			if (spinfo->txrate_idx < 0
++			    || spinfo->txrate_idx >= rc_sta->rc_num_rate) {
++				WARN_ON(1);
++			}
++			if (pinfo->oldrate != spinfo->txrate_idx) {
++				i = rinfo[pinfo->oldrate].index;
++				j = rinfo[spinfo->txrate_idx].index;
++				tmp = (pf - spinfo->last_pf);
++				tmp =
++				    RC_PID_DO_ARITH_RIGHT_SHIFT(tmp,
++								rc_table->arith_shift);
++				rinfo[j].diff = rinfo[i].diff + tmp;
++				pinfo->oldrate = spinfo->txrate_idx;
++			}
++			rate_control_pid_normalize(pinfo, rc_sta->rc_num_rate);
++			err_prop =
++			    (rc_table->target_pf - pf) << rc_table->arith_shift;
++			err_avg = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
++			spinfo->err_avg_sc =
++			    spinfo->err_avg_sc - err_avg + err_prop;
++			err_int = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
++			err_der = pf - spinfo->last_pf;
++			spinfo->last_pf = pf;
++			spinfo->last_dlr = dlr;
++			spinfo->oldrate = spinfo->txrate_idx;
++			adj =
++			    (err_prop * RC_PID_COEFF_P +
++			     err_int * RC_PID_COEFF_I +
++			     err_der * RC_PID_COEFF_D);
++			adj =
++			    RC_PID_DO_ARITH_RIGHT_SHIFT(adj,
++							rc_table->arith_shift <<
++							1);
++			if (adj) {
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++				if ((spinfo->txrate_idx != 11)
++				    || ((spinfo->txrate_idx == 11)
++					&& (adj < 0)))
++					pr_debug
++					    ("[RC]Probe adjust[%d] dlr[%d%%] this_thp[%d] ewma_thp[%d] index[%d]\n",
++					     adj, dlr, this_thp, ewma_thp,
++					     spinfo->txrate_idx);
++#endif
++				rate_control_pid_adjust_rate(rc_sta, spinfo,
++							     adj, rinfo);
++			}
++		}
++	} else {
++		if ((spinfo->feedback_probes >= MAXPROBES)
++		    || (spinfo->feedback_probes && spinfo->probe_cnt)) {
++			rate = &pinfo->rinfo[spinfo->txrate_idx];
++			spinfo->last_sample = jiffies;
++			if (rate->this_attempt > 0) {
++				dlr =
++				    100 -
++				    rate->this_fail * 100 / rate->this_attempt;
++#ifdef RATE_CONTROL_DEBUG
++#ifdef PROBE
++				txrate_dlr = dlr;
++#endif
++#endif
++				spinfo->last_dlr = dlr;
++				perfect_time = rate->perfect_tx_time;
++				if (!perfect_time)
++					perfect_time = 1000000;
++				this_thp = dlr * (1000000 / perfect_time);
++				ewma_thp = rate->throughput;
++				if (ewma_thp == 0)
++					rate->throughput = this_thp;
++				else
++					rate->throughput =
++					    (ewma_thp + this_thp) >> 1;
++				rate->attempt += rate->this_attempt;
++				rate->success += rate->this_success;
++				rinfo[spinfo->txrate_idx].fail +=
++				    rate->this_fail;
++				rate->this_fail = 0;
++				rate->this_success = 0;
++				rate->this_attempt = 0;
++			} else {
++#ifdef RATE_CONTROL_DEBUG
++#ifdef PROBE
++				txrate_dlr = 0;
++#endif
++#endif
++			}
++			rate = &pinfo->rinfo[spinfo->tmp_rate_idx];
++			if (rate->this_attempt > 0) {
++				dlr =
++				    100 -
++				    ((rate->this_fail * 100) /
++				     rate->this_attempt);
++				{
++					perfect_time = rate->perfect_tx_time;
++					if (!perfect_time)
++						perfect_time = 1000000;
++					if (dlr)
++						this_thp =
++						    dlr * (1000000 /
++							   perfect_time);
++					else
++						this_thp = 0;
++					ewma_thp = rate->throughput;
++					if (ewma_thp == 0)
++						rate->throughput = this_thp;
++					else
++						rate->throughput =
++						    (ewma_thp + this_thp) >> 1;
++					if (rate->throughput >
++					    pinfo->rinfo[spinfo->
++							 txrate_idx].throughput)
++					{
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++						pr_debug
++						    ("[RC]UPDATE probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
++						     spinfo->tmp_rate_idx,
++						     rate->throughput, dlr,
++						     spinfo->txrate_idx,
++						     pinfo->
++						     rinfo
++						     [spinfo->txrate_idx].throughput,
++						     txrate_dlr,
++						     spinfo->feedback_probes);
++#endif
++						spinfo->txrate_idx =
++						    spinfo->tmp_rate_idx;
++					} else {
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++						pr_debug
++						    ("[RC]Fail probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
++						     spinfo->tmp_rate_idx,
++						     rate->throughput, dlr,
++						     spinfo->txrate_idx,
++						     pinfo->
++						     rinfo
++						     [spinfo->txrate_idx].throughput,
++						     txrate_dlr,
++						     spinfo->feedback_probes);
++#endif
++						;
++					}
++					rate->attempt += rate->this_attempt;
++					rate->success += rate->this_success;
++					rate->fail += rate->this_fail;
++					rate->this_fail = 0;
++					rate->this_success = 0;
++					rate->this_attempt = 0;
++					spinfo->oldrate = spinfo->txrate_idx;
++				}
++			}
++#ifdef RATE_CONTROL_DEBUG
++			else
++				pr_err("Unexpected error\n");
++#endif
++			spinfo->feedback_probes = 0;
++			spinfo->tx_num_xmit = 0;
++			spinfo->tx_num_failed = 0;
++			spinfo->monitoring = 0;
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++			pr_debug("Disable monitor\n");
++#endif
++			spinfo->probe_report_flag = 0;
++			spinfo->probe_wating_times = 0;
++		} else {
++			spinfo->probe_wating_times++;
++#ifdef RATE_CONTROL_DEBUG
++			if (spinfo->probe_wating_times > 3) {
++				pr_debug
++				    ("[RC]@@@@@ PROBE LOSE @@@@@ feedback=[%d] need=[%d] probe_cnt=[%d] wating times[%d]\n",
++				     spinfo->feedback_probes, MAXPROBES,
++				     spinfo->probe_cnt,
++				     spinfo->probe_wating_times);
++				spinfo->feedback_probes = 0;
++				spinfo->tx_num_xmit = 0;
++				spinfo->tx_num_failed = 0;
++				spinfo->monitoring = 0;
++				spinfo->probe_report_flag = 0;
++				spinfo->probe_wating_times = 0;
++			}
++#else
++			if (spinfo->probe_wating_times > 3) {
++				spinfo->feedback_probes = 0;
++				spinfo->tx_num_xmit = 0;
++				spinfo->tx_num_failed = 0;
++				spinfo->monitoring = 0;
++				spinfo->probe_report_flag = 0;
++				spinfo->probe_wating_times = 0;
++			}
++#endif
++		}
++	}
++}
++
++#ifdef RATE_CONTROL_PERCENTAGE_TRACE
++int percentage = 0;
++int percentageCounter = 0;
++#endif
++void ssv6xxx_legacy_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
++				   struct ssv_sta_rc_info *rc_sta)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct cfg_host_event *host_event;
++	struct firmware_rate_control_report_data *report_data;
++	struct rc_pid_info *pinfo;
++	struct rc_pid_sta_info *spinfo;
++	struct rc_pid_rateinfo *pidrate;
++	struct rc_pid_rateinfo *rate;
++	s32 report_data_index = 0;
++	unsigned long period;
++	host_event = (struct cfg_host_event *)skb->data;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
++	if ((report_data->wsid != (-1))
++	    && sc->sta_info[report_data->wsid].sta == NULL) {
++		dev_warn(sc->dev, "RC report has no valid STA.(%d)\n",
++			 report_data->wsid);
++		return;
++	}
++	pinfo = &rc_sta->pinfo;
++	spinfo = &rc_sta->spinfo;
++	pidrate = rc_sta->pinfo.rinfo;
++	if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
++		period = msecs_to_jiffies(HT_RC_UPDATE_INTERVAL);
++		if (time_after(jiffies, spinfo->last_sample + period)) {
++			if (rc_sta->rc_num_rate == 12)
++				spinfo->txrate_idx = rc_sta->ht.max_tp_rate + 4;
++			else
++				spinfo->txrate_idx = rc_sta->ht.max_tp_rate;
++#ifdef RATE_CONTROL_DEBUG
++			pr_debug("MPDU rate update time txrate_idx[%d]!!\n",
++			       spinfo->txrate_idx);
++#endif
++			spinfo->last_sample = jiffies;
++		}
++		return;
++	} else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
++		;
++	} else {
++		dev_warn(sc->dev, "RC report handler got garbage\n");
++		return;
++	}
++	if (report_data->rates[0].data_rate < 7) {
++		if (report_data->rates[0].data_rate > 3) {
++			report_data->rates[0].data_rate -= 3;
++		}
++	}
++	if (ssv_rc->
++	    rc_table[rc_sta->pinfo.rinfo[spinfo->txrate_idx].
++		     rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
++		report_data_index =
++		    rc_sta->pinfo.rinfo[spinfo->txrate_idx].index;
++	} else
++	    if (ssv_rc->rc_table
++		[rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].
++		 rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
++		report_data_index =
++		    rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].index;
++	}
++	if ((report_data_index != spinfo->tmp_rate_idx)
++	    && (report_data_index != spinfo->txrate_idx)) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg
++		    (sc->dev, "Rate control report mismatch report_rate_idx[%d] tmp_rate_idx[%d]rate[%d] txrate_idx[%d]rate[%d]!!\n",
++		     report_data->rates[0].data_rate, spinfo->tmp_rate_idx,
++		     ssv_rc->rc_table[rc_sta->pinfo.
++				      rinfo[spinfo->tmp_rate_idx].rc_index].
++		     hw_rate_idx, spinfo->txrate_idx,
++		     ssv_rc->rc_table[rc_sta->pinfo.
++				      rinfo[spinfo->txrate_idx].rc_index].
++		     hw_rate_idx);
++#endif
++		return;
++	}
++	if (report_data_index == spinfo->txrate_idx) {
++		spinfo->tx_num_xmit += report_data->rates[0].count;
++		spinfo->tx_num_failed +=
++		    (report_data->rates[0].count - report_data->ampdu_ack_len);
++		rate = &pidrate[spinfo->txrate_idx];
++		rate->this_fail +=
++		    (report_data->rates[0].count - report_data->ampdu_ack_len);
++		rate->this_attempt += report_data->rates[0].count;
++		rate->this_success += report_data->ampdu_ack_len;
++	}
++	if (report_data_index != spinfo->txrate_idx
++	    && report_data_index == spinfo->tmp_rate_idx) {
++		spinfo->feedback_probes += report_data->ampdu_len;
++		rate = &pidrate[spinfo->tmp_rate_idx];
++		rate->this_fail +=
++		    (report_data->rates[0].count - report_data->ampdu_ack_len);
++		rate->this_attempt += report_data->rates[0].count;
++		rate->this_success += report_data->ampdu_ack_len;
++	}
++	period = msecs_to_jiffies(RC_PID_INTERVAL);
++	if (time_after(jiffies, spinfo->last_sample + period)) {
++#ifdef RATE_CONTROL_PERCENTAGE_TRACE
++		rate = &pidrate[spinfo->txrate_idx];
++		if (rate->this_success > rate->this_attempt) {
++			dev_dbg(sc->dev, "this_success[%ld] this_attempt[%ld]\n",
++			       rate->this_success, rate->this_attempt);
++		} else {
++			if (percentage == 0)
++				percentage =
++				    (int)((rate->this_success * 100) /
++					  rate->this_attempt);
++			else
++				percentage =
++				    (percentage +
++				     (int)((rate->this_success * 100) /
++					   rate->this_attempt)) / 2;
++			deb_dbg(sc->dev, "Percentage[%d]\n", percentage);
++			if ((percentageCounter % 16) == 1)
++				percentage = 0;
++		}
++#endif
++#ifdef RATE_CONTROL_STUPID_DEBUG
++		if (spinfo->txrate_idx != spinfo->tmp_rate_idx) {
++			rate = &pidrate[spinfo->tmp_rate_idx];
++			if (spinfo->monitoring && ((rate->this_attempt == 0)
++						   || (rate->this_attempt !=
++						       MAXPROBES))) {
++				dev_dbg(sc->dev, "Probe result a[%ld]s[%ld]f[%ld]",
++				       rate->this_attempt, rate->this_success,
++				       rate->this_fail);
++			}
++			rate = &pidrate[spinfo->txrate_idx];
++			dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
++			       rate->this_success, rate->this_fail);
++		} else {
++			rate = &pidrate[spinfo->txrate_idx];
++			dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
++			       rate->this_success, rate->this_fail);
++		}
++		dev_dbg(sc->dev, "w[%d]x%03d-f%03d\n", rc_sta->rc_wsid,
++		       spinfo->tx_num_xmit, spinfo->tx_num_failed);
++#endif
++		rate_control_pid_sample(sc->rc, pinfo, rc_sta, spinfo);
++	}
++}
++
++void ssv6xxx_sample_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, rc_sample_work);
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct sk_buff *skb;
++	struct cfg_host_event *host_event;
++	struct ssv_sta_rc_info *rc_sta = NULL;
++	struct firmware_rate_control_report_data *report_data;
++	struct ssv_sta_info *ssv_sta;
++	u8 hw_wsid = 0;
++	sc->rc_sample_sechedule = 1;
++	while (1) {
++		skb = skb_dequeue(&sc->rc_report_queue);
++		if (skb == NULL)
++			break;
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++		{
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++#endif
++		host_event = (struct cfg_host_event *)skb->data;
++		if ((host_event->h_event == SOC_EVT_RC_AMPDU_REPORT)
++		    || (host_event->h_event == SOC_EVT_RC_MPDU_REPORT)) {
++			report_data =
++			    (struct firmware_rate_control_report_data *)
++			    &host_event->dat[0];
++			hw_wsid = report_data->wsid;
++		} else {
++			dev_warn(sc->dev, "rate control sampling got garbage\n");
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		if (hw_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
++#ifdef RATE_CONTROL_DEBUG
++			dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-0!!\n");
++#endif
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		ssv_sta = &sc->sta_info[hw_wsid];
++		if (ssv_sta->sta == NULL) {
++			dev_err(sc->dev, "Null STA %d for RC report.\n",
++				hw_wsid);
++			rc_sta = NULL;
++		} else {
++			struct ssv_sta_priv_data *ssv_sta_priv =
++			    (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv;
++			rc_sta = &ssv_rc->sta_rc_info[ssv_sta_priv->rc_idx];
++			if (rc_sta->rc_wsid != hw_wsid) {
++				rc_sta = NULL;
++			}
++		}
++		if (rc_sta == NULL) {
++			dev_err(sc->dev,
++				"[RC]rc_sta is NULL pointer Check-1!!\n");
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		if (rc_sta == NULL) {
++#ifdef RATE_CONTROL_DEBUG
++			dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-2!!\n");
++#endif
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		if (rc_sta->is_ht) {
++			ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
++			ssv6xxx_ht_report_handler(sc, skb, rc_sta);
++		} else
++			ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
++		dev_kfree_skb_any(skb);
++	}
++	sc->rc_sample_sechedule = 0;
++}
++
++static void ssv6xxx_tx_status(void *priv,
++			      struct ieee80211_supported_band *sband,
++			      struct ieee80211_sta *sta, void *priv_sta,
++			      struct sk_buff *skb)
++{
++	struct ssv_softc *sc;
++	struct ieee80211_hdr *hdr;
++	__le16 fc;
++	hdr = (struct ieee80211_hdr *)skb->data;
++	fc = hdr->frame_control;
++	if (!priv_sta || !ieee80211_is_data_qos(fc))
++		return;
++	sc = (struct ssv_softc *)priv;
++	if (conf_is_ht(&sc->hw->conf)
++	    && (!(skb->protocol == cpu_to_be16(ETH_P_PAE)))) {
++		if (skb_get_queue_mapping(skb) != IEEE80211_AC_VO)
++			ssv6200_ampdu_tx_update_state(priv, sta, skb);
++	}
++	return;
++}
++
++static void rateControlGetRate(u8 rateIndex, char *pointer)
++{
++	switch (rateIndex) {
++	case 0:
++		sprintf(pointer, "1Mbps");
++		return;
++	case 1:
++	case 4:
++		sprintf(pointer, "2Mbps");
++		return;
++	case 2:
++	case 5:
++		sprintf(pointer, "5.5Mbps");
++		return;
++	case 3:
++	case 6:
++		sprintf(pointer, "11Mbps");
++		return;
++	case 7:
++		sprintf(pointer, "6Mbps");
++		return;
++	case 8:
++		sprintf(pointer, "9Mbps");
++		return;
++	case 9:
++		sprintf(pointer, "12Mbps");
++		return;
++	case 10:
++		sprintf(pointer, "18Mbps");
++		return;
++	case 11:
++		sprintf(pointer, "24Mbps");
++		return;
++	case 12:
++		sprintf(pointer, "36Mbps");
++		return;
++	case 13:
++		sprintf(pointer, "48Mbps");
++		return;
++	case 14:
++		sprintf(pointer, "54Mbps");
++		return;
++	case 15:
++	case 31:
++		sprintf(pointer, "MCS0-l");
++		return;
++	case 16:
++	case 32:
++		sprintf(pointer, "MCS1-l");
++		return;
++	case 17:
++	case 33:
++		sprintf(pointer, "MCS2-l");
++		return;
++	case 18:
++	case 34:
++		sprintf(pointer, "MCS3-l");
++		return;
++	case 19:
++	case 35:
++		sprintf(pointer, "MCS4-l");
++		return;
++	case 20:
++	case 36:
++		sprintf(pointer, "MCS5-l");
++		return;
++	case 21:
++	case 37:
++		sprintf(pointer, "MCS6-l");
++		return;
++	case 22:
++	case 38:
++		sprintf(pointer, "MCS7-l");
++		return;
++	case 23:
++		sprintf(pointer, "MCS0-s");
++		return;
++	case 24:
++		sprintf(pointer, "MCS1-s");
++		return;
++	case 25:
++		sprintf(pointer, "MCS2-s");
++		return;
++	case 26:
++		sprintf(pointer, "MCS3-s");
++		return;
++	case 27:
++		sprintf(pointer, "MCS4-s");
++		return;
++	case 28:
++		sprintf(pointer, "MCS5-s");
++		return;
++	case 29:
++		sprintf(pointer, "MCS6-s");
++		return;
++	case 30:
++		sprintf(pointer, "MCS7-s");
++		return;
++	default:
++		sprintf(pointer, "Unknow");
++		return;
++	};
++}
++
++static void ssv6xxx_get_rate(void *priv, struct ieee80211_sta *sta,
++			     void *priv_sta,
++			     struct ieee80211_tx_rate_control *txrc)
++{
++	struct ssv_softc *sc = priv;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ssv_sta_rc_info *rc_sta = priv_sta;
++	struct sk_buff *skb = txrc->skb;
++	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_tx_rate *rates = tx_info->control.rates;
++	struct rc_pid_sta_info *spinfo = &rc_sta->spinfo;
++	struct ssv_rc_rate *rc_rate = NULL;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	int rateidx = 99;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0)
++	if (rate_control_send_low(sta, priv_sta, txrc)) {
++		int i = 0;
++		int total_rates =
++		    (sizeof(ssv_11bgn_rate_table) /
++		     sizeof(ssv_11bgn_rate_table[0]));
++#if 1
++		if ((txrc->rate_idx_mask & (1 << rates[0].idx)) == 0) {
++			u32 rate_idx = rates[0].idx + 1;
++			u32 rate_idx_mask = txrc->rate_idx_mask >> rate_idx;
++			while (rate_idx_mask && (rate_idx_mask & 1) == 0) {
++				rate_idx_mask >>= 1;
++				rate_idx++;
++			}
++			if (rate_idx_mask)
++				rates[0].idx = rate_idx;
++			else {
++				WARN_ON(rate_idx_mask == 0);
++			}
++		}
++#endif
++		for (i = 0; i < total_rates; i++) {
++			if (rates[0].idx ==
++			    ssv_11bgn_rate_table[i].dot11_rate_idx) {
++				break;
++			}
++		}
++		if (i < total_rates)
++			rc_rate = &ssv_rc->rc_table[i];
++		else {
++			WARN_ON("Failed to find matching low rate.");
++		}
++	}
++#endif
++	if (rc_rate == NULL) {
++		if (conf_is_ht(&sc->hw->conf) &&
++		    (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
++			tx_info->flags |= IEEE80211_TX_CTL_LDPC;
++		if (conf_is_ht(&sc->hw->conf) &&
++		    (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_TX_STBC))
++			tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT);
++		if (sc->sc_flags & SC_OP_FIXED_RATE) {
++			rateidx = sc->max_rate_idx;
++		} else {
++			if (rc_sta->rc_valid == false) {
++				rateidx = 0;
++			} else {
++				if ((rc_sta->rc_wsid >=
++				     SSV_RC_MAX_HARDWARE_SUPPORT)
++				    || (rc_sta->rc_wsid < 0)) {
++					ssv_sta_priv =
++					    (struct ssv_sta_priv_data *)
++					    sta->drv_priv;
++					{
++						if ((rc_sta->ht_rc_type >=
++						     RC_TYPE_HT_SGI_20)
++						    &&
++						    (ssv_sta_priv->rx_data_rate
++						     <
++						     SSV62XX_RATE_MCS_INDEX)) {
++							rateidx =
++							    rc_sta->
++							    pinfo.rinfo
++							    [spinfo->txrate_idx].rc_index;
++						} else {
++							rateidx =
++							    ssv_sta_priv->rx_data_rate;
++						}
++					}
++				} else {
++					if (rc_sta->is_ht) {
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++						rateidx =
++						    rc_sta->ht.
++						    groups.rates[MCS_GROUP_RATES
++								 - 1].rc_index;
++#else
++						rateidx =
++						    rc_sta->pinfo.
++						    rinfo
++						    [spinfo->txrate_idx].rc_index;
++#endif
++					} else {
++						{
++							BUG_ON
++							    (spinfo->txrate_idx
++							     >=
++							     rc_sta->rc_num_rate);
++							rateidx =
++							    rc_sta->
++							    pinfo.rinfo
++							    [spinfo->txrate_idx].rc_index;
++						}
++						if (rateidx < 4) {
++							if (rateidx) {
++								if ((sc->sc_flags & SC_OP_SHORT_PREAMBLE)
++								    ||
++								    (txrc->short_preamble))
++								{
++									rateidx
++									    +=
++									    3;
++								}
++							}
++						}
++					}
++				}
++			}
++		}
++		rc_rate = &ssv_rc->rc_table[rateidx];
++		if (spinfo->real_hw_index != rc_rate->hw_rate_idx) {
++			char string[24];
++			rateControlGetRate(rc_rate->hw_rate_idx, string);
++		}
++		spinfo->real_hw_index = rc_rate->hw_rate_idx;
++		rates[0].count = 4;
++		rates[0].idx = rc_rate->dot11_rate_idx;
++		tx_info->control.rts_cts_rate_idx =
++		    ssv_rc->rc_table[rc_rate->ctrl_rate_idx].dot11_rate_idx;
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
++		if (rc_rate->rc_flags & RC_FLAG_HT) {
++			rates[0].flags |= IEEE80211_TX_RC_MCS;
++			if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++				rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
++			if (rc_rate->rc_flags & RC_FLAG_HT_GF)
++				rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
++		}
++	}
++	rates[1].count = 0;
++	rates[1].idx = -1;
++	rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
++	rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
++	rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
++}
++
++int pide_frame_duration(size_t len, int rate, int short_preamble, int flags)
++{
++	int dur = 0;
++	if (flags == WLAN_RC_PHY_CCK) {
++		dur = 10;
++		dur += short_preamble ? (72 + 24) : (144 + 48);
++		dur += DIV_ROUND_UP(8 * (len + 4) * 10, rate);
++	} else {
++		dur = 16;
++		dur += 16;
++		dur += 4;
++		dur += 4 * DIV_ROUND_UP((16 + 8 * (len + 4) + 6) * 10,
++					4 * rate);
++	}
++	return dur;
++}
++
++static void ssv62xx_rc_caps(struct ssv_sta_rc_info *rc_sta)
++{
++	struct rc_pid_sta_info *spinfo;
++	struct rc_pid_info *pinfo;
++	struct rc_pid_rateinfo *rinfo;
++	int i;
++	spinfo = &rc_sta->spinfo;
++	pinfo = &rc_sta->pinfo;
++	memset(spinfo, 0, sizeof(struct rc_pid_sta_info));
++	memset(pinfo, 0, sizeof(struct rc_pid_info));
++	rinfo = rc_sta->pinfo.rinfo;
++	for (i = 0; i < rc_sta->rc_num_rate; i++) {
++		rinfo[i].rc_index = ssv6xxx_rc_rate_set[rc_sta->rc_type][i + 1];
++		rinfo[i].diff = i * RC_PID_NORM_OFFSET;
++		rinfo[i].index = (u16) i;
++		rinfo[i].perfect_tx_time =
++		    TDIFS + (TSLOT * 15 >> 1) + pide_frame_duration(1530,
++								    ssv_11bgn_rate_table
++								    [rinfo
++								     [i].rc_index].rate_kbps
++								    / 100, 1,
++								    ssv_11bgn_rate_table
++								    [rinfo
++								     [i].rc_index].phy_type)
++		    + pide_frame_duration(10,
++					  ssv_11bgn_rate_table[rinfo[i].
++							       rc_index].rate_kbps
++					  / 100, 1,
++					  ssv_11bgn_rate_table[rinfo[i].
++							       rc_index].phy_type);
++		pr_debug("[RC]Init perfect_tx_time[%d][%d]\n", i,
++		       rinfo[i].perfect_tx_time);
++		rinfo[i].throughput = 0;
++	}
++	if (rc_sta->is_ht) {
++		if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0] == 12)
++			spinfo->txrate_idx = 4;
++		else
++			spinfo->txrate_idx = 0;
++	} else {
++		spinfo->txrate_idx = ssv6xxx_rate_lowest_index(rc_sta);
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++		spinfo->txrate_idx = ssv6xxx_rate_highest_index(rc_sta);
++#endif
++	}
++	spinfo->real_hw_index = 0;
++	spinfo->probe_cnt = MAXPROBES;
++	spinfo->tmp_rate_idx = spinfo->txrate_idx;
++	spinfo->oldrate = spinfo->txrate_idx;
++	spinfo->last_sample = jiffies;
++	spinfo->last_report = jiffies;
++}
++
++static void ssv6xxx_rate_update_rc_type(void *priv,
++					struct ieee80211_supported_band *sband,
++					struct ieee80211_sta *sta,
++					void *priv_sta)
++{
++	struct ssv_softc *sc = priv;
++	struct ssv_hw *sh = sc->sh;
++	struct ssv_sta_rc_info *rc_sta = priv_sta;
++	int i;
++	u32 ht_supp_rates = 0;
++	BUG_ON(rc_sta->rc_valid == false);
++	dev_dbg(sc->dev, "[I] %s(): \n", __FUNCTION__);
++	rc_sta->ht_supp_rates = 0;
++	rc_sta->rc_supp_rates = 0;
++	rc_sta->is_ht = 0;
++#ifndef CONFIG_CH14_SUPPORT_GN_MODE
++	if (sc->cur_channel->hw_value == 14) {
++		dev_dbg(sc->dev, "[RC init ]Channel 14 support\n");
++		if ((sta->deflink.supp_rates[sband->band] & (~0xfL)) == 0x0) {
++			dev_dbg(sc->dev, "[RC init ]B only mode\n");
++			rc_sta->rc_type = RC_TYPE_B_ONLY;
++		} else {
++			dev_dbg(sc->dev, "[RC init ]GB mode\n");
++			rc_sta->rc_type = RC_TYPE_LEGACY_GB;
++		}
++	} else
++#endif
++	if (sta->deflink.ht_cap.ht_supported == true) {
++		dev_dbg(sc->dev, "[RC init ]HT support wsid\n");
++		for (i = 0; i < SSV_HT_RATE_MAX; i++) {
++			if (sta->deflink.ht_cap.mcs.rx_mask[i /
++						    MCS_GROUP_RATES] & (1 << (i
++									      %
++									      MCS_GROUP_RATES)))
++				ht_supp_rates |= BIT(i);
++		}
++		rc_sta->ht_supp_rates = ht_supp_rates;
++		if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD) {
++			rc_sta->rc_type = RC_TYPE_HT_GF;
++			rc_sta->ht_rc_type = RC_TYPE_HT_GF;
++		} else if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) {
++			rc_sta->rc_type = RC_TYPE_SGI_20;
++			rc_sta->ht_rc_type = RC_TYPE_HT_SGI_20;
++		} else {
++			rc_sta->rc_type = RC_TYPE_LGI_20;
++			rc_sta->ht_rc_type = RC_TYPE_HT_LGI_20;
++		}
++	} else {
++		if ((sta->deflink.supp_rates[sband->band] & (~0xfL)) == 0x0) {
++			rc_sta->rc_type = RC_TYPE_B_ONLY;
++			dev_dbg(sc->dev, "[RC init ]B only mode\n");
++		} else {
++			rc_sta->rc_type = RC_TYPE_LEGACY_GB;
++			dev_dbg(sc->dev, "[RC init ]legacy G mode\n");
++		}
++	}
++#ifdef CONFIG_SSV_DPD
++	if (rc_sta->rc_type == RC_TYPE_B_ONLY) {
++		SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3D3E84FE);
++		SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x1457D79);
++		SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x0);
++	} else {
++		SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3CBE84FE);
++		SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x4507F9);
++		SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x3);
++	}
++#endif
++	if ((rc_sta->rc_type != RC_TYPE_B_ONLY)
++	    && (rc_sta->rc_type != RC_TYPE_LEGACY_GB)) {
++		if ((sta->deflink.ht_cap.ht_supported)
++		    && (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)) {
++			rc_sta->is_ht = 1;
++			ssv62xx_ht_rc_caps(ssv6xxx_rc_rate_set, rc_sta);
++		}
++	}
++	{
++		rc_sta->rc_num_rate =
++		    (u8) ssv6xxx_rc_rate_set[rc_sta->rc_type][0];
++		if ((rc_sta->rc_type == RC_TYPE_HT_GF)
++		    || (rc_sta->rc_type == RC_TYPE_LGI_20)
++		    || (rc_sta->rc_type == RC_TYPE_SGI_20)) {
++			if (rc_sta->rc_num_rate == 12) {
++				rc_sta->rc_supp_rates =
++				    sta->deflink.supp_rates[sband->band] & 0xfL;
++				rc_sta->rc_supp_rates |= (ht_supp_rates << 4);
++			} else
++				rc_sta->rc_supp_rates = ht_supp_rates;
++		} else if (rc_sta->rc_type == RC_TYPE_LEGACY_GB)
++			rc_sta->rc_supp_rates = sta->deflink.supp_rates[sband->band];
++		else if (rc_sta->rc_type == RC_TYPE_B_ONLY)
++			rc_sta->rc_supp_rates =
++			    sta->deflink.supp_rates[sband->band] & 0xfL;
++		ssv62xx_rc_caps(rc_sta);
++	}
++}
++
++static void ssv6xxx_rate_update(void *priv,
++				struct ieee80211_supported_band *sband,
++				struct cfg80211_chan_def *chandef,
++				struct ieee80211_sta *sta, void *priv_sta,
++				u32 changed)
++{
++	pr_debug("%s: changed=%d\n", __FUNCTION__, changed);
++	return;
++}
++
++static void ssv6xxx_rate_init(void *priv,
++			      struct ieee80211_supported_band *sband,
++			      struct cfg80211_chan_def *chandef,
++			      struct ieee80211_sta *sta, void *priv_sta)
++{
++	ssv6xxx_rate_update_rc_type(priv, sband, sta, priv_sta);
++}
++
++static void *ssv6xxx_rate_alloc_sta(void *priv, struct ieee80211_sta *sta,
++				    gfp_t gfp)
++{
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++#ifndef RC_STA_DIRECT_MAP
++	struct ssv_softc *sc = priv;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	int s;
++	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	for (s = 0; s < SSV_RC_MAX_STA; s++) {
++		if (ssv_rc->sta_rc_info[s].rc_valid == false) {
++			dev_dbg(sc->dev, "%s(): use index %d\n", __FUNCTION__, s);
++			memset(&ssv_rc->sta_rc_info[s], 0,
++			       sizeof(struct ssv_sta_rc_info));
++			ssv_rc->sta_rc_info[s].rc_valid = true;
++			ssv_rc->sta_rc_info[s].rc_wsid = -1;
++			sta_priv->rc_idx = s;
++			return &ssv_rc->sta_rc_info[s];
++		}
++	}
++	return NULL;
++#else
++	sta_priv->rc_idx = (-1);
++	return sta_priv;
++#endif
++}
++
++static void ssv6xxx_rate_free_sta(void *priv, struct ieee80211_sta *sta,
++				  void *priv_sta)
++{
++	struct ssv_sta_rc_info *rc_sta = priv_sta;
++	rc_sta->rc_valid = false;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
++static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw)
++#else
++static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw,
++				struct dentry *debugfsdir)
++#endif
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_rate_ctrl *ssv_rc;
++	sc->rc = kzalloc(sizeof(struct ssv_rate_ctrl), GFP_KERNEL);
++	if (!sc->rc) {
++		pr_err("%s(): Unable to allocate RC structure !\n",
++		       __FUNCTION__);
++		return NULL;
++	}
++	memset(sc->rc, 0, sizeof(struct ssv_rate_ctrl));
++	ssv_rc = (struct ssv_rate_ctrl *)sc->rc;
++	ssv_rc->rc_table = ssv_11bgn_rate_table;
++	skb_queue_head_init(&sc->rc_report_queue);
++	INIT_WORK(&sc->rc_sample_work, ssv6xxx_sample_work);
++	sc->rc_sample_workqueue = create_workqueue("ssv6xxx_rc_sample");
++	sc->rc_sample_sechedule = 0;
++	return hw->priv;
++}
++
++static void ssv6xxx_rate_free(void *priv)
++{
++	struct ssv_softc *sc = priv;
++	if (sc->rc) {
++		kfree(sc->rc);
++		sc->rc = NULL;
++	}
++	sc->rc_sample_sechedule = 0;
++	cancel_work_sync(&sc->rc_sample_work);
++	flush_workqueue(sc->rc_sample_workqueue);
++	destroy_workqueue(sc->rc_sample_workqueue);
++}
++
++static struct rate_control_ops ssv_rate_ops = {
++	.name = "ssv6xxx_rate_control",
++	.tx_status = ssv6xxx_tx_status,
++	.get_rate = ssv6xxx_get_rate,
++	.rate_init = ssv6xxx_rate_init,
++	.rate_update = ssv6xxx_rate_update,
++	.alloc = ssv6xxx_rate_alloc,
++	.free = ssv6xxx_rate_free,
++	.alloc_sta = ssv6xxx_rate_alloc_sta,
++	.free_sta = ssv6xxx_rate_free_sta,
++};
++
++void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc,
++				 int hw_rate_idx,
++				 struct ieee80211_rx_status *rxs)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ssv_rc_rate *rc_rate;
++	BUG_ON(hw_rate_idx >= RATE_TABLE_SIZE && hw_rate_idx < 0);
++	rc_rate = &ssv_rc->rc_table[hw_rate_idx];
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)
++	if (rc_rate->rc_flags & RC_FLAG_HT) {
++		// rxs->flag |= RC_FLAG_HT;
++		if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++			rxs->enc_flags |= RX_ENC_FLAG_SHORT_GI;
++	} else {
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rxs->enc_flags |= RX_ENC_FLAG_SHORTPRE;
++	}
++#else
++	if (rc_rate->rc_flags & RC_FLAG_HT) {
++		rxs->flag |= RC_FLAG_HT;
++		if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++			rxs->flag |= RX_FLAG_SHORT_GI;
++	} else {
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rxs->flag |= RX_FLAG_SHORTPRE;
++	}
++#endif
++	rxs->rate_idx = rc_rate->dot11_rate_idx;
++}
++
++void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
++			    struct ieee80211_tx_info *info,
++			    struct ssv_rate_info *sr)
++{
++	struct ieee80211_tx_rate *tx_rate;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	tx_rate = &info->control.rates[0];
++	sr->d_flags =
++	    (ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].phy_type ==
++	     WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
++	sr->d_flags |=
++	    (ssv_rc->
++	     rc_table[tx_rate[SSV_DRATE_IDX].
++		      count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
++	    IEEE80211_RATE_SHORT_PREAMBLE : 0;
++	sr->c_flags =
++	    (ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].phy_type ==
++	     WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
++	sr->c_flags |=
++	    (ssv_rc->
++	     rc_table[tx_rate[SSV_CRATE_IDX].
++		      count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
++	    IEEE80211_RATE_SHORT_PREAMBLE : 0;
++	sr->drate_kbps =
++	    ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].rate_kbps;
++	sr->drate_hw_idx = tx_rate[SSV_DRATE_IDX].count;
++	sr->crate_kbps =
++	    ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].rate_kbps;
++	sr->crate_hw_idx = tx_rate[SSV_CRATE_IDX].count;
++}
++
++u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
++				   u32 do_rts_cts)
++{
++	int ret = 0;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++	struct ieee80211_sta *sta = skb_info->sta;
++	struct ieee80211_tx_rate *rates = &tx_info->control.rates[0];
++	struct ssv_rc_rate *rc_rate = NULL;
++	u8 rateidx = 0;
++	struct ssv_sta_rc_info *rc_sta = NULL;
++	struct rc_pid_sta_info *spinfo;
++	struct ssv_sta_priv_data *sta_priv = NULL;
++	unsigned long period = 0;
++	if (sc->sc_flags & SC_OP_FIXED_RATE)
++		return ret;
++	if (sta == NULL)
++		return ret;
++	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	if (sta_priv == NULL) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg(rc->dev, "%s sta_priv == NULL \n\r", __FUNCTION__);
++#endif
++		return ret;
++	}
++	if ((sta_priv->rc_idx < 0) || (sta_priv->rc_idx >= SSV_RC_MAX_STA)) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg(sc->dev, "%s rc_idx %x illegal \n\r", __FUNCTION__,
++		       sta_priv->rc_idx);
++#endif
++		return ret;
++	}
++	rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
++	if (rc_sta->rc_valid == false) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg(sc->dev, "%s rc_valid false \n\r", __FUNCTION__);
++#endif
++		return ret;
++	}
++	spinfo = &rc_sta->spinfo;
++	period = msecs_to_jiffies(RC_PID_REPORT_INTERVAL);
++	if (time_after(jiffies, spinfo->last_report + period)) {
++		ret |= RC_FIRMWARE_REPORT_FLAG;
++		spinfo->last_report = jiffies;
++	}
++	{
++		if (spinfo->monitoring) {
++			if (spinfo->probe_report_flag == 0) {
++				ret |= RC_FIRMWARE_REPORT_FLAG;
++				spinfo->last_report = jiffies;
++				spinfo->probe_report_flag = 1;
++				rateidx = spinfo->real_hw_index;
++			} else if (spinfo->probe_cnt > 0
++				   && spinfo->probe_report_flag) {
++				rateidx =
++				    rc_sta->pinfo.rinfo[spinfo->
++							tmp_rate_idx].rc_index;
++				spinfo->probe_cnt--;
++				if (spinfo->probe_cnt == 0) {
++					ret |= RC_FIRMWARE_REPORT_FLAG;
++					spinfo->last_report = jiffies;
++				}
++			} else
++				rateidx = spinfo->real_hw_index;
++		} else
++			rateidx = spinfo->real_hw_index;
++	}
++	if (rateidx >= RATE_TABLE_SIZE) {
++		dev_err(sc->dev, "rateidx over range\n");
++		return 0;
++	}
++	rc_rate = &ssv_rc->rc_table[rateidx];
++#ifdef RATE_CONTROL_STUPID_DEBUG
++	if (spinfo->monitoring && (spinfo->probe_cnt)) {
++		char string[24];
++		rateControlGetRate(rc_rate->hw_rate_idx, string);
++		dev_dbg(sc->dev, "[RC]Probe rate[%s]\n", string);
++	}
++#endif
++	if (rc_rate == NULL)
++		return ret;
++	if (rc_rate->hw_rate_idx != rates[SSV_DRATE_IDX].count) {
++		rates[0].flags = 0;
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
++		if (rc_rate->rc_flags & RC_FLAG_HT) {
++			rates[0].flags |= IEEE80211_TX_RC_MCS;
++			if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++				rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
++			if (rc_rate->rc_flags & RC_FLAG_HT_GF)
++				rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
++		}
++		rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
++		if (do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
++			rates[SSV_CRATE_IDX].count = 0;
++		} else {
++			rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
++			rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
++		}
++		ret |= 0x1;
++	}
++	return ret;
++}
++
++void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ssv_sta_rc_info *rc_sta;
++	u32 rc_hw_reg[] = { ADR_MTX_MIB_WSID0, ADR_MTX_MIB_WSID1 };
++	BUG_ON(rc_idx >= SSV_RC_MAX_STA);
++	rc_sta = &ssv_rc->sta_rc_info[rc_idx];
++	if (hwidx >= 0 && hwidx < SSV_NUM_HW_STA) {
++		rc_sta->rc_wsid = hwidx;
++		dev_dbg(sc->dev, "rc_wsid[%d] rc_idx[%d]\n", rc_sta[rc_idx].rc_wsid,
++		       rc_idx);
++		SMAC_REG_WRITE(sc->sh, rc_hw_reg[hwidx], 0x40000000);
++	} else {
++		rc_sta->rc_wsid = -1;
++	}
++}
++
++#define UPDATE_PHY_INFO_ACK_RATE(_phy_info,_ack_rate_idx) ( _phy_info = (_phy_info&0xfffffc0f)|(_ack_rate_idx<<4))
++int ssv6xxx_rc_update_bmode_ctrl_rate(struct ssv_softc *sc, int rate_tbl_idx,
++				      int ctrl_rate_idx)
++{
++	u32 temp32;
++	struct ssv_hw *sh = sc->sh;
++	u32 addr;
++	addr = sh->hw_pinfo + rate_tbl_idx * 4;
++	ssv_11bgn_rate_table[rate_tbl_idx].ctrl_rate_idx = ctrl_rate_idx;
++	SMAC_REG_READ(sh, addr, &temp32);
++	UPDATE_PHY_INFO_ACK_RATE(temp32, ctrl_rate_idx);
++	SMAC_REG_WRITE(sh, addr, temp32);
++	SMAC_REG_CONFIRM(sh, addr, temp32);
++	return 0;
++}
++
++void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates)
++{
++	int i;
++	int rate_idx, pre_rate_idx = 0;
++	for (i = 0; i < 4; i++) {
++		if (((basic_rates >> i) & 0x01)) {
++			rate_idx = i;
++			pre_rate_idx = i;
++		} else
++			rate_idx = pre_rate_idx;
++		ssv6xxx_rc_update_bmode_ctrl_rate(sc, i, rate_idx);
++		if (i)
++			ssv6xxx_rc_update_bmode_ctrl_rate(sc, i + 3, rate_idx);
++	}
++}
++
++int ssv6xxx_rate_control_register(void)
++{
++	return ieee80211_rate_control_register(&ssv_rate_ops);
++}
++
++void ssv6xxx_rate_control_unregister(void)
++{
++	ieee80211_rate_control_unregister(&ssv_rate_ops);
++}
++
++void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
++				u32 rate_index)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_sta *sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
++	if (sta == NULL) {
++		return;
++	}
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ssv_sta_priv->rx_data_rate = rate_index;
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
+new file mode 100644
+index 000000000000..911c182897fa
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
+@@ -0,0 +1,50 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_RC_H_
++#define _SSV_RC_H_
++#include "ssv_rc_common.h"
++#define RC_PID_REPORT_INTERVAL 40
++#define RC_PID_INTERVAL 125
++#define RC_PID_DO_ARITH_RIGHT_SHIFT(x,y) \
++ ((x) < 0 ? -((-(x)) >> (y)) : (x) >> (y))
++#define RC_PID_NORM_OFFSET 3
++#define RC_PID_SMOOTHING_SHIFT 1
++#define RC_PID_SMOOTHING (1 << RC_PID_SMOOTHING_SHIFT)
++#define RC_PID_COEFF_P 15
++#define RC_PID_COEFF_I 15
++#define RC_PID_COEFF_D 5
++#define MAXPROBES 3
++#define SSV_DRATE_IDX (2)
++#define SSV_CRATE_IDX (3)
++
++struct ssv_softc;
++struct ssv_rc_rate *ssv6xxx_rc_get_rate(int rc_index);
++void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
++			    struct ieee80211_tx_info *info,
++			    struct ssv_rate_info *sr);
++u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
++				   u32 do_rts_cts);
++void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc, int hw_rate_idx,
++				 struct ieee80211_rx_status *rxs);
++void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx);
++void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates);
++int ssv6xxx_rate_control_register(void);
++void ssv6xxx_rate_control_unregister(void);
++void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
++				u32 rate_index);
++int pide_frame_duration(size_t len, int rate, int short_preamble, int flags);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
+new file mode 100644
+index 000000000000..13f3fdd8072b
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
+@@ -0,0 +1,175 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_RC_COM_H_
++#define _SSV_RC_COM_H_
++#define SSV_RC_MAX_STA 8
++#define MCS_GROUP_RATES 8
++#define SSV_HT_RATE_MAX 8
++#define TDIFS 34
++#define TSLOT 9
++#define SSV_RC_MAX_HARDWARE_SUPPORT 2
++#define RC_FIRMWARE_REPORT_FLAG 0x80
++#define RC_FLAG_INVALID 0x00000001
++#define RC_FLAG_LEGACY 0x00000002
++#define RC_FLAG_HT 0x00000004
++#define RC_FLAG_HT_SGI 0x00000008
++#define RC_FLAG_HT_GF 0x00000010
++#define RC_FLAG_SHORT_PREAMBLE 0x00000020
++enum ssv6xxx_rc_phy_type {
++	WLAN_RC_PHY_CCK,
++	WLAN_RC_PHY_OFDM,
++	WLAN_RC_PHY_HT_20_SS_LGI,
++	WLAN_RC_PHY_HT_20_SS_SGI,
++	WLAN_RC_PHY_HT_20_SS_GF,
++};
++#define RATE_TABLE_SIZE 39
++#define RC_STA_VALID 0x00000001
++#define RC_STA_CAP_HT 0x00000002
++#define RC_STA_CAP_GF 0x00000004
++#define RC_STA_CAP_SGI_20 0x00000008
++#define RC_STA_CAP_SHORT_PREAMBLE 0x00000010
++#define SSV62XX_G_RATE_INDEX 7
++#define SSV62XX_RATE_MCS_INDEX 15
++#define SSV62XX_RATE_MCS_LGI_INDEX 15
++#define SSV62XX_RATE_MCS_SGI_INDEX 23
++#define SSV62XX_RATE_MCS_GREENFIELD_INDEX 31
++enum ssv_rc_rate_type {
++	RC_TYPE_B_ONLY = 0,
++	RC_TYPE_LEGACY_GB,
++	RC_TYPE_SGI_20,
++	RC_TYPE_LGI_20,
++	RC_TYPE_HT_SGI_20,
++	RC_TYPE_HT_LGI_20,
++	RC_TYPE_HT_GF,
++	RC_TYPE_MAX,
++};
++struct ssv_rate_info {
++	int crate_kbps;
++	int crate_hw_idx;
++	int drate_kbps;
++	int drate_hw_idx;
++	u32 d_flags;
++	u32 c_flags;
++};
++struct ssv_rc_rate {
++	u32 rc_flags;
++	u16 phy_type;
++	u32 rate_kbps;
++	u8 dot11_rate_idx;
++	u8 ctrl_rate_idx;
++	u8 hw_rate_idx;
++	u8 arith_shift;
++	u8 target_pf;
++};
++struct rc_pid_sta_info {
++	unsigned long last_sample;
++	unsigned long last_report;
++	u16 tx_num_failed;
++	u16 tx_num_xmit;
++	u8 probe_report_flag;
++	u8 probe_wating_times;
++	u8 real_hw_index;
++	int txrate_idx;
++	u8 last_pf;
++	s32 err_avg_sc;
++	int last_dlr;
++	u8 feedback_probes;
++	u8 monitoring;
++	u8 oldrate;
++	u8 tmp_rate_idx;
++	u8 probe_cnt;
++};
++struct rc_pid_rateinfo {
++	u16 rc_index;
++	u16 index;
++	s32 diff;
++	u16 perfect_tx_time;
++	u32 throughput;
++	unsigned long this_attempt;
++	unsigned long this_success;
++	unsigned long this_fail;
++	u64 attempt;
++	u64 success;
++	u64 fail;
++};
++struct rc_pid_info {
++	unsigned int target;
++	int oldrate;
++	struct rc_pid_rateinfo rinfo[12];
++};
++struct mcs_group {
++	unsigned int duration[MCS_GROUP_RATES];
++};
++struct minstrel_rate_stats {
++	u16 rc_index;
++	unsigned int attempts, last_attempts;
++	unsigned int success, last_success;
++	u64 att_hist, succ_hist;
++	unsigned int cur_tp;
++	unsigned int cur_prob, probability;
++	unsigned int retry_count;
++	unsigned int retry_count_rtscts;
++	u8 sample_skipped;
++};
++struct minstrel_mcs_group_data {
++	u8 index;
++	u8 column;
++	unsigned int max_tp_rate;
++	unsigned int max_tp_rate2;
++	unsigned int max_prob_rate;
++	struct minstrel_rate_stats rates[MCS_GROUP_RATES];
++};
++struct ssv62xx_ht {
++	unsigned int ampdu_len;
++	unsigned int ampdu_packets;
++	unsigned int avg_ampdu_len;
++	unsigned int max_tp_rate;
++	unsigned int max_tp_rate2;
++	unsigned int max_prob_rate;
++	int first_try_count;
++	int second_try_count;
++	int other_try_count;
++	unsigned long stats_update;
++	unsigned int overhead;
++	unsigned int overhead_rtscts;
++	unsigned int total_packets;
++	unsigned int sample_packets;
++	u8 sample_wait;
++	u8 sample_tries;
++	u8 sample_count;
++	u8 sample_slow;
++	struct minstrel_mcs_group_data groups;
++};
++struct ssv_sta_rc_info {
++	u8 rc_valid;
++	u8 rc_type;
++	u8 rc_num_rate;
++	s8 rc_wsid;
++	u8 ht_rc_type;
++	u8 is_ht;
++	u32 rc_supp_rates;
++	u32 ht_supp_rates;
++	struct rc_pid_info pinfo;
++	struct rc_pid_sta_info spinfo;
++	struct ssv62xx_ht ht;
++};
++struct ssv_rate_ctrl {
++	struct ssv_rc_rate *rc_table;
++	struct ssv_sta_rc_info sta_rc_info[SSV_RC_MAX_STA];
++};
++#define HT_RC_UPDATE_INTERVAL 1000
++#endif
+diff --git a/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
+new file mode 100644
+index 000000000000..10a9a77081db
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/irq.h>
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/vmalloc.h>
++#include <linux/gpio.h>
++#include <linux/mmc/host.h>
++#include <linux/delay.h>
++#include <linux/regulator/consumer.h>
++#include <asm/io.h>
++#include <linux/printk.h>
++#include <linux/err.h>
++
++static int g_wifidev_registered = 0;
++extern int ssvdevice_init(void);
++extern void ssvdevice_exit(void);
++extern int ssv6xxx_get_dev_status(void);
++
++static __init int ssv_init_module(void)
++{
++	int ret = 0;
++	int time = 5;
++
++	msleep(120);
++
++	g_wifidev_registered = 1;
++	ret = ssvdevice_init();
++
++	while(time-- > 0){
++		msleep(500);
++		if(ssv6xxx_get_dev_status() == 1)
++			break;
++		pr_info("%s : Retry to carddetect\n",__func__);
++	}
++
++	return ret;
++
++}
++static __exit void ssv_exit_module(void)
++{
++
++	if (g_wifidev_registered)
++    {
++        ssvdevice_exit();
++        msleep(50);
++        g_wifidev_registered = 0;
++    }
++
++    return;
++
++}
++
++module_init(ssv_init_module);
++module_exit(ssv_exit_module);
++
++MODULE_AUTHOR("iComm Semiconductor Co., Ltd");
++MODULE_FIRMWARE("ssv*-sw.bin");
++MODULE_FIRMWARE("ssv*-wifi.cfg");
++MODULE_DESCRIPTION("Shared library for SSV wireless LAN cards.");
++MODULE_LICENSE("Dual BSD/GPL");
++
+diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
+new file mode 100644
+index 000000000000..503df1ea6dc3
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
+@@ -0,0 +1,1765 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/export.h>
++#include <linux/platform_device.h>
++#include <linux/string.h>
++#include <ssv6200_reg.h>
++#include <ssv6200.h>
++#include <hci/hctrl.h>
++#include <smac/dev.h>
++#include "ssv_cmd.h"
++#include <ssv_version.h>
++#include <ssv6200_configuration.h>
++#define SSV_CMD_PRINTF()
++struct ssv6xxx_dev_table {
++	u32 address;
++	u32 val;
++};
++struct ssv6xxx_debug {
++	struct device *dev;
++	struct platform_device *pdev;
++	struct ssv6xxx_hwif_ops *ifops;
++};
++static struct ssv6xxx_debug *ssv6xxx_debug_ifops;
++static char sg_cmd_buffer[CLI_BUFFER_SIZE + 1];
++static char *sg_argv[CLI_ARG_SIZE];
++static u32 sg_argc;
++extern char *ssv6xxx_result_buf;
++#if defined (CONFIG_ARM64) || defined (__x86_64__)
++u64 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
++#else
++u32 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
++#endif
++EXPORT_SYMBOL(ssv6xxx_ifdebug_info);
++struct sk_buff *ssvdevice_skb_alloc(s32 len)
++{
++	struct sk_buff *skb;
++	skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
++	if (skb != NULL) {
++		skb_put(skb, 0x20);
++		skb_pull(skb, 0x20);
++	}
++	return skb;
++}
++
++void ssvdevice_skb_free(struct sk_buff *skb)
++{
++	dev_kfree_skb_any(skb);
++}
++
++static int ssv_cmd_help(int argc, char *argv[])
++{
++	extern struct ssv_cmd_table cmd_table[];
++	struct ssv_cmd_table *sc_tbl;
++	char tmpbf[161];
++	int total_cmd = 0;
++	{
++		sprintf(ssv6xxx_result_buf, "Usage:\n");
++		for (sc_tbl = &cmd_table[3]; sc_tbl->cmd; sc_tbl++) {
++			sprintf(tmpbf, "%-20s\t\t%s\n", sc_tbl->cmd,
++				sc_tbl->usage);
++			strcat(ssv6xxx_result_buf, tmpbf);
++			total_cmd++;
++		}
++		sprintf(tmpbf,
++			"Total CMDs: %d\n\nType cli help [CMD] for more detail command.\n\n",
++			total_cmd);
++		strcat(ssv6xxx_result_buf, tmpbf);
++	}
++	return 0;
++}
++
++static int ssv_cmd_reg(int argc, char *argv[])
++{
++	u32 addr, value, count;
++	char tmpbf[64], *endp;
++	int s;
++	if (argc == 4 && strcmp(argv[1], "w") == 0) {
++		addr = simple_strtoul(argv[2], &endp, 16);
++		value = simple_strtoul(argv[3], &endp, 16);
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
++		sprintf(ssv6xxx_result_buf, " => write [0x%08x]: 0x%08x\n",
++			addr, value);
++		return 0;
++	} else if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
++		count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
++		addr = simple_strtoul(argv[2], &endp, 16);
++		sprintf(ssv6xxx_result_buf, "ADDRESS: 0x%08x\n", addr);
++		for (s = 0; s < count; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++			sprintf(tmpbf, "%08x ", value);
++			strcat(ssv6xxx_result_buf, tmpbf);
++			if (((s + 1) & 0x07) == 0)
++				strcat(ssv6xxx_result_buf, "\n");
++		}
++		strcat(ssv6xxx_result_buf, "\n");
++		return 0;
++	} else {
++		sprintf(tmpbf, "reg [r|w] [address] [value|word-count]\n\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	return -1;
++}
++
++struct ssv6xxx_cfg ssv_cfg;
++EXPORT_SYMBOL(ssv_cfg);
++static int __string2u32(u8 * u8str, void *val, u32 arg)
++{
++	char *endp;
++	int base = 10;
++	if (u8str[0] == '0' && ((u8str[1] == 'x') || (u8str[1] == 'X')))
++		base = 16;
++	*(u32 *) val = simple_strtoul(u8str, &endp, base);
++	return 0;
++}
++
++static int __string2flag32(u8 * flag_str, void *flag, u32 arg)
++{
++	u32 *val = (u32 *) flag;
++	if (arg >= (sizeof(u32) << 3))
++		return -1;
++	if (strcmp(flag_str, "on") == 0) {
++		*val |= (1 << arg);
++		return 0;
++	}
++	if (strcmp(flag_str, "off") == 0) {
++		*val &= ~(1 << arg);
++		return 0;
++	}
++	return -1;
++}
++
++static int __string2mac(u8 * mac_str, void *val, u32 arg)
++{
++	int s, macaddr[6];
++	u8 *mac = (u8 *) val;
++	s = sscanf(mac_str, "%02x:%02x:%02x:%02x:%02x:%02x",
++		   &macaddr[0], &macaddr[1], &macaddr[2],
++		   &macaddr[3], &macaddr[4], &macaddr[5]);
++	if (s != 6)
++		return -1;
++	mac[0] = (u8) macaddr[0], mac[1] = (u8) macaddr[1];
++	mac[2] = (u8) macaddr[2], mac[3] = (u8) macaddr[3];
++	mac[4] = (u8) macaddr[4], mac[5] = (u8) macaddr[5];
++	return 0;
++}
++
++static int __string2str(u8 * path, void *val, u32 arg)
++{
++	u8 *temp = (u8 *) val;
++	sprintf(temp, "%s", path);
++	return 0;
++}
++
++static int __string2configuration(u8 * mac_str, void *val, u32 arg)
++{
++	unsigned int address, value;
++	int i;
++	i = sscanf(mac_str, "%08x:%08x", &address, &value);
++	if (i != 2)
++		return -1;
++	for (i = 0; i < EXTERNEL_CONFIG_SUPPORT; i++) {
++		if (ssv_cfg.configuration[i][0] == 0x0) {
++			ssv_cfg.configuration[i][0] = address;
++			ssv_cfg.configuration[i][1] = value;
++			return 0;
++		}
++	}
++	return 0;
++}
++
++struct ssv6xxx_cfg_cmd_table cfg_cmds[] = {
++	{"hw_mac", (void *)&ssv_cfg.maddr[0][0], 0, __string2mac},
++	{"hw_mac_2", (void *)&ssv_cfg.maddr[1][0], 0, __string2mac},
++	{"def_chan", (void *)&ssv_cfg.def_chan, 0, __string2u32},
++	{"hw_cap_ht", (void *)&ssv_cfg.hw_caps, 0, __string2flag32},
++	{"hw_cap_gf", (void *)&ssv_cfg.hw_caps, 1, __string2flag32},
++	{"hw_cap_2ghz", (void *)&ssv_cfg.hw_caps, 2, __string2flag32},
++	{"hw_cap_5ghz", (void *)&ssv_cfg.hw_caps, 3, __string2flag32},
++	{"hw_cap_security", (void *)&ssv_cfg.hw_caps, 4, __string2flag32},
++	{"hw_cap_sgi_20", (void *)&ssv_cfg.hw_caps, 5, __string2flag32},
++	{"hw_cap_sgi_40", (void *)&ssv_cfg.hw_caps, 6, __string2flag32},
++	{"hw_cap_ap", (void *)&ssv_cfg.hw_caps, 7, __string2flag32},
++	{"hw_cap_p2p", (void *)&ssv_cfg.hw_caps, 8, __string2flag32},
++	{"hw_cap_ampdu_rx", (void *)&ssv_cfg.hw_caps, 9, __string2flag32},
++	{"hw_cap_ampdu_tx", (void *)&ssv_cfg.hw_caps, 10, __string2flag32},
++	{"hw_cap_tdls", (void *)&ssv_cfg.hw_caps, 11, __string2flag32},
++	{"use_wpa2_only", (void *)&ssv_cfg.use_wpa2_only, 0, __string2u32},
++	{"wifi_tx_gain_level_gn", (void *)&ssv_cfg.wifi_tx_gain_level_gn, 0,
++	 __string2u32},
++	{"wifi_tx_gain_level_b", (void *)&ssv_cfg.wifi_tx_gain_level_b, 0,
++	 __string2u32},
++	{"rssi_ctl", (void *)&ssv_cfg.rssi_ctl, 0, __string2u32},
++	{"xtal_clock", (void *)&ssv_cfg.crystal_type, 0, __string2u32},
++	{"volt_regulator", (void *)&ssv_cfg.volt_regulator, 0, __string2u32},
++	{"force_chip_identity", (void *)&ssv_cfg.force_chip_identity, 0,
++	 __string2u32},
++	{"firmware_path", (void *)&ssv_cfg.firmware_path[0], 0, __string2str},
++	{"flash_bin_path", (void *)&ssv_cfg.flash_bin_path[0], 0, __string2str},
++	{"mac_address_path", (void *)&ssv_cfg.mac_address_path[0], 0,
++	 __string2str},
++	{"mac_output_path", (void *)&ssv_cfg.mac_output_path[0], 0,
++	 __string2str},
++	{"ignore_efuse_mac", (void *)&ssv_cfg.ignore_efuse_mac, 0,
++	 __string2u32},
++	{"mac_address_mode", (void *)&ssv_cfg.mac_address_mode, 0,
++	 __string2u32},
++	{"sr_bhvr", (void *)&ssv_cfg.sr_bhvr, 0, __string2u32},
++	{"register", NULL, 0, __string2configuration},
++	{NULL, NULL, 0, NULL},
++};
++
++EXPORT_SYMBOL(cfg_cmds);
++static int ssv_cmd_cfg(int argc, char *argv[])
++{
++	char temp_buf[64];
++	int s;
++	if (argc == 2 && strcmp(argv[1], "reset") == 0) {
++		memset(&ssv_cfg, 0, sizeof(ssv_cfg));
++		return 0;
++	} else if (argc == 2 && strcmp(argv[1], "show") == 0) {
++		strcpy(ssv6xxx_result_buf, ">> ssv6xxx config:\n");
++		sprintf(temp_buf, "    hw_caps = 0x%08x\n", ssv_cfg.hw_caps);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    def_chan = %d\n", ssv_cfg.def_chan);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    wifi_tx_gain_level_gn = %d\n",
++			ssv_cfg.wifi_tx_gain_level_gn);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    wifi_tx_gain_level_b = %d\n",
++			ssv_cfg.wifi_tx_gain_level_b);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    rssi_ctl = %d\n", ssv_cfg.rssi_ctl);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    sr_bhvr = %d\n", ssv_cfg.sr_bhvr);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    sta-mac = %02x:%02x:%02x:%02x:%02x:%02x",
++			ssv_cfg.maddr[0][0], ssv_cfg.maddr[0][1],
++			ssv_cfg.maddr[0][2], ssv_cfg.maddr[0][3],
++			ssv_cfg.maddr[0][4], ssv_cfg.maddr[0][5]);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		strcat(ssv6xxx_result_buf, "\n");
++		return 0;
++	}
++	if (argc != 4)
++		return -1;
++	for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
++		if (strcmp(cfg_cmds[s].cfg_cmd, argv[1]) == 0) {
++			cfg_cmds[s].translate_func(argv[3],
++						   cfg_cmds[s].var,
++						   cfg_cmds[s].arg);
++			strcpy(ssv6xxx_result_buf, "");
++			return 0;
++		}
++	}
++	return -1;
++}
++
++void *ssv_dbg_phy_table = NULL;
++EXPORT_SYMBOL(ssv_dbg_phy_table);
++u32 ssv_dbg_phy_len = 0;
++EXPORT_SYMBOL(ssv_dbg_phy_len);
++void *ssv_dbg_rf_table = NULL;
++EXPORT_SYMBOL(ssv_dbg_rf_table);
++u32 ssv_dbg_rf_len = 0;
++EXPORT_SYMBOL(ssv_dbg_rf_len);
++struct ssv_softc *ssv_dbg_sc = NULL;
++EXPORT_SYMBOL(ssv_dbg_sc);
++struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci = NULL;
++EXPORT_SYMBOL(ssv_dbg_ctrl_hci);
++struct Dump_Sta_Info {
++	char *dump_buf;
++	int sta_idx;
++};
++static void _dump_sta_info(struct ssv_softc *sc,
++			   struct ssv_vif_info *vif_info,
++			   struct ssv_sta_info *sta_info, void *param)
++{
++	char tmpbf[128];
++	struct Dump_Sta_Info *dump_sta_info = (struct Dump_Sta_Info *)param;
++	struct ssv_sta_priv_data *priv_sta =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	if ((sta_info->s_flags & STA_FLAG_VALID) == 0)
++		sprintf(tmpbf,
++			"        Station %d: %d is not valid\n",
++			dump_sta_info->sta_idx, priv_sta->sta_idx);
++	else
++		sprintf(tmpbf,
++			"        Station %d: %d\n"
++			"             Address: %02X:%02X:%02X:%02X:%02X:%02X\n"
++			"             WISD: %d\n"
++			"             AID: %d\n"
++			"             Sleep: %d\n",
++			dump_sta_info->sta_idx, priv_sta->sta_idx,
++			sta_info->sta->addr[0], sta_info->sta->addr[1],
++			sta_info->sta->addr[2], sta_info->sta->addr[3],
++			sta_info->sta->addr[4], sta_info->sta->addr[5],
++			sta_info->hw_wsid, sta_info->aid, sta_info->sleeping);
++	dump_sta_info->sta_idx++;
++	strcat(dump_sta_info->dump_buf, tmpbf);
++}
++
++void ssv6xxx_dump_sta_info(struct ssv_softc *sc, char *target_buf)
++{
++	int j;
++	char tmpbf[128];
++	struct Dump_Sta_Info dump_sta_info = { target_buf, 0 };
++	sprintf(tmpbf, "  >>>> bcast queue len[%d]\n", sc->bcast_txq.cur_qsize);
++	strcat(target_buf, tmpbf);
++	for (j = 0; j < SSV6200_MAX_VIF; j++) {
++		struct ieee80211_vif *vif = sc->vif_info[j].vif;
++		struct ssv_vif_priv_data *priv_vif;
++		struct ssv_sta_priv_data *sta_priv_iter;
++		if (vif == NULL) {
++			sprintf(tmpbf, "    VIF: %d is not used.\n", j);
++			strcat(target_buf, tmpbf);
++			continue;
++		}
++		sprintf(tmpbf,
++			"    VIF: %d - [%02X:%02X:%02X:%02X:%02X:%02X] type[%d] p2p[%d]\n",
++			j, vif->addr[0], vif->addr[1], vif->addr[2],
++			vif->addr[3], vif->addr[4], vif->addr[5], vif->type,
++			vif->p2p);
++		strcat(target_buf, tmpbf);
++		priv_vif = (struct ssv_vif_priv_data *)(vif->drv_priv);
++		list_for_each_entry(sta_priv_iter, &priv_vif->sta_list, list) {
++			if ((sta_priv_iter->sta_info->
++			     s_flags & STA_FLAG_VALID) == 0) {
++				sprintf(tmpbf, "    VIF: %d  is not valid.\n",
++					j);
++				strcat(target_buf, tmpbf);
++				continue;
++			}
++			_dump_sta_info(sc, &sc->vif_info[priv_vif->vif_idx],
++				       sta_priv_iter->sta_info, &dump_sta_info);
++		}
++	}
++}
++
++static int ssv_cmd_sta(int argc, char *argv[])
++{
++	if (argc >= 2 && strcmp(argv[1], "show") == 0)
++		ssv6xxx_dump_sta_info(ssv_dbg_sc, ssv6xxx_result_buf);
++	else
++		strcat(ssv6xxx_result_buf, "sta show\n\n");
++	return 0;
++}
++
++static int ssv_cmd_dump(int argc, char *argv[])
++{
++	u32 addr, regval;
++	char tmpbf[64];
++	int s;
++	if (!ssv6xxx_result_buf) {
++		pr_warn("ssv6xxx_result_buf = NULL!!\n");
++		return -1;
++	}
++	if (argc != 2) {
++		sprintf(tmpbf,
++			"dump [wsid|decision|phy-info|phy-reg|rf-reg]\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	if (strcmp(argv[1], "wsid") == 0) {
++		const u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
++		const u32 reg_wsid_tid0[] =
++		    { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
++		const u32 reg_wsid_tid7[] =
++		    { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
++		const u8 *op_mode_str[] = { "STA", "AP", "AD-HOC", "WDS" };
++		const u8 *ht_mode_str[] =
++		    { "Non-HT", "HT-MF", "HT-GF", "RSVD" };
++		for (s = 0; s < SSV_NUM_HW_STA; s++) {
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, reg_wsid[s], &regval)) ;
++			sprintf(tmpbf,
++				"==>WSID[%d]\n\tvalid[%d] qos[%d] op_mode[%s] ht_mode[%s]\n",
++				s, regval & 0x1, (regval >> 1) & 0x1,
++				op_mode_str[((regval >> 2) & 3)],
++				ht_mode_str[((regval >> 4) & 3)]);
++			strcat(ssv6xxx_result_buf, tmpbf);
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, reg_wsid[s] + 4, &regval)) ;
++			sprintf(tmpbf, "\tMAC[%02x:%02x:%02x:%02x:",
++				(regval & 0xff), ((regval >> 8) & 0xff),
++				((regval >> 16) & 0xff),
++				((regval >> 24) & 0xff));
++			strcat(ssv6xxx_result_buf, tmpbf);
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, reg_wsid[s] + 8, &regval)) ;
++			sprintf(tmpbf, "%02x:%02x]\n", (regval & 0xff),
++				((regval >> 8) & 0xff));
++			strcat(ssv6xxx_result_buf, tmpbf);
++			for (addr = reg_wsid_tid0[s]; addr <= reg_wsid_tid7[s];
++			     addr += 4) {
++				if (SSV_REG_READ1
++				    (ssv6xxx_debug_ifops, addr, &regval)) ;
++				sprintf(tmpbf, "\trx_seq%d[%d]\n",
++					((addr - reg_wsid_tid0[s]) >> 2),
++					((regval) & 0xffff));
++				strcat(ssv6xxx_result_buf, tmpbf);
++			}
++		}
++		return 0;
++	}
++	if (strcmp(argv[1], "decision") == 0) {
++		strcpy(ssv6xxx_result_buf, ">> Decision Table:\n");
++		for (s = 0, addr = ADR_MRX_FLT_TB0; s < 16; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
++			sprintf(tmpbf, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
++				s, addr, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n>> Decision Mask:\n");
++		for (s = 0, addr = ADR_MRX_FLT_EN0; s < 9; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
++			sprintf(tmpbf, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
++				s, addr, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n");
++		return 0;
++	}
++	if (strcmp(argv[1], "phy-info") == 0) {
++		return 0;
++	}
++	if (strcmp(argv[1], "phy-reg") == 0) {
++		struct ssv6xxx_dev_table *raw;
++		raw = (struct ssv6xxx_dev_table *)ssv_dbg_phy_table;
++		strcpy(ssv6xxx_result_buf, ">> PHY Register Table:\n");
++		for (s = 0; s < ssv_dbg_phy_len; s++, raw++) {
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, raw->address, &regval)) ;
++			sprintf(tmpbf, "   ADDR[0x%08x] = 0x%08x\n",
++				raw->address, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n");
++		return 0;
++	}
++	if (strcmp(argv[1], "rf-reg") == 0) {
++		struct ssv6xxx_dev_table *raw;
++		raw = (struct ssv6xxx_dev_table *)ssv_dbg_rf_table;
++		strcpy(ssv6xxx_result_buf, ">> RF Register Table:\n");
++		for (s = 0; s < ssv_dbg_rf_len; s++, raw++) {
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, raw->address, &regval)) ;
++			sprintf(tmpbf, "   ADDR[0x%08x] = 0x%08x\n",
++				raw->address, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n");
++		return 0;
++	}
++	return -1;
++}
++
++static int ssv_cmd_irq(int argc, char *argv[])
++{
++	char *endp;
++	u32 irq_sts;
++	if (argc >= 3 && strcmp(argv[1], "set") == 0) {
++		if (strcmp(argv[2], "mask") == 0 && argc == 4) {
++			irq_sts = simple_strtoul(argv[3], &endp, 16);
++			if (!ssv6xxx_debug_ifops->ifops->irq_setmask) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_setmask operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_setmask(ssv6xxx_debug_ifops->dev, irq_sts);
++			sprintf(ssv6xxx_result_buf,
++				"set sdio irq mask to 0x%08x\n", irq_sts);
++			return 0;
++		}
++		if (strcmp(argv[2], "enable") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_enable) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_enable operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_enable(ssv6xxx_debug_ifops->dev);
++			strcpy(ssv6xxx_result_buf, "enable sdio irq.\n");
++			return 0;
++		}
++		if (strcmp(argv[2], "disable") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_disable) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_disable operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_disable(ssv6xxx_debug_ifops->dev, false);
++			strcpy(ssv6xxx_result_buf, "disable sdio irq.\n");
++			return 0;
++		}
++		return -1;
++	} else if (argc == 3 && strcmp(argv[1], "get") == 0) {
++		if (strcmp(argv[2], "mask") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_getmask) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_getmask operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_getmask(ssv6xxx_debug_ifops->dev, &irq_sts);
++			sprintf(ssv6xxx_result_buf,
++				"sdio irq mask: 0x%08x, int_mask=0x%08x\n",
++				irq_sts, ssv_dbg_ctrl_hci->int_mask);
++			return 0;
++		}
++		if (strcmp(argv[2], "status") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_getstatus) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_getstatus operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_getstatus(ssv6xxx_debug_ifops->dev, &irq_sts);
++			sprintf(ssv6xxx_result_buf, "sdio irq status: 0x%08x\n",
++				irq_sts);
++			return 0;
++		}
++		return -1;
++	} else {
++		sprintf(ssv6xxx_result_buf,
++			"irq [set|get] [mask|enable|disable|status]\n");
++	}
++	return 0;
++}
++
++static int ssv_cmd_mac(int argc, char *argv[])
++{
++	char temp_str[128], *endp;
++	u32 s;
++	int i;
++	if (argc == 3 && !strcmp(argv[1], "wsid") && !strcmp(argv[2], "show")) {
++		for (s = 0; s < SSV_NUM_HW_STA; s++) {
++		}
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "rx")) {
++		if (!strcmp(argv[2], "enable")) {
++			ssv_dbg_sc->dbg_rx_frame = 1;
++		} else {
++			ssv_dbg_sc->dbg_rx_frame = 0;
++		}
++		sprintf(temp_str, "  dbg_rx_frame %d\n",
++			ssv_dbg_sc->dbg_rx_frame);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "tx")) {
++		if (!strcmp(argv[2], "enable")) {
++			ssv_dbg_sc->dbg_tx_frame = 1;
++		} else {
++			ssv_dbg_sc->dbg_tx_frame = 0;
++		}
++		sprintf(temp_str, "  dbg_tx_frame %d\n",
++			ssv_dbg_sc->dbg_tx_frame);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "rxq")
++		   && !strcmp(argv[2], "show")) {
++		sprintf(temp_str, ">> MAC RXQ: (%s)\n    cur_qsize=%d\n",
++			((ssv_dbg_sc->
++			  sc_flags & SC_OP_OFFCHAN) ? "off channel" :
++			 "on channel"), ssv_dbg_sc->rx.rxq_count);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 4 && !strcmp(argv[1], "set")
++		   && !strcmp(argv[2], "rate")) {
++		if (strcmp(argv[3], "auto") == 0) {
++			ssv_dbg_sc->sc_flags &= ~SC_OP_FIXED_RATE;
++			return 0;
++		}
++		i = simple_strtoul(argv[3], &endp, 10);
++		if (i < 0 || i > 38) {
++			strcpy(ssv6xxx_result_buf, " Invalid rat index !!\n");
++			return -1;
++		}
++		ssv_dbg_sc->max_rate_idx = i;
++		ssv_dbg_sc->sc_flags |= SC_OP_FIXED_RATE;
++		sprintf(temp_str, " Set rate to index %d\n", i);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "get")
++		   && !strcmp(argv[2], "rate")) {
++		if (ssv_dbg_sc->sc_flags & SC_OP_FIXED_RATE)
++			sprintf(temp_str, " Current Rate Index: %d\n",
++				ssv_dbg_sc->max_rate_idx);
++		else
++			sprintf(temp_str, "  Current Rate Index: auto\n");
++		strcpy(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else {
++		sprintf(temp_str, "mac [security|wsid|rxq]  [show]\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "mac [set|get] [rate] [auto|idx]\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "mac [rx|tx] [eable|disable]\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	}
++	return 0;
++}
++
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++void print_irq_count(void)
++{
++	char temp_str[512];
++	sprintf(temp_str, "irq debug (%s)\n",
++		ssv_dbg_ctrl_hci->irq_enable ? "enable" : "disable");
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "total irq (%d)\n", ssv_dbg_ctrl_hci->irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "invalid irq (%d)\n",
++		ssv_dbg_ctrl_hci->invalid_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "rx irq (%d)\n", ssv_dbg_ctrl_hci->rx_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "tx irq (%d)\n", ssv_dbg_ctrl_hci->tx_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "real tx count irq (%d)\n",
++		ssv_dbg_ctrl_hci->real_tx_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "tx  packet count (%d)\n",
++		ssv_dbg_ctrl_hci->irq_tx_pkt_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "rx packet (%d)\n",
++		ssv_dbg_ctrl_hci->irq_rx_pkt_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++}
++#endif
++void print_isr_info(void)
++{
++	char temp_str[512];
++	sprintf(temp_str, ">>>> HCI Calculate ISR TIME(%s) unit:us\n",
++		((ssv_dbg_ctrl_hci->isr_summary_eable) ? "enable" : "disable"));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_routine_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_routine_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_tx_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_tx_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_rx_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_idle_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_idle_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_rx_idle_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_idle_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_miss_cnt(%d)\n", ssv_dbg_ctrl_hci->isr_miss_cnt);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "prev_isr_jiffes(%lu)\n",
++		ssv_dbg_ctrl_hci->prev_isr_jiffes);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "prev_rx_isr_jiffes(%lu)\n",
++		ssv_dbg_ctrl_hci->prev_rx_isr_jiffes);
++	strcat(ssv6xxx_result_buf, temp_str);
++}
++
++static int ssv_cmd_hci(int argc, char *argv[])
++{
++	struct ssv_hw_txq *txq;
++	char temp_str[512];
++	int s, ac = 0;
++	if (argc == 3 && !strcmp(argv[1], "txq") && !strcmp(argv[2], "show")) {
++		for (s = 0; s < WMM_NUM_AC; s++) {
++			if (ssv_dbg_sc != NULL)
++				ac = ssv_dbg_sc->tx.ac_txqid[s];
++			txq = &ssv_dbg_ctrl_hci->hw_txq[s];
++			sprintf(temp_str, ">> txq[%d]", txq->txq_no);
++			if (ssv_dbg_sc != NULL)
++				sprintf(temp_str, "(%s): ",
++					((ssv_dbg_sc->
++					  sc_flags & SC_OP_OFFCHAN) ?
++					 "off channel" : "on channel"));
++			sprintf(temp_str, "cur_qsize=%d\n",
++				skb_queue_len(&txq->qhead));
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str,
++				"            max_qsize=%d, pause=%d, resume_thres=%d",
++				txq->max_qsize, txq->paused, txq->resum_thres);
++			if (ssv_dbg_sc != NULL)
++				sprintf(temp_str, " flow_control[%d]\n",
++					!!(ssv_dbg_sc->tx.
++					   flow_ctrl_status & (1 << ac)));
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "            Total %d frame sent\n",
++				txq->tx_pkt);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		sprintf(temp_str,
++			">> HCI Debug Counters:\n    read_rs0_info_fail=%d, read_rs1_info_fail=%d\n",
++			ssv_dbg_ctrl_hci->read_rs0_info_fail,
++			ssv_dbg_ctrl_hci->read_rs1_info_fail);
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str,
++			"    rx_work_running=%d, isr_running=%d, xmit_running=%d\n",
++			ssv_dbg_ctrl_hci->rx_work_running,
++			ssv_dbg_ctrl_hci->isr_running,
++			ssv_dbg_ctrl_hci->xmit_running);
++		strcat(ssv6xxx_result_buf, temp_str);
++		if (ssv_dbg_sc != NULL)
++			sprintf(temp_str, "    flow_ctrl_status=%08x\n",
++				ssv_dbg_sc->tx.flow_ctrl_status);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "rxq")
++		   && !strcmp(argv[2], "show")) {
++		sprintf(temp_str, ">> HCI RX Queue (%s): cur_qsize=%d\n",
++			((ssv_dbg_sc->
++			  sc_flags & SC_OP_OFFCHAN) ? "off channel" :
++			 "on channel"), ssv_dbg_ctrl_hci->rx_pkt);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
++		   && !strcmp(argv[2], "start")) {
++		ssv_dbg_ctrl_hci->isr_summary_eable = 1;
++		ssv_dbg_ctrl_hci->isr_routine_time = 0;
++		ssv_dbg_ctrl_hci->isr_tx_time = 0;
++		ssv_dbg_ctrl_hci->isr_rx_time = 0;
++		ssv_dbg_ctrl_hci->isr_idle_time = 0;
++		ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
++		ssv_dbg_ctrl_hci->isr_miss_cnt = 0;
++		ssv_dbg_ctrl_hci->prev_isr_jiffes = 0;
++		ssv_dbg_ctrl_hci->prev_rx_isr_jiffes = 0;
++		print_isr_info();
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
++		   && !strcmp(argv[2], "stop")) {
++		ssv_dbg_ctrl_hci->isr_summary_eable = 0;
++		print_isr_info();
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
++		   && !strcmp(argv[2], "show")) {
++		print_isr_info();
++		return 0;
++	}
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++	else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		 && !strcmp(argv[2], "reset")) {
++		ssv_dbg_ctrl_hci->irq_enable = 0;
++		ssv_dbg_ctrl_hci->irq_count = 0;
++		ssv_dbg_ctrl_hci->invalid_irq_count = 0;
++		ssv_dbg_ctrl_hci->tx_irq_count = 0;
++		ssv_dbg_ctrl_hci->real_tx_irq_count = 0;
++		ssv_dbg_ctrl_hci->rx_irq_count = 0;
++		ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
++		ssv_dbg_ctrl_hci->irq_rx_pkt_count = 0;
++		ssv_dbg_ctrl_hci->irq_tx_pkt_count = 0;
++		strcat(ssv6xxx_result_buf, "irq debug reset count\n");
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		   && !strcmp(argv[2], "show")) {
++		print_irq_count();
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		   && !strcmp(argv[2], "stop")) {
++		ssv_dbg_ctrl_hci->irq_enable = 0;
++		strcat(ssv6xxx_result_buf, "irq debug stop\n");
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		   && !strcmp(argv[2], "start")) {
++		ssv_dbg_ctrl_hci->irq_enable = 1;
++		strcat(ssv6xxx_result_buf, "irq debug start\n");
++		return 0;
++	}
++#endif
++	else {
++		strcat(ssv6xxx_result_buf,
++		       "hci [txq|rxq] [show]\nhci [isr_time] [start|stop|show]\n\n");
++		return 0;
++	}
++	return -1;
++}
++
++static int ssv_cmd_hwq(int argc, char *argv[])
++{
++#undef GET_FFO0_CNT
++#undef GET_FFO1_CNT
++#undef GET_FFO2_CNT
++#undef GET_FFO3_CNT
++#undef GET_FFO4_CNT
++#undef GET_FFO5_CNT
++#undef GET_FFO6_CNT
++#undef GET_FFO7_CNT
++#undef GET_FFO8_CNT
++#undef GET_FFO9_CNT
++#undef GET_FFO10_CNT
++#undef GET_FFO11_CNT
++#undef GET_FFO12_CNT
++#undef GET_FFO13_CNT
++#undef GET_FFO14_CNT
++#undef GET_FFO15_CNT
++#undef GET_FF0_CNT
++#undef GET_FF1_CNT
++#undef GET_FF3_CNT
++#undef GET_FF5_CNT
++#undef GET_FF6_CNT
++#undef GET_FF7_CNT
++#undef GET_FF8_CNT
++#undef GET_FF9_CNT
++#undef GET_FF10_CNT
++#undef GET_FF11_CNT
++#undef GET_FF12_CNT
++#undef GET_FF13_CNT
++#undef GET_FF14_CNT
++#undef GET_FF15_CNT
++#undef GET_FF4_CNT
++#undef GET_FF2_CNT
++#undef GET_TX_ID_ALC_LEN
++#undef GET_RX_ID_ALC_LEN
++#undef GET_AVA_TAG
++#define GET_FFO0_CNT ((value & 0x0000001f ) >> 0)
++#define GET_FFO1_CNT ((value & 0x000003e0 ) >> 5)
++#define GET_FFO2_CNT ((value & 0x00000c00 ) >> 10)
++#define GET_FFO3_CNT ((value & 0x000f8000 ) >> 15)
++#define GET_FFO4_CNT ((value & 0x00300000 ) >> 20)
++#define GET_FFO5_CNT ((value & 0x0e000000 ) >> 25)
++#define GET_FFO6_CNT ((value1 & 0x0000000f ) >> 0)
++#define GET_FFO7_CNT ((value1 & 0x000003e0 ) >> 5)
++#define GET_FFO8_CNT ((value1 & 0x00007c00 ) >> 10)
++#define GET_FFO9_CNT ((value1 & 0x000f8000 ) >> 15)
++#define GET_FFO10_CNT ((value1 & 0x00f00000 ) >> 20)
++#define GET_FFO11_CNT ((value1 & 0x3e000000 ) >> 25)
++#define GET_FFO12_CNT ((value2 & 0x00000007 ) >> 0)
++#define GET_FFO13_CNT ((value2 & 0x00000060 ) >> 5)
++#define GET_FFO14_CNT ((value2 & 0x00000c00 ) >> 10)
++#define GET_FFO15_CNT ((value2 & 0x001f8000 ) >> 15)
++#define GET_FF0_CNT ((value & 0x0000001f ) >> 0)
++#define GET_FF1_CNT ((value & 0x000001e0 ) >> 5)
++#define GET_FF3_CNT ((value & 0x00003800 ) >> 11)
++#define GET_FF5_CNT ((value & 0x000e0000 ) >> 17)
++#define GET_FF6_CNT ((value & 0x00700000 ) >> 20)
++#define GET_FF7_CNT ((value & 0x03800000 ) >> 23)
++#define GET_FF8_CNT ((value & 0x1c000000 ) >> 26)
++#define GET_FF9_CNT ((value & 0xe0000000 ) >> 29)
++#define GET_FF10_CNT ((value1 & 0x00000007 ) >> 0)
++#define GET_FF11_CNT ((value1 & 0x00000038 ) >> 3)
++#define GET_FF12_CNT ((value1 & 0x000001c0 ) >> 6)
++#define GET_FF13_CNT ((value1 & 0x00000600 ) >> 9)
++#define GET_FF14_CNT ((value1 & 0x00001800 ) >> 11)
++#define GET_FF15_CNT ((value1 & 0x00006000 ) >> 13)
++#define GET_FF4_CNT ((value1 & 0x000f8000 ) >> 15)
++#define GET_FF2_CNT ((value1 & 0x00700000 ) >> 20)
++#define GET_TX_ID_ALC_LEN ((value & 0x0003fe00 ) >> 9)
++#define GET_RX_ID_ALC_LEN ((value & 0x07fc0000 ) >> 18)
++#define GET_AVA_TAG ((value1 & 0x01ff0000 ) >> 16)
++	u32 addr, value, value1, value2;
++	char temp_str[512];
++	addr = ADR_RD_FFOUT_CNT1;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++	addr = ADR_RD_FFOUT_CNT2;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
++	addr = ADR_RD_FFOUT_CNT3;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value2)) ;
++	sprintf(temp_str,
++		"\n[TAG]  MCU - HCI - SEC -  RX - MIC - TX0 - TX1 - TX2 - TX3 - TX4 - SEC - MIC - TSH\n");
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str,
++		"OUTPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
++		GET_FFO0_CNT, GET_FFO1_CNT, GET_FFO3_CNT, GET_FFO4_CNT,
++		GET_FFO5_CNT, GET_FFO6_CNT, GET_FFO7_CNT, GET_FFO8_CNT,
++		GET_FFO9_CNT, GET_FFO10_CNT, GET_FFO11_CNT, GET_FFO12_CNT,
++		GET_FFO15_CNT);
++	strcat(ssv6xxx_result_buf, temp_str);
++	addr = ADR_RD_IN_FFCNT1;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++	addr = ADR_RD_IN_FFCNT2;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
++	sprintf(temp_str,
++		"INPUT  %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
++		GET_FF0_CNT, GET_FF1_CNT, GET_FF3_CNT, GET_FF4_CNT, GET_FF5_CNT,
++		GET_FF6_CNT, GET_FF7_CNT, GET_FF8_CNT, GET_FF9_CNT,
++		GET_FF10_CNT, GET_FF11_CNT, GET_FF12_CNT, GET_FF15_CNT);
++	strcat(ssv6xxx_result_buf, temp_str);
++	addr = ADR_ID_LEN_THREADSHOLD2;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++	addr = ADR_TAG_STATUS;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
++	sprintf(temp_str, "TX[%d]RX[%d]AVA[%d]\n", GET_TX_ID_ALC_LEN,
++		GET_RX_ID_ALC_LEN, GET_AVA_TAG);
++	strcat(ssv6xxx_result_buf, temp_str);
++	return 0;
++}
++
++#ifdef CONFIG_P2P_NOA
++static struct ssv6xxx_p2p_noa_param cmd_noa_param = {
++	50,
++	100,
++	0x12345678,
++	1,
++	255,
++	{0x4c, 0xe6, 0x76, 0xa2, 0x4e, 0x7c}
++};
++
++void noa_dump(char *temp_str)
++{
++	sprintf(temp_str,
++		"NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]\n",
++		cmd_noa_param.enable, cmd_noa_param.interval,
++		cmd_noa_param.duration, cmd_noa_param.start_time,
++		cmd_noa_param.count, cmd_noa_param.addr[0],
++		cmd_noa_param.addr[1], cmd_noa_param.addr[2],
++		cmd_noa_param.addr[3], cmd_noa_param.addr[4],
++		cmd_noa_param.addr[5]);
++	strcat(ssv6xxx_result_buf, temp_str);
++}
++
++void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
++			  struct ssv6xxx_p2p_noa_param *p2p_noa_param)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int retry_cnt = 5;
++	skb =
++	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
++				sizeof(struct ssv6xxx_p2p_noa_param));
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, p2p_noa_param,
++	       sizeof(struct ssv6xxx_p2p_noa_param));
++	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
++		pr_debug("NOA cmd retry=%d\n", retry_cnt);
++		retry_cnt--;
++	}
++	ssvdevice_skb_free(skb);
++}
++
++static int ssv_cmd_noa(int argc, char *argv[])
++{
++	char temp_str[512];
++	char *endp;
++	if (argc == 2 && !strcmp(argv[1], "show")) {
++		;
++	} else if (argc == 3 && !strcmp(argv[1], "duration")) {
++		cmd_noa_param.duration = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "interval")) {
++		cmd_noa_param.interval = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "start")) {
++		cmd_noa_param.start_time = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "enable")) {
++		cmd_noa_param.enable = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "count")) {
++		cmd_noa_param.count = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 8 && !strcmp(argv[1], "addr")) {
++		cmd_noa_param.addr[0] = simple_strtoul(argv[2], &endp, 16);
++		cmd_noa_param.addr[1] = simple_strtoul(argv[3], &endp, 16);
++		cmd_noa_param.addr[2] = simple_strtoul(argv[4], &endp, 16);
++		cmd_noa_param.addr[3] = simple_strtoul(argv[5], &endp, 16);
++		cmd_noa_param.addr[4] = simple_strtoul(argv[6], &endp, 16);
++		cmd_noa_param.addr[5] = simple_strtoul(argv[7], &endp, 16);
++	} else if (argc == 2 && !strcmp(argv[1], "send")) {
++		ssv6xxx_send_noa_cmd(ssv_dbg_sc, &cmd_noa_param);
++	} else {
++		sprintf(temp_str, "## wrong command\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	}
++	noa_dump(temp_str);
++	return 0;
++}
++#endif
++static int ssv_cmd_mib(int argc, char *argv[])
++{
++	u32 addr, value;
++	char temp_str[512];
++	int i;
++	if (argc == 2 && !strcmp(argv[1], "reset")) {
++		addr = MIB_REG_BASE;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
++		value = 0xffffffff;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
++		value = 0x100000;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
++		value = 0x100000;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
++		value = 0x80000000;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
++		sprintf(temp_str, " => MIB reseted\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if (argc == 2 && !strcmp(argv[1], "list")) {
++		addr = MIB_REG_BASE;
++		for (i = 0; i < 120; i++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++			sprintf(temp_str, "%08x ", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			if (((i + 1) & 0x07) == 0)
++				strcat(ssv6xxx_result_buf, "\n");
++		}
++		strcat(ssv6xxx_result_buf, "\n");
++	} else if (argc == 2 && strcmp(argv[1], "rx") == 0) {
++		sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t\t%-10s\n",
++			"MRX_FCS_SUCC", "MRX_FCS_ERR", "MRX_ALC_FAIL",
++			"MRX_MISS");
++		strcat(ssv6xxx_result_buf, temp_str);
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_MRX_FCS_SUCC, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_FCS_ERR, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_MRX_ALC_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MISS, &value)) {
++			sprintf(temp_str, "[%08x]\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t%-10s\n",
++				"MRX_MB_MISS", "MRX_NIDLE_MISS",
++				"DBG_LEN_ALC_FAIL", "DBG_LEN_CRC_FAIL");
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MB_MISS, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_MRX_NIDLE_MISS, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_LEN_ALC_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_LEN_CRC_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\n\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_PASS, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL1, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL2, &value)) {
++			sprintf(temp_str, "[%08x]\n\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "PHY B mode:\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
++				"CRC error", "CCA", "counter");
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023E8, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023EC, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "PHY G/N mode:\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
++				"CRC error", "CCA", "counter");
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043E8, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043EC, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++	} else {
++		sprintf(temp_str, "mib [reset|list|rx]\n\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	}
++	return 0;
++}
++
++static int ssv_cmd_sdio(int argc, char *argv[])
++{
++	u32 addr, value;
++	char temp_str[512], *endp;
++	int ret = 0;
++	if (argc == 4 && !strcmp(argv[1], "reg") && !strcmp(argv[2], "r")) {
++		addr = simple_strtoul(argv[3], &endp, 16);
++		if (!ssv6xxx_debug_ifops->ifops->cmd52_read) {
++			sprintf(temp_str,
++				"The interface doesn't provide cmd52 read\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++		ret =
++		    ssv6xxx_debug_ifops->ifops->cmd52_read(ssv6xxx_debug_ifops->
++							   dev, addr, &value);
++		if (ret >= 0) {
++			sprintf(temp_str, "  ==> %x\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++	} else if (argc == 5 && !strcmp(argv[1], "reg")
++		   && !strcmp(argv[2], "w")) {
++		addr = simple_strtoul(argv[3], &endp, 16);
++		value = simple_strtoul(argv[4], &endp, 16);
++		if (!ssv6xxx_debug_ifops->ifops->cmd52_write) {
++			sprintf(temp_str,
++				"The interface doesn't provide cmd52 write\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++		ret =
++		    ssv6xxx_debug_ifops->ifops->
++		    cmd52_write(ssv6xxx_debug_ifops->dev, addr, value);
++		if (ret >= 0) {
++			sprintf(temp_str, "  ==> write odne.\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++	}
++	sprintf(temp_str, "sdio cmd52 fail: %d\n", ret);
++	strcat(ssv6xxx_result_buf, temp_str);
++	return 0;
++}
++
++static struct ssv6xxx_iqk_cfg cmd_iqk_cfg = {
++	SSV6XXX_IQK_CFG_XTAL_26M,
++	SSV6XXX_IQK_CFG_PA_DEF,
++	0,
++	0,
++	26,
++	3,
++	0x75,
++	0x75,
++	0x80,
++	0x80,
++	SSV6XXX_IQK_CMD_INIT_CALI,
++	{SSV6XXX_IQK_TEMPERATURE
++	 + SSV6XXX_IQK_RXDC
++	 + SSV6XXX_IQK_RXRC
++	 + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ},
++};
++
++static int ssv_cmd_iqk(int argc, char *argv[])
++{
++	char temp_str[512], *endp;
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	u32 rxcnt_total, rxcnt_error;
++	sprintf(temp_str, "# got iqk command\n");
++	strcat(ssv6xxx_result_buf, temp_str);
++	if ((argc == 3) && (strcmp(argv[1], "cfg-pa") == 0)) {
++		cmd_iqk_cfg.cfg_pa = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## set cfg_pa as %d\n", cmd_iqk_cfg.cfg_pa);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if ((argc == 3) && (strcmp(argv[1], "cfg-tssi-trgt") == 0)) {
++		cmd_iqk_cfg.cfg_tssi_trgt = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## set cfg_tssi_trgt as %d\n",
++			cmd_iqk_cfg.cfg_tssi_trgt);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if ((argc == 3) && (strcmp(argv[1], "init-cali") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_INIT_CALI;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do init-cali\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-load") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-load\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-load-def") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD_DEF;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-load\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-reset") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_RESET;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-reset\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-set") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_SET;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-set\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-export") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_EXPORT;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-export\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "tk-evm") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_EVM;
++		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do tk-evm\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "tk-tone") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_TONE;
++		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do tk-tone\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "channel") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_CHCH;
++		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do change channel\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 2) && (strcmp(argv[1], "tk-rxcnt-report") == 0)) {
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0043E8, &rxcnt_error)) ;
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0043EC, &rxcnt_total)) ;
++		sprintf(temp_str, "## GN Rx error rate = (%06d/%06d)\n",
++			rxcnt_error, rxcnt_total);
++		strcat(ssv6xxx_result_buf, temp_str);
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0023E8, &rxcnt_error)) ;
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0023EC, &rxcnt_total)) ;
++		sprintf(temp_str, "## B Rx error rate = (%06d/%06d)\n",
++			rxcnt_error, rxcnt_total);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else {
++		sprintf(temp_str, "## invalid iqk command\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "## cmd: cfg-pa/cfg-tssi-trgt\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str,
++			"## cmd: init-cali/rtbl-load/rtbl-load-def/rtbl-reset/rtbl-set/rtbl-export/tk-evm/tk-tone/tk-channel\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "## fx_sel: 0x0008: RXDC\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0010: RXRC\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0020: TXDC\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0040: TXIQ\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0080: RXIQ\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0100: TSSI\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0200: PAPD\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	}
++	skb =
++	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN +
++				PHY_SETTING_SIZE + RF_SETTING_SIZE);
++	if (skb == NULL) {
++		pr_err("ssv command ssvdevice_skb_alloc failure\n");
++		return 0;
++	}
++	if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
++	    (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
++		pr_err("Please check RF or PHY table size\n");
++		BUG_ON(1);
++		return 0;
++	}
++	skb->data_len =
++	    HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
++	host_cmd->len = skb->data_len;
++	cmd_iqk_cfg.phy_tbl_size = PHY_SETTING_SIZE;
++	cmd_iqk_cfg.rf_tbl_size = RF_SETTING_SIZE;
++	memcpy(host_cmd->dat32, &cmd_iqk_cfg, IQK_CFG_LEN);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, asic_rf_setting,
++	       RF_SETTING_SIZE);
++	if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
++		sprintf(temp_str, "## hci send cmd success\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else {
++		sprintf(temp_str, "## hci send cmd fail\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	}
++	ssvdevice_skb_free(skb);
++	return 0;
++}
++
++#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
++    (((a) & 0xff00ff00) >> 8))
++#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
++static int ssv_cmd_version(int argc, char *argv[])
++{
++	char temp_str[256];
++	u32 regval;
++	u64 chip_tag = 0;
++	char chip_id[24] = "";
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_1, &regval)) ;
++	chip_tag = ((u64) regval << 32);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_0, &regval)) ;
++	chip_tag |= (regval);
++	sprintf(temp_str, "CHIP TAG: %llx \n", chip_tag);
++	strcat(ssv6xxx_result_buf, temp_str);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_3, &regval)) ;
++	*((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_2, &regval)) ;
++	*((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_1, &regval)) ;
++	*((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_0, &regval)) ;
++	*((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
++	sprintf(temp_str, "CHIP ID: %s \n", chip_id);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "# current Software mac version: %d\n",
++		ssv_root_version);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "SVN ROOT URL %s \n", SSV_ROOT_URl);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER HOST %s \n", COMPILERHOST);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER DATE %s \n", COMPILERDATE);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER OS %s \n", COMPILEROS);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER OS ARCH %s \n", COMPILEROSARCH);
++	strcat(ssv6xxx_result_buf, temp_str);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, FW_VERSION_REG, &regval)) ;
++	sprintf(temp_str, "Firmware image version: %d\n", regval);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "\n[Compiler Option!!]\n");
++	strcat(ssv6xxx_result_buf, temp_str);
++	return 0;
++}
++
++static int ssv_cmd_tool(int argc, char *argv[])
++{
++	u32 addr, value, count;
++	char tmpbf[12], *endp;
++	int s;
++	if (argc == 4 && strcmp(argv[1], "w") == 0) {
++		addr = simple_strtoul(argv[2], &endp, 16);
++		value = simple_strtoul(argv[3], &endp, 16);
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
++		sprintf(ssv6xxx_result_buf, "ok");
++		return 0;
++	}
++	if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
++		count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
++		addr = simple_strtoul(argv[2], &endp, 16);
++		for (s = 0; s < count; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++			sprintf(tmpbf, "%08x\n", value);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		return 0;
++	}
++	return -1;
++}
++
++struct _ssv6xxx_txtput {
++	struct task_struct *txtput_tsk;
++	struct sk_buff *skb;
++	u32 size_per_frame;
++	u32 loop_times;
++	u32 occupied_tx_pages;
++};
++struct _ssv6xxx_txtput *ssv6xxx_txtput;
++struct _ssv6xxx_txtput ssv_txtput = { NULL, NULL, 0, 0, 0 };
++
++static int txtput_thread_m2(void *data)
++{
++#define Q_DELAY_MS 20
++	struct sk_buff *skb = NULL;
++	struct ssv6200_tx_desc *tx_desc;
++	int qlen = 0, max_qlen, q_delay_urange[2];
++	max_qlen =
++	    (200 * 1000 / 8 * Q_DELAY_MS) / ssv6xxx_txtput->size_per_frame;
++	q_delay_urange[0] = Q_DELAY_MS * 1000;
++	q_delay_urange[1] = q_delay_urange[0] + 1000;
++	pr_debug("max_qlen: %d\n", max_qlen);
++	while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
++		ssv6xxx_txtput->loop_times--;
++		skb = ssvdevice_skb_alloc(ssv6xxx_txtput->size_per_frame);
++		if (skb == NULL) {
++			pr_debug("ssv command txtput_generate_m2 "
++			       "ssvdevice_skb_alloc fail!!!\n");
++			goto end;
++		}
++		skb->data_len = ssv6xxx_txtput->size_per_frame;
++		skb->len = ssv6xxx_txtput->size_per_frame;
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		memset((void *)tx_desc, 0xff, SSV6XXX_TX_DESC_LEN);
++		tx_desc->len = skb->len;
++		tx_desc->c_type = M2_TXREQ;
++		tx_desc->fCmd = (M_ENG_CPU << 4) | M_ENG_HWHCI;
++		tx_desc->reason = ID_TRAP_SW_TXTPUT;
++		qlen = ssv_dbg_ctrl_hci->shi->hci_ops->hci_tx(skb, 0, 0);
++		if (qlen >= max_qlen) {
++			usleep_range(q_delay_urange[0], q_delay_urange[1]);
++		}
++	}
++ end:
++	ssv6xxx_txtput->txtput_tsk = NULL;
++	return 0;
++}
++
++static int txtput_thread(void *data)
++{
++	struct sk_buff *skb = ssv6xxx_txtput->skb;
++	struct ssv6xxx_hci_txq_info2 txq_info2;
++	u32 ret = 0, free_tx_page;
++	int send_cnt;
++	unsigned long start_time, end_time, throughput, time_elapse;
++	throughput =
++	    ssv6xxx_txtput->loop_times * ssv6xxx_txtput->size_per_frame * 8;
++	start_time = jiffies;
++	while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
++		ret =
++		    SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_TX_ID_ALL_INFO2,
++				  (u32 *) & txq_info2);
++		if (ret < 0) {
++			pr_debug("%s, read ADR_TX_ID_ALL_INFO2 failed\n",
++			       __func__);
++			goto end;
++		}
++		free_tx_page =
++		    SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
++		send_cnt = free_tx_page / ssv6xxx_txtput->occupied_tx_pages;
++		while (send_cnt > 0 && ssv6xxx_txtput->loop_times > 0) {
++			send_cnt--;
++			ssv6xxx_txtput->loop_times--;
++			ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb);
++		}
++	}
++	end_time = jiffies;
++	ssvdevice_skb_free(skb);
++	time_elapse = ((end_time - start_time) * 1000) / HZ;
++	if (time_elapse > 0) {
++		throughput = throughput / time_elapse;
++		pr_debug("duration %ldms, avg. throughput %d Kbps\n", time_elapse,
++		       (int)throughput);
++	}
++ end:
++	ssv6xxx_txtput->txtput_tsk = NULL;
++	return 0;
++}
++
++int txtput_generate_m2(u32 size_per_frame, u32 loop_times)
++{
++	ssv6xxx_txtput->size_per_frame = size_per_frame;
++	ssv6xxx_txtput->loop_times = loop_times;
++	ssv6xxx_txtput->txtput_tsk =
++	    kthread_run(txtput_thread_m2, NULL, "txtput_thread_m2");
++	return 0;
++}
++
++int txtput_generate_host_cmd(u32 size_per_frame, u32 loop_times)
++{
++#define PAGESIZE 256
++	struct cfg_host_cmd *host_cmd;
++	struct sk_buff *skb;
++	skb = ssvdevice_skb_alloc(size_per_frame);
++	if (skb == NULL) {
++		pr_debug
++		    ("ssv command txtput_generate_host_cmd ssvdevice_skb_alloc fail!!!\n");
++		return 0;
++	}
++	skb->data_len = size_per_frame;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = TEST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_TX_TPUT;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, skb->data, size_per_frame);
++	ssv6xxx_txtput->occupied_tx_pages =
++	    (size_per_frame / PAGESIZE) + ((size_per_frame % PAGESIZE) != 0);
++	ssv6xxx_txtput->size_per_frame = size_per_frame;
++	ssv6xxx_txtput->loop_times = loop_times;
++	ssv6xxx_txtput->skb = skb;
++	ssv6xxx_txtput->txtput_tsk =
++	    kthread_run(txtput_thread, NULL, "txtput_thread");
++	return 0;
++}
++
++int txtput_tsk_cleanup(void)
++{
++	int ret = 0;
++	if (ssv6xxx_txtput->txtput_tsk) {
++		ret = kthread_stop(ssv6xxx_txtput->txtput_tsk);
++		ssv6xxx_txtput->txtput_tsk = NULL;
++	}
++	return ret;
++}
++
++int watchdog_controller(struct ssv_hw *sh, u8 flag)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int ret = 0;
++	pr_debug("watchdog_controller %d\n", flag);
++	skb = ssvdevice_skb_alloc(HOST_CMD_HDR_LEN);
++	if (skb == NULL) {
++		pr_err("init watchdog_controller failure\n");
++		return (-1);
++	}
++	skb->data_len = HOST_CMD_HDR_LEN;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) flag;
++	host_cmd->len = skb->data_len;
++	sh->hci.hci_ops->hci_send_cmd(skb);
++	ssvdevice_skb_free(skb);
++	return ret;
++}
++
++static int ssv_cmd_txtput(int argc, char *argv[])
++{
++	char tmpbf[64], *endp;
++	u32 size_per_frame, loop_times, pkt_type;
++	ssv6xxx_txtput = &ssv_txtput;
++	if (argc == 2 && !strcmp(argv[1], "stop")) {
++		txtput_tsk_cleanup();
++		return 0;
++	}
++	if (argc != 4) {
++		sprintf(tmpbf, "* txtput stop\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "* txtput [type] [size] [frames]\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "    type(packet type):\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "         0 = host_cmd\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "         1 = m2_type \n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, " EX: txtput 1 14000 9999 \n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	pkt_type = simple_strtoul(argv[1], &endp, 10);
++	size_per_frame = simple_strtoul(argv[2], &endp, 10);
++	loop_times = simple_strtoul(argv[3], &endp, 10);
++	sprintf(tmpbf, "type&size&frames:%d&%d&%d\n", pkt_type, size_per_frame,
++		loop_times);
++	strcat(ssv6xxx_result_buf, tmpbf);
++	if (ssv6xxx_txtput->txtput_tsk) {
++		sprintf(tmpbf, "txtput already in progress\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
++			    (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
++	((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
++	if (pkt_type)
++		txtput_generate_m2(size_per_frame + SSV6XXX_TX_DESC_LEN,
++				   loop_times);
++	else
++		txtput_generate_host_cmd(size_per_frame + HOST_CMD_HDR_LEN,
++					 loop_times);
++	return 0;
++}
++
++static int ssv_cmd_rxtput(int argc, char *argv[])
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	struct sdio_rxtput_cfg cmd_rxtput_cfg;
++	char tmpbf[32], *endp;
++	if (argc != 3) {
++		sprintf(ssv6xxx_result_buf, "rxtput [size] [frames]\n");
++		return 0;
++	}
++	skb =
++	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
++				sizeof(struct sdio_rxtput_cfg));
++	if (skb == NULL) {
++		pr_err("ssv command ssvdevice_skb_alloc fail\n");
++		return 0;
++	}
++	watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
++			    (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
++	((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
++	cmd_rxtput_cfg.size_per_frame = simple_strtoul(argv[1], &endp, 10);
++	cmd_rxtput_cfg.total_frames = simple_strtoul(argv[2], &endp, 10);
++	sprintf(tmpbf, "size&frames:%d&%d\n", cmd_rxtput_cfg.size_per_frame,
++		cmd_rxtput_cfg.total_frames);
++	strcat(ssv6xxx_result_buf, tmpbf);
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct sdio_rxtput_cfg);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_RX_TPUT;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, &cmd_rxtput_cfg,
++	       sizeof(struct sdio_rxtput_cfg));
++	if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
++		strcat(ssv6xxx_result_buf,
++		       "## hci cmd was sent successfully\n");
++	} else {
++		strcat(ssv6xxx_result_buf, "## hci cmd was sent failed\n");
++	}
++	ssvdevice_skb_free(skb);
++	return 0;
++}
++
++static int ssv_cmd_check(int argc, char *argv[])
++{
++	u32 size, i, j, x, y, id, value, address, id_value;
++	char *endp;
++	u32 id_base_address[4];
++	id_base_address[0] = 0xcd010008;
++	id_base_address[1] = 0xcd01000c;
++	id_base_address[2] = 0xcd010054;
++	id_base_address[3] = 0xcd010058;
++	if (argc != 2) {
++		sprintf(ssv6xxx_result_buf, "check [packet size]\n");
++		return 0;
++	}
++	size = simple_strtoul(argv[1], &endp, 10);
++	size = size >> 2;
++	for (x = 0; x < 4; x++) {
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, id_base_address[x], &id_value)) ;
++		for (y = 0; y < 32 && id_value; y++, id_value >>= 1) {
++			if (id_value & 0x1) {
++				id = 32 * x + y;
++				address = 0x80000000 + (id << 16);
++				{
++					for (i = 0; i < size; i += 8) {
++						if (SSV_REG_READ1
++						    (ssv6xxx_debug_ifops,
++						     address, &value)) ;
++						address += 4;
++						for (j = 1; j < 8; j++) {
++							if (SSV_REG_READ1
++							    (ssv6xxx_debug_ifops,
++							     address, &value)) ;
++							address += 4;
++						}
++					}
++				}
++			}
++		}
++	}
++	return 0;
++}
++
++struct ssv_cmd_table cmd_table[] = {
++	{"help", ssv_cmd_help, "ssv6200 command usage."},
++	{"-h", ssv_cmd_help, "ssv6200 command usage."},
++	{"--help", ssv_cmd_help, "ssv6200 command usage."},
++	{"reg", ssv_cmd_reg, "ssv6200 register read/write."},
++	{"cfg", ssv_cmd_cfg, "ssv6200 configuration."},
++	{"sta", ssv_cmd_sta, "svv6200 station info."},
++	{"dump", ssv_cmd_dump, "dump ssv6200 tables."},
++	{"hwq", ssv_cmd_hwq, "hardware queue staus"},
++#ifdef CONFIG_P2P_NOA
++	{"noa", ssv_cmd_noa, "config noa param"},
++#endif
++	{"irq", ssv_cmd_irq, "get sdio irq status."},
++	{"mac", ssv_cmd_mac, "ieee80211 swmac."},
++	{"hci", ssv_cmd_hci, "HCI command."},
++	{"sdio", ssv_cmd_sdio, "SDIO command."},
++	{"iqk", ssv_cmd_iqk, "iqk command"},
++	{"version", ssv_cmd_version, "version information"},
++	{"mib", ssv_cmd_mib, "mib counter related"},
++	{"tool", ssv_cmd_tool, "ssv6200 tool register read/write."},
++	{"rxtput", ssv_cmd_rxtput, "test rx sdio throughput"},
++	{"txtput", ssv_cmd_txtput, "test tx sdio throughput"},
++	{"check", ssv_cmd_check, "dump all allocate packet buffer"},
++	{NULL, NULL, NULL},
++};
++
++int ssv_cmd_submit(char *cmd)
++{
++	struct ssv_cmd_table *sc_tbl;
++	char *pch, ch;
++	int ret;
++	ssv6xxx_debug_ifops = (void *)ssv6xxx_ifdebug_info;
++	strcpy(sg_cmd_buffer, cmd);
++	for (sg_argc = 0, ch = 0, pch = sg_cmd_buffer;
++	     (*pch != 0x00) && (sg_argc < CLI_ARG_SIZE); pch++) {
++		if ((ch == 0) && (*pch != ' ')) {
++			ch = 1;
++			sg_argv[sg_argc] = pch;
++		}
++		if ((ch == 1) && (*pch == ' ')) {
++			*pch = 0x00;
++			ch = 0;
++			sg_argc++;
++		}
++	}
++	if (ch == 1) {
++		sg_argc++;
++	} else if (sg_argc > 0) {
++		*(pch - 1) = ' ';
++	}
++	if (sg_argc > 0) {
++		for (sc_tbl = cmd_table; sc_tbl->cmd; sc_tbl++) {
++			if (!strcmp(sg_argv[0], sc_tbl->cmd)) {
++				if ((sc_tbl->cmd_func_ptr != ssv_cmd_cfg) &&
++				    (!ssv6xxx_debug_ifops->dev ||
++				     !ssv6xxx_debug_ifops->ifops ||
++				     !ssv6xxx_debug_ifops->pdev)) {
++					strcpy(ssv6xxx_result_buf,
++					       "Member of ssv6xxx_ifdebug_info is NULL !\n");
++					return -1;
++				}
++				ssv6xxx_result_buf[0] = 0x00;
++				ret = sc_tbl->cmd_func_ptr(sg_argc, sg_argv);
++				if (ret < 0) {
++					strcpy(ssv6xxx_result_buf,
++					       "Invalid command !\n");
++				}
++				return 0;
++			}
++		}
++		strcpy(ssv6xxx_result_buf, "Command not found !\n");
++	} else {
++		strcpy(ssv6xxx_result_buf, "./cli -h\n");
++	}
++	return 0;
++}
+diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
+new file mode 100644
+index 000000000000..d96bfcc54954
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
+@@ -0,0 +1,50 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_CMD_H_
++#define _SSV_CMD_H_
++#define CLI_BUFFER_SIZE 256
++#define CLI_ARG_SIZE 10
++#define CLI_RESULT_BUF_SIZE (4096)
++#define DEBUG_DIR_ENTRY "ssv"
++#define DEBUG_DEVICETYPE_ENTRY "ssv_devicetype"
++#define DEBUG_CMD_ENTRY "ssv_cmd"
++#define MAX_CHARS_PER_LINE 256
++struct ssv_cmd_table {
++	const char *cmd;
++	int (*cmd_func_ptr)(int, char **);
++	const char *usage;
++};
++struct ssv6xxx_cfg_cmd_table {
++	u8 *cfg_cmd;
++	void *var;
++	u32 arg;
++	int (*translate_func)(u8 *, void *, u32);
++};
++#define SSV_REG_READ1(ops,reg,val) \
++        (ops)->ifops->readreg((ops)->dev, reg, val)
++#define SSV_REG_WRITE1(ops,reg,val) \
++        (ops)->ifops->writereg((ops)->dev, reg, val)
++#define SSV_REG_SET_BITS1(ops,reg,set,clr) \
++    { \
++        u32 reg_val; \
++        SSV_REG_READ(ops, reg, &reg_val); \
++        reg_val &= ~(clr); \
++        reg_val |= (set); \
++        SSV_REG_WRITE(ops, reg, reg_val); \
++    }
++int ssv_cmd_submit(char *cmd);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
+new file mode 100644
+index 000000000000..eb848553798f
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
+@@ -0,0 +1,256 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/slab.h>
++#include <asm/uaccess.h>
++#include <linux/errno.h>
++#include "ssv_cmd.h"
++#include "ssv_cfg.h"
++#include <linux/fs.h>
++#include <asm/uaccess.h>
++#include <linux/buffer_head.h>
++#include <linux/ctype.h>
++
++#ifdef CONFIG_DEBUG_FS
++#include <linux/debugfs.h>
++#endif
++
++char *ssv_initmac = NULL;
++EXPORT_SYMBOL(ssv_initmac);
++module_param(ssv_initmac, charp, 0644);
++MODULE_PARM_DESC(ssv_initmac, "Wi-Fi MAC address");
++
++u32 ssv_devicetype = 0;
++EXPORT_SYMBOL(ssv_devicetype);
++
++#ifdef CONFIG_DEBUG_FS
++static struct dentry *debugfs;
++#endif
++
++struct proc_dir_entry *procfs;
++static char *ssv6xxx_cmd_buf;
++char *ssv6xxx_result_buf;
++extern struct ssv6xxx_cfg_cmd_table cfg_cmds[];
++extern struct ssv6xxx_cfg ssv_cfg;
++char DEFAULT_CFG_PATH[] = "/lib/firmware/ssv6051-wifi.cfg";
++static int ssv6xxx_dbg_open(struct inode *inode, struct file *filp)
++{
++	filp->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t ssv6xxx_dbg_read(struct file *filp, char __user * buffer,
++				size_t count, loff_t * ppos)
++{
++	int len;
++	if (*ppos != 0)
++		return 0;
++	len = strlen(ssv6xxx_result_buf) + 1;
++	if (len == 1)
++		return 0;
++	if (copy_to_user(buffer, ssv6xxx_result_buf, len))
++		return -EFAULT;
++	ssv6xxx_result_buf[0] = 0x00;
++	return len;
++}
++
++static ssize_t ssv6xxx_dbg_write(struct file *filp, const char __user * buffer,
++				 size_t count, loff_t * ppos)
++{
++	if (*ppos != 0 || count > 255)
++		return 0;
++	if (copy_from_user(ssv6xxx_cmd_buf, buffer, count))
++		return -EFAULT;
++	ssv6xxx_cmd_buf[count - 1] = 0x00;
++	ssv_cmd_submit(ssv6xxx_cmd_buf);
++	return count;
++}
++
++size_t read_line(struct file * fp, char *buf, size_t size)
++{
++	size_t num_read = 0;
++	size_t total_read = 0;
++	char *buffer;
++	char ch;
++	size_t start_ignore = 0;
++	if (size <= 0 || buf == NULL) {
++		total_read = -EINVAL;
++		return -EINVAL;
++	}
++	buffer = buf;
++	for (;;) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
++		num_read = kernel_read(fp, &ch, 1, &fp->f_pos);
++#else
++		mm_segment_t fs;
++		fs = get_fs();
++		set_fs(KERNEL_DS);
++		num_read = vfs_read(fp, &ch, 1, &fp->f_pos);
++		set_fs(fs);
++#endif
++		if (num_read < 0) {
++			if (num_read == EINTR)
++				continue;
++			else
++				return -1;
++		} else if (num_read == 0) {
++			if (total_read == 0)
++				return 0;
++			else
++				break;
++		} else {
++			if (ch == '#')
++				start_ignore = 1;
++			if (total_read < size - 1) {
++				total_read++;
++				if (start_ignore)
++					*buffer++ = '\0';
++				else
++					*buffer++ = ch;
++			}
++			if (ch == '\n')
++				break;
++		}
++	}
++	*buffer = '\0';
++	return total_read;
++}
++
++int ischar(char *c)
++{
++	int is_char = 1;
++	while (*c) {
++		if (isalpha(*c) || isdigit(*c) || *c == '_' || *c == ':'
++		    || *c == '/' || *c == '.' || *c == '-')
++			c++;
++		else {
++			is_char = 0;
++			break;
++		}
++	}
++	return is_char;
++}
++
++void sta_cfg_set(void)
++{
++	struct file *fp = (struct file *)NULL;
++	char buf[MAX_CHARS_PER_LINE], cfg_cmd[32], cfg_value[32];
++	size_t s, read_len = 0, is_cmd_support = 0;
++
++	memset(&ssv_cfg, 0, sizeof(ssv_cfg));
++	memset(buf, 0, sizeof(buf));
++	fp = filp_open(DEFAULT_CFG_PATH, O_RDONLY, 0);
++	if (IS_ERR(fp) || fp == NULL) {
++		WARN_ON(1);
++		return;
++	}
++	if (fp->f_path.dentry == NULL) {
++		WARN_ON(1);
++		return;
++	}
++	do {
++		memset(cfg_cmd, '\0', sizeof(cfg_cmd));
++		memset(cfg_value, '\0', sizeof(cfg_value));
++		read_len = read_line(fp, buf, MAX_CHARS_PER_LINE);
++		sscanf(buf, "%s = %s", cfg_cmd, cfg_value);
++		if (!ischar(cfg_cmd) || !ischar(cfg_value)) {
++			pr_warn("Invalid configuration parameter: %s\n", buf);
++			continue;
++		}
++		is_cmd_support = 0;
++		for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
++			if (strcmp(cfg_cmds[s].cfg_cmd, cfg_cmd) == 0) {
++				cfg_cmds[s].translate_func(cfg_value,
++							   cfg_cmds[s].var,
++							   cfg_cmds[s].arg);
++				is_cmd_support = 1;
++				break;
++			}
++		}
++		if (!is_cmd_support && strlen(cfg_cmd) > 0) {
++			pr_warn("Unsupported configuration command: %s", cfg_cmd);
++		}
++	} while (read_len > 0);
++	filp_close(fp, NULL);
++}
++
++static const struct file_operations ssv6xxx_dbg_fops = {
++	.owner = THIS_MODULE,
++	.open = ssv6xxx_dbg_open,
++	.read = ssv6xxx_dbg_read,
++	.write = ssv6xxx_dbg_write,
++};
++
++extern int ssv6xxx_hci_init(void);
++extern void ssv6xxx_hci_exit(void);
++extern int ssv6xxx_init(void);
++extern void ssv6xxx_exit(void);
++extern int ssv6xxx_sdio_init(void);
++extern void ssv6xxx_sdio_exit(void);
++
++int ssvdevice_init(void)
++{
++	ssv6xxx_cmd_buf =
++	    (char *)kzalloc(CLI_BUFFER_SIZE + CLI_RESULT_BUF_SIZE, GFP_KERNEL);
++	if (!ssv6xxx_cmd_buf)
++		return -ENOMEM;
++	ssv6xxx_result_buf = ssv6xxx_cmd_buf + CLI_BUFFER_SIZE;
++	ssv6xxx_cmd_buf[0] = 0x00;
++	ssv6xxx_result_buf[0] = 0x00;
++#ifdef CONFIG_DEBUG_FS
++	debugfs = debugfs_create_dir(DEBUG_DIR_ENTRY, NULL);
++	if (!debugfs)
++		return -ENOMEM;
++	debugfs_create_u32(DEBUG_DEVICETYPE_ENTRY, S_IRUGO | S_IWUSR, debugfs,
++			   &ssv_devicetype);
++	debugfs_create_file(DEBUG_CMD_ENTRY, S_IRUGO | S_IWUSR, debugfs, NULL,
++			    &ssv6xxx_dbg_fops);
++#endif
++	sta_cfg_set();
++	{
++		int ret;
++		ret = ssv6xxx_hci_init();
++		if (!ret) {
++			ret = ssv6xxx_init();
++		}
++		if (!ret) {
++			ret = ssv6xxx_sdio_init();
++		}
++		return ret;
++	}
++
++	return 0;
++}
++
++void ssvdevice_exit(void)
++{
++
++	ssv6xxx_exit();
++	ssv6xxx_hci_exit();
++	ssv6xxx_sdio_exit();
++
++#ifdef CONFIG_DEBUG_FS
++	debugfs_remove_recursive(debugfs);
++#endif
++	kfree(ssv6xxx_cmd_buf);
++}
++
++EXPORT_SYMBOL(ssvdevice_init);
++EXPORT_SYMBOL(ssvdevice_exit);
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-0002-rockchip-from-list.patch b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-0002-rockchip-from-list.patch
new file mode 100644
index 000000000000..517eaf53c059
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-0002-rockchip-from-list.patch
@@ -0,0 +1,131 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 17 Feb 2019 22:14:38 +0000
+Subject: [PATCH] mmc: core: set initial signal voltage on power off
+
+Some boards have SD card connectors where the power rail cannot be switched
+off by the driver. If the card has not been power cycled, it may still be
+using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
+will fail to boot from a UHS card that continue to use 1.8V signaling.
+
+Set initial signal voltage in mmc_power_off() to allow re-boot to function.
+
+This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
+same issue have been seen on some Rockchip RK3399 boards.
+
+I am sending this as a RFC because I have no insights into SD/MMC subsystem,
+this change fix a re-boot issue on my boards and does not break emmc/sdio.
+Is this an acceptable workaround? Any advice is appreciated.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/mmc/core/core.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
+index ef53a2578824..d4c53074154a 100644
+--- a/drivers/mmc/core/core.c
++++ b/drivers/mmc/core/core.c
+@@ -1358,6 +1358,14 @@ void mmc_power_off(struct mmc_host *host)
+ 	if (host->ios.power_mode == MMC_POWER_OFF)
+ 		return;
+ 
++	mmc_set_initial_signal_voltage(host);
++
++	/*
++	 * This delay should be sufficient to allow the power supply
++	 * to reach the minimum voltage.
++	 */
++	mmc_delay(host->ios.power_delay_ms);
++
+ 	mmc_pwrseq_power_off(host);
+ 
+ 	host->ios.clock = 0;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Wed, 23 Jun 2021 16:59:18 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add sdmmc_ext for RK3328
+
+RK3328 SoC has a fourth mmc controller called SDMMC_EXT. Some
+boards have sdio wifi connected to it. In order to use it
+one would have to add the pinctrls from sdmmc0ext group which
+is done on board level.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 49ae15708a0b..60348d517efb 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -993,6 +993,20 @@ usb_host0_ohci: usb@ff5d0000 {
+ 		status = "disabled";
+ 	};
+ 
++	sdmmc_ext: mmc@ff5f0000 {
++		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
++		reg = <0x0 0xff5f0000 0x0 0x4000>;
++		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
++			 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
++		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++		fifo-depth = <0x100>;
++		max-frequency = <150000000>;
++		resets = <&cru SRST_SDMMCEXT>;
++		reset-names = "reset";
++		status = "disabled";
++	};
++
+ 	usbdrd3: usb@ff600000 {
+ 		compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
+ 		reg = <0x0 0xff600000 0x0 0x100000>;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Wed, 23 Jun 2021 17:02:08 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add sdmmc/sdio/emmc reset controls for
+ RK3328
+
+The DW MCI controller driver will use them to reset the IP block before
+initialisation.
+
+Fixes: d717f7352ec6 ("arm64: dts: rockchip: add sdmmc/sdio/emmc nodes for RK3328 SoCs")
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 60348d517efb..d7e44d174d7b 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -871,6 +871,8 @@ sdmmc: mmc@ff500000 {
+ 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ 		fifo-depth = <0x100>;
+ 		max-frequency = <150000000>;
++		resets = <&cru SRST_MMC0>;
++		reset-names = "reset";
+ 		status = "disabled";
+ 	};
+ 
+@@ -883,6 +885,8 @@ sdio: mmc@ff510000 {
+ 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ 		fifo-depth = <0x100>;
+ 		max-frequency = <150000000>;
++		resets = <&cru SRST_SDIO>;
++		reset-names = "reset";
+ 		status = "disabled";
+ 	};
+ 
+@@ -895,6 +899,8 @@ emmc: mmc@ff520000 {
+ 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ 		fifo-depth = <0x100>;
+ 		max-frequency = <150000000>;
++		resets = <&cru SRST_EMMC>;
++		reset-names = "reset";
+ 		status = "disabled";
+ 	};
+ 
diff --git a/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-0011-v4l2-from-list.patch b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-0011-v4l2-from-list.patch
new file mode 100644
index 000000000000..ed0c61c2cb9c
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-0011-v4l2-from-list.patch
@@ -0,0 +1,659 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:35 +0000
+Subject: [PATCH] media: v4l2-common: Add helpers to calculate bytesperline and
+ sizeimage
+
+Add helper functions to calculate plane bytesperline and sizeimage, these
+new helpers consider block width and height when calculating plane
+bytesperline and sizeimage.
+
+This prepare support for new pixel formats added in next patch that make
+use of block width and height.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/media/v4l2-core/v4l2-common.c | 77 +++++++++++++--------------
+ 1 file changed, 38 insertions(+), 39 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
+index e0fbe6ba4b6c..cb2f1acab7cf 100644
+--- a/drivers/media/v4l2-core/v4l2-common.c
++++ b/drivers/media/v4l2-core/v4l2-common.c
+@@ -338,6 +338,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf
+ 	return info->block_h[plane];
+ }
+ 
++static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane,
++						   unsigned int width)
++{
++	unsigned int hdiv = plane ? info->hdiv : 1;
++	unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane],
++				v4l2_format_block_width(info, plane) *
++				v4l2_format_block_height(info, plane));
++
++	return DIV_ROUND_UP(bytes, hdiv);
++}
++
++static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane,
++						    unsigned int height)
++{
++	unsigned int vdiv = plane ? info->vdiv : 1;
++	unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane));
++
++	return DIV_ROUND_UP(lines, vdiv);
++}
++
++static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane,
++						  unsigned int width, unsigned int height)
++{
++	return v4l2_format_plane_width(info, plane, width) *
++	       v4l2_format_plane_height(info, plane, height);
++}
++
+ void v4l2_apply_frmsize_constraints(u32 *width, u32 *height,
+ 				    const struct v4l2_frmsize_stepwise *frmsize)
+ {
+@@ -373,37 +400,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
+ 
+ 	if (info->mem_planes == 1) {
+ 		plane = &pixfmt->plane_fmt[0];
+-		plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0];
++		plane->bytesperline = v4l2_format_plane_width(info, 0, width);
+ 		plane->sizeimage = 0;
+ 
+-		for (i = 0; i < info->comp_planes; i++) {
+-			unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+-			unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+-			unsigned int aligned_width;
+-			unsigned int aligned_height;
+-
+-			aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
+-			aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
+-
+-			plane->sizeimage += info->bpp[i] *
+-				DIV_ROUND_UP(aligned_width, hdiv) *
+-				DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i];
+-		}
++		for (i = 0; i < info->comp_planes; i++)
++			plane->sizeimage +=
++				v4l2_format_plane_size(info, i, width, height);
+ 	} else {
+ 		for (i = 0; i < info->comp_planes; i++) {
+-			unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+-			unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+-			unsigned int aligned_width;
+-			unsigned int aligned_height;
+-
+-			aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
+-			aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
+-
+ 			plane = &pixfmt->plane_fmt[i];
+ 			plane->bytesperline =
+-				info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv) / info->bpp_div[i];
+-			plane->sizeimage =
+-				plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv);
++				v4l2_format_plane_width(info, i, width);
++			plane->sizeimage = plane->bytesperline *
++				v4l2_format_plane_height(info, i, height);
+ 		}
+ 	}
+ 	return 0;
+@@ -427,22 +436,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
+ 	pixfmt->width = width;
+ 	pixfmt->height = height;
+ 	pixfmt->pixelformat = pixelformat;
+-	pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0];
++	pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width);
+ 	pixfmt->sizeimage = 0;
+ 
+-	for (i = 0; i < info->comp_planes; i++) {
+-		unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+-		unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+-		unsigned int aligned_width;
+-		unsigned int aligned_height;
+-
+-		aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
+-		aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
+-
+-		pixfmt->sizeimage += info->bpp[i] *
+-			DIV_ROUND_UP(aligned_width, hdiv) *
+-			DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i];
+-	}
++	for (i = 0; i < info->comp_planes; i++)
++		pixfmt->sizeimage +=
++			v4l2_format_plane_size(info, i, width, height);
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt);
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:36 +0000
+Subject: [PATCH] media: v4l2: Add NV15 and NV20 pixel formats
+
+Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for
+10-bit buffers.
+
+NV15 and NV20 is a packed 10-bit 4:2:0/4:2:2 semi-planar Y/UV format
+similar to P010 and P210 but has no padding between components. Instead,
+luminance and chrominance samples are grouped into 4s so that each group is
+packed into an integer number of bytes:
+
+YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
+
+The '15' and '20' suffix refers to the optimum effective bits per pixel
+which is achieved when the total number of luminance samples is a multiple
+of 8 for NV15 and 4 for NV20.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/media/v4l2-core/v4l2-common.c | 3 +++
+ drivers/media/v4l2-core/v4l2-ioctl.c  | 2 ++
+ include/uapi/linux/videodev2.h        | 3 +++
+ 3 files changed, 8 insertions(+)
+
+diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
+index cb2f1acab7cf..8446a1deffd8 100644
+--- a/drivers/media/v4l2-core/v4l2-common.c
++++ b/drivers/media/v4l2-core/v4l2-common.c
+@@ -268,6 +268,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
+ 		{ .format = V4L2_PIX_FMT_NV42,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ 		{ .format = V4L2_PIX_FMT_P010,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 },
+ 
++		{ .format = V4L2_PIX_FMT_NV15,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
++		{ .format = V4L2_PIX_FMT_NV20,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
++
+ 		{ .format = V4L2_PIX_FMT_YUV410,  .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 4 },
+ 		{ .format = V4L2_PIX_FMT_YVU410,  .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 4 },
+ 		{ .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 1 },
+diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
+index e6fd355a2e92..24771edaa4f2 100644
+--- a/drivers/media/v4l2-core/v4l2-ioctl.c
++++ b/drivers/media/v4l2-core/v4l2-ioctl.c
+@@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
+ 	case V4L2_PIX_FMT_NV42:		descr = "Y/VU 4:4:4"; break;
+ 	case V4L2_PIX_FMT_P010:		descr = "10-bit Y/UV 4:2:0"; break;
+ 	case V4L2_PIX_FMT_P012:		descr = "12-bit Y/UV 4:2:0"; break;
++	case V4L2_PIX_FMT_NV15:		descr = "10-bit Y/UV 4:2:0 (Packed)"; break;
++	case V4L2_PIX_FMT_NV20:		descr = "10-bit Y/UV 4:2:2 (Packed)"; break;
+ 	case V4L2_PIX_FMT_NV12_4L4:	descr = "Y/UV 4:2:0 (4x4 Linear)"; break;
+ 	case V4L2_PIX_FMT_NV12_16L16:	descr = "Y/UV 4:2:0 (16x16 Linear)"; break;
+ 	case V4L2_PIX_FMT_NV12_32L32:   descr = "Y/UV 4:2:0 (32x32 Linear)"; break;
+diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
+index 01e630f2ec78..cea44992aea3 100644
+--- a/include/uapi/linux/videodev2.h
++++ b/include/uapi/linux/videodev2.h
+@@ -628,6 +628,9 @@ struct v4l2_pix_format {
+ #define V4L2_PIX_FMT_NV42    v4l2_fourcc('N', 'V', '4', '2') /* 24  Y/VU 4:4:4  */
+ #define V4L2_PIX_FMT_P010    v4l2_fourcc('P', '0', '1', '0') /* 24  Y/UV 4:2:0 10-bit per component */
+ 
++#define V4L2_PIX_FMT_NV15    v4l2_fourcc('N', 'V', '1', '5') /* 15  Y/UV 4:2:0 10-bit packed */
++#define V4L2_PIX_FMT_NV20    v4l2_fourcc('N', 'V', '2', '0') /* 20  Y/UV 4:2:2 10-bit packed */
++
+ /* two non contiguous planes - one Y, one Cr + Cb interleaved  */
+ #define V4L2_PIX_FMT_NV12M   v4l2_fourcc('N', 'M', '1', '2') /* 12  Y/UV 4:2:0  */
+ #define V4L2_PIX_FMT_NV21M   v4l2_fourcc('N', 'M', '2', '1') /* 21  Y/VU 4:2:0  */
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:36 +0000
+Subject: [PATCH] media: rkvdec: h264: Use bytesperline and buffer height to
+ calculate stride
+
+Use bytesperline and buffer height to calculate the strides configured.
+
+This does not really change anything other than ensuring the bytesperline
+that is signaled to userspace matches what is configured in HW.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/rkvdec/rkvdec-h264.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
+index 4fc167b42cf0..a8635105e387 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
+@@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx,
+ 	dma_addr_t rlc_addr;
+ 	dma_addr_t refer_addr;
+ 	u32 rlc_len;
+-	u32 hor_virstride = 0;
+-	u32 ver_virstride = 0;
+-	u32 y_virstride = 0;
++	u32 hor_virstride;
++	u32 ver_virstride;
++	u32 y_virstride;
+ 	u32 yuv_virstride = 0;
+ 	u32 offset;
+ 	dma_addr_t dst_addr;
+@@ -909,8 +909,8 @@ static void config_registers(struct rkvdec_ctx *ctx,
+ 
+ 	f = &ctx->decoded_fmt;
+ 	dst_fmt = &f->fmt.pix_mp;
+-	hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8;
+-	ver_virstride = round_up(dst_fmt->height, 16);
++	hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
++	ver_virstride = dst_fmt->height;
+ 	y_virstride = hor_virstride * ver_virstride;
+ 
+ 	if (sps->chroma_format_idc == 0)
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:37 +0000
+Subject: [PATCH] media: rkvdec: Extract rkvdec_fill_decoded_pixfmt helper
+ method
+
+This extract setting decoded pixfmt into a helper method, current code is
+replaced with a call to the new helper method.
+
+The helper method is also called from a new function in next patch.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/rkvdec/rkvdec.c | 29 ++++++++++++++-------------
+ 1 file changed, 15 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index 7bab7586918c..40cc791aef26 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -27,6 +27,17 @@
+ #include "rkvdec.h"
+ #include "rkvdec-regs.h"
+ 
++static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
++				       struct v4l2_pix_format_mplane *pix_mp)
++{
++	v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
++			    pix_mp->width, pix_mp->height);
++	pix_mp->plane_fmt[0].sizeimage += 128 *
++		DIV_ROUND_UP(pix_mp->width, 16) *
++		DIV_ROUND_UP(pix_mp->height, 16);
++	pix_mp->field = V4L2_FIELD_NONE;
++}
++
+ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
+ {
+ 	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
+@@ -192,13 +203,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
+ 
+ 	rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
+ 	f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+-	v4l2_fill_pixfmt_mp(&f->fmt.pix_mp,
+-			    ctx->coded_fmt_desc->decoded_fmts[0],
+-			    ctx->coded_fmt.fmt.pix_mp.width,
+-			    ctx->coded_fmt.fmt.pix_mp.height);
+-	f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 *
+-		DIV_ROUND_UP(f->fmt.pix_mp.width, 16) *
+-		DIV_ROUND_UP(f->fmt.pix_mp.height, 16);
++	f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
++	f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height;
++	rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp);
+ }
+ 
+ static int rkvdec_enum_framesizes(struct file *file, void *priv,
+@@ -264,13 +271,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
+ 				       &pix_mp->height,
+ 				       &coded_desc->frmsize);
+ 
+-	v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
+-			    pix_mp->width, pix_mp->height);
+-	pix_mp->plane_fmt[0].sizeimage +=
+-		128 *
+-		DIV_ROUND_UP(pix_mp->width, 16) *
+-		DIV_ROUND_UP(pix_mp->height, 16);
+-	pix_mp->field = V4L2_FIELD_NONE;
++	rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
+ 
+ 	return 0;
+ }
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:37 +0000
+Subject: [PATCH] media: rkvdec: Lock capture pixel format in s_ctrl and s_fmt
+
+Add an optional valid_fmt operation that should return the valid
+pixelformat of CAPTURE buffers.
+
+This is used in next patch to ensure correct pixelformat is used for 10-bit
+and 4:2:2 content.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/rkvdec/rkvdec.c | 67 +++++++++++++++++++++++----
+ drivers/staging/media/rkvdec/rkvdec.h |  2 +
+ 2 files changed, 61 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index 40cc791aef26..e93e1cb0f829 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -38,19 +38,56 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
+ 	pix_mp->field = V4L2_FIELD_NONE;
+ }
+ 
++static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
++{
++	const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc;
++
++	if (coded_desc->ops->valid_fmt)
++		return coded_desc->ops->valid_fmt(ctx, ctrl);
++
++	return ctx->valid_fmt;
++}
++
+ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
+ {
+ 	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
+ 	const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc;
+ 
+-	if (desc->ops->try_ctrl)
+-		return desc->ops->try_ctrl(ctx, ctrl);
++	if (desc->ops->try_ctrl) {
++		int ret;
++		ret = desc->ops->try_ctrl(ctx, ctrl);
++		if (ret)
++			return ret;
++	}
++
++	if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
++		/* Only current valid format */
++		return -EINVAL;
++
++	return 0;
++}
++
++static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
++
++	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) {
++		ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl);
++		if (ctx->valid_fmt) {
++			struct v4l2_pix_format_mplane *pix_mp;
++
++			pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
++			pix_mp->pixelformat = ctx->valid_fmt;
++			rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
++		}
++	}
+ 
+ 	return 0;
+ }
+ 
+ static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
+ 	.try_ctrl = rkvdec_try_ctrl,
++	.s_ctrl = rkvdec_s_ctrl,
+ };
+ 
+ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
+@@ -201,6 +238,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
+ {
+ 	struct v4l2_format *f = &ctx->decoded_fmt;
+ 
++	ctx->valid_fmt = 0;
+ 	rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
+ 	f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+ 	f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
+@@ -256,13 +294,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
+ 	if (WARN_ON(!coded_desc))
+ 		return -EINVAL;
+ 
+-	for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
+-		if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
+-			break;
+-	}
++	if (ctx->valid_fmt) {
++		pix_mp->pixelformat = ctx->valid_fmt;
++	} else {
++		for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
++			if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
++				break;
++		}
+ 
+-	if (i == coded_desc->num_decoded_fmts)
+-		pix_mp->pixelformat = coded_desc->decoded_fmts[0];
++		if (i == coded_desc->num_decoded_fmts)
++			pix_mp->pixelformat = coded_desc->decoded_fmts[0];
++	}
+ 
+ 	/* Always apply the frmsize constraint of the coded end. */
+ 	pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
+@@ -326,6 +368,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv,
+ 		return ret;
+ 
+ 	ctx->decoded_fmt = *f;
++	ctx->valid_fmt = f->fmt.pix_mp.pixelformat;
+ 	return 0;
+ }
+ 
+@@ -429,6 +472,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv,
+ 	if (WARN_ON(!ctx->coded_fmt_desc))
+ 		return -EINVAL;
+ 
++	if (ctx->valid_fmt) {
++		if (f->index)
++			return -EINVAL;
++
++		f->pixelformat = ctx->valid_fmt;
++		return 0;
++	}
++
+ 	if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
+ 		return -EINVAL;
+ 
+diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
+index 633335ebb9c4..b9e219438bc9 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.h
++++ b/drivers/staging/media/rkvdec/rkvdec.h
+@@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
+ struct rkvdec_coded_fmt_ops {
+ 	int (*adjust_fmt)(struct rkvdec_ctx *ctx,
+ 			  struct v4l2_format *f);
++	u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl);
+ 	int (*start)(struct rkvdec_ctx *ctx);
+ 	void (*stop)(struct rkvdec_ctx *ctx);
+ 	int (*run)(struct rkvdec_ctx *ctx);
+@@ -101,6 +102,7 @@ struct rkvdec_ctx {
+ 	struct v4l2_fh fh;
+ 	struct v4l2_format coded_fmt;
+ 	struct v4l2_format decoded_fmt;
++	u32 valid_fmt;
+ 	const struct rkvdec_coded_fmt_desc *coded_fmt_desc;
+ 	struct v4l2_ctrl_handler ctrl_hdl;
+ 	struct rkvdec_dev *dev;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:37 +0000
+Subject: [PATCH] media: rkvdec: h264: Support High 10 and 4:2:2 profiles
+
+Add support and enable decoding of H264 High 10 and 4:2:2 profiles.
+
+Decoded CAPTURE buffer width is aligned to 64 pixels to accommodate HW
+requirement on 10-bit format buffers.
+
+The new valid_fmt operation is implemented and return a valid pixelformat
+for the provided SPS control.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/rkvdec/rkvdec-h264.c | 33 ++++++++++++++++------
+ drivers/staging/media/rkvdec/rkvdec.c      | 19 +++++++++----
+ 2 files changed, 37 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
+index a8635105e387..0069d3d198db 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
+@@ -1031,19 +1031,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
+ {
+ 	unsigned int width, height;
+ 
+-	/*
+-	 * TODO: The hardware supports 10-bit and 4:2:2 profiles,
+-	 * but it's currently broken in the driver.
+-	 * Reject them for now, until it's fixed.
+-	 */
+-	if (sps->chroma_format_idc > 1)
+-		/* Only 4:0:0 and 4:2:0 are supported */
++	if (sps->chroma_format_idc > 2)
++		/* Only 4:0:0, 4:2:0 and 4:2:2 are supported */
+ 		return -EINVAL;
+ 	if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
+ 		/* Luma and chroma bit depth mismatch */
+ 		return -EINVAL;
+-	if (sps->bit_depth_luma_minus8 != 0)
+-		/* Only 8-bit is supported */
++	if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
++		/* Only 8-bit and 10-bit is supported */
+ 		return -EINVAL;
+ 
+ 	width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
+@@ -1064,6 +1059,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
+ 	return 0;
+ }
+ 
++static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
++{
++	const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
++
++	if (sps->bit_depth_luma_minus8 == 0) {
++		if (sps->chroma_format_idc == 2)
++			return V4L2_PIX_FMT_NV16;
++		else
++			return V4L2_PIX_FMT_NV12;
++	} else if (sps->bit_depth_luma_minus8 == 2) {
++		if (sps->chroma_format_idc == 2)
++			return V4L2_PIX_FMT_NV20;
++		else
++			return V4L2_PIX_FMT_NV15;
++	}
++
++	return 0;
++}
++
+ static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
+ {
+ 	struct rkvdec_dev *rkvdec = ctx->dev;
+@@ -1185,6 +1199,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+ 
+ const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
+ 	.adjust_fmt = rkvdec_h264_adjust_fmt,
++	.valid_fmt = rkvdec_h264_valid_fmt,
+ 	.start = rkvdec_h264_start,
+ 	.stop = rkvdec_h264_stop,
+ 	.run = rkvdec_h264_run,
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index e93e1cb0f829..4f5436c89e08 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
+ 				       struct v4l2_pix_format_mplane *pix_mp)
+ {
+ 	v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
+-			    pix_mp->width, pix_mp->height);
++			    ALIGN(pix_mp->width, 64), pix_mp->height);
+ 	pix_mp->plane_fmt[0].sizeimage += 128 *
+ 		DIV_ROUND_UP(pix_mp->width, 16) *
+ 		DIV_ROUND_UP(pix_mp->height, 16);
+@@ -136,8 +136,11 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
+ 	.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
+ };
+ 
+-static const u32 rkvdec_h264_vp9_decoded_fmts[] = {
++static const u32 rkvdec_h264_decoded_fmts[] = {
+ 	V4L2_PIX_FMT_NV12,
++	V4L2_PIX_FMT_NV15,
++	V4L2_PIX_FMT_NV16,
++	V4L2_PIX_FMT_NV20,
+ };
+ 
+ static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = {
+@@ -160,6 +163,10 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = {
+ 	.num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs),
+ };
+ 
++static const u32 rkvdec_vp9_decoded_fmts[] = {
++	V4L2_PIX_FMT_NV12,
++};
++
+ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 	{
+ 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
+@@ -173,8 +180,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 		},
+ 		.ctrls = &rkvdec_h264_ctrls,
+ 		.ops = &rkvdec_h264_fmt_ops,
+-		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts),
+-		.decoded_fmts = rkvdec_h264_vp9_decoded_fmts,
++		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
++		.decoded_fmts = rkvdec_h264_decoded_fmts,
+ 		.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+ 	},
+ 	{
+@@ -189,8 +196,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 		},
+ 		.ctrls = &rkvdec_vp9_ctrls,
+ 		.ops = &rkvdec_vp9_fmt_ops,
+-		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts),
+-		.decoded_fmts = rkvdec_h264_vp9_decoded_fmts,
++		.num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
++		.decoded_fmts = rkvdec_vp9_decoded_fmts,
+ 	}
+ };
+ 
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 27 Mar 2022 14:18:07 +0200
+Subject: [PATCH] media: rkvdec-h264: Don't hardcode SPS/PPS parameters
+
+Some SPS/PPS parameters are currently hardcoded in the driver
+even though so do exist in the uapi which is stable by now.
+
+Use them instead of hardcoding them.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/staging/media/rkvdec/rkvdec-h264.c | 13 +++++++------
+ 1 file changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
+index 0069d3d198db..2c27acaba85e 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
+@@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
+ 
+ #define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
+ 	/* write sps */
+-	WRITE_PPS(0xf, SEQ_PARAMETER_SET_ID);
+-	WRITE_PPS(0xff, PROFILE_IDC);
+-	WRITE_PPS(1, CONSTRAINT_SET3_FLAG);
++	WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
++	WRITE_PPS(sps->profile_idc, PROFILE_IDC);
++	WRITE_PPS((sps->constraint_set_flags & 1 << 3) ? 1 : 0, CONSTRAINT_SET3_FLAG);
+ 	WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
+ 	WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA);
+ 	WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA);
+-	WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
++	WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS),
++		  QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
+ 	WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
+ 	WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
+ 	WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE);
+@@ -688,8 +689,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
+ 		  DIRECT_8X8_INFERENCE_FLAG);
+ 
+ 	/* write pps */
+-	WRITE_PPS(0xff, PIC_PARAMETER_SET_ID);
+-	WRITE_PPS(0x1f, PPS_SEQ_PARAMETER_SET_ID);
++	WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
++	WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
+ 	WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE),
+ 		  ENTROPY_CODING_MODE_FLAG);
+ 	WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT),
diff --git a/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1000-drm-rockchip.patch b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1000-drm-rockchip.patch
new file mode 100644
index 000000000000..c7796aaafe7c
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1000-drm-rockchip.patch
@@ -0,0 +1,2956 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 3 May 2020 16:51:31 +0000
+Subject: [PATCH] drm/rockchip: vop: filter modes outside 0.5% pixel clock
+ tolerance
+
+Filter modes that require a pixel clock that differ more then 0.5%
+from the requested pixel clock.
+
+This filter is only applied to tmds only connector and/or encoders.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 54 +++++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index dbe4d411b30f..fac23d370ee0 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1206,6 +1206,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
+ 	spin_unlock_irqrestore(&vop->irq_lock, flags);
+ }
+ 
++static bool vop_crtc_is_tmds(struct drm_crtc *crtc)
++{
++	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
++	struct drm_encoder *encoder;
++
++	switch (s->output_type) {
++	case DRM_MODE_CONNECTOR_LVDS:
++	case DRM_MODE_CONNECTOR_DSI:
++		return false;
++	case DRM_MODE_CONNECTOR_eDP:
++	case DRM_MODE_CONNECTOR_HDMIA:
++	case DRM_MODE_CONNECTOR_DisplayPort:
++		return true;
++	}
++
++	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
++		if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
++			return true;
++
++	return false;
++}
++
++/*
++ * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance.
++ * The CVT spec reuses that tolerance in its examples.
++ */
++#define	CLOCK_TOLERANCE_PER_MILLE	5
++
++static enum drm_mode_status vop_crtc_mode_valid5(struct drm_crtc *crtc,
++					const struct drm_display_mode *mode)
++{
++	struct vop *vop = to_vop(crtc);
++	long rounded_rate;
++	long lowest, highest;
++
++	if (!vop_crtc_is_tmds(crtc))
++		return MODE_OK;
++
++	rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999);
++	if (rounded_rate < 0)
++		return MODE_NOCLOCK;
++
++	lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE);
++	if (rounded_rate < lowest)
++		return MODE_CLOCK_LOW;
++
++	highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE);
++	if (rounded_rate > highest)
++		return MODE_CLOCK_HIGH;
++
++	return MODE_OK;
++}
++
+ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
+ 				const struct drm_display_mode *mode,
+ 				struct drm_display_mode *adjusted_mode)
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 20 Jul 2020 15:15:50 +0000
+Subject: [PATCH] drm/rockchip: vop: filter interlaced modes
+
+The current version of the driver does not support interlaced modes,
+lets filter any interlaced mode.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index fac23d370ee0..9f7326c5b1f5 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1244,6 +1244,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
+ 	if (!vop_crtc_is_tmds(crtc))
+ 		return MODE_OK;
+ 
++	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++		return MODE_NO_INTERLACE;
++
+ 	rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999);
+ 	if (rounded_rate < 0)
+ 		return MODE_NOCLOCK;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 20 Jul 2020 11:46:16 +0000
+Subject: [PATCH] drm/rockchip: vop: filter modes above max output supported
+
+Filter any mode with a resolution not supported by the VOP.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 48 +++++++++++++++------
+ 1 file changed, 34 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index 9f7326c5b1f5..30e252ba7184 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1228,6 +1228,24 @@ static bool vop_crtc_is_tmds(struct drm_crtc *crtc)
+ 	return false;
+ }
+ 
++static enum drm_mode_status vop_crtc_size_valid(struct drm_crtc *crtc,
++					const struct drm_display_mode *mode)
++{
++	struct vop *vop = to_vop(crtc);
++	const struct vop_rect *max_output = &vop->data->max_output;
++
++	if (max_output->width && max_output->height) {
++		/* only the size of the resulting rect matters */
++		if(drm_mode_validate_size(mode, max_output->width,
++					  max_output->height) != MODE_OK) {
++			return drm_mode_validate_size(mode, max_output->height,
++						      max_output->width);
++		}
++	}
++
++	return MODE_OK;
++}
++
+ /*
+  * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance.
+  * The CVT spec reuses that tolerance in its examples.
+@@ -1241,25 +1259,24 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
+ 	long rounded_rate;
+ 	long lowest, highest;
+ 
+-	if (!vop_crtc_is_tmds(crtc))
+-		return MODE_OK;
+-
+ 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+-		return MODE_NO_INTERLACE;
++			return MODE_NO_INTERLACE;
+ 
+-	rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999);
+-	if (rounded_rate < 0)
+-		return MODE_NOCLOCK;
++	if (vop_crtc_is_tmds(crtc)) {
++		rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999);
++		if (rounded_rate < 0)
++			return MODE_NOCLOCK;
+ 
+-	lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE);
+-	if (rounded_rate < lowest)
+-		return MODE_CLOCK_LOW;
++		lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE);
++		if (rounded_rate < lowest)
++			return MODE_CLOCK_LOW;
+ 
+-	highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE);
+-	if (rounded_rate > highest)
+-		return MODE_CLOCK_HIGH;
++		highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE);
++		if (rounded_rate > highest)
++			return MODE_CLOCK_HIGH;
++	}
+ 
+-	return MODE_OK;
++	return vop_crtc_size_valid(crtc, mode);
+ }
+ 
+ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
+@@ -1269,6 +1286,9 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
+ 	struct vop *vop = to_vop(crtc);
+ 	unsigned long rate;
+ 
++	if (vop_crtc_size_valid(crtc, adjusted_mode) != MODE_OK)
++		return false;
++
+ 	/*
+ 	 * Clock craziness.
+ 	 *
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Yakir Yang <ykk@rock-chips.com>
+Date: Mon, 11 Jul 2016 19:05:39 +0800
+Subject: [PATCH] drm/rockchip: dw_hdmi: adjust cklvl & txlvl for RF/EMI
+
+Dut to the high HDMI signal voltage driver, Mickey have meet
+a serious RF/EMI problem, so we decided to reduce HDMI signal
+voltage to a proper value.
+
+The default params for phy is cklvl = 20 & txlvl = 13 (RF/EMI failed)
+  ck: lvl = 13, term=100, vlo = 2.71, vhi=3.14, vswing = 0.43
+  tx: lvl = 20, term=100, vlo = 2.81, vhi=3.16, vswing = 0.35
+
+1. We decided to reduce voltage value to lower, but VSwing still
+keep high, RF/EMI have been improved but still failed.
+   ck: lvl =  6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50
+   tx: lvl =  6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50
+
+2. We try to keep voltage value and vswing both lower, then RF/EMI
+test all passed  ;)
+   ck: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40
+   tx: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40
+When we back to run HDMI different test and single-end test, we see
+different test passed, but signle-end test failed. The oscilloscope
+show that simgle-end clock's VL value is 1.78v (which remind LowLimit
+should not lower then 2.6v).
+
+3. That's to say there are some different between PHY document and
+measure value. And according to experiment 2 results, we need to
+higher clock voltage and lower data voltage, then we can keep RF/EMI
+satisfied and single-end & differen test passed.
+  ck: lvl =  9, term=100, vlo = 2.65, vhi=3.12, vswing = 0.47
+  tx: lvl = 16, term=100, vlo = 2.75, vhi=3.15, vswing = 0.39
+
+Signed-off-by: Yakir Yang <ykk@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index c14f88893868..4411ca8fd7ed 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -193,7 +193,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
+ 	/*pixelclk   symbol   term   vlev*/
+ 	{ 74250000,  0x8009, 0x0004, 0x0272},
+-	{ 148500000, 0x802b, 0x0004, 0x028d},
++	{ 165000000, 0x802b, 0x0004, 0x0209},
+ 	{ 297000000, 0x8039, 0x0005, 0x028d},
+ 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
+ };
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Nickey Yang <nickey.yang@rock-chips.com>
+Date: Mon, 13 Feb 2017 15:40:29 +0800
+Subject: [PATCH] drm/rockchip: dw_hdmi: add phy_config for 594Mhz pixel clock
+
+Add phy_config for 594Mhz pixel clock used for 4K@60hz
+
+Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 4411ca8fd7ed..bec381cde0bc 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -195,6 +195,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
+ 	{ 74250000,  0x8009, 0x0004, 0x0272},
+ 	{ 165000000, 0x802b, 0x0004, 0x0209},
+ 	{ 297000000, 0x8039, 0x0005, 0x028d},
++	{ 594000000, 0x8039, 0x0000, 0x019d},
+ 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
+ };
+ 
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Douglas Anderson <dianders@chromium.org>
+Date: Mon, 11 Jul 2016 19:05:36 +0800
+Subject: [PATCH] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always
+
+Jitter was improved by lowering the MPLL bandwidth to account for high
+frequency noise in the rk3288 PLL.  In each case MPLL bandwidth was
+lowered only enough to get us a comfortable margin.  We believe that
+lowering the bandwidth like this is safe given sufficient testing.
+
+Signed-off-by: Douglas Anderson <dianders@chromium.org>
+Signed-off-by: Yakir Yang <ykk@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++--------------
+ 1 file changed, 2 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index bec381cde0bc..72c1d65c7b75 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -172,20 +172,6 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ 	/*      pixelclk    bpp8    bpp10   bpp12 */
+ 	{
+-		40000000,  { 0x0018, 0x0018, 0x0018 },
+-	}, {
+-		65000000,  { 0x0028, 0x0028, 0x0028 },
+-	}, {
+-		66000000,  { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		74250000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		83500000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		146250000, { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		148500000, { 0x0000, 0x0038, 0x0038 },
+-	}, {
+ 		600000000, { 0x0000, 0x0000, 0x0000 },
+ 	},  {
+ 		~0UL,      { 0x0000, 0x0000, 0x0000},
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Douglas Anderson <dianders@chromium.org>
+Date: Mon, 11 Jul 2016 19:05:42 +0800
+Subject: [PATCH] drm/rockchip: dw_hdmi: Use auto-generated tables
+
+The previous tables for mpll_cfg and curr_ctrl were created using the
+20-pages of example settings provided by the PHY vendor.  Those
+example settings weren't particularly dense, so there were places
+where we were guessing what the settings would be for 10-bit and
+12-bit (not that we use those anyway).  It was also always a lot of
+extra work every time we wanted to add a new clock rate since we had
+to cross-reference several tables.
+
+In <http://crosreview.com/285855> I've gone through the work to figure
+out how to generate this table automatically.  Let's now use the
+automatically generated table and then we'll never need to look at it
+again.
+
+We only support 8-bit mode right now and only support a small number
+of clock rates and and I've verified that the only 8-bit rate that was
+affected was 148.5.  That mode appears to have been wrong in the old
+table.
+
+Signed-off-by: Douglas Anderson <dianders@chromium.org>
+Signed-off-by: Yakir Yang <ykk@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 130 +++++++++++---------
+ 1 file changed, 69 insertions(+), 61 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 72c1d65c7b75..0370bb247fcb 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -95,86 +95,88 @@
+ 
+ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ 	{
+-		27000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
+-		},
+-	}, {
+-		36000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
+-		},
+-	}, {
+-		40000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
+-		},
+-	}, {
+-		54000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
+-		},
+-	}, {
+-		65000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
+-		},
+-	}, {
+-		66000000, {
+-			{ 0x013e, 0x0003},
+-			{ 0x217e, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		74250000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		83500000, {
+-			{ 0x0072, 0x0001},
+-		},
+-	}, {
+-		108000000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		106500000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		146250000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		148500000, {
+-			{ 0x0051, 0x0003},
+-			{ 0x214c, 0x0003},
+-			{ 0x4064, 0x0003}
++		30666000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40f3, 0x0000 },
++		},
++	},  {
++		36800000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40a2, 0x0001 },
++		},
++	},  {
++		46000000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
++		},
++	},  {
++		61333000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
++		},
++	},  {
++		73600000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x4061, 0x0002 },
++		},
++	},  {
++		92000000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
++		},
++	},  {
++		122666000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
++		},
++	},  {
++		147200000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4064, 0x0003 },
++		},
++	},  {
++		184000000, {
++			{ 0x0051, 0x0002 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
+ 		},
+-	}, {
++	},  {
++		226666000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
++		},
++	},  {
++		272000000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x5a64, 0x0003 },
++		},
++	},  {
+ 		340000000, {
+ 			{ 0x0040, 0x0003 },
+ 			{ 0x3b4c, 0x0003 },
+ 			{ 0x5a64, 0x0003 },
+ 		},
+-	}, {
++	},  {
++		600000000, {
++			{ 0x1a40, 0x0003 },
++			{ 0x3b4c, 0x0003 },
++			{ 0x5a64, 0x0003 },
++		},
++	},  {
+ 		~0UL, {
+-			{ 0x00a0, 0x000a },
+-			{ 0x2001, 0x000f },
+-			{ 0x4002, 0x000f },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
+ 		},
+ 	}
+ };
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 8 Jan 2020 21:07:49 +0000
+Subject: [PATCH] drm/rockchip: dw-hdmi: allow high tmds bit rates
+
+Prepare support for High TMDS Bit Rates used by HDMI2.0 display modes.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 55c0b8dddad5..15ecb257b902 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -327,6 +327,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
+ {
+ 	struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
+ 
++	dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display);
++
+ 	return phy_power_on(hdmi->phy);
+ }
+ 
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 8 Jan 2020 21:07:52 +0000
+Subject: [PATCH] drm/rockchip: dw-hdmi: remove unused plat_data on
+ rk3228/rk3328
+
+mpll_cfg/cur_ctr/phy_config is not used when phy_force_vendor is true,
+lets remove them.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 15ecb257b902..38dded2baaf7 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -417,9 +417,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = {
+ 
+ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
+ 	.mode_valid = dw_hdmi_rockchip_mode_valid,
+-	.mpll_cfg = rockchip_mpll_cfg,
+-	.cur_ctr = rockchip_cur_ctr,
+-	.phy_config = rockchip_phy_config,
+ 	.phy_data = &rk3228_chip_data,
+ 	.phy_ops = &rk3228_hdmi_phy_ops,
+ 	.phy_name = "inno_dw_hdmi_phy2",
+@@ -454,9 +451,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = {
+ 
+ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
+ 	.mode_valid = dw_hdmi_rockchip_mode_valid,
+-	.mpll_cfg = rockchip_mpll_cfg,
+-	.cur_ctr = rockchip_cur_ctr,
+-	.phy_config = rockchip_phy_config,
+ 	.phy_data = &rk3328_chip_data,
+ 	.phy_ops = &rk3328_hdmi_phy_ops,
+ 	.phy_name = "inno_dw_hdmi_phy2",
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 10 Oct 2020 10:16:32 +0000
+Subject: [PATCH] drm/rockchip: dw-hdmi: encoder error handling
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 38dded2baaf7..9e460b7e14a4 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -558,7 +558,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 	if (IS_ERR(hdmi->phy)) {
+ 		ret = PTR_ERR(hdmi->phy);
+ 		if (ret != -EPROBE_DEFER)
+-			DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n");
++			DRM_DEV_ERROR(hdmi->dev, "Failed to get phy: %d\n", ret);
+ 		return ret;
+ 	}
+ 
+@@ -590,7 +590,12 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 	}
+ 
+ 	drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
+-	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
++
++	ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
++	if (ret) {
++		DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret);
++		goto err_disable_clk;
++	}
+ 
+ 	platform_set_drvdata(pdev, hdmi);
+ 
+@@ -609,6 +614,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 
+ err_bind:
+ 	drm_encoder_cleanup(encoder);
++err_disable_clk:
+ 	clk_disable_unprepare(hdmi->ref_clk);
+ err_clk:
+ 	regulator_disable(hdmi->avdd_1v8);
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 8 Jan 2020 21:07:50 +0000
+Subject: [PATCH] clk: rockchip: set parent rate for DCLK_VOP clock on rk3228
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/clk/rockchip/clk-rk3228.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index a24a35553e13..7343d2d7676b 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 			RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
+ 	DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
+ 			RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
+-	MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
++	MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ 			RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
+ 
+ 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 10 Oct 2020 14:32:21 +0000
+Subject: [PATCH] drm/rockchip: vop: split rk3288 vop
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 21 ++++++++++++++++++---
+ 1 file changed, 18 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index 9b25b8ffd0ce..a2b281e290e0 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -740,7 +740,7 @@ static const struct vop_intr rk3288_vop_intr = {
+ 	.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
+ };
+ 
+-static const struct vop_data rk3288_vop = {
++static const struct vop_data rk3288_vop_big = {
+ 	.version = VOP_VERSION(3, 1),
+ 	.feature = VOP_FEATURE_OUTPUT_RGB10,
+ 	.max_output = { 3840, 2160 },
+@@ -753,6 +753,19 @@ static const struct vop_data rk3288_vop = {
+ 	.lut_size = 1024,
+ };
+ 
++static const struct vop_data rk3288_vop_lit = {
++	.version = VOP_VERSION(3, 1),
++	.feature = VOP_FEATURE_OUTPUT_RGB10,
++	.max_output = { 2560, 1600 },
++	.intr = &rk3288_vop_intr,
++	.common = &rk3288_common,
++	.modeset = &rk3288_modeset,
++	.output = &rk3288_output,
++	.win = rk3288_vop_win_data,
++	.win_size = ARRAY_SIZE(rk3288_vop_win_data),
++	.lut_size = 1024,
++};
++
+ static const int rk3368_vop_intrs[] = {
+ 	FS_INTR,
+ 	0, 0,
+@@ -1142,8 +1155,10 @@ static const struct of_device_id vop_driver_dt_match[] = {
+ 	  .data = &rk3066_vop },
+ 	{ .compatible = "rockchip,rk3188-vop",
+ 	  .data = &rk3188_vop },
+-	{ .compatible = "rockchip,rk3288-vop",
+-	  .data = &rk3288_vop },
++	{ .compatible = "rockchip,rk3288-vop-big",
++	  .data = &rk3288_vop_big },
++	{ .compatible = "rockchip,rk3288-vop-lit",
++	  .data = &rk3288_vop_lit },
+ 	{ .compatible = "rockchip,rk3368-vop",
+ 	  .data = &rk3368_vop },
+ 	{ .compatible = "rockchip,rk3366-vop",
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 10 Oct 2020 14:33:30 +0000
+Subject: [PATCH] ARM: dts: rockchip: split rk3288 vop
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ arch/arm/boot/dts/rockchip/rk3288.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index 487b0e03d4b4..c60eacab8a79 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -1017,7 +1017,7 @@ rga: rga@ff920000 {
+ 	};
+ 
+ 	vopb: vop@ff930000 {
+-		compatible = "rockchip,rk3288-vop";
++		compatible = "rockchip,rk3288-vop-big";
+ 		reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
+ 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
+@@ -1066,7 +1066,7 @@ vopb_mmu: iommu@ff930300 {
+ 	};
+ 
+ 	vopl: vop@ff940000 {
+-		compatible = "rockchip,rk3288-vop";
++		compatible = "rockchip,rk3288-vop-lit";
+ 		reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
+ 		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 20 Jul 2020 18:00:44 +0000
+Subject: [PATCH] drm/bridge: dw-hdmi: add mtmdsclock parameter to phy
+ configure ops
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 10 ++++++----
+ drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c    |  3 ++-
+ include/drm/bridge/dw_hdmi.h              |  3 ++-
+ 3 files changed, 10 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 40d8ca37f5bc..22af42a08980 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -138,7 +138,8 @@ struct dw_hdmi_phy_data {
+ 	bool has_svsret;
+ 	int (*configure)(struct dw_hdmi *hdmi,
+ 			 const struct dw_hdmi_plat_data *pdata,
+-			 unsigned long mpixelclock);
++			 unsigned long mpixelclock,
++			 unsigned long mtmdsclock);
+ };
+ 
+ struct dw_hdmi {
+@@ -1585,7 +1586,8 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
+  */
+ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
+ 		const struct dw_hdmi_plat_data *pdata,
+-		unsigned long mpixelclock)
++		unsigned long mpixelclock,
++		unsigned long mtmdsclock)
+ {
+ 	const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
+ 	const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
+@@ -1660,9 +1662,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi,
+ 
+ 	/* Write to the PHY as configured by the platform */
+ 	if (pdata->configure_phy)
+-		ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
++		ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock, mtmdsclock);
+ 	else
+-		ret = phy->configure(hdmi, pdata, mpixelclock);
++		ret = phy->configure(hdmi, pdata, mpixelclock, mtmdsclock);
+ 	if (ret) {
+ 		dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
+ 			mpixelclock);
+diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c
+index 18ed14911b98..9c75095a25c5 100644
+--- a/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c
++++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c
+@@ -53,7 +53,8 @@ rcar_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
+ }
+ 
+ static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data,
+-				   unsigned long mpixelclock)
++				   unsigned long mpixelclock,
++				   unsigned long mtmdsclock)
+ {
+ 	const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params;
+ 
+diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
+index f668e75fbabe..48fb72f9614f 100644
+--- a/include/drm/bridge/dw_hdmi.h
++++ b/include/drm/bridge/dw_hdmi.h
+@@ -159,7 +159,8 @@ struct dw_hdmi_plat_data {
+ 	const struct dw_hdmi_curr_ctrl *cur_ctr;
+ 	const struct dw_hdmi_phy_config *phy_config;
+ 	int (*configure_phy)(struct dw_hdmi *hdmi, void *data,
+-			     unsigned long mpixelclock);
++			     unsigned long mpixelclock,
++			     unsigned long mtmdsclock);
+ 
+ 	unsigned int disable_cec : 1;
+ };
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 20 Jul 2020 21:34:48 +0000
+Subject: [PATCH] drm/bridge: dw-hdmi: support configuring phy for deep color
+
+Q: Should we rename dw_hdmi_curr_ctrl and dw_hdmi_phy_config mpixelclock to mtmdsclock ?
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 ++++++++++++-----
+ 1 file changed, 12 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 22af42a08980..7fd45a7006b1 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -1592,6 +1592,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
+ 	const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
+ 	const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
+ 	const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
++	int depth;
+ 
+ 	/* TOFIX Will need 420 specific PHY configuration tables */
+ 
+@@ -1601,11 +1602,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
+ 			break;
+ 
+ 	for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
+-		if (mpixelclock <= curr_ctrl->mpixelclock)
++		if (mtmdsclock <= curr_ctrl->mpixelclock)
+ 			break;
+ 
+ 	for (; phy_config->mpixelclock != ~0UL; phy_config++)
+-		if (mpixelclock <= phy_config->mpixelclock)
++		if (mtmdsclock <= phy_config->mpixelclock)
+ 			break;
+ 
+ 	if (mpll_config->mpixelclock == ~0UL ||
+@@ -1613,11 +1614,17 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
+ 	    phy_config->mpixelclock == ~0UL)
+ 		return -EINVAL;
+ 
+-	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
++	depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
++	if (depth > 8 && mpixelclock != mtmdsclock)
++		depth = fls(depth - 8) - 1;
++	else
++		depth = 0;
++
++	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce,
+ 			      HDMI_3D_TX_PHY_CPCE_CTRL);
+-	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
++	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp,
+ 			      HDMI_3D_TX_PHY_GMPCTRL);
+-	dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
++	dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth],
+ 			      HDMI_3D_TX_PHY_CURRCTRL);
+ 
+ 	dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 20 Jul 2020 22:25:15 +0000
+Subject: [PATCH] drm/bridge: dw-hdmi: add mpll_cfg_420 for ycbcr420 mode
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 +++-
+ include/drm/bridge/dw_hdmi.h              | 1 +
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 7fd45a7006b1..a2d101ebf7a7 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -1594,7 +1594,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
+ 	const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
+ 	int depth;
+ 
+-	/* TOFIX Will need 420 specific PHY configuration tables */
++	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) &&
++	    pdata->mpll_cfg_420)
++		mpll_config = pdata->mpll_cfg_420;
+ 
+ 	/* PLL/MPLL Cfg - always match on final entry */
+ 	for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
+diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
+index 48fb72f9614f..02554d324b4b 100644
+--- a/include/drm/bridge/dw_hdmi.h
++++ b/include/drm/bridge/dw_hdmi.h
+@@ -156,6 +156,7 @@ struct dw_hdmi_plat_data {
+ 
+ 	/* Synopsys PHY support */
+ 	const struct dw_hdmi_mpll_config *mpll_cfg;
++	const struct dw_hdmi_mpll_config *mpll_cfg_420;
+ 	const struct dw_hdmi_curr_ctrl *cur_ctr;
+ 	const struct dw_hdmi_phy_config *phy_config;
+ 	int (*configure_phy)(struct dw_hdmi *hdmi, void *data,
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 20 Jul 2020 22:26:19 +0000
+Subject: [PATCH] drm/rockchip: dw-hdmi: add YCbCr420 mpll cfg for rk3399
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index d42ac9fa3246..a37565649c13 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -177,6 +177,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ 	}
+ };
+ 
++static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = {
++	{
++		30666000, {
++			{ 0x00b7, 0x0000 },
++			{ 0x2157, 0x0000 },
++			{ 0x40f7, 0x0000 },
++		},
++	},  {
++		92000000, {
++			{ 0x00b7, 0x0000 },
++			{ 0x2143, 0x0001 },
++			{ 0x40a3, 0x0001 },
++		},
++	},  {
++		184000000, {
++			{ 0x0073, 0x0001 },
++			{ 0x2146, 0x0002 },
++			{ 0x4062, 0x0002 },
++		},
++	},  {
++		340000000, {
++			{ 0x0052, 0x0003 },
++			{ 0x214d, 0x0003 },
++			{ 0x4065, 0x0003 },
++		},
++	},  {
++		600000000, {
++			{ 0x0041, 0x0003 },
++			{ 0x3b4d, 0x0003 },
++			{ 0x5a65, 0x0003 },
++		},
++	},  {
++		~0UL, {
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++		},
++	}
++};
++
+ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ 	/*      pixelclk    bpp8    bpp10   bpp12 */
+ 	{
+@@ -474,6 +514,7 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = {
+ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
+ 	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg   = rockchip_mpll_cfg,
++	.mpll_cfg_420 = rockchip_mpll_cfg_420,
+ 	.cur_ctr    = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+ 	.phy_data = &rk3399_chip_data,
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Shunqing Chen <csq@rock-chips.com>
+Date: Wed, 15 Jul 2020 15:19:11 +0800
+Subject: [PATCH] drm/rockchip: dw-hdmi: add YCbCr420 mpll cfg for rk3288w
+
+Signed-off-by: Shunqing Chen <csq@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index a37565649c13..66fee351f4a7 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -217,6 +217,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = {
+ 	}
+ };
+ 
++static const struct dw_hdmi_mpll_config rockchip_rk3288w_mpll_cfg_420[] = {
++	{
++		30666000, {
++			{ 0x00b7, 0x0000 },
++			{ 0x2157, 0x0000 },
++			{ 0x40f7, 0x0000 },
++		},
++	},  {
++		92000000, {
++			{ 0x00b7, 0x0000 },
++			{ 0x2143, 0x0001 },
++			{ 0x40a3, 0x0001 },
++		},
++	},  {
++		184000000, {
++			{ 0x0073, 0x0001 },
++			{ 0x2146, 0x0002 },
++			{ 0x4062, 0x0002 },
++		},
++	},  {
++		340000000, {
++			{ 0x0052, 0x0003 },
++			{ 0x214d, 0x0003 },
++			{ 0x4065, 0x0003 },
++		},
++	},  {
++		600000000, {
++			{ 0x0040, 0x0003 },
++			{ 0x3b4c, 0x0003 },
++			{ 0x5a65, 0x0003 },
++		},
++	},  {
++		~0UL, {
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++		},
++	}
++};
++
+ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ 	/*      pixelclk    bpp8    bpp10   bpp12 */
+ 	{
+@@ -479,6 +519,7 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
+ static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
+ 	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg   = rockchip_mpll_cfg,
++	.mpll_cfg_420 = rockchip_rk3288w_mpll_cfg_420,
+ 	.cur_ctr    = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+ 	.phy_data = &rk3288_chip_data,
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 20 Dec 2019 08:12:42 +0000
+Subject: [PATCH] drm/rockchip: dw-hdmi: add bridge and switch to
+ drm_bridge_funcs
+
+Switch the dw-hdmi driver to drm_bridge_funcs by implementing
+a new local bridge, connecting it to the dw-hdmi bridge.
+
+Also enable bridge format negotiation by implementing
+atomic_get_input_bus_fmts and support for 8-bit RGB 4:4:4.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 118 ++++++++++++++------
+ 1 file changed, 81 insertions(+), 37 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 66fee351f4a7..d6d8f3335813 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -5,6 +5,7 @@
+ 
+ #include <linux/clk.h>
+ #include <linux/mfd/syscon.h>
++#include <linux/media-bus-format.h>
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/phy/phy.h>
+@@ -72,6 +73,7 @@ struct rockchip_hdmi_chip_data {
+ struct rockchip_hdmi {
+ 	struct device *dev;
+ 	struct regmap *regmap;
++	struct drm_bridge bridge;
+ 	struct rockchip_encoder encoder;
+ 	const struct rockchip_hdmi_chip_data *chip_data;
+ 	struct clk *ref_clk;
+@@ -82,11 +84,9 @@ struct rockchip_hdmi {
+ 	struct phy *phy;
+ };
+ 
+-static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
++static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge)
+ {
+-	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+-
+-	return container_of(rkencoder, struct rockchip_hdmi, encoder);
++	return container_of(bridge, struct rockchip_hdmi, bridge);
+ }
+ 
+ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+@@ -335,31 +335,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
+ 
+ 	return MODE_OK;
+ }
+-
+-static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
++static void
++dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge,
++				 const struct drm_display_mode *mode,
++				 const struct drm_display_mode *adjusted_mode)
+ {
+-}
++	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
+ 
+-static bool
+-dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
+-				    const struct drm_display_mode *mode,
+-				    struct drm_display_mode *adj_mode)
+-{
+-	return true;
++	clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000);
+ }
+ 
+-static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
+-					      struct drm_display_mode *mode,
+-					      struct drm_display_mode *adj_mode)
++static void dw_hdmi_rockchip_bridge_enable(struct drm_bridge *bridge)
+ {
+-	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
++	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
++	struct drm_encoder *encoder = bridge->encoder;
+ 
+-	clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
+-}
+-
+-static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
+-{
+-	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
+ 	u32 val;
+ 	int ret;
+ 
+@@ -387,10 +377,21 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
+ 		      ret ? "LIT" : "BIG");
+ }
+ 
++static bool is_rgb(u32 format)
++{
++	switch (format) {
++	case MEDIA_BUS_FMT_RGB888_1X24:
++		return true;
++	default:
++		return false;
++	}
++}
++
+ static int
+-dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
+-				      struct drm_crtc_state *crtc_state,
+-				      struct drm_connector_state *conn_state)
++dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge,
++				     struct drm_bridge_state *bridge_state,
++				     struct drm_crtc_state *crtc_state,
++				     struct drm_connector_state *conn_state)
+ {
+ 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ 
+@@ -400,12 +401,38 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
+ 	return 0;
+ }
+ 
+-static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
+-	.mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
+-	.mode_set   = dw_hdmi_rockchip_encoder_mode_set,
+-	.enable     = dw_hdmi_rockchip_encoder_enable,
+-	.disable    = dw_hdmi_rockchip_encoder_disable,
+-	.atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
++static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
++					struct drm_bridge_state *bridge_state,
++					struct drm_crtc_state *crtc_state,
++					struct drm_connector_state *conn_state,
++					u32 output_fmt,
++					unsigned int *num_input_fmts)
++{
++	u32 *input_fmt;
++
++	*num_input_fmts = 0;
++
++	if (!is_rgb(output_fmt))
++		return NULL;
++
++	input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL);
++	if (!input_fmt)
++		return NULL;
++
++	*num_input_fmts = 1;
++	*input_fmt = output_fmt;
++
++	return input_fmt;
++}
++
++static const struct drm_bridge_funcs dw_hdmi_rockchip_bridge_funcs = {
++	.mode_set = dw_hdmi_rockchip_bridge_mode_set,
++	.enable = dw_hdmi_rockchip_bridge_enable,
++	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
++	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
++	.atomic_get_input_bus_fmts = dw_hdmi_rockchip_get_input_bus_fmts,
++	.atomic_check = dw_hdmi_rockchip_bridge_atomic_check,
++	.atomic_reset = drm_atomic_helper_bridge_reset,
+ };
+ 
+ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
+@@ -602,6 +629,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 	struct dw_hdmi_plat_data *plat_data;
+ 	const struct of_device_id *match;
+ 	struct drm_device *drm = data;
++	struct drm_bridge *next_bridge;
+ 	struct drm_encoder *encoder;
+ 	struct rockchip_hdmi *hdmi;
+ 	int ret;
+@@ -679,20 +707,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 					   RK3568_HDMI_SCLIN_MSK));
+ 	}
+ 
+-	drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
+-
+ 	ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
+ 	if (ret) {
+ 		DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret);
+ 		goto err_disable_clk;
+ 	}
+ 
++	hdmi->bridge.funcs = &dw_hdmi_rockchip_bridge_funcs;
++	drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
++
+ 	platform_set_drvdata(pdev, hdmi);
+ 
+-	hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
++	hdmi->hdmi = dw_hdmi_probe(pdev, plat_data);
+ 
+ 	/*
+-	 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
++	 * If dw_hdmi_probe() fails we'll never call dw_hdmi_unbind(),
+ 	 * which would have called the encoder cleanup.  Do it manually.
+ 	 */
+ 	if (IS_ERR(hdmi->hdmi)) {
+@@ -700,8 +729,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 		goto err_bind;
+ 	}
+ 
++	next_bridge = of_drm_find_bridge(pdev->dev.of_node);
++	if (!next_bridge) {
++		ret = -EPROBE_DEFER;
++		goto err_dw_hdmi_remove;
++	}
++
++	ret = drm_bridge_attach(encoder, next_bridge, &hdmi->bridge, 0);
++	if (ret) {
++		if (ret != -EPROBE_DEFER)
++			DRM_DEV_ERROR(hdmi->dev, "Failed to attach dw-hdmi bridge: %d\n", ret);
++		goto err_dw_hdmi_remove;
++	}
++
+ 	return 0;
+ 
++err_dw_hdmi_remove:
++	dw_hdmi_remove(hdmi->hdmi);
+ err_bind:
+ 	drm_encoder_cleanup(encoder);
+ err_disable_clk:
+@@ -719,7 +763,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
+ {
+ 	struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
+ 
+-	dw_hdmi_unbind(hdmi->hdmi);
++	dw_hdmi_remove(hdmi->hdmi);
+ 	drm_encoder_cleanup(&hdmi->encoder.encoder);
+ 	clk_disable_unprepare(hdmi->ref_clk);
+ 
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 9 Oct 2020 15:29:27 +0000
+Subject: [PATCH] drm/rockchip: vop: add immutable zpos property
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_fb.c  | 2 ++
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++++--
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
+index 092bf863110b..e2ee0d6a8d55 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
+@@ -133,6 +133,8 @@ void rockchip_drm_mode_config_init(struct drm_device *dev)
+ 	dev->mode_config.max_width = 4096;
+ 	dev->mode_config.max_height = 4096;
+ 
++	dev->mode_config.normalize_zpos = true;
++
+ 	dev->mode_config.funcs = &rockchip_drm_mode_config_funcs;
+ 	dev->mode_config.helper_private = &rockchip_mode_config_helpers;
+ 
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index 30e252ba7184..897f7980ee5d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1917,7 +1917,7 @@ static irqreturn_t vop_isr(int irq, void *data)
+ 	return ret;
+ }
+ 
+-static void vop_plane_add_properties(struct drm_plane *plane,
++static void vop_plane_add_properties(struct drm_plane *plane, int zpos,
+ 				     const struct vop_win_data *win_data)
+ {
+ 	unsigned int flags = 0;
+@@ -1927,6 +1927,8 @@ static void vop_plane_add_properties(struct drm_plane *plane,
+ 	if (flags)
+ 		drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
+ 						   DRM_MODE_ROTATE_0 | flags);
++
++	drm_plane_create_zpos_immutable_property(plane, zpos);
+ }
+ 
+ static int vop_create_crtc(struct vop *vop)
+@@ -1967,7 +1969,7 @@ static int vop_create_crtc(struct vop *vop)
+ 
+ 		plane = &vop_win->base;
+ 		drm_plane_helper_add(plane, &plane_helper_funcs);
+-		vop_plane_add_properties(plane, win_data);
++		vop_plane_add_properties(plane, i, win_data);
+ 		if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+ 			primary = plane;
+ 		else if (plane->type == DRM_PLANE_TYPE_CURSOR)
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 10 Oct 2020 09:20:44 +0000
+Subject: [PATCH] drm/rockchip: vop: add plane color properties
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 32 +++++++++++++++++++--
+ 1 file changed, 30 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index 897f7980ee5d..eadf1b0f1704 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1917,8 +1917,23 @@ static irqreturn_t vop_isr(int irq, void *data)
+ 	return ret;
+ }
+ 
++static bool plane_supports_yuv_format(const struct drm_plane *plane)
++{
++	const struct drm_format_info *info;
++	int i;
++
++	for (i = 0; i < plane->format_count; i++) {
++		info = drm_format_info(plane->format_types[i]);
++		if (info->is_yuv)
++			return true;
++	}
++
++	return false;
++}
++
+ static void vop_plane_add_properties(struct drm_plane *plane, int zpos,
+-				     const struct vop_win_data *win_data)
++				     const struct vop_win_data *win_data,
++				     const struct vop_data *vop_data)
+ {
+ 	unsigned int flags = 0;
+ 
+@@ -1929,6 +1944,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos,
+ 						   DRM_MODE_ROTATE_0 | flags);
+ 
+ 	drm_plane_create_zpos_immutable_property(plane, zpos);
++
++	if (!plane_supports_yuv_format(plane))
++		return;
++
++	flags = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
++	if (vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)
++		flags |= BIT(DRM_COLOR_YCBCR_BT2020);
++
++	drm_plane_create_color_properties(plane, flags,
++					  BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
++					  BIT(DRM_COLOR_YCBCR_FULL_RANGE),
++					  DRM_COLOR_YCBCR_BT601,
++					  DRM_COLOR_YCBCR_LIMITED_RANGE);
+ }
+ 
+ static int vop_create_crtc(struct vop *vop)
+@@ -1969,7 +1997,7 @@ static int vop_create_crtc(struct vop *vop)
+ 
+ 		plane = &vop_win->base;
+ 		drm_plane_helper_add(plane, &plane_helper_funcs);
+-		vop_plane_add_properties(plane, i, win_data);
++		vop_plane_add_properties(plane, i, win_data, vop_data);
+ 		if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+ 			primary = plane;
+ 		else if (plane->type == DRM_PLANE_TYPE_CURSOR)
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Nickey Yang <nickey.yang@rock-chips.com>
+Date: Mon, 17 Jul 2017 16:35:34 +0800
+Subject: [PATCH] HACK: clk: rockchip: rk3288: dedicate npll for vopb and hdmi
+ use
+
+MINIARM: set npll be used for hdmi only
+
+Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm/boot/dts/rockchip/rk3288.dtsi     | 2 ++
+ drivers/clk/rockchip/clk-rk3288.c | 9 +++++----
+ 2 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index c60eacab8a79..d1ae42757242 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -1026,6 +1026,8 @@ vopb: vop@ff930000 {
+ 		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+ 		reset-names = "axi", "ahb", "dclk";
+ 		iommus = <&vopb_mmu>;
++		assigned-clocks = <&cru DCLK_VOP0>;
++		assigned-clock-parents = <&cru PLL_NPLL>;
+ 		status = "disabled";
+ 
+ 		vopb_out: port {
+diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
+index baa5aebd3277..5cfcbaaa154e 100644
+--- a/drivers/clk/rockchip/clk-rk3288.c
++++ b/drivers/clk/rockchip/clk-rk3288.c
+@@ -195,8 +195,9 @@ PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
+ PNAME(mux_aclk_cpu_src_p)	= { "cpll_aclk_cpu", "gpll_aclk_cpu" };
+ 
+ PNAME(mux_pll_src_cpll_gpll_p)		= { "cpll", "gpll" };
+-PNAME(mux_pll_src_npll_cpll_gpll_p)	= { "npll", "cpll", "gpll" };
+-PNAME(mux_pll_src_cpll_gpll_npll_p)	= { "cpll", "gpll", "npll" };
++PNAME(mux_pll_src_npll_cpll_gpll_p)	= { "prevent:npll", "cpll", "gpll" };
++PNAME(mux_pll_src_cpll_gpll_npll_p)	= { "cpll", "gpll", "prevent:npll" };
++PNAME(vop0_mux_pll_src_cpll_gpll_npll_p) = { "prevent:cpll", "prevent:gpll", "npll" };
+ PNAME(mux_pll_src_cpll_gpll_usb480m_p)	= { "cpll", "gpll", "unstable:usbphy480m_src" };
+ PNAME(mux_pll_src_cpll_gll_usb_npll_p)	= { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
+ 
+@@ -232,7 +233,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
+ 	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
+ 		     RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
+ 	[npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),
+-		     RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
++		     RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
+ };
+ 
+ static struct clk_div_table div_hclk_cpu_t[] = {
+@@ -442,7 +443,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
+ 			RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ 			RK3288_CLKGATE_CON(3), 4, GFLAGS),
+ 
+-	COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
++	COMPOSITE(DCLK_VOP0, "dclk_vop0", vop0_mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+ 			RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
+ 			RK3288_CLKGATE_CON(3), 1, GFLAGS),
+ 	COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 4 Aug 2018 14:51:14 +0200
+Subject: [PATCH] HACK: clk: rockchip: rk3288: use npll table to to improve
+ HDMI compatibility
+
+Based on https://github.com/TinkerBoard/debian_kernel/commit/3d90870530b8a2901681f7b7fa598ee7381e49f3
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/clk/rockchip/clk-rk3288.c | 39 ++++++++++++++++++++++++++++++-
+ 1 file changed, 38 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
+index 5cfcbaaa154e..fa1c6e646bdf 100644
+--- a/drivers/clk/rockchip/clk-rk3288.c
++++ b/drivers/clk/rockchip/clk-rk3288.c
+@@ -121,6 +121,43 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
+ 	{ /* sentinel */ },
+ };
+ 
++static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
++	RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
++	RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
++	RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
++	RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
++	RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
++	RK3066_PLL_RATE(348500000, 8, 697, 6),
++	RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
++	RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
++	RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
++	RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
++	RK3066_PLL_RATE(241500000, 2, 161, 8),
++	RK3066_PLL_RATE(162000000, 1, 81, 12),
++	RK3066_PLL_RATE(154000000, 6, 539, 14),
++	RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
++	RK3066_PLL_RATE(148352000, 13, 1125, 14),
++	RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
++	RK3066_PLL_RATE(121750000, 6, 487, 16),
++	RK3066_PLL_RATE(119000000, 3, 238, 16),
++	RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
++	RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
++	RK3066_PLL_RATE(101000000, 3, 202, 16),
++	RK3066_PLL_RATE(88750000, 6, 355, 16),
++	RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
++	RK3066_PLL_RATE(83500000, 3, 167, 16),
++	RK3066_PLL_RATE(79500000, 1, 53, 16),
++	RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
++	RK3066_PLL_RATE(74176000, 26, 1125, 14),
++	RK3066_PLL_RATE(72000000, 1, 48, 16),
++	RK3066_PLL_RATE(71000000, 3, 142, 16),
++	RK3066_PLL_RATE(68250000, 2, 91, 16),
++	RK3066_PLL_RATE(65000000, 3, 130, 16),
++	RK3066_PLL_RATE(40000000, 3, 80, 16),
++	RK3066_PLL_RATE(33750000, 2, 45, 16),
++	{ /* sentinel */ },
++};
++
+ #define RK3288_DIV_ACLK_CORE_M0_MASK	0xf
+ #define RK3288_DIV_ACLK_CORE_M0_SHIFT	0
+ #define RK3288_DIV_ACLK_CORE_MP_MASK	0xf
+@@ -233,7 +270,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
+ 	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
+ 		     RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
+ 	[npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),
+-		     RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
++		     RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates),
+ };
+ 
+ static struct clk_div_table div_hclk_cpu_t[] = {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 25 May 2020 20:36:45 +0000
+Subject: [PATCH] HACK: clk: rockchip: rk3399: dedicate vpll for vopb and hdmi
+ use
+
+Rockchip PLLs are kown provide the least jitter for
+vco rates between 800 MHz and 2 GHz. I added the
+rates for VPLL which are used for VOPs dclk and there-
+fore HDMI phy in that manner and used the rates which
+require the lowest frac divs.
+Additionally I added some rates which are useful to
+provide additional VESA and non-VESA rates for HDMI
+output.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/clk/rockchip/clk-rk3399.c | 49 ++++++++++++++++++++++++++-----
+ 1 file changed, 42 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
+index 306910a3a0d3..436d2789611c 100644
+--- a/drivers/clk/rockchip/clk-rk3399.c
++++ b/drivers/clk/rockchip/clk-rk3399.c
+@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
+ 	{ /* sentinel */ },
+ };
+ 
++static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
++	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
++	RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0,  4194304),  /* vco = 1782000000  fout = 594000000 */
++	RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0,  2949838),  /* vco = 1780219777  fout = 593406592.36908 */
++	RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640),  /* vco = 1918500000  fout = 319750000 */
++	RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0,  4194304),  /* vco = 1782000000  fout = 297000000 */
++	RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0,  2949838),  /* vco = 1780219777  fout = 296703296.18454 */
++	RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0,  6291456),  /* vco = 1449000000  fout = 241500000 */
++	RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0,  8388608),  /* vco = 1620000000  fout = 162000000 */
++	RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0,  4194304),  /* vco = 1782000000  fout = 148500000*/
++	RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0,  2949838),  /* vco = 1780219777  fout = 148351648.09227 */
++	RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0,  6291456),  /* vco = 1641000000  fout = 136750000 */
++	RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0,  4194304),  /* vco = 1350000000  fout = 135000000 */
++	RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0,  8388608),  /* vco = 1428000000  fout = 119000000 */
++	RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1,        0),  /* vco = 1512000000  fout = 108000000 */
++	RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0,  2097152),  /* vco = 1491000000  fout = 106500000 */
++	RK3036_PLL_RATE(  88750000, 1, 55, 5, 3, 0,  7864320),  /* vco = 1331250000  fout = 88750000 */
++	RK3036_PLL_RATE(  85500000, 1, 57, 4, 4, 1,        0),  /* vco = 1368000000  fout = 85500000 */
++	RK3036_PLL_RATE(  78750000, 1, 59, 6, 3, 0,  1048576),  /* vco = 1417500000  fout = 78750000 */
++	RK3036_PLL_RATE(  74250000, 1, 74, 6, 4, 0,  4194304),  /* vco = 1782000000  fout = 74250000 */
++	RK3036_PLL_RATE(  74175824, 1, 74, 6, 4, 0,  2949838),  /* vco = 1780219777  fout = 74175824.046135 */
++	RK3036_PLL_RATE(  71000000, 1, 71, 6, 4, 1,        0),  /* vco = 1704000000  fout = 71000000 */
++	RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 0,        0),  /* vco = 1560000000  fout = 65000000 */
++	RK3036_PLL_RATE(  59340659, 1, 59, 6, 4, 0,  5715310),  /* vco = 1424175816  fout = 59340659.022331 */
++	RK3036_PLL_RATE(  54000000, 1, 63, 7, 4, 1,        0),  /* vco = 1512000000  fout = 54000000 */
++	RK3036_PLL_RATE(  49500000, 1, 72, 5, 7, 0,  3145728),  /* vco = 1732500000  fout = 49500000 */
++	RK3036_PLL_RATE(  40000000, 1, 70, 7, 6, 1,        0),  /* vco = 1680000000  fout = 40000000 */
++	RK3036_PLL_RATE(  31500000, 1, 55, 7, 6, 0,  2097152),  /* vco = 1323000000  fout = 31500000 */
++	RK3036_PLL_RATE(  27000000, 1, 55, 7, 7, 0,  2097152),  /* vco = 1323000000  fout = 27000000 */
++	RK3036_PLL_RATE(  26973026, 1, 55, 7, 7, 0,  1173214),  /* vco = 1321678296  fout = 26973026.450799 */
++	{ /* sentinel */ },
++};
++
+ /* CRU parents */
+ PNAME(mux_pll_p)				= { "xin24m", "xin32k" };
+ 
+@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p)				= { "clk_ddrc_lpll_src",
+ PNAME(mux_aclk_cci_p)				= { "cpll_aclk_cci_src",
+ 						    "gpll_aclk_cci_src",
+ 						    "npll_aclk_cci_src",
+-						    "vpll_aclk_cci_src" };
++						    "prevent:vpll" };
+ PNAME(mux_cci_trace_p)				= { "cpll_cci_trace",
+ 						    "gpll_cci_trace" };
+ PNAME(mux_cs_p)					= { "cpll_cs", "gpll_cs",
+@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)	= { "cpll", "gpll", "npll",
+ PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
+ 						    "ppll", "upll", "xin24m" };
+ 
+-PNAME(mux_pll_src_vpll_cpll_gpll_p)		= { "vpll", "cpll", "gpll" };
+-PNAME(mux_pll_src_vpll_cpll_gpll_npll_p)	= { "vpll", "cpll", "gpll",
++PNAME(mux_pll_src_vpll_cpll_gpll_p)		= { "prevent:vpll", "cpll", "gpll" };
++PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p)	= { "vpll", "prevent:cpll", "prevent:gpll" };
++
++PNAME(mux_pll_src_vpll_cpll_gpll_npll_p)	= { "prevent:vpll", "cpll", "gpll",
+ 						    "npll" };
+-PNAME(mux_pll_src_vpll_cpll_gpll_24m_p)		= { "vpll", "cpll", "gpll",
++PNAME(mux_pll_src_vpll_cpll_gpll_24m_p)		= { "prevent:vpll", "cpll", "gpll",
+ 						    "xin24m" };
+ 
+ PNAME(mux_dclk_vop0_p)			= { "dclk_vop0_div",
+@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
+ 	[npll] = PLL(pll_rk3399, PLL_NPLL, "npll",  mux_pll_p, 0, RK3399_PLL_CON(40),
+ 		     RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
+ 	[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll",  mux_pll_p, 0, RK3399_PLL_CON(48),
+-		     RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
++		     RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates),
+ };
+ 
+ static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
+@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
+ 			RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
+ 
+ static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
+-	MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
++	MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ 			RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
+ 
+ static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
+@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
+ 			RK3399_CLKGATE_CON(28), 0, GFLAGS),
+ 
+-	COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
++	COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ 			RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ 			RK3399_CLKGATE_CON(10), 12, GFLAGS),
+ 
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 19 Jul 2020 16:35:11 +0000
+Subject: [PATCH] HACK: dts: rockchip: do not use vopl for hdmi
+
+---
+ arch/arm/boot/dts/rockchip/rk3288.dtsi            | 9 ---------
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 9 ---------
+ 2 files changed, 18 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index d1ae42757242..7b2cde230b87 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -1090,11 +1090,6 @@
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 
+-			vopl_out_hdmi: endpoint@0 {
+-				reg = <0>;
+-				remote-endpoint = <&hdmi_in_vopl>;
+-			};
+-
+ 			vopl_out_edp: endpoint@1 {
+ 				reg = <1>;
+ 				remote-endpoint = <&edp_in_vopl>;
+@@ -1257,10 +1262,6 @@
+ 					remote-endpoint = <&vopb_out_hdmi>;
+ 				};
+ 
+-				hdmi_in_vopl: endpoint@1 {
+-					reg = <1>;
+-					remote-endpoint = <&vopl_out_hdmi>;
+-				};
+ 			};
+ 
+ 			hdmi_out: port@1 {
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 92c2207e686c..980b12cb0a49 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -1728,11 +1728,6 @@ vopl_out_edp: endpoint@1 {
+ 				remote-endpoint = <&edp_in_vopl>;
+ 			};
+ 
+-			vopl_out_hdmi: endpoint@2 {
+-				reg = <2>;
+-				remote-endpoint = <&hdmi_in_vopl>;
+-			};
+-
+ 			vopl_out_mipi1: endpoint@3 {
+ 				reg = <3>;
+ 				remote-endpoint = <&mipi1_in_vopl>;
+@@ -1926,10 +1921,6 @@ hdmi_in_vopb: endpoint@0 {
+ 					reg = <0>;
+ 					remote-endpoint = <&vopb_out_hdmi>;
+ 				};
+-				hdmi_in_vopl: endpoint@1 {
+-					reg = <1>;
+-					remote-endpoint = <&vopl_out_hdmi>;
+-				};
+ 			};
+ 		};
+ 	};
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 20 Dec 2019 08:12:43 +0000
+Subject: [PATCH] WIP: drm/bridge: dw-hdmi: limit mode and bus format to
+ max_tmds_clock
+
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 120 ++++++++++++++--------
+ 1 file changed, 76 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index a2d101ebf7a7..7f6ffbc3e7b2 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -2003,6 +2003,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
+ 		  HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
+ }
+ 
++static unsigned int
++hdmi_get_tmdsclock(unsigned int bus_format, unsigned int pixelclock)
++{
++	int color_depth = hdmi_bus_fmt_color_depth(bus_format);
++	unsigned int tmdsclock = pixelclock;
++
++	if (!hdmi_bus_fmt_is_yuv422(bus_format) && color_depth > 8)
++		tmdsclock = (u64)pixelclock * color_depth / 8;
++
++	if (hdmi_bus_fmt_is_yuv420(bus_format))
++		tmdsclock /= 2;
++
++	return tmdsclock;
++}
++
+ static void hdmi_av_composer(struct dw_hdmi *hdmi,
+ 			     const struct drm_display_info *display,
+ 			     const struct drm_display_mode *mode)
+@@ -2014,29 +2029,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
+ 	unsigned int vdisplay, hdisplay;
+ 
+ 	vmode->mpixelclock = mode->clock * 1000;
++	vmode->mtmdsclock =
++		hdmi_get_tmdsclock(hdmi->hdmi_data.enc_out_bus_format,
++				   vmode->mpixelclock);
+ 
+ 	dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
+-
+-	vmode->mtmdsclock = vmode->mpixelclock;
+-
+-	if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
+-		switch (hdmi_bus_fmt_color_depth(
+-				hdmi->hdmi_data.enc_out_bus_format)) {
+-		case 16:
+-			vmode->mtmdsclock = vmode->mpixelclock * 2;
+-			break;
+-		case 12:
+-			vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
+-			break;
+-		case 10:
+-			vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
+-			break;
+-		}
+-	}
+-
+-	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
+-		vmode->mtmdsclock /= 2;
+-
+ 	dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
+ 
+ 	/* Set up HDMI_FC_INVIDCONF */
+@@ -2663,8 +2660,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
+  * - MEDIA_BUS_FMT_RGB888_1X24,
+  */
+ 
+-/* Can return a maximum of 11 possible output formats for a mode/connector */
+-#define MAX_OUTPUT_SEL_FORMATS	11
++/* Can return a maximum of 15 possible output formats for a mode/connector */
++#define MAX_OUTPUT_SEL_FORMATS	15
++
++static bool is_tmds_allowed(struct drm_display_info *info,
++			    struct drm_display_mode *mode,
++			    u32 bus_format)
++{
++	unsigned long tmdsclock = hdmi_get_tmdsclock(bus_format, mode->clock);
++	int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000;
++
++	if (max_tmds_clock >= tmdsclock)
++		return true;
++
++	return false;
++}
+ 
+ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ 					struct drm_bridge_state *bridge_state,
+@@ -2676,8 +2686,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ 	struct drm_display_info *info = &conn->display_info;
+ 	struct drm_display_mode *mode = &crtc_state->mode;
+ 	u8 max_bpc = conn_state->max_requested_bpc;
+-	bool is_hdmi2_sink = info->hdmi.scdc.supported ||
+-			     (info->color_formats & DRM_COLOR_FORMAT_YCBCR420);
+ 	u32 *output_fmts;
+ 	unsigned int i = 0;
+ 
+@@ -2701,25 +2709,28 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ 	 * If the current mode enforces 4:2:0, force the output but format
+ 	 * to 4:2:0 and do not add the YUV422/444/RGB formats
+ 	 */
+-	if (conn->ycbcr_420_allowed &&
+-	    (drm_mode_is_420_only(info, mode) ||
+-	     (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
++	if (conn->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
++	    (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) {
+ 
+ 		/* Order bus formats from 16bit to 8bit if supported */
+ 		if (max_bpc >= 16 && info->bpc == 16 &&
+-		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
++		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) &&
++		    is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY16_0_5X48))
+ 			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
+ 
+ 		if (max_bpc >= 12 && info->bpc >= 12 &&
+-		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
++		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) &&
++		    is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY12_0_5X36))
+ 			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
+ 
+ 		if (max_bpc >= 10 && info->bpc >= 10 &&
+-		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
++		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) &&
++		    is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY10_0_5X30))
+ 			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
+ 
+ 		/* Default 8bit fallback */
+-		output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
++		if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYYVYY8_0_5X24))
++			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
+ 
+ 		if (drm_mode_is_420_only(info, mode))
+ 			*num_output_fmts = i;
+@@ -2732,40 +2744,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ 	 */
+ 
+ 	/* Default 8bit RGB fallback */
+-	output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
++	if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24))
++		output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ 
+ 	if (max_bpc >= 16 && info->bpc == 16) {
+-		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
++		if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
++		    is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV16_1X48))
+ 			output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
+ 
+-		output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
++		if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB161616_1X48))
++			output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
+ 	}
+ 
+ 	if (max_bpc >= 12 && info->bpc >= 12) {
+-		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
++		if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) &&
++		    is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY12_1X24))
+ 			output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
+ 
+-		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
++		if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
++		    is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV12_1X36))
+ 			output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
+ 
+-		output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
++		if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB121212_1X36))
++			output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
+ 	}
+ 
+ 	if (max_bpc >= 10 && info->bpc >= 10) {
+-		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
++		if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) &&
++		    is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY10_1X20))
+ 			output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
+ 
+-		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
++		if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
++		    is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV10_1X30))
+ 			output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
+ 
+-		output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
++		if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB101010_1X30))
++			output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
+ 	}
+ 
+-	if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
++	if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) &&
++	    is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY8_1X16))
+ 		output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
+ 
+-	if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
++	if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
++	    is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV8_1X24))
+ 		output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+ 
+ 	*num_output_fmts = i;
+ 
+@@ -2946,11 +2969,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
+ 	struct dw_hdmi *hdmi = bridge->driver_private;
+ 	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
+ 	enum drm_mode_status mode_status = MODE_OK;
++	int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000;
++	int clock = mode->clock;
+ 
+ 	/* We don't support double-clocked modes */
+ 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ 		return MODE_BAD;
+ 
++	if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
++	    (info->color_formats & DRM_COLOR_FORMAT_YCBCR420))
++		clock /= 2;
++
++	if (clock > max_tmds_clock)
++		return MODE_CLOCK_HIGH;
++
+ 	if (pdata->mode_valid)
+ 		mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
+ 						mode);
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 20 Dec 2019 08:12:42 +0000
+Subject: [PATCH] WIP: drm/rockchip: dw_hdmi: add 10-bit rgb bus format
+
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 42 +++++++++++++++++++++
+ drivers/gpu/drm/rockchip/rockchip_drm_drv.h |  1 +
+ 2 files changed, 43 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index d6d8f3335813..89424c5bc24a 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -84,6 +84,8 @@ struct rockchip_hdmi {
+ 	struct phy *phy;
+ };
+ 
++#define to_crtc_state(x)	container_of(x, struct drm_crtc_state, x)
++
+ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge)
+ {
+ 	return container_of(bridge, struct rockchip_hdmi, bridge);
+@@ -341,6 +343,11 @@ dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge,
+ 				 const struct drm_display_mode *adjusted_mode)
+ {
+ 	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
++	struct drm_crtc_state *crtc_state = to_crtc_state(adjusted_mode);
++	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
++
++	if (hdmi->phy)
++		phy_set_bus_width(hdmi->phy, s->bus_width);
+ 
+ 	clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000);
+ }
+@@ -381,6 +388,17 @@ static bool is_rgb(u32 format)
+ {
+ 	switch (format) {
+ 	case MEDIA_BUS_FMT_RGB888_1X24:
++	case MEDIA_BUS_FMT_RGB101010_1X30:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static bool is_10bit(u32 format)
++{
++	switch (format) {
++	case MEDIA_BUS_FMT_RGB101010_1X30:
+ 		return true;
+ 	default:
+ 		return false;
+@@ -394,9 +412,24 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge,
+ 				     struct drm_connector_state *conn_state)
+ {
+ 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
++	struct drm_atomic_state *state = bridge_state->base.state;
++	struct drm_crtc_state *old_crtc_state;
++	struct rockchip_crtc_state *old_state;
++	u32 format = bridge_state->output_bus_cfg.format;
+ 
+ 	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
+ 	s->output_type = DRM_MODE_CONNECTOR_HDMIA;
++	s->output_bpc = 10;
++	s->bus_format = format;
++	s->bus_width = is_10bit(format) ? 10 : 8;
++
++	old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc);
++	if (old_crtc_state && !crtc_state->mode_changed) {
++		old_state = to_rockchip_crtc_state(old_crtc_state);
++		if (s->bus_format != old_state->bus_format ||
++		    s->bus_width != old_state->bus_width)
++			crtc_state->mode_changed = true;
++	}
+ 
+ 	return 0;
+ }
+@@ -408,10 +441,19 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
+ 					u32 output_fmt,
+ 					unsigned int *num_input_fmts)
+ {
++	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
++	struct drm_encoder *encoder = bridge->encoder;
+ 	u32 *input_fmt;
++	bool has_10bit = true;
+ 
+ 	*num_input_fmts = 0;
+ 
++	if (drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder))
++		has_10bit = false;
++
++	if (!has_10bit && is_10bit(output_fmt))
++		return NULL;
++
+ 	if (!is_rgb(output_fmt))
+ 		return NULL;
+ 
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+index 1641440837af..381e5ccab5f3 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+@@ -34,6 +34,7 @@ struct rockchip_crtc_state {
+ 	u32 bus_format;
+ 	u32 bus_flags;
+ 	int color_space;
++	int bus_width;
+ };
+ #define to_rockchip_crtc_state(s) \
+ 		container_of(s, struct rockchip_crtc_state, base)
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 8 Dec 2019 23:42:44 +0000
+Subject: [PATCH] WIP: drm: dw-hdmi: add content type connector property
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 7f6ffbc3e7b2..ae4c49e84470 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -1790,6 +1790,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi,
+ 			    const struct drm_connector *connector,
+ 			    const struct drm_display_mode *mode)
+ {
++	const struct drm_connector_state *conn_state = connector->state;
+ 	struct hdmi_avi_infoframe frame;
+ 	u8 val;
+ 
+@@ -1847,6 +1848,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi,
+ 			HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
+ 	}
+ 
++	drm_hdmi_avi_infoframe_content_type(&frame, conn_state);
++
+ 	/*
+ 	 * The Designware IP uses a different byte format from standard
+ 	 * AVI info frames, though generally the bits are in the correct
+@@ -2551,7 +2554,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
+ 	if (!crtc)
+ 		return 0;
+ 
+-	if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
++	if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state) ||
++	    old_state->content_type != new_state->content_type) {
+ 		crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ 		if (IS_ERR(crtc_state))
+ 			return PTR_ERR(crtc_state);
+@@ -2619,6 +2623,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
+ 
+ 	drm_connector_attach_max_bpc_property(connector, 8, 16);
+ 
++	drm_connector_attach_content_type_property(connector);
++
+ 	if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
+ 		drm_connector_attach_hdr_output_metadata_property(connector);
+ 
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 20 Dec 2019 08:12:43 +0000
+Subject: [PATCH] WIP: drm/rockchip: add yuv444 support
+
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 29 ++++++++++++++++++++-
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++++++
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  6 +++++
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 19 ++++++++++++++
+ 4 files changed, 82 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 89424c5bc24a..05de2052d95d 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -68,6 +68,7 @@ struct rockchip_hdmi_chip_data {
+ 	int	lcdsel_grf_reg;
+ 	u32	lcdsel_big;
+ 	u32	lcdsel_lit;
++	bool	ycbcr_444_allowed;
+ };
+ 
+ struct rockchip_hdmi {
+@@ -395,10 +396,22 @@ static bool is_rgb(u32 format)
+ 	}
+ }
+ 
++static bool is_yuv444(u32 format)
++{
++	switch (format) {
++	case MEDIA_BUS_FMT_YUV10_1X30:
++	case MEDIA_BUS_FMT_YUV8_1X24:
++		return true;
++	default:
++		return false;
++	}
++}
++
+ static bool is_10bit(u32 format)
+ {
+ 	switch (format) {
+ 	case MEDIA_BUS_FMT_RGB101010_1X30:
++	case MEDIA_BUS_FMT_YUV10_1X30:
+ 		return true;
+ 	default:
+ 		return false;
+@@ -415,12 +428,22 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge,
+ 	struct drm_atomic_state *state = bridge_state->base.state;
+ 	struct drm_crtc_state *old_crtc_state;
+ 	struct rockchip_crtc_state *old_state;
++	struct drm_bridge *next_bridge;
++	struct drm_bridge_state *next_bridge_state;
+ 	u32 format = bridge_state->output_bus_cfg.format;
+ 
+ 	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
+ 	s->output_type = DRM_MODE_CONNECTOR_HDMIA;
+ 	s->output_bpc = 10;
+ 	s->bus_format = format;
++
++	next_bridge = drm_bridge_get_next_bridge(bridge);
++	if (next_bridge) {
++		next_bridge_state = drm_atomic_get_new_bridge_state(state,
++								next_bridge);
++		format = next_bridge_state->output_bus_cfg.format;
++	}
++
+ 	s->bus_width = is_10bit(format) ? 10 : 8;
+ 
+ 	old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc);
+@@ -454,7 +477,10 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
+ 	if (!has_10bit && is_10bit(output_fmt))
+ 		return NULL;
+ 
+-	if (!is_rgb(output_fmt))
++	if (is_yuv444(output_fmt)) {
++		if (!hdmi->chip_data->ycbcr_444_allowed)
++			return NULL;
++	} else if (!is_rgb(output_fmt))
+ 		return NULL;
+ 
+ 	input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL);
+@@ -604,6 +630,7 @@ static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
+ 
+ static struct rockchip_hdmi_chip_data rk3328_chip_data = {
+ 	.lcdsel_grf_reg = -1,
++	.ycbcr_444_allowed = true,
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index eadf1b0f1704..0e4eca0d5121 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -347,6 +347,17 @@ static int vop_convert_afbc_format(uint32_t format)
+ 	return -EINVAL;
+ }
+ 
++static bool is_yuv_output(uint32_t bus_format)
++{
++	switch (bus_format) {
++	case MEDIA_BUS_FMT_YUV8_1X24:
++	case MEDIA_BUS_FMT_YUV10_1X30:
++		return true;
++	default:
++		return false;
++	}
++}
++
+ static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
+ 				  uint32_t dst, bool is_horizontal,
+ 				  int vsu_mode, int *vskiplines)
+@@ -1455,6 +1466,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
+ 	u16 vact_end = vact_st + vdisplay;
+ 	uint32_t pin_pol, val;
+ 	int dither_bpc = s->output_bpc ? s->output_bpc : 10;
++	bool yuv_output = is_yuv_output(s->bus_format);
+ 	int ret;
+ 
+ 	if (old_state && old_state->self_refresh_active) {
+@@ -1520,6 +1532,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
+ 	    !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
+ 		s->output_mode = ROCKCHIP_OUT_MODE_P888;
+ 
++	VOP_REG_SET(vop, common, dsp_data_swap, yuv_output ? 2 : 0);
++
+ 	if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
+ 		VOP_REG_SET(vop, common, pre_dither_down, 1);
+ 	else
+@@ -1535,6 +1549,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	VOP_REG_SET(vop, common, out_mode, s->output_mode);
+ 
++	VOP_REG_SET(vop, common, overlay_mode, yuv_output);
++	VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output);
++
++	/*
++	 * Background color is 10bit depth if vop version >= 3.5
++	 */
++	if (!yuv_output)
++		val = 0;
++	else if (VOP_MAJOR(vop_data->version) == 3 &&
++		 VOP_MINOR(vop_data->version) >= 5)
++		val = 0x20010200;
++	else
++		val = 0x801080;
++	VOP_REG_SET(vop, common, dsp_background, val);
++
+ 	VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
+ 	val = hact_st << 16;
+ 	val |= hact_end;
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+index ca4e2b7415fe..47ad74ef1afb 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+@@ -119,10 +119,16 @@ struct vop_common {
+ 	struct vop_reg mmu_en;
+ 	struct vop_reg out_mode;
+ 	struct vop_reg standby;
++
++	struct vop_reg overlay_mode;
++	struct vop_reg dsp_data_swap;
++	struct vop_reg dsp_out_yuv;
++	struct vop_reg dsp_background;
+ };
+ 
+ struct vop_misc {
+ 	struct vop_reg global_regdone_en;
++	struct vop_reg win_channel[4];
+ };
+ 
+ struct vop_intr {
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index a2b281e290e0..b16a4c42773c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -705,6 +705,11 @@ static const struct vop_common rk3288_common = {
+ 	.dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
+ 	.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
+ 	.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
++
++	.overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16),
++	.dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
++	.dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2),
++	.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
+ };
+ 
+ /*
+@@ -926,6 +931,11 @@ static const struct vop_common rk3399_common = {
+ 	.dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18),
+ 	.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
+ 	.cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
++
++	.overlay_mode = VOP_REG(RK3399_SYS_CTRL, 0x1, 16),
++	.dsp_data_swap = VOP_REG(RK3399_DSP_CTRL0, 0x1f, 12),
++	.dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2),
++	.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
+ };
+ 
+ static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = {
+@@ -1096,6 +1106,10 @@ static const struct vop_output rk3328_output = {
+ 
+ static const struct vop_misc rk3328_misc = {
+ 	.global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
++
++	.win_channel[0] = VOP_REG(RK3328_WIN0_CTRL2, 0xff, 0),
++	.win_channel[1] = VOP_REG(RK3328_WIN1_CTRL2, 0xff, 0),
++	.win_channel[2] = VOP_REG(RK3328_WIN2_CTRL2, 0xff, 0),
+ };
+ 
+ static const struct vop_common rk3328_common = {
+@@ -1108,6 +1122,11 @@ static const struct vop_common rk3328_common = {
+ 	.dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
+ 	.out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
+ 	.cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0),
++
++	.overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
++	.dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
++	.dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2),
++	.dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
+ };
+ 
+ static const struct vop_intr rk3328_vop_intr = {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 20 Dec 2019 08:12:43 +0000
+Subject: [PATCH] WIP: drm/rockchip: add yuv420 support
+
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 22 +++++++++++++++++++++
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 19 +++++++++++++++++-
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++++++----
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  2 ++
+ 4 files changed, 48 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 05de2052d95d..cb201612199f 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -407,9 +407,21 @@ static bool is_yuv444(u32 format)
+ 	}
+ }
+ 
++static bool is_yuv420(u32 format)
++{
++	switch (format) {
++	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
++	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
++		return true;
++	default:
++		return false;
++	}
++}
++
+ static bool is_10bit(u32 format)
+ {
+ 	switch (format) {
++	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
+ 	case MEDIA_BUS_FMT_RGB101010_1X30:
+ 	case MEDIA_BUS_FMT_YUV10_1X30:
+ 		return true;
+@@ -446,6 +458,11 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge,
+ 
+ 	s->bus_width = is_10bit(format) ? 10 : 8;
+ 
++	if (is_yuv420(format)) {
++		s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
++		s->bus_width /= 2;
++	}
++
+ 	old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc);
+ 	if (old_crtc_state && !crtc_state->mode_changed) {
+ 		old_state = to_rockchip_crtc_state(old_crtc_state);
+@@ -466,6 +483,7 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
+ {
+ 	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
+ 	struct drm_encoder *encoder = bridge->encoder;
++	struct drm_connector *connector = conn_state->connector;
+ 	u32 *input_fmt;
+ 	bool has_10bit = true;
+ 
+@@ -480,6 +498,9 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
+ 	if (is_yuv444(output_fmt)) {
+ 		if (!hdmi->chip_data->ycbcr_444_allowed)
+ 			return NULL;
++	} else if (is_yuv420(output_fmt)) {
++		if (!connector->ycbcr_420_allowed)
++			return NULL;
+ 	} else if (!is_rgb(output_fmt))
+ 		return NULL;
+ 
+@@ -640,6 +661,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
+ 	.phy_name = "inno_dw_hdmi_phy2",
+ 	.phy_force_vendor = true,
+ 	.use_drm_infoframe = true,
++	.ycbcr_420_allowed = true,
+ };
+ 
+ static struct rockchip_hdmi_chip_data rk3399_chip_data = {
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index 0e4eca0d5121..e50f71ad3ceb 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -10,6 +10,7 @@
+ #include <linux/iopoll.h>
+ #include <linux/kernel.h>
+ #include <linux/log2.h>
++#include <linux/media-bus-format.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+@@ -348,6 +349,19 @@ static int vop_convert_afbc_format(uint32_t format)
+ }
+ 
+ static bool is_yuv_output(uint32_t bus_format)
++{
++	switch (bus_format) {
++	case MEDIA_BUS_FMT_YUV8_1X24:
++	case MEDIA_BUS_FMT_YUV10_1X30:
++	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
++	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static bool bus_fmt_has_uv_swapped(uint32_t bus_format)
+ {
+ 	switch (bus_format) {
+ 	case MEDIA_BUS_FMT_YUV8_1X24:
+@@ -1532,7 +1546,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
+ 	    !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
+ 		s->output_mode = ROCKCHIP_OUT_MODE_P888;
+ 
+-	VOP_REG_SET(vop, common, dsp_data_swap, yuv_output ? 2 : 0);
++	VOP_REG_SET(vop, common, dsp_data_swap, bus_fmt_has_uv_swapped(s->bus_format) ? 2 : 0);
+ 
+ 	if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
+ 		VOP_REG_SET(vop, common, pre_dither_down, 1);
+@@ -1549,6 +1563,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	VOP_REG_SET(vop, common, out_mode, s->output_mode);
+ 
++	VOP_REG_SET(vop, common, dclk_ddr,
++		    s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
++
+ 	VOP_REG_SET(vop, common, overlay_mode, yuv_output);
+ 	VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output);
+ 
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+index 47ad74ef1afb..94a615dca672 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+@@ -121,6 +121,7 @@ struct vop_common {
+ 	struct vop_reg standby;
+ 
+ 	struct vop_reg overlay_mode;
++	struct vop_reg dclk_ddr;
+ 	struct vop_reg dsp_data_swap;
+ 	struct vop_reg dsp_out_yuv;
+ 	struct vop_reg dsp_background;
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index b16a4c42773c..5463b04240f7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -707,6 +707,7 @@ static const struct vop_common rk3288_common = {
+ 	.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
+ 
+ 	.overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16),
++	.dclk_ddr = VOP_REG(RK3288_DSP_CTRL0, 0x1, 8),
+ 	.dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
+ 	.dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2),
+ 	.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
+@@ -1124,6 +1125,7 @@ static const struct vop_common rk3328_common = {
+ 	.cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0),
+ 
+ 	.overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
++	.dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8),
+ 	.dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
+ 	.dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2),
+ 	.dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 15 Aug 2020 23:20:34 +0200
+Subject: [PATCH] drm/rockchip: enable ycbcr_420_allowed and ycbcr_444_allowed
+ for RK3228
+
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index cb201612199f..8627f6826bfe 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -616,6 +616,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = {
+ 
+ static struct rockchip_hdmi_chip_data rk3228_chip_data = {
+ 	.lcdsel_grf_reg = -1,
++	.ycbcr_444_allowed = true,
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
+@@ -624,6 +625,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
+ 	.phy_ops = &rk3228_hdmi_phy_ops,
+ 	.phy_name = "inno_dw_hdmi_phy2",
+ 	.phy_force_vendor = true,
++	.ycbcr_420_allowed = true,
+ };
+ 
+ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 18 Nov 2017 11:09:39 +0100
+Subject: [PATCH] rockchip: vop: force skip lines if image too big
+
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index e50f71ad3ceb..ef0a078c22f4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -965,6 +965,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
+ 	int format;
+ 	int is_yuv = fb->format->is_yuv;
+ 	int i;
++	int skiplines = 0;
+ 
+ 	/*
+ 	 * can't update plane when vop is disabled.
+@@ -983,8 +984,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
+ 	obj = fb->obj[0];
+ 	rk_obj = to_rockchip_obj(obj);
+ 
++	/*
++	 * Force skip lines when image is yuv and 3840 width,
++	 * fixes a "jumping" green lines issue on RK3328.
++	 */
+ 	actual_w = drm_rect_width(src) >> 16;
+-	actual_h = drm_rect_height(src) >> 16;
++	if (actual_w == 3840 && is_yuv)
++		skiplines = 1;
++	actual_h = drm_rect_height(src) >> (16 + skiplines);
+ 	act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
+ 
+ 	dsp_info = (drm_rect_height(dest) - 1) << 16;
+@@ -1026,7 +1033,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
+ 
+ 	VOP_WIN_SET(vop, win, format, format);
+ 	VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
+-	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
++	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4 >> skiplines));
+ 	VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
+ 	VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
+ 	VOP_WIN_SET(vop, win, y_mir_en,
+@@ -1050,7 +1057,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
+ 		offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
+ 
+ 		dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
+-		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
++		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4 >> skiplines));
+ 		VOP_WIN_SET(vop, win, uv_mst, dma_addr);
+ 
+ 		for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
+
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 10 Apr 2021 16:54:26 +0200
+Subject: [PATCH] drm/bridge: dw-hdmi: fix RGB to YUV color space conversion
+
+We are currently providing color space conversion coefficents
+for RGB to YUV conversion for full range to full range.
+This is wrong, since we are hardcoding YCC quantization range
+limited in the AVI infoframe (which is correct according to
+HDMI specs). This results in to dark colors if this conversion
+is used.
+I verfied this by setting YCC quantization range to full in
+AVI infoframe which resulted in correct colors. Doing this,
+however, will be ignored by some (most) sinks.
+
+This patch fixes this, by providing CSC coefficents which
+convert RGB full range to YUV limited range for both BT601
+and BT709 colorspaces.
+
+Fixes: 9aaf880ed4ee ("imx-drm: Add mx6 hdmi transmitter support")
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index ae4c49e84470..92e621f2714f 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -82,15 +82,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
+ };
+ 
+ static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
+-	{ 0x2591, 0x1322, 0x074b, 0x0000 },
+-	{ 0x6535, 0x2000, 0x7acc, 0x0200 },
+-	{ 0x6acd, 0x7534, 0x2000, 0x0200 }
++	{ 0x2040, 0x1080, 0x0640, 0x0040 },
++	{ 0xe880, 0x1c00, 0xfb80, 0x0200 },
++	{ 0xed80, 0xf680, 0x1c00, 0x0200 }
+ };
+ 
+ static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
+-	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
+-	{ 0x62f0, 0x2000, 0x7d11, 0x0200 },
+-	{ 0x6756, 0x78ab, 0x2000, 0x0200 }
++	{ 0x2740, 0x0bc0, 0x0400, 0x0040 },
++	{ 0xe680, 0x1c00, 0xfd80, 0x0200 },
++	{ 0xea40, 0xf980, 0x1c00, 0x0200 }
+ };
+ 
+ static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Tue, 1 Jun 2021 19:24:37 +0200
+Subject: [PATCH] drm/rockchip: allow 4096px width modes
+
+There is not reason to limit vop output to 3840px width modes.
+Also drop the limitation from dw_hdmi_rockchip_mode_valid, since
+the max dimenstions of the actual vop version is validated in
+vop_crtc_mode_valid anyways.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index ef0a078c22f4..49619f794061 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -424,8 +424,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
+ 	if (info->is_yuv)
+ 		is_yuv = true;
+ 
+-	if (dst_w > 3840) {
+-		DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
++	if (dst_w > 4096) {
++		DRM_DEV_ERROR(vop->dev, "Maximum dst width (4096) exceeded\n");
+ 		return;
+ 	}
+ 
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 1 Oct 2019 20:52:42 +0000
+Subject: [PATCH] media: cec-adap: add debounce support when setting an invalid
+ phys addr
+
+When EDID is refreshed, HDMI cable is unplugged/replugged or
+an AVR is power cycled the CEC phys addr gets invalidated.
+
+This can cause some disruption of CEC communication when
+adapter is being reconfigured.
+
+Add a debounce_ms module option that can be used to debounce setting
+an invalid phys addr. Default is not to use debouncing.
+
+Using a configured debounce_ms of e.g. 5000 ms, cec reconfiguring
+could be avoided when AVR was power cycled on my setup.
+
+Power off AVR (default cec.debounce_ms=0):
+[  101.536866] cec-dw_hdmi: new physical address f.f.f.f
+[  102.495686] cec-dw_hdmi: new physical address 2.1.0.0
+[  102.495913] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses
+[  102.628574] cec-dw_hdmi: config: la 1 pa 2.1.0.0
+[  105.130115] cec-dw_hdmi: new physical address f.f.f.f
+[  106.979705] cec-dw_hdmi: new physical address 2.1.0.0
+[  106.979872] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses
+[  107.112399] cec-dw_hdmi: config: la 1 pa 2.1.0.0
+[  108.979408] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5
+[  109.205386] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11
+
+Power on AVR (default cec.debounce_ms=0):
+[  158.398447] cec-dw_hdmi: new physical address f.f.f.f
+[  161.977714] cec-dw_hdmi: new physical address 2.1.0.0
+[  161.978766] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses
+[  162.115624] cec-dw_hdmi: config: la 1 pa 2.1.0.0
+[  162.402750] cec-dw_hdmi: new physical address f.f.f.f
+[  162.403389] cec-dw_hdmi: cec_transmit_msg_fh: adapter is unconfigured
+[  162.886757] cec-dw_hdmi: new physical address 2.1.0.0
+[  162.886964] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses
+[  163.510725] cec-dw_hdmi: config: la 1 pa 2.1.0.0
+[  173.034200] cec-dw_hdmi: message 10 89 02 05 timed out
+
+Power off AVR (cec.debounce_ms=5000):
+[  251.720471] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5
+[  251.922432] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11
+
+Power on AVR (cec.debounce_ms=5000):
+[  291.154262] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5
+[  291.296199] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/media/cec/core/cec-adap.c |  9 ++++++++-
+ drivers/media/cec/core/cec-core.c | 18 ++++++++++++++++++
+ drivers/media/cec/core/cec-priv.h |  1 +
+ include/media/cec.h               |  2 ++
+ 4 files changed, 29 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c
+index 41a79293ee02..542ab1425339 100644
+--- a/drivers/media/cec/core/cec-adap.c
++++ b/drivers/media/cec/core/cec-adap.c
+@@ -1674,8 +1674,15 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block)
+ 	if (IS_ERR_OR_NULL(adap))
+ 		return;
+ 
++	cancel_delayed_work_sync(&adap->debounce_work);
++
+ 	mutex_lock(&adap->lock);
+-	__cec_s_phys_addr(adap, phys_addr, block);
++	if (cec_debounce_ms > 0 && !block && phys_addr == CEC_PHYS_ADDR_INVALID &&
++	    adap->phys_addr != phys_addr)
++		schedule_delayed_work(&adap->debounce_work,
++				      msecs_to_jiffies(cec_debounce_ms));
++	else
++		__cec_s_phys_addr(adap, phys_addr, block);
+ 	mutex_unlock(&adap->lock);
+ }
+ EXPORT_SYMBOL_GPL(cec_s_phys_addr);
+diff --git a/drivers/media/cec/core/cec-core.c b/drivers/media/cec/core/cec-core.c
+index af358e901b5f..bece8c56e5af 100644
+--- a/drivers/media/cec/core/cec-core.c
++++ b/drivers/media/cec/core/cec-core.c
+@@ -40,6 +40,10 @@ static bool debug_phys_addr;
+ module_param(debug_phys_addr, bool, 0644);
+ MODULE_PARM_DESC(debug_phys_addr, "add CEC_CAP_PHYS_ADDR if set");
+ 
++int cec_debounce_ms;
++module_param_named(debounce_ms, cec_debounce_ms, int, 0644);
++MODULE_PARM_DESC(debounce_ms, "debounce invalid phys addr");
++
+ static dev_t cec_dev_t;
+ 
+ /* Active devices */
+@@ -188,6 +192,8 @@ static void cec_devnode_unregister(struct cec_adapter *adap)
+ 
+ 	mutex_unlock(&devnode->lock);
+ 
++	cancel_delayed_work_sync(&adap->debounce_work);
++
+ 	mutex_lock(&adap->lock);
+ 	__cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false);
+ 	__cec_s_log_addrs(adap, NULL, false);
+@@ -246,6 +252,17 @@ static const struct file_operations cec_error_inj_fops = {
+ };
+ #endif
+ 
++static void cec_s_phys_addr_debounce(struct work_struct *work)
++{
++	struct delayed_work *delayed_work = to_delayed_work(work);
++	struct cec_adapter *adap =
++		container_of(delayed_work, struct cec_adapter, debounce_work);
++
++	mutex_lock(&adap->lock);
++	__cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false);
++	mutex_unlock(&adap->lock);
++}
++
+ struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops,
+ 					 void *priv, const char *name, u32 caps,
+ 					 u8 available_las)
+@@ -283,6 +300,7 @@ struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops,
+ 	INIT_LIST_HEAD(&adap->transmit_queue);
+ 	INIT_LIST_HEAD(&adap->wait_queue);
+ 	init_waitqueue_head(&adap->kthread_waitq);
++	INIT_DELAYED_WORK(&adap->debounce_work, cec_s_phys_addr_debounce);
+ 
+ 	/* adap->devnode initialization */
+ 	INIT_LIST_HEAD(&adap->devnode.fhs);
+diff --git a/drivers/media/cec/core/cec-priv.h b/drivers/media/cec/core/cec-priv.h
+index b78df931aa74..ebbea63ea9de 100644
+--- a/drivers/media/cec/core/cec-priv.h
++++ b/drivers/media/cec/core/cec-priv.h
+@@ -37,6 +37,7 @@ static inline bool msg_is_raw(const struct cec_msg *msg)
+ 
+ /* cec-core.c */
+ extern int cec_debug;
++extern int cec_debounce_ms;
+ int cec_get_device(struct cec_devnode *devnode);
+ void cec_put_device(struct cec_devnode *devnode);
+ 
+diff --git a/include/media/cec.h b/include/media/cec.h
+index abee41ae02d0..544eedb5d671 100644
+--- a/include/media/cec.h
++++ b/include/media/cec.h
+@@ -236,6 +236,8 @@ struct cec_adapter {
+ 	struct task_struct *kthread;
+ 	wait_queue_head_t kthread_waitq;
+ 
++	struct delayed_work debounce_work;
++
+ 	const struct cec_adap_ops *ops;
+ 	void *priv;
+ 	u32 capabilities;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Fri, 22 Oct 2021 11:17:30 +0200
+Subject: [PATCH] WIP: drm/bridge: synopsys: Fix CEC not working after
+ power-cyclying
+
+This fixes standby -> power-on on Rockchip platform for, at least,
+RK3288/RK3328/RK3399 where CEC wasn't working after powering on again.
+It might differ for other phy implementations:
+The whole HPD-detection part shoud be reworked and we should in general
+avoid to rely in RX_SENSE phy status (at least for HDMI), since it differs
+depending on sink's implementation.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 92e621f2714f..7551e3ab77d6 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -3179,12 +3179,6 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ 				       phy_stat & HDMI_PHY_HPD,
+ 				       phy_stat & HDMI_PHY_RX_SENSE);
+ 
+-		if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
+-			mutex_lock(&hdmi->cec_notifier_mutex);
+-			cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
+-			mutex_unlock(&hdmi->cec_notifier_mutex);
+-		}
+-
+ 		if (phy_stat & HDMI_PHY_HPD)
+ 			status = connector_status_connected;
+ 
+@@ -3201,6 +3195,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ 			drm_helper_hpd_irq_event(hdmi->bridge.dev);
+ 			drm_bridge_hpd_notify(&hdmi->bridge, status);
+ 		}
++
++		if (status == connector_status_disconnected &&
++		    (phy_stat & HDMI_PHY_RX_SENSE) &&
++		    (phy_int_pol & HDMI_PHY_RX_SENSE)) {
++			mutex_lock(&hdmi->cec_notifier_mutex);
++			cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
++			mutex_unlock(&hdmi->cec_notifier_mutex);
++		}
+ 	}
+ 
+ 	hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 9 Oct 2020 15:24:53 +0000
+Subject: [PATCH] drm/rockchip: vop: create planes in window order
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 +++------------------
+ 1 file changed, 4 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index 49619f794061..9915bf124374 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -2023,19 +2023,10 @@ static int vop_create_crtc(struct vop *vop)
+ 	int ret;
+ 	int i;
+ 
+-	/*
+-	 * Create drm_plane for primary and cursor planes first, since we need
+-	 * to pass them to drm_crtc_init_with_planes, which sets the
+-	 * "possible_crtcs" to the newly initialized crtc.
+-	 */
+ 	for (i = 0; i < vop_data->win_size; i++) {
+ 		struct vop_win *vop_win = &vop->win[i];
+ 		const struct vop_win_data *win_data = vop_win->data;
+ 
+-		if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
+-		    win_data->type != DRM_PLANE_TYPE_CURSOR)
+-			continue;
+-
+ 		ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
+ 					       0, &vop_plane_funcs,
+ 					       win_data->phy->data_formats,
+@@ -2068,32 +2059,13 @@ static int vop_create_crtc(struct vop *vop)
+ 		drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
+ 	}
+ 
+-	/*
+-	 * Create drm_planes for overlay windows with possible_crtcs restricted
+-	 * to the newly created crtc.
+-	 */
++	/* Set possible_crtcs to the newly created crtc for overlay windows */
+ 	for (i = 0; i < vop_data->win_size; i++) {
+ 		struct vop_win *vop_win = &vop->win[i];
+-		const struct vop_win_data *win_data = vop_win->data;
+-		unsigned long possible_crtcs = drm_crtc_mask(crtc);
+-
+-		if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
+-			continue;
+ 
+-		ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
+-					       possible_crtcs,
+-					       &vop_plane_funcs,
+-					       win_data->phy->data_formats,
+-					       win_data->phy->nformats,
+-					       win_data->phy->format_modifiers,
+-					       win_data->type, NULL);
+-		if (ret) {
+-			DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
+-				      ret);
+-			goto err_cleanup_crtc;
+-		}
+-		drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
+-		vop_plane_add_properties(&vop_win->base, win_data);
++		plane = &vop_win->base;
++		if (plane->type == DRM_PLANE_TYPE_OVERLAY)
++			plane->possible_crtcs = drm_crtc_mask(crtc);
+ 	}
+ 
+ 	port = of_get_child_by_name(dev->of_node, "port");
diff --git a/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1001-v4l2-rockchip.patch b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1001-v4l2-rockchip.patch
new file mode 100644
index 000000000000..d705909546c6
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1001-v4l2-rockchip.patch
@@ -0,0 +1,506 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 23 May 2020 10:16:01 +0000
+Subject: [PATCH] WIP: media: rkvdec: pm runtime dont use autosuspend before
+ disable and cleanup
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/rkvdec/rkvdec.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index 4f5436c89e08..eaf2f133a264 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -1125,9 +1125,9 @@ static int rkvdec_remove(struct platform_device *pdev)
+ 
+ 	cancel_delayed_work_sync(&rkvdec->watchdog_work);
+ 
+-	rkvdec_v4l2_cleanup(rkvdec);
+-	pm_runtime_disable(&pdev->dev);
+ 	pm_runtime_dont_use_autosuspend(&pdev->dev);
++	pm_runtime_disable(&pdev->dev);
++	rkvdec_v4l2_cleanup(rkvdec);
+ }
+ 
+ #ifdef CONFIG_PM
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Randy Li <ayaka@soulik.info>
+Date: Sun, 6 Jan 2019 01:48:37 +0800
+Subject: [PATCH] soc: rockchip: power-domain: export idle request
+
+We need to put the power status of HEVC IP into IDLE unless
+we can't reset that IP or the SoC would crash down.
+rockchip_pmu_idle_request(dev, true)---> enter idle
+rockchip_pmu_idle_request(dev, false)---> exit idle
+
+Signed-off-by: Caesar Wang <wxt@rock-chips.com>
+Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
+Signed-off-by: Randy Li <ayaka@soulik.info>
+---
+ drivers/pmdomain/rockchip/pm-domains.c | 23 +++++++++++++++++++++++
+ include/linux/rockchip_pmu.h      | 15 +++++++++++++++
+ include/soc/rockchip/pm_domains.h |  6 ++++++
+ 3 files changed, 44 insertions(+)
+ create mode 100644 include/linux/rockchip_pmu.h
+
+diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
+index 89795abac951..ffb5d62c9d52 100644
+--- a/drivers/pmdomain/rockchip/pm-domains.c
++++ b/drivers/pmdomain/rockchip/pm-domains.c
+@@ -309,6 +309,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
+ 	return 0;
+ }
+ 
++int rockchip_pmu_idle_request(struct device *dev, bool idle)
++{
++	struct generic_pm_domain *genpd;
++	struct rockchip_pm_domain *pd;
++	int ret;
++
++	if (IS_ERR_OR_NULL(dev))
++		return -EINVAL;
++
++	if (IS_ERR_OR_NULL(dev->pm_domain))
++		return -EINVAL;
++
++	genpd = pd_to_genpd(dev->pm_domain);
++	pd = to_rockchip_pd(genpd);
++
++	mutex_lock(&pd->pmu->mutex);
++	ret = rockchip_pmu_set_idle_request(pd, idle);
++	mutex_unlock(&pd->pmu->mutex);
++
++	return ret;
++}
++EXPORT_SYMBOL(rockchip_pmu_idle_request);
++
+ static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
+ {
+ 	int i;
+diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h
+new file mode 100644
+index 000000000000..720b3314e71a
+--- /dev/null
++++ b/include/linux/rockchip_pmu.h
+@@ -0,0 +1,15 @@
++/*
++ * pm_domain.h - Definitions and headers related to device power domains.
++ *
++ * Copyright (C) 2017 Randy Li <ayaka@soulik.info>.
++ *
++ * This file is released under the GPLv2.
++ */
++
++#ifndef _LINUX_ROCKCHIP_PM_H
++#define _LINUX_ROCKCHIP_PM_H
++#include <linux/device.h>
++
++int rockchip_pmu_idle_request(struct device *dev, bool idle);
++
++#endif /* _LINUX_ROCKCHIP_PM_H */
+diff --git a/include/soc/rockchip/pm_domains.h b/include/soc/rockchip/pm_domains.h
+index 7dbd941fc937..c5a59dd71754 100644
+--- a/include/soc/rockchip/pm_domains.h
++++ b/include/soc/rockchip/pm_domains.h
+@@ -10,6 +10,7 @@
+ 
+ int rockchip_pmu_block(void);
+ void rockchip_pmu_unblock(void);
++int rockchip_pmu_idle_request(struct device *dev, bool idle);
+ 
+ #else /* CONFIG_ROCKCHIP_PM_DOMAINS */
+ 
+@@ -20,6 +21,11 @@ static inline int rockchip_pmu_block(void)
+ 
+ static inline void rockchip_pmu_unblock(void) { }
+ 
++static inline int rockchip_pmu_idle_request(struct device *dev, bool idle)
++{
++	return -ENOTSUPP;
++}
++
+ #endif /* CONFIG_ROCKCHIP_PM_DOMAINS */
+ 
+ #endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Wed, 20 May 2020 17:04:47 +0200
+Subject: [PATCH] WIP: media: rkvdec: implement reset controls
+
+---
+ .../bindings/media/rockchip,vdec.yaml         | 19 +++++++
+ drivers/staging/media/rkvdec/rkvdec-regs.h    |  5 ++
+ drivers/staging/media/rkvdec/rkvdec.c         | 53 +++++++++++++++++++
+ drivers/staging/media/rkvdec/rkvdec.h         | 11 +++-
+ 4 files changed, 87 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
+index 3bcfb8e12333..dd6958df1de8 100644
+--- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
+@@ -53,6 +53,18 @@ properties:
+   iommus:
+     maxItems: 1
+ 
++  resets:
++    maxItems: 6
++
++  reset-names:
++    items:
++      - const: video_h
++      - const: video_a
++      - const: video_core
++      - const: video_cabac
++      - const: niu_a
++      - const: niu_h
++
+ required:
+   - compatible
+   - reg
+@@ -60,6 +72,8 @@ required:
+   - clocks
+   - clock-names
+   - power-domains
++  - resets
++  - reset-names
+ 
+ additionalProperties: false
+ 
+@@ -78,6 +92,11 @@ examples:
+         clock-names = "axi", "ahb", "cabac", "core";
+         power-domains = <&power RK3399_PD_VDU>;
+         iommus = <&vdec_mmu>;
++        resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
++                 <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
++                 <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
++        reset-names = "video_h", "video_a", "video_core", "video_cabac",
++                      "niu_a", "niu_h";
+     };
+ 
+ ...
+diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
+index 15b9bee92016..3acc914888f6 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
+@@ -28,6 +28,11 @@
+ #define RKVDEC_SOFTRST_EN_P				BIT(20)
+ #define RKVDEC_FORCE_SOFTRESET_VALID			BIT(21)
+ #define RKVDEC_SOFTRESET_RDY				BIT(22)
++#define RKVDEC_ERR_MASK					(RKVDEC_BUS_STA \
++							 | RKVDEC_ERR_STA \
++							 | RKVDEC_TIMEOUT_STA \
++							 | RKVDEC_BUF_EMPTY_STA \
++							 | RKVDEC_COLMV_REF_ERR_STA )
+ 
+ #define RKVDEC_REG_SYSCTRL				0x008
+ #define RKVDEC_IN_ENDIAN				BIT(0)
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index eaf2f133a264..f55abb7c377f 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -10,12 +10,15 @@
+  */
+ 
+ #include <linux/clk.h>
++#include <linux/delay.h>
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm.h>
+ #include <linux/pm_runtime.h>
++#include <linux/reset.h>
++#include <linux/rockchip_pmu.h>
+ #include <linux/slab.h>
+ #include <linux/videodev2.h>
+ #include <linux/workqueue.h>
+@@ -717,6 +720,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx,
+ 
+ 	pm_runtime_mark_last_busy(rkvdec->dev);
+ 	pm_runtime_put_autosuspend(rkvdec->dev);
++
++	if (result == VB2_BUF_STATE_ERROR &&
++	    rkvdec->reset_mask == RESET_NONE)
++		rkvdec->reset_mask |= RESET_SOFT;
++
+ 	rkvdec_job_finish_no_pm(ctx, result);
+ }
+ 
+@@ -754,6 +762,33 @@ static void rkvdec_device_run(void *priv)
+ 
+ 	if (WARN_ON(!desc))
+ 		return;
++	if (rkvdec->reset_mask != RESET_NONE) {
++
++		if (rkvdec->reset_mask & RESET_SOFT) {
++			writel(RKVDEC_SOFTRST_EN_P,
++			       rkvdec->regs + RKVDEC_REG_INTERRUPT);
++			udelay(RKVDEC_RESET_DELAY);
++			if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT)
++			    & RKVDEC_SOFTRESET_RDY)
++				dev_info_ratelimited(rkvdec->dev,
++						      "softreset failed\n");
++		}
++
++		if (rkvdec->reset_mask & RESET_HARD) {
++			rockchip_pmu_idle_request(rkvdec->dev, true);
++			ret = reset_control_assert(rkvdec->rstc);
++			if (!ret) {
++				udelay(RKVDEC_RESET_DELAY);
++				ret = reset_control_deassert(rkvdec->rstc);
++			}
++			rockchip_pmu_idle_request(rkvdec->dev, false);
++			if (ret)
++				dev_notice_ratelimited(rkvdec->dev,
++							"hardreset failed\n");
++		}
++		rkvdec->reset_mask = RESET_NONE;
++		pm_runtime_suspend(rkvdec->dev);
++	}
+ 
+ 	ret = pm_runtime_resume_and_get(rkvdec->dev);
+ 	if (ret < 0) {
+@@ -1020,6 +1055,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv)
+ 	if (cancel_delayed_work(&rkvdec->watchdog_work)) {
+ 		struct rkvdec_ctx *ctx;
+ 
++		if (state == VB2_BUF_STATE_ERROR) {
++			rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ?
++						RESET_HARD : RESET_SOFT;
++		}
++
+ 		ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
+ 		rkvdec_job_finish(ctx, state);
+ 	}
+@@ -1037,6 +1077,7 @@ static void rkvdec_watchdog_func(struct work_struct *work)
+ 	ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
+ 	if (ctx) {
+ 		dev_err(rkvdec->dev, "Frame processing timed out!\n");
++		rkvdec->reset_mask |= RESET_HARD;
+ 		writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT);
+ 		writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL);
+ 		rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR);
+@@ -1105,6 +1146,18 @@ static int rkvdec_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
++
++	rkvdec->rstc = devm_reset_control_array_get(&pdev->dev, false, true);
++	if (IS_ERR(rkvdec->rstc)) {
++		dev_err(&pdev->dev,
++			"get resets failed %ld\n", PTR_ERR(rkvdec->rstc));
++		return PTR_ERR(rkvdec->rstc);
++	} else {
++		dev_dbg(&pdev->dev,
++			 "requested %d resets\n",
++			 reset_control_get_count(&pdev->dev));
++	}
++
+ 	pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
+ 	pm_runtime_use_autosuspend(&pdev->dev);
+ 	pm_runtime_enable(&pdev->dev);
+diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
+index b9e219438bc9..f02f79c405f0 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.h
++++ b/drivers/staging/media/rkvdec/rkvdec.h
+@@ -11,10 +11,11 @@
+ #ifndef RKVDEC_H_
+ #define RKVDEC_H_
+ 
++#include <linux/clk.h>
+ #include <linux/platform_device.h>
++#include <linux/reset.h>
+ #include <linux/videodev2.h>
+ #include <linux/wait.h>
+-#include <linux/clk.h>
+ 
+ #include <media/v4l2-ctrls.h>
+ #include <media/v4l2-device.h>
+@@ -22,6 +23,12 @@
+ #include <media/videobuf2-core.h>
+ #include <media/videobuf2-dma-contig.h>
+ 
++#define RESET_NONE		0
++#define RESET_SOFT		BIT(0)
++#define RESET_HARD		BIT(1)
++
++#define RKVDEC_RESET_DELAY	5
++
+ struct rkvdec_ctx;
+ 
+ struct rkvdec_ctrl_desc {
+@@ -96,6 +103,8 @@ struct rkvdec_dev {
+ 	void __iomem *regs;
+ 	struct mutex vdev_lock; /* serializes ioctls */
+ 	struct delayed_work watchdog_work;
++	struct reset_control *rstc;
++	u8 reset_mask;
+ };
+ 
+ struct rkvdec_ctx {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Tue, 18 Aug 2020 11:38:04 +0200
+Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399
+
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 980b12cb0a49..6e3149e587c5 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -1345,6 +1348,11 @@ vdec: video-codec@ff660000 {
+ 		clock-names = "axi", "ahb", "cabac", "core";
+ 		iommus = <&vdec_mmu>;
+ 		power-domains = <&power RK3399_PD_VDU>;
++		resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
++			 <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
++			 <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
++		reset-names = "video_h", "video_a", "video_core", "video_cabac",
++			       "niu_a", "niu_h";
+ 	};
+ 
+ 	vdec_mmu: iommu@ff660480 {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 21 Aug 2021 16:12:36 +0200
+Subject: [PATCH] media: hantro: rockchip: Increase RK3288's max ACLK
+
+Required to proper decode H.264@4K
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/media/platform/verisilicon/rockchip_vpu_hw.c | 14 +++++++++++---
+ 1 file changed, 11 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+index 8de6fd2e8eef..002b1a600f93 100644
+--- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
++++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+@@ -15,7 +15,8 @@
+ #include "rockchip_vpu2_regs.h"
+ 
+ #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
+-#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
++#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000)
++#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000)
+ #define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000)
+ 
+ #define ROCKCHIP_VPU981_MIN_SIZE 64
+@@ -346,13 +347,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
+ 	return 0;
+ }
+ 
+-static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
++static int rk3288_vpu_hw_init(struct hantro_dev *vpu)
+ {
+ 	/* Bump ACLK to max. possible freq. to improve performance. */
+ 	clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
+ 	return 0;
+ }
+ 
++static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
++{
++	/* Bump ACLK to max. possible freq. to improve performance. */
++	clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ);
++	return 0;
++}
++
+ static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
+ {
+ 	struct hantro_dev *vpu = ctx->dev;
+@@ -592,7 +600,7 @@ const struct hantro_variant rk3288_vpu_variant = {
+ 	.codec_ops = rk3288_vpu_codec_ops,
+ 	.irqs = rockchip_vpu1_irqs,
+ 	.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
+-	.init = rockchip_vpu_hw_init,
++	.init = rk3288_vpu_hw_init,
+ 	.clk_names = rockchip_vpu_clk_names,
+ 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
+ };
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 4 Jul 2021 15:19:44 +0200
+Subject: [PATCH] media: rkvdec: disable QoS for VP9 (corruptions on RK3328
+ otherwise)
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++
+ drivers/staging/media/rkvdec/rkvdec-vp9.c  | 8 ++++++++
+ 2 files changed, 10 insertions(+)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
+index 3acc914888f6..265f5234f4eb 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
+@@ -222,6 +222,8 @@
+ #define RKVDEC_REG_H264_ERR_E				0x134
+ #define RKVDEC_H264_ERR_EN_HIGHBITS(x)			((x) & 0x3fffffff)
+ 
++#define RKVDEC_QOS_CTRL					0x18C
++
+ #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND		0x410
+ #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND		0x450
+ 
+diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c
+index d8c1c0db15c7..a289bc968e91 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-vp9.c
++++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c
+@@ -802,6 +802,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
+ 	struct rkvdec_dev *rkvdec = ctx->dev;
+ 	struct rkvdec_vp9_run run = { };
+ 	int ret;
++	u32 reg;
+ 
+ 	ret = rkvdec_vp9_run_preamble(ctx, &run);
+ 	if (ret) {
+@@ -823,6 +824,13 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
+ 	writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
+ 
+ 	writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
++
++	/* disable QOS for RK3328 - no effect on other SoCs */
++	reg = readl(rkvdec->regs + RKVDEC_QOS_CTRL);
++	reg |= 0xFFFF;
++	reg &= (~BIT(12));
++	writel(reg, rkvdec->regs + RKVDEC_QOS_CTRL);
++
+ 	/* Start decoding! */
+ 	writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
+ 	       RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Thu, 16 Jun 2022 13:18:22 +0200
+Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3328
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 5519347232f6..431c4ec198be 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -674,6 +674,11 @@ vdec: video-codec@ff360000 {
+ 		assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
+ 				  <&cru SCLK_VDEC_CORE>;
+ 		assigned-clock-rates = <400000000>, <400000000>, <300000000>;
++		resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>,
++			 <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>,
++			 <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>;
++		reset-names = "video_h", "video_a", "video_core", "video_cabac",
++			       "niu_a", "niu_h";
+ 		iommus = <&vdec_mmu>;
+ 		power-domains = <&power RK3328_PD_VIDEO>;
+ 	};
diff --git a/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1002-for-libreelec.patch b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1002-for-libreelec.patch
new file mode 100644
index 000000000000..1143681e4d09
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1002-for-libreelec.patch
@@ -0,0 +1,688 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Wed, 2 Sep 2020 19:52:02 +0200
+Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and
+ cooling cell for RK3328
+
+Note: since the regulator that supplies the GPU usually also supplies
+other SoC components, we have to make sure voltage is never lower then
+1075 mV - also disable 500 MHz for now, since it will crash if rkvdec
+is running at the same time (voltage to high)
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ .../arm64/boot/dts/rockchip/rk3328-roc-cc.dts |  4 +++
+ .../arm64/boot/dts/rockchip/rk3328-rock64.dts |  4 +++
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi      | 35 +++++++++++++++++++
+ 3 files changed, 43 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+index aa22a0c22265..51c7723d6762 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -166,6 +166,10 @@ &gmac2io {
+ 	status = "okay";
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_logic>;
++};
++
+ &hdmi {
+ 	status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+index f69a38f42d2d..c198a8a7f95a 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+@@ -162,6 +162,10 @@ &gmac2io {
+ 	status = "okay";
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_logic>;
++};
++
+ &hdmi {
+ 	status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 431c4ec198be..eec03adf0902 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -300,6 +300,11 @@ power: power-controller {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 
++			power-domain@RK3328_PD_GPU {
++				reg = <RK3328_PD_GPU>;
++				clocks = <&cru ACLK_GPU>;
++				#power-domain-cells = <0>;
++			};
+ 			power-domain@RK3328_PD_HEVC {
+ 				reg = <RK3328_PD_HEVC>;
+ 				#power-domain-cells = <0>;
+@@ -539,6 +544,11 @@ map0 {
+ 							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ 					contribution = <4096>;
+ 				};
++				map1 {
++					trip = <&target>;
++					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++					contribution = <4096>;
++				};
+ 			};
+ 		};
+ 
+@@ -620,7 +630,32 @@ gpu: gpu@ff300000 {
+ 				  "ppmmu1";
+ 		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+ 		clock-names = "bus", "core";
++		operating-points-v2 = <&gpu_opp_table>;
++		power-domains = <&power RK3328_PD_GPU>;
+ 		resets = <&cru SRST_GPU_A>;
++		#cooling-cells = <2>;
++	};
++
++	gpu_opp_table: gpu-opp-table {
++		compatible = "operating-points-v2";
++
++		opp-200000000 {
++			opp-hz = /bits/ 64 <200000000>;
++			opp-microvolt = <1075000>;
++		};
++		opp-300000000 {
++			opp-hz = /bits/ 64 <300000000>;
++			opp-microvolt = <1075000>;
++		};
++		opp-400000000 {
++			opp-hz = /bits/ 64 <400000000>;
++			opp-microvolt = <1075000>;
++		};
++		opp-500000000 {
++			opp-hz = /bits/ 64 <500000000>;
++			opp-microvolt = <1150000>;
++			status = "disabled";
++		};
+ 	};
+ 
+ 	h265e_mmu: iommu@ff330200 {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Tue, 2 Feb 2021 17:22:21 +0200
+Subject: [PATCH] ARM: dts: RK3288 miqi add hdmi sound nodes
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+index 713f55e143c6..8d30c49f406e 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
++++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+@@ -78,6 +78,21 @@ vcc_sys: vsys-regulator {
+ 		regulator-always-on;
+ 		regulator-boot-on;
+ 	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "HDMI";
++		simple-audio-card,mclk-fs = <512>;
++
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s>;
++		};
++	};
+ };
+ 
+ &cpu0 {
+@@ -284,6 +299,11 @@ &i2c5 {
+ 	status = "okay";
+ };
+ 
++&i2s {
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
+ &io_domains {
+ 	status = "okay";
+ 
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Fri, 2 Apr 2021 17:54:22 +0200
+Subject: [PATCH] ARM/arm64: dts: rockchip: align sound card names
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi     | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+index 09618bb7d872..db9106a3dd22 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+@@ -73,7 +73,7 @@ sdio_pwrseq: sdio-pwrseq {
+ 	sound {
+ 		compatible = "simple-audio-card";
+ 		simple-audio-card,format = "i2s";
+-		simple-audio-card,name = "rockchip,tinker-codec";
++		simple-audio-card,name = "HDMI";
+ 		simple-audio-card,mclk-fs = <512>;
+ 
+ 		simple-audio-card,codec {
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 093ebe070775..a10fe60b7680 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -1893,7 +1893,7 @@ hdmi_sound: hdmi-sound {
+ 		compatible = "simple-audio-card";
+ 		simple-audio-card,format = "i2s";
+ 		simple-audio-card,mclk-fs = <256>;
+-		simple-audio-card,name = "hdmi-sound";
++		simple-audio-card,name = "HDMI";
+ 		status = "disabled";
+ 
+ 		simple-audio-card,cpu {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 25 Mar 2018 22:17:06 +0200
+Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation
+
+---
+ sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------
+ 1 file changed, 52 insertions(+), 61 deletions(-)
+
+diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c
+index 5679102de91f..f0cd183f7873 100644
+--- a/sound/soc/codecs/hdmi-codec.c
++++ b/sound/soc/codecs/hdmi-codec.c
+@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = {
+  */
+ static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
+ 	{ .ca_id = 0x00, .n_ch = 2,
+-	  .mask = FL | FR},
+-	/* 2.1 */
+-	{ .ca_id = 0x01, .n_ch = 4,
+-	  .mask = FL | FR | LFE},
+-	/* Dolby Surround */
++	  .mask = FL | FR },
++	{ .ca_id = 0x03, .n_ch = 4,
++	  .mask = FL | FR | LFE | FC },
+ 	{ .ca_id = 0x02, .n_ch = 4,
+ 	  .mask = FL | FR | FC },
+-	/* surround51 */
++	{ .ca_id = 0x01, .n_ch = 4,
++	  .mask = FL | FR | LFE },
+ 	{ .ca_id = 0x0b, .n_ch = 6,
+-	  .mask = FL | FR | LFE | FC | RL | RR},
+-	/* surround40 */
+-	{ .ca_id = 0x08, .n_ch = 6,
+-	  .mask = FL | FR | RL | RR },
+-	/* surround41 */
+-	{ .ca_id = 0x09, .n_ch = 6,
+-	  .mask = FL | FR | LFE | RL | RR },
+-	/* surround50 */
++	  .mask = FL | FR | LFE | FC | RL | RR },
+ 	{ .ca_id = 0x0a, .n_ch = 6,
+ 	  .mask = FL | FR | FC | RL | RR },
+-	/* 6.1 */
+-	{ .ca_id = 0x0f, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RL | RR | RC },
+-	/* surround71 */
++	{ .ca_id = 0x09, .n_ch = 6,
++	  .mask = FL | FR | LFE | RL | RR },
++	{ .ca_id = 0x08, .n_ch = 6,
++	  .mask = FL | FR | RL | RR },
++	{ .ca_id = 0x07, .n_ch = 6,
++	  .mask = FL | FR | LFE | FC | RC },
++	{ .ca_id = 0x06, .n_ch = 6,
++	  .mask = FL | FR | FC | RC },
++	{ .ca_id = 0x05, .n_ch = 6,
++	  .mask = FL | FR | LFE | RC },
++	{ .ca_id = 0x04, .n_ch = 6,
++	  .mask = FL | FR | RC },
+ 	{ .ca_id = 0x13, .n_ch = 8,
+ 	  .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
+-	/* others */
+-	{ .ca_id = 0x03, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC },
+-	{ .ca_id = 0x04, .n_ch = 8,
+-	  .mask = FL | FR | RC},
+-	{ .ca_id = 0x05, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC },
+-	{ .ca_id = 0x06, .n_ch = 8,
+-	  .mask = FL | FR | FC | RC },
+-	{ .ca_id = 0x07, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RC },
+-	{ .ca_id = 0x0c, .n_ch = 8,
+-	  .mask = FL | FR | RC | RL | RR },
+-	{ .ca_id = 0x0d, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | RC },
+-	{ .ca_id = 0x0e, .n_ch = 8,
+-	  .mask = FL | FR | FC | RL | RR | RC },
+-	{ .ca_id = 0x10, .n_ch = 8,
+-	  .mask = FL | FR | RL | RR | RLC | RRC },
+-	{ .ca_id = 0x11, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1f, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
+ 	{ .ca_id = 0x12, .n_ch = 8,
+ 	  .mask = FL | FR | FC | RL | RR | RLC | RRC },
+-	{ .ca_id = 0x14, .n_ch = 8,
+-	  .mask = FL | FR | FLC | FRC },
+-	{ .ca_id = 0x15, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FLC | FRC },
+-	{ .ca_id = 0x16, .n_ch = 8,
+-	  .mask = FL | FR | FC | FLC | FRC },
+-	{ .ca_id = 0x17, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | FLC | FRC },
+-	{ .ca_id = 0x18, .n_ch = 8,
+-	  .mask = FL | FR | RC | FLC | FRC },
+-	{ .ca_id = 0x19, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC | FLC | FRC },
+-	{ .ca_id = 0x1a, .n_ch = 8,
+-	  .mask = FL | FR | RC | FC | FLC | FRC },
+-	{ .ca_id = 0x1b, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC | FC | FLC | FRC },
+-	{ .ca_id = 0x1c, .n_ch = 8,
+-	  .mask = FL | FR | RL | RR | FLC | FRC },
+-	{ .ca_id = 0x1d, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | FLC | FRC },
+ 	{ .ca_id = 0x1e, .n_ch = 8,
+ 	  .mask = FL | FR | FC | RL | RR | FLC | FRC },
+-	{ .ca_id = 0x1f, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
++	{ .ca_id = 0x11, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1d, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | FLC | FRC },
++	{ .ca_id = 0x10, .n_ch = 8,
++	  .mask = FL | FR | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1c, .n_ch = 8,
++	  .mask = FL | FR | RL | RR | FLC | FRC },
++	{ .ca_id = 0x0f, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | RL | RR | RC },
++	{ .ca_id = 0x1b, .n_ch = 8,
++	  .mask = FL | FR | LFE | RC | FC | FLC | FRC },
++	{ .ca_id = 0x0e, .n_ch = 8,
++	  .mask = FL | FR | FC | RL | RR | RC },
++	{ .ca_id = 0x1a, .n_ch = 8,
++	  .mask = FL | FR | RC | FC | FLC | FRC },
++	{ .ca_id = 0x0d, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | RC },
++	{ .ca_id = 0x19, .n_ch = 8,
++	  .mask = FL | FR | LFE | RC | FLC | FRC },
++	{ .ca_id = 0x0c, .n_ch = 8,
++	  .mask = FL | FR | RC | RL | RR },
++	{ .ca_id = 0x18, .n_ch = 8,
++	  .mask = FL | FR | RC | FLC | FRC },
++	{ .ca_id = 0x17, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | FLC | FRC },
++	{ .ca_id = 0x16, .n_ch = 8,
++	  .mask = FL | FR | FC | FLC | FRC },
++	{ .ca_id = 0x15, .n_ch = 8,
++	  .mask = FL | FR | LFE | FLC | FRC },
++	{ .ca_id = 0x14, .n_ch = 8,
++	  .mask = FL | FR | FLC | FRC },
+ };
+ 
+ struct hdmi_codec_priv {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 27 Feb 2021 17:52:02 +0100
+Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1 board
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+index 40bf808642b9..27a1799027c2 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+@@ -57,6 +57,24 @@ ir-receiver {
+ 		gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ 		linux,rc-map-name = "rc-beelink-gs1";
+ 	};
++
++	spdif_sound: spdif-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "SPDIF";
++
++		simple-audio-card,cpu {
++			sound-dai = <&spdif>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&spdif_dit>;
++		};
++	};
++
++	spdif_dit: spdif-dit {
++		compatible = "linux,spdif-dit";
++		#sound-dai-cells = <0>;
++	};
+ };
+ 
+ &analog_sound {
+@@ -325,6 +343,11 @@ &sdmmc {
+ 	status = "okay";
+ };
+ 
++&spdif {
++	pinctrl-0 = <&spdifm0_tx>;
++	status = "okay";
++};
++
+ &tsadc {
+ 	rockchip,hw-tshut-mode = <0>;
+ 	rockchip,hw-tshut-polarity = <0>;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 27 Feb 2021 18:01:13 +0100
+Subject: [PATCH] arm64: dts: rockchip: Add ir-receiver node for RK3328 ROC CC
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+index 51c7723d6762..cf321302daec 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator {
+ 		regulator-boot-on;
+ 	};
+ 
++	ir-receiver {
++		compatible = "gpio-ir-receiver";
++		gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
++		pinctrl-0 = <&ir_int>;
++		pinctrl-names = "default";
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -312,6 +319,13 @@ &io_domains {
+ };
+ 
+ &pinctrl {
++
++	ir {
++		ir_int: ir-int {
++			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		pmic_int_l: pmic-int-l {
+ 			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Mon, 1 Mar 2021 21:24:15 +0100
+Subject: [PATCH] ARM: dts: add cec pinctrl for RK3288 miqi board
+
+---
+ arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+index 8d30c49f406e..6d90db5a3b75 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
++++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+@@ -145,6 +145,8 @@ &gpu {
+ 
+ &hdmi {
+ 	ddc-i2c-bus = <&i2c5>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&hdmi_cec_c0>;
+ 	status = "okay";
+ };
+ 
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Mon, 1 Mar 2021 19:22:15 +0100
+Subject: [PATCH] HACK: arm64: dts: enable FE phy for Beelink A1 also
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+index 27a1799027c2..7de9dfa71d89 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+@@ -147,6 +147,14 @@ rtl8211f: ethernet-phy@0 {
+ 	};
+ };
+ 
++&gmac2phy {
++	clock_in_out = "output";
++	assigned-clock-rate = <50000000>;
++	assigned-clocks = <&cru SCLK_MAC2PHY>;
++	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
++	status = "okay";
++};
++
+ &gpu {
+ 	mali-supply = <&vdd_logic>;
+ };
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 26 Feb 2019 20:45:14 +0000
+Subject: [PATCH] WIP: dw-hdmi-cec: sleep 100ms on error
+
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++--
+ 1 file changed, 16 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
+index c8f44bcb298a..d4280ce4542c 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
+@@ -4,6 +4,7 @@
+  *
+  * Copyright (C) 2015-2017 Russell King.
+  */
++#include <linux/delay.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+@@ -129,8 +130,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data)
+ 
+ 	dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0);
+ 
+-	if (stat & CEC_STAT_ERROR_INIT) {
+-		cec->tx_status = CEC_TX_STATUS_ERROR;
++	/* Status with both done and error_initiator bits have been seen
++	 * on Rockchip RK3328 devices, transmit attempt seems to have failed
++	 * when this happens, report as low drive and block cec-framework
++	 * 100ms before core retransmits the failed message, this seems to
++	 * mitigate the issue with failed transmit attempts.
++	 */
++	if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) {
++		pr_debug("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat);
++		cec->tx_status = CEC_TX_STATUS_LOW_DRIVE;
+ 		cec->tx_done = true;
+ 		ret = IRQ_WAKE_THREAD;
+ 	} else if (stat & CEC_STAT_DONE) {
+@@ -141,6 +149,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data)
+ 		cec->tx_status = CEC_TX_STATUS_NACK;
+ 		cec->tx_done = true;
+ 		ret = IRQ_WAKE_THREAD;
++	} else if (stat & CEC_STAT_ERROR_INIT) {
++		cec->tx_status = CEC_TX_STATUS_ERROR;
++		cec->tx_done = true;
++		ret = IRQ_WAKE_THREAD;
+ 	}
+ 
+ 	if (stat & CEC_STAT_EOM) {
+@@ -173,6 +185,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data)
+ 
+ 	if (cec->tx_done) {
+ 		cec->tx_done = false;
++		if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE)
++			msleep(100);
+ 		cec_transmit_attempt_done(adap, cec->tx_status);
+ 	}
+ 	if (cec->rx_done) {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Wed, 5 May 2021 19:11:12 +0200
+Subject: [PATCH] arm64: boot: dts: Increase ACLK_PERILP0 clock rate for RK3399
+
+As per vendor kernel. Leaving this clock at the lower rate will
+result in poor DMA controller performance
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index a10fe60b7680..dbe6a9cb98a5 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -1477,7 +1477,7 @@ cru: clock-controller@ff760000 {
+ 			<1000000000>,
+ 			 <150000000>,   <75000000>,
+ 			  <37500000>,
+-			 <100000000>,  <100000000>,
++			 <300000000>,  <100000000>,
+ 			  <50000000>, <600000000>,
+ 			 <100000000>,   <50000000>,
+ 			 <400000000>, <400000000>,
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 21 Aug 2021 17:04:46 +0200
+Subject: [PATCH] arm64: dts: rockchip: Enable USB3 for rk3328 Beelink A1
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+index 7de9dfa71d89..e857e5a727f4 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+@@ -389,6 +389,11 @@ &usb_host0_ehci {
+ 	status = "okay";
+ };
+ 
++&usbdrd3 {
++	dr_mode = "host";
++	status = "okay";
++};
++
+ &vop {
+ 	status = "okay";
+ };
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 30 Oct 2021 12:19:19 +0200
+Subject: [PATCH] WIP: drm: bridge: dw-hdmi: switch from .hw_parmas to .prepare
+ for i2s
+
+Seems to be the only way to get AES bits correctly as set by
+userspace.
+TODO: check other consequences.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
+index a2f0860b20bb..8961f9c7885d 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
+@@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset)
+ 	return audio->read(hdmi, offset);
+ }
+ 
+-static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
+-				 struct hdmi_codec_daifmt *fmt,
+-				 struct hdmi_codec_params *hparms)
++static int dw_hdmi_i2s_prepare(struct device *dev, void *data,
++			       struct hdmi_codec_daifmt *fmt,
++			       struct hdmi_codec_params *hparms)
+ {
+ 	struct dw_hdmi_i2s_audio_data *audio = data;
+ 	struct dw_hdmi *hdmi = audio->hdmi;
+@@ -178,7 +178,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(struct device *dev, void *data,
+ }
+ 
+ static const struct hdmi_codec_ops dw_hdmi_i2s_ops = {
+-	.hw_params	= dw_hdmi_i2s_hw_params,
++	.prepare	= dw_hdmi_i2s_prepare,
+ 	.audio_startup  = dw_hdmi_i2s_audio_startup,
+ 	.audio_shutdown	= dw_hdmi_i2s_audio_shutdown,
+ 	.get_eld	= dw_hdmi_i2s_get_eld,
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 18 Sep 2022 10:35:52 +0200
+Subject: [PATCH] arm64: dts: rockchip: Disbake fusb for rk3399-roc-pc
+
+As it will lead to an unbootable device in case one if those ports
+is used to power up the device.
+See https://lkml.org/lkml/2022/6/20/413
+---
+ arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+index 2f4b1b2e3ac7..7217ead94d39 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+@@ -215,7 +215,7 @@ vdd_log: vdd-log {
+ 		regulator-name = "vdd_log";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		regulator-min-microvolt = <450000>;
++		regulator-min-microvolt = <430000>;
+ 		regulator-max-microvolt = <1400000>;
+ 		pwm-supply = <&vcc3v3_sys>;
+ 	};
+@@ -536,7 +536,7 @@ fusb1: usb-typec@22 {
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&fusb1_int>;
+ 		vbus-supply = <&vcc_vbus_typec1>;
+-		status = "okay";
++		status = "disabled";
+ 	};
+ };
+ 
+@@ -553,7 +553,7 @@ fusb0: usb-typec@22 {
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&fusb0_int>;
+ 		vbus-supply = <&vcc_vbus_typec0>;
+-		status = "okay";
++		status = "disabled";
+ 	};
+ 
+ 	mp8859: regulator@66 {
diff --git a/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch
new file mode 100644
index 000000000000..649732ddbedd
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch
@@ -0,0 +1,63 @@
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 0370bb247fcb..55c0b8dddad5 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c	2023-06-25 03:23:55.724209412 +0000
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c	2023-06-25 04:16:27.469899470 +0000
+@@ -254,35 +245,31 @@
+ 			    const struct drm_display_info *info,
+ 			    const struct drm_display_mode *mode)
+ {
+-	struct rockchip_hdmi *hdmi = data;
+-	const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
+-	int pclk = mode->clock * 1000;
+-	bool exact_match = hdmi->plat_data->phy_force_vendor;
+-	int i;
+-
+-	if (hdmi->ref_clk) {
+-		int rpclk = clk_round_rate(hdmi->ref_clk, pclk);
+-
+-		if (abs(rpclk - pclk) > pclk / 1000)
+-			return MODE_NOCLOCK;
+-	}
+-
+-	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
+-		/*
+-		 * For vendor specific phys force an exact match of the pixelclock
+-		 * to preserve the original behaviour of the driver.
+-		 */
+-		if (exact_match && pclk == mpll_cfg[i].mpixelclock)
+-			return MODE_OK;
+-		/*
+-		 * The Synopsys phy can work with pixelclocks up to the value given
+-		 * in the corresponding mpll_cfg entry.
+-		 */
+-		if (!exact_match && pclk <= mpll_cfg[i].mpixelclock)
+-			return MODE_OK;
++	struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data;
++	const struct dw_hdmi_mpll_config *mpll_cfg = pdata->mpll_cfg;
++	int clock = mode->clock;
++	unsigned int i = 0;
++
++	if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
++	    (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) {
++		clock /= 2;
++		mpll_cfg = pdata->mpll_cfg_420;
++	}
++
++	if ((!mpll_cfg && clock > 340000) ||
++	    (info->max_tmds_clock && clock > info->max_tmds_clock))
++		return MODE_CLOCK_HIGH;
++
++	if (mpll_cfg) {
++		while ((clock * 1000) < mpll_cfg[i].mpixelclock &&
++		       mpll_cfg[i].mpixelclock != (~0UL))
++		       i++;
++
++		if (mpll_cfg[i].mpixelclock == (~0UL))
++			return MODE_CLOCK_HIGH;
+ 	}
+ 
+-	return MODE_BAD;
++	return MODE_OK;
+ }
+ 
+ static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
diff --git a/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch
new file mode 100644
index 000000000000..58b3e72e5a27
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch
@@ -0,0 +1,3226 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 23 May 2020 15:17:45 +0000
+Subject: [PATCH] WIP: media: rkvdec: add HEVC backend
+
+NOTE: cabac table and scailing list code is copied 1:1 from mpp
+TODO: fix lowdelay flag and rework the scaling list part
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/staging/media/rkvdec/Makefile      |    2 +-
+ drivers/staging/media/rkvdec/rkvdec-hevc.c | 2572 ++++++++++++++++++++
+ drivers/staging/media/rkvdec/rkvdec-regs.h |    1 +
+ drivers/staging/media/rkvdec/rkvdec.c      |   73 +-
+ drivers/staging/media/rkvdec/rkvdec.h      |    1 +
+ 5 files changed, 2647 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
+
+diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
+index cb86b429cfaa..a77122641d14 100644
+--- a/drivers/staging/media/rkvdec/Makefile
++++ b/drivers/staging/media/rkvdec/Makefile
+@@ -1,3 +1,3 @@
+ obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o
+ 
+-rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
++rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
+diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+new file mode 100644
+index 000000000000..7a375a23eaf1
+--- /dev/null
++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+@@ -0,0 +1,2572 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Rockchip Video Decoder HEVC backend
++ *
++ * Copyright (C) 2019 Collabora, Ltd.
++ *	Boris Brezillon <boris.brezillon@collabora.com>
++ *
++ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
++ *	Jeffy Chen <jeffy.chen@rock-chips.com>
++ */
++
++#include <media/v4l2-mem2mem.h>
++
++#include "rkvdec.h"
++#include "rkvdec-regs.h"
++
++/* Size in u8/u32 units. */
++#define RKV_CABAC_TABLE_SIZE		27456
++#define RKV_SCALING_LIST_SIZE		1360
++#define RKV_PPS_SIZE			(80 / 4)
++#define RKV_PPS_LEN			64
++#define RKV_RPS_SIZE			(32 / 4)
++#define RKV_RPS_LEN			600
++
++struct rkvdec_sps_pps_packet {
++	u32 info[RKV_PPS_SIZE];
++};
++
++struct rkvdec_rps_packet {
++	u32 info[RKV_RPS_SIZE];
++};
++
++struct rkvdec_ps_field {
++	u16 offset;
++	u8 len;
++};
++
++#define PS_FIELD(_offset, _len) \
++	((struct rkvdec_ps_field){ _offset, _len })
++
++/* SPS */
++#define VIDEO_PARAMETER_SET_ID				PS_FIELD(0, 4)
++#define SEQ_PARAMETER_SET_ID				PS_FIELD(4, 4)
++#define CHROMA_FORMAT_IDC				PS_FIELD(8, 2)
++#define PIC_WIDTH_IN_LUMA_SAMPLES			PS_FIELD(10, 13)
++#define PIC_HEIGHT_IN_LUMA_SAMPLES			PS_FIELD(23, 13)
++#define BIT_DEPTH_LUMA					PS_FIELD(36, 4)
++#define BIT_DEPTH_CHROMA				PS_FIELD(40, 4)
++#define LOG2_MAX_PIC_ORDER_CNT_LSB			PS_FIELD(44, 5)
++#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE	PS_FIELD(49, 2)
++#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE			PS_FIELD(51, 3)
++#define LOG2_MIN_TRANSFORM_BLOCK_SIZE			PS_FIELD(54, 3)
++#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE	PS_FIELD(57, 2)
++#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER		PS_FIELD(59, 3)
++#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA		PS_FIELD(62, 3)
++#define SCALING_LIST_ENABLED_FLAG			PS_FIELD(65, 1)
++#define AMP_ENABLED_FLAG				PS_FIELD(66, 1)
++#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG		PS_FIELD(67, 1)
++#define PCM_ENABLED_FLAG				PS_FIELD(68, 1)
++#define PCM_SAMPLE_BIT_DEPTH_LUMA			PS_FIELD(69, 4)
++#define PCM_SAMPLE_BIT_DEPTH_CHROMA			PS_FIELD(73, 4)
++#define PCM_LOOP_FILTER_DISABLED_FLAG			PS_FIELD(77, 1)
++#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE	PS_FIELD(78, 3)
++#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE		PS_FIELD(81, 3)
++#define NUM_SHORT_TERM_REF_PIC_SETS			PS_FIELD(84, 7)
++#define LONG_TERM_REF_PICS_PRESENT_FLAG			PS_FIELD(91, 1)
++#define NUM_LONG_TERM_REF_PICS_SPS			PS_FIELD(92, 6)
++#define SPS_TEMPORAL_MVP_ENABLED_FLAG			PS_FIELD(98, 1)
++#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG		PS_FIELD(99, 1)
++/* PPS */
++#define PIC_PARAMETER_SET_ID				PS_FIELD(128, 6)
++#define PPS_SEQ_PARAMETER_SET_ID			PS_FIELD(134, 4)
++#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG		PS_FIELD(138, 1)
++#define OUTPUT_FLAG_PRESENT_FLAG			PS_FIELD(139, 1)
++#define NUM_EXTRA_SLICE_HEADER_BITS			PS_FIELD(140, 13)
++#define SIGN_DATA_HIDING_ENABLED_FLAG			PS_FIELD(153, 1)
++#define CABAC_INIT_PRESENT_FLAG				PS_FIELD(154, 1)
++#define NUM_REF_IDX_L0_DEFAULT_ACTIVE			PS_FIELD(155, 4)
++#define NUM_REF_IDX_L1_DEFAULT_ACTIVE			PS_FIELD(159, 4)
++#define INIT_QP_MINUS26					PS_FIELD(163, 7)
++#define CONSTRAINED_INTRA_PRED_FLAG			PS_FIELD(170, 1)
++#define TRANSFORM_SKIP_ENABLED_FLAG			PS_FIELD(171, 1)
++#define CU_QP_DELTA_ENABLED_FLAG			PS_FIELD(172, 1)
++#define LOG2_MIN_CU_QP_DELTA_SIZE			PS_FIELD(173, 3)
++#define PPS_CB_QP_OFFSET				PS_FIELD(176, 5)
++#define PPS_CR_QP_OFFSET				PS_FIELD(181, 5)
++#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG	PS_FIELD(186, 1)
++#define WEIGHTED_PRED_FLAG				PS_FIELD(187, 1)
++#define WEIGHTED_BIPRED_FLAG				PS_FIELD(188, 1)
++#define TRANSQUANT_BYPASS_ENABLED_FLAG			PS_FIELD(189, 1)
++#define TILES_ENABLED_FLAG				PS_FIELD(190, 1)
++#define ENTROPY_CODING_SYNC_ENABLED_FLAG		PS_FIELD(191, 1)
++#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG	PS_FIELD(192, 1)
++#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG		PS_FIELD(193, 1)
++#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG		PS_FIELD(194, 1)
++#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG		PS_FIELD(195, 1)
++#define PPS_BETA_OFFSET_DIV2				PS_FIELD(196, 4)
++#define PPS_TC_OFFSET_DIV2				PS_FIELD(200, 4)
++#define LISTS_MODIFICATION_PRESENT_FLAG			PS_FIELD(204, 1)
++#define LOG2_PARALLEL_MERGE_LEVEL			PS_FIELD(205, 3)
++#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG	PS_FIELD(208, 1)
++#define NUM_TILE_COLUMNS				PS_FIELD(212, 5)
++#define NUM_TILE_ROWS					PS_FIELD(217, 5)
++#define COLUMN_WIDTH(i)					PS_FIELD(256 + (i * 8), 8)
++#define ROW_HEIGHT(i)					PS_FIELD(416 + (i * 8), 8)
++#define SCALING_LIST_ADDRESS				PS_FIELD(592, 32)
++
++/* Data structure describing auxiliary buffer format. */
++struct rkvdec_hevc_priv_tbl {
++	u8 cabac_table[RKV_CABAC_TABLE_SIZE];
++	u8 scaling_list[RKV_SCALING_LIST_SIZE];
++	struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
++	struct rkvdec_rps_packet rps[RKV_RPS_LEN];
++};
++
++struct rkvdec_hevc_run {
++	struct rkvdec_run base;
++	const struct v4l2_ctrl_hevc_slice_params *slices_params;
++	const struct v4l2_ctrl_hevc_decode_params *decode_params;
++	const struct v4l2_ctrl_hevc_sps *sps;
++	const struct v4l2_ctrl_hevc_pps *pps;
++	const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
++	int num_slices;
++};
++
++struct rkvdec_hevc_ctx {
++	struct rkvdec_aux_buf priv_tbl;
++	struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
++};
++
++// TODO: refactor scaling list code, was copied 1:1 from mpp
++
++typedef struct ScalingList {
++    /* This is a little wasteful, since sizeID 0 only needs 8 coeffs,
++     * and size ID 3 only has 2 arrays, not 6. */
++    u8 sl[4][6][64];
++    u8 sl_dc[2][6];
++} scalingList_t;
++
++typedef struct ScalingFactor_Model {
++    u8 scalingfactor0[1248];
++    u8 scalingfactor1[96];     /*4X4 TU Rotate, total 16X4*/
++    u8 scalingdc[12];          /*N1005 Vienna Meeting*/
++    u8 reserverd[4];           /*16Bytes align*/
++} scalingFactor_t;
++
++#define SCALING_LIST_SIZE_NUM 4
++
++static void
++hal_record_scaling_list(scalingFactor_t *pScalingFactor_out,
++                        scalingList_t *pScalingList)
++{
++    int i;
++    u32 g_scalingListNum_model[SCALING_LIST_SIZE_NUM] = {6, 6, 6, 2}; // from C Model
++    u32 nIndex = 0;
++    u32 sizeId, matrixId, listId;
++    u8 *p = pScalingFactor_out->scalingfactor0;
++    u8 tmpBuf[8 * 8];
++
++    //output non-default scalingFactor Table (1248 BYTES)
++    for (sizeId = 0; sizeId < SCALING_LIST_SIZE_NUM; sizeId++) {
++        for (listId = 0; listId < g_scalingListNum_model[sizeId]; listId++) {
++            if (sizeId < 3) {
++                for (i = 0; i < (sizeId == 0 ? 16 : 64); i++) {
++                    pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i];
++                }
++            } else {
++                for (i = 0; i < 64; i ++) {
++                    pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i];
++                }
++                for (i = 0; i < 128; i ++) {
++                    pScalingFactor_out->scalingfactor0[nIndex++] = 0;
++                }
++            }
++        }
++    }
++    //output non-default scalingFactor Table Rotation(96 Bytes)
++    nIndex = 0;
++    for (listId = 0; listId < g_scalingListNum_model[0]; listId++) {
++        u8 temp16[16] = {0};
++        for (i = 0; i < 16; i ++) {
++            temp16[i] = (u8)pScalingList->sl[0][listId][i];
++        }
++        for (i = 0; i < 4; i ++) {
++            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i];
++            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 4];
++            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 8];
++            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 12];
++        }
++    }
++    //output non-default ScalingList_DC_Coeff (12 BYTES)
++    nIndex = 0;
++    for (listId = 0; listId < g_scalingListNum_model[2]; listId++) { //sizeId = 2
++        pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[0][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC
++    }
++    for (listId = 0; listId < g_scalingListNum_model[3]; listId++) { //sizeId = 3
++        pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[1][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC
++        pScalingFactor_out->scalingdc[nIndex++] = 0;
++        pScalingFactor_out->scalingdc[nIndex++] = 0;
++    }
++
++    //align 16X address
++    nIndex = 0;
++    for (i = 0; i < 4; i ++) {
++        pScalingFactor_out->reserverd[nIndex++] = 0;
++    }
++
++    //----------------------All above code show the normal store way in HM--------------------------
++    //--------from now on, the scalingfactor0 is rotated 90', the scalingfactor1 is also rotated 90'
++
++    //sizeId == 0
++    for (matrixId = 0; matrixId < 6; matrixId++) {
++        p = pScalingFactor_out->scalingfactor0 + matrixId * 16;
++
++        for (i = 0; i < 4; i++) {
++            tmpBuf[4 * 0 + i] = p[i * 4 + 0];
++            tmpBuf[4 * 1 + i] = p[i * 4 + 1];
++            tmpBuf[4 * 2 + i] = p[i * 4 + 2];
++            tmpBuf[4 * 3 + i] = p[i * 4 + 3];
++        }
++        memcpy(p, tmpBuf, 4 * 4 * sizeof(u8));
++    }
++    //sizeId == 1
++    for (matrixId = 0; matrixId < 6; matrixId++) {
++        p = pScalingFactor_out->scalingfactor0 + 6 * 16 + matrixId * 64;
++
++        for (i = 0; i < 8; i++) {
++            tmpBuf[8 * 0 + i] = p[i * 8 + 0];
++            tmpBuf[8 * 1 + i] = p[i * 8 + 1];
++            tmpBuf[8 * 2 + i] = p[i * 8 + 2];
++            tmpBuf[8 * 3 + i] = p[i * 8 + 3];
++            tmpBuf[8 * 4 + i] = p[i * 8 + 4];
++            tmpBuf[8 * 5 + i] = p[i * 8 + 5];
++            tmpBuf[8 * 6 + i] = p[i * 8 + 6];
++            tmpBuf[8 * 7 + i] = p[i * 8 + 7];
++        }
++        memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
++    }
++    //sizeId == 2
++    for (matrixId = 0; matrixId < 6; matrixId++) {
++        p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + matrixId * 64;
++
++        for (i = 0; i < 8; i++) {
++            tmpBuf[8 * 0 + i] = p[i * 8 + 0];
++            tmpBuf[8 * 1 + i] = p[i * 8 + 1];
++            tmpBuf[8 * 2 + i] = p[i * 8 + 2];
++            tmpBuf[8 * 3 + i] = p[i * 8 + 3];
++            tmpBuf[8 * 4 + i] = p[i * 8 + 4];
++            tmpBuf[8 * 5 + i] = p[i * 8 + 5];
++            tmpBuf[8 * 6 + i] = p[i * 8 + 6];
++            tmpBuf[8 * 7 + i] = p[i * 8 + 7];
++        }
++        memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
++    }
++    //sizeId == 3
++    for (matrixId = 0; matrixId < 6; matrixId++) {
++        p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + 6 * 64 + matrixId * 64;
++
++        for (i = 0; i < 8; i++) {
++            tmpBuf[8 * 0 + i] = p[i * 8 + 0];
++            tmpBuf[8 * 1 + i] = p[i * 8 + 1];
++            tmpBuf[8 * 2 + i] = p[i * 8 + 2];
++            tmpBuf[8 * 3 + i] = p[i * 8 + 3];
++            tmpBuf[8 * 4 + i] = p[i * 8 + 4];
++            tmpBuf[8 * 5 + i] = p[i * 8 + 5];
++            tmpBuf[8 * 6 + i] = p[i * 8 + 6];
++            tmpBuf[8 * 7 + i] = p[i * 8 + 7];
++        }
++        memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
++    }
++
++    //sizeId == 0
++    for (matrixId = 0; matrixId < 6; matrixId++) {
++        p = pScalingFactor_out->scalingfactor1 + matrixId * 16;
++
++        for (i = 0; i < 4; i++) {
++            tmpBuf[4 * 0 + i] = p[i * 4 + 0];
++            tmpBuf[4 * 1 + i] = p[i * 4 + 1];
++            tmpBuf[4 * 2 + i] = p[i * 4 + 2];
++            tmpBuf[4 * 3 + i] = p[i * 4 + 3];
++        }
++        memcpy(p, tmpBuf, 4 * 4 * sizeof(u8));
++    }
++}
++
++static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = {
++    0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x68,
++    0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x68,
++    0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, 0x60, 0x50, 0x58,
++    0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, 0x60, 0x60,
++    0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68,
++    0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, 0x50, 0x50, 0x50, 0x48, 0x58, 0x58,
++    0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50,
++    0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40,
++    0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f,
++    0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0f, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66,
++    0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67,
++    0x57, 0x5e, 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57,
++    0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f,
++    0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66,
++    0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, 0x57, 0x57,
++    0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x4f,
++    0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, 0x47, 0x67, 0x40, 0x40,
++    0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, 0x4e, 0x47, 0x47, 0x00, 0x0f,
++    0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64,
++    0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66,
++    0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56,
++    0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e,
++    0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64,
++    0x45, 0x48, 0x20, 0x57, 0x66, 0x66, 0x56, 0x5e, 0x5e, 0x5d, 0x4e, 0x4e, 0x4e, 0x46, 0x56, 0x57,
++    0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f,
++    0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x66, 0x10, 0x47, 0x66, 0x40, 0x40,
++    0x4f, 0x4d, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x03, 0x27, 0x4d, 0x47, 0x46, 0x01, 0x0f,
++    0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x34, 0x01, 0x26, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0d, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x62,
++    0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x65,
++    0x57, 0x5c, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5d, 0x5d, 0x4e, 0x56,
++    0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62, 0x5d, 0x5d,
++    0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62,
++    0x44, 0x48, 0x20, 0x57, 0x65, 0x65, 0x56, 0x5d, 0x5d, 0x5c, 0x4e, 0x4d, 0x4e, 0x45, 0x56, 0x57,
++    0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f,
++    0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x65, 0x10, 0x47, 0x65, 0x40, 0x40,
++    0x4f, 0x4c, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x04, 0x27, 0x4c, 0x47, 0x45, 0x01, 0x0f,
++    0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x33, 0x01, 0x25, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0c, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0d, 0x40, 0x40, 0x40, 0x0d, 0x60,
++    0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x64,
++    0x56, 0x5b, 0x01, 0x1d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5c, 0x5c, 0x4d, 0x55,
++    0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60, 0x5c, 0x5c,
++    0x4d, 0x55, 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60,
++    0x43, 0x49, 0x21, 0x56, 0x64, 0x64, 0x55, 0x5c, 0x5c, 0x5b, 0x4d, 0x4c, 0x4d, 0x44, 0x55, 0x56,
++    0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x4e,
++    0x46, 0x1d, 0x1d, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x64, 0x11, 0x46, 0x64, 0x40, 0x40,
++    0x4e, 0x4b, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x06, 0x27, 0x4b, 0x46, 0x44, 0x02, 0x0f,
++    0x4e, 0x35, 0x1e, 0x1d, 0x4e, 0x31, 0x02, 0x24, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0b, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5e,
++    0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x63,
++    0x56, 0x59, 0x01, 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5b, 0x5b, 0x4c, 0x54,
++    0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e, 0x5b, 0x5b,
++    0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e,
++    0x41, 0x49, 0x21, 0x56, 0x63, 0x63, 0x54, 0x5b, 0x5b, 0x59, 0x4c, 0x4b, 0x4c, 0x43, 0x54, 0x56,
++    0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e,
++    0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x63, 0x11, 0x46, 0x63, 0x40, 0x40,
++    0x4e, 0x49, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x07, 0x27, 0x49, 0x46, 0x43, 0x03, 0x0f,
++    0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x30, 0x03, 0x23, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0a, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5c,
++    0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x62,
++    0x56, 0x58, 0x01, 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5a, 0x5a, 0x4c, 0x54,
++    0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c, 0x5a, 0x5a,
++    0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c,
++    0x40, 0x49, 0x21, 0x56, 0x62, 0x62, 0x54, 0x5a, 0x5a, 0x58, 0x4c, 0x4a, 0x4c, 0x42, 0x54, 0x56,
++    0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e,
++    0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x62, 0x11, 0x46, 0x62, 0x40, 0x40,
++    0x4e, 0x48, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x09, 0x27, 0x48, 0x46, 0x42, 0x03, 0x0f,
++    0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x2e, 0x03, 0x22, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x09, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0b, 0x40, 0x40, 0x40, 0x0b, 0x5a,
++    0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x61,
++    0x55, 0x57, 0x02, 0x1b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x59, 0x59, 0x4b, 0x53,
++    0x4d, 0x07, 0x53, 0x63, 0x4d, 0x51, 0x61, 0x65, 0x63, 0x61, 0x5d, 0x49, 0x43, 0x5a, 0x59, 0x59,
++    0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x51, 0x61, 0x65, 0x63, 0x61, 0x5d, 0x49, 0x43, 0x5a,
++    0x00, 0x4a, 0x22, 0x55, 0x61, 0x61, 0x53, 0x59, 0x59, 0x57, 0x4b, 0x49, 0x4b, 0x41, 0x53, 0x55,
++    0x33, 0x07, 0x53, 0x41, 0x53, 0x55, 0x33, 0x07, 0x53, 0x41, 0x53, 0x55, 0x33, 0x07, 0x53, 0x4d,
++    0x45, 0x1b, 0x1b, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x61, 0x12, 0x45, 0x61, 0x40, 0x40,
++    0x4d, 0x47, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0a, 0x27, 0x47, 0x45, 0x41, 0x04, 0x0f,
++    0x4d, 0x33, 0x1d, 0x1b, 0x4d, 0x2d, 0x04, 0x21, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x08, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, 0x40, 0x40, 0x40, 0x0a, 0x59,
++    0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x60,
++    0x55, 0x56, 0x02, 0x1a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x58, 0x58, 0x4b, 0x53,
++    0x4d, 0x07, 0x53, 0x63, 0x4d, 0x50, 0x60, 0x65, 0x63, 0x60, 0x5b, 0x48, 0x43, 0x59, 0x58, 0x58,
++    0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x50, 0x60, 0x65, 0x63, 0x60, 0x5b, 0x48, 0x43, 0x59,
++    0x01, 0x4a, 0x22, 0x55, 0x60, 0x60, 0x53, 0x58, 0x58, 0x56, 0x4b, 0x48, 0x4b, 0x40, 0x53, 0x55,
++    0x32, 0x07, 0x53, 0x40, 0x53, 0x55, 0x32, 0x07, 0x53, 0x40, 0x53, 0x55, 0x32, 0x07, 0x53, 0x4d,
++    0x45, 0x1a, 0x1a, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x60, 0x12, 0x45, 0x60, 0x40, 0x40,
++    0x4d, 0x46, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0c, 0x27, 0x46, 0x45, 0x40, 0x04, 0x0f,
++    0x4d, 0x32, 0x1d, 0x1a, 0x4d, 0x2b, 0x04, 0x20, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x07, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, 0x40, 0x40, 0x40, 0x0a, 0x57,
++    0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x5f,
++    0x55, 0x54, 0x02, 0x1a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x57, 0x57, 0x4a, 0x52,
++    0x4d, 0x07, 0x52, 0x62, 0x4d, 0x4f, 0x5f, 0x65, 0x62, 0x5f, 0x59, 0x47, 0x42, 0x57, 0x57, 0x57,
++    0x4a, 0x52, 0x4d, 0x07, 0x52, 0x62, 0x4d, 0x4f, 0x5f, 0x65, 0x62, 0x5f, 0x59, 0x47, 0x42, 0x57,
++    0x03, 0x4a, 0x22, 0x55, 0x5f, 0x5f, 0x52, 0x57, 0x57, 0x54, 0x4a, 0x47, 0x4a, 0x00, 0x52, 0x55,
++    0x32, 0x07, 0x52, 0x00, 0x52, 0x55, 0x32, 0x07, 0x52, 0x00, 0x52, 0x55, 0x32, 0x07, 0x52, 0x4d,
++    0x45, 0x1a, 0x1a, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x5f, 0x12, 0x45, 0x5f, 0x40, 0x40,
++    0x4d, 0x44, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0e, 0x27, 0x44, 0x45, 0x00, 0x05, 0x0f,
++    0x4d, 0x32, 0x1d, 0x1a, 0x4d, 0x29, 0x05, 0x1f, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x06, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x09, 0x40, 0x40, 0x40, 0x09, 0x55,
++    0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5e,
++    0x54, 0x53, 0x03, 0x19, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x56, 0x56, 0x49, 0x51,
++    0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4e, 0x5e, 0x64, 0x61, 0x5e, 0x58, 0x46, 0x41, 0x55, 0x56, 0x56,
++    0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4e, 0x5e, 0x64, 0x61, 0x5e, 0x58, 0x46, 0x41, 0x55,
++    0x04, 0x4b, 0x23, 0x54, 0x5e, 0x5e, 0x51, 0x56, 0x56, 0x53, 0x49, 0x46, 0x49, 0x01, 0x51, 0x54,
++    0x31, 0x07, 0x51, 0x01, 0x51, 0x54, 0x31, 0x07, 0x51, 0x01, 0x51, 0x54, 0x31, 0x07, 0x51, 0x4c,
++    0x44, 0x19, 0x19, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5e, 0x13, 0x44, 0x5e, 0x40, 0x40,
++    0x4c, 0x43, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x0f, 0x27, 0x43, 0x44, 0x01, 0x06, 0x0f,
++    0x4c, 0x31, 0x1c, 0x19, 0x4c, 0x28, 0x06, 0x1e, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x05, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x09, 0x40, 0x40, 0x40, 0x09, 0x53,
++    0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5d,
++    0x54, 0x52, 0x03, 0x19, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x55, 0x55, 0x49, 0x51,
++    0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4d, 0x5d, 0x64, 0x61, 0x5d, 0x56, 0x45, 0x41, 0x53, 0x55, 0x55,
++    0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4d, 0x5d, 0x64, 0x61, 0x5d, 0x56, 0x45, 0x41, 0x53,
++    0x05, 0x4b, 0x23, 0x54, 0x5d, 0x5d, 0x51, 0x55, 0x55, 0x52, 0x49, 0x45, 0x49, 0x02, 0x51, 0x54,
++    0x31, 0x07, 0x51, 0x02, 0x51, 0x54, 0x31, 0x07, 0x51, 0x02, 0x51, 0x54, 0x31, 0x07, 0x51, 0x4c,
++    0x44, 0x19, 0x19, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5d, 0x13, 0x44, 0x5d, 0x40, 0x40,
++    0x4c, 0x42, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x11, 0x27, 0x42, 0x44, 0x02, 0x06, 0x0f,
++    0x4c, 0x31, 0x1c, 0x19, 0x4c, 0x26, 0x06, 0x1d, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x04, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x08, 0x40, 0x40, 0x40, 0x08, 0x51,
++    0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5c,
++    0x54, 0x51, 0x03, 0x18, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x54, 0x54, 0x48, 0x50,
++    0x4c, 0x07, 0x50, 0x60, 0x4c, 0x4c, 0x5c, 0x64, 0x60, 0x5c, 0x55, 0x44, 0x40, 0x51, 0x54, 0x54,
++    0x48, 0x50, 0x4c, 0x07, 0x50, 0x60, 0x4c, 0x4c, 0x5c, 0x64, 0x60, 0x5c, 0x55, 0x44, 0x40, 0x51,
++    0x06, 0x4b, 0x23, 0x54, 0x5c, 0x5c, 0x50, 0x54, 0x54, 0x51, 0x48, 0x44, 0x48, 0x03, 0x50, 0x54,
++    0x30, 0x07, 0x50, 0x03, 0x50, 0x54, 0x30, 0x07, 0x50, 0x03, 0x50, 0x54, 0x30, 0x07, 0x50, 0x4c,
++    0x44, 0x18, 0x18, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5c, 0x13, 0x44, 0x5c, 0x40, 0x40,
++    0x4c, 0x41, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x12, 0x27, 0x41, 0x44, 0x03, 0x07, 0x0f,
++    0x4c, 0x30, 0x1c, 0x18, 0x4c, 0x25, 0x07, 0x1c, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x03, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x07, 0x4f,
++    0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x5b,
++    0x53, 0x4f, 0x04, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x53, 0x53, 0x47, 0x4f,
++    0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4b, 0x5b, 0x63, 0x5f, 0x5b, 0x53, 0x43, 0x00, 0x4f, 0x53, 0x53,
++    0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4b, 0x5b, 0x63, 0x5f, 0x5b, 0x53, 0x43, 0x00, 0x4f,
++    0x08, 0x4c, 0x24, 0x53, 0x5b, 0x5b, 0x4f, 0x53, 0x53, 0x4f, 0x47, 0x43, 0x47, 0x04, 0x4f, 0x53,
++    0x2f, 0x07, 0x4f, 0x04, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x04, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x4b,
++    0x43, 0x17, 0x17, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x5b, 0x14, 0x43, 0x5b, 0x40, 0x40,
++    0x4b, 0x00, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x14, 0x27, 0x00, 0x43, 0x04, 0x08, 0x0f,
++    0x4b, 0x2f, 0x1b, 0x17, 0x4b, 0x23, 0x08, 0x1b, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x02, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x07, 0x4d,
++    0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x5a,
++    0x53, 0x4e, 0x04, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x52, 0x52, 0x47, 0x4f,
++    0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4a, 0x5a, 0x63, 0x5f, 0x5a, 0x52, 0x42, 0x00, 0x4d, 0x52, 0x52,
++    0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4a, 0x5a, 0x63, 0x5f, 0x5a, 0x52, 0x42, 0x00, 0x4d,
++    0x09, 0x4c, 0x24, 0x53, 0x5a, 0x5a, 0x4f, 0x52, 0x52, 0x4e, 0x47, 0x42, 0x47, 0x05, 0x4f, 0x53,
++    0x2f, 0x07, 0x4f, 0x05, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x05, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x4b,
++    0x43, 0x17, 0x17, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x5a, 0x14, 0x43, 0x5a, 0x40, 0x40,
++    0x4b, 0x01, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x15, 0x27, 0x01, 0x43, 0x05, 0x08, 0x0f,
++    0x4b, 0x2f, 0x1b, 0x17, 0x4b, 0x22, 0x08, 0x1a, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x01, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x40, 0x40, 0x40, 0x06, 0x4b,
++    0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x59,
++    0x53, 0x4d, 0x04, 0x16, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x51, 0x51, 0x46, 0x4e,
++    0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x50, 0x41, 0x01, 0x4b, 0x51, 0x51,
++    0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x50, 0x41, 0x01, 0x4b,
++    0x0a, 0x4c, 0x24, 0x53, 0x59, 0x59, 0x4e, 0x51, 0x51, 0x4d, 0x46, 0x41, 0x46, 0x06, 0x4e, 0x53,
++    0x2e, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, 0x4b,
++    0x43, 0x16, 0x16, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x59, 0x14, 0x43, 0x59, 0x40, 0x40,
++    0x4b, 0x02, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x17, 0x27, 0x02, 0x43, 0x06, 0x09, 0x0f,
++    0x4b, 0x2e, 0x1b, 0x16, 0x4b, 0x20, 0x09, 0x19, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x00, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x05, 0x4a,
++    0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x59,
++    0x53, 0x4c, 0x04, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x51, 0x51, 0x46, 0x4e,
++    0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x4f, 0x41, 0x01, 0x4a, 0x51, 0x51,
++    0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x4f, 0x41, 0x01, 0x4a,
++    0x0b, 0x4d, 0x24, 0x53, 0x59, 0x59, 0x4e, 0x51, 0x51, 0x4c, 0x46, 0x41, 0x46, 0x06, 0x4e, 0x53,
++    0x2d, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2d, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2d, 0x07, 0x4e, 0x4b,
++    0x43, 0x15, 0x15, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x59, 0x14, 0x43, 0x59, 0x40, 0x40,
++    0x4b, 0x03, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x18, 0x27, 0x03, 0x43, 0x06, 0x09, 0x0f,
++    0x4b, 0x2d, 0x1a, 0x15, 0x4b, 0x1e, 0x09, 0x18, 0x04, 0x07, 0x14, 0x12, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x00, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x05, 0x48,
++    0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x58,
++    0x52, 0x4a, 0x05, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x50, 0x50, 0x45, 0x4d,
++    0x4a, 0x07, 0x4d, 0x5d, 0x4a, 0x48, 0x58, 0x62, 0x5d, 0x58, 0x4d, 0x40, 0x02, 0x48, 0x50, 0x50,
++    0x45, 0x4d, 0x4a, 0x07, 0x4d, 0x5d, 0x4a, 0x48, 0x58, 0x62, 0x5d, 0x58, 0x4d, 0x40, 0x02, 0x48,
++    0x0d, 0x4d, 0x25, 0x52, 0x58, 0x58, 0x4d, 0x50, 0x50, 0x4a, 0x45, 0x40, 0x45, 0x07, 0x4d, 0x52,
++    0x2d, 0x07, 0x4d, 0x07, 0x4d, 0x52, 0x2d, 0x07, 0x4d, 0x07, 0x4d, 0x52, 0x2d, 0x07, 0x4d, 0x4a,
++    0x42, 0x15, 0x15, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x58, 0x15, 0x42, 0x58, 0x40, 0x40,
++    0x4a, 0x05, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1a, 0x27, 0x05, 0x42, 0x07, 0x0a, 0x0f,
++    0x4a, 0x2d, 0x1a, 0x15, 0x4a, 0x1d, 0x0a, 0x18, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x40, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x40, 0x40, 0x40, 0x04, 0x46,
++    0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x57,
++    0x52, 0x49, 0x05, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4f, 0x4f, 0x44, 0x4c,
++    0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x47, 0x57, 0x62, 0x5c, 0x57, 0x4b, 0x00, 0x03, 0x46, 0x4f, 0x4f,
++    0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x47, 0x57, 0x62, 0x5c, 0x57, 0x4b, 0x00, 0x03, 0x46,
++    0x0e, 0x4d, 0x25, 0x52, 0x57, 0x57, 0x4c, 0x4f, 0x4f, 0x49, 0x44, 0x00, 0x44, 0x08, 0x4c, 0x52,
++    0x2c, 0x07, 0x4c, 0x08, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x08, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x4a,
++    0x42, 0x14, 0x14, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x57, 0x15, 0x42, 0x57, 0x40, 0x40,
++    0x4a, 0x06, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1c, 0x27, 0x06, 0x42, 0x08, 0x0b, 0x0f,
++    0x4a, 0x2c, 0x1a, 0x14, 0x4a, 0x1b, 0x0b, 0x17, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x41, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x40, 0x40, 0x40, 0x04, 0x44,
++    0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x56,
++    0x52, 0x48, 0x05, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4e, 0x4e, 0x44, 0x4c,
++    0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x46, 0x56, 0x62, 0x5c, 0x56, 0x4a, 0x01, 0x03, 0x44, 0x4e, 0x4e,
++    0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x46, 0x56, 0x62, 0x5c, 0x56, 0x4a, 0x01, 0x03, 0x44,
++    0x0f, 0x4d, 0x25, 0x52, 0x56, 0x56, 0x4c, 0x4e, 0x4e, 0x48, 0x44, 0x01, 0x44, 0x09, 0x4c, 0x52,
++    0x2c, 0x07, 0x4c, 0x09, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x09, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x4a,
++    0x42, 0x14, 0x14, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x56, 0x15, 0x42, 0x56, 0x40, 0x40,
++    0x4a, 0x07, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1d, 0x27, 0x07, 0x42, 0x09, 0x0b, 0x0f,
++    0x4a, 0x2c, 0x1a, 0x14, 0x4a, 0x1a, 0x0b, 0x16, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x42, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x40, 0x40, 0x40, 0x03, 0x42,
++    0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x55,
++    0x51, 0x47, 0x06, 0x13, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4d, 0x4d, 0x43, 0x4b,
++    0x49, 0x07, 0x4b, 0x5b, 0x49, 0x45, 0x55, 0x61, 0x5b, 0x55, 0x48, 0x02, 0x04, 0x42, 0x4d, 0x4d,
++    0x43, 0x4b, 0x49, 0x07, 0x4b, 0x5b, 0x49, 0x45, 0x55, 0x61, 0x5b, 0x55, 0x48, 0x02, 0x04, 0x42,
++    0x10, 0x4e, 0x26, 0x51, 0x55, 0x55, 0x4b, 0x4d, 0x4d, 0x47, 0x43, 0x02, 0x43, 0x0a, 0x4b, 0x51,
++    0x2b, 0x07, 0x4b, 0x0a, 0x4b, 0x51, 0x2b, 0x07, 0x4b, 0x0a, 0x4b, 0x51, 0x2b, 0x07, 0x4b, 0x49,
++    0x41, 0x13, 0x13, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x55, 0x16, 0x41, 0x55, 0x40, 0x40,
++    0x49, 0x08, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x1f, 0x27, 0x08, 0x41, 0x0a, 0x0c, 0x0f,
++    0x49, 0x2b, 0x19, 0x13, 0x49, 0x18, 0x0c, 0x15, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x43, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x40, 0x40, 0x40, 0x02, 0x40,
++    0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x54,
++    0x51, 0x45, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4c, 0x4c, 0x42, 0x4a,
++    0x49, 0x07, 0x4a, 0x5a, 0x49, 0x44, 0x54, 0x61, 0x5a, 0x54, 0x47, 0x03, 0x05, 0x40, 0x4c, 0x4c,
++    0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x44, 0x54, 0x61, 0x5a, 0x54, 0x47, 0x03, 0x05, 0x40,
++    0x12, 0x4e, 0x26, 0x51, 0x54, 0x54, 0x4a, 0x4c, 0x4c, 0x45, 0x42, 0x03, 0x42, 0x0b, 0x4a, 0x51,
++    0x2a, 0x07, 0x4a, 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x49,
++    0x41, 0x12, 0x12, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x54, 0x16, 0x41, 0x54, 0x40, 0x40,
++    0x49, 0x0a, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x20, 0x27, 0x0a, 0x41, 0x0b, 0x0d, 0x0f,
++    0x49, 0x2a, 0x19, 0x12, 0x49, 0x17, 0x0d, 0x14, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x44, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x40, 0x40, 0x40, 0x02, 0x01,
++    0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x53,
++    0x51, 0x44, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4b, 0x42, 0x4a,
++    0x49, 0x07, 0x4a, 0x5a, 0x49, 0x43, 0x53, 0x61, 0x5a, 0x53, 0x45, 0x04, 0x05, 0x01, 0x4b, 0x4b,
++    0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x43, 0x53, 0x61, 0x5a, 0x53, 0x45, 0x04, 0x05, 0x01,
++    0x13, 0x4e, 0x26, 0x51, 0x53, 0x53, 0x4a, 0x4b, 0x4b, 0x44, 0x42, 0x04, 0x42, 0x0c, 0x4a, 0x51,
++    0x2a, 0x07, 0x4a, 0x0c, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x0c, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x49,
++    0x41, 0x12, 0x12, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x53, 0x16, 0x41, 0x53, 0x40, 0x40,
++    0x49, 0x0b, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x22, 0x27, 0x0b, 0x41, 0x0c, 0x0d, 0x0f,
++    0x49, 0x2a, 0x19, 0x12, 0x49, 0x15, 0x0d, 0x13, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x45, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x40, 0x40, 0x40, 0x01, 0x03,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x52,
++    0x50, 0x43, 0x07, 0x11, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x4a, 0x41, 0x49,
++    0x48, 0x07, 0x49, 0x59, 0x48, 0x42, 0x52, 0x60, 0x59, 0x52, 0x44, 0x05, 0x06, 0x03, 0x4a, 0x4a,
++    0x41, 0x49, 0x48, 0x07, 0x49, 0x59, 0x48, 0x42, 0x52, 0x60, 0x59, 0x52, 0x44, 0x05, 0x06, 0x03,
++    0x14, 0x4f, 0x27, 0x50, 0x52, 0x52, 0x49, 0x4a, 0x4a, 0x43, 0x41, 0x05, 0x41, 0x0d, 0x49, 0x50,
++    0x29, 0x07, 0x49, 0x0d, 0x49, 0x50, 0x29, 0x07, 0x49, 0x0d, 0x49, 0x50, 0x29, 0x07, 0x49, 0x48,
++    0x40, 0x11, 0x11, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x52, 0x17, 0x40, 0x52, 0x40, 0x40,
++    0x48, 0x0c, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x23, 0x27, 0x0c, 0x40, 0x0d, 0x0e, 0x0f,
++    0x48, 0x29, 0x18, 0x11, 0x48, 0x14, 0x0e, 0x12, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x46, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, 0x40, 0x40, 0x00, 0x04,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x51,
++    0x50, 0x42, 0x07, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x41, 0x49,
++    0x48, 0x07, 0x49, 0x59, 0x48, 0x41, 0x51, 0x60, 0x59, 0x51, 0x42, 0x06, 0x06, 0x04, 0x49, 0x49,
++    0x41, 0x49, 0x48, 0x07, 0x49, 0x59, 0x48, 0x41, 0x51, 0x60, 0x59, 0x51, 0x42, 0x06, 0x06, 0x04,
++    0x15, 0x4f, 0x27, 0x50, 0x51, 0x51, 0x49, 0x49, 0x49, 0x42, 0x41, 0x06, 0x41, 0x0e, 0x49, 0x50,
++    0x28, 0x07, 0x49, 0x0e, 0x49, 0x50, 0x28, 0x07, 0x49, 0x0e, 0x49, 0x50, 0x28, 0x07, 0x49, 0x48,
++    0x40, 0x10, 0x10, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x51, 0x17, 0x40, 0x51, 0x40, 0x40,
++    0x48, 0x0d, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x25, 0x27, 0x0d, 0x40, 0x0e, 0x0e, 0x0f,
++    0x48, 0x28, 0x18, 0x10, 0x48, 0x12, 0x0e, 0x11, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x47, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, 0x40, 0x40, 0x00, 0x06,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x50,
++    0x50, 0x40, 0x07, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48,
++    0x48, 0x07, 0x48, 0x58, 0x48, 0x40, 0x50, 0x60, 0x58, 0x50, 0x40, 0x07, 0x07, 0x06, 0x48, 0x48,
++    0x40, 0x48, 0x48, 0x07, 0x48, 0x58, 0x48, 0x40, 0x50, 0x60, 0x58, 0x50, 0x40, 0x07, 0x07, 0x06,
++    0x17, 0x4f, 0x27, 0x50, 0x50, 0x50, 0x48, 0x48, 0x48, 0x40, 0x40, 0x07, 0x40, 0x0f, 0x48, 0x50,
++    0x28, 0x07, 0x48, 0x0f, 0x48, 0x50, 0x28, 0x07, 0x48, 0x0f, 0x48, 0x50, 0x28, 0x07, 0x48, 0x48,
++    0x40, 0x10, 0x10, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x50, 0x17, 0x40, 0x50, 0x40, 0x40,
++    0x48, 0x0f, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x27, 0x27, 0x0f, 0x40, 0x0f, 0x0f, 0x0f,
++    0x48, 0x28, 0x18, 0x10, 0x48, 0x10, 0x0f, 0x10, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x48, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x08,
++    0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4f,
++    0x4f, 0x00, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47,
++    0x47, 0x07, 0x47, 0x57, 0x47, 0x00, 0x4f, 0x5f, 0x57, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47,
++    0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x00, 0x4f, 0x5f, 0x57, 0x4f, 0x00, 0x08, 0x08, 0x08,
++    0x18, 0x50, 0x28, 0x4f, 0x4f, 0x4f, 0x47, 0x47, 0x47, 0x00, 0x00, 0x08, 0x00, 0x10, 0x47, 0x4f,
++    0x27, 0x07, 0x47, 0x10, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x10, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x47,
++    0x00, 0x0f, 0x0f, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4f, 0x18, 0x00, 0x4f, 0x40, 0x40,
++    0x47, 0x10, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x28, 0x27, 0x10, 0x00, 0x10, 0x10, 0x0f,
++    0x47, 0x27, 0x17, 0x0f, 0x47, 0x0f, 0x10, 0x0f, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x49, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a,
++    0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4e,
++    0x4f, 0x01, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x46, 0x00, 0x47,
++    0x47, 0x07, 0x47, 0x57, 0x47, 0x01, 0x4e, 0x5f, 0x57, 0x4e, 0x02, 0x09, 0x08, 0x0a, 0x46, 0x46,
++    0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x01, 0x4e, 0x5f, 0x57, 0x4e, 0x02, 0x09, 0x08, 0x0a,
++    0x19, 0x50, 0x28, 0x4f, 0x4e, 0x4e, 0x47, 0x46, 0x46, 0x01, 0x00, 0x09, 0x00, 0x11, 0x47, 0x4f,
++    0x27, 0x07, 0x47, 0x11, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x11, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x47,
++    0x00, 0x0f, 0x0f, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4e, 0x18, 0x00, 0x4e, 0x40, 0x40,
++    0x47, 0x11, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x2a, 0x27, 0x11, 0x00, 0x11, 0x10, 0x0f,
++    0x47, 0x27, 0x17, 0x0f, 0x47, 0x0d, 0x10, 0x0e, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4a, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x40, 0x40, 0x40, 0x41, 0x0c,
++    0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4d,
++    0x4f, 0x02, 0x08, 0x0e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x45, 0x45, 0x01, 0x46,
++    0x47, 0x07, 0x46, 0x56, 0x47, 0x02, 0x4d, 0x5f, 0x56, 0x4d, 0x03, 0x0a, 0x09, 0x0c, 0x45, 0x45,
++    0x01, 0x46, 0x47, 0x07, 0x46, 0x56, 0x47, 0x02, 0x4d, 0x5f, 0x56, 0x4d, 0x03, 0x0a, 0x09, 0x0c,
++    0x1a, 0x50, 0x28, 0x4f, 0x4d, 0x4d, 0x46, 0x45, 0x45, 0x02, 0x01, 0x0a, 0x01, 0x12, 0x46, 0x4f,
++    0x26, 0x07, 0x46, 0x12, 0x46, 0x4f, 0x26, 0x07, 0x46, 0x12, 0x46, 0x4f, 0x26, 0x07, 0x46, 0x47,
++    0x00, 0x0e, 0x0e, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4d, 0x18, 0x00, 0x4d, 0x40, 0x40,
++    0x47, 0x12, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x2b, 0x27, 0x12, 0x00, 0x12, 0x11, 0x0f,
++    0x47, 0x26, 0x17, 0x0e, 0x47, 0x0c, 0x11, 0x0d, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4b, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x40, 0x40, 0x40, 0x42, 0x0e,
++    0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4c,
++    0x4e, 0x04, 0x09, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x44, 0x02, 0x45,
++    0x46, 0x07, 0x45, 0x55, 0x46, 0x03, 0x4c, 0x5e, 0x55, 0x4c, 0x05, 0x0b, 0x0a, 0x0e, 0x44, 0x44,
++    0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x03, 0x4c, 0x5e, 0x55, 0x4c, 0x05, 0x0b, 0x0a, 0x0e,
++    0x1c, 0x51, 0x29, 0x4e, 0x4c, 0x4c, 0x45, 0x44, 0x44, 0x04, 0x02, 0x0b, 0x02, 0x13, 0x45, 0x4e,
++    0x25, 0x07, 0x45, 0x13, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x13, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x46,
++    0x01, 0x0d, 0x0d, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4c, 0x19, 0x01, 0x4c, 0x40, 0x40,
++    0x46, 0x14, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x2d, 0x27, 0x14, 0x01, 0x13, 0x12, 0x0f,
++    0x46, 0x25, 0x16, 0x0d, 0x46, 0x0a, 0x12, 0x0c, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4c, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x40, 0x40, 0x40, 0x42, 0x10,
++    0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4b,
++    0x4e, 0x05, 0x09, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x43, 0x43, 0x02, 0x45,
++    0x46, 0x07, 0x45, 0x55, 0x46, 0x04, 0x4b, 0x5e, 0x55, 0x4b, 0x06, 0x0c, 0x0a, 0x10, 0x43, 0x43,
++    0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x04, 0x4b, 0x5e, 0x55, 0x4b, 0x06, 0x0c, 0x0a, 0x10,
++    0x1d, 0x51, 0x29, 0x4e, 0x4b, 0x4b, 0x45, 0x43, 0x43, 0x05, 0x02, 0x0c, 0x02, 0x14, 0x45, 0x4e,
++    0x25, 0x07, 0x45, 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x46,
++    0x01, 0x0d, 0x0d, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4b, 0x19, 0x01, 0x4b, 0x40, 0x40,
++    0x46, 0x15, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x2e, 0x27, 0x15, 0x01, 0x14, 0x12, 0x0f,
++    0x46, 0x25, 0x16, 0x0d, 0x46, 0x09, 0x12, 0x0b, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4d, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x40, 0x40, 0x40, 0x43, 0x12,
++    0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4a,
++    0x4e, 0x06, 0x09, 0x0c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x42, 0x42, 0x03, 0x44,
++    0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x08, 0x0d, 0x0b, 0x12, 0x42, 0x42,
++    0x03, 0x44, 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x08, 0x0d, 0x0b, 0x12,
++    0x1e, 0x51, 0x29, 0x4e, 0x4a, 0x4a, 0x44, 0x42, 0x42, 0x06, 0x03, 0x0d, 0x03, 0x15, 0x44, 0x4e,
++    0x24, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x24, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x24, 0x07, 0x44, 0x46,
++    0x01, 0x0c, 0x0c, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4a, 0x19, 0x01, 0x4a, 0x40, 0x40,
++    0x46, 0x16, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x30, 0x27, 0x16, 0x01, 0x15, 0x13, 0x0f,
++    0x46, 0x24, 0x16, 0x0c, 0x46, 0x07, 0x13, 0x0a, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4e, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x40, 0x40, 0x40, 0x44, 0x13,
++    0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4a,
++    0x4e, 0x07, 0x09, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x42, 0x42, 0x03, 0x44,
++    0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x09, 0x0d, 0x0b, 0x13, 0x42, 0x42,
++    0x03, 0x44, 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x09, 0x0d, 0x0b, 0x13,
++    0x1f, 0x52, 0x29, 0x4e, 0x4a, 0x4a, 0x44, 0x42, 0x42, 0x07, 0x03, 0x0d, 0x03, 0x15, 0x44, 0x4e,
++    0x23, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x23, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x23, 0x07, 0x44, 0x46,
++    0x01, 0x0b, 0x0b, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4a, 0x19, 0x01, 0x4a, 0x40, 0x40,
++    0x46, 0x17, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x31, 0x27, 0x17, 0x01, 0x15, 0x13, 0x0f,
++    0x46, 0x23, 0x15, 0x0b, 0x46, 0x05, 0x13, 0x09, 0x09, 0x07, 0x19, 0x0d, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4e, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x40, 0x40, 0x40, 0x44, 0x15,
++    0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x49,
++    0x4d, 0x09, 0x0a, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x41, 0x41, 0x04, 0x43,
++    0x45, 0x07, 0x43, 0x53, 0x45, 0x06, 0x49, 0x5d, 0x53, 0x49, 0x0b, 0x0e, 0x0c, 0x15, 0x41, 0x41,
++    0x04, 0x43, 0x45, 0x07, 0x43, 0x53, 0x45, 0x06, 0x49, 0x5d, 0x53, 0x49, 0x0b, 0x0e, 0x0c, 0x15,
++    0x21, 0x52, 0x2a, 0x4d, 0x49, 0x49, 0x43, 0x41, 0x41, 0x09, 0x04, 0x0e, 0x04, 0x16, 0x43, 0x4d,
++    0x23, 0x07, 0x43, 0x16, 0x43, 0x4d, 0x23, 0x07, 0x43, 0x16, 0x43, 0x4d, 0x23, 0x07, 0x43, 0x45,
++    0x02, 0x0b, 0x0b, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x49, 0x1a, 0x02, 0x49, 0x40, 0x40,
++    0x45, 0x19, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x33, 0x27, 0x19, 0x02, 0x16, 0x14, 0x0f,
++    0x45, 0x23, 0x15, 0x0b, 0x45, 0x04, 0x14, 0x09, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4f, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x40, 0x40, 0x40, 0x45, 0x17,
++    0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x48,
++    0x4d, 0x0a, 0x0a, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x40, 0x40, 0x05, 0x42,
++    0x45, 0x07, 0x42, 0x52, 0x45, 0x07, 0x48, 0x5d, 0x52, 0x48, 0x0d, 0x0f, 0x0d, 0x17, 0x40, 0x40,
++    0x05, 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x07, 0x48, 0x5d, 0x52, 0x48, 0x0d, 0x0f, 0x0d, 0x17,
++    0x22, 0x52, 0x2a, 0x4d, 0x48, 0x48, 0x42, 0x40, 0x40, 0x0a, 0x05, 0x0f, 0x05, 0x17, 0x42, 0x4d,
++    0x22, 0x07, 0x42, 0x17, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x17, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x45,
++    0x02, 0x0a, 0x0a, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x48, 0x1a, 0x02, 0x48, 0x40, 0x40,
++    0x45, 0x1a, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x35, 0x27, 0x1a, 0x02, 0x17, 0x15, 0x0f,
++    0x45, 0x22, 0x15, 0x0a, 0x45, 0x02, 0x15, 0x08, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x50, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x40, 0x40, 0x40, 0x45, 0x19,
++    0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x47,
++    0x4d, 0x0b, 0x0a, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x00, 0x00, 0x05, 0x42,
++    0x45, 0x07, 0x42, 0x52, 0x45, 0x08, 0x47, 0x5d, 0x52, 0x47, 0x0e, 0x10, 0x0d, 0x19, 0x00, 0x00,
++    0x05, 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x08, 0x47, 0x5d, 0x52, 0x47, 0x0e, 0x10, 0x0d, 0x19,
++    0x23, 0x52, 0x2a, 0x4d, 0x47, 0x47, 0x42, 0x00, 0x00, 0x0b, 0x05, 0x10, 0x05, 0x18, 0x42, 0x4d,
++    0x22, 0x07, 0x42, 0x18, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x18, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x45,
++    0x02, 0x0a, 0x0a, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x47, 0x1a, 0x02, 0x47, 0x40, 0x40,
++    0x45, 0x1b, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x36, 0x27, 0x1b, 0x02, 0x18, 0x15, 0x0f,
++    0x45, 0x22, 0x15, 0x0a, 0x45, 0x01, 0x15, 0x07, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x51, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x40, 0x40, 0x40, 0x46, 0x1b,
++    0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x46,
++    0x4c, 0x0c, 0x0b, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x01, 0x01, 0x06, 0x41,
++    0x44, 0x07, 0x41, 0x51, 0x44, 0x09, 0x46, 0x5c, 0x51, 0x46, 0x10, 0x11, 0x0e, 0x1b, 0x01, 0x01,
++    0x06, 0x41, 0x44, 0x07, 0x41, 0x51, 0x44, 0x09, 0x46, 0x5c, 0x51, 0x46, 0x10, 0x11, 0x0e, 0x1b,
++    0x24, 0x53, 0x2b, 0x4c, 0x46, 0x46, 0x41, 0x01, 0x01, 0x0c, 0x06, 0x11, 0x06, 0x19, 0x41, 0x4c,
++    0x21, 0x07, 0x41, 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, 0x44,
++    0x03, 0x09, 0x09, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x46, 0x1b, 0x03, 0x46, 0x40, 0x40,
++    0x44, 0x1c, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x38, 0x27, 0x1c, 0x03, 0x19, 0x16, 0x0f,
++    0x44, 0x21, 0x14, 0x09, 0x44, 0x40, 0x16, 0x06, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x52, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x40, 0x40, 0x40, 0x47, 0x1d,
++    0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x45,
++    0x4c, 0x0e, 0x0b, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x02, 0x02, 0x07, 0x40,
++    0x44, 0x07, 0x40, 0x50, 0x44, 0x0a, 0x45, 0x5c, 0x50, 0x45, 0x11, 0x12, 0x0f, 0x1d, 0x02, 0x02,
++    0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0a, 0x45, 0x5c, 0x50, 0x45, 0x11, 0x12, 0x0f, 0x1d,
++    0x26, 0x53, 0x2b, 0x4c, 0x45, 0x45, 0x40, 0x02, 0x02, 0x0e, 0x07, 0x12, 0x07, 0x1a, 0x40, 0x4c,
++    0x20, 0x07, 0x40, 0x1a, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1a, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x44,
++    0x03, 0x08, 0x08, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x45, 0x1b, 0x03, 0x45, 0x40, 0x40,
++    0x44, 0x1e, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x39, 0x27, 0x1e, 0x03, 0x1a, 0x17, 0x0f,
++    0x44, 0x20, 0x14, 0x08, 0x44, 0x41, 0x17, 0x05, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x53, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x40, 0x40, 0x40, 0x47, 0x1f,
++    0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x44,
++    0x4c, 0x0f, 0x0b, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x03, 0x03, 0x07, 0x40,
++    0x44, 0x07, 0x40, 0x50, 0x44, 0x0b, 0x44, 0x5c, 0x50, 0x44, 0x13, 0x13, 0x0f, 0x1f, 0x03, 0x03,
++    0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0b, 0x44, 0x5c, 0x50, 0x44, 0x13, 0x13, 0x0f, 0x1f,
++    0x27, 0x53, 0x2b, 0x4c, 0x44, 0x44, 0x40, 0x03, 0x03, 0x0f, 0x07, 0x13, 0x07, 0x1b, 0x40, 0x4c,
++    0x20, 0x07, 0x40, 0x1b, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1b, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x44,
++    0x03, 0x08, 0x08, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x44, 0x1b, 0x03, 0x44, 0x40, 0x40,
++    0x44, 0x1f, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x3b, 0x27, 0x1f, 0x03, 0x1b, 0x17, 0x0f,
++    0x44, 0x20, 0x14, 0x08, 0x44, 0x43, 0x17, 0x04, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x54, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x40, 0x40, 0x40, 0x48, 0x21,
++    0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x43,
++    0x4b, 0x10, 0x0c, 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x04, 0x04, 0x08, 0x00,
++    0x43, 0x07, 0x00, 0x4f, 0x43, 0x0c, 0x43, 0x5b, 0x4f, 0x43, 0x14, 0x14, 0x10, 0x21, 0x04, 0x04,
++    0x08, 0x00, 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0c, 0x43, 0x5b, 0x4f, 0x43, 0x14, 0x14, 0x10, 0x21,
++    0x28, 0x54, 0x2c, 0x4b, 0x43, 0x43, 0x00, 0x04, 0x04, 0x10, 0x08, 0x14, 0x08, 0x1c, 0x00, 0x4b,
++    0x1f, 0x07, 0x00, 0x1c, 0x00, 0x4b, 0x1f, 0x07, 0x00, 0x1c, 0x00, 0x4b, 0x1f, 0x07, 0x00, 0x43,
++    0x04, 0x07, 0x07, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x43, 0x1c, 0x04, 0x43, 0x40, 0x40,
++    0x43, 0x20, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3c, 0x27, 0x20, 0x04, 0x1c, 0x18, 0x0f,
++    0x43, 0x1f, 0x13, 0x07, 0x43, 0x44, 0x18, 0x03, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x55, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x40, 0x40, 0x40, 0x49, 0x22,
++    0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x42,
++    0x4b, 0x11, 0x0c, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x05, 0x05, 0x08, 0x00,
++    0x43, 0x07, 0x00, 0x4f, 0x43, 0x0d, 0x42, 0x5b, 0x4f, 0x42, 0x16, 0x15, 0x10, 0x22, 0x05, 0x05,
++    0x08, 0x00, 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0d, 0x42, 0x5b, 0x4f, 0x42, 0x16, 0x15, 0x10, 0x22,
++    0x29, 0x54, 0x2c, 0x4b, 0x42, 0x42, 0x00, 0x05, 0x05, 0x11, 0x08, 0x15, 0x08, 0x1d, 0x00, 0x4b,
++    0x1e, 0x07, 0x00, 0x1d, 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x1d, 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x43,
++    0x04, 0x06, 0x06, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x42, 0x1c, 0x04, 0x42, 0x40, 0x40,
++    0x43, 0x21, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3e, 0x27, 0x21, 0x04, 0x1d, 0x18, 0x0f,
++    0x43, 0x1e, 0x13, 0x06, 0x43, 0x46, 0x18, 0x02, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x56, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x40, 0x40, 0x40, 0x49, 0x24,
++    0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x41,
++    0x4b, 0x13, 0x0c, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x06, 0x06, 0x09, 0x01,
++    0x43, 0x07, 0x01, 0x4e, 0x43, 0x0e, 0x41, 0x5b, 0x4e, 0x41, 0x18, 0x16, 0x11, 0x24, 0x06, 0x06,
++    0x09, 0x01, 0x43, 0x07, 0x01, 0x4e, 0x43, 0x0e, 0x41, 0x5b, 0x4e, 0x41, 0x18, 0x16, 0x11, 0x24,
++    0x2b, 0x54, 0x2c, 0x4b, 0x41, 0x41, 0x01, 0x06, 0x06, 0x13, 0x09, 0x16, 0x09, 0x1e, 0x01, 0x4b,
++    0x1e, 0x07, 0x01, 0x1e, 0x01, 0x4b, 0x1e, 0x07, 0x01, 0x1e, 0x01, 0x4b, 0x1e, 0x07, 0x01, 0x43,
++    0x04, 0x06, 0x06, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x41, 0x1c, 0x04, 0x41, 0x40, 0x40,
++    0x43, 0x23, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3e, 0x27, 0x23, 0x04, 0x1e, 0x19, 0x0f,
++    0x43, 0x1e, 0x13, 0x06, 0x43, 0x48, 0x19, 0x01, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x57, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x40, 0x40, 0x40, 0x4a, 0x26,
++    0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x40,
++    0x4a, 0x14, 0x0d, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x07, 0x07, 0x0a, 0x02,
++    0x42, 0x07, 0x02, 0x4d, 0x42, 0x0f, 0x40, 0x5a, 0x4d, 0x40, 0x19, 0x17, 0x12, 0x26, 0x07, 0x07,
++    0x0a, 0x02, 0x42, 0x07, 0x02, 0x4d, 0x42, 0x0f, 0x40, 0x5a, 0x4d, 0x40, 0x19, 0x17, 0x12, 0x26,
++    0x2c, 0x55, 0x2d, 0x4a, 0x40, 0x40, 0x02, 0x07, 0x07, 0x14, 0x0a, 0x17, 0x0a, 0x1f, 0x02, 0x4a,
++    0x1d, 0x07, 0x02, 0x1f, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x1f, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x42,
++    0x05, 0x05, 0x05, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x40, 0x1d, 0x05, 0x40, 0x40, 0x40,
++    0x42, 0x24, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x24, 0x05, 0x1f, 0x1a, 0x0f,
++    0x42, 0x1d, 0x12, 0x05, 0x42, 0x49, 0x1a, 0x00, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x58, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x40, 0x40, 0x40, 0x4a, 0x28,
++    0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x00,
++    0x4a, 0x15, 0x0d, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x08, 0x08, 0x0a, 0x02,
++    0x42, 0x07, 0x02, 0x4d, 0x42, 0x10, 0x00, 0x5a, 0x4d, 0x00, 0x1b, 0x18, 0x12, 0x28, 0x08, 0x08,
++    0x0a, 0x02, 0x42, 0x07, 0x02, 0x4d, 0x42, 0x10, 0x00, 0x5a, 0x4d, 0x00, 0x1b, 0x18, 0x12, 0x28,
++    0x2d, 0x55, 0x2d, 0x4a, 0x00, 0x00, 0x02, 0x08, 0x08, 0x15, 0x0a, 0x18, 0x0a, 0x20, 0x02, 0x4a,
++    0x1d, 0x07, 0x02, 0x20, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x20, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x42,
++    0x05, 0x05, 0x05, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x00, 0x1d, 0x05, 0x00, 0x40, 0x40,
++    0x42, 0x25, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x25, 0x05, 0x20, 0x1a, 0x0f,
++    0x42, 0x1d, 0x12, 0x05, 0x42, 0x4b, 0x1a, 0x40, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x59, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4b, 0x40, 0x40, 0x40, 0x4b, 0x2a,
++    0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x01,
++    0x4a, 0x16, 0x0d, 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x09, 0x09, 0x0b, 0x03,
++    0x42, 0x07, 0x03, 0x4c, 0x42, 0x11, 0x01, 0x5a, 0x4c, 0x01, 0x1c, 0x19, 0x13, 0x2a, 0x09, 0x09,
++    0x0b, 0x03, 0x42, 0x07, 0x03, 0x4c, 0x42, 0x11, 0x01, 0x5a, 0x4c, 0x01, 0x1c, 0x19, 0x13, 0x2a,
++    0x2e, 0x55, 0x2d, 0x4a, 0x01, 0x01, 0x03, 0x09, 0x09, 0x16, 0x0b, 0x19, 0x0b, 0x21, 0x03, 0x4a,
++    0x1c, 0x07, 0x03, 0x21, 0x03, 0x4a, 0x1c, 0x07, 0x03, 0x21, 0x03, 0x4a, 0x1c, 0x07, 0x03, 0x42,
++    0x05, 0x04, 0x04, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x01, 0x1d, 0x05, 0x01, 0x40, 0x40,
++    0x42, 0x26, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x26, 0x05, 0x21, 0x1b, 0x0f,
++    0x42, 0x1c, 0x12, 0x04, 0x42, 0x4c, 0x1b, 0x41, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5a, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4c, 0x40, 0x40, 0x40, 0x4c, 0x2c,
++    0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x02,
++    0x49, 0x18, 0x0e, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0a, 0x0a, 0x0c, 0x04,
++    0x41, 0x07, 0x04, 0x4b, 0x41, 0x12, 0x02, 0x59, 0x4b, 0x02, 0x1e, 0x1a, 0x14, 0x2c, 0x0a, 0x0a,
++    0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x12, 0x02, 0x59, 0x4b, 0x02, 0x1e, 0x1a, 0x14, 0x2c,
++    0x30, 0x56, 0x2e, 0x49, 0x02, 0x02, 0x04, 0x0a, 0x0a, 0x18, 0x0c, 0x1a, 0x0c, 0x22, 0x04, 0x49,
++    0x1b, 0x07, 0x04, 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x41,
++    0x06, 0x03, 0x03, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x02, 0x1e, 0x06, 0x02, 0x40, 0x40,
++    0x41, 0x28, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x28, 0x06, 0x22, 0x1c, 0x0f,
++    0x41, 0x1b, 0x11, 0x03, 0x41, 0x4e, 0x1c, 0x42, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5b, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4c, 0x40, 0x40, 0x40, 0x4c, 0x2e,
++    0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x03,
++    0x49, 0x19, 0x0e, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0b, 0x0b, 0x0c, 0x04,
++    0x41, 0x07, 0x04, 0x4b, 0x41, 0x13, 0x03, 0x59, 0x4b, 0x03, 0x1f, 0x1b, 0x14, 0x2e, 0x0b, 0x0b,
++    0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x13, 0x03, 0x59, 0x4b, 0x03, 0x1f, 0x1b, 0x14, 0x2e,
++    0x31, 0x56, 0x2e, 0x49, 0x03, 0x03, 0x04, 0x0b, 0x0b, 0x19, 0x0c, 0x1b, 0x0c, 0x23, 0x04, 0x49,
++    0x1b, 0x07, 0x04, 0x23, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x23, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x41,
++    0x06, 0x03, 0x03, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x03, 0x1e, 0x06, 0x03, 0x40, 0x40,
++    0x41, 0x29, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x29, 0x06, 0x23, 0x1c, 0x0f,
++    0x41, 0x1b, 0x11, 0x03, 0x41, 0x4f, 0x1c, 0x43, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5c, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4d, 0x40, 0x40, 0x40, 0x4d, 0x30,
++    0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x04,
++    0x49, 0x1a, 0x0e, 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0c, 0x0c, 0x0d, 0x05,
++    0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x21, 0x1c, 0x15, 0x30, 0x0c, 0x0c,
++    0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x21, 0x1c, 0x15, 0x30,
++    0x32, 0x56, 0x2e, 0x49, 0x04, 0x04, 0x05, 0x0c, 0x0c, 0x1a, 0x0d, 0x1c, 0x0d, 0x24, 0x05, 0x49,
++    0x1a, 0x07, 0x05, 0x24, 0x05, 0x49, 0x1a, 0x07, 0x05, 0x24, 0x05, 0x49, 0x1a, 0x07, 0x05, 0x41,
++    0x06, 0x02, 0x02, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x04, 0x1e, 0x06, 0x04, 0x40, 0x40,
++    0x41, 0x2a, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x2a, 0x06, 0x24, 0x1d, 0x0f,
++    0x41, 0x1a, 0x11, 0x02, 0x41, 0x51, 0x1d, 0x44, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5d, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x4e, 0x31,
++    0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x04,
++    0x49, 0x1b, 0x0e, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0c, 0x0c, 0x0d, 0x05,
++    0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x22, 0x1c, 0x15, 0x31, 0x0c, 0x0c,
++    0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x22, 0x1c, 0x15, 0x31,
++    0x33, 0x57, 0x2e, 0x49, 0x04, 0x04, 0x05, 0x0c, 0x0c, 0x1b, 0x0d, 0x1c, 0x0d, 0x24, 0x05, 0x49,
++    0x19, 0x07, 0x05, 0x24, 0x05, 0x49, 0x19, 0x07, 0x05, 0x24, 0x05, 0x49, 0x19, 0x07, 0x05, 0x41,
++    0x06, 0x01, 0x01, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x04, 0x1e, 0x06, 0x04, 0x40, 0x40,
++    0x41, 0x2b, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x2b, 0x06, 0x24, 0x1d, 0x0f,
++    0x41, 0x19, 0x10, 0x01, 0x41, 0x53, 0x1d, 0x45, 0x0e, 0x07, 0x1e, 0x08, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5d, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x4e, 0x33,
++    0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x05,
++    0x48, 0x1d, 0x0f, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0d, 0x0d, 0x0e, 0x06,
++    0x40, 0x07, 0x06, 0x49, 0x40, 0x15, 0x05, 0x58, 0x49, 0x05, 0x24, 0x1d, 0x16, 0x33, 0x0d, 0x0d,
++    0x0e, 0x06, 0x40, 0x07, 0x06, 0x49, 0x40, 0x15, 0x05, 0x58, 0x49, 0x05, 0x24, 0x1d, 0x16, 0x33,
++    0x35, 0x57, 0x2f, 0x48, 0x05, 0x05, 0x06, 0x0d, 0x0d, 0x1d, 0x0e, 0x1d, 0x0e, 0x25, 0x06, 0x48,
++    0x19, 0x07, 0x06, 0x25, 0x06, 0x48, 0x19, 0x07, 0x06, 0x25, 0x06, 0x48, 0x19, 0x07, 0x06, 0x40,
++    0x07, 0x01, 0x01, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x05, 0x1f, 0x07, 0x05, 0x40, 0x40,
++    0x40, 0x2d, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2d, 0x07, 0x25, 0x1e, 0x0f,
++    0x40, 0x19, 0x10, 0x01, 0x40, 0x54, 0x1e, 0x45, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5e, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x4f, 0x35,
++    0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x06,
++    0x48, 0x1e, 0x0f, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0e, 0x0e, 0x0f, 0x07,
++    0x40, 0x07, 0x07, 0x48, 0x40, 0x16, 0x06, 0x58, 0x48, 0x06, 0x26, 0x1e, 0x17, 0x35, 0x0e, 0x0e,
++    0x0f, 0x07, 0x40, 0x07, 0x07, 0x48, 0x40, 0x16, 0x06, 0x58, 0x48, 0x06, 0x26, 0x1e, 0x17, 0x35,
++    0x36, 0x57, 0x2f, 0x48, 0x06, 0x06, 0x07, 0x0e, 0x0e, 0x1e, 0x0f, 0x1e, 0x0f, 0x26, 0x07, 0x48,
++    0x18, 0x07, 0x07, 0x26, 0x07, 0x48, 0x18, 0x07, 0x07, 0x26, 0x07, 0x48, 0x18, 0x07, 0x07, 0x40,
++    0x07, 0x00, 0x00, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x06, 0x1f, 0x07, 0x06, 0x40, 0x40,
++    0x40, 0x2e, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2e, 0x07, 0x26, 0x1f, 0x0f,
++    0x40, 0x18, 0x10, 0x00, 0x40, 0x56, 0x1f, 0x46, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5f, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x4f, 0x37,
++    0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x07,
++    0x48, 0x1f, 0x0f, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x07,
++    0x40, 0x07, 0x07, 0x48, 0x40, 0x17, 0x07, 0x58, 0x48, 0x07, 0x27, 0x1f, 0x17, 0x37, 0x0f, 0x0f,
++    0x0f, 0x07, 0x40, 0x07, 0x07, 0x48, 0x40, 0x17, 0x07, 0x58, 0x48, 0x07, 0x27, 0x1f, 0x17, 0x37,
++    0x37, 0x57, 0x2f, 0x48, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x1f, 0x0f, 0x1f, 0x0f, 0x27, 0x07, 0x48,
++    0x18, 0x07, 0x07, 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, 0x40,
++    0x07, 0x00, 0x00, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x07, 0x1f, 0x07, 0x07, 0x40, 0x40,
++    0x40, 0x2f, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2f, 0x07, 0x27, 0x1f, 0x0f,
++    0x40, 0x18, 0x10, 0x00, 0x40, 0x57, 0x1f, 0x47, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x07, 0x48, 0x48, 0x60, 0x40, 0x27, 0x07, 0x07, 0x27, 0x40, 0x48, 0x40, 0x40, 0x40, 0x0f,
++    0x48, 0x68, 0x60, 0x40, 0x68, 0x68, 0x68, 0x68, 0x68, 0x07, 0x07, 0x0f, 0x50, 0x40, 0x60, 0x07,
++    0x68, 0x27, 0x48, 0x17, 0x40, 0x50, 0x1f, 0x40, 0x40, 0x40, 0x48, 0x48, 0x58, 0x60, 0x60, 0x60,
++    0x68, 0x68, 0x58, 0x68, 0x60, 0x60, 0x60, 0x68, 0x68, 0x68, 0x60, 0x50, 0x48, 0x50, 0x58, 0x60,
++    0x60, 0x60, 0x68, 0x68, 0x58, 0x68, 0x60, 0x60, 0x60, 0x68, 0x68, 0x68, 0x60, 0x50, 0x48, 0x50,
++    0x07, 0x50, 0x58, 0x40, 0x48, 0x40, 0x48, 0x07, 0x48, 0x48, 0x48, 0x68, 0x07, 0x1f, 0x17, 0x50,
++    0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x40,
++    0x07, 0x48, 0x48, 0x48, 0x07, 0x48, 0x07, 0x17, 0x17, 0x17, 0x50, 0x17, 0x17, 0x50, 0x40, 0x40,
++    0x40, 0x2f, 0x2f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x1f, 0x27, 0x0f, 0x07, 0x07, 0x0f, 0x07,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x07, 0x1f, 0x48, 0x17, 0x48, 0x40, 0x48, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x07, 0x47, 0x47, 0x5f, 0x40, 0x27, 0x07, 0x07, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f,
++    0x47, 0x66, 0x5f, 0x00, 0x66, 0x66, 0x66, 0x65, 0x65, 0x07, 0x07, 0x0f, 0x4f, 0x00, 0x5e, 0x07,
++    0x67, 0x27, 0x47, 0x17, 0x40, 0x4f, 0x1f, 0x40, 0x40, 0x40, 0x47, 0x47, 0x57, 0x5f, 0x5e, 0x5f,
++    0x66, 0x66, 0x57, 0x67, 0x5f, 0x5e, 0x5f, 0x67, 0x67, 0x66, 0x5e, 0x4f, 0x47, 0x4f, 0x57, 0x5f,
++    0x5e, 0x5f, 0x66, 0x66, 0x57, 0x67, 0x5f, 0x5e, 0x5f, 0x67, 0x67, 0x66, 0x5e, 0x4f, 0x47, 0x4f,
++    0x08, 0x4f, 0x56, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x47, 0x47, 0x66, 0x07, 0x1f, 0x17, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x47, 0x47, 0x47, 0x08, 0x47, 0x08, 0x17, 0x17, 0x17, 0x4f, 0x17, 0x17, 0x4f, 0x40, 0x40,
++    0x40, 0x2f, 0x2f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x20, 0x27, 0x10, 0x07, 0x08, 0x10, 0x08,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1f, 0x47, 0x17, 0x46, 0x00, 0x47, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x06, 0x46, 0x47, 0x5e, 0x40, 0x26, 0x06, 0x06, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f,
++    0x47, 0x64, 0x5e, 0x01, 0x65, 0x64, 0x64, 0x63, 0x63, 0x07, 0x07, 0x0f, 0x4e, 0x00, 0x5d, 0x07,
++    0x66, 0x27, 0x46, 0x17, 0x40, 0x4f, 0x1e, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5e, 0x5d, 0x5e,
++    0x65, 0x64, 0x56, 0x66, 0x5e, 0x5c, 0x5e, 0x66, 0x66, 0x65, 0x5d, 0x4e, 0x46, 0x4e, 0x56, 0x5e,
++    0x5d, 0x5e, 0x65, 0x64, 0x56, 0x66, 0x5e, 0x5c, 0x5e, 0x66, 0x66, 0x65, 0x5d, 0x4e, 0x46, 0x4e,
++    0x09, 0x4f, 0x54, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x64, 0x07, 0x1f, 0x16, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x46, 0x46, 0x46, 0x09, 0x46, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40,
++    0x40, 0x2e, 0x2e, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x08,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1e, 0x46, 0x17, 0x45, 0x01, 0x46, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x06, 0x45, 0x47, 0x5e, 0x40, 0x25, 0x06, 0x05, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f,
++    0x47, 0x63, 0x5d, 0x01, 0x64, 0x63, 0x62, 0x60, 0x60, 0x07, 0x07, 0x0f, 0x4e, 0x00, 0x5c, 0x07,
++    0x65, 0x27, 0x45, 0x17, 0x40, 0x4f, 0x1d, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5d, 0x5c, 0x5d,
++    0x64, 0x63, 0x56, 0x65, 0x5d, 0x5b, 0x5d, 0x65, 0x65, 0x64, 0x5c, 0x4d, 0x46, 0x4d, 0x56, 0x5d,
++    0x5c, 0x5d, 0x64, 0x63, 0x56, 0x65, 0x5d, 0x5b, 0x5d, 0x65, 0x65, 0x64, 0x5c, 0x4d, 0x46, 0x4d,
++    0x09, 0x4f, 0x52, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x62, 0x07, 0x1f, 0x16, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x46, 0x46, 0x45, 0x09, 0x45, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40,
++    0x40, 0x2d, 0x2d, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x08,
++    0x07, 0x3d, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1e, 0x45, 0x17, 0x44, 0x01, 0x45, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x05, 0x44, 0x46, 0x5d, 0x40, 0x24, 0x05, 0x04, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f,
++    0x46, 0x61, 0x5c, 0x02, 0x63, 0x61, 0x60, 0x5e, 0x5e, 0x07, 0x07, 0x0e, 0x4d, 0x01, 0x5b, 0x07,
++    0x64, 0x27, 0x44, 0x16, 0x40, 0x4e, 0x1c, 0x40, 0x40, 0x40, 0x46, 0x46, 0x55, 0x5c, 0x5b, 0x5c,
++    0x63, 0x61, 0x55, 0x64, 0x5c, 0x59, 0x5c, 0x64, 0x64, 0x63, 0x5b, 0x4c, 0x45, 0x4c, 0x55, 0x5c,
++    0x5b, 0x5c, 0x63, 0x61, 0x55, 0x64, 0x5c, 0x59, 0x5c, 0x64, 0x64, 0x63, 0x5b, 0x4c, 0x45, 0x4c,
++    0x0a, 0x4e, 0x50, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x45, 0x45, 0x60, 0x07, 0x1e, 0x15, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x45, 0x45, 0x44, 0x0a, 0x44, 0x0a, 0x16, 0x17, 0x15, 0x4e, 0x17, 0x15, 0x4e, 0x40, 0x40,
++    0x40, 0x2c, 0x2c, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x1d, 0x21, 0x27, 0x11, 0x07, 0x0a, 0x11, 0x09,
++    0x06, 0x3c, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1d, 0x44, 0x16, 0x43, 0x02, 0x44, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x04, 0x43, 0x46, 0x5c, 0x40, 0x23, 0x04, 0x03, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f,
++    0x46, 0x60, 0x5b, 0x03, 0x61, 0x60, 0x5e, 0x5b, 0x5b, 0x07, 0x07, 0x0e, 0x4c, 0x01, 0x59, 0x07,
++    0x63, 0x27, 0x43, 0x16, 0x40, 0x4e, 0x1b, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5b, 0x59, 0x5b,
++    0x61, 0x60, 0x54, 0x63, 0x5b, 0x58, 0x5b, 0x63, 0x63, 0x61, 0x59, 0x4b, 0x44, 0x4b, 0x54, 0x5b,
++    0x59, 0x5b, 0x61, 0x60, 0x54, 0x63, 0x5b, 0x58, 0x5b, 0x63, 0x63, 0x61, 0x59, 0x4b, 0x44, 0x4b,
++    0x0b, 0x4e, 0x4e, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5e, 0x07, 0x1e, 0x14, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x44, 0x44, 0x43, 0x0b, 0x43, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40,
++    0x40, 0x2b, 0x2b, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x09,
++    0x06, 0x3b, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1c, 0x43, 0x16, 0x41, 0x03, 0x43, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x04, 0x42, 0x46, 0x5c, 0x40, 0x22, 0x04, 0x02, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f,
++    0x46, 0x5e, 0x5a, 0x03, 0x60, 0x5e, 0x5c, 0x59, 0x59, 0x07, 0x07, 0x0e, 0x4c, 0x01, 0x58, 0x07,
++    0x62, 0x27, 0x42, 0x16, 0x40, 0x4e, 0x1a, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5a, 0x58, 0x5a,
++    0x60, 0x5e, 0x54, 0x62, 0x5a, 0x56, 0x5a, 0x62, 0x62, 0x60, 0x58, 0x4a, 0x44, 0x4a, 0x54, 0x5a,
++    0x58, 0x5a, 0x60, 0x5e, 0x54, 0x62, 0x5a, 0x56, 0x5a, 0x62, 0x62, 0x60, 0x58, 0x4a, 0x44, 0x4a,
++    0x0b, 0x4e, 0x4c, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5c, 0x07, 0x1e, 0x14, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x44, 0x44, 0x42, 0x0b, 0x42, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40,
++    0x40, 0x2a, 0x2a, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x09,
++    0x06, 0x3a, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1c, 0x42, 0x16, 0x40, 0x03, 0x42, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x03, 0x41, 0x45, 0x5b, 0x40, 0x21, 0x03, 0x01, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f,
++    0x45, 0x5d, 0x59, 0x04, 0x5f, 0x5d, 0x5a, 0x56, 0x56, 0x07, 0x07, 0x0d, 0x4b, 0x02, 0x57, 0x07,
++    0x61, 0x27, 0x41, 0x15, 0x40, 0x4d, 0x19, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x59, 0x57, 0x59,
++    0x5f, 0x5d, 0x53, 0x61, 0x59, 0x55, 0x59, 0x61, 0x61, 0x5f, 0x57, 0x49, 0x43, 0x49, 0x53, 0x59,
++    0x57, 0x59, 0x5f, 0x5d, 0x53, 0x61, 0x59, 0x55, 0x59, 0x61, 0x61, 0x5f, 0x57, 0x49, 0x43, 0x49,
++    0x0c, 0x4d, 0x4a, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x5a, 0x07, 0x1d, 0x13, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x43, 0x43, 0x41, 0x0c, 0x41, 0x0c, 0x15, 0x17, 0x13, 0x4d, 0x17, 0x13, 0x4d, 0x40, 0x40,
++    0x40, 0x29, 0x29, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x1b, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x0a,
++    0x05, 0x39, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1b, 0x41, 0x15, 0x00, 0x04, 0x41, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x02, 0x40, 0x45, 0x5b, 0x40, 0x20, 0x02, 0x00, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f,
++    0x45, 0x5b, 0x58, 0x04, 0x5e, 0x5b, 0x59, 0x54, 0x54, 0x07, 0x07, 0x0d, 0x4b, 0x02, 0x56, 0x07,
++    0x60, 0x27, 0x40, 0x15, 0x40, 0x4d, 0x18, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x58, 0x56, 0x58,
++    0x5e, 0x5b, 0x53, 0x60, 0x58, 0x53, 0x58, 0x60, 0x60, 0x5e, 0x56, 0x48, 0x43, 0x48, 0x53, 0x58,
++    0x56, 0x58, 0x5e, 0x5b, 0x53, 0x60, 0x58, 0x53, 0x58, 0x60, 0x60, 0x5e, 0x56, 0x48, 0x43, 0x48,
++    0x0c, 0x4d, 0x49, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x59, 0x07, 0x1d, 0x12, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x43, 0x43, 0x40, 0x0c, 0x40, 0x0c, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40,
++    0x40, 0x28, 0x28, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x0a,
++    0x05, 0x38, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1a, 0x40, 0x15, 0x01, 0x04, 0x40, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x02, 0x00, 0x45, 0x5a, 0x40, 0x1f, 0x02, 0x40, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f,
++    0x45, 0x59, 0x57, 0x05, 0x5c, 0x59, 0x57, 0x51, 0x51, 0x07, 0x07, 0x0d, 0x4a, 0x02, 0x54, 0x07,
++    0x5f, 0x27, 0x00, 0x15, 0x40, 0x4d, 0x17, 0x40, 0x40, 0x40, 0x45, 0x45, 0x52, 0x57, 0x54, 0x57,
++    0x5c, 0x59, 0x52, 0x5f, 0x57, 0x51, 0x57, 0x5f, 0x5f, 0x5c, 0x54, 0x47, 0x42, 0x47, 0x52, 0x57,
++    0x54, 0x57, 0x5c, 0x59, 0x52, 0x5f, 0x57, 0x51, 0x57, 0x5f, 0x5f, 0x5c, 0x54, 0x47, 0x42, 0x47,
++    0x0d, 0x4d, 0x47, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x42, 0x42, 0x57, 0x07, 0x1d, 0x12, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x42, 0x42, 0x00, 0x0d, 0x00, 0x0d, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40,
++    0x40, 0x27, 0x27, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0d, 0x12, 0x0a,
++    0x05, 0x37, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1a, 0x00, 0x15, 0x03, 0x05, 0x00, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x01, 0x01, 0x44, 0x59, 0x40, 0x1e, 0x01, 0x41, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f,
++    0x44, 0x58, 0x56, 0x06, 0x5b, 0x58, 0x55, 0x4f, 0x4f, 0x07, 0x07, 0x0c, 0x49, 0x03, 0x53, 0x07,
++    0x5e, 0x27, 0x01, 0x14, 0x40, 0x4c, 0x16, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x56, 0x53, 0x56,
++    0x5b, 0x58, 0x51, 0x5e, 0x56, 0x50, 0x56, 0x5e, 0x5e, 0x5b, 0x53, 0x46, 0x41, 0x46, 0x51, 0x56,
++    0x53, 0x56, 0x5b, 0x58, 0x51, 0x5e, 0x56, 0x50, 0x56, 0x5e, 0x5e, 0x5b, 0x53, 0x46, 0x41, 0x46,
++    0x0e, 0x4c, 0x45, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x55, 0x07, 0x1c, 0x11, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x41, 0x41, 0x01, 0x0e, 0x01, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40,
++    0x40, 0x26, 0x26, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x0b,
++    0x04, 0x36, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x19, 0x01, 0x14, 0x04, 0x06, 0x01, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x01, 0x02, 0x44, 0x59, 0x40, 0x1d, 0x01, 0x42, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f,
++    0x44, 0x56, 0x55, 0x06, 0x5a, 0x56, 0x53, 0x4c, 0x4c, 0x07, 0x07, 0x0c, 0x49, 0x03, 0x52, 0x07,
++    0x5d, 0x27, 0x02, 0x14, 0x40, 0x4c, 0x15, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x55, 0x52, 0x55,
++    0x5a, 0x56, 0x51, 0x5d, 0x55, 0x4e, 0x55, 0x5d, 0x5d, 0x5a, 0x52, 0x45, 0x41, 0x45, 0x51, 0x55,
++    0x52, 0x55, 0x5a, 0x56, 0x51, 0x5d, 0x55, 0x4e, 0x55, 0x5d, 0x5d, 0x5a, 0x52, 0x45, 0x41, 0x45,
++    0x0e, 0x4c, 0x43, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x53, 0x07, 0x1c, 0x11, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x41, 0x41, 0x02, 0x0e, 0x02, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40,
++    0x40, 0x25, 0x25, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x0b,
++    0x04, 0x35, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x19, 0x02, 0x14, 0x05, 0x06, 0x02, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x00, 0x03, 0x44, 0x58, 0x40, 0x1c, 0x00, 0x43, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f,
++    0x44, 0x55, 0x54, 0x07, 0x59, 0x55, 0x51, 0x4a, 0x4a, 0x07, 0x07, 0x0c, 0x48, 0x03, 0x51, 0x07,
++    0x5c, 0x27, 0x03, 0x14, 0x40, 0x4c, 0x14, 0x40, 0x40, 0x40, 0x44, 0x44, 0x50, 0x54, 0x51, 0x54,
++    0x59, 0x55, 0x50, 0x5c, 0x54, 0x4d, 0x54, 0x5c, 0x5c, 0x59, 0x51, 0x44, 0x40, 0x44, 0x50, 0x54,
++    0x51, 0x54, 0x59, 0x55, 0x50, 0x5c, 0x54, 0x4d, 0x54, 0x5c, 0x5c, 0x59, 0x51, 0x44, 0x40, 0x44,
++    0x0f, 0x4c, 0x41, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x40, 0x40, 0x51, 0x07, 0x1c, 0x10, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x40, 0x40, 0x03, 0x0f, 0x03, 0x0f, 0x14, 0x17, 0x10, 0x4c, 0x17, 0x10, 0x4c, 0x40, 0x40,
++    0x40, 0x24, 0x24, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x18, 0x23, 0x27, 0x13, 0x07, 0x0f, 0x13, 0x0b,
++    0x04, 0x34, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x18, 0x03, 0x14, 0x06, 0x07, 0x03, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x40, 0x04, 0x43, 0x57, 0x40, 0x1b, 0x40, 0x44, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f,
++    0x43, 0x53, 0x53, 0x08, 0x57, 0x53, 0x4f, 0x47, 0x47, 0x07, 0x07, 0x0b, 0x47, 0x04, 0x4f, 0x07,
++    0x5b, 0x27, 0x04, 0x13, 0x40, 0x4b, 0x13, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x53, 0x4f, 0x53,
++    0x57, 0x53, 0x4f, 0x5b, 0x53, 0x4b, 0x53, 0x5b, 0x5b, 0x57, 0x4f, 0x43, 0x00, 0x43, 0x4f, 0x53,
++    0x4f, 0x53, 0x57, 0x53, 0x4f, 0x5b, 0x53, 0x4b, 0x53, 0x5b, 0x5b, 0x57, 0x4f, 0x43, 0x00, 0x43,
++    0x10, 0x4b, 0x00, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4f, 0x07, 0x1b, 0x0f, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x00, 0x00, 0x04, 0x10, 0x04, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40,
++    0x40, 0x23, 0x23, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x0c,
++    0x03, 0x33, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x17, 0x04, 0x13, 0x08, 0x08, 0x04, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x40, 0x05, 0x43, 0x57, 0x40, 0x1a, 0x40, 0x45, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f,
++    0x43, 0x52, 0x52, 0x08, 0x56, 0x52, 0x4d, 0x45, 0x45, 0x07, 0x07, 0x0b, 0x47, 0x04, 0x4e, 0x07,
++    0x5a, 0x27, 0x05, 0x13, 0x40, 0x4b, 0x12, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x52, 0x4e, 0x52,
++    0x56, 0x52, 0x4f, 0x5a, 0x52, 0x4a, 0x52, 0x5a, 0x5a, 0x56, 0x4e, 0x42, 0x00, 0x42, 0x4f, 0x52,
++    0x4e, 0x52, 0x56, 0x52, 0x4f, 0x5a, 0x52, 0x4a, 0x52, 0x5a, 0x5a, 0x56, 0x4e, 0x42, 0x00, 0x42,
++    0x10, 0x4b, 0x02, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4d, 0x07, 0x1b, 0x0f, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x00, 0x00, 0x05, 0x10, 0x05, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40,
++    0x40, 0x22, 0x22, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x0c,
++    0x03, 0x32, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x17, 0x05, 0x13, 0x09, 0x08, 0x05, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x41, 0x06, 0x43, 0x56, 0x40, 0x19, 0x41, 0x46, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f,
++    0x43, 0x50, 0x51, 0x09, 0x55, 0x50, 0x4b, 0x42, 0x42, 0x07, 0x07, 0x0b, 0x46, 0x04, 0x4d, 0x07,
++    0x59, 0x27, 0x06, 0x13, 0x40, 0x4b, 0x11, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x4d, 0x51,
++    0x55, 0x50, 0x4e, 0x59, 0x51, 0x48, 0x51, 0x59, 0x59, 0x55, 0x4d, 0x41, 0x01, 0x41, 0x4e, 0x51,
++    0x4d, 0x51, 0x55, 0x50, 0x4e, 0x59, 0x51, 0x48, 0x51, 0x59, 0x59, 0x55, 0x4d, 0x41, 0x01, 0x41,
++    0x11, 0x4b, 0x04, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4b, 0x07, 0x1b, 0x0e, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x01, 0x01, 0x06, 0x11, 0x06, 0x11, 0x13, 0x17, 0x0e, 0x4b, 0x17, 0x0e, 0x4b, 0x40, 0x40,
++    0x40, 0x21, 0x21, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x16, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x0c,
++    0x03, 0x31, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x16, 0x06, 0x13, 0x0a, 0x09, 0x06, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x42, 0x06, 0x43, 0x56, 0x40, 0x18, 0x42, 0x47, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f,
++    0x43, 0x4f, 0x51, 0x09, 0x54, 0x4f, 0x4a, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x46, 0x04, 0x4c, 0x07,
++    0x59, 0x27, 0x06, 0x12, 0x40, 0x4b, 0x10, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x4c, 0x51,
++    0x54, 0x4f, 0x4e, 0x59, 0x51, 0x47, 0x51, 0x59, 0x59, 0x54, 0x4c, 0x41, 0x01, 0x41, 0x4e, 0x51,
++    0x4c, 0x51, 0x54, 0x4f, 0x4e, 0x59, 0x51, 0x47, 0x51, 0x59, 0x59, 0x54, 0x4c, 0x41, 0x01, 0x41,
++    0x11, 0x4b, 0x05, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4a, 0x07, 0x1a, 0x0d, 0x4b,
++    0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x45,
++    0x07, 0x01, 0x01, 0x06, 0x11, 0x06, 0x11, 0x12, 0x17, 0x0d, 0x4b, 0x17, 0x0d, 0x4b, 0x40, 0x40,
++    0x40, 0x20, 0x20, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x0c,
++    0x02, 0x30, 0x1a, 0x12, 0x40, 0x12, 0x0c, 0x15, 0x06, 0x12, 0x0b, 0x09, 0x06, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x42, 0x07, 0x42, 0x55, 0x40, 0x18, 0x42, 0x47, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f,
++    0x42, 0x4d, 0x50, 0x0a, 0x52, 0x4d, 0x48, 0x02, 0x02, 0x07, 0x07, 0x0a, 0x45, 0x05, 0x4a, 0x07,
++    0x58, 0x27, 0x07, 0x12, 0x40, 0x4a, 0x10, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4d, 0x50, 0x4a, 0x50,
++    0x52, 0x4d, 0x4d, 0x58, 0x50, 0x45, 0x50, 0x58, 0x58, 0x52, 0x4a, 0x40, 0x02, 0x40, 0x4d, 0x50,
++    0x4a, 0x50, 0x52, 0x4d, 0x4d, 0x58, 0x50, 0x45, 0x50, 0x58, 0x58, 0x52, 0x4a, 0x40, 0x02, 0x40,
++    0x12, 0x4a, 0x07, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x02, 0x02, 0x48, 0x07, 0x1a, 0x0d, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x02, 0x02, 0x07, 0x12, 0x07, 0x12, 0x12, 0x17, 0x0d, 0x4a, 0x17, 0x0d, 0x4a, 0x40, 0x40,
++    0x40, 0x20, 0x20, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x25, 0x27, 0x15, 0x07, 0x12, 0x15, 0x0d,
++    0x02, 0x30, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x15, 0x07, 0x12, 0x0d, 0x0a, 0x07, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x43, 0x08, 0x42, 0x54, 0x40, 0x17, 0x43, 0x48, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f,
++    0x42, 0x4b, 0x4f, 0x0b, 0x51, 0x4b, 0x46, 0x04, 0x04, 0x07, 0x07, 0x0a, 0x44, 0x05, 0x49, 0x07,
++    0x57, 0x27, 0x08, 0x12, 0x40, 0x4a, 0x0f, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4f, 0x49, 0x4f,
++    0x51, 0x4b, 0x4c, 0x57, 0x4f, 0x43, 0x4f, 0x57, 0x57, 0x51, 0x49, 0x00, 0x03, 0x00, 0x4c, 0x4f,
++    0x49, 0x4f, 0x51, 0x4b, 0x4c, 0x57, 0x4f, 0x43, 0x4f, 0x57, 0x57, 0x51, 0x49, 0x00, 0x03, 0x00,
++    0x13, 0x4a, 0x09, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x46, 0x07, 0x1a, 0x0c, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x03, 0x03, 0x08, 0x13, 0x08, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40,
++    0x40, 0x1f, 0x1f, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0d,
++    0x02, 0x2f, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x14, 0x08, 0x12, 0x0e, 0x0b, 0x08, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x43, 0x09, 0x42, 0x54, 0x40, 0x16, 0x43, 0x49, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f,
++    0x42, 0x4a, 0x4e, 0x0b, 0x50, 0x4a, 0x44, 0x07, 0x07, 0x07, 0x07, 0x0a, 0x44, 0x05, 0x48, 0x07,
++    0x56, 0x27, 0x09, 0x12, 0x40, 0x4a, 0x0e, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4e, 0x48, 0x4e,
++    0x50, 0x4a, 0x4c, 0x56, 0x4e, 0x42, 0x4e, 0x56, 0x56, 0x50, 0x48, 0x01, 0x03, 0x01, 0x4c, 0x4e,
++    0x48, 0x4e, 0x50, 0x4a, 0x4c, 0x56, 0x4e, 0x42, 0x4e, 0x56, 0x56, 0x50, 0x48, 0x01, 0x03, 0x01,
++    0x13, 0x4a, 0x0b, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x44, 0x07, 0x1a, 0x0c, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x03, 0x03, 0x09, 0x13, 0x09, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40,
++    0x40, 0x1e, 0x1e, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0d,
++    0x02, 0x2e, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x14, 0x09, 0x12, 0x0f, 0x0b, 0x09, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x44, 0x0a, 0x41, 0x53, 0x40, 0x15, 0x44, 0x4a, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f,
++    0x41, 0x48, 0x4d, 0x0c, 0x4f, 0x48, 0x42, 0x09, 0x09, 0x07, 0x07, 0x09, 0x43, 0x06, 0x47, 0x07,
++    0x55, 0x27, 0x0a, 0x11, 0x40, 0x49, 0x0d, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4d, 0x47, 0x4d,
++    0x4f, 0x48, 0x4b, 0x55, 0x4d, 0x40, 0x4d, 0x55, 0x55, 0x4f, 0x47, 0x02, 0x04, 0x02, 0x4b, 0x4d,
++    0x47, 0x4d, 0x4f, 0x48, 0x4b, 0x55, 0x4d, 0x40, 0x4d, 0x55, 0x55, 0x4f, 0x47, 0x02, 0x04, 0x02,
++    0x14, 0x49, 0x0d, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x04, 0x04, 0x42, 0x07, 0x19, 0x0b, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x04, 0x04, 0x0a, 0x14, 0x0a, 0x14, 0x11, 0x17, 0x0b, 0x49, 0x17, 0x0b, 0x49, 0x40, 0x40,
++    0x40, 0x1d, 0x1d, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x13, 0x26, 0x27, 0x16, 0x07, 0x14, 0x16, 0x0e,
++    0x01, 0x2d, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x13, 0x0a, 0x11, 0x10, 0x0c, 0x0a, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x45, 0x0b, 0x41, 0x52, 0x40, 0x14, 0x45, 0x4b, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f,
++    0x41, 0x47, 0x4c, 0x0d, 0x4d, 0x47, 0x40, 0x0c, 0x0c, 0x07, 0x07, 0x09, 0x42, 0x06, 0x45, 0x07,
++    0x54, 0x27, 0x0b, 0x11, 0x40, 0x49, 0x0c, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4c, 0x45, 0x4c,
++    0x4d, 0x47, 0x4a, 0x54, 0x4c, 0x00, 0x4c, 0x54, 0x54, 0x4d, 0x45, 0x03, 0x05, 0x03, 0x4a, 0x4c,
++    0x45, 0x4c, 0x4d, 0x47, 0x4a, 0x54, 0x4c, 0x00, 0x4c, 0x54, 0x54, 0x4d, 0x45, 0x03, 0x05, 0x03,
++    0x15, 0x49, 0x0f, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x40, 0x07, 0x19, 0x0a, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x05, 0x05, 0x0b, 0x15, 0x0b, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40,
++    0x40, 0x1c, 0x1c, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0e,
++    0x01, 0x2c, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x12, 0x0b, 0x11, 0x12, 0x0d, 0x0b, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x45, 0x0c, 0x41, 0x52, 0x40, 0x13, 0x45, 0x4c, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f,
++    0x41, 0x45, 0x4b, 0x0d, 0x4c, 0x45, 0x01, 0x0e, 0x0e, 0x07, 0x07, 0x09, 0x42, 0x06, 0x44, 0x07,
++    0x53, 0x27, 0x0c, 0x11, 0x40, 0x49, 0x0b, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4b, 0x44, 0x4b,
++    0x4c, 0x45, 0x4a, 0x53, 0x4b, 0x02, 0x4b, 0x53, 0x53, 0x4c, 0x44, 0x04, 0x05, 0x04, 0x4a, 0x4b,
++    0x44, 0x4b, 0x4c, 0x45, 0x4a, 0x53, 0x4b, 0x02, 0x4b, 0x53, 0x53, 0x4c, 0x44, 0x04, 0x05, 0x04,
++    0x15, 0x49, 0x11, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x01, 0x07, 0x19, 0x0a, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x05, 0x05, 0x0c, 0x15, 0x0c, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40,
++    0x40, 0x1b, 0x1b, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0e,
++    0x01, 0x2b, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x12, 0x0c, 0x11, 0x13, 0x0d, 0x0c, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x46, 0x0d, 0x40, 0x51, 0x40, 0x12, 0x46, 0x4d, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f,
++    0x40, 0x44, 0x4a, 0x0e, 0x4b, 0x44, 0x03, 0x11, 0x11, 0x07, 0x07, 0x08, 0x41, 0x07, 0x43, 0x07,
++    0x52, 0x27, 0x0d, 0x10, 0x40, 0x48, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x4a, 0x43, 0x4a,
++    0x4b, 0x44, 0x49, 0x52, 0x4a, 0x03, 0x4a, 0x52, 0x52, 0x4b, 0x43, 0x05, 0x06, 0x05, 0x49, 0x4a,
++    0x43, 0x4a, 0x4b, 0x44, 0x49, 0x52, 0x4a, 0x03, 0x4a, 0x52, 0x52, 0x4b, 0x43, 0x05, 0x06, 0x05,
++    0x16, 0x48, 0x13, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x03, 0x07, 0x18, 0x09, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x06, 0x06, 0x0d, 0x16, 0x0d, 0x16, 0x10, 0x17, 0x09, 0x48, 0x17, 0x09, 0x48, 0x40, 0x40,
++    0x40, 0x1a, 0x1a, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x11, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0f,
++    0x00, 0x2a, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x11, 0x0d, 0x10, 0x14, 0x0e, 0x0d, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x47, 0x0e, 0x40, 0x51, 0x40, 0x11, 0x47, 0x4e, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f,
++    0x40, 0x42, 0x49, 0x0e, 0x4a, 0x42, 0x04, 0x13, 0x13, 0x07, 0x07, 0x08, 0x41, 0x07, 0x42, 0x07,
++    0x51, 0x27, 0x0e, 0x10, 0x40, 0x48, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x42, 0x49,
++    0x4a, 0x42, 0x49, 0x51, 0x49, 0x05, 0x49, 0x51, 0x51, 0x4a, 0x42, 0x06, 0x06, 0x06, 0x49, 0x49,
++    0x42, 0x49, 0x4a, 0x42, 0x49, 0x51, 0x49, 0x05, 0x49, 0x51, 0x51, 0x4a, 0x42, 0x06, 0x06, 0x06,
++    0x16, 0x48, 0x14, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x04, 0x07, 0x18, 0x08, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x06, 0x06, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40,
++    0x40, 0x19, 0x19, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0f,
++    0x00, 0x29, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x10, 0x0e, 0x10, 0x15, 0x0e, 0x0e, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x47, 0x0f, 0x40, 0x50, 0x40, 0x10, 0x47, 0x4f, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f,
++    0x40, 0x40, 0x48, 0x0f, 0x48, 0x40, 0x06, 0x16, 0x16, 0x07, 0x07, 0x08, 0x40, 0x07, 0x40, 0x07,
++    0x50, 0x27, 0x0f, 0x10, 0x40, 0x48, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48,
++    0x48, 0x40, 0x48, 0x50, 0x48, 0x07, 0x48, 0x50, 0x50, 0x48, 0x40, 0x07, 0x07, 0x07, 0x48, 0x48,
++    0x40, 0x48, 0x48, 0x40, 0x48, 0x50, 0x48, 0x07, 0x48, 0x50, 0x50, 0x48, 0x40, 0x07, 0x07, 0x07,
++    0x17, 0x48, 0x16, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x07, 0x07, 0x06, 0x07, 0x18, 0x08, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x07, 0x07, 0x0f, 0x17, 0x0f, 0x17, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40,
++    0x40, 0x18, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x17, 0x17, 0x0f,
++    0x00, 0x28, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x10, 0x0f, 0x10, 0x17, 0x0f, 0x0f, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x48, 0x10, 0x00, 0x4f, 0x40, 0x0f, 0x48, 0x50, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f,
++    0x00, 0x00, 0x47, 0x10, 0x47, 0x00, 0x08, 0x18, 0x18, 0x07, 0x07, 0x07, 0x00, 0x08, 0x00, 0x07,
++    0x4f, 0x27, 0x10, 0x0f, 0x40, 0x47, 0x07, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47,
++    0x47, 0x00, 0x47, 0x4f, 0x47, 0x08, 0x47, 0x4f, 0x4f, 0x47, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47,
++    0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x47, 0x08, 0x47, 0x4f, 0x4f, 0x47, 0x00, 0x08, 0x08, 0x08,
++    0x18, 0x47, 0x18, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x08, 0x07, 0x17, 0x07, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40,
++    0x40, 0x17, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10,
++    0x40, 0x27, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0f, 0x10, 0x0f, 0x18, 0x10, 0x10, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x48, 0x11, 0x00, 0x4f, 0x40, 0x0e, 0x48, 0x51, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f,
++    0x00, 0x02, 0x46, 0x10, 0x46, 0x02, 0x0a, 0x1b, 0x1b, 0x07, 0x07, 0x07, 0x00, 0x08, 0x01, 0x07,
++    0x4e, 0x27, 0x11, 0x0f, 0x40, 0x47, 0x06, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x46, 0x01, 0x46,
++    0x46, 0x02, 0x47, 0x4e, 0x46, 0x0a, 0x46, 0x4e, 0x4e, 0x46, 0x01, 0x09, 0x08, 0x09, 0x47, 0x46,
++    0x01, 0x46, 0x46, 0x02, 0x47, 0x4e, 0x46, 0x0a, 0x46, 0x4e, 0x4e, 0x46, 0x01, 0x09, 0x08, 0x09,
++    0x18, 0x47, 0x1a, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x0a, 0x07, 0x17, 0x07, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x08, 0x08, 0x11, 0x18, 0x11, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40,
++    0x40, 0x16, 0x16, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10,
++    0x40, 0x26, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0f, 0x11, 0x0f, 0x19, 0x10, 0x11, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x49, 0x12, 0x00, 0x4e, 0x40, 0x0d, 0x49, 0x52, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f,
++    0x00, 0x03, 0x45, 0x11, 0x45, 0x03, 0x0c, 0x1d, 0x1d, 0x07, 0x07, 0x07, 0x01, 0x08, 0x02, 0x07,
++    0x4d, 0x27, 0x12, 0x0f, 0x40, 0x47, 0x05, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x45, 0x02, 0x45,
++    0x45, 0x03, 0x46, 0x4d, 0x45, 0x0b, 0x45, 0x4d, 0x4d, 0x45, 0x02, 0x0a, 0x09, 0x0a, 0x46, 0x45,
++    0x02, 0x45, 0x45, 0x03, 0x46, 0x4d, 0x45, 0x0b, 0x45, 0x4d, 0x4d, 0x45, 0x02, 0x0a, 0x09, 0x0a,
++    0x19, 0x47, 0x1c, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x09, 0x09, 0x0c, 0x07, 0x17, 0x06, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x09, 0x09, 0x12, 0x19, 0x12, 0x19, 0x0f, 0x17, 0x06, 0x47, 0x17, 0x06, 0x47, 0x40, 0x40,
++    0x40, 0x15, 0x15, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x0e, 0x28, 0x27, 0x18, 0x07, 0x19, 0x18, 0x10,
++    0x40, 0x25, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0e, 0x12, 0x0f, 0x1a, 0x11, 0x12, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4a, 0x13, 0x01, 0x4d, 0x40, 0x0c, 0x4a, 0x53, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f,
++    0x01, 0x05, 0x44, 0x12, 0x43, 0x05, 0x0e, 0x20, 0x20, 0x07, 0x07, 0x06, 0x02, 0x09, 0x04, 0x07,
++    0x4c, 0x27, 0x13, 0x0e, 0x40, 0x46, 0x04, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x44, 0x04, 0x44,
++    0x43, 0x05, 0x45, 0x4c, 0x44, 0x0d, 0x44, 0x4c, 0x4c, 0x43, 0x04, 0x0b, 0x0a, 0x0b, 0x45, 0x44,
++    0x04, 0x44, 0x43, 0x05, 0x45, 0x4c, 0x44, 0x0d, 0x44, 0x4c, 0x4c, 0x43, 0x04, 0x0b, 0x0a, 0x0b,
++    0x1a, 0x46, 0x1e, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x0e, 0x07, 0x16, 0x05, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x0a, 0x0a, 0x13, 0x1a, 0x13, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40,
++    0x40, 0x14, 0x14, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x11,
++    0x41, 0x24, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0d, 0x13, 0x0e, 0x1c, 0x12, 0x13, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4a, 0x14, 0x01, 0x4d, 0x40, 0x0b, 0x4a, 0x54, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f,
++    0x01, 0x06, 0x43, 0x12, 0x42, 0x06, 0x10, 0x22, 0x22, 0x07, 0x07, 0x06, 0x02, 0x09, 0x05, 0x07,
++    0x4b, 0x27, 0x14, 0x0e, 0x40, 0x46, 0x03, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x43, 0x05, 0x43,
++    0x42, 0x06, 0x45, 0x4b, 0x43, 0x0e, 0x43, 0x4b, 0x4b, 0x42, 0x05, 0x0c, 0x0a, 0x0c, 0x45, 0x43,
++    0x05, 0x43, 0x42, 0x06, 0x45, 0x4b, 0x43, 0x0e, 0x43, 0x4b, 0x4b, 0x42, 0x05, 0x0c, 0x0a, 0x0c,
++    0x1a, 0x46, 0x20, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x10, 0x07, 0x16, 0x05, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x0a, 0x0a, 0x14, 0x1a, 0x14, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40,
++    0x40, 0x13, 0x13, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x11,
++    0x41, 0x23, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0d, 0x14, 0x0e, 0x1d, 0x12, 0x14, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4b, 0x15, 0x01, 0x4c, 0x40, 0x0a, 0x4b, 0x55, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f,
++    0x01, 0x08, 0x42, 0x13, 0x41, 0x08, 0x12, 0x25, 0x25, 0x07, 0x07, 0x06, 0x03, 0x09, 0x06, 0x07,
++    0x4a, 0x27, 0x15, 0x0e, 0x40, 0x46, 0x02, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x06, 0x42,
++    0x41, 0x08, 0x44, 0x4a, 0x42, 0x10, 0x42, 0x4a, 0x4a, 0x41, 0x06, 0x0d, 0x0b, 0x0d, 0x44, 0x42,
++    0x06, 0x42, 0x41, 0x08, 0x44, 0x4a, 0x42, 0x10, 0x42, 0x4a, 0x4a, 0x41, 0x06, 0x0d, 0x0b, 0x0d,
++    0x1b, 0x46, 0x22, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x12, 0x07, 0x16, 0x04, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x0b, 0x0b, 0x15, 0x1b, 0x15, 0x1b, 0x0e, 0x17, 0x04, 0x46, 0x17, 0x04, 0x46, 0x40, 0x40,
++    0x40, 0x12, 0x12, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x0c, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x11,
++    0x41, 0x22, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0c, 0x15, 0x0e, 0x1e, 0x13, 0x15, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4c, 0x15, 0x01, 0x4c, 0x40, 0x09, 0x4c, 0x56, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f,
++    0x01, 0x09, 0x42, 0x13, 0x40, 0x09, 0x13, 0x27, 0x27, 0x07, 0x07, 0x05, 0x03, 0x09, 0x07, 0x07,
++    0x4a, 0x27, 0x15, 0x0d, 0x40, 0x46, 0x01, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x07, 0x42,
++    0x40, 0x09, 0x44, 0x4a, 0x42, 0x11, 0x42, 0x4a, 0x4a, 0x40, 0x07, 0x0d, 0x0b, 0x0d, 0x44, 0x42,
++    0x07, 0x42, 0x40, 0x09, 0x44, 0x4a, 0x42, 0x11, 0x42, 0x4a, 0x4a, 0x40, 0x07, 0x0d, 0x0b, 0x0d,
++    0x1b, 0x46, 0x23, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x13, 0x07, 0x15, 0x03, 0x46,
++    0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x4a,
++    0x07, 0x0b, 0x0b, 0x15, 0x1b, 0x15, 0x1b, 0x0d, 0x17, 0x03, 0x46, 0x17, 0x03, 0x46, 0x40, 0x40,
++    0x40, 0x11, 0x11, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x11,
++    0x42, 0x21, 0x15, 0x0d, 0x40, 0x0d, 0x11, 0x0b, 0x15, 0x0d, 0x1f, 0x13, 0x15, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4c, 0x16, 0x02, 0x4b, 0x40, 0x09, 0x4c, 0x56, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f,
++    0x02, 0x0b, 0x41, 0x14, 0x01, 0x0b, 0x15, 0x2a, 0x2a, 0x07, 0x07, 0x05, 0x04, 0x0a, 0x09, 0x07,
++    0x49, 0x27, 0x16, 0x0d, 0x40, 0x45, 0x01, 0x40, 0x40, 0x40, 0x02, 0x02, 0x43, 0x41, 0x09, 0x41,
++    0x01, 0x0b, 0x43, 0x49, 0x41, 0x13, 0x41, 0x49, 0x49, 0x01, 0x09, 0x0e, 0x0c, 0x0e, 0x43, 0x41,
++    0x09, 0x41, 0x01, 0x0b, 0x43, 0x49, 0x41, 0x13, 0x41, 0x49, 0x49, 0x01, 0x09, 0x0e, 0x0c, 0x0e,
++    0x1c, 0x45, 0x25, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0c, 0x0c, 0x15, 0x07, 0x15, 0x03, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0c, 0x0c, 0x16, 0x1c, 0x16, 0x1c, 0x0d, 0x17, 0x03, 0x45, 0x17, 0x03, 0x45, 0x40, 0x40,
++    0x40, 0x11, 0x11, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x2a, 0x27, 0x1a, 0x07, 0x1c, 0x1a, 0x12,
++    0x42, 0x21, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0b, 0x16, 0x0d, 0x21, 0x14, 0x16, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4d, 0x17, 0x02, 0x4a, 0x40, 0x08, 0x4d, 0x57, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f,
++    0x02, 0x0d, 0x40, 0x15, 0x02, 0x0d, 0x17, 0x2c, 0x2c, 0x07, 0x07, 0x05, 0x05, 0x0a, 0x0a, 0x07,
++    0x48, 0x27, 0x17, 0x0d, 0x40, 0x45, 0x00, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x40, 0x0a, 0x40,
++    0x02, 0x0d, 0x42, 0x48, 0x40, 0x15, 0x40, 0x48, 0x48, 0x02, 0x0a, 0x0f, 0x0d, 0x0f, 0x42, 0x40,
++    0x0a, 0x40, 0x02, 0x0d, 0x42, 0x48, 0x40, 0x15, 0x40, 0x48, 0x48, 0x02, 0x0a, 0x0f, 0x0d, 0x0f,
++    0x1d, 0x45, 0x27, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x17, 0x07, 0x15, 0x02, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0d, 0x0d, 0x17, 0x1d, 0x17, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40,
++    0x40, 0x10, 0x10, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x12,
++    0x42, 0x20, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0a, 0x17, 0x0d, 0x22, 0x15, 0x17, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4d, 0x18, 0x02, 0x4a, 0x40, 0x07, 0x4d, 0x58, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f,
++    0x02, 0x0e, 0x00, 0x15, 0x03, 0x0e, 0x19, 0x2f, 0x2f, 0x07, 0x07, 0x05, 0x05, 0x0a, 0x0b, 0x07,
++    0x47, 0x27, 0x18, 0x0d, 0x40, 0x45, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x00, 0x0b, 0x00,
++    0x03, 0x0e, 0x42, 0x47, 0x00, 0x16, 0x00, 0x47, 0x47, 0x03, 0x0b, 0x10, 0x0d, 0x10, 0x42, 0x00,
++    0x0b, 0x00, 0x03, 0x0e, 0x42, 0x47, 0x00, 0x16, 0x00, 0x47, 0x47, 0x03, 0x0b, 0x10, 0x0d, 0x10,
++    0x1d, 0x45, 0x29, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x19, 0x07, 0x15, 0x02, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0d, 0x0d, 0x18, 0x1d, 0x18, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40,
++    0x40, 0x0f, 0x0f, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x12,
++    0x42, 0x1f, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0a, 0x18, 0x0d, 0x23, 0x15, 0x18, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4e, 0x19, 0x03, 0x49, 0x40, 0x06, 0x4e, 0x59, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f,
++    0x03, 0x10, 0x01, 0x16, 0x04, 0x10, 0x1b, 0x31, 0x31, 0x07, 0x07, 0x04, 0x06, 0x0b, 0x0c, 0x07,
++    0x46, 0x27, 0x19, 0x0c, 0x40, 0x44, 0x41, 0x40, 0x40, 0x40, 0x03, 0x03, 0x41, 0x01, 0x0c, 0x01,
++    0x04, 0x10, 0x41, 0x46, 0x01, 0x18, 0x01, 0x46, 0x46, 0x04, 0x0c, 0x11, 0x0e, 0x11, 0x41, 0x01,
++    0x0c, 0x01, 0x04, 0x10, 0x41, 0x46, 0x01, 0x18, 0x01, 0x46, 0x46, 0x04, 0x0c, 0x11, 0x0e, 0x11,
++    0x1e, 0x44, 0x2b, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0e, 0x0e, 0x1b, 0x07, 0x14, 0x01, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0e, 0x0e, 0x19, 0x1e, 0x19, 0x1e, 0x0c, 0x17, 0x01, 0x44, 0x17, 0x01, 0x44, 0x40, 0x40,
++    0x40, 0x0e, 0x0e, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x09, 0x2b, 0x27, 0x1b, 0x07, 0x1e, 0x1b, 0x13,
++    0x43, 0x1e, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x09, 0x19, 0x0c, 0x24, 0x16, 0x19, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4f, 0x1a, 0x03, 0x48, 0x40, 0x05, 0x4f, 0x5a, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f,
++    0x03, 0x11, 0x02, 0x17, 0x06, 0x11, 0x1d, 0x34, 0x34, 0x07, 0x07, 0x04, 0x07, 0x0b, 0x0e, 0x07,
++    0x45, 0x27, 0x1a, 0x0c, 0x40, 0x44, 0x42, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x02, 0x0e, 0x02,
++    0x06, 0x11, 0x40, 0x45, 0x02, 0x19, 0x02, 0x45, 0x45, 0x06, 0x0e, 0x12, 0x0f, 0x12, 0x40, 0x02,
++    0x0e, 0x02, 0x06, 0x11, 0x40, 0x45, 0x02, 0x19, 0x02, 0x45, 0x45, 0x06, 0x0e, 0x12, 0x0f, 0x12,
++    0x1f, 0x44, 0x2d, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1d, 0x07, 0x14, 0x00, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0f, 0x0f, 0x1a, 0x1f, 0x1a, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40,
++    0x40, 0x0d, 0x0d, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x13,
++    0x43, 0x1d, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x08, 0x1a, 0x0c, 0x26, 0x17, 0x1a, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4f, 0x1b, 0x03, 0x48, 0x40, 0x04, 0x4f, 0x5b, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f,
++    0x03, 0x13, 0x03, 0x17, 0x07, 0x13, 0x1f, 0x36, 0x36, 0x07, 0x07, 0x04, 0x07, 0x0b, 0x0f, 0x07,
++    0x44, 0x27, 0x1b, 0x0c, 0x40, 0x44, 0x43, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x03, 0x0f, 0x03,
++    0x07, 0x13, 0x40, 0x44, 0x03, 0x1b, 0x03, 0x44, 0x44, 0x07, 0x0f, 0x13, 0x0f, 0x13, 0x40, 0x03,
++    0x0f, 0x03, 0x07, 0x13, 0x40, 0x44, 0x03, 0x1b, 0x03, 0x44, 0x44, 0x07, 0x0f, 0x13, 0x0f, 0x13,
++    0x1f, 0x44, 0x2f, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1f, 0x07, 0x14, 0x00, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0f, 0x0f, 0x1b, 0x1f, 0x1b, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40,
++    0x40, 0x0c, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x13,
++    0x43, 0x1c, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x08, 0x1b, 0x0c, 0x27, 0x17, 0x1b, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x50, 0x1c, 0x04, 0x47, 0x40, 0x03, 0x50, 0x5c, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f,
++    0x04, 0x14, 0x04, 0x18, 0x08, 0x14, 0x21, 0x39, 0x39, 0x07, 0x07, 0x03, 0x08, 0x0c, 0x10, 0x07,
++    0x43, 0x27, 0x1c, 0x0b, 0x40, 0x43, 0x44, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x04, 0x10, 0x04,
++    0x08, 0x14, 0x00, 0x43, 0x04, 0x1c, 0x04, 0x43, 0x43, 0x08, 0x10, 0x14, 0x10, 0x14, 0x00, 0x04,
++    0x10, 0x04, 0x08, 0x14, 0x00, 0x43, 0x04, 0x1c, 0x04, 0x43, 0x43, 0x08, 0x10, 0x14, 0x10, 0x14,
++    0x20, 0x43, 0x31, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x21, 0x07, 0x13, 0x40, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x10, 0x10, 0x1c, 0x20, 0x1c, 0x20, 0x0b, 0x17, 0x40, 0x43, 0x17, 0x40, 0x43, 0x40, 0x40,
++    0x40, 0x0b, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x07, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x14,
++    0x44, 0x1b, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x07, 0x1c, 0x0b, 0x28, 0x18, 0x1c, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x51, 0x1d, 0x04, 0x47, 0x40, 0x02, 0x51, 0x5d, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f,
++    0x04, 0x16, 0x05, 0x18, 0x09, 0x16, 0x22, 0x3b, 0x3b, 0x07, 0x07, 0x03, 0x08, 0x0c, 0x11, 0x07,
++    0x42, 0x27, 0x1d, 0x0b, 0x40, 0x43, 0x45, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x05, 0x11, 0x05,
++    0x09, 0x16, 0x00, 0x42, 0x05, 0x1e, 0x05, 0x42, 0x42, 0x09, 0x11, 0x15, 0x10, 0x15, 0x00, 0x05,
++    0x11, 0x05, 0x09, 0x16, 0x00, 0x42, 0x05, 0x1e, 0x05, 0x42, 0x42, 0x09, 0x11, 0x15, 0x10, 0x15,
++    0x20, 0x43, 0x32, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x22, 0x07, 0x13, 0x41, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x10, 0x10, 0x1d, 0x20, 0x1d, 0x20, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40,
++    0x40, 0x0a, 0x0a, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x14,
++    0x44, 0x1a, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x06, 0x1d, 0x0b, 0x29, 0x18, 0x1d, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x51, 0x1e, 0x04, 0x46, 0x40, 0x01, 0x51, 0x5e, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f,
++    0x04, 0x18, 0x06, 0x19, 0x0b, 0x18, 0x24, 0x3e, 0x3e, 0x07, 0x07, 0x03, 0x09, 0x0c, 0x13, 0x07,
++    0x41, 0x27, 0x1e, 0x0b, 0x40, 0x43, 0x46, 0x40, 0x40, 0x40, 0x04, 0x04, 0x01, 0x06, 0x13, 0x06,
++    0x0b, 0x18, 0x01, 0x41, 0x06, 0x20, 0x06, 0x41, 0x41, 0x0b, 0x13, 0x16, 0x11, 0x16, 0x01, 0x06,
++    0x13, 0x06, 0x0b, 0x18, 0x01, 0x41, 0x06, 0x20, 0x06, 0x41, 0x41, 0x0b, 0x13, 0x16, 0x11, 0x16,
++    0x21, 0x43, 0x34, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x11, 0x11, 0x24, 0x07, 0x13, 0x41, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x11, 0x11, 0x1e, 0x21, 0x1e, 0x21, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40,
++    0x40, 0x09, 0x09, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x21, 0x1c, 0x14,
++    0x44, 0x19, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x06, 0x1e, 0x0b, 0x2b, 0x19, 0x1e, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x52, 0x1f, 0x05, 0x45, 0x40, 0x00, 0x52, 0x5f, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f,
++    0x05, 0x19, 0x07, 0x1a, 0x0c, 0x19, 0x26, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0a, 0x0d, 0x14, 0x07,
++    0x40, 0x27, 0x1f, 0x0a, 0x40, 0x42, 0x47, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x07, 0x14, 0x07,
++    0x0c, 0x19, 0x02, 0x40, 0x07, 0x21, 0x07, 0x40, 0x40, 0x0c, 0x14, 0x17, 0x12, 0x17, 0x02, 0x07,
++    0x14, 0x07, 0x0c, 0x19, 0x02, 0x40, 0x07, 0x21, 0x07, 0x40, 0x40, 0x0c, 0x14, 0x17, 0x12, 0x17,
++    0x22, 0x42, 0x36, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x26, 0x07, 0x12, 0x42, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x12, 0x12, 0x1f, 0x22, 0x1f, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40,
++    0x40, 0x08, 0x08, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x15,
++    0x45, 0x18, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x05, 0x1f, 0x0a, 0x2c, 0x1a, 0x1f, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x52, 0x20, 0x05, 0x45, 0x40, 0x40, 0x52, 0x60, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f,
++    0x05, 0x1b, 0x08, 0x1a, 0x0d, 0x1b, 0x28, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0a, 0x0d, 0x15, 0x07,
++    0x00, 0x27, 0x20, 0x0a, 0x40, 0x42, 0x48, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x08, 0x15, 0x08,
++    0x0d, 0x1b, 0x02, 0x00, 0x08, 0x23, 0x08, 0x00, 0x00, 0x0d, 0x15, 0x18, 0x12, 0x18, 0x02, 0x08,
++    0x15, 0x08, 0x0d, 0x1b, 0x02, 0x00, 0x08, 0x23, 0x08, 0x00, 0x00, 0x0d, 0x15, 0x18, 0x12, 0x18,
++    0x22, 0x42, 0x38, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x28, 0x07, 0x12, 0x42, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x12, 0x12, 0x20, 0x22, 0x20, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40,
++    0x40, 0x07, 0x07, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x15,
++    0x45, 0x17, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x05, 0x20, 0x0a, 0x2d, 0x1a, 0x20, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x53, 0x21, 0x05, 0x44, 0x40, 0x41, 0x53, 0x61, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f,
++    0x05, 0x1c, 0x09, 0x1b, 0x0e, 0x1c, 0x2a, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0d, 0x16, 0x07,
++    0x01, 0x27, 0x21, 0x0a, 0x40, 0x42, 0x49, 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x16, 0x09,
++    0x0e, 0x1c, 0x03, 0x01, 0x09, 0x24, 0x09, 0x01, 0x01, 0x0e, 0x16, 0x19, 0x13, 0x19, 0x03, 0x09,
++    0x16, 0x09, 0x0e, 0x1c, 0x03, 0x01, 0x09, 0x24, 0x09, 0x01, 0x01, 0x0e, 0x16, 0x19, 0x13, 0x19,
++    0x23, 0x42, 0x3a, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x07, 0x12, 0x43, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x13, 0x13, 0x21, 0x23, 0x21, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, 0x40,
++    0x40, 0x06, 0x06, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, 0x1d, 0x15,
++    0x45, 0x16, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x04, 0x21, 0x0a, 0x2e, 0x1b, 0x21, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x54, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f,
++    0x06, 0x1e, 0x0a, 0x1c, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0c, 0x0e, 0x18, 0x07,
++    0x02, 0x27, 0x22, 0x09, 0x40, 0x41, 0x4a, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0a, 0x18, 0x0a,
++    0x10, 0x1e, 0x04, 0x02, 0x0a, 0x26, 0x0a, 0x02, 0x02, 0x10, 0x18, 0x1a, 0x14, 0x1a, 0x04, 0x0a,
++    0x18, 0x0a, 0x10, 0x1e, 0x04, 0x02, 0x0a, 0x26, 0x0a, 0x02, 0x02, 0x10, 0x18, 0x1a, 0x14, 0x1a,
++    0x24, 0x41, 0x3c, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2c, 0x07, 0x11, 0x44, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x14, 0x14, 0x22, 0x24, 0x22, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
++    0x40, 0x05, 0x05, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x16,
++    0x46, 0x15, 0x11, 0x09, 0x40, 0x09, 0x16, 0x03, 0x22, 0x09, 0x30, 0x1c, 0x22, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x54, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f,
++    0x06, 0x1f, 0x0b, 0x1c, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0c, 0x0e, 0x19, 0x07,
++    0x03, 0x27, 0x23, 0x09, 0x40, 0x41, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x19, 0x0b,
++    0x11, 0x1f, 0x04, 0x03, 0x0b, 0x27, 0x0b, 0x03, 0x03, 0x11, 0x19, 0x1b, 0x14, 0x1b, 0x04, 0x0b,
++    0x19, 0x0b, 0x11, 0x1f, 0x04, 0x03, 0x0b, 0x27, 0x0b, 0x03, 0x03, 0x11, 0x19, 0x1b, 0x14, 0x1b,
++    0x24, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, 0x07, 0x11, 0x44, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x14, 0x14, 0x23, 0x24, 0x23, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
++    0x40, 0x04, 0x04, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x16,
++    0x46, 0x14, 0x11, 0x09, 0x40, 0x09, 0x16, 0x03, 0x23, 0x09, 0x31, 0x1c, 0x23, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x55, 0x24, 0x06, 0x42, 0x40, 0x44, 0x55, 0x64, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f,
++    0x06, 0x21, 0x0c, 0x1d, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0d, 0x0e, 0x1a, 0x07,
++    0x04, 0x27, 0x24, 0x09, 0x40, 0x41, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x1a, 0x0c,
++    0x12, 0x21, 0x05, 0x04, 0x0c, 0x29, 0x0c, 0x04, 0x04, 0x12, 0x1a, 0x1c, 0x15, 0x1c, 0x05, 0x0c,
++    0x1a, 0x0c, 0x12, 0x21, 0x05, 0x04, 0x0c, 0x29, 0x0c, 0x04, 0x04, 0x12, 0x1a, 0x1c, 0x15, 0x1c,
++    0x25, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x07, 0x11, 0x45, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x15, 0x15, 0x24, 0x25, 0x24, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, 0x40, 0x40,
++    0x40, 0x03, 0x03, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x16,
++    0x46, 0x13, 0x11, 0x09, 0x40, 0x09, 0x16, 0x02, 0x24, 0x09, 0x32, 0x1d, 0x24, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x56, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f,
++    0x06, 0x22, 0x0c, 0x1d, 0x13, 0x22, 0x31, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0d, 0x0e, 0x1b, 0x07,
++    0x04, 0x27, 0x24, 0x08, 0x40, 0x41, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x1b, 0x0c,
++    0x13, 0x22, 0x05, 0x04, 0x0c, 0x2a, 0x0c, 0x04, 0x04, 0x13, 0x1b, 0x1c, 0x15, 0x1c, 0x05, 0x0c,
++    0x1b, 0x0c, 0x13, 0x22, 0x05, 0x04, 0x0c, 0x2a, 0x0c, 0x04, 0x04, 0x13, 0x1b, 0x1c, 0x15, 0x1c,
++    0x25, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x07, 0x10, 0x46, 0x41,
++    0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f,
++    0x07, 0x15, 0x15, 0x24, 0x25, 0x24, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40,
++    0x40, 0x02, 0x02, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x16,
++    0x47, 0x12, 0x10, 0x08, 0x40, 0x08, 0x16, 0x01, 0x24, 0x08, 0x33, 0x1d, 0x24, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x56, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f,
++    0x07, 0x24, 0x0d, 0x1e, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0e, 0x0f, 0x1d, 0x07,
++    0x05, 0x27, 0x25, 0x08, 0x40, 0x40, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x1d, 0x0d,
++    0x15, 0x24, 0x06, 0x05, 0x0d, 0x2c, 0x0d, 0x05, 0x05, 0x15, 0x1d, 0x1d, 0x16, 0x1d, 0x06, 0x0d,
++    0x1d, 0x0d, 0x15, 0x24, 0x06, 0x05, 0x0d, 0x2c, 0x0d, 0x05, 0x05, 0x15, 0x1d, 0x1d, 0x16, 0x1d,
++    0x26, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x07, 0x10, 0x46, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x16, 0x16, 0x25, 0x26, 0x25, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40,
++    0x40, 0x02, 0x02, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x17,
++    0x47, 0x12, 0x10, 0x08, 0x40, 0x08, 0x17, 0x01, 0x25, 0x08, 0x35, 0x1e, 0x25, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x57, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f,
++    0x07, 0x26, 0x0e, 0x1f, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0f, 0x0f, 0x1e, 0x07,
++    0x06, 0x27, 0x26, 0x08, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x1e, 0x0e,
++    0x16, 0x26, 0x07, 0x06, 0x0e, 0x2e, 0x0e, 0x06, 0x06, 0x16, 0x1e, 0x1e, 0x17, 0x1e, 0x07, 0x0e,
++    0x1e, 0x0e, 0x16, 0x26, 0x07, 0x06, 0x0e, 0x2e, 0x0e, 0x06, 0x06, 0x16, 0x1e, 0x1e, 0x17, 0x1e,
++    0x27, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x07, 0x10, 0x47, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x17, 0x17, 0x26, 0x27, 0x26, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
++    0x40, 0x01, 0x01, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x17,
++    0x47, 0x11, 0x10, 0x08, 0x40, 0x08, 0x17, 0x00, 0x26, 0x08, 0x36, 0x1f, 0x26, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x57, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f,
++    0x07, 0x27, 0x0f, 0x1f, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0f, 0x0f, 0x1f, 0x07,
++    0x07, 0x27, 0x27, 0x08, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x1f, 0x0f,
++    0x17, 0x27, 0x07, 0x07, 0x0f, 0x2f, 0x0f, 0x07, 0x07, 0x17, 0x1f, 0x1f, 0x17, 0x1f, 0x07, 0x0f,
++    0x1f, 0x0f, 0x17, 0x27, 0x07, 0x07, 0x0f, 0x2f, 0x0f, 0x07, 0x07, 0x17, 0x1f, 0x1f, 0x17, 0x1f,
++    0x27, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x07, 0x10, 0x47, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x17, 0x17, 0x27, 0x27, 0x27, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
++    0x40, 0x00, 0x00, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x17,
++    0x47, 0x10, 0x10, 0x08, 0x40, 0x08, 0x17, 0x00, 0x27, 0x08, 0x37, 0x1f, 0x27, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x48, 0x48, 0x60, 0x40, 0x27, 0x07, 0x07, 0x1f, 0x40, 0x48, 0x40, 0x40, 0x17, 0x0f,
++    0x48, 0x68, 0x40, 0x07, 0x68, 0x68, 0x68, 0x68, 0x68, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x40, 0x07,
++    0x68, 0x27, 0x50, 0x17, 0x40, 0x07, 0x1f, 0x40, 0x40, 0x40, 0x48, 0x48, 0x58, 0x60, 0x50, 0x60,
++    0x68, 0x60, 0x58, 0x68, 0x68, 0x68, 0x58, 0x60, 0x68, 0x68, 0x68, 0x50, 0x48, 0x58, 0x58, 0x60,
++    0x50, 0x60, 0x68, 0x60, 0x58, 0x68, 0x68, 0x68, 0x58, 0x60, 0x68, 0x68, 0x68, 0x50, 0x48, 0x58,
++    0x07, 0x50, 0x58, 0x40, 0x40, 0x40, 0x48, 0x07, 0x48, 0x48, 0x48, 0x68, 0x50, 0x1f, 0x17, 0x50,
++    0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x40,
++    0x07, 0x40, 0x40, 0x40, 0x07, 0x40, 0x07, 0x17, 0x17, 0x17, 0x50, 0x17, 0x17, 0x50, 0x40, 0x40,
++    0x40, 0x2f, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x1f, 0x27, 0x0f, 0x07, 0x07, 0x0f, 0x40,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x48, 0x17, 0x48, 0x48, 0x48, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x47, 0x47, 0x5f, 0x40, 0x27, 0x07, 0x07, 0x20, 0x40, 0x47, 0x40, 0x40, 0x17, 0x0f,
++    0x47, 0x66, 0x40, 0x08, 0x66, 0x66, 0x66, 0x65, 0x65, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x00, 0x07,
++    0x67, 0x27, 0x4e, 0x17, 0x40, 0x07, 0x1f, 0x40, 0x40, 0x40, 0x47, 0x47, 0x57, 0x5f, 0x4f, 0x5f,
++    0x66, 0x5e, 0x57, 0x67, 0x67, 0x66, 0x57, 0x5f, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x56, 0x57, 0x5f,
++    0x4f, 0x5f, 0x66, 0x5e, 0x57, 0x67, 0x67, 0x66, 0x57, 0x5f, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x56,
++    0x08, 0x4f, 0x56, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x47, 0x47, 0x66, 0x4f, 0x1f, 0x17, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x17, 0x17, 0x17, 0x4f, 0x17, 0x17, 0x4f, 0x40, 0x40,
++    0x40, 0x2f, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x20, 0x27, 0x10, 0x07, 0x08, 0x10, 0x00,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x47, 0x17, 0x46, 0x47, 0x47, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x46, 0x47, 0x5e, 0x40, 0x26, 0x06, 0x06, 0x20, 0x40, 0x47, 0x40, 0x40, 0x16, 0x0f,
++    0x47, 0x64, 0x40, 0x08, 0x65, 0x64, 0x64, 0x63, 0x63, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x01, 0x07,
++    0x66, 0x27, 0x4d, 0x17, 0x40, 0x07, 0x1e, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5e, 0x4e, 0x5e,
++    0x65, 0x5d, 0x56, 0x66, 0x66, 0x64, 0x56, 0x5e, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x55, 0x56, 0x5e,
++    0x4e, 0x5e, 0x65, 0x5d, 0x56, 0x66, 0x66, 0x64, 0x56, 0x5e, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x55,
++    0x09, 0x4f, 0x54, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x64, 0x4e, 0x1f, 0x16, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x00, 0x00, 0x01, 0x09, 0x01, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40,
++    0x40, 0x2e, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x01,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x46, 0x17, 0x45, 0x46, 0x46, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x45, 0x47, 0x5e, 0x40, 0x25, 0x06, 0x05, 0x20, 0x40, 0x47, 0x40, 0x40, 0x16, 0x0f,
++    0x47, 0x63, 0x40, 0x08, 0x64, 0x63, 0x62, 0x60, 0x60, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x01, 0x07,
++    0x65, 0x27, 0x4c, 0x17, 0x40, 0x07, 0x1d, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5d, 0x4e, 0x5d,
++    0x64, 0x5c, 0x56, 0x65, 0x65, 0x63, 0x56, 0x5e, 0x65, 0x65, 0x63, 0x4d, 0x46, 0x54, 0x56, 0x5d,
++    0x4e, 0x5d, 0x64, 0x5c, 0x56, 0x65, 0x65, 0x63, 0x56, 0x5e, 0x65, 0x65, 0x63, 0x4d, 0x46, 0x54,
++    0x09, 0x4f, 0x52, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x62, 0x4e, 0x1f, 0x16, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x00, 0x00, 0x01, 0x09, 0x01, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40,
++    0x40, 0x2d, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x01,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x45, 0x17, 0x44, 0x45, 0x45, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x44, 0x46, 0x5d, 0x40, 0x24, 0x05, 0x04, 0x21, 0x40, 0x46, 0x40, 0x40, 0x15, 0x0f,
++    0x46, 0x61, 0x40, 0x09, 0x63, 0x61, 0x60, 0x5e, 0x5e, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x02, 0x07,
++    0x64, 0x27, 0x4b, 0x16, 0x40, 0x06, 0x1c, 0x40, 0x40, 0x40, 0x46, 0x46, 0x55, 0x5c, 0x4d, 0x5c,
++    0x63, 0x5b, 0x55, 0x64, 0x64, 0x61, 0x55, 0x5d, 0x64, 0x64, 0x61, 0x4c, 0x45, 0x53, 0x55, 0x5c,
++    0x4d, 0x5c, 0x63, 0x5b, 0x55, 0x64, 0x64, 0x61, 0x55, 0x5d, 0x64, 0x64, 0x61, 0x4c, 0x45, 0x53,
++    0x0a, 0x4e, 0x50, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x45, 0x45, 0x60, 0x4d, 0x1e, 0x15, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x01, 0x01, 0x02, 0x0a, 0x02, 0x0a, 0x16, 0x17, 0x15, 0x4e, 0x17, 0x15, 0x4e, 0x40, 0x40,
++    0x40, 0x2c, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x1d, 0x21, 0x27, 0x11, 0x07, 0x0a, 0x11, 0x02,
++    0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x44, 0x16, 0x43, 0x44, 0x44, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x43, 0x46, 0x5c, 0x40, 0x23, 0x04, 0x03, 0x21, 0x40, 0x46, 0x40, 0x40, 0x14, 0x0f,
++    0x46, 0x60, 0x40, 0x09, 0x61, 0x60, 0x5e, 0x5b, 0x5b, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x03, 0x07,
++    0x63, 0x27, 0x49, 0x16, 0x40, 0x06, 0x1b, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5b, 0x4c, 0x5b,
++    0x61, 0x59, 0x54, 0x63, 0x63, 0x60, 0x54, 0x5c, 0x63, 0x63, 0x60, 0x4b, 0x44, 0x51, 0x54, 0x5b,
++    0x4c, 0x5b, 0x61, 0x59, 0x54, 0x63, 0x63, 0x60, 0x54, 0x5c, 0x63, 0x63, 0x60, 0x4b, 0x44, 0x51,
++    0x0b, 0x4e, 0x4e, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5e, 0x4c, 0x1e, 0x14, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x01, 0x01, 0x03, 0x0b, 0x03, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40,
++    0x40, 0x2b, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x03,
++    0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x43, 0x16, 0x41, 0x43, 0x43, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x42, 0x46, 0x5c, 0x40, 0x22, 0x04, 0x02, 0x21, 0x40, 0x46, 0x40, 0x40, 0x14, 0x0f,
++    0x46, 0x5e, 0x40, 0x09, 0x60, 0x5e, 0x5c, 0x59, 0x59, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x03, 0x07,
++    0x62, 0x27, 0x48, 0x16, 0x40, 0x06, 0x1a, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5a, 0x4c, 0x5a,
++    0x60, 0x58, 0x54, 0x62, 0x62, 0x5e, 0x54, 0x5c, 0x62, 0x62, 0x5e, 0x4a, 0x44, 0x50, 0x54, 0x5a,
++    0x4c, 0x5a, 0x60, 0x58, 0x54, 0x62, 0x62, 0x5e, 0x54, 0x5c, 0x62, 0x62, 0x5e, 0x4a, 0x44, 0x50,
++    0x0b, 0x4e, 0x4c, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5c, 0x4c, 0x1e, 0x14, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x01, 0x01, 0x03, 0x0b, 0x03, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40,
++    0x40, 0x2a, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x03,
++    0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x42, 0x16, 0x40, 0x42, 0x42, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x41, 0x45, 0x5b, 0x40, 0x21, 0x03, 0x01, 0x22, 0x40, 0x45, 0x40, 0x40, 0x13, 0x0f,
++    0x45, 0x5d, 0x40, 0x0a, 0x5f, 0x5d, 0x5a, 0x56, 0x56, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x04, 0x07,
++    0x61, 0x27, 0x47, 0x15, 0x40, 0x05, 0x19, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x59, 0x4b, 0x59,
++    0x5f, 0x57, 0x53, 0x61, 0x61, 0x5d, 0x53, 0x5b, 0x61, 0x61, 0x5d, 0x49, 0x43, 0x4f, 0x53, 0x59,
++    0x4b, 0x59, 0x5f, 0x57, 0x53, 0x61, 0x61, 0x5d, 0x53, 0x5b, 0x61, 0x61, 0x5d, 0x49, 0x43, 0x4f,
++    0x0c, 0x4d, 0x4a, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x5a, 0x4b, 0x1d, 0x13, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x02, 0x02, 0x04, 0x0c, 0x04, 0x0c, 0x15, 0x17, 0x13, 0x4d, 0x17, 0x13, 0x4d, 0x40, 0x40,
++    0x40, 0x29, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x1b, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x04,
++    0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x41, 0x15, 0x00, 0x41, 0x41, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x40, 0x45, 0x5b, 0x40, 0x20, 0x02, 0x00, 0x22, 0x40, 0x45, 0x40, 0x40, 0x12, 0x0f,
++    0x45, 0x5b, 0x40, 0x0a, 0x5e, 0x5b, 0x59, 0x54, 0x54, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x04, 0x07,
++    0x60, 0x27, 0x46, 0x15, 0x40, 0x05, 0x18, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x58, 0x4b, 0x58,
++    0x5e, 0x56, 0x53, 0x60, 0x60, 0x5b, 0x53, 0x5b, 0x60, 0x60, 0x5b, 0x48, 0x43, 0x4e, 0x53, 0x58,
++    0x4b, 0x58, 0x5e, 0x56, 0x53, 0x60, 0x60, 0x5b, 0x53, 0x5b, 0x60, 0x60, 0x5b, 0x48, 0x43, 0x4e,
++    0x0c, 0x4d, 0x49, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x59, 0x4b, 0x1d, 0x12, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x02, 0x02, 0x04, 0x0c, 0x04, 0x0c, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40,
++    0x40, 0x28, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x04,
++    0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x40, 0x15, 0x01, 0x40, 0x40, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x00, 0x45, 0x5a, 0x40, 0x1f, 0x02, 0x40, 0x22, 0x40, 0x45, 0x40, 0x40, 0x12, 0x0f,
++    0x45, 0x59, 0x40, 0x0a, 0x5c, 0x59, 0x57, 0x51, 0x51, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x05, 0x07,
++    0x5f, 0x27, 0x44, 0x15, 0x40, 0x05, 0x17, 0x40, 0x40, 0x40, 0x45, 0x45, 0x52, 0x57, 0x4a, 0x57,
++    0x5c, 0x54, 0x52, 0x5f, 0x5f, 0x59, 0x52, 0x5a, 0x5f, 0x5f, 0x59, 0x47, 0x42, 0x4c, 0x52, 0x57,
++    0x4a, 0x57, 0x5c, 0x54, 0x52, 0x5f, 0x5f, 0x59, 0x52, 0x5a, 0x5f, 0x5f, 0x59, 0x47, 0x42, 0x4c,
++    0x0d, 0x4d, 0x47, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x42, 0x42, 0x57, 0x4a, 0x1d, 0x12, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x02, 0x02, 0x05, 0x0d, 0x05, 0x0d, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40,
++    0x40, 0x27, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0d, 0x12, 0x05,
++    0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x00, 0x15, 0x03, 0x00, 0x00, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x01, 0x44, 0x59, 0x40, 0x1e, 0x01, 0x41, 0x23, 0x40, 0x44, 0x40, 0x40, 0x11, 0x0f,
++    0x44, 0x58, 0x40, 0x0b, 0x5b, 0x58, 0x55, 0x4f, 0x4f, 0x07, 0x07, 0x0c, 0x3e, 0x14, 0x06, 0x07,
++    0x5e, 0x27, 0x43, 0x14, 0x40, 0x04, 0x16, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x56, 0x49, 0x56,
++    0x5b, 0x53, 0x51, 0x5e, 0x5e, 0x58, 0x51, 0x59, 0x5e, 0x5e, 0x58, 0x46, 0x41, 0x4b, 0x51, 0x56,
++    0x49, 0x56, 0x5b, 0x53, 0x51, 0x5e, 0x5e, 0x58, 0x51, 0x59, 0x5e, 0x5e, 0x58, 0x46, 0x41, 0x4b,
++    0x0e, 0x4c, 0x45, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x55, 0x49, 0x1c, 0x11, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x03, 0x03, 0x06, 0x0e, 0x06, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40,
++    0x40, 0x26, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x06,
++    0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x01, 0x14, 0x04, 0x01, 0x01, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x02, 0x44, 0x59, 0x40, 0x1d, 0x01, 0x42, 0x23, 0x40, 0x44, 0x40, 0x40, 0x11, 0x0f,
++    0x44, 0x56, 0x40, 0x0b, 0x5a, 0x56, 0x53, 0x4c, 0x4c, 0x07, 0x07, 0x0c, 0x3e, 0x14, 0x06, 0x07,
++    0x5d, 0x27, 0x42, 0x14, 0x40, 0x04, 0x15, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x55, 0x49, 0x55,
++    0x5a, 0x52, 0x51, 0x5d, 0x5d, 0x56, 0x51, 0x59, 0x5d, 0x5d, 0x56, 0x45, 0x41, 0x4a, 0x51, 0x55,
++    0x49, 0x55, 0x5a, 0x52, 0x51, 0x5d, 0x5d, 0x56, 0x51, 0x59, 0x5d, 0x5d, 0x56, 0x45, 0x41, 0x4a,
++    0x0e, 0x4c, 0x43, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x53, 0x49, 0x1c, 0x11, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x03, 0x03, 0x06, 0x0e, 0x06, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40,
++    0x40, 0x25, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x06,
++    0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x02, 0x14, 0x05, 0x02, 0x02, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x03, 0x44, 0x58, 0x40, 0x1c, 0x00, 0x43, 0x23, 0x40, 0x44, 0x40, 0x40, 0x10, 0x0f,
++    0x44, 0x55, 0x40, 0x0b, 0x59, 0x55, 0x51, 0x4a, 0x4a, 0x07, 0x07, 0x0c, 0x3d, 0x14, 0x07, 0x07,
++    0x5c, 0x27, 0x41, 0x14, 0x40, 0x04, 0x14, 0x40, 0x40, 0x40, 0x44, 0x44, 0x50, 0x54, 0x48, 0x54,
++    0x59, 0x51, 0x50, 0x5c, 0x5c, 0x55, 0x50, 0x58, 0x5c, 0x5c, 0x55, 0x44, 0x40, 0x49, 0x50, 0x54,
++    0x48, 0x54, 0x59, 0x51, 0x50, 0x5c, 0x5c, 0x55, 0x50, 0x58, 0x5c, 0x5c, 0x55, 0x44, 0x40, 0x49,
++    0x0f, 0x4c, 0x41, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x40, 0x40, 0x51, 0x48, 0x1c, 0x10, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x03, 0x03, 0x07, 0x0f, 0x07, 0x0f, 0x14, 0x17, 0x10, 0x4c, 0x17, 0x10, 0x4c, 0x40, 0x40,
++    0x40, 0x24, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x18, 0x23, 0x27, 0x13, 0x07, 0x0f, 0x13, 0x07,
++    0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x03, 0x14, 0x06, 0x03, 0x03, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x04, 0x43, 0x57, 0x40, 0x1b, 0x40, 0x44, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0f, 0x0f,
++    0x43, 0x53, 0x40, 0x0c, 0x57, 0x53, 0x4f, 0x47, 0x47, 0x07, 0x07, 0x0b, 0x3b, 0x13, 0x08, 0x07,
++    0x5b, 0x27, 0x00, 0x13, 0x40, 0x03, 0x13, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x53, 0x47, 0x53,
++    0x57, 0x4f, 0x4f, 0x5b, 0x5b, 0x53, 0x4f, 0x57, 0x5b, 0x5b, 0x53, 0x43, 0x00, 0x47, 0x4f, 0x53,
++    0x47, 0x53, 0x57, 0x4f, 0x4f, 0x5b, 0x5b, 0x53, 0x4f, 0x57, 0x5b, 0x5b, 0x53, 0x43, 0x00, 0x47,
++    0x10, 0x4b, 0x00, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4f, 0x47, 0x1b, 0x0f, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x04, 0x04, 0x08, 0x10, 0x08, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40,
++    0x40, 0x23, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x08,
++    0x03, 0x3e, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x04, 0x13, 0x08, 0x04, 0x04, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x05, 0x43, 0x57, 0x40, 0x1a, 0x40, 0x45, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0f, 0x0f,
++    0x43, 0x52, 0x40, 0x0c, 0x56, 0x52, 0x4d, 0x45, 0x45, 0x07, 0x07, 0x0b, 0x3a, 0x13, 0x08, 0x07,
++    0x5a, 0x27, 0x01, 0x13, 0x40, 0x03, 0x12, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x52, 0x47, 0x52,
++    0x56, 0x4e, 0x4f, 0x5a, 0x5a, 0x52, 0x4f, 0x57, 0x5a, 0x5a, 0x52, 0x42, 0x00, 0x46, 0x4f, 0x52,
++    0x47, 0x52, 0x56, 0x4e, 0x4f, 0x5a, 0x5a, 0x52, 0x4f, 0x57, 0x5a, 0x5a, 0x52, 0x42, 0x00, 0x46,
++    0x10, 0x4b, 0x02, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4d, 0x47, 0x1b, 0x0f, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x04, 0x04, 0x08, 0x10, 0x08, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40,
++    0x40, 0x22, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x08,
++    0x03, 0x3e, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x05, 0x13, 0x09, 0x05, 0x05, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x06, 0x43, 0x56, 0x40, 0x19, 0x41, 0x46, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0e, 0x0f,
++    0x43, 0x50, 0x40, 0x0c, 0x55, 0x50, 0x4b, 0x42, 0x42, 0x07, 0x07, 0x0b, 0x38, 0x13, 0x09, 0x07,
++    0x59, 0x27, 0x02, 0x13, 0x40, 0x03, 0x11, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x46, 0x51,
++    0x55, 0x4d, 0x4e, 0x59, 0x59, 0x50, 0x4e, 0x56, 0x59, 0x59, 0x50, 0x41, 0x01, 0x45, 0x4e, 0x51,
++    0x46, 0x51, 0x55, 0x4d, 0x4e, 0x59, 0x59, 0x50, 0x4e, 0x56, 0x59, 0x59, 0x50, 0x41, 0x01, 0x45,
++    0x11, 0x4b, 0x04, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4b, 0x46, 0x1b, 0x0e, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x04, 0x04, 0x09, 0x11, 0x09, 0x11, 0x13, 0x17, 0x0e, 0x4b, 0x17, 0x0e, 0x4b, 0x40, 0x40,
++    0x40, 0x21, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x16, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x09,
++    0x03, 0x3d, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x06, 0x13, 0x0a, 0x06, 0x06, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x06, 0x43, 0x56, 0x40, 0x18, 0x42, 0x47, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0d, 0x0f,
++    0x43, 0x4f, 0x40, 0x0c, 0x54, 0x4f, 0x4a, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x36, 0x12, 0x09, 0x07,
++    0x59, 0x27, 0x03, 0x12, 0x40, 0x02, 0x10, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x46, 0x51,
++    0x54, 0x4c, 0x4e, 0x59, 0x59, 0x4f, 0x4e, 0x56, 0x59, 0x59, 0x4f, 0x41, 0x01, 0x44, 0x4e, 0x51,
++    0x46, 0x51, 0x54, 0x4c, 0x4e, 0x59, 0x59, 0x4f, 0x4e, 0x56, 0x59, 0x59, 0x4f, 0x41, 0x01, 0x44,
++    0x11, 0x4b, 0x05, 0x40, 0x45, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4a, 0x46, 0x1a, 0x0d, 0x4b,
++    0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x45,
++    0x07, 0x04, 0x04, 0x09, 0x11, 0x09, 0x11, 0x12, 0x17, 0x0d, 0x4b, 0x17, 0x0d, 0x4b, 0x40, 0x40,
++    0x40, 0x20, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x09,
++    0x02, 0x3b, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x06, 0x12, 0x0b, 0x06, 0x06, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x07, 0x42, 0x55, 0x40, 0x18, 0x42, 0x47, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0d, 0x0f,
++    0x42, 0x4d, 0x40, 0x0d, 0x52, 0x4d, 0x48, 0x02, 0x02, 0x07, 0x07, 0x0a, 0x35, 0x12, 0x0a, 0x07,
++    0x58, 0x27, 0x05, 0x12, 0x40, 0x02, 0x10, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4d, 0x50, 0x45, 0x50,
++    0x52, 0x4a, 0x4d, 0x58, 0x58, 0x4d, 0x4d, 0x55, 0x58, 0x58, 0x4d, 0x40, 0x02, 0x42, 0x4d, 0x50,
++    0x45, 0x50, 0x52, 0x4a, 0x4d, 0x58, 0x58, 0x4d, 0x4d, 0x55, 0x58, 0x58, 0x4d, 0x40, 0x02, 0x42,
++    0x12, 0x4a, 0x07, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x02, 0x02, 0x48, 0x45, 0x1a, 0x0d, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x05, 0x05, 0x0a, 0x12, 0x0a, 0x12, 0x12, 0x17, 0x0d, 0x4a, 0x17, 0x0d, 0x4a, 0x40, 0x40,
++    0x40, 0x20, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x25, 0x27, 0x15, 0x07, 0x12, 0x15, 0x0a,
++    0x02, 0x3a, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x07, 0x12, 0x0d, 0x07, 0x07, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x08, 0x42, 0x54, 0x40, 0x17, 0x43, 0x48, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0c, 0x0f,
++    0x42, 0x4b, 0x40, 0x0d, 0x51, 0x4b, 0x46, 0x04, 0x04, 0x07, 0x07, 0x0a, 0x33, 0x12, 0x0b, 0x07,
++    0x57, 0x27, 0x06, 0x12, 0x40, 0x02, 0x0f, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4f, 0x44, 0x4f,
++    0x51, 0x49, 0x4c, 0x57, 0x57, 0x4b, 0x4c, 0x54, 0x57, 0x57, 0x4b, 0x00, 0x03, 0x41, 0x4c, 0x4f,
++    0x44, 0x4f, 0x51, 0x49, 0x4c, 0x57, 0x57, 0x4b, 0x4c, 0x54, 0x57, 0x57, 0x4b, 0x00, 0x03, 0x41,
++    0x13, 0x4a, 0x09, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x46, 0x44, 0x1a, 0x0c, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x05, 0x05, 0x0b, 0x13, 0x0b, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40,
++    0x40, 0x1f, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0b,
++    0x02, 0x39, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x08, 0x12, 0x0e, 0x08, 0x08, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x09, 0x42, 0x54, 0x40, 0x16, 0x43, 0x49, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0c, 0x0f,
++    0x42, 0x4a, 0x40, 0x0d, 0x50, 0x4a, 0x44, 0x07, 0x07, 0x07, 0x07, 0x0a, 0x32, 0x12, 0x0b, 0x07,
++    0x56, 0x27, 0x07, 0x12, 0x40, 0x02, 0x0e, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4e, 0x44, 0x4e,
++    0x50, 0x48, 0x4c, 0x56, 0x56, 0x4a, 0x4c, 0x54, 0x56, 0x56, 0x4a, 0x01, 0x03, 0x40, 0x4c, 0x4e,
++    0x44, 0x4e, 0x50, 0x48, 0x4c, 0x56, 0x56, 0x4a, 0x4c, 0x54, 0x56, 0x56, 0x4a, 0x01, 0x03, 0x40,
++    0x13, 0x4a, 0x0b, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x44, 0x44, 0x1a, 0x0c, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x05, 0x05, 0x0b, 0x13, 0x0b, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40,
++    0x40, 0x1e, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0b,
++    0x02, 0x38, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x09, 0x12, 0x0f, 0x09, 0x09, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0a, 0x41, 0x53, 0x40, 0x15, 0x44, 0x4a, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0b, 0x0f,
++    0x41, 0x48, 0x40, 0x0e, 0x4f, 0x48, 0x42, 0x09, 0x09, 0x07, 0x07, 0x09, 0x30, 0x11, 0x0c, 0x07,
++    0x55, 0x27, 0x08, 0x11, 0x40, 0x01, 0x0d, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4d, 0x43, 0x4d,
++    0x4f, 0x47, 0x4b, 0x55, 0x55, 0x48, 0x4b, 0x53, 0x55, 0x55, 0x48, 0x02, 0x04, 0x00, 0x4b, 0x4d,
++    0x43, 0x4d, 0x4f, 0x47, 0x4b, 0x55, 0x55, 0x48, 0x4b, 0x53, 0x55, 0x55, 0x48, 0x02, 0x04, 0x00,
++    0x14, 0x49, 0x0d, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x04, 0x04, 0x42, 0x43, 0x19, 0x0b, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x06, 0x06, 0x0c, 0x14, 0x0c, 0x14, 0x11, 0x17, 0x0b, 0x49, 0x17, 0x0b, 0x49, 0x40, 0x40,
++    0x40, 0x1d, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x13, 0x26, 0x27, 0x16, 0x07, 0x14, 0x16, 0x0c,
++    0x01, 0x36, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x0a, 0x11, 0x10, 0x0a, 0x0a, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0b, 0x41, 0x52, 0x40, 0x14, 0x45, 0x4b, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0a, 0x0f,
++    0x41, 0x47, 0x40, 0x0e, 0x4d, 0x47, 0x40, 0x0c, 0x0c, 0x07, 0x07, 0x09, 0x2f, 0x11, 0x0d, 0x07,
++    0x54, 0x27, 0x0a, 0x11, 0x40, 0x01, 0x0c, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4c, 0x42, 0x4c,
++    0x4d, 0x45, 0x4a, 0x54, 0x54, 0x47, 0x4a, 0x52, 0x54, 0x54, 0x47, 0x03, 0x05, 0x02, 0x4a, 0x4c,
++    0x42, 0x4c, 0x4d, 0x45, 0x4a, 0x54, 0x54, 0x47, 0x4a, 0x52, 0x54, 0x54, 0x47, 0x03, 0x05, 0x02,
++    0x15, 0x49, 0x0f, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x40, 0x42, 0x19, 0x0a, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x06, 0x06, 0x0d, 0x15, 0x0d, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40,
++    0x40, 0x1c, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0d,
++    0x01, 0x35, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x0b, 0x11, 0x12, 0x0b, 0x0b, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0c, 0x41, 0x52, 0x40, 0x13, 0x45, 0x4c, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0a, 0x0f,
++    0x41, 0x45, 0x40, 0x0e, 0x4c, 0x45, 0x01, 0x0e, 0x0e, 0x07, 0x07, 0x09, 0x2d, 0x11, 0x0d, 0x07,
++    0x53, 0x27, 0x0b, 0x11, 0x40, 0x01, 0x0b, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4b, 0x42, 0x4b,
++    0x4c, 0x44, 0x4a, 0x53, 0x53, 0x45, 0x4a, 0x52, 0x53, 0x53, 0x45, 0x04, 0x05, 0x03, 0x4a, 0x4b,
++    0x42, 0x4b, 0x4c, 0x44, 0x4a, 0x53, 0x53, 0x45, 0x4a, 0x52, 0x53, 0x53, 0x45, 0x04, 0x05, 0x03,
++    0x15, 0x49, 0x11, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x01, 0x42, 0x19, 0x0a, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x06, 0x06, 0x0d, 0x15, 0x0d, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40,
++    0x40, 0x1b, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0d,
++    0x01, 0x34, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x0c, 0x11, 0x13, 0x0c, 0x0c, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0d, 0x40, 0x51, 0x40, 0x12, 0x46, 0x4d, 0x27, 0x40, 0x40, 0x40, 0x40, 0x09, 0x0f,
++    0x40, 0x44, 0x40, 0x0f, 0x4b, 0x44, 0x03, 0x11, 0x11, 0x07, 0x07, 0x08, 0x2c, 0x10, 0x0e, 0x07,
++    0x52, 0x27, 0x0c, 0x10, 0x40, 0x00, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x4a, 0x41, 0x4a,
++    0x4b, 0x43, 0x49, 0x52, 0x52, 0x44, 0x49, 0x51, 0x52, 0x52, 0x44, 0x05, 0x06, 0x04, 0x49, 0x4a,
++    0x41, 0x4a, 0x4b, 0x43, 0x49, 0x52, 0x52, 0x44, 0x49, 0x51, 0x52, 0x52, 0x44, 0x05, 0x06, 0x04,
++    0x16, 0x48, 0x13, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x03, 0x41, 0x18, 0x09, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x07, 0x07, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x09, 0x48, 0x17, 0x09, 0x48, 0x40, 0x40,
++    0x40, 0x1a, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x11, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0e,
++    0x00, 0x33, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x0d, 0x10, 0x14, 0x0d, 0x0d, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0e, 0x40, 0x51, 0x40, 0x11, 0x47, 0x4e, 0x27, 0x40, 0x40, 0x40, 0x40, 0x08, 0x0f,
++    0x40, 0x42, 0x40, 0x0f, 0x4a, 0x42, 0x04, 0x13, 0x13, 0x07, 0x07, 0x08, 0x2a, 0x10, 0x0e, 0x07,
++    0x51, 0x27, 0x0d, 0x10, 0x40, 0x00, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x41, 0x49,
++    0x4a, 0x42, 0x49, 0x51, 0x51, 0x42, 0x49, 0x51, 0x51, 0x51, 0x42, 0x06, 0x06, 0x05, 0x49, 0x49,
++    0x41, 0x49, 0x4a, 0x42, 0x49, 0x51, 0x51, 0x42, 0x49, 0x51, 0x51, 0x51, 0x42, 0x06, 0x06, 0x05,
++    0x16, 0x48, 0x14, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x04, 0x41, 0x18, 0x08, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x07, 0x07, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40,
++    0x40, 0x19, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0e,
++    0x00, 0x31, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x0e, 0x10, 0x15, 0x0e, 0x0e, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0f, 0x40, 0x50, 0x40, 0x10, 0x47, 0x4f, 0x27, 0x40, 0x40, 0x40, 0x40, 0x08, 0x0f,
++    0x40, 0x40, 0x40, 0x0f, 0x48, 0x40, 0x06, 0x16, 0x16, 0x07, 0x07, 0x08, 0x28, 0x10, 0x0f, 0x07,
++    0x50, 0x27, 0x0f, 0x10, 0x40, 0x00, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48,
++    0x48, 0x40, 0x48, 0x50, 0x50, 0x40, 0x48, 0x50, 0x50, 0x50, 0x40, 0x07, 0x07, 0x07, 0x48, 0x48,
++    0x40, 0x48, 0x48, 0x40, 0x48, 0x50, 0x50, 0x40, 0x48, 0x50, 0x50, 0x50, 0x40, 0x07, 0x07, 0x07,
++    0x17, 0x48, 0x16, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x07, 0x07, 0x06, 0x40, 0x18, 0x08, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x07, 0x07, 0x0f, 0x17, 0x0f, 0x17, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40,
++    0x40, 0x18, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x17, 0x17, 0x0f,
++    0x00, 0x30, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x0f, 0x10, 0x17, 0x0f, 0x0f, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x10, 0x00, 0x4f, 0x40, 0x0f, 0x48, 0x50, 0x28, 0x40, 0x00, 0x40, 0x40, 0x07, 0x0f,
++    0x00, 0x00, 0x40, 0x10, 0x47, 0x00, 0x08, 0x18, 0x18, 0x07, 0x07, 0x07, 0x27, 0x0f, 0x10, 0x07,
++    0x4f, 0x27, 0x10, 0x0f, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47,
++    0x47, 0x00, 0x47, 0x4f, 0x4f, 0x00, 0x47, 0x4f, 0x4f, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47,
++    0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x4f, 0x00, 0x47, 0x4f, 0x4f, 0x4f, 0x00, 0x08, 0x08, 0x08,
++    0x18, 0x47, 0x18, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x08, 0x00, 0x17, 0x07, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40,
++    0x40, 0x17, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10,
++    0x40, 0x2f, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x10, 0x0f, 0x18, 0x10, 0x10, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x11, 0x00, 0x4f, 0x40, 0x0e, 0x48, 0x51, 0x28, 0x40, 0x00, 0x40, 0x40, 0x07, 0x0f,
++    0x00, 0x02, 0x40, 0x10, 0x46, 0x02, 0x0a, 0x1b, 0x1b, 0x07, 0x07, 0x07, 0x25, 0x0f, 0x10, 0x07,
++    0x4e, 0x27, 0x11, 0x0f, 0x40, 0x40, 0x06, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x46, 0x00, 0x46,
++    0x46, 0x01, 0x47, 0x4e, 0x4e, 0x02, 0x47, 0x4f, 0x4e, 0x4e, 0x02, 0x09, 0x08, 0x09, 0x47, 0x46,
++    0x00, 0x46, 0x46, 0x01, 0x47, 0x4e, 0x4e, 0x02, 0x47, 0x4f, 0x4e, 0x4e, 0x02, 0x09, 0x08, 0x09,
++    0x18, 0x47, 0x1a, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x0a, 0x00, 0x17, 0x07, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40,
++    0x40, 0x16, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10,
++    0x40, 0x2e, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x11, 0x0f, 0x19, 0x11, 0x11, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x12, 0x00, 0x4e, 0x40, 0x0d, 0x49, 0x52, 0x28, 0x40, 0x00, 0x40, 0x40, 0x06, 0x0f,
++    0x00, 0x03, 0x40, 0x10, 0x45, 0x03, 0x0c, 0x1d, 0x1d, 0x07, 0x07, 0x07, 0x24, 0x0f, 0x11, 0x07,
++    0x4d, 0x27, 0x12, 0x0f, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x45, 0x01, 0x45,
++    0x45, 0x02, 0x46, 0x4d, 0x4d, 0x03, 0x46, 0x4e, 0x4d, 0x4d, 0x03, 0x0a, 0x09, 0x0a, 0x46, 0x45,
++    0x01, 0x45, 0x45, 0x02, 0x46, 0x4d, 0x4d, 0x03, 0x46, 0x4e, 0x4d, 0x4d, 0x03, 0x0a, 0x09, 0x0a,
++    0x19, 0x47, 0x1c, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x09, 0x09, 0x0c, 0x01, 0x17, 0x06, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x08, 0x08, 0x11, 0x19, 0x11, 0x19, 0x0f, 0x17, 0x06, 0x47, 0x17, 0x06, 0x47, 0x40, 0x40,
++    0x40, 0x15, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x0e, 0x28, 0x27, 0x18, 0x07, 0x19, 0x18, 0x11,
++    0x40, 0x2c, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x12, 0x0f, 0x1a, 0x12, 0x12, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x13, 0x01, 0x4d, 0x40, 0x0c, 0x4a, 0x53, 0x29, 0x40, 0x01, 0x40, 0x40, 0x05, 0x0f,
++    0x01, 0x05, 0x40, 0x11, 0x43, 0x05, 0x0e, 0x20, 0x20, 0x07, 0x07, 0x06, 0x22, 0x0e, 0x12, 0x07,
++    0x4c, 0x27, 0x14, 0x0e, 0x40, 0x41, 0x04, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x44, 0x02, 0x44,
++    0x43, 0x04, 0x45, 0x4c, 0x4c, 0x05, 0x45, 0x4d, 0x4c, 0x4c, 0x05, 0x0b, 0x0a, 0x0c, 0x45, 0x44,
++    0x02, 0x44, 0x43, 0x04, 0x45, 0x4c, 0x4c, 0x05, 0x45, 0x4d, 0x4c, 0x4c, 0x05, 0x0b, 0x0a, 0x0c,
++    0x1a, 0x46, 0x1e, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x0e, 0x02, 0x16, 0x05, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x09, 0x09, 0x12, 0x1a, 0x12, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40,
++    0x40, 0x14, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x12,
++    0x41, 0x2b, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x13, 0x0e, 0x1c, 0x13, 0x13, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x14, 0x01, 0x4d, 0x40, 0x0b, 0x4a, 0x54, 0x29, 0x40, 0x01, 0x40, 0x40, 0x05, 0x0f,
++    0x01, 0x06, 0x40, 0x11, 0x42, 0x06, 0x10, 0x22, 0x22, 0x07, 0x07, 0x06, 0x21, 0x0e, 0x12, 0x07,
++    0x4b, 0x27, 0x15, 0x0e, 0x40, 0x41, 0x03, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x43, 0x02, 0x43,
++    0x42, 0x05, 0x45, 0x4b, 0x4b, 0x06, 0x45, 0x4d, 0x4b, 0x4b, 0x06, 0x0c, 0x0a, 0x0d, 0x45, 0x43,
++    0x02, 0x43, 0x42, 0x05, 0x45, 0x4b, 0x4b, 0x06, 0x45, 0x4d, 0x4b, 0x4b, 0x06, 0x0c, 0x0a, 0x0d,
++    0x1a, 0x46, 0x20, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x10, 0x02, 0x16, 0x05, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x09, 0x09, 0x12, 0x1a, 0x12, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40,
++    0x40, 0x13, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x12,
++    0x41, 0x2a, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x14, 0x0e, 0x1d, 0x14, 0x14, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x15, 0x01, 0x4c, 0x40, 0x0a, 0x4b, 0x55, 0x29, 0x40, 0x01, 0x40, 0x40, 0x04, 0x0f,
++    0x01, 0x08, 0x40, 0x11, 0x41, 0x08, 0x12, 0x25, 0x25, 0x07, 0x07, 0x06, 0x1f, 0x0e, 0x13, 0x07,
++    0x4a, 0x27, 0x16, 0x0e, 0x40, 0x41, 0x02, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x03, 0x42,
++    0x41, 0x06, 0x44, 0x4a, 0x4a, 0x08, 0x44, 0x4c, 0x4a, 0x4a, 0x08, 0x0d, 0x0b, 0x0e, 0x44, 0x42,
++    0x03, 0x42, 0x41, 0x06, 0x44, 0x4a, 0x4a, 0x08, 0x44, 0x4c, 0x4a, 0x4a, 0x08, 0x0d, 0x0b, 0x0e,
++    0x1b, 0x46, 0x22, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x12, 0x03, 0x16, 0x04, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x09, 0x09, 0x13, 0x1b, 0x13, 0x1b, 0x0e, 0x17, 0x04, 0x46, 0x17, 0x04, 0x46, 0x40, 0x40,
++    0x40, 0x12, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x0c, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x13,
++    0x41, 0x29, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x15, 0x0e, 0x1e, 0x15, 0x15, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x15, 0x01, 0x4c, 0x40, 0x09, 0x4c, 0x56, 0x29, 0x40, 0x01, 0x40, 0x40, 0x03, 0x0f,
++    0x01, 0x09, 0x40, 0x11, 0x40, 0x09, 0x13, 0x27, 0x27, 0x07, 0x07, 0x05, 0x1d, 0x0d, 0x13, 0x07,
++    0x4a, 0x27, 0x17, 0x0d, 0x40, 0x42, 0x01, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x03, 0x42,
++    0x40, 0x07, 0x44, 0x4a, 0x4a, 0x09, 0x44, 0x4c, 0x4a, 0x4a, 0x09, 0x0d, 0x0b, 0x0f, 0x44, 0x42,
++    0x03, 0x42, 0x40, 0x07, 0x44, 0x4a, 0x4a, 0x09, 0x44, 0x4c, 0x4a, 0x4a, 0x09, 0x0d, 0x0b, 0x0f,
++    0x1b, 0x46, 0x23, 0x40, 0x4a, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x13, 0x03, 0x15, 0x03, 0x46,
++    0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x4a,
++    0x07, 0x09, 0x09, 0x13, 0x1b, 0x13, 0x1b, 0x0d, 0x17, 0x03, 0x46, 0x17, 0x03, 0x46, 0x40, 0x40,
++    0x40, 0x11, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x13,
++    0x42, 0x27, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x15, 0x0d, 0x1f, 0x15, 0x15, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x16, 0x02, 0x4b, 0x40, 0x09, 0x4c, 0x56, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x03, 0x0f,
++    0x02, 0x0b, 0x40, 0x12, 0x01, 0x0b, 0x15, 0x2a, 0x2a, 0x07, 0x07, 0x05, 0x1c, 0x0d, 0x14, 0x07,
++    0x49, 0x27, 0x19, 0x0d, 0x40, 0x42, 0x01, 0x40, 0x40, 0x40, 0x02, 0x02, 0x43, 0x41, 0x04, 0x41,
++    0x01, 0x09, 0x43, 0x49, 0x49, 0x0b, 0x43, 0x4b, 0x49, 0x49, 0x0b, 0x0e, 0x0c, 0x11, 0x43, 0x41,
++    0x04, 0x41, 0x01, 0x09, 0x43, 0x49, 0x49, 0x0b, 0x43, 0x4b, 0x49, 0x49, 0x0b, 0x0e, 0x0c, 0x11,
++    0x1c, 0x45, 0x25, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0c, 0x0c, 0x15, 0x04, 0x15, 0x03, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0a, 0x0a, 0x14, 0x1c, 0x14, 0x1c, 0x0d, 0x17, 0x03, 0x45, 0x17, 0x03, 0x45, 0x40, 0x40,
++    0x40, 0x11, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x2a, 0x27, 0x1a, 0x07, 0x1c, 0x1a, 0x14,
++    0x42, 0x26, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x16, 0x0d, 0x21, 0x16, 0x16, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x17, 0x02, 0x4a, 0x40, 0x08, 0x4d, 0x57, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x02, 0x0f,
++    0x02, 0x0d, 0x40, 0x12, 0x02, 0x0d, 0x17, 0x2c, 0x2c, 0x07, 0x07, 0x05, 0x1a, 0x0d, 0x15, 0x07,
++    0x48, 0x27, 0x1a, 0x0d, 0x40, 0x42, 0x00, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x40, 0x05, 0x40,
++    0x02, 0x0a, 0x42, 0x48, 0x48, 0x0d, 0x42, 0x4a, 0x48, 0x48, 0x0d, 0x0f, 0x0d, 0x12, 0x42, 0x40,
++    0x05, 0x40, 0x02, 0x0a, 0x42, 0x48, 0x48, 0x0d, 0x42, 0x4a, 0x48, 0x48, 0x0d, 0x0f, 0x0d, 0x12,
++    0x1d, 0x45, 0x27, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x17, 0x05, 0x15, 0x02, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0a, 0x0a, 0x15, 0x1d, 0x15, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40,
++    0x40, 0x10, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x15,
++    0x42, 0x25, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x17, 0x0d, 0x22, 0x17, 0x17, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x18, 0x02, 0x4a, 0x40, 0x07, 0x4d, 0x58, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x02, 0x0f,
++    0x02, 0x0e, 0x40, 0x12, 0x03, 0x0e, 0x19, 0x2f, 0x2f, 0x07, 0x07, 0x05, 0x19, 0x0d, 0x15, 0x07,
++    0x47, 0x27, 0x1b, 0x0d, 0x40, 0x42, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x00, 0x05, 0x00,
++    0x03, 0x0b, 0x42, 0x47, 0x47, 0x0e, 0x42, 0x4a, 0x47, 0x47, 0x0e, 0x10, 0x0d, 0x13, 0x42, 0x00,
++    0x05, 0x00, 0x03, 0x0b, 0x42, 0x47, 0x47, 0x0e, 0x42, 0x4a, 0x47, 0x47, 0x0e, 0x10, 0x0d, 0x13,
++    0x1d, 0x45, 0x29, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x19, 0x05, 0x15, 0x02, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0a, 0x0a, 0x15, 0x1d, 0x15, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40,
++    0x40, 0x0f, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x15,
++    0x42, 0x24, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x18, 0x0d, 0x23, 0x18, 0x18, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x19, 0x03, 0x49, 0x40, 0x06, 0x4e, 0x59, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x01, 0x0f,
++    0x03, 0x10, 0x40, 0x13, 0x04, 0x10, 0x1b, 0x31, 0x31, 0x07, 0x07, 0x04, 0x17, 0x0c, 0x16, 0x07,
++    0x46, 0x27, 0x1c, 0x0c, 0x40, 0x43, 0x41, 0x40, 0x40, 0x40, 0x03, 0x03, 0x41, 0x01, 0x06, 0x01,
++    0x04, 0x0c, 0x41, 0x46, 0x46, 0x10, 0x41, 0x49, 0x46, 0x46, 0x10, 0x11, 0x0e, 0x14, 0x41, 0x01,
++    0x06, 0x01, 0x04, 0x0c, 0x41, 0x46, 0x46, 0x10, 0x41, 0x49, 0x46, 0x46, 0x10, 0x11, 0x0e, 0x14,
++    0x1e, 0x44, 0x2b, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0e, 0x0e, 0x1b, 0x06, 0x14, 0x01, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0b, 0x0b, 0x16, 0x1e, 0x16, 0x1e, 0x0c, 0x17, 0x01, 0x44, 0x17, 0x01, 0x44, 0x40, 0x40,
++    0x40, 0x0e, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x09, 0x2b, 0x27, 0x1b, 0x07, 0x1e, 0x1b, 0x16,
++    0x43, 0x22, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x19, 0x0c, 0x24, 0x19, 0x19, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1a, 0x03, 0x48, 0x40, 0x05, 0x4f, 0x5a, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x00, 0x0f,
++    0x03, 0x11, 0x40, 0x13, 0x06, 0x11, 0x1d, 0x34, 0x34, 0x07, 0x07, 0x04, 0x16, 0x0c, 0x17, 0x07,
++    0x45, 0x27, 0x1e, 0x0c, 0x40, 0x43, 0x42, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x02, 0x07, 0x02,
++    0x06, 0x0e, 0x40, 0x45, 0x45, 0x11, 0x40, 0x48, 0x45, 0x45, 0x11, 0x12, 0x0f, 0x16, 0x40, 0x02,
++    0x07, 0x02, 0x06, 0x0e, 0x40, 0x45, 0x45, 0x11, 0x40, 0x48, 0x45, 0x45, 0x11, 0x12, 0x0f, 0x16,
++    0x1f, 0x44, 0x2d, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1d, 0x07, 0x14, 0x00, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0b, 0x0b, 0x17, 0x1f, 0x17, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40,
++    0x40, 0x0d, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x17,
++    0x43, 0x21, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x1a, 0x0c, 0x26, 0x1a, 0x1a, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1b, 0x03, 0x48, 0x40, 0x04, 0x4f, 0x5b, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x00, 0x0f,
++    0x03, 0x13, 0x40, 0x13, 0x07, 0x13, 0x1f, 0x36, 0x36, 0x07, 0x07, 0x04, 0x14, 0x0c, 0x17, 0x07,
++    0x44, 0x27, 0x1f, 0x0c, 0x40, 0x43, 0x43, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x03, 0x07, 0x03,
++    0x07, 0x0f, 0x40, 0x44, 0x44, 0x13, 0x40, 0x48, 0x44, 0x44, 0x13, 0x13, 0x0f, 0x17, 0x40, 0x03,
++    0x07, 0x03, 0x07, 0x0f, 0x40, 0x44, 0x44, 0x13, 0x40, 0x48, 0x44, 0x44, 0x13, 0x13, 0x0f, 0x17,
++    0x1f, 0x44, 0x2f, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1f, 0x07, 0x14, 0x00, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0b, 0x0b, 0x17, 0x1f, 0x17, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40,
++    0x40, 0x0c, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x17,
++    0x43, 0x20, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x1b, 0x0c, 0x27, 0x1b, 0x1b, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1c, 0x04, 0x47, 0x40, 0x03, 0x50, 0x5c, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f,
++    0x04, 0x14, 0x40, 0x14, 0x08, 0x14, 0x21, 0x39, 0x39, 0x07, 0x07, 0x03, 0x13, 0x0b, 0x18, 0x07,
++    0x43, 0x27, 0x20, 0x0b, 0x40, 0x44, 0x44, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x04, 0x08, 0x04,
++    0x08, 0x10, 0x00, 0x43, 0x43, 0x14, 0x00, 0x47, 0x43, 0x43, 0x14, 0x14, 0x10, 0x18, 0x00, 0x04,
++    0x08, 0x04, 0x08, 0x10, 0x00, 0x43, 0x43, 0x14, 0x00, 0x47, 0x43, 0x43, 0x14, 0x14, 0x10, 0x18,
++    0x20, 0x43, 0x31, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x21, 0x08, 0x13, 0x40, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x0c, 0x0c, 0x18, 0x20, 0x18, 0x20, 0x0b, 0x17, 0x40, 0x43, 0x17, 0x40, 0x43, 0x40, 0x40,
++    0x40, 0x0b, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x07, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x18,
++    0x44, 0x1f, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x1c, 0x0b, 0x28, 0x1c, 0x1c, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1d, 0x04, 0x47, 0x40, 0x02, 0x51, 0x5d, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x41, 0x0f,
++    0x04, 0x16, 0x40, 0x14, 0x09, 0x16, 0x22, 0x3b, 0x3b, 0x07, 0x07, 0x03, 0x11, 0x0b, 0x18, 0x07,
++    0x42, 0x27, 0x21, 0x0b, 0x40, 0x44, 0x45, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x05, 0x08, 0x05,
++    0x09, 0x11, 0x00, 0x42, 0x42, 0x16, 0x00, 0x47, 0x42, 0x42, 0x16, 0x15, 0x10, 0x19, 0x00, 0x05,
++    0x08, 0x05, 0x09, 0x11, 0x00, 0x42, 0x42, 0x16, 0x00, 0x47, 0x42, 0x42, 0x16, 0x15, 0x10, 0x19,
++    0x20, 0x43, 0x32, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x22, 0x08, 0x13, 0x41, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x0c, 0x0c, 0x18, 0x20, 0x18, 0x20, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40,
++    0x40, 0x0a, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x18,
++    0x44, 0x1d, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x1d, 0x0b, 0x29, 0x1d, 0x1d, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1e, 0x04, 0x46, 0x40, 0x01, 0x51, 0x5e, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x41, 0x0f,
++    0x04, 0x18, 0x40, 0x14, 0x0b, 0x18, 0x24, 0x3e, 0x3e, 0x07, 0x07, 0x03, 0x0f, 0x0b, 0x19, 0x07,
++    0x41, 0x27, 0x23, 0x0b, 0x40, 0x44, 0x46, 0x40, 0x40, 0x40, 0x04, 0x04, 0x01, 0x06, 0x09, 0x06,
++    0x0b, 0x13, 0x01, 0x41, 0x41, 0x18, 0x01, 0x46, 0x41, 0x41, 0x18, 0x16, 0x11, 0x1b, 0x01, 0x06,
++    0x09, 0x06, 0x0b, 0x13, 0x01, 0x41, 0x41, 0x18, 0x01, 0x46, 0x41, 0x41, 0x18, 0x16, 0x11, 0x1b,
++    0x21, 0x43, 0x34, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x11, 0x11, 0x24, 0x09, 0x13, 0x41, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x0c, 0x0c, 0x19, 0x21, 0x19, 0x21, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40,
++    0x40, 0x09, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x21, 0x1c, 0x19,
++    0x44, 0x1c, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x1e, 0x0b, 0x2b, 0x1e, 0x1e, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1f, 0x05, 0x45, 0x40, 0x00, 0x52, 0x5f, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x42, 0x0f,
++    0x05, 0x19, 0x40, 0x15, 0x0c, 0x19, 0x26, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0e, 0x0a, 0x1a, 0x07,
++    0x40, 0x27, 0x24, 0x0a, 0x40, 0x45, 0x47, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x07, 0x0a, 0x07,
++    0x0c, 0x14, 0x02, 0x40, 0x40, 0x19, 0x02, 0x45, 0x40, 0x40, 0x19, 0x17, 0x12, 0x1c, 0x02, 0x07,
++    0x0a, 0x07, 0x0c, 0x14, 0x02, 0x40, 0x40, 0x19, 0x02, 0x45, 0x40, 0x40, 0x19, 0x17, 0x12, 0x1c,
++    0x22, 0x42, 0x36, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x26, 0x0a, 0x12, 0x42, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x0d, 0x0d, 0x1a, 0x22, 0x1a, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40,
++    0x40, 0x08, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a,
++    0x45, 0x1b, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x1f, 0x0a, 0x2c, 0x1f, 0x1f, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x20, 0x05, 0x45, 0x40, 0x40, 0x52, 0x60, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x42, 0x0f,
++    0x05, 0x1b, 0x40, 0x15, 0x0d, 0x1b, 0x28, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0c, 0x0a, 0x1a, 0x07,
++    0x00, 0x27, 0x25, 0x0a, 0x40, 0x45, 0x48, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x08, 0x0a, 0x08,
++    0x0d, 0x15, 0x02, 0x00, 0x00, 0x1b, 0x02, 0x45, 0x00, 0x00, 0x1b, 0x18, 0x12, 0x1d, 0x02, 0x08,
++    0x0a, 0x08, 0x0d, 0x15, 0x02, 0x00, 0x00, 0x1b, 0x02, 0x45, 0x00, 0x00, 0x1b, 0x18, 0x12, 0x1d,
++    0x22, 0x42, 0x38, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x28, 0x0a, 0x12, 0x42, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x0d, 0x0d, 0x1a, 0x22, 0x1a, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40,
++    0x40, 0x07, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a,
++    0x45, 0x1a, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x20, 0x0a, 0x2d, 0x20, 0x20, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x21, 0x05, 0x44, 0x40, 0x41, 0x53, 0x61, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x43, 0x0f,
++    0x05, 0x1c, 0x40, 0x15, 0x0e, 0x1c, 0x2a, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0a, 0x1b, 0x07,
++    0x01, 0x27, 0x26, 0x0a, 0x40, 0x45, 0x49, 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x0b, 0x09,
++    0x0e, 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e, 0x03, 0x09,
++    0x0b, 0x09, 0x0e, 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e,
++    0x23, 0x42, 0x3a, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x0b, 0x12, 0x43, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x0d, 0x0d, 0x1b, 0x23, 0x1b, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, 0x40,
++    0x40, 0x06, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, 0x1d, 0x1b,
++    0x45, 0x18, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x21, 0x0a, 0x2e, 0x21, 0x21, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f,
++    0x06, 0x1e, 0x40, 0x16, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x09, 0x09, 0x1c, 0x07,
++    0x02, 0x27, 0x28, 0x09, 0x40, 0x46, 0x4a, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0a, 0x0c, 0x0a,
++    0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20, 0x04, 0x0a,
++    0x0c, 0x0a, 0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20,
++    0x24, 0x41, 0x3c, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2c, 0x0c, 0x11, 0x44, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
++    0x40, 0x05, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c,
++    0x46, 0x17, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x22, 0x09, 0x30, 0x22, 0x22, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f,
++    0x06, 0x1f, 0x40, 0x16, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x08, 0x09, 0x1c, 0x07,
++    0x03, 0x27, 0x29, 0x09, 0x40, 0x46, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x0c, 0x0b,
++    0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21, 0x04, 0x0b,
++    0x0c, 0x0b, 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21,
++    0x24, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, 0x0c, 0x11, 0x44, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
++    0x40, 0x04, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c,
++    0x46, 0x16, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x23, 0x09, 0x31, 0x23, 0x23, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x44, 0x55, 0x64, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x45, 0x0f,
++    0x06, 0x21, 0x40, 0x16, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x06, 0x09, 0x1d, 0x07,
++    0x04, 0x27, 0x2a, 0x09, 0x40, 0x46, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c,
++    0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22, 0x05, 0x0c,
++    0x0d, 0x0c, 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22,
++    0x25, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x0d, 0x11, 0x45, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, 0x40, 0x40,
++    0x40, 0x03, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d,
++    0x46, 0x15, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x24, 0x09, 0x32, 0x24, 0x24, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x46, 0x0f,
++    0x06, 0x22, 0x40, 0x16, 0x13, 0x22, 0x31, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x04, 0x08, 0x1d, 0x07,
++    0x04, 0x27, 0x2b, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c,
++    0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x05, 0x0c,
++    0x0d, 0x0c, 0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23,
++    0x25, 0x41, 0x3e, 0x40, 0x4f, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x0d, 0x10, 0x46, 0x41,
++    0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f,
++    0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40,
++    0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d,
++    0x47, 0x13, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x24, 0x08, 0x33, 0x24, 0x24, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x46, 0x0f,
++    0x07, 0x24, 0x40, 0x17, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x03, 0x08, 0x1e, 0x07,
++    0x05, 0x27, 0x2d, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x0e, 0x0d,
++    0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, 0x06, 0x0d,
++    0x0e, 0x0d, 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25,
++    0x26, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x0e, 0x10, 0x46, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x0f, 0x0f, 0x1e, 0x26, 0x1e, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40,
++    0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x1e,
++    0x47, 0x12, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x25, 0x08, 0x35, 0x25, 0x25, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
++    0x07, 0x26, 0x40, 0x17, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x01, 0x08, 0x1f, 0x07,
++    0x06, 0x27, 0x2e, 0x08, 0x40, 0x47, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x0f, 0x0e,
++    0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26, 0x07, 0x0e,
++    0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26,
++    0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x0f, 0x10, 0x47, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
++    0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f,
++    0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
++    0x07, 0x27, 0x40, 0x17, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07,
++    0x07, 0x27, 0x2f, 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f,
++    0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f,
++    0x0f, 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27,
++    0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
++    0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f,
++    0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, 0x27, 0x27, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++};
++
++static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
++{
++	u8 bit = field.offset % 32, word = field.offset / 32;
++	u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
++	u64 val = ((u64)value << bit) & mask;
++
++	buf[word] &= ~mask;
++	buf[word] |= val;
++	if (bit + field.len > 32) {
++		buf[word + 1] &= ~(mask >> 32);
++		buf[word + 1] |= val >> 32;
++	}
++}
++
++static void assemble_hw_pps(struct rkvdec_ctx *ctx,
++			    struct rkvdec_hevc_run *run)
++{
++	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
++	const struct v4l2_ctrl_hevc_sps *sps = run->sps;
++	const struct v4l2_ctrl_hevc_pps *pps = run->pps;
++	struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
++	struct rkvdec_sps_pps_packet *hw_ps;
++	u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
++	u32 log2_min_cu_qp_delta_size;
++	dma_addr_t scaling_list_address;
++	u32 scaling_distance;
++	int i;
++
++	/*
++	 * HW read the SPS/PPS information from PPS packet index by PPS id.
++	 * offset from the base can be calculated by PPS_id * 80 (size per PPS
++	 * packet unit). so the driver copy SPS/PPS information to the exact PPS
++	 * packet unit for HW accessing.
++	 */
++	hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
++	memset(hw_ps, 0, sizeof(*hw_ps));
++
++	min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
++	ctb_log2_size_y = min_cb_log2_size_y +
++	    sps->log2_diff_max_min_luma_coding_block_size;
++	ctb_size_y = 1 << ctb_log2_size_y;
++
++#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
++	/* write sps */
++	WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
++	WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
++	WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
++	WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
++	WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
++	WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
++	WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
++	WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
++		  LOG2_MAX_PIC_ORDER_CNT_LSB);
++	WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
++		  LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
++	WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
++		  LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
++	WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
++		  LOG2_MIN_TRANSFORM_BLOCK_SIZE);
++	WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
++		  LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
++	WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
++		  MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
++	WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
++		  MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
++		  SCALING_LIST_ENABLED_FLAG);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
++		  AMP_ENABLED_FLAG);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
++		  SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
++	if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
++		WRITE_PPS(1, PCM_ENABLED_FLAG);
++		WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1,
++			  PCM_SAMPLE_BIT_DEPTH_LUMA);
++		WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1,
++			  PCM_SAMPLE_BIT_DEPTH_CHROMA);
++		WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
++			  PCM_LOOP_FILTER_DISABLED_FLAG);
++		WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
++			  LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
++		WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3,
++			  LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
++	}
++	WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
++		  LONG_TERM_REF_PICS_PRESENT_FLAG);
++	WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
++		  SPS_TEMPORAL_MVP_ENABLED_FLAG);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
++		  STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
++
++	/* write pps */
++	WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
++	WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
++		  DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
++		  OUTPUT_FLAG_PRESENT_FLAG);
++	WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
++		  SIGN_DATA_HIDING_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
++		  CABAC_INIT_PRESENT_FLAG);
++	WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
++		  NUM_REF_IDX_L0_DEFAULT_ACTIVE);
++	WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
++		  NUM_REF_IDX_L1_DEFAULT_ACTIVE);
++	WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
++		  CONSTRAINED_INTRA_PRED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
++		  TRANSFORM_SKIP_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
++		  CU_QP_DELTA_ENABLED_FLAG);
++
++	log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
++	WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
++
++	WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
++	WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
++		  PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
++		  WEIGHTED_PRED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
++		  WEIGHTED_BIPRED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
++		  TRANSQUANT_BYPASS_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
++		  TILES_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
++		  ENTROPY_CODING_SYNC_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
++		  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
++		  LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
++		  DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
++		  PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
++	WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
++	WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
++		  LISTS_MODIFICATION_PRESENT_FLAG);
++	WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
++		  SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
++	WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
++	WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
++
++	if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
++		for (i = 0; i <= pps->num_tile_columns_minus1; i++)
++			WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i));
++		for (i = 0; i <= pps->num_tile_rows_minus1; i++)
++			WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));
++	} else {
++		WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
++			  COLUMN_WIDTH(0));
++		WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
++			  ROW_HEIGHT(0));
++	}
++
++	scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
++	scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
++	WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
++}
++
++static void assemble_hw_rps(struct rkvdec_ctx *ctx,
++			    struct rkvdec_hevc_run *run)
++{
++	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
++	const struct v4l2_ctrl_hevc_slice_params *sl_params;
++	const struct v4l2_hevc_dpb_entry *dpb;
++	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
++	struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
++	struct rkvdec_rps_packet *hw_ps;
++	int i, j;
++	unsigned int lowdelay;
++
++#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
++
++#define REF_PIC_LONG_TERM_L0(i)			PS_FIELD(i * 5, 1)
++#define REF_PIC_IDX_L0(i)			PS_FIELD(1 + (i * 5), 4)
++#define REF_PIC_LONG_TERM_L1(i)			PS_FIELD((i < 5 ? 75 : 132) + (i * 5), 1)
++#define REF_PIC_IDX_L1(i)			PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4)
++
++#define LOWDELAY				PS_FIELD(182, 1)
++#define LONG_TERM_RPS_BIT_OFFSET		PS_FIELD(183, 10)
++#define SHORT_TERM_RPS_BIT_OFFSET		PS_FIELD(193, 9)
++#define NUM_RPS_POC				PS_FIELD(202, 4)
++
++	for (j = 0; j < run->num_slices; j++) {
++		sl_params = &run->slices_params[j];
++		dpb = decode_params->dpb;
++		lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1;
++
++		hw_ps = &priv_tbl->rps[j];
++		memset(hw_ps, 0, sizeof(*hw_ps));
++
++		for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) {
++			WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
++				  REF_PIC_LONG_TERM_L0(i));
++			WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
++
++			if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt)
++				lowdelay = 0;
++
++		}
++
++		for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) {
++			WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
++				  REF_PIC_LONG_TERM_L1(i));
++			WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
++
++			if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt)
++				lowdelay = 0;
++		}
++
++		WRITE_RPS(lowdelay, LOWDELAY);
++
++		WRITE_RPS(sl_params->long_term_ref_pic_set_size +
++			  sl_params->short_term_ref_pic_set_size,
++			  LONG_TERM_RPS_BIT_OFFSET);
++		WRITE_RPS(sl_params->short_term_ref_pic_set_size,
++			  SHORT_TERM_RPS_BIT_OFFSET);
++
++		WRITE_RPS(decode_params->num_poc_st_curr_before +
++			  decode_params->num_poc_st_curr_after +
++			  decode_params->num_poc_lt_curr,
++			  NUM_RPS_POC);
++	}
++}
++
++static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx,
++				     struct rkvdec_hevc_run *run)
++{
++	const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix;
++	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
++	struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
++	u8 *dst;
++	scalingList_t sl;
++	int i, j;
++
++	if (!memcmp((void*)&hevc_ctx->scaling_matrix_cache, scaling,
++		    sizeof(struct v4l2_ctrl_hevc_scaling_matrix)))
++		return;
++
++	memset(&sl, 0, sizeof(scalingList_t));
++
++	for (i = 0; i < 6; i++) {
++		for (j = 0; j < 16; j++)
++			sl.sl[0][i][j] = scaling->scaling_list_4x4[i][j];
++		for (j = 0; j < 64; j++) {
++			sl.sl[1][i][j] = scaling->scaling_list_8x8[i][j];
++			sl.sl[2][i][j] = scaling->scaling_list_16x16[i][j];
++		if (i < 2)
++			sl.sl[3][i][j] = scaling->scaling_list_32x32[i][j];
++		}
++		sl.sl_dc[0][i] = scaling->scaling_list_dc_coef_16x16[i];
++		if (i < 2)
++			sl.sl_dc[1][i] = scaling->scaling_list_dc_coef_32x32[i];
++	}
++
++	dst = tbl->scaling_list;
++	hal_record_scaling_list((scalingFactor_t *)dst, &sl);
++
++	memcpy((void*)&hevc_ctx->scaling_matrix_cache, scaling,
++	       sizeof(struct v4l2_ctrl_hevc_scaling_matrix));
++}
++
++static struct vb2_buffer *
++get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run,
++	    unsigned int dpb_idx)
++{
++	struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
++	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
++	const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
++	struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
++	struct vb2_buffer *vb2_buf = NULL;
++
++	if (dpb_idx < decode_params->num_active_dpb_entries)
++		vb2_buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp);
++
++	/*
++	 * If a DPB entry is unused or invalid, address of current destination
++	 * buffer is returned.
++	 */
++	if (!vb2_buf)
++		return &run->base.bufs.dst->vb2_buf;
++
++	return vb2_buf;
++}
++
++static void config_registers(struct rkvdec_ctx *ctx,
++			     struct rkvdec_hevc_run *run)
++{
++	struct rkvdec_dev *rkvdec = ctx->dev;
++	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
++	const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
++	const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
++	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
++	dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
++	const struct v4l2_pix_format_mplane *dst_fmt;
++	struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
++	struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
++	const struct v4l2_format *f;
++	dma_addr_t rlc_addr;
++	dma_addr_t refer_addr;
++	u32 rlc_len;
++	u32 hor_virstride;
++	u32 ver_virstride;
++	u32 y_virstride;
++	u32 uv_virstride;
++	u32 yuv_virstride;
++	u32 offset;
++	dma_addr_t dst_addr;
++	u32 reg, i;
++
++	reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
++
++	f = &ctx->decoded_fmt;
++	dst_fmt = &f->fmt.pix_mp;
++	hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
++	ver_virstride = dst_fmt->height;
++	y_virstride = hor_virstride * ver_virstride;
++	uv_virstride = y_virstride / 2;
++	yuv_virstride = y_virstride + uv_virstride;
++
++	reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
++	      RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
++	      RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
++
++	/* config rlc base address */
++	rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
++	writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
++
++	rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
++	reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
++
++	/* config cabac table */
++	offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
++	writel_relaxed(priv_start_addr + offset,
++		       rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
++
++	/* config output base address */
++	dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
++	writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
++
++	reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
++
++	reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
++
++	/* config ref pic address */
++	for (i = 0; i < 15; i++) {
++		struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
++
++		if (i < 4 && decode_params->num_active_dpb_entries) {
++			reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);
++			reg = (reg >> (i * 4)) & 0xf;
++		} else
++			reg = 0;
++
++		refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
++		writel_relaxed(refer_addr | reg,
++			       rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
++
++		reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0);
++		writel_relaxed(reg,
++			       rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
++	}
++
++	reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
++
++	/* config hw pps address */
++	offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
++	writel_relaxed(priv_start_addr + offset,
++		       rkvdec->regs + RKVDEC_REG_PPS_BASE);
++
++	/* config hw rps address */
++	offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
++	writel_relaxed(priv_start_addr + offset,
++		       rkvdec->regs + RKVDEC_REG_RPS_BASE);
++
++	reg = RKVDEC_AXI_DDR_RDATA(0);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
++
++	reg = RKVDEC_AXI_DDR_WDATA(0);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
++}
++
++#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES		2
++
++static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx,
++				  struct v4l2_format *f)
++{
++	struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
++
++	fmt->num_planes = 1;
++	if (!fmt->plane_fmt[0].sizeimage)
++		fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
++					      RKVDEC_HEVC_MAX_DEPTH_IN_BYTES;
++	return 0;
++}
++
++static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx,
++				    const struct v4l2_ctrl_hevc_sps *sps)
++{
++	if (sps->chroma_format_idc > 1)
++		/* Only 4:0:0 and 4:2:0 are supported */
++		return -EINVAL;
++	if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
++		/* Luma and chroma bit depth mismatch */
++		return -EINVAL;
++	if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
++		/* Only 8-bit and 10-bit is supported */
++		return -EINVAL;
++
++	if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width ||
++	    sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height)
++		return -EINVAL;
++
++	return 0;
++}
++
++static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
++{
++	const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
++
++	if (sps->bit_depth_luma_minus8 == 2)
++		return V4L2_PIX_FMT_NV15;
++	else
++		return V4L2_PIX_FMT_NV12;
++}
++
++static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
++{
++	struct rkvdec_dev *rkvdec = ctx->dev;
++	struct rkvdec_hevc_priv_tbl *priv_tbl;
++	struct rkvdec_hevc_ctx *hevc_ctx;
++	struct v4l2_ctrl *ctrl;
++	int ret;
++
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_SPS);
++	if (!ctrl)
++		return -EINVAL;
++
++	ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
++	if (ret)
++		return ret;
++
++	hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL);
++	if (!hevc_ctx)
++		return -ENOMEM;
++
++
++	priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
++				      &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
++	if (!priv_tbl) {
++		ret = -ENOMEM;
++		goto err_free_ctx;
++	}
++
++	hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
++	hevc_ctx->priv_tbl.cpu = priv_tbl;
++	memset(priv_tbl, 0, sizeof(*priv_tbl));
++	memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table,
++	       sizeof(rkvdec_hevc_cabac_table));
++
++	ctx->priv = hevc_ctx;
++	return 0;
++
++err_free_ctx:
++	kfree(hevc_ctx);
++	return ret;
++}
++
++static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
++{
++	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
++	struct rkvdec_dev *rkvdec = ctx->dev;
++
++	dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
++			  hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
++	kfree(hevc_ctx);
++}
++
++static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx,
++				     struct rkvdec_hevc_run *run)
++{
++	struct v4l2_ctrl *ctrl;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
++	run->decode_params = ctrl ? ctrl->p_cur.p : NULL;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_SLICE_PARAMS);
++	run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
++	run->num_slices = ctrl->new_elems;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_SPS);
++	run->sps = ctrl ? ctrl->p_cur.p : NULL;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_PPS);
++	run->pps = ctrl ? ctrl->p_cur.p : NULL;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
++	run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
++
++	rkvdec_run_preamble(ctx, &run->base);
++}
++
++static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
++{
++	struct rkvdec_dev *rkvdec = ctx->dev;
++	struct rkvdec_hevc_run run;
++
++	rkvdec_hevc_run_preamble(ctx, &run);
++
++	assemble_hw_scaling_list(ctx, &run);
++	assemble_hw_pps(ctx, &run);
++	assemble_hw_rps(ctx, &run);
++	config_registers(ctx, &run);
++
++	rkvdec_run_postamble(ctx, &run.base);
++
++	// sw_cabac_error_e - cabac error enable
++	writel_relaxed(0xfdfffffd, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
++	// slice end error enable = BIT(28)
++	// frame end error enable = BIT(29)
++	writel_relaxed(0x30000000, rkvdec->regs + RKVDEC_REG_H264_ERR_E);
++
++	schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
++
++	writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
++	writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
++
++	/* Start decoding! */
++	writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
++	       RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
++	       rkvdec->regs + RKVDEC_REG_INTERRUPT);
++
++	return 0;
++}
++
++static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
++{
++	if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS)
++		return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
++
++	return 0;
++}
++
++const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
++	.adjust_fmt = rkvdec_hevc_adjust_fmt,
++	.start = rkvdec_hevc_start,
++	.stop = rkvdec_hevc_stop,
++	.run = rkvdec_hevc_run,
++	.try_ctrl = rkvdec_hevc_try_ctrl,
++	.valid_fmt = rkvdec_hevc_valid_fmt,
++};
+diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
+index 265f5234f4eb..4319ee3ccbbc 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
+@@ -48,6 +48,7 @@
+ #define RKVDEC_RLC_MODE					BIT(11)
+ #define RKVDEC_STRM_START_BIT(x)			(((x) & 0x7f) << 12)
+ #define RKVDEC_MODE(x)					(((x) & 0x03) << 20)
++#define RKVDEC_MODE_HEVC				0
+ #define RKVDEC_MODE_H264				1
+ #define RKVDEC_MODE_VP9					2
+ #define RKVDEC_RPS_MODE					BIT(24)
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index f55abb7c377f..00a9bf583596 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
+ {
+ 	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
+ 
+-	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) {
++	if (!ctx->valid_fmt) {
+ 		ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl);
+ 		if (ctx->valid_fmt) {
+ 			struct v4l2_pix_format_mplane *pix_mp;
+@@ -134,6 +134,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
+ 	},
+ };
+ 
++static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS,
++		.cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY,
++		.cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS,
++		.cfg.dims = { 600 },
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_SPS,
++		.cfg.ops = &rkvdec_ctrl_ops,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_PPS,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
++		.cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
++		.cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
++		.cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE,
++		.cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
++		.cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
++		.cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
++	},
++	{
++		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
++		.cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
++		.cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
++		.cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
++	},
++	{
++		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
++		.cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
++		.cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
++	},
++};
++
++static const struct rkvdec_ctrls rkvdec_hevc_ctrls = {
++	.ctrls = rkvdec_hevc_ctrl_descs,
++	.num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs),
++};
++
++static const u32 rkvdec_hevc_decoded_fmts[] = {
++	V4L2_PIX_FMT_NV12,
++	V4L2_PIX_FMT_NV15,
++};
++
++
+ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
+ 	.ctrls = rkvdec_h264_ctrl_descs,
+ 	.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
+@@ -187,6 +243,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 		.decoded_fmts = rkvdec_h264_decoded_fmts,
+ 		.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+ 	},
++	{
++		.fourcc = V4L2_PIX_FMT_HEVC_SLICE,
++		.frmsize = {
++			.min_width = 64,
++			.max_width = 4096,
++			.step_width = 64,
++			.min_height = 64,
++			.max_height = 2304,
++			.step_height = 16,
++		},
++		.ctrls = &rkvdec_hevc_ctrls,
++		.ops = &rkvdec_hevc_fmt_ops,
++		.num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
++		.decoded_fmts = rkvdec_hevc_decoded_fmts,
++	},
+ 	{
+ 		.fourcc = V4L2_PIX_FMT_VP9_FRAME,
+ 		.frmsize = {
+diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
+index f02f79c405f0..d6222a2588be 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.h
++++ b/drivers/staging/media/rkvdec/rkvdec.h
+@@ -133,6 +133,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
+ void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
+ 
+ extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
++extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops;
+ extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
+ 
+ #endif /* RKVDEC_H_ */
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 30 Jan 2021 18:16:39 +0100
+Subject: [PATCH] media: rkvdec: add variants support
+
+rkvdec IP has different versions which among others differ in
+the supported decoding formats.
+This adds an variant implementation in order support other
+than the currently supported RK3399 version.
+
+Note: Since matching of supported codecs is index-based the
+available codec options have been reordered here: from
+supported by all versions to not commonly supported. This seems
+the better soultion than duplicatiing code for every newly added IP.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/staging/media/rkvdec/rkvdec.c | 105 ++++++++++++++++++--------
+ drivers/staging/media/rkvdec/rkvdec.h |  10 +++
+ 2 files changed, 85 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index 00a9bf583596..955c53afe20f 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -14,6 +14,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm.h>
+ #include <linux/pm_runtime.h>
+@@ -227,6 +228,22 @@ static const u32 rkvdec_vp9_decoded_fmts[] = {
+ };
+ 
+ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
++	{
++		.fourcc = V4L2_PIX_FMT_HEVC_SLICE,
++		.frmsize = {
++			.min_width = 64,
++			.max_width = 4096,
++			.step_width = 64,
++			.min_height = 64,
++			.max_height = 2304,
++			.step_height = 16,
++		},
++		.ctrls = &rkvdec_hevc_ctrls,
++		.ops = &rkvdec_hevc_fmt_ops,
++		.num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
++		.decoded_fmts = rkvdec_hevc_decoded_fmts,
++		.capability = RKVDEC_CAPABILITY_HEVC,
++	},
+ 	{
+ 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
+ 		.frmsize = {
+@@ -242,21 +259,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
+ 		.decoded_fmts = rkvdec_h264_decoded_fmts,
+ 		.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+-	},
+-	{
+-		.fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+-		.frmsize = {
+-			.min_width = 64,
+-			.max_width = 4096,
+-			.step_width = 64,
+-			.min_height = 64,
+-			.max_height = 2304,
+-			.step_height = 16,
+-		},
+-		.ctrls = &rkvdec_hevc_ctrls,
+-		.ops = &rkvdec_hevc_fmt_ops,
+-		.num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
+-		.decoded_fmts = rkvdec_hevc_decoded_fmts,
++		.capability = RKVDEC_CAPABILITY_H264,
+ 	},
+ 	{
+ 		.fourcc = V4L2_PIX_FMT_VP9_FRAME,
+@@ -272,16 +275,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 		.ops = &rkvdec_vp9_fmt_ops,
+ 		.num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
+ 		.decoded_fmts = rkvdec_vp9_decoded_fmts,
+-	}
++		.capability = RKVDEC_CAPABILITY_VP9,
++	},
+ };
+ 
+ static const struct rkvdec_coded_fmt_desc *
+-rkvdec_find_coded_fmt_desc(u32 fourcc)
++rkvdec_default_coded_fmt_desc(unsigned int capabilities)
++{
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
++		if (rkvdec_coded_fmts[i].capability & capabilities)
++			return &rkvdec_coded_fmts[i];
++	}
++
++	return NULL;
++}
++
++static const struct rkvdec_coded_fmt_desc *
++rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities)
+ {
+ 	unsigned int i;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
+-		if (rkvdec_coded_fmts[i].fourcc == fourcc)
++		if (rkvdec_coded_fmts[i].fourcc == fourcc &&
++		    (rkvdec_coded_fmts[i].capability & capabilities))
+ 			return &rkvdec_coded_fmts[i];
+ 	}
+ 
+@@ -304,7 +322,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
+ {
+ 	struct v4l2_format *f = &ctx->coded_fmt;
+ 
+-	ctx->coded_fmt_desc = &rkvdec_coded_fmts[0];
++	ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
+ 	rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc);
+ 
+ 	f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+@@ -331,11 +349,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv,
+ 				  struct v4l2_frmsizeenum *fsize)
+ {
+ 	const struct rkvdec_coded_fmt_desc *fmt;
++	struct rkvdec_dev *rkvdec = video_drvdata(file);
+ 
+ 	if (fsize->index != 0)
+ 		return -EINVAL;
+ 
+-	fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format);
++	fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format,
++					 rkvdec->capabilities);
+ 	if (!fmt)
+ 		return -EINVAL;
+ 
+@@ -406,10 +426,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv,
+ 	struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
+ 	const struct rkvdec_coded_fmt_desc *desc;
+ 
+-	desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat);
++	desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat,
++					  ctx->dev->capabilities);
+ 	if (!desc) {
+-		pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc;
+-		desc = &rkvdec_coded_fmts[0];
++		desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
++		pix_mp->pixelformat = desc->fourcc;
+ 	}
+ 
+ 	v4l2_apply_frmsize_constraints(&pix_mp->width,
+@@ -487,7 +508,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv,
+ 	if (ret)
+ 		return ret;
+ 
+-	desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat);
++	desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat,
++					  ctx->dev->capabilities);
+ 	if (!desc)
+ 		return -EINVAL;
+ 	ctx->coded_fmt_desc = desc;
+@@ -538,7 +560,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv,
+ static int rkvdec_enum_output_fmt(struct file *file, void *priv,
+ 				  struct v4l2_fmtdesc *f)
+ {
+-	if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts))
++	struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
++
++	if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) ||
++	    !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability))
+ 		return -EINVAL;
+ 
+ 	f->pixelformat = rkvdec_coded_fmts[f->index].fourcc;
+@@ -946,14 +971,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx)
+ 	int ret;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++)
+-		nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
++		if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities)
++			nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
+ 
+ 	v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
+-		ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
+-		if (ret)
+-			goto err_free_handler;
++		if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) {
++			ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
++			if (ret)
++				goto err_free_handler;
++		}
+ 	}
+ 
+ 	ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
+@@ -1155,8 +1183,17 @@ static void rkvdec_watchdog_func(struct work_struct *work)
+ 	}
+ }
+ 
++static const struct rkvdec_variant rk3399_rkvdec_variant = {
++        .capabilities   = RKVDEC_CAPABILITY_H264 |
++		           RKVDEC_CAPABILITY_HEVC |
++			   RKVDEC_CAPABILITY_VP9
++};
++
+ static const struct of_device_id of_rkvdec_match[] = {
+-	{ .compatible = "rockchip,rk3399-vdec" },
++	{
++		.compatible = "rockchip,rk3399-vdec",
++		.data = &rk3399_rkvdec_variant,
++	},
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, of_rkvdec_match);
+@@ -1168,6 +1205,7 @@ static const char * const rkvdec_clk_names[] = {
+ static int rkvdec_probe(struct platform_device *pdev)
+ {
+ 	struct rkvdec_dev *rkvdec;
++	const struct rkvdec_variant *variant;
+ 	unsigned int i;
+ 	int ret, irq;
+ 
+@@ -1193,6 +1231,13 @@ static int rkvdec_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
++	variant = of_device_get_match_data(rkvdec->dev);
++	if (!variant)
++		return -EINVAL;
++
++	rkvdec->capabilities = variant->capabilities;
++
++
+ 	rkvdec->regs = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(rkvdec->regs))
+ 		return PTR_ERR(rkvdec->regs);
+diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
+index d6222a2588be..ad8e83884121 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.h
++++ b/drivers/staging/media/rkvdec/rkvdec.h
+@@ -29,6 +29,10 @@
+ 
+ #define RKVDEC_RESET_DELAY	5
+ 
++#define RKVDEC_CAPABILITY_H264	BIT(0)
++#define RKVDEC_CAPABILITY_HEVC	BIT(1)
++#define RKVDEC_CAPABILITY_VP9	BIT(2)
++
+ struct rkvdec_ctx;
+ 
+ struct rkvdec_ctrl_desc {
+@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
+ 			    base.vb.vb2_buf);
+ }
+ 
++struct rkvdec_variant {
++        unsigned int capabilities;
++};
++
+ struct rkvdec_coded_fmt_ops {
+ 	int (*adjust_fmt)(struct rkvdec_ctx *ctx,
+ 			  struct v4l2_format *f);
+@@ -91,6 +99,7 @@ struct rkvdec_coded_fmt_desc {
+ 	unsigned int num_decoded_fmts;
+ 	const u32 *decoded_fmts;
+ 	u32 subsystem_flags;
++	unsigned int capability;
+ };
+ 
+ struct rkvdec_dev {
+@@ -105,6 +114,7 @@ struct rkvdec_dev {
+ 	struct delayed_work watchdog_work;
+ 	struct reset_control *rstc;
+ 	u8 reset_mask;
++	unsigned int capabilities;
+ };
+ 
+ struct rkvdec_ctx {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 30 Jan 2021 18:21:59 +0100
+Subject: [PATCH] media: rkvdec: add RK3288 variant
+
+This adds RK3288 variant to rkvdec driver. In this earlier version
+of the IP only HEVC decoding is supported.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index 955c53afe20f..4e228cd82f21 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -1189,11 +1189,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = {
+ 			   RKVDEC_CAPABILITY_VP9
+ };
+ 
++static const struct rkvdec_variant rk3288_hevc_variant = {
++        .capabilities   = RKVDEC_CAPABILITY_HEVC
++};
++
+ static const struct of_device_id of_rkvdec_match[] = {
+ 	{
+ 		.compatible = "rockchip,rk3399-vdec",
+ 		.data = &rk3399_rkvdec_variant,
+ 	},
++	{
++		.compatible = "rockchip,rk3288-hevc",
++		.data = &rk3288_hevc_variant,
++	},
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, of_rkvdec_match);
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 30 Jan 2021 18:27:30 +0100
+Subject: [PATCH] ARM: dts: RK3288: add hevc node
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm/boot/dts/rockchip/rk3288.dtsi | 21 ++++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index 7b2cde230b87..59fba3ac6aae 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -1248,6 +1248,25 @@ vpu_mmu: iommu@ff9a0800 {
+ 		power-domains = <&power RK3288_PD_VIDEO>;
+ 	};
+ 
++	hevc: hevc@ff9c0000 {
++		compatible = "rockchip,rk3288-hevc";
++		reg = <0x0 0xff9c0000 0x0 0x400>;
++		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "irq_dec";
++		clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>,
++			 <&cru SCLK_HEVC_CORE>;
++		clock-names = "axi", "ahb", "cabac", "core";
++		assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
++				   <&cru SCLK_HEVC_CORE>,
++				   <&cru SCLK_HEVC_CABAC>;
++		assigned-clock-rates = <400000000>, <100000000>,
++				       <300000000>, <300000000>;
++		iommus = <&hevc_mmu>;
++		power-domains = <&power RK3288_PD_HEVC>;
++		resets =  <&cru SRST_HEVC>;
++		reset-names = "video_core";
++	};
++
+ 	hevc_mmu: iommu@ff9c0440 {
+ 		compatible = "rockchip,iommu";
+ 		reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
+@@ -1255,7 +1274,7 @@ hevc_mmu: iommu@ff9c0440 {
+ 		clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
+ 		clock-names = "aclk", "iface";
+ 		#iommu-cells = <0>;
+-		status = "disabled";
++		power-domains = <&power RK3288_PD_HEVC>;
+ 	};
+ 
+ 	gpu: gpu@ffa30000 {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+Date: Tue, 10 May 2022 14:37:29 -0400
+Subject: [PATCH] media: rkvdec: Fix HEVC RPS bit offsets
+
+The offsets from the uAPI need to be extended to include some bits
+that can be calculated from the parameters. This has been compared
+to match with the vendor bit sizes (which simply parse again the
+data to calcualte it).
+
+Fixed by this change:
+- LTRPSPS_A_Qualcomm_1
+- RPS_C_ericsson_5
+- RPS_D_ericsson_6
+- RPS_E_qualcomm_5
+
+Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+---
+ drivers/staging/media/rkvdec/rkvdec-hevc.c | 26 +++++++++++++++++++---
+ 1 file changed, 23 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+index 7a375a23eaf1..580073d49b6a 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+@@ -10,6 +10,7 @@
+  */
+ 
+ #include <media/v4l2-mem2mem.h>
++#include <linux/bitops.h>
+ 
+ #include "rkvdec.h"
+ #include "rkvdec-regs.h"
+@@ -2175,6 +2176,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ 			    struct rkvdec_hevc_run *run)
+ {
+ 	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
++	const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ 	const struct v4l2_ctrl_hevc_slice_params *sl_params;
+ 	const struct v4l2_hevc_dpb_entry *dpb;
+ 	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+@@ -2196,9 +2198,21 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ #define NUM_RPS_POC				PS_FIELD(202, 4)
+ 
+ 	for (j = 0; j < run->num_slices; j++) {
++		uint st_bit_offset = 0;
++
+ 		sl_params = &run->slices_params[j];
+ 		dpb = decode_params->dpb;
+-		lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1;
++
++		if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
++			num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
++
++			if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
++				num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
++
++			lowdelay = 1;
++		} else {
++			lowdelay = 0;
++		}
+ 
+ 		hw_ps = &priv_tbl->rps[j];
+ 		memset(hw_ps, 0, sizeof(*hw_ps));
+@@ -2224,8 +2238,14 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ 
+ 		WRITE_RPS(lowdelay, LOWDELAY);
+ 
+-		WRITE_RPS(sl_params->long_term_ref_pic_set_size +
+-			  sl_params->short_term_ref_pic_set_size,
++		if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
++			if (sl_params->short_term_ref_pic_set_size)
++				st_bit_offset = sl_params->short_term_ref_pic_set_size;
++			else if (sps->num_short_term_ref_pic_sets > 1)
++				st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
++		}
++
++		WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
+ 			  LONG_TERM_RPS_BIT_OFFSET);
+ 		WRITE_RPS(sl_params->short_term_ref_pic_set_size,
+ 			  SHORT_TERM_RPS_BIT_OFFSET);
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+Date: Tue, 10 May 2022 15:12:03 -0400
+Subject: [PATCH] media: rkvdec: Fix number of HEVC references being set in RPS
+
+The numbers from the bitstream are values between 1 - 16 (as they are
+the number - 1). The difference between 0 and 1 needs to be determined
+base on the slice type. I frames have no reference, P frames only have
+L0 reference, and B frames have both.
+
+Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+---
+ drivers/staging/media/rkvdec/rkvdec-hevc.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+index 580073d49b6a..ce15028918b2 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+@@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ 
+ 	for (j = 0; j < run->num_slices; j++) {
+ 		uint st_bit_offset = 0;
++		uint num_l0_refs = 0;
++		uint num_l1_refs = 0;
+ 
+ 		sl_params = &run->slices_params[j];
+ 		dpb = decode_params->dpb;
+@@ -2217,7 +2219,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ 		hw_ps = &priv_tbl->rps[j];
+ 		memset(hw_ps, 0, sizeof(*hw_ps));
+ 
+-		for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) {
++		for (i = 0; i < num_l0_refs; i++) {
+ 			WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
+ 				  REF_PIC_LONG_TERM_L0(i));
+ 			WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
+@@ -2227,7 +2229,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ 
+ 		}
+ 
+-		for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) {
++		for (i = 0; i < num_l1_refs; i++) {
+ 			WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
+ 				  REF_PIC_LONG_TERM_L1(i));
+ 			WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
diff --git a/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch
new file mode 100644
index 000000000000..e69f13a6a6e1
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch
@@ -0,0 +1,1805 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 11 Oct 2020 17:03:12 +0200
+Subject: [PATCH] dt-bindings: media: Add Rockchip IEP binding
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ .../bindings/media/rockchip-iep.yaml          | 73 +++++++++++++++++++
+ 1 file changed, 73 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/media/rockchip-iep.yaml
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
+new file mode 100644
+index 000000000000..a9efcda13fc1
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
+@@ -0,0 +1,73 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/media/rockchip-iep.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip Image Enhancement Processor (IEP)
++
++description:
++    Rockchip IEP supports various image enhancement operations for YUV and RGB domains.
++    Deinterlacing, spatial and temporal sampling noise reduction are supported by the
++    YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in
++    the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for
++    both domains. Furthermore it supports converting RGB to YUV / YUV to RGB.
++
++maintainers:
++  - Heiko Stuebner <heiko@sntech.de>
++
++properties:
++  compatible:
++    oneOf:
++      - const: rockchip,rk3228-iep
++      - items:
++          - enum:
++              - rockchip,rk3288-iep
++              - rockchip,rk3328-iep
++              - rockchip,rk3368-iep
++              - rockchip,rk3399-iep
++          - const: rockchip,rk3228-iep
++
++  reg:
++    maxItems: 1
++
++  interrupts:
++    maxItems: 1
++
++  clocks:
++    maxItems: 2
++
++  clock-names:
++    items:
++      - const: axi
++      - const: ahb
++
++  power-domains:
++    maxItems: 1
++
++  iommus:
++    maxItems: 1
++
++required:
++  - compatible
++  - reg
++  - interrupts
++  - clocks
++  - clock-names
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/rk3228-cru.h>
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/power/rk3228-power.h>
++    iep: iep@20070000 {
++      compatible = "rockchip,rk3228-iep";
++      reg = <0x20070000 0x800>;
++      interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++      clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++      clock-names = "axi", "ahb";
++      iommus = <&iep_mmu>;
++      power-domains = <&power RK3228_PD_VIO>;
++    };
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 11 Oct 2020 21:24:10 +0200
+Subject: [PATCH] media: rockchip: Add Rockchip IEP driver
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/media/platform/rockchip/Kconfig       |    1 +
+ drivers/media/platform/rockchip/Makefile      |    1 +
+ drivers/media/platform/rockchip/iep/Kconfig   |   16 +
+ drivers/media/platform/rockchip/iep/Makefile  |    5 +
+ .../media/platform/rockchip/iep/iep-regs.h    |  291 +++++
+ drivers/media/platform/rockchip/iep/iep.c     | 1089 +++++++++++++++++
+ drivers/media/platform/rockchip/iep/iep.h     |  112 ++
+ 7 files changed, 1515 insertions(+)
+ create mode 100644 drivers/media/platform/rockchip/iep/Kconfig
+ create mode 100644 drivers/media/platform/rockchip/iep/Makefile
+ create mode 100644 drivers/media/platform/rockchip/iep/iep-regs.h
+ create mode 100644 drivers/media/platform/rockchip/iep/iep.c
+ create mode 100644 drivers/media/platform/rockchip/iep/iep.h
+
+diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig
+index b41d3960c1b4..9ff362805ded 100644
+--- a/drivers/media/platform/rockchip/Kconfig
++++ b/drivers/media/platform/rockchip/Kconfig
+@@ -2,5 +2,6 @@
+ 
+ comment "Rockchip media platform drivers"
+ 
++source "drivers/media/platform/rockchip/iep/Kconfig"
+ source "drivers/media/platform/rockchip/rga/Kconfig"
+ source "drivers/media/platform/rockchip/rkisp1/Kconfig"
+diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile
+index 4f782b876ac9..c075ecc2fa14 100644
+--- a/drivers/media/platform/rockchip/Makefile
++++ b/drivers/media/platform/rockchip/Makefile
+@@ -1,3 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0-only
++obj-y += iep/
+ obj-y += rga/
+ obj-y += rkisp1/
+diff --git a/drivers/media/platform/rockchip/iep/Kconfig b/drivers/media/platform/rockchip/iep/Kconfig
+new file mode 100644
+index 000000000000..d95155a95133
+--- /dev/null
++++ b/drivers/media/platform/rockchip/iep/Kconfig
+@@ -0,0 +1,16 @@
++# SPDX-License-Identifier: GPL-2.0-only
++ 
++config VIDEO_ROCKCHIP_IEP
++	tristate "Rockchip Image Enhancement Processor"
++	depends on V4L_MEM2MEM_DRIVERS
++	depends on VIDEO_DEV
++	depends on ARCH_ROCKCHIP || COMPILE_TEST
++	select VIDEOBUF2_DMA_CONTIG
++	select V4L2_MEM2MEM_DEV
++	help
++	  This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP)
++	  found in most Rockchip RK3xxx SoCs.
++	  Rockchip IEP supports various enhancement operations for RGB and YUV
++	  images. The driver currently implements YUV deinterlacing only.
++	  To compile this driver as a module, choose M here: the module
++	  will be called rockchip-iep
+diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile
+new file mode 100644
+index 000000000000..5c89b3277469
+--- /dev/null
++++ b/drivers/media/platform/rockchip/iep/Makefile
+@@ -0,0 +1,5 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++rockchip-iep-objs := iep.o
++
++obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o
+diff --git a/drivers/media/platform/rockchip/iep/iep-regs.h b/drivers/media/platform/rockchip/iep/iep-regs.h
+new file mode 100644
+index 000000000000..a68685ef3604
+--- /dev/null
++++ b/drivers/media/platform/rockchip/iep/iep-regs.h
+@@ -0,0 +1,291 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Rockchip Image Enhancement Processor (IEP) driver
++ *
++ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
++ *
++ */
++
++#ifndef __IEP_REGS_H__
++#define __IEP_REGS_H__
++
++/* IEP Registers addresses */
++#define IEP_CONFIG0			0x000 /* Configuration register0 */
++#define IEP_VOP_DIRECT_PATH			BIT(0)
++#define IEP_DEIN_HIGH_FREQ_SHFT			1
++#define IEP_DEIN_HIGH_FREQ_MASK			(0x7f << IEP_DEIN_HIGH_FREQ_SHFT)
++#define IEP_DEIN_MODE_SHFT			8
++#define IEP_DEIN_MODE_MASK			(7 << IEP_DEIN_MODE_SHFT)
++#define IEP_DEIN_HIGH_FREQ_EN			BIT(11)
++#define IEP_DEIN_EDGE_INTPOL_EN			BIT(12)
++#define IEP_YUV_DENOISE_EN			BIT(13)
++#define IEP_YUV_ENHNC_EN			BIT(14)
++#define IEP_DEIN_EDGE_INTPOL_SMTH_EN		BIT(15)
++#define IEP_RGB_CLR_ENHNC_EN			BIT(16)
++#define IEP_RGB_CNTRST_ENHNC_EN			BIT(17)
++#define IEP_RGB_ENHNC_MODE_BYPASS		(0 << 18)
++#define IEP_RGB_ENHNC_MODE_DNS			BIT(18)
++#define IEP_RGB_ENHNC_MODE_DTL			(2 << 18)
++#define IEP_RGB_ENHNC_MODE_EDG			(3 << 18)
++#define IEP_RGB_ENHNC_MODE_MASK			(3 << 18)
++#define IEP_RGB_CNTRST_ENHNC_DDE_FRST		BIT(20)
++#define IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT	21
++#define IEP_DEIN_EDGE_INTPOL_RADIUS_MASK	(3 << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT)
++#define IEP_DEIN_EDGE_INTPOL_SELECT		BIT(23)
++
++#define IEP_CONFIG1			0x004 /* Configuration register1 */
++#define IEP_SRC_FMT_SHFT			0
++#define IEP_SRC_FMT_MASK			(3 << IEP_SRC_FMT_SHFT)
++#define IEP_SRC_RGB_SWP_SHFT			2
++#define IEP_SRC_RGB_SWP_MASK			(2 << IEP_SRC_RGB_SWP_SHFT)
++#define IEP_SRC_YUV_SWP_SHFT			4
++#define IEP_SRC_YUV_SWP_MASK			(3 << IEP_SRC_YUV_SWP_SHFT)
++#define IEP_DST_FMT_SHFT			8
++#define IEP_DST_FMT_MASK			(3 << IEP_DST_FMT_SHFT)
++#define IEP_DST_RGB_SWP_SHFT			10
++#define IEP_DST_RGB_SWP_MASK			(2 << IEP_DST_RGB_SWP_SHFT)
++#define IEP_DST_YUV_SWP_SHFT			12
++#define IEP_DST_YUV_SWP_MASK			(3 << IEP_DST_YUV_SWP_SHFT)
++#define IEP_DTH_UP_EN				BIT(14)
++#define IEP_DTH_DWN_EN				BIT(15)
++#define IEP_YUV2RGB_COE_BT601_1			(0 << 16)
++#define IEP_YUV2RGB_COE_BT601_F			BIT(16)
++#define IEP_YUV2RGB_COE_BT709_1			(2 << 16)
++#define IEP_YUV2RGB_COE_BT709_F			(3 << 16)
++#define IEP_YUV2RGB_COE_MASK			(3 << 16)
++#define IEP_RGB2YUV_COE_BT601_1			(0 << 18)
++#define IEP_RGB2YUV_COE_BT601_F			BIT(18)
++#define IEP_RGB2YUV_COE_BT709_1			(2 << 18)
++#define IEP_RGB2YUV_COE_BT709_F			(3 << 18)
++#define IEP_RGB2YUV_COE_MASK			(3 << 18)
++#define IEP_YUV2RGB_EN				BIT(20)
++#define IEP_RGB2YUV_EN				BIT(21)
++#define IEP_YUV2RGB_CLIP_EN			BIT(22)
++#define IEP_RGB2YUV_CLIP_EN			BIT(23)
++#define IEP_GLB_ALPHA_SHFT			24
++#define IEP_GLB_ALPHA_MASK			(0x7f << IEP_GLB_ALPHA_SHFT)
++
++#define IEP_STATUS			0x008 /* Status register */
++#define IEP_STATUS_YUV_DNS			BIT(0)
++#define IEP_STATUS_SCL				BIT(1)
++#define IEP_STATUS_DIL				BIT(2)
++#define IEP_STATUS_DDE				BIT(3)
++#define IEP_STATUS_DMA_WR_YUV			BIT(4)
++#define IEP_STATUS_DMA_RE_YUV			BIT(5)
++#define IEP_STATUS_DMA_WR_RGB			BIT(6)
++#define IEP_STATUS_DMA_RE_RGB			BIT(7)
++#define IEP_STATUS_VOP_DIRECT_PATH		BIT(8)
++#define IEP_STATUS_DMA_IA_WR_YUV		BIT(16)
++#define IEP_STATUS_DMA_IA_RE_YUV		BIT(17)
++#define IEP_STATUS_DMA_IA_WR_RGB		BIT(18)
++#define IEP_STATUS_DMA_IA_RE_RGB		BIT(19)
++
++#define IEP_INT				0x00c /* Interrupt register*/
++#define IEP_INT_FRAME_DONE			BIT(0) /* Frame process done interrupt */
++#define IEP_INT_FRAME_DONE_EN			BIT(8) /* Frame process done interrupt enable */
++#define IEP_INT_FRAME_DONE_CLR			BIT(16) /* Frame process done interrupt clear */
++
++#define IEP_FRM_START			0x010 /* Frame start */
++#define IEP_SRST			0x014 /* Soft reset */
++#define IEP_CONFIG_DONE			0x018 /* Configuration done */
++#define IEP_FRM_CNT			0x01c /* Frame counter */
++
++#define IEP_VIR_IMG_WIDTH		0x020 /* Image virtual width */
++#define IEP_IMG_SCL_FCT			0x024 /* Scaling factor */
++#define IEP_SRC_IMG_SIZE		0x028 /* src image width/height */
++#define IEP_DST_IMG_SIZE		0x02c /* dst image width/height */
++#define IEP_DST_IMG_WIDTH_TILE0		0x030 /* dst image tile0 width */
++#define IEP_DST_IMG_WIDTH_TILE1		0x034 /* dst image tile1 width */
++#define IEP_DST_IMG_WIDTH_TILE2		0x038 /* dst image tile2 width */
++#define IEP_DST_IMG_WIDTH_TILE3		0x03c /* dst image tile3 width */
++
++#define IEP_ENH_YUV_CNFG_0		0x040 /* Brightness, contrast, saturation adjustment */
++#define IEP_YUV_BRIGHTNESS_SHFT			0
++#define IEP_YUV_BRIGHTNESS_MASK			(0x3f << IEP_YUV_BRIGHTNESS_SHFT)
++#define IEP_YUV_CONTRAST_SHFT			8
++#define IEP_YUV_CONTRAST_MASK			(0xff << IEP_YUV_CONTRAST_SHFT)
++#define IEP_YUV_SATURATION_SHFT			16
++#define IEP_YUV_SATURATION_MASK			(0x1ff << IEP_YUV_SATURATION_SHFT)
++
++#define IEP_ENH_YUV_CNFG_1		0x044 /* Hue configuration */
++#define IEP_YUV_COS_HUE_SHFT			0
++#define IEP_YUV_COS_HUE_MASK			(0xff << IEP_YUV_COS_HUE_SHFT)
++#define IEP_YUV_SIN_HUE_SHFT			8
++#define IEP_YUV_SIN_HUE_MASK			(0xff << IEP_YUV_SIN_HUE_SHFT)
++
++#define IEP_ENH_YUV_CNFG_2		0x048 /* Color bar configuration */
++#define IEP_YUV_COLOR_BAR_Y_SHFT		0
++#define IEP_YUV_COLOR_BAR_Y_MASK		(0xff << IEP_YUV_COLOR_BAR_Y_SHFT)
++#define IEP_YUV_COLOR_BAR_U_SHFT		8
++#define IEP_YUV_COLOR_BAR_U_MASK		(0xff << IEP_YUV_COLOR_BAR_U_SHFT)
++#define IEP_YUV_COLOR_BAR_V_SHFT		16
++#define IEP_YUV_COLOR_BAR_V_MASK		(0xff << IEP_YUV_COLOR_BAR_V_SHFT)
++#define IEP_YUV_VIDEO_MODE_SHFT			24
++#define IEP_YUV_VIDEO_MODE_MASK			(3 << IEP_YUV_VIDEO_MODE_SHFT)
++
++#define IEP_ENH_RGB_CNFG		0x04c /* RGB enhancement configuration */
++#define IEP_ENH_RGB_C_COE		0x050 /* RGB color enhancement coefficient */
++
++#define IEP_RAW_CONFIG0			0x058 /* Raw configuration register0 */
++#define IEP_RAW_CONFIG1			0x05c /* Raw configuration register1 */
++#define IEP_RAW_VIR_IMG_WIDTH		0x060 /* Raw image virtual width */
++#define IEP_RAW_IMG_SCL_FCT		0x064 /* Raw scaling factor */
++#define IEP_RAW_SRC_IMG_SIZE		0x068 /* Raw src image width/height  */
++#define IEP_RAW_DST_IMG_SIZE		0x06c /* Raw src image width/height  */
++#define IEP_RAW_ENH_YUV_CNFG_0		0x070 /* Raw brightness,contrast,saturation adjustment */
++#define IEP_RAW_ENH_YUV_CNFG_1		0x074 /* Raw hue configuration */
++#define IEP_RAW_ENH_YUV_CNFG_2		0x078 /* Raw color bar configuration */
++#define IEP_RAW_ENH_RGB_CNFG		0x07c /* Raw RGB enhancement configuration */
++
++#define IEP_SRC_ADDR_Y_RGB		0x080 /* Start addr. of src image 0 (Y/RGB) */
++#define IEP_SRC_ADDR_CBCR		0x084 /* Start addr. of src image 0 (Cb/Cr) */
++#define IEP_SRC_ADDR_CR			0x088 /* Start addr. of src image 0 (Cr) */
++#define IEP_SRC_ADDR_Y1			0x08c /* Start addr. of src image 1 (Y) */
++#define IEP_SRC_ADDR_CBCR1		0x090 /* Start addr. of src image 1 (Cb/Cr) */
++#define IEP_SRC_ADDR_CR1		0x094 /* Start addr. of src image 1 (Cr) */
++#define IEP_SRC_ADDR_Y_ITEMP		0x098 /* Start addr. of src image(Y int part) */
++#define IEP_SRC_ADDR_CBCR_ITEMP		0x09c /* Start addr. of src image(CBCR int part) */
++#define IEP_SRC_ADDR_CR_ITEMP		0x0a0 /* Start addr. of src image(CR int part) */
++#define IEP_SRC_ADDR_Y_FTEMP		0x0a4 /* Start addr. of src image(Y frac part) */
++#define IEP_SRC_ADDR_CBCR_FTEMP		0x0a8 /* Start addr. of src image(CBCR frac part) */
++#define IEP_SRC_ADDR_CR_FTEMP		0x0ac /* Start addr. of src image(CR frac part) */
++
++#define IEP_DST_ADDR_Y_RGB		0x0b0 /* Start addr. of dst image 0 (Y/RGB) */
++#define IEP_DST_ADDR_CBCR		0x0b4 /* Start addr. of dst image 0 (Cb/Cr) */
++#define IEP_DST_ADDR_CR			0x0b8 /* Start addr. of dst image 0 (Cr) */
++#define IEP_DST_ADDR_Y1			0x0bc /* Start addr. of dst image 1 (Y) */
++#define IEP_DST_ADDR_CBCR1		0x0c0 /* Start addr. of dst image 1 (Cb/Cr) */
++#define IEP_DST_ADDR_CR1		0x0c4 /* Start addr. of dst image 1 (Cr) */
++#define IEP_DST_ADDR_Y_ITEMP		0x0c8 /* Start addr. of dst image(Y int part) */
++#define IEP_DST_ADDR_CBCR_ITEMP		0x0cc /* Start addr. of dst image(CBCR int part)*/
++#define IEP_DST_ADDR_CR_ITEMP		0x0d0 /* Start addr. of dst image(CR int part) */
++#define IEP_DST_ADDR_Y_FTEMP		0x0d4 /* Start addr. of dst image(Y frac part) */
++#define IEP_DST_ADDR_CBCR_FTEMP		0x0d8 /* Start addr. of dst image(CBCR frac part) */
++#define IEP_DST_ADDR_CR_FTEMP		0x0dc /* Start addr. of dst image(CR frac part)*/
++
++#define IEP_DEIN_MTN_TAB0		0x0e0 /* Deinterlace motion table0 */
++#define IEP_DEIN_MTN_TAB1		0x0e4 /* Deinterlace motion table1 */
++#define IEP_DEIN_MTN_TAB2		0x0e8 /* Deinterlace motion table2 */
++#define IEP_DEIN_MTN_TAB3		0x0ec /* Deinterlace motion table3 */
++#define IEP_DEIN_MTN_TAB4		0x0f0 /* Deinterlace motion table4 */
++#define IEP_DEIN_MTN_TAB5		0x0f4 /* Deinterlace motion table5 */
++#define IEP_DEIN_MTN_TAB6		0x0f8 /* Deinterlace motion table6 */
++#define IEP_DEIN_MTN_TAB7		0x0fc /* Deinterlace motion table7 */
++
++#define IEP_ENH_CG_TAB			0x100 /* Contrast and gamma enhancement table */
++#define IEP_ENH_DDE_COE0		0x400 /* Denoise,detail and edge enhancement coefficient */
++#define IEP_ENH_DDE_COE1		0x500 /* Denoise,detail and edge enhancement coefficient1 */
++
++#define IEP_INT_MASK			(IEP_INT_FRAME_DONE)
++
++/* IEP colorformats */
++#define IEP_COLOR_FMT_XRGB		0U
++#define IEP_COLOR_FMT_RGB565		1U
++#define IEP_COLOR_FMT_YUV422		2U
++#define IEP_COLOR_FMT_YUV420		3U
++
++/* IEP YUV color swaps */
++#define IEP_YUV_SWP_SP_UV		0U
++#define IEP_YUV_SWP_SP_VU		1U
++#define IEP_YUV_SWP_P			2U
++
++/* IEP XRGB color swaps */
++#define XRGB_SWP_XRGB			0U
++#define XRGB_SWP_XBGR			1U
++#define XRGB_SWP_BGRX			2U
++
++/* IEP RGB565 color swaps */
++#define RGB565_SWP_RGB			0U
++#define RGB565_SWP_BGR			1U
++
++#define FMT_IS_YUV(fmt) (fmt == IEP_COLOR_FMT_XRGB || fmt == IEP_COLOR_FMT_RGB565 ? 0 : 1)
++
++#define IEP_IMG_SIZE(w, h) (((w - 1) & 0x1fff) << 0 | \
++			    ((h - 1) & 0x1fff) << 16)
++
++#define IEP_VIR_WIDTH(src_w, dst_w) (((src_w / 4) & 0x1fff) << 0 | \
++				     ((dst_w / 4) & 0x1fff) << 16)
++
++#define IEP_Y_STRIDE(w, h) (w * h)
++#define IEP_UV_STRIDE(w, h, fac) (w * h + w * h / fac)
++
++#define IEP_SRC_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_MASK : IEP_SRC_RGB_SWP_MASK)
++#define IEP_DST_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_MASK : IEP_DST_RGB_SWP_MASK)
++
++#define IEP_SRC_FMT(f, swp) (f << IEP_SRC_FMT_SHFT | \
++			     (swp << (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_SHFT : IEP_SRC_RGB_SWP_SHFT)))
++#define IEP_DST_FMT(f, swp) (f << IEP_DST_FMT_SHFT | \
++			     (swp << (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_SHFT : IEP_DST_RGB_SWP_SHFT)))
++
++/* IEP DEINTERLACE MODES */
++#define IEP_DEIN_MODE_YUV		0U
++#define IEP_DEIN_MODE_I4O2		1U
++#define IEP_DEIN_MODE_I4O1B		2U
++#define IEP_DEIN_MODE_I4O1T		3U
++#define IEP_DEIN_MODE_I2O1B		4U
++#define IEP_DEIN_MODE_I2O1T		5U
++#define IEP_DEIN_MODE_BYPASS		6U
++
++#define IEP_DEIN_IN_FIELDS_2		2U
++#define IEP_DEIN_IN_FIELDS_4		4U
++
++#define IEP_DEIN_OUT_FRAMES_1		1U
++#define IEP_DEIN_OUT_FRAMES_2		2U
++
++/* values taken from BSP driver */
++static const u32 default_dein_motion_tbl[][2] = {
++	{ IEP_DEIN_MTN_TAB0, 0x40404040 },
++	{ IEP_DEIN_MTN_TAB1, 0x3c3e3f3f },
++	{ IEP_DEIN_MTN_TAB2, 0x3336393b },
++	{ IEP_DEIN_MTN_TAB3, 0x272a2d31 },
++	{ IEP_DEIN_MTN_TAB4, 0x181c2023 },
++	{ IEP_DEIN_MTN_TAB5, 0x0c0e1215 },
++	{ IEP_DEIN_MTN_TAB6, 0x03040609 },
++	{ IEP_DEIN_MTN_TAB7, 0x00000001 },
++
++};
++
++#define IEP_DEIN_IN_IMG0_Y(bff) (bff ? IEP_SRC_ADDR_Y_RGB : IEP_SRC_ADDR_Y1)
++#define IEP_DEIN_IN_IMG0_CBCR(bff) (bff ? IEP_SRC_ADDR_CBCR : IEP_SRC_ADDR_CBCR1)
++#define IEP_DEIN_IN_IMG0_CR(bff) (bff ? IEP_SRC_ADDR_CR : IEP_SRC_ADDR_CR1)
++#define IEP_DEIN_IN_IMG1_Y(bff) (IEP_DEIN_IN_IMG0_Y(!bff))
++#define IEP_DEIN_IN_IMG1_CBCR(bff) (IEP_DEIN_IN_IMG0_CBCR(!bff))
++#define IEP_DEIN_IN_IMG1_CR(bff) (IEP_DEIN_IN_IMG0_CR(!bff))
++
++#define IEP_DEIN_OUT_IMG0_Y(bff) (bff ? IEP_DST_ADDR_Y1 : IEP_DST_ADDR_Y_RGB)
++#define IEP_DEIN_OUT_IMG0_CBCR(bff) (bff ? IEP_DST_ADDR_CBCR1 : IEP_DST_ADDR_CBCR)
++#define IEP_DEIN_OUT_IMG0_CR(bff) (bff ? IEP_DST_ADDR_CR1 : IEP_DST_ADDR_CR)
++#define IEP_DEIN_OUT_IMG1_Y(bff) (IEP_DEIN_OUT_IMG0_Y(!bff))
++#define IEP_DEIN_OUT_IMG1_CBCR(bff) (IEP_DEIN_OUT_IMG0_CBCR(!bff))
++#define IEP_DEIN_OUT_IMG1_CR(bff) (IEP_DEIN_OUT_IMG0_CR(!bff))
++
++#define IEP_DEIN_MODE(m) (m << IEP_DEIN_MODE_SHFT)
++
++#define IEP_DEIN_IN_MODE_FIELDS(m) ((m == IEP_DEIN_MODE_I4O1T || m == IEP_DEIN_MODE_I4O1B \
++				     || m == IEP_DEIN_MODE_I4O2) \
++				    ? IEP_DEIN_IN_FIELDS_4 : IEP_DEIN_IN_FIELDS_2)
++
++#define IEP_DEIN_OUT_MODE_FRAMES(m) (m == IEP_DEIN_MODE_I4O2 \
++				     ? IEP_DEIN_OUT_FRAMES_2 : IEP_DEIN_OUT_FRAMES_1)
++
++#define IEP_DEIN_OUT_MODE_1FRM_TOP_FIELD(m) (m == IEP_DEIN_MODE_I4O1T || IEP_DEIN_MODE_I2O1T \
++					      ? 1 : 0)
++
++#define IEP_DEIN_EDGE_INTPOL_RADIUS(r) (r << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT)
++
++#define IEP_DEIN_HIGH_FREQ(f) (f << IEP_DEIN_HIGH_FREQ_SHFT)
++
++/* YUV Enhance video modes */
++#define VIDEO_MODE_BLACK_SCREEN		0U
++#define VIDEO_MODE_BLUE_SCREEN		1U
++#define VIDEO_MODE_COLOR_BARS		2U
++#define VIDEO_MODE_NORMAL_VIDEO		3U
++
++#define YUV_VIDEO_MODE(m) ((m << IEP_YUV_VIDEO_MODE_SHFT) & IEP_YUV_VIDEO_MODE_MASK)
++#define YUV_BRIGHTNESS(v) ((v << IEP_YUV_BRIGHTNESS_SHFT) & IEP_YUV_BRIGHTNESS_MASK)
++#define YUV_CONTRAST(v) ((v << IEP_YUV_CONTRAST_SHFT) & IEP_YUV_CONTRAST_MASK)
++#define YUV_SATURATION(v) ((v << IEP_YUV_SATURATION_SHFT) & IEP_YUV_SATURATION_MASK)
++#define YUV_COS_HUE(v) ((v << IEP_YUV_COS_HUE_SHFT) & IEP_YUV_COS_HUE_MASK)
++#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK)
++
++#endif
+diff --git a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/rockchip/iep/iep.c
+new file mode 100644
+index 000000000000..f4b9320733be
+--- /dev/null
++++ b/drivers/media/platform/rockchip/iep/iep.c
+@@ -0,0 +1,1089 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Rockchip Image Enhancement Processor (IEP) driver
++ *
++ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
++ *
++ * Based on Allwinner sun8i deinterlacer with scaler driver
++ *  Copyright (C) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ *
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-mem2mem.h>
++#include <media/videobuf2-v4l2.h>
++#include <media/videobuf2-core.h>
++#include <media/videobuf2-dma-contig.h>
++#include <linux/videodev2.h>
++
++#include "iep-regs.h"
++#include "iep.h"
++
++static struct iep_fmt formats[] = {
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.color_swap = IEP_YUV_SWP_SP_UV,
++		.hw_format = IEP_COLOR_FMT_YUV420,
++		.depth = 12,
++		.uv_factor = 4,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.color_swap = IEP_YUV_SWP_SP_VU,
++		.hw_format = IEP_COLOR_FMT_YUV420,
++		.depth = 12,
++		.uv_factor = 4,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV16,
++		.color_swap = IEP_YUV_SWP_SP_UV,
++		.hw_format = IEP_COLOR_FMT_YUV422,
++		.depth = 16,
++		.uv_factor = 2,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV61,
++		.color_swap = IEP_YUV_SWP_SP_VU,
++		.hw_format = IEP_COLOR_FMT_YUV422,
++		.depth = 16,
++		.uv_factor = 2,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_YUV420,
++		.color_swap = IEP_YUV_SWP_P,
++		.hw_format = IEP_COLOR_FMT_YUV420,
++		.depth = 12,
++		.uv_factor = 4,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_YUV422P,
++		.color_swap = IEP_YUV_SWP_P,
++		.hw_format = IEP_COLOR_FMT_YUV422,
++		.depth = 16,
++		.uv_factor = 2,
++	},
++};
++
++static struct iep_fmt *iep_fmt_find(struct v4l2_pix_format *pix_fmt)
++{
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(formats); i++) {
++		if (formats[i].fourcc == pix_fmt->pixelformat)
++			return &formats[i];
++	}
++
++	return NULL;
++}
++
++static bool iep_check_pix_format(u32 pixelformat)
++{
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(formats); i++)
++		if (formats[i].fourcc == pixelformat)
++			return true;
++
++	return false;
++}
++
++static struct vb2_v4l2_buffer *iep_m2m_next_dst_buf(struct iep_ctx *ctx)
++{
++	struct vb2_v4l2_buffer *dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
++
++	/* application has set a dst sequence: take it as start point */
++	if (ctx->dst_sequence == 0 && dst_buf->sequence > 0)
++		ctx->dst_sequence = dst_buf->sequence;
++
++	dst_buf->sequence = ctx->dst_sequence++;
++
++	return dst_buf;
++}
++
++static void iep_m2m_dst_bufs_done(struct iep_ctx *ctx, enum vb2_buffer_state state)
++{
++	if (ctx->dst0_buf) {
++		v4l2_m2m_buf_done(ctx->dst0_buf, state);
++		ctx->dst_buffs_done++;
++		ctx->dst0_buf = NULL;
++	}
++
++	if (ctx->dst1_buf) {
++		v4l2_m2m_buf_done(ctx->dst1_buf, state);
++		ctx->dst_buffs_done++;
++		ctx->dst1_buf = NULL;
++	}
++}
++
++static void iep_setup_formats(struct iep_ctx *ctx)
++{
++	/* setup src dimensions */
++	iep_write(ctx->iep, IEP_SRC_IMG_SIZE,
++		  IEP_IMG_SIZE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height));
++
++	/* setup dst dimensions */
++	iep_write(ctx->iep, IEP_DST_IMG_SIZE,
++		  IEP_IMG_SIZE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height));
++
++	/* setup virtual width */
++	iep_write(ctx->iep, IEP_VIR_IMG_WIDTH,
++		  IEP_VIR_WIDTH(ctx->src_fmt.pix.width, ctx->dst_fmt.pix.width));
++
++	/* setup src format */
++	iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1,
++		       IEP_SRC_FMT_MASK | IEP_SRC_FMT_SWP_MASK(ctx->src_fmt.hw_fmt->hw_format),
++		       IEP_SRC_FMT(ctx->src_fmt.hw_fmt->hw_format,
++				   ctx->src_fmt.hw_fmt->color_swap));
++	/* setup dst format */
++	iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1,
++		       IEP_DST_FMT_MASK | IEP_DST_FMT_SWP_MASK(ctx->dst_fmt.hw_fmt->hw_format),
++		       IEP_DST_FMT(ctx->dst_fmt.hw_fmt->hw_format,
++				   ctx->dst_fmt.hw_fmt->color_swap));
++
++	ctx->fmt_changed = false;
++}
++
++static void iep_dein_init(struct rockchip_iep *iep)
++{
++	unsigned int i;
++
++	/* values taken from BSP driver */
++	iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0,
++		       (IEP_DEIN_EDGE_INTPOL_SMTH_EN |
++		       IEP_DEIN_EDGE_INTPOL_RADIUS_MASK |
++		       IEP_DEIN_HIGH_FREQ_EN |
++		       IEP_DEIN_HIGH_FREQ_MASK),
++		       (IEP_DEIN_EDGE_INTPOL_SMTH_EN |
++		       IEP_DEIN_EDGE_INTPOL_RADIUS(3) |
++		       IEP_DEIN_HIGH_FREQ_EN |
++		       IEP_DEIN_HIGH_FREQ(64)));
++
++	for (i = 0; i < ARRAY_SIZE(default_dein_motion_tbl); i++)
++		iep_write(iep, default_dein_motion_tbl[i][0],
++			  default_dein_motion_tbl[i][1]);
++}
++
++static void iep_init(struct rockchip_iep *iep)
++{
++	iep_write(iep, IEP_CONFIG0,
++		  IEP_DEIN_MODE(IEP_DEIN_MODE_BYPASS) // |
++		  //IEP_YUV_ENHNC_EN
++	);
++
++	/* TODO: B/S/C/H works
++	 *  only in 1-frame-out modes
++	iep_write(iep, IEP_ENH_YUV_CNFG_0,
++		  YUV_BRIGHTNESS(0) |
++		  YUV_CONTRAST(128) |
++		  YUV_SATURATION(128));
++
++	iep_write(iep, IEP_ENH_YUV_CNFG_1,
++		  YUV_COS_HUE(255) |
++		  YUV_SIN_HUE(255));
++
++	iep_write(iep, IEP_ENH_YUV_CNFG_2,
++		  YUV_VIDEO_MODE(VIDEO_MODE_NORMAL_VIDEO));
++
++	*/
++
++	/* reset frame counter */
++	iep_write(iep, IEP_FRM_CNT, 0);
++}
++
++static void iep_device_run(void *priv)
++{
++	struct iep_ctx *ctx = priv;
++	struct rockchip_iep *iep = ctx->iep;
++	struct vb2_v4l2_buffer *src, *dst;
++	unsigned int dein_mode;
++	dma_addr_t addr;
++
++	if (ctx->fmt_changed)
++		iep_setup_formats(ctx);
++
++	if (ctx->prev_src_buf)
++		dein_mode = IEP_DEIN_MODE_I4O2;
++	else
++		dein_mode = ctx->field_bff ? IEP_DEIN_MODE_I2O1B : IEP_DEIN_MODE_I2O1T;
++
++	iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0,
++		       IEP_DEIN_MODE_MASK, IEP_DEIN_MODE(dein_mode));
++
++	/* sync RAW_xxx registers with actual used */
++	iep_write(iep, IEP_CONFIG_DONE, 1);
++
++	/* setup src buff(s)/addresses */
++	src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
++	addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0);
++
++	iep_write(iep, IEP_DEIN_IN_IMG0_Y(ctx->field_bff), addr);
++
++	iep_write(iep, IEP_DEIN_IN_IMG0_CBCR(ctx->field_bff),
++		  addr + ctx->src_fmt.y_stride);
++
++	iep_write(iep, IEP_DEIN_IN_IMG0_CR(ctx->field_bff),
++		  addr + ctx->src_fmt.uv_stride);
++
++	if (IEP_DEIN_IN_MODE_FIELDS(dein_mode) == IEP_DEIN_IN_FIELDS_4)
++		addr = vb2_dma_contig_plane_dma_addr(&ctx->prev_src_buf->vb2_buf, 0);
++
++	iep_write(iep, IEP_DEIN_IN_IMG1_Y(ctx->field_bff), addr);
++
++	iep_write(iep, IEP_DEIN_IN_IMG1_CBCR(ctx->field_bff),
++		  addr + ctx->src_fmt.y_stride);
++
++	iep_write(iep, IEP_DEIN_IN_IMG1_CR(ctx->field_bff),
++		  addr + ctx->src_fmt.uv_stride);
++
++	/* setup dst buff(s)/addresses */
++	dst = iep_m2m_next_dst_buf(ctx);
++	addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0);
++
++	if (IEP_DEIN_OUT_MODE_FRAMES(dein_mode) == IEP_DEIN_OUT_FRAMES_2) {
++		v4l2_m2m_buf_copy_metadata(ctx->prev_src_buf, dst, true);
++
++		iep_write(iep, IEP_DEIN_OUT_IMG0_Y(ctx->field_bff), addr);
++
++		iep_write(iep, IEP_DEIN_OUT_IMG0_CBCR(ctx->field_bff),
++			  addr + ctx->dst_fmt.y_stride);
++
++		iep_write(iep, IEP_DEIN_OUT_IMG0_CR(ctx->field_bff),
++			  addr + ctx->dst_fmt.uv_stride);
++
++		ctx->dst0_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
++
++		dst = iep_m2m_next_dst_buf(ctx);
++		addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0);
++	}
++
++	v4l2_m2m_buf_copy_metadata(src, dst, true);
++
++	iep_write(iep, IEP_DEIN_OUT_IMG1_Y(ctx->field_bff), addr);
++
++	iep_write(iep, IEP_DEIN_OUT_IMG1_CBCR(ctx->field_bff),
++		  addr + ctx->dst_fmt.y_stride);
++
++	iep_write(iep, IEP_DEIN_OUT_IMG1_CR(ctx->field_bff),
++		  addr + ctx->dst_fmt.uv_stride);
++
++	ctx->dst1_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
++
++	iep_mod(ctx->iep, IEP_INT, IEP_INT_FRAME_DONE_EN,
++		IEP_INT_FRAME_DONE_EN);
++
++	/* start HW */
++	iep_write(iep, IEP_FRM_START, 1);
++}
++
++static int iep_job_ready(void *priv)
++{
++	struct iep_ctx *ctx = priv;
++
++	return v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2 &&
++	       v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1;
++}
++
++static void iep_job_abort(void *priv)
++{
++	struct iep_ctx *ctx = priv;
++
++	/* Will cancel the transaction in the next interrupt handler */
++	ctx->job_abort = true;
++}
++
++static const struct v4l2_m2m_ops iep_m2m_ops = {
++	.device_run	= iep_device_run,
++	.job_ready	= iep_job_ready,
++	.job_abort	= iep_job_abort,
++};
++
++static int iep_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
++			   unsigned int *nplanes, unsigned int sizes[],
++				   struct device *alloc_devs[])
++{
++	struct iep_ctx *ctx = vb2_get_drv_priv(vq);
++	struct v4l2_pix_format *pix_fmt;
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type))
++		pix_fmt = &ctx->src_fmt.pix;
++	else
++		pix_fmt = &ctx->dst_fmt.pix;
++
++	if (*nplanes) {
++		if (sizes[0] < pix_fmt->sizeimage)
++			return -EINVAL;
++	} else {
++		sizes[0] = pix_fmt->sizeimage;
++		*nplanes = 1;
++	}
++
++	return 0;
++}
++
++static int iep_buf_prepare(struct vb2_buffer *vb)
++{
++	struct vb2_queue *vq = vb->vb2_queue;
++	struct iep_ctx *ctx = vb2_get_drv_priv(vq);
++	struct v4l2_pix_format *pix_fmt;
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type))
++		pix_fmt = &ctx->src_fmt.pix;
++	else
++		pix_fmt = &ctx->dst_fmt.pix;
++
++	if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage)
++		return -EINVAL;
++
++	/* set bytesused for capture buffers */
++	if (!V4L2_TYPE_IS_OUTPUT(vq->type))
++		vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage);
++
++	return 0;
++}
++
++static void iep_buf_queue(struct vb2_buffer *vb)
++{
++	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
++	struct iep_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++
++	v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
++}
++
++static void iep_queue_cleanup(struct vb2_queue *vq, u32 state)
++{
++	struct iep_ctx *ctx = vb2_get_drv_priv(vq);
++	struct vb2_v4l2_buffer *vbuf;
++
++	do {
++		if (V4L2_TYPE_IS_OUTPUT(vq->type))
++			vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
++		else
++			vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
++
++		if (vbuf)
++			v4l2_m2m_buf_done(vbuf, state);
++	} while (vbuf);
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev_src_buf)
++		v4l2_m2m_buf_done(ctx->prev_src_buf, state);
++	else
++		iep_m2m_dst_bufs_done(ctx, state);
++}
++
++static int iep_start_streaming(struct vb2_queue *vq, unsigned int count)
++{
++	struct iep_ctx *ctx = vb2_get_drv_priv(vq);
++	struct device *dev = ctx->iep->dev;
++	int ret;
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
++		ret = pm_runtime_get_sync(dev);
++		if (ret < 0) {
++			dev_err(dev, "Failed to enable module\n");
++			goto err_runtime_get;
++		}
++
++		ctx->field_order_bff =
++			ctx->src_fmt.pix.field == V4L2_FIELD_INTERLACED_BT;
++		ctx->field_bff = ctx->field_order_bff;
++
++		ctx->src_sequence = 0;
++		ctx->dst_sequence = 0;
++
++		ctx->prev_src_buf = NULL;
++
++		ctx->dst0_buf = NULL;
++		ctx->dst1_buf = NULL;
++		ctx->dst_buffs_done = 0;
++
++		ctx->job_abort = false;
++
++		iep_init(ctx->iep);
++		//if (ctx->src_fmt.pix.field != ctx->dst_fmt.pix.field)
++		iep_dein_init(ctx->iep);
++	}
++
++	return 0;
++
++err_runtime_get:
++	iep_queue_cleanup(vq, VB2_BUF_STATE_QUEUED);
++
++	return ret;
++}
++
++static void iep_stop_streaming(struct vb2_queue *vq)
++{
++	struct iep_ctx *ctx = vb2_get_drv_priv(vq);
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
++		pm_runtime_mark_last_busy(ctx->iep->dev);
++		pm_runtime_put_autosuspend(ctx->iep->dev);
++	}
++
++	iep_queue_cleanup(vq, VB2_BUF_STATE_ERROR);
++}
++
++static const struct vb2_ops iep_qops = {
++	.queue_setup		= iep_queue_setup,
++	.buf_prepare		= iep_buf_prepare,
++	.buf_queue		= iep_buf_queue,
++	.start_streaming	= iep_start_streaming,
++	.stop_streaming		= iep_stop_streaming,
++	.wait_prepare		= vb2_ops_wait_prepare,
++	.wait_finish		= vb2_ops_wait_finish,
++};
++
++static int iep_queue_init(void *priv, struct vb2_queue *src_vq,
++			  struct vb2_queue *dst_vq)
++{
++	struct iep_ctx *ctx = priv;
++	int ret;
++
++	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
++	src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
++			    DMA_ATTR_NO_KERNEL_MAPPING;
++	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
++	src_vq->drv_priv = ctx;
++	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	src_vq->min_queued_buffers = 1;
++	src_vq->ops = &iep_qops;
++	src_vq->mem_ops = &vb2_dma_contig_memops;
++	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	src_vq->lock = &ctx->iep->mutex;
++	src_vq->dev = ctx->iep->v4l2_dev.dev;
++
++	ret = vb2_queue_init(src_vq);
++	if (ret)
++		return ret;
++
++	dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
++			    DMA_ATTR_NO_KERNEL_MAPPING;
++	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
++	dst_vq->drv_priv = ctx;
++	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	dst_vq->min_queued_buffers = 2;
++	dst_vq->ops = &iep_qops;
++	dst_vq->mem_ops = &vb2_dma_contig_memops;
++	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	dst_vq->lock = &ctx->iep->mutex;
++	dst_vq->dev = ctx->iep->v4l2_dev.dev;
++
++	ret = vb2_queue_init(dst_vq);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static void iep_prepare_format(struct v4l2_pix_format *pix_fmt)
++{
++	unsigned int height = pix_fmt->height;
++	unsigned int width = pix_fmt->width;
++	unsigned int sizeimage, bytesperline;
++
++	struct iep_fmt *hw_fmt = iep_fmt_find(pix_fmt);
++
++	if (!hw_fmt) {
++		hw_fmt = &formats[0];
++		pix_fmt->pixelformat = hw_fmt->fourcc;
++	}
++
++	width = ALIGN(clamp(width, IEP_MIN_WIDTH,
++			    IEP_MAX_WIDTH), 16);
++	height = ALIGN(clamp(height, IEP_MIN_HEIGHT,
++			     IEP_MAX_HEIGHT), 16);
++
++	bytesperline = FMT_IS_YUV(hw_fmt->hw_format)
++		       ? width : (width * hw_fmt->depth) >> 3;
++
++	sizeimage = height * (width * hw_fmt->depth) >> 3;
++
++	pix_fmt->width = width;
++	pix_fmt->height = height;
++	pix_fmt->bytesperline = bytesperline;
++	pix_fmt->sizeimage = sizeimage;
++}
++
++static int iep_open(struct file *file)
++{
++	struct rockchip_iep *iep = video_drvdata(file);
++	struct iep_ctx *ctx = NULL;
++
++	int ret;
++
++	if (mutex_lock_interruptible(&iep->mutex))
++		return -ERESTARTSYS;
++
++	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
++	if (!ctx) {
++		mutex_unlock(&iep->mutex);
++		return -ENOMEM;
++	}
++
++	/* default output format */
++	ctx->src_fmt.pix.pixelformat = formats[0].fourcc;
++	ctx->src_fmt.pix.field = V4L2_FIELD_INTERLACED;
++	ctx->src_fmt.pix.width = IEP_DEFAULT_WIDTH;
++	ctx->src_fmt.pix.height = IEP_DEFAULT_HEIGHT;
++	iep_prepare_format(&ctx->src_fmt.pix);
++	ctx->src_fmt.hw_fmt = &formats[0];
++	ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height);
++	ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height,
++					       ctx->src_fmt.hw_fmt->uv_factor);
++
++	/* default capture format */
++	ctx->dst_fmt.pix.pixelformat = formats[0].fourcc;
++	ctx->dst_fmt.pix.field = V4L2_FIELD_NONE;
++	ctx->dst_fmt.pix.width = IEP_DEFAULT_WIDTH;
++	ctx->dst_fmt.pix.height = IEP_DEFAULT_HEIGHT;
++	iep_prepare_format(&ctx->dst_fmt.pix);
++	ctx->dst_fmt.hw_fmt = &formats[0];
++	ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height);
++	ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height,
++					       ctx->dst_fmt.hw_fmt->uv_factor);
++	/* ensure fmts are written to HW */
++	ctx->fmt_changed = true;
++
++	v4l2_fh_init(&ctx->fh, video_devdata(file));
++	file->private_data = &ctx->fh;
++	ctx->iep = iep;
++
++	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(iep->m2m_dev, ctx,
++					    &iep_queue_init);
++
++	if (IS_ERR(ctx->fh.m2m_ctx)) {
++		ret = PTR_ERR(ctx->fh.m2m_ctx);
++		goto err_free;
++	}
++
++	v4l2_fh_add(&ctx->fh);
++
++	mutex_unlock(&iep->mutex);
++
++	return 0;
++
++err_free:
++	kfree(ctx);
++	mutex_unlock(&iep->mutex);
++
++	return ret;
++}
++
++static int iep_release(struct file *file)
++{
++	struct rockchip_iep *iep = video_drvdata(file);
++	struct iep_ctx *ctx = container_of(file->private_data,
++						   struct iep_ctx, fh);
++
++	mutex_lock(&iep->mutex);
++
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
++	kfree(ctx);
++
++	mutex_unlock(&iep->mutex);
++	return 0;
++}
++
++static const struct v4l2_file_operations iep_fops = {
++	.owner		= THIS_MODULE,
++	.open		= iep_open,
++	.release	= iep_release,
++	.poll		= v4l2_m2m_fop_poll,
++	.unlocked_ioctl	= video_ioctl2,
++	.mmap		= v4l2_m2m_fop_mmap,
++};
++
++static int iep_querycap(struct file *file, void *priv,
++			struct v4l2_capability *cap)
++{
++	strscpy(cap->driver, IEP_NAME, sizeof(cap->driver));
++	strscpy(cap->card, IEP_NAME, sizeof(cap->card));
++	snprintf(cap->bus_info, sizeof(cap->bus_info),
++		 "platform:%s", IEP_NAME);
++
++	return 0;
++}
++
++static int iep_enum_fmt(struct file *file, void *priv,
++			struct v4l2_fmtdesc *f)
++{
++	struct iep_fmt *fmt;
++
++	if (f->index < ARRAY_SIZE(formats)) {
++		fmt = &formats[f->index];
++		f->pixelformat = fmt->fourcc;
++
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
++static int iep_enum_framesizes(struct file *file, void *priv,
++			       struct v4l2_frmsizeenum *fsize)
++{
++	if (fsize->index != 0)
++		return -EINVAL;
++
++	if (!iep_check_pix_format(fsize->pixel_format))
++		return -EINVAL;
++
++	fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
++
++	fsize->stepwise.min_width = IEP_MIN_WIDTH;
++	fsize->stepwise.max_width = IEP_MAX_WIDTH;
++	fsize->stepwise.step_width = 16;
++
++	fsize->stepwise.min_height = IEP_MIN_HEIGHT;
++	fsize->stepwise.max_height = IEP_MAX_HEIGHT;
++	fsize->stepwise.step_height = 16;
++
++	return 0;
++}
++
++static inline struct iep_ctx *iep_file2ctx(struct file *file)
++{
++	return container_of(file->private_data, struct iep_ctx, fh);
++}
++
++static int iep_g_fmt_vid_cap(struct file *file, void *priv,
++			     struct v4l2_format *f)
++{
++	struct iep_ctx *ctx = iep_file2ctx(file);
++
++	f->fmt.pix = ctx->dst_fmt.pix;
++
++	return 0;
++}
++
++static int iep_g_fmt_vid_out(struct file *file, void *priv,
++			     struct v4l2_format *f)
++{
++	struct iep_ctx *ctx = iep_file2ctx(file);
++
++	f->fmt.pix = ctx->src_fmt.pix;
++
++	return 0;
++}
++
++static int iep_try_fmt_vid_cap(struct file *file, void *priv,
++			       struct v4l2_format *f)
++{
++	f->fmt.pix.field = V4L2_FIELD_NONE;
++	iep_prepare_format(&f->fmt.pix);
++
++	return 0;
++}
++
++static int iep_try_fmt_vid_out(struct file *file, void *priv,
++			       struct v4l2_format *f)
++{
++	if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB &&
++	    f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT &&
++	    f->fmt.pix.field != V4L2_FIELD_INTERLACED)
++		f->fmt.pix.field = V4L2_FIELD_INTERLACED;
++
++	iep_prepare_format(&f->fmt.pix);
++
++	return 0;
++}
++
++static int iep_s_fmt_vid_out(struct file *file, void *priv,
++			     struct v4l2_format *f)
++{
++	struct iep_ctx *ctx = iep_file2ctx(file);
++	struct vb2_queue *vq;
++
++	int ret;
++
++	ret = iep_try_fmt_vid_out(file, priv, f);
++	if (ret)
++		return ret;
++
++	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
++	if (vb2_is_busy(vq))
++		return -EBUSY;
++
++	ctx->src_fmt.pix = f->fmt.pix;
++	ctx->src_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix);
++	ctx->src_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
++	ctx->src_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
++					       ctx->src_fmt.hw_fmt->uv_factor);
++
++	/* Propagate colorspace information to capture. */
++	ctx->dst_fmt.pix.colorspace = f->fmt.pix.colorspace;
++	ctx->dst_fmt.pix.xfer_func = f->fmt.pix.xfer_func;
++	ctx->dst_fmt.pix.ycbcr_enc = f->fmt.pix.ycbcr_enc;
++	ctx->dst_fmt.pix.quantization = f->fmt.pix.quantization;
++
++	/* scaling is not supported */
++	ctx->dst_fmt.pix.width = f->fmt.pix.width;
++	ctx->dst_fmt.pix.height = f->fmt.pix.height;
++	ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
++	ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
++					       ctx->dst_fmt.hw_fmt->uv_factor);
++
++	ctx->fmt_changed = true;
++
++	return 0;
++}
++
++static int iep_s_fmt_vid_cap(struct file *file, void *priv,
++			     struct v4l2_format *f)
++{
++	struct iep_ctx *ctx = iep_file2ctx(file);
++	struct vb2_queue *vq;
++	int ret;
++
++	ret = iep_try_fmt_vid_cap(file, priv, f);
++	if (ret)
++		return ret;
++
++	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
++	if (vb2_is_busy(vq))
++		return -EBUSY;
++
++	/* scaling is not supported */
++	f->fmt.pix.width = ctx->src_fmt.pix.width;
++	f->fmt.pix.height = ctx->src_fmt.pix.height;
++
++	ctx->dst_fmt.pix = f->fmt.pix;
++	ctx->dst_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix);
++
++	ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
++	ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
++					       ctx->dst_fmt.hw_fmt->uv_factor);
++
++	ctx->fmt_changed = true;
++
++	return 0;
++}
++
++static const struct v4l2_ioctl_ops iep_ioctl_ops = {
++	.vidioc_querycap		= iep_querycap,
++
++	.vidioc_enum_framesizes		= iep_enum_framesizes,
++
++	.vidioc_enum_fmt_vid_cap	= iep_enum_fmt,
++	.vidioc_g_fmt_vid_cap		= iep_g_fmt_vid_cap,
++	.vidioc_try_fmt_vid_cap		= iep_try_fmt_vid_cap,
++	.vidioc_s_fmt_vid_cap		= iep_s_fmt_vid_cap,
++
++	.vidioc_enum_fmt_vid_out	= iep_enum_fmt,
++	.vidioc_g_fmt_vid_out		= iep_g_fmt_vid_out,
++	.vidioc_try_fmt_vid_out		= iep_try_fmt_vid_out,
++	.vidioc_s_fmt_vid_out		= iep_s_fmt_vid_out,
++
++	.vidioc_reqbufs			= v4l2_m2m_ioctl_reqbufs,
++	.vidioc_querybuf		= v4l2_m2m_ioctl_querybuf,
++	.vidioc_qbuf			= v4l2_m2m_ioctl_qbuf,
++	.vidioc_dqbuf			= v4l2_m2m_ioctl_dqbuf,
++	.vidioc_prepare_buf		= v4l2_m2m_ioctl_prepare_buf,
++	.vidioc_create_bufs		= v4l2_m2m_ioctl_create_bufs,
++	.vidioc_expbuf			= v4l2_m2m_ioctl_expbuf,
++
++	.vidioc_streamon		= v4l2_m2m_ioctl_streamon,
++	.vidioc_streamoff		= v4l2_m2m_ioctl_streamoff,
++};
++
++static const struct video_device iep_video_device = {
++	.name		= IEP_NAME,
++	.vfl_dir	= VFL_DIR_M2M,
++	.fops		= &iep_fops,
++	.ioctl_ops	= &iep_ioctl_ops,
++	.minor		= -1,
++	.release	= video_device_release_empty,
++	.device_caps	= V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
++};
++
++static int iep_parse_dt(struct rockchip_iep *iep)
++{
++	int ret = 0;
++
++	iep->axi_clk = devm_clk_get(iep->dev, "axi");
++	if (IS_ERR(iep->axi_clk)) {
++		dev_err(iep->dev, "failed to get aclk clock\n");
++		return PTR_ERR(iep->axi_clk);
++	}
++
++	iep->ahb_clk = devm_clk_get(iep->dev, "ahb");
++	if (IS_ERR(iep->ahb_clk)) {
++		dev_err(iep->dev, "failed to get hclk clock\n");
++		return PTR_ERR(iep->ahb_clk);
++	}
++
++	ret = clk_set_rate(iep->axi_clk, 300000000);
++
++	if (ret)
++		dev_err(iep->dev, "failed to set axi clock rate to 300 MHz\n");
++
++	return ret;
++}
++
++static irqreturn_t iep_isr(int irq, void *prv)
++{
++	struct rockchip_iep *iep = prv;
++	struct iep_ctx *ctx;
++	u32 val;
++	enum vb2_buffer_state state = VB2_BUF_STATE_DONE;
++
++	ctx = v4l2_m2m_get_curr_priv(iep->m2m_dev);
++	if (!ctx) {
++		v4l2_err(&iep->v4l2_dev,
++			 "Instance released before the end of transaction\n");
++		return IRQ_NONE;
++	}
++
++	/*
++	 * The irq is shared with the iommu. If the runtime-pm state of the
++	 * iep-device is disabled or the interrupt status doesn't match the
++	 * expeceted mask the irq has been targeted to the iommu.
++	 */
++
++	if (!pm_runtime_active(iep->dev) ||
++	    !(iep_read(iep, IEP_INT) & IEP_INT_MASK))
++		return IRQ_NONE;
++
++	/* disable interrupt - will be re-enabled at next iep_device_run */
++	iep_mod(ctx->iep, IEP_INT,
++		IEP_INT_FRAME_DONE_EN, 0);
++
++	iep_mod(iep, IEP_INT, IEP_INT_FRAME_DONE_CLR,
++		IEP_INT_FRAME_DONE_CLR);
++
++	/* wait for all status regs to show "idle" */
++	val = readl_poll_timeout(iep->regs + IEP_STATUS, val,
++				  (val == 0), 100, IEP_TIMEOUT);
++
++	if (val) {
++		dev_err(iep->dev,
++			"Failed to wait for job to finish: status: %u\n", val);
++		state = VB2_BUF_STATE_ERROR;
++		ctx->job_abort = true;
++	}
++
++	iep_m2m_dst_bufs_done(ctx, state);
++
++	ctx->field_bff = (ctx->dst_buffs_done % 2 == 0)
++		     ? ctx->field_order_bff : !ctx->field_order_bff;
++
++	if (ctx->dst_buffs_done == 2 || ctx->job_abort) {
++		if (ctx->prev_src_buf)
++			v4l2_m2m_buf_done(ctx->prev_src_buf, state);
++
++		/* current src buff will be next prev */
++		ctx->prev_src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
++
++		v4l2_m2m_job_finish(ctx->iep->m2m_dev, ctx->fh.m2m_ctx);
++		ctx->dst_buffs_done = 0;
++
++	} else {
++		iep_device_run(ctx);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static int iep_probe(struct platform_device *pdev)
++{
++	struct rockchip_iep *iep;
++	struct video_device *vfd;
++	struct resource *res;
++	int ret = 0;
++	int irq;
++
++	if (!pdev->dev.of_node)
++		return -ENODEV;
++
++	iep = devm_kzalloc(&pdev->dev, sizeof(*iep), GFP_KERNEL);
++	if (!iep)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, iep);
++	iep->dev = &pdev->dev;
++	iep->vfd = iep_video_device;
++
++	ret = iep_parse_dt(iep);
++	if (ret)
++		dev_err(&pdev->dev, "Unable to parse OF data\n");
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++	iep->regs = devm_ioremap_resource(iep->dev, res);
++	if (IS_ERR(iep->regs)) {
++		ret = PTR_ERR(iep->regs);
++		goto err_put_clk;
++	}
++
++	ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++	if (ret) {
++		dev_err(&pdev->dev, "Could not set DMA coherent mask.\n");
++		goto err_put_clk;
++	}
++
++	vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0) {
++		ret = irq;
++		goto err_put_clk;
++	}
++
++	/* IRQ is shared with IOMMU */
++	ret = devm_request_irq(iep->dev, irq, iep_isr, IRQF_SHARED,
++			       dev_name(iep->dev), iep);
++	if (ret < 0) {
++		dev_err(iep->dev, "failed to request irq\n");
++		goto err_put_clk;
++	}
++
++	mutex_init(&iep->mutex);
++
++	ret = v4l2_device_register(&pdev->dev, &iep->v4l2_dev);
++	if (ret) {
++		dev_err(iep->dev, "Failed to register V4L2 device\n");
++
++		return ret;
++	}
++
++	vfd = &iep->vfd;
++	vfd->lock = &iep->mutex;
++	vfd->v4l2_dev = &iep->v4l2_dev;
++
++	snprintf(vfd->name, sizeof(vfd->name), "%s",
++		 iep_video_device.name);
++
++	video_set_drvdata(vfd, iep);
++
++	ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
++	if (ret) {
++		v4l2_err(&iep->v4l2_dev, "Failed to register video device\n");
++
++		goto err_v4l2;
++	}
++
++	v4l2_info(&iep->v4l2_dev,
++		  "Device %s registered as /dev/video%d\n", vfd->name, vfd->num);
++
++	iep->m2m_dev = v4l2_m2m_init(&iep_m2m_ops);
++	if (IS_ERR(iep->m2m_dev)) {
++		v4l2_err(&iep->v4l2_dev,
++			 "Failed to initialize V4L2 M2M device\n");
++		ret = PTR_ERR(iep->m2m_dev);
++
++		goto err_video;
++	}
++
++	pm_runtime_set_autosuspend_delay(iep->dev, 100);
++	pm_runtime_use_autosuspend(iep->dev);
++	pm_runtime_enable(iep->dev);
++
++	return ret;
++
++err_video:
++	video_unregister_device(&iep->vfd);
++err_v4l2:
++	v4l2_device_unregister(&iep->v4l2_dev);
++err_put_clk:
++	pm_runtime_dont_use_autosuspend(iep->dev);
++	pm_runtime_disable(iep->dev);
++
++return ret;
++}
++
++static int iep_remove(struct platform_device *pdev)
++{
++	struct rockchip_iep *iep = platform_get_drvdata(pdev);
++
++	pm_runtime_dont_use_autosuspend(iep->dev);
++	pm_runtime_disable(iep->dev);
++
++	v4l2_m2m_release(iep->m2m_dev);
++	video_unregister_device(&iep->vfd);
++	v4l2_device_unregister(&iep->v4l2_dev);
++
++	return 0;
++}
++
++static int __maybe_unused iep_runtime_suspend(struct device *dev)
++{
++	struct rockchip_iep *iep = dev_get_drvdata(dev);
++
++	clk_disable_unprepare(iep->ahb_clk);
++	clk_disable_unprepare(iep->axi_clk);
++
++	return 0;
++}
++
++static int __maybe_unused iep_runtime_resume(struct device *dev)
++{
++	struct rockchip_iep *iep;
++	int ret = 0;
++
++	iep = dev_get_drvdata(dev);
++
++	ret = clk_prepare_enable(iep->axi_clk);
++	if (ret) {
++		dev_err(iep->dev, "Cannot enable axi clock: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(iep->ahb_clk);
++	if (ret) {
++		dev_err(iep->dev, "Cannot enable ahb clock: %d\n", ret);
++		goto err_disable_axi_clk;
++	}
++
++	return ret;
++
++err_disable_axi_clk:
++	clk_disable_unprepare(iep->axi_clk);
++	return ret;
++}
++
++static const struct dev_pm_ops iep_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
++	SET_RUNTIME_PM_OPS(iep_runtime_suspend,
++			   iep_runtime_resume, NULL)
++};
++
++static const struct of_device_id rockchip_iep_match[] = {
++	{
++		.compatible = "rockchip,rk3228-iep",
++	},
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, rockchip_iep_match);
++
++static struct platform_driver iep_pdrv = {
++	.probe = iep_probe,
++	.remove = iep_remove,
++	.driver = {
++		.name = IEP_NAME,
++		.pm = &iep_pm_ops,
++		.of_match_table = rockchip_iep_match,
++	},
++};
++
++module_platform_driver(iep_pdrv);
++
++MODULE_AUTHOR("Alex Bee <knaerzche@gmail.com>");
++MODULE_DESCRIPTION("Rockchip Image Enhancement Processor");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/media/platform/rockchip/iep/iep.h b/drivers/media/platform/rockchip/iep/iep.h
+new file mode 100644
+index 000000000000..7d9fc61624b6
+--- /dev/null
++++ b/drivers/media/platform/rockchip/iep/iep.h
+@@ -0,0 +1,112 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Rockchip Image Enhancement Processor (IEP) driver
++ *
++ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
++ *
++ */
++#ifndef __IEP_H__
++#define __IEP_H__
++
++#include <linux/platform_device.h>
++#include <media/videobuf2-v4l2.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++
++#define IEP_NAME "rockchip-iep"
++
++/* Hardware limits */
++#define IEP_MIN_WIDTH 320U
++#define IEP_MAX_WIDTH 1920U
++
++#define IEP_MIN_HEIGHT 240U
++#define IEP_MAX_HEIGHT 1088U
++
++/* Hardware defaults */
++#define IEP_DEFAULT_WIDTH 320U
++#define IEP_DEFAULT_HEIGHT 240U
++
++//ns
++#define IEP_TIMEOUT 250000
++
++struct iep_fmt {
++	u32 fourcc;
++	u8 depth;
++	u8 uv_factor;
++	u8 color_swap;
++	u8 hw_format;
++};
++
++struct iep_frm_fmt {
++	struct iep_fmt *hw_fmt;
++	struct v4l2_pix_format pix;
++
++	unsigned int y_stride;
++	unsigned int uv_stride;
++};
++
++struct iep_ctx {
++	struct v4l2_fh fh;
++	struct rockchip_iep *iep;
++
++	struct iep_frm_fmt src_fmt;
++	struct iep_frm_fmt dst_fmt;
++
++	struct vb2_v4l2_buffer	*prev_src_buf;
++	struct vb2_v4l2_buffer	*dst0_buf;
++	struct vb2_v4l2_buffer	*dst1_buf;
++
++	u32 dst_sequence;
++	u32 src_sequence;
++
++	/* bff = bottom field first */
++	bool field_order_bff;
++	bool field_bff;
++
++	unsigned int dst_buffs_done;
++
++	bool fmt_changed;
++	bool job_abort;
++};
++
++struct rockchip_iep {
++	struct v4l2_device v4l2_dev;
++	struct v4l2_m2m_dev *m2m_dev;
++	struct video_device vfd;
++
++	struct device *dev;
++
++	void __iomem *regs;
++
++	struct clk *axi_clk;
++	struct clk *ahb_clk;
++
++	/* vfd lock */
++	struct mutex mutex;
++};
++
++static inline void iep_write(struct rockchip_iep *iep, u32 reg, u32 value)
++{
++	writel(value, iep->regs + reg);
++};
++
++static inline u32 iep_read(struct rockchip_iep *iep, u32 reg)
++{
++	return readl(iep->regs + reg);
++};
++
++static inline void iep_shadow_mod(struct rockchip_iep *iep, u32 reg,
++				  u32 shadow_reg, u32 mask, u32 val)
++{
++	u32 temp = iep_read(iep, shadow_reg) & ~(mask);
++
++	temp |= val & mask;
++	iep_write(iep, reg, temp);
++};
++
++static inline void iep_mod(struct rockchip_iep *iep, u32 reg, u32 mask, u32 val)
++{
++	iep_shadow_mod(iep, reg, reg, mask, val);
++};
++
++#endif
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Wed, 14 Oct 2020 20:22:38 +0200
+Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3328
+
+while at that also add the mmu required
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index eec03adf0902..5455a46c9a6b 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -760,6 +760,28 @@ vop_mmu: iommu@ff373f00 {
+ 		status = "disabled";
+ 	};
+ 
++	iep: iep@ff3a0000 {
++		compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep";
++		reg = <0x0 0xff3a0000 0x0 0x800>;
++		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "iep";
++		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++		clock-names = "axi", "ahb";
++		power-domains = <&power RK3328_PD_VIDEO>;
++		iommus = <&iep_mmu>;
++	};
++
++	iep_mmu: iommu@ff3a0800 {
++		compatible = "rockchip,iommu";
++		reg = <0x0 0xff3a0800 0x0 0x40>;
++		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "iep_mmu";
++		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++		clock-names = "aclk", "iface";
++		power-domains = <&power RK3328_PD_VIDEO>;
++		#iommu-cells = <0>;
++	};
++
+ 	hdmi: hdmi@ff3c0000 {
+ 		compatible = "rockchip,rk3328-dw-hdmi";
+ 		reg = <0x0 0xff3c0000 0x0 0x20000>;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Wed, 14 Oct 2020 20:43:12 +0200
+Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3399
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index dbe6a9cb98a5..f0629b7a81c6 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -1365,14 +1365,25 @@ vdec_mmu: iommu@ff660480 {
+ 		#iommu-cells = <0>;
+ 	};
+ 
++	iep: iep@ff670000 {
++		compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep";
++		reg = <0x0 0xff670000 0x0 0x800>;
++		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "iep";
++		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++		clock-names = "axi", "ahb";
++		power-domains = <&power RK3399_PD_IEP>;
++		iommus = <&iep_mmu>;
++	};
++
+ 	iep_mmu: iommu@ff670800 {
+ 		compatible = "rockchip,iommu";
+ 		reg = <0x0 0xff670800 0x0 0x40>;
+ 		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ 		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ 		clock-names = "aclk", "iface";
++		power-domains = <&power RK3399_PD_IEP>;
+ 		#iommu-cells = <0>;
+-		status = "disabled";
+ 	};
+ 
+ 	rga: rga@ff680000 {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Wed, 14 Oct 2020 20:53:56 +0200
+Subject: [PATCH] ARM: dts: rockchip: Add IEP node for RK3288
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm/boot/dts/rockchip/rk3288.dtsi | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index 59fba3ac6aae..06545f423de2 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -984,14 +984,25 @@ crypto: crypto@ff8a0000 {
+ 		reset-names = "crypto-rst";
+ 	};
+ 
++	iep: iep@ff90000 {
++		compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep";
++		reg = <0x0 0xff900000 0x0 0x800>;
++		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "iep";
++		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++		clock-names = "axi", "ahb";
++		power-domains = <&power RK3288_PD_VIO>;
++		iommus = <&iep_mmu>;
++	};
++
+ 	iep_mmu: iommu@ff900800 {
+ 		compatible = "rockchip,iommu";
+ 		reg = <0x0 0xff900800 0x0 0x40>;
+ 		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ 		clock-names = "aclk", "iface";
++		power-domains = <&power RK3288_PD_VIO>;
+ 		#iommu-cells = <0>;
+-		status = "disabled";
+ 	};
+ 
+ 	isp_mmu: iommu@ff914000 {
diff --git a/patch/kernel/archive/rockchip-6.10/series.conf b/patch/kernel/archive/rockchip-6.10/series.conf
new file mode 100644
index 000000000000..530f1fbbb0cf
--- /dev/null
+++ b/patch/kernel/archive/rockchip-6.10/series.conf
@@ -0,0 +1,62 @@
+# Series from patches.libreelec/
+	patches.libreelec/linux-0002-rockchip-from-list.patch
+	patches.libreelec/linux-0011-v4l2-from-list.patch
+	patches.libreelec/linux-1000-drm-rockchip.patch
+	patches.libreelec/linux-1001-v4l2-rockchip.patch
+	patches.libreelec/linux-1002-for-libreelec.patch
+	patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch
+	patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch
+	patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch
+# Series from patches.armbian/
+	patches.armbian/bt-broadcom-serdev-workaround.patch
+	patches.armbian/clk-rk322x-composite-mmc-clk.patch
+	patches.armbian/clk-rockchip-max-frac-divider.patch
+	patches.armbian/driver-rk322x-audio-codec.patch
+	patches.armbian/driver-rk3288-gpiomem.patch
+	patches.armbian/driver-tinkerboard-alc4040-codec.patch
+	patches.armbian/drm-rk322x-plane-overlay.patch
+	patches.armbian/drm-rk322x-yuv-10bit-modes.patch
+	patches.armbian/drm-rockchip-hardware-cursor.patch
+	patches.armbian/dts-miqi-fan.patch
+	patches.armbian/dts-miqi-hevc-rga.patch
+	patches.armbian/dts-miqi-mali-gpu.patch
+	patches.armbian/dts-miqi-regulator-fix.patch
+	patches.armbian/dts-rk322x-iep-node.patch
+	patches.armbian/dts-rk322x-pinctrl-nand.patch
+	patches.armbian/dts-rk3288-disable-serial-dma.patch
+	patches.armbian/dts-rk3288-fix-mmc-aliases.patch
+	patches.armbian/dts-rk3288-gpu-500mhz-opp.patch
+	patches.armbian/dts-rk3288-pinctrl-spi2.patch
+	patches.armbian/dts-rk3288-thermal-rearrange-zones.patch
+	patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch
+	patches.armbian/dts-tinkerboard-bt-uart-pins.patch
+	patches.armbian/dts-tinkerboard-hevc-rga.patch
+	patches.armbian/dts-tinkerboard-sdio-wifi.patch
+	patches.armbian/dts-tinkerboard-sdmmc-properties.patch
+	patches.armbian/dts-tinkerboard-spi-interface.patch
+	patches.armbian/dts-veyron-flag-cache-flush.patch
+	patches.armbian/general-add-overlay-compilation-support.patch
+	patches.armbian/general-add-overlay-configfs.patch
+	patches.armbian/general-add-restart-handler-for-act8846.patch
+	patches.armbian/general-dwc2-fix-wait-peripheral.patch
+	patches.armbian/general-dwc2-fix-wait-time.patch
+	patches.armbian/general-dwc2-nak-gadget.patch
+	patches.armbian/general-fix-reboot-from-kwiboo.patch
+	patches.armbian/general-linux-export-mm-trace-rss-stats.patch
+	patches.armbian/general-rk322x-gpio-ir-driver.patch
+	patches.armbian/general-rockchip-various-fixes.patch
+	patches.armbian/ir-keymap-rk322x-box.patch
+	patches.armbian/ir-keymap-xt-q8l-v10.patch
+	patches.armbian/misc-tinkerboard-spi-interface.patch
+	patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch
+	patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch
+	patches.armbian/rk322x-dmc-driver-02-sip-constants.patch
+	patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch
+	patches.armbian/rk322x-dmc-driver-04-driver.patch
+	patches.armbian/rk322x-dwc2-no-clock-gating.patch
+	patches.armbian/rk322x-usb-reset-props.patch
+	patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch
+	patches.armbian/wifi-brcmfmac-add-bcm43342.patch
+	patches.armbian/wifi-brcmfmac-ap6330-firmware.patch
+	patches.armbian/wifi-driver-esp8089.patch
+	patches.armbian/wifi-driver-ssv6051.patch
diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0113-add-synopsys-designware-hdmi-rx-controller.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0113-add-synopsys-designware-hdmi-rx-controller.patch
new file mode 100644
index 000000000000..e436902d4d5e
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.10/0113-add-synopsys-designware-hdmi-rx-controller.patch
@@ -0,0 +1,3770 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Wed, 7 Aug 2024 11:33:46 +0000
+Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi         |   42 +
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi                 |   57 +
+ drivers/media/platform/Kconfig                           |    1 +
+ drivers/media/platform/Makefile                          |    1 +
+ drivers/media/platform/synopsys/Kconfig                  |    3 +
+ drivers/media/platform/synopsys/Makefile                 |    2 +
+ drivers/media/platform/synopsys/hdmirx/Kconfig           |   27 +
+ drivers/media/platform/synopsys/hdmirx/Makefile          |    4 +
+ drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c     | 2763 ++++++++++
+ drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h     |  394 ++
+ drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c |  285 +
+ drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h |   44 +
+ 12 files changed, 3623 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi
+@@ -169,6 +169,48 @@ hdmim0_tx1_sda: hdmim0-tx1-sda {
+ 				/* hdmim0_tx1_sda */
+ 				<2 RK_PB4 4 &pcfg_pull_none>;
+ 		};
++
++        /omit-if-no-ref/
++		hdmim1_rx: hdmim1-rx {
++			rockchip,pins =
++				/* hdmim1_rx_cec */
++				<3 RK_PD1 5 &pcfg_pull_none>,
++				/* hdmim1_rx_scl */
++				<3 RK_PD2 5 &pcfg_pull_none_smt>,
++				/* hdmim1_rx_sda */
++				<3 RK_PD3 5 &pcfg_pull_none_smt>,
++				/* hdmim1_rx_hpdin */
++				<3 RK_PD4 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_rx_cec: hdmim1-rx-cec {
++			rockchip,pins =
++				/* hdmim1_rx_cec */
++				<3 RK_PD1 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_rx_hpdin: hdmim1-rx-hpdin {
++			rockchip,pins =
++				/* hdmim1_rx_hpdin */
++				<3 RK_PD4 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_rx_scl: hdmim1-rx-scl {
++			rockchip,pins =
++				/* hdmim1_rx_scl */
++				<3 RK_PD2 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_rx_sda: hdmim1-rx-sda {
++			rockchip,pins =
++				/* hdmim1_rx_sda */
++				<3 RK_PD3 5 &pcfg_pull_none>;
++		};
++
+ 	};
+ 
+ 	i2c0 {
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -7,6 +7,29 @@
+ #include "rk3588-pinctrl.dtsi"
+ 
+ / {
++    reserved-memory {
++       #address-cells = <2>;
++       #size-cells = <2>;
++       ranges;
++
++       /*
++        * The 4k HDMI capture controller works only with 32bit
++        * phys addresses and doesn't support IOMMU. HDMI RX CMA
++        * must be reserved below 4GB.
++        * The size of 160MB was determined as follows:
++        * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB
++        * To ensure sufficient support for practical use-cases,
++        * we doubled the 66MB value.
++        */
++       hdmi_receiver_cma: hdmi-receiver-cma {
++           compatible = "shared-dma-pool";
++           alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
++           size = <0x0 (160 * 0x100000)>; /* 160MiB */
++           no-map;
++           status = "disabled";
++       };
++   };
++
+ 	usb_host1_xhci: usb@fc400000 {
+ 		compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ 		reg = <0x0 0xfc400000 0x0 0x400000>;
+@@ -27,6 +50,40 @@ usb_host1_xhci: usb@fc400000 {
+ 		status = "disabled";
+ 	};
+ 
++    hdmi_receiver: hdmi_receiver@fdee0000 {
++        compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
++        reg = <0x0 0xfdee0000 0x0 0x6000>;
++        power-domains = <&power RK3588_PD_VO1>;
++        rockchip,grf = <&sys_grf>;
++        rockchip,vo1-grf = <&vo1_grf>;
++        interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
++                 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
++                 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
++        interrupt-names = "cec", "hdmi", "dma";
++        clocks = <&cru ACLK_HDMIRX>,
++             <&cru CLK_HDMIRX_AUD>,
++             <&cru CLK_CR_PARA>,
++             <&cru PCLK_HDMIRX>,
++             <&cru CLK_HDMIRX_REF>,
++             <&cru PCLK_S_HDMIRX>,
++             <&cru HCLK_VO1>;
++        clock-names = "aclk",
++                  "audio",
++                  "cr_para",
++                  "pclk",
++                  "ref",
++                  "hclk_s_hdmirx",
++                  "hclk_vo1";
++        resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
++             <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
++        reset-names = "axi", "apb", "ref", "biu";
++        memory-region = <&hdmi_receiver_cma>;
++       pinctrl-0 = <&hdmim1_rx>;
++       pinctrl-names = "default";
++       status = "disabled";
++   };
++
++
+ 	pcie30_phy_grf: syscon@fd5b8000 {
+ 		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
+ 		reg = <0x0 0xfd5b8000 0x0 0x10000>;
+diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/Kconfig
++++ b/drivers/media/platform/Kconfig
+@@ -83,6 +83,7 @@ source "drivers/media/platform/rockchip/Kconfig"
+ source "drivers/media/platform/samsung/Kconfig"
+ source "drivers/media/platform/st/Kconfig"
+ source "drivers/media/platform/sunxi/Kconfig"
++source "drivers/media/platform/synopsys/Kconfig"
+ source "drivers/media/platform/ti/Kconfig"
+ source "drivers/media/platform/verisilicon/Kconfig"
+ source "drivers/media/platform/via/Kconfig"
+diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/Makefile
++++ b/drivers/media/platform/Makefile
+@@ -26,6 +26,7 @@ obj-y += rockchip/
+ obj-y += samsung/
+ obj-y += st/
+ obj-y += sunxi/
++obj-y += synopsys/
+ obj-y += ti/
+ obj-y += verisilicon/
+ obj-y += via/
+diff --git a/drivers/media/platform/synopsys/Kconfig b/drivers/media/platform/synopsys/Kconfig
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/Kconfig
+@@ -0,0 +1,3 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++source "drivers/media/platform/synopsys/hdmirx/Kconfig"
+diff --git a/drivers/media/platform/synopsys/Makefile b/drivers/media/platform/synopsys/Makefile
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0-only
++obj-y += hdmirx/
+diff --git a/drivers/media/platform/synopsys/hdmirx/Kconfig b/drivers/media/platform/synopsys/hdmirx/Kconfig
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/Kconfig
+@@ -0,0 +1,27 @@
++# SPDX-License-Identifier: GPL-2.0
++
++config VIDEO_SYNOPSYS_HDMIRX
++	tristate "Synopsys DesignWare HDMI Receiver driver"
++	depends on VIDEO_DEV
++	depends on ARCH_ROCKCHIP
++	select MEDIA_CONTROLLER
++	select VIDEO_V4L2_SUBDEV_API
++	select VIDEOBUF2_DMA_CONTIG
++	select CEC_CORE
++	select CEC_NOTIFIER
++	select HDMI
++	help
++	  Support for Synopsys HDMI HDMI RX Controller.
++	  This driver supports HDMI 2.0 version.
++
++	  To compile this driver as a module, choose M here. The module
++	  will be called synopsys_hdmirx.
++
++config HDMIRX_LOAD_DEFAULT_EDID
++	bool "Load default EDID"
++	depends on VIDEO_SYNOPSYS_HDMIRX
++	default "y"
++	help
++	  Preload the default EDID (Extended Display Identification Data).
++	  EDID contains information about the capabilities of the display,
++	  such as supported resolutions, refresh rates, and audio formats.
+diff --git a/drivers/media/platform/synopsys/hdmirx/Makefile b/drivers/media/platform/synopsys/hdmirx/Makefile
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/Makefile
+@@ -0,0 +1,4 @@
++# SPDX-License-Identifier: GPL-2.0
++synopsys-hdmirx-objs := snps_hdmirx.o snps_hdmirx_cec.o
++
++obj-$(CONFIG_VIDEO_SYNOPSYS_HDMIRX) += synopsys-hdmirx.o
+diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
+@@ -0,0 +1,2763 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2024 Collabora, Ltd.
++ * Author: Shreeya Patel <shreeya.patel@collabora.com>
++ *
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ * Author: Dingxian Wen <shawn.wen@rock-chips.com>
++ */
++
++#include <linux/arm-smccc.h>
++#include <linux/clk.h>
++#include <linux/completion.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/gpio/consumer.h>
++#include <linux/hdmi.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/of_reserved_mem.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/platform_device.h>
++#include <linux/property.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/v4l2-dv-timings.h>
++#include <linux/workqueue.h>
++
++#include <media/cec.h>
++#include <media/cec-notifier.h>
++#include <media/v4l2-common.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-dv-timings.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-fh.h>
++#include <media/v4l2-ioctl.h>
++#include <media/videobuf2-dma-contig.h>
++#include <media/videobuf2-v4l2.h>
++#include <media/v4l2-common.h>
++
++#include <sound/hdmi-codec.h>
++
++#include "snps_hdmirx.h"
++#include "snps_hdmirx_cec.h"
++
++static int debug;
++module_param(debug, int, 0644);
++MODULE_PARM_DESC(debug, "debug level (0-3)");
++
++#define EDID_NUM_BLOCKS_MAX			2
++#define EDID_BLOCK_SIZE				128
++#define HDMIRX_STORED_BIT_WIDTH			8
++#define IREF_CLK_FREQ_HZ			428571429
++#define MEMORY_ALIGN_ROUND_UP_BYTES		64
++#define HDMIRX_PLANE_Y				0
++#define HDMIRX_PLANE_CBCR			1
++#define RK_IRQ_HDMIRX_HDMI			210
++#define FILTER_FRAME_CNT			6
++#define RK_SIP_FIQ_CTRL				0x82000024
++#define SIP_WDT_CFG				0x82000026
++#define DETECTION_THRESHOLD			7
++
++/* fiq control sub func */
++enum {
++	RK_SIP_FIQ_CTRL_FIQ_EN = 1,
++	RK_SIP_FIQ_CTRL_FIQ_DIS,
++	RK_SIP_FIQ_CTRL_SET_AFF
++};
++
++/* SIP_WDT_CONFIG call types  */
++enum {
++	WDT_START = 0,
++	WDT_STOP = 1,
++	WDT_PING = 2,
++};
++
++enum hdmirx_pix_fmt {
++	HDMIRX_RGB888 = 0,
++	HDMIRX_YUV422 = 1,
++	HDMIRX_YUV444 = 2,
++	HDMIRX_YUV420 = 3,
++};
++
++enum ddr_store_fmt {
++	STORE_RGB888 = 0,
++	STORE_RGBA_ARGB,
++	STORE_YUV420_8BIT,
++	STORE_YUV420_10BIT,
++	STORE_YUV422_8BIT,
++	STORE_YUV422_10BIT,
++	STORE_YUV444_8BIT,
++	STORE_YUV420_16BIT = 8,
++	STORE_YUV422_16BIT = 9,
++};
++
++enum hdmirx_reg_attr {
++	HDMIRX_ATTR_RW = 0,
++	HDMIRX_ATTR_RO = 1,
++	HDMIRX_ATTR_WO = 2,
++	HDMIRX_ATTR_RE = 3,
++};
++
++enum {
++	HDMIRX_RST_A,
++	HDMIRX_RST_P,
++	HDMIRX_RST_REF,
++	HDMIRX_RST_BIU,
++	HDMIRX_NUM_RST,
++};
++
++static const char * const pix_fmt_str[] = {
++	"RGB888",
++	"YUV422",
++	"YUV444",
++	"YUV420",
++};
++
++struct hdmirx_buffer {
++	struct vb2_v4l2_buffer vb;
++	struct list_head queue;
++	u32 buff_addr[VIDEO_MAX_PLANES];
++};
++
++struct hdmirx_stream {
++	struct snps_hdmirx_dev *hdmirx_dev;
++	struct video_device vdev;
++	struct vb2_queue buf_queue;
++	struct list_head buf_head;
++	struct hdmirx_buffer *curr_buf;
++	struct hdmirx_buffer *next_buf;
++	struct v4l2_pix_format_mplane pixm;
++	const struct v4l2_format_info *out_finfo;
++	struct mutex vlock; /* to lock resources associated with video buffer and video device */
++	spinlock_t vbq_lock; /* to lock video buffer queue */
++	bool stopping;
++	wait_queue_head_t wq_stopped;
++	u32 frame_idx;
++	u32 line_flag_int_cnt;
++	u32 irq_stat;
++};
++
++struct snps_hdmirx_dev {
++	struct device *dev;
++	struct device *codec_dev;
++	struct hdmirx_stream stream;
++	struct v4l2_device v4l2_dev;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *detect_tx_5v_ctrl;
++	struct v4l2_ctrl *rgb_range;
++	struct v4l2_dv_timings timings;
++	struct gpio_desc *detect_5v_gpio;
++	struct work_struct work_wdt_config;
++	struct delayed_work delayed_work_hotplug;
++	struct delayed_work delayed_work_res_change;
++	struct delayed_work delayed_work_heartbeat;
++	struct cec_notifier *cec_notifier;
++	struct hdmirx_cec *cec;
++	struct mutex stream_lock; /* to lock video stream capture */
++	struct mutex work_lock; /* to lock the critical section of hotplug event */
++	struct reset_control_bulk_data resets[HDMIRX_NUM_RST];
++	struct clk_bulk_data *clks;
++	struct regmap *grf;
++	struct regmap *vo1_grf;
++	struct completion cr_write_done;
++	struct completion timer_base_lock;
++	struct completion avi_pkt_rcv;
++	enum hdmirx_pix_fmt pix_fmt;
++	void __iomem *regs;
++	int hdmi_irq;
++	int dma_irq;
++	int det_irq;
++	bool hpd_trigger_level;
++	bool tmds_clk_ratio;
++	bool is_dvi_mode;
++	bool got_timing;
++	u32 num_clks;
++	u32 edid_blocks_written;
++	u32 cur_vic;
++	u32 cur_fmt_fourcc;
++	u32 color_depth;
++	u8 edid[EDID_BLOCK_SIZE * 2];
++	hdmi_codec_plugged_cb plugged_cb;
++	spinlock_t rst_lock; /* to lock register access */
++};
++
++static u8 edid_init_data_340M[] = {
++	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
++	0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00,
++	0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78,
++	0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23,
++	0x09, 0x48, 0x4C, 0x21, 0x08, 0x00, 0x61, 0x40,
++	0x01, 0x01, 0x81, 0x00, 0x95, 0x00, 0xA9, 0xC0,
++	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
++	0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
++	0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E,
++	0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
++	0x6E, 0x28, 0x55, 0x00, 0x20, 0xC2, 0x31, 0x00,
++	0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52,
++	0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20,
++	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
++	0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
++	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xA7,
++
++	0x02, 0x03, 0x2F, 0xD1, 0x51, 0x07, 0x16, 0x14,
++	0x05, 0x01, 0x03, 0x12, 0x13, 0x84, 0x22, 0x1F,
++	0x90, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x23, 0x09,
++	0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03,
++	0x0C, 0x00, 0x30, 0x00, 0x10, 0x44, 0xE3, 0x05,
++	0x03, 0x01, 0xE4, 0x0F, 0x00, 0x80, 0x01, 0x02,
++	0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58,
++	0x2C, 0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00,
++	0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F,
++};
++
++static const struct v4l2_dv_timings cea640x480 = V4L2_DV_BT_CEA_640X480P59_94;
++
++static const struct v4l2_dv_timings_cap hdmirx_timings_cap = {
++	.type = V4L2_DV_BT_656_1120,
++	.reserved = { 0 },
++	V4L2_INIT_BT_TIMINGS(640, 4096,			/* min/max width */
++			     480, 2160,			/* min/max height */
++			     20000000, 600000000,	/* min/max pixelclock */
++			     /* standards */
++			     V4L2_DV_BT_STD_CEA861,
++			     /* capabilities */
++			     V4L2_DV_BT_CAP_PROGRESSIVE |
++			     V4L2_DV_BT_CAP_INTERLACED)
++};
++
++static void hdmirx_writel(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val)
++{
++	unsigned long lock_flags = 0;
++
++	spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
++	writel(val, hdmirx_dev->regs + reg);
++	spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
++}
++
++static u32 hdmirx_readl(struct snps_hdmirx_dev *hdmirx_dev, int reg)
++{
++	unsigned long lock_flags = 0;
++	u32 val;
++
++	spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
++	val = readl(hdmirx_dev->regs + reg);
++	spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
++	return val;
++}
++
++static void hdmirx_reset_dma(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	unsigned long lock_flags = 0;
++
++	spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
++	reset_control_reset(hdmirx_dev->resets[0].rstc);
++	spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
++}
++
++static void hdmirx_update_bits(struct snps_hdmirx_dev *hdmirx_dev, int reg,
++			       u32 mask, u32 data)
++{
++	unsigned long lock_flags = 0;
++	u32 val;
++
++	spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
++	val = readl(hdmirx_dev->regs + reg) & ~mask;
++	val |= (data & mask);
++	writel(val, hdmirx_dev->regs + reg);
++	spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
++}
++
++static int hdmirx_subscribe_event(struct v4l2_fh *fh,
++				  const struct v4l2_event_subscription *sub)
++{
++	switch (sub->type) {
++	case V4L2_EVENT_SOURCE_CHANGE:
++		if (fh->vdev->vfl_dir == VFL_DIR_RX)
++			return v4l2_src_change_event_subscribe(fh, sub);
++		break;
++	case V4L2_EVENT_CTRL:
++		return v4l2_ctrl_subscribe_event(fh, sub);
++	default:
++		break;
++	}
++
++	return -EINVAL;
++}
++
++static bool tx_5v_power_present(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	bool ret;
++	int val, i, cnt;
++
++	cnt = 0;
++	for (i = 0; i < 10; i++) {
++		usleep_range(1000, 1100);
++		val = gpiod_get_value(hdmirx_dev->detect_5v_gpio);
++		if (val > 0)
++			cnt++;
++		if (cnt >= DETECTION_THRESHOLD)
++			break;
++	}
++
++	ret = (cnt >= DETECTION_THRESHOLD) ? true : false;
++	v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: %d\n", __func__, ret);
++
++	return ret;
++}
++
++static bool signal_not_lock(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	u32 mu_status, dma_st10, cmu_st;
++
++	mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS);
++	dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10);
++	cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS);
++
++	if ((mu_status & TMDSVALID_STABLE_ST) &&
++	    (dma_st10 & HDMIRX_LOCK) &&
++	    (cmu_st & TMDSQPCLK_LOCKED_ST))
++		return false;
++
++	return true;
++}
++
++static void hdmirx_get_colordepth(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 val, color_depth_reg;
++
++	val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
++	color_depth_reg = (val & HDMIRX_COLOR_DEPTH_MASK) >> 3;
++
++	switch (color_depth_reg) {
++	case 0x4:
++		hdmirx_dev->color_depth = 24;
++		break;
++	case 0x5:
++		hdmirx_dev->color_depth = 30;
++		break;
++	case 0x6:
++		hdmirx_dev->color_depth = 36;
++		break;
++	case 0x7:
++		hdmirx_dev->color_depth = 48;
++		break;
++	default:
++		hdmirx_dev->color_depth = 24;
++		break;
++	}
++
++	v4l2_dbg(1, debug, v4l2_dev, "%s: color_depth: %d, reg_val:%d\n",
++		 __func__, hdmirx_dev->color_depth, color_depth_reg);
++}
++
++static void hdmirx_get_pix_fmt(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 val;
++
++	val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
++	hdmirx_dev->pix_fmt = val & HDMIRX_FORMAT_MASK;
++
++	switch (hdmirx_dev->pix_fmt) {
++	case HDMIRX_RGB888:
++		hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
++		break;
++	case HDMIRX_YUV422:
++		hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV16;
++		break;
++	case HDMIRX_YUV444:
++		hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV24;
++		break;
++	case HDMIRX_YUV420:
++		hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV12;
++		break;
++	default:
++		v4l2_err(v4l2_dev,
++			 "%s: err pix_fmt: %d, set RGB888 as default\n",
++			 __func__, hdmirx_dev->pix_fmt);
++		hdmirx_dev->pix_fmt = HDMIRX_RGB888;
++		hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
++		break;
++	}
++
++	v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s\n", __func__,
++		 pix_fmt_str[hdmirx_dev->pix_fmt]);
++}
++
++static void hdmirx_get_timings(struct snps_hdmirx_dev *hdmirx_dev,
++			       struct v4l2_bt_timings *bt, bool from_dma)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 hact, vact, htotal, vtotal, fps;
++	u32 hfp, hs, hbp, vfp, vs, vbp;
++	u32 val;
++
++	if (from_dma) {
++		val = hdmirx_readl(hdmirx_dev, DMA_STATUS2);
++		hact = (val >> 16) & 0xffff;
++		vact = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, DMA_STATUS3);
++		htotal = (val >> 16) & 0xffff;
++		vtotal = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, DMA_STATUS4);
++		hs = (val >> 16) & 0xffff;
++		vs = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, DMA_STATUS5);
++		hbp = (val >> 16) & 0xffff;
++		vbp = val & 0xffff;
++		hfp = htotal - hact - hs - hbp;
++		vfp = vtotal - vact - vs - vbp;
++	} else {
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS1);
++		hs = (val >> 16) & 0xffff;
++		hfp = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS2);
++		hbp = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS3);
++		htotal = (val >> 16) & 0xffff;
++		hact = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS4);
++		vs = (val >> 16) & 0xffff;
++		vfp = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS5);
++		vbp = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS6);
++		vtotal = (val >> 16) & 0xffff;
++		vact = val & 0xffff;
++		if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
++			hact *= 2;
++	}
++	if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
++		htotal *= 2;
++	fps = (bt->pixelclock + (htotal * vtotal) / 2) / (htotal * vtotal);
++	if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
++		fps *= 2;
++	bt->width = hact;
++	bt->height = vact;
++	bt->hfrontporch = hfp;
++	bt->hsync = hs;
++	bt->hbackporch = hbp;
++	bt->vfrontporch = vfp;
++	bt->vsync = vs;
++	bt->vbackporch = vbp;
++
++	v4l2_dbg(1, debug, v4l2_dev, "get timings from %s\n", from_dma ? "dma" : "ctrl");
++	v4l2_dbg(1, debug, v4l2_dev, "act:%ux%u, total:%ux%u, fps:%u, pixclk:%llu\n",
++		 bt->width, bt->height, htotal, vtotal, fps, bt->pixelclock);
++
++	v4l2_dbg(2, debug, v4l2_dev, "hfp:%u, hs:%u, hbp:%u, vfp:%u, vs:%u, vbp:%u\n",
++		 bt->hfrontporch, bt->hsync, bt->hbackporch,
++		 bt->vfrontporch, bt->vsync, bt->vbackporch);
++}
++
++static bool hdmirx_check_timing_valid(struct v4l2_bt_timings *bt)
++{
++	if (bt->width < 100 || bt->width > 5000 ||
++	    bt->height < 100 || bt->height > 5000)
++		return false;
++
++	if (!bt->hsync || bt->hsync > 200 ||
++	    !bt->vsync || bt->vsync > 100)
++		return false;
++
++	if (!bt->hbackporch || bt->hbackporch > 2000 ||
++	    !bt->vbackporch || bt->vbackporch > 2000)
++		return false;
++
++	if (!bt->hfrontporch || bt->hfrontporch > 2000 ||
++	    !bt->vfrontporch || bt->vfrontporch > 2000)
++		return false;
++
++	return true;
++}
++
++static void hdmirx_get_avi_infoframe(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	union hdmi_infoframe frame = {};
++	int err, i, b, itr = 0;
++	u8 aviif[3 + 7 * 4];
++	u32 val;
++
++	aviif[itr++] = HDMI_INFOFRAME_TYPE_AVI;
++	val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1);
++	aviif[itr++] = val & 0xff;
++	aviif[itr++] = (val >> 8) & 0xff;
++
++	for (i = 0; i < 7; i++) {
++		val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB3_0 + 4 * i);
++
++		for (b = 0; b < 4; b++)
++			aviif[itr++] = (val >> (8 * b)) & 0xff;
++	}
++
++	err = hdmi_infoframe_unpack(&frame, aviif, sizeof(aviif));
++	if (err) {
++		v4l2_err(v4l2_dev, "failed to unpack AVI infoframe\n");
++		return;
++	}
++
++	v4l2_ctrl_s_ctrl(hdmirx_dev->rgb_range, frame.avi.quantization_range);
++}
++
++/*
++ * When querying DV timings during preview, if the DMA's timing is stable,
++ * we retrieve the timings directly from the DMA. However, if the current
++ * resolution is negative, obtaining the timing from CTRL may require a
++ * change in the sync polarity, potentially leading to DMA errors.
++ */
++static int hdmirx_get_detected_timings(struct snps_hdmirx_dev *hdmirx_dev,
++				       struct v4l2_dv_timings *timings,
++				       bool from_dma)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct v4l2_bt_timings *bt = &timings->bt;
++	u32 field_type, color_depth, deframer_st;
++	u32 val, tmdsqpclk_freq, pix_clk;
++	u64 tmp_data, tmds_clk;
++
++	memset(timings, 0, sizeof(struct v4l2_dv_timings));
++	timings->type = V4L2_DV_BT_656_1120;
++
++	val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
++	field_type = (val & HDMIRX_TYPE_MASK) >> 7;
++	hdmirx_get_pix_fmt(hdmirx_dev);
++	bt->interlaced = field_type & BIT(0) ? V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
++	val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB7_4);
++	hdmirx_dev->cur_vic =  val | VIC_VAL_MASK;
++	hdmirx_get_colordepth(hdmirx_dev);
++	color_depth = hdmirx_dev->color_depth;
++	deframer_st = hdmirx_readl(hdmirx_dev, DEFRAMER_STATUS);
++	hdmirx_dev->is_dvi_mode = deframer_st & OPMODE_STS_MASK ? false : true;
++	tmdsqpclk_freq = hdmirx_readl(hdmirx_dev, CMU_TMDSQPCLK_FREQ);
++	tmds_clk = tmdsqpclk_freq * 4 * 1000;
++	tmp_data = tmds_clk * 24;
++	do_div(tmp_data, color_depth);
++	pix_clk = tmp_data;
++	bt->pixelclock = pix_clk;
++
++	hdmirx_get_avi_infoframe(hdmirx_dev);
++
++	hdmirx_get_timings(hdmirx_dev, bt, from_dma);
++	if (bt->interlaced == V4L2_DV_INTERLACED) {
++		bt->height *= 2;
++		bt->il_vsync = bt->vsync + 1;
++	}
++
++	v4l2_dbg(2, debug, v4l2_dev, "tmds_clk:%llu\n", tmds_clk);
++	v4l2_dbg(1, debug, v4l2_dev, "interlace:%d, fmt:%d, vic:%d, color:%d, mode:%s\n",
++		 bt->interlaced, hdmirx_dev->pix_fmt,
++		 hdmirx_dev->cur_vic, hdmirx_dev->color_depth,
++		 hdmirx_dev->is_dvi_mode ? "dvi" : "hdmi");
++	v4l2_dbg(2, debug, v4l2_dev, "deframer_st:%#x\n", deframer_st);
++
++	if (!hdmirx_check_timing_valid(bt))
++		return -EINVAL;
++
++	return 0;
++}
++
++static bool port_no_link(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	return !tx_5v_power_present(hdmirx_dev);
++}
++
++static int hdmirx_query_dv_timings(struct file *file, void *_fh,
++				   struct v4l2_dv_timings *timings)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	int ret;
++
++	if (port_no_link(hdmirx_dev)) {
++		v4l2_err(v4l2_dev, "%s: port has no link\n", __func__);
++		return -ENOLINK;
++	}
++
++	if (signal_not_lock(hdmirx_dev)) {
++		v4l2_err(v4l2_dev, "%s: signal is not locked\n", __func__);
++		return -ENOLCK;
++	}
++
++	ret = hdmirx_get_detected_timings(hdmirx_dev, timings, true);
++	if (ret)
++		return ret;
++
++	if (debug)
++		v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name,
++				      "query_dv_timings: ", timings, false);
++
++	if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) {
++		v4l2_dbg(1, debug, v4l2_dev, "%s: timings out of range\n", __func__);
++		return -ERANGE;
++	}
++
++	return 0;
++}
++
++static void hdmirx_hpd_ctrl(struct snps_hdmirx_dev *hdmirx_dev, bool en)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	v4l2_dbg(1, debug, v4l2_dev, "%s: %sable, hpd_trigger_level:%d\n",
++		 __func__, en ? "en" : "dis",
++		 hdmirx_dev->hpd_trigger_level);
++	hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, HPDLOW, en ? 0 : HPDLOW);
++	en = hdmirx_dev->hpd_trigger_level ? en : !en;
++	hdmirx_writel(hdmirx_dev, CORE_CONFIG, en);
++}
++
++static int hdmirx_write_edid(struct snps_hdmirx_dev *hdmirx_dev,
++			     struct v4l2_edid *edid, bool hpd_up)
++{
++	u32 edid_len = edid->blocks * EDID_BLOCK_SIZE;
++	char data[300];
++	u32 i;
++
++	memset(edid->reserved, 0, sizeof(edid->reserved));
++	if (edid->pad)
++		return -EINVAL;
++
++	if (edid->start_block)
++		return -EINVAL;
++
++	if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
++		edid->blocks = EDID_NUM_BLOCKS_MAX;
++		return -E2BIG;
++	}
++
++	if (!edid->blocks) {
++		hdmirx_dev->edid_blocks_written = 0;
++		return 0;
++	}
++
++	cec_s_phys_addr_from_edid(hdmirx_dev->cec->adap,
++				  (const struct edid *)edid->edid);
++
++	memset(&hdmirx_dev->edid, 0, sizeof(hdmirx_dev->edid));
++	hdmirx_hpd_ctrl(hdmirx_dev, false);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
++			   EDID_READ_EN_MASK |
++			   EDID_WRITE_EN_MASK |
++			   EDID_SLAVE_ADDR_MASK,
++			   EDID_READ_EN(0) |
++			   EDID_WRITE_EN(1) |
++			   EDID_SLAVE_ADDR(0x50));
++	for (i = 0; i < edid_len; i++)
++		hdmirx_writel(hdmirx_dev, DMA_CONFIG10, edid->edid[i]);
++
++	/* read out for debug */
++	if (debug >= 2) {
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
++				   EDID_READ_EN_MASK |
++				   EDID_WRITE_EN_MASK,
++				   EDID_READ_EN(1) |
++				   EDID_WRITE_EN(0));
++		edid_len = edid_len > sizeof(data) ? sizeof(data) : edid_len;
++		memset(data, 0, sizeof(data));
++		for (i = 0; i < edid_len; i++)
++			data[i] = hdmirx_readl(hdmirx_dev, DMA_STATUS14);
++
++		print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, data,
++			       edid_len, false);
++	}
++
++	/*
++	 * You must set EDID_READ_EN & EDID_WRITE_EN bit to 0,
++	 * when the read/write edid operation is completed.Otherwise, it
++	 * will affect the reading and writing of other registers
++	 */
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
++			   EDID_READ_EN_MASK | EDID_WRITE_EN_MASK,
++			   EDID_READ_EN(0) | EDID_WRITE_EN(0));
++
++	hdmirx_dev->edid_blocks_written = edid->blocks;
++	memcpy(&hdmirx_dev->edid, edid->edid, edid->blocks * EDID_BLOCK_SIZE);
++	if (hpd_up) {
++		if (tx_5v_power_present(hdmirx_dev)) {
++			/* Add 100ms delay after updating the EDID as per HDMI specs */
++			msleep(100);
++			hdmirx_hpd_ctrl(hdmirx_dev, true);
++		}
++	}
++
++	return 0;
++}
++
++/*
++ * Before clearing interrupt, we need to read the interrupt status.
++ */
++static inline void hdmirx_clear_interrupt(struct snps_hdmirx_dev *hdmirx_dev,
++					  u32 reg, u32 val)
++{
++	/* (interrupt status register) = (interrupt clear register) - 0x8 */
++	hdmirx_readl(hdmirx_dev, reg - 0x8);
++	hdmirx_writel(hdmirx_dev, reg, val);
++}
++
++static void hdmirx_interrupts_setup(struct snps_hdmirx_dev *hdmirx_dev, bool en)
++{
++	v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: %sable\n",
++		 __func__, en ? "en" : "dis");
++
++	/* Note: In DVI mode, it needs to be written twice to take effect. */
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff);
++
++	if (en) {
++		hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N,
++				   TMDSQPCLK_OFF_CHG | TMDSQPCLK_LOCKED_CHG,
++				   TMDSQPCLK_OFF_CHG | TMDSQPCLK_LOCKED_CHG);
++		hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
++				   TMDSVALID_STABLE_CHG, TMDSVALID_STABLE_CHG);
++		hdmirx_update_bits(hdmirx_dev, AVPUNIT_0_INT_MASK_N,
++				   CED_DYN_CNT_CH2_IRQ |
++				   CED_DYN_CNT_CH1_IRQ |
++				   CED_DYN_CNT_CH0_IRQ,
++				   CED_DYN_CNT_CH2_IRQ |
++				   CED_DYN_CNT_CH1_IRQ |
++				   CED_DYN_CNT_CH0_IRQ);
++	} else {
++		hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0);
++		hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0);
++		hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0);
++	}
++}
++
++static void hdmirx_plugout(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct arm_smccc_res res;
++
++	hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, 0);
++	hdmirx_interrupts_setup(hdmirx_dev, false);
++	hdmirx_hpd_ctrl(hdmirx_dev, false);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
++			   LINE_FLAG_INT_EN |
++			   HDMIRX_DMA_IDLE_INT |
++			   HDMIRX_LOCK_DISABLE_INT |
++			   LAST_FRAME_AXI_UNFINISH_INT_EN |
++			   FIFO_OVERFLOW_INT_EN |
++			   FIFO_UNDERFLOW_INT_EN |
++			   HDMIRX_AXI_ERROR_INT_EN, 0);
++	hdmirx_reset_dma(hdmirx_dev);
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE | PHY_RESET |
++			   PHY_PDDQ, HDMI_DISABLE);
++	hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x0);
++	cancel_delayed_work(&hdmirx_dev->delayed_work_res_change);
++	cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat);
++	flush_work(&hdmirx_dev->work_wdt_config);
++	arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res);
++}
++
++static int hdmirx_set_edid(struct file *file, void *fh, struct v4l2_edid *edid)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct arm_smccc_res res;
++	int ret;
++
++	disable_irq(hdmirx_dev->hdmi_irq);
++	disable_irq(hdmirx_dev->dma_irq);
++	arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_DIS,
++		      RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res);
++
++	if (tx_5v_power_present(hdmirx_dev))
++		hdmirx_plugout(hdmirx_dev);
++	ret = hdmirx_write_edid(hdmirx_dev, edid, false);
++	if (ret)
++		return ret;
++
++	enable_irq(hdmirx_dev->hdmi_irq);
++	enable_irq(hdmirx_dev->dma_irq);
++	arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN,
++		      RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res);
++	queue_delayed_work(system_unbound_wq,
++			   &hdmirx_dev->delayed_work_hotplug,
++			   msecs_to_jiffies(500));
++	return 0;
++}
++
++static int hdmirx_get_edid(struct file *file, void *fh, struct v4l2_edid *edid)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	memset(edid->reserved, 0, sizeof(edid->reserved));
++
++	if (edid->pad)
++		return -EINVAL;
++
++	if (!edid->start_block && !edid->blocks) {
++		edid->blocks = hdmirx_dev->edid_blocks_written;
++		return 0;
++	}
++
++	if (!hdmirx_dev->edid_blocks_written)
++		return -ENODATA;
++
++	if (edid->start_block >= hdmirx_dev->edid_blocks_written || !edid->blocks)
++		return -EINVAL;
++
++	if (edid->start_block + edid->blocks > hdmirx_dev->edid_blocks_written)
++		edid->blocks = hdmirx_dev->edid_blocks_written - edid->start_block;
++
++	memcpy(edid->edid, &hdmirx_dev->edid, edid->blocks * EDID_BLOCK_SIZE);
++
++	v4l2_dbg(1, debug, v4l2_dev, "%s: read EDID:\n", __func__);
++	if (debug > 0)
++		print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1,
++			       edid->edid, edid->blocks * EDID_BLOCK_SIZE, false);
++
++	return 0;
++}
++
++static int hdmirx_g_parm(struct file *file, void *priv,
++			 struct v4l2_streamparm *parm)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_fract fps;
++
++	if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
++		return -EINVAL;
++
++	fps = v4l2_calc_timeperframe(&hdmirx_dev->timings);
++	parm->parm.capture.timeperframe.numerator = fps.numerator;
++	parm->parm.capture.timeperframe.denominator = fps.denominator;
++
++	return 0;
++}
++
++static int hdmirx_dv_timings_cap(struct file *file, void *fh,
++				 struct v4l2_dv_timings_cap *cap)
++{
++	*cap = hdmirx_timings_cap;
++	return 0;
++}
++
++static int hdmirx_enum_dv_timings(struct file *file, void *_fh,
++				  struct v4l2_enum_dv_timings *timings)
++{
++	return v4l2_enum_dv_timings_cap(timings, &hdmirx_timings_cap, NULL, NULL);
++}
++
++static void hdmirx_scdc_init(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	hdmirx_update_bits(hdmirx_dev, I2C_SLAVE_CONFIG1,
++			   I2C_SDA_OUT_HOLD_VALUE_QST_MASK |
++			   I2C_SDA_IN_HOLD_VALUE_QST_MASK,
++			   I2C_SDA_OUT_HOLD_VALUE_QST(0x80) |
++			   I2C_SDA_IN_HOLD_VALUE_QST(0x15));
++	hdmirx_update_bits(hdmirx_dev, SCDC_REGBANK_CONFIG0,
++			   SCDC_SINKVERSION_QST_MASK,
++			   SCDC_SINKVERSION_QST(1));
++}
++
++static int wait_reg_bit_status(struct snps_hdmirx_dev *hdmirx_dev, u32 reg,
++			       u32 bit_mask, u32 expect_val, bool is_grf,
++			       u32 ms)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 i, val;
++
++	for (i = 0; i < ms; i++) {
++		if (is_grf)
++			regmap_read(hdmirx_dev->grf, reg, &val);
++		else
++			val = hdmirx_readl(hdmirx_dev, reg);
++
++		if ((val & bit_mask) == expect_val) {
++			v4l2_dbg(2, debug, v4l2_dev,
++				 "%s:  i:%d, time: %dms\n", __func__, i, ms);
++			break;
++		}
++		usleep_range(1000, 1010);
++	}
++
++	if (i == ms)
++		return -1;
++
++	return 0;
++}
++
++static int hdmirx_phy_register_write(struct snps_hdmirx_dev *hdmirx_dev,
++				     u32 phy_reg, u32 val)
++{
++	struct device *dev = hdmirx_dev->dev;
++
++	reinit_completion(&hdmirx_dev->cr_write_done);
++	/* clear irq status */
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
++	/* en irq */
++	hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
++			   PHYCREG_CR_WRITE_DONE, PHYCREG_CR_WRITE_DONE);
++	/* write phy reg addr */
++	hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG1, phy_reg);
++	/* write phy reg val */
++	hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG2, val);
++	/* config write enable */
++	hdmirx_writel(hdmirx_dev, PHYCREG_CONTROL, PHYCREG_CR_PARA_WRITE_P);
++
++	if (!wait_for_completion_timeout(&hdmirx_dev->cr_write_done,
++					 msecs_to_jiffies(20))) {
++		dev_err(dev, "%s wait cr write done failed\n", __func__);
++		return -1;
++	}
++
++	return 0;
++}
++
++static void hdmirx_tmds_clk_ratio_config(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 val;
++
++	val = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS1);
++	v4l2_dbg(3, debug, v4l2_dev, "%s: scdc_regbank_st:%#x\n", __func__, val);
++	hdmirx_dev->tmds_clk_ratio = (val & SCDC_TMDSBITCLKRATIO) > 0;
++
++	if (hdmirx_dev->tmds_clk_ratio) {
++		v4l2_dbg(3, debug, v4l2_dev, "%s: HDMITX greater than 3.4Gbps\n", __func__);
++		hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
++				   TMDS_CLOCK_RATIO, TMDS_CLOCK_RATIO);
++	} else {
++		v4l2_dbg(3, debug, v4l2_dev, "%s: HDMITX less than 3.4Gbps\n", __func__);
++		hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
++				   TMDS_CLOCK_RATIO, 0);
++	}
++}
++
++static void hdmirx_phy_config(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct device *dev = hdmirx_dev->dev;
++
++	hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff);
++	hdmirx_update_bits(hdmirx_dev, SCDC_INT_MASK_N, SCDCTMDSCCFG_CHG,
++			   SCDCTMDSCCFG_CHG);
++	/* cr_para_clk 24M */
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, REFFREQ_SEL_MASK, REFFREQ_SEL(0));
++	/* rx data width 40bit valid */
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, RXDATA_WIDTH, RXDATA_WIDTH);
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, PHY_RESET);
++	usleep_range(100, 110);
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, 0);
++	usleep_range(100, 110);
++	/* select cr para interface */
++	hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x3);
++
++	if (wait_reg_bit_status(hdmirx_dev, SYS_GRF_SOC_STATUS1,
++				HDMIRXPHY_SRAM_INIT_DONE,
++				HDMIRXPHY_SRAM_INIT_DONE, true, 10))
++		dev_err(dev, "%s: phy SRAM init failed\n", __func__);
++
++	regmap_write(hdmirx_dev->grf, SYS_GRF_SOC_CON1,
++		     (HDMIRXPHY_SRAM_EXT_LD_DONE << 16) |
++		     HDMIRXPHY_SRAM_EXT_LD_DONE);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 3);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 3);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 1);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
++
++	hdmirx_phy_register_write(hdmirx_dev,
++				  HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG,
++				  CDR_SETTING_BOUNDARY_3_DEFAULT);
++	hdmirx_phy_register_write(hdmirx_dev,
++				  HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG,
++				  CDR_SETTING_BOUNDARY_4_DEFAULT);
++	hdmirx_phy_register_write(hdmirx_dev,
++				  HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG,
++				  CDR_SETTING_BOUNDARY_5_DEFAULT);
++	hdmirx_phy_register_write(hdmirx_dev,
++				  HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG,
++				  CDR_SETTING_BOUNDARY_6_DEFAULT);
++	hdmirx_phy_register_write(hdmirx_dev,
++				  HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG,
++				  CDR_SETTING_BOUNDARY_7_DEFAULT);
++
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_PDDQ, 0);
++	if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, PDDQ_ACK, 0, false, 10))
++		dev_err(dev, "%s: wait pddq ack failed\n", __func__);
++
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE, 0);
++	if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, HDMI_DISABLE_ACK, 0,
++				false, 50))
++		dev_err(dev, "%s: wait hdmi disable ack failed\n", __func__);
++
++	hdmirx_tmds_clk_ratio_config(hdmirx_dev);
++}
++
++static void hdmirx_controller_init(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct device *dev = hdmirx_dev->dev;
++
++	reinit_completion(&hdmirx_dev->timer_base_lock);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
++	/* en irq */
++	hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N,
++			   TIMER_BASE_LOCKED_IRQ, TIMER_BASE_LOCKED_IRQ);
++	/* write irefclk freq */
++	hdmirx_writel(hdmirx_dev, GLOBAL_TIMER_REF_BASE, IREF_CLK_FREQ_HZ);
++
++	if (!wait_for_completion_timeout(&hdmirx_dev->timer_base_lock,
++					 msecs_to_jiffies(20)))
++		dev_err(dev, "%s wait timer base lock failed\n", __func__);
++
++	hdmirx_update_bits(hdmirx_dev, CMU_CONFIG0,
++			   TMDSQPCLK_STABLE_FREQ_MARGIN_MASK |
++			   AUDCLK_STABLE_FREQ_MARGIN_MASK,
++			   TMDSQPCLK_STABLE_FREQ_MARGIN(2) |
++			   AUDCLK_STABLE_FREQ_MARGIN(1));
++	hdmirx_update_bits(hdmirx_dev, DESCRAND_EN_CONTROL,
++			   SCRAMB_EN_SEL_QST_MASK, SCRAMB_EN_SEL_QST(1));
++	hdmirx_update_bits(hdmirx_dev, CED_CONFIG,
++			   CED_VIDDATACHECKEN_QST |
++			   CED_DATAISCHECKEN_QST |
++			   CED_GBCHECKEN_QST |
++			   CED_CTRLCHECKEN_QST |
++			   CED_CHLOCKMAXER_QST_MASK,
++			   CED_VIDDATACHECKEN_QST |
++			   CED_GBCHECKEN_QST |
++			   CED_CTRLCHECKEN_QST |
++			   CED_CHLOCKMAXER_QST(0x10));
++	hdmirx_update_bits(hdmirx_dev, DEFRAMER_CONFIG0,
++			   VS_REMAPFILTER_EN_QST | VS_FILTER_ORDER_QST_MASK,
++			   VS_REMAPFILTER_EN_QST | VS_FILTER_ORDER_QST(0x3));
++}
++
++static void hdmirx_set_negative_pol(struct snps_hdmirx_dev *hdmirx_dev, bool en)
++{
++	if (en) {
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6,
++				   VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN,
++				   VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN);
++		hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2,
++				   VPROC_VSYNC_POL_OVR_VALUE |
++				   VPROC_VSYNC_POL_OVR_EN |
++				   VPROC_HSYNC_POL_OVR_VALUE |
++				   VPROC_HSYNC_POL_OVR_EN,
++				   VPROC_VSYNC_POL_OVR_EN |
++				   VPROC_HSYNC_POL_OVR_EN);
++		return;
++	}
++
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6,
++			   VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN, 0);
++
++	hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2,
++			   VPROC_VSYNC_POL_OVR_VALUE |
++			   VPROC_VSYNC_POL_OVR_EN |
++			   VPROC_HSYNC_POL_OVR_VALUE |
++			   VPROC_HSYNC_POL_OVR_EN, 0);
++}
++
++static int hdmirx_try_to_get_timings(struct snps_hdmirx_dev *hdmirx_dev,
++				     struct v4l2_dv_timings *timings,
++				     int try_cnt)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	int i, cnt = 0, fail_cnt = 0, ret = 0;
++	bool from_dma = false;
++
++	hdmirx_set_negative_pol(hdmirx_dev, false);
++	for (i = 0; i < try_cnt; i++) {
++		ret = hdmirx_get_detected_timings(hdmirx_dev, timings, from_dma);
++		if (ret) {
++			cnt = 0;
++			fail_cnt++;
++			if (fail_cnt > 3) {
++				hdmirx_set_negative_pol(hdmirx_dev, true);
++				from_dma = true;
++			}
++		} else {
++			cnt++;
++		}
++		if (cnt >= 5)
++			break;
++
++		usleep_range(10 * 1000, 10 * 1100);
++	}
++
++	if (try_cnt > 8 && cnt < 5)
++		v4l2_dbg(1, debug, v4l2_dev, "%s: res not stable\n", __func__);
++
++	return ret;
++}
++
++static void hdmirx_format_change(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_dv_timings timings;
++	struct hdmirx_stream *stream = &hdmirx_dev->stream;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	const struct v4l2_event ev_src_chg = {
++		.type = V4L2_EVENT_SOURCE_CHANGE,
++		.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
++	};
++
++	if (hdmirx_try_to_get_timings(hdmirx_dev, &timings, 20)) {
++		queue_delayed_work(system_unbound_wq,
++				   &hdmirx_dev->delayed_work_hotplug,
++				   msecs_to_jiffies(20));
++		return;
++	}
++
++	hdmirx_dev->got_timing = true;
++	v4l2_dbg(1, debug, v4l2_dev, "%s: queue res_chg_event\n", __func__);
++	v4l2_event_queue(&stream->vdev, &ev_src_chg);
++}
++
++static void hdmirx_set_ddr_store_fmt(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	enum ddr_store_fmt store_fmt;
++	u32 dma_cfg1;
++
++	switch (hdmirx_dev->pix_fmt) {
++	case HDMIRX_RGB888:
++		store_fmt = STORE_RGB888;
++		break;
++	case HDMIRX_YUV444:
++		store_fmt = STORE_YUV444_8BIT;
++		break;
++	case HDMIRX_YUV422:
++		store_fmt = STORE_YUV422_8BIT;
++		break;
++	case HDMIRX_YUV420:
++		store_fmt = STORE_YUV420_8BIT;
++		break;
++	default:
++		store_fmt = STORE_RGB888;
++		break;
++	}
++
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG1,
++			   DDR_STORE_FORMAT_MASK, DDR_STORE_FORMAT(store_fmt));
++	dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1);
++	v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n",
++		 __func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1);
++}
++
++static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 mu_status, scdc_status, dma_st10, cmu_st;
++	u32 i;
++
++	for (i = 0; i < 300; i++) {
++		mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS);
++		scdc_status = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS3);
++		dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10);
++		cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS);
++
++		if ((mu_status & TMDSVALID_STABLE_ST) &&
++		    (dma_st10 & HDMIRX_LOCK) &&
++		    (cmu_st & TMDSQPCLK_LOCKED_ST))
++			break;
++
++		if (!tx_5v_power_present(hdmirx_dev)) {
++			v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__);
++			return -1;
++		}
++
++		hdmirx_tmds_clk_ratio_config(hdmirx_dev);
++	}
++
++	if (i == 300) {
++		v4l2_err(v4l2_dev, "%s: signal not lock, tmds_clk_ratio:%d\n",
++			 __func__, hdmirx_dev->tmds_clk_ratio);
++		v4l2_err(v4l2_dev, "%s: mu_st:%#x, scdc_st:%#x, dma_st10:%#x\n",
++			 __func__, mu_status, scdc_status, dma_st10);
++		return -1;
++	}
++
++	v4l2_info(v4l2_dev, "%s: signal lock ok, i:%d\n", __func__, i);
++	hdmirx_writel(hdmirx_dev, GLOBAL_SWRESET_REQUEST, DATAPATH_SWRESETREQ);
++
++	reinit_completion(&hdmirx_dev->avi_pkt_rcv);
++	hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N,
++			   PKTDEC_AVIIF_RCV_IRQ, PKTDEC_AVIIF_RCV_IRQ);
++
++	if (!wait_for_completion_timeout(&hdmirx_dev->avi_pkt_rcv,
++					 msecs_to_jiffies(300))) {
++		v4l2_err(v4l2_dev, "%s wait avi_pkt_rcv failed\n", __func__);
++		hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N,
++				   PKTDEC_AVIIF_RCV_IRQ, 0);
++	}
++
++	usleep_range(50 * 1000, 50 * 1010);
++	hdmirx_format_change(hdmirx_dev);
++
++	return 0;
++}
++
++static void hdmirx_dma_config(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	hdmirx_set_ddr_store_fmt(hdmirx_dev);
++
++	/* Note: uv_swap, rb can not swap, doc err*/
++	if (hdmirx_dev->cur_fmt_fourcc != V4L2_PIX_FMT_NV16)
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, RB_SWAP_EN, RB_SWAP_EN);
++	else
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, RB_SWAP_EN, 0);
++
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG7,
++			   LOCK_FRAME_NUM_MASK,
++			   LOCK_FRAME_NUM(2));
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG1,
++			   UV_WID_MASK | Y_WID_MASK | ABANDON_EN,
++			   UV_WID(1) | Y_WID(2) | ABANDON_EN);
++}
++
++static void hdmirx_submodule_init(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	/* Note: if not config HDCP2_CONFIG, there will be some errors; */
++	hdmirx_update_bits(hdmirx_dev, HDCP2_CONFIG,
++			   HDCP2_SWITCH_OVR_VALUE |
++			   HDCP2_SWITCH_OVR_EN,
++			   HDCP2_SWITCH_OVR_EN);
++	hdmirx_scdc_init(hdmirx_dev);
++	hdmirx_controller_init(hdmirx_dev);
++}
++
++static int hdmirx_enum_input(struct file *file, void *priv,
++			     struct v4l2_input *input)
++{
++	if (input->index > 0)
++		return -EINVAL;
++
++	input->type = V4L2_INPUT_TYPE_CAMERA;
++	input->std = 0;
++	strscpy(input->name, "HDMI IN", sizeof(input->name));
++	input->capabilities = V4L2_IN_CAP_DV_TIMINGS;
++
++	return 0;
++}
++
++static int hdmirx_get_input(struct file *file, void *priv, unsigned int *i)
++{
++	*i = 0;
++	return 0;
++}
++
++static int hdmirx_set_input(struct file *file, void *priv, unsigned int i)
++{
++	if (i)
++		return -EINVAL;
++	return 0;
++}
++
++static void hdmirx_set_fmt(struct hdmirx_stream *stream,
++			   struct v4l2_pix_format_mplane *pixm, bool try)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct v4l2_bt_timings *bt = &hdmirx_dev->timings.bt;
++	const struct v4l2_format_info *finfo;
++	unsigned int imagesize = 0;
++	int i;
++
++	memset(&pixm->plane_fmt[0], 0, sizeof(struct v4l2_plane_pix_format));
++	finfo = v4l2_format_info(pixm->pixelformat);
++	if (!finfo) {
++		finfo = v4l2_format_info(V4L2_PIX_FMT_BGR24);
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "%s: set_fmt:%#x not supported, use def_fmt:%x\n",
++			 __func__, pixm->pixelformat, finfo->format);
++	}
++
++	if (!bt->width || !bt->height)
++		v4l2_dbg(1, debug, v4l2_dev, "%s: invalid resolution:%#xx%#x\n",
++			 __func__, bt->width, bt->height);
++
++	pixm->pixelformat = finfo->format;
++	pixm->width = bt->width;
++	pixm->height = bt->height;
++	pixm->num_planes = finfo->mem_planes;
++	pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
++	pixm->colorspace = V4L2_COLORSPACE_SRGB;
++	pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++
++	if (bt->interlaced == V4L2_DV_INTERLACED)
++		pixm->field = V4L2_FIELD_INTERLACED_TB;
++	else
++		pixm->field = V4L2_FIELD_NONE;
++
++	memset(pixm->reserved, 0, sizeof(pixm->reserved));
++
++	v4l2_fill_pixfmt_mp(pixm, finfo->format, pixm->width, pixm->height);
++
++	for (i = 0; i < pixm->num_planes; i++) {
++		struct v4l2_plane_pix_format *plane_fmt;
++		int width, height, bpl, size, bpp = 0;
++
++		if (!i) {
++			width = pixm->width;
++			height = pixm->height;
++		} else {
++			width = pixm->width / finfo->hdiv;
++			height = pixm->height / finfo->vdiv;
++		}
++
++		switch (finfo->format) {
++		case V4L2_PIX_FMT_NV24:
++		case V4L2_PIX_FMT_NV16:
++		case V4L2_PIX_FMT_NV12:
++		case V4L2_PIX_FMT_BGR24:
++			bpp = finfo->bpp[i];
++			break;
++		default:
++			v4l2_dbg(1, debug, v4l2_dev,
++				 "fourcc: %#x is not supported\n",
++				 finfo->format);
++			break;
++		}
++
++		bpl = ALIGN(width * bpp, MEMORY_ALIGN_ROUND_UP_BYTES);
++		size = bpl * height;
++		imagesize += size;
++
++		if (finfo->mem_planes > i) {
++			/* Set bpl and size for each mplane */
++			plane_fmt = pixm->plane_fmt + i;
++			plane_fmt->bytesperline = bpl;
++			plane_fmt->sizeimage = size;
++		}
++
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "C-Plane %i size: %d, Total imagesize: %d\n",
++			 i, size, imagesize);
++	}
++
++	/* Convert to non-MPLANE format as we want to unify non-MPLANE and MPLANE */
++	if (finfo->mem_planes == 1)
++		pixm->plane_fmt[0].sizeimage = imagesize;
++
++	if (!try) {
++		stream->out_finfo = finfo;
++		stream->pixm = *pixm;
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "%s: req(%d, %d), out(%d, %d), fmt:%#x\n", __func__,
++			 pixm->width, pixm->height, stream->pixm.width,
++			 stream->pixm.height, finfo->format);
++	}
++}
++
++static int hdmirx_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
++					  struct v4l2_fmtdesc *f)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++
++	if (f->index >= 1)
++		return -EINVAL;
++
++	f->pixelformat = hdmirx_dev->cur_fmt_fourcc;
++
++	return 0;
++}
++
++static int hdmirx_s_fmt_vid_cap_mplane(struct file *file,
++				       void *priv, struct v4l2_format *f)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	if (vb2_is_busy(&stream->buf_queue)) {
++		v4l2_err(v4l2_dev, "%s: queue busy\n", __func__);
++		return -EBUSY;
++	}
++
++	hdmirx_set_fmt(stream, &f->fmt.pix_mp, false);
++
++	return 0;
++}
++
++static int hdmirx_g_fmt_vid_cap_mplane(struct file *file, void *fh,
++				       struct v4l2_format *f)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_pix_format_mplane pixm = {};
++
++	pixm.pixelformat = hdmirx_dev->cur_fmt_fourcc;
++	hdmirx_set_fmt(stream, &pixm, true);
++	f->fmt.pix_mp = pixm;
++
++	return 0;
++}
++
++static int hdmirx_g_dv_timings(struct file *file, void *_fh,
++			       struct v4l2_dv_timings *timings)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 dma_cfg1;
++
++	*timings = hdmirx_dev->timings;
++	dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1);
++	v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n",
++		 __func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1);
++
++	return 0;
++}
++
++static int hdmirx_s_dv_timings(struct file *file, void *_fh,
++			       struct v4l2_dv_timings *timings)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	if (!timings)
++		return -EINVAL;
++
++	if (debug)
++		v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name,
++				      "s_dv_timings: ", timings, false);
++
++	if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) {
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "%s: timings out of range\n", __func__);
++		return -ERANGE;
++	}
++
++	/* Check if the timings are part of the CEA-861 timings. */
++	v4l2_find_dv_timings_cap(timings, &hdmirx_timings_cap, 0, NULL, NULL);
++
++	if (v4l2_match_dv_timings(&hdmirx_dev->timings, timings, 0, false)) {
++		v4l2_dbg(1, debug, v4l2_dev, "%s: no change\n", __func__);
++		return 0;
++	}
++
++	/*
++	 * Changing the timings implies a format change, which is not allowed
++	 * while buffers for use with streaming have already been allocated.
++	 */
++	if (vb2_is_busy(&stream->buf_queue))
++		return -EBUSY;
++
++	hdmirx_dev->timings = *timings;
++	/* Update the internal format */
++	hdmirx_set_fmt(stream, &stream->pixm, false);
++
++	return 0;
++}
++
++static int hdmirx_querycap(struct file *file, void *priv,
++			   struct v4l2_capability *cap)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct device *dev = stream->hdmirx_dev->dev;
++
++	strscpy(cap->driver, dev->driver->name, sizeof(cap->driver));
++	strscpy(cap->card, dev->driver->name, sizeof(cap->card));
++
++	return 0;
++}
++
++static int hdmirx_queue_setup(struct vb2_queue *queue,
++			      unsigned int *num_buffers,
++			      unsigned int *num_planes,
++			      unsigned int sizes[],
++			      struct device *alloc_ctxs[])
++{
++	struct hdmirx_stream *stream = vb2_get_drv_priv(queue);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	const struct v4l2_pix_format_mplane *pixm = NULL;
++	const struct v4l2_format_info *out_finfo;
++	u32 i, height;
++
++	pixm = &stream->pixm;
++	out_finfo = stream->out_finfo;
++
++	if (!num_planes || !out_finfo) {
++		v4l2_err(v4l2_dev, "%s: out_fmt not set\n", __func__);
++		return -EINVAL;
++	}
++
++	if (*num_planes) {
++		if (*num_planes != pixm->num_planes)
++			return -EINVAL;
++
++		for (i = 0; i < *num_planes; i++)
++			if (sizes[i] < pixm->plane_fmt[i].sizeimage)
++				return -EINVAL;
++		return 0;
++	}
++
++	*num_planes = out_finfo->mem_planes;
++	height = pixm->height;
++
++	for (i = 0; i < out_finfo->mem_planes; i++)
++		sizes[i] = pixm->plane_fmt[i].sizeimage;
++
++	v4l2_dbg(1, debug, v4l2_dev, "%s: count %d, size %d\n",
++		 v4l2_type_names[queue->type], *num_buffers, sizes[0]);
++
++	return 0;
++}
++
++/*
++ * The vb2_buffer are stored in hdmirx_buffer, in order to unify
++ * mplane buffer and none-mplane buffer.
++ */
++static void hdmirx_buf_queue(struct vb2_buffer *vb)
++{
++	const struct v4l2_format_info *out_finfo;
++	struct vb2_v4l2_buffer *vbuf;
++	struct hdmirx_buffer *hdmirx_buf;
++	struct vb2_queue *queue;
++	struct hdmirx_stream *stream;
++	const struct v4l2_pix_format_mplane *pixm;
++	unsigned long lock_flags = 0;
++	int i;
++
++	vbuf = to_vb2_v4l2_buffer(vb);
++	hdmirx_buf = container_of(vbuf, struct hdmirx_buffer, vb);
++	queue = vb->vb2_queue;
++	stream = vb2_get_drv_priv(queue);
++	pixm = &stream->pixm;
++	out_finfo = stream->out_finfo;
++
++	memset(hdmirx_buf->buff_addr, 0, sizeof(hdmirx_buf->buff_addr));
++
++	/*
++	 * If mplanes > 1, every c-plane has its own m-plane,
++	 * otherwise, multiple c-planes are in the same m-plane
++	 */
++	for (i = 0; i < out_finfo->mem_planes; i++)
++		hdmirx_buf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
++
++	if (out_finfo->mem_planes == 1) {
++		if (out_finfo->comp_planes == 1) {
++			hdmirx_buf->buff_addr[HDMIRX_PLANE_CBCR] =
++				hdmirx_buf->buff_addr[HDMIRX_PLANE_Y];
++		} else {
++			for (i = 0; i < out_finfo->comp_planes - 1; i++)
++				hdmirx_buf->buff_addr[i + 1] =
++					hdmirx_buf->buff_addr[i] +
++					pixm->plane_fmt[i].bytesperline *
++					pixm->height;
++		}
++	}
++
++	spin_lock_irqsave(&stream->vbq_lock, lock_flags);
++	list_add_tail(&hdmirx_buf->queue, &stream->buf_head);
++	spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
++}
++
++static void return_all_buffers(struct hdmirx_stream *stream,
++			       enum vb2_buffer_state state)
++{
++	struct hdmirx_buffer *buf;
++	unsigned long flags;
++
++	spin_lock_irqsave(&stream->vbq_lock, flags);
++	if (stream->curr_buf)
++		list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
++	if (stream->next_buf && stream->next_buf != stream->curr_buf)
++		list_add_tail(&stream->next_buf->queue, &stream->buf_head);
++	stream->curr_buf = NULL;
++	stream->next_buf = NULL;
++
++	while (!list_empty(&stream->buf_head)) {
++		buf = list_first_entry(&stream->buf_head,
++				       struct hdmirx_buffer, queue);
++		list_del(&buf->queue);
++		spin_unlock_irqrestore(&stream->vbq_lock, flags);
++		vb2_buffer_done(&buf->vb.vb2_buf, state);
++		spin_lock_irqsave(&stream->vbq_lock, flags);
++	}
++	spin_unlock_irqrestore(&stream->vbq_lock, flags);
++}
++
++static void hdmirx_stop_streaming(struct vb2_queue *queue)
++{
++	struct hdmirx_stream *stream = vb2_get_drv_priv(queue);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	int ret;
++
++	v4l2_info(v4l2_dev, "stream start stopping\n");
++	mutex_lock(&hdmirx_dev->stream_lock);
++	WRITE_ONCE(stream->stopping, true);
++
++	/* wait last irq to return the buffer */
++	ret = wait_event_timeout(stream->wq_stopped, !stream->stopping,
++				 msecs_to_jiffies(500));
++	if (!ret) {
++		v4l2_err(v4l2_dev, "%s: timeout waiting last irq\n",
++			 __func__);
++		WRITE_ONCE(stream->stopping, false);
++	}
++
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
++	return_all_buffers(stream, VB2_BUF_STATE_ERROR);
++	mutex_unlock(&hdmirx_dev->stream_lock);
++	v4l2_info(v4l2_dev, "stream stopping finished\n");
++}
++
++static int hdmirx_start_streaming(struct vb2_queue *queue, unsigned int count)
++{
++	struct hdmirx_stream *stream = vb2_get_drv_priv(queue);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct v4l2_dv_timings timings = hdmirx_dev->timings;
++	struct v4l2_bt_timings *bt = &timings.bt;
++	unsigned long lock_flags = 0;
++	int line_flag;
++
++	if (!hdmirx_dev->got_timing) {
++		v4l2_dbg(1, debug, v4l2_dev, "timing is invalid\n");
++		return 0;
++	}
++
++	mutex_lock(&hdmirx_dev->stream_lock);
++	stream->frame_idx = 0;
++	stream->line_flag_int_cnt = 0;
++	stream->curr_buf = NULL;
++	stream->next_buf = NULL;
++	stream->irq_stat = 0;
++	queue->min_queued_buffers = 1;
++
++	WRITE_ONCE(stream->stopping, false);
++
++	spin_lock_irqsave(&stream->vbq_lock, lock_flags);
++	if (!stream->curr_buf) {
++		if (!list_empty(&stream->buf_head)) {
++			stream->curr_buf = list_first_entry(&stream->buf_head,
++							    struct hdmirx_buffer,
++							    queue);
++			list_del(&stream->curr_buf->queue);
++		} else {
++			stream->curr_buf = NULL;
++		}
++	}
++	spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
++
++	v4l2_dbg(2, debug, v4l2_dev,
++		 "%s: start_stream cur_buf y_addr:%#x, uv_addr:%#x\n",
++		 __func__, stream->curr_buf->buff_addr[HDMIRX_PLANE_Y],
++		 stream->curr_buf->buff_addr[HDMIRX_PLANE_CBCR]);
++	hdmirx_writel(hdmirx_dev, DMA_CONFIG2,
++		      stream->curr_buf->buff_addr[HDMIRX_PLANE_Y]);
++	hdmirx_writel(hdmirx_dev, DMA_CONFIG3,
++		      stream->curr_buf->buff_addr[HDMIRX_PLANE_CBCR]);
++
++	if (bt->height) {
++		if (bt->interlaced == V4L2_DV_INTERLACED)
++			line_flag = bt->height / 4;
++		else
++			line_flag = bt->height / 2;
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG7,
++				   LINE_FLAG_NUM_MASK,
++				   LINE_FLAG_NUM(line_flag));
++	} else {
++		v4l2_err(v4l2_dev, "height err: %d\n", bt->height);
++	}
++
++	hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
++	hdmirx_writel(hdmirx_dev, CED_DYN_CONTROL, 0x1);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
++			   LINE_FLAG_INT_EN |
++			   HDMIRX_DMA_IDLE_INT |
++			   HDMIRX_LOCK_DISABLE_INT |
++			   LAST_FRAME_AXI_UNFINISH_INT_EN |
++			   FIFO_OVERFLOW_INT_EN |
++			   FIFO_UNDERFLOW_INT_EN |
++			   HDMIRX_AXI_ERROR_INT_EN,
++			   LINE_FLAG_INT_EN |
++			   HDMIRX_DMA_IDLE_INT |
++			   HDMIRX_LOCK_DISABLE_INT |
++			   LAST_FRAME_AXI_UNFINISH_INT_EN |
++			   FIFO_OVERFLOW_INT_EN |
++			   FIFO_UNDERFLOW_INT_EN |
++			   HDMIRX_AXI_ERROR_INT_EN);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, HDMIRX_DMA_EN);
++	v4l2_dbg(1, debug, v4l2_dev, "%s: enable dma", __func__);
++	mutex_unlock(&hdmirx_dev->stream_lock);
++
++	return 0;
++}
++
++/* vb2 queue */
++static const struct vb2_ops hdmirx_vb2_ops = {
++	.queue_setup = hdmirx_queue_setup,
++	.buf_queue = hdmirx_buf_queue,
++	.wait_prepare = vb2_ops_wait_prepare,
++	.wait_finish = vb2_ops_wait_finish,
++	.stop_streaming = hdmirx_stop_streaming,
++	.start_streaming = hdmirx_start_streaming,
++};
++
++static int hdmirx_init_vb2_queue(struct vb2_queue *q,
++				 struct hdmirx_stream *stream,
++				 enum v4l2_buf_type buf_type)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++
++	q->type = buf_type;
++	q->io_modes = VB2_MMAP | VB2_DMABUF;
++	q->drv_priv = stream;
++	q->ops = &hdmirx_vb2_ops;
++	q->mem_ops = &vb2_dma_contig_memops;
++	q->buf_struct_size = sizeof(struct hdmirx_buffer);
++	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++	q->lock = &stream->vlock;
++	q->dev = hdmirx_dev->dev;
++	/*
++	 * rk3588 doesn't use iommu and works only with dma buffers
++	 * that are physically contiguous in memory.
++	 */
++	q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
++	return vb2_queue_init(q);
++}
++
++/* video device */
++static const struct v4l2_ioctl_ops hdmirx_v4l2_ioctl_ops = {
++	.vidioc_querycap = hdmirx_querycap,
++	.vidioc_try_fmt_vid_cap_mplane = hdmirx_g_fmt_vid_cap_mplane,
++	.vidioc_s_fmt_vid_cap_mplane = hdmirx_s_fmt_vid_cap_mplane,
++	.vidioc_g_fmt_vid_cap_mplane = hdmirx_g_fmt_vid_cap_mplane,
++	.vidioc_enum_fmt_vid_cap = hdmirx_enum_fmt_vid_cap_mplane,
++
++	.vidioc_s_dv_timings = hdmirx_s_dv_timings,
++	.vidioc_g_dv_timings = hdmirx_g_dv_timings,
++	.vidioc_enum_dv_timings = hdmirx_enum_dv_timings,
++	.vidioc_query_dv_timings = hdmirx_query_dv_timings,
++	.vidioc_dv_timings_cap = hdmirx_dv_timings_cap,
++	.vidioc_enum_input = hdmirx_enum_input,
++	.vidioc_g_input = hdmirx_get_input,
++	.vidioc_s_input = hdmirx_set_input,
++	.vidioc_g_edid = hdmirx_get_edid,
++	.vidioc_s_edid = hdmirx_set_edid,
++	.vidioc_g_parm = hdmirx_g_parm,
++
++	.vidioc_reqbufs = vb2_ioctl_reqbufs,
++	.vidioc_querybuf = vb2_ioctl_querybuf,
++	.vidioc_create_bufs = vb2_ioctl_create_bufs,
++	.vidioc_qbuf = vb2_ioctl_qbuf,
++	.vidioc_expbuf = vb2_ioctl_expbuf,
++	.vidioc_dqbuf = vb2_ioctl_dqbuf,
++	.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
++	.vidioc_streamon = vb2_ioctl_streamon,
++	.vidioc_streamoff = vb2_ioctl_streamoff,
++
++	.vidioc_log_status = v4l2_ctrl_log_status,
++	.vidioc_subscribe_event = hdmirx_subscribe_event,
++	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
++};
++
++static const struct v4l2_file_operations hdmirx_fops = {
++	.owner = THIS_MODULE,
++	.open = v4l2_fh_open,
++	.release = vb2_fop_release,
++	.unlocked_ioctl = video_ioctl2,
++	.poll = vb2_fop_poll,
++	.mmap = vb2_fop_mmap,
++};
++
++static int hdmirx_register_stream_vdev(struct hdmirx_stream *stream)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct video_device *vdev = &stream->vdev;
++	int ret = 0;
++
++	strscpy(vdev->name, "stream_hdmirx", sizeof(vdev->name));
++	INIT_LIST_HEAD(&stream->buf_head);
++	spin_lock_init(&stream->vbq_lock);
++	mutex_init(&stream->vlock);
++	init_waitqueue_head(&stream->wq_stopped);
++	stream->curr_buf = NULL;
++	stream->next_buf = NULL;
++
++	vdev->ioctl_ops = &hdmirx_v4l2_ioctl_ops;
++	vdev->release = video_device_release_empty;
++	vdev->fops = &hdmirx_fops;
++	vdev->minor = -1;
++	vdev->v4l2_dev = v4l2_dev;
++	vdev->lock = &stream->vlock;
++	vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
++			    V4L2_CAP_STREAMING;
++	video_set_drvdata(vdev, stream);
++	vdev->vfl_dir = VFL_DIR_RX;
++
++	hdmirx_init_vb2_queue(&stream->buf_queue, stream,
++			      V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
++	vdev->queue = &stream->buf_queue;
++
++	ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
++	if (ret < 0) {
++		v4l2_err(v4l2_dev, "video_register_device failed: %d\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static void process_signal_change(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
++			   LINE_FLAG_INT_EN |
++			   HDMIRX_DMA_IDLE_INT |
++			   HDMIRX_LOCK_DISABLE_INT |
++			   LAST_FRAME_AXI_UNFINISH_INT_EN |
++			   FIFO_OVERFLOW_INT_EN |
++			   FIFO_UNDERFLOW_INT_EN |
++			   HDMIRX_AXI_ERROR_INT_EN, 0);
++	hdmirx_reset_dma(hdmirx_dev);
++	hdmirx_dev->got_timing = false;
++	queue_delayed_work(system_unbound_wq,
++			   &hdmirx_dev->delayed_work_res_change,
++			   msecs_to_jiffies(50));
++}
++
++static void avpunit_0_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				  int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	if (status & (CED_DYN_CNT_CH2_IRQ |
++		      CED_DYN_CNT_CH1_IRQ |
++		      CED_DYN_CNT_CH0_IRQ)) {
++		process_signal_change(hdmirx_dev);
++		v4l2_dbg(2, debug, v4l2_dev, "%s: avp0_st:%#x\n",
++			 __func__, status);
++		*handled = true;
++	}
++
++	hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_FORCE, 0x0);
++}
++
++static void avpunit_1_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				  int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	if (status & DEFRAMER_VSYNC_THR_REACHED_IRQ) {
++		v4l2_info(v4l2_dev, "Vertical Sync threshold reached interrupt %#x", status);
++		hdmirx_update_bits(hdmirx_dev, AVPUNIT_1_INT_MASK_N,
++				   DEFRAMER_VSYNC_THR_REACHED_MASK_N, 0);
++		*handled = true;
++	}
++}
++
++static void mainunit_0_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				   int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	v4l2_dbg(2, debug, v4l2_dev, "mu0_st:%#x\n", status);
++	if (status & TIMER_BASE_LOCKED_IRQ) {
++		hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N,
++				   TIMER_BASE_LOCKED_IRQ, 0);
++		complete(&hdmirx_dev->timer_base_lock);
++		*handled = true;
++	}
++
++	if (status & TMDSQPCLK_OFF_CHG) {
++		process_signal_change(hdmirx_dev);
++		v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSQPCLK_OFF_CHG\n", __func__);
++		*handled = true;
++	}
++
++	if (status & TMDSQPCLK_LOCKED_CHG) {
++		process_signal_change(hdmirx_dev);
++		v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSQPCLK_LOCKED_CHG\n", __func__);
++		*handled = true;
++	}
++
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_FORCE, 0x0);
++}
++
++static void mainunit_2_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				   int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	v4l2_dbg(2, debug, v4l2_dev, "mu2_st:%#x\n", status);
++	if (status & PHYCREG_CR_WRITE_DONE) {
++		hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
++				   PHYCREG_CR_WRITE_DONE, 0);
++		complete(&hdmirx_dev->cr_write_done);
++		*handled = true;
++	}
++
++	if (status & TMDSVALID_STABLE_CHG) {
++		process_signal_change(hdmirx_dev);
++		v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSVALID_STABLE_CHG\n", __func__);
++		*handled = true;
++	}
++
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_FORCE, 0x0);
++}
++
++static void pkt_2_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++			      int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	v4l2_dbg(2, debug, v4l2_dev, "%s: pk2_st:%#x\n", __func__, status);
++	if (status & PKTDEC_AVIIF_RCV_IRQ) {
++		hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N,
++				   PKTDEC_AVIIF_RCV_IRQ, 0);
++		complete(&hdmirx_dev->avi_pkt_rcv);
++		v4l2_dbg(2, debug, v4l2_dev, "%s: AVIIF_RCV_IRQ\n", __func__);
++		*handled = true;
++	}
++
++	hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff);
++}
++
++static void scdc_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++			     int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	v4l2_dbg(2, debug, v4l2_dev, "%s: scdc_st:%#x\n", __func__, status);
++	if (status & SCDCTMDSCCFG_CHG) {
++		hdmirx_tmds_clk_ratio_config(hdmirx_dev);
++		*handled = true;
++	}
++
++	hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff);
++}
++
++static irqreturn_t hdmirx_hdmi_irq_handler(int irq, void *dev_id)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_id;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct arm_smccc_res res;
++	u32 mu0_st, mu2_st, pk2_st, scdc_st, avp1_st, avp0_st;
++	u32 mu0_mask, mu2_mask, pk2_mask, scdc_mask, avp1_msk, avp0_msk;
++	bool handled = false;
++
++	mu0_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_MASK_N);
++	mu2_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_MASK_N);
++	pk2_mask = hdmirx_readl(hdmirx_dev, PKT_2_INT_MASK_N);
++	scdc_mask = hdmirx_readl(hdmirx_dev, SCDC_INT_MASK_N);
++	mu0_st = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_STATUS);
++	mu2_st = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_STATUS);
++	pk2_st = hdmirx_readl(hdmirx_dev, PKT_2_INT_STATUS);
++	scdc_st = hdmirx_readl(hdmirx_dev, SCDC_INT_STATUS);
++	avp0_st = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_STATUS);
++	avp1_st = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_STATUS);
++	avp0_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_MASK_N);
++	avp1_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_MASK_N);
++	mu0_st &= mu0_mask;
++	mu2_st &= mu2_mask;
++	pk2_st &= pk2_mask;
++	avp1_st &= avp1_msk;
++	avp0_st &= avp0_msk;
++	scdc_st &= scdc_mask;
++
++	if (avp0_st)
++		avpunit_0_int_handler(hdmirx_dev, avp0_st, &handled);
++	if (avp1_st)
++		avpunit_1_int_handler(hdmirx_dev, avp1_st, &handled);
++	if (mu0_st)
++		mainunit_0_int_handler(hdmirx_dev, mu0_st, &handled);
++	if (mu2_st)
++		mainunit_2_int_handler(hdmirx_dev, mu2_st, &handled);
++	if (pk2_st)
++		pkt_2_int_handler(hdmirx_dev, pk2_st, &handled);
++	if (scdc_st)
++		scdc_int_handler(hdmirx_dev, scdc_st, &handled);
++
++	if (!handled) {
++		v4l2_dbg(2, debug, v4l2_dev, "%s: hdmi irq not handled", __func__);
++		v4l2_dbg(2, debug, v4l2_dev,
++			 "avp0:%#x, avp1:%#x, mu0:%#x, mu2:%#x, pk2:%#x, scdc:%#x\n",
++			 avp0_st, avp1_st, mu0_st, mu2_st, pk2_st, scdc_st);
++	}
++
++	v4l2_dbg(2, debug, v4l2_dev, "%s: en_fiq", __func__);
++	arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN,
++		      RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res);
++
++	return handled ? IRQ_HANDLED : IRQ_NONE;
++}
++
++static void hdmirx_vb_done(struct hdmirx_stream *stream,
++			   struct vb2_v4l2_buffer *vb_done)
++{
++	const struct v4l2_format_info *finfo = stream->out_finfo;
++	u32 i;
++
++	/* Dequeue a filled buffer */
++	for (i = 0; i < finfo->mem_planes; i++) {
++		vb2_set_plane_payload(&vb_done->vb2_buf, i,
++				      stream->pixm.plane_fmt[i].sizeimage);
++	}
++
++	vb_done->vb2_buf.timestamp = ktime_get_ns();
++	vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
++}
++
++static void dma_idle_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				 bool *handled)
++{
++	struct hdmirx_stream *stream = &hdmirx_dev->stream;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct v4l2_dv_timings timings = hdmirx_dev->timings;
++	struct v4l2_bt_timings *bt = &timings.bt;
++	struct vb2_v4l2_buffer *vb_done = NULL;
++
++	if (!(stream->irq_stat) && !(stream->irq_stat & LINE_FLAG_INT_EN))
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "%s: last time have no line_flag_irq\n", __func__);
++
++	if (stream->line_flag_int_cnt <= FILTER_FRAME_CNT)
++		goto DMA_IDLE_OUT;
++
++	if (bt->interlaced != V4L2_DV_INTERLACED ||
++	    !(stream->line_flag_int_cnt % 2)) {
++		if (stream->next_buf) {
++			if (stream->curr_buf)
++				vb_done = &stream->curr_buf->vb;
++
++			if (vb_done) {
++				vb_done->vb2_buf.timestamp = ktime_get_ns();
++				vb_done->sequence = stream->frame_idx;
++				hdmirx_vb_done(stream, vb_done);
++				stream->frame_idx++;
++				if (stream->frame_idx == 30)
++					v4l2_info(v4l2_dev, "rcv frames\n");
++			}
++
++			stream->curr_buf = NULL;
++			if (stream->next_buf) {
++				stream->curr_buf = stream->next_buf;
++				stream->next_buf = NULL;
++			}
++		} else {
++			v4l2_dbg(3, debug, v4l2_dev,
++				 "%s: next_buf NULL, skip vb_done\n", __func__);
++		}
++	}
++
++DMA_IDLE_OUT:
++	*handled = true;
++}
++
++static void line_flag_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				  bool *handled)
++{
++	struct hdmirx_stream *stream = &hdmirx_dev->stream;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct v4l2_dv_timings timings = hdmirx_dev->timings;
++	struct v4l2_bt_timings *bt = &timings.bt;
++	u32 dma_cfg6;
++
++	stream->line_flag_int_cnt++;
++	if (!(stream->irq_stat) && !(stream->irq_stat & HDMIRX_DMA_IDLE_INT))
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "%s: last have no dma_idle_irq\n", __func__);
++	dma_cfg6 = hdmirx_readl(hdmirx_dev, DMA_CONFIG6);
++	if (!(dma_cfg6 & HDMIRX_DMA_EN)) {
++		v4l2_dbg(2, debug, v4l2_dev, "%s: dma not on\n", __func__);
++		goto LINE_FLAG_OUT;
++	}
++
++	if (stream->line_flag_int_cnt <= FILTER_FRAME_CNT)
++		goto LINE_FLAG_OUT;
++
++	if (bt->interlaced != V4L2_DV_INTERLACED ||
++	    !(stream->line_flag_int_cnt % 2)) {
++		if (!stream->next_buf) {
++			spin_lock(&stream->vbq_lock);
++			if (!list_empty(&stream->buf_head)) {
++				stream->next_buf = list_first_entry(&stream->buf_head,
++								    struct hdmirx_buffer,
++								    queue);
++				list_del(&stream->next_buf->queue);
++			} else {
++				stream->next_buf = NULL;
++			}
++			spin_unlock(&stream->vbq_lock);
++
++			if (stream->next_buf) {
++				hdmirx_writel(hdmirx_dev, DMA_CONFIG2,
++					      stream->next_buf->buff_addr[HDMIRX_PLANE_Y]);
++				hdmirx_writel(hdmirx_dev, DMA_CONFIG3,
++					      stream->next_buf->buff_addr[HDMIRX_PLANE_CBCR]);
++			} else {
++				v4l2_dbg(3, debug, v4l2_dev,
++					 "%s: no buffer is available\n", __func__);
++			}
++		}
++	} else {
++		v4l2_dbg(3, debug, v4l2_dev, "%s: interlace:%d, line_flag_int_cnt:%d\n",
++			 __func__, bt->interlaced, stream->line_flag_int_cnt);
++	}
++
++LINE_FLAG_OUT:
++	*handled = true;
++}
++
++static irqreturn_t hdmirx_dma_irq_handler(int irq, void *dev_id)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_id;
++	struct hdmirx_stream *stream = &hdmirx_dev->stream;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 dma_stat1, dma_stat13;
++	bool handled = false;
++
++	dma_stat1 = hdmirx_readl(hdmirx_dev, DMA_STATUS1);
++	dma_stat13 = hdmirx_readl(hdmirx_dev, DMA_STATUS13);
++	v4l2_dbg(3, debug, v4l2_dev, "dma_irq st1:%#x, st13:%d\n",
++		 dma_stat1, dma_stat13);
++
++	if (READ_ONCE(stream->stopping)) {
++		v4l2_dbg(1, debug, v4l2_dev, "%s: stop stream\n", __func__);
++		hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
++				   LINE_FLAG_INT_EN |
++				   HDMIRX_DMA_IDLE_INT |
++				   HDMIRX_LOCK_DISABLE_INT |
++				   LAST_FRAME_AXI_UNFINISH_INT_EN |
++				   FIFO_OVERFLOW_INT_EN |
++				   FIFO_UNDERFLOW_INT_EN |
++				   HDMIRX_AXI_ERROR_INT_EN, 0);
++		WRITE_ONCE(stream->stopping, false);
++		wake_up(&stream->wq_stopped);
++		return IRQ_HANDLED;
++	}
++
++	if (dma_stat1 & HDMIRX_DMA_IDLE_INT)
++		dma_idle_int_handler(hdmirx_dev, &handled);
++
++	if (dma_stat1 & LINE_FLAG_INT_EN)
++		line_flag_int_handler(hdmirx_dev, &handled);
++
++	if (!handled)
++		v4l2_dbg(3, debug, v4l2_dev,
++			 "%s: dma irq not handled, dma_stat1:%#x\n",
++			 __func__, dma_stat1);
++
++	stream->irq_stat = dma_stat1;
++	hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
++
++	return IRQ_HANDLED;
++}
++
++static void hdmirx_plugin(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct arm_smccc_res res;
++	int ret;
++
++	queue_delayed_work(system_unbound_wq,
++			   &hdmirx_dev->delayed_work_heartbeat,
++			   msecs_to_jiffies(10));
++	arm_smccc_smc(SIP_WDT_CFG, WDT_START, 0, 0, 0, 0, 0, 0, &res);
++	hdmirx_submodule_init(hdmirx_dev);
++	hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED,
++			   POWERPROVIDED);
++	hdmirx_hpd_ctrl(hdmirx_dev, true);
++	hdmirx_phy_config(hdmirx_dev);
++	ret = hdmirx_wait_lock_and_get_timing(hdmirx_dev);
++	if (ret) {
++		hdmirx_plugout(hdmirx_dev);
++		queue_delayed_work(system_unbound_wq,
++				   &hdmirx_dev->delayed_work_hotplug,
++				   msecs_to_jiffies(200));
++		return;
++	}
++	hdmirx_dma_config(hdmirx_dev);
++	hdmirx_interrupts_setup(hdmirx_dev, true);
++}
++
++static void hdmirx_delayed_work_hotplug(struct work_struct *work)
++{
++	struct snps_hdmirx_dev *hdmirx_dev;
++	bool plugin;
++
++	hdmirx_dev = container_of(work, struct snps_hdmirx_dev,
++				  delayed_work_hotplug.work);
++
++	mutex_lock(&hdmirx_dev->work_lock);
++	hdmirx_dev->got_timing = false;
++	plugin = tx_5v_power_present(hdmirx_dev);
++	v4l2_ctrl_s_ctrl(hdmirx_dev->detect_tx_5v_ctrl, plugin);
++	v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: plugin:%d\n",
++		 __func__, plugin);
++
++	if (plugin)
++		hdmirx_plugin(hdmirx_dev);
++	else
++		hdmirx_plugout(hdmirx_dev);
++
++	mutex_unlock(&hdmirx_dev->work_lock);
++}
++
++static void hdmirx_delayed_work_res_change(struct work_struct *work)
++{
++	struct snps_hdmirx_dev *hdmirx_dev;
++	bool plugin;
++
++	hdmirx_dev = container_of(work, struct snps_hdmirx_dev,
++				  delayed_work_res_change.work);
++
++	mutex_lock(&hdmirx_dev->work_lock);
++	plugin = tx_5v_power_present(hdmirx_dev);
++	v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: plugin:%d\n",
++		 __func__, plugin);
++	if (plugin) {
++		hdmirx_interrupts_setup(hdmirx_dev, false);
++		hdmirx_submodule_init(hdmirx_dev);
++		hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED,
++				   POWERPROVIDED);
++		hdmirx_hpd_ctrl(hdmirx_dev, true);
++		hdmirx_phy_config(hdmirx_dev);
++
++		if (hdmirx_wait_lock_and_get_timing(hdmirx_dev)) {
++			hdmirx_plugout(hdmirx_dev);
++			queue_delayed_work(system_unbound_wq,
++					   &hdmirx_dev->delayed_work_hotplug,
++					   msecs_to_jiffies(200));
++		} else {
++			hdmirx_dma_config(hdmirx_dev);
++			hdmirx_interrupts_setup(hdmirx_dev, true);
++		}
++	}
++	mutex_unlock(&hdmirx_dev->work_lock);
++}
++
++static void hdmirx_delayed_work_heartbeat(struct work_struct *work)
++{
++	struct delayed_work *dwork = to_delayed_work(work);
++	struct snps_hdmirx_dev *hdmirx_dev = container_of(dwork,
++							struct snps_hdmirx_dev,
++							delayed_work_heartbeat);
++
++	queue_work(system_highpri_wq, &hdmirx_dev->work_wdt_config);
++	queue_delayed_work(system_unbound_wq,
++			   &hdmirx_dev->delayed_work_heartbeat, HZ);
++}
++
++static void hdmirx_work_wdt_config(struct work_struct *work)
++{
++	struct arm_smccc_res res;
++	struct snps_hdmirx_dev *hdmirx_dev = container_of(work,
++							struct snps_hdmirx_dev,
++							work_wdt_config);
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	arm_smccc_smc(SIP_WDT_CFG, WDT_PING, 0, 0, 0, 0, 0, 0, &res);
++	v4l2_dbg(3, debug, v4l2_dev, "hb\n");
++}
++
++static irqreturn_t hdmirx_5v_det_irq_handler(int irq, void *dev_id)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_id;
++	u32 val;
++
++	val = gpiod_get_value(hdmirx_dev->detect_5v_gpio);
++	v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: 5v:%d\n", __func__, val);
++
++	queue_delayed_work(system_unbound_wq,
++			   &hdmirx_dev->delayed_work_hotplug,
++			   msecs_to_jiffies(10));
++
++	return IRQ_HANDLED;
++}
++
++static const struct hdmirx_cec_ops hdmirx_cec_ops = {
++	.write = hdmirx_writel,
++	.read = hdmirx_readl,
++};
++
++static int hdmirx_parse_dt(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct device *dev = hdmirx_dev->dev;
++	int ret;
++
++	hdmirx_dev->num_clks = devm_clk_bulk_get_all(dev, &hdmirx_dev->clks);
++	if (hdmirx_dev->num_clks < 1)
++		return -ENODEV;
++
++	hdmirx_dev->resets[HDMIRX_RST_A].id = "axi";
++	hdmirx_dev->resets[HDMIRX_RST_P].id = "apb";
++	hdmirx_dev->resets[HDMIRX_RST_REF].id = "ref";
++	hdmirx_dev->resets[HDMIRX_RST_BIU].id = "biu";
++
++	ret = devm_reset_control_bulk_get_exclusive(dev, HDMIRX_NUM_RST,
++						    hdmirx_dev->resets);
++	if (ret < 0) {
++		dev_err(dev, "failed to get reset controls\n");
++		return ret;
++	}
++
++	hdmirx_dev->detect_5v_gpio =
++		devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
++
++	if (IS_ERR(hdmirx_dev->detect_5v_gpio)) {
++		dev_err(dev, "failed to get hdmirx hot plug detection gpio\n");
++		return PTR_ERR(hdmirx_dev->detect_5v_gpio);
++	}
++
++	hdmirx_dev->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
++							  "rockchip,grf");
++	if (IS_ERR(hdmirx_dev->grf)) {
++		dev_err(dev, "failed to get rockchip,grf\n");
++		return PTR_ERR(hdmirx_dev->grf);
++	}
++
++	hdmirx_dev->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
++							      "rockchip,vo1-grf");
++	if (IS_ERR(hdmirx_dev->vo1_grf)) {
++		dev_err(dev, "failed to get rockchip,vo1-grf\n");
++		return PTR_ERR(hdmirx_dev->vo1_grf);
++	}
++
++	hdmirx_dev->hpd_trigger_level = !device_property_read_bool(dev, "hpd-is-active-low");
++
++	ret = of_reserved_mem_device_init(dev);
++	if (ret)
++		dev_warn(dev, "No reserved memory for HDMIRX, use default CMA\n");
++
++	return 0;
++}
++
++static void hdmirx_disable_all_interrupts(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, MAINUNIT_1_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, AVPUNIT_1_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, PKT_0_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, PKT_1_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, PKT_2_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, SCDC_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, CEC_INT_MASK_N, 0);
++
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_1_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_1_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, PKT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, PKT_1_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, HDCP_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, HDCP_1_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, CEC_INT_CLEAR, 0xffffffff);
++}
++
++static int hdmirx_init(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET | PHY_PDDQ, 0);
++
++	regmap_write(hdmirx_dev->vo1_grf, VO1_GRF_VO1_CON2,
++		     (HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) |
++		     ((HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) << 16));
++	/*
++	 * Some interrupts are enabled by default, so we disable
++	 * all interrupts and clear interrupts status first.
++	 */
++	hdmirx_disable_all_interrupts(hdmirx_dev);
++
++	return 0;
++}
++
++static void hdmirx_load_default_edid(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	int ret;
++	struct v4l2_edid def_edid;
++
++	hdmirx_hpd_ctrl(hdmirx_dev, false);
++
++	/* disable hpd and write edid */
++	def_edid.pad = 0;
++	def_edid.start_block = 0;
++	def_edid.blocks = EDID_NUM_BLOCKS_MAX;
++
++	if (IS_ENABLED(CONFIG_HDMIRX_LOAD_DEFAULT_EDID))
++		def_edid.edid = edid_init_data_340M;
++	else
++		def_edid.edid = hdmirx_dev->edid;
++
++	ret = hdmirx_write_edid(hdmirx_dev, &def_edid, true);
++	if (ret)
++		dev_err(hdmirx_dev->dev, "%s: write edid failed\n", __func__);
++}
++
++static void hdmirx_disable_irq(struct device *dev)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
++	struct arm_smccc_res res;
++
++	disable_irq(hdmirx_dev->hdmi_irq);
++	disable_irq(hdmirx_dev->dma_irq);
++	disable_irq(hdmirx_dev->det_irq);
++
++	arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_DIS,
++		      RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res);
++
++	cancel_delayed_work_sync(&hdmirx_dev->delayed_work_hotplug);
++	cancel_delayed_work_sync(&hdmirx_dev->delayed_work_res_change);
++	cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat);
++	flush_work(&hdmirx_dev->work_wdt_config);
++
++	arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res);
++}
++
++static int hdmirx_disable(struct device *dev)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	clk_bulk_disable_unprepare(hdmirx_dev->num_clks, hdmirx_dev->clks);
++
++	v4l2_dbg(2, debug, v4l2_dev, "%s: suspend\n", __func__);
++
++	return pinctrl_pm_select_sleep_state(dev);
++}
++
++static void hdmirx_enable_irq(struct device *dev)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
++	struct arm_smccc_res res;
++
++	enable_irq(hdmirx_dev->hdmi_irq);
++	enable_irq(hdmirx_dev->dma_irq);
++	enable_irq(hdmirx_dev->det_irq);
++
++	arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN,
++		      RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res);
++
++	queue_delayed_work(system_unbound_wq, &hdmirx_dev->delayed_work_hotplug,
++			   msecs_to_jiffies(20));
++}
++
++static int hdmirx_enable(struct device *dev)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	int ret;
++
++	v4l2_dbg(2, debug, v4l2_dev, "%s: resume\n", __func__);
++	ret = pinctrl_pm_select_default_state(dev);
++	if (ret < 0)
++		return ret;
++
++	ret = clk_bulk_prepare_enable(hdmirx_dev->num_clks, hdmirx_dev->clks);
++	if (ret) {
++		dev_err(dev, "failed to enable hdmirx bulk clks: %d\n", ret);
++		return ret;
++	}
++
++	reset_control_bulk_assert(HDMIRX_NUM_RST, hdmirx_dev->resets);
++	usleep_range(150, 160);
++	reset_control_bulk_deassert(HDMIRX_NUM_RST, hdmirx_dev->resets);
++	usleep_range(150, 160);
++
++	return 0;
++}
++
++static int hdmirx_suspend(struct device *dev)
++{
++	hdmirx_disable_irq(dev);
++
++	return hdmirx_disable(dev);
++}
++
++static int hdmirx_resume(struct device *dev)
++{
++	int ret = hdmirx_enable(dev);
++
++	if (ret)
++		return ret;
++
++	hdmirx_enable_irq(dev);
++
++	return 0;
++}
++
++static const struct dev_pm_ops snps_hdmirx_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(hdmirx_suspend, hdmirx_resume)
++};
++
++static int hdmirx_setup_irq(struct snps_hdmirx_dev *hdmirx_dev,
++			    struct platform_device *pdev)
++{
++	struct device *dev = hdmirx_dev->dev;
++	int ret, irq;
++
++	irq = platform_get_irq_byname(pdev, "hdmi");
++	if (irq < 0) {
++		dev_err_probe(dev, irq, "failed to get hdmi irq\n");
++		return irq;
++	}
++
++	irq_set_status_flags(irq, IRQ_NOAUTOEN);
++
++	hdmirx_dev->hdmi_irq = irq;
++	ret = devm_request_irq(dev, irq, hdmirx_hdmi_irq_handler, 0,
++			       "rk_hdmirx-hdmi", hdmirx_dev);
++	if (ret) {
++		dev_err_probe(dev, ret, "failed to request hdmi irq\n");
++		return ret;
++	}
++
++	irq = platform_get_irq_byname(pdev, "dma");
++	if (irq < 0) {
++		dev_err_probe(dev, irq, "failed to get dma irq\n");
++		return irq;
++	}
++
++	irq_set_status_flags(irq, IRQ_NOAUTOEN);
++
++	hdmirx_dev->dma_irq = irq;
++	ret = devm_request_threaded_irq(dev, irq, NULL, hdmirx_dma_irq_handler,
++					IRQF_ONESHOT, "rk_hdmirx-dma",
++					hdmirx_dev);
++	if (ret) {
++		dev_err_probe(dev, ret, "failed to request dma irq\n");
++		return ret;
++	}
++
++	irq = gpiod_to_irq(hdmirx_dev->detect_5v_gpio);
++	if (irq < 0) {
++		dev_err_probe(dev, irq, "failed to get hdmirx-5v irq\n");
++		return irq;
++	}
++
++	irq_set_status_flags(irq, IRQ_NOAUTOEN);
++
++	hdmirx_dev->det_irq = irq;
++	ret = devm_request_irq(dev, irq, hdmirx_5v_det_irq_handler,
++			       IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
++			       "rk_hdmirx-5v", hdmirx_dev);
++	if (ret) {
++		dev_err_probe(dev, ret, "failed to request hdmirx-5v irq\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int hdmirx_register_cec(struct snps_hdmirx_dev *hdmirx_dev,
++			       struct platform_device *pdev)
++{
++	struct device *dev = hdmirx_dev->dev;
++	struct hdmirx_cec_data cec_data;
++	int irq;
++
++	irq = platform_get_irq_byname(pdev, "cec");
++	if (irq < 0) {
++		dev_err_probe(dev, irq, "failed to get cec irq\n");
++		return irq;
++	}
++
++	hdmirx_dev->cec_notifier = cec_notifier_conn_register(dev, NULL, NULL);
++	if (!hdmirx_dev->cec_notifier)
++		return -EINVAL;
++
++	cec_data.hdmirx = hdmirx_dev;
++	cec_data.dev = hdmirx_dev->dev;
++	cec_data.ops = &hdmirx_cec_ops;
++	cec_data.irq = irq;
++
++	hdmirx_dev->cec = snps_hdmirx_cec_register(&cec_data);
++	if (!hdmirx_dev->cec) {
++		cec_notifier_conn_unregister(hdmirx_dev->cec_notifier);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int hdmirx_probe(struct platform_device *pdev)
++{
++	struct snps_hdmirx_dev *hdmirx_dev;
++	struct device *dev = &pdev->dev;
++	struct v4l2_ctrl_handler *hdl;
++	struct hdmirx_stream *stream;
++	struct v4l2_device *v4l2_dev;
++	int ret;
++
++	hdmirx_dev = devm_kzalloc(dev, sizeof(*hdmirx_dev), GFP_KERNEL);
++	if (!hdmirx_dev)
++		return -ENOMEM;
++
++	ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
++	if (ret)
++		return ret;
++
++	hdmirx_dev->dev = dev;
++	dev_set_drvdata(dev, hdmirx_dev);
++
++	ret = hdmirx_parse_dt(hdmirx_dev);
++	if (ret)
++		return ret;
++
++	ret = hdmirx_setup_irq(hdmirx_dev, pdev);
++	if (ret)
++		return ret;
++
++	hdmirx_dev->regs = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(hdmirx_dev->regs))
++		return dev_err_probe(dev, PTR_ERR(hdmirx_dev->regs),
++				     "failed to remap regs resource\n");
++
++	mutex_init(&hdmirx_dev->stream_lock);
++	mutex_init(&hdmirx_dev->work_lock);
++	spin_lock_init(&hdmirx_dev->rst_lock);
++
++	init_completion(&hdmirx_dev->cr_write_done);
++	init_completion(&hdmirx_dev->timer_base_lock);
++	init_completion(&hdmirx_dev->avi_pkt_rcv);
++
++	INIT_WORK(&hdmirx_dev->work_wdt_config, hdmirx_work_wdt_config);
++	INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_hotplug,
++			  hdmirx_delayed_work_hotplug);
++	INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_res_change,
++			  hdmirx_delayed_work_res_change);
++	INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_heartbeat,
++			  hdmirx_delayed_work_heartbeat);
++
++	hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
++	hdmirx_dev->timings = cea640x480;
++
++	hdmirx_enable(dev);
++	hdmirx_init(hdmirx_dev);
++
++	v4l2_dev = &hdmirx_dev->v4l2_dev;
++	strscpy(v4l2_dev->name, dev_name(dev), sizeof(v4l2_dev->name));
++
++	hdl = &hdmirx_dev->hdl;
++	v4l2_ctrl_handler_init(hdl, 1);
++
++	hdmirx_dev->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
++							  V4L2_CID_DV_RX_POWER_PRESENT,
++							  0, 1, 0, 0);
++
++	hdmirx_dev->rgb_range = v4l2_ctrl_new_std_menu(hdl, 0,
++						       V4L2_CID_DV_RX_RGB_RANGE,
++						       V4L2_DV_RGB_RANGE_FULL, 0,
++						       V4L2_DV_RGB_RANGE_AUTO);
++
++	hdmirx_dev->rgb_range->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++
++	if (hdl->error) {
++		dev_err(dev, "v4l2 ctrl handler init failed\n");
++		ret = hdl->error;
++		goto err_pm;
++	}
++	hdmirx_dev->v4l2_dev.ctrl_handler = hdl;
++
++	ret = v4l2_device_register(dev, &hdmirx_dev->v4l2_dev);
++	if (ret < 0) {
++		dev_err(dev, "register v4l2 device failed\n");
++		goto err_hdl;
++	}
++
++	stream = &hdmirx_dev->stream;
++	stream->hdmirx_dev = hdmirx_dev;
++	ret = hdmirx_register_stream_vdev(stream);
++	if (ret < 0) {
++		dev_err(dev, "register video device failed\n");
++		goto err_unreg_v4l2_dev;
++	}
++
++	ret = hdmirx_register_cec(hdmirx_dev, pdev);
++	if (ret)
++		goto err_unreg_video_dev;
++
++	hdmirx_load_default_edid(hdmirx_dev);
++
++	hdmirx_enable_irq(dev);
++
++	return 0;
++
++err_unreg_video_dev:
++	video_unregister_device(&hdmirx_dev->stream.vdev);
++err_unreg_v4l2_dev:
++	v4l2_device_unregister(&hdmirx_dev->v4l2_dev);
++err_hdl:
++	v4l2_ctrl_handler_free(&hdmirx_dev->hdl);
++err_pm:
++	hdmirx_disable(dev);
++
++	return ret;
++}
++
++static void hdmirx_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
++
++	snps_hdmirx_cec_unregister(hdmirx_dev->cec);
++	cec_notifier_conn_unregister(hdmirx_dev->cec_notifier);
++
++	hdmirx_disable_irq(dev);
++
++	video_unregister_device(&hdmirx_dev->stream.vdev);
++	v4l2_ctrl_handler_free(&hdmirx_dev->hdl);
++	v4l2_device_unregister(&hdmirx_dev->v4l2_dev);
++
++	hdmirx_disable(dev);
++
++	reset_control_bulk_assert(HDMIRX_NUM_RST, hdmirx_dev->resets);
++
++	of_reserved_mem_device_release(dev);
++}
++
++static const struct of_device_id hdmirx_id[] = {
++	{ .compatible = "rockchip,rk3588-hdmirx-ctrler" },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, hdmirx_id);
++
++static struct platform_driver hdmirx_driver = {
++	.probe = hdmirx_probe,
++	.remove_new = hdmirx_remove,
++	.driver = {
++		.name = "snps_hdmirx",
++		.of_match_table = hdmirx_id,
++		.pm = &snps_hdmirx_pm_ops,
++	}
++};
++module_platform_driver(hdmirx_driver);
++
++MODULE_DESCRIPTION("Rockchip HDMI Receiver Driver");
++MODULE_AUTHOR("Dingxian Wen <shawn.wen@rock-chips.com>");
++MODULE_AUTHOR("Shreeya Patel <shreeya.patel@collabora.com>");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h
+@@ -0,0 +1,394 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ *
++ * Author: Dingxian Wen <shawn.wen@rock-chips.com>
++ */
++
++#ifndef DW_HDMIRX_H
++#define DW_HDMIRX_H
++
++#include <linux/bitops.h>
++
++#define UPDATE(x, h, l)		(((x) << (l)) & GENMASK((h), (l)))
++#define HIWORD_UPDATE(v, h, l)	(((v) << (l)) | (GENMASK((h), (l)) << 16))
++
++/* SYS_GRF */
++#define SYS_GRF_SOC_CON1			0x0304
++#define HDMIRXPHY_SRAM_EXT_LD_DONE		BIT(1)
++#define HDMIRXPHY_SRAM_BYPASS			BIT(0)
++#define SYS_GRF_SOC_STATUS1			0x0384
++#define HDMIRXPHY_SRAM_INIT_DONE		BIT(10)
++#define SYS_GRF_CHIP_ID				0x0600
++
++/* VO1_GRF */
++#define VO1_GRF_VO1_CON2			0x0008
++#define HDMIRX_SDAIN_MSK			BIT(2)
++#define HDMIRX_SCLIN_MSK			BIT(1)
++
++/* HDMIRX PHY */
++#define SUP_DIG_ANA_CREGS_SUP_ANA_NC			0x004f
++
++#define	LANE0_DIG_ASIC_RX_OVRD_OUT_0			0x100f
++#define	LANE1_DIG_ASIC_RX_OVRD_OUT_0			0x110f
++#define	LANE2_DIG_ASIC_RX_OVRD_OUT_0			0x120f
++#define	LANE3_DIG_ASIC_RX_OVRD_OUT_0			0x130f
++#define ASIC_ACK_OVRD_EN				BIT(1)
++#define ASIC_ACK					BIT(0)
++
++#define	LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x104a
++#define	LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x114a
++#define	LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x124a
++#define	LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x134a
++#define FREQ_TUNE_START_VAL_MASK			GENMASK(9, 0)
++#define FREQ_TUNE_START_VAL(x)				UPDATE(x, 9, 0)
++
++#define	HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG	0x20c4
++#define	HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM	0x20c7
++#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG	0x20e9
++#define CDR_SETTING_BOUNDARY_3_DEFAULT			0x52da
++#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG	0x20ea
++#define CDR_SETTING_BOUNDARY_4_DEFAULT			0x43cd
++#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG	0x20eb
++#define CDR_SETTING_BOUNDARY_5_DEFAULT			0x35b3
++#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG	0x20fb
++#define	CDR_SETTING_BOUNDARY_6_DEFAULT			0x2799
++#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG	0x20fc
++#define CDR_SETTING_BOUNDARY_7_DEFAULT			0x1b65
++
++#define	RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT			0x300e
++#define	RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT			0x310e
++#define	RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT			0x320e
++#define	RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT			0x330e
++#define PCS_ACK_WRITE_SELECT				BIT(14)
++#define PCS_EN_CTL					BIT(1)
++#define PCS_ACK						BIT(0)
++
++#define	RAWLANE0_DIG_AON_FAST_FLAGS			0x305c
++#define	RAWLANE1_DIG_AON_FAST_FLAGS			0x315c
++#define	RAWLANE2_DIG_AON_FAST_FLAGS			0x325c
++#define	RAWLANE3_DIG_AON_FAST_FLAGS			0x335c
++
++/* HDMIRX Ctrler */
++#define GLOBAL_SWRESET_REQUEST			0x0020
++#define DATAPATH_SWRESETREQ			BIT(12)
++#define GLOBAL_SWENABLE				0x0024
++#define PHYCTRL_ENABLE				BIT(21)
++#define CEC_ENABLE				BIT(16)
++#define TMDS_ENABLE				BIT(13)
++#define DATAPATH_ENABLE				BIT(12)
++#define PKTFIFO_ENABLE				BIT(11)
++#define AVPUNIT_ENABLE				BIT(8)
++#define MAIN_ENABLE				BIT(0)
++#define GLOBAL_TIMER_REF_BASE			0x0028
++#define CORE_CONFIG				0x0050
++#define CMU_CONFIG0				0x0060
++#define TMDSQPCLK_STABLE_FREQ_MARGIN_MASK	GENMASK(30, 16)
++#define TMDSQPCLK_STABLE_FREQ_MARGIN(x)		UPDATE(x, 30, 16)
++#define AUDCLK_STABLE_FREQ_MARGIN_MASK		GENMASK(11, 9)
++#define AUDCLK_STABLE_FREQ_MARGIN(x)		UPDATE(x, 11, 9)
++#define CMU_STATUS				0x007c
++#define TMDSQPCLK_LOCKED_ST			BIT(4)
++#define CMU_TMDSQPCLK_FREQ			0x0084
++#define PHY_CONFIG				0x00c0
++#define LDO_AFE_PROG_MASK			GENMASK(24, 23)
++#define LDO_AFE_PROG(x)				UPDATE(x, 24, 23)
++#define LDO_PWRDN				BIT(21)
++#define TMDS_CLOCK_RATIO			BIT(16)
++#define RXDATA_WIDTH				BIT(15)
++#define REFFREQ_SEL_MASK			GENMASK(11, 9)
++#define REFFREQ_SEL(x)				UPDATE(x, 11, 9)
++#define HDMI_DISABLE				BIT(8)
++#define PHY_PDDQ				BIT(1)
++#define PHY_RESET				BIT(0)
++#define PHY_STATUS				0x00c8
++#define HDMI_DISABLE_ACK			BIT(1)
++#define PDDQ_ACK				BIT(0)
++#define PHYCREG_CONFIG0				0x00e0
++#define PHYCREG_CR_PARA_SELECTION_MODE_MASK	GENMASK(1, 0)
++#define PHYCREG_CR_PARA_SELECTION_MODE(x)	UPDATE(x, 1, 0)
++#define PHYCREG_CONFIG1				0x00e4
++#define PHYCREG_CONFIG2				0x00e8
++#define PHYCREG_CONFIG3				0x00ec
++#define PHYCREG_CONTROL				0x00f0
++#define PHYCREG_CR_PARA_WRITE_P			BIT(1)
++#define PHYCREG_CR_PARA_READ_P			BIT(0)
++#define PHYCREG_STATUS				0x00f4
++
++#define MAINUNIT_STATUS				0x0150
++#define TMDSVALID_STABLE_ST			BIT(1)
++#define DESCRAND_EN_CONTROL			0x0210
++#define SCRAMB_EN_SEL_QST_MASK			GENMASK(1, 0)
++#define SCRAMB_EN_SEL_QST(x)			UPDATE(x, 1, 0)
++#define DESCRAND_SYNC_CONTROL			0x0214
++#define RECOVER_UNSYNC_STREAM_QST		BIT(0)
++#define DESCRAND_SYNC_SEQ_CONFIG		0x022c
++#define DESCRAND_SYNC_SEQ_ERR_CNT_EN		BIT(0)
++#define DESCRAND_SYNC_SEQ_STATUS		0x0234
++#define DEFRAMER_CONFIG0			0x0270
++#define VS_CNT_THR_QST_MASK			GENMASK(27, 20)
++#define VS_CNT_THR_QST(x)			UPDATE(x, 27, 20)
++#define HS_POL_QST_MASK				GENMASK(19, 18)
++#define HS_POL_QST(x)				UPDATE(x, 19, 18)
++#define VS_POL_QST_MASK				GENMASK(17, 16)
++#define VS_POL_QST(x)				UPDATE(x, 17, 16)
++#define VS_REMAPFILTER_EN_QST			BIT(8)
++#define VS_FILTER_ORDER_QST_MASK		GENMASK(1, 0)
++#define VS_FILTER_ORDER_QST(x)			UPDATE(x, 1, 0)
++#define DEFRAMER_VSYNC_CNT_CLEAR		0x0278
++#define VSYNC_CNT_CLR_P				BIT(0)
++#define DEFRAMER_STATUS				0x027c
++#define OPMODE_STS_MASK				GENMASK(6, 4)
++#define I2C_SLAVE_CONFIG1			0x0164
++#define I2C_SDA_OUT_HOLD_VALUE_QST_MASK		GENMASK(15, 8)
++#define I2C_SDA_OUT_HOLD_VALUE_QST(x)		UPDATE(x, 15, 8)
++#define I2C_SDA_IN_HOLD_VALUE_QST_MASK		GENMASK(7, 0)
++#define I2C_SDA_IN_HOLD_VALUE_QST(x)		UPDATE(x, 7, 0)
++#define OPMODE_STS_MASK				GENMASK(6, 4)
++#define REPEATER_QST				BIT(28)
++#define FASTREAUTH_QST				BIT(27)
++#define FEATURES_1DOT1_QST			BIT(26)
++#define FASTI2C_QST				BIT(25)
++#define EESS_CTL_THR_QST_MASK			GENMASK(19, 16)
++#define EESS_CTL_THR_QST(x)			UPDATE(x, 19, 16)
++#define OESS_CTL3_THR_QST_MASK			GENMASK(11, 8)
++#define OESS_CTL3_THR_QST(x)			UPDATE(x, 11, 8)
++#define EESS_OESS_SEL_QST_MASK			GENMASK(5, 4)
++#define EESS_OESS_SEL_QST(x)			UPDATE(x, 5, 4)
++#define KEY_DECRYPT_EN_QST			BIT(0)
++#define KEY_DECRYPT_SEED_QST_MASK		GENMASK(15, 0)
++#define KEY_DECRYPT_SEED_QST(x)			UPDATE(x, 15, 0)
++#define HDCP_INT_CLEAR				0x50d8
++#define HDCP_1_INT_CLEAR			0x50e8
++#define HDCP2_CONFIG				0x02f0
++#define HDCP2_SWITCH_OVR_VALUE			BIT(2)
++#define HDCP2_SWITCH_OVR_EN			BIT(1)
++
++#define VIDEO_CONFIG2				0x042c
++#define VPROC_VSYNC_POL_OVR_VALUE		BIT(19)
++#define VPROC_VSYNC_POL_OVR_EN			BIT(18)
++#define VPROC_HSYNC_POL_OVR_VALUE		BIT(17)
++#define VPROC_HSYNC_POL_OVR_EN			BIT(16)
++#define VPROC_FMT_OVR_VALUE_MASK		GENMASK(6, 4)
++#define VPROC_FMT_OVR_VALUE(x)			UPDATE(x, 6, 4)
++#define VPROC_FMT_OVR_EN			BIT(0)
++
++#define AFIFO_FILL_RESTART			BIT(0)
++#define AFIFO_INIT_P				BIT(0)
++#define AFIFO_THR_LOW_QST_MASK			GENMASK(25, 16)
++#define AFIFO_THR_LOW_QST(x)			UPDATE(x, 25, 16)
++#define AFIFO_THR_HIGH_QST_MASK			GENMASK(9, 0)
++#define AFIFO_THR_HIGH_QST(x)			UPDATE(x, 9, 0)
++#define AFIFO_THR_MUTE_LOW_QST_MASK		GENMASK(25, 16)
++#define AFIFO_THR_MUTE_LOW_QST(x)		UPDATE(x, 25, 16)
++#define AFIFO_THR_MUTE_HIGH_QST_MASK		GENMASK(9, 0)
++#define AFIFO_THR_MUTE_HIGH_QST(x)		UPDATE(x, 9, 0)
++
++#define AFIFO_UNDERFLOW_ST			BIT(25)
++#define AFIFO_OVERFLOW_ST			BIT(24)
++
++#define SPEAKER_ALLOC_OVR_EN			BIT(16)
++#define I2S_BPCUV_EN				BIT(4)
++#define SPDIF_EN				BIT(2)
++#define I2S_EN					BIT(1)
++#define AFIFO_THR_PASS_DEMUTEMASK_N		BIT(24)
++#define AVMUTE_DEMUTEMASK_N			BIT(16)
++#define AFIFO_THR_MUTE_LOW_MUTEMASK_N		BIT(9)
++#define AFIFO_THR_MUTE_HIGH_MUTEMASK_N		BIT(8)
++#define AVMUTE_MUTEMASK_N			BIT(0)
++#define SCDC_CONFIG				0x0580
++#define HPDLOW					BIT(1)
++#define POWERPROVIDED				BIT(0)
++#define SCDC_REGBANK_STATUS1			0x058c
++#define SCDC_TMDSBITCLKRATIO			BIT(1)
++#define SCDC_REGBANK_STATUS3			0x0594
++#define SCDC_REGBANK_CONFIG0			0x05c0
++#define SCDC_SINKVERSION_QST_MASK		GENMASK(7, 0)
++#define SCDC_SINKVERSION_QST(x)			UPDATE(x, 7, 0)
++#define AGEN_LAYOUT				BIT(4)
++#define AGEN_SPEAKER_ALLOC			GENMASK(15, 8)
++
++#define CED_CONFIG				0x0760
++#define CED_VIDDATACHECKEN_QST			BIT(27)
++#define CED_DATAISCHECKEN_QST			BIT(26)
++#define CED_GBCHECKEN_QST			BIT(25)
++#define CED_CTRLCHECKEN_QST			BIT(24)
++#define CED_CHLOCKMAXER_QST_MASK		GENMASK(14, 0)
++#define CED_CHLOCKMAXER_QST(x)			UPDATE(x, 14, 0)
++#define CED_DYN_CONFIG				0x0768
++#define CED_DYN_CONTROL				0x076c
++#define PKTEX_BCH_ERRFILT_CONFIG		0x07c4
++#define PKTEX_CHKSUM_ERRFILT_CONFIG		0x07c8
++
++#define PKTDEC_ACR_PH2_1			0x1100
++#define PKTDEC_ACR_PB3_0			0x1104
++#define PKTDEC_ACR_PB7_4			0x1108
++#define PKTDEC_AVIIF_PH2_1			0x1200
++#define PKTDEC_AVIIF_PB3_0			0x1204
++#define PKTDEC_AVIIF_PB7_4			0x1208
++#define VIC_VAL_MASK				GENMASK(6, 0)
++#define PKTDEC_AVIIF_PB11_8			0x120c
++#define PKTDEC_AVIIF_PB15_12			0x1210
++#define PKTDEC_AVIIF_PB19_16			0x1214
++#define PKTDEC_AVIIF_PB23_20			0x1218
++#define PKTDEC_AVIIF_PB27_24			0x121c
++
++#define PKTFIFO_CONFIG				0x1500
++#define PKTFIFO_STORE_FILT_CONFIG		0x1504
++#define PKTFIFO_THR_CONFIG0			0x1508
++#define PKTFIFO_THR_CONFIG1			0x150c
++#define PKTFIFO_CONTROL				0x1510
++
++#define VMON_STATUS1				0x1580
++#define VMON_STATUS2				0x1584
++#define VMON_STATUS3				0x1588
++#define VMON_STATUS4				0x158c
++#define VMON_STATUS5				0x1590
++#define VMON_STATUS6				0x1594
++#define VMON_STATUS7				0x1598
++#define VMON_ILACE_DETECT			BIT(4)
++
++#define CEC_TX_CONTROL				0x2000
++#define CEC_STATUS				0x2004
++#define CEC_CONFIG				0x2008
++#define RX_AUTO_DRIVE_ACKNOWLEDGE		BIT(9)
++#define CEC_ADDR				0x200c
++#define CEC_TX_COUNT				0x2020
++#define CEC_TX_DATA3_0				0x2024
++#define CEC_RX_COUNT_STATUS			0x2040
++#define CEC_RX_DATA3_0				0x2044
++#define CEC_LOCK_CONTROL			0x2054
++#define CEC_RXQUAL_BITTIME_CONFIG		0x2060
++#define CEC_RX_BITTIME_CONFIG			0x2064
++#define CEC_TX_BITTIME_CONFIG			0x2068
++
++#define DMA_CONFIG1				0x4400
++#define UV_WID_MASK				GENMASK(31, 28)
++#define UV_WID(x)				UPDATE(x, 31, 28)
++#define Y_WID_MASK				GENMASK(27, 24)
++#define Y_WID(x)				UPDATE(x, 27, 24)
++#define DDR_STORE_FORMAT_MASK			GENMASK(15, 12)
++#define DDR_STORE_FORMAT(x)			UPDATE(x, 15, 12)
++#define ABANDON_EN				BIT(0)
++#define DMA_CONFIG2				0x4404
++#define DMA_CONFIG3				0x4408
++#define DMA_CONFIG4				0x440c // dma irq en
++#define DMA_CONFIG5				0x4410 // dma irq clear status
++#define LINE_FLAG_INT_EN			BIT(8)
++#define HDMIRX_DMA_IDLE_INT			BIT(7)
++#define HDMIRX_LOCK_DISABLE_INT			BIT(6)
++#define LAST_FRAME_AXI_UNFINISH_INT_EN		BIT(5)
++#define FIFO_OVERFLOW_INT_EN			BIT(2)
++#define FIFO_UNDERFLOW_INT_EN			BIT(1)
++#define HDMIRX_AXI_ERROR_INT_EN			BIT(0)
++#define DMA_CONFIG6				0x4414
++#define RB_SWAP_EN				BIT(9)
++#define HSYNC_TOGGLE_EN				BIT(5)
++#define VSYNC_TOGGLE_EN				BIT(4)
++#define HDMIRX_DMA_EN				BIT(1)
++#define DMA_CONFIG7				0x4418
++#define LINE_FLAG_NUM_MASK			GENMASK(31, 16)
++#define LINE_FLAG_NUM(x)			UPDATE(x, 31, 16)
++#define LOCK_FRAME_NUM_MASK			GENMASK(11, 0)
++#define LOCK_FRAME_NUM(x)			UPDATE(x, 11, 0)
++#define DMA_CONFIG8				0x441c
++#define REG_MIRROR_EN				BIT(0)
++#define DMA_CONFIG9				0x4420
++#define DMA_CONFIG10				0x4424
++#define DMA_CONFIG11				0x4428
++#define EDID_READ_EN_MASK			BIT(8)
++#define EDID_READ_EN(x)				UPDATE(x, 8, 8)
++#define EDID_WRITE_EN_MASK			BIT(7)
++#define EDID_WRITE_EN(x)			UPDATE(x, 7, 7)
++#define EDID_SLAVE_ADDR_MASK			GENMASK(6, 0)
++#define EDID_SLAVE_ADDR(x)			UPDATE(x, 6, 0)
++#define DMA_STATUS1				0x4430 // dma irq status
++#define DMA_STATUS2				0x4434
++#define DMA_STATUS3				0x4438
++#define DMA_STATUS4				0x443c
++#define DMA_STATUS5				0x4440
++#define DMA_STATUS6				0x4444
++#define DMA_STATUS7				0x4448
++#define DMA_STATUS8				0x444c
++#define DMA_STATUS9				0x4450
++#define DMA_STATUS10				0x4454
++#define HDMIRX_LOCK				BIT(3)
++#define DMA_STATUS11				0x4458
++#define HDMIRX_TYPE_MASK			GENMASK(8, 7)
++#define HDMIRX_COLOR_DEPTH_MASK			GENMASK(6, 3)
++#define HDMIRX_FORMAT_MASK			GENMASK(2, 0)
++#define DMA_STATUS12				0x445c
++#define DMA_STATUS13				0x4460
++#define DMA_STATUS14				0x4464
++
++#define MAINUNIT_INTVEC_INDEX			0x5000
++#define MAINUNIT_0_INT_STATUS			0x5010
++#define CECRX_NOTIFY_ERR			BIT(12)
++#define CECRX_EOM				BIT(11)
++#define CECTX_DRIVE_ERR				BIT(10)
++#define CECRX_BUSY				BIT(9)
++#define CECTX_BUSY				BIT(8)
++#define CECTX_FRAME_DISCARDED			BIT(5)
++#define CECTX_NRETRANSMIT_FAIL			BIT(4)
++#define CECTX_LINE_ERR				BIT(3)
++#define CECTX_ARBLOST				BIT(2)
++#define CECTX_NACK				BIT(1)
++#define CECTX_DONE				BIT(0)
++#define MAINUNIT_0_INT_MASK_N			0x5014
++#define MAINUNIT_0_INT_CLEAR			0x5018
++#define MAINUNIT_0_INT_FORCE			0x501c
++#define TIMER_BASE_LOCKED_IRQ			BIT(26)
++#define TMDSQPCLK_OFF_CHG			BIT(5)
++#define TMDSQPCLK_LOCKED_CHG			BIT(4)
++#define MAINUNIT_1_INT_STATUS			0x5020
++#define MAINUNIT_1_INT_MASK_N			0x5024
++#define MAINUNIT_1_INT_CLEAR			0x5028
++#define MAINUNIT_1_INT_FORCE			0x502c
++#define MAINUNIT_2_INT_STATUS			0x5030
++#define MAINUNIT_2_INT_MASK_N			0x5034
++#define MAINUNIT_2_INT_CLEAR			0x5038
++#define MAINUNIT_2_INT_FORCE			0x503c
++#define PHYCREG_CR_READ_DONE			BIT(11)
++#define PHYCREG_CR_WRITE_DONE			BIT(10)
++#define TMDSVALID_STABLE_CHG			BIT(1)
++
++#define AVPUNIT_0_INT_STATUS			0x5040
++#define AVPUNIT_0_INT_MASK_N			0x5044
++#define AVPUNIT_0_INT_CLEAR			0x5048
++#define AVPUNIT_0_INT_FORCE			0x504c
++#define CED_DYN_CNT_CH2_IRQ			BIT(22)
++#define CED_DYN_CNT_CH1_IRQ			BIT(21)
++#define CED_DYN_CNT_CH0_IRQ			BIT(20)
++#define AVPUNIT_1_INT_STATUS			0x5050
++#define DEFRAMER_VSYNC_THR_REACHED_IRQ		BIT(1)
++#define AVPUNIT_1_INT_MASK_N			0x5054
++#define DEFRAMER_VSYNC_THR_REACHED_MASK_N	BIT(1)
++#define DEFRAMER_VSYNC_MASK_N			BIT(0)
++#define AVPUNIT_1_INT_CLEAR			0x5058
++#define DEFRAMER_VSYNC_THR_REACHED_CLEAR	BIT(1)
++#define PKT_0_INT_STATUS			0x5080
++#define PKTDEC_ACR_CHG_IRQ			BIT(3)
++#define PKT_0_INT_MASK_N			0x5084
++#define PKTDEC_ACR_CHG_MASK_N			BIT(3)
++#define PKT_0_INT_CLEAR				0x5088
++#define PKT_1_INT_STATUS			0x5090
++#define PKT_1_INT_MASK_N			0x5094
++#define PKT_1_INT_CLEAR				0x5098
++#define PKT_2_INT_STATUS			0x50a0
++#define PKTDEC_ACR_RCV_IRQ			BIT(3)
++#define PKT_2_INT_MASK_N			0x50a4
++#define PKTDEC_AVIIF_RCV_IRQ			BIT(11)
++#define PKTDEC_ACR_RCV_MASK_N			BIT(3)
++#define PKT_2_INT_CLEAR				0x50a8
++#define PKTDEC_AVIIF_RCV_CLEAR			BIT(11)
++#define PKTDEC_ACR_RCV_CLEAR			BIT(3)
++#define SCDC_INT_STATUS				0x50c0
++#define SCDC_INT_MASK_N				0x50c4
++#define SCDC_INT_CLEAR				0x50c8
++#define SCDCTMDSCCFG_CHG			BIT(2)
++
++#define CEC_INT_STATUS				0x5100
++#define CEC_INT_MASK_N				0x5104
++#define CEC_INT_CLEAR				0x5108
++
++#endif
+diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c
+@@ -0,0 +1,285 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ *
++ * Author: Shunqing Chen <csq@rock-chips.com>
++ */
++
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++
++#include <media/cec.h>
++#include <media/cec-notifier.h>
++
++#include "snps_hdmirx.h"
++#include "snps_hdmirx_cec.h"
++
++static void hdmirx_cec_write(struct hdmirx_cec *cec, int reg, u32 val)
++{
++	cec->ops->write(cec->hdmirx, reg, val);
++}
++
++static u32 hdmirx_cec_read(struct hdmirx_cec *cec, int reg)
++{
++	return cec->ops->read(cec->hdmirx, reg);
++}
++
++static void hdmirx_cec_update_bits(struct hdmirx_cec *cec, int reg, u32 mask,
++				   u32 data)
++{
++	u32 val = hdmirx_cec_read(cec, reg) & ~mask;
++
++	val |= (data & mask);
++	hdmirx_cec_write(cec, reg, val);
++}
++
++static int hdmirx_cec_log_addr(struct cec_adapter *adap, u8 logical_addr)
++{
++	struct hdmirx_cec *cec = cec_get_drvdata(adap);
++
++	if (logical_addr == CEC_LOG_ADDR_INVALID)
++		cec->addresses = 0;
++	else
++		cec->addresses |= BIT(logical_addr) | BIT(15);
++
++	hdmirx_cec_write(cec, CEC_ADDR, cec->addresses);
++
++	return 0;
++}
++
++/* signal_free_time is handled by the Synopsys Designware
++ * HDMIRX Controller hardware.
++ */
++static int hdmirx_cec_transmit(struct cec_adapter *adap, u8 attempts,
++			       u32 signal_free_time, struct cec_msg *msg)
++{
++	struct hdmirx_cec *cec = cec_get_drvdata(adap);
++	u32 data[4] = {0};
++	int i, data_len, msg_len;
++
++	msg_len = msg->len;
++
++	hdmirx_cec_write(cec, CEC_TX_COUNT, msg_len - 1);
++	for (i = 0; i < msg_len; i++)
++		data[i / 4] |= msg->msg[i] << (i % 4) * 8;
++
++	data_len = DIV_ROUND_UP(msg_len, 4);
++
++	for (i = 0; i < data_len; i++)
++		hdmirx_cec_write(cec, CEC_TX_DATA3_0 + i * 4, data[i]);
++
++	hdmirx_cec_write(cec, CEC_TX_CONTROL, 0x1);
++
++	return 0;
++}
++
++static irqreturn_t hdmirx_cec_hardirq(int irq, void *data)
++{
++	struct cec_adapter *adap = data;
++	struct hdmirx_cec *cec = cec_get_drvdata(adap);
++	u32 stat = hdmirx_cec_read(cec, CEC_INT_STATUS);
++	irqreturn_t ret = IRQ_HANDLED;
++	u32 val;
++
++	if (!stat)
++		return IRQ_NONE;
++
++	hdmirx_cec_write(cec, CEC_INT_CLEAR, stat);
++
++	if (stat & CECTX_LINE_ERR) {
++		cec->tx_status = CEC_TX_STATUS_ERROR;
++		cec->tx_done = true;
++		ret = IRQ_WAKE_THREAD;
++	} else if (stat & CECTX_DONE) {
++		cec->tx_status = CEC_TX_STATUS_OK;
++		cec->tx_done = true;
++		ret = IRQ_WAKE_THREAD;
++	} else if (stat & CECTX_NACK) {
++		cec->tx_status = CEC_TX_STATUS_NACK;
++		cec->tx_done = true;
++		ret = IRQ_WAKE_THREAD;
++	} else if (stat & CECTX_ARBLOST) {
++		cec->tx_status = CEC_TX_STATUS_ARB_LOST;
++		cec->tx_done = true;
++		ret = IRQ_WAKE_THREAD;
++	}
++
++	if (stat & CECRX_EOM) {
++		unsigned int len, i;
++
++		val = hdmirx_cec_read(cec, CEC_RX_COUNT_STATUS);
++		/* rxbuffer locked status */
++		if ((val & 0x80))
++			return ret;
++
++		len = (val & 0xf) + 1;
++		if (len > sizeof(cec->rx_msg.msg))
++			len = sizeof(cec->rx_msg.msg);
++
++		for (i = 0; i < len; i++) {
++			if (!(i % 4))
++				val = hdmirx_cec_read(cec, CEC_RX_DATA3_0 + i / 4 * 4);
++			cec->rx_msg.msg[i] = (val >> ((i % 4) * 8)) & 0xff;
++		}
++
++		cec->rx_msg.len = len;
++		smp_wmb(); /* receive RX msg */
++		cec->rx_done = true;
++		hdmirx_cec_write(cec, CEC_LOCK_CONTROL, 0x1);
++
++		ret = IRQ_WAKE_THREAD;
++	}
++
++	return ret;
++}
++
++static irqreturn_t hdmirx_cec_thread(int irq, void *data)
++{
++	struct cec_adapter *adap = data;
++	struct hdmirx_cec *cec = cec_get_drvdata(adap);
++
++	if (cec->tx_done) {
++		cec->tx_done = false;
++		cec_transmit_attempt_done(adap, cec->tx_status);
++	}
++	if (cec->rx_done) {
++		cec->rx_done = false;
++		smp_rmb(); /* RX msg has been received */
++		cec_received_msg(adap, &cec->rx_msg);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static int hdmirx_cec_enable(struct cec_adapter *adap, bool enable)
++{
++	struct hdmirx_cec *cec = cec_get_drvdata(adap);
++
++	if (!enable) {
++		hdmirx_cec_write(cec, CEC_INT_MASK_N, 0);
++		hdmirx_cec_write(cec, CEC_INT_CLEAR, 0);
++		if (cec->ops->disable)
++			cec->ops->disable(cec->hdmirx);
++	} else {
++		unsigned int irqs;
++
++		hdmirx_cec_log_addr(cec->adap, CEC_LOG_ADDR_INVALID);
++		if (cec->ops->enable)
++			cec->ops->enable(cec->hdmirx);
++		hdmirx_cec_update_bits(cec, GLOBAL_SWENABLE, CEC_ENABLE, CEC_ENABLE);
++
++		irqs = CECTX_LINE_ERR | CECTX_NACK | CECRX_EOM | CECTX_DONE;
++		hdmirx_cec_write(cec, CEC_INT_MASK_N, irqs);
++	}
++
++	return 0;
++}
++
++static const struct cec_adap_ops hdmirx_cec_ops = {
++	.adap_enable = hdmirx_cec_enable,
++	.adap_log_addr = hdmirx_cec_log_addr,
++	.adap_transmit = hdmirx_cec_transmit,
++};
++
++static void hdmirx_cec_del(void *data)
++{
++	struct hdmirx_cec *cec = data;
++
++	cec_delete_adapter(cec->adap);
++}
++
++struct hdmirx_cec *snps_hdmirx_cec_register(struct hdmirx_cec_data *data)
++{
++	struct hdmirx_cec *cec;
++	unsigned int irqs;
++	int ret;
++
++	/*
++	 * Our device is just a convenience - we want to link to the real
++	 * hardware device here, so that userspace can see the association
++	 * between the HDMI hardware and its associated CEC chardev.
++	 */
++	cec = devm_kzalloc(data->dev, sizeof(*cec), GFP_KERNEL);
++	if (!cec)
++		return NULL;
++
++	cec->dev = data->dev;
++	cec->irq = data->irq;
++	cec->ops = data->ops;
++	cec->hdmirx = data->hdmirx;
++
++	hdmirx_cec_update_bits(cec, GLOBAL_SWENABLE, CEC_ENABLE, CEC_ENABLE);
++	hdmirx_cec_update_bits(cec, CEC_CONFIG, RX_AUTO_DRIVE_ACKNOWLEDGE,
++			       RX_AUTO_DRIVE_ACKNOWLEDGE);
++
++	hdmirx_cec_write(cec, CEC_TX_COUNT, 0);
++	hdmirx_cec_write(cec, CEC_INT_MASK_N, 0);
++	hdmirx_cec_write(cec, CEC_INT_CLEAR, ~0);
++
++	cec->adap = cec_allocate_adapter(&hdmirx_cec_ops, cec, "snps-hdmirx",
++					 CEC_CAP_LOG_ADDRS | CEC_CAP_TRANSMIT |
++					 CEC_CAP_RC | CEC_CAP_PASSTHROUGH |
++					 CEC_CAP_MONITOR_ALL,
++					 CEC_MAX_LOG_ADDRS);
++	if (IS_ERR(cec->adap)) {
++		dev_err(cec->dev, "cec adap allocate failed\n");
++		return NULL;
++	}
++
++	/* override the module pointer */
++	cec->adap->owner = THIS_MODULE;
++
++	ret = devm_add_action(cec->dev, hdmirx_cec_del, cec);
++	if (ret) {
++		cec_delete_adapter(cec->adap);
++		return NULL;
++	}
++
++	irq_set_status_flags(cec->irq, IRQ_NOAUTOEN);
++
++	ret = devm_request_threaded_irq(cec->dev, cec->irq,
++					hdmirx_cec_hardirq,
++					hdmirx_cec_thread, IRQF_ONESHOT,
++					"rk_hdmirx_cec", cec->adap);
++	if (ret) {
++		dev_err(cec->dev, "cec irq request failed\n");
++		return NULL;
++	}
++
++	cec->notify = cec_notifier_cec_adap_register(cec->dev,
++						     NULL, cec->adap);
++	if (!cec->notify) {
++		dev_err(cec->dev, "cec notify register failed\n");
++		return NULL;
++	}
++
++	ret = cec_register_adapter(cec->adap, cec->dev);
++	if (ret < 0) {
++		dev_err(cec->dev, "cec register adapter failed\n");
++		cec_unregister_adapter(cec->adap);
++		return NULL;
++	}
++
++	irqs = CECTX_LINE_ERR | CECTX_NACK | CECRX_EOM | CECTX_DONE;
++	hdmirx_cec_write(cec, CEC_INT_MASK_N, irqs);
++
++	/*
++	 * CEC documentation says we must not call cec_delete_adapter
++	 * after a successful call to cec_register_adapter().
++	 */
++	devm_remove_action(cec->dev, hdmirx_cec_del, cec);
++
++	enable_irq(cec->irq);
++
++	return cec;
++}
++
++void snps_hdmirx_cec_unregister(struct hdmirx_cec *cec)
++{
++	disable_irq(cec->irq);
++
++	cec_unregister_adapter(cec->adap);
++}
+diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h
+@@ -0,0 +1,44 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ *
++ * Author: Shunqing Chen <csq@rock-chips.com>
++ */
++
++#ifndef DW_HDMI_RX_CEC_H
++#define DW_HDMI_RX_CEC_H
++
++struct snps_hdmirx_dev;
++
++struct hdmirx_cec_ops {
++	void (*write)(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val);
++	u32 (*read)(struct snps_hdmirx_dev *hdmirx_dev, int reg);
++	void (*enable)(struct snps_hdmirx_dev *hdmirx);
++	void (*disable)(struct snps_hdmirx_dev *hdmirx);
++};
++
++struct hdmirx_cec_data {
++	struct snps_hdmirx_dev *hdmirx;
++	const struct hdmirx_cec_ops *ops;
++	struct device *dev;
++	int irq;
++};
++
++struct hdmirx_cec {
++	struct snps_hdmirx_dev *hdmirx;
++	struct device *dev;
++	const struct hdmirx_cec_ops *ops;
++	u32 addresses;
++	struct cec_adapter *adap;
++	struct cec_msg rx_msg;
++	unsigned int tx_status;
++	bool tx_done;
++	bool rx_done;
++	struct cec_notifier *notify;
++	int irq;
++};
++
++struct hdmirx_cec *snps_hdmirx_cec_register(struct hdmirx_cec_data *data);
++void snps_hdmirx_cec_unregister(struct hdmirx_cec *cec);
++
++#endif /* DW_HDMI_RX_CEC_H */
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Thu, 1 Aug 2024 16:47:35 +0300
+Subject: comment v4l2 error on hdmirx
+
+---
+ drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
+@@ -1180,7 +1180,7 @@ static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev)
+ 			break;
+ 
+ 		if (!tx_5v_power_present(hdmirx_dev)) {
+-			v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__);
++			//v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__);
+ 			return -1;
+ 		}
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-hdmirx.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-hdmirx.dtso
new file mode 100644
index 000000000000..b61eff3047be
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-hdmirx.dtso
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&hdmi_receiver_cma>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&hdmi_receiver>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/rk3588-rock-5b_dts_add_rfkill-bt.patch b/patch/kernel/archive/rockchip-rk3588-6.10/rk3588-rock-5b_dts_add_rfkill-bt.patch
new file mode 100644
index 000000000000..3a5c5919abc6
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.10/rk3588-rock-5b_dts_add_rfkill-bt.patch
@@ -0,0 +1,31 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: John Doe <john.doe@somewhere.on.planet>
+Date: Tue, 20 Aug 2024 22:47:51 +0000
+Subject: rk3588-rock-5b.dts: add rfkill-bt node to Radxa Rock5B board DT
+
+Signed-off-by: John Doe <john.doe@somewhere.on.planet>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -66,6 +66,13 @@ rfkill {
+ 		shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ 	};
+ 
++	rfkill-bt {
++		compatible = "rfkill-gpio";
++		label = "rfkill-m2-bt";
++		radio-type = "bluetooth";
++		shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
++	};
++
+ 	vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0000.patching_config.yaml b/patch/kernel/archive/rockchip-rk3588-6.11/0000.patching_config.yaml
new file mode 100644
index 000000000000..2a2b52cbc6ca
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0000.patching_config.yaml
@@ -0,0 +1,47 @@
+config: # This is file 'patch/kernel/rockchip-rk3588-edge/0000.patching_config.yaml'
+
+  # PATCH NUMBERING INFO
+  #
+  # Patches should be ordered in such a way that general kernel patches are applied first, then SoC-related patches and at last board-specific patches
+  #
+  # Patch numbers in this folder are sorted by category:
+  #
+  # 000* for general patches
+  # 01** for GPU/HDMI related patches
+  # 08** for wireless patches
+  # 1*** for board specific patches:
+  # 101* for Rock-5B, 102* for Rock-5A and so on
+
+  # Just some info stuff; not used by the patching scripts
+  name: rockchip-rk3588-edge
+  kind: kernel
+  type: mainline # or: vendor
+  branch: linux-6.11.y
+  last-known-good-tag: v6.11-rc1
+  maintainers:
+    - { github: rpardini, name: Ricardo Pardini, email: ricardo@pardini.net, armbian-forum: rpardini }
+
+  # .dts files in these directories will be copied as-is to the build tree; later ones overwrite earlier ones.
+  # This is meant to provide a way to "add a board DTS" without having to null-patch them in.
+  dts-directories:
+    - { source: "dt", target: "arch/arm64/boot/dts/rockchip" }
+
+  # every file in these directories will be copied as-is to the build tree; later ones overwrite earlier ones
+  # This is meant as a way to have overlays, bare, in a directory, without having to null-patch them in.
+  # @TODO need a solution to auto-Makefile the overlays as well
+  overlay-directories:
+    - { source: "overlay", target: "arch/arm64/boot/dts/rockchip/overlay" }
+
+  # the Makefile in each of these directories will be magically patched to include the dts files copied
+  #  or patched-in; overlay subdir will be included "-y" if it exists.
+  # No more Makefile patching needed, yay!
+  auto-patch-dt-makefile:
+    - { directory: "arch/arm64/boot/dts/rockchip", config-var: "CONFIG_ARCH_ROCKCHIP" }
+
+  # configuration for when applying patches to git / auto-rewriting patches (development cycle helpers)
+  patches-to-git:
+    do-not-commit-files:
+      - "MAINTAINERS" # constant churn, drop them. sorry.
+      - "Documentation/devicetree/bindings/arm/rockchip.yaml" # constant churn, conflicts on every bump, drop it. sorry.
+    do-not-commit-regexes: # Python-style regexes
+      - "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9]+)/Makefile$" # ignore DT Makefile patches, we've an auto-patcher now
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0001-general-add-overlay-support.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0001-general-add-overlay-support.patch
new file mode 100644
index 000000000000..1b42e27aaab9
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0001-general-add-overlay-support.patch
@@ -0,0 +1,69 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 2 Jun 2024 21:53:01 +0200
+Subject: compile .scr and install overlays in right path
+
+---
+ scripts/Makefile.dtbinst | 13 +++++++++-
+ scripts/Makefile.lib     |  8 +++++-
+ 2 files changed, 19 insertions(+), 2 deletions(-)
+
+diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
+index 111111111111..222222222222 100644
+--- a/scripts/Makefile.dtbinst
++++ b/scripts/Makefile.dtbinst
+@@ -33,7 +33,18 @@ endef
+ 
+ $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d))))
+ 
+-dtbs := $(notdir $(dtbs))
++# Very convoluted way to flatten all the device tree
++# directories, but keep the "/overlay/" directory
++
++# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip)
++topmost_dir = $(firstword $(subst /, ,$(dtbs)))
++# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir"
++dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs)))
++# collect the non-overlay dtbs
++dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs))
++# compose the dtbs variable flattening all the non-overlays entries
++# and appending the overlays entries
++dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays)
+ 
+ endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL
+ 
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 111111111111..222222222222 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -402,7 +402,7 @@ $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE
+ 
+ quiet_cmd_dtc = DTC     $@
+ cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+-	$(DTC) -o $@ -b 0 \
++	$(DTC) -@ -o $@ -b 0 \
+ 		$(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \
+ 		-d $(depfile).dtc.tmp $(dtc-tmp) ; \
+ 	cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+@@ -438,12 +438,18 @@ quiet_cmd_dtb = $(quiet_cmd_dtc)
+       cmd_dtb = $(cmd_dtc)
+ endif
+ 
++quiet_cmd_scr = MKIMAGE $@
++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
++
+ $(obj)/%.dtb: $(obj)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE
+ 	$(call if_changed_dep,dtb)
+ 
+ $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
+ 	$(call if_changed_dep,dtc)
+ 
++$(obj)/%.scr: $(src)/%.scr-cmd FORCE
++	$(call if_changed,scr)
++
+ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+ 
+ # Bzip2
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0010-fix-clk-divisions.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0010-fix-clk-divisions.patch
new file mode 100644
index 000000000000..25c4a67db09b
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0010-fix-clk-divisions.patch
@@ -0,0 +1,142 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 24 Oct 2023 16:09:35 +0200
+Subject: math.h: add DIV_ROUND_UP_NO_OVERFLOW
+
+Add a new DIV_ROUND_UP helper, which cannot overflow when
+big numbers are being used.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ include/linux/math.h | 11 ++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/include/linux/math.h b/include/linux/math.h
+index 111111111111..222222222222 100644
+--- a/include/linux/math.h
++++ b/include/linux/math.h
+@@ -36,6 +36,17 @@
+ 
+ #define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
+ 
++/**
++ * DIV_ROUND_UP_NO_OVERFLOW - divide two numbers and always round up
++ * @n: numerator / dividend
++ * @d: denominator / divisor
++ *
++ * This functions does the same as DIV_ROUND_UP, but internally uses a
++ * division and a modulo operation instead of math tricks. This way it
++ * avoids overflowing when handling big numbers.
++ */
++#define DIV_ROUND_UP_NO_OVERFLOW(n, d) (((n) / (d)) + !!((n) % (d)))
++
+ #define DIV_ROUND_DOWN_ULL(ll, d) \
+ 	({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
+ 
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 24 Oct 2023 16:13:50 +0200
+Subject: clk: divider: Fix divisor masking on 64 bit platforms
+
+The clock framework handles clock rates as "unsigned long", so u32 on
+32-bit architectures and u64 on 64-bit architectures.
+
+The current code casts the dividend to u64 on 32-bit to avoid a
+potential overflow. For example DIV_ROUND_UP(3000000000, 1500000000)
+= (3.0G + 1.5G - 1) / 1.5G = = OVERFLOW / 1.5G, which has been
+introduced in commit 9556f9dad8f5 ("clk: divider: handle integer overflow
+when dividing large clock rates").
+
+On 64 bit platforms this masks the divisor, so that only the lower
+32 bit are used. Thus requesting a frequency >= 4.3GHz results
+in incorrect values. For example requesting 4300000000 (4.3 GHz) will
+effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX)
+is a bit of a special case, since that still returns correct values as
+long as the parent clock is below 8.5 GHz.
+
+Fix this by switching to DIV_ROUND_UP_NO_OVERFLOW, which cannot
+overflow. This avoids any requirements on the arguments (except
+that divisor should not be 0 obviously).
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/clk/clk-divider.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
+index 111111111111..222222222222 100644
+--- a/drivers/clk/clk-divider.c
++++ b/drivers/clk/clk-divider.c
+@@ -220,7 +220,7 @@ static int _div_round_up(const struct clk_div_table *table,
+ 			 unsigned long parent_rate, unsigned long rate,
+ 			 unsigned long flags)
+ {
+-	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
++	int div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
+ 
+ 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ 		div = __roundup_pow_of_two(div);
+@@ -237,7 +237,7 @@ static int _div_round_closest(const struct clk_div_table *table,
+ 	int up, down;
+ 	unsigned long up_rate, down_rate;
+ 
+-	up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
++	up = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
+ 	down = parent_rate / rate;
+ 
+ 	if (flags & CLK_DIVIDER_POWER_OF_TWO) {
+@@ -473,7 +473,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
+ {
+ 	unsigned int div, value;
+ 
+-	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
++	div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
+ 
+ 	if (!_is_valid_div(table, div, flags))
+ 		return -EINVAL;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 24 Oct 2023 18:09:57 +0200
+Subject: clk: composite: replace open-coded abs_diff()
+
+Replace the open coded abs_diff() with the existing helper function.
+
+Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/clk/clk-composite.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
+index 111111111111..222222222222 100644
+--- a/drivers/clk/clk-composite.c
++++ b/drivers/clk/clk-composite.c
+@@ -6,6 +6,7 @@
+ #include <linux/clk-provider.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
++#include <linux/math.h>
+ #include <linux/slab.h>
+ 
+ static u8 clk_composite_get_parent(struct clk_hw *hw)
+@@ -119,10 +120,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,
+ 			if (ret)
+ 				continue;
+ 
+-			if (req->rate >= tmp_req.rate)
+-				rate_diff = req->rate - tmp_req.rate;
+-			else
+-				rate_diff = tmp_req.rate - req->rate;
++			rate_diff = abs_diff(req->rate, tmp_req.rate);
+ 
+ 			if (!rate_diff || !req->best_parent_hw
+ 				       || best_rate_diff > rate_diff) {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0011-irqchip-fix-its-timeout-issue.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0011-irqchip-fix-its-timeout-issue.patch
new file mode 100644
index 000000000000..bcea28c349cb
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0011-irqchip-fix-its-timeout-issue.patch
@@ -0,0 +1,214 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Fri, 11 Aug 2023 17:56:00 +0300
+Subject: irqchip/irq-gic-v3-its: fix its timeout issue for rk35xx boards
+
+---
+ drivers/irqchip/irq-gic-v3-its.c | 79 +++++++++-
+ 1 file changed, 72 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
+index 111111111111..222222222222 100644
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -164,6 +164,7 @@ struct its_device {
+ 	struct its_node		*its;
+ 	struct event_lpi_map	event_map;
+ 	void			*itt;
++	u32			itt_sz;
+ 	u32			nr_ites;
+ 	u32			device_id;
+ 	bool			shared;
+@@ -2186,6 +2187,9 @@ static void gic_reset_prop_table(void *va)
+ static struct page *its_allocate_prop_table(gfp_t gfp_flags)
+ {
+ 	struct page *prop_page;
++	
++	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++		gfp_flags |= GFP_DMA32;
+ 
+ 	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
+ 	if (!prop_page)
+@@ -2310,6 +2314,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
+ 	u32 alloc_pages, psz;
+ 	struct page *page;
+ 	void *base;
++	gfp_t gfp_flags;
+ 
+ 	psz = baser->psz;
+ 	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
+@@ -2321,7 +2326,11 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
+ 		order = get_order(GITS_BASER_PAGES_MAX * psz);
+ 	}
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
++	gfp_flags = GFP_KERNEL | __GFP_ZERO;
++	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++		gfp_flags |= GFP_DMA32;
++	
++	page = alloc_pages_node(its->numa_node, gfp_flags, order);
+ 	if (!page)
+ 		return -ENOMEM;
+ 
+@@ -2371,6 +2380,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
+ 	its_write_baser(its, baser, val);
+ 	tmp = baser->val;
+ 
++	if (of_machine_is_compatible("rockchip,rk3568") ||
++	     of_machine_is_compatible("rockchip,rk3566") ||
++	     of_machine_is_compatible("rockchip,rk3588")) {
++		if (tmp & GITS_BASER_SHAREABILITY_MASK)
++			tmp &= ~GITS_BASER_SHAREABILITY_MASK;
++		else
++			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
++	}
++
+ 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
+ 		/*
+ 		 * Shareability didn't stick. Just use
+@@ -2960,7 +2978,9 @@ static int its_alloc_collections(struct its_node *its)
+ static struct page *its_allocate_pending_table(gfp_t gfp_flags)
+ {
+ 	struct page *pend_page;
+-
++	
++	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++		gfp_flags |= GFP_DMA32;
+ 	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
+ 				get_order(LPI_PENDBASE_SZ));
+ 	if (!pend_page)
+@@ -3119,6 +3139,11 @@ static void its_cpu_init_lpis(void)
+ 	if (!rdists_support_shareable())
+ 		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+ 
++	if (of_machine_is_compatible("rockchip,rk3568") ||
++	     of_machine_is_compatible("rockchip,rk3566") ||
++	     of_machine_is_compatible("rockchip,rk3588"))
++		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
++
+ 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
+ 			/*
+@@ -3146,6 +3171,11 @@ static void its_cpu_init_lpis(void)
+ 	if (!rdists_support_shareable())
+ 		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
+ 
++	if (of_machine_is_compatible("rockchip,rk3568") ||
++	     of_machine_is_compatible("rockchip,rk3566") ||
++	     of_machine_is_compatible("rockchip,rk3588"))
++		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
++
+ 	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
+ 		/*
+ 		 * The HW reports non-shareable, we must remove the
+@@ -3309,7 +3339,11 @@ static bool its_alloc_table_entry(struct its_node *its,
+ 
+ 	/* Allocate memory for 2nd level table */
+ 	if (!table[idx]) {
+-		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++		gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
++
++		if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++			gfp_flags |= GFP_DMA32;
++		page = alloc_pages_node(its->numa_node, gfp_flags,
+ 					get_order(baser->psz));
+ 		if (!page)
+ 			return false;
+@@ -3398,6 +3432,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
+ 	int nr_lpis;
+ 	int nr_ites;
+ 	int sz;
++	gfp_t gfp_flags;
+ 
+ 	if (!its_alloc_device_table(its, dev_id))
+ 		return NULL;
+@@ -3413,7 +3448,15 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
+ 	nr_ites = max(2, nvecs);
+ 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
+ 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
+-	itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
++	gfp_flags = GFP_KERNEL;
++	
++	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) {
++		gfp_flags |= GFP_DMA32;
++		itt = (void *)__get_free_pages(gfp_flags, get_order(sz));
++	} else {
++		itt = kzalloc_node(sz, gfp_flags, its->numa_node);
++	}
++
+ 	if (alloc_lpis) {
+ 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
+ 		if (lpi_map)
+@@ -3427,7 +3470,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
+ 
+ 	if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
+ 		kfree(dev);
+-		kfree(itt);
++
++		if (of_machine_is_compatible("rockchip,rk3568") ||
++		    of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++			free_pages((unsigned long)itt, get_order(sz));
++		else
++			kfree(itt);
++
+ 		bitmap_free(lpi_map);
+ 		kfree(col_map);
+ 		return NULL;
+@@ -3437,6 +3486,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
+ 
+ 	dev->its = its;
+ 	dev->itt = itt;
++	dev->itt_sz = sz;
+ 	dev->nr_ites = nr_ites;
+ 	dev->event_map.lpi_map = lpi_map;
+ 	dev->event_map.col_map = col_map;
+@@ -3464,7 +3514,13 @@ static void its_free_device(struct its_device *its_dev)
+ 	list_del(&its_dev->entry);
+ 	raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
+ 	kfree(its_dev->event_map.col_map);
+-	kfree(its_dev->itt);
++	
++	if (of_machine_is_compatible("rockchip,rk3568") ||
++	    of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++		free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz));
++	else
++		kfree(its_dev->itt);
++	
+ 	kfree(its_dev);
+ }
+ 
+@@ -5079,6 +5135,7 @@ static int __init its_probe_one(struct its_node *its)
+ 	struct page *page;
+ 	u32 ctlr;
+ 	int err;
++	gfp_t gfp_flags;
+ 
+ 	its_enable_quirks(its);
+ 
+@@ -5112,7 +5169,10 @@ static int __init its_probe_one(struct its_node *its)
+ 		}
+ 	}
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++	gfp_flags = GFP_KERNEL | __GFP_ZERO;
++	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++		gfp_flags |= GFP_DMA32;
++	page = alloc_pages_node(its->numa_node, gfp_flags,
+ 				get_order(ITS_CMD_QUEUE_SZ));
+ 	if (!page) {
+ 		err = -ENOMEM;
+@@ -5141,6 +5201,11 @@ static int __init its_probe_one(struct its_node *its)
+ 	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
+ 		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
+ 
++	if (of_machine_is_compatible("rockchip,rk3568") ||
++	     of_machine_is_compatible("rockchip,rk3566") ||
++	     of_machine_is_compatible("rockchip,rk3588"))
++		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
++
+ 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
+ 			/*
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0024-RK3588-Add-Crypto-Support.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0024-RK3588-Add-Crypto-Support.patch
new file mode 100644
index 000000000000..636d11ec130f
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0024-RK3588-Add-Crypto-Support.patch
@@ -0,0 +1,2322 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe@baylibre.com>
+Date: Tue, 7 Nov 2023 15:55:27 +0000
+Subject: dt-bindings: crypto: add support for rockchip,crypto-rk3588
+
+Add device tree binding documentation for the Rockchip cryptographic
+offloader V2.
+
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+---
+ Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml | 65 ++++++++++
+ 1 file changed, 65 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
+@@ -0,0 +1,65 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/crypto/rockchip,rk3588-crypto.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip cryptographic offloader V2
++
++maintainers:
++  - Corentin Labbe <clabbe@baylibre.com>
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk3568-crypto
++      - rockchip,rk3588-crypto
++
++  reg:
++    maxItems: 1
++
++  interrupts:
++    maxItems: 1
++
++  clocks:
++    minItems: 3
++
++  clock-names:
++    items:
++      - const: core
++      - const: a
++      - const: h
++
++  resets:
++    minItems: 1
++
++  reset-names:
++    items:
++      - const: core
++
++required:
++  - compatible
++  - reg
++  - interrupts
++  - clocks
++  - clock-names
++  - resets
++  - reset-names
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
++    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
++    crypto@fe370000 {
++      compatible = "rockchip,rk3588-crypto";
++      reg = <0xfe370000 0x4000>;
++      interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
++      clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>,
++               <&scmi_clk SCMI_HCLK_SECURE_NS>;
++      clock-names = "core", "a", "h";
++      resets = <&scmi_reset SRST_CRYPTO_CORE>;
++      reset-names = "core";
++    };
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe@baylibre.com>
+Date: Tue, 7 Nov 2023 15:55:30 +0000
+Subject: ARM64: dts: rk356x: add crypto node
+
+Both RK3566 and RK3568 have a crypto IP handled by the rk3588 crypto driver so adds a
+node for it.
+
+Tested-by: Ricardo Pardini <ricardo@pardini.net>
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1113,6 +1113,18 @@ sdhci: mmc@fe310000 {
+ 		status = "disabled";
+ 	};
+ 
++	crypto: crypto@fe380000 {
++		compatible = "rockchip,rk3568-crypto";
++		reg = <0x0 0xfe380000 0x0 0x2000>;
++		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>,
++			 <&cru CLK_CRYPTO_NS_CORE>;
++		clock-names = "aclk", "hclk", "core";
++		resets = <&cru SRST_CRYPTO_NS_CORE>;
++		reset-names = "core";
++		status = "okay";
++	};
++
+ 	i2s0_8ch: i2s@fe400000 {
+ 		compatible = "rockchip,rk3568-i2s-tdm";
+ 		reg = <0x0 0xfe400000 0x0 0x1000>;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Fri, 2 Aug 2024 00:05:59 +0300
+Subject: arm64: dts: rockchip: rk3588: enable crypto node
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 11 ++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1763,6 +1763,17 @@ sdhci: mmc@fe2e0000 {
+ 		status = "disabled";
+ 	};
+ 
++	crypto: crypto@fe370000 {
++		compatible = "rockchip,rk3588-crypto";
++		reg = <0x0 0xfe370000 0x0 0x2000>;
++		interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>,
++			 <&scmi_clk SCMI_HCLK_SECURE_NS>;
++		clock-names = "core", "aclk", "hclk";
++		resets = <&scmi_reset SRST_CRYPTO_CORE>;
++		reset-names = "core";
++	};
++
+ 	i2s0_8ch: i2s@fe470000 {
+ 		compatible = "rockchip,rk3588-i2s-tdm";
+ 		reg = <0x0 0xfe470000 0x0 0x1000>;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe@baylibre.com>
+Date: Tue, 7 Nov 2023 15:55:31 +0000
+Subject: reset: rockchip: secure reset must be used by SCMI
+
+While working on the rk3588 crypto driver, I loose lot of time
+understanding why resetting the IP failed.
+This is due to RK3588_SECURECRU_RESET_OFFSET being in the secure world,
+so impossible to operate on it from the kernel.
+All resets in this block must be handled via SCMI call.
+
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+---
+ drivers/clk/rockchip/rst-rk3588.c               | 42 ------
+ include/dt-bindings/reset/rockchip,rk3588-cru.h | 68 +++++-----
+ 2 files changed, 34 insertions(+), 76 deletions(-)
+
+diff --git a/drivers/clk/rockchip/rst-rk3588.c b/drivers/clk/rockchip/rst-rk3588.c
+index 111111111111..222222222222 100644
+--- a/drivers/clk/rockchip/rst-rk3588.c
++++ b/drivers/clk/rockchip/rst-rk3588.c
+@@ -16,9 +16,6 @@
+ /* 0xFD7C8000 + 0x0A00 */
+ #define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
+ 
+-/* 0xFD7D0000 + 0x0A00 */
+-#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
+-
+ /* 0xFD7F0000 + 0x0A00 */
+ #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
+ 
+@@ -807,45 +804,6 @@ static const int rk3588_register_offset[] = {
+ 	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4),
+ 	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5),
+ 	RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6),
+-
+-	/* SECURECRU_SOFTRST_CON00 */
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15),
+-
+-	/* SECURECRU_SOFTRST_CON01 */
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15),
+-
+-	/* SECURECRU_SOFTRST_CON02 */
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15),
+-
+-	/* SECURECRU_SOFTRST_CON03 */
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6),
+ };
+ 
+ void rk3588_rst_init(struct device_node *np, void __iomem *reg_base)
+diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h
+index 111111111111..222222222222 100644
+--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
++++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
+@@ -716,40 +716,40 @@
+ #define SRST_P_GPIO0			627
+ #define SRST_GPIO0			628
+ 
+-#define SRST_A_SECURE_NS_BIU		629
+-#define SRST_H_SECURE_NS_BIU		630
+-#define SRST_A_SECURE_S_BIU		631
+-#define SRST_H_SECURE_S_BIU		632
+-#define SRST_P_SECURE_S_BIU		633
+-#define SRST_CRYPTO_CORE		634
+-
+-#define SRST_CRYPTO_PKA			635
+-#define SRST_CRYPTO_RNG			636
+-#define SRST_A_CRYPTO			637
+-#define SRST_H_CRYPTO			638
+-#define SRST_KEYLADDER_CORE		639
+-#define SRST_KEYLADDER_RNG		640
+-#define SRST_A_KEYLADDER		641
+-#define SRST_H_KEYLADDER		642
+-#define SRST_P_OTPC_S			643
+-#define SRST_OTPC_S			644
+-#define SRST_WDT_S			645
+-
+-#define SRST_T_WDT_S			646
+-#define SRST_H_BOOTROM			647
+-#define SRST_A_DCF			648
+-#define SRST_P_DCF			649
+-#define SRST_H_BOOTROM_NS		650
+-#define SRST_P_KEYLADDER		651
+-#define SRST_H_TRNG_S			652
+-
+-#define SRST_H_TRNG_NS			653
+-#define SRST_D_SDMMC_BUFFER		654
+-#define SRST_H_SDMMC			655
+-#define SRST_H_SDMMC_BUFFER		656
+-#define SRST_SDMMC			657
+-#define SRST_P_TRNG_CHK			658
+-#define SRST_TRNG_S			659
++#define SRST_A_SECURE_NS_BIU		10
++#define SRST_H_SECURE_NS_BIU		11
++#define SRST_A_SECURE_S_BIU		12
++#define SRST_H_SECURE_S_BIU		13
++#define SRST_P_SECURE_S_BIU		14
++#define SRST_CRYPTO_CORE		15
++
++#define SRST_CRYPTO_PKA			16
++#define SRST_CRYPTO_RNG			17
++#define SRST_A_CRYPTO			18
++#define SRST_H_CRYPTO			19
++#define SRST_KEYLADDER_CORE		25
++#define SRST_KEYLADDER_RNG		26
++#define SRST_A_KEYLADDER		27
++#define SRST_H_KEYLADDER		28
++#define SRST_P_OTPC_S			29
++#define SRST_OTPC_S			30
++#define SRST_WDT_S			31
++
++#define SRST_T_WDT_S			32
++#define SRST_H_BOOTROM			33
++#define SRST_A_DCF			34
++#define SRST_P_DCF			35
++#define SRST_H_BOOTROM_NS		37
++#define SRST_P_KEYLADDER		46
++#define SRST_H_TRNG_S			47
++
++#define SRST_H_TRNG_NS			48
++#define SRST_D_SDMMC_BUFFER		49
++#define SRST_H_SDMMC			50
++#define SRST_H_SDMMC_BUFFER		51
++#define SRST_SDMMC			52
++#define SRST_P_TRNG_CHK			53
++#define SRST_TRNG_S			54
+ 
+ #define SRST_A_HDMIRX_BIU		660
+ 
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe@baylibre.com>
+Date: Tue, 7 Nov 2023 15:55:32 +0000
+Subject: crypto: rockchip: add rk3588 driver
+
+RK3588 have a new crypto IP, this patch adds basic support for it.
+Only hashes and cipher are handled for the moment.
+
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+---
+ drivers/crypto/Kconfig                        |  29 +
+ drivers/crypto/rockchip/Makefile              |   5 +
+ drivers/crypto/rockchip/rk2_crypto.c          | 738 ++++++++++
+ drivers/crypto/rockchip/rk2_crypto.h          | 246 ++++
+ drivers/crypto/rockchip/rk2_crypto_ahash.c    | 344 +++++
+ drivers/crypto/rockchip/rk2_crypto_skcipher.c | 576 ++++++++
+ 6 files changed, 1938 insertions(+)
+
+diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -653,6 +653,35 @@ config CRYPTO_DEV_TEGRA
+ 	  Select this to enable Tegra Security Engine which accelerates various
+ 	  AES encryption/decryption and HASH algorithms.
+ 
++config CRYPTO_DEV_ROCKCHIP2
++	tristate "Rockchip's cryptographic offloader V2"
++	depends on OF && ARCH_ROCKCHIP
++	depends on PM
++	select CRYPTO_ECB
++	select CRYPTO_CBC
++	select CRYPTO_AES
++	select CRYPTO_MD5
++	select CRYPTO_SHA1
++	select CRYPTO_SHA256
++	select CRYPTO_SHA512
++	select CRYPTO_SM3_GENERIC
++	select CRYPTO_HASH
++	select CRYPTO_SKCIPHER
++	select CRYPTO_ENGINE
++
++	help
++	  This driver interfaces with the hardware crypto offloader present
++	  on RK3566, RK3568 and RK3588.
++
++config CRYPTO_DEV_ROCKCHIP2_DEBUG
++	bool "Enable Rockchip V2 crypto stats"
++	depends on CRYPTO_DEV_ROCKCHIP2
++	depends on DEBUG_FS
++	help
++	  Say y to enable Rockchip crypto debug stats.
++	  This will create /sys/kernel/debug/rk3588_crypto/stats for displaying
++	  the number of requests per algorithm and other internal stats.
++
+ config CRYPTO_DEV_ZYNQMP_AES
+ 	tristate "Support for Xilinx ZynqMP AES hw accelerator"
+ 	depends on ZYNQMP_FIRMWARE || COMPILE_TEST
+diff --git a/drivers/crypto/rockchip/Makefile b/drivers/crypto/rockchip/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/crypto/rockchip/Makefile
++++ b/drivers/crypto/rockchip/Makefile
+@@ -3,3 +3,8 @@ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o
+ rk_crypto-objs := rk3288_crypto.o \
+ 		  rk3288_crypto_skcipher.o \
+ 		  rk3288_crypto_ahash.o
++
++obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP2) += rk_crypto2.o
++rk_crypto2-objs := rk2_crypto.o \
++		  rk2_crypto_skcipher.o \
++		  rk2_crypto_ahash.o
+diff --git a/drivers/crypto/rockchip/rk2_crypto.c b/drivers/crypto/rockchip/rk2_crypto.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/crypto/rockchip/rk2_crypto.c
+@@ -0,0 +1,738 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * hardware cryptographic offloader for RK3568/RK3588 SoC
++ *
++ * Copyright (c) 2022-2023, Corentin Labbe <clabbe@baylibre.com>
++ */
++
++#include "rk2_crypto.h"
++#include <linux/clk.h>
++#include <linux/crypto.h>
++#include <linux/dma-mapping.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/reset.h>
++
++static struct rockchip_ip rocklist = {
++	.dev_list = LIST_HEAD_INIT(rocklist.dev_list),
++	.lock = __SPIN_LOCK_UNLOCKED(rocklist.lock),
++};
++
++struct rk2_crypto_dev *get_rk2_crypto(void)
++{
++	struct rk2_crypto_dev *first;
++
++	spin_lock(&rocklist.lock);
++	first = list_first_entry_or_null(&rocklist.dev_list,
++					 struct rk2_crypto_dev, list);
++	list_rotate_left(&rocklist.dev_list);
++	spin_unlock(&rocklist.lock);
++	return first;
++}
++
++static const struct rk2_variant rk3568_variant = {
++	.num_clks = 3,
++};
++
++static const struct rk2_variant rk3588_variant = {
++	.num_clks = 3,
++};
++
++static int rk2_crypto_get_clks(struct rk2_crypto_dev *dev)
++{
++	int i, j, err;
++	unsigned long cr;
++
++	dev->num_clks = devm_clk_bulk_get_all(dev->dev, &dev->clks);
++	if (dev->num_clks < dev->variant->num_clks) {
++		dev_err(dev->dev, "Missing clocks, got %d instead of %d\n",
++			dev->num_clks, dev->variant->num_clks);
++		return -EINVAL;
++	}
++
++	for (i = 0; i < dev->num_clks; i++) {
++		cr = clk_get_rate(dev->clks[i].clk);
++		for (j = 0; j < ARRAY_SIZE(dev->variant->rkclks); j++) {
++			if (dev->variant->rkclks[j].max == 0)
++				continue;
++			if (strcmp(dev->variant->rkclks[j].name, dev->clks[i].id))
++				continue;
++			if (cr > dev->variant->rkclks[j].max) {
++				err = clk_set_rate(dev->clks[i].clk,
++						   dev->variant->rkclks[j].max);
++				if (err)
++					dev_err(dev->dev, "Fail downclocking %s from %lu to %lu\n",
++						dev->variant->rkclks[j].name, cr,
++						dev->variant->rkclks[j].max);
++				else
++					dev_info(dev->dev, "Downclocking %s from %lu to %lu\n",
++						 dev->variant->rkclks[j].name, cr,
++						 dev->variant->rkclks[j].max);
++			}
++		}
++	}
++	return 0;
++}
++
++static int rk2_crypto_enable_clk(struct rk2_crypto_dev *dev)
++{
++	int err;
++
++	err = clk_bulk_prepare_enable(dev->num_clks, dev->clks);
++	if (err)
++		dev_err(dev->dev, "Could not enable clock clks\n");
++
++	return err;
++}
++
++static void rk2_crypto_disable_clk(struct rk2_crypto_dev *dev)
++{
++	clk_bulk_disable_unprepare(dev->num_clks, dev->clks);
++}
++
++/*
++ * Power management strategy: The device is suspended until a request
++ * is handled. For avoiding suspend/resume yoyo, the autosuspend is set to 2s.
++ */
++static int rk2_crypto_pm_suspend(struct device *dev)
++{
++	struct rk2_crypto_dev *rkdev = dev_get_drvdata(dev);
++
++	rk2_crypto_disable_clk(rkdev);
++	reset_control_assert(rkdev->rst);
++
++	return 0;
++}
++
++static int rk2_crypto_pm_resume(struct device *dev)
++{
++	struct rk2_crypto_dev *rkdev = dev_get_drvdata(dev);
++	int ret;
++
++	ret = rk2_crypto_enable_clk(rkdev);
++	if (ret)
++		return ret;
++
++	reset_control_deassert(rkdev->rst);
++	return 0;
++}
++
++static const struct dev_pm_ops rk2_crypto_pm_ops = {
++	SET_RUNTIME_PM_OPS(rk2_crypto_pm_suspend, rk2_crypto_pm_resume, NULL)
++};
++
++static int rk2_crypto_pm_init(struct rk2_crypto_dev *rkdev)
++{
++	int err;
++
++	pm_runtime_use_autosuspend(rkdev->dev);
++	pm_runtime_set_autosuspend_delay(rkdev->dev, 2000);
++
++	err = pm_runtime_set_suspended(rkdev->dev);
++	if (err)
++		return err;
++	pm_runtime_enable(rkdev->dev);
++	return err;
++}
++
++static void rk2_crypto_pm_exit(struct rk2_crypto_dev *rkdev)
++{
++	pm_runtime_disable(rkdev->dev);
++}
++
++static irqreturn_t rk2_crypto_irq_handle(int irq, void *dev_id)
++{
++	struct rk2_crypto_dev *rkc  = platform_get_drvdata(dev_id);
++	u32 v;
++
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_INT_ST);
++	writel(v, rkc->reg + RK2_CRYPTO_DMA_INT_ST);
++
++	rkc->status = 1;
++	if (v & 0xF8) {
++		dev_warn(rkc->dev, "DMA Error\n");
++		rkc->status = 0;
++	}
++	complete(&rkc->complete);
++
++	return IRQ_HANDLED;
++}
++
++static struct rk2_crypto_template rk2_crypto_algs[] = {
++	{
++		.type = CRYPTO_ALG_TYPE_SKCIPHER,
++		.rk2_mode = RK2_CRYPTO_AES_ECB,
++		.alg.skcipher.base = {
++			.base.cra_name		= "ecb(aes)",
++			.base.cra_driver_name	= "ecb-aes-rk2",
++			.base.cra_priority	= 300,
++			.base.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
++			.base.cra_blocksize	= AES_BLOCK_SIZE,
++			.base.cra_ctxsize	= sizeof(struct rk2_cipher_ctx),
++			.base.cra_alignmask	= 0x0f,
++			.base.cra_module	= THIS_MODULE,
++
++			.init			= rk2_cipher_tfm_init,
++			.exit			= rk2_cipher_tfm_exit,
++			.min_keysize		= AES_MIN_KEY_SIZE,
++			.max_keysize		= AES_MAX_KEY_SIZE,
++			.setkey			= rk2_aes_setkey,
++			.encrypt		= rk2_skcipher_encrypt,
++			.decrypt		= rk2_skcipher_decrypt,
++		},
++		.alg.skcipher.op = {
++			.do_one_request = rk2_cipher_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_SKCIPHER,
++		.rk2_mode = RK2_CRYPTO_AES_CBC,
++		.alg.skcipher.base = {
++			.base.cra_name		= "cbc(aes)",
++			.base.cra_driver_name	= "cbc-aes-rk2",
++			.base.cra_priority	= 300,
++			.base.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
++			.base.cra_blocksize	= AES_BLOCK_SIZE,
++			.base.cra_ctxsize	= sizeof(struct rk2_cipher_ctx),
++			.base.cra_alignmask	= 0x0f,
++			.base.cra_module	= THIS_MODULE,
++
++			.init			= rk2_cipher_tfm_init,
++			.exit			= rk2_cipher_tfm_exit,
++			.min_keysize		= AES_MIN_KEY_SIZE,
++			.max_keysize		= AES_MAX_KEY_SIZE,
++			.ivsize			= AES_BLOCK_SIZE,
++			.setkey			= rk2_aes_setkey,
++			.encrypt		= rk2_skcipher_encrypt,
++			.decrypt		= rk2_skcipher_decrypt,
++		},
++		.alg.skcipher.op = {
++			.do_one_request = rk2_cipher_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_SKCIPHER,
++		.rk2_mode = RK2_CRYPTO_AES_XTS,
++		.is_xts = true,
++		.alg.skcipher.base = {
++			.base.cra_name		= "xts(aes)",
++			.base.cra_driver_name	= "xts-aes-rk2",
++			.base.cra_priority	= 300,
++			.base.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
++			.base.cra_blocksize	= AES_BLOCK_SIZE,
++			.base.cra_ctxsize	= sizeof(struct rk2_cipher_ctx),
++			.base.cra_alignmask	= 0x0f,
++			.base.cra_module	= THIS_MODULE,
++
++			.init			= rk2_cipher_tfm_init,
++			.exit			= rk2_cipher_tfm_exit,
++			.min_keysize		= AES_MIN_KEY_SIZE * 2,
++			.max_keysize		= AES_MAX_KEY_SIZE * 2,
++			.ivsize			= AES_BLOCK_SIZE,
++			.setkey			= rk2_aes_xts_setkey,
++			.encrypt		= rk2_skcipher_encrypt,
++			.decrypt		= rk2_skcipher_decrypt,
++		},
++		.alg.skcipher.op = {
++			.do_one_request = rk2_cipher_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_MD5,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = MD5_DIGEST_SIZE,
++				.statesize = sizeof(struct md5_state),
++				.base = {
++					.cra_name = "md5",
++					.cra_driver_name = "rk2-md5",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_SHA1,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = SHA1_DIGEST_SIZE,
++				.statesize = sizeof(struct sha1_state),
++				.base = {
++					.cra_name = "sha1",
++					.cra_driver_name = "rk2-sha1",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = SHA1_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_SHA256,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = SHA256_DIGEST_SIZE,
++				.statesize = sizeof(struct sha256_state),
++				.base = {
++					.cra_name = "sha256",
++					.cra_driver_name = "rk2-sha256",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = SHA256_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_SHA384,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = SHA384_DIGEST_SIZE,
++				.statesize = sizeof(struct sha512_state),
++				.base = {
++					.cra_name = "sha384",
++					.cra_driver_name = "rk2-sha384",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = SHA384_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_SHA512,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = SHA512_DIGEST_SIZE,
++				.statesize = sizeof(struct sha512_state),
++				.base = {
++					.cra_name = "sha512",
++					.cra_driver_name = "rk2-sha512",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = SHA512_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_SM3,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = SM3_DIGEST_SIZE,
++				.statesize = sizeof(struct sm3_state),
++				.base = {
++					.cra_name = "sm3",
++					.cra_driver_name = "rk2-sm3",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = SM3_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++	},
++};
++
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG
++static int rk2_crypto_debugfs_stats_show(struct seq_file *seq, void *v)
++{
++	struct rk2_crypto_dev *rkc;
++	unsigned int i;
++
++	spin_lock(&rocklist.lock);
++	list_for_each_entry(rkc, &rocklist.dev_list, list) {
++		seq_printf(seq, "%s %s requests: %lu\n",
++			   dev_driver_string(rkc->dev), dev_name(rkc->dev),
++			   rkc->nreq);
++	}
++	spin_unlock(&rocklist.lock);
++
++	for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) {
++		if (!rk2_crypto_algs[i].dev)
++			continue;
++		switch (rk2_crypto_algs[i].type) {
++		case CRYPTO_ALG_TYPE_SKCIPHER:
++			seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n",
++				   rk2_crypto_algs[i].alg.skcipher.base.base.cra_driver_name,
++				   rk2_crypto_algs[i].alg.skcipher.base.base.cra_name,
++				   rk2_crypto_algs[i].stat_req, rk2_crypto_algs[i].stat_fb);
++			seq_printf(seq, "\tfallback due to length: %lu\n",
++				   rk2_crypto_algs[i].stat_fb_len);
++			seq_printf(seq, "\tfallback due to alignment: %lu\n",
++				   rk2_crypto_algs[i].stat_fb_align);
++			seq_printf(seq, "\tfallback due to SGs: %lu\n",
++				   rk2_crypto_algs[i].stat_fb_sgdiff);
++			break;
++		case CRYPTO_ALG_TYPE_AHASH:
++			seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n",
++				   rk2_crypto_algs[i].alg.hash.base.halg.base.cra_driver_name,
++				   rk2_crypto_algs[i].alg.hash.base.halg.base.cra_name,
++				   rk2_crypto_algs[i].stat_req, rk2_crypto_algs[i].stat_fb);
++			break;
++		}
++	}
++	return 0;
++}
++
++static int rk2_crypto_debugfs_info_show(struct seq_file *seq, void *d)
++{
++	struct rk2_crypto_dev *rkc;
++	u32 v;
++
++	spin_lock(&rocklist.lock);
++	list_for_each_entry(rkc, &rocklist.dev_list, list) {
++		v = readl(rkc->reg + RK2_CRYPTO_CLK_CTL);
++		seq_printf(seq, "CRYPTO_CLK_CTL %x\n", v);
++		v = readl(rkc->reg + RK2_CRYPTO_RST_CTL);
++		seq_printf(seq, "CRYPTO_RST_CTL %x\n", v);
++
++		v = readl(rkc->reg + CRYPTO_AES_VERSION);
++		seq_printf(seq, "CRYPTO_AES_VERSION %x\n", v);
++		if (v & BIT(17))
++			seq_puts(seq, "AES 192\n");
++
++		v = readl(rkc->reg + CRYPTO_DES_VERSION);
++		seq_printf(seq, "CRYPTO_DES_VERSION %x\n", v);
++		v = readl(rkc->reg + CRYPTO_SM4_VERSION);
++		seq_printf(seq, "CRYPTO_SM4_VERSION %x\n", v);
++		v = readl(rkc->reg + CRYPTO_HASH_VERSION);
++		seq_printf(seq, "CRYPTO_HASH_VERSION %x\n", v);
++		v = readl(rkc->reg + CRYPTO_HMAC_VERSION);
++		seq_printf(seq, "CRYPTO_HMAC_VERSION %x\n", v);
++	v = readl(rkc->reg + CRYPTO_RNG_VERSION);
++	seq_printf(seq, "CRYPTO_RNG_VERSION %x\n", v);
++	v = readl(rkc->reg + CRYPTO_PKA_VERSION);
++	seq_printf(seq, "CRYPTO_PKA_VERSION %x\n", v);
++	v = readl(rkc->reg + CRYPTO_CRYPTO_VERSION);
++	seq_printf(seq, "CRYPTO_CRYPTO_VERSION %x\n", v);
++	}
++	spin_unlock(&rocklist.lock);
++
++	return 0;
++}
++
++DEFINE_SHOW_ATTRIBUTE(rk2_crypto_debugfs_stats);
++DEFINE_SHOW_ATTRIBUTE(rk2_crypto_debugfs_info);
++
++#endif
++
++static void register_debugfs(struct rk2_crypto_dev *crypto_dev)
++{
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG
++	/* Ignore error of debugfs */
++	rocklist.dbgfs_dir = debugfs_create_dir("rk2_crypto", NULL);
++	rocklist.dbgfs_stats = debugfs_create_file("stats", 0440,
++						   rocklist.dbgfs_dir,
++						   &rocklist,
++						   &rk2_crypto_debugfs_stats_fops);
++	rocklist.dbgfs_stats = debugfs_create_file("info", 0440,
++						   rocklist.dbgfs_dir,
++						   &rocklist,
++						   &rk2_crypto_debugfs_info_fops);
++#endif
++}
++
++static int rk2_crypto_register(struct rk2_crypto_dev *rkc)
++{
++	unsigned int i, k;
++	int err = 0;
++
++	for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) {
++		rk2_crypto_algs[i].dev = rkc;
++		switch (rk2_crypto_algs[i].type) {
++		case CRYPTO_ALG_TYPE_SKCIPHER:
++			dev_info(rkc->dev, "Register %s as %s\n",
++				 rk2_crypto_algs[i].alg.skcipher.base.base.cra_name,
++				 rk2_crypto_algs[i].alg.skcipher.base.base.cra_driver_name);
++			err = crypto_engine_register_skcipher(&rk2_crypto_algs[i].alg.skcipher);
++			break;
++		case CRYPTO_ALG_TYPE_AHASH:
++			dev_info(rkc->dev, "Register %s as %s %d\n",
++				 rk2_crypto_algs[i].alg.hash.base.halg.base.cra_name,
++				 rk2_crypto_algs[i].alg.hash.base.halg.base.cra_driver_name, i);
++			err = crypto_engine_register_ahash(&rk2_crypto_algs[i].alg.hash);
++			break;
++		default:
++			dev_err(rkc->dev, "unknown algorithm\n");
++		}
++		if (err)
++			goto err_cipher_algs;
++	}
++	return 0;
++
++err_cipher_algs:
++	for (k = 0; k < i; k++) {
++		if (rk2_crypto_algs[k].type == CRYPTO_ALG_TYPE_SKCIPHER)
++			crypto_engine_unregister_skcipher(&rk2_crypto_algs[k].alg.skcipher);
++		else
++			crypto_engine_unregister_ahash(&rk2_crypto_algs[k].alg.hash);
++	}
++	return err;
++}
++
++static void rk2_crypto_unregister(void)
++{
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) {
++		if (rk2_crypto_algs[i].type == CRYPTO_ALG_TYPE_SKCIPHER)
++			crypto_engine_unregister_skcipher(&rk2_crypto_algs[i].alg.skcipher);
++		else
++			crypto_engine_unregister_ahash(&rk2_crypto_algs[i].alg.hash);
++	}
++}
++
++static const struct of_device_id crypto_of_id_table[] = {
++	{ .compatible = "rockchip,rk3568-crypto",
++	  .data = &rk3568_variant,
++	},
++	{ .compatible = "rockchip,rk3588-crypto",
++	  .data = &rk3588_variant,
++	},
++	{}
++};
++MODULE_DEVICE_TABLE(of, crypto_of_id_table);
++
++static int rk2_crypto_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct rk2_crypto_dev *rkc, *first;
++	int err = 0;
++
++	rkc = devm_kzalloc(&pdev->dev, sizeof(*rkc), GFP_KERNEL);
++	if (!rkc) {
++		err = -ENOMEM;
++		goto err_crypto;
++	}
++
++	rkc->dev = &pdev->dev;
++	platform_set_drvdata(pdev, rkc);
++
++	rkc->variant = of_device_get_match_data(&pdev->dev);
++	if (!rkc->variant) {
++		dev_err(&pdev->dev, "Missing variant\n");
++		return -EINVAL;
++	}
++
++	rkc->rst = devm_reset_control_array_get_exclusive(dev);
++	if (IS_ERR(rkc->rst)) {
++		err = PTR_ERR(rkc->rst);
++		dev_err(&pdev->dev, "Fail to get resets err=%d\n", err);
++		goto err_crypto;
++	}
++
++	rkc->tl = dma_alloc_coherent(rkc->dev,
++				     sizeof(struct rk2_crypto_lli) * MAX_LLI,
++				     &rkc->t_phy, GFP_KERNEL);
++	if (!rkc->tl) {
++		dev_err(rkc->dev, "Cannot get DMA memory for task\n");
++		err = -ENOMEM;
++		goto err_crypto;
++	}
++
++	reset_control_assert(rkc->rst);
++	usleep_range(10, 20);
++	reset_control_deassert(rkc->rst);
++
++	rkc->reg = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(rkc->reg)) {
++		err = PTR_ERR(rkc->reg);
++		dev_err(&pdev->dev, "Fail to get resources\n");
++		goto err_crypto;
++	}
++
++	err = rk2_crypto_get_clks(rkc);
++	if (err)
++		goto err_crypto;
++
++	rkc->irq = platform_get_irq(pdev, 0);
++	if (rkc->irq < 0) {
++		dev_err(&pdev->dev, "control Interrupt is not available.\n");
++		err = rkc->irq;
++		goto err_crypto;
++	}
++
++	err = devm_request_irq(&pdev->dev, rkc->irq,
++			       rk2_crypto_irq_handle, IRQF_SHARED,
++			       "rk-crypto", pdev);
++
++	if (err) {
++		dev_err(&pdev->dev, "irq request failed.\n");
++		goto err_crypto;
++	}
++
++	rkc->engine = crypto_engine_alloc_init(&pdev->dev, true);
++	crypto_engine_start(rkc->engine);
++	init_completion(&rkc->complete);
++
++	err = rk2_crypto_pm_init(rkc);
++	if (err)
++		goto err_pm;
++
++	err = pm_runtime_resume_and_get(&pdev->dev);
++
++	spin_lock(&rocklist.lock);
++	first = list_first_entry_or_null(&rocklist.dev_list,
++					 struct rk2_crypto_dev, list);
++	list_add_tail(&rkc->list, &rocklist.dev_list);
++	spin_unlock(&rocklist.lock);
++
++	if (!first) {
++		dev_info(dev, "Registers crypto algos\n");
++		err = rk2_crypto_register(rkc);
++		if (err) {
++			dev_err(dev, "Fail to register crypto algorithms");
++			goto err_register_alg;
++		}
++
++		register_debugfs(rkc);
++	}
++
++	return 0;
++
++err_register_alg:
++	rk2_crypto_pm_exit(rkc);
++err_pm:
++	crypto_engine_exit(rkc->engine);
++err_crypto:
++	dev_err(dev, "Crypto Accelerator not successfully registered\n");
++	return err;
++}
++
++static void rk2_crypto_remove(struct platform_device *pdev)
++{
++	struct rk2_crypto_dev *rkc = platform_get_drvdata(pdev);
++	struct rk2_crypto_dev *first;
++
++	spin_lock_bh(&rocklist.lock);
++	list_del(&rkc->list);
++	first = list_first_entry_or_null(&rocklist.dev_list,
++					 struct rk2_crypto_dev, list);
++	spin_unlock_bh(&rocklist.lock);
++
++	if (!first) {
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG
++		debugfs_remove_recursive(rocklist.dbgfs_dir);
++#endif
++		rk2_crypto_unregister();
++	}
++	rk2_crypto_pm_exit(rkc);
++	crypto_engine_exit(rkc->engine);
++}
++
++static struct platform_driver crypto_driver = {
++	.probe		= rk2_crypto_probe,
++	.remove		= rk2_crypto_remove,
++	.driver		= {
++		.name	= "rk2-crypto",
++		.pm		= &rk2_crypto_pm_ops,
++		.of_match_table	= crypto_of_id_table,
++	},
++};
++
++module_platform_driver(crypto_driver);
++
++MODULE_DESCRIPTION("Rockchip Crypto Engine cryptographic offloader");
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Corentin Labbe <clabbe@baylibre.com>");
+diff --git a/drivers/crypto/rockchip/rk2_crypto.h b/drivers/crypto/rockchip/rk2_crypto.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/crypto/rockchip/rk2_crypto.h
+@@ -0,0 +1,246 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#include <crypto/aes.h>
++#include <crypto/xts.h>
++#include <crypto/engine.h>
++#include <crypto/internal/des.h>
++#include <crypto/internal/hash.h>
++#include <crypto/internal/skcipher.h>
++#include <crypto/algapi.h>
++#include <crypto/md5.h>
++#include <crypto/sha1.h>
++#include <crypto/sha2.h>
++#include <crypto/sm3.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/debugfs.h>
++#include <linux/delay.h>
++#include <linux/pm_runtime.h>
++#include <linux/scatterlist.h>
++#include <linux/hw_random.h>
++
++#define RK2_CRYPTO_CLK_CTL	0x0000
++#define RK2_CRYPTO_RST_CTL	0x0004
++
++#define RK2_CRYPTO_DMA_INT_EN	0x0008
++/* values for RK2_CRYPTO_DMA_INT_EN */
++#define RK2_CRYPTO_DMA_INT_LISTDONE	BIT(0)
++
++#define RK2_CRYPTO_DMA_INT_ST	0x000C
++/* values in RK2_CRYPTO_DMA_INT_ST are the same than in RK2_CRYPTO_DMA_INT_EN */
++
++#define RK2_CRYPTO_DMA_CTL	0x0010
++#define RK2_CRYPTO_DMA_CTL_START	BIT(0)
++
++#define RK2_CRYPTO_DMA_LLI_ADDR	0x0014
++#define RK2_CRYPTO_DMA_ST	0x0018
++#define RK2_CRYPTO_DMA_STATE	0x001C
++#define RK2_CRYPTO_DMA_LLI_RADDR	0x0020
++#define RK2_CRYPTO_DMA_SRC_RADDR	0x0024
++#define RK2_CRYPTO_DMA_DST_WADDR	0x0028
++#define RK2_CRYPTO_DMA_ITEM_ID		0x002C
++
++#define RK2_CRYPTO_FIFO_CTL	0x0040
++
++#define RK2_CRYPTO_BC_CTL	0x0044
++#define RK2_CRYPTO_AES		(0 << 8)
++#define RK2_CRYPTO_MODE_ECB	(0 << 4)
++#define RK2_CRYPTO_MODE_CBC	(1 << 4)
++#define RK2_CRYPTO_XTS		(6 << 4)
++
++#define RK2_CRYPTO_HASH_CTL	0x0048
++#define RK2_CRYPTO_HW_PAD	BIT(2)
++#define RK2_CRYPTO_SHA1		(0 << 4)
++#define RK2_CRYPTO_MD5		(1 << 4)
++#define RK2_CRYPTO_SHA224	(3 << 4)
++#define RK2_CRYPTO_SHA256	(2 << 4)
++#define RK2_CRYPTO_SHA384	(9 << 4)
++#define RK2_CRYPTO_SHA512	(8 << 4)
++#define RK2_CRYPTO_SM3		(4 << 4)
++
++#define RK2_CRYPTO_AES_ECB		(RK2_CRYPTO_AES | RK2_CRYPTO_MODE_ECB)
++#define RK2_CRYPTO_AES_CBC		(RK2_CRYPTO_AES | RK2_CRYPTO_MODE_CBC)
++#define RK2_CRYPTO_AES_XTS		(RK2_CRYPTO_AES | RK2_CRYPTO_XTS)
++#define RK2_CRYPTO_AES_CTR_MODE		3
++#define RK2_CRYPTO_AES_128BIT_key	(0 << 2)
++#define RK2_CRYPTO_AES_192BIT_key	(1 << 2)
++#define RK2_CRYPTO_AES_256BIT_key	(2 << 2)
++
++#define RK2_CRYPTO_DEC			BIT(1)
++#define RK2_CRYPTO_ENABLE		BIT(0)
++
++#define RK2_CRYPTO_CIPHER_ST	0x004C
++#define RK2_CRYPTO_CIPHER_STATE	0x0050
++
++#define RK2_CRYPTO_CH0_IV_0		0x0100
++
++#define RK2_CRYPTO_KEY0			0x0180
++#define RK2_CRYPTO_KEY1			0x0184
++#define RK2_CRYPTO_KEY2			0x0188
++#define RK2_CRYPTO_KEY3			0x018C
++#define RK2_CRYPTO_KEY4			0x0190
++#define RK2_CRYPTO_KEY5			0x0194
++#define RK2_CRYPTO_KEY6			0x0198
++#define RK2_CRYPTO_KEY7			0x019C
++#define RK2_CRYPTO_CH4_KEY0		0x01c0
++
++#define RK2_CRYPTO_CH0_PC_LEN_0		0x0280
++
++#define RK2_CRYPTO_CH0_IV_LEN		0x0300
++
++#define RK2_CRYPTO_HASH_DOUT_0	0x03A0
++#define RK2_CRYPTO_HASH_VALID	0x03E4
++
++#define RK2_CRYPTO_TRNG_CTL	0x0400
++#define RK2_CRYPTO_TRNG_START	BIT(0)
++#define RK2_CRYPTO_TRNG_ENABLE	BIT(1)
++#define RK2_CRYPTO_TRNG_256	(0x3 << 4)
++#define RK2_CRYPTO_TRNG_SAMPLE_CNT	0x0404
++#define RK2_CRYPTO_TRNG_DOUT	0x0410
++
++#define CRYPTO_AES_VERSION	0x0680
++#define CRYPTO_DES_VERSION	0x0684
++#define CRYPTO_SM4_VERSION	0x0688
++#define CRYPTO_HASH_VERSION	0x068C
++#define CRYPTO_HMAC_VERSION	0x0690
++#define CRYPTO_RNG_VERSION	0x0694
++#define CRYPTO_PKA_VERSION	0x0698
++#define CRYPTO_CRYPTO_VERSION	0x06F0
++
++#define RK2_LLI_DMA_CTRL_SRC_INT		BIT(10)
++#define RK2_LLI_DMA_CTRL_DST_INT		BIT(9)
++#define RK2_LLI_DMA_CTRL_LIST_INT	BIT(8)
++#define RK2_LLI_DMA_CTRL_LAST		BIT(0)
++
++#define RK2_LLI_STRING_LAST		BIT(2)
++#define RK2_LLI_STRING_FIRST		BIT(1)
++#define RK2_LLI_CIPHER_START		BIT(0)
++
++#define RK2_MAX_CLKS 4
++
++#define MAX_LLI 20
++
++struct rk2_crypto_lli {
++	__le32 src_addr;
++	__le32 src_len;
++	__le32 dst_addr;
++	__le32 dst_len;
++	__le32 user;
++	__le32 iv;
++	__le32 dma_ctrl;
++	__le32 next;
++};
++
++/*
++ * struct rockchip_ip - struct for managing a list of RK crypto instance
++ * @dev_list:		Used for doing a list of rk2_crypto_dev
++ * @lock:		Control access to dev_list
++ * @dbgfs_dir:		Debugfs dentry for statistic directory
++ * @dbgfs_stats:	Debugfs dentry for statistic counters
++ */
++struct rockchip_ip {
++	struct list_head	dev_list;
++	spinlock_t		lock; /* Control access to dev_list */
++	struct dentry		*dbgfs_dir;
++	struct dentry		*dbgfs_stats;
++};
++
++struct rk2_clks {
++	const char *name;
++	unsigned long max;
++};
++
++struct rk2_variant {
++	int num_clks;
++	struct rk2_clks rkclks[RK2_MAX_CLKS];
++};
++
++struct rk2_crypto_dev {
++	struct list_head		list;
++	struct device			*dev;
++	struct clk_bulk_data		*clks;
++	int				num_clks;
++	struct reset_control		*rst;
++	void __iomem			*reg;
++	int				irq;
++	const struct rk2_variant *variant;
++	unsigned long nreq;
++	struct crypto_engine *engine;
++	struct completion complete;
++	int status;
++	struct rk2_crypto_lli *tl;
++	dma_addr_t t_phy;
++};
++
++/* the private variable of hash */
++struct rk2_ahash_ctx {
++	/* for fallback */
++	struct crypto_ahash		*fallback_tfm;
++};
++
++/* the private variable of hash for fallback */
++struct rk2_ahash_rctx {
++	struct rk2_crypto_dev		*dev;
++	struct ahash_request		fallback_req;
++	u32				mode;
++	int nrsgs;
++};
++
++/* the private variable of cipher */
++struct rk2_cipher_ctx {
++	unsigned int			keylen;
++	u8				key[AES_MAX_KEY_SIZE * 2];
++	u8				iv[AES_BLOCK_SIZE];
++	struct crypto_skcipher *fallback_tfm;
++};
++
++struct rk2_cipher_rctx {
++	struct rk2_crypto_dev		*dev;
++	u8 backup_iv[AES_BLOCK_SIZE];
++	u32				mode;
++	struct skcipher_request fallback_req;   // keep at the end
++};
++
++struct rk2_crypto_template {
++	u32 type;
++	u32 rk2_mode;
++	bool is_xts;
++	struct rk2_crypto_dev           *dev;
++	union {
++		struct skcipher_engine_alg	skcipher;
++		struct ahash_engine_alg	hash;
++	} alg;
++	unsigned long stat_req;
++	unsigned long stat_fb;
++	unsigned long stat_fb_len;
++	unsigned long stat_fb_sglen;
++	unsigned long stat_fb_align;
++	unsigned long stat_fb_sgdiff;
++};
++
++struct rk2_crypto_dev *get_rk2_crypto(void);
++int rk2_cipher_run(struct crypto_engine *engine, void *async_req);
++int rk2_hash_run(struct crypto_engine *engine, void *breq);
++
++int rk2_cipher_tfm_init(struct crypto_skcipher *tfm);
++void rk2_cipher_tfm_exit(struct crypto_skcipher *tfm);
++int rk2_aes_setkey(struct crypto_skcipher *cipher, const u8 *key,
++		   unsigned int keylen);
++int rk2_aes_xts_setkey(struct crypto_skcipher *cipher, const u8 *key,
++		       unsigned int keylen);
++int rk2_skcipher_encrypt(struct skcipher_request *req);
++int rk2_skcipher_decrypt(struct skcipher_request *req);
++int rk2_aes_ecb_encrypt(struct skcipher_request *req);
++int rk2_aes_ecb_decrypt(struct skcipher_request *req);
++int rk2_aes_cbc_encrypt(struct skcipher_request *req);
++int rk2_aes_cbc_decrypt(struct skcipher_request *req);
++
++int rk2_ahash_init(struct ahash_request *req);
++int rk2_ahash_update(struct ahash_request *req);
++int rk2_ahash_final(struct ahash_request *req);
++int rk2_ahash_finup(struct ahash_request *req);
++int rk2_ahash_import(struct ahash_request *req, const void *in);
++int rk2_ahash_export(struct ahash_request *req, void *out);
++int rk2_ahash_digest(struct ahash_request *req);
++int rk2_hash_init_tfm(struct crypto_ahash *tfm);
++void rk2_hash_exit_tfm(struct crypto_ahash *tfm);
+diff --git a/drivers/crypto/rockchip/rk2_crypto_ahash.c b/drivers/crypto/rockchip/rk2_crypto_ahash.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/crypto/rockchip/rk2_crypto_ahash.c
+@@ -0,0 +1,344 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Crypto offloader support for Rockchip RK3568/RK3588
++ *
++ * Copyright (c) 2022-2023 Corentin Labbe <clabbe@baylibre.com>
++ */
++#include <asm/unaligned.h>
++#include <linux/iopoll.h>
++#include "rk2_crypto.h"
++
++static bool rk2_ahash_need_fallback(struct ahash_request *areq)
++{
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
++	struct ahash_alg *alg = crypto_ahash_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base);
++	struct scatterlist *sg;
++
++	sg = areq->src;
++	while (sg) {
++		if (!IS_ALIGNED(sg->offset, sizeof(u32))) {
++			algt->stat_fb_align++;
++			return true;
++		}
++		if (sg->length % 4) {
++			algt->stat_fb_sglen++;
++			return true;
++		}
++		sg = sg_next(sg);
++	}
++	return false;
++}
++
++static int rk2_ahash_digest_fb(struct ahash_request *areq)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
++	struct rk2_ahash_ctx *tfmctx = crypto_ahash_ctx(tfm);
++	struct ahash_alg *alg = crypto_ahash_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base);
++
++	algt->stat_fb++;
++
++	ahash_request_set_tfm(&rctx->fallback_req, tfmctx->fallback_tfm);
++	rctx->fallback_req.base.flags = areq->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++
++	rctx->fallback_req.nbytes = areq->nbytes;
++	rctx->fallback_req.src = areq->src;
++	rctx->fallback_req.result = areq->result;
++
++	return crypto_ahash_digest(&rctx->fallback_req);
++}
++
++static int zero_message_process(struct ahash_request *req)
++{
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct ahash_alg *alg = crypto_ahash_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base);
++	int digestsize = crypto_ahash_digestsize(tfm);
++
++	switch (algt->rk2_mode) {
++	case RK2_CRYPTO_SHA1:
++		memcpy(req->result, sha1_zero_message_hash, digestsize);
++		break;
++	case RK2_CRYPTO_SHA256:
++		memcpy(req->result, sha256_zero_message_hash, digestsize);
++		break;
++	case RK2_CRYPTO_SHA384:
++		memcpy(req->result, sha384_zero_message_hash, digestsize);
++		break;
++	case RK2_CRYPTO_SHA512:
++		memcpy(req->result, sha512_zero_message_hash, digestsize);
++		break;
++	case RK2_CRYPTO_MD5:
++		memcpy(req->result, md5_zero_message_hash, digestsize);
++		break;
++	case RK2_CRYPTO_SM3:
++		memcpy(req->result, sm3_zero_message_hash, digestsize);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++int rk2_ahash_init(struct ahash_request *req)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++
++	return crypto_ahash_init(&rctx->fallback_req);
++}
++
++int rk2_ahash_update(struct ahash_request *req)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++	rctx->fallback_req.nbytes = req->nbytes;
++	rctx->fallback_req.src = req->src;
++
++	return crypto_ahash_update(&rctx->fallback_req);
++}
++
++int rk2_ahash_final(struct ahash_request *req)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++	rctx->fallback_req.result = req->result;
++
++	return crypto_ahash_final(&rctx->fallback_req);
++}
++
++int rk2_ahash_finup(struct ahash_request *req)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++
++	rctx->fallback_req.nbytes = req->nbytes;
++	rctx->fallback_req.src = req->src;
++	rctx->fallback_req.result = req->result;
++
++	return crypto_ahash_finup(&rctx->fallback_req);
++}
++
++int rk2_ahash_import(struct ahash_request *req, const void *in)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++
++	return crypto_ahash_import(&rctx->fallback_req, in);
++}
++
++int rk2_ahash_export(struct ahash_request *req, void *out)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++
++	return crypto_ahash_export(&rctx->fallback_req, out);
++}
++
++int rk2_ahash_digest(struct ahash_request *req)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct rk2_crypto_dev *dev;
++	struct crypto_engine *engine;
++
++	if (rk2_ahash_need_fallback(req))
++		return rk2_ahash_digest_fb(req);
++
++	if (!req->nbytes)
++		return zero_message_process(req);
++
++	dev = get_rk2_crypto();
++
++	rctx->dev = dev;
++	engine = dev->engine;
++
++	return crypto_transfer_hash_request_to_engine(engine, req);
++}
++
++static int rk2_hash_prepare(struct crypto_engine *engine, void *breq)
++{
++	struct ahash_request *areq = container_of(breq, struct ahash_request, base);
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq);
++	struct rk2_crypto_dev *rkc = rctx->dev;
++	int ret;
++
++	ret = dma_map_sg(rkc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE);
++	if (ret <= 0)
++		return -EINVAL;
++
++	rctx->nrsgs = ret;
++
++	return 0;
++}
++
++static void rk2_hash_unprepare(struct crypto_engine *engine, void *breq)
++{
++	struct ahash_request *areq = container_of(breq, struct ahash_request, base);
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq);
++	struct rk2_crypto_dev *rkc = rctx->dev;
++
++	dma_unmap_sg(rkc->dev, areq->src, rctx->nrsgs, DMA_TO_DEVICE);
++}
++
++int rk2_hash_run(struct crypto_engine *engine, void *breq)
++{
++	struct ahash_request *areq = container_of(breq, struct ahash_request, base);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq);
++	struct ahash_alg *alg = crypto_ahash_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base);
++	struct scatterlist *sgs = areq->src;
++	struct rk2_crypto_dev *rkc = rctx->dev;
++	struct rk2_crypto_lli *dd = &rkc->tl[0];
++	int ddi = 0;
++	int err = 0;
++	unsigned int len = areq->nbytes;
++	unsigned int todo;
++	u32 v;
++	int i;
++
++	err = rk2_hash_prepare(engine, breq);
++
++	err = pm_runtime_resume_and_get(rkc->dev);
++	if (err)
++		return err;
++
++	dev_dbg(rkc->dev, "%s %s len=%d\n", __func__,
++		crypto_tfm_alg_name(areq->base.tfm), areq->nbytes);
++
++	algt->stat_req++;
++	rkc->nreq++;
++
++	rctx->mode = algt->rk2_mode;
++	rctx->mode |= 0xffff0000;
++	rctx->mode |= RK2_CRYPTO_ENABLE | RK2_CRYPTO_HW_PAD;
++	writel(rctx->mode, rkc->reg + RK2_CRYPTO_HASH_CTL);
++
++	while (sgs && len > 0) {
++		dd = &rkc->tl[ddi];
++
++		todo = min(sg_dma_len(sgs), len);
++		dd->src_addr = sg_dma_address(sgs);
++		dd->src_len = todo;
++		dd->dst_addr = 0;
++		dd->dst_len = 0;
++		dd->dma_ctrl = ddi << 24;
++		dd->iv = 0;
++		dd->next = rkc->t_phy + sizeof(struct rk2_crypto_lli) * (ddi + 1);
++
++		if (ddi == 0)
++			dd->user = RK2_LLI_CIPHER_START | RK2_LLI_STRING_FIRST;
++		else
++			dd->user = 0;
++
++		len -= todo;
++		dd->dma_ctrl |= RK2_LLI_DMA_CTRL_SRC_INT;
++		if (len == 0) {
++			dd->user |= RK2_LLI_STRING_LAST;
++			dd->dma_ctrl |= RK2_LLI_DMA_CTRL_LAST;
++		}
++		dev_dbg(rkc->dev, "HASH SG %d sglen=%d user=%x dma=%x mode=%x len=%d todo=%d phy=%llx\n",
++			ddi, sgs->length, dd->user, dd->dma_ctrl, rctx->mode, len, todo, rkc->t_phy);
++
++		sgs = sg_next(sgs);
++		ddi++;
++	}
++	dd->next = 1;
++	writel(RK2_CRYPTO_DMA_INT_LISTDONE | 0x7F, rkc->reg + RK2_CRYPTO_DMA_INT_EN);
++
++	writel(rkc->t_phy, rkc->reg + RK2_CRYPTO_DMA_LLI_ADDR);
++
++	reinit_completion(&rkc->complete);
++	rkc->status = 0;
++
++	writel(RK2_CRYPTO_DMA_CTL_START | RK2_CRYPTO_DMA_CTL_START << 16, rkc->reg + RK2_CRYPTO_DMA_CTL);
++
++	wait_for_completion_interruptible_timeout(&rkc->complete,
++						  msecs_to_jiffies(2000));
++	if (!rkc->status) {
++		dev_err(rkc->dev, "DMA timeout\n");
++		err = -EFAULT;
++		goto theend;
++	}
++
++	readl_poll_timeout_atomic(rkc->reg + RK2_CRYPTO_HASH_VALID, v, v == 1,
++				  10, 1000);
++
++	for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) {
++		v = readl(rkc->reg + RK2_CRYPTO_HASH_DOUT_0 + i * 4);
++		put_unaligned_le32(be32_to_cpu(v), areq->result + i * 4);
++	}
++
++theend:
++	pm_runtime_put_autosuspend(rkc->dev);
++
++	rk2_hash_unprepare(engine, breq);
++
++	local_bh_disable();
++	crypto_finalize_hash_request(engine, breq, err);
++	local_bh_enable();
++
++	return 0;
++}
++
++int rk2_hash_init_tfm(struct crypto_ahash *tfm)
++{
++	struct rk2_ahash_ctx *tctx = crypto_ahash_ctx(tfm);
++	const char *alg_name = crypto_ahash_alg_name(tfm);
++	struct ahash_alg *alg = crypto_ahash_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base);
++
++	/* for fallback */
++	tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0,
++						CRYPTO_ALG_NEED_FALLBACK);
++	if (IS_ERR(tctx->fallback_tfm)) {
++		dev_err(algt->dev->dev, "Could not load fallback driver.\n");
++		return PTR_ERR(tctx->fallback_tfm);
++	}
++
++	crypto_ahash_set_reqsize(tfm,
++				 sizeof(struct rk2_ahash_rctx) +
++				 crypto_ahash_reqsize(tctx->fallback_tfm));
++	return 0;
++}
++
++void rk2_hash_exit_tfm(struct crypto_ahash *tfm)
++{
++	struct rk2_ahash_ctx *tctx = crypto_ahash_ctx(tfm);
++
++	crypto_free_ahash(tctx->fallback_tfm);
++}
+diff --git a/drivers/crypto/rockchip/rk2_crypto_skcipher.c b/drivers/crypto/rockchip/rk2_crypto_skcipher.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/crypto/rockchip/rk2_crypto_skcipher.c
+@@ -0,0 +1,576 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * hardware cryptographic offloader for RK3568/RK3588 SoC
++ *
++ * Copyright (c) 2022-2023 Corentin Labbe <clabbe@baylibre.com>
++ */
++#include <crypto/scatterwalk.h>
++#include "rk2_crypto.h"
++
++static void rk2_print(struct rk2_crypto_dev *rkc)
++{
++	u32 v;
++
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_ST);
++	dev_info(rkc->dev, "DMA_ST %x\n", v);
++	switch (v) {
++	case 0:
++		dev_info(rkc->dev, "DMA_ST: DMA IDLE\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "DMA_ST: DMA BUSY\n");
++		break;
++	default:
++		dev_err(rkc->dev, "DMA_ST: invalid value\n");
++	}
++
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_STATE);
++	dev_info(rkc->dev, "DMA_STATE %x\n", v);
++
++	switch (v & 0x3) {
++	case 0:
++		dev_info(rkc->dev, "DMA_STATE: DMA DST IDLE\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "DMA_STATE: DMA DST LOAD\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "DMA_STATE: DMA DST WORK\n");
++		break;
++	default:
++		dev_err(rkc->dev, "DMA DST invalid\n");
++		break;
++	}
++	switch (v & 0xC) {
++	case 0:
++		dev_info(rkc->dev, "DMA_STATE: DMA SRC IDLE\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "DMA_STATE: DMA SRC LOAD\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "DMA_STATE: DMA SRC WORK\n");
++		break;
++	default:
++		dev_err(rkc->dev, "DMA_STATE: DMA SRC invalid\n");
++		break;
++	}
++	switch (v & 0x30) {
++	case 0:
++		dev_info(rkc->dev, "DMA_STATE: DMA LLI IDLE\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "DMA_STATE: DMA LLI LOAD\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "DMA LLI WORK\n");
++		break;
++	default:
++		dev_err(rkc->dev, "DMA LLI invalid\n");
++		break;
++	}
++
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_LLI_RADDR);
++	dev_info(rkc->dev, "DMA_LLI_RADDR %x\n", v);
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_SRC_RADDR);
++	dev_info(rkc->dev, "DMA_SRC_RADDR %x\n", v);
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_DST_WADDR);
++	dev_info(rkc->dev, "DMA_LLI_WADDR %x\n", v);
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_ITEM_ID);
++	dev_info(rkc->dev, "DMA_LLI_ITEMID %x\n", v);
++
++	v = readl(rkc->reg + RK2_CRYPTO_CIPHER_ST);
++	dev_info(rkc->dev, "CIPHER_ST %x\n", v);
++	if (v & BIT(0))
++		dev_info(rkc->dev, "CIPHER_ST: BLOCK CIPHER BUSY\n");
++	else
++		dev_info(rkc->dev, "CIPHER_ST: BLOCK CIPHER IDLE\n");
++	if (v & BIT(2))
++		dev_info(rkc->dev, "CIPHER_ST: HASH BUSY\n");
++	else
++		dev_info(rkc->dev, "CIPHER_ST: HASH IDLE\n");
++	if (v & BIT(2))
++		dev_info(rkc->dev, "CIPHER_ST: OTP KEY VALID\n");
++	else
++		dev_info(rkc->dev, "CIPHER_ST: OTP KEY INVALID\n");
++
++	v = readl(rkc->reg + RK2_CRYPTO_CIPHER_STATE);
++	dev_info(rkc->dev, "CIPHER_STATE %x\n", v);
++	switch (v & 0x3) {
++	case 0:
++		dev_info(rkc->dev, "serial: IDLE state\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "serial: PRE state\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "serial: BULK state\n");
++		break;
++	default:
++		dev_info(rkc->dev, "serial: reserved state\n");
++		break;
++	}
++	switch (v & 0xC) {
++	case 0:
++		dev_info(rkc->dev, "mac_state: IDLE state\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "mac_state: PRE state\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "mac_state: BULK state\n");
++		break;
++	default:
++		dev_info(rkc->dev, "mac_state: reserved state\n");
++		break;
++	}
++	switch (v & 0x30) {
++	case 0:
++		dev_info(rkc->dev, "parallel_state: IDLE state\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "parallel_state: PRE state\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "parallel_state: BULK state\n");
++		break;
++	default:
++		dev_info(rkc->dev, "parallel_state: reserved state\n");
++		break;
++	}
++	switch (v & 0xC0) {
++	case 0:
++		dev_info(rkc->dev, "ccm_state: IDLE state\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "ccm_state: PRE state\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "ccm_state: NA state\n");
++		break;
++	default:
++		dev_info(rkc->dev, "ccm_state: reserved state\n");
++		break;
++	}
++	switch (v & 0xF00) {
++	case 0:
++		dev_info(rkc->dev, "gcm_state: IDLE state\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "gcm_state: PRE state\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "gcm_state: NA state\n");
++		break;
++	case 3:
++		dev_info(rkc->dev, "gcm_state: PC state\n");
++		break;
++	}
++	switch (v & 0xC00) {
++	case 0x1:
++		dev_info(rkc->dev, "hash_state: IDLE state\n");
++		break;
++	case 0x2:
++		dev_info(rkc->dev, "hash_state: IPAD state\n");
++		break;
++	case 0x4:
++		dev_info(rkc->dev, "hash_state: TEXT state\n");
++		break;
++	case 0x8:
++		dev_info(rkc->dev, "hash_state: OPAD state\n");
++		break;
++	case 0x10:
++		dev_info(rkc->dev, "hash_state: OPAD EXT state\n");
++		break;
++	default:
++		dev_info(rkc->dev, "hash_state: invalid state\n");
++		break;
++	}
++
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_INT_ST);
++	dev_info(rkc->dev, "RK2_CRYPTO_DMA_INT_ST %x\n", v);
++}
++
++static int rk2_cipher_need_fallback(struct skcipher_request *req)
++{
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++	struct scatterlist *sgs, *sgd;
++	unsigned int stodo, dtodo, len;
++	unsigned int bs = crypto_skcipher_blocksize(tfm);
++
++	if (!req->cryptlen)
++		return true;
++
++	if (algt->is_xts) {
++		if (sg_nents_for_len(req->src, req->cryptlen) > 1)
++			return true;
++		if (sg_nents_for_len(req->dst, req->cryptlen) > 1)
++			return true;
++	}
++
++	len = req->cryptlen;
++	sgs = req->src;
++	sgd = req->dst;
++	while (sgs && sgd) {
++		if (!IS_ALIGNED(sgs->offset, sizeof(u32))) {
++			algt->stat_fb_align++;
++			return true;
++		}
++		if (!IS_ALIGNED(sgd->offset, sizeof(u32))) {
++			algt->stat_fb_align++;
++			return true;
++		}
++		stodo = min(len, sgs->length);
++		if (stodo % bs) {
++			algt->stat_fb_len++;
++			return true;
++		}
++		dtodo = min(len, sgd->length);
++		if (dtodo % bs) {
++			algt->stat_fb_len++;
++			return true;
++		}
++		if (stodo != dtodo) {
++			algt->stat_fb_sgdiff++;
++			return true;
++		}
++		len -= stodo;
++		sgs = sg_next(sgs);
++		sgd = sg_next(sgd);
++	}
++	return false;
++}
++
++static int rk2_cipher_fallback(struct skcipher_request *areq)
++{
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
++	struct rk2_cipher_ctx *op = crypto_skcipher_ctx(tfm);
++	struct rk2_cipher_rctx *rctx = skcipher_request_ctx(areq);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++	int err;
++
++	algt->stat_fb++;
++
++	skcipher_request_set_tfm(&rctx->fallback_req, op->fallback_tfm);
++	skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags,
++				      areq->base.complete, areq->base.data);
++	skcipher_request_set_crypt(&rctx->fallback_req, areq->src, areq->dst,
++				   areq->cryptlen, areq->iv);
++	if (rctx->mode & RK2_CRYPTO_DEC)
++		err = crypto_skcipher_decrypt(&rctx->fallback_req);
++	else
++		err = crypto_skcipher_encrypt(&rctx->fallback_req);
++	return err;
++}
++
++static int rk2_cipher_handle_req(struct skcipher_request *req)
++{
++	struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req);
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++	struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++	struct rk2_crypto_dev *rkc;
++	struct crypto_engine *engine;
++
++	if (ctx->keylen == AES_KEYSIZE_192 * 2)
++		return rk2_cipher_fallback(req);
++
++	if (rk2_cipher_need_fallback(req))
++		return rk2_cipher_fallback(req);
++
++	rkc = get_rk2_crypto();
++
++	engine = rkc->engine;
++	rctx->dev = rkc;
++
++	return crypto_transfer_skcipher_request_to_engine(engine, req);
++}
++
++int rk2_aes_xts_setkey(struct crypto_skcipher *cipher, const u8 *key,
++		       unsigned int keylen)
++{
++	struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher);
++	struct rk2_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
++	int err;
++
++	err = xts_verify_key(cipher, key, keylen);
++	if (err)
++		return err;
++
++	ctx->keylen = keylen;
++	memcpy(ctx->key, key, keylen);
++
++	return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen);
++}
++
++int rk2_aes_setkey(struct crypto_skcipher *cipher, const u8 *key,
++		   unsigned int keylen)
++{
++	struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher);
++	struct rk2_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
++
++	if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
++	    keylen != AES_KEYSIZE_256)
++		return -EINVAL;
++	ctx->keylen = keylen;
++	memcpy(ctx->key, key, keylen);
++
++	return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen);
++}
++
++int rk2_skcipher_encrypt(struct skcipher_request *req)
++{
++	struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req);
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++
++	rctx->mode = algt->rk2_mode;
++	return rk2_cipher_handle_req(req);
++}
++
++int rk2_skcipher_decrypt(struct skcipher_request *req)
++{
++	struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req);
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++
++	rctx->mode = algt->rk2_mode | RK2_CRYPTO_DEC;
++	return rk2_cipher_handle_req(req);
++}
++
++int rk2_cipher_run(struct crypto_engine *engine, void *async_req)
++{
++	struct skcipher_request *areq = container_of(async_req, struct skcipher_request, base);
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
++	struct rk2_cipher_rctx *rctx = skcipher_request_ctx(areq);
++	struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++	struct scatterlist *sgs, *sgd;
++	int err = 0;
++	int ivsize = crypto_skcipher_ivsize(tfm);
++	unsigned int len = areq->cryptlen;
++	unsigned int todo;
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++	struct rk2_crypto_dev *rkc = rctx->dev;
++	struct rk2_crypto_lli *dd = &rkc->tl[0];
++	u32 m, v;
++	u32 *rkey = (u32 *)ctx->key;
++	u32 *riv = (u32 *)areq->iv;
++	int i;
++	unsigned int offset;
++
++	algt->stat_req++;
++	rkc->nreq++;
++
++	m = rctx->mode | RK2_CRYPTO_ENABLE;
++	if (algt->is_xts) {
++		switch (ctx->keylen) {
++		case AES_KEYSIZE_128 * 2:
++			m |= RK2_CRYPTO_AES_128BIT_key;
++			break;
++		case AES_KEYSIZE_256 * 2:
++			m |= RK2_CRYPTO_AES_256BIT_key;
++			break;
++		default:
++			dev_err(rkc->dev, "Invalid key length %u\n", ctx->keylen);
++			return -EINVAL;
++		}
++	} else {
++		switch (ctx->keylen) {
++		case AES_KEYSIZE_128:
++			m |= RK2_CRYPTO_AES_128BIT_key;
++			break;
++		case AES_KEYSIZE_192:
++			m |= RK2_CRYPTO_AES_192BIT_key;
++			break;
++		case AES_KEYSIZE_256:
++			m |= RK2_CRYPTO_AES_256BIT_key;
++			break;
++		default:
++			dev_err(rkc->dev, "Invalid key length %u\n", ctx->keylen);
++			return -EINVAL;
++		}
++	}
++
++	err = pm_runtime_resume_and_get(rkc->dev);
++	if (err)
++		return err;
++
++	/* the upper bits are a write enable mask, so we need to write 1 to all
++	 * upper 16 bits to allow write to the 16 lower bits
++	 */
++	m |= 0xffff0000;
++
++	dev_dbg(rkc->dev, "%s %s len=%u keylen=%u mode=%x\n", __func__,
++		crypto_tfm_alg_name(areq->base.tfm),
++		areq->cryptlen, ctx->keylen, m);
++	sgs = areq->src;
++	sgd = areq->dst;
++
++	while (sgs && sgd && len) {
++		ivsize = crypto_skcipher_ivsize(tfm);
++		if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) {
++			if (rctx->mode & RK2_CRYPTO_DEC) {
++				offset = sgs->length - ivsize;
++				scatterwalk_map_and_copy(rctx->backup_iv, sgs,
++							 offset, ivsize, 0);
++			}
++		}
++
++		dev_dbg(rkc->dev, "SG len=%u mode=%x ivsize=%u\n", sgs->length, m, ivsize);
++
++		if (sgs == sgd) {
++			err = dma_map_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL);
++			if (err != 1) {
++				dev_err(rkc->dev, "Invalid sg number %d\n", err);
++				err = -EINVAL;
++				goto theend;
++			}
++		} else {
++			err = dma_map_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE);
++			if (err != 1) {
++				dev_err(rkc->dev, "Invalid sg number %d\n", err);
++				err = -EINVAL;
++				goto theend;
++			}
++			err = dma_map_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE);
++			if (err != 1) {
++				dev_err(rkc->dev, "Invalid sg number %d\n", err);
++				err = -EINVAL;
++				dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE);
++				goto theend;
++			}
++		}
++		err = 0;
++		writel(m, rkc->reg + RK2_CRYPTO_BC_CTL);
++
++		if (algt->is_xts) {
++			for (i = 0; i < ctx->keylen / 8; i++) {
++				v = cpu_to_be32(rkey[i]);
++				writel(v, rkc->reg + RK2_CRYPTO_KEY0 + i * 4);
++			}
++			for (i = 0; i < (ctx->keylen / 8); i++) {
++				v = cpu_to_be32(rkey[i + ctx->keylen / 8]);
++				writel(v, rkc->reg + RK2_CRYPTO_CH4_KEY0 + i * 4);
++			}
++		} else {
++			for (i = 0; i < ctx->keylen / 4; i++) {
++				v = cpu_to_be32(rkey[i]);
++				writel(v, rkc->reg + RK2_CRYPTO_KEY0 + i * 4);
++			}
++		}
++
++		if (ivsize) {
++			for (i = 0; i < ivsize / 4; i++)
++				writel(cpu_to_be32(riv[i]),
++				       rkc->reg + RK2_CRYPTO_CH0_IV_0 + i * 4);
++			writel(ivsize, rkc->reg + RK2_CRYPTO_CH0_IV_LEN);
++		}
++		if (!sgs->length) {
++			sgs = sg_next(sgs);
++			sgd = sg_next(sgd);
++			continue;
++		}
++
++		/* The hw support multiple descriptor, so why this driver use
++		 * only one descriptor ?
++		 * Using one descriptor per SG seems the way to do and it works
++		 * but only when doing encryption.
++		 * With decryption it always fail on second descriptor.
++		 * Probably the HW dont know how to use IV.
++		 */
++		todo = min(sg_dma_len(sgs), len);
++		len -= todo;
++		dd->src_addr = sg_dma_address(sgs);
++		dd->src_len = todo;
++		dd->dst_addr = sg_dma_address(sgd);
++		dd->dst_len = todo;
++		dd->iv = 0;
++		dd->next = 1;
++
++		dd->user = RK2_LLI_CIPHER_START | RK2_LLI_STRING_FIRST | RK2_LLI_STRING_LAST;
++		dd->dma_ctrl |= RK2_LLI_DMA_CTRL_DST_INT | RK2_LLI_DMA_CTRL_LAST;
++
++		writel(RK2_CRYPTO_DMA_INT_LISTDONE | 0x7F, rkc->reg + RK2_CRYPTO_DMA_INT_EN);
++
++		/*writel(0x00030000, rkc->reg + RK2_CRYPTO_FIFO_CTL);*/
++		writel(rkc->t_phy, rkc->reg + RK2_CRYPTO_DMA_LLI_ADDR);
++
++		reinit_completion(&rkc->complete);
++		rkc->status = 0;
++
++		writel(RK2_CRYPTO_DMA_CTL_START | 1 << 16, rkc->reg + RK2_CRYPTO_DMA_CTL);
++
++		wait_for_completion_interruptible_timeout(&rkc->complete,
++							  msecs_to_jiffies(10000));
++		if (sgs == sgd) {
++			dma_unmap_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL);
++		} else {
++			dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE);
++			dma_unmap_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE);
++		}
++
++		if (!rkc->status) {
++			dev_err(rkc->dev, "DMA timeout\n");
++			rk2_print(rkc);
++			err = -EFAULT;
++			goto theend;
++		}
++		if (areq->iv && ivsize > 0) {
++			offset = sgd->length - ivsize;
++			if (rctx->mode & RK2_CRYPTO_DEC) {
++				memcpy(areq->iv, rctx->backup_iv, ivsize);
++				memzero_explicit(rctx->backup_iv, ivsize);
++			} else {
++				scatterwalk_map_and_copy(areq->iv, sgd, offset,
++							 ivsize, 0);
++			}
++		}
++		sgs = sg_next(sgs);
++		sgd = sg_next(sgd);
++	}
++theend:
++	writel(0xffff0000, rkc->reg + RK2_CRYPTO_BC_CTL);
++	pm_runtime_put_autosuspend(rkc->dev);
++
++	local_bh_disable();
++	crypto_finalize_skcipher_request(engine, areq, err);
++	local_bh_enable();
++	return 0;
++}
++
++int rk2_cipher_tfm_init(struct crypto_skcipher *tfm)
++{
++	struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++	const char *name = crypto_tfm_alg_name(&tfm->base);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++
++	ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
++	if (IS_ERR(ctx->fallback_tfm)) {
++		dev_err(algt->dev->dev, "ERROR: Cannot allocate fallback for %s %ld\n",
++			name, PTR_ERR(ctx->fallback_tfm));
++		return PTR_ERR(ctx->fallback_tfm);
++	}
++
++	dev_info(algt->dev->dev, "Fallback for %s is %s\n",
++		 crypto_tfm_alg_driver_name(&tfm->base),
++		 crypto_tfm_alg_driver_name(crypto_skcipher_tfm(ctx->fallback_tfm)));
++
++	tfm->reqsize = sizeof(struct rk2_cipher_rctx) +
++		crypto_skcipher_reqsize(ctx->fallback_tfm);
++
++	return 0;
++}
++
++void rk2_cipher_tfm_exit(struct crypto_skcipher *tfm)
++{
++	struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++
++	memzero_explicit(ctx->key, ctx->keylen);
++	crypto_free_skcipher(ctx->fallback_tfm);
++}
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0025-RK3588-Add-HW-RNG-Support.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0025-RK3588-Add-HW-RNG-Support.patch
new file mode 100644
index 000000000000..ef9b7791121b
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0025-RK3588-Add-HW-RNG-Support.patch
@@ -0,0 +1,663 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Thu, 16 Nov 2023 17:49:42 +0300
+Subject: hwrng: rockchip: Add support for Rockchip HW RNG
+
+---
+ drivers/char/hw_random/Kconfig        |  13 +
+ drivers/char/hw_random/Makefile       |   1 +
+ drivers/char/hw_random/rockchip-rng.c | 574 ++++++++++
+ 3 files changed, 588 insertions(+)
+
+diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/char/hw_random/Kconfig
++++ b/drivers/char/hw_random/Kconfig
+@@ -538,6 +538,19 @@ config HW_RANDOM_XIPHERA
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called xiphera-trng.
+ 
++config HW_RANDOM_ROCKCHIP
++	tristate "Rockchip Random Number Generator support"
++	depends on ARCH_ROCKCHIP
++	default HW_RANDOM
++	help
++	  This driver provides kernel-side support for the Random Number
++	  Generator hardware found on Rockchip cpus.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called rockchip-rng.
++
++	  If unsure, say Y.
++
+ config HW_RANDOM_ARM_SMCCC_TRNG
+ 	tristate "Arm SMCCC TRNG firmware interface support"
+ 	depends on HAVE_ARM_SMCCC_DISCOVERY
+diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/char/hw_random/Makefile
++++ b/drivers/char/hw_random/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
+ obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
+ obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
+ obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
+ obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
+ obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
+ obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
+diff --git a/drivers/char/hw_random/rockchip-rng.c b/drivers/char/hw_random/rockchip-rng.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -0,0 +1,574 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rockchip-rng.c Random Number Generator driver for the Rockchip
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
++ * Author: Lin Jinhan <troy.lin@rock-chips.com>
++ *
++ */
++#include <linux/clk.h>
++#include <linux/hw_random.h>
++#include <linux/iopoll.h>
++#include <linux/module.h>
++#include <linux/mod_devicetable.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++
++#define _SBF(s, v)	((v) << (s))
++#define HIWORD_UPDATE(val, mask, shift) \
++			((val) << (shift) | (mask) << ((shift) + 16))
++
++#define ROCKCHIP_AUTOSUSPEND_DELAY		100
++#define ROCKCHIP_POLL_PERIOD_US			100
++#define ROCKCHIP_POLL_TIMEOUT_US		50000
++#define RK_MAX_RNG_BYTE				(32)
++
++/* start of CRYPTO V1 register define */
++#define CRYPTO_V1_CTRL				0x0008
++#define CRYPTO_V1_RNG_START			BIT(8)
++#define CRYPTO_V1_RNG_FLUSH			BIT(9)
++
++#define CRYPTO_V1_TRNG_CTRL			0x0200
++#define CRYPTO_V1_OSC_ENABLE			BIT(16)
++#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x)		(x)
++
++#define CRYPTO_V1_TRNG_DOUT_0			0x0204
++/* end of CRYPTO V1 register define */
++
++/* start of CRYPTO V2 register define */
++#define CRYPTO_V2_RNG_DEFAULT_OFFSET		0x0400
++#define CRYPTO_V2_RNG_CTL			0x0
++#define CRYPTO_V2_RNG_64_BIT_LEN		_SBF(4, 0x00)
++#define CRYPTO_V2_RNG_128_BIT_LEN		_SBF(4, 0x01)
++#define CRYPTO_V2_RNG_192_BIT_LEN		_SBF(4, 0x02)
++#define CRYPTO_V2_RNG_256_BIT_LEN		_SBF(4, 0x03)
++#define CRYPTO_V2_RNG_FATESY_SOC_RING		_SBF(2, 0x00)
++#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0		_SBF(2, 0x01)
++#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1		_SBF(2, 0x02)
++#define CRYPTO_V2_RNG_SLOWEST_SOC_RING		_SBF(2, 0x03)
++#define CRYPTO_V2_RNG_ENABLE			BIT(1)
++#define CRYPTO_V2_RNG_START			BIT(0)
++#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0004
++#define CRYPTO_V2_RNG_DOUT_0			0x0010
++/* end of CRYPTO V2 register define */
++
++/* start of TRNG_V1 register define */
++/* TRNG is no longer subordinate to the Crypto module */
++#define TRNG_V1_CTRL				0x0000
++#define TRNG_V1_CTRL_NOP			_SBF(0, 0x00)
++#define TRNG_V1_CTRL_RAND			_SBF(0, 0x01)
++#define TRNG_V1_CTRL_SEED			_SBF(0, 0x02)
++
++#define TRNG_V1_STAT				0x0004
++#define TRNG_V1_STAT_SEEDED			BIT(9)
++#define TRNG_V1_STAT_GENERATING			BIT(30)
++#define TRNG_V1_STAT_RESEEDING			BIT(31)
++
++#define TRNG_V1_MODE				0x0008
++#define TRNG_V1_MODE_128_BIT			_SBF(3, 0x00)
++#define TRNG_V1_MODE_256_BIT			_SBF(3, 0x01)
++
++#define TRNG_V1_IE				0x0010
++#define TRNG_V1_IE_GLBL_EN			BIT(31)
++#define TRNG_V1_IE_SEED_DONE_EN			BIT(1)
++#define TRNG_V1_IE_RAND_RDY_EN			BIT(0)
++
++#define TRNG_V1_ISTAT				0x0014
++#define TRNG_V1_ISTAT_RAND_RDY			BIT(0)
++
++/* RAND0 ~ RAND7 */
++#define TRNG_V1_RAND0				0x0020
++#define TRNG_V1_RAND7				0x003C
++
++#define TRNG_V1_AUTO_RQSTS			0x0060
++
++#define TRNG_V1_VERSION				0x00F0
++#define TRNG_v1_VERSION_CODE			0x46bc
++/* end of TRNG_V1 register define */
++
++/* start of RKRNG register define */
++#define RKRNG_CTRL				0x0010
++#define RKRNG_CTRL_INST_REQ			BIT(0)
++#define RKRNG_CTRL_RESEED_REQ			BIT(1)
++#define RKRNG_CTRL_TEST_REQ			BIT(2)
++#define RKRNG_CTRL_SW_DRNG_REQ			BIT(3)
++#define RKRNG_CTRL_SW_TRNG_REQ			BIT(4)
++
++#define RKRNG_STATE				0x0014
++#define RKRNG_STATE_INST_ACK			BIT(0)
++#define RKRNG_STATE_RESEED_ACK			BIT(1)
++#define RKRNG_STATE_TEST_ACK			BIT(2)
++#define RKRNG_STATE_SW_DRNG_ACK			BIT(3)
++#define RKRNG_STATE_SW_TRNG_ACK			BIT(4)
++
++/* DRNG_DATA_0 ~ DNG_DATA_7 */
++#define RKRNG_DRNG_DATA_0			0x0070
++#define RKRNG_DRNG_DATA_7			0x008C
++
++/* end of RKRNG register define */
++
++struct rk_rng_soc_data {
++	u32 default_offset;
++
++	int (*rk_rng_init)(struct hwrng *rng);
++	int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
++};
++
++struct rk_rng {
++	struct device		*dev;
++	struct hwrng		rng;
++	void __iomem		*mem;
++	struct rk_rng_soc_data	*soc_data;
++	int			clk_num;
++	struct clk_bulk_data	*clk_bulks;
++};
++
++static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
++{
++	__raw_writel(val, rng->mem + offset);
++}
++
++static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
++{
++	return __raw_readl(rng->mem + offset);
++}
++
++static int rk_rng_init(struct hwrng *rng)
++{
++	int ret;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
++
++	ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
++	if (ret < 0) {
++		dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static void rk_rng_cleanup(struct hwrng *rng)
++{
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
++	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
++}
++
++static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	int ret;
++	int read_len = 0;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	if (!rk_rng->soc_data->rk_rng_read)
++		return -EFAULT;
++
++	ret = pm_runtime_get_sync(rk_rng->dev);
++	if (ret < 0) {
++		pm_runtime_put_noidle(rk_rng->dev);
++		return ret;
++	}
++
++	ret = 0;
++	while (max > ret) {
++		read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
++							 max - ret, wait);
++		if (read_len < 0) {
++			ret = read_len;
++			break;
++		}
++		ret += read_len;
++	}
++
++	pm_runtime_mark_last_busy(rk_rng->dev);
++	pm_runtime_put_sync_autosuspend(rk_rng->dev);
++
++	return ret;
++}
++
++static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
++			     size_t size)
++{
++	u32 i;
++
++	for (i = 0; i < size; i += 4)
++		*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
++}
++
++static int crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	int ret = 0;
++	u32 reg_ctrl = 0;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	/* enable osc_ring to get entropy, sample period is set as 100 */
++	reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
++	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
++
++	reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
++
++	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
++
++	ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
++				!(reg_ctrl & CRYPTO_V1_RNG_START),
++				ROCKCHIP_POLL_PERIOD_US,
++				ROCKCHIP_POLL_TIMEOUT_US, false,
++				rk_rng, CRYPTO_V1_CTRL);
++
++	if (ret < 0)
++		goto out;
++
++	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
++
++	rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
++
++out:
++	/* close TRNG */
++	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
++		      CRYPTO_V1_CTRL);
++
++	return ret;
++}
++
++static int crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	int ret = 0;
++	u32 reg_ctrl = 0;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	/* enable osc_ring to get entropy, sample period is set as 100 */
++	rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
++
++	reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
++	reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
++	reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
++	reg_ctrl |= CRYPTO_V2_RNG_START;
++
++	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
++		      CRYPTO_V2_RNG_CTL);
++
++	ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
++				!(reg_ctrl & CRYPTO_V2_RNG_START),
++				ROCKCHIP_POLL_PERIOD_US,
++				ROCKCHIP_POLL_TIMEOUT_US, false,
++				rk_rng, CRYPTO_V2_RNG_CTL);
++	if (ret < 0)
++		goto out;
++
++	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
++
++	rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
++
++out:
++	/* close TRNG */
++	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
++
++	return ret;
++}
++
++static int trng_v1_init(struct hwrng *rng)
++{
++	int ret;
++	uint32_t auto_reseed_cnt = 1000;
++	uint32_t reg_ctrl, status, version;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
++	if (version != TRNG_v1_VERSION_CODE) {
++		dev_err(rk_rng->dev,
++			"wrong trng version, expected = %08x, actual = %08x\n",
++			TRNG_V1_VERSION, version);
++		ret = -EFAULT;
++		goto exit;
++	}
++
++	status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
++
++	/* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
++	if (!(status & TRNG_V1_STAT_SEEDED) ||
++	    (status & TRNG_V1_STAT_GENERATING) ||
++	    (status & TRNG_V1_STAT_RESEEDING)) {
++		uint32_t mask = TRNG_V1_STAT_SEEDED |
++				TRNG_V1_STAT_GENERATING |
++				TRNG_V1_STAT_RESEEDING;
++
++		udelay(10);
++
++		/* wait for GENERATING and RESEEDING flag to clear */
++		read_poll_timeout(rk_rng_readl, reg_ctrl,
++				  (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
++				  ROCKCHIP_POLL_PERIOD_US,
++				  ROCKCHIP_POLL_TIMEOUT_US, false,
++				  rk_rng, TRNG_V1_STAT);
++	}
++
++	/* clear ISTAT flag because trng may auto reseeding when power on */
++	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
++	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
++
++	/* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
++	rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
++
++	ret = 0;
++exit:
++
++	return ret;
++}
++
++static int trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	int ret = 0;
++	u32 reg_ctrl = 0;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	/* clear ISTAT anyway */
++	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
++	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
++
++	/* generate 256bit random */
++	rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
++	rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
++
++	/*
++	 * Generate2 56 bit random data will cost 1024 clock cycles.
++	 * Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
++	 */
++	udelay(10);
++	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
++	if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
++		/* wait RAND_RDY triggered */
++		ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
++					(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
++					ROCKCHIP_POLL_PERIOD_US,
++					ROCKCHIP_POLL_TIMEOUT_US, false,
++					rk_rng, TRNG_V1_ISTAT);
++		if (ret < 0)
++			goto out;
++	}
++
++	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
++
++	rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
++
++	/* clear all status flag */
++	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
++out:
++	/* close TRNG */
++	rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
++
++	return ret;
++}
++
++static int rkrng_init(struct hwrng *rng)
++{
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++	u32 reg = 0;
++
++	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
++
++	reg = rk_rng_readl(rk_rng, RKRNG_STATE);
++	rk_rng_writel(rk_rng, reg, RKRNG_STATE);
++
++	return 0;
++}
++
++static int rkrng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++	u32 reg_ctrl = 0;
++	int ret;
++
++	reg_ctrl = RKRNG_CTRL_SW_DRNG_REQ;
++
++	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), RKRNG_CTRL);
++
++	ret = readl_poll_timeout(rk_rng->mem + RKRNG_STATE, reg_ctrl,
++				 (reg_ctrl & RKRNG_STATE_SW_DRNG_ACK),
++				 ROCKCHIP_POLL_PERIOD_US,
++				 ROCKCHIP_POLL_TIMEOUT_US);
++
++	if (ret)
++		goto exit;
++
++	rk_rng_writel(rk_rng, reg_ctrl, RKRNG_STATE);
++
++	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
++
++	rk_rng_read_regs(rk_rng, RKRNG_DRNG_DATA_0, buf, ret);
++
++exit:
++	/* close TRNG */
++	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
++
++	return ret;
++}
++
++static const struct rk_rng_soc_data crypto_v1_soc_data = {
++	.default_offset = 0,
++
++	.rk_rng_read = crypto_v1_read,
++};
++
++static const struct rk_rng_soc_data crypto_v2_soc_data = {
++	.default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
++
++	.rk_rng_read = crypto_v2_read,
++};
++
++static const struct rk_rng_soc_data trng_v1_soc_data = {
++	.default_offset = 0,
++
++	.rk_rng_init = trng_v1_init,
++	.rk_rng_read = trng_v1_read,
++};
++
++static const struct rk_rng_soc_data rkrng_soc_data = {
++	.default_offset = 0,
++
++	.rk_rng_init = rkrng_init,
++	.rk_rng_read = rkrng_read,
++};
++
++static const struct of_device_id rk_rng_dt_match[] = {
++	{
++		.compatible = "rockchip,cryptov1-rng",
++		.data = (void *)&crypto_v1_soc_data,
++	},
++	{
++		.compatible = "rockchip,cryptov2-rng",
++		.data = (void *)&crypto_v2_soc_data,
++	},
++	{
++		.compatible = "rockchip,trngv1",
++		.data = (void *)&trng_v1_soc_data,
++	},
++		{
++		.compatible = "rockchip,rkrng",
++		.data = (void *)&rkrng_soc_data,
++	},
++	{ },
++};
++
++MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
++
++static int rk_rng_probe(struct platform_device *pdev)
++{
++	int ret;
++	struct rk_rng *rk_rng;
++	struct device_node *np = pdev->dev.of_node;
++	const struct of_device_id *match;
++	resource_size_t map_size;
++
++	dev_dbg(&pdev->dev, "probing...\n");
++	rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
++	if (!rk_rng)
++		return -ENOMEM;
++
++	match = of_match_node(rk_rng_dt_match, np);
++	rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
++
++	rk_rng->dev = &pdev->dev;
++	rk_rng->rng.name    = "rockchip";
++#ifndef CONFIG_PM
++	rk_rng->rng.init    = rk_rng_init;
++	rk_rng->rng.cleanup = rk_rng_cleanup,
++#endif
++	rk_rng->rng.read    = rk_rng_read;
++	rk_rng->rng.quality = 999;
++
++	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
++	if (IS_ERR(rk_rng->mem))
++		return PTR_ERR(rk_rng->mem);
++
++	/* compatible with crypto v2 module */
++	/*
++	 * With old dtsi configurations, the RNG base was equal to the crypto
++	 * base, so both drivers could not be enabled at the same time.
++	 * RNG base = CRYPTO base + RNG offset
++	 * (Since RK356X, RNG module is no longer belongs to CRYPTO module)
++	 *
++	 * With new dtsi configurations, CRYPTO regs is divided into two parts
++	 * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
++	 * RNG driver and CRYPTO driver could be enabled at the same time.
++	 */
++	if (map_size > rk_rng->soc_data->default_offset)
++		rk_rng->mem += rk_rng->soc_data->default_offset;
++
++	rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
++	if (rk_rng->clk_num < 0) {
++		dev_err(&pdev->dev, "failed to get clks property\n");
++		return -ENODEV;
++	}
++
++	platform_set_drvdata(pdev, rk_rng);
++
++	pm_runtime_set_autosuspend_delay(&pdev->dev,
++					 ROCKCHIP_AUTOSUSPEND_DELAY);
++	pm_runtime_use_autosuspend(&pdev->dev);
++	pm_runtime_enable(&pdev->dev);
++
++	ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
++	if (ret) {
++		pm_runtime_dont_use_autosuspend(&pdev->dev);
++		pm_runtime_disable(&pdev->dev);
++	}
++
++	/* for some platform need hardware operation when probe */
++	if (rk_rng->soc_data->rk_rng_init) {
++		pm_runtime_get_sync(rk_rng->dev);
++
++		ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
++
++		pm_runtime_mark_last_busy(rk_rng->dev);
++		pm_runtime_put_sync_autosuspend(rk_rng->dev);
++	}
++
++	return ret;
++}
++
++#ifdef CONFIG_PM
++static int rk_rng_runtime_suspend(struct device *dev)
++{
++	struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++	rk_rng_cleanup(&rk_rng->rng);
++
++	return 0;
++}
++
++static int rk_rng_runtime_resume(struct device *dev)
++{
++	struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++	return rk_rng_init(&rk_rng->rng);
++}
++
++static const struct dev_pm_ops rk_rng_pm_ops = {
++	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
++			   rk_rng_runtime_resume, NULL)
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
++};
++
++#endif
++
++static struct platform_driver rk_rng_driver = {
++	.driver	= {
++		.name	= "rockchip-rng",
++#ifdef CONFIG_PM
++		.pm	= &rk_rng_pm_ops,
++#endif
++		.of_match_table = rk_rng_dt_match,
++	},
++	.probe	= rk_rng_probe,
++};
++
++module_platform_driver(rk_rng_driver);
++
++MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
++MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Fri, 2 Aug 2024 00:10:39 +0300
+Subject: arm64: dts: rockchip: rk3588: enable RNG node
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1774,6 +1774,16 @@ crypto: crypto@fe370000 {
+ 		reset-names = "core";
+ 	};
+ 
++	rng: rng@fe378000 {
++		compatible = "rockchip,trngv1";
++		reg = <0x0 0xfe378000 0x0 0x200>;
++		interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
++		clock-names = "hclk_trng";
++		resets = <&scmi_reset SRST_H_TRNG_NS>;
++		reset-names = "reset";
++	};
++
+ 	i2s0_8ch: i2s@fe470000 {
+ 		compatible = "rockchip,rk3588-i2s-tdm";
+ 		reg = <0x0 0xfe470000 0x0 0x1000>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch
new file mode 100644
index 000000000000..35298c4c4663
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch
@@ -0,0 +1,395 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
+Date: Thu, 18 Apr 2024 16:15:05 +0200
+Subject: media: dt-bindings: rk3568-vepu: Add RK3588 VEPU121
+
+This encoder-only device is present four times on this SoC, and should
+support everything the rk3568 vepu supports (so JPEG, H.264 and VP8
+encoding). No fallback compatible has been added, since the operating
+systems might already support RK3568 VEPU and want to avoid registering
+four of them separately considering they can be used as a cluster.
+
+Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
+@@ -17,6 +17,7 @@ properties:
+   compatible:
+     enum:
+       - rockchip,rk3568-vepu
++      - rockchip,rk3588-vepu121
+ 
+   reg:
+     maxItems: 1
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+Date: Tue, 30 Apr 2024 10:40:01 +0800
+Subject: media: dt-bindings: rockchip-vpu: Add RK3588 VPU121
+
+RK3588 has four Hantro H1 VEPUs (encoder-only) modules and one combined
+Hantro H1/G1 VPU (decoder and encoder). These are not described as
+separate IP, since they are sharing an internal cache. This adds the
+RK3588 specific compatible string for the combined VPU, which seems to
+be identical to the version found in the RK3568.
+
+Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+@@ -31,6 +31,9 @@ properties:
+       - items:
+           - const: rockchip,rk3228-vpu
+           - const: rockchip,rk3399-vpu
++      - items:
++          - const: rockchip,rk3588-vpu121
++          - const: rockchip,rk3568-vpu
+ 
+   reg:
+     maxItems: 1
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 13 Jun 2024 14:29:55 +0200
+Subject: media: hantro: Disable multicore support
+
+Avoid exposing equal Hantro video codecs to userspace. Equal video
+codecs allow scheduling work between the cores. For that kernel support
+is required, which does not yet exist. Until that is implemented avoid
+exposing each core separately to userspace so that multicore can be
+added in the future without breaking userspace ABI.
+
+This was written with Rockchip RK3588 in mind (which has 4 Hantro H1
+cores), but applies to all SoCs.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/media/platform/verisilicon/hantro_drv.c | 47 ++++++++++
+ 1 file changed, 47 insertions(+)
+
+diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/verisilicon/hantro_drv.c
++++ b/drivers/media/platform/verisilicon/hantro_drv.c
+@@ -992,6 +992,49 @@ static const struct media_device_ops hantro_m2m_media_ops = {
+ 	.req_queue = v4l2_m2m_request_queue,
+ };
+ 
++/*
++ * Some SoCs, like RK3588 have multiple identical Hantro cores, but the
++ * kernel is currently missing support for multi-core handling. Exposing
++ * separate devices for each core to userspace is bad, since that does
++ * not allow scheduling tasks properly (and creates ABI). With this workaround
++ * the driver will only probe for the first core and early exit for the other
++ * cores. Once the driver gains multi-core support, the same technique
++ * for detecting the main core can be used to cluster all cores together.
++ */
++static int hantro_disable_multicore(struct hantro_dev *vpu)
++{
++	struct device_node *node = NULL;
++	const char *compatible;
++	bool is_main_core;
++	int ret;
++
++	/* Intentionally ignores the fallback strings */
++	ret = of_property_read_string(vpu->dev->of_node, "compatible", &compatible);
++	if (ret)
++		return ret;
++
++	/* The first compatible and available node found is considered the main core */
++	do {
++		node = of_find_compatible_node(node, NULL, compatible);
++		if (of_device_is_available(node))
++			break;
++	} while (node);
++
++	if (!node)
++		return -EINVAL;
++
++	is_main_core = (vpu->dev->of_node == node);
++
++	of_node_put(node);
++
++	if (!is_main_core) {
++		dev_info(vpu->dev, "missing multi-core support, ignoring this instance\n");
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
+ static int hantro_probe(struct platform_device *pdev)
+ {
+ 	const struct of_device_id *match;
+@@ -1011,6 +1054,10 @@ static int hantro_probe(struct platform_device *pdev)
+ 	match = of_match_node(of_hantro_match, pdev->dev.of_node);
+ 	vpu->variant = match->data;
+ 
++	ret = hantro_disable_multicore(vpu);
++	if (ret)
++		return ret;
++
+ 	/*
+ 	 * Support for nxp,imx8mq-vpu is kept for backwards compatibility
+ 	 * but it's deprecated. Please update your DTS file to use
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 13 Jun 2024 14:48:43 +0200
+Subject: media: hantro: Add RK3588 VEPU121
+
+RK3588 handling is exactly the same as RK3568. This is not
+handled using fallback compatibles to avoid exposing multiple
+video devices on kernels not having the multicore disable
+patch.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/media/platform/verisilicon/hantro_drv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/verisilicon/hantro_drv.c
++++ b/drivers/media/platform/verisilicon/hantro_drv.c
+@@ -722,6 +722,7 @@ static const struct of_device_id of_hantro_match[] = {
+ 	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
+ 	{ .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
+ 	{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
++	{ .compatible = "rockchip,rk3588-vepu121", .data = &rk3568_vepu_variant, },
+ 	{ .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, },
+ #endif
+ #ifdef CONFIG_VIDEO_HANTRO_IMX8M
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
+Date: Wed, 5 Jun 2024 15:28:33 +0200
+Subject: arm64: dts: rockchip: Add VEPU121 to RK3588
+
+RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
+but can be used as a cluster (i.e. sharing work between the cores).
+These cores are called VEPU121 in the TRM. The TRM describes one more
+VEPU121, but that is combined with a Hantro H1. That one will be handled
+using the VPU binding instead.
+
+Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 80 ++++++++++
+ 1 file changed, 80 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1122,6 +1122,86 @@ power-domain@RK3588_PD_SDMMC {
+ 		};
+ 	};
+ 
++	vepu121_0: video-codec@fdba0000 {
++		compatible = "rockchip,rk3588-vepu121";
++		reg = <0x0 0xfdba0000 0x0 0x800>;
++		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
++		clock-names = "aclk", "hclk";
++		iommus = <&vepu121_0_mmu>;
++		power-domains = <&power RK3588_PD_VDPU>;
++	};
++
++	vepu121_0_mmu: iommu@fdba0800 {
++		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
++		reg = <0x0 0xfdba0800 0x0 0x40>;
++		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
++		clock-names = "aclk", "iface";
++		power-domains = <&power RK3588_PD_VDPU>;
++		#iommu-cells = <0>;
++	};
++
++	vepu121_1: video-codec@fdba4000 {
++		compatible = "rockchip,rk3588-vepu121";
++		reg = <0x0 0xfdba4000 0x0 0x800>;
++		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
++		clock-names = "aclk", "hclk";
++		iommus = <&vepu121_1_mmu>;
++		power-domains = <&power RK3588_PD_VDPU>;
++	};
++
++	vepu121_1_mmu: iommu@fdba4800 {
++		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
++		reg = <0x0 0xfdba4800 0x0 0x40>;
++		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
++		clock-names = "aclk", "iface";
++		power-domains = <&power RK3588_PD_VDPU>;
++		#iommu-cells = <0>;
++	};
++
++	vepu121_2: video-codec@fdba8000 {
++		compatible = "rockchip,rk3588-vepu121";
++		reg = <0x0 0xfdba8000 0x0 0x800>;
++		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
++		clock-names = "aclk", "hclk";
++		iommus = <&vepu121_2_mmu>;
++		power-domains = <&power RK3588_PD_VDPU>;
++	};
++
++	vepu121_2_mmu: iommu@fdba8800 {
++		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
++		reg = <0x0 0xfdba8800 0x0 0x40>;
++		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
++		clock-names = "aclk", "iface";
++		power-domains = <&power RK3588_PD_VDPU>;
++		#iommu-cells = <0>;
++	};
++
++	vepu121_3: video-codec@fdbac000 {
++		compatible = "rockchip,rk3588-vepu121";
++		reg = <0x0 0xfdbac000 0x0 0x800>;
++		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
++		clock-names = "aclk", "hclk";
++		iommus = <&vepu121_3_mmu>;
++		power-domains = <&power RK3588_PD_VDPU>;
++	};
++
++	vepu121_3_mmu: iommu@fdbac800 {
++		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
++		reg = <0x0 0xfdbac800 0x0 0x40>;
++		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
++		clock-names = "aclk", "iface";
++		power-domains = <&power RK3588_PD_VDPU>;
++		#iommu-cells = <0>;
++	};
++
+ 	av1d: video-codec@fdc70000 {
+ 		compatible = "rockchip,rk3588-av1-vpu";
+ 		reg = <0x0 0xfdc70000 0x0 0x800>;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+Date: Tue, 30 Apr 2024 10:40:02 +0800
+Subject: arm64: dts: rockchip: Add VPU121 support for RK3588
+
+Enable Hantro G1 video decoder in RK3588's devicetree.
+
+Tested with FFmpeg v4l2_request code taken from [1]
+with MPEG2, H.264 and VP8 samples.
+
+[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch
+
+Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
+Tested-by: Hugh Cole-Baker <sigmaris@gmail.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 21 ++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1122,6 +1122,27 @@ power-domain@RK3588_PD_SDMMC {
+ 		};
+ 	};
+ 
++	vpu121: video-codec@fdb50000 {
++		compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
++		reg = <0x0 0xfdb50000 0x0 0x800>;
++		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "vdpu";
++		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
++		clock-names = "aclk", "hclk";
++		iommus = <&vpu121_mmu>;
++		power-domains = <&power RK3588_PD_VDPU>;
++	};
++
++	vpu121_mmu: iommu@fdb50800 {
++		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
++		reg = <0x0 0xfdb50800 0x0 0x40>;
++		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
++		clock-names = "aclk", "iface";
++		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
++		power-domains = <&power RK3588_PD_VDPU>;
++		#iommu-cells = <0>;
++	};
++
+ 	vepu121_0: video-codec@fdba0000 {
+ 		compatible = "rockchip,rk3588-vepu121";
+ 		reg = <0x0 0xfdba0000 0x0 0x800>;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Mon, 29 Jul 2024 23:21:19 +0300
+Subject: arm64: dts: rockchip: rk3588: disable H264 decoding on Hantro decoder
+
+---
+ Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi             | 7 ++++---
+ 2 files changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+@@ -33,7 +33,7 @@ properties:
+           - const: rockchip,rk3399-vpu
+       - items:
+           - const: rockchip,rk3588-vpu121
+-          - const: rockchip,rk3568-vpu
++          - const: rockchip,rk3399-vpu
+ 
+   reg:
+     maxItems: 1
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1123,10 +1123,11 @@ power-domain@RK3588_PD_SDMMC {
+ 	};
+ 
+ 	vpu121: video-codec@fdb50000 {
+-		compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
++		compatible = "rockchip,rk3588-vpu121", "rockchip,rk3399-vpu";
+ 		reg = <0x0 0xfdb50000 0x0 0x800>;
+-		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+-		interrupt-names = "vdpu";
++		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "vepu", "vdpu";
+ 		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ 		clock-names = "aclk", "hclk";
+ 		iommus = <&vpu121_mmu>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0027-RK3588-Add-rkvdec2-Support-v3.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0027-RK3588-Add-rkvdec2-Support-v3.patch
new file mode 100644
index 000000000000..5687b1fb8a1a
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0027-RK3588-Add-rkvdec2-Support-v3.patch
@@ -0,0 +1,3887 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Tue, 18 Jun 2024 12:41:51 -0400
+Subject: media: rockchip: Move H264 CABAC table to header file
+
+The table will be shared with the rkvdec2 driver in following commits.
+
+As HW formatted CABAC tables can be shared between drivers, it makes sense
+to group them in an include folder.
+
+Each driver can include the tables they need so that all tables are not
+built in the kernel, but rather in each driver, if the driver is enabled.
+
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+---
+ drivers/staging/media/rkvdec/rkvdec-h264.c | 500 +--------
+ include/media/v4l2-cabac/rkvdec-cabac.h    | 509 ++++++++++
+ 2 files changed, 510 insertions(+), 499 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
+index 111111111111..222222222222 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
+@@ -11,6 +11,7 @@
+ 
+ #include <media/v4l2-h264.h>
+ #include <media/v4l2-mem2mem.h>
++#include <media/v4l2-cabac/rkvdec-cabac.h>
+ 
+ #include "rkvdec.h"
+ #include "rkvdec-regs.h"
+@@ -117,505 +118,6 @@ struct rkvdec_h264_ctx {
+ 	struct rkvdec_h264_reflists reflists;
+ };
+ 
+-#define CABAC_ENTRY(ctxidx, idc0_m, idc0_n, idc1_m, idc1_n,		\
+-	    idc2_m, idc2_n, intra_m, intra_n)			\
+-	[0][(ctxidx)] = {idc0_m, idc0_n},			\
+-	[1][(ctxidx)] = {idc1_m, idc1_n},			\
+-	[2][(ctxidx)] = {idc2_m, idc2_n},			\
+-	[3][(ctxidx)] = {intra_m, intra_n}
+-
+-/*
+- * Constant CABAC table.
+- * Built from the tables described in section '9.3.1.1 Initialisation process
+- * for context variables' of the H264 spec.
+- */
+-static const s8 rkvdec_h264_cabac_table[4][464][2] = {
+-	/* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */
+-	CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15),
+-	CABAC_ENTRY(1, 2, 54, 2, 54, 2, 54, 2, 54),
+-	CABAC_ENTRY(2, 3, 74, 3, 74, 3, 74, 3, 74),
+-	CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15),
+-	CABAC_ENTRY(4, 2, 54, 2, 54, 2, 54, 2, 54),
+-	CABAC_ENTRY(5, 3, 74, 3, 74, 3, 74, 3, 74),
+-	CABAC_ENTRY(6, -28, 127, -28, 127, -28, 127, -28, 127),
+-	CABAC_ENTRY(7, -23, 104, -23, 104, -23, 104, -23, 104),
+-	CABAC_ENTRY(8, -6, 53, -6, 53, -6, 53, -6, 53),
+-	CABAC_ENTRY(9, -1, 54, -1, 54, -1, 54, -1, 54),
+-	CABAC_ENTRY(10, 7, 51, 7, 51, 7, 51, 7, 51),
+-
+-	/* Table 9-13 – Values of variables m and n for ctxIdx from 11 to 23 */
+-	CABAC_ENTRY(11, 23, 33, 22, 25, 29, 16, 0, 0),
+-	CABAC_ENTRY(12, 23, 2, 34, 0, 25, 0, 0, 0),
+-	CABAC_ENTRY(13, 21, 0, 16, 0, 14, 0, 0, 0),
+-	CABAC_ENTRY(14, 1, 9, -2, 9, -10, 51, 0, 0),
+-	CABAC_ENTRY(15, 0, 49, 4, 41, -3, 62, 0, 0),
+-	CABAC_ENTRY(16, -37, 118, -29, 118, -27, 99, 0, 0),
+-	CABAC_ENTRY(17, 5, 57, 2, 65, 26, 16, 0, 0),
+-	CABAC_ENTRY(18, -13, 78, -6, 71, -4, 85, 0, 0),
+-	CABAC_ENTRY(19, -11, 65, -13, 79, -24, 102, 0, 0),
+-	CABAC_ENTRY(20, 1, 62, 5, 52, 5, 57, 0, 0),
+-	CABAC_ENTRY(21, 12, 49, 9, 50, 6, 57, 0, 0),
+-	CABAC_ENTRY(22, -4, 73, -3, 70, -17, 73, 0, 0),
+-	CABAC_ENTRY(23, 17, 50, 10, 54, 14, 57, 0, 0),
+-
+-	/* Table 9-14 – Values of variables m and n for ctxIdx from 24 to 39 */
+-	CABAC_ENTRY(24, 18, 64, 26, 34, 20, 40, 0, 0),
+-	CABAC_ENTRY(25, 9, 43, 19, 22, 20, 10, 0, 0),
+-	CABAC_ENTRY(26, 29, 0, 40, 0, 29, 0, 0, 0),
+-	CABAC_ENTRY(27, 26, 67, 57, 2, 54, 0, 0, 0),
+-	CABAC_ENTRY(28, 16, 90, 41, 36, 37, 42, 0, 0),
+-	CABAC_ENTRY(29, 9, 104, 26, 69, 12, 97, 0, 0),
+-	CABAC_ENTRY(30, -46, 127, -45, 127, -32, 127, 0, 0),
+-	CABAC_ENTRY(31, -20, 104, -15, 101, -22, 117, 0, 0),
+-	CABAC_ENTRY(32, 1, 67, -4, 76, -2, 74, 0, 0),
+-	CABAC_ENTRY(33, -13, 78, -6, 71, -4, 85, 0, 0),
+-	CABAC_ENTRY(34, -11, 65, -13, 79, -24, 102, 0, 0),
+-	CABAC_ENTRY(35, 1, 62, 5, 52, 5, 57, 0, 0),
+-	CABAC_ENTRY(36, -6, 86, 6, 69, -6, 93, 0, 0),
+-	CABAC_ENTRY(37, -17, 95, -13, 90, -14, 88, 0, 0),
+-	CABAC_ENTRY(38, -6, 61, 0, 52, -6, 44, 0, 0),
+-	CABAC_ENTRY(39, 9, 45, 8, 43, 4, 55, 0, 0),
+-
+-	/* Table 9-15 – Values of variables m and n for ctxIdx from 40 to 53 */
+-	CABAC_ENTRY(40, -3, 69, -2, 69, -11, 89, 0, 0),
+-	CABAC_ENTRY(41, -6, 81, -5, 82, -15, 103, 0, 0),
+-	CABAC_ENTRY(42, -11, 96, -10, 96, -21, 116, 0, 0),
+-	CABAC_ENTRY(43, 6, 55, 2, 59, 19, 57, 0, 0),
+-	CABAC_ENTRY(44, 7, 67, 2, 75, 20, 58, 0, 0),
+-	CABAC_ENTRY(45, -5, 86, -3, 87, 4, 84, 0, 0),
+-	CABAC_ENTRY(46, 2, 88, -3, 100, 6, 96, 0, 0),
+-	CABAC_ENTRY(47, 0, 58, 1, 56, 1, 63, 0, 0),
+-	CABAC_ENTRY(48, -3, 76, -3, 74, -5, 85, 0, 0),
+-	CABAC_ENTRY(49, -10, 94, -6, 85, -13, 106, 0, 0),
+-	CABAC_ENTRY(50, 5, 54, 0, 59, 5, 63, 0, 0),
+-	CABAC_ENTRY(51, 4, 69, -3, 81, 6, 75, 0, 0),
+-	CABAC_ENTRY(52, -3, 81, -7, 86, -3, 90, 0, 0),
+-	CABAC_ENTRY(53, 0, 88, -5, 95, -1, 101, 0, 0),
+-
+-	/* Table 9-16 – Values of variables m and n for ctxIdx from 54 to 59 */
+-	CABAC_ENTRY(54, -7, 67, -1, 66, 3, 55, 0, 0),
+-	CABAC_ENTRY(55, -5, 74, -1, 77, -4, 79, 0, 0),
+-	CABAC_ENTRY(56, -4, 74, 1, 70, -2, 75, 0, 0),
+-	CABAC_ENTRY(57, -5, 80, -2, 86, -12, 97, 0, 0),
+-	CABAC_ENTRY(58, -7, 72, -5, 72, -7, 50, 0, 0),
+-	CABAC_ENTRY(59, 1, 58, 0, 61, 1, 60, 0, 0),
+-
+-	/* Table 9-17 – Values of variables m and n for ctxIdx from 60 to 69 */
+-	CABAC_ENTRY(60, 0, 41, 0, 41, 0, 41, 0, 41),
+-	CABAC_ENTRY(61, 0, 63, 0, 63, 0, 63, 0, 63),
+-	CABAC_ENTRY(62, 0, 63, 0, 63, 0, 63, 0, 63),
+-	CABAC_ENTRY(63, 0, 63, 0, 63, 0, 63, 0, 63),
+-	CABAC_ENTRY(64, -9, 83, -9, 83, -9, 83, -9, 83),
+-	CABAC_ENTRY(65, 4, 86, 4, 86, 4, 86, 4, 86),
+-	CABAC_ENTRY(66, 0, 97, 0, 97, 0, 97, 0, 97),
+-	CABAC_ENTRY(67, -7, 72, -7, 72, -7, 72, -7, 72),
+-	CABAC_ENTRY(68, 13, 41, 13, 41, 13, 41, 13, 41),
+-	CABAC_ENTRY(69, 3, 62, 3, 62, 3, 62, 3, 62),
+-
+-	/* Table 9-18 – Values of variables m and n for ctxIdx from 70 to 104 */
+-	CABAC_ENTRY(70, 0, 45, 13, 15, 7, 34, 0, 11),
+-	CABAC_ENTRY(71, -4, 78, 7, 51, -9, 88, 1, 55),
+-	CABAC_ENTRY(72, -3, 96, 2, 80, -20, 127, 0, 69),
+-	CABAC_ENTRY(73, -27, 126, -39, 127, -36, 127, -17, 127),
+-	CABAC_ENTRY(74, -28, 98, -18, 91, -17, 91, -13, 102),
+-	CABAC_ENTRY(75, -25, 101, -17, 96, -14, 95, 0, 82),
+-	CABAC_ENTRY(76, -23, 67, -26, 81, -25, 84, -7, 74),
+-	CABAC_ENTRY(77, -28, 82, -35, 98, -25, 86, -21, 107),
+-	CABAC_ENTRY(78, -20, 94, -24, 102, -12, 89, -27, 127),
+-	CABAC_ENTRY(79, -16, 83, -23, 97, -17, 91, -31, 127),
+-	CABAC_ENTRY(80, -22, 110, -27, 119, -31, 127, -24, 127),
+-	CABAC_ENTRY(81, -21, 91, -24, 99, -14, 76, -18, 95),
+-	CABAC_ENTRY(82, -18, 102, -21, 110, -18, 103, -27, 127),
+-	CABAC_ENTRY(83, -13, 93, -18, 102, -13, 90, -21, 114),
+-	CABAC_ENTRY(84, -29, 127, -36, 127, -37, 127, -30, 127),
+-	CABAC_ENTRY(85, -7, 92, 0, 80, 11, 80, -17, 123),
+-	CABAC_ENTRY(86, -5, 89, -5, 89, 5, 76, -12, 115),
+-	CABAC_ENTRY(87, -7, 96, -7, 94, 2, 84, -16, 122),
+-	CABAC_ENTRY(88, -13, 108, -4, 92, 5, 78, -11, 115),
+-	CABAC_ENTRY(89, -3, 46, 0, 39, -6, 55, -12, 63),
+-	CABAC_ENTRY(90, -1, 65, 0, 65, 4, 61, -2, 68),
+-	CABAC_ENTRY(91, -1, 57, -15, 84, -14, 83, -15, 84),
+-	CABAC_ENTRY(92, -9, 93, -35, 127, -37, 127, -13, 104),
+-	CABAC_ENTRY(93, -3, 74, -2, 73, -5, 79, -3, 70),
+-	CABAC_ENTRY(94, -9, 92, -12, 104, -11, 104, -8, 93),
+-	CABAC_ENTRY(95, -8, 87, -9, 91, -11, 91, -10, 90),
+-	CABAC_ENTRY(96, -23, 126, -31, 127, -30, 127, -30, 127),
+-	CABAC_ENTRY(97, 5, 54, 3, 55, 0, 65, -1, 74),
+-	CABAC_ENTRY(98, 6, 60, 7, 56, -2, 79, -6, 97),
+-	CABAC_ENTRY(99, 6, 59, 7, 55, 0, 72, -7, 91),
+-	CABAC_ENTRY(100, 6, 69, 8, 61, -4, 92, -20, 127),
+-	CABAC_ENTRY(101, -1, 48, -3, 53, -6, 56, -4, 56),
+-	CABAC_ENTRY(102, 0, 68, 0, 68, 3, 68, -5, 82),
+-	CABAC_ENTRY(103, -4, 69, -7, 74, -8, 71, -7, 76),
+-	CABAC_ENTRY(104, -8, 88, -9, 88, -13, 98, -22, 125),
+-
+-	/* Table 9-19 – Values of variables m and n for ctxIdx from 105 to 165 */
+-	CABAC_ENTRY(105, -2, 85, -13, 103, -4, 86, -7, 93),
+-	CABAC_ENTRY(106, -6, 78, -13, 91, -12, 88, -11, 87),
+-	CABAC_ENTRY(107, -1, 75, -9, 89, -5, 82, -3, 77),
+-	CABAC_ENTRY(108, -7, 77, -14, 92, -3, 72, -5, 71),
+-	CABAC_ENTRY(109, 2, 54, -8, 76, -4, 67, -4, 63),
+-	CABAC_ENTRY(110, 5, 50, -12, 87, -8, 72, -4, 68),
+-	CABAC_ENTRY(111, -3, 68, -23, 110, -16, 89, -12, 84),
+-	CABAC_ENTRY(112, 1, 50, -24, 105, -9, 69, -7, 62),
+-	CABAC_ENTRY(113, 6, 42, -10, 78, -1, 59, -7, 65),
+-	CABAC_ENTRY(114, -4, 81, -20, 112, 5, 66, 8, 61),
+-	CABAC_ENTRY(115, 1, 63, -17, 99, 4, 57, 5, 56),
+-	CABAC_ENTRY(116, -4, 70, -78, 127, -4, 71, -2, 66),
+-	CABAC_ENTRY(117, 0, 67, -70, 127, -2, 71, 1, 64),
+-	CABAC_ENTRY(118, 2, 57, -50, 127, 2, 58, 0, 61),
+-	CABAC_ENTRY(119, -2, 76, -46, 127, -1, 74, -2, 78),
+-	CABAC_ENTRY(120, 11, 35, -4, 66, -4, 44, 1, 50),
+-	CABAC_ENTRY(121, 4, 64, -5, 78, -1, 69, 7, 52),
+-	CABAC_ENTRY(122, 1, 61, -4, 71, 0, 62, 10, 35),
+-	CABAC_ENTRY(123, 11, 35, -8, 72, -7, 51, 0, 44),
+-	CABAC_ENTRY(124, 18, 25, 2, 59, -4, 47, 11, 38),
+-	CABAC_ENTRY(125, 12, 24, -1, 55, -6, 42, 1, 45),
+-	CABAC_ENTRY(126, 13, 29, -7, 70, -3, 41, 0, 46),
+-	CABAC_ENTRY(127, 13, 36, -6, 75, -6, 53, 5, 44),
+-	CABAC_ENTRY(128, -10, 93, -8, 89, 8, 76, 31, 17),
+-	CABAC_ENTRY(129, -7, 73, -34, 119, -9, 78, 1, 51),
+-	CABAC_ENTRY(130, -2, 73, -3, 75, -11, 83, 7, 50),
+-	CABAC_ENTRY(131, 13, 46, 32, 20, 9, 52, 28, 19),
+-	CABAC_ENTRY(132, 9, 49, 30, 22, 0, 67, 16, 33),
+-	CABAC_ENTRY(133, -7, 100, -44, 127, -5, 90, 14, 62),
+-	CABAC_ENTRY(134, 9, 53, 0, 54, 1, 67, -13, 108),
+-	CABAC_ENTRY(135, 2, 53, -5, 61, -15, 72, -15, 100),
+-	CABAC_ENTRY(136, 5, 53, 0, 58, -5, 75, -13, 101),
+-	CABAC_ENTRY(137, -2, 61, -1, 60, -8, 80, -13, 91),
+-	CABAC_ENTRY(138, 0, 56, -3, 61, -21, 83, -12, 94),
+-	CABAC_ENTRY(139, 0, 56, -8, 67, -21, 64, -10, 88),
+-	CABAC_ENTRY(140, -13, 63, -25, 84, -13, 31, -16, 84),
+-	CABAC_ENTRY(141, -5, 60, -14, 74, -25, 64, -10, 86),
+-	CABAC_ENTRY(142, -1, 62, -5, 65, -29, 94, -7, 83),
+-	CABAC_ENTRY(143, 4, 57, 5, 52, 9, 75, -13, 87),
+-	CABAC_ENTRY(144, -6, 69, 2, 57, 17, 63, -19, 94),
+-	CABAC_ENTRY(145, 4, 57, 0, 61, -8, 74, 1, 70),
+-	CABAC_ENTRY(146, 14, 39, -9, 69, -5, 35, 0, 72),
+-	CABAC_ENTRY(147, 4, 51, -11, 70, -2, 27, -5, 74),
+-	CABAC_ENTRY(148, 13, 68, 18, 55, 13, 91, 18, 59),
+-	CABAC_ENTRY(149, 3, 64, -4, 71, 3, 65, -8, 102),
+-	CABAC_ENTRY(150, 1, 61, 0, 58, -7, 69, -15, 100),
+-	CABAC_ENTRY(151, 9, 63, 7, 61, 8, 77, 0, 95),
+-	CABAC_ENTRY(152, 7, 50, 9, 41, -10, 66, -4, 75),
+-	CABAC_ENTRY(153, 16, 39, 18, 25, 3, 62, 2, 72),
+-	CABAC_ENTRY(154, 5, 44, 9, 32, -3, 68, -11, 75),
+-	CABAC_ENTRY(155, 4, 52, 5, 43, -20, 81, -3, 71),
+-	CABAC_ENTRY(156, 11, 48, 9, 47, 0, 30, 15, 46),
+-	CABAC_ENTRY(157, -5, 60, 0, 44, 1, 7, -13, 69),
+-	CABAC_ENTRY(158, -1, 59, 0, 51, -3, 23, 0, 62),
+-	CABAC_ENTRY(159, 0, 59, 2, 46, -21, 74, 0, 65),
+-	CABAC_ENTRY(160, 22, 33, 19, 38, 16, 66, 21, 37),
+-	CABAC_ENTRY(161, 5, 44, -4, 66, -23, 124, -15, 72),
+-	CABAC_ENTRY(162, 14, 43, 15, 38, 17, 37, 9, 57),
+-	CABAC_ENTRY(163, -1, 78, 12, 42, 44, -18, 16, 54),
+-	CABAC_ENTRY(164, 0, 60, 9, 34, 50, -34, 0, 62),
+-	CABAC_ENTRY(165, 9, 69, 0, 89, -22, 127, 12, 72),
+-
+-	/* Table 9-20 – Values of variables m and n for ctxIdx from 166 to 226 */
+-	CABAC_ENTRY(166, 11, 28, 4, 45, 4, 39, 24, 0),
+-	CABAC_ENTRY(167, 2, 40, 10, 28, 0, 42, 15, 9),
+-	CABAC_ENTRY(168, 3, 44, 10, 31, 7, 34, 8, 25),
+-	CABAC_ENTRY(169, 0, 49, 33, -11, 11, 29, 13, 18),
+-	CABAC_ENTRY(170, 0, 46, 52, -43, 8, 31, 15, 9),
+-	CABAC_ENTRY(171, 2, 44, 18, 15, 6, 37, 13, 19),
+-	CABAC_ENTRY(172, 2, 51, 28, 0, 7, 42, 10, 37),
+-	CABAC_ENTRY(173, 0, 47, 35, -22, 3, 40, 12, 18),
+-	CABAC_ENTRY(174, 4, 39, 38, -25, 8, 33, 6, 29),
+-	CABAC_ENTRY(175, 2, 62, 34, 0, 13, 43, 20, 33),
+-	CABAC_ENTRY(176, 6, 46, 39, -18, 13, 36, 15, 30),
+-	CABAC_ENTRY(177, 0, 54, 32, -12, 4, 47, 4, 45),
+-	CABAC_ENTRY(178, 3, 54, 102, -94, 3, 55, 1, 58),
+-	CABAC_ENTRY(179, 2, 58, 0, 0, 2, 58, 0, 62),
+-	CABAC_ENTRY(180, 4, 63, 56, -15, 6, 60, 7, 61),
+-	CABAC_ENTRY(181, 6, 51, 33, -4, 8, 44, 12, 38),
+-	CABAC_ENTRY(182, 6, 57, 29, 10, 11, 44, 11, 45),
+-	CABAC_ENTRY(183, 7, 53, 37, -5, 14, 42, 15, 39),
+-	CABAC_ENTRY(184, 6, 52, 51, -29, 7, 48, 11, 42),
+-	CABAC_ENTRY(185, 6, 55, 39, -9, 4, 56, 13, 44),
+-	CABAC_ENTRY(186, 11, 45, 52, -34, 4, 52, 16, 45),
+-	CABAC_ENTRY(187, 14, 36, 69, -58, 13, 37, 12, 41),
+-	CABAC_ENTRY(188, 8, 53, 67, -63, 9, 49, 10, 49),
+-	CABAC_ENTRY(189, -1, 82, 44, -5, 19, 58, 30, 34),
+-	CABAC_ENTRY(190, 7, 55, 32, 7, 10, 48, 18, 42),
+-	CABAC_ENTRY(191, -3, 78, 55, -29, 12, 45, 10, 55),
+-	CABAC_ENTRY(192, 15, 46, 32, 1, 0, 69, 17, 51),
+-	CABAC_ENTRY(193, 22, 31, 0, 0, 20, 33, 17, 46),
+-	CABAC_ENTRY(194, -1, 84, 27, 36, 8, 63, 0, 89),
+-	CABAC_ENTRY(195, 25, 7, 33, -25, 35, -18, 26, -19),
+-	CABAC_ENTRY(196, 30, -7, 34, -30, 33, -25, 22, -17),
+-	CABAC_ENTRY(197, 28, 3, 36, -28, 28, -3, 26, -17),
+-	CABAC_ENTRY(198, 28, 4, 38, -28, 24, 10, 30, -25),
+-	CABAC_ENTRY(199, 32, 0, 38, -27, 27, 0, 28, -20),
+-	CABAC_ENTRY(200, 34, -1, 34, -18, 34, -14, 33, -23),
+-	CABAC_ENTRY(201, 30, 6, 35, -16, 52, -44, 37, -27),
+-	CABAC_ENTRY(202, 30, 6, 34, -14, 39, -24, 33, -23),
+-	CABAC_ENTRY(203, 32, 9, 32, -8, 19, 17, 40, -28),
+-	CABAC_ENTRY(204, 31, 19, 37, -6, 31, 25, 38, -17),
+-	CABAC_ENTRY(205, 26, 27, 35, 0, 36, 29, 33, -11),
+-	CABAC_ENTRY(206, 26, 30, 30, 10, 24, 33, 40, -15),
+-	CABAC_ENTRY(207, 37, 20, 28, 18, 34, 15, 41, -6),
+-	CABAC_ENTRY(208, 28, 34, 26, 25, 30, 20, 38, 1),
+-	CABAC_ENTRY(209, 17, 70, 29, 41, 22, 73, 41, 17),
+-	CABAC_ENTRY(210, 1, 67, 0, 75, 20, 34, 30, -6),
+-	CABAC_ENTRY(211, 5, 59, 2, 72, 19, 31, 27, 3),
+-	CABAC_ENTRY(212, 9, 67, 8, 77, 27, 44, 26, 22),
+-	CABAC_ENTRY(213, 16, 30, 14, 35, 19, 16, 37, -16),
+-	CABAC_ENTRY(214, 18, 32, 18, 31, 15, 36, 35, -4),
+-	CABAC_ENTRY(215, 18, 35, 17, 35, 15, 36, 38, -8),
+-	CABAC_ENTRY(216, 22, 29, 21, 30, 21, 28, 38, -3),
+-	CABAC_ENTRY(217, 24, 31, 17, 45, 25, 21, 37, 3),
+-	CABAC_ENTRY(218, 23, 38, 20, 42, 30, 20, 38, 5),
+-	CABAC_ENTRY(219, 18, 43, 18, 45, 31, 12, 42, 0),
+-	CABAC_ENTRY(220, 20, 41, 27, 26, 27, 16, 35, 16),
+-	CABAC_ENTRY(221, 11, 63, 16, 54, 24, 42, 39, 22),
+-	CABAC_ENTRY(222, 9, 59, 7, 66, 0, 93, 14, 48),
+-	CABAC_ENTRY(223, 9, 64, 16, 56, 14, 56, 27, 37),
+-	CABAC_ENTRY(224, -1, 94, 11, 73, 15, 57, 21, 60),
+-	CABAC_ENTRY(225, -2, 89, 10, 67, 26, 38, 12, 68),
+-	CABAC_ENTRY(226, -9, 108, -10, 116, -24, 127, 2, 97),
+-
+-	/* Table 9-21 – Values of variables m and n for ctxIdx from 227 to 275 */
+-	CABAC_ENTRY(227, -6, 76, -23, 112, -24, 115, -3, 71),
+-	CABAC_ENTRY(228, -2, 44, -15, 71, -22, 82, -6, 42),
+-	CABAC_ENTRY(229, 0, 45, -7, 61, -9, 62, -5, 50),
+-	CABAC_ENTRY(230, 0, 52, 0, 53, 0, 53, -3, 54),
+-	CABAC_ENTRY(231, -3, 64, -5, 66, 0, 59, -2, 62),
+-	CABAC_ENTRY(232, -2, 59, -11, 77, -14, 85, 0, 58),
+-	CABAC_ENTRY(233, -4, 70, -9, 80, -13, 89, 1, 63),
+-	CABAC_ENTRY(234, -4, 75, -9, 84, -13, 94, -2, 72),
+-	CABAC_ENTRY(235, -8, 82, -10, 87, -11, 92, -1, 74),
+-	CABAC_ENTRY(236, -17, 102, -34, 127, -29, 127, -9, 91),
+-	CABAC_ENTRY(237, -9, 77, -21, 101, -21, 100, -5, 67),
+-	CABAC_ENTRY(238, 3, 24, -3, 39, -14, 57, -5, 27),
+-	CABAC_ENTRY(239, 0, 42, -5, 53, -12, 67, -3, 39),
+-	CABAC_ENTRY(240, 0, 48, -7, 61, -11, 71, -2, 44),
+-	CABAC_ENTRY(241, 0, 55, -11, 75, -10, 77, 0, 46),
+-	CABAC_ENTRY(242, -6, 59, -15, 77, -21, 85, -16, 64),
+-	CABAC_ENTRY(243, -7, 71, -17, 91, -16, 88, -8, 68),
+-	CABAC_ENTRY(244, -12, 83, -25, 107, -23, 104, -10, 78),
+-	CABAC_ENTRY(245, -11, 87, -25, 111, -15, 98, -6, 77),
+-	CABAC_ENTRY(246, -30, 119, -28, 122, -37, 127, -10, 86),
+-	CABAC_ENTRY(247, 1, 58, -11, 76, -10, 82, -12, 92),
+-	CABAC_ENTRY(248, -3, 29, -10, 44, -8, 48, -15, 55),
+-	CABAC_ENTRY(249, -1, 36, -10, 52, -8, 61, -10, 60),
+-	CABAC_ENTRY(250, 1, 38, -10, 57, -8, 66, -6, 62),
+-	CABAC_ENTRY(251, 2, 43, -9, 58, -7, 70, -4, 65),
+-	CABAC_ENTRY(252, -6, 55, -16, 72, -14, 75, -12, 73),
+-	CABAC_ENTRY(253, 0, 58, -7, 69, -10, 79, -8, 76),
+-	CABAC_ENTRY(254, 0, 64, -4, 69, -9, 83, -7, 80),
+-	CABAC_ENTRY(255, -3, 74, -5, 74, -12, 92, -9, 88),
+-	CABAC_ENTRY(256, -10, 90, -9, 86, -18, 108, -17, 110),
+-	CABAC_ENTRY(257, 0, 70, 2, 66, -4, 79, -11, 97),
+-	CABAC_ENTRY(258, -4, 29, -9, 34, -22, 69, -20, 84),
+-	CABAC_ENTRY(259, 5, 31, 1, 32, -16, 75, -11, 79),
+-	CABAC_ENTRY(260, 7, 42, 11, 31, -2, 58, -6, 73),
+-	CABAC_ENTRY(261, 1, 59, 5, 52, 1, 58, -4, 74),
+-	CABAC_ENTRY(262, -2, 58, -2, 55, -13, 78, -13, 86),
+-	CABAC_ENTRY(263, -3, 72, -2, 67, -9, 83, -13, 96),
+-	CABAC_ENTRY(264, -3, 81, 0, 73, -4, 81, -11, 97),
+-	CABAC_ENTRY(265, -11, 97, -8, 89, -13, 99, -19, 117),
+-	CABAC_ENTRY(266, 0, 58, 3, 52, -13, 81, -8, 78),
+-	CABAC_ENTRY(267, 8, 5, 7, 4, -6, 38, -5, 33),
+-	CABAC_ENTRY(268, 10, 14, 10, 8, -13, 62, -4, 48),
+-	CABAC_ENTRY(269, 14, 18, 17, 8, -6, 58, -2, 53),
+-	CABAC_ENTRY(270, 13, 27, 16, 19, -2, 59, -3, 62),
+-	CABAC_ENTRY(271, 2, 40, 3, 37, -16, 73, -13, 71),
+-	CABAC_ENTRY(272, 0, 58, -1, 61, -10, 76, -10, 79),
+-	CABAC_ENTRY(273, -3, 70, -5, 73, -13, 86, -12, 86),
+-	CABAC_ENTRY(274, -6, 79, -1, 70, -9, 83, -13, 90),
+-	CABAC_ENTRY(275, -8, 85, -4, 78, -10, 87, -14, 97),
+-
+-	/* Table 9-22 – Values of variables m and n for ctxIdx from 277 to 337 */
+-	CABAC_ENTRY(277, -13, 106, -21, 126, -22, 127, -6, 93),
+-	CABAC_ENTRY(278, -16, 106, -23, 124, -25, 127, -6, 84),
+-	CABAC_ENTRY(279, -10, 87, -20, 110, -25, 120, -8, 79),
+-	CABAC_ENTRY(280, -21, 114, -26, 126, -27, 127, 0, 66),
+-	CABAC_ENTRY(281, -18, 110, -25, 124, -19, 114, -1, 71),
+-	CABAC_ENTRY(282, -14, 98, -17, 105, -23, 117, 0, 62),
+-	CABAC_ENTRY(283, -22, 110, -27, 121, -25, 118, -2, 60),
+-	CABAC_ENTRY(284, -21, 106, -27, 117, -26, 117, -2, 59),
+-	CABAC_ENTRY(285, -18, 103, -17, 102, -24, 113, -5, 75),
+-	CABAC_ENTRY(286, -21, 107, -26, 117, -28, 118, -3, 62),
+-	CABAC_ENTRY(287, -23, 108, -27, 116, -31, 120, -4, 58),
+-	CABAC_ENTRY(288, -26, 112, -33, 122, -37, 124, -9, 66),
+-	CABAC_ENTRY(289, -10, 96, -10, 95, -10, 94, -1, 79),
+-	CABAC_ENTRY(290, -12, 95, -14, 100, -15, 102, 0, 71),
+-	CABAC_ENTRY(291, -5, 91, -8, 95, -10, 99, 3, 68),
+-	CABAC_ENTRY(292, -9, 93, -17, 111, -13, 106, 10, 44),
+-	CABAC_ENTRY(293, -22, 94, -28, 114, -50, 127, -7, 62),
+-	CABAC_ENTRY(294, -5, 86, -6, 89, -5, 92, 15, 36),
+-	CABAC_ENTRY(295, 9, 67, -2, 80, 17, 57, 14, 40),
+-	CABAC_ENTRY(296, -4, 80, -4, 82, -5, 86, 16, 27),
+-	CABAC_ENTRY(297, -10, 85, -9, 85, -13, 94, 12, 29),
+-	CABAC_ENTRY(298, -1, 70, -8, 81, -12, 91, 1, 44),
+-	CABAC_ENTRY(299, 7, 60, -1, 72, -2, 77, 20, 36),
+-	CABAC_ENTRY(300, 9, 58, 5, 64, 0, 71, 18, 32),
+-	CABAC_ENTRY(301, 5, 61, 1, 67, -1, 73, 5, 42),
+-	CABAC_ENTRY(302, 12, 50, 9, 56, 4, 64, 1, 48),
+-	CABAC_ENTRY(303, 15, 50, 0, 69, -7, 81, 10, 62),
+-	CABAC_ENTRY(304, 18, 49, 1, 69, 5, 64, 17, 46),
+-	CABAC_ENTRY(305, 17, 54, 7, 69, 15, 57, 9, 64),
+-	CABAC_ENTRY(306, 10, 41, -7, 69, 1, 67, -12, 104),
+-	CABAC_ENTRY(307, 7, 46, -6, 67, 0, 68, -11, 97),
+-	CABAC_ENTRY(308, -1, 51, -16, 77, -10, 67, -16, 96),
+-	CABAC_ENTRY(309, 7, 49, -2, 64, 1, 68, -7, 88),
+-	CABAC_ENTRY(310, 8, 52, 2, 61, 0, 77, -8, 85),
+-	CABAC_ENTRY(311, 9, 41, -6, 67, 2, 64, -7, 85),
+-	CABAC_ENTRY(312, 6, 47, -3, 64, 0, 68, -9, 85),
+-	CABAC_ENTRY(313, 2, 55, 2, 57, -5, 78, -13, 88),
+-	CABAC_ENTRY(314, 13, 41, -3, 65, 7, 55, 4, 66),
+-	CABAC_ENTRY(315, 10, 44, -3, 66, 5, 59, -3, 77),
+-	CABAC_ENTRY(316, 6, 50, 0, 62, 2, 65, -3, 76),
+-	CABAC_ENTRY(317, 5, 53, 9, 51, 14, 54, -6, 76),
+-	CABAC_ENTRY(318, 13, 49, -1, 66, 15, 44, 10, 58),
+-	CABAC_ENTRY(319, 4, 63, -2, 71, 5, 60, -1, 76),
+-	CABAC_ENTRY(320, 6, 64, -2, 75, 2, 70, -1, 83),
+-	CABAC_ENTRY(321, -2, 69, -1, 70, -2, 76, -7, 99),
+-	CABAC_ENTRY(322, -2, 59, -9, 72, -18, 86, -14, 95),
+-	CABAC_ENTRY(323, 6, 70, 14, 60, 12, 70, 2, 95),
+-	CABAC_ENTRY(324, 10, 44, 16, 37, 5, 64, 0, 76),
+-	CABAC_ENTRY(325, 9, 31, 0, 47, -12, 70, -5, 74),
+-	CABAC_ENTRY(326, 12, 43, 18, 35, 11, 55, 0, 70),
+-	CABAC_ENTRY(327, 3, 53, 11, 37, 5, 56, -11, 75),
+-	CABAC_ENTRY(328, 14, 34, 12, 41, 0, 69, 1, 68),
+-	CABAC_ENTRY(329, 10, 38, 10, 41, 2, 65, 0, 65),
+-	CABAC_ENTRY(330, -3, 52, 2, 48, -6, 74, -14, 73),
+-	CABAC_ENTRY(331, 13, 40, 12, 41, 5, 54, 3, 62),
+-	CABAC_ENTRY(332, 17, 32, 13, 41, 7, 54, 4, 62),
+-	CABAC_ENTRY(333, 7, 44, 0, 59, -6, 76, -1, 68),
+-	CABAC_ENTRY(334, 7, 38, 3, 50, -11, 82, -13, 75),
+-	CABAC_ENTRY(335, 13, 50, 19, 40, -2, 77, 11, 55),
+-	CABAC_ENTRY(336, 10, 57, 3, 66, -2, 77, 5, 64),
+-	CABAC_ENTRY(337, 26, 43, 18, 50, 25, 42, 12, 70),
+-
+-	/* Table 9-23 – Values of variables m and n for ctxIdx from 338 to 398 */
+-	CABAC_ENTRY(338, 14, 11, 19, -6, 17, -13, 15, 6),
+-	CABAC_ENTRY(339, 11, 14, 18, -6, 16, -9, 6, 19),
+-	CABAC_ENTRY(340, 9, 11, 14, 0, 17, -12, 7, 16),
+-	CABAC_ENTRY(341, 18, 11, 26, -12, 27, -21, 12, 14),
+-	CABAC_ENTRY(342, 21, 9, 31, -16, 37, -30, 18, 13),
+-	CABAC_ENTRY(343, 23, -2, 33, -25, 41, -40, 13, 11),
+-	CABAC_ENTRY(344, 32, -15, 33, -22, 42, -41, 13, 15),
+-	CABAC_ENTRY(345, 32, -15, 37, -28, 48, -47, 15, 16),
+-	CABAC_ENTRY(346, 34, -21, 39, -30, 39, -32, 12, 23),
+-	CABAC_ENTRY(347, 39, -23, 42, -30, 46, -40, 13, 23),
+-	CABAC_ENTRY(348, 42, -33, 47, -42, 52, -51, 15, 20),
+-	CABAC_ENTRY(349, 41, -31, 45, -36, 46, -41, 14, 26),
+-	CABAC_ENTRY(350, 46, -28, 49, -34, 52, -39, 14, 44),
+-	CABAC_ENTRY(351, 38, -12, 41, -17, 43, -19, 17, 40),
+-	CABAC_ENTRY(352, 21, 29, 32, 9, 32, 11, 17, 47),
+-	CABAC_ENTRY(353, 45, -24, 69, -71, 61, -55, 24, 17),
+-	CABAC_ENTRY(354, 53, -45, 63, -63, 56, -46, 21, 21),
+-	CABAC_ENTRY(355, 48, -26, 66, -64, 62, -50, 25, 22),
+-	CABAC_ENTRY(356, 65, -43, 77, -74, 81, -67, 31, 27),
+-	CABAC_ENTRY(357, 43, -19, 54, -39, 45, -20, 22, 29),
+-	CABAC_ENTRY(358, 39, -10, 52, -35, 35, -2, 19, 35),
+-	CABAC_ENTRY(359, 30, 9, 41, -10, 28, 15, 14, 50),
+-	CABAC_ENTRY(360, 18, 26, 36, 0, 34, 1, 10, 57),
+-	CABAC_ENTRY(361, 20, 27, 40, -1, 39, 1, 7, 63),
+-	CABAC_ENTRY(362, 0, 57, 30, 14, 30, 17, -2, 77),
+-	CABAC_ENTRY(363, -14, 82, 28, 26, 20, 38, -4, 82),
+-	CABAC_ENTRY(364, -5, 75, 23, 37, 18, 45, -3, 94),
+-	CABAC_ENTRY(365, -19, 97, 12, 55, 15, 54, 9, 69),
+-	CABAC_ENTRY(366, -35, 125, 11, 65, 0, 79, -12, 109),
+-	CABAC_ENTRY(367, 27, 0, 37, -33, 36, -16, 36, -35),
+-	CABAC_ENTRY(368, 28, 0, 39, -36, 37, -14, 36, -34),
+-	CABAC_ENTRY(369, 31, -4, 40, -37, 37, -17, 32, -26),
+-	CABAC_ENTRY(370, 27, 6, 38, -30, 32, 1, 37, -30),
+-	CABAC_ENTRY(371, 34, 8, 46, -33, 34, 15, 44, -32),
+-	CABAC_ENTRY(372, 30, 10, 42, -30, 29, 15, 34, -18),
+-	CABAC_ENTRY(373, 24, 22, 40, -24, 24, 25, 34, -15),
+-	CABAC_ENTRY(374, 33, 19, 49, -29, 34, 22, 40, -15),
+-	CABAC_ENTRY(375, 22, 32, 38, -12, 31, 16, 33, -7),
+-	CABAC_ENTRY(376, 26, 31, 40, -10, 35, 18, 35, -5),
+-	CABAC_ENTRY(377, 21, 41, 38, -3, 31, 28, 33, 0),
+-	CABAC_ENTRY(378, 26, 44, 46, -5, 33, 41, 38, 2),
+-	CABAC_ENTRY(379, 23, 47, 31, 20, 36, 28, 33, 13),
+-	CABAC_ENTRY(380, 16, 65, 29, 30, 27, 47, 23, 35),
+-	CABAC_ENTRY(381, 14, 71, 25, 44, 21, 62, 13, 58),
+-	CABAC_ENTRY(382, 8, 60, 12, 48, 18, 31, 29, -3),
+-	CABAC_ENTRY(383, 6, 63, 11, 49, 19, 26, 26, 0),
+-	CABAC_ENTRY(384, 17, 65, 26, 45, 36, 24, 22, 30),
+-	CABAC_ENTRY(385, 21, 24, 22, 22, 24, 23, 31, -7),
+-	CABAC_ENTRY(386, 23, 20, 23, 22, 27, 16, 35, -15),
+-	CABAC_ENTRY(387, 26, 23, 27, 21, 24, 30, 34, -3),
+-	CABAC_ENTRY(388, 27, 32, 33, 20, 31, 29, 34, 3),
+-	CABAC_ENTRY(389, 28, 23, 26, 28, 22, 41, 36, -1),
+-	CABAC_ENTRY(390, 28, 24, 30, 24, 22, 42, 34, 5),
+-	CABAC_ENTRY(391, 23, 40, 27, 34, 16, 60, 32, 11),
+-	CABAC_ENTRY(392, 24, 32, 18, 42, 15, 52, 35, 5),
+-	CABAC_ENTRY(393, 28, 29, 25, 39, 14, 60, 34, 12),
+-	CABAC_ENTRY(394, 23, 42, 18, 50, 3, 78, 39, 11),
+-	CABAC_ENTRY(395, 19, 57, 12, 70, -16, 123, 30, 29),
+-	CABAC_ENTRY(396, 22, 53, 21, 54, 21, 53, 34, 26),
+-	CABAC_ENTRY(397, 22, 61, 14, 71, 22, 56, 29, 39),
+-	CABAC_ENTRY(398, 11, 86, 11, 83, 25, 61, 19, 66),
+-
+-	/* Values of variables m and n for ctxIdx from 399 to 463 (not documented) */
+-	CABAC_ENTRY(399, 12, 40, 25, 32, 21, 33, 31, 21),
+-	CABAC_ENTRY(400, 11, 51, 21, 49, 19, 50, 31, 31),
+-	CABAC_ENTRY(401, 14, 59, 21, 54, 17, 61, 25, 50),
+-	CABAC_ENTRY(402, -4, 79, -5, 85, -3, 78, -17, 120),
+-	CABAC_ENTRY(403, -7, 71, -6, 81, -8, 74, -20, 112),
+-	CABAC_ENTRY(404, -5, 69, -10, 77, -9, 72, -18, 114),
+-	CABAC_ENTRY(405, -9, 70, -7, 81, -10, 72, -11, 85),
+-	CABAC_ENTRY(406, -8, 66, -17, 80, -18, 75, -15, 92),
+-	CABAC_ENTRY(407, -10, 68, -18, 73, -12, 71, -14, 89),
+-	CABAC_ENTRY(408, -19, 73, -4, 74, -11, 63, -26, 71),
+-	CABAC_ENTRY(409, -12, 69, -10, 83, -5, 70, -15, 81),
+-	CABAC_ENTRY(410, -16, 70, -9, 71, -17, 75, -14, 80),
+-	CABAC_ENTRY(411, -15, 67, -9, 67, -14, 72, 0, 68),
+-	CABAC_ENTRY(412, -20, 62, -1, 61, -16, 67, -14, 70),
+-	CABAC_ENTRY(413, -19, 70, -8, 66, -8, 53, -24, 56),
+-	CABAC_ENTRY(414, -16, 66, -14, 66, -14, 59, -23, 68),
+-	CABAC_ENTRY(415, -22, 65, 0, 59, -9, 52, -24, 50),
+-	CABAC_ENTRY(416, -20, 63, 2, 59, -11, 68, -11, 74),
+-	CABAC_ENTRY(417, 9, -2, 17, -10, 9, -2, 23, -13),
+-	CABAC_ENTRY(418, 26, -9, 32, -13, 30, -10, 26, -13),
+-	CABAC_ENTRY(419, 33, -9, 42, -9, 31, -4, 40, -15),
+-	CABAC_ENTRY(420, 39, -7, 49, -5, 33, -1, 49, -14),
+-	CABAC_ENTRY(421, 41, -2, 53, 0, 33, 7, 44, 3),
+-	CABAC_ENTRY(422, 45, 3, 64, 3, 31, 12, 45, 6),
+-	CABAC_ENTRY(423, 49, 9, 68, 10, 37, 23, 44, 34),
+-	CABAC_ENTRY(424, 45, 27, 66, 27, 31, 38, 33, 54),
+-	CABAC_ENTRY(425, 36, 59, 47, 57, 20, 64, 19, 82),
+-	CABAC_ENTRY(426, -6, 66, -5, 71, -9, 71, -3, 75),
+-	CABAC_ENTRY(427, -7, 35, 0, 24, -7, 37, -1, 23),
+-	CABAC_ENTRY(428, -7, 42, -1, 36, -8, 44, 1, 34),
+-	CABAC_ENTRY(429, -8, 45, -2, 42, -11, 49, 1, 43),
+-	CABAC_ENTRY(430, -5, 48, -2, 52, -10, 56, 0, 54),
+-	CABAC_ENTRY(431, -12, 56, -9, 57, -12, 59, -2, 55),
+-	CABAC_ENTRY(432, -6, 60, -6, 63, -8, 63, 0, 61),
+-	CABAC_ENTRY(433, -5, 62, -4, 65, -9, 67, 1, 64),
+-	CABAC_ENTRY(434, -8, 66, -4, 67, -6, 68, 0, 68),
+-	CABAC_ENTRY(435, -8, 76, -7, 82, -10, 79, -9, 92),
+-	CABAC_ENTRY(436, -5, 85, -3, 81, -3, 78, -14, 106),
+-	CABAC_ENTRY(437, -6, 81, -3, 76, -8, 74, -13, 97),
+-	CABAC_ENTRY(438, -10, 77, -7, 72, -9, 72, -15, 90),
+-	CABAC_ENTRY(439, -7, 81, -6, 78, -10, 72, -12, 90),
+-	CABAC_ENTRY(440, -17, 80, -12, 72, -18, 75, -18, 88),
+-	CABAC_ENTRY(441, -18, 73, -14, 68, -12, 71, -10, 73),
+-	CABAC_ENTRY(442, -4, 74, -3, 70, -11, 63, -9, 79),
+-	CABAC_ENTRY(443, -10, 83, -6, 76, -5, 70, -14, 86),
+-	CABAC_ENTRY(444, -9, 71, -5, 66, -17, 75, -10, 73),
+-	CABAC_ENTRY(445, -9, 67, -5, 62, -14, 72, -10, 70),
+-	CABAC_ENTRY(446, -1, 61, 0, 57, -16, 67, -10, 69),
+-	CABAC_ENTRY(447, -8, 66, -4, 61, -8, 53, -5, 66),
+-	CABAC_ENTRY(448, -14, 66, -9, 60, -14, 59, -9, 64),
+-	CABAC_ENTRY(449, 0, 59, 1, 54, -9, 52, -5, 58),
+-	CABAC_ENTRY(450, 2, 59, 2, 58, -11, 68, 2, 59),
+-	CABAC_ENTRY(451, 21, -13, 17, -10, 9, -2, 21, -10),
+-	CABAC_ENTRY(452, 33, -14, 32, -13, 30, -10, 24, -11),
+-	CABAC_ENTRY(453, 39, -7, 42, -9, 31, -4, 28, -8),
+-	CABAC_ENTRY(454, 46, -2, 49, -5, 33, -1, 28, -1),
+-	CABAC_ENTRY(455, 51, 2, 53, 0, 33, 7, 29, 3),
+-	CABAC_ENTRY(456, 60, 6, 64, 3, 31, 12, 29, 9),
+-	CABAC_ENTRY(457, 61, 17, 68, 10, 37, 23, 35, 20),
+-	CABAC_ENTRY(458, 55, 34, 66, 27, 31, 38, 29, 36),
+-	CABAC_ENTRY(459, 42, 62, 47, 57, 20, 64, 14, 67),
+-};
+-
+ static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
+ {
+ 	u8 bit = field.offset % 32, word = field.offset / 32;
+diff --git a/include/media/v4l2-cabac/rkvdec-cabac.h b/include/media/v4l2-cabac/rkvdec-cabac.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/include/media/v4l2-cabac/rkvdec-cabac.h
+@@ -0,0 +1,509 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++/*
++ * Define the H264 CABAC table common to rkvdec and rkvdec2 drivers.
++ */
++
++#ifndef RKVDEC_H264_CABAC_H_
++#define RKVDEC_H264_CABAC_H_
++
++#define CABAC_ENTRY(ctxidx, idc0_m, idc0_n, idc1_m, idc1_n,	\
++		    idc2_m, idc2_n, intra_m, intra_n)		\
++	[0][(ctxidx)] = {idc0_m, idc0_n},			\
++	[1][(ctxidx)] = {idc1_m, idc1_n},			\
++	[2][(ctxidx)] = {idc2_m, idc2_n},			\
++	[3][(ctxidx)] = {intra_m, intra_n}
++
++/*
++ * Constant CABAC table.
++ * Built from the tables described in section '9.3.1.1 Initialisation process
++ * for context variables' of the H264 spec.
++ */
++static const s8 rkvdec_h264_cabac_table[4][464][2] = {
++	/* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */
++	CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15),
++	CABAC_ENTRY(1, 2, 54, 2, 54, 2, 54, 2, 54),
++	CABAC_ENTRY(2, 3, 74, 3, 74, 3, 74, 3, 74),
++	CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15),
++	CABAC_ENTRY(4, 2, 54, 2, 54, 2, 54, 2, 54),
++	CABAC_ENTRY(5, 3, 74, 3, 74, 3, 74, 3, 74),
++	CABAC_ENTRY(6, -28, 127, -28, 127, -28, 127, -28, 127),
++	CABAC_ENTRY(7, -23, 104, -23, 104, -23, 104, -23, 104),
++	CABAC_ENTRY(8, -6, 53, -6, 53, -6, 53, -6, 53),
++	CABAC_ENTRY(9, -1, 54, -1, 54, -1, 54, -1, 54),
++	CABAC_ENTRY(10, 7, 51, 7, 51, 7, 51, 7, 51),
++
++	/* Table 9-13 – Values of variables m and n for ctxIdx from 11 to 23 */
++	CABAC_ENTRY(11, 23, 33, 22, 25, 29, 16, 0, 0),
++	CABAC_ENTRY(12, 23, 2, 34, 0, 25, 0, 0, 0),
++	CABAC_ENTRY(13, 21, 0, 16, 0, 14, 0, 0, 0),
++	CABAC_ENTRY(14, 1, 9, -2, 9, -10, 51, 0, 0),
++	CABAC_ENTRY(15, 0, 49, 4, 41, -3, 62, 0, 0),
++	CABAC_ENTRY(16, -37, 118, -29, 118, -27, 99, 0, 0),
++	CABAC_ENTRY(17, 5, 57, 2, 65, 26, 16, 0, 0),
++	CABAC_ENTRY(18, -13, 78, -6, 71, -4, 85, 0, 0),
++	CABAC_ENTRY(19, -11, 65, -13, 79, -24, 102, 0, 0),
++	CABAC_ENTRY(20, 1, 62, 5, 52, 5, 57, 0, 0),
++	CABAC_ENTRY(21, 12, 49, 9, 50, 6, 57, 0, 0),
++	CABAC_ENTRY(22, -4, 73, -3, 70, -17, 73, 0, 0),
++	CABAC_ENTRY(23, 17, 50, 10, 54, 14, 57, 0, 0),
++
++	/* Table 9-14 – Values of variables m and n for ctxIdx from 24 to 39 */
++	CABAC_ENTRY(24, 18, 64, 26, 34, 20, 40, 0, 0),
++	CABAC_ENTRY(25, 9, 43, 19, 22, 20, 10, 0, 0),
++	CABAC_ENTRY(26, 29, 0, 40, 0, 29, 0, 0, 0),
++	CABAC_ENTRY(27, 26, 67, 57, 2, 54, 0, 0, 0),
++	CABAC_ENTRY(28, 16, 90, 41, 36, 37, 42, 0, 0),
++	CABAC_ENTRY(29, 9, 104, 26, 69, 12, 97, 0, 0),
++	CABAC_ENTRY(30, -46, 127, -45, 127, -32, 127, 0, 0),
++	CABAC_ENTRY(31, -20, 104, -15, 101, -22, 117, 0, 0),
++	CABAC_ENTRY(32, 1, 67, -4, 76, -2, 74, 0, 0),
++	CABAC_ENTRY(33, -13, 78, -6, 71, -4, 85, 0, 0),
++	CABAC_ENTRY(34, -11, 65, -13, 79, -24, 102, 0, 0),
++	CABAC_ENTRY(35, 1, 62, 5, 52, 5, 57, 0, 0),
++	CABAC_ENTRY(36, -6, 86, 6, 69, -6, 93, 0, 0),
++	CABAC_ENTRY(37, -17, 95, -13, 90, -14, 88, 0, 0),
++	CABAC_ENTRY(38, -6, 61, 0, 52, -6, 44, 0, 0),
++	CABAC_ENTRY(39, 9, 45, 8, 43, 4, 55, 0, 0),
++
++	/* Table 9-15 – Values of variables m and n for ctxIdx from 40 to 53 */
++	CABAC_ENTRY(40, -3, 69, -2, 69, -11, 89, 0, 0),
++	CABAC_ENTRY(41, -6, 81, -5, 82, -15, 103, 0, 0),
++	CABAC_ENTRY(42, -11, 96, -10, 96, -21, 116, 0, 0),
++	CABAC_ENTRY(43, 6, 55, 2, 59, 19, 57, 0, 0),
++	CABAC_ENTRY(44, 7, 67, 2, 75, 20, 58, 0, 0),
++	CABAC_ENTRY(45, -5, 86, -3, 87, 4, 84, 0, 0),
++	CABAC_ENTRY(46, 2, 88, -3, 100, 6, 96, 0, 0),
++	CABAC_ENTRY(47, 0, 58, 1, 56, 1, 63, 0, 0),
++	CABAC_ENTRY(48, -3, 76, -3, 74, -5, 85, 0, 0),
++	CABAC_ENTRY(49, -10, 94, -6, 85, -13, 106, 0, 0),
++	CABAC_ENTRY(50, 5, 54, 0, 59, 5, 63, 0, 0),
++	CABAC_ENTRY(51, 4, 69, -3, 81, 6, 75, 0, 0),
++	CABAC_ENTRY(52, -3, 81, -7, 86, -3, 90, 0, 0),
++	CABAC_ENTRY(53, 0, 88, -5, 95, -1, 101, 0, 0),
++
++	/* Table 9-16 – Values of variables m and n for ctxIdx from 54 to 59 */
++	CABAC_ENTRY(54, -7, 67, -1, 66, 3, 55, 0, 0),
++	CABAC_ENTRY(55, -5, 74, -1, 77, -4, 79, 0, 0),
++	CABAC_ENTRY(56, -4, 74, 1, 70, -2, 75, 0, 0),
++	CABAC_ENTRY(57, -5, 80, -2, 86, -12, 97, 0, 0),
++	CABAC_ENTRY(58, -7, 72, -5, 72, -7, 50, 0, 0),
++	CABAC_ENTRY(59, 1, 58, 0, 61, 1, 60, 0, 0),
++
++	/* Table 9-17 – Values of variables m and n for ctxIdx from 60 to 69 */
++	CABAC_ENTRY(60, 0, 41, 0, 41, 0, 41, 0, 41),
++	CABAC_ENTRY(61, 0, 63, 0, 63, 0, 63, 0, 63),
++	CABAC_ENTRY(62, 0, 63, 0, 63, 0, 63, 0, 63),
++	CABAC_ENTRY(63, 0, 63, 0, 63, 0, 63, 0, 63),
++	CABAC_ENTRY(64, -9, 83, -9, 83, -9, 83, -9, 83),
++	CABAC_ENTRY(65, 4, 86, 4, 86, 4, 86, 4, 86),
++	CABAC_ENTRY(66, 0, 97, 0, 97, 0, 97, 0, 97),
++	CABAC_ENTRY(67, -7, 72, -7, 72, -7, 72, -7, 72),
++	CABAC_ENTRY(68, 13, 41, 13, 41, 13, 41, 13, 41),
++	CABAC_ENTRY(69, 3, 62, 3, 62, 3, 62, 3, 62),
++
++	/* Table 9-18 – Values of variables m and n for ctxIdx from 70 to 104 */
++	CABAC_ENTRY(70, 0, 45, 13, 15, 7, 34, 0, 11),
++	CABAC_ENTRY(71, -4, 78, 7, 51, -9, 88, 1, 55),
++	CABAC_ENTRY(72, -3, 96, 2, 80, -20, 127, 0, 69),
++	CABAC_ENTRY(73, -27, 126, -39, 127, -36, 127, -17, 127),
++	CABAC_ENTRY(74, -28, 98, -18, 91, -17, 91, -13, 102),
++	CABAC_ENTRY(75, -25, 101, -17, 96, -14, 95, 0, 82),
++	CABAC_ENTRY(76, -23, 67, -26, 81, -25, 84, -7, 74),
++	CABAC_ENTRY(77, -28, 82, -35, 98, -25, 86, -21, 107),
++	CABAC_ENTRY(78, -20, 94, -24, 102, -12, 89, -27, 127),
++	CABAC_ENTRY(79, -16, 83, -23, 97, -17, 91, -31, 127),
++	CABAC_ENTRY(80, -22, 110, -27, 119, -31, 127, -24, 127),
++	CABAC_ENTRY(81, -21, 91, -24, 99, -14, 76, -18, 95),
++	CABAC_ENTRY(82, -18, 102, -21, 110, -18, 103, -27, 127),
++	CABAC_ENTRY(83, -13, 93, -18, 102, -13, 90, -21, 114),
++	CABAC_ENTRY(84, -29, 127, -36, 127, -37, 127, -30, 127),
++	CABAC_ENTRY(85, -7, 92, 0, 80, 11, 80, -17, 123),
++	CABAC_ENTRY(86, -5, 89, -5, 89, 5, 76, -12, 115),
++	CABAC_ENTRY(87, -7, 96, -7, 94, 2, 84, -16, 122),
++	CABAC_ENTRY(88, -13, 108, -4, 92, 5, 78, -11, 115),
++	CABAC_ENTRY(89, -3, 46, 0, 39, -6, 55, -12, 63),
++	CABAC_ENTRY(90, -1, 65, 0, 65, 4, 61, -2, 68),
++	CABAC_ENTRY(91, -1, 57, -15, 84, -14, 83, -15, 84),
++	CABAC_ENTRY(92, -9, 93, -35, 127, -37, 127, -13, 104),
++	CABAC_ENTRY(93, -3, 74, -2, 73, -5, 79, -3, 70),
++	CABAC_ENTRY(94, -9, 92, -12, 104, -11, 104, -8, 93),
++	CABAC_ENTRY(95, -8, 87, -9, 91, -11, 91, -10, 90),
++	CABAC_ENTRY(96, -23, 126, -31, 127, -30, 127, -30, 127),
++	CABAC_ENTRY(97, 5, 54, 3, 55, 0, 65, -1, 74),
++	CABAC_ENTRY(98, 6, 60, 7, 56, -2, 79, -6, 97),
++	CABAC_ENTRY(99, 6, 59, 7, 55, 0, 72, -7, 91),
++	CABAC_ENTRY(100, 6, 69, 8, 61, -4, 92, -20, 127),
++	CABAC_ENTRY(101, -1, 48, -3, 53, -6, 56, -4, 56),
++	CABAC_ENTRY(102, 0, 68, 0, 68, 3, 68, -5, 82),
++	CABAC_ENTRY(103, -4, 69, -7, 74, -8, 71, -7, 76),
++	CABAC_ENTRY(104, -8, 88, -9, 88, -13, 98, -22, 125),
++
++	/* Table 9-19 – Values of variables m and n for ctxIdx from 105 to 165 */
++	CABAC_ENTRY(105, -2, 85, -13, 103, -4, 86, -7, 93),
++	CABAC_ENTRY(106, -6, 78, -13, 91, -12, 88, -11, 87),
++	CABAC_ENTRY(107, -1, 75, -9, 89, -5, 82, -3, 77),
++	CABAC_ENTRY(108, -7, 77, -14, 92, -3, 72, -5, 71),
++	CABAC_ENTRY(109, 2, 54, -8, 76, -4, 67, -4, 63),
++	CABAC_ENTRY(110, 5, 50, -12, 87, -8, 72, -4, 68),
++	CABAC_ENTRY(111, -3, 68, -23, 110, -16, 89, -12, 84),
++	CABAC_ENTRY(112, 1, 50, -24, 105, -9, 69, -7, 62),
++	CABAC_ENTRY(113, 6, 42, -10, 78, -1, 59, -7, 65),
++	CABAC_ENTRY(114, -4, 81, -20, 112, 5, 66, 8, 61),
++	CABAC_ENTRY(115, 1, 63, -17, 99, 4, 57, 5, 56),
++	CABAC_ENTRY(116, -4, 70, -78, 127, -4, 71, -2, 66),
++	CABAC_ENTRY(117, 0, 67, -70, 127, -2, 71, 1, 64),
++	CABAC_ENTRY(118, 2, 57, -50, 127, 2, 58, 0, 61),
++	CABAC_ENTRY(119, -2, 76, -46, 127, -1, 74, -2, 78),
++	CABAC_ENTRY(120, 11, 35, -4, 66, -4, 44, 1, 50),
++	CABAC_ENTRY(121, 4, 64, -5, 78, -1, 69, 7, 52),
++	CABAC_ENTRY(122, 1, 61, -4, 71, 0, 62, 10, 35),
++	CABAC_ENTRY(123, 11, 35, -8, 72, -7, 51, 0, 44),
++	CABAC_ENTRY(124, 18, 25, 2, 59, -4, 47, 11, 38),
++	CABAC_ENTRY(125, 12, 24, -1, 55, -6, 42, 1, 45),
++	CABAC_ENTRY(126, 13, 29, -7, 70, -3, 41, 0, 46),
++	CABAC_ENTRY(127, 13, 36, -6, 75, -6, 53, 5, 44),
++	CABAC_ENTRY(128, -10, 93, -8, 89, 8, 76, 31, 17),
++	CABAC_ENTRY(129, -7, 73, -34, 119, -9, 78, 1, 51),
++	CABAC_ENTRY(130, -2, 73, -3, 75, -11, 83, 7, 50),
++	CABAC_ENTRY(131, 13, 46, 32, 20, 9, 52, 28, 19),
++	CABAC_ENTRY(132, 9, 49, 30, 22, 0, 67, 16, 33),
++	CABAC_ENTRY(133, -7, 100, -44, 127, -5, 90, 14, 62),
++	CABAC_ENTRY(134, 9, 53, 0, 54, 1, 67, -13, 108),
++	CABAC_ENTRY(135, 2, 53, -5, 61, -15, 72, -15, 100),
++	CABAC_ENTRY(136, 5, 53, 0, 58, -5, 75, -13, 101),
++	CABAC_ENTRY(137, -2, 61, -1, 60, -8, 80, -13, 91),
++	CABAC_ENTRY(138, 0, 56, -3, 61, -21, 83, -12, 94),
++	CABAC_ENTRY(139, 0, 56, -8, 67, -21, 64, -10, 88),
++	CABAC_ENTRY(140, -13, 63, -25, 84, -13, 31, -16, 84),
++	CABAC_ENTRY(141, -5, 60, -14, 74, -25, 64, -10, 86),
++	CABAC_ENTRY(142, -1, 62, -5, 65, -29, 94, -7, 83),
++	CABAC_ENTRY(143, 4, 57, 5, 52, 9, 75, -13, 87),
++	CABAC_ENTRY(144, -6, 69, 2, 57, 17, 63, -19, 94),
++	CABAC_ENTRY(145, 4, 57, 0, 61, -8, 74, 1, 70),
++	CABAC_ENTRY(146, 14, 39, -9, 69, -5, 35, 0, 72),
++	CABAC_ENTRY(147, 4, 51, -11, 70, -2, 27, -5, 74),
++	CABAC_ENTRY(148, 13, 68, 18, 55, 13, 91, 18, 59),
++	CABAC_ENTRY(149, 3, 64, -4, 71, 3, 65, -8, 102),
++	CABAC_ENTRY(150, 1, 61, 0, 58, -7, 69, -15, 100),
++	CABAC_ENTRY(151, 9, 63, 7, 61, 8, 77, 0, 95),
++	CABAC_ENTRY(152, 7, 50, 9, 41, -10, 66, -4, 75),
++	CABAC_ENTRY(153, 16, 39, 18, 25, 3, 62, 2, 72),
++	CABAC_ENTRY(154, 5, 44, 9, 32, -3, 68, -11, 75),
++	CABAC_ENTRY(155, 4, 52, 5, 43, -20, 81, -3, 71),
++	CABAC_ENTRY(156, 11, 48, 9, 47, 0, 30, 15, 46),
++	CABAC_ENTRY(157, -5, 60, 0, 44, 1, 7, -13, 69),
++	CABAC_ENTRY(158, -1, 59, 0, 51, -3, 23, 0, 62),
++	CABAC_ENTRY(159, 0, 59, 2, 46, -21, 74, 0, 65),
++	CABAC_ENTRY(160, 22, 33, 19, 38, 16, 66, 21, 37),
++	CABAC_ENTRY(161, 5, 44, -4, 66, -23, 124, -15, 72),
++	CABAC_ENTRY(162, 14, 43, 15, 38, 17, 37, 9, 57),
++	CABAC_ENTRY(163, -1, 78, 12, 42, 44, -18, 16, 54),
++	CABAC_ENTRY(164, 0, 60, 9, 34, 50, -34, 0, 62),
++	CABAC_ENTRY(165, 9, 69, 0, 89, -22, 127, 12, 72),
++
++	/* Table 9-20 – Values of variables m and n for ctxIdx from 166 to 226 */
++	CABAC_ENTRY(166, 11, 28, 4, 45, 4, 39, 24, 0),
++	CABAC_ENTRY(167, 2, 40, 10, 28, 0, 42, 15, 9),
++	CABAC_ENTRY(168, 3, 44, 10, 31, 7, 34, 8, 25),
++	CABAC_ENTRY(169, 0, 49, 33, -11, 11, 29, 13, 18),
++	CABAC_ENTRY(170, 0, 46, 52, -43, 8, 31, 15, 9),
++	CABAC_ENTRY(171, 2, 44, 18, 15, 6, 37, 13, 19),
++	CABAC_ENTRY(172, 2, 51, 28, 0, 7, 42, 10, 37),
++	CABAC_ENTRY(173, 0, 47, 35, -22, 3, 40, 12, 18),
++	CABAC_ENTRY(174, 4, 39, 38, -25, 8, 33, 6, 29),
++	CABAC_ENTRY(175, 2, 62, 34, 0, 13, 43, 20, 33),
++	CABAC_ENTRY(176, 6, 46, 39, -18, 13, 36, 15, 30),
++	CABAC_ENTRY(177, 0, 54, 32, -12, 4, 47, 4, 45),
++	CABAC_ENTRY(178, 3, 54, 102, -94, 3, 55, 1, 58),
++	CABAC_ENTRY(179, 2, 58, 0, 0, 2, 58, 0, 62),
++	CABAC_ENTRY(180, 4, 63, 56, -15, 6, 60, 7, 61),
++	CABAC_ENTRY(181, 6, 51, 33, -4, 8, 44, 12, 38),
++	CABAC_ENTRY(182, 6, 57, 29, 10, 11, 44, 11, 45),
++	CABAC_ENTRY(183, 7, 53, 37, -5, 14, 42, 15, 39),
++	CABAC_ENTRY(184, 6, 52, 51, -29, 7, 48, 11, 42),
++	CABAC_ENTRY(185, 6, 55, 39, -9, 4, 56, 13, 44),
++	CABAC_ENTRY(186, 11, 45, 52, -34, 4, 52, 16, 45),
++	CABAC_ENTRY(187, 14, 36, 69, -58, 13, 37, 12, 41),
++	CABAC_ENTRY(188, 8, 53, 67, -63, 9, 49, 10, 49),
++	CABAC_ENTRY(189, -1, 82, 44, -5, 19, 58, 30, 34),
++	CABAC_ENTRY(190, 7, 55, 32, 7, 10, 48, 18, 42),
++	CABAC_ENTRY(191, -3, 78, 55, -29, 12, 45, 10, 55),
++	CABAC_ENTRY(192, 15, 46, 32, 1, 0, 69, 17, 51),
++	CABAC_ENTRY(193, 22, 31, 0, 0, 20, 33, 17, 46),
++	CABAC_ENTRY(194, -1, 84, 27, 36, 8, 63, 0, 89),
++	CABAC_ENTRY(195, 25, 7, 33, -25, 35, -18, 26, -19),
++	CABAC_ENTRY(196, 30, -7, 34, -30, 33, -25, 22, -17),
++	CABAC_ENTRY(197, 28, 3, 36, -28, 28, -3, 26, -17),
++	CABAC_ENTRY(198, 28, 4, 38, -28, 24, 10, 30, -25),
++	CABAC_ENTRY(199, 32, 0, 38, -27, 27, 0, 28, -20),
++	CABAC_ENTRY(200, 34, -1, 34, -18, 34, -14, 33, -23),
++	CABAC_ENTRY(201, 30, 6, 35, -16, 52, -44, 37, -27),
++	CABAC_ENTRY(202, 30, 6, 34, -14, 39, -24, 33, -23),
++	CABAC_ENTRY(203, 32, 9, 32, -8, 19, 17, 40, -28),
++	CABAC_ENTRY(204, 31, 19, 37, -6, 31, 25, 38, -17),
++	CABAC_ENTRY(205, 26, 27, 35, 0, 36, 29, 33, -11),
++	CABAC_ENTRY(206, 26, 30, 30, 10, 24, 33, 40, -15),
++	CABAC_ENTRY(207, 37, 20, 28, 18, 34, 15, 41, -6),
++	CABAC_ENTRY(208, 28, 34, 26, 25, 30, 20, 38, 1),
++	CABAC_ENTRY(209, 17, 70, 29, 41, 22, 73, 41, 17),
++	CABAC_ENTRY(210, 1, 67, 0, 75, 20, 34, 30, -6),
++	CABAC_ENTRY(211, 5, 59, 2, 72, 19, 31, 27, 3),
++	CABAC_ENTRY(212, 9, 67, 8, 77, 27, 44, 26, 22),
++	CABAC_ENTRY(213, 16, 30, 14, 35, 19, 16, 37, -16),
++	CABAC_ENTRY(214, 18, 32, 18, 31, 15, 36, 35, -4),
++	CABAC_ENTRY(215, 18, 35, 17, 35, 15, 36, 38, -8),
++	CABAC_ENTRY(216, 22, 29, 21, 30, 21, 28, 38, -3),
++	CABAC_ENTRY(217, 24, 31, 17, 45, 25, 21, 37, 3),
++	CABAC_ENTRY(218, 23, 38, 20, 42, 30, 20, 38, 5),
++	CABAC_ENTRY(219, 18, 43, 18, 45, 31, 12, 42, 0),
++	CABAC_ENTRY(220, 20, 41, 27, 26, 27, 16, 35, 16),
++	CABAC_ENTRY(221, 11, 63, 16, 54, 24, 42, 39, 22),
++	CABAC_ENTRY(222, 9, 59, 7, 66, 0, 93, 14, 48),
++	CABAC_ENTRY(223, 9, 64, 16, 56, 14, 56, 27, 37),
++	CABAC_ENTRY(224, -1, 94, 11, 73, 15, 57, 21, 60),
++	CABAC_ENTRY(225, -2, 89, 10, 67, 26, 38, 12, 68),
++	CABAC_ENTRY(226, -9, 108, -10, 116, -24, 127, 2, 97),
++
++	/* Table 9-21 – Values of variables m and n for ctxIdx from 227 to 275 */
++	CABAC_ENTRY(227, -6, 76, -23, 112, -24, 115, -3, 71),
++	CABAC_ENTRY(228, -2, 44, -15, 71, -22, 82, -6, 42),
++	CABAC_ENTRY(229, 0, 45, -7, 61, -9, 62, -5, 50),
++	CABAC_ENTRY(230, 0, 52, 0, 53, 0, 53, -3, 54),
++	CABAC_ENTRY(231, -3, 64, -5, 66, 0, 59, -2, 62),
++	CABAC_ENTRY(232, -2, 59, -11, 77, -14, 85, 0, 58),
++	CABAC_ENTRY(233, -4, 70, -9, 80, -13, 89, 1, 63),
++	CABAC_ENTRY(234, -4, 75, -9, 84, -13, 94, -2, 72),
++	CABAC_ENTRY(235, -8, 82, -10, 87, -11, 92, -1, 74),
++	CABAC_ENTRY(236, -17, 102, -34, 127, -29, 127, -9, 91),
++	CABAC_ENTRY(237, -9, 77, -21, 101, -21, 100, -5, 67),
++	CABAC_ENTRY(238, 3, 24, -3, 39, -14, 57, -5, 27),
++	CABAC_ENTRY(239, 0, 42, -5, 53, -12, 67, -3, 39),
++	CABAC_ENTRY(240, 0, 48, -7, 61, -11, 71, -2, 44),
++	CABAC_ENTRY(241, 0, 55, -11, 75, -10, 77, 0, 46),
++	CABAC_ENTRY(242, -6, 59, -15, 77, -21, 85, -16, 64),
++	CABAC_ENTRY(243, -7, 71, -17, 91, -16, 88, -8, 68),
++	CABAC_ENTRY(244, -12, 83, -25, 107, -23, 104, -10, 78),
++	CABAC_ENTRY(245, -11, 87, -25, 111, -15, 98, -6, 77),
++	CABAC_ENTRY(246, -30, 119, -28, 122, -37, 127, -10, 86),
++	CABAC_ENTRY(247, 1, 58, -11, 76, -10, 82, -12, 92),
++	CABAC_ENTRY(248, -3, 29, -10, 44, -8, 48, -15, 55),
++	CABAC_ENTRY(249, -1, 36, -10, 52, -8, 61, -10, 60),
++	CABAC_ENTRY(250, 1, 38, -10, 57, -8, 66, -6, 62),
++	CABAC_ENTRY(251, 2, 43, -9, 58, -7, 70, -4, 65),
++	CABAC_ENTRY(252, -6, 55, -16, 72, -14, 75, -12, 73),
++	CABAC_ENTRY(253, 0, 58, -7, 69, -10, 79, -8, 76),
++	CABAC_ENTRY(254, 0, 64, -4, 69, -9, 83, -7, 80),
++	CABAC_ENTRY(255, -3, 74, -5, 74, -12, 92, -9, 88),
++	CABAC_ENTRY(256, -10, 90, -9, 86, -18, 108, -17, 110),
++	CABAC_ENTRY(257, 0, 70, 2, 66, -4, 79, -11, 97),
++	CABAC_ENTRY(258, -4, 29, -9, 34, -22, 69, -20, 84),
++	CABAC_ENTRY(259, 5, 31, 1, 32, -16, 75, -11, 79),
++	CABAC_ENTRY(260, 7, 42, 11, 31, -2, 58, -6, 73),
++	CABAC_ENTRY(261, 1, 59, 5, 52, 1, 58, -4, 74),
++	CABAC_ENTRY(262, -2, 58, -2, 55, -13, 78, -13, 86),
++	CABAC_ENTRY(263, -3, 72, -2, 67, -9, 83, -13, 96),
++	CABAC_ENTRY(264, -3, 81, 0, 73, -4, 81, -11, 97),
++	CABAC_ENTRY(265, -11, 97, -8, 89, -13, 99, -19, 117),
++	CABAC_ENTRY(266, 0, 58, 3, 52, -13, 81, -8, 78),
++	CABAC_ENTRY(267, 8, 5, 7, 4, -6, 38, -5, 33),
++	CABAC_ENTRY(268, 10, 14, 10, 8, -13, 62, -4, 48),
++	CABAC_ENTRY(269, 14, 18, 17, 8, -6, 58, -2, 53),
++	CABAC_ENTRY(270, 13, 27, 16, 19, -2, 59, -3, 62),
++	CABAC_ENTRY(271, 2, 40, 3, 37, -16, 73, -13, 71),
++	CABAC_ENTRY(272, 0, 58, -1, 61, -10, 76, -10, 79),
++	CABAC_ENTRY(273, -3, 70, -5, 73, -13, 86, -12, 86),
++	CABAC_ENTRY(274, -6, 79, -1, 70, -9, 83, -13, 90),
++	CABAC_ENTRY(275, -8, 85, -4, 78, -10, 87, -14, 97),
++
++	/* Table 9-22 – Values of variables m and n for ctxIdx from 277 to 337 */
++	CABAC_ENTRY(277, -13, 106, -21, 126, -22, 127, -6, 93),
++	CABAC_ENTRY(278, -16, 106, -23, 124, -25, 127, -6, 84),
++	CABAC_ENTRY(279, -10, 87, -20, 110, -25, 120, -8, 79),
++	CABAC_ENTRY(280, -21, 114, -26, 126, -27, 127, 0, 66),
++	CABAC_ENTRY(281, -18, 110, -25, 124, -19, 114, -1, 71),
++	CABAC_ENTRY(282, -14, 98, -17, 105, -23, 117, 0, 62),
++	CABAC_ENTRY(283, -22, 110, -27, 121, -25, 118, -2, 60),
++	CABAC_ENTRY(284, -21, 106, -27, 117, -26, 117, -2, 59),
++	CABAC_ENTRY(285, -18, 103, -17, 102, -24, 113, -5, 75),
++	CABAC_ENTRY(286, -21, 107, -26, 117, -28, 118, -3, 62),
++	CABAC_ENTRY(287, -23, 108, -27, 116, -31, 120, -4, 58),
++	CABAC_ENTRY(288, -26, 112, -33, 122, -37, 124, -9, 66),
++	CABAC_ENTRY(289, -10, 96, -10, 95, -10, 94, -1, 79),
++	CABAC_ENTRY(290, -12, 95, -14, 100, -15, 102, 0, 71),
++	CABAC_ENTRY(291, -5, 91, -8, 95, -10, 99, 3, 68),
++	CABAC_ENTRY(292, -9, 93, -17, 111, -13, 106, 10, 44),
++	CABAC_ENTRY(293, -22, 94, -28, 114, -50, 127, -7, 62),
++	CABAC_ENTRY(294, -5, 86, -6, 89, -5, 92, 15, 36),
++	CABAC_ENTRY(295, 9, 67, -2, 80, 17, 57, 14, 40),
++	CABAC_ENTRY(296, -4, 80, -4, 82, -5, 86, 16, 27),
++	CABAC_ENTRY(297, -10, 85, -9, 85, -13, 94, 12, 29),
++	CABAC_ENTRY(298, -1, 70, -8, 81, -12, 91, 1, 44),
++	CABAC_ENTRY(299, 7, 60, -1, 72, -2, 77, 20, 36),
++	CABAC_ENTRY(300, 9, 58, 5, 64, 0, 71, 18, 32),
++	CABAC_ENTRY(301, 5, 61, 1, 67, -1, 73, 5, 42),
++	CABAC_ENTRY(302, 12, 50, 9, 56, 4, 64, 1, 48),
++	CABAC_ENTRY(303, 15, 50, 0, 69, -7, 81, 10, 62),
++	CABAC_ENTRY(304, 18, 49, 1, 69, 5, 64, 17, 46),
++	CABAC_ENTRY(305, 17, 54, 7, 69, 15, 57, 9, 64),
++	CABAC_ENTRY(306, 10, 41, -7, 69, 1, 67, -12, 104),
++	CABAC_ENTRY(307, 7, 46, -6, 67, 0, 68, -11, 97),
++	CABAC_ENTRY(308, -1, 51, -16, 77, -10, 67, -16, 96),
++	CABAC_ENTRY(309, 7, 49, -2, 64, 1, 68, -7, 88),
++	CABAC_ENTRY(310, 8, 52, 2, 61, 0, 77, -8, 85),
++	CABAC_ENTRY(311, 9, 41, -6, 67, 2, 64, -7, 85),
++	CABAC_ENTRY(312, 6, 47, -3, 64, 0, 68, -9, 85),
++	CABAC_ENTRY(313, 2, 55, 2, 57, -5, 78, -13, 88),
++	CABAC_ENTRY(314, 13, 41, -3, 65, 7, 55, 4, 66),
++	CABAC_ENTRY(315, 10, 44, -3, 66, 5, 59, -3, 77),
++	CABAC_ENTRY(316, 6, 50, 0, 62, 2, 65, -3, 76),
++	CABAC_ENTRY(317, 5, 53, 9, 51, 14, 54, -6, 76),
++	CABAC_ENTRY(318, 13, 49, -1, 66, 15, 44, 10, 58),
++	CABAC_ENTRY(319, 4, 63, -2, 71, 5, 60, -1, 76),
++	CABAC_ENTRY(320, 6, 64, -2, 75, 2, 70, -1, 83),
++	CABAC_ENTRY(321, -2, 69, -1, 70, -2, 76, -7, 99),
++	CABAC_ENTRY(322, -2, 59, -9, 72, -18, 86, -14, 95),
++	CABAC_ENTRY(323, 6, 70, 14, 60, 12, 70, 2, 95),
++	CABAC_ENTRY(324, 10, 44, 16, 37, 5, 64, 0, 76),
++	CABAC_ENTRY(325, 9, 31, 0, 47, -12, 70, -5, 74),
++	CABAC_ENTRY(326, 12, 43, 18, 35, 11, 55, 0, 70),
++	CABAC_ENTRY(327, 3, 53, 11, 37, 5, 56, -11, 75),
++	CABAC_ENTRY(328, 14, 34, 12, 41, 0, 69, 1, 68),
++	CABAC_ENTRY(329, 10, 38, 10, 41, 2, 65, 0, 65),
++	CABAC_ENTRY(330, -3, 52, 2, 48, -6, 74, -14, 73),
++	CABAC_ENTRY(331, 13, 40, 12, 41, 5, 54, 3, 62),
++	CABAC_ENTRY(332, 17, 32, 13, 41, 7, 54, 4, 62),
++	CABAC_ENTRY(333, 7, 44, 0, 59, -6, 76, -1, 68),
++	CABAC_ENTRY(334, 7, 38, 3, 50, -11, 82, -13, 75),
++	CABAC_ENTRY(335, 13, 50, 19, 40, -2, 77, 11, 55),
++	CABAC_ENTRY(336, 10, 57, 3, 66, -2, 77, 5, 64),
++	CABAC_ENTRY(337, 26, 43, 18, 50, 25, 42, 12, 70),
++
++	/* Table 9-23 – Values of variables m and n for ctxIdx from 338 to 398 */
++	CABAC_ENTRY(338, 14, 11, 19, -6, 17, -13, 15, 6),
++	CABAC_ENTRY(339, 11, 14, 18, -6, 16, -9, 6, 19),
++	CABAC_ENTRY(340, 9, 11, 14, 0, 17, -12, 7, 16),
++	CABAC_ENTRY(341, 18, 11, 26, -12, 27, -21, 12, 14),
++	CABAC_ENTRY(342, 21, 9, 31, -16, 37, -30, 18, 13),
++	CABAC_ENTRY(343, 23, -2, 33, -25, 41, -40, 13, 11),
++	CABAC_ENTRY(344, 32, -15, 33, -22, 42, -41, 13, 15),
++	CABAC_ENTRY(345, 32, -15, 37, -28, 48, -47, 15, 16),
++	CABAC_ENTRY(346, 34, -21, 39, -30, 39, -32, 12, 23),
++	CABAC_ENTRY(347, 39, -23, 42, -30, 46, -40, 13, 23),
++	CABAC_ENTRY(348, 42, -33, 47, -42, 52, -51, 15, 20),
++	CABAC_ENTRY(349, 41, -31, 45, -36, 46, -41, 14, 26),
++	CABAC_ENTRY(350, 46, -28, 49, -34, 52, -39, 14, 44),
++	CABAC_ENTRY(351, 38, -12, 41, -17, 43, -19, 17, 40),
++	CABAC_ENTRY(352, 21, 29, 32, 9, 32, 11, 17, 47),
++	CABAC_ENTRY(353, 45, -24, 69, -71, 61, -55, 24, 17),
++	CABAC_ENTRY(354, 53, -45, 63, -63, 56, -46, 21, 21),
++	CABAC_ENTRY(355, 48, -26, 66, -64, 62, -50, 25, 22),
++	CABAC_ENTRY(356, 65, -43, 77, -74, 81, -67, 31, 27),
++	CABAC_ENTRY(357, 43, -19, 54, -39, 45, -20, 22, 29),
++	CABAC_ENTRY(358, 39, -10, 52, -35, 35, -2, 19, 35),
++	CABAC_ENTRY(359, 30, 9, 41, -10, 28, 15, 14, 50),
++	CABAC_ENTRY(360, 18, 26, 36, 0, 34, 1, 10, 57),
++	CABAC_ENTRY(361, 20, 27, 40, -1, 39, 1, 7, 63),
++	CABAC_ENTRY(362, 0, 57, 30, 14, 30, 17, -2, 77),
++	CABAC_ENTRY(363, -14, 82, 28, 26, 20, 38, -4, 82),
++	CABAC_ENTRY(364, -5, 75, 23, 37, 18, 45, -3, 94),
++	CABAC_ENTRY(365, -19, 97, 12, 55, 15, 54, 9, 69),
++	CABAC_ENTRY(366, -35, 125, 11, 65, 0, 79, -12, 109),
++	CABAC_ENTRY(367, 27, 0, 37, -33, 36, -16, 36, -35),
++	CABAC_ENTRY(368, 28, 0, 39, -36, 37, -14, 36, -34),
++	CABAC_ENTRY(369, 31, -4, 40, -37, 37, -17, 32, -26),
++	CABAC_ENTRY(370, 27, 6, 38, -30, 32, 1, 37, -30),
++	CABAC_ENTRY(371, 34, 8, 46, -33, 34, 15, 44, -32),
++	CABAC_ENTRY(372, 30, 10, 42, -30, 29, 15, 34, -18),
++	CABAC_ENTRY(373, 24, 22, 40, -24, 24, 25, 34, -15),
++	CABAC_ENTRY(374, 33, 19, 49, -29, 34, 22, 40, -15),
++	CABAC_ENTRY(375, 22, 32, 38, -12, 31, 16, 33, -7),
++	CABAC_ENTRY(376, 26, 31, 40, -10, 35, 18, 35, -5),
++	CABAC_ENTRY(377, 21, 41, 38, -3, 31, 28, 33, 0),
++	CABAC_ENTRY(378, 26, 44, 46, -5, 33, 41, 38, 2),
++	CABAC_ENTRY(379, 23, 47, 31, 20, 36, 28, 33, 13),
++	CABAC_ENTRY(380, 16, 65, 29, 30, 27, 47, 23, 35),
++	CABAC_ENTRY(381, 14, 71, 25, 44, 21, 62, 13, 58),
++	CABAC_ENTRY(382, 8, 60, 12, 48, 18, 31, 29, -3),
++	CABAC_ENTRY(383, 6, 63, 11, 49, 19, 26, 26, 0),
++	CABAC_ENTRY(384, 17, 65, 26, 45, 36, 24, 22, 30),
++	CABAC_ENTRY(385, 21, 24, 22, 22, 24, 23, 31, -7),
++	CABAC_ENTRY(386, 23, 20, 23, 22, 27, 16, 35, -15),
++	CABAC_ENTRY(387, 26, 23, 27, 21, 24, 30, 34, -3),
++	CABAC_ENTRY(388, 27, 32, 33, 20, 31, 29, 34, 3),
++	CABAC_ENTRY(389, 28, 23, 26, 28, 22, 41, 36, -1),
++	CABAC_ENTRY(390, 28, 24, 30, 24, 22, 42, 34, 5),
++	CABAC_ENTRY(391, 23, 40, 27, 34, 16, 60, 32, 11),
++	CABAC_ENTRY(392, 24, 32, 18, 42, 15, 52, 35, 5),
++	CABAC_ENTRY(393, 28, 29, 25, 39, 14, 60, 34, 12),
++	CABAC_ENTRY(394, 23, 42, 18, 50, 3, 78, 39, 11),
++	CABAC_ENTRY(395, 19, 57, 12, 70, -16, 123, 30, 29),
++	CABAC_ENTRY(396, 22, 53, 21, 54, 21, 53, 34, 26),
++	CABAC_ENTRY(397, 22, 61, 14, 71, 22, 56, 29, 39),
++	CABAC_ENTRY(398, 11, 86, 11, 83, 25, 61, 19, 66),
++
++	/* Values of variables m and n for ctxIdx from 399 to 463 (not documented) */
++	CABAC_ENTRY(399, 12, 40, 25, 32, 21, 33, 31, 21),
++	CABAC_ENTRY(400, 11, 51, 21, 49, 19, 50, 31, 31),
++	CABAC_ENTRY(401, 14, 59, 21, 54, 17, 61, 25, 50),
++	CABAC_ENTRY(402, -4, 79, -5, 85, -3, 78, -17, 120),
++	CABAC_ENTRY(403, -7, 71, -6, 81, -8, 74, -20, 112),
++	CABAC_ENTRY(404, -5, 69, -10, 77, -9, 72, -18, 114),
++	CABAC_ENTRY(405, -9, 70, -7, 81, -10, 72, -11, 85),
++	CABAC_ENTRY(406, -8, 66, -17, 80, -18, 75, -15, 92),
++	CABAC_ENTRY(407, -10, 68, -18, 73, -12, 71, -14, 89),
++	CABAC_ENTRY(408, -19, 73, -4, 74, -11, 63, -26, 71),
++	CABAC_ENTRY(409, -12, 69, -10, 83, -5, 70, -15, 81),
++	CABAC_ENTRY(410, -16, 70, -9, 71, -17, 75, -14, 80),
++	CABAC_ENTRY(411, -15, 67, -9, 67, -14, 72, 0, 68),
++	CABAC_ENTRY(412, -20, 62, -1, 61, -16, 67, -14, 70),
++	CABAC_ENTRY(413, -19, 70, -8, 66, -8, 53, -24, 56),
++	CABAC_ENTRY(414, -16, 66, -14, 66, -14, 59, -23, 68),
++	CABAC_ENTRY(415, -22, 65, 0, 59, -9, 52, -24, 50),
++	CABAC_ENTRY(416, -20, 63, 2, 59, -11, 68, -11, 74),
++	CABAC_ENTRY(417, 9, -2, 17, -10, 9, -2, 23, -13),
++	CABAC_ENTRY(418, 26, -9, 32, -13, 30, -10, 26, -13),
++	CABAC_ENTRY(419, 33, -9, 42, -9, 31, -4, 40, -15),
++	CABAC_ENTRY(420, 39, -7, 49, -5, 33, -1, 49, -14),
++	CABAC_ENTRY(421, 41, -2, 53, 0, 33, 7, 44, 3),
++	CABAC_ENTRY(422, 45, 3, 64, 3, 31, 12, 45, 6),
++	CABAC_ENTRY(423, 49, 9, 68, 10, 37, 23, 44, 34),
++	CABAC_ENTRY(424, 45, 27, 66, 27, 31, 38, 33, 54),
++	CABAC_ENTRY(425, 36, 59, 47, 57, 20, 64, 19, 82),
++	CABAC_ENTRY(426, -6, 66, -5, 71, -9, 71, -3, 75),
++	CABAC_ENTRY(427, -7, 35, 0, 24, -7, 37, -1, 23),
++	CABAC_ENTRY(428, -7, 42, -1, 36, -8, 44, 1, 34),
++	CABAC_ENTRY(429, -8, 45, -2, 42, -11, 49, 1, 43),
++	CABAC_ENTRY(430, -5, 48, -2, 52, -10, 56, 0, 54),
++	CABAC_ENTRY(431, -12, 56, -9, 57, -12, 59, -2, 55),
++	CABAC_ENTRY(432, -6, 60, -6, 63, -8, 63, 0, 61),
++	CABAC_ENTRY(433, -5, 62, -4, 65, -9, 67, 1, 64),
++	CABAC_ENTRY(434, -8, 66, -4, 67, -6, 68, 0, 68),
++	CABAC_ENTRY(435, -8, 76, -7, 82, -10, 79, -9, 92),
++	CABAC_ENTRY(436, -5, 85, -3, 81, -3, 78, -14, 106),
++	CABAC_ENTRY(437, -6, 81, -3, 76, -8, 74, -13, 97),
++	CABAC_ENTRY(438, -10, 77, -7, 72, -9, 72, -15, 90),
++	CABAC_ENTRY(439, -7, 81, -6, 78, -10, 72, -12, 90),
++	CABAC_ENTRY(440, -17, 80, -12, 72, -18, 75, -18, 88),
++	CABAC_ENTRY(441, -18, 73, -14, 68, -12, 71, -10, 73),
++	CABAC_ENTRY(442, -4, 74, -3, 70, -11, 63, -9, 79),
++	CABAC_ENTRY(443, -10, 83, -6, 76, -5, 70, -14, 86),
++	CABAC_ENTRY(444, -9, 71, -5, 66, -17, 75, -10, 73),
++	CABAC_ENTRY(445, -9, 67, -5, 62, -14, 72, -10, 70),
++	CABAC_ENTRY(446, -1, 61, 0, 57, -16, 67, -10, 69),
++	CABAC_ENTRY(447, -8, 66, -4, 61, -8, 53, -5, 66),
++	CABAC_ENTRY(448, -14, 66, -9, 60, -14, 59, -9, 64),
++	CABAC_ENTRY(449, 0, 59, 1, 54, -9, 52, -5, 58),
++	CABAC_ENTRY(450, 2, 59, 2, 58, -11, 68, 2, 59),
++	CABAC_ENTRY(451, 21, -13, 17, -10, 9, -2, 21, -10),
++	CABAC_ENTRY(452, 33, -14, 32, -13, 30, -10, 24, -11),
++	CABAC_ENTRY(453, 39, -7, 42, -9, 31, -4, 28, -8),
++	CABAC_ENTRY(454, 46, -2, 49, -5, 33, -1, 28, -1),
++	CABAC_ENTRY(455, 51, 2, 53, 0, 33, 7, 29, 3),
++	CABAC_ENTRY(456, 60, 6, 64, 3, 31, 12, 29, 9),
++	CABAC_ENTRY(457, 61, 17, 68, 10, 37, 23, 35, 20),
++	CABAC_ENTRY(458, 55, 34, 66, 27, 31, 38, 29, 36),
++	CABAC_ENTRY(459, 42, 62, 47, 57, 20, 64, 14, 67),
++};
++
++#endif /* RKVDEC_H264_CABAC_H_ */
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Fri, 14 Jun 2024 19:52:12 -0400
+Subject: media: rockchip: Introduce the rkvdec2 driver
+
+This driver supports the second generation of the Rockchip Video
+decoder, also known as vdpu34x.
+It is currently only used on the RK3588(s) SoC.
+
+There are 2 decoders on the RK3588 SoC that can work in pair to decode
+8K video at 30 FPS but currently, only using one core at a time is
+supported.
+
+Scheduling requests between the two cores will be implemented later.
+
+The core supports H264, HEVC, VP9 and AVS2 decoding but this driver
+currently only supports H264.
+
+The driver is based on rkvdec and they may share some code in the
+future.
+The decision to make a different driver is mainly because rkvdec2 has
+more features and can work with multiple cores.
+
+The registers are mapped in a struct in RAM using bitfields. It is IO
+copied to the HW when all values are configured.
+The decision to use such a struct instead of writing buffers one by one
+is based on the following reasons:
+ - Rockchip cores are known to misbehave when registers are not written
+   in address order,
+ - Those cores also need the software to write all registers, even if
+   they are written their default values or are not related to the task
+   (this core will not start decoding some H264 frames if some VP9
+   registers are not written to 0)
+ - In the future, to support multiple cores, the scheduler could be
+   optimized by storing the precomputed registers values and copy them
+   to the HW as soos as a core becomes available.
+
+This makes the code more readable and may bring performance improvements
+in future features.
+
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+---
+ drivers/media/platform/rockchip/Kconfig                |    1 +
+ drivers/media/platform/rockchip/Makefile               |    1 +
+ drivers/media/platform/rockchip/rkvdec2/Kconfig        |   15 +
+ drivers/media/platform/rockchip/rkvdec2/Makefile       |    3 +
+ drivers/media/platform/rockchip/rkvdec2/rkvdec2-h264.c |  744 ++++++
+ drivers/media/platform/rockchip/rkvdec2/rkvdec2-regs.h |  346 +++
+ drivers/media/platform/rockchip/rkvdec2/rkvdec2.c      | 1263 ++++++++++
+ drivers/media/platform/rockchip/rkvdec2/rkvdec2.h      |  130 +
+ 8 files changed, 2503 insertions(+)
+
+diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/rockchip/Kconfig
++++ b/drivers/media/platform/rockchip/Kconfig
+@@ -4,3 +4,4 @@ comment "Rockchip media platform drivers"
+ 
+ source "drivers/media/platform/rockchip/rga/Kconfig"
+ source "drivers/media/platform/rockchip/rkisp1/Kconfig"
++source "drivers/media/platform/rockchip/rkvdec2/Kconfig"
+diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/rockchip/Makefile
++++ b/drivers/media/platform/rockchip/Makefile
+@@ -1,3 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ obj-y += rga/
+ obj-y += rkisp1/
++obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC2)	+= rkvdec2/
+diff --git a/drivers/media/platform/rockchip/rkvdec2/Kconfig b/drivers/media/platform/rockchip/rkvdec2/Kconfig
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/rockchip/rkvdec2/Kconfig
+@@ -0,0 +1,15 @@
++# SPDX-License-Identifier: GPL-2.0
++config VIDEO_ROCKCHIP_VDEC2
++	tristate "Rockchip Video Decoder driver 2"
++	depends on ARCH_ROCKCHIP || COMPILE_TEST
++	depends on VIDEO_DEV
++	select MEDIA_CONTROLLER
++	select VIDEOBUF2_DMA_CONTIG
++	select VIDEOBUF2_VMALLOC
++	select V4L2_MEM2MEM_DEV
++	select V4L2_H264
++	help
++	  Support for the Rockchip Video Decoder 2 IP present on Rockchip SoCs,
++	  which accelerates video decoding.
++	  To compile this driver as a module, choose M here: the module
++	  will be called rockchip-vdec2.
+diff --git a/drivers/media/platform/rockchip/rkvdec2/Makefile b/drivers/media/platform/rockchip/rkvdec2/Makefile
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/rockchip/rkvdec2/Makefile
+@@ -0,0 +1,3 @@
++obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC2) += rockchip-vdec2.o
++
++rockchip-vdec2-y += rkvdec2.o rkvdec2-h264.o
+diff --git a/drivers/media/platform/rockchip/rkvdec2/rkvdec2-h264.c b/drivers/media/platform/rockchip/rkvdec2/rkvdec2-h264.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/rockchip/rkvdec2/rkvdec2-h264.c
+@@ -0,0 +1,744 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Rockchip Video Decoder 2 H264 backend
++ *
++ * Copyright (C) 2024 Collabora, Ltd.
++ *  Detlev Casanova <detlev.casanova@collabora.com>
++ *
++ * Based on rkvdec driver by Boris Brezillon <boris.brezillon@collabora.com>
++ */
++
++#include <media/v4l2-h264.h>
++#include <media/v4l2-mem2mem.h>
++#include <media/v4l2-cabac/rkvdec-cabac.h>
++
++#include "rkvdec2.h"
++#include "rkvdec2-regs.h"
++
++#define RKVDEC_NUM_REFLIST		3
++
++struct rkvdec2_h264_scaling_list {
++	u8 scaling_list_4x4[6][16];
++	u8 scaling_list_8x8[6][64];
++	u8 padding[128];
++};
++
++struct rkvdec2_sps {
++	u16 seq_parameter_set_id:			4;
++	u16 profile_idc:				8;
++	u16 constraint_set3_flag:			1;
++	u16 chroma_format_idc:				2;
++	u16 bit_depth_luma:				3;
++	u16 bit_depth_chroma:				3;
++	u16 qpprime_y_zero_transform_bypass_flag:	1;
++	u16 log2_max_frame_num_minus4:			4;
++	u16 max_num_ref_frames:				5;
++	u16 pic_order_cnt_type:				2;
++	u16 log2_max_pic_order_cnt_lsb_minus4:		4;
++	u16 delta_pic_order_always_zero_flag:		1;
++	u16 pic_width_in_mbs:				12;
++	u16 pic_height_in_mbs:				12;
++	u16 frame_mbs_only_flag:			1;
++	u16 mb_adaptive_frame_field_flag:		1;
++	u16 direct_8x8_inference_flag:			1;
++	u16 mvc_extension_enable:			1;
++	u16 num_views:					2;
++
++	u16 reserved_bits:				12;
++	u16 reserved[11];
++} __packed;
++
++struct rkvdec2_pps {
++	u16 pic_parameter_set_id:				8;
++	u16 pps_seq_parameter_set_id:				5;
++	u16 entropy_coding_mode_flag:				1;
++	u16 bottom_field_pic_order_in_frame_present_flag:	1;
++	u16 num_ref_idx_l0_default_active_minus1:		5;
++	u16 num_ref_idx_l1_default_active_minus1:		5;
++	u16 weighted_pred_flag:					1;
++	u16 weighted_bipred_idc:				2;
++	u16 pic_init_qp_minus26:				7;
++	u16 pic_init_qs_minus26:				6;
++	u16 chroma_qp_index_offset:				5;
++	u16 deblocking_filter_control_present_flag:		1;
++	u16 constrained_intra_pred_flag:			1;
++	u16 redundant_pic_cnt_present:				1;
++	u16 transform_8x8_mode_flag:				1;
++	u16 second_chroma_qp_index_offset:			5;
++	u16 scaling_list_enable_flag:				1;
++	u32 scaling_list_address;
++	u16 is_longterm;
++
++	u8 reserved[3];
++} __packed;
++
++struct rkvdec2_rps_entry {
++	u32 dpb_info0:		5;
++	u32 bottom_flag0:	1;
++	u32 view_index_off0:	1;
++	u32 dpb_info1:		5;
++	u32 bottom_flag1:	1;
++	u32 view_index_off1:	1;
++	u32 dpb_info2:		5;
++	u32 bottom_flag2:	1;
++	u32 view_index_off2:	1;
++	u32 dpb_info3:		5;
++	u32 bottom_flag3:	1;
++	u32 view_index_off3:	1;
++	u32 dpb_info4:		5;
++	u32 bottom_flag4:	1;
++	u32 view_index_off4:	1;
++	u32 dpb_info5:		5;
++	u32 bottom_flag5:	1;
++	u32 view_index_off5:	1;
++	u32 dpb_info6:		5;
++	u32 bottom_flag6:	1;
++	u32 view_index_off6:	1;
++	u32 dpb_info7:		5;
++	u32 bottom_flag7:	1;
++	u32 view_index_off7:	1;
++} __packed;
++
++struct rkvdec2_rps {
++	u16 frame_num[16];
++	u32 reserved0;
++	struct rkvdec2_rps_entry entries[12];
++	u32 reserved1[66];
++}  __packed;
++
++struct rkvdec2_sps_pps {
++	struct rkvdec2_sps sps;
++	struct rkvdec2_pps pps;
++}  __packed;
++
++/* Data structure describing auxiliary buffer format. */
++struct rkvdec2_h264_priv_tbl {
++	u32 cabac_table[4][464][2];
++	struct rkvdec2_h264_scaling_list scaling_list;
++	struct rkvdec2_sps_pps param_set[256];
++	struct rkvdec2_rps rps;
++};
++
++struct rkvdec2_h264_reflists {
++	struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN];
++	struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN];
++	struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN];
++};
++
++struct rkvdec2_h264_run {
++	struct rkvdec2_run base;
++	const struct v4l2_ctrl_h264_decode_params *decode_params;
++	const struct v4l2_ctrl_h264_sps *sps;
++	const struct v4l2_ctrl_h264_pps *pps;
++	const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix;
++	struct vb2_buffer *ref_buf[V4L2_H264_NUM_DPB_ENTRIES];
++};
++
++struct rkvdec2_h264_ctx {
++	struct rkvdec2_aux_buf priv_tbl;
++	struct rkvdec2_h264_reflists reflists;
++	struct rkvdec2_regs_h264 regs;
++};
++
++static void assemble_hw_pps(struct rkvdec2_ctx *ctx,
++			    struct rkvdec2_h264_run *run)
++{
++	struct rkvdec2_h264_ctx *h264_ctx = ctx->priv;
++	const struct v4l2_ctrl_h264_sps *sps = run->sps;
++	const struct v4l2_ctrl_h264_pps *pps = run->pps;
++	const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params;
++	const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb;
++	struct rkvdec2_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu;
++	struct rkvdec2_sps_pps *hw_ps;
++	dma_addr_t scaling_list_address;
++	u32 scaling_distance;
++	u32 i;
++
++	/*
++	 * HW read the SPS/PPS information from PPS packet index by PPS id.
++	 * offset from the base can be calculated by PPS_id * 32 (size per PPS
++	 * packet unit). so the driver copy SPS/PPS information to the exact PPS
++	 * packet unit for HW accessing.
++	 */
++	hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
++	memset(hw_ps, 0, sizeof(*hw_ps));
++
++	/* write sps */
++	hw_ps->sps.seq_parameter_set_id = sps->seq_parameter_set_id;
++	hw_ps->sps.profile_idc = sps->profile_idc;
++	hw_ps->sps.constraint_set3_flag = !!(sps->constraint_set_flags & (1 << 3));
++	hw_ps->sps.chroma_format_idc = sps->chroma_format_idc;
++	hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8;
++	hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8;
++	hw_ps->sps.qpprime_y_zero_transform_bypass_flag = !!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS);
++	hw_ps->sps.log2_max_frame_num_minus4 = sps->log2_max_frame_num_minus4;
++	hw_ps->sps.max_num_ref_frames = sps->max_num_ref_frames;
++	hw_ps->sps.pic_order_cnt_type = sps->pic_order_cnt_type;
++	hw_ps->sps.log2_max_pic_order_cnt_lsb_minus4 =
++		sps->log2_max_pic_order_cnt_lsb_minus4;
++	hw_ps->sps.delta_pic_order_always_zero_flag =
++		!!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO);
++	hw_ps->sps.mvc_extension_enable = 1;
++	hw_ps->sps.num_views = 1;
++
++	/*
++	 * Use the SPS values since they are already in macroblocks
++	 * dimensions, height can be field height (halved) if
++	 * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY is not set and also it allows
++	 * decoding smaller images into larger allocation which can be used
++	 * to implementing SVC spatial layer support.
++	 */
++	hw_ps->sps.pic_width_in_mbs = sps->pic_width_in_mbs_minus1 + 1;
++	hw_ps->sps.pic_height_in_mbs = sps->pic_height_in_map_units_minus1 + 1;
++	hw_ps->sps.frame_mbs_only_flag =
++		!!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY);
++	hw_ps->sps.mb_adaptive_frame_field_flag =
++		!!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD);
++	hw_ps->sps.direct_8x8_inference_flag =
++		!!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE);
++
++	/* write pps */
++	hw_ps->pps.pic_parameter_set_id = pps->pic_parameter_set_id;
++	hw_ps->pps.pps_seq_parameter_set_id = pps->seq_parameter_set_id;
++	hw_ps->pps.entropy_coding_mode_flag =
++		!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE);
++	hw_ps->pps.bottom_field_pic_order_in_frame_present_flag =
++		!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT);
++	hw_ps->pps.num_ref_idx_l0_default_active_minus1 =
++		pps->num_ref_idx_l0_default_active_minus1;
++	hw_ps->pps.num_ref_idx_l1_default_active_minus1 =
++		pps->num_ref_idx_l1_default_active_minus1;
++	hw_ps->pps.weighted_pred_flag =
++		!!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED);
++	hw_ps->pps.weighted_bipred_idc = pps->weighted_bipred_idc;
++	hw_ps->pps.pic_init_qp_minus26 = pps->pic_init_qp_minus26;
++	hw_ps->pps.pic_init_qs_minus26 = pps->pic_init_qs_minus26;
++	hw_ps->pps.chroma_qp_index_offset = pps->chroma_qp_index_offset;
++	hw_ps->pps.deblocking_filter_control_present_flag =
++		!!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT);
++	hw_ps->pps.constrained_intra_pred_flag =
++		!!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED);
++	hw_ps->pps.redundant_pic_cnt_present =
++		!!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT);
++	hw_ps->pps.transform_8x8_mode_flag =
++		!!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE);
++	hw_ps->pps.second_chroma_qp_index_offset = pps->second_chroma_qp_index_offset;
++	hw_ps->pps.scaling_list_enable_flag =
++		!!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT);
++
++	/*
++	 * To be on the safe side, program the scaling matrix address
++	 *
++	 * With this set here,
++	 *  RKVDEC_SWREG12_SENCODARY_EN:sw_scanlist_addr_valid_en
++	 * can stay at 0
++	 */
++	scaling_distance = offsetof(struct rkvdec2_h264_priv_tbl, scaling_list);
++	scaling_list_address = h264_ctx->priv_tbl.dma + scaling_distance;
++	hw_ps->pps.scaling_list_address = scaling_list_address;
++
++	for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
++		if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
++			hw_ps->pps.is_longterm |= (1 << i);
++	}
++}
++
++static void lookup_ref_buf_idx(struct rkvdec2_ctx *ctx,
++			       struct rkvdec2_h264_run *run)
++{
++	const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params;
++	u32 i;
++
++	for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
++		struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
++		const struct v4l2_h264_dpb_entry *dpb = run->decode_params->dpb;
++		struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
++		struct vb2_buffer *buf = NULL;
++
++		if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) {
++			buf = vb2_find_buffer(cap_q, dpb[i].reference_ts);
++			if (!buf) {
++				dev_dbg(ctx->dev->dev, "No buffer for reference_ts %llu",
++					dpb[i].reference_ts);
++			}
++		}
++
++		run->ref_buf[i] = buf;
++	}
++}
++
++static void set_dpb_info(struct rkvdec2_rps_entry *entries,
++			 u8 reflist,
++			 u8 refnum,
++			 u8 info,
++			 bool bottom)
++{
++	struct rkvdec2_rps_entry *entry = &entries[(reflist * 4) + refnum / 8];
++	u8 idx = refnum % 8;
++
++	switch (idx) {
++	case 0:
++		entry->dpb_info0 = info;
++		entry->bottom_flag0 = bottom;
++		break;
++	case 1:
++		entry->dpb_info1 = info;
++		entry->bottom_flag1 = bottom;
++		break;
++	case 2:
++		entry->dpb_info2 = info;
++		entry->bottom_flag2 = bottom;
++		break;
++	case 3:
++		entry->dpb_info3 = info;
++		entry->bottom_flag3 = bottom;
++		break;
++	case 4:
++		entry->dpb_info4 = info;
++		entry->bottom_flag4 = bottom;
++		break;
++	case 5:
++		entry->dpb_info5 = info;
++		entry->bottom_flag5 = bottom;
++		break;
++	case 6:
++		entry->dpb_info6 = info;
++		entry->bottom_flag6 = bottom;
++		break;
++	case 7:
++		entry->dpb_info7 = info;
++		entry->bottom_flag7 = bottom;
++		break;
++	}
++}
++
++static void assemble_hw_rps(struct rkvdec2_ctx *ctx,
++			    struct v4l2_h264_reflist_builder *builder,
++			    struct rkvdec2_h264_run *run)
++{
++	const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params;
++	const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb;
++	struct rkvdec2_h264_ctx *h264_ctx = ctx->priv;
++	struct rkvdec2_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu;
++
++	struct rkvdec2_rps *hw_rps = &priv_tbl->rps;
++	u32 i, j;
++
++	memset(hw_rps, 0, sizeof(priv_tbl->rps));
++
++	/*
++	 * Assign an invalid pic_num if DPB entry at that position is inactive.
++	 * If we assign 0 in that position hardware will treat that as a real
++	 * reference picture with pic_num 0, triggering output picture
++	 * corruption.
++	 */
++	for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
++		if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
++			continue;
++
++		hw_rps->frame_num[i] = builder->refs[i].frame_num;
++	}
++
++	for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
++		for (i = 0; i < builder->num_valid; i++) {
++			struct v4l2_h264_reference *ref;
++			bool dpb_valid;
++			bool bottom;
++
++			switch (j) {
++			case 0:
++				ref = &h264_ctx->reflists.p[i];
++				break;
++			case 1:
++				ref = &h264_ctx->reflists.b0[i];
++				break;
++			case 2:
++				ref = &h264_ctx->reflists.b1[i];
++				break;
++			}
++
++			if (WARN_ON(ref->index >= ARRAY_SIZE(dec_params->dpb)))
++				continue;
++
++			dpb_valid = !!(run->ref_buf[ref->index]);
++			bottom = ref->fields == V4L2_H264_BOTTOM_FIELD_REF;
++
++			set_dpb_info(hw_rps->entries, j, i, ref->index | (dpb_valid << 4), bottom);
++		}
++	}
++}
++
++static void assemble_hw_scaling_list(struct rkvdec2_ctx *ctx,
++				     struct rkvdec2_h264_run *run)
++{
++	const struct v4l2_ctrl_h264_scaling_matrix *scaling = run->scaling_matrix;
++	const struct v4l2_ctrl_h264_pps *pps = run->pps;
++	struct rkvdec2_h264_ctx *h264_ctx = ctx->priv;
++	struct rkvdec2_h264_priv_tbl *tbl = h264_ctx->priv_tbl.cpu;
++
++	if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT))
++		return;
++
++	BUILD_BUG_ON(sizeof(tbl->scaling_list.scaling_list_4x4) !=
++		     sizeof(scaling->scaling_list_4x4));
++	BUILD_BUG_ON(sizeof(tbl->scaling_list.scaling_list_8x8) !=
++		     sizeof(scaling->scaling_list_8x8));
++
++	memcpy(tbl->scaling_list.scaling_list_4x4,
++	       scaling->scaling_list_4x4,
++	       sizeof(scaling->scaling_list_4x4));
++
++	memcpy(tbl->scaling_list.scaling_list_8x8,
++	       scaling->scaling_list_8x8,
++	       sizeof(scaling->scaling_list_8x8));
++}
++
++static inline void rkvdec2_memcpy_toio(void __iomem *dst, void *src, size_t len)
++{
++#ifdef CONFIG_ARM64
++	__iowrite32_copy(dst, src, len);
++#else
++	memcpy_toio(dst, src, len);
++#endif
++}
++
++static void rkvdec2_write_regs(struct rkvdec2_ctx *ctx)
++{
++	struct rkvdec2_dev *rkvdec = ctx->dev;
++	struct rkvdec2_h264_ctx *h264_ctx = ctx->priv;
++
++	rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_COMMON_REGS,
++			    &h264_ctx->regs.common,
++			    sizeof(h264_ctx->regs.common));
++	rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_CODEC_PARAMS_REGS,
++			    &h264_ctx->regs.h264_param,
++			    sizeof(h264_ctx->regs.h264_param));
++	rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_COMMON_ADDR_REGS,
++			    &h264_ctx->regs.common_addr,
++			    sizeof(h264_ctx->regs.common_addr));
++	rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_CODEC_ADDR_REGS,
++			    &h264_ctx->regs.h264_addr,
++			    sizeof(h264_ctx->regs.h264_addr));
++	rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_POC_HIGHBIT_REGS,
++			    &h264_ctx->regs.h264_highpoc,
++			    sizeof(h264_ctx->regs.h264_highpoc));
++}
++
++static void config_registers(struct rkvdec2_ctx *ctx,
++			     struct rkvdec2_h264_run *run)
++{
++	const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params;
++	const struct v4l2_ctrl_h264_sps *sps = run->sps;
++	const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb;
++	struct rkvdec2_h264_ctx *h264_ctx = ctx->priv;
++	dma_addr_t priv_start_addr = h264_ctx->priv_tbl.dma;
++	const struct v4l2_pix_format_mplane *dst_fmt;
++	struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
++	struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
++	struct rkvdec2_regs_h264 *regs = &h264_ctx->regs;
++	const struct v4l2_format *f;
++	dma_addr_t rlc_addr;
++	dma_addr_t dst_addr;
++	u32 hor_virstride = 0;
++	u32 ver_virstride = 0;
++	u32 y_virstride = 0;
++	u32 offset;
++	u32 pixels;
++	u32 i;
++
++	memset(regs, 0, sizeof(*regs));
++
++	/* Set H264 mode */
++	regs->common.reg009.dec_mode = RKVDEC2_MODE_H264;
++
++	/* Set config */
++	regs->common.reg011.buf_empty_en = 1;
++	regs->common.reg011.dec_clkgate_e = 1;
++	regs->common.reg011.dec_timeout_e = 1;
++	regs->common.reg011.pix_range_detection_e = 1;
++
++	/* Set IDR flag */
++	regs->common.reg013.cur_pic_is_idr =
++		!!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC);
++
++	/* Set input stream length */
++	regs->common.stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
++
++	/* Set max slice number */
++	regs->common.reg017.slice_num = MAX_SLICE_NUMBER;
++
++	/* Set strides */
++	f = &ctx->decoded_fmt;
++	dst_fmt = &f->fmt.pix_mp;
++	hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8;
++	ver_virstride = round_up(dst_fmt->height, 16);
++	y_virstride = hor_virstride * ver_virstride;
++	pixels = dst_fmt->height * dst_fmt->width;
++
++	regs->common.reg018.y_hor_virstride = hor_virstride / 16;
++	regs->common.reg019.uv_hor_virstride = hor_virstride / 16;
++	regs->common.reg020.y_virstride = y_virstride / 16;
++
++	/* Activate block gating */
++	regs->common.reg026.swreg_block_gating_e = 0xfffef;
++	regs->common.reg026.reg_cfg_gating_en = 1;
++
++	/* Set timeout threshold */
++	if (pixels < RKVDEC2_1080P_PIXELS)
++		regs->common.timeout_threshold = RKVDEC2_TIMEOUT_1080p;
++	else if (pixels < RKVDEC2_4K_PIXELS)
++		regs->common.timeout_threshold = RKVDEC2_TIMEOUT_4K;
++	else if (pixels < RKVDEC2_8K_PIXELS)
++		regs->common.timeout_threshold = RKVDEC2_TIMEOUT_8K;
++	else
++		regs->common.timeout_threshold = RKVDEC2_TIMEOUT_MAX;
++
++	/* Set TOP and BOTTOM POCs */
++	regs->h264_param.cur_top_poc = dec_params->top_field_order_cnt;
++	regs->h264_param.cur_bot_poc = dec_params->bottom_field_order_cnt;
++
++	/* Set ref pic address & poc */
++	for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
++		struct vb2_buffer *vb_buf = run->ref_buf[i];
++		dma_addr_t buf_dma;
++
++		/*
++		 * If a DPB entry is unused or invalid, address of current destination
++		 * buffer is returned.
++		 */
++		if (!vb_buf)
++			vb_buf = &dst_buf->vb2_buf;
++
++		buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
++
++		/* Set reference addresses */
++		regs->h264_addr.ref_base[i] = buf_dma;
++
++		/* Set COLMV addresses */
++		regs->h264_addr.colmv_base[i] = buf_dma + ctx->colmv_offset;
++
++		struct rkvdec2_h264_ref_info *ref_info =
++			&regs->h264_param.ref_info_regs[i / 4].ref_info[i % 4];
++
++		ref_info->ref_field =
++			!!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD);
++		ref_info->ref_colmv_use_flag =
++			!!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE);
++		ref_info->ref_topfield_used =
++			!!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF);
++		ref_info->ref_botfield_used =
++			!!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF);
++
++		regs->h264_param.ref_pocs[i * 2] =
++			dpb[i].top_field_order_cnt;
++		regs->h264_param.ref_pocs[i * 2 + 1] =
++			dpb[i].bottom_field_order_cnt;
++	}
++
++	/* Set rlc base address (input stream) */
++	rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
++	regs->common_addr.rlc_base = rlc_addr;
++	regs->common_addr.rlcwrite_base = rlc_addr;
++
++	/* Set output base address */
++	dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
++	regs->common_addr.decout_base = dst_addr;
++
++	/* Set colmv address */
++	regs->common_addr.colmv_cur_base = dst_addr + ctx->colmv_offset;
++
++	/* Set RCB addresses */
++	for (i = 0; i < RKVDEC2_RCB_COUNT; i++)
++		regs->common_addr.rcb_base[i] = ctx->rcb_bufs[i].dma;
++
++	/* Set hw pps address */
++	offset = offsetof(struct rkvdec2_h264_priv_tbl, param_set);
++	regs->h264_addr.pps_base = priv_start_addr + offset;
++
++	/* Set hw rps address */
++	offset = offsetof(struct rkvdec2_h264_priv_tbl, rps);
++	regs->h264_addr.rps_base = priv_start_addr + offset;
++
++	/* Set cabac table */
++	offset = offsetof(struct rkvdec2_h264_priv_tbl, cabac_table);
++	regs->h264_addr.cabactbl_base = priv_start_addr + offset;
++
++	rkvdec2_write_regs(ctx);
++}
++
++#define RKVDEC_H264_MAX_DEPTH_IN_BYTES		2
++
++static int rkvdec2_h264_adjust_fmt(struct rkvdec2_ctx *ctx,
++				   struct v4l2_format *f)
++{
++	struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
++
++	fmt->num_planes = 1;
++	if (!fmt->plane_fmt[0].sizeimage)
++		fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
++					      RKVDEC_H264_MAX_DEPTH_IN_BYTES;
++	return 0;
++}
++
++static int rkvdec2_h264_validate_sps(struct rkvdec2_ctx *ctx,
++				     const struct v4l2_ctrl_h264_sps *sps)
++{
++	unsigned int width, height;
++
++	/*
++	 * TODO: The hardware supports 10-bit and 4:2:2 profiles,
++	 * but it's currently broken in the driver.
++	 * Reject them for now, until it's fixed.
++	 */
++	if (sps->chroma_format_idc > 1)
++		/* Only 4:0:0 and 4:2:0 are supported */
++		return -EINVAL;
++	if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
++		/* Luma and chroma bit depth mismatch */
++		return -EINVAL;
++	if (sps->bit_depth_luma_minus8 != 0)
++		/* Only 8-bit is supported */
++		return -EINVAL;
++
++	width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
++	height = (sps->pic_height_in_map_units_minus1 + 1) * 16;
++
++	/*
++	 * When frame_mbs_only_flag is not set, this is field height,
++	 * which is half the final height (see (7-8) in the
++	 * specification)
++	 */
++	if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
++		height *= 2;
++
++	if (width > ctx->coded_fmt.fmt.pix_mp.width ||
++	    height > ctx->coded_fmt.fmt.pix_mp.height)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int rkvdec2_h264_start(struct rkvdec2_ctx *ctx)
++{
++	struct rkvdec2_dev *rkvdec = ctx->dev;
++	struct rkvdec2_h264_priv_tbl *priv_tbl;
++	struct rkvdec2_h264_ctx *h264_ctx;
++	struct v4l2_ctrl *ctrl;
++	int ret;
++
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_H264_SPS);
++	if (!ctrl)
++		return -EINVAL;
++
++	ret = rkvdec2_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
++	if (ret)
++		return ret;
++
++	h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL);
++	if (!h264_ctx)
++		return -ENOMEM;
++
++	priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
++				      &h264_ctx->priv_tbl.dma, GFP_KERNEL);
++	if (!priv_tbl) {
++		ret = -ENOMEM;
++		goto err_free_ctx;
++	}
++
++	h264_ctx->priv_tbl.size = sizeof(*priv_tbl);
++	h264_ctx->priv_tbl.cpu = priv_tbl;
++	memcpy(priv_tbl->cabac_table, rkvdec_h264_cabac_table,
++	       sizeof(rkvdec_h264_cabac_table));
++
++	ctx->priv = h264_ctx;
++	return 0;
++
++err_free_ctx:
++	kfree(h264_ctx);
++	return ret;
++}
++
++static void rkvdec2_h264_stop(struct rkvdec2_ctx *ctx)
++{
++	struct rkvdec2_h264_ctx *h264_ctx = ctx->priv;
++	struct rkvdec2_dev *rkvdec = ctx->dev;
++
++	dma_free_coherent(rkvdec->dev, h264_ctx->priv_tbl.size,
++			  h264_ctx->priv_tbl.cpu, h264_ctx->priv_tbl.dma);
++	kfree(h264_ctx);
++}
++
++static void rkvdec2_h264_run_preamble(struct rkvdec2_ctx *ctx,
++				      struct rkvdec2_h264_run *run)
++{
++	struct v4l2_ctrl *ctrl;
++
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_H264_DECODE_PARAMS);
++	run->decode_params = ctrl ? ctrl->p_cur.p : NULL;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_H264_SPS);
++	run->sps = ctrl ? ctrl->p_cur.p : NULL;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_H264_PPS);
++	run->pps = ctrl ? ctrl->p_cur.p : NULL;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_H264_SCALING_MATRIX);
++	run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
++
++	rkvdec2_run_preamble(ctx, &run->base);
++}
++
++static int rkvdec2_h264_run(struct rkvdec2_ctx *ctx)
++{
++	struct v4l2_h264_reflist_builder reflist_builder;
++	struct rkvdec2_dev *rkvdec = ctx->dev;
++	struct rkvdec2_h264_ctx *h264_ctx = ctx->priv;
++	struct rkvdec2_h264_run run;
++	uint32_t watchdog_time;
++
++	rkvdec2_h264_run_preamble(ctx, &run);
++
++	/* Build the P/B{0,1} ref lists. */
++	v4l2_h264_init_reflist_builder(&reflist_builder, run.decode_params,
++				       run.sps, run.decode_params->dpb);
++	v4l2_h264_build_p_ref_list(&reflist_builder, h264_ctx->reflists.p);
++	v4l2_h264_build_b_ref_lists(&reflist_builder, h264_ctx->reflists.b0,
++				    h264_ctx->reflists.b1);
++
++	assemble_hw_scaling_list(ctx, &run);
++	assemble_hw_pps(ctx, &run);
++	lookup_ref_buf_idx(ctx, &run);
++	assemble_hw_rps(ctx, &reflist_builder, &run);
++
++	config_registers(ctx, &run);
++
++	rkvdec2_run_postamble(ctx, &run.base);
++
++	/* Set watchdog at 2 times the hardware timeout threshold */
++	u64 timeout_threshold = h264_ctx->regs.common.timeout_threshold;
++	watchdog_time = 2 * (1000 * timeout_threshold) / clk_get_rate(rkvdec->clocks[0].clk);
++	schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(watchdog_time));
++
++	/* Start decoding! */
++	writel(RKVDEC2_REG_DEC_E_BIT, rkvdec->regs + RKVDEC2_REG_DEC_E);
++
++	return 0;
++}
++
++static int rkvdec2_h264_try_ctrl(struct rkvdec2_ctx *ctx, struct v4l2_ctrl *ctrl)
++{
++	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS)
++		return rkvdec2_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
++
++	return 0;
++}
++
++const struct rkvdec2_coded_fmt_ops rkvdec2_h264_fmt_ops = {
++	.adjust_fmt = rkvdec2_h264_adjust_fmt,
++	.start = rkvdec2_h264_start,
++	.stop = rkvdec2_h264_stop,
++	.run = rkvdec2_h264_run,
++	.try_ctrl = rkvdec2_h264_try_ctrl,
++};
+diff --git a/drivers/media/platform/rockchip/rkvdec2/rkvdec2-regs.h b/drivers/media/platform/rockchip/rkvdec2/rkvdec2-regs.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/rockchip/rkvdec2/rkvdec2-regs.h
+@@ -0,0 +1,346 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Rockchip Video Decoder 2 driver registers description
++ *
++ * Copyright (C) 2024 Collabora, Ltd.
++ *  Detlev Casanova <detlev.casanova@collabora.com>
++ */
++
++#ifndef _RKVDEC_REGS_H_
++#define _RKVDEC_REGS_H_
++
++#define OFFSET_COMMON_REGS		(8 * sizeof(u32))
++#define OFFSET_CODEC_PARAMS_REGS	(64 * sizeof(u32))
++#define OFFSET_COMMON_ADDR_REGS		(128 * sizeof(u32))
++#define OFFSET_CODEC_ADDR_REGS		(160 * sizeof(u32))
++#define OFFSET_POC_HIGHBIT_REGS		(200 * sizeof(u32))
++
++#define RKVDEC2_MODE_HEVC	0
++#define RKVDEC2_MODE_H264	1
++#define RKVDEC2_MODE_VP9	2
++#define RKVDEC2_MODE_AVS2	3
++
++#define MAX_SLICE_NUMBER	0x3fff
++
++#define RKVDEC2_1080P_PIXELS		(1920 * 1080)
++#define RKVDEC2_4K_PIXELS		(4096 * 2304)
++#define RKVDEC2_8K_PIXELS		(7680 * 4320)
++#define RKVDEC2_TIMEOUT_1080p		(0xefffff)
++#define RKVDEC2_TIMEOUT_4K		(0x2cfffff)
++#define RKVDEC2_TIMEOUT_8K		(0x4ffffff)
++#define RKVDEC2_TIMEOUT_MAX		(0xffffffff)
++
++#define RKVDEC2_REG_DEC_E		0x028
++#define RKVDEC2_REG_DEC_E_BIT		1
++
++#define RKVDEC2_REG_IMPORTANT_EN	0x02c
++#define RKVDEC2_REG_DEC_IRQ_DISABLE	BIT(4)
++
++#define RKVDEC2_REG_STA_INT		0x380
++#define STA_INT_DEC_RDY_STA		BIT(2)
++
++/* base: OFFSET_COMMON_REGS */
++struct rkvdec2_regs_common {
++	struct rkvdec2_in_out {
++		u32 in_endian		: 1;
++		u32 in_swap32_e		: 1;
++		u32 in_swap64_e		: 1;
++		u32 str_endian		: 1;
++		u32 str_swap32_e	: 1;
++		u32 str_swap64_e	: 1;
++		u32 out_endian		: 1;
++		u32 out_swap32_e	: 1;
++		u32 out_cbcr_swap	: 1;
++		u32 out_swap64_e	: 1;
++		u32 reserved		: 22;
++	} reg008;
++
++	struct rkvdec2_dec_mode {
++		u32 dec_mode	: 10;
++		u32 reserved	: 22;
++	} reg009;
++
++	struct rkvdec2_dec_e {
++		u32 dec_e	: 1;
++		u32 reserved	: 31;
++	} reg010;
++
++	struct rkvdec2_important_en {
++		u32 reserved			: 1;
++		u32 dec_clkgate_e		: 1;
++		u32 dec_e_strmd_clkgate_dis	: 1;
++		u32 reserved0			: 1;
++
++		u32 dec_irq_dis			: 1;
++		u32 dec_timeout_e		: 1;
++		u32 buf_empty_en		: 1;
++		u32 reserved1			: 3;
++
++		u32 dec_e_rewrite_valid		: 1;
++		u32 reserved2			: 9;
++		u32 softrst_en_p		: 1;
++		u32 force_softreset_valid	: 1;
++		u32 reserved3			: 2;
++		u32 pix_range_detection_e	: 1;
++		u32 reserved4			: 7;
++	} reg011;
++
++	struct rkvdec2_sencodary_en {
++		u32 wr_ddr_align_en		: 1;
++		u32 colmv_compress_en		: 1;
++		u32 fbc_e			: 1;
++		u32 reserved0			: 1;
++
++		u32 buspr_slot_disable		: 1;
++		u32 error_info_en		: 1;
++		u32 info_collect_en		: 1;
++		u32 wait_reset_en		: 1;
++
++		u32 scanlist_addr_valid_en	: 1;
++		u32 scale_down_en		: 1;
++		u32 error_cfg_wr_disable	: 1;
++		u32 reserved1			: 21;
++	} reg012;
++
++	struct rkvdec2_en_mode_set {
++		u32 timeout_mode		: 1;
++		u32 req_timeout_rst_sel		: 1;
++		u32 reserved0			: 1;
++		u32 dec_commonirq_mode		: 1;
++		u32 reserved1			: 2;
++		u32 stmerror_waitdecfifo_empty	: 1;
++		u32 reserved2			: 2;
++		u32 h26x_streamd_error_mode	: 1;
++		u32 reserved3			: 2;
++		u32 allow_not_wr_unref_bframe	: 1;
++		u32 fbc_output_wr_disable	: 1;
++		u32 reserved4			: 1;
++		u32 colmv_error_mode		: 1;
++
++		u32 reserved5			: 2;
++		u32 h26x_error_mode		: 1;
++		u32 reserved6			: 2;
++		u32 ycacherd_prior		: 1;
++		u32 reserved7			: 2;
++		u32 cur_pic_is_idr		: 1;
++		u32 reserved8			: 1;
++		u32 right_auto_rst_disable	: 1;
++		u32 frame_end_err_rst_flag	: 1;
++		u32 rd_prior_mode		: 1;
++		u32 rd_ctrl_prior_mode		: 1;
++		u32 reserved9			: 1;
++		u32 filter_outbuf_mode		: 1;
++	} reg013;
++
++	struct rkvdec2_fbc_param_set {
++		u32 fbc_force_uncompress	: 1;
++
++		u32 reserved0			: 2;
++		u32 allow_16x8_cp_flag		: 1;
++		u32 reserved1			: 2;
++
++		u32 fbc_h264_exten_4or8_flag	: 1;
++		u32 reserved2			: 25;
++	} reg014;
++
++	struct rkvdec2_stream_param_set {
++		u32 rlc_mode_direct_write	: 1;
++		u32 rlc_mode			: 1;
++		u32 reserved0			: 3;
++
++		u32 strm_start_bit		: 7;
++		u32 reserved1			: 20;
++	} reg015;
++
++	u32 stream_len;
++
++	struct rkvdec2_slice_number {
++		u32 slice_num	: 25;
++		u32 reserved	: 7;
++	} reg017;
++
++	struct rkvdec2_y_hor_stride {
++		u32 y_hor_virstride	: 16;
++		u32 reserved		: 16;
++	} reg018;
++
++	struct rkvdec2_uv_hor_stride {
++		u32 uv_hor_virstride	: 16;
++		u32 reserved		: 16;
++	} reg019;
++
++	struct rkvdec2_y_stride {
++		u32 y_virstride		: 28;
++		u32 reserved		: 4;
++	} reg020;
++
++	struct rkvdec2_error_ctrl_set {
++		u32 inter_error_prc_mode		: 1;
++		u32 error_intra_mode			: 1;
++		u32 error_deb_en			: 1;
++		u32 picidx_replace			: 5;
++		u32 error_spread_e			: 1;
++		u32 reserved0				: 3;
++		u32 error_inter_pred_cross_slice	: 1;
++		u32 reserved1				: 11;
++		u32 roi_error_ctu_cal_en		: 1;
++		u32 reserved2				: 7;
++	} reg021;
++
++	struct rkvdec2_err_roi_ctu_offset_start {
++		u32 roi_x_ctu_offset_st	: 12;
++		u32 reserved0		: 4;
++		u32 roi_y_ctu_offset_st	: 12;
++		u32 reserved1		: 4;
++	} reg022;
++
++	struct rkvdec2_err_roi_ctu_offset_end {
++		u32 roi_x_ctu_offset_end	: 12;
++		u32 reserved0			: 4;
++		u32 roi_y_ctu_offset_end	: 12;
++		u32 reserved1			: 4;
++	} reg023;
++
++	struct rkvdec2_cabac_error_en_lowbits {
++		u32 cabac_err_en_lowbits	: 32;
++	} reg024;
++
++	struct rkvdec2_cabac_error_en_highbits {
++		u32 cabac_err_en_highbits	: 30;
++		u32 reserved			: 2;
++	} reg025;
++
++	struct rkvdec2_block_gating_en {
++		u32 swreg_block_gating_e	: 20;
++		u32 reserved			: 11;
++		u32 reg_cfg_gating_en		: 1;
++	} reg026;
++
++	struct SW027_CORE_SAFE_PIXELS {
++		u32 core_safe_x_pixels	: 16;
++		u32 core_safe_y_pixels	: 16;
++	} reg027;
++
++	struct rkvdec2_multiply_core_ctrl {
++		u32 swreg_vp9_wr_prob_idx	: 3;
++		u32 reserved0			: 1;
++		u32 swreg_vp9_rd_prob_idx	: 3;
++		u32 reserved1			: 1;
++
++		u32 swreg_ref_req_advance_flag	: 1;
++		u32 sw_colmv_req_advance_flag	: 1;
++		u32 sw_poc_only_highbit_flag	: 1;
++		u32 sw_poc_arb_flag		: 1;
++
++		u32 reserved2			: 4;
++		u32 sw_film_idx			: 10;
++		u32 reserved3			: 2;
++		u32 sw_pu_req_mismatch_dis	: 1;
++		u32 sw_colmv_req_mismatch_dis	: 1;
++		u32 reserved4			: 2;
++	} reg028;
++
++	struct SW029_SCALE_DOWN_CTRL {
++		u32 scale_down_hor_ratio	: 2;
++		u32 reserved0			: 6;
++		u32 scale_down_vrz_ratio	: 2;
++		u32 reserved1			: 22;
++	} reg029;
++
++	struct SW032_Y_SCALE_DOWN_TILE8x8_HOR_STRIDE {
++		u32 y_scale_down_hor_stride	: 20;
++		u32 reserved0			: 12;
++	} reg030;
++
++	struct SW031_UV_SCALE_DOWN_TILE8x8_HOR_STRIDE {
++		u32 uv_scale_down_hor_stride	: 20;
++		u32 reserved0			: 12;
++	} reg031;
++
++	u32 timeout_threshold;
++} __packed;
++
++/* base: OFFSET_COMMON_ADDR_REGS */
++struct rkvdec2_regs_common_addr {
++	u32 rlc_base;
++	u32 rlcwrite_base;
++	u32 decout_base;
++	u32 colmv_cur_base;
++	u32 error_ref_base;
++	u32 rcb_base[10];
++} __packed;
++
++/* base: OFFSET_CODEC_PARAMS_REGS */
++struct rkvdec2_regs_h264_params {
++	struct rkvdec2_h26x_set {
++		u32 h26x_frame_orslice		: 1;
++		u32 h26x_rps_mode		: 1;
++		u32 h26x_stream_mode		: 1;
++		u32 h26x_stream_lastpacket	: 1;
++		u32 h264_firstslice_flag	: 1;
++		u32 reserved			: 27;
++	} reg064;
++
++	u32 cur_top_poc;
++	u32 cur_bot_poc;
++	u32 ref_pocs[32];
++
++	struct rkvdec2_h264_info {
++		struct rkvdec2_h264_ref_info {
++			u32 ref_field		: 1;
++			u32 ref_topfield_used	: 1;
++			u32 ref_botfield_used	: 1;
++			u32 ref_colmv_use_flag	: 1;
++			u32 ref_reserved	: 4;
++		} __packed ref_info[4];
++	} __packed ref_info_regs[4];
++
++	u32 reserved_103_111[9];
++
++	struct rkvdec2_error_ref_info {
++		u32 avs2_ref_error_field	: 1;
++		u32 avs2_ref_error_topfield	: 1;
++		u32 ref_error_topfield_used	: 1;
++		u32 ref_error_botfield_used	: 1;
++		u32 reserved			: 28;
++	} reg112;
++} __packed;
++
++/* base: OFFSET_CODEC_ADDR_REGS */
++struct rkvdec2_regs_h264_addr {
++	u32 reserved_160;
++	u32 pps_base;
++	u32 reserved_162;
++	u32 rps_base;
++	u32 ref_base[16];
++	u32 scanlist_addr;
++	u32 colmv_base[16];
++	u32 cabactbl_base;
++} __packed;
++
++struct rkvdec2_regs_h264_highpoc {
++	struct rkvdec2_ref_poc_highbit {
++		u32 ref0_poc_highbit	: 4;
++		u32 ref1_poc_highbit	: 4;
++		u32 ref2_poc_highbit	: 4;
++		u32 ref3_poc_highbit	: 4;
++		u32 ref4_poc_highbit	: 4;
++		u32 ref5_poc_highbit	: 4;
++		u32 ref6_poc_highbit	: 4;
++		u32 ref7_poc_highbit	: 4;
++	} reg200[4];
++	struct rkvdec2_cur_poc_highbit {
++		u32 cur_poc_highbit	: 4;
++		u32 reserved		: 28;
++	} reg204;
++} __packed;
++
++struct rkvdec2_regs_h264 {
++	struct rkvdec2_regs_common		common;
++	struct rkvdec2_regs_h264_params		h264_param;
++	struct rkvdec2_regs_common_addr		common_addr;
++	struct rkvdec2_regs_h264_addr		h264_addr;
++	struct rkvdec2_regs_h264_highpoc	h264_highpoc;
++} __packed;
++
++#endif /* __RKVDEC_REGS_H__ */
+diff --git a/drivers/media/platform/rockchip/rkvdec2/rkvdec2.c b/drivers/media/platform/rockchip/rkvdec2/rkvdec2.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/rockchip/rkvdec2/rkvdec2.c
+@@ -0,0 +1,1263 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Rockchip Video Decoder 2 driver
++ *
++ * Copyright (C) 2024 Collabora, Ltd.
++ *  Detlev Casanova <detlev.casanova@collabora.com>
++ *
++ * Based on rkvdec driver by Boris Brezillon <boris.brezillon@collabora.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/genalloc.h>
++#include <linux/interrupt.h>
++#include <linux/iommu.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm.h>
++#include <linux/pm_runtime.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/workqueue.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-mem2mem.h>
++#include <media/videobuf2-core.h>
++#include <media/videobuf2-vmalloc.h>
++
++#include "rkvdec2.h"
++
++static int rkvdec2_try_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct rkvdec2_ctx *ctx = container_of(ctrl->handler, struct rkvdec2_ctx, ctrl_hdl);
++	const struct rkvdec2_coded_fmt_desc *desc = ctx->coded_fmt_desc;
++
++	if (desc->ops->try_ctrl)
++		return desc->ops->try_ctrl(ctx, ctrl);
++
++	return 0;
++}
++
++static const struct v4l2_ctrl_ops rkvdec2_ctrl_ops = {
++	.try_ctrl = rkvdec2_try_ctrl,
++};
++
++static const struct rkvdec2_ctrl_desc rkvdec2_h264_ctrl_descs[] = {
++	{
++		.cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_H264_SPS,
++		.cfg.ops = &rkvdec2_ctrl_ops,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_H264_PPS,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_H264_DECODE_MODE,
++		.cfg.min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
++		.cfg.max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
++		.cfg.def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_H264_START_CODE,
++		.cfg.min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
++		.cfg.def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
++		.cfg.max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
++	},
++	{
++		.cfg.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
++		.cfg.min = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE,
++		.cfg.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
++		.cfg.menu_skip_mask =
++			BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
++		.cfg.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
++	},
++	{
++		.cfg.id = V4L2_CID_MPEG_VIDEO_H264_LEVEL,
++		.cfg.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
++		.cfg.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_1,
++	},
++};
++
++static const struct rkvdec2_ctrls rkvdec2_h264_ctrls = {
++	.ctrls = rkvdec2_h264_ctrl_descs,
++	.num_ctrls = ARRAY_SIZE(rkvdec2_h264_ctrl_descs),
++};
++
++static const u32 rkvdec2_h264_decoded_fmts[] = {
++	V4L2_PIX_FMT_NV12
++};
++
++static const struct rkvdec2_coded_fmt_desc rkvdec2_coded_fmts[] = {
++	{
++		.fourcc = V4L2_PIX_FMT_H264_SLICE,
++		.frmsize = {
++			.min_width = 16,
++			.max_width =  65520,
++			.step_width = 16,
++			.min_height = 16,
++			.max_height =  65520,
++			.step_height = 16,
++		},
++		.ctrls = &rkvdec2_h264_ctrls,
++		.ops = &rkvdec2_h264_fmt_ops,
++		.num_decoded_fmts = ARRAY_SIZE(rkvdec2_h264_decoded_fmts),
++		.decoded_fmts = rkvdec2_h264_decoded_fmts,
++		.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
++	},
++};
++
++enum rcb_axis {
++	PIC_WIDTH = 0,
++	PIC_HEIGHT = 1
++};
++
++struct rcb_size_info {
++	u8 multiplier;
++	enum rcb_axis axis;
++};
++
++static struct rcb_size_info rcb_sizes[] = {
++	{6,	PIC_WIDTH},	// intrar
++	{1,	PIC_WIDTH},	// transdr (Is actually 0.4*pic_width)
++	{1,	PIC_HEIGHT},	// transdc (Is actually 0.1*pic_height)
++	{3,	PIC_WIDTH},	// streamdr
++	{6,	PIC_WIDTH},	// interr
++	{3,	PIC_HEIGHT},	// interc
++	{22,	PIC_WIDTH},	// dblkr
++	{6,	PIC_WIDTH},	// saor
++	{11,	PIC_WIDTH},	// fbcr
++	{67,	PIC_HEIGHT},	// filtc col
++};
++
++#define RCB_SIZE(n,w,h) (rcb_sizes[(n)].multiplier * (rcb_sizes[(n)].axis ? (h) : (w)))
++
++static const struct rkvdec2_coded_fmt_desc *
++rkvdec2_find_coded_fmt_desc(u32 fourcc)
++{
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(rkvdec2_coded_fmts); i++) {
++		if (rkvdec2_coded_fmts[i].fourcc == fourcc)
++			return &rkvdec2_coded_fmts[i];
++	}
++
++	return NULL;
++}
++
++static void rkvdec2_reset_fmt(struct rkvdec2_ctx *ctx, struct v4l2_format *f,
++			      u32 fourcc)
++{
++	memset(f, 0, sizeof(*f));
++	f->fmt.pix_mp.pixelformat = fourcc;
++	f->fmt.pix_mp.field = V4L2_FIELD_NONE;
++	f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709;
++	f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++	f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
++	f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT;
++}
++
++static void rkvdec2_reset_coded_fmt(struct rkvdec2_ctx *ctx)
++{
++	struct v4l2_format *f = &ctx->coded_fmt;
++
++	ctx->coded_fmt_desc = &rkvdec2_coded_fmts[0];
++	rkvdec2_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc);
++
++	f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
++	f->fmt.pix_mp.width = ctx->coded_fmt_desc->frmsize.min_width;
++	f->fmt.pix_mp.height = ctx->coded_fmt_desc->frmsize.min_height;
++
++	if (ctx->coded_fmt_desc->ops->adjust_fmt)
++		ctx->coded_fmt_desc->ops->adjust_fmt(ctx, f);
++}
++
++static void rkvdec2_reset_decoded_fmt(struct rkvdec2_ctx *ctx)
++{
++	struct v4l2_format *f = &ctx->decoded_fmt;
++
++	rkvdec2_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
++	f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
++	v4l2_fill_pixfmt_mp(&f->fmt.pix_mp,
++			    ctx->coded_fmt_desc->decoded_fmts[0],
++			    ctx->coded_fmt.fmt.pix_mp.width,
++			    ctx->coded_fmt.fmt.pix_mp.height);
++
++	ctx->colmv_offset = f->fmt.pix_mp.plane_fmt[0].sizeimage;
++
++	f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 *
++		DIV_ROUND_UP(f->fmt.pix_mp.width, 16) *
++		DIV_ROUND_UP(f->fmt.pix_mp.height, 16);
++}
++
++static int rkvdec2_enum_framesizes(struct file *file, void *priv,
++				   struct v4l2_frmsizeenum *fsize)
++{
++	const struct rkvdec2_coded_fmt_desc *desc;
++
++	if (fsize->index != 0)
++		return -EINVAL;
++
++	desc = rkvdec2_find_coded_fmt_desc(fsize->pixel_format);
++	if (!desc)
++		return -EINVAL;
++
++	fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
++	
++	fsize->stepwise.min_height = 1;
++	fsize->stepwise.min_width = 1;
++	fsize->stepwise.step_height = 1;
++	fsize->stepwise.step_width = 1;
++	fsize->stepwise.max_height = desc->frmsize.max_height;
++	fsize->stepwise.max_width = desc->frmsize.max_width;
++	
++	return 0;
++}
++
++static int rkvdec2_querycap(struct file *file, void *priv,
++			    struct v4l2_capability *cap)
++{
++	struct rkvdec2_dev *rkvdec = video_drvdata(file);
++	struct video_device *vdev = video_devdata(file);
++
++	strscpy(cap->driver, rkvdec->dev->driver->name,
++		sizeof(cap->driver));
++	strscpy(cap->card, vdev->name, sizeof(cap->card));
++	snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
++		 rkvdec->dev->driver->name);
++	return 0;
++}
++
++static int rkvdec2_try_capture_fmt(struct file *file, void *priv,
++				   struct v4l2_format *f)
++{
++	struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
++	struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv);
++	const struct rkvdec2_coded_fmt_desc *coded_desc;
++	unsigned int i;
++
++	/*
++	 * The codec context should point to a coded format desc, if the format
++	 * on the coded end has not been set yet, it should point to the
++	 * default value.
++	 */
++	coded_desc = ctx->coded_fmt_desc;
++	if (WARN_ON(!coded_desc))
++		return -EINVAL;
++
++	for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
++		if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
++			break;
++	}
++
++	if (i == coded_desc->num_decoded_fmts)
++		pix_mp->pixelformat = coded_desc->decoded_fmts[0];
++
++	/* Always apply the frmsize constraint of the coded end. */
++	pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
++	pix_mp->height = max(pix_mp->height, ctx->coded_fmt.fmt.pix_mp.height);
++	v4l2_apply_frmsize_constraints(&pix_mp->width,
++				       &pix_mp->height,
++				       &coded_desc->frmsize);
++
++	v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
++			    pix_mp->width, pix_mp->height);
++
++	pix_mp->plane_fmt[0].sizeimage +=
++		128 *
++		DIV_ROUND_UP(pix_mp->width, 16) *
++		DIV_ROUND_UP(pix_mp->height, 16);
++
++	pix_mp->field = V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++static int rkvdec2_try_output_fmt(struct file *file, void *priv,
++				  struct v4l2_format *f)
++{
++	struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
++	struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv);
++	const struct rkvdec2_coded_fmt_desc *desc;
++
++	desc = rkvdec2_find_coded_fmt_desc(pix_mp->pixelformat);
++	if (!desc) {
++		pix_mp->pixelformat = rkvdec2_coded_fmts[0].fourcc;
++		desc = &rkvdec2_coded_fmts[0];
++	}
++
++	v4l2_apply_frmsize_constraints(&pix_mp->width,
++				       &pix_mp->height,
++				       &desc->frmsize);
++
++	pix_mp->field = V4L2_FIELD_NONE;
++	/* All coded formats are considered single planar for now. */
++	pix_mp->num_planes = 1;
++
++	if (desc->ops->adjust_fmt) {
++		int ret;
++
++		ret = desc->ops->adjust_fmt(ctx, f);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int rkvdec2_s_capture_fmt(struct file *file, void *priv,
++				 struct v4l2_format *f)
++{
++	struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv);
++	struct vb2_queue *vq;
++	int ret;
++
++	/* Change not allowed if queue is busy */
++	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
++			     V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
++	if (vb2_is_busy(vq))
++		return -EBUSY;
++
++	ret = rkvdec2_try_capture_fmt(file, priv, f);
++	if (ret)
++		return ret;
++
++	ctx->decoded_fmt = *f;
++	return 0;
++}
++
++static int rkvdec2_s_output_fmt(struct file *file, void *priv,
++				struct v4l2_format *f)
++{
++	struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv);
++	struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
++	const struct rkvdec2_coded_fmt_desc *desc;
++	struct v4l2_format *cap_fmt;
++	struct vb2_queue *peer_vq, *vq;
++	int ret;
++
++	/*
++	 * In order to support dynamic resolution change, the decoder admits
++	 * a resolution change, as long as the pixelformat remains. Can't be
++	 * done if streaming.
++	 */
++	vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
++	if (vb2_is_streaming(vq) ||
++	    (vb2_is_busy(vq) &&
++	     f->fmt.pix_mp.pixelformat != ctx->coded_fmt.fmt.pix_mp.pixelformat))
++		return -EBUSY;
++
++	/*
++	 * Since format change on the OUTPUT queue will reset the CAPTURE
++	 * queue, we can't allow doing so when the CAPTURE queue has buffers
++	 * allocated.
++	 */
++	peer_vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
++	if (vb2_is_busy(peer_vq))
++		return -EBUSY;
++
++	ret = rkvdec2_try_output_fmt(file, priv, f);
++	if (ret)
++		return ret;
++
++	desc = rkvdec2_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat);
++	if (!desc)
++		return -EINVAL;
++	ctx->coded_fmt_desc = desc;
++	ctx->coded_fmt = *f;
++
++	/*
++	 * Current decoded format might have become invalid with newly
++	 * selected codec, so reset it to default just to be safe and
++	 * keep internal driver state sane. User is mandated to set
++	 * the decoded format again after we return, so we don't need
++	 * anything smarter.
++	 *
++	 * Note that this will propagate any size changes to the decoded format.
++	 */
++	rkvdec2_reset_decoded_fmt(ctx);
++
++	/* Propagate colorspace information to capture. */
++	cap_fmt = &ctx->decoded_fmt;
++	cap_fmt->fmt.pix_mp.colorspace = f->fmt.pix_mp.colorspace;
++	cap_fmt->fmt.pix_mp.xfer_func = f->fmt.pix_mp.xfer_func;
++	cap_fmt->fmt.pix_mp.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;
++	cap_fmt->fmt.pix_mp.quantization = f->fmt.pix_mp.quantization;
++
++	/* Enable format specific queue features */
++	vq->subsystem_flags |= desc->subsystem_flags;
++
++	return 0;
++}
++
++static int rkvdec2_g_output_fmt(struct file *file, void *priv,
++				struct v4l2_format *f)
++{
++	struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv);
++
++	*f = ctx->coded_fmt;
++	return 0;
++}
++
++static int rkvdec2_g_capture_fmt(struct file *file, void *priv,
++				 struct v4l2_format *f)
++{
++	struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv);
++
++	*f = ctx->decoded_fmt;
++	return 0;
++}
++
++static int rkvdec2_enum_output_fmt(struct file *file, void *priv,
++				   struct v4l2_fmtdesc *f)
++{
++	if (f->index >= ARRAY_SIZE(rkvdec2_coded_fmts))
++		return -EINVAL;
++
++	f->pixelformat = rkvdec2_coded_fmts[f->index].fourcc;
++	return 0;
++}
++
++static int rkvdec2_enum_capture_fmt(struct file *file, void *priv,
++				    struct v4l2_fmtdesc *f)
++{
++	struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv);
++
++	if (WARN_ON(!ctx->coded_fmt_desc))
++		return -EINVAL;
++
++	if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
++		return -EINVAL;
++
++	f->pixelformat = ctx->coded_fmt_desc->decoded_fmts[f->index];
++	return 0;
++}
++
++static const struct v4l2_ioctl_ops rkvdec2_ioctl_ops = {
++	.vidioc_querycap = rkvdec2_querycap,
++	.vidioc_enum_framesizes = rkvdec2_enum_framesizes,
++
++	.vidioc_try_fmt_vid_cap_mplane = rkvdec2_try_capture_fmt,
++	.vidioc_try_fmt_vid_out_mplane = rkvdec2_try_output_fmt,
++	.vidioc_s_fmt_vid_out_mplane = rkvdec2_s_output_fmt,
++	.vidioc_s_fmt_vid_cap_mplane = rkvdec2_s_capture_fmt,
++	.vidioc_g_fmt_vid_out_mplane = rkvdec2_g_output_fmt,
++	.vidioc_g_fmt_vid_cap_mplane = rkvdec2_g_capture_fmt,
++	.vidioc_enum_fmt_vid_out = rkvdec2_enum_output_fmt,
++	.vidioc_enum_fmt_vid_cap = rkvdec2_enum_capture_fmt,
++
++	.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
++	.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
++	.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
++	.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
++	.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
++	.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
++	.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
++
++	.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
++	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
++
++	.vidioc_streamon = v4l2_m2m_ioctl_streamon,
++	.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
++
++	.vidioc_decoder_cmd = v4l2_m2m_ioctl_stateless_decoder_cmd,
++	.vidioc_try_decoder_cmd = v4l2_m2m_ioctl_stateless_try_decoder_cmd,
++};
++
++static int rkvdec2_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
++			       unsigned int *num_planes, unsigned int sizes[],
++			      struct device *alloc_devs[])
++{
++	struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vq);
++	struct v4l2_format *f;
++	unsigned int i;
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type))
++		f = &ctx->coded_fmt;
++	else
++		f = &ctx->decoded_fmt;
++
++	if (*num_planes) {
++		if (*num_planes != f->fmt.pix_mp.num_planes)
++			return -EINVAL;
++
++		for (i = 0; i < f->fmt.pix_mp.num_planes; i++) {
++			if (sizes[i] < f->fmt.pix_mp.plane_fmt[i].sizeimage)
++				return -EINVAL;
++		}
++	} else {
++		*num_planes = f->fmt.pix_mp.num_planes;
++		for (i = 0; i < f->fmt.pix_mp.num_planes; i++)
++			sizes[i] = f->fmt.pix_mp.plane_fmt[i].sizeimage;
++	}
++
++	return 0;
++}
++
++static int rkvdec2_buf_prepare(struct vb2_buffer *vb)
++{
++	struct vb2_queue *vq = vb->vb2_queue;
++	struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vq);
++	struct v4l2_format *f;
++	unsigned int i;
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type))
++		f = &ctx->coded_fmt;
++	else
++		f = &ctx->decoded_fmt;
++
++	for (i = 0; i < f->fmt.pix_mp.num_planes; ++i) {
++		u32 sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage;
++
++		if (vb2_plane_size(vb, i) < sizeimage)
++			return -EINVAL;
++	}
++
++	/*
++	 * Buffer's bytesused must be written by driver for CAPTURE buffers.
++	 * (for OUTPUT buffers, if userspace passes 0 bytesused, v4l2-core sets
++	 * it to buffer length).
++	 */
++	if (V4L2_TYPE_IS_CAPTURE(vq->type))
++		vb2_set_plane_payload(vb, 0, f->fmt.pix_mp.plane_fmt[0].sizeimage);
++
++	return 0;
++}
++
++static void rkvdec2_buf_queue(struct vb2_buffer *vb)
++{
++	struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
++
++	v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
++}
++
++static int rkvdec2_buf_out_validate(struct vb2_buffer *vb)
++{
++	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
++
++	vbuf->field = V4L2_FIELD_NONE;
++	return 0;
++}
++
++static void rkvdec2_buf_request_complete(struct vb2_buffer *vb)
++{
++	struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++
++	v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->ctrl_hdl);
++}
++
++static void rkvdec2_free_rcb(struct rkvdec2_ctx *ctx)
++{
++	u32 width, height;
++	int i;
++
++	width = ctx->decoded_fmt.fmt.pix_mp.width;
++	height = ctx->decoded_fmt.fmt.pix_mp.height;
++
++	for (i = 0; i < RKVDEC2_RCB_COUNT; i++) {
++		size_t rcb_size = RCB_SIZE(i, width, height);
++
++		if (!ctx->rcb_bufs[i].cpu)
++			continue;
++
++		switch (ctx->rcb_bufs[i].type) {
++		case RKVDEC2_ALLOC_SRAM:
++			gen_pool_free(ctx->dev->sram_pool,
++				      (unsigned long)ctx->rcb_bufs[i].cpu,
++				      rcb_size);
++			break;
++		case RKVDEC2_ALLOC_DMA:
++			dma_free_coherent(ctx->dev->dev,
++					  rcb_size,
++					  ctx->rcb_bufs[i].cpu,
++					  ctx->rcb_bufs[i].dma);
++			break;
++		}
++	}
++}
++
++static int rkvdec2_allocate_rcb(struct rkvdec2_ctx *ctx)
++{
++	int ret, i;
++	u32 width, height;
++
++	memset(ctx->rcb_bufs, 0, sizeof(*ctx->rcb_bufs));
++
++	width = ctx->decoded_fmt.fmt.pix_mp.width;
++	height = ctx->decoded_fmt.fmt.pix_mp.height;
++
++	for (i = 0; i < RKVDEC2_RCB_COUNT; i++) {
++		void *cpu = NULL;
++		dma_addr_t dma;
++		size_t rcb_size = RCB_SIZE(i, width, height);
++		enum rkvdec2_alloc_type alloc_type = RKVDEC2_ALLOC_SRAM;
++
++		if (ctx->dev->sram_pool) {
++			cpu = gen_pool_dma_zalloc_align(ctx->dev->sram_pool,
++							rcb_size,
++							&dma,
++							64);
++		}
++
++		/* Fallback to RAM */
++		if (!cpu) {
++			cpu = dma_alloc_coherent(ctx->dev->dev,
++						 rcb_size,
++						 &dma,
++						 GFP_KERNEL);
++			alloc_type = RKVDEC2_ALLOC_DMA;
++		}
++
++		if (!cpu) {
++			ret = -ENOMEM;
++			goto err_alloc;
++		}
++
++		ctx->rcb_bufs[i].cpu = cpu;
++		ctx->rcb_bufs[i].dma = dma;
++		ctx->rcb_bufs[i].size = rcb_size;
++		ctx->rcb_bufs[i].type = alloc_type;
++	}
++
++	return 0;
++
++err_alloc:
++	rkvdec2_free_rcb(ctx);
++
++	return ret;
++}
++
++static int rkvdec2_start_streaming(struct vb2_queue *q, unsigned int count)
++{
++	struct rkvdec2_ctx *ctx = vb2_get_drv_priv(q);
++	const struct rkvdec2_coded_fmt_desc *desc;
++	int ret;
++
++	if (V4L2_TYPE_IS_CAPTURE(q->type))
++		return 0;
++
++	desc = ctx->coded_fmt_desc;
++	if (WARN_ON(!desc))
++		return -EINVAL;
++
++	ret = rkvdec2_allocate_rcb(ctx);
++	if (ret)
++		return ret;
++
++	if (desc->ops->start) {
++		ret = desc->ops->start(ctx);
++		if (ret)
++			goto err_ops_start;
++	}
++
++	return 0;
++
++err_ops_start:
++	rkvdec2_free_rcb(ctx);
++
++	return ret;
++}
++
++static void rkvdec2_queue_cleanup(struct vb2_queue *vq, u32 state)
++{
++	struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vq);
++
++	while (true) {
++		struct vb2_v4l2_buffer *vbuf;
++
++		if (V4L2_TYPE_IS_OUTPUT(vq->type))
++			vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
++		else
++			vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
++
++		if (!vbuf)
++			break;
++
++		v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req,
++					   &ctx->ctrl_hdl);
++		v4l2_m2m_buf_done(vbuf, state);
++	}
++}
++
++static void rkvdec2_stop_streaming(struct vb2_queue *q)
++{
++	struct rkvdec2_ctx *ctx = vb2_get_drv_priv(q);
++
++	if (V4L2_TYPE_IS_OUTPUT(q->type)) {
++		const struct rkvdec2_coded_fmt_desc *desc = ctx->coded_fmt_desc;
++
++		if (WARN_ON(!desc))
++			return;
++
++		if (desc->ops->stop)
++			desc->ops->stop(ctx);
++
++		rkvdec2_free_rcb(ctx);
++	}
++
++	rkvdec2_queue_cleanup(q, VB2_BUF_STATE_ERROR);
++}
++
++static const struct vb2_ops rkvdec2_queue_ops = {
++	.queue_setup = rkvdec2_queue_setup,
++	.buf_prepare = rkvdec2_buf_prepare,
++	.buf_queue = rkvdec2_buf_queue,
++	.buf_out_validate = rkvdec2_buf_out_validate,
++	.buf_request_complete = rkvdec2_buf_request_complete,
++	.start_streaming = rkvdec2_start_streaming,
++	.stop_streaming = rkvdec2_stop_streaming,
++	.wait_prepare = vb2_ops_wait_prepare,
++	.wait_finish = vb2_ops_wait_finish,
++};
++
++static int rkvdec2_request_validate(struct media_request *req)
++{
++	unsigned int count;
++
++	count = vb2_request_buffer_cnt(req);
++	if (!count)
++		return -ENOENT;
++	else if (count > 1)
++		return -EINVAL;
++
++	return vb2_request_validate(req);
++}
++
++static const struct media_device_ops rkvdec2_media_ops = {
++	.req_validate = rkvdec2_request_validate,
++	.req_queue = v4l2_m2m_request_queue,
++};
++
++static void rkvdec2_job_finish_no_pm(struct rkvdec2_ctx *ctx,
++				     enum vb2_buffer_state result)
++{
++	if (ctx->coded_fmt_desc->ops->done) {
++		struct vb2_v4l2_buffer *src_buf, *dst_buf;
++
++		src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
++		dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
++		ctx->coded_fmt_desc->ops->done(ctx, src_buf, dst_buf, result);
++	}
++
++	v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
++					 result);
++}
++
++static void rkvdec2_job_finish(struct rkvdec2_ctx *ctx,
++			       enum vb2_buffer_state result)
++{
++	struct rkvdec2_dev *rkvdec = ctx->dev;
++
++	pm_runtime_mark_last_busy(rkvdec->dev);
++	pm_runtime_put_autosuspend(rkvdec->dev);
++	rkvdec2_job_finish_no_pm(ctx, result);
++}
++
++void rkvdec2_run_preamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run)
++{
++	struct media_request *src_req;
++
++	memset(run, 0, sizeof(*run));
++
++	run->bufs.src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
++	run->bufs.dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
++
++	/* Apply request(s) controls if needed. */
++	src_req = run->bufs.src->vb2_buf.req_obj.req;
++	if (src_req)
++		v4l2_ctrl_request_setup(src_req, &ctx->ctrl_hdl);
++
++	v4l2_m2m_buf_copy_metadata(run->bufs.src, run->bufs.dst, true);
++}
++
++void rkvdec2_run_postamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run)
++{
++	struct media_request *src_req = run->bufs.src->vb2_buf.req_obj.req;
++
++	if (src_req)
++		v4l2_ctrl_request_complete(src_req, &ctx->ctrl_hdl);
++}
++
++static void rkvdec2_device_run(void *priv)
++{
++	struct rkvdec2_ctx *ctx = priv;
++	struct rkvdec2_dev *rkvdec = ctx->dev;
++	const struct rkvdec2_coded_fmt_desc *desc = ctx->coded_fmt_desc;
++	int ret;
++
++	if (WARN_ON(!desc))
++		return;
++
++	ret = pm_runtime_resume_and_get(rkvdec->dev);
++	if (ret < 0) {
++		rkvdec2_job_finish_no_pm(ctx, VB2_BUF_STATE_ERROR);
++		return;
++	}
++
++	ret = desc->ops->run(ctx);
++	if (ret)
++		rkvdec2_job_finish(ctx, VB2_BUF_STATE_ERROR);
++}
++
++static const struct v4l2_m2m_ops rkvdec2_m2m_ops = {
++	.device_run = rkvdec2_device_run,
++};
++
++static int rkvdec2_queue_init(void *priv,
++			      struct vb2_queue *src_vq,
++			      struct vb2_queue *dst_vq)
++{
++	struct rkvdec2_ctx *ctx = priv;
++	struct rkvdec2_dev *rkvdec = ctx->dev;
++	int ret;
++
++	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
++	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
++	src_vq->drv_priv = ctx;
++	src_vq->ops = &rkvdec2_queue_ops;
++	src_vq->mem_ops = &vb2_dma_contig_memops;
++
++	/*
++	 * No CPU access on the queues, so no kernel mapping needed.
++	 */
++	src_vq->dma_attrs = DMA_ATTR_NO_KERNEL_MAPPING;
++	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	src_vq->lock = &rkvdec->vdev_lock;
++	src_vq->dev = rkvdec->v4l2_dev.dev;
++	src_vq->supports_requests = true;
++	src_vq->requires_requests = true;
++
++	ret = vb2_queue_init(src_vq);
++	if (ret)
++		return ret;
++
++	dst_vq->bidirectional = true;
++	dst_vq->mem_ops = &vb2_dma_contig_memops;
++	dst_vq->dma_attrs = DMA_ATTR_NO_KERNEL_MAPPING;
++	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
++	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
++	dst_vq->drv_priv = ctx;
++	dst_vq->ops = &rkvdec2_queue_ops;
++	dst_vq->buf_struct_size = sizeof(struct rkvdec2_decoded_buffer);
++	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	dst_vq->lock = &rkvdec->vdev_lock;
++	dst_vq->dev = rkvdec->v4l2_dev.dev;
++
++	return vb2_queue_init(dst_vq);
++}
++
++static int rkvdec2_add_ctrls(struct rkvdec2_ctx *ctx,
++			     const struct rkvdec2_ctrls *ctrls)
++{
++	unsigned int i;
++
++	for (i = 0; i < ctrls->num_ctrls; i++) {
++		const struct v4l2_ctrl_config *cfg = &ctrls->ctrls[i].cfg;
++
++		v4l2_ctrl_new_custom(&ctx->ctrl_hdl, cfg, ctx);
++		if (ctx->ctrl_hdl.error)
++			return ctx->ctrl_hdl.error;
++	}
++
++	return 0;
++}
++
++static int rkvdec2_init_ctrls(struct rkvdec2_ctx *ctx)
++{
++	unsigned int i, nctrls = 0;
++	int ret;
++
++	for (i = 0; i < ARRAY_SIZE(rkvdec2_coded_fmts); i++)
++		nctrls += rkvdec2_coded_fmts[i].ctrls->num_ctrls;
++
++	v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls);
++
++	for (i = 0; i < ARRAY_SIZE(rkvdec2_coded_fmts); i++) {
++		ret = rkvdec2_add_ctrls(ctx, rkvdec2_coded_fmts[i].ctrls);
++		if (ret)
++			goto err_free_handler;
++	}
++
++	ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
++	if (ret)
++		goto err_free_handler;
++
++	ctx->fh.ctrl_handler = &ctx->ctrl_hdl;
++	return 0;
++
++err_free_handler:
++	v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
++	return ret;
++}
++
++static int rkvdec2_open(struct file *filp)
++{
++	struct rkvdec2_dev *rkvdec = video_drvdata(filp);
++	struct rkvdec2_ctx *ctx;
++	int ret;
++
++	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
++	if (!ctx)
++		return -ENOMEM;
++
++	ctx->dev = rkvdec;
++	rkvdec2_reset_coded_fmt(ctx);
++	rkvdec2_reset_decoded_fmt(ctx);
++	v4l2_fh_init(&ctx->fh, video_devdata(filp));
++
++	ret = rkvdec2_init_ctrls(ctx);
++	if (ret)
++		goto err_free_ctx;
++
++	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rkvdec->m2m_dev, ctx,
++					    rkvdec2_queue_init);
++	if (IS_ERR(ctx->fh.m2m_ctx)) {
++		ret = PTR_ERR(ctx->fh.m2m_ctx);
++		goto err_cleanup_ctrls;
++	}
++
++	filp->private_data = &ctx->fh;
++	v4l2_fh_add(&ctx->fh);
++
++	return 0;
++
++err_cleanup_ctrls:
++	v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
++
++err_free_ctx:
++	kfree(ctx);
++	return ret;
++}
++
++static int rkvdec2_release(struct file *filp)
++{
++	struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(filp->private_data);
++
++	v4l2_fh_del(&ctx->fh);
++	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
++	v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
++	v4l2_fh_exit(&ctx->fh);
++	kfree(ctx);
++
++	return 0;
++}
++
++static const struct v4l2_file_operations rkvdec2_fops = {
++	.owner = THIS_MODULE,
++	.open = rkvdec2_open,
++	.release = rkvdec2_release,
++	.poll = v4l2_m2m_fop_poll,
++	.unlocked_ioctl = video_ioctl2,
++	.mmap = v4l2_m2m_fop_mmap,
++};
++
++static int rkvdec2_v4l2_init(struct rkvdec2_dev *rkvdec)
++{
++	int ret;
++
++	ret = v4l2_device_register(rkvdec->dev, &rkvdec->v4l2_dev);
++	if (ret) {
++		dev_err(rkvdec->dev, "Failed to register V4L2 device\n");
++		return ret;
++	}
++
++	rkvdec->m2m_dev = v4l2_m2m_init(&rkvdec2_m2m_ops);
++	if (IS_ERR(rkvdec->m2m_dev)) {
++		v4l2_err(&rkvdec->v4l2_dev, "Failed to init mem2mem device\n");
++		ret = PTR_ERR(rkvdec->m2m_dev);
++		goto err_unregister_v4l2;
++	}
++
++	rkvdec->mdev.dev = rkvdec->dev;
++	strscpy(rkvdec->mdev.model, "rkvdec2", sizeof(rkvdec->mdev.model));
++	strscpy(rkvdec->mdev.bus_info, "platform:rkvdec2",
++		sizeof(rkvdec->mdev.bus_info));
++	media_device_init(&rkvdec->mdev);
++	rkvdec->mdev.ops = &rkvdec2_media_ops;
++	rkvdec->v4l2_dev.mdev = &rkvdec->mdev;
++
++	rkvdec->vdev.lock = &rkvdec->vdev_lock;
++	rkvdec->vdev.v4l2_dev = &rkvdec->v4l2_dev;
++	rkvdec->vdev.fops = &rkvdec2_fops;
++	rkvdec->vdev.release = video_device_release_empty;
++	rkvdec->vdev.vfl_dir = VFL_DIR_M2M;
++	rkvdec->vdev.device_caps = V4L2_CAP_STREAMING |
++				   V4L2_CAP_VIDEO_M2M_MPLANE;
++	rkvdec->vdev.ioctl_ops = &rkvdec2_ioctl_ops;
++	video_set_drvdata(&rkvdec->vdev, rkvdec);
++	strscpy(rkvdec->vdev.name, "rkvdec2", sizeof(rkvdec->vdev.name));
++
++	ret = video_register_device(&rkvdec->vdev, VFL_TYPE_VIDEO, -1);
++	if (ret) {
++		v4l2_err(&rkvdec->v4l2_dev, "Failed to register video device\n");
++		goto err_cleanup_mc;
++	}
++
++	ret = v4l2_m2m_register_media_controller(rkvdec->m2m_dev, &rkvdec->vdev,
++						 MEDIA_ENT_F_PROC_VIDEO_DECODER);
++	if (ret) {
++		v4l2_err(&rkvdec->v4l2_dev,
++			 "Failed to initialize V4L2 M2M media controller\n");
++		goto err_unregister_vdev;
++	}
++
++	ret = media_device_register(&rkvdec->mdev);
++	if (ret) {
++		v4l2_err(&rkvdec->v4l2_dev, "Failed to register media device\n");
++		goto err_unregister_mc;
++	}
++
++	return 0;
++
++err_unregister_mc:
++	v4l2_m2m_unregister_media_controller(rkvdec->m2m_dev);
++
++err_unregister_vdev:
++	video_unregister_device(&rkvdec->vdev);
++
++err_cleanup_mc:
++	media_device_cleanup(&rkvdec->mdev);
++	v4l2_m2m_release(rkvdec->m2m_dev);
++
++err_unregister_v4l2:
++	v4l2_device_unregister(&rkvdec->v4l2_dev);
++	return ret;
++}
++
++static void rkvdec2_v4l2_cleanup(struct rkvdec2_dev *rkvdec)
++{
++	media_device_unregister(&rkvdec->mdev);
++	v4l2_m2m_unregister_media_controller(rkvdec->m2m_dev);
++	video_unregister_device(&rkvdec->vdev);
++	media_device_cleanup(&rkvdec->mdev);
++	v4l2_m2m_release(rkvdec->m2m_dev);
++	v4l2_device_unregister(&rkvdec->v4l2_dev);
++}
++
++static irqreturn_t rkvdec2_irq_handler(int irq, void *priv)
++{
++	struct rkvdec2_dev *rkvdec = priv;
++	enum vb2_buffer_state state;
++	u32 status;
++
++	status = readl(rkvdec->regs + RKVDEC2_REG_STA_INT);
++	state = (status & STA_INT_DEC_RDY_STA) ?
++		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
++
++	/* Clear interrupt status */
++	writel(0, rkvdec->regs + RKVDEC2_REG_STA_INT);
++	if (cancel_delayed_work(&rkvdec->watchdog_work)) {
++		struct rkvdec2_ctx *ctx;
++
++		ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
++		rkvdec2_job_finish(ctx, state);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static void rkvdec2_watchdog_func(struct work_struct *work)
++{
++	struct rkvdec2_dev *rkvdec = container_of(to_delayed_work(work), struct rkvdec2_dev,
++			      watchdog_work);
++	struct rkvdec2_ctx *ctx;
++
++	ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
++	if (ctx) {
++		dev_err(rkvdec->dev, "Frame processing timed out!\n");
++		writel(RKVDEC2_REG_DEC_IRQ_DISABLE, rkvdec->regs + RKVDEC2_REG_IMPORTANT_EN);
++		writel(0, rkvdec->regs + RKVDEC2_REG_DEC_E);
++		rkvdec2_job_finish(ctx, VB2_BUF_STATE_ERROR);
++	}
++}
++
++static const struct of_device_id of_rkvdec2_match[] = {
++	{ .compatible = "rockchip,rk3588-vdec" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_rkvdec2_match);
++
++static const char * const rkvdec2_clk_names[] = {
++	"axi",
++	"ahb",
++	"core",
++	"cabac",
++	"hevc_cabac",
++};
++
++/*
++ * Some SoCs, like RK3588 have multiple identical vdpu34x cores, but the
++ * kernel is currently missing support for multi-core handling. Exposing
++ * separate devices for each core to userspace is bad, since that does
++ * not allow scheduling tasks properly (and creates ABI). With this workaround
++ * the driver will only probe for the first core and early exit for the other
++ * cores. Once the driver gains multi-core support, the same technique
++ * for detecting the main core can be used to cluster all cores together.
++ */
++static int rkvdec2_disable_multicore(struct rkvdec2_dev *rkvdec)
++{
++	const char *compatible;
++	struct device_node *node;
++	int ret;
++
++	/* Intentionally ignores the fallback strings */
++	ret = of_property_read_string(rkvdec->dev->of_node, "compatible", &compatible);
++	if (ret)
++		return ret;
++
++	/* first compatible node found from the root node is considered the main core */
++	node = of_find_compatible_node(NULL, NULL, compatible);
++	if (!node)
++		return -EINVAL; /* broken DT? */
++
++	if (rkvdec->dev->of_node != node) {
++		dev_info(rkvdec->dev, "missing multi-core support, ignoring this instance\n");
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static int rkvdec2_probe(struct platform_device *pdev)
++{
++	struct rkvdec2_dev *rkvdec;
++	unsigned int i;
++	int ret, irq;
++
++	rkvdec = devm_kzalloc(&pdev->dev, sizeof(*rkvdec), GFP_KERNEL);
++	if (!rkvdec)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, rkvdec);
++	rkvdec->dev = &pdev->dev;
++
++	ret = rkvdec2_disable_multicore(rkvdec);
++	if (ret)
++		return ret;
++
++	mutex_init(&rkvdec->vdev_lock);
++	INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec2_watchdog_func);
++
++	rkvdec->clocks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(rkvdec2_clk_names),
++				      sizeof(*rkvdec->clocks), GFP_KERNEL);
++	if (!rkvdec->clocks)
++		return -ENOMEM;
++
++	for (i = 0; i < ARRAY_SIZE(rkvdec2_clk_names); i++)
++		rkvdec->clocks[i].id = rkvdec2_clk_names[i];
++
++	ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(rkvdec2_clk_names),
++				rkvdec->clocks);
++	if (ret)
++		return ret;
++
++	rkvdec->regs = devm_platform_ioremap_resource_byname(pdev, "function");
++	if (IS_ERR(rkvdec->regs))
++		return PTR_ERR(rkvdec->regs);
++
++	/*
++	 * Without IOMMU support, keep DMA in the lower 32 bits.
++	 */
++	ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++	if (ret) {
++		dev_err(&pdev->dev, "Could not set DMA coherent mask.\n");
++		return ret;
++	}
++
++	vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq <= 0)
++		return -ENXIO;
++
++	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
++					rkvdec2_irq_handler, IRQF_ONESHOT,
++					dev_name(&pdev->dev), rkvdec);
++	if (ret) {
++		dev_err(&pdev->dev, "Could not request vdec2 IRQ\n");
++		return ret;
++	}
++
++	rkvdec->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0);
++	if (!rkvdec->sram_pool)
++		dev_info(&pdev->dev, "No sram node, RCB will be stored in RAM\n");
++
++	pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
++	pm_runtime_use_autosuspend(&pdev->dev);
++	pm_runtime_enable(&pdev->dev);
++
++	ret = rkvdec2_v4l2_init(rkvdec);
++	if (ret)
++		goto err_disable_runtime_pm;
++
++	return 0;
++
++err_disable_runtime_pm:
++	pm_runtime_dont_use_autosuspend(&pdev->dev);
++	pm_runtime_disable(&pdev->dev);
++
++	if (rkvdec->sram_pool)
++		gen_pool_destroy(rkvdec->sram_pool);
++
++	return ret;
++}
++
++static void rkvdec2_remove(struct platform_device *pdev)
++{
++	struct rkvdec2_dev *rkvdec = platform_get_drvdata(pdev);
++
++	cancel_delayed_work_sync(&rkvdec->watchdog_work);
++
++	rkvdec2_v4l2_cleanup(rkvdec);
++	pm_runtime_disable(&pdev->dev);
++	pm_runtime_dont_use_autosuspend(&pdev->dev);
++
++	if (rkvdec->sram_pool)
++		gen_pool_destroy(rkvdec->sram_pool);
++}
++
++#ifdef CONFIG_PM
++static int rkvdec2_runtime_resume(struct device *dev)
++{
++	struct rkvdec2_dev *rkvdec = dev_get_drvdata(dev);
++
++	return clk_bulk_prepare_enable(ARRAY_SIZE(rkvdec2_clk_names),
++				       rkvdec->clocks);
++}
++
++static int rkvdec2_runtime_suspend(struct device *dev)
++{
++	struct rkvdec2_dev *rkvdec = dev_get_drvdata(dev);
++
++	clk_bulk_disable_unprepare(ARRAY_SIZE(rkvdec2_clk_names),
++				   rkvdec->clocks);
++	return 0;
++}
++#endif
++
++static const struct dev_pm_ops rkvdec2_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
++	SET_RUNTIME_PM_OPS(rkvdec2_runtime_suspend, rkvdec2_runtime_resume, NULL)
++};
++
++static struct platform_driver rkvdec2_driver = {
++	.probe = rkvdec2_probe,
++	.remove_new = rkvdec2_remove,
++	.driver = {
++		   .name = "rkvdec2",
++		   .of_match_table = of_rkvdec2_match,
++		   .pm = &rkvdec2_pm_ops,
++	},
++};
++module_platform_driver(rkvdec2_driver);
++
++MODULE_AUTHOR("Detlev Casanova <detlev.casanova@collabora.com>");
++MODULE_DESCRIPTION("Rockchip Video Decoder 2 driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/media/platform/rockchip/rkvdec2/rkvdec2.h b/drivers/media/platform/rockchip/rkvdec2/rkvdec2.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/rockchip/rkvdec2/rkvdec2.h
+@@ -0,0 +1,130 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Rockchip Video Decoder 2 driver
++ *
++ * Copyright (C) 2024 Collabora, Ltd.
++ *  Detlev Casanova <detlev.casanova@collabora.com>
++ *
++ * Based on rkvdec driver by Boris Brezillon <boris.brezillon@collabora.com>
++ */
++#ifndef RKVDEC_H_
++#define RKVDEC_H_
++
++#include <linux/platform_device.h>
++#include <linux/videodev2.h>
++#include <linux/wait.h>
++#include <linux/clk.h>
++#include <linux/dma-mapping.h>
++
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++#include <media/videobuf2-core.h>
++#include <media/videobuf2-dma-contig.h>
++
++#include "rkvdec2-regs.h"
++
++#define RKVDEC2_RCB_COUNT	10
++
++struct rkvdec2_ctx;
++
++enum rkvdec2_alloc_type {
++	RKVDEC2_ALLOC_SRAM,
++	RKVDEC2_ALLOC_DMA,
++};
++
++struct rkvdec2_aux_buf {
++	void *cpu;
++	dma_addr_t dma;
++	size_t size;
++	enum rkvdec2_alloc_type type;
++};
++
++struct rkvdec2_ctrl_desc {
++	struct v4l2_ctrl_config cfg;
++};
++
++struct rkvdec2_ctrls {
++	const struct rkvdec2_ctrl_desc *ctrls;
++	unsigned int num_ctrls;
++};
++
++struct rkvdec2_run {
++	struct {
++		struct vb2_v4l2_buffer *src;
++		struct vb2_v4l2_buffer *dst;
++	} bufs;
++};
++
++struct rkvdec2_decoded_buffer {
++	/* Must be the first field in this struct. */
++	struct v4l2_m2m_buffer base;
++};
++
++static inline struct rkvdec2_decoded_buffer *
++vb2_to_rkvdec2_decoded_buf(struct vb2_buffer *buf)
++{
++	return container_of(buf, struct rkvdec2_decoded_buffer,
++			    base.vb.vb2_buf);
++}
++
++struct rkvdec2_coded_fmt_ops {
++	int (*adjust_fmt)(struct rkvdec2_ctx *ctx,
++			  struct v4l2_format *f);
++	int (*start)(struct rkvdec2_ctx *ctx);
++	void (*stop)(struct rkvdec2_ctx *ctx);
++	int (*run)(struct rkvdec2_ctx *ctx);
++	void (*done)(struct rkvdec2_ctx *ctx, struct vb2_v4l2_buffer *src_buf,
++		     struct vb2_v4l2_buffer *dst_buf,
++		     enum vb2_buffer_state result);
++	int (*try_ctrl)(struct rkvdec2_ctx *ctx, struct v4l2_ctrl *ctrl);
++};
++
++struct rkvdec2_coded_fmt_desc {
++	u32 fourcc;
++	struct v4l2_frmsize_stepwise frmsize;
++	const struct rkvdec2_ctrls *ctrls;
++	const struct rkvdec2_coded_fmt_ops *ops;
++	unsigned int num_decoded_fmts;
++	const u32 *decoded_fmts;
++	u32 subsystem_flags;
++};
++
++struct rkvdec2_dev {
++	struct v4l2_device v4l2_dev;
++	struct media_device mdev;
++	struct video_device vdev;
++	struct v4l2_m2m_dev *m2m_dev;
++	struct device *dev;
++	struct clk_bulk_data *clocks;
++	void __iomem *regs;
++	struct gen_pool *sram_pool;
++	struct mutex vdev_lock; /* serializes ioctls */
++	struct delayed_work watchdog_work;
++};
++
++struct rkvdec2_ctx {
++	struct v4l2_fh fh;
++	struct v4l2_format coded_fmt;
++	struct v4l2_format decoded_fmt;
++	const struct rkvdec2_coded_fmt_desc *coded_fmt_desc;
++	struct v4l2_ctrl_handler ctrl_hdl;
++	struct rkvdec2_dev *dev;
++	struct rkvdec2_aux_buf rcb_bufs[RKVDEC2_RCB_COUNT];
++
++	u32 colmv_offset;
++
++	void *priv;
++};
++
++static inline struct rkvdec2_ctx *fh_to_rkvdec2_ctx(struct v4l2_fh *fh)
++{
++	return container_of(fh, struct rkvdec2_ctx, fh);
++}
++
++void rkvdec2_run_preamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run);
++void rkvdec2_run_postamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run);
++
++extern const struct rkvdec2_coded_fmt_ops rkvdec2_h264_fmt_ops;
++
++#endif /* RKVDEC_H_ */
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Fri, 14 Jun 2024 19:53:40 -0400
+Subject: media: dt-bindings: rockchip: Document RK3588 Video Decoder bindings
+
+Document the Rockchip RK3588 Video Decoder bindings.
+
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+---
+ Documentation/devicetree/bindings/media/rockchip,vdec.yaml | 73 +++++++++-
+ 1 file changed, 72 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
+@@ -17,6 +17,7 @@ properties:
+   compatible:
+     oneOf:
+       - const: rockchip,rk3399-vdec
++      - const: rockchip,rk3588-vdec
+       - items:
+           - enum:
+               - rockchip,rk3228-vdec
+@@ -24,35 +25,72 @@ properties:
+           - const: rockchip,rk3399-vdec
+ 
+   reg:
+-    maxItems: 1
++    minItems: 1
++    items:
++      - description: The link table configuration registers base
++      - description: The function configuration registers base
++      - description: The cache configuration registers base
++
++  reg-names:
++    items:
++      - const: link
++      - const: function
++      - const: cache
+ 
+   interrupts:
+     maxItems: 1
+ 
+   clocks:
++    minItems: 4
+     items:
+       - description: The Video Decoder AXI interface clock
+       - description: The Video Decoder AHB interface clock
+       - description: The Video Decoded CABAC clock
+       - description: The Video Decoder core clock
++      - description: The Video decoder HEVC CABAC clock
+ 
+   clock-names:
++    minItems: 4
+     items:
+       - const: axi
+       - const: ahb
+       - const: cabac
+       - const: core
++      - const: hevc_cabac
+ 
+   assigned-clocks: true
+ 
+   assigned-clock-rates: true
+ 
++  resets:
++    items:
++      - description: The Video Decoder AXI interface reset
++      - description: The Video Decoder AHB interface reset
++      - description: The Video Decoded CABAC reset
++      - description: The Video Decoder core reset
++      - description: The Video decoder HEVC CABAC reset
++
++  reset-names:
++    items:
++      - const: axi
++      - const: ahb
++      - const: cabac
++      - const: core
++      - const: hevc_cabac
++
+   power-domains:
+     maxItems: 1
+ 
+   iommus:
+     maxItems: 1
+ 
++  sram:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description: |
++      phandle to a reserved on-chip SRAM regions.
++      Some SoCs, like rk3588 provide on-chip SRAM to store temporary
++      buffers during decoding.
++
+ required:
+   - compatible
+   - reg
+@@ -61,6 +99,39 @@ required:
+   - clock-names
+   - power-domains
+ 
++allOf:
++  - if:
++      properties:
++        compatible:
++          contains:
++            const: rockchip,rk3588-vdec
++    then:
++      properties:
++        reg:
++          minItems: 3
++        reg-names:
++          minItems: 3
++        clocks:
++          minItems: 5
++        clock-names:
++          minItems: 5
++        resets:
++          minItems: 5
++        reset-names:
++          minItems: 5
++    else:
++      properties:
++        reg:
++          maxItems: 1
++        reg-names: false
++        clocks:
++          maxItems: 4
++        clock-names:
++          maxItems: 4
++        resets: false
++        reset-names: false
++        sram: false
++
+ additionalProperties: false
+ 
+ examples:
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Fri, 14 Jun 2024 19:56:19 -0400
+Subject: arm64: dts: rockchip: Add rkvdec2 Video Decoder on rk3588(s)
+
+Add the rkvdec2 Video Decoder to the RK3588s devicetree.
+
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 48 ++++++++++
+ 1 file changed, 48 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1224,6 +1224,44 @@ vepu121_3_mmu: iommu@fdbac800 {
+ 		#iommu-cells = <0>;
+ 	};
+ 
++	vdec0: video-decoder@fdc38000 {
++		compatible = "rockchip,rk3588-vdec";
++		reg = <0x0 0xfdc38000 0x0 0x100>, <0x0 0xfdc38100 0x0 0x500>, <0x0 0xfdc38600 0x0 0x100>;
++		reg-names = "link", "function", "cache";
++		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
++			 <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
++		clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
++		assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
++				  <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
++		assigned-clock-rates = <800000000>, <600000000>,
++				       <600000000>, <1000000000>;
++		resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>,
++			 <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>;
++		reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
++		power-domains = <&power RK3588_PD_RKVDEC0>;
++		sram = <&vdec0_sram>;
++	};
++
++	vdec1: video-decoder@fdc40000 {
++		compatible = "rockchip,rk3588-vdec";
++		reg = <0x0 0xfdc40000 0x0 0x100>, <0x0 0xfdc40100 0x0 0x500>, <0x0 0xfdc40600 0x0 0x100>;
++		reg-names = "link", "function", "cache";
++		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
++			 <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
++		clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
++		assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
++				  <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
++		assigned-clock-rates = <800000000>, <600000000>,
++				       <600000000>, <1000000000>;
++		resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>,
++			 <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>;
++		reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
++		power-domains = <&power RK3588_PD_RKVDEC1>;
++		sram = <&vdec1_sram>;
++	};
++
+ 	av1d: video-codec@fdc70000 {
+ 		compatible = "rockchip,rk3588-av1-vpu";
+ 		reg = <0x0 0xfdc70000 0x0 0x800>;
+@@ -2848,6 +2886,16 @@ system_sram2: sram@ff001000 {
+ 		ranges = <0x0 0x0 0xff001000 0xef000>;
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
++
++		vdec0_sram: codec-sram@0 {
++			reg = <0x0 0x78000>;
++			pool;
++		};
++
++		vdec1_sram: codec-sram@78000 {
++			reg = <0x78000 0x77000>;
++			pool;
++		};
+ 	};
+ 
+ 	pinctrl: pinctrl {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch
new file mode 100644
index 000000000000..13b5aecefc5b
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch
@@ -0,0 +1,43 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: amazingfate <liujianfeng1994@gmail.com>
+Date: Fri, 21 Jun 2024 16:32:55 +0800
+Subject: media: v4l2-core: Initialize h264 frame_mbs_only_flag as 1
+
+---
+ drivers/media/v4l2-core/v4l2-ctrls-core.c | 13 ++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/v4l2-core/v4l2-ctrls-core.c
++++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c
+@@ -111,6 +111,7 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx,
+ 	struct v4l2_ctrl_vp9_frame *p_vp9_frame;
+ 	struct v4l2_ctrl_fwht_params *p_fwht_params;
+ 	struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix;
++	struct v4l2_ctrl_h264_sps *p_h264_sps;
+ 	struct v4l2_ctrl_av1_sequence *p_av1_sequence;
+ 	void *p = ptr.p + idx * ctrl->elem_size;
+ 
+@@ -179,6 +180,18 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx,
+ 		 */
+ 		memset(p_h264_scaling_matrix, 16, sizeof(*p_h264_scaling_matrix));
+ 		break;
++	case V4L2_CTRL_TYPE_H264_SPS:
++		p_h264_sps = p;
++		/*
++		 * Without V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY,
++		 * frame_mbs_only_flag set to 0 will translate to a miniumum
++		 * height of 32 (see H.264 specification 7-8). Some driver may
++		 * have a minimum size lower then 32, which would fail
++		 * validation with the SPS value. Set this flag, so that there
++		 * is now doubling in the height, allowing a valid default.
++		*/
++		p_h264_sps->flags = V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY;
++		break;
+ 	}
+ }
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0029-arm64-dts-rockchip-rk3588-add-RGA2-node.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0029-arm64-dts-rockchip-rk3588-add-RGA2-node.patch
new file mode 100644
index 000000000000..abb8d1683714
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0029-arm64-dts-rockchip-rk3588-add-RGA2-node.patch
@@ -0,0 +1,34 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Mon, 13 May 2024 20:29:49 +0300
+Subject: arm64: dts: rockchip: rk3588: add VDPU and RGA2 nodes
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 11 ++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -566,6 +566,17 @@ mmu600_php: iommu@fcb00000 {
+ 		status = "disabled";
+ 	};
+ 
++	rga: rga@fdb80000 {
++		compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
++		reg = <0x0 0xfdb80000 0x0 0x1000>;
++		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>;
++		clock-names = "aclk", "hclk", "sclk";
++		resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>;
++		reset-names = "core", "axi", "ahb";
++		power-domains = <&power RK3588_PD_VDPU>;
++	};
++
+ 	pmu1grf: syscon@fd58a000 {
+ 		compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
+ 		reg = <0x0 0xfd58a000 0x0 0x10000>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0113-add-synopsys-designware-hdmi-rx-controller.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0113-add-synopsys-designware-hdmi-rx-controller.patch
new file mode 100644
index 000000000000..7c37c6b79ceb
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0113-add-synopsys-designware-hdmi-rx-controller.patch
@@ -0,0 +1,3967 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Fri, 19 Jul 2024 18:10:30 +0530
+Subject: dt-bindings: media: Document bindings for HDMI RX Controller
+
+Document bindings for the Synopsys DesignWare HDMI RX Controller.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20240719124032.26852-3-shreeya.patel@collabora.com
+Signed-off-by: Sebastian Reichel <sre@kernel.org>
+---
+ Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml | 132 ++++++++++
+ 1 file changed, 132 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml
+@@ -0,0 +1,132 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++# Device Tree bindings for Synopsys DesignWare HDMI RX Controller
++
++---
++$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Synopsys DesignWare HDMI RX Controller
++
++maintainers:
++  - Shreeya Patel <shreeya.patel@collabora.com>
++
++description:
++  Synopsys DesignWare HDMI Input Controller preset on RK3588 SoCs
++  allowing devices to receive and decode high-resolution video streams
++  from external sources like media players, cameras, laptops, etc.
++
++properties:
++  compatible:
++    items:
++      - const: rockchip,rk3588-hdmirx-ctrler
++      - const: snps,dw-hdmi-rx
++
++  reg:
++    maxItems: 1
++
++  interrupts:
++    maxItems: 3
++
++  interrupt-names:
++    items:
++      - const: cec
++      - const: hdmi
++      - const: dma
++
++  clocks:
++    maxItems: 7
++
++  clock-names:
++    items:
++      - const: aclk
++      - const: audio
++      - const: cr_para
++      - const: pclk
++      - const: ref
++      - const: hclk_s_hdmirx
++      - const: hclk_vo1
++
++  power-domains:
++    maxItems: 1
++
++  resets:
++    maxItems: 4
++
++  reset-names:
++    items:
++      - const: axi
++      - const: apb
++      - const: ref
++      - const: biu
++
++  memory-region:
++    maxItems: 1
++
++  hpd-gpios:
++    description: GPIO specifier for HPD.
++    maxItems: 1
++
++  rockchip,grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      The phandle of the syscon node for the general register file
++      containing HDMIRX PHY status bits.
++
++  rockchip,vo1-grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      The phandle of the syscon node for the Video Output GRF register
++      to enable EDID transfer through SDAIN and SCLIN.
++
++required:
++  - compatible
++  - reg
++  - interrupts
++  - interrupt-names
++  - clocks
++  - clock-names
++  - power-domains
++  - resets
++  - pinctrl-0
++  - hpd-gpios
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
++    #include <dt-bindings/gpio/gpio.h>
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/interrupt-controller/irq.h>
++    #include <dt-bindings/power/rk3588-power.h>
++    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
++    hdmi_receiver: hdmi-receiver@fdee0000 {
++      compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
++      reg = <0xfdee0000 0x6000>;
++      interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
++                   <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
++                   <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
++      interrupt-names = "cec", "hdmi", "dma";
++      clocks = <&cru ACLK_HDMIRX>,
++               <&cru CLK_HDMIRX_AUD>,
++               <&cru CLK_CR_PARA>,
++               <&cru PCLK_HDMIRX>,
++               <&cru CLK_HDMIRX_REF>,
++               <&cru PCLK_S_HDMIRX>,
++               <&cru HCLK_VO1>;
++      clock-names = "aclk",
++                    "audio",
++                    "cr_para",
++                    "pclk",
++                    "ref",
++                    "hclk_s_hdmirx",
++                    "hclk_vo1";
++      power-domains = <&power RK3588_PD_VO1>;
++      resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
++               <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
++      reset-names = "axi", "apb", "ref", "biu";
++      memory-region = <&hdmi_receiver_cma>;
++      pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>;
++      pinctrl-names = "default";
++      hpd-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
++    };
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Fri, 19 Jul 2024 18:10:31 +0530
+Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller
+
+Add device tree support for Synopsys DesignWare HDMI RX
+Controller.
+
+Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
+Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Link: https://lore.kernel.org/r/20240719124032.26852-4-shreeya.patel@collabora.com
+Signed-off-by: Sebastian Reichel <sre@kernel.org>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi | 14 +++
+ arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi        | 56 ++++++++++
+ 2 files changed, 70 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
+@@ -594,6 +594,20 @@ hdmim0_tx1_hpd: hdmim0-tx1-hpd {
+ 				/* hdmim0_tx1_hpd */
+ 				<1 RK_PA6 5 &pcfg_pull_none>;
+ 		};
++
++		/omit-if-no-ref/
++		hdmim1_rx: hdmim1-rx {
++			rockchip,pins =
++				/* hdmim1_rx_cec */
++				<3 RK_PD1 5 &pcfg_pull_none>,
++				/* hdmim1_rx_scl */
++				<3 RK_PD2 5 &pcfg_pull_none_smt>,
++				/* hdmim1_rx_sda */
++				<3 RK_PD3 5 &pcfg_pull_none_smt>,
++				/* hdmim1_rx_hpdin */
++				<3 RK_PD4 5 &pcfg_pull_none>;
++		};
++
+ 		/omit-if-no-ref/
+ 		hdmim1_rx_cec: hdmim1-rx-cec {
+ 			rockchip,pins =
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+@@ -7,6 +7,29 @@
+ #include "rk3588-extra-pinctrl.dtsi"
+ 
+ / {
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		/*
++		 * The 4k HDMI capture controller works only with 32bit
++		 * phys addresses and doesn't support IOMMU. HDMI RX CMA
++		 * must be reserved below 4GB.
++		 * The size of 160MB was determined as follows:
++		 * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB
++		 * To ensure sufficient support for practical use-cases,
++		 * we doubled the 66MB value.
++		 */
++		hdmi_receiver_cma: hdmi-receiver-cma {
++			compatible = "shared-dma-pool";
++			alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
++			size = <0x0 (160 * 0x100000)>; /* 160MiB */
++			no-map;
++			status = "disabled";
++		};
++	};
++
+ 	usb_host1_xhci: usb@fc400000 {
+ 		compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ 		reg = <0x0 0xfc400000 0x0 0x400000>;
+@@ -135,6 +158,39 @@ i2s10_8ch: i2s@fde00000 {
+ 		status = "disabled";
+ 	};
+ 
++	hdmi_receiver: hdmi_receiver@fdee0000 {
++		compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
++		reg = <0x0 0xfdee0000 0x0 0x6000>;
++		power-domains = <&power RK3588_PD_VO1>;
++		rockchip,grf = <&sys_grf>;
++		rockchip,vo1-grf = <&vo1_grf>;
++		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "cec", "hdmi", "dma";
++		clocks = <&cru ACLK_HDMIRX>,
++			 <&cru CLK_HDMIRX_AUD>,
++			 <&cru CLK_CR_PARA>,
++			 <&cru PCLK_HDMIRX>,
++			 <&cru CLK_HDMIRX_REF>,
++			 <&cru PCLK_S_HDMIRX>,
++			 <&cru HCLK_VO1>;
++		clock-names = "aclk",
++			      "audio",
++			      "cr_para",
++			      "pclk",
++			      "ref",
++			      "hclk_s_hdmirx",
++			      "hclk_vo1";
++		resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
++			 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
++		reset-names = "axi", "apb", "ref", "biu";
++		memory-region = <&hdmi_receiver_cma>;
++		pinctrl-0 = <&hdmim1_rx>;
++		pinctrl-names = "default";
++		status = "disabled";
++	};
++
+ 	pcie3x4: pcie@fe150000 {
+ 		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ 		#address-cells = <3>;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Fri, 19 Jul 2024 18:10:32 +0530
+Subject: media: platform: synopsys: Add support for hdmi input driver
+
+Add initial support for the Synopsys DesignWare HDMI RX
+Controller Driver used by Rockchip RK3588. The driver
+supports:
+ - HDMI 1.4b and 2.0 modes (HDMI 4k@60Hz)
+ - RGB888, YUV422, YUV444 and YCC420 pixel formats
+ - CEC
+ - EDID configuration
+
+The hardware also has Audio and HDCP capabilities, but these are
+not yet supported by the driver.
+
+Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
+Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Link: https://lore.kernel.org/r/20240719124032.26852-5-shreeya.patel@collabora.com
+Signed-off-by: Sebastian Reichel <sre@kernel.org>
+---
+ drivers/media/platform/Kconfig                           |    1 +
+ drivers/media/platform/Makefile                          |    1 +
+ drivers/media/platform/synopsys/Kconfig                  |    3 +
+ drivers/media/platform/synopsys/Makefile                 |    2 +
+ drivers/media/platform/synopsys/hdmirx/Kconfig           |   27 +
+ drivers/media/platform/synopsys/hdmirx/Makefile          |    4 +
+ drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c     | 2763 ++++++++++
+ drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h     |  394 ++
+ drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c |  285 +
+ drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h |   44 +
+ 10 files changed, 3524 insertions(+)
+
+diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/Kconfig
++++ b/drivers/media/platform/Kconfig
+@@ -85,6 +85,7 @@ source "drivers/media/platform/rockchip/Kconfig"
+ source "drivers/media/platform/samsung/Kconfig"
+ source "drivers/media/platform/st/Kconfig"
+ source "drivers/media/platform/sunxi/Kconfig"
++source "drivers/media/platform/synopsys/Kconfig"
+ source "drivers/media/platform/ti/Kconfig"
+ source "drivers/media/platform/verisilicon/Kconfig"
+ source "drivers/media/platform/via/Kconfig"
+diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/Makefile
++++ b/drivers/media/platform/Makefile
+@@ -28,6 +28,7 @@ obj-y += rockchip/
+ obj-y += samsung/
+ obj-y += st/
+ obj-y += sunxi/
++obj-y += synopsys/
+ obj-y += ti/
+ obj-y += verisilicon/
+ obj-y += via/
+diff --git a/drivers/media/platform/synopsys/Kconfig b/drivers/media/platform/synopsys/Kconfig
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/Kconfig
+@@ -0,0 +1,3 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++source "drivers/media/platform/synopsys/hdmirx/Kconfig"
+diff --git a/drivers/media/platform/synopsys/Makefile b/drivers/media/platform/synopsys/Makefile
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0-only
++obj-y += hdmirx/
+diff --git a/drivers/media/platform/synopsys/hdmirx/Kconfig b/drivers/media/platform/synopsys/hdmirx/Kconfig
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/Kconfig
+@@ -0,0 +1,27 @@
++# SPDX-License-Identifier: GPL-2.0
++
++config VIDEO_SYNOPSYS_HDMIRX
++	tristate "Synopsys DesignWare HDMI Receiver driver"
++	depends on VIDEO_DEV
++	depends on ARCH_ROCKCHIP
++	select MEDIA_CONTROLLER
++	select VIDEO_V4L2_SUBDEV_API
++	select VIDEOBUF2_DMA_CONTIG
++	select CEC_CORE
++	select CEC_NOTIFIER
++	select HDMI
++	help
++	  Support for Synopsys HDMI HDMI RX Controller.
++	  This driver supports HDMI 2.0 version.
++
++	  To compile this driver as a module, choose M here. The module
++	  will be called synopsys_hdmirx.
++
++config HDMIRX_LOAD_DEFAULT_EDID
++	bool "Load default EDID"
++	depends on VIDEO_SYNOPSYS_HDMIRX
++	default "y"
++	help
++	  Preload the default EDID (Extended Display Identification Data).
++	  EDID contains information about the capabilities of the display,
++	  such as supported resolutions, refresh rates, and audio formats.
+diff --git a/drivers/media/platform/synopsys/hdmirx/Makefile b/drivers/media/platform/synopsys/hdmirx/Makefile
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/Makefile
+@@ -0,0 +1,4 @@
++# SPDX-License-Identifier: GPL-2.0
++synopsys-hdmirx-objs := snps_hdmirx.o snps_hdmirx_cec.o
++
++obj-$(CONFIG_VIDEO_SYNOPSYS_HDMIRX) += synopsys-hdmirx.o
+diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
+@@ -0,0 +1,2763 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2024 Collabora, Ltd.
++ * Author: Shreeya Patel <shreeya.patel@collabora.com>
++ *
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ * Author: Dingxian Wen <shawn.wen@rock-chips.com>
++ */
++
++#include <linux/arm-smccc.h>
++#include <linux/clk.h>
++#include <linux/completion.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/gpio/consumer.h>
++#include <linux/hdmi.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/of_reserved_mem.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/platform_device.h>
++#include <linux/property.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/v4l2-dv-timings.h>
++#include <linux/workqueue.h>
++
++#include <media/cec.h>
++#include <media/cec-notifier.h>
++#include <media/v4l2-common.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-dv-timings.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-fh.h>
++#include <media/v4l2-ioctl.h>
++#include <media/videobuf2-dma-contig.h>
++#include <media/videobuf2-v4l2.h>
++#include <media/v4l2-common.h>
++
++#include <sound/hdmi-codec.h>
++
++#include "snps_hdmirx.h"
++#include "snps_hdmirx_cec.h"
++
++static int debug;
++module_param(debug, int, 0644);
++MODULE_PARM_DESC(debug, "debug level (0-3)");
++
++#define EDID_NUM_BLOCKS_MAX			2
++#define EDID_BLOCK_SIZE				128
++#define HDMIRX_STORED_BIT_WIDTH			8
++#define IREF_CLK_FREQ_HZ			428571429
++#define MEMORY_ALIGN_ROUND_UP_BYTES		64
++#define HDMIRX_PLANE_Y				0
++#define HDMIRX_PLANE_CBCR			1
++#define RK_IRQ_HDMIRX_HDMI			210
++#define FILTER_FRAME_CNT			6
++#define RK_SIP_FIQ_CTRL				0x82000024
++#define SIP_WDT_CFG				0x82000026
++#define DETECTION_THRESHOLD			7
++
++/* fiq control sub func */
++enum {
++	RK_SIP_FIQ_CTRL_FIQ_EN = 1,
++	RK_SIP_FIQ_CTRL_FIQ_DIS,
++	RK_SIP_FIQ_CTRL_SET_AFF
++};
++
++/* SIP_WDT_CONFIG call types  */
++enum {
++	WDT_START = 0,
++	WDT_STOP = 1,
++	WDT_PING = 2,
++};
++
++enum hdmirx_pix_fmt {
++	HDMIRX_RGB888 = 0,
++	HDMIRX_YUV422 = 1,
++	HDMIRX_YUV444 = 2,
++	HDMIRX_YUV420 = 3,
++};
++
++enum ddr_store_fmt {
++	STORE_RGB888 = 0,
++	STORE_RGBA_ARGB,
++	STORE_YUV420_8BIT,
++	STORE_YUV420_10BIT,
++	STORE_YUV422_8BIT,
++	STORE_YUV422_10BIT,
++	STORE_YUV444_8BIT,
++	STORE_YUV420_16BIT = 8,
++	STORE_YUV422_16BIT = 9,
++};
++
++enum hdmirx_reg_attr {
++	HDMIRX_ATTR_RW = 0,
++	HDMIRX_ATTR_RO = 1,
++	HDMIRX_ATTR_WO = 2,
++	HDMIRX_ATTR_RE = 3,
++};
++
++enum {
++	HDMIRX_RST_A,
++	HDMIRX_RST_P,
++	HDMIRX_RST_REF,
++	HDMIRX_RST_BIU,
++	HDMIRX_NUM_RST,
++};
++
++static const char * const pix_fmt_str[] = {
++	"RGB888",
++	"YUV422",
++	"YUV444",
++	"YUV420",
++};
++
++struct hdmirx_buffer {
++	struct vb2_v4l2_buffer vb;
++	struct list_head queue;
++	u32 buff_addr[VIDEO_MAX_PLANES];
++};
++
++struct hdmirx_stream {
++	struct snps_hdmirx_dev *hdmirx_dev;
++	struct video_device vdev;
++	struct vb2_queue buf_queue;
++	struct list_head buf_head;
++	struct hdmirx_buffer *curr_buf;
++	struct hdmirx_buffer *next_buf;
++	struct v4l2_pix_format_mplane pixm;
++	const struct v4l2_format_info *out_finfo;
++	struct mutex vlock; /* to lock resources associated with video buffer and video device */
++	spinlock_t vbq_lock; /* to lock video buffer queue */
++	bool stopping;
++	wait_queue_head_t wq_stopped;
++	u32 frame_idx;
++	u32 line_flag_int_cnt;
++	u32 irq_stat;
++};
++
++struct snps_hdmirx_dev {
++	struct device *dev;
++	struct device *codec_dev;
++	struct hdmirx_stream stream;
++	struct v4l2_device v4l2_dev;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *detect_tx_5v_ctrl;
++	struct v4l2_ctrl *rgb_range;
++	struct v4l2_dv_timings timings;
++	struct gpio_desc *detect_5v_gpio;
++	struct work_struct work_wdt_config;
++	struct delayed_work delayed_work_hotplug;
++	struct delayed_work delayed_work_res_change;
++	struct delayed_work delayed_work_heartbeat;
++	struct cec_notifier *cec_notifier;
++	struct hdmirx_cec *cec;
++	struct mutex stream_lock; /* to lock video stream capture */
++	struct mutex work_lock; /* to lock the critical section of hotplug event */
++	struct reset_control_bulk_data resets[HDMIRX_NUM_RST];
++	struct clk_bulk_data *clks;
++	struct regmap *grf;
++	struct regmap *vo1_grf;
++	struct completion cr_write_done;
++	struct completion timer_base_lock;
++	struct completion avi_pkt_rcv;
++	enum hdmirx_pix_fmt pix_fmt;
++	void __iomem *regs;
++	int hdmi_irq;
++	int dma_irq;
++	int det_irq;
++	bool hpd_trigger_level;
++	bool tmds_clk_ratio;
++	bool is_dvi_mode;
++	bool got_timing;
++	u32 num_clks;
++	u32 edid_blocks_written;
++	u32 cur_vic;
++	u32 cur_fmt_fourcc;
++	u32 color_depth;
++	u8 edid[EDID_BLOCK_SIZE * 2];
++	hdmi_codec_plugged_cb plugged_cb;
++	spinlock_t rst_lock; /* to lock register access */
++};
++
++static u8 edid_init_data_340M[] = {
++	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
++	0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00,
++	0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78,
++	0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23,
++	0x09, 0x48, 0x4C, 0x21, 0x08, 0x00, 0x61, 0x40,
++	0x01, 0x01, 0x81, 0x00, 0x95, 0x00, 0xA9, 0xC0,
++	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
++	0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
++	0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E,
++	0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
++	0x6E, 0x28, 0x55, 0x00, 0x20, 0xC2, 0x31, 0x00,
++	0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52,
++	0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20,
++	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
++	0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
++	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xA7,
++
++	0x02, 0x03, 0x2F, 0xD1, 0x51, 0x07, 0x16, 0x14,
++	0x05, 0x01, 0x03, 0x12, 0x13, 0x84, 0x22, 0x1F,
++	0x90, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x23, 0x09,
++	0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03,
++	0x0C, 0x00, 0x30, 0x00, 0x10, 0x44, 0xE3, 0x05,
++	0x03, 0x01, 0xE4, 0x0F, 0x00, 0x80, 0x01, 0x02,
++	0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58,
++	0x2C, 0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00,
++	0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F,
++};
++
++static const struct v4l2_dv_timings cea640x480 = V4L2_DV_BT_CEA_640X480P59_94;
++
++static const struct v4l2_dv_timings_cap hdmirx_timings_cap = {
++	.type = V4L2_DV_BT_656_1120,
++	.reserved = { 0 },
++	V4L2_INIT_BT_TIMINGS(640, 4096,			/* min/max width */
++			     480, 2160,			/* min/max height */
++			     20000000, 600000000,	/* min/max pixelclock */
++			     /* standards */
++			     V4L2_DV_BT_STD_CEA861,
++			     /* capabilities */
++			     V4L2_DV_BT_CAP_PROGRESSIVE |
++			     V4L2_DV_BT_CAP_INTERLACED)
++};
++
++static void hdmirx_writel(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val)
++{
++	unsigned long lock_flags = 0;
++
++	spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
++	writel(val, hdmirx_dev->regs + reg);
++	spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
++}
++
++static u32 hdmirx_readl(struct snps_hdmirx_dev *hdmirx_dev, int reg)
++{
++	unsigned long lock_flags = 0;
++	u32 val;
++
++	spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
++	val = readl(hdmirx_dev->regs + reg);
++	spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
++	return val;
++}
++
++static void hdmirx_reset_dma(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	unsigned long lock_flags = 0;
++
++	spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
++	reset_control_reset(hdmirx_dev->resets[0].rstc);
++	spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
++}
++
++static void hdmirx_update_bits(struct snps_hdmirx_dev *hdmirx_dev, int reg,
++			       u32 mask, u32 data)
++{
++	unsigned long lock_flags = 0;
++	u32 val;
++
++	spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
++	val = readl(hdmirx_dev->regs + reg) & ~mask;
++	val |= (data & mask);
++	writel(val, hdmirx_dev->regs + reg);
++	spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
++}
++
++static int hdmirx_subscribe_event(struct v4l2_fh *fh,
++				  const struct v4l2_event_subscription *sub)
++{
++	switch (sub->type) {
++	case V4L2_EVENT_SOURCE_CHANGE:
++		if (fh->vdev->vfl_dir == VFL_DIR_RX)
++			return v4l2_src_change_event_subscribe(fh, sub);
++		break;
++	case V4L2_EVENT_CTRL:
++		return v4l2_ctrl_subscribe_event(fh, sub);
++	default:
++		break;
++	}
++
++	return -EINVAL;
++}
++
++static bool tx_5v_power_present(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	bool ret;
++	int val, i, cnt;
++
++	cnt = 0;
++	for (i = 0; i < 10; i++) {
++		usleep_range(1000, 1100);
++		val = gpiod_get_value(hdmirx_dev->detect_5v_gpio);
++		if (val > 0)
++			cnt++;
++		if (cnt >= DETECTION_THRESHOLD)
++			break;
++	}
++
++	ret = (cnt >= DETECTION_THRESHOLD) ? true : false;
++	v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: %d\n", __func__, ret);
++
++	return ret;
++}
++
++static bool signal_not_lock(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	u32 mu_status, dma_st10, cmu_st;
++
++	mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS);
++	dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10);
++	cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS);
++
++	if ((mu_status & TMDSVALID_STABLE_ST) &&
++	    (dma_st10 & HDMIRX_LOCK) &&
++	    (cmu_st & TMDSQPCLK_LOCKED_ST))
++		return false;
++
++	return true;
++}
++
++static void hdmirx_get_colordepth(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 val, color_depth_reg;
++
++	val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
++	color_depth_reg = (val & HDMIRX_COLOR_DEPTH_MASK) >> 3;
++
++	switch (color_depth_reg) {
++	case 0x4:
++		hdmirx_dev->color_depth = 24;
++		break;
++	case 0x5:
++		hdmirx_dev->color_depth = 30;
++		break;
++	case 0x6:
++		hdmirx_dev->color_depth = 36;
++		break;
++	case 0x7:
++		hdmirx_dev->color_depth = 48;
++		break;
++	default:
++		hdmirx_dev->color_depth = 24;
++		break;
++	}
++
++	v4l2_dbg(1, debug, v4l2_dev, "%s: color_depth: %d, reg_val:%d\n",
++		 __func__, hdmirx_dev->color_depth, color_depth_reg);
++}
++
++static void hdmirx_get_pix_fmt(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 val;
++
++	val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
++	hdmirx_dev->pix_fmt = val & HDMIRX_FORMAT_MASK;
++
++	switch (hdmirx_dev->pix_fmt) {
++	case HDMIRX_RGB888:
++		hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
++		break;
++	case HDMIRX_YUV422:
++		hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV16;
++		break;
++	case HDMIRX_YUV444:
++		hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV24;
++		break;
++	case HDMIRX_YUV420:
++		hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV12;
++		break;
++	default:
++		v4l2_err(v4l2_dev,
++			 "%s: err pix_fmt: %d, set RGB888 as default\n",
++			 __func__, hdmirx_dev->pix_fmt);
++		hdmirx_dev->pix_fmt = HDMIRX_RGB888;
++		hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
++		break;
++	}
++
++	v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s\n", __func__,
++		 pix_fmt_str[hdmirx_dev->pix_fmt]);
++}
++
++static void hdmirx_get_timings(struct snps_hdmirx_dev *hdmirx_dev,
++			       struct v4l2_bt_timings *bt, bool from_dma)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 hact, vact, htotal, vtotal, fps;
++	u32 hfp, hs, hbp, vfp, vs, vbp;
++	u32 val;
++
++	if (from_dma) {
++		val = hdmirx_readl(hdmirx_dev, DMA_STATUS2);
++		hact = (val >> 16) & 0xffff;
++		vact = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, DMA_STATUS3);
++		htotal = (val >> 16) & 0xffff;
++		vtotal = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, DMA_STATUS4);
++		hs = (val >> 16) & 0xffff;
++		vs = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, DMA_STATUS5);
++		hbp = (val >> 16) & 0xffff;
++		vbp = val & 0xffff;
++		hfp = htotal - hact - hs - hbp;
++		vfp = vtotal - vact - vs - vbp;
++	} else {
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS1);
++		hs = (val >> 16) & 0xffff;
++		hfp = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS2);
++		hbp = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS3);
++		htotal = (val >> 16) & 0xffff;
++		hact = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS4);
++		vs = (val >> 16) & 0xffff;
++		vfp = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS5);
++		vbp = val & 0xffff;
++		val = hdmirx_readl(hdmirx_dev, VMON_STATUS6);
++		vtotal = (val >> 16) & 0xffff;
++		vact = val & 0xffff;
++		if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
++			hact *= 2;
++	}
++	if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
++		htotal *= 2;
++	fps = (bt->pixelclock + (htotal * vtotal) / 2) / (htotal * vtotal);
++	if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
++		fps *= 2;
++	bt->width = hact;
++	bt->height = vact;
++	bt->hfrontporch = hfp;
++	bt->hsync = hs;
++	bt->hbackporch = hbp;
++	bt->vfrontporch = vfp;
++	bt->vsync = vs;
++	bt->vbackporch = vbp;
++
++	v4l2_dbg(1, debug, v4l2_dev, "get timings from %s\n", from_dma ? "dma" : "ctrl");
++	v4l2_dbg(1, debug, v4l2_dev, "act:%ux%u, total:%ux%u, fps:%u, pixclk:%llu\n",
++		 bt->width, bt->height, htotal, vtotal, fps, bt->pixelclock);
++
++	v4l2_dbg(2, debug, v4l2_dev, "hfp:%u, hs:%u, hbp:%u, vfp:%u, vs:%u, vbp:%u\n",
++		 bt->hfrontporch, bt->hsync, bt->hbackporch,
++		 bt->vfrontporch, bt->vsync, bt->vbackporch);
++}
++
++static bool hdmirx_check_timing_valid(struct v4l2_bt_timings *bt)
++{
++	if (bt->width < 100 || bt->width > 5000 ||
++	    bt->height < 100 || bt->height > 5000)
++		return false;
++
++	if (!bt->hsync || bt->hsync > 200 ||
++	    !bt->vsync || bt->vsync > 100)
++		return false;
++
++	if (!bt->hbackporch || bt->hbackporch > 2000 ||
++	    !bt->vbackporch || bt->vbackporch > 2000)
++		return false;
++
++	if (!bt->hfrontporch || bt->hfrontporch > 2000 ||
++	    !bt->vfrontporch || bt->vfrontporch > 2000)
++		return false;
++
++	return true;
++}
++
++static void hdmirx_get_avi_infoframe(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	union hdmi_infoframe frame = {};
++	int err, i, b, itr = 0;
++	u8 aviif[3 + 7 * 4];
++	u32 val;
++
++	aviif[itr++] = HDMI_INFOFRAME_TYPE_AVI;
++	val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1);
++	aviif[itr++] = val & 0xff;
++	aviif[itr++] = (val >> 8) & 0xff;
++
++	for (i = 0; i < 7; i++) {
++		val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB3_0 + 4 * i);
++
++		for (b = 0; b < 4; b++)
++			aviif[itr++] = (val >> (8 * b)) & 0xff;
++	}
++
++	err = hdmi_infoframe_unpack(&frame, aviif, sizeof(aviif));
++	if (err) {
++		v4l2_err(v4l2_dev, "failed to unpack AVI infoframe\n");
++		return;
++	}
++
++	v4l2_ctrl_s_ctrl(hdmirx_dev->rgb_range, frame.avi.quantization_range);
++}
++
++/*
++ * When querying DV timings during preview, if the DMA's timing is stable,
++ * we retrieve the timings directly from the DMA. However, if the current
++ * resolution is negative, obtaining the timing from CTRL may require a
++ * change in the sync polarity, potentially leading to DMA errors.
++ */
++static int hdmirx_get_detected_timings(struct snps_hdmirx_dev *hdmirx_dev,
++				       struct v4l2_dv_timings *timings,
++				       bool from_dma)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct v4l2_bt_timings *bt = &timings->bt;
++	u32 field_type, color_depth, deframer_st;
++	u32 val, tmdsqpclk_freq, pix_clk;
++	u64 tmp_data, tmds_clk;
++
++	memset(timings, 0, sizeof(struct v4l2_dv_timings));
++	timings->type = V4L2_DV_BT_656_1120;
++
++	val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
++	field_type = (val & HDMIRX_TYPE_MASK) >> 7;
++	hdmirx_get_pix_fmt(hdmirx_dev);
++	bt->interlaced = field_type & BIT(0) ? V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
++	val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB7_4);
++	hdmirx_dev->cur_vic =  val | VIC_VAL_MASK;
++	hdmirx_get_colordepth(hdmirx_dev);
++	color_depth = hdmirx_dev->color_depth;
++	deframer_st = hdmirx_readl(hdmirx_dev, DEFRAMER_STATUS);
++	hdmirx_dev->is_dvi_mode = deframer_st & OPMODE_STS_MASK ? false : true;
++	tmdsqpclk_freq = hdmirx_readl(hdmirx_dev, CMU_TMDSQPCLK_FREQ);
++	tmds_clk = tmdsqpclk_freq * 4 * 1000;
++	tmp_data = tmds_clk * 24;
++	do_div(tmp_data, color_depth);
++	pix_clk = tmp_data;
++	bt->pixelclock = pix_clk;
++
++	hdmirx_get_avi_infoframe(hdmirx_dev);
++
++	hdmirx_get_timings(hdmirx_dev, bt, from_dma);
++	if (bt->interlaced == V4L2_DV_INTERLACED) {
++		bt->height *= 2;
++		bt->il_vsync = bt->vsync + 1;
++	}
++
++	v4l2_dbg(2, debug, v4l2_dev, "tmds_clk:%llu\n", tmds_clk);
++	v4l2_dbg(1, debug, v4l2_dev, "interlace:%d, fmt:%d, vic:%d, color:%d, mode:%s\n",
++		 bt->interlaced, hdmirx_dev->pix_fmt,
++		 hdmirx_dev->cur_vic, hdmirx_dev->color_depth,
++		 hdmirx_dev->is_dvi_mode ? "dvi" : "hdmi");
++	v4l2_dbg(2, debug, v4l2_dev, "deframer_st:%#x\n", deframer_st);
++
++	if (!hdmirx_check_timing_valid(bt))
++		return -EINVAL;
++
++	return 0;
++}
++
++static bool port_no_link(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	return !tx_5v_power_present(hdmirx_dev);
++}
++
++static int hdmirx_query_dv_timings(struct file *file, void *_fh,
++				   struct v4l2_dv_timings *timings)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	int ret;
++
++	if (port_no_link(hdmirx_dev)) {
++		v4l2_err(v4l2_dev, "%s: port has no link\n", __func__);
++		return -ENOLINK;
++	}
++
++	if (signal_not_lock(hdmirx_dev)) {
++		v4l2_err(v4l2_dev, "%s: signal is not locked\n", __func__);
++		return -ENOLCK;
++	}
++
++	ret = hdmirx_get_detected_timings(hdmirx_dev, timings, true);
++	if (ret)
++		return ret;
++
++	if (debug)
++		v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name,
++				      "query_dv_timings: ", timings, false);
++
++	if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) {
++		v4l2_dbg(1, debug, v4l2_dev, "%s: timings out of range\n", __func__);
++		return -ERANGE;
++	}
++
++	return 0;
++}
++
++static void hdmirx_hpd_ctrl(struct snps_hdmirx_dev *hdmirx_dev, bool en)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	v4l2_dbg(1, debug, v4l2_dev, "%s: %sable, hpd_trigger_level:%d\n",
++		 __func__, en ? "en" : "dis",
++		 hdmirx_dev->hpd_trigger_level);
++	hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, HPDLOW, en ? 0 : HPDLOW);
++	en = hdmirx_dev->hpd_trigger_level ? en : !en;
++	hdmirx_writel(hdmirx_dev, CORE_CONFIG, en);
++}
++
++static int hdmirx_write_edid(struct snps_hdmirx_dev *hdmirx_dev,
++			     struct v4l2_edid *edid, bool hpd_up)
++{
++	u32 edid_len = edid->blocks * EDID_BLOCK_SIZE;
++	char data[300];
++	u32 i;
++
++	memset(edid->reserved, 0, sizeof(edid->reserved));
++	if (edid->pad)
++		return -EINVAL;
++
++	if (edid->start_block)
++		return -EINVAL;
++
++	if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
++		edid->blocks = EDID_NUM_BLOCKS_MAX;
++		return -E2BIG;
++	}
++
++	if (!edid->blocks) {
++		hdmirx_dev->edid_blocks_written = 0;
++		return 0;
++	}
++
++	cec_s_phys_addr_from_edid(hdmirx_dev->cec->adap,
++				  (const struct edid *)edid->edid);
++
++	memset(&hdmirx_dev->edid, 0, sizeof(hdmirx_dev->edid));
++	hdmirx_hpd_ctrl(hdmirx_dev, false);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
++			   EDID_READ_EN_MASK |
++			   EDID_WRITE_EN_MASK |
++			   EDID_SLAVE_ADDR_MASK,
++			   EDID_READ_EN(0) |
++			   EDID_WRITE_EN(1) |
++			   EDID_SLAVE_ADDR(0x50));
++	for (i = 0; i < edid_len; i++)
++		hdmirx_writel(hdmirx_dev, DMA_CONFIG10, edid->edid[i]);
++
++	/* read out for debug */
++	if (debug >= 2) {
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
++				   EDID_READ_EN_MASK |
++				   EDID_WRITE_EN_MASK,
++				   EDID_READ_EN(1) |
++				   EDID_WRITE_EN(0));
++		edid_len = edid_len > sizeof(data) ? sizeof(data) : edid_len;
++		memset(data, 0, sizeof(data));
++		for (i = 0; i < edid_len; i++)
++			data[i] = hdmirx_readl(hdmirx_dev, DMA_STATUS14);
++
++		print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, data,
++			       edid_len, false);
++	}
++
++	/*
++	 * You must set EDID_READ_EN & EDID_WRITE_EN bit to 0,
++	 * when the read/write edid operation is completed.Otherwise, it
++	 * will affect the reading and writing of other registers
++	 */
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
++			   EDID_READ_EN_MASK | EDID_WRITE_EN_MASK,
++			   EDID_READ_EN(0) | EDID_WRITE_EN(0));
++
++	hdmirx_dev->edid_blocks_written = edid->blocks;
++	memcpy(&hdmirx_dev->edid, edid->edid, edid->blocks * EDID_BLOCK_SIZE);
++	if (hpd_up) {
++		if (tx_5v_power_present(hdmirx_dev)) {
++			/* Add 100ms delay after updating the EDID as per HDMI specs */
++			msleep(100);
++			hdmirx_hpd_ctrl(hdmirx_dev, true);
++		}
++	}
++
++	return 0;
++}
++
++/*
++ * Before clearing interrupt, we need to read the interrupt status.
++ */
++static inline void hdmirx_clear_interrupt(struct snps_hdmirx_dev *hdmirx_dev,
++					  u32 reg, u32 val)
++{
++	/* (interrupt status register) = (interrupt clear register) - 0x8 */
++	hdmirx_readl(hdmirx_dev, reg - 0x8);
++	hdmirx_writel(hdmirx_dev, reg, val);
++}
++
++static void hdmirx_interrupts_setup(struct snps_hdmirx_dev *hdmirx_dev, bool en)
++{
++	v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: %sable\n",
++		 __func__, en ? "en" : "dis");
++
++	/* Note: In DVI mode, it needs to be written twice to take effect. */
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff);
++
++	if (en) {
++		hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N,
++				   TMDSQPCLK_OFF_CHG | TMDSQPCLK_LOCKED_CHG,
++				   TMDSQPCLK_OFF_CHG | TMDSQPCLK_LOCKED_CHG);
++		hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
++				   TMDSVALID_STABLE_CHG, TMDSVALID_STABLE_CHG);
++		hdmirx_update_bits(hdmirx_dev, AVPUNIT_0_INT_MASK_N,
++				   CED_DYN_CNT_CH2_IRQ |
++				   CED_DYN_CNT_CH1_IRQ |
++				   CED_DYN_CNT_CH0_IRQ,
++				   CED_DYN_CNT_CH2_IRQ |
++				   CED_DYN_CNT_CH1_IRQ |
++				   CED_DYN_CNT_CH0_IRQ);
++	} else {
++		hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0);
++		hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0);
++		hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0);
++	}
++}
++
++static void hdmirx_plugout(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct arm_smccc_res res;
++
++	hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, 0);
++	hdmirx_interrupts_setup(hdmirx_dev, false);
++	hdmirx_hpd_ctrl(hdmirx_dev, false);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
++			   LINE_FLAG_INT_EN |
++			   HDMIRX_DMA_IDLE_INT |
++			   HDMIRX_LOCK_DISABLE_INT |
++			   LAST_FRAME_AXI_UNFINISH_INT_EN |
++			   FIFO_OVERFLOW_INT_EN |
++			   FIFO_UNDERFLOW_INT_EN |
++			   HDMIRX_AXI_ERROR_INT_EN, 0);
++	hdmirx_reset_dma(hdmirx_dev);
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE | PHY_RESET |
++			   PHY_PDDQ, HDMI_DISABLE);
++	hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x0);
++	cancel_delayed_work(&hdmirx_dev->delayed_work_res_change);
++	cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat);
++	flush_work(&hdmirx_dev->work_wdt_config);
++	arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res);
++}
++
++static int hdmirx_set_edid(struct file *file, void *fh, struct v4l2_edid *edid)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct arm_smccc_res res;
++	int ret;
++
++	disable_irq(hdmirx_dev->hdmi_irq);
++	disable_irq(hdmirx_dev->dma_irq);
++	arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_DIS,
++		      RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res);
++
++	if (tx_5v_power_present(hdmirx_dev))
++		hdmirx_plugout(hdmirx_dev);
++	ret = hdmirx_write_edid(hdmirx_dev, edid, false);
++	if (ret)
++		return ret;
++
++	enable_irq(hdmirx_dev->hdmi_irq);
++	enable_irq(hdmirx_dev->dma_irq);
++	arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN,
++		      RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res);
++	queue_delayed_work(system_unbound_wq,
++			   &hdmirx_dev->delayed_work_hotplug,
++			   msecs_to_jiffies(500));
++	return 0;
++}
++
++static int hdmirx_get_edid(struct file *file, void *fh, struct v4l2_edid *edid)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	memset(edid->reserved, 0, sizeof(edid->reserved));
++
++	if (edid->pad)
++		return -EINVAL;
++
++	if (!edid->start_block && !edid->blocks) {
++		edid->blocks = hdmirx_dev->edid_blocks_written;
++		return 0;
++	}
++
++	if (!hdmirx_dev->edid_blocks_written)
++		return -ENODATA;
++
++	if (edid->start_block >= hdmirx_dev->edid_blocks_written || !edid->blocks)
++		return -EINVAL;
++
++	if (edid->start_block + edid->blocks > hdmirx_dev->edid_blocks_written)
++		edid->blocks = hdmirx_dev->edid_blocks_written - edid->start_block;
++
++	memcpy(edid->edid, &hdmirx_dev->edid, edid->blocks * EDID_BLOCK_SIZE);
++
++	v4l2_dbg(1, debug, v4l2_dev, "%s: read EDID:\n", __func__);
++	if (debug > 0)
++		print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1,
++			       edid->edid, edid->blocks * EDID_BLOCK_SIZE, false);
++
++	return 0;
++}
++
++static int hdmirx_g_parm(struct file *file, void *priv,
++			 struct v4l2_streamparm *parm)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_fract fps;
++
++	if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
++		return -EINVAL;
++
++	fps = v4l2_calc_timeperframe(&hdmirx_dev->timings);
++	parm->parm.capture.timeperframe.numerator = fps.numerator;
++	parm->parm.capture.timeperframe.denominator = fps.denominator;
++
++	return 0;
++}
++
++static int hdmirx_dv_timings_cap(struct file *file, void *fh,
++				 struct v4l2_dv_timings_cap *cap)
++{
++	*cap = hdmirx_timings_cap;
++	return 0;
++}
++
++static int hdmirx_enum_dv_timings(struct file *file, void *_fh,
++				  struct v4l2_enum_dv_timings *timings)
++{
++	return v4l2_enum_dv_timings_cap(timings, &hdmirx_timings_cap, NULL, NULL);
++}
++
++static void hdmirx_scdc_init(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	hdmirx_update_bits(hdmirx_dev, I2C_SLAVE_CONFIG1,
++			   I2C_SDA_OUT_HOLD_VALUE_QST_MASK |
++			   I2C_SDA_IN_HOLD_VALUE_QST_MASK,
++			   I2C_SDA_OUT_HOLD_VALUE_QST(0x80) |
++			   I2C_SDA_IN_HOLD_VALUE_QST(0x15));
++	hdmirx_update_bits(hdmirx_dev, SCDC_REGBANK_CONFIG0,
++			   SCDC_SINKVERSION_QST_MASK,
++			   SCDC_SINKVERSION_QST(1));
++}
++
++static int wait_reg_bit_status(struct snps_hdmirx_dev *hdmirx_dev, u32 reg,
++			       u32 bit_mask, u32 expect_val, bool is_grf,
++			       u32 ms)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 i, val;
++
++	for (i = 0; i < ms; i++) {
++		if (is_grf)
++			regmap_read(hdmirx_dev->grf, reg, &val);
++		else
++			val = hdmirx_readl(hdmirx_dev, reg);
++
++		if ((val & bit_mask) == expect_val) {
++			v4l2_dbg(2, debug, v4l2_dev,
++				 "%s:  i:%d, time: %dms\n", __func__, i, ms);
++			break;
++		}
++		usleep_range(1000, 1010);
++	}
++
++	if (i == ms)
++		return -1;
++
++	return 0;
++}
++
++static int hdmirx_phy_register_write(struct snps_hdmirx_dev *hdmirx_dev,
++				     u32 phy_reg, u32 val)
++{
++	struct device *dev = hdmirx_dev->dev;
++
++	reinit_completion(&hdmirx_dev->cr_write_done);
++	/* clear irq status */
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
++	/* en irq */
++	hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
++			   PHYCREG_CR_WRITE_DONE, PHYCREG_CR_WRITE_DONE);
++	/* write phy reg addr */
++	hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG1, phy_reg);
++	/* write phy reg val */
++	hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG2, val);
++	/* config write enable */
++	hdmirx_writel(hdmirx_dev, PHYCREG_CONTROL, PHYCREG_CR_PARA_WRITE_P);
++
++	if (!wait_for_completion_timeout(&hdmirx_dev->cr_write_done,
++					 msecs_to_jiffies(20))) {
++		dev_err(dev, "%s wait cr write done failed\n", __func__);
++		return -1;
++	}
++
++	return 0;
++}
++
++static void hdmirx_tmds_clk_ratio_config(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 val;
++
++	val = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS1);
++	v4l2_dbg(3, debug, v4l2_dev, "%s: scdc_regbank_st:%#x\n", __func__, val);
++	hdmirx_dev->tmds_clk_ratio = (val & SCDC_TMDSBITCLKRATIO) > 0;
++
++	if (hdmirx_dev->tmds_clk_ratio) {
++		v4l2_dbg(3, debug, v4l2_dev, "%s: HDMITX greater than 3.4Gbps\n", __func__);
++		hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
++				   TMDS_CLOCK_RATIO, TMDS_CLOCK_RATIO);
++	} else {
++		v4l2_dbg(3, debug, v4l2_dev, "%s: HDMITX less than 3.4Gbps\n", __func__);
++		hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
++				   TMDS_CLOCK_RATIO, 0);
++	}
++}
++
++static void hdmirx_phy_config(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct device *dev = hdmirx_dev->dev;
++
++	hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff);
++	hdmirx_update_bits(hdmirx_dev, SCDC_INT_MASK_N, SCDCTMDSCCFG_CHG,
++			   SCDCTMDSCCFG_CHG);
++	/* cr_para_clk 24M */
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, REFFREQ_SEL_MASK, REFFREQ_SEL(0));
++	/* rx data width 40bit valid */
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, RXDATA_WIDTH, RXDATA_WIDTH);
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, PHY_RESET);
++	usleep_range(100, 110);
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, 0);
++	usleep_range(100, 110);
++	/* select cr para interface */
++	hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x3);
++
++	if (wait_reg_bit_status(hdmirx_dev, SYS_GRF_SOC_STATUS1,
++				HDMIRXPHY_SRAM_INIT_DONE,
++				HDMIRXPHY_SRAM_INIT_DONE, true, 10))
++		dev_err(dev, "%s: phy SRAM init failed\n", __func__);
++
++	regmap_write(hdmirx_dev->grf, SYS_GRF_SOC_CON1,
++		     (HDMIRXPHY_SRAM_EXT_LD_DONE << 16) |
++		     HDMIRXPHY_SRAM_EXT_LD_DONE);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 3);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 3);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 1);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
++	hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
++
++	hdmirx_phy_register_write(hdmirx_dev,
++				  HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG,
++				  CDR_SETTING_BOUNDARY_3_DEFAULT);
++	hdmirx_phy_register_write(hdmirx_dev,
++				  HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG,
++				  CDR_SETTING_BOUNDARY_4_DEFAULT);
++	hdmirx_phy_register_write(hdmirx_dev,
++				  HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG,
++				  CDR_SETTING_BOUNDARY_5_DEFAULT);
++	hdmirx_phy_register_write(hdmirx_dev,
++				  HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG,
++				  CDR_SETTING_BOUNDARY_6_DEFAULT);
++	hdmirx_phy_register_write(hdmirx_dev,
++				  HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG,
++				  CDR_SETTING_BOUNDARY_7_DEFAULT);
++
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_PDDQ, 0);
++	if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, PDDQ_ACK, 0, false, 10))
++		dev_err(dev, "%s: wait pddq ack failed\n", __func__);
++
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE, 0);
++	if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, HDMI_DISABLE_ACK, 0,
++				false, 50))
++		dev_err(dev, "%s: wait hdmi disable ack failed\n", __func__);
++
++	hdmirx_tmds_clk_ratio_config(hdmirx_dev);
++}
++
++static void hdmirx_controller_init(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct device *dev = hdmirx_dev->dev;
++
++	reinit_completion(&hdmirx_dev->timer_base_lock);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
++	/* en irq */
++	hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N,
++			   TIMER_BASE_LOCKED_IRQ, TIMER_BASE_LOCKED_IRQ);
++	/* write irefclk freq */
++	hdmirx_writel(hdmirx_dev, GLOBAL_TIMER_REF_BASE, IREF_CLK_FREQ_HZ);
++
++	if (!wait_for_completion_timeout(&hdmirx_dev->timer_base_lock,
++					 msecs_to_jiffies(20)))
++		dev_err(dev, "%s wait timer base lock failed\n", __func__);
++
++	hdmirx_update_bits(hdmirx_dev, CMU_CONFIG0,
++			   TMDSQPCLK_STABLE_FREQ_MARGIN_MASK |
++			   AUDCLK_STABLE_FREQ_MARGIN_MASK,
++			   TMDSQPCLK_STABLE_FREQ_MARGIN(2) |
++			   AUDCLK_STABLE_FREQ_MARGIN(1));
++	hdmirx_update_bits(hdmirx_dev, DESCRAND_EN_CONTROL,
++			   SCRAMB_EN_SEL_QST_MASK, SCRAMB_EN_SEL_QST(1));
++	hdmirx_update_bits(hdmirx_dev, CED_CONFIG,
++			   CED_VIDDATACHECKEN_QST |
++			   CED_DATAISCHECKEN_QST |
++			   CED_GBCHECKEN_QST |
++			   CED_CTRLCHECKEN_QST |
++			   CED_CHLOCKMAXER_QST_MASK,
++			   CED_VIDDATACHECKEN_QST |
++			   CED_GBCHECKEN_QST |
++			   CED_CTRLCHECKEN_QST |
++			   CED_CHLOCKMAXER_QST(0x10));
++	hdmirx_update_bits(hdmirx_dev, DEFRAMER_CONFIG0,
++			   VS_REMAPFILTER_EN_QST | VS_FILTER_ORDER_QST_MASK,
++			   VS_REMAPFILTER_EN_QST | VS_FILTER_ORDER_QST(0x3));
++}
++
++static void hdmirx_set_negative_pol(struct snps_hdmirx_dev *hdmirx_dev, bool en)
++{
++	if (en) {
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6,
++				   VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN,
++				   VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN);
++		hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2,
++				   VPROC_VSYNC_POL_OVR_VALUE |
++				   VPROC_VSYNC_POL_OVR_EN |
++				   VPROC_HSYNC_POL_OVR_VALUE |
++				   VPROC_HSYNC_POL_OVR_EN,
++				   VPROC_VSYNC_POL_OVR_EN |
++				   VPROC_HSYNC_POL_OVR_EN);
++		return;
++	}
++
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6,
++			   VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN, 0);
++
++	hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2,
++			   VPROC_VSYNC_POL_OVR_VALUE |
++			   VPROC_VSYNC_POL_OVR_EN |
++			   VPROC_HSYNC_POL_OVR_VALUE |
++			   VPROC_HSYNC_POL_OVR_EN, 0);
++}
++
++static int hdmirx_try_to_get_timings(struct snps_hdmirx_dev *hdmirx_dev,
++				     struct v4l2_dv_timings *timings,
++				     int try_cnt)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	int i, cnt = 0, fail_cnt = 0, ret = 0;
++	bool from_dma = false;
++
++	hdmirx_set_negative_pol(hdmirx_dev, false);
++	for (i = 0; i < try_cnt; i++) {
++		ret = hdmirx_get_detected_timings(hdmirx_dev, timings, from_dma);
++		if (ret) {
++			cnt = 0;
++			fail_cnt++;
++			if (fail_cnt > 3) {
++				hdmirx_set_negative_pol(hdmirx_dev, true);
++				from_dma = true;
++			}
++		} else {
++			cnt++;
++		}
++		if (cnt >= 5)
++			break;
++
++		usleep_range(10 * 1000, 10 * 1100);
++	}
++
++	if (try_cnt > 8 && cnt < 5)
++		v4l2_dbg(1, debug, v4l2_dev, "%s: res not stable\n", __func__);
++
++	return ret;
++}
++
++static void hdmirx_format_change(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_dv_timings timings;
++	struct hdmirx_stream *stream = &hdmirx_dev->stream;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	const struct v4l2_event ev_src_chg = {
++		.type = V4L2_EVENT_SOURCE_CHANGE,
++		.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
++	};
++
++	if (hdmirx_try_to_get_timings(hdmirx_dev, &timings, 20)) {
++		queue_delayed_work(system_unbound_wq,
++				   &hdmirx_dev->delayed_work_hotplug,
++				   msecs_to_jiffies(20));
++		return;
++	}
++
++	hdmirx_dev->got_timing = true;
++	v4l2_dbg(1, debug, v4l2_dev, "%s: queue res_chg_event\n", __func__);
++	v4l2_event_queue(&stream->vdev, &ev_src_chg);
++}
++
++static void hdmirx_set_ddr_store_fmt(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	enum ddr_store_fmt store_fmt;
++	u32 dma_cfg1;
++
++	switch (hdmirx_dev->pix_fmt) {
++	case HDMIRX_RGB888:
++		store_fmt = STORE_RGB888;
++		break;
++	case HDMIRX_YUV444:
++		store_fmt = STORE_YUV444_8BIT;
++		break;
++	case HDMIRX_YUV422:
++		store_fmt = STORE_YUV422_8BIT;
++		break;
++	case HDMIRX_YUV420:
++		store_fmt = STORE_YUV420_8BIT;
++		break;
++	default:
++		store_fmt = STORE_RGB888;
++		break;
++	}
++
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG1,
++			   DDR_STORE_FORMAT_MASK, DDR_STORE_FORMAT(store_fmt));
++	dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1);
++	v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n",
++		 __func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1);
++}
++
++static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 mu_status, scdc_status, dma_st10, cmu_st;
++	u32 i;
++
++	for (i = 0; i < 300; i++) {
++		mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS);
++		scdc_status = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS3);
++		dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10);
++		cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS);
++
++		if ((mu_status & TMDSVALID_STABLE_ST) &&
++		    (dma_st10 & HDMIRX_LOCK) &&
++		    (cmu_st & TMDSQPCLK_LOCKED_ST))
++			break;
++
++		if (!tx_5v_power_present(hdmirx_dev)) {
++			v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__);
++			return -1;
++		}
++
++		hdmirx_tmds_clk_ratio_config(hdmirx_dev);
++	}
++
++	if (i == 300) {
++		v4l2_err(v4l2_dev, "%s: signal not lock, tmds_clk_ratio:%d\n",
++			 __func__, hdmirx_dev->tmds_clk_ratio);
++		v4l2_err(v4l2_dev, "%s: mu_st:%#x, scdc_st:%#x, dma_st10:%#x\n",
++			 __func__, mu_status, scdc_status, dma_st10);
++		return -1;
++	}
++
++	v4l2_info(v4l2_dev, "%s: signal lock ok, i:%d\n", __func__, i);
++	hdmirx_writel(hdmirx_dev, GLOBAL_SWRESET_REQUEST, DATAPATH_SWRESETREQ);
++
++	reinit_completion(&hdmirx_dev->avi_pkt_rcv);
++	hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N,
++			   PKTDEC_AVIIF_RCV_IRQ, PKTDEC_AVIIF_RCV_IRQ);
++
++	if (!wait_for_completion_timeout(&hdmirx_dev->avi_pkt_rcv,
++					 msecs_to_jiffies(300))) {
++		v4l2_err(v4l2_dev, "%s wait avi_pkt_rcv failed\n", __func__);
++		hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N,
++				   PKTDEC_AVIIF_RCV_IRQ, 0);
++	}
++
++	usleep_range(50 * 1000, 50 * 1010);
++	hdmirx_format_change(hdmirx_dev);
++
++	return 0;
++}
++
++static void hdmirx_dma_config(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	hdmirx_set_ddr_store_fmt(hdmirx_dev);
++
++	/* Note: uv_swap, rb can not swap, doc err*/
++	if (hdmirx_dev->cur_fmt_fourcc != V4L2_PIX_FMT_NV16)
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, RB_SWAP_EN, RB_SWAP_EN);
++	else
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, RB_SWAP_EN, 0);
++
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG7,
++			   LOCK_FRAME_NUM_MASK,
++			   LOCK_FRAME_NUM(2));
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG1,
++			   UV_WID_MASK | Y_WID_MASK | ABANDON_EN,
++			   UV_WID(1) | Y_WID(2) | ABANDON_EN);
++}
++
++static void hdmirx_submodule_init(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	/* Note: if not config HDCP2_CONFIG, there will be some errors; */
++	hdmirx_update_bits(hdmirx_dev, HDCP2_CONFIG,
++			   HDCP2_SWITCH_OVR_VALUE |
++			   HDCP2_SWITCH_OVR_EN,
++			   HDCP2_SWITCH_OVR_EN);
++	hdmirx_scdc_init(hdmirx_dev);
++	hdmirx_controller_init(hdmirx_dev);
++}
++
++static int hdmirx_enum_input(struct file *file, void *priv,
++			     struct v4l2_input *input)
++{
++	if (input->index > 0)
++		return -EINVAL;
++
++	input->type = V4L2_INPUT_TYPE_CAMERA;
++	input->std = 0;
++	strscpy(input->name, "HDMI IN", sizeof(input->name));
++	input->capabilities = V4L2_IN_CAP_DV_TIMINGS;
++
++	return 0;
++}
++
++static int hdmirx_get_input(struct file *file, void *priv, unsigned int *i)
++{
++	*i = 0;
++	return 0;
++}
++
++static int hdmirx_set_input(struct file *file, void *priv, unsigned int i)
++{
++	if (i)
++		return -EINVAL;
++	return 0;
++}
++
++static void hdmirx_set_fmt(struct hdmirx_stream *stream,
++			   struct v4l2_pix_format_mplane *pixm, bool try)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct v4l2_bt_timings *bt = &hdmirx_dev->timings.bt;
++	const struct v4l2_format_info *finfo;
++	unsigned int imagesize = 0;
++	int i;
++
++	memset(&pixm->plane_fmt[0], 0, sizeof(struct v4l2_plane_pix_format));
++	finfo = v4l2_format_info(pixm->pixelformat);
++	if (!finfo) {
++		finfo = v4l2_format_info(V4L2_PIX_FMT_BGR24);
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "%s: set_fmt:%#x not supported, use def_fmt:%x\n",
++			 __func__, pixm->pixelformat, finfo->format);
++	}
++
++	if (!bt->width || !bt->height)
++		v4l2_dbg(1, debug, v4l2_dev, "%s: invalid resolution:%#xx%#x\n",
++			 __func__, bt->width, bt->height);
++
++	pixm->pixelformat = finfo->format;
++	pixm->width = bt->width;
++	pixm->height = bt->height;
++	pixm->num_planes = finfo->mem_planes;
++	pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
++	pixm->colorspace = V4L2_COLORSPACE_SRGB;
++	pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++
++	if (bt->interlaced == V4L2_DV_INTERLACED)
++		pixm->field = V4L2_FIELD_INTERLACED_TB;
++	else
++		pixm->field = V4L2_FIELD_NONE;
++
++	memset(pixm->reserved, 0, sizeof(pixm->reserved));
++
++	v4l2_fill_pixfmt_mp(pixm, finfo->format, pixm->width, pixm->height);
++
++	for (i = 0; i < pixm->num_planes; i++) {
++		struct v4l2_plane_pix_format *plane_fmt;
++		int width, height, bpl, size, bpp = 0;
++
++		if (!i) {
++			width = pixm->width;
++			height = pixm->height;
++		} else {
++			width = pixm->width / finfo->hdiv;
++			height = pixm->height / finfo->vdiv;
++		}
++
++		switch (finfo->format) {
++		case V4L2_PIX_FMT_NV24:
++		case V4L2_PIX_FMT_NV16:
++		case V4L2_PIX_FMT_NV12:
++		case V4L2_PIX_FMT_BGR24:
++			bpp = finfo->bpp[i];
++			break;
++		default:
++			v4l2_dbg(1, debug, v4l2_dev,
++				 "fourcc: %#x is not supported\n",
++				 finfo->format);
++			break;
++		}
++
++		bpl = ALIGN(width * bpp, MEMORY_ALIGN_ROUND_UP_BYTES);
++		size = bpl * height;
++		imagesize += size;
++
++		if (finfo->mem_planes > i) {
++			/* Set bpl and size for each mplane */
++			plane_fmt = pixm->plane_fmt + i;
++			plane_fmt->bytesperline = bpl;
++			plane_fmt->sizeimage = size;
++		}
++
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "C-Plane %i size: %d, Total imagesize: %d\n",
++			 i, size, imagesize);
++	}
++
++	/* Convert to non-MPLANE format as we want to unify non-MPLANE and MPLANE */
++	if (finfo->mem_planes == 1)
++		pixm->plane_fmt[0].sizeimage = imagesize;
++
++	if (!try) {
++		stream->out_finfo = finfo;
++		stream->pixm = *pixm;
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "%s: req(%d, %d), out(%d, %d), fmt:%#x\n", __func__,
++			 pixm->width, pixm->height, stream->pixm.width,
++			 stream->pixm.height, finfo->format);
++	}
++}
++
++static int hdmirx_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
++					  struct v4l2_fmtdesc *f)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++
++	if (f->index >= 1)
++		return -EINVAL;
++
++	f->pixelformat = hdmirx_dev->cur_fmt_fourcc;
++
++	return 0;
++}
++
++static int hdmirx_s_fmt_vid_cap_mplane(struct file *file,
++				       void *priv, struct v4l2_format *f)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	if (vb2_is_busy(&stream->buf_queue)) {
++		v4l2_err(v4l2_dev, "%s: queue busy\n", __func__);
++		return -EBUSY;
++	}
++
++	hdmirx_set_fmt(stream, &f->fmt.pix_mp, false);
++
++	return 0;
++}
++
++static int hdmirx_g_fmt_vid_cap_mplane(struct file *file, void *fh,
++				       struct v4l2_format *f)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_pix_format_mplane pixm = {};
++
++	pixm.pixelformat = hdmirx_dev->cur_fmt_fourcc;
++	hdmirx_set_fmt(stream, &pixm, true);
++	f->fmt.pix_mp = pixm;
++
++	return 0;
++}
++
++static int hdmirx_g_dv_timings(struct file *file, void *_fh,
++			       struct v4l2_dv_timings *timings)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 dma_cfg1;
++
++	*timings = hdmirx_dev->timings;
++	dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1);
++	v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n",
++		 __func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1);
++
++	return 0;
++}
++
++static int hdmirx_s_dv_timings(struct file *file, void *_fh,
++			       struct v4l2_dv_timings *timings)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	if (!timings)
++		return -EINVAL;
++
++	if (debug)
++		v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name,
++				      "s_dv_timings: ", timings, false);
++
++	if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) {
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "%s: timings out of range\n", __func__);
++		return -ERANGE;
++	}
++
++	/* Check if the timings are part of the CEA-861 timings. */
++	v4l2_find_dv_timings_cap(timings, &hdmirx_timings_cap, 0, NULL, NULL);
++
++	if (v4l2_match_dv_timings(&hdmirx_dev->timings, timings, 0, false)) {
++		v4l2_dbg(1, debug, v4l2_dev, "%s: no change\n", __func__);
++		return 0;
++	}
++
++	/*
++	 * Changing the timings implies a format change, which is not allowed
++	 * while buffers for use with streaming have already been allocated.
++	 */
++	if (vb2_is_busy(&stream->buf_queue))
++		return -EBUSY;
++
++	hdmirx_dev->timings = *timings;
++	/* Update the internal format */
++	hdmirx_set_fmt(stream, &stream->pixm, false);
++
++	return 0;
++}
++
++static int hdmirx_querycap(struct file *file, void *priv,
++			   struct v4l2_capability *cap)
++{
++	struct hdmirx_stream *stream = video_drvdata(file);
++	struct device *dev = stream->hdmirx_dev->dev;
++
++	strscpy(cap->driver, dev->driver->name, sizeof(cap->driver));
++	strscpy(cap->card, dev->driver->name, sizeof(cap->card));
++
++	return 0;
++}
++
++static int hdmirx_queue_setup(struct vb2_queue *queue,
++			      unsigned int *num_buffers,
++			      unsigned int *num_planes,
++			      unsigned int sizes[],
++			      struct device *alloc_ctxs[])
++{
++	struct hdmirx_stream *stream = vb2_get_drv_priv(queue);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	const struct v4l2_pix_format_mplane *pixm = NULL;
++	const struct v4l2_format_info *out_finfo;
++	u32 i, height;
++
++	pixm = &stream->pixm;
++	out_finfo = stream->out_finfo;
++
++	if (!num_planes || !out_finfo) {
++		v4l2_err(v4l2_dev, "%s: out_fmt not set\n", __func__);
++		return -EINVAL;
++	}
++
++	if (*num_planes) {
++		if (*num_planes != pixm->num_planes)
++			return -EINVAL;
++
++		for (i = 0; i < *num_planes; i++)
++			if (sizes[i] < pixm->plane_fmt[i].sizeimage)
++				return -EINVAL;
++		return 0;
++	}
++
++	*num_planes = out_finfo->mem_planes;
++	height = pixm->height;
++
++	for (i = 0; i < out_finfo->mem_planes; i++)
++		sizes[i] = pixm->plane_fmt[i].sizeimage;
++
++	v4l2_dbg(1, debug, v4l2_dev, "%s: count %d, size %d\n",
++		 v4l2_type_names[queue->type], *num_buffers, sizes[0]);
++
++	return 0;
++}
++
++/*
++ * The vb2_buffer are stored in hdmirx_buffer, in order to unify
++ * mplane buffer and none-mplane buffer.
++ */
++static void hdmirx_buf_queue(struct vb2_buffer *vb)
++{
++	const struct v4l2_format_info *out_finfo;
++	struct vb2_v4l2_buffer *vbuf;
++	struct hdmirx_buffer *hdmirx_buf;
++	struct vb2_queue *queue;
++	struct hdmirx_stream *stream;
++	const struct v4l2_pix_format_mplane *pixm;
++	unsigned long lock_flags = 0;
++	int i;
++
++	vbuf = to_vb2_v4l2_buffer(vb);
++	hdmirx_buf = container_of(vbuf, struct hdmirx_buffer, vb);
++	queue = vb->vb2_queue;
++	stream = vb2_get_drv_priv(queue);
++	pixm = &stream->pixm;
++	out_finfo = stream->out_finfo;
++
++	memset(hdmirx_buf->buff_addr, 0, sizeof(hdmirx_buf->buff_addr));
++
++	/*
++	 * If mplanes > 1, every c-plane has its own m-plane,
++	 * otherwise, multiple c-planes are in the same m-plane
++	 */
++	for (i = 0; i < out_finfo->mem_planes; i++)
++		hdmirx_buf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
++
++	if (out_finfo->mem_planes == 1) {
++		if (out_finfo->comp_planes == 1) {
++			hdmirx_buf->buff_addr[HDMIRX_PLANE_CBCR] =
++				hdmirx_buf->buff_addr[HDMIRX_PLANE_Y];
++		} else {
++			for (i = 0; i < out_finfo->comp_planes - 1; i++)
++				hdmirx_buf->buff_addr[i + 1] =
++					hdmirx_buf->buff_addr[i] +
++					pixm->plane_fmt[i].bytesperline *
++					pixm->height;
++		}
++	}
++
++	spin_lock_irqsave(&stream->vbq_lock, lock_flags);
++	list_add_tail(&hdmirx_buf->queue, &stream->buf_head);
++	spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
++}
++
++static void return_all_buffers(struct hdmirx_stream *stream,
++			       enum vb2_buffer_state state)
++{
++	struct hdmirx_buffer *buf;
++	unsigned long flags;
++
++	spin_lock_irqsave(&stream->vbq_lock, flags);
++	if (stream->curr_buf)
++		list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
++	if (stream->next_buf && stream->next_buf != stream->curr_buf)
++		list_add_tail(&stream->next_buf->queue, &stream->buf_head);
++	stream->curr_buf = NULL;
++	stream->next_buf = NULL;
++
++	while (!list_empty(&stream->buf_head)) {
++		buf = list_first_entry(&stream->buf_head,
++				       struct hdmirx_buffer, queue);
++		list_del(&buf->queue);
++		spin_unlock_irqrestore(&stream->vbq_lock, flags);
++		vb2_buffer_done(&buf->vb.vb2_buf, state);
++		spin_lock_irqsave(&stream->vbq_lock, flags);
++	}
++	spin_unlock_irqrestore(&stream->vbq_lock, flags);
++}
++
++static void hdmirx_stop_streaming(struct vb2_queue *queue)
++{
++	struct hdmirx_stream *stream = vb2_get_drv_priv(queue);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	int ret;
++
++	v4l2_info(v4l2_dev, "stream start stopping\n");
++	mutex_lock(&hdmirx_dev->stream_lock);
++	WRITE_ONCE(stream->stopping, true);
++
++	/* wait last irq to return the buffer */
++	ret = wait_event_timeout(stream->wq_stopped, !stream->stopping,
++				 msecs_to_jiffies(500));
++	if (!ret) {
++		v4l2_err(v4l2_dev, "%s: timeout waiting last irq\n",
++			 __func__);
++		WRITE_ONCE(stream->stopping, false);
++	}
++
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
++	return_all_buffers(stream, VB2_BUF_STATE_ERROR);
++	mutex_unlock(&hdmirx_dev->stream_lock);
++	v4l2_info(v4l2_dev, "stream stopping finished\n");
++}
++
++static int hdmirx_start_streaming(struct vb2_queue *queue, unsigned int count)
++{
++	struct hdmirx_stream *stream = vb2_get_drv_priv(queue);
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct v4l2_dv_timings timings = hdmirx_dev->timings;
++	struct v4l2_bt_timings *bt = &timings.bt;
++	unsigned long lock_flags = 0;
++	int line_flag;
++
++	if (!hdmirx_dev->got_timing) {
++		v4l2_dbg(1, debug, v4l2_dev, "timing is invalid\n");
++		return 0;
++	}
++
++	mutex_lock(&hdmirx_dev->stream_lock);
++	stream->frame_idx = 0;
++	stream->line_flag_int_cnt = 0;
++	stream->curr_buf = NULL;
++	stream->next_buf = NULL;
++	stream->irq_stat = 0;
++	queue->min_queued_buffers = 1;
++
++	WRITE_ONCE(stream->stopping, false);
++
++	spin_lock_irqsave(&stream->vbq_lock, lock_flags);
++	if (!stream->curr_buf) {
++		if (!list_empty(&stream->buf_head)) {
++			stream->curr_buf = list_first_entry(&stream->buf_head,
++							    struct hdmirx_buffer,
++							    queue);
++			list_del(&stream->curr_buf->queue);
++		} else {
++			stream->curr_buf = NULL;
++		}
++	}
++	spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
++
++	v4l2_dbg(2, debug, v4l2_dev,
++		 "%s: start_stream cur_buf y_addr:%#x, uv_addr:%#x\n",
++		 __func__, stream->curr_buf->buff_addr[HDMIRX_PLANE_Y],
++		 stream->curr_buf->buff_addr[HDMIRX_PLANE_CBCR]);
++	hdmirx_writel(hdmirx_dev, DMA_CONFIG2,
++		      stream->curr_buf->buff_addr[HDMIRX_PLANE_Y]);
++	hdmirx_writel(hdmirx_dev, DMA_CONFIG3,
++		      stream->curr_buf->buff_addr[HDMIRX_PLANE_CBCR]);
++
++	if (bt->height) {
++		if (bt->interlaced == V4L2_DV_INTERLACED)
++			line_flag = bt->height / 4;
++		else
++			line_flag = bt->height / 2;
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG7,
++				   LINE_FLAG_NUM_MASK,
++				   LINE_FLAG_NUM(line_flag));
++	} else {
++		v4l2_err(v4l2_dev, "height err: %d\n", bt->height);
++	}
++
++	hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
++	hdmirx_writel(hdmirx_dev, CED_DYN_CONTROL, 0x1);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
++			   LINE_FLAG_INT_EN |
++			   HDMIRX_DMA_IDLE_INT |
++			   HDMIRX_LOCK_DISABLE_INT |
++			   LAST_FRAME_AXI_UNFINISH_INT_EN |
++			   FIFO_OVERFLOW_INT_EN |
++			   FIFO_UNDERFLOW_INT_EN |
++			   HDMIRX_AXI_ERROR_INT_EN,
++			   LINE_FLAG_INT_EN |
++			   HDMIRX_DMA_IDLE_INT |
++			   HDMIRX_LOCK_DISABLE_INT |
++			   LAST_FRAME_AXI_UNFINISH_INT_EN |
++			   FIFO_OVERFLOW_INT_EN |
++			   FIFO_UNDERFLOW_INT_EN |
++			   HDMIRX_AXI_ERROR_INT_EN);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, HDMIRX_DMA_EN);
++	v4l2_dbg(1, debug, v4l2_dev, "%s: enable dma", __func__);
++	mutex_unlock(&hdmirx_dev->stream_lock);
++
++	return 0;
++}
++
++/* vb2 queue */
++static const struct vb2_ops hdmirx_vb2_ops = {
++	.queue_setup = hdmirx_queue_setup,
++	.buf_queue = hdmirx_buf_queue,
++	.wait_prepare = vb2_ops_wait_prepare,
++	.wait_finish = vb2_ops_wait_finish,
++	.stop_streaming = hdmirx_stop_streaming,
++	.start_streaming = hdmirx_start_streaming,
++};
++
++static int hdmirx_init_vb2_queue(struct vb2_queue *q,
++				 struct hdmirx_stream *stream,
++				 enum v4l2_buf_type buf_type)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++
++	q->type = buf_type;
++	q->io_modes = VB2_MMAP | VB2_DMABUF;
++	q->drv_priv = stream;
++	q->ops = &hdmirx_vb2_ops;
++	q->mem_ops = &vb2_dma_contig_memops;
++	q->buf_struct_size = sizeof(struct hdmirx_buffer);
++	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++	q->lock = &stream->vlock;
++	q->dev = hdmirx_dev->dev;
++	/*
++	 * rk3588 doesn't use iommu and works only with dma buffers
++	 * that are physically contiguous in memory.
++	 */
++	q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
++	return vb2_queue_init(q);
++}
++
++/* video device */
++static const struct v4l2_ioctl_ops hdmirx_v4l2_ioctl_ops = {
++	.vidioc_querycap = hdmirx_querycap,
++	.vidioc_try_fmt_vid_cap_mplane = hdmirx_g_fmt_vid_cap_mplane,
++	.vidioc_s_fmt_vid_cap_mplane = hdmirx_s_fmt_vid_cap_mplane,
++	.vidioc_g_fmt_vid_cap_mplane = hdmirx_g_fmt_vid_cap_mplane,
++	.vidioc_enum_fmt_vid_cap = hdmirx_enum_fmt_vid_cap_mplane,
++
++	.vidioc_s_dv_timings = hdmirx_s_dv_timings,
++	.vidioc_g_dv_timings = hdmirx_g_dv_timings,
++	.vidioc_enum_dv_timings = hdmirx_enum_dv_timings,
++	.vidioc_query_dv_timings = hdmirx_query_dv_timings,
++	.vidioc_dv_timings_cap = hdmirx_dv_timings_cap,
++	.vidioc_enum_input = hdmirx_enum_input,
++	.vidioc_g_input = hdmirx_get_input,
++	.vidioc_s_input = hdmirx_set_input,
++	.vidioc_g_edid = hdmirx_get_edid,
++	.vidioc_s_edid = hdmirx_set_edid,
++	.vidioc_g_parm = hdmirx_g_parm,
++
++	.vidioc_reqbufs = vb2_ioctl_reqbufs,
++	.vidioc_querybuf = vb2_ioctl_querybuf,
++	.vidioc_create_bufs = vb2_ioctl_create_bufs,
++	.vidioc_qbuf = vb2_ioctl_qbuf,
++	.vidioc_expbuf = vb2_ioctl_expbuf,
++	.vidioc_dqbuf = vb2_ioctl_dqbuf,
++	.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
++	.vidioc_streamon = vb2_ioctl_streamon,
++	.vidioc_streamoff = vb2_ioctl_streamoff,
++
++	.vidioc_log_status = v4l2_ctrl_log_status,
++	.vidioc_subscribe_event = hdmirx_subscribe_event,
++	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
++};
++
++static const struct v4l2_file_operations hdmirx_fops = {
++	.owner = THIS_MODULE,
++	.open = v4l2_fh_open,
++	.release = vb2_fop_release,
++	.unlocked_ioctl = video_ioctl2,
++	.poll = vb2_fop_poll,
++	.mmap = vb2_fop_mmap,
++};
++
++static int hdmirx_register_stream_vdev(struct hdmirx_stream *stream)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct video_device *vdev = &stream->vdev;
++	int ret = 0;
++
++	strscpy(vdev->name, "stream_hdmirx", sizeof(vdev->name));
++	INIT_LIST_HEAD(&stream->buf_head);
++	spin_lock_init(&stream->vbq_lock);
++	mutex_init(&stream->vlock);
++	init_waitqueue_head(&stream->wq_stopped);
++	stream->curr_buf = NULL;
++	stream->next_buf = NULL;
++
++	vdev->ioctl_ops = &hdmirx_v4l2_ioctl_ops;
++	vdev->release = video_device_release_empty;
++	vdev->fops = &hdmirx_fops;
++	vdev->minor = -1;
++	vdev->v4l2_dev = v4l2_dev;
++	vdev->lock = &stream->vlock;
++	vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
++			    V4L2_CAP_STREAMING;
++	video_set_drvdata(vdev, stream);
++	vdev->vfl_dir = VFL_DIR_RX;
++
++	hdmirx_init_vb2_queue(&stream->buf_queue, stream,
++			      V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
++	vdev->queue = &stream->buf_queue;
++
++	ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
++	if (ret < 0) {
++		v4l2_err(v4l2_dev, "video_register_device failed: %d\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static void process_signal_change(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
++	hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
++			   LINE_FLAG_INT_EN |
++			   HDMIRX_DMA_IDLE_INT |
++			   HDMIRX_LOCK_DISABLE_INT |
++			   LAST_FRAME_AXI_UNFINISH_INT_EN |
++			   FIFO_OVERFLOW_INT_EN |
++			   FIFO_UNDERFLOW_INT_EN |
++			   HDMIRX_AXI_ERROR_INT_EN, 0);
++	hdmirx_reset_dma(hdmirx_dev);
++	hdmirx_dev->got_timing = false;
++	queue_delayed_work(system_unbound_wq,
++			   &hdmirx_dev->delayed_work_res_change,
++			   msecs_to_jiffies(50));
++}
++
++static void avpunit_0_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				  int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	if (status & (CED_DYN_CNT_CH2_IRQ |
++		      CED_DYN_CNT_CH1_IRQ |
++		      CED_DYN_CNT_CH0_IRQ)) {
++		process_signal_change(hdmirx_dev);
++		v4l2_dbg(2, debug, v4l2_dev, "%s: avp0_st:%#x\n",
++			 __func__, status);
++		*handled = true;
++	}
++
++	hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_FORCE, 0x0);
++}
++
++static void avpunit_1_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				  int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	if (status & DEFRAMER_VSYNC_THR_REACHED_IRQ) {
++		v4l2_info(v4l2_dev, "Vertical Sync threshold reached interrupt %#x", status);
++		hdmirx_update_bits(hdmirx_dev, AVPUNIT_1_INT_MASK_N,
++				   DEFRAMER_VSYNC_THR_REACHED_MASK_N, 0);
++		*handled = true;
++	}
++}
++
++static void mainunit_0_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				   int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	v4l2_dbg(2, debug, v4l2_dev, "mu0_st:%#x\n", status);
++	if (status & TIMER_BASE_LOCKED_IRQ) {
++		hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N,
++				   TIMER_BASE_LOCKED_IRQ, 0);
++		complete(&hdmirx_dev->timer_base_lock);
++		*handled = true;
++	}
++
++	if (status & TMDSQPCLK_OFF_CHG) {
++		process_signal_change(hdmirx_dev);
++		v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSQPCLK_OFF_CHG\n", __func__);
++		*handled = true;
++	}
++
++	if (status & TMDSQPCLK_LOCKED_CHG) {
++		process_signal_change(hdmirx_dev);
++		v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSQPCLK_LOCKED_CHG\n", __func__);
++		*handled = true;
++	}
++
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_FORCE, 0x0);
++}
++
++static void mainunit_2_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				   int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	v4l2_dbg(2, debug, v4l2_dev, "mu2_st:%#x\n", status);
++	if (status & PHYCREG_CR_WRITE_DONE) {
++		hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
++				   PHYCREG_CR_WRITE_DONE, 0);
++		complete(&hdmirx_dev->cr_write_done);
++		*handled = true;
++	}
++
++	if (status & TMDSVALID_STABLE_CHG) {
++		process_signal_change(hdmirx_dev);
++		v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSVALID_STABLE_CHG\n", __func__);
++		*handled = true;
++	}
++
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_FORCE, 0x0);
++}
++
++static void pkt_2_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++			      int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	v4l2_dbg(2, debug, v4l2_dev, "%s: pk2_st:%#x\n", __func__, status);
++	if (status & PKTDEC_AVIIF_RCV_IRQ) {
++		hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N,
++				   PKTDEC_AVIIF_RCV_IRQ, 0);
++		complete(&hdmirx_dev->avi_pkt_rcv);
++		v4l2_dbg(2, debug, v4l2_dev, "%s: AVIIF_RCV_IRQ\n", __func__);
++		*handled = true;
++	}
++
++	hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff);
++}
++
++static void scdc_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++			     int status, bool *handled)
++{
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	v4l2_dbg(2, debug, v4l2_dev, "%s: scdc_st:%#x\n", __func__, status);
++	if (status & SCDCTMDSCCFG_CHG) {
++		hdmirx_tmds_clk_ratio_config(hdmirx_dev);
++		*handled = true;
++	}
++
++	hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff);
++}
++
++static irqreturn_t hdmirx_hdmi_irq_handler(int irq, void *dev_id)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_id;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct arm_smccc_res res;
++	u32 mu0_st, mu2_st, pk2_st, scdc_st, avp1_st, avp0_st;
++	u32 mu0_mask, mu2_mask, pk2_mask, scdc_mask, avp1_msk, avp0_msk;
++	bool handled = false;
++
++	mu0_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_MASK_N);
++	mu2_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_MASK_N);
++	pk2_mask = hdmirx_readl(hdmirx_dev, PKT_2_INT_MASK_N);
++	scdc_mask = hdmirx_readl(hdmirx_dev, SCDC_INT_MASK_N);
++	mu0_st = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_STATUS);
++	mu2_st = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_STATUS);
++	pk2_st = hdmirx_readl(hdmirx_dev, PKT_2_INT_STATUS);
++	scdc_st = hdmirx_readl(hdmirx_dev, SCDC_INT_STATUS);
++	avp0_st = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_STATUS);
++	avp1_st = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_STATUS);
++	avp0_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_MASK_N);
++	avp1_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_MASK_N);
++	mu0_st &= mu0_mask;
++	mu2_st &= mu2_mask;
++	pk2_st &= pk2_mask;
++	avp1_st &= avp1_msk;
++	avp0_st &= avp0_msk;
++	scdc_st &= scdc_mask;
++
++	if (avp0_st)
++		avpunit_0_int_handler(hdmirx_dev, avp0_st, &handled);
++	if (avp1_st)
++		avpunit_1_int_handler(hdmirx_dev, avp1_st, &handled);
++	if (mu0_st)
++		mainunit_0_int_handler(hdmirx_dev, mu0_st, &handled);
++	if (mu2_st)
++		mainunit_2_int_handler(hdmirx_dev, mu2_st, &handled);
++	if (pk2_st)
++		pkt_2_int_handler(hdmirx_dev, pk2_st, &handled);
++	if (scdc_st)
++		scdc_int_handler(hdmirx_dev, scdc_st, &handled);
++
++	if (!handled) {
++		v4l2_dbg(2, debug, v4l2_dev, "%s: hdmi irq not handled", __func__);
++		v4l2_dbg(2, debug, v4l2_dev,
++			 "avp0:%#x, avp1:%#x, mu0:%#x, mu2:%#x, pk2:%#x, scdc:%#x\n",
++			 avp0_st, avp1_st, mu0_st, mu2_st, pk2_st, scdc_st);
++	}
++
++	v4l2_dbg(2, debug, v4l2_dev, "%s: en_fiq", __func__);
++	arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN,
++		      RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res);
++
++	return handled ? IRQ_HANDLED : IRQ_NONE;
++}
++
++static void hdmirx_vb_done(struct hdmirx_stream *stream,
++			   struct vb2_v4l2_buffer *vb_done)
++{
++	const struct v4l2_format_info *finfo = stream->out_finfo;
++	u32 i;
++
++	/* Dequeue a filled buffer */
++	for (i = 0; i < finfo->mem_planes; i++) {
++		vb2_set_plane_payload(&vb_done->vb2_buf, i,
++				      stream->pixm.plane_fmt[i].sizeimage);
++	}
++
++	vb_done->vb2_buf.timestamp = ktime_get_ns();
++	vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
++}
++
++static void dma_idle_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				 bool *handled)
++{
++	struct hdmirx_stream *stream = &hdmirx_dev->stream;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct v4l2_dv_timings timings = hdmirx_dev->timings;
++	struct v4l2_bt_timings *bt = &timings.bt;
++	struct vb2_v4l2_buffer *vb_done = NULL;
++
++	if (!(stream->irq_stat) && !(stream->irq_stat & LINE_FLAG_INT_EN))
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "%s: last time have no line_flag_irq\n", __func__);
++
++	if (stream->line_flag_int_cnt <= FILTER_FRAME_CNT)
++		goto DMA_IDLE_OUT;
++
++	if (bt->interlaced != V4L2_DV_INTERLACED ||
++	    !(stream->line_flag_int_cnt % 2)) {
++		if (stream->next_buf) {
++			if (stream->curr_buf)
++				vb_done = &stream->curr_buf->vb;
++
++			if (vb_done) {
++				vb_done->vb2_buf.timestamp = ktime_get_ns();
++				vb_done->sequence = stream->frame_idx;
++				hdmirx_vb_done(stream, vb_done);
++				stream->frame_idx++;
++				if (stream->frame_idx == 30)
++					v4l2_info(v4l2_dev, "rcv frames\n");
++			}
++
++			stream->curr_buf = NULL;
++			if (stream->next_buf) {
++				stream->curr_buf = stream->next_buf;
++				stream->next_buf = NULL;
++			}
++		} else {
++			v4l2_dbg(3, debug, v4l2_dev,
++				 "%s: next_buf NULL, skip vb_done\n", __func__);
++		}
++	}
++
++DMA_IDLE_OUT:
++	*handled = true;
++}
++
++static void line_flag_int_handler(struct snps_hdmirx_dev *hdmirx_dev,
++				  bool *handled)
++{
++	struct hdmirx_stream *stream = &hdmirx_dev->stream;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	struct v4l2_dv_timings timings = hdmirx_dev->timings;
++	struct v4l2_bt_timings *bt = &timings.bt;
++	u32 dma_cfg6;
++
++	stream->line_flag_int_cnt++;
++	if (!(stream->irq_stat) && !(stream->irq_stat & HDMIRX_DMA_IDLE_INT))
++		v4l2_dbg(1, debug, v4l2_dev,
++			 "%s: last have no dma_idle_irq\n", __func__);
++	dma_cfg6 = hdmirx_readl(hdmirx_dev, DMA_CONFIG6);
++	if (!(dma_cfg6 & HDMIRX_DMA_EN)) {
++		v4l2_dbg(2, debug, v4l2_dev, "%s: dma not on\n", __func__);
++		goto LINE_FLAG_OUT;
++	}
++
++	if (stream->line_flag_int_cnt <= FILTER_FRAME_CNT)
++		goto LINE_FLAG_OUT;
++
++	if (bt->interlaced != V4L2_DV_INTERLACED ||
++	    !(stream->line_flag_int_cnt % 2)) {
++		if (!stream->next_buf) {
++			spin_lock(&stream->vbq_lock);
++			if (!list_empty(&stream->buf_head)) {
++				stream->next_buf = list_first_entry(&stream->buf_head,
++								    struct hdmirx_buffer,
++								    queue);
++				list_del(&stream->next_buf->queue);
++			} else {
++				stream->next_buf = NULL;
++			}
++			spin_unlock(&stream->vbq_lock);
++
++			if (stream->next_buf) {
++				hdmirx_writel(hdmirx_dev, DMA_CONFIG2,
++					      stream->next_buf->buff_addr[HDMIRX_PLANE_Y]);
++				hdmirx_writel(hdmirx_dev, DMA_CONFIG3,
++					      stream->next_buf->buff_addr[HDMIRX_PLANE_CBCR]);
++			} else {
++				v4l2_dbg(3, debug, v4l2_dev,
++					 "%s: no buffer is available\n", __func__);
++			}
++		}
++	} else {
++		v4l2_dbg(3, debug, v4l2_dev, "%s: interlace:%d, line_flag_int_cnt:%d\n",
++			 __func__, bt->interlaced, stream->line_flag_int_cnt);
++	}
++
++LINE_FLAG_OUT:
++	*handled = true;
++}
++
++static irqreturn_t hdmirx_dma_irq_handler(int irq, void *dev_id)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_id;
++	struct hdmirx_stream *stream = &hdmirx_dev->stream;
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	u32 dma_stat1, dma_stat13;
++	bool handled = false;
++
++	dma_stat1 = hdmirx_readl(hdmirx_dev, DMA_STATUS1);
++	dma_stat13 = hdmirx_readl(hdmirx_dev, DMA_STATUS13);
++	v4l2_dbg(3, debug, v4l2_dev, "dma_irq st1:%#x, st13:%d\n",
++		 dma_stat1, dma_stat13);
++
++	if (READ_ONCE(stream->stopping)) {
++		v4l2_dbg(1, debug, v4l2_dev, "%s: stop stream\n", __func__);
++		hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
++		hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
++				   LINE_FLAG_INT_EN |
++				   HDMIRX_DMA_IDLE_INT |
++				   HDMIRX_LOCK_DISABLE_INT |
++				   LAST_FRAME_AXI_UNFINISH_INT_EN |
++				   FIFO_OVERFLOW_INT_EN |
++				   FIFO_UNDERFLOW_INT_EN |
++				   HDMIRX_AXI_ERROR_INT_EN, 0);
++		WRITE_ONCE(stream->stopping, false);
++		wake_up(&stream->wq_stopped);
++		return IRQ_HANDLED;
++	}
++
++	if (dma_stat1 & HDMIRX_DMA_IDLE_INT)
++		dma_idle_int_handler(hdmirx_dev, &handled);
++
++	if (dma_stat1 & LINE_FLAG_INT_EN)
++		line_flag_int_handler(hdmirx_dev, &handled);
++
++	if (!handled)
++		v4l2_dbg(3, debug, v4l2_dev,
++			 "%s: dma irq not handled, dma_stat1:%#x\n",
++			 __func__, dma_stat1);
++
++	stream->irq_stat = dma_stat1;
++	hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
++
++	return IRQ_HANDLED;
++}
++
++static void hdmirx_plugin(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct arm_smccc_res res;
++	int ret;
++
++	queue_delayed_work(system_unbound_wq,
++			   &hdmirx_dev->delayed_work_heartbeat,
++			   msecs_to_jiffies(10));
++	arm_smccc_smc(SIP_WDT_CFG, WDT_START, 0, 0, 0, 0, 0, 0, &res);
++	hdmirx_submodule_init(hdmirx_dev);
++	hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED,
++			   POWERPROVIDED);
++	hdmirx_hpd_ctrl(hdmirx_dev, true);
++	hdmirx_phy_config(hdmirx_dev);
++	ret = hdmirx_wait_lock_and_get_timing(hdmirx_dev);
++	if (ret) {
++		hdmirx_plugout(hdmirx_dev);
++		queue_delayed_work(system_unbound_wq,
++				   &hdmirx_dev->delayed_work_hotplug,
++				   msecs_to_jiffies(200));
++		return;
++	}
++	hdmirx_dma_config(hdmirx_dev);
++	hdmirx_interrupts_setup(hdmirx_dev, true);
++}
++
++static void hdmirx_delayed_work_hotplug(struct work_struct *work)
++{
++	struct snps_hdmirx_dev *hdmirx_dev;
++	bool plugin;
++
++	hdmirx_dev = container_of(work, struct snps_hdmirx_dev,
++				  delayed_work_hotplug.work);
++
++	mutex_lock(&hdmirx_dev->work_lock);
++	hdmirx_dev->got_timing = false;
++	plugin = tx_5v_power_present(hdmirx_dev);
++	v4l2_ctrl_s_ctrl(hdmirx_dev->detect_tx_5v_ctrl, plugin);
++	v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: plugin:%d\n",
++		 __func__, plugin);
++
++	if (plugin)
++		hdmirx_plugin(hdmirx_dev);
++	else
++		hdmirx_plugout(hdmirx_dev);
++
++	mutex_unlock(&hdmirx_dev->work_lock);
++}
++
++static void hdmirx_delayed_work_res_change(struct work_struct *work)
++{
++	struct snps_hdmirx_dev *hdmirx_dev;
++	bool plugin;
++
++	hdmirx_dev = container_of(work, struct snps_hdmirx_dev,
++				  delayed_work_res_change.work);
++
++	mutex_lock(&hdmirx_dev->work_lock);
++	plugin = tx_5v_power_present(hdmirx_dev);
++	v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: plugin:%d\n",
++		 __func__, plugin);
++	if (plugin) {
++		hdmirx_interrupts_setup(hdmirx_dev, false);
++		hdmirx_submodule_init(hdmirx_dev);
++		hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED,
++				   POWERPROVIDED);
++		hdmirx_hpd_ctrl(hdmirx_dev, true);
++		hdmirx_phy_config(hdmirx_dev);
++
++		if (hdmirx_wait_lock_and_get_timing(hdmirx_dev)) {
++			hdmirx_plugout(hdmirx_dev);
++			queue_delayed_work(system_unbound_wq,
++					   &hdmirx_dev->delayed_work_hotplug,
++					   msecs_to_jiffies(200));
++		} else {
++			hdmirx_dma_config(hdmirx_dev);
++			hdmirx_interrupts_setup(hdmirx_dev, true);
++		}
++	}
++	mutex_unlock(&hdmirx_dev->work_lock);
++}
++
++static void hdmirx_delayed_work_heartbeat(struct work_struct *work)
++{
++	struct delayed_work *dwork = to_delayed_work(work);
++	struct snps_hdmirx_dev *hdmirx_dev = container_of(dwork,
++							struct snps_hdmirx_dev,
++							delayed_work_heartbeat);
++
++	queue_work(system_highpri_wq, &hdmirx_dev->work_wdt_config);
++	queue_delayed_work(system_unbound_wq,
++			   &hdmirx_dev->delayed_work_heartbeat, HZ);
++}
++
++static void hdmirx_work_wdt_config(struct work_struct *work)
++{
++	struct arm_smccc_res res;
++	struct snps_hdmirx_dev *hdmirx_dev = container_of(work,
++							struct snps_hdmirx_dev,
++							work_wdt_config);
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	arm_smccc_smc(SIP_WDT_CFG, WDT_PING, 0, 0, 0, 0, 0, 0, &res);
++	v4l2_dbg(3, debug, v4l2_dev, "hb\n");
++}
++
++static irqreturn_t hdmirx_5v_det_irq_handler(int irq, void *dev_id)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_id;
++	u32 val;
++
++	val = gpiod_get_value(hdmirx_dev->detect_5v_gpio);
++	v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: 5v:%d\n", __func__, val);
++
++	queue_delayed_work(system_unbound_wq,
++			   &hdmirx_dev->delayed_work_hotplug,
++			   msecs_to_jiffies(10));
++
++	return IRQ_HANDLED;
++}
++
++static const struct hdmirx_cec_ops hdmirx_cec_ops = {
++	.write = hdmirx_writel,
++	.read = hdmirx_readl,
++};
++
++static int hdmirx_parse_dt(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	struct device *dev = hdmirx_dev->dev;
++	int ret;
++
++	hdmirx_dev->num_clks = devm_clk_bulk_get_all(dev, &hdmirx_dev->clks);
++	if (hdmirx_dev->num_clks < 1)
++		return -ENODEV;
++
++	hdmirx_dev->resets[HDMIRX_RST_A].id = "axi";
++	hdmirx_dev->resets[HDMIRX_RST_P].id = "apb";
++	hdmirx_dev->resets[HDMIRX_RST_REF].id = "ref";
++	hdmirx_dev->resets[HDMIRX_RST_BIU].id = "biu";
++
++	ret = devm_reset_control_bulk_get_exclusive(dev, HDMIRX_NUM_RST,
++						    hdmirx_dev->resets);
++	if (ret < 0) {
++		dev_err(dev, "failed to get reset controls\n");
++		return ret;
++	}
++
++	hdmirx_dev->detect_5v_gpio =
++		devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
++
++	if (IS_ERR(hdmirx_dev->detect_5v_gpio)) {
++		dev_err(dev, "failed to get hdmirx hot plug detection gpio\n");
++		return PTR_ERR(hdmirx_dev->detect_5v_gpio);
++	}
++
++	hdmirx_dev->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
++							  "rockchip,grf");
++	if (IS_ERR(hdmirx_dev->grf)) {
++		dev_err(dev, "failed to get rockchip,grf\n");
++		return PTR_ERR(hdmirx_dev->grf);
++	}
++
++	hdmirx_dev->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
++							      "rockchip,vo1-grf");
++	if (IS_ERR(hdmirx_dev->vo1_grf)) {
++		dev_err(dev, "failed to get rockchip,vo1-grf\n");
++		return PTR_ERR(hdmirx_dev->vo1_grf);
++	}
++
++	hdmirx_dev->hpd_trigger_level = !device_property_read_bool(dev, "hpd-is-active-low");
++
++	ret = of_reserved_mem_device_init(dev);
++	if (ret)
++		dev_warn(dev, "No reserved memory for HDMIRX, use default CMA\n");
++
++	return 0;
++}
++
++static void hdmirx_disable_all_interrupts(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, MAINUNIT_1_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, AVPUNIT_1_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, PKT_0_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, PKT_1_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, PKT_2_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, SCDC_INT_MASK_N, 0);
++	hdmirx_writel(hdmirx_dev, CEC_INT_MASK_N, 0);
++
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_1_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_1_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, PKT_0_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, PKT_1_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, HDCP_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, HDCP_1_INT_CLEAR, 0xffffffff);
++	hdmirx_clear_interrupt(hdmirx_dev, CEC_INT_CLEAR, 0xffffffff);
++}
++
++static int hdmirx_init(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET | PHY_PDDQ, 0);
++
++	regmap_write(hdmirx_dev->vo1_grf, VO1_GRF_VO1_CON2,
++		     (HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) |
++		     ((HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) << 16));
++	/*
++	 * Some interrupts are enabled by default, so we disable
++	 * all interrupts and clear interrupts status first.
++	 */
++	hdmirx_disable_all_interrupts(hdmirx_dev);
++
++	return 0;
++}
++
++static void hdmirx_load_default_edid(struct snps_hdmirx_dev *hdmirx_dev)
++{
++	int ret;
++	struct v4l2_edid def_edid;
++
++	hdmirx_hpd_ctrl(hdmirx_dev, false);
++
++	/* disable hpd and write edid */
++	def_edid.pad = 0;
++	def_edid.start_block = 0;
++	def_edid.blocks = EDID_NUM_BLOCKS_MAX;
++
++	if (IS_ENABLED(CONFIG_HDMIRX_LOAD_DEFAULT_EDID))
++		def_edid.edid = edid_init_data_340M;
++	else
++		def_edid.edid = hdmirx_dev->edid;
++
++	ret = hdmirx_write_edid(hdmirx_dev, &def_edid, true);
++	if (ret)
++		dev_err(hdmirx_dev->dev, "%s: write edid failed\n", __func__);
++}
++
++static void hdmirx_disable_irq(struct device *dev)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
++	struct arm_smccc_res res;
++
++	disable_irq(hdmirx_dev->hdmi_irq);
++	disable_irq(hdmirx_dev->dma_irq);
++	disable_irq(hdmirx_dev->det_irq);
++
++	arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_DIS,
++		      RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res);
++
++	cancel_delayed_work_sync(&hdmirx_dev->delayed_work_hotplug);
++	cancel_delayed_work_sync(&hdmirx_dev->delayed_work_res_change);
++	cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat);
++	flush_work(&hdmirx_dev->work_wdt_config);
++
++	arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res);
++}
++
++static int hdmirx_disable(struct device *dev)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++
++	clk_bulk_disable_unprepare(hdmirx_dev->num_clks, hdmirx_dev->clks);
++
++	v4l2_dbg(2, debug, v4l2_dev, "%s: suspend\n", __func__);
++
++	return pinctrl_pm_select_sleep_state(dev);
++}
++
++static void hdmirx_enable_irq(struct device *dev)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
++	struct arm_smccc_res res;
++
++	enable_irq(hdmirx_dev->hdmi_irq);
++	enable_irq(hdmirx_dev->dma_irq);
++	enable_irq(hdmirx_dev->det_irq);
++
++	arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN,
++		      RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res);
++
++	queue_delayed_work(system_unbound_wq, &hdmirx_dev->delayed_work_hotplug,
++			   msecs_to_jiffies(20));
++}
++
++static int hdmirx_enable(struct device *dev)
++{
++	struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
++	struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
++	int ret;
++
++	v4l2_dbg(2, debug, v4l2_dev, "%s: resume\n", __func__);
++	ret = pinctrl_pm_select_default_state(dev);
++	if (ret < 0)
++		return ret;
++
++	ret = clk_bulk_prepare_enable(hdmirx_dev->num_clks, hdmirx_dev->clks);
++	if (ret) {
++		dev_err(dev, "failed to enable hdmirx bulk clks: %d\n", ret);
++		return ret;
++	}
++
++	reset_control_bulk_assert(HDMIRX_NUM_RST, hdmirx_dev->resets);
++	usleep_range(150, 160);
++	reset_control_bulk_deassert(HDMIRX_NUM_RST, hdmirx_dev->resets);
++	usleep_range(150, 160);
++
++	return 0;
++}
++
++static int hdmirx_suspend(struct device *dev)
++{
++	hdmirx_disable_irq(dev);
++
++	return hdmirx_disable(dev);
++}
++
++static int hdmirx_resume(struct device *dev)
++{
++	int ret = hdmirx_enable(dev);
++
++	if (ret)
++		return ret;
++
++	hdmirx_enable_irq(dev);
++
++	return 0;
++}
++
++static const struct dev_pm_ops snps_hdmirx_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(hdmirx_suspend, hdmirx_resume)
++};
++
++static int hdmirx_setup_irq(struct snps_hdmirx_dev *hdmirx_dev,
++			    struct platform_device *pdev)
++{
++	struct device *dev = hdmirx_dev->dev;
++	int ret, irq;
++
++	irq = platform_get_irq_byname(pdev, "hdmi");
++	if (irq < 0) {
++		dev_err_probe(dev, irq, "failed to get hdmi irq\n");
++		return irq;
++	}
++
++	irq_set_status_flags(irq, IRQ_NOAUTOEN);
++
++	hdmirx_dev->hdmi_irq = irq;
++	ret = devm_request_irq(dev, irq, hdmirx_hdmi_irq_handler, 0,
++			       "rk_hdmirx-hdmi", hdmirx_dev);
++	if (ret) {
++		dev_err_probe(dev, ret, "failed to request hdmi irq\n");
++		return ret;
++	}
++
++	irq = platform_get_irq_byname(pdev, "dma");
++	if (irq < 0) {
++		dev_err_probe(dev, irq, "failed to get dma irq\n");
++		return irq;
++	}
++
++	irq_set_status_flags(irq, IRQ_NOAUTOEN);
++
++	hdmirx_dev->dma_irq = irq;
++	ret = devm_request_threaded_irq(dev, irq, NULL, hdmirx_dma_irq_handler,
++					IRQF_ONESHOT, "rk_hdmirx-dma",
++					hdmirx_dev);
++	if (ret) {
++		dev_err_probe(dev, ret, "failed to request dma irq\n");
++		return ret;
++	}
++
++	irq = gpiod_to_irq(hdmirx_dev->detect_5v_gpio);
++	if (irq < 0) {
++		dev_err_probe(dev, irq, "failed to get hdmirx-5v irq\n");
++		return irq;
++	}
++
++	irq_set_status_flags(irq, IRQ_NOAUTOEN);
++
++	hdmirx_dev->det_irq = irq;
++	ret = devm_request_irq(dev, irq, hdmirx_5v_det_irq_handler,
++			       IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
++			       "rk_hdmirx-5v", hdmirx_dev);
++	if (ret) {
++		dev_err_probe(dev, ret, "failed to request hdmirx-5v irq\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int hdmirx_register_cec(struct snps_hdmirx_dev *hdmirx_dev,
++			       struct platform_device *pdev)
++{
++	struct device *dev = hdmirx_dev->dev;
++	struct hdmirx_cec_data cec_data;
++	int irq;
++
++	irq = platform_get_irq_byname(pdev, "cec");
++	if (irq < 0) {
++		dev_err_probe(dev, irq, "failed to get cec irq\n");
++		return irq;
++	}
++
++	hdmirx_dev->cec_notifier = cec_notifier_conn_register(dev, NULL, NULL);
++	if (!hdmirx_dev->cec_notifier)
++		return -EINVAL;
++
++	cec_data.hdmirx = hdmirx_dev;
++	cec_data.dev = hdmirx_dev->dev;
++	cec_data.ops = &hdmirx_cec_ops;
++	cec_data.irq = irq;
++
++	hdmirx_dev->cec = snps_hdmirx_cec_register(&cec_data);
++	if (!hdmirx_dev->cec) {
++		cec_notifier_conn_unregister(hdmirx_dev->cec_notifier);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int hdmirx_probe(struct platform_device *pdev)
++{
++	struct snps_hdmirx_dev *hdmirx_dev;
++	struct device *dev = &pdev->dev;
++	struct v4l2_ctrl_handler *hdl;
++	struct hdmirx_stream *stream;
++	struct v4l2_device *v4l2_dev;
++	int ret;
++
++	hdmirx_dev = devm_kzalloc(dev, sizeof(*hdmirx_dev), GFP_KERNEL);
++	if (!hdmirx_dev)
++		return -ENOMEM;
++
++	ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
++	if (ret)
++		return ret;
++
++	hdmirx_dev->dev = dev;
++	dev_set_drvdata(dev, hdmirx_dev);
++
++	ret = hdmirx_parse_dt(hdmirx_dev);
++	if (ret)
++		return ret;
++
++	ret = hdmirx_setup_irq(hdmirx_dev, pdev);
++	if (ret)
++		return ret;
++
++	hdmirx_dev->regs = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(hdmirx_dev->regs))
++		return dev_err_probe(dev, PTR_ERR(hdmirx_dev->regs),
++				     "failed to remap regs resource\n");
++
++	mutex_init(&hdmirx_dev->stream_lock);
++	mutex_init(&hdmirx_dev->work_lock);
++	spin_lock_init(&hdmirx_dev->rst_lock);
++
++	init_completion(&hdmirx_dev->cr_write_done);
++	init_completion(&hdmirx_dev->timer_base_lock);
++	init_completion(&hdmirx_dev->avi_pkt_rcv);
++
++	INIT_WORK(&hdmirx_dev->work_wdt_config, hdmirx_work_wdt_config);
++	INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_hotplug,
++			  hdmirx_delayed_work_hotplug);
++	INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_res_change,
++			  hdmirx_delayed_work_res_change);
++	INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_heartbeat,
++			  hdmirx_delayed_work_heartbeat);
++
++	hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
++	hdmirx_dev->timings = cea640x480;
++
++	hdmirx_enable(dev);
++	hdmirx_init(hdmirx_dev);
++
++	v4l2_dev = &hdmirx_dev->v4l2_dev;
++	strscpy(v4l2_dev->name, dev_name(dev), sizeof(v4l2_dev->name));
++
++	hdl = &hdmirx_dev->hdl;
++	v4l2_ctrl_handler_init(hdl, 1);
++
++	hdmirx_dev->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
++							  V4L2_CID_DV_RX_POWER_PRESENT,
++							  0, 1, 0, 0);
++
++	hdmirx_dev->rgb_range = v4l2_ctrl_new_std_menu(hdl, 0,
++						       V4L2_CID_DV_RX_RGB_RANGE,
++						       V4L2_DV_RGB_RANGE_FULL, 0,
++						       V4L2_DV_RGB_RANGE_AUTO);
++
++	hdmirx_dev->rgb_range->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++
++	if (hdl->error) {
++		dev_err(dev, "v4l2 ctrl handler init failed\n");
++		ret = hdl->error;
++		goto err_pm;
++	}
++	hdmirx_dev->v4l2_dev.ctrl_handler = hdl;
++
++	ret = v4l2_device_register(dev, &hdmirx_dev->v4l2_dev);
++	if (ret < 0) {
++		dev_err(dev, "register v4l2 device failed\n");
++		goto err_hdl;
++	}
++
++	stream = &hdmirx_dev->stream;
++	stream->hdmirx_dev = hdmirx_dev;
++	ret = hdmirx_register_stream_vdev(stream);
++	if (ret < 0) {
++		dev_err(dev, "register video device failed\n");
++		goto err_unreg_v4l2_dev;
++	}
++
++	ret = hdmirx_register_cec(hdmirx_dev, pdev);
++	if (ret)
++		goto err_unreg_video_dev;
++
++	hdmirx_load_default_edid(hdmirx_dev);
++
++	hdmirx_enable_irq(dev);
++
++	return 0;
++
++err_unreg_video_dev:
++	video_unregister_device(&hdmirx_dev->stream.vdev);
++err_unreg_v4l2_dev:
++	v4l2_device_unregister(&hdmirx_dev->v4l2_dev);
++err_hdl:
++	v4l2_ctrl_handler_free(&hdmirx_dev->hdl);
++err_pm:
++	hdmirx_disable(dev);
++
++	return ret;
++}
++
++static void hdmirx_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
++
++	snps_hdmirx_cec_unregister(hdmirx_dev->cec);
++	cec_notifier_conn_unregister(hdmirx_dev->cec_notifier);
++
++	hdmirx_disable_irq(dev);
++
++	video_unregister_device(&hdmirx_dev->stream.vdev);
++	v4l2_ctrl_handler_free(&hdmirx_dev->hdl);
++	v4l2_device_unregister(&hdmirx_dev->v4l2_dev);
++
++	hdmirx_disable(dev);
++
++	reset_control_bulk_assert(HDMIRX_NUM_RST, hdmirx_dev->resets);
++
++	of_reserved_mem_device_release(dev);
++}
++
++static const struct of_device_id hdmirx_id[] = {
++	{ .compatible = "rockchip,rk3588-hdmirx-ctrler" },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, hdmirx_id);
++
++static struct platform_driver hdmirx_driver = {
++	.probe = hdmirx_probe,
++	.remove = hdmirx_remove,
++	.driver = {
++		.name = "snps_hdmirx",
++		.of_match_table = hdmirx_id,
++		.pm = &snps_hdmirx_pm_ops,
++	}
++};
++module_platform_driver(hdmirx_driver);
++
++MODULE_DESCRIPTION("Rockchip HDMI Receiver Driver");
++MODULE_AUTHOR("Dingxian Wen <shawn.wen@rock-chips.com>");
++MODULE_AUTHOR("Shreeya Patel <shreeya.patel@collabora.com>");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h
+@@ -0,0 +1,394 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ *
++ * Author: Dingxian Wen <shawn.wen@rock-chips.com>
++ */
++
++#ifndef DW_HDMIRX_H
++#define DW_HDMIRX_H
++
++#include <linux/bitops.h>
++
++#define UPDATE(x, h, l)		(((x) << (l)) & GENMASK((h), (l)))
++#define HIWORD_UPDATE(v, h, l)	(((v) << (l)) | (GENMASK((h), (l)) << 16))
++
++/* SYS_GRF */
++#define SYS_GRF_SOC_CON1			0x0304
++#define HDMIRXPHY_SRAM_EXT_LD_DONE		BIT(1)
++#define HDMIRXPHY_SRAM_BYPASS			BIT(0)
++#define SYS_GRF_SOC_STATUS1			0x0384
++#define HDMIRXPHY_SRAM_INIT_DONE		BIT(10)
++#define SYS_GRF_CHIP_ID				0x0600
++
++/* VO1_GRF */
++#define VO1_GRF_VO1_CON2			0x0008
++#define HDMIRX_SDAIN_MSK			BIT(2)
++#define HDMIRX_SCLIN_MSK			BIT(1)
++
++/* HDMIRX PHY */
++#define SUP_DIG_ANA_CREGS_SUP_ANA_NC			0x004f
++
++#define	LANE0_DIG_ASIC_RX_OVRD_OUT_0			0x100f
++#define	LANE1_DIG_ASIC_RX_OVRD_OUT_0			0x110f
++#define	LANE2_DIG_ASIC_RX_OVRD_OUT_0			0x120f
++#define	LANE3_DIG_ASIC_RX_OVRD_OUT_0			0x130f
++#define ASIC_ACK_OVRD_EN				BIT(1)
++#define ASIC_ACK					BIT(0)
++
++#define	LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x104a
++#define	LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x114a
++#define	LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x124a
++#define	LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x134a
++#define FREQ_TUNE_START_VAL_MASK			GENMASK(9, 0)
++#define FREQ_TUNE_START_VAL(x)				UPDATE(x, 9, 0)
++
++#define	HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG	0x20c4
++#define	HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM	0x20c7
++#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG	0x20e9
++#define CDR_SETTING_BOUNDARY_3_DEFAULT			0x52da
++#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG	0x20ea
++#define CDR_SETTING_BOUNDARY_4_DEFAULT			0x43cd
++#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG	0x20eb
++#define CDR_SETTING_BOUNDARY_5_DEFAULT			0x35b3
++#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG	0x20fb
++#define	CDR_SETTING_BOUNDARY_6_DEFAULT			0x2799
++#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG	0x20fc
++#define CDR_SETTING_BOUNDARY_7_DEFAULT			0x1b65
++
++#define	RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT			0x300e
++#define	RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT			0x310e
++#define	RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT			0x320e
++#define	RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT			0x330e
++#define PCS_ACK_WRITE_SELECT				BIT(14)
++#define PCS_EN_CTL					BIT(1)
++#define PCS_ACK						BIT(0)
++
++#define	RAWLANE0_DIG_AON_FAST_FLAGS			0x305c
++#define	RAWLANE1_DIG_AON_FAST_FLAGS			0x315c
++#define	RAWLANE2_DIG_AON_FAST_FLAGS			0x325c
++#define	RAWLANE3_DIG_AON_FAST_FLAGS			0x335c
++
++/* HDMIRX Ctrler */
++#define GLOBAL_SWRESET_REQUEST			0x0020
++#define DATAPATH_SWRESETREQ			BIT(12)
++#define GLOBAL_SWENABLE				0x0024
++#define PHYCTRL_ENABLE				BIT(21)
++#define CEC_ENABLE				BIT(16)
++#define TMDS_ENABLE				BIT(13)
++#define DATAPATH_ENABLE				BIT(12)
++#define PKTFIFO_ENABLE				BIT(11)
++#define AVPUNIT_ENABLE				BIT(8)
++#define MAIN_ENABLE				BIT(0)
++#define GLOBAL_TIMER_REF_BASE			0x0028
++#define CORE_CONFIG				0x0050
++#define CMU_CONFIG0				0x0060
++#define TMDSQPCLK_STABLE_FREQ_MARGIN_MASK	GENMASK(30, 16)
++#define TMDSQPCLK_STABLE_FREQ_MARGIN(x)		UPDATE(x, 30, 16)
++#define AUDCLK_STABLE_FREQ_MARGIN_MASK		GENMASK(11, 9)
++#define AUDCLK_STABLE_FREQ_MARGIN(x)		UPDATE(x, 11, 9)
++#define CMU_STATUS				0x007c
++#define TMDSQPCLK_LOCKED_ST			BIT(4)
++#define CMU_TMDSQPCLK_FREQ			0x0084
++#define PHY_CONFIG				0x00c0
++#define LDO_AFE_PROG_MASK			GENMASK(24, 23)
++#define LDO_AFE_PROG(x)				UPDATE(x, 24, 23)
++#define LDO_PWRDN				BIT(21)
++#define TMDS_CLOCK_RATIO			BIT(16)
++#define RXDATA_WIDTH				BIT(15)
++#define REFFREQ_SEL_MASK			GENMASK(11, 9)
++#define REFFREQ_SEL(x)				UPDATE(x, 11, 9)
++#define HDMI_DISABLE				BIT(8)
++#define PHY_PDDQ				BIT(1)
++#define PHY_RESET				BIT(0)
++#define PHY_STATUS				0x00c8
++#define HDMI_DISABLE_ACK			BIT(1)
++#define PDDQ_ACK				BIT(0)
++#define PHYCREG_CONFIG0				0x00e0
++#define PHYCREG_CR_PARA_SELECTION_MODE_MASK	GENMASK(1, 0)
++#define PHYCREG_CR_PARA_SELECTION_MODE(x)	UPDATE(x, 1, 0)
++#define PHYCREG_CONFIG1				0x00e4
++#define PHYCREG_CONFIG2				0x00e8
++#define PHYCREG_CONFIG3				0x00ec
++#define PHYCREG_CONTROL				0x00f0
++#define PHYCREG_CR_PARA_WRITE_P			BIT(1)
++#define PHYCREG_CR_PARA_READ_P			BIT(0)
++#define PHYCREG_STATUS				0x00f4
++
++#define MAINUNIT_STATUS				0x0150
++#define TMDSVALID_STABLE_ST			BIT(1)
++#define DESCRAND_EN_CONTROL			0x0210
++#define SCRAMB_EN_SEL_QST_MASK			GENMASK(1, 0)
++#define SCRAMB_EN_SEL_QST(x)			UPDATE(x, 1, 0)
++#define DESCRAND_SYNC_CONTROL			0x0214
++#define RECOVER_UNSYNC_STREAM_QST		BIT(0)
++#define DESCRAND_SYNC_SEQ_CONFIG		0x022c
++#define DESCRAND_SYNC_SEQ_ERR_CNT_EN		BIT(0)
++#define DESCRAND_SYNC_SEQ_STATUS		0x0234
++#define DEFRAMER_CONFIG0			0x0270
++#define VS_CNT_THR_QST_MASK			GENMASK(27, 20)
++#define VS_CNT_THR_QST(x)			UPDATE(x, 27, 20)
++#define HS_POL_QST_MASK				GENMASK(19, 18)
++#define HS_POL_QST(x)				UPDATE(x, 19, 18)
++#define VS_POL_QST_MASK				GENMASK(17, 16)
++#define VS_POL_QST(x)				UPDATE(x, 17, 16)
++#define VS_REMAPFILTER_EN_QST			BIT(8)
++#define VS_FILTER_ORDER_QST_MASK		GENMASK(1, 0)
++#define VS_FILTER_ORDER_QST(x)			UPDATE(x, 1, 0)
++#define DEFRAMER_VSYNC_CNT_CLEAR		0x0278
++#define VSYNC_CNT_CLR_P				BIT(0)
++#define DEFRAMER_STATUS				0x027c
++#define OPMODE_STS_MASK				GENMASK(6, 4)
++#define I2C_SLAVE_CONFIG1			0x0164
++#define I2C_SDA_OUT_HOLD_VALUE_QST_MASK		GENMASK(15, 8)
++#define I2C_SDA_OUT_HOLD_VALUE_QST(x)		UPDATE(x, 15, 8)
++#define I2C_SDA_IN_HOLD_VALUE_QST_MASK		GENMASK(7, 0)
++#define I2C_SDA_IN_HOLD_VALUE_QST(x)		UPDATE(x, 7, 0)
++#define OPMODE_STS_MASK				GENMASK(6, 4)
++#define REPEATER_QST				BIT(28)
++#define FASTREAUTH_QST				BIT(27)
++#define FEATURES_1DOT1_QST			BIT(26)
++#define FASTI2C_QST				BIT(25)
++#define EESS_CTL_THR_QST_MASK			GENMASK(19, 16)
++#define EESS_CTL_THR_QST(x)			UPDATE(x, 19, 16)
++#define OESS_CTL3_THR_QST_MASK			GENMASK(11, 8)
++#define OESS_CTL3_THR_QST(x)			UPDATE(x, 11, 8)
++#define EESS_OESS_SEL_QST_MASK			GENMASK(5, 4)
++#define EESS_OESS_SEL_QST(x)			UPDATE(x, 5, 4)
++#define KEY_DECRYPT_EN_QST			BIT(0)
++#define KEY_DECRYPT_SEED_QST_MASK		GENMASK(15, 0)
++#define KEY_DECRYPT_SEED_QST(x)			UPDATE(x, 15, 0)
++#define HDCP_INT_CLEAR				0x50d8
++#define HDCP_1_INT_CLEAR			0x50e8
++#define HDCP2_CONFIG				0x02f0
++#define HDCP2_SWITCH_OVR_VALUE			BIT(2)
++#define HDCP2_SWITCH_OVR_EN			BIT(1)
++
++#define VIDEO_CONFIG2				0x042c
++#define VPROC_VSYNC_POL_OVR_VALUE		BIT(19)
++#define VPROC_VSYNC_POL_OVR_EN			BIT(18)
++#define VPROC_HSYNC_POL_OVR_VALUE		BIT(17)
++#define VPROC_HSYNC_POL_OVR_EN			BIT(16)
++#define VPROC_FMT_OVR_VALUE_MASK		GENMASK(6, 4)
++#define VPROC_FMT_OVR_VALUE(x)			UPDATE(x, 6, 4)
++#define VPROC_FMT_OVR_EN			BIT(0)
++
++#define AFIFO_FILL_RESTART			BIT(0)
++#define AFIFO_INIT_P				BIT(0)
++#define AFIFO_THR_LOW_QST_MASK			GENMASK(25, 16)
++#define AFIFO_THR_LOW_QST(x)			UPDATE(x, 25, 16)
++#define AFIFO_THR_HIGH_QST_MASK			GENMASK(9, 0)
++#define AFIFO_THR_HIGH_QST(x)			UPDATE(x, 9, 0)
++#define AFIFO_THR_MUTE_LOW_QST_MASK		GENMASK(25, 16)
++#define AFIFO_THR_MUTE_LOW_QST(x)		UPDATE(x, 25, 16)
++#define AFIFO_THR_MUTE_HIGH_QST_MASK		GENMASK(9, 0)
++#define AFIFO_THR_MUTE_HIGH_QST(x)		UPDATE(x, 9, 0)
++
++#define AFIFO_UNDERFLOW_ST			BIT(25)
++#define AFIFO_OVERFLOW_ST			BIT(24)
++
++#define SPEAKER_ALLOC_OVR_EN			BIT(16)
++#define I2S_BPCUV_EN				BIT(4)
++#define SPDIF_EN				BIT(2)
++#define I2S_EN					BIT(1)
++#define AFIFO_THR_PASS_DEMUTEMASK_N		BIT(24)
++#define AVMUTE_DEMUTEMASK_N			BIT(16)
++#define AFIFO_THR_MUTE_LOW_MUTEMASK_N		BIT(9)
++#define AFIFO_THR_MUTE_HIGH_MUTEMASK_N		BIT(8)
++#define AVMUTE_MUTEMASK_N			BIT(0)
++#define SCDC_CONFIG				0x0580
++#define HPDLOW					BIT(1)
++#define POWERPROVIDED				BIT(0)
++#define SCDC_REGBANK_STATUS1			0x058c
++#define SCDC_TMDSBITCLKRATIO			BIT(1)
++#define SCDC_REGBANK_STATUS3			0x0594
++#define SCDC_REGBANK_CONFIG0			0x05c0
++#define SCDC_SINKVERSION_QST_MASK		GENMASK(7, 0)
++#define SCDC_SINKVERSION_QST(x)			UPDATE(x, 7, 0)
++#define AGEN_LAYOUT				BIT(4)
++#define AGEN_SPEAKER_ALLOC			GENMASK(15, 8)
++
++#define CED_CONFIG				0x0760
++#define CED_VIDDATACHECKEN_QST			BIT(27)
++#define CED_DATAISCHECKEN_QST			BIT(26)
++#define CED_GBCHECKEN_QST			BIT(25)
++#define CED_CTRLCHECKEN_QST			BIT(24)
++#define CED_CHLOCKMAXER_QST_MASK		GENMASK(14, 0)
++#define CED_CHLOCKMAXER_QST(x)			UPDATE(x, 14, 0)
++#define CED_DYN_CONFIG				0x0768
++#define CED_DYN_CONTROL				0x076c
++#define PKTEX_BCH_ERRFILT_CONFIG		0x07c4
++#define PKTEX_CHKSUM_ERRFILT_CONFIG		0x07c8
++
++#define PKTDEC_ACR_PH2_1			0x1100
++#define PKTDEC_ACR_PB3_0			0x1104
++#define PKTDEC_ACR_PB7_4			0x1108
++#define PKTDEC_AVIIF_PH2_1			0x1200
++#define PKTDEC_AVIIF_PB3_0			0x1204
++#define PKTDEC_AVIIF_PB7_4			0x1208
++#define VIC_VAL_MASK				GENMASK(6, 0)
++#define PKTDEC_AVIIF_PB11_8			0x120c
++#define PKTDEC_AVIIF_PB15_12			0x1210
++#define PKTDEC_AVIIF_PB19_16			0x1214
++#define PKTDEC_AVIIF_PB23_20			0x1218
++#define PKTDEC_AVIIF_PB27_24			0x121c
++
++#define PKTFIFO_CONFIG				0x1500
++#define PKTFIFO_STORE_FILT_CONFIG		0x1504
++#define PKTFIFO_THR_CONFIG0			0x1508
++#define PKTFIFO_THR_CONFIG1			0x150c
++#define PKTFIFO_CONTROL				0x1510
++
++#define VMON_STATUS1				0x1580
++#define VMON_STATUS2				0x1584
++#define VMON_STATUS3				0x1588
++#define VMON_STATUS4				0x158c
++#define VMON_STATUS5				0x1590
++#define VMON_STATUS6				0x1594
++#define VMON_STATUS7				0x1598
++#define VMON_ILACE_DETECT			BIT(4)
++
++#define CEC_TX_CONTROL				0x2000
++#define CEC_STATUS				0x2004
++#define CEC_CONFIG				0x2008
++#define RX_AUTO_DRIVE_ACKNOWLEDGE		BIT(9)
++#define CEC_ADDR				0x200c
++#define CEC_TX_COUNT				0x2020
++#define CEC_TX_DATA3_0				0x2024
++#define CEC_RX_COUNT_STATUS			0x2040
++#define CEC_RX_DATA3_0				0x2044
++#define CEC_LOCK_CONTROL			0x2054
++#define CEC_RXQUAL_BITTIME_CONFIG		0x2060
++#define CEC_RX_BITTIME_CONFIG			0x2064
++#define CEC_TX_BITTIME_CONFIG			0x2068
++
++#define DMA_CONFIG1				0x4400
++#define UV_WID_MASK				GENMASK(31, 28)
++#define UV_WID(x)				UPDATE(x, 31, 28)
++#define Y_WID_MASK				GENMASK(27, 24)
++#define Y_WID(x)				UPDATE(x, 27, 24)
++#define DDR_STORE_FORMAT_MASK			GENMASK(15, 12)
++#define DDR_STORE_FORMAT(x)			UPDATE(x, 15, 12)
++#define ABANDON_EN				BIT(0)
++#define DMA_CONFIG2				0x4404
++#define DMA_CONFIG3				0x4408
++#define DMA_CONFIG4				0x440c // dma irq en
++#define DMA_CONFIG5				0x4410 // dma irq clear status
++#define LINE_FLAG_INT_EN			BIT(8)
++#define HDMIRX_DMA_IDLE_INT			BIT(7)
++#define HDMIRX_LOCK_DISABLE_INT			BIT(6)
++#define LAST_FRAME_AXI_UNFINISH_INT_EN		BIT(5)
++#define FIFO_OVERFLOW_INT_EN			BIT(2)
++#define FIFO_UNDERFLOW_INT_EN			BIT(1)
++#define HDMIRX_AXI_ERROR_INT_EN			BIT(0)
++#define DMA_CONFIG6				0x4414
++#define RB_SWAP_EN				BIT(9)
++#define HSYNC_TOGGLE_EN				BIT(5)
++#define VSYNC_TOGGLE_EN				BIT(4)
++#define HDMIRX_DMA_EN				BIT(1)
++#define DMA_CONFIG7				0x4418
++#define LINE_FLAG_NUM_MASK			GENMASK(31, 16)
++#define LINE_FLAG_NUM(x)			UPDATE(x, 31, 16)
++#define LOCK_FRAME_NUM_MASK			GENMASK(11, 0)
++#define LOCK_FRAME_NUM(x)			UPDATE(x, 11, 0)
++#define DMA_CONFIG8				0x441c
++#define REG_MIRROR_EN				BIT(0)
++#define DMA_CONFIG9				0x4420
++#define DMA_CONFIG10				0x4424
++#define DMA_CONFIG11				0x4428
++#define EDID_READ_EN_MASK			BIT(8)
++#define EDID_READ_EN(x)				UPDATE(x, 8, 8)
++#define EDID_WRITE_EN_MASK			BIT(7)
++#define EDID_WRITE_EN(x)			UPDATE(x, 7, 7)
++#define EDID_SLAVE_ADDR_MASK			GENMASK(6, 0)
++#define EDID_SLAVE_ADDR(x)			UPDATE(x, 6, 0)
++#define DMA_STATUS1				0x4430 // dma irq status
++#define DMA_STATUS2				0x4434
++#define DMA_STATUS3				0x4438
++#define DMA_STATUS4				0x443c
++#define DMA_STATUS5				0x4440
++#define DMA_STATUS6				0x4444
++#define DMA_STATUS7				0x4448
++#define DMA_STATUS8				0x444c
++#define DMA_STATUS9				0x4450
++#define DMA_STATUS10				0x4454
++#define HDMIRX_LOCK				BIT(3)
++#define DMA_STATUS11				0x4458
++#define HDMIRX_TYPE_MASK			GENMASK(8, 7)
++#define HDMIRX_COLOR_DEPTH_MASK			GENMASK(6, 3)
++#define HDMIRX_FORMAT_MASK			GENMASK(2, 0)
++#define DMA_STATUS12				0x445c
++#define DMA_STATUS13				0x4460
++#define DMA_STATUS14				0x4464
++
++#define MAINUNIT_INTVEC_INDEX			0x5000
++#define MAINUNIT_0_INT_STATUS			0x5010
++#define CECRX_NOTIFY_ERR			BIT(12)
++#define CECRX_EOM				BIT(11)
++#define CECTX_DRIVE_ERR				BIT(10)
++#define CECRX_BUSY				BIT(9)
++#define CECTX_BUSY				BIT(8)
++#define CECTX_FRAME_DISCARDED			BIT(5)
++#define CECTX_NRETRANSMIT_FAIL			BIT(4)
++#define CECTX_LINE_ERR				BIT(3)
++#define CECTX_ARBLOST				BIT(2)
++#define CECTX_NACK				BIT(1)
++#define CECTX_DONE				BIT(0)
++#define MAINUNIT_0_INT_MASK_N			0x5014
++#define MAINUNIT_0_INT_CLEAR			0x5018
++#define MAINUNIT_0_INT_FORCE			0x501c
++#define TIMER_BASE_LOCKED_IRQ			BIT(26)
++#define TMDSQPCLK_OFF_CHG			BIT(5)
++#define TMDSQPCLK_LOCKED_CHG			BIT(4)
++#define MAINUNIT_1_INT_STATUS			0x5020
++#define MAINUNIT_1_INT_MASK_N			0x5024
++#define MAINUNIT_1_INT_CLEAR			0x5028
++#define MAINUNIT_1_INT_FORCE			0x502c
++#define MAINUNIT_2_INT_STATUS			0x5030
++#define MAINUNIT_2_INT_MASK_N			0x5034
++#define MAINUNIT_2_INT_CLEAR			0x5038
++#define MAINUNIT_2_INT_FORCE			0x503c
++#define PHYCREG_CR_READ_DONE			BIT(11)
++#define PHYCREG_CR_WRITE_DONE			BIT(10)
++#define TMDSVALID_STABLE_CHG			BIT(1)
++
++#define AVPUNIT_0_INT_STATUS			0x5040
++#define AVPUNIT_0_INT_MASK_N			0x5044
++#define AVPUNIT_0_INT_CLEAR			0x5048
++#define AVPUNIT_0_INT_FORCE			0x504c
++#define CED_DYN_CNT_CH2_IRQ			BIT(22)
++#define CED_DYN_CNT_CH1_IRQ			BIT(21)
++#define CED_DYN_CNT_CH0_IRQ			BIT(20)
++#define AVPUNIT_1_INT_STATUS			0x5050
++#define DEFRAMER_VSYNC_THR_REACHED_IRQ		BIT(1)
++#define AVPUNIT_1_INT_MASK_N			0x5054
++#define DEFRAMER_VSYNC_THR_REACHED_MASK_N	BIT(1)
++#define DEFRAMER_VSYNC_MASK_N			BIT(0)
++#define AVPUNIT_1_INT_CLEAR			0x5058
++#define DEFRAMER_VSYNC_THR_REACHED_CLEAR	BIT(1)
++#define PKT_0_INT_STATUS			0x5080
++#define PKTDEC_ACR_CHG_IRQ			BIT(3)
++#define PKT_0_INT_MASK_N			0x5084
++#define PKTDEC_ACR_CHG_MASK_N			BIT(3)
++#define PKT_0_INT_CLEAR				0x5088
++#define PKT_1_INT_STATUS			0x5090
++#define PKT_1_INT_MASK_N			0x5094
++#define PKT_1_INT_CLEAR				0x5098
++#define PKT_2_INT_STATUS			0x50a0
++#define PKTDEC_ACR_RCV_IRQ			BIT(3)
++#define PKT_2_INT_MASK_N			0x50a4
++#define PKTDEC_AVIIF_RCV_IRQ			BIT(11)
++#define PKTDEC_ACR_RCV_MASK_N			BIT(3)
++#define PKT_2_INT_CLEAR				0x50a8
++#define PKTDEC_AVIIF_RCV_CLEAR			BIT(11)
++#define PKTDEC_ACR_RCV_CLEAR			BIT(3)
++#define SCDC_INT_STATUS				0x50c0
++#define SCDC_INT_MASK_N				0x50c4
++#define SCDC_INT_CLEAR				0x50c8
++#define SCDCTMDSCCFG_CHG			BIT(2)
++
++#define CEC_INT_STATUS				0x5100
++#define CEC_INT_MASK_N				0x5104
++#define CEC_INT_CLEAR				0x5108
++
++#endif
+diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c
+@@ -0,0 +1,285 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ *
++ * Author: Shunqing Chen <csq@rock-chips.com>
++ */
++
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++
++#include <media/cec.h>
++#include <media/cec-notifier.h>
++
++#include "snps_hdmirx.h"
++#include "snps_hdmirx_cec.h"
++
++static void hdmirx_cec_write(struct hdmirx_cec *cec, int reg, u32 val)
++{
++	cec->ops->write(cec->hdmirx, reg, val);
++}
++
++static u32 hdmirx_cec_read(struct hdmirx_cec *cec, int reg)
++{
++	return cec->ops->read(cec->hdmirx, reg);
++}
++
++static void hdmirx_cec_update_bits(struct hdmirx_cec *cec, int reg, u32 mask,
++				   u32 data)
++{
++	u32 val = hdmirx_cec_read(cec, reg) & ~mask;
++
++	val |= (data & mask);
++	hdmirx_cec_write(cec, reg, val);
++}
++
++static int hdmirx_cec_log_addr(struct cec_adapter *adap, u8 logical_addr)
++{
++	struct hdmirx_cec *cec = cec_get_drvdata(adap);
++
++	if (logical_addr == CEC_LOG_ADDR_INVALID)
++		cec->addresses = 0;
++	else
++		cec->addresses |= BIT(logical_addr) | BIT(15);
++
++	hdmirx_cec_write(cec, CEC_ADDR, cec->addresses);
++
++	return 0;
++}
++
++/* signal_free_time is handled by the Synopsys Designware
++ * HDMIRX Controller hardware.
++ */
++static int hdmirx_cec_transmit(struct cec_adapter *adap, u8 attempts,
++			       u32 signal_free_time, struct cec_msg *msg)
++{
++	struct hdmirx_cec *cec = cec_get_drvdata(adap);
++	u32 data[4] = {0};
++	int i, data_len, msg_len;
++
++	msg_len = msg->len;
++
++	hdmirx_cec_write(cec, CEC_TX_COUNT, msg_len - 1);
++	for (i = 0; i < msg_len; i++)
++		data[i / 4] |= msg->msg[i] << (i % 4) * 8;
++
++	data_len = DIV_ROUND_UP(msg_len, 4);
++
++	for (i = 0; i < data_len; i++)
++		hdmirx_cec_write(cec, CEC_TX_DATA3_0 + i * 4, data[i]);
++
++	hdmirx_cec_write(cec, CEC_TX_CONTROL, 0x1);
++
++	return 0;
++}
++
++static irqreturn_t hdmirx_cec_hardirq(int irq, void *data)
++{
++	struct cec_adapter *adap = data;
++	struct hdmirx_cec *cec = cec_get_drvdata(adap);
++	u32 stat = hdmirx_cec_read(cec, CEC_INT_STATUS);
++	irqreturn_t ret = IRQ_HANDLED;
++	u32 val;
++
++	if (!stat)
++		return IRQ_NONE;
++
++	hdmirx_cec_write(cec, CEC_INT_CLEAR, stat);
++
++	if (stat & CECTX_LINE_ERR) {
++		cec->tx_status = CEC_TX_STATUS_ERROR;
++		cec->tx_done = true;
++		ret = IRQ_WAKE_THREAD;
++	} else if (stat & CECTX_DONE) {
++		cec->tx_status = CEC_TX_STATUS_OK;
++		cec->tx_done = true;
++		ret = IRQ_WAKE_THREAD;
++	} else if (stat & CECTX_NACK) {
++		cec->tx_status = CEC_TX_STATUS_NACK;
++		cec->tx_done = true;
++		ret = IRQ_WAKE_THREAD;
++	} else if (stat & CECTX_ARBLOST) {
++		cec->tx_status = CEC_TX_STATUS_ARB_LOST;
++		cec->tx_done = true;
++		ret = IRQ_WAKE_THREAD;
++	}
++
++	if (stat & CECRX_EOM) {
++		unsigned int len, i;
++
++		val = hdmirx_cec_read(cec, CEC_RX_COUNT_STATUS);
++		/* rxbuffer locked status */
++		if ((val & 0x80))
++			return ret;
++
++		len = (val & 0xf) + 1;
++		if (len > sizeof(cec->rx_msg.msg))
++			len = sizeof(cec->rx_msg.msg);
++
++		for (i = 0; i < len; i++) {
++			if (!(i % 4))
++				val = hdmirx_cec_read(cec, CEC_RX_DATA3_0 + i / 4 * 4);
++			cec->rx_msg.msg[i] = (val >> ((i % 4) * 8)) & 0xff;
++		}
++
++		cec->rx_msg.len = len;
++		smp_wmb(); /* receive RX msg */
++		cec->rx_done = true;
++		hdmirx_cec_write(cec, CEC_LOCK_CONTROL, 0x1);
++
++		ret = IRQ_WAKE_THREAD;
++	}
++
++	return ret;
++}
++
++static irqreturn_t hdmirx_cec_thread(int irq, void *data)
++{
++	struct cec_adapter *adap = data;
++	struct hdmirx_cec *cec = cec_get_drvdata(adap);
++
++	if (cec->tx_done) {
++		cec->tx_done = false;
++		cec_transmit_attempt_done(adap, cec->tx_status);
++	}
++	if (cec->rx_done) {
++		cec->rx_done = false;
++		smp_rmb(); /* RX msg has been received */
++		cec_received_msg(adap, &cec->rx_msg);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static int hdmirx_cec_enable(struct cec_adapter *adap, bool enable)
++{
++	struct hdmirx_cec *cec = cec_get_drvdata(adap);
++
++	if (!enable) {
++		hdmirx_cec_write(cec, CEC_INT_MASK_N, 0);
++		hdmirx_cec_write(cec, CEC_INT_CLEAR, 0);
++		if (cec->ops->disable)
++			cec->ops->disable(cec->hdmirx);
++	} else {
++		unsigned int irqs;
++
++		hdmirx_cec_log_addr(cec->adap, CEC_LOG_ADDR_INVALID);
++		if (cec->ops->enable)
++			cec->ops->enable(cec->hdmirx);
++		hdmirx_cec_update_bits(cec, GLOBAL_SWENABLE, CEC_ENABLE, CEC_ENABLE);
++
++		irqs = CECTX_LINE_ERR | CECTX_NACK | CECRX_EOM | CECTX_DONE;
++		hdmirx_cec_write(cec, CEC_INT_MASK_N, irqs);
++	}
++
++	return 0;
++}
++
++static const struct cec_adap_ops hdmirx_cec_ops = {
++	.adap_enable = hdmirx_cec_enable,
++	.adap_log_addr = hdmirx_cec_log_addr,
++	.adap_transmit = hdmirx_cec_transmit,
++};
++
++static void hdmirx_cec_del(void *data)
++{
++	struct hdmirx_cec *cec = data;
++
++	cec_delete_adapter(cec->adap);
++}
++
++struct hdmirx_cec *snps_hdmirx_cec_register(struct hdmirx_cec_data *data)
++{
++	struct hdmirx_cec *cec;
++	unsigned int irqs;
++	int ret;
++
++	/*
++	 * Our device is just a convenience - we want to link to the real
++	 * hardware device here, so that userspace can see the association
++	 * between the HDMI hardware and its associated CEC chardev.
++	 */
++	cec = devm_kzalloc(data->dev, sizeof(*cec), GFP_KERNEL);
++	if (!cec)
++		return NULL;
++
++	cec->dev = data->dev;
++	cec->irq = data->irq;
++	cec->ops = data->ops;
++	cec->hdmirx = data->hdmirx;
++
++	hdmirx_cec_update_bits(cec, GLOBAL_SWENABLE, CEC_ENABLE, CEC_ENABLE);
++	hdmirx_cec_update_bits(cec, CEC_CONFIG, RX_AUTO_DRIVE_ACKNOWLEDGE,
++			       RX_AUTO_DRIVE_ACKNOWLEDGE);
++
++	hdmirx_cec_write(cec, CEC_TX_COUNT, 0);
++	hdmirx_cec_write(cec, CEC_INT_MASK_N, 0);
++	hdmirx_cec_write(cec, CEC_INT_CLEAR, ~0);
++
++	cec->adap = cec_allocate_adapter(&hdmirx_cec_ops, cec, "snps-hdmirx",
++					 CEC_CAP_LOG_ADDRS | CEC_CAP_TRANSMIT |
++					 CEC_CAP_RC | CEC_CAP_PASSTHROUGH |
++					 CEC_CAP_MONITOR_ALL,
++					 CEC_MAX_LOG_ADDRS);
++	if (IS_ERR(cec->adap)) {
++		dev_err(cec->dev, "cec adap allocate failed\n");
++		return NULL;
++	}
++
++	/* override the module pointer */
++	cec->adap->owner = THIS_MODULE;
++
++	ret = devm_add_action(cec->dev, hdmirx_cec_del, cec);
++	if (ret) {
++		cec_delete_adapter(cec->adap);
++		return NULL;
++	}
++
++	irq_set_status_flags(cec->irq, IRQ_NOAUTOEN);
++
++	ret = devm_request_threaded_irq(cec->dev, cec->irq,
++					hdmirx_cec_hardirq,
++					hdmirx_cec_thread, IRQF_ONESHOT,
++					"rk_hdmirx_cec", cec->adap);
++	if (ret) {
++		dev_err(cec->dev, "cec irq request failed\n");
++		return NULL;
++	}
++
++	cec->notify = cec_notifier_cec_adap_register(cec->dev,
++						     NULL, cec->adap);
++	if (!cec->notify) {
++		dev_err(cec->dev, "cec notify register failed\n");
++		return NULL;
++	}
++
++	ret = cec_register_adapter(cec->adap, cec->dev);
++	if (ret < 0) {
++		dev_err(cec->dev, "cec register adapter failed\n");
++		cec_unregister_adapter(cec->adap);
++		return NULL;
++	}
++
++	irqs = CECTX_LINE_ERR | CECTX_NACK | CECRX_EOM | CECTX_DONE;
++	hdmirx_cec_write(cec, CEC_INT_MASK_N, irqs);
++
++	/*
++	 * CEC documentation says we must not call cec_delete_adapter
++	 * after a successful call to cec_register_adapter().
++	 */
++	devm_remove_action(cec->dev, hdmirx_cec_del, cec);
++
++	enable_irq(cec->irq);
++
++	return cec;
++}
++
++void snps_hdmirx_cec_unregister(struct hdmirx_cec *cec)
++{
++	disable_irq(cec->irq);
++
++	cec_unregister_adapter(cec->adap);
++}
+diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h
+@@ -0,0 +1,44 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ *
++ * Author: Shunqing Chen <csq@rock-chips.com>
++ */
++
++#ifndef DW_HDMI_RX_CEC_H
++#define DW_HDMI_RX_CEC_H
++
++struct snps_hdmirx_dev;
++
++struct hdmirx_cec_ops {
++	void (*write)(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val);
++	u32 (*read)(struct snps_hdmirx_dev *hdmirx_dev, int reg);
++	void (*enable)(struct snps_hdmirx_dev *hdmirx);
++	void (*disable)(struct snps_hdmirx_dev *hdmirx);
++};
++
++struct hdmirx_cec_data {
++	struct snps_hdmirx_dev *hdmirx;
++	const struct hdmirx_cec_ops *ops;
++	struct device *dev;
++	int irq;
++};
++
++struct hdmirx_cec {
++	struct snps_hdmirx_dev *hdmirx;
++	struct device *dev;
++	const struct hdmirx_cec_ops *ops;
++	u32 addresses;
++	struct cec_adapter *adap;
++	struct cec_msg rx_msg;
++	unsigned int tx_status;
++	bool tx_done;
++	bool rx_done;
++	struct cec_notifier *notify;
++	int irq;
++};
++
++struct hdmirx_cec *snps_hdmirx_cec_register(struct hdmirx_cec_data *data);
++void snps_hdmirx_cec_unregister(struct hdmirx_cec *cec);
++
++#endif /* DW_HDMI_RX_CEC_H */
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 29 Jul 2024 17:29:46 +0200
+Subject: arm64: defconfig: Enable Synopsys HDMI receiver
+
+The Rockchip RK3588 has a built-in HDMI receiver block from
+Synopsys. Let's enable the driver for it.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 111111111111..222222222222 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -840,6 +840,7 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
+ CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
+ CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
+ CONFIG_VIDEO_SUN6I_CSI=m
++CONFIG_VIDEO_SYNOPSYS_HDMIRX=m
+ CONFIG_VIDEO_TI_J721E_CSI2RX=m
+ CONFIG_VIDEO_HANTRO=m
+ CONFIG_VIDEO_IMX219=m
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Thu, 1 Aug 2024 16:47:35 +0300
+Subject: comment v4l2 error on hdmirx
+
+---
+ drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
+@@ -1180,7 +1180,7 @@ static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev)
+ 			break;
+ 
+ 		if (!tx_5v_power_present(hdmirx_dev)) {
+-			v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__);
++			//v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__);
+ 			return -1;
+ 		}
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0130-phy-phy-rockchip-samsung-hdptx-Enable-runtime-PM.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0130-phy-phy-rockchip-samsung-hdptx-Enable-runtime-PM.patch
new file mode 100644
index 000000000000..7efdc0b75ec1
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0130-phy-phy-rockchip-samsung-hdptx-Enable-runtime-PM.patch
@@ -0,0 +1,123 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Tue, 11 Jun 2024 02:06:10 +0300
+Subject: phy: phy-rockchip-samsung-hdptx: Explicitly include pm_runtime.h
+
+Driver makes use of helpers from pm_runtime.h, but relies on the header
+file being implicitly included.
+
+Explicitly pull the header in to avoid potential build failures in some
+configurations.
+
+Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+index 111111111111..222222222222 100644
+--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
++++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+@@ -15,6 +15,7 @@
+ #include <linux/of_platform.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
+ #include <linux/rational.h>
+ #include <linux/regmap.h>
+ #include <linux/reset.h>
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Tue, 11 Jun 2024 02:28:26 +0300
+Subject: phy: phy-rockchip-samsung-hdptx: Enable runtime PM at PHY core level
+
+When a new PHY is created via [devm_]phy_create(), the runtime PM for it
+is not enabled unless the parent device (which creates the PHY) has its
+own runtime PM already enabled.
+
+Move the call to devm_pm_runtime_enable() before devm_phy_create() to
+enable runtime PM at PHY core level.
+
+With this change the ->power_on() and ->power_off() callbacks do not
+require explicit runtime PM management anymore, since the PHY core
+handles that via phy_pm_runtime_{get,put}_sync() when phy_power_on() and
+phy_power_off() are invoked.
+
+Hence drop the now unnecessary calls to pm_runtime_resume_and_get() and
+pm_runtime_put() helpers.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 24 +++-------
+ 1 file changed, 6 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+index 111111111111..222222222222 100644
+--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
++++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+@@ -860,7 +860,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
+ static int rk_hdptx_phy_power_on(struct phy *phy)
+ {
+ 	struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
+-	int ret, bus_width = phy_get_bus_width(hdptx->phy);
++	int bus_width = phy_get_bus_width(hdptx->phy);
+ 	/*
+ 	 * FIXME: Temporary workaround to pass pixel_clk_rate
+ 	 * from the HDMI bridge driver until phy_configure_opts_hdmi
+@@ -871,17 +871,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
+ 	dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
+ 		__func__, bus_width, rate);
+ 
+-	ret = pm_runtime_resume_and_get(hdptx->dev);
+-	if (ret) {
+-		dev_err(hdptx->dev, "Failed to resume phy: %d\n", ret);
+-		return ret;
+-	}
+-
+-	ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
+-	if (ret)
+-		pm_runtime_put(hdptx->dev);
+-
+-	return ret;
++	return rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
+ }
+ 
+ static int rk_hdptx_phy_power_off(struct phy *phy)
+@@ -894,8 +884,6 @@ static int rk_hdptx_phy_power_off(struct phy *phy)
+ 	if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
+ 		rk_hdptx_phy_disable(hdptx);
+ 
+-	pm_runtime_put(hdptx->dev);
+-
+ 	return ret;
+ }
+ 
+@@ -977,6 +965,10 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
+ 		return dev_err_probe(dev, PTR_ERR(hdptx->grf),
+ 				     "Could not get GRF syscon\n");
+ 
++	ret = devm_pm_runtime_enable(dev);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
++
+ 	hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops);
+ 	if (IS_ERR(hdptx->phy))
+ 		return dev_err_probe(dev, PTR_ERR(hdptx->phy),
+@@ -986,10 +978,6 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
+ 	phy_set_drvdata(hdptx->phy, hdptx);
+ 	phy_set_bus_width(hdptx->phy, 8);
+ 
+-	ret = devm_pm_runtime_enable(dev);
+-	if (ret)
+-		return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
+-
+ 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ 	if (IS_ERR(phy_provider))
+ 		return dev_err_probe(dev, PTR_ERR(phy_provider),
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0131-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0131-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch
new file mode 100644
index 000000000000..721cf796ee3d
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0131-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch
@@ -0,0 +1,323 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Mon, 19 Feb 2024 21:53:24 +0200
+Subject: dt-bindings: phy: rockchip,rk3588-hdptx-phy: Add #clock-cells
+
+The HDMI PHY can be used as a clock provider on RK3588 SoC, hence add
+the necessary '#clock-cells' property.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml
++++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml
+@@ -27,6 +27,9 @@ properties:
+       - const: ref
+       - const: apb
+ 
++  "#clock-cells":
++    const: 0
++
+   "#phy-cells":
+     const: 0
+ 
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Tue, 16 Jan 2024 19:27:40 +0200
+Subject: phy: phy-rockchip-samsung-hdptx: Add clock provider support
+
+The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC
+CRU. It provides more accurate clock rates required by VOP2 to improve
+existing support for display modes handling, which is known to be
+problematic when dealing with non-integer refresh rates, among others.
+
+It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be
+used to support HDMI 2.1 4K@120Hz mode.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 195 ++++++++--
+ 1 file changed, 173 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+index 111111111111..222222222222 100644
+--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
++++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+@@ -8,6 +8,7 @@
+  */
+ #include <linux/bitfield.h>
+ #include <linux/clk.h>
++#include <linux/clk-provider.h>
+ #include <linux/delay.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+@@ -191,6 +192,8 @@
+ #define LN3_TX_SER_RATE_SEL_HBR2	BIT(3)
+ #define LN3_TX_SER_RATE_SEL_HBR3	BIT(2)
+ 
++#define HDMI20_MAX_RATE			600000000
++
+ struct lcpll_config {
+ 	u32 bit_rate;
+ 	u8 lcvco_mode_en;
+@@ -273,6 +276,12 @@ struct rk_hdptx_phy {
+ 	struct clk_bulk_data *clks;
+ 	int nr_clks;
+ 	struct reset_control_bulk_data rsts[RST_MAX];
++
++	/* clk provider */
++	struct clk_hw hw;
++	unsigned long rate;
++
++	atomic_t usage_count;
+ };
+ 
+ static const struct ropll_config ropll_tmds_cfg[] = {
+@@ -760,6 +769,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
+ 	struct ropll_config rc = {0};
+ 	int i;
+ 
++	hdptx->rate = rate * 100;
++
+ 	for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
+ 		if (rate == ropll_tmds_cfg[i].bit_rate) {
+ 			cfg = &ropll_tmds_cfg[i];
+@@ -823,19 +834,6 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
+ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
+ 					   unsigned int rate)
+ {
+-	u32 val;
+-	int ret;
+-
+-	ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
+-	if (ret)
+-		return ret;
+-
+-	if (!(val & HDPTX_O_PLL_LOCK_DONE)) {
+-		ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
+-		if (ret)
+-			return ret;
+-	}
+-
+ 	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
+ 
+ 	regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
+@@ -857,10 +855,68 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
+ 	return rk_hdptx_post_enable_lane(hdptx);
+ }
+ 
++static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
++				     unsigned int rate)
++{
++	u32 status;
++	int ret;
++
++	if (atomic_inc_return(&hdptx->usage_count) > 1)
++		return 0;
++
++	ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
++	if (ret)
++		goto dec_usage;
++
++	if (status & HDPTX_O_PLL_LOCK_DONE)
++		dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n");
++
++	if (rate) {
++		ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
++		if (ret)
++			goto dec_usage;
++	}
++
++	return 0;
++
++dec_usage:
++	atomic_dec(&hdptx->usage_count);
++	return ret;
++}
++
++static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force)
++{
++	u32 status;
++	int ret;
++
++	ret = atomic_dec_return(&hdptx->usage_count);
++	if (ret > 0)
++		return 0;
++
++	if (ret < 0) {
++		dev_warn(hdptx->dev, "Usage count underflow!\n");
++		ret = -EINVAL;
++	} else {
++		ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
++		if (!ret) {
++			if (status & HDPTX_O_PLL_LOCK_DONE)
++				rk_hdptx_phy_disable(hdptx);
++			return 0;
++		} else if (force) {
++			return 0;
++		}
++	}
++
++	atomic_inc(&hdptx->usage_count);
++	return ret;
++}
++
+ static int rk_hdptx_phy_power_on(struct phy *phy)
+ {
+ 	struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
+ 	int bus_width = phy_get_bus_width(hdptx->phy);
++	int ret;
++
+ 	/*
+ 	 * FIXME: Temporary workaround to pass pixel_clk_rate
+ 	 * from the HDMI bridge driver until phy_configure_opts_hdmi
+@@ -871,20 +927,22 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
+ 	dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
+ 		__func__, bus_width, rate);
+ 
+-	return rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
++	ret = rk_hdptx_phy_consumer_get(hdptx, rate);
++	if (ret)
++		return ret;
++
++	ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
++	if (ret)
++		rk_hdptx_phy_consumer_put(hdptx, true);
++
++	return ret;
+ }
+ 
+ static int rk_hdptx_phy_power_off(struct phy *phy)
+ {
+ 	struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
+-	u32 val;
+-	int ret;
+ 
+-	ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
+-	if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
+-		rk_hdptx_phy_disable(hdptx);
+-
+-	return ret;
++	return rk_hdptx_phy_consumer_put(hdptx, false);
+ }
+ 
+ static const struct phy_ops rk_hdptx_phy_ops = {
+@@ -893,6 +951,99 @@ static const struct phy_ops rk_hdptx_phy_ops = {
+ 	.owner	   = THIS_MODULE,
+ };
+ 
++static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw)
++{
++	return container_of(hw, struct rk_hdptx_phy, hw);
++}
++
++static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
++{
++	struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
++
++	return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100);
++}
++
++static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
++{
++	struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
++
++	rk_hdptx_phy_consumer_put(hdptx, true);
++}
++
++static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
++						  unsigned long parent_rate)
++{
++	struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
++
++	return hdptx->rate;
++}
++
++static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
++					unsigned long *parent_rate)
++{
++	u32 bit_rate = rate / 100;
++	int i;
++
++	if (rate > HDMI20_MAX_RATE)
++		return rate;
++
++	for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
++		if (bit_rate == ropll_tmds_cfg[i].bit_rate)
++			break;
++
++	if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
++	    !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL))
++		return -EINVAL;
++
++	return rate;
++}
++
++static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
++				     unsigned long parent_rate)
++{
++	struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
++
++	return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
++}
++
++static const struct clk_ops hdptx_phy_clk_ops = {
++	.prepare = rk_hdptx_phy_clk_prepare,
++	.unprepare = rk_hdptx_phy_clk_unprepare,
++	.recalc_rate = rk_hdptx_phy_clk_recalc_rate,
++	.round_rate = rk_hdptx_phy_clk_round_rate,
++	.set_rate = rk_hdptx_phy_clk_set_rate,
++};
++
++static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx)
++{
++	struct device *dev = hdptx->dev;
++	const char *name, *pname;
++	struct clk *refclk;
++	int ret, id;
++
++	refclk = devm_clk_get(dev, "ref");
++	if (IS_ERR(refclk))
++		return dev_err_probe(dev, PTR_ERR(refclk),
++				     "Failed to get ref clock\n");
++
++	id = of_alias_get_id(dev->of_node, "hdptxphy");
++	name = id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0";
++	pname = __clk_get_name(refclk);
++
++	hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops,
++				     CLK_GET_RATE_NOCACHE);
++
++	ret = devm_clk_hw_register(dev, &hdptx->hw);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to register clock\n");
++
++	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw);
++	if (ret)
++		return dev_err_probe(dev, ret,
++				     "Failed to register clk provider\n");
++	return 0;
++}
++
+ static int rk_hdptx_phy_runtime_suspend(struct device *dev)
+ {
+ 	struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
+@@ -987,7 +1138,7 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
+ 	reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
+ 	reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
+ 
+-	return 0;
++	return rk_hdptx_phy_clk_register(hdptx);
+ }
+ 
+ static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0132-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0132-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch
new file mode 100644
index 000000000000..2f76a087e845
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0132-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch
@@ -0,0 +1,547 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Mon, 5 Feb 2024 01:38:48 +0200
+Subject: [WIP] phy: phy-rockchip-samsung-hdptx: Add FRL & EARC support
+
+For upstreaming, this requires extending the standard PHY API to support
+HDMI configuration options [1].
+
+Currently, the bus_width PHY attribute is used to pass clock rate and
+flags for 10-bit color depth, FRL and EARC. This is done by the HDMI
+bridge driver via phy_set_bus_width().
+
+[1]: https://lore.kernel.org/all/20240306101625.795732-3-alexander.stein@ew.tq-group.com/
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 428 +++++++++-
+ 1 file changed, 426 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+index 111111111111..222222222222 100644
+--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
++++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+@@ -193,6 +193,10 @@
+ #define LN3_TX_SER_RATE_SEL_HBR3	BIT(2)
+ 
+ #define HDMI20_MAX_RATE			600000000
++#define DATA_RATE_MASK			0xFFFFFFF
++#define COLOR_DEPTH_MASK		BIT(31)
++#define HDMI_MODE_MASK			BIT(30)
++#define HDMI_EARC_MASK			BIT(29)
+ 
+ struct lcpll_config {
+ 	u32 bit_rate;
+@@ -276,6 +280,7 @@ struct rk_hdptx_phy {
+ 	struct clk_bulk_data *clks;
+ 	int nr_clks;
+ 	struct reset_control_bulk_data rsts[RST_MAX];
++	bool earc_en;
+ 
+ 	/* clk provider */
+ 	struct clk_hw hw;
+@@ -284,6 +289,24 @@ struct rk_hdptx_phy {
+ 	atomic_t usage_count;
+ };
+ 
++static const struct lcpll_config lcpll_cfg[] = {
++	{ 48000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2,
++	  0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, },
++	{ 40000000, 1, 1, 0, 0x68, 0x68, 1, 1, 0, 0, 0, 1, 1, 1, 1, 9, 0, 1, 1,
++	  0, 2, 3, 1, 0, 0x20, 0x0c, 1, 0, },
++	{ 32000000, 1, 1, 1, 0x6b, 0x6b, 1, 1, 0, 1, 2, 1, 1, 1, 1, 9, 1, 2, 1,
++	  0, 0x0d, 0x18, 1, 0, 0x20, 0x0c, 1, 1, },
++};
++
++static const struct ropll_config ropll_frl_cfg[] = {
++	{ 24000000, 0x19, 0x19, 1, 1, 0, 1, 2, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1,
++	  0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
++	{ 18000000, 0x7d, 0x7d, 1, 1, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1,
++	  0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
++	{ 9000000, 0x7d, 0x7d, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1,
++	  0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
++};
++
+ static const struct ropll_config ropll_tmds_cfg[] = {
+ 	{ 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
+ 	  1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
+@@ -459,6 +482,73 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
+ 	REG_SEQ0(CMN_REG(009b), 0x00),
+ };
+ 
++static const struct reg_sequence rk_hdtpx_frl_cmn_init_seq[] = {
++	REG_SEQ0(CMN_REG(0011), 0x00),
++	REG_SEQ0(CMN_REG(0017), 0x00),
++	REG_SEQ0(CMN_REG(0026), 0x53),
++	REG_SEQ0(CMN_REG(0030), 0x00),
++	REG_SEQ0(CMN_REG(0031), 0x20),
++	REG_SEQ0(CMN_REG(0032), 0x30),
++	REG_SEQ0(CMN_REG(0033), 0x0b),
++	REG_SEQ0(CMN_REG(0034), 0x23),
++	REG_SEQ0(CMN_REG(0042), 0xb8),
++	REG_SEQ0(CMN_REG(004e), 0x14),
++	REG_SEQ0(CMN_REG(0074), 0x00),
++	REG_SEQ0(CMN_REG(0081), 0x09),
++	REG_SEQ0(CMN_REG(0086), 0x01),
++	REG_SEQ0(CMN_REG(0087), 0x0c),
++	REG_SEQ0(CMN_REG(009b), 0x10),
++};
++
++static const struct reg_sequence rk_hdtpx_frl_ropll_cmn_init_seq[] = {
++	REG_SEQ0(CMN_REG(0008), 0x00),
++	REG_SEQ0(CMN_REG(001e), 0x14),
++	REG_SEQ0(CMN_REG(0020), 0x00),
++	REG_SEQ0(CMN_REG(0021), 0x00),
++	REG_SEQ0(CMN_REG(0022), 0x11),
++	REG_SEQ0(CMN_REG(0023), 0x00),
++	REG_SEQ0(CMN_REG(0025), 0x00),
++	REG_SEQ0(CMN_REG(0027), 0x00),
++	REG_SEQ0(CMN_REG(0028), 0x00),
++	REG_SEQ0(CMN_REG(002a), 0x01),
++	REG_SEQ0(CMN_REG(002b), 0x00),
++	REG_SEQ0(CMN_REG(002c), 0x00),
++	REG_SEQ0(CMN_REG(002d), 0x00),
++	REG_SEQ0(CMN_REG(002e), 0x00),
++	REG_SEQ0(CMN_REG(002f), 0x04),
++	REG_SEQ0(CMN_REG(003d), 0x40),
++	REG_SEQ0(CMN_REG(005c), 0x25),
++	REG_SEQ0(CMN_REG(0089), 0x00),
++	REG_SEQ0(CMN_REG(0094), 0x00),
++	REG_SEQ0(CMN_REG(0097), 0x02),
++	REG_SEQ0(CMN_REG(0099), 0x04),
++};
++
++static const struct reg_sequence rk_hdtpx_frl_lcpll_cmn_init_seq[] = {
++	REG_SEQ0(CMN_REG(0025), 0x10),
++	REG_SEQ0(CMN_REG(0027), 0x01),
++	REG_SEQ0(CMN_REG(0028), 0x0d),
++	REG_SEQ0(CMN_REG(002e), 0x02),
++	REG_SEQ0(CMN_REG(002f), 0x0d),
++	REG_SEQ0(CMN_REG(003d), 0x00),
++	REG_SEQ0(CMN_REG(0051), 0x00),
++	REG_SEQ0(CMN_REG(0055), 0x00),
++	REG_SEQ0(CMN_REG(0059), 0x11),
++	REG_SEQ0(CMN_REG(005a), 0x03),
++	REG_SEQ0(CMN_REG(005c), 0x05),
++	REG_SEQ0(CMN_REG(005e), 0x07),
++	REG_SEQ0(CMN_REG(0060), 0x01),
++	REG_SEQ0(CMN_REG(0064), 0x07),
++	REG_SEQ0(CMN_REG(0065), 0x00),
++	REG_SEQ0(CMN_REG(0069), 0x00),
++	REG_SEQ0(CMN_REG(006c), 0x00),
++	REG_SEQ0(CMN_REG(0070), 0x01),
++	REG_SEQ0(CMN_REG(0089), 0x02),
++	REG_SEQ0(CMN_REG(0095), 0x00),
++	REG_SEQ0(CMN_REG(0097), 0x00),
++	REG_SEQ0(CMN_REG(0099), 0x00),
++};
++
+ static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
+ 	REG_SEQ0(SB_REG(0114), 0x00),
+ 	REG_SEQ0(SB_REG(0115), 0x00),
+@@ -482,6 +572,17 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
+ 	REG_SEQ0(LNTOP_REG(0205), 0x1f),
+ };
+ 
++static const struct reg_sequence rk_hdtpx_frl_lntop_init_seq[] = {
++	REG_SEQ0(LNTOP_REG(0200), 0x04),
++	REG_SEQ0(LNTOP_REG(0201), 0x00),
++	REG_SEQ0(LNTOP_REG(0202), 0x00),
++	REG_SEQ0(LNTOP_REG(0203), 0xf0),
++	REG_SEQ0(LNTOP_REG(0204), 0xff),
++	REG_SEQ0(LNTOP_REG(0205), 0xff),
++	REG_SEQ0(LNTOP_REG(0206), 0x05),
++	REG_SEQ0(LNTOP_REG(0207), 0x0f),
++};
++
+ static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
+ 	REG_SEQ0(LANE_REG(0303), 0x0c),
+ 	REG_SEQ0(LANE_REG(0307), 0x20),
+@@ -560,6 +661,40 @@ static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
+ 	REG_SEQ0(LANE_REG(0606), 0x1c),
+ };
+ 
++static const struct reg_sequence rk_hdtpx_frl_ropll_lane_init_seq[] = {
++	REG_SEQ0(LANE_REG(0312), 0x3c),
++	REG_SEQ0(LANE_REG(0412), 0x3c),
++	REG_SEQ0(LANE_REG(0512), 0x3c),
++	REG_SEQ0(LANE_REG(0612), 0x3c),
++};
++
++static const struct reg_sequence rk_hdtpx_frl_lcpll_lane_init_seq[] = {
++	REG_SEQ0(LANE_REG(0312), 0x3c),
++	REG_SEQ0(LANE_REG(0412), 0x3c),
++	REG_SEQ0(LANE_REG(0512), 0x3c),
++	REG_SEQ0(LANE_REG(0612), 0x3c),
++	REG_SEQ0(LANE_REG(0303), 0x2f),
++	REG_SEQ0(LANE_REG(0403), 0x2f),
++	REG_SEQ0(LANE_REG(0503), 0x2f),
++	REG_SEQ0(LANE_REG(0603), 0x2f),
++	REG_SEQ0(LANE_REG(0305), 0x03),
++	REG_SEQ0(LANE_REG(0405), 0x03),
++	REG_SEQ0(LANE_REG(0505), 0x03),
++	REG_SEQ0(LANE_REG(0605), 0x03),
++	REG_SEQ0(LANE_REG(0306), 0xfc),
++	REG_SEQ0(LANE_REG(0406), 0xfc),
++	REG_SEQ0(LANE_REG(0506), 0xfc),
++	REG_SEQ0(LANE_REG(0606), 0xfc),
++	REG_SEQ0(LANE_REG(0305), 0x4f),
++	REG_SEQ0(LANE_REG(0405), 0x4f),
++	REG_SEQ0(LANE_REG(0505), 0x4f),
++	REG_SEQ0(LANE_REG(0605), 0x4f),
++	REG_SEQ0(LANE_REG(0304), 0x14),
++	REG_SEQ0(LANE_REG(0404), 0x14),
++	REG_SEQ0(LANE_REG(0504), 0x14),
++	REG_SEQ0(LANE_REG(0604), 0x14),
++};
++
+ static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg)
+ {
+ 	switch (reg) {
+@@ -661,6 +796,47 @@ static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx)
+ 	return 0;
+ }
+ 
++static int rk_hdptx_post_power_up(struct rk_hdptx_phy *hdptx)
++{
++	u32 val;
++	int ret;
++
++	val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
++	       HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
++	regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
++
++	usleep_range(10, 15);
++	reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
++
++	usleep_range(10, 15);
++	val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN;
++	regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
++
++	usleep_range(10, 15);
++	reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
++
++	ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
++				       val & HDPTX_O_PLL_LOCK_DONE, 20, 400);
++	if (ret) {
++		dev_err(hdptx->dev, "Failed to get PHY PLL lock: %d\n", ret);
++		return ret;
++	}
++
++	usleep_range(20, 30);
++	reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
++
++	ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
++				       val & HDPTX_O_PHY_RDY, 100, 5000);
++	if (ret) {
++		dev_err(hdptx->dev, "Failed to get PHY ready: %d\n", ret);
++		return ret;
++	}
++
++	dev_dbg(hdptx->dev, "PHY ready\n");
++
++	return 0;
++}
++
+ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
+ {
+ 	u32 val;
+@@ -690,6 +866,99 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
+ 	regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
+ }
+ 
++static void rk_hdptx_earc_config(struct rk_hdptx_phy *hdptx)
++{
++	regmap_update_bits(hdptx->regmap, SB_REG(0113), SB_RX_RCAL_OPT_CODE_MASK,
++			   FIELD_PREP(SB_RX_RCAL_OPT_CODE_MASK, 1));
++	regmap_write(hdptx->regmap, SB_REG(011c), 0x04);
++	regmap_update_bits(hdptx->regmap, SB_REG(011b), SB_AFC_TOL_MASK,
++			   FIELD_PREP(SB_AFC_TOL_MASK, 3));
++	regmap_write(hdptx->regmap, SB_REG(0109), 0x05);
++
++	regmap_update_bits(hdptx->regmap, SB_REG(0120),
++			   SB_EARC_EN_MASK | SB_EARC_AFC_EN_MASK,
++			   FIELD_PREP(SB_EARC_EN_MASK, 1) |
++			   FIELD_PREP(SB_EARC_AFC_EN_MASK, 1));
++	regmap_update_bits(hdptx->regmap, SB_REG(011b), SB_EARC_SIG_DET_BYPASS_MASK,
++			   FIELD_PREP(SB_EARC_SIG_DET_BYPASS_MASK, 1));
++	regmap_update_bits(hdptx->regmap, SB_REG(011f),
++			   SB_PWM_AFC_CTRL_MASK | SB_RCAL_RSTN_MASK,
++			   FIELD_PREP(SB_PWM_AFC_CTRL_MASK, 0xc) |
++			   FIELD_PREP(SB_RCAL_RSTN_MASK, 1));
++	regmap_update_bits(hdptx->regmap, SB_REG(0115), SB_READY_DELAY_TIME_MASK,
++			   FIELD_PREP(SB_READY_DELAY_TIME_MASK, 2));
++	regmap_update_bits(hdptx->regmap, SB_REG(0113), SB_RX_RTERM_CTRL_MASK,
++			   FIELD_PREP(SB_RX_RTERM_CTRL_MASK, 3));
++	regmap_update_bits(hdptx->regmap, SB_REG(0102), ANA_SB_RXTERM_OFFSP_MASK,
++			   FIELD_PREP(ANA_SB_RXTERM_OFFSP_MASK, 3));
++	regmap_update_bits(hdptx->regmap, SB_REG(0103), ANA_SB_RXTERM_OFFSN_MASK,
++			   FIELD_PREP(ANA_SB_RXTERM_OFFSN_MASK, 3));
++
++	regmap_write(hdptx->regmap, SB_REG(011a), 0x03);
++	regmap_write(hdptx->regmap, SB_REG(0118), 0x0a);
++	regmap_write(hdptx->regmap, SB_REG(011e), 0x6a);
++	regmap_write(hdptx->regmap, SB_REG(011d), 0x67);
++
++	regmap_update_bits(hdptx->regmap, SB_REG(0117), FAST_PULSE_TIME_MASK,
++			   FIELD_PREP(FAST_PULSE_TIME_MASK, 4));
++	regmap_update_bits(hdptx->regmap, SB_REG(0114),
++			   SB_TG_SB_EN_DELAY_TIME_MASK | SB_TG_RXTERM_EN_DELAY_TIME_MASK,
++			   FIELD_PREP(SB_TG_SB_EN_DELAY_TIME_MASK, 2) |
++			   FIELD_PREP(SB_TG_RXTERM_EN_DELAY_TIME_MASK, 2));
++	regmap_update_bits(hdptx->regmap, SB_REG(0105), ANA_SB_TX_HLVL_PROG_MASK,
++			   FIELD_PREP(ANA_SB_TX_HLVL_PROG_MASK, 7));
++	regmap_update_bits(hdptx->regmap, SB_REG(0106), ANA_SB_TX_LLVL_PROG_MASK,
++			   FIELD_PREP(ANA_SB_TX_LLVL_PROG_MASK, 7));
++	regmap_update_bits(hdptx->regmap, SB_REG(010f), ANA_SB_VREG_GAIN_CTRL_MASK,
++			   FIELD_PREP(ANA_SB_VREG_GAIN_CTRL_MASK, 0));
++	regmap_update_bits(hdptx->regmap, SB_REG(0110), ANA_SB_VREG_REF_SEL_MASK,
++			   FIELD_PREP(ANA_SB_VREG_REF_SEL_MASK, 1));
++	regmap_update_bits(hdptx->regmap, SB_REG(0115), SB_TG_OSC_EN_DELAY_TIME_MASK,
++			   FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME_MASK, 2));
++	regmap_update_bits(hdptx->regmap, SB_REG(0116), AFC_RSTN_DELAY_TIME_MASK,
++			   FIELD_PREP(AFC_RSTN_DELAY_TIME_MASK, 2));
++	regmap_update_bits(hdptx->regmap, SB_REG(0109), ANA_SB_DMRX_AFC_DIV_RATIO_MASK,
++			   FIELD_PREP(ANA_SB_DMRX_AFC_DIV_RATIO_MASK, 5));
++	regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK,
++			   FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 1));
++	regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_EN_MASK,
++			   FIELD_PREP(OVRD_SB_EN_MASK, 1));
++	regmap_update_bits(hdptx->regmap, SB_REG(0102), OVRD_SB_RXTERM_EN_MASK,
++			   FIELD_PREP(OVRD_SB_RXTERM_EN_MASK, 1));
++	regmap_update_bits(hdptx->regmap, SB_REG(0105), OVRD_SB_EARC_CMDC_EN_MASK,
++			   FIELD_PREP(OVRD_SB_EARC_CMDC_EN_MASK, 1));
++	regmap_update_bits(hdptx->regmap, SB_REG(010f),
++			   OVRD_SB_VREG_EN_MASK | OVRD_SB_VREG_LPF_BYPASS_MASK,
++			   FIELD_PREP(OVRD_SB_VREG_EN_MASK, 1) |
++			   FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 1));
++	regmap_update_bits(hdptx->regmap, SB_REG(0123), OVRD_SB_READY_MASK,
++			   FIELD_PREP(OVRD_SB_READY_MASK, 1));
++
++	usleep_range(1000, 1100);
++	regmap_update_bits(hdptx->regmap, SB_REG(0103), SB_RX_RESCAL_DONE_MASK,
++			   FIELD_PREP(SB_RX_RESCAL_DONE_MASK, 1));
++	usleep_range(50, 60);
++	regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_EN_MASK,
++			   FIELD_PREP(SB_EN_MASK, 1));
++	usleep_range(50, 60);
++	regmap_update_bits(hdptx->regmap, SB_REG(0102), SB_RXTERM_EN_MASK,
++			   FIELD_PREP(SB_RXTERM_EN_MASK, 1));
++	usleep_range(50, 60);
++	regmap_update_bits(hdptx->regmap, SB_REG(0105), SB_EARC_CMDC_EN_MASK,
++			   FIELD_PREP(SB_EARC_CMDC_EN_MASK, 1));
++	regmap_update_bits(hdptx->regmap, SB_REG(010f), SB_VREG_EN_MASK,
++			   FIELD_PREP(SB_VREG_EN_MASK, 1));
++	usleep_range(50, 60);
++	regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_LPF_BYPASS_MASK,
++			   FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 1));
++	usleep_range(250, 300);
++	regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_LPF_BYPASS_MASK,
++			   FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 0));
++	usleep_range(100, 120);
++	regmap_update_bits(hdptx->regmap, SB_REG(0123), SB_READY_MASK,
++			   FIELD_PREP(SB_READY_MASK, 1));
++}
++
+ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
+ 				      struct ropll_config *cfg)
+ {
+@@ -765,9 +1034,13 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
+ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
+ 					  unsigned int rate)
+ {
++	int i, bus_width = phy_get_bus_width(hdptx->phy);
++	u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0;
+ 	const struct ropll_config *cfg = NULL;
+ 	struct ropll_config rc = {0};
+-	int i;
++
++	if (color_depth)
++		rate = rate * 10 / 8;
+ 
+ 	hdptx->rate = rate * 100;
+ 
+@@ -825,6 +1098,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
+ 	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
+ 			   FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
+ 
++	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK,
++			   FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth));
++
+ 	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN,
+ 			   PLL_PCG_CLK_EN);
+ 
+@@ -852,9 +1128,146 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
+ 	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
+ 	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
+ 
++	if (hdptx->earc_en)
++		rk_hdptx_earc_config(hdptx);
++
+ 	return rk_hdptx_post_enable_lane(hdptx);
+ }
+ 
++static int rk_hdptx_ropll_frl_mode_config(struct rk_hdptx_phy *hdptx,
++					  u32 bus_width)
++{
++	u32 bit_rate = bus_width & DATA_RATE_MASK;
++	u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0;
++	const struct ropll_config *cfg = NULL;
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(ropll_frl_cfg); i++)
++		if (bit_rate == ropll_frl_cfg[i].bit_rate) {
++			cfg = &ropll_frl_cfg[i];
++			break;
++		}
++
++	if (!cfg) {
++		dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
++		return -EINVAL;
++	}
++
++	rk_hdptx_pre_power_up(hdptx);
++
++	reset_control_assert(hdptx->rsts[RST_ROPLL].rstc);
++	usleep_range(10, 20);
++	reset_control_deassert(hdptx->rsts[RST_ROPLL].rstc);
++
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_cmn_init_seq);
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_ropll_cmn_init_seq);
++
++	regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
++	regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
++	regmap_write(hdptx->regmap, CMN_REG(0059),
++		     (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
++	regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4);
++
++	regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
++			   FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en));
++	if (!cfg->sdm_en)
++		regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0);
++
++	regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK,
++			   FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign));
++
++	regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno);
++	regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num);
++
++	regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
++			   FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n));
++
++	regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num);
++	regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno);
++
++	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
++			   FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
++	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK,
++			   FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth));
++
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lntop_init_seq);
++
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_ropll_lane_init_seq);
++
++	if (hdptx->earc_en)
++		rk_hdptx_earc_config(hdptx);
++
++	return rk_hdptx_post_power_up(hdptx);
++}
++
++static int rk_hdptx_lcpll_frl_mode_config(struct rk_hdptx_phy *hdptx,
++					  u32 bus_width)
++{
++	u32 bit_rate = bus_width & DATA_RATE_MASK;
++	u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0;
++	const struct lcpll_config *cfg = NULL;
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(lcpll_cfg); i++)
++		if (bit_rate == lcpll_cfg[i].bit_rate) {
++			cfg = &lcpll_cfg[i];
++			break;
++		}
++
++	if (!cfg) {
++		dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
++		return -EINVAL;
++	}
++
++	rk_hdptx_pre_power_up(hdptx);
++
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_cmn_init_seq);
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lcpll_cmn_init_seq);
++
++	regmap_update_bits(hdptx->regmap, CMN_REG(0008),
++			   LCPLL_EN_MASK | LCPLL_LCVCO_MODE_EN_MASK,
++			   FIELD_PREP(LCPLL_EN_MASK, 1) |
++			   FIELD_PREP(LCPLL_LCVCO_MODE_EN_MASK, cfg->lcvco_mode_en));
++
++	regmap_update_bits(hdptx->regmap, CMN_REG(001e),
++			   LCPLL_PI_EN_MASK | LCPLL_100M_CLK_EN_MASK,
++			   FIELD_PREP(LCPLL_PI_EN_MASK, cfg->pi_en) |
++			   FIELD_PREP(LCPLL_100M_CLK_EN_MASK, cfg->clk_en_100m));
++
++	regmap_write(hdptx->regmap, CMN_REG(0020), cfg->pms_mdiv);
++	regmap_write(hdptx->regmap, CMN_REG(0021), cfg->pms_mdiv_afc);
++	regmap_write(hdptx->regmap, CMN_REG(0022),
++		     (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
++	regmap_write(hdptx->regmap, CMN_REG(0023),
++		     (cfg->pms_sdiv << 4) | cfg->pms_sdiv);
++	regmap_write(hdptx->regmap, CMN_REG(002a), cfg->sdm_deno);
++	regmap_write(hdptx->regmap, CMN_REG(002b), cfg->sdm_num_sign);
++	regmap_write(hdptx->regmap, CMN_REG(002c), cfg->sdm_num);
++
++	regmap_update_bits(hdptx->regmap, CMN_REG(002d), LCPLL_SDC_N_MASK,
++			   FIELD_PREP(LCPLL_SDC_N_MASK, cfg->sdc_n));
++
++	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
++			   FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
++	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK,
++			   FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth));
++
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lntop_init_seq);
++
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
++	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lcpll_lane_init_seq);
++
++	if (hdptx->earc_en)
++		rk_hdptx_earc_config(hdptx);
++
++	return rk_hdptx_post_power_up(hdptx);
++}
++
+ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
+ 				     unsigned int rate)
+ {
+@@ -922,11 +1335,22 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
+ 	 * from the HDMI bridge driver until phy_configure_opts_hdmi
+ 	 * becomes available in the PHY API.
+ 	 */
+-	unsigned int rate = bus_width & 0xfffffff;
++	unsigned int rate = bus_width & DATA_RATE_MASK;
+ 
+ 	dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
+ 		__func__, bus_width, rate);
+ 
++	if (bus_width & HDMI_EARC_MASK)
++		hdptx->earc_en = true;
++	else
++		hdptx->earc_en = false;
++
++	if (bus_width & HDMI_MODE_MASK) {
++		if (rate > 24000000)
++			return rk_hdptx_lcpll_frl_mode_config(hdptx, bus_width);
++		return rk_hdptx_ropll_frl_mode_config(hdptx, bus_width);
++	}
++
+ 	ret = rk_hdptx_phy_consumer_get(hdptx, rate);
+ 	if (ret)
+ 		return ret;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0133-drm-rockchip-vop2-Improve-display-modes-handling.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0133-drm-rockchip-vop2-Improve-display-modes-handling.patch
new file mode 100644
index 000000000000..4caa301abf58
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0133-drm-rockchip-vop2-Improve-display-modes-handling.patch
@@ -0,0 +1,715 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Wed, 27 Mar 2024 20:36:15 +0200
+Subject: [WIP] dt-bindings: display: rockchip-drm: Add optional clocks
+ property
+
+Allow using the clock provided by HDMI0 PHY PLL to improve HDMI output
+support on RK3588 SoC.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml
+@@ -28,6 +28,14 @@ properties:
+       of vop devices. vop definitions as defined in
+       Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
+ 
++  clocks:
++    maxItems: 1
++    description: Optional clock provided by HDMI0 PLL
++
++  clock-names:
++    items:
++      - const: hdmi0_phy_pll
++
+ required:
+   - compatible
+   - ports
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Fri, 3 Nov 2023 19:58:02 +0200
+Subject: [WIP] drm/rockchip: vop2: Improve display modes handling on rk3588
+
+The initial vop2 support for rk3588 in mainline is not able to handle
+all display modes supported by connected displays, e.g.
+2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz.
+
+Additionally, it doesn't cope with non-integer refresh rates like 59.94,
+29.97, 23.98, etc.
+
+Improve HDMI0 clocking in order to support the additional display modes.
+
+Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 553 +++++++++-
+ 1 file changed, 552 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+@@ -5,6 +5,8 @@
+  */
+ #include <linux/bitfield.h>
+ #include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/clkdev.h>
+ #include <linux/component.h>
+ #include <linux/delay.h>
+ #include <linux/iopoll.h>
+@@ -212,6 +214,10 @@ struct vop2 {
+ 	struct clk *hclk;
+ 	struct clk *aclk;
+ 	struct clk *pclk;
++	// [CC:] hack to support additional display modes
++	struct clk *hdmi0_phy_pll;
++	/* list_head of internal clk */
++	struct list_head clk_list_head;
+ 
+ 	/* optional internal rgb encoder */
+ 	struct rockchip_rgb *rgb;
+@@ -220,6 +226,19 @@ struct vop2 {
+ 	struct vop2_win win[];
+ };
+ 
++struct vop2_clk {
++	struct vop2 *vop2;
++	struct list_head list;
++	unsigned long rate;
++	struct clk_hw hw;
++	struct clk_divider div;
++	int div_val;
++	u8 parent_index;
++};
++
++#define to_vop2_clk(_hw) container_of(_hw, struct vop2_clk, hw)
++#define VOP2_MAX_DCLK_RATE	600000 /* kHz */
++
+ #define vop2_output_if_is_hdmi(x)	((x) == ROCKCHIP_VOP2_EP_HDMI0 || \
+ 					 (x) == ROCKCHIP_VOP2_EP_HDMI1)
+ 
+@@ -1476,9 +1495,30 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
+ 				 const struct drm_display_mode *mode,
+ 				 struct drm_display_mode *adj_mode)
+ {
++	struct vop2_video_port *vp = to_vop2_video_port(crtc);
++	struct drm_connector *connector;
++	struct drm_connector_list_iter conn_iter;
++	struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
+ 	drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V |
+ 					CRTC_STEREO_DOUBLE);
+ 
++	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
++		adj_mode->crtc_clock *= 2;
++
++	drm_connector_list_iter_begin(crtc->dev, &conn_iter);
++	drm_for_each_connector_iter(connector, &conn_iter) {
++		if ((new_crtc_state->connector_mask & drm_connector_mask(connector)) &&
++		    ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
++		     (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))) {
++			drm_connector_list_iter_end(&conn_iter);
++			return true;
++		}
++	}
++	drm_connector_list_iter_end(&conn_iter);
++
++	if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE)
++		adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
++						    adj_mode->crtc_clock * 1000), 1000);
+ 	return true;
+ }
+ 
+@@ -1663,6 +1703,31 @@ static unsigned long rk3588_calc_dclk(unsigned long child_clk, unsigned long max
+ 		return 0;
+ }
+ 
++static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name);
++
++static int vop2_cru_set_rate(struct vop2_clk *if_pixclk, struct vop2_clk *if_dclk)
++{
++	int ret = 0;
++
++	if (if_pixclk) {
++		ret =  clk_set_rate(if_pixclk->hw.clk, if_pixclk->rate);
++		if (ret < 0) {
++			DRM_DEV_ERROR(if_pixclk->vop2->dev, "set %s to %ld failed: %d\n",
++				      clk_hw_get_name(&if_pixclk->hw), if_pixclk->rate, ret);
++			return ret;
++		}
++	}
++
++	if (if_dclk) {
++		ret = clk_set_rate(if_dclk->hw.clk, if_dclk->rate);
++		if (ret < 0)
++			DRM_DEV_ERROR(if_dclk->vop2->dev, "set %s to %ld failed %d\n",
++				      clk_hw_get_name(&if_dclk->hw), if_dclk->rate, ret);
++	}
++
++	return ret;
++}
++
+ /*
+  * 4 pixclk/cycle on rk3588
+  * RGB/eDP/HDMI: if_pixclk >= dclk_core
+@@ -1686,6 +1751,72 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
+ 	int K = 1;
+ 
+ 	if (vop2_output_if_is_hdmi(id)) {
++		if (vop2->data->soc_id == 3588 && id == ROCKCHIP_VOP2_EP_HDMI0 &&
++		    vop2->hdmi0_phy_pll) {
++			const char *clk_src_name = "hdmi_edp0_clk_src";
++			const char *clk_parent_name = "dclk";
++			const char *pixclk_name = "hdmi_edp0_pixclk";
++			const char *dclk_name = "hdmi_edp0_dclk";
++			struct vop2_clk *if_clk_src, *if_clk_parent, *if_pixclk, *if_dclk, *dclk, *dclk_core, *dclk_out;
++			char clk_name[32];
++			int ret;
++
++			if_clk_src = vop2_clk_get(vop2, clk_src_name);
++			snprintf(clk_name, sizeof(clk_name), "%s%d", clk_parent_name, vp->id);
++			if_clk_parent = vop2_clk_get(vop2, clk_name);
++			if_pixclk = vop2_clk_get(vop2, pixclk_name);
++			if_dclk = vop2_clk_get(vop2, dclk_name);
++			if (!if_pixclk || !if_clk_parent) {
++				DRM_DEV_ERROR(vop2->dev, "failed to get connector interface clk\n");
++				return -ENODEV;
++			}
++
++			ret = clk_set_parent(if_clk_src->hw.clk, if_clk_parent->hw.clk);
++			if (ret < 0) {
++				DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n",
++					      __clk_get_name(if_clk_parent->hw.clk),
++					      __clk_get_name(if_clk_src->hw.clk), ret);
++				return ret;
++			}
++
++			if (output_mode == ROCKCHIP_OUT_MODE_YUV420)
++				K = 2;
++
++			if_pixclk->rate = (dclk_core_rate << 1) / K;
++			if_dclk->rate = dclk_core_rate / K;
++
++			snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
++			dclk_core = vop2_clk_get(vop2, clk_name);
++
++			snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
++			dclk_out = vop2_clk_get(vop2, clk_name);
++
++			snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
++			dclk = vop2_clk_get(vop2, clk_name);
++			if (v_pixclk <= (VOP2_MAX_DCLK_RATE * 1000)) {
++				if (output_mode == ROCKCHIP_OUT_MODE_YUV420)
++					v_pixclk = v_pixclk >> 1;
++			} else {
++				v_pixclk = v_pixclk >> 2;
++			}
++			clk_set_rate(dclk->hw.clk, v_pixclk);
++
++			if (dclk_core_rate > if_pixclk->rate) {
++				clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
++				ret = vop2_cru_set_rate(if_pixclk, if_dclk);
++			} else {
++				ret = vop2_cru_set_rate(if_pixclk, if_dclk);
++				clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
++			}
++
++			*dclk_core_div = dclk_core->div_val;
++			*dclk_out_div = dclk_out->div_val;
++			*if_pixclk_div = if_pixclk->div_val;
++			*if_dclk_div = if_dclk->div_val;
++
++			return dclk->rate;
++		}
++
+ 		/*
+ 		 * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate
+ 		 * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate
+@@ -1917,6 +2048,22 @@ static int us_to_vertical_line(struct drm_display_mode *mode, int us)
+ 	return us * mode->clock / mode->htotal / 1000;
+ }
+ 
++// [CC:] rework virtual clock
++static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name)
++{
++	struct vop2_clk *clk, *n;
++
++	if (!name)
++		return NULL;
++
++	list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) {
++		if (!strcmp(clk_hw_get_name(&clk->hw), name))
++			return clk;
++	}
++
++	return NULL;
++}
++
+ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
+ 				    struct drm_atomic_state *state)
+ {
+@@ -1944,6 +2091,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
+ 	u32 val, polflags;
+ 	int ret;
+ 	struct drm_encoder *encoder;
++	char clk_name[32];
++	struct vop2_clk *dclk;
+ 
+ 	drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
+ 		hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
+@@ -2044,11 +2193,38 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
+ 		dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV;
+-		clock *= 2;
++		// [CC:] done via mode_fixup
++		// clock *= 2;
+ 	}
+ 
+ 	vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
+ 
++	snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
++	dclk = vop2_clk_get(vop2, clk_name);
++	if (dclk) {
++		/*
++		 * use HDMI_PHY_PLL as dclk source under 4K@60 if it is available,
++		 * otherwise use system cru as dclk source.
++		 */
++		drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
++			struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
++
++			// [CC:] Using PHY PLL to handle all display modes
++			if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) {
++				clk_get_rate(vop2->hdmi0_phy_pll);
++
++				if (mode->crtc_clock <= VOP2_MAX_DCLK_RATE) {
++					ret = clk_set_parent(vp->dclk, vop2->hdmi0_phy_pll);
++					if (ret < 0)
++						DRM_WARN("failed to set clock parent for %s\n",
++							 __clk_get_name(vp->dclk));
++				}
++
++				clock = dclk->rate;
++			}
++		}
++	}
++
+ 	clk_set_rate(vp->dclk, clock);
+ 
+ 	vop2_post_config(crtc);
+@@ -2504,7 +2680,43 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc,
+ 	spin_unlock_irq(&crtc->dev->event_lock);
+ }
+ 
++static enum drm_mode_status
++vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
++{
++	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
++	struct vop2_video_port *vp = to_vop2_video_port(crtc);
++	struct vop2 *vop2 = vp->vop2;
++	const struct vop2_data *vop2_data = vop2->data;
++	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
++	int request_clock = mode->clock;
++	int clock;
++
++	if (mode->hdisplay > vp_data->max_output.width)
++		return MODE_BAD_HVALUE;
++
++	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
++		request_clock *= 2;
++
++	if (request_clock <= VOP2_MAX_DCLK_RATE) {
++		clock = request_clock;
++	} else {
++		request_clock = request_clock >> 2;
++		clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000;
++	}
++
++	/*
++	 * Hdmi or DisplayPort request a Accurate clock.
++	 */
++	if (vcstate->output_type == DRM_MODE_CONNECTOR_HDMIA ||
++	    vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort)
++		if (clock != request_clock)
++			return MODE_CLOCK_RANGE;
++
++	return MODE_OK;
++}
++
+ static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
++	.mode_valid = vop2_crtc_mode_valid,
+ 	.mode_fixup = vop2_crtc_mode_fixup,
+ 	.atomic_check = vop2_crtc_atomic_check,
+ 	.atomic_begin = vop2_crtc_atomic_begin,
+@@ -3074,6 +3286,336 @@ static const struct regmap_config vop2_regmap_config = {
+ 	.cache_type	= REGCACHE_MAPLE,
+ };
+ 
++/*
++ * BEGIN virtual clock
++ */
++#define PLL_RATE_MIN	30000000
++
++#define cru_dbg(format, ...) do {				\
++		if (cru_debug)					\
++			pr_info("%s: " format, __func__, ## __VA_ARGS__); \
++	} while (0)
++
++#define PNAME(x) static const char *const x[]
++
++enum vop_clk_branch_type {
++	branch_mux,
++	branch_divider,
++	branch_factor,
++	branch_virtual,
++};
++
++#define VIR(cname)						\
++	{							\
++		.branch_type	= branch_virtual,		\
++		.name		= cname,			\
++	}
++
++
++#define MUX(cname, pnames, f)			\
++	{							\
++		.branch_type	= branch_mux,			\
++		.name		= cname,			\
++		.parent_names	= pnames,			\
++		.num_parents	= ARRAY_SIZE(pnames),		\
++		.flags		= f,				\
++	}
++
++#define FACTOR(cname, pname,  f)			\
++	{							\
++		.branch_type	= branch_factor,		\
++		.name		= cname,			\
++		.parent_names	= (const char *[]){ pname },	\
++		.num_parents	= 1,				\
++		.flags		= f,				\
++	}
++
++#define DIV(cname, pname, f, w)			\
++	{							\
++		.branch_type	= branch_divider,		\
++		.name		= cname,			\
++		.parent_names	= (const char *[]){ pname },	\
++		.num_parents	= 1,				\
++		.flags		= f,				\
++		.div_width	= w,				\
++	}
++
++struct vop2_clk_branch {
++	enum vop_clk_branch_type	branch_type;
++	const char			*name;
++	const char			*const *parent_names;
++	u8				num_parents;
++	unsigned long			flags;
++	u8				div_shift;
++	u8				div_width;
++	u8				div_flags;
++};
++
++PNAME(mux_port0_dclk_src_p)		= { "dclk0", "dclk1" };
++PNAME(mux_port2_dclk_src_p)		= { "dclk2", "dclk1" };
++PNAME(mux_dp_pixclk_p)			= { "dclk_out0", "dclk_out1", "dclk_out2" };
++PNAME(mux_hdmi_edp_clk_src_p)		= { "dclk0", "dclk1", "dclk2" };
++PNAME(mux_mipi_clk_src_p)		= { "dclk_out1", "dclk_out2", "dclk_out3" };
++PNAME(mux_dsc_8k_clk_src_p)		= { "dclk0", "dclk1", "dclk2", "dclk3" };
++PNAME(mux_dsc_4k_clk_src_p)		= { "dclk0", "dclk1", "dclk2", "dclk3" };
++
++/*
++ * We only use this clk driver calculate the div
++ * of dclk_core/dclk_out/if_pixclk/if_dclk and
++ * the rate of the dclk from the soc.
++ *
++ * We don't touch the cru in the vop here, as
++ * these registers has special read andy write
++ * limits.
++ */
++static struct vop2_clk_branch rk3588_vop_clk_branches[] = {
++	VIR("dclk0"),
++	VIR("dclk1"),
++	VIR("dclk2"),
++	VIR("dclk3"),
++
++	MUX("port0_dclk_src", mux_port0_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
++	DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
++	DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
++
++	FACTOR("port1_dclk_src", "dclk1", CLK_SET_RATE_PARENT),
++	DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
++	DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
++
++	MUX("port2_dclk_src", mux_port2_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
++	DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
++	DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
++
++	FACTOR("port3_dclk_src", "dclk3", CLK_SET_RATE_PARENT),
++	DIV("dclk_core3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
++	DIV("dclk_out3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
++
++	MUX("dp0_pixclk", mux_dp_pixclk_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
++	MUX("dp1_pixclk", mux_dp_pixclk_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
++
++	MUX("hdmi_edp0_clk_src", mux_hdmi_edp_clk_src_p,
++	    CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
++	DIV("hdmi_edp0_dclk", "hdmi_edp0_clk_src", 0, 2),
++	DIV("hdmi_edp0_pixclk", "hdmi_edp0_clk_src", CLK_SET_RATE_PARENT, 1),
++
++	MUX("hdmi_edp1_clk_src", mux_hdmi_edp_clk_src_p,
++	    CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
++	DIV("hdmi_edp1_dclk", "hdmi_edp1_clk_src", 0, 2),
++	DIV("hdmi_edp1_pixclk", "hdmi_edp1_clk_src", CLK_SET_RATE_PARENT, 1),
++
++	MUX("mipi0_clk_src", mux_mipi_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
++	DIV("mipi0_pixclk", "mipi0_clk_src", CLK_SET_RATE_PARENT, 2),
++
++	MUX("mipi1_clk_src", mux_mipi_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
++	DIV("mipi1_pixclk", "mipi1_clk_src", CLK_SET_RATE_PARENT, 2),
++
++	FACTOR("rgb_pixclk", "port3_dclk_src", CLK_SET_RATE_PARENT),
++
++	MUX("dsc_8k_txp_clk_src", mux_dsc_8k_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
++	DIV("dsc_8k_txp_clk", "dsc_8k_txp_clk_src", 0, 2),
++	DIV("dsc_8k_pxl_clk", "dsc_8k_txp_clk_src", 0, 2),
++	DIV("dsc_8k_cds_clk", "dsc_8k_txp_clk_src", 0, 2),
++
++	MUX("dsc_4k_txp_clk_src", mux_dsc_4k_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
++	DIV("dsc_4k_txp_clk", "dsc_4k_txp_clk_src", 0, 2),
++	DIV("dsc_4k_pxl_clk", "dsc_4k_txp_clk_src", 0, 2),
++	DIV("dsc_4k_cds_clk", "dsc_4k_txp_clk_src", 0, 2),
++};
++
++static unsigned long clk_virtual_recalc_rate(struct clk_hw *hw,
++		unsigned long parent_rate)
++{
++	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
++
++	return (unsigned long)vop2_clk->rate;
++}
++
++static long clk_virtual_round_rate(struct clk_hw *hw, unsigned long rate,
++				unsigned long *prate)
++{
++	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
++
++	vop2_clk->rate = rate;
++
++	return rate;
++}
++
++static int clk_virtual_set_rate(struct clk_hw *hw, unsigned long rate,
++				unsigned long parent_rate)
++{
++	return 0;
++}
++
++const struct clk_ops clk_virtual_ops = {
++	.round_rate = clk_virtual_round_rate,
++	.set_rate = clk_virtual_set_rate,
++	.recalc_rate = clk_virtual_recalc_rate,
++};
++
++static u8 vop2_mux_get_parent(struct clk_hw *hw)
++{
++	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
++
++	// cru_dbg("%s index: %d\n", clk_hw_get_name(hw), vop2_clk->parent_index);
++	return vop2_clk->parent_index;
++}
++
++static int vop2_mux_set_parent(struct clk_hw *hw, u8 index)
++{
++	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
++
++	vop2_clk->parent_index = index;
++
++	// cru_dbg("%s index: %d\n", clk_hw_get_name(hw), index);
++	return 0;
++}
++
++static int vop2_clk_mux_determine_rate(struct clk_hw *hw,
++			     struct clk_rate_request *req)
++{
++	// cru_dbg("%s  %ld(min: %ld max: %ld)\n",
++	//        clk_hw_get_name(hw), req->rate, req->min_rate, req->max_rate);
++	return __clk_mux_determine_rate(hw, req);
++}
++
++static const struct clk_ops vop2_mux_clk_ops = {
++	.get_parent = vop2_mux_get_parent,
++	.set_parent = vop2_mux_set_parent,
++	.determine_rate = vop2_clk_mux_determine_rate,
++};
++
++#define div_mask(width)	((1 << (width)) - 1)
++
++static int vop2_div_get_val(unsigned long rate, unsigned long parent_rate)
++{
++	unsigned int div, value;
++
++	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
++
++	value = ilog2(div);
++
++	return value;
++}
++
++static unsigned long vop2_clk_div_recalc_rate(struct clk_hw *hw,
++					  unsigned long parent_rate)
++{
++	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
++	unsigned long rate;
++	unsigned int div;
++
++	div =  1 << vop2_clk->div_val;
++	rate = parent_rate / div;
++
++	// cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, parent_rate);
++	return rate;
++}
++
++static long vop2_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
++				unsigned long *prate)
++{
++	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
++
++	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
++		if (*prate < rate)
++			*prate = rate;
++		if ((*prate >> vop2_clk->div.width) > rate)
++			*prate = rate;
++
++		if ((*prate % rate))
++			*prate = rate;
++
++		/* SOC PLL can't output a too low pll freq */
++		if (*prate < PLL_RATE_MIN)
++			*prate = rate << vop2_clk->div.width;
++	}
++
++	// cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, *prate);
++	return rate;
++}
++
++static int vop2_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
++{
++	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
++	int div_val;
++
++	div_val = vop2_div_get_val(rate, parent_rate);
++	vop2_clk->div_val = div_val;
++
++	// cru_dbg("%s prate: %ld rate: %ld div_val: %d\n",
++	//        clk_hw_get_name(hw), parent_rate, rate, div_val);
++	return 0;
++}
++
++static const struct clk_ops vop2_div_clk_ops = {
++	.recalc_rate = vop2_clk_div_recalc_rate,
++	.round_rate = vop2_clk_div_round_rate,
++	.set_rate = vop2_clk_div_set_rate,
++};
++
++static struct clk *vop2_clk_register(struct vop2 *vop2, struct vop2_clk_branch *branch)
++{
++	struct clk_init_data init = {};
++	struct vop2_clk *vop2_clk;
++	struct clk *clk;
++
++	vop2_clk = devm_kzalloc(vop2->dev, sizeof(*vop2_clk), GFP_KERNEL);
++	if (!vop2_clk)
++		return ERR_PTR(-ENOMEM);
++
++	vop2_clk->vop2 = vop2;
++	vop2_clk->hw.init = &init;
++	vop2_clk->div.shift = branch->div_shift;
++	vop2_clk->div.width = branch->div_width;
++
++	init.name = branch->name;
++	init.flags = branch->flags;
++	init.num_parents = branch->num_parents;
++	init.parent_names = branch->parent_names;
++	if (branch->branch_type == branch_divider) {
++		init.ops = &vop2_div_clk_ops;
++	} else if (branch->branch_type == branch_virtual) {
++		init.ops = &clk_virtual_ops;
++		init.num_parents = 0;
++		init.parent_names = NULL;
++	} else {
++		init.ops = &vop2_mux_clk_ops;
++	}
++
++	clk = devm_clk_register(vop2->dev, &vop2_clk->hw);
++	if (!IS_ERR(clk))
++		list_add_tail(&vop2_clk->list, &vop2->clk_list_head);
++	else
++		DRM_DEV_ERROR(vop2->dev, "Register %s failed\n", branch->name);
++
++	return clk;
++}
++
++static int vop2_clk_init(struct vop2 *vop2)
++{
++	struct vop2_clk_branch *branch = rk3588_vop_clk_branches;
++	unsigned int nr_clk = ARRAY_SIZE(rk3588_vop_clk_branches);
++	unsigned int idx;
++	struct vop2_clk *clk, *n;
++
++	INIT_LIST_HEAD(&vop2->clk_list_head);
++
++	if (vop2->data->soc_id < 3588 || vop2->hdmi0_phy_pll == NULL)
++		return 0;
++
++	list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) {
++		list_del(&clk->list);
++	}
++
++	for (idx = 0; idx < nr_clk; idx++, branch++)
++		vop2_clk_register(vop2, branch);
++
++	return 0;
++}
++/*
++ * END virtual clock
++ */
++
+ static int vop2_bind(struct device *dev, struct device *master, void *data)
+ {
+ 	struct platform_device *pdev = to_platform_device(dev);
+@@ -3167,6 +3709,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
+ 		return PTR_ERR(vop2->pclk);
+ 	}
+ 
++	vop2->hdmi0_phy_pll = devm_clk_get_optional(vop2->drm->dev, "hdmi0_phy_pll");
++	if (IS_ERR(vop2->hdmi0_phy_pll)) {
++		DRM_DEV_ERROR(vop2->dev, "failed to get hdmi0_phy_pll source\n");
++		return PTR_ERR(vop2->hdmi0_phy_pll);
++	}
++
+ 	vop2->irq = platform_get_irq(pdev, 0);
+ 	if (vop2->irq < 0) {
+ 		drm_err(vop2->drm, "cannot find irq for vop2\n");
+@@ -3183,6 +3731,9 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
+ 	if (ret)
+ 		return ret;
+ 
++	// [CC:] rework virtual clock
++	vop2_clk_init(vop2);
++
+ 	ret = vop2_find_rgb_encoder(vop2);
+ 	if (ret >= 0) {
+ 		vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0134-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0134-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch
new file mode 100644
index 000000000000..2c8539458c64
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0134-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch
@@ -0,0 +1,2603 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Fri, 26 Jul 2024 02:54:52 +0300
+Subject: dt-bindings: display: bridge: Add schema for Synopsys DW HDMI QP TX
+ IP
+
+Add dt-binding schema containing the common properties for the Synopsys
+DesignWare HDMI QP TX controller.
+
+Note this is not a full dt-binding specification, but is meant to be
+referenced by platform-specific bindings for this IP core.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml | 66 ++++++++++
+ 1 file changed, 66 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml
+@@ -0,0 +1,66 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi-qp.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Common Properties for Synopsys DesignWare HDMI QP TX Controller IP
++
++maintainers:
++  - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
++
++description: |
++  This document defines device tree properties for the Synopsys DesignWare
++  HDMI 2.1 Quad-Pixel (QP) TX controller IP core.
++  It doesn't constitute a device tree binding specification by itself, but
++  is meant to be referenced by platform-specific device tree bindings.
++
++  When referenced from platform device tree bindings, the properties defined
++  in this document are defined as follows. The platform device tree bindings
++  are responsible for defining whether each property is required or optional.
++
++properties:
++  reg:
++    maxItems: 1
++
++  clocks:
++    minItems: 4
++    maxItems: 6
++    items:
++      - description: Peripheral/APB bus clock
++      - description: EARC RX biphase clock
++      - description: Reference clock
++      - description: Audio interface clock
++    additionalItems: true
++
++  clock-names:
++    minItems: 4
++    maxItems: 6
++    items:
++      - const: pclk
++      - const: earc
++      - const: ref
++      - const: aud
++    additionalItems: true
++
++  interrupts:
++    minItems: 4
++    maxItems: 5
++    items:
++      - description: AVP Unit interrupt
++      - description: CEC interrupt
++      - description: eARC RX interrupt
++      - description: Main Unit interrupt
++    additionalItems: true
++
++  interrupt-names:
++    minItems: 4
++    maxItems: 5
++    items:
++      - const: avp
++      - const: cec
++      - const: earc
++      - const: main
++    additionalItems: true
++
++additionalProperties: true
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Mon, 20 May 2024 14:49:50 +0300
+Subject: drm/bridge: synopsys: Add DW HDMI QP TX Controller driver
+
+The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX Controller supports
+the following features, among others:
+
+* Fixed Rate Link (FRL)
+* Display Stream Compression (DSC)
+* 4K@120Hz and 8K@60Hz video modes
+* Variable Refresh Rate (VRR) including Quick Media Switching (QMS), aka
+  Cinema VRR
+* Fast Vactive (FVA), aka Quick Frame Transport (QFT)
+* SCDC I2C DDC access
+* TMDS Scrambler enabling 2160p@60Hz with RGB/YCbCr4:4:4
+* YCbCr4:2:0 enabling 2160p@60Hz at lower HDMI link speeds
+* Multi-stream audio
+* Enhanced Audio Return Channel (EARC)
+
+Add driver to enable basic support, i.e. RGB output up to 4K@60Hz,
+without audio, CEC or any HDMI 2.1 specific features.
+
+Co-developed-by: Algea Cao <algea.cao@rock-chips.com>
+Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ drivers/gpu/drm/bridge/synopsys/Kconfig      |   8 +
+ drivers/gpu/drm/bridge/synopsys/Makefile     |   2 +
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 748 +++++++++
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h | 834 ++++++++++
+ include/drm/bridge/dw_hdmi_qp.h              |  37 +
+ 5 files changed, 1629 insertions(+)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
++++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
+@@ -46,6 +46,14 @@ config DRM_DW_HDMI_CEC
+ 	  Support the CE interface which is part of the Synopsys
+ 	  Designware HDMI block.
+ 
++config DRM_DW_HDMI_QP
++	tristate
++	select DRM_DISPLAY_HDMI_HELPER
++	select DRM_DISPLAY_HDMI_STATE_HELPER
++	select DRM_DISPLAY_HELPER
++	select DRM_KMS_HELPER
++	select REGMAP_MMIO
++
+ config DRM_DW_MIPI_DSI
+ 	tristate
+ 	select DRM_KMS_HELPER
+diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/bridge/synopsys/Makefile
++++ b/drivers/gpu/drm/bridge/synopsys/Makefile
+@@ -5,4 +5,6 @@ obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o
+ obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
+ obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
+ 
++obj-$(CONFIG_DRM_DW_HDMI_QP) += dw-hdmi-qp.o
++
+ obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+@@ -0,0 +1,748 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2024 Collabora Ltd.
++ *
++ * Author: Algea Cao <algea.cao@rock-chips.com>
++ * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
++ */
++#include <linux/clk.h>
++#include <linux/completion.h>
++#include <linux/hdmi.h>
++#include <linux/i2c.h>
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++
++#include <drm/bridge/dw_hdmi_qp.h>
++#include <drm/display/drm_hdmi_state_helper.h>
++#include <drm/display/drm_scdc_helper.h>
++
++#include <drm/drm_atomic.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_bridge.h>
++#include <drm/drm_connector.h>
++#include <drm/drm_edid.h>
++
++#include <sound/hdmi-codec.h>
++
++#include "dw-hdmi-qp.h"
++
++#define DDC_CI_ADDR		0x37
++#define DDC_SEGMENT_ADDR	0x30
++
++#define SCDC_MIN_SOURCE_VERSION	0x1
++
++#define HDMI14_MAX_TMDSCLK	340000000
++
++struct dw_hdmi_qp_i2c {
++	struct i2c_adapter	adap;
++
++	struct mutex		lock;	/* used to serialize data transfers */
++	struct completion	cmp;
++	u8			stat;
++
++	u8			slave_reg;
++	bool			is_regaddr;
++	bool			is_segment;
++};
++
++struct dw_hdmi_qp {
++	struct drm_bridge bridge;
++
++	struct device *dev;
++	struct dw_hdmi_qp_i2c *i2c;
++
++	struct {
++		const struct dw_hdmi_qp_phy_ops *ops;
++		void *data;
++	} phy;
++
++	struct clk *ref_clk;
++
++	struct drm_connector *curr_conn;
++	unsigned long long pix_clock;
++
++	struct regmap *regm;
++};
++
++/* Filter out invalid setups to avoid configuring SCDC and scrambling */
++static bool dw_hdmi_qp_support_scdc(struct dw_hdmi_qp *hdmi,
++				    const struct drm_display_info *display)
++{
++	/* Disable if no DDC bus */
++	if (!hdmi->bridge.ddc)
++		return false;
++
++	/* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
++	if (!display->hdmi.scdc.supported ||
++	    !display->hdmi.scdc.scrambling.supported)
++		return false;
++
++	/*
++	 * Disable if display only support low TMDS rates and scrambling
++	 * for low rates is not supported either
++	 */
++	if (!display->hdmi.scdc.scrambling.low_rates &&
++	    display->max_tmds_clock <= 340000)
++		return false;
++
++	return true;
++}
++
++int dw_hdmi_qp_set_refclk_rate(struct dw_hdmi_qp *hdmi, unsigned long rate)
++{
++	return clk_set_rate(hdmi->ref_clk, rate);
++}
++EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_refclk_rate);
++
++/*
++ * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
++ * - The Source shall suspend transmission of the TMDS clock and data
++ *
++ * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
++ *   from a 0 to a 1 or from a 1 to a 0
++ *
++ * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
++ *   the time the TMDS_Bit_Clock_Ratio bit is written until resuming
++ *   transmission of TMDS clock and data
++ *
++ * To respect the 100ms max delay, the dw_hdmi_qp_set_high_tmds_clock_ratio()
++ * helper should be called right before enabling the TMDS Clock and Data in
++ * the PHY configuration callback.
++ */
++void dw_hdmi_qp_set_high_tmds_clock_ratio(struct dw_hdmi_qp *hdmi,
++					  const struct drm_display_info *display)
++{
++	bool set;
++
++	if (hdmi->curr_conn && dw_hdmi_qp_support_scdc(hdmi, display)) {
++		set = (hdmi->pix_clock > HDMI14_MAX_TMDSCLK);
++		drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, set);
++	}
++}
++EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_high_tmds_clock_ratio);
++
++static void dw_hdmi_qp_write(struct dw_hdmi_qp *hdmi, unsigned int val,
++			     int offset)
++{
++	regmap_write(hdmi->regm, offset, val);
++}
++
++static unsigned int dw_hdmi_qp_read(struct dw_hdmi_qp *hdmi, int offset)
++{
++	unsigned int val = 0;
++
++	regmap_read(hdmi->regm, offset, &val);
++
++	return val;
++}
++
++static void dw_hdmi_qp_mod(struct dw_hdmi_qp *hdmi, unsigned int data,
++			   unsigned int mask, unsigned int reg)
++{
++	regmap_update_bits(hdmi->regm, reg, mask, data);
++}
++
++static int dw_hdmi_qp_i2c_read(struct dw_hdmi_qp *hdmi,
++			       unsigned char *buf, unsigned int length)
++{
++	struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
++	int stat;
++
++	if (!i2c->is_regaddr) {
++		dev_dbg(hdmi->dev, "set read register address to 0\n");
++		i2c->slave_reg = 0x00;
++		i2c->is_regaddr = true;
++	}
++
++	while (length--) {
++		reinit_completion(&i2c->cmp);
++
++		dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
++			       I2CM_INTERFACE_CONTROL0);
++
++		if (i2c->is_segment)
++			dw_hdmi_qp_mod(hdmi, I2CM_EXT_READ, I2CM_WR_MASK,
++				       I2CM_INTERFACE_CONTROL0);
++		else
++			dw_hdmi_qp_mod(hdmi, I2CM_FM_READ, I2CM_WR_MASK,
++				       I2CM_INTERFACE_CONTROL0);
++
++		stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
++		if (!stat) {
++			dev_err(hdmi->dev, "i2c read timed out\n");
++			dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
++			return -EAGAIN;
++		}
++
++		/* Check for error condition on the bus */
++		if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
++			dev_err(hdmi->dev, "i2c read error\n");
++			dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
++			return -EIO;
++		}
++
++		*buf++ = dw_hdmi_qp_read(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff;
++		dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
++	}
++
++	i2c->is_segment = false;
++
++	return 0;
++}
++
++static int dw_hdmi_qp_i2c_write(struct dw_hdmi_qp *hdmi,
++				unsigned char *buf, unsigned int length)
++{
++	struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
++	int stat;
++
++	if (!i2c->is_regaddr) {
++		/* Use the first write byte as register address */
++		i2c->slave_reg = buf[0];
++		length--;
++		buf++;
++		i2c->is_regaddr = true;
++	}
++
++	while (length--) {
++		reinit_completion(&i2c->cmp);
++
++		dw_hdmi_qp_write(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3);
++		dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
++			       I2CM_INTERFACE_CONTROL0);
++		dw_hdmi_qp_mod(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK,
++			       I2CM_INTERFACE_CONTROL0);
++
++		stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
++		if (!stat) {
++			dev_err(hdmi->dev, "i2c write time out!\n");
++			dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
++			return -EAGAIN;
++		}
++
++		/* Check for error condition on the bus */
++		if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
++			dev_err(hdmi->dev, "i2c write nack!\n");
++			dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
++			return -EIO;
++		}
++
++		dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
++	}
++
++	return 0;
++}
++
++static int dw_hdmi_qp_i2c_xfer(struct i2c_adapter *adap,
++			       struct i2c_msg *msgs, int num)
++{
++	struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap);
++	struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
++	u8 addr = msgs[0].addr;
++	int i, ret = 0;
++
++	if (addr == DDC_CI_ADDR)
++		/*
++		 * The internal I2C controller does not support the multi-byte
++		 * read and write operations needed for DDC/CI.
++		 * FIXME: Blacklist the DDC/CI address until we filter out
++		 * unsupported I2C operations.
++		 */
++		return -EOPNOTSUPP;
++
++	for (i = 0; i < num; i++) {
++		if (msgs[i].len == 0) {
++			dev_err(hdmi->dev,
++				"unsupported transfer %d/%d, no data\n",
++				i + 1, num);
++			return -EOPNOTSUPP;
++		}
++	}
++
++	mutex_lock(&i2c->lock);
++
++	/* Unmute DONE and ERROR interrupts */
++	dw_hdmi_qp_mod(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
++		       I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
++		       MAINUNIT_1_INT_MASK_N);
++
++	/* Set slave device address taken from the first I2C message */
++	if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1)
++		addr = DDC_ADDR;
++
++	dw_hdmi_qp_mod(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0);
++
++	/* Set slave device register address on transfer */
++	i2c->is_regaddr = false;
++
++	/* Set segment pointer for I2C extended read mode operation */
++	i2c->is_segment = false;
++
++	for (i = 0; i < num; i++) {
++		if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
++			i2c->is_segment = true;
++			dw_hdmi_qp_mod(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR,
++				       I2CM_INTERFACE_CONTROL1);
++			dw_hdmi_qp_mod(hdmi, *msgs[i].buf << 7, I2CM_SEG_PTR,
++				       I2CM_INTERFACE_CONTROL1);
++		} else {
++			if (msgs[i].flags & I2C_M_RD)
++				ret = dw_hdmi_qp_i2c_read(hdmi, msgs[i].buf,
++							  msgs[i].len);
++			else
++				ret = dw_hdmi_qp_i2c_write(hdmi, msgs[i].buf,
++							   msgs[i].len);
++		}
++		if (ret < 0)
++			break;
++	}
++
++	if (!ret)
++		ret = num;
++
++	/* Mute DONE and ERROR interrupts */
++	dw_hdmi_qp_mod(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N,
++		       MAINUNIT_1_INT_MASK_N);
++
++	mutex_unlock(&i2c->lock);
++
++	return ret;
++}
++
++static u32 dw_hdmi_qp_i2c_func(struct i2c_adapter *adapter)
++{
++	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++static const struct i2c_algorithm dw_hdmi_qp_algorithm = {
++	.master_xfer	= dw_hdmi_qp_i2c_xfer,
++	.functionality	= dw_hdmi_qp_i2c_func,
++};
++
++static struct i2c_adapter *dw_hdmi_qp_i2c_adapter(struct dw_hdmi_qp *hdmi)
++{
++	struct dw_hdmi_qp_i2c *i2c;
++	struct i2c_adapter *adap;
++	int ret;
++
++	i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
++	if (!i2c)
++		return ERR_PTR(-ENOMEM);
++
++	mutex_init(&i2c->lock);
++	init_completion(&i2c->cmp);
++
++	adap = &i2c->adap;
++	adap->owner = THIS_MODULE;
++	adap->dev.parent = hdmi->dev;
++	adap->algo = &dw_hdmi_qp_algorithm;
++	strscpy(adap->name, "DesignWare HDMI QP", sizeof(adap->name));
++
++	i2c_set_adapdata(adap, hdmi);
++
++	ret = devm_i2c_add_adapter(hdmi->dev, adap);
++	if (ret) {
++		dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
++		devm_kfree(hdmi->dev, i2c);
++		return ERR_PTR(ret);
++	}
++
++	hdmi->i2c = i2c;
++	dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
++
++	return adap;
++}
++
++static int dw_hdmi_qp_config_avi_infoframe(struct dw_hdmi_qp *hdmi,
++					   const u8 *buffer, size_t len)
++{
++	u32 val, i, j;
++
++	if (len != HDMI_INFOFRAME_SIZE(AVI)) {
++		dev_err(hdmi->dev, "failed to configure avi infoframe\n");
++		return -EINVAL;
++	}
++
++	/*
++	 * DW HDMI QP IP uses a different byte format from standard AVI info
++	 * frames, though generally the bits are in the correct bytes.
++	 */
++	val = buffer[1] << 8 | buffer[2] << 16;
++	dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS0);
++
++	for (i = 0; i < 4; i++) {
++		for (j = 0; j < 4; j++) {
++			if (i * 4 + j >= 14)
++				break;
++			if (!j)
++				val = buffer[i * 4 + j + 3];
++			val |= buffer[i * 4 + j + 3] << (8 * j);
++		}
++
++		dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS1 + i * 4);
++	}
++
++	dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
++
++	dw_hdmi_qp_mod(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
++		       PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN);
++
++	return 0;
++}
++
++static int dw_hdmi_qp_config_drm_infoframe(struct dw_hdmi_qp *hdmi,
++					   const u8 *buffer, size_t len)
++{
++	u32 val, i;
++
++	if (len != HDMI_INFOFRAME_SIZE(DRM)) {
++		dev_err(hdmi->dev, "failed to configure drm infoframe\n");
++		return -EINVAL;
++	}
++
++	dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
++
++	val = buffer[1] << 8 | buffer[2] << 16;
++	dw_hdmi_qp_write(hdmi, val, PKT_DRMI_CONTENTS0);
++
++	for (i = 0; i <= buffer[2]; i++) {
++		if (i % 4 == 0)
++			val = buffer[3 + i];
++		val |= buffer[3 + i] << ((i % 4) * 8);
++
++		if ((i % 4 == 3) || i == buffer[2])
++			dw_hdmi_qp_write(hdmi, val,
++					 PKT_DRMI_CONTENTS1 + ((i / 4) * 4));
++	}
++
++	dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
++	dw_hdmi_qp_mod(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN,
++		       PKTSCHED_PKT_EN);
++
++	return 0;
++}
++
++static void dw_hdmi_qp_setup(struct dw_hdmi_qp *hdmi,
++			     struct drm_connector *connector)
++{
++	bool scramb;
++	u8 ver;
++
++	if (!connector->display_info.is_hdmi) {
++		dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
++
++		dw_hdmi_qp_mod(hdmi, HDCP2_BYPASS, HDCP2_BYPASS,
++			       HDCP2LOGIC_CONFIG0);
++		dw_hdmi_qp_mod(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0);
++
++		return;
++	}
++
++	dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
++
++	dw_hdmi_qp_mod(hdmi, 0, OPMODE_DVI, LINK_CONFIG0);
++	dw_hdmi_qp_mod(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0);
++
++	scramb = (hdmi->pix_clock > HDMI14_MAX_TMDSCLK);
++
++	if (dw_hdmi_qp_support_scdc(hdmi, &connector->display_info)) {
++		if (scramb) {
++			drm_scdc_readb(hdmi->bridge.ddc, SCDC_SINK_VERSION, &ver);
++			drm_scdc_writeb(hdmi->bridge.ddc, SCDC_SOURCE_VERSION,
++					min_t(u8, ver, SCDC_MIN_SOURCE_VERSION));
++		}
++
++		drm_scdc_set_high_tmds_clock_ratio(connector, scramb);
++		drm_scdc_set_scrambling(connector, scramb);
++	}
++
++	dw_hdmi_qp_write(hdmi, scramb, SCRAMB_CONFIG0);
++}
++
++static int dw_hdmi_qp_bridge_atomic_check(struct drm_bridge *bridge,
++					  struct drm_bridge_state *bridge_state,
++					  struct drm_crtc_state *crtc_state,
++					  struct drm_connector_state *conn_state)
++{
++	struct dw_hdmi_qp *hdmi = bridge->driver_private;
++	int ret;
++
++	ret = drm_atomic_helper_connector_hdmi_check(conn_state->connector,
++						     conn_state->state);
++	if (ret)
++		dev_dbg(hdmi->dev, "%s failed: %d\n", __func__, ret);
++
++	return ret;
++}
++
++static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge,
++					    struct drm_bridge_state *old_state)
++{
++	struct dw_hdmi_qp *hdmi = bridge->driver_private;
++	struct drm_atomic_state *state = old_state->base.state;
++	struct drm_connector *connector;
++	struct drm_connector_state *conn_state;
++
++	connector = drm_atomic_get_new_connector_for_encoder(state,
++							     bridge->encoder);
++	conn_state = drm_atomic_get_new_connector_state(state, connector);
++
++	hdmi->pix_clock = conn_state->hdmi.tmds_char_rate;
++	hdmi->curr_conn = connector;
++
++	hdmi->phy.ops->init(hdmi, hdmi->phy.data, &connector->display_info);
++
++	dw_hdmi_qp_setup(hdmi, connector);
++
++	drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
++}
++
++static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge,
++					     struct drm_bridge_state *old_state)
++{
++	struct dw_hdmi_qp *hdmi = bridge->driver_private;
++
++	hdmi->curr_conn = NULL;
++	hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
++}
++
++static enum drm_connector_status
++dw_hdmi_qp_bridge_detect(struct drm_bridge *bridge)
++{
++	struct dw_hdmi_qp *hdmi = bridge->driver_private;
++
++	return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
++}
++
++static const struct drm_edid *
++dw_hdmi_qp_bridge_edid_read(struct drm_bridge *bridge,
++			    struct drm_connector *connector)
++{
++	struct dw_hdmi_qp *hdmi = bridge->driver_private;
++	const struct drm_edid *drm_edid;
++
++	if (!bridge->ddc)
++		return NULL;
++
++	drm_edid = drm_edid_read_ddc(connector, bridge->ddc);
++	if (!drm_edid)
++		dev_dbg(hdmi->dev, "failed to get edid\n");
++
++	return drm_edid;
++}
++
++static int dw_hdmi_qp_bridge_clear_infoframe(struct drm_bridge *bridge,
++					     enum hdmi_infoframe_type type)
++{
++	struct dw_hdmi_qp *hdmi = bridge->driver_private;
++
++	switch (type) {
++	case HDMI_INFOFRAME_TYPE_AVI:
++		dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
++			       PKTSCHED_PKT_EN);
++		break;
++
++	case HDMI_INFOFRAME_TYPE_DRM:
++		dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
++		break;
++
++	default:
++		dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type);
++	}
++
++	return 0;
++}
++
++static int dw_hdmi_qp_bridge_write_infoframe(struct drm_bridge *bridge,
++					     enum hdmi_infoframe_type type,
++					     const u8 *buffer, size_t len)
++{
++	struct dw_hdmi_qp *hdmi = bridge->driver_private;
++
++	dw_hdmi_qp_bridge_clear_infoframe(bridge, type);
++
++	switch (type) {
++	case HDMI_INFOFRAME_TYPE_AVI:
++		return dw_hdmi_qp_config_avi_infoframe(hdmi, buffer, len);
++
++	case HDMI_INFOFRAME_TYPE_DRM:
++		return dw_hdmi_qp_config_drm_infoframe(hdmi, buffer, len);
++
++	default:
++		dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type);
++		return 0;
++	}
++}
++
++static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs = {
++	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
++	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
++	.atomic_reset = drm_atomic_helper_bridge_reset,
++	.atomic_check = dw_hdmi_qp_bridge_atomic_check,
++	.atomic_enable = dw_hdmi_qp_bridge_atomic_enable,
++	.atomic_disable = dw_hdmi_qp_bridge_atomic_disable,
++	.detect = dw_hdmi_qp_bridge_detect,
++	.edid_read = dw_hdmi_qp_bridge_edid_read,
++	.hdmi_clear_infoframe = dw_hdmi_qp_bridge_clear_infoframe,
++	.hdmi_write_infoframe = dw_hdmi_qp_bridge_write_infoframe,
++};
++
++static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id)
++{
++	struct dw_hdmi_qp *hdmi = dev_id;
++	struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
++	u32 stat;
++
++	stat = dw_hdmi_qp_read(hdmi, MAINUNIT_1_INT_STATUS);
++
++	i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ |
++			    I2CM_NACK_RCVD_IRQ);
++
++	if (i2c->stat) {
++		dw_hdmi_qp_write(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR);
++		complete(&i2c->cmp);
++	}
++
++	if (stat)
++		return IRQ_HANDLED;
++
++	return IRQ_NONE;
++}
++
++static const struct regmap_config dw_hdmi_qp_regmap_config = {
++	.reg_bits	= 32,
++	.val_bits	= 32,
++	.reg_stride	= 4,
++	.max_register	= EARCRX_1_INT_FORCE,
++};
++
++static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *hdmi)
++{
++	dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N);
++	dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N);
++	dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0);
++
++	/* Software reset */
++	dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
++
++	dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0);
++
++	dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0);
++
++	/* Clear DONE and ERROR interrupts */
++	dw_hdmi_qp_write(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR,
++			 MAINUNIT_1_INT_CLEAR);
++
++	if (hdmi->phy.ops->setup_hpd)
++		hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
++}
++
++struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
++				   struct drm_encoder *encoder,
++				   const struct dw_hdmi_qp_plat_data *plat_data)
++{
++	static const char * const clk_names[] = {
++		"pclk", "earc", "aud", "ref" /* keep "ref" last */
++	};
++	struct device *dev = &pdev->dev;
++	struct dw_hdmi_qp *hdmi;
++	void __iomem *regs;
++	struct clk *clk;
++	int irq, ret, i;
++
++	if (!plat_data->phy_ops || !plat_data->phy_ops->init ||
++	    !plat_data->phy_ops->disable || !plat_data->phy_ops->read_hpd) {
++		dev_err(dev, "Missing platform PHY ops\n");
++		return ERR_PTR(-ENODEV);
++	}
++
++	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
++	if (!hdmi)
++		return ERR_PTR(-ENOMEM);
++
++	hdmi->dev = dev;
++
++	regs = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(regs))
++		return regs;
++
++	hdmi->regm = devm_regmap_init_mmio(dev, regs, &dw_hdmi_qp_regmap_config);
++	if (IS_ERR(hdmi->regm)) {
++		dev_err(dev, "Failed to configure regmap\n");
++		return ERR_CAST(hdmi->regm);
++	}
++
++	for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
++		clk = devm_clk_get_enabled(hdmi->dev, clk_names[i]);
++
++		if (IS_ERR(clk)) {
++			if (PTR_ERR(clk) != -EPROBE_DEFER)
++				dev_err(dev, "Failed to get %s clock\n",
++					clk_names[i]);
++			return ERR_CAST(clk);
++		}
++	}
++	hdmi->ref_clk = clk;
++
++	hdmi->phy.ops = plat_data->phy_ops;
++	hdmi->phy.data = plat_data->phy_data;
++
++	dw_hdmi_qp_init_hw(hdmi);
++
++	irq = platform_get_irq_byname(pdev, "main");
++	if (irq < 0)
++		return ERR_PTR(irq);
++
++	ret = devm_request_threaded_irq(dev, irq,
++					dw_hdmi_qp_main_hardirq, NULL,
++					IRQF_SHARED, dev_name(dev), hdmi);
++	if (ret)
++		return ERR_PTR(ret);
++
++	hdmi->bridge.driver_private = hdmi;
++	hdmi->bridge.funcs = &dw_hdmi_qp_bridge_funcs;
++	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT |
++			   DRM_BRIDGE_OP_EDID |
++			   DRM_BRIDGE_OP_HDMI |
++			   DRM_BRIDGE_OP_HPD;
++	hdmi->bridge.of_node = pdev->dev.of_node;
++	hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
++	hdmi->bridge.vendor = "Synopsys";
++	hdmi->bridge.product = "DW HDMI QP TX";
++
++	hdmi->bridge.ddc = dw_hdmi_qp_i2c_adapter(hdmi);
++	if (IS_ERR(hdmi->bridge.ddc))
++		hdmi->bridge.ddc = NULL;
++
++	ret = devm_drm_bridge_add(dev, &hdmi->bridge);
++	if (ret)
++		return ERR_PTR(ret);
++
++	ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL,
++				DRM_BRIDGE_ATTACH_NO_CONNECTOR);
++	if (ret)
++		return ERR_PTR(ret);
++
++	return hdmi;
++}
++EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind);
++
++void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi)
++{
++}
++EXPORT_SYMBOL_GPL(dw_hdmi_qp_unbind);
++
++void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi)
++{
++	dw_hdmi_qp_init_hw(hdmi);
++}
++EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume);
++
++MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
++MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>");
++MODULE_DESCRIPTION("DW HDMI QP transmitter driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:dw-hdmi-qp");
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h
+@@ -0,0 +1,834 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) Rockchip Electronics Co.Ltd
++ * Author:
++ *      Algea Cao <algea.cao@rock-chips.com>
++ */
++#ifndef __DW_HDMI_QP_H__
++#define __DW_HDMI_QP_H__
++
++#include <linux/bits.h>
++
++/* Main Unit Registers */
++#define CORE_ID						0x0
++#define VER_NUMBER					0x4
++#define VER_TYPE					0x8
++#define CONFIG_REG					0xc
++#define CONFIG_CEC					BIT(28)
++#define CONFIG_AUD_UD					BIT(23)
++#define CORE_TIMESTAMP_HHMM				0x14
++#define CORE_TIMESTAMP_MMDD				0x18
++#define CORE_TIMESTAMP_YYYY				0x1c
++/* Reset Manager Registers */
++#define GLOBAL_SWRESET_REQUEST				0x40
++#define EARCRX_CMDC_SWINIT_P				BIT(27)
++#define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P		BIT(10)
++#define GLOBAL_SWDISABLE				0x44
++#define CEC_SWDISABLE					BIT(17)
++#define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE		BIT(10)
++#define AVP_DATAPATH_VIDEO_SWDISABLE			BIT(6)
++#define RESET_MANAGER_CONFIG0				0x48
++#define RESET_MANAGER_STATUS0				0x50
++#define RESET_MANAGER_STATUS1				0x54
++#define RESET_MANAGER_STATUS2				0x58
++/* Timer Base Registers */
++#define TIMER_BASE_CONFIG0				0x80
++#define TIMER_BASE_STATUS0				0x84
++/* CMU Registers */
++#define CMU_CONFIG0					0xa0
++#define CMU_CONFIG1					0xa4
++#define CMU_CONFIG2					0xa8
++#define CMU_CONFIG3					0xac
++#define CMU_STATUS					0xb0
++#define DISPLAY_CLK_MONITOR				0x3f
++#define DISPLAY_CLK_LOCKED				0X15
++#define EARC_BPCLK_OFF					BIT(9)
++#define AUDCLK_OFF					BIT(7)
++#define LINKQPCLK_OFF					BIT(5)
++#define VIDQPCLK_OFF					BIT(3)
++#define IPI_CLK_OFF					BIT(1)
++#define CMU_IPI_CLK_FREQ				0xb4
++#define CMU_VIDQPCLK_FREQ				0xb8
++#define CMU_LINKQPCLK_FREQ				0xbc
++#define CMU_AUDQPCLK_FREQ				0xc0
++#define CMU_EARC_BPCLK_FREQ				0xc4
++/* I2CM Registers */
++#define I2CM_SM_SCL_CONFIG0				0xe0
++#define I2CM_FM_SCL_CONFIG0				0xe4
++#define I2CM_CONFIG0					0xe8
++#define I2CM_CONTROL0					0xec
++#define I2CM_STATUS0					0xf0
++#define I2CM_INTERFACE_CONTROL0				0xf4
++#define I2CM_ADDR					0xff000
++#define I2CM_SLVADDR					0xfe0
++#define I2CM_WR_MASK					0x1e
++#define I2CM_EXT_READ					BIT(4)
++#define I2CM_SHORT_READ					BIT(3)
++#define I2CM_FM_READ					BIT(2)
++#define I2CM_FM_WRITE					BIT(1)
++#define I2CM_FM_EN					BIT(0)
++#define I2CM_INTERFACE_CONTROL1				0xf8
++#define I2CM_SEG_PTR					0x7f80
++#define I2CM_SEG_ADDR					0x7f
++#define I2CM_INTERFACE_WRDATA_0_3			0xfc
++#define I2CM_INTERFACE_WRDATA_4_7			0x100
++#define I2CM_INTERFACE_WRDATA_8_11			0x104
++#define I2CM_INTERFACE_WRDATA_12_15			0x108
++#define I2CM_INTERFACE_RDDATA_0_3			0x10c
++#define I2CM_INTERFACE_RDDATA_4_7			0x110
++#define I2CM_INTERFACE_RDDATA_8_11			0x114
++#define I2CM_INTERFACE_RDDATA_12_15			0x118
++/* SCDC Registers */
++#define SCDC_CONFIG0					0x140
++#define SCDC_I2C_FM_EN					BIT(12)
++#define SCDC_UPD_FLAGS_AUTO_CLR				BIT(6)
++#define SCDC_UPD_FLAGS_POLL_EN				BIT(4)
++#define SCDC_CONTROL0					0x148
++#define SCDC_STATUS0					0x150
++#define STATUS_UPDATE					BIT(0)
++#define FRL_START					BIT(4)
++#define FLT_UPDATE					BIT(5)
++/* FLT Registers */
++#define FLT_CONFIG0					0x160
++#define FLT_CONFIG1					0x164
++#define FLT_CONFIG2					0x168
++#define FLT_CONTROL0					0x170
++/*  Main Unit 2 Registers */
++#define MAINUNIT_STATUS0				0x180
++/* Video Interface Registers */
++#define VIDEO_INTERFACE_CONFIG0				0x800
++#define VIDEO_INTERFACE_CONFIG1				0x804
++#define VIDEO_INTERFACE_CONFIG2				0x808
++#define VIDEO_INTERFACE_CONTROL0			0x80c
++#define VIDEO_INTERFACE_STATUS0				0x814
++/* Video Packing Registers */
++#define VIDEO_PACKING_CONFIG0				0x81c
++/* Audio Interface Registers */
++#define AUDIO_INTERFACE_CONFIG0				0x820
++#define AUD_IF_SEL_MSK					0x3
++#define AUD_IF_SPDIF					0x2
++#define AUD_IF_I2S					0x1
++#define AUD_IF_PAI					0x0
++#define AUD_FIFO_INIT_ON_OVF_MSK			BIT(2)
++#define AUD_FIFO_INIT_ON_OVF_EN				BIT(2)
++#define I2S_LINES_EN_MSK				GENMASK(7, 4)
++#define I2S_LINES_EN(x)					BIT((x) + 4)
++#define I2S_BPCUV_RCV_MSK				BIT(12)
++#define I2S_BPCUV_RCV_EN				BIT(12)
++#define I2S_BPCUV_RCV_DIS				0
++#define SPDIF_LINES_EN					GENMASK(19, 16)
++#define AUD_FORMAT_MSK					GENMASK(26, 24)
++#define AUD_3DOBA					(0x7 << 24)
++#define AUD_3DASP					(0x6 << 24)
++#define AUD_MSOBA					(0x5 << 24)
++#define AUD_MSASP					(0x4 << 24)
++#define AUD_HBR						(0x3 << 24)
++#define AUD_DST						(0x2 << 24)
++#define AUD_OBA						(0x1 << 24)
++#define AUD_ASP						(0x0 << 24)
++#define AUDIO_INTERFACE_CONFIG1				0x824
++#define AUDIO_INTERFACE_CONTROL0			0x82c
++#define AUDIO_FIFO_CLR_P				BIT(0)
++#define AUDIO_INTERFACE_STATUS0				0x834
++/* Frame Composer Registers */
++#define FRAME_COMPOSER_CONFIG0				0x840
++#define FRAME_COMPOSER_CONFIG1				0x844
++#define FRAME_COMPOSER_CONFIG2				0x848
++#define FRAME_COMPOSER_CONFIG3				0x84c
++#define FRAME_COMPOSER_CONFIG4				0x850
++#define FRAME_COMPOSER_CONFIG5				0x854
++#define FRAME_COMPOSER_CONFIG6				0x858
++#define FRAME_COMPOSER_CONFIG7				0x85c
++#define FRAME_COMPOSER_CONFIG8				0x860
++#define FRAME_COMPOSER_CONFIG9				0x864
++#define FRAME_COMPOSER_CONTROL0				0x86c
++/* Video Monitor Registers */
++#define VIDEO_MONITOR_CONFIG0				0x880
++#define VIDEO_MONITOR_STATUS0				0x884
++#define VIDEO_MONITOR_STATUS1				0x888
++#define VIDEO_MONITOR_STATUS2				0x88c
++#define VIDEO_MONITOR_STATUS3				0x890
++#define VIDEO_MONITOR_STATUS4				0x894
++#define VIDEO_MONITOR_STATUS5				0x898
++#define VIDEO_MONITOR_STATUS6				0x89c
++/* HDCP2 Logic Registers */
++#define HDCP2LOGIC_CONFIG0				0x8e0
++#define HDCP2_BYPASS					BIT(0)
++#define HDCP2LOGIC_ESM_GPIO_IN				0x8e4
++#define HDCP2LOGIC_ESM_GPIO_OUT				0x8e8
++/* HDCP14 Registers */
++#define HDCP14_CONFIG0					0x900
++#define HDCP14_CONFIG1					0x904
++#define HDCP14_CONFIG2					0x908
++#define HDCP14_CONFIG3					0x90c
++#define HDCP14_KEY_SEED					0x914
++#define HDCP14_KEY_H					0x918
++#define HDCP14_KEY_L					0x91c
++#define HDCP14_KEY_STATUS				0x920
++#define HDCP14_AKSV_H					0x924
++#define HDCP14_AKSV_L					0x928
++#define HDCP14_AN_H					0x92c
++#define HDCP14_AN_L					0x930
++#define HDCP14_STATUS0					0x934
++#define HDCP14_STATUS1					0x938
++/* Scrambler Registers */
++#define SCRAMB_CONFIG0					0x960
++/* Video Configuration Registers */
++#define LINK_CONFIG0					0x968
++#define OPMODE_FRL_4LANES				BIT(8)
++#define OPMODE_DVI					BIT(4)
++#define OPMODE_FRL					BIT(0)
++/* TMDS FIFO Registers */
++#define TMDS_FIFO_CONFIG0				0x970
++#define TMDS_FIFO_CONTROL0				0x974
++/* FRL RSFEC Registers */
++#define FRL_RSFEC_CONFIG0				0xa20
++#define FRL_RSFEC_STATUS0				0xa30
++/* FRL Packetizer Registers */
++#define FRL_PKTZ_CONFIG0				0xa40
++#define FRL_PKTZ_CONTROL0				0xa44
++#define FRL_PKTZ_CONTROL1				0xa50
++#define FRL_PKTZ_STATUS1				0xa54
++/* Packet Scheduler Registers */
++#define PKTSCHED_CONFIG0				0xa80
++#define PKTSCHED_PRQUEUE0_CONFIG0			0xa84
++#define PKTSCHED_PRQUEUE1_CONFIG0			0xa88
++#define PKTSCHED_PRQUEUE2_CONFIG0			0xa8c
++#define PKTSCHED_PRQUEUE2_CONFIG1			0xa90
++#define PKTSCHED_PRQUEUE2_CONFIG2			0xa94
++#define PKTSCHED_PKT_CONFIG0				0xa98
++#define PKTSCHED_PKT_CONFIG1				0xa9c
++#define PKTSCHED_DRMI_FIELDRATE				BIT(13)
++#define PKTSCHED_AVI_FIELDRATE				BIT(12)
++#define PKTSCHED_PKT_CONFIG2				0xaa0
++#define PKTSCHED_PKT_CONFIG3				0xaa4
++#define PKTSCHED_PKT_EN					0xaa8
++#define PKTSCHED_DRMI_TX_EN				BIT(17)
++#define PKTSCHED_AUDI_TX_EN				BIT(15)
++#define PKTSCHED_AVI_TX_EN				BIT(13)
++#define PKTSCHED_EMP_CVTEM_TX_EN			BIT(10)
++#define PKTSCHED_AMD_TX_EN				BIT(8)
++#define PKTSCHED_GCP_TX_EN				BIT(3)
++#define PKTSCHED_AUDS_TX_EN				BIT(2)
++#define PKTSCHED_ACR_TX_EN				BIT(1)
++#define PKTSCHED_NULL_TX_EN				BIT(0)
++#define PKTSCHED_PKT_CONTROL0				0xaac
++#define PKTSCHED_PKT_SEND				0xab0
++#define PKTSCHED_PKT_STATUS0				0xab4
++#define PKTSCHED_PKT_STATUS1				0xab8
++#define PKT_NULL_CONTENTS0				0xb00
++#define PKT_NULL_CONTENTS1				0xb04
++#define PKT_NULL_CONTENTS2				0xb08
++#define PKT_NULL_CONTENTS3				0xb0c
++#define PKT_NULL_CONTENTS4				0xb10
++#define PKT_NULL_CONTENTS5				0xb14
++#define PKT_NULL_CONTENTS6				0xb18
++#define PKT_NULL_CONTENTS7				0xb1c
++#define PKT_ACP_CONTENTS0				0xb20
++#define PKT_ACP_CONTENTS1				0xb24
++#define PKT_ACP_CONTENTS2				0xb28
++#define PKT_ACP_CONTENTS3				0xb2c
++#define PKT_ACP_CONTENTS4				0xb30
++#define PKT_ACP_CONTENTS5				0xb34
++#define PKT_ACP_CONTENTS6				0xb38
++#define PKT_ACP_CONTENTS7				0xb3c
++#define PKT_ISRC1_CONTENTS0				0xb40
++#define PKT_ISRC1_CONTENTS1				0xb44
++#define PKT_ISRC1_CONTENTS2				0xb48
++#define PKT_ISRC1_CONTENTS3				0xb4c
++#define PKT_ISRC1_CONTENTS4				0xb50
++#define PKT_ISRC1_CONTENTS5				0xb54
++#define PKT_ISRC1_CONTENTS6				0xb58
++#define PKT_ISRC1_CONTENTS7				0xb5c
++#define PKT_ISRC2_CONTENTS0				0xb60
++#define PKT_ISRC2_CONTENTS1				0xb64
++#define PKT_ISRC2_CONTENTS2				0xb68
++#define PKT_ISRC2_CONTENTS3				0xb6c
++#define PKT_ISRC2_CONTENTS4				0xb70
++#define PKT_ISRC2_CONTENTS5				0xb74
++#define PKT_ISRC2_CONTENTS6				0xb78
++#define PKT_ISRC2_CONTENTS7				0xb7c
++#define PKT_GMD_CONTENTS0				0xb80
++#define PKT_GMD_CONTENTS1				0xb84
++#define PKT_GMD_CONTENTS2				0xb88
++#define PKT_GMD_CONTENTS3				0xb8c
++#define PKT_GMD_CONTENTS4				0xb90
++#define PKT_GMD_CONTENTS5				0xb94
++#define PKT_GMD_CONTENTS6				0xb98
++#define PKT_GMD_CONTENTS7				0xb9c
++#define PKT_AMD_CONTENTS0				0xba0
++#define PKT_AMD_CONTENTS1				0xba4
++#define PKT_AMD_CONTENTS2				0xba8
++#define PKT_AMD_CONTENTS3				0xbac
++#define PKT_AMD_CONTENTS4				0xbb0
++#define PKT_AMD_CONTENTS5				0xbb4
++#define PKT_AMD_CONTENTS6				0xbb8
++#define PKT_AMD_CONTENTS7				0xbbc
++#define PKT_VSI_CONTENTS0				0xbc0
++#define PKT_VSI_CONTENTS1				0xbc4
++#define PKT_VSI_CONTENTS2				0xbc8
++#define PKT_VSI_CONTENTS3				0xbcc
++#define PKT_VSI_CONTENTS4				0xbd0
++#define PKT_VSI_CONTENTS5				0xbd4
++#define PKT_VSI_CONTENTS6				0xbd8
++#define PKT_VSI_CONTENTS7				0xbdc
++#define PKT_AVI_CONTENTS0				0xbe0
++#define HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT	BIT(4)
++#define HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR		0x04
++#define HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR		0x08
++#define HDMI_FC_AVICONF2_IT_CONTENT_VALID		0x80
++#define PKT_AVI_CONTENTS1				0xbe4
++#define PKT_AVI_CONTENTS2				0xbe8
++#define PKT_AVI_CONTENTS3				0xbec
++#define PKT_AVI_CONTENTS4				0xbf0
++#define PKT_AVI_CONTENTS5				0xbf4
++#define PKT_AVI_CONTENTS6				0xbf8
++#define PKT_AVI_CONTENTS7				0xbfc
++#define PKT_SPDI_CONTENTS0				0xc00
++#define PKT_SPDI_CONTENTS1				0xc04
++#define PKT_SPDI_CONTENTS2				0xc08
++#define PKT_SPDI_CONTENTS3				0xc0c
++#define PKT_SPDI_CONTENTS4				0xc10
++#define PKT_SPDI_CONTENTS5				0xc14
++#define PKT_SPDI_CONTENTS6				0xc18
++#define PKT_SPDI_CONTENTS7				0xc1c
++#define PKT_AUDI_CONTENTS0				0xc20
++#define PKT_AUDI_CONTENTS1				0xc24
++#define PKT_AUDI_CONTENTS2				0xc28
++#define PKT_AUDI_CONTENTS3				0xc2c
++#define PKT_AUDI_CONTENTS4				0xc30
++#define PKT_AUDI_CONTENTS5				0xc34
++#define PKT_AUDI_CONTENTS6				0xc38
++#define PKT_AUDI_CONTENTS7				0xc3c
++#define PKT_NVI_CONTENTS0				0xc40
++#define PKT_NVI_CONTENTS1				0xc44
++#define PKT_NVI_CONTENTS2				0xc48
++#define PKT_NVI_CONTENTS3				0xc4c
++#define PKT_NVI_CONTENTS4				0xc50
++#define PKT_NVI_CONTENTS5				0xc54
++#define PKT_NVI_CONTENTS6				0xc58
++#define PKT_NVI_CONTENTS7				0xc5c
++#define PKT_DRMI_CONTENTS0				0xc60
++#define PKT_DRMI_CONTENTS1				0xc64
++#define PKT_DRMI_CONTENTS2				0xc68
++#define PKT_DRMI_CONTENTS3				0xc6c
++#define PKT_DRMI_CONTENTS4				0xc70
++#define PKT_DRMI_CONTENTS5				0xc74
++#define PKT_DRMI_CONTENTS6				0xc78
++#define PKT_DRMI_CONTENTS7				0xc7c
++#define PKT_GHDMI1_CONTENTS0				0xc80
++#define PKT_GHDMI1_CONTENTS1				0xc84
++#define PKT_GHDMI1_CONTENTS2				0xc88
++#define PKT_GHDMI1_CONTENTS3				0xc8c
++#define PKT_GHDMI1_CONTENTS4				0xc90
++#define PKT_GHDMI1_CONTENTS5				0xc94
++#define PKT_GHDMI1_CONTENTS6				0xc98
++#define PKT_GHDMI1_CONTENTS7				0xc9c
++#define PKT_GHDMI2_CONTENTS0				0xca0
++#define PKT_GHDMI2_CONTENTS1				0xca4
++#define PKT_GHDMI2_CONTENTS2				0xca8
++#define PKT_GHDMI2_CONTENTS3				0xcac
++#define PKT_GHDMI2_CONTENTS4				0xcb0
++#define PKT_GHDMI2_CONTENTS5				0xcb4
++#define PKT_GHDMI2_CONTENTS6				0xcb8
++#define PKT_GHDMI2_CONTENTS7				0xcbc
++/* EMP Packetizer Registers */
++#define PKT_EMP_CONFIG0					0xce0
++#define PKT_EMP_CONTROL0				0xcec
++#define PKT_EMP_CONTROL1				0xcf0
++#define PKT_EMP_CONTROL2				0xcf4
++#define PKT_EMP_VTEM_CONTENTS0				0xd00
++#define PKT_EMP_VTEM_CONTENTS1				0xd04
++#define PKT_EMP_VTEM_CONTENTS2				0xd08
++#define PKT_EMP_VTEM_CONTENTS3				0xd0c
++#define PKT_EMP_VTEM_CONTENTS4				0xd10
++#define PKT_EMP_VTEM_CONTENTS5				0xd14
++#define PKT_EMP_VTEM_CONTENTS6				0xd18
++#define PKT_EMP_VTEM_CONTENTS7				0xd1c
++#define PKT0_EMP_CVTEM_CONTENTS0			0xd20
++#define PKT0_EMP_CVTEM_CONTENTS1			0xd24
++#define PKT0_EMP_CVTEM_CONTENTS2			0xd28
++#define PKT0_EMP_CVTEM_CONTENTS3			0xd2c
++#define PKT0_EMP_CVTEM_CONTENTS4			0xd30
++#define PKT0_EMP_CVTEM_CONTENTS5			0xd34
++#define PKT0_EMP_CVTEM_CONTENTS6			0xd38
++#define PKT0_EMP_CVTEM_CONTENTS7			0xd3c
++#define PKT1_EMP_CVTEM_CONTENTS0			0xd40
++#define PKT1_EMP_CVTEM_CONTENTS1			0xd44
++#define PKT1_EMP_CVTEM_CONTENTS2			0xd48
++#define PKT1_EMP_CVTEM_CONTENTS3			0xd4c
++#define PKT1_EMP_CVTEM_CONTENTS4			0xd50
++#define PKT1_EMP_CVTEM_CONTENTS5			0xd54
++#define PKT1_EMP_CVTEM_CONTENTS6			0xd58
++#define PKT1_EMP_CVTEM_CONTENTS7			0xd5c
++#define PKT2_EMP_CVTEM_CONTENTS0			0xd60
++#define PKT2_EMP_CVTEM_CONTENTS1			0xd64
++#define PKT2_EMP_CVTEM_CONTENTS2			0xd68
++#define PKT2_EMP_CVTEM_CONTENTS3			0xd6c
++#define PKT2_EMP_CVTEM_CONTENTS4			0xd70
++#define PKT2_EMP_CVTEM_CONTENTS5			0xd74
++#define PKT2_EMP_CVTEM_CONTENTS6			0xd78
++#define PKT2_EMP_CVTEM_CONTENTS7			0xd7c
++#define PKT3_EMP_CVTEM_CONTENTS0			0xd80
++#define PKT3_EMP_CVTEM_CONTENTS1			0xd84
++#define PKT3_EMP_CVTEM_CONTENTS2			0xd88
++#define PKT3_EMP_CVTEM_CONTENTS3			0xd8c
++#define PKT3_EMP_CVTEM_CONTENTS4			0xd90
++#define PKT3_EMP_CVTEM_CONTENTS5			0xd94
++#define PKT3_EMP_CVTEM_CONTENTS6			0xd98
++#define PKT3_EMP_CVTEM_CONTENTS7			0xd9c
++#define PKT4_EMP_CVTEM_CONTENTS0			0xda0
++#define PKT4_EMP_CVTEM_CONTENTS1			0xda4
++#define PKT4_EMP_CVTEM_CONTENTS2			0xda8
++#define PKT4_EMP_CVTEM_CONTENTS3			0xdac
++#define PKT4_EMP_CVTEM_CONTENTS4			0xdb0
++#define PKT4_EMP_CVTEM_CONTENTS5			0xdb4
++#define PKT4_EMP_CVTEM_CONTENTS6			0xdb8
++#define PKT4_EMP_CVTEM_CONTENTS7			0xdbc
++#define PKT5_EMP_CVTEM_CONTENTS0			0xdc0
++#define PKT5_EMP_CVTEM_CONTENTS1			0xdc4
++#define PKT5_EMP_CVTEM_CONTENTS2			0xdc8
++#define PKT5_EMP_CVTEM_CONTENTS3			0xdcc
++#define PKT5_EMP_CVTEM_CONTENTS4			0xdd0
++#define PKT5_EMP_CVTEM_CONTENTS5			0xdd4
++#define PKT5_EMP_CVTEM_CONTENTS6			0xdd8
++#define PKT5_EMP_CVTEM_CONTENTS7			0xddc
++/* Audio Packetizer Registers */
++#define AUDPKT_CONTROL0					0xe20
++#define AUDPKT_PBIT_FORCE_EN_MASK			BIT(12)
++#define AUDPKT_PBIT_FORCE_EN				BIT(12)
++#define AUDPKT_CHSTATUS_OVR_EN_MASK			BIT(0)
++#define AUDPKT_CHSTATUS_OVR_EN				BIT(0)
++#define AUDPKT_CONTROL1					0xe24
++#define AUDPKT_ACR_CONTROL0				0xe40
++#define AUDPKT_ACR_N_VALUE				0xfffff
++#define AUDPKT_ACR_CONTROL1				0xe44
++#define AUDPKT_ACR_CTS_OVR_VAL_MSK			GENMASK(23, 4)
++#define AUDPKT_ACR_CTS_OVR_VAL(x)			((x) << 4)
++#define AUDPKT_ACR_CTS_OVR_EN_MSK			BIT(1)
++#define AUDPKT_ACR_CTS_OVR_EN				BIT(1)
++#define AUDPKT_ACR_STATUS0				0xe4c
++#define AUDPKT_CHSTATUS_OVR0				0xe60
++#define AUDPKT_CHSTATUS_OVR1				0xe64
++/* IEC60958 Byte 3: Sampleing frenuency Bits 24 to 27 */
++#define AUDPKT_CHSTATUS_SR_MASK				GENMASK(3, 0)
++#define AUDPKT_CHSTATUS_SR_22050			0x4
++#define AUDPKT_CHSTATUS_SR_24000			0x6
++#define AUDPKT_CHSTATUS_SR_32000			0x3
++#define AUDPKT_CHSTATUS_SR_44100			0x0
++#define AUDPKT_CHSTATUS_SR_48000			0x2
++#define AUDPKT_CHSTATUS_SR_88200			0x8
++#define AUDPKT_CHSTATUS_SR_96000			0xa
++#define AUDPKT_CHSTATUS_SR_176400			0xc
++#define AUDPKT_CHSTATUS_SR_192000			0xe
++#define AUDPKT_CHSTATUS_SR_768000			0x9
++#define AUDPKT_CHSTATUS_SR_NOT_INDICATED		0x1
++/* IEC60958 Byte 4: Original Sampleing frenuency Bits 36 to 39 */
++#define AUDPKT_CHSTATUS_0SR_MASK			GENMASK(15, 12)
++#define AUDPKT_CHSTATUS_OSR_8000			0x6
++#define AUDPKT_CHSTATUS_OSR_11025			0xa
++#define AUDPKT_CHSTATUS_OSR_12000			0x2
++#define AUDPKT_CHSTATUS_OSR_16000			0x8
++#define AUDPKT_CHSTATUS_OSR_22050			0xb
++#define AUDPKT_CHSTATUS_OSR_24000			0x9
++#define AUDPKT_CHSTATUS_OSR_32000			0xc
++#define AUDPKT_CHSTATUS_OSR_44100			0xf
++#define AUDPKT_CHSTATUS_OSR_48000			0xd
++#define AUDPKT_CHSTATUS_OSR_88200			0x7
++#define AUDPKT_CHSTATUS_OSR_96000			0x5
++#define AUDPKT_CHSTATUS_OSR_176400			0x3
++#define AUDPKT_CHSTATUS_OSR_192000			0x1
++#define AUDPKT_CHSTATUS_OSR_NOT_INDICATED		0x0
++#define AUDPKT_CHSTATUS_OVR2				0xe68
++#define AUDPKT_CHSTATUS_OVR3				0xe6c
++#define AUDPKT_CHSTATUS_OVR4				0xe70
++#define AUDPKT_CHSTATUS_OVR5				0xe74
++#define AUDPKT_CHSTATUS_OVR6				0xe78
++#define AUDPKT_CHSTATUS_OVR7				0xe7c
++#define AUDPKT_CHSTATUS_OVR8				0xe80
++#define AUDPKT_CHSTATUS_OVR9				0xe84
++#define AUDPKT_CHSTATUS_OVR10				0xe88
++#define AUDPKT_CHSTATUS_OVR11				0xe8c
++#define AUDPKT_CHSTATUS_OVR12				0xe90
++#define AUDPKT_CHSTATUS_OVR13				0xe94
++#define AUDPKT_CHSTATUS_OVR14				0xe98
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC0			0xea0
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC1			0xea4
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC2			0xea8
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC3			0xeac
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC4			0xeb0
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC5			0xeb4
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC6			0xeb8
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC7			0xebc
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC8			0xec0
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC9			0xec4
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC10		0xec8
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC11		0xecc
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC12		0xed0
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC13		0xed4
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC14		0xed8
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC15		0xedc
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC16		0xee0
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC17		0xee4
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC18		0xee8
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC19		0xeec
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC20		0xef0
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC21		0xef4
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC22		0xef8
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC23		0xefc
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC24		0xf00
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC25		0xf04
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC26		0xf08
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC27		0xf0c
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC28		0xf10
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC29		0xf14
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC30		0xf18
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC31		0xf1c
++#define AUDPKT_USRDATA_OVR_MSG_GENERIC32		0xf20
++#define AUDPKT_VBIT_OVR0				0xf24
++/* CEC Registers */
++#define CEC_TX_CONTROL					0x1000
++#define CEC_STATUS					0x1004
++#define CEC_CONFIG					0x1008
++#define CEC_ADDR					0x100c
++#define CEC_TX_COUNT					0x1020
++#define CEC_TX_DATA3_0					0x1024
++#define CEC_TX_DATA7_4					0x1028
++#define CEC_TX_DATA11_8					0x102c
++#define CEC_TX_DATA15_12				0x1030
++#define CEC_RX_COUNT_STATUS				0x1040
++#define CEC_RX_DATA3_0					0x1044
++#define CEC_RX_DATA7_4					0x1048
++#define CEC_RX_DATA11_8					0x104c
++#define CEC_RX_DATA15_12				0x1050
++#define CEC_LOCK_CONTROL				0x1054
++#define CEC_RXQUAL_BITTIME_CONFIG			0x1060
++#define CEC_RX_BITTIME_CONFIG				0x1064
++#define CEC_TX_BITTIME_CONFIG				0x1068
++/* eARC RX CMDC Registers */
++#define EARCRX_CMDC_CONFIG0				0x1800
++#define EARCRX_XACTREAD_STOP_CFG			BIT(26)
++#define EARCRX_XACTREAD_RETRY_CFG			BIT(25)
++#define EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1		BIT(24)
++#define EARCRX_CMDC_XACT_RESTART_EN			BIT(18)
++#define EARCRX_CMDC_CONFIG1				0x1804
++#define EARCRX_CMDC_CONTROL				0x1808
++#define EARCRX_CMDC_HEARTBEAT_LOSS_EN			BIT(4)
++#define EARCRX_CMDC_DISCOVERY_EN			BIT(3)
++#define EARCRX_CONNECTOR_HPD				BIT(1)
++#define EARCRX_CMDC_WHITELIST0_CONFIG			0x180c
++#define EARCRX_CMDC_WHITELIST1_CONFIG			0x1810
++#define EARCRX_CMDC_WHITELIST2_CONFIG			0x1814
++#define EARCRX_CMDC_WHITELIST3_CONFIG			0x1818
++#define EARCRX_CMDC_STATUS				0x181c
++#define EARCRX_CMDC_XACT_INFO				0x1820
++#define EARCRX_CMDC_XACT_ACTION				0x1824
++#define EARCRX_CMDC_HEARTBEAT_RXSTAT_SE			0x1828
++#define EARCRX_CMDC_HEARTBEAT_STATUS			0x182c
++#define EARCRX_CMDC_XACT_WR0				0x1840
++#define EARCRX_CMDC_XACT_WR1				0x1844
++#define EARCRX_CMDC_XACT_WR2				0x1848
++#define EARCRX_CMDC_XACT_WR3				0x184c
++#define EARCRX_CMDC_XACT_WR4				0x1850
++#define EARCRX_CMDC_XACT_WR5				0x1854
++#define EARCRX_CMDC_XACT_WR6				0x1858
++#define EARCRX_CMDC_XACT_WR7				0x185c
++#define EARCRX_CMDC_XACT_WR8				0x1860
++#define EARCRX_CMDC_XACT_WR9				0x1864
++#define EARCRX_CMDC_XACT_WR10				0x1868
++#define EARCRX_CMDC_XACT_WR11				0x186c
++#define EARCRX_CMDC_XACT_WR12				0x1870
++#define EARCRX_CMDC_XACT_WR13				0x1874
++#define EARCRX_CMDC_XACT_WR14				0x1878
++#define EARCRX_CMDC_XACT_WR15				0x187c
++#define EARCRX_CMDC_XACT_WR16				0x1880
++#define EARCRX_CMDC_XACT_WR17				0x1884
++#define EARCRX_CMDC_XACT_WR18				0x1888
++#define EARCRX_CMDC_XACT_WR19				0x188c
++#define EARCRX_CMDC_XACT_WR20				0x1890
++#define EARCRX_CMDC_XACT_WR21				0x1894
++#define EARCRX_CMDC_XACT_WR22				0x1898
++#define EARCRX_CMDC_XACT_WR23				0x189c
++#define EARCRX_CMDC_XACT_WR24				0x18a0
++#define EARCRX_CMDC_XACT_WR25				0x18a4
++#define EARCRX_CMDC_XACT_WR26				0x18a8
++#define EARCRX_CMDC_XACT_WR27				0x18ac
++#define EARCRX_CMDC_XACT_WR28				0x18b0
++#define EARCRX_CMDC_XACT_WR29				0x18b4
++#define EARCRX_CMDC_XACT_WR30				0x18b8
++#define EARCRX_CMDC_XACT_WR31				0x18bc
++#define EARCRX_CMDC_XACT_WR32				0x18c0
++#define EARCRX_CMDC_XACT_WR33				0x18c4
++#define EARCRX_CMDC_XACT_WR34				0x18c8
++#define EARCRX_CMDC_XACT_WR35				0x18cc
++#define EARCRX_CMDC_XACT_WR36				0x18d0
++#define EARCRX_CMDC_XACT_WR37				0x18d4
++#define EARCRX_CMDC_XACT_WR38				0x18d8
++#define EARCRX_CMDC_XACT_WR39				0x18dc
++#define EARCRX_CMDC_XACT_WR40				0x18e0
++#define EARCRX_CMDC_XACT_WR41				0x18e4
++#define EARCRX_CMDC_XACT_WR42				0x18e8
++#define EARCRX_CMDC_XACT_WR43				0x18ec
++#define EARCRX_CMDC_XACT_WR44				0x18f0
++#define EARCRX_CMDC_XACT_WR45				0x18f4
++#define EARCRX_CMDC_XACT_WR46				0x18f8
++#define EARCRX_CMDC_XACT_WR47				0x18fc
++#define EARCRX_CMDC_XACT_WR48				0x1900
++#define EARCRX_CMDC_XACT_WR49				0x1904
++#define EARCRX_CMDC_XACT_WR50				0x1908
++#define EARCRX_CMDC_XACT_WR51				0x190c
++#define EARCRX_CMDC_XACT_WR52				0x1910
++#define EARCRX_CMDC_XACT_WR53				0x1914
++#define EARCRX_CMDC_XACT_WR54				0x1918
++#define EARCRX_CMDC_XACT_WR55				0x191c
++#define EARCRX_CMDC_XACT_WR56				0x1920
++#define EARCRX_CMDC_XACT_WR57				0x1924
++#define EARCRX_CMDC_XACT_WR58				0x1928
++#define EARCRX_CMDC_XACT_WR59				0x192c
++#define EARCRX_CMDC_XACT_WR60				0x1930
++#define EARCRX_CMDC_XACT_WR61				0x1934
++#define EARCRX_CMDC_XACT_WR62				0x1938
++#define EARCRX_CMDC_XACT_WR63				0x193c
++#define EARCRX_CMDC_XACT_WR64				0x1940
++#define EARCRX_CMDC_XACT_RD0				0x1960
++#define EARCRX_CMDC_XACT_RD1				0x1964
++#define EARCRX_CMDC_XACT_RD2				0x1968
++#define EARCRX_CMDC_XACT_RD3				0x196c
++#define EARCRX_CMDC_XACT_RD4				0x1970
++#define EARCRX_CMDC_XACT_RD5				0x1974
++#define EARCRX_CMDC_XACT_RD6				0x1978
++#define EARCRX_CMDC_XACT_RD7				0x197c
++#define EARCRX_CMDC_XACT_RD8				0x1980
++#define EARCRX_CMDC_XACT_RD9				0x1984
++#define EARCRX_CMDC_XACT_RD10				0x1988
++#define EARCRX_CMDC_XACT_RD11				0x198c
++#define EARCRX_CMDC_XACT_RD12				0x1990
++#define EARCRX_CMDC_XACT_RD13				0x1994
++#define EARCRX_CMDC_XACT_RD14				0x1998
++#define EARCRX_CMDC_XACT_RD15				0x199c
++#define EARCRX_CMDC_XACT_RD16				0x19a0
++#define EARCRX_CMDC_XACT_RD17				0x19a4
++#define EARCRX_CMDC_XACT_RD18				0x19a8
++#define EARCRX_CMDC_XACT_RD19				0x19ac
++#define EARCRX_CMDC_XACT_RD20				0x19b0
++#define EARCRX_CMDC_XACT_RD21				0x19b4
++#define EARCRX_CMDC_XACT_RD22				0x19b8
++#define EARCRX_CMDC_XACT_RD23				0x19bc
++#define EARCRX_CMDC_XACT_RD24				0x19c0
++#define EARCRX_CMDC_XACT_RD25				0x19c4
++#define EARCRX_CMDC_XACT_RD26				0x19c8
++#define EARCRX_CMDC_XACT_RD27				0x19cc
++#define EARCRX_CMDC_XACT_RD28				0x19d0
++#define EARCRX_CMDC_XACT_RD29				0x19d4
++#define EARCRX_CMDC_XACT_RD30				0x19d8
++#define EARCRX_CMDC_XACT_RD31				0x19dc
++#define EARCRX_CMDC_XACT_RD32				0x19e0
++#define EARCRX_CMDC_XACT_RD33				0x19e4
++#define EARCRX_CMDC_XACT_RD34				0x19e8
++#define EARCRX_CMDC_XACT_RD35				0x19ec
++#define EARCRX_CMDC_XACT_RD36				0x19f0
++#define EARCRX_CMDC_XACT_RD37				0x19f4
++#define EARCRX_CMDC_XACT_RD38				0x19f8
++#define EARCRX_CMDC_XACT_RD39				0x19fc
++#define EARCRX_CMDC_XACT_RD40				0x1a00
++#define EARCRX_CMDC_XACT_RD41				0x1a04
++#define EARCRX_CMDC_XACT_RD42				0x1a08
++#define EARCRX_CMDC_XACT_RD43				0x1a0c
++#define EARCRX_CMDC_XACT_RD44				0x1a10
++#define EARCRX_CMDC_XACT_RD45				0x1a14
++#define EARCRX_CMDC_XACT_RD46				0x1a18
++#define EARCRX_CMDC_XACT_RD47				0x1a1c
++#define EARCRX_CMDC_XACT_RD48				0x1a20
++#define EARCRX_CMDC_XACT_RD49				0x1a24
++#define EARCRX_CMDC_XACT_RD50				0x1a28
++#define EARCRX_CMDC_XACT_RD51				0x1a2c
++#define EARCRX_CMDC_XACT_RD52				0x1a30
++#define EARCRX_CMDC_XACT_RD53				0x1a34
++#define EARCRX_CMDC_XACT_RD54				0x1a38
++#define EARCRX_CMDC_XACT_RD55				0x1a3c
++#define EARCRX_CMDC_XACT_RD56				0x1a40
++#define EARCRX_CMDC_XACT_RD57				0x1a44
++#define EARCRX_CMDC_XACT_RD58				0x1a48
++#define EARCRX_CMDC_XACT_RD59				0x1a4c
++#define EARCRX_CMDC_XACT_RD60				0x1a50
++#define EARCRX_CMDC_XACT_RD61				0x1a54
++#define EARCRX_CMDC_XACT_RD62				0x1a58
++#define EARCRX_CMDC_XACT_RD63				0x1a5c
++#define EARCRX_CMDC_XACT_RD64				0x1a60
++#define EARCRX_CMDC_SYNC_CONFIG				0x1b00
++/* eARC RX DMAC Registers */
++#define EARCRX_DMAC_PHY_CONTROL				0x1c00
++#define EARCRX_DMAC_CONFIG				0x1c08
++#define EARCRX_DMAC_CONTROL0				0x1c0c
++#define EARCRX_DMAC_AUDIO_EN				BIT(1)
++#define EARCRX_DMAC_EN					BIT(0)
++#define EARCRX_DMAC_CONTROL1				0x1c10
++#define EARCRX_DMAC_STATUS				0x1c14
++#define EARCRX_DMAC_CHSTATUS0				0x1c18
++#define EARCRX_DMAC_CHSTATUS1				0x1c1c
++#define EARCRX_DMAC_CHSTATUS2				0x1c20
++#define EARCRX_DMAC_CHSTATUS3				0x1c24
++#define EARCRX_DMAC_CHSTATUS4				0x1c28
++#define EARCRX_DMAC_CHSTATUS5				0x1c2c
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC0		0x1c30
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC1		0x1c34
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC2		0x1c38
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC3		0x1c3c
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC4		0x1c40
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC5		0x1c44
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC6		0x1c48
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC7		0x1c4c
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC8		0x1c50
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC9		0x1c54
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC10		0x1c58
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC11		0x1c5c
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT0		0x1c60
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT1		0x1c64
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT2		0x1c68
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT3		0x1c6c
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT4		0x1c70
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT5		0x1c74
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT6		0x1c78
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT7		0x1c7c
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT8		0x1c80
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT9		0x1c84
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT10	0x1c88
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT11	0x1c8c
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT0		0x1c90
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT1		0x1c94
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT2		0x1c98
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT3		0x1c9c
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT4		0x1ca0
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT5		0x1ca4
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT6		0x1ca8
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT7		0x1cac
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT8		0x1cb0
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT9		0x1cb4
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT10	0x1cb8
++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT11	0x1cbc
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC0		0x1cc0
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC1		0x1cc4
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC2		0x1cc8
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC3		0x1ccc
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC4		0x1cd0
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC5		0x1cd4
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC6		0x1cd8
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC7		0x1cdc
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC8		0x1ce0
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC9		0x1ce4
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC10		0x1ce8
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC11		0x1cec
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC12		0x1cf0
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC13		0x1cf4
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC14		0x1cf8
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC15		0x1cfc
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC16		0x1d00
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC17		0x1d04
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC18		0x1d08
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC19		0x1d0c
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC20		0x1d10
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC21		0x1d14
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC22		0x1d18
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC23		0x1d1c
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC24		0x1d20
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC25		0x1d24
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC26		0x1d28
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC27		0x1d2c
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC28		0x1d30
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC29		0x1d34
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC30		0x1d38
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC31		0x1d3c
++#define EARCRX_DMAC_USRDATA_MSG_GENERIC32		0x1d40
++#define EARCRX_DMAC_CHSTATUS_STREAMER0			0x1d44
++#define EARCRX_DMAC_CHSTATUS_STREAMER1			0x1d48
++#define EARCRX_DMAC_CHSTATUS_STREAMER2			0x1d4c
++#define EARCRX_DMAC_CHSTATUS_STREAMER3			0x1d50
++#define EARCRX_DMAC_CHSTATUS_STREAMER4			0x1d54
++#define EARCRX_DMAC_CHSTATUS_STREAMER5			0x1d58
++#define EARCRX_DMAC_CHSTATUS_STREAMER6			0x1d5c
++#define EARCRX_DMAC_CHSTATUS_STREAMER7			0x1d60
++#define EARCRX_DMAC_CHSTATUS_STREAMER8			0x1d64
++#define EARCRX_DMAC_CHSTATUS_STREAMER9			0x1d68
++#define EARCRX_DMAC_CHSTATUS_STREAMER10			0x1d6c
++#define EARCRX_DMAC_CHSTATUS_STREAMER11			0x1d70
++#define EARCRX_DMAC_CHSTATUS_STREAMER12			0x1d74
++#define EARCRX_DMAC_CHSTATUS_STREAMER13			0x1d78
++#define EARCRX_DMAC_CHSTATUS_STREAMER14			0x1d7c
++#define EARCRX_DMAC_USRDATA_STREAMER0			0x1d80
++/* Main Unit Interrupt Registers */
++#define MAIN_INTVEC_INDEX				0x3000
++#define MAINUNIT_0_INT_STATUS				0x3010
++#define MAINUNIT_0_INT_MASK_N				0x3014
++#define MAINUNIT_0_INT_CLEAR				0x3018
++#define MAINUNIT_0_INT_FORCE				0x301c
++#define MAINUNIT_1_INT_STATUS				0x3020
++#define FLT_EXIT_TO_LTSL_IRQ				BIT(22)
++#define FLT_EXIT_TO_LTS4_IRQ				BIT(21)
++#define FLT_EXIT_TO_LTSP_IRQ				BIT(20)
++#define SCDC_NACK_RCVD_IRQ				BIT(12)
++#define SCDC_RR_REPLY_STOP_IRQ				BIT(11)
++#define SCDC_UPD_FLAGS_CLR_IRQ				BIT(10)
++#define SCDC_UPD_FLAGS_CHG_IRQ				BIT(9)
++#define SCDC_UPD_FLAGS_RD_IRQ				BIT(8)
++#define I2CM_NACK_RCVD_IRQ				BIT(2)
++#define I2CM_READ_REQUEST_IRQ				BIT(1)
++#define I2CM_OP_DONE_IRQ				BIT(0)
++#define MAINUNIT_1_INT_MASK_N				0x3024
++#define I2CM_NACK_RCVD_MASK_N				BIT(2)
++#define I2CM_READ_REQUEST_MASK_N			BIT(1)
++#define I2CM_OP_DONE_MASK_N				BIT(0)
++#define MAINUNIT_1_INT_CLEAR				0x3028
++#define I2CM_NACK_RCVD_CLEAR				BIT(2)
++#define I2CM_READ_REQUEST_CLEAR				BIT(1)
++#define I2CM_OP_DONE_CLEAR				BIT(0)
++#define MAINUNIT_1_INT_FORCE				0x302c
++/* AVPUNIT Interrupt Registers */
++#define AVP_INTVEC_INDEX				0x3800
++#define AVP_0_INT_STATUS				0x3810
++#define AVP_0_INT_MASK_N				0x3814
++#define AVP_0_INT_CLEAR					0x3818
++#define AVP_0_INT_FORCE					0x381c
++#define AVP_1_INT_STATUS				0x3820
++#define AVP_1_INT_MASK_N				0x3824
++#define HDCP14_AUTH_CHG_MASK_N				BIT(6)
++#define AVP_1_INT_CLEAR					0x3828
++#define AVP_1_INT_FORCE					0x382c
++#define AVP_2_INT_STATUS				0x3830
++#define AVP_2_INT_MASK_N				0x3834
++#define AVP_2_INT_CLEAR					0x3838
++#define AVP_2_INT_FORCE					0x383c
++#define AVP_3_INT_STATUS				0x3840
++#define AVP_3_INT_MASK_N				0x3844
++#define AVP_3_INT_CLEAR					0x3848
++#define AVP_3_INT_FORCE					0x384c
++#define AVP_4_INT_STATUS				0x3850
++#define AVP_4_INT_MASK_N				0x3854
++#define AVP_4_INT_CLEAR					0x3858
++#define AVP_4_INT_FORCE					0x385c
++#define AVP_5_INT_STATUS				0x3860
++#define AVP_5_INT_MASK_N				0x3864
++#define AVP_5_INT_CLEAR					0x3868
++#define AVP_5_INT_FORCE					0x386c
++#define AVP_6_INT_STATUS				0x3870
++#define AVP_6_INT_MASK_N				0x3874
++#define AVP_6_INT_CLEAR					0x3878
++#define AVP_6_INT_FORCE					0x387c
++/* CEC Interrupt Registers */
++#define CEC_INT_STATUS					0x4000
++#define CEC_INT_MASK_N					0x4004
++#define CEC_INT_CLEAR					0x4008
++#define CEC_INT_FORCE					0x400c
++/* eARC RX Interrupt Registers  */
++#define EARCRX_INTVEC_INDEX				0x4800
++#define EARCRX_0_INT_STATUS				0x4810
++#define EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ		BIT(9)
++#define EARCRX_CMDC_DISCOVERY_DONE_IRQ			BIT(8)
++#define EARCRX_0_INT_MASK_N				0x4814
++#define EARCRX_0_INT_CLEAR				0x4818
++#define EARCRX_0_INT_FORCE				0x481c
++#define EARCRX_1_INT_STATUS				0x4820
++#define EARCRX_1_INT_MASK_N				0x4824
++#define EARCRX_1_INT_CLEAR				0x4828
++#define EARCRX_1_INT_FORCE				0x482c
++
++#endif /* __DW_HDMI_QP_H__ */
+diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_qp.h
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/include/drm/bridge/dw_hdmi_qp.h
+@@ -0,0 +1,37 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++/*
++ * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2024 Collabora Ltd.
++ */
++
++#ifndef __DW_HDMI_QP__
++#define __DW_HDMI_QP__
++
++struct device;
++struct drm_display_info;
++struct drm_encoder;
++struct dw_hdmi_qp;
++struct platform_device;
++
++struct dw_hdmi_qp_phy_ops {
++	int (*init)(struct dw_hdmi_qp *hdmi, void *data,
++		    const struct drm_display_info *display);
++	void (*disable)(struct dw_hdmi_qp *hdmi, void *data);
++	enum drm_connector_status (*read_hpd)(struct dw_hdmi_qp *hdmi, void *data);
++	void (*setup_hpd)(struct dw_hdmi_qp *hdmi, void *data);
++};
++
++struct dw_hdmi_qp_plat_data {
++	const struct dw_hdmi_qp_phy_ops *phy_ops;
++	void *phy_data;
++};
++
++int dw_hdmi_qp_set_refclk_rate(struct dw_hdmi_qp *hdmi, unsigned long rate);
++void dw_hdmi_qp_set_high_tmds_clock_ratio(struct dw_hdmi_qp *hdmi,
++					  const struct drm_display_info *display);
++void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi);
++struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
++				   struct drm_encoder *encoder,
++				   const struct dw_hdmi_qp_plat_data *plat_data);
++void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi);
++#endif /* __DW_HDMI_QP__ */
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Fri, 26 Jul 2024 03:07:04 +0300
+Subject: dt-bindings: display: rockchip: Add schema for RK3588 HDMI TX
+ Controller
+
+Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI 2.1
+Quad-Pixel (QP) TX controller IP.
+
+Since this is a new IP block, quite different from those used in the
+previous generations of Rockchip SoCs, add a dedicated binding file.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml | 188 ++++++++++
+ 1 file changed, 188 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml
+@@ -0,0 +1,188 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi-qp.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip DW HDMI QP TX Encoder
++
++maintainers:
++  - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
++
++description:
++  Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX controller
++  IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block.
++
++allOf:
++  - $ref: ../bridge/synopsys,dw-hdmi-qp.yaml#
++  - $ref: /schemas/sound/dai-common.yaml#
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk3588-dw-hdmi-qp
++
++  clocks:
++    minItems: 4
++    items:
++      - {}
++      - {}
++      - {}
++      - {}
++      # The next clocks are optional, but shall be specified in this
++      # order when present.
++      - description: TMDS/FRL link clock
++      - description: Video datapath clock
++
++  clock-names:
++    minItems: 4
++    items:
++      - {}
++      - {}
++      - {}
++      - {}
++      - enum: [hdp, hclk_vo1]
++      - const: hclk_vo1
++
++  interrupts:
++    items:
++      - {}
++      - {}
++      - {}
++      - {}
++      - description: HPD interrupt
++
++  interrupt-names:
++    items:
++      - {}
++      - {}
++      - {}
++      - {}
++      - const: hpd
++
++  phys:
++    maxItems: 1
++    description: The HDMI/eDP PHY.
++
++  phy-names:
++    const: hdmi
++
++  ports:
++    $ref: /schemas/graph.yaml#/properties/ports
++
++    properties:
++      port@0:
++        $ref: /schemas/graph.yaml#/properties/port
++        description:
++          Port node with one endpoint connected to a vop node.
++
++      port@1:
++        $ref: /schemas/graph.yaml#/properties/port
++        description:
++          Port node with one endpoint connected to a hdmi-connector node.
++
++    required:
++      - port@0
++      - port@1
++
++  power-domains:
++    maxItems: 1
++
++  resets:
++    minItems: 2
++    maxItems: 2
++
++  reset-names:
++    items:
++      - const: ref
++      - const: hdp
++
++  "#sound-dai-cells":
++    const: 0
++
++  rockchip,grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      Most HDMI QP related data is accessed through SYS GRF regs.
++
++  rockchip,vo1_grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      Additional HDMI QP related data is accessed through VO1 GRF regs.
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - interrupts
++  - interrupt-names
++  - phys
++  - phy-names
++  - ports
++  - resets
++  - reset-names
++  - rockchip,grf
++  - rockchip,vo1_grf
++
++unevaluatedProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/interrupt-controller/irq.h>
++    #include <dt-bindings/power/rk3588-power.h>
++    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
++
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      hdmi@fde80000 {
++        compatible = "rockchip,rk3588-dw-hdmi-qp";
++        reg = <0x0 0xfde80000 0x0 0x20000>;
++        clocks = <&cru PCLK_HDMITX0>,
++                 <&cru CLK_HDMITX0_EARC>,
++                 <&cru CLK_HDMITX0_REF>,
++                 <&cru MCLK_I2S5_8CH_TX>,
++                 <&cru CLK_HDMIHDP0>,
++                 <&cru HCLK_VO1>;
++        clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
++        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
++                     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
++                     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
++                     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
++                     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
++        interrupt-names = "avp", "cec", "earc", "main", "hpd";
++        phys = <&hdptxphy_hdmi0>;
++        phy-names = "hdmi";
++        power-domains = <&power RK3588_PD_VO1>;
++        resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
++        reset-names = "ref", "hdp";
++        rockchip,grf = <&sys_grf>;
++        rockchip,vo1_grf = <&vo1_grf>;
++        #sound-dai-cells = <0>;
++
++        ports {
++          #address-cells = <1>;
++          #size-cells = <0>;
++
++          port@0 {
++            reg = <0>;
++
++            hdmi0_in_vp0: endpoint {
++                remote-endpoint = <&vp0_out_hdmi0>;
++            };
++          };
++
++          port@1 {
++            reg = <1>;
++
++            hdmi0_out_con0: endpoint {
++                remote-endpoint = <&hdmi_con0_in>;
++            };
++          };
++        };
++      };
++    };
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Wed, 17 Jul 2024 03:34:36 +0300
+Subject: drm/rockchip: Explicitly include bits header
+
+Driver makes use of the BIT() macro, but relies on the bits header being
+implicitly included.
+
+Explicitly pull the header in to avoid potential build failures in some
+configurations.
+
+While at it, reorder include directives alphabetically.
+
+Fixes: 8c8546546f25 ("drm/rockchip: move output interface related definition to rockchip_drm_drv.h")
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+@@ -12,9 +12,10 @@
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_gem.h>
+ 
++#include <linux/bits.h>
++#include <linux/component.h>
+ #include <linux/i2c.h>
+ #include <linux/module.h>
+-#include <linux/component.h>
+ 
+ #define ROCKCHIP_MAX_FB_BUFFER	3
+ #define ROCKCHIP_MAX_CONNECTOR	2
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sat, 6 Jul 2024 03:22:35 +0300
+Subject: drm/rockchip: Add basic RK3588 HDMI output support
+
+The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1
+Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a
+Samsung IP block.
+
+Add just the basic support for now, i.e. RGB output up to 4K@60Hz,
+without audio, CEC or any of the HDMI 2.1 specific features.
+
+Co-developed-by: Algea Cao <algea.cao@rock-chips.com>
+Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ drivers/gpu/drm/rockchip/Kconfig               |   8 +
+ drivers/gpu/drm/rockchip/Makefile              |   1 +
+ drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 430 ++++++++++
+ drivers/gpu/drm/rockchip/rockchip_drm_drv.c    |   2 +
+ drivers/gpu/drm/rockchip/rockchip_drm_drv.h    |   1 +
+ 5 files changed, 442 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/rockchip/Kconfig
++++ b/drivers/gpu/drm/rockchip/Kconfig
+@@ -8,6 +8,7 @@ config DRM_ROCKCHIP
+ 	select VIDEOMODE_HELPERS
+ 	select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
+ 	select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
++	select DRM_DW_HDMI_QP if ROCKCHIP_DW_HDMI_QP
+ 	select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+ 	select GENERIC_PHY if ROCKCHIP_DW_MIPI_DSI
+ 	select GENERIC_PHY_MIPI_DPHY if ROCKCHIP_DW_MIPI_DSI
+@@ -63,6 +64,13 @@ config ROCKCHIP_DW_HDMI
+ 	  enable HDMI on RK3288 or RK3399 based SoC, you should select
+ 	  this option.
+ 
++config ROCKCHIP_DW_HDMI_QP
++	bool "Rockchip specific extensions for Synopsys DW HDMI QP"
++	help
++	  This selects support for Rockchip SoC specific extensions
++	  for the Synopsys DesignWare HDMI QP driver. If you want to
++	  enable HDMI on RK3588 based SoC, you should select this option.
++
+ config ROCKCHIP_DW_MIPI_DSI
+ 	bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
+ 	select GENERIC_PHY_MIPI_DPHY
+diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/rockchip/Makefile
++++ b/drivers/gpu/drm/rockchip/Makefile
+@@ -11,6 +11,7 @@ rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o
+ rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
+ rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
+ rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
++rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI_QP) += dw_hdmi_qp-rockchip.o
+ rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
+ rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
+ rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
++++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
+@@ -0,0 +1,430 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2024 Collabora Ltd.
++ *
++ * Author: Algea Cao <algea.cao@rock-chips.com>
++ * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/gpio/consumer.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/phy/phy.h>
++#include <linux/regmap.h>
++
++#include <drm/bridge/dw_hdmi_qp.h>
++#include <drm/drm_bridge_connector.h>
++#include <drm/drm_of.h>
++#include <drm/drm_probe_helper.h>
++#include <drm/drm_simple_kms_helper.h>
++
++#include "rockchip_drm_drv.h"
++
++#define RK3588_GRF_SOC_CON2		0x0308
++#define RK3588_HDMI0_HPD_INT_MSK	BIT(13)
++#define RK3588_HDMI0_HPD_INT_CLR	BIT(12)
++#define RK3588_GRF_SOC_CON7		0x031c
++#define RK3588_SET_HPD_PATH_MASK	GENMASK(13, 12)
++#define RK3588_GRF_SOC_STATUS1		0x0384
++#define RK3588_HDMI0_LEVEL_INT		BIT(16)
++#define RK3588_GRF_VO1_CON3		0x000c
++#define RK3588_SCLIN_MASK		BIT(9)
++#define RK3588_SDAIN_MASK		BIT(10)
++#define RK3588_MODE_MASK		BIT(11)
++#define RK3588_I2S_SEL_MASK		BIT(13)
++#define RK3588_GRF_VO1_CON9		0x0024
++#define RK3588_HDMI0_GRANT_SEL		BIT(10)
++
++#define HIWORD_UPDATE(val, mask)	((val) | (mask) << 16)
++
++struct rockchip_hdmi_qp {
++	struct device *dev;
++	struct regmap *regmap;
++	struct regmap *vo1_regmap;
++	struct rockchip_encoder encoder;
++	struct dw_hdmi_qp *hdmi;
++	struct phy *phy;
++	struct gpio_desc *enable_gpio;
++	struct delayed_work hpd_work;
++};
++
++static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(struct drm_encoder *encoder)
++{
++	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
++
++	return container_of(rkencoder, struct rockchip_hdmi_qp, encoder);
++}
++
++static void
++dw_hdmi_qp_rockchip_encoder_mode_set(struct drm_encoder *encoder,
++				     struct drm_display_mode *mode,
++				     struct drm_display_mode *adj_mode)
++{
++	struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder);
++
++	dw_hdmi_qp_set_refclk_rate(hdmi->hdmi, adj_mode->clock * 1000);
++}
++
++static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder)
++{
++	struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder);
++	struct drm_crtc *crtc = encoder->crtc;
++	int rate;
++
++	/* Unconditionally switch to TMDS as FRL is not yet supported */
++	gpiod_set_value(hdmi->enable_gpio, 1);
++
++	if (crtc && crtc->state) {
++		dw_hdmi_qp_set_refclk_rate(hdmi->hdmi,
++					   crtc->state->adjusted_mode.crtc_clock * 1000);
++		/*
++		 * FIXME: Temporary workaround to pass pixel clock rate
++		 * to the PHY driver until phy_configure_opts_hdmi
++		 * becomes available in the PHY API. See also the related
++		 * comment in rk_hdptx_phy_power_on() from
++		 * drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
++		 */
++		rate = crtc->state->mode.clock * 10;
++		phy_set_bus_width(hdmi->phy, rate);
++		drm_dbg(hdmi, "%s set bus_width=%u\n", __func__, rate);
++	}
++}
++
++static int
++dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
++					 struct drm_crtc_state *crtc_state,
++					 struct drm_connector_state *conn_state)
++{
++	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
++
++	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
++	s->output_type = DRM_MODE_CONNECTOR_HDMIA;
++
++	return 0;
++}
++
++static const struct
++drm_encoder_helper_funcs dw_hdmi_qp_rockchip_encoder_helper_funcs = {
++	.mode_set	= dw_hdmi_qp_rockchip_encoder_mode_set,
++	.enable		= dw_hdmi_qp_rockchip_encoder_enable,
++	.atomic_check	= dw_hdmi_qp_rockchip_encoder_atomic_check,
++};
++
++static int dw_hdmi_qp_rk3588_phy_init(struct dw_hdmi_qp *dw_hdmi, void *data,
++				      const struct drm_display_info *display)
++{
++	struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
++
++	dw_hdmi_qp_set_high_tmds_clock_ratio(dw_hdmi, display);
++
++	return phy_power_on(hdmi->phy);
++}
++
++static void dw_hdmi_qp_rk3588_phy_disable(struct dw_hdmi_qp *dw_hdmi,
++					  void *data)
++{
++	struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
++
++	phy_power_off(hdmi->phy);
++}
++
++static enum drm_connector_status
++dw_hdmi_qp_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
++{
++	struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
++	u32 val;
++
++	regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &val);
++
++	return val & RK3588_HDMI0_LEVEL_INT ?
++		connector_status_connected : connector_status_disconnected;
++}
++
++static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
++{
++	struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
++
++	regmap_write(hdmi->regmap,
++		     RK3588_GRF_SOC_CON2,
++		     HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,
++				   RK3588_HDMI0_HPD_INT_CLR |
++				   RK3588_HDMI0_HPD_INT_MSK));
++}
++
++static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = {
++	.init		= dw_hdmi_qp_rk3588_phy_init,
++	.disable	= dw_hdmi_qp_rk3588_phy_disable,
++	.read_hpd	= dw_hdmi_qp_rk3588_read_hpd,
++	.setup_hpd	= dw_hdmi_qp_rk3588_setup_hpd,
++};
++
++static void dw_hdmi_qp_rk3588_hpd_work(struct work_struct *work)
++{
++	struct rockchip_hdmi_qp *hdmi = container_of(work,
++						     struct rockchip_hdmi_qp,
++						     hpd_work.work);
++	struct drm_device *drm = hdmi->encoder.encoder.dev;
++	bool changed;
++
++	if (drm) {
++		changed = drm_helper_hpd_irq_event(drm);
++		if (changed)
++			drm_dbg(hdmi, "connector status changed\n");
++	}
++}
++
++static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id)
++{
++	struct rockchip_hdmi_qp *hdmi = dev_id;
++	u32 intr_stat, val;
++
++	regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat);
++
++	if (intr_stat) {
++		val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK,
++				    RK3588_HDMI0_HPD_INT_MSK);
++		regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
++		return IRQ_WAKE_THREAD;
++	}
++
++	return IRQ_NONE;
++}
++
++static irqreturn_t dw_hdmi_qp_rk3588_irq(int irq, void *dev_id)
++{
++	struct rockchip_hdmi_qp *hdmi = dev_id;
++	u32 intr_stat, val;
++	int debounce_ms;
++
++	regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat);
++	if (!intr_stat)
++		return IRQ_NONE;
++
++	val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,
++			    RK3588_HDMI0_HPD_INT_CLR);
++	regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
++
++	debounce_ms = intr_stat & RK3588_HDMI0_LEVEL_INT ? 150 : 20;
++	mod_delayed_work(system_wq, &hdmi->hpd_work,
++			 msecs_to_jiffies(debounce_ms));
++
++	val |= HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK);
++	regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
++
++	return IRQ_HANDLED;
++}
++
++static const struct of_device_id dw_hdmi_qp_rockchip_dt_ids[] = {
++	{ .compatible = "rockchip,rk3588-dw-hdmi-qp",
++	  .data = &rk3588_hdmi_phy_ops },
++	{},
++};
++MODULE_DEVICE_TABLE(of, dw_hdmi_qp_rockchip_dt_ids);
++
++static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master,
++				    void *data)
++{
++	static const char * const clk_names[] = { "hdp", "hclk_vo1" };
++	struct platform_device *pdev = to_platform_device(dev);
++	struct dw_hdmi_qp_plat_data plat_data;
++	struct drm_device *drm = data;
++	struct drm_connector *connector;
++	struct drm_encoder *encoder;
++	struct rockchip_hdmi_qp *hdmi;
++	struct clk *clk;
++	int ret, irq, i;
++	u32 val;
++
++	if (!pdev->dev.of_node)
++		return -ENODEV;
++
++	hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
++	if (!hdmi)
++		return -ENOMEM;
++
++	plat_data.phy_ops = of_device_get_match_data(dev);
++	if (!plat_data.phy_ops)
++		return -ENODEV;
++
++	plat_data.phy_data = hdmi;
++	hdmi->dev = &pdev->dev;
++
++	encoder = &hdmi->encoder.encoder;
++	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
++
++	rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
++						  dev->of_node, 0, 0);
++	/*
++	 * If we failed to find the CRTC(s) which this encoder is
++	 * supposed to be connected to, it's because the CRTC has
++	 * not been registered yet.  Defer probing, and hope that
++	 * the required CRTC is added later.
++	 */
++	if (encoder->possible_crtcs == 0)
++		return -EPROBE_DEFER;
++
++	hdmi->regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
++						       "rockchip,grf");
++	if (IS_ERR(hdmi->regmap)) {
++		drm_err(hdmi, "Unable to get rockchip,grf\n");
++		return PTR_ERR(hdmi->regmap);
++	}
++
++	hdmi->vo1_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
++							   "rockchip,vo1_grf");
++	if (IS_ERR(hdmi->vo1_regmap)) {
++		drm_err(hdmi, "Unable to get rockchip,vo1_grf\n");
++		return PTR_ERR(hdmi->vo1_regmap);
++	}
++
++	for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
++		clk = devm_clk_get_optional_enabled(hdmi->dev, clk_names[i]);
++
++		if (IS_ERR(clk)) {
++			ret = PTR_ERR(clk);
++			if (ret != -EPROBE_DEFER)
++				drm_err(hdmi, "Failed to get %s clock: %d\n",
++					clk_names[i], ret);
++			return ret;
++		}
++	}
++
++	hdmi->enable_gpio = devm_gpiod_get_optional(hdmi->dev, "enable",
++						    GPIOD_OUT_HIGH);
++	if (IS_ERR(hdmi->enable_gpio)) {
++		ret = PTR_ERR(hdmi->enable_gpio);
++		drm_err(hdmi, "Failed to request enable GPIO: %d\n", ret);
++		return ret;
++	}
++
++	hdmi->phy = devm_phy_get(dev, "hdmi");
++	if (IS_ERR(hdmi->phy)) {
++		ret = PTR_ERR(hdmi->phy);
++		if (ret != -EPROBE_DEFER)
++			drm_err(hdmi, "failed to get phy: %d\n", ret);
++		return ret;
++	}
++
++	val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) |
++	      HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) |
++	      HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) |
++	      HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK);
++	regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val);
++
++	val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK,
++			    RK3588_SET_HPD_PATH_MASK);
++	regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val);
++
++	val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL,
++			    RK3588_HDMI0_GRANT_SEL);
++	regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val);
++
++	val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK);
++	regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
++
++	INIT_DELAYED_WORK(&hdmi->hpd_work, dw_hdmi_qp_rk3588_hpd_work);
++
++	irq = platform_get_irq_byname(pdev, "hpd");
++	if (irq < 0)
++		return irq;
++
++	ret = devm_request_threaded_irq(hdmi->dev, irq,
++					dw_hdmi_qp_rk3588_hardirq,
++					dw_hdmi_qp_rk3588_irq,
++					IRQF_SHARED, "dw-hdmi-qp-hpd",
++					hdmi);
++	if (ret)
++		return ret;
++
++	drm_encoder_helper_add(encoder, &dw_hdmi_qp_rockchip_encoder_helper_funcs);
++	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
++
++	platform_set_drvdata(pdev, hdmi);
++
++	hdmi->hdmi = dw_hdmi_qp_bind(pdev, encoder, &plat_data);
++	if (IS_ERR(hdmi->hdmi)) {
++		ret = PTR_ERR(hdmi->hdmi);
++		drm_encoder_cleanup(encoder);
++		return ret;
++	}
++
++	connector = drm_bridge_connector_init(drm, encoder);
++	if (IS_ERR(connector)) {
++		ret = PTR_ERR(connector);
++		drm_err(hdmi, "failed to init bridge connector: %d\n", ret);
++		return ret;
++	}
++
++	return drm_connector_attach_encoder(connector, encoder);
++}
++
++static void dw_hdmi_qp_rockchip_unbind(struct device *dev,
++				       struct device *master,
++				       void *data)
++{
++	struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev);
++
++	cancel_delayed_work_sync(&hdmi->hpd_work);
++	dw_hdmi_qp_unbind(hdmi->hdmi);
++
++	drm_encoder_cleanup(&hdmi->encoder.encoder);
++}
++
++static const struct component_ops dw_hdmi_qp_rockchip_ops = {
++	.bind	= dw_hdmi_qp_rockchip_bind,
++	.unbind	= dw_hdmi_qp_rockchip_unbind,
++};
++
++static int dw_hdmi_qp_rockchip_probe(struct platform_device *pdev)
++{
++	return component_add(&pdev->dev, &dw_hdmi_qp_rockchip_ops);
++}
++
++static void dw_hdmi_qp_rockchip_remove(struct platform_device *pdev)
++{
++	component_del(&pdev->dev, &dw_hdmi_qp_rockchip_ops);
++}
++
++static int __maybe_unused dw_hdmi_qp_rockchip_resume(struct device *dev)
++{
++	struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev);
++	u32 val;
++
++	val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) |
++	      HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) |
++	      HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) |
++	      HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK);
++	regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val);
++
++	val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK,
++			    RK3588_SET_HPD_PATH_MASK);
++	regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val);
++
++	val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL,
++			    RK3588_HDMI0_GRANT_SEL);
++	regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val);
++
++	dw_hdmi_qp_resume(dev, hdmi->hdmi);
++
++	if (hdmi->encoder.encoder.dev)
++		drm_helper_hpd_irq_event(hdmi->encoder.encoder.dev);
++
++	return 0;
++}
++
++static const struct dev_pm_ops dw_hdmi_qp_rockchip_pm = {
++	SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_qp_rockchip_resume)
++};
++
++struct platform_driver dw_hdmi_qp_rockchip_pltfm_driver = {
++	.probe  = dw_hdmi_qp_rockchip_probe,
++	.remove_new = dw_hdmi_qp_rockchip_remove,
++	.driver = {
++		.name = "dwhdmiqp-rockchip",
++		.pm = &dw_hdmi_qp_rockchip_pm,
++		.of_match_table = dw_hdmi_qp_rockchip_dt_ids,
++	},
++};
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+@@ -503,6 +503,8 @@ static int __init rockchip_drm_init(void)
+ 	ADD_ROCKCHIP_SUB_DRIVER(cdn_dp_driver, CONFIG_ROCKCHIP_CDN_DP);
+ 	ADD_ROCKCHIP_SUB_DRIVER(dw_hdmi_rockchip_pltfm_driver,
+ 				CONFIG_ROCKCHIP_DW_HDMI);
++	ADD_ROCKCHIP_SUB_DRIVER(dw_hdmi_qp_rockchip_pltfm_driver,
++				CONFIG_ROCKCHIP_DW_HDMI_QP);
+ 	ADD_ROCKCHIP_SUB_DRIVER(dw_mipi_dsi_rockchip_driver,
+ 				CONFIG_ROCKCHIP_DW_MIPI_DSI);
+ 	ADD_ROCKCHIP_SUB_DRIVER(inno_hdmi_driver, CONFIG_ROCKCHIP_INNO_HDMI);
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+@@ -88,6 +88,7 @@ int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rencoder,
+ int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
+ extern struct platform_driver cdn_dp_driver;
+ extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
++extern struct platform_driver dw_hdmi_qp_rockchip_pltfm_driver;
+ extern struct platform_driver dw_mipi_dsi_rockchip_driver;
+ extern struct platform_driver inno_hdmi_driver;
+ extern struct platform_driver rockchip_dp_driver;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Thu, 11 Jul 2024 14:48:43 +0300
+Subject: arm64: defconfig: Enable Rockchip extensions for Synopsys DW HDMI QP
+
+Enable Rockchip specific extensions for the Synopsys DesignWare HDMI QP
+driver.
+
+This is needed for the HDMI output support on RK3588 SoC based boards.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 111111111111..222222222222 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -865,6 +865,7 @@ CONFIG_ROCKCHIP_VOP2=y
+ CONFIG_ROCKCHIP_ANALOGIX_DP=y
+ CONFIG_ROCKCHIP_CDN_DP=y
+ CONFIG_ROCKCHIP_DW_HDMI=y
++CONFIG_ROCKCHIP_DW_HDMI_QP=y
+ CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+ CONFIG_ROCKCHIP_INNO_HDMI=y
+ CONFIG_ROCKCHIP_LVDS=y
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0135-arm64-dts-rockchip-Add-HDMI0-bridge-CLK-to-rk3588.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0135-arm64-dts-rockchip-Add-HDMI0-bridge-CLK-to-rk3588.patch
new file mode 100644
index 000000000000..4707239f4ad3
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0135-arm64-dts-rockchip-Add-HDMI0-bridge-CLK-to-rk3588.patch
@@ -0,0 +1,94 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Mon, 15 Jan 2024 22:47:41 +0200
+Subject: arm64: dts: rockchip: Add HDMI0 bridge to rk3588
+
+Add DT node for the HDMI0 bridge found on RK3588 SoC.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 42 ++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1405,6 +1405,48 @@ i2s9_8ch: i2s@fddfc000 {
+ 		status = "disabled";
+ 	};
+ 
++	hdmi0: hdmi@fde80000 {
++		compatible = "rockchip,rk3588-dw-hdmi-qp";
++		reg = <0x0 0xfde80000 0x0 0x20000>;
++		clocks = <&cru PCLK_HDMITX0>,
++			 <&cru CLK_HDMITX0_EARC>,
++			 <&cru CLK_HDMITX0_REF>,
++			 <&cru MCLK_I2S5_8CH_TX>,
++			 <&cru CLK_HDMIHDP0>,
++			 <&cru HCLK_VO1>;
++		clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
++		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "avp", "cec", "earc", "main", "hpd";
++		phys = <&hdptxphy_hdmi0>;
++		phy-names = "hdmi";
++		pinctrl-names = "default";
++		pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
++			     &hdmim0_tx0_scl &hdmim0_tx0_sda>;
++		power-domains = <&power RK3588_PD_VO1>;
++		resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
++		reset-names = "ref", "hdp";
++		rockchip,grf = <&sys_grf>;
++		rockchip,vo1_grf = <&vo1_grf>;
++		status = "disabled";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			hdmi0_in: port@0 {
++				reg = <0>;
++			};
++
++			hdmi0_out: port@1 {
++				reg = <1>;
++			};
++		};
++	};
++
+ 	qos_gpu_m0: qos@fdf35000 {
+ 		compatible = "rockchip,rk3588-qos", "syscon";
+ 		reg = <0x0 0xfdf35000 0x0 0x20>;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Tue, 16 Jan 2024 03:13:38 +0200
+Subject: [WIP] arm64: dts: rockchip: Enable HDMI0 PHY clk provider on rk3588
+
+The HDMI0 PHY can be used as a clock provider on RK3588, hence add the
+missing #clock-cells property.
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -2868,6 +2868,7 @@ hdptxphy_hdmi0: phy@fed60000 {
+ 		reg = <0x0 0xfed60000 0x0 0x2000>;
+ 		clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
+ 		clock-names = "ref", "apb";
++		#clock-cells = <0>;
+ 		#phy-cells = <0>;
+ 		resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
+ 			 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0170-drm-rockchip-vop2-add-clocks-reset-support.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0170-drm-rockchip-vop2-add-clocks-reset-support.patch
new file mode 100644
index 000000000000..78e0ae900c10
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0170-drm-rockchip-vop2-add-clocks-reset-support.patch
@@ -0,0 +1,187 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Fri, 3 May 2024 14:27:39 -0400
+Subject: vop2: Add clock resets support
+
+At the end of initialization, each VP clock needs to be reset before
+they can be used.
+
+Failing to do so can put the VOP in an undefined state where the
+generated HDMI signal is either lost or not matching the selected mode.
+
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 30 ++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+@@ -19,6 +19,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
++#include <linux/reset.h>
+ #include <linux/swab.h>
+ 
+ #include <drm/drm.h>
+@@ -159,6 +160,7 @@ struct vop2_win {
+ struct vop2_video_port {
+ 	struct drm_crtc crtc;
+ 	struct vop2 *vop2;
++	struct reset_control *dclk_rst;
+ 	struct clk *dclk;
+ 	unsigned int id;
+ 	const struct vop2_video_port_data *data;
+@@ -2064,6 +2066,26 @@ static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name)
+ 	return NULL;
+ }
+ 
++static int vop2_clk_reset(struct vop2_video_port *vp)
++{
++	struct reset_control *rstc = vp->dclk_rst;
++	struct vop2 *vop2 = vp->vop2;
++	int ret;
++
++	if (!rstc)
++		return 0;
++
++	ret = reset_control_assert(rstc);
++	if (ret < 0)
++		drm_warn(vop2->drm, "failed to assert reset\n");
++	udelay(10);
++	ret = reset_control_deassert(rstc);
++	if (ret < 0)
++		drm_warn(vop2->drm, "failed to deassert reset\n");
++
++	return ret;
++}
++
+ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
+ 				    struct drm_atomic_state *state)
+ {
+@@ -2233,6 +2255,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
+ 
++	vop2_clk_reset(vp);
++
+ 	drm_crtc_vblank_on(crtc);
+ 
+ 	vop2_unlock(vop2);
+@@ -2920,6 +2944,12 @@ static int vop2_create_crtcs(struct vop2 *vop2)
+ 		vp->data = vp_data;
+ 
+ 		snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
++		vp->dclk_rst = devm_reset_control_get_optional(vop2->dev, dclk_name);
++		if (IS_ERR(vp->dclk_rst)) {
++		        drm_err(vop2->drm, "failed to get %s reset\n", dclk_name);
++		        return PTR_ERR(vp->dclk_rst);
++		}
++
+ 		vp->dclk = devm_clk_get(vop2->dev, dclk_name);
+ 		if (IS_ERR(vp->dclk)) {
+ 			drm_err(vop2->drm, "failed to get %s\n", dclk_name);
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Mon, 6 May 2024 13:54:01 -0400
+Subject: dt-bindings: display: vop2: Add VP clock resets
+
+Add the documentation for VOP2 video ports reset clocks.
+One reset can be set per video port.
+
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+---
+ Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 27 ++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
+@@ -65,6 +65,22 @@ properties:
+       - const: dclk_vp3
+       - const: pclk_vop
+ 
++  resets:
++    minItems: 3
++    items:
++      - description: Pixel clock reset for video port 0.
++      - description: Pixel clock reset for video port 1.
++      - description: Pixel clock reset for video port 2.
++      - description: Pixel clock reset for video port 3.
++
++  reset-names:
++    minItems: 3
++    items:
++      - const: dclk_vp0
++      - const: dclk_vp1
++      - const: dclk_vp2
++      - const: dclk_vp3
++
+   rockchip,grf:
+     $ref: /schemas/types.yaml#/definitions/phandle
+     description:
+@@ -128,6 +144,11 @@ allOf:
+         clock-names:
+           minItems: 7
+ 
++        resets:
++          minItems: 4
++        reset-names:
++          minItems: 4
++
+         ports:
+           required:
+             - port@0
+@@ -183,6 +204,12 @@ examples:
+                               "dclk_vp0",
+                               "dclk_vp1",
+                               "dclk_vp2";
++                resets = <&cru SRST_VOP0>,
++                         <&cru SRST_VOP1>,
++                         <&cru SRST_VOP2>;
++                reset-names = "dclk_vp0",
++                              "dclk_vp1",
++                              "dclk_vp2";
+                 power-domains = <&power RK3568_PD_VO>;
+                 iommus = <&vop_mmu>;
+                 vop_out: ports {
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Fri, 2 Aug 2024 00:13:32 +0300
+Subject: arm64: dts: rockchip: rk3588: add VOP2 clock resets
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1307,6 +1307,14 @@ vop: vop@fdd90000 {
+ 			      "pclk_vop";
+ 		iommus = <&vop_mmu>;
+ 		power-domains = <&power RK3588_PD_VOP>;
++		resets = <&cru SRST_D_VOP0>,
++			 <&cru SRST_D_VOP1>,
++			 <&cru SRST_D_VOP2>,
++			 <&cru SRST_D_VOP3>;
++		reset-names = "dclk_vp0",
++			      "dclk_vp1",
++			      "dclk_vp2",
++			      "dclk_vp3";
+ 		rockchip,grf = <&sys_grf>;
+ 		rockchip,vop-grf = <&vop_grf>;
+ 		rockchip,vo1-grf = <&vo1_grf>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0801-wireless-add-bcm43752.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0801-wireless-add-bcm43752.patch
new file mode 100644
index 000000000000..bdcd77c10ebd
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0801-wireless-add-bcm43752.patch
@@ -0,0 +1,74 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <unknown-email@domain.tld>
+Date: Wed, 28 Feb 2024 20:59:15 +0100
+Subject: net: wireless: brcmfmac: Add support for AP6275P
+
+This module features BCM43752A2 chipset. The firmware requires
+randomness seeding, so enabled it.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c       | 5 ++++-
+ drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h | 2 ++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+index 111111111111..222222222222 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+@@ -70,6 +70,7 @@ BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie");
+ BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie");
+ BRCMF_FW_CLM_DEF(4378B3, "brcmfmac4378b3-pcie");
+ BRCMF_FW_CLM_DEF(4387C2, "brcmfmac4387c2-pcie");
++BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-pcie");
+ 
+ /* firmware config files */
+ MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt");
+@@ -104,6 +105,7 @@ static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
+ 	BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
++	BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */
+ 	BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0x0000000F, 4378B1), /* revision ID 3 */
+ 	BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFE0, 4378B3), /* revision ID 5 */
+@@ -1715,7 +1717,7 @@ static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
+ 		memcpy_toio(devinfo->tcm + address, nvram, nvram_len);
+ 		brcmf_fw_nvram_free(nvram);
+ 
+-		if (devinfo->otp.valid) {
++		if (devinfo->otp.valid || devinfo->ci->chip == BRCM_CC_43752_CHIP_ID) {
+ 			size_t rand_len = BRCMF_RANDOM_SEED_LENGTH;
+ 			struct brcmf_random_seed_footer footer = {
+ 				.length = cpu_to_le32(rand_len),
+@@ -2695,6 +2697,7 @@ static const struct pci_device_id brcmf_pcie_devid_table[] = {
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA),
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC),
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW),
++	BRCMF_PCIE_DEVICE(BRCM_PCIE_43752_DEVICE_ID, WCC),
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC),
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC),
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4387_DEVICE_ID, WCC),
+diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+index 111111111111..222222222222 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
++++ b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+@@ -52,6 +52,7 @@
+ #define BRCM_CC_43664_CHIP_ID		43664
+ #define BRCM_CC_43666_CHIP_ID		43666
+ #define BRCM_CC_4371_CHIP_ID		0x4371
++#define BRCM_CC_43752_CHIP_ID		43752
+ #define BRCM_CC_4377_CHIP_ID		0x4377
+ #define BRCM_CC_4378_CHIP_ID		0x4378
+ #define BRCM_CC_4387_CHIP_ID		0x4387
+@@ -94,6 +95,7 @@
+ #define BRCM_PCIE_4366_5G_DEVICE_ID	0x43c5
+ #define BRCM_PCIE_4371_DEVICE_ID	0x440d
+ #define BRCM_PCIE_43596_DEVICE_ID	0x4415
++#define BRCM_PCIE_43752_DEVICE_ID	0x449d
+ #define BRCM_PCIE_4377_DEVICE_ID	0x4488
+ #define BRCM_PCIE_4378_DEVICE_ID	0x4425
+ #define BRCM_PCIE_4387_DEVICE_ID	0x4433
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0802-wireless-add-clk-property.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0802-wireless-add-clk-property.patch
new file mode 100644
index 000000000000..dcf8c70b0b68
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/0802-wireless-add-clk-property.patch
@@ -0,0 +1,51 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <unknown-email@domain.tld>
+Date: Wed, 28 Feb 2024 21:09:51 +0100
+Subject: net: wireless: brcmfmac: Add optional 32k clock enable support
+
+WiFi modules often require 32kHz clock to function. Add support to
+enable the clock to pcie driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+index 111111111111..222222222222 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+@@ -3,6 +3,7 @@
+  * Copyright (c) 2014 Broadcom Corporation
+  */
+ 
++#include <linux/clk.h>
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/firmware.h>
+@@ -2408,6 +2409,7 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+ 	struct brcmf_pciedev *pcie_bus_dev;
+ 	struct brcmf_core *core;
+ 	struct brcmf_bus *bus;
++	struct clk *clk;
+ 
+ 	if (!id) {
+ 		id = pci_match_id(brcmf_pcie_devid_table, pdev);
+@@ -2419,6 +2421,14 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+ 
+ 	brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
+ 
++	clk = devm_clk_get_optional_enabled(&pdev->dev, "32k");
++	if (IS_ERR(clk))
++		return PTR_ERR(clk);
++	if (clk) {
++		dev_info(&pdev->dev, "enabling 32kHz clock\n");
++		clk_set_rate(clk, 32768);
++	}
++
+ 	ret = -ENOMEM;
+ 	devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
+ 	if (devinfo == NULL)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch
new file mode 100644
index 000000000000..cad0ed1438f8
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch
@@ -0,0 +1,37 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: amazingfate <liujianfeng1994@gmail.com>
+Date: Wed, 27 Dec 2023 15:03:57 +0800
+Subject: arm64: dts: rock-5b: Slow down emmc to hs200 and add tsadc node
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -408,8 +408,7 @@ &sdhci {
+ 	no-sdio;
+ 	no-sd;
+ 	non-removable;
+-	mmc-hs400-1_8v;
+-	mmc-hs400-enhanced-strobe;
++	mmc-hs200-1_8v;
+ 	status = "okay";
+ };
+ 
+@@ -463,6 +462,10 @@ flash@0 {
+ 	};
+ };
+ 
++&tsadc {
++	status = "okay";
++};
++
+ &uart6 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch
new file mode 100644
index 000000000000..1867a9b42d8b
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch
@@ -0,0 +1,67 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Mon, 15 Jan 2024 22:51:17 +0200
+Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5b
+
+Add the necessary DT changes to enable HDMI0 on Rock 5B.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 30 ++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -4,6 +4,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3588.dtsi"
+ 
+ / {
+@@ -192,6 +193,20 @@ &gpu {
+ 	status = "okay";
+ };
+ 
++&hdmi0 {
++	status = "okay";
++};
++
++&hdmi0_in {
++	hdmi0_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi0>;
++	};
++};
++
++&hdptxphy_hdmi0 {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&i2c0m2_xfer>;
+@@ -861,3 +876,18 @@ &usb_host1_xhci {
+ &usb_host2_xhci {
+ 	status = "okay";
+ };
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vop {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi0_in_vp0>;
++	};
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch
new file mode 100644
index 000000000000..4a17782ae85a
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Fri, 3 Nov 2023 20:05:05 +0200
+Subject: arm64: dts: rockchip: Make use of HDMI0 PHY PLL on rock-5b
+
+The initial vop2 support for rk3588 in mainline is not able to handle
+all display modes supported by connected displays, e.g.
+2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz.
+
+Additionally, it doesn't cope with non-integer refresh rates like 59.94,
+29.97, 23.98, etc.
+
+Make use of the HDMI0 PHY PLL to support the additional display modes.
+
+Note this requires commit "drm/rockchip: vop2: Improve display modes
+handling on rk3588", which needs a rework to be upstreamable.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -193,6 +193,11 @@ &gpu {
+ 	status = "okay";
+ };
+ 
++&display_subsystem {
++	clocks = <&hdptxphy_hdmi0>;
++	clock-names = "hdmi0_phy_pll";
++};
++
+ &hdmi0 {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch
new file mode 100644
index 000000000000..6ac64dd819cc
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch
@@ -0,0 +1,57 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Tue, 27 Feb 2024 16:04:42 +0300
+Subject: Add HDMI and VOP2 to Rock 5A
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 30 ++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -5,6 +5,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3588s.dtsi"
+ 
+ / {
+@@ -778,3 +779,32 @@ &usb_host1_ohci {
+ &usb_host2_xhci {
+ 	status = "okay";
+ };
++
++&hdmi0 {
++	status = "okay";
++};
++
++&hdptxphy_hdmi0 {
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&hdmi0_in {
++	hdmi0_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi0>;
++	};
++};
++
++&vop {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi0_in_vp0>;
++	};
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch
new file mode 100644
index 000000000000..ceafeea6decb
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch
@@ -0,0 +1,36 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: amazingfate <liujianfeng1994@gmail.com>
+Date: Thu, 28 Mar 2024 00:41:34 +0800
+Subject: arch: arm64: dts: enable gpu node for rock-5a
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -281,6 +281,11 @@ &gmac1_rgmii_clk
+ 	status = "okay";
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_gpu_s0>;
++	status = "okay";
++};
++
+ &mdio1 {
+ 	rgmii_phy1: ethernet-phy@1 {
+ 		/* RTL8211F */
+@@ -447,6 +452,7 @@ rk806_dvs3_null: dvs3-null-pins {
+ 		regulators {
+ 			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ 				regulator-name = "vdd_gpu_s0";
++				regulator-always-on;
+ 				regulator-boot-on;
+ 				regulator-min-microvolt = <550000>;
+ 				regulator-max-microvolt = <950000>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch
new file mode 100644
index 000000000000..7814d306607b
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch
@@ -0,0 +1,322 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Thu, 16 Nov 2023 18:15:09 +0300
+Subject: arm64: dts: Add missing nodes to Orange Pi 5 Plus
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 221 +++++++++-
+ 1 file changed, 218 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+@@ -10,6 +10,7 @@
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/usb/pd.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3588.dtsi"
+ 
+ / {
+@@ -72,6 +73,17 @@ ir-receiver {
+ 		pinctrl-0 = <&ir_receiver_pin>;
+ 	};
+ 
++	hdmi0-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi0_con_in: endpoint {
++				remote-endpoint = <&hdmi0_out_con>;
++			};
++		};
++	};
++
+ 	gpio-leds {
+ 		compatible = "gpio-leds";
+ 		pinctrl-names = "default";
+@@ -98,10 +110,10 @@ pwm-leds {
+ 
+ 		led {
+ 			color = <LED_COLOR_ID_GREEN>;
+-			function = LED_FUNCTION_INDICATOR;
+-			function-enumerator = <2>;
++			function = LED_FUNCTION_HEARTBEAT;
+ 			max-brightness = <255>;
+ 			pwms = <&pwm2 0 25000 0>;
++			linux,default-trigger = "heartbeat";
+ 		};
+ 	};
+ 
+@@ -158,6 +170,20 @@ daicodec: simple-audio-card,codec {
+ 		};
+ 	};
+ 
++	wlan-rfkill {
++		compatible = "rfkill-gpio";
++		label = "rfkill-wlan";
++		radio-type = "wlan";
++		shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
++	};
++
++	bluetooth-rfkill {
++		compatible = "rfkill-gpio";
++		label = "rfkill-bluetooth";
++		radio-type = "bluetooth";
++		shutdown-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++	};
++
+ 	vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+@@ -199,6 +225,18 @@ vcc5v0_sys: vcc5v0-sys-regulator {
+ 		regulator-max-microvolt = <5000000>;
+ 	};
+ 
++	vbus5v0_typec: vbus5v0-typec-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
++		regulator-name = "vbus5v0_typec";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&typec5v_pwren>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
+ 	vcc5v0_usb20: vcc5v0-usb20-regulator {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+@@ -311,6 +349,53 @@ hym8563: rtc@51 {
+ 		pinctrl-0 = <&hym8563_int>;
+ 		wakeup-source;
+ 	};
++
++	usbc0: usb-typec@22 {
++		compatible = "fcs,fusb302";
++		reg = <0x22>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&usbc0_int>;
++		vbus-supply = <&vbus5v0_typec>;
++
++		usb_con: connector {
++			compatible = "usb-c-connector";
++			label = "USB-C";
++			data-role = "dual";
++			power-role = "dual";
++			try-power-role = "source";
++			op-sink-microwatt = <1000000>;
++			sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
++			source-pdos = <PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					usbc0_hs: endpoint {
++						remote-endpoint = <&usb_host0_xhci_drd_sw>;
++					};
++				};
++
++				port@1 {
++					reg = <1>;
++					usbc0_ss: endpoint {
++						remote-endpoint = <&usbdp_phy0_typec_ss>;
++					};
++				};
++
++				port@2 {
++					reg = <2>;
++					usbc0_sbu: endpoint {
++						remote-endpoint = <&usbdp_phy0_typec_sbu>;
++					};
++				};
++			};
++		};
++	};
+ };
+ 
+ &i2c7 {
+@@ -383,9 +468,15 @@ &pcie3x4 {
+ };
+ 
+ &pinctrl {
++    	hdmirx {
++		hdmirx_hpd: hdmirx-hpd {
++			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
+ 	hym8563 {
+ 		hym8563_int: hym8563-int {
+-			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
+ 
+@@ -408,6 +499,14 @@ hp_detect: hp-detect {
+ 	};
+ 
+ 	usb {
++		typec5v_pwren: typec5v-pwren {
++			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		usbc0_int: usbc0-int {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
+ 		vcc5v0_usb20_en: vcc5v0-usb20-en {
+ 			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+@@ -803,6 +902,22 @@ &tsadc {
+ 	status = "okay";
+ };
+ 
++&u2phy0 {
++	status = "okay";
++};
++
++&u2phy0_otg {
++	status = "okay";
++};
++
++&u2phy1 {
++	status = "okay";
++};
++
++&u2phy1_otg {
++	status = "okay";
++};
++
+ &u2phy2 {
+ 	status = "okay";
+ };
+@@ -831,6 +946,35 @@ &uart9 {
+ 	status = "okay";
+ };
+ 
++&usbdp_phy0 {
++	orientation-switch;
++	mode-switch;
++	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
++	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
++	status = "okay";
++	svid = <0xff01>;
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		usbdp_phy0_typec_ss: endpoint@0 {
++			reg = <0>;
++			remote-endpoint = <&usbc0_ss>;
++		};
++
++		usbdp_phy0_typec_sbu: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&usbc0_sbu>;
++		};
++	};
++};
++
++&usbdp_phy1 {
++	rockchip,dp-lane-mux = <2 3>;
++	status = "okay";
++};
++
+ &usb_host0_ehci {
+ 	status = "okay";
+ };
+@@ -839,6 +983,20 @@ &usb_host0_ohci {
+ 	status = "okay";
+ };
+ 
++&usb_host0_xhci {
++	dr_mode = "otg";
++	usb-role-switch;
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		usb_host0_xhci_drd_sw: endpoint {
++			remote-endpoint = <&usbc0_hs>;
++		};
++	};
++};
++
+ &usb_host1_ehci {
+ 	status = "okay";
+ };
+@@ -846,3 +1004,60 @@ &usb_host1_ehci {
+ &usb_host1_ohci {
+ 	status = "okay";
+ };
++
++&usb_host1_xhci {
++	dr_mode = "host";
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu_s0>;
++	status = "okay";
++};
++
++&hdptxphy_hdmi0 {
++	status = "okay";
++};
++
++&hdmi0 {
++   	enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
++	status = "okay";
++};
++
++&hdmi0_in {
++	hdmi0_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi0>;
++	};
++};
++
++&hdmi0_out {
++	hdmi0_out_con: endpoint {
++		remote-endpoint = <&hdmi0_con_in>;
++	};
++};
++
++&hdmi_receiver_cma {
++	status = "disabled";
++};
++
++&hdmi_receiver {
++	hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
++	pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
++	pinctrl-names = "default";
++	status = "disabled";
++};
++
++&vop {
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi0_in_vp0>;
++	};
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch
new file mode 100644
index 000000000000..bd33b5976c41
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch
@@ -0,0 +1,39 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: amazingfate <liujianfeng1994@gmail.com>
+Date: Thu, 28 Mar 2024 16:07:18 +0800
+Subject: arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5a
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -115,6 +115,10 @@ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ 	};
+ };
+ 
++&combphy0_ps {
++	status = "okay";
++};
++
+ &combphy2_psu {
+ 	status = "okay";
+ };
+@@ -299,6 +303,11 @@ rgmii_phy1: ethernet-phy@1 {
+ 	};
+ };
+ 
++&pcie2x1l2 {
++	status = "okay";
++	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
++};
++
+ &pinctrl {
+ 	leds {
+ 		io_led: io-led {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch
new file mode 100644
index 000000000000..8ee172545f55
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch
@@ -0,0 +1,64 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+Date: Thu, 6 Jun 2024 23:28:01 +0800
+Subject: arm64: dts: rockchip: Add HDMI support to ArmSoM Sige7
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 30 ++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+@@ -4,6 +4,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3588.dtsi"
+ 
+ / {
+@@ -164,6 +165,20 @@ &gpu {
+ 	status = "okay";
+ };
+ 
++&hdmi0 {
++	status = "okay";
++};
++
++&hdmi0_in {
++	hdmi0_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi0>;
++	};
++};
++
++&hdptxphy_hdmi0 {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&i2c0m2_xfer>;
+@@ -723,3 +738,18 @@ &usb_host1_xhci {
+ 	dr_mode = "host";
+ 	status = "okay";
+ };
++
++&vop {
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi0_in_vp0>;
++	};
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch
new file mode 100644
index 000000000000..a57707485c0e
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch
@@ -0,0 +1,39 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+Date: Thu, 6 Jun 2024 23:29:39 +0800
+Subject: arm64: dts: rockchip: Add ap6275p wireless support to ArmSoM Sige7
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 16 ++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+@@ -283,6 +283,22 @@ &pcie2x1l0 {
+ &pcie2x1l1 {
+ 	reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+ 	status = "okay";
++
++	pcie@0,0 {
++		reg = <0x300000 0 0 0 0>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++		ranges;
++		device_type = "pci";
++		bus-range = <0x30 0x3f>;
++
++		wifi: wifi@0,0 {
++			compatible = "pci14e4,449d";
++			reg = <0x310000 0 0 0 0>;
++			clocks = <&hym8563>;
++			clock-names = "32k";
++		};
++	};
+ };
+ 
+ /* phy0 - left ethernet port */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1040-board-khadas-edge2-add-nodes.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1040-board-khadas-edge2-add-nodes.patch
new file mode 100644
index 000000000000..17e8fbd06bcd
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1040-board-khadas-edge2-add-nodes.patch
@@ -0,0 +1,359 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Mon, 12 Feb 2024 17:35:13 +0300
+Subject: arm64: dts: rockchip: Add USB-C to Khadas Edge 2
+
+Khadas Edge 2 has 2x Type-C port. One just supports PD and
+controlled by MCU. The other one supports PD, DP Alt mode and DRD. This
+commit adds support for DRD.
+
+Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 120 ++++++++++
+ 1 file changed, 120 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+@@ -6,6 +6,7 @@
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/leds/common.h>
++#include <dt-bindings/usb/pd.h>
+ #include "rk3588s.dtsi"
+ 
+ / {
+@@ -76,6 +77,18 @@ blue_led: led-2 {
+ 		};
+ 	};
+ 
++	vbus5v0_typec: vbus5v0-typec-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vbus5v0_typec";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
++		vin-supply = <&vcc5v0_sys>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&typec5v_pwren>;
++	};
++
+ 	vcc3v3_pcie_wl: vcc3v3-pcie-wl-regulator {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+@@ -224,6 +237,56 @@ regulator-state-mem {
+ &i2c2 {
+ 	status = "okay";
+ 
++	usbc0: usb-typec@22 {
++		compatible = "fcs,fusb302";
++		reg = <0x22>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <RK_PB5 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&usbc0_int>;
++		vbus-supply = <&vbus5v0_typec>;
++		status = "okay";
++
++		usb_con: connector {
++			compatible = "usb-c-connector";
++			label = "USB-C";
++			data-role = "dual";
++			power-role = "dual";
++			try-power-role = "source";
++			op-sink-microwatt = <1000000>;
++			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
++                		     PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
++                		     PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
++            		source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					usbc0_orien_sw: endpoint {
++						remote-endpoint = <&usbdp_phy0_orientation_switch>;
++					};
++				};
++
++				port@1 {
++					reg = <1>;
++					usbc0_role_sw: endpoint {
++						remote-endpoint = <&dwc3_0_role_switch>;
++					};
++				};
++
++				port@2 {
++					reg = <2>;
++					dp_altmode_mux: endpoint {
++						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
++					};
++				};
++			};
++		};
++	};
++
+ 	hym8563: rtc@51 {
+ 		compatible = "haoyu,hym8563";
+ 		reg = <0x51>;
+@@ -256,6 +319,16 @@ vcc5v0_host_en: vcc5v0-host-en {
+ 		};
+ 	};
+ 
++	usb-typec {
++		usbc0_int: usbc0-int {
++			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		typec5v_pwren: typec5v-pwren {
++			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	ir-receiver {
+ 		ir_receiver_pin: ir-receiver-pin {
+ 			rockchip,pins = <1  RK_PA7  RK_FUNC_GPIO  &pcfg_pull_none>;
+@@ -681,6 +754,15 @@ &uart9 {
+ 	status = "okay";
+ };
+ 
++&u2phy0 {
++	status = "okay";
++};
++
++&u2phy0_otg {
++	status = "okay";
++};
++
++
+ &u2phy2 {
+ 	status = "okay";
+ };
+@@ -707,6 +789,44 @@ &usb_host0_ohci {
+ 	status = "okay";
+ };
+ 
++&usbdp_phy0 {
++	orientation-switch;
++	mode-switch;
++	svid = <0xff01>;
++	sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
++	sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		usbdp_phy0_orientation_switch: endpoint@0 {
++			reg = <0>;
++			remote-endpoint = <&usbc0_orien_sw>;
++		};
++
++		usbdp_phy0_dp_altmode_mux: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&dp_altmode_mux>;
++		};
++	};
++};
++
++&usb_host0_xhci {
++	usb-role-switch;
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		dwc3_0_role_switch: endpoint@0 {
++			reg = <0>;
++			remote-endpoint = <&usbc0_role_sw>;
++		};
++	};
++};
++
+ &usb_host1_ehci {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Mon, 12 Feb 2024 17:35:13 +0300
+Subject: arm64: dts: rockchip: Add bluetooth support to Khadas Edge 2
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 18 +++++++++-
+ 1 file changed, 17 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+@@ -750,8 +750,24 @@ &uart2 {
+ 
+ &uart9 {
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>;
++	pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn &uart9m2_rtsn>;
+ 	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm43438-bt";
++		clocks = <&hym8563>;
++		clock-names = "lpo";
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PD5 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "host-wakeup";
++		device-wakeup-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
++		shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++		max-speed = <1500000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_wake_host_irq &bt_wake_pin &bt_reset_pin>;
++		vbat-supply = <&vcc_3v3_s3>;
++		vddio-supply = <&vcc_1v8_s3>;
++	};
+ };
+ 
+ &u2phy0 {
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Mon, 19 Feb 2024 23:32:11 +0300
+Subject: arm64: dts: rockchip: Add HDMI & VOP2 to Khadas Edge 2
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 53 ++++++++++
+ 1 file changed, 53 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+@@ -7,6 +7,7 @@
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/usb/pd.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3588s.dtsi"
+ 
+ / {
+@@ -43,6 +44,17 @@ ir-receiver {
+ 		pinctrl-0 = <&ir_receiver_pin>;
+ 	};
+ 
++	hdmi0-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi0_con_in: endpoint {
++				remote-endpoint = <&hdmi0_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "pwm-leds";
+ 
+@@ -830,6 +842,7 @@ usbdp_phy0_dp_altmode_mux: endpoint@1 {
+ };
+ 
+ &usb_host0_xhci {
++	dr-mode = "otg";
+ 	usb-role-switch;
+ 	status = "okay";
+ 
+@@ -854,3 +867,43 @@ &usb_host1_ohci {
+ &usb_host2_xhci {
+ 	status = "okay";
+ };
++
++&hdmi0 {
++	status = "okay";
++};
++
++&hdmi0_in {
++	hdmi0_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi0>;
++	};
++};
++
++&hdmi0_out {
++	hdmi0_out_con: endpoint {
++		remote-endpoint = <&hdmi0_con_in>;
++	};
++};
++
++&hdptxphy_hdmi0 {
++	status = "okay";
++};
++
++&display_subsystem {
++	clocks = <&hdptxphy_hdmi0>;
++	clock-names = "hdmi0_phy_pll";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vop {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi0_in_vp0>;
++	};
++};
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Sat, 2 Mar 2024 19:13:59 +0300
+Subject: arm64: dts: rockchip: Add AP6275P wireless support to Khadas Edge 2
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 17 ++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+@@ -368,6 +368,23 @@ &pcie2x1l2 {
+ 	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ 	vpcie3v3-supply = <&vcc3v3_pcie_wl>;
+ 	status = "okay";
++
++	pcie@0,0 {
++		reg = <0x400000 0 0 0 0>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++		ranges;
++		device_type = "pci";
++		bus-range = <0x40 0x4f>;
++
++		wifi: wifi@0,0 {
++			compatible = "pci14e4,449d";
++			reg = <0x410000 0 0 0 0>;
++			clocks = <&hym8563>;
++			clock-names = "32k";
++		};
++	};
++
+ };
+ 
+ &pwm11 {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1041-board-khadas-edge2-mcu.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1041-board-khadas-edge2-mcu.patch
new file mode 100644
index 000000000000..856b524ef432
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1041-board-khadas-edge2-mcu.patch
@@ -0,0 +1,441 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Wed, 6 Mar 2024 00:09:25 +0300
+Subject: mfd: khadas-mcu: add Edge2 registers
+
+---
+ drivers/mfd/khadas-mcu.c       |  8 +++-
+ include/linux/mfd/khadas-mcu.h | 24 ++++++++++
+ 2 files changed, 30 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c
+index 111111111111..222222222222 100644
+--- a/drivers/mfd/khadas-mcu.c
++++ b/drivers/mfd/khadas-mcu.c
+@@ -26,6 +26,10 @@ static bool khadas_mcu_reg_volatile(struct device *dev, unsigned int reg)
+ 	case KHADAS_MCU_CHECK_USER_PASSWD_REG:
+ 	case KHADAS_MCU_WOL_INIT_START_REG:
+ 	case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG:
++	case KHADAS_MCU_LED_ON_RAM_REG:
++	case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2:
++	case KHADAS_MCU_WDT_EN_REG:
++	case KHADAS_MCU_SYS_RST_REG:
+ 		return true;
+ 	default:
+ 		return false;
+@@ -69,14 +73,14 @@ static const struct regmap_config khadas_mcu_regmap_config = {
+ 	.reg_bits	= 8,
+ 	.reg_stride	= 1,
+ 	.val_bits	= 8,
+-	.max_register	= KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG,
++	.max_register	= KHADAS_MCU_SYS_RST_REG,
+ 	.volatile_reg	= khadas_mcu_reg_volatile,
+ 	.writeable_reg	= khadas_mcu_reg_writeable,
+ 	.cache_type	= REGCACHE_MAPLE,
+ };
+ 
+ static struct mfd_cell khadas_mcu_fan_cells[] = {
+-	/* VIM1/2 Rev13+ and VIM3 only */
++	/* VIM1/2 Rev13+, VIM3 and Edge2 only */
+ 	{ .name = "khadas-mcu-fan-ctrl", },
+ };
+ 
+diff --git a/include/linux/mfd/khadas-mcu.h b/include/linux/mfd/khadas-mcu.h
+index 111111111111..222222222222 100644
+--- a/include/linux/mfd/khadas-mcu.h
++++ b/include/linux/mfd/khadas-mcu.h
+@@ -35,26 +35,45 @@
+ #define KHADAS_MCU_FACTORY_TEST_REG		0x16 /* R */
+ #define KHADAS_MCU_BOOT_MODE_REG		0x20 /* RW */
+ #define KHADAS_MCU_BOOT_EN_WOL_REG		0x21 /* RW */
++#define KHADAS_MCU_BOOT_EN_DCIN_REG_V2		0x21 /* RW */
+ #define KHADAS_MCU_BOOT_EN_RTC_REG		0x22 /* RW */
+ #define KHADAS_MCU_BOOT_EN_EXP_REG		0x23 /* RW */
++#define KHADAS_MCU_LED_MODE_ON_REG_V2		0x23 /* RW */
++#define KHADAS_MCU_LED_MODE_OFF_REG_V2		0x24 /* RW */
+ #define KHADAS_MCU_BOOT_EN_IR_REG		0x24 /* RW */
+ #define KHADAS_MCU_BOOT_EN_DCIN_REG		0x25 /* RW */
++#define KHADAS_MCU_RGB_ON_R_REG			0x25 /* RW */
++#define KHADAS_MCU_RGB_ON_G_REG			0x26 /* RW */
+ #define KHADAS_MCU_BOOT_EN_KEY_REG		0x26 /* RW */
++#define KHADAS_MCU_RGB_ON_B_REG			0x27 /* RW */
+ #define KHADAS_MCU_KEY_MODE_REG			0x27 /* RW */
++#define KHADAS_MCU_RGB_OFF_R_REG		0x28 /* RW */
+ #define KHADAS_MCU_LED_MODE_ON_REG		0x28 /* RW */
++#define KHADAS_MCU_RGB_OFF_G_REG		0x29 /* RW */
+ #define KHADAS_MCU_LED_MODE_OFF_REG		0x29 /* RW */
++#define KHADAS_MCU_RGB_OFF_B_REG		0x2a /* RW */
+ #define KHADAS_MCU_SHUTDOWN_NORMAL_REG		0x2c /* RW */
+ #define KHADAS_MCU_MAC_SWITCH_REG		0x2d /* RW */
++#define KHADAS_MCU_REST_CONF_REG		0x2e /* RW */
+ #define KHADAS_MCU_MCU_SLEEP_MODE_REG		0x2e /* RW */
++#define KHADAS_MCU_BOOT_EN_IR_REG_V2		0x2f /* RW */
+ #define KHADAS_MCU_IR_CODE1_0_REG		0x2f /* RW */
+ #define KHADAS_MCU_IR_CODE1_1_REG		0x30 /* RW */
++#define KHADAS_MCU_IR1_CUST1_REG		0x30 /* RW */
+ #define KHADAS_MCU_IR_CODE1_2_REG		0x31 /* RW */
++#define KHADAS_MCU_IR1_CUST2_REG		0x31 /* RW */
+ #define KHADAS_MCU_IR_CODE1_3_REG		0x32 /* RW */
++#define KHADAS_MCU_IR1_ORDER1_REG		0x32 /* RW */
+ #define KHADAS_MCU_USB_PCIE_SWITCH_REG		0x33 /* RW */
++#define KHADAS_MCU_IR1_ORDER2_REG		0x33 /* RW */
++#define KHADAS_MCU_IR2_CUST1_REG		0x34 /* RW */
+ #define KHADAS_MCU_IR_CODE2_0_REG		0x34 /* RW */
+ #define KHADAS_MCU_IR_CODE2_1_REG		0x35 /* RW */
++#define KHADAS_MCU_IR2_CUST2_REG		0x35 /* RW */
+ #define KHADAS_MCU_IR_CODE2_2_REG		0x36 /* RW */
++#define KHADAS_MCU_IR2_ORDER1_REG		0x36 /* RW */
+ #define KHADAS_MCU_IR_CODE2_3_REG		0x37 /* RW */
++#define KHADAS_MCU_IR2_ORDER2_REG		0x36 /* RW */
+ #define KHADAS_MCU_PASSWD_USER_0_REG		0x40 /* RW */
+ #define KHADAS_MCU_PASSWD_USER_1_REG		0x41 /* RW */
+ #define KHADAS_MCU_PASSWD_USER_2_REG		0x42 /* RW */
+@@ -69,6 +88,10 @@
+ #define KHADAS_MCU_SHUTDOWN_NORMAL_STATUS_REG	0x86 /* RO */
+ #define KHADAS_MCU_WOL_INIT_START_REG		0x87 /* WO */
+ #define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG	0x88 /* WO */
++#define KHADAS_MCU_LED_ON_RAM_REG		0x89 /* WO */
++#define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2	0x8A /* WO */
++#define KHADAS_MCU_WDT_EN_REG			0x8B /* WO */
++#define KHADAS_MCU_SYS_RST_REG			0x91 /* WO */
+ 
+ enum {
+ 	KHADAS_BOARD_VIM1 = 0x1,
+@@ -76,6 +99,7 @@ enum {
+ 	KHADAS_BOARD_VIM3,
+ 	KHADAS_BOARD_EDGE = 0x11,
+ 	KHADAS_BOARD_EDGE_V,
++	KHADAS_BOARD_EDGE2,
+ };
+ 
+ /**
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Wed, 6 Mar 2024 00:09:58 +0300
+Subject: mfd: khadas-mcu: drop unused code
+
+---
+ drivers/mfd/khadas-mcu.c | 11 ----------
+ 1 file changed, 11 deletions(-)
+
+diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c
+index 111111111111..222222222222 100644
+--- a/drivers/mfd/khadas-mcu.c
++++ b/drivers/mfd/khadas-mcu.c
+@@ -84,10 +84,6 @@ static struct mfd_cell khadas_mcu_fan_cells[] = {
+ 	{ .name = "khadas-mcu-fan-ctrl", },
+ };
+ 
+-static struct mfd_cell khadas_mcu_cells[] = {
+-	{ .name = "khadas-mcu-user-mem", },
+-};
+-
+ static int khadas_mcu_probe(struct i2c_client *client)
+ {
+ 	struct device *dev = &client->dev;
+@@ -109,13 +105,6 @@ static int khadas_mcu_probe(struct i2c_client *client)
+ 		return ret;
+ 	}
+ 
+-	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
+-				   khadas_mcu_cells,
+-				   ARRAY_SIZE(khadas_mcu_cells),
+-				   NULL, 0, NULL);
+-	if (ret)
+-		return ret;
+-
+ 	if (of_property_present(dev->of_node, "#cooling-cells"))
+ 		return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
+ 					    khadas_mcu_fan_cells,
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Wed, 6 Mar 2024 00:13:10 +0300
+Subject: thermal: khadas_mcu_fan: add support for Khadas Edge 2
+
+---
+ drivers/thermal/khadas_mcu_fan.c | 77 +++++++++-
+ 1 file changed, 73 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/thermal/khadas_mcu_fan.c b/drivers/thermal/khadas_mcu_fan.c
+index 111111111111..222222222222 100644
+--- a/drivers/thermal/khadas_mcu_fan.c
++++ b/drivers/thermal/khadas_mcu_fan.c
+@@ -15,10 +15,16 @@
+ #include <linux/thermal.h>
+ 
+ #define MAX_LEVEL 3
++#define MAX_SPEED 0x64
+ 
+ struct khadas_mcu_fan_ctx {
+ 	struct khadas_mcu *mcu;
+ 	unsigned int level;
++
++	unsigned int fan_max_level;
++	unsigned int fan_register;
++	unsigned int *fan_cooling_levels;
++
+ 	struct thermal_cooling_device *cdev;
+ };
+ 
+@@ -26,9 +32,21 @@ static int khadas_mcu_fan_set_level(struct khadas_mcu_fan_ctx *ctx,
+ 				    unsigned int level)
+ {
+ 	int ret;
++	unsigned int write_level = level;
++
++	if (level > ctx->fan_max_level)
++		return -EINVAL;
++
++	if (ctx->fan_cooling_levels != NULL) {
++		write_level = ctx->fan_cooling_levels[level];
++
++		if (write_level > MAX_SPEED)
++			return -EINVAL;
++	}
++
++	ret = regmap_write(ctx->mcu->regmap, ctx->fan_register,
++			   write_level);
+ 
+-	ret = regmap_write(ctx->mcu->regmap, KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG,
+-			   level);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -40,7 +58,9 @@ static int khadas_mcu_fan_set_level(struct khadas_mcu_fan_ctx *ctx,
+ static int khadas_mcu_fan_get_max_state(struct thermal_cooling_device *cdev,
+ 					unsigned long *state)
+ {
+-	*state = MAX_LEVEL;
++	struct khadas_mcu_fan_ctx *ctx = cdev->devdata;
++
++	*state = ctx->fan_max_level;
+ 
+ 	return 0;
+ }
+@@ -61,7 +81,7 @@ khadas_mcu_fan_set_cur_state(struct thermal_cooling_device *cdev,
+ {
+ 	struct khadas_mcu_fan_ctx *ctx = cdev->devdata;
+ 
+-	if (state > MAX_LEVEL)
++	if (state > ctx->fan_max_level)
+ 		return -EINVAL;
+ 
+ 	if (state == ctx->level)
+@@ -76,6 +96,48 @@ static const struct thermal_cooling_device_ops khadas_mcu_fan_cooling_ops = {
+ 	.set_cur_state = khadas_mcu_fan_set_cur_state,
+ };
+ 
++// Khadas Edge 2 sets fan level by passing fan speed(0-100). So we need different logic here like pwm-fan cooling-levels.
++// This is optional and just necessary for Edge 2.
++static int khadas_mcu_fan_get_cooling_data_edge2(struct khadas_mcu_fan_ctx *ctx, struct device *dev) {
++	struct device_node *np = ctx->mcu->dev->of_node;
++	int num, i, ret;
++
++	if (!of_property_present(np, "cooling-levels"))
++		return 0;
++
++	ret = of_property_count_u32_elems(np, "cooling-levels");
++	if (ret <= 0) {
++		dev_err(dev, "Wrong data!\n");
++		return ret ? : -EINVAL;
++	}
++
++	num = ret;
++	ctx->fan_cooling_levels = devm_kcalloc(dev, num, sizeof(u32),
++						   GFP_KERNEL);
++	if (!ctx->fan_cooling_levels)
++		return -ENOMEM;
++
++	ret = of_property_read_u32_array(np, "cooling-levels",
++					 ctx->fan_cooling_levels, num);
++	if (ret) {
++		dev_err(dev, "Property 'cooling-levels' cannot be read!\n");
++		return ret;
++	}
++
++	for (i = 0; i < num; i++) {
++		if (ctx->fan_cooling_levels[i] > MAX_SPEED) {
++			dev_err(dev, "PWM fan state[%d]:%d > %d\n", i,
++				ctx->fan_cooling_levels[i], MAX_SPEED);
++			return -EINVAL;
++		}
++	}
++
++	ctx->fan_max_level = num - 1;
++	ctx->fan_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2;
++
++	return 0;
++}
++
+ static int khadas_mcu_fan_probe(struct platform_device *pdev)
+ {
+ 	struct khadas_mcu *mcu = dev_get_drvdata(pdev->dev.parent);
+@@ -90,6 +152,13 @@ static int khadas_mcu_fan_probe(struct platform_device *pdev)
+ 	ctx->mcu = mcu;
+ 	platform_set_drvdata(pdev, ctx);
+ 
++	ctx->fan_max_level = MAX_LEVEL;
++	ctx->fan_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG;
++
++	ret = khadas_mcu_fan_get_cooling_data_edge2(ctx, dev);
++	if (ret)
++		return ret;
++
+ 	cdev = devm_thermal_of_cooling_device_register(dev->parent,
+ 			dev->parent->of_node, "khadas-mcu-fan", ctx,
+ 			&khadas_mcu_fan_cooling_ops);
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Wed, 6 Mar 2024 00:14:58 +0300
+Subject: dt-bindings: mfd: khadas-mcu: add cooling-levels property
+
+---
+ Documentation/devicetree/bindings/mfd/khadas,mcu.yaml | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
++++ b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
+@@ -11,7 +11,7 @@ maintainers:
+ 
+ description: |
+   Khadas embeds a microcontroller on their VIM and Edge boards adding some
+-  system feature as PWM Fan control (for VIM2 rev14 or VIM3), User memory
++  system feature as PWM Fan control (for VIM2 rev14, VIM3, Edge2), User memory
+   storage, IR/Key resume control, system power LED control and more.
+ 
+ properties:
+@@ -22,6 +22,11 @@ properties:
+   "#cooling-cells": # Only needed for boards having FAN control feature
+     const: 2
+ 
++  cooling-levels:
++    description: Max speed of PWM fan. This property is necessary for Khadas Edge 2.
++    items:
++      maximum: 100
++
+   reg:
+     maxItems: 1
+ 
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Wed, 6 Mar 2024 00:17:58 +0300
+Subject: arm64: dts: rockchip: Add MCU to Khadas Edge 2
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+@@ -306,6 +306,13 @@ hym8563: rtc@51 {
+ 		clock-output-names = "hym8563";
+ 		wakeup-source;
+ 	};
++
++	khadas_mcu: system-controller@18 {
++		compatible = "khadas,mcu";
++		reg = <0x18>;
++		cooling-levels = <0 50 72 100>;
++		#cooling-cells = <2>;
++	};
+ };
+ 
+ &pinctrl {
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Mon, 25 Mar 2024 22:41:26 +0300
+Subject: arm64: dts: rockchip: Add automatic fan control to Khadas Edge 2
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 56 ++++++++++
+ 1 file changed, 56 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+@@ -315,6 +315,62 @@ khadas_mcu: system-controller@18 {
+ 	};
+ };
+ 
++&package_thermal {
++	polling-delay = <1000>;
++
++	trips {
++		package_fan0: package-fan0 {
++			temperature = <45000>;
++			hysteresis = <5000>;
++			type = "active";
++		};
++
++		package_fan1: package-fan1 {
++			temperature = <55000>;
++			hysteresis = <5000>;
++			type = "active";
++		};
++
++		package_fan2: package-fan2 {
++			temperature = <60000>;
++			hysteresis = <5000>;
++			type = "active";
++		};
++
++		package_fan3: package-fan3 {
++			temperature = <70000>;
++			hysteresis = <5000>;
++			type = "active";
++		};
++	};
++
++	cooling-maps {
++		map0 {
++			trip = <&package_fan0>;
++			cooling-device = <&khadas_mcu 0 1>;
++			contribution = <1024>;
++		};
++
++		map1 {
++			trip = <&package_fan1>;
++			cooling-device = <&khadas_mcu 1 2>;
++			contribution = <1024>;
++		};
++
++		map2 {
++			trip = <&package_fan2>;
++			cooling-device = <&khadas_mcu 2 3>;
++			contribution = <1024>;
++		};
++
++		map3 {
++			trip = <&package_fan3>;
++			cooling-device = <&khadas_mcu 3 THERMAL_NO_LIMIT>;
++			contribution = <1024>;
++		};
++	};
++};
++
+ &pinctrl {
+ 	vdd_sd {
+ 		vdd_sd_en: vdd-sd-en {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch
new file mode 100644
index 000000000000..6b842c006ea3
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch
@@ -0,0 +1,38 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ricardo Pardini <ricardo@pardini.net>
+Date: Thu, 6 Jun 2024 23:00:05 +0200
+Subject: arm64: dts: rockchip: Add NanoPC T6 SPI Flash
+
+Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 14 ++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+@@ -576,6 +576,20 @@ &sdmmc {
+ 	status = "okay";
+ };
+ 
++&sfc {
++	pinctrl-names = "default";
++	pinctrl-0 = <&fspim1_pins>;
++	status = "okay";
++
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0x0>;
++		spi-max-frequency = <50000000>;
++		spi-rx-bus-width = <4>;
++		spi-tx-bus-width = <1>;
++	};
++};
++
+ &spi2 {
+ 	status = "okay";
+ 	assigned-clocks = <&cru CLK_SPI2>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-bananapi-m7.dts b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-bananapi-m7.dts
new file mode 100644
index 000000000000..8489240ab8bd
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-bananapi-m7.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3588-armsom-sige7.dts"
+
+/ {
+	model = "Banana Pi M7";
+	compatible = "bananapi,m7", "rockchip,rk3588";
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-hinlink-h88k.dts b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-hinlink-h88k.dts
new file mode 100644
index 000000000000..ed962d5a9ee1
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-hinlink-h88k.dts
@@ -0,0 +1,858 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3588.dtsi"
+
+/ {
+	model = "HINLINK H88K";
+	compatible = "hinlink,h88k", "rockchip,rk3588";
+
+	aliases {
+		ethernet0 = &gmac0;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+		mmc2 = &sdio;
+	};
+
+	analog-sound {
+		compatible = "simple-audio-card";
+		label = "rockchip,es8388-codec";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_detect>;
+		simple-audio-card,name = "Analog";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+		simple-audio-card,bitclock-master = <&daicpu>;
+		simple-audio-card,frame-master = <&daicpu>;
+
+		simple-audio-card,widgets =
+			"Microphone", "Onboard Microphone",
+			"Microphone", "Microphone Jack",
+			"Speaker", "Speaker",
+			"Headphone", "Headphones";
+
+		simple-audio-card,routing =
+			"Headphones", "LOUT1",
+			"Headphones", "ROUT1",
+			"Speaker", "LOUT2",
+			"Speaker", "ROUT2",
+
+			/* single ended signal to LINPUT1 */
+			"LINPUT1", "Microphone Jack",
+			"RINPUT1", "Microphone Jack",
+			/* differential signal */
+			"LINPUT2", "Onboard Microphone",
+			"RINPUT2", "Onboard Microphone";
+
+		daicpu: simple-audio-card,cpu {
+			sound-dai = <&i2s0_8ch>;
+			system-clock-frequency = <12288000>;
+		};
+
+		daicodec: simple-audio-card,codec {
+			sound-dai = <&es8388>;
+			system-clock-frequency = <12288000>;
+		};
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_net_en>, <&led_sata_en>,
+			    <&led_user_en>, <&led_work_en>;
+
+		net {
+			label = "blue:net";
+			gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>;
+		};
+
+		sata {
+			label = "amber:sata";
+			gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+		};
+
+		user {
+			label = "green:user";
+			gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+		};
+
+		work {
+			label = "red:work";
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	vcc12v_dcin: vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-name = "vcc12v_dcin";
+	};
+
+	vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc3v3_pcie30";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb_hub: vcc5v0-usb-hub {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_hub_en>;
+		regulator-name = "vcc5v0_usb_hub";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac0 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	pinctrl-names = "default";
+	rx_delay = <0x00>;
+	tx_delay = <0x43>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&i2c7 {
+	pinctrl-0 = <&i2c7m0_xfer>;
+	status = "okay";
+
+	es8388: audio-codec@11 {
+		compatible = "everest,es8388";
+		reg = <0x11>;
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		AVDD-supply = <&vcc_3v3_s3>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		clock-names = "mclk";
+		DVDD-supply = <&vcc_1v8_s3>;
+		HPVDD-supply = <&vcc_3v3_s3>;
+		PVDD-supply = <&vcc_1v8_s3>;
+		#sound-dai-cells = <0>;
+
+		port {
+			es8388_p0_0: endpoint {
+				remote-endpoint = <&i2s0_8ch_p0_0>;
+			};
+		};
+	};
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_mclk
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	status = "okay";
+
+	i2s0_8ch_p0: port {
+		i2s0_8ch_p0_0: endpoint {
+			dai-format = "i2s";
+			mclk-fs = <256>;
+			remote-endpoint = <&es8388_p0_0>;
+		};
+	};
+};
+
+&mdio0 {
+	rgmii_phy: ethernet-phy@1 {
+		/* RTL8211F */
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtl8211f_rst>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pcie2x1l0 {
+	reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie2x1l1 {
+	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie2x1l2 {
+	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x4 {
+	pinctrl-names = "default";
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
+	status = "okay";
+};
+
+&pinctrl {
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_net_en: led_net_en {
+			rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_sata_en: led_sata_en {
+			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_user_en: led_user_en {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_work_en: led_work_en {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtl8211f {
+		rtl8211f_rst: rtl8211f-rst {
+			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sound {
+		hp_detect: hp-detect {
+			rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
+			rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&saradc {
+	vref-supply = <&avcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	mmc-hs200-1_8v;
+	status = "okay";
+};
+
+&sdmmc {
+	max-frequency = <200000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_s3>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	num-cs = <1>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		spi-max-frequency = <1000000>;
+		reg = <0x0>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_log_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_vdenc_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_2v0_pldo_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "avcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "avdd_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vcc_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "avdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	/* connected to USB hub, which is powered by vcc5v0_sys */
+	phy-supply = <&vcc5v0_sys>;
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy3_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usbdp_phy1 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb_host2_xhci {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-mixtile-blade3.dts b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-mixtile-blade3.dts
new file mode 100644
index 000000000000..ef0adae48ebf
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-mixtile-blade3.dts
@@ -0,0 +1,712 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588.dtsi"
+
+/ {
+	model = "Mixtile Blade 3";
+	compatible = "mixtile,blade3", "rockchip,rk3588";
+
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+		serial2 = &uart2;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	vcc12v_dcin: vcc12v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usbdcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usbdcin>;
+	};
+
+	pcie20_avdd0v85: pcie20-avdd0v85-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie20_avdd0v85";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <850000>;
+		vin-supply = <&vdd_0v85_s0>;
+	};
+
+	pcie20_avdd1v8: pcie20-avdd1v8-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie20_avdd1v8";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&avcc_1v8_s0>;
+	};
+
+	pcie30_avdd0v75: pcie30-avdd0v75-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v75";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <750000>;
+		regulator-max-microvolt = <750000>;
+		vin-supply = <&avdd_0v75_s0>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&avcc_1v8_s0>;
+	};
+
+	vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie30";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+		gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc12v_dcin>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie3_vcc3v3_en>;
+	};
+
+	vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sd_s0";
+		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwr>;
+		enable-active-high;
+	};
+
+	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_mem_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_mem_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_mem_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_mem_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1m2_xfer>;
+	status = "okay";
+
+	vdd_npu_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c4 {
+	pinctrl-0 = <&i2c4m0_xfer>;
+	status = "okay";
+};
+
+/* exposed on the 30-pin connector; shows up as i2c-3 */
+&i2c5 {
+	pinctrl-0 = <&i2c5m3_xfer>;
+	status = "okay";
+};
+
+&i2s2_2ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s2m1_mclk
+				 &i2s2m1_lrck
+				 &i2s2m1_sclk
+				 &i2s2m1_sdi
+				 &i2s2m1_sdo>;
+	status = "okay";
+};
+
+&pcie2x1l0 {
+	reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	status = "okay";
+};
+
+&pcie2x1l1 {
+	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_1_rst>;
+	status = "okay";
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x4 {
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3_rst>;
+	status = "okay";
+};
+
+&pinctrl {
+	sdmmc {
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_1_rst: pcie2-1-rst {
+			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie3 {
+		pcie3_rst: pcie3-rst {
+			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm8 {
+    pinctrl-names = "active";
+	pinctrl-0 = <&pwm8m2_pins>;
+	status = "okay";
+};
+
+&pwm14 {
+	pinctrl-0 = <&pwm14m2_pins>;
+	status = "okay";
+};
+
+&pwm15 {
+	pinctrl-0 = <&pwm15m3_pins>;
+	status = "disabled";
+};
+
+&spi4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi4m2_cs0 &spi4m2_pins>;
+	num-cs = <1>;
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vcc_1v8_s0>;
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	max-frequency = <200000000>;
+	// hs400 causes immediate trouble, hs200 works at around 150mb/s
+	// mmc-hs400-1_8v;
+	// mmc-hs400-enhanced-strobe;
+	mmc-hs200-1_8v;
+	status = "okay";
+};
+
+&sdmmc {
+	max-frequency = <150000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_s3>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	num-cs = <1>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		spi-max-frequency = <1000000>;
+		reg = <0x0>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_log_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_vdenc_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_2v0_pldo_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "avcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "avdd_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vcc_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "avdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-nanopc-cm3588-nas.dts b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-nanopc-cm3588-nas.dts
new file mode 100644
index 000000000000..f95c8a708aba
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588-nanopc-cm3588-nas.dts
@@ -0,0 +1,1436 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd.
+ * Copyright (c) 2023 Thomas McKahan
+ * Author: ColorfulRhino
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+	model = "FriendlyElec CM3588 NAS";
+	compatible = "friendlyarm,cm3588", "rockchip,rk3588";
+
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+		// nvme0 = &nvme0;
+		// nvme1 = &nvme1;
+		// nvme2 = &nvme2;
+		// nvme3 = &nvme3;
+		// ethernet0 = &r8125_u10;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-vol-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <17000>;
+		};
+	};
+
+	analog-sound {
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&headphone_detect>;
+
+		simple-audio-card,name = "realtek,rt5616-codec";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
+
+		simple-audio-card,routing =
+			"Headphones", "HPOL",
+			"Headphones", "HPOR",
+			"MIC1", "Microphone Jack",
+			"Microphone Jack", "micbias1";
+		simple-audio-card,widgets =
+			"Headphone", "Headphones",
+			"Microphone", "Microphone Jack";
+		
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0_8ch>;
+		};
+		
+		simple-audio-card,codec {
+			sound-dai = <&rt5616>;
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		cooling-levels = <0 50 100 150 200 255>;
+		pwms = <&pwm1 0 50000 0>;
+		status = "disabled";
+	};
+
+	gpio_keys: gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&key1_pin>;
+
+		button-user {
+			debounce-interval = <50>;
+			gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;
+			label = "User Button";
+			linux,code = <BTN_1>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_sys: led-0 {
+			gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+			label = "system-led";
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_sys_pin>;
+		};
+
+		led_usr: led-1 {
+			gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
+			label = "user-led";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_usr_pin>;
+		};
+	};
+
+	vcc_12v_dcin: vcc-12v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	/* vcc_5v0_sys powers peripherals */
+	vcc_5v0_sys: vcc-5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_12v_dcin>;
+	};
+
+	vcc_5v0_host_20: vcc-5v0-host-20 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_5v0_host20_en>;
+		regulator-name = "vcc_5v0_host_20";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_5v0_sys>;
+	};
+
+	vcc_5v0_host_30: vcc-5v0-host-30 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_5v0_host30_en>;
+		regulator-name = "vcc_5v0_host_30";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_5v0_sys>;
+	};
+
+	vcc_3v3_host_32: vcc-3v3-host-32-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_3v3_host32_en>;
+		regulator-name = "vcc_3v3_host_32";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_5v0_sys>;
+	};
+
+	vbus_5v0_typec: vbus-5v0-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&typec_5v_pwr_en>;
+		regulator-name = "vbus_5v0_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_5v0_sys>;
+	};
+
+	/* vcc_4v0_sys powers the RK806, RK860's */
+	vcc_4v0_sys: vcc-4v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_4v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <4000000>;
+		vin-supply = <&vcc_12v_dcin>;
+	};
+
+	vcc_3v3_pcie20: vcc-3v3-pcie20-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pcie20";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc_3v3_pcie30: vcc-3v3-pcie30-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pcie30";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_5v0_sys>;
+	};
+
+	vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sd_s0_pwr>;
+		regulator-boot-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "vcc_3v3_sd_s0";
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc-1v1-nldo-s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc_4v0_sys>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+/* Properties "clock" and "clock-names" introduced by Collabora https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/8fff68cb7cfe1e698445896252e34f79fad41720 */
+&display_subsystem {
+	clocks = <&hdptxphy_hdmi0>;
+	clock-names = "hdmi0_phy_pll";
+};
+
+/* Signal labels [SIGNAL_LABEL] are from the official CM3588 NAS schematic revision 2309 */
+/* Some GPIOs like USB, sdmmc or SPI-NOR are not listed here */
+&gpio0 {
+	gpio-line-names =
+		/* GPIO0 A0-A7 */
+		"", "", "", "",
+		"", "", "", "",
+		/* GPIO0 B0-B7 */
+		"", "", "", "",
+		"", "", "", "",
+		/* GPIO0 C0-C7 */
+		"", "", "", "",
+		"Pin 10 [UART0_RX_M0]", "Pin 08 [UART0_TX_M0/PWM4_M0]", "Pin 32 [PWM5_M1]", "",
+		/* GPIO0 D0-D7 */
+		"", "", "", "",
+		"IR sensor [PWM3_IR_M0]", "User Button", "", "";
+};
+
+&gpio1 {
+	gpio-line-names =
+		/* GPIO1 A0-A7 */
+		"Pin 27 [UART6_RX_M1]", "Pin 28 [UART6_TX_M1]", "", "",
+		"", "", "", "Pin 15",
+		/* GPIO1 B0-B7 */
+		"Pin 26", "Pin 21 [SPI0_MISO_M2]", "Pin 19 [SPI0_MOSI_M2/UART4_RX_M2]", "Pin 23 [SPI0_CLK_M2/UART4_TX_M2]",
+		"Pin 24 [SPI0_CS0_M2/UART7_RX_M2]", "Pin 22 [SPI0_CS1_M0/UART7_TX_M2]", "", "CSI-Pin 14 [MIPI_CAM2_CLKOUT]",
+		/* GPIO1 C0-C7 */
+		"", "", "", "",
+		"Headphone detect [HP_DET_L]", "", "", "",
+		/* GPIO1 D0-D7 */
+		"", "", "", "Fan [PWM1_M1]",
+		"", "", "Pin 05 [I2C8_SCL_M2]", "Pin 03 [I2C8_SDA_M2]";
+};
+
+&gpio2 {
+	gpio-line-names =
+		/* GPIO2 A0-A7 */
+		"", "", "", "",
+		"", "", "", "",
+		/* GPIO2 B0-B7 */
+		"", "", "", "",
+		"", "", "", "",
+		/* GPIO2 C0-C7 */
+		"", "CSI-Pin 11 [MIPI_CAM2_RESET_L]", "CSI-Pin 12 [MIPI_CAM2_PDN_L]", "",
+		"", "", "", "",
+		/* GPIO2 D0-D7 */
+		"", "", "", "",
+		"", "", "", "";
+};
+
+&gpio3 {
+	gpio-line-names =
+		/* GPIO3 A0-A7 */
+		"Pin 35 [SPI4_MISO_M1/PW M10_M0]", "Pin 38 [SPI4_MOSI_M1]", "Pin 40 [SPI4_CLK_M1/UART8_TX_M1]", "Pin 36 [SPI4_CS0_M1/UART8_RX_M1]",
+		"Pin 37 [SPI4_CS1_M1]", "", "DSI-Pin 12 [LCD_RST]", "Buzzer [PW M8_M0]",
+		/* GPIO3 B0-B7 */
+		"Pin 33 [PW M9_M0]", "DSI-Pin 10 [PW M2_M1/LCD_BL]", "Pin 07", "Pin 16",
+		"Pin 18", "Pin 29 [UART3_TX_M1/PW M12_M0]", "Pin 31 [UART3_RX_M1/PW M13_M0]", "Pin 12",
+		/* GPIO3 C0-C7 */
+		"DSI-Pin 08 [TP_INT_L]", "DSI-Pin 14 [TP_RST_L]", "Pin 11 [PWM14_M0]", "Pin 13 [PWM15_IR_M0]",
+		"", "", "", "DSI-Pin 06 [I2C5_SCL_M0_TP]",
+		/* GPIO3 D0-D7 */
+		"DSI-Pin 05 [I2C5_SDA_M0_TP]", "", "", "",
+		"", "", "", "";
+};
+
+&gpio4 {
+	gpio-line-names =
+		/* GPIO4 A0-A7 */
+		"", "", "", "",
+		"", "", "", "",
+		/* GPIO4 B0-B7 */
+		"", "", "", "",
+		"", "", "", "",
+		/* GPIO4 C0-C7 */
+		"", "", "", "",
+		"", "", "", "",
+		/* GPIO4 D0-D7 */
+		"", "", "", "",
+		"", "", "", "";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	sram-supply = <&vdd_gpu_mem_s0>;
+	status = "okay";
+};
+
+&hdmi0 {
+	// avdd-0v9-supply = 
+	// avdd-1v8-supply =
+	/* Dmesg error/warning:
+	* [  +0.000055] dwhdmi-rockchip fde80000.hdmi: Looking up avdd-0v9-supply from device tree
+	* [  +0.000011] dwhdmi-rockchip fde80000.hdmi: Looking up avdd-0v9-supply property in node /hdmi@fde80000 failed
+	* [  +0.000014] dwhdmi-rockchip fde80000.hdmi: supply avdd-0v9 not found, using dummy regulator
+	* [  +0.000080] dwhdmi-rockchip fde80000.hdmi: Looking up avdd-1v8-supply from device tree
+	* [  +0.000010] dwhdmi-rockchip fde80000.hdmi: Looking up avdd-1v8-supply property in node /hdmi@fde80000 failed
+	* [  +0.000010] dwhdmi-rockchip fde80000.hdmi: supply avdd-1v8 not found, using dummy regulator
+	* [  +0.001009] dwhdmi-rockchip fde80000.hdmi: registered ddc I2C bus driver
+	*/
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+// /* 4k HDMI capture controller (see rk3588.dtsi) */
+// &hdmirx_cma {
+// 	status = "okay";
+// };
+
+// &hdmirx_ctrler {
+// 	status = "okay";
+// 	hdmirx-5v-detection-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+// 	pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>;
+// 	pinctrl-names = "default";
+// 	memory-region = <&hdmirx_cma>;
+// };
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_4v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_4v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	vdd_npu_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_4v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c4m3_xfer>;
+	status = "disabled";
+};
+
+/* Connected to MIPI-DSI0 */
+&i2c5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5m0_xfer>;
+	status = "disabled";
+};
+
+&i2c6 {
+	clock-frequency = <200000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c6m0_xfer>;
+	status = "okay";
+
+	fusb302: typec-portc@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-0 = <&usbc0_int>;
+		pinctrl-names = "default";
+		vbus-supply = <&vbus_5v0_typec>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+				port@0 {
+				reg = <0>;
+				usbc0_role_sw: endpoint@0 {
+					remote-endpoint = <&dwc3_0_role_switch>;
+				};
+			};
+		};
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			op-sink-microwatt = <1000000>;
+			power-role = "dual";
+			source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			try-power-role = "sink";
+
+			altmodes {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				altmode@0 {
+					reg = <0>;
+					svid = <0xff01>;
+					vdo = <0xffffffff>;
+				};
+			};
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dp_altmode_mux: endpoint {
+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		wakeup-source;
+	};
+};
+
+/* Connected to MIPI-CSI1 */
+&i2c7 {
+	clock-frequency = <200000>;
+	status = "okay";
+
+	rt5616: audio-codec@1b {
+		compatible = "realtek,rt5616";
+		reg = <0x1b>;
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		clock-names = "mclk";
+		#sound-dai-cells = <0>;
+
+		port {
+			rt5616_p0_0: endpoint {
+				remote-endpoint = <&i2s0_8ch_p0_0>;
+			};
+		};
+	};
+};
+
+/* GPIO Connector, connected to 40-pin GPIO header */
+&i2c8 {
+	pinctrl-0 = <&i2c8m2_xfer>;
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+				&i2s0_mclk
+				&i2s0_sclk
+				&i2s0_sdi0
+				&i2s0_sdo0>;
+	status = "okay";
+
+	i2s0_8ch_p0: port {
+		i2s0_8ch_p0_0: endpoint {
+			dai-format = "i2s";
+			mclk-fs = <256>;
+			remote-endpoint = <&rt5616_p0_0>;
+		};
+	};
+};
+
+&i2s5_8ch {
+	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};
+
+&i2s7_8ch {
+	status = "okay";
+};
+
+/* Temperature sensor near the center of the SoC */
+&package_thermal {
+	polling-delay = <1000>;
+
+	trips {
+		package_hot: package_hot {
+			hysteresis = <2000>;
+			temperature = <65000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&package_hot>;
+		};
+	};
+};
+
+&pcie2x1l0 { // @fe170000
+	/* 2. M.2 slot, CON14: pcie30phy port0 lane1 */
+	max-link-speed = <3>;
+	num-lanes = <1>;
+	phys = <&pcie30phy>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie30>;
+	status = "okay";
+
+	// pcie@0,0 {
+	// 	reg = <0x00200000 0 0 0 0>;
+	// 	#address-cells = <3>;
+	// 	#size-cells = <2>;
+
+	// 	nvme1: pcie@20,0 {
+	// 		reg = <0x000000 0 0 0 0>;
+	// 	};
+	// };
+};
+
+&pcie2x1l1 { // @fe180000
+	/* 4. M.2 slot, CON16: pcie30phy port1 lane1 */
+	max-link-speed = <3>;
+	num-lanes = <1>;
+	phys = <&pcie30phy>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_1_rst>;
+	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie30>;
+	status = "okay";
+
+	// pcie@0,0 {
+	// 	reg = <0x00300000 0 0 0 0>;
+	// 	#address-cells = <3>;
+	// 	#size-cells = <2>;
+
+	// 	nvme3: pcie@30,0 {
+	// 		reg = <0x000000 0 0 0 0>;
+	// 	};
+	// };
+};
+
+&pcie2x1l2 { // @fe190000
+	/* r8125 ethernet */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_2_rst>;
+	reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie20>;
+	status = "okay";
+
+	// pcie@0,0 {
+	// 	reg = <0x00400000 0 0 0 0>;
+	// 	#address-cells = <3>;
+	// 	#size-cells = <2>;
+
+	// 	r8125_u10: pcie@40,0 {
+	// 		reg = <0x000000 0 0 0 0>;
+	// 		local-mac-address = [ 00 00 00 00 00 00 ];
+	// 	};
+	// };
+};
+
+&pcie30phy {
+	/*
+	* Michal Tomek describes:
+	* The PHY offers the following mapping options:
+	* 
+	* port 0 lane 0 - always mapped to controller 0 (4L)
+ 	* port 0 lane 1 - to controller 0 or 2 (1L0)
+	* port 1 lane 0 - to controller 0 or 1 (2L)
+	* port 1 lane 1 - to controller 0, 1 or 3 (1L1)
+	* 
+	* The data-lanes DT property maps these as follows:
+	* 
+	* 0 = no controller (unsupported by the HW)
+ 	* 1 = 4L
+	* 2 = 2L
+	* 3 = 1L0
+ 	* 4 = 1L1
+	*
+	* <1 3 2 4> = NABIBI = [3 3] = x1x1 x1x1 (bif. of both ports;
+	*/
+	data-lanes = <1 3 2 4>;
+	status = "okay";
+};
+
+&pcie3x4 { // @fe150000
+	/* 1. M.2 slot, CON13: pcie30phy port0 lane0 */
+	max-link-speed = <3>;
+	num-lanes = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3x4_rst>;
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie30>;
+	status = "okay";
+
+	// pcie@0,0 {
+	// 	reg = <0x00000000 0 0 0 0>;
+	// 	#address-cells = <3>;
+	// 	#size-cells = <2>;
+
+	// 	nvme0: pcie@0,0 {
+	// 		reg = <0x000000 0 0 0 0>;
+	// 	};
+	// };
+};
+
+&pcie3x2 { // @fe160000
+	/* 3. M.2 slot, CON15: pcie30phy port1 lane0 */
+	max-link-speed = <3>;
+	num-lanes = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3x2_rst>;
+	reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie30>;
+	status = "okay";
+
+	// pcie@0,0 {
+	// 	reg = <0x00100000 0 0 0 0>;
+	// 	#address-cells = <3>;
+	// 	#size-cells = <2>;
+
+	// 	nvme2: pcie@10,0 {
+	// 		reg = <0x000000 0 0 0 0>;
+	// 	};
+	// };
+};
+
+&pinctrl {
+	audio {
+		headphone_detect: headphone-detect {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gpio-key {
+		key1_pin: key1-pin {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gpio-leds {
+		led_sys_pin: led-sys-pin {
+			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_usr_pin: led-usr-pin {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pcie {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_1_rst: pcie2-1-rst {
+			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_2_rst: pcie2-2-rst {
+			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie3x2_rst: pcie3x2-rst {
+			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie3x4_rst: pcie3x4-rst {
+			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc {
+		sd_s0_pwr: sd-s0-pwr {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc_5v0_host20_en: vcc-5v0-host20-en {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc_5v0_host30_en: vcc-5v0-host30-en {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		
+		vcc_3v3_host32_en: vcc-3v3-host32-en {
+			rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		typec_5v_pwr_en: typec-5v-pwr-en {
+			rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+/* Connected to 5V Fan */
+&pwm1 {
+	pinctrl-0 = <&pwm1m1_pins>;
+	status = "okay";
+};
+
+/* Connected to MIPI-DSI0 */
+&pwm2 {
+	pinctrl-0 = <&pwm2m1_pins>;
+};
+
+/* GPIO Connector, connected to 40-pin GPIO header */
+&pwm5 {
+	pinctrl-0 = <&pwm5m1_pins>;
+	status = "okay";
+};
+
+/* GPIO Connector */
+&pwm8 {
+	pinctrl-0 = <&pwm8m0_pins>;
+	status = "okay";
+};
+
+/* GPIO Connector */
+&pwm9 {
+	pinctrl-0 = <&pwm9m0_pins>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&avcc_1v8_s0>;
+	status = "okay";
+};
+
+/* eMMC */
+&sdhci {
+	bus-width = <8>;
+	full-pwr-cycle-in-suspend;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	no-sd;
+	no-sdio;
+	non-removable;
+	status = "okay";
+};
+
+/* microSD card */
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	max-frequency = <150000000>;
+	no-mmc;
+	no-sdio;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_sd_s0>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+/* GPIO Connector */
+&spi0 {
+	num-cs = <1>;
+	pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>;
+	status = "disabled";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	num-cs = <1>;
+
+	rk806_single: pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0x0>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		
+		spi-max-frequency = <1000000>;
+
+		system-power-controller;
+
+		vcc1-supply = <&vcc_4v0_sys>;
+		vcc2-supply = <&vcc_4v0_sys>;
+		vcc3-supply = <&vcc_4v0_sys>;
+		vcc4-supply = <&vcc_4v0_sys>;
+		vcc5-supply = <&vcc_4v0_sys>;
+		vcc6-supply = <&vcc_4v0_sys>;
+		vcc7-supply = <&vcc_4v0_sys>;
+		vcc8-supply = <&vcc_4v0_sys>;
+		vcc9-supply = <&vcc_4v0_sys>;
+		vcc10-supply = <&vcc_4v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc_4v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc_4v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_log_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_vdenc_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_2v0_pldo_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "avcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "avdd_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vcc_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "avdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+/* GPIO Connector, connected to 40-pin GPIO header */
+&spi4 {
+	num-cs = <1>;
+	pinctrl-0 = <&spi4m1_cs0 &spi4m1_pins>;
+	status = "disabled";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+/* GPIO Connector, connected to 40-pin GPIO header */
+&uart0 {
+	pinctrl-0 = <&uart0m0_xfer>;
+	status = "disabled";
+};
+
+/* Debug UART */
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+/* GPIO Connector, connected to 40-pin GPIO header */
+&uart3 {
+	pinctrl-0 = <&uart3m1_xfer>;
+	status = "disabled";
+};
+
+/* GPIO Connector, connected to 40-pin GPIO header */
+&uart4 {
+	pinctrl-0 = <&uart4m2_xfer>;
+	status = "disabled";
+};
+
+/* GPIO Connector, connected to 40-pin GPIO header */
+&uart6 {
+	pinctrl-0 = <&uart6m1_xfer>;
+	status = "okay";
+};
+
+/* GPIO Connector, connected to 40-pin GPIO header */
+&uart7 {
+	pinctrl-0 = <&uart7m2_xfer>;
+	status = "disabled";
+};
+
+/* GPIO Connector, connected to 40-pin GPIO header */
+&uart8 {
+	pinctrl-0 = <&uart8m1_xfer>;
+	status = "disabled";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	rockchip,typec-vbus-det; /* @TODO Note: This flag is not (yet?) present in Linux 6.9 "Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml" */
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc_5v0_host_30>;
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc_5v0_host_20>;
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy3_host {
+	phy-supply = <&vcc_3v3_host_32>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "otg";
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+/* Upper USB 3.0 port */
+&usb_host1_xhci {
+	dr_mode = "host";
+	snps,xhci-trb-ent-quirk;
+	status = "okay";
+};
+
+/* Lower USB 3.0 port */
+&usb_host2_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	orientation-switch;
+	svid = <0xff01>;
+	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		usbdp_phy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+
+		usbdp_phy0_dp_altmode_mux: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&dp_altmode_mux>;
+		};
+	};
+};
+
+&usbdp_phy1 {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-nanopi-r6c.dts b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-nanopi-r6c.dts
new file mode 100644
index 000000000000..5c8b850efe75
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-nanopi-r6c.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3588s-nanopi-r6s.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R6C";
+	compatible = "friendlyelec,nanopi-r6c", "rockchip,rk3588s";
+};
+
+&lan2_led {
+	/delete-property/ linux,default-trigger;
+	label = "user_led";
+};
+
+&pcie2x1l2 {
+	/delete-node/ pcie@0,0;
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-nanopi-r6s.dts b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-nanopi-r6s.dts
new file mode 100644
index 000000000000..b39a3fc976b5
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-nanopi-r6s.dts
@@ -0,0 +1,865 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3588s.dtsi"
+
+/ {
+	model = "FriendlyElec NanoPi R6S";
+	compatible = "friendlyelec,nanopi-r6s", "rockchip,rk3588s";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+		serial2 = &uart2;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		sys_led: led-0 {
+			label = "sys_led";
+			gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&sys_led_pin>;
+		};
+
+		wan_led: led-1 {
+			label = "wan_led";
+			gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "r8169-3-3100:00:link";
+			pinctrl-names = "default";
+			pinctrl-0 = <&wan_led_pin>;
+		};
+
+		lan1_led: led-2 {
+			label = "lan1_led";
+			gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "r8169-4-4100:00:link";
+			pinctrl-names = "default";
+			pinctrl-0 = <&lan1_led_pin>;
+		};
+
+		lan2_led: led-3 {
+			label = "lan2_led";
+			gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "stmmac-0:01:link";
+			pinctrl-names = "default";
+			pinctrl-0 = <&lan2_led_pin>;
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-maskrom {
+			label = "Maskrom";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <1800>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&key1_pin>;
+
+		button-user {
+			label = "User";
+			linux,code = <BTN_1>;
+			gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
+			debounce-interval = <50>;
+			wakeup-source;
+		};
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sd_s0";
+		enable-active-high;
+		regulator-boot-on;
+		gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sd_s0_pwr>;
+		regulator-max-microvolt = <3000000>;
+		regulator-min-microvolt = <3000000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pcie20";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_otg0";
+		enable-active-high;
+		gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&typec5v_pwren>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_host_20: vcc5v0-host-20-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host_20";
+		enable-active-high;
+		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host20_en>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+	pinctrl-names = "default";
+	tx_delay = <0x42>;
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_mem_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_mem_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_mem_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_mem_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-compatible = "rk860x-reg";
+		regulator-name = "vdd_npu_s0";
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		regulator-boot-on;
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c6 {
+	clock-frequency = <200000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c6m0_xfer>;
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+
+	eeprom@53 {
+		compatible = "microchip,24c02", "atmel,24c02";
+		reg = <0x53>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		pagesize = <16>;
+		size = <256>;
+
+		eui_48: eui-48@fa {
+			reg = <0xfa 0x06>;
+		};
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <0x1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtl8211f_rst>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pcie2x1l1 {
+	reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie20>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00300000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		r8125_u25: pcie@30,0 {
+			reg = <0x000000 0 0 0 0>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+		};
+	};
+};
+
+&pcie2x1l2 {
+	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie20>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00400000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		r8125_u40: pcie@40,0 {
+			reg = <0x000000 0 0 0 0>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+		};
+	};
+};
+
+&pinctrl {
+	gpio-key {
+		key1_pin: key1-pin {
+			rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gpio-leds {
+		sys_led_pin: sys-led-pin {
+			rockchip,pins =
+				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_pin: wan-led-pin {
+			rockchip,pins =
+				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lan1_led_pin: lan1-led-pin {
+			rockchip,pins =
+				<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lan2_led_pin: lan2-led-pin {
+			rockchip,pins =
+				<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	hym8563 {
+		rtc_int: rtc-int {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdmmc {
+		sd_s0_pwr: sd-s0-pwr {
+			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vcc5v0_host20_en: vcc5v0-host20-en {
+			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtl8211f {
+		rtl8211f_rst: rtl8211f-rst {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&saradc {
+	vref-supply = <&avcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	/* HS400 doesn't work properly -> https://github.com/torvalds/linux/commit/cee572756aa2cb46e959e9797ad4b730b78a050b */
+	mmc-hs200-1_8v;
+	max-frequency = <200000000>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <150000000>;
+	no-mmc;
+	no-sdio;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_sd_s0>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	num-cs = <1>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		spi-max-frequency = <1000000>;
+		reg = <0x0>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fudr_moden0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_log_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-init-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_vdenc_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_2v0_pldo_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "avcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "avdd_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vcc_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "avdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg0>;
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc5v0_host_20>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	extcon = <&u2phy0>;
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	status = "okay";
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-orangepi-5.dts b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-orangepi-5.dts
new file mode 100644
index 000000000000..ea8c082a58c9
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-orangepi-5.dts
@@ -0,0 +1,814 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3588s.dtsi"
+
+/ {
+	model = "Xunlong Orange Pi 5";
+	compatible = "xunlong,orangepi-5", "rockchip,rk3588s";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <1800>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_gpio>;
+
+		led-1 {
+			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+			label = "status_led";
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&typec5v_pwren>;
+		regulator-name = "vbus_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
+		compatible = "regulator-fixed";
+		enable-active-low;
+		gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
+		regulator-name = "vcc_3v3_sd_s0";
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc3v3_pcie20: vcc3v3-pcie20-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc3v3_pcie20";
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		startup-delay-us = <50000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+	pinctrl-names = "default";
+	tx_delay = <0x42>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	vdd_npu_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c6m3_xfer>;
+	status = "okay";
+
+	usbc0: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus_typec>;
+		status = "okay";
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			op-sink-microwatt = <1000000>;
+			power-role = "dual";
+			sink-pdos =
+				<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			try-power-role = "source";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_hs: endpoint {
+						remote-endpoint = <&usb_host0_xhci_drd_sw>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					usbc0_ss: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					usbc0_sbu: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_sbu>;
+					};
+				};
+			};
+		};
+	};
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pcie2x1l2 {
+	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie20>;
+	status = "okay";
+};
+
+&pinctrl {
+	gpio-func {
+		leds_gpio: leds-gpio {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&saradc {
+	vref-supply = <&avcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <150000000>;
+	no-mmc;
+	no-sdio;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_sd_s0>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&sfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&fspim0_pins>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <100000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0x0>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+				<&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: dcdc-reg1 {
+				regulator-name = "vdd_gpu_s0";
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: dcdc-reg2 {
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-name = "vdd_log_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: dcdc-reg4 {
+				regulator-name = "vdd_vdenc_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-name = "vdd_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 {
+				regulator-name = "vdd2_ddr_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1100000>;
+				regulator-min-microvolt = <1100000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-name = "vdd_2v0_pldo_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-name = "vcc_3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-name = "vddq_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-name = "vcc_1v8_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-name = "avcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-name = "vcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-name = "avdd_1v2_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-name = "vcc_3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-name = "vccio_sd_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-name = "pldo6_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-name = "vdd_0v75_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-name = "vdd_ddr_pll_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-name = "avdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-name = "vdd_0v85_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-name = "vdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy3_host {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	mode-switch;
+	orientation-switch;
+	sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbdp_phy0_typec_ss: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_ss>;
+		};
+
+		usbdp_phy0_typec_sbu: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&usbc0_sbu>;
+		};
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		usb_host0_xhci_drd_sw: endpoint {
+			remote-endpoint = <&usbc0_hs>;
+		};
+	};
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host2_xhci {
+	status = "okay";
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&hdmi0 {
+   	enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-orangepi-5b.dts b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-orangepi-5b.dts
new file mode 100644
index 000000000000..3194df7a5fc8
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-orangepi-5b.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3588s-orangepi-5.dts"
+
+/ {
+	model = "Xunlong Orange Pi 5B";
+	compatible = "xunlong,orangepi-5b", "rockchip,rk3588s";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	/* HS400 doesn't work properly -> https://github.com/torvalds/linux/commit/cee572756aa2cb46e959e9797ad4b730b78a050b */
+	mmc-hs200-1_8v;
+	max-frequency = <200000000>;
+	status = "okay";
+};
+
+&sfc {
+	status = "disabled";
+};
+
+&pcie2x1l2 {
+	pcie@0,0 {
+		reg = <0x400000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x40 0x4f>;
+
+		wifi: wifi@0,0 {
+			compatible = "pci14e4,449d";
+			reg = <0x410000 0 0 0 0>;
+			clocks = <&hym8563>;
+			clock-names = "32k";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-rock-5c.dts b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-rock-5c.dts
new file mode 100644
index 000000000000..0666da126cf0
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/dt/rk3588s-rock-5c.dts
@@ -0,0 +1,825 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3588s.dtsi"
+
+/ {
+	model = "Radxa ROCK 5 Model C";
+	compatible = "radxa,rock-5c", "rockchip,rk3588s";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+
+	analog-sound {
+		compatible = "audio-graph-card";
+		label = "rk3588-es8316";
+
+		widgets = "Microphone", "Mic Jack",
+			  "Headphone", "Headphones";
+
+		routing = "MIC2", "Mic Jack",
+			  "Headphones", "HPOL",
+			  "Headphones", "HPOR";
+
+		dais = <&i2s0_8ch_p0>;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+
+		user-led {
+			gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+		};
+
+		io-led {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 95 145 195 255>;
+		fan-supply = <&vcc_5v0>;
+		pwms = <&pwm3 0 50000 0>;
+		#cooling-cells = <2>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <5000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_5v0: vcc-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+		enable-active-high;
+		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_5v0_en>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	vdd_npu_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	eeprom: eeprom@50 {
+		compatible = "belling,bl24c16a", "atmel,24c16";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5m2_xfer>;
+};
+
+&i2c7 {
+	status = "okay";
+
+	es8316: audio-codec@11 {
+		compatible = "everest,es8316";
+		reg = <0x11>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		clock-names = "mclk";
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		#sound-dai-cells = <0>;
+
+		port {
+			es8316_p0_0: endpoint {
+				remote-endpoint = <&i2s0_8ch_p0_0>;
+			};
+		};
+	};
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_mclk
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	status = "okay";
+
+	i2s0_8ch_p0: port {
+		i2s0_8ch_p0_0: endpoint {
+			dai-format = "i2s";
+			mclk-fs = <256>;
+			remote-endpoint = <&es8316_p0_0>;
+		};
+	};
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+	pinctrl-names = "default";
+	tx_delay = <0x3a>;
+	rx_delay = <0x3e>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		/* RTL8211F */
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <0x1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtl8211f_rst>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pcie2x1l2 {
+	status = "okay";
+	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+};
+
+&pinctrl {
+	power {
+		vcc_5v0_en: vcc-5v0-en {
+			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtl8211f {
+		rtl8211f_rst: rtl8211f-rst {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_en: vcc5v0-otg-en {
+                        rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+	};
+
+	wifibt {
+		wifibt_en: wifibit-en {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		host_wake_wl: host-wake-wl {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+
+		wl_wake_host: wl-wake-host {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		host_wake_bt: host-wake-bt {
+			rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+
+		bt_wake_host: bt-wake-host {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm3m1_pins>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&avcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	max-frequency = <150000000>;
+	no-sdio;
+	no-mmc;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_s0>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0x0>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-name = "vdd_gpu_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-name = "vdd_log_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-name = "vdd_vdenc_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-name = "vdd_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-name = "vdd2_ddr_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-name = "vdd_2v0_pldo_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-name = "vcc_3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-name = "vddq_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-name = "vcc_1v8_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-name = "avcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-name = "vcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-name = "avdd_1v2_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-name = "vcc_3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-name = "vccio_sd_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-name = "pldo6_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-name = "vdd_0v75_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-name = "vdd_ddr_pll_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-name = "avdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-name = "vdd_0v85_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-name = "vdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+	vbus-supply = <&vcc5v0_otg>;
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	status = "okay";
+	phy-supply = <&vcc5v0_host>;
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy3_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	status = "okay";
+	rockchip,dp-lane-mux = <2 3>;
+};
+
+&usb_host0_ehci {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&wifibt_en &host_wake_wl &wl_wake_host &host_wake_bt &bt_wake_host>;
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host2_xhci {
+	status = "okay";
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/Makefile b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/Makefile
new file mode 100644
index 000000000000..51ee0419354c
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/Makefile
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0
+dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
+	rockchip-rk3588-sata1.dtbo \
+	rockchip-rk3588-sata2.dtbo \
+	rockchip-rk3588-hdmirx.dtbo \
+	rockchip-rk3588-i2c8-m2.dtbo \
+	rockchip-rk3588-pwm0-m0.dtbo \
+	rockchip-rk3588-pwm0-m1.dtbo \
+	rockchip-rk3588-pwm0-m2.dtbo \
+	rockchip-rk3588-pwm1-m0.dtbo \
+	rockchip-rk3588-pwm1-m1.dtbo \
+	rockchip-rk3588-pwm1-m2.dtbo \
+	rockchip-rk3588-pwm2-m1.dtbo \
+	rockchip-rk3588-pwm3-m0.dtbo \
+	rockchip-rk3588-pwm3-m1.dtbo \
+	rockchip-rk3588-pwm3-m2.dtbo \
+	rockchip-rk3588-pwm3-m3.dtbo \
+	rockchip-rk3588-pwm5-m2.dtbo \
+	rockchip-rk3588-pwm6-m0.dtbo \
+	rockchip-rk3588-pwm6-m2.dtbo \
+	rockchip-rk3588-pwm7-m0.dtbo \
+	rockchip-rk3588-pwm7-m3.dtbo \
+	rockchip-rk3588-pwm8-m0.dtbo \
+	rockchip-rk3588-pwm10-m0.dtbo \
+	rockchip-rk3588-pwm11-m0.dtbo \
+	rockchip-rk3588-pwm11-m1.dtbo \
+	rockchip-rk3588-pwm12-m0.dtbo \
+	rockchip-rk3588-pwm13-m0.dtbo \
+	rockchip-rk3588-pwm13-m2.dtbo \
+	rockchip-rk3588-pwm14-m0.dtbo \
+	rockchip-rk3588-pwm14-m1.dtbo \
+	rockchip-rk3588-pwm14-m2.dtbo \
+	rockchip-rk3588-pwm15-m0.dtbo \
+	rockchip-rk3588-pwm15-m1.dtbo \
+	rockchip-rk3588-pwm15-m2.dtbo \
+	rockchip-rk3588-pwm15-m3.dtbo \
+	rockchip-rk3588-uart1-m1.dtbo \
+	rockchip-rk3588-uart3-m1.dtbo \
+	rockchip-rk3588-uart4-m2.dtbo \
+	rockchip-rk3588-uart6-m1.dtbo \
+	rockchip-rk3588-uart7-m2.dtbo \
+	rockchip-rk3588-uart8-m1.dtbo
+
+dtb-y += $(dtbo-y)
+
+clean-files    := *.dtbo
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-hdmirx.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-hdmirx.dtso
new file mode 100644
index 000000000000..b61eff3047be
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-hdmirx.dtso
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&hdmi_receiver_cma>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&hdmi_receiver>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-i2c8-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-i2c8-m2.dtso
new file mode 100644
index 000000000000..24993c880984
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-i2c8-m2.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&i2c8>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c8m2_xfer>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm0-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm0-m0.dtso
new file mode 100644
index 000000000000..211ddc646f45
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm0-m0.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm0>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "active";
+			pinctrl-0 = <&pwm0m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm0-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm0-m1.dtso
new file mode 100644
index 000000000000..353162ec79ee
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm0-m1.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm0>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm0m1_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm0-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm0-m2.dtso
new file mode 100644
index 000000000000..f7c03e93e3b8
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm0-m2.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm0>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm0m2_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm1-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm1-m0.dtso
new file mode 100644
index 000000000000..bb19090ad249
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm1-m0.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm1>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "active";
+			pinctrl-0 = <&pwm1m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm1-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm1-m1.dtso
new file mode 100644
index 000000000000..e935135023ee
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm1-m1.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm1>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm1m1_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm1-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm1-m2.dtso
new file mode 100644
index 000000000000..155d0bd4138b
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm1-m2.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm1>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm1m2_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm10-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm10-m0.dtso
new file mode 100644
index 000000000000..281071bbbc0f
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm10-m0.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm10>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm10m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm11-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm11-m0.dtso
new file mode 100644
index 000000000000..1bebcd619d95
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm11-m0.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm11>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm11m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm11-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm11-m1.dtso
new file mode 100644
index 000000000000..b85076feabad
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm11-m1.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM11-M1";
+		compatible = "radxa,rock-5a";
+		category = "misc";
+		exclusive = "GPIO4_B4";
+		description = "Enable PWM11-M1.\nOn Radxa ROCK 5A this is pin 15.";
+	};
+
+	fragment@0 {
+		target = <&pwm11>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm11m1_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm12-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm12-m0.dtso
new file mode 100644
index 000000000000..6dc0c7ed0b58
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm12-m0.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm12>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm12m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm13-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm13-m0.dtso
new file mode 100644
index 000000000000..38ec499ce586
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm13-m0.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm13>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm13m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm13-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm13-m2.dtso
new file mode 100644
index 000000000000..0d9b225fff0d
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm13-m2.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm13>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm13m2_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm14-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm14-m0.dtso
new file mode 100644
index 000000000000..330406d939ad
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm14-m0.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm14>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "active";
+			pinctrl-0 = <&pwm14m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm14-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm14-m1.dtso
new file mode 100644
index 000000000000..82fec22ebbd1
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm14-m1.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm14>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "active";
+			pinctrl-0 = <&pwm14m1_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm14-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm14-m2.dtso
new file mode 100644
index 000000000000..7a26f2dc891a
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm14-m2.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm14>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm14m2_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m0.dtso
new file mode 100644
index 000000000000..076bef9f64d9
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m0.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM15-M0";
+		compatible = "radxa,rock-5b";
+		category = "misc";
+		exclusive = "GPIO3_C3";
+		description = "Enable PWM15-M0.\nOn Radxa ROCK 5B this is pin 7.";
+	};
+
+	fragment@0 {
+		target = <&pwm15>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm15m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m1.dtso
new file mode 100644
index 000000000000..7d3de70b05cf
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m1.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm15>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm15m1_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m2.dtso
new file mode 100644
index 000000000000..c1b2aea10acb
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m2.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm15>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm15m2_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m3.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m3.dtso
new file mode 100644
index 000000000000..79e421a4958f
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm15-m3.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM15-M3";
+		compatible = "radxa,rock-5a", "radxa,rock-5b";
+		category = "misc";
+		exclusive = "GPIO1_D7";
+		description = "Enable PWM15-M3.\nOn Radxa ROCK 5A this is pin 3.\nOn Radxa ROCK 5B this is pin 29.";
+	};
+
+	fragment@0 {
+		target = <&pwm15>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm15m3_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm2-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm2-m1.dtso
new file mode 100644
index 000000000000..653583fdb7e4
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm2-m1.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM2-M1";
+		compatible = "radxa,rock-5b";
+		category = "misc";
+		exclusive = "GPIO3_B1";
+		description = "Enable PWM2-M1.\nOn Radxa ROCK 5B this is pin 36.";
+	};
+
+	fragment@0 {
+		target = <&pwm2>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm2m1_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m0.dtso
new file mode 100644
index 000000000000..a6a9181ab596
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m0.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm3>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm3m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m1.dtso
new file mode 100644
index 000000000000..23ff1ad68993
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m1.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM3-M1";
+		compatible = "radxa,rock-5b";
+		category = "misc";
+		exclusive = "GPIO3_B2";
+		description = "Enable PWM3-M1.\nOn Radxa ROCK 5B this is pin 38.";
+	};
+
+	fragment@0 {
+		target = <&pwm3>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm3m1_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m2.dtso
new file mode 100644
index 000000000000..b70d2097ea32
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m2.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm3>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm3m2_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m3.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m3.dtso
new file mode 100644
index 000000000000..db544f2502fd
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm3-m3.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pwm3>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm3m3_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm5-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm5-m2.dtso
new file mode 100644
index 000000000000..ce26d29f33cf
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm5-m2.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM5-M2";
+		compatible = "radxa,rock-5b";
+		category = "misc";
+		exclusive = "GPIO4_C4";
+		description = "Enable PWM5-M2.\nOn Radxa ROCK 5B this is pin 18.";
+	};
+
+	fragment@0 {
+		target = <&pwm5>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm5m2_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm6-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm6-m0.dtso
new file mode 100644
index 000000000000..e4d0ce3f5864
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm6-m0.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM6-M0";
+		compatible = "radxa,rock-5a";
+		category = "misc";
+		exclusive = "GPIO0_C7";
+		description = "Enable PWM6-M0.\nOn Radxa ROCK 5A this is pin 27.";
+	};
+
+	fragment@0 {
+		target = <&pwm6>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm6m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm6-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm6-m2.dtso
new file mode 100644
index 000000000000..5e66d1d33ef4
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm6-m2.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM6-M2";
+		compatible = "radxa,rock-5b";
+		category = "misc";
+		exclusive = "GPIO4_C5";
+		description = "Enable PWM6-M2.\nOn Radxa ROCK 5B this is pin 28.";
+	};
+
+	fragment@0 {
+		target = <&pwm6>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm6m2_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm7-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm7-m0.dtso
new file mode 100644
index 000000000000..6516762486dd
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm7-m0.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM7-M0";
+		compatible = "radxa,rock-5a";
+		category = "misc";
+		exclusive = "GPIO0_D0";
+		description = "Enable PWM7-M0.\nOn Radxa ROCK 5A this is pin 28.";
+	};
+
+	fragment@0 {
+		target = <&pwm7>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm7m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm7-m3.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm7-m3.dtso
new file mode 100644
index 000000000000..9a7d919f6cd6
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm7-m3.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM7-M3";
+		compatible = "radxa,rock-5b";
+		category = "misc";
+		exclusive = "GPIO4_C6";
+		description = "Enable PWM7-M3.\nOn Radxa ROCK 5B this is pin 27.";
+	};
+
+	fragment@0 {
+		target = <&pwm7>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm7m3_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm8-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm8-m0.dtso
new file mode 100644
index 000000000000..e461cffb597a
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-pwm8-m0.dtso
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable PWM8-M0";
+		compatible = "radxa,rock-5b";
+		category = "misc";
+		exclusive = "GPIO3_A7";
+		description = "Enable PWM8-M0.\nOn Radxa ROCK 5B this is pin 33.";
+	};
+
+	fragment@0 {
+		target = <&pwm8>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&pwm8m0_pins>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-sata1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-sata1.dtso
new file mode 100644
index 000000000000..2759ab9cf7af
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-sata1.dtso
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pcie2x1l0>;
+
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+	fragment@1 {
+		target = <&sata1>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-sata2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-sata2.dtso
new file mode 100644
index 000000000000..c68e11dc1604
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-sata2.dtso
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pcie2x1l1>;
+
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+	fragment@1 {
+		target = <&sata2>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart1-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart1-m1.dtso
new file mode 100644
index 000000000000..909f6058fd69
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart1-m1.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&uart1>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&uart1m1_xfer>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart3-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart3-m1.dtso
new file mode 100644
index 000000000000..cc5522c9cd3a
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart3-m1.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&uart3>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&uart3m1_xfer>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart4-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart4-m2.dtso
new file mode 100644
index 000000000000..a371018ef585
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart4-m2.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&uart4>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&uart4m2_xfer>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart6-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart6-m1.dtso
new file mode 100644
index 000000000000..46cea59e9fee
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart6-m1.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&uart6>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&uart6m1_xfer>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart7-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart7-m2.dtso
new file mode 100644
index 000000000000..6a56f61d13de
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart7-m2.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&uart7>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&uart7m2_xfer>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart8-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart8-m1.dtso
new file mode 100644
index 000000000000..e1b3b3a38b27
--- /dev/null
+++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-uart8-m1.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&uart8>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-0 = <&uart8m1_xfer>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/0000.patching_config.yaml b/patch/kernel/archive/rockchip64-6.10/0000.patching_config.yaml
new file mode 100644
index 000000000000..61a898c1035a
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/0000.patching_config.yaml
@@ -0,0 +1,37 @@
+config: # This is file 'patch/kernel/archive/rockchip64-6.8/0000.patching_config.yaml'
+
+  # Just some info stuff; not used by the patching scripts
+  name: rockchip64-6.10
+  kind: kernel
+  type: mainline # or: vendor
+  branch: linux-6.10.y
+  last-known-good-tag: v6.10
+  maintainers:
+    - { github: rpardini, name: Ricardo Pardini, email: ricardo@pardini.net, armbian-forum: rpardini }
+    - { github: paolosabatino, name: Paolo Sabatino, email: paolo.sabatino@gmail.com, armbian-forum: jock }
+
+  # .dts files in these directories will be copied as-is to the build tree; later ones overwrite earlier ones.
+  # This is meant to provide a way to "add a board DTS" without having to null-patch them in.
+  dts-directories:
+    - { source: "dt", target: "arch/arm64/boot/dts/rockchip" }
+
+  # every file in these directories will be copied as-is to the build tree; later ones overwrite earlier ones
+  # This is meant as a way to have overlays, bare, in a directory, without having to null-patch them in.
+  # @TODO need a solution to auto-Makefile the overlays as well
+  overlay-directories:
+    - { source: "overlay", target: "arch/arm64/boot/dts/rockchip/overlay" }
+
+  # the Makefile in each of these directories will be magically patched to include the dts files copied
+  #  or patched-in; overlay subdir will be included "-y" if it exists.
+  # No more Makefile patching needed, yay!
+  auto-patch-dt-makefile:
+    - { directory: "arch/arm64/boot/dts/rockchip", config-var: "CONFIG_ARCH_ROCKCHIP" }
+
+  # configuration for when applying patches to git / auto-rewriting patches (development cycle helpers)
+  patches-to-git:
+    do-not-commit-files:
+      - "MAINTAINERS" # constant churn, drop them. sorry.
+      - "Documentation/devicetree/bindings/arm/rockchip.yaml" # constant churn, conflicts on every bump, drop it. sorry.
+    do-not-commit-regexes: # Python-style regexes
+      - "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9]+)/Makefile$" # ignore DT Makefile patches, we've an auto-patcher now
+
diff --git a/patch/kernel/archive/rockchip64-6.10/add-board-fine3399-dts.patch b/patch/kernel/archive/rockchip64-6.10/add-board-fine3399-dts.patch
new file mode 100644
index 000000000000..e4f6ac366906
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/add-board-fine3399-dts.patch
@@ -0,0 +1,876 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts b/arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts
+new file mode 100644
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts
+@@ -0,0 +1,871 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/input/input.h>
++#include "rk3399.dtsi"
++#include "rk3399-opp.dtsi"
++
++
++/ {
++	model = "Rockchip Fine3399";
++	compatible = "rockchip,fine3399", "rockchip,rk3399";
++
++	aliases {
++		mmc0 = &sdio0;
++		mmc1 = &sdmmc;
++		mmc2 = &sdhci;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	clkin_gmac: external-gmac-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "clkin_gmac";
++		#clock-cells = <0>;
++	};
++
++	dc_12v: dc-12v {
++		compatible = "regulator-fixed";
++		regulator-name = "dc_12v";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk808 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_reg_on_h>;
++		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; // bsp
++	};
++
++	/* switched by pmic_sleep */
++	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc1v8_s3";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_1v8>;
++	};
++
++	vcc3v3_sys: vcc3v3_pcie: vcc3v3_bl: vcc3v3-sys { // sch
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&dc_12v>;
++	};
++
++	vcc_sys: vcc-sys { // sch
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&dc_12v>;
++	};
++
++	vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc_phy_h>;
++		regulator-name = "vcc_phy";
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vdd_log: vdd-log {
++		compatible = "pwm-regulator";
++		pwms = <&pwm2 0 25000 1>;
++		regulator-name = "vdd_log";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1400000>;
++		vin-supply = <&vcc_sys>;
++	};
++
++	leds: gpio-leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&user_led2>;
++
++		user_led2 {
++			label = "blue:work_led";
++			gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; // sch
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++		autorepeat;
++		pinctrl-names = "default";
++		pinctrl-0 = <&power_key>;
++
++		power {
++			debounce-interval = <100>;
++			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; // bsp
++			label = "GPIO Key Power";
++			linux,code = <KEY_POWER>;
++			wakeup-source;
++		};
++	};
++
++	fan0: pwm-fan {
++		compatible = "pwm-fan";
++		cooling-levels = <0 30 60 90 120 160>;
++		#cooling-cells = <2>;
++		fan-supply = <&vcc_sys>;
++		pwms = <&pwm1 0 40000 0>;
++	};
++
++	// pwm3
++	ir-receiver {
++		compatible = "gpio-ir-receiver";
++		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&ir_int>;
++	};
++
++	adc-keys {
++		compatible = "adc-keys";
++		io-channels = <&saradc 1>;
++		io-channel-names = "buttons";
++		keyup-threshold-microvolt = <1750000>;
++		poll-interval = <100>;
++
++		recovery {
++			label = "Recovery";
++			linux,code = <KEY_VENDOR>; // ??
++			press-threshold-microvolt = <0>;
++		};
++	};
++
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		brightness-levels = <0 4 8 16 32 64 128 255>;
++		default-brightness-level = <5>;
++		pwms = <&pwm0 0 1000000 0>;
++		status = "okay";
++	};
++
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l1 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l2 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l3 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_b1 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&cpu_thermal {
++	trips {
++		cpu_warm: cpu_warm {
++			temperature = <50000>;
++			hysteresis = <2000>;
++			type = "active";
++		};
++
++		cpu_hot: cpu_hot {
++			temperature = <65000>;
++			hysteresis = <2000>;
++			type = "active";
++		};
++	};
++
++	cooling-maps {
++		map2 {
++			trip = <&cpu_warm>;
++			cooling-device = <&fan0 THERMAL_NO_LIMIT 1>;
++		};
++
++		map3 {
++			trip = <&cpu_hot>;
++			cooling-device = <&fan0 4 THERMAL_NO_LIMIT>;
++		};
++	};
++};
++
++&emmc_phy {
++	status = "okay";
++};
++
++&gmac {
++	assigned-clocks = <&cru SCLK_RMII_SRC>;
++	assigned-clock-parents = <&clkin_gmac>;
++	clock_in_out = "input";
++	phy-supply = <&vcc_phy>;
++	phy-mode = "rgmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; // bsp
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 50000>;
++	tx_delay = <0x28>;
++	rx_delay = <0x11>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&gpu_thermal {
++	trips {
++		gpu_warm: gpu_warm {
++			temperature = <50000>;
++			hysteresis = <2000>;
++			type = "active";
++		};
++
++		gpu_hot: gpu_hot {
++			temperature = <65000>;
++			hysteresis = <2000>;
++			type = "active";
++		};
++	};
++
++	cooling-maps {
++		map1 {
++			trip = <&gpu_warm>;
++			cooling-device = <&fan0 THERMAL_NO_LIMIT 1>;
++		};
++
++		map2 {
++			trip = <&gpu_hot>;
++			cooling-device = <&fan0 4 THERMAL_NO_LIMIT>;
++		};
++	};
++};
++
++&hdmi {
++	ddc-i2c-bus = <&i2c3>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&hdmi_cec>;
++	status = "okay";
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	i2c-scl-rising-time-ns = <168>;
++	i2c-scl-falling-time-ns = <4>;
++	status = "okay";
++
++	rk808: pmic@1b {
++		compatible = "rockchip,rk808";
++		reg = <0x1b>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk808-clkout2";
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++		vcc10-supply = <&vcc3v3_sys>;
++		vcc11-supply = <&vcc3v3_sys>;
++		vcc12-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc1v8_pmu>;
++
++		regulators {
++			vdd_center: DCDC_REG1 {
++				regulator-name = "vdd_center";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_l: DCDC_REG2 {
++				regulator-name = "vdd_cpu_l";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG4 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc1v8_dvp: LDO_REG1 {
++				regulator-name = "vcc1v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v0_tp: LDO_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-name = "vcc3v0_tp";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc1v8_pmu: LDO_REG3 {
++				regulator-name = "vcc1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_sd: LDO_REG4 {
++				regulator-name = "vcc_sd";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca3v0_codec: LDO_REG5 {
++				regulator-name = "vcca3v0_codec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v5: LDO_REG6 {
++				regulator-name = "vcc_1v5";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <1500000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1500000>;
++				};
++			};
++
++			vcca1v8_codec: LDO_REG7 {
++				regulator-name = "vcca1v8_codec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v0: LDO_REG8 {
++				regulator-name = "vcc_3v0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc3v3_s3: SWITCH_REG1 {
++				regulator-name = "vcc3v3_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_s0: SWITCH_REG2 {
++				regulator-name = "vcc3v3_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++
++	vdd_cpu_b: regulator@40 {
++		compatible = "silergy,syr827";
++		reg = <0x40>;
++		fcs,suspend-voltage-selector = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cpu_b_sleep>;
++		regulator-name = "vdd_cpu_b";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_gpu: regulator@41 {
++		compatible = "silergy,syr828";
++		reg = <0x41>;
++		fcs,suspend-voltage-selector = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&gpu_sleep>;
++		regulator-name = "vdd_gpu";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++};
++
++// Used for HDMI
++&i2c3 {
++	i2c-scl-rising-time-ns = <450>;
++	i2c-scl-falling-time-ns = <15>;
++	status = "okay";
++};
++
++// HDMI sound
++&i2s2 {
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
++&io_domains {
++	status = "okay";
++
++	bt656-supply = <&vcc_3v0>;
++	audio-supply = <&vcca1v8_codec>;
++	sdmmc-supply = <&vcc_sd>;
++	gpio1830-supply = <&vcc_3v0>;
++};
++
++&pmu_io_domains {
++	status = "okay";
++	pmu1830-supply = <&vcc_1v8>;
++};
++
++&pcie_phy {
++	status = "okay";
++};
++
++&pcie0 {
++	ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; // sch
++	max-link-speed = <2>;
++	num-lanes = <2>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_clkreqn_cpm>;
++	status = "okay";
++};
++
++&pinctrl {
++	pmic {
++		cpu_b_sleep: cpu-b-sleep {
++			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		gpu_sleep: gpu-sleep {
++			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		pmic_dvs2: pmic-dvs2 {
++			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_reg_on_h: wifi-reg-on-h {
++			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	wifi {
++		wifi_host_wake_l: wifi-host-wake-l {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	spi2 {
++		spi2_cs0: spi2-cs0 {
++			rockchip,pins =
++				<2 RK_PB4 2 &pcfg_pull_up>;
++		};
++	};
++
++	display_pin:display-pin {
++		DC_pin: dc-pin {
++			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++		reset_pin: reset-pin {
++			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	bt {
++		bt_enable_h: bt-enable-h {
++			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_host_wake_l: bt-host-wake-l {
++			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		bt_wake_l: bt-wake-l {
++			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	gmac {
++		vcc_phy_h: vcc-phy-h {
++			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	leds {
++		user_led2: user_led2 {
++			rockchip,pins =
++				<2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	ir {
++		ir_int: ir-int {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	buttons {
++		power_key: power_key {
++			rockchip,pins = 
++				<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++// TFT
++&pwm0 {
++	status = "okay";
++};
++
++// FAN
++&pwm1 {
++	status = "okay";
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca1v8_s3>;
++	status = "okay";
++};
++
++&sdio0 {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	clock-frequency = <50000000>;
++	disable-wp;
++	keep-power-in-suspend;
++	max-frequency = <50000000>;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
++	sd-uhs-sdr104;
++	#address-cells = <1>;
++	#size-cells = <0>;
++	status = "okay";
++
++	brcmf: wifi@1 {
++		reg = <1>;
++		compatible = "brcm,bcm4329-fmac";
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
++		interrupt-names = "host-wake";
++		brcm,drive-strength = <5>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_host_wake_l>;
++	};
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // bsp
++	clock-frequency = <150000000>;
++	disable-wp;
++	sd-uhs-sdr104;
++	max-frequency = <150000000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
++	vqmmc-supply = <&vcc_sd>;
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	keep-power-in-suspend;
++	non-removable;
++	status = "okay";
++};
++/*
++&spi1 {
++	status = "okay";
++
++	norflash: flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <50000000>;
++	};
++};
++*/
++
++&spi2 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi2_clk &spi2_tx &spi2_cs0>;
++
++	st7735r@0 {
++		status = "okay";
++		compatible = "sitronix,st7735r";
++		reg = <0>;
++		rgb;
++		rotate = <270>;
++		width = <80>;
++		height = <160>;
++		fps = <30>;
++		buswidth = <8>;
++		backlight = <&backlight>;
++		dc-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
++		reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
++		led-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;  
++		spi-max-frequency = <32000000>;
++		spi-cpol;
++		spi-cpha;
++	};
++};
++
++&tcphy0 {
++	status = "okay";
++};
++
++&tcphy1 {
++	status = "okay";
++};
++
++&tsadc {
++	/* tshut mode 0:CRU 1:GPIO */
++	rockchip,hw-tshut-mode = <1>;
++	/* tshut polarity 0:LOW 1:HIGH */
++	rockchip,hw-tshut-polarity = <1>;
++	status = "okay";
++};
++
++&u2phy0 {
++	status = "okay";
++
++	u2phy0_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy0_host: host-port {
++		status = "okay";
++	};
++};
++
++&u2phy1 {
++	status = "okay";
++
++	u2phy1_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy1_host: host-port {
++		status = "okay";
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
++	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm43438-bt";
++		clocks = <&rk808 1>;
++		clock-names = "lpo";
++		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
++		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
++		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
++		max-speed = <4000000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
++		vbat-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc_1v8>;
++	};
++};
++
++// Debug TTL
++&uart2 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usbdrd3_0 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_0 {
++	status = "okay";
++	dr_mode = "host";
++};
++
++&usbdrd3_1 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_1 {
++	status = "okay";
++	dr_mode = "host";
++};
++
++&vopb {
++	status = "okay";
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&vopl {
++	status = "okay";
++};
++
++&vopl_mmu {
++	status = "okay";
++};
++
++&iep_mmu {
++	status = "okay";
++};
diff --git a/patch/kernel/archive/rockchip64-6.10/add-board-helios64.patch b/patch/kernel/archive/rockchip64-6.10/add-board-helios64.patch
new file mode 100644
index 000000000000..be107a49e16a
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/add-board-helios64.patch
@@ -0,0 +1,1038 @@
+From 98834ee2745daea7ee9c2f620acc1d09a4da2cdc Mon Sep 17 00:00:00 2001
+From: Aditya Prayoga <aditya@kobol.io>
+Date: Tue, 15 Sep 2020 20:04:22 +0700
+Subject: [PATCH] Add board Helios64
+
+note: rpardini: this patch was rebased on top of 6.3.1, finally admitting
+that it used to blindly overwrite the mainline dts (it was added when helios64
+was not in the tree, and thus a "file addition"). the resulting patch
+is the complete set of changes actually done.
+
+Signed-off-by: Aditya Prayoga <aditya@kobol.io>
+---
+ .../dts/rockchip/rk3399-kobol-helios64.dts    | 735 ++++++++++++++++--
+ 1 file changed, 654 insertions(+), 81 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+index 9586bb12a5d8..09e2cfe40696 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+@@ -11,6 +11,10 @@
+  */
+ 
+ /dts-v1/;
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/usb/pd.h>
+ #include "rk3399.dtsi"
+ #include "rk3399-opp.dtsi"
+ 
+@@ -48,6 +52,25 @@ chosen {
+ 		stdout-path = "serial2:1500000n8";
+ 	};
+ 
++	adc-keys {
++		compatible = "adc-keys";
++		io-channels = <&saradc 1>;
++		io-channel-names = "buttons";
++		keyup-threshold-microvolt = <1800000>;
++		poll-interval = <100>;
++
++		user2-button {
++			label = "User Button 2";
++			linux,code = <BTN_1>;
++			press-threshold-microvolt = <100000>;
++		};
++	};
++
++	beeper: beeper {
++		compatible = "gpio-beeper";
++		gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
++	};
++
+ 	clkin_gmac: external-gmac-clock {
+ 		compatible = "fixed-clock";
+ 		clock-frequency = <125000000>;
+@@ -55,35 +78,119 @@ clkin_gmac: external-gmac-clock {
+ 		#clock-cells = <0>;
+ 	};
+ 
+-	fan1 {
++	fan1: p7-fan {
+ 		/* fan connected to P7 */
+ 		compatible = "pwm-fan";
+ 		pwms = <&pwm0 0 40000 0>;
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
+ 		cooling-levels = <0 80 170 255>;
+ 	};
+ 
+-	fan2 {
++	fan2: p6-fan {
+ 		/* fan connected to P6 */
+ 		compatible = "pwm-fan";
+ 		pwms = <&pwm1 0 40000 0>;
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
+ 		cooling-levels = <0 80 170 255>;
+ 	};
+ 
+-	leds {
++	io_leds: io-gpio-leds {
++		status = "okay";
+ 		compatible = "gpio-leds";
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>;
++		pinctrl-0 = <&network_act>, <&usb3_act>,
++			<&sata_act>, <&sata_err_led>;
++
++		network	{
++			label = "helios64:blue:net";
++			gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "netdev";
++			default-state = "off";
++		};
++
++		sata	{
++			label = "helios64:blue:hdd-status";
++			gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "disk-activity";
++			default-state = "off";
++		};
++
++		sata_err1 {
++			label = "helios64:red:ata1-err";
++			gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
++			default-state = "keep";
++		};
++
++		sata_err2 {
++			label = "helios64:red:ata2-err";
++			gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
++			default-state = "keep";
++		};
++
++		sata_err3 {
++			label = "helios64:red:ata3-err";
++			gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
++			default-state = "keep";
++		};
++
++		sata_err4 {
++			label = "helios64:red:ata4-err";
++			gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
++			default-state = "keep";
++		};
+ 
+-		led-0 {
++		sata_err5 {
++			label = "helios64:red:ata5-err";
++			gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
++			default-state = "keep";
++		};
++
++		usb3 {
++			label = "helios64:blue:usb3";
++			gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
++			trigger-sources = <&int_hub_port1>,
++					<&int_hub_port2>,
++					<&int_hub_port3>;
++			linux,default-trigger = "usbport";
++			default-state = "off";
++		};
++	};
++
++	pwmleds {
++		compatible = "pwm-leds";
++		status = "okay";
++
++		power-led {
++			label = "helios64:blue:power-status";
++			pwms = <&pwm3 0 2000000000 0>;
++			max-brightness = <255>;
++		};
++	};
++
++	system_leds: system-gpio-leds {
++		status = "okay";
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&system_led>;
++
++		status-led {
+ 			label = "helios64:green:status";
+ 			gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "none";
+ 			default-state = "on";
++			mode = <0x23>;
+ 		};
+ 
+-		led-1 {
++		fault-led {
+ 			label = "helios64:red:fault";
+ 			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "panic";
+ 			default-state = "keep";
++			mode = <0x23>;
+ 		};
+ 	};
+ 
+@@ -115,7 +222,7 @@ pcie_power: pcie-power {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+ 		gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+-		pinctrl-0 = <&pcie_pwr>;
++		pinctrl-0 = <&pcie_pwr_en>;
+ 		pinctrl-names = "default";
+ 		regulator-boot-on;
+ 		regulator-name = "pcie_power";
+@@ -135,6 +242,7 @@ usblan_power: usblan-power {
+ 		vin-supply = <&vcc5v0_usb>;
+ 	};
+ 
++	/* switched by pmic_sleep */
+ 	vcc1v8_sys_s0: vcc1v8-sys-s0 {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc1v8_sys_s0";
+@@ -145,6 +253,36 @@ vcc1v8_sys_s0: vcc1v8-sys-s0 {
+ 		vin-supply = <&vcc1v8_sys_s3>;
+ 	};
+ 
++	vcc0v9_s3: vcc0v9-s3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc0v9_s3";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&vcc3v3_sys_s3>;
++	};
++
++	avdd_0v9_s0: avdd-0v9-s0 {
++		compatible = "regulator-fixed";
++		regulator-name = "avdd_0v9_s0";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&vcc1v8_sys_s3>;
++	};
++
++	avdd_1v8_s0: avdd-1v8-s0 {
++		compatible = "regulator-fixed";
++		regulator-name = "avdd_1v8_s0";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc3v3_sys_s3>;
++	};
++
+ 	vcc3v0_sd: vcc3v0-sd {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+@@ -210,6 +346,36 @@ vcc5v0_usb: vcc5v0-usb {
+ 		vin-supply = <&vcc5v0_perdev>;
+ 	};
+ 
++	vcc5v0_typec: vcc5v0-typec-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fusb0_vbus_en>;
++		regulator-name = "vcc5v0_typec";
++		vin-supply = <&vcc5v0_usb>;
++	};
++
++	vcc5v0_hdd: vcc5v0-hdd {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_hdd";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc12v_dcin_bkup>;
++	};
++
++	vcc12v_hdd: vcc12v-hdd {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc12v_hdd";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++		vin-supply = <&vcc12v_dcin_bkup>;
++	};
++
+ 	vcc12v_dcin: vcc12v-dcin {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc12v_dcin";
+@@ -228,36 +394,60 @@ vcc12v_dcin_bkup: vcc12v-dcin-bkup {
+ 		regulator-max-microvolt = <12000000>;
+ 		vin-supply = <&vcc12v_dcin>;
+ 	};
+-};
+ 
+-/*
+- * The system doesn't run stable with cpu freq enabled, so disallow the lower
+- * frequencies until this problem is properly understood and resolved.
+- */
+-&cluster0_opp {
+-	/delete-node/ opp00;
+-	/delete-node/ opp01;
+-	/delete-node/ opp02;
+-	/delete-node/ opp03;
+-	/delete-node/ opp04;
+-};
++	vdd_log: vdd-log {
++		compatible = "pwm-regulator";
++		pwms = <&pwm2 0 25000 1>;
++		pwm-supply = <&vcc5v0_sys>;
++		regulator-name = "vdd_log";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <830000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-state-mem {
++			regulator-on-in-suspend;
++			regulator-suspend-microvolt = <900000>;
++		};
++	};
+ 
+-&cluster1_opp {
+-	/delete-node/ opp00;
+-	/delete-node/ opp01;
+-	/delete-node/ opp02;
+-	/delete-node/ opp03;
+-	/delete-node/ opp04;
+-	/delete-node/ opp05;
+-	/delete-node/ opp06;
+-};
++	gpio-charger {
++		compatible = "gpio-charger";
++		charger-type = "mains";
++		gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
++		charge-status-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&ac_present_ap>, <&charger_status>;
++	};
+ 
+-&cpu_b0 {
+-	cpu-supply = <&vdd_cpu_b>;
+-};
++	gpio-keys {
++		compatible = "gpio-keys";
++		autorepeat;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pwrbtn>, <&user1btn>, <&wake_on_lan>;
++
++		power {
++			debounce-interval = <100>;
++			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
++			label = "Power";
++			linux,code = <KEY_POWER>;
++			wakeup-source;
++		};
+ 
+-&cpu_b1 {
+-	cpu-supply = <&vdd_cpu_b>;
++		user1-button {
++			debounce-interval = <100>;
++			gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>;
++			label = "User Button 1";
++			linux,code = <BTN_0>;
++			wakeup-source;
++		};
++	};
++
++	hdmi_dp_sound: hdmi-dp-sound {
++		status = "okay";
++		compatible = "rockchip,rk3399-hdmi-dp";
++		rockchip,cpu = <&i2s2>;
++		rockchip,codec = <&cdn_dp>;
++	};
+ };
+ 
+ &cpu_l0 {
+@@ -276,6 +467,20 @@ &cpu_l3 {
+ 	cpu-supply = <&vdd_cpu_l>;
+ };
+ 
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_b1 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&cdn_dp {
++	status = "okay";
++	extcon = <&fusb0>;
++	phys = <&tcphy0_dp>;
++};
++
+ &emmc_phy {
+ 	status = "okay";
+ };
+@@ -296,6 +500,11 @@ &gmac {
+ 	status = "okay";
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
+ &i2c0 {
+ 	clock-frequency = <400000>;
+ 	i2c-scl-rising-time-ns = <168>;
+@@ -311,6 +520,7 @@ rk808: pmic@1b {
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pmic_int_l>;
+ 		rockchip,system-power-controller;
++
+ 		vcc1-supply = <&vcc5v0_sys>;
+ 		vcc2-supply = <&vcc5v0_sys>;
+ 		vcc3-supply = <&vcc5v0_sys>;
+@@ -327,6 +537,19 @@ rk808: pmic@1b {
+ 		#clock-cells = <1>;
+ 
+ 		regulators {
++			vdd_center: DCDC_REG1 {
++				regulator-name = "vdd_center";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <800000>;
++				regulator-max-microvolt = <1000000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <950000>;
++				};
++			};
++
+ 			vdd_cpu_l: DCDC_REG2 {
+ 				regulator-name = "vdd_cpu_l";
+ 				regulator-always-on;
+@@ -334,19 +557,48 @@ vdd_cpu_l: DCDC_REG2 {
+ 				regulator-min-microvolt = <750000>;
+ 				regulator-max-microvolt = <1350000>;
+ 				regulator-ramp-delay = <6001>;
+-
+ 				regulator-state-mem {
+ 					regulator-off-in-suspend;
+ 				};
+ 			};
+ 
++			vcc_ddr_s3: DCDC_REG3 {
++				regulator-name = "vcc_ddr_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
+ 			vcc1v8_sys_s3: DCDC_REG4 {
+ 				regulator-name = "vcc1v8_sys_s3";
+ 				regulator-always-on;
+ 				regulator-boot-on;
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			/* not used */
++			vcc1v8_dvp: LDO_REG1 {
++				regulator-name = "vcc1v8_dvp";
++			};
+ 
++			/* not used */
++			vcc3v0_touch: LDO_REG2 {
++				regulator-name = "vcc3v0_touch";
++			};
++
++			vcc1v8_s3: LDO_REG3 {
++				regulator-name = "vcc1v8_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
+ 				regulator-state-mem {
+ 					regulator-on-in-suspend;
+ 					regulator-suspend-microvolt = <1800000>;
+@@ -359,25 +611,61 @@ vcc_sdio_s0: LDO_REG4 {
+ 				regulator-boot-on;
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <3000000>;
+-
+ 				regulator-state-mem {
+ 					regulator-on-in-suspend;
+ 					regulator-suspend-microvolt = <3000000>;
+ 				};
+ 			};
+ 
++			/* not used */
++			vcca3v0_codec: LDO_REG5 {
++				regulator-name = "vcca3v0_codec";
++			};
++
++			vcc1v5_s3: LDO_REG6 {
++				regulator-name = "vcc1v5_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <1500000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1500000>;
++				};
++			};
++
++			/* not used */
++			vcca1v8_codec: LDO_REG7 {
++				regulator-name = "vcca1v8_codec";
++			};
++
+ 			vcc3v0_s3: LDO_REG8 {
+ 				regulator-name = "vcc3v0_s3";
+ 				regulator-always-on;
+ 				regulator-boot-on;
+ 				regulator-min-microvolt = <3000000>;
+ 				regulator-max-microvolt = <3000000>;
+-
+ 				regulator-state-mem {
+ 					regulator-on-in-suspend;
+ 					regulator-suspend-microvolt = <3000000>;
+ 				};
+ 			};
++
++			vcc3v3_sys_s0: SWITCH_REG1 {
++				regulator-name = "vcc3v3_sys_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			/* not used */
++			vcc3v3_s0: SWITCH_REG2 {
++				regulator-name = "vcc3v3_s0";
++			};
+ 		};
+ 	};
+ 
+@@ -385,12 +673,33 @@ vdd_cpu_b: regulator@40 {
+ 		compatible = "silergy,syr827";
+ 		reg = <0x40>;
+ 		fcs,suspend-voltage-selector = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vsel1_gpio>;
+ 		regulator-name = "vdd_cpu_b";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <40000>;
+ 		regulator-always-on;
+ 		regulator-boot-on;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_gpu: regulator@41 {
++		compatible = "silergy,syr828";
++		reg = <0x41>;
++		fcs,suspend-voltage-selector = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vsel2_gpio>;
++		regulator-name = "vdd_gpu";
+ 		regulator-min-microvolt = <712500>;
+ 		regulator-max-microvolt = <1500000>;
+ 		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
+ 		vin-supply = <&vcc5v0_sys>;
+ 
+ 		regulator-state-mem {
+@@ -405,17 +714,101 @@ &i2c2 {
+ 	i2c-scl-falling-time-ns = <30>;
+ 	status = "okay";
+ 
++	gpio-expander@20 {
++		compatible = "nxp,pca9555";
++		reg = <0x20>;
++		gpio-controller;
++		#gpio-cells = <2>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pca0_pins>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
++		interrupt-controller;
++		#interrupt-cells = <2>;
++		vcc-supply = <&vcc3v3_sys_s3>;
++	};
++
+ 	temp@4c {
+ 		compatible = "national,lm75";
+ 		reg = <0x4c>;
+ 	};
+ };
+ 
++&i2c4 {
++	clock-frequency = <400000>;
++	i2c-scl-rising-time-ns = <160>;
++	i2c-scl-falling-time-ns = <30>;
++	status = "okay";
++
++	fusb0: typec-portc@22 {
++		compatible = "fcs,fusb302";
++		reg = <0x22>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fusb0_int>;
++		vbus-supply = <&vcc5v0_typec>;
++
++		connector {
++			compatible = "usb-c-connector";
++			label = "USB-C";
++			power-role = "dual";
++			data-role = "dual";
++			try-power-role = "sink";
++			source-pdos = <PDO_FIXED(5000, 1200, PDO_FIXED_USB_COMM)>;
++			sink-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)>;
++			op-sink-microwatt = <5000000>;
++
++			extcon-cables = <1 2 5 6 9 10 12 44>;
++			typec-altmodes = <0xff01 1 0x001c0000 1>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					usb_con_hs: endpoint {
++						remote-endpoint = <&u2phy0_typec_hs>;
++					};
++				};
++				port@1 {
++					reg = <1>;
++					usb_con_ss: endpoint {
++						remote-endpoint = <&tcphy0_typec_ss>;
++					};
++				};
++				port@2 {
++					reg = <2>;
++					usb_con_sbu: endpoint {
++						remote-endpoint = <&tcphy0_typec_dp>;
++					};
++				};
++			};
++		};
++	};
++};
++
++/* I2C on UEXT */
++&i2c7 {
++	status = "okay";
++};
++
++/* External I2C */
++&i2c8 {
++	status = "okay";
++};
++
++&i2s2 {
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
+ &io_domains {
+-	audio-supply = <&vcc1v8_sys_s0>;
+ 	bt656-supply = <&vcc1v8_sys_s0>;
+-	gpio1830-supply = <&vcc3v0_s3>;
++	audio-supply = <&vcc1v8_sys_s0>;
+ 	sdmmc-supply = <&vcc_sdio_s0>;
++	gpio1830-supply = <&vcc3v0_s3>;
+ 	status = "okay";
+ };
+ 
+@@ -428,6 +821,7 @@ &pcie0 {
+ 	max-link-speed = <2>;
+ 	num-lanes = <2>;
+ 	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_prst &pcie_clkreqn_cpm>;
+ 	status = "okay";
+ 
+ 	vpcie12v-supply = <&vcc12v_dcin>;
+@@ -437,36 +831,116 @@ &pcie0 {
+ };
+ 
+ &pinctrl {
++	buttons {
++		pwrbtn: pwrbtn {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		user1btn: usr1btn {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	charger {
++		ac_present_ap: ac-present-ap {
++			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		charger_status: charger-status {
++			rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	fan {
++		fan1_sense: fan1-sense {
++			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		fan2_sense: fan2-sense {
++			rockchip,pins = <4 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	fusb30x {
++		fusb0_int: fusb0-int {
++			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		fusb0_vbus_en: fusb0-vbus-en {
++			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
+ 	gmac {
+ 		gphy_reset: gphy-reset {
+-			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
++			rockchip,pins =
++				<3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
+ 		};
+ 	};
+ 
+ 	leds {
+-		sys_grn_led_on: sys-grn-led-on {
+-			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
++		network_act: network-act {
++			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		usb3_act: usb3-act {
++			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		sata_act: sata-act {
++			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		system_led: sys-led {
++			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>,
++					<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		sata_err_led: sata-err-led {
++			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>,
++					<2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>,
++					<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>,
++					<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>,
++					<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	misc {
++		pca0_pins: pca0-pins {
++			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 
+-		sys_red_led_on: sys-red-led-on {
+-			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
++		wake_on_lan: wake-on-lan {
++			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+ 
+ 	pcie {
+-		pcie_pwr: pcie-pwr {
++		pcie_pwr_en: pcie-pwr-en {
+ 			rockchip,pins =
+ 				<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++
++		pcie_prst: pcie-prst {
++			rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
+ 	};
+ 
+ 	pmic {
+ 		pmic_int_l: pmic-int-l {
+-			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		vsel1_gpio: vsel1-gpio {
++			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		vsel2_gpio: vsel2-gpio {
++			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ 		};
+ 	};
+ 
+-	power {
++	power  {
+ 		hdd_a_power_en: hdd-a-power-en {
+ 			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+@@ -486,7 +960,7 @@ usb_lan_en: usb-lan-en {
+ 
+ 	vcc3v0-sd {
+ 		sdmmc0_pwr_h: sdmmc0-pwr-h {
+-			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
++			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>;
+ 		};
+ 	};
+ };
+@@ -506,10 +980,29 @@ &pwm1 {
+ 	status = "okay";
+ };
+ 
++&pwm2 {
++	status = "okay";
++};
++
++&pwm3 {
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcc1v8_s3>;
++	status = "okay";
++};
++
+ &sdhci {
++	assigned-clock-rates = <150000000>;
+ 	bus-width = <8>;
+ 	mmc-hs200-1_8v;
++	// hs400 is broken on Helios64 since 5.10.60
++	// mmc-hs400-1_8v;
++	// mmc-hs400-enhanced-strobe;
++	supports-emmc;
+ 	non-removable;
++	disable-wp;
+ 	vqmmc-supply = <&vcc1v8_sys_s0>;
+ 	status = "okay";
+ };
+@@ -517,8 +1010,9 @@ &sdhci {
+ &sdmmc {
+ 	bus-width = <4>;
+ 	cap-sd-highspeed;
+-	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
++	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // TODO: verify what needs to be done to use implicit CD definition
+ 	disable-wp;
++	sd-uhs-sdr104;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ 	vmmc-supply = <&vcc3v0_sd>;
+@@ -547,6 +1041,27 @@ &spi5 {
+ 	status = "okay";
+ };
+ 
++&tcphy0 {
++	extcon = <&fusb0>;
++	status = "okay";
++};
++
++&tcphy0_dp {
++	port {
++		tcphy0_typec_dp: endpoint {
++			remote-endpoint = <&usb_con_sbu>;
++		};
++	};
++};
++
++&tcphy0_usb3 {
++	port {
++		tcphy0_typec_ss: endpoint {
++			remote-endpoint = <&usb_con_ss>;
++		};
++	};
++};
++
+ &tcphy1 {
+ 	/* phy for &usbdrd_dwc3_1 */
+ 	status = "okay";
+@@ -560,61 +1075,118 @@ &tsadc {
+ 	status = "okay";
+ };
+ 
+-&u2phy1 {
++&u2phy0 {
+ 	status = "okay";
+ 
+-	otg-port {
+-		/* phy for &usbdrd_dwc3_1 */
++	u2phy0_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy0_host: host-port {
+ 		phy-supply = <&vcc5v0_usb>;
+ 		status = "okay";
+ 	};
++
++	port {
++		u2phy0_typec_hs: endpoint {
++			remote-endpoint = <&usb_con_hs>;
++		};
++	};
++};
++
++&u2phy1 {
++	status = "okay";
++
++	u2phy1_otg: otg-port {
++		status = "okay";
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer>;
++	status = "okay";
+ };
+ 
+ &uart2 {
+ 	status = "okay";
+ };
+ 
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usbdrd3_0 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_0 {
++	status = "okay";
++	dr_mode = "otg";
++};
++
+ &usbdrd3_1 {
+ 	status = "okay";
++};
+ 
+-	usb@fe900000 {
+-		dr_mode = "host";
+-		status = "okay";
++&usbdrd_dwc3_1 {
++	dr_mode = "host";
++	status = "okay";
++
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	int_hub: hub@1 {
++		compatible = "usb2109,0815";
++		reg = <1>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
+-		hub@1 {
+-			compatible = "usb2109,0815";
++		int_hub_port1: port@1 {
+ 			reg = <1>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@1 {
+-				reg = <1>;
+-				#trigger-source-cells = <0>;
+-			};
++			#trigger-source-cells = <0>;
++		};
+ 
+-			port@2 {
+-				reg = <2>;
+-				#trigger-source-cells = <0>;
+-			};
++		int_hub_port2: port@2 {
++			reg = <2>;
++			#trigger-source-cells = <0>;
++		};
+ 
+-			port@3 {
+-				reg = <3>;
+-				#trigger-source-cells = <0>;
+-			};
++		int_hub_port3: port@3 {
++			reg = <3>;
++			#trigger-source-cells = <0>;
++		};
+ 
+-			device@4 {
+-				compatible = "usbbda,8156";
+-				reg = <4>;
+-				#address-cells = <2>;
+-				#size-cells = <0>;
++		usb_lan: device@4 {
++			compatible = "usbbda,8156";
++			reg = <4>;
++			#address-cells = <2>;
++			#size-cells = <0>;
+ 
+-				interface@0 {	/* interface 0 of configuration 1 */
+-					compatible = "usbifbda,8156.config1.0";
+-					reg = <0 1>;
+-				};
++			interface@0 {	/* interface 0 of configuration 1 */
++				compatible = "usbifbda,8156.config1.0";
++				reg = <0 1>;
+ 			};
+ 		};
+ 	};
+ };
++
++&vopb {
++	status = "okay";
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&vopl {
++	status = "okay";
++};
++
++&vopl_mmu {
++	status = "okay";
++};
+-- 
+2.43.0
+
diff --git a/patch/kernel/archive/rockchip64-6.10/add-board-xiaobao-nas-dts.patch b/patch/kernel/archive/rockchip64-6.10/add-board-xiaobao-nas-dts.patch
new file mode 100644
index 000000000000..a82ffbdd2b5c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/add-board-xiaobao-nas-dts.patch
@@ -0,0 +1,779 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-xiaobao-nas.dts b/arch/arm64/boot/dts/rockchip/rk3399-xiaobao-nas.dts
+new file mode 100644
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3399-xiaobao-nas.dts
+@@ -0,0 +1,774 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/usb/pd.h>
++#include "rk3399.dtsi"
++#include "rk3399-opp.dtsi"
++
++/ {
++	model = "Codinge Xiaobao NAS";
++	compatible = "codinge,xiaobao-nas", "rockchip,rk3399";
++
++	aliases {
++		mmc0 = &sdmmc;
++		mmc1 = &sdhci;
++		mmc2 = &sdio0;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	clkin_gmac: external-gmac-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "clkin_gmac";
++		#clock-cells = <0>;
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk808 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;
++		reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
++	};
++
++	vcc_dc: vcc-dc {
++		compatible = "regulator-fixed";
++		regulator-name = "dc_12v";
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vcc_12v: vcc-12v {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_12v";
++		regulator-always-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc1v8_s3: vcc1v8-s3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc1v8_s3";
++		regulator-always-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_1v8>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	vcc5v0_host: vcc5v0-host-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_host_en>;
++		regulator-name = "vcc5v0_host";
++	};
++
++	vcc_sd: vcc-sd {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sd";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc_sd_h>;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	vcc5v0_typec: vcc5v0-typec {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_typec_en>;
++		regulator-name = "vcc5v0_typec";
++		regulator-always-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc_12v>;
++	};
++
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_pcie";
++		enable-active-high;
++		gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_pwr_en>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vcc_lan: vcc3v3-phy-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_lan";
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	adc-keys {
++		compatible = "adc-keys";
++		io-channels = <&saradc 1>;
++		io-channel-names = "buttons";
++		keyup-threshold-microvolt = <1800000>;
++		poll-interval = <100>;
++
++		recovery {
++			label = "Recovery";
++			linux,code = <0x168>;
++			press-threshold-microvolt = <18000>;
++		};
++	};
++
++	gpio-leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&leds_pins>;
++
++		led1: system-led1 {
++			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
++			label = "system_led1";
++			retain-state-suspended;
++			default-state = "on";
++		};
++
++		led2: system-led2 {
++			gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
++			label = "system_led2";
++			retain-state-suspended;
++			default-state = "off";
++		};
++	};
++
++	pwm-fan {
++		compatible = "pwm-fan";
++		pwms = <&pwm1 0 50000 0>;
++	};
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l1 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l2 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l3 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_b1 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&emmc_phy {
++	status = "okay";
++};
++
++&gmac {
++	assigned-clocks = <&cru SCLK_RMII_SRC>;
++	assigned-clock-parents = <&clkin_gmac>;
++	clock_in_out = "input";
++	phy-supply = <&vcc_lan>;
++	phy-mode = "rgmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 50000>;
++	tx_delay = <0x28>;
++	rx_delay = <0x11>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&hdmi {
++	ddc-i2c-bus = <&i2c3>;
++	ddc-i2c-scl-high-time-ns = <9625>;
++	ddc-i2c-scl-low-time-ns = <10000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&hdmi_cec>;
++	status = "okay";
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	i2c-scl-rising-time-ns = <168>;
++	i2c-scl-falling-time-ns = <4>;
++	status = "okay";
++
++	rk808: pmic@1b {
++		compatible = "rockchip,rk808";
++		reg = <0x1b>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk808-clkout2";
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++		vcc10-supply = <&vcc3v3_sys>;
++		vcc11-supply = <&vcc3v3_sys>;
++		vcc12-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc_3v0>;
++
++		regulators {
++			vdd_center: DCDC_REG1 {
++				regulator-name = "vdd_center";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_l: DCDC_REG2 {
++				regulator-name = "vdd_cpu_l";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG4 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc1v8_dvp: LDO_REG1 {
++				regulator-name = "vcc1v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca_1v8: LDO_REG2 {
++				regulator-name = "vcca_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc1v8_pmupll: LDO_REG3 {
++				regulator-name = "vcc1v8_pmupll";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_sdio: LDO_REG4 {
++				regulator-name = "vcc_sdio";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3000000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcca3v0_codec: LDO_REG5 {
++				regulator-name = "vcca3v0_codec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc_1v5: LDO_REG6 {
++				regulator-name = "vcc_1v5";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <1500000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1500000>;
++				};
++			};
++
++			vcca1v8_codec: LDO_REG7 {
++				regulator-name = "vcca1v8_codec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_3v0: LDO_REG8 {
++				regulator-name = "vcc_3v0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc3v3_s3: SWITCH_REG1 {
++				regulator-name = "vcc3v3_s3";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_s0: SWITCH_REG2 {
++				regulator-name = "vcc3v3_s0";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++
++	vdd_cpu_b: regulator@40 {
++		compatible = "silergy,syr827";
++		reg = <0x40>;
++		fcs,suspend-voltage-selector = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vsel1_pin>;
++		regulator-name = "vdd_cpu_b";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_gpu: regulator@41 {
++		compatible = "silergy,syr828";
++		reg = <0x41>;
++		fcs,suspend-voltage-selector = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vsel2_pin>;
++		regulator-name = "vdd_gpu";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	hym8563@51 {
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++		clock-output-names = "xin32k";
++	};
++};
++
++&i2c3 {
++	i2c-scl-rising-time-ns = <450>;
++	i2c-scl-falling-time-ns = <15>;
++	status = "okay";
++};
++
++&i2c4 {
++	clock-frequency = <400000>;
++	i2c-scl-rising-time-ns = <160>;
++	i2c-scl-falling-time-ns = <30>;
++	status = "okay";
++
++	typec-portc@22 {
++		compatible = "fcs,fusb302";
++		reg = <0x22>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fusb0_int>;
++		vbus-supply = <&vcc5v0_typec>;
++	};
++};
++
++&i2s0 {
++	rockchip,capture-channels = <8>;
++	rockchip,playback-channels = <8>;
++	status = "okay";
++};
++
++&i2s1 {
++	rockchip,capture-channels = <2>;
++	rockchip,playback-channels = <2>;
++	status = "okay";
++};
++
++&i2s2 {
++	status = "okay";
++};
++
++&io_domains {
++	status = "okay";
++
++	bt656-supply = <&vcc_3v0>;
++	audio-supply = <&vcca1v8_codec>;
++	sdmmc-supply = <&vcc_sdio>;
++	gpio1830-supply = <&vcc_3v0>;
++};
++
++&pcie_phy {
++	status = "okay";
++	drive-impedance-ohm = <50>;
++};
++
++&pcie0 {
++	ep-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
++	num-lanes = <4>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_clkreqnb_cpm &fn8274_en_h>;
++	status = "okay";
++};
++
++&pmu_io_domains {
++	status = "okay";
++
++	pmu1830-supply = <&vcc_3v0>;
++};
++
++&pinctrl {
++	pcie {
++		fn8274_en_h: fn8274-en-h {
++			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>,
++					<4 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>,
++					<1 RK_PC7 RK_FUNC_GPIO &pcfg_output_high>;
++		};
++
++		pcie_pwr_en: pcie-pwr-en {
++			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		vsel1_pin: vsel1-pin {
++			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		vsel2_pin: vsel2-pin {
++			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	usb2 {
++		vcc5v0_host_en: vcc5v0-host-en {
++			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc5v0_typec_en: vcc5v0-typec-en {
++			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
++		};
++	};
++
++	vcc_sd {
++		vcc_sd_h: vcc-sd-h {
++			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	fusb30x {
++		fusb0_int: fusb0-int {
++			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	leds {
++		leds_pins: leds-pins {
++			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++&pwm1 {
++	status = "okay";
++};
++
++&saradc {
++	status = "okay";
++};
++
++&sdio0 {
++	bus-width = <4>;
++	clock-frequency = <50000000>;
++	cap-sdio-irq;
++	cap-sd-highspeed;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	num-slots = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
++	sd-uhs-sdr104;
++	status = "okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
++	disable-wp;
++	max-frequency = <150000000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
++	vmmc-supply = <&vcc_sd>;
++	vqmmc-supply = <&vcc_sdio>;
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	non-removable;
++	status = "okay";
++};
++
++&spi1 {
++	status = "okay";
++
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0x00>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&tcphy0 {
++	status = "okay";
++};
++
++&tcphy1 {
++	status = "okay";
++};
++
++&tsadc {
++	status = "okay";
++
++	/* tshut mode 0:CRU 1:GPIO */
++	rockchip,hw-tshut-mode = <1>;
++	/* tshut polarity 0:LOW 1:HIGH */
++	rockchip,hw-tshut-polarity = <1>;
++};
++
++&u2phy0 {
++	status = "okay";
++};
++
++&u2phy0_otg {
++	status = "okay";
++};
++
++&u2phy0_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&u2phy1 {
++	status = "okay";
++};
++
++&u2phy1_otg {
++	status = "okay";
++};
++
++&u2phy1_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usbdrd3_0 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_0 {
++	status = "okay";
++	dr_mode = "host";
++};
++
++&usbdrd3_1 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_1 {
++	status = "okay";
++	dr_mode = "host";
++};
++
++&vopb {
++	status = "okay";
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&vopl {
++	status = "okay";
++};
++
++&vopl_mmu {
++	status = "okay";
++};
diff --git a/patch/kernel/archive/rockchip64-6.10/board-firefly-rk3399-dts.patch b/patch/kernel/archive/rockchip64-6.10/board-firefly-rk3399-dts.patch
new file mode 100644
index 000000000000..f212d69355a7
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-firefly-rk3399-dts.patch
@@ -0,0 +1,282 @@
+index c654b6b02f3..f73f792eb44 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+@@ -217,7 +216,7 @@
+ 		enable-active-high;
+ 		gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&vcc5v0_host_en>;
++		pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
+ 		regulator-name = "vcc5v0_host";
+ 		regulator-always-on;
+ 		vin-supply = <&vcc_sys>;
+@@ -236,8 +235,11 @@
+ 
+ 	vcc_sys: vcc-sys {
+ 		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc_sys_en>;
+ 		regulator-name = "vcc_sys";
+-		regulator-always-on;
+ 		regulator-boot-on;
+ 		regulator-min-microvolt = <5000000>;
+ 		regulator-max-microvolt = <5000000>;
+@@ -254,6 +256,27 @@
+ 		regulator-min-microvolt = <430000>;
+ 		regulator-max-microvolt = <1400000>;
+ 	};
++
++	vcca_0v9: vcca-0v9 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcca_0v9";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++	
++	vcc3v3_3g: vcc3v3-3g-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_3g_drv>;
++		regulator-name = "vcc3v3_3g";
++		regulator-always-on;
++		regulator-boot-on;
++	};
+ };
+ 
+ &cpu_l0 {
+@@ -306,6 +329,8 @@
+ };
+ 
+ &hdmi {
++	avdd-0v9-supply = <&vcca0v9_hdmi>;
++	avdd-1v8-supply = <&vcca1v8_hdmi>;
+ 	ddc-i2c-bus = <&i2c3>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&hdmi_cec>;
+@@ -330,18 +355,18 @@
+ 		rockchip,system-power-controller;
+ 		wakeup-source;
+ 
+-		vcc1-supply = <&vcc_sys>;
+-		vcc2-supply = <&vcc_sys>;
+-		vcc3-supply = <&vcc_sys>;
+-		vcc4-supply = <&vcc_sys>;
+-		vcc6-supply = <&vcc_sys>;
+-		vcc7-supply = <&vcc_sys>;
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
+ 		vcc8-supply = <&vcc3v3_sys>;
+-		vcc9-supply = <&vcc_sys>;
+-		vcc10-supply = <&vcc_sys>;
+-		vcc11-supply = <&vcc_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++		vcc10-supply = <&vcc3v3_sys>;
++		vcc11-supply = <&vcc3v3_sys>;
+ 		vcc12-supply = <&vcc3v3_sys>;
+-		vddio-supply = <&vcc1v8_pmu>;
++		vddio-supply = <&vcc_3v0>;
+ 
+ 		regulators {
+ 			vdd_center: DCDC_REG1 {
+@@ -389,8 +414,8 @@
+ 				};
+ 			};
+ 
+-			vcc1v8_dvp: LDO_REG1 {
+-				regulator-name = "vcc1v8_dvp";
++			vcca1v8_codec: LDO_REG1 {
++				regulator-name = "vcca1v8_codec";
+ 				regulator-always-on;
+ 				regulator-boot-on;
+ 				regulator-min-microvolt = <1800000>;
+@@ -400,12 +425,12 @@
+ 				};
+ 			};
+ 
+-			vcc2v8_dvp: LDO_REG2 {
+-				regulator-name = "vcc2v8_dvp";
++			vcca1v8_hdmi: LDO_REG2 {
++				regulator-name = "vcca1v8_hdmi";
+ 				regulator-always-on;
+ 				regulator-boot-on;
+-				regulator-min-microvolt = <2800000>;
+-				regulator-max-microvolt = <2800000>;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
+ 				regulator-state-mem {
+ 					regulator-off-in-suspend;
+ 				};
+@@ -458,12 +483,12 @@
+ 				};
+ 			};
+ 
+-			vcca1v8_codec: LDO_REG7 {
+-				regulator-name = "vcca1v8_codec";
++			vcca0v9_hdmi: LDO_REG7 {
++				regulator-name = "vcca0v9_hdmi";
+ 				regulator-always-on;
+ 				regulator-boot-on;
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
+ 				regulator-state-mem {
+ 					regulator-off-in-suspend;
+ 				};
+@@ -504,14 +529,16 @@
+ 	vdd_cpu_b: regulator@40 {
+ 		compatible = "silergy,syr827";
+ 		reg = <0x40>;
+-		fcs,suspend-voltage-selector = <0>;
++		fcs,suspend-voltage-selector = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vsel1_pin>;
+ 		regulator-name = "vdd_cpu_b";
+ 		regulator-min-microvolt = <712500>;
+ 		regulator-max-microvolt = <1500000>;
+ 		regulator-ramp-delay = <1000>;
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		vin-supply = <&vcc_sys>;
++		vin-supply = <&vcc3v3_sys>;
+ 
+ 		regulator-state-mem {
+ 			regulator-off-in-suspend;
+@@ -522,13 +549,15 @@
+ 		compatible = "silergy,syr828";
+ 		reg = <0x41>;
+ 		fcs,suspend-voltage-selector = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vsel2_pin>;
+ 		regulator-name = "vdd_gpu";
+ 		regulator-min-microvolt = <712500>;
+ 		regulator-max-microvolt = <1500000>;
+ 		regulator-ramp-delay = <1000>;
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		vin-supply = <&vcc_sys>;
++		vin-supply = <&vcc3v3_sys>;
+ 
+ 		regulator-state-mem {
+ 			regulator-off-in-suspend;
+@@ -565,7 +594,7 @@
+ 	status = "okay";
+ 
+ 	fusb0: typec-portc@22 {
+-		compatible = "fcs,fusb302";
++		compatible = "fairchild,fusb302";
+ 		reg = <0x22>;
+ 		interrupt-parent = <&gpio1>;
+ 		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+@@ -638,7 +667,7 @@
+ &io_domains {
+ 	status = "okay";
+ 
+-	bt656-supply = <&vcc1v8_dvp>;
++	bt656-supply = <&vcc_3v0>;
+ 	audio-supply = <&vcca1v8_codec>;
+ 	sdmmc-supply = <&vcc_sdio>;
+ 	gpio1830-supply = <&vcc_3v0>;
+@@ -652,7 +681,10 @@
+ 	ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ 	num-lanes = <4>;
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&pcie_clkreqn_cpm>;
++	pinctrl-0 = <&pcie_perst>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	vpcie1v8-supply = <&vcc1v8_pmu>;
++	vpcie0v9-supply = <&vcca_0v9>;
+ 	status = "okay";
+ };
+ 
+@@ -704,6 +736,10 @@
+ 		pcie_3g_drv: pcie-3g-drv {
+ 			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
++
++		pcie_perst: pcie-perst {
++			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
+ 	};
+ 
+ 	pmic {
+@@ -742,6 +778,14 @@
+ 		vcc5v0_host_en: vcc5v0-host-en {
+ 			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++
++		vcc_sys_en: vcc-sys-en {
++			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		hub_rst: hub-rst {
++			rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>;
++		};
+ 	};
+ 
+ 	wifi {
+@@ -749,6 +793,20 @@
+ 			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
++
++	bt {
++		bt_host_wake_l: bt-host-wake-l {
++			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_reg_on_h: bt-reg-on-h {
++			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_wake_l: bt-wake-l {
++			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
+ };
+ 
+ &pwm0 {
+@@ -788,7 +846,7 @@
+ 		reg = <1>;
+ 		compatible = "brcm,bcm4329-fmac";
+ 		interrupt-parent = <&gpio0>;
+-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
++		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ 		interrupt-names = "host-wake";
+ 		brcm,drive-strength = <5>;
+ 		pinctrl-names = "default";
+@@ -885,8 +943,22 @@
+ 
+ &uart0 {
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&uart0_xfer &uart0_cts>;
++	pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+ 	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm43438-bt";
++		clocks = <&rk808 1>;
++		clock-names = "lpo";
++		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
++		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
++		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
++		max-speed = <4000000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
++		vbat-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc_1v8>;
++	};
+ };
+ 
+ &uart2 {
diff --git a/patch/kernel/archive/rockchip64-6.10/board-helios64-dts-fix-stability-issues.patch b/patch/kernel/archive/rockchip64-6.10/board-helios64-dts-fix-stability-issues.patch
new file mode 100644
index 000000000000..1b427c141177
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-helios64-dts-fix-stability-issues.patch
@@ -0,0 +1,72 @@
+From 4244bd791ab2fe68abebc1b6bf71ffbc02535828 Mon Sep 17 00:00:00 2001
+From: Aditya Prayoga <aprayoga@users.noreply.github.com>
+Date: Thu, 4 Mar 2021 10:39:40 +0700
+Subject: [PATCH] Attempt to improve stability on Helios64 (#2680)
+
+> X-Git-Archeology: > recovered message: > * Adjust the RK808 buck step to improve stability
+> X-Git-Archeology: > recovered message: > * Adjust vdd_log and enable vdd_center init voltage
+> X-Git-Archeology: > recovered message: > For some reason, regulator-init-microvolt property under PMIC does not applied. Set the voltage on board file.
+> X-Git-Archeology: - Revision eefad69215557708b151a5d9244617a4ffd1281c: https://github.com/armbian/build/commit/eefad69215557708b151a5d9244617a4ffd1281c
+> X-Git-Archeology:   Date: Thu, 04 Mar 2021 10:39:40 +0700
+> X-Git-Archeology:   From: Aditya Prayoga <aprayoga@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Attempt to improve stability on Helios64 (#2680)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+index 09e2cfe40696..4cb72981809a 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+@@ -522,6 +522,7 @@ rk808: pmic@1b {
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pmic_int_l>;
+ 		rockchip,system-power-controller;
++		max-buck-steps-per-change = <4>;
+ 
+ 		vcc1-supply = <&vcc5v0_sys>;
+ 		vcc2-supply = <&vcc5v0_sys>;
+-- 
+2.43.0
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-helios64-remove-pcie-ep-gpios.patch b/patch/kernel/archive/rockchip64-6.10/board-helios64-remove-pcie-ep-gpios.patch
new file mode 100644
index 000000000000..ff7ca38b5346
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-helios64-remove-pcie-ep-gpios.patch
@@ -0,0 +1,25 @@
+From 9fd42a26755ee7303a033c9c1fba3a492e0044f5 Mon Sep 17 00:00:00 2001
+From: Aditya Prayoga <aditya@kobol.io>
+Date: Tue, 15 Sep 2020 13:42:02 +0700
+Subject: [PATCH] Remove PCIE ep-gpios from Helios64
+
+Signed-off-by: Aditya Prayoga <aditya@kobol.io>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+index 4cb72981809a..824e7a4d8e40 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+@@ -820,7 +820,6 @@ &pcie_phy {
+ };
+ 
+ &pcie0 {
+-	ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
+ 	max-link-speed = <2>;
+ 	num-lanes = <2>;
+ 	pinctrl-names = "default";
+-- 
+2.43.0
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-nanopc-t4-add-typec-dp.patch b/patch/kernel/archive/rockchip64-6.10/board-nanopc-t4-add-typec-dp.patch
new file mode 100644
index 000000000000..b6a2dc3d616b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-nanopc-t4-add-typec-dp.patch
@@ -0,0 +1,147 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: tonymac32 <tonymckahan@gmail.com>
+Date: Wed, 17 Feb 2021 00:54:00 -0500
+Subject: Patching something
+
+Signed-off-by: tonymac32 <tonymckahan@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts | 96 ++++++++++
+ 1 file changed, 96 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
+index 3bf8f959e42c..2b1220beabd5 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
+@@ -9,6 +9,7 @@
+  */
+ 
+ /dts-v1/;
++#include <dt-bindings/usb/pd.h>
+ #include "rk3399-nanopi4.dtsi"
+ 
+ / {
+@@ -66,6 +67,12 @@ fan: pwm-fan {
+ 	};
+ };
+ 
++&cdn_dp {
++	status = "okay";
++	extcon = <&fusb0>;
++	phys = <&tcphy0_dp>;
++};
++
+ &cpu_thermal {
+ 	trips {
+ 		cpu_warm: cpu_warm {
+@@ -94,6 +101,50 @@ map3 {
+ 	};
+ };
+ 
++&fusb0 {
++
++	connector {
++		compatible = "usb-c-connector";
++		label = "USB-C";
++		power-role = "dual";
++		data-role = "dual";
++		try-power-role = "sink";
++		source-pdos = <PDO_FIXED(5000, 1200, PDO_FIXED_USB_COMM)>;
++		sink-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)>;
++		op-sink-microwatt = <5000000>;
++		
++		extcon-cables = <1 2 5 6 9 10 12 44>;
++		typec-altmodes = <0xff01 1 0x001c0000 1>;
++		
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			port@0 {
++				reg = <0>;
++				usb_con_hs: endpoint {
++					remote-endpoint = 
++						<&u2phy0_typec_hs>;
++				};
++			};
++			port@1 {
++				reg = <1>;
++
++				usb_con_ss: endpoint {
++					remote-endpoint = 
++						<&tcphy0_typec_ss>;
++				};
++			};
++			port@2 {
++				reg = <2>;
++				usb_con_dp: endpoint {
++					remote-endpoint = 
++						<&tcphy0_typec_dp>;
++				};
++			};
++		};
++	};		
++};
++
+ &pcie0 {
+ 	ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+ 	num-lanes = <4>;
+@@ -114,12 +165,57 @@ &sdhci {
+ 	mmc-hs400-enhanced-strobe;
+ };
+ 
++&tcphy0 {
++	extcon = <&fusb0>;
++	status = "okay";
++};
++
++&tcphy0_dp {
++	port {
++		tcphy0_typec_dp: endpoint {
++			remote-endpoint = <&usb_con_dp>;
++		};
++	};
++};
++
++&tcphy0_usb3 {
++	port {
++		tcphy0_typec_ss: endpoint {
++			remote-endpoint = <&usb_con_ss>;
++		};
++	};
++};
++
++&u2phy0 {
++	extcon = <&fusb0>;
++};
++
+ &u2phy0_host {
+ 	phy-supply = <&vcc5v0_host0>;
++	status = "okay";
++};
++
++&u2phy0_otg {
++	status = "okay";
++
++	port {
++		u2phy0_typec_hs: endpoint {
++			remote-endpoint = <&usb_con_hs>;
++		};
++	};
+ };
+ 
+ &u2phy1_host {
+ 	phy-supply = <&vcc5v0_host0>;
++	status = "okay";
++};
++
++&u2phy1_otg {
++	status = "okay";
++};
++
++&usbdrd_dwc3_0 {
++	extcon = <&fusb0>;
+ };
+ 
+ &vcc5v0_sys {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-nanopi-m4v2-dts-add-sound-card.patch b/patch/kernel/archive/rockchip64-6.10/board-nanopi-m4v2-dts-add-sound-card.patch
new file mode 100644
index 000000000000..8c03adf2bfa8
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-nanopi-m4v2-dts-add-sound-card.patch
@@ -0,0 +1,190 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Piotr Szczepanik <piter75@gmail.com>
+Date: Thu, 28 Nov 2019 22:29:54 +0000
+Subject: [ARCHEOLOGY] Initial addition of NanoPi M4V2
+
+> X-Git-Archeology: - Revision c4eecbcef0d4dc499baf0155449e71dc774bc7c4: https://github.com/armbian/build/commit/c4eecbcef0d4dc499baf0155449e71dc774bc7c4
+> X-Git-Archeology:   Date: Thu, 28 Nov 2019 22:29:54 +0000
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Initial addition of NanoPi M4V2
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 40a3d4ecb9a75c17183e2129491b7bc03060a315: https://github.com/armbian/build/commit/40a3d4ecb9a75c17183e2129491b7bc03060a315
+> X-Git-Archeology:   Date: Sun, 17 May 2020 18:42:24 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Fixed rt5651 codec probing after its driver was changed to module (#1969)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 401fb1fde426c93121c4639b34a450d8ff551c85: https://github.com/armbian/build/commit/401fb1fde426c93121c4639b34a450d8ff551c85
+> X-Git-Archeology:   Date: Sat, 20 Nov 2021 19:49:22 +0100
+> X-Git-Archeology:   From: simple <991605149@qq.com>
+> X-Git-Archeology:   Subject: Fixed rt5651 codec build module (#3270)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 51 ++++++++++
+ sound/soc/rockchip/Kconfig                       |  9 ++
+ 2 files changed, 60 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+index 7c5f441a2219..3e899f584871 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+@@ -132,6 +132,27 @@ status_led: led-0 {
+ 		};
+ 	};
+ 
++	rt5651-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "realtek,rt5651-codec";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,widgets =
++			"Microphone", "Mic Jack",
++			"Headphone", "Headphone Jack";
++		simple-audio-card,routing =
++			"Mic Jack", "micbias1",
++			"IN1P", "Mic Jack",
++			"Headphone Jack", "HPOL",
++			"Headphone Jack", "HPOR";
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&rt5651>;
++		};
++	};
++
+ 	sdio_pwrseq: sdio-pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		clocks = <&rk808 1>;
+@@ -216,6 +237,10 @@ &hdmi_sound {
+ 	status = "okay";
+ };
+ 
++&hdmi_sound {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	clock-frequency = <400000>;
+ 	i2c-scl-rising-time-ns = <160>;
+@@ -463,6 +488,16 @@ &i2c1 {
+ 	i2c-scl-rising-time-ns = <150>;
+ 	i2c-scl-falling-time-ns = <30>;
+ 	status = "okay";
++
++	rt5651: rt5651@1a {
++		compatible = "realtek,rt5651";
++		reg = <0x1a>;
++		clocks = <&cru SCLK_I2S_8CH_OUT>;
++		clock-names = "mclk";
++		hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
++		// spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
++		#sound-dai-cells = <0>;
++	};
+ };
+ 
+ &i2c2 {
+@@ -494,6 +529,16 @@ &i2s2 {
+ 	status = "okay";
+ };
+ 
++&i2s1 {
++	rockchip,playback-channels = <8>;
++	rockchip,capture-channels = <8>;
++	status = "okay";
++};
++
++&i2s2 {
++	status = "okay";
++};
++
+ &io_domains {
+ 	bt656-supply = <&vcc_1v8>;
+ 	audio-supply = <&vcca1v8_codec>;
+@@ -759,3 +804,9 @@ &vopl {
+ &vopl_mmu {
+ 	status = "okay";
+ };
++
++&spdif {
++	i2c-scl-rising-time-ns = <450>;
++	i2c-scl-falling-time-ns = <15>;
++	status = "okay";
++};
+diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
+index f98a2fa85edd..be36e36c8783 100644
+--- a/sound/soc/rockchip/Kconfig
++++ b/sound/soc/rockchip/Kconfig
+@@ -65,6 +65,15 @@ config SND_SOC_ROCKCHIP_RT5645
+ 	  Say Y or M here if you want to add support for SoC audio on Rockchip
+ 	  boards using the RT5645/RT5650 codec, such as Veyron.
+ 
++config SND_SOC_ROCKCHIP_RT5651
++	tristate "ASoC support for Rockchip boards using a RT5651 codec"
++	depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK
++	select SND_SOC_ROCKCHIP_I2S
++	select SND_SOC_RT5651
++	help
++	  Say Y or M here if you want to add support for SoC audio on Rockchip
++	  boards using the RT5651 codec, such as FriendlyARM's Nano{Pi,PC} family.
++
+ config SND_SOC_RK3288_HDMI_ANALOG
+ 	tristate "ASoC support multiple codecs for Rockchip RK3288 boards"
+ 	depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-nanopi-r2c-plus.patch b/patch/kernel/archive/rockchip64-6.10/board-nanopi-r2c-plus.patch
new file mode 100644
index 000000000000..72fe01212211
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-nanopi-r2c-plus.patch
@@ -0,0 +1,30 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: amazingfate <liujianfeng1994@gmail.com>
+Date: Thu, 31 Aug 2023 11:41:37 +0200
+Subject: [ARCHEOLOGY] rockchip64: bump rockchip64-edge kernel to 6.5
+
+> X-Git-Archeology: - Revision 8254411054a99f9750770bb6055facfbdedacbba: https://github.com/armbian/build/commit/8254411054a99f9750770bb6055facfbdedacbba
+> X-Git-Archeology:   Date: Thu, 31 Aug 2023 11:41:37 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64: bump rockchip64-edge kernel to 6.5
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
+index 16a1958e4572..45954295d51d 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
+@@ -27,7 +27,7 @@ &emmc {
+ 	non-removable;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+-	vmmc-supply = <&vcc_io_33>;
++	vmmc-supply = <&vcc_io>;
+ 	vqmmc-supply = <&vcc18_emmc>;
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-nanopi-r2s.patch b/patch/kernel/archive/rockchip64-6.10/board-nanopi-r2s.patch
new file mode 100644
index 000000000000..c707061370f8
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-nanopi-r2s.patch
@@ -0,0 +1,735 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 7 Jan 2023 11:59:47 +0000
+Subject: rockchip64: consolidate nanopi r2s device trees
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 493 ++++++----
+ 1 file changed, 328 insertions(+), 165 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+index 1445b879ac7a..7ebf21d7faac 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -1,119 +1,167 @@
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+- * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
++ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+  */
+ 
+ /dts-v1/;
+-
+-#include <dt-bindings/input/input.h>
+-#include <dt-bindings/gpio/gpio.h>
++#include "rk3328-dram-default-timing.dtsi"
+ #include "rk3328.dtsi"
+ 
+ / {
+-	model = "FriendlyElec NanoPi R2S";
+-	compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
++	model = "FriendlyElec boards based on Rockchip RK3328";
++	compatible = "friendlyelec,nanopi-r2",
++		   "rockchip,rk3328";
+ 
+ 	aliases {
+-		ethernet0 = &gmac2io;
+-		ethernet1 = &rtl8153;
+-		mmc0 = &sdmmc;
++		ethernet0 = &gmac2io;
++		ethernet1 = &r8153;
+ 	};
+ 
+ 	chosen {
++		bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0";
+ 		stdout-path = "serial2:1500000n8";
+ 	};
+ 
+-	gmac_clk: gmac-clock {
++	gmac_clkin: external-gmac-clock {
+ 		compatible = "fixed-clock";
+ 		clock-frequency = <125000000>;
+ 		clock-output-names = "gmac_clkin";
+ 		#clock-cells = <0>;
+ 	};
+ 
+-	keys {
+-		compatible = "gpio-keys";
+-		pinctrl-0 = <&reset_button_pin>;
+-		pinctrl-names = "default";
+-
+-		key-reset {
+-			label = "reset";
+-			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+-			linux,code = <KEY_RESTART>;
+-			debounce-interval = <50>;
+-		};
++	mach: board {
++		compatible = "friendlyelec,board";
++		machine = "NANOPI-R2";
++		hwrev = <255>;
++		model = "NanoPi R2 Series";
++		nvmem-cells = <&efuse_id>, <&efuse_cpu_version>;
++		nvmem-cell-names = "id", "cpu-version";
+ 	};
+ 
+-	leds {
++	leds: gpio-leds {
+ 		compatible = "gpio-leds";
+-		pinctrl-0 = <&lan_led_pin>,  <&sys_led_pin>, <&wan_led_pin>;
+ 		pinctrl-names = "default";
++		pinctrl-0 =<&leds_gpio>;
++		status = "disabled";
+ 
+-		lan_led: led-0 {
+-			gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+-			label = "nanopi-r2s:green:lan";
+-		};
+-
+-		sys_led: led-1 {
++		led@1 {
+ 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+-			label = "nanopi-r2s:red:sys";
+-			default-state = "on";
+-		};
+-
+-		wan_led: led-2 {
+-			gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+-			label = "nanopi-r2s:green:wan";
++			label = "status_led";
++			linux,default-trigger = "heartbeat";
++			linux,default-trigger-delay-ms = <0>;
+ 		};
+ 	};
+ 
+-	vcc_io_sdio: sdmmcio-regulator {
+-		compatible = "regulator-gpio";
+-		enable-active-high;
+-		gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+-		pinctrl-0 = <&sdio_vcc_pin>;
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk805 1>;
++		clock-names = "ext_clock";
+ 		pinctrl-names = "default";
+-		regulator-name = "vcc_io_sdio";
+-		regulator-always-on;
+-		regulator-min-microvolt = <1800000>;
+-		regulator-max-microvolt = <3300000>;
+-		regulator-settling-time-us = <5000>;
+-		regulator-type = "voltage";
+-		startup-delay-us = <2000>;
+-		states = <1800000 0x1>,
+-			 <3300000 0x0>;
+-		vin-supply = <&vcc_io_33>;
++		pinctrl-0 = <&wifi_enable_h>;
++
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
++		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
++	};
++
++	sdmmc_ext: dwmmc@ff5f0000 {
++		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
++		reg = <0x0 0xff5f0000 0x0 0x4000>;
++		clock-freq-min-max = <400000 150000000>;
++		clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
++			 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
++		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
++		fifo-depth = <0x100>;
++		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++		status = "disabled";
+ 	};
+ 
+ 	vcc_sd: sdmmc-regulator {
+ 		compatible = "regulator-fixed";
+-		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+-		pinctrl-0 = <&sdmmc0m1_pin>;
++		gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ 		pinctrl-names = "default";
+-		regulator-name = "vcc_sd";
++		pinctrl-0 = <&sdmmc0m1_pin>;
+ 		regulator-boot-on;
++		regulator-name = "vcc_sd";
+ 		regulator-min-microvolt = <3300000>;
+ 		regulator-max-microvolt = <3300000>;
+-		vin-supply = <&vcc_io_33>;
++		vin-supply = <&vcc_io>;
++	};
++
++	vccio_sd: sdmmcio-regulator {
++		compatible = "regulator-gpio";
++		gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
++		states = <1800000 0x1
++			  3300000 0x0>;
++		regulator-name = "vccio_sd";
++		regulator-type = "voltage";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&vcc_io>;
++		startup-delay-us = <2000>;
++		regulator-settling-time-us = <5000>;
++		enable-active-high;
++		status = "disabled";
+ 	};
+ 
+-	vdd_5v: vdd-5v {
++	vcc_sys: vcc-sys {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vdd_5v";
++		regulator-name = "vcc_sys";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+ 		regulator-min-microvolt = <5000000>;
+ 		regulator-max-microvolt = <5000000>;
+ 	};
+ 
+-	vdd_5v_lan: vdd-5v-lan {
++	vcc_phy: vcc-phy-regulator {
+ 		compatible = "regulator-fixed";
+-		enable-active-high;
+-		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+-		pinctrl-0 = <&lan_vdd_pin>;
+-		pinctrl-names = "default";
+-		regulator-name = "vdd_5v_lan";
++		regulator-name = "vcc_phy";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		vin-supply = <&vdd_5v>;
++	};
++
++	vcc_host_vbus: host-vbus-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_host_vbus";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	/delete-node/ dmc-opp-table;
++
++	dmc_opp_table: dmc_opp_table {
++		compatible = "operating-points-v2";
++
++		opp-786000000 {
++			opp-hz = /bits/ 64 <786000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++		};
++		opp-798000000 {
++			opp-hz = /bits/ 64 <798000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++		};
++		opp-840000000 {
++			opp-hz = /bits/ 64 <840000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++		};
++		opp-924000000 {
++			opp-hz = /bits/ 64 <924000000>;
++			opp-microvolt = <1100000 1100000 1200000>;
++		};
++		opp-1056000000 {
++			opp-hz = /bits/ 64 <1056000000>;
++			opp-microvolt = <1175000 1175000 1200000>;
++		};
+ 	};
+ };
+ 
+@@ -120,34 +168,57 @@ &cpu0 {
+ 	cpu-supply = <&vdd_arm>;
+ };
+ 
+-&cpu1 {
+-	cpu-supply = <&vdd_arm>;
++&dfi {
++	status = "okay";
+ };
+ 
+-&cpu2 {
+-	cpu-supply = <&vdd_arm>;
++&dmc {
++	center-supply = <&vdd_logic>;
++	ddr_timing = <&ddr_timing>;
++	status = "okay";
+ };
+ 
+-&cpu3 {
+-	cpu-supply = <&vdd_arm>;
++&emmc {
++	bus-width = <8>;
++	cap-mmc-highspeed;
++	max-frequency = <150000000>;
++	mmc-hs200-1_8v;
++	no-sd;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
++	vmmc-supply = <&vcc_io>;
++	vqmmc-supply = <&vcc18_emmc>;
++	status = "okay";
+ };
+ 
+-&display_subsystem {
++&gmac2phy {
++	phy-supply = <&vcc_phy>;
++	clock_in_out = "output";
++	assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
++	assigned-clock-rate = <50000000>;
++	assigned-clocks = <&cru SCLK_MAC2PHY>;
++	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ 	status = "disabled";
+ };
+ 
+ &gmac2io {
+ 	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+-	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
++	assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ 	clock_in_out = "input";
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmiim1_pins>;
+ 	phy-handle = <&rtl8211e>;
+ 	phy-mode = "rgmii";
+-	phy-supply = <&vcc_io_33>;
+-	pinctrl-0 = <&rgmiim1_pins>;
+-	pinctrl-names = "default";
+-	rx_delay = <0x18>;
++	phy-supply = <&vcc_phy>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 30000>;
++	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ 	snps,aal;
++	snps,rxpbl = <0x4>;
++	snps,txpbl = <0x4>;
+ 	tx_delay = <0x24>;
++	rx_delay = <0x18>;
+ 	status = "okay";
+ 
+ 	mdio {
+@@ -155,13 +226,11 @@ mdio {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
+-		rtl8211e: ethernet-phy@1 {
+-			reg = <1>;
+-			pinctrl-0 = <&eth_phy_reset_pin>;
+-			pinctrl-names = "default";
++		rtl8211e: phy@0 {
++			reg = <0>;
+ 			reset-assert-us = <10000>;
+-			reset-deassert-us = <50000>;
+-			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++			reset-deassert-us = <30000>;
++			/* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */
+ 		};
+ 	};
+ };
+@@ -169,36 +238,35 @@ rtl8211e: ethernet-phy@1 {
+ &i2c1 {
+ 	status = "okay";
+ 
+-	rk805: pmic@18 {
++	rk805: rk805@18 {
+ 		compatible = "rockchip,rk805";
+ 		reg = <0x18>;
+-		interrupt-parent = <&gpio1>;
+-		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-parent = <&gpio2>;
++		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ 		#clock-cells = <1>;
+ 		clock-output-names = "xin32k", "rk805-clkout2";
+ 		gpio-controller;
+ 		#gpio-cells = <2>;
+-		pinctrl-0 = <&pmic_int_l>;
+ 		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
+ 		rockchip,system-power-controller;
+ 		wakeup-source;
+ 
+-		vcc1-supply = <&vdd_5v>;
+-		vcc2-supply = <&vdd_5v>;
+-		vcc3-supply = <&vdd_5v>;
+-		vcc4-supply = <&vdd_5v>;
+-		vcc5-supply = <&vcc_io_33>;
+-		vcc6-supply = <&vdd_5v>;
++		vcc1-supply = <&vcc_sys>;
++		vcc2-supply = <&vcc_sys>;
++		vcc3-supply = <&vcc_sys>;
++		vcc4-supply = <&vcc_sys>;
++		vcc5-supply = <&vcc_io>;
++		vcc6-supply = <&vcc_io>;
+ 
+ 		regulators {
+-			vdd_log: DCDC_REG1 {
+-				regulator-name = "vdd_log";
+-				regulator-always-on;
+-				regulator-boot-on;
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-init-microvolt = <1075000>;
+ 				regulator-min-microvolt = <712500>;
+ 				regulator-max-microvolt = <1450000>;
+-				regulator-ramp-delay = <12500>;
+-
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-state-mem {
+ 					regulator-on-in-suspend;
+ 					regulator-suspend-microvolt = <1000000>;
+@@ -207,12 +275,11 @@ regulator-state-mem {
+ 
+ 			vdd_arm: DCDC_REG2 {
+ 				regulator-name = "vdd_arm";
+-				regulator-always-on;
+-				regulator-boot-on;
++				regulator-init-microvolt = <1225000>;
+ 				regulator-min-microvolt = <712500>;
+ 				regulator-max-microvolt = <1450000>;
+-				regulator-ramp-delay = <12500>;
+-
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-state-mem {
+ 					regulator-on-in-suspend;
+ 					regulator-suspend-microvolt = <950000>;
+@@ -223,19 +290,17 @@ vcc_ddr: DCDC_REG3 {
+ 				regulator-name = "vcc_ddr";
+ 				regulator-always-on;
+ 				regulator-boot-on;
+-
+ 				regulator-state-mem {
+ 					regulator-on-in-suspend;
+ 				};
+ 			};
+ 
+-			vcc_io_33: DCDC_REG4 {
+-				regulator-name = "vcc_io_33";
+-				regulator-always-on;
+-				regulator-boot-on;
++			vcc_io: DCDC_REG4 {
++				regulator-name = "vcc_io";
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+-
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-state-mem {
+ 					regulator-on-in-suspend;
+ 					regulator-suspend-microvolt = <3300000>;
+@@ -244,11 +309,10 @@ regulator-state-mem {
+ 
+ 			vcc_18: LDO_REG1 {
+ 				regulator-name = "vcc_18";
+-				regulator-always-on;
+-				regulator-boot-on;
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <1800000>;
+-
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-state-mem {
+ 					regulator-on-in-suspend;
+ 					regulator-suspend-microvolt = <1800000>;
+@@ -257,11 +321,10 @@ regulator-state-mem {
+ 
+ 			vcc18_emmc: LDO_REG2 {
+ 				regulator-name = "vcc18_emmc";
+-				regulator-always-on;
+-				regulator-boot-on;
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <1800000>;
+-
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-state-mem {
+ 					regulator-on-in-suspend;
+ 					regulator-suspend-microvolt = <1800000>;
+@@ -270,11 +333,10 @@ regulator-state-mem {
+ 
+ 			vdd_10: LDO_REG3 {
+ 				regulator-name = "vdd_10";
+-				regulator-always-on;
+-				regulator-boot-on;
+ 				regulator-min-microvolt = <1000000>;
+ 				regulator-max-microvolt = <1000000>;
+-
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-state-mem {
+ 					regulator-on-in-suspend;
+ 					regulator-suspend-microvolt = <1000000>;
+@@ -285,20 +347,21 @@ regulator-state-mem {
+ };
+ 
+ &io_domains {
+-	pmuio-supply = <&vcc_io_33>;
+-	vccio1-supply = <&vcc_io_33>;
+-	vccio2-supply = <&vcc18_emmc>;
+-	vccio3-supply = <&vcc_io_sdio>;
+-	vccio4-supply = <&vcc_18>;
+-	vccio5-supply = <&vcc_io_33>;
+-	vccio6-supply = <&vcc_io_33>;
+ 	status = "okay";
++
++	vccio1-supply = <&vcc_io>;
++	vccio2-supply = <&vcc18_emmc>;
++	vccio3-supply = <&vcc_io>;
++	vccio4-supply = <&vcc_io>;
++	vccio5-supply = <&vcc_io>;
++	vccio6-supply = <&vcc_18>;
++	pmuio-supply = <&vcc_io>;
+ };
+ 
+ &pinctrl {
+-	button {
+-		reset_button_pin: reset-button-pin {
+-			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
+ 
+@@ -308,61 +371,165 @@ eth_phy_reset_pin: eth-phy-reset-pin {
+ 		};
+ 	};
+ 
+-	leds {
+-		lan_led_pin: lan-led-pin {
+-			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++	};
+ 
+-		sys_led_pin: sys-led-pin {
+-			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++	sdmmc0 {
++		sdmmc0_clk: sdmmc0-clk {
++			rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
++		};
++
++		sdmmc0_cmd: sdmmc0-cmd {
++			rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
+ 		};
+ 
+-		wan_led_pin: wan-led-pin {
+-			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		sdmmc0_dectn: sdmmc0-dectn {
++			rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
++		};
++
++		sdmmc0_bus4: sdmmc0-bus4 {
++			rockchip,pins =
++				<1 RK_PA0 1 &pcfg_pull_up_4ma>,
++				<1 RK_PA1 1 &pcfg_pull_up_4ma>,
++				<1 RK_PA2 1 &pcfg_pull_up_4ma>,
++				<1 RK_PA3 1 &pcfg_pull_up_4ma>;
+ 		};
+ 	};
+ 
+-	lan {
+-		lan_vdd_pin: lan-vdd-pin {
+-			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++	sdmmc0ext {
++		sdmmc0ext_clk: sdmmc0ext-clk {
++			rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>;
++		};
++
++		sdmmc0ext_cmd: sdmmc0ext-cmd {
++			rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>;
++		};
++
++		sdmmc0ext_bus4: sdmmc0ext-bus4 {
++			rockchip,pins =
++				<3 RK_PA4 3 &pcfg_pull_up_2ma>,
++				<3 RK_PA5 3 &pcfg_pull_up_2ma>,
++				<3 RK_PA6 3 &pcfg_pull_up_2ma>,
++				<3 RK_PA7 3 &pcfg_pull_up_2ma>;
+ 		};
+ 	};
+ 
+-	pmic {
+-		pmic_int_l: pmic-int-l {
+-			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
++	gmac-1 {
++		rgmiim1_pins: rgmiim1-pins {
++			rockchip,pins =
++				/* mac_txclk */
++				<1 RK_PB4 2 &pcfg_pull_none_4ma>,
++				/* mac_rxclk */
++				<1 RK_PB5 2 &pcfg_pull_none>,
++				/* mac_mdio */
++				<1 RK_PC3 2 &pcfg_pull_none_2ma>,
++				/* mac_txen */
++				<1 RK_PD1 2 &pcfg_pull_none_4ma>,
++				/* mac_clk */
++				<1 RK_PC5 2 &pcfg_pull_none_2ma>,
++				/* mac_rxdv */
++				<1 RK_PC6 2 &pcfg_pull_none>,
++				/* mac_mdc */
++				<1 RK_PC7 2 &pcfg_pull_none_2ma>,
++				/* mac_rxd1 */
++				<1 RK_PB2 2 &pcfg_pull_none>,
++				/* mac_rxd0 */
++				<1 RK_PB3 2 &pcfg_pull_none>,
++				/* mac_txd1 */
++				<1 RK_PB0 2 &pcfg_pull_none_4ma>,
++				/* mac_txd0 */
++				<1 RK_PB1 2 &pcfg_pull_none_4ma>,
++				/* mac_rxd3 */
++				<1 RK_PB6 2 &pcfg_pull_none>,
++				/* mac_rxd2 */
++				<1 RK_PB7 2 &pcfg_pull_none>,
++				/* mac_txd3 */
++				<1 RK_PC0 2 &pcfg_pull_none_4ma>,
++				/* mac_txd2 */
++				<1 RK_PC1 2 &pcfg_pull_none_4ma>,
++
++				/* mac_txclk */
++				<0 RK_PB0 1 &pcfg_pull_none>,
++				/* mac_txen */
++				<0 RK_PB4 1 &pcfg_pull_none>,
++				/* mac_clk */
++				<0 RK_PD0 1 &pcfg_pull_none>,
++				/* mac_txd1 */
++				<0 RK_PC0 1 &pcfg_pull_none>,
++				/* mac_txd0 */
++				<0 RK_PC1 1 &pcfg_pull_none>,
++				/* mac_txd3 */
++				<0 RK_PC7 1 &pcfg_pull_none>,
++				/* mac_txd2 */
++				<0 RK_PC6 1 &pcfg_pull_none>;
+ 		};
+ 	};
+ 
+-	sd {
+-		sdio_vcc_pin: sdio-vcc-pin {
+-			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
++	usb {
++		host_vbus_drv: host-vbus-drv {
++			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		otg_vbus_drv: otg-vbus-drv {
++			rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
++
++	gpio-leds {
++		leds_gpio: leds-gpio {
++			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++	   };
++	};
+ };
+ 
+-&pwm2 {
++&sdmmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	max-frequency = <150000000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
++	vmmc-supply = <&vcc_sd>;
+ 	status = "okay";
+ };
+ 
+-&sdmmc {
++&sdmmc_ext {
+ 	bus-width = <4>;
+ 	cap-sd-highspeed;
++	cap-sdio-irq;
+ 	disable-wp;
+-	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
++	keep-power-in-suspend;
++	max-frequency = <100000000>;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	num-slots = <1>;
+ 	pinctrl-names = "default";
+-	sd-uhs-sdr12;
+-	sd-uhs-sdr25;
+-	sd-uhs-sdr50;
++	pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>;
++	rockchip,default-sample-phase = <120>;
++	supports-sdio;
+ 	sd-uhs-sdr104;
+-	vmmc-supply = <&vcc_sd>;
+-	vqmmc-supply = <&vcc_io_sdio>;
++	#address-cells = <1>;
++	#size-cells = <0>;
+ 	status = "okay";
++
++	brcmf: bcrmf@1 {
++		reg = <1>;
++		compatible = "brcm,bcm4329-fmac";
++		interrupt-parent = <&gpio1>;
++		interrupts = <RK_PD2 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "host-wake";
++	};
+ };
+ 
+ &tsadc {
+-	rockchip,hw-tshut-mode = <0>;
+-	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
++&uart2 {
+ 	status = "okay";
+ };
+ 
+@@ -378,13 +545,16 @@ &u2phy_otg {
+ 	status = "okay";
+ };
+ 
+-&uart2 {
++&usb20_otg {
+ 	status = "okay";
+ };
+ 
+-&usb20_otg {
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
+ 	status = "okay";
+-	dr_mode = "host";
+ };
+ 
+ &usbdrd3 {
+@@ -393,17 +563,10 @@ &usbdrd3 {
+ 	#address-cells = <1>;
+ 	#size-cells = <0>;
+ 
+-	/* Second port is for USB 3.0 */
+-	rtl8153: device@2 {
++	r8153: device@2 {
+ 		compatible = "usbbda,8153";
+ 		reg = <2>;
++		realtek,led-data = <0x87>;
++		local-mac-address = [00 00 00 00 00 00];
+ 	};
+ };
+-
+-&usb_host0_ehci {
+-	status = "okay";
+-};
+-
+-&usb_host0_ohci {
+-	status = "okay";
+-};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-nanopi-r4s-pwmfan.patch b/patch/kernel/archive/rockchip64-6.10/board-nanopi-r4s-pwmfan.patch
new file mode 100644
index 000000000000..2fb280e546cd
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-nanopi-r4s-pwmfan.patch
@@ -0,0 +1,58 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Bochun Bai <bbc@sinofool.net>
+Date: Sun, 18 Jun 2023 11:56:34 +0200
+Subject: Add pwm-fan support to nanopi r4s
+
+---
+ arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 35 ++++++++++
+ 1 file changed, 35 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+index fe5b52610010..10cc254fd1dc 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -62,6 +62,41 @@ vdd_5v: vdd-5v {
+ 		regulator-always-on;
+ 		regulator-boot-on;
+ 	};
++
++	fan: pwm-fan {
++		compatible = "pwm-fan";
++		cooling-levels = <0 18 102 170 255>;
++		fan-supply = <&vdd_5v>;
++		pwms = <&pwm1 0 50000 0>;
++	};
++};
++
++&cpu_thermal {
++	trips {
++		cpu_warm: cpu_warm {
++			temperature = <55000>;
++			hysteresis = <2000>;
++			type = "active";
++		};
++
++		cpu_hot: cpu_hot {
++			temperature = <65000>;
++			hysteresis = <2000>;
++			type = "active";
++		};
++	};
++
++	cooling-maps {
++		map2 {
++			trip = <&cpu_warm>;
++			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
++		};
++
++		map3 {
++			trip = <&cpu_hot>;
++			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
++		};
++	};
+ };
+ 
+ &emmc_phy {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-orangepi-r1-plus.patch b/patch/kernel/archive/rockchip64-6.10/board-orangepi-r1-plus.patch
new file mode 100644
index 000000000000..7cb0c747bf7b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-orangepi-r1-plus.patch
@@ -0,0 +1,216 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+Date: Sat, 20 Jun 2020 22:39:57 +0200
+Subject: [ARCHEOLOGY] Initial ROCK Pi E support (as WIP) (#2042)
+
+> X-Git-Archeology: > recovered message: > * WIP: Adding RockpiE config
+> X-Git-Archeology: > recovered message: > Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology: > recovered message: > * Mainline u-boot for ROCK Pi E
+> X-Git-Archeology: > recovered message: > * Initial ROCK Pi E device tree in kernel
+> X-Git-Archeology: > recovered message: > * Fixed supplies for ROCK Pi E device tree
+> X-Git-Archeology: > recovered message: > * Adjusted u-boot load address for rockchip64 boards with 256MB eg. ROCK Pi E
+> X-Git-Archeology: > recovered message: > * Blacklisted lima on ROCK Pi E
+> X-Git-Archeology: > recovered message: > * Fixed ROCK Pi E patch after merge from master
+> X-Git-Archeology: > recovered message: > * Removed mode settings from rk805 regulators
+> X-Git-Archeology: > recovered message: > * Fixed issues with offloading for gigabit interface of RockPi E
+> X-Git-Archeology: > recovered message: > * Adjusted ROCK Pi E board config
+> X-Git-Archeology: > recovered message: > * Added dev branch for ROCK Pi E
+> X-Git-Archeology: > recovered message: > * Add build targets
+> X-Git-Archeology: > recovered message: > Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology: > recovered message: > * Exchange legacy to current in ROCK Pi E build targets
+> X-Git-Archeology: > recovered message: > Co-authored-by: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology: - Revision e1ecb098330dc372740371dc2386f911833a0529: https://github.com/armbian/build/commit/e1ecb098330dc372740371dc2386f911833a0529
+> X-Git-Archeology:   Date: Sat, 20 Jun 2020 22:39:57 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Initial ROCK Pi E support (as WIP) (#2042)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 72257bd0648c28fca32962126bb885a4a2c188cc: https://github.com/armbian/build/commit/72257bd0648c28fca32962126bb885a4a2c188cc
+> X-Git-Archeology:   Date: Tue, 23 Jun 2020 16:37:54 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Make USB3 support of ROCK Pi E on par with other rk3328 boards (#2050)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e36ce875b025e112127cf8cc2d34825ebfe36569: https://github.com/armbian/build/commit/e36ce875b025e112127cf8cc2d34825ebfe36569
+> X-Git-Archeology:   Date: Tue, 10 Nov 2020 21:43:13 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switched rockchip64-current to linux 5.9.y (#2309)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ccbc888b3f5731790128684959b55b6552e26190: https://github.com/armbian/build/commit/ccbc888b3f5731790128684959b55b6552e26190
+> X-Git-Archeology:   Date: Sat, 28 Nov 2020 16:52:34 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: add dts rk3328-roc-pc, fix WIFI and USB 3.0 rk3328 (#2390)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 25bd76527e1276c4c00829f68c0ca0742ecc94c1: https://github.com/armbian/build/commit/25bd76527e1276c4c00829f68c0ca0742ecc94c1
+> X-Git-Archeology:   Date: Sat, 28 Nov 2020 18:10:53 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Fix roc-rk3328-pc device tree reference to missing RK_FUNC_1
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070
+> X-Git-Archeology:   Date: Sun, 13 Dec 2020 22:13:03 -0500
+> X-Git-Archeology:   From: tonymac32 <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: [ rockchip64 ] Clean up patchset
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 25e0f1633467c020f6ae68d09964a522fbfbe613: https://github.com/armbian/build/commit/25e0f1633467c020f6ae68d09964a522fbfbe613
+> X-Git-Archeology:   Date: Mon, 18 Jan 2021 23:21:40 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Adjusted power and pmic configuration for Station M1 in current/dev
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision d8dbefd61838e5b0cfc2b93d2d168f3fb2666dfb: https://github.com/armbian/build/commit/d8dbefd61838e5b0cfc2b93d2d168f3fb2666dfb
+> X-Git-Archeology:   Date: Tue, 27 Jul 2021 00:05:09 -0400
+> X-Git-Archeology:   From: tonymac32 <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: [ rockchip64 ] rk3328 change to mainline USB3
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision a16699260fb786a4d89a1c335722e9fed49d19d2: https://github.com/armbian/build/commit/a16699260fb786a4d89a1c335722e9fed49d19d2
+> X-Git-Archeology:   Date: Fri, 08 Jul 2022 22:35:59 +1200
+> X-Git-Archeology:   From: schwar3kat <61094841+schwar3kat@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Refactored orangepi-r1plus-lts dts in kernel add board patch
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8648dde23ff090b5fb704adab036ed14cd944ba3: https://github.com/armbian/build/commit/8648dde23ff090b5fb704adab036ed14cd944ba3
+> X-Git-Archeology:   Date: Thu, 22 Sep 2022 10:25:28 +0200
+> X-Git-Archeology:   From: aiamadeus <42570690+aiamadeus@users.noreply.github.com>
+> X-Git-Archeology:   Subject: rockchip: fixes support for orangepi-r1plus (#4215)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 85bab47bba73e0ef0e4ea5fde60e0aab56f82906: https://github.com/armbian/build/commit/85bab47bba73e0ef0e4ea5fde60e0aab56f82906
+> X-Git-Archeology:   Date: Sat, 06 May 2023 12:55:10 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 906ca66430329ab774f5b9d0f62eef1ce5e398fe: https://github.com/armbian/build/commit/906ca66430329ab774f5b9d0f62eef1ce5e398fe
+> X-Git-Archeology:   Date: Tue, 16 May 2023 08:55:33 +0200
+> X-Git-Archeology:   From: Ricardo Pardini <ricardo@pardini.net>
+> X-Git-Archeology:   Subject: `rockchip64`/`edge`/`6.3`: rebase/rewrite patches against `v6.3.1`; do archeology for mbox-less patches; materialize overwrites
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 19d532b13cabc1a749f61b9c400d933ba5aeb7e3: https://github.com/armbian/build/commit/19d532b13cabc1a749f61b9c400d933ba5aeb7e3
+> X-Git-Archeology:   Date: Tue, 13 Jun 2023 12:33:59 +0200
+> X-Git-Archeology:   From: Ricardo Pardini <ricardo@pardini.net>
+> X-Git-Archeology:   Subject: `rockchip64` `edge` 6.3: rename most remaining "add-board" patches to "board" (all "add-board"s are now bare .dts in `dt/` folder)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 41ade999f04c26a277cfa1c3c721cbe869d3ad12: https://github.com/armbian/build/commit/41ade999f04c26a277cfa1c3c721cbe869d3ad12
+> X-Git-Archeology:   Date: Tue, 03 Oct 2023 13:54:03 +0200
+> X-Git-Archeology:   From: Ricardo Pardini <ricardo@pardini.net>
+> X-Git-Archeology:   Subject: `rockchip64`/`edge`: bump to `6.6-rc4`; initial copy patches from 6.5
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 1f4df4c41fe33f9822ca2f42d14a2a445e27aed7: https://github.com/armbian/build/commit/1f4df4c41fe33f9822ca2f42d14a2a445e27aed7
+> X-Git-Archeology:   Date: Sun, 14 Jan 2024 14:14:50 +0100
+> X-Git-Archeology:   From: Paolo Sabatino <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64: bump edge to 6.7, current to 6.6
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e4d413b9166e3633b40fb23382fb1045b9d0e315: https://github.com/armbian/build/commit/e4d413b9166e3633b40fb23382fb1045b9d0e315
+> X-Git-Archeology:   Date: Tue, 26 Mar 2024 13:46:35 +0100
+> X-Git-Archeology:   From: Paolo Sabatino <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64: bump edge kernel to 6.8
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision fae4549764c548cb65d3cbfe319f1e11bc777505: https://github.com/armbian/build/commit/fae4549764c548cb65d3cbfe319f1e11bc777505
+> X-Git-Archeology:   Date: Thu, 04 Apr 2024 13:38:18 +0800
+> X-Git-Archeology:   From: aiamadeus <2789289348@qq.com>
+> X-Git-Archeology:   Subject: rockchip: update dts patches for orangepi r1-plus
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 45 ++++++++++
+ 1 file changed, 45 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+index f20662929c77..c55d79e12f16 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+@@ -8,6 +8,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
++#include "rk3328-dram-default-timing.dtsi"
+ #include "rk3328.dtsi"
+ 
+ / {
+@@ -86,6 +87,33 @@ vdd_5v_lan: vdd-5v-lan-regulator {
+ 		regulator-boot-on;
+ 		vin-supply = <&vcc_sys>;
+ 	};
++
++	/delete-node/ dmc-opp-table;
++
++	dmc_opp_table: dmc_opp_table {
++		compatible = "operating-points-v2";
++
++		opp-786000000 {
++			opp-hz = /bits/ 64 <786000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++		};
++		opp-798000000 {
++			opp-hz = /bits/ 64 <798000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++		};
++		opp-840000000 {
++			opp-hz = /bits/ 64 <840000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++		};
++		opp-924000000 {
++			opp-hz = /bits/ 64 <924000000>;
++			opp-microvolt = <1100000 1100000 1200000>;
++		};
++		opp-1056000000 {
++			opp-hz = /bits/ 64 <1056000000>;
++			opp-microvolt = <1175000 1175000 1200000>;
++		};
++	};
+ };
+ 
+ &cpu0 {
+@@ -108,6 +136,16 @@ &display_subsystem {
+ 	status = "disabled";
+ };
+ 
++&dfi {
++	status = "okay";
++};
++
++&dmc {
++	center-supply = <&vdd_log>;
++	ddr_timing = <&ddr_timing>;
++	status = "okay";
++};
++
+ &gmac2io {
+ 	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ 	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
+@@ -138,6 +176,10 @@ rtl8211e: ethernet-phy@1 {
+ 	};
+ };
+ 
++&i2c0 {
++	status = "okay";
++};
++
+ &i2c1 {
+ 	status = "okay";
+ 
+@@ -167,6 +209,7 @@ vdd_log: DCDC_REG1 {
+ 				regulator-name = "vdd_log";
+ 				regulator-always-on;
+ 				regulator-boot-on;
++				regulator-init-microvolt = <1075000>;
+ 				regulator-min-microvolt = <712500>;
+ 				regulator-max-microvolt = <1450000>;
+ 				regulator-ramp-delay = <12500>;
+@@ -181,6 +224,7 @@ vdd_arm: DCDC_REG2 {
+ 				regulator-name = "vdd_arm";
+ 				regulator-always-on;
+ 				regulator-boot-on;
++				regulator-init-microvolt = <1225000>;
+ 				regulator-min-microvolt = <712500>;
+ 				regulator-max-microvolt = <1450000>;
+ 				regulator-ramp-delay = <12500>;
+@@ -362,6 +406,7 @@ &usbdrd3 {
+ 	rtl8153: device@2 {
+ 		compatible = "usbbda,8153";
+ 		reg = <2>;
++		realtek,led-data = <0x87>;
+ 	};
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-orangepi-rk3399-pcie.patch b/patch/kernel/archive/rockchip64-6.10/board-orangepi-rk3399-pcie.patch
new file mode 100644
index 000000000000..dfbf219abd24
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-orangepi-rk3399-pcie.patch
@@ -0,0 +1,68 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: amazingfate <liujianfeng1994@gmail.com>
+Date: Thu, 18 Apr 2024 00:42:13 +0800
+Subject: arm64: dts: rockchip: add pcie support to orangepi rk3399 board
+
+---
+ arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 31 ++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
+index e7551449e718..fc23d4733509 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
+@@ -124,6 +124,17 @@ vcc3v0_sd: vcc3v0-sd {
+ 		vin-supply = <&vcc3v3_sys>;
+ 	};
+ 
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 2 0>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_drv>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-name = "vcc3v3_pcie";
++	};
++
+ 	vcc3v3_sys: vcc3v3-sys {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc3v3_sys";
+@@ -588,6 +599,20 @@ &io_domains {
+ 	gpio1830-supply = <&vcc_3v0>;
+ };
+ 
++&pcie_phy {
++	status = "okay";
++	assigned-clocks = <&cru 138>;
++	assigned-clock-parents = <&cru 167>;
++	assigned-clock-rates = <100000000>;
++};
++
++&pcie0 {
++	status = "okay";
++	ep-gpios = <&gpio2 4 0>;
++	num-lanes = <4>;
++	max-link-speed = <1>;
++};
++
+ &pmu_io_domains {
+ 	status = "okay";
+ 	pmu1830-supply = <&vcc_3v0>;
+@@ -610,6 +635,12 @@ phy_rstb: phy-rstb {
+ 		};
+ 	};
+ 
++	pcie {
++		pcie_drv: pcie-drv {
++			rockchip,pins = <0 2 0 &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		cpu_b_sleep: cpu-b-sleep {
+ 			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-pbp-add-dp-alt-mode.patch b/patch/kernel/archive/rockchip64-6.10/board-pbp-add-dp-alt-mode.patch
new file mode 100644
index 000000000000..6e29666c547e
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-pbp-add-dp-alt-mode.patch
@@ -0,0 +1,421 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Dan Johansen <strit@manjaro.org>
+Date: Tue, 2 Jun 2020 20:20:29 +0200
+Subject: add-dp-alt-mode-to-PBP
+
+---
+ arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts |   5 +
+ drivers/phy/rockchip/phy-rockchip-typec.c            |  17 ++
+ drivers/usb/typec/altmodes/displayport.c             |  52 +++-
+ drivers/usb/typec/tcpm/tcpm.c                        | 139 +++++++++-
+ 4 files changed, 210 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+index 054c6a4d1a45..48b865d30b14 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+@@ -422,6 +422,7 @@ edp_out_panel: endpoint@0 {
+ 
+ &emmc_phy {
+ 	status = "okay";
++	extcon = <&fusb0>;
+ };
+ 
+ &gpu {
+@@ -706,6 +707,9 @@ connector {
+ 				<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+ 			try-power-role = "sink";
+ 
++			extcon-cables = <1 2 5 6 9 10 12 44>;
++			typec-altmodes = <0xff01 1 0x001c0000 1>;
++
+ 			ports {
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+@@ -972,6 +976,7 @@ spiflash: flash@0 {
+ };
+ 
+ &tcphy0 {
++	extcon = <&fusb0>;
+ 	status = "okay";
+ };
+ 
+diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
+index 4efcb78b0ab1..6a641d9f752c 100644
+--- a/drivers/phy/rockchip/phy-rockchip-typec.c
++++ b/drivers/phy/rockchip/phy-rockchip-typec.c
+@@ -40,6 +40,7 @@
+ #include <linux/clk-provider.h>
+ #include <linux/delay.h>
+ #include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/io.h>
+ #include <linux/iopoll.h>
+ #include <linux/kernel.h>
+@@ -1156,6 +1157,22 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev)
+ 				dev_err(dev, "Invalid or missing extcon\n");
+ 			return PTR_ERR(tcphy->extcon);
+ 		}
++	} else {
++		extcon_set_property_capability(tcphy->extcon, EXTCON_USB,
++					       EXTCON_PROP_USB_SS);
++		extcon_set_property_capability(tcphy->extcon, EXTCON_USB_HOST,
++					       EXTCON_PROP_USB_SS);
++		extcon_set_property_capability(tcphy->extcon, EXTCON_DISP_DP,
++					       EXTCON_PROP_USB_SS);
++		extcon_set_property_capability(tcphy->extcon, EXTCON_USB,
++					       EXTCON_PROP_USB_TYPEC_POLARITY);
++		extcon_set_property_capability(tcphy->extcon, EXTCON_USB_HOST,
++					       EXTCON_PROP_USB_TYPEC_POLARITY);
++		extcon_set_property_capability(tcphy->extcon, EXTCON_DISP_DP,
++					       EXTCON_PROP_USB_TYPEC_POLARITY);
++		extcon_sync(tcphy->extcon, EXTCON_USB);
++		extcon_sync(tcphy->extcon, EXTCON_USB_HOST);
++		extcon_sync(tcphy->extcon, EXTCON_DISP_DP);
+ 	}
+ 
+ 	pm_runtime_enable(dev);
+diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c
+index 59e0218a8bc5..5b046eb1fad7 100644
+--- a/drivers/usb/typec/altmodes/displayport.c
++++ b/drivers/usb/typec/altmodes/displayport.c
+@@ -9,6 +9,8 @@
+  */
+ 
+ #include <linux/delay.h>
++#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/mutex.h>
+ #include <linux/module.h>
+ #include <linux/property.h>
+@@ -69,6 +71,8 @@ struct dp_altmode {
+ 	struct fwnode_handle *connector_fwnode;
+ };
+ 
++void dp_altmode_update_extcon(struct dp_altmode *dp, bool disconnect);
++
+ static int dp_altmode_notify(struct dp_altmode *dp)
+ {
+ 	unsigned long conf;
+@@ -77,7 +81,9 @@ static int dp_altmode_notify(struct dp_altmode *dp)
+ 	if (dp->data.conf) {
+ 		state = get_count_order(DP_CONF_GET_PIN_ASSIGN(dp->data.conf));
+ 		conf = TYPEC_MODAL_STATE(state);
++		dp_altmode_update_extcon(dp, false);
+ 	} else {
++		dp_altmode_update_extcon(dp, true);
+ 		conf = TYPEC_STATE_USB;
+ 	}
+ 
+@@ -163,6 +169,40 @@ static int dp_altmode_status_update(struct dp_altmode *dp)
+ 	return ret;
+ }
+ 
++void dp_altmode_update_extcon(struct dp_altmode *dp, bool disconnect) {
++	const struct device *dev = &dp->port->dev;
++	struct extcon_dev* edev = NULL;
++
++	while (dev) {
++		edev = extcon_find_edev_by_node(dev->of_node);
++		if(!IS_ERR(edev)) {
++			break;
++		}
++		dev = dev->parent;
++	}
++
++	if (IS_ERR_OR_NULL(edev)) {
++		return;
++	}
++
++	if (disconnect || !dp->data.conf) {
++		extcon_set_state_sync(edev, EXTCON_DISP_DP, false);
++	} else {
++		union extcon_property_value extcon_true = { .intval = true };
++		extcon_set_state(edev, EXTCON_DISP_DP, true);
++		if (DP_CONF_GET_PIN_ASSIGN(dp->data.conf) & DP_PIN_ASSIGN_MULTI_FUNC_MASK) {
++			extcon_set_state_sync(edev, EXTCON_USB_HOST, true);
++			extcon_set_property(edev, EXTCON_DISP_DP, EXTCON_PROP_USB_SS,
++						 extcon_true);
++		} else {
++			extcon_set_state_sync(edev, EXTCON_USB_HOST, false);
++		}
++		extcon_sync(edev, EXTCON_DISP_DP);
++		extcon_set_state_sync(edev, EXTCON_USB, false);
++	}
++
++}
++
+ static int dp_altmode_configured(struct dp_altmode *dp)
+ {
+ 	sysfs_notify(&dp->alt->dev.kobj, "displayport", "configuration");
+@@ -242,6 +282,8 @@ static void dp_altmode_work(struct work_struct *work)
+ 	case DP_STATE_EXIT:
+ 		if (typec_altmode_exit(dp->alt))
+ 			dev_err(&dp->alt->dev, "Exit Mode Failed!\n");
++		else
++			dp_altmode_update_extcon(dp, true);
+ 		break;
+ 	default:
+ 		break;
+@@ -579,8 +621,14 @@ int dp_altmode_probe(struct typec_altmode *alt)
+ 	if (!(DP_CAP_PIN_ASSIGN_DFP_D(port->vdo) &
+ 	      DP_CAP_PIN_ASSIGN_UFP_D(alt->vdo)) &&
+ 	    !(DP_CAP_PIN_ASSIGN_UFP_D(port->vdo) &
+-	      DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo)))
+-		return -ENODEV;
++	      DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo))) {
++            dev_err(&alt->dev, "No compatible pin configuration found:"\
++                    "%04lx -> %04lx, %04lx <- %04lx",
++                    DP_CAP_PIN_ASSIGN_DFP_D(port->vdo), DP_CAP_PIN_ASSIGN_UFP_D(alt->vdo),
++                    DP_CAP_PIN_ASSIGN_UFP_D(port->vdo), DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo));
++            return -ENODEV;
++	}
++
+ 
+ 	ret = sysfs_create_group(&alt->dev.kobj, &dp_altmode_group);
+ 	if (ret)
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index d962f67c95ae..5ac809870867 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -8,6 +8,7 @@
+ #include <linux/completion.h>
+ #include <linux/debugfs.h>
+ #include <linux/device.h>
++#include <linux/extcon-provider.h>
+ #include <linux/hrtimer.h>
+ #include <linux/jiffies.h>
+ #include <linux/kernel.h>
+@@ -552,6 +552,12 @@ struct tcpm_port {
+ 	 */
+ 	unsigned int message_id_prime;
+ 	unsigned int rx_msgid_prime;
++
++#ifdef CONFIG_EXTCON
++	struct extcon_dev *extcon;
++	unsigned int *extcon_cables;
++#endif
++
+ #ifdef CONFIG_DEBUG_FS
+ 	struct dentry *dentry;
+ 	struct mutex logbuffer_lock;	/* log buffer access lock */
+@@ -879,6 +886,35 @@ static void tcpm_ams_finish(struct tcpm_port *port)
+ 	port->ams = NONE_AMS;
+ }
+ 
++static void tcpm_update_extcon_data(struct tcpm_port *port, bool attached) {
++#ifdef CONFIG_EXTCON
++	unsigned int *capability = port->extcon_cables;
++	if (port->data_role == TYPEC_HOST) {
++		extcon_set_state(port->extcon, EXTCON_USB, false);
++		extcon_set_state(port->extcon, EXTCON_USB_HOST, attached);
++	} else {
++		extcon_set_state(port->extcon, EXTCON_USB, true);
++		extcon_set_state(port->extcon, EXTCON_USB_HOST, attached);
++	}
++	while (*capability != EXTCON_NONE) {
++		if (attached) {
++			union extcon_property_value val;
++			val.intval = (port->polarity == TYPEC_POLARITY_CC2);
++			extcon_set_property(port->extcon, *capability,
++				EXTCON_PROP_USB_TYPEC_POLARITY, val);
++		} else {
++			extcon_set_state(port->extcon, *capability, false);
++		}
++		extcon_sync(port->extcon, *capability);
++		capability++;
++	}
++	tcpm_log(port, "Extcon update (%s): %s, %s",
++		attached ? "attached" : "detached",
++		port->data_role == TYPEC_HOST ? "host" : "device",
++		port->polarity == TYPEC_POLARITY_CC1 ? "normal" : "flipped");
++#endif
++}
++
+ static int tcpm_pd_transmit(struct tcpm_port *port,
+ 			    enum tcpm_transmit_type type,
+ 			    const struct pd_message *msg)
+@@ -1091,6 +1127,8 @@ static int tcpm_set_roles(struct tcpm_port *port, bool attached,
+ 	typec_set_data_role(port->typec_port, data);
+ 	typec_set_pwr_role(port->typec_port, role);
+ 
++	tcpm_update_extcon_data(port, attached);
++
+ 	return 0;
+ }
+ 
+@@ -1562,7 +1600,7 @@ static void svdm_consume_modes(struct tcpm_port *port, const u32 *p, int cnt)
+ 		paltmode->mode = i;
+ 		paltmode->vdo = p[i];
+ 
+-		tcpm_log(port, " Alternate mode %d: SVID 0x%04x, VDO %d: 0x%08x",
++		tcpm_log(port, "Alternate mode %d: SVID 0x%04x, VDO %d: 0x%08x",
+ 			 pmdata->altmodes, paltmode->svid,
+ 			 paltmode->mode, paltmode->vdo);
+ 
+@@ -1583,6 +1621,8 @@ static void tcpm_register_partner_altmodes(struct tcpm_port *port)
+ 			tcpm_log(port, "Failed to register partner SVID 0x%04x",
+ 				 modep->altmode_desc[i].svid);
+ 			altmode = NULL;
++		} else {
++			tcpm_log(port, "Registered altmode 0x%04x", modep->altmode_desc[i].svid);
+ 		}
+ 		port->partner_altmode[i] = altmode;
+ 	}
+@@ -2167,11 +2173,13 @@ static int tcpm_pd_svdm(struct tcpm_port *port, struct typec_altmode *adev,
+ 				modep->svid_index++;
+ 				if (modep->svid_index < modep->nsvids) {
+ 					u16 svid = modep->svids[modep->svid_index];
++					tcpm_log(port, "More modes available, sending discover");
+ 					*response_tx_sop_type = TCPC_TX_SOP;
+ 					response[0] = VDO(svid, 1, svdm_version,
+ 							  CMD_DISCOVER_MODES);
+ 					rlen = 1;
+ 				} else if (tcpm_cable_vdm_supported(port)) {
++					tcpm_log(port, "Got all patner modes, registering");
+ 					*response_tx_sop_type = TCPC_TX_SOP_PRIME;
+ 					response[0] = VDO(USB_SID_PD, 1,
+ 							  typec_get_cable_svdm_version(typec),
+@@ -3650,8 +3692,9 @@ static int tcpm_src_attach(struct tcpm_port *port)
+ static void tcpm_typec_disconnect(struct tcpm_port *port)
+ {
+ 	if (port->connected) {
+ 		if (port->partner) {
++			tcpm_update_extcon_data(port, false);
+ 			typec_partner_set_usb_power_delivery(port->partner, NULL);
+ 			typec_unregister_partner(port->partner);
+ 			port->partner = NULL;
+ 		}
+@@ -3739,6 +3782,8 @@ static void tcpm_detach(struct tcpm_port *port)
+ 	}
+ 
+ 	tcpm_reset_port(port);
++
++	tcpm_update_extcon_data(port, false);
+ }
+ 
+ static void tcpm_src_detach(struct tcpm_port *port)
+@@ -6258,6 +6303,64 @@ static int tcpm_port_register_pd(struct tcpm_port *port)
+ 	return ret;
+ }
+ 
++unsigned int default_supported_cables[] = {
++	EXTCON_NONE
++};
++
++static int tcpm_fw_get_caps_late(struct tcpm_port *port,
++			    struct fwnode_handle *fwnode)
++{
++	int ret, i;
++	ret = fwnode_property_count_u32(fwnode, "typec-altmodes");
++	if (ret > 0) {
++		u32 *props;
++		if (ret % 4) {
++			dev_err(port->dev, "Length of typec altmode array must be divisible by 4");
++			return -EINVAL;
++		}
++
++		props = devm_kzalloc(port->dev, sizeof(u32) * ret, GFP_KERNEL);
++		if (!props) {
++			dev_err(port->dev, "Failed to allocate memory for altmode properties");
++			return -ENOMEM;
++		}
++
++		if(fwnode_property_read_u32_array(fwnode, "typec-altmodes", props, ret) < 0) {
++			dev_err(port->dev, "Failed to read altmodes from port");
++			return -EINVAL;
++		}
++
++		i = 0;
++		while (ret > 0 && i < ARRAY_SIZE(port->port_altmode)) {
++			struct typec_altmode *alt;
++			struct typec_altmode_desc alt_desc = {
++				.svid = props[i * 4],
++				.mode = props[i * 4 + 1],
++				.vdo  = props[i * 4 + 2],
++				.roles = props[i * 4 + 3],
++			};
++
++
++			tcpm_log(port, "Adding altmode SVID: 0x%04x, mode: %d, vdo: %u, role: %d",
++				alt_desc.svid, alt_desc.mode, alt_desc.vdo, alt_desc.roles);
++			alt = typec_port_register_altmode(port->typec_port,
++							  &alt_desc);
++			if (IS_ERR(alt)) {
++				tcpm_log(port,
++					 "%s: failed to register port alternate mode 0x%x",
++					 dev_name(port->dev), alt_desc.svid);
++				break;
++			}
++			typec_altmode_set_drvdata(alt, port);
++			alt->ops = &tcpm_altmode_ops;
++			port->port_altmode[i] = alt;
++			i++;
++			ret -= 4;
++		}
++	}
++	return 0;
++}
++
+ static int tcpm_fw_get_caps(struct tcpm_port *port, struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *capabilities, *child, *caps = NULL;
+@@ -6119,6 +6222,23 @@ static int tcpm_fw_get_caps(struct tcpm_port *port,
+ 	if (!fwnode)
+ 		return -EINVAL;
+ 
++#ifdef CONFIG_EXTCON
++	ret = fwnode_property_count_u32(fwnode, "extcon-cables");
++	if (ret > 0) {
++		port->extcon_cables = devm_kzalloc(port->dev, sizeof(u32) * ret, GFP_KERNEL);
++		if (!port->extcon_cables) {
++			dev_err(port->dev, "Failed to allocate memory for extcon cable types. "\
++				"Using default tyes");
++			goto extcon_default;
++		}
++		fwnode_property_read_u32_array(fwnode, "extcon-cables", port->extcon_cables, ret);
++	} else {
++extcon_default:
++		dev_info(port->dev, "No cable types defined, using default cables");
++		port->extcon_cables = default_supported_cables;
++	}
++#endif
++
+ 	/*
+ 	 * This fwnode has a "compatible" property, but is never populated as a
+ 	 * struct device. Instead we simply parse it to read the properties.
+@@ -6571,6 +6691,17 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc)
+ 		goto out_destroy_wq;
+ 
+ 	port->try_role = port->typec_caps.prefer_role;
++#ifdef CONFIG_EXTCON
++	port->extcon = devm_extcon_dev_allocate(dev, port->extcon_cables);
++	if (IS_ERR(port->extcon)) {
++		dev_err(dev, "Failed to allocate extcon device: %ld", PTR_ERR(port->extcon));
++		goto out_destroy_wq;
++	}
++	if((err = devm_extcon_dev_register(dev, port->extcon))) {
++		dev_err(dev, "Failed to register extcon device: %d", err);
++		goto out_destroy_wq;
++	}
++#endif
+ 
+ 	port->typec_caps.fwnode = tcpc->fwnode;
+ 	port->typec_caps.revision = 0x0120;	/* Type-C spec release 1.2 */
+@@ -6613,6 +6744,12 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc)
+ 				     port->port_altmode, ALTMODE_DISCOVERY_MAX);
+ 	port->registered = true;
+ 
++	err = tcpm_fw_get_caps_late(port, tcpc->fwnode);
++	if (err < 0) {
++		dev_err(dev, "Failed to get altmodes from fwnode");
++		goto out_destroy_wq;
++	}
++
+ 	mutex_lock(&port->lock);
+ 	tcpm_init(port);
+ 	mutex_unlock(&port->lock);
+-- 
+Armbian
+
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-radxa-e25-sdmmc0-fix.patch b/patch/kernel/archive/rockchip64-6.10/board-radxa-e25-sdmmc0-fix.patch
new file mode 100644
index 000000000000..41758a620fbd
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-radxa-e25-sdmmc0-fix.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: krachlatte <krachlatte1977@gmail.com>
+Date: Wed, 17 May 2023 00:55:30 +0200
+Subject: [ARCHEOLOGY] Improve SD card compatibility on Radxa E25 (#5165)
+
+> X-Git-Archeology: - Revision 45c85878613108c238e491aa69650fcad1fba4bb: https://github.com/armbian/build/commit/45c85878613108c238e491aa69650fcad1fba4bb
+> X-Git-Archeology:   Date: Wed, 17 May 2023 00:55:30 +0200
+> X-Git-Archeology:   From: krachlatte <krachlatte1977@gmail.com>
+> X-Git-Archeology:   Subject: Improve SD card compatibility on Radxa E25 (#5165)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f6a0c53d08f53aadd0588a571662dc199232825b: https://github.com/armbian/build/commit/f6a0c53d08f53aadd0588a571662dc199232825b
+> X-Git-Archeology:   Date: Wed, 24 May 2023 10:39:21 +0200
+> X-Git-Archeology:   From: Ricardo Pardini <ricardo@pardini.net>
+> X-Git-Archeology:   Subject: manual e25 patch fix
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+index 72ad74c38a2b..5751dc7e2ebc 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+@@ -194,7 +194,7 @@ &sdmmc0 {
+ 	disable-wp;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
+-	sd-uhs-sdr104;
++    sd-uhs-sdr50;
+ 	vmmc-supply = <&vcc3v3_sd>;
+ 	vqmmc-supply = <&vccio_sd>;
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-radxa-e25-usb3-and-emmc-fix.patch b/patch/kernel/archive/rockchip64-6.10/board-radxa-e25-usb3-and-emmc-fix.patch
new file mode 100644
index 000000000000..afd5918a0b7e
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-radxa-e25-usb3-and-emmc-fix.patch
@@ -0,0 +1,64 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: krachlatte <krachlatte1977@gmail.com>
+Date: Wed, 17 May 2023 00:55:30 +0200
+Subject: [ARCHEOLOGY] Improve SD card compatibility on Radxa E25 (#5165)
+
+> X-Git-Archeology: - Revision 45c85878613108c238e491aa69650fcad1fba4bb: https://github.com/armbian/build/commit/45c85878613108c238e491aa69650fcad1fba4bb
+> X-Git-Archeology:   Date: Wed, 17 May 2023 00:55:30 +0200
+> X-Git-Archeology:   From: krachlatte <krachlatte1977@gmail.com>
+> X-Git-Archeology:   Subject: Improve SD card compatibility on Radxa E25 (#5165)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f6a0c53d08f53aadd0588a571662dc199232825b: https://github.com/armbian/build/commit/f6a0c53d08f53aadd0588a571662dc199232825b
+> X-Git-Archeology:   Date: Wed, 24 May 2023 10:39:21 +0200
+> X-Git-Archeology:   From: Ricardo Pardini <ricardo@pardini.net>
+> X-Git-Archeology:   Subject: manual e25 patch fix
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 12 ++++++++++
+ arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts   |  2 ++
+ 2 files changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
+index 45b03dcbbad4..ffae714d56dc 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
+@@ -389,6 +389,17 @@ &sdhci {
+ 	status = "okay";
+ };
+ 
++&sfc {
++	status = "okay";
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <108000000>;
++		spi-rx-bus-width = <2>;
++		spi-tx-bus-width = <2>;
++	};
++};
++
+ &tsadc {
+ 	rockchip,hw-tshut-mode = <1>;
+ 	rockchip,hw-tshut-polarity = <0>;
+@@ -409,4 +420,5 @@ &usb2phy1 {
+ 
+ &usb_host0_xhci {
+ 	extcon = <&usb2phy0>;
++	dr_mode = "host";
+ };
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+index 5751dc7e2ebc..7d7d00adf10a 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+@@ -209,6 +209,8 @@ &usb_host0_ohci {
+ };
+ 
+ &usb_host0_xhci {
++	extcon = <&usb2phy0>;
++	dr_mode = "host";
+ 	status = "okay";
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-cc-dts-enable-dmc.patch b/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-cc-dts-enable-dmc.patch
new file mode 100644
index 000000000000..658c3e15ce3e
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-cc-dts-enable-dmc.patch
@@ -0,0 +1,75 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 12 Oct 2021 18:31:28 +0000
+Subject: enable roc-cc dmc
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 38 ++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+index 5d5d9574088c..be5d064d6a93 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -4,6 +4,7 @@
+  */
+ 
+ /dts-v1/;
++#include "rk3328-dram-renegade-timing.dtsi"
+ #include "rk3328.dtsi"
+ 
+ / {
+@@ -19,6 +20,32 @@ chosen {
+ 		stdout-path = "serial2:1500000n8";
+ 	};
+ 
++	/delete-node/ dmc-opp-table;
++	dmc_opp_table: dmc-opp-table {
++		compatible = "operating-points-v2";
++
++		opp-786000000 {
++			opp-hz = /bits/ 64 <786000000>;
++			opp-microvolt = <1075000 1075000 12000000>;
++		};
++		opp-798000000 {
++			opp-hz = /bits/ 64 <798000000>;
++			opp-microvolt = <1075000 1075000 12000000>;
++		};
++		opp-840000000 {
++			opp-hz = /bits/ 64 <840000000>;
++			opp-microvolt = <1075000 1075000 12000000>;
++		};
++		opp-924000000 {
++			opp-hz = /bits/ 64 <924000000>;
++			opp-microvolt = <1100000 1100000 12000000>;
++		};
++		opp-1068000000 {
++			opp-hz = /bits/ 64 <1068000000>;
++			opp-microvolt = <1175000 1175000 12000000>;
++		};
++	};
++
+ 	gmac_clkin: external-gmac-clock {
+ 		compatible = "fixed-clock";
+ 		clock-frequency = <125000000>;
+@@ -115,6 +142,17 @@ &codec {
+ 	status = "okay";
+ };
+ 
++&dfi {
++	status = "okay";
++};
++
++&dmc {
++	center-supply = <&vdd_logic>;
++	ddr_timing = <&ddr_timing>;
++	status = "okay";
++};
++
++
+ &cpu0 {
+ 	cpu-supply = <&vdd_arm>;
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-cc-dts-ram-profile.patch b/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-cc-dts-ram-profile.patch
new file mode 100644
index 000000000000..71b23c423c80
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-cc-dts-ram-profile.patch
@@ -0,0 +1,330 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: tonymac32 <tonymckahan@gmail.com>
+Date: Wed, 7 Oct 2020 23:39:54 -0400
+Subject: board-rk3328-roc-cc-adjust-DMC-opps
+
+Signed-off-by: tonymac32 <tonymckahan@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi | 311 ++++++++++
+ 1 file changed, 311 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi
+new file mode 100644
+index 000000000000..303428153094
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi
+@@ -0,0 +1,311 @@
++/*
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++#include <dt-bindings/clock/rockchip-ddr.h>
++#include <dt-bindings/memory/rk3328-dram.h>
++
++/ {
++	ddr_timing: ddr_timing {
++		compatible = "rockchip,ddr-timing";
++		ddr3_speed_bin = <DDR3_DEFAULT>;
++		ddr4_speed_bin = <DDR4_DEFAULT>;
++		pd_idle = <0>;
++		sr_idle = <0>;
++		sr_mc_gate_idle = <0>;
++		srpd_lite_idle	= <0>;
++		standby_idle = <0>;
++
++		auto_pd_dis_freq = <1066>;
++		auto_sr_dis_freq = <800>;
++		ddr3_dll_dis_freq = <300>;
++		ddr4_dll_dis_freq = <625>;
++		phy_dll_dis_freq = <400>;
++
++		ddr3_odt_dis_freq = <100>;
++		phy_ddr3_odt_dis_freq = <100>;
++		ddr3_drv = <DDR3_DS_40ohm>;
++		ddr3_odt = <DDR3_ODT_120ohm>;
++		phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
++		phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
++		phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
++		phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
++
++		lpddr3_odt_dis_freq = <666>;
++		phy_lpddr3_odt_dis_freq = <666>;
++		lpddr3_drv = <LP3_DS_40ohm>;
++		lpddr3_odt = <LP3_ODT_240ohm>;
++		phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
++		phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
++		phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
++		phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
++
++		lpddr4_odt_dis_freq = <800>;
++		phy_lpddr4_odt_dis_freq = <800>;
++		lpddr4_drv = <LP4_PDDS_60ohm>;
++		lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
++		lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
++		phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
++		phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
++		phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
++		phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
++
++		ddr4_odt_dis_freq = <666>;
++		phy_ddr4_odt_dis_freq = <666>;
++		ddr4_drv = <DDR4_DS_34ohm>;
++		ddr4_odt = <DDR4_RTT_NOM_240ohm>;
++		phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
++		phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
++		phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
++		phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
++
++		/* CA de-skew, one step is 47.8ps, range 0-15 */
++		ddr3a1_ddr4a9_de-skew = <0>;
++		ddr3a0_ddr4a10_de-skew = <0>;
++		ddr3a3_ddr4a6_de-skew = <1>;
++		ddr3a2_ddr4a4_de-skew = <1>;
++		ddr3a5_ddr4a8_de-skew = <0>;
++		ddr3a4_ddr4a5_de-skew = <2>;
++		ddr3a7_ddr4a11_de-skew = <0>;
++		ddr3a6_ddr4a7_de-skew = <2>;
++		ddr3a9_ddr4a0_de-skew = <1>;
++		ddr3a8_ddr4a13_de-skew = <0>;
++		ddr3a11_ddr4a3_de-skew = <2>;
++		ddr3a10_ddr4cs0_de-skew = <0>;
++		ddr3a13_ddr4a2_de-skew = <1>;
++		ddr3a12_ddr4ba1_de-skew = <0>;
++		ddr3a15_ddr4odt0_de-skew = <0>;
++		ddr3a14_ddr4a1_de-skew = <1>;
++		ddr3ba1_ddr4a15_de-skew = <0>;
++		ddr3ba0_ddr4bg0_de-skew = <0>;
++		ddr3ras_ddr4cke_de-skew = <0>;
++		ddr3ba2_ddr4ba0_de-skew = <1>;
++		ddr3we_ddr4bg1_de-skew = <1>;
++		ddr3cas_ddr4a12_de-skew = <0>;
++		ddr3ckn_ddr4ckn_de-skew = <5>;
++		ddr3ckp_ddr4ckp_de-skew = <5>;
++		ddr3cke_ddr4a16_de-skew = <1>;
++		ddr3odt0_ddr4a14_de-skew = <0>;
++		ddr3cs0_ddr4act_de-skew = <1>;
++		ddr3reset_ddr4reset_de-skew = <0>;
++		ddr3cs1_ddr4cs1_de-skew = <0>;
++		ddr3odt1_ddr4odt1_de-skew = <0>;
++
++		/* DATA de-skew
++		 * RX one step is 25.1ps, range 0-15
++		 * TX one step is 47.8ps, range 0-15
++		 */
++		cs0_dm0_rx_de-skew = <7>;
++		cs0_dm0_tx_de-skew = <8>;
++		cs0_dq0_rx_de-skew = <7>;
++		cs0_dq0_tx_de-skew = <8>;
++		cs0_dq1_rx_de-skew = <7>;
++		cs0_dq1_tx_de-skew = <8>;
++		cs0_dq2_rx_de-skew = <7>;
++		cs0_dq2_tx_de-skew = <8>;
++		cs0_dq3_rx_de-skew = <7>;
++		cs0_dq3_tx_de-skew = <8>;
++		cs0_dq4_rx_de-skew = <7>;
++		cs0_dq4_tx_de-skew = <8>;
++		cs0_dq5_rx_de-skew = <7>;
++		cs0_dq5_tx_de-skew = <8>;
++		cs0_dq6_rx_de-skew = <7>;
++		cs0_dq6_tx_de-skew = <8>;
++		cs0_dq7_rx_de-skew = <7>;
++		cs0_dq7_tx_de-skew = <8>;
++		cs0_dqs0_rx_de-skew = <6>;
++		cs0_dqs0p_tx_de-skew = <9>;
++		cs0_dqs0n_tx_de-skew = <9>;
++
++		cs0_dm1_rx_de-skew = <7>;
++		cs0_dm1_tx_de-skew = <7>;
++		cs0_dq8_rx_de-skew = <7>;
++		cs0_dq8_tx_de-skew = <8>;
++		cs0_dq9_rx_de-skew = <7>;
++		cs0_dq9_tx_de-skew = <7>;
++		cs0_dq10_rx_de-skew = <7>;
++		cs0_dq10_tx_de-skew = <8>;
++		cs0_dq11_rx_de-skew = <7>;
++		cs0_dq11_tx_de-skew = <7>;
++		cs0_dq12_rx_de-skew = <7>;
++		cs0_dq12_tx_de-skew = <8>;
++		cs0_dq13_rx_de-skew = <7>;
++		cs0_dq13_tx_de-skew = <7>;
++		cs0_dq14_rx_de-skew = <7>;
++		cs0_dq14_tx_de-skew = <8>;
++		cs0_dq15_rx_de-skew = <7>;
++		cs0_dq15_tx_de-skew = <7>;
++		cs0_dqs1_rx_de-skew = <7>;
++		cs0_dqs1p_tx_de-skew = <9>;
++		cs0_dqs1n_tx_de-skew = <9>;
++
++		cs0_dm2_rx_de-skew = <7>;
++		cs0_dm2_tx_de-skew = <8>;
++		cs0_dq16_rx_de-skew = <7>;
++		cs0_dq16_tx_de-skew = <8>;
++		cs0_dq17_rx_de-skew = <7>;
++		cs0_dq17_tx_de-skew = <8>;
++		cs0_dq18_rx_de-skew = <7>;
++		cs0_dq18_tx_de-skew = <8>;
++		cs0_dq19_rx_de-skew = <7>;
++		cs0_dq19_tx_de-skew = <8>;
++		cs0_dq20_rx_de-skew = <7>;
++		cs0_dq20_tx_de-skew = <8>;
++		cs0_dq21_rx_de-skew = <7>;
++		cs0_dq21_tx_de-skew = <8>;
++		cs0_dq22_rx_de-skew = <7>;
++		cs0_dq22_tx_de-skew = <8>;
++		cs0_dq23_rx_de-skew = <7>;
++		cs0_dq23_tx_de-skew = <8>;
++		cs0_dqs2_rx_de-skew = <6>;
++		cs0_dqs2p_tx_de-skew = <9>;
++		cs0_dqs2n_tx_de-skew = <9>;
++
++		cs0_dm3_rx_de-skew = <7>;
++		cs0_dm3_tx_de-skew = <7>;
++		cs0_dq24_rx_de-skew = <7>;
++		cs0_dq24_tx_de-skew = <8>;
++		cs0_dq25_rx_de-skew = <7>;
++		cs0_dq25_tx_de-skew = <7>;
++		cs0_dq26_rx_de-skew = <7>;
++		cs0_dq26_tx_de-skew = <7>;
++		cs0_dq27_rx_de-skew = <7>;
++		cs0_dq27_tx_de-skew = <7>;
++		cs0_dq28_rx_de-skew = <7>;
++		cs0_dq28_tx_de-skew = <7>;
++		cs0_dq29_rx_de-skew = <7>;
++		cs0_dq29_tx_de-skew = <7>;
++		cs0_dq30_rx_de-skew = <7>;
++		cs0_dq30_tx_de-skew = <7>;
++		cs0_dq31_rx_de-skew = <7>;
++		cs0_dq31_tx_de-skew = <7>;
++		cs0_dqs3_rx_de-skew = <7>;
++		cs0_dqs3p_tx_de-skew = <9>;
++		cs0_dqs3n_tx_de-skew = <9>;
++
++		cs1_dm0_rx_de-skew = <7>;
++		cs1_dm0_tx_de-skew = <8>;
++		cs1_dq0_rx_de-skew = <7>;
++		cs1_dq0_tx_de-skew = <8>;
++		cs1_dq1_rx_de-skew = <7>;
++		cs1_dq1_tx_de-skew = <8>;
++		cs1_dq2_rx_de-skew = <7>;
++		cs1_dq2_tx_de-skew = <8>;
++		cs1_dq3_rx_de-skew = <7>;
++		cs1_dq3_tx_de-skew = <8>;
++		cs1_dq4_rx_de-skew = <7>;
++		cs1_dq4_tx_de-skew = <8>;
++		cs1_dq5_rx_de-skew = <7>;
++		cs1_dq5_tx_de-skew = <8>;
++		cs1_dq6_rx_de-skew = <7>;
++		cs1_dq6_tx_de-skew = <8>;
++		cs1_dq7_rx_de-skew = <7>;
++		cs1_dq7_tx_de-skew = <8>;
++		cs1_dqs0_rx_de-skew = <6>;
++		cs1_dqs0p_tx_de-skew = <9>;
++		cs1_dqs0n_tx_de-skew = <9>;
++
++		cs1_dm1_rx_de-skew = <7>;
++		cs1_dm1_tx_de-skew = <7>;
++		cs1_dq8_rx_de-skew = <7>;
++		cs1_dq8_tx_de-skew = <8>;
++		cs1_dq9_rx_de-skew = <7>;
++		cs1_dq9_tx_de-skew = <7>;
++		cs1_dq10_rx_de-skew = <7>;
++		cs1_dq10_tx_de-skew = <8>;
++		cs1_dq11_rx_de-skew = <7>;
++		cs1_dq11_tx_de-skew = <7>;
++		cs1_dq12_rx_de-skew = <7>;
++		cs1_dq12_tx_de-skew = <8>;
++		cs1_dq13_rx_de-skew = <7>;
++		cs1_dq13_tx_de-skew = <7>;
++		cs1_dq14_rx_de-skew = <7>;
++		cs1_dq14_tx_de-skew = <8>;
++		cs1_dq15_rx_de-skew = <7>;
++		cs1_dq15_tx_de-skew = <7>;
++		cs1_dqs1_rx_de-skew = <7>;
++		cs1_dqs1p_tx_de-skew = <9>;
++		cs1_dqs1n_tx_de-skew = <9>;
++
++		cs1_dm2_rx_de-skew = <7>;
++		cs1_dm2_tx_de-skew = <8>;
++		cs1_dq16_rx_de-skew = <7>;
++		cs1_dq16_tx_de-skew = <8>;
++		cs1_dq17_rx_de-skew = <7>;
++		cs1_dq17_tx_de-skew = <8>;
++		cs1_dq18_rx_de-skew = <7>;
++		cs1_dq18_tx_de-skew = <8>;
++		cs1_dq19_rx_de-skew = <7>;
++		cs1_dq19_tx_de-skew = <8>;
++		cs1_dq20_rx_de-skew = <7>;
++		cs1_dq20_tx_de-skew = <8>;
++		cs1_dq21_rx_de-skew = <7>;
++		cs1_dq21_tx_de-skew = <8>;
++		cs1_dq22_rx_de-skew = <7>;
++		cs1_dq22_tx_de-skew = <8>;
++		cs1_dq23_rx_de-skew = <7>;
++		cs1_dq23_tx_de-skew = <8>;
++		cs1_dqs2_rx_de-skew = <6>;
++		cs1_dqs2p_tx_de-skew = <9>;
++		cs1_dqs2n_tx_de-skew = <9>;
++
++		cs1_dm3_rx_de-skew = <7>;
++		cs1_dm3_tx_de-skew = <7>;
++		cs1_dq24_rx_de-skew = <7>;
++		cs1_dq24_tx_de-skew = <8>;
++		cs1_dq25_rx_de-skew = <7>;
++		cs1_dq25_tx_de-skew = <7>;
++		cs1_dq26_rx_de-skew = <7>;
++		cs1_dq26_tx_de-skew = <7>;
++		cs1_dq27_rx_de-skew = <7>;
++		cs1_dq27_tx_de-skew = <7>;
++		cs1_dq28_rx_de-skew = <7>;
++		cs1_dq28_tx_de-skew = <7>;
++		cs1_dq29_rx_de-skew = <7>;
++		cs1_dq29_tx_de-skew = <7>;
++		cs1_dq30_rx_de-skew = <7>;
++		cs1_dq30_tx_de-skew = <7>;
++		cs1_dq31_rx_de-skew = <7>;
++		cs1_dq31_tx_de-skew = <7>;
++		cs1_dqs3_rx_de-skew = <7>;
++		cs1_dqs3p_tx_de-skew = <9>;
++		cs1_dqs3n_tx_de-skew = <9>;
++	};
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-pc-dts-ram-profile.patch b/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-pc-dts-ram-profile.patch
new file mode 100644
index 000000000000..872a1574beec
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-pc-dts-ram-profile.patch
@@ -0,0 +1,301 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tony <tonymckahan@gmail.com>
+Date: Thu, 8 Oct 2020 01:56:28 -0400
+Subject: [ARCHEOLOGY] Add files via upload
+
+> X-Git-Archeology: - Revision 8fc20a15b12561e76e92d5bd29b5afd1c62f08ac: https://github.com/armbian/build/commit/8fc20a15b12561e76e92d5bd29b5afd1c62f08ac
+> X-Git-Archeology:   Date: Thu, 08 Oct 2020 01:56:28 -0400
+> X-Git-Archeology:   From: Tony <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: Add files via upload
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 2788adccedc25f12fc9e71e01a92863d97683979: https://github.com/armbian/build/commit/2788adccedc25f12fc9e71e01a92863d97683979
+> X-Git-Archeology:   Date: Tue, 26 Jan 2021 21:22:04 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Enable DMC for Station M1 in current and dev (#2575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi | 223 ++++++++++
+ 1 file changed, 223 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi
+new file mode 100644
+index 000000000000..8b2077d086f5
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi
+@@ -0,0 +1,223 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
++ *
++ */
++#include <dt-bindings/clock/rockchip-ddr.h>
++#include <dt-bindings/memory/rk3328-dram.h>
++
++/ {
++	ddr_timing: ddr_timing {
++		/* CA de-skew, one step is 47.8ps, range 0-15 */
++		ddr3a1_ddr4a9_de-skew = <0>;
++		ddr3a0_ddr4a10_de-skew = <0>;
++		ddr3a3_ddr4a6_de-skew = <1>;
++		ddr3a2_ddr4a4_de-skew = <1>;
++		ddr3a5_ddr4a8_de-skew = <0>;
++		ddr3a4_ddr4a5_de-skew = <2>;
++		ddr3a7_ddr4a11_de-skew = <0>;
++		ddr3a6_ddr4a7_de-skew = <2>;
++		ddr3a9_ddr4a0_de-skew = <1>;
++		ddr3a8_ddr4a13_de-skew = <0>;
++		ddr3a11_ddr4a3_de-skew = <2>;
++		ddr3a10_ddr4cs0_de-skew = <0>;
++		ddr3a13_ddr4a2_de-skew = <1>;
++		ddr3a12_ddr4ba1_de-skew = <0>;
++		ddr3a15_ddr4odt0_de-skew = <0>;
++		ddr3a14_ddr4a1_de-skew = <1>;
++		ddr3ba1_ddr4a15_de-skew = <0>;
++		ddr3ba0_ddr4bg0_de-skew = <0>;
++		ddr3ras_ddr4cke_de-skew = <0>;
++		ddr3ba2_ddr4ba0_de-skew = <1>;
++		ddr3we_ddr4bg1_de-skew = <1>;
++		ddr3cas_ddr4a12_de-skew = <0>;
++		ddr3ckn_ddr4ckn_de-skew = <5>;
++		ddr3ckp_ddr4ckp_de-skew = <5>;
++		ddr3cke_ddr4a16_de-skew = <1>;
++		ddr3odt0_ddr4a14_de-skew = <0>;
++		ddr3cs0_ddr4act_de-skew = <1>;
++		ddr3reset_ddr4reset_de-skew = <0>;
++		ddr3cs1_ddr4cs1_de-skew = <0>;
++		ddr3odt1_ddr4odt1_de-skew = <0>;
++
++		/* DATA de-skew
++		 * RX one step is 25.1ps, range 0-15
++		 * TX one step is 47.8ps, range 0-15
++		 */
++		cs0_dm0_rx_de-skew = <7>;
++		cs0_dm0_tx_de-skew = <8>;
++		cs0_dq0_rx_de-skew = <7>;
++		cs0_dq0_tx_de-skew = <8>;
++		cs0_dq1_rx_de-skew = <7>;
++		cs0_dq1_tx_de-skew = <8>;
++		cs0_dq2_rx_de-skew = <7>;
++		cs0_dq2_tx_de-skew = <8>;
++		cs0_dq3_rx_de-skew = <7>;
++		cs0_dq3_tx_de-skew = <8>;
++		cs0_dq4_rx_de-skew = <7>;
++		cs0_dq4_tx_de-skew = <8>;
++		cs0_dq5_rx_de-skew = <7>;
++		cs0_dq5_tx_de-skew = <8>;
++		cs0_dq6_rx_de-skew = <7>;
++		cs0_dq6_tx_de-skew = <8>;
++		cs0_dq7_rx_de-skew = <7>;
++		cs0_dq7_tx_de-skew = <8>;
++		cs0_dqs0_rx_de-skew = <6>;
++		cs0_dqs0p_tx_de-skew = <9>;
++		cs0_dqs0n_tx_de-skew = <9>;
++
++		cs0_dm1_rx_de-skew = <7>;
++		cs0_dm1_tx_de-skew = <7>;
++		cs0_dq8_rx_de-skew = <7>;
++		cs0_dq8_tx_de-skew = <8>;
++		cs0_dq9_rx_de-skew = <7>;
++		cs0_dq9_tx_de-skew = <7>;
++		cs0_dq10_rx_de-skew = <7>;
++		cs0_dq10_tx_de-skew = <8>;
++		cs0_dq11_rx_de-skew = <7>;
++		cs0_dq11_tx_de-skew = <7>;
++		cs0_dq12_rx_de-skew = <7>;
++		cs0_dq12_tx_de-skew = <8>;
++		cs0_dq13_rx_de-skew = <7>;
++		cs0_dq13_tx_de-skew = <7>;
++		cs0_dq14_rx_de-skew = <7>;
++		cs0_dq14_tx_de-skew = <8>;
++		cs0_dq15_rx_de-skew = <7>;
++		cs0_dq15_tx_de-skew = <7>;
++		cs0_dqs1_rx_de-skew = <7>;
++		cs0_dqs1p_tx_de-skew = <9>;
++		cs0_dqs1n_tx_de-skew = <9>;
++
++		cs0_dm2_rx_de-skew = <7>;
++		cs0_dm2_tx_de-skew = <8>;
++		cs0_dq16_rx_de-skew = <7>;
++		cs0_dq16_tx_de-skew = <8>;
++		cs0_dq17_rx_de-skew = <7>;
++		cs0_dq17_tx_de-skew = <8>;
++		cs0_dq18_rx_de-skew = <7>;
++		cs0_dq18_tx_de-skew = <8>;
++		cs0_dq19_rx_de-skew = <7>;
++		cs0_dq19_tx_de-skew = <8>;
++		cs0_dq20_rx_de-skew = <7>;
++		cs0_dq20_tx_de-skew = <8>;
++		cs0_dq21_rx_de-skew = <7>;
++		cs0_dq21_tx_de-skew = <8>;
++		cs0_dq22_rx_de-skew = <7>;
++		cs0_dq22_tx_de-skew = <8>;
++		cs0_dq23_rx_de-skew = <7>;
++		cs0_dq23_tx_de-skew = <8>;
++		cs0_dqs2_rx_de-skew = <6>;
++		cs0_dqs2p_tx_de-skew = <9>;
++		cs0_dqs2n_tx_de-skew = <9>;
++
++		cs0_dm3_rx_de-skew = <7>;
++		cs0_dm3_tx_de-skew = <7>;
++		cs0_dq24_rx_de-skew = <7>;
++		cs0_dq24_tx_de-skew = <8>;
++		cs0_dq25_rx_de-skew = <7>;
++		cs0_dq25_tx_de-skew = <7>;
++		cs0_dq26_rx_de-skew = <7>;
++		cs0_dq26_tx_de-skew = <7>;
++		cs0_dq27_rx_de-skew = <7>;
++		cs0_dq27_tx_de-skew = <7>;
++		cs0_dq28_rx_de-skew = <7>;
++		cs0_dq28_tx_de-skew = <7>;
++		cs0_dq29_rx_de-skew = <7>;
++		cs0_dq29_tx_de-skew = <7>;
++		cs0_dq30_rx_de-skew = <7>;
++		cs0_dq30_tx_de-skew = <7>;
++		cs0_dq31_rx_de-skew = <7>;
++		cs0_dq31_tx_de-skew = <7>;
++		cs0_dqs3_rx_de-skew = <7>;
++		cs0_dqs3p_tx_de-skew = <9>;
++		cs0_dqs3n_tx_de-skew = <9>;
++
++		cs1_dm0_rx_de-skew = <7>;
++		cs1_dm0_tx_de-skew = <8>;
++		cs1_dq0_rx_de-skew = <7>;
++		cs1_dq0_tx_de-skew = <8>;
++		cs1_dq1_rx_de-skew = <7>;
++		cs1_dq1_tx_de-skew = <8>;
++		cs1_dq2_rx_de-skew = <7>;
++		cs1_dq2_tx_de-skew = <8>;
++		cs1_dq3_rx_de-skew = <7>;
++		cs1_dq3_tx_de-skew = <8>;
++		cs1_dq4_rx_de-skew = <7>;
++		cs1_dq4_tx_de-skew = <8>;
++		cs1_dq5_rx_de-skew = <7>;
++		cs1_dq5_tx_de-skew = <8>;
++		cs1_dq6_rx_de-skew = <7>;
++		cs1_dq6_tx_de-skew = <8>;
++		cs1_dq7_rx_de-skew = <7>;
++		cs1_dq7_tx_de-skew = <8>;
++		cs1_dqs0_rx_de-skew = <6>;
++		cs1_dqs0p_tx_de-skew = <9>;
++		cs1_dqs0n_tx_de-skew = <9>;
++
++		cs1_dm1_rx_de-skew = <7>;
++		cs1_dm1_tx_de-skew = <7>;
++		cs1_dq8_rx_de-skew = <7>;
++		cs1_dq8_tx_de-skew = <8>;
++		cs1_dq9_rx_de-skew = <7>;
++		cs1_dq9_tx_de-skew = <7>;
++		cs1_dq10_rx_de-skew = <7>;
++		cs1_dq10_tx_de-skew = <8>;
++		cs1_dq11_rx_de-skew = <7>;
++		cs1_dq11_tx_de-skew = <7>;
++		cs1_dq12_rx_de-skew = <7>;
++		cs1_dq12_tx_de-skew = <8>;
++		cs1_dq13_rx_de-skew = <7>;
++		cs1_dq13_tx_de-skew = <7>;
++		cs1_dq14_rx_de-skew = <7>;
++		cs1_dq14_tx_de-skew = <8>;
++		cs1_dq15_rx_de-skew = <7>;
++		cs1_dq15_tx_de-skew = <7>;
++		cs1_dqs1_rx_de-skew = <7>;
++		cs1_dqs1p_tx_de-skew = <9>;
++		cs1_dqs1n_tx_de-skew = <9>;
++
++		cs1_dm2_rx_de-skew = <7>;
++		cs1_dm2_tx_de-skew = <8>;
++		cs1_dq16_rx_de-skew = <7>;
++		cs1_dq16_tx_de-skew = <8>;
++		cs1_dq17_rx_de-skew = <7>;
++		cs1_dq17_tx_de-skew = <8>;
++		cs1_dq18_rx_de-skew = <7>;
++		cs1_dq18_tx_de-skew = <8>;
++		cs1_dq19_rx_de-skew = <7>;
++		cs1_dq19_tx_de-skew = <8>;
++		cs1_dq20_rx_de-skew = <7>;
++		cs1_dq20_tx_de-skew = <8>;
++		cs1_dq21_rx_de-skew = <7>;
++		cs1_dq21_tx_de-skew = <8>;
++		cs1_dq22_rx_de-skew = <7>;
++		cs1_dq22_tx_de-skew = <8>;
++		cs1_dq23_rx_de-skew = <7>;
++		cs1_dq23_tx_de-skew = <8>;
++		cs1_dqs2_rx_de-skew = <6>;
++		cs1_dqs2p_tx_de-skew = <9>;
++		cs1_dqs2n_tx_de-skew = <9>;
++
++		cs1_dm3_rx_de-skew = <7>;
++		cs1_dm3_tx_de-skew = <7>;
++		cs1_dq24_rx_de-skew = <7>;
++		cs1_dq24_tx_de-skew = <8>;
++		cs1_dq25_rx_de-skew = <7>;
++		cs1_dq25_tx_de-skew = <7>;
++		cs1_dq26_rx_de-skew = <7>;
++		cs1_dq26_tx_de-skew = <7>;
++		cs1_dq27_rx_de-skew = <7>;
++		cs1_dq27_tx_de-skew = <7>;
++		cs1_dq28_rx_de-skew = <7>;
++		cs1_dq28_tx_de-skew = <7>;
++		cs1_dq29_rx_de-skew = <7>;
++		cs1_dq29_tx_de-skew = <7>;
++		cs1_dq30_rx_de-skew = <7>;
++		cs1_dq30_tx_de-skew = <7>;
++		cs1_dq31_rx_de-skew = <7>;
++		cs1_dq31_tx_de-skew = <7>;
++		cs1_dqs3_rx_de-skew = <7>;
++		cs1_dqs3p_tx_de-skew = <9>;
++		cs1_dqs3n_tx_de-skew = <9>;
++	};
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-pc.patch b/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-pc.patch
new file mode 100644
index 000000000000..43892ae48fb7
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rk3328-roc-pc.patch
@@ -0,0 +1,593 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 12 Oct 2021 19:34:29 +0000
+Subject: enable dmc for rk3328-roc-pc
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 525 ++++++++--
+ 1 file changed, 466 insertions(+), 59 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
+index e3e3984d01d4..02047f049822 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
+@@ -1,110 +1,517 @@
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+-// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd
++/*
++ * SPDX-License-Identifier: (GPL-2.0+ or MIT)
++ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
++ */
+ 
+ /dts-v1/;
+-
++#include "rk3328-roc-pc-dram-timing.dtsi"
++#include "rk3328.dtsi"
+ #include <dt-bindings/input/input.h>
+ 
+-#include "rk3328-roc-cc.dts"
+-
+ / {
+-	model = "Firefly ROC-RK3328-PC";
++	model = "Firefly roc-rk3328-pc";
+ 	compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328";
+ 
+-	adc-keys {
+-		compatible = "adc-keys";
+-		io-channels = <&saradc 0>;
+-		io-channel-names = "buttons";
+-		keyup-threshold-microvolt = <1750000>;
++	aliases {
++		mmc0 = &sdmmc;
++		mmc1 = &emmc; /* MMC boot device */
++	};
++
++	gmac_clkin: external-gmac-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "gmac_clkin";
++		#clock-cells = <0>;
++	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,name = "rockchip,rk3328";
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&codec>;
++		};
++	};
+ 
+-		/* This button is unpopulated out of the factory. */
+-		button-recovery {
+-			label = "Recovery";
+-			linux,code = <KEY_VENDOR>;
+-			press-threshold-microvolt = <10000>;
++	hdmi-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <128>;
++		simple-audio-card,name = "rockchip,hdmi";
++		simple-audio-card,cpu {
++			sound-dai = <&i2s0>;
+ 		};
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++	};
++
++	vcc_host_5v: vcc-host-5v-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&usb30_host_drv>;
++		regulator-name = "vcc_host_5v";
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++	};
++	
++	vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_phy";
++		regulator-always-on;
++		regulator-boot-on;
+ 	};
+ 
+-	ir-receiver {
+-		compatible = "gpio-ir-receiver";
+-		gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+-		linux,rc-map-name = "rc-khadas";
++	vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&ir_int>;
++		pinctrl-0 = <&usb20_host_drv>;
++		regulator-name = "vcc_host1_5v";
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
+ 	};
+ 
+-	sdio_pwrseq: sdio-pwrseq {
+-		compatible = "mmc-pwrseq-simple";
++	vcc_sd: sdmmc-regulator {
++		compatible = "regulator-fixed";
++		gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&wifi_en>, <&wifi_host_wake>;
+-		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
++		pinctrl-0 = <&sdmmc0m1_pin>;
++		regulator-name = "vcc_sd";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc_io>;
++	};
++
++	vcc_sys: vcc-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	xin32k: xin32k {
++		compatible = "fixed-clock";
++		clock-frequency = <32768>;
++		clock-output-names = "xin32k";
++		#clock-cells = <0>;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		power_led: led-0 {
++			label = "firefly:blue:power";
++			linux,default-trigger = "heartbeat";
++			gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
++			default-state = "on";
++			mode = <0x23>;
++		};
++
++		user_led: led-1 {
++			label = "firefly:yellow:user";
++			linux,default-trigger = "mmc1";
++			gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++			mode = <0x05>;
++		};
++	};
++
++	/delete-node/ dmc-opp-table;
++	dmc_opp_table: dmc-opp-table {
++		compatible = "operating-points-v2";
++
++		opp-786000000 {
++			opp-hz = /bits/ 64 <786000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++		};
++		opp-798000000 {
++			opp-hz = /bits/ 64 <798000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++		};
++		opp-840000000 {
++			opp-hz = /bits/ 64 <840000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++		};
++		opp-924000000 {
++			status = "disabled"; // unstable
++			opp-hz = /bits/ 64 <924000000>;
++			opp-microvolt = <1100000 1100000 1200000>;
++		};
+ 	};
+ };
+ 
+-&codec {
+-	mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
++&dfi {
++	status = "okay";
++};
++
++&dmc {
++	center-supply = <&vdd_logic>;
++	ddr_timing = <&ddr_timing>;
++	status = "okay";
++};
++
++&io_domains {
++	status = "okay";
++
++	vccio1-supply = <&vcc_io>;
++	vccio2-supply = <&vcc_18emmc>;
++	vccio3-supply = <&vcc_io>;
++	vccio4-supply = <&vcc_io>;
++	vccio5-supply = <&vcc_io>;
++	vccio6-supply = <&vcc_io>;
++	pmuio-supply = <&vcc_io>;
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_arm>;
+ };
+ 
+ &gpu {
++	status = "okay";
+ 	mali-supply = <&vdd_logic>;
+ };
+ 
+-&pinctrl {
+-	ir {
+-		ir_int: ir-int {
+-			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++&gmac2phy {
++	phy-supply = <&vcc_phy>;
++	clock_in_out = "output";
++	assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
++	assigned-clock-rate = <50000000>;
++	assigned-clocks = <&cru SCLK_MAC2PHY>;
++	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
++	status = "disabled";
++};
++
++&gmac2io {
++	phy-supply = <&vcc_io>;
++	phy-mode = "rgmii";
++	clock_in_out = "input";
++	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 50000>;
++	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
++	assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmiim1_pins>;
++	snps,aal;
++	snps,rxpbl = <0x4>;
++	snps,txpbl = <0x4>;
++	tx_delay = <0x24>;
++	rx_delay = <0x18>;
++	status = "okay";
++};
++
++&display_subsystem {
++	status = "okay";
++};
++
++&hdmi {
++	#sound-dai-cells = <0>;
++	ddc-i2c-scl-high-time-ns = <9625>;
++	ddc-i2c-scl-low-time-ns = <10000>;
++	status = "okay";
++};
++
++&hdmiphy {
++	status = "okay";
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++/*&h265e {
++	status = "okay";
++};
++
++&vdec {
++	status = "okay";
++};
++
++&vepu {
++	status = "okay";
++};*/
++
++&vop {
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++/*&vpu_service {
++	status = "okay";
++};*/
++
++&i2s0 {
++	#sound-dai-cells = <0>;
++	rockchip,bclk-fs = <128>;
++	status = "okay";
++};
++
++&i2s1 {
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
++&codec {
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
++&emmc {
++	bus-width = <8>;
++	cap-mmc-highspeed;
++	mmc-hs200-1_8v;
++	supports-emmc;
++	disable-wp;
++	non-removable;
++	num-slots = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
++	status = "okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	max-frequency = <150000000>;
++	num-slots = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
++	supports-sd;
++	status = "okay";
++	vmmc-supply = <&vcc_sd>;
++};
++
++&i2c1 {
++	status = "okay";
++
++	rk805: rk805@18 {
++		compatible = "rockchip,rk805";
++		status = "okay";
++		reg = <0x18>;
++		interrupt-parent = <&gpio2>;
++		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
++		rockchip,system-power-controller;
++		wakeup-source;
++		gpio-controller;
++		#gpio-cells = <2>;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk805-clkout2";
++
++		vcc1-supply = <&vcc_sys>;
++		vcc2-supply = <&vcc_sys>;
++		vcc3-supply = <&vcc_sys>;
++		vcc4-supply = <&vcc_sys>;
++		vcc5-supply = <&vcc_io>;
++		vcc6-supply = <&vcc_io>;
++
++		rtc {
++			status = "okay";
+ 		};
+-	};
+ 
+-	sdmmcio {
+-		sdio_per_pin: sdio-per-pin {
+-			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
++		pwrkey {
++			status = "okay";
++		};
++
++		gpio {
++			status = "okay";
++		};
++
++		regulators {
++			compatible = "rk805-regulator";
++			status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-min-microvolt = <712500>;
++				regulator-max-microvolt = <1450000>;
++				regulator-ramp-delay = <12500>;
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1000000>;
++				};
++			};
++
++			vdd_arm: DCDC_REG2 {
++				regulator-name = "vdd_arm";
++				regulator-min-microvolt = <712500>;
++				regulator-max-microvolt = <1450000>;
++				regulator-ramp-delay = <12500>;
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <950000>;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_io: DCDC_REG4 {
++				regulator-name = "vcc_io";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vdd_18: LDO_REG1 {
++				regulator-name = "vdd_18";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_18emmc: LDO_REG2 {
++				regulator-name = "vcc_18emmc";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vdd_11: LDO_REG3 {
++				regulator-name = "vdd_11";
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1100000>;
++				};
++			};
+ 		};
+ 	};
++};
++
++&pinctrl {
++	pinctrl-names = "default";
++    pinctrl-0 = <&clk_32k_out>;
+ 
+-	wifi {
+-		wifi_en: wifi-en {
+-			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++    clk_32k {
++		clk_32k_out: clk-32k-out {
++			rockchip,pins =
++				<1 RK_PD4 1 &pcfg_pull_none>;
++        };
++    };
++
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins =
++				<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;	/* gpio2_a6 */
+ 		};
++	};
+ 
+-		wifi_host_wake: wifi-host-wake {
+-			rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>;
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
++				<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>,
++				<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
++				<1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++	};
+ 
+-		bt_rst: bt-rst {
+-			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
++	usb2 {
++		usb20_host_drv: usb20-host-drv {
++			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++	};
+ 
+-		bt_en: bt-en {
+-			rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++	usb3 {
++		usb30_host_drv: usb30-host-drv {
++			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+ };
+ 
+-&pmic_int_l {
+-	rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
++&u2phy {
++	status = "okay";
+ };
+ 
+-&rk805 {
+-	interrupt-parent = <&gpio0>;
+-	interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
++&u2phy_host {
++	status = "okay";
+ };
+ 
+-&saradc {
+-	vref-supply = <&vcc_18>;
++&u2phy_otg {
++	status = "okay";
++};
++
++&uart2 {
+ 	status = "okay";
+ };
+ 
+-&usb20_host_drv {
+-	rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
++&usb20_otg {
++	dr_mode = "host";
++	status = "okay";
+ };
+ 
+-&vcc_host1_5v {
+-	gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
++&usb_host0_ehci {
++	status = "okay";
+ };
+ 
+-&vcc_sdio {
+-	gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&sdio_per_pin>;
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usbdrd3 {
++	dr_mode = "host";
++	status = "okay";
++};
++
++&wdt {
++	status = "okay";
++};
++
++&saradc {
++	status = "okay";
++	vref-supply = <&vdd_18>;
++};
++
++&tsadc {
++	status = "okay";
++	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
++	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rock3a-emmc-sfc.patch b/patch/kernel/archive/rockchip64-6.10/board-rock3a-emmc-sfc.patch
new file mode 100644
index 000000000000..84e0169a4d63
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rock3a-emmc-sfc.patch
@@ -0,0 +1,54 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+Date: Wed, 3 Aug 2022 22:22:55 +0200
+Subject: [ARCHEOLOGY] update rockchip64 edge to 5.19 (#4039)
+
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 11 ++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+index e05ab11981f5..37de541cd4a1 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -753,6 +753,17 @@ &sdmmc2 {
+ 	status = "okay";
+ };
+ 
++&sfc {
++	status = "okay";
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <108000000>;
++		spi-rx-bus-width = <2>;
++		spi-tx-bus-width = <2>;
++	};
++};
++
+ &tsadc {
+ 	rockchip,hw-tshut-mode = <1>;
+ 	rockchip,hw-tshut-polarity = <0>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rock3a-usb3.patch b/patch/kernel/archive/rockchip64-6.10/board-rock3a-usb3.patch
new file mode 100644
index 000000000000..b5dfe00f774a
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rock3a-usb3.patch
@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+Date: Wed, 3 Aug 2022 22:22:55 +0200
+Subject: [ARCHEOLOGY] update rockchip64 edge to 5.19 (#4039)
+
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+index 37de541cd4a1..effcb2ee471f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -805,6 +805,7 @@ &usb_host0_ohci {
+ 
+ &usb_host0_xhci {
+ 	extcon = <&usb2phy0>;
++	dr_mode = "host";
+ 	status = "okay";
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rock64-mail-supply.patch b/patch/kernel/archive/rockchip64-6.10/board-rock64-mail-supply.patch
new file mode 100644
index 000000000000..a108ddef5e55
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rock64-mail-supply.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: tonymac32 <tonymckahan@gmail.com>
+Date: Sun, 8 Aug 2021 11:49:27 -0400
+Subject: board_rock64_mali-usb-supply
+
+Signed-off-by: tonymac32 <tonymckahan@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+index 0a27fa5271f5..1596ce3368f7 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+@@ -135,6 +135,11 @@ &emmc {
+ 	status = "okay";
+ };
+ 
++&gpu {
++	status = "okay";
++	mali-supply = <&vdd_logic>;
++};
++
+ &gmac2io {
+ 	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ 	assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpi3-enable-dmc.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpi3-enable-dmc.patch
new file mode 100644
index 000000000000..6164405eedc8
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpi3-enable-dmc.patch
@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Wed, 8 Mar 2023 11:12:22 +0100
+Subject: [ARCHEOLOGY] rockchip64: enable dmc on Rock PI E board
+
+> X-Git-Archeology: - Revision 4ea9330e5185e1c6e248af035cc615d23408316d: https://github.com/armbian/build/commit/4ea9330e5185e1c6e248af035cc615d23408316d
+> X-Git-Archeology:   Date: Wed, 08 Mar 2023 11:12:22 +0100
+> X-Git-Archeology:   From: Paolo Sabatino <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64: enable dmc on Rock PI E board
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+index 018a3a5075c7..9b3453cece85 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+@@ -15,6 +15,7 @@
+ #include <dt-bindings/pinctrl/rockchip.h>
+ 
+ #include "rk3328.dtsi"
++#include "rk3328-dram-default-timing.dtsi"
+ 
+ / {
+ 	model = "Radxa ROCK Pi E";
+@@ -388,3 +389,9 @@ &usbdrd3 {
+ &usb_host0_ehci {
+ 	status = "okay";
+ };
++
++&dmc {
++	status = "okay";
++	center-supply = <&vdd_log>;
++	ddr_timing = <&ddr_timing>;
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpi4-0003-arm64-dts-pcie.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpi4-0003-arm64-dts-pcie.patch
new file mode 100644
index 000000000000..3552a282ba37
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpi4-0003-arm64-dts-pcie.patch
@@ -0,0 +1,130 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Piotr Szczepanik <piter75@gmail.com>
+Date: Mon, 18 Nov 2019 18:23:10 +0100
+Subject: [ARCHEOLOGY] Rock Pi 4 enable PCIe in device tree for "dev" target
+ (#1624)
+
+> X-Git-Archeology: > recovered message: > * Rock Pi 4 enabled support for PCIe in device tree
+> X-Git-Archeology: > recovered message: > * Rockchip64-dev added possibility to enable PCIe Gen2 speed via overlay
+> X-Git-Archeology: - Revision b3bb9345439250d8247f0e24a8e1ef6290b2c279: https://github.com/armbian/build/commit/b3bb9345439250d8247f0e24a8e1ef6290b2c279
+> X-Git-Archeology:   Date: Mon, 18 Nov 2019 18:23:10 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Rock Pi 4 enable PCIe in device tree for "dev" target (#1624)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3
+> X-Git-Archeology:   Date: Tue, 19 Nov 2019 23:25:39 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Remove K<4, change branches, new features (#1586)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 812245def37a695bce9e7ece148b2920d82c8b37: https://github.com/armbian/build/commit/812245def37a695bce9e7ece148b2920d82c8b37
+> X-Git-Archeology:   Date: Sat, 18 Jul 2020 23:07:01 +0200
+> X-Git-Archeology:   From: Werner <EvilOlaf@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Move rockchip/64 current to 5.7.y (#2099)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070
+> X-Git-Archeology:   Date: Sun, 13 Dec 2020 22:13:03 -0500
+> X-Git-Archeology:   From: tonymac32 <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: [ rockchip64 ] Clean up patchset
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 091d91468e383c3d12a03a465be36b76112ce798: https://github.com/armbian/build/commit/091d91468e383c3d12a03a465be36b76112ce798
+> X-Git-Archeology:   Date: Sun, 17 Jan 2021 19:07:59 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switched rockchip64-current to 5.10.y (and synced -dev config/patches) (#2546)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 44c4cdf8653104bc395c504d7611d819906ff69b: https://github.com/armbian/build/commit/44c4cdf8653104bc395c504d7611d819906ff69b
+> X-Git-Archeology:   Date: Fri, 30 Dec 2022 21:17:33 +0100
+> X-Git-Archeology:   From: Konstantin Litvinov <koftikes@gmail.com>
+> X-Git-Archeology:   Subject: Fixed issue with NVMe identification in rk3399-rock-pi-4.dts (#4627)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 44c95b7b0a64486a85f23c5630842ea1b877a695: https://github.com/armbian/build/commit/44c95b7b0a64486a85f23c5630842ea1b877a695
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:01 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: fix unidiff warning from patches of rockchip64-6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+index f2279aa6ca9e..9d1b2129431c 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+@@ -112,6 +112,8 @@ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ 		regulator-name = "vcc3v3_pcie";
+ 		regulator-always-on;
+ 		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
+ 
+@@ -528,9 +530,11 @@ &pcie0 {
+ 	num-lanes = <4>;
+ 	pinctrl-0 = <&pcie_clkreqnb_cpm>;
+ 	pinctrl-names = "default";
++	vpcie12v-supply = <&vcc12v_dcin>;
+ 	vpcie0v9-supply = <&vcc_0v9>;
+ 	vpcie1v8-supply = <&vcc_1v8>;
+ 	vpcie3v3-supply = <&vcc3v3_pcie>;
++	bus-scan-delay-ms = <1500>;
+ 	status = "okay";
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0001-arm64-dts.patch.disabled b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0001-arm64-dts.patch.disabled
new file mode 100644
index 000000000000..fe2d91d22ffe
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0001-arm64-dts.patch.disabled
@@ -0,0 +1,408 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: brentr <brent@mbari.org>
+Date: Fri, 23 Dec 2022 21:57:53 +0100
+Subject: [ARCHEOLOGY] Rockpis devtree mainlined (#4603)
+
+> X-Git-Archeology: > recovered message: > * moved rockpro64 patch out of rockpis patch sequence
+> X-Git-Archeology: > recovered message: > It had been misnamed
+> X-Git-Archeology: > recovered message: > * patch new mainline devtree for Rock Pi-S instead of overwritting it.
+> X-Git-Archeology: > recovered message: > Also restores lost bluetooth compatibility items on UART4
+> X-Git-Archeology: - Revision 588c2ec17e709dec19304fa50522459702ebfadd: https://github.com/armbian/build/commit/588c2ec17e709dec19304fa50522459702ebfadd
+> X-Git-Archeology:   Date: Fri, 23 Dec 2022 21:57:53 +0100
+> X-Git-Archeology:   From: brentr <brent@mbari.org>
+> X-Git-Archeology:   Subject: Rockpis devtree mainlined (#4603)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 240 +++++++---
+ 1 file changed, 164 insertions(+), 76 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+index e9810d2f0407..0d917658d24a 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+@@ -2,6 +2,7 @@
+ /*
+  * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
+  * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
++ * Revised: 2022 Brent Roman <brent@mbari.org>
+  */
+ 
+ /dts-v1/;
+@@ -11,12 +12,6 @@ / {
+ 	model = "Radxa ROCK Pi S";
+ 	compatible = "radxa,rockpis", "rockchip,rk3308";
+ 
+-	aliases {
+-		ethernet0 = &gmac;
+-		mmc0 = &emmc;
+-		mmc1 = &sdmmc;
+-	};
+-
+ 	chosen {
+ 		stdout-path = "serial0:1500000n8";
+ 	};
+@@ -27,48 +22,106 @@ leds {
+ 		pinctrl-0 = <&green_led>, <&heartbeat_led>;
+ 
+ 		green-led {
+ 			color = <LED_COLOR_ID_GREEN>;
+-			default-state = "on";
+ 			function = LED_FUNCTION_POWER;
+-			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ 			label = "rockpis:green:power";
++			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ 			linux,default-trigger = "default-on";
++			default-state = "on";
+ 		};
+ 
+ 		blue-led {
+ 			color = <LED_COLOR_ID_BLUE>;
+-			default-state = "on";
+ 			function = LED_FUNCTION_HEARTBEAT;
+-			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ 			label = "rockpis:blue:user";
++			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ 			linux,default-trigger = "heartbeat";
++			default-state = "on";
+ 		};
+ 	};
+ 
++	acodec-sound {
++			compatible = "simple-audio-card";
++			simple-audio-card,format = "i2s";
++			simple-audio-card,name = "rockchip,rk3308-acodec";
++			simple-audio-card,mclk-fs = <256>;
++			simple-audio-card,codec-hp-det;
++			simple-audio-card,widgets =
++				"Headphone", "Headphones";
++			simple-audio-card,cpu {
++				sound-dai = <&i2s_8ch_2>;
++			};
++			simple-audio-card,codec {
++				sound-dai = <&codec>;
++			};
++	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,name = "i2s_8ch_0";
++
++		simple-audio-card,dai-link@1 {
++			format = "i2s";
++			cpu {
++				sound-dai = <&i2s_8ch_0>;
++			};
++
++			codec {
++				sound-dai = <&pcm5102a>;
++			};
++		};
++	};
++
++	pcm5102a: pcm5102a {
++			#sound-dai-cells = <0>;
++			compatible = "ti,pcm5102a";
++			pcm510x,format = "i2s";
++	};
++
+ 	sdio_pwrseq: sdio-pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		pinctrl-0 = <&wifi_enable_h>;
+ 		pinctrl-names = "default";
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
+ 		reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ 	};
+ 
+-	vcc_1v8: vcc-1v8 {
++	vcc5v0_sys: vcc5v0-sys {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vcc_1v8";
++		regulator-name = "vcc5v0_sys";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		regulator-min-microvolt = <1800000>;
+-		regulator-max-microvolt = <1800000>;
+-		vin-supply = <&vcc_io>;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
+ 	};
+ 
+-	vcc_io: vcc-io {
++	vdd_core: vdd-core {
++		compatible = "pwm-regulator";
++		pwms = <&pwm0 0 5000 1>;
++		regulator-name = "vdd_core";
++		regulator-min-microvolt = <827000>;
++		regulator-max-microvolt = <1340000>;
++		regulator-init-microvolt = <1015000>;
++		regulator-settling-time-up-us = <250>;
++		regulator-always-on;
++		regulator-boot-on;
++		pwm-supply = <&vcc5v0_sys>;
++	};
++
++	vdd_log: vdd-log {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vcc_io";
++		regulator-name = "vdd_log";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
++		regulator-min-microvolt = <1050000>;
++		regulator-max-microvolt = <1050000>;
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
+ 
+@@ -78,49 +131,50 @@ vcc_ddr: vcc-ddr {
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
+ 
+-	vcc5v0_otg: vcc5v0-otg {
++	vcc_1v8: vcc-1v8 {
+ 		compatible = "regulator-fixed";
+-		enable-active-high;
+-		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&otg_vbus_drv>;
+-		regulator-name = "vcc5v0_otg";
++		regulator-name = "vcc_1v8";
+ 		regulator-always-on;
+-		vin-supply = <&vcc5v0_sys>;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_io>;
+ 	};
+ 
+-	vcc5v0_sys: vcc5v0-sys {
++	vcc_io: vcc-io {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vcc5v0_sys";
++		regulator-name = "vcc_io";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		regulator-min-microvolt = <5000000>;
+-		regulator-max-microvolt = <5000000>;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
+ 	};
+ 
+-	vdd_core: vdd-core {
+-		compatible = "pwm-regulator";
+-		pwms = <&pwm0 0 5000 1>;
+-		pwm-supply = <&vcc5v0_sys>;
+-		regulator-name = "vdd_core";
+-		regulator-min-microvolt = <827000>;
+-		regulator-max-microvolt = <1340000>;
+-		regulator-settling-time-up-us = <250>;
++  vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_phy";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+ 	};
+ 
+-	vdd_log: vdd-log {
++	vcc5v0_otg: vcc5v0-otg {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vdd_log";
++		regulator-name = "vcc5v0_otg";
+ 		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <1050000>;
+-		regulator-max-microvolt = <1050000>;
++		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++		pinctrl-names = "default";
++		pinctrl-0 = <&otg_vbus_drv>;
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
+ };
+ 
++&codec {
++	status = "okay";
++	#sound-dai-cells = <0>;
++};
++
+ &cpu0 {
+ 	cpu-supply = <&vdd_core>;
+ };
+@@ -132,13 +132,43 @@
+ 	non-removable;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+-	vmmc-supply = <&vcc_io>;
+ 	status = "okay";
+ };
+ 
++&sdmmc {
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
++	card-detect-delay = <800>;
++	status = "okay";
++};
++
++&sdio {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	no-mmc;
++	status = "okay";
++
++	rtl8723ds: wifi@1 {
++			interrupt-parent = <&gpio0>;
++			interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
++			interrupt-names = "host-wake";
++			pinctrl-names = "default";
++			pinctrl-0 = <&wifi_host_wake>;
++	};
++};
++
+ &gmac {
++	phy-supply = <&vcc_phy>;
+ 	clock_in_out = "output";
+-	phy-supply = <&vcc_io>;
++	assigned-clocks = <&cru SCLK_MAC>;
++	assigned-clock-parents = <&cru SCLK_MAC_SRC>;
+ 	snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ 	snps,reset-active-low;
+ 	snps,reset-delays-us = <0 50000 50000>;
+@@ -207,8 +237,16 @@
+ 		"", "", "", "", "", "", "", "";
+ };
+ 
+-&i2c1 {
+-	status = "okay";
++&i2s_8ch_0 {
++	assigned-clocks = <&cru SCLK_I2S0_8CH_RX>;
++	assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>;
++	rockchip,clk-trcm = <1>;
++	#sound-dai-cells = <0>;
++};
++
++&i2s_8ch_2 {
++ 	status = "okay";
++	#sound-dai-cells = <0>;
+ };
+ 
+ &pinctrl {
+@@ -171,7 +262,9 @@ sdio-pwrseq {
+ 		wifi_enable_h: wifi-enable-h {
+ 			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++	};
+ 
++	wifi {
+ 		wifi_host_wake: wifi-host-wake {
+ 			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ 		};
+@@ -188,42 +281,29 @@ &saradc {
+ 	status = "okay";
+ };
+ 
+-&sdio {
+-	#address-cells = <1>;
+-	#size-cells = <0>;
+-	cap-sd-highspeed;
+-	cap-sdio-irq;
+-	keep-power-in-suspend;
+-	max-frequency = <1000000>;
+-	mmc-pwrseq = <&sdio_pwrseq>;
+-	non-removable;
+-	sd-uhs-sdr104;
++&tsadc {
++	rockchip,hw-tshut-mode = <0>;		/* 0:CRU */
++	rockchip,hw-tshut-polarity = <1>;	/* 1:HIGH */
+ 	status = "okay";
+ };
+ 
+-&sdmmc {
+-	cap-sd-highspeed;
++&i2c1 {
+ 	status = "okay";
+ };
+ 
+-&u2phy {
+-	status = "okay";
+-
+-	u2phy_host: host-port {
+-		phy-supply = <&vcc5v0_otg>;
+-		status = "okay";
+-	};
+-
+-	u2phy_otg: otg-port {
+-		phy-supply = <&vcc5v0_otg>;
+-		status = "okay";
+-	};
++&spi2 {
++//	status = "okay";  //conflicts with UART2
++	max-freq = <10000000>;
+ };
+ 
+ &uart0 {
+ 	status = "okay";
+ };
+ 
++&uart2 {
++	status = "okay";
++};
++
+ &uart4 {
+ 	status = "okay";
+ 
+@@ -234,19 +314,27 @@ bluetooth {
+ 	};
+ };
+ 
+-&usb_host_ehci {
++&u2phy {
+ 	status = "okay";
++
++	u2phy_host: host-port {
++		phy-supply = <&vcc5v0_otg>;
++		status = "okay";
++	};
++
++	u2phy_otg: otg-port {
++		status = "okay";
++	};
+ };
+ 
+-&usb_host_ohci {
++&usb20_otg {
+ 	status = "okay";
+ };
+ 
+-&usb20_otg {
+-	dr_mode = "peripheral";
++&usb_host_ehci {
+ 	status = "okay";
+ };
+ 
+-&wdt {
++&usb_host_ohci{
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0005-arm64-dts-rk3308-Add-gmac-node-at-dtsi-level.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0005-arm64-dts-rk3308-Add-gmac-node-at-dtsi-level.patch
new file mode 100644
index 000000000000..3db2657a852c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0005-arm64-dts-rk3308-Add-gmac-node-at-dtsi-level.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ashthespy <ashthespy@gmail.com>
+Date: Thu, 16 Jan 2020 21:13:09 +0100
+Subject: arm64: dts: rk3308: Add mac node at dtsi level
+
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+index 2ae4bb7d5e62..2a6f41e2281f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -24,6 +24,7 @@ aliases {
+ 		i2c1 = &i2c1;
+ 		i2c2 = &i2c2;
+ 		i2c3 = &i2c3;
++		ethernet0 = &gmac;
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
+ 		serial2 = &uart2;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0007-arm64-dts-rockchip-add-cpu-s-thermal-config-for-rk33.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0007-arm64-dts-rockchip-add-cpu-s-thermal-config-for-rk33.patch
new file mode 100644
index 000000000000..2d86ad6c3580
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0007-arm64-dts-rockchip-add-cpu-s-thermal-config-for-rk33.patch
@@ -0,0 +1,87 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ashthespy <ashthespy@gmail.com>
+Date: Fri, 17 Jan 2020 15:57:53 +0100
+Subject: arm64: dts: rockchip: add cpu's thermal config for rk3308
+
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 64 ++++++++++
+ 1 file changed, 64 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+index 2a6f41e2281f..fde32008902a 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -552,6 +552,70 @@ saradc: saradc@ff1e0000 {
+ 		status = "disabled";
+ 	};
+ 
++	thermal_zones: thermal-zones {
++
++		soc_thermal: soc-thermal {
++			polling-delay-passive = <20>;
++			polling-delay = <1000>;
++			sustainable-power = <300>;
++
++			thermal-sensors = <&tsadc 1>;
++
++			trips {
++				threshold: trip-point-0 {
++					temperature = <70000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				target: trip-point-1 {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				soc_crit: soc-crit {
++					temperature = <115000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&target>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++					contribution = <4096>;
++				};
++			};
++
++		};
++
++		logic_thermal: logic-thermal {
++			polling-delay-passive = <100>; /* milliseconds */
++			polling-delay = <1000>; /* milliseconds */
++
++			thermal-sensors = <&tsadc 0>;
++		};
++	};
++
++	tsadc: tsadc@ff1f0000 {
++		compatible = "rockchip,rk3308-tsadc";
++		reg = <0x0 0xff1f0000 0x0 0x100>;
++		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
++		rockchip,grf = <&grf>;
++		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
++		clock-names = "tsadc", "apb_pclk";
++		assigned-clocks = <&cru SCLK_TSADC>;
++		assigned-clock-rates = <50000>;
++		resets = <&cru SRST_TSADC>;
++		reset-names = "tsadc-apb";
++		pinctrl-names = "gpio", "otpout";
++		pinctrl-0 = <&tsadc_otp_pin>;
++		pinctrl-1 = <&tsadc_otp_out>;
++		#thermal-sensor-cells = <1>;
++		rockchip,hw-tshut-temp = <120000>;
++		status = "disabled";
++	};
++
+ 	dmac0: dma-controller@ff2c0000 {
+ 		compatible = "arm,pl330", "arm,primecell";
+ 		reg = <0x0 0xff2c0000 0x0 0x4000>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0008-thermal-rockchip-add-tsadc-support-for-rk3308.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0008-thermal-rockchip-add-tsadc-support-for-rk3308.patch
new file mode 100644
index 000000000000..3902d61c8fba
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0008-thermal-rockchip-add-tsadc-support-for-rk3308.patch
@@ -0,0 +1,71 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Rocky Hao <rocky.hao@rock-chips.com>
+Date: Fri, 9 Mar 2018 17:36:39 +0800
+Subject: thermal: rockchip: add tsadc support for rk3308
+
+Change-Id: Ibf1782ca471c8ad4b14d6fd64eeb123181903adc
+Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
+---
+ Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml |  1 +
+ drivers/thermal/rockchip_thermal.c                              | 26 ++++++++++
+ 2 files changed, 27 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml
+index 55f8ec0bec01..c822baf04aed 100644
+--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml
++++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml
+@@ -15,6 +15,7 @@ properties:
+       - rockchip,px30-tsadc
+       - rockchip,rk3228-tsadc
+       - rockchip,rk3288-tsadc
++      - rockchip,rk3308-tsadc
+       - rockchip,rk3328-tsadc
+       - rockchip,rk3368-tsadc
+       - rockchip,rk3399-tsadc
+diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
+index 77231a9d28ff..13182e2a3142 100644
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -1060,6 +1060,28 @@ static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs,
+ 	writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
+ }
+ 
++static const struct rockchip_tsadc_chip rk3308_tsadc_data = {
++	.chn_num = 2, /* 2 channels for tsadc */
++
++	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
++	.tshut_temp = 95000,
++
++	.initialize = rk_tsadcv4_initialize,
++	.irq_ack = rk_tsadcv3_irq_ack,
++	.control = rk_tsadcv3_control,
++	.get_temp = rk_tsadcv2_get_temp,
++	.set_alarm_temp = rk_tsadcv2_alarm_temp,
++	.set_tshut_temp = rk_tsadcv2_tshut_temp,
++	.set_tshut_mode = rk_tsadcv2_tshut_mode,
++
++	.table = {
++		.id = rk3328_code_table,
++		.length = ARRAY_SIZE(rk3328_code_table),
++		.data_mask = TSADCV2_DATA_MASK,
++		.mode = ADC_INCREMENT,
++	},
++};
++
+ static const struct rockchip_tsadc_chip px30_tsadc_data = {
+ 	/* cpu, gpu */
+ 	.chn_offset = 0,
+@@ -1321,6 +1343,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = {
+ 		.compatible = "rockchip,rk3288-tsadc",
+ 		.data = (void *)&rk3288_tsadc_data,
+ 	},
++	{
++		.compatible = "rockchip,rk3308-tsadc",
++		.data = (void *)&rk3308_tsadc_data,
++	},
+ 	{
+ 		.compatible = "rockchip,rk3328-tsadc",
+ 		.data = (void *)&rk3328_tsadc_data,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch.disabled b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch.disabled
new file mode 100644
index 000000000000..e4c527331216
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch.disabled
@@ -0,0 +1,126 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ashthespy <ashthespy@gmail.com>
+Date: Fri, 17 Jan 2020 16:22:13 +0100
+Subject: arm64: dts: rockchip: add i2s_8ch for rk3308
+
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 103 ++++++++++
+ 1 file changed, 103 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+index fde32008902a..1567758ca90e 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -638,6 +638,109 @@ dmac1: dma-controller@ff2d0000 {
+ 		#dma-cells = <1>;
+ 	};
+ 
++	i2s_8ch_0: i2s@ff300000 {
++		compatible = "rockchip,rk3308-i2s-tdm";
++		reg = <0x0 0xff300000 0x0 0x1000>;
++		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>,
++			 <&cru SCLK_I2S0_8CH_TX_SRC>,
++			 <&cru SCLK_I2S0_8CH_RX_SRC>,
++			 <&cru PLL_VPLL0>,
++			 <&cru PLL_VPLL1>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk",
++						"mclk_tx_src", "mclk_rx_src",
++						"mclk_root0", "mclk_root1";
++		dmas = <&dmac1 0>, <&dmac1 1>;
++		dma-names = "tx", "rx";
++		resets = <&cru SRST_I2S0_8CH_TX_M>, <&cru SRST_I2S0_8CH_RX_M>;
++		reset-names = "tx-m", "rx-m";
++		rockchip,cru = <&cru>;
++		rockchip,grf = <&grf>;
++		rockchip,mclk-calibrate;
++		pinctrl-names = "default";
++		pinctrl-0 = <&i2s_8ch_0_sclktx
++					 &i2s_8ch_0_sclkrx
++					 &i2s_8ch_0_lrcktx
++					 &i2s_8ch_0_lrckrx
++					 &i2s_8ch_0_sdi0
++					 &i2s_8ch_0_sdi1
++					 &i2s_8ch_0_sdi2
++					 &i2s_8ch_0_sdi3
++					 &i2s_8ch_0_sdo0
++					 &i2s_8ch_0_sdo1
++					 &i2s_8ch_0_sdo2
++					 &i2s_8ch_0_sdo3
++					 &i2s_8ch_0_mclk>;
++		status = "disabled";
++	};
++
++	i2s_8ch_1: i2s@ff310000 {
++		compatible = "rockchip,rk3308-i2s-tdm";
++		reg = <0x0 0xff310000 0x0 0x1000>;
++		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru SCLK_I2S1_8CH_TX>, <&cru SCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>,
++			 <&cru SCLK_I2S1_8CH_TX_SRC>,
++			 <&cru SCLK_I2S1_8CH_RX_SRC>,
++			 <&cru PLL_VPLL0>,
++			 <&cru PLL_VPLL1>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk",
++						"mclk_tx_src", "mclk_rx_src",
++						"mclk_root0", "mclk_root1";
++		dmas = <&dmac1 2>, <&dmac1 3>;
++		dma-names = "tx", "rx";
++		resets = <&cru SRST_I2S1_8CH_TX_M>, <&cru SRST_I2S1_8CH_RX_M>;
++		reset-names = "tx-m", "rx-m";
++		rockchip,cru = <&cru>;
++		rockchip,grf = <&grf>;
++		rockchip,mclk-calibrate;
++		rockchip,io-multiplex;
++		status = "disabled";
++	};
++
++	i2s_8ch_2: i2s@ff320000 {
++		compatible = "rockchip,rk3308-i2s-tdm";
++		reg = <0x0 0xff320000 0x0 0x1000>;
++		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru SCLK_I2S2_8CH_TX>, <&cru SCLK_I2S2_8CH_RX>, <&cru HCLK_I2S2_8CH>,
++			 <&cru SCLK_I2S2_8CH_TX_SRC>,
++			 <&cru SCLK_I2S2_8CH_RX_SRC>,
++			 <&cru PLL_VPLL0>,
++			 <&cru PLL_VPLL1>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk",
++						"mclk_tx_src", "mclk_rx_src",
++						"mclk_root0", "mclk_root1";
++		dmas = <&dmac1 4>, <&dmac1 5>;
++		dma-names = "tx", "rx";
++		resets = <&cru SRST_I2S2_8CH_TX_M>, <&cru SRST_I2S2_8CH_RX_M>;
++		reset-names = "tx-m", "rx-m";
++		rockchip,cru = <&cru>;
++		rockchip,grf = <&grf>;
++		rockchip,mclk-calibrate;
++		status = "disabled";
++	};
++
++	i2s_8ch_3: i2s@ff330000 {
++		compatible = "rockchip,rk3308-i2s-tdm";
++		reg = <0x0 0xff330000 0x0 0x1000>;
++		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru SCLK_I2S3_8CH_TX>, <&cru SCLK_I2S3_8CH_RX>, <&cru HCLK_I2S3_8CH>,
++			 <&cru SCLK_I2S3_8CH_TX_SRC>,
++			 <&cru SCLK_I2S3_8CH_RX_SRC>,
++			 <&cru PLL_VPLL0>,
++			 <&cru PLL_VPLL1>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk",
++						"mclk_tx_src", "mclk_rx_src",
++						"mclk_root0", "mclk_root1";
++		dmas = <&dmac1 7>;
++		dma-names = "rx";
++		resets = <&cru SRST_I2S3_8CH_TX_M>, <&cru SRST_I2S3_8CH_RX_M>;
++		reset-names = "tx-m", "rx-m";
++		rockchip,cru = <&cru>;
++		rockchip,grf = <&grf>;
++		rockchip,mclk-calibrate;
++		status = "disabled";
++	};
++	
+ 	i2s_2ch_0: i2s@ff350000 {
+ 		compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
+ 		reg = <0x0 0xff350000 0x0 0x1000>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0012-arm64-dts-rk3308-Add-rk-timer-rtc.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0012-arm64-dts-rk3308-Add-rk-timer-rtc.patch
new file mode 100644
index 000000000000..e8ecc0a02a2f
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0012-arm64-dts-rk3308-Add-rk-timer-rtc.patch
@@ -0,0 +1,32 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ashthespy <ashthespy@gmail.com>
+Date: Fri, 17 Jan 2020 17:12:51 +0100
+Subject: arm64: dts: rk3308: Add rk-timer-rtc
+
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 11 +++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+index 1567758ca90e..291f011800b2 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -540,6 +540,15 @@ rktimer: rktimer@ff1a0000 {
+ 		clock-names = "pclk", "timer";
+ 	};
+ 
++	rk_timer_rtc: rk-timer-rtc@ff1a0020 {
++		compatible = "rockchip,rk3308-timer-rtc";
++		reg = <0x0 0xff1a0020 0x0 0x20>;
++		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
++		clock-names = "pclk", "timer";
++		status = "disabled";
++	};
++		
+ 	saradc: saradc@ff1e0000 {
+ 		compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
+ 		reg = <0x0 0xff1e0000 0x0 0x100>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch.disabled b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch.disabled
new file mode 100644
index 000000000000..30bfaeaf504a
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch.disabled
@@ -0,0 +1,2638 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Xing Zheng <zhengxing@rock-chips.com>
+Date: Sun, 11 Mar 2018 11:37:28 +0800
+Subject: ASoC: codecs: Add RK3308 internal codec driver
+
+This adds support for the RK3308 audio codec.
+
+Change-Id: Ieccdebaa27f4a46f6de9406046a6e02e20398013
+Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
+---
+ sound/soc/codecs/Kconfig        |    5 +
+ sound/soc/codecs/Makefile       |    2 +
+ sound/soc/codecs/rk3308_codec.c | 1604 ++++++++++
+ sound/soc/codecs/rk3308_codec.h |  960 ++++++
+ 4 files changed, 2571 insertions(+)
+
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index f1e1dbc509f6..8ce353dad530 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -177,6 +177,7 @@ config SND_SOC_ALL_CODECS
+ 	imply SND_SOC_PCM512x_I2C
+ 	imply SND_SOC_PCM512x_SPI
+ 	imply SND_SOC_PEB2466
++	imply SND_SOC_RK3308
+ 	imply SND_SOC_RK3328
+ 	imply SND_SOC_RK817
+ 	imply SND_SOC_RT274
+@@ -1370,6 +1371,10 @@ config SND_SOC_PEB2466
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called snd-soc-peb2466.
+ 
++config SND_SOC_RK3308
++	select REGMAP_MMIO
++	tristate "Rockchip RK3308 CODEC"
++
+ config SND_SOC_RK3328
+ 	tristate "Rockchip RK3328 audio CODEC"
+ 	select REGMAP_MMIO
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index a87e56938ce5..8f539b13864d 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -199,6 +199,7 @@ snd-soc-pcm512x-objs := pcm512x.o
+ snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o
+ snd-soc-pcm512x-spi-objs := pcm512x-spi.o
+ snd-soc-peb2466-objs := peb2466.o
++snd-soc-rk3308-objs := rk3308_codec.o
+ snd-soc-rk3328-objs := rk3328_codec.o
+ snd-soc-rk817-objs := rk817_codec.o
+ snd-soc-rl6231-objs := rl6231.o
+@@ -580,6 +581,7 @@ obj-$(CONFIG_SND_SOC_PCM512x)	+= snd-soc-pcm512x.o
+ obj-$(CONFIG_SND_SOC_PCM512x_I2C)	+= snd-soc-pcm512x-i2c.o
+ obj-$(CONFIG_SND_SOC_PCM512x_SPI)	+= snd-soc-pcm512x-spi.o
+ obj-$(CONFIG_SND_SOC_PEB2466)	+= snd-soc-peb2466.o
++obj-$(CONFIG_SND_SOC_RK3308)	+= snd-soc-rk3308.o
+ obj-$(CONFIG_SND_SOC_RK3328)	+= snd-soc-rk3328.o
+ obj-$(CONFIG_SND_SOC_RK817)	+= snd-soc-rk817.o
+ obj-$(CONFIG_SND_SOC_RL6231)	+= snd-soc-rl6231.o
+diff --git a/sound/soc/codecs/rk3308_codec.c b/sound/soc/codecs/rk3308_codec.c
+new file mode 100644
+index 000000000000..106f09738dd0
+--- /dev/null
++++ b/sound/soc/codecs/rk3308_codec.c
+@@ -0,0 +1,1604 @@
++/*
++ * rk3308_codec.c -- RK3308 ALSA Soc Audio Driver
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/rockchip/grf.h>
++#include <linux/version.h>
++#include <sound/core.h>
++#include <sound/dmaengine_pcm.h>
++#include <sound/initval.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/tlv.h>
++
++#include "rk3308_codec.h"
++
++struct rk3308_codec_priv {
++	const struct device *plat_dev;
++	struct device dev;
++	struct reset_control *reset;
++	struct regmap *regmap;
++	struct clk *pclk;
++	struct gpio_desc *spk_ctl_gpio;
++	int adc_ch;			/* To select ADCs for channel */
++	int adc_ch0_using_linein;
++};
++
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_gain_tlv,
++				  -1800, 150, 2850);
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_max_gain_tlv,
++				  -1350, 600, 2850);
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_min_gain_tlv,
++				  -1800, 600, 2400);
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_mic_gain_tlv,
++				  0, 600, 3000);
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_alc_gain_tlv,
++				  -1800, 150, 2850);
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_gain_tlv,
++				  0, 150, 600);
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpout_gain_tlv,
++				  -3900, 150, 600);
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpmix_gain_tlv,
++				  -600, 600, 0);
++
++static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = {
++	/* ALC AGC Channel*/
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Volume",
++			     RK3308_ALC_L_DIG_CON03(0),
++			     RK3308_ALC_R_DIG_CON03(0),
++			     RK3308_AGC_PGA_GAIN_SFT,
++			     RK3308_AGC_PGA_GAIN_NDB_18,
++			     RK3308_AGC_PGA_GAIN_PDB_28_5,
++			     0, rk3308_codec_alc_agc_ch_gain_tlv),
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Volume",
++			     RK3308_ALC_L_DIG_CON03(1),
++			     RK3308_ALC_R_DIG_CON03(1),
++			     RK3308_AGC_PGA_GAIN_SFT,
++			     RK3308_AGC_PGA_GAIN_NDB_18,
++			     RK3308_AGC_PGA_GAIN_PDB_28_5,
++			     0, rk3308_codec_alc_agc_ch_gain_tlv),
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Volume",
++			     RK3308_ALC_L_DIG_CON03(2),
++			     RK3308_ALC_R_DIG_CON03(2),
++			     RK3308_AGC_PGA_GAIN_SFT,
++			     RK3308_AGC_PGA_GAIN_NDB_18,
++			     RK3308_AGC_PGA_GAIN_PDB_28_5,
++			     0, rk3308_codec_alc_agc_ch_gain_tlv),
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Volume",
++			     RK3308_ALC_L_DIG_CON03(3),
++			     RK3308_ALC_R_DIG_CON03(3),
++			     RK3308_AGC_PGA_GAIN_SFT,
++			     RK3308_AGC_PGA_GAIN_NDB_18,
++			     RK3308_AGC_PGA_GAIN_PDB_28_5,
++			     0, rk3308_codec_alc_agc_ch_gain_tlv),
++
++	/* ALC AGC MAX */
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Max Volume",
++			     RK3308_ALC_L_DIG_CON09(0),
++			     RK3308_ALC_R_DIG_CON09(0),
++			     RK3308_AGC_MAX_GAIN_PGA_SFT,
++			     RK3308_AGC_MAX_GAIN_PGA_NDB_13_5,
++			     RK3308_AGC_MAX_GAIN_PGA_PDB_28_5,
++			     0, rk3308_codec_alc_agc_ch_max_gain_tlv),
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Max Volume",
++			     RK3308_ALC_L_DIG_CON09(1),
++			     RK3308_ALC_R_DIG_CON09(1),
++			     RK3308_AGC_MAX_GAIN_PGA_SFT,
++			     RK3308_AGC_MAX_GAIN_PGA_NDB_13_5,
++			     RK3308_AGC_MAX_GAIN_PGA_PDB_28_5,
++			     0, rk3308_codec_alc_agc_ch_max_gain_tlv),
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Max Volume",
++			     RK3308_ALC_L_DIG_CON09(2),
++			     RK3308_ALC_R_DIG_CON09(2),
++			     RK3308_AGC_MAX_GAIN_PGA_SFT,
++			     RK3308_AGC_MAX_GAIN_PGA_NDB_13_5,
++			     RK3308_AGC_MAX_GAIN_PGA_PDB_28_5,
++			     0, rk3308_codec_alc_agc_ch_max_gain_tlv),
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Max Volume",
++			     RK3308_ALC_L_DIG_CON09(3),
++			     RK3308_ALC_R_DIG_CON09(3),
++			     RK3308_AGC_MAX_GAIN_PGA_SFT,
++			     RK3308_AGC_MAX_GAIN_PGA_NDB_13_5,
++			     RK3308_AGC_MAX_GAIN_PGA_PDB_28_5,
++			     0, rk3308_codec_alc_agc_ch_max_gain_tlv),
++
++	/* ALC AGC MIN */
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Min Volume",
++			     RK3308_ALC_L_DIG_CON09(0),
++			     RK3308_ALC_R_DIG_CON09(0),
++			     RK3308_AGC_MIN_GAIN_PGA_SFT,
++			     RK3308_AGC_MIN_GAIN_PGA_NDB_18,
++			     RK3308_AGC_MIN_GAIN_PGA_PDB_24,
++			     0, rk3308_codec_alc_agc_ch_min_gain_tlv),
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Min Volume",
++			     RK3308_ALC_L_DIG_CON09(1),
++			     RK3308_ALC_R_DIG_CON09(1),
++			     RK3308_AGC_MIN_GAIN_PGA_SFT,
++			     RK3308_AGC_MIN_GAIN_PGA_NDB_18,
++			     RK3308_AGC_MIN_GAIN_PGA_PDB_24,
++			     0, rk3308_codec_alc_agc_ch_min_gain_tlv),
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Min Volume",
++			     RK3308_ALC_L_DIG_CON09(2),
++			     RK3308_ALC_R_DIG_CON09(2),
++			     RK3308_AGC_MIN_GAIN_PGA_SFT,
++			     RK3308_AGC_MIN_GAIN_PGA_NDB_18,
++			     RK3308_AGC_MIN_GAIN_PGA_PDB_24,
++			     0, rk3308_codec_alc_agc_ch_min_gain_tlv),
++	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Min Volume",
++			     RK3308_ALC_L_DIG_CON09(3),
++			     RK3308_ALC_R_DIG_CON09(3),
++			     RK3308_AGC_MIN_GAIN_PGA_SFT,
++			     RK3308_AGC_MIN_GAIN_PGA_NDB_18,
++			     RK3308_AGC_MIN_GAIN_PGA_PDB_24,
++			     0, rk3308_codec_alc_agc_ch_min_gain_tlv),
++
++	/* ADC MIC */
++	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 0 Left Volume",
++			     RK3308_ADC_ANA_CON01(0),
++			     RK3308_ADC_CH1_MIC_GAIN_SFT,
++			     RK3308_ADC_CH1_MIC_GAIN_0DB,
++			     RK3308_ADC_CH1_MIC_GAIN_30DB,
++			     0, rk3308_codec_adc_mic_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 0 Right Volume",
++			     RK3308_ADC_ANA_CON01(0),
++			     RK3308_ADC_CH2_MIC_GAIN_SFT,
++			     RK3308_ADC_CH2_MIC_GAIN_0DB,
++			     RK3308_ADC_CH2_MIC_GAIN_30DB,
++			     0, rk3308_codec_adc_mic_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 1 Left Volume",
++			     RK3308_ADC_ANA_CON01(1),
++			     RK3308_ADC_CH1_MIC_GAIN_SFT,
++			     RK3308_ADC_CH1_MIC_GAIN_0DB,
++			     RK3308_ADC_CH1_MIC_GAIN_30DB,
++			     0, rk3308_codec_adc_mic_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 1 Right Volume",
++			     RK3308_ADC_ANA_CON01(1),
++			     RK3308_ADC_CH2_MIC_GAIN_SFT,
++			     RK3308_ADC_CH2_MIC_GAIN_0DB,
++			     RK3308_ADC_CH2_MIC_GAIN_30DB,
++			     0, rk3308_codec_adc_mic_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 2 Left Volume",
++			     RK3308_ADC_ANA_CON01(2),
++			     RK3308_ADC_CH1_MIC_GAIN_SFT,
++			     RK3308_ADC_CH1_MIC_GAIN_0DB,
++			     RK3308_ADC_CH1_MIC_GAIN_30DB,
++			     0, rk3308_codec_adc_mic_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 2 Right Volume",
++			     RK3308_ADC_ANA_CON01(2),
++			     RK3308_ADC_CH2_MIC_GAIN_SFT,
++			     RK3308_ADC_CH2_MIC_GAIN_0DB,
++			     RK3308_ADC_CH2_MIC_GAIN_30DB,
++			     0, rk3308_codec_adc_mic_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 3 Left Volume",
++			     RK3308_ADC_ANA_CON01(3),
++			     RK3308_ADC_CH1_MIC_GAIN_SFT,
++			     RK3308_ADC_CH1_MIC_GAIN_0DB,
++			     RK3308_ADC_CH1_MIC_GAIN_30DB,
++			     0, rk3308_codec_adc_mic_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 3 Right Volume",
++			     RK3308_ADC_ANA_CON01(3),
++			     RK3308_ADC_CH2_MIC_GAIN_SFT,
++			     RK3308_ADC_CH2_MIC_GAIN_0DB,
++			     RK3308_ADC_CH2_MIC_GAIN_30DB,
++			     0, rk3308_codec_adc_mic_gain_tlv),
++
++	/* ADC ALC */
++	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 0 Left Volume",
++			     RK3308_ADC_ANA_CON03(0),
++			     RK3308_ADC_CH1_ALC_GAIN_SFT,
++			     RK3308_ADC_CH1_ALC_GAIN_NDB_18,
++			     RK3308_ADC_CH1_ALC_GAIN_PDB_28_5,
++			     0, rk3308_codec_adc_alc_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 0 Right Volume",
++			     RK3308_ADC_ANA_CON04(0),
++			     RK3308_ADC_CH2_ALC_GAIN_SFT,
++			     RK3308_ADC_CH2_ALC_GAIN_NDB_18,
++			     RK3308_ADC_CH2_ALC_GAIN_PDB_28_5,
++			     0, rk3308_codec_adc_alc_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 1 Left Volume",
++			     RK3308_ADC_ANA_CON03(1),
++			     RK3308_ADC_CH1_ALC_GAIN_SFT,
++			     RK3308_ADC_CH1_ALC_GAIN_NDB_18,
++			     RK3308_ADC_CH1_ALC_GAIN_PDB_28_5,
++			     0, rk3308_codec_adc_alc_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 1 Right Volume",
++			     RK3308_ADC_ANA_CON04(1),
++			     RK3308_ADC_CH2_ALC_GAIN_SFT,
++			     RK3308_ADC_CH2_ALC_GAIN_NDB_18,
++			     RK3308_ADC_CH2_ALC_GAIN_PDB_28_5,
++			     0, rk3308_codec_adc_alc_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 2 Left Volume",
++			     RK3308_ADC_ANA_CON03(2),
++			     RK3308_ADC_CH1_ALC_GAIN_SFT,
++			     RK3308_ADC_CH1_ALC_GAIN_NDB_18,
++			     RK3308_ADC_CH1_ALC_GAIN_PDB_28_5,
++			     0, rk3308_codec_adc_alc_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 2 Right Volume",
++			     RK3308_ADC_ANA_CON04(2),
++			     RK3308_ADC_CH2_ALC_GAIN_SFT,
++			     RK3308_ADC_CH2_ALC_GAIN_NDB_18,
++			     RK3308_ADC_CH2_ALC_GAIN_PDB_28_5,
++			     0, rk3308_codec_adc_alc_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 3 Left Volume",
++			     RK3308_ADC_ANA_CON03(3),
++			     RK3308_ADC_CH1_ALC_GAIN_SFT,
++			     RK3308_ADC_CH1_ALC_GAIN_NDB_18,
++			     RK3308_ADC_CH1_ALC_GAIN_PDB_28_5,
++			     0, rk3308_codec_adc_alc_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 3 Right Volume",
++			     RK3308_ADC_ANA_CON04(3),
++			     RK3308_ADC_CH2_ALC_GAIN_SFT,
++			     RK3308_ADC_CH2_ALC_GAIN_NDB_18,
++			     RK3308_ADC_CH2_ALC_GAIN_PDB_28_5,
++			     0, rk3308_codec_adc_alc_gain_tlv),
++
++	/* DAC */
++	SOC_SINGLE_RANGE_TLV("DAC Left Volume",
++			     RK3308_DAC_ANA_CON04,
++			     RK3308_DAC_L_GAIN_SFT,
++			     RK3308_DAC_L_GAIN_0DB,
++			     RK3308_DAC_L_GAIN_PDB_6,
++			     0, rk3308_codec_dac_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("DAC Right Volume",
++			     RK3308_DAC_ANA_CON04,
++			     RK3308_DAC_R_GAIN_SFT,
++			     RK3308_DAC_R_GAIN_0DB,
++			     RK3308_DAC_R_GAIN_PDB_6,
++			     0, rk3308_codec_dac_gain_tlv),
++
++	/* DAC HPOUT */
++	SOC_SINGLE_RANGE_TLV("DAC HPOUT Left Volume",
++			     RK3308_DAC_ANA_CON05,
++			     RK3308_DAC_L_HPOUT_GAIN_SFT,
++			     RK3308_DAC_L_HPOUT_GAIN_NDB_39,
++			     RK3308_DAC_L_HPOUT_GAIN_PDB_6,
++			     0, rk3308_codec_dac_hpout_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("DAC HPOUT Right Volume",
++			     RK3308_DAC_ANA_CON06,
++			     RK3308_DAC_R_HPOUT_GAIN_SFT,
++			     RK3308_DAC_R_HPOUT_GAIN_NDB_39,
++			     RK3308_DAC_R_HPOUT_GAIN_PDB_6,
++			     0, rk3308_codec_dac_hpout_gain_tlv),
++
++	/* DAC HPMIX */
++	SOC_SINGLE_RANGE_TLV("DAC HPMIX Left Volume",
++			     RK3308_DAC_ANA_CON05,
++			     RK3308_DAC_L_HPMIX_GAIN_SFT,
++			     RK3308_DAC_L_HPMIX_GAIN_NDB_6,
++			     RK3308_DAC_L_HPMIX_GAIN_0DB,
++			     0, rk3308_codec_dac_hpmix_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("DAC HPMIX Right Volume",
++			     RK3308_DAC_ANA_CON05,
++			     RK3308_DAC_R_HPMIX_GAIN_SFT,
++			     RK3308_DAC_R_HPMIX_GAIN_NDB_6,
++			     RK3308_DAC_R_HPMIX_GAIN_0DB,
++			     0, rk3308_codec_dac_hpmix_gain_tlv),
++};
++
++static void rk3308_speaker_ctl(struct rk3308_codec_priv *rk3308, int on)
++{
++	gpiod_direction_output(rk3308->spk_ctl_gpio, on);
++}
++
++static int rk3308_codec_reset(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	reset_control_assert(rk3308->reset);
++	usleep_range(200, 300);		/* estimated value */
++	reset_control_deassert(rk3308->reset);
++
++	regmap_write(rk3308->regmap, RK3308_GLB_CON, 0x00);
++	usleep_range(200, 300);		/* estimated value */
++	regmap_write(rk3308->regmap, RK3308_GLB_CON,
++		     RK3308_SYS_WORK |
++		     RK3308_DAC_DIG_WORK |
++		     RK3308_ADC_DIG_WORK);
++
++	return 0;
++}
++
++static int rk3308_set_bias_level(struct snd_soc_codec *codec,
++				 enum snd_soc_bias_level level)
++{
++	switch (level) {
++	case SND_SOC_BIAS_ON:
++		break;
++
++	case SND_SOC_BIAS_PREPARE:
++		break;
++
++	case SND_SOC_BIAS_STANDBY:
++	case SND_SOC_BIAS_OFF:
++		break;
++	}
++
++	snd_soc_codec_force_bias_level(codec, level);
++
++	return 0;
++}
++
++static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai,
++			      unsigned int fmt)
++{
++	struct snd_soc_codec *codec = codec_dai->codec;
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0;
++	int ch = rk3308->adc_ch;
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBS_CFS:
++		adc_aif2 |= RK3308_ADC_IO_MODE_SLAVE;
++		adc_aif2 |= RK3308_ADC_MODE_SLAVE;
++		dac_aif2 |= RK3308_DAC_IO_MODE_SLAVE;
++		dac_aif2 |= RK3308_DAC_MODE_SLAVE;
++		break;
++	case SND_SOC_DAIFMT_CBM_CFM:
++		adc_aif2 |= RK3308_ADC_IO_MODE_MASTER;
++		adc_aif2 |= RK3308_ADC_MODE_MASTER;
++		dac_aif2 |= RK3308_DAC_IO_MODE_MASTER;
++		dac_aif2 |= RK3308_DAC_MODE_MASTER;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_DSP_A:
++		adc_aif1 |= RK3308_ADC_I2S_MODE_PCM;
++		dac_aif1 |= RK3308_DAC_I2S_MODE_PCM;
++		break;
++	case SND_SOC_DAIFMT_I2S:
++		adc_aif1 |= RK3308_ADC_I2S_MODE_I2S;
++		dac_aif1 |= RK3308_DAC_I2S_MODE_I2S;
++		break;
++	case SND_SOC_DAIFMT_RIGHT_J:
++		adc_aif1 |= RK3308_ADC_I2S_MODE_RJ;
++		dac_aif1 |= RK3308_DAC_I2S_MODE_RJ;
++		break;
++	case SND_SOC_DAIFMT_LEFT_J:
++		adc_aif1 |= RK3308_ADC_I2S_MODE_RJ;
++		dac_aif1 |= RK3308_DAC_I2S_MODE_LJ;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_NB_NF:
++		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL;
++		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL;
++		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL;
++		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL;
++		break;
++	case SND_SOC_DAIFMT_IB_IF:
++		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL;
++		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL;
++		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL;
++		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL;
++		break;
++	case SND_SOC_DAIFMT_IB_NF:
++		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL;
++		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL;
++		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL;
++		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL;
++		break;
++	case SND_SOC_DAIFMT_NB_IF:
++		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL;
++		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL;
++		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL;
++		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(ch),
++			   RK3308_ADC_I2S_LRC_POL_MSK |
++			   RK3308_ADC_I2S_MODE_MSK,
++			   adc_aif1);
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(ch),
++			   RK3308_ADC_IO_MODE_MSK |
++			   RK3308_ADC_MODE_MSK |
++			   RK3308_ADC_I2S_BIT_CLK_POL_MSK,
++			   adc_aif2);
++
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01,
++			   RK3308_DAC_I2S_LRC_POL_MSK |
++			   RK3308_DAC_I2S_MODE_MSK,
++			   dac_aif1);
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02,
++			   RK3308_DAC_IO_MODE_MSK |
++			   RK3308_DAC_MODE_MSK |
++			   RK3308_DAC_I2S_BIT_CLK_POL_MSK,
++			   dac_aif2);
++
++	return 0;
++}
++
++static int rk3308_hw_params(struct snd_pcm_substream *substream,
++			    struct snd_pcm_hw_params *params,
++			    struct snd_soc_dai *dai)
++{
++	struct snd_soc_codec *codec = dai->codec;
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	unsigned int adc_aif1 = 0, adc_aif2  = 0, dac_aif1 = 0, dac_aif2  = 0;
++	int ch = rk3308->adc_ch;
++
++	switch (params_format(params)) {
++	case SNDRV_PCM_FORMAT_S16_LE:
++		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_16BITS;
++		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_16BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S20_3LE:
++		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_20BITS;
++		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_20BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S24_LE:
++		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_24BITS;
++		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_24BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S32_LE:
++		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_32BITS;
++		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_32BITS;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (params_channels(params)) {
++	case 1:
++		adc_aif1 |= RK3308_ADC_I2S_MONO;
++		break;
++	case 2:
++		adc_aif1 |= RK3308_ADC_I2S_STEREO;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	adc_aif1 |= RK3308_ADC_I2S_LR_NORMAL;
++	adc_aif2 |= RK3308_ADC_I2S_WORK;
++	dac_aif1 |= RK3308_DAC_I2S_LR_NORMAL;
++	dac_aif2 |= RK3308_DAC_I2S_WORK;
++
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(ch),
++			   RK3308_ADC_I2S_VALID_LEN_MSK |
++			   RK3308_ADC_I2S_LR_MSK |
++			   RK3308_ADC_I2S_TYPE_MSK,
++			   adc_aif1);
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(ch),
++			   RK3308_ADC_I2S_MSK,
++			   adc_aif2);
++
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01,
++			   RK3308_DAC_I2S_VALID_LEN_MSK |
++			   RK3308_DAC_I2S_LR_MSK,
++			   dac_aif1);
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02,
++			   RK3308_DAC_I2S_MSK,
++			   dac_aif2);
++
++	return 0;
++}
++
++static int rk3308_digital_mute(struct snd_soc_dai *dai, int mute)
++{
++	return 0;
++}
++
++static int rk3308_codec_dac_enable(struct rk3308_codec_priv *rk3308)
++{
++	/* Step 01 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
++			   RK3308_DAC_CURRENT_MSK,
++			   RK3308_DAC_CURRENT_EN);
++
++	/* Step 02 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_BUF_REF_L_MSK |
++			   RK3308_DAC_BUF_REF_R_MSK,
++			   RK3308_DAC_BUF_REF_L_EN |
++			   RK3308_DAC_BUF_REF_R_EN);
++
++	/* Step 03 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_POP_SOUND_L_MSK |
++			   RK3308_DAC_POP_SOUND_R_MSK,
++			   RK3308_DAC_POP_SOUND_L_WORK |
++			   RK3308_DAC_POP_SOUND_R_WORK);
++
++	/* Step 04 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN,
++			   RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN);
++
++	/* Step 05 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK,
++			   RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK);
++
++	/* Step 06 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN,
++			   RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN);
++
++	/* Step 07 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN,
++			   RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN);
++
++	/* Step 08 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK,
++			   RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK);
++
++	/* Step 09 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN,
++			   RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN);
++
++	/* Step 10 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN,
++			   RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN);
++
++	/* Step 11 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN,
++			   RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN);
++
++	/* Step 12 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK,
++			   RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK);
++
++	/* Step 13 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
++			   RK3308_DAC_L_HPMIX_SEL_MSK |
++			   RK3308_DAC_R_HPMIX_SEL_MSK,
++			   RK3308_DAC_L_HPMIX_I2S |
++			   RK3308_DAC_R_HPMIX_I2S);
++
++	/* Step 14 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_UNMUTE |
++			   RK3308_DAC_R_HPMIX_UNMUTE,
++			   RK3308_DAC_L_HPMIX_UNMUTE |
++			   RK3308_DAC_R_HPMIX_UNMUTE);
++
++	/* Step 15 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
++			   RK3308_DAC_L_HPMIX_GAIN_MSK |
++			   RK3308_DAC_R_HPMIX_GAIN_MSK,
++			   RK3308_DAC_L_HPMIX_GAIN_0DB |
++			   RK3308_DAC_R_HPMIX_GAIN_0DB);
++
++	/* Step 16 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_UNMUTE |
++			   RK3308_DAC_R_HPOUT_UNMUTE,
++			   RK3308_DAC_L_HPOUT_UNMUTE |
++			   RK3308_DAC_R_HPOUT_UNMUTE);
++
++	/* Step 17 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_UNMUTE |
++			   RK3308_DAC_R_LINEOUT_UNMUTE,
++			   RK3308_DAC_L_LINEOUT_UNMUTE |
++			   RK3308_DAC_R_LINEOUT_UNMUTE);
++
++	/* Step 18 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05,
++			   RK3308_DAC_L_HPOUT_GAIN_MSK,
++			   RK3308_DAC_L_HPOUT_GAIN_0DB);
++
++	/* Step 18 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06,
++			   RK3308_DAC_R_HPOUT_GAIN_MSK,
++			   RK3308_DAC_R_HPOUT_GAIN_0DB);
++
++	/* Step 19 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_GAIN_MSK | RK3308_DAC_R_GAIN_MSK,
++			   RK3308_DAC_L_GAIN_0DB | RK3308_DAC_R_GAIN_0DB);
++
++	return 0;
++}
++
++static int rk3308_codec_dac_disable(struct rk3308_codec_priv *rk3308)
++{
++	/* Step 01 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_GAIN_MSK | RK3308_DAC_R_GAIN_MSK,
++			   RK3308_DAC_L_GAIN_0DB | RK3308_DAC_R_GAIN_0DB);
++
++	/*
++	 * Step 02
++	 *
++	 * Note1. In the step2, adjusting the register step by step to the
++	 * appropriate value and taking 20ms as time step
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05,
++			   RK3308_DAC_L_HPOUT_GAIN_MSK,
++			   RK3308_DAC_L_HPOUT_GAIN_NDB_39);
++
++	/* Step 02 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06,
++			   RK3308_DAC_R_HPOUT_GAIN_MSK,
++			   RK3308_DAC_R_HPOUT_GAIN_NDB_39);
++
++	/* Step 03 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_UNMUTE |
++			   RK3308_DAC_R_HPMIX_UNMUTE,
++			   RK3308_DAC_L_HPMIX_MUTE |
++			   RK3308_DAC_R_HPMIX_MUTE);
++
++	/* Step 04 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
++			   RK3308_DAC_L_HPMIX_SEL_MSK |
++			   RK3308_DAC_R_HPMIX_SEL_MSK,
++			   RK3308_DAC_L_HPMIX_NONE |
++			   RK3308_DAC_R_HPMIX_NONE);
++
++	/* Step 05 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_UNMUTE |
++			   RK3308_DAC_R_HPOUT_UNMUTE,
++			   RK3308_DAC_L_HPOUT_MUTE |
++			   RK3308_DAC_R_HPOUT_MUTE);
++
++	/* Step 06 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK,
++			   RK3308_DAC_L_DAC_INIT | RK3308_DAC_R_DAC_INIT);
++
++	/* Step 07 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN,
++			   RK3308_DAC_L_HPOUT_DIS | RK3308_DAC_R_HPOUT_DIS);
++
++	/* Step 08 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_UNMUTE |
++			   RK3308_DAC_R_LINEOUT_UNMUTE,
++			   RK3308_DAC_L_LINEOUT_MUTE |
++			   RK3308_DAC_R_LINEOUT_MUTE);
++
++	/* Step 09 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN,
++			   RK3308_DAC_L_LINEOUT_DIS | RK3308_DAC_R_LINEOUT_DIS);
++
++	/* Step 10 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN,
++			   RK3308_DAC_L_HPMIX_DIS | RK3308_DAC_R_HPMIX_DIS);
++
++	/* Step 11 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN,
++			   RK3308_DAC_L_DAC_DIS | RK3308_DAC_R_DAC_DIS);
++
++	/* Step 12 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN,
++			   RK3308_DAC_L_CLK_DIS | RK3308_DAC_R_CLK_DIS);
++
++	/* Step 13 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN,
++			   RK3308_DAC_L_REF_DIS | RK3308_DAC_R_REF_DIS);
++
++	/* Step 14 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_POP_SOUND_L_MSK |
++			   RK3308_DAC_POP_SOUND_R_MSK,
++			   RK3308_DAC_POP_SOUND_L_INIT |
++			   RK3308_DAC_POP_SOUND_R_INIT);
++
++	/* Step 15 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_BUF_REF_L_EN | RK3308_DAC_BUF_REF_R_EN,
++			   RK3308_DAC_BUF_REF_L_DIS | RK3308_DAC_BUF_REF_R_DIS);
++
++	/* Step 16 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
++			   RK3308_DAC_CURRENT_EN,
++			   RK3308_DAC_CURRENT_DIS);
++
++	/* Step 17 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK,
++			   RK3308_DAC_L_HPOUT_INIT | RK3308_DAC_R_HPOUT_INIT);
++
++	/* Step 18 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK,
++			   RK3308_DAC_L_HPMIX_INIT | RK3308_DAC_R_HPMIX_INIT);
++
++	/* Step 19 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
++			   RK3308_DAC_L_HPMIX_GAIN_MSK |
++			   RK3308_DAC_R_HPMIX_GAIN_MSK,
++			   RK3308_DAC_L_HPMIX_GAIN_NDB_6 |
++			   RK3308_DAC_R_HPMIX_GAIN_NDB_6);
++
++	/*
++	 * Note2. If the ACODEC_DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3]
++	 * is set to 0x1, add the steps from the section Disable DAC
++	 * Configuration Standard Usage Flow after complete the step 19
++	 */
++
++	return 0;
++}
++
++static int rk3308_codec_power_on(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	/* 1. Supply the power of digital part and reset the Audio Codec */
++	/* Do nothing */
++
++	/*
++	 * 2. Configure ACODEC_DAC_ANA_CON1[1:0] and ACODEC_DAC_ANA_CON1[5:4]
++	 *    to 0x1, to setup dc voltage of the DAC channel output
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_POP_SOUND_L_MSK, RK3308_DAC_POP_SOUND_L_INIT);
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_POP_SOUND_R_MSK, RK3308_DAC_POP_SOUND_R_INIT);
++
++	/*
++	 * 3. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 0x1
++	 *
++	 * Note: Only the reg (ADC_ANA_CON10+0x0)[6:0] represent the control
++	 * signal to select current to pre-charge/dis_charge
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_CURRENT_CHARGE_MSK, RK3308_ADC_SEL_I_64(1));
++
++	/* 4. Supply the power of the analog part(AVDD,AVDDRV) */
++
++	/*
++	 * 5. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x1 to setup
++	 *    reference voltage
++	 *
++	 * Note: Only the reg (ADC_ANA_CON10+0x0)[7] represent the enable
++	 * signal of reference voltage module
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_REF_EN, RK3308_ADC_REF_EN);
++
++	/*
++	 * 6. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to
++	 *    0x7f step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to
++	 *    0x7f directly. The suggestion slot time of the step is 20ms.
++	 */
++	mdelay(20);
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_CURRENT_CHARGE_MSK,
++			   RK3308_ADC_DONT_SEL_ALL);
++
++	/* 7. Wait until the voltage of VCM keeps stable at the AVDD/2 */
++	usleep_range(200, 300);	/* estimated value */
++
++	/*
++	 * 8. Configure the register ACODEC_ADC_ANA_CON10[6:0] to the
++	 *    appropriate value(expect 0x0) for reducing power.
++	 */
++
++	 /* TODO: choose an appropriate charge value */
++
++	return 0;
++}
++
++static int rk3308_codec_power_off(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	/*
++	 * 1. Keep the power on and disable the DAC and ADC path according to
++	 *    the section power on configuration standard usage flow.
++	 */
++
++	/* 2. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 0x1 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_CURRENT_CHARGE_MSK, RK3308_ADC_SEL_I_64(1));
++
++	/* 3. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x0 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_REF_EN, RK3308_ADC_REF_DIS);
++
++	/*
++	 * 4.Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to 0x7f
++	 *   step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to 0x7f
++	 *   directly. The suggestion slot time of the step is 20ms
++	 */
++	mdelay(20);
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_CURRENT_CHARGE_MSK,
++			   RK3308_ADC_DONT_SEL_ALL);
++
++	/* 5. Wait until the voltage of VCM keeps stable at the AGND */
++	usleep_range(200, 300);	/* estimated value */
++
++	/* 6. Power off the analog power supply */
++	/* 7. Power off the digital power supply */
++
++	/* Do something via hardware */
++
++	return 0;
++}
++
++static int check_micbias(int micbias)
++{
++	switch (micbias) {
++	case RK3308_ADC_MICBIAS_VOLT_0_85:
++	case RK3308_ADC_MICBIAS_VOLT_0_8:
++	case RK3308_ADC_MICBIAS_VOLT_0_75:
++	case RK3308_ADC_MICBIAS_VOLT_0_7:
++	case RK3308_ADC_MICBIAS_VOLT_0_65:
++	case RK3308_ADC_MICBIAS_VOLT_0_6:
++	case RK3308_ADC_MICBIAS_VOLT_0_55:
++	case RK3308_ADC_MICBIAS_VOLT_0_5:
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
++static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308,
++				       int micbias)
++{
++	int ch = rk3308->adc_ch;
++	int ret;
++
++	if (ch != 1 && ch != 2) {
++		dev_err(rk3308->plat_dev,
++			 "%s: currnet ch: %d, only ch1/2 control MICBIAS1/2\n",
++			 __func__, ch);
++		return -EINVAL;
++	}
++
++	/* 1. Power up the ACODEC and keep the AVDDH stable */
++
++	/* 2. Configure ACODEC_ADC_ANA_CON7[2:0] to the certain value */
++	ret = check_micbias(micbias);
++	if (ret < 0) {
++		dev_err(rk3308->plat_dev, "This is an invalid micbias: %d\n",
++			micbias);
++		return ret;
++	}
++
++	/*
++	 * Note: Only the reg (ADC_ANA_CON7+0x0)[2:0] represent the level range
++	 * control signal of MICBIAS voltage
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0),
++			   RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK,
++			   micbias);
++
++	/* 3. Wait until the VCMH keep stable */
++	usleep_range(200, 300);	/* estimated value */
++
++	/* 4. Configure ACODEC_ADC_ANA_CON8[4] to 0x1 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(ch),
++			   RK3308_ADC_MICBIAS_CURRENT_MSK,
++			   RK3308_ADC_MICBIAS_CURRENT_EN);
++
++	/*
++	 * 5. Configure the (ADC_ANA_CON7+0x40)[3] or (ADC_ANA_CON7+0x80)[3]
++	 * to 0x1.
++	 * (ADC_ANA_CON7+0x40)[3] used to control the MICBIAS1, and
++	 * (ADC_ANA_CON7+0x80)[3] used to control the MICBIAS2
++	 */
++
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
++			   RK3308_ADC_MIC_BIAS_BUF_EN,
++			   RK3308_ADC_MIC_BIAS_BUF_EN);
++
++	return 0;
++}
++
++static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308)
++{
++	int ch = rk3308->adc_ch;
++
++	if (ch != 1 && ch != 2) {
++		dev_err(rk3308->plat_dev,
++			 "%s: currnet ch: %d, only ch1/2 control MICBIAS1/2\n",
++			 __func__, ch);
++		return -EINVAL;
++	}
++
++	/* 1. Enable the MICBIAS and keep the Audio Codec stable */
++	/* Do nothing */
++
++	/*
++	 * 2. Configure the (ADC_ANA_CON7+0x40)[3] or
++	 * (ADC_ANA_CON7+0x80)[3] to 0x0
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
++			   RK3308_ADC_MIC_BIAS_BUF_EN,
++			   RK3308_ADC_MIC_BIAS_BUF_DIS);
++
++	/* 3. Configure ACODEC_ADC_ANA_CON8[4] to 0x0 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(ch),
++			   RK3308_ADC_MICBIAS_CURRENT_MSK,
++			   RK3308_ADC_MICBIAS_CURRENT_DIS);
++
++	return 0;
++}
++
++static int rk3308_codec_alc_enable(struct rk3308_codec_priv *rk3308)
++{
++	int ch = rk3308->adc_ch;
++
++	/*
++	 * 1. Set he max level and min level of the ALC need to control.
++	 *
++	 * These values are estimated
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON05(ch),
++			   RK3308_AGC_LO_8BITS_AGC_MIN_MSK,
++			   0x16);
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON05(ch),
++			   RK3308_AGC_HI_8BITS_AGC_MIN_MSK,
++			   0x40);
++
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON05(ch),
++			   RK3308_AGC_LO_8BITS_AGC_MAX_MSK,
++			   0x26);
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON05(ch),
++			   RK3308_AGC_HI_8BITS_AGC_MAX_MSK,
++			   0x40);
++
++	/*
++	 * 2. Set ACODEC_ALC_DIG_CON4[2:0] according to the sample rate
++	 *
++	 * By default is 44.1KHz for sample.
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON04(ch),
++			   RK3308_AGC_APPROX_RATE_MSK,
++			   RK3308_AGC_APPROX_RATE_44_1K);
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON04(ch),
++			   RK3308_AGC_APPROX_RATE_MSK,
++			   RK3308_AGC_APPROX_RATE_44_1K);
++
++	/* 3. Set ACODEC_ALC_DIG_CON9[6] to 0x1, to enable the ALC module */
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch),
++			   RK3308_AGC_FUNC_SEL_MSK,
++			   RK3308_AGC_FUNC_SEL_EN);
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(ch),
++			   RK3308_AGC_FUNC_SEL_MSK,
++			   RK3308_AGC_FUNC_SEL_EN);
++
++	/*
++	 * 4. Set ACODEC_ADC_ANA_CON11[1:0], (ACODEC_ADC_ANA_CON11+0x40)[1:0],
++	 * (ACODEC_ADC_ANA_CON11+0x80)[1:0] and (ACODEC_ADC_ANA_CON11+0xc0)[1:0]
++	 * to 0x3, to enable the ALC module to control the gain of PGA.
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(ch),
++			   RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK |
++			   RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK,
++			   RK3308_ADC_ALCL_CON_GAIN_PGAL_EN |
++			   RK3308_ADC_ALCR_CON_GAIN_PGAR_EN);
++
++	/*
++	 * 5.Observe the current ALC output gain by reading
++	 * ACODEC_ALC_DIG_CON12[4:0]
++	 *
++	 * The default GAIN is 0x0c
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON12(ch),
++			   RK3308_AGC_GAIN_MSK,
++			   0x0c);
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON12(ch),
++			   RK3308_AGC_GAIN_MSK,
++			   0x0c);
++
++	return 0;
++}
++
++static int rk3308_codec_alc_disable(struct rk3308_codec_priv *rk3308)
++{
++	int ch = rk3308->adc_ch;
++
++	/*
++	 * 1. Set ACODEC_ALC_DIG_CON9[6] to 0x0, to disable the ALC module,
++	 * then the ALC output gain will keep to the last value
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch),
++			   RK3308_AGC_FUNC_SEL_MSK,
++			   RK3308_AGC_FUNC_SEL_DIS);
++	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(ch),
++			   RK3308_AGC_FUNC_SEL_MSK,
++			   RK3308_AGC_FUNC_SEL_DIS);
++
++	/*
++	 * 2. Set ACODEC_ADC_ANA_CON11[1:0], (ACODEC_ADC_ANA_CON11+0x40)[1:0],
++	 * (ACODEC_ADC_ANA_CON11+0x80)[1:0] and (ACODEC_ADC_ANA_CON11+0xc0)[1:0]
++	 * to 0x0, to disable the ALC module to control the gain of PGA.
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(ch),
++			   RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK |
++			   RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK,
++			   RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS |
++			   RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS);
++
++	return 0;
++}
++
++static int rk3308_codec_adc_ana_enable(struct rk3308_codec_priv *rk3308)
++{
++	unsigned int adc_aif1 = 0, adc_aif2 = 0;
++	unsigned int agc_func_en;
++	int ch = rk3308->adc_ch;
++
++	/*
++	 * 1. Set the ACODEC_ADC_ANA_CON7[7:6] and ACODEC_ADC_ANA_CON7[5:4],
++	 * to select the line-in or microphone as input of ADC
++	 *
++	 * Note1. Please ignore the step1 for enabling ADC3, ADC4, ADC5,
++	 * ADC6, ADC7, and ADC8
++	 */
++	if (ch == 0) {
++		if (rk3308->adc_ch0_using_linein) {
++			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
++				   RK3308_ADC_CH1_IN_SEL_MSK,
++				   RK3308_ADC_CH1_IN_LINEIN);
++			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
++				   RK3308_ADC_CH2_IN_SEL_MSK,
++				   RK3308_ADC_CH2_IN_LINEIN);
++		} else {
++			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
++				   RK3308_ADC_CH1_IN_SEL_MSK,
++				   RK3308_ADC_CH1_IN_MIC);
++			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
++				   RK3308_ADC_CH2_IN_SEL_MSK,
++				   RK3308_ADC_CH2_IN_MIC);
++		}
++	}
++
++	/*
++	 * 2. Set ACODEC_ADC_ANA_CON0[7:0] to 0xff, to end the mute station
++	 * of ADC, to enable the MIC module, to enable the reference voltage
++	 * buffer, and to end the initialization of MIC
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(ch),
++				   RK3308_ADC_CH1_CH2_MIC_ALL_MSK,
++				   RK3308_ADC_CH1_CH2_MIC_ALL);
++
++	/*
++	 * 3. Set ACODEC_ADC_ANA_CON6[0] to 0x1, to enable the current source
++	 * of audio
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(ch),
++				   RK3308_ADC_CURRENT_MSK,
++				   RK3308_ADC_CURRENT_EN);
++
++	/*
++	 * 4. Set ACODEC_ADC_ANA_CON2[7:0] to 0x77, to enable the ALC module,
++	 * to enable the zero-crossing detection function, and to end the
++	 * initialization of ALC
++	 *
++	 * Note2. Please set ACODEC_ADC_ANA_CON2[7:0] to 0x33 in step4
++	 * if the AGC function is closed
++	 */
++
++	adc_aif1 = RK3308_ADC_CH1_ALC_EN | RK3308_ADC_CH1_ALC_WORK;
++	regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), &agc_func_en);
++	if (agc_func_en & RK3308_AGC_FUNC_SEL_EN)
++		adc_aif1 |= RK3308_ADC_CH1_ZEROCROSS_DET_EN;
++
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch),
++				   RK3308_ADC_CH1_ALC_ZC_MSK,
++				   adc_aif1);
++
++	adc_aif2 = RK3308_ADC_CH2_ALC_EN | RK3308_ADC_CH2_ALC_WORK;
++	regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), &agc_func_en);
++	if (agc_func_en & RK3308_AGC_FUNC_SEL_EN)
++		adc_aif2 |= RK3308_ADC_CH2_ZEROCROSS_DET_EN;
++
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch),
++				   RK3308_ADC_CH2_ALC_ZC_MSK,
++				   adc_aif2);
++
++	/*
++	 * 5. Set ACODEC_ADC_ANA_CON5[7:0] to 0x77, to enable the clock and
++	 * ADC module, and to end the initialization of ADC
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
++				   RK3308_ADC_CH1_ADC_CLK_MSK,
++				   RK3308_ADC_CH1_CLK_EN |
++				   RK3308_ADC_CH1_ADC_EN |
++				   RK3308_ADC_CH1_ADC_WORK);
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
++				   RK3308_ADC_CH2_ADC_CLK_MSK,
++				   RK3308_ADC_CH2_CLK_EN |
++				   RK3308_ADC_CH2_ADC_EN |
++				   RK3308_ADC_CH2_ADC_WORK);
++
++	/*
++	 * 6. Set ACODEC_ADC_ANA_CON1[5:4] and ACODEC_ADC_ANA_CON1[1:0],
++	 * to select the gain of the MIC
++	 *
++	 * By default is 0db.
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
++				   RK3308_ADC_CH1_MIC_GAIN_MSK,
++				   RK3308_ADC_CH1_MIC_GAIN_0DB);
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
++				   RK3308_ADC_CH2_MIC_GAIN_MSK,
++				   RK3308_ADC_CH2_MIC_GAIN_0DB);
++
++	/*
++	 * 7.Set ACODEC_ADC_ANA_CON3[4:0] and ACODEC_ADC_ANA_CON4[3:0] to
++	 * select the gain of ALC
++	 *
++	 * By default is 0db.
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON03(ch),
++				   RK3308_ADC_CH1_ALC_GAIN_MSK,
++				   RK3308_ADC_CH1_ALC_GAIN_0DB);
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON04(ch),
++				   RK3308_ADC_CH2_ALC_GAIN_MSK,
++				   RK3308_ADC_CH2_ALC_GAIN_0DB);
++
++	/* 8.Begin recording */
++
++	return 0;
++}
++
++static int rk3308_codec_adc_ana_disable(struct rk3308_codec_priv *rk3308)
++{
++	int ch = rk3308->adc_ch;
++
++	/*
++	 * 1. Set ACODEC_ADC_ANA_CON2[7:0] to 0x0, to disable the ALC module,
++	 * to disable the zero-crossing detection function, and to begin the
++	 * initialization of ALC
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch),
++				   RK3308_ADC_CH1_ALC_ZC_MSK,
++				   0);
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch),
++				   RK3308_ADC_CH2_ALC_ZC_MSK,
++				   0);
++
++	/*
++	 * 2. Set ACODEC_ADC_ANA_CON5[7:0] to 0x0, to disable the clock and
++	 * ADC module, and to begin the initialization of ADC
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
++				   RK3308_ADC_CH1_ADC_CLK_MSK,
++				   0);
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
++				   RK3308_ADC_CH2_ADC_CLK_MSK,
++				   0);
++
++	/*
++	 * 3. Set ACODEC_ADC_ANA_CON0[7:0] to 0x88, to disable the MIC module,
++	 * to disable the reference voltage buffer, and to begin the
++	 * initialization of MIC
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(ch),
++				   RK3308_ADC_CH1_CH2_MIC_ALL_MSK,
++				   RK3308_ADC_CH1_MIC_UNMUTE |
++				   RK3308_ADC_CH2_MIC_UNMUTE);
++
++	/*
++	 * 4. Set ACODEC_ADC_ANA_CON6[0] to 0x0, to disable the current
++	 * source of audio
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(ch),
++				   RK3308_ADC_CURRENT_MSK,
++				   RK3308_ADC_CURRENT_DIS);
++
++	return 0;
++}
++
++static int rk3308_codec_open_capture(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	rk3308_codec_alc_enable(rk3308);
++	rk3308_codec_adc_ana_enable(rk3308);
++
++	return 0;
++}
++
++static int rk3308_codec_close_capture(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	rk3308_codec_alc_disable(rk3308);
++	rk3308_codec_adc_ana_disable(rk3308);
++
++	return 0;
++}
++
++static int rk3308_codec_open_playback(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	rk3308_codec_dac_enable(rk3308);
++	rk3308_speaker_ctl(rk3308, 1);
++
++	return 0;
++}
++
++static int rk3308_codec_close_playback(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	rk3308_speaker_ctl(rk3308, 0);
++	rk3308_codec_dac_disable(rk3308);
++
++	return 0;
++}
++
++static int rk3308_pcm_startup(struct snd_pcm_substream *substream,
++			      struct snd_soc_dai *dai)
++{
++	struct snd_soc_codec *codec = dai->codec;
++	int ret = 0;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		ret = rk3308_codec_open_playback(codec);
++	else
++		ret = rk3308_codec_open_capture(codec);
++
++	return ret;
++}
++
++static void rk3308_pcm_shutdown(struct snd_pcm_substream *substream,
++				struct snd_soc_dai *dai)
++{
++	struct snd_soc_codec *codec = dai->codec;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		rk3308_codec_close_playback(codec);
++	else
++		rk3308_codec_close_capture(codec);
++}
++
++static struct snd_soc_dai_ops rk3308_dai_ops = {
++	.hw_params = rk3308_hw_params,
++	.set_fmt = rk3308_set_dai_fmt,
++	.digital_mute = rk3308_digital_mute,
++	.startup = rk3308_pcm_startup,
++	.shutdown = rk3308_pcm_shutdown,
++};
++
++static struct snd_soc_dai_driver rk3308_dai[] = {
++	{
++		.name = "rk3308-hifi",
++		.id = RK3308_HIFI,
++		.playback = {
++			.stream_name = "HiFi Playback",
++			.channels_min = 2,
++			.channels_max = 2,
++			.rates = SNDRV_PCM_RATE_8000_96000,
++			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++				    SNDRV_PCM_FMTBIT_S20_3LE |
++				    SNDRV_PCM_FMTBIT_S24_LE |
++				    SNDRV_PCM_FMTBIT_S32_LE),
++		},
++		.capture = {
++			.stream_name = "HiFi Capture",
++			.channels_min = 1,
++			.channels_max = 8,
++			.rates = SNDRV_PCM_RATE_8000_96000,
++			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++				    SNDRV_PCM_FMTBIT_S20_3LE |
++				    SNDRV_PCM_FMTBIT_S24_LE |
++				    SNDRV_PCM_FMTBIT_S32_LE),
++		},
++		.ops = &rk3308_dai_ops,
++	},
++};
++
++static int rk3308_suspend(struct snd_soc_codec *codec)
++{
++	rk3308_set_bias_level(codec, SND_SOC_BIAS_OFF);
++
++	return 0;
++}
++
++static int rk3308_resume(struct snd_soc_codec *codec)
++{
++	rk3308_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++
++	return 0;
++}
++
++static int rk3308_probe(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	rk3308_codec_reset(codec);
++	rk3308_codec_power_on(codec);
++
++	rk3308_codec_micbias_enable(rk3308, RK3308_ADC_MICBIAS_VOLT_0_7);
++
++	return 0;
++}
++
++static int rk3308_remove(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	rk3308_speaker_ctl(rk3308, 0);
++	rk3308_codec_micbias_disable(rk3308);
++	rk3308_codec_power_off(codec);
++
++	return 0;
++}
++
++static struct snd_soc_codec_driver soc_codec_dev_rk3308 = {
++	.probe = rk3308_probe,
++	.remove = rk3308_remove,
++	.suspend = rk3308_suspend,
++	.resume = rk3308_resume,
++	.set_bias_level = rk3308_set_bias_level,
++	.controls = rk3308_codec_dapm_controls,
++	.num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls),
++};
++
++static const struct reg_default rk3308_codec_reg_defaults[] = {
++	{ RK3308_GLB_CON, 0x07 },
++};
++
++static bool rk3308_codec_write_read_reg(struct device *dev, unsigned int reg)
++{
++	/* All registers can be read / write */
++	return true;
++}
++
++static bool rk3308_codec_volatile_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case RK3308_GLB_CON:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static const struct regmap_config rk3308_codec_regmap_config = {
++	.reg_bits = 32,
++	.reg_stride = 4,
++	.val_bits = 32,
++	.max_register = RK3308_DAC_ANA_CON13,
++	.writeable_reg = rk3308_codec_write_read_reg,
++	.readable_reg = rk3308_codec_write_read_reg,
++	.volatile_reg = rk3308_codec_volatile_reg,
++	.reg_defaults = rk3308_codec_reg_defaults,
++	.num_reg_defaults = ARRAY_SIZE(rk3308_codec_reg_defaults),
++	.cache_type = REGCACHE_FLAT,
++};
++
++static ssize_t adc_ch_show(struct device *dev,
++				struct device_attribute *attr,
++				char *buf)
++{
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++
++	return sprintf(buf, "adc_ch: %d\n", rk3308->adc_ch);
++}
++
++static ssize_t adc_ch_store(struct device *dev,
++				 struct device_attribute *attr,
++				 const char *buf, size_t count)
++{
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	unsigned long ch;
++	int ret = kstrtoul(buf, 10, &ch);
++
++	if (ret < 0 || ch > 4) {
++		dev_err(dev, "Invalid ch: %ld, ret: %d\n", ch, ret);
++		return -EINVAL;
++	}
++
++	rk3308->adc_ch = ch;
++
++	dev_info(dev, "Store ch: %d\n", rk3308->adc_ch);
++
++	return count;
++}
++
++static const struct device_attribute adc_ch_attrs[] = {
++	__ATTR(adc_ch, 0644, adc_ch_show, adc_ch_store),
++};
++
++static void rk3308_codec_device_release(struct device *dev)
++{
++	/* Do nothing */
++}
++
++static int rk3308_codec_sysfs_init(struct platform_device *pdev,
++				   struct rk3308_codec_priv *rk3308)
++{
++	struct device *dev = &rk3308->dev;
++	int i;
++
++	dev->release = rk3308_codec_device_release;
++	dev->parent = &pdev->dev;
++	set_dev_node(dev, dev_to_node(&pdev->dev));
++	dev_set_name(dev, "rk3308-acodec-dev");
++
++	if (device_register(dev)) {
++		dev_err(&pdev->dev,
++			"Register 'rk3308-acodec-dev' failed\n");
++		dev->parent = NULL;
++		return -ENOMEM;
++	}
++
++	for (i = 0; i < ARRAY_SIZE(adc_ch_attrs); i++) {
++		if (device_create_file(dev, &adc_ch_attrs[i])) {
++			dev_err(&pdev->dev,
++				"Create 'rk3308-acodec-dev' attr failed\n");
++			device_unregister(dev);
++			return -ENOMEM;
++		}
++	}
++
++	return 0;
++}
++
++static int rk3308_platform_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct rk3308_codec_priv *rk3308;
++	struct resource *res;
++	void __iomem *base;
++	int ret = 0;
++	struct regmap *grf;
++
++	grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
++	if (IS_ERR(grf)) {
++		dev_err(&pdev->dev,
++			"Missing 'rockchip,grf' property\n");
++		return PTR_ERR(grf);
++	}
++
++	rk3308 = devm_kzalloc(&pdev->dev, sizeof(*rk3308), GFP_KERNEL);
++	if (!rk3308)
++		return -ENOMEM;
++
++	ret = rk3308_codec_sysfs_init(pdev, rk3308);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Sysfs init failed\n");
++		return ret;
++	}
++
++	rk3308->plat_dev = &pdev->dev;
++
++	rk3308->reset = devm_reset_control_get(&pdev->dev, "acodec-reset");
++	if (IS_ERR(rk3308->reset)) {
++		ret = PTR_ERR(rk3308->reset);
++		if (ret != -ENOENT)
++			return ret;
++
++		dev_dbg(&pdev->dev, "No reset control found\n");
++		rk3308->reset = NULL;
++	}
++
++	/* GPIO0_A5 control speaker on RK3308 EVB */
++	rk3308->spk_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "spk_ctl",
++						       GPIOD_OUT_HIGH);
++	if (IS_ERR(rk3308->spk_ctl_gpio)) {
++		ret = PTR_ERR(rk3308->spk_ctl_gpio);
++		dev_err(&pdev->dev, "Unable to claim gpio spk_ctl\n");
++		return ret;
++	}
++
++	rk3308->pclk = devm_clk_get(&pdev->dev, "acodec");
++	if (IS_ERR(rk3308->pclk)) {
++		dev_err(&pdev->dev, "Can't get acodec pclk\n");
++		return PTR_ERR(rk3308->pclk);
++	}
++
++	ret = clk_prepare_enable(rk3308->pclk);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Failed to enable acodec pclk: %d\n", ret);
++		return ret;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(base)) {
++		ret = PTR_ERR(base);
++		dev_err(&pdev->dev, "Failed to ioremap resource\n");
++		goto failed;
++	}
++
++	rk3308->regmap = devm_regmap_init_mmio(&pdev->dev, base,
++					       &rk3308_codec_regmap_config);
++	if (IS_ERR(rk3308->regmap)) {
++		ret = PTR_ERR(rk3308->regmap);
++		dev_err(&pdev->dev, "Failed to regmap mmio\n");
++		goto failed;
++	}
++
++	platform_set_drvdata(pdev, rk3308);
++
++	ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_rk3308,
++				      rk3308_dai, ARRAY_SIZE(rk3308_dai));
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Failed to register codec: %d\n", ret);
++		goto failed;
++	}
++
++	return ret;
++
++failed:
++	clk_disable_unprepare(rk3308->pclk);
++
++	return ret;
++}
++
++static int rk3308_platform_remove(struct platform_device *pdev)
++{
++	struct rk3308_codec_priv *rk3308 =
++		(struct rk3308_codec_priv *)platform_get_drvdata(pdev);
++
++	clk_disable_unprepare(rk3308->pclk);
++	snd_soc_unregister_codec(&pdev->dev);
++
++	return 0;
++}
++
++static const struct of_device_id rk3308codec_of_match[] = {
++	{ .compatible = "rockchip,rk3308-codec", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, rk3308codec_of_match);
++
++static struct platform_driver rk3308_codec_driver = {
++	.driver = {
++		   .name = "rk3308-acodec",
++		   .of_match_table = of_match_ptr(rk3308codec_of_match),
++	},
++	.probe = rk3308_platform_probe,
++	.remove = rk3308_platform_remove,
++};
++module_platform_driver(rk3308_codec_driver);
++
++MODULE_AUTHOR("Xing Zheng <zhengxing@rock-chips.com>");
++MODULE_DESCRIPTION("ASoC RK3308 Codec Driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/sound/soc/codecs/rk3308_codec.h b/sound/soc/codecs/rk3308_codec.h
+new file mode 100644
+index 000000000000..6cfa69157785
+--- /dev/null
++++ b/sound/soc/codecs/rk3308_codec.h
+@@ -0,0 +1,960 @@
++/*
++ * rk3308_codec.h -- RK3308 ALSA Soc Audio Driver
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++#ifndef __RK3308_CODEC_H__
++#define __RK3308_CODEC_H__
++
++#define ACODEC_RESET_CTL			0x00 /* REG 0x00 */
++
++/* ADC DIGITAL REGISTERS */
++#define ACODEC_ADC_I2S_CTL0			0x04 /* REG 0x01 */
++#define ACODEC_ADC_I2S_CTL1			0x08 /* REG 0x02 */
++#define ACODEC_ADC_BIST_MODE_SEL		0x0c /* REG 0x03 */
++/* Resevred REG 0x04 ~ 0x06 */
++#define ACODEC_ADC_DATA_PATH			0x1c /* REG 0x07 */
++/* Resevred REG 0x08 ~ 0x0f */
++
++/* REG 0x10 ~ 0x1c are used to configure AGC of Left channel (ALC1) */
++#define ACODEC_ADC_PGA_AGC_L_CTL0		0x40 /* REG 0x10 */
++#define ACODEC_ADC_PGA_AGC_L_CTL1		0x44 /* REG 0x11 */
++#define ACODEC_ADC_PGA_AGC_L_CTL2		0x48 /* REG 0x12 */
++#define ACODEC_ADC_PGA_AGC_L_CTL3		0x4c /* REG 0x13 */
++#define ACODEC_ADC_PGA_AGC_L_CTL4		0x50 /* REG 0x14 */
++#define ACODEC_ADC_PGA_AGC_L_LO_MAX		0x54 /* REG 0x15 */
++#define ACODEC_ADC_PGA_AGC_L_HI_MAX		0x58 /* REG 0x16 */
++#define ACODEC_ADC_PGA_AGC_L_LO_MIN		0x5c /* REG 0x17 */
++#define ACODEC_ADC_PGA_AGC_L_HI_MIN		0x60 /* REG 0x18 */
++#define ACODEC_ADC_PGA_AGC_L_CTL5		0x64 /* REG 0x19 */
++/* Resevred REG 0x1a ~ 0x1b */
++#define ACODEC_ADC_AGC_L_RO_GAIN		0x70 /* REG 0x1c */
++
++/* REG 0x20 ~ 0x2c are used to configure AGC of Right channel (ALC2) */
++#define ACODEC_ADC_PGA_AGC_R_CTL0		0x80 /* REG 0x20 */
++#define ACODEC_ADC_PGA_AGC_R_CTL1		0x84 /* REG 0x21 */
++#define ACODEC_ADC_PGA_AGC_R_CTL2		0x88 /* REG 0x22 */
++#define ACODEC_ADC_PGA_AGC_R_CTL3		0x8c /* REG 0x23 */
++#define ACODEC_ADC_PGA_AGC_R_CTL4		0x90 /* REG 0x24 */
++#define ACODEC_ADC_PGA_AGC_R_LO_MAX		0x94 /* REG 0x25 */
++#define ACODEC_ADC_PGA_AGC_R_HI_MAX		0x98 /* REG 0x26 */
++#define ACODEC_ADC_PGA_AGC_R_LO_MIN		0x9c /* REG 0x27 */
++#define ACODEC_ADC_PGA_AGC_R_HI_MIN		0xa0 /* REG 0x28 */
++#define ACODEC_ADC_PGA_AGC_R_CTL5		0xa4 /* REG 0x29 */
++/* Resevred REG 0x2a ~ 0x2b */
++#define ACODEC_ADC_AGC_R_RO_GAIN		0xb0 /* REG 0x2c */
++
++/* DAC DIGITAL REGISTERS */
++#define ACODEC_DAC_I2S_CTL0			0x04 /* REG 0x01 */
++#define ACODEC_DAC_I2S_CTL1			0x08 /* REG 0x02 */
++#define ACODEC_DAC_BIST_MODE_SEL		0x0c /* REG 0x03 */
++/* Resevred REG 0x04 */
++#define ACODEC_DAC_DATA_SEL			0x14 /* REG 0x05 */
++/* Resevred REG 0x06 ~ 0x09 */
++#define ACODEC_DAC_DATA_HI			0x28 /* REG 0x0a */
++#define ACODEC_DAC_DATA_LO			0x2c /* REG 0x0b */
++/* Resevred REG 0x0c ~ 0x0f */
++
++/* ADC ANALOG REGISTERS */
++#define ACODEC_ADC_ANA_MIC_CTL			0x00 /* REG 0x00 */
++#define ACODEC_ADC_ANA_MIC_GAIN			0x04 /* REG 0x01 */
++#define ACODEC_ADC_ANA_ALC_CTL			0x08 /* REG 0x02 */
++#define ACODEC_ADC_ANA_ALC_GAIN1		0x0c /* REG 0x03 */
++#define ACODEC_ADC_ANA_ALC_GAIN2		0x10 /* REG 0x04 */
++#define ACODEC_ADC_ANA_CTL0			0x14 /* REG 0x05 */
++#define ACODEC_ADC_ANA_CTL1			0x18 /* REG 0x06 */
++#define ACODEC_ADC_ANA_CTL2			0x1c /* REG 0x07 */
++#define ACODEC_ADC_ANA_CTL3			0x20 /* REG 0x08 */
++/* Resevred REG 0x09 */
++#define ACODEC_ADC_ANA_CTL4			0x28 /* REG 0x0a */
++#define ACODEC_ADC_ANA_ALC_PGA			0x2c /* REG 0x0b */
++/* Resevred REG 0x0c ~ 0x0f */
++
++/* DAC ANALOG REGISTERS */
++#define ACODEC_DAC_ANA_CTL0			0x00 /* REG 0x00 */
++#define ACODEC_DAC_ANA_POP_VOLT			0x04 /* REG 0x01 */
++#define ACODEC_DAC_ANA_CTL1			0x08 /* REG 0x02 */
++#define ACODEC_DAC_ANA_HPOUT			0x0c /* REG 0x03 */
++#define ACODEC_DAC_ANA_LINEOUT			0x10 /* REG 0x04 */
++#define ACODEC_DAC_ANA_L_HPOUT_GAIN		0x14 /* REG 0x05 */
++#define ACODEC_DAC_ANA_R_HPOUT_GAIN		0x18 /* REG 0x06 */
++/* Resevred REG 0x07 ~ 0x0b */
++#define ACODEC_DAC_ANA_HPMIX_CTL0		0x30 /* REG 0x0c */
++#define ACODEC_DAC_ANA_HPMIX_CTL1		0x34 /* REG 0x0d */
++/* Resevred REG 0x0e ~ 0x0f */
++
++/*
++ * These registers are referenced by codec driver
++ */
++
++#define RK3308_GLB_CON				ACODEC_RESET_CTL
++
++/* ADC DIGITAL REGISTERS */
++
++/*
++ * The ADC chanel are 0 ~ 3, that control:
++ *
++ * CH0: left_0(ADC1) and right_0(ADC2)
++ * CH1: left_1(ADC3) and right_1(ADC4)
++ * CH2: left_2(ADC5) and right_2(ADC6)
++ * CH3: left_3(ADC7) and right_3(ADC8)
++ */
++#define RK3308_ADC_DIG_OFFSET(ch)		((ch & 0x3) * 0xc0 + 0x0)
++
++#define RK3308_ADC_DIG_CON01(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL0)
++#define RK3308_ADC_DIG_CON02(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL1)
++#define RK3308_ADC_DIG_CON03(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_BIST_MODE_SEL)
++#define RK3308_ADC_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH)
++
++#define RK3308_ALC_L_DIG_CON00(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL0)
++#define RK3308_ALC_L_DIG_CON01(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL1)
++#define RK3308_ALC_L_DIG_CON02(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL2)
++#define RK3308_ALC_L_DIG_CON03(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL3)
++#define RK3308_ALC_L_DIG_CON04(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL4)
++#define RK3308_ALC_L_DIG_CON05(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MAX)
++#define RK3308_ALC_L_DIG_CON06(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MAX)
++#define RK3308_ALC_L_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MIN)
++#define RK3308_ALC_L_DIG_CON08(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MIN)
++#define RK3308_ALC_L_DIG_CON09(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL5)
++#define RK3308_ALC_L_DIG_CON12(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_L_RO_GAIN)
++
++#define RK3308_ALC_R_DIG_CON00(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL0)
++#define RK3308_ALC_R_DIG_CON01(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL1)
++#define RK3308_ALC_R_DIG_CON02(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL2)
++#define RK3308_ALC_R_DIG_CON03(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL3)
++#define RK3308_ALC_R_DIG_CON04(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL4)
++#define RK3308_ALC_R_DIG_CON05(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MAX)
++#define RK3308_ALC_R_DIG_CON06(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MAX)
++#define RK3308_ALC_R_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MIN)
++#define RK3308_ALC_R_DIG_CON08(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MIN)
++#define RK3308_ALC_R_DIG_CON09(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL5)
++#define RK3308_ALC_R_DIG_CON12(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_R_RO_GAIN)
++
++/* DAC DIGITAL REGISTERS */
++#define RK3308_DAC_DIG_OFFSET			0x300
++
++#define RK3308_DAC_DIG_CON01			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL0)
++#define RK3308_DAC_DIG_CON02			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL1)
++#define RK3308_DAC_DIG_CON03			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_BIST_MODE_SEL)
++#define RK3308_DAC_DIG_CON05			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_SEL)
++#define RK3308_DAC_DIG_CON10			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_HI)
++#define RK3308_DAC_DIG_CON11			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_LO)
++
++/* ADC ANALOG REGISTERS */
++/*
++ * The ADC chanel are 0 ~ 3, that control:
++ *
++ * CH0: left_0(ADC1) and right_0(ADC2)
++ * CH1: left_1(ADC3) and right_1(ADC4)
++ * CH2: left_2(ADC5) and right_2(ADC6)
++ * CH3: left_3(ADC7) and right_3(ADC8)
++ */
++#define RK3308_ADC_ANA_OFFSET(ch)		((ch & 0x3) * 0x40 + 0x340)
++
++#define RK3308_ADC_ANA_CON00(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_CTL)
++#define RK3308_ADC_ANA_CON01(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_GAIN)
++#define RK3308_ADC_ANA_CON02(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_CTL)
++#define RK3308_ADC_ANA_CON03(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_GAIN1)
++#define RK3308_ADC_ANA_CON04(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_GAIN2)
++#define RK3308_ADC_ANA_CON05(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL0)
++#define RK3308_ADC_ANA_CON06(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL1)
++#define RK3308_ADC_ANA_CON07(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL2)
++#define RK3308_ADC_ANA_CON08(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL3)
++#define RK3308_ADC_ANA_CON10(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL4)
++#define RK3308_ADC_ANA_CON11(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_PGA)
++
++/* DAC ANALOG REGISTERS */
++#define RK3308_DAC_ANA_OFFSET			0x440
++
++#define RK3308_DAC_ANA_CON00			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL0)
++#define RK3308_DAC_ANA_CON01			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_POP_VOLT)
++#define RK3308_DAC_ANA_CON02			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL1)
++#define RK3308_DAC_ANA_CON03			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPOUT)
++#define RK3308_DAC_ANA_CON04			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT)
++#define RK3308_DAC_ANA_CON05			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_L_HPOUT_GAIN)
++#define RK3308_DAC_ANA_CON06			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_R_HPOUT_GAIN)
++#define RK3308_DAC_ANA_CON12			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL0)
++#define RK3308_DAC_ANA_CON13			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL1)
++
++/*
++ * These are the bits for registers
++ */
++
++/* RK3308_GLB_CON - REG: 0x0000 */
++#define RK3308_ADC_BIST_WORK			(1 << 7)
++#define RK3308_ADC_BIST_RESET			(0 << 7)
++#define RK3308_DAC_BIST_WORK			(1 << 6)
++#define RK3308_DAC_BIST_RESET			(0 << 6)
++#define RK3308_CODEC_RST_MSK			(0x7 << 0)
++#define RK3308_ADC_DIG_WORK			(1 << 2)
++#define RK3308_ADC_DIG_RESET			(0 << 2)
++#define RK3308_DAC_DIG_WORK			(1 << 1)
++#define RK3308_DAC_DIG_RESET			(0 << 1)
++#define RK3308_SYS_WORK				(1 << 0)
++#define RK3308_SYS_RESET			(0 << 0)
++
++/* RK3308_ADC_DIG_CON01 - REG: 0x0004 */
++#define RK3308_ADC_I2S_LRC_POL_MSK		(1 << 0)
++#define RK3308_ADC_I2S_LRC_POL_REVERSAL		(1 << 0)
++#define RK3308_ADC_I2S_LRC_POL_NORMAL		(0 << 0)
++#define RK3308_ADC_I2S_VALID_LEN_SFT		5
++#define RK3308_ADC_I2S_VALID_LEN_MSK		(0x3 << RK3308_ADC_I2S_VALID_LEN_SFT)
++#define RK3308_ADC_I2S_VALID_LEN_32BITS		(0x3 << RK3308_ADC_I2S_VALID_LEN_SFT)
++#define RK3308_ADC_I2S_VALID_LEN_24BITS		(0x2 << RK3308_ADC_I2S_VALID_LEN_SFT)
++#define RK3308_ADC_I2S_VALID_LEN_20BITS		(0x1 << RK3308_ADC_I2S_VALID_LEN_SFT)
++#define RK3308_ADC_I2S_VALID_LEN_16BITS		(0x0 << RK3308_ADC_I2S_VALID_LEN_SFT)
++#define RK3308_ADC_I2S_MODE_SFT			3
++#define RK3308_ADC_I2S_MODE_MSK			(0x3 << RK3308_ADC_I2S_MODE_SFT)
++#define RK3308_ADC_I2S_MODE_PCM			(0x3 << RK3308_ADC_I2S_MODE_SFT)
++#define RK3308_ADC_I2S_MODE_I2S			(0x2 << RK3308_ADC_I2S_MODE_SFT)
++#define RK3308_ADC_I2S_MODE_LJ			(0x1 << RK3308_ADC_I2S_MODE_SFT)
++#define RK3308_ADC_I2S_MODE_RJ			(0x0 << RK3308_ADC_I2S_MODE_SFT)
++#define RK3308_ADC_I2S_LR_MSK			(1 << 1)
++#define RK3308_ADC_I2S_LR_SWAP			(1 << 1)
++#define RK3308_ADC_I2S_LR_NORMAL		(0 << 1)
++#define RK3308_ADC_I2S_TYPE_MSK			(1 << 0)
++#define RK3308_ADC_I2S_MONO			(1 << 0)
++#define RK3308_ADC_I2S_STEREO			(0 << 0)
++
++/* RK3308_ADC_DIG_CON02 - REG: 0x0008 */
++#define RK3308_ADC_IO_MODE_MSK			(1 << 5)
++#define RK3308_ADC_IO_MODE_MASTER		(1 << 5)
++#define RK3308_ADC_IO_MODE_SLAVE		(0 << 5)
++#define RK3308_ADC_MODE_MSK			(1 << 4)
++#define RK3308_ADC_MODE_MASTER			(1 << 4)
++#define RK3308_ADC_MODE_SLAVE			(0 << 4)
++#define RK3308_ADC_I2S_FRAME_LEN_SFT		2
++#define RK3308_ADC_I2S_FRAME_LEN_MSK		(0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT)
++#define RK3308_ADC_I2S_FRAME_32BITS		(0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT)
++#define RK3308_ADC_I2S_FRAME_24BITS		(0x2 << RK3308_ADC_I2S_FRAME_LEN_SFT)
++#define RK3308_ADC_I2S_FRAME_20BITS		(0x1 << RK3308_ADC_I2S_FRAME_LEN_SFT)
++#define RK3308_ADC_I2S_FRAME_16BITS		(0x0 << RK3308_ADC_I2S_FRAME_LEN_SFT)
++#define RK3308_ADC_I2S_MSK			(0x1 << 1)
++#define RK3308_ADC_I2S_WORK			(0x1 << 1)
++#define RK3308_ADC_I2S_RESET			(0x0 << 1)
++#define RK3308_ADC_I2S_BIT_CLK_POL_MSK		(0x1 << 0)
++#define RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL	(0x1 << 0)
++#define RK3308_ADC_I2S_BIT_CLK_POL_NORMAL	(0x0 << 0)
++
++/* RK3308_ADC_DIG_CON03 - REG: 0x000c */
++#define RK3308_ADC_L_CH_BIST_SFT		2
++#define RK3308_ADC_L_CH_BIST_MSK		(0x3 << RK3308_ADC_L_CH_BIST_SFT)
++#define RK3308_ADC_L_CH_BIST_LEFT		(0x3 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */
++#define RK3308_ADC_L_CH_BIST_SINE		(0x2 << RK3308_ADC_L_CH_BIST_SFT)
++#define RK3308_ADC_L_CH_BIST_CUBE		(0x1 << RK3308_ADC_L_CH_BIST_SFT)
++#define RK3308_ADC_L_CH_BIST_RIGHT		(0x0 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */
++#define RK3308_ADC_R_CH_BIST_SFT		0
++#define RK3308_ADC_R_CH_BIST_MSK		(0x3 << RK3308_ADC_R_CH_BIST_SFT)
++#define RK3308_ADC_R_CH_BIST_LEFT		(0x3 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */
++#define RK3308_ADC_R_CH_BIST_SINE		(0x2 << RK3308_ADC_R_CH_BIST_SFT)
++#define RK3308_ADC_R_CH_BIST_CUBE		(0x1 << RK3308_ADC_R_CH_BIST_SFT)
++#define RK3308_ADC_R_CH_BIST_RIGHT		(0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */
++
++/* RK3308_ADC_DIG_CON07 - REG: 0x001c */
++#define RK3308_ADCL_DATA_SFT			4
++#define RK3308_ADCL_DATA(x)			(x << RK3308_ADCL_DATA_SFT)
++#define RK3308_ADCR_DATA_SFT			2
++#define RK3308_ADCR_DATA(x)			(x << RK3308_ADCR_DATA_SFT)
++#define RK3308_ADCL_DATA_SEL_ADCL		(0x1 << 1)
++#define RK3308_ADCL_DATA_SEL_NORMAL		(0x0 << 1)
++#define RK3308_ADCR_DATA_SEL_ADCR		(0x1 << 0)
++#define RK3308_ADCR_DATA_SEL_NORMAL		(0x0 << 0)
++
++/*
++ * RK3308_ALC_L_DIG_CON00 - REG: 0x0040 + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON00 - REG: 0x0080 + ch * 0xc0
++ */
++#define RK3308_GAIN_ATTACK_JACK			(0x1 << 6)
++#define RK3308_GAIN_ATTACK_NORMAL		(0x0 << 6)
++#define RK3308_CTRL_GEN_SFT			4
++#define RK3308_CTRL_GEN_MSK			(0x3 << RK3308_ALC_CTRL_GEN_SFT)
++#define RK3308_CTRL_GEN_JACK3			(0x3 << RK3308_ALC_CTRL_GEN_SFT)
++#define RK3308_CTRL_GEN_JACK2			(0x2 << RK3308_ALC_CTRL_GEN_SFT)
++#define RK3308_CTRL_GEN_JACK1			(0x1 << RK3308_ALC_CTRL_GEN_SFT)
++#define RK3308_CTRL_GEN_NORMAL			(0x0 << RK3308_ALC_CTRL_GEN_SFT)
++#define RK3308_AGC_HOLD_TIME_SFT		0
++#define RK3308_AGC_HOLD_TIME_MSK		(0xf << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_1S			(0xa << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_512MS		(0x9 << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_256MS		(0x8 << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_128MS		(0x7 << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_64MS		(0x6 << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_32MS		(0x5 << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_16MS		(0x4 << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_8MS		(0x3 << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_4MS		(0x2 << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_2MS		(0x1 << RK3308_AGC_HOLD_TIME_SFT)
++#define RK3308_AGC_HOLD_TIME_0MS		(0x0 << RK3308_AGC_HOLD_TIME_SFT)
++
++/*
++ * RK3308_ALC_L_DIG_CON01 - REG: 0x0044 + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON01 - REG: 0x0084 + ch * 0xc0
++ */
++#define RK3308_AGC_DECAY_TIME_SFT		4
++/* Normal mode (reg_agc_mode = 0) */
++#define RK3308_AGC_DECAY_NORMAL_MSK		(0xf << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_512MS		(0xa << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_256MS		(0x9 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_128MS		(0x8 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_64MS		(0x7 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_32MS		(0x6 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_16MS		(0x5 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_8MS		(0x4 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_4MS		(0x3 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_2MS		(0x2 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_1MS		(0x1 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_NORMAL_0MS		(0x0 << RK3308_AGC_DECAY_TIME_SFT)
++/* Limiter mode (reg_agc_mode = 1) */
++#define RK3308_AGC_DECAY_LIMITER_MSK		(0xf << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_128MS		(0xa << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_64MS		(0x9 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_32MS		(0x8 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_16MS		(0x7 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_8MS		(0x6 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_4MS		(0x5 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_2MS		(0x4 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_1MS		(0x3 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_500US		(0x2 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_250US		(0x1 << RK3308_AGC_DECAY_TIME_SFT)
++#define RK3308_AGC_DECAY_LIMITER_125US		(0x0 << RK3308_AGC_DECAY_TIME_SFT)
++
++#define RK3308_AGC_ATTACK_TIME_SFT		0
++/* Normal mode (reg_agc_mode = 0) */
++#define RK3308_AGC_ATTACK_NORMAL_MSK		(0xf << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_128MS		(0xa << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_64MS		(0x9 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_32MS		(0x8 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_16MS		(0x7 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_8MS		(0x6 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_4MS		(0x5 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_2MS		(0x4 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_1MS		(0x3 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_500US		(0x2 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_250US		(0x1 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_NORMAL_125US		(0x0 << RK3308_AGC_ATTACK_TIME_SFT)
++/* Limiter mode (reg_agc_mode = 1) */
++#define RK3308_AGC_ATTACK_LIMITER_MSK		(0xf << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_32MS		(0xa << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_16MS		(0x9 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_8MS		(0x8 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_4MS		(0x7 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_2MS		(0x6 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_1MS		(0x5 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_500US		(0x4 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_250US		(0x3 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_125US		(0x2 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_64US		(0x1 << RK3308_AGC_ATTACK_TIME_SFT)
++#define RK3308_AGC_ATTACK_LIMITER_32US		(0x0 << RK3308_AGC_ATTACK_TIME_SFT)
++
++/*
++ * RK3308_ALC_L_DIG_CON02 - REG: 0x0048 + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON02 - REG: 0x0088 + ch * 0xc0
++ */
++#define RK3308_AGC_MODE_LIMITER			(0x1 << 7)
++#define RK3308_AGC_MODE_NORMAL			(0x0 << 7)
++#define RK3308_AGC_ZERO_CRO_EN			(0x1 << 6)
++#define RK3308_AGC_ZERO_CRO_DIS			(0x0 << 6)
++#define RK3308_AGC_AMP_RECOVER_GAIN		(0x1 << 5)
++#define RK3308_AGC_AMP_RECOVER_LVOL		(0x0 << 5)
++#define RK3308_AGC_FAST_DEC_EN			(0x1 << 4)
++#define RK3308_AGC_FAST_DEC_DIS			(0x0 << 4)
++#define RK3308_AGC_NOISE_GATE_EN		(0x1 << 3)
++#define RK3308_AGC_NOISE_GATE_DIS		(0x0 << 3)
++#define RK3308_AGC_NOISE_GATE_THRESH_SFT	0
++#define RK3308_AGC_NOISE_GATE_THRESH_MSK	(0x7 << RK3308_AGC_NOISE_GATE_THRESH_SFT)
++#define RK3308_AGC_NOISE_GATE_THRESH_N81DB	(0x7 << RK3308_AGC_NOISE_GATE_THRESH_SFT)
++#define RK3308_AGC_NOISE_GATE_THRESH_N75DB	(0x6 << RK3308_AGC_NOISE_GATE_THRESH_SFT)
++#define RK3308_AGC_NOISE_GATE_THRESH_N69DB	(0x5 << RK3308_AGC_NOISE_GATE_THRESH_SFT)
++#define RK3308_AGC_NOISE_GATE_THRESH_N63DB	(0x4 << RK3308_AGC_NOISE_GATE_THRESH_SFT)
++#define RK3308_AGC_NOISE_GATE_THRESH_N57DB	(0x3 << RK3308_AGC_NOISE_GATE_THRESH_SFT)
++#define RK3308_AGC_NOISE_GATE_THRESH_N51DB	(0x2 << RK3308_AGC_NOISE_GATE_THRESH_SFT)
++#define RK3308_AGC_NOISE_GATE_THRESH_N45DB	(0x1 << RK3308_AGC_NOISE_GATE_THRESH_SFT)
++#define RK3308_AGC_NOISE_GATE_THRESH_N39DB	(0x0 << RK3308_AGC_NOISE_GATE_THRESH_SFT)
++
++/*
++ * RK3308_ALC_L_DIG_CON03 - REG: 0x004c + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON03 - REG: 0x008c + ch * 0xc0
++ */
++#define RK3308_AGC_PGA_ZERO_CRO_EN		(0x1 << 5)
++#define RK3308_AGC_PGA_ZERO_CRO_DIS		(0x0 << 5)
++#define RK3308_AGC_PGA_GAIN_SFT			0
++#define RK3308_AGC_PGA_GAIN_MSK			(0x1f << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_28_5		(0x1f << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_27		(0x1e << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_25_5		(0x1d << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_24		(0x1c << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_22_5		(0x1b << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_21		(0x1a << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_19_5		(0x19 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_18		(0x18 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_16_5		(0x17 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_15		(0x16 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_13_5		(0x15 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_12		(0x14 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_10_5		(0x13 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_9		(0x12 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_7_5		(0x11 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_6		(0x10 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_4_5		(0x0f << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_3		(0x0e << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_PDB_1_5		(0x0d << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_0DB			(0x0c << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_1_5		(0x0b << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_3		(0x0a << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_4_5		(0x09 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_6		(0x08 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_7_5		(0x07 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_9		(0x06 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_10_5		(0x05 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_12		(0x04 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_13_5		(0x03 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_15		(0x02 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_16_5		(0x01 << RK3308_AGC_PGA_GAIN_SFT)
++#define RK3308_AGC_PGA_GAIN_NDB_18		(0x00 << RK3308_AGC_PGA_GAIN_SFT)
++
++/*
++ * RK3308_ALC_L_DIG_CON04 - REG: 0x0050 + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON04 - REG: 0x0090 + ch * 0xc0
++ */
++#define RK3308_AGC_SLOW_CLK_EN			(0x1 << 3)
++#define RK3308_AGC_SLOW_CLK_DIS			(0x0 << 3)
++#define RK3308_AGC_APPROX_RATE_SFT		0
++#define RK3308_AGC_APPROX_RATE_MSK		(0x7 << RK3308_AGC_APPROX_RATE_SFT)
++#define RK3308_AGC_APPROX_RATE_8K		(0x7 << RK3308_AGC_APPROX_RATE_SFT)
++#define RK3308_AGC_APPROX_RATE_12K		(0x6 << RK3308_AGC_APPROX_RATE_SFT)
++#define RK3308_AGC_APPROX_RATE_16K		(0x5 << RK3308_AGC_APPROX_RATE_SFT)
++#define RK3308_AGC_APPROX_RATE_24K		(0x4 << RK3308_AGC_APPROX_RATE_SFT)
++#define RK3308_AGC_APPROX_RATE_32K		(0x3 << RK3308_AGC_APPROX_RATE_SFT)
++#define RK3308_AGC_APPROX_RATE_44_1K		(0x2 << RK3308_AGC_APPROX_RATE_SFT)
++#define RK3308_AGC_APPROX_RATE_48K		(0x1 << RK3308_AGC_APPROX_RATE_SFT)
++#define RK3308_AGC_APPROX_RATE_96K		(0x0 << RK3308_AGC_APPROX_RATE_SFT)
++
++/*
++ * RK3308_ALC_L_DIG_CON05 - REG: 0x0054 + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON05 - REG: 0x0094 + ch * 0xc0
++ */
++#define RK3308_AGC_LO_8BITS_AGC_MAX_MSK		0xff
++
++/*
++ * RK3308_ALC_L_DIG_CON06 - REG: 0x0058 + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON06 - REG: 0x0098 + ch * 0xc0
++ */
++#define RK3308_AGC_HI_8BITS_AGC_MAX_MSK		0xff
++
++/*
++ * RK3308_ALC_L_DIG_CON07 - REG: 0x005c + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON07 - REG: 0x009c + ch * 0xc0
++ */
++#define RK3308_AGC_LO_8BITS_AGC_MIN_MSK		0xff
++
++/*
++ * RK3308_ALC_L_DIG_CON08 - REG: 0x0060 + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON08 - REG: 0x00a0 + ch * 0xc0
++ */
++#define RK3308_AGC_HI_8BITS_AGC_MIN_MSK		0xff
++
++/*
++ * RK3308_ALC_L_DIG_CON09 - REG: 0x0064 + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON09 - REG: 0x00a4 + ch * 0xc0
++ */
++#define RK3308_AGC_FUNC_SEL_MSK			(0x1 << 6)
++#define RK3308_AGC_FUNC_SEL_EN			(0x1 << 6)
++#define RK3308_AGC_FUNC_SEL_DIS			(0x0 << 6)
++#define RK3308_AGC_MAX_GAIN_PGA_SFT		3
++#define RK3308_AGC_MAX_GAIN_PGA_MSK		(0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT)
++#define RK3308_AGC_MAX_GAIN_PGA_PDB_28_5	(0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT)
++#define RK3308_AGC_MAX_GAIN_PGA_PDB_22_5	(0x6 << RK3308_AGC_MAX_GAIN_PGA_SFT)
++#define RK3308_AGC_MAX_GAIN_PGA_PDB_16_5	(0x5 << RK3308_AGC_MAX_GAIN_PGA_SFT)
++#define RK3308_AGC_MAX_GAIN_PGA_PDB_10_5	(0x4 << RK3308_AGC_MAX_GAIN_PGA_SFT)
++#define RK3308_AGC_MAX_GAIN_PGA_PDB_4_5		(0x3 << RK3308_AGC_MAX_GAIN_PGA_SFT)
++#define RK3308_AGC_MAX_GAIN_PGA_NDB_1_5		(0x2 << RK3308_AGC_MAX_GAIN_PGA_SFT)
++#define RK3308_AGC_MAX_GAIN_PGA_NDB_7_5		(0x1 << RK3308_AGC_MAX_GAIN_PGA_SFT)
++#define RK3308_AGC_MAX_GAIN_PGA_NDB_13_5	(0x0 << RK3308_AGC_MAX_GAIN_PGA_SFT)
++#define RK3308_AGC_MIN_GAIN_PGA_SFT		0
++#define RK3308_AGC_MIN_GAIN_PGA_MSK		(0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT)
++#define RK3308_AGC_MIN_GAIN_PGA_PDB_24		(0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT)
++#define RK3308_AGC_MIN_GAIN_PGA_PDB_18		(0x6 << RK3308_AGC_MIN_GAIN_PGA_SFT)
++#define RK3308_AGC_MIN_GAIN_PGA_PDB_12		(0x5 << RK3308_AGC_MIN_GAIN_PGA_SFT)
++#define RK3308_AGC_MIN_GAIN_PGA_PDB_6		(0x4 << RK3308_AGC_MIN_GAIN_PGA_SFT)
++#define RK3308_AGC_MIN_GAIN_PGA_0DB		(0x3 << RK3308_AGC_MIN_GAIN_PGA_SFT)
++#define RK3308_AGC_MIN_GAIN_PGA_NDB_6		(0x2 << RK3308_AGC_MIN_GAIN_PGA_SFT)
++#define RK3308_AGC_MIN_GAIN_PGA_NDB_12		(0x1 << RK3308_AGC_MIN_GAIN_PGA_SFT)
++#define RK3308_AGC_MIN_GAIN_PGA_NDB_18		(0x0 << RK3308_AGC_MIN_GAIN_PGA_SFT)
++
++/*
++ * RK3308_ALC_L_DIG_CON12 - REG: 0x0068 + ch * 0xc0
++ * RK3308_ALC_R_DIG_CON12 - REG: 0x00a8 + ch * 0xc0
++ */
++#define RK3308_AGC_GAIN_MSK			0x1f
++
++/* RK3308_DAC_DIG_CON01 - REG: 0x0304 */
++#define RK3308_DAC_I2S_LRC_POL_MSK		(0x1 << 7)
++#define RK3308_DAC_I2S_LRC_POL_REVERSAL		(0x1 << 7)
++#define RK3308_DAC_I2S_LRC_POL_NORMAL		(0x0 << 7)
++#define RK3308_DAC_I2S_VALID_LEN_SFT		5
++#define RK3308_DAC_I2S_VALID_LEN_MSK		(0x3 << RK3308_DAC_I2S_VALID_LEN_SFT)
++#define RK3308_DAC_I2S_VALID_LEN_32BITS		(0x3 << RK3308_DAC_I2S_VALID_LEN_SFT)
++#define RK3308_DAC_I2S_VALID_LEN_24BITS		(0x2 << RK3308_DAC_I2S_VALID_LEN_SFT)
++#define RK3308_DAC_I2S_VALID_LEN_20BITS		(0x1 << RK3308_DAC_I2S_VALID_LEN_SFT)
++#define RK3308_DAC_I2S_VALID_LEN_16BITS		(0x0 << RK3308_DAC_I2S_VALID_LEN_SFT)
++#define RK3308_DAC_I2S_MODE_SFT			3
++#define RK3308_DAC_I2S_MODE_MSK			(0x3 << RK3308_DAC_I2S_MODE_SFT)
++#define RK3308_DAC_I2S_MODE_PCM			(0x3 << RK3308_DAC_I2S_MODE_SFT)
++#define RK3308_DAC_I2S_MODE_I2S			(0x2 << RK3308_DAC_I2S_MODE_SFT)
++#define RK3308_DAC_I2S_MODE_LJ			(0x1 << RK3308_DAC_I2S_MODE_SFT)
++#define RK3308_DAC_I2S_MODE_RJ			(0x0 << RK3308_DAC_I2S_MODE_SFT)
++#define RK3308_DAC_I2S_LR_MSK			(0x1 << 2)
++#define RK3308_DAC_I2S_LR_SWAP			(0x1 << 2)
++#define RK3308_DAC_I2S_LR_NORMAL		(0x0 << 2)
++
++/* RK3308_DAC_DIG_CON02 - REG: 0x0308 */
++#define RK3308_DAC_IO_MODE_MSK			(0x1 << 5)
++#define RK3308_DAC_IO_MODE_MASTER		(0x1 << 5)
++#define RK3308_DAC_IO_MODE_SLAVE		(0x0 << 5)
++#define RK3308_DAC_MODE_MSK			(0x1 << 4)
++#define RK3308_DAC_MODE_MASTER			(0x1 << 4)
++#define RK3308_DAC_MODE_SLAVE			(0x0 << 4)
++#define RK3308_DAC_I2S_FRAME_LEN_SFT		2
++#define RK3308_DAC_I2S_FRAME_LEN_MSK		(0x3 << RK3308_DAC_I2S_FRAME_LEN_SFT)
++#define RK3308_DAC_I2S_FRAME_32BITS		(0x3 << RK3308_DAC_I2S_FRAME_LEN_SFT)
++#define RK3308_DAC_I2S_FRAME_24BITS		(0x2 << RK3308_DAC_I2S_FRAME_LEN_SFT)
++#define RK3308_DAC_I2S_FRAME_20BITS		(0x1 << RK3308_DAC_I2S_FRAME_LEN_SFT)
++#define RK3308_DAC_I2S_FRAME_16BITS		(0x0 << RK3308_DAC_I2S_FRAME_LEN_SFT)
++#define RK3308_DAC_I2S_MSK			(0x1 << 1)
++#define RK3308_DAC_I2S_WORK			(0x1 << 1)
++#define RK3308_DAC_I2S_RESET			(0x0 << 1)
++#define RK3308_DAC_I2S_BIT_CLK_POL_MSK		(0x1 << 0)
++#define RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL	(0x1 << 0)
++#define RK3308_DAC_I2S_BIT_CLK_POL_NORMAL	(0x0 << 0)
++
++/* RK3308_DAC_DIG_CON03 - REG: 0x030C */
++#define RK3308_DAC_L_CH_BIST_SFT		2
++#define RK3308_DAC_L_CH_BIST_MSK		(0x3 << RK3308_DAC_L_CH_BIST_SFT)
++#define RK3308_DAC_L_CH_BIST_LEFT		(0x3 << RK3308_DAC_L_CH_BIST_SFT) /* normal mode */
++#define RK3308_DAC_L_CH_BIST_CUBE		(0x2 << RK3308_DAC_L_CH_BIST_SFT)
++#define RK3308_DAC_L_CH_BIST_SINE		(0x1 << RK3308_DAC_L_CH_BIST_SFT)
++#define RK3308_DAC_L_CH_BIST_RIGHT		(0x0 << RK3308_DAC_L_CH_BIST_SFT) /* normal mode */
++#define RK3308_DAC_R_CH_BIST_SFT		0
++#define RK3308_DAC_R_CH_BIST_MSK		(0x3 << RK3308_DAC_R_CH_BIST_SFT)
++#define RK3308_DAC_R_CH_BIST_LEFT		(0x3 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */
++#define RK3308_DAC_R_CH_BIST_CUBE		(0x2 << RK3308_DAC_R_CH_BIST_SFT)
++#define RK3308_DAC_R_CH_BIST_SINE		(0x1 << RK3308_DAC_R_CH_BIST_SFT)
++#define RK3308_DAC_R_CH_BIST_RIGHT		(0x0 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */
++
++/* RK3308_DAC_DIG_CON05 - REG: 0x0314 */
++#define RK3308_DAC_L_REG_CTL_INDATA		(0x1 << 2)
++#define RK3308_DAC_L_NORMAL_DATA		(0x0 << 2)
++#define RK3308_DAC_R_REG_CTL_INDATA		(0x1 << 1)
++#define RK3308_DAC_R_NORMAL_DATA		(0x0 << 1)
++
++/* RK3308_DAC_DIG_CON10 - REG: 0x0328 */
++#define RK3308_DAC_DATA_HI4(x)			(x & 0xf) /* Need to RK3308_DAC_x_REG_CTL_INDATA */
++
++/* RK3308_DAC_DIG_CON11 - REG: 0x032c */
++#define RK3308_DAC_DATA_LO8(x)			(x & 0xff) /* Need to RK3308_DAC_x_REG_CTL_INDATA */
++
++/* RK3308_ADC_ANA_CON00 - REG: 0x0340 */
++#define RK3308_ADC_CH1_CH2_MIC_ALL_MSK		(0xff << 0)
++#define RK3308_ADC_CH1_CH2_MIC_ALL		0xff
++#define RK3308_ADC_CH2_MIC_UNMUTE		(0x1 << 7)
++#define RK3308_ADC_CH2_MIC_MUTE			(0x0 << 7)
++#define RK3308_ADC_CH2_MIC_WORK			(0x1 << 6)
++#define RK3308_ADC_CH2_MIC_INIT			(0x0 << 6)
++#define RK3308_ADC_CH2_MIC_EN			(0x1 << 5)
++#define RK3308_ADC_CH2_MIC_DIS			(0x0 << 5)
++#define RK3308_ADC_CH2_BUF_REF_EN		(0x1 << 4)
++#define RK3308_ADC_CH2_BUF_REF_DIS		(0x0 << 4)
++#define RK3308_ADC_CH1_MIC_UNMUTE		(0x1 << 3)
++#define RK3308_ADC_CH1_MIC_MUTE			(0x0 << 3)
++#define RK3308_ADC_CH1_MIC_WORK			(0x1 << 2)
++#define RK3308_ADC_CH1_MIC_INIT			(0x0 << 2)
++#define RK3308_ADC_CH1_MIC_EN			(0x1 << 1)
++#define RK3308_ADC_CH1_MIC_DIS			(0x0 << 1)
++#define RK3308_ADC_CH1_BUF_REF_EN		(0x1 << 0)
++#define RK3308_ADC_CH1_BUF_REF_DIS		(0x0 << 0)
++
++/* RK3308_ADC_ANA_CON01 - REG: 0x0344 */
++#define RK3308_ADC_CH2_MIC_GAIN_SFT		4
++#define RK3308_ADC_CH2_MIC_GAIN_MSK		(0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT)
++#define RK3308_ADC_CH2_MIC_GAIN_30DB		(0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT)
++#define RK3308_ADC_CH2_MIC_GAIN_20DB		(0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT)
++#define RK3308_ADC_CH2_MIC_GAIN_6DB		(0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT)
++#define RK3308_ADC_CH2_MIC_GAIN_0DB		(0x0 << RK3308_ADC_CH2_MIC_GAIN_SFT)
++#define RK3308_ADC_CH1_MIC_GAIN_SFT		0
++#define RK3308_ADC_CH1_MIC_GAIN_MSK		(0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT)
++#define RK3308_ADC_CH1_MIC_GAIN_30DB		(0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT)
++#define RK3308_ADC_CH1_MIC_GAIN_20DB		(0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT)
++#define RK3308_ADC_CH1_MIC_GAIN_6DB		(0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT)
++#define RK3308_ADC_CH1_MIC_GAIN_0DB		(0x0 << RK3308_ADC_CH1_MIC_GAIN_SFT)
++
++/* RK3308_ADC_ANA_CON02 - REG: 0x0348 */
++#define RK3308_ADC_CH2_ALC_ZC_MSK		(0x7 << 4)
++#define RK3308_ADC_CH2_ZEROCROSS_DET_EN		(0x1 << 6)
++#define RK3308_ADC_CH2_ZEROCROSS_DET_DIS	(0x0 << 6)
++#define RK3308_ADC_CH2_ALC_WORK			(0x1 << 5)
++#define RK3308_ADC_CH2_ALC_INIT			(0x0 << 5)
++#define RK3308_ADC_CH2_ALC_EN			(0x1 << 4)
++#define RK3308_ADC_CH2_ALC_DIS			(0x0 << 4)
++
++#define RK3308_ADC_CH1_ALC_ZC_MSK		(0x7 << 0)
++#define RK3308_ADC_CH1_ZEROCROSS_DET_EN		(0x1 << 2)
++#define RK3308_ADC_CH1_ZEROCROSS_DET_DIS	(0x0 << 2)
++#define RK3308_ADC_CH1_ALC_WORK			(0x1 << 1)
++#define RK3308_ADC_CH1_ALC_INIT			(0x0 << 1)
++#define RK3308_ADC_CH1_ALC_EN			(0x1 << 0)
++#define RK3308_ADC_CH1_ALC_DIS			(0x0 << 0)
++
++/* RK3308_ADC_ANA_CON03 - REG: 0x034c */
++#define RK3308_ADC_CH1_ALC_GAIN_SFT		0
++#define RK3308_ADC_CH1_ALC_GAIN_MSK		(0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_28_5	(0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_27		(0x1e << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_25_5	(0x1d << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_24		(0x1c << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_22_5	(0x1b << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_21		(0x1a << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_19_5	(0x19 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_18		(0x18 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_16_5	(0x17 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_15		(0x16 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_13_5	(0x15 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_12		(0x14 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_10_5	(0x13 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_9		(0x12 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_7_5		(0x11 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_6		(0x10 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_4_5		(0x0f << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_3		(0x0e << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_PDB_1_5		(0x0d << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_0DB		(0x0c << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_1_5		(0x0b << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_3		(0x0a << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_4_5		(0x09 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_6		(0x08 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_7_5		(0x07 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_9		(0x06 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_10_5	(0x05 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_12		(0x04 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_13_5	(0x03 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_15		(0x02 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_16_5	(0x01 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++#define RK3308_ADC_CH1_ALC_GAIN_NDB_18		(0x00 << RK3308_ADC_CH1_ALC_GAIN_SFT)
++
++/* RK3308_ADC_ANA_CON04 - REG: 0x0350 */
++#define RK3308_ADC_CH2_ALC_GAIN_SFT		0
++#define RK3308_ADC_CH2_ALC_GAIN_MSK		(0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_28_5	(0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_27		(0x1e << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_25_5	(0x1d << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_24		(0x1c << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_22_5	(0x1b << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_21		(0x1a << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_19_5	(0x19 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_18		(0x18 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_16_5	(0x17 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_15		(0x16 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_13_5	(0x15 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_12		(0x14 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_10_5	(0x13 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_9		(0x12 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_7_5		(0x11 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_6		(0x10 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_4_5		(0x0f << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_3		(0x0e << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_PDB_1_5		(0x0d << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_0DB		(0x0c << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_1_5		(0x0b << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_3		(0x0a << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_4_5		(0x09 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_6		(0x08 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_7_5		(0x07 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_9		(0x06 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_10_5	(0x05 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_12		(0x04 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_13_5	(0x03 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_15		(0x02 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_16_5	(0x01 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++#define RK3308_ADC_CH2_ALC_GAIN_NDB_18		(0x00 << RK3308_ADC_CH2_ALC_GAIN_SFT)
++
++/* RK3308_ADC_ANA_CON05 - REG: 0x0354 */
++#define RK3308_ADC_CH2_ADC_CLK_MSK		(0x7 << 4)
++#define RK3308_ADC_CH2_ADC_WORK			(0x1 << 6)
++#define RK3308_ADC_CH2_ADC_INIT			(0x0 << 6)
++#define RK3308_ADC_CH2_ADC_EN			(0x1 << 5)
++#define RK3308_ADC_CH2_ADC_DIS			(0x0 << 5)
++#define RK3308_ADC_CH2_CLK_EN			(0x1 << 4)
++#define RK3308_ADC_CH2_CLK_DIS			(0x0 << 4)
++
++#define RK3308_ADC_CH1_ADC_CLK_MSK		(0x7 << 0)
++#define RK3308_ADC_CH1_ADC_WORK			(0x1 << 2)
++#define RK3308_ADC_CH1_ADC_INIT			(0x0 << 2)
++#define RK3308_ADC_CH1_ADC_EN			(0x1 << 1)
++#define RK3308_ADC_CH1_ADC_DIS			(0x0 << 1)
++#define RK3308_ADC_CH1_CLK_EN			(0x1 << 0)
++#define RK3308_ADC_CH1_CLK_DIS			(0x0 << 0)
++
++/* RK3308_ADC_ANA_CON06 - REG: 0x0358 */
++#define RK3308_ADC_CURRENT_MSK			(0x1 << 0)
++#define RK3308_ADC_CURRENT_EN			(0x1 << 0)
++#define RK3308_ADC_CURRENT_DIS			(0x0 << 0)
++
++/* RK3308_ADC_ANA_CON07 - REG: 0x035c */
++/* Note: The register configuration is only valid for ADC2 */
++#define RK3308_ADC_CH2_IN_SEL_SFT		6
++#define RK3308_ADC_CH2_IN_SEL_MSK		(0x3 << RK3308_ADC_CH2_IN_SEL_SFT)
++#define RK3308_ADC_CH2_IN_LINEIN_MIC		(0x3 << RK3308_ADC_CH2_IN_SEL_SFT)
++#define RK3308_ADC_CH2_IN_LINEIN		(0x2 << RK3308_ADC_CH2_IN_SEL_SFT)
++#define RK3308_ADC_CH2_IN_MIC			(0x1 << RK3308_ADC_CH2_IN_SEL_SFT)
++#define RK3308_ADC_CH2_IN_NONE			(0x0 << RK3308_ADC_CH2_IN_SEL_SFT)
++/* Note: The register configuration is only valid for ADC1 */
++#define RK3308_ADC_CH1_IN_SEL_SFT		4
++#define RK3308_ADC_CH1_IN_SEL_MSK		(0x3 << RK3308_ADC_CH1_IN_SEL_SFT)
++#define RK3308_ADC_CH1_IN_LINEIN_MIC		(0x3 << RK3308_ADC_CH1_IN_SEL_SFT)
++#define RK3308_ADC_CH1_IN_LINEIN		(0x2 << RK3308_ADC_CH1_IN_SEL_SFT)
++#define RK3308_ADC_CH1_IN_MIC			(0x1 << RK3308_ADC_CH1_IN_SEL_SFT)
++#define RK3308_ADC_CH1_IN_NONE			(0x0 << RK3308_ADC_CH1_IN_SEL_SFT)
++
++#define RK3308_ADC_MIC_BIAS_BUF_EN		(0x1 << 3)
++#define RK3308_ADC_MIC_BIAS_BUF_DIS		(0x0 << 3)
++#define RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT	0
++#define RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK	(0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
++#define RK3308_ADC_MICBIAS_VOLT_0_85		(0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
++#define RK3308_ADC_MICBIAS_VOLT_0_8		(0x6 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
++#define RK3308_ADC_MICBIAS_VOLT_0_75		(0x5 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
++#define RK3308_ADC_MICBIAS_VOLT_0_7		(0x4 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
++#define RK3308_ADC_MICBIAS_VOLT_0_65		(0x3 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
++#define RK3308_ADC_MICBIAS_VOLT_0_6		(0x2 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
++#define RK3308_ADC_MICBIAS_VOLT_0_55		(0x1 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
++#define RK3308_ADC_MICBIAS_VOLT_0_5		(0x0 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
++
++/* RK3308_ADC_ANA_CON08 - REG: 0x0360 */
++#define RK3308_ADC_MICBIAS_CURRENT_MSK		(0x1 << 4)
++#define RK3308_ADC_MICBIAS_CURRENT_EN		(0x1 << 4)
++#define RK3308_ADC_MICBIAS_CURRENT_DIS		(0x0 << 4)
++
++/* RK3308_ADC_ANA_CON10 - REG: 0x0368 */
++#define RK3308_ADC_REF_EN			(0x1 << 7)
++#define RK3308_ADC_REF_DIS			(0x0 << 7)
++#define RK3308_ADC_CURRENT_CHARGE_SFT		0
++#define RK3308_ADC_CURRENT_CHARGE_MSK		(0x7f << RK3308_ADC_CURRENT_CHARGE_SFT)
++#define RK3308_ADC_DONT_SEL_ALL			(0x7f << RK3308_ADC_CURRENT_CHARGE_SFT)
++/*
++ * 0: Choose the current I
++ * 1: Don't choose the current I
++ */
++#define RK3308_ADC_SEL_I_1(x)			((x & 0x1) << 6)
++#define RK3308_ADC_SEL_I_2(x)			((x & 0x1) << 5)
++#define RK3308_ADC_SEL_I_4(x)			((x & 0x1) << 4)
++#define RK3308_ADC_SEL_I_8(x)			((x & 0x1) << 3)
++#define RK3308_ADC_SEL_I_16(x)			((x & 0x1) << 2)
++#define RK3308_ADC_SEL_I_32(x)			((x & 0x1) << 1)
++#define RK3308_ADC_SEL_I_64(x)			((x & 0x1) << 0)
++
++/* RK3308_ADC_ANA_CON11 - REG: 0x036c */
++#define RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK	(0x1 << 1)
++#define RK3308_ADC_ALCR_CON_GAIN_PGAR_EN	(0x1 << 1)
++#define RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS	(0x0 << 1)
++#define RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK	(0x1 << 0)
++#define RK3308_ADC_ALCL_CON_GAIN_PGAL_EN	(0x1 << 0)
++#define RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS	(0x0 << 0)
++
++/* RK3308_DAC_ANA_CON00 - REG: 0x0440 */
++#define RK3308_DAC_HEADPHONE_DET_EN		(0x1 << 1)
++#define RK3308_DAC_HEADPHONE_DET_DIS		(0x0 << 1)
++#define RK3308_DAC_CURRENT_MSK			(0x1 << 0)
++#define RK3308_DAC_CURRENT_EN			(0x1 << 0)
++#define RK3308_DAC_CURRENT_DIS			(0x0 << 0)
++
++/* RK3308_DAC_ANA_CON01 - REG: 0x0444 */
++#define RK3308_DAC_BUF_REF_R_MSK		(0x1 << 6)
++#define RK3308_DAC_BUF_REF_R_EN			(0x1 << 6)
++#define RK3308_DAC_BUF_REF_R_DIS		(0x0 << 6)
++#define RK3308_DAC_POP_SOUND_R_SFT		4
++#define RK3308_DAC_POP_SOUND_R_MSK		(0x3 << RK3308_DAC_POP_SOUND_R_SFT)
++#define RK3308_DAC_POP_SOUND_R_WORK		(0x2 << RK3308_DAC_POP_SOUND_R_SFT)
++#define RK3308_DAC_POP_SOUND_R_INIT		(0x1 << RK3308_DAC_POP_SOUND_R_SFT)
++#define RK3308_DAC_BUF_REF_L_MSK		(0x1 << 2)
++#define RK3308_DAC_BUF_REF_L_EN			(0x1 << 2)
++#define RK3308_DAC_BUF_REF_L_DIS		(0x0 << 2)
++#define RK3308_DAC_POP_SOUND_L_SFT		0
++#define RK3308_DAC_POP_SOUND_L_MSK		(0x3 << RK3308_DAC_POP_SOUND_L_SFT)
++#define RK3308_DAC_POP_SOUND_L_WORK		(0x2 << RK3308_DAC_POP_SOUND_L_SFT)
++#define RK3308_DAC_POP_SOUND_L_INIT		(0x1 << RK3308_DAC_POP_SOUND_L_SFT)
++
++/* RK3308_DAC_ANA_CON02 - REG: 0x0448 */
++#define RK3308_DAC_R_DAC_WORK			(0x1 << 7)
++#define RK3308_DAC_R_DAC_INIT			(0x0 << 7)
++#define RK3308_DAC_R_DAC_EN			(0x1 << 6)
++#define RK3308_DAC_R_DAC_DIS			(0x0 << 6)
++#define RK3308_DAC_R_CLK_EN			(0x1 << 5)
++#define RK3308_DAC_R_CLK_DIS			(0x0 << 5)
++#define RK3308_DAC_R_REF_EN			(0x1 << 4)
++#define RK3308_DAC_R_REF_DIS			(0x0 << 4)
++#define RK3308_DAC_L_DAC_WORK			(0x1 << 3)
++#define RK3308_DAC_L_DAC_INIT			(0x0 << 3)
++#define RK3308_DAC_L_DAC_EN			(0x1 << 2)
++#define RK3308_DAC_L_DAC_DIS			(0x0 << 2)
++#define RK3308_DAC_L_CLK_EN			(0x1 << 1)
++#define RK3308_DAC_L_CLK_DIS			(0x0 << 1)
++#define RK3308_DAC_L_REF_EN			(0x1 << 0)
++#define RK3308_DAC_L_REF_DIS			(0x0 << 0)
++
++/* RK3308_DAC_ANA_CON03 - REG: 0x044c */
++#define RK3308_DAC_R_HPOUT_WORK			(0x1 << 6)
++#define RK3308_DAC_R_HPOUT_INIT			(0x0 << 6)
++#define RK3308_DAC_R_HPOUT_EN			(0x1 << 5)
++#define RK3308_DAC_R_HPOUT_DIS			(0x0 << 5)
++#define RK3308_DAC_R_HPOUT_UNMUTE		(0x1 << 4)
++#define RK3308_DAC_R_HPOUT_MUTE			(0x0 << 4)
++#define RK3308_DAC_L_HPOUT_WORK			(0x1 << 2)
++#define RK3308_DAC_L_HPOUT_INIT			(0x0 << 2)
++#define RK3308_DAC_L_HPOUT_EN			(0x1 << 1)
++#define RK3308_DAC_L_HPOUT_DIS			(0x0 << 1)
++#define RK3308_DAC_L_HPOUT_UNMUTE		(0x1 << 0)
++#define RK3308_DAC_L_HPOUT_MUTE			(0x0 << 0)
++
++/* RK3308_DAC_ANA_CON04 - REG: 0x0450 */
++#define RK3308_DAC_R_GAIN_SFT			6
++#define RK3308_DAC_R_GAIN_MSK			(0x3 << RK3308_DAC_R_GAIN_SFT)
++#define RK3308_DAC_R_GAIN_0DB			(0x3 << RK3308_DAC_R_GAIN_SFT)
++#define RK3308_DAC_R_GAIN_PDB_1_5		(0x2 << RK3308_DAC_R_GAIN_SFT)
++#define RK3308_DAC_R_GAIN_PDB_3			(0x1 << RK3308_DAC_R_GAIN_SFT)
++#define RK3308_DAC_R_GAIN_PDB_6			(0x0 << RK3308_DAC_R_GAIN_SFT)
++#define RK3308_DAC_R_LINEOUT_UNMUTE		(0x1 << 5)
++#define RK3308_DAC_R_LINEOUT_MUTE		(0x0 << 5)
++#define RK3308_DAC_R_LINEOUT_EN			(0x1 << 4)
++#define RK3308_DAC_R_LINEOUT_DIS		(0x0 << 4)
++#define RK3308_DAC_L_GAIN_SFT			2
++#define RK3308_DAC_L_GAIN_MSK			(0x3 << RK3308_DAC_L_GAIN_SFT)
++#define RK3308_DAC_L_GAIN_0DB			(0x3 << RK3308_DAC_L_GAIN_SFT)
++#define RK3308_DAC_L_GAIN_PDB_1_5		(0x2 << RK3308_DAC_L_GAIN_SFT)
++#define RK3308_DAC_L_GAIN_PDB_3			(0x1 << RK3308_DAC_L_GAIN_SFT)
++#define RK3308_DAC_L_GAIN_PDB_6			(0x0 << RK3308_DAC_L_GAIN_SFT)
++#define RK3308_DAC_L_LINEOUT_UNMUTE		(0x1 << 1)
++#define RK3308_DAC_L_LINEOUT_MUTE		(0x0 << 1)
++#define RK3308_DAC_L_LINEOUT_EN			(0x1 << 0)
++#define RK3308_DAC_L_LINEOUT_DIS		(0x0 << 0)
++
++/* RK3308_DAC_ANA_CON05 - REG: 0x0454, step is 1.5db */
++#define RK3308_DAC_L_HPOUT_GAIN_SFT		0
++#define RK3308_DAC_L_HPOUT_GAIN_MSK		(0x1f << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_PDB_6		(0x1e << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_PDB_4_5		(0x1d << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_PDB_3		(0x1c << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_PDB_1_5		(0x1b << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_0DB		(0x1a << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_1_5		(0x19 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_3		(0x18 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_4_5		(0x17 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_6		(0x16 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_7_5		(0x15 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_9		(0x14 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_10_5	(0x13 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_12		(0x12 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_13_5	(0x11 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_15		(0x10 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_16_5	(0x0f << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_18		(0x0e << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_19_5	(0x0d << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_21		(0x0c << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_22_5	(0x0b << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_24		(0x0a << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_25_5	(0x09 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_27		(0x08 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_28_5	(0x07 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_30		(0x06 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_31_5	(0x05 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_33		(0x04 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_34_5	(0x03 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_36		(0x02 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_37_5	(0x01 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++#define RK3308_DAC_L_HPOUT_GAIN_NDB_39		(0x00 << RK3308_DAC_L_HPOUT_GAIN_SFT)
++
++/* RK3308_DAC_ANA_CON06 - REG: 0x0458, step is 1.5db */
++#define RK3308_DAC_R_HPOUT_GAIN_SFT		0
++#define RK3308_DAC_R_HPOUT_GAIN_MSK		(0x1f << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_PDB_6		(0x1e << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_PDB_4_5		(0x1d << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_PDB_3		(0x1c << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_PDB_1_5		(0x1b << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_0DB		(0x1a << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_1_5		(0x19 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_3		(0x18 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_4_5		(0x17 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_6		(0x16 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_7_5		(0x15 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_9		(0x14 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_10_5	(0x13 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_12		(0x12 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_13_5	(0x11 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_15		(0x10 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_16_5	(0x0f << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_18		(0x0e << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_19_5	(0x0d << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_21		(0x0c << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_22_5	(0x0b << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_24		(0x0a << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_25_5	(0x09 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_27		(0x08 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_28_5	(0x07 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_30		(0x06 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_31_5	(0x05 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_33		(0x04 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_34_5	(0x03 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_36		(0x02 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_37_5	(0x01 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++#define RK3308_DAC_R_HPOUT_GAIN_NDB_39		(0x00 << RK3308_DAC_R_HPOUT_GAIN_SFT)
++
++/* RK3308_DAC_ANA_CON12 - REG: 0x0470 */
++#define RK3308_DAC_R_HPMIX_SEL_SFT		6
++#define RK3308_DAC_R_HPMIX_SEL_MSK		(0x3 << RK3308_DAC_R_HPMIX_SEL_SFT)
++#define RK3308_DAC_R_HPMIX_LINEIN_I2S		(0x3 << RK3308_DAC_R_HPMIX_SEL_SFT)
++#define RK3308_DAC_R_HPMIX_LINEIN		(0x2 << RK3308_DAC_R_HPMIX_SEL_SFT)
++#define RK3308_DAC_R_HPMIX_I2S			(0x1 << RK3308_DAC_R_HPMIX_SEL_SFT)
++#define RK3308_DAC_R_HPMIX_NONE			(0x0 << RK3308_DAC_R_HPMIX_SEL_SFT)
++#define RK3308_DAC_R_HPMIX_GAIN_SFT		4
++#define RK3308_DAC_R_HPMIX_GAIN_MSK		(0x3 << RK3308_DAC_R_HPMIX_GAIN_SFT)
++#define RK3308_DAC_R_HPMIX_GAIN_0DB		(0x2 << RK3308_DAC_R_HPMIX_GAIN_SFT)
++#define RK3308_DAC_R_HPMIX_GAIN_NDB_6		(0x1 << RK3308_DAC_R_HPMIX_GAIN_SFT)
++#define RK3308_DAC_L_HPMIX_SEL_SFT		2
++#define RK3308_DAC_L_HPMIX_SEL_MSK		(0x3 << RK3308_DAC_L_HPMIX_SEL_SFT)
++#define RK3308_DAC_L_HPMIX_LINEIN_I2S		(0x3 << RK3308_DAC_L_HPMIX_SEL_SFT)
++#define RK3308_DAC_L_HPMIX_LINEIN		(0x2 << RK3308_DAC_L_HPMIX_SEL_SFT)
++#define RK3308_DAC_L_HPMIX_I2S			(0x1 << RK3308_DAC_L_HPMIX_SEL_SFT)
++#define RK3308_DAC_L_HPMIX_NONE			(0x0 << RK3308_DAC_L_HPMIX_SEL_SFT)
++#define RK3308_DAC_L_HPMIX_GAIN_SFT		0
++#define RK3308_DAC_L_HPMIX_GAIN_MSK		(0x3 << RK3308_DAC_L_HPMIX_GAIN_SFT)
++#define RK3308_DAC_L_HPMIX_GAIN_0DB		(0x2 << RK3308_DAC_L_HPMIX_GAIN_SFT)
++#define RK3308_DAC_L_HPMIX_GAIN_NDB_6		(0x1 << RK3308_DAC_L_HPMIX_GAIN_SFT)
++
++/* RK3308_DAC_ANA_CON13 - REG: 0x0474 */
++#define RK3308_DAC_R_HPMIX_UNMUTE		(0x1 << 6)
++#define RK3308_DAC_R_HPMIX_MUTE			(0x0 << 6)
++#define RK3308_DAC_R_HPMIX_WORK			(0x1 << 5)
++#define RK3308_DAC_R_HPMIX_INIT			(0x0 << 5)
++#define RK3308_DAC_R_HPMIX_EN			(0x1 << 4)
++#define RK3308_DAC_R_HPMIX_DIS			(0x0 << 4)
++#define RK3308_DAC_L_HPMIX_UNMUTE		(0x1 << 2)
++#define RK3308_DAC_L_HPMIX_MUTE			(0x0 << 2)
++#define RK3308_DAC_L_HPMIX_WORK			(0x1 << 1)
++#define RK3308_DAC_L_HPMIX_INIT			(0x0 << 1)
++#define RK3308_DAC_L_HPMIX_EN			(0x1 << 0)
++#define RK3308_DAC_L_HPMIX_DIS			(0x0 << 0)
++
++#define RK3308_HIFI				0x0
++
++#endif /* __RK3308_CODEC_H__ */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch.disabled b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch.disabled
new file mode 100644
index 000000000000..8c83b14e0c8c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch.disabled
@@ -0,0 +1,6738 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ashthespy <ashthespy@gmail.com>
+Date: Mon, 3 Feb 2020 17:13:59 +0100
+Subject: Sync `rk3308_codec` to BSP tree
+
+---
+ Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.txt |   78 +
+ sound/soc/codecs/rk3308_codec.c                                   | 5687 ++++++++--
+ sound/soc/codecs/rk3308_codec.h                                   |  217 +-
+ sound/soc/codecs/rk3308_codec_provider.h                          |   28 +
+ 4 files changed, 4894 insertions(+), 1116 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.txt
+new file mode 100644
+index 000000000000..e20bbd73e37e
+--- /dev/null
++++ b/Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.txt
+@@ -0,0 +1,78 @@
++* Rockchip RK3308 Internal Codec
++
++Required properties:
++
++- compatible: "rockchip,rk3308-codec"
++- reg: The physical base address of the controller and length of memory
++  mapped region.
++- rockchip,grf: The phandle of the syscon node for GRF register.
++- clocks: A list of phandle + clock-specifer pairs, one for each entry in
++  clock-names.
++- clock-names: It should be "acodec".
++- resets : Must contain an entry for each entry in reset-names.
++- reset-names : Must include the following entries: "acodec-reset".
++
++Optional properties:
++- rockchip,enable-all-adcs: This is a boolean type property, that shows whether
++  force enable all of ADCs. The following shows the relationship between grps
++  and ADC:
++  * grp 0 -- select ADC1 / ADC2
++  * grp 1 -- select ADC3 / ADC4
++  * grp 2 -- select ADC5 / ADC6
++  * grp 3 -- select ADC7 / ADC8
++  If the property is not used, the enabled ADC groups refer to needed channels
++  via configure hw_params.
++
++- rockchip,adc-grps-route: This is a variable length array, that shows the
++  mapping route of ACODEC sdo to I2S sdi. By default, they are one-to-one
++  mapping:
++  * sdi_0 <-- sdo_0
++  * sdi_1 <-- sdo_1
++  * sdi_2 <-- sdo_2
++  * sdi_3 <-- sdo_3
++  If you would like to change the route mapping like this:
++  * sdi_0 <-- sdo_3
++  * sdi_1 <-- sdo_0
++  * sdi_2 <-- sdo_2
++  * sdi_3 <-- sdo_1
++  You need to add the property on dts:
++  - rockchip,adc-grps-route = <3 0 2 1>;
++
++- rockchip,delay-loopback-handle-ms: This property points out that the delay for
++  handling ADC after enable PAs during loopback.
++- rockchip,delay-start-play-ms: This property points out the delay ms of start
++  playback according to different amplifier performance.
++- rockchip,en-always-grps: This property will keep the needed ADCs enabled
++  always after enabling once.
++- rockchip,loopback-grp: It points out the ADC group which is the loopback used.
++- rockchip,no-deep-low-power: The codec will not enter deep low power mode
++  during suspend.
++- rockchip,no-hp-det: If there is no headphone on boards, we don't need to
++  enable headphone detection.
++- rockchip,micbias1: Using internal micbias1 supply which are from codec.
++- rockchip,micbias2: Using internal micbias2 supply which are from codec.
++- rockchip,hp-jack-reversed;: To detect headphone via the reversed jack.
++- hp-ctl-gpios: The gpio of head phone controller.
++- pa-drv-gpios: The gpio of poweramplifier controller
++- rockchip,delay-pa-drv-ms: This property points out that the delay for
++  power on amplifier
++- spk-ctl-gpios: The gpio of speak controller.
++- micbias-en-gpios: The GPIO to enable external micbias.
++- vmicbias-supply: The phandle to the regulator to handle external micbias.
++
++Example for rk3308 internal codec:
++
++acodec: acodec@ff560000 {
++	compatible = "rockchip,rk3308-codec";
++	reg = <0x0 0xff560000 0x0 0x10000>;
++	rockchip,grf = <&grf>;
++	clocks = <&cru PCLK_ACODEC>;
++	clock-names = "acodec";
++	resets = <&cru SRST_ACODEC_P>;
++	reset-names = "acodec-reset";
++	rockchip,loopback-grp = <0>;
++	hp-ctl-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
++	pa-drv-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
++	spk-ctl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
++	status = "okay";
++};
+diff --git a/sound/soc/codecs/rk3308_codec.c b/sound/soc/codecs/rk3308_codec.c
+index 106f09738dd0..815e22fc346c 100644
+--- a/sound/soc/codecs/rk3308_codec.c
++++ b/sound/soc/codecs/rk3308_codec.c
+@@ -29,1420 +29,4699 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/reset.h>
+ #include <linux/rockchip/grf.h>
+ #include <linux/version.h>
+ #include <sound/core.h>
+ #include <sound/dmaengine_pcm.h>
+ #include <sound/initval.h>
++#include <sound/jack.h>
+ #include <sound/pcm.h>
+ #include <sound/pcm_params.h>
++#include <sound/simple_card.h>
+ #include <sound/soc.h>
+ #include <sound/tlv.h>
+ 
+ #include "rk3308_codec.h"
++#include "rk3308_codec_provider.h"
++
++#if defined(CONFIG_DEBUG_FS)
++#include <linux/fs.h>
++#include <linux/debugfs.h>
++#include <linux/seq_file.h>
++#endif
++
++#define CODEC_DRV_NAME			"rk3308-acodec"
++
++#define ADC_GRP_SKIP_MAGIC		0x1001
++#define ADC_LR_GROUP_MAX		4
++#define ADC_STABLE_MS			200
++#define DEBUG_POP_ALWAYS		0
++#define HPDET_POLL_MS			2000
++#define NOT_USED			255
++#define LOOPBACK_HANDLE_MS		100
++#define PA_DRV_MS		        5
++
++#define GRF_SOC_CON1			0x304
++#define GRF_CHIP_ID			0x800
++#define GRF_I2S2_8CH_SDI_SFT		0
++#define GRF_I2S3_4CH_SDI_SFT		8
++#define GRF_I2S1_2CH_SDI_SFT		12
++
++#define GRF_I2S2_8CH_SDI_R_MSK(i, v)	((v >> (i * 2 + GRF_I2S2_8CH_SDI_SFT)) & 0x3)
++#define GRF_I2S2_8CH_SDI_W_MSK(i)	(0x3 << (i * 2 + GRF_I2S2_8CH_SDI_SFT + 16))
++#define GRF_I2S2_8CH_SDI(i, v)		(((v & 0x3) << (i * 2 + GRF_I2S2_8CH_SDI_SFT)) |\
++					 GRF_I2S2_8CH_SDI_W_MSK(i))
++
++#define GRF_I2S3_4CH_SDI_W_MSK(i)	(0x3 << (i * 2 + GRF_I2S3_4CH_SDI_SFT + 16))
++#define GRF_I2S3_4CH_SDI(i, v)		(((v & 0x3) << (i * 2 + GRF_I2S3_4CH_SDI_SFT)) |\
++					 GRF_I2S3_4CH_SDI_W_MSK(i))
++
++#define GRF_I2S1_2CH_SDI_W_MSK		(0x3 << (GRF_I2S1_2CH_SDI_SFT + 16))
++#define GRF_I2S1_2CH_SDI(v)		(((v & 0x3) << GRF_I2S1_2CH_SDI_SFT) |\
++					 GRF_I2S1_2CH_SDI_W_MSK)
++
++#define DETECT_GRF_ACODEC_HPDET_COUNTER		0x0030
++#define DETECT_GRF_ACODEC_HPDET_CON		0x0034
++#define DETECT_GRF_ACODEC_HPDET_STATUS		0x0038
++#define DETECT_GRF_ACODEC_HPDET_STATUS_CLR	0x003c
++
++/* 200ms based on pclk is 100MHz */
++#define DEFAULT_HPDET_COUNT			20000000
++#define HPDET_NEG_IRQ_SFT			1
++#define HPDET_POS_IRQ_SFT			0
++#define HPDET_BOTH_NEG_POS			((1 << HPDET_NEG_IRQ_SFT) |\
++						 (1 << HPDET_POS_IRQ_SFT))
++
++#define ACODEC_VERSION_A			0xa
++#define ACODEC_VERSION_B			0xb
++
++enum {
++	ACODEC_TO_I2S2_8CH = 0,
++	ACODEC_TO_I2S3_4CH,
++	ACODEC_TO_I2S1_2CH,
++};
++
++enum {
++	ADC_GRP0_MICIN = 0,
++	ADC_GRP0_LINEIN
++};
++
++enum {
++	ADC_TYPE_NORMAL = 0,
++	ADC_TYPE_LOOPBACK,
++	ADC_TYPE_DBG,
++	ADC_TYPE_ALL,
++};
++
++enum {
++	DAC_LINEOUT = 0,
++	DAC_HPOUT = 1,
++	DAC_LINEOUT_HPOUT = 11,
++};
++
++enum {
++	EXT_MICBIAS_NONE = 0,
++	EXT_MICBIAS_FUNC1,  /* enable external micbias via GPIO */
++	EXT_MICBIAS_FUNC2,  /* enable external micbias via regulator */
++};
++
++enum {
++	PATH_IDLE = 0,
++	PATH_BUSY,
++};
++
++enum {
++	PM_NORMAL = 0,
++	PM_LLP_DOWN,		/* light low power down */
++	PM_LLP_UP,
++	PM_DLP_DOWN,		/* deep low power down */
++	PM_DLP_UP,
++	PM_DLP_DOWN2,
++	PM_DLP_UP2,
++};
+ 
+ struct rk3308_codec_priv {
+ 	const struct device *plat_dev;
+ 	struct device dev;
+ 	struct reset_control *reset;
+ 	struct regmap *regmap;
++	struct regmap *grf;
++	struct regmap *detect_grf;
+ 	struct clk *pclk;
++	struct clk *mclk_rx;
++	struct clk *mclk_tx;
++	struct gpio_desc *micbias_en_gpio;
++	struct gpio_desc *hp_ctl_gpio;
+ 	struct gpio_desc *spk_ctl_gpio;
+-	int adc_ch;			/* To select ADCs for channel */
+-	int adc_ch0_using_linein;
++	struct gpio_desc *pa_drv_gpio;
++	struct snd_soc_codec *codec;
++	struct snd_soc_jack *hpdet_jack;
++	struct regulator *vcc_micbias;
++	u32 codec_ver;
++
++	/*
++	 * To select ADCs for groups:
++	 *
++	 * grp 0 -- select ADC1 / ADC2
++	 * grp 1 -- select ADC3 / ADC4
++	 * grp 2 -- select ADC5 / ADC6
++	 * grp 3 -- select ADC7 / ADC8
++	 */
++	u32 used_adc_grps;
++	/* The ADC group which is used for loop back */
++	u32 loopback_grp;
++	u32 cur_dbg_grp;
++	u32 en_always_grps[ADC_LR_GROUP_MAX];
++	u32 en_always_grps_num;
++	u32 skip_grps[ADC_LR_GROUP_MAX];
++	u32 i2s_sdis[ADC_LR_GROUP_MAX];
++	u32 to_i2s_grps;
++	u32 delay_loopback_handle_ms;
++	u32 delay_start_play_ms;
++	u32 delay_pa_drv_ms;
++	u32 micbias_num;
++	u32 micbias_volt;
++	int which_i2s;
++	int irq;
++	int adc_grp0_using_linein;
++	int adc_zerocross;
++	/* 0: line out, 1: hp out, 11: lineout and hpout */
++	int dac_output;
++	int dac_path_state;
++
++	int ext_micbias;
++	int pm_state;
++
++	/* AGC L/R Off/on */
++	unsigned int agc_l[ADC_LR_GROUP_MAX];
++	unsigned int agc_r[ADC_LR_GROUP_MAX];
++
++	/* AGC L/R Approximate Sample Rate */
++	unsigned int agc_asr_l[ADC_LR_GROUP_MAX];
++	unsigned int agc_asr_r[ADC_LR_GROUP_MAX];
++
++	/* ADC MIC Mute/Work */
++	unsigned int mic_mute_l[ADC_LR_GROUP_MAX];
++	unsigned int mic_mute_r[ADC_LR_GROUP_MAX];
++
++	/* For the high pass filter */
++	unsigned int hpf_cutoff[ADC_LR_GROUP_MAX];
++
++	/* Only hpout do fade-in and fade-out */
++	unsigned int hpout_l_dgain;
++	unsigned int hpout_r_dgain;
++
++	bool adc_grps_endisable[ADC_LR_GROUP_MAX];
++	bool dac_endisable;
++	bool enable_all_adcs;
++	bool enable_micbias;
++	bool micbias1;
++	bool micbias2;
++	bool hp_jack_reversed;
++	bool hp_plugged;
++	bool loopback_dacs_enabled;
++	bool no_deep_low_power;
++	bool no_hp_det;
++	struct delayed_work hpdet_work;
++	struct delayed_work loopback_work;
++
++#if defined(CONFIG_DEBUG_FS)
++	struct dentry *dbg_codec;
++#endif
+ };
+ 
+-static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_gain_tlv,
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_gain_tlv,
+ 				  -1800, 150, 2850);
+-static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_max_gain_tlv,
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_max_gain_tlv,
+ 				  -1350, 600, 2850);
+-static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_min_gain_tlv,
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_min_gain_tlv,
+ 				  -1800, 600, 2400);
+-static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_mic_gain_tlv,
+-				  0, 600, 3000);
+ static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_alc_gain_tlv,
+ 				  -1800, 150, 2850);
+-static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_gain_tlv,
+-				  0, 150, 600);
++static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_lineout_gain_tlv,
++				  -600, 150, 0);
+ static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpout_gain_tlv,
+ 				  -3900, 150, 600);
+ static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpmix_gain_tlv,
+ 				  -600, 600, 0);
+ 
++static const DECLARE_TLV_DB_RANGE(rk3308_codec_adc_mic_gain_tlv_a,
++	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
++	3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0),
++);
++
++static const DECLARE_TLV_DB_RANGE(rk3308_codec_adc_mic_gain_tlv_b,
++	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
++	1, 1, TLV_DB_SCALE_ITEM(660, 0, 0),
++	2, 2, TLV_DB_SCALE_ITEM(1300, 0, 0),
++	3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0),
++);
++
++static bool handle_loopback(struct rk3308_codec_priv *rk3308);
++
++static int check_micbias(int micbias);
++
++static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308,
++				       int micbias);
++static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308);
++
++static int rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol *kcontrol,
++					struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol *kcontrol,
++					struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol *kcontrol,
++					struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol *kcontrol,
++					struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol,
++				struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol,
++				struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol,
++				struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol,
++				struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol,
++				    struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol,
++				    struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol,
++				     struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol,
++				     struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_mic_gain_get(struct snd_kcontrol *kcontrol,
++				     struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol,
++				     struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol,
++					  struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol,
++					  struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol,
++					 struct snd_ctl_elem_value *ucontrol);
++static int rk3308_codec_main_micbias_put(struct snd_kcontrol *kcontrol,
++					 struct snd_ctl_elem_value *ucontrol);
++
++static const char *offon_text[2] = {
++	[0] = "Off",
++	[1] = "On",
++};
++
++static const char *mute_text[2] = {
++	[0] = "Work",
++	[1] = "Mute",
++};
++
++/* ADC MICBIAS Volt */
++#define MICBIAS_VOLT_NUM		8
++
++#define MICBIAS_VREFx0_5		0
++#define MICBIAS_VREFx0_55		1
++#define MICBIAS_VREFx0_6		2
++#define MICBIAS_VREFx0_65		3
++#define MICBIAS_VREFx0_7		4
++#define MICBIAS_VREFx0_75		5
++#define MICBIAS_VREFx0_8		6
++#define MICBIAS_VREFx0_85		7
++
++static const char *micbias_volts_enum_array[MICBIAS_VOLT_NUM] = {
++	[MICBIAS_VREFx0_5] = "VREFx0_5",
++	[MICBIAS_VREFx0_55] = "VREFx0_55",
++	[MICBIAS_VREFx0_6] = "VREFx0_6",
++	[MICBIAS_VREFx0_65] = "VREFx0_65",
++	[MICBIAS_VREFx0_7] = "VREFx0_7",
++	[MICBIAS_VREFx0_75] = "VREFx0_75",
++	[MICBIAS_VREFx0_8] = "VREFx0_8",
++	[MICBIAS_VREFx0_85] = "VREFx0_85",
++};
++
++static const struct soc_enum rk3308_micbias_volts_enum_array[] = {
++	SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(micbias_volts_enum_array), micbias_volts_enum_array),
++};
++
++/* ADC MICBIAS1 and MICBIAS2 Main Switch */
++static const struct soc_enum rk3308_main_micbias_enum_array[] = {
++	SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text),
++};
++
++static const struct soc_enum rk3308_hpf_enum_array[] = {
++	SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text),
++	SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(offon_text), offon_text),
++	SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(offon_text), offon_text),
++	SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(offon_text), offon_text),
++};
++
++/* ALC AGC Switch */
++static const struct soc_enum rk3308_agc_enum_array[] = {
++	SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text),
++	SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(offon_text), offon_text),
++	SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(offon_text), offon_text),
++	SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(offon_text), offon_text),
++	SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(offon_text), offon_text),
++	SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(offon_text), offon_text),
++	SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(offon_text), offon_text),
++	SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(offon_text), offon_text),
++};
++
++/* ADC MIC Mute/Work Switch */
++static const struct soc_enum rk3308_mic_mute_enum_array[] = {
++	SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(mute_text), mute_text),
++	SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(mute_text), mute_text),
++	SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(mute_text), mute_text),
++	SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(mute_text), mute_text),
++	SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(mute_text), mute_text),
++	SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(mute_text), mute_text),
++	SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(mute_text), mute_text),
++	SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(mute_text), mute_text),
++};
++
++/* ALC AGC Approximate Sample Rate */
++#define AGC_ASR_NUM				8
++
++#define AGC_ASR_96KHZ				0
++#define AGC_ASR_48KHZ				1
++#define AGC_ASR_44_1KHZ				2
++#define AGC_ASR_32KHZ				3
++#define AGC_ASR_24KHZ				4
++#define AGC_ASR_16KHZ				5
++#define AGC_ASR_12KHZ				6
++#define AGC_ASR_8KHZ				7
++
++static const char *agc_asr_text[AGC_ASR_NUM] = {
++	[AGC_ASR_96KHZ] = "96KHz",
++	[AGC_ASR_48KHZ] = "48KHz",
++	[AGC_ASR_44_1KHZ] = "44.1KHz",
++	[AGC_ASR_32KHZ] = "32KHz",
++	[AGC_ASR_24KHZ] = "24KHz",
++	[AGC_ASR_16KHZ] = "16KHz",
++	[AGC_ASR_12KHZ] = "12KHz",
++	[AGC_ASR_8KHZ] = "8KHz",
++};
++
++static const struct soc_enum rk3308_agc_asr_enum_array[] = {
++	SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text),
++	SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text),
++	SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text),
++	SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text),
++	SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text),
++	SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text),
++	SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text),
++	SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text),
++};
++
++static const struct snd_kcontrol_new mic_gains_a[] = {
++	/* ADC MIC */
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Left Volume",
++			   RK3308_ADC_ANA_CON01(0),
++			   RK3308_ADC_CH1_MIC_GAIN_SFT,
++			   RK3308_ADC_CH1_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_a),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Right Volume",
++			   RK3308_ADC_ANA_CON01(0),
++			   RK3308_ADC_CH2_MIC_GAIN_SFT,
++			   RK3308_ADC_CH2_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_a),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Left Volume",
++			   RK3308_ADC_ANA_CON01(1),
++			   RK3308_ADC_CH1_MIC_GAIN_SFT,
++			   RK3308_ADC_CH1_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_a),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Right Volume",
++			   RK3308_ADC_ANA_CON01(1),
++			   RK3308_ADC_CH2_MIC_GAIN_SFT,
++			   RK3308_ADC_CH2_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_a),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Left Volume",
++			   RK3308_ADC_ANA_CON01(2),
++			   RK3308_ADC_CH1_MIC_GAIN_SFT,
++			   RK3308_ADC_CH1_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_a),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Right Volume",
++			   RK3308_ADC_ANA_CON01(2),
++			   RK3308_ADC_CH2_MIC_GAIN_SFT,
++			   RK3308_ADC_CH2_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_a),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Left Volume",
++			   RK3308_ADC_ANA_CON01(3),
++			   RK3308_ADC_CH1_MIC_GAIN_SFT,
++			   RK3308_ADC_CH1_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_a),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Right Volume",
++			   RK3308_ADC_ANA_CON01(3),
++			   RK3308_ADC_CH2_MIC_GAIN_SFT,
++			   RK3308_ADC_CH2_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_a),
++};
++
++static const struct snd_kcontrol_new mic_gains_b[] = {
++	/* ADC MIC */
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Left Volume",
++			   RK3308_ADC_ANA_CON01(0),
++			   RK3308_ADC_CH1_MIC_GAIN_SFT,
++			   RK3308_ADC_CH1_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_b),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Right Volume",
++			   RK3308_ADC_ANA_CON01(0),
++			   RK3308_ADC_CH2_MIC_GAIN_SFT,
++			   RK3308_ADC_CH2_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_b),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Left Volume",
++			   RK3308_ADC_ANA_CON01(1),
++			   RK3308_ADC_CH1_MIC_GAIN_SFT,
++			   RK3308_ADC_CH1_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_b),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Right Volume",
++			   RK3308_ADC_ANA_CON01(1),
++			   RK3308_ADC_CH2_MIC_GAIN_SFT,
++			   RK3308_ADC_CH2_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_b),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Left Volume",
++			   RK3308_ADC_ANA_CON01(2),
++			   RK3308_ADC_CH1_MIC_GAIN_SFT,
++			   RK3308_ADC_CH1_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_b),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Right Volume",
++			   RK3308_ADC_ANA_CON01(2),
++			   RK3308_ADC_CH2_MIC_GAIN_SFT,
++			   RK3308_ADC_CH2_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_b),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Left Volume",
++			   RK3308_ADC_ANA_CON01(3),
++			   RK3308_ADC_CH1_MIC_GAIN_SFT,
++			   RK3308_ADC_CH1_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_b),
++	SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Right Volume",
++			   RK3308_ADC_ANA_CON01(3),
++			   RK3308_ADC_CH2_MIC_GAIN_SFT,
++			   RK3308_ADC_CH2_MIC_GAIN_MAX,
++			   0,
++			   rk3308_codec_mic_gain_get,
++			   rk3308_codec_mic_gain_put,
++			   rk3308_codec_adc_mic_gain_tlv_b),
++};
++
+ static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = {
+-	/* ALC AGC Channel*/
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Volume",
++	/* ALC AGC Group */
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Volume",
+ 			     RK3308_ALC_L_DIG_CON03(0),
++			     RK3308_AGC_PGA_GAIN_SFT,
++			     RK3308_AGC_PGA_GAIN_MIN,
++			     RK3308_AGC_PGA_GAIN_MAX,
++			     0, rk3308_codec_alc_agc_grp_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Volume",
+ 			     RK3308_ALC_R_DIG_CON03(0),
+ 			     RK3308_AGC_PGA_GAIN_SFT,
+-			     RK3308_AGC_PGA_GAIN_NDB_18,
+-			     RK3308_AGC_PGA_GAIN_PDB_28_5,
+-			     0, rk3308_codec_alc_agc_ch_gain_tlv),
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Volume",
++			     RK3308_AGC_PGA_GAIN_MIN,
++			     RK3308_AGC_PGA_GAIN_MAX,
++			     0, rk3308_codec_alc_agc_grp_gain_tlv),
++
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Volume",
+ 			     RK3308_ALC_L_DIG_CON03(1),
++			     RK3308_AGC_PGA_GAIN_SFT,
++			     RK3308_AGC_PGA_GAIN_MIN,
++			     RK3308_AGC_PGA_GAIN_MAX,
++			     0, rk3308_codec_alc_agc_grp_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Volume",
+ 			     RK3308_ALC_R_DIG_CON03(1),
+ 			     RK3308_AGC_PGA_GAIN_SFT,
+-			     RK3308_AGC_PGA_GAIN_NDB_18,
+-			     RK3308_AGC_PGA_GAIN_PDB_28_5,
+-			     0, rk3308_codec_alc_agc_ch_gain_tlv),
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Volume",
++			     RK3308_AGC_PGA_GAIN_MIN,
++			     RK3308_AGC_PGA_GAIN_MAX,
++			     0, rk3308_codec_alc_agc_grp_gain_tlv),
++
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Volume",
+ 			     RK3308_ALC_L_DIG_CON03(2),
++			     RK3308_AGC_PGA_GAIN_SFT,
++			     RK3308_AGC_PGA_GAIN_MIN,
++			     RK3308_AGC_PGA_GAIN_MAX,
++			     0, rk3308_codec_alc_agc_grp_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Volume",
+ 			     RK3308_ALC_R_DIG_CON03(2),
+ 			     RK3308_AGC_PGA_GAIN_SFT,
+-			     RK3308_AGC_PGA_GAIN_NDB_18,
+-			     RK3308_AGC_PGA_GAIN_PDB_28_5,
+-			     0, rk3308_codec_alc_agc_ch_gain_tlv),
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Volume",
++			     RK3308_AGC_PGA_GAIN_MIN,
++			     RK3308_AGC_PGA_GAIN_MAX,
++			     0, rk3308_codec_alc_agc_grp_gain_tlv),
++
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Volume",
+ 			     RK3308_ALC_L_DIG_CON03(3),
++			     RK3308_AGC_PGA_GAIN_SFT,
++			     RK3308_AGC_PGA_GAIN_MIN,
++			     RK3308_AGC_PGA_GAIN_MAX,
++			     0, rk3308_codec_alc_agc_grp_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Volume",
+ 			     RK3308_ALC_R_DIG_CON03(3),
+ 			     RK3308_AGC_PGA_GAIN_SFT,
+-			     RK3308_AGC_PGA_GAIN_NDB_18,
+-			     RK3308_AGC_PGA_GAIN_PDB_28_5,
+-			     0, rk3308_codec_alc_agc_ch_gain_tlv),
++			     RK3308_AGC_PGA_GAIN_MIN,
++			     RK3308_AGC_PGA_GAIN_MAX,
++			     0, rk3308_codec_alc_agc_grp_gain_tlv),
+ 
+ 	/* ALC AGC MAX */
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Max Volume",
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Max Volume",
+ 			     RK3308_ALC_L_DIG_CON09(0),
++			     RK3308_AGC_MAX_GAIN_PGA_SFT,
++			     RK3308_AGC_MAX_GAIN_PGA_MIN,
++			     RK3308_AGC_MAX_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_max_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Max Volume",
+ 			     RK3308_ALC_R_DIG_CON09(0),
+ 			     RK3308_AGC_MAX_GAIN_PGA_SFT,
+-			     RK3308_AGC_MAX_GAIN_PGA_NDB_13_5,
+-			     RK3308_AGC_MAX_GAIN_PGA_PDB_28_5,
+-			     0, rk3308_codec_alc_agc_ch_max_gain_tlv),
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Max Volume",
++			     RK3308_AGC_MAX_GAIN_PGA_MIN,
++			     RK3308_AGC_MAX_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_max_gain_tlv),
++
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Max Volume",
+ 			     RK3308_ALC_L_DIG_CON09(1),
++			     RK3308_AGC_MAX_GAIN_PGA_SFT,
++			     RK3308_AGC_MAX_GAIN_PGA_MIN,
++			     RK3308_AGC_MAX_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_max_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Max Volume",
+ 			     RK3308_ALC_R_DIG_CON09(1),
+ 			     RK3308_AGC_MAX_GAIN_PGA_SFT,
+-			     RK3308_AGC_MAX_GAIN_PGA_NDB_13_5,
+-			     RK3308_AGC_MAX_GAIN_PGA_PDB_28_5,
+-			     0, rk3308_codec_alc_agc_ch_max_gain_tlv),
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Max Volume",
++			     RK3308_AGC_MAX_GAIN_PGA_MIN,
++			     RK3308_AGC_MAX_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_max_gain_tlv),
++
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Max Volume",
+ 			     RK3308_ALC_L_DIG_CON09(2),
++			     RK3308_AGC_MAX_GAIN_PGA_SFT,
++			     RK3308_AGC_MAX_GAIN_PGA_MIN,
++			     RK3308_AGC_MAX_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_max_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Max Volume",
+ 			     RK3308_ALC_R_DIG_CON09(2),
+ 			     RK3308_AGC_MAX_GAIN_PGA_SFT,
+-			     RK3308_AGC_MAX_GAIN_PGA_NDB_13_5,
+-			     RK3308_AGC_MAX_GAIN_PGA_PDB_28_5,
+-			     0, rk3308_codec_alc_agc_ch_max_gain_tlv),
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Max Volume",
++			     RK3308_AGC_MAX_GAIN_PGA_MIN,
++			     RK3308_AGC_MAX_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_max_gain_tlv),
++
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Max Volume",
+ 			     RK3308_ALC_L_DIG_CON09(3),
++			     RK3308_AGC_MAX_GAIN_PGA_SFT,
++			     RK3308_AGC_MAX_GAIN_PGA_MIN,
++			     RK3308_AGC_MAX_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_max_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Max Volume",
+ 			     RK3308_ALC_R_DIG_CON09(3),
+ 			     RK3308_AGC_MAX_GAIN_PGA_SFT,
+-			     RK3308_AGC_MAX_GAIN_PGA_NDB_13_5,
+-			     RK3308_AGC_MAX_GAIN_PGA_PDB_28_5,
+-			     0, rk3308_codec_alc_agc_ch_max_gain_tlv),
++			     RK3308_AGC_MAX_GAIN_PGA_MIN,
++			     RK3308_AGC_MAX_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_max_gain_tlv),
+ 
+ 	/* ALC AGC MIN */
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Min Volume",
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Min Volume",
+ 			     RK3308_ALC_L_DIG_CON09(0),
++			     RK3308_AGC_MIN_GAIN_PGA_SFT,
++			     RK3308_AGC_MIN_GAIN_PGA_MIN,
++			     RK3308_AGC_MIN_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_min_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Min Volume",
+ 			     RK3308_ALC_R_DIG_CON09(0),
+ 			     RK3308_AGC_MIN_GAIN_PGA_SFT,
+-			     RK3308_AGC_MIN_GAIN_PGA_NDB_18,
+-			     RK3308_AGC_MIN_GAIN_PGA_PDB_24,
+-			     0, rk3308_codec_alc_agc_ch_min_gain_tlv),
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Min Volume",
++			     RK3308_AGC_MIN_GAIN_PGA_MIN,
++			     RK3308_AGC_MIN_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_min_gain_tlv),
++
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Min Volume",
+ 			     RK3308_ALC_L_DIG_CON09(1),
++			     RK3308_AGC_MIN_GAIN_PGA_SFT,
++			     RK3308_AGC_MIN_GAIN_PGA_MIN,
++			     RK3308_AGC_MIN_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_min_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Min Volume",
+ 			     RK3308_ALC_R_DIG_CON09(1),
+ 			     RK3308_AGC_MIN_GAIN_PGA_SFT,
+-			     RK3308_AGC_MIN_GAIN_PGA_NDB_18,
+-			     RK3308_AGC_MIN_GAIN_PGA_PDB_24,
+-			     0, rk3308_codec_alc_agc_ch_min_gain_tlv),
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Min Volume",
++			     RK3308_AGC_MIN_GAIN_PGA_MIN,
++			     RK3308_AGC_MIN_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_min_gain_tlv),
++
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Min Volume",
+ 			     RK3308_ALC_L_DIG_CON09(2),
++			     RK3308_AGC_MIN_GAIN_PGA_SFT,
++			     RK3308_AGC_MIN_GAIN_PGA_MIN,
++			     RK3308_AGC_MIN_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_min_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Min Volume",
+ 			     RK3308_ALC_R_DIG_CON09(2),
+ 			     RK3308_AGC_MIN_GAIN_PGA_SFT,
+-			     RK3308_AGC_MIN_GAIN_PGA_NDB_18,
+-			     RK3308_AGC_MIN_GAIN_PGA_PDB_24,
+-			     0, rk3308_codec_alc_agc_ch_min_gain_tlv),
+-	SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Min Volume",
++			     RK3308_AGC_MIN_GAIN_PGA_MIN,
++			     RK3308_AGC_MIN_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_min_gain_tlv),
++
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Min Volume",
+ 			     RK3308_ALC_L_DIG_CON09(3),
++			     RK3308_AGC_MIN_GAIN_PGA_SFT,
++			     RK3308_AGC_MIN_GAIN_PGA_MIN,
++			     RK3308_AGC_MIN_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_min_gain_tlv),
++	SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Min Volume",
+ 			     RK3308_ALC_R_DIG_CON09(3),
+ 			     RK3308_AGC_MIN_GAIN_PGA_SFT,
+-			     RK3308_AGC_MIN_GAIN_PGA_NDB_18,
+-			     RK3308_AGC_MIN_GAIN_PGA_PDB_24,
+-			     0, rk3308_codec_alc_agc_ch_min_gain_tlv),
+-
+-	/* ADC MIC */
+-	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 0 Left Volume",
+-			     RK3308_ADC_ANA_CON01(0),
+-			     RK3308_ADC_CH1_MIC_GAIN_SFT,
+-			     RK3308_ADC_CH1_MIC_GAIN_0DB,
+-			     RK3308_ADC_CH1_MIC_GAIN_30DB,
+-			     0, rk3308_codec_adc_mic_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 0 Right Volume",
+-			     RK3308_ADC_ANA_CON01(0),
+-			     RK3308_ADC_CH2_MIC_GAIN_SFT,
+-			     RK3308_ADC_CH2_MIC_GAIN_0DB,
+-			     RK3308_ADC_CH2_MIC_GAIN_30DB,
+-			     0, rk3308_codec_adc_mic_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 1 Left Volume",
+-			     RK3308_ADC_ANA_CON01(1),
+-			     RK3308_ADC_CH1_MIC_GAIN_SFT,
+-			     RK3308_ADC_CH1_MIC_GAIN_0DB,
+-			     RK3308_ADC_CH1_MIC_GAIN_30DB,
+-			     0, rk3308_codec_adc_mic_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 1 Right Volume",
+-			     RK3308_ADC_ANA_CON01(1),
+-			     RK3308_ADC_CH2_MIC_GAIN_SFT,
+-			     RK3308_ADC_CH2_MIC_GAIN_0DB,
+-			     RK3308_ADC_CH2_MIC_GAIN_30DB,
+-			     0, rk3308_codec_adc_mic_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 2 Left Volume",
+-			     RK3308_ADC_ANA_CON01(2),
+-			     RK3308_ADC_CH1_MIC_GAIN_SFT,
+-			     RK3308_ADC_CH1_MIC_GAIN_0DB,
+-			     RK3308_ADC_CH1_MIC_GAIN_30DB,
+-			     0, rk3308_codec_adc_mic_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 2 Right Volume",
+-			     RK3308_ADC_ANA_CON01(2),
+-			     RK3308_ADC_CH2_MIC_GAIN_SFT,
+-			     RK3308_ADC_CH2_MIC_GAIN_0DB,
+-			     RK3308_ADC_CH2_MIC_GAIN_30DB,
+-			     0, rk3308_codec_adc_mic_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 3 Left Volume",
+-			     RK3308_ADC_ANA_CON01(3),
+-			     RK3308_ADC_CH1_MIC_GAIN_SFT,
+-			     RK3308_ADC_CH1_MIC_GAIN_0DB,
+-			     RK3308_ADC_CH1_MIC_GAIN_30DB,
+-			     0, rk3308_codec_adc_mic_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC MIC Channel 3 Right Volume",
+-			     RK3308_ADC_ANA_CON01(3),
+-			     RK3308_ADC_CH2_MIC_GAIN_SFT,
+-			     RK3308_ADC_CH2_MIC_GAIN_0DB,
+-			     RK3308_ADC_CH2_MIC_GAIN_30DB,
+-			     0, rk3308_codec_adc_mic_gain_tlv),
++			     RK3308_AGC_MIN_GAIN_PGA_MIN,
++			     RK3308_AGC_MIN_GAIN_PGA_MAX,
++			     0, rk3308_codec_alc_agc_grp_min_gain_tlv),
++
++	/* ALC AGC Switch */
++	SOC_ENUM_EXT("ALC AGC Group 0 Left Switch", rk3308_agc_enum_array[0],
++		     rk3308_codec_agc_get, rk3308_codec_agc_put),
++	SOC_ENUM_EXT("ALC AGC Group 0 Right Switch", rk3308_agc_enum_array[1],
++		     rk3308_codec_agc_get, rk3308_codec_agc_put),
++	SOC_ENUM_EXT("ALC AGC Group 1 Left Switch", rk3308_agc_enum_array[2],
++		     rk3308_codec_agc_get, rk3308_codec_agc_put),
++	SOC_ENUM_EXT("ALC AGC Group 1 Right Switch", rk3308_agc_enum_array[3],
++		     rk3308_codec_agc_get, rk3308_codec_agc_put),
++	SOC_ENUM_EXT("ALC AGC Group 2 Left Switch", rk3308_agc_enum_array[4],
++		     rk3308_codec_agc_get, rk3308_codec_agc_put),
++	SOC_ENUM_EXT("ALC AGC Group 2 Right Switch", rk3308_agc_enum_array[5],
++		     rk3308_codec_agc_get, rk3308_codec_agc_put),
++	SOC_ENUM_EXT("ALC AGC Group 3 Left Switch", rk3308_agc_enum_array[6],
++		     rk3308_codec_agc_get, rk3308_codec_agc_put),
++	SOC_ENUM_EXT("ALC AGC Group 3 Right Switch", rk3308_agc_enum_array[7],
++		     rk3308_codec_agc_get, rk3308_codec_agc_put),
++
++	/* ALC AGC Approximate Sample Rate */
++	SOC_ENUM_EXT("AGC Group 0 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[0],
++		     rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
++	SOC_ENUM_EXT("AGC Group 0 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[1],
++		     rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
++	SOC_ENUM_EXT("AGC Group 1 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[2],
++		     rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
++	SOC_ENUM_EXT("AGC Group 1 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[3],
++		     rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
++	SOC_ENUM_EXT("AGC Group 2 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[4],
++		     rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
++	SOC_ENUM_EXT("AGC Group 2 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[5],
++		     rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
++	SOC_ENUM_EXT("AGC Group 3 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[6],
++		     rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
++	SOC_ENUM_EXT("AGC Group 3 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[7],
++		     rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
++
++	/* ADC MICBIAS Voltage */
++	SOC_ENUM_EXT("ADC MICBIAS Voltage", rk3308_micbias_volts_enum_array[0],
++		     rk3308_codec_micbias_volts_get, rk3308_codec_micbias_volts_put),
++
++	/* ADC Main MICBIAS Switch */
++	SOC_ENUM_EXT("ADC Main MICBIAS", rk3308_main_micbias_enum_array[0],
++		     rk3308_codec_main_micbias_get, rk3308_codec_main_micbias_put),
++
++	/* ADC MICBIAS1 and MICBIAS2 Switch */
++	SOC_SINGLE("ADC MICBIAS1", RK3308_ADC_ANA_CON07(1),
++		   RK3308_ADC_MIC_BIAS_BUF_SFT, 1, 0),
++	SOC_SINGLE("ADC MICBIAS2", RK3308_ADC_ANA_CON07(2),
++		   RK3308_ADC_MIC_BIAS_BUF_SFT, 1, 0),
++
++	/* ADC MIC Mute/Work Switch */
++	SOC_ENUM_EXT("ADC MIC Group 0 Left Switch", rk3308_mic_mute_enum_array[0],
++		     rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
++	SOC_ENUM_EXT("ADC MIC Group 0 Right Switch", rk3308_mic_mute_enum_array[1],
++		     rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
++	SOC_ENUM_EXT("ADC MIC Group 1 Left Switch", rk3308_mic_mute_enum_array[2],
++		     rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
++	SOC_ENUM_EXT("ADC MIC Group 1 Right Switch", rk3308_mic_mute_enum_array[3],
++		     rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
++	SOC_ENUM_EXT("ADC MIC Group 2 Left Switch", rk3308_mic_mute_enum_array[4],
++		     rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
++	SOC_ENUM_EXT("ADC MIC Group 2 Right Switch", rk3308_mic_mute_enum_array[5],
++		     rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
++	SOC_ENUM_EXT("ADC MIC Group 3 Left Switch", rk3308_mic_mute_enum_array[6],
++		     rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
++	SOC_ENUM_EXT("ADC MIC Group 3 Right Switch", rk3308_mic_mute_enum_array[7],
++		     rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
+ 
+ 	/* ADC ALC */
+-	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 0 Left Volume",
++	SOC_SINGLE_RANGE_TLV("ADC ALC Group 0 Left Volume",
+ 			     RK3308_ADC_ANA_CON03(0),
+ 			     RK3308_ADC_CH1_ALC_GAIN_SFT,
+-			     RK3308_ADC_CH1_ALC_GAIN_NDB_18,
+-			     RK3308_ADC_CH1_ALC_GAIN_PDB_28_5,
++			     RK3308_ADC_CH1_ALC_GAIN_MIN,
++			     RK3308_ADC_CH1_ALC_GAIN_MAX,
+ 			     0, rk3308_codec_adc_alc_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 0 Right Volume",
++	SOC_SINGLE_RANGE_TLV("ADC ALC Group 0 Right Volume",
+ 			     RK3308_ADC_ANA_CON04(0),
+ 			     RK3308_ADC_CH2_ALC_GAIN_SFT,
+-			     RK3308_ADC_CH2_ALC_GAIN_NDB_18,
+-			     RK3308_ADC_CH2_ALC_GAIN_PDB_28_5,
++			     RK3308_ADC_CH2_ALC_GAIN_MIN,
++			     RK3308_ADC_CH2_ALC_GAIN_MAX,
+ 			     0, rk3308_codec_adc_alc_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 1 Left Volume",
++	SOC_SINGLE_RANGE_TLV("ADC ALC Group 1 Left Volume",
+ 			     RK3308_ADC_ANA_CON03(1),
+ 			     RK3308_ADC_CH1_ALC_GAIN_SFT,
+-			     RK3308_ADC_CH1_ALC_GAIN_NDB_18,
+-			     RK3308_ADC_CH1_ALC_GAIN_PDB_28_5,
++			     RK3308_ADC_CH1_ALC_GAIN_MIN,
++			     RK3308_ADC_CH1_ALC_GAIN_MAX,
+ 			     0, rk3308_codec_adc_alc_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 1 Right Volume",
++	SOC_SINGLE_RANGE_TLV("ADC ALC Group 1 Right Volume",
+ 			     RK3308_ADC_ANA_CON04(1),
+ 			     RK3308_ADC_CH2_ALC_GAIN_SFT,
+-			     RK3308_ADC_CH2_ALC_GAIN_NDB_18,
+-			     RK3308_ADC_CH2_ALC_GAIN_PDB_28_5,
++			     RK3308_ADC_CH2_ALC_GAIN_MIN,
++			     RK3308_ADC_CH2_ALC_GAIN_MAX,
+ 			     0, rk3308_codec_adc_alc_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 2 Left Volume",
++	SOC_SINGLE_RANGE_TLV("ADC ALC Group 2 Left Volume",
+ 			     RK3308_ADC_ANA_CON03(2),
+ 			     RK3308_ADC_CH1_ALC_GAIN_SFT,
+-			     RK3308_ADC_CH1_ALC_GAIN_NDB_18,
+-			     RK3308_ADC_CH1_ALC_GAIN_PDB_28_5,
++			     RK3308_ADC_CH1_ALC_GAIN_MIN,
++			     RK3308_ADC_CH1_ALC_GAIN_MAX,
+ 			     0, rk3308_codec_adc_alc_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 2 Right Volume",
++	SOC_SINGLE_RANGE_TLV("ADC ALC Group 2 Right Volume",
+ 			     RK3308_ADC_ANA_CON04(2),
+ 			     RK3308_ADC_CH2_ALC_GAIN_SFT,
+-			     RK3308_ADC_CH2_ALC_GAIN_NDB_18,
+-			     RK3308_ADC_CH2_ALC_GAIN_PDB_28_5,
++			     RK3308_ADC_CH2_ALC_GAIN_MIN,
++			     RK3308_ADC_CH2_ALC_GAIN_MAX,
+ 			     0, rk3308_codec_adc_alc_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 3 Left Volume",
++	SOC_SINGLE_RANGE_TLV("ADC ALC Group 3 Left Volume",
+ 			     RK3308_ADC_ANA_CON03(3),
+ 			     RK3308_ADC_CH1_ALC_GAIN_SFT,
+-			     RK3308_ADC_CH1_ALC_GAIN_NDB_18,
+-			     RK3308_ADC_CH1_ALC_GAIN_PDB_28_5,
++			     RK3308_ADC_CH1_ALC_GAIN_MIN,
++			     RK3308_ADC_CH1_ALC_GAIN_MAX,
+ 			     0, rk3308_codec_adc_alc_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("ADC ALC Channel 3 Right Volume",
++	SOC_SINGLE_RANGE_TLV("ADC ALC Group 3 Right Volume",
+ 			     RK3308_ADC_ANA_CON04(3),
+ 			     RK3308_ADC_CH2_ALC_GAIN_SFT,
+-			     RK3308_ADC_CH2_ALC_GAIN_NDB_18,
+-			     RK3308_ADC_CH2_ALC_GAIN_PDB_28_5,
++			     RK3308_ADC_CH2_ALC_GAIN_MIN,
++			     RK3308_ADC_CH2_ALC_GAIN_MAX,
+ 			     0, rk3308_codec_adc_alc_gain_tlv),
+ 
+-	/* DAC */
+-	SOC_SINGLE_RANGE_TLV("DAC Left Volume",
+-			     RK3308_DAC_ANA_CON04,
+-			     RK3308_DAC_L_GAIN_SFT,
+-			     RK3308_DAC_L_GAIN_0DB,
+-			     RK3308_DAC_L_GAIN_PDB_6,
+-			     0, rk3308_codec_dac_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("DAC Right Volume",
+-			     RK3308_DAC_ANA_CON04,
+-			     RK3308_DAC_R_GAIN_SFT,
+-			     RK3308_DAC_R_GAIN_0DB,
+-			     RK3308_DAC_R_GAIN_PDB_6,
+-			     0, rk3308_codec_dac_gain_tlv),
++	/* ADC High Pass Filter */
++	SOC_ENUM_EXT("ADC Group 0 HPF Cut-off", rk3308_hpf_enum_array[0],
++		     rk3308_codec_hpf_get, rk3308_codec_hpf_put),
++	SOC_ENUM_EXT("ADC Group 1 HPF Cut-off", rk3308_hpf_enum_array[1],
++		     rk3308_codec_hpf_get, rk3308_codec_hpf_put),
++	SOC_ENUM_EXT("ADC Group 2 HPF Cut-off", rk3308_hpf_enum_array[2],
++		     rk3308_codec_hpf_get, rk3308_codec_hpf_put),
++	SOC_ENUM_EXT("ADC Group 3 HPF Cut-off", rk3308_hpf_enum_array[3],
++		     rk3308_codec_hpf_get, rk3308_codec_hpf_put),
++
++	/* DAC LINEOUT */
++	SOC_SINGLE_TLV("DAC LINEOUT Left Volume",
++		       RK3308_DAC_ANA_CON04,
++		       RK3308_DAC_L_LINEOUT_GAIN_SFT,
++		       RK3308_DAC_L_LINEOUT_GAIN_MAX,
++		       0, rk3308_codec_dac_lineout_gain_tlv),
++	SOC_SINGLE_TLV("DAC LINEOUT Right Volume",
++		       RK3308_DAC_ANA_CON04,
++		       RK3308_DAC_R_LINEOUT_GAIN_SFT,
++		       RK3308_DAC_R_LINEOUT_GAIN_MAX,
++		       0, rk3308_codec_dac_lineout_gain_tlv),
+ 
+ 	/* DAC HPOUT */
+-	SOC_SINGLE_RANGE_TLV("DAC HPOUT Left Volume",
+-			     RK3308_DAC_ANA_CON05,
+-			     RK3308_DAC_L_HPOUT_GAIN_SFT,
+-			     RK3308_DAC_L_HPOUT_GAIN_NDB_39,
+-			     RK3308_DAC_L_HPOUT_GAIN_PDB_6,
+-			     0, rk3308_codec_dac_hpout_gain_tlv),
+-	SOC_SINGLE_RANGE_TLV("DAC HPOUT Right Volume",
+-			     RK3308_DAC_ANA_CON06,
+-			     RK3308_DAC_R_HPOUT_GAIN_SFT,
+-			     RK3308_DAC_R_HPOUT_GAIN_NDB_39,
+-			     RK3308_DAC_R_HPOUT_GAIN_PDB_6,
+-			     0, rk3308_codec_dac_hpout_gain_tlv),
++	SOC_SINGLE_EXT_TLV("DAC HPOUT Left Volume",
++			   RK3308_DAC_ANA_CON05,
++			   RK3308_DAC_L_HPOUT_GAIN_SFT,
++			   RK3308_DAC_L_HPOUT_GAIN_MAX,
++			   0,
++			   rk3308_codec_hpout_l_get_tlv,
++			   rk3308_codec_hpout_l_put_tlv,
++			   rk3308_codec_dac_hpout_gain_tlv),
++	SOC_SINGLE_EXT_TLV("DAC HPOUT Right Volume",
++			   RK3308_DAC_ANA_CON06,
++			   RK3308_DAC_R_HPOUT_GAIN_SFT,
++			   RK3308_DAC_R_HPOUT_GAIN_MAX,
++			   0,
++			   rk3308_codec_hpout_r_get_tlv,
++			   rk3308_codec_hpout_r_put_tlv,
++			   rk3308_codec_dac_hpout_gain_tlv),
+ 
+ 	/* DAC HPMIX */
+ 	SOC_SINGLE_RANGE_TLV("DAC HPMIX Left Volume",
+-			     RK3308_DAC_ANA_CON05,
++			     RK3308_DAC_ANA_CON12,
+ 			     RK3308_DAC_L_HPMIX_GAIN_SFT,
+-			     RK3308_DAC_L_HPMIX_GAIN_NDB_6,
+-			     RK3308_DAC_L_HPMIX_GAIN_0DB,
++			     RK3308_DAC_L_HPMIX_GAIN_MIN,
++			     RK3308_DAC_L_HPMIX_GAIN_MAX,
+ 			     0, rk3308_codec_dac_hpmix_gain_tlv),
+ 	SOC_SINGLE_RANGE_TLV("DAC HPMIX Right Volume",
+-			     RK3308_DAC_ANA_CON05,
++			     RK3308_DAC_ANA_CON12,
+ 			     RK3308_DAC_R_HPMIX_GAIN_SFT,
+-			     RK3308_DAC_R_HPMIX_GAIN_NDB_6,
+-			     RK3308_DAC_R_HPMIX_GAIN_0DB,
++			     RK3308_DAC_R_HPMIX_GAIN_MIN,
++			     RK3308_DAC_R_HPMIX_GAIN_MAX,
+ 			     0, rk3308_codec_dac_hpmix_gain_tlv),
+ };
+ 
+-static void rk3308_speaker_ctl(struct rk3308_codec_priv *rk3308, int on)
++static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol,
++				struct snd_ctl_elem_value *ucontrol)
+ {
+-	gpiod_direction_output(rk3308->spk_ctl_gpio, on);
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
++
++	if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
++		dev_err(rk3308->plat_dev,
++			"%s: Invalid ADC grp: %d\n", __func__, e->reg);
++		return -EINVAL;
++	}
++
++	if (e->shift_l)
++		ucontrol->value.integer.value[0] = rk3308->agc_r[e->reg];
++	else
++		ucontrol->value.integer.value[0] = rk3308->agc_l[e->reg];
++
++	return 0;
+ }
+ 
+-static int rk3308_codec_reset(struct snd_soc_codec *codec)
++static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol,
++				struct snd_ctl_elem_value *ucontrol)
+ {
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ 	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
++	unsigned int value = ucontrol->value.integer.value[0];
++	int grp = e->reg;
+ 
+-	reset_control_assert(rk3308->reset);
+-	usleep_range(200, 300);		/* estimated value */
+-	reset_control_deassert(rk3308->reset);
++	if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
++		dev_err(rk3308->plat_dev,
++			"%s: Invalid ADC grp: %d\n", __func__, e->reg);
++		return -EINVAL;
++	}
+ 
+-	regmap_write(rk3308->regmap, RK3308_GLB_CON, 0x00);
+-	usleep_range(200, 300);		/* estimated value */
+-	regmap_write(rk3308->regmap, RK3308_GLB_CON,
+-		     RK3308_SYS_WORK |
+-		     RK3308_DAC_DIG_WORK |
+-		     RK3308_ADC_DIG_WORK);
++	if (value) {
++		/* ALC AGC On */
++		if (e->shift_l) {
++			/* ALC AGC Right On */
++			regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp),
++					   RK3308_AGC_FUNC_SEL_MSK,
++					   RK3308_AGC_FUNC_SEL_EN);
++			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp),
++					   RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK,
++					   RK3308_ADC_ALCR_CON_GAIN_PGAR_EN);
++
++			rk3308->agc_r[e->reg] = 1;
++		} else {
++			/* ALC AGC Left On */
++			regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp),
++					   RK3308_AGC_FUNC_SEL_MSK,
++					   RK3308_AGC_FUNC_SEL_EN);
++			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp),
++					   RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK,
++					   RK3308_ADC_ALCL_CON_GAIN_PGAL_EN);
++
++			rk3308->agc_l[e->reg] = 1;
++		}
++	} else {
++		/* ALC AGC Off */
++		if (e->shift_l) {
++			/* ALC AGC Right Off */
++			regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp),
++					   RK3308_AGC_FUNC_SEL_MSK,
++					   RK3308_AGC_FUNC_SEL_DIS);
++			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp),
++					   RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK,
++					   RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS);
++
++			rk3308->agc_r[e->reg] = 0;
++		} else {
++			/* ALC AGC Left Off */
++			regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp),
++					   RK3308_AGC_FUNC_SEL_MSK,
++					   RK3308_AGC_FUNC_SEL_DIS);
++			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp),
++					   RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK,
++					   RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS);
++
++			rk3308->agc_l[e->reg] = 0;
++		}
++	}
+ 
+ 	return 0;
+ }
+ 
+-static int rk3308_set_bias_level(struct snd_soc_codec *codec,
+-				 enum snd_soc_bias_level level)
++static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol,
++				    struct snd_ctl_elem_value *ucontrol)
+ {
+-	switch (level) {
+-	case SND_SOC_BIAS_ON:
+-		break;
+-
+-	case SND_SOC_BIAS_PREPARE:
+-		break;
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
++	unsigned int value;
++	int grp = e->reg;
+ 
+-	case SND_SOC_BIAS_STANDBY:
+-	case SND_SOC_BIAS_OFF:
+-		break;
++	if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
++		dev_err(rk3308->plat_dev,
++			"%s: Invalid ADC grp: %d\n", __func__, e->reg);
++		return -EINVAL;
+ 	}
+ 
+-	snd_soc_codec_force_bias_level(codec, level);
++	if (e->shift_l) {
++		regmap_read(rk3308->regmap, RK3308_ALC_R_DIG_CON04(grp), &value);
++		rk3308->agc_asr_r[e->reg] = value >> RK3308_AGC_APPROX_RATE_SFT;
++		ucontrol->value.integer.value[0] = rk3308->agc_asr_r[e->reg];
++	} else {
++		regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON04(grp), &value);
++		rk3308->agc_asr_l[e->reg] = value >> RK3308_AGC_APPROX_RATE_SFT;
++		ucontrol->value.integer.value[0] = rk3308->agc_asr_l[e->reg];
++	}
+ 
+ 	return 0;
+ }
+ 
+-static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai,
+-			      unsigned int fmt)
++static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol,
++				    struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = codec_dai->codec;
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ 	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
+-	unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0;
+-	int ch = rk3308->adc_ch;
++	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
++	unsigned int value;
++	int grp = e->reg;
+ 
+-	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+-	case SND_SOC_DAIFMT_CBS_CFS:
+-		adc_aif2 |= RK3308_ADC_IO_MODE_SLAVE;
+-		adc_aif2 |= RK3308_ADC_MODE_SLAVE;
+-		dac_aif2 |= RK3308_DAC_IO_MODE_SLAVE;
+-		dac_aif2 |= RK3308_DAC_MODE_SLAVE;
+-		break;
+-	case SND_SOC_DAIFMT_CBM_CFM:
+-		adc_aif2 |= RK3308_ADC_IO_MODE_MASTER;
+-		adc_aif2 |= RK3308_ADC_MODE_MASTER;
+-		dac_aif2 |= RK3308_DAC_IO_MODE_MASTER;
+-		dac_aif2 |= RK3308_DAC_MODE_MASTER;
+-		break;
+-	default:
++	if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
++		dev_err(rk3308->plat_dev,
++			"%s: Invalid ADC grp: %d\n", __func__, e->reg);
+ 		return -EINVAL;
+ 	}
+ 
+-	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+-	case SND_SOC_DAIFMT_DSP_A:
+-		adc_aif1 |= RK3308_ADC_I2S_MODE_PCM;
+-		dac_aif1 |= RK3308_DAC_I2S_MODE_PCM;
+-		break;
+-	case SND_SOC_DAIFMT_I2S:
+-		adc_aif1 |= RK3308_ADC_I2S_MODE_I2S;
+-		dac_aif1 |= RK3308_DAC_I2S_MODE_I2S;
+-		break;
+-	case SND_SOC_DAIFMT_RIGHT_J:
+-		adc_aif1 |= RK3308_ADC_I2S_MODE_RJ;
+-		dac_aif1 |= RK3308_DAC_I2S_MODE_RJ;
+-		break;
+-	case SND_SOC_DAIFMT_LEFT_J:
+-		adc_aif1 |= RK3308_ADC_I2S_MODE_RJ;
+-		dac_aif1 |= RK3308_DAC_I2S_MODE_LJ;
+-		break;
+-	default:
+-		return -EINVAL;
++	value = ucontrol->value.integer.value[0] << RK3308_AGC_APPROX_RATE_SFT;
++
++	if (e->shift_l) {
++		/* ALC AGC Right Approximate Sample Rate */
++		regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON04(grp),
++				   RK3308_AGC_APPROX_RATE_MSK,
++				   value);
++		rk3308->agc_asr_r[e->reg] = ucontrol->value.integer.value[0];
++	} else {
++		/* ALC AGC Left Approximate Sample Rate */
++		regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON04(grp),
++				   RK3308_AGC_APPROX_RATE_MSK,
++				   value);
++		rk3308->agc_asr_l[e->reg] = ucontrol->value.integer.value[0];
+ 	}
+ 
+-	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+-	case SND_SOC_DAIFMT_NB_NF:
+-		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL;
+-		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL;
+-		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL;
+-		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL;
+-		break;
+-	case SND_SOC_DAIFMT_IB_IF:
+-		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL;
+-		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL;
+-		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL;
+-		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL;
+-		break;
+-	case SND_SOC_DAIFMT_IB_NF:
+-		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL;
+-		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL;
+-		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL;
+-		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL;
+-		break;
+-	case SND_SOC_DAIFMT_NB_IF:
+-		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL;
+-		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL;
+-		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL;
+-		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL;
+-		break;
+-	default:
++	return 0;
++}
++
++static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol,
++				     struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
++	unsigned int value;
++	int grp = e->reg;
++
++	if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
++		dev_err(rk3308->plat_dev,
++			"%s: Invalid ADC grp: %d\n", __func__, e->reg);
+ 		return -EINVAL;
+ 	}
+ 
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(ch),
+-			   RK3308_ADC_I2S_LRC_POL_MSK |
+-			   RK3308_ADC_I2S_MODE_MSK,
+-			   adc_aif1);
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(ch),
+-			   RK3308_ADC_IO_MODE_MSK |
+-			   RK3308_ADC_MODE_MSK |
+-			   RK3308_ADC_I2S_BIT_CLK_POL_MSK,
+-			   adc_aif2);
+-
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01,
+-			   RK3308_DAC_I2S_LRC_POL_MSK |
+-			   RK3308_DAC_I2S_MODE_MSK,
+-			   dac_aif1);
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02,
+-			   RK3308_DAC_IO_MODE_MSK |
+-			   RK3308_DAC_MODE_MSK |
+-			   RK3308_DAC_I2S_BIT_CLK_POL_MSK,
+-			   dac_aif2);
++	if (e->shift_l) {
++		/* ADC MIC Right Mute/Work Infos */
++		regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), &value);
++		rk3308->mic_mute_r[e->reg] = (value & RK3308_ADC_R_CH_BIST_SINE) >>
++					     RK3308_ADC_R_CH_BIST_SFT;
++		ucontrol->value.integer.value[0] = rk3308->mic_mute_r[e->reg];
++	} else {
++		/* ADC MIC Left Mute/Work Infos */
++		regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), &value);
++		rk3308->mic_mute_l[e->reg] = (value & RK3308_ADC_L_CH_BIST_SINE) >>
++					     RK3308_ADC_L_CH_BIST_SFT;
++		ucontrol->value.integer.value[0] = rk3308->mic_mute_l[e->reg];
++	}
+ 
+ 	return 0;
+ }
+ 
+-static int rk3308_hw_params(struct snd_pcm_substream *substream,
+-			    struct snd_pcm_hw_params *params,
+-			    struct snd_soc_dai *dai)
++static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol,
++				     struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = dai->codec;
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ 	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
+-	unsigned int adc_aif1 = 0, adc_aif2  = 0, dac_aif1 = 0, dac_aif2  = 0;
+-	int ch = rk3308->adc_ch;
++	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
++	unsigned int value;
++	int grp = e->reg;
+ 
+-	switch (params_format(params)) {
+-	case SNDRV_PCM_FORMAT_S16_LE:
+-		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_16BITS;
+-		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_16BITS;
+-		break;
+-	case SNDRV_PCM_FORMAT_S20_3LE:
+-		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_20BITS;
+-		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_20BITS;
+-		break;
+-	case SNDRV_PCM_FORMAT_S24_LE:
+-		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_24BITS;
+-		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_24BITS;
+-		break;
+-	case SNDRV_PCM_FORMAT_S32_LE:
+-		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_32BITS;
+-		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_32BITS;
+-		break;
+-	default:
++	if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
++		dev_err(rk3308->plat_dev,
++			"%s: Invalid ADC grp: %d\n", __func__, e->reg);
+ 		return -EINVAL;
+ 	}
+ 
+-	switch (params_channels(params)) {
+-	case 1:
+-		adc_aif1 |= RK3308_ADC_I2S_MONO;
+-		break;
+-	case 2:
+-		adc_aif1 |= RK3308_ADC_I2S_STEREO;
+-		break;
+-	default:
+-		return -EINVAL;
++	if (e->shift_l) {
++		/* ADC MIC Right Mute/Work Configuration */
++		value = ucontrol->value.integer.value[0] << RK3308_ADC_R_CH_BIST_SFT;
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(grp),
++				   RK3308_ADC_R_CH_BIST_SINE,
++				   value);
++		rk3308->mic_mute_r[e->reg] = ucontrol->value.integer.value[0];
++	} else {
++		/* ADC MIC Left Mute/Work Configuration */
++		value = ucontrol->value.integer.value[0] << RK3308_ADC_L_CH_BIST_SFT;
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(grp),
++				   RK3308_ADC_L_CH_BIST_SINE,
++				   value);
++		rk3308->mic_mute_l[e->reg] = ucontrol->value.integer.value[0];
+ 	}
+ 
+-	adc_aif1 |= RK3308_ADC_I2S_LR_NORMAL;
+-	adc_aif2 |= RK3308_ADC_I2S_WORK;
+-	dac_aif1 |= RK3308_DAC_I2S_LR_NORMAL;
+-	dac_aif2 |= RK3308_DAC_I2S_WORK;
++	return 0;
++}
+ 
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(ch),
+-			   RK3308_ADC_I2S_VALID_LEN_MSK |
+-			   RK3308_ADC_I2S_LR_MSK |
+-			   RK3308_ADC_I2S_TYPE_MSK,
+-			   adc_aif1);
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(ch),
+-			   RK3308_ADC_I2S_MSK,
+-			   adc_aif2);
++static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol,
++					  struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
+ 
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01,
+-			   RK3308_DAC_I2S_VALID_LEN_MSK |
+-			   RK3308_DAC_I2S_LR_MSK,
+-			   dac_aif1);
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02,
+-			   RK3308_DAC_I2S_MSK,
+-			   dac_aif2);
++	ucontrol->value.integer.value[0] = rk3308->micbias_volt;
+ 
+ 	return 0;
+ }
+ 
+-static int rk3308_digital_mute(struct snd_soc_dai *dai, int mute)
++static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol,
++					  struct snd_ctl_elem_value *ucontrol)
+ {
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	unsigned int volt = ucontrol->value.integer.value[0];
++	int ret;
++
++	ret = check_micbias(volt);
++	if (ret < 0) {
++		dev_err(rk3308->plat_dev, "The invalid micbias volt: %d\n",
++			volt);
++		return ret;
++	}
++
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0),
++			   RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK,
++			   volt);
++
++	rk3308->micbias_volt = volt;
++
+ 	return 0;
+ }
+ 
+-static int rk3308_codec_dac_enable(struct rk3308_codec_priv *rk3308)
++static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol,
++					 struct snd_ctl_elem_value *ucontrol)
+ {
+-	/* Step 01 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
+-			   RK3308_DAC_CURRENT_MSK,
+-			   RK3308_DAC_CURRENT_EN);
+-
+-	/* Step 02 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
+-			   RK3308_DAC_BUF_REF_L_MSK |
+-			   RK3308_DAC_BUF_REF_R_MSK,
+-			   RK3308_DAC_BUF_REF_L_EN |
+-			   RK3308_DAC_BUF_REF_R_EN);
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
+ 
+-	/* Step 03 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
+-			   RK3308_DAC_POP_SOUND_L_MSK |
+-			   RK3308_DAC_POP_SOUND_R_MSK,
+-			   RK3308_DAC_POP_SOUND_L_WORK |
+-			   RK3308_DAC_POP_SOUND_R_WORK);
++	ucontrol->value.integer.value[0] = rk3308->enable_micbias;
+ 
+-	/* Step 04 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
+-			   RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN,
+-			   RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN);
++	return 0;
++}
+ 
+-	/* Step 05 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
+-			   RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK,
+-			   RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK);
++static int rk3308_codec_main_micbias_put(struct snd_kcontrol *kcontrol,
++					 struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	unsigned int on = ucontrol->value.integer.value[0];
++
++	if (on) {
++		if (!rk3308->enable_micbias)
++			rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt);
++	} else {
++		if (rk3308->enable_micbias)
++			rk3308_codec_micbias_disable(rk3308);
++	}
+ 
+-	/* Step 06 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
+-			   RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN,
+-			   RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN);
++	return 0;
++}
+ 
+-	/* Step 07 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
+-			   RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN,
+-			   RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN);
++static int rk3308_codec_mic_gain_get(struct snd_kcontrol *kcontrol,
++				     struct snd_ctl_elem_value *ucontrol)
++{
++	return snd_soc_get_volsw_range(kcontrol, ucontrol);
++}
+ 
+-	/* Step 08 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
+-			   RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK,
+-			   RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK);
++static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol,
++				     struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	unsigned int gain = ucontrol->value.integer.value[0];
+ 
+-	/* Step 09 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
+-			   RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN,
+-			   RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN);
++	if (gain > RK3308_ADC_CH1_MIC_GAIN_MAX) {
++		dev_err(rk3308->plat_dev, "%s: invalid mic gain: %d\n",
++			__func__, gain);
++		return -EINVAL;
++	}
+ 
+-	/* Step 10 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
+-			   RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN,
+-			   RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN);
++	if (rk3308->codec_ver == ACODEC_VERSION_A) {
++		/*
++		 * From the TRM, there are only suupport 0dB(gain==0) and
++		 * 20dB(gain==3) on the codec version A.
++		 */
++		if (!(gain == 0 || gain == RK3308_ADC_CH1_MIC_GAIN_MAX)) {
++			dev_err(rk3308->plat_dev,
++				"version A doesn't supported: %d, expect: 0,%d\n",
++				gain, RK3308_ADC_CH1_MIC_GAIN_MAX);
++			return 0;
++		}
++	}
+ 
+-	/* Step 11 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
+-			   RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN,
+-			   RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN);
++	return snd_soc_put_volsw_range(kcontrol, ucontrol);
++}
+ 
+-	/* Step 12 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
+-			   RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK,
+-			   RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK);
++static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol,
++				struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
++	unsigned int value;
+ 
+-	/* Step 13 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
+-			   RK3308_DAC_L_HPMIX_SEL_MSK |
+-			   RK3308_DAC_R_HPMIX_SEL_MSK,
+-			   RK3308_DAC_L_HPMIX_I2S |
+-			   RK3308_DAC_R_HPMIX_I2S);
++	if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
++		dev_err(rk3308->plat_dev,
++			"%s: Invalid ADC grp: %d\n", __func__, e->reg);
++		return -EINVAL;
++	}
+ 
+-	/* Step 14 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
+-			   RK3308_DAC_L_HPMIX_UNMUTE |
+-			   RK3308_DAC_R_HPMIX_UNMUTE,
+-			   RK3308_DAC_L_HPMIX_UNMUTE |
+-			   RK3308_DAC_R_HPMIX_UNMUTE);
++	regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg), &value);
++	if (value & RK3308_ADC_HPF_PATH_MSK)
++		rk3308->hpf_cutoff[e->reg] = 0;
++	else
++		rk3308->hpf_cutoff[e->reg] = 1;
+ 
+-	/* Step 15 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
+-			   RK3308_DAC_L_HPMIX_GAIN_MSK |
+-			   RK3308_DAC_R_HPMIX_GAIN_MSK,
+-			   RK3308_DAC_L_HPMIX_GAIN_0DB |
+-			   RK3308_DAC_R_HPMIX_GAIN_0DB);
++	ucontrol->value.integer.value[0] = rk3308->hpf_cutoff[e->reg];
+ 
+-	/* Step 16 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
+-			   RK3308_DAC_L_HPOUT_UNMUTE |
+-			   RK3308_DAC_R_HPOUT_UNMUTE,
+-			   RK3308_DAC_L_HPOUT_UNMUTE |
+-			   RK3308_DAC_R_HPOUT_UNMUTE);
++	return 0;
++}
+ 
+-	/* Step 17 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
+-			   RK3308_DAC_L_LINEOUT_UNMUTE |
+-			   RK3308_DAC_R_LINEOUT_UNMUTE,
+-			   RK3308_DAC_L_LINEOUT_UNMUTE |
+-			   RK3308_DAC_R_LINEOUT_UNMUTE);
++static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol,
++				struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
++	unsigned int value = ucontrol->value.integer.value[0];
+ 
+-	/* Step 18 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05,
+-			   RK3308_DAC_L_HPOUT_GAIN_MSK,
+-			   RK3308_DAC_L_HPOUT_GAIN_0DB);
++	if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
++		dev_err(rk3308->plat_dev,
++			"%s: Invalid ADC grp: %d\n", __func__, e->reg);
++		return -EINVAL;
++	}
+ 
+-	/* Step 18 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06,
+-			   RK3308_DAC_R_HPOUT_GAIN_MSK,
+-			   RK3308_DAC_R_HPOUT_GAIN_0DB);
++	if (value) {
++		/* Enable high pass filter for ADCs */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg),
++				   RK3308_ADC_HPF_PATH_MSK,
++				   RK3308_ADC_HPF_PATH_EN);
++	} else {
++		/* Disable high pass filter for ADCs. */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg),
++				   RK3308_ADC_HPF_PATH_MSK,
++				   RK3308_ADC_HPF_PATH_DIS);
++	}
+ 
+-	/* Step 19 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
+-			   RK3308_DAC_L_GAIN_MSK | RK3308_DAC_R_GAIN_MSK,
+-			   RK3308_DAC_L_GAIN_0DB | RK3308_DAC_R_GAIN_0DB);
++	rk3308->hpf_cutoff[e->reg] = value;
+ 
+ 	return 0;
+ }
+ 
+-static int rk3308_codec_dac_disable(struct rk3308_codec_priv *rk3308)
++static int rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol *kcontrol,
++					struct snd_ctl_elem_value *ucontrol)
+ {
+-	/* Step 01 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
+-			   RK3308_DAC_L_GAIN_MSK | RK3308_DAC_R_GAIN_MSK,
+-			   RK3308_DAC_L_GAIN_0DB | RK3308_DAC_R_GAIN_0DB);
+-
+-	/*
+-	 * Step 02
+-	 *
+-	 * Note1. In the step2, adjusting the register step by step to the
+-	 * appropriate value and taking 20ms as time step
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05,
+-			   RK3308_DAC_L_HPOUT_GAIN_MSK,
+-			   RK3308_DAC_L_HPOUT_GAIN_NDB_39);
+-
+-	/* Step 02 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06,
+-			   RK3308_DAC_R_HPOUT_GAIN_MSK,
+-			   RK3308_DAC_R_HPOUT_GAIN_NDB_39);
++	return snd_soc_get_volsw_range(kcontrol, ucontrol);
++}
+ 
+-	/* Step 03 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
+-			   RK3308_DAC_L_HPMIX_UNMUTE |
+-			   RK3308_DAC_R_HPMIX_UNMUTE,
+-			   RK3308_DAC_L_HPMIX_MUTE |
+-			   RK3308_DAC_R_HPMIX_MUTE);
++static int rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol *kcontrol,
++					struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	unsigned int dgain = ucontrol->value.integer.value[0];
+ 
+-	/* Step 04 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
+-			   RK3308_DAC_L_HPMIX_SEL_MSK |
+-			   RK3308_DAC_R_HPMIX_SEL_MSK,
+-			   RK3308_DAC_L_HPMIX_NONE |
+-			   RK3308_DAC_R_HPMIX_NONE);
++	if (dgain > RK3308_DAC_L_HPOUT_GAIN_MAX) {
++		dev_err(rk3308->plat_dev, "%s: invalid l_dgain: %d\n",
++			__func__, dgain);
++		return -EINVAL;
++	}
+ 
+-	/* Step 05 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
+-			   RK3308_DAC_L_HPOUT_UNMUTE |
+-			   RK3308_DAC_R_HPOUT_UNMUTE,
+-			   RK3308_DAC_L_HPOUT_MUTE |
+-			   RK3308_DAC_R_HPOUT_MUTE);
++	rk3308->hpout_l_dgain = dgain;
+ 
+-	/* Step 06 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
+-			   RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK,
+-			   RK3308_DAC_L_DAC_INIT | RK3308_DAC_R_DAC_INIT);
++	return snd_soc_put_volsw_range(kcontrol, ucontrol);
++}
+ 
+-	/* Step 07 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
+-			   RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN,
+-			   RK3308_DAC_L_HPOUT_DIS | RK3308_DAC_R_HPOUT_DIS);
++static int rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol *kcontrol,
++					struct snd_ctl_elem_value *ucontrol)
++{
++	return snd_soc_get_volsw_range(kcontrol, ucontrol);
++}
+ 
+-	/* Step 08 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
+-			   RK3308_DAC_L_LINEOUT_UNMUTE |
+-			   RK3308_DAC_R_LINEOUT_UNMUTE,
+-			   RK3308_DAC_L_LINEOUT_MUTE |
+-			   RK3308_DAC_R_LINEOUT_MUTE);
++static int rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol *kcontrol,
++					struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	unsigned int dgain = ucontrol->value.integer.value[0];
+ 
+-	/* Step 09 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
+-			   RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN,
+-			   RK3308_DAC_L_LINEOUT_DIS | RK3308_DAC_R_LINEOUT_DIS);
++	if (dgain > RK3308_DAC_R_HPOUT_GAIN_MAX) {
++		dev_err(rk3308->plat_dev, "%s: invalid r_dgain: %d\n",
++			__func__, dgain);
++		return -EINVAL;
++	}
+ 
+-	/* Step 10 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
+-			   RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN,
+-			   RK3308_DAC_L_HPMIX_DIS | RK3308_DAC_R_HPMIX_DIS);
++	rk3308->hpout_r_dgain = dgain;
+ 
+-	/* Step 11 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
+-			   RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN,
+-			   RK3308_DAC_L_DAC_DIS | RK3308_DAC_R_DAC_DIS);
++	return snd_soc_put_volsw_range(kcontrol, ucontrol);
++}
+ 
+-	/* Step 12 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
+-			   RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN,
+-			   RK3308_DAC_L_CLK_DIS | RK3308_DAC_R_CLK_DIS);
++static u32 to_mapped_grp(struct rk3308_codec_priv *rk3308, int idx)
++{
++	return rk3308->i2s_sdis[idx];
++}
+ 
+-	/* Step 13 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
+-			   RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN,
+-			   RK3308_DAC_L_REF_DIS | RK3308_DAC_R_REF_DIS);
++static bool adc_for_each_grp(struct rk3308_codec_priv *rk3308,
++			     int type, int idx, u32 *grp)
++{
++	if (type == ADC_TYPE_NORMAL) {
++		u32 mapped_grp = to_mapped_grp(rk3308, idx);
++		int max_grps;
++
++		if (rk3308->enable_all_adcs)
++			max_grps = ADC_LR_GROUP_MAX;
++		else
++			max_grps = rk3308->used_adc_grps;
++
++		if (idx >= max_grps)
++			return false;
++
++		if ((!rk3308->loopback_dacs_enabled) &&
++		    handle_loopback(rk3308) &&
++		    rk3308->loopback_grp == mapped_grp) {
++			/*
++			 * Ths loopback DACs are closed, and specify the
++			 * loopback ADCs.
++			 */
++			*grp = ADC_GRP_SKIP_MAGIC;
++		} else if (rk3308->en_always_grps_num &&
++			   rk3308->skip_grps[mapped_grp]) {
++			/* To set the skip flag if the ADC GRP is enabled. */
++			*grp = ADC_GRP_SKIP_MAGIC;
++		} else {
++			*grp = mapped_grp;
++		}
+ 
+-	/* Step 14 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
+-			   RK3308_DAC_POP_SOUND_L_MSK |
+-			   RK3308_DAC_POP_SOUND_R_MSK,
+-			   RK3308_DAC_POP_SOUND_L_INIT |
+-			   RK3308_DAC_POP_SOUND_R_INIT);
++		dev_dbg(rk3308->plat_dev,
++			"ADC_TYPE_NORMAL, idx: %d, mapped_grp: %d, get grp: %d,\n",
++			idx, mapped_grp, *grp);
++	} else if (type == ADC_TYPE_ALL) {
++		if (idx >= ADC_LR_GROUP_MAX)
++			return false;
++
++		*grp = idx;
++		dev_dbg(rk3308->plat_dev,
++			"ADC_TYPE_ALL, idx: %d, get grp: %d\n",
++			idx, *grp);
++	} else if (type == ADC_TYPE_DBG) {
++		if (idx >= ADC_LR_GROUP_MAX)
++			return false;
++
++		if (idx == (int)rk3308->cur_dbg_grp)
++			*grp = idx;
++		else
++			*grp = ADC_GRP_SKIP_MAGIC;
++
++		dev_dbg(rk3308->plat_dev,
++			"ADC_TYPE_DBG, idx: %d, get grp: %d\n",
++			idx, *grp);
++	} else {
++		if (idx >= 1)
++			return false;
++
++		*grp = rk3308->loopback_grp;
++		dev_dbg(rk3308->plat_dev,
++			"ADC_TYPE_LOOPBACK, idx: %d, get grp: %d\n",
++			idx, *grp);
++	}
+ 
+-	/* Step 15 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
+-			   RK3308_DAC_BUF_REF_L_EN | RK3308_DAC_BUF_REF_R_EN,
+-			   RK3308_DAC_BUF_REF_L_DIS | RK3308_DAC_BUF_REF_R_DIS);
++	return true;
++}
+ 
+-	/* Step 16 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
+-			   RK3308_DAC_CURRENT_EN,
+-			   RK3308_DAC_CURRENT_DIS);
++static int rk3308_codec_get_dac_path_state(struct rk3308_codec_priv *rk3308)
++{
++	return rk3308->dac_path_state;
++}
+ 
+-	/* Step 17 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
+-			   RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK,
+-			   RK3308_DAC_L_HPOUT_INIT | RK3308_DAC_R_HPOUT_INIT);
++static void rk3308_codec_set_dac_path_state(struct rk3308_codec_priv *rk3308,
++					    int state)
++{
++	rk3308->dac_path_state = state;
++}
+ 
+-	/* Step 18 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
+-			   RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK,
+-			   RK3308_DAC_L_HPMIX_INIT | RK3308_DAC_R_HPMIX_INIT);
++static void rk3308_headphone_ctl(struct rk3308_codec_priv *rk3308, int on)
++{
++	if (rk3308->hp_ctl_gpio)
++		gpiod_direction_output(rk3308->hp_ctl_gpio, on);
++}
+ 
+-	/* Step 19 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
+-			   RK3308_DAC_L_HPMIX_GAIN_MSK |
+-			   RK3308_DAC_R_HPMIX_GAIN_MSK,
+-			   RK3308_DAC_L_HPMIX_GAIN_NDB_6 |
+-			   RK3308_DAC_R_HPMIX_GAIN_NDB_6);
++static void rk3308_speaker_ctl(struct rk3308_codec_priv *rk3308, int on)
++{
++	if (on) {
++		if (rk3308->pa_drv_gpio) {
++			gpiod_direction_output(rk3308->pa_drv_gpio, on);
++			msleep(rk3308->delay_pa_drv_ms);
++		}
+ 
+-	/*
+-	 * Note2. If the ACODEC_DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3]
+-	 * is set to 0x1, add the steps from the section Disable DAC
+-	 * Configuration Standard Usage Flow after complete the step 19
+-	 */
++		if (rk3308->spk_ctl_gpio)
++			gpiod_direction_output(rk3308->spk_ctl_gpio, on);
++	} else {
++		if (rk3308->spk_ctl_gpio)
++			gpiod_direction_output(rk3308->spk_ctl_gpio, on);
+ 
+-	return 0;
++		if (rk3308->pa_drv_gpio) {
++			msleep(rk3308->delay_pa_drv_ms);
++			gpiod_direction_output(rk3308->pa_drv_gpio, on);
++		}
++	}
+ }
+ 
+-static int rk3308_codec_power_on(struct snd_soc_codec *codec)
++static int rk3308_codec_reset(struct snd_soc_codec *codec)
+ {
+ 	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
+ 
+-	/* 1. Supply the power of digital part and reset the Audio Codec */
+-	/* Do nothing */
++	reset_control_assert(rk3308->reset);
++	usleep_range(2000, 2500);	/* estimated value */
++	reset_control_deassert(rk3308->reset);
+ 
+-	/*
+-	 * 2. Configure ACODEC_DAC_ANA_CON1[1:0] and ACODEC_DAC_ANA_CON1[5:4]
+-	 *    to 0x1, to setup dc voltage of the DAC channel output
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
+-			   RK3308_DAC_POP_SOUND_L_MSK, RK3308_DAC_POP_SOUND_L_INIT);
+-	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
+-			   RK3308_DAC_POP_SOUND_R_MSK, RK3308_DAC_POP_SOUND_R_INIT);
++	regmap_write(rk3308->regmap, RK3308_GLB_CON, 0x00);
++	usleep_range(200, 300);		/* estimated value */
++	regmap_write(rk3308->regmap, RK3308_GLB_CON,
++		     RK3308_SYS_WORK |
++		     RK3308_DAC_DIG_WORK |
++		     RK3308_ADC_DIG_WORK);
+ 
+-	/*
+-	 * 3. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 0x1
+-	 *
+-	 * Note: Only the reg (ADC_ANA_CON10+0x0)[6:0] represent the control
+-	 * signal to select current to pre-charge/dis_charge
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
+-			   RK3308_ADC_CURRENT_CHARGE_MSK, RK3308_ADC_SEL_I_64(1));
++	return 0;
++}
+ 
+-	/* 4. Supply the power of the analog part(AVDD,AVDDRV) */
++static int rk3308_codec_adc_dig_reset(struct rk3308_codec_priv *rk3308)
++{
++	regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
++			   RK3308_ADC_DIG_WORK,
++			   RK3308_ADC_DIG_RESET);
++	udelay(50);
++	regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
++			   RK3308_ADC_DIG_WORK,
++			   RK3308_ADC_DIG_WORK);
+ 
+-	/*
+-	 * 5. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x1 to setup
+-	 *    reference voltage
+-	 *
+-	 * Note: Only the reg (ADC_ANA_CON10+0x0)[7] represent the enable
+-	 * signal of reference voltage module
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
+-			   RK3308_ADC_REF_EN, RK3308_ADC_REF_EN);
++	return 0;
++}
+ 
+-	/*
+-	 * 6. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to
+-	 *    0x7f step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to
+-	 *    0x7f directly. The suggestion slot time of the step is 20ms.
+-	 */
+-	mdelay(20);
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
+-			   RK3308_ADC_CURRENT_CHARGE_MSK,
+-			   RK3308_ADC_DONT_SEL_ALL);
++static int rk3308_codec_dac_dig_reset(struct rk3308_codec_priv *rk3308)
++{
++	regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
++			   RK3308_DAC_DIG_WORK,
++			   RK3308_DAC_DIG_RESET);
++	udelay(50);
++	regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
++			   RK3308_DAC_DIG_WORK,
++			   RK3308_DAC_DIG_WORK);
+ 
+-	/* 7. Wait until the voltage of VCM keeps stable at the AVDD/2 */
+-	usleep_range(200, 300);	/* estimated value */
++	return 0;
++}
+ 
+-	/*
+-	 * 8. Configure the register ACODEC_ADC_ANA_CON10[6:0] to the
+-	 *    appropriate value(expect 0x0) for reducing power.
+-	 */
++static int rk3308_set_bias_level(struct snd_soc_codec *codec,
++				 enum snd_soc_bias_level level)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
+ 
+-	 /* TODO: choose an appropriate charge value */
++	switch (level) {
++	case SND_SOC_BIAS_ON:
++		break;
++	case SND_SOC_BIAS_PREPARE:
++		break;
++	case SND_SOC_BIAS_STANDBY:
++		regcache_cache_only(rk3308->regmap, false);
++		regcache_sync(rk3308->regmap);
++		break;
++	case SND_SOC_BIAS_OFF:
++		break;
++	}
+ 
+ 	return 0;
+ }
+ 
+-static int rk3308_codec_power_off(struct snd_soc_codec *codec)
++static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai,
++			      unsigned int fmt)
+ {
++	struct snd_soc_codec *codec = codec_dai->codec;
+ 	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0;
++	int idx, grp, is_master;
++	int type = ADC_TYPE_ALL;
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBS_CFS:
++		adc_aif2 |= RK3308_ADC_IO_MODE_SLAVE;
++		adc_aif2 |= RK3308_ADC_MODE_SLAVE;
++		dac_aif2 |= RK3308_DAC_IO_MODE_SLAVE;
++		dac_aif2 |= RK3308_DAC_MODE_SLAVE;
++		is_master = 0;
++		break;
++	case SND_SOC_DAIFMT_CBM_CFM:
++		adc_aif2 |= RK3308_ADC_IO_MODE_MASTER;
++		adc_aif2 |= RK3308_ADC_MODE_MASTER;
++		dac_aif2 |= RK3308_DAC_IO_MODE_MASTER;
++		dac_aif2 |= RK3308_DAC_MODE_MASTER;
++		is_master = 1;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_DSP_A:
++		adc_aif1 |= RK3308_ADC_I2S_MODE_PCM;
++		dac_aif1 |= RK3308_DAC_I2S_MODE_PCM;
++		break;
++	case SND_SOC_DAIFMT_I2S:
++		adc_aif1 |= RK3308_ADC_I2S_MODE_I2S;
++		dac_aif1 |= RK3308_DAC_I2S_MODE_I2S;
++		break;
++	case SND_SOC_DAIFMT_RIGHT_J:
++		adc_aif1 |= RK3308_ADC_I2S_MODE_RJ;
++		dac_aif1 |= RK3308_DAC_I2S_MODE_RJ;
++		break;
++	case SND_SOC_DAIFMT_LEFT_J:
++		adc_aif1 |= RK3308_ADC_I2S_MODE_LJ;
++		dac_aif1 |= RK3308_DAC_I2S_MODE_LJ;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_NB_NF:
++		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL;
++		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL;
++		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL;
++		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL;
++		break;
++	case SND_SOC_DAIFMT_IB_IF:
++		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL;
++		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL;
++		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL;
++		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL;
++		break;
++	case SND_SOC_DAIFMT_IB_NF:
++		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL;
++		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL;
++		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL;
++		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL;
++		break;
++	case SND_SOC_DAIFMT_NB_IF:
++		adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL;
++		adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL;
++		dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL;
++		dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL;
++		break;
++	default:
++		return -EINVAL;
++	}
+ 
+ 	/*
+-	 * 1. Keep the power on and disable the DAC and ADC path according to
+-	 *    the section power on configuration standard usage flow.
++	 * Hold ADC Digital registers start at master mode
++	 *
++	 * There are 8 ADCs and use the same SCLK and LRCK internal for master
++	 * mode, We need to make sure that they are in effect at the same time,
++	 * otherwise they will cause the abnormal clocks.
+ 	 */
++	if (is_master)
++		regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
++				   RK3308_ADC_DIG_WORK,
++				   RK3308_ADC_DIG_RESET);
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp),
++				   RK3308_ADC_I2S_LRC_POL_MSK |
++				   RK3308_ADC_I2S_MODE_MSK,
++				   adc_aif1);
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp),
++				   RK3308_ADC_IO_MODE_MSK |
++				   RK3308_ADC_MODE_MSK |
++				   RK3308_ADC_I2S_BIT_CLK_POL_MSK,
++				   adc_aif2);
++	}
+ 
+-	/* 2. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 0x1 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
+-			   RK3308_ADC_CURRENT_CHARGE_MSK, RK3308_ADC_SEL_I_64(1));
++	/* Hold ADC Digital registers end at master mode */
++	if (is_master)
++		regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
++				   RK3308_ADC_DIG_WORK,
++				   RK3308_ADC_DIG_WORK);
+ 
+-	/* 3. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x0 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
+-			   RK3308_ADC_REF_EN, RK3308_ADC_REF_DIS);
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01,
++			   RK3308_DAC_I2S_LRC_POL_MSK |
++			   RK3308_DAC_I2S_MODE_MSK,
++			   dac_aif1);
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02,
++			   RK3308_DAC_IO_MODE_MSK |
++			   RK3308_DAC_MODE_MSK |
++			   RK3308_DAC_I2S_BIT_CLK_POL_MSK,
++			   dac_aif2);
++
++	return 0;
++}
++
++static int rk3308_codec_dac_dig_config(struct rk3308_codec_priv *rk3308,
++				       struct snd_pcm_hw_params *params)
++{
++	unsigned int dac_aif1 = 0, dac_aif2 = 0;
++
++	/* Clear the status of DAC DIG Digital reigisters */
++	rk3308_codec_dac_dig_reset(rk3308);
++
++	switch (params_format(params)) {
++	case SNDRV_PCM_FORMAT_S16_LE:
++		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_16BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S20_3LE:
++		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_20BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S24_LE:
++		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_24BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S32_LE:
++		dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_32BITS;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	dac_aif1 |= RK3308_DAC_I2S_LR_NORMAL;
++	dac_aif2 |= RK3308_DAC_I2S_WORK;
++
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01,
++			   RK3308_DAC_I2S_VALID_LEN_MSK |
++			   RK3308_DAC_I2S_LR_MSK,
++			   dac_aif1);
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02,
++			   RK3308_DAC_I2S_MSK,
++			   dac_aif2);
++
++	return 0;
++}
++
++static int rk3308_codec_adc_dig_config(struct rk3308_codec_priv *rk3308,
++				       struct snd_pcm_hw_params *params)
++{
++	unsigned int adc_aif1 = 0, adc_aif2 = 0;
++	int type = ADC_TYPE_NORMAL;
++	int idx, grp;
++
++	/* Clear the status of ADC DIG Digital reigisters */
++	rk3308_codec_adc_dig_reset(rk3308);
++
++	switch (params_format(params)) {
++	case SNDRV_PCM_FORMAT_S16_LE:
++		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_16BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S20_3LE:
++		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_20BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S24_LE:
++		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_24BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S32_LE:
++		adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_32BITS;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (params_channels(params)) {
++	case 1:
++		adc_aif1 |= RK3308_ADC_I2S_MONO;
++		break;
++	case 2:
++	case 4:
++	case 6:
++	case 8:
++		adc_aif1 |= RK3308_ADC_I2S_STEREO;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	adc_aif1 |= RK3308_ADC_I2S_LR_NORMAL;
++	adc_aif2 |= RK3308_ADC_I2S_WORK;
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp),
++				   RK3308_ADC_I2S_VALID_LEN_MSK |
++				   RK3308_ADC_I2S_LR_MSK |
++				   RK3308_ADC_I2S_TYPE_MSK,
++				   adc_aif1);
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp),
++				   RK3308_ADC_I2S_MSK,
++				   adc_aif2);
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_update_adc_grps(struct rk3308_codec_priv *rk3308,
++					struct snd_pcm_hw_params *params)
++{
++	switch (params_channels(params)) {
++	case 1:
++		rk3308->used_adc_grps = 1;
++		break;
++	case 2:
++	case 4:
++	case 6:
++	case 8:
++		rk3308->used_adc_grps = params_channels(params) / 2;
++		break;
++	default:
++		dev_err(rk3308->plat_dev, "Invalid channels: %d\n",
++			params_channels(params));
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int rk3308_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
++{
++	struct snd_soc_codec *codec = dai->codec;
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		int dgain;
++
++		if (mute) {
++			for (dgain = 0x2; dgain <= 0x7; dgain++) {
++				/*
++				 * Keep the max -> min digital CIC interpolation
++				 * filter gain step by step.
++				 *
++				 * loud: 0x2; whisper: 0x7
++				 */
++				regmap_update_bits(rk3308->regmap,
++						   RK3308_DAC_DIG_CON04,
++						   RK3308_DAC_CIC_IF_GAIN_MSK,
++						   dgain);
++				usleep_range(200, 300);  /* estimated value */
++			}
++
++#if !DEBUG_POP_ALWAYS
++			rk3308_headphone_ctl(rk3308, 0);
++			rk3308_speaker_ctl(rk3308, 0);
++#endif
++		} else {
++#if !DEBUG_POP_ALWAYS
++			if (rk3308->dac_output == DAC_LINEOUT)
++				rk3308_speaker_ctl(rk3308, 1);
++			else if (rk3308->dac_output == DAC_HPOUT)
++				rk3308_headphone_ctl(rk3308, 1);
++
++			if (rk3308->delay_start_play_ms)
++				msleep(rk3308->delay_start_play_ms);
++#endif
++			for (dgain = 0x7; dgain >= 0x2; dgain--) {
++				/*
++				 * Keep the min -> max digital CIC interpolation
++				 * filter gain step by step
++				 *
++				 * loud: 0x2; whisper: 0x7
++				 */
++				regmap_update_bits(rk3308->regmap,
++						   RK3308_DAC_DIG_CON04,
++						   RK3308_DAC_CIC_IF_GAIN_MSK,
++						   dgain);
++				usleep_range(200, 300);  /* estimated value */
++			}
++		}
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_digital_fadein(struct rk3308_codec_priv *rk3308)
++{
++	unsigned int dgain, dgain_ref;
++
++	if (rk3308->hpout_l_dgain != rk3308->hpout_r_dgain) {
++		pr_warn("HPOUT l_dgain: 0x%x != r_dgain: 0x%x\n",
++			rk3308->hpout_l_dgain, rk3308->hpout_r_dgain);
++		dgain_ref = min(rk3308->hpout_l_dgain, rk3308->hpout_r_dgain);
++	} else {
++		dgain_ref = rk3308->hpout_l_dgain;
++	}
+ 
+ 	/*
+-	 * 4.Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to 0x7f
+-	 *   step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to 0x7f
+-	 *   directly. The suggestion slot time of the step is 20ms
++	 * We'd better change the gain of the left and right channels
++	 * at the same time to avoid different listening
+ 	 */
+-	mdelay(20);
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
+-			   RK3308_ADC_CURRENT_CHARGE_MSK,
+-			   RK3308_ADC_DONT_SEL_ALL);
++	for (dgain = RK3308_DAC_L_HPOUT_GAIN_NDB_39;
++	     dgain <= dgain_ref; dgain++) {
++		/* Step 02 decrease dgains for de-pop */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05,
++				   RK3308_DAC_L_HPOUT_GAIN_MSK,
++				   dgain);
++
++		/* Step 02 decrease dgains for de-pop */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06,
++				   RK3308_DAC_R_HPOUT_GAIN_MSK,
++				   dgain);
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_digital_fadeout(struct rk3308_codec_priv *rk3308)
++{
++	unsigned int l_dgain, r_dgain;
++
++	/*
++	 * Note. In the step2, adjusting the register step by step to
++	 * the appropriate value and taking 20ms as time step
++	 */
++	regmap_read(rk3308->regmap, RK3308_DAC_ANA_CON05, &l_dgain);
++	l_dgain &= RK3308_DAC_L_HPOUT_GAIN_MSK;
++
++	regmap_read(rk3308->regmap, RK3308_DAC_ANA_CON06, &r_dgain);
++	r_dgain &= RK3308_DAC_R_HPOUT_GAIN_MSK;
++
++	if (l_dgain != r_dgain) {
++		pr_warn("HPOUT l_dgain: 0x%x != r_dgain: 0x%x\n",
++			l_dgain, r_dgain);
++		l_dgain = min(l_dgain, r_dgain);
++	}
++
++	/*
++	 * We'd better change the gain of the left and right channels
++	 * at the same time to avoid different listening
++	 */
++	while (l_dgain >= RK3308_DAC_L_HPOUT_GAIN_NDB_39) {
++		/* Step 02 decrease dgains for de-pop */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05,
++				   RK3308_DAC_L_HPOUT_GAIN_MSK,
++				   l_dgain);
++
++		/* Step 02 decrease dgains for de-pop */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06,
++				   RK3308_DAC_R_HPOUT_GAIN_MSK,
++				   l_dgain);
++
++		usleep_range(200, 300);  /* estimated value */
++
++		if (l_dgain == RK3308_DAC_L_HPOUT_GAIN_NDB_39)
++			break;
++
++		l_dgain--;
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_dac_lineout_enable(struct rk3308_codec_priv *rk3308)
++{
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/* Step 04 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
++				   RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
++				   RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
++				   RK3308_DAC_L_SEL_DC_FROM_INTERNAL |
++				   RK3308_DAC_R_SEL_DC_FROM_INTERNAL);
++	}
++
++	/* Step 07 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_EN |
++			   RK3308_DAC_R_LINEOUT_EN,
++			   RK3308_DAC_L_LINEOUT_EN |
++			   RK3308_DAC_R_LINEOUT_EN);
++
++	udelay(20);
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/* Step 10 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
++				   RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
++				   RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
++				   RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL |
++				   RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL);
++
++		udelay(20);
++	}
++
++	/* Step 19 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_UNMUTE |
++			   RK3308_DAC_R_LINEOUT_UNMUTE,
++			   RK3308_DAC_L_LINEOUT_UNMUTE |
++			   RK3308_DAC_R_LINEOUT_UNMUTE);
++	udelay(20);
++
++	return 0;
++}
++
++static int rk3308_codec_dac_lineout_disable(struct rk3308_codec_priv *rk3308)
++{
++	/* Step 08 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_UNMUTE |
++			   RK3308_DAC_R_LINEOUT_UNMUTE,
++			   RK3308_DAC_L_LINEOUT_MUTE |
++			   RK3308_DAC_R_LINEOUT_MUTE);
++
++	/* Step 09 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_EN |
++			   RK3308_DAC_R_LINEOUT_EN,
++			   RK3308_DAC_L_LINEOUT_DIS |
++			   RK3308_DAC_R_LINEOUT_DIS);
++
++	return 0;
++}
++
++static int rk3308_codec_dac_hpout_enable(struct rk3308_codec_priv *rk3308)
++{
++	/* Step 03 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_HPOUT_POP_SOUND_L_MSK |
++			   RK3308_DAC_HPOUT_POP_SOUND_R_MSK,
++			   RK3308_DAC_HPOUT_POP_SOUND_L_WORK |
++			   RK3308_DAC_HPOUT_POP_SOUND_R_WORK);
++
++	udelay(20);
++
++	/* Step 07 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_EN |
++			   RK3308_DAC_R_HPOUT_EN,
++			   RK3308_DAC_L_HPOUT_EN |
++			   RK3308_DAC_R_HPOUT_EN);
++
++	udelay(20);
++
++	/* Step 08 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_WORK |
++			   RK3308_DAC_R_HPOUT_WORK,
++			   RK3308_DAC_L_HPOUT_WORK |
++			   RK3308_DAC_R_HPOUT_WORK);
++
++	udelay(20);
++
++	/* Step 16 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_UNMUTE |
++			   RK3308_DAC_R_HPOUT_UNMUTE,
++			   RK3308_DAC_L_HPOUT_UNMUTE |
++			   RK3308_DAC_R_HPOUT_UNMUTE);
++
++	udelay(20);
++
++	return 0;
++}
++
++static int rk3308_codec_dac_hpout_disable(struct rk3308_codec_priv *rk3308)
++{
++	/* Step 03 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_HPOUT_POP_SOUND_L_MSK |
++			   RK3308_DAC_HPOUT_POP_SOUND_R_MSK,
++			   RK3308_DAC_HPOUT_POP_SOUND_L_INIT |
++			   RK3308_DAC_HPOUT_POP_SOUND_R_INIT);
++
++	/* Step 07 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_EN |
++			   RK3308_DAC_R_HPOUT_EN,
++			   RK3308_DAC_L_HPOUT_DIS |
++			   RK3308_DAC_R_HPOUT_DIS);
++
++	/* Step 08 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_WORK |
++			   RK3308_DAC_R_HPOUT_WORK,
++			   RK3308_DAC_L_HPOUT_INIT |
++			   RK3308_DAC_R_HPOUT_INIT);
++
++	/* Step 16 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_UNMUTE |
++			   RK3308_DAC_R_HPOUT_UNMUTE,
++			   RK3308_DAC_L_HPOUT_MUTE |
++			   RK3308_DAC_R_HPOUT_MUTE);
++
++	return 0;
++}
++
++static int rk3308_codec_dac_switch(struct rk3308_codec_priv *rk3308,
++				   int dac_output)
++{	int ret = 0;
++
++	if (rk3308->dac_output == dac_output) {
++		dev_info(rk3308->plat_dev,
++			 "Don't need to change dac_output: %d\n", dac_output);
++		goto out;
++	}
++
++	switch (dac_output) {
++	case DAC_LINEOUT:
++	case DAC_HPOUT:
++	case DAC_LINEOUT_HPOUT:
++		break;
++	default:
++		dev_err(rk3308->plat_dev, "Unknown value: %d\n", dac_output);
++		ret = -EINVAL;
++		goto out;
++	}
++
++	if (rk3308_codec_get_dac_path_state(rk3308) == PATH_BUSY) {
++		/*
++		 * We can only switch the audio path to LINEOUT or HPOUT on
++		 * codec during playbacking, otherwise, just update the
++		 * dac_output flag.
++		 */
++		switch (dac_output) {
++		case DAC_LINEOUT:
++			rk3308_headphone_ctl(rk3308, 0);
++			rk3308_speaker_ctl(rk3308, 1);
++			rk3308_codec_dac_hpout_disable(rk3308);
++			rk3308_codec_dac_lineout_enable(rk3308);
++			break;
++		case DAC_HPOUT:
++			rk3308_speaker_ctl(rk3308, 0);
++			rk3308_headphone_ctl(rk3308, 1);
++			rk3308_codec_dac_lineout_disable(rk3308);
++			rk3308_codec_dac_hpout_enable(rk3308);
++			break;
++		case DAC_LINEOUT_HPOUT:
++			rk3308_speaker_ctl(rk3308, 1);
++			rk3308_headphone_ctl(rk3308, 1);
++			rk3308_codec_dac_lineout_enable(rk3308);
++			rk3308_codec_dac_hpout_enable(rk3308);
++			break;
++		default:
++			break;
++		}
++	}
++
++	rk3308->dac_output = dac_output;
++out:
++	dev_dbg(rk3308->plat_dev, "switch dac_output to: %d\n",
++		rk3308->dac_output);
++
++	return ret;
++}
++
++static int rk3308_codec_dac_enable(struct rk3308_codec_priv *rk3308)
++{
++	/*
++	 * Note1. If the ACODEC_DAC_ANA_CON12[6] or ACODEC_DAC_ANA_CON12[2]
++	 * is set to 0x1, ignoring the step9~12.
++	 */
++
++	/*
++	 * Note2. If the ACODEC_ DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3]
++	 * is set to 0x1, the ADC0 or ADC1 should be enabled firstly, and
++	 * please refer to Enable ADC Configuration Standard Usage Flow(expect
++	 * step7~step9,step14).
++	 */
++
++	/*
++	 * Note3. If no opening the line out, ignoring the step6, step17 and
++	 * step19.
++	 */
++
++	/*
++	 * Note4. If no opening the headphone out, ignoring the step3,step7~8,
++	 * step16 and step18.
++	 */
++
++	/*
++	 * Note5. In the step18, adjust the register step by step to the
++	 * appropriate value and taking 10ms as one time step
++	 */
++
++	/*
++	 * 1. Set the ACODEC_DAC_ANA_CON0[0] to 0x1, to enable the current
++	 * source of DAC
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
++			   RK3308_DAC_CURRENT_MSK,
++			   RK3308_DAC_CURRENT_EN);
++
++	udelay(20);
++
++	/*
++	 * 2. Set the ACODEC_DAC_ANA_CON1[6] and ACODEC_DAC_ANA_CON1[2] to 0x1,
++	 * to enable the reference voltage buffer
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_BUF_REF_L_MSK |
++			   RK3308_DAC_BUF_REF_R_MSK,
++			   RK3308_DAC_BUF_REF_L_EN |
++			   RK3308_DAC_BUF_REF_R_EN);
++
++	/* Waiting the stable reference voltage */
++	mdelay(1);
++
++	if (rk3308->dac_output == DAC_HPOUT ||
++	    rk3308->dac_output == DAC_LINEOUT_HPOUT) {
++		/* Step 03 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++				   RK3308_DAC_HPOUT_POP_SOUND_L_MSK |
++				   RK3308_DAC_HPOUT_POP_SOUND_R_MSK,
++				   RK3308_DAC_HPOUT_POP_SOUND_L_WORK |
++				   RK3308_DAC_HPOUT_POP_SOUND_R_WORK);
++
++		udelay(20);
++	}
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B &&
++	    (rk3308->dac_output == DAC_LINEOUT ||
++	     rk3308->dac_output == DAC_LINEOUT_HPOUT)) {
++		/* Step 04 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
++				   RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
++				   RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
++				   RK3308_DAC_L_SEL_DC_FROM_INTERNAL |
++				   RK3308_DAC_R_SEL_DC_FROM_INTERNAL);
++
++		udelay(20);
++	}
++
++	/* Step 05 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_EN |
++			   RK3308_DAC_R_HPMIX_EN,
++			   RK3308_DAC_L_HPMIX_EN |
++			   RK3308_DAC_R_HPMIX_EN);
++
++	/* Waiting the stable HPMIX */
++	mdelay(1);
++
++	/* Step 06. Reset HPMIX and recover HPMIX gains */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_WORK |
++			   RK3308_DAC_R_HPMIX_WORK,
++			   RK3308_DAC_L_HPMIX_INIT |
++			   RK3308_DAC_R_HPMIX_INIT);
++	udelay(50);
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_WORK |
++			   RK3308_DAC_R_HPMIX_WORK,
++			   RK3308_DAC_L_HPMIX_WORK |
++			   RK3308_DAC_R_HPMIX_WORK);
++
++	udelay(20);
++
++	if (rk3308->dac_output == DAC_LINEOUT ||
++	    rk3308->dac_output == DAC_LINEOUT_HPOUT) {
++		/* Step 07 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++				   RK3308_DAC_L_LINEOUT_EN |
++				   RK3308_DAC_R_LINEOUT_EN,
++				   RK3308_DAC_L_LINEOUT_EN |
++				   RK3308_DAC_R_LINEOUT_EN);
++
++		udelay(20);
++	}
++
++	if (rk3308->dac_output == DAC_HPOUT ||
++	    rk3308->dac_output == DAC_LINEOUT_HPOUT) {
++		/* Step 08 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++				   RK3308_DAC_L_HPOUT_EN |
++				   RK3308_DAC_R_HPOUT_EN,
++				   RK3308_DAC_L_HPOUT_EN |
++				   RK3308_DAC_R_HPOUT_EN);
++
++		udelay(20);
++
++		/* Step 09 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++				   RK3308_DAC_L_HPOUT_WORK |
++				   RK3308_DAC_R_HPOUT_WORK,
++				   RK3308_DAC_L_HPOUT_WORK |
++				   RK3308_DAC_R_HPOUT_WORK);
++
++		udelay(20);
++	}
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/* Step 10 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
++				   RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
++				   RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
++				   RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL |
++				   RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL);
++
++		udelay(20);
++	}
++
++	/* Step 11 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_REF_EN |
++			   RK3308_DAC_R_REF_EN,
++			   RK3308_DAC_L_REF_EN |
++			   RK3308_DAC_R_REF_EN);
++
++	udelay(20);
++
++	/* Step 12 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_CLK_EN |
++			   RK3308_DAC_R_CLK_EN,
++			   RK3308_DAC_L_CLK_EN |
++			   RK3308_DAC_R_CLK_EN);
++
++	udelay(20);
++
++	/* Step 13 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_DAC_EN |
++			   RK3308_DAC_R_DAC_EN,
++			   RK3308_DAC_L_DAC_EN |
++			   RK3308_DAC_R_DAC_EN);
++
++	udelay(20);
++
++	/* Step 14 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_DAC_WORK |
++			   RK3308_DAC_R_DAC_WORK,
++			   RK3308_DAC_L_DAC_WORK |
++			   RK3308_DAC_R_DAC_WORK);
++
++	udelay(20);
++
++	/* Step 15 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
++			   RK3308_DAC_L_HPMIX_SEL_MSK |
++			   RK3308_DAC_R_HPMIX_SEL_MSK,
++			   RK3308_DAC_L_HPMIX_I2S |
++			   RK3308_DAC_R_HPMIX_I2S);
++
++	udelay(20);
++
++	/* Step 16 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_UNMUTE |
++			   RK3308_DAC_R_HPMIX_UNMUTE,
++			   RK3308_DAC_L_HPMIX_UNMUTE |
++			   RK3308_DAC_R_HPMIX_UNMUTE);
++
++	udelay(20);
++
++	/* Step 17: Put configuration HPMIX Gain to DAPM */
++
++	if (rk3308->dac_output == DAC_HPOUT ||
++	    rk3308->dac_output == DAC_LINEOUT_HPOUT) {
++		/* Step 18 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++				   RK3308_DAC_L_HPOUT_UNMUTE |
++				   RK3308_DAC_R_HPOUT_UNMUTE,
++				   RK3308_DAC_L_HPOUT_UNMUTE |
++				   RK3308_DAC_R_HPOUT_UNMUTE);
++
++		udelay(20);
++	}
++
++	if (rk3308->dac_output == DAC_LINEOUT ||
++	    rk3308->dac_output == DAC_LINEOUT_HPOUT) {
++		/* Step 19 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++				   RK3308_DAC_L_LINEOUT_UNMUTE |
++				   RK3308_DAC_R_LINEOUT_UNMUTE,
++				   RK3308_DAC_L_LINEOUT_UNMUTE |
++				   RK3308_DAC_R_LINEOUT_UNMUTE);
++		udelay(20);
++	}
++
++	/* Step 20, put configuration HPOUT gain to DAPM control */
++	/* Step 21, put configuration LINEOUT gain to DAPM control */
++
++	if (rk3308->dac_output == DAC_HPOUT ||
++	    rk3308->dac_output == DAC_LINEOUT_HPOUT) {
++		/* Just for HPOUT */
++		rk3308_codec_digital_fadein(rk3308);
++	}
++
++	rk3308->dac_endisable = true;
++
++	/* TODO: TRY TO TEST DRIVE STRENGTH */
++
++	return 0;
++}
++
++static int rk3308_codec_dac_disable(struct rk3308_codec_priv *rk3308)
++{
++	/*
++	 * Step 00 skipped. Keep the DAC channel work and input the mute signal.
++	 */
++
++	/* Step 01 skipped. May set the min gain for LINEOUT. */
++
++	/* Step 02 skipped. May set the min gain for HPOUT. */
++
++	if (rk3308->dac_output == DAC_HPOUT ||
++	    rk3308->dac_output == DAC_LINEOUT_HPOUT) {
++		/* Just for HPOUT */
++		rk3308_codec_digital_fadeout(rk3308);
++	}
++
++	/* Step 03 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_UNMUTE |
++			   RK3308_DAC_R_HPMIX_UNMUTE,
++			   RK3308_DAC_L_HPMIX_UNMUTE |
++			   RK3308_DAC_R_HPMIX_UNMUTE);
++
++	/* Step 04 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
++			   RK3308_DAC_L_HPMIX_SEL_MSK |
++			   RK3308_DAC_R_HPMIX_SEL_MSK,
++			   RK3308_DAC_L_HPMIX_NONE |
++			   RK3308_DAC_R_HPMIX_NONE);
++	/* Step 05 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_UNMUTE |
++			   RK3308_DAC_R_HPOUT_UNMUTE,
++			   RK3308_DAC_L_HPOUT_MUTE |
++			   RK3308_DAC_R_HPOUT_MUTE);
++
++	/* Step 06 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_DAC_WORK |
++			   RK3308_DAC_R_DAC_WORK,
++			   RK3308_DAC_L_DAC_INIT |
++			   RK3308_DAC_R_DAC_INIT);
++
++	/* Step 07 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_EN |
++			   RK3308_DAC_R_HPOUT_EN,
++			   RK3308_DAC_L_HPOUT_DIS |
++			   RK3308_DAC_R_HPOUT_DIS);
++
++	/* Step 08 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_UNMUTE |
++			   RK3308_DAC_R_LINEOUT_UNMUTE,
++			   RK3308_DAC_L_LINEOUT_MUTE |
++			   RK3308_DAC_R_LINEOUT_MUTE);
++
++	/* Step 09 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_EN |
++			   RK3308_DAC_R_LINEOUT_EN,
++			   RK3308_DAC_L_LINEOUT_DIS |
++			   RK3308_DAC_R_LINEOUT_DIS);
++
++	/* Step 10 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_EN |
++			   RK3308_DAC_R_HPMIX_EN,
++			   RK3308_DAC_L_HPMIX_DIS |
++			   RK3308_DAC_R_HPMIX_DIS);
++
++	/* Step 11 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_DAC_EN |
++			   RK3308_DAC_R_DAC_EN,
++			   RK3308_DAC_L_DAC_DIS |
++			   RK3308_DAC_R_DAC_DIS);
++
++	/* Step 12 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_CLK_EN |
++			   RK3308_DAC_R_CLK_EN,
++			   RK3308_DAC_L_CLK_DIS |
++			   RK3308_DAC_R_CLK_DIS);
++
++	/* Step 13 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
++			   RK3308_DAC_L_REF_EN |
++			   RK3308_DAC_R_REF_EN,
++			   RK3308_DAC_L_REF_DIS |
++			   RK3308_DAC_R_REF_DIS);
++
++	/* Step 14 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_HPOUT_POP_SOUND_L_MSK |
++			   RK3308_DAC_HPOUT_POP_SOUND_R_MSK,
++			   RK3308_DAC_HPOUT_POP_SOUND_L_INIT |
++			   RK3308_DAC_HPOUT_POP_SOUND_R_INIT);
++
++	/* Step 15 */
++	if (rk3308->codec_ver == ACODEC_VERSION_B &&
++	    (rk3308->dac_output == DAC_LINEOUT ||
++	     rk3308->dac_output == DAC_LINEOUT_HPOUT)) {
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
++				   RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
++				   RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
++				   RK3308_DAC_L_SEL_DC_FROM_VCM |
++				   RK3308_DAC_R_SEL_DC_FROM_VCM);
++	}
++
++	/* Step 16 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_BUF_REF_L_EN |
++			   RK3308_DAC_BUF_REF_R_EN,
++			   RK3308_DAC_BUF_REF_L_DIS |
++			   RK3308_DAC_BUF_REF_R_DIS);
++
++	/* Step 17 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
++			   RK3308_DAC_CURRENT_EN,
++			   RK3308_DAC_CURRENT_DIS);
++
++	/* Step 18 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
++			   RK3308_DAC_L_HPOUT_WORK |
++			   RK3308_DAC_R_HPOUT_WORK,
++			   RK3308_DAC_L_HPOUT_INIT |
++			   RK3308_DAC_R_HPOUT_INIT);
++
++	/* Step 19 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
++			   RK3308_DAC_L_HPMIX_WORK |
++			   RK3308_DAC_R_HPMIX_WORK,
++			   RK3308_DAC_L_HPMIX_WORK |
++			   RK3308_DAC_R_HPMIX_WORK);
++
++	/* Step 20 skipped, may set the min gain for HPOUT. */
++
++	/*
++	 * Note2. If the ACODEC_DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3]
++	 * is set to 0x1, add the steps from the section Disable ADC
++	 * Configuration Standard Usage Flow after complete the step 19
++	 *
++	 * IF USING LINE-IN
++	 * rk3308_codec_adc_ana_disable(rk3308, type);
++	 */
++
++	rk3308->dac_endisable = false;
++
++	return 0;
++}
++
++static int rk3308_codec_power_on(struct rk3308_codec_priv *rk3308)
++{
++	unsigned int v;
++
++	/* 0. Supply the power of digital part and reset the Audio Codec */
++	/* Do nothing */
++
++	/*
++	 * 1. Configure ACODEC_DAC_ANA_CON1[1:0] and ACODEC_DAC_ANA_CON1[5:4]
++	 *    to 0x1, to setup dc voltage of the DAC channel output.
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_HPOUT_POP_SOUND_L_MSK,
++			   RK3308_DAC_HPOUT_POP_SOUND_L_INIT);
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
++			   RK3308_DAC_HPOUT_POP_SOUND_R_MSK,
++			   RK3308_DAC_HPOUT_POP_SOUND_R_INIT);
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/*
++		 * 2. Configure ACODEC_DAC_ANA_CON15[1:0] and
++		 *    ACODEC_DAC_ANA_CON15[5:4] to 0x1, to setup dc voltage of
++		 *    the DAC channel output.
++		 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
++				   RK3308_DAC_LINEOUT_POP_SOUND_L_MSK,
++				   RK3308_DAC_L_SEL_DC_FROM_VCM);
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
++				   RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
++				   RK3308_DAC_R_SEL_DC_FROM_VCM);
++	}
++
++	/*
++	 * 3. Configure the register ACODEC_ADC_ANA_CON10[3:0] to 7’b000_0001.
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_CURRENT_CHARGE_MSK,
++			   RK3308_ADC_SEL_I(0x1));
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/*
++		 * 4. Configure the register ACODEC_ADC_ANA_CON14[3:0] to
++		 *    4’b0001.
++		 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
++				   RK3308_DAC_CURRENT_CHARGE_MSK,
++				   RK3308_DAC_SEL_I(0x1));
++	}
++
++	/* 5. Supply the power of the analog part(AVDD,AVDDRV) */
++
++	/*
++	 * 6. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x1 to setup
++	 *    reference voltage
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_REF_EN, RK3308_ADC_REF_EN);
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/*
++		 * 7. Configure the register ACODEC_ADC_ANA_CON14[4] to 0x1 to
++		 *    setup reference voltage
++		 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
++				   RK3308_DAC_VCM_LINEOUT_EN,
++				   RK3308_DAC_VCM_LINEOUT_EN);
++	}
++
++	/*
++	 * 8. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to
++	 *    0x7f step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to
++	 *    0x7f directly. Here the slot time of the step is 200us.
++	 */
++	for (v = 0x1; v <= 0x7f; v++) {
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++				   RK3308_ADC_CURRENT_CHARGE_MSK,
++				   v);
++		udelay(200);
++	}
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/*
++		 * 9. Change the register ACODEC_ADC_ANA_CON14[3:0] from the 0x1
++		 *    to 0xf step by step or configure the
++		 *    ACODEC_ADC_ANA_CON14[3:0] to 0xf directly. Here the slot
++		 *    time of the step is 200us.
++		 */
++		for (v = 0x1; v <= 0xf; v++) {
++			regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
++					   RK3308_DAC_CURRENT_CHARGE_MSK,
++					   v);
++			udelay(200);
++		}
++	}
++
++	/* 10. Wait until the voltage of VCM keeps stable at the AVDD/2 */
++	msleep(20);	/* estimated value */
++
++	/*
++	 * 11. Configure the register ACODEC_ADC_ANA_CON10[6:0] to the
++	 *     appropriate value(expect 0x0) for reducing power.
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_CURRENT_CHARGE_MSK, 0x7c);
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/*
++		 * 12. Configure the register ACODEC_DAC_ANA_CON14[6:0] to the
++		 *     appropriate value(expect 0x0) for reducing power.
++		 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
++				   RK3308_DAC_CURRENT_CHARGE_MSK, 0xf);
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_power_off(struct rk3308_codec_priv *rk3308)
++{
++	unsigned int v;
++
++	/*
++	 * 0. Keep the power on and disable the DAC and ADC path according to
++	 *    the section power on configuration standard usage flow.
++	 */
++
++	/*
++	 * 1. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 7’b000_0001.
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_CURRENT_CHARGE_MSK,
++			   RK3308_ADC_SEL_I(0x1));
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/*
++		 * 2. Configure the register ACODEC_DAC_ANA_CON14[3:0] to
++		 *    4’b0001.
++		 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
++				   RK3308_DAC_CURRENT_CHARGE_MSK,
++				   RK3308_DAC_SEL_I(0x1));
++	}
++
++	/* 3. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x0 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++			   RK3308_ADC_REF_EN,
++			   RK3308_ADC_REF_DIS);
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/* 4. Configure the register ACODEC_DAC_ANA_CON14[7] to 0x0 */
++		regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
++				   RK3308_DAC_VCM_LINEOUT_EN,
++				   RK3308_DAC_VCM_LINEOUT_DIS);
++	}
++
++	/*
++	 * 5. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to 0x7f
++	 *    step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to 0x7f
++	 *    directly. Here the slot time of the step is 200us.
++	 */
++	for (v = 0x1; v <= 0x7f; v++) {
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
++				   RK3308_ADC_CURRENT_CHARGE_MSK,
++				   v);
++		udelay(200);
++	}
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/*
++		 * 6. Change the register ACODEC_DAC_ANA_CON14[3:0] from the 0x1
++		 *    to 0xf step by step or configure the
++		 *    ACODEC_DAC_ANA_CON14[3:0] to 0xf directly. Here the slot
++		 *    time of the step is 200us.
++		 */
++		for (v = 0x1; v <= 0x7f; v++) {
++			regmap_update_bits(rk3308->regmap,
++					   RK3308_ADC_ANA_CON10(0),
++					   RK3308_ADC_CURRENT_CHARGE_MSK,
++					   v);
++			udelay(200);
++		}
++	}
++
++	/* 7. Wait until the voltage of VCM keeps stable at the AGND */
++	msleep(20);	/* estimated value */
++
++	/* 8. Power off the analog power supply */
++	/* 9. Power off the digital power supply */
++
++	/* Do something via hardware */
++
++	return 0;
++}
++
++static int rk3308_codec_headset_detect_enable(struct rk3308_codec_priv *rk3308)
++{
++	/*
++	 * Set ACODEC_DAC_ANA_CON0[1] to 0x1, to enable the headset insert
++	 * detection
++	 *
++	 * Note. When the voltage of PAD HPDET> 8*AVDD/9, the output value of
++	 * the pin_hpdet will be set to 0x1 and assert a interrupt
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
++			   RK3308_DAC_HEADPHONE_DET_MSK,
++			   RK3308_DAC_HEADPHONE_DET_EN);
++
++	return 0;
++}
++
++static int rk3308_codec_headset_detect_disable(struct rk3308_codec_priv *rk3308)
++{
++	/*
++	 * Set ACODEC_DAC_ANA_CON0[1] to 0x0, to disable the headset insert
++	 * detection
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
++			   RK3308_DAC_HEADPHONE_DET_MSK,
++			   RK3308_DAC_HEADPHONE_DET_DIS);
++
++	return 0;
++}
++
++static int rk3308_codec_check_i2s_sdis(struct rk3308_codec_priv *rk3308,
++				       int num)
++{
++	int i, j, ret = 0;
++
++	switch (num) {
++	case 1:
++		rk3308->which_i2s = ACODEC_TO_I2S1_2CH;
++		break;
++	case 2:
++		rk3308->which_i2s = ACODEC_TO_I2S3_4CH;
++		break;
++	case 4:
++		rk3308->which_i2s = ACODEC_TO_I2S2_8CH;
++		break;
++	default:
++		dev_err(rk3308->plat_dev, "Invalid i2s sdis num: %d\n", num);
++		ret = -EINVAL;
++		goto err;
++	}
++
++	for (i = 0; i < num; i++) {
++		if (rk3308->i2s_sdis[i] > ADC_LR_GROUP_MAX - 1) {
++			dev_err(rk3308->plat_dev,
++				"i2s_sdis[%d]: %d is overflow\n",
++				i, rk3308->i2s_sdis[i]);
++			ret = -EINVAL;
++			goto err;
++		}
++
++		for (j = 0; j < num; j++) {
++			if (i == j)
++				continue;
++
++			if (rk3308->i2s_sdis[i] == rk3308->i2s_sdis[j]) {
++				dev_err(rk3308->plat_dev,
++					"Invalid i2s_sdis: [%d]%d == [%d]%d\n",
++					i, rk3308->i2s_sdis[i],
++					j, rk3308->i2s_sdis[j]);
++				ret = -EINVAL;
++				goto err;
++			}
++		}
++	}
++
++err:
++	return ret;
++}
++
++static int rk3308_codec_adc_grps_route_config(struct rk3308_codec_priv *rk3308)
++{
++	int idx = 0;
++
++	if (rk3308->which_i2s == ACODEC_TO_I2S2_8CH) {
++		for (idx = 0; idx < rk3308->to_i2s_grps; idx++) {
++			regmap_write(rk3308->grf, GRF_SOC_CON1,
++				     GRF_I2S2_8CH_SDI(idx, rk3308->i2s_sdis[idx]));
++		}
++	} else if (rk3308->which_i2s == ACODEC_TO_I2S3_4CH) {
++		for (idx = 0; idx < rk3308->to_i2s_grps; idx++) {
++			regmap_write(rk3308->grf, GRF_SOC_CON1,
++				     GRF_I2S3_4CH_SDI(idx, rk3308->i2s_sdis[idx]));
++		}
++	} else if (rk3308->which_i2s == ACODEC_TO_I2S1_2CH) {
++		regmap_write(rk3308->grf, GRF_SOC_CON1,
++			     GRF_I2S1_2CH_SDI(rk3308->i2s_sdis[idx]));
++	}
++
++	return 0;
++}
++
++/* Put default one-to-one mapping */
++static int rk3308_codec_adc_grps_route_default(struct rk3308_codec_priv *rk3308)
++{
++	unsigned int idx;
++
++	/*
++	 * The GRF values may be kept the previous status after hot reboot,
++	 * if the property 'rockchip,adc-grps-route' is not set, we need to
++	 * recover default the order of sdi/sdo for i2s2_8ch/i2s3_8ch/i2s1_2ch.
++	 */
++	regmap_write(rk3308->grf, GRF_SOC_CON1,
++		     GRF_I2S1_2CH_SDI(0));
++
++	for (idx = 0; idx < 2; idx++) {
++		regmap_write(rk3308->grf, GRF_SOC_CON1,
++			     GRF_I2S3_4CH_SDI(idx, idx));
++	}
++
++	/* Using i2s2_8ch by default. */
++	rk3308->which_i2s = ACODEC_TO_I2S2_8CH;
++	rk3308->to_i2s_grps = ADC_LR_GROUP_MAX;
++
++	for (idx = 0; idx < ADC_LR_GROUP_MAX; idx++) {
++		rk3308->i2s_sdis[idx] = idx;
++		regmap_write(rk3308->grf, GRF_SOC_CON1,
++			     GRF_I2S2_8CH_SDI(idx, idx));
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_adc_grps_route(struct rk3308_codec_priv *rk3308,
++				       struct device_node *np)
++{
++	int num, ret;
++
++	num = of_count_phandle_with_args(np, "rockchip,adc-grps-route", NULL);
++	if (num < 0) {
++		if (num == -ENOENT) {
++			/* Not use 'rockchip,adc-grps-route' property here */
++			rk3308_codec_adc_grps_route_default(rk3308);
++			ret = 0;
++		} else {
++			dev_err(rk3308->plat_dev,
++				"Failed to read 'rockchip,adc-grps-route' num: %d\n",
++				num);
++			ret = num;
++		}
++		return ret;
++	}
++
++	ret = of_property_read_u32_array(np, "rockchip,adc-grps-route",
++					 rk3308->i2s_sdis, num);
++	if (ret < 0) {
++		dev_err(rk3308->plat_dev,
++			"Failed to read 'rockchip,adc-grps-route': %d\n",
++			ret);
++		return ret;
++	}
++
++	ret = rk3308_codec_check_i2s_sdis(rk3308, num);
++	if (ret < 0) {
++		dev_err(rk3308->plat_dev,
++			"Failed to check i2s_sdis: %d\n", ret);
++		return ret;
++	}
++
++	rk3308->to_i2s_grps = num;
++
++	rk3308_codec_adc_grps_route_config(rk3308);
++
++	return 0;
++}
++
++static int check_micbias(int micbias)
++{
++	switch (micbias) {
++	case RK3308_ADC_MICBIAS_VOLT_0_85:
++	case RK3308_ADC_MICBIAS_VOLT_0_8:
++	case RK3308_ADC_MICBIAS_VOLT_0_75:
++	case RK3308_ADC_MICBIAS_VOLT_0_7:
++	case RK3308_ADC_MICBIAS_VOLT_0_65:
++	case RK3308_ADC_MICBIAS_VOLT_0_6:
++	case RK3308_ADC_MICBIAS_VOLT_0_55:
++	case RK3308_ADC_MICBIAS_VOLT_0_5:
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
++static bool handle_loopback(struct rk3308_codec_priv *rk3308)
++{
++	/* The version B doesn't need to handle loopback. */
++	if (rk3308->codec_ver == ACODEC_VERSION_B)
++		return false;
++
++	switch (rk3308->loopback_grp) {
++	case 0:
++	case 1:
++	case 2:
++	case 3:
++		return true;
++	}
++
++	return false;
++}
++
++static bool has_en_always_grps(struct rk3308_codec_priv *rk3308)
++{
++	int idx;
++
++	if (rk3308->en_always_grps_num) {
++		for (idx = 0; idx < ADC_LR_GROUP_MAX; idx++) {
++			if (rk3308->en_always_grps[idx] >= 0 &&
++			    rk3308->en_always_grps[idx] <= ADC_LR_GROUP_MAX - 1)
++				return true;
++		}
++	}
++
++	return false;
++}
++
++static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308,
++				       int micbias)
++{
++	int ret;
++
++	if (rk3308->ext_micbias != EXT_MICBIAS_NONE)
++		return 0;
++
++	/* 0. Power up the ACODEC and keep the AVDDH stable */
++
++	/* Step 1. Configure ACODEC_ADC_ANA_CON7[2:0] to the certain value */
++	ret = check_micbias(micbias);
++	if (ret < 0) {
++		dev_err(rk3308->plat_dev, "This is an invalid micbias: %d\n",
++			micbias);
++		return ret;
++	}
++
++	/*
++	 * Note: Only the reg (ADC_ANA_CON7+0x0)[2:0] represent the level range
++	 * control signal of MICBIAS voltage
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0),
++			   RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK,
++			   micbias);
++
++	/* Step 2. Wait until the VCMH keep stable */
++	msleep(20);	/* estimated value */
++
++	/*
++	 * Step 3. Configure ACODEC_ADC_ANA_CON8[4] to 0x1
++	 *
++	 * Note: Only the reg (ADC_ANA_CON8+0x0)[4] represent the enable
++	 * signal of current source for MICBIAS
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(0),
++			   RK3308_ADC_MICBIAS_CURRENT_MSK,
++			   RK3308_ADC_MICBIAS_CURRENT_EN);
++
++	/*
++	 * Step 4. Configure the (ADC_ANA_CON7+0x40)[3] or
++	 * (ADC_ANA_CON7+0x80)[3] to 0x1.
++	 *
++	 * (ADC_ANA_CON7+0x40)[3] used to control the MICBIAS1, and
++	 * (ADC_ANA_CON7+0x80)[3] used to control the MICBIAS2
++	 */
++	if (rk3308->micbias1)
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(1),
++				   RK3308_ADC_MIC_BIAS_BUF_EN,
++				   RK3308_ADC_MIC_BIAS_BUF_EN);
++
++	if (rk3308->micbias2)
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(2),
++				   RK3308_ADC_MIC_BIAS_BUF_EN,
++				   RK3308_ADC_MIC_BIAS_BUF_EN);
++
++	/* waiting micbias stabled*/
++	mdelay(50);
++
++	rk3308->enable_micbias = true;
++
++	return 0;
++}
++
++static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308)
++{
++	if (rk3308->ext_micbias != EXT_MICBIAS_NONE)
++		return 0;
++
++	/* Step 0. Enable the MICBIAS and keep the Audio Codec stable */
++	/* Do nothing */
++
++	/*
++	 * Step 1. Configure the (ADC_ANA_CON7+0x40)[3] or
++	 * (ADC_ANA_CON7+0x80)[3] to 0x0
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(1),
++			   RK3308_ADC_MIC_BIAS_BUF_EN,
++			   RK3308_ADC_MIC_BIAS_BUF_DIS);
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(2),
++			   RK3308_ADC_MIC_BIAS_BUF_EN,
++			   RK3308_ADC_MIC_BIAS_BUF_DIS);
++
++	/*
++	 * Step 2. Configure ACODEC_ADC_ANA_CON8[4] to 0x0
++	 *
++	 * Note: Only the reg (ADC_ANA_CON8+0x0)[4] represent the enable
++	 * signal of current source for MICBIAS
++	 */
++	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(0),
++			   RK3308_ADC_MICBIAS_CURRENT_MSK,
++			   RK3308_ADC_MICBIAS_CURRENT_DIS);
++
++	rk3308->enable_micbias = false;
++
++	return 0;
++}
++
++static int rk3308_codec_adc_reinit_mics(struct rk3308_codec_priv *rk3308,
++					int type)
++{
++	int idx, grp;
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 1 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
++				   RK3308_ADC_CH1_ADC_WORK |
++				   RK3308_ADC_CH2_ADC_WORK,
++				   RK3308_ADC_CH1_ADC_INIT |
++				   RK3308_ADC_CH2_ADC_INIT);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 2 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
++				   RK3308_ADC_CH1_ALC_WORK |
++				   RK3308_ADC_CH2_ALC_WORK,
++				   RK3308_ADC_CH1_ALC_INIT |
++				   RK3308_ADC_CH2_ALC_INIT);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 3 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
++				   RK3308_ADC_CH1_MIC_WORK |
++				   RK3308_ADC_CH2_MIC_WORK,
++				   RK3308_ADC_CH1_MIC_INIT |
++				   RK3308_ADC_CH2_MIC_INIT);
++	}
++
++	usleep_range(200, 250);	/* estimated value */
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 1 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
++				   RK3308_ADC_CH1_ADC_WORK |
++				   RK3308_ADC_CH2_ADC_WORK,
++				   RK3308_ADC_CH1_ADC_WORK |
++				   RK3308_ADC_CH2_ADC_WORK);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 2 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
++				   RK3308_ADC_CH1_ALC_WORK |
++				   RK3308_ADC_CH2_ALC_WORK,
++				   RK3308_ADC_CH1_ALC_WORK |
++				   RK3308_ADC_CH2_ALC_WORK);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 3 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
++				   RK3308_ADC_CH1_MIC_WORK |
++				   RK3308_ADC_CH2_MIC_WORK,
++				   RK3308_ADC_CH1_MIC_WORK |
++				   RK3308_ADC_CH2_MIC_WORK);
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_adc_ana_enable(struct rk3308_codec_priv *rk3308,
++				       int type)
++{
++	unsigned int agc_func_en;
++	int idx, grp;
++
++	/*
++	 * 1. Set the ACODEC_ADC_ANA_CON7[7:6] and ACODEC_ADC_ANA_CON7[5:4],
++	 * to select the line-in or microphone as input of ADC
++	 *
++	 * Note1. Please ignore the step1 for enabling ADC3, ADC4, ADC5,
++	 * ADC6, ADC7, and ADC8
++	 */
++	if (rk3308->adc_grp0_using_linein) {
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0),
++				   RK3308_ADC_CH1_IN_SEL_MSK |
++				   RK3308_ADC_CH2_IN_SEL_MSK,
++				   RK3308_ADC_CH1_IN_LINEIN |
++				   RK3308_ADC_CH2_IN_LINEIN);
++
++		/* Keep other ADCs as MIC-IN */
++		for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++			/* The groups without line-in are >= 1 */
++			if (grp < 1 || grp > ADC_LR_GROUP_MAX - 1)
++				continue;
++
++			regmap_update_bits(rk3308->regmap,
++					   RK3308_ADC_ANA_CON07(grp),
++					   RK3308_ADC_CH1_IN_SEL_MSK |
++					   RK3308_ADC_CH2_IN_SEL_MSK,
++					   RK3308_ADC_CH1_IN_MIC |
++					   RK3308_ADC_CH2_IN_MIC);
++		}
++	} else {
++		for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++			if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++				continue;
++
++			regmap_update_bits(rk3308->regmap,
++					   RK3308_ADC_ANA_CON07(grp),
++					   RK3308_ADC_CH1_IN_SEL_MSK |
++					   RK3308_ADC_CH2_IN_SEL_MSK,
++					   RK3308_ADC_CH1_IN_MIC |
++					   RK3308_ADC_CH2_IN_MIC);
++		}
++	}
++
++	/*
++	 * 2. Set ACODEC_ADC_ANA_CON0[7] and [3] to 0x1, to end the mute station
++	 * of ADC, to enable the MIC module, to enable the reference voltage
++	 * buffer, and to end the initialization of MIC
++	 */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
++				   RK3308_ADC_CH1_MIC_UNMUTE |
++				   RK3308_ADC_CH2_MIC_UNMUTE,
++				   RK3308_ADC_CH1_MIC_UNMUTE |
++				   RK3308_ADC_CH2_MIC_UNMUTE);
++	}
++
++	/*
++	 * 3. Set ACODEC_ADC_ANA_CON6[0] to 0x1, to enable the current source
++	 * of audio
++	 */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(grp),
++				   RK3308_ADC_CURRENT_MSK,
++				   RK3308_ADC_CURRENT_EN);
++	}
++
++	/*
++	 * This is mainly used for BIST mode that wait ADCs are stable.
++	 *
++	 * By tested results, the type delay is >40us, but we need to leave
++	 * enough delay margin.
++	 */
++	usleep_range(400, 500);
++
++	/* vendor step 4*/
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
++				   RK3308_ADC_CH1_BUF_REF_EN |
++				   RK3308_ADC_CH2_BUF_REF_EN,
++				   RK3308_ADC_CH1_BUF_REF_EN |
++				   RK3308_ADC_CH2_BUF_REF_EN);
++	}
++
++	/* vendor step 5 */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
++				   RK3308_ADC_CH1_MIC_EN |
++				   RK3308_ADC_CH2_MIC_EN,
++				   RK3308_ADC_CH1_MIC_EN |
++				   RK3308_ADC_CH2_MIC_EN);
++	}
++
++	/* vendor step 6 */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
++				   RK3308_ADC_CH1_ALC_EN |
++				   RK3308_ADC_CH2_ALC_EN,
++				   RK3308_ADC_CH1_ALC_EN |
++				   RK3308_ADC_CH2_ALC_EN);
++	}
++
++	/* vendor step 7 */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
++				   RK3308_ADC_CH1_CLK_EN |
++				   RK3308_ADC_CH2_CLK_EN,
++				   RK3308_ADC_CH1_CLK_EN |
++				   RK3308_ADC_CH2_CLK_EN);
++	}
++
++	/* vendor step 8 */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
++				   RK3308_ADC_CH1_ADC_EN |
++				   RK3308_ADC_CH2_ADC_EN,
++				   RK3308_ADC_CH1_ADC_EN |
++				   RK3308_ADC_CH2_ADC_EN);
++	}
++
++	/* vendor step 9 */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
++				   RK3308_ADC_CH1_ADC_WORK |
++				   RK3308_ADC_CH2_ADC_WORK,
++				   RK3308_ADC_CH1_ADC_WORK |
++				   RK3308_ADC_CH2_ADC_WORK);
++	}
++
++	/* vendor step 10 */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
++				   RK3308_ADC_CH1_ALC_WORK |
++				   RK3308_ADC_CH2_ALC_WORK,
++				   RK3308_ADC_CH1_ALC_WORK |
++				   RK3308_ADC_CH2_ALC_WORK);
++	}
++
++	/* vendor step 11 */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
++				   RK3308_ADC_CH1_MIC_WORK |
++				   RK3308_ADC_CH2_MIC_WORK,
++				   RK3308_ADC_CH1_MIC_WORK |
++				   RK3308_ADC_CH2_MIC_WORK);
++	}
++
++	/* vendor step 12 */
++
++	/* vendor step 13 */
++
++	/* vendor step 14 */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp),
++			    &agc_func_en);
++		if (rk3308->adc_zerocross ||
++		    agc_func_en & RK3308_AGC_FUNC_SEL_EN) {
++			regmap_update_bits(rk3308->regmap,
++					   RK3308_ADC_ANA_CON02(grp),
++					   RK3308_ADC_CH1_ZEROCROSS_DET_EN,
++					   RK3308_ADC_CH1_ZEROCROSS_DET_EN);
++		}
++		regmap_read(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp),
++			    &agc_func_en);
++		if (rk3308->adc_zerocross ||
++		    agc_func_en & RK3308_AGC_FUNC_SEL_EN) {
++			regmap_update_bits(rk3308->regmap,
++					   RK3308_ADC_ANA_CON02(grp),
++					   RK3308_ADC_CH2_ZEROCROSS_DET_EN,
++					   RK3308_ADC_CH2_ZEROCROSS_DET_EN);
++		}
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		rk3308->adc_grps_endisable[grp] = true;
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_adc_ana_disable(struct rk3308_codec_priv *rk3308,
++					int type)
++{
++	int idx, grp;
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 1 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
++				   RK3308_ADC_CH1_ZEROCROSS_DET_EN |
++				   RK3308_ADC_CH2_ZEROCROSS_DET_EN,
++				   RK3308_ADC_CH1_ZEROCROSS_DET_DIS |
++				   RK3308_ADC_CH2_ZEROCROSS_DET_DIS);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 2 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
++				   RK3308_ADC_CH1_ADC_EN |
++				   RK3308_ADC_CH2_ADC_EN,
++				   RK3308_ADC_CH1_ADC_DIS |
++				   RK3308_ADC_CH2_ADC_DIS);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 3 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
++				   RK3308_ADC_CH1_CLK_EN |
++				   RK3308_ADC_CH2_CLK_EN,
++				   RK3308_ADC_CH1_CLK_DIS |
++				   RK3308_ADC_CH2_CLK_DIS);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 4 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
++				   RK3308_ADC_CH1_ALC_EN |
++				   RK3308_ADC_CH2_ALC_EN,
++				   RK3308_ADC_CH1_ALC_DIS |
++				   RK3308_ADC_CH2_ALC_DIS);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 5 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
++				   RK3308_ADC_CH1_MIC_EN |
++				   RK3308_ADC_CH2_MIC_EN,
++				   RK3308_ADC_CH1_MIC_DIS |
++				   RK3308_ADC_CH2_MIC_DIS);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 6 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
++				   RK3308_ADC_CH1_BUF_REF_EN |
++				   RK3308_ADC_CH2_BUF_REF_EN,
++				   RK3308_ADC_CH1_BUF_REF_DIS |
++				   RK3308_ADC_CH2_BUF_REF_DIS);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 7 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(grp),
++				   RK3308_ADC_CURRENT_MSK,
++				   RK3308_ADC_CURRENT_DIS);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 8 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
++				   RK3308_ADC_CH1_ADC_WORK |
++				   RK3308_ADC_CH2_ADC_WORK,
++				   RK3308_ADC_CH1_ADC_INIT |
++				   RK3308_ADC_CH2_ADC_INIT);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 9 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
++				   RK3308_ADC_CH1_ALC_WORK |
++				   RK3308_ADC_CH2_ALC_WORK,
++				   RK3308_ADC_CH1_ALC_INIT |
++				   RK3308_ADC_CH2_ALC_INIT);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		/* vendor step 10 */
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
++				   RK3308_ADC_CH1_MIC_WORK |
++				   RK3308_ADC_CH2_MIC_WORK,
++				   RK3308_ADC_CH1_MIC_INIT |
++				   RK3308_ADC_CH2_MIC_INIT);
++	}
++
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		rk3308->adc_grps_endisable[grp] = false;
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_open_capture(struct rk3308_codec_priv *rk3308)
++{
++	int idx, grp = 0;
++	int type = ADC_TYPE_NORMAL;
++
++	rk3308_codec_adc_ana_enable(rk3308, type);
++	rk3308_codec_adc_reinit_mics(rk3308, type);
++
++	if (rk3308->adc_grp0_using_linein) {
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(0),
++				   RK3308_ADC_L_CH_BIST_MSK,
++				   RK3308_ADC_L_CH_NORMAL_RIGHT);
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(0),
++				   RK3308_ADC_R_CH_BIST_MSK,
++				   RK3308_ADC_R_CH_NORMAL_LEFT);
++	} else {
++		for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++			if (handle_loopback(rk3308) &&
++			    idx == rk3308->loopback_grp &&
++			    grp == ADC_GRP_SKIP_MAGIC) {
++				/*
++				 * Switch to dummy BIST mode (BIST keep reset
++				 * now) to keep the zero input data in I2S bus.
++				 *
++				 * It may cause the glitch if we hold the ADC
++				 * digtital i2s module in codec.
++				 *
++				 * Then, the grp which is set from loopback_grp.
++				 */
++				regmap_update_bits(rk3308->regmap,
++						   RK3308_ADC_DIG_CON03(rk3308->loopback_grp),
++						   RK3308_ADC_L_CH_BIST_MSK,
++						   RK3308_ADC_L_CH_BIST_SINE);
++				regmap_update_bits(rk3308->regmap,
++						   RK3308_ADC_DIG_CON03(rk3308->loopback_grp),
++						   RK3308_ADC_R_CH_BIST_MSK,
++						   RK3308_ADC_R_CH_BIST_SINE);
++			} else {
++				if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++					continue;
++
++				regmap_update_bits(rk3308->regmap,
++						   RK3308_ADC_DIG_CON03(grp),
++						   RK3308_ADC_L_CH_BIST_MSK,
++						   RK3308_ADC_L_CH_NORMAL_LEFT);
++				regmap_update_bits(rk3308->regmap,
++						   RK3308_ADC_DIG_CON03(grp),
++						   RK3308_ADC_R_CH_BIST_MSK,
++						   RK3308_ADC_R_CH_NORMAL_RIGHT);
++			}
++		}
++	}
++
++	return 0;
++}
++
++static void rk3308_codec_adc_mclk_disable(struct rk3308_codec_priv *rk3308)
++{
++	regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
++			   RK3308_ADC_MCLK_MSK,
++			   RK3308_ADC_MCLK_DIS);
++}
++
++static void rk3308_codec_adc_mclk_enable(struct rk3308_codec_priv *rk3308)
++{
++	regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
++			   RK3308_ADC_MCLK_MSK,
++			   RK3308_ADC_MCLK_EN);
++	udelay(20);
++}
++
++static void rk3308_codec_dac_mclk_disable(struct rk3308_codec_priv *rk3308)
++{
++	regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
++			   RK3308_DAC_MCLK_MSK,
++			   RK3308_DAC_MCLK_DIS);
++}
++
++static void rk3308_codec_dac_mclk_enable(struct rk3308_codec_priv *rk3308)
++{
++	regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
++			   RK3308_DAC_MCLK_MSK,
++			   RK3308_DAC_MCLK_EN);
++	udelay(20);
++}
++
++static int rk3308_codec_open_dbg_capture(struct rk3308_codec_priv *rk3308)
++{
++	rk3308_codec_adc_ana_enable(rk3308, ADC_TYPE_DBG);
++
++	return 0;
++}
++
++static int rk3308_codec_close_dbg_capture(struct rk3308_codec_priv *rk3308)
++{
++	rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_DBG);
++
++	return 0;
++}
++
++static int rk3308_codec_close_all_capture(struct rk3308_codec_priv *rk3308)
++{
++	rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_ALL);
++
++	return 0;
++}
++
++static int rk3308_codec_close_capture(struct rk3308_codec_priv *rk3308)
++{
++	rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_NORMAL);
++
++	return 0;
++}
++
++static int rk3308_codec_open_playback(struct rk3308_codec_priv *rk3308)
++{
++	rk3308_codec_dac_enable(rk3308);
++
++	return 0;
++}
++
++static int rk3308_codec_close_playback(struct rk3308_codec_priv *rk3308)
++{
++	rk3308_codec_dac_disable(rk3308);
++
++	return 0;
++}
++
++static int rk3308_codec_llp_down(struct rk3308_codec_priv *rk3308)
++{
++	rk3308_codec_adc_mclk_disable(rk3308);
++	rk3308_codec_dac_mclk_disable(rk3308);
++
++	return 0;
++}
++
++static int rk3308_codec_llp_up(struct rk3308_codec_priv *rk3308)
++{
++	rk3308_codec_adc_mclk_enable(rk3308);
++	rk3308_codec_dac_mclk_enable(rk3308);
++
++	return 0;
++}
++
++static int rk3308_codec_dlp_down(struct rk3308_codec_priv *rk3308)
++{
++	rk3308_codec_micbias_disable(rk3308);
++	rk3308_codec_power_off(rk3308);
++
++	return 0;
++}
++
++static int rk3308_codec_dlp_up(struct rk3308_codec_priv *rk3308)
++{
++	rk3308_codec_power_on(rk3308);
++	rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt);
++
++	return 0;
++}
++
++/* Just used for debug and trace power state */
++static void rk3308_codec_set_pm_state(struct rk3308_codec_priv *rk3308,
++				      int pm_state)
++{
++	int ret;
++
++	switch (pm_state) {
++	case PM_LLP_DOWN:
++		rk3308_codec_llp_down(rk3308);
++		break;
++	case PM_LLP_UP:
++		rk3308_codec_llp_up(rk3308);
++		break;
++	case PM_DLP_DOWN:
++		rk3308_codec_dlp_down(rk3308);
++		break;
++	case PM_DLP_UP:
++		rk3308_codec_dlp_up(rk3308);
++		break;
++	case PM_DLP_DOWN2:
++		clk_disable_unprepare(rk3308->mclk_rx);
++		clk_disable_unprepare(rk3308->mclk_tx);
++		clk_disable_unprepare(rk3308->pclk);
++		break;
++	case PM_DLP_UP2:
++		ret = clk_prepare_enable(rk3308->pclk);
++		if (ret < 0) {
++			dev_err(rk3308->plat_dev,
++				"Failed to enable acodec pclk: %d\n", ret);
++			goto err;
++		}
++
++		ret = clk_prepare_enable(rk3308->mclk_rx);
++		if (ret < 0) {
++			dev_err(rk3308->plat_dev,
++				"Failed to enable i2s mclk_rx: %d\n", ret);
++			goto err;
++		}
++
++		ret = clk_prepare_enable(rk3308->mclk_tx);
++		if (ret < 0) {
++			dev_err(rk3308->plat_dev,
++				"Failed to enable i2s mclk_tx: %d\n", ret);
++			goto err;
++		}
++		break;
++	default:
++		dev_err(rk3308->plat_dev, "Invalid pm_state: %d\n", pm_state);
++		goto err;
++	}
++
++	rk3308->pm_state = pm_state;
++
++err:
++	return;
++}
++
++static void rk3308_codec_update_adcs_status(struct rk3308_codec_priv *rk3308,
++					    int state)
++{
++	int idx, grp;
++
++	/* Update skip_grps flags if the ADCs need to be enabled always. */
++	if (state == PATH_BUSY) {
++		for (idx = 0; idx < rk3308->used_adc_grps; idx++) {
++			u32 mapped_grp = to_mapped_grp(rk3308, idx);
++
++			for (grp = 0; grp < rk3308->en_always_grps_num; grp++) {
++				u32 en_always_grp = rk3308->en_always_grps[grp];
++
++				if (mapped_grp == en_always_grp)
++					rk3308->skip_grps[en_always_grp] = 1;
++			}
++		}
++	}
++}
++
++static int rk3308_hw_params(struct snd_pcm_substream *substream,
++			    struct snd_pcm_hw_params *params,
++			    struct snd_soc_dai *dai)
++{
++	struct snd_soc_codec *codec = dai->codec;
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_pcm_str *playback_str =
++			&substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
++	int type = ADC_TYPE_LOOPBACK;
++	int idx, grp;
++	int ret;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		/* DAC only supports 2 channels */
++		rk3308_codec_dac_mclk_enable(rk3308);
++		rk3308_codec_open_playback(rk3308);
++		rk3308_codec_dac_dig_config(rk3308, params);
++		rk3308_codec_set_dac_path_state(rk3308, PATH_BUSY);
++	} else {
++		if (rk3308->micbias_num &&
++		    !rk3308->enable_micbias)
++			rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt);
++
++		rk3308_codec_adc_mclk_enable(rk3308);
++		ret = rk3308_codec_update_adc_grps(rk3308, params);
++		if (ret < 0)
++			return ret;
++
++		if (handle_loopback(rk3308)) {
++			if (rk3308->micbias_num &&
++			    (params_channels(params) == 2) &&
++			    to_mapped_grp(rk3308, 0) == rk3308->loopback_grp)
++				rk3308_codec_micbias_disable(rk3308);
++
++			/* Check the DACs are opened */
++			if (playback_str->substream_opened) {
++				rk3308->loopback_dacs_enabled = true;
++				for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++					if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++						continue;
++
++					regmap_update_bits(rk3308->regmap,
++							   RK3308_ADC_DIG_CON03(grp),
++							   RK3308_ADC_L_CH_BIST_MSK,
++							   RK3308_ADC_L_CH_NORMAL_LEFT);
++					regmap_update_bits(rk3308->regmap,
++							   RK3308_ADC_DIG_CON03(grp),
++							   RK3308_ADC_R_CH_BIST_MSK,
++							   RK3308_ADC_R_CH_NORMAL_RIGHT);
++				}
++			} else {
++				rk3308->loopback_dacs_enabled = false;
++				for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++					if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++						continue;
++
++					regmap_update_bits(rk3308->regmap,
++							   RK3308_ADC_DIG_CON03(grp),
++							   RK3308_ADC_L_CH_BIST_MSK,
++							   RK3308_ADC_L_CH_BIST_SINE);
++					regmap_update_bits(rk3308->regmap,
++							   RK3308_ADC_DIG_CON03(grp),
++							   RK3308_ADC_R_CH_BIST_MSK,
++							   RK3308_ADC_R_CH_BIST_SINE);
++				}
++			}
++		}
++
++		rk3308_codec_open_capture(rk3308);
++		rk3308_codec_adc_dig_config(rk3308, params);
++		rk3308_codec_update_adcs_status(rk3308, PATH_BUSY);
++	}
++
++	return 0;
++}
++
++static int rk3308_pcm_trigger(struct snd_pcm_substream *substream,
++			      int cmd, struct snd_soc_dai *dai)
++{
++	struct snd_soc_codec *codec = dai->codec;
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	int type = ADC_TYPE_LOOPBACK;
++	int idx, grp;
++
++	if (handle_loopback(rk3308) &&
++	    rk3308->dac_output == DAC_LINEOUT &&
++	    substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		if (cmd == SNDRV_PCM_TRIGGER_START) {
++			struct snd_pcm_str *capture_str =
++				&substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
++
++			if (capture_str->substream_opened)
++				queue_delayed_work(system_power_efficient_wq,
++						   &rk3308->loopback_work,
++						   msecs_to_jiffies(rk3308->delay_loopback_handle_ms));
++		} else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
++			/*
++			 * Switch to dummy bist mode to kick the glitch during disable
++			 * ADCs and keep zero input data
++			 */
++			for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++				if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++					continue;
++
++				regmap_update_bits(rk3308->regmap,
++						   RK3308_ADC_DIG_CON03(grp),
++						   RK3308_ADC_L_CH_BIST_MSK,
++						   RK3308_ADC_L_CH_BIST_SINE);
++				regmap_update_bits(rk3308->regmap,
++						   RK3308_ADC_DIG_CON03(grp),
++						   RK3308_ADC_R_CH_BIST_MSK,
++						   RK3308_ADC_R_CH_BIST_SINE);
++			}
++			rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_LOOPBACK);
++		}
++	}
++
++	return 0;
++}
++
++static void rk3308_pcm_shutdown(struct snd_pcm_substream *substream,
++				struct snd_soc_dai *dai)
++{
++	struct snd_soc_codec *codec = dai->codec;
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		rk3308_codec_close_playback(rk3308);
++		rk3308_codec_dac_mclk_disable(rk3308);
++		regcache_cache_only(rk3308->regmap, false);
++		regcache_sync(rk3308->regmap);
++		rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE);
++	} else {
++		rk3308_codec_close_capture(rk3308);
++		if (!has_en_always_grps(rk3308)) {
++			rk3308_codec_adc_mclk_disable(rk3308);
++			rk3308_codec_update_adcs_status(rk3308, PATH_IDLE);
++			if (rk3308->micbias_num &&
++			    rk3308->enable_micbias)
++				rk3308_codec_micbias_disable(rk3308);
++		}
++
++		regcache_cache_only(rk3308->regmap, false);
++		regcache_sync(rk3308->regmap);
++	}
++}
++
++static struct snd_soc_dai_ops rk3308_dai_ops = {
++	.hw_params = rk3308_hw_params,
++	.set_fmt = rk3308_set_dai_fmt,
++	.mute_stream = rk3308_mute_stream,
++	.trigger = rk3308_pcm_trigger,
++	.shutdown = rk3308_pcm_shutdown,
++};
++
++static struct snd_soc_dai_driver rk3308_dai[] = {
++	{
++		.name = "rk3308-hifi",
++		.id = RK3308_HIFI,
++		.playback = {
++			.stream_name = "HiFi Playback",
++			.channels_min = 2,
++			.channels_max = 2,
++			.rates = SNDRV_PCM_RATE_8000_192000,
++			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++				    SNDRV_PCM_FMTBIT_S20_3LE |
++				    SNDRV_PCM_FMTBIT_S24_LE |
++				    SNDRV_PCM_FMTBIT_S32_LE),
++		},
++		.capture = {
++			.stream_name = "HiFi Capture",
++			.channels_min = 1,
++			.channels_max = 8,
++			.rates = SNDRV_PCM_RATE_8000_192000,
++			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++				    SNDRV_PCM_FMTBIT_S20_3LE |
++				    SNDRV_PCM_FMTBIT_S24_LE |
++				    SNDRV_PCM_FMTBIT_S32_LE),
++		},
++		.ops = &rk3308_dai_ops,
++	},
++};
++
++static int rk3308_suspend(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	if (rk3308->no_deep_low_power)
++		goto out;
++
++	rk3308_codec_dlp_down(rk3308);
++	clk_disable_unprepare(rk3308->mclk_rx);
++	clk_disable_unprepare(rk3308->mclk_tx);
++	clk_disable_unprepare(rk3308->pclk);
++
++out:
++	rk3308_set_bias_level(codec, SND_SOC_BIAS_OFF);
++	return 0;
++}
++
++static int rk3308_resume(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	int ret = 0;
++
++	if (rk3308->no_deep_low_power)
++		goto out;
++
++	ret = clk_prepare_enable(rk3308->pclk);
++	if (ret < 0) {
++		dev_err(rk3308->plat_dev,
++			"Failed to enable acodec pclk: %d\n", ret);
++		goto out;
++	}
++
++	ret = clk_prepare_enable(rk3308->mclk_rx);
++	if (ret < 0) {
++		dev_err(rk3308->plat_dev,
++			"Failed to enable i2s mclk_rx: %d\n", ret);
++		goto out;
++	}
++
++	ret = clk_prepare_enable(rk3308->mclk_tx);
++	if (ret < 0) {
++		dev_err(rk3308->plat_dev,
++			"Failed to enable i2s mclk_tx: %d\n", ret);
++		goto out;
++	}
++
++	rk3308_codec_dlp_up(rk3308);
++out:
++	rk3308_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++	return ret;
++}
++
++static int rk3308_codec_default_gains(struct rk3308_codec_priv *rk3308)
++{
++	int grp;
++
++	/* Prepare ADC gains */
++	/* vendor step 12, set MIC PGA default gains */
++	for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) {
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON01(grp),
++				   RK3308_ADC_CH1_MIC_GAIN_MSK |
++				   RK3308_ADC_CH2_MIC_GAIN_MSK,
++				   RK3308_ADC_CH1_MIC_GAIN_0DB |
++				   RK3308_ADC_CH2_MIC_GAIN_0DB);
++	}
++
++	/* vendor step 13, set ALC default gains */
++	for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) {
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON03(grp),
++				   RK3308_ADC_CH1_ALC_GAIN_MSK,
++				   RK3308_ADC_CH1_ALC_GAIN_0DB);
++		regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON04(grp),
++				   RK3308_ADC_CH2_ALC_GAIN_MSK,
++				   RK3308_ADC_CH2_ALC_GAIN_0DB);
++	}
++
++	/* Prepare DAC gains */
++	/* Step 15, set HPMIX default gains */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
++			   RK3308_DAC_L_HPMIX_GAIN_MSK |
++			   RK3308_DAC_R_HPMIX_GAIN_MSK,
++			   RK3308_DAC_L_HPMIX_GAIN_NDB_6 |
++			   RK3308_DAC_R_HPMIX_GAIN_NDB_6);
++
++	/* Step 18, set HPOUT default gains */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05,
++			   RK3308_DAC_L_HPOUT_GAIN_MSK,
++			   RK3308_DAC_L_HPOUT_GAIN_NDB_39);
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06,
++			   RK3308_DAC_R_HPOUT_GAIN_MSK,
++			   RK3308_DAC_R_HPOUT_GAIN_NDB_39);
++
++	/* Using the same gain to HPOUT LR channels */
++	rk3308->hpout_l_dgain = RK3308_DAC_L_HPOUT_GAIN_NDB_39;
++
++	/* Step 19, set LINEOUT default gains */
++	regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
++			   RK3308_DAC_L_LINEOUT_GAIN_MSK |
++			   RK3308_DAC_R_LINEOUT_GAIN_MSK,
++			   RK3308_DAC_L_LINEOUT_GAIN_NDB_6 |
++			   RK3308_DAC_R_LINEOUT_GAIN_NDB_6);
++
++	return 0;
++}
++
++static int rk3308_codec_setup_en_always_adcs(struct rk3308_codec_priv *rk3308,
++					     struct device_node *np)
++{
++	int num, ret;
++
++	num = of_count_phandle_with_args(np, "rockchip,en-always-grps", NULL);
++	if (num < 0) {
++		if (num == -ENOENT) {
++			/*
++			 * If there is note use 'rockchip,en-always-grps'
++			 * property, return 0 is also right.
++			 */
++			ret = 0;
++		} else {
++			dev_err(rk3308->plat_dev,
++				"Failed to read 'rockchip,adc-grps-route' num: %d\n",
++				num);
++			ret = num;
++		}
++
++		rk3308->en_always_grps_num = 0;
++		return ret;
++	}
++
++	rk3308->en_always_grps_num = num;
++
++	ret = of_property_read_u32_array(np, "rockchip,en-always-grps",
++					 rk3308->en_always_grps, num);
++	if (ret < 0) {
++		dev_err(rk3308->plat_dev,
++			"Failed to read 'rockchip,en-always-grps': %d\n",
++			ret);
++		return ret;
++	}
++
++	/* Clear all of skip_grps flags. */
++	for (num = 0; num < ADC_LR_GROUP_MAX; num++)
++		rk3308->skip_grps[num] = 0;
++
++	/* The loopback grp should not be enabled always. */
++	for (num = 0; num < rk3308->en_always_grps_num; num++) {
++		if (rk3308->en_always_grps[num] == rk3308->loopback_grp) {
++			dev_err(rk3308->plat_dev,
++				"loopback_grp: %d should not be enabled always!\n",
++				rk3308->loopback_grp);
++			ret = -EINVAL;
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_dapm_mic_gains(struct rk3308_codec_priv *rk3308)
++{
++	int ret;
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		ret = snd_soc_add_codec_controls(rk3308->codec,
++						 mic_gains_b,
++						 ARRAY_SIZE(mic_gains_b));
++		if (ret) {
++			dev_err(rk3308->plat_dev,
++				"%s: add mic_gains_b failed: %d\n",
++				__func__, ret);
++			return ret;
++		}
++	} else {
++		ret = snd_soc_add_codec_controls(rk3308->codec,
++						 mic_gains_a,
++						 ARRAY_SIZE(mic_gains_a));
++		if (ret) {
++			dev_err(rk3308->plat_dev,
++				"%s: add mic_gains_a failed: %d\n",
++				__func__, ret);
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static int rk3308_codec_check_micbias(struct rk3308_codec_priv *rk3308,
++				      struct device_node *np)
++{
++	struct device *dev = (struct device *)rk3308->plat_dev;
++	int num = 0, ret;
++
++	/* Check internal micbias */
++	rk3308->micbias1 =
++		of_property_read_bool(np, "rockchip,micbias1");
++	if (rk3308->micbias1)
++		num++;
++
++	rk3308->micbias2 =
++		of_property_read_bool(np, "rockchip,micbias2");
++	if (rk3308->micbias2)
++		num++;
++
++	rk3308->micbias_volt = RK3308_ADC_MICBIAS_VOLT_0_85; /* by default */
++	rk3308->micbias_num = num;
++
++	/* Check external micbias */
++	rk3308->ext_micbias = EXT_MICBIAS_NONE;
++
++	rk3308->micbias_en_gpio = devm_gpiod_get_optional(dev,
++							  "micbias-en",
++							  GPIOD_IN);
++	if (!rk3308->micbias_en_gpio) {
++		dev_info(dev, "Don't need micbias-en gpio\n");
++	} else if (IS_ERR(rk3308->micbias_en_gpio)) {
++		ret = PTR_ERR(rk3308->micbias_en_gpio);
++		dev_err(dev, "Unable to claim gpio micbias-en\n");
++		return ret;
++	} else if (gpiod_get_value(rk3308->micbias_en_gpio)) {
++		rk3308->ext_micbias = EXT_MICBIAS_FUNC1;
++	}
++
++	rk3308->vcc_micbias = devm_regulator_get_optional(dev,
++							  "vmicbias");
++	if (IS_ERR(rk3308->vcc_micbias)) {
++		if (PTR_ERR(rk3308->vcc_micbias) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++		dev_info(dev, "no vmicbias regulator found\n");
++	} else {
++		ret = regulator_enable(rk3308->vcc_micbias);
++		if (ret) {
++			dev_err(dev, "Can't enable vmicbias: %d\n", ret);
++			return ret;
++		}
++		rk3308->ext_micbias = EXT_MICBIAS_FUNC2;
++	}
++
++	dev_info(dev, "Check ext_micbias: %d\n", rk3308->ext_micbias);
++
++	return 0;
++}
++
++static int rk3308_codec_dapm_controls_prepare(struct rk3308_codec_priv *rk3308)
++{
++	int grp;
++
++	for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) {
++		rk3308->hpf_cutoff[grp] = 0;
++		rk3308->agc_l[grp] = 0;
++		rk3308->agc_r[grp] = 0;
++		rk3308->agc_asr_l[grp] = AGC_ASR_96KHZ;
++		rk3308->agc_asr_r[grp] = AGC_ASR_96KHZ;
++	}
++
++	rk3308_codec_dapm_mic_gains(rk3308);
++
++	return 0;
++}
++
++static int rk3308_codec_prepare(struct rk3308_codec_priv *rk3308)
++{
++	/* Clear registers for ADC and DAC */
++	rk3308_codec_close_playback(rk3308);
++	rk3308_codec_close_all_capture(rk3308);
++	rk3308_codec_default_gains(rk3308);
++	rk3308_codec_llp_down(rk3308);
++	rk3308_codec_dapm_controls_prepare(rk3308);
++
++	return 0;
++}
++
++static int rk3308_probe(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	int ext_micbias;
++
++	rk3308->codec = codec;
++	rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE);
++
++	rk3308_codec_reset(codec);
++	rk3308_codec_power_on(rk3308);
++
++	/* From vendor recommend, disable micbias at first. */
++	ext_micbias = rk3308->ext_micbias;
++	rk3308->ext_micbias = EXT_MICBIAS_NONE;
++	rk3308_codec_micbias_disable(rk3308);
++	rk3308->ext_micbias = ext_micbias;
++
++	rk3308_codec_prepare(rk3308);
++	if (!rk3308->no_hp_det)
++		rk3308_codec_headset_detect_enable(rk3308);
++
++	regcache_cache_only(rk3308->regmap, false);
++	regcache_sync(rk3308->regmap);
++
++	return 0;
++}
+ 
+-	/* 5. Wait until the voltage of VCM keeps stable at the AGND */
+-	usleep_range(200, 300);	/* estimated value */
++static int rk3308_remove(struct snd_soc_codec *codec)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++
++	rk3308_headphone_ctl(rk3308, 0);
++	rk3308_speaker_ctl(rk3308, 0);
++	if (!rk3308->no_hp_det)
++		rk3308_codec_headset_detect_disable(rk3308);
++	rk3308_codec_micbias_disable(rk3308);
++	rk3308_codec_power_off(rk3308);
+ 
+-	/* 6. Power off the analog power supply */
+-	/* 7. Power off the digital power supply */
++	rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE);
+ 
+-	/* Do something via hardware */
++	regcache_cache_only(rk3308->regmap, false);
++	regcache_sync(rk3308->regmap);
+ 
+ 	return 0;
+ }
+ 
+-static int check_micbias(int micbias)
++static struct snd_soc_codec_driver soc_codec_dev_rk3308 = {
++	.probe = rk3308_probe,
++	.remove = rk3308_remove,
++	.suspend = rk3308_suspend,
++	.resume = rk3308_resume,
++	.set_bias_level = rk3308_set_bias_level,
++	.controls = rk3308_codec_dapm_controls,
++	.num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls),
++};
++
++static const struct reg_default rk3308_codec_reg_defaults[] = {
++	{ RK3308_GLB_CON, 0x07 },
++};
++
++static bool rk3308_codec_write_read_reg(struct device *dev, unsigned int reg)
+ {
+-	switch (micbias) {
+-	case RK3308_ADC_MICBIAS_VOLT_0_85:
+-	case RK3308_ADC_MICBIAS_VOLT_0_8:
+-	case RK3308_ADC_MICBIAS_VOLT_0_75:
+-	case RK3308_ADC_MICBIAS_VOLT_0_7:
+-	case RK3308_ADC_MICBIAS_VOLT_0_65:
+-	case RK3308_ADC_MICBIAS_VOLT_0_6:
+-	case RK3308_ADC_MICBIAS_VOLT_0_55:
+-	case RK3308_ADC_MICBIAS_VOLT_0_5:
+-		return 0;
+-	}
++	/* All registers can be read / write */
++	return true;
++}
+ 
+-	return -EINVAL;
++static bool rk3308_codec_volatile_reg(struct device *dev, unsigned int reg)
++{
++	return true;
+ }
+ 
+-static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308,
+-				       int micbias)
++static void rk3308_codec_hpdetect_work(struct work_struct *work)
+ {
+-	int ch = rk3308->adc_ch;
+-	int ret;
++	struct rk3308_codec_priv *rk3308 =
++		container_of(work, struct rk3308_codec_priv, hpdet_work.work);
++	unsigned int val;
++	int need_poll = 0, need_irq = 0;
++	int need_report = 0, report_type = 0;
++	int dac_output = DAC_LINEOUT;
++
++	if (rk3308->codec_ver == ACODEC_VERSION_B) {
++		/* Check headphone plugged/unplugged directly. */
++		regmap_read(rk3308->detect_grf,
++			    DETECT_GRF_ACODEC_HPDET_STATUS, &val);
++		regmap_write(rk3308->detect_grf,
++			     DETECT_GRF_ACODEC_HPDET_STATUS_CLR, val);
++
++		if (rk3308->hp_jack_reversed) {
++			switch (val) {
++			case 0x0:
++			case 0x2:
++				dac_output = DAC_HPOUT;
++				report_type = SND_JACK_HEADPHONE;
++				break;
++			default:
++				break;
++			}
++		} else {
++			switch (val) {
++			case 0x1:
++				dac_output = DAC_HPOUT;
++				report_type = SND_JACK_HEADPHONE;
++				break;
++			default:
++				/* Includes val == 2 or others. */
++				break;
++			}
++		}
+ 
+-	if (ch != 1 && ch != 2) {
+-		dev_err(rk3308->plat_dev,
+-			 "%s: currnet ch: %d, only ch1/2 control MICBIAS1/2\n",
+-			 __func__, ch);
+-		return -EINVAL;
+-	}
++		rk3308_codec_dac_switch(rk3308, dac_output);
++		if (rk3308->hpdet_jack)
++			snd_soc_jack_report(rk3308->hpdet_jack,
++					    report_type,
++					    SND_JACK_HEADPHONE);
+ 
+-	/* 1. Power up the ACODEC and keep the AVDDH stable */
++		enable_irq(rk3308->irq);
+ 
+-	/* 2. Configure ACODEC_ADC_ANA_CON7[2:0] to the certain value */
+-	ret = check_micbias(micbias);
+-	if (ret < 0) {
+-		dev_err(rk3308->plat_dev, "This is an invalid micbias: %d\n",
+-			micbias);
+-		return ret;
++		return;
+ 	}
+ 
+-	/*
+-	 * Note: Only the reg (ADC_ANA_CON7+0x0)[2:0] represent the level range
+-	 * control signal of MICBIAS voltage
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0),
+-			   RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK,
+-			   micbias);
++	/* Check headphone unplugged via poll. */
++	regmap_read(rk3308->regmap, RK3308_DAC_DIG_CON14, &val);
+ 
+-	/* 3. Wait until the VCMH keep stable */
+-	usleep_range(200, 300);	/* estimated value */
++	if (rk3308->hp_jack_reversed) {
++		if (!val) {
++			rk3308->hp_plugged = true;
++			report_type = SND_JACK_HEADPHONE;
+ 
+-	/* 4. Configure ACODEC_ADC_ANA_CON8[4] to 0x1 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(ch),
+-			   RK3308_ADC_MICBIAS_CURRENT_MSK,
+-			   RK3308_ADC_MICBIAS_CURRENT_EN);
++			need_report = 1;
++			need_irq = 1;
++		} else {
++			if (rk3308->hp_plugged) {
++				rk3308->hp_plugged = false;
++				need_report = 1;
++			}
++			need_poll = 1;
++		}
++	} else {
++		if (!val) {
++			rk3308->hp_plugged = false;
+ 
+-	/*
+-	 * 5. Configure the (ADC_ANA_CON7+0x40)[3] or (ADC_ANA_CON7+0x80)[3]
+-	 * to 0x1.
+-	 * (ADC_ANA_CON7+0x40)[3] used to control the MICBIAS1, and
+-	 * (ADC_ANA_CON7+0x80)[3] used to control the MICBIAS2
+-	 */
++			need_report = 1;
++			need_irq = 1;
++		} else {
++			if (!rk3308->hp_plugged) {
++				rk3308->hp_plugged = true;
++				report_type = SND_JACK_HEADPHONE;
++				need_report = 1;
++			}
++			need_poll = 1;
++		}
++	}
+ 
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
+-			   RK3308_ADC_MIC_BIAS_BUF_EN,
+-			   RK3308_ADC_MIC_BIAS_BUF_EN);
++	if (need_poll)
++		queue_delayed_work(system_power_efficient_wq,
++				   &rk3308->hpdet_work,
++				   msecs_to_jiffies(HPDET_POLL_MS));
+ 
+-	return 0;
+-}
++	if (need_report) {
++		if (report_type)
++			dac_output = DAC_HPOUT;
+ 
+-static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308)
+-{
+-	int ch = rk3308->adc_ch;
++		rk3308_codec_dac_switch(rk3308, dac_output);
+ 
+-	if (ch != 1 && ch != 2) {
+-		dev_err(rk3308->plat_dev,
+-			 "%s: currnet ch: %d, only ch1/2 control MICBIAS1/2\n",
+-			 __func__, ch);
+-		return -EINVAL;
++		if (rk3308->hpdet_jack)
++			snd_soc_jack_report(rk3308->hpdet_jack,
++					    report_type,
++					    SND_JACK_HEADPHONE);
+ 	}
+ 
+-	/* 1. Enable the MICBIAS and keep the Audio Codec stable */
+-	/* Do nothing */
+-
+-	/*
+-	 * 2. Configure the (ADC_ANA_CON7+0x40)[3] or
+-	 * (ADC_ANA_CON7+0x80)[3] to 0x0
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
+-			   RK3308_ADC_MIC_BIAS_BUF_EN,
+-			   RK3308_ADC_MIC_BIAS_BUF_DIS);
+-
+-	/* 3. Configure ACODEC_ADC_ANA_CON8[4] to 0x0 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(ch),
+-			   RK3308_ADC_MICBIAS_CURRENT_MSK,
+-			   RK3308_ADC_MICBIAS_CURRENT_DIS);
++	if (need_irq)
++		enable_irq(rk3308->irq);
++}
+ 
+-	return 0;
++static void rk3308_codec_loopback_work(struct work_struct *work)
++{
++	struct rk3308_codec_priv *rk3308 =
++		container_of(work, struct rk3308_codec_priv, loopback_work.work);
++	int type = ADC_TYPE_LOOPBACK;
++	int idx, grp;
++
++	/* Prepare loopback ADCs */
++	rk3308_codec_adc_ana_enable(rk3308, type);
++
++	/* Waiting ADCs are stable */
++	msleep(ADC_STABLE_MS);
++
++	/* Recover normal mode after enable ADCs */
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
++		if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
++			continue;
++
++		regmap_update_bits(rk3308->regmap,
++				   RK3308_ADC_DIG_CON03(grp),
++				   RK3308_ADC_L_CH_BIST_MSK,
++				   RK3308_ADC_L_CH_NORMAL_LEFT);
++		regmap_update_bits(rk3308->regmap,
++				   RK3308_ADC_DIG_CON03(grp),
++				   RK3308_ADC_R_CH_BIST_MSK,
++				   RK3308_ADC_R_CH_NORMAL_RIGHT);
++	}
+ }
+ 
+-static int rk3308_codec_alc_enable(struct rk3308_codec_priv *rk3308)
++static irqreturn_t rk3308_codec_hpdet_isr(int irq, void *data)
+ {
+-	int ch = rk3308->adc_ch;
++	struct rk3308_codec_priv *rk3308 = data;
+ 
+ 	/*
+-	 * 1. Set he max level and min level of the ALC need to control.
+-	 *
+-	 * These values are estimated
++	 * For the high level irq trigger, disable irq and avoid a lot of
++	 * repeated irq handlers entry.
+ 	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON05(ch),
+-			   RK3308_AGC_LO_8BITS_AGC_MIN_MSK,
+-			   0x16);
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON05(ch),
+-			   RK3308_AGC_HI_8BITS_AGC_MIN_MSK,
+-			   0x40);
+-
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON05(ch),
+-			   RK3308_AGC_LO_8BITS_AGC_MAX_MSK,
+-			   0x26);
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON05(ch),
+-			   RK3308_AGC_HI_8BITS_AGC_MAX_MSK,
+-			   0x40);
++	disable_irq_nosync(rk3308->irq);
++	queue_delayed_work(system_power_efficient_wq,
++			   &rk3308->hpdet_work, msecs_to_jiffies(10));
+ 
+-	/*
+-	 * 2. Set ACODEC_ALC_DIG_CON4[2:0] according to the sample rate
+-	 *
+-	 * By default is 44.1KHz for sample.
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON04(ch),
+-			   RK3308_AGC_APPROX_RATE_MSK,
+-			   RK3308_AGC_APPROX_RATE_44_1K);
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON04(ch),
+-			   RK3308_AGC_APPROX_RATE_MSK,
+-			   RK3308_AGC_APPROX_RATE_44_1K);
+-
+-	/* 3. Set ACODEC_ALC_DIG_CON9[6] to 0x1, to enable the ALC module */
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch),
+-			   RK3308_AGC_FUNC_SEL_MSK,
+-			   RK3308_AGC_FUNC_SEL_EN);
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(ch),
+-			   RK3308_AGC_FUNC_SEL_MSK,
+-			   RK3308_AGC_FUNC_SEL_EN);
++	return IRQ_HANDLED;
++}
+ 
+-	/*
+-	 * 4. Set ACODEC_ADC_ANA_CON11[1:0], (ACODEC_ADC_ANA_CON11+0x40)[1:0],
+-	 * (ACODEC_ADC_ANA_CON11+0x80)[1:0] and (ACODEC_ADC_ANA_CON11+0xc0)[1:0]
+-	 * to 0x3, to enable the ALC module to control the gain of PGA.
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(ch),
+-			   RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK |
+-			   RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK,
+-			   RK3308_ADC_ALCL_CON_GAIN_PGAL_EN |
+-			   RK3308_ADC_ALCR_CON_GAIN_PGAR_EN);
++void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_codec *codec,
++					struct snd_soc_jack *hpdet_jack);
++EXPORT_SYMBOL_GPL(rk3308_codec_set_jack_detect_cb);
+ 
+-	/*
+-	 * 5.Observe the current ALC output gain by reading
+-	 * ACODEC_ALC_DIG_CON12[4:0]
+-	 *
+-	 * The default GAIN is 0x0c
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON12(ch),
+-			   RK3308_AGC_GAIN_MSK,
+-			   0x0c);
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON12(ch),
+-			   RK3308_AGC_GAIN_MSK,
+-			   0x0c);
++static void rk3308_codec_set_jack_detect(struct snd_soc_codec *codec,
++				  struct snd_soc_jack *hpdet_jack)
++{
++	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
+ 
+-	return 0;
+-}
++	rk3308->hpdet_jack = hpdet_jack;
+ 
+-static int rk3308_codec_alc_disable(struct rk3308_codec_priv *rk3308)
+-{
+-	int ch = rk3308->adc_ch;
++	/* To detect jack once during startup */
++	disable_irq_nosync(rk3308->irq);
++	queue_delayed_work(system_power_efficient_wq,
++			   &rk3308->hpdet_work, msecs_to_jiffies(10));
+ 
+-	/*
+-	 * 1. Set ACODEC_ALC_DIG_CON9[6] to 0x0, to disable the ALC module,
+-	 * then the ALC output gain will keep to the last value
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch),
+-			   RK3308_AGC_FUNC_SEL_MSK,
+-			   RK3308_AGC_FUNC_SEL_DIS);
+-	regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(ch),
+-			   RK3308_AGC_FUNC_SEL_MSK,
+-			   RK3308_AGC_FUNC_SEL_DIS);
++	dev_info(rk3308->plat_dev, "%s: Request detect hp jack once\n",
++		 __func__);
++}
+ 
+-	/*
+-	 * 2. Set ACODEC_ADC_ANA_CON11[1:0], (ACODEC_ADC_ANA_CON11+0x40)[1:0],
+-	 * (ACODEC_ADC_ANA_CON11+0x80)[1:0] and (ACODEC_ADC_ANA_CON11+0xc0)[1:0]
+-	 * to 0x0, to disable the ALC module to control the gain of PGA.
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(ch),
+-			   RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK |
+-			   RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK,
+-			   RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS |
+-			   RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS);
++static const struct regmap_config rk3308_codec_regmap_config = {
++	.reg_bits = 32,
++	.reg_stride = 4,
++	.val_bits = 32,
++	.max_register = RK3308_DAC_ANA_CON15,
++	.writeable_reg = rk3308_codec_write_read_reg,
++	.readable_reg = rk3308_codec_write_read_reg,
++	.volatile_reg = rk3308_codec_volatile_reg,
++	.reg_defaults = rk3308_codec_reg_defaults,
++	.num_reg_defaults = ARRAY_SIZE(rk3308_codec_reg_defaults),
++	.cache_type = REGCACHE_FLAT,
++};
+ 
+-	return 0;
++static ssize_t pm_state_show(struct device *dev,
++			     struct device_attribute *attr,
++			     char *buf)
++{
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++
++	return sprintf(buf, "pm_state: %d\n", rk3308->pm_state);
+ }
+ 
+-static int rk3308_codec_adc_ana_enable(struct rk3308_codec_priv *rk3308)
++static ssize_t pm_state_store(struct device *dev,
++			      struct device_attribute *attr,
++			      const char *buf, size_t count)
+ {
+-	unsigned int adc_aif1 = 0, adc_aif2 = 0;
+-	unsigned int agc_func_en;
+-	int ch = rk3308->adc_ch;
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	unsigned long pm_state;
++	int ret = kstrtoul(buf, 10, &pm_state);
+ 
+-	/*
+-	 * 1. Set the ACODEC_ADC_ANA_CON7[7:6] and ACODEC_ADC_ANA_CON7[5:4],
+-	 * to select the line-in or microphone as input of ADC
+-	 *
+-	 * Note1. Please ignore the step1 for enabling ADC3, ADC4, ADC5,
+-	 * ADC6, ADC7, and ADC8
+-	 */
+-	if (ch == 0) {
+-		if (rk3308->adc_ch0_using_linein) {
+-			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
+-				   RK3308_ADC_CH1_IN_SEL_MSK,
+-				   RK3308_ADC_CH1_IN_LINEIN);
+-			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
+-				   RK3308_ADC_CH2_IN_SEL_MSK,
+-				   RK3308_ADC_CH2_IN_LINEIN);
+-		} else {
+-			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
+-				   RK3308_ADC_CH1_IN_SEL_MSK,
+-				   RK3308_ADC_CH1_IN_MIC);
+-			regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch),
+-				   RK3308_ADC_CH2_IN_SEL_MSK,
+-				   RK3308_ADC_CH2_IN_MIC);
+-		}
++	if (ret < 0) {
++		dev_err(dev, "Invalid pm_state: %ld, ret: %d\n",
++			pm_state, ret);
++		return -EINVAL;
+ 	}
+ 
+-	/*
+-	 * 2. Set ACODEC_ADC_ANA_CON0[7:0] to 0xff, to end the mute station
+-	 * of ADC, to enable the MIC module, to enable the reference voltage
+-	 * buffer, and to end the initialization of MIC
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(ch),
+-				   RK3308_ADC_CH1_CH2_MIC_ALL_MSK,
+-				   RK3308_ADC_CH1_CH2_MIC_ALL);
++	rk3308_codec_set_pm_state(rk3308, pm_state);
+ 
+-	/*
+-	 * 3. Set ACODEC_ADC_ANA_CON6[0] to 0x1, to enable the current source
+-	 * of audio
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(ch),
+-				   RK3308_ADC_CURRENT_MSK,
+-				   RK3308_ADC_CURRENT_EN);
++	dev_info(dev, "Store pm_state: %d\n", rk3308->pm_state);
+ 
+-	/*
+-	 * 4. Set ACODEC_ADC_ANA_CON2[7:0] to 0x77, to enable the ALC module,
+-	 * to enable the zero-crossing detection function, and to end the
+-	 * initialization of ALC
+-	 *
+-	 * Note2. Please set ACODEC_ADC_ANA_CON2[7:0] to 0x33 in step4
+-	 * if the AGC function is closed
+-	 */
++	return count;
++}
+ 
+-	adc_aif1 = RK3308_ADC_CH1_ALC_EN | RK3308_ADC_CH1_ALC_WORK;
+-	regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), &agc_func_en);
+-	if (agc_func_en & RK3308_AGC_FUNC_SEL_EN)
+-		adc_aif1 |= RK3308_ADC_CH1_ZEROCROSS_DET_EN;
++static ssize_t adc_grps_show(struct device *dev,
++			     struct device_attribute *attr,
++			     char *buf)
++{
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	u32 grp;
++	int type = ADC_TYPE_NORMAL, count = 0;
++	int idx;
++
++	count += sprintf(buf + count, "current used adc_grps:\n");
++	count += sprintf(buf + count, "- normal:");
++	for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++)
++		count += sprintf(buf + count, " %d", grp);
++	count += sprintf(buf + count, "\n");
++	count += sprintf(buf + count, "- loopback: %d\n",
++			 rk3308->loopback_grp);
+ 
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch),
+-				   RK3308_ADC_CH1_ALC_ZC_MSK,
+-				   adc_aif1);
++	return count;
++}
+ 
+-	adc_aif2 = RK3308_ADC_CH2_ALC_EN | RK3308_ADC_CH2_ALC_WORK;
+-	regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), &agc_func_en);
+-	if (agc_func_en & RK3308_AGC_FUNC_SEL_EN)
+-		adc_aif2 |= RK3308_ADC_CH2_ZEROCROSS_DET_EN;
++static ssize_t adc_grps_store(struct device *dev,
++			      struct device_attribute *attr,
++			      const char *buf, size_t count)
++{
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	char adc_type;
++	int grps, ret;
++
++	ret = sscanf(buf, "%c,%d", &adc_type, &grps);
++	if (ret != 2) {
++		dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n",
++			__func__, ret);
++		return -EFAULT;
++	}
+ 
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch),
+-				   RK3308_ADC_CH2_ALC_ZC_MSK,
+-				   adc_aif2);
++	if (adc_type == 'n')
++		rk3308->used_adc_grps = grps;
++	else if (adc_type == 'l')
++		rk3308->loopback_grp = grps;
+ 
+-	/*
+-	 * 5. Set ACODEC_ADC_ANA_CON5[7:0] to 0x77, to enable the clock and
+-	 * ADC module, and to end the initialization of ADC
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
+-				   RK3308_ADC_CH1_ADC_CLK_MSK,
+-				   RK3308_ADC_CH1_CLK_EN |
+-				   RK3308_ADC_CH1_ADC_EN |
+-				   RK3308_ADC_CH1_ADC_WORK);
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
+-				   RK3308_ADC_CH2_ADC_CLK_MSK,
+-				   RK3308_ADC_CH2_CLK_EN |
+-				   RK3308_ADC_CH2_ADC_EN |
+-				   RK3308_ADC_CH2_ADC_WORK);
++	return count;
++}
+ 
+-	/*
+-	 * 6. Set ACODEC_ADC_ANA_CON1[5:4] and ACODEC_ADC_ANA_CON1[1:0],
+-	 * to select the gain of the MIC
+-	 *
+-	 * By default is 0db.
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
+-				   RK3308_ADC_CH1_MIC_GAIN_MSK,
+-				   RK3308_ADC_CH1_MIC_GAIN_0DB);
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
+-				   RK3308_ADC_CH2_MIC_GAIN_MSK,
+-				   RK3308_ADC_CH2_MIC_GAIN_0DB);
++static ssize_t adc_grps_route_show(struct device *dev,
++				   struct device_attribute *attr,
++				   char *buf)
++{
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	char which_i2s[32] = {0};
++	int count = 0;
++	u32 grp;
+ 
+-	/*
+-	 * 7.Set ACODEC_ADC_ANA_CON3[4:0] and ACODEC_ADC_ANA_CON4[3:0] to
+-	 * select the gain of ALC
+-	 *
+-	 * By default is 0db.
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON03(ch),
+-				   RK3308_ADC_CH1_ALC_GAIN_MSK,
+-				   RK3308_ADC_CH1_ALC_GAIN_0DB);
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON04(ch),
+-				   RK3308_ADC_CH2_ALC_GAIN_MSK,
+-				   RK3308_ADC_CH2_ALC_GAIN_0DB);
++	switch (rk3308->which_i2s) {
++	case ACODEC_TO_I2S1_2CH:
++		strcpy(which_i2s, "i2s1_2ch");
++		break;
++	case ACODEC_TO_I2S3_4CH:
++		strcpy(which_i2s, "i2s3_4ch");
++		break;
++	default:
++		strcpy(which_i2s, "i2s2_8ch");
++		break;
++	}
+ 
+-	/* 8.Begin recording */
++	count += sprintf(buf + count, "%s from acodec route mapping:\n",
++			 which_i2s);
++	for (grp = 0; grp < rk3308->to_i2s_grps; grp++) {
++		count += sprintf(buf + count, "* sdi_%d <-- sdo_%d\n",
++				 grp, rk3308->i2s_sdis[grp]);
++	}
+ 
+-	return 0;
++	return count;
+ }
+ 
+-static int rk3308_codec_adc_ana_disable(struct rk3308_codec_priv *rk3308)
++static ssize_t adc_grps_route_store(struct device *dev,
++				    struct device_attribute *attr,
++				    const char *buf, size_t count)
+ {
+-	int ch = rk3308->adc_ch;
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	int which_i2s, idx, i2s_sdis[ADC_LR_GROUP_MAX];
++	int ret;
+ 
+-	/*
+-	 * 1. Set ACODEC_ADC_ANA_CON2[7:0] to 0x0, to disable the ALC module,
+-	 * to disable the zero-crossing detection function, and to begin the
+-	 * initialization of ALC
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch),
+-				   RK3308_ADC_CH1_ALC_ZC_MSK,
+-				   0);
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch),
+-				   RK3308_ADC_CH2_ALC_ZC_MSK,
+-				   0);
++	ret = sscanf(buf, "%d,%d,%d,%d,%d", &which_i2s,
++		     &i2s_sdis[0], &i2s_sdis[1], &i2s_sdis[2], &i2s_sdis[3]);
++	if (ret != 5) {
++		dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n",
++			__func__, ret);
++		goto err;
++	}
+ 
+-	/*
+-	 * 2. Set ACODEC_ADC_ANA_CON5[7:0] to 0x0, to disable the clock and
+-	 * ADC module, and to begin the initialization of ADC
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
+-				   RK3308_ADC_CH1_ADC_CLK_MSK,
+-				   0);
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch),
+-				   RK3308_ADC_CH2_ADC_CLK_MSK,
+-				   0);
++	if (which_i2s < ACODEC_TO_I2S2_8CH ||
++	    which_i2s > ACODEC_TO_I2S1_2CH) {
++		dev_err(rk3308->plat_dev, "Invalid i2s type: %d\n", which_i2s);
++		goto err;
++	}
+ 
+-	/*
+-	 * 3. Set ACODEC_ADC_ANA_CON0[7:0] to 0x88, to disable the MIC module,
+-	 * to disable the reference voltage buffer, and to begin the
+-	 * initialization of MIC
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(ch),
+-				   RK3308_ADC_CH1_CH2_MIC_ALL_MSK,
+-				   RK3308_ADC_CH1_MIC_UNMUTE |
+-				   RK3308_ADC_CH2_MIC_UNMUTE);
++	rk3308->which_i2s = which_i2s;
+ 
+-	/*
+-	 * 4. Set ACODEC_ADC_ANA_CON6[0] to 0x0, to disable the current
+-	 * source of audio
+-	 */
+-	regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(ch),
+-				   RK3308_ADC_CURRENT_MSK,
+-				   RK3308_ADC_CURRENT_DIS);
++	switch (rk3308->which_i2s) {
++	case ACODEC_TO_I2S1_2CH:
++		rk3308->to_i2s_grps = 1;
++		break;
++	case ACODEC_TO_I2S3_4CH:
++		rk3308->to_i2s_grps = 2;
++		break;
++	default:
++		rk3308->to_i2s_grps = 4;
++		break;
++	}
+ 
+-	return 0;
++	for (idx = 0; idx < rk3308->to_i2s_grps; idx++)
++		rk3308->i2s_sdis[idx] = i2s_sdis[idx];
++
++	rk3308_codec_adc_grps_route_config(rk3308);
++
++err:
++	return count;
+ }
+ 
+-static int rk3308_codec_open_capture(struct snd_soc_codec *codec)
++static ssize_t adc_grp0_in_show(struct device *dev,
++				struct device_attribute *attr,
++				char *buf)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
+-
+-	rk3308_codec_alc_enable(rk3308);
+-	rk3308_codec_adc_ana_enable(rk3308);
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
+ 
+-	return 0;
++	return sprintf(buf, "adc ch0 using: %s\n",
++		       rk3308->adc_grp0_using_linein ? "line in" : "mic in");
+ }
+ 
+-static int rk3308_codec_close_capture(struct snd_soc_codec *codec)
++static ssize_t adc_grp0_in_store(struct device *dev,
++				 struct device_attribute *attr,
++				 const char *buf, size_t count)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	unsigned long using_linein;
++	int ret = kstrtoul(buf, 10, &using_linein);
++
++	if (ret < 0 || using_linein > 1) {
++		dev_err(dev, "Invalid input status: %ld, ret: %d\n",
++			using_linein, ret);
++		return -EINVAL;
++	}
+ 
+-	rk3308_codec_alc_disable(rk3308);
+-	rk3308_codec_adc_ana_disable(rk3308);
++	rk3308->adc_grp0_using_linein = using_linein;
+ 
+-	return 0;
++	dev_info(dev, "store using_linein: %d\n",
++		 rk3308->adc_grp0_using_linein);
++
++	return count;
+ }
+ 
+-static int rk3308_codec_open_playback(struct snd_soc_codec *codec)
++static ssize_t adc_zerocross_show(struct device *dev,
++				  struct device_attribute *attr,
++				  char *buf)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
+-
+-	rk3308_codec_dac_enable(rk3308);
+-	rk3308_speaker_ctl(rk3308, 1);
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
+ 
+-	return 0;
++	return sprintf(buf, "adc zerocross: %s\n",
++		       rk3308->adc_zerocross ? "enabled" : "disabled");
+ }
+ 
+-static int rk3308_codec_close_playback(struct snd_soc_codec *codec)
++static ssize_t adc_zerocross_store(struct device *dev,
++				   struct device_attribute *attr,
++				   const char *buf, size_t count)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	unsigned long zerocross;
++	int ret = kstrtoul(buf, 10, &zerocross);
+ 
+-	rk3308_speaker_ctl(rk3308, 0);
+-	rk3308_codec_dac_disable(rk3308);
++	if (ret < 0 || zerocross > 1) {
++		dev_err(dev, "Invalid zerocross: %ld, ret: %d\n",
++			zerocross, ret);
++		return -EINVAL;
++	}
+ 
+-	return 0;
++	rk3308->adc_zerocross = zerocross;
++
++	dev_info(dev, "store adc zerocross: %d\n", rk3308->adc_zerocross);
++
++	return count;
+ }
+ 
+-static int rk3308_pcm_startup(struct snd_pcm_substream *substream,
+-			      struct snd_soc_dai *dai)
++static ssize_t adc_grps_endisable_show(struct device *dev,
++				    struct device_attribute *attr,
++				    char *buf)
+ {
+-	struct snd_soc_codec *codec = dai->codec;
+-	int ret = 0;
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	int count = 0, i;
+ 
+-	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+-		ret = rk3308_codec_open_playback(codec);
+-	else
+-		ret = rk3308_codec_open_capture(codec);
++	count += sprintf(buf + count, "enabled adc grps:");
++	for (i = 0; i < ADC_LR_GROUP_MAX; i++)
++		count += sprintf(buf + count, "%d ",
++				 rk3308->adc_grps_endisable[i]);
+ 
+-	return ret;
++	count += sprintf(buf + count, "\n");
++	return count;
+ }
+ 
+-static void rk3308_pcm_shutdown(struct snd_pcm_substream *substream,
+-				struct snd_soc_dai *dai)
++static ssize_t adc_grps_endisable_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t count)
+ {
+-	struct snd_soc_codec *codec = dai->codec;
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	int grp, endisable, ret;
+ 
+-	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+-		rk3308_codec_close_playback(codec);
+-	else
+-		rk3308_codec_close_capture(codec);
+-}
++	ret = sscanf(buf, "%d,%d", &grp, &endisable);
++	if (ret != 2) {
++		dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n",
++			__func__, ret);
++		return -EFAULT;
++	}
+ 
+-static struct snd_soc_dai_ops rk3308_dai_ops = {
+-	.hw_params = rk3308_hw_params,
+-	.set_fmt = rk3308_set_dai_fmt,
+-	.digital_mute = rk3308_digital_mute,
+-	.startup = rk3308_pcm_startup,
+-	.shutdown = rk3308_pcm_shutdown,
+-};
++	rk3308->cur_dbg_grp = grp;
+ 
+-static struct snd_soc_dai_driver rk3308_dai[] = {
+-	{
+-		.name = "rk3308-hifi",
+-		.id = RK3308_HIFI,
+-		.playback = {
+-			.stream_name = "HiFi Playback",
+-			.channels_min = 2,
+-			.channels_max = 2,
+-			.rates = SNDRV_PCM_RATE_8000_96000,
+-			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
+-				    SNDRV_PCM_FMTBIT_S20_3LE |
+-				    SNDRV_PCM_FMTBIT_S24_LE |
+-				    SNDRV_PCM_FMTBIT_S32_LE),
+-		},
+-		.capture = {
+-			.stream_name = "HiFi Capture",
+-			.channels_min = 1,
+-			.channels_max = 8,
+-			.rates = SNDRV_PCM_RATE_8000_96000,
+-			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
+-				    SNDRV_PCM_FMTBIT_S20_3LE |
+-				    SNDRV_PCM_FMTBIT_S24_LE |
+-				    SNDRV_PCM_FMTBIT_S32_LE),
+-		},
+-		.ops = &rk3308_dai_ops,
+-	},
+-};
++	if (endisable)
++		rk3308_codec_open_dbg_capture(rk3308);
++	else
++		rk3308_codec_close_dbg_capture(rk3308);
+ 
+-static int rk3308_suspend(struct snd_soc_codec *codec)
+-{
+-	rk3308_set_bias_level(codec, SND_SOC_BIAS_OFF);
++	dev_info(dev, "ADC grp %d endisable: %d\n", grp, endisable);
+ 
+-	return 0;
++	return count;
+ }
+ 
+-static int rk3308_resume(struct snd_soc_codec *codec)
++static ssize_t dac_endisable_show(struct device *dev,
++				    struct device_attribute *attr,
++				    char *buf)
+ {
+-	rk3308_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
+ 
+-	return 0;
++	return sprintf(buf, "%d\n", rk3308->dac_endisable);
+ }
+ 
+-static int rk3308_probe(struct snd_soc_codec *codec)
++static ssize_t dac_endisable_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t count)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	unsigned long endisable;
++	int ret = kstrtoul(buf, 10, &endisable);
+ 
+-	rk3308_codec_reset(codec);
+-	rk3308_codec_power_on(codec);
++	if (ret < 0) {
++		dev_err(dev, "Invalid endisable: %ld, ret: %d\n",
++			endisable, ret);
++		return -EINVAL;
++	}
++
++	if (endisable)
++		rk3308_codec_open_playback(rk3308);
++	else
++		rk3308_codec_close_playback(rk3308);
+ 
+-	rk3308_codec_micbias_enable(rk3308, RK3308_ADC_MICBIAS_VOLT_0_7);
++	dev_info(dev, "DAC endisable: %ld\n", endisable);
+ 
+-	return 0;
++	return count;
+ }
+ 
+-static int rk3308_remove(struct snd_soc_codec *codec)
++static ssize_t dac_output_show(struct device *dev,
++			       struct device_attribute *attr,
++			       char *buf)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	ssize_t ret = 0;
+ 
+-	rk3308_speaker_ctl(rk3308, 0);
+-	rk3308_codec_micbias_disable(rk3308);
+-	rk3308_codec_power_off(codec);
++	switch (rk3308->dac_output) {
++	case DAC_LINEOUT:
++		ret = sprintf(buf, "dac path: %s\n", "line out");
++		break;
++	case DAC_HPOUT:
++		ret = sprintf(buf, "dac path: %s\n", "hp out");
++		break;
++	case DAC_LINEOUT_HPOUT:
++		ret = sprintf(buf, "dac path: %s\n",
++			      "both line out and hp out");
++		break;
++	default:
++		pr_err("Invalid dac path: %d ?\n", rk3308->dac_output);
++		break;
++	}
+ 
+-	return 0;
++	return ret;
+ }
+ 
+-static struct snd_soc_codec_driver soc_codec_dev_rk3308 = {
+-	.probe = rk3308_probe,
+-	.remove = rk3308_remove,
+-	.suspend = rk3308_suspend,
+-	.resume = rk3308_resume,
+-	.set_bias_level = rk3308_set_bias_level,
+-	.controls = rk3308_codec_dapm_controls,
+-	.num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls),
+-};
+-
+-static const struct reg_default rk3308_codec_reg_defaults[] = {
+-	{ RK3308_GLB_CON, 0x07 },
+-};
+-
+-static bool rk3308_codec_write_read_reg(struct device *dev, unsigned int reg)
++static ssize_t dac_output_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t count)
+ {
+-	/* All registers can be read / write */
+-	return true;
+-}
++	struct rk3308_codec_priv *rk3308 =
++		container_of(dev, struct rk3308_codec_priv, dev);
++	unsigned long dac_output;
++	int ret = kstrtoul(buf, 10, &dac_output);
+ 
+-static bool rk3308_codec_volatile_reg(struct device *dev, unsigned int reg)
+-{
+-	switch (reg) {
+-	case RK3308_GLB_CON:
+-		return true;
+-	default:
+-		return false;
++	if (ret < 0) {
++		dev_err(dev, "Invalid input status: %ld, ret: %d\n",
++			dac_output, ret);
++		return -EINVAL;
+ 	}
+-}
+ 
+-static const struct regmap_config rk3308_codec_regmap_config = {
+-	.reg_bits = 32,
+-	.reg_stride = 4,
+-	.val_bits = 32,
+-	.max_register = RK3308_DAC_ANA_CON13,
+-	.writeable_reg = rk3308_codec_write_read_reg,
+-	.readable_reg = rk3308_codec_write_read_reg,
+-	.volatile_reg = rk3308_codec_volatile_reg,
+-	.reg_defaults = rk3308_codec_reg_defaults,
+-	.num_reg_defaults = ARRAY_SIZE(rk3308_codec_reg_defaults),
+-	.cache_type = REGCACHE_FLAT,
+-};
++	rk3308_codec_dac_switch(rk3308, dac_output);
+ 
+-static ssize_t adc_ch_show(struct device *dev,
+-				struct device_attribute *attr,
+-				char *buf)
++	dev_info(dev, "Store dac_output: %d\n", rk3308->dac_output);
++
++	return count;
++}
++
++static ssize_t enable_all_adcs_show(struct device *dev,
++				    struct device_attribute *attr,
++				    char *buf)
+ {
+ 	struct rk3308_codec_priv *rk3308 =
+ 		container_of(dev, struct rk3308_codec_priv, dev);
+ 
+-	return sprintf(buf, "adc_ch: %d\n", rk3308->adc_ch);
++	return sprintf(buf, "%d\n", rk3308->enable_all_adcs);
+ }
+ 
+-static ssize_t adc_ch_store(struct device *dev,
+-				 struct device_attribute *attr,
+-				 const char *buf, size_t count)
++static ssize_t enable_all_adcs_store(struct device *dev,
++				     struct device_attribute *attr,
++				     const char *buf, size_t count)
+ {
+ 	struct rk3308_codec_priv *rk3308 =
+ 		container_of(dev, struct rk3308_codec_priv, dev);
+-	unsigned long ch;
+-	int ret = kstrtoul(buf, 10, &ch);
++	unsigned long enable;
++	int ret = kstrtoul(buf, 10, &enable);
+ 
+-	if (ret < 0 || ch > 4) {
+-		dev_err(dev, "Invalid ch: %ld, ret: %d\n", ch, ret);
++	if (ret < 0) {
++		dev_err(dev, "Invalid enable value: %ld, ret: %d\n",
++			enable, ret);
+ 		return -EINVAL;
+ 	}
+ 
+-	rk3308->adc_ch = ch;
+-
+-	dev_info(dev, "Store ch: %d\n", rk3308->adc_ch);
++	rk3308->enable_all_adcs = enable;
+ 
+ 	return count;
+ }
+ 
+-static const struct device_attribute adc_ch_attrs[] = {
+-	__ATTR(adc_ch, 0644, adc_ch_show, adc_ch_store),
++static const struct device_attribute acodec_attrs[] = {
++	__ATTR_RW(adc_grps),
++	__ATTR_RW(adc_grps_endisable),
++	__ATTR_RW(adc_grps_route),
++	__ATTR_RW(adc_grp0_in),
++	__ATTR_RW(adc_zerocross),
++	__ATTR_RW(dac_endisable),
++	__ATTR_RW(dac_output),
++	__ATTR_RW(enable_all_adcs),
++	__ATTR_RW(pm_state),
+ };
+ 
+ static void rk3308_codec_device_release(struct device *dev)
+@@ -1468,8 +4747,8 @@ static int rk3308_codec_sysfs_init(struct platform_device *pdev,
+ 		return -ENOMEM;
+ 	}
+ 
+-	for (i = 0; i < ARRAY_SIZE(adc_ch_attrs); i++) {
+-		if (device_create_file(dev, &adc_ch_attrs[i])) {
++	for (i = 0; i < ARRAY_SIZE(acodec_attrs); i++) {
++		if (device_create_file(dev, &acodec_attrs[i])) {
+ 			dev_err(&pdev->dev,
+ 				"Create 'rk3308-acodec-dev' attr failed\n");
+ 			device_unregister(dev);
+@@ -1480,32 +4759,136 @@ static int rk3308_codec_sysfs_init(struct platform_device *pdev,
+ 	return 0;
+ }
+ 
++#if defined(CONFIG_DEBUG_FS)
++static int rk3308_codec_debugfs_reg_show(struct seq_file *s, void *v)
++{
++	struct rk3308_codec_priv *rk3308 = s->private;
++	unsigned int i;
++	unsigned int val;
++
++	for (i = RK3308_GLB_CON; i <= RK3308_DAC_ANA_CON13; i += 4) {
++		regmap_read(rk3308->regmap, i, &val);
++		if (!(i % 16))
++			seq_printf(s, "\nR:%04x: ", i);
++		seq_printf(s, "%08x ", val);
++	}
++
++	seq_puts(s, "\n");
++
++	return 0;
++}
++
++static ssize_t rk3308_codec_debugfs_reg_operate(struct file *file,
++						const char __user *buf,
++						size_t count, loff_t *ppos)
++{
++	struct rk3308_codec_priv *rk3308 =
++		((struct seq_file *)file->private_data)->private;
++	unsigned int reg, val;
++	char op;
++	char kbuf[32];
++	int ret;
++
++	if (count >= sizeof(kbuf))
++		return -EINVAL;
++
++	if (copy_from_user(kbuf, buf, count))
++		return -EFAULT;
++	kbuf[count] = '\0';
++
++	ret = sscanf(kbuf, "%c,%x,%x", &op, &reg, &val);
++	if (ret != 3) {
++		pr_err("sscanf failed: %d\n", ret);
++		return -EFAULT;
++	}
++
++	if (op == 'w') {
++		pr_info("Write reg: 0x%04x with val: 0x%08x\n", reg, val);
++		regmap_write(rk3308->regmap, reg, val);
++		regcache_cache_only(rk3308->regmap, false);
++		regcache_sync(rk3308->regmap);
++		pr_info("Read back reg: 0x%04x with val: 0x%08x\n", reg, val);
++	} else if (op == 'r') {
++		regmap_read(rk3308->regmap, reg, &val);
++		pr_info("Read reg: 0x%04x with val: 0x%08x\n", reg, val);
++	} else {
++		pr_err("This is an invalid operation: %c\n", op);
++	}
++
++	return count;
++}
++
++static int rk3308_codec_debugfs_open(struct inode *inode, struct file *file)
++{
++	return single_open(file,
++			   rk3308_codec_debugfs_reg_show, inode->i_private);
++}
++
++static const struct file_operations rk3308_codec_reg_debugfs_fops = {
++	.owner = THIS_MODULE,
++	.open = rk3308_codec_debugfs_open,
++	.read = seq_read,
++	.write = rk3308_codec_debugfs_reg_operate,
++	.llseek = seq_lseek,
++	.release = single_release,
++};
++#endif /* CONFIG_DEBUG_FS */
++
++static int rk3308_codec_get_version(struct rk3308_codec_priv *rk3308)
++{
++	unsigned int chip_id;
++
++	regmap_read(rk3308->grf, GRF_CHIP_ID, &chip_id);
++	switch (chip_id) {
++	case 3306:
++		rk3308->codec_ver = ACODEC_VERSION_A;
++		break;
++	case 0x3308:
++		rk3308->codec_ver = ACODEC_VERSION_B;
++		break;
++	default:
++		pr_err("Unknown chip_id: %d / 0x%x\n", chip_id, chip_id);
++		return -EFAULT;
++	}
++
++	pr_info("The acodec version is: %x\n", rk3308->codec_ver);
++	return 0;
++}
++
+ static int rk3308_platform_probe(struct platform_device *pdev)
+ {
+ 	struct device_node *np = pdev->dev.of_node;
+ 	struct rk3308_codec_priv *rk3308;
+ 	struct resource *res;
+ 	void __iomem *base;
+-	int ret = 0;
+-	struct regmap *grf;
+-
+-	grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+-	if (IS_ERR(grf)) {
+-		dev_err(&pdev->dev,
+-			"Missing 'rockchip,grf' property\n");
+-		return PTR_ERR(grf);
+-	}
++	int ret;
+ 
+ 	rk3308 = devm_kzalloc(&pdev->dev, sizeof(*rk3308), GFP_KERNEL);
+ 	if (!rk3308)
+ 		return -ENOMEM;
+ 
++	rk3308->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
++	if (IS_ERR(rk3308->grf)) {
++		dev_err(&pdev->dev,
++			"Missing 'rockchip,grf' property\n");
++		return PTR_ERR(rk3308->grf);
++	}
++
+ 	ret = rk3308_codec_sysfs_init(pdev, rk3308);
+ 	if (ret < 0) {
+ 		dev_err(&pdev->dev, "Sysfs init failed\n");
+ 		return ret;
+ 	}
+ 
++#if defined(CONFIG_DEBUG_FS)
++	rk3308->dbg_codec = debugfs_create_dir(CODEC_DRV_NAME, NULL);
++	if (IS_ERR(rk3308->dbg_codec))
++		dev_err(&pdev->dev,
++			"Failed to create debugfs dir for rk3308!\n");
++	else
++		debugfs_create_file("reg", 0644, rk3308->dbg_codec,
++				    rk3308, &rk3308_codec_reg_debugfs_fops);
++#endif
+ 	rk3308->plat_dev = &pdev->dev;
+ 
+ 	rk3308->reset = devm_reset_control_get(&pdev->dev, "acodec-reset");
+@@ -1518,27 +4901,146 @@ static int rk3308_platform_probe(struct platform_device *pdev)
+ 		rk3308->reset = NULL;
+ 	}
+ 
+-	/* GPIO0_A5 control speaker on RK3308 EVB */
+-	rk3308->spk_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "spk_ctl",
+-						       GPIOD_OUT_HIGH);
+-	if (IS_ERR(rk3308->spk_ctl_gpio)) {
++	rk3308->hp_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "hp-ctl",
++						       GPIOD_OUT_LOW);
++	if (!rk3308->hp_ctl_gpio) {
++		dev_info(&pdev->dev, "Don't need hp-ctl gpio\n");
++	} else if (IS_ERR(rk3308->hp_ctl_gpio)) {
++		ret = PTR_ERR(rk3308->hp_ctl_gpio);
++		dev_err(&pdev->dev, "Unable to claim gpio hp-ctl\n");
++		return ret;
++	}
++
++	rk3308->spk_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "spk-ctl",
++						       GPIOD_OUT_LOW);
++
++	if (!rk3308->spk_ctl_gpio) {
++		dev_info(&pdev->dev, "Don't need spk-ctl gpio\n");
++	} else if (IS_ERR(rk3308->spk_ctl_gpio)) {
+ 		ret = PTR_ERR(rk3308->spk_ctl_gpio);
+-		dev_err(&pdev->dev, "Unable to claim gpio spk_ctl\n");
++		dev_err(&pdev->dev, "Unable to claim gpio spk-ctl\n");
++		return ret;
++	}
++
++	rk3308->pa_drv_gpio = devm_gpiod_get_optional(&pdev->dev, "pa-drv",
++						       GPIOD_OUT_LOW);
++
++	if (!rk3308->pa_drv_gpio) {
++		dev_info(&pdev->dev, "Don't need pa-drv gpio\n");
++	} else if (IS_ERR(rk3308->pa_drv_gpio)) {
++		ret = PTR_ERR(rk3308->pa_drv_gpio);
++		dev_err(&pdev->dev, "Unable to claim gpio pa-drv\n");
+ 		return ret;
+ 	}
+ 
++	if (rk3308->pa_drv_gpio) {
++		rk3308->delay_pa_drv_ms = PA_DRV_MS;
++		ret = of_property_read_u32(np, "rockchip,delay-pa-drv-ms",
++					   &rk3308->delay_pa_drv_ms);
++	}
++
++#if DEBUG_POP_ALWAYS
++	dev_info(&pdev->dev, "Enable all ctl gpios always for debugging pop\n");
++	rk3308_headphone_ctl(rk3308, 1);
++	rk3308_speaker_ctl(rk3308, 1);
++#else
++	dev_info(&pdev->dev, "De-pop as much as possible\n");
++	rk3308_headphone_ctl(rk3308, 0);
++	rk3308_speaker_ctl(rk3308, 0);
++#endif
++
+ 	rk3308->pclk = devm_clk_get(&pdev->dev, "acodec");
+ 	if (IS_ERR(rk3308->pclk)) {
+ 		dev_err(&pdev->dev, "Can't get acodec pclk\n");
+ 		return PTR_ERR(rk3308->pclk);
+ 	}
+ 
++	rk3308->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
++	if (IS_ERR(rk3308->mclk_rx)) {
++		dev_err(&pdev->dev, "Can't get acodec mclk_rx\n");
++		return PTR_ERR(rk3308->mclk_rx);
++	}
++
++	rk3308->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
++	if (IS_ERR(rk3308->mclk_tx)) {
++		dev_err(&pdev->dev, "Can't get acodec mclk_tx\n");
++		return PTR_ERR(rk3308->mclk_tx);
++	}
++
+ 	ret = clk_prepare_enable(rk3308->pclk);
+ 	if (ret < 0) {
+ 		dev_err(&pdev->dev, "Failed to enable acodec pclk: %d\n", ret);
+ 		return ret;
+ 	}
+ 
++	ret = clk_prepare_enable(rk3308->mclk_rx);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Failed to enable i2s mclk_rx: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(rk3308->mclk_tx);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Failed to enable i2s mclk_tx: %d\n", ret);
++		return ret;
++	}
++
++	rk3308_codec_check_micbias(rk3308, np);
++
++	rk3308->enable_all_adcs =
++		of_property_read_bool(np, "rockchip,enable-all-adcs");
++
++	rk3308->hp_jack_reversed =
++		of_property_read_bool(np, "rockchip,hp-jack-reversed");
++
++	rk3308->no_deep_low_power =
++		of_property_read_bool(np, "rockchip,no-deep-low-power");
++
++	rk3308->no_hp_det =
++		of_property_read_bool(np, "rockchip,no-hp-det");
++
++	rk3308->delay_loopback_handle_ms = LOOPBACK_HANDLE_MS;
++	ret = of_property_read_u32(np, "rockchip,delay-loopback-handle-ms",
++				   &rk3308->delay_loopback_handle_ms);
++
++	rk3308->delay_start_play_ms = 0;
++	ret = of_property_read_u32(np, "rockchip,delay-start-play-ms",
++				   &rk3308->delay_start_play_ms);
++
++	rk3308->loopback_grp = NOT_USED;
++	ret = of_property_read_u32(np, "rockchip,loopback-grp",
++				   &rk3308->loopback_grp);
++	/*
++	 * If there is no loopback on some board, the -EINVAL indicates that
++	 * we don't need add the node, and it is not an error.
++	 */
++	if (ret < 0 && ret != -EINVAL) {
++		dev_err(&pdev->dev, "Failed to read loopback property: %d\n",
++			ret);
++		return ret;
++	}
++
++	ret = rk3308_codec_adc_grps_route(rk3308, np);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Failed to route ADC groups: %d\n",
++			ret);
++		return ret;
++	}
++
++	ret = rk3308_codec_setup_en_always_adcs(rk3308, np);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Failed to setup enabled always ADCs: %d\n",
++			ret);
++		return ret;
++	}
++
++	ret = rk3308_codec_get_version(rk3308);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Failed to get acodec version: %d\n",
++			ret);
++		return ret;
++	}
++
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	base = devm_ioremap_resource(&pdev->dev, res);
+ 	if (IS_ERR(base)) {
+@@ -1555,10 +5057,65 @@ static int rk3308_platform_probe(struct platform_device *pdev)
+ 		goto failed;
+ 	}
+ 
++	if (!rk3308->no_hp_det) {
++		int index = 0;
++
++		if (rk3308->codec_ver == ACODEC_VERSION_B)
++			index = 1;
++
++		rk3308->irq = platform_get_irq(pdev, index);
++		if (rk3308->irq < 0) {
++			dev_err(&pdev->dev, "Can not get codec irq\n");
++			goto failed;
++		}
++
++		INIT_DELAYED_WORK(&rk3308->hpdet_work, rk3308_codec_hpdetect_work);
++
++		ret = devm_request_irq(&pdev->dev, rk3308->irq,
++				       rk3308_codec_hpdet_isr,
++				       0,
++				       "acodec-hpdet",
++				       rk3308);
++		if (ret < 0) {
++			dev_err(&pdev->dev, "Failed to request IRQ: %d\n", ret);
++			goto failed;
++		}
++
++		if (rk3308->codec_ver == ACODEC_VERSION_B) {
++			rk3308->detect_grf =
++				syscon_regmap_lookup_by_phandle(np, "rockchip,detect-grf");
++			if (IS_ERR(rk3308->detect_grf)) {
++				dev_err(&pdev->dev,
++					"Missing 'rockchip,detect-grf' property\n");
++				return PTR_ERR(rk3308->detect_grf);
++			}
++
++			/* Configure filter count and enable hpdet irq. */
++			regmap_write(rk3308->detect_grf,
++				     DETECT_GRF_ACODEC_HPDET_COUNTER,
++				     DEFAULT_HPDET_COUNT);
++			regmap_write(rk3308->detect_grf,
++				     DETECT_GRF_ACODEC_HPDET_CON,
++				     (HPDET_BOTH_NEG_POS << 16) |
++				      HPDET_BOTH_NEG_POS);
++		}
++
++		rk3308_codec_set_jack_detect_cb = rk3308_codec_set_jack_detect;
++	}
++
++	if (rk3308->codec_ver == ACODEC_VERSION_A)
++		INIT_DELAYED_WORK(&rk3308->loopback_work,
++				  rk3308_codec_loopback_work);
++
++	rk3308->adc_grp0_using_linein = ADC_GRP0_MICIN;
++	rk3308->dac_output = DAC_LINEOUT;
++	rk3308->adc_zerocross = 1;
++	rk3308->pm_state = PM_NORMAL;
++
+ 	platform_set_drvdata(pdev, rk3308);
+ 
+ 	ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_rk3308,
+-				      rk3308_dai, ARRAY_SIZE(rk3308_dai));
++				     rk3308_dai, ARRAY_SIZE(rk3308_dai));
+ 	if (ret < 0) {
+ 		dev_err(&pdev->dev, "Failed to register codec: %d\n", ret);
+ 		goto failed;
+@@ -1567,7 +5124,10 @@ static int rk3308_platform_probe(struct platform_device *pdev)
+ 	return ret;
+ 
+ failed:
++	clk_disable_unprepare(rk3308->mclk_rx);
++	clk_disable_unprepare(rk3308->mclk_tx);
+ 	clk_disable_unprepare(rk3308->pclk);
++	device_unregister(&rk3308->dev);
+ 
+ 	return ret;
+ }
+@@ -1577,8 +5137,11 @@ static int rk3308_platform_remove(struct platform_device *pdev)
+ 	struct rk3308_codec_priv *rk3308 =
+ 		(struct rk3308_codec_priv *)platform_get_drvdata(pdev);
+ 
++	clk_disable_unprepare(rk3308->mclk_rx);
++	clk_disable_unprepare(rk3308->mclk_tx);
+ 	clk_disable_unprepare(rk3308->pclk);
+ 	snd_soc_unregister_codec(&pdev->dev);
++	device_unregister(&rk3308->dev);
+ 
+ 	return 0;
+ }
+@@ -1591,7 +5154,7 @@ MODULE_DEVICE_TABLE(of, rk3308codec_of_match);
+ 
+ static struct platform_driver rk3308_codec_driver = {
+ 	.driver = {
+-		   .name = "rk3308-acodec",
++		   .name = CODEC_DRV_NAME,
+ 		   .of_match_table = of_match_ptr(rk3308codec_of_match),
+ 	},
+ 	.probe = rk3308_platform_probe,
+diff --git a/sound/soc/codecs/rk3308_codec.h b/sound/soc/codecs/rk3308_codec.h
+index 6cfa69157785..93e089dae081 100644
+--- a/sound/soc/codecs/rk3308_codec.h
++++ b/sound/soc/codecs/rk3308_codec.h
+@@ -26,7 +26,8 @@
+ #define ACODEC_ADC_I2S_CTL0			0x04 /* REG 0x01 */
+ #define ACODEC_ADC_I2S_CTL1			0x08 /* REG 0x02 */
+ #define ACODEC_ADC_BIST_MODE_SEL		0x0c /* REG 0x03 */
+-/* Resevred REG 0x04 ~ 0x06 */
++#define ACODEC_ADC_HPF_PATH			0x10 /* REG 0x04 */
++/* Resevred REG 0x05 ~ 0x06 */
+ #define ACODEC_ADC_DATA_PATH			0x1c /* REG 0x07 */
+ /* Resevred REG 0x08 ~ 0x0f */
+ 
+@@ -62,12 +63,15 @@
+ #define ACODEC_DAC_I2S_CTL0			0x04 /* REG 0x01 */
+ #define ACODEC_DAC_I2S_CTL1			0x08 /* REG 0x02 */
+ #define ACODEC_DAC_BIST_MODE_SEL		0x0c /* REG 0x03 */
+-/* Resevred REG 0x04 */
++#define ACODEC_DAC_DIGITAL_GAIN			0x10 /* REG 0x04 */
+ #define ACODEC_DAC_DATA_SEL			0x14 /* REG 0x05 */
+ /* Resevred REG 0x06 ~ 0x09 */
+ #define ACODEC_DAC_DATA_HI			0x28 /* REG 0x0a */
+ #define ACODEC_DAC_DATA_LO			0x2c /* REG 0x0b */
+-/* Resevred REG 0x0c ~ 0x0f */
++/* Resevred REG 0x0c */
++#define ACODEC_DAC_HPDET_DELAYTIME		0x34 /* REG 0x0d */
++#define ACODEC_DAC_HPDET_STATUS			0x38 /* REG 0x0e, Read-only */
++/* Resevred REG 0x0f */
+ 
+ /* ADC ANALOG REGISTERS */
+ #define ACODEC_ADC_ANA_MIC_CTL			0x00 /* REG 0x00 */
+@@ -92,10 +96,13 @@
+ #define ACODEC_DAC_ANA_LINEOUT			0x10 /* REG 0x04 */
+ #define ACODEC_DAC_ANA_L_HPOUT_GAIN		0x14 /* REG 0x05 */
+ #define ACODEC_DAC_ANA_R_HPOUT_GAIN		0x18 /* REG 0x06 */
++#define ACODEC_DAC_ANA_DRV_HPOUT		0x1c /* REG 0x07 */
++#define ACODEC_DAC_ANA_DRV_LINEOUT		0x20 /* REG 0x08 */
+ /* Resevred REG 0x07 ~ 0x0b */
+ #define ACODEC_DAC_ANA_HPMIX_CTL0		0x30 /* REG 0x0c */
+ #define ACODEC_DAC_ANA_HPMIX_CTL1		0x34 /* REG 0x0d */
+-/* Resevred REG 0x0e ~ 0x0f */
++#define ACODEC_DAC_ANA_LINEOUT_CTL0		0x38 /* REG 0x0e */
++#define ACODEC_DAC_ANA_LINEOUT_CTL1		0x3c /* REG 0x0f */
+ 
+ /*
+  * These registers are referenced by codec driver
+@@ -106,7 +113,7 @@
+ /* ADC DIGITAL REGISTERS */
+ 
+ /*
+- * The ADC chanel are 0 ~ 3, that control:
++ * The ADC group are 0 ~ 3, that control:
+  *
+  * CH0: left_0(ADC1) and right_0(ADC2)
+  * CH1: left_1(ADC3) and right_1(ADC4)
+@@ -118,6 +125,7 @@
+ #define RK3308_ADC_DIG_CON01(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL0)
+ #define RK3308_ADC_DIG_CON02(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL1)
+ #define RK3308_ADC_DIG_CON03(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_BIST_MODE_SEL)
++#define RK3308_ADC_DIG_CON04(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_HPF_PATH)
+ #define RK3308_ADC_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH)
+ 
+ #define RK3308_ALC_L_DIG_CON00(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL0)
+@@ -150,13 +158,16 @@
+ #define RK3308_DAC_DIG_CON01			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL0)
+ #define RK3308_DAC_DIG_CON02			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL1)
+ #define RK3308_DAC_DIG_CON03			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_BIST_MODE_SEL)
++#define RK3308_DAC_DIG_CON04			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DIGITAL_GAIN)
+ #define RK3308_DAC_DIG_CON05			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_SEL)
+ #define RK3308_DAC_DIG_CON10			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_HI)
+ #define RK3308_DAC_DIG_CON11			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_LO)
++#define RK3308_DAC_DIG_CON13			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_DELAYTIME)
++#define RK3308_DAC_DIG_CON14			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_STATUS)
+ 
+ /* ADC ANALOG REGISTERS */
+ /*
+- * The ADC chanel are 0 ~ 3, that control:
++ * The ADC group are 0 ~ 3, that control:
+  *
+  * CH0: left_0(ADC1) and right_0(ADC2)
+  * CH1: left_1(ADC3) and right_1(ADC4)
+@@ -179,7 +190,6 @@
+ 
+ /* DAC ANALOG REGISTERS */
+ #define RK3308_DAC_ANA_OFFSET			0x440
+-
+ #define RK3308_DAC_ANA_CON00			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL0)
+ #define RK3308_DAC_ANA_CON01			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_POP_VOLT)
+ #define RK3308_DAC_ANA_CON02			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL1)
+@@ -187,8 +197,12 @@
+ #define RK3308_DAC_ANA_CON04			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT)
+ #define RK3308_DAC_ANA_CON05			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_L_HPOUT_GAIN)
+ #define RK3308_DAC_ANA_CON06			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_R_HPOUT_GAIN)
++#define RK3308_DAC_ANA_CON07			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_DRV_HPOUT)
++#define RK3308_DAC_ANA_CON08			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_DRV_LINEOUT)
+ #define RK3308_DAC_ANA_CON12			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL0)
+ #define RK3308_DAC_ANA_CON13			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL1)
++#define RK3308_DAC_ANA_CON14			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT_CTL0)
++#define RK3308_DAC_ANA_CON15			(RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT_CTL1)
+ 
+ /*
+  * These are the bits for registers
+@@ -199,6 +213,12 @@
+ #define RK3308_ADC_BIST_RESET			(0 << 7)
+ #define RK3308_DAC_BIST_WORK			(1 << 6)
+ #define RK3308_DAC_BIST_RESET			(0 << 6)
++#define RK3308_ADC_MCLK_MSK			(1 << 5)
++#define RK3308_ADC_MCLK_DIS			(1 << 5)
++#define RK3308_ADC_MCLK_EN			(0 << 5)
++#define RK3308_DAC_MCLK_MSK			(1 << 4)
++#define RK3308_DAC_MCLK_DIS			(1 << 4)
++#define RK3308_DAC_MCLK_EN			(0 << 4)
+ #define RK3308_CODEC_RST_MSK			(0x7 << 0)
+ #define RK3308_ADC_DIG_WORK			(1 << 2)
+ #define RK3308_ADC_DIG_RESET			(0 << 2)
+@@ -253,16 +273,27 @@
+ /* RK3308_ADC_DIG_CON03 - REG: 0x000c */
+ #define RK3308_ADC_L_CH_BIST_SFT		2
+ #define RK3308_ADC_L_CH_BIST_MSK		(0x3 << RK3308_ADC_L_CH_BIST_SFT)
+-#define RK3308_ADC_L_CH_BIST_LEFT		(0x3 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */
+-#define RK3308_ADC_L_CH_BIST_SINE		(0x2 << RK3308_ADC_L_CH_BIST_SFT)
+-#define RK3308_ADC_L_CH_BIST_CUBE		(0x1 << RK3308_ADC_L_CH_BIST_SFT)
+-#define RK3308_ADC_L_CH_BIST_RIGHT		(0x0 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */
++#define RK3308_ADC_L_CH_NORMAL_RIGHT		(0x3 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */
++#define RK3308_ADC_L_CH_BIST_CUBE		(0x2 << RK3308_ADC_L_CH_BIST_SFT)
++#define RK3308_ADC_L_CH_BIST_SINE		(0x1 << RK3308_ADC_L_CH_BIST_SFT)
++#define RK3308_ADC_L_CH_NORMAL_LEFT		(0x0 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */
+ #define RK3308_ADC_R_CH_BIST_SFT		0
+ #define RK3308_ADC_R_CH_BIST_MSK		(0x3 << RK3308_ADC_R_CH_BIST_SFT)
+-#define RK3308_ADC_R_CH_BIST_LEFT		(0x3 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */
+-#define RK3308_ADC_R_CH_BIST_SINE		(0x2 << RK3308_ADC_R_CH_BIST_SFT)
+-#define RK3308_ADC_R_CH_BIST_CUBE		(0x1 << RK3308_ADC_R_CH_BIST_SFT)
+-#define RK3308_ADC_R_CH_BIST_RIGHT		(0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */
++#define RK3308_ADC_R_CH_NORMAL_LEFT		(0x3 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */
++#define RK3308_ADC_R_CH_BIST_CUBE		(0x2 << RK3308_ADC_R_CH_BIST_SFT)
++#define RK3308_ADC_R_CH_BIST_SINE		(0x1 << RK3308_ADC_R_CH_BIST_SFT)
++#define RK3308_ADC_R_CH_NORMAL_RIGHT		(0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */
++
++/* RK3308_ADC_DIG_CON04 - REG: 0x0010 */
++#define RK3308_ADC_HPF_PATH_SFT			2
++#define RK3308_ADC_HPF_PATH_MSK			(1 << RK3308_ADC_HPF_PATH_SFT)
++#define RK3308_ADC_HPF_PATH_DIS			(1 << RK3308_ADC_HPF_PATH_SFT)
++#define RK3308_ADC_HPF_PATH_EN			(0 << RK3308_ADC_HPF_PATH_SFT)
++#define RK3308_ADC_HPF_CUTOFF_SFT		0
++#define RK3308_ADC_HPF_CUTOFF_MSK		(0x3 << RK3308_ADC_HPF_CUTOFF_SFT)
++#define RK3308_ADC_HPF_CUTOFF_612HZ		(0x2 << RK3308_ADC_HPF_CUTOFF_SFT)
++#define RK3308_ADC_HPF_CUTOFF_245HZ		(0x1 << RK3308_ADC_HPF_CUTOFF_SFT)
++#define RK3308_ADC_HPF_CUTOFF_20HZ		(0x0 << RK3308_ADC_HPF_CUTOFF_SFT)
+ 
+ /* RK3308_ADC_DIG_CON07 - REG: 0x001c */
+ #define RK3308_ADCL_DATA_SFT			4
+@@ -391,6 +422,8 @@
+  */
+ #define RK3308_AGC_PGA_ZERO_CRO_EN		(0x1 << 5)
+ #define RK3308_AGC_PGA_ZERO_CRO_DIS		(0x0 << 5)
++#define RK3308_AGC_PGA_GAIN_MAX			0x1f
++#define RK3308_AGC_PGA_GAIN_MIN			0
+ #define RK3308_AGC_PGA_GAIN_SFT			0
+ #define RK3308_AGC_PGA_GAIN_MSK			(0x1f << RK3308_AGC_PGA_GAIN_SFT)
+ #define RK3308_AGC_PGA_GAIN_PDB_28_5		(0x1f << RK3308_AGC_PGA_GAIN_SFT)
+@@ -474,6 +507,8 @@
+ #define RK3308_AGC_FUNC_SEL_MSK			(0x1 << 6)
+ #define RK3308_AGC_FUNC_SEL_EN			(0x1 << 6)
+ #define RK3308_AGC_FUNC_SEL_DIS			(0x0 << 6)
++#define RK3308_AGC_MAX_GAIN_PGA_MAX		0x7
++#define RK3308_AGC_MAX_GAIN_PGA_MIN		0
+ #define RK3308_AGC_MAX_GAIN_PGA_SFT		3
+ #define RK3308_AGC_MAX_GAIN_PGA_MSK		(0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT)
+ #define RK3308_AGC_MAX_GAIN_PGA_PDB_28_5	(0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT)
+@@ -484,6 +519,8 @@
+ #define RK3308_AGC_MAX_GAIN_PGA_NDB_1_5		(0x2 << RK3308_AGC_MAX_GAIN_PGA_SFT)
+ #define RK3308_AGC_MAX_GAIN_PGA_NDB_7_5		(0x1 << RK3308_AGC_MAX_GAIN_PGA_SFT)
+ #define RK3308_AGC_MAX_GAIN_PGA_NDB_13_5	(0x0 << RK3308_AGC_MAX_GAIN_PGA_SFT)
++#define RK3308_AGC_MIN_GAIN_PGA_MAX		0x7
++#define RK3308_AGC_MIN_GAIN_PGA_MIN		0
+ #define RK3308_AGC_MIN_GAIN_PGA_SFT		0
+ #define RK3308_AGC_MIN_GAIN_PGA_MSK		(0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT)
+ #define RK3308_AGC_MIN_GAIN_PGA_PDB_24		(0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT)
+@@ -555,6 +592,18 @@
+ #define RK3308_DAC_R_CH_BIST_SINE		(0x1 << RK3308_DAC_R_CH_BIST_SFT)
+ #define RK3308_DAC_R_CH_BIST_RIGHT		(0x0 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */
+ 
++/* RK3308_DAC_DIG_CON04 - REG: 0x0310 */
++#define RK3308_DAC_MODULATOR_GAIN_SFT		4
++#define RK3308_DAC_MODULATOR_GAIN_MSK		(0x7 << RK3308_DAC_MODULATOR_GAIN_SFT)
++#define RK3308_DAC_MODULATOR_GAIN_4_8DB		(0x5 << RK3308_DAC_MODULATOR_GAIN_SFT)
++#define RK3308_DAC_MODULATOR_GAIN_4_2DB		(0x4 << RK3308_DAC_MODULATOR_GAIN_SFT)
++#define RK3308_DAC_MODULATOR_GAIN_3_5DB		(0x3 << RK3308_DAC_MODULATOR_GAIN_SFT)
++#define RK3308_DAC_MODULATOR_GAIN_2_8DB		(0x2 << RK3308_DAC_MODULATOR_GAIN_SFT)
++#define RK3308_DAC_MODULATOR_GAIN_2DB		(0x1 << RK3308_DAC_MODULATOR_GAIN_SFT)
++#define RK3308_DAC_MODULATOR_GAIN_0DB		(0x0 << RK3308_DAC_MODULATOR_GAIN_SFT)
++#define RK3308_DAC_CIC_IF_GAIN_SFT		0
++#define RK3308_DAC_CIC_IF_GAIN_MSK		(0x7 << RK3308_DAC_CIC_IF_GAIN_SFT)
++
+ /* RK3308_DAC_DIG_CON05 - REG: 0x0314 */
+ #define RK3308_DAC_L_REG_CTL_INDATA		(0x1 << 2)
+ #define RK3308_DAC_L_NORMAL_DATA		(0x0 << 2)
+@@ -587,18 +636,30 @@
+ #define RK3308_ADC_CH1_BUF_REF_EN		(0x1 << 0)
+ #define RK3308_ADC_CH1_BUF_REF_DIS		(0x0 << 0)
+ 
+-/* RK3308_ADC_ANA_CON01 - REG: 0x0344 */
++/* RK3308_ADC_ANA_CON01 - REG: 0x0344
++ *
++ * The PGA of MIC-INs:
++ * 0x0 - MIC1~MIC8 0dB
++ * 0x1 - MIC1~MIC8 6.6dB
++ * 0x2 - MIC1~MIC8 13dB
++ * 0x3 - MIC1~MIC8 20dB
++ */
++#define RK3308_ADC_CH2_MIC_GAIN_MAX		0x3
++#define RK3308_ADC_CH2_MIC_GAIN_MIN		0
+ #define RK3308_ADC_CH2_MIC_GAIN_SFT		4
+ #define RK3308_ADC_CH2_MIC_GAIN_MSK		(0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT)
+-#define RK3308_ADC_CH2_MIC_GAIN_30DB		(0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT)
+-#define RK3308_ADC_CH2_MIC_GAIN_20DB		(0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT)
+-#define RK3308_ADC_CH2_MIC_GAIN_6DB		(0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT)
++#define RK3308_ADC_CH2_MIC_GAIN_20DB		(0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT)
++#define RK3308_ADC_CH2_MIC_GAIN_13DB		(0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT) /* TRM: only used for version B  */
++#define RK3308_ADC_CH2_MIC_GAIN_6_6DB		(0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT) /* TRM: only used for version B  */
+ #define RK3308_ADC_CH2_MIC_GAIN_0DB		(0x0 << RK3308_ADC_CH2_MIC_GAIN_SFT)
++
++#define RK3308_ADC_CH1_MIC_GAIN_MAX		0x3
++#define RK3308_ADC_CH1_MIC_GAIN_MIN		0
+ #define RK3308_ADC_CH1_MIC_GAIN_SFT		0
+ #define RK3308_ADC_CH1_MIC_GAIN_MSK		(0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT)
+-#define RK3308_ADC_CH1_MIC_GAIN_30DB		(0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT)
+-#define RK3308_ADC_CH1_MIC_GAIN_20DB		(0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT)
+-#define RK3308_ADC_CH1_MIC_GAIN_6DB		(0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT)
++#define RK3308_ADC_CH1_MIC_GAIN_20DB		(0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT)
++#define RK3308_ADC_CH1_MIC_GAIN_13DB		(0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT) /* TRM: only used for version B  */
++#define RK3308_ADC_CH1_MIC_GAIN_6_6DB		(0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT) /* TRM: only used for version B  */
+ #define RK3308_ADC_CH1_MIC_GAIN_0DB		(0x0 << RK3308_ADC_CH1_MIC_GAIN_SFT)
+ 
+ /* RK3308_ADC_ANA_CON02 - REG: 0x0348 */
+@@ -619,6 +680,8 @@
+ #define RK3308_ADC_CH1_ALC_DIS			(0x0 << 0)
+ 
+ /* RK3308_ADC_ANA_CON03 - REG: 0x034c */
++#define RK3308_ADC_CH1_ALC_GAIN_MAX		0x1f
++#define RK3308_ADC_CH1_ALC_GAIN_MIN		0
+ #define RK3308_ADC_CH1_ALC_GAIN_SFT		0
+ #define RK3308_ADC_CH1_ALC_GAIN_MSK		(0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT)
+ #define RK3308_ADC_CH1_ALC_GAIN_PDB_28_5	(0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT)
+@@ -655,6 +718,8 @@
+ #define RK3308_ADC_CH1_ALC_GAIN_NDB_18		(0x00 << RK3308_ADC_CH1_ALC_GAIN_SFT)
+ 
+ /* RK3308_ADC_ANA_CON04 - REG: 0x0350 */
++#define RK3308_ADC_CH2_ALC_GAIN_MAX		0x1f
++#define RK3308_ADC_CH2_ALC_GAIN_MIN		0
+ #define RK3308_ADC_CH2_ALC_GAIN_SFT		0
+ #define RK3308_ADC_CH2_ALC_GAIN_MSK		(0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT)
+ #define RK3308_ADC_CH2_ALC_GAIN_PDB_28_5	(0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT)
+@@ -728,10 +793,16 @@
+ #define RK3308_ADC_CH1_IN_MIC			(0x1 << RK3308_ADC_CH1_IN_SEL_SFT)
+ #define RK3308_ADC_CH1_IN_NONE			(0x0 << RK3308_ADC_CH1_IN_SEL_SFT)
+ 
+-#define RK3308_ADC_MIC_BIAS_BUF_EN		(0x1 << 3)
+-#define RK3308_ADC_MIC_BIAS_BUF_DIS		(0x0 << 3)
++#define RK3308_ADC_MIC_BIAS_BUF_SFT		3
++#define RK3308_ADC_MIC_BIAS_BUF_EN		(0x1 << RK3308_ADC_MIC_BIAS_BUF_SFT)
++#define RK3308_ADC_MIC_BIAS_BUF_DIS		(0x0 << RK3308_ADC_MIC_BIAS_BUF_SFT)
+ #define RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT	0
+ #define RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK	(0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
++/*
++ * The follow MICBIAS_VOLTs are based on the external reference voltage(Vref).
++ * For example, the Vref == 3.3V, the MICBIAS_VOLT_0_85 is equal:
++ * 3.3V * 0.85 = 2.805V.
++ */
+ #define RK3308_ADC_MICBIAS_VOLT_0_85		(0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
+ #define RK3308_ADC_MICBIAS_VOLT_0_8		(0x6 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
+ #define RK3308_ADC_MICBIAS_VOLT_0_75		(0x5 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)
+@@ -751,18 +822,11 @@
+ #define RK3308_ADC_REF_DIS			(0x0 << 7)
+ #define RK3308_ADC_CURRENT_CHARGE_SFT		0
+ #define RK3308_ADC_CURRENT_CHARGE_MSK		(0x7f << RK3308_ADC_CURRENT_CHARGE_SFT)
+-#define RK3308_ADC_DONT_SEL_ALL			(0x7f << RK3308_ADC_CURRENT_CHARGE_SFT)
+ /*
+- * 0: Choose the current I
+- * 1: Don't choose the current I
++ * 1: Choose the current I
++ * 0: Don't choose the current I
+  */
+-#define RK3308_ADC_SEL_I_1(x)			((x & 0x1) << 6)
+-#define RK3308_ADC_SEL_I_2(x)			((x & 0x1) << 5)
+-#define RK3308_ADC_SEL_I_4(x)			((x & 0x1) << 4)
+-#define RK3308_ADC_SEL_I_8(x)			((x & 0x1) << 3)
+-#define RK3308_ADC_SEL_I_16(x)			((x & 0x1) << 2)
+-#define RK3308_ADC_SEL_I_32(x)			((x & 0x1) << 1)
+-#define RK3308_ADC_SEL_I_64(x)			((x & 0x1) << 0)
++#define RK3308_ADC_SEL_I(x)			(x & 0x7f)
+ 
+ /* RK3308_ADC_ANA_CON11 - REG: 0x036c */
+ #define RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK	(0x1 << 1)
+@@ -773,6 +837,7 @@
+ #define RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS	(0x0 << 0)
+ 
+ /* RK3308_DAC_ANA_CON00 - REG: 0x0440 */
++#define RK3308_DAC_HEADPHONE_DET_MSK		(0x1 << 1)
+ #define RK3308_DAC_HEADPHONE_DET_EN		(0x1 << 1)
+ #define RK3308_DAC_HEADPHONE_DET_DIS		(0x0 << 1)
+ #define RK3308_DAC_CURRENT_MSK			(0x1 << 0)
+@@ -783,17 +848,17 @@
+ #define RK3308_DAC_BUF_REF_R_MSK		(0x1 << 6)
+ #define RK3308_DAC_BUF_REF_R_EN			(0x1 << 6)
+ #define RK3308_DAC_BUF_REF_R_DIS		(0x0 << 6)
+-#define RK3308_DAC_POP_SOUND_R_SFT		4
+-#define RK3308_DAC_POP_SOUND_R_MSK		(0x3 << RK3308_DAC_POP_SOUND_R_SFT)
+-#define RK3308_DAC_POP_SOUND_R_WORK		(0x2 << RK3308_DAC_POP_SOUND_R_SFT)
+-#define RK3308_DAC_POP_SOUND_R_INIT		(0x1 << RK3308_DAC_POP_SOUND_R_SFT)
++#define RK3308_DAC_HPOUT_POP_SOUND_R_SFT	4
++#define RK3308_DAC_HPOUT_POP_SOUND_R_MSK	(0x3 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT)
++#define RK3308_DAC_HPOUT_POP_SOUND_R_WORK	(0x2 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT)
++#define RK3308_DAC_HPOUT_POP_SOUND_R_INIT	(0x1 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT)
+ #define RK3308_DAC_BUF_REF_L_MSK		(0x1 << 2)
+ #define RK3308_DAC_BUF_REF_L_EN			(0x1 << 2)
+ #define RK3308_DAC_BUF_REF_L_DIS		(0x0 << 2)
+-#define RK3308_DAC_POP_SOUND_L_SFT		0
+-#define RK3308_DAC_POP_SOUND_L_MSK		(0x3 << RK3308_DAC_POP_SOUND_L_SFT)
+-#define RK3308_DAC_POP_SOUND_L_WORK		(0x2 << RK3308_DAC_POP_SOUND_L_SFT)
+-#define RK3308_DAC_POP_SOUND_L_INIT		(0x1 << RK3308_DAC_POP_SOUND_L_SFT)
++#define RK3308_DAC_HPOUT_POP_SOUND_L_SFT	0
++#define RK3308_DAC_HPOUT_POP_SOUND_L_MSK	(0x3 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT)
++#define RK3308_DAC_HPOUT_POP_SOUND_L_WORK	(0x2 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT)
++#define RK3308_DAC_HPOUT_POP_SOUND_L_INIT	(0x1 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT)
+ 
+ /* RK3308_DAC_ANA_CON02 - REG: 0x0448 */
+ #define RK3308_DAC_R_DAC_WORK			(0x1 << 7)
+@@ -828,28 +893,31 @@
+ #define RK3308_DAC_L_HPOUT_MUTE			(0x0 << 0)
+ 
+ /* RK3308_DAC_ANA_CON04 - REG: 0x0450 */
+-#define RK3308_DAC_R_GAIN_SFT			6
+-#define RK3308_DAC_R_GAIN_MSK			(0x3 << RK3308_DAC_R_GAIN_SFT)
+-#define RK3308_DAC_R_GAIN_0DB			(0x3 << RK3308_DAC_R_GAIN_SFT)
+-#define RK3308_DAC_R_GAIN_PDB_1_5		(0x2 << RK3308_DAC_R_GAIN_SFT)
+-#define RK3308_DAC_R_GAIN_PDB_3			(0x1 << RK3308_DAC_R_GAIN_SFT)
+-#define RK3308_DAC_R_GAIN_PDB_6			(0x0 << RK3308_DAC_R_GAIN_SFT)
++#define RK3308_DAC_R_LINEOUT_GAIN_MAX		0x3
++#define RK3308_DAC_R_LINEOUT_GAIN_SFT		6
++#define RK3308_DAC_R_LINEOUT_GAIN_MSK		(0x3 << RK3308_DAC_R_LINEOUT_GAIN_SFT)
++#define RK3308_DAC_R_LINEOUT_GAIN_0DB		(0x3 << RK3308_DAC_R_LINEOUT_GAIN_SFT)
++#define RK3308_DAC_R_LINEOUT_GAIN_NDB_1_5	(0x2 << RK3308_DAC_R_LINEOUT_GAIN_SFT)
++#define RK3308_DAC_R_LINEOUT_GAIN_NDB_3		(0x1 << RK3308_DAC_R_LINEOUT_GAIN_SFT)
++#define RK3308_DAC_R_LINEOUT_GAIN_NDB_6		(0x0 << RK3308_DAC_R_LINEOUT_GAIN_SFT)
+ #define RK3308_DAC_R_LINEOUT_UNMUTE		(0x1 << 5)
+ #define RK3308_DAC_R_LINEOUT_MUTE		(0x0 << 5)
+ #define RK3308_DAC_R_LINEOUT_EN			(0x1 << 4)
+ #define RK3308_DAC_R_LINEOUT_DIS		(0x0 << 4)
+-#define RK3308_DAC_L_GAIN_SFT			2
+-#define RK3308_DAC_L_GAIN_MSK			(0x3 << RK3308_DAC_L_GAIN_SFT)
+-#define RK3308_DAC_L_GAIN_0DB			(0x3 << RK3308_DAC_L_GAIN_SFT)
+-#define RK3308_DAC_L_GAIN_PDB_1_5		(0x2 << RK3308_DAC_L_GAIN_SFT)
+-#define RK3308_DAC_L_GAIN_PDB_3			(0x1 << RK3308_DAC_L_GAIN_SFT)
+-#define RK3308_DAC_L_GAIN_PDB_6			(0x0 << RK3308_DAC_L_GAIN_SFT)
++#define RK3308_DAC_L_LINEOUT_GAIN_MAX		0x3
++#define RK3308_DAC_L_LINEOUT_GAIN_SFT		2
++#define RK3308_DAC_L_LINEOUT_GAIN_MSK		(0x3 << RK3308_DAC_L_LINEOUT_GAIN_SFT)
++#define RK3308_DAC_L_LINEOUT_GAIN_0DB		(0x3 << RK3308_DAC_L_LINEOUT_GAIN_SFT)
++#define RK3308_DAC_L_LINEOUT_GAIN_NDB_1_5	(0x2 << RK3308_DAC_L_LINEOUT_GAIN_SFT)
++#define RK3308_DAC_L_LINEOUT_GAIN_NDB_3		(0x1 << RK3308_DAC_L_LINEOUT_GAIN_SFT)
++#define RK3308_DAC_L_LINEOUT_GAIN_NDB_6		(0x0 << RK3308_DAC_L_LINEOUT_GAIN_SFT)
+ #define RK3308_DAC_L_LINEOUT_UNMUTE		(0x1 << 1)
+ #define RK3308_DAC_L_LINEOUT_MUTE		(0x0 << 1)
+ #define RK3308_DAC_L_LINEOUT_EN			(0x1 << 0)
+ #define RK3308_DAC_L_LINEOUT_DIS		(0x0 << 0)
+ 
+ /* RK3308_DAC_ANA_CON05 - REG: 0x0454, step is 1.5db */
++#define RK3308_DAC_L_HPOUT_GAIN_MAX		0x1e
+ #define RK3308_DAC_L_HPOUT_GAIN_SFT		0
+ #define RK3308_DAC_L_HPOUT_GAIN_MSK		(0x1f << RK3308_DAC_L_HPOUT_GAIN_SFT)
+ #define RK3308_DAC_L_HPOUT_GAIN_PDB_6		(0x1e << RK3308_DAC_L_HPOUT_GAIN_SFT)
+@@ -885,6 +953,7 @@
+ #define RK3308_DAC_L_HPOUT_GAIN_NDB_39		(0x00 << RK3308_DAC_L_HPOUT_GAIN_SFT)
+ 
+ /* RK3308_DAC_ANA_CON06 - REG: 0x0458, step is 1.5db */
++#define RK3308_DAC_R_HPOUT_GAIN_MAX		0x1e
+ #define RK3308_DAC_R_HPOUT_GAIN_SFT		0
+ #define RK3308_DAC_R_HPOUT_GAIN_MSK		(0x1f << RK3308_DAC_R_HPOUT_GAIN_SFT)
+ #define RK3308_DAC_R_HPOUT_GAIN_PDB_6		(0x1e << RK3308_DAC_R_HPOUT_GAIN_SFT)
+@@ -919,6 +988,18 @@
+ #define RK3308_DAC_R_HPOUT_GAIN_NDB_37_5	(0x01 << RK3308_DAC_R_HPOUT_GAIN_SFT)
+ #define RK3308_DAC_R_HPOUT_GAIN_NDB_39		(0x00 << RK3308_DAC_R_HPOUT_GAIN_SFT)
+ 
++/* RK3308_DAC_ANA_CON07 - REG: 0x045c */
++#define RK3308_DAC_R_HPOUT_DRV_SFT		4
++#define RK3308_DAC_R_HPOUT_DRV_MSK		(0xf << RK3308_DAC_R_HPOUT_DRV_SFT)
++#define RK3308_DAC_L_HPOUT_DRV_SFT		0
++#define RK3308_DAC_L_HPOUT_DRV_MSK		(0xf << RK3308_DAC_L_HPOUT_DRV_SFT)
++
++/* RK3308_DAC_ANA_CON08 - REG: 0x0460 */
++#define RK3308_DAC_R_LINEOUT_DRV_SFT		4
++#define RK3308_DAC_R_LINEOUT_DRV_MSK		(0xf << RK3308_DAC_R_LINEOUT_DRV_SFT)
++#define RK3308_DAC_L_LINEOUT_DRV_SFT		0
++#define RK3308_DAC_L_LINEOUT_DRV_MSK		(0xf << RK3308_DAC_L_LINEOUT_DRV_SFT)
++
+ /* RK3308_DAC_ANA_CON12 - REG: 0x0470 */
+ #define RK3308_DAC_R_HPMIX_SEL_SFT		6
+ #define RK3308_DAC_R_HPMIX_SEL_MSK		(0x3 << RK3308_DAC_R_HPMIX_SEL_SFT)
+@@ -926,6 +1007,8 @@
+ #define RK3308_DAC_R_HPMIX_LINEIN		(0x2 << RK3308_DAC_R_HPMIX_SEL_SFT)
+ #define RK3308_DAC_R_HPMIX_I2S			(0x1 << RK3308_DAC_R_HPMIX_SEL_SFT)
+ #define RK3308_DAC_R_HPMIX_NONE			(0x0 << RK3308_DAC_R_HPMIX_SEL_SFT)
++#define RK3308_DAC_R_HPMIX_GAIN_MIN		0x1
++#define RK3308_DAC_R_HPMIX_GAIN_MAX		0x2
+ #define RK3308_DAC_R_HPMIX_GAIN_SFT		4
+ #define RK3308_DAC_R_HPMIX_GAIN_MSK		(0x3 << RK3308_DAC_R_HPMIX_GAIN_SFT)
+ #define RK3308_DAC_R_HPMIX_GAIN_0DB		(0x2 << RK3308_DAC_R_HPMIX_GAIN_SFT)
+@@ -936,6 +1019,8 @@
+ #define RK3308_DAC_L_HPMIX_LINEIN		(0x2 << RK3308_DAC_L_HPMIX_SEL_SFT)
+ #define RK3308_DAC_L_HPMIX_I2S			(0x1 << RK3308_DAC_L_HPMIX_SEL_SFT)
+ #define RK3308_DAC_L_HPMIX_NONE			(0x0 << RK3308_DAC_L_HPMIX_SEL_SFT)
++#define RK3308_DAC_L_HPMIX_GAIN_MIN		0x1
++#define RK3308_DAC_L_HPMIX_GAIN_MAX		0x2
+ #define RK3308_DAC_L_HPMIX_GAIN_SFT		0
+ #define RK3308_DAC_L_HPMIX_GAIN_MSK		(0x3 << RK3308_DAC_L_HPMIX_GAIN_SFT)
+ #define RK3308_DAC_L_HPMIX_GAIN_0DB		(0x2 << RK3308_DAC_L_HPMIX_GAIN_SFT)
+@@ -955,6 +1040,30 @@
+ #define RK3308_DAC_L_HPMIX_EN			(0x1 << 0)
+ #define RK3308_DAC_L_HPMIX_DIS			(0x0 << 0)
+ 
++/* RK3308_DAC_ANA_CON14 - REG: 0x0478 */
++#define RK3308_DAC_VCM_LINEOUT_EN		(0x1 << 4)
++#define RK3308_DAC_VCM_LINEOUT_DIS		(0x0 << 4)
++#define RK3308_DAC_CURRENT_CHARGE_SFT		0
++#define RK3308_DAC_CURRENT_CHARGE_MSK		(0xf << RK3308_DAC_CURRENT_CHARGE_SFT)
++
++/*
++ * 1: Choose the current I
++ * 0: Don't choose the current I
++ */
++#define RK3308_DAC_SEL_I(x)			(x & 0xf)
++
++/* RK3308_DAC_ANA_CON15 - REG: 0x047C */
++#define RK3308_DAC_LINEOUT_POP_SOUND_R_SFT	4
++#define RK3308_DAC_LINEOUT_POP_SOUND_R_MSK	(0x3 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT)
++#define RK3308_DAC_R_SEL_DC_FROM_INTERNAL	(0x2 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT)
++#define RK3308_DAC_R_SEL_DC_FROM_VCM		(0x1 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT)
++#define RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL	(0x0 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT)
++#define RK3308_DAC_LINEOUT_POP_SOUND_L_SFT	0
++#define RK3308_DAC_LINEOUT_POP_SOUND_L_MSK	(0x3 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT)
++#define RK3308_DAC_L_SEL_DC_FROM_INTERNAL	(0x2 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT)
++#define RK3308_DAC_L_SEL_DC_FROM_VCM		(0x1 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT)
++#define RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL	(0x0 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT)
++
+ #define RK3308_HIFI				0x0
+ 
+ #endif /* __RK3308_CODEC_H__ */
+diff --git a/sound/soc/codecs/rk3308_codec_provider.h b/sound/soc/codecs/rk3308_codec_provider.h
+new file mode 100644
+index 000000000000..68042b1328dc
+--- /dev/null
++++ b/sound/soc/codecs/rk3308_codec_provider.h
+@@ -0,0 +1,28 @@
++/*
++ * rk3308_codec_provider.h -- RK3308 ALSA Soc Audio Driver
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++#ifndef __RK3308_CODEC_PROVIDER_H__
++#define __RK3308_CODEC_PROVIDER_H__
++
++#ifdef CONFIG_SND_SOC_RK3308
++extern void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_codec *codec,
++					       struct snd_soc_jack *hpdet_jack);
++#endif
++
++#endif /* __RK3308_CODEC_PROVIDER_H__ */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch.disabled b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch.disabled
new file mode 100644
index 000000000000..821e69964ccd
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch.disabled
@@ -0,0 +1,50 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ashthespy <ashthespy@gmail.com>
+Date: Mon, 3 Feb 2020 17:19:33 +0100
+Subject: arm64: dts: rockchip: Add acodec node for rk3308
+
+Change-Id: I76f4a877711d33620bdef295e9047bdba26d4da4
+Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 18 +++++++++-
+ 1 file changed, 17 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+index 291f011800b2..dd221ee88722 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -548,7 +548,7 @@ rk_timer_rtc: rk-timer-rtc@ff1a0020 {
+ 		clock-names = "pclk", "timer";
+ 		status = "disabled";
+ 	};
+-		
++
+ 	saradc: saradc@ff1e0000 {
+ 		compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
+ 		reg = <0x0 0xff1e0000 0x0 0x100>;
+@@ -933,6 +933,22 @@ cru: clock-controller@ff500000 {
+ 		assigned-clock-rates = <32768>;
+ 	};
+ 
++	acodec: acodec@ff560000 {
++		compatible = "rockchip,rk3308-codec";
++		reg = <0x0 0xff560000 0x0 0x10000>;
++		rockchip,grf = <&grf>;
++		rockchip,detect-grf = <&detect_grf>;
++		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
++				 			   <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru PCLK_ACODEC>,
++			 			 <&cru SCLK_I2S2_8CH_TX_OUT>,
++			 		 	 <&cru SCLK_I2S2_8CH_RX_OUT>;
++		clock-names = "acodec", "mclk_tx", "mclk_rx";
++		resets = <&cru SRST_ACODEC_P>;
++		reset-names = "acodec-reset";
++		status = "disabled";
++};
++
+ 	gic: interrupt-controller@ff580000 {
+ 		compatible = "arm,gic-400";
+ 		reg = <0x0 0xff581000 0x0 0x1000>,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch.disabled b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch.disabled
new file mode 100644
index 000000000000..5855cf80a551
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch.disabled
@@ -0,0 +1,459 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ashthespy <ashthespy@gmail.com>
+Date: Mon, 3 Feb 2020 19:35:42 +0100
+Subject: ASoC: rk3308_codec: replace codec to component
+
+---
+ sound/soc/codecs/rk3308_codec.c          | 159 +++++-----
+ sound/soc/codecs/rk3308_codec_provider.h |   2 +-
+ 2 files changed, 84 insertions(+), 77 deletions(-)
+
+diff --git a/sound/soc/codecs/rk3308_codec.c b/sound/soc/codecs/rk3308_codec.c
+index 815e22fc346c..b6862fc5a3da 100644
+--- a/sound/soc/codecs/rk3308_codec.c
++++ b/sound/soc/codecs/rk3308_codec.c
+@@ -31,7 +31,7 @@
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+ #include <linux/reset.h>
+-#include <linux/rockchip/grf.h>
++// #include <linux/rockchip/grf.h>
+ #include <linux/version.h>
+ #include <sound/core.h>
+ #include <sound/dmaengine_pcm.h>
+@@ -156,7 +156,7 @@ struct rk3308_codec_priv {
+ 	struct gpio_desc *hp_ctl_gpio;
+ 	struct gpio_desc *spk_ctl_gpio;
+ 	struct gpio_desc *pa_drv_gpio;
+-	struct snd_soc_codec *codec;
++	struct snd_soc_component *component;
+ 	struct snd_soc_jack *hpdet_jack;
+ 	struct regulator *vcc_micbias;
+ 	u32 codec_ver;
+@@ -883,8 +883,8 @@ static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = {
+ static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol,
+ 				struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ 
+ 	if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
+@@ -904,8 +904,8 @@ static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol,
+ 				struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ 	unsigned int value = ucontrol->value.integer.value[0];
+ 	int grp = e->reg;
+@@ -970,8 +970,8 @@ static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol,
+ 				    struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ 	unsigned int value;
+ 	int grp = e->reg;
+@@ -998,8 +998,8 @@ static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol,
+ 				    struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ 	unsigned int value;
+ 	int grp = e->reg;
+@@ -1032,8 +1032,8 @@ static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol,
+ 				     struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ 	unsigned int value;
+ 	int grp = e->reg;
+@@ -1064,8 +1064,8 @@ static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol,
+ 				     struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ 	unsigned int value;
+ 	int grp = e->reg;
+@@ -1098,8 +1098,8 @@ static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol,
+ 					  struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 
+ 	ucontrol->value.integer.value[0] = rk3308->micbias_volt;
+ 
+@@ -1109,8 +1109,8 @@ static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol,
+ 					  struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	unsigned int volt = ucontrol->value.integer.value[0];
+ 	int ret;
+ 
+@@ -1133,8 +1133,8 @@ static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol,
+ 					 struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 
+ 	ucontrol->value.integer.value[0] = rk3308->enable_micbias;
+ 
+@@ -1144,8 +1144,8 @@ static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_main_micbias_put(struct snd_kcontrol *kcontrol,
+ 					 struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	unsigned int on = ucontrol->value.integer.value[0];
+ 
+ 	if (on) {
+@@ -1168,8 +1168,8 @@ static int rk3308_codec_mic_gain_get(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol,
+ 				     struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	unsigned int gain = ucontrol->value.integer.value[0];
+ 
+ 	if (gain > RK3308_ADC_CH1_MIC_GAIN_MAX) {
+@@ -1197,8 +1197,8 @@ static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol,
+ 				struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ 	unsigned int value;
+ 
+@@ -1222,8 +1222,8 @@ static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol,
+ 				struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ 	unsigned int value = ucontrol->value.integer.value[0];
+ 
+@@ -1259,8 +1259,8 @@ static int rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol *kcontrol,
+ 					struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	unsigned int dgain = ucontrol->value.integer.value[0];
+ 
+ 	if (dgain > RK3308_DAC_L_HPOUT_GAIN_MAX) {
+@@ -1283,8 +1283,8 @@ static int rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol *kcontrol,
+ static int rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol *kcontrol,
+ 					struct snd_ctl_elem_value *ucontrol)
+ {
+-	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	unsigned int dgain = ucontrol->value.integer.value[0];
+ 
+ 	if (dgain > RK3308_DAC_R_HPOUT_GAIN_MAX) {
+@@ -1408,9 +1408,9 @@ static void rk3308_speaker_ctl(struct rk3308_codec_priv *rk3308, int on)
+ 	}
+ }
+ 
+-static int rk3308_codec_reset(struct snd_soc_codec *codec)
++static int rk3308_codec_reset(struct snd_soc_component *component)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 
+ 	reset_control_assert(rk3308->reset);
+ 	usleep_range(2000, 2500);	/* estimated value */
+@@ -1452,10 +1452,10 @@ static int rk3308_codec_dac_dig_reset(struct rk3308_codec_priv *rk3308)
+ 	return 0;
+ }
+ 
+-static int rk3308_set_bias_level(struct snd_soc_codec *codec,
++static int rk3308_set_bias_level(struct snd_soc_component *component,
+ 				 enum snd_soc_bias_level level)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 
+ 	switch (level) {
+ 	case SND_SOC_BIAS_ON:
+@@ -1473,11 +1473,11 @@ static int rk3308_set_bias_level(struct snd_soc_codec *codec,
+ 	return 0;
+ }
+ 
+-static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai,
++static int rk3308_set_dai_fmt(struct snd_soc_dai *dai,
+ 			      unsigned int fmt)
+ {
+-	struct snd_soc_codec *codec = codec_dai->codec;
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = dai->component;
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0;
+ 	int idx, grp, is_master;
+ 	int type = ADC_TYPE_ALL;
+@@ -1721,8 +1721,8 @@ static int rk3308_codec_update_adc_grps(struct rk3308_codec_priv *rk3308,
+ 
+ static int rk3308_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
+ {
+-	struct snd_soc_codec *codec = dai->codec;
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = dai->component;
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 
+ 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ 		int dgain;
+@@ -3630,8 +3630,8 @@ static int rk3308_hw_params(struct snd_pcm_substream *substream,
+ 			    struct snd_pcm_hw_params *params,
+ 			    struct snd_soc_dai *dai)
+ {
+-	struct snd_soc_codec *codec = dai->codec;
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = dai->component;
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	struct snd_pcm_str *playback_str =
+ 			&substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
+ 	int type = ADC_TYPE_LOOPBACK;
+@@ -3705,8 +3705,8 @@ static int rk3308_hw_params(struct snd_pcm_substream *substream,
+ static int rk3308_pcm_trigger(struct snd_pcm_substream *substream,
+ 			      int cmd, struct snd_soc_dai *dai)
+ {
+-	struct snd_soc_codec *codec = dai->codec;
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = dai->component;
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	int type = ADC_TYPE_LOOPBACK;
+ 	int idx, grp;
+ 
+@@ -3749,8 +3749,8 @@ static int rk3308_pcm_trigger(struct snd_pcm_substream *substream,
+ static void rk3308_pcm_shutdown(struct snd_pcm_substream *substream,
+ 				struct snd_soc_dai *dai)
+ {
+-	struct snd_soc_codec *codec = dai->codec;
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct snd_soc_component *component = dai->component;
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 
+ 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ 		rk3308_codec_close_playback(rk3308);
+@@ -3809,9 +3809,9 @@ static struct snd_soc_dai_driver rk3308_dai[] = {
+ 	},
+ };
+ 
+-static int rk3308_suspend(struct snd_soc_codec *codec)
++static int rk3308_suspend(struct snd_soc_component *component)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 
+ 	if (rk3308->no_deep_low_power)
+ 		goto out;
+@@ -3822,13 +3822,13 @@ static int rk3308_suspend(struct snd_soc_codec *codec)
+ 	clk_disable_unprepare(rk3308->pclk);
+ 
+ out:
+-	rk3308_set_bias_level(codec, SND_SOC_BIAS_OFF);
++	rk3308_set_bias_level(component, SND_SOC_BIAS_OFF);
+ 	return 0;
+ }
+ 
+-static int rk3308_resume(struct snd_soc_codec *codec)
++static int rk3308_resume(struct snd_soc_component *component)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	int ret = 0;
+ 
+ 	if (rk3308->no_deep_low_power)
+@@ -3857,7 +3857,7 @@ static int rk3308_resume(struct snd_soc_codec *codec)
+ 
+ 	rk3308_codec_dlp_up(rk3308);
+ out:
+-	rk3308_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++	rk3308_set_bias_level(component, SND_SOC_BIAS_STANDBY);
+ 	return ret;
+ }
+ 
+@@ -3972,7 +3972,7 @@ static int rk3308_codec_dapm_mic_gains(struct rk3308_codec_priv *rk3308)
+ 	int ret;
+ 
+ 	if (rk3308->codec_ver == ACODEC_VERSION_B) {
+-		ret = snd_soc_add_codec_controls(rk3308->codec,
++		ret = snd_soc_add_component_controls(rk3308->component,
+ 						 mic_gains_b,
+ 						 ARRAY_SIZE(mic_gains_b));
+ 		if (ret) {
+@@ -3982,7 +3982,7 @@ static int rk3308_codec_dapm_mic_gains(struct rk3308_codec_priv *rk3308)
+ 			return ret;
+ 		}
+ 	} else {
+-		ret = snd_soc_add_codec_controls(rk3308->codec,
++		ret = snd_soc_add_component_controls(rk3308->component,
+ 						 mic_gains_a,
+ 						 ARRAY_SIZE(mic_gains_a));
+ 		if (ret) {
+@@ -4081,15 +4081,15 @@ static int rk3308_codec_prepare(struct rk3308_codec_priv *rk3308)
+ 	return 0;
+ }
+ 
+-static int rk3308_probe(struct snd_soc_codec *codec)
++static int rk3308_probe(struct snd_soc_component *component)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 	int ext_micbias;
+ 
+-	rk3308->codec = codec;
++	rk3308->component = component;
+ 	rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE);
+ 
+-	rk3308_codec_reset(codec);
++	rk3308_codec_reset(component);
+ 	rk3308_codec_power_on(rk3308);
+ 
+ 	/* From vendor recommend, disable micbias at first. */
+@@ -4108,9 +4108,9 @@ static int rk3308_probe(struct snd_soc_codec *codec)
+ 	return 0;
+ }
+ 
+-static int rk3308_remove(struct snd_soc_codec *codec)
++static void rk3308_remove(struct snd_soc_component *component)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 
+ 	rk3308_headphone_ctl(rk3308, 0);
+ 	rk3308_speaker_ctl(rk3308, 0);
+@@ -4124,17 +4124,25 @@ static int rk3308_remove(struct snd_soc_codec *codec)
+ 	regcache_cache_only(rk3308->regmap, false);
+ 	regcache_sync(rk3308->regmap);
+ 
+-	return 0;
+ }
+ 
+-static struct snd_soc_codec_driver soc_codec_dev_rk3308 = {
+-	.probe = rk3308_probe,
+-	.remove = rk3308_remove,
+-	.suspend = rk3308_suspend,
+-	.resume = rk3308_resume,
+-	.set_bias_level = rk3308_set_bias_level,
+-	.controls = rk3308_codec_dapm_controls,
+-	.num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls),
++static const struct snd_soc_component_driver soc_codec_dev_rk3308_component = {
++	.probe					= rk3308_probe,
++	.remove					= rk3308_remove,
++	.resume         = rk3308_resume,
++	.suspend        = rk3308_suspend,
++	.set_bias_level	= rk3308_set_bias_level,
++	.controls				= rk3308_codec_dapm_controls,
++	.num_controls		= ARRAY_SIZE(rk3308_codec_dapm_controls),
++	// .dapm_widgets		= rk3308_dapm_widgets,
++	// .num_dapm_widgets	= ARRAY_SIZE(rk3308_dapm_widgets),
++	// .dapm_routes		= rk3308_dapm_routes,
++	// .num_dapm_routes	= ARRAY_SIZE(rk3308_dapm_routes),
++	// .suspend_bias_off	= 1,
++	// .idle_bias_on		= 1,
++	// .use_pmdown_time	= 1,
++	.endianness		= 1,
++	.legacy_dai_naming	= 1,
+ };
+ 
+ static const struct reg_default rk3308_codec_reg_defaults[] = {
+@@ -4299,14 +4307,14 @@ static irqreturn_t rk3308_codec_hpdet_isr(int irq, void *data)
+ 	return IRQ_HANDLED;
+ }
+ 
+-void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_codec *codec,
++void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_component *component,
+ 					struct snd_soc_jack *hpdet_jack);
+ EXPORT_SYMBOL_GPL(rk3308_codec_set_jack_detect_cb);
+ 
+-static void rk3308_codec_set_jack_detect(struct snd_soc_codec *codec,
++static void rk3308_codec_set_jack_detect(struct snd_soc_component *component,
+ 				  struct snd_soc_jack *hpdet_jack)
+ {
+-	struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec);
++	struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
+ 
+ 	rk3308->hpdet_jack = hpdet_jack;
+ 
+@@ -5114,10 +5122,10 @@ static int rk3308_platform_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, rk3308);
+ 
+-	ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_rk3308,
++	ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk3308_component,
+ 				     rk3308_dai, ARRAY_SIZE(rk3308_dai));
+ 	if (ret < 0) {
+-		dev_err(&pdev->dev, "Failed to register codec: %d\n", ret);
++		dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
+ 		goto failed;
+ 	}
+ 
+@@ -5140,7 +5148,6 @@ static int rk3308_platform_remove(struct platform_device *pdev)
+ 	clk_disable_unprepare(rk3308->mclk_rx);
+ 	clk_disable_unprepare(rk3308->mclk_tx);
+ 	clk_disable_unprepare(rk3308->pclk);
+-	snd_soc_unregister_codec(&pdev->dev);
+ 	device_unregister(&rk3308->dev);
+ 
+ 	return 0;
+diff --git a/sound/soc/codecs/rk3308_codec_provider.h b/sound/soc/codecs/rk3308_codec_provider.h
+index 68042b1328dc..34c1ef86a507 100644
+--- a/sound/soc/codecs/rk3308_codec_provider.h
++++ b/sound/soc/codecs/rk3308_codec_provider.h
+@@ -21,7 +21,7 @@
+ #define __RK3308_CODEC_PROVIDER_H__
+ 
+ #ifdef CONFIG_SND_SOC_RK3308
+-extern void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_codec *codec,
++extern void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_component *component,
+ 					       struct snd_soc_jack *hpdet_jack);
+ #endif
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0027-arm64-dts-rk3308-add-otp-cpuinfo.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0027-arm64-dts-rk3308-add-otp-cpuinfo.patch
new file mode 100644
index 000000000000..f11c766eb4e2
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0027-arm64-dts-rk3308-add-otp-cpuinfo.patch
@@ -0,0 +1,115 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+Date: Wed, 8 Sep 2021 17:51:34 +0200
+Subject: [ARCHEOLOGY] Bumping EDGE kernel to 5.14.y (#3125)
+
+> X-Git-Archeology: > recovered message: > * Bumping EDGE kernel to 5.14.y
+> X-Git-Archeology: > recovered message: > Meson64:
+> X-Git-Archeology: > recovered message: > - removing Odroid reboot shutdown patch since its probably not needed anymore
+> X-Git-Archeology: > recovered message: > Rockchip64:
+> X-Git-Archeology: > recovered message: > - removing Rockpi S. No interest to maintain this any further
+> X-Git-Archeology: > recovered message: > - removing PBP suspend. Doesn't align. Need inspection if some other way was mainstreamed
+> X-Git-Archeology: > recovered message: > - temporally removing Orangepi R1
+> X-Git-Archeology: > recovered message: > * Re-adding rockpis, pbp suspend, HFLPS170 wifi and cleanup
+> X-Git-Archeology: > recovered message: > * Removing deprecated patch, fixing ap6256 wifi
+> X-Git-Archeology: > recovered message: > * Re-enable Opi R1 plus, untest
+> X-Git-Archeology: > recovered message: > * Add and fix Radxa Zero
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 29 ++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+index dd221ee88722..5f48dcee7548 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -138,6 +138,12 @@ arm-pmu {
+ 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ 	};
+ 
++	cpuinfo {
++		compatible = "rockchip,cpuinfo";
++		nvmem-cells = <&cpu_id>;
++		nvmem-cell-names = "id";
++	};
++
+ 	mac_clkin: external-mac-clock {
+ 		compatible = "fixed-clock";
+ 		clock-frequency = <50000000>;
+@@ -145,6 +151,29 @@ mac_clkin: external-mac-clock {
+ 		#clock-cells = <0>;
+ 	};
+ 
++	otp: otp@ff210000 {
++		compatible = "rockchip,rk3308-otp";
++		reg = <0x0 0xff210000 0x0 0x4000>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
++			 <&cru PCLK_OTP_PHY>;
++		clock-names = "otp", "apb_pclk", "phy";
++		resets = <&cru SRST_OTP_PHY>;
++		reset-names = "phy";
++
++		/* Data cells */
++		cpu_id: id@7 {
++			reg = <0x07 0x10>;
++		};
++		cpu_leakage: cpu-leakage@17 {
++			reg = <0x17 0x1>;
++		};
++		logic_leakage: logic-leakage@18 {
++			reg = <0x18 0x1>;
++		};
++	};
++
+ 	psci {
+ 		compatible = "arm,psci-1.0";
+ 		method = "smc";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpis-0029-arm64-dts-rk3308-add-reserved-memory-ramoops.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0029-arm64-dts-rk3308-add-reserved-memory-ramoops.patch
new file mode 100644
index 000000000000..e64c536bc09a
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpis-0029-arm64-dts-rk3308-add-reserved-memory-ramoops.patch
@@ -0,0 +1,99 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+Date: Wed, 8 Sep 2021 17:51:34 +0200
+Subject: [ARCHEOLOGY] Bumping EDGE kernel to 5.14.y (#3125)
+
+> X-Git-Archeology: > recovered message: > * Bumping EDGE kernel to 5.14.y
+> X-Git-Archeology: > recovered message: > Meson64:
+> X-Git-Archeology: > recovered message: > - removing Odroid reboot shutdown patch since its probably not needed anymore
+> X-Git-Archeology: > recovered message: > Rockchip64:
+> X-Git-Archeology: > recovered message: > - removing Rockpi S. No interest to maintain this any further
+> X-Git-Archeology: > recovered message: > - removing PBP suspend. Doesn't align. Need inspection if some other way was mainstreamed
+> X-Git-Archeology: > recovered message: > - temporally removing Orangepi R1
+> X-Git-Archeology: > recovered message: > * Re-adding rockpis, pbp suspend, HFLPS170 wifi and cleanup
+> X-Git-Archeology: > recovered message: > * Removing deprecated patch, fixing ap6256 wifi
+> X-Git-Archeology: > recovered message: > * Re-enable Opi R1 plus, untest
+> X-Git-Archeology: > recovered message: > * Add and fix Radxa Zero
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 20 ++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+index 5f48dcee7548..c5fe355c6deb 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -179,6 +179,26 @@ psci {
+ 		method = "smc";
+ 	};
+ 
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		drm_logo: drm-logo@00000000 {
++			compatible = "rockchip,drm-logo";
++			reg = <0x0 0x0 0x0 0x0>;
++		};
++
++		ramoops: ramoops@110000 {
++			compatible = "ramoops";
++			reg = <0x0 0x110000 0x0 0xf0000>;
++			record-size = <0x30000>;
++			console-size = <0xc0000>;
++			ftrace-size = <0x00000>;
++			pmsg-size = <0x00000>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch
new file mode 100644
index 000000000000..42c9ba693774
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch
@@ -0,0 +1,64 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Piotr Szczepanik <piter75@gmail.com>
+Date: Mon, 24 Aug 2020 22:47:03 +0200
+Subject: Rockpro64 add pcie bus scan delay
+
+> X-Git-Archeology: - Revision 42e76b9277ad492e935cc76c2b37c9f6d882a675: https://github.com/armbian/build/commit/42e76b9277ad492e935cc76c2b37c9f6d882a675
+> X-Git-Archeology:   Date: Mon, 24 Aug 2020 22:47:03 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch RockPro64 work led to heartbeat trigger
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5: https://github.com/armbian/build/commit/4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5
+> X-Git-Archeology:   Date: Wed, 02 Sep 2020 23:22:09 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switched rockchip64 curent to kernel 5.8.y (#2175)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 7be9e8b99590e32c0594365d00a2a2cfc3c4bd5a: https://github.com/armbian/build/commit/7be9e8b99590e32c0594365d00a2a2cfc3c4bd5a
+> X-Git-Archeology:   Date: Thu, 16 Dec 2021 05:17:33 -0500
+> X-Git-Archeology:   From: Dan Pasanen <dan.pasanen@gmail.com>
+> X-Git-Archeology:   Subject: rockchip-[current,edge]: add pcie hack and lsi scsi/sas support (#3351)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 588c2ec17e709dec19304fa50522459702ebfadd: https://github.com/armbian/build/commit/588c2ec17e709dec19304fa50522459702ebfadd
+> X-Git-Archeology:   Date: Fri, 23 Dec 2022 21:57:53 +0100
+> X-Git-Archeology:   From: brentr <brent@mbari.org>
+> X-Git-Archeology:   Subject: Rockpis devtree mainlined (#4603)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+index bca2b50e0a93..1e7295215b58 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+@@ -663,6 +663,7 @@ &pcie0 {
+ 	pinctrl-0 = <&pcie_perst>;
+ 	vpcie12v-supply = <&vcc12v_dcin>;
+ 	vpcie3v3-supply = <&vcc3v3_pcie>;
++	bus-scan-delay-ms = <1000>;
+ 	status = "okay";
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpro64-change-rx_delay-for-gmac.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpro64-change-rx_delay-for-gmac.patch
new file mode 100644
index 000000000000..4e7ed60cfbef
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpro64-change-rx_delay-for-gmac.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ayufan <ayufan@ayufan.eu>
+Date: Sun, 30 Dec 2018 13:32:47 +0100
+Subject: ayufan: dts: rockpro64: change rx_delay for gmac
+
+Change-Id: Ib3899f684188aa1ed1545717af004bba53fe0e07
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+index 1e7295215b58..25ee84e06874 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+@@ -307,7 +307,7 @@ &gmac {
+ 	snps,reset-active-low;
+ 	snps,reset-delays-us = <0 10000 50000>;
+ 	tx_delay = <0x28>;
+-	rx_delay = <0x11>;
++	rx_delay = <0x20>;
+ 	status = "okay";
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpro64-fix-emmc.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpro64-fix-emmc.patch
new file mode 100644
index 000000000000..7aeb8dc4fac6
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpro64-fix-emmc.patch
@@ -0,0 +1,123 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Ayotte <martinayotte@yahoo.ca>
+Date: Wed, 5 Dec 2018 14:09:24 -0500
+Subject: [ARCHEOLOGY] fix PMIC_INT_L gpio conflicting with I2C8_SCL in
+ RockPro64
+
+> X-Git-Archeology: - Revision 9324bde9b94db6c2f43ff1e75bedb74fbe6e29a1: https://github.com/armbian/build/commit/9324bde9b94db6c2f43ff1e75bedb74fbe6e29a1
+> X-Git-Archeology:   Date: Wed, 05 Dec 2018 14:09:24 -0500
+> X-Git-Archeology:   From: Martin Ayotte <martinayotte@yahoo.ca>
+> X-Git-Archeology:   Subject: fix PMIC_INT_L gpio conflicting with I2C8_SCL in RockPro64
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8f82cb60b958ad235ee91899ab2ca8e4a8a2a33b: https://github.com/armbian/build/commit/8f82cb60b958ad235ee91899ab2ca8e4a8a2a33b
+> X-Git-Archeology:   Date: Mon, 31 Dec 2018 12:29:56 -0500
+> X-Git-Archeology:   From: Martin Ayotte <martinayotte@yahoo.ca>
+> X-Git-Archeology:   Subject: set lower speed for RockPro64 eMMC
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision cbbbf0631969bf0e4578f4b1eef62c1aab115d79: https://github.com/armbian/build/commit/cbbbf0631969bf0e4578f4b1eef62c1aab115d79
+> X-Git-Archeology:   Date: Tue, 01 Jan 2019 19:37:27 -0500
+> X-Git-Archeology:   From: Martin Ayotte <martinayotte@yahoo.ca>
+> X-Git-Archeology:   Subject: fix RockPi-4B naming + fix vcc5v0_host gpio pin
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision a186fd498404fdae7d3a25dec64f014c590027d6: https://github.com/armbian/build/commit/a186fd498404fdae7d3a25dec64f014c590027d6
+> X-Git-Archeology:   Date: Wed, 05 Feb 2020 00:19:00 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switched rockchip64-dev to mainline kernel 5.5.y (#1781)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 5e251dc4148f7a7e3fa61d440c5a268626624de3: https://github.com/armbian/build/commit/5e251dc4148f7a7e3fa61d440c5a268626624de3
+> X-Git-Archeology:   Date: Mon, 06 Apr 2020 19:06:28 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Merged rockpi-s dev info rockchip64-dev and moved to 5.6.y (#1874)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 812245def37a695bce9e7ece148b2920d82c8b37: https://github.com/armbian/build/commit/812245def37a695bce9e7ece148b2920d82c8b37
+> X-Git-Archeology:   Date: Sat, 18 Jul 2020 23:07:01 +0200
+> X-Git-Archeology:   From: Werner <EvilOlaf@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Move rockchip/64 current to 5.7.y (#2099)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070
+> X-Git-Archeology:   Date: Sun, 13 Dec 2020 22:13:03 -0500
+> X-Git-Archeology:   From: tonymac32 <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: [ rockchip64 ] Clean up patchset
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+index 25ee84e06874..f5f521986d43 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+@@ -17,6 +17,7 @@ aliases {
+ 	};
+ 
+ 	chosen {
++		bootargs = "mmc_cmdqueue=0 earlycon=uart8250,mmio32,0xff1a0000";
+ 		stdout-path = "serial2:1500000n8";
+ 	};
+ 
+@@ -815,6 +816,7 @@ &sdmmc {
+ 
+ &sdhci {
+ 	bus-width = <8>;
++	keep-power-in-suspend;
+ 	mmc-hs200-1_8v;
+ 	non-removable;
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpro64-fix-spi1-flash-speed.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpro64-fix-spi1-flash-speed.patch
new file mode 100644
index 000000000000..3fb67e1c646b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpro64-fix-spi1-flash-speed.patch
@@ -0,0 +1,105 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Ayotte <martinayotte@yahoo.ca>
+Date: Sat, 5 Jan 2019 09:50:02 -0500
+Subject: [ARCHEOLOGY] slow SPIFlash to avoid errors
+
+> X-Git-Archeology: - Revision ea20f750bfead37ced7b604a44f8f014e317abad: https://github.com/armbian/build/commit/ea20f750bfead37ced7b604a44f8f014e317abad
+> X-Git-Archeology:   Date: Sat, 05 Jan 2019 09:50:02 -0500
+> X-Git-Archeology:   From: Martin Ayotte <martinayotte@yahoo.ca>
+> X-Git-Archeology:   Subject: slow SPIFlash to avoid errors
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision a186fd498404fdae7d3a25dec64f014c590027d6: https://github.com/armbian/build/commit/a186fd498404fdae7d3a25dec64f014c590027d6
+> X-Git-Archeology:   Date: Wed, 05 Feb 2020 00:19:00 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switched rockchip64-dev to mainline kernel 5.5.y (#1781)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 5e251dc4148f7a7e3fa61d440c5a268626624de3: https://github.com/armbian/build/commit/5e251dc4148f7a7e3fa61d440c5a268626624de3
+> X-Git-Archeology:   Date: Mon, 06 Apr 2020 19:06:28 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Merged rockpi-s dev info rockchip64-dev and moved to 5.6.y (#1874)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 812245def37a695bce9e7ece148b2920d82c8b37: https://github.com/armbian/build/commit/812245def37a695bce9e7ece148b2920d82c8b37
+> X-Git-Archeology:   Date: Sat, 18 Jul 2020 23:07:01 +0200
+> X-Git-Archeology:   From: Werner <EvilOlaf@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Move rockchip/64 current to 5.7.y (#2099)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 40665cde86285060e6bdd5ef7dc33be6c301ec66: https://github.com/armbian/build/commit/40665cde86285060e6bdd5ef7dc33be6c301ec66
+> X-Git-Archeology:   Date: Sun, 13 Dec 2020 23:22:08 -0500
+> X-Git-Archeology:   From: tonymac32 <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: [ rockchip64 ] Patch reorg round 2
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+index f5f521986d43..6eddc07a958f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+@@ -838,7 +838,7 @@ &spi1 {
+ 	flash@0 {
+ 		compatible = "jedec,spi-nor";
+ 		reg = <0>;
+-		spi-max-frequency = <10000000>;
++		spi-max-frequency = <3000000>;
+ 	};
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rockpro64-work-led-heartbeat.patch b/patch/kernel/archive/rockchip64-6.10/board-rockpro64-work-led-heartbeat.patch
new file mode 100644
index 000000000000..9e17aa826118
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rockpro64-work-led-heartbeat.patch
@@ -0,0 +1,95 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Piotr Szczepanik <piter75@gmail.com>
+Date: Mon, 24 Aug 2020 22:47:03 +0200
+Subject: [ARCHEOLOGY] Switch RockPro64 work led to heartbeat trigger
+
+> X-Git-Archeology: - Revision 42e76b9277ad492e935cc76c2b37c9f6d882a675: https://github.com/armbian/build/commit/42e76b9277ad492e935cc76c2b37c9f6d882a675
+> X-Git-Archeology:   Date: Mon, 24 Aug 2020 22:47:03 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch RockPro64 work led to heartbeat trigger
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision d1eb0003854909824d17b529cd513feb542bf228: https://github.com/armbian/build/commit/d1eb0003854909824d17b529cd513feb542bf228
+> X-Git-Archeology:   Date: Mon, 24 Aug 2020 23:11:20 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch RockPro64 work led to heartbeat trigger (in legacy too)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5: https://github.com/armbian/build/commit/4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5
+> X-Git-Archeology:   Date: Wed, 02 Sep 2020 23:22:09 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switched rockchip64 curent to kernel 5.8.y (#2175)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+index 6eddc07a958f..eb1eebadb637 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+@@ -66,7 +66,7 @@ leds {
+ 
+ 		work_led: led-0 {
+ 			label = "work";
+-			default-state = "on";
++			linux,default-trigger = "heartbeat";
+ 			gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ 		};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-rocks0-0001-deviceTree.patch b/patch/kernel/archive/rockchip64-6.10/board-rocks0-0001-deviceTree.patch
new file mode 100644
index 000000000000..fa0f46a0c85a
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-rocks0-0001-deviceTree.patch
@@ -0,0 +1,366 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Brent Roman <genosenosor@gmail.com>
+Date: Wed, 7 Feb 2024 18:02:07 -0800
+Subject: Added Linux device tree for Rock S0
+
+Signed-off-by: Brent Roman <genosenosor@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts | 347 ++++++++++
+ 1 files changed, 347 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
+new file mode 100644
+index 000000000..aded16959
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
+@@ -0,0 +1,347 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
++ * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
++ * Revised: 2024 Brent Roman <brent@mbari.org>
++ */
++
++/dts-v1/;
++#include "rk3308.dtsi"
++
++/ {
++	model = "Radxa ROCK S0";
++	compatible = "radxa,rock-s0", "rockchip,rk3308";
++
++	chosen {
++		stdout-path = "serial0:1500000n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&green_led_gio>;
++
++		green-led {
++			label = "rock-s0:green:power";
++			gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
++			default-state = "on";
++		};
++	};
++
++	acodec-sound {
++			compatible = "simple-audio-card";
++			simple-audio-card,format = "i2s";
++			simple-audio-card,name = "rockchip,rk3308-acodec";
++			simple-audio-card,mclk-fs = <256>;
++			simple-audio-card,codec-hp-det;
++			simple-audio-card,widgets =
++				"Headphone", "Headphones";
++			simple-audio-card,cpu {
++				sound-dai = <&i2s_8ch_2>;
++			};
++			simple-audio-card,codec {
++				sound-dai = <&codec>;
++			};
++	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,name = "i2s_8ch_0";
++
++		simple-audio-card,dai-link@1 {
++			format = "i2s";
++			cpu {
++				sound-dai = <&i2s_8ch_0>;
++			};
++
++			codec {
++				sound-dai = <&pcm5102a>;
++			};
++		};
++	};
++
++	pcm5102a: pcm5102a {
++			#sound-dai-cells = <0>;
++			compatible = "ti,pcm5102a";
++			pcm510x,format = "i2s";
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		pinctrl-0 = <&wifi_enable_h>;
++		pinctrl-names = "default";
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
++		reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
++	};
++
++	vcc_1v8: vcc-1v8 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_io>;
++	};
++
++	vcc_io: vcc-io {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_io";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc_ddr: vcc-ddr {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_ddr";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1500000>;
++		regulator-max-microvolt = <1500000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_otg: vcc5v0-otg {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&otg_vbus_drv>;
++		regulator-name = "vcc5v0_otg";
++		regulator-always-on;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vdd_core: vdd-core {
++		compatible = "pwm-regulator";
++		pwms = <&pwm0 0 5000 1>;
++		pwm-supply = <&vcc5v0_sys>;
++		regulator-name = "vdd_core";
++		regulator-min-microvolt = <827000>;
++		regulator-max-microvolt = <1340000>;
++		regulator-init-microvolt = <1015000>;
++		regulator-settling-time-up-us = <250>;
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vdd_log: vdd-log {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd_log";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1050000>;
++		regulator-max-microvolt = <1050000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	board_antenna: board-antenna {
++		status = "okay";
++		compatible = "regulator-fixed";
++		enable-active-low;
++		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
++		regulator-always-on;
++		regulator-boot-on;
++		pinctrl-0 = <&ant_1>;
++		pinctrl-names = "default";
++		regulator-name = "board_antenna";
++	};
++};
++
++&codec {
++	status = "okay";
++	#sound-dai-cells = <0>;
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_core>;
++};
++
++&emmc {
++	cap-mmc-highspeed;
++	mmc-hs200-1_8v;
++	non-removable;
++	vmmc-supply = <&vcc_io>;  //was vin-supply
++        status = "okay";
++};
++
++&sdmmc {
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	card-detect-delay = <800>;
++	status = "okay";
++};
++
++&sdio {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	no-mmc;
++	status = "okay";
++
++	AP6212: wifi@1 {
++		compatible = "brcm,bcm4329-fmac";
++		reg = <1>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "host-wake";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_host_wake>;
++	};
++};
++
++&gmac {
++	phy-supply = <&vcc_io>;
++	clock_in_out = "output";
++	assigned-clocks = <&cru SCLK_MAC>;
++	assigned-clock-parents = <&cru SCLK_MAC_SRC>;
++	snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 50000 50000>;
++	status = "okay";
++};
++
++&i2s_8ch_0 {
++	assigned-clocks = <&cru SCLK_I2S0_8CH_RX>;
++	assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>;
++	rockchip,clk-trcm = <1>;
++	#sound-dai-cells = <0>;
++};
++
++&i2s_8ch_2 {
++	status = "okay";
++	#sound-dai-cells = <0>;
++};
++
++&pinctrl {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rtc_32k>;
++
++	leds {
++		green_led_gio: green-led-gpio {
++			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		otg_vbus_drv: otg-vbus-drv {
++			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	wifi {
++		wifi_host_wake: wifi-host-wake {
++			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++	};
++	antenna {
++		ant_1: ant-1 {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++};
++
++&pwm0 {
++	status = "okay";
++	pinctrl-0 = <&pwm0_pin_pull_down>;
++};
++
++&saradc {
++	vref-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <0>;		/* 0:CRU */
++	rockchip,hw-tshut-polarity = <1>;	/* 1:HIGH */
++	status = "okay";
++};
++
++&i2c1 {
++	status = "okay";
++};
++
++&spi2 {
++//	status = "okay";  //conflicts with UART2
++	max-freq = <10000000>;
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&uart4 {
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723bs-bt";
++		device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
++		host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
++	};
++};
++
++&u2phy {
++	status = "okay";
++
++	u2phy_host: host-port {
++		phy-supply = <&vcc5v0_otg>;
++		status = "okay";
++	};
++
++	u2phy_otg: otg-port {
++		status = "okay";
++	};
++};
++
++&usb20_otg {
++	status = "okay";
++};
++
++&usb_host_ehci {
++	status = "okay";
++};
++
++&usb_host_ohci{
++	status = "okay";
++};
++
++&wdt {
++	status = "okay";
++};
++
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+
diff --git a/patch/kernel/archive/rockchip64-6.10/board-station-p2.patch b/patch/kernel/archive/rockchip64-6.10/board-station-p2.patch
new file mode 100644
index 000000000000..670c56d8fea3
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/board-station-p2.patch
@@ -0,0 +1,580 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
+@@ -48,17 +48,15 @@
+ 		#clock-cells = <0>;
+ 	};
+ 
+-	leds {
++	firefly_leds: leds {
+ 		compatible = "gpio-leds";
+-
+-		led-user {
+-			label = "user-led";
++		power_led: power {
++			label = "firefly:blue:power";
++			linux,default-trigger = "ir-power-click";
+ 			default-state = "on";
+ 			gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+-			linux,default-trigger = "heartbeat";
+ 			pinctrl-names = "default";
+-			pinctrl-0 = <&user_led_enable_h>;
+-			retain-state-suspended;
++			pinctrl-0 = <&led_power>;
+ 		};
+ 	};
+ 
+@@ -126,41 +124,134 @@
+ 		vin-supply = <&dc_12v>;
+ 	};
+ 
+-	vcc5v0_usb: vcc5v0-usb-regulator {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc5v0_usb";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <5000000>;
+-		regulator-max-microvolt = <5000000>;
+-		vin-supply = <&vcc5v0_sys>;
+-	};
+-
+ 	vcc5v0_host: vcc5v0-host-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc5v0_host";
+ 		enable-active-high;
+-		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&vcc5v0_host_en>;
+ 		regulator-always-on;
+-		vin-supply = <&vcc5v0_usb>;
+ 	};
+ 
+ 	vcc5v0_otg: vcc5v0-otg-regulator {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vcc5v0_otg";
+ 		enable-active-high;
+ 		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&vcc5v0_otg_en>;
+-		vin-supply = <&vcc5v0_usb>;
++		regulator-name = "vcc5v0_otg";
+ 	};
+-};
+ 
+-&combphy0 {
+-	/* used for USB3 */
+-	status = "okay";
++	vcc2v5_sys: vcc2v5-ddr-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc2v5-sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <2500000>;
++		regulator-max-microvolt = <2500000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vcc_hub_power: vcc-hub-power-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc_hub_power_en>;
++		regulator-name = "vcc_hub_power_en";
++		regulator-always-on;
++	};
++
++	vcc_hub_reset: vcc-hub-reset-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc_hub_reset_en>;
++		regulator-name = "vcc_hub_reset_en";
++		regulator-always-on;
++	};
++
++	pcie_pi6c_oe: pcie-pi6c-oe-regulator {
++		compatible = "regulator-fixed";
++		//enable-active-high;
++		gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_pi6c_oe_en>;
++		regulator-name = "pcie_pi6c_oe_en";
++		regulator-always-on;
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		status = "okay";
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk809 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;
++		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
++		post-power-on-delay-ms = <100>;
++	};
++
++	wireless_wlan: wireless-wlan {
++		compatible = "wlan-platdata";
++		rockchip,grf = <&grf>;
++		wifi_chip_type = "ap6275s";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_host_wake_irq>;
++		WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
++		status = "okay";
++	};
++
++	wireless_bluetooth: wireless-bluetooth {
++		compatible = "bluetooth-platdata";
++		clocks = <&rk809 1>;
++		clock-names = "ext_clock";
++		//wifi-bt-power-toggle;
++		uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default", "rts_gpio";
++		pinctrl-0 = <&uart8m0_rtsn>;
++		pinctrl-1 = <&uart8_gpios>;
++		BT,reset_gpio    = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
++		BT,wake_gpio     = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
++		BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
++		status = "okay";
++	};
++
++	flash_led: flash-led {
++		compatible = "led,rgb13h";
++		label = "pwm-flash-led";
++		led-max-microamp = <20000>;
++		flash-max-microamp = <20000>;
++		flash-max-timeout-us = <1000000>;
++		pwms = <&pwm11 0 25000 0>;
++		rockchip,camera-module-index = <1>;
++		rockchip,camera-module-facing = "front";
++		status = "disabled";
++	};
++
++	rk809-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "Analog RK809";
++		simple-audio-card,mclk-fs = <256>;
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&rk809>;
++		};
++	};
++
++	rk_headset: rk-headset {
++		compatible = "rockchip_headset";
++		headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&hp_det>;
++		io-channels = <&saradc 2>;    //HP_HOOK pin
++	};
+ };
+ 
+ &combphy1 {
+@@ -247,15 +338,59 @@
+ &i2c0 {
+ 	status = "okay";
+ 
++	fusb0: fusb30x@22 {
++		compatible = "fairchild,fusb302";
++		reg = <0x22>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fusb0_int>;
++		int-n-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
++		fusb340-switch-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
++		vbus-5v-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++		status = "okay";
++	};
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		vin-supply = <&vcc5v0_sys>;
++		regulator-compatible = "fan53555-reg";
++		regulator-name = "vdd_cpu";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1390000>;
++		regulator-ramp-delay = <2300>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-boot-on;
++		regulator-always-on;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
+ 	rk809: pmic@20 {
+ 		compatible = "rockchip,rk809";
+ 		reg = <0x20>;
+ 		interrupt-parent = <&gpio0>;
+ 		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
++		assigned-clock-rates = <12288000>;
++		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ 		#clock-cells = <1>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&pmic_int>;
++		clock-names = "mclk";
++		clocks = <&cru I2S1_MCLKOUT_TX>;
++		pinctrl-names = "default", "pmic-sleep",
++				"pmic-power-off", "pmic-reset";
++		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
++
+ 		rockchip,system-power-controller;
++		#sound-dai-cells = <0>;
++		clock-output-names = "rk808-clkout1", "rk808-clkout2";
++		//fb-inner-reg-idxs = <2>;
++		/* 1: rst regs (default in codes), 0: rst the pmic */
++		pmic-reset-func = <0>;
++		/* not save the PMIC_POWER_EN register in uboot */
++		not-save-power-en = <1>;
++
+ 		vcc1-supply = <&vcc3v3_sys>;
+ 		vcc2-supply = <&vcc3v3_sys>;
+ 		vcc3-supply = <&vcc3v3_sys>;
+@@ -284,6 +419,8 @@
+ 			};
+ 
+ 			vdd_gpu: DCDC_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-name = "vdd_gpu";
+ 				regulator-init-microvolt = <900000>;
+ 				regulator-initial-mode = <0x2>;
+@@ -320,19 +457,9 @@
+ 				};
+ 			};
+ 
+-			vcc_1v8: DCDC_REG5 {
+-				regulator-name = "vcc_1v8";
+-				regulator-always-on;
+-				regulator-boot-on;
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+ 			vdda0v9_image: LDO_REG1 {
++				regulator-boot-on;
++				regulator-always-on;
+ 				regulator-name = "vdda0v9_image";
+ 				regulator-min-microvolt = <900000>;
+ 				regulator-max-microvolt = <900000>;
+@@ -368,6 +495,8 @@
+ 			};
+ 
+ 			vccio_acodec: LDO_REG4 {
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-name = "vccio_acodec";
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+@@ -379,6 +508,8 @@
+ 
+ 			vccio_sd: LDO_REG5 {
+ 				regulator-name = "vccio_sd";
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <3300000>;
+ 
+@@ -426,6 +557,8 @@
+ 			};
+ 
+ 			vcca1v8_image: LDO_REG9 {
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-name = "vcca1v8_image";
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <1800000>;
+@@ -435,6 +568,17 @@
+ 				};
+ 			};
+ 
++			vcc_1v8: DCDC_REG5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc_1v8";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
+ 			vcc_3v3: SWITCH_REG1 {
+ 				regulator-name = "vcc_3v3";
+ 				regulator-always-on;
+@@ -455,6 +599,10 @@
+ 				};
+ 			};
+ 		};
++
++		codec {
++			mic-in-differential;
++		};
+ 	};
+ };
+ 
+@@ -477,7 +625,7 @@
+ };
+ 
+ &pcie30phy {
+-	status = "okay";
++	tatus = "okay";
+ };
+ 
+ &pcie3x2 {
+@@ -490,19 +638,27 @@
+ 
+ &pinctrl {
+ 	leds {
+-		user_led_enable_h: user-led-enable-h {
+-			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		led_power: led-power {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+ 
+ 	usb {
+ 		vcc5v0_host_en: vcc5v0-host-en {
+-			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 
+ 		vcc5v0_otg_en: vcc5v0-otg-en {
+ 			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++
++		vcc_hub_power_en: vcc-hub-power-en {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc_hub_reset_en: vcc-hub-reset-en {
++			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
+ 	};
+ 
+ 	pcie {
+@@ -512,21 +668,53 @@
+ 		vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
+ 			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++		pcie_pi6c_oe_en: pcie-pi6c-oe-en {
++			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
+ 	};
+ 
+ 	pmic {
+-		pmic_int: pmic-int {
++		pmic_int: pmic_int {
+ 			rockchip,pins =
+ 				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	wireless-wlan {
++		wifi_host_wake_irq: wifi-host-wake-irq {
++			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	wireless-bluetooth {
++		uart8_gpios: uart8-gpios {
++			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	fusb30x {
++		fusb0_int: fusb0-int {
++			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	headphone {
++		hp_det: hp-det {
++			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
+ };
+ 
+ &pmu_io_domains {
+ 	pmuio1-supply = <&vcc3v3_pmu>;
+ 	pmuio2-supply = <&vcc3v3_pmu>;
+ 	vccio1-supply = <&vccio_acodec>;
+-	vccio2-supply = <&vcc_1v8>;
+ 	vccio3-supply = <&vccio_sd>;
+ 	vccio4-supply = <&vcc_1v8>;
+ 	vccio5-supply = <&vcc_3v3>;
+@@ -548,25 +736,44 @@
+ 	bus-width = <8>;
+ 	max-frequency = <200000000>;
+ 	non-removable;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
++	supports-emmc;
+ 	status = "okay";
+ };
+ 
+ &sdmmc0 {
+ 	bus-width = <4>;
+ 	cap-sd-highspeed;
+-	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ 	disable-wp;
+-	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ 	sd-uhs-sdr104;
+ 	vmmc-supply = <&vcc3v3_sd>;
+ 	vqmmc-supply = <&vccio_sd>;
++	max-frequency = <150000000>;
++	supports-sd;
++	cap-mmc-highspeed;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&sdmmc2 {
++	max-frequency = <150000000>;
++	supports-sdio;
++	bus-width = <4>;
++	disable-wp;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
++	sd-uhs-sdr104;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
+ 	status = "okay";
+ };
+ 
+ &tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
+ 	status = "okay";
+ };
+ 
+@@ -588,6 +795,7 @@
+ };
+ 
+ &usb2phy0_otg {
++	vbus-supply = <&vcc5v0_otg>;
+ 	status = "okay";
+ };
+ 
+@@ -609,6 +817,10 @@
+ 	status = "okay";
+ };
+ 
++&usb_host0_xhci {
++	status = "okay";
++};
++
+ &usb_host1_ehci {
+ 	status = "okay";
+ };
+@@ -617,11 +829,13 @@
+ 	status = "okay";
+ };
+ 
+-&usb_host0_xhci {
++&usb_host1_xhci {
+ 	status = "okay";
+ };
+ 
+-&usb_host1_xhci {
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ 	status = "okay";
+ };
+ 
+@@ -632,12 +846,68 @@
+ 	};
+ };
+ 
+-&vop {
+-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++&vop_mmu {
+ 	status = "okay";
+ };
+ 
+-&vop_mmu {
++&i2s1_8ch {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2s1m0_sclktx
++		     &i2s1m0_lrcktx
++		     &i2s1m0_sdi0
++		     &i2s1m0_sdo0>;
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
++&i2c1 {
++    status = "okay";
++};
++
++&i2c4 {
++	status = "okay";
++};
++
++&i2c5 {
++    status = "okay";
++};
++
++&gic {
++    status = "okay";
++};
++
++&uart3 {
++//	status = "disabled";
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&uart4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart4m1_xfer>;
++        status = "okay";
++};
++
++&uart8 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
++};
++
++&rk809 {
++    rtc {
++        status = "disabled";
++    };
++};
++
++&pwm4 {
++	status = "okay";
++};
++
++&pwm5 {
++	status = "okay";
++};
++
++&pwm7 {
+ 	status = "okay";
+ };
diff --git a/patch/kernel/archive/rockchip64-6.10/drv-spi-spidev-remove-warnings.patch b/patch/kernel/archive/rockchip64-6.10/drv-spi-spidev-remove-warnings.patch
new file mode 100644
index 000000000000..80987aa16384
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/drv-spi-spidev-remove-warnings.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: John Doe <john.doe@somewhere.on.planet>
+Date: Wed, 14 Aug 2024 16:33:07 +0000
+Subject: rockchip64: edge: 6.10.5 drv:spi:spidev remove warnings
+
+Signed-off-by: John Doe <john.doe@somewhere.on.planet>
+---
+ drivers/spi/spidev.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index 5304728c6..64c4280de 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -698,10 +698,11 @@ static const struct file_operations spidev_fops = {
+ static const struct class spidev_class = {
+ 	.name = "spidev",
+ };
+ 
+ static const struct spi_device_id spidev_spi_ids[] = {
++	{ .name = "spi-dev" },
+ 	{ .name = "bh2228fv" },
+ 	{ .name = "dh2228fv" },
+ 	{ .name = "ltc2488" },
+ 	{ .name = "sx1301" },
+ 	{ .name = "bk4" },
+@@ -727,10 +728,11 @@ static int spidev_of_check(struct device *dev)
+ 	dev_err(dev, "spidev listed directly in DT is not supported\n");
+ 	return -EINVAL;
+ }
+ 
+ static const struct of_device_id spidev_dt_ids[] = {
++	{ .compatible = "armbian,spi-dev", .data = &spidev_of_check },
+ 	{ .compatible = "cisco,spi-petra", .data = &spidev_of_check },
+ 	{ .compatible = "dh,dhcom-board", .data = &spidev_of_check },
+ 	{ .compatible = "lineartechnology,ltc2488", .data = &spidev_of_check },
+ 	{ .compatible = "lwn,bk4", .data = &spidev_of_check },
+ 	{ .compatible = "menlo,m53cpld", .data = &spidev_of_check },
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3308-sakurapi-rk3308b.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3308-sakurapi-rk3308b.dts
new file mode 100644
index 000000000000..7d942a8f5e54
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3308-sakurapi-rk3308b.dts
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
+ * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
+ * Copyright (C) 2024 Chiyuki Akatsuki
+ */
+
+/dts-v1/;
+#include "rk3308.dtsi"
+
+/ {
+	model = "Sakura Pi RK3308B";
+	compatible = "rockchip,rk3308";
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-0 = <&wifi_enable_h>;
+		pinctrl-names = "default";
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vdd_core: vdd-core {
+		compatible = "pwm-regulator";
+		pwms = <&pwm0 0 5000 1>;
+		regulator-name = "vdd_core";
+		regulator-min-microvolt = <827000>;
+		regulator-max-microvolt = <1340000>;
+		regulator-init-microvolt = <1015000>;
+		regulator-settling-time-up-us = <250>;
+		regulator-always-on;
+		regulator-boot-on;
+		pwm-supply = <&vcc5v0_sys>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1050000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_ddr: vcc-ddr {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_ddr";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_1v8: vcc-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_io: vcc-io {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_io";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_otg: vcc5v0-otg {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		regulator-always-on;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&otg_vbus_drv>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_core>;
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	non-removable;
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&sdmmc {
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
+	card-detect-delay = <800>;
+	status = "okay";
+};
+
+&sdio {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	no-mmc;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm43455-fmac";
+		reg = <1>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake>;
+	};
+};
+
+&spi2 {
+	status = "okay";
+	max-freq = <10000000>;
+};
+
+&pinctrl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rtc_32k>;
+
+	usb {
+		otg_vbus_drv: otg-vbus-drv {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifi {
+		wifi_host_wake: wifi-host-wake {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_pin_pull_down>;
+};
+
+&saradc {
+	vref-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&usb20_otg {
+	status = "okay";
+};
+
+&u2phy {
+	status = "okay";
+};
+
+&u2phy_otg {
+	status = "okay";
+};
+
+&u2phy_host {
+	state = "okay";
+};
+
+&usb_host_ehci {
+	status = "okay";
+};
+
+&usb_host_ohci{
+	status = "okay";
+};
+
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3318-box.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3318-box.dts
new file mode 100644
index 000000000000..8024338b41f5
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3318-box.dts
@@ -0,0 +1,1007 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Paolo Sabatino
+ */
+
+/dts-v1/;
+#include "dt-bindings/pwm/pwm.h"
+#include "dt-bindings/input/input.h"
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/memory/rk3328-dram.h>
+#include "rk3328.dtsi"
+
+/ {
+	model = "Rockchip RK3318 BOX";
+	compatible = "rockchip,rk3318-box", "rockchip,rk3328-box", "rockchip,rk3328";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdio;
+		mmc2 = &emmc;
+		mmc3 = &sdmmc_ext;
+		mmc4 = &sdio_ext;
+	};
+
+	/delete-node/ opp-table-0;
+	/delete-node/ gpu-opp-table;
+
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <950000>;
+			clock-latency-ns = <40000>;
+			opp-suspend;
+		};
+		opp-816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1200000>;
+			clock-latency-ns = <40000>;
+			status = "disabled";
+		};
+		opp-1296000000 {
+			opp-hz = /bits/ 64 <1296000000>;
+			opp-microvolt = <1275000>;
+			clock-latency-ns = <40000>;
+			status = "disabled";
+		};
+	};
+
+	gpu_opp_table: gpu-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1000000 950000 1200000>;
+		};
+
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <1050000 950000 1200000>;
+		};
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1050000 950000 1200000>;
+		};
+
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <1100000 950000 1200000>;
+		};
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	adc_keys: adc-keys {
+
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		recovery {
+			label = "recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <17000>;
+		};
+
+	};
+
+	xin32k: xin32k {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		#clock-cells = <0>;
+	};
+
+	gmac_clkin: gmac-clkin {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac_clkin";
+		#clock-cells = <0x00>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		vcc_18: regulator@0 {
+			compatible = "regulator-fixed";
+			regulator-name = "vccio_1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		vcc_io: regulator@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "vccio_3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0m1_pin>;
+		regulator-name = "vcc_sd";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	/*
+	 * USB3 vbus
+	 */
+	vcc_host_vbus: vcc-host-vbus {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb30_host_drv>;
+		regulator-name = "vcc_host_vbus";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	/*
+	 * USB2 OTG vbus
+	 */
+	vcc_otg_vbus: vcc-otg-vbus {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb20_host_drv>;
+		regulator-name = "vcc_otg_vbus";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vdd_arm: vdd-arm {
+		compatible = "pwm-regulator";
+		pwms = <&pwm0 0 5000 PWM_POLARITY_INVERTED>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_arm";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-ramp-delay = <12500>;
+		regulator-settling-time-up-us = <250>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_logic: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-ramp-delay = <12500>;
+		regulator-settling-time-up-us = <250>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	gpio_led: gpio-leds {
+		compatible = "gpio-leds";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&working_led>;
+
+		working {
+			gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "timer";
+			default-state = "on";
+		};
+
+	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&ir_int>;
+		pinctrl-names = "default";
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+	};
+
+	/*
+	wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default", "rts_gpio";
+		pinctrl-0 = <&uart0_rts>;
+		pinctrl-1 = <&uart0_rts_gpio>;
+		BT,power_gpio = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+		BT,wake_host_irq = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+	};
+
+	wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6330";
+		sdio_vref = <1800>;
+		WIFI,host_wake_irq = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+	};
+	*/
+
+	fd628_dev {
+		compatible = "fd628_dev";
+		fd628_gpio_clk = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		fd628_gpio_dat = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	analog-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "ANALOG";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&codec>;
+		};
+	};
+
+	hdmi-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <128>;
+		simple-audio-card,name = "HDMI";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&hdmi>;
+		};
+	};
+
+	/*
+	 * This node is a duplicate of sdmmc_ext: most common board do not use sdmmc_ext
+	 * controller, so it is left unused. Some other boards use it as sdio controller
+	 * for wifi and some others use it as sdcard controller.
+	 * To handle the most critical situation, the controller will be configured as
+	 * sdcard controller by default. An overlay can be set to disable the sdmmc_ext
+	 * node and enable this sdio_ext in case wifi chips are attached to this.
+	 */
+	sdio_ext: mmc@ff5f0000 {
+		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x0 0xff5f0000 0x0 0x4000>;
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
+			 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <150000000>;
+		resets = <&cru SRST_SDMMCEXT>;
+		reset-names = "reset";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		bus-width = <4>;
+		cap-sd-highspeed;
+		cap-sdio-irq;
+		disable-wp;
+		keep-power-in-suspend;
+		mmc-pwrseq = <>;
+		non-removable;
+		num-slots = <1>;
+		pinctrl-0 = <&sdmmc0ext_cmd &sdmmc0ext_clk &sdmmc0ext_bus4>;
+		pinctrl-names = "default";
+		supports-sdio;
+		status = "disabled";
+	};
+
+	ddr_timing: ddr_timing {
+		compatible = "rockchip,ddr-timing";
+		ddr3_speed_bin = <DDR3_DEFAULT>;
+		ddr4_speed_bin = <DDR4_DEFAULT>;
+		pd_idle = <0>;
+		sr_idle = <0>;
+		sr_mc_gate_idle = <0>;
+		srpd_lite_idle	= <0>;
+		standby_idle = <0>;
+
+		auto_pd_dis_freq = <1066>;
+		auto_sr_dis_freq = <800>;
+		ddr3_dll_dis_freq = <300>;
+		ddr4_dll_dis_freq = <625>;
+		phy_dll_dis_freq = <400>;
+
+		ddr3_odt_dis_freq = <100>;
+		phy_ddr3_odt_dis_freq = <100>;
+		ddr3_drv = <DDR3_DS_40ohm>;
+		ddr3_odt = <DDR3_ODT_120ohm>;
+		phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_23ohm>;
+		phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_34ohm>;
+		phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
+		phy_ddr3_odt = <PHY_DDR3_RON_RTT_150ohm>;
+
+		lpddr3_odt_dis_freq = <666>;
+		phy_lpddr3_odt_dis_freq = <666>;
+		lpddr3_drv = <LP3_DS_40ohm>;
+		lpddr3_odt = <LP3_ODT_240ohm>;
+		phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+		phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
+		phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+		phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
+
+		lpddr4_odt_dis_freq = <800>;
+		phy_lpddr4_odt_dis_freq = <800>;
+		lpddr4_drv = <LP4_PDDS_60ohm>;
+		lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
+		lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
+		phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
+		phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
+		phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
+		phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
+
+		ddr4_odt_dis_freq = <666>;
+		phy_ddr4_odt_dis_freq = <666>;
+		ddr4_drv = <DDR4_DS_34ohm>;
+		ddr4_odt = <DDR4_RTT_NOM_240ohm>;
+		phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+		phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
+		phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+		phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
+
+		/* CA de-skew, one step is 47.8ps, range 0-15 */
+		ddr3a1_ddr4a9_de-skew = <2>;
+		ddr3a0_ddr4a10_de-skew = <3>;
+		ddr3a3_ddr4a6_de-skew = <3>;
+		ddr3a2_ddr4a4_de-skew = <2>;
+		ddr3a5_ddr4a8_de-skew = <3>;
+		ddr3a4_ddr4a5_de-skew = <2>;
+		ddr3a7_ddr4a11_de-skew = <3>;
+		ddr3a6_ddr4a7_de-skew = <2>;
+		ddr3a9_ddr4a0_de-skew = <2>;
+		ddr3a8_ddr4a13_de-skew = <1>;
+		ddr3a11_ddr4a3_de-skew = <2>;
+		ddr3a10_ddr4cs0_de-skew = <2>;
+		ddr3a13_ddr4a2_de-skew = <1>;
+		ddr3a12_ddr4ba1_de-skew = <2>;
+		ddr3a15_ddr4odt0_de-skew = <3>;
+		ddr3a14_ddr4a1_de-skew = <2>;
+		ddr3ba1_ddr4a15_de-skew = <2>;
+		ddr3ba0_ddr4bg0_de-skew = <4>;
+		ddr3ras_ddr4cke_de-skew = <4>;
+		ddr3ba2_ddr4ba0_de-skew = <3>;
+		ddr3we_ddr4bg1_de-skew = <2>;
+		ddr3cas_ddr4a12_de-skew = <2>;
+		ddr3ckn_ddr4ckn_de-skew = <11>;
+		ddr3ckp_ddr4ckp_de-skew = <11>;
+		ddr3cke_ddr4a16_de-skew = <2>;
+		ddr3odt0_ddr4a14_de-skew = <4>;
+		ddr3cs0_ddr4act_de-skew = <4>;
+		ddr3reset_ddr4reset_de-skew = <7>;
+		ddr3cs1_ddr4cs1_de-skew = <7>;
+		ddr3odt1_ddr4odt1_de-skew = <7>;
+
+		/* DATA de-skew
+		 * RX one step is 25.1ps, range 0-15
+		 * TX one step is 47.8ps, range 0-15
+		 */
+		cs0_dm0_rx_de-skew = <12>;
+		cs0_dm0_tx_de-skew = <10>;
+		cs0_dq0_rx_de-skew = <12>;
+		cs0_dq0_tx_de-skew = <10>;
+		cs0_dq1_rx_de-skew = <12>;
+		cs0_dq1_tx_de-skew = <10>;
+		cs0_dq2_rx_de-skew = <12>;
+		cs0_dq2_tx_de-skew = <10>;
+		cs0_dq3_rx_de-skew = <12>;
+		cs0_dq3_tx_de-skew = <10>;
+		cs0_dq4_rx_de-skew = <12>;
+		cs0_dq4_tx_de-skew = <10>;
+		cs0_dq5_rx_de-skew = <12>;
+		cs0_dq5_tx_de-skew = <10>;
+		cs0_dq6_rx_de-skew = <12>;
+		cs0_dq6_tx_de-skew = <10>;
+		cs0_dq7_rx_de-skew = <12>;
+		cs0_dq7_tx_de-skew = <10>;
+		cs0_dqs0_rx_de-skew = <10>;
+		cs0_dqs0p_tx_de-skew = <12>;
+		cs0_dqs0n_tx_de-skew = <12>;
+
+		cs0_dm1_rx_de-skew = <10>;
+		cs0_dm1_tx_de-skew = <8>;
+		cs0_dq8_rx_de-skew = <10>;
+		cs0_dq8_tx_de-skew = <8>;
+		cs0_dq9_rx_de-skew = <10>;
+		cs0_dq9_tx_de-skew = <8>;
+		cs0_dq10_rx_de-skew = <10>;
+		cs0_dq10_tx_de-skew = <8>;
+		cs0_dq11_rx_de-skew = <10>;
+		cs0_dq11_tx_de-skew = <8>;
+		cs0_dq12_rx_de-skew = <10>;
+		cs0_dq12_tx_de-skew = <8>;
+		cs0_dq13_rx_de-skew = <10>;
+		cs0_dq13_tx_de-skew = <8>;
+		cs0_dq14_rx_de-skew = <10>;
+		cs0_dq14_tx_de-skew = <8>;
+		cs0_dq15_rx_de-skew = <10>;
+		cs0_dq15_tx_de-skew = <8>;
+		cs0_dqs1_rx_de-skew = <9>;
+		cs0_dqs1p_tx_de-skew = <10>;
+		cs0_dqs1n_tx_de-skew = <10>;
+
+		cs0_dm2_rx_de-skew = <10>;
+		cs0_dm2_tx_de-skew = <9>;
+		cs0_dq16_rx_de-skew = <10>;
+		cs0_dq16_tx_de-skew = <9>;
+		cs0_dq17_rx_de-skew = <10>;
+		cs0_dq17_tx_de-skew = <9>;
+		cs0_dq18_rx_de-skew = <10>;
+		cs0_dq18_tx_de-skew = <9>;
+		cs0_dq19_rx_de-skew = <10>;
+		cs0_dq19_tx_de-skew = <9>;
+		cs0_dq20_rx_de-skew = <10>;
+		cs0_dq20_tx_de-skew = <9>;
+		cs0_dq21_rx_de-skew = <10>;
+		cs0_dq21_tx_de-skew = <9>;
+		cs0_dq22_rx_de-skew = <10>;
+		cs0_dq22_tx_de-skew = <9>;
+		cs0_dq23_rx_de-skew = <10>;
+		cs0_dq23_tx_de-skew = <9>;
+		cs0_dqs2_rx_de-skew = <9>;
+		cs0_dqs2p_tx_de-skew = <11>;
+		cs0_dqs2n_tx_de-skew = <11>;
+
+		cs0_dm3_rx_de-skew = <7>;
+		cs0_dm3_tx_de-skew = <7>;
+		cs0_dq24_rx_de-skew = <7>;
+		cs0_dq24_tx_de-skew = <7>;
+		cs0_dq25_rx_de-skew = <7>;
+		cs0_dq25_tx_de-skew = <7>;
+		cs0_dq26_rx_de-skew = <7>;
+		cs0_dq26_tx_de-skew = <7>;
+		cs0_dq27_rx_de-skew = <7>;
+		cs0_dq27_tx_de-skew = <7>;
+		cs0_dq28_rx_de-skew = <7>;
+		cs0_dq28_tx_de-skew = <7>;
+		cs0_dq29_rx_de-skew = <7>;
+		cs0_dq29_tx_de-skew = <7>;
+		cs0_dq30_rx_de-skew = <7>;
+		cs0_dq30_tx_de-skew = <7>;
+		cs0_dq31_rx_de-skew = <7>;
+		cs0_dq31_tx_de-skew = <7>;
+		cs0_dqs3_rx_de-skew = <7>;
+		cs0_dqs3p_tx_de-skew = <10>;
+		cs0_dqs3n_tx_de-skew = <10>;
+
+		cs1_dm0_rx_de-skew = <7>;
+		cs1_dm0_tx_de-skew = <8>;
+		cs1_dq0_rx_de-skew = <7>;
+		cs1_dq0_tx_de-skew = <8>;
+		cs1_dq1_rx_de-skew = <7>;
+		cs1_dq1_tx_de-skew = <8>;
+		cs1_dq2_rx_de-skew = <7>;
+		cs1_dq2_tx_de-skew = <8>;
+		cs1_dq3_rx_de-skew = <7>;
+		cs1_dq3_tx_de-skew = <8>;
+		cs1_dq4_rx_de-skew = <7>;
+		cs1_dq4_tx_de-skew = <8>;
+		cs1_dq5_rx_de-skew = <7>;
+		cs1_dq5_tx_de-skew = <8>;
+		cs1_dq6_rx_de-skew = <7>;
+		cs1_dq6_tx_de-skew = <8>;
+		cs1_dq7_rx_de-skew = <7>;
+		cs1_dq7_tx_de-skew = <8>;
+		cs1_dqs0_rx_de-skew = <6>;
+		cs1_dqs0p_tx_de-skew = <9>;
+		cs1_dqs0n_tx_de-skew = <9>;
+
+		cs1_dm1_rx_de-skew = <7>;
+		cs1_dm1_tx_de-skew = <7>;
+		cs1_dq8_rx_de-skew = <7>;
+		cs1_dq8_tx_de-skew = <8>;
+		cs1_dq9_rx_de-skew = <7>;
+		cs1_dq9_tx_de-skew = <7>;
+		cs1_dq10_rx_de-skew = <7>;
+		cs1_dq10_tx_de-skew = <8>;
+		cs1_dq11_rx_de-skew = <7>;
+		cs1_dq11_tx_de-skew = <7>;
+		cs1_dq12_rx_de-skew = <7>;
+		cs1_dq12_tx_de-skew = <8>;
+		cs1_dq13_rx_de-skew = <7>;
+		cs1_dq13_tx_de-skew = <7>;
+		cs1_dq14_rx_de-skew = <7>;
+		cs1_dq14_tx_de-skew = <8>;
+		cs1_dq15_rx_de-skew = <7>;
+		cs1_dq15_tx_de-skew = <7>;
+		cs1_dqs1_rx_de-skew = <7>;
+		cs1_dqs1p_tx_de-skew = <9>;
+		cs1_dqs1n_tx_de-skew = <9>;
+
+		cs1_dm2_rx_de-skew = <7>;
+		cs1_dm2_tx_de-skew = <8>;
+		cs1_dq16_rx_de-skew = <7>;
+		cs1_dq16_tx_de-skew = <8>;
+		cs1_dq17_rx_de-skew = <7>;
+		cs1_dq17_tx_de-skew = <8>;
+		cs1_dq18_rx_de-skew = <7>;
+		cs1_dq18_tx_de-skew = <8>;
+		cs1_dq19_rx_de-skew = <7>;
+		cs1_dq19_tx_de-skew = <8>;
+		cs1_dq20_rx_de-skew = <7>;
+		cs1_dq20_tx_de-skew = <8>;
+		cs1_dq21_rx_de-skew = <7>;
+		cs1_dq21_tx_de-skew = <8>;
+		cs1_dq22_rx_de-skew = <7>;
+		cs1_dq22_tx_de-skew = <8>;
+		cs1_dq23_rx_de-skew = <7>;
+		cs1_dq23_tx_de-skew = <8>;
+		cs1_dqs2_rx_de-skew = <6>;
+		cs1_dqs2p_tx_de-skew = <9>;
+		cs1_dqs2n_tx_de-skew = <9>;
+
+		cs1_dm3_rx_de-skew = <7>;
+		cs1_dm3_tx_de-skew = <7>;
+		cs1_dq24_rx_de-skew = <7>;
+		cs1_dq24_tx_de-skew = <8>;
+		cs1_dq25_rx_de-skew = <7>;
+		cs1_dq25_tx_de-skew = <7>;
+		cs1_dq26_rx_de-skew = <7>;
+		cs1_dq26_tx_de-skew = <7>;
+		cs1_dq27_rx_de-skew = <7>;
+		cs1_dq27_tx_de-skew = <7>;
+		cs1_dq28_rx_de-skew = <7>;
+		cs1_dq28_tx_de-skew = <7>;
+		cs1_dq29_rx_de-skew = <7>;
+		cs1_dq29_tx_de-skew = <7>;
+		cs1_dq30_rx_de-skew = <7>;
+		cs1_dq30_tx_de-skew = <7>;
+		cs1_dq31_rx_de-skew = <7>;
+		cs1_dq31_tx_de-skew = <7>;
+		cs1_dqs3_rx_de-skew = <7>;
+		cs1_dqs3p_tx_de-skew = <9>;
+		cs1_dqs3n_tx_de-skew = <9>;
+	};
+
+};
+
+&dfi {
+	status = "okay";
+};
+
+&dmc {
+	center-supply = <&vdd_logic>;
+	ddr_timing = <&ddr_timing>;
+	status = "disabled";
+};
+
+&codec {
+	status = "okay";
+	mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&emmc {
+
+	supports-emmc;
+	no-sdio;
+	no-sd;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	bus-width = <8>;
+	num-slots = <0x01>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+
+	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc_18>;
+
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <500>;
+	cd-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	no-sdio;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+	supports-sd;
+	status = "okay";
+	vmmc-supply = <&vcc_sd>;
+};
+
+&sdio {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	disable-wp;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	supports-sdio;
+	status = "okay";
+};
+
+/*
+ * sdmmc_ext is configured as sdcard controller and enabled by default.
+ * In this way boards which have the sdcard attached to sdmmc_ext will work
+ * by default. In case the controller is not attached to anything, the
+ * kernel will just autodetect and give up.
+ */
+&sdmmc_ext {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <500>;
+	cd-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	no-sdio;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_dectn &sdmmc0ext_bus4>;
+	supports-sd;
+	status = "okay";
+	vmmc-supply = <&vcc_sd>;
+};
+
+&gmac2phy {
+	phy-supply = <&vcc_phy>;
+
+	phy-mode = "rmii";
+
+	clock_in_out = "output";
+	assigned-clocks = <&cru SCLK_MAC2PHY>;
+	assigned-clock-rate = <50000000>;
+	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+
+	status = "okay";
+
+};
+
+&gpu {
+	status = "okay";
+	mali-supply = <&vdd_logic>;
+};
+
+/*
+&h265e {
+	status = "okay";
+};
+*/
+
+&h265e_mmu {
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-0 = <&spdifm0_tx>;
+	status = "okay";
+};
+
+&spdif_out {
+	status = "okay";
+};
+
+&spdif_sound {
+	status = "okay";
+};
+
+&hdmiphy {
+	status = "okay";
+};
+
+&i2s0 {
+	status = "okay";
+};
+
+&i2s1 {
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	vccio1-supply = <&vcc_io>;
+	vccio2-supply = <&vcc_18>;
+	vccio3-supply = <&vcc_io>;
+	vccio4-supply = <&vcc_18>;
+	vccio5-supply = <&vcc_io>;
+	vccio6-supply = <&vcc_io>;
+	pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&clk_32k_out>;
+
+	clk_32k {
+		clk_32k_out: clk-32k-out {
+			rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		working_led: working-led {
+			rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none_2ma>;
+		};
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_4ma>;/*,
+				<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none_4ma>;*/
+		};
+	};
+
+	usb2 {
+		usb20_host_drv: usb20-host-drv {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb3 {
+		usb30_host_drv: usb30-host-drv {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wireless-wlan {
+
+		/*
+		 * SDIO host wake interrupt on YX_RK3328 board (sdio is attached to
+		 * regular mmc controller mmc@ff510000)
+		 */
+		sdio_host_wake: sdio-host-wake {
+			rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		/*
+		 * SDIO host wake interrupt on X88_PRO_B board (sdio is attached to
+		 * alternative mmc controller mmc@ff5f0000)
+		 */
+		sdio_host_wake_ext: sdio-host-wake-ext {
+			rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+};
+
+/*
+&vdec {
+	status = "okay";
+	vcodec-supply = <&vdd_logic>;
+};
+*/
+
+&vdec_mmu {
+	status = "okay";
+};
+
+&threshold {
+	temperature = <80000>; /* millicelsius */
+};
+
+&target {
+	temperature = <95000>; /* millicelsius */
+};
+
+&soc_crit {
+	temperature = <100000>; /* millicelsius */
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart0 {
+
+	status = "okay";
+
+};
+
+&uart2 {
+	/delete-property/ dmas;
+	/delete-property/ dma-names;
+
+	status = "okay";
+};
+
+&u2phy {
+	status = "okay";
+
+	u2phy_host: host-port {
+		status = "okay";
+	};
+
+	u2phy_otg: otg-port {
+		status = "okay";
+	};
+};
+
+&usb20_otg {
+	dr_mode = "host";
+	resets = <&cru SRST_USB2OTG>;
+	reset-names = "dwc2";
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	resets = <&cru SRST_USB2HOST_EHCIPHY>;
+	reset-names = "ehci";
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usbdrd3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+	vcodec-supply = <&vdd_logic>;
+};
+
+&vpu_mmu {
+	status = "okay";
+};
+
+/*
+&vepu {
+	status = "okay";
+};
+*/
+
+&vepu_mmu {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcc_18>;
+	status = "okay";
+};
+
+/*
+&rga {
+	status = "okay";
+};
+*/
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&analog_sound {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3328-heltec.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-heltec.dts
new file mode 100755
index 000000000000..1cb919d9adba
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-heltec.dts
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+	model = "Rockchip RK3328 Heltec";
+	compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdio;
+		mmc2 = &emmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0m1_pin>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+	status = "okay";
+};
+
+&gmac2phy {
+	phy-supply = <&vcc_phy>;
+	clock_in_out = "output";
+	assigned-clock-rate = <50000000>;
+	assigned-clocks = <&cru SCLK_MAC2PHY>;
+	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	rk805: pmic@18 {
+		compatible = "rockchip,rk805";
+		reg = <0x18>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk805-clkout2";
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc5-supply = <&vcc_io>;
+		vcc6-supply = <&vcc_io>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vdd_arm: DCDC_REG2 {
+				regulator-name = "vdd_arm";
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io: DCDC_REG4 {
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_18: LDO_REG1 {
+				regulator-name = "vcc_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc18_emmc: LDO_REG2 {
+				regulator-name = "vcc18_emmc";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_10: LDO_REG3 {
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+		rockchip,pins =
+			<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdio {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	max-frequency = <150000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+	vmmc-supply = <&vcc_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&u2phy {
+	status = "okay";
+};
+
+&u2phy_host {
+	status = "okay";
+};
+
+&u2phy_otg {
+	status = "okay";
+};
+
+&usb20_otg {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-neo3-rev02.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-neo3-rev02.dts
new file mode 100644
index 000000000000..496e334d3030
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-neo3-rev02.dts
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+	model = "FriendlyElec NanoPi NEO3";
+	compatible = "friendlyelec,nanopi-neo3", "rockchip,rk3328";
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_key1>;
+
+		button@0 {
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+			label = "reset";
+			linux,code = <BTN_1>;
+			linux,input-type = <1>;
+			gpio-key,wakeup = <1>;
+			debounce-interval = <100>;
+		};
+	};
+
+	i2s-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "I2S Out";
+        status = "okay";
+
+		simple-audio-card,cpu {
+				sound-dai = <&i2s1>;
+		};
+
+		simple-audio-card,codec {
+				sound-dai = <&pcm5102>;
+		};
+	};
+
+    pcm5102: pcm510x {
+	    #sound-dai-cells = <0>;
+	    compatible = "ti,pcm5102a";
+	    pcm510x,format = "i2s";
+    };
+
+	sound-spdif {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	vcc_rtl8153: vcc-rtl8153-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb30_en_drv>;
+		regulator-always-on;
+		regulator-name = "vcc_rtl8153";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		off-on-delay-us = <5000>;
+		enable-active-high;
+	};
+};
+
+&mach {
+	hwrev = <2>;
+	model = "NanoPi NEO3";
+};
+
+&i2s1 {
+    rockchip,playback-channels = <2>;
+    pinctrl-names = "default";
+	pinctrl-0 = <&i2s1_mclk
+		     &i2s1_sclk
+		     &i2s1_lrcktx
+		     &i2s1_lrckrx
+		     &i2s1_sdo
+		     &i2s1_sdi>;
+	status = "okay";
+};
+
+&spdif {
+    status = "okay";
+    pinctrl-0 = <&spdifm0_tx>;
+};
+
+&emmc {
+	status = "disabled";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&leds {
+	status = "okay";
+
+};
+
+&leds_gpio {
+	rockchip,pins =
+		<0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&pwm2 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-1 = <&pwm2_sleep_pin>;
+	status = "okay";
+};
+
+&rk805 {
+	interrupt-parent = <&gpio1>;
+	interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&vccio_sd {
+	status = "okay";
+};
+
+&io_domains {
+	vccio3-supply = <&vccio_sd>;
+};
+
+&sdmmc {
+	vqmmc-supply = <&vccio_sd>;
+	max-frequency = <150000000>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc_ext {
+	status = "disabled";
+};
+
+&sdio_pwrseq {
+	status = "disabled";
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pwm {
+		pwm2_sleep_pin: pwm2-sleep-pin {
+			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+	};
+
+	rockchip-key {
+		gpio_key1: gpio-key1 {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		otg_vbus_drv: otg-vbus-drv {
+			rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usb30_en_drv: usb30-en-drv {
+			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&uart1{
+    status = "okay";
+    pinctl-0 = <&uart1_xfer>;
+};
+
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-r2-rev00.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-r2-rev00.dts
new file mode 100644
index 000000000000..8ba95189c031
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-r2-rev00.dts
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R2S";
+	compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_key1>;
+
+		button@0 {
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+			label = "reset";
+			linux,code = <BTN_1>;
+			linux,input-type = <1>;
+			gpio-key,wakeup = <1>;
+			debounce-interval = <100>;
+		};
+	};
+
+	vcc_rtl8153: vcc-rtl8153-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb30_en_drv>;
+		regulator-always-on;
+		regulator-name = "vcc_rtl8153";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		off-on-delay-us = <5000>;
+		enable-active-high;
+	};
+};
+
+&mach {
+	hwrev = <0>;
+	model = "NanoPi R2S";
+};
+
+&emmc {
+	status = "disabled";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&leds {
+	status = "okay";
+
+	led@2 {
+		gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		label = "lan_led";
+	};
+
+	led@3 {
+		gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+		label = "wan_led";
+	};
+};
+
+&rk805 {
+	interrupt-parent = <&gpio1>;
+	interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&vccio_sd {
+	status = "okay";
+};
+
+&io_domains {
+	vccio3-supply = <&vccio_sd>;
+};
+
+&sdmmc {
+	vqmmc-supply = <&vccio_sd>;
+	max-frequency = <150000000>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc_ext {
+	status = "disabled";
+};
+
+&sdio_pwrseq {
+	status = "disabled";
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rockchip-key {
+		gpio_key1: gpio-key1 {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		otg_vbus_drv: otg-vbus-drv {
+			rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usb30_en_drv: usb30-en-drv {
+			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-r2-rev06.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-r2-rev06.dts
new file mode 100644
index 000000000000..5de8b51db0bf
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-r2-rev06.dts
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+/dts-v1/;
+
+#include "rk3328-nanopi-r2-rev00.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R2C";
+	compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
+};
+
+&mach {
+	hwrev = <6>;
+	model = "NanoPi R2C";
+};
+
+&rgmiim1_pins {
+	rockchip,pins =
+		/* mac_txclk */
+		<1 RK_PB4 2 &pcfg_pull_none_8ma>,
+		/* mac_rxclk */
+		<1 RK_PB5 2 &pcfg_pull_none>,
+		/* mac_mdio */
+		<1 RK_PC3 2 &pcfg_pull_none_2ma>,
+		/* mac_txen */
+		<1 RK_PD1 2 &pcfg_pull_none_8ma>,
+		/* mac_clk */
+		<1 RK_PC5 2 &pcfg_pull_none_2ma>,
+		/* mac_rxdv */
+		<1 RK_PC6 2 &pcfg_pull_none>,
+		/* mac_mdc */
+		<1 RK_PC7 2 &pcfg_pull_none_2ma>,
+		/* mac_rxd1 */
+		<1 RK_PB2 2 &pcfg_pull_none>,
+		/* mac_rxd0 */
+		<1 RK_PB3 2 &pcfg_pull_none>,
+		/* mac_txd1 */
+		<1 RK_PB0 2 &pcfg_pull_none_8ma>,
+		/* mac_txd0 */
+		<1 RK_PB1 2 &pcfg_pull_none_8ma>,
+		/* mac_rxd3 */
+		<1 RK_PB6 2 &pcfg_pull_none>,
+		/* mac_rxd2 */
+		<1 RK_PB7 2 &pcfg_pull_none>,
+		/* mac_txd3 */
+		<1 RK_PC0 2 &pcfg_pull_none_8ma>,
+		/* mac_txd2 */
+		<1 RK_PC1 2 &pcfg_pull_none_8ma>,
+
+		/* mac_txclk */
+		<0 RK_PB0 1 &pcfg_pull_none>,
+		/* mac_txen */
+		<0 RK_PB4 1 &pcfg_pull_none>,
+		/* mac_clk */
+		<0 RK_PD0 1 &pcfg_pull_none>,
+		/* mac_txd1 */
+		<0 RK_PC0 1 &pcfg_pull_none>,
+		/* mac_txd0 */
+		<0 RK_PC1 1 &pcfg_pull_none>,
+		/* mac_txd3 */
+		<0 RK_PC7 1 &pcfg_pull_none>,
+		/* mac_txd2 */
+		<0 RK_PC6 1 &pcfg_pull_none>;
+};
+
+/delete-node/ &rtl8211e;
+
+&gmac2io {
+	phy-handle = <&ethphy3>;
+       snps,reset-delays-us = <0 15000 50000>;
+       tx_delay = <0x22>;
+	rx_delay = <0x12>;
+	mdio {
+
+		ethphy3: ethernet-phy@3 {
+			compatible = "ethernet-phy-id0000.011a",
+				     "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+			interrupt-parent = <&gpio2>;
+			interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
+			//reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+			motorcomm,clk-out-frequency-hz = <125000000>; // enable gmac clock
+			motorcomm,keep-pll-enabled; // keep pll run without link
+			motorcomm,auto-sleep-disabled; // disable sleep without link
+			keep-clkout-on;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-r2-rev20.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-r2-rev20.dts
new file mode 100644
index 000000000000..ad327ca56858
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-nanopi-r2-rev20.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+/dts-v1/;
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R2";
+	compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
+};
+
+&mach {
+	hwrev = <0x20>;
+	model = "NanoPi R2";
+};
+
+&gmac2io {
+	pinctrl-0 = <&rgmiim1_pins>, <&phy_intb>, <&phy_rstb>;
+};
+
+&rtl8211e {
+	interrupt-parent = <&gpio1>;
+	interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&pinctrl {
+	phy {
+		phy_intb: phy-intb {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		phy_rstb: phy-rstb {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3328-orangepi-r1-plus-lts.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-orangepi-r1-plus-lts.dts
new file mode 100644
index 000000000000..4e944e0c1908
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,449 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* Copyright (c) 2020 David Bauer <mail@david-bauer.net>
+ * Copyright (c) 2020 Shenzhen Xunlong Software CO.,Limited
+ * Copyright (c) 2021 AmadeusGhost <amadeus@jmu.edu.cn>
+ * Revised for Orange Pi R1 Plus LTS (c) 2022 schwar3kat
+ * Based on Orange Pi R1 plus
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "rk3328.dtsi"
+
+/ {
+	model = "Xunlong Orange Pi R1 Plus LTS";
+	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+
+	aliases {
+		ethernet1 = &rtl8153;
+		mmc0 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac_clk: gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac_clkin";
+		#clock-cells = <0>;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&reset_button_pin>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <50>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
+		pinctrl-names = "default";
+
+		lan_led: led-0 {
+			gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+			label = "orangepi-r1-plus-lts:green:lan";
+		};
+
+		sys_led: led-1 {
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+			label = "orangepi-r1-plus-lts:red:status";
+			linux,default-trigger = "heartbeat";
+		};
+
+		wan_led: led-2 {
+			gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+			label = "orangepi-r1-plus-lts:green:wan";
+		};
+	};
+
+	vcc_io_sdio: sdmmcio-regulator {
+		compatible = "regulator-gpio";
+		enable-active-high;
+		gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&sdio_vcc_pin>;
+		pinctrl-names = "default";
+		regulator-name = "vcc_io_sdio";
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-settling-time-us = <5000>;
+		regulator-type = "voltage";
+		startup-delay-us = <2000>;
+		states = <1800000 0x1>,
+			 <3300000 0x0>;
+		vin-supply = <&vcc_io_33>;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&sdmmc0m1_pin>;
+		pinctrl-names = "default";
+		regulator-name = "vcc_sd";
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_io_33>;
+	};
+
+	vdd_5v: vdd-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vdd_5v_lan: vdd-5v-lan {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&lan_vdd_pin>;
+		pinctrl-names = "default";
+		regulator-name = "vdd_5v_lan";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vdd_5v>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&display_subsystem {
+	status = "disabled";
+};
+
+&gmac2io {
+	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
+	clock_in_out = "input";
+	phy-mode = "rgmii";
+	phy-supply = <&vcc_io_33>;
+	pinctrl-0 = <&rgmiim1_pins>;
+	pinctrl-names = "default";
+	snps,aal;
+	status = "okay";
+	phy-handle = <&yt8531c>;
+	tx_delay = <0x19>;
+	rx_delay = <0x05>;
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		yt8531c: ethernet-phy@0 {
+			compatible = "ethernet-phy-id4f51.e91b",
+				     "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			motorcomm,clk-out-frequency-hz = <125000000>;
+			motorcomm,keep-pll-enabled;
+			motorcomm,auto-sleep-disabled;
+			pinctrl-0 = <&eth_phy_reset_pin>;
+			pinctrl-names = "default";
+			reset-assert-us = <15000>;
+			reset-deassert-us = <50000>;
+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	rk805: pmic@18 {
+		compatible = "rockchip,rk805";
+		reg = <0x18>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk805-clkout2";
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-0 = <&pmic_int_l>;
+		pinctrl-names = "default";
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vdd_5v>;
+		vcc2-supply = <&vdd_5v>;
+		vcc3-supply = <&vdd_5v>;
+		vcc4-supply = <&vdd_5v>;
+		vcc5-supply = <&vcc_io_33>;
+		vcc6-supply = <&vdd_5v>;
+
+		regulators {
+			vdd_log: DCDC_REG1 {
+				regulator-name = "vdd_log";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vdd_arm: DCDC_REG2 {
+				regulator-name = "vdd_arm";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io_33: DCDC_REG4 {
+				regulator-name = "vcc_io_33";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_18: LDO_REG1 {
+				regulator-name = "vcc_18";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc18_emmc: LDO_REG2 {
+				regulator-name = "vcc18_emmc";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_10: LDO_REG3 {
+				regulator-name = "vdd_10";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+		};
+	};
+};
+
+&io_domains {
+	pmuio-supply = <&vcc_io_33>;
+	vccio1-supply = <&vcc_io_33>;
+	vccio2-supply = <&vcc18_emmc>;
+	vccio3-supply = <&vcc_io_sdio>;
+	vccio4-supply = <&vcc_18>;
+	vccio5-supply = <&vcc_io_33>;
+	vccio6-supply = <&vcc_io_33>;
+	status = "okay";
+};
+
+&pinctrl {
+	button {
+		reset_button_pin: reset-button-pin {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac2io {
+		eth_phy_reset_pin: eth-phy-reset-pin {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	leds {
+		lan_led_pin: lan-led-pin {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		sys_led_pin: sys-led-pin {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_pin: wan-led-pin {
+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	lan {
+		lan_vdd_pin: lan-vdd-pin {
+			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sd {
+		sdio_vcc_pin: sdio-vcc-pin {
+			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+	pinctrl-names = "default";
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vcc_io_sdio>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&u2phy {
+	status = "okay";
+};
+
+&u2phy_host {
+	status = "okay";
+};
+
+&u2phy_otg {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb20_otg {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3 {
+	dr_mode = "host";
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	snps,xhci-trb-ent-quirk;
+
+	/* Second port is for USB 3.0 */
+	rtl8153: device@2 {
+		compatible = "usbbda,8153";
+		reg = <2>;
+		realtek,led-data = <0x87>;
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&spi0 {
+	max-freq = <48000000>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&dmc_opp_table {
+	opp-798000000 {
+		status = "disabled";
+	};
+	opp-840000000 {
+		status = "disabled";
+	};
+	opp-924000000 {
+		status = "disabled";
+	};
+	opp-1056000000 {
+		status = "disabled";
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3328-z28pro.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-z28pro.dts
new file mode 100644
index 000000000000..0b2e21a13990
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3328-z28pro.dts
@@ -0,0 +1 @@
+#include "rk3328-rock64.dts"
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3399-fine3399.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-fine3399.dts
new file mode 100644
index 000000000000..9022e0195531
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-fine3399.dts
@@ -0,0 +1,797 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+
+/ {
+	model = "Rockchip Fine3399";
+	compatible = "rockchip,fine3399", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdio0;
+		mmc1 = &sdmmc;
+		mmc2 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; // bsp
+	};
+
+	/* switched by pmic_sleep */
+	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v3_sys: vcc3v3_pcie: vcc3v3_bl: vcc3v3-sys { // sch
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc_sys: vcc-sys { // sch
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_phy_h>;
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	leds: gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_led2>;
+
+		user_led2 {
+			label = "blue:work_led";
+			gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; // sch
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&power_key>;
+
+		power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; // bsp
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	fan0: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 150 200 255>;
+		#cooling-cells = <2>;
+		fan-supply = <&vcc_sys>;
+		pwms = <&pwm1 0 40000 0>;
+	};
+
+	// pwm3
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_int>;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1750000>;
+		poll-interval = <100>;
+
+		recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>; // ??
+			press-threshold-microvolt = <0>;
+		};
+	};
+
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&cpu_thermal {
+	trips {
+		cpu_hot: cpu_hot {
+			hysteresis = <10000>;
+			temperature = <55000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map2 {
+			cooling-device =
+				<&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu_hot>;
+		};
+	};
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; // bsp
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc1v8_pmu>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_tp: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc3v0_tp";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sd: LDO_REG4 {
+				regulator-name = "vcc_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cpu_b_sleep>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpu_sleep>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+// Used for HDMI
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+// HDMI sound
+&i2s2 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc_3v0>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sd>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_1v8>;
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pcie0 {
+	ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; // sch
+	max-link-speed = <2>;
+	num-lanes = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqn_cpm>;
+	status = "okay";
+};
+
+&pinctrl {
+	pmic {
+		cpu_b_sleep: cpu-b-sleep {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		gpu_sleep: gpu-sleep {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		pmic_dvs2: pmic-dvs2 {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_reg_on_h: wifi-reg-on-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifi {
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac {
+		vcc_phy_h: vcc-phy-h {
+			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+		user_led2: user_led2 {
+			rockchip,pins =
+				<2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	buttons {
+		power_key: power_key {
+			rockchip,pins = 
+				<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+/*
+// TFT
+&pwm0 {
+	status = "okay";
+};
+*/
+// FAN
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca1v8_s3>;
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	clock-frequency = <50000000>;
+	disable-wp;
+	keep-power-in-suspend;
+	max-frequency = <50000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+		interrupt-names = "host-wake";
+		brcm,drive-strength = <5>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // bsp
+	clock-frequency = <150000000>;
+	disable-wp;
+	sd-uhs-sdr104;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	vqmmc-supply = <&vcc_sd>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	keep-power-in-suspend;
+	non-removable;
+	status = "okay";
+};
+/*
+&spi1 {
+	status = "okay";
+
+	norflash: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+	};
+};
+*/
+/*
+&spi2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_clk &spi2_tx &spi2_cs0>;
+
+	panel@0 {
+		compatible = "sitronix,st7789v";
+		reg = <0>;
+		// backlight = <&pwm0>;
+		dc-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
+		led-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;  
+		spi-max-frequency = <15000000>;
+		spi-cs-high;
+		status = "okay";
+	};
+};
+*/
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk808 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		max-speed = <4000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+	};
+};
+
+// Debug TTL
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3399-nanopi-m4v2.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-nanopi-m4v2.dts
new file mode 100644
index 000000000000..094440ce38ad
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-nanopi-m4v2.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPi M4V2 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+	model = "FriendlyElec NanoPi M4 Ver2.0";
+	compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
+
+	vdd_5v: vdd-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_5v";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_core: vcc5v0-core {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_core";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vdd_5v>;
+	};
+
+	vcc5v0_usb1: vcc5v0-usb1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb1";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb2: vcc5v0-usb2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb2";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-init-microvolt = <900000>;
+		vin-supply = <&vcc5v0_core>;
+	};
+};
+
+&gmac {
+	rx_delay = <0x16>;
+};
+
+&rk808 {
+	max-buck-steps-per-change = <4>;
+};
+
+&vcc3v3_sys {
+	vin-supply = <&vcc5v0_core>;
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_usb1>;
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_usb2>;
+};
+
+&vbus_typec {
+	regulator-always-on;
+	vin-supply = <&vdd_5v>;
+};
+
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3399-nanopi-r4se.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-nanopi-r4se.dts
new file mode 100644
index 000000000000..1c9d0c34f151
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-nanopi-r4se.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3399-nanopi-r4s-enterprise.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R4SE";
+	compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&sdhci {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3399-orangepi-4-lts.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-orangepi-4-lts.dts
new file mode 100644
index 000000000000..2f0baf9fd43b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-orangepi-4-lts.dts
@@ -0,0 +1,1334 @@
+/*
+ * SPDX-License-Identifier: (GPL-2.0+ or MIT)
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
+ * Copyright (c) 2020-2022 Armbian (chwe17, piter75, jock)
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	model = "OrangePi 4 LTS";
+	compatible = "xunlong,orangepi-4-lts", "rockchip,rk3399";
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	aliases {
+		spi1 = &spi1;
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	usb_vbus: usb-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	usb3_vbus: usb3-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb3_vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	vbus_typec: vbus-typec {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec_en>;
+		regulator-name = "vbus-5v";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	/* 0.9 V supply, over PMIC
+	vcc_0v9: vcc-0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	}
+	*/
+
+	vcc3v0_sd: vcc3v0-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwr>;
+		regulator-name = "vcc3v0_sd";
+		regulator-always-on;
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_drv>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc3v3_pcie";
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	es8316c_card: es8316c-card {
+		compatible = "simple-audio-card";
+
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "rockchip-es8316c";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Headphone", "Headphones";
+
+		simple-audio-card,routing =
+			"MIC1", "Mic Jack",
+			"Headphones", "HPOL",
+			"Headphones", "HPOR";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&es8316c_codec>;
+		};
+
+	};
+
+	hdmi-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "hdmi-sound";
+		status = "okay";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s2>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&hdmi>;
+		};
+	};
+
+	spdif-sound {
+		status = "disable";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "ROCKCHIP,SPDIF";
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+		status = "disable";
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	pwm_bl: backlight {
+		status = "disable";
+		compatible = "pwm-backlight";
+		pwms = <&pwm0 0 25000 0>;
+		brightness-levels = <
+			  0   1   2   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255>;
+		default-brightness-level = <200>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&power_key>;
+
+		button@0 {
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			label = "GPIO Key Power";
+			linux,input-type = <1>;
+			gpio-key,wakeup = <1>;
+			debounce-interval = <100>;
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		poll-interval = <100>;
+		keyup-threshold-microvolt = <1800000>;
+
+		button-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <100000>;
+		};
+
+		button-down {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <300000>;
+		};
+	};
+
+	leds: gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 =<&leds_gpio>;
+
+		led@1 {
+			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+			label = "status_led";
+			linux,default-trigger = "heartbeat";
+			linux,default-trigger-delay-ms = <0>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
+	};
+
+	unisoc_uwe_bsp: uwe-bsp {
+		compatible = "unisoc,uwe_bsp";
+		//wl-reg-on = <&gpio0 10 GPIO_ACTIVE_HIGH>;  // handled by sdio-pwrseq
+		bt-reg-on = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+		wl-wake-host-gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+		bt-wake-host-gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+		sdio-ext-int-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+		unisoc,btwf-file-name = "/lib/firmware/uwe5622/wcnmodem-38222.bin";
+		data-irq;
+		blksz-512;
+		keep-power-on;
+		status = "okay";
+	};
+
+	sprd-wlan {
+		compatible = "sprd,uwe5622-wifi";
+		status = "okay";
+	};
+
+	sprd-mtty {
+		compatible = "sprd,mtty";
+		sprd,name = "ttyBT";
+		status = "okay";
+	};
+
+	dmc_opp_table: dmc_opp_table {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <328000000>;
+			opp-microvolt = <900000>;
+		};
+
+		opp01 {
+			opp-hz = /bits/ 64 <416000000>;
+			opp-microvolt = <900000>;
+		};
+
+		opp02 {
+			opp-hz = /bits/ 64 <666000000>;
+			opp-microvolt = <900000>;
+		};
+
+	};
+
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+	status = "okay";
+	mali-supply = <&vdd_gpu>;
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rstb>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc3v3_s3>;
+	phy-handle = <&yt8531c>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+        	#address-cells = <1>;
+	        #size-cells = <0>;
+	        yt8531c: ethernet-phy@0 {
+			compatible = "ethernet-phy-id4f51.e91b",
+				     "ethernet-phy-ieee802.3-c22";
+            		reg = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&phy_intb>;
+            		motorcomm,clk-out-frequency-hz = <125000000>;
+            		motorcomm,keep-pll-enabled;
+            		motorcomm,auto-sleep-disabled;
+			interrupt-parent = <&gpio3>;
+			interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+        	};
+    	};
+
+};
+
+&spi1 {
+	status = "disable";
+	pinctrl-names = "default", "sleep";
+	pinctrl-1 = <&spi1_gpio>;
+
+	spidev0: spidev@0 {
+		compatible = "rockchip,spidev";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+};
+
+&rga {
+	status = "okay";
+};
+
+&cdn_dp {
+	status = "okay";
+	extcon = <&fusb0>;
+	phys = <&tcphy0_dp>;
+};
+
+&hdmi {
+	/* remove the hdmi_i2c_xfer */
+	pinctrl-0 = <&hdmi_cec>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	#sound-dai-cells = <0>;
+	status = "okay";
+	ddc-i2c-bus = <&i2c7>;
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vcc13-supply = <&vcc3v3_sys>;
+		vcc14-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc1v8: vcc1v8_s3: vcca1v8_s3: DCDC_REG4 {
+				regulator-name = "vcc1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_touch: LDO_REG2 {
+				regulator-name = "vcc3v0_touch";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-init-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_gpio>;
+		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_gpio>;
+		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <200000>;
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	es8316c_codec: es8316c@11 {
+		#sound-dai-cells = <0>;
+		compatible = "everest,es8316";
+		reg = <17>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		//pinctrl-names = "default";
+		//pinctrl-0 = <&i2s_8ch_mclk>;
+		status = "okay";
+	};
+
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	clock-frequency = <400000>;
+
+	fusb0: fusb30x@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+		vbus-supply = <&vbus_typec>;
+		status = "okay";
+
+		connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			op-sink-microwatt = <1000000>;
+			power-role = "dual";
+			sink-pdos =
+				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+			try-power-role = "sink";
+
+			extcon-cables = <1 2 5 6 9 10 12 44>;
+			typec-altmodes = <0xff01 1 0x001c0000 1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc_hs: endpoint {
+						remote-endpoint =
+							<&u2phy0_typec_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc_ss: endpoint {
+						remote-endpoint =
+							<&tcphy0_typec_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					usbc_dp: endpoint {
+						remote-endpoint =
+							<&tcphy0_typec_dp>;
+					};
+				};
+			};
+		};
+
+	};
+
+	ft5x06_ts@38 {
+		compatible = "edt,edt-ft5x06", "ft5x06";
+		reg = <0x38>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
+		status = "okay";
+	};
+
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&spdif {
+	status = "disable";
+	pinctrl-0 = <&spdif_bus>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	#sound-dai-cells = <0>;
+};
+
+&i2s0 {
+	rockchip,i2s-broken-burst-len;
+	assigned-clocks = <&cru SCLK_I2SOUT_SRC>;
+	assigned-clock-parents = <&cru SCLK_I2S0_8CH>;
+	resets = <&cru SRST_I2S0_8CH>, <&cru SRST_H_I2S0_8CH>;
+	reset-names = "reset-m", "reset-h";
+	rockchip,playback-channels = <2>;
+	rockchip,capture-channels = <2>;
+	status = "okay";
+	#sound-dai-cells = <0>;
+};
+
+&i2s2 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc1v8_dvp>;		/* bt656_gpio2ab_ms */
+	audio-supply = <&vcca1v8_codec>;	/* audio_gpio3d4a_ms */
+	sdmmc-supply = <&vcc_sdio>;		/* sdmmc_gpio4b_ms */
+	gpio1830-supply = <&vcc_3v0>;		/* gpio1833_gpio4cd_ms */
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pcie_phy {
+	status = "okay";
+	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+	assigned-clock-rates = <100000000>;
+};
+
+&pcie0 {
+	status = "okay";
+	ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+	num-lanes = <4>;
+	max-link-speed = <1>;
+};
+
+&pwm_bl {
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm2_pin_pull_down>;
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vcca1v8_s3>; /* TBD */
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	supports-emmc;
+	non-removable;
+	keep-power-in-suspend;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&sdio0 {
+	clock-frequency = <150000000>;
+	max-frequency = <150000000>;
+	supports-sdio;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	cd-debounce-delay-ms = <500>;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v0_sd>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&tcphy0 {
+	extcon = <&fusb0>;
+	status = "okay";
+};
+
+&tcphy0_dp {
+	port {
+		tcphy0_typec_dp: endpoint {
+			remote-endpoint = <&usbc_dp>;
+		};
+	};
+};
+
+&tcphy0_usb3 {
+	port {
+		tcphy0_typec_ss: endpoint {
+			remote-endpoint = <&usbc_ss>;
+		};
+	};
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&usb3_vbus>;
+		status = "okay";
+	};
+
+	port {
+		u2phy0_typec_hs: endpoint {
+			remote-endpoint = <&usbc_hs>;
+		};
+	};
+
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&usb_vbus>;
+		status = "okay";
+	};
+};
+
+&usbdrd3_0 {
+	status = "okay";
+	extcon = <&fusb0>;
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&sdmmc_bus4 {
+	rockchip,pins =
+		<4 RK_PB0 1 &pcfg_pull_up_12ma>,
+		<4 RK_PB1 1 &pcfg_pull_up_12ma>,
+		<4 RK_PB2 1 &pcfg_pull_up_12ma>,
+		<4 RK_PB3 1 &pcfg_pull_up_12ma>;
+};
+
+&sdmmc_cmd {
+	rockchip,pins =
+		<4 RK_PB5 1 &pcfg_pull_up_12ma>;
+};
+
+&pinctrl {
+
+	pcfg_pull_up_12ma: pcfg-pull-up-12ma {
+		bias-pull-up;
+		drive-strength = <12>;
+	};
+
+	pcie {
+		pcie_drv: pcie-drv {
+			rockchip,pins =
+				<1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	hdmi {
+		/delete-node/ hdmi-i2c-xfer;
+	};
+
+	i2s0 {
+		i2s_8ch_mclk: i2s-8ch-mclk {
+			rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_gpio: vsel1-gpio {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_gpio: vsel2-gpio {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	usb-typec {
+		vcc5v0_typec_en: vcc5v0_typec_en {
+			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wireless-bluetooth {
+		uart0_gpios: uart0-gpios {
+			rockchip,pins = <2 19 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rockchip-key {
+		power_key: power-key {
+			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gpio-leds {
+		leds_gpio: leds-gpio {
+			rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	cam_pins {
+		cif_clkout_a: cif-clkout-a {
+			rockchip,pins = <2 11 3 &pcfg_pull_none>;
+		};
+
+		cif_clkout_a_sleep: cif-clkout-a-sleep {
+			rockchip,pins = <2 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		cam0_default_pins: cam0-default-pins {
+			rockchip,pins =
+				<4 27 0 &pcfg_pull_down>,
+				<2 11 3 &pcfg_pull_none>;
+		};
+
+		cam0_sleep_pins: cam0-sleep-pins {
+			rockchip,pins =
+			<4 27 3 &pcfg_pull_none>,
+			<2 11 0 &pcfg_pull_none>;
+		};
+
+		cam1_default_pins: cam1-default-pins {
+			rockchip,pins =
+				<0 12 RK_FUNC_GPIO &pcfg_pull_down>,
+				<0  8 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	spi1 {
+		spi1_gpio: spi1-gpio {
+			rockchip,pins =
+				<1 7 RK_FUNC_GPIO &pcfg_output_low>,
+				<1 8 RK_FUNC_GPIO &pcfg_output_low>,
+				<1 9 RK_FUNC_GPIO &pcfg_output_low>,
+				<1 10 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+	};
+
+	bt {
+		bt_host_wake: bt-host-wake {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_reset: bt-reset {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake: bt-wake {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac {
+		phy_intb: phy-intb {
+			rockchip,pins = <3 RK_PB2 1 &pcfg_pull_up>;
+		};
+
+		phy_rstb: phy-rstb {
+			rockchip,pins = <3 RK_PB7 1 &pcfg_pull_none>;
+		};
+	};
+
+};
+
+&hdmi_in_vopb {
+	status = "okay";
+};
+
+&hdmi_in_vopl {
+	status = "disable";
+};
+
+&dp_in_vopb {
+	status = "disable";
+};
+&dp_in_vopl {
+	status = "okay";
+};
+
+&dmc {
+	#cooling-cells = <2>; /* min followed by max */
+
+	status = "okay";
+	center-supply = <&vdd_log>;
+	operating-points-v2 = <&dmc_opp_table>;
+
+	rockchip,pd-idle-ns = <160>;
+	rockchip,sr-idle-ns = <10240>;
+	rockchip,sr-mc-gate-idle-ns = <40960>;
+	rockchip,srpd-lite-idle-ns = <61440>;
+	rockchip,standby-idle-ns = <81920>;
+
+	rockchip,ddr3_odt_dis_freq = <666000000>;
+	rockchip,lpddr3_odt_dis_freq = <666000000>;
+	rockchip,lpddr4_odt_dis_freq = <666000000>;
+
+	rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
+	rockchip,srpd-lite-idle-dis-freq-hz = <0>;
+	rockchip,standby-idle-dis-freq-hz = <928000000>;
+
+};
+
+&dfi {
+	status = "okay";
+};
+
+/*
+ * Redefine some parameters for the thermal trip points for Opi4 LTS.
+ * First of all, the Soc does not like getting over 90°C. My sample
+ * froze at 94.4°C, so we lower the critical temprature to 90°C, hopefully
+ * giving enough room for safe reboot of the device.
+ * Big cores are getting throttled a bit when reaching 82°C, then at 85°C
+ * we aggressively throttle all the cores and even the memory controller.
+ * The GPU is handled by existing trip points in the base device tree, here
+ * we just set the same critical temperature as CPU.
+ */
+&cpu_alert0 {
+	temperature = <82000>;
+};
+
+&cpu_alert1 {
+	temperature = <85000>;
+};
+
+&cpu_crit {
+	temperatue = <90000>;
+};
+
+&gpu_crit {
+	temperatue = <90000>;
+};
+
+&cpu_thermal {
+
+	cooling-maps {
+
+		map0 {
+			trip = <&cpu_alert0>;
+			cooling-device =
+				<&cpu_b0 THERMAL_NO_LIMIT 3>,
+				<&cpu_b1 THERMAL_NO_LIMIT 3>;
+		};
+
+		map1 {
+			trip = <&cpu_alert1>;
+			cooling-device =
+				<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+				<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+
+		map2 {
+			trip = <&cpu_alert1>;
+			cooling-device =
+				<&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3399-orangepi-4.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-orangepi-4.dts
new file mode 100644
index 000000000000..976d3f9964f3
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-orangepi-4.dts
@@ -0,0 +1,1194 @@
+/*
+ * SPDX-License-Identifier: (GPL-2.0+ or MIT)
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
+ * Copyright (c) 2020 Armbian (chwe17, piter75)
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+//#include <dt-bindings/leds/common.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	model = "OrangePi 4";
+	compatible = "xunlong,orangepi-4", "rockchip,rk3399";
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	aliases {
+		spi1 = &spi1;
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	usb_vbus: usb-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	usb3_vbus: usb3-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb3_vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	vbus_typec: vbus-typec {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec_en>;
+		regulator-name = "vbus_typec";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	/* 0.9 V supply, over PMIC
+	vcc_0v9: vcc-0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	}
+	*/
+
+	vcc3v0_sd: vcc3v0-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0_pwr_h>;
+		regulator-name = "vcc3v0_sd";
+		regulator-always-on;
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_drv>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc3v3_pcie";
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	rt5651_card: rt5651-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+
+		simple-audio-card,name = "realtek,rt5651-codec";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Headphone", "Headphone Jack";
+		simple-audio-card,routing =
+			"Mic Jack", "micbias1",
+			"IN2P", "Mic Jack",
+			"IN3P", "Mic Jack",
+			"Headphone Jack", "HPOL",
+			"Headphone Jack", "HPOR";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rt5651>;
+		};
+	};
+
+	dw_hdmi_audio: dw-hdmi-audio {
+		status = "disable";
+		compatible = "rockchip,dw-hdmi-audio";
+		#sound-dai-cells = <0>;
+	};
+
+	hdmi_sound: hdmi-sound {
+		status = "okay";
+	};
+
+        hdmi_dp_sound: hdmi-dp-sound {
+                status = "okay";
+                compatible = "rockchip,rk3399-hdmi-dp";
+                rockchip,cpu = <&i2s2>;
+                rockchip,codec = <&hdmi>, <&cdn_dp>;
+        };
+
+	spdif-sound {
+		status = "disable";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "ROCKCHIP,SPDIF";
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+		status = "disable";
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	pwm_bl: backlight {
+		status = "disable";
+		compatible = "pwm-backlight";
+		pwms = <&pwm0 0 25000 0>;
+		brightness-levels = <
+			  0   1   2   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255>;
+		default-brightness-level = <200>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&power_key>;
+
+		button@0 {
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			label = "GPIO Key Power";
+			linux,input-type = <1>;
+			gpio-key,wakeup = <1>;
+			debounce-interval = <100>;
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		poll-interval = <100>;
+		keyup-threshold-microvolt = <1800000>;
+
+		button-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <100000>;
+		};
+
+		button-down {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <300000>;
+		};
+	};
+
+	leds: gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 =<&leds_gpio>;
+
+		led@1 {
+			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+			label = "status_led";
+			linux,default-trigger = "heartbeat";
+			linux,default-trigger-delay-ms = <0>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+	status = "okay";
+	mali-supply = <&vdd_gpu>;
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc3v3_s3>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&spi1 {
+	status = "disable";
+	pinctrl-names = "default", "sleep";
+	pinctrl-1 = <&spi1_gpio>;
+
+	spidev0: spidev@0 {
+		compatible = "rockchip,spidev";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+		status = "okay";
+	};
+};
+/*
+&spi1 {
+    status = "okay";
+    max-freq = <48000000>;
+    spidev@00 {
+        compatible = "linux,spidev";
+        reg = <0x00>;
+        spi-max-frequency = <48000000>;
+    };
+};
+*/
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		clocks = <&rk808 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		max-speed = <1500000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake &bt_wake &bt_reset>;
+	};
+
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+	/* 0 means ion, 1 means drm */
+	//allocator = <0>;
+};
+
+&rga {
+	status = "disabled";
+};
+
+&cdn_dp {
+	status = "okay";
+	extcon = <&fusb0>;
+	phys = <&tcphy0_dp>;
+};
+
+&hdmi {
+	/* remove the hdmi_i2c_xfer */
+	pinctrl-0 = <&hdmi_cec>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	#sound-dai-cells = <0>;
+	status = "okay";
+	ddc-i2c-bus = <&i2c7>;
+	rockchip,defaultmode = <16>; /* CEA 1920x1080@60Hz */
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vcc13-supply = <&vcc3v3_sys>;
+		vcc14-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc1v8: vcc1v8_s3: vcca1v8_s3: DCDC_REG4 {
+				regulator-name = "vcc1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_touch: LDO_REG2 {
+				regulator-name = "vcc3v0_touch";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-init-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_gpio>;
+		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_gpio>;
+		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	clock-frequency = <200000>;
+
+	rt5651: rt5651@1a {
+		#sound-dai-cells = <0>;
+		compatible = "realtek,rt5651";
+		reg = <0x1a>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		status = "okay";
+	};
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	clock-frequency = <400000>;
+
+	fusb0: fusb30x@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+		vbus-supply = <&vbus_typec>;
+		status = "okay";
+
+		connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			op-sink-microwatt = <1000000>;
+			power-role = "dual";
+			sink-pdos =
+				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+			try-power-role = "sink";
+
+			extcon-cables = <1 2 5 6 9 10 12 44>;
+			typec-altmodes = <0xff01 1 0x001c0000 1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc_hs: endpoint {
+						remote-endpoint =
+							<&u2phy0_typec_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc_ss: endpoint {
+						remote-endpoint =
+							<&tcphy0_typec_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					usbc_dp: endpoint {
+						remote-endpoint =
+							<&tcphy0_typec_dp>;
+					};
+				};
+			};
+		};
+
+	};
+
+	ft5x06_ts@38 {
+		compatible = "edt,edt-ft5x06", "ft5x06";
+		reg = <0x38>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
+		status = "okay";
+	};
+
+	/*
+	onewire_ts@2f {
+		compatible = "onewire";
+		reg = <0x2f>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
+	}; */
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&spdif {
+	status = "disable";
+	pinctrl-0 = <&spdif_bus>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	#sound-dai-cells = <0>;
+};
+
+&i2s1 {
+	assigned-clocks = <&cru SCLK_I2SOUT_SRC>;
+	assigned-clock-parents = <&cru SCLK_I2S1_8CH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s_8ch_mclk>,<&i2s1_2ch_bus>;
+	rockchip,playback-channels = <2>;
+	rockchip,capture-channels = <2>;
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+/*
+&i2s0 {
+	assigned-clocks = <&cru SCLK_I2S1_DIV>;
+	assigned-clock-parents = <&cru PLL_GPLL>;
+};*/
+
+&i2s2 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc1v8_dvp>;		/* bt656_gpio2ab_ms */
+	audio-supply = <&vcca1v8_codec>;	/* audio_gpio3d4a_ms */
+	sdmmc-supply = <&vcc_sdio>;		/* sdmmc_gpio4b_ms */
+	gpio1830-supply = <&vcc_3v0>;		/* gpio1833_gpio4cd_ms */
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pcie_phy {
+	status = "okay";
+	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+	assigned-clock-rates = <100000000>;
+};
+
+&pcie0 {
+	status = "okay";
+	ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+	num-lanes = <4>;
+	max-link-speed = <1>;
+};
+
+&pwm_bl {
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm2_pin_pull_down>;
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vcca1v8_s3>; /* TBD */
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	supports-emmc;
+	non-removable;
+	keep-power-in-suspend;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&sdio0 {
+	clock-frequency = <50000000>;
+	clock-freq-min-max = <200000 50000000>;
+	supports-sdio;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
+//	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v0_sd>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&tcphy0 {
+	extcon = <&fusb0>;
+	status = "okay";
+};
+
+&tcphy0_dp {
+	port {
+		tcphy0_typec_dp: endpoint {
+			remote-endpoint = <&usbc_dp>;
+		};
+	};
+};
+
+&tcphy0_usb3 {
+	port {
+		tcphy0_typec_ss: endpoint {
+			remote-endpoint = <&usbc_ss>;
+		};
+	};
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&usb3_vbus>;
+		status = "okay";
+	};
+
+	port {
+		u2phy0_typec_hs: endpoint {
+			remote-endpoint = <&usbc_hs>;
+		};
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&usb_vbus>;
+		status = "okay";
+	};
+};
+
+&usbdrd3_0 {
+	status = "okay";
+	extcon = <&fusb0>;
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&pinctrl {
+	pcie {
+		pcie_drv: pcie-drv {
+			rockchip,pins =
+				<1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	hdmi {
+		/delete-node/ hdmi-i2c-xfer;
+	};
+
+	i2s1 {
+		i2s_8ch_mclk: i2s-8ch-mclk {
+			rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_gpio: vsel1-gpio {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_gpio: vsel2-gpio {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	sdmmc {
+		sdmmc0_det_l: sdmmc0-det-l {
+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		sdmmc0_pwr_h: sdmmc0-pwr-h {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb-typec {
+		vcc5v0_typec_en: vcc5v0_typec_en {
+			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wireless-bluetooth {
+		uart0_gpios: uart0-gpios {
+			rockchip,pins = <2 19 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rockchip-key {
+		power_key: power-key {
+			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gpio-leds {
+		leds_gpio: leds-gpio {
+			rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	cam_pins {
+		cif_clkout_a: cif-clkout-a {
+			rockchip,pins = <2 11 3 &pcfg_pull_none>;
+		};
+
+		cif_clkout_a_sleep: cif-clkout-a-sleep {
+			rockchip,pins = <2 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		cam0_default_pins: cam0-default-pins {
+			rockchip,pins =
+				<4 27 0 &pcfg_pull_down>,
+				<2 11 3 &pcfg_pull_none>;
+		};
+		cam0_sleep_pins: cam0-sleep-pins {
+   			rockchip,pins =
+    			<4 27 3 &pcfg_pull_none>,
+		    	<2 11 0 &pcfg_pull_none>;
+ 		 };
+
+		cam1_default_pins: cam1-default-pins {
+			rockchip,pins =
+				<0 12 RK_FUNC_GPIO &pcfg_pull_down>,
+				<0  8 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	spi1 {
+		spi1_gpio: spi1-gpio {
+			rockchip,pins =
+				<1 7 RK_FUNC_GPIO &pcfg_output_low>,
+				<1 8 RK_FUNC_GPIO &pcfg_output_low>,
+				<1 9 RK_FUNC_GPIO &pcfg_output_low>,
+				<1 10 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+	};
+
+	bt {
+		bt_host_wake: bt-host-wake {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_reset: bt-reset {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake: bt-wake {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+};
+
+&hdmi_in_vopb {
+	status = "okay";
+};
+
+&hdmi_in_vopl {
+	status = "disable";
+};
+
+&dp_in_vopb {
+	status = "disable";
+};
+&dp_in_vopl {
+	status = "okay";
+};
+
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3399-rock-pi-4.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-rock-pi-4.dts
new file mode 100644
index 000000000000..8d0aa5346293
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-rock-pi-4.dts
@@ -0,0 +1 @@
+#include "rk3399-rock-pi-4b.dts"
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3399-rock-pi-4c.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-rock-pi-4c.dts
new file mode 100644
index 000000000000..4053ba72618c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-rock-pi-4c.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2019 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "rk3399-rock-pi-4.dtsi"
+
+/ {
+	model = "Radxa ROCK Pi 4C";
+	compatible = "radxa,rockpi4c", "radxa,rockpi4", "rockchip,rk3399";
+
+	aliases {
+		mmc2 = &sdio0;
+	};
+};
+
+&es8316 {
+	pinctrl-0 = <&hp_detect &hp_int>;
+	pinctrl-names = "default";
+	interrupt-parent = <&gpio1>;
+	interrupts = <RK_PA1 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sdio0 {
+	status = "okay";
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm4329-fmac";
+		reg = <1>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+	};
+};
+
+&sound {
+	hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+};
+
+&uart0 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		clocks = <&rk808 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		max-speed = <1500000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+	};
+};
+
+&vcc5v0_host {
+	gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+};
+
+&vcc5v0_host_en {
+	rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3399-tinker-2.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-tinker-2.dts
new file mode 100644
index 000000000000..0f4b28ae0118
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-tinker-2.dts
@@ -0,0 +1,751 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2021 Thomas McKahan
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3399.dtsi"
+#include "rk3399-op1-opp.dtsi"
+
+/ {
+	model = "Asus Tinker Board 2/2S";
+	compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+	
+	board_info: board-info {
+		compatible = "board-info";
+
+		hw-id0 = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+		hw-id1 = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+		hw-id2 = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+
+		pid-id0 = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pid-id1 = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pid-id2 = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
+
+		ddr-id1 = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+		ddr-id2 = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
+
+		pmic-reset = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+	};
+	
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+	
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		pwr-led {
+			gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-on";
+			retain-state-suspended = <1>;
+		};
+
+		act-led {
+			gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger="mmc0";
+		};
+
+		rsv-led {
+			gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger="heartbeat";
+		};
+	};
+	
+	vcc_lcd: vcc-lcd {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_lcd";
+		gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <20000>;
+		enable-active-high;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+	
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+	
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+	
+	vbus_typec: vbus-5vout {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec0_en_pin>;
+		regulator-name = "vbus_5vout";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+	
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-always-on;
+		regulator-boot-on;
+
+		/* for rockchip boot on */
+		rockchip,pwm_id= <2>;
+		rockchip,pwm_voltage = <900000>;
+	};
+	
+	xin32k: xin32k {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		#clock-cells = <0>;
+	};
+};
+
+&cdn_dp {
+	status = "okay";
+	extcon = <&fusb0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&cru SCLK_MAC>;
+	clock_in_out = "input";
+	assigned-clock-rates = <125000000>;
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 16000 72000>;
+	tx_delay = <0x25>;
+	rx_delay = <0x20>;
+	wakeup-enable = "0";
+	status = "okay";
+};
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc1v8_pmu>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc3v3_dsi: LDO_REG1 {
+				regulator-name = "vcc3v3_dsi";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_hdmi: LDO_REG2 {
+				regulator-name = "vcca1v8_hdmi";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vccio_sd: LDO_REG4 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_csi: LDO_REG5 {
+				regulator-name = "vcc3v3_csi";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca0v9_hdmi: LDO_REG7 {
+				regulator-name = "vcca0v9_hdmi";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: vdd_cpu_b@60 {
+		compatible = "fcs,fan53200";
+		reg = <0x60>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-regulator";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_gpio>;
+		vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1250000>;
+		regulator-ramp-delay = <1000>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		status = "okay";
+		
+		regulator-initial-state = <3>;
+			regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c3 { 
+	status = "okay";
+};
+
+&i2c4 {
+
+	status = "okay";
+	i2c-scl-rising-time-ns = <475>;
+	i2c-scl-falling-time-ns = <26>;
+	fusb0: fusb30x@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+		vbus-supply = <&vbus_typec>;
+		status = "okay";
+		
+		connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			op-sink-microwatt = <1000000>;
+			power-role = "dual";
+			sink-pdos =
+				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+			try-power-role = "sink";
+
+			extcon-cables = <1 2 5 6 9 10 12 44>;
+			typec-altmodes = <0xff01 1 0x001c0000 1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc_hs: endpoint {
+						remote-endpoint =
+							<&u2phy0_typec_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc_ss: endpoint {
+						remote-endpoint =
+							<&tcphy0_typec_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					usbc_dp: endpoint {
+						remote-endpoint =
+							<&tcphy0_typec_dp>;
+					};
+				};
+			};
+		};
+		
+		
+		
+		
+	};
+	
+	vdd_gpu: vdd_gpu@60 {
+		compatible = "fcs,fan53200";
+		reg = <0x60>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-regulator";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_gpio>;
+		vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-ramp-delay = <1000>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		status = "okay";
+		
+		regulator-initial-state = <3>;
+			regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};	
+
+&i2c8 {
+
+	m24c08: m24c08@50 {
+		compatible = "atmel,24c08";
+		reg = <0x50>;
+	};
+};
+
+&i2s0 {
+	rockchip,playback-channels = <8>;
+	rockchip,capture-channels = <8>;
+	status = "okay";
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pcie0 {
+	ep-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+	num-lanes = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqn_cpm>;
+	status = "okay";
+};
+
+&pwm0 {
+	status = "disabled";
+};
+
+&pwm2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm2_pin_pull_down>;
+};
+
+&pwm3 {
+	status = "disabled";
+};
+
+&saradc {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	supports-emmc;
+	//mmc-hs400-enhanced-strobe;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&sdmmc {
+	clock-frequency = <150000000>;
+	clock-freq-min-max = <100000 150000000>;
+	supports-sd;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	num-slots = <1>;
+	//sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_s3>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	status = "okay";
+};
+
+&tcphy0 {
+	extcon = <&fusb0>;
+	status = "okay";
+};
+
+&tcphy0_dp {
+	port {
+		tcphy0_typec_dp: endpoint {
+			remote-endpoint = <&usbc_dp>;
+		};
+	};
+};
+
+&tcphy0_usb3 {
+	port {
+		tcphy0_typec_ss: endpoint {
+			remote-endpoint = <&usbc_ss>;
+		};
+	};
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+
+	port {
+		u2phy0_typec_hs: endpoint {
+			remote-endpoint = <&usbc_hs>;
+		};
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&pinctrl {
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins =
+				<1 18 RK_FUNC_GPIO &pcfg_pull_up>,
+				<0 9 RK_FUNC_GPIO &pcfg_pull_none>; /* GPIO0_B1 */
+		};
+		vsel1_gpio: vsel1-gpio {
+			rockchip,pins =
+				<1 17 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+		vsel2_gpio: vsel2-gpio {
+			rockchip,pins =
+				<1 14 RK_FUNC_GPIO &pcfg_pull_down>;
+		};	
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins =
+				<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+	
+	usb-typec {
+		vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin {
+			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+	
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&vopl {
+	status = "okay";	
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+}; 
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3399-xiaobao-nas.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-xiaobao-nas.dts
new file mode 100644
index 000000000000..16f12e573472
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3399-xiaobao-nas.dts
@@ -0,0 +1,774 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	model = "Codinge Xiaobao NAS";
+	compatible = "codinge,xiaobao-nas", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+		mmc2 = &sdio0;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc_dc: vcc-dc {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_12v: vcc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_12v";
+		regulator-always-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s3";
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+	};
+
+	vcc_sd: vcc-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sd";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_sd_h>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc5v0_typec: vcc5v0-typec {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec_en>;
+		regulator-name = "vcc5v0_typec";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_12v>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_pwr_en>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc_lan: vcc3v3-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_lan";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		recovery {
+			label = "Recovery";
+			linux,code = <0x168>;
+			press-threshold-microvolt = <18000>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_pins>;
+
+		led1: system-led1 {
+			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+			label = "system_led1";
+			retain-state-suspended;
+			default-state = "on";
+		};
+
+		led2: system-led2 {
+			gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
+			label = "system_led2";
+			retain-state-suspended;
+			default-state = "off";
+		};
+	};
+
+	pwm-fan {
+		compatible = "pwm-fan";
+		pwms = <&pwm1 0 50000 0>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	ddc-i2c-scl-high-time-ns = <9625>;
+	ddc-i2c-scl-low-time-ns = <10000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG2 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_pmupll: LDO_REG3 {
+				regulator-name = "vcc1v8_pmupll";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_pin>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_pin>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+	};
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+
+	typec-portc@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		vbus-supply = <&vcc5v0_typec>;
+	};
+};
+
+&i2s0 {
+	rockchip,capture-channels = <8>;
+	rockchip,playback-channels = <8>;
+	status = "okay";
+};
+
+&i2s1 {
+	rockchip,capture-channels = <2>;
+	rockchip,playback-channels = <2>;
+	status = "okay";
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc_3v0>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pcie_phy {
+	status = "okay";
+	drive-impedance-ohm = <50>;
+};
+
+&pcie0 {
+	ep-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+	num-lanes = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqnb_cpm &fn8274_en_h>;
+	status = "okay";
+};
+
+&pmu_io_domains {
+	status = "okay";
+
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+	pcie {
+		fn8274_en_h: fn8274-en-h {
+			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>,
+					<4 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>,
+					<1 RK_PC7 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+
+		pcie_pwr_en: pcie-pwr-en {
+			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_typec_en: vcc5v0-typec-en {
+			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	vcc_sd {
+		vcc_sd_h: vcc-sd-h {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		leds_pins: leds-pins {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+					<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	clock-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x00>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3399pro-tinker-edge-r.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3399pro-tinker-edge-r.dts
new file mode 100644
index 000000000000..3785bb5d7f3b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3399pro-tinker-edge-r.dts
@@ -0,0 +1,1080 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2019 Amarula Solutions(India)
+ * Copyright (c) 2024 ARCW <wmx129674@126.com> rk3399pro-tinker_edge_r
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399pro.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	model = "ASUS Tinker Edge R";
+	compatible = "ASUS,rk3399-tinker_edge_r", "rockchip,rk3399pro";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		// bootargs = "earlycon=uart8250,mmio32,0xff180000 swiotlb=1 coherent_pool=1m";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		pwr-led {
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-on";
+			retain-state-suspended = <1>;
+		};
+
+		act-led {
+			gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger="mmc0";
+		};
+
+		rsv-led {
+			gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger="none";
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+	};
+
+	rk_headset {
+		compatible = "rockchip_headset";
+		headset_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+		io-channels = <&saradc 3>;
+	};
+
+	sdhci_pwrseq: sdhci-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		pinctrl-0 = <&sdhci_reset>;
+		pinctrl-names = "default";
+		reset-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+	};
+
+	display-subsystem{
+		status = "okay";
+	};
+
+	vdd_3v3_reg: fixedregulator_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_sys: vccsys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vbus_typec: vbus-typec {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vbus_typec";
+	};
+
+	backlight: backlight {
+		status = "disabled";
+		compatible = "pwm-backlight";
+		pwms = <&pwm0 0 400000 0>;//f=2500 t=400,000ns
+		brightness-levels = <
+				  0   1   2   3    4    5    6   7
+				 9    10  11  12  13  14  15  16
+				 17  18  19  20  21  22  23  24
+				 25  26  27  28  29  30  31  32
+				 33  34  35  37  37  38  38  39
+				 40  41  42  43  44  45  46  47
+				 48  49  50  51  52  53  54  55
+				 56  57  58  59  60  61  62  63
+				 64  65  66  67  68  69  70  71
+				 72  73  74  75  76  77  78  79
+				 80  81  82  83  84  85  86  87
+				 88  89  90  91  92  93  94  95
+				 96  97  98  99 100 101 102 103
+				104 105 106 107 108 109 110 111
+				112 113 114 115 116 117 118 119
+				120 121 122 123 124 125 126 127
+				128 129 130 131 132 133 134 135
+				136 137 138 139 140 141 142 143
+				144 145 146 147 148 149 150 151
+				152 153 154 155 156 157 158 159
+				160 161 162 163 164 165 166 167
+				168 169 170 171 172 173 174 175
+				176 177 178 179 180 181 182 183
+				184 185 186 187 188 189 190 191
+				192 193 194 195 196 197 198 199
+				200 201 202 203 204 205 206 207
+				208 209 210 211 212 213 214 215
+				216 217 218 219 220 221 222 223
+				224 225 226 227 228 229 230 231
+				232 233 234 235 236 237 238 239
+				240 241 242 243 244 245 246 247
+				248 249 250 251 252 253 254 255
+		>;
+		default-brightness-level = <200>;
+		minimal-brightness-level = <26>;
+		soc_enablekl-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
+		enable_delay = <15>;
+		disable_delay = <5>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds_bl_en>;
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "rockchip,rk809";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Headphone", "Headphone Jack";
+		simple-audio-card,routing =
+			"Mic Jack", "MICBIAS1",
+			"IN1P", "Mic Jack",
+			"Headphone Jack", "HPOL",
+			"Headphone Jack", "HPOR";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rk809_codec>;
+		};
+	};
+
+	spdif-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "rockchip,spdif";
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+		status = "okay";
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+	
+	hdmi_dp_sound: hdmi-dp-sound {
+		status = "okay";
+		compatible = "rockchip,rk3399-hdmi-dp";
+		rockchip,cpu = <&i2s2>;
+		rockchip,codec = <&hdmi>, <&cdn_dp>;
+	};
+
+	route_hdmi: route-hdmi {
+		status = "okay";
+		logo,mode = "center";
+		charge_logo,mode = "center";
+		connect = <&vopb_out_hdmi>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 16000 72000>;
+	wolirq-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	tx_delay = <0x23>;
+	rx_delay = <0x22>;
+	wakeup-enable = "0";
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	#sound-dai-cells = <0>;	// must exist
+	rockchip,phy-table =
+		<74250000  0x8009 0x0004 0x0272>,
+		<165000000 0x802b 0x0004 0x0209>,
+		<297000000 0x8039 0x0005 0x028d>,
+		<594000000 0x8039 0x0000 0x019d>,
+		<000000000 0x0000 0x0000 0x0000>;
+};
+
+&hdmi_in_vopl {
+	status = "disabled";
+};
+
+&vopb {	
+	status = "okay";
+	// assigned-clocks = <&cru DCLK_VOP0_DIV>;
+	// assigned-clock-parents = <&cru PLL_VPLL>;
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+	// assigned-clocks = <&cru DCLK_VOP1_DIV>;
+	// assigned-clock-parents = <&cru PLL_CPLL>;
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <180>;
+	i2c-scl-falling-time-ns = <30>;
+	clock-frequency = <400000>;
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PC2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default", "pmic-sleep",
+				"pmic-power-off", "pmic-reset";
+		pinctrl-0 = <&pmic_int_l>;
+		pinctrl-1 = <&soc_slppin_slp>, <&rk809_slppin_slp>;
+		pinctrl-2 = <&soc_slppin_gpio>, <&rk809_slppin_pwrdn>;
+		pinctrl-3 = <&soc_slppin_gpio>, <&rk809_slppin_null>;
+		rockchip,system-power-controller;
+		pmic-reset-func = <0>;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc_buck5>;
+		vcc6-supply = <&vcc_buck5>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+
+		pwrkey {
+			status = "okay";
+		};
+
+		rtc {
+			status = "okay";
+		};
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk809_slppin_null: rk809_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk809_slppin_slp: rk809_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk809_slppin_pwrdn: rk809_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk809_slppin_rst: rk809_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <925000>;
+				regulator-max-microvolt = <1025000>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <925000>;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <925000>;
+				regulator-max-microvolt = <1225000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_sys: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc3v3_sys";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_buck5: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_buck5";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_0v9: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <925000>;
+				regulator-max-microvolt = <925000>;
+				regulator-name = "vcca_0v9";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <925000>;
+				};
+			};
+
+			vcc_1v8: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1850000>;
+				regulator-max-microvolt = <1850000>;
+
+				regulator-name = "vcc_1v8";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1850000>;
+				};
+			};
+
+			vcc0v9_soc: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <950000>;
+				regulator-max-microvolt = <950000>;
+
+				regulator-name = "vcc0v9_soc";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1850000>;
+				regulator-max-microvolt = <1850000>;
+
+				regulator-name = "vcca_1v8";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1850000>;
+				};
+			};
+
+			vdd1v5_dvp: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1850000>;
+				regulator-max-microvolt = <1850000>;
+
+				regulator-name = "vdd1v5_dvp";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1550000>;
+				regulator-max-microvolt = <1550000>;
+
+				regulator-name = "vcc_1v5";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG7 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3075000>;
+				regulator-max-microvolt = <3075000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1850000>;
+				regulator-max-microvolt = <3375000>;
+
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_sd: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3375000>;
+				regulator-max-microvolt = <3375000>;
+
+				regulator-name = "vcc_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc5v0_usb: SWITCH_REG1 {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5000000>;
+
+				regulator-name = "vcc5v0_usb";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <5000000>;
+				};
+			};
+
+			vccio_3v3: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-name = "vccio_3v3";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+		};
+
+		rk809_codec: codec {
+			#sound-dai-cells = <0>;
+			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
+			clocks = <&cru SCLK_I2S_8CH_OUT>;
+			clock-names = "mclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2s_8ch_mclk>;
+			hp-volume = <20>;
+			spk-volume = <3>;
+			status = "okay";
+		};
+	};
+
+	vdd_cpu_b: fan53555@60 {
+		compatible = "fcs,fan53555";
+		reg = <0x60>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-reg";
+		pinctrl-0 = <&vsel1_gpio>;
+		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <925000>;
+		regulator-max-microvolt = <1275000>;
+		regulator-ramp-delay = <1000>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-initial-state = <3>;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	bq25700: bq25700@6b {
+		compatible = "ti,bq25703";
+		reg = <0x6b>;
+		extcon = <&fusb0>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&charger_ok_int>;
+		ti,charge-current = <1500000>;
+		ti,max-charge-voltage = <8704000>;
+		ti,max-input-voltage = <20000000>;
+		ti,max-input-current = <6000000>;
+		ti,input-current-sdp = <500000>;
+		ti,input-current-dcp = <2000000>;
+		ti,input-current-cdp = <2000000>;
+		ti,input-current-dc = <2000000>;
+		ti,minimum-sys-voltage = <6700000>;
+		ti,otg-voltage = <5000000>;
+		ti,otg-current = <500000>;
+		ti,input-current = <500000>;
+		pd-charge-only = <0>;
+		status = "disabled";
+	};
+};
+
+&spdif {
+	status = "disabled";
+	pinctrl-0 = <&spdif_bus>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+};
+
+&i2c1 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <140>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <140>;
+	i2c-scl-falling-time-ns = <30>;
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+	i2c-scl-rising-time-ns = <345>;
+	i2c-scl-falling-time-ns = <11>;
+	status = "okay";
+};
+
+&i2c8 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <345>;
+	i2c-scl-falling-time-ns = <11>;
+	clock-frequency = <100000>;
+
+	fusb0: typec-portc@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+		vbus-5v-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+		vbus2-5v-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	vdd_gpu: fan53555@60 {
+		compatible = "fcs,fan53555";
+		reg = <0x60>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-reg";
+		pinctrl-0 = <&vsel2_gpio>;
+		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <925000>;
+		regulator-max-microvolt = <1225000>;
+		regulator-ramp-delay = <1000>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-initial-state = <3>;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+};
+
+&i2s0 {
+	i2s_8ch_mclk: i2s-8ch-mclk {
+		rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
+	};
+};
+
+&i2s1 {
+	status = "okay";
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+	bt656-supply = <&vcca_1v8>;
+	audio-supply = <&vcca_1v8>;
+	sdmmc-supply = <&vccio_sd>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&isp0_mmu {
+	status = "okay";
+};
+
+&isp1_mmu {
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_1v8>;
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+// &isp0 {
+// 	status = "okay";
+
+// 	port {
+// 		#address-cells = <1>;
+// 		#size-cells = <0>;
+
+// 		isp0_mipi_in: endpoint@0 {
+// 			reg = <0>;
+// 			remote-endpoint = <&dphy_rx0_out>;
+// 		};
+// 	};
+// };
+
+// &isp1 {
+// 	status = "okay";
+
+// 	port {
+// 		#address-cells = <1>;
+// 		#size-cells = <0>;
+
+// 		isp1_mipi_in: endpoint@0 {
+// 			reg = <0>;
+// 			remote-endpoint = <&dphy_tx1rx1_out>;
+// 		};
+// 	};
+// };
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vcc_1v8>;
+};
+
+&sdio0 {
+	status = "okay";
+};
+
+&sdmmc {
+	status = "okay";
+	supports-emmc;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+};
+
+&sdhci {
+	mmc-pwrseq = <&sdhci_pwrseq>;
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	status = "okay";
+};
+
+&spi1 {
+	status = "disable";
+	max-freq = <48000000>; /* spi internal clk, don't modify */
+	spi_dev@0 {
+		compatible = "rockchip,spidev";
+		reg = <0>;
+		spi-max-frequency = <48000000>;
+	};
+};
+
+&spi5 {
+	status = "disable";
+	max-freq = <48000000>;   //spi internal clk, don't modify
+	spi_dev@0 {
+		compatible = "rockchip,spidev";
+		reg = <0>;   //chip select  0:cs0  1:cs1
+		id = <0>;
+		spi-max-frequency = <48000000>;   //spi output clock
+	};
+};
+
+&tcphy0 {
+	extcon = <&fusb0>;
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+	extcon = <&fusb0>;
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_usb>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_usb>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+// &uart4 {
+// 	status = "disable";
+// };
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	extcon = <&fusb0>;
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+    dr_mode = "otg";
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+    dr_mode = "host";
+};
+
+&vpu {
+	status = "okay";
+	/* 0 means ion, 1 means drm */
+	//allocator = <0>;
+};
+
+&pinctrl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&npu_ref_clk &gpio_init>;
+
+	mipi_to_lvds {
+		/*pinctrl_lvds_hdmi_sel: lvds_hdmi_sel {
+			rockchip,pins = <0 5 0  &pcfg_pull_none>;
+		};*/
+
+		pinctrl_sn65dsi84_irq: sn65dsi84_irq{
+			rockchip,pins = <1 RK_PB2 0  &pcfg_pull_none>;
+		};
+
+		pinctrl_lvds_bl_en: lvds_bl_en {
+			rockchip,pins = <1 RK_PB0 0  &pcfg_pull_none>;
+		};
+
+		pinctrl_sn65dsi84_en: sn65dsi84_en {
+			rockchip,pins = <1 RK_PA7 0   &pcfg_pull_none>;
+		};
+
+		pinctrl_lvds_vdd_en: lvds_vdd_en {
+			rockchip,pins = <1 RK_PB1 0  &pcfg_pull_none>;
+		};
+
+		pinctrl_pwr_source: pwr_source {
+			rockchip,pins = <0 RK_PA6 0  &pcfg_pull_none>;
+		};
+	 };
+
+	bq2570 {
+		charger_ok_int: charger-ok-int {
+			rockchip,pins = <1 RK_PA1 0 &pcfg_pull_up>;
+		};
+	};
+
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 0 &pcfg_pull_up>;
+		};
+	};
+
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <0 RK_PB5 0 &pcfg_pull_up>;
+		};
+	};
+
+	lcd_rst {
+		lcd_rst_gpio: lcd-rst-gpio {
+			rockchip,pins = <3 RK_PA4 0 &pcfg_pull_none>;
+		};
+	};
+
+	gpio_init_config {
+                gpio_init: gpio_init {
+                     rockchip,pins =
+                             <1 9 0 &pcfg_pull_none>,
+                             <1 10 0 &pcfg_pull_none>,
+                             <1 7 0 &pcfg_pull_none>,
+                             <1 8 0 &pcfg_pull_none>;
+		};
+	};
+
+	npu_clk {
+		npu_ref_clk: npu-ref-clk {
+		     rockchip,pins =
+			     <0 RK_PA2 1 &pcfg_pull_none>;
+	     };
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins =
+				<1 RK_PC2 0 &pcfg_pull_up>;
+		};
+		vsel1_gpio: vsel1-gpio {
+			rockchip,pins =
+				<1 RK_PC1 0 &pcfg_pull_down>;
+		};
+		vsel2_gpio: vsel2-gpio {
+			rockchip,pins =
+				<1 RK_PB6 0 &pcfg_pull_down>;
+		};
+
+		soc_slppin_gpio: soc-slppin-gpio {
+			rockchip,pins =
+				<1 RK_PA5 0 &pcfg_output_low>;
+		};
+
+		soc_slppin_slp: soc-slppin-slp {
+			rockchip,pins =
+				<1 RK_PA5 1 &pcfg_pull_down>;
+		};
+
+		soc_slppin_rst: soc-slppin-rst {
+			rockchip,pins =
+				<1 RK_PA5 2 &pcfg_pull_none>;
+		};
+	};
+
+	sdhci-pwrseq {
+		sdhci_reset: sdhci-reset {
+			rockchip,pins = <2 4 0 &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins =
+				<2 RK_PD3 0 &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc {
+		sdmmc_bus1: sdmmc-bus1 {
+			rockchip,pins =
+				<4 RK_PB0 1 &pcfg_pull_up>;
+		};
+
+		sdmmc_bus4: sdmmc-bus4 {
+			rockchip,pins =
+				<4 RK_PB0 1 &pcfg_pull_up>,
+				<4 RK_PB1 1 &pcfg_pull_up>,
+				<4 RK_PB2 1 &pcfg_pull_up>,
+				<4 RK_PB3 1 &pcfg_pull_up>;
+		};
+
+		sdmmc_clk: sdmmc-clk {
+			rockchip,pins =
+				<4 RK_PB4 1 &pcfg_pull_none>;
+		};
+
+		sdmmc_cmd: sdmmc-cmd {
+			rockchip,pins =
+				<4 RK_PB5 1 &pcfg_pull_up>;
+		};
+	};
+
+	tp_irq {
+		tp_irq_gpio: tp-irq-gpio {
+			rockchip,pins =
+				<3 RK_PB0 0 &pcfg_pull_up>;
+		};
+	};
+
+	// wireless-bluetooth {
+	// 	bt_irq_gpio: bt-irq-gpio {
+	// 		rockchip,pins =
+	// 			<0 RK_PA5 0 &pcfg_pull_down>;
+	// 	};
+
+		//uart0_gpios: uart0-gpios {
+		//	rockchip,pins =
+		//		<2 RK_PC3 0 &pcfg_pull_none>;
+		//};
+	// };
+
+	// isp {
+	// 	test_clkout2: cif-test_clkout2 {
+	// 		rockchip,pins =
+	// 			/* test_clkout2 */
+	// 			<0 8 3 &pcfg_pull_none>;
+	// 	};
+	// };
+};
+
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3566-firefly-roc-pc.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-firefly-roc-pc.dts
new file mode 100644
index 000000000000..f999fb2b46b4
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-firefly-roc-pc.dts
@@ -0,0 +1,760 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "Firefly rk3566-roc-pc";
+	compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+		mmc2 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	vcc5v0_in: vcc5v0_in {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_in";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0_sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_in>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_enable_h>;
+		regulator-name = "vcc3v3_pcie_p";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3>;
+	};
+
+	firefly_leds: leds {
+		compatible = "gpio-leds";
+		power_led: power {
+		label = "firefly:blue:power";
+		linux,default-trigger = "ir-power-click";
+		default-state = "on";
+		gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_power>;
+	};
+
+	user_led: user {
+		label = "firefly:yellow:user";
+		linux,default-trigger = "ir-user-click";
+		default-state = "off";
+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_user>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		status = "okay";
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	rk_headset: rk-headset {
+		compatible = "rockchip_headset";
+		headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+		io-channels = <&saradc 2>;    //HP_HOOK pin
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_hot: cpu_hot {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_3v3>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk
+		     &gmac1m0_clkinout
+		     &gmac1m0_rgmii_bus>;
+	snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x4e>;
+	rx_delay = <0x2c>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint@0 {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-always-on;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		#sound-dai-cells = <0>;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		codec {
+			mic-in-differential;
+		};
+
+		regulators {
+			vdd_log: DCDC_REG1 {
+				regulator-name = "vdd_log";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-boot-on;
+				regulator-name = "vcc3v3";
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+			};
+		};
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx
+		     &i2s1m0_lrcktx
+		     &i2s1m0_sdi0
+		     &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie_p>;
+	status = "okay";
+};
+
+&pinctrl {
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_enable_h: pcie-enable-h {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_power: led-power {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_user: led-user {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	disable-wp;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	vmmc-supply = <&vcc3v3_sys>;
+	vqmmc-supply = <&vcca1v8_pmu>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &uart9m1_xfer &uart8m1_xfer>;
+	status = "okay";
+};
+
+&sdmmc2 {
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	bus-width = <4>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcca1v8_pmu>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart0 {
+//	pinctrl-names = "default";
+//	pinctrl-0 = <&uart0_xfer>;
+	status = "disabled";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	status = "okay";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	vbus-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&vop {
+	compatible = "rockchip,rk3568-vop";
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
\ No newline at end of file
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3566-jp-tvbox.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-jp-tvbox.dts
new file mode 100644
index 000000000000..6a53d23a55a4
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-jp-tvbox.dts
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 tdleiyao <tdleiyao@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "JP TVbox 3566";
+	compatible = "JP-TVbox,rk3566", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status: led-status {
+			label = "led-status";
+			gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_status_enable_h>;
+		};
+	};
+
+	vbus: vbus-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		status = "okay";
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+		post-power-on-delay-ms = <100>;
+	};
+
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6398s";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_irq>;
+		WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+};
+
+&combphy1 {
+       status = "okay";
+};
+
+&combphy2 {
+       status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+       mali-supply = <&vdd_gpu>;
+       status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_3v3>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk
+		     &gmac1m0_clkinout
+		     &gmac1m0_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x41>;
+	rx_delay = <0x2e>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		status = "okay";
+	};
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+					regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+		};
+	};
+};
+
+&pinctrl {
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wireless-wlan {
+		wifi_host_wake_irq: wifi-host-wake-irq {
+			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_status_enable_h: led-status-enable-h {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sata2 {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	supports-sdio;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	non-removable;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	status = "okay";
+
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		max-speed = <1500000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3566-orangepi-3b-sata.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-orangepi-3b-sata.dts
new file mode 100644
index 000000000000..7957970244d7
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-orangepi-3b-sata.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-orangepi-3b.dts"
+
+/ {
+	model = "Rockchip RK3566 OPi 3B with SATA instead of PCIe";
+};
+
+&pcie2x1 {
+	status = "disabled";
+};
+
+&sata2 {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3566-orangepi-3b.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-orangepi-3b.dts
new file mode 100644
index 000000000000..0d385cfa23c0
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-orangepi-3b.dts
@@ -0,0 +1,869 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ *
+ */
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "Rockchip RK3566 OPi 3B";
+	compatible = "rockchip,rk3566-orangepi-3b", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		pwms = <&pwm7 0 50000 0>;
+		cooling-levels = <0 50 100 150 200 255>;
+		rockchip,temp-trips = <
+			50000   1
+			55000   2
+			60000   3
+			65000   4
+			70000   5
+		>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 =<&leds_gpio>;
+
+		led@1 {
+			gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+			label = "status_led";
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		post-power-on-delay-ms = <200>;
+		reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+	};
+
+	sprd-mtty {
+		compatible = "sprd,mtty";
+		sprd,name = "ttyBT";
+	};
+
+	unisoc_uwe_bsp: uwe-bsp {
+		compatible = "unisoc,uwe_bsp";
+		wl-reg-on = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+		bt-reg-on = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		wl-wake-host-gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+		bt-wake-host;
+		bt-wake-host-gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		sdio-ext-int-gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		unisoc,btwf-file-name = "/lib/firmware/wcnmodem.bin";
+		blksz-512;
+		keep-power-on;
+	};
+
+	/* labeled +12v in schematic */
+	vcc12v_dcin: vcc12v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	/* labeled +5v in schematic */
+	vcc_5v: vcc-5v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vbus: vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	/* labeled +3.3v For PCIe only in schematic */
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_drv>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc_sd: vcc-sd {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "vcc_sd";
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+		regulator-name = "vcc5v0_otg";
+		regulator-always-on;
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "input";
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk
+		     &gmac1m0_clkinout
+		     &gmac1m0_rgmii_bus>;
+
+	snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	//snps,reset-delays-us = <0 20000 100000>;
+	snps,reset-delays-us = <0 50000 200000>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: syr837@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1390000>;
+		regulator-init-microvolt = <900000>;
+		regulator-initial-mode = <1>;
+		regulator-ramp-delay = <2300>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default", "pmic-sleep",
+				"pmic-power-off", "pmic-reset";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
+		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
+		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
+		#sound-dai-cells = <0>;
+
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk817_slppin_null: rk817_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk817_slppin_slp: rk817_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk817_slppin_rst: rk817_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_logic";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_gpu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		codec {
+			mic-in-differential;
+		};
+	};
+};
+
+/*
+ * i2c3_m0 is exposed on the 40-pin (green connectors)
+ * pin 27 - i2c3_sda_m0
+ * pin 28 - i2c3_scl_m0
+ */
+&i2c3 {
+	status = "okay";
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx
+		     &i2s1m0_lrcktx
+		     &i2s1m0_sdi0
+		     &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy0: phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&pcie2x1 {
+	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	wireless-bluetooth {
+		uart1_gpios: uart1-gpios {
+			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sd {
+		sdmmc0_pwr_h: sdmmc0-pwr-h {
+			rockchip,pins =
+			        <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	mxc6655xa {
+		mxc6655xa_irq_gpio: mxc6655xa_irq_gpio {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		soc_slppin_gpio: soc_slppin_gpio {
+			rockchip,pins =
+				<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+
+		soc_slppin_slp: soc_slppin_slp {
+			rockchip,pins =
+				<0 RK_PA2 1 &pcfg_pull_none>;
+		};
+
+		soc_slppin_rst: soc_slppin_rst {
+			rockchip,pins =
+				<0 RK_PA2 2 &pcfg_pull_none>;
+		};
+	};
+
+	touch {
+		touch_gpio: touch-gpio {
+			rockchip,pins =
+				<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
+				<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	work-led {
+		leds_gpio: leds-gpio {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	pcie {
+		pcie_drv: pcie-drv {
+			rockchip,pins =
+				<0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	edp {
+	        edp_hpd: edp-hpd {
+	                rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+	        };
+
+	        bl_en: bl-en {
+	                rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>;
+	        };
+	};
+};
+
+ /*
+  * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7].
+  * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured;
+  * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages
+  *    must be consistent with the software configuration correspondingly
+  *	a/ When the hardware IO level is connected to 1.8V, the software voltage configuration
+  *	   should also be configured to 1.8V accordingly;
+  *	b/ When the hardware IO level is connected to 3.3V, the software voltage configuration
+  *	   should also be configured to 3.3V accordingly;
+  * 3/ VCCIO2 voltage control selection (0xFDC20140)
+  *	BIT[0]: 0x0: from GPIO_0A7 (default)
+  *	BIT[0]: 0x1: from GRF
+  *    Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7:
+  *	L:VCCIO2 must supply 3.3V
+  *	H:VCCIO2 must supply 1.8V
+  */
+
+&pmu_io_domains {
+        status = "okay";
+        pmuio1-supply = <&vcc3v3_pmu>;
+        pmuio2-supply = <&vcc3v3_pmu>;
+        vccio1-supply = <&vcc_3v3>;
+	vccio2-supply = <&vcc_1v8>;
+        vccio3-supply = <&vccio_sd>;
+        vccio4-supply = <&vcc_1v8>;
+        vccio5-supply = <&vcc_3v3>;
+        vccio6-supply = <&vcc_3v3>;
+        vccio7-supply = <&vcc_3v3>;
+};
+
+&pwm7 {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vcca_1v8>;
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	max-frequency = <150000000>;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sfc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <100000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	uart-has-rtscts;
+};
+
+/* (debug) uart2 has connectors near the usb-c power, but also on the 40-pin pins 6 (tx) and 8 (rx) - don't wire both */
+&uart2 {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vbus>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3566-panther-x2.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-panther-x2.dts
new file mode 100644
index 000000000000..2d077f3bb36f
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-panther-x2.dts
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 tdleiyao <tdleiyao@gmail.com>
+ */
+ 
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "Panther X2";
+	compatible = "panther,x2", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+		mmc2 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+	//Corresponds to the actual order
+		led_pwr: led-pwr {
+			label = "led-pwr";
+			default-state = "on";
+			gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_pwr_enable_h>;
+			retain-state-suspended;
+			status = "okay";
+		};
+		
+		led_wifi: led-wifi {
+			label = "led-wifi";
+			default-state = "off";
+			gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_wifi_enable_h>;
+			retain-state-suspended;
+			status = "okay";
+		};
+		
+		led_eth: led-eth {
+			label = "led-eth";
+			default-state = "off";
+			gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_eth_enable_h>;
+			retain-state-suspended;
+			status = "okay";
+		};
+		
+		led_status: led-status {
+			label = "led-status";
+			default-state = "on";
+			gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_status_enable_h>;
+			retain-state-suspended;
+			status = "okay";
+		};
+	};
+	
+	vbus: vbus-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		status = "okay";
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+		post-power-on-delay-ms = <100>;
+	};
+
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6236";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_irq>;
+		WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+       mali-supply = <&vdd_gpu>;
+       status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_3v3>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk
+		     &gmac1m0_clkinout
+		     &gmac1m0_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		status = "okay";
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+					regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				status = "disabled";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+		};
+	};
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
+		     &i2s1m1_lrcktx &i2s1m1_lrckrx
+		     &i2s1m1_sdi0   &i2s1m1_sdi1
+		     &i2s1m1_sdi2   &i2s1m1_sdi3
+		     &i2s1m1_sdo0   &i2s1m1_sdo1
+		     &i2s1m1_sdo2   &i2s1m1_sdo3>;
+	status = "disabled";
+};
+
+&pinctrl {	
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+	
+	wireless-wlan {
+		wifi_host_wake_irq: wifi-host-wake-irq {
+			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+	
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_pwr_enable_h: led-pwr-enable-h {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		
+		led_wifi_enable_h: led-wifi-enable-h {
+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		
+		led_eth_enable_h: led-eth-enable-h {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_status_enable_h: led-status-enable-h {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vcc_3v3>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	broken-cd;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	supports-sdio;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	non-removable;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	status = "okay";
+
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	status = "okay";
+	
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		max-speed = <1500000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3566-radxa-zero-3.dtsi b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-radxa-zero-3.dtsi
new file mode 100644
index 000000000000..9cc7aa3298d0
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-radxa-zero-3.dtsi
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "d";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_led2>;
+
+		led-green {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "on";
+			function = LED_FUNCTION_HEARTBEAT;
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	vcc_1v8: regulator-1v8-vcc {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8_p>;
+	};
+
+	vcca_1v8: regulator-1v8-vcca {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8_p>;
+	};
+
+	vcca1v8_image: regulator-1v8-vcca-image {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca1v8_image";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8_p>;
+	};
+
+	vcc_3v3: regulator-3v3-vcc {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc_sys: regulator-5v0-vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gpio0 {
+	gpio-line-names =
+		/* GPIO0_A0 - A7 */
+		"", "", "", "", "", "", "", "",
+		/* GPIO0_B0 - B7 */
+		"", "", "", "", "", "", "", "",
+		/* GPIO0_C0 - C7 */
+		"", "", "", "", "", "", "", "",
+		/* GPIO0_D0 - D7 */
+		"pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "",
+		"", "", "", "", "";
+};
+
+&gpio1 {
+	gpio-line-names =
+		/* GPIO1_A0 - A7 */
+		"pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "",
+		"",                  "pin-37 [GPIO1_A4]", "",
+		"",                  "",
+		/* GPIO1_B0 - B7 */
+		"", "", "", "", "", "", "", "",
+		/* GPIO1_C0 - C7 */
+		"", "", "", "", "", "", "", "",
+		/* GPIO1_D0 - D7 */
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+	gpio-line-names =
+		/* GPIO2_A0 - A7 */
+		"", "", "", "", "", "", "", "",
+		/* GPIO2_B0 - B7 */
+		"", "", "", "", "", "", "", "",
+		/* GPIO2_C0 - C7 */
+		"", "", "", "", "", "", "", "",
+		/* GPIO2_D0 - D7 */
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+	gpio-line-names =
+		/* GPIO3_A0 - A7 */
+		"",                  "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]",
+		"pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]",
+		"pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]",
+		/* GPIO3_B0 - B7 */
+		"pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]",
+		"pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "",
+		"", "",
+		/* GPIO3_C0 - C7 */
+		"",                  "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]",
+		"pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "",
+		"", "",
+		/* GPIO3_D0 - D7 */
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+	gpio-line-names =
+		/* GPIO4_A0 - A7 */
+		"", "", "", "", "", "", "", "",
+		/* GPIO4_B0 - B7 */
+		"",                  "",                  "pin-27 [GPIO4_B2]",
+		"pin-28 [GPIO4_B3]", "", "", "", "",
+		/* GPIO4_C0 - C7 */
+		"",                  "",                  "pin-23 [GPIO4_C2]",
+		"pin-19 [GPIO4_C3]", "",                  "pin-21 [GPIO4_C5]",
+		"pin-24 [GPIO4_C6]", "",
+		/* GPIO4_D0 - D7 */
+		"", "", "", "", "", "", "", "";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_npu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda_0v9>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk817: pmic@20 {
+		compatible = "rockchip,rk817";
+		reg = <0x20>;
+		#clock-cells = <1>;
+		clock-output-names = "rk817-clkout1", "rk817-clkout2";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc5-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_sys>;
+		vcc9-supply = <&vcc5v_midu>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_gpu_npu: DCDC_REG2 {
+				regulator-name = "vdd_gpu_npu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_sys: DCDC_REG4 {
+				regulator-name = "vcc3v3_sys";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG1 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_1v8_p: LDO_REG7 {
+				regulator-name = "vcc_1v8_p";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG8 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc2v8_dvp: LDO_REG9 {
+				regulator-name = "vcc2v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc5v_midu: BOOST {
+				regulator-name = "vcc5v_midu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5000000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vbus: OTG_SWITCH {
+				regulator-name = "vbus";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu: regulator@40 {
+		compatible = "rockchip,rk8600";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1390000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&pinctrl {
+	leds {
+		user_led2: user-led2 {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcca1v8_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sys>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3566-radxa-zero-3e.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-radxa-zero-3e.dts
new file mode 100644
index 000000000000..4a830eb09f0b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-radxa-zero-3e.dts
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-radxa-zero-3.dtsi"
+
+/ {
+	model = "Radxa ZERO 3E";
+	compatible = "radxa,zero-3e", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+	};
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	clock_in_out = "input";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-id";
+	phy-supply = <&vcc_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus
+		     &gmac1m1_clkinout>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gmac1_rstn>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <50000>;
+		reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pinctrl {
+	gmac1 {
+		gmac1_rstn: gmac1-rstn {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3566-radxa-zero-3w.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-radxa-zero-3w.dts
new file mode 100644
index 000000000000..f92475c59deb
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-radxa-zero-3w.dts
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-radxa-zero-3.dtsi"
+
+/ {
+	model = "Radxa ZERO 3W";
+	compatible = "radxa,zero-3w", "rockchip,rk3566";
+
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+		mmc2 = &sdmmc1;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk817 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <5000000>;
+		reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pinctrl {
+	bluetooth {
+		bt_reg_on_h: bt-reg-on-h {
+			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_host_h: bt-wake-host-h {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		host_wake_bt_h: host-wake-bt-h {
+			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifi {
+		wifi_reg_on_h: wifi-reg-on-h {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_wake_host_h: wifi-wake-host-h {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;
+	no-sd;
+	no-sdio;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	no-mmc;
+	no-sd;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	uart-has-rtscts;
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3566-rock-3c.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-rock-3c.dts
new file mode 100644
index 000000000000..774134de72a7
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3566-rock-3c.dts
@@ -0,0 +1,786 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "Radxa ROCK3 Model C";
+	compatible = "radxa,rock3c", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+		mmc2 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_user: led-0 {
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_user_en>;
+		};
+	};
+
+	pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		cooling-levels = <0 64 128 192 255>;
+		pwms = <&pwm15 0 40000 0>;
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <5000000>;
+		reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc5v_dcin: vcc5v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_pwr_en>;
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v_dcin>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_cam: vcc-cam-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_cam_en>;
+		regulator-name = "vcc_cam";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vcc_mipi: vcc-mipi-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_mipi_en>;
+		regulator-name = "vcc_mipi";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+	clock_in_out = "input";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_clkinout
+		     &gmac1m1_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x47>;
+	rx_delay = <0x27>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		codec {
+			mic-in-differential;
+		};
+	};
+
+	eeprom: eeprom@50 {
+		compatible = "belling,bl24c16a", "atmel,24c16";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	bluetooth {
+		bt_reg_on_h: bt-reg-on-h {
+			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_host_h: bt-wake-host-h {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_h: bt-host-wake-h {
+			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	cam {
+		vcc_cam_en: vcc_cam_en {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	display {
+		vcc_mipi_en: vcc_mipi_en {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_user_en: led_user_en {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_pwr_en: pcie-pwr-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins =	<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifi {
+		wifi_host_wake_h: wifi-host-wake-h {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_reg_on_h: wifi-reg-on-h {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcca1v8_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcca1v8_pmu>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm15 {
+	pinctrl-names = "active";
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr50;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sys>;
+	vqmmc-supply = <&vcca1v8_pmu>;
+	status = "okay";
+
+	wifi@1 {
+		reg = <1>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_h>;
+	};
+};
+
+&sfc {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3568-hinlink-h66k.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3568-hinlink-h66k.dts
new file mode 100644
index 000000000000..f51e626f28a2
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3568-hinlink-h66k.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
+// Copyright (c) 2022 Flippy <flippy@sina.com>
+// Copyright (c) 2023 amazingfate <liujianfeng1994@gmail.com>
+
+/dts-v1/;
+
+#include "rk3568-hinlink-h68k.dts"
+
+/ {
+	model = "HINLINK H66K";
+	compatible = "hinlink,h66k", "rockchip,rk3568";
+};
+
+&gmac0 {
+	status = "disabled";
+};
+
+&gmac1 {
+	status = "disabled";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3568-hinlink-h68k.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3568-hinlink-h68k.dts
new file mode 100644
index 000000000000..7eed082c4edf
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3568-hinlink-h68k.dts
@@ -0,0 +1,889 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
+// Copyright (c) 2023 amazingfate <liujianfeng1994@gmail.com>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "HINLINK H68K";
+	compatible = "hinlink,h68k", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+
+		led-boot = &led_work;
+		led-failsafe = &led_work;
+		led-running = &led_work;
+		led-upgrade = &led_work;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&reset_button_pin>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <50>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_net_en>, <&led_sata_en>, <&led_work_en>;
+
+		led_net: net {
+			label = "blue:net";
+			gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_sata: sata {
+			label = "amber:sata";
+			gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_work: work {
+			label = "green:work";
+			gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	dc_12v: dc-12v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		enable-active-high;
+		gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_sys_en>;
+
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	/* wifi power
+	   for H68K-MAX & H69K-MAX
+	 */
+	vcc3v3_pcie2: vcc3v3-pcie2-regulator {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_pcie2";
+		regulator-boot-on;
+
+		gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_pcie2_en>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	/* eth 2.5g power
+	   for H66K H69K
+	 */
+	vcc3v3_pcie3: vcc3v3-pcie3-regulator {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_pcie3";
+		regulator-boot-on;
+
+		enable-active-high;
+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_pcie3_en>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+
+		vin-supply = <&vcc5v0_sys>;
+
+	};
+
+	vcc3v3_sd_pwren: vcc3v3-sd-pwren-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vcc3v3_sd_pwren";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;	/*      SD_PWREN	*/
+		vin-supply = <&vcc3v3_sys>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_sd_en>;
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+ 	fan: pwm-fan {
+ 		compatible = "pwm-fan";
+		cooling-levels = <0 127 163 255>;
+ 		#cooling-cells = <2>;
+ 		fan-supply = <&vcc5v0_sys>;
+ 		pwms = <&pwm0 0 50000 0>;
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_cool: cpu_cool {
+			temperature = <45000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_warm: cpu_warm {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_hot: cpu_hot {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map1 {
+			trip = <&cpu_cool>;
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+		};
+
+		map2 {
+			trip = <&cpu_warm>;
+			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+		};
+
+		map3 {
+			trip = <&cpu_hot>;
+			cooling-device = <&fan 3 THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "input";
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 50000 200000>;
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "input";
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+	snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 50000 200000>;
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#sound-dai-cells = <0>;
+
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		pwrkey {
+			status = "okay";
+		};
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk817_slppin_null: rk817_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk817_slppin_slp: rk817_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk817_slppin_rst: rk817_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		rk809_codec: codec {
+			#sound-dai-cells = <0>;
+			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
+			clocks = <&cru I2S1_MCLKOUT_TX>;
+			clock-names = "mclk";
+			assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+			assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2s1m0_mclk>;
+			hp-volume = <20>;
+			spk-volume = <3>;
+			mic-in-differential;
+			status = "okay";
+		};
+	};
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		phy-supply = <&vcc3v3_sys>;
+		reg = <0x0>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		phy-supply = <&vcc3v3_sys>;
+		reg = <0x0>;
+	};
+};
+
+&pcie2x1 {
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie2>;
+	status = "okay";
+};
+
+&pcie30phy {
+	data-lanes = <1 2>;
+	status = "okay";
+};
+
+&pcie3x1 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie3>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00100000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		rtl8125_1: pcie-eth@10,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x000000 0 0 0 0>;
+			realtek,led-data = <0x0200>;
+		};
+	};
+};
+
+&pcie3x2 {
+	num-lanes = <1>;
+	rockchip,init-delay-ms = <100>;
+	reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie3>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00200000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		rtl8125_2: pcie-eth@20,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x000000 0 0 0 0>;
+			realtek,led-data = <0x0200>;
+		};
+	};
+};
+
+&pinctrl {
+	button {
+		reset_button_pin: reset-button-pin {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+		led_work_en: led-work-en {
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_sata_en: led-user-en {
+			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_net_en: led-net-en {
+			rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	vcc {
+		vcc3v3_sys_en: vcc3v3-sys-en {
+			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sd {
+		vcc3v3_sd_en: vcc3v3-sd_en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		vcc3v3_pcie2_en: vcc3v3_pcie2_en {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc3v3_pcie3_en: vcc3v3_pcie3_en {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+
+	cap-sd-highspeed;
+	max-frequency = <50000000>;
+	disable-wp;
+
+	vmmc-supply = <&vcc3v3_sd_pwren>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "disabled";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/dt/rk3568-odroid-m1.dts b/patch/kernel/archive/rockchip64-6.10/dt/rk3568-odroid-m1.dts
new file mode 100644
index 000000000000..2cb03c95a0f4
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/dt/rk3568-odroid-m1.dts
@@ -0,0 +1,775 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Hardkernel Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "Hardkernel ODROID-M1";
+	compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		i2c0 = &i2c3;
+		i2c3 = &i2c0;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+		serial0 = &uart1;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	dc_12v: dc-12v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_receiver_pin>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_power: led-0 {
+			gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			default-state = "keep";
+			linux,default-trigger = "default-on";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_power_pin>;
+		};
+		led_work: led-1 {
+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_work_pin>;
+		};
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det_pin>;
+		simple-audio-card,name = "Analog RK817";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,widgets =
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"Headphones", "HPOL",
+			"Headphones", "HPOR",
+			"Speaker", "SPKO";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		enable-active-high;
+		gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_pcie_en_pin>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_host";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_otg";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en_pin>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy0 {
+	/* Used for USB3 */
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&combphy1 {
+	/* Used for USB3 */
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&combphy2 {
+	/* used for SATA */
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc3v3_sys>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	status = "okay";
+
+	tx_delay = <0x4f>;
+	rx_delay = <0x2d>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_pin>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	fspi {
+		fspi_dual_io_pins: fspi-dual-io-pins {
+			rockchip,pins =
+				/* fspi_clk */
+				<1 RK_PD0 1 &pcfg_pull_none>,
+				/* fspi_cs0n */
+				<1 RK_PD3 1 &pcfg_pull_none>,
+				/* fspi_d0 */
+				<1 RK_PD1 1 &pcfg_pull_none>,
+				/* fspi_d1 */
+				<1 RK_PD2 1 &pcfg_pull_none>;
+		};
+	};
+
+	ir-receiver {
+		ir_receiver_pin: ir-receiver-pin {
+			/* external pullup to VCC3V3_SYS */
+			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_power_pin: led-power-pin {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		led_work_pin: led-work-pin {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_reset_pin: pcie-reset-pin {
+			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
+			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rk809 {
+		hp_det_pin: hp-det-pin {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sata2 {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr50;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sfc {
+	/* Dual I/O mode as the D2 pin conflicts with the eMMC */
+	pinctrl-0 = <&fspi_dual_io_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <100000000>;
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "SPL";
+				reg = <0x0 0xe0000>;
+			};
+			partition@e0000 {
+				label = "U-Boot Env";
+				reg = <0xe0000 0x20000>;
+			};
+			partition@100000 {
+				label = "U-Boot";
+				reg = <0x100000 0x200000>;
+			};
+			partition@300000 {
+				label = "splash";
+				reg = <0x300000 0x100000>;
+			};
+			partition@400000 {
+				label = "Filesystem";
+				reg = <0x400000 0xc00000>;
+			};
+		};
+	};
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
+
+&i2c3 {
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3m1_xfer>;
+};
+
+&pwm1 {
+	status = "disabled";
+	pinctrl-0 = <&pwm1m1_pins>;
+};
+
+&pwm2 {
+	status = "disabled";
+	pinctrl-0 = <&pwm2m1_pins>;
+};
+
+&spi0 {
+	status = "disabled";
+
+	pinctrl-0 = <&spi0m1_pins>;
+	pinctrl-1 = <&spi0m1_pins_hs>;
+	num_chipselect = <1>;
+
+	cs-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
+};
+
+&uart1 {
+	status = "disabled";
+	dma-names = "tx", "rx";
+	/* uart1 uart1-with-ctsrts */
+	pinctrl-0 = <&uart1m1_xfer>;
+	pinctrl-1 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>;
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/general-add-miniDP-dt-doc.patch b/patch/kernel/archive/rockchip64-6.10/general-add-miniDP-dt-doc.patch
new file mode 100644
index 000000000000..c74bfad3e38f
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-add-miniDP-dt-doc.patch
@@ -0,0 +1,133 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tony <tonymckahan@gmail.com>
+Date: Wed, 3 Mar 2021 07:59:25 +0100
+Subject: [ARCHEOLOGY] RK3399 Typec DP (#2676)
+
+> X-Git-Archeology: > recovered message: > * RK3399 NanoPC-T4 Add Type-C alt mode DP
+> X-Git-Archeology: > recovered message: > * rk3399 rockpi 4C add mini-DP (WIP)
+> X-Git-Archeology: > recovered message: > * [ rockchip64 ] revert rockPi 4C DP patch
+> X-Git-Archeology: > recovered message: > Add an extension to disable it, but leave for future work.
+> X-Git-Archeology: - Revision 4971535c774a1f49a811baebc083ea028ced0300: https://github.com/armbian/build/commit/4971535c774a1f49a811baebc083ea028ced0300
+> X-Git-Archeology:   Date: Wed, 03 Mar 2021 07:59:25 +0100
+> X-Git-Archeology:   From: Tony <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: RK3399 Typec DP (#2676)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml | 66 ++++++++++
+ 1 file changed, 66 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml
+new file mode 100644
+index 000000000000..8110fbe2ddc2
+--- /dev/null
++++ b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml
+@@ -0,0 +1,66 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/extcon/extcon-usbc-virtual-pd.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Type-C Virtual PD extcon
++
++maintainers:
++  - Jagan Teki <jagan@amarulasolutions.com>
++
++description: |
++  USB Type-C protocol supports various modes of operations includes PD,
++  USB3, and Altmode. If the platform design supports a Type-C connector
++  then configuring these modes can be done via enumeration.
++
++  However, there are some platforms that design these modes as separate
++  protocol connectors like design Display Port from on-chip USB3 controller.
++  So we can access Type-C Altmode Display Port via onboard Display Port
++  connector instead of a Type-C connector. These kinds of platforms require
++  an explicit extcon driver in order to handle Power Delivery and
++  Port Detection.
++
++properties:
++  compatible:
++    const: linux,extcon-usbc-virtual-pd
++
++  det-gpios:
++    description: Detect GPIO pin. Pin can be Display Port Detect or USB ID.
++    maxItems: 1
++
++  vpd-polarity:
++    description: USB Type-C Polarity. false for Normal and true for Flip.
++    type: boolean
++
++  vpd-super-speed:
++    description: USB Super Speed. false for USB2 and true for USB3.
++    type: boolean
++
++  vpd-data-role:
++    description: USB Data roles for Virtual Type-C.
++    $ref: /schemas/types.yaml#definitions/string
++
++    enum:
++      - host
++      - device
++      - display-port
++
++required:
++  - compatible
++  - det-gpios
++  - vpd-data-role
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/gpio/gpio.h>
++    #include <dt-bindings/pinctrl/rockchip.h>
++
++    virtual_pd: virtual-pd {
++        compatible = "linux,extcon-usbc-virtual-pd";
++        det-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
++        vpd-data-role = "display-port";
++        vpd-super-speed;
++    };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-add-miniDP-virtual-extcon.patch b/patch/kernel/archive/rockchip64-6.10/general-add-miniDP-virtual-extcon.patch
new file mode 100644
index 000000000000..00551e8b3159
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-add-miniDP-virtual-extcon.patch
@@ -0,0 +1,382 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tony <tonymckahan@gmail.com>
+Date: Wed, 3 Mar 2021 07:59:25 +0100
+Subject: [ARCHEOLOGY] RK3399 Typec DP (#2676)
+
+> X-Git-Archeology: > recovered message: > * RK3399 NanoPC-T4 Add Type-C alt mode DP
+> X-Git-Archeology: > recovered message: > * rk3399 rockpi 4C add mini-DP (WIP)
+> X-Git-Archeology: > recovered message: > * [ rockchip64 ] revert rockPi 4C DP patch
+> X-Git-Archeology: > recovered message: > Add an extension to disable it, but leave for future work.
+> X-Git-Archeology: - Revision 4971535c774a1f49a811baebc083ea028ced0300: https://github.com/armbian/build/commit/4971535c774a1f49a811baebc083ea028ced0300
+> X-Git-Archeology:   Date: Wed, 03 Mar 2021 07:59:25 +0100
+> X-Git-Archeology:   From: Tony <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: RK3399 Typec DP (#2676)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ drivers/extcon/Kconfig                  |  10 +
+ drivers/extcon/Makefile                 |   1 +
+ drivers/extcon/extcon-usbc-virtual-pd.c | 285 ++++++++++
+ 3 files changed, 296 insertions(+)
+
+diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
+index 8de9023c2a38..21f0f856cacb 100644
+--- a/drivers/extcon/Kconfig
++++ b/drivers/extcon/Kconfig
+@@ -191,4 +191,14 @@ config EXTCON_USBC_TUSB320
+ 	  Say Y here to enable support for USB Type C cable detection extcon
+ 	  support using a TUSB320.
+ 
++config EXTCON_USBC_VIRTUAL_PD
++	tristate "Virtual Type-C PD EXTCON support"
++	depends on GPIOLIB || COMPILE_TEST
++	help
++	  Say Y here to enable Virtual Type-C PD extcon driver support, if
++	  hardware platform designed Type-C modes separately.
++
++	  Example, of designing Display Port separately from Type-C Altmode
++	  instead of accessing Altmode Display Port in Type-C connector.
++
+ endif
+diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
+index 1b390d934ca9..57c1e65bfcfd 100644
+--- a/drivers/extcon/Makefile
++++ b/drivers/extcon/Makefile
+@@ -25,3 +25,4 @@ obj-$(CONFIG_EXTCON_RTK_TYPE_C) += extcon-rtk-type-c.o
+ obj-$(CONFIG_EXTCON_USBC_CROS_EC) += extcon-usbc-cros-ec.o
+ obj-$(CONFIG_EXTCON_USBC_TUSB320) += extcon-usbc-tusb320.o
+ obj-$(CONFIG_EXTCON_RTK_TYPE_C) += extcon-rtk-type-c.o
++obj-$(CONFIG_EXTCON_USBC_VIRTUAL_PD) += extcon-usbc-virtual-pd.o
+diff --git a/drivers/extcon/extcon-usbc-virtual-pd.c b/drivers/extcon/extcon-usbc-virtual-pd.c
+new file mode 100644
+index 000000000000..e0713670e33d
+--- /dev/null
++++ b/drivers/extcon/extcon-usbc-virtual-pd.c
+@@ -0,0 +1,285 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Type-C Virtual PD Extcon driver
++ *
++ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
++ * Copyright (c) 2019 Radxa Limited
++ * Copyright (c) 2019 Amarula Solutions(India)
++ */
++
++#include <linux/extcon-provider.h>
++#include <linux/gpio.h>
++#include <linux/interrupt.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++
++static const unsigned int vpd_cable[] = {
++	EXTCON_USB,
++	EXTCON_USB_HOST,
++	EXTCON_DISP_DP,
++	EXTCON_NONE,
++};
++
++enum vpd_data_role {
++	DR_NONE,
++	DR_HOST,
++	DR_DEVICE,
++	DR_DISPLAY_PORT,
++};
++
++enum vpd_polarity {
++	POLARITY_NORMAL,
++	POLARITY_FLIP,
++};
++
++enum vpd_usb_ss {
++	USB_SS_USB2,
++	USB_SS_USB3,
++};
++
++struct vpd_extcon {
++	struct device *dev;
++	struct extcon_dev *extcon;
++	struct gpio_desc *det_gpio;
++
++	u8 polarity;
++	u8 usb_ss;
++	enum vpd_data_role data_role;
++
++	int irq;
++	bool enable_irq;
++	struct work_struct work;
++	struct delayed_work irq_work;
++};
++
++static void vpd_extcon_irq_work(struct work_struct *work)
++{
++	struct vpd_extcon *vpd = container_of(work, struct vpd_extcon, irq_work.work);
++	bool host_connected = false, device_connected = false, dp_connected = false;
++	union extcon_property_value property;
++	int det;
++
++	det = vpd->det_gpio ? gpiod_get_raw_value(vpd->det_gpio) : 0;
++	if (det) {
++		device_connected = (vpd->data_role == DR_DEVICE) ? true : false;
++		host_connected = (vpd->data_role == DR_HOST) ? true : false;
++		dp_connected = (vpd->data_role == DR_DISPLAY_PORT) ? true : false;
++	}
++
++	extcon_set_state(vpd->extcon, EXTCON_USB, host_connected);
++	extcon_set_state(vpd->extcon, EXTCON_USB_HOST, device_connected);
++	extcon_set_state(vpd->extcon, EXTCON_DISP_DP, dp_connected);
++
++	property.intval = vpd->polarity;
++	extcon_set_property(vpd->extcon, EXTCON_USB,
++			    EXTCON_PROP_USB_TYPEC_POLARITY, property);
++	extcon_set_property(vpd->extcon, EXTCON_USB_HOST,
++			    EXTCON_PROP_USB_TYPEC_POLARITY, property);
++	extcon_set_property(vpd->extcon, EXTCON_DISP_DP,
++			    EXTCON_PROP_USB_TYPEC_POLARITY, property);
++
++	property.intval = vpd->usb_ss;
++	extcon_set_property(vpd->extcon, EXTCON_USB,
++			    EXTCON_PROP_USB_SS, property);
++	extcon_set_property(vpd->extcon, EXTCON_USB_HOST,
++			    EXTCON_PROP_USB_SS, property);
++	extcon_set_property(vpd->extcon, EXTCON_DISP_DP,
++			    EXTCON_PROP_USB_SS, property);
++
++	extcon_sync(vpd->extcon, EXTCON_USB);
++	extcon_sync(vpd->extcon, EXTCON_USB_HOST);
++	extcon_sync(vpd->extcon, EXTCON_DISP_DP);
++}
++
++static irqreturn_t vpd_extcon_irq_handler(int irq, void *dev_id)
++{
++	struct vpd_extcon *vpd = dev_id;
++
++	schedule_delayed_work(&vpd->irq_work, msecs_to_jiffies(10));
++
++	return IRQ_HANDLED;
++}
++
++static enum vpd_data_role vpd_extcon_data_role(struct vpd_extcon *vpd)
++{
++	const char *const data_roles[] = {
++		[DR_NONE]		= "NONE",
++		[DR_HOST]		= "host",
++		[DR_DEVICE]		= "device",
++		[DR_DISPLAY_PORT]	= "display-port",
++	};
++	struct device *dev = vpd->dev;
++	int ret;
++	const char *dr;
++
++	ret = device_property_read_string(dev, "vpd-data-role", &dr);
++	if (ret < 0)
++		return DR_NONE;
++
++	ret = match_string(data_roles, ARRAY_SIZE(data_roles), dr);
++
++	return (ret < 0) ? DR_NONE : ret;
++}
++
++static int vpd_extcon_parse_dts(struct vpd_extcon *vpd)
++{
++	struct device *dev = vpd->dev;
++	bool val = false;
++	int ret;
++
++	val = device_property_read_bool(dev, "vpd-polarity");
++	if (val)
++		vpd->polarity = POLARITY_FLIP;
++	else
++		vpd->polarity = POLARITY_NORMAL;
++
++	val = device_property_read_bool(dev, "vpd-super-speed");
++	if (val)
++		vpd->usb_ss = USB_SS_USB3;
++	else
++		vpd->usb_ss = USB_SS_USB2;
++
++	vpd->data_role = vpd_extcon_data_role(vpd);
++
++	vpd->det_gpio = devm_gpiod_get_optional(dev, "det", GPIOD_OUT_LOW);
++	if (IS_ERR(vpd->det_gpio)) {
++		ret = PTR_ERR(vpd->det_gpio);
++		dev_warn(dev, "failed to get det gpio: %d\n", ret);
++		return ret;
++	}
++
++	vpd->irq = gpiod_to_irq(vpd->det_gpio);
++	if (vpd->irq < 0) {
++		dev_err(dev, "failed to get irq for gpio: %d\n", vpd->irq);
++		return vpd->irq;
++	}
++
++	ret = devm_request_threaded_irq(dev, vpd->irq, NULL,
++					vpd_extcon_irq_handler,
++					IRQF_TRIGGER_FALLING |
++					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
++					NULL, vpd);
++	if (ret)
++		dev_err(dev, "failed to request gpio irq\n");
++
++	return ret;
++}
++
++static int vpd_extcon_probe(struct platform_device *pdev)
++{
++	struct vpd_extcon *vpd;
++	struct device *dev = &pdev->dev;
++	int ret;
++
++	vpd = devm_kzalloc(dev, sizeof(*vpd), GFP_KERNEL);
++	if (!vpd)
++		return -ENOMEM;
++
++	vpd->dev = dev;
++	ret = vpd_extcon_parse_dts(vpd);
++	if (ret)
++		return ret;
++
++	INIT_DELAYED_WORK(&vpd->irq_work, vpd_extcon_irq_work);
++
++	vpd->extcon = devm_extcon_dev_allocate(dev, vpd_cable);
++	if (IS_ERR(vpd->extcon)) {
++		dev_err(dev, "allocat extcon failed\n");
++		return PTR_ERR(vpd->extcon);
++	}
++
++	ret = devm_extcon_dev_register(dev, vpd->extcon);
++	if (ret) {
++		dev_err(dev, "register extcon failed: %d\n", ret);
++		return ret;
++	}
++
++	extcon_set_property_capability(vpd->extcon, EXTCON_USB,
++				       EXTCON_PROP_USB_VBUS);
++	extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST,
++				       EXTCON_PROP_USB_VBUS);
++
++	extcon_set_property_capability(vpd->extcon, EXTCON_USB,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++	extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++	extcon_set_property_capability(vpd->extcon, EXTCON_USB,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST,
++				       EXTCON_PROP_USB_SS);
++
++	extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++
++	platform_set_drvdata(pdev, vpd);
++
++	vpd_extcon_irq_work(&vpd->irq_work.work);
++
++	return 0;
++}
++
++static int vpd_extcon_remove(struct platform_device *pdev)
++{
++	struct vpd_extcon *vpd = platform_get_drvdata(pdev);
++
++	cancel_delayed_work_sync(&vpd->irq_work);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int vpd_extcon_suspend(struct device *dev)
++{
++	struct vpd_extcon *vpd = dev_get_drvdata(dev);
++
++	if (!vpd->enable_irq) {
++		disable_irq_nosync(vpd->irq);
++		vpd->enable_irq = true;
++	}
++
++	return 0;
++}
++
++static int vpd_extcon_resume(struct device *dev)
++{
++	struct vpd_extcon *vpd = dev_get_drvdata(dev);
++
++	if (vpd->enable_irq) {
++		enable_irq(vpd->irq);
++		vpd->enable_irq = false;
++	}
++
++	return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(vpd_extcon_pm_ops,
++			 vpd_extcon_suspend, vpd_extcon_resume);
++
++static const struct of_device_id vpd_extcon_dt_match[] = {
++	{ .compatible = "linux,extcon-usbc-virtual-pd", },
++	{ /* sentinel */ }
++};
++
++static struct platform_driver vpd_extcon_driver = {
++	.probe		= vpd_extcon_probe,
++	.remove		= vpd_extcon_remove,
++	.driver		= {
++		.name	= "extcon-usbc-virtual-pd",
++		.pm	= &vpd_extcon_pm_ops,
++		.of_match_table = vpd_extcon_dt_match,
++	},
++};
++
++module_platform_driver(vpd_extcon_driver);
++
++MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
++MODULE_DESCRIPTION("Type-C Virtual PD extcon driver");
++MODULE_LICENSE("GPL v2");
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-add-overlay-compilation-support.patch b/patch/kernel/archive/rockchip64-6.10/general-add-overlay-compilation-support.patch
new file mode 100644
index 000000000000..3a0c05e60cab
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-add-overlay-compilation-support.patch
@@ -0,0 +1,64 @@
+From a8f9689004d59f0a454ce8cb06bf1556971c1bad Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 20 Jul 2024 13:58:49 +0200
+Subject: [PATCH] compile .scr and install overlays in right path
+
+---
+ scripts/Makefile.dtbinst | 13 ++++++++++++-
+ scripts/Makefile.lib     |  8 +++++++-
+ 2 files changed, 19 insertions(+), 2 deletions(-)
+
+diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
+index 9d920419a62c..9144a1b7c909 100644
+--- a/scripts/Makefile.dtbinst
++++ b/scripts/Makefile.dtbinst
+@@ -33,7 +33,18 @@ endef
+ 
+ $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d))))
+ 
+-dtbs := $(notdir $(dtbs))
++# Very convoluted way to flatten all the device tree
++# directories, but keep the "/overlay/" directory
++
++# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip)
++topmost_dir = $(firstword $(subst /, ,$(dtbs)))
++# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir"
++dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs)))
++# collect the non-overlay dtbs
++dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs))
++# compose the dtbs variable flattening all the non-overlays entries
++# and appending the overlays entries
++dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays)
+ 
+ endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL
+ 
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 9f06f6aaf7fc..67a7b73b6688 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -394,15 +394,21 @@ quiet_cmd_wrap_S_dtb = WRAP    $@
+ 		echo '.balign STRUCT_ALIGNMENT';					\
+ 	} > $@
+ 
++quiet_cmd_scr = MKIMAGE $@
++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
++
+ $(obj)/%.dtb.S: $(obj)/%.dtb FORCE
+ 	$(call if_changed,wrap_S_dtb)
+ 
+ $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE
+ 	$(call if_changed,wrap_S_dtb)
+ 
++$(obj)/%.scr: $(src)/%.scr-cmd FORCE
++	$(call if_changed,scr)
++
+ quiet_cmd_dtc = DTC     $@
+ cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+-	$(DTC) -o $@ -b 0 \
++	$(DTC) -@ -o $@ -b 0 \
+ 		$(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \
+ 		-d $(depfile).dtc.tmp $(dtc-tmp) ; \
+ 	cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-add-overlay-configfs.patch b/patch/kernel/archive/rockchip64-6.10/general-add-overlay-configfs.patch
new file mode 100644
index 000000000000..895edaddbfbf
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-add-overlay-configfs.patch
@@ -0,0 +1,419 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
+Date: Wed, 3 Dec 2014 13:23:28 +0200
+Subject: OF: DT-Overlay configfs interface
+
+This is a port of Pantelis Antoniou's v3 port that makes use of the
+new upstreamed configfs support for binary attributes.
+
+Original commit message:
+
+Add a runtime interface to using configfs for generic device tree overlay
+usage. With it its possible to use device tree overlays without having
+to use a per-platform overlay manager.
+
+Please see Documentation/devicetree/configfs-overlays.txt for more info.
+
+Changes since v2:
+- Removed ifdef CONFIG_OF_OVERLAY (since for now it's required)
+- Created a documentation entry
+- Slight rewording in Kconfig
+
+Changes since v1:
+- of_resolve() -> of_resolve_phandles().
+
+Originally-signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+
+DT configfs: Fix build errors on other platforms
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+
+DT configfs: fix build error
+
+There is an error when compiling rpi-4.6.y branch:
+  CC      drivers/of/configfs.o
+drivers/of/configfs.c:291:21: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
+   .default_groups = of_cfs_def_groups,
+                     ^
+drivers/of/configfs.c:291:21: note: (near initialization for 'of_cfs_subsys.su_group.default_groups.next')
+
+The .default_groups is linked list since commit
+1ae1602de028acaa42a0f6ff18d19756f8e825c6.
+This commit uses configfs_add_default_group to fix this problem.
+
+Signed-off-by: Slawomir Stepien <sst@poczta.fm>
+
+configfs: New of_overlay API
+
+of: configfs: Use of_overlay_fdt_apply API call
+
+The published API to the dynamic overlay application mechanism now
+takes a Flattened Device Tree blob as input so that it can manage the
+lifetime of the unflattened tree. Conveniently, the new API call -
+of_overlay_fdt_apply - is virtually a drop-in replacement for
+create_overlay, which can now be deleted.
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ Documentation/devicetree/configfs-overlays.txt |  31 ++
+ drivers/of/Kconfig                             |  11 +
+ drivers/of/Makefile                            |   1 +
+ drivers/of/configfs.c                          | 277 ++++++++++
+ 4 files changed, 320 insertions(+)
+
+diff --git a/Documentation/devicetree/configfs-overlays.txt b/Documentation/devicetree/configfs-overlays.txt
+new file mode 100644
+index 000000000000..5fa43e064307
+--- /dev/null
++++ b/Documentation/devicetree/configfs-overlays.txt
+@@ -0,0 +1,31 @@
++Howto use the configfs overlay interface.
++
++A device-tree configfs entry is created in /config/device-tree/overlays
++and and it is manipulated using standard file system I/O.
++Note that this is a debug level interface, for use by developers and
++not necessarily something accessed by normal users due to the
++security implications of having direct access to the kernel's device tree.
++
++* To create an overlay you mkdir the directory:
++
++	# mkdir /config/device-tree/overlays/foo
++
++* Either you echo the overlay firmware file to the path property file.
++
++	# echo foo.dtbo >/config/device-tree/overlays/foo/path
++
++* Or you cat the contents of the overlay to the dtbo file
++
++	# cat foo.dtbo >/config/device-tree/overlays/foo/dtbo
++
++The overlay file will be applied, and devices will be created/destroyed
++as required.
++
++To remove it simply rmdir the directory.
++
++	# rmdir /config/device-tree/overlays/foo
++
++The rationalle of the dual interface (firmware & direct copy) is that each is
++better suited to different use patterns. The firmware interface is what's
++intended to be used by hardware managers in the kernel, while the copy interface
++make sense for developers (since it avoids problems with namespaces).
+diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
+index da9826accb1b..69e7c420b8f4 100644
+--- a/drivers/of/Kconfig
++++ b/drivers/of/Kconfig
+@@ -102,4 +102,15 @@ config OF_OVERLAY
+ config OF_NUMA
+ 	bool
+ 
++config OF_DMA_DEFAULT_COHERENT
++	# arches should select this if DMA is coherent by default for OF devices
++	bool
++
++config OF_CONFIGFS
++	bool "Device Tree Overlay ConfigFS interface"
++	select CONFIGFS_FS
++	select OF_OVERLAY
++	help
++	  Enable a simple user-space driven DT overlay interface.
++
+ endif # OF
+diff --git a/drivers/of/Makefile b/drivers/of/Makefile
+index eff624854575..61bd05f08ca1 100644
+--- a/drivers/of/Makefile
++++ b/drivers/of/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-y = base.o cpu.o device.o module.o platform.o property.o
+ obj-$(CONFIG_OF_KOBJ) += kobj.o
++obj-$(CONFIG_OF_CONFIGFS) += configfs.o
+ obj-$(CONFIG_OF_DYNAMIC) += dynamic.o
+ obj-$(CONFIG_OF_FLATTREE) += fdt.o
+ obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o
+diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c
+new file mode 100644
+index 000000000000..1c30f35c3ca1
+--- /dev/null
++++ b/drivers/of/configfs.c
+@@ -0,0 +1,277 @@
++/*
++ * Configfs entries for device-tree
++ *
++ * Copyright (C) 2013 - Pantelis Antoniou <panto@antoniou-consulting.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ */
++#include <linux/ctype.h>
++#include <linux/cpu.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_fdt.h>
++#include <linux/spinlock.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/configfs.h>
++#include <linux/types.h>
++#include <linux/stat.h>
++#include <linux/limits.h>
++#include <linux/file.h>
++#include <linux/vmalloc.h>
++#include <linux/firmware.h>
++#include <linux/sizes.h>
++
++#include "of_private.h"
++
++struct cfs_overlay_item {
++	struct config_item	item;
++
++	char			path[PATH_MAX];
++
++	const struct firmware	*fw;
++	struct device_node	*overlay;
++	int			ov_id;
++
++	void			*dtbo;
++	int			dtbo_size;
++};
++
++static inline struct cfs_overlay_item *to_cfs_overlay_item(
++		struct config_item *item)
++{
++	return item ? container_of(item, struct cfs_overlay_item, item) : NULL;
++}
++
++static ssize_t cfs_overlay_item_path_show(struct config_item *item,
++		char *page)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	return sprintf(page, "%s\n", overlay->path);
++}
++
++static ssize_t cfs_overlay_item_path_store(struct config_item *item,
++		const char *page, size_t count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	const char *p = page;
++	char *s;
++	int err;
++
++	/* if it's set do not allow changes */
++	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
++		return -EPERM;
++
++	/* copy to path buffer (and make sure it's always zero terminated */
++	count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p);
++	overlay->path[sizeof(overlay->path) - 1] = '\0';
++
++	/* strip trailing newlines */
++	s = overlay->path + strlen(overlay->path);
++	while (s > overlay->path && *--s == '\n')
++		*s = '\0';
++
++	pr_debug("%s: path is '%s'\n", __func__, overlay->path);
++
++	err = request_firmware(&overlay->fw, overlay->path, NULL);
++	if (err != 0)
++		goto out_err;
++
++	err = of_overlay_fdt_apply((void *)overlay->fw->data,
++				   (u32)overlay->fw->size, &overlay->ov_id, NULL);
++	if (err != 0)
++		goto out_err;
++
++	return count;
++
++out_err:
++
++	release_firmware(overlay->fw);
++	overlay->fw = NULL;
++
++	overlay->path[0] = '\0';
++	return err;
++}
++
++static ssize_t cfs_overlay_item_status_show(struct config_item *item,
++		char *page)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	return sprintf(page, "%s\n",
++			overlay->ov_id > 0 ? "applied" : "unapplied");
++}
++
++CONFIGFS_ATTR(cfs_overlay_item_, path);
++CONFIGFS_ATTR_RO(cfs_overlay_item_, status);
++
++static struct configfs_attribute *cfs_overlay_attrs[] = {
++	&cfs_overlay_item_attr_path,
++	&cfs_overlay_item_attr_status,
++	NULL,
++};
++
++ssize_t cfs_overlay_item_dtbo_read(struct config_item *item,
++		void *buf, size_t max_count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	pr_debug("%s: buf=%p max_count=%zu\n", __func__,
++			buf, max_count);
++
++	if (overlay->dtbo == NULL)
++		return 0;
++
++	/* copy if buffer provided */
++	if (buf != NULL) {
++		/* the buffer must be large enough */
++		if (overlay->dtbo_size > max_count)
++			return -ENOSPC;
++
++		memcpy(buf, overlay->dtbo, overlay->dtbo_size);
++	}
++
++	return overlay->dtbo_size;
++}
++
++ssize_t cfs_overlay_item_dtbo_write(struct config_item *item,
++		const void *buf, size_t count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	int err;
++
++	/* if it's set do not allow changes */
++	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
++		return -EPERM;
++
++	/* copy the contents */
++	overlay->dtbo = kmemdup(buf, count, GFP_KERNEL);
++	if (overlay->dtbo == NULL)
++		return -ENOMEM;
++
++	overlay->dtbo_size = count;
++
++	err = of_overlay_fdt_apply(overlay->dtbo, overlay->dtbo_size,
++				   &overlay->ov_id, NULL);
++	if (err != 0)
++		goto out_err;
++
++	return count;
++
++out_err:
++	kfree(overlay->dtbo);
++	overlay->dtbo = NULL;
++	overlay->dtbo_size = 0;
++	overlay->ov_id = 0;
++
++	return err;
++}
++
++CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M);
++
++static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = {
++	&cfs_overlay_item_attr_dtbo,
++	NULL,
++};
++
++static void cfs_overlay_release(struct config_item *item)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	if (overlay->ov_id > 0)
++		of_overlay_remove(&overlay->ov_id);
++	if (overlay->fw)
++		release_firmware(overlay->fw);
++	/* kfree with NULL is safe */
++	kfree(overlay->dtbo);
++	kfree(overlay);
++}
++
++static struct configfs_item_operations cfs_overlay_item_ops = {
++	.release	= cfs_overlay_release,
++};
++
++static struct config_item_type cfs_overlay_type = {
++	.ct_item_ops	= &cfs_overlay_item_ops,
++	.ct_attrs	= cfs_overlay_attrs,
++	.ct_bin_attrs	= cfs_overlay_bin_attrs,
++	.ct_owner	= THIS_MODULE,
++};
++
++static struct config_item *cfs_overlay_group_make_item(
++		struct config_group *group, const char *name)
++{
++	struct cfs_overlay_item *overlay;
++
++	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
++	if (!overlay)
++		return ERR_PTR(-ENOMEM);
++
++	config_item_init_type_name(&overlay->item, name, &cfs_overlay_type);
++	return &overlay->item;
++}
++
++static void cfs_overlay_group_drop_item(struct config_group *group,
++		struct config_item *item)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	config_item_put(&overlay->item);
++}
++
++static struct configfs_group_operations overlays_ops = {
++	.make_item	= cfs_overlay_group_make_item,
++	.drop_item	= cfs_overlay_group_drop_item,
++};
++
++static struct config_item_type overlays_type = {
++	.ct_group_ops   = &overlays_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++static struct configfs_group_operations of_cfs_ops = {
++	/* empty - we don't allow anything to be created */
++};
++
++static struct config_item_type of_cfs_type = {
++	.ct_group_ops   = &of_cfs_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++struct config_group of_cfs_overlay_group;
++
++static struct configfs_subsystem of_cfs_subsys = {
++	.su_group = {
++		.cg_item = {
++			.ci_namebuf = "device-tree",
++			.ci_type = &of_cfs_type,
++		},
++	},
++	.su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex),
++};
++
++static int __init of_cfs_init(void)
++{
++	int ret;
++
++	pr_info("%s\n", __func__);
++
++	config_group_init(&of_cfs_subsys.su_group);
++	config_group_init_type_name(&of_cfs_overlay_group, "overlays",
++			&overlays_type);
++	configfs_add_default_group(&of_cfs_overlay_group,
++			&of_cfs_subsys.su_group);
++
++	ret = configfs_register_subsystem(&of_cfs_subsys);
++	if (ret != 0) {
++		pr_err("%s: failed to register subsys\n", __func__);
++		goto out;
++	}
++	pr_info("%s: OK\n", __func__);
++out:
++	return ret;
++}
++late_initcall(of_cfs_init);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-add-panel-simple-dsi.patch b/patch/kernel/archive/rockchip64-6.10/general-add-panel-simple-dsi.patch
new file mode 100644
index 000000000000..536acee59be8
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-add-panel-simple-dsi.patch
@@ -0,0 +1,856 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: simple <991605149@qq.com>
+Date: Sun, 12 Sep 2021 20:06:02 +0200
+Subject: [ARCHEOLOGY] general add panel simple dsi (#3140)
+
+> X-Git-Archeology: > recovered message: > * Backporting patch to 5.10 kernel makes sense. Lets do it.
+> X-Git-Archeology: > recovered message: > Co-authored-by: iamdrq <iamdrq@qq.com>
+> X-Git-Archeology: > recovered message: > Co-authored-by: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology: - Revision 15819f00e21238e36ca70f6d8445efd6157fbe66: https://github.com/armbian/build/commit/15819f00e21238e36ca70f6d8445efd6157fbe66
+> X-Git-Archeology:   Date: Sun, 12 Sep 2021 20:06:02 +0200
+> X-Git-Archeology:   From: simple <991605149@qq.com>
+> X-Git-Archeology:   Subject: general add panel simple dsi (#3140)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4
+> X-Git-Archeology:   Date: Tue, 11 Jan 2022 15:26:11 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel edge to 5.16 (#3387)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 3b78b57fe367e60ad874d9e16ff1cd67957f8382: https://github.com/armbian/build/commit/3b78b57fe367e60ad874d9e16ff1cd67957f8382
+> X-Git-Archeology:   Date: Sat, 24 Dec 2022 09:43:51 +0100
+> X-Git-Archeology:   From: simple <991605149@qq.com>
+> X-Git-Archeology:   Subject: Fix general-add-panel-simple-dsi.patch on linux6.1 (#4607)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ drivers/gpu/drm/panel/Makefile           |   1 +
+ drivers/gpu/drm/panel/panel-simple-dsi.c | 772 ++++++++++
+ 2 files changed, 773 insertions(+)
+
+diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
+index 433e93d57949..02076386ed5f 100644
+--- a/drivers/gpu/drm/panel/Makefile
++++ b/drivers/gpu/drm/panel/Makefile
+@@ -9,6 +9,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
+ obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o
+ obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
+ obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
++obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple-dsi.o
+ obj-$(CONFIG_DRM_PANEL_EDP) += panel-edp.o
+ obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) += panel-ebbg-ft8719.o
+ obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o
+diff --git a/drivers/gpu/drm/panel/panel-simple-dsi.c b/drivers/gpu/drm/panel/panel-simple-dsi.c
+new file mode 100644
+index 000000000000..e3c8dcf8cb5e
+--- /dev/null
++++ b/drivers/gpu/drm/panel/panel-simple-dsi.c
+@@ -0,0 +1,772 @@
++/*
++ * Copyright (C) 2021
++ * This simple dsi driver porting from rock-chip panel-simple.c on linux-4.4
++ */
++
++#include <linux/backlight.h>
++#include <linux/gpio/consumer.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++
++#include <drm/drm_crtc.h>
++#include <drm/drm_mipi_dsi.h>
++#include <drm/drm_panel.h>
++
++#include <video/display_timing.h>
++#include <video/mipi_display.h>
++#include <linux/of_device.h>
++#include <video/of_display_timing.h>
++#include <linux/of_graph.h>
++#include <video/videomode.h>
++#include <linux/delay.h>
++
++struct cmd_ctrl_hdr {
++	u8 dtype;	/* data type */
++	u8 wait;	/* ms */
++	u8 dlen;	/* payload len */
++} __packed;
++
++struct cmd_desc {
++	struct cmd_ctrl_hdr dchdr;
++	u8 *payload;
++};
++
++struct panel_cmds {
++	u8 *buf;
++	int blen;
++	struct cmd_desc *cmds;
++	int cmd_cnt;
++};
++
++struct panel_desc {
++	const struct drm_display_mode *modes;
++	unsigned int num_modes;
++	const struct display_timing *timings;
++	unsigned int num_timings;
++
++	unsigned int bpc;
++
++	struct {
++		unsigned int width;
++		unsigned int height;
++	} size;
++
++	/**
++	 * @reset: the time (in milliseconds) indicates the delay time
++	 *         after the panel to operate reset gpio
++	 * @init: the time (in milliseconds) that it takes for the panel to
++	 *           power on and dsi host can send command to panel
++	 * @prepare: the time (in milliseconds) that it takes for the panel to
++	 *           become ready and start receiving video data
++	 * @enable: the time (in milliseconds) that it takes for the panel to
++	 *          display the first valid frame after starting to receive
++	 *          video data
++	 * @disable: the time (in milliseconds) that it takes for the panel to
++	 *           turn the display off (no content is visible)
++	 * @unprepare: the time (in milliseconds) that it takes for the panel
++	 *             to power itself down completely
++	 */
++	struct {
++		unsigned int reset;
++		unsigned int init;
++		unsigned int prepare;
++		unsigned int enable;
++		unsigned int disable;
++		unsigned int unprepare;
++	} delay;
++
++	u32 bus_format;
++};
++
++struct panel_simple {
++	struct drm_panel base;
++	struct mipi_dsi_device *dsi;
++	bool prepared;
++	bool enabled;
++	bool power_invert;
++
++	struct device *dev;
++	const struct panel_desc *desc;
++
++	struct regulator *supply;
++
++	struct gpio_desc *enable_gpio;
++	struct gpio_desc *reset_gpio;
++	int cmd_type;
++
++	struct panel_cmds *on_cmds;
++	struct panel_cmds *off_cmds;
++	struct device_node *np_crtc;
++	
++	int reset_level;
++	enum drm_panel_orientation orientation;
++};
++
++enum rockchip_cmd_type {
++	CMD_TYPE_DEFAULT,
++	CMD_TYPE_SPI,
++	CMD_TYPE_MCU
++};
++
++static void panel_simple_sleep(unsigned int msec)
++{
++	if (msec > 20)
++		msleep(msec);
++	else
++		usleep_range(msec * 1000, (msec + 1) * 1000);
++}
++
++static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
++{
++	return container_of(panel, struct panel_simple, base);
++}
++
++static void panel_simple_cmds_cleanup(struct panel_simple *p)
++{
++	if (p->on_cmds) {
++		kfree(p->on_cmds->buf);
++		kfree(p->on_cmds->cmds);
++	}
++
++	if (p->off_cmds) {
++		kfree(p->off_cmds->buf);
++		kfree(p->off_cmds->cmds);
++	}
++}
++
++static int panel_simple_parse_cmds(struct device *dev,
++				   const u8 *data, int blen,
++				   struct panel_cmds *pcmds)
++{
++	unsigned int len;
++	char *buf, *bp;
++	struct cmd_ctrl_hdr *dchdr;
++	int i, cnt;
++
++	if (!pcmds)
++		return -EINVAL;
++
++	buf = kmemdup(data, blen, GFP_KERNEL);
++	if (!buf)
++		return -ENOMEM;
++
++	/* scan init commands */
++	bp = buf;
++	len = blen;
++	cnt = 0;
++	while (len > sizeof(*dchdr)) {
++		dchdr = (struct cmd_ctrl_hdr *)bp;
++
++		if (dchdr->dlen > len) {
++			dev_err(dev, "%s: error, len=%d", __func__,
++				dchdr->dlen);
++			return -EINVAL;
++		}
++
++		bp += sizeof(*dchdr);
++		len -= sizeof(*dchdr);
++		bp += dchdr->dlen;
++		len -= dchdr->dlen;
++		cnt++;
++	}
++
++	if (len != 0) {
++		dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
++			__func__, buf[0], blen);
++		kfree(buf);
++		return -EINVAL;
++	}
++
++	pcmds->cmds = kcalloc(cnt, sizeof(struct cmd_desc), GFP_KERNEL);
++	if (!pcmds->cmds) {
++		kfree(buf);
++		return -ENOMEM;
++	}
++
++	pcmds->cmd_cnt = cnt;
++	pcmds->buf = buf;
++	pcmds->blen = blen;
++
++	bp = buf;
++	len = blen;
++	for (i = 0; i < cnt; i++) {
++		dchdr = (struct cmd_ctrl_hdr *)bp;
++		len -= sizeof(*dchdr);
++		bp += sizeof(*dchdr);
++		pcmds->cmds[i].dchdr = *dchdr;
++		pcmds->cmds[i].payload = bp;
++		bp += dchdr->dlen;
++		len -= dchdr->dlen;
++	}
++
++	return 0;
++}
++
++static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
++				      struct panel_cmds *cmds)
++{
++	struct mipi_dsi_device *dsi = panel->dsi;
++	int i, err;
++
++	if (!cmds)
++		return -EINVAL;
++
++	for (i = 0; i < cmds->cmd_cnt; i++) {
++		struct cmd_desc *cmd = &cmds->cmds[i];
++
++		switch (cmd->dchdr.dtype) {
++		case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
++		case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
++		case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
++		case MIPI_DSI_GENERIC_LONG_WRITE:
++			err = mipi_dsi_generic_write(dsi, cmd->payload,
++						     cmd->dchdr.dlen);
++			break;
++		case MIPI_DSI_DCS_SHORT_WRITE:
++		case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
++		case MIPI_DSI_DCS_LONG_WRITE:
++			err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
++							cmd->dchdr.dlen);
++			break;
++		default:
++			return -EINVAL;
++		}
++
++		if (err < 0)
++			dev_err(panel->dev, "failed to write dcs cmd: %d\n",
++				err);
++
++		if (cmd->dchdr.wait)
++			panel_simple_sleep(cmd->dchdr.wait);
++	}
++
++	return 0;
++}
++
++static int panel_simple_get_cmds(struct panel_simple *panel)
++{
++	const void *data;
++	int len;
++	int err;
++
++	data = of_get_property(panel->dev->of_node, "panel-init-sequence",
++			       &len);
++	if (data) {
++		panel->on_cmds = devm_kzalloc(panel->dev,
++					      sizeof(*panel->on_cmds),
++					      GFP_KERNEL);
++		if (!panel->on_cmds)
++			return -ENOMEM;
++
++		err = panel_simple_parse_cmds(panel->dev, data, len,
++					      panel->on_cmds);
++		if (err) {
++			dev_err(panel->dev, "failed to parse panel init sequence\n");
++			return err;
++		}
++	}
++
++	data = of_get_property(panel->dev->of_node, "panel-exit-sequence",
++			       &len);
++	if (data) {
++		panel->off_cmds = devm_kzalloc(panel->dev,
++					       sizeof(*panel->off_cmds),
++					       GFP_KERNEL);
++		if (!panel->off_cmds)
++			return -ENOMEM;
++
++		err = panel_simple_parse_cmds(panel->dev, data, len,
++					      panel->off_cmds);
++		if (err) {
++			dev_err(panel->dev, "failed to parse panel exit sequence\n");
++			return err;
++		}
++	}
++	return 0;
++}
++
++static int panel_simple_get_modes(struct drm_panel *panel,struct drm_connector *connector)
++{
++ 	struct panel_simple *p = to_panel_simple(panel);
++	struct drm_device *drm = connector->dev;
++	struct drm_display_mode *mode;
++	struct device_node *timings_np;
++	int ret;
++
++	timings_np = of_get_child_by_name(panel->dev->of_node,
++					  "display-timings");
++	if (!timings_np) {
++		dev_dbg(panel->dev, "failed to find display-timings node\n");
++		return 0;
++	}
++
++	of_node_put(timings_np);
++	mode = drm_mode_create(drm);
++	if (!mode)
++		return 0;
++
++	ret = of_get_drm_display_mode(panel->dev->of_node, mode, p->desc->bus_format,
++				      OF_USE_NATIVE_MODE);
++	if (ret) {
++		dev_dbg(panel->dev, "failed to find dts display timings\n");
++		drm_mode_destroy(drm, mode);
++		return 0;
++	}
++
++	drm_mode_set_name(mode);
++	mode->type |= DRM_MODE_TYPE_PREFERRED;
++
++	connector->display_info.width_mm = mode->width_mm;
++	connector->display_info.height_mm = mode->height_mm;
++
++	drm_mode_probed_add(connector, mode);
++
++	/*
++	 * TODO: Remove once all drm drivers call
++	 * drm_connector_set_orientation_from_panel()
++	 */
++	drm_connector_set_panel_orientation(connector, p->orientation);
++	
++	return 1;
++}
++
++static int panel_simple_regulator_enable(struct drm_panel *panel)
++{
++	struct panel_simple *p = to_panel_simple(panel);
++	int err = 0;
++
++	if (p->power_invert) {
++		if (regulator_is_enabled(p->supply) > 0)
++			regulator_disable(p->supply);
++	} else {
++		err = regulator_enable(p->supply);
++		if (err < 0) {
++			dev_err(panel->dev, "failed to enable supply: %d\n",
++				err);
++			return err;
++		}
++	}
++
++	return err;
++}
++
++static int panel_simple_regulator_disable(struct drm_panel *panel)
++{
++	struct panel_simple *p = to_panel_simple(panel);
++	int err = 0;
++
++	if (p->power_invert) {
++		if (!regulator_is_enabled(p->supply)) {
++			err = regulator_enable(p->supply);
++			if (err < 0) {
++				dev_err(panel->dev, "failed to enable supply: %d\n",
++					err);
++				return err;
++			}
++		}
++	} else {
++		regulator_disable(p->supply);
++	}
++
++	return err;
++}
++
++static int panel_simple_disable(struct drm_panel *panel)
++{
++	struct panel_simple *p = to_panel_simple(panel);
++	int err = 0;
++
++	if (!p->enabled)
++		return 0;
++
++	if (p->desc && p->desc->delay.disable)
++		panel_simple_sleep(p->desc->delay.disable);
++
++	p->enabled = false;
++
++	return 0;
++}
++
++static int panel_simple_unprepare(struct drm_panel *panel)
++{
++	struct panel_simple *p = to_panel_simple(panel);
++	int err = 0;
++
++	if (!p->prepared)
++		return 0;
++
++	if (p->off_cmds) {
++		if (p->dsi)
++			err = panel_simple_dsi_send_cmds(p, p->off_cmds);
++		if (err)
++			dev_err(p->dev, "failed to send off cmds\n");
++	}
++
++	if (p->reset_gpio)
++		gpiod_direction_output(p->reset_gpio, !p->reset_level);
++
++	if (p->enable_gpio)
++		gpiod_direction_output(p->enable_gpio, 0);
++
++	panel_simple_regulator_disable(panel);
++
++	if (p->desc && p->desc->delay.unprepare)
++		panel_simple_sleep(p->desc->delay.unprepare);
++
++	p->prepared = false;
++
++	return 0;
++}
++
++static int panel_simple_prepare(struct drm_panel *panel)
++{
++	struct panel_simple *p = to_panel_simple(panel);
++	int err;
++
++	if (p->prepared)
++		return 0;
++
++	err = panel_simple_regulator_enable(panel);
++	if (err < 0) {
++		dev_err(panel->dev, "failed to enable supply: %d\n", err);
++		return err;
++	}
++
++	if (p->enable_gpio)
++		gpiod_direction_output(p->enable_gpio, 1);
++
++	if (p->desc && p->desc->delay.prepare)
++		panel_simple_sleep(p->desc->delay.prepare);
++
++	if (p->reset_gpio)
++		gpiod_direction_output(p->reset_gpio, !p->reset_level);
++	
++	if (p->desc && p->desc->delay.reset)
++                panel_simple_sleep(p->desc->delay.reset);
++
++       if (p->reset_gpio)
++                gpiod_direction_output(p->reset_gpio, p->reset_level);
++		
++	if (p->desc && p->desc->delay.init)
++		panel_simple_sleep(p->desc->delay.init);
++
++	if (p->on_cmds) {
++		if (p->dsi)
++			err = panel_simple_dsi_send_cmds(p, p->on_cmds);
++		if (err)
++			dev_err(p->dev, "failed to send on cmds\n");
++	}
++
++	p->prepared = true;
++
++	return 0;
++}
++
++static int panel_simple_enable(struct drm_panel *panel)
++{
++	struct panel_simple *p = to_panel_simple(panel);
++	int err = 0;
++
++	if (p->enabled)
++		return 0;
++
++	if (p->desc && p->desc->delay.enable)
++		panel_simple_sleep(p->desc->delay.enable);
++
++	p->enabled = true;
++
++	return 0;
++}
++
++static int panel_simple_get_timings(struct drm_panel *panel,
++				    unsigned int num_timings,
++				    struct display_timing *timings)
++{
++	struct panel_simple *p = to_panel_simple(panel);
++	unsigned int i;
++
++	if (!p->desc)
++		return 0;
++
++	if (p->desc->num_timings < num_timings)
++		num_timings = p->desc->num_timings;
++
++	if (timings)
++		for (i = 0; i < num_timings; i++)
++			timings[i] = p->desc->timings[i];
++
++	return p->desc->num_timings;
++}
++
++static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
++{
++	struct panel_simple *p = to_panel_simple(panel);
++
++	return p->orientation;
++}
++
++
++static const struct drm_panel_funcs panel_simple_funcs = {
++	.disable = panel_simple_disable,
++	.unprepare = panel_simple_unprepare,
++	.prepare = panel_simple_prepare,
++	.enable = panel_simple_enable,
++	.get_modes = panel_simple_get_modes,
++	.get_orientation = panel_simple_get_orientation,
++	.get_timings = panel_simple_get_timings,
++};
++
++static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
++{
++	struct panel_simple *panel;
++	struct panel_desc *of_desc;
++	const char *cmd_type;
++	u32 val;
++	int err;
++
++	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
++	if (!panel)
++		return -ENOMEM;
++
++	if (!desc)
++		of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
++	else
++		of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
++
++	if (!of_property_read_u32(dev->of_node, "bus-format", &val))
++		of_desc->bus_format = val;
++	if (!of_property_read_u32(dev->of_node, "bpc", &val))
++		of_desc->bpc = val;
++	if (!of_property_read_u32(dev->of_node, "prepare-delay-ms", &val))
++		of_desc->delay.prepare = val;
++	if (!of_property_read_u32(dev->of_node, "enable-delay-ms", &val))
++		of_desc->delay.enable = val;
++	if (!of_property_read_u32(dev->of_node, "disable-delay-ms", &val))
++		of_desc->delay.disable = val;
++	if (!of_property_read_u32(dev->of_node, "unprepare-delay-ms", &val))
++		of_desc->delay.unprepare = val;
++	if (!of_property_read_u32(dev->of_node, "reset-delay-ms", &val))
++		of_desc->delay.reset = val;
++	if (!of_property_read_u32(dev->of_node, "init-delay-ms", &val))
++		of_desc->delay.init = val;
++	if (!of_property_read_u32(dev->of_node, "width-mm", &val))
++		of_desc->size.width = val;
++	if (!of_property_read_u32(dev->of_node, "height-mm", &val))
++		of_desc->size.height = val;
++
++	panel->enabled = false;
++	panel->prepared = false;
++	panel->desc = of_desc;
++	panel->dev = dev;
++
++	err = panel_simple_get_cmds(panel);
++	if (err) {
++		dev_err(dev, "failed to get init cmd: %d\n", err);
++		return err;
++	}
++	panel->supply = devm_regulator_get(dev, "power");
++	if (IS_ERR(panel->supply))
++		return PTR_ERR(panel->supply);
++
++	panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
++	if (IS_ERR(panel->enable_gpio)) {
++		err = PTR_ERR(panel->enable_gpio);
++		dev_err(dev, "failed to request enable GPIO: %d\n", err);
++		return err;
++	}
++
++	panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
++	if (IS_ERR(panel->reset_gpio)) {
++		err = PTR_ERR(panel->reset_gpio);
++		dev_err(dev, "failed to request reset GPIO: %d\n", err);
++		return err;
++	}
++	
++	if (!of_property_read_u32(dev->of_node, "reset-level", &val)) {
++		panel->reset_level = val;
++	} else {
++		panel->reset_level = 0;
++	}
++	
++	err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
++	if (err) {
++		dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
++		return err;
++	}
++
++    	panel->cmd_type = CMD_TYPE_DEFAULT;
++
++	panel->power_invert =
++			of_property_read_bool(dev->of_node, "power-invert");
++
++	drm_panel_init(&panel->base, dev, &panel_simple_funcs,DRM_MODE_CONNECTOR_DSI);
++	panel->base.dev = dev;
++	panel->base.funcs = &panel_simple_funcs;
++
++	err = drm_panel_of_backlight(&panel->base);
++	if (err)
++		return err;
++
++	drm_panel_add(&panel->base);
++
++	dev_set_drvdata(dev, panel);
++
++	return 0;
++}
++
++static int panel_simple_remove(struct device *dev)
++{
++	struct panel_simple *panel = dev_get_drvdata(dev);
++
++	drm_panel_remove(&panel->base);
++
++	panel_simple_disable(&panel->base);
++	panel_simple_unprepare(&panel->base);
++
++	panel_simple_cmds_cleanup(panel);
++
++	return 0;
++}
++
++static void panel_simple_shutdown(struct device *dev)
++{
++	struct panel_simple *panel = dev_get_drvdata(dev);
++
++	panel_simple_disable(&panel->base);
++
++	if (panel->prepared) {
++		if (panel->reset_gpio)
++			gpiod_direction_output(panel->reset_gpio, !panel->reset_level);
++
++		if (panel->enable_gpio)
++			gpiod_direction_output(panel->enable_gpio, 0);
++
++		panel_simple_regulator_disable(&panel->base);
++	}
++}
++
++struct panel_desc_dsi {
++	struct panel_desc desc;
++
++	unsigned long flags;
++	enum mipi_dsi_pixel_format format;
++	unsigned int lanes;
++};
++
++/*
++static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
++	.clock = 157200,
++	.hdisplay = 1920,
++	.hsync_start = 1920 + 154,
++	.hsync_end = 1920 + 154 + 16,
++	.htotal = 1920 + 154 + 16 + 32,
++	.vdisplay = 1200,
++	.vsync_start = 1200 + 17,
++	.vsync_end = 1200 + 17 + 2,
++	.vtotal = 1200 + 17 + 2 + 16,
++	.vrefresh = 60,
++};
++static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
++	.desc = {
++		.modes = &panasonic_vvx10f004b00_mode,
++		.num_modes = 1,
++		.bpc = 8,
++		.size = {
++			.width = 217,
++			.height = 136,
++		},
++	},
++	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
++		 MIPI_DSI_CLOCK_NON_CONTINUOUS,
++	.format = MIPI_DSI_FMT_RGB888,
++	.lanes = 4,
++};
++*/
++
++static const struct of_device_id dsi_of_match[] = {
++	{
++		.compatible = "panel-dsi-simple",
++		.data = NULL
++	}, {
++		/* sentinel */
++	}
++};
++MODULE_DEVICE_TABLE(of, dsi_of_match);
++
++static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
++{
++	struct device *dev = &dsi->dev;
++	struct panel_simple *panel;
++	const struct panel_desc_dsi *desc;
++	const struct of_device_id *id;
++	const struct panel_desc *pdesc;
++	int err;
++	u32 val;
++
++	id = of_match_node(dsi_of_match, dev->of_node);
++	if (!id)
++		return -ENODEV;
++
++	desc = id->data;
++
++	if (desc) {
++		dsi->mode_flags = desc->flags;
++		dsi->format = desc->format;
++		dsi->lanes = desc->lanes;
++		pdesc = &desc->desc;
++	} else {
++		pdesc = NULL;
++	}
++
++	err = panel_simple_probe(dev, pdesc);
++	if (err < 0)
++		return err;
++
++	panel = dev_get_drvdata(dev);
++	panel->dsi = dsi;
++
++	if (!of_property_read_u32(dev->of_node, "dsi,flags", &val))
++		dsi->mode_flags = val;
++
++	if (!of_property_read_u32(dev->of_node, "dsi,format", &val))
++		dsi->format = val;
++
++	if (!of_property_read_u32(dev->of_node, "dsi,lanes", &val))
++		dsi->lanes = val;
++
++	return mipi_dsi_attach(dsi);
++}
++
++static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
++{
++	int err;
++
++	err = mipi_dsi_detach(dsi);
++	if (err < 0)
++		dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
++
++	panel_simple_remove(&dsi->dev);
++}
++
++static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
++{
++	panel_simple_shutdown(&dsi->dev);
++}
++
++static struct mipi_dsi_driver panel_simple_dsi_driver = {
++	.driver = {
++		.name = "panel-dsi-simple",
++		.of_match_table = dsi_of_match,
++	},
++	.probe = panel_simple_dsi_probe,
++	.remove = panel_simple_dsi_remove,
++	.shutdown = panel_simple_dsi_shutdown,
++};
++
++module_mipi_dsi_driver(panel_simple_dsi_driver);
++
++MODULE_AUTHOR("iamdrq <iamdrq@qq.com>");
++MODULE_DESCRIPTION("DRM Driver for DSI Simple Panels");
++MODULE_LICENSE("GPL");
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-add-pll-hdmi-timings.patch b/patch/kernel/archive/rockchip64-6.10/general-add-pll-hdmi-timings.patch
new file mode 100644
index 000000000000..1e8adef25fef
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-add-pll-hdmi-timings.patch
@@ -0,0 +1,155 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: paolo <paolo.sabatino@gmail.com>
+Date: Sun, 17 Jan 2021 10:20:21 +0000
+Subject: [ARCHEOLOGY] Adding pll hdmi timing to rockchip64-dev too
+
+> X-Git-Archeology: > recovered message: > Fixed rk3328 mali node, shortening memory range to 0x30000 as per-stated in official documentation
+> X-Git-Archeology: - Revision 3a037e899b06452043e23cd2a17f40fe1a932c5f: https://github.com/armbian/build/commit/3a037e899b06452043e23cd2a17f40fe1a932c5f
+> X-Git-Archeology:   Date: Sun, 17 Jan 2021 10:20:21 +0000
+> X-Git-Archeology:   From: paolo <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: Adding pll hdmi timing to rockchip64-dev too
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 71 ++++++++++
+ 1 file changed, 71 insertions(+)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index 053bd62e31ba..db774d97918f 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -464,6 +464,77 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
+ 	{594000000, 297000000,  1,   99, 0, 1, 1,  1, 0, 1,  1, 0,      0x0},
+ 	{594000000, 371250000,  4,  495, 0, 3, 1,  1, 3, 0,  0, 1,      0x0},
+ 	{594000000, 594000000,  1,   99, 0, 2, 0,  1, 0, 1,  1, 0,      0x0},
++	{ 25175000,  25175000, 30, 1007, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{ 31500000,  31500000,  1,   21, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{ 33750000,  33750000,  1,   45, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{ 35500000,  35500000,  3,   71, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{ 36000000,  36000000,  1,   12, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{ 49500000,  49500000,  1,   33, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{ 50000000,  50000000,  3,   50, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{ 56250000,  56250000,  1,   75, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{ 65000000,  65000000,  3,   65, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{ 68250000,  68250000,  1,   91, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{ 71000000,  71000000,  3,   71, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{ 72000000,  72000000,  1,   24, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{ 73250000,  73250000,  3,  293, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{ 75000000,  75000000,  1,   25, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{ 78750000,  78750000,  1,  105, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{ 79500000,  79500000,  1,   53, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{ 83500000,  83500000,  3,  167, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{ 85500000,  85500000,  1,   57, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{ 88750000,  88750000,  3,  355, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{ 94500000,  94500000,  1,   63, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{101000000, 101000000,  3,  101, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{102250000, 102250000,  3,  409, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{106500000, 106500000,  1,   71, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{108000000, 108000000,  1,   36, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{115500000, 115500000,  1,   77, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{117500000, 117500000,  3,  235, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{119000000, 119000000,  3,  119, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{121750000, 121750000,  3,  487, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{122500000, 122500000,  3,  245, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{135000000, 135000000,  1,   45, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{136750000, 136750000,  3,  547, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{140250000, 140250000,  1,  187, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{146250000, 146250000,  1,  195, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{148250000, 148250000,  3,  593, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{154000000, 154000000,  3,  154, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{156000000, 156000000,  1,   52, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{156750000, 156750000,  1,  209, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{157000000, 157000000,  3,  157, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{157500000, 157500000,  1,  105, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{162000000, 162000000,  1,   54, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{175500000, 175500000,  1,  117, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{179500000, 179500000,  3,  359, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{182750000, 182750000,  3,  731, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{187000000, 187000000,  3,  187, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{187250000, 187250000,  3,  749, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{189000000, 189000000,  1,   63, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{193250000, 193250000,  3,  773, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{202500000, 202500000,  1,  135, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{204750000, 204750000,  1,  273, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{208000000, 208000000,  3,  208, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{214750000, 214750000,  3,  859, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{218250000, 218250000,  1,  291, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{229500000, 229500000,  1,  153, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{234000000, 234000000,  1,   78, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{241500000, 241500000,  1,  161, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{245250000, 245250000,  1,  327, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{245500000, 245500000,  3,  491, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{261000000, 261000000,  1,   87, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{268250000, 268250000,  3, 1073, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{268500000, 268500000,  1,  179, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{281250000, 281250000,  1,  375, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{288000000, 288000000,  1,   96, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{312250000, 312250000,  3, 1249, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{317000000, 317000000,  3,  317, 0, 1, 1, 1, 0, 2, 2, 0, 0},
++	{333250000, 333250000,  3, 1333, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{348500000, 348500000,  3,  697, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{356500000, 356500000,  3,  713, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{380500000, 380500000,  3,  761, 1, 1, 1, 1, 2, 2, 2, 0, 0},
++	{443250000, 443250000,  1,  591, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{505250000, 505250000,  3, 2021, 1, 2, 2, 1, 2, 3, 4, 0, 0},
++	{552750000, 552750000,  1,  737, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ 	{ /* sentinel */ }
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-add-xtx-spi-nor-chips.patch b/patch/kernel/archive/rockchip64-6.10/general-add-xtx-spi-nor-chips.patch
new file mode 100644
index 000000000000..c634008efd61
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-add-xtx-spi-nor-chips.patch
@@ -0,0 +1,82 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: microcai <microcaicai@gmail.com>
+Date: Mon, 29 Jun 2020 23:36:40 +0800
+Subject: spi-nor: Add support for xt25f32b/xt25f128b
+
+The RockPi4b dev board ship with xt25f32b solded. add these ids so the
+board's spi flash can be accessed within linux.
+
+Signed-off-by: microcai <microcaicai@gmail.com>
+---
+ drivers/mtd/spi-nor/Makefile |  1 +
+ drivers/mtd/spi-nor/core.c   |  1 +
+ drivers/mtd/spi-nor/core.h   |  1 +
+ drivers/mtd/spi-nor/xtx.c    | 21 ++++++++++
+ 4 files changed, 24 insertions(+)
+
+diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
+index e347b435a038..364413da729b 100644
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -18,6 +18,7 @@ spi-nor-objs			+= winbond.o
+ spi-nor-objs			+= xilinx.o
+ spi-nor-objs			+= xmc.o
+ spi-nor-$(CONFIG_DEBUG_FS)	+= debugfs.o
++spi-nor-objs			+= xtx.o
+ obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o
+ 
+ obj-$(CONFIG_MTD_SPI_NOR)	+= controllers/
+diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
+index 1b0c6770c14e..0cd1b57ecfcd 100644
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -2015,6 +2015,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
+ 	&spi_nor_winbond,
+ 	&spi_nor_xilinx,
+ 	&spi_nor_xmc,
++	&spi_nor_xtx,
+ };
+ 
+ static const struct flash_info spi_nor_generic_flash = {
+diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
+index 9217379b9cfe..28b90256425a 100644
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -647,6 +647,7 @@ extern const struct spi_nor_manufacturer spi_nor_sst;
+ extern const struct spi_nor_manufacturer spi_nor_winbond;
+ extern const struct spi_nor_manufacturer spi_nor_xilinx;
+ extern const struct spi_nor_manufacturer spi_nor_xmc;
++extern const struct spi_nor_manufacturer spi_nor_xtx;
+ 
+ extern const struct attribute_group *spi_nor_sysfs_groups[];
+ 
+diff --git a/drivers/mtd/spi-nor/xtx.c b/drivers/mtd/spi-nor/xtx.c
+new file mode 100644
+index 000000000000..5a7ec40c9701
+--- /dev/null
++++ b/drivers/mtd/spi-nor/xtx.c
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2005, Intec Automation Inc.
++ * Copyright (C) 2014, Freescale Semiconductor, Inc.
++ */
++
++#include <linux/mtd/spi-nor.h>
++
++#include "core.h"
++
++static const struct flash_info xtx_parts[] = {
++ /* XTX (Shenzhen Xin Tian Xia Tech) */
++ { "xt25f32b", SNOR_ID(0x0b, 0x40, 0x16) },
++ { "xt25f128b", SNOR_ID(0x0b, 0x40, 0x18) },
++};
++
++const struct spi_nor_manufacturer spi_nor_xtx = {
++ .name = "xtx",
++ .parts = xtx_parts,
++ .nparts = ARRAY_SIZE(xtx_parts),
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-cryptov1-trng.patch b/patch/kernel/archive/rockchip64-6.10/general-cryptov1-trng.patch
new file mode 100644
index 000000000000..3e89f9960d68
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-cryptov1-trng.patch
@@ -0,0 +1,304 @@
+From a5046250a7e335dcb8541b8851754e43a362a6a7 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 14 Jan 2024 11:53:20 +0100
+Subject: [PATCH] rockchip64: add TRNG to existing crypto v1 driver
+
+ original patch source: https://patchwork.kernel.org/project/linux-rockchip/patch/20230707115242.3411259-1-clabbe@baylibre.com/
+---
+ drivers/crypto/Kconfig                        |  8 ++
+ drivers/crypto/rockchip/Makefile              |  1 +
+ drivers/crypto/rockchip/rk3288_crypto.c       | 18 +++-
+ drivers/crypto/rockchip/rk3288_crypto.h       | 18 ++++
+ drivers/crypto/rockchip/rk3288_crypto_ahash.c |  2 +
+ .../crypto/rockchip/rk3288_crypto_skcipher.c  |  2 +
+ drivers/crypto/rockchip/rk3288_crypto_trng.c  | 92 +++++++++++++++++++
+ 7 files changed, 140 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/crypto/rockchip/rk3288_crypto_trng.c
+
+diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
+index c761952f0dc6..3c5bffccad5b 100644
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -649,6 +649,14 @@ config CRYPTO_DEV_ROCKCHIP
+ 	  This driver interfaces with the hardware crypto accelerator.
+ 	  Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
+ 
++config CRYPTO_DEV_ROCKCHIP_TRNG
++	bool "Support for Rockchip TRNG"
++	depends on CRYPTO_DEV_ROCKCHIP
++	select HW_RANDOM
++	help
++	  Select this option if you want to provide kernel-side support for
++	  the True Random Number Generator found in the Crypto IP.
++
+ config CRYPTO_DEV_ROCKCHIP_DEBUG
+ 	bool "Enable Rockchip crypto stats"
+ 	depends on CRYPTO_DEV_ROCKCHIP
+diff --git a/drivers/crypto/rockchip/Makefile b/drivers/crypto/rockchip/Makefile
+index 2132d8326223..955e95504b3c 100644
+--- a/drivers/crypto/rockchip/Makefile
++++ b/drivers/crypto/rockchip/Makefile
+@@ -3,3 +3,4 @@ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o
+ rk_crypto-objs := rk3288_crypto.o \
+ 		  rk3288_crypto_skcipher.o \
+ 		  rk3288_crypto_ahash.o
++rk_crypto-$(CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG) += rk3288_crypto_trng.o
+diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c
+index 77d5705a5d96..d17c7069306e 100644
+--- a/drivers/crypto/rockchip/rk3288_crypto.c
++++ b/drivers/crypto/rockchip/rk3288_crypto.c
+@@ -47,15 +47,18 @@ static const struct rk_variant rk3288_variant = {
+ 	.num_clks = 4,
+ 	.rkclks = {
+ 		{ "sclk", 150000000},
+-	}
++	},
++	.trng = false,
+ };
+ 
+ static const struct rk_variant rk3328_variant = {
+ 	.num_clks = 3,
++	.trng = false,
+ };
+ 
+ static const struct rk_variant rk3399_variant = {
+ 	.num_clks = 3,
++	.trng = true,
+ };
+ 
+ static int rk_crypto_get_clks(struct rk_crypto_info *dev)
+@@ -201,6 +204,10 @@ static int rk_crypto_debugfs_show(struct seq_file *seq, void *v)
+ 		seq_printf(seq, "%s %s requests: %lu\n",
+ 			   dev_driver_string(dd->dev), dev_name(dd->dev),
+ 			   dd->nreq);
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG
++		seq_printf(seq, "HWRNG: %lu %lu\n",
++			   dd->hwrng_stat_req, dd->hwrng_stat_bytes);
++#endif
+ 	}
+ 	spin_unlock(&rocklist.lock);
+ 
+@@ -390,6 +397,10 @@ static int rk_crypto_probe(struct platform_device *pdev)
+ 			dev_err(dev, "Fail to register crypto algorithms");
+ 			goto err_register_alg;
+ 		}
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG
++		if (crypto_info->variant->trng)
++			rk3288_hwrng_register(crypto_info);
++#endif
+ 
+ 		register_debugfs(crypto_info);
+ 	}
+@@ -420,6 +431,11 @@ static int rk_crypto_remove(struct platform_device *pdev)
+ #ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG
+ 		debugfs_remove_recursive(rocklist.dbgfs_dir);
+ #endif
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG
++		if (crypto_tmp->variant->trng)
++			rk3288_hwrng_unregister(crypto_tmp);
++#endif
++
+ 		rk_crypto_unregister();
+ 	}
+ 	rk_crypto_pm_exit(crypto_tmp);
+diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h
+index 3aa03cbfb6be..c90bbb1d9069 100644
+--- a/drivers/crypto/rockchip/rk3288_crypto.h
++++ b/drivers/crypto/rockchip/rk3288_crypto.h
+@@ -11,6 +11,7 @@
+ #include <crypto/sha1.h>
+ #include <crypto/sha2.h>
+ #include <linux/dma-mapping.h>
++#include <linux/hw_random.h>
+ #include <linux/interrupt.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/scatterlist.h>
+@@ -180,6 +181,16 @@
+ #define RK_CRYPTO_HASH_DOUT_6		0x01a4
+ #define RK_CRYPTO_HASH_DOUT_7		0x01a8
+ 
++#define RK_CRYPTO_TRNG_CTRL		0x0200
++#define RK_CRYPTO_OSC_ENABLE		BIT(16)
++#define RK_CRYPTO_TRNG_DOUT_0		0x0204
++/* sample < 1000 lead to 100% failure on rngtest,
++ * using more than 1200 does not increase success.
++ */
++#define RK_CRYPTO_RNG_SAMPLE		1200
++
++#define RK_CRYPTO_MAX_TRNG_BYTE		32
++
+ #define CRYPTO_READ(dev, offset)		  \
+ 		readl_relaxed(((dev)->reg + (offset)))
+ #define CRYPTO_WRITE(dev, offset, val)	  \
+@@ -209,6 +220,7 @@ struct rk_clks {
+ struct rk_variant {
+ 	int num_clks;
+ 	struct rk_clks rkclks[RK_MAX_CLKS];
++	bool trng;
+ };
+ 
+ struct rk_crypto_info {
+@@ -219,11 +231,15 @@ struct rk_crypto_info {
+ 	struct reset_control		*rst;
+ 	void __iomem			*reg;
+ 	int				irq;
++	struct mutex			lock;
++	struct hwrng			hwrng;
+ 	const struct rk_variant *variant;
+ 	unsigned long nreq;
+ 	struct crypto_engine *engine;
+ 	struct completion complete;
+ 	int status;
++	unsigned long hwrng_stat_req;
++	unsigned long hwrng_stat_bytes;
+ };
+ 
+ /* the private variable of hash */
+@@ -283,3 +299,5 @@ extern struct rk_crypto_tmp rk_ahash_md5;
+ 
+ struct rk_crypto_info *get_rk_crypto(void);
+ #endif
++int rk3288_hwrng_register(struct rk_crypto_info *rk);
++void rk3288_hwrng_unregister(struct rk_crypto_info *rk);
+diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c
+index 8c143180645e..cefd68b8af5c 100644
+--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c
++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c
+@@ -296,6 +296,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq)
+ 		goto theend;
+ 	}
+ 
++	mutex_lock(&rkc->lock);
+ 	rk_ahash_reg_init(areq, rkc);
+ 
+ 	while (sg) {
+@@ -330,6 +331,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq)
+ 	}
+ 
+ theend:
++	mutex_unlock(&rkc->lock);
+ 	pm_runtime_put_autosuspend(rkc->dev);
+ 
+ 	local_bh_disable();
+diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
+index da95747d973f..4c124d8f9294 100644
+--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
+@@ -363,6 +363,7 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req)
+ 			}
+ 		}
+ 		err = 0;
++		mutex_unlock(&rkc->lock);
+ 		rk_cipher_hw_init(rkc, areq);
+ 		if (ivsize) {
+ 			if (ivsize == DES_BLOCK_SIZE)
+@@ -378,6 +379,7 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req)
+ 		crypto_dma_start(rkc, sgs, sgd, todo / 4);
+ 		wait_for_completion_interruptible_timeout(&rkc->complete,
+ 							  msecs_to_jiffies(2000));
++		mutex_unlock(&rkc->lock);
+ 		if (!rkc->status) {
+ 			dev_err(rkc->dev, "DMA timeout\n");
+ 			err = -EFAULT;
+diff --git a/drivers/crypto/rockchip/rk3288_crypto_trng.c b/drivers/crypto/rockchip/rk3288_crypto_trng.c
+new file mode 100644
+index 000000000000..7a0e1300d0e8
+--- /dev/null
++++ b/drivers/crypto/rockchip/rk3288_crypto_trng.c
+@@ -0,0 +1,92 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rk3288_crypto_trng.c - hardware cryptographic offloader for rockchip
++ *
++ * Copyright (C) 2022-2023 Corentin Labbe <clabbe@baylibre.com>
++ *
++ * This file handle the TRNG
++ */
++#include "rk3288_crypto.h"
++#include <linux/hw_random.h>
++#include <linux/iopoll.h>
++#include <linux/pm_runtime.h>
++
++static int rk3288_trng_read(struct hwrng *hwrng, void *data, size_t max, bool wait)
++{
++	struct rk_crypto_info *rk;
++	unsigned int todo;
++	int err = 0;
++	int i;
++	u32 v;
++
++	rk = container_of(hwrng, struct rk_crypto_info, hwrng);
++
++	todo = min_t(size_t, max, RK_CRYPTO_MAX_TRNG_BYTE);
++
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG
++	rk->hwrng_stat_req++;
++	rk->hwrng_stat_bytes += todo;
++#endif
++
++	err = pm_runtime_resume_and_get(rk->dev);
++	if (err < 0)
++		goto err_pm;
++
++	mutex_lock(&rk->lock);
++
++#define HIWORD_UPDATE(val, mask, shift) \
++			((val) << (shift) | (mask) << ((shift) + 16))
++	v = RK_CRYPTO_OSC_ENABLE | RK_CRYPTO_RNG_SAMPLE;
++	CRYPTO_WRITE(rk, RK_CRYPTO_TRNG_CTRL, v);
++
++	v = HIWORD_UPDATE(RK_CRYPTO_TRNG_START, RK_CRYPTO_TRNG_START, 0);
++	CRYPTO_WRITE(rk, RK_CRYPTO_CTRL, v);
++	wmb();
++
++	err = readl_poll_timeout(rk->reg + RK_CRYPTO_CTRL, v,
++				 !(v & RK_CRYPTO_TRNG_START),
++				 100, 2000);
++	if (err) {
++		dev_err(rk->dev, "HWRNG read timeout");
++		goto readfail;
++	}
++
++	for (i = 0; i < todo / 4; i++) {
++		v = readl(rk->reg + RK_CRYPTO_TRNG_DOUT_0 + i * 4);
++		put_unaligned_le32(v, data + i * 4);
++	}
++
++	err = todo;
++
++	v = HIWORD_UPDATE(0, RK_CRYPTO_TRNG_START, 0);
++	CRYPTO_WRITE(rk, RK_CRYPTO_CTRL, v);
++
++readfail:
++	mutex_unlock(&rk->lock);
++
++	pm_runtime_put(rk->dev);
++
++err_pm:
++	return err;
++}
++
++int rk3288_hwrng_register(struct rk_crypto_info *rk)
++{
++	int ret;
++
++	dev_info(rk->dev, "Register TRNG with sample=%d\n", RK_CRYPTO_RNG_SAMPLE);
++
++	rk->hwrng.name = "Rockchip rk3288 TRNG";
++	rk->hwrng.read = rk3288_trng_read;
++	rk->hwrng.quality = 300;
++
++	ret = hwrng_register(&rk->hwrng);
++	if (ret)
++		dev_err(rk->dev, "Fail to register the TRNG\n");
++	return ret;
++}
++
++void rk3288_hwrng_unregister(struct rk_crypto_info *rk)
++{
++	hwrng_unregister(&rk->hwrng);
++}
+-- 
+2.34.1
+
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-disable-mtu-validation.patch b/patch/kernel/archive/rockchip64-6.10/general-disable-mtu-validation.patch
new file mode 100644
index 000000000000..951aef6b4881
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-disable-mtu-validation.patch
@@ -0,0 +1,51 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igor.pecovnik@gmail.com>
+Date: Wed, 21 Jul 2021 20:59:39 +0000
+Subject: Disable MTU validation
+
+This patch reverts: https://github.com/torvalds/linux/commit/eaf4fac478077d4ed57cbca2c044c4b58a96bd98
+
+It works around following issues:
+ - no way to change MTU (tx_fifo_size is reported as 0 for Rockchip's dwmac)
+
+Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
+Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
+---
+ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 ----------
+ 1 file changed, 12 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+index 5801f4d50f95..6f9b14164fc8 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+@@ -5676,27 +5676,15 @@ static void stmmac_set_rx_mode(struct net_device *dev)
+ static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
+ {
+ 	struct stmmac_priv *priv = netdev_priv(dev);
+-	int txfifosz = priv->plat->tx_fifo_size;
+ 	struct stmmac_dma_conf *dma_conf;
+ 	const int mtu = new_mtu;
+ 	int ret;
+ 
+-	if (txfifosz == 0)
+-		txfifosz = priv->dma_cap.tx_fifo_size;
+-
+-	txfifosz /= priv->plat->tx_queues_to_use;
+-
+ 	if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
+ 		netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
+ 		return -EINVAL;
+ 	}
+ 
+-	new_mtu = STMMAC_ALIGN(new_mtu);
+-
+-	/* If condition true, FIFO is too small or MTU too large */
+-	if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
+-		return -EINVAL;
+-
+ 	if (netif_running(dev)) {
+ 		netdev_dbg(priv->dev, "restarting interface to change its MTU\n");
+ 		/* Try to allocate the new DMA conf with the new mtu */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-fix-es8316-kernel-panic.patch b/patch/kernel/archive/rockchip64-6.10/general-fix-es8316-kernel-panic.patch
new file mode 100644
index 000000000000..7978106e95fd
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-fix-es8316-kernel-panic.patch
@@ -0,0 +1,105 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Yannick Adam <yannick.adam@gmail.com>
+Date: Tue, 14 Apr 2020 17:15:09 +0200
+Subject: [ARCHEOLOGY] Enable es8316 on RockPi4 (#1885)
+
+> X-Git-Archeology: - Revision 454038a50d1d24e636626213ad65b3463d632aa0: https://github.com/armbian/build/commit/454038a50d1d24e636626213ad65b3463d632aa0
+> X-Git-Archeology:   Date: Tue, 14 Apr 2020 17:15:09 +0200
+> X-Git-Archeology:   From: Yannick Adam <yannick.adam@gmail.com>
+> X-Git-Archeology:   Subject: Enable es8316 on RockPi4 (#1885)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision bd486c75623e75bdf2bdcaf09dc5a0affe9706c1: https://github.com/armbian/build/commit/bd486c75623e75bdf2bdcaf09dc5a0affe9706c1
+> X-Git-Archeology:   Date: Tue, 14 Apr 2020 20:14:24 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: Enable es8316 on RockPi4 for Rockchip64 current too https://github.com/armbian/build/pull/1885
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4
+> X-Git-Archeology:   Date: Tue, 11 Jan 2022 15:26:11 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel edge to 5.16 (#3387)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41
+> X-Git-Archeology:   Date: Sun, 20 Mar 2022 22:58:21 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: Adding Pine64 Quartz64a as WIP target (#3539)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c
+> X-Git-Archeology:   Date: Sun, 24 Apr 2022 22:33:47 +0200
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel media edge to 5.17 (#3704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ sound/soc/codecs/es8316.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c
+index a8f347f1affb..a9a7746f1adb 100644
+--- a/sound/soc/codecs/es8316.c
++++ b/sound/soc/codecs/es8316.c
+@@ -702,7 +702,7 @@ static void es8316_disable_jack_detect(struct snd_soc_component *component)
+ 	snd_soc_component_update_bits(component, ES8316_GPIO_DEBOUNCE,
+ 				      ES8316_GPIO_ENABLE_INTERRUPT, 0);
+ 
+-	if (es8316->jack->status & SND_JACK_MICROPHONE) {
++	if (es8316->jack && (es8316->jack->status & SND_JACK_MICROPHONE)) {
+ 		es8316_disable_micbias_for_mic_gnd_short_detect(component);
+ 		snd_soc_jack_report(es8316->jack, 0, SND_JACK_BTN_0);
+ 	}
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-fix-inno-usb2-phy-init.patch b/patch/kernel/archive/rockchip64-6.10/general-fix-inno-usb2-phy-init.patch
new file mode 100644
index 000000000000..550e5183b197
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-fix-inno-usb2-phy-init.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Mon, 22 Aug 2022 20:51:22 +0000
+Subject: remove usb2phy extcon initialization causing kernel oops
+
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+index b982c3f0d4b5..25514646ad8e 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -1286,11 +1286,6 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
+ 			goto out;
+ 		}
+ 
+-		if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
+-			/* do initial sync of usb state */
+-			id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
+-			extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
+-		}
+ 	}
+ 
+ out:
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-fix-mmc-signal-voltage-before-reboot.patch b/patch/kernel/archive/rockchip64-6.10/general-fix-mmc-signal-voltage-before-reboot.patch
new file mode 100644
index 000000000000..9850e7f0a59a
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-fix-mmc-signal-voltage-before-reboot.patch
@@ -0,0 +1,46 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 17 Feb 2019 22:14:38 +0000
+Subject: mmc: core: set initial signal voltage on power off
+
+Some boards have SD card connectors where the power rail cannot be switched
+off by the driver. If the card has not been power cycled, it may still be
+using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
+will fail to boot from a UHS card that continue to use 1.8V signaling.
+
+Set initial signal voltage in mmc_power_off() to allow re-boot to function.
+
+This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
+same issue have been seen on some Rockchip RK3399 boards.
+
+I am sending this as a RFC because I have no insights into SD/MMC subsystem,
+this change fix a re-boot issue on my boards and does not break emmc/sdio.
+Is this an acceptable workaround? Any advice is appreciated.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/mmc/core/core.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
+index 3d3e0ca52614..33cb13b7bf88 100644
+--- a/drivers/mmc/core/core.c
++++ b/drivers/mmc/core/core.c
+@@ -1363,6 +1363,14 @@ void mmc_power_off(struct mmc_host *host)
+ 	if (host->ios.power_mode == MMC_POWER_OFF)
+ 		return;
+ 
++	mmc_set_initial_signal_voltage(host);
++
++	/*
++	 * This delay should be sufficient to allow the power supply
++	 * to reach the minimum voltage.
++	 */
++	mmc_delay(host->ios.power_delay_ms);
++
+ 	mmc_pwrseq_power_off(host);
+ 
+ 	host->ios.clock = 0;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-hdmi-clock-fixes.patch b/patch/kernel/archive/rockchip64-6.10/general-hdmi-clock-fixes.patch
new file mode 100644
index 000000000000..1058b35e10af
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-hdmi-clock-fixes.patch
@@ -0,0 +1,523 @@
+From 5113ec8e82ea78884308aac6b0b8172c417d570b Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 6 Apr 2024 15:40:30 +0200
+Subject: [PATCH 1/2] hdmi timing core changes and fixes
+
+---
+ drivers/clk/rockchip/clk-rk3399.c           | 49 ++++++++++++++++++---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c   | 29 ++++++++----
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 44 +++++++++++++++++-
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 31 ++++++++++---
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  7 +++
+ 6 files changed, 140 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
+index 9ebd6c451b3d..d2391fdd6cb5 100644
+--- a/drivers/clk/rockchip/clk-rk3399.c
++++ b/drivers/clk/rockchip/clk-rk3399.c
+@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
+ 	{ /* sentinel */ },
+ };
+ 
++static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
++	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
++	RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0,  4194304),  /* vco = 1782000000  fout = 594000000 */
++	RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0,  2949838),  /* vco = 1780219777  fout = 593406592.36908 */
++	RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640),  /* vco = 1918500000  fout = 319750000 */
++	RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0,  4194304),  /* vco = 1782000000  fout = 297000000 */
++	RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0,  2949838),  /* vco = 1780219777  fout = 296703296.18454 */
++	RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0,  6291456),  /* vco = 1449000000  fout = 241500000 */
++	RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0,  8388608),  /* vco = 1620000000  fout = 162000000 */
++	RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0,  4194304),  /* vco = 1782000000  fout = 148500000*/
++	RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0,  2949838),  /* vco = 1780219777  fout = 148351648.09227 */
++	RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0,  6291456),  /* vco = 1641000000  fout = 136750000 */
++	RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0,  4194304),  /* vco = 1350000000  fout = 135000000 */
++	RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0,  8388608),  /* vco = 1428000000  fout = 119000000 */
++	RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1,        0),  /* vco = 1512000000  fout = 108000000 */
++	RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0,  2097152),  /* vco = 1491000000  fout = 106500000 */
++	RK3036_PLL_RATE(  88750000, 1, 55, 5, 3, 0,  7864320),  /* vco = 1331250000  fout = 88750000 */
++	RK3036_PLL_RATE(  85500000, 1, 57, 4, 4, 1,        0),  /* vco = 1368000000  fout = 85500000 */
++	RK3036_PLL_RATE(  78750000, 1, 59, 6, 3, 0,  1048576),  /* vco = 1417500000  fout = 78750000 */
++	RK3036_PLL_RATE(  74250000, 1, 74, 6, 4, 0,  4194304),  /* vco = 1782000000  fout = 74250000 */
++	RK3036_PLL_RATE(  74175824, 1, 74, 6, 4, 0,  2949838),  /* vco = 1780219777  fout = 74175824.046135 */
++	RK3036_PLL_RATE(  71000000, 1, 71, 6, 4, 1,        0),  /* vco = 1704000000  fout = 71000000 */
++	RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 0,        0),  /* vco = 1560000000  fout = 65000000 */
++	RK3036_PLL_RATE(  59340659, 1, 59, 6, 4, 0,  5715310),  /* vco = 1424175816  fout = 59340659.022331 */
++	RK3036_PLL_RATE(  54000000, 1, 63, 7, 4, 1,        0),  /* vco = 1512000000  fout = 54000000 */
++	RK3036_PLL_RATE(  49500000, 1, 72, 5, 7, 0,  3145728),  /* vco = 1732500000  fout = 49500000 */
++	RK3036_PLL_RATE(  40000000, 1, 70, 7, 6, 1,        0),  /* vco = 1680000000  fout = 40000000 */
++	RK3036_PLL_RATE(  31500000, 1, 55, 7, 6, 0,  2097152),  /* vco = 1323000000  fout = 31500000 */
++	RK3036_PLL_RATE(  27000000, 1, 55, 7, 7, 0,  2097152),  /* vco = 1323000000  fout = 27000000 */
++	RK3036_PLL_RATE(  26973026, 1, 55, 7, 7, 0,  1173214),  /* vco = 1321678296  fout = 26973026.450799 */
++	{ /* sentinel */ },
++};
++
+ /* CRU parents */
+ PNAME(mux_pll_p)				= { "xin24m", "xin32k" };
+ 
+@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p)				= { "clk_ddrc_lpll_src",
+ PNAME(mux_aclk_cci_p)				= { "cpll_aclk_cci_src",
+ 						    "gpll_aclk_cci_src",
+ 						    "npll_aclk_cci_src",
+-						    "vpll_aclk_cci_src" };
++						    "prevent:vpll" };
+ PNAME(mux_cci_trace_p)				= { "cpll_cci_trace",
+ 						    "gpll_cci_trace" };
+ PNAME(mux_cs_p)					= { "cpll_cs", "gpll_cs",
+@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)	= { "cpll", "gpll", "npll",
+ PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
+ 						    "ppll", "upll", "xin24m" };
+ 
+-PNAME(mux_pll_src_vpll_cpll_gpll_p)		= { "vpll", "cpll", "gpll" };
+-PNAME(mux_pll_src_vpll_cpll_gpll_npll_p)	= { "vpll", "cpll", "gpll",
++PNAME(mux_pll_src_vpll_cpll_gpll_p)		= { "prevent:vpll", "cpll", "gpll" };
++PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p)	= { "vpll", "prevent:cpll", "prevent:gpll" };
++
++PNAME(mux_pll_src_vpll_cpll_gpll_npll_p)	= { "prevent:vpll", "cpll", "gpll",
+ 						    "npll" };
+-PNAME(mux_pll_src_vpll_cpll_gpll_24m_p)		= { "vpll", "cpll", "gpll",
++PNAME(mux_pll_src_vpll_cpll_gpll_24m_p)		= { "prevent:vpll", "cpll", "gpll",
+ 						    "xin24m" };
+ 
+ PNAME(mux_dclk_vop0_p)			= { "dclk_vop0_div",
+@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
+ 	[npll] = PLL(pll_rk3399, PLL_NPLL, "npll",  mux_pll_p, 0, RK3399_PLL_CON(40),
+ 		     RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
+ 	[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll",  mux_pll_p, 0, RK3399_PLL_CON(48),
+-		     RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
++		     RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates),
+ };
+ 
+ static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
+@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
+ 			RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
+ 
+ static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
+-	MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
++	MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ 			RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
+ 
+ static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
+@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
+ 			RK3399_CLKGATE_CON(28), 0, GFLAGS),
+ 
+-	COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
++	COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ 			RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ 			RK3399_CLKGATE_CON(10), 12, GFLAGS),
+ 
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 6c1d79474505..e3de91dc100b 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -68,15 +68,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
+ };
+ 
+ static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
+-	{ 0x2591, 0x1322, 0x074b, 0x0000 },
+-	{ 0x6535, 0x2000, 0x7acc, 0x0200 },
+-	{ 0x6acd, 0x7534, 0x2000, 0x0200 }
++	{ 0x2040, 0x1080, 0x0640, 0x0040 },
++	{ 0xe880, 0x1c00, 0xfb80, 0x0200 },
++	{ 0xed80, 0xf680, 0x1c00, 0x0200 }
+ };
+ 
+ static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
+-	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
+-	{ 0x62f0, 0x2000, 0x7d11, 0x0200 },
+-	{ 0x6756, 0x78ab, 0x2000, 0x0200 }
++	{ 0x2740, 0x0bc0, 0x0400, 0x0040 },
++	{ 0xe680, 0x1c00, 0xfd80, 0x0200 },
++	{ 0xea40, 0xf980, 0x1c00, 0x0200 }
+ };
+ 
+ static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 341550199111..1159fc713a2a 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -176,6 +176,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ 	}
+ };
+ 
++static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = {
++	{
++		30666000, {
++			{ 0x00b7, 0x0000 },
++			{ 0x2157, 0x0000 },
++			{ 0x40f7, 0x0000 },
++		},
++	},  {
++		92000000, {
++			{ 0x00b7, 0x0000 },
++			{ 0x2143, 0x0001 },
++			{ 0x40a3, 0x0001 },
++		},
++	},  {
++		184000000, {
++			{ 0x0073, 0x0001 },
++			{ 0x2146, 0x0002 },
++			{ 0x4062, 0x0002 },
++		},
++	},  {
++		340000000, {
++			{ 0x0052, 0x0003 },
++			{ 0x214d, 0x0003 },
++			{ 0x4065, 0x0003 },
++		},
++	},  {
++		600000000, {
++			{ 0x0041, 0x0003 },
++			{ 0x3b4d, 0x0003 },
++			{ 0x5a65, 0x0003 },
++		},
++	},  {
++		~0UL, {
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++		},
++	}
++};
++
+ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ 	/*      pixelclk    bpp8    bpp10   bpp12 */
+ 	{
+@@ -202,7 +242,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
+ 	/*pixelclk   symbol   term   vlev*/
+ 	{ 74250000,  0x8009, 0x0004, 0x0272},
+-	{ 148500000, 0x802b, 0x0004, 0x028d},
++	{ 165000000, 0x802b, 0x0004, 0x0209},
+ 	{ 297000000, 0x8039, 0x0005, 0x028d},
+ 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
+ };
+@@ -363,6 +403,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
+ {
+ 	struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
+ 
++	dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display);
++
+ 	return phy_power_on(hdmi->phy);
+ }
+ 
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index 4b338cb89d32..468347e16f92 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -381,8 +381,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
+ 	if (info->is_yuv)
+ 		is_yuv = true;
+ 
+-	if (dst_w > 3840) {
+-		DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
++	if (dst_w > 4096) {
++		DRM_DEV_ERROR(vop->dev, "Maximum dst width (4096) exceeded\n");
+ 		return;
+ 	}
+ 
+@@ -923,6 +923,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
+ 	int format;
+ 	int is_yuv = fb->format->is_yuv;
+ 	int i;
++	int skiplines = 0;
+ 
+ 	/*
+ 	 * can't update plane when vop is disabled.
+@@ -941,8 +942,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
+ 	obj = fb->obj[0];
+ 	rk_obj = to_rockchip_obj(obj);
+ 
++	/*
++	 * Force skip lines when image is yuv and 3840 width,
++	 * fixes a "jumping" green lines issue on RK3328.
++	 */
+ 	actual_w = drm_rect_width(src) >> 16;
+-	actual_h = drm_rect_height(src) >> 16;
++	if (actual_w == 3840 && is_yuv)
++		skiplines = 1;
++	actual_h = drm_rect_height(src) >> (16 + skiplines);
+ 	act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
+ 
+ 	dsp_info = (drm_rect_height(dest) - 1) << 16;
+@@ -1022,7 +1022,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
+ 		offset += (src->y1 >> 16) * fb->pitches[1] / fb->format->vsub;
+ 
+ 		dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
+-		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
++		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4 >> skiplines));
+ 		VOP_WIN_SET(vop, win, uv_mst, dma_addr);
+ 
+ 		for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index 7b2805006776..ffa0c717290e 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -731,6 +731,7 @@ static const struct vop_intr rk3288_vop_intr = {
+ static const struct vop_data rk3288_vop = {
+ 	.version = VOP_VERSION(3, 1),
+ 	.feature = VOP_FEATURE_OUTPUT_RGB10,
++	.max_output = { 3840, 2160 },
+ 	.intr = &rk3288_vop_intr,
+ 	.common = &rk3288_common,
+ 	.modeset = &rk3288_modeset,
+@@ -838,6 +839,7 @@ static const struct vop_misc rk3368_misc = {
+ 
+ static const struct vop_data rk3368_vop = {
+ 	.version = VOP_VERSION(3, 2),
++	.max_output = { 4096, 2160 },
+ 	.intr = &rk3368_vop_intr,
+ 	.common = &rk3288_common,
+ 	.modeset = &rk3288_modeset,
+@@ -860,6 +862,7 @@ static const struct vop_intr rk3366_vop_intr = {
+ 
+ static const struct vop_data rk3366_vop = {
+ 	.version = VOP_VERSION(3, 4),
++	.max_output = { 4096, 2160 },
+ 	.intr = &rk3366_vop_intr,
+ 	.common = &rk3288_common,
+ 	.modeset = &rk3288_modeset,
+@@ -988,6 +991,7 @@ static const struct vop_afbc rk3399_vop_afbc = {
+ static const struct vop_data rk3399_vop_big = {
+ 	.version = VOP_VERSION(3, 5),
+ 	.feature = VOP_FEATURE_OUTPUT_RGB10,
++	.max_output = { 4096, 2160 },
+ 	.intr = &rk3366_vop_intr,
+ 	.common = &rk3399_common,
+ 	.modeset = &rk3288_modeset,
+@@ -1016,6 +1020,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = {
+ 
+ static const struct vop_data rk3399_vop_lit = {
+ 	.version = VOP_VERSION(3, 6),
++	.max_output = { 2560, 1600 },
+ 	.intr = &rk3366_vop_intr,
+ 	.common = &rk3399_common,
+ 	.modeset = &rk3288_modeset,
+@@ -1038,6 +1043,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = {
+ static const struct vop_data rk3228_vop = {
+ 	.version = VOP_VERSION(3, 7),
+ 	.feature = VOP_FEATURE_OUTPUT_RGB10,
++	.max_output = { 4096, 2160 },
+ 	.intr = &rk3366_vop_intr,
+ 	.common = &rk3288_common,
+ 	.modeset = &rk3288_modeset,
+@@ -1110,6 +1116,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = {
+ static const struct vop_data rk3328_vop = {
+ 	.version = VOP_VERSION(3, 8),
+ 	.feature = VOP_FEATURE_OUTPUT_RGB10,
++	.max_output = { 4096, 2160 },
+ 	.intr = &rk3328_vop_intr,
+ 	.common = &rk3328_common,
+ 	.modeset = &rk3328_modeset,
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Miouyouyou <myy@miouyouyou.fr>
+Date: Sun, 24 May 2020 23:08:01 +0200
+Subject: [ARCHEOLOGY] [RFC] RK3288 : Add HDMI resolutions (#1887)
+
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 147 +++++-----
+ 1 file changed, 68 insertions(+), 79 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 341550199111..05c5a4fb16b2 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -92,86 +92,88 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
+ 
+ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ 	{
+-		27000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++		30666000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40f3, 0x0000 },
+ 		},
+-	}, {
+-		36000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++	},  {
++		36800000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40a2, 0x0001 },
+ 		},
+-	}, {
+-		40000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++	},  {
++		46000000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
+ 		},
+-	}, {
+-		54000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
++	},  {
++		61333000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
+ 		},
+-	}, {
+-		65000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
++	},  {
++		73600000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x4061, 0x0002 },
+ 		},
+-	}, {
+-		66000000, {
+-			{ 0x013e, 0x0003},
+-			{ 0x217e, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		92000000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
+ 		},
+-	}, {
+-		74250000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		122666000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
+ 		},
+-	}, {
+-		83500000, {
+-			{ 0x0072, 0x0001},
++	},  {
++		147200000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4064, 0x0003 },
+ 		},
+-	}, {
+-		108000000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		184000000, {
++			{ 0x0051, 0x0002 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
+ 		},
+-	}, {
+-		106500000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		146250000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		226666000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
+ 		},
+-	}, {
+-		148500000, {
+-			{ 0x0051, 0x0003},
+-			{ 0x214c, 0x0003},
+-			{ 0x4064, 0x0003}
++	},  {
++		272000000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x5a64, 0x0003 },
+ 		},
+-	}, {
++	},  {
+ 		340000000, {
+ 			{ 0x0040, 0x0003 },
+ 			{ 0x3b4c, 0x0003 },
+ 			{ 0x5a64, 0x0003 },
+ 		},
+-	}, {
++	},  {
++		600000000, {
++			{ 0x1a40, 0x0003 },
++			{ 0x3b4c, 0x0003 },
++			{ 0x5a64, 0x0003 },
++		},
++	},  {
+ 		~0UL, {
+-			{ 0x00a0, 0x000a },
+-			{ 0x2001, 0x000f },
+-			{ 0x4002, 0x000f },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
+ 		},
+ 	}
+ };
+@@ -179,22 +181,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ 	/*      pixelclk    bpp8    bpp10   bpp12 */
+ 	{
+-		40000000,  { 0x0018, 0x0018, 0x0018 },
+-	}, {
+-		65000000,  { 0x0028, 0x0028, 0x0028 },
+-	}, {
+-		66000000,  { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		74250000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		83500000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		146250000, { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		148500000, { 0x0000, 0x0038, 0x0038 },
+-	}, {
+ 		600000000, { 0x0000, 0x0000, 0x0000 },
+-	}, {
++	}, {
+ 		~0UL,      { 0x0000, 0x0000, 0x0000},
+ 	}
+ };
+@@ -204,6 +192,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
+ 	{ 74250000,  0x8009, 0x0004, 0x0272},
+ 	{ 148500000, 0x802b, 0x0004, 0x028d},
+ 	{ 297000000, 0x8039, 0x0005, 0x028d},
++	{ 594000000, 0x8039, 0x0000, 0x019d},
+ 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
+ };
+ 
+@@ -257,7 +246,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
+ 	struct rockchip_hdmi *hdmi = data;
+ 	const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
+ 	int pclk = mode->clock * 1000;
+-	bool exact_match = hdmi->plat_data->phy_force_vendor;
++	bool exact_match = false;
+ 	int i;
+ 
+ 	if (hdmi->ref_clk) {
+
+-- 
+2.34.1
diff --git a/patch/kernel/archive/rockchip64-6.10/general-increasing_DMA_block_memory_allocation_to_2048.patch b/patch/kernel/archive/rockchip64-6.10/general-increasing_DMA_block_memory_allocation_to_2048.patch
new file mode 100644
index 000000000000..e6f706a0ac16
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-increasing_DMA_block_memory_allocation_to_2048.patch
@@ -0,0 +1,21 @@
+diff --git a/kernel/dma/pool.c b/kernel/dma/pool.c
+index d10613eb0f63..d2223bc39f79 100644
+--- a/kernel/dma/pool.c
++++ b/kernel/dma/pool.c
+@@ -189,13 +189,11 @@ static int __init dma_atomic_pool_init(void)
+ 	int ret = 0;
+ 
+ 	/*
+-	 * If coherent_pool was not used on the command line, default the pool
+-	 * sizes to 128KB per 1GB of memory, min 128KB, max MAX_PAGE_ORDER.
++	 * Always use 2MiB as default pool size.
++	 * See: https://forum.armbian.com/topic/4811-uas-mainline-kernel-coherent-pool-memory-size/
+ 	 */
+ 	if (!atomic_pool_size) {
+-		unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
+-		pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES);
+-		atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K);
++		atomic_pool_size = SZ_2M;
+ 	}
+ 	INIT_WORK(&atomic_pool_work, atomic_pool_work_fn);
+ 
diff --git a/patch/kernel/archive/rockchip64-6.10/general-legacy-rockchip-hwrng.patch b/patch/kernel/archive/rockchip64-6.10/general-legacy-rockchip-hwrng.patch
new file mode 100644
index 000000000000..4dad1529a165
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-legacy-rockchip-hwrng.patch
@@ -0,0 +1,436 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: brentr <brent@mbari.org>
+Date: Sat, 15 Oct 2022 10:46:04 +0200
+Subject: [ARCHEOLOGY] Restored Hardware Random Number Generator from legacy
+ (4.4) kernel (#4286)
+
+> X-Git-Archeology: > recovered message: > so boot no longer starves for entropy, delaying for up to 15 seconds
+> X-Git-Archeology: > recovered message: > Advances kernel to v5.19.15
+> X-Git-Archeology: - Revision f6f3f1b8b034bf7c1f069e831fc42a46940d2239: https://github.com/armbian/build/commit/f6f3f1b8b034bf7c1f069e831fc42a46940d2239
+> X-Git-Archeology:   Date: Sat, 15 Oct 2022 10:46:04 +0200
+> X-Git-Archeology:   From: brentr <brent@mbari.org>
+> X-Git-Archeology:   Subject: Restored Hardware Random Number Generator from legacy (4.4) kernel (#4286)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi |  15 +
+ drivers/char/hw_random/Kconfig           |  13 +
+ drivers/char/hw_random/Makefile          |   1 +
+ drivers/char/hw_random/rockchip-rng.c    | 330 ++++++++++
+ 4 files changed, 359 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+index c5fe355c6deb..3eaef6941a8f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -655,6 +655,21 @@ logic_thermal: logic-thermal {
+ 		};
+ 	};
+ 
++	rng: rng@ff2f0000 {
++		compatible = "rockchip,cryptov2-rng";
++		reg = <0x0 0xff2f0000 0x0 0x4000>;
++		clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
++			<&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
++		clock-names = "clk_crypto", "clk_crypto_apk",
++				"aclk_crypto", "hclk_crypto";
++		assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
++					<&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
++		assigned-clock-rates = <150000000>, <150000000>,
++					<200000000>, <100000000>;
++		resets = <&cru SRST_CRYPTO>;
++		reset-names = "reset";
++	};
++
+ 	tsadc: tsadc@ff1f0000 {
+ 		compatible = "rockchip,rk3308-tsadc";
+ 		reg = <0x0 0xff1f0000 0x0 0x100>;
+diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
+index 8de74dcfa18c..89000c996d77 100644
+--- a/drivers/char/hw_random/Kconfig
++++ b/drivers/char/hw_random/Kconfig
+@@ -383,6 +383,19 @@ config HW_RANDOM_STM32
+ 
+ 	  If unsure, say N.
+ 
++config HW_RANDOM_ROCKCHIP
++	tristate "Rockchip Random Number Generator support"
++	depends on ARCH_ROCKCHIP
++	default HW_RANDOM
++	help
++	  This driver provides kernel-side support for the Random Number
++	  Generator hardware found on Rockchip cpus.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called rockchip-rng.
++
++	  If unsure, say Y.
++
+ config HW_RANDOM_PIC32
+ 	tristate "Microchip PIC32 Random Number Generator support"
+ 	depends on MACH_PIC32 || COMPILE_TEST
+diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
+index 32549a1186dc..fd3bbf6e08e1 100644
+--- a/drivers/char/hw_random/Makefile
++++ b/drivers/char/hw_random/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
+ obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
+ obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
+ obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
+ obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
+ obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
+ obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
+diff --git a/drivers/char/hw_random/rockchip-rng.c b/drivers/char/hw_random/rockchip-rng.c
+new file mode 100644
+index 000000000000..c0121f1f542e
+--- /dev/null
++++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -0,0 +1,330 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rockchip-rng.c Random Number Generator driver for the Rockchip
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
++ * Author: Lin Jinhan <troy.lin@rock-chips.com>
++ *
++ */
++#include <linux/clk.h>
++#include <linux/hw_random.h>
++#include <linux/iopoll.h>
++#include <linux/module.h>
++#include <linux/mod_devicetable.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++
++#define _SBF(s, v)	((v) << (s))
++#define HIWORD_UPDATE(val, mask, shift) \
++			((val) << (shift) | (mask) << ((shift) + 16))
++
++#define ROCKCHIP_AUTOSUSPEND_DELAY		100
++#define ROCKCHIP_POLL_PERIOD_US			100
++#define ROCKCHIP_POLL_TIMEOUT_US		10000
++#define RK_MAX_RNG_BYTE				(32)
++
++#define CRYPTO_V1_CTRL				0x0008
++#define CRYPTO_V1_RNG_START			BIT(8)
++#define CRYPTO_V1_RNG_FLUSH			BIT(9)
++#define CRYPTO_V1_TRNG_CTRL			0x0200
++#define CRYPTO_V1_OSC_ENABLE			BIT(16)
++#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x)		(x)
++#define CRYPTO_V1_TRNG_DOUT_0			0x0204
++
++#define CRYPTO_V2_RNG_CTL			0x0400
++#define CRYPTO_V2_RNG_64_BIT_LEN		_SBF(4, 0x00)
++#define CRYPTO_V2_RNG_128_BIT_LEN		_SBF(4, 0x01)
++#define CRYPTO_V2_RNG_192_BIT_LEN		_SBF(4, 0x02)
++#define CRYPTO_V2_RNG_256_BIT_LEN		_SBF(4, 0x03)
++#define CRYPTO_V2_RNG_FATESY_SOC_RING		_SBF(2, 0x00)
++#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0		_SBF(2, 0x01)
++#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1		_SBF(2, 0x02)
++#define CRYPTO_V2_RNG_SLOWEST_SOC_RING		_SBF(2, 0x03)
++#define CRYPTO_V2_RNG_ENABLE			BIT(1)
++#define CRYPTO_V2_RNG_START			BIT(0)
++#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0404
++#define CRYPTO_V2_RNG_DOUT_0			0x0410
++
++struct rk_rng_soc_data {
++	const char * const *clks;
++	int clks_num;
++	int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
++};
++
++struct rk_rng {
++	struct device		*dev;
++	struct hwrng		rng;
++	void __iomem		*mem;
++	struct rk_rng_soc_data	*soc_data;
++	u32			clk_num;
++	struct clk_bulk_data	*clk_bulks;
++};
++
++static const char * const rk_rng_v1_clks[] = {
++	"hclk_crypto",
++	"clk_crypto",
++};
++
++static const char * const rk_rng_v2_clks[] = {
++	"hclk_crypto",
++	"aclk_crypto",
++	"clk_crypto",
++	"clk_crypto_apk",
++};
++
++static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
++{
++	__raw_writel(val, rng->mem + offset);
++}
++
++static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
++{
++	return __raw_readl(rng->mem + offset);
++}
++
++static int rk_rng_init(struct hwrng *rng)
++{
++	int ret;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
++	if (ret < 0) {
++		dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static void rk_rng_cleanup(struct hwrng *rng)
++{
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
++}
++
++static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
++			     size_t size)
++{
++	u32 i, sample;
++
++	for (i = 0; i < size; i += 4) {
++		sample = rk_rng_readl(rng, offset + i);
++		memcpy(buf + i, &sample, sizeof(sample));
++	}
++}
++
++static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	int ret = 0;
++	u32 reg_ctrl = 0;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	ret = pm_runtime_get_sync(rk_rng->dev);
++	if (ret < 0) {
++		pm_runtime_put_noidle(rk_rng->dev);
++		return ret;
++	}
++
++	/* enable osc_ring to get entropy, sample period is set as 100 */
++	reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
++	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
++
++	reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
++
++	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
++
++	ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl,
++				 !(reg_ctrl & CRYPTO_V1_RNG_START),
++				 ROCKCHIP_POLL_PERIOD_US,
++				 ROCKCHIP_POLL_TIMEOUT_US);
++	if (ret < 0)
++		goto out;
++
++	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
++
++	rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
++
++out:
++	/* close TRNG */
++	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
++		      CRYPTO_V1_CTRL);
++
++	pm_runtime_mark_last_busy(rk_rng->dev);
++	pm_runtime_put_sync_autosuspend(rk_rng->dev);
++
++	return ret;
++}
++
++static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	int ret = 0;
++	u32 reg_ctrl = 0;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	ret = pm_runtime_get_sync(rk_rng->dev);
++	if (ret < 0) {
++		pm_runtime_put_noidle(rk_rng->dev);
++		return ret;
++	}
++
++	/* enable osc_ring to get entropy, sample period is set as 100 */
++	rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
++
++	reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
++	reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
++	reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
++	reg_ctrl |= CRYPTO_V2_RNG_START;
++
++	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
++			CRYPTO_V2_RNG_CTL);
++
++	ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
++				 !(reg_ctrl & CRYPTO_V2_RNG_START),
++				 ROCKCHIP_POLL_PERIOD_US,
++				 ROCKCHIP_POLL_TIMEOUT_US);
++	if (ret < 0)
++		goto out;
++
++	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
++
++	rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
++
++out:
++	/* close TRNG */
++	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
++
++	pm_runtime_mark_last_busy(rk_rng->dev);
++	pm_runtime_put_sync_autosuspend(rk_rng->dev);
++
++	return ret;
++}
++
++static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
++	.clks_num = ARRAY_SIZE(rk_rng_v1_clks),
++	.clks = rk_rng_v1_clks,
++	.rk_rng_read = rk_rng_v1_read,
++};
++
++static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
++	.clks_num = ARRAY_SIZE(rk_rng_v2_clks),
++	.clks = rk_rng_v2_clks,
++	.rk_rng_read = rk_rng_v2_read,
++};
++
++static const struct of_device_id rk_rng_dt_match[] = {
++	{
++		.compatible = "rockchip,cryptov1-rng",
++		.data = (void *)&rk_rng_v1_soc_data,
++	},
++	{
++		.compatible = "rockchip,cryptov2-rng",
++		.data = (void *)&rk_rng_v2_soc_data,
++	},
++	{ },
++};
++
++MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
++
++static int rk_rng_probe(struct platform_device *pdev)
++{
++	int i;
++	int ret;
++	struct rk_rng *rk_rng;
++	struct device_node *np = pdev->dev.of_node;
++	const struct of_device_id *match;
++
++	rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
++	if (!rk_rng)
++		return -ENOMEM;
++
++	match = of_match_node(rk_rng_dt_match, np);
++	rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
++
++	rk_rng->dev = &pdev->dev;
++	rk_rng->rng.name    = "rockchip";
++#ifndef CONFIG_PM
++	rk_rng->rng.init    = rk_rng_init;
++	rk_rng->rng.cleanup = rk_rng_cleanup,
++#endif
++	rk_rng->rng.read    = rk_rng->soc_data->rk_rng_read;
++	rk_rng->rng.quality = 1024;
++
++	rk_rng->clk_bulks =
++		devm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) *
++			     rk_rng->soc_data->clks_num, GFP_KERNEL);
++
++	rk_rng->clk_num = rk_rng->soc_data->clks_num;
++
++	for (i = 0; i < rk_rng->soc_data->clks_num; i++)
++		rk_rng->clk_bulks[i].id = rk_rng->soc_data->clks[i];
++
++	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
++	if (IS_ERR(rk_rng->mem))
++		return PTR_ERR(rk_rng->mem);
++
++	ret = devm_clk_bulk_get(&pdev->dev, rk_rng->clk_num,
++				rk_rng->clk_bulks);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to get clks property\n");
++		return ret;
++	}
++
++	platform_set_drvdata(pdev, rk_rng);
++
++	pm_runtime_set_autosuspend_delay(&pdev->dev,
++					ROCKCHIP_AUTOSUSPEND_DELAY);
++	pm_runtime_use_autosuspend(&pdev->dev);
++	pm_runtime_enable(&pdev->dev);
++
++	ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
++	if (ret) {
++		pm_runtime_dont_use_autosuspend(&pdev->dev);
++		pm_runtime_disable(&pdev->dev);
++	}
++
++	return ret;
++}
++
++#ifdef CONFIG_PM
++static int rk_rng_runtime_suspend(struct device *dev)
++{
++	struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++	rk_rng_cleanup(&rk_rng->rng);
++
++	return 0;
++}
++
++static int rk_rng_runtime_resume(struct device *dev)
++{
++	struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++	return rk_rng_init(&rk_rng->rng);
++}
++
++static const struct dev_pm_ops rk_rng_pm_ops = {
++	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
++				rk_rng_runtime_resume, NULL)
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
++};
++#endif
++
++static struct platform_driver rk_rng_driver = {
++	.driver	= {
++		.name	= "rockchip-rng",
++#ifdef CONFIG_PM
++		.pm	= &rk_rng_pm_ops,
++#endif
++		.of_match_table = rk_rng_dt_match,
++	},
++	.probe	= rk_rng_probe,
++};
++
++module_platform_driver(rk_rng_driver);
++
++MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
++MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-legacy-rockchip-hwrng_5.10.patch b/patch/kernel/archive/rockchip64-6.10/general-legacy-rockchip-hwrng_5.10.patch
new file mode 100644
index 000000000000..5fa902ca1ce6
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-legacy-rockchip-hwrng_5.10.patch
@@ -0,0 +1,523 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: brentr <brent@mbari.org>
+Date: Fri, 25 Nov 2022 18:02:13 +0100
+Subject: [ARCHEOLOGY] Updated v4.4 HW RND driver with that from v5.10 kernel
+ (#4485)
+
+> X-Git-Archeology: - Revision d8fd01bc54d666efc1145920ad5538b050a7ef2c: https://github.com/armbian/build/commit/d8fd01bc54d666efc1145920ad5538b050a7ef2c
+> X-Git-Archeology:   Date: Fri, 25 Nov 2022 18:02:13 +0100
+> X-Git-Archeology:   From: brentr <brent@mbari.org>
+> X-Git-Archeology:   Subject: Updated v4.4 HW RND driver with that from v5.10 kernel (#4485)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ drivers/char/hw_random/rockchip-rng.c | 328 +++++++---
+ 1 file changed, 249 insertions(+), 79 deletions(-)
+
+diff --git a/drivers/char/hw_random/rockchip-rng.c b/drivers/char/hw_random/rockchip-rng.c
+index c0121f1f542e..13503c54fe62 100644
+--- a/drivers/char/hw_random/rockchip-rng.c
++++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -21,18 +21,24 @@
+ 
+ #define ROCKCHIP_AUTOSUSPEND_DELAY		100
+ #define ROCKCHIP_POLL_PERIOD_US			100
+-#define ROCKCHIP_POLL_TIMEOUT_US		10000
++#define ROCKCHIP_POLL_TIMEOUT_US		50000
+ #define RK_MAX_RNG_BYTE				(32)
+ 
++/* start of CRYPTO V1 register define */
+ #define CRYPTO_V1_CTRL				0x0008
+ #define CRYPTO_V1_RNG_START			BIT(8)
+ #define CRYPTO_V1_RNG_FLUSH			BIT(9)
++
+ #define CRYPTO_V1_TRNG_CTRL			0x0200
+ #define CRYPTO_V1_OSC_ENABLE			BIT(16)
+ #define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x)		(x)
++
+ #define CRYPTO_V1_TRNG_DOUT_0			0x0204
++/* end of CRYPTO V1 register define */
+ 
+-#define CRYPTO_V2_RNG_CTL			0x0400
++/* start of CRYPTO V2 register define */
++#define CRYPTO_V2_RNG_DEFAULT_OFFSET		0x0400
++#define CRYPTO_V2_RNG_CTL			0x0
+ #define CRYPTO_V2_RNG_64_BIT_LEN		_SBF(4, 0x00)
+ #define CRYPTO_V2_RNG_128_BIT_LEN		_SBF(4, 0x01)
+ #define CRYPTO_V2_RNG_192_BIT_LEN		_SBF(4, 0x02)
+@@ -43,12 +49,48 @@
+ #define CRYPTO_V2_RNG_SLOWEST_SOC_RING		_SBF(2, 0x03)
+ #define CRYPTO_V2_RNG_ENABLE			BIT(1)
+ #define CRYPTO_V2_RNG_START			BIT(0)
+-#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0404
+-#define CRYPTO_V2_RNG_DOUT_0			0x0410
++#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0004
++#define CRYPTO_V2_RNG_DOUT_0			0x0010
++/* end of CRYPTO V2 register define */
++
++/* start of TRNG_V1 register define */
++/* TRNG is no longer subordinate to the Crypto module */
++#define TRNG_V1_CTRL				0x0000
++#define TRNG_V1_CTRL_NOP			_SBF(0, 0x00)
++#define TRNG_V1_CTRL_RAND			_SBF(0, 0x01)
++#define TRNG_V1_CTRL_SEED			_SBF(0, 0x02)
++
++#define TRNG_V1_STAT				0x0004
++#define TRNG_V1_STAT_SEEDED			BIT(9)
++#define TRNG_V1_STAT_GENERATING			BIT(30)
++#define TRNG_V1_STAT_RESEEDING			BIT(31)
++
++#define TRNG_V1_MODE				0x0008
++#define TRNG_V1_MODE_128_BIT			_SBF(3, 0x00)
++#define TRNG_V1_MODE_256_BIT			_SBF(3, 0x01)
++
++#define TRNG_V1_IE				0x0010
++#define TRNG_V1_IE_GLBL_EN			BIT(31)
++#define TRNG_V1_IE_SEED_DONE_EN			BIT(1)
++#define TRNG_V1_IE_RAND_RDY_EN			BIT(0)
++
++#define TRNG_V1_ISTAT				0x0014
++#define TRNG_V1_ISTAT_RAND_RDY			BIT(0)
++
++/* RAND0 ~ RAND7 */
++#define TRNG_V1_RAND0				0x0020
++#define TRNG_V1_RAND7				0x003C
++
++#define TRNG_V1_AUTO_RQSTS			0x0060
++
++#define TRNG_V1_VERSION				0x00F0
++#define TRNG_v1_VERSION_CODE			0x46bc
++/* end of TRNG_V1 register define */
+ 
+ struct rk_rng_soc_data {
+-	const char * const *clks;
+-	int clks_num;
++	u32 default_offset;
++
++	int (*rk_rng_init)(struct hwrng *rng);
+ 	int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
+ };
+ 
+@@ -57,22 +99,10 @@ struct rk_rng {
+ 	struct hwrng		rng;
+ 	void __iomem		*mem;
+ 	struct rk_rng_soc_data	*soc_data;
+-	u32			clk_num;
++	int			clk_num;
+ 	struct clk_bulk_data	*clk_bulks;
+ };
+ 
+-static const char * const rk_rng_v1_clks[] = {
+-	"hclk_crypto",
+-	"clk_crypto",
+-};
+-
+-static const char * const rk_rng_v2_clks[] = {
+-	"hclk_crypto",
+-	"aclk_crypto",
+-	"clk_crypto",
+-	"clk_crypto_apk",
+-};
+-
+ static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
+ {
+ 	__raw_writel(val, rng->mem + offset);
+@@ -88,6 +118,8 @@ static int rk_rng_init(struct hwrng *rng)
+ 	int ret;
+ 	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+ 
++	dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
++
+ 	ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
+ 	if (ret < 0) {
+ 		dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
+@@ -101,32 +133,57 @@ static void rk_rng_cleanup(struct hwrng *rng)
+ {
+ 	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+ 
++	dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
+ 	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
+ }
+ 
++static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	int ret;
++	int read_len = 0;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	if (!rk_rng->soc_data->rk_rng_read)
++		return -EFAULT;
++
++	ret = pm_runtime_get_sync(rk_rng->dev);
++	if (ret < 0) {
++		pm_runtime_put_noidle(rk_rng->dev);
++		return ret;
++	}
++
++	ret = 0;
++	while (max > ret) {
++		read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
++							 max - ret, wait);
++		if (read_len < 0) {
++			ret = read_len;
++			break;
++		}
++		ret += read_len;
++	}
++
++	pm_runtime_mark_last_busy(rk_rng->dev);
++	pm_runtime_put_sync_autosuspend(rk_rng->dev);
++
++	return ret;
++}
++
+ static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
+ 			     size_t size)
+ {
+-	u32 i, sample;
++	u32 i;
+ 
+-	for (i = 0; i < size; i += 4) {
+-		sample = rk_rng_readl(rng, offset + i);
+-		memcpy(buf + i, &sample, sizeof(sample));
+-	}
++	for (i = 0; i < size; i += 4)
++		*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
+ }
+ 
+-static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++static int rk_crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+ {
+ 	int ret = 0;
+ 	u32 reg_ctrl = 0;
+ 	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+ 
+-	ret = pm_runtime_get_sync(rk_rng->dev);
+-	if (ret < 0) {
+-		pm_runtime_put_noidle(rk_rng->dev);
+-		return ret;
+-	}
+-
+ 	/* enable osc_ring to get entropy, sample period is set as 100 */
+ 	reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
+ 	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
+@@ -135,10 +192,12 @@ static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+ 
+ 	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
+ 
+-	ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl,
+-				 !(reg_ctrl & CRYPTO_V1_RNG_START),
+-				 ROCKCHIP_POLL_PERIOD_US,
+-				 ROCKCHIP_POLL_TIMEOUT_US);
++	ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
++				!(reg_ctrl & CRYPTO_V1_RNG_START),
++				ROCKCHIP_POLL_PERIOD_US,
++				ROCKCHIP_POLL_TIMEOUT_US, false,
++				rk_rng, CRYPTO_V1_CTRL);
++
+ 	if (ret < 0)
+ 		goto out;
+ 
+@@ -151,24 +210,15 @@ static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+ 	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
+ 		      CRYPTO_V1_CTRL);
+ 
+-	pm_runtime_mark_last_busy(rk_rng->dev);
+-	pm_runtime_put_sync_autosuspend(rk_rng->dev);
+-
+ 	return ret;
+ }
+ 
+-static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++static int rk_crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+ {
+ 	int ret = 0;
+ 	u32 reg_ctrl = 0;
+ 	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+ 
+-	ret = pm_runtime_get_sync(rk_rng->dev);
+-	if (ret < 0) {
+-		pm_runtime_put_noidle(rk_rng->dev);
+-		return ret;
+-	}
+-
+ 	/* enable osc_ring to get entropy, sample period is set as 100 */
+ 	rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
+ 
+@@ -178,12 +228,13 @@ static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+ 	reg_ctrl |= CRYPTO_V2_RNG_START;
+ 
+ 	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
+-			CRYPTO_V2_RNG_CTL);
++		      CRYPTO_V2_RNG_CTL);
+ 
+-	ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
+-				 !(reg_ctrl & CRYPTO_V2_RNG_START),
+-				 ROCKCHIP_POLL_PERIOD_US,
+-				 ROCKCHIP_POLL_TIMEOUT_US);
++	ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
++				!(reg_ctrl & CRYPTO_V2_RNG_START),
++				ROCKCHIP_POLL_PERIOD_US,
++				ROCKCHIP_POLL_TIMEOUT_US, false,
++				rk_rng, CRYPTO_V2_RNG_CTL);
+ 	if (ret < 0)
+ 		goto out;
+ 
+@@ -195,32 +246,141 @@ static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+ 	/* close TRNG */
+ 	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
+ 
++	return ret;
++}
++
++static int rk_trng_v1_init(struct hwrng *rng)
++{
++	int ret;
++	uint32_t auto_reseed_cnt = 1000;
++	uint32_t reg_ctrl, status, version;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	ret = pm_runtime_get_sync(rk_rng->dev);
++	if (ret < 0) {
++		pm_runtime_put_noidle(rk_rng->dev);
++		return ret;
++	}
++
++	version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
++	if (version != TRNG_v1_VERSION_CODE) {
++		dev_err(rk_rng->dev,
++			"wrong trng version, expected = %08x, actual = %08x\n",
++			TRNG_V1_VERSION, version);
++		ret = -EFAULT;
++		goto exit;
++	}
++
++	status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
++
++	/* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
++	if (!(status & TRNG_V1_STAT_SEEDED) ||
++	    (status & TRNG_V1_STAT_GENERATING) ||
++	    (status & TRNG_V1_STAT_RESEEDING)) {
++		uint32_t mask = TRNG_V1_STAT_SEEDED |
++				TRNG_V1_STAT_GENERATING |
++				TRNG_V1_STAT_RESEEDING;
++
++		udelay(10);
++
++		/* wait for GENERATING and RESEEDING flag to clear */
++		read_poll_timeout(rk_rng_readl, reg_ctrl,
++				  (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
++				  ROCKCHIP_POLL_PERIOD_US,
++				  ROCKCHIP_POLL_TIMEOUT_US, false,
++				  rk_rng, TRNG_V1_STAT);
++	}
++
++	/* clear ISTAT flag because trng may auto reseeding when power on */
++	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
++	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
++
++	/* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
++	rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
++
++	ret = 0;
++exit:
+ 	pm_runtime_mark_last_busy(rk_rng->dev);
+ 	pm_runtime_put_sync_autosuspend(rk_rng->dev);
+ 
+ 	return ret;
+ }
+ 
+-static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
+-	.clks_num = ARRAY_SIZE(rk_rng_v1_clks),
+-	.clks = rk_rng_v1_clks,
+-	.rk_rng_read = rk_rng_v1_read,
++static int rk_trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	int ret = 0;
++	u32 reg_ctrl = 0;
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++	/* clear ISTAT anyway */
++	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
++	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
++
++	/* generate 256bit random */
++	rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
++	rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
++
++	/*
++	 * Generate2 56 bit random data will cost 1024 clock cycles.
++	 * Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
++	 */
++	udelay(10);
++	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
++	if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
++		/* wait RAND_RDY triggered */
++		ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
++					(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
++					ROCKCHIP_POLL_PERIOD_US,
++					ROCKCHIP_POLL_TIMEOUT_US, false,
++					rk_rng, TRNG_V1_ISTAT);
++		if (ret < 0)
++			goto out;
++	}
++
++	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
++
++	rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
++
++	/* clear all status flag */
++	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
++out:
++	/* close TRNG */
++	rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
++
++	return ret;
++}
++
++static const struct rk_rng_soc_data rk_crypto_v1_soc_data = {
++	.default_offset = 0,
++
++	.rk_rng_read = rk_crypto_v1_read,
+ };
+ 
+-static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
+-	.clks_num = ARRAY_SIZE(rk_rng_v2_clks),
+-	.clks = rk_rng_v2_clks,
+-	.rk_rng_read = rk_rng_v2_read,
++static const struct rk_rng_soc_data rk_crypto_v2_soc_data = {
++	.default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
++
++	.rk_rng_read = rk_crypto_v2_read,
++};
++
++static const struct rk_rng_soc_data rk_trng_v1_soc_data = {
++	.default_offset = 0,
++
++	.rk_rng_init = rk_trng_v1_init,
++	.rk_rng_read = rk_trng_v1_read,
+ };
+ 
+ static const struct of_device_id rk_rng_dt_match[] = {
+ 	{
+ 		.compatible = "rockchip,cryptov1-rng",
+-		.data = (void *)&rk_rng_v1_soc_data,
++		.data = (void *)&rk_crypto_v1_soc_data,
+ 	},
+ 	{
+ 		.compatible = "rockchip,cryptov2-rng",
+-		.data = (void *)&rk_rng_v2_soc_data,
++		.data = (void *)&rk_crypto_v2_soc_data,
++	},
++	{
++		.compatible = "rockchip,trngv1",
++		.data = (void *)&rk_trng_v1_soc_data,
+ 	},
+ 	{ },
+ };
+@@ -229,12 +389,13 @@ MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
+ 
+ static int rk_rng_probe(struct platform_device *pdev)
+ {
+-	int i;
+ 	int ret;
+ 	struct rk_rng *rk_rng;
+ 	struct device_node *np = pdev->dev.of_node;
+ 	const struct of_device_id *match;
++	resource_size_t map_size;
+ 
++	dev_dbg(&pdev->dev, "probing...\n");
+ 	rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
+ 	if (!rk_rng)
+ 		return -ENOMEM;
+@@ -248,33 +409,37 @@ static int rk_rng_probe(struct platform_device *pdev)
+ 	rk_rng->rng.init    = rk_rng_init;
+ 	rk_rng->rng.cleanup = rk_rng_cleanup,
+ #endif
+-	rk_rng->rng.read    = rk_rng->soc_data->rk_rng_read;
+-	rk_rng->rng.quality = 1024;
+-
+-	rk_rng->clk_bulks =
+-		devm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) *
+-			     rk_rng->soc_data->clks_num, GFP_KERNEL);
++	rk_rng->rng.read    = rk_rng_read;
++	rk_rng->rng.quality = 999;
+ 
+-	rk_rng->clk_num = rk_rng->soc_data->clks_num;
+-
+-	for (i = 0; i < rk_rng->soc_data->clks_num; i++)
+-		rk_rng->clk_bulks[i].id = rk_rng->soc_data->clks[i];
+-
+-	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
++	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
+ 	if (IS_ERR(rk_rng->mem))
+ 		return PTR_ERR(rk_rng->mem);
+ 
+-	ret = devm_clk_bulk_get(&pdev->dev, rk_rng->clk_num,
+-				rk_rng->clk_bulks);
+-	if (ret) {
++	/* compatible with crypto v2 module */
++	/*
++	 * With old dtsi configurations, the RNG base was equal to the crypto
++	 * base, so both drivers could not be enabled at the same time.
++	 * RNG base = CRYPTO base + RNG offset
++	 * (Since RK356X, RNG module is no longer belongs to CRYPTO module)
++	 *
++	 * With new dtsi configurations, CRYPTO regs is divided into two parts
++	 * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
++	 * RNG driver and CRYPTO driver could be enabled at the same time.
++	 */
++	if (map_size > rk_rng->soc_data->default_offset)
++		rk_rng->mem += rk_rng->soc_data->default_offset;
++
++	rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
++	if (rk_rng->clk_num < 0) {
+ 		dev_err(&pdev->dev, "failed to get clks property\n");
+-		return ret;
++		return -ENODEV;
+ 	}
+ 
+ 	platform_set_drvdata(pdev, rk_rng);
+ 
+ 	pm_runtime_set_autosuspend_delay(&pdev->dev,
+-					ROCKCHIP_AUTOSUSPEND_DELAY);
++					 ROCKCHIP_AUTOSUSPEND_DELAY);
+ 	pm_runtime_use_autosuspend(&pdev->dev);
+ 	pm_runtime_enable(&pdev->dev);
+ 
+@@ -284,6 +449,10 @@ static int rk_rng_probe(struct platform_device *pdev)
+ 		pm_runtime_disable(&pdev->dev);
+ 	}
+ 
++	/* for some platform need hardware operation when probe */
++	if (rk_rng->soc_data->rk_rng_init)
++		ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
++
+ 	return ret;
+ }
+ 
+@@ -306,10 +475,11 @@ static int rk_rng_runtime_resume(struct device *dev)
+ 
+ static const struct dev_pm_ops rk_rng_pm_ops = {
+ 	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
+-				rk_rng_runtime_resume, NULL)
++			   rk_rng_runtime_resume, NULL)
+ 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ 				pm_runtime_force_resume)
+ };
++
+ #endif
+ 
+ static struct platform_driver rk_rng_driver = {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-possibility-of-disabling-rk808-rtc.patch b/patch/kernel/archive/rockchip64-6.10/general-possibility-of-disabling-rk808-rtc.patch
new file mode 100644
index 000000000000..86229a2e7ac2
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-possibility-of-disabling-rk808-rtc.patch
@@ -0,0 +1,51 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Piotr Szczepanik <piter75@gmail.com>
+Date: Sun, 24 Jan 2021 16:14:06 +0100
+Subject: add possibility of disabling rk808-rtc
+
+To disable rk808-rtc driver from loading for specific board
+add the following stanza to rk808 node in device tree:
+
+	rtc {
+		compatible = "rk808-rtc";
+		status = "disabled";
+	}
+
+This is needed for roc-rk3399-pc plus (a.k.a. Station P1).
+Without the change rk808's rtc is initialised and used for time keeping
+although there is another rtc (hym8563) that should be actually used.
+
+Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
+---
+ drivers/mfd/mfd-core.c   | 2 +-
+ drivers/mfd/rk8xx-core.c | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
+index 0ed7c0d7784e..528917b236f9 100644
+--- a/drivers/mfd/mfd-core.c
++++ b/drivers/mfd/mfd-core.c
+@@ -202,7 +202,7 @@ static int mfd_add_device(struct device *parent, int id,
+ 		}
+ 
+ 		if (!pdev->dev.of_node)
+-			pr_warn("%s: Failed to locate of_node [id: %d]\n",
++			pr_debug("%s: Failed to locate of_node [id: %d]\n",
+ 				cell->name, platform_id);
+ 	}
+ 
+diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c
+index 11a831e92da8..9ec56d4abcfa 100644
+--- a/drivers/mfd/rk8xx-core.c
++++ b/drivers/mfd/rk8xx-core.c
+@@ -120,6 +120,7 @@ static const struct mfd_cell rk818s[] = {
+ 	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+ 	{
+ 		.name = "rk808-rtc",
++		.of_compatible = "rk808-rtc",
+ 		.num_resources = ARRAY_SIZE(rtc_resources),
+ 		.resources = rtc_resources,
+ 		.id = PLATFORM_DEVID_NONE,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-rk3328-dtsi-trb-ent-quirk.patch b/patch/kernel/archive/rockchip64-6.10/general-rk3328-dtsi-trb-ent-quirk.patch
new file mode 100644
index 000000000000..7a103ed1a3f2
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-rk3328-dtsi-trb-ent-quirk.patch
@@ -0,0 +1,61 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: schwar3kat <61094841+schwar3kat@users.noreply.github.com>
+Date: Sat, 7 May 2022 15:51:38 +0200
+Subject: [ARCHEOLOGY] Enable rockchip64: XHCI HCD USB TRB ENT quirk for RK3328
+ (#3763)
+
+> X-Git-Archeology: > recovered message: > This resolves a bug that affects r8153b USB network interface causing the RX interface to hang on load.
+> X-Git-Archeology: > recovered message: > On some xHCI controllers (e.g. Rockchip RK3399/RK3328/RK1808),
+> X-Git-Archeology: > recovered message: > they need to enable the ENT flag in the TRB data structure
+> X-Git-Archeology: > recovered message: > to force xHC to prefetch the next TRB of a TD.
+> X-Git-Archeology: > recovered message: > The quirk patch is already applied to dwc3 xhci usb on rockchip64.
+> X-Git-Archeology: > recovered message: > Enable the quirk on RK3328 through device tree node properties in rk3328.dtsi
+> X-Git-Archeology: - Revision 5e477fd42c734794edc13efd474ad1099d449446: https://github.com/armbian/build/commit/5e477fd42c734794edc13efd474ad1099d449446
+> X-Git-Archeology:   Date: Sat, 07 May 2022 15:51:38 +0200
+> X-Git-Archeology:   From: schwar3kat <61094841+schwar3kat@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Enable rockchip64: XHCI HCD USB TRB ENT quirk for RK3328 (#3763)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 4e30c5279ac6..303680413ed9 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -1030,6 +1030,7 @@ usbdrd3: usb@ff600000 {
+ 		snps,dis-del-phy-power-chg-quirk;
+ 		snps,dis_enblslpm_quirk;
+ 		snps,dis-tx-ipgap-linecheck-quirk;
++        snps,xhci-trb-ent-quirk;
+ 		snps,dis-u2-freeclk-exists-quirk;
+ 		snps,dis_u2_susphy_quirk;
+ 		snps,dis_u3_susphy_quirk;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-rk808-configurable-switch-voltage-steps.patch b/patch/kernel/archive/rockchip64-6.10/general-rk808-configurable-switch-voltage-steps.patch
new file mode 100644
index 000000000000..40dc792d063d
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-rk808-configurable-switch-voltage-steps.patch
@@ -0,0 +1,104 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Piotr Szczepanik <piter75@gmail.com>
+Date: Tue, 2 Mar 2021 21:07:22 +0100
+Subject: allows to change the way that BUCK1 and BUCK2 of rk808 PMIC
+
+This patch allows to change the way that BUCK1 and BUCK2 of rk808 PMIC set voltage.
+
+It allows to change the hardcoded max. 100mV per one change
+to any multiple of 12.5mV while keeping the 100mV default.
+
+It was observed that making the steps smaller (eg. 50mV = 4 * 12.5mV)
+makes the NanoPi M4V2 running stable.
+
+One can configure the max number of steps per single change using
+the "max-buck-steps-per-change" property of rk808 node in device tree.
+
+Below example ensures that voltage is not changed in jumps larger than 50mV:
+
+&rk808 {
+	max-buck-steps-per-change = <4>;
+}
+
+Be aware that changing this parameter affects the time taken to switch between
+OPPs of LiTTLE cores of rk3399.
+
+For overclocked LiTTLE cores with base 408MHz @ 0.825V
+and max. 1.5GHz @ 1.2V it will take 7 steps of 50mV (at least 65uS each - caused by i2c),
+the final 25mV step and 1uS to settle: 7 x 65uS + 1uS = 456uS.
+
+With default setting it would be 3 steps of 100mV (at least 65uS each - caused by i2c),
+the final 75mV step and 1uS to settle: 3 x 65uS + 1uS = 196uS.
+
+- rpardini: fix 'client_dev' -> 'dev' (for '->of_node') for 6.5.y
+
+Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
+Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
+---
+ drivers/regulator/rk808-regulator.c | 17 +++++++---
+ 1 file changed, 13 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c
+index 867a2cf243f6..52575e71ce33 100644
+--- a/drivers/regulator/rk808-regulator.c
++++ b/drivers/regulator/rk808-regulator.c
+@@ -204,6 +204,7 @@ struct rk8xx_register_bit {
+ 
+ struct rk808_regulator_data {
+ 	struct gpio_desc *dvs_gpio[2];
++	unsigned max_buck_steps_per_change;
+ };
+ 
+ static const struct linear_range rk808_ldo3_voltage_ranges[] = {
+@@ -416,7 +417,8 @@ static int rk808_buck1_2_get_voltage_sel_regmap(struct regulator_dev *rdev)
+ }
+ 
+ static int rk808_buck1_2_i2c_set_voltage_sel(struct regulator_dev *rdev,
+-					     unsigned sel)
++					     unsigned sel,
++					     int max_steps)
+ {
+ 	int ret, delta_sel;
+ 	unsigned int old_sel, tmp, val, mask = rdev->desc->vsel_mask;
+@@ -435,8 +437,8 @@ static int rk808_buck1_2_i2c_set_voltage_sel(struct regulator_dev *rdev,
+ 	 * the risk of overshoot. Put it into a multi-step, can effectively
+ 	 * avoid this problem, a step is 100mv here.
+ 	 */
+-	while (delta_sel > MAX_STEPS_ONE_TIME) {
+-		old_sel += MAX_STEPS_ONE_TIME;
++	while (delta_sel > max_steps) {
++		old_sel += max_steps;
+ 		val = old_sel << (ffs(mask) - 1);
+ 		val |= tmp;
+ 
+@@ -470,12 +472,13 @@ static int rk808_buck1_2_set_voltage_sel(struct regulator_dev *rdev,
+ 	struct rk808_regulator_data *pdata = rdev_get_drvdata(rdev);
+ 	int id = rdev_get_id(rdev);
+ 	struct gpio_desc *gpio = pdata->dvs_gpio[id];
++	int max_steps = pdata->max_buck_steps_per_change;
+ 	unsigned int reg = rdev->desc->vsel_reg;
+ 	unsigned old_sel;
+ 	int ret, gpio_level;
+ 
+ 	if (!gpio)
+-		return rk808_buck1_2_i2c_set_voltage_sel(rdev, sel);
++		return rk808_buck1_2_i2c_set_voltage_sel(rdev, sel, max_steps);
+ 
+ 	gpio_level = gpiod_get_value(gpio);
+ 	if (gpio_level == 0) {
+@@ -1657,6 +1660,12 @@ static int rk808_regulator_dt_parse_pdata(struct device *dev,
+ 				0 : tmp);
+ 	}
+ 
++	tmp = of_property_read_u32(dev->of_node, "max-buck-steps-per-change", &pdata->max_buck_steps_per_change);
++	if (tmp) {
++		pdata->max_buck_steps_per_change = MAX_STEPS_ONE_TIME;
++	}
++	dev_info(dev, "max buck steps per change: %d\n", pdata->max_buck_steps_per_change);
++
+ dt_parse_end:
+ 	of_node_put(np);
+ 	return ret;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-rockchip-overlays.patch b/patch/kernel/archive/rockchip64-6.10/general-rockchip-overlays.patch
new file mode 100644
index 000000000000..7c39c266c95c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-rockchip-overlays.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Ayotte <martinayotte@yahoo.ca>
+Date: Wed, 5 Dec 2018 15:00:44 -0500
+Subject: add overlays framework for rockchip (scripts/Makefile.lib only)
+
+- rpardini: real overlays are now bare in "overlay" directory and are handled
+  directly by the patching scripts. No more null-patching of overlays.
+---
+ scripts/Makefile.lib | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 9ea801a22569..3cde7d57e261 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -88,6 +88,9 @@ base-dtb-y := $(foreach m, $(multi-dtb-y), $(firstword $(call suffix-search, $m,
+ 
+ always-y			+= $(dtb-y)
+ 
++# Overlay targets
++extra-y				+= $(dtbo-y) $(scr-y) $(dtbotxt-y)
++
+ # Add subdir path
+ 
+ ifneq ($(obj),.)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-rt5651-add-mclk.patch b/patch/kernel/archive/rockchip64-6.10/general-rt5651-add-mclk.patch
new file mode 100644
index 000000000000..87e230ed24bb
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-rt5651-add-mclk.patch
@@ -0,0 +1,133 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Piotr Szczepanik <piter75@gmail.com>
+Date: Sun, 5 Apr 2020 18:15:06 +0200
+Subject: [ARCHEOLOGY] Fixed sound from rt5651 on OrangePi 4 (#1870)
+
+> X-Git-Archeology: - Revision e14a61c229db1216fedc397e351c4bed15df820e: https://github.com/armbian/build/commit/e14a61c229db1216fedc397e351c4bed15df820e
+> X-Git-Archeology:   Date: Sun, 05 Apr 2020 18:15:06 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Fixed sound from rt5651 on OrangePi 4 (#1870)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ sound/soc/codecs/rt5651.c | 16 ++++++++++
+ sound/soc/codecs/rt5651.h |  1 +
+ 2 files changed, 17 insertions(+)
+
+diff --git a/sound/soc/codecs/rt5651.c b/sound/soc/codecs/rt5651.c
+index 0cee4fd1c84b..90b08604e615 100644
+--- a/sound/soc/codecs/rt5651.c
++++ b/sound/soc/codecs/rt5651.c
+@@ -24,6 +24,7 @@
+ #include <sound/initval.h>
+ #include <sound/tlv.h>
+ #include <sound/jack.h>
++#include <linux/clk.h>
+ 
+ #include "rl6231.h"
+ #include "rt5651.h"
+@@ -1511,6 +1512,7 @@ static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
+ static int rt5651_set_bias_level(struct snd_soc_component *component,
+ 			enum snd_soc_bias_level level)
+ {
++	struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
+ 	switch (level) {
+ 	case SND_SOC_BIAS_PREPARE:
+ 		if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
+@@ -1518,6 +1520,13 @@ static int rt5651_set_bias_level(struct snd_soc_component *component,
+ 				snd_soc_component_update_bits(component, RT5651_D_MISC,
+ 						    0xc00, 0xc00);
+ 		}
++		if (!IS_ERR(rt5651->mclk)){
++			if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
++				clk_disable_unprepare(rt5651->mclk);
++			} else {
++				clk_prepare_enable(rt5651->mclk);
++			}
++		}
+ 		break;
+ 	case SND_SOC_BIAS_STANDBY:
+ 		if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
+@@ -2059,6 +2068,13 @@ static int rt5651_probe(struct snd_soc_component *component)
+ {
+ 	struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
+ 
++	/* Check if MCLK provided */
++	rt5651->mclk = devm_clk_get(component->dev, "mclk");
++	if (PTR_ERR(rt5651->mclk) == -EPROBE_DEFER){
++		dev_err(component->dev, "unable to get mclk\n");
++		return -EPROBE_DEFER;
++	}
++
+ 	rt5651->component = component;
+ 
+ 	snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
+diff --git a/sound/soc/codecs/rt5651.h b/sound/soc/codecs/rt5651.h
+index 20c33a3ece37..17524fa9fdfc 100644
+--- a/sound/soc/codecs/rt5651.h
++++ b/sound/soc/codecs/rt5651.h
+@@ -2097,6 +2097,7 @@ struct rt5651_priv {
+ 
+ 	int dmic_en;
+ 	bool hp_mute;
++	struct clk *mclk;
+ };
+ 
+ #endif /* __RT5651_H__ */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-v4l2-iep-driver.patch b/patch/kernel/archive/rockchip64-6.10/general-v4l2-iep-driver.patch
new file mode 100644
index 000000000000..370691b33a0c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-v4l2-iep-driver.patch
@@ -0,0 +1,1808 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo <paolo.sabatino@gmail.com>
+Date: Thu, 9 Sep 2021 22:59:12 +0200
+Subject: Rockchip IEP driver
+
+> X-Git-Archeology: - Revision 4425589e15c3b1593731703c379df0fa1b4432fb: https://github.com/armbian/build/commit/4425589e15c3b1593731703c379df0fa1b4432fb
+> X-Git-Archeology:   Date: Thu, 09 Sep 2021 22:59:12 +0200
+> X-Git-Archeology:   From: Paolo <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rk322x: bump edge kernel to 5.14, u-boot to 2021.07 (#3133)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision a1d044de8e0bb6ca504386bc31f5615a9d169067: https://github.com/armbian/build/commit/a1d044de8e0bb6ca504386bc31f5615a9d169067
+> X-Git-Archeology:   Date: Tue, 12 Oct 2021 15:59:01 +0200
+> X-Git-Archeology:   From: Paolo Sabatino <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rockchip: update support for edge kernel 5.14
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 682e4085ab8faa278db21a41ed23a6b12f8868ea: https://github.com/armbian/build/commit/682e4085ab8faa278db21a41ed23a6b12f8868ea
+> X-Git-Archeology:   Date: Thu, 21 Oct 2021 22:55:25 +0200
+> X-Git-Archeology:   From: Paolo <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64: add IEP driver (#3215)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ Documentation/devicetree/bindings/media/rockchip-iep.yaml |   73 +
+ arch/arm/boot/dts/rockchip/rk3288.dtsi                    |   13 +-
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi                  |   22 +
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi                  |   13 +
+ drivers/media/platform/rockchip/Kconfig                   |    1 +
+ drivers/media/platform/rockchip/Makefile                  |    1 +
+ drivers/media/platform/rockchip/iep/Kconfig               |   13 +
+ drivers/media/platform/rockchip/iep/Makefile              |    5 +
+ drivers/media/platform/rockchip/iep/iep-regs.h            |  291 +++
+ drivers/media/platform/rockchip/iep/iep.c                 | 1089 ++++++++++
+ drivers/media/platform/rockchip/iep/iep.h                 |  112 +
+ 11 files changed, 1632 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
+new file mode 100644
+index 000000000000..a9efcda13fc1
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
+@@ -0,0 +1,73 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/media/rockchip-iep.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip Image Enhancement Processor (IEP)
++
++description:
++    Rockchip IEP supports various image enhancement operations for YUV and RGB domains.
++    Deinterlacing, spatial and temporal sampling noise reduction are supported by the
++    YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in
++    the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for
++    both domains. Furthermore it supports converting RGB to YUV / YUV to RGB.
++
++maintainers:
++  - Heiko Stuebner <heiko@sntech.de>
++
++properties:
++  compatible:
++    oneOf:
++      - const: rockchip,rk3228-iep
++      - items:
++          - enum:
++              - rockchip,rk3288-iep
++              - rockchip,rk3328-iep
++              - rockchip,rk3368-iep
++              - rockchip,rk3399-iep
++          - const: rockchip,rk3228-iep
++
++  reg:
++    maxItems: 1
++
++  interrupts:
++    maxItems: 1
++
++  clocks:
++    maxItems: 2
++
++  clock-names:
++    items:
++      - const: axi
++      - const: ahb
++
++  power-domains:
++    maxItems: 1
++
++  iommus:
++    maxItems: 1
++
++required:
++  - compatible
++  - reg
++  - interrupts
++  - clocks
++  - clock-names
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/rk3228-cru.h>
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/power/rk3228-power.h>
++    iep: iep@20070000 {
++      compatible = "rockchip,rk3228-iep";
++      reg = <0x20070000 0x800>;
++      interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++      clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++      clock-names = "axi", "ahb";
++      iommus = <&iep_mmu>;
++      power-domains = <&power RK3228_PD_VIO>;
++    };
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index cb9cdaddffd4..54bf9ae3ab4b 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -984,14 +984,25 @@ crypto: crypto@ff8a0000 {
+ 		reset-names = "crypto-rst";
+ 	};
+ 
++	iep: iep@ff90000 {
++		compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep";
++		reg = <0x0 0xff900000 0x0 0x800>;
++		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "iep";
++		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++		clock-names = "axi", "ahb";
++		power-domains = <&power RK3288_PD_VIO>;
++		iommus = <&iep_mmu>;
++	};
++
+ 	iep_mmu: iommu@ff900800 {
+ 		compatible = "rockchip,iommu";
+ 		reg = <0x0 0xff900800 0x0 0x40>;
+ 		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ 		clock-names = "aclk", "iface";
++		power-domains = <&power RK3288_PD_VIO>;
+ 		#iommu-cells = <0>;
+-		status = "disabled";
+ 	};
+ 
+ 	isp_mmu: iommu@ff914000 {
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index e729e7a22b23..4e30c5279ac6 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -722,6 +722,28 @@ vop_mmu: iommu@ff373f00 {
+ 		status = "disabled";
+ 	};
+ 
++	iep: iep@ff3a0000 {
++		compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep";
++		reg = <0x0 0xff3a0000 0x0 0x800>;
++		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "iep";
++		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++		clock-names = "axi", "ahb";
++		power-domains = <&power RK3328_PD_VIDEO>;
++		iommus = <&iep_mmu>;
++	};
++
++	iep_mmu: iommu@ff3a0800 {
++		compatible = "rockchip,iommu";
++		reg = <0x0 0xff3a0800 0x0 0x40>;
++		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "iep_mmu";
++		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++		clock-names = "aclk", "iface";
++		power-domains = <&power RK3328_PD_VIDEO>;
++		#iommu-cells = <0>;
++	};
++
+ 	hdmi: hdmi@ff3c0000 {
+ 		compatible = "rockchip,rk3328-dw-hdmi";
+ 		reg = <0x0 0xff3c0000 0x0 0x20000>;
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 5bc2d4faeea6..8aa038f5657a 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -1404,12 +1404,25 @@ vdec_mmu: iommu@ff660480 {
+ 		#iommu-cells = <0>;
+ 	};
+ 
++
++	iep: iep@ff670000 {
++		compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep";
++		reg = <0x0 0xff670000 0x0 0x800>;
++		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "iep";
++		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
++		clock-names = "axi", "ahb";
++		power-domains = <&power RK3399_PD_IEP>;
++		iommus = <&iep_mmu>;
++	};
++
+ 	iep_mmu: iommu@ff670800 {
+ 		compatible = "rockchip,iommu";
+ 		reg = <0x0 0xff670800 0x0 0x40>;
+ 		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ 		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ 		clock-names = "aclk", "iface";
++		power-domains = <&power RK3399_PD_IEP>;
+ 		#iommu-cells = <0>;
+ 		status = "disabled";
+ 	};
+diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig
+index b41d3960c1b4..862590be7916 100644
+--- a/drivers/media/platform/rockchip/Kconfig
++++ b/drivers/media/platform/rockchip/Kconfig
+@@ -4,3 +4,4 @@ comment "Rockchip media platform drivers"
+ 
+ source "drivers/media/platform/rockchip/rga/Kconfig"
+ source "drivers/media/platform/rockchip/rkisp1/Kconfig"
++source "drivers/media/platform/rockchip/iep/Kconfig"
+diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile
+index 4f782b876ac9..be8015c6d9e4 100644
+--- a/drivers/media/platform/rockchip/Makefile
++++ b/drivers/media/platform/rockchip/Makefile
+@@ -1,3 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ obj-y += rga/
+ obj-y += rkisp1/
++obj-y += iep/
+diff --git a/drivers/media/platform/rockchip/iep/Kconfig b/drivers/media/platform/rockchip/iep/Kconfig
+new file mode 100644
+index 000000000000..e513fa7f45f2
+--- /dev/null
++++ b/drivers/media/platform/rockchip/iep/Kconfig
+@@ -0,0 +1,13 @@
++config VIDEO_ROCKCHIP_IEP
++	tristate "Rockchip Image Enhancement Processor"
++	depends on VIDEO_DEV && VIDEO_V4L2
++	depends on ARCH_ROCKCHIP || COMPILE_TEST
++	select VIDEOBUF2_DMA_CONTIG
++	select V4L2_MEM2MEM_DEV
++	help
++	  This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP)
++	  found in most Rockchip RK3xxx SoCs.
++	  Rockchip IEP supports various enhancement operations for RGB and YUV
++	  images. The driver currently implements YUV deinterlacing only.
++	  To compile this driver as a module, choose M here: the module
++	  will be called rockchip-iep
+diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile
+new file mode 100644
+index 000000000000..5c89b3277469
+--- /dev/null
++++ b/drivers/media/platform/rockchip/iep/Makefile
+@@ -0,0 +1,5 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++rockchip-iep-objs := iep.o
++
++obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o
+diff --git a/drivers/media/platform/rockchip/iep/iep-regs.h b/drivers/media/platform/rockchip/iep/iep-regs.h
+new file mode 100644
+index 000000000000..a68685ef3604
+--- /dev/null
++++ b/drivers/media/platform/rockchip/iep/iep-regs.h
+@@ -0,0 +1,291 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Rockchip Image Enhancement Processor (IEP) driver
++ *
++ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
++ *
++ */
++
++#ifndef __IEP_REGS_H__
++#define __IEP_REGS_H__
++
++/* IEP Registers addresses */
++#define IEP_CONFIG0			0x000 /* Configuration register0 */
++#define IEP_VOP_DIRECT_PATH			BIT(0)
++#define IEP_DEIN_HIGH_FREQ_SHFT			1
++#define IEP_DEIN_HIGH_FREQ_MASK			(0x7f << IEP_DEIN_HIGH_FREQ_SHFT)
++#define IEP_DEIN_MODE_SHFT			8
++#define IEP_DEIN_MODE_MASK			(7 << IEP_DEIN_MODE_SHFT)
++#define IEP_DEIN_HIGH_FREQ_EN			BIT(11)
++#define IEP_DEIN_EDGE_INTPOL_EN			BIT(12)
++#define IEP_YUV_DENOISE_EN			BIT(13)
++#define IEP_YUV_ENHNC_EN			BIT(14)
++#define IEP_DEIN_EDGE_INTPOL_SMTH_EN		BIT(15)
++#define IEP_RGB_CLR_ENHNC_EN			BIT(16)
++#define IEP_RGB_CNTRST_ENHNC_EN			BIT(17)
++#define IEP_RGB_ENHNC_MODE_BYPASS		(0 << 18)
++#define IEP_RGB_ENHNC_MODE_DNS			BIT(18)
++#define IEP_RGB_ENHNC_MODE_DTL			(2 << 18)
++#define IEP_RGB_ENHNC_MODE_EDG			(3 << 18)
++#define IEP_RGB_ENHNC_MODE_MASK			(3 << 18)
++#define IEP_RGB_CNTRST_ENHNC_DDE_FRST		BIT(20)
++#define IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT	21
++#define IEP_DEIN_EDGE_INTPOL_RADIUS_MASK	(3 << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT)
++#define IEP_DEIN_EDGE_INTPOL_SELECT		BIT(23)
++
++#define IEP_CONFIG1			0x004 /* Configuration register1 */
++#define IEP_SRC_FMT_SHFT			0
++#define IEP_SRC_FMT_MASK			(3 << IEP_SRC_FMT_SHFT)
++#define IEP_SRC_RGB_SWP_SHFT			2
++#define IEP_SRC_RGB_SWP_MASK			(2 << IEP_SRC_RGB_SWP_SHFT)
++#define IEP_SRC_YUV_SWP_SHFT			4
++#define IEP_SRC_YUV_SWP_MASK			(3 << IEP_SRC_YUV_SWP_SHFT)
++#define IEP_DST_FMT_SHFT			8
++#define IEP_DST_FMT_MASK			(3 << IEP_DST_FMT_SHFT)
++#define IEP_DST_RGB_SWP_SHFT			10
++#define IEP_DST_RGB_SWP_MASK			(2 << IEP_DST_RGB_SWP_SHFT)
++#define IEP_DST_YUV_SWP_SHFT			12
++#define IEP_DST_YUV_SWP_MASK			(3 << IEP_DST_YUV_SWP_SHFT)
++#define IEP_DTH_UP_EN				BIT(14)
++#define IEP_DTH_DWN_EN				BIT(15)
++#define IEP_YUV2RGB_COE_BT601_1			(0 << 16)
++#define IEP_YUV2RGB_COE_BT601_F			BIT(16)
++#define IEP_YUV2RGB_COE_BT709_1			(2 << 16)
++#define IEP_YUV2RGB_COE_BT709_F			(3 << 16)
++#define IEP_YUV2RGB_COE_MASK			(3 << 16)
++#define IEP_RGB2YUV_COE_BT601_1			(0 << 18)
++#define IEP_RGB2YUV_COE_BT601_F			BIT(18)
++#define IEP_RGB2YUV_COE_BT709_1			(2 << 18)
++#define IEP_RGB2YUV_COE_BT709_F			(3 << 18)
++#define IEP_RGB2YUV_COE_MASK			(3 << 18)
++#define IEP_YUV2RGB_EN				BIT(20)
++#define IEP_RGB2YUV_EN				BIT(21)
++#define IEP_YUV2RGB_CLIP_EN			BIT(22)
++#define IEP_RGB2YUV_CLIP_EN			BIT(23)
++#define IEP_GLB_ALPHA_SHFT			24
++#define IEP_GLB_ALPHA_MASK			(0x7f << IEP_GLB_ALPHA_SHFT)
++
++#define IEP_STATUS			0x008 /* Status register */
++#define IEP_STATUS_YUV_DNS			BIT(0)
++#define IEP_STATUS_SCL				BIT(1)
++#define IEP_STATUS_DIL				BIT(2)
++#define IEP_STATUS_DDE				BIT(3)
++#define IEP_STATUS_DMA_WR_YUV			BIT(4)
++#define IEP_STATUS_DMA_RE_YUV			BIT(5)
++#define IEP_STATUS_DMA_WR_RGB			BIT(6)
++#define IEP_STATUS_DMA_RE_RGB			BIT(7)
++#define IEP_STATUS_VOP_DIRECT_PATH		BIT(8)
++#define IEP_STATUS_DMA_IA_WR_YUV		BIT(16)
++#define IEP_STATUS_DMA_IA_RE_YUV		BIT(17)
++#define IEP_STATUS_DMA_IA_WR_RGB		BIT(18)
++#define IEP_STATUS_DMA_IA_RE_RGB		BIT(19)
++
++#define IEP_INT				0x00c /* Interrupt register*/
++#define IEP_INT_FRAME_DONE			BIT(0) /* Frame process done interrupt */
++#define IEP_INT_FRAME_DONE_EN			BIT(8) /* Frame process done interrupt enable */
++#define IEP_INT_FRAME_DONE_CLR			BIT(16) /* Frame process done interrupt clear */
++
++#define IEP_FRM_START			0x010 /* Frame start */
++#define IEP_SRST			0x014 /* Soft reset */
++#define IEP_CONFIG_DONE			0x018 /* Configuration done */
++#define IEP_FRM_CNT			0x01c /* Frame counter */
++
++#define IEP_VIR_IMG_WIDTH		0x020 /* Image virtual width */
++#define IEP_IMG_SCL_FCT			0x024 /* Scaling factor */
++#define IEP_SRC_IMG_SIZE		0x028 /* src image width/height */
++#define IEP_DST_IMG_SIZE		0x02c /* dst image width/height */
++#define IEP_DST_IMG_WIDTH_TILE0		0x030 /* dst image tile0 width */
++#define IEP_DST_IMG_WIDTH_TILE1		0x034 /* dst image tile1 width */
++#define IEP_DST_IMG_WIDTH_TILE2		0x038 /* dst image tile2 width */
++#define IEP_DST_IMG_WIDTH_TILE3		0x03c /* dst image tile3 width */
++
++#define IEP_ENH_YUV_CNFG_0		0x040 /* Brightness, contrast, saturation adjustment */
++#define IEP_YUV_BRIGHTNESS_SHFT			0
++#define IEP_YUV_BRIGHTNESS_MASK			(0x3f << IEP_YUV_BRIGHTNESS_SHFT)
++#define IEP_YUV_CONTRAST_SHFT			8
++#define IEP_YUV_CONTRAST_MASK			(0xff << IEP_YUV_CONTRAST_SHFT)
++#define IEP_YUV_SATURATION_SHFT			16
++#define IEP_YUV_SATURATION_MASK			(0x1ff << IEP_YUV_SATURATION_SHFT)
++
++#define IEP_ENH_YUV_CNFG_1		0x044 /* Hue configuration */
++#define IEP_YUV_COS_HUE_SHFT			0
++#define IEP_YUV_COS_HUE_MASK			(0xff << IEP_YUV_COS_HUE_SHFT)
++#define IEP_YUV_SIN_HUE_SHFT			8
++#define IEP_YUV_SIN_HUE_MASK			(0xff << IEP_YUV_SIN_HUE_SHFT)
++
++#define IEP_ENH_YUV_CNFG_2		0x048 /* Color bar configuration */
++#define IEP_YUV_COLOR_BAR_Y_SHFT		0
++#define IEP_YUV_COLOR_BAR_Y_MASK		(0xff << IEP_YUV_COLOR_BAR_Y_SHFT)
++#define IEP_YUV_COLOR_BAR_U_SHFT		8
++#define IEP_YUV_COLOR_BAR_U_MASK		(0xff << IEP_YUV_COLOR_BAR_U_SHFT)
++#define IEP_YUV_COLOR_BAR_V_SHFT		16
++#define IEP_YUV_COLOR_BAR_V_MASK		(0xff << IEP_YUV_COLOR_BAR_V_SHFT)
++#define IEP_YUV_VIDEO_MODE_SHFT			24
++#define IEP_YUV_VIDEO_MODE_MASK			(3 << IEP_YUV_VIDEO_MODE_SHFT)
++
++#define IEP_ENH_RGB_CNFG		0x04c /* RGB enhancement configuration */
++#define IEP_ENH_RGB_C_COE		0x050 /* RGB color enhancement coefficient */
++
++#define IEP_RAW_CONFIG0			0x058 /* Raw configuration register0 */
++#define IEP_RAW_CONFIG1			0x05c /* Raw configuration register1 */
++#define IEP_RAW_VIR_IMG_WIDTH		0x060 /* Raw image virtual width */
++#define IEP_RAW_IMG_SCL_FCT		0x064 /* Raw scaling factor */
++#define IEP_RAW_SRC_IMG_SIZE		0x068 /* Raw src image width/height  */
++#define IEP_RAW_DST_IMG_SIZE		0x06c /* Raw src image width/height  */
++#define IEP_RAW_ENH_YUV_CNFG_0		0x070 /* Raw brightness,contrast,saturation adjustment */
++#define IEP_RAW_ENH_YUV_CNFG_1		0x074 /* Raw hue configuration */
++#define IEP_RAW_ENH_YUV_CNFG_2		0x078 /* Raw color bar configuration */
++#define IEP_RAW_ENH_RGB_CNFG		0x07c /* Raw RGB enhancement configuration */
++
++#define IEP_SRC_ADDR_Y_RGB		0x080 /* Start addr. of src image 0 (Y/RGB) */
++#define IEP_SRC_ADDR_CBCR		0x084 /* Start addr. of src image 0 (Cb/Cr) */
++#define IEP_SRC_ADDR_CR			0x088 /* Start addr. of src image 0 (Cr) */
++#define IEP_SRC_ADDR_Y1			0x08c /* Start addr. of src image 1 (Y) */
++#define IEP_SRC_ADDR_CBCR1		0x090 /* Start addr. of src image 1 (Cb/Cr) */
++#define IEP_SRC_ADDR_CR1		0x094 /* Start addr. of src image 1 (Cr) */
++#define IEP_SRC_ADDR_Y_ITEMP		0x098 /* Start addr. of src image(Y int part) */
++#define IEP_SRC_ADDR_CBCR_ITEMP		0x09c /* Start addr. of src image(CBCR int part) */
++#define IEP_SRC_ADDR_CR_ITEMP		0x0a0 /* Start addr. of src image(CR int part) */
++#define IEP_SRC_ADDR_Y_FTEMP		0x0a4 /* Start addr. of src image(Y frac part) */
++#define IEP_SRC_ADDR_CBCR_FTEMP		0x0a8 /* Start addr. of src image(CBCR frac part) */
++#define IEP_SRC_ADDR_CR_FTEMP		0x0ac /* Start addr. of src image(CR frac part) */
++
++#define IEP_DST_ADDR_Y_RGB		0x0b0 /* Start addr. of dst image 0 (Y/RGB) */
++#define IEP_DST_ADDR_CBCR		0x0b4 /* Start addr. of dst image 0 (Cb/Cr) */
++#define IEP_DST_ADDR_CR			0x0b8 /* Start addr. of dst image 0 (Cr) */
++#define IEP_DST_ADDR_Y1			0x0bc /* Start addr. of dst image 1 (Y) */
++#define IEP_DST_ADDR_CBCR1		0x0c0 /* Start addr. of dst image 1 (Cb/Cr) */
++#define IEP_DST_ADDR_CR1		0x0c4 /* Start addr. of dst image 1 (Cr) */
++#define IEP_DST_ADDR_Y_ITEMP		0x0c8 /* Start addr. of dst image(Y int part) */
++#define IEP_DST_ADDR_CBCR_ITEMP		0x0cc /* Start addr. of dst image(CBCR int part)*/
++#define IEP_DST_ADDR_CR_ITEMP		0x0d0 /* Start addr. of dst image(CR int part) */
++#define IEP_DST_ADDR_Y_FTEMP		0x0d4 /* Start addr. of dst image(Y frac part) */
++#define IEP_DST_ADDR_CBCR_FTEMP		0x0d8 /* Start addr. of dst image(CBCR frac part) */
++#define IEP_DST_ADDR_CR_FTEMP		0x0dc /* Start addr. of dst image(CR frac part)*/
++
++#define IEP_DEIN_MTN_TAB0		0x0e0 /* Deinterlace motion table0 */
++#define IEP_DEIN_MTN_TAB1		0x0e4 /* Deinterlace motion table1 */
++#define IEP_DEIN_MTN_TAB2		0x0e8 /* Deinterlace motion table2 */
++#define IEP_DEIN_MTN_TAB3		0x0ec /* Deinterlace motion table3 */
++#define IEP_DEIN_MTN_TAB4		0x0f0 /* Deinterlace motion table4 */
++#define IEP_DEIN_MTN_TAB5		0x0f4 /* Deinterlace motion table5 */
++#define IEP_DEIN_MTN_TAB6		0x0f8 /* Deinterlace motion table6 */
++#define IEP_DEIN_MTN_TAB7		0x0fc /* Deinterlace motion table7 */
++
++#define IEP_ENH_CG_TAB			0x100 /* Contrast and gamma enhancement table */
++#define IEP_ENH_DDE_COE0		0x400 /* Denoise,detail and edge enhancement coefficient */
++#define IEP_ENH_DDE_COE1		0x500 /* Denoise,detail and edge enhancement coefficient1 */
++
++#define IEP_INT_MASK			(IEP_INT_FRAME_DONE)
++
++/* IEP colorformats */
++#define IEP_COLOR_FMT_XRGB		0U
++#define IEP_COLOR_FMT_RGB565		1U
++#define IEP_COLOR_FMT_YUV422		2U
++#define IEP_COLOR_FMT_YUV420		3U
++
++/* IEP YUV color swaps */
++#define IEP_YUV_SWP_SP_UV		0U
++#define IEP_YUV_SWP_SP_VU		1U
++#define IEP_YUV_SWP_P			2U
++
++/* IEP XRGB color swaps */
++#define XRGB_SWP_XRGB			0U
++#define XRGB_SWP_XBGR			1U
++#define XRGB_SWP_BGRX			2U
++
++/* IEP RGB565 color swaps */
++#define RGB565_SWP_RGB			0U
++#define RGB565_SWP_BGR			1U
++
++#define FMT_IS_YUV(fmt) (fmt == IEP_COLOR_FMT_XRGB || fmt == IEP_COLOR_FMT_RGB565 ? 0 : 1)
++
++#define IEP_IMG_SIZE(w, h) (((w - 1) & 0x1fff) << 0 | \
++			    ((h - 1) & 0x1fff) << 16)
++
++#define IEP_VIR_WIDTH(src_w, dst_w) (((src_w / 4) & 0x1fff) << 0 | \
++				     ((dst_w / 4) & 0x1fff) << 16)
++
++#define IEP_Y_STRIDE(w, h) (w * h)
++#define IEP_UV_STRIDE(w, h, fac) (w * h + w * h / fac)
++
++#define IEP_SRC_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_MASK : IEP_SRC_RGB_SWP_MASK)
++#define IEP_DST_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_MASK : IEP_DST_RGB_SWP_MASK)
++
++#define IEP_SRC_FMT(f, swp) (f << IEP_SRC_FMT_SHFT | \
++			     (swp << (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_SHFT : IEP_SRC_RGB_SWP_SHFT)))
++#define IEP_DST_FMT(f, swp) (f << IEP_DST_FMT_SHFT | \
++			     (swp << (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_SHFT : IEP_DST_RGB_SWP_SHFT)))
++
++/* IEP DEINTERLACE MODES */
++#define IEP_DEIN_MODE_YUV		0U
++#define IEP_DEIN_MODE_I4O2		1U
++#define IEP_DEIN_MODE_I4O1B		2U
++#define IEP_DEIN_MODE_I4O1T		3U
++#define IEP_DEIN_MODE_I2O1B		4U
++#define IEP_DEIN_MODE_I2O1T		5U
++#define IEP_DEIN_MODE_BYPASS		6U
++
++#define IEP_DEIN_IN_FIELDS_2		2U
++#define IEP_DEIN_IN_FIELDS_4		4U
++
++#define IEP_DEIN_OUT_FRAMES_1		1U
++#define IEP_DEIN_OUT_FRAMES_2		2U
++
++/* values taken from BSP driver */
++static const u32 default_dein_motion_tbl[][2] = {
++	{ IEP_DEIN_MTN_TAB0, 0x40404040 },
++	{ IEP_DEIN_MTN_TAB1, 0x3c3e3f3f },
++	{ IEP_DEIN_MTN_TAB2, 0x3336393b },
++	{ IEP_DEIN_MTN_TAB3, 0x272a2d31 },
++	{ IEP_DEIN_MTN_TAB4, 0x181c2023 },
++	{ IEP_DEIN_MTN_TAB5, 0x0c0e1215 },
++	{ IEP_DEIN_MTN_TAB6, 0x03040609 },
++	{ IEP_DEIN_MTN_TAB7, 0x00000001 },
++
++};
++
++#define IEP_DEIN_IN_IMG0_Y(bff) (bff ? IEP_SRC_ADDR_Y_RGB : IEP_SRC_ADDR_Y1)
++#define IEP_DEIN_IN_IMG0_CBCR(bff) (bff ? IEP_SRC_ADDR_CBCR : IEP_SRC_ADDR_CBCR1)
++#define IEP_DEIN_IN_IMG0_CR(bff) (bff ? IEP_SRC_ADDR_CR : IEP_SRC_ADDR_CR1)
++#define IEP_DEIN_IN_IMG1_Y(bff) (IEP_DEIN_IN_IMG0_Y(!bff))
++#define IEP_DEIN_IN_IMG1_CBCR(bff) (IEP_DEIN_IN_IMG0_CBCR(!bff))
++#define IEP_DEIN_IN_IMG1_CR(bff) (IEP_DEIN_IN_IMG0_CR(!bff))
++
++#define IEP_DEIN_OUT_IMG0_Y(bff) (bff ? IEP_DST_ADDR_Y1 : IEP_DST_ADDR_Y_RGB)
++#define IEP_DEIN_OUT_IMG0_CBCR(bff) (bff ? IEP_DST_ADDR_CBCR1 : IEP_DST_ADDR_CBCR)
++#define IEP_DEIN_OUT_IMG0_CR(bff) (bff ? IEP_DST_ADDR_CR1 : IEP_DST_ADDR_CR)
++#define IEP_DEIN_OUT_IMG1_Y(bff) (IEP_DEIN_OUT_IMG0_Y(!bff))
++#define IEP_DEIN_OUT_IMG1_CBCR(bff) (IEP_DEIN_OUT_IMG0_CBCR(!bff))
++#define IEP_DEIN_OUT_IMG1_CR(bff) (IEP_DEIN_OUT_IMG0_CR(!bff))
++
++#define IEP_DEIN_MODE(m) (m << IEP_DEIN_MODE_SHFT)
++
++#define IEP_DEIN_IN_MODE_FIELDS(m) ((m == IEP_DEIN_MODE_I4O1T || m == IEP_DEIN_MODE_I4O1B \
++				     || m == IEP_DEIN_MODE_I4O2) \
++				    ? IEP_DEIN_IN_FIELDS_4 : IEP_DEIN_IN_FIELDS_2)
++
++#define IEP_DEIN_OUT_MODE_FRAMES(m) (m == IEP_DEIN_MODE_I4O2 \
++				     ? IEP_DEIN_OUT_FRAMES_2 : IEP_DEIN_OUT_FRAMES_1)
++
++#define IEP_DEIN_OUT_MODE_1FRM_TOP_FIELD(m) (m == IEP_DEIN_MODE_I4O1T || IEP_DEIN_MODE_I2O1T \
++					      ? 1 : 0)
++
++#define IEP_DEIN_EDGE_INTPOL_RADIUS(r) (r << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT)
++
++#define IEP_DEIN_HIGH_FREQ(f) (f << IEP_DEIN_HIGH_FREQ_SHFT)
++
++/* YUV Enhance video modes */
++#define VIDEO_MODE_BLACK_SCREEN		0U
++#define VIDEO_MODE_BLUE_SCREEN		1U
++#define VIDEO_MODE_COLOR_BARS		2U
++#define VIDEO_MODE_NORMAL_VIDEO		3U
++
++#define YUV_VIDEO_MODE(m) ((m << IEP_YUV_VIDEO_MODE_SHFT) & IEP_YUV_VIDEO_MODE_MASK)
++#define YUV_BRIGHTNESS(v) ((v << IEP_YUV_BRIGHTNESS_SHFT) & IEP_YUV_BRIGHTNESS_MASK)
++#define YUV_CONTRAST(v) ((v << IEP_YUV_CONTRAST_SHFT) & IEP_YUV_CONTRAST_MASK)
++#define YUV_SATURATION(v) ((v << IEP_YUV_SATURATION_SHFT) & IEP_YUV_SATURATION_MASK)
++#define YUV_COS_HUE(v) ((v << IEP_YUV_COS_HUE_SHFT) & IEP_YUV_COS_HUE_MASK)
++#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK)
++
++#endif
+diff --git a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/rockchip/iep/iep.c
+new file mode 100644
+index 000000000000..f4b9320733be
+--- /dev/null
++++ b/drivers/media/platform/rockchip/iep/iep.c
+@@ -0,0 +1,1089 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Rockchip Image Enhancement Processor (IEP) driver
++ *
++ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
++ *
++ * Based on Allwinner sun8i deinterlacer with scaler driver
++ *  Copyright (C) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ *
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-mem2mem.h>
++#include <media/videobuf2-v4l2.h>
++#include <media/videobuf2-core.h>
++#include <media/videobuf2-dma-contig.h>
++#include <linux/videodev2.h>
++
++#include "iep-regs.h"
++#include "iep.h"
++
++static struct iep_fmt formats[] = {
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.color_swap = IEP_YUV_SWP_SP_UV,
++		.hw_format = IEP_COLOR_FMT_YUV420,
++		.depth = 12,
++		.uv_factor = 4,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.color_swap = IEP_YUV_SWP_SP_VU,
++		.hw_format = IEP_COLOR_FMT_YUV420,
++		.depth = 12,
++		.uv_factor = 4,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV16,
++		.color_swap = IEP_YUV_SWP_SP_UV,
++		.hw_format = IEP_COLOR_FMT_YUV422,
++		.depth = 16,
++		.uv_factor = 2,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV61,
++		.color_swap = IEP_YUV_SWP_SP_VU,
++		.hw_format = IEP_COLOR_FMT_YUV422,
++		.depth = 16,
++		.uv_factor = 2,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_YUV420,
++		.color_swap = IEP_YUV_SWP_P,
++		.hw_format = IEP_COLOR_FMT_YUV420,
++		.depth = 12,
++		.uv_factor = 4,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_YUV422P,
++		.color_swap = IEP_YUV_SWP_P,
++		.hw_format = IEP_COLOR_FMT_YUV422,
++		.depth = 16,
++		.uv_factor = 2,
++	},
++};
++
++static struct iep_fmt *iep_fmt_find(struct v4l2_pix_format *pix_fmt)
++{
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(formats); i++) {
++		if (formats[i].fourcc == pix_fmt->pixelformat)
++			return &formats[i];
++	}
++
++	return NULL;
++}
++
++static bool iep_check_pix_format(u32 pixelformat)
++{
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(formats); i++)
++		if (formats[i].fourcc == pixelformat)
++			return true;
++
++	return false;
++}
++
++static struct vb2_v4l2_buffer *iep_m2m_next_dst_buf(struct iep_ctx *ctx)
++{
++	struct vb2_v4l2_buffer *dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
++
++	/* application has set a dst sequence: take it as start point */
++	if (ctx->dst_sequence == 0 && dst_buf->sequence > 0)
++		ctx->dst_sequence = dst_buf->sequence;
++
++	dst_buf->sequence = ctx->dst_sequence++;
++
++	return dst_buf;
++}
++
++static void iep_m2m_dst_bufs_done(struct iep_ctx *ctx, enum vb2_buffer_state state)
++{
++	if (ctx->dst0_buf) {
++		v4l2_m2m_buf_done(ctx->dst0_buf, state);
++		ctx->dst_buffs_done++;
++		ctx->dst0_buf = NULL;
++	}
++
++	if (ctx->dst1_buf) {
++		v4l2_m2m_buf_done(ctx->dst1_buf, state);
++		ctx->dst_buffs_done++;
++		ctx->dst1_buf = NULL;
++	}
++}
++
++static void iep_setup_formats(struct iep_ctx *ctx)
++{
++	/* setup src dimensions */
++	iep_write(ctx->iep, IEP_SRC_IMG_SIZE,
++		  IEP_IMG_SIZE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height));
++
++	/* setup dst dimensions */
++	iep_write(ctx->iep, IEP_DST_IMG_SIZE,
++		  IEP_IMG_SIZE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height));
++
++	/* setup virtual width */
++	iep_write(ctx->iep, IEP_VIR_IMG_WIDTH,
++		  IEP_VIR_WIDTH(ctx->src_fmt.pix.width, ctx->dst_fmt.pix.width));
++
++	/* setup src format */
++	iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1,
++		       IEP_SRC_FMT_MASK | IEP_SRC_FMT_SWP_MASK(ctx->src_fmt.hw_fmt->hw_format),
++		       IEP_SRC_FMT(ctx->src_fmt.hw_fmt->hw_format,
++				   ctx->src_fmt.hw_fmt->color_swap));
++	/* setup dst format */
++	iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1,
++		       IEP_DST_FMT_MASK | IEP_DST_FMT_SWP_MASK(ctx->dst_fmt.hw_fmt->hw_format),
++		       IEP_DST_FMT(ctx->dst_fmt.hw_fmt->hw_format,
++				   ctx->dst_fmt.hw_fmt->color_swap));
++
++	ctx->fmt_changed = false;
++}
++
++static void iep_dein_init(struct rockchip_iep *iep)
++{
++	unsigned int i;
++
++	/* values taken from BSP driver */
++	iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0,
++		       (IEP_DEIN_EDGE_INTPOL_SMTH_EN |
++		       IEP_DEIN_EDGE_INTPOL_RADIUS_MASK |
++		       IEP_DEIN_HIGH_FREQ_EN |
++		       IEP_DEIN_HIGH_FREQ_MASK),
++		       (IEP_DEIN_EDGE_INTPOL_SMTH_EN |
++		       IEP_DEIN_EDGE_INTPOL_RADIUS(3) |
++		       IEP_DEIN_HIGH_FREQ_EN |
++		       IEP_DEIN_HIGH_FREQ(64)));
++
++	for (i = 0; i < ARRAY_SIZE(default_dein_motion_tbl); i++)
++		iep_write(iep, default_dein_motion_tbl[i][0],
++			  default_dein_motion_tbl[i][1]);
++}
++
++static void iep_init(struct rockchip_iep *iep)
++{
++	iep_write(iep, IEP_CONFIG0,
++		  IEP_DEIN_MODE(IEP_DEIN_MODE_BYPASS) // |
++		  //IEP_YUV_ENHNC_EN
++	);
++
++	/* TODO: B/S/C/H works
++	 *  only in 1-frame-out modes
++	iep_write(iep, IEP_ENH_YUV_CNFG_0,
++		  YUV_BRIGHTNESS(0) |
++		  YUV_CONTRAST(128) |
++		  YUV_SATURATION(128));
++
++	iep_write(iep, IEP_ENH_YUV_CNFG_1,
++		  YUV_COS_HUE(255) |
++		  YUV_SIN_HUE(255));
++
++	iep_write(iep, IEP_ENH_YUV_CNFG_2,
++		  YUV_VIDEO_MODE(VIDEO_MODE_NORMAL_VIDEO));
++
++	*/
++
++	/* reset frame counter */
++	iep_write(iep, IEP_FRM_CNT, 0);
++}
++
++static void iep_device_run(void *priv)
++{
++	struct iep_ctx *ctx = priv;
++	struct rockchip_iep *iep = ctx->iep;
++	struct vb2_v4l2_buffer *src, *dst;
++	unsigned int dein_mode;
++	dma_addr_t addr;
++
++	if (ctx->fmt_changed)
++		iep_setup_formats(ctx);
++
++	if (ctx->prev_src_buf)
++		dein_mode = IEP_DEIN_MODE_I4O2;
++	else
++		dein_mode = ctx->field_bff ? IEP_DEIN_MODE_I2O1B : IEP_DEIN_MODE_I2O1T;
++
++	iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0,
++		       IEP_DEIN_MODE_MASK, IEP_DEIN_MODE(dein_mode));
++
++	/* sync RAW_xxx registers with actual used */
++	iep_write(iep, IEP_CONFIG_DONE, 1);
++
++	/* setup src buff(s)/addresses */
++	src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
++	addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0);
++
++	iep_write(iep, IEP_DEIN_IN_IMG0_Y(ctx->field_bff), addr);
++
++	iep_write(iep, IEP_DEIN_IN_IMG0_CBCR(ctx->field_bff),
++		  addr + ctx->src_fmt.y_stride);
++
++	iep_write(iep, IEP_DEIN_IN_IMG0_CR(ctx->field_bff),
++		  addr + ctx->src_fmt.uv_stride);
++
++	if (IEP_DEIN_IN_MODE_FIELDS(dein_mode) == IEP_DEIN_IN_FIELDS_4)
++		addr = vb2_dma_contig_plane_dma_addr(&ctx->prev_src_buf->vb2_buf, 0);
++
++	iep_write(iep, IEP_DEIN_IN_IMG1_Y(ctx->field_bff), addr);
++
++	iep_write(iep, IEP_DEIN_IN_IMG1_CBCR(ctx->field_bff),
++		  addr + ctx->src_fmt.y_stride);
++
++	iep_write(iep, IEP_DEIN_IN_IMG1_CR(ctx->field_bff),
++		  addr + ctx->src_fmt.uv_stride);
++
++	/* setup dst buff(s)/addresses */
++	dst = iep_m2m_next_dst_buf(ctx);
++	addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0);
++
++	if (IEP_DEIN_OUT_MODE_FRAMES(dein_mode) == IEP_DEIN_OUT_FRAMES_2) {
++		v4l2_m2m_buf_copy_metadata(ctx->prev_src_buf, dst, true);
++
++		iep_write(iep, IEP_DEIN_OUT_IMG0_Y(ctx->field_bff), addr);
++
++		iep_write(iep, IEP_DEIN_OUT_IMG0_CBCR(ctx->field_bff),
++			  addr + ctx->dst_fmt.y_stride);
++
++		iep_write(iep, IEP_DEIN_OUT_IMG0_CR(ctx->field_bff),
++			  addr + ctx->dst_fmt.uv_stride);
++
++		ctx->dst0_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
++
++		dst = iep_m2m_next_dst_buf(ctx);
++		addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0);
++	}
++
++	v4l2_m2m_buf_copy_metadata(src, dst, true);
++
++	iep_write(iep, IEP_DEIN_OUT_IMG1_Y(ctx->field_bff), addr);
++
++	iep_write(iep, IEP_DEIN_OUT_IMG1_CBCR(ctx->field_bff),
++		  addr + ctx->dst_fmt.y_stride);
++
++	iep_write(iep, IEP_DEIN_OUT_IMG1_CR(ctx->field_bff),
++		  addr + ctx->dst_fmt.uv_stride);
++
++	ctx->dst1_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
++
++	iep_mod(ctx->iep, IEP_INT, IEP_INT_FRAME_DONE_EN,
++		IEP_INT_FRAME_DONE_EN);
++
++	/* start HW */
++	iep_write(iep, IEP_FRM_START, 1);
++}
++
++static int iep_job_ready(void *priv)
++{
++	struct iep_ctx *ctx = priv;
++
++	return v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2 &&
++	       v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1;
++}
++
++static void iep_job_abort(void *priv)
++{
++	struct iep_ctx *ctx = priv;
++
++	/* Will cancel the transaction in the next interrupt handler */
++	ctx->job_abort = true;
++}
++
++static const struct v4l2_m2m_ops iep_m2m_ops = {
++	.device_run	= iep_device_run,
++	.job_ready	= iep_job_ready,
++	.job_abort	= iep_job_abort,
++};
++
++static int iep_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
++			   unsigned int *nplanes, unsigned int sizes[],
++				   struct device *alloc_devs[])
++{
++	struct iep_ctx *ctx = vb2_get_drv_priv(vq);
++	struct v4l2_pix_format *pix_fmt;
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type))
++		pix_fmt = &ctx->src_fmt.pix;
++	else
++		pix_fmt = &ctx->dst_fmt.pix;
++
++	if (*nplanes) {
++		if (sizes[0] < pix_fmt->sizeimage)
++			return -EINVAL;
++	} else {
++		sizes[0] = pix_fmt->sizeimage;
++		*nplanes = 1;
++	}
++
++	return 0;
++}
++
++static int iep_buf_prepare(struct vb2_buffer *vb)
++{
++	struct vb2_queue *vq = vb->vb2_queue;
++	struct iep_ctx *ctx = vb2_get_drv_priv(vq);
++	struct v4l2_pix_format *pix_fmt;
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type))
++		pix_fmt = &ctx->src_fmt.pix;
++	else
++		pix_fmt = &ctx->dst_fmt.pix;
++
++	if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage)
++		return -EINVAL;
++
++	/* set bytesused for capture buffers */
++	if (!V4L2_TYPE_IS_OUTPUT(vq->type))
++		vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage);
++
++	return 0;
++}
++
++static void iep_buf_queue(struct vb2_buffer *vb)
++{
++	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
++	struct iep_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++
++	v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
++}
++
++static void iep_queue_cleanup(struct vb2_queue *vq, u32 state)
++{
++	struct iep_ctx *ctx = vb2_get_drv_priv(vq);
++	struct vb2_v4l2_buffer *vbuf;
++
++	do {
++		if (V4L2_TYPE_IS_OUTPUT(vq->type))
++			vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
++		else
++			vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
++
++		if (vbuf)
++			v4l2_m2m_buf_done(vbuf, state);
++	} while (vbuf);
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev_src_buf)
++		v4l2_m2m_buf_done(ctx->prev_src_buf, state);
++	else
++		iep_m2m_dst_bufs_done(ctx, state);
++}
++
++static int iep_start_streaming(struct vb2_queue *vq, unsigned int count)
++{
++	struct iep_ctx *ctx = vb2_get_drv_priv(vq);
++	struct device *dev = ctx->iep->dev;
++	int ret;
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
++		ret = pm_runtime_get_sync(dev);
++		if (ret < 0) {
++			dev_err(dev, "Failed to enable module\n");
++			goto err_runtime_get;
++		}
++
++		ctx->field_order_bff =
++			ctx->src_fmt.pix.field == V4L2_FIELD_INTERLACED_BT;
++		ctx->field_bff = ctx->field_order_bff;
++
++		ctx->src_sequence = 0;
++		ctx->dst_sequence = 0;
++
++		ctx->prev_src_buf = NULL;
++
++		ctx->dst0_buf = NULL;
++		ctx->dst1_buf = NULL;
++		ctx->dst_buffs_done = 0;
++
++		ctx->job_abort = false;
++
++		iep_init(ctx->iep);
++		//if (ctx->src_fmt.pix.field != ctx->dst_fmt.pix.field)
++		iep_dein_init(ctx->iep);
++	}
++
++	return 0;
++
++err_runtime_get:
++	iep_queue_cleanup(vq, VB2_BUF_STATE_QUEUED);
++
++	return ret;
++}
++
++static void iep_stop_streaming(struct vb2_queue *vq)
++{
++	struct iep_ctx *ctx = vb2_get_drv_priv(vq);
++
++	if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
++		pm_runtime_mark_last_busy(ctx->iep->dev);
++		pm_runtime_put_autosuspend(ctx->iep->dev);
++	}
++
++	iep_queue_cleanup(vq, VB2_BUF_STATE_ERROR);
++}
++
++static const struct vb2_ops iep_qops = {
++	.queue_setup		= iep_queue_setup,
++	.buf_prepare		= iep_buf_prepare,
++	.buf_queue		= iep_buf_queue,
++	.start_streaming	= iep_start_streaming,
++	.stop_streaming		= iep_stop_streaming,
++	.wait_prepare		= vb2_ops_wait_prepare,
++	.wait_finish		= vb2_ops_wait_finish,
++};
++
++static int iep_queue_init(void *priv, struct vb2_queue *src_vq,
++			  struct vb2_queue *dst_vq)
++{
++	struct iep_ctx *ctx = priv;
++	int ret;
++
++	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
++	src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
++			    DMA_ATTR_NO_KERNEL_MAPPING;
++	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
++	src_vq->drv_priv = ctx;
++	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	src_vq->min_buffers_needed = 1;
++	src_vq->ops = &iep_qops;
++	src_vq->mem_ops = &vb2_dma_contig_memops;
++	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	src_vq->lock = &ctx->iep->mutex;
++	src_vq->dev = ctx->iep->v4l2_dev.dev;
++
++	ret = vb2_queue_init(src_vq);
++	if (ret)
++		return ret;
++
++	dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
++			    DMA_ATTR_NO_KERNEL_MAPPING;
++	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
++	dst_vq->drv_priv = ctx;
++	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	dst_vq->min_buffers_needed = 2;
++	dst_vq->ops = &iep_qops;
++	dst_vq->mem_ops = &vb2_dma_contig_memops;
++	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	dst_vq->lock = &ctx->iep->mutex;
++	dst_vq->dev = ctx->iep->v4l2_dev.dev;
++
++	ret = vb2_queue_init(dst_vq);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static void iep_prepare_format(struct v4l2_pix_format *pix_fmt)
++{
++	unsigned int height = pix_fmt->height;
++	unsigned int width = pix_fmt->width;
++	unsigned int sizeimage, bytesperline;
++
++	struct iep_fmt *hw_fmt = iep_fmt_find(pix_fmt);
++
++	if (!hw_fmt) {
++		hw_fmt = &formats[0];
++		pix_fmt->pixelformat = hw_fmt->fourcc;
++	}
++
++	width = ALIGN(clamp(width, IEP_MIN_WIDTH,
++			    IEP_MAX_WIDTH), 16);
++	height = ALIGN(clamp(height, IEP_MIN_HEIGHT,
++			     IEP_MAX_HEIGHT), 16);
++
++	bytesperline = FMT_IS_YUV(hw_fmt->hw_format)
++		       ? width : (width * hw_fmt->depth) >> 3;
++
++	sizeimage = height * (width * hw_fmt->depth) >> 3;
++
++	pix_fmt->width = width;
++	pix_fmt->height = height;
++	pix_fmt->bytesperline = bytesperline;
++	pix_fmt->sizeimage = sizeimage;
++}
++
++static int iep_open(struct file *file)
++{
++	struct rockchip_iep *iep = video_drvdata(file);
++	struct iep_ctx *ctx = NULL;
++
++	int ret;
++
++	if (mutex_lock_interruptible(&iep->mutex))
++		return -ERESTARTSYS;
++
++	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
++	if (!ctx) {
++		mutex_unlock(&iep->mutex);
++		return -ENOMEM;
++	}
++
++	/* default output format */
++	ctx->src_fmt.pix.pixelformat = formats[0].fourcc;
++	ctx->src_fmt.pix.field = V4L2_FIELD_INTERLACED;
++	ctx->src_fmt.pix.width = IEP_DEFAULT_WIDTH;
++	ctx->src_fmt.pix.height = IEP_DEFAULT_HEIGHT;
++	iep_prepare_format(&ctx->src_fmt.pix);
++	ctx->src_fmt.hw_fmt = &formats[0];
++	ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height);
++	ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height,
++					       ctx->src_fmt.hw_fmt->uv_factor);
++
++	/* default capture format */
++	ctx->dst_fmt.pix.pixelformat = formats[0].fourcc;
++	ctx->dst_fmt.pix.field = V4L2_FIELD_NONE;
++	ctx->dst_fmt.pix.width = IEP_DEFAULT_WIDTH;
++	ctx->dst_fmt.pix.height = IEP_DEFAULT_HEIGHT;
++	iep_prepare_format(&ctx->dst_fmt.pix);
++	ctx->dst_fmt.hw_fmt = &formats[0];
++	ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height);
++	ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height,
++					       ctx->dst_fmt.hw_fmt->uv_factor);
++	/* ensure fmts are written to HW */
++	ctx->fmt_changed = true;
++
++	v4l2_fh_init(&ctx->fh, video_devdata(file));
++	file->private_data = &ctx->fh;
++	ctx->iep = iep;
++
++	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(iep->m2m_dev, ctx,
++					    &iep_queue_init);
++
++	if (IS_ERR(ctx->fh.m2m_ctx)) {
++		ret = PTR_ERR(ctx->fh.m2m_ctx);
++		goto err_free;
++	}
++
++	v4l2_fh_add(&ctx->fh);
++
++	mutex_unlock(&iep->mutex);
++
++	return 0;
++
++err_free:
++	kfree(ctx);
++	mutex_unlock(&iep->mutex);
++
++	return ret;
++}
++
++static int iep_release(struct file *file)
++{
++	struct rockchip_iep *iep = video_drvdata(file);
++	struct iep_ctx *ctx = container_of(file->private_data,
++						   struct iep_ctx, fh);
++
++	mutex_lock(&iep->mutex);
++
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
++	kfree(ctx);
++
++	mutex_unlock(&iep->mutex);
++	return 0;
++}
++
++static const struct v4l2_file_operations iep_fops = {
++	.owner		= THIS_MODULE,
++	.open		= iep_open,
++	.release	= iep_release,
++	.poll		= v4l2_m2m_fop_poll,
++	.unlocked_ioctl	= video_ioctl2,
++	.mmap		= v4l2_m2m_fop_mmap,
++};
++
++static int iep_querycap(struct file *file, void *priv,
++			struct v4l2_capability *cap)
++{
++	strscpy(cap->driver, IEP_NAME, sizeof(cap->driver));
++	strscpy(cap->card, IEP_NAME, sizeof(cap->card));
++	snprintf(cap->bus_info, sizeof(cap->bus_info),
++		 "platform:%s", IEP_NAME);
++
++	return 0;
++}
++
++static int iep_enum_fmt(struct file *file, void *priv,
++			struct v4l2_fmtdesc *f)
++{
++	struct iep_fmt *fmt;
++
++	if (f->index < ARRAY_SIZE(formats)) {
++		fmt = &formats[f->index];
++		f->pixelformat = fmt->fourcc;
++
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
++static int iep_enum_framesizes(struct file *file, void *priv,
++			       struct v4l2_frmsizeenum *fsize)
++{
++	if (fsize->index != 0)
++		return -EINVAL;
++
++	if (!iep_check_pix_format(fsize->pixel_format))
++		return -EINVAL;
++
++	fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
++
++	fsize->stepwise.min_width = IEP_MIN_WIDTH;
++	fsize->stepwise.max_width = IEP_MAX_WIDTH;
++	fsize->stepwise.step_width = 16;
++
++	fsize->stepwise.min_height = IEP_MIN_HEIGHT;
++	fsize->stepwise.max_height = IEP_MAX_HEIGHT;
++	fsize->stepwise.step_height = 16;
++
++	return 0;
++}
++
++static inline struct iep_ctx *iep_file2ctx(struct file *file)
++{
++	return container_of(file->private_data, struct iep_ctx, fh);
++}
++
++static int iep_g_fmt_vid_cap(struct file *file, void *priv,
++			     struct v4l2_format *f)
++{
++	struct iep_ctx *ctx = iep_file2ctx(file);
++
++	f->fmt.pix = ctx->dst_fmt.pix;
++
++	return 0;
++}
++
++static int iep_g_fmt_vid_out(struct file *file, void *priv,
++			     struct v4l2_format *f)
++{
++	struct iep_ctx *ctx = iep_file2ctx(file);
++
++	f->fmt.pix = ctx->src_fmt.pix;
++
++	return 0;
++}
++
++static int iep_try_fmt_vid_cap(struct file *file, void *priv,
++			       struct v4l2_format *f)
++{
++	f->fmt.pix.field = V4L2_FIELD_NONE;
++	iep_prepare_format(&f->fmt.pix);
++
++	return 0;
++}
++
++static int iep_try_fmt_vid_out(struct file *file, void *priv,
++			       struct v4l2_format *f)
++{
++	if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB &&
++	    f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT &&
++	    f->fmt.pix.field != V4L2_FIELD_INTERLACED)
++		f->fmt.pix.field = V4L2_FIELD_INTERLACED;
++
++	iep_prepare_format(&f->fmt.pix);
++
++	return 0;
++}
++
++static int iep_s_fmt_vid_out(struct file *file, void *priv,
++			     struct v4l2_format *f)
++{
++	struct iep_ctx *ctx = iep_file2ctx(file);
++	struct vb2_queue *vq;
++
++	int ret;
++
++	ret = iep_try_fmt_vid_out(file, priv, f);
++	if (ret)
++		return ret;
++
++	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
++	if (vb2_is_busy(vq))
++		return -EBUSY;
++
++	ctx->src_fmt.pix = f->fmt.pix;
++	ctx->src_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix);
++	ctx->src_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
++	ctx->src_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
++					       ctx->src_fmt.hw_fmt->uv_factor);
++
++	/* Propagate colorspace information to capture. */
++	ctx->dst_fmt.pix.colorspace = f->fmt.pix.colorspace;
++	ctx->dst_fmt.pix.xfer_func = f->fmt.pix.xfer_func;
++	ctx->dst_fmt.pix.ycbcr_enc = f->fmt.pix.ycbcr_enc;
++	ctx->dst_fmt.pix.quantization = f->fmt.pix.quantization;
++
++	/* scaling is not supported */
++	ctx->dst_fmt.pix.width = f->fmt.pix.width;
++	ctx->dst_fmt.pix.height = f->fmt.pix.height;
++	ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
++	ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
++					       ctx->dst_fmt.hw_fmt->uv_factor);
++
++	ctx->fmt_changed = true;
++
++	return 0;
++}
++
++static int iep_s_fmt_vid_cap(struct file *file, void *priv,
++			     struct v4l2_format *f)
++{
++	struct iep_ctx *ctx = iep_file2ctx(file);
++	struct vb2_queue *vq;
++	int ret;
++
++	ret = iep_try_fmt_vid_cap(file, priv, f);
++	if (ret)
++		return ret;
++
++	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
++	if (vb2_is_busy(vq))
++		return -EBUSY;
++
++	/* scaling is not supported */
++	f->fmt.pix.width = ctx->src_fmt.pix.width;
++	f->fmt.pix.height = ctx->src_fmt.pix.height;
++
++	ctx->dst_fmt.pix = f->fmt.pix;
++	ctx->dst_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix);
++
++	ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
++	ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
++					       ctx->dst_fmt.hw_fmt->uv_factor);
++
++	ctx->fmt_changed = true;
++
++	return 0;
++}
++
++static const struct v4l2_ioctl_ops iep_ioctl_ops = {
++	.vidioc_querycap		= iep_querycap,
++
++	.vidioc_enum_framesizes		= iep_enum_framesizes,
++
++	.vidioc_enum_fmt_vid_cap	= iep_enum_fmt,
++	.vidioc_g_fmt_vid_cap		= iep_g_fmt_vid_cap,
++	.vidioc_try_fmt_vid_cap		= iep_try_fmt_vid_cap,
++	.vidioc_s_fmt_vid_cap		= iep_s_fmt_vid_cap,
++
++	.vidioc_enum_fmt_vid_out	= iep_enum_fmt,
++	.vidioc_g_fmt_vid_out		= iep_g_fmt_vid_out,
++	.vidioc_try_fmt_vid_out		= iep_try_fmt_vid_out,
++	.vidioc_s_fmt_vid_out		= iep_s_fmt_vid_out,
++
++	.vidioc_reqbufs			= v4l2_m2m_ioctl_reqbufs,
++	.vidioc_querybuf		= v4l2_m2m_ioctl_querybuf,
++	.vidioc_qbuf			= v4l2_m2m_ioctl_qbuf,
++	.vidioc_dqbuf			= v4l2_m2m_ioctl_dqbuf,
++	.vidioc_prepare_buf		= v4l2_m2m_ioctl_prepare_buf,
++	.vidioc_create_bufs		= v4l2_m2m_ioctl_create_bufs,
++	.vidioc_expbuf			= v4l2_m2m_ioctl_expbuf,
++
++	.vidioc_streamon		= v4l2_m2m_ioctl_streamon,
++	.vidioc_streamoff		= v4l2_m2m_ioctl_streamoff,
++};
++
++static const struct video_device iep_video_device = {
++	.name		= IEP_NAME,
++	.vfl_dir	= VFL_DIR_M2M,
++	.fops		= &iep_fops,
++	.ioctl_ops	= &iep_ioctl_ops,
++	.minor		= -1,
++	.release	= video_device_release_empty,
++	.device_caps	= V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
++};
++
++static int iep_parse_dt(struct rockchip_iep *iep)
++{
++	int ret = 0;
++
++	iep->axi_clk = devm_clk_get(iep->dev, "axi");
++	if (IS_ERR(iep->axi_clk)) {
++		dev_err(iep->dev, "failed to get aclk clock\n");
++		return PTR_ERR(iep->axi_clk);
++	}
++
++	iep->ahb_clk = devm_clk_get(iep->dev, "ahb");
++	if (IS_ERR(iep->ahb_clk)) {
++		dev_err(iep->dev, "failed to get hclk clock\n");
++		return PTR_ERR(iep->ahb_clk);
++	}
++
++	ret = clk_set_rate(iep->axi_clk, 300000000);
++
++	if (ret)
++		dev_err(iep->dev, "failed to set axi clock rate to 300 MHz\n");
++
++	return ret;
++}
++
++static irqreturn_t iep_isr(int irq, void *prv)
++{
++	struct rockchip_iep *iep = prv;
++	struct iep_ctx *ctx;
++	u32 val;
++	enum vb2_buffer_state state = VB2_BUF_STATE_DONE;
++
++	ctx = v4l2_m2m_get_curr_priv(iep->m2m_dev);
++	if (!ctx) {
++		v4l2_err(&iep->v4l2_dev,
++			 "Instance released before the end of transaction\n");
++		return IRQ_NONE;
++	}
++
++	/*
++	 * The irq is shared with the iommu. If the runtime-pm state of the
++	 * iep-device is disabled or the interrupt status doesn't match the
++	 * expeceted mask the irq has been targeted to the iommu.
++	 */
++
++	if (!pm_runtime_active(iep->dev) ||
++	    !(iep_read(iep, IEP_INT) & IEP_INT_MASK))
++		return IRQ_NONE;
++
++	/* disable interrupt - will be re-enabled at next iep_device_run */
++	iep_mod(ctx->iep, IEP_INT,
++		IEP_INT_FRAME_DONE_EN, 0);
++
++	iep_mod(iep, IEP_INT, IEP_INT_FRAME_DONE_CLR,
++		IEP_INT_FRAME_DONE_CLR);
++
++	/* wait for all status regs to show "idle" */
++	val = readl_poll_timeout(iep->regs + IEP_STATUS, val,
++				  (val == 0), 100, IEP_TIMEOUT);
++
++	if (val) {
++		dev_err(iep->dev,
++			"Failed to wait for job to finish: status: %u\n", val);
++		state = VB2_BUF_STATE_ERROR;
++		ctx->job_abort = true;
++	}
++
++	iep_m2m_dst_bufs_done(ctx, state);
++
++	ctx->field_bff = (ctx->dst_buffs_done % 2 == 0)
++		     ? ctx->field_order_bff : !ctx->field_order_bff;
++
++	if (ctx->dst_buffs_done == 2 || ctx->job_abort) {
++		if (ctx->prev_src_buf)
++			v4l2_m2m_buf_done(ctx->prev_src_buf, state);
++
++		/* current src buff will be next prev */
++		ctx->prev_src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
++
++		v4l2_m2m_job_finish(ctx->iep->m2m_dev, ctx->fh.m2m_ctx);
++		ctx->dst_buffs_done = 0;
++
++	} else {
++		iep_device_run(ctx);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static int iep_probe(struct platform_device *pdev)
++{
++	struct rockchip_iep *iep;
++	struct video_device *vfd;
++	struct resource *res;
++	int ret = 0;
++	int irq;
++
++	if (!pdev->dev.of_node)
++		return -ENODEV;
++
++	iep = devm_kzalloc(&pdev->dev, sizeof(*iep), GFP_KERNEL);
++	if (!iep)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, iep);
++	iep->dev = &pdev->dev;
++	iep->vfd = iep_video_device;
++
++	ret = iep_parse_dt(iep);
++	if (ret)
++		dev_err(&pdev->dev, "Unable to parse OF data\n");
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++	iep->regs = devm_ioremap_resource(iep->dev, res);
++	if (IS_ERR(iep->regs)) {
++		ret = PTR_ERR(iep->regs);
++		goto err_put_clk;
++	}
++
++	ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++	if (ret) {
++		dev_err(&pdev->dev, "Could not set DMA coherent mask.\n");
++		goto err_put_clk;
++	}
++
++	vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0) {
++		ret = irq;
++		goto err_put_clk;
++	}
++
++	/* IRQ is shared with IOMMU */
++	ret = devm_request_irq(iep->dev, irq, iep_isr, IRQF_SHARED,
++			       dev_name(iep->dev), iep);
++	if (ret < 0) {
++		dev_err(iep->dev, "failed to request irq\n");
++		goto err_put_clk;
++	}
++
++	mutex_init(&iep->mutex);
++
++	ret = v4l2_device_register(&pdev->dev, &iep->v4l2_dev);
++	if (ret) {
++		dev_err(iep->dev, "Failed to register V4L2 device\n");
++
++		return ret;
++	}
++
++	vfd = &iep->vfd;
++	vfd->lock = &iep->mutex;
++	vfd->v4l2_dev = &iep->v4l2_dev;
++
++	snprintf(vfd->name, sizeof(vfd->name), "%s",
++		 iep_video_device.name);
++
++	video_set_drvdata(vfd, iep);
++
++	ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
++	if (ret) {
++		v4l2_err(&iep->v4l2_dev, "Failed to register video device\n");
++
++		goto err_v4l2;
++	}
++
++	v4l2_info(&iep->v4l2_dev,
++		  "Device %s registered as /dev/video%d\n", vfd->name, vfd->num);
++
++	iep->m2m_dev = v4l2_m2m_init(&iep_m2m_ops);
++	if (IS_ERR(iep->m2m_dev)) {
++		v4l2_err(&iep->v4l2_dev,
++			 "Failed to initialize V4L2 M2M device\n");
++		ret = PTR_ERR(iep->m2m_dev);
++
++		goto err_video;
++	}
++
++	pm_runtime_set_autosuspend_delay(iep->dev, 100);
++	pm_runtime_use_autosuspend(iep->dev);
++	pm_runtime_enable(iep->dev);
++
++	return ret;
++
++err_video:
++	video_unregister_device(&iep->vfd);
++err_v4l2:
++	v4l2_device_unregister(&iep->v4l2_dev);
++err_put_clk:
++	pm_runtime_dont_use_autosuspend(iep->dev);
++	pm_runtime_disable(iep->dev);
++
++return ret;
++}
++
++static int iep_remove(struct platform_device *pdev)
++{
++	struct rockchip_iep *iep = platform_get_drvdata(pdev);
++
++	pm_runtime_dont_use_autosuspend(iep->dev);
++	pm_runtime_disable(iep->dev);
++
++	v4l2_m2m_release(iep->m2m_dev);
++	video_unregister_device(&iep->vfd);
++	v4l2_device_unregister(&iep->v4l2_dev);
++
++	return 0;
++}
++
++static int __maybe_unused iep_runtime_suspend(struct device *dev)
++{
++	struct rockchip_iep *iep = dev_get_drvdata(dev);
++
++	clk_disable_unprepare(iep->ahb_clk);
++	clk_disable_unprepare(iep->axi_clk);
++
++	return 0;
++}
++
++static int __maybe_unused iep_runtime_resume(struct device *dev)
++{
++	struct rockchip_iep *iep;
++	int ret = 0;
++
++	iep = dev_get_drvdata(dev);
++
++	ret = clk_prepare_enable(iep->axi_clk);
++	if (ret) {
++		dev_err(iep->dev, "Cannot enable axi clock: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(iep->ahb_clk);
++	if (ret) {
++		dev_err(iep->dev, "Cannot enable ahb clock: %d\n", ret);
++		goto err_disable_axi_clk;
++	}
++
++	return ret;
++
++err_disable_axi_clk:
++	clk_disable_unprepare(iep->axi_clk);
++	return ret;
++}
++
++static const struct dev_pm_ops iep_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
++	SET_RUNTIME_PM_OPS(iep_runtime_suspend,
++			   iep_runtime_resume, NULL)
++};
++
++static const struct of_device_id rockchip_iep_match[] = {
++	{
++		.compatible = "rockchip,rk3228-iep",
++	},
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, rockchip_iep_match);
++
++static struct platform_driver iep_pdrv = {
++	.probe = iep_probe,
++	.remove = iep_remove,
++	.driver = {
++		.name = IEP_NAME,
++		.pm = &iep_pm_ops,
++		.of_match_table = rockchip_iep_match,
++	},
++};
++
++module_platform_driver(iep_pdrv);
++
++MODULE_AUTHOR("Alex Bee <knaerzche@gmail.com>");
++MODULE_DESCRIPTION("Rockchip Image Enhancement Processor");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/media/platform/rockchip/iep/iep.h b/drivers/media/platform/rockchip/iep/iep.h
+new file mode 100644
+index 000000000000..7d9fc61624b6
+--- /dev/null
++++ b/drivers/media/platform/rockchip/iep/iep.h
+@@ -0,0 +1,112 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Rockchip Image Enhancement Processor (IEP) driver
++ *
++ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
++ *
++ */
++#ifndef __IEP_H__
++#define __IEP_H__
++
++#include <linux/platform_device.h>
++#include <media/videobuf2-v4l2.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++
++#define IEP_NAME "rockchip-iep"
++
++/* Hardware limits */
++#define IEP_MIN_WIDTH 320U
++#define IEP_MAX_WIDTH 1920U
++
++#define IEP_MIN_HEIGHT 240U
++#define IEP_MAX_HEIGHT 1088U
++
++/* Hardware defaults */
++#define IEP_DEFAULT_WIDTH 320U
++#define IEP_DEFAULT_HEIGHT 240U
++
++//ns
++#define IEP_TIMEOUT 250000
++
++struct iep_fmt {
++	u32 fourcc;
++	u8 depth;
++	u8 uv_factor;
++	u8 color_swap;
++	u8 hw_format;
++};
++
++struct iep_frm_fmt {
++	struct iep_fmt *hw_fmt;
++	struct v4l2_pix_format pix;
++
++	unsigned int y_stride;
++	unsigned int uv_stride;
++};
++
++struct iep_ctx {
++	struct v4l2_fh fh;
++	struct rockchip_iep *iep;
++
++	struct iep_frm_fmt src_fmt;
++	struct iep_frm_fmt dst_fmt;
++
++	struct vb2_v4l2_buffer	*prev_src_buf;
++	struct vb2_v4l2_buffer	*dst0_buf;
++	struct vb2_v4l2_buffer	*dst1_buf;
++
++	u32 dst_sequence;
++	u32 src_sequence;
++
++	/* bff = bottom field first */
++	bool field_order_bff;
++	bool field_bff;
++
++	unsigned int dst_buffs_done;
++
++	bool fmt_changed;
++	bool job_abort;
++};
++
++struct rockchip_iep {
++	struct v4l2_device v4l2_dev;
++	struct v4l2_m2m_dev *m2m_dev;
++	struct video_device vfd;
++
++	struct device *dev;
++
++	void __iomem *regs;
++
++	struct clk *axi_clk;
++	struct clk *ahb_clk;
++
++	/* vfd lock */
++	struct mutex mutex;
++};
++
++static inline void iep_write(struct rockchip_iep *iep, u32 reg, u32 value)
++{
++	writel(value, iep->regs + reg);
++};
++
++static inline u32 iep_read(struct rockchip_iep *iep, u32 reg)
++{
++	return readl(iep->regs + reg);
++};
++
++static inline void iep_shadow_mod(struct rockchip_iep *iep, u32 reg,
++				  u32 shadow_reg, u32 mask, u32 val)
++{
++	u32 temp = iep_read(iep, shadow_reg) & ~(mask);
++
++	temp |= val & mask;
++	iep_write(iep, reg, temp);
++};
++
++static inline void iep_mod(struct rockchip_iep *iep, u32 reg, u32 mask, u32 val)
++{
++	iep_shadow_mod(iep, reg, reg, mask, val);
++};
++
++#endif
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/general-v4l2-rkvdec-00-fixes.patch b/patch/kernel/archive/rockchip64-6.10/general-v4l2-rkvdec-00-fixes.patch
new file mode 100644
index 000000000000..ed0c61c2cb9c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-v4l2-rkvdec-00-fixes.patch
@@ -0,0 +1,659 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:35 +0000
+Subject: [PATCH] media: v4l2-common: Add helpers to calculate bytesperline and
+ sizeimage
+
+Add helper functions to calculate plane bytesperline and sizeimage, these
+new helpers consider block width and height when calculating plane
+bytesperline and sizeimage.
+
+This prepare support for new pixel formats added in next patch that make
+use of block width and height.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/media/v4l2-core/v4l2-common.c | 77 +++++++++++++--------------
+ 1 file changed, 38 insertions(+), 39 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
+index e0fbe6ba4b6c..cb2f1acab7cf 100644
+--- a/drivers/media/v4l2-core/v4l2-common.c
++++ b/drivers/media/v4l2-core/v4l2-common.c
+@@ -338,6 +338,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf
+ 	return info->block_h[plane];
+ }
+ 
++static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane,
++						   unsigned int width)
++{
++	unsigned int hdiv = plane ? info->hdiv : 1;
++	unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane],
++				v4l2_format_block_width(info, plane) *
++				v4l2_format_block_height(info, plane));
++
++	return DIV_ROUND_UP(bytes, hdiv);
++}
++
++static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane,
++						    unsigned int height)
++{
++	unsigned int vdiv = plane ? info->vdiv : 1;
++	unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane));
++
++	return DIV_ROUND_UP(lines, vdiv);
++}
++
++static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane,
++						  unsigned int width, unsigned int height)
++{
++	return v4l2_format_plane_width(info, plane, width) *
++	       v4l2_format_plane_height(info, plane, height);
++}
++
+ void v4l2_apply_frmsize_constraints(u32 *width, u32 *height,
+ 				    const struct v4l2_frmsize_stepwise *frmsize)
+ {
+@@ -373,37 +400,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
+ 
+ 	if (info->mem_planes == 1) {
+ 		plane = &pixfmt->plane_fmt[0];
+-		plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0];
++		plane->bytesperline = v4l2_format_plane_width(info, 0, width);
+ 		plane->sizeimage = 0;
+ 
+-		for (i = 0; i < info->comp_planes; i++) {
+-			unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+-			unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+-			unsigned int aligned_width;
+-			unsigned int aligned_height;
+-
+-			aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
+-			aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
+-
+-			plane->sizeimage += info->bpp[i] *
+-				DIV_ROUND_UP(aligned_width, hdiv) *
+-				DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i];
+-		}
++		for (i = 0; i < info->comp_planes; i++)
++			plane->sizeimage +=
++				v4l2_format_plane_size(info, i, width, height);
+ 	} else {
+ 		for (i = 0; i < info->comp_planes; i++) {
+-			unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+-			unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+-			unsigned int aligned_width;
+-			unsigned int aligned_height;
+-
+-			aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
+-			aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
+-
+ 			plane = &pixfmt->plane_fmt[i];
+ 			plane->bytesperline =
+-				info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv) / info->bpp_div[i];
+-			plane->sizeimage =
+-				plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv);
++				v4l2_format_plane_width(info, i, width);
++			plane->sizeimage = plane->bytesperline *
++				v4l2_format_plane_height(info, i, height);
+ 		}
+ 	}
+ 	return 0;
+@@ -427,22 +436,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
+ 	pixfmt->width = width;
+ 	pixfmt->height = height;
+ 	pixfmt->pixelformat = pixelformat;
+-	pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0];
++	pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width);
+ 	pixfmt->sizeimage = 0;
+ 
+-	for (i = 0; i < info->comp_planes; i++) {
+-		unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+-		unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+-		unsigned int aligned_width;
+-		unsigned int aligned_height;
+-
+-		aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
+-		aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
+-
+-		pixfmt->sizeimage += info->bpp[i] *
+-			DIV_ROUND_UP(aligned_width, hdiv) *
+-			DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i];
+-	}
++	for (i = 0; i < info->comp_planes; i++)
++		pixfmt->sizeimage +=
++			v4l2_format_plane_size(info, i, width, height);
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt);
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:36 +0000
+Subject: [PATCH] media: v4l2: Add NV15 and NV20 pixel formats
+
+Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for
+10-bit buffers.
+
+NV15 and NV20 is a packed 10-bit 4:2:0/4:2:2 semi-planar Y/UV format
+similar to P010 and P210 but has no padding between components. Instead,
+luminance and chrominance samples are grouped into 4s so that each group is
+packed into an integer number of bytes:
+
+YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
+
+The '15' and '20' suffix refers to the optimum effective bits per pixel
+which is achieved when the total number of luminance samples is a multiple
+of 8 for NV15 and 4 for NV20.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/media/v4l2-core/v4l2-common.c | 3 +++
+ drivers/media/v4l2-core/v4l2-ioctl.c  | 2 ++
+ include/uapi/linux/videodev2.h        | 3 +++
+ 3 files changed, 8 insertions(+)
+
+diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
+index cb2f1acab7cf..8446a1deffd8 100644
+--- a/drivers/media/v4l2-core/v4l2-common.c
++++ b/drivers/media/v4l2-core/v4l2-common.c
+@@ -268,6 +268,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
+ 		{ .format = V4L2_PIX_FMT_NV42,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ 		{ .format = V4L2_PIX_FMT_P010,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 },
+ 
++		{ .format = V4L2_PIX_FMT_NV15,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
++		{ .format = V4L2_PIX_FMT_NV20,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
++
+ 		{ .format = V4L2_PIX_FMT_YUV410,  .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 4 },
+ 		{ .format = V4L2_PIX_FMT_YVU410,  .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 4 },
+ 		{ .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 1 },
+diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
+index e6fd355a2e92..24771edaa4f2 100644
+--- a/drivers/media/v4l2-core/v4l2-ioctl.c
++++ b/drivers/media/v4l2-core/v4l2-ioctl.c
+@@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
+ 	case V4L2_PIX_FMT_NV42:		descr = "Y/VU 4:4:4"; break;
+ 	case V4L2_PIX_FMT_P010:		descr = "10-bit Y/UV 4:2:0"; break;
+ 	case V4L2_PIX_FMT_P012:		descr = "12-bit Y/UV 4:2:0"; break;
++	case V4L2_PIX_FMT_NV15:		descr = "10-bit Y/UV 4:2:0 (Packed)"; break;
++	case V4L2_PIX_FMT_NV20:		descr = "10-bit Y/UV 4:2:2 (Packed)"; break;
+ 	case V4L2_PIX_FMT_NV12_4L4:	descr = "Y/UV 4:2:0 (4x4 Linear)"; break;
+ 	case V4L2_PIX_FMT_NV12_16L16:	descr = "Y/UV 4:2:0 (16x16 Linear)"; break;
+ 	case V4L2_PIX_FMT_NV12_32L32:   descr = "Y/UV 4:2:0 (32x32 Linear)"; break;
+diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
+index 01e630f2ec78..cea44992aea3 100644
+--- a/include/uapi/linux/videodev2.h
++++ b/include/uapi/linux/videodev2.h
+@@ -628,6 +628,9 @@ struct v4l2_pix_format {
+ #define V4L2_PIX_FMT_NV42    v4l2_fourcc('N', 'V', '4', '2') /* 24  Y/VU 4:4:4  */
+ #define V4L2_PIX_FMT_P010    v4l2_fourcc('P', '0', '1', '0') /* 24  Y/UV 4:2:0 10-bit per component */
+ 
++#define V4L2_PIX_FMT_NV15    v4l2_fourcc('N', 'V', '1', '5') /* 15  Y/UV 4:2:0 10-bit packed */
++#define V4L2_PIX_FMT_NV20    v4l2_fourcc('N', 'V', '2', '0') /* 20  Y/UV 4:2:2 10-bit packed */
++
+ /* two non contiguous planes - one Y, one Cr + Cb interleaved  */
+ #define V4L2_PIX_FMT_NV12M   v4l2_fourcc('N', 'M', '1', '2') /* 12  Y/UV 4:2:0  */
+ #define V4L2_PIX_FMT_NV21M   v4l2_fourcc('N', 'M', '2', '1') /* 21  Y/VU 4:2:0  */
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:36 +0000
+Subject: [PATCH] media: rkvdec: h264: Use bytesperline and buffer height to
+ calculate stride
+
+Use bytesperline and buffer height to calculate the strides configured.
+
+This does not really change anything other than ensuring the bytesperline
+that is signaled to userspace matches what is configured in HW.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/rkvdec/rkvdec-h264.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
+index 4fc167b42cf0..a8635105e387 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
+@@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx,
+ 	dma_addr_t rlc_addr;
+ 	dma_addr_t refer_addr;
+ 	u32 rlc_len;
+-	u32 hor_virstride = 0;
+-	u32 ver_virstride = 0;
+-	u32 y_virstride = 0;
++	u32 hor_virstride;
++	u32 ver_virstride;
++	u32 y_virstride;
+ 	u32 yuv_virstride = 0;
+ 	u32 offset;
+ 	dma_addr_t dst_addr;
+@@ -909,8 +909,8 @@ static void config_registers(struct rkvdec_ctx *ctx,
+ 
+ 	f = &ctx->decoded_fmt;
+ 	dst_fmt = &f->fmt.pix_mp;
+-	hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8;
+-	ver_virstride = round_up(dst_fmt->height, 16);
++	hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
++	ver_virstride = dst_fmt->height;
+ 	y_virstride = hor_virstride * ver_virstride;
+ 
+ 	if (sps->chroma_format_idc == 0)
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:37 +0000
+Subject: [PATCH] media: rkvdec: Extract rkvdec_fill_decoded_pixfmt helper
+ method
+
+This extract setting decoded pixfmt into a helper method, current code is
+replaced with a call to the new helper method.
+
+The helper method is also called from a new function in next patch.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/rkvdec/rkvdec.c | 29 ++++++++++++++-------------
+ 1 file changed, 15 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index 7bab7586918c..40cc791aef26 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -27,6 +27,17 @@
+ #include "rkvdec.h"
+ #include "rkvdec-regs.h"
+ 
++static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
++				       struct v4l2_pix_format_mplane *pix_mp)
++{
++	v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
++			    pix_mp->width, pix_mp->height);
++	pix_mp->plane_fmt[0].sizeimage += 128 *
++		DIV_ROUND_UP(pix_mp->width, 16) *
++		DIV_ROUND_UP(pix_mp->height, 16);
++	pix_mp->field = V4L2_FIELD_NONE;
++}
++
+ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
+ {
+ 	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
+@@ -192,13 +203,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
+ 
+ 	rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
+ 	f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+-	v4l2_fill_pixfmt_mp(&f->fmt.pix_mp,
+-			    ctx->coded_fmt_desc->decoded_fmts[0],
+-			    ctx->coded_fmt.fmt.pix_mp.width,
+-			    ctx->coded_fmt.fmt.pix_mp.height);
+-	f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 *
+-		DIV_ROUND_UP(f->fmt.pix_mp.width, 16) *
+-		DIV_ROUND_UP(f->fmt.pix_mp.height, 16);
++	f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
++	f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height;
++	rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp);
+ }
+ 
+ static int rkvdec_enum_framesizes(struct file *file, void *priv,
+@@ -264,13 +271,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
+ 				       &pix_mp->height,
+ 				       &coded_desc->frmsize);
+ 
+-	v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
+-			    pix_mp->width, pix_mp->height);
+-	pix_mp->plane_fmt[0].sizeimage +=
+-		128 *
+-		DIV_ROUND_UP(pix_mp->width, 16) *
+-		DIV_ROUND_UP(pix_mp->height, 16);
+-	pix_mp->field = V4L2_FIELD_NONE;
++	rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
+ 
+ 	return 0;
+ }
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:37 +0000
+Subject: [PATCH] media: rkvdec: Lock capture pixel format in s_ctrl and s_fmt
+
+Add an optional valid_fmt operation that should return the valid
+pixelformat of CAPTURE buffers.
+
+This is used in next patch to ensure correct pixelformat is used for 10-bit
+and 4:2:2 content.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/rkvdec/rkvdec.c | 67 +++++++++++++++++++++++----
+ drivers/staging/media/rkvdec/rkvdec.h |  2 +
+ 2 files changed, 61 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index 40cc791aef26..e93e1cb0f829 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -38,19 +38,56 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
+ 	pix_mp->field = V4L2_FIELD_NONE;
+ }
+ 
++static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
++{
++	const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc;
++
++	if (coded_desc->ops->valid_fmt)
++		return coded_desc->ops->valid_fmt(ctx, ctrl);
++
++	return ctx->valid_fmt;
++}
++
+ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
+ {
+ 	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
+ 	const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc;
+ 
+-	if (desc->ops->try_ctrl)
+-		return desc->ops->try_ctrl(ctx, ctrl);
++	if (desc->ops->try_ctrl) {
++		int ret;
++		ret = desc->ops->try_ctrl(ctx, ctrl);
++		if (ret)
++			return ret;
++	}
++
++	if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
++		/* Only current valid format */
++		return -EINVAL;
++
++	return 0;
++}
++
++static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
++
++	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) {
++		ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl);
++		if (ctx->valid_fmt) {
++			struct v4l2_pix_format_mplane *pix_mp;
++
++			pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
++			pix_mp->pixelformat = ctx->valid_fmt;
++			rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
++		}
++	}
+ 
+ 	return 0;
+ }
+ 
+ static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
+ 	.try_ctrl = rkvdec_try_ctrl,
++	.s_ctrl = rkvdec_s_ctrl,
+ };
+ 
+ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
+@@ -201,6 +238,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
+ {
+ 	struct v4l2_format *f = &ctx->decoded_fmt;
+ 
++	ctx->valid_fmt = 0;
+ 	rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
+ 	f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+ 	f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
+@@ -256,13 +294,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
+ 	if (WARN_ON(!coded_desc))
+ 		return -EINVAL;
+ 
+-	for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
+-		if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
+-			break;
+-	}
++	if (ctx->valid_fmt) {
++		pix_mp->pixelformat = ctx->valid_fmt;
++	} else {
++		for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
++			if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
++				break;
++		}
+ 
+-	if (i == coded_desc->num_decoded_fmts)
+-		pix_mp->pixelformat = coded_desc->decoded_fmts[0];
++		if (i == coded_desc->num_decoded_fmts)
++			pix_mp->pixelformat = coded_desc->decoded_fmts[0];
++	}
+ 
+ 	/* Always apply the frmsize constraint of the coded end. */
+ 	pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
+@@ -326,6 +368,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv,
+ 		return ret;
+ 
+ 	ctx->decoded_fmt = *f;
++	ctx->valid_fmt = f->fmt.pix_mp.pixelformat;
+ 	return 0;
+ }
+ 
+@@ -429,6 +472,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv,
+ 	if (WARN_ON(!ctx->coded_fmt_desc))
+ 		return -EINVAL;
+ 
++	if (ctx->valid_fmt) {
++		if (f->index)
++			return -EINVAL;
++
++		f->pixelformat = ctx->valid_fmt;
++		return 0;
++	}
++
+ 	if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
+ 		return -EINVAL;
+ 
+diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
+index 633335ebb9c4..b9e219438bc9 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.h
++++ b/drivers/staging/media/rkvdec/rkvdec.h
+@@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
+ struct rkvdec_coded_fmt_ops {
+ 	int (*adjust_fmt)(struct rkvdec_ctx *ctx,
+ 			  struct v4l2_format *f);
++	u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl);
+ 	int (*start)(struct rkvdec_ctx *ctx);
+ 	void (*stop)(struct rkvdec_ctx *ctx);
+ 	int (*run)(struct rkvdec_ctx *ctx);
+@@ -101,6 +102,7 @@ struct rkvdec_ctx {
+ 	struct v4l2_fh fh;
+ 	struct v4l2_format coded_fmt;
+ 	struct v4l2_format decoded_fmt;
++	u32 valid_fmt;
+ 	const struct rkvdec_coded_fmt_desc *coded_fmt_desc;
+ 	struct v4l2_ctrl_handler ctrl_hdl;
+ 	struct rkvdec_dev *dev;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 21:54:37 +0000
+Subject: [PATCH] media: rkvdec: h264: Support High 10 and 4:2:2 profiles
+
+Add support and enable decoding of H264 High 10 and 4:2:2 profiles.
+
+Decoded CAPTURE buffer width is aligned to 64 pixels to accommodate HW
+requirement on 10-bit format buffers.
+
+The new valid_fmt operation is implemented and return a valid pixelformat
+for the provided SPS control.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/rkvdec/rkvdec-h264.c | 33 ++++++++++++++++------
+ drivers/staging/media/rkvdec/rkvdec.c      | 19 +++++++++----
+ 2 files changed, 37 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
+index a8635105e387..0069d3d198db 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
+@@ -1031,19 +1031,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
+ {
+ 	unsigned int width, height;
+ 
+-	/*
+-	 * TODO: The hardware supports 10-bit and 4:2:2 profiles,
+-	 * but it's currently broken in the driver.
+-	 * Reject them for now, until it's fixed.
+-	 */
+-	if (sps->chroma_format_idc > 1)
+-		/* Only 4:0:0 and 4:2:0 are supported */
++	if (sps->chroma_format_idc > 2)
++		/* Only 4:0:0, 4:2:0 and 4:2:2 are supported */
+ 		return -EINVAL;
+ 	if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
+ 		/* Luma and chroma bit depth mismatch */
+ 		return -EINVAL;
+-	if (sps->bit_depth_luma_minus8 != 0)
+-		/* Only 8-bit is supported */
++	if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
++		/* Only 8-bit and 10-bit is supported */
+ 		return -EINVAL;
+ 
+ 	width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
+@@ -1064,6 +1059,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
+ 	return 0;
+ }
+ 
++static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
++{
++	const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
++
++	if (sps->bit_depth_luma_minus8 == 0) {
++		if (sps->chroma_format_idc == 2)
++			return V4L2_PIX_FMT_NV16;
++		else
++			return V4L2_PIX_FMT_NV12;
++	} else if (sps->bit_depth_luma_minus8 == 2) {
++		if (sps->chroma_format_idc == 2)
++			return V4L2_PIX_FMT_NV20;
++		else
++			return V4L2_PIX_FMT_NV15;
++	}
++
++	return 0;
++}
++
+ static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
+ {
+ 	struct rkvdec_dev *rkvdec = ctx->dev;
+@@ -1185,6 +1199,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+ 
+ const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
+ 	.adjust_fmt = rkvdec_h264_adjust_fmt,
++	.valid_fmt = rkvdec_h264_valid_fmt,
+ 	.start = rkvdec_h264_start,
+ 	.stop = rkvdec_h264_stop,
+ 	.run = rkvdec_h264_run,
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index e93e1cb0f829..4f5436c89e08 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
+ 				       struct v4l2_pix_format_mplane *pix_mp)
+ {
+ 	v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
+-			    pix_mp->width, pix_mp->height);
++			    ALIGN(pix_mp->width, 64), pix_mp->height);
+ 	pix_mp->plane_fmt[0].sizeimage += 128 *
+ 		DIV_ROUND_UP(pix_mp->width, 16) *
+ 		DIV_ROUND_UP(pix_mp->height, 16);
+@@ -136,8 +136,11 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
+ 	.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
+ };
+ 
+-static const u32 rkvdec_h264_vp9_decoded_fmts[] = {
++static const u32 rkvdec_h264_decoded_fmts[] = {
+ 	V4L2_PIX_FMT_NV12,
++	V4L2_PIX_FMT_NV15,
++	V4L2_PIX_FMT_NV16,
++	V4L2_PIX_FMT_NV20,
+ };
+ 
+ static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = {
+@@ -160,6 +163,10 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = {
+ 	.num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs),
+ };
+ 
++static const u32 rkvdec_vp9_decoded_fmts[] = {
++	V4L2_PIX_FMT_NV12,
++};
++
+ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 	{
+ 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
+@@ -173,8 +180,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 		},
+ 		.ctrls = &rkvdec_h264_ctrls,
+ 		.ops = &rkvdec_h264_fmt_ops,
+-		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts),
+-		.decoded_fmts = rkvdec_h264_vp9_decoded_fmts,
++		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
++		.decoded_fmts = rkvdec_h264_decoded_fmts,
+ 		.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+ 	},
+ 	{
+@@ -189,8 +196,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 		},
+ 		.ctrls = &rkvdec_vp9_ctrls,
+ 		.ops = &rkvdec_vp9_fmt_ops,
+-		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts),
+-		.decoded_fmts = rkvdec_h264_vp9_decoded_fmts,
++		.num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
++		.decoded_fmts = rkvdec_vp9_decoded_fmts,
+ 	}
+ };
+ 
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 27 Mar 2022 14:18:07 +0200
+Subject: [PATCH] media: rkvdec-h264: Don't hardcode SPS/PPS parameters
+
+Some SPS/PPS parameters are currently hardcoded in the driver
+even though so do exist in the uapi which is stable by now.
+
+Use them instead of hardcoding them.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/staging/media/rkvdec/rkvdec-h264.c | 13 +++++++------
+ 1 file changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
+index 0069d3d198db..2c27acaba85e 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
+@@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
+ 
+ #define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
+ 	/* write sps */
+-	WRITE_PPS(0xf, SEQ_PARAMETER_SET_ID);
+-	WRITE_PPS(0xff, PROFILE_IDC);
+-	WRITE_PPS(1, CONSTRAINT_SET3_FLAG);
++	WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
++	WRITE_PPS(sps->profile_idc, PROFILE_IDC);
++	WRITE_PPS((sps->constraint_set_flags & 1 << 3) ? 1 : 0, CONSTRAINT_SET3_FLAG);
+ 	WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
+ 	WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA);
+ 	WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA);
+-	WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
++	WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS),
++		  QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
+ 	WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
+ 	WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
+ 	WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE);
+@@ -688,8 +689,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
+ 		  DIRECT_8X8_INFERENCE_FLAG);
+ 
+ 	/* write pps */
+-	WRITE_PPS(0xff, PIC_PARAMETER_SET_ID);
+-	WRITE_PPS(0x1f, PPS_SEQ_PARAMETER_SET_ID);
++	WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
++	WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
+ 	WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE),
+ 		  ENTROPY_CODING_MODE_FLAG);
+ 	WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT),
diff --git a/patch/kernel/archive/rockchip64-6.10/general-v4l2-rkvdec-01-vp9.patch b/patch/kernel/archive/rockchip64-6.10/general-v4l2-rkvdec-01-vp9.patch
new file mode 100644
index 000000000000..69d274d591e7
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-v4l2-rkvdec-01-vp9.patch
@@ -0,0 +1,493 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 23 May 2020 10:16:01 +0000
+Subject: [PATCH] WIP: media: rkvdec: pm runtime dont use autosuspend before
+ disable and cleanup
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/rkvdec/rkvdec.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index 4f5436c89e08..eaf2f133a264 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -1125,9 +1125,9 @@ static int rkvdec_remove(struct platform_device *pdev)
+ 
+ 	cancel_delayed_work_sync(&rkvdec->watchdog_work);
+ 
+-	rkvdec_v4l2_cleanup(rkvdec);
+-	pm_runtime_disable(&pdev->dev);
+ 	pm_runtime_dont_use_autosuspend(&pdev->dev);
++	pm_runtime_disable(&pdev->dev);
++	rkvdec_v4l2_cleanup(rkvdec);
+ }
+ 
+ #ifdef CONFIG_PM
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Randy Li <ayaka@soulik.info>
+Date: Sun, 6 Jan 2019 01:48:37 +0800
+Subject: [PATCH] soc: rockchip: power-domain: export idle request
+
+We need to put the power status of HEVC IP into IDLE unless
+we can't reset that IP or the SoC would crash down.
+rockchip_pmu_idle_request(dev, true)---> enter idle
+rockchip_pmu_idle_request(dev, false)---> exit idle
+
+Signed-off-by: Caesar Wang <wxt@rock-chips.com>
+Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
+Signed-off-by: Randy Li <ayaka@soulik.info>
+---
+ drivers/pmdomain/rockchip/pm-domains.c | 23 +++++++++++++++++++++++
+ include/linux/rockchip_pmu.h      | 15 +++++++++++++++
+ include/soc/rockchip/pm_domains.h |  6 ++++++
+ 3 files changed, 44 insertions(+)
+ create mode 100644 include/linux/rockchip_pmu.h
+
+diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
+index 89795abac951..ffb5d62c9d52 100644
+--- a/drivers/pmdomain/rockchip/pm-domains.c
++++ b/drivers/pmdomain/rockchip/pm-domains.c
+@@ -309,6 +309,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
+ 	return 0;
+ }
+ 
++int rockchip_pmu_idle_request(struct device *dev, bool idle)
++{
++	struct generic_pm_domain *genpd;
++	struct rockchip_pm_domain *pd;
++	int ret;
++
++	if (IS_ERR_OR_NULL(dev))
++		return -EINVAL;
++
++	if (IS_ERR_OR_NULL(dev->pm_domain))
++		return -EINVAL;
++
++	genpd = pd_to_genpd(dev->pm_domain);
++	pd = to_rockchip_pd(genpd);
++
++	mutex_lock(&pd->pmu->mutex);
++	ret = rockchip_pmu_set_idle_request(pd, idle);
++	mutex_unlock(&pd->pmu->mutex);
++
++	return ret;
++}
++EXPORT_SYMBOL(rockchip_pmu_idle_request);
++
+ static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
+ {
+ 	int i;
+diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h
+new file mode 100644
+index 000000000000..720b3314e71a
+--- /dev/null
++++ b/include/linux/rockchip_pmu.h
+@@ -0,0 +1,15 @@
++/*
++ * pm_domain.h - Definitions and headers related to device power domains.
++ *
++ * Copyright (C) 2017 Randy Li <ayaka@soulik.info>.
++ *
++ * This file is released under the GPLv2.
++ */
++
++#ifndef _LINUX_ROCKCHIP_PM_H
++#define _LINUX_ROCKCHIP_PM_H
++#include <linux/device.h>
++
++int rockchip_pmu_idle_request(struct device *dev, bool idle);
++
++#endif /* _LINUX_ROCKCHIP_PM_H */
+diff --git a/include/soc/rockchip/pm_domains.h b/include/soc/rockchip/pm_domains.h
+index 7dbd941fc937..c5a59dd71754 100644
+--- a/include/soc/rockchip/pm_domains.h
++++ b/include/soc/rockchip/pm_domains.h
+@@ -10,6 +10,7 @@
+ 
+ int rockchip_pmu_block(void);
+ void rockchip_pmu_unblock(void);
++int rockchip_pmu_idle_request(struct device *dev, bool idle);
+ 
+ #else /* CONFIG_ROCKCHIP_PM_DOMAINS */
+ 
+@@ -20,6 +21,11 @@ static inline int rockchip_pmu_block(void)
+ 
+ static inline void rockchip_pmu_unblock(void) { }
+ 
++static inline int rockchip_pmu_idle_request(struct device *dev, bool idle)
++{
++	return -ENOTSUPP;
++}
++
+ #endif /* CONFIG_ROCKCHIP_PM_DOMAINS */
+ 
+ #endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Wed, 20 May 2020 17:04:47 +0200
+Subject: [PATCH] WIP: media: rkvdec: implement reset controls
+
+---
+ .../bindings/media/rockchip,vdec.yaml         | 19 +++++++
+ drivers/staging/media/rkvdec/rkvdec-regs.h    |  5 ++
+ drivers/staging/media/rkvdec/rkvdec.c         | 53 +++++++++++++++++++
+ drivers/staging/media/rkvdec/rkvdec.h         | 11 +++-
+ 4 files changed, 87 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
+index 3bcfb8e12333..dd6958df1de8 100644
+--- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
+@@ -53,6 +53,18 @@ properties:
+   iommus:
+     maxItems: 1
+ 
++  resets:
++    maxItems: 6
++
++  reset-names:
++    items:
++      - const: video_h
++      - const: video_a
++      - const: video_core
++      - const: video_cabac
++      - const: niu_a
++      - const: niu_h
++
+ required:
+   - compatible
+   - reg
+@@ -60,6 +72,8 @@ required:
+   - clocks
+   - clock-names
+   - power-domains
++  - resets
++  - reset-names
+ 
+ additionalProperties: false
+ 
+@@ -78,6 +92,11 @@ examples:
+         clock-names = "axi", "ahb", "cabac", "core";
+         power-domains = <&power RK3399_PD_VDU>;
+         iommus = <&vdec_mmu>;
++        resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
++                 <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
++                 <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
++        reset-names = "video_h", "video_a", "video_core", "video_cabac",
++                      "niu_a", "niu_h";
+     };
+ 
+ ...
+diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
+index 15b9bee92016..3acc914888f6 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
+@@ -28,6 +28,11 @@
+ #define RKVDEC_SOFTRST_EN_P				BIT(20)
+ #define RKVDEC_FORCE_SOFTRESET_VALID			BIT(21)
+ #define RKVDEC_SOFTRESET_RDY				BIT(22)
++#define RKVDEC_ERR_MASK					(RKVDEC_BUS_STA \
++							 | RKVDEC_ERR_STA \
++							 | RKVDEC_TIMEOUT_STA \
++							 | RKVDEC_BUF_EMPTY_STA \
++							 | RKVDEC_COLMV_REF_ERR_STA )
+ 
+ #define RKVDEC_REG_SYSCTRL				0x008
+ #define RKVDEC_IN_ENDIAN				BIT(0)
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index eaf2f133a264..f55abb7c377f 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -10,12 +10,15 @@
+  */
+ 
+ #include <linux/clk.h>
++#include <linux/delay.h>
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm.h>
+ #include <linux/pm_runtime.h>
++#include <linux/reset.h>
++#include <linux/rockchip_pmu.h>
+ #include <linux/slab.h>
+ #include <linux/videodev2.h>
+ #include <linux/workqueue.h>
+@@ -717,6 +720,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx,
+ 
+ 	pm_runtime_mark_last_busy(rkvdec->dev);
+ 	pm_runtime_put_autosuspend(rkvdec->dev);
++
++	if (result == VB2_BUF_STATE_ERROR &&
++	    rkvdec->reset_mask == RESET_NONE)
++		rkvdec->reset_mask |= RESET_SOFT;
++
+ 	rkvdec_job_finish_no_pm(ctx, result);
+ }
+ 
+@@ -754,6 +762,33 @@ static void rkvdec_device_run(void *priv)
+ 
+ 	if (WARN_ON(!desc))
+ 		return;
++	if (rkvdec->reset_mask != RESET_NONE) {
++
++		if (rkvdec->reset_mask & RESET_SOFT) {
++			writel(RKVDEC_SOFTRST_EN_P,
++			       rkvdec->regs + RKVDEC_REG_INTERRUPT);
++			udelay(RKVDEC_RESET_DELAY);
++			if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT)
++			    & RKVDEC_SOFTRESET_RDY)
++				dev_info_ratelimited(rkvdec->dev,
++						      "softreset failed\n");
++		}
++
++		if (rkvdec->reset_mask & RESET_HARD) {
++			rockchip_pmu_idle_request(rkvdec->dev, true);
++			ret = reset_control_assert(rkvdec->rstc);
++			if (!ret) {
++				udelay(RKVDEC_RESET_DELAY);
++				ret = reset_control_deassert(rkvdec->rstc);
++			}
++			rockchip_pmu_idle_request(rkvdec->dev, false);
++			if (ret)
++				dev_notice_ratelimited(rkvdec->dev,
++							"hardreset failed\n");
++		}
++		rkvdec->reset_mask = RESET_NONE;
++		pm_runtime_suspend(rkvdec->dev);
++	}
+ 
+ 	ret = pm_runtime_resume_and_get(rkvdec->dev);
+ 	if (ret < 0) {
+@@ -1020,6 +1055,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv)
+ 	if (cancel_delayed_work(&rkvdec->watchdog_work)) {
+ 		struct rkvdec_ctx *ctx;
+ 
++		if (state == VB2_BUF_STATE_ERROR) {
++			rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ?
++						RESET_HARD : RESET_SOFT;
++		}
++
+ 		ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
+ 		rkvdec_job_finish(ctx, state);
+ 	}
+@@ -1037,6 +1077,7 @@ static void rkvdec_watchdog_func(struct work_struct *work)
+ 	ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
+ 	if (ctx) {
+ 		dev_err(rkvdec->dev, "Frame processing timed out!\n");
++		rkvdec->reset_mask |= RESET_HARD;
+ 		writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT);
+ 		writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL);
+ 		rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR);
+@@ -1105,6 +1146,18 @@ static int rkvdec_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
++
++	rkvdec->rstc = devm_reset_control_array_get(&pdev->dev, false, true);
++	if (IS_ERR(rkvdec->rstc)) {
++		dev_err(&pdev->dev,
++			"get resets failed %ld\n", PTR_ERR(rkvdec->rstc));
++		return PTR_ERR(rkvdec->rstc);
++	} else {
++		dev_dbg(&pdev->dev,
++			 "requested %d resets\n",
++			 reset_control_get_count(&pdev->dev));
++	}
++
+ 	pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
+ 	pm_runtime_use_autosuspend(&pdev->dev);
+ 	pm_runtime_enable(&pdev->dev);
+diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
+index b9e219438bc9..f02f79c405f0 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.h
++++ b/drivers/staging/media/rkvdec/rkvdec.h
+@@ -11,10 +11,11 @@
+ #ifndef RKVDEC_H_
+ #define RKVDEC_H_
+ 
++#include <linux/clk.h>
+ #include <linux/platform_device.h>
++#include <linux/reset.h>
+ #include <linux/videodev2.h>
+ #include <linux/wait.h>
+-#include <linux/clk.h>
+ 
+ #include <media/v4l2-ctrls.h>
+ #include <media/v4l2-device.h>
+@@ -22,6 +23,12 @@
+ #include <media/videobuf2-core.h>
+ #include <media/videobuf2-dma-contig.h>
+ 
++#define RESET_NONE		0
++#define RESET_SOFT		BIT(0)
++#define RESET_HARD		BIT(1)
++
++#define RKVDEC_RESET_DELAY	5
++
+ struct rkvdec_ctx;
+ 
+ struct rkvdec_ctrl_desc {
+@@ -96,6 +103,8 @@ struct rkvdec_dev {
+ 	void __iomem *regs;
+ 	struct mutex vdev_lock; /* serializes ioctls */
+ 	struct delayed_work watchdog_work;
++	struct reset_control *rstc;
++	u8 reset_mask;
+ };
+ 
+ struct rkvdec_ctx {
+
+@@ -1345,6 +1348,11 @@ vdec: video-codec@ff660000 {
+ 		clock-names = "axi", "ahb", "cabac", "core";
+ 		iommus = <&vdec_mmu>;
+ 		power-domains = <&power RK3399_PD_VDU>;
++		resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
++			 <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
++			 <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
++		reset-names = "video_h", "video_a", "video_core", "video_cabac",
++			       "niu_a", "niu_h";
+ 	};
+ 
+ 	vdec_mmu: iommu@ff660480 {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 21 Aug 2021 16:12:36 +0200
+Subject: [PATCH] media: hantro: rockchip: Increase RK3288's max ACLK
+
+Required to proper decode H.264@4K
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/media/platform/verisilicon/rockchip_vpu_hw.c | 14 +++++++++++---
+ 1 file changed, 11 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+index 8de6fd2e8eef..002b1a600f93 100644
+--- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
++++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+@@ -15,7 +15,8 @@
+ #include "rockchip_vpu2_regs.h"
+ 
+ #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
+-#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
++#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000)
++#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000)
+ #define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000)
+ 
+ #define ROCKCHIP_VPU981_MIN_SIZE 64
+@@ -346,13 +347,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
+ 	return 0;
+ }
+ 
+-static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
++static int rk3288_vpu_hw_init(struct hantro_dev *vpu)
+ {
+ 	/* Bump ACLK to max. possible freq. to improve performance. */
+ 	clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
+ 	return 0;
+ }
+ 
++static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
++{
++	/* Bump ACLK to max. possible freq. to improve performance. */
++	clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ);
++	return 0;
++}
++
+ static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
+ {
+ 	struct hantro_dev *vpu = ctx->dev;
+@@ -592,7 +600,7 @@ const struct hantro_variant rk3288_vpu_variant = {
+ 	.codec_ops = rk3288_vpu_codec_ops,
+ 	.irqs = rockchip_vpu1_irqs,
+ 	.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
+-	.init = rockchip_vpu_hw_init,
++	.init = rk3288_vpu_hw_init,
+ 	.clk_names = rockchip_vpu_clk_names,
+ 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
+ };
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 4 Jul 2021 15:19:44 +0200
+Subject: [PATCH] media: rkvdec: disable QoS for VP9 (corruptions on RK3328
+ otherwise)
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++
+ drivers/staging/media/rkvdec/rkvdec-vp9.c  | 8 ++++++++
+ 2 files changed, 10 insertions(+)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
+index 3acc914888f6..265f5234f4eb 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
+@@ -222,6 +222,8 @@
+ #define RKVDEC_REG_H264_ERR_E				0x134
+ #define RKVDEC_H264_ERR_EN_HIGHBITS(x)			((x) & 0x3fffffff)
+ 
++#define RKVDEC_QOS_CTRL					0x18C
++
+ #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND		0x410
+ #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND		0x450
+ 
+diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c
+index d8c1c0db15c7..a289bc968e91 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-vp9.c
++++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c
+@@ -802,6 +802,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
+ 	struct rkvdec_dev *rkvdec = ctx->dev;
+ 	struct rkvdec_vp9_run run = { };
+ 	int ret;
++	u32 reg;
+ 
+ 	ret = rkvdec_vp9_run_preamble(ctx, &run);
+ 	if (ret) {
+@@ -823,6 +824,13 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
+ 	writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
+ 
+ 	writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
++
++	/* disable QOS for RK3328 - no effect on other SoCs */
++	reg = readl(rkvdec->regs + RKVDEC_QOS_CTRL);
++	reg |= 0xFFFF;
++	reg &= (~BIT(12));
++	writel(reg, rkvdec->regs + RKVDEC_QOS_CTRL);
++
+ 	/* Start decoding! */
+ 	writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
+ 	       RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Thu, 16 Jun 2022 13:18:22 +0200
+Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3328
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 5519347232f6..431c4ec198be 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -674,6 +674,11 @@ vdec: video-codec@ff360000 {
+ 		assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
+ 				  <&cru SCLK_VDEC_CORE>;
+ 		assigned-clock-rates = <400000000>, <400000000>, <300000000>;
++		resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>,
++			 <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>,
++			 <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>;
++		reset-names = "video_h", "video_a", "video_core", "video_cabac",
++			       "niu_a", "niu_h";
+ 		iommus = <&vdec_mmu>;
+ 		power-domains = <&power RK3328_PD_VIDEO>;
+ 	};
diff --git a/patch/kernel/archive/rockchip64-6.10/general-v4l2-rkvdec-02-hevc.patch b/patch/kernel/archive/rockchip64-6.10/general-v4l2-rkvdec-02-hevc.patch
new file mode 100644
index 000000000000..58b3e72e5a27
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-v4l2-rkvdec-02-hevc.patch
@@ -0,0 +1,3226 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 23 May 2020 15:17:45 +0000
+Subject: [PATCH] WIP: media: rkvdec: add HEVC backend
+
+NOTE: cabac table and scailing list code is copied 1:1 from mpp
+TODO: fix lowdelay flag and rework the scaling list part
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/staging/media/rkvdec/Makefile      |    2 +-
+ drivers/staging/media/rkvdec/rkvdec-hevc.c | 2572 ++++++++++++++++++++
+ drivers/staging/media/rkvdec/rkvdec-regs.h |    1 +
+ drivers/staging/media/rkvdec/rkvdec.c      |   73 +-
+ drivers/staging/media/rkvdec/rkvdec.h      |    1 +
+ 5 files changed, 2647 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
+
+diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
+index cb86b429cfaa..a77122641d14 100644
+--- a/drivers/staging/media/rkvdec/Makefile
++++ b/drivers/staging/media/rkvdec/Makefile
+@@ -1,3 +1,3 @@
+ obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o
+ 
+-rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
++rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
+diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+new file mode 100644
+index 000000000000..7a375a23eaf1
+--- /dev/null
++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+@@ -0,0 +1,2572 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Rockchip Video Decoder HEVC backend
++ *
++ * Copyright (C) 2019 Collabora, Ltd.
++ *	Boris Brezillon <boris.brezillon@collabora.com>
++ *
++ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
++ *	Jeffy Chen <jeffy.chen@rock-chips.com>
++ */
++
++#include <media/v4l2-mem2mem.h>
++
++#include "rkvdec.h"
++#include "rkvdec-regs.h"
++
++/* Size in u8/u32 units. */
++#define RKV_CABAC_TABLE_SIZE		27456
++#define RKV_SCALING_LIST_SIZE		1360
++#define RKV_PPS_SIZE			(80 / 4)
++#define RKV_PPS_LEN			64
++#define RKV_RPS_SIZE			(32 / 4)
++#define RKV_RPS_LEN			600
++
++struct rkvdec_sps_pps_packet {
++	u32 info[RKV_PPS_SIZE];
++};
++
++struct rkvdec_rps_packet {
++	u32 info[RKV_RPS_SIZE];
++};
++
++struct rkvdec_ps_field {
++	u16 offset;
++	u8 len;
++};
++
++#define PS_FIELD(_offset, _len) \
++	((struct rkvdec_ps_field){ _offset, _len })
++
++/* SPS */
++#define VIDEO_PARAMETER_SET_ID				PS_FIELD(0, 4)
++#define SEQ_PARAMETER_SET_ID				PS_FIELD(4, 4)
++#define CHROMA_FORMAT_IDC				PS_FIELD(8, 2)
++#define PIC_WIDTH_IN_LUMA_SAMPLES			PS_FIELD(10, 13)
++#define PIC_HEIGHT_IN_LUMA_SAMPLES			PS_FIELD(23, 13)
++#define BIT_DEPTH_LUMA					PS_FIELD(36, 4)
++#define BIT_DEPTH_CHROMA				PS_FIELD(40, 4)
++#define LOG2_MAX_PIC_ORDER_CNT_LSB			PS_FIELD(44, 5)
++#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE	PS_FIELD(49, 2)
++#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE			PS_FIELD(51, 3)
++#define LOG2_MIN_TRANSFORM_BLOCK_SIZE			PS_FIELD(54, 3)
++#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE	PS_FIELD(57, 2)
++#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER		PS_FIELD(59, 3)
++#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA		PS_FIELD(62, 3)
++#define SCALING_LIST_ENABLED_FLAG			PS_FIELD(65, 1)
++#define AMP_ENABLED_FLAG				PS_FIELD(66, 1)
++#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG		PS_FIELD(67, 1)
++#define PCM_ENABLED_FLAG				PS_FIELD(68, 1)
++#define PCM_SAMPLE_BIT_DEPTH_LUMA			PS_FIELD(69, 4)
++#define PCM_SAMPLE_BIT_DEPTH_CHROMA			PS_FIELD(73, 4)
++#define PCM_LOOP_FILTER_DISABLED_FLAG			PS_FIELD(77, 1)
++#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE	PS_FIELD(78, 3)
++#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE		PS_FIELD(81, 3)
++#define NUM_SHORT_TERM_REF_PIC_SETS			PS_FIELD(84, 7)
++#define LONG_TERM_REF_PICS_PRESENT_FLAG			PS_FIELD(91, 1)
++#define NUM_LONG_TERM_REF_PICS_SPS			PS_FIELD(92, 6)
++#define SPS_TEMPORAL_MVP_ENABLED_FLAG			PS_FIELD(98, 1)
++#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG		PS_FIELD(99, 1)
++/* PPS */
++#define PIC_PARAMETER_SET_ID				PS_FIELD(128, 6)
++#define PPS_SEQ_PARAMETER_SET_ID			PS_FIELD(134, 4)
++#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG		PS_FIELD(138, 1)
++#define OUTPUT_FLAG_PRESENT_FLAG			PS_FIELD(139, 1)
++#define NUM_EXTRA_SLICE_HEADER_BITS			PS_FIELD(140, 13)
++#define SIGN_DATA_HIDING_ENABLED_FLAG			PS_FIELD(153, 1)
++#define CABAC_INIT_PRESENT_FLAG				PS_FIELD(154, 1)
++#define NUM_REF_IDX_L0_DEFAULT_ACTIVE			PS_FIELD(155, 4)
++#define NUM_REF_IDX_L1_DEFAULT_ACTIVE			PS_FIELD(159, 4)
++#define INIT_QP_MINUS26					PS_FIELD(163, 7)
++#define CONSTRAINED_INTRA_PRED_FLAG			PS_FIELD(170, 1)
++#define TRANSFORM_SKIP_ENABLED_FLAG			PS_FIELD(171, 1)
++#define CU_QP_DELTA_ENABLED_FLAG			PS_FIELD(172, 1)
++#define LOG2_MIN_CU_QP_DELTA_SIZE			PS_FIELD(173, 3)
++#define PPS_CB_QP_OFFSET				PS_FIELD(176, 5)
++#define PPS_CR_QP_OFFSET				PS_FIELD(181, 5)
++#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG	PS_FIELD(186, 1)
++#define WEIGHTED_PRED_FLAG				PS_FIELD(187, 1)
++#define WEIGHTED_BIPRED_FLAG				PS_FIELD(188, 1)
++#define TRANSQUANT_BYPASS_ENABLED_FLAG			PS_FIELD(189, 1)
++#define TILES_ENABLED_FLAG				PS_FIELD(190, 1)
++#define ENTROPY_CODING_SYNC_ENABLED_FLAG		PS_FIELD(191, 1)
++#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG	PS_FIELD(192, 1)
++#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG		PS_FIELD(193, 1)
++#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG		PS_FIELD(194, 1)
++#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG		PS_FIELD(195, 1)
++#define PPS_BETA_OFFSET_DIV2				PS_FIELD(196, 4)
++#define PPS_TC_OFFSET_DIV2				PS_FIELD(200, 4)
++#define LISTS_MODIFICATION_PRESENT_FLAG			PS_FIELD(204, 1)
++#define LOG2_PARALLEL_MERGE_LEVEL			PS_FIELD(205, 3)
++#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG	PS_FIELD(208, 1)
++#define NUM_TILE_COLUMNS				PS_FIELD(212, 5)
++#define NUM_TILE_ROWS					PS_FIELD(217, 5)
++#define COLUMN_WIDTH(i)					PS_FIELD(256 + (i * 8), 8)
++#define ROW_HEIGHT(i)					PS_FIELD(416 + (i * 8), 8)
++#define SCALING_LIST_ADDRESS				PS_FIELD(592, 32)
++
++/* Data structure describing auxiliary buffer format. */
++struct rkvdec_hevc_priv_tbl {
++	u8 cabac_table[RKV_CABAC_TABLE_SIZE];
++	u8 scaling_list[RKV_SCALING_LIST_SIZE];
++	struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
++	struct rkvdec_rps_packet rps[RKV_RPS_LEN];
++};
++
++struct rkvdec_hevc_run {
++	struct rkvdec_run base;
++	const struct v4l2_ctrl_hevc_slice_params *slices_params;
++	const struct v4l2_ctrl_hevc_decode_params *decode_params;
++	const struct v4l2_ctrl_hevc_sps *sps;
++	const struct v4l2_ctrl_hevc_pps *pps;
++	const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
++	int num_slices;
++};
++
++struct rkvdec_hevc_ctx {
++	struct rkvdec_aux_buf priv_tbl;
++	struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
++};
++
++// TODO: refactor scaling list code, was copied 1:1 from mpp
++
++typedef struct ScalingList {
++    /* This is a little wasteful, since sizeID 0 only needs 8 coeffs,
++     * and size ID 3 only has 2 arrays, not 6. */
++    u8 sl[4][6][64];
++    u8 sl_dc[2][6];
++} scalingList_t;
++
++typedef struct ScalingFactor_Model {
++    u8 scalingfactor0[1248];
++    u8 scalingfactor1[96];     /*4X4 TU Rotate, total 16X4*/
++    u8 scalingdc[12];          /*N1005 Vienna Meeting*/
++    u8 reserverd[4];           /*16Bytes align*/
++} scalingFactor_t;
++
++#define SCALING_LIST_SIZE_NUM 4
++
++static void
++hal_record_scaling_list(scalingFactor_t *pScalingFactor_out,
++                        scalingList_t *pScalingList)
++{
++    int i;
++    u32 g_scalingListNum_model[SCALING_LIST_SIZE_NUM] = {6, 6, 6, 2}; // from C Model
++    u32 nIndex = 0;
++    u32 sizeId, matrixId, listId;
++    u8 *p = pScalingFactor_out->scalingfactor0;
++    u8 tmpBuf[8 * 8];
++
++    //output non-default scalingFactor Table (1248 BYTES)
++    for (sizeId = 0; sizeId < SCALING_LIST_SIZE_NUM; sizeId++) {
++        for (listId = 0; listId < g_scalingListNum_model[sizeId]; listId++) {
++            if (sizeId < 3) {
++                for (i = 0; i < (sizeId == 0 ? 16 : 64); i++) {
++                    pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i];
++                }
++            } else {
++                for (i = 0; i < 64; i ++) {
++                    pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i];
++                }
++                for (i = 0; i < 128; i ++) {
++                    pScalingFactor_out->scalingfactor0[nIndex++] = 0;
++                }
++            }
++        }
++    }
++    //output non-default scalingFactor Table Rotation(96 Bytes)
++    nIndex = 0;
++    for (listId = 0; listId < g_scalingListNum_model[0]; listId++) {
++        u8 temp16[16] = {0};
++        for (i = 0; i < 16; i ++) {
++            temp16[i] = (u8)pScalingList->sl[0][listId][i];
++        }
++        for (i = 0; i < 4; i ++) {
++            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i];
++            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 4];
++            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 8];
++            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 12];
++        }
++    }
++    //output non-default ScalingList_DC_Coeff (12 BYTES)
++    nIndex = 0;
++    for (listId = 0; listId < g_scalingListNum_model[2]; listId++) { //sizeId = 2
++        pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[0][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC
++    }
++    for (listId = 0; listId < g_scalingListNum_model[3]; listId++) { //sizeId = 3
++        pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[1][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC
++        pScalingFactor_out->scalingdc[nIndex++] = 0;
++        pScalingFactor_out->scalingdc[nIndex++] = 0;
++    }
++
++    //align 16X address
++    nIndex = 0;
++    for (i = 0; i < 4; i ++) {
++        pScalingFactor_out->reserverd[nIndex++] = 0;
++    }
++
++    //----------------------All above code show the normal store way in HM--------------------------
++    //--------from now on, the scalingfactor0 is rotated 90', the scalingfactor1 is also rotated 90'
++
++    //sizeId == 0
++    for (matrixId = 0; matrixId < 6; matrixId++) {
++        p = pScalingFactor_out->scalingfactor0 + matrixId * 16;
++
++        for (i = 0; i < 4; i++) {
++            tmpBuf[4 * 0 + i] = p[i * 4 + 0];
++            tmpBuf[4 * 1 + i] = p[i * 4 + 1];
++            tmpBuf[4 * 2 + i] = p[i * 4 + 2];
++            tmpBuf[4 * 3 + i] = p[i * 4 + 3];
++        }
++        memcpy(p, tmpBuf, 4 * 4 * sizeof(u8));
++    }
++    //sizeId == 1
++    for (matrixId = 0; matrixId < 6; matrixId++) {
++        p = pScalingFactor_out->scalingfactor0 + 6 * 16 + matrixId * 64;
++
++        for (i = 0; i < 8; i++) {
++            tmpBuf[8 * 0 + i] = p[i * 8 + 0];
++            tmpBuf[8 * 1 + i] = p[i * 8 + 1];
++            tmpBuf[8 * 2 + i] = p[i * 8 + 2];
++            tmpBuf[8 * 3 + i] = p[i * 8 + 3];
++            tmpBuf[8 * 4 + i] = p[i * 8 + 4];
++            tmpBuf[8 * 5 + i] = p[i * 8 + 5];
++            tmpBuf[8 * 6 + i] = p[i * 8 + 6];
++            tmpBuf[8 * 7 + i] = p[i * 8 + 7];
++        }
++        memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
++    }
++    //sizeId == 2
++    for (matrixId = 0; matrixId < 6; matrixId++) {
++        p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + matrixId * 64;
++
++        for (i = 0; i < 8; i++) {
++            tmpBuf[8 * 0 + i] = p[i * 8 + 0];
++            tmpBuf[8 * 1 + i] = p[i * 8 + 1];
++            tmpBuf[8 * 2 + i] = p[i * 8 + 2];
++            tmpBuf[8 * 3 + i] = p[i * 8 + 3];
++            tmpBuf[8 * 4 + i] = p[i * 8 + 4];
++            tmpBuf[8 * 5 + i] = p[i * 8 + 5];
++            tmpBuf[8 * 6 + i] = p[i * 8 + 6];
++            tmpBuf[8 * 7 + i] = p[i * 8 + 7];
++        }
++        memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
++    }
++    //sizeId == 3
++    for (matrixId = 0; matrixId < 6; matrixId++) {
++        p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + 6 * 64 + matrixId * 64;
++
++        for (i = 0; i < 8; i++) {
++            tmpBuf[8 * 0 + i] = p[i * 8 + 0];
++            tmpBuf[8 * 1 + i] = p[i * 8 + 1];
++            tmpBuf[8 * 2 + i] = p[i * 8 + 2];
++            tmpBuf[8 * 3 + i] = p[i * 8 + 3];
++            tmpBuf[8 * 4 + i] = p[i * 8 + 4];
++            tmpBuf[8 * 5 + i] = p[i * 8 + 5];
++            tmpBuf[8 * 6 + i] = p[i * 8 + 6];
++            tmpBuf[8 * 7 + i] = p[i * 8 + 7];
++        }
++        memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
++    }
++
++    //sizeId == 0
++    for (matrixId = 0; matrixId < 6; matrixId++) {
++        p = pScalingFactor_out->scalingfactor1 + matrixId * 16;
++
++        for (i = 0; i < 4; i++) {
++            tmpBuf[4 * 0 + i] = p[i * 4 + 0];
++            tmpBuf[4 * 1 + i] = p[i * 4 + 1];
++            tmpBuf[4 * 2 + i] = p[i * 4 + 2];
++            tmpBuf[4 * 3 + i] = p[i * 4 + 3];
++        }
++        memcpy(p, tmpBuf, 4 * 4 * sizeof(u8));
++    }
++}
++
++static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = {
++    0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x68,
++    0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x68,
++    0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, 0x60, 0x50, 0x58,
++    0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, 0x60, 0x60,
++    0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68,
++    0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, 0x50, 0x50, 0x50, 0x48, 0x58, 0x58,
++    0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50,
++    0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40,
++    0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f,
++    0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0f, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66,
++    0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67,
++    0x57, 0x5e, 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57,
++    0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f,
++    0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66,
++    0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, 0x57, 0x57,
++    0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x4f,
++    0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, 0x47, 0x67, 0x40, 0x40,
++    0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, 0x4e, 0x47, 0x47, 0x00, 0x0f,
++    0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64,
++    0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66,
++    0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56,
++    0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e,
++    0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64,
++    0x45, 0x48, 0x20, 0x57, 0x66, 0x66, 0x56, 0x5e, 0x5e, 0x5d, 0x4e, 0x4e, 0x4e, 0x46, 0x56, 0x57,
++    0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f,
++    0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x66, 0x10, 0x47, 0x66, 0x40, 0x40,
++    0x4f, 0x4d, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x03, 0x27, 0x4d, 0x47, 0x46, 0x01, 0x0f,
++    0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x34, 0x01, 0x26, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0d, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x62,
++    0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x65,
++    0x57, 0x5c, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5d, 0x5d, 0x4e, 0x56,
++    0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62, 0x5d, 0x5d,
++    0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62,
++    0x44, 0x48, 0x20, 0x57, 0x65, 0x65, 0x56, 0x5d, 0x5d, 0x5c, 0x4e, 0x4d, 0x4e, 0x45, 0x56, 0x57,
++    0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f,
++    0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x65, 0x10, 0x47, 0x65, 0x40, 0x40,
++    0x4f, 0x4c, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x04, 0x27, 0x4c, 0x47, 0x45, 0x01, 0x0f,
++    0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x33, 0x01, 0x25, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0c, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0d, 0x40, 0x40, 0x40, 0x0d, 0x60,
++    0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x64,
++    0x56, 0x5b, 0x01, 0x1d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5c, 0x5c, 0x4d, 0x55,
++    0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60, 0x5c, 0x5c,
++    0x4d, 0x55, 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60,
++    0x43, 0x49, 0x21, 0x56, 0x64, 0x64, 0x55, 0x5c, 0x5c, 0x5b, 0x4d, 0x4c, 0x4d, 0x44, 0x55, 0x56,
++    0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x4e,
++    0x46, 0x1d, 0x1d, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x64, 0x11, 0x46, 0x64, 0x40, 0x40,
++    0x4e, 0x4b, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x06, 0x27, 0x4b, 0x46, 0x44, 0x02, 0x0f,
++    0x4e, 0x35, 0x1e, 0x1d, 0x4e, 0x31, 0x02, 0x24, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0b, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5e,
++    0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x63,
++    0x56, 0x59, 0x01, 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5b, 0x5b, 0x4c, 0x54,
++    0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e, 0x5b, 0x5b,
++    0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e,
++    0x41, 0x49, 0x21, 0x56, 0x63, 0x63, 0x54, 0x5b, 0x5b, 0x59, 0x4c, 0x4b, 0x4c, 0x43, 0x54, 0x56,
++    0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e,
++    0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x63, 0x11, 0x46, 0x63, 0x40, 0x40,
++    0x4e, 0x49, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x07, 0x27, 0x49, 0x46, 0x43, 0x03, 0x0f,
++    0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x30, 0x03, 0x23, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x0a, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5c,
++    0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x62,
++    0x56, 0x58, 0x01, 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5a, 0x5a, 0x4c, 0x54,
++    0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c, 0x5a, 0x5a,
++    0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c,
++    0x40, 0x49, 0x21, 0x56, 0x62, 0x62, 0x54, 0x5a, 0x5a, 0x58, 0x4c, 0x4a, 0x4c, 0x42, 0x54, 0x56,
++    0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e,
++    0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x62, 0x11, 0x46, 0x62, 0x40, 0x40,
++    0x4e, 0x48, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x09, 0x27, 0x48, 0x46, 0x42, 0x03, 0x0f,
++    0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x2e, 0x03, 0x22, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x09, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0b, 0x40, 0x40, 0x40, 0x0b, 0x5a,
++    0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x61,
++    0x55, 0x57, 0x02, 0x1b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x59, 0x59, 0x4b, 0x53,
++    0x4d, 0x07, 0x53, 0x63, 0x4d, 0x51, 0x61, 0x65, 0x63, 0x61, 0x5d, 0x49, 0x43, 0x5a, 0x59, 0x59,
++    0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x51, 0x61, 0x65, 0x63, 0x61, 0x5d, 0x49, 0x43, 0x5a,
++    0x00, 0x4a, 0x22, 0x55, 0x61, 0x61, 0x53, 0x59, 0x59, 0x57, 0x4b, 0x49, 0x4b, 0x41, 0x53, 0x55,
++    0x33, 0x07, 0x53, 0x41, 0x53, 0x55, 0x33, 0x07, 0x53, 0x41, 0x53, 0x55, 0x33, 0x07, 0x53, 0x4d,
++    0x45, 0x1b, 0x1b, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x61, 0x12, 0x45, 0x61, 0x40, 0x40,
++    0x4d, 0x47, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0a, 0x27, 0x47, 0x45, 0x41, 0x04, 0x0f,
++    0x4d, 0x33, 0x1d, 0x1b, 0x4d, 0x2d, 0x04, 0x21, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x08, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, 0x40, 0x40, 0x40, 0x0a, 0x59,
++    0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x60,
++    0x55, 0x56, 0x02, 0x1a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x58, 0x58, 0x4b, 0x53,
++    0x4d, 0x07, 0x53, 0x63, 0x4d, 0x50, 0x60, 0x65, 0x63, 0x60, 0x5b, 0x48, 0x43, 0x59, 0x58, 0x58,
++    0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x50, 0x60, 0x65, 0x63, 0x60, 0x5b, 0x48, 0x43, 0x59,
++    0x01, 0x4a, 0x22, 0x55, 0x60, 0x60, 0x53, 0x58, 0x58, 0x56, 0x4b, 0x48, 0x4b, 0x40, 0x53, 0x55,
++    0x32, 0x07, 0x53, 0x40, 0x53, 0x55, 0x32, 0x07, 0x53, 0x40, 0x53, 0x55, 0x32, 0x07, 0x53, 0x4d,
++    0x45, 0x1a, 0x1a, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x60, 0x12, 0x45, 0x60, 0x40, 0x40,
++    0x4d, 0x46, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0c, 0x27, 0x46, 0x45, 0x40, 0x04, 0x0f,
++    0x4d, 0x32, 0x1d, 0x1a, 0x4d, 0x2b, 0x04, 0x20, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x07, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, 0x40, 0x40, 0x40, 0x0a, 0x57,
++    0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x5f,
++    0x55, 0x54, 0x02, 0x1a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x57, 0x57, 0x4a, 0x52,
++    0x4d, 0x07, 0x52, 0x62, 0x4d, 0x4f, 0x5f, 0x65, 0x62, 0x5f, 0x59, 0x47, 0x42, 0x57, 0x57, 0x57,
++    0x4a, 0x52, 0x4d, 0x07, 0x52, 0x62, 0x4d, 0x4f, 0x5f, 0x65, 0x62, 0x5f, 0x59, 0x47, 0x42, 0x57,
++    0x03, 0x4a, 0x22, 0x55, 0x5f, 0x5f, 0x52, 0x57, 0x57, 0x54, 0x4a, 0x47, 0x4a, 0x00, 0x52, 0x55,
++    0x32, 0x07, 0x52, 0x00, 0x52, 0x55, 0x32, 0x07, 0x52, 0x00, 0x52, 0x55, 0x32, 0x07, 0x52, 0x4d,
++    0x45, 0x1a, 0x1a, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x5f, 0x12, 0x45, 0x5f, 0x40, 0x40,
++    0x4d, 0x44, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0e, 0x27, 0x44, 0x45, 0x00, 0x05, 0x0f,
++    0x4d, 0x32, 0x1d, 0x1a, 0x4d, 0x29, 0x05, 0x1f, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x06, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x09, 0x40, 0x40, 0x40, 0x09, 0x55,
++    0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5e,
++    0x54, 0x53, 0x03, 0x19, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x56, 0x56, 0x49, 0x51,
++    0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4e, 0x5e, 0x64, 0x61, 0x5e, 0x58, 0x46, 0x41, 0x55, 0x56, 0x56,
++    0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4e, 0x5e, 0x64, 0x61, 0x5e, 0x58, 0x46, 0x41, 0x55,
++    0x04, 0x4b, 0x23, 0x54, 0x5e, 0x5e, 0x51, 0x56, 0x56, 0x53, 0x49, 0x46, 0x49, 0x01, 0x51, 0x54,
++    0x31, 0x07, 0x51, 0x01, 0x51, 0x54, 0x31, 0x07, 0x51, 0x01, 0x51, 0x54, 0x31, 0x07, 0x51, 0x4c,
++    0x44, 0x19, 0x19, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5e, 0x13, 0x44, 0x5e, 0x40, 0x40,
++    0x4c, 0x43, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x0f, 0x27, 0x43, 0x44, 0x01, 0x06, 0x0f,
++    0x4c, 0x31, 0x1c, 0x19, 0x4c, 0x28, 0x06, 0x1e, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x05, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x09, 0x40, 0x40, 0x40, 0x09, 0x53,
++    0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5d,
++    0x54, 0x52, 0x03, 0x19, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x55, 0x55, 0x49, 0x51,
++    0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4d, 0x5d, 0x64, 0x61, 0x5d, 0x56, 0x45, 0x41, 0x53, 0x55, 0x55,
++    0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4d, 0x5d, 0x64, 0x61, 0x5d, 0x56, 0x45, 0x41, 0x53,
++    0x05, 0x4b, 0x23, 0x54, 0x5d, 0x5d, 0x51, 0x55, 0x55, 0x52, 0x49, 0x45, 0x49, 0x02, 0x51, 0x54,
++    0x31, 0x07, 0x51, 0x02, 0x51, 0x54, 0x31, 0x07, 0x51, 0x02, 0x51, 0x54, 0x31, 0x07, 0x51, 0x4c,
++    0x44, 0x19, 0x19, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5d, 0x13, 0x44, 0x5d, 0x40, 0x40,
++    0x4c, 0x42, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x11, 0x27, 0x42, 0x44, 0x02, 0x06, 0x0f,
++    0x4c, 0x31, 0x1c, 0x19, 0x4c, 0x26, 0x06, 0x1d, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x04, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x08, 0x40, 0x40, 0x40, 0x08, 0x51,
++    0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5c,
++    0x54, 0x51, 0x03, 0x18, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x54, 0x54, 0x48, 0x50,
++    0x4c, 0x07, 0x50, 0x60, 0x4c, 0x4c, 0x5c, 0x64, 0x60, 0x5c, 0x55, 0x44, 0x40, 0x51, 0x54, 0x54,
++    0x48, 0x50, 0x4c, 0x07, 0x50, 0x60, 0x4c, 0x4c, 0x5c, 0x64, 0x60, 0x5c, 0x55, 0x44, 0x40, 0x51,
++    0x06, 0x4b, 0x23, 0x54, 0x5c, 0x5c, 0x50, 0x54, 0x54, 0x51, 0x48, 0x44, 0x48, 0x03, 0x50, 0x54,
++    0x30, 0x07, 0x50, 0x03, 0x50, 0x54, 0x30, 0x07, 0x50, 0x03, 0x50, 0x54, 0x30, 0x07, 0x50, 0x4c,
++    0x44, 0x18, 0x18, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5c, 0x13, 0x44, 0x5c, 0x40, 0x40,
++    0x4c, 0x41, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x12, 0x27, 0x41, 0x44, 0x03, 0x07, 0x0f,
++    0x4c, 0x30, 0x1c, 0x18, 0x4c, 0x25, 0x07, 0x1c, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x03, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x07, 0x4f,
++    0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x5b,
++    0x53, 0x4f, 0x04, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x53, 0x53, 0x47, 0x4f,
++    0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4b, 0x5b, 0x63, 0x5f, 0x5b, 0x53, 0x43, 0x00, 0x4f, 0x53, 0x53,
++    0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4b, 0x5b, 0x63, 0x5f, 0x5b, 0x53, 0x43, 0x00, 0x4f,
++    0x08, 0x4c, 0x24, 0x53, 0x5b, 0x5b, 0x4f, 0x53, 0x53, 0x4f, 0x47, 0x43, 0x47, 0x04, 0x4f, 0x53,
++    0x2f, 0x07, 0x4f, 0x04, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x04, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x4b,
++    0x43, 0x17, 0x17, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x5b, 0x14, 0x43, 0x5b, 0x40, 0x40,
++    0x4b, 0x00, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x14, 0x27, 0x00, 0x43, 0x04, 0x08, 0x0f,
++    0x4b, 0x2f, 0x1b, 0x17, 0x4b, 0x23, 0x08, 0x1b, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x02, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x07, 0x4d,
++    0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x5a,
++    0x53, 0x4e, 0x04, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x52, 0x52, 0x47, 0x4f,
++    0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4a, 0x5a, 0x63, 0x5f, 0x5a, 0x52, 0x42, 0x00, 0x4d, 0x52, 0x52,
++    0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4a, 0x5a, 0x63, 0x5f, 0x5a, 0x52, 0x42, 0x00, 0x4d,
++    0x09, 0x4c, 0x24, 0x53, 0x5a, 0x5a, 0x4f, 0x52, 0x52, 0x4e, 0x47, 0x42, 0x47, 0x05, 0x4f, 0x53,
++    0x2f, 0x07, 0x4f, 0x05, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x05, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x4b,
++    0x43, 0x17, 0x17, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x5a, 0x14, 0x43, 0x5a, 0x40, 0x40,
++    0x4b, 0x01, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x15, 0x27, 0x01, 0x43, 0x05, 0x08, 0x0f,
++    0x4b, 0x2f, 0x1b, 0x17, 0x4b, 0x22, 0x08, 0x1a, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x01, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x40, 0x40, 0x40, 0x06, 0x4b,
++    0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x59,
++    0x53, 0x4d, 0x04, 0x16, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x51, 0x51, 0x46, 0x4e,
++    0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x50, 0x41, 0x01, 0x4b, 0x51, 0x51,
++    0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x50, 0x41, 0x01, 0x4b,
++    0x0a, 0x4c, 0x24, 0x53, 0x59, 0x59, 0x4e, 0x51, 0x51, 0x4d, 0x46, 0x41, 0x46, 0x06, 0x4e, 0x53,
++    0x2e, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, 0x4b,
++    0x43, 0x16, 0x16, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x59, 0x14, 0x43, 0x59, 0x40, 0x40,
++    0x4b, 0x02, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x17, 0x27, 0x02, 0x43, 0x06, 0x09, 0x0f,
++    0x4b, 0x2e, 0x1b, 0x16, 0x4b, 0x20, 0x09, 0x19, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x00, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x05, 0x4a,
++    0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x59,
++    0x53, 0x4c, 0x04, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x51, 0x51, 0x46, 0x4e,
++    0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x4f, 0x41, 0x01, 0x4a, 0x51, 0x51,
++    0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x4f, 0x41, 0x01, 0x4a,
++    0x0b, 0x4d, 0x24, 0x53, 0x59, 0x59, 0x4e, 0x51, 0x51, 0x4c, 0x46, 0x41, 0x46, 0x06, 0x4e, 0x53,
++    0x2d, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2d, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2d, 0x07, 0x4e, 0x4b,
++    0x43, 0x15, 0x15, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x59, 0x14, 0x43, 0x59, 0x40, 0x40,
++    0x4b, 0x03, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x18, 0x27, 0x03, 0x43, 0x06, 0x09, 0x0f,
++    0x4b, 0x2d, 0x1a, 0x15, 0x4b, 0x1e, 0x09, 0x18, 0x04, 0x07, 0x14, 0x12, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x00, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x05, 0x48,
++    0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x58,
++    0x52, 0x4a, 0x05, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x50, 0x50, 0x45, 0x4d,
++    0x4a, 0x07, 0x4d, 0x5d, 0x4a, 0x48, 0x58, 0x62, 0x5d, 0x58, 0x4d, 0x40, 0x02, 0x48, 0x50, 0x50,
++    0x45, 0x4d, 0x4a, 0x07, 0x4d, 0x5d, 0x4a, 0x48, 0x58, 0x62, 0x5d, 0x58, 0x4d, 0x40, 0x02, 0x48,
++    0x0d, 0x4d, 0x25, 0x52, 0x58, 0x58, 0x4d, 0x50, 0x50, 0x4a, 0x45, 0x40, 0x45, 0x07, 0x4d, 0x52,
++    0x2d, 0x07, 0x4d, 0x07, 0x4d, 0x52, 0x2d, 0x07, 0x4d, 0x07, 0x4d, 0x52, 0x2d, 0x07, 0x4d, 0x4a,
++    0x42, 0x15, 0x15, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x58, 0x15, 0x42, 0x58, 0x40, 0x40,
++    0x4a, 0x05, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1a, 0x27, 0x05, 0x42, 0x07, 0x0a, 0x0f,
++    0x4a, 0x2d, 0x1a, 0x15, 0x4a, 0x1d, 0x0a, 0x18, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x40, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x40, 0x40, 0x40, 0x04, 0x46,
++    0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x57,
++    0x52, 0x49, 0x05, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4f, 0x4f, 0x44, 0x4c,
++    0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x47, 0x57, 0x62, 0x5c, 0x57, 0x4b, 0x00, 0x03, 0x46, 0x4f, 0x4f,
++    0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x47, 0x57, 0x62, 0x5c, 0x57, 0x4b, 0x00, 0x03, 0x46,
++    0x0e, 0x4d, 0x25, 0x52, 0x57, 0x57, 0x4c, 0x4f, 0x4f, 0x49, 0x44, 0x00, 0x44, 0x08, 0x4c, 0x52,
++    0x2c, 0x07, 0x4c, 0x08, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x08, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x4a,
++    0x42, 0x14, 0x14, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x57, 0x15, 0x42, 0x57, 0x40, 0x40,
++    0x4a, 0x06, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1c, 0x27, 0x06, 0x42, 0x08, 0x0b, 0x0f,
++    0x4a, 0x2c, 0x1a, 0x14, 0x4a, 0x1b, 0x0b, 0x17, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x41, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x40, 0x40, 0x40, 0x04, 0x44,
++    0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x56,
++    0x52, 0x48, 0x05, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4e, 0x4e, 0x44, 0x4c,
++    0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x46, 0x56, 0x62, 0x5c, 0x56, 0x4a, 0x01, 0x03, 0x44, 0x4e, 0x4e,
++    0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x46, 0x56, 0x62, 0x5c, 0x56, 0x4a, 0x01, 0x03, 0x44,
++    0x0f, 0x4d, 0x25, 0x52, 0x56, 0x56, 0x4c, 0x4e, 0x4e, 0x48, 0x44, 0x01, 0x44, 0x09, 0x4c, 0x52,
++    0x2c, 0x07, 0x4c, 0x09, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x09, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x4a,
++    0x42, 0x14, 0x14, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x56, 0x15, 0x42, 0x56, 0x40, 0x40,
++    0x4a, 0x07, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1d, 0x27, 0x07, 0x42, 0x09, 0x0b, 0x0f,
++    0x4a, 0x2c, 0x1a, 0x14, 0x4a, 0x1a, 0x0b, 0x16, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x42, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x40, 0x40, 0x40, 0x03, 0x42,
++    0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x55,
++    0x51, 0x47, 0x06, 0x13, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4d, 0x4d, 0x43, 0x4b,
++    0x49, 0x07, 0x4b, 0x5b, 0x49, 0x45, 0x55, 0x61, 0x5b, 0x55, 0x48, 0x02, 0x04, 0x42, 0x4d, 0x4d,
++    0x43, 0x4b, 0x49, 0x07, 0x4b, 0x5b, 0x49, 0x45, 0x55, 0x61, 0x5b, 0x55, 0x48, 0x02, 0x04, 0x42,
++    0x10, 0x4e, 0x26, 0x51, 0x55, 0x55, 0x4b, 0x4d, 0x4d, 0x47, 0x43, 0x02, 0x43, 0x0a, 0x4b, 0x51,
++    0x2b, 0x07, 0x4b, 0x0a, 0x4b, 0x51, 0x2b, 0x07, 0x4b, 0x0a, 0x4b, 0x51, 0x2b, 0x07, 0x4b, 0x49,
++    0x41, 0x13, 0x13, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x55, 0x16, 0x41, 0x55, 0x40, 0x40,
++    0x49, 0x08, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x1f, 0x27, 0x08, 0x41, 0x0a, 0x0c, 0x0f,
++    0x49, 0x2b, 0x19, 0x13, 0x49, 0x18, 0x0c, 0x15, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x43, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x40, 0x40, 0x40, 0x02, 0x40,
++    0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x54,
++    0x51, 0x45, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4c, 0x4c, 0x42, 0x4a,
++    0x49, 0x07, 0x4a, 0x5a, 0x49, 0x44, 0x54, 0x61, 0x5a, 0x54, 0x47, 0x03, 0x05, 0x40, 0x4c, 0x4c,
++    0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x44, 0x54, 0x61, 0x5a, 0x54, 0x47, 0x03, 0x05, 0x40,
++    0x12, 0x4e, 0x26, 0x51, 0x54, 0x54, 0x4a, 0x4c, 0x4c, 0x45, 0x42, 0x03, 0x42, 0x0b, 0x4a, 0x51,
++    0x2a, 0x07, 0x4a, 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x49,
++    0x41, 0x12, 0x12, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x54, 0x16, 0x41, 0x54, 0x40, 0x40,
++    0x49, 0x0a, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x20, 0x27, 0x0a, 0x41, 0x0b, 0x0d, 0x0f,
++    0x49, 0x2a, 0x19, 0x12, 0x49, 0x17, 0x0d, 0x14, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x44, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x40, 0x40, 0x40, 0x02, 0x01,
++    0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x53,
++    0x51, 0x44, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4b, 0x42, 0x4a,
++    0x49, 0x07, 0x4a, 0x5a, 0x49, 0x43, 0x53, 0x61, 0x5a, 0x53, 0x45, 0x04, 0x05, 0x01, 0x4b, 0x4b,
++    0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x43, 0x53, 0x61, 0x5a, 0x53, 0x45, 0x04, 0x05, 0x01,
++    0x13, 0x4e, 0x26, 0x51, 0x53, 0x53, 0x4a, 0x4b, 0x4b, 0x44, 0x42, 0x04, 0x42, 0x0c, 0x4a, 0x51,
++    0x2a, 0x07, 0x4a, 0x0c, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x0c, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x49,
++    0x41, 0x12, 0x12, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x53, 0x16, 0x41, 0x53, 0x40, 0x40,
++    0x49, 0x0b, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x22, 0x27, 0x0b, 0x41, 0x0c, 0x0d, 0x0f,
++    0x49, 0x2a, 0x19, 0x12, 0x49, 0x15, 0x0d, 0x13, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x45, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x40, 0x40, 0x40, 0x01, 0x03,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x52,
++    0x50, 0x43, 0x07, 0x11, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x4a, 0x41, 0x49,
++    0x48, 0x07, 0x49, 0x59, 0x48, 0x42, 0x52, 0x60, 0x59, 0x52, 0x44, 0x05, 0x06, 0x03, 0x4a, 0x4a,
++    0x41, 0x49, 0x48, 0x07, 0x49, 0x59, 0x48, 0x42, 0x52, 0x60, 0x59, 0x52, 0x44, 0x05, 0x06, 0x03,
++    0x14, 0x4f, 0x27, 0x50, 0x52, 0x52, 0x49, 0x4a, 0x4a, 0x43, 0x41, 0x05, 0x41, 0x0d, 0x49, 0x50,
++    0x29, 0x07, 0x49, 0x0d, 0x49, 0x50, 0x29, 0x07, 0x49, 0x0d, 0x49, 0x50, 0x29, 0x07, 0x49, 0x48,
++    0x40, 0x11, 0x11, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x52, 0x17, 0x40, 0x52, 0x40, 0x40,
++    0x48, 0x0c, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x23, 0x27, 0x0c, 0x40, 0x0d, 0x0e, 0x0f,
++    0x48, 0x29, 0x18, 0x11, 0x48, 0x14, 0x0e, 0x12, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x46, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, 0x40, 0x40, 0x00, 0x04,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x51,
++    0x50, 0x42, 0x07, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x41, 0x49,
++    0x48, 0x07, 0x49, 0x59, 0x48, 0x41, 0x51, 0x60, 0x59, 0x51, 0x42, 0x06, 0x06, 0x04, 0x49, 0x49,
++    0x41, 0x49, 0x48, 0x07, 0x49, 0x59, 0x48, 0x41, 0x51, 0x60, 0x59, 0x51, 0x42, 0x06, 0x06, 0x04,
++    0x15, 0x4f, 0x27, 0x50, 0x51, 0x51, 0x49, 0x49, 0x49, 0x42, 0x41, 0x06, 0x41, 0x0e, 0x49, 0x50,
++    0x28, 0x07, 0x49, 0x0e, 0x49, 0x50, 0x28, 0x07, 0x49, 0x0e, 0x49, 0x50, 0x28, 0x07, 0x49, 0x48,
++    0x40, 0x10, 0x10, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x51, 0x17, 0x40, 0x51, 0x40, 0x40,
++    0x48, 0x0d, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x25, 0x27, 0x0d, 0x40, 0x0e, 0x0e, 0x0f,
++    0x48, 0x28, 0x18, 0x10, 0x48, 0x12, 0x0e, 0x11, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x47, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, 0x40, 0x40, 0x00, 0x06,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x50,
++    0x50, 0x40, 0x07, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48,
++    0x48, 0x07, 0x48, 0x58, 0x48, 0x40, 0x50, 0x60, 0x58, 0x50, 0x40, 0x07, 0x07, 0x06, 0x48, 0x48,
++    0x40, 0x48, 0x48, 0x07, 0x48, 0x58, 0x48, 0x40, 0x50, 0x60, 0x58, 0x50, 0x40, 0x07, 0x07, 0x06,
++    0x17, 0x4f, 0x27, 0x50, 0x50, 0x50, 0x48, 0x48, 0x48, 0x40, 0x40, 0x07, 0x40, 0x0f, 0x48, 0x50,
++    0x28, 0x07, 0x48, 0x0f, 0x48, 0x50, 0x28, 0x07, 0x48, 0x0f, 0x48, 0x50, 0x28, 0x07, 0x48, 0x48,
++    0x40, 0x10, 0x10, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x50, 0x17, 0x40, 0x50, 0x40, 0x40,
++    0x48, 0x0f, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x27, 0x27, 0x0f, 0x40, 0x0f, 0x0f, 0x0f,
++    0x48, 0x28, 0x18, 0x10, 0x48, 0x10, 0x0f, 0x10, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x48, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x08,
++    0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4f,
++    0x4f, 0x00, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47,
++    0x47, 0x07, 0x47, 0x57, 0x47, 0x00, 0x4f, 0x5f, 0x57, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47,
++    0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x00, 0x4f, 0x5f, 0x57, 0x4f, 0x00, 0x08, 0x08, 0x08,
++    0x18, 0x50, 0x28, 0x4f, 0x4f, 0x4f, 0x47, 0x47, 0x47, 0x00, 0x00, 0x08, 0x00, 0x10, 0x47, 0x4f,
++    0x27, 0x07, 0x47, 0x10, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x10, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x47,
++    0x00, 0x0f, 0x0f, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4f, 0x18, 0x00, 0x4f, 0x40, 0x40,
++    0x47, 0x10, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x28, 0x27, 0x10, 0x00, 0x10, 0x10, 0x0f,
++    0x47, 0x27, 0x17, 0x0f, 0x47, 0x0f, 0x10, 0x0f, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x49, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a,
++    0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4e,
++    0x4f, 0x01, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x46, 0x00, 0x47,
++    0x47, 0x07, 0x47, 0x57, 0x47, 0x01, 0x4e, 0x5f, 0x57, 0x4e, 0x02, 0x09, 0x08, 0x0a, 0x46, 0x46,
++    0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x01, 0x4e, 0x5f, 0x57, 0x4e, 0x02, 0x09, 0x08, 0x0a,
++    0x19, 0x50, 0x28, 0x4f, 0x4e, 0x4e, 0x47, 0x46, 0x46, 0x01, 0x00, 0x09, 0x00, 0x11, 0x47, 0x4f,
++    0x27, 0x07, 0x47, 0x11, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x11, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x47,
++    0x00, 0x0f, 0x0f, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4e, 0x18, 0x00, 0x4e, 0x40, 0x40,
++    0x47, 0x11, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x2a, 0x27, 0x11, 0x00, 0x11, 0x10, 0x0f,
++    0x47, 0x27, 0x17, 0x0f, 0x47, 0x0d, 0x10, 0x0e, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4a, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x40, 0x40, 0x40, 0x41, 0x0c,
++    0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4d,
++    0x4f, 0x02, 0x08, 0x0e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x45, 0x45, 0x01, 0x46,
++    0x47, 0x07, 0x46, 0x56, 0x47, 0x02, 0x4d, 0x5f, 0x56, 0x4d, 0x03, 0x0a, 0x09, 0x0c, 0x45, 0x45,
++    0x01, 0x46, 0x47, 0x07, 0x46, 0x56, 0x47, 0x02, 0x4d, 0x5f, 0x56, 0x4d, 0x03, 0x0a, 0x09, 0x0c,
++    0x1a, 0x50, 0x28, 0x4f, 0x4d, 0x4d, 0x46, 0x45, 0x45, 0x02, 0x01, 0x0a, 0x01, 0x12, 0x46, 0x4f,
++    0x26, 0x07, 0x46, 0x12, 0x46, 0x4f, 0x26, 0x07, 0x46, 0x12, 0x46, 0x4f, 0x26, 0x07, 0x46, 0x47,
++    0x00, 0x0e, 0x0e, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4d, 0x18, 0x00, 0x4d, 0x40, 0x40,
++    0x47, 0x12, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x2b, 0x27, 0x12, 0x00, 0x12, 0x11, 0x0f,
++    0x47, 0x26, 0x17, 0x0e, 0x47, 0x0c, 0x11, 0x0d, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4b, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x40, 0x40, 0x40, 0x42, 0x0e,
++    0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4c,
++    0x4e, 0x04, 0x09, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x44, 0x02, 0x45,
++    0x46, 0x07, 0x45, 0x55, 0x46, 0x03, 0x4c, 0x5e, 0x55, 0x4c, 0x05, 0x0b, 0x0a, 0x0e, 0x44, 0x44,
++    0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x03, 0x4c, 0x5e, 0x55, 0x4c, 0x05, 0x0b, 0x0a, 0x0e,
++    0x1c, 0x51, 0x29, 0x4e, 0x4c, 0x4c, 0x45, 0x44, 0x44, 0x04, 0x02, 0x0b, 0x02, 0x13, 0x45, 0x4e,
++    0x25, 0x07, 0x45, 0x13, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x13, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x46,
++    0x01, 0x0d, 0x0d, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4c, 0x19, 0x01, 0x4c, 0x40, 0x40,
++    0x46, 0x14, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x2d, 0x27, 0x14, 0x01, 0x13, 0x12, 0x0f,
++    0x46, 0x25, 0x16, 0x0d, 0x46, 0x0a, 0x12, 0x0c, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4c, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x40, 0x40, 0x40, 0x42, 0x10,
++    0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4b,
++    0x4e, 0x05, 0x09, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x43, 0x43, 0x02, 0x45,
++    0x46, 0x07, 0x45, 0x55, 0x46, 0x04, 0x4b, 0x5e, 0x55, 0x4b, 0x06, 0x0c, 0x0a, 0x10, 0x43, 0x43,
++    0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x04, 0x4b, 0x5e, 0x55, 0x4b, 0x06, 0x0c, 0x0a, 0x10,
++    0x1d, 0x51, 0x29, 0x4e, 0x4b, 0x4b, 0x45, 0x43, 0x43, 0x05, 0x02, 0x0c, 0x02, 0x14, 0x45, 0x4e,
++    0x25, 0x07, 0x45, 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x46,
++    0x01, 0x0d, 0x0d, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4b, 0x19, 0x01, 0x4b, 0x40, 0x40,
++    0x46, 0x15, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x2e, 0x27, 0x15, 0x01, 0x14, 0x12, 0x0f,
++    0x46, 0x25, 0x16, 0x0d, 0x46, 0x09, 0x12, 0x0b, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4d, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x40, 0x40, 0x40, 0x43, 0x12,
++    0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4a,
++    0x4e, 0x06, 0x09, 0x0c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x42, 0x42, 0x03, 0x44,
++    0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x08, 0x0d, 0x0b, 0x12, 0x42, 0x42,
++    0x03, 0x44, 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x08, 0x0d, 0x0b, 0x12,
++    0x1e, 0x51, 0x29, 0x4e, 0x4a, 0x4a, 0x44, 0x42, 0x42, 0x06, 0x03, 0x0d, 0x03, 0x15, 0x44, 0x4e,
++    0x24, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x24, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x24, 0x07, 0x44, 0x46,
++    0x01, 0x0c, 0x0c, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4a, 0x19, 0x01, 0x4a, 0x40, 0x40,
++    0x46, 0x16, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x30, 0x27, 0x16, 0x01, 0x15, 0x13, 0x0f,
++    0x46, 0x24, 0x16, 0x0c, 0x46, 0x07, 0x13, 0x0a, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4e, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x40, 0x40, 0x40, 0x44, 0x13,
++    0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4a,
++    0x4e, 0x07, 0x09, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x42, 0x42, 0x03, 0x44,
++    0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x09, 0x0d, 0x0b, 0x13, 0x42, 0x42,
++    0x03, 0x44, 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x09, 0x0d, 0x0b, 0x13,
++    0x1f, 0x52, 0x29, 0x4e, 0x4a, 0x4a, 0x44, 0x42, 0x42, 0x07, 0x03, 0x0d, 0x03, 0x15, 0x44, 0x4e,
++    0x23, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x23, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x23, 0x07, 0x44, 0x46,
++    0x01, 0x0b, 0x0b, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4a, 0x19, 0x01, 0x4a, 0x40, 0x40,
++    0x46, 0x17, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x31, 0x27, 0x17, 0x01, 0x15, 0x13, 0x0f,
++    0x46, 0x23, 0x15, 0x0b, 0x46, 0x05, 0x13, 0x09, 0x09, 0x07, 0x19, 0x0d, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4e, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x40, 0x40, 0x40, 0x44, 0x15,
++    0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x49,
++    0x4d, 0x09, 0x0a, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x41, 0x41, 0x04, 0x43,
++    0x45, 0x07, 0x43, 0x53, 0x45, 0x06, 0x49, 0x5d, 0x53, 0x49, 0x0b, 0x0e, 0x0c, 0x15, 0x41, 0x41,
++    0x04, 0x43, 0x45, 0x07, 0x43, 0x53, 0x45, 0x06, 0x49, 0x5d, 0x53, 0x49, 0x0b, 0x0e, 0x0c, 0x15,
++    0x21, 0x52, 0x2a, 0x4d, 0x49, 0x49, 0x43, 0x41, 0x41, 0x09, 0x04, 0x0e, 0x04, 0x16, 0x43, 0x4d,
++    0x23, 0x07, 0x43, 0x16, 0x43, 0x4d, 0x23, 0x07, 0x43, 0x16, 0x43, 0x4d, 0x23, 0x07, 0x43, 0x45,
++    0x02, 0x0b, 0x0b, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x49, 0x1a, 0x02, 0x49, 0x40, 0x40,
++    0x45, 0x19, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x33, 0x27, 0x19, 0x02, 0x16, 0x14, 0x0f,
++    0x45, 0x23, 0x15, 0x0b, 0x45, 0x04, 0x14, 0x09, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4f, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x40, 0x40, 0x40, 0x45, 0x17,
++    0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x48,
++    0x4d, 0x0a, 0x0a, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x40, 0x40, 0x05, 0x42,
++    0x45, 0x07, 0x42, 0x52, 0x45, 0x07, 0x48, 0x5d, 0x52, 0x48, 0x0d, 0x0f, 0x0d, 0x17, 0x40, 0x40,
++    0x05, 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x07, 0x48, 0x5d, 0x52, 0x48, 0x0d, 0x0f, 0x0d, 0x17,
++    0x22, 0x52, 0x2a, 0x4d, 0x48, 0x48, 0x42, 0x40, 0x40, 0x0a, 0x05, 0x0f, 0x05, 0x17, 0x42, 0x4d,
++    0x22, 0x07, 0x42, 0x17, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x17, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x45,
++    0x02, 0x0a, 0x0a, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x48, 0x1a, 0x02, 0x48, 0x40, 0x40,
++    0x45, 0x1a, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x35, 0x27, 0x1a, 0x02, 0x17, 0x15, 0x0f,
++    0x45, 0x22, 0x15, 0x0a, 0x45, 0x02, 0x15, 0x08, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x50, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x40, 0x40, 0x40, 0x45, 0x19,
++    0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x47,
++    0x4d, 0x0b, 0x0a, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x00, 0x00, 0x05, 0x42,
++    0x45, 0x07, 0x42, 0x52, 0x45, 0x08, 0x47, 0x5d, 0x52, 0x47, 0x0e, 0x10, 0x0d, 0x19, 0x00, 0x00,
++    0x05, 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x08, 0x47, 0x5d, 0x52, 0x47, 0x0e, 0x10, 0x0d, 0x19,
++    0x23, 0x52, 0x2a, 0x4d, 0x47, 0x47, 0x42, 0x00, 0x00, 0x0b, 0x05, 0x10, 0x05, 0x18, 0x42, 0x4d,
++    0x22, 0x07, 0x42, 0x18, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x18, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x45,
++    0x02, 0x0a, 0x0a, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x47, 0x1a, 0x02, 0x47, 0x40, 0x40,
++    0x45, 0x1b, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x36, 0x27, 0x1b, 0x02, 0x18, 0x15, 0x0f,
++    0x45, 0x22, 0x15, 0x0a, 0x45, 0x01, 0x15, 0x07, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x51, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x40, 0x40, 0x40, 0x46, 0x1b,
++    0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x46,
++    0x4c, 0x0c, 0x0b, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x01, 0x01, 0x06, 0x41,
++    0x44, 0x07, 0x41, 0x51, 0x44, 0x09, 0x46, 0x5c, 0x51, 0x46, 0x10, 0x11, 0x0e, 0x1b, 0x01, 0x01,
++    0x06, 0x41, 0x44, 0x07, 0x41, 0x51, 0x44, 0x09, 0x46, 0x5c, 0x51, 0x46, 0x10, 0x11, 0x0e, 0x1b,
++    0x24, 0x53, 0x2b, 0x4c, 0x46, 0x46, 0x41, 0x01, 0x01, 0x0c, 0x06, 0x11, 0x06, 0x19, 0x41, 0x4c,
++    0x21, 0x07, 0x41, 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, 0x44,
++    0x03, 0x09, 0x09, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x46, 0x1b, 0x03, 0x46, 0x40, 0x40,
++    0x44, 0x1c, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x38, 0x27, 0x1c, 0x03, 0x19, 0x16, 0x0f,
++    0x44, 0x21, 0x14, 0x09, 0x44, 0x40, 0x16, 0x06, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x52, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x40, 0x40, 0x40, 0x47, 0x1d,
++    0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x45,
++    0x4c, 0x0e, 0x0b, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x02, 0x02, 0x07, 0x40,
++    0x44, 0x07, 0x40, 0x50, 0x44, 0x0a, 0x45, 0x5c, 0x50, 0x45, 0x11, 0x12, 0x0f, 0x1d, 0x02, 0x02,
++    0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0a, 0x45, 0x5c, 0x50, 0x45, 0x11, 0x12, 0x0f, 0x1d,
++    0x26, 0x53, 0x2b, 0x4c, 0x45, 0x45, 0x40, 0x02, 0x02, 0x0e, 0x07, 0x12, 0x07, 0x1a, 0x40, 0x4c,
++    0x20, 0x07, 0x40, 0x1a, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1a, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x44,
++    0x03, 0x08, 0x08, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x45, 0x1b, 0x03, 0x45, 0x40, 0x40,
++    0x44, 0x1e, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x39, 0x27, 0x1e, 0x03, 0x1a, 0x17, 0x0f,
++    0x44, 0x20, 0x14, 0x08, 0x44, 0x41, 0x17, 0x05, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x53, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x40, 0x40, 0x40, 0x47, 0x1f,
++    0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x44,
++    0x4c, 0x0f, 0x0b, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x03, 0x03, 0x07, 0x40,
++    0x44, 0x07, 0x40, 0x50, 0x44, 0x0b, 0x44, 0x5c, 0x50, 0x44, 0x13, 0x13, 0x0f, 0x1f, 0x03, 0x03,
++    0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0b, 0x44, 0x5c, 0x50, 0x44, 0x13, 0x13, 0x0f, 0x1f,
++    0x27, 0x53, 0x2b, 0x4c, 0x44, 0x44, 0x40, 0x03, 0x03, 0x0f, 0x07, 0x13, 0x07, 0x1b, 0x40, 0x4c,
++    0x20, 0x07, 0x40, 0x1b, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1b, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x44,
++    0x03, 0x08, 0x08, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x44, 0x1b, 0x03, 0x44, 0x40, 0x40,
++    0x44, 0x1f, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x3b, 0x27, 0x1f, 0x03, 0x1b, 0x17, 0x0f,
++    0x44, 0x20, 0x14, 0x08, 0x44, 0x43, 0x17, 0x04, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x54, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x40, 0x40, 0x40, 0x48, 0x21,
++    0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x43,
++    0x4b, 0x10, 0x0c, 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x04, 0x04, 0x08, 0x00,
++    0x43, 0x07, 0x00, 0x4f, 0x43, 0x0c, 0x43, 0x5b, 0x4f, 0x43, 0x14, 0x14, 0x10, 0x21, 0x04, 0x04,
++    0x08, 0x00, 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0c, 0x43, 0x5b, 0x4f, 0x43, 0x14, 0x14, 0x10, 0x21,
++    0x28, 0x54, 0x2c, 0x4b, 0x43, 0x43, 0x00, 0x04, 0x04, 0x10, 0x08, 0x14, 0x08, 0x1c, 0x00, 0x4b,
++    0x1f, 0x07, 0x00, 0x1c, 0x00, 0x4b, 0x1f, 0x07, 0x00, 0x1c, 0x00, 0x4b, 0x1f, 0x07, 0x00, 0x43,
++    0x04, 0x07, 0x07, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x43, 0x1c, 0x04, 0x43, 0x40, 0x40,
++    0x43, 0x20, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3c, 0x27, 0x20, 0x04, 0x1c, 0x18, 0x0f,
++    0x43, 0x1f, 0x13, 0x07, 0x43, 0x44, 0x18, 0x03, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x55, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x40, 0x40, 0x40, 0x49, 0x22,
++    0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x42,
++    0x4b, 0x11, 0x0c, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x05, 0x05, 0x08, 0x00,
++    0x43, 0x07, 0x00, 0x4f, 0x43, 0x0d, 0x42, 0x5b, 0x4f, 0x42, 0x16, 0x15, 0x10, 0x22, 0x05, 0x05,
++    0x08, 0x00, 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0d, 0x42, 0x5b, 0x4f, 0x42, 0x16, 0x15, 0x10, 0x22,
++    0x29, 0x54, 0x2c, 0x4b, 0x42, 0x42, 0x00, 0x05, 0x05, 0x11, 0x08, 0x15, 0x08, 0x1d, 0x00, 0x4b,
++    0x1e, 0x07, 0x00, 0x1d, 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x1d, 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x43,
++    0x04, 0x06, 0x06, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x42, 0x1c, 0x04, 0x42, 0x40, 0x40,
++    0x43, 0x21, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3e, 0x27, 0x21, 0x04, 0x1d, 0x18, 0x0f,
++    0x43, 0x1e, 0x13, 0x06, 0x43, 0x46, 0x18, 0x02, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x56, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x40, 0x40, 0x40, 0x49, 0x24,
++    0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x41,
++    0x4b, 0x13, 0x0c, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x06, 0x06, 0x09, 0x01,
++    0x43, 0x07, 0x01, 0x4e, 0x43, 0x0e, 0x41, 0x5b, 0x4e, 0x41, 0x18, 0x16, 0x11, 0x24, 0x06, 0x06,
++    0x09, 0x01, 0x43, 0x07, 0x01, 0x4e, 0x43, 0x0e, 0x41, 0x5b, 0x4e, 0x41, 0x18, 0x16, 0x11, 0x24,
++    0x2b, 0x54, 0x2c, 0x4b, 0x41, 0x41, 0x01, 0x06, 0x06, 0x13, 0x09, 0x16, 0x09, 0x1e, 0x01, 0x4b,
++    0x1e, 0x07, 0x01, 0x1e, 0x01, 0x4b, 0x1e, 0x07, 0x01, 0x1e, 0x01, 0x4b, 0x1e, 0x07, 0x01, 0x43,
++    0x04, 0x06, 0x06, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x41, 0x1c, 0x04, 0x41, 0x40, 0x40,
++    0x43, 0x23, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3e, 0x27, 0x23, 0x04, 0x1e, 0x19, 0x0f,
++    0x43, 0x1e, 0x13, 0x06, 0x43, 0x48, 0x19, 0x01, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x57, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x40, 0x40, 0x40, 0x4a, 0x26,
++    0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x40,
++    0x4a, 0x14, 0x0d, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x07, 0x07, 0x0a, 0x02,
++    0x42, 0x07, 0x02, 0x4d, 0x42, 0x0f, 0x40, 0x5a, 0x4d, 0x40, 0x19, 0x17, 0x12, 0x26, 0x07, 0x07,
++    0x0a, 0x02, 0x42, 0x07, 0x02, 0x4d, 0x42, 0x0f, 0x40, 0x5a, 0x4d, 0x40, 0x19, 0x17, 0x12, 0x26,
++    0x2c, 0x55, 0x2d, 0x4a, 0x40, 0x40, 0x02, 0x07, 0x07, 0x14, 0x0a, 0x17, 0x0a, 0x1f, 0x02, 0x4a,
++    0x1d, 0x07, 0x02, 0x1f, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x1f, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x42,
++    0x05, 0x05, 0x05, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x40, 0x1d, 0x05, 0x40, 0x40, 0x40,
++    0x42, 0x24, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x24, 0x05, 0x1f, 0x1a, 0x0f,
++    0x42, 0x1d, 0x12, 0x05, 0x42, 0x49, 0x1a, 0x00, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x58, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x40, 0x40, 0x40, 0x4a, 0x28,
++    0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x00,
++    0x4a, 0x15, 0x0d, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x08, 0x08, 0x0a, 0x02,
++    0x42, 0x07, 0x02, 0x4d, 0x42, 0x10, 0x00, 0x5a, 0x4d, 0x00, 0x1b, 0x18, 0x12, 0x28, 0x08, 0x08,
++    0x0a, 0x02, 0x42, 0x07, 0x02, 0x4d, 0x42, 0x10, 0x00, 0x5a, 0x4d, 0x00, 0x1b, 0x18, 0x12, 0x28,
++    0x2d, 0x55, 0x2d, 0x4a, 0x00, 0x00, 0x02, 0x08, 0x08, 0x15, 0x0a, 0x18, 0x0a, 0x20, 0x02, 0x4a,
++    0x1d, 0x07, 0x02, 0x20, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x20, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x42,
++    0x05, 0x05, 0x05, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x00, 0x1d, 0x05, 0x00, 0x40, 0x40,
++    0x42, 0x25, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x25, 0x05, 0x20, 0x1a, 0x0f,
++    0x42, 0x1d, 0x12, 0x05, 0x42, 0x4b, 0x1a, 0x40, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x59, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4b, 0x40, 0x40, 0x40, 0x4b, 0x2a,
++    0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x01,
++    0x4a, 0x16, 0x0d, 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x09, 0x09, 0x0b, 0x03,
++    0x42, 0x07, 0x03, 0x4c, 0x42, 0x11, 0x01, 0x5a, 0x4c, 0x01, 0x1c, 0x19, 0x13, 0x2a, 0x09, 0x09,
++    0x0b, 0x03, 0x42, 0x07, 0x03, 0x4c, 0x42, 0x11, 0x01, 0x5a, 0x4c, 0x01, 0x1c, 0x19, 0x13, 0x2a,
++    0x2e, 0x55, 0x2d, 0x4a, 0x01, 0x01, 0x03, 0x09, 0x09, 0x16, 0x0b, 0x19, 0x0b, 0x21, 0x03, 0x4a,
++    0x1c, 0x07, 0x03, 0x21, 0x03, 0x4a, 0x1c, 0x07, 0x03, 0x21, 0x03, 0x4a, 0x1c, 0x07, 0x03, 0x42,
++    0x05, 0x04, 0x04, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x01, 0x1d, 0x05, 0x01, 0x40, 0x40,
++    0x42, 0x26, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x26, 0x05, 0x21, 0x1b, 0x0f,
++    0x42, 0x1c, 0x12, 0x04, 0x42, 0x4c, 0x1b, 0x41, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5a, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4c, 0x40, 0x40, 0x40, 0x4c, 0x2c,
++    0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x02,
++    0x49, 0x18, 0x0e, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0a, 0x0a, 0x0c, 0x04,
++    0x41, 0x07, 0x04, 0x4b, 0x41, 0x12, 0x02, 0x59, 0x4b, 0x02, 0x1e, 0x1a, 0x14, 0x2c, 0x0a, 0x0a,
++    0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x12, 0x02, 0x59, 0x4b, 0x02, 0x1e, 0x1a, 0x14, 0x2c,
++    0x30, 0x56, 0x2e, 0x49, 0x02, 0x02, 0x04, 0x0a, 0x0a, 0x18, 0x0c, 0x1a, 0x0c, 0x22, 0x04, 0x49,
++    0x1b, 0x07, 0x04, 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x41,
++    0x06, 0x03, 0x03, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x02, 0x1e, 0x06, 0x02, 0x40, 0x40,
++    0x41, 0x28, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x28, 0x06, 0x22, 0x1c, 0x0f,
++    0x41, 0x1b, 0x11, 0x03, 0x41, 0x4e, 0x1c, 0x42, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5b, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4c, 0x40, 0x40, 0x40, 0x4c, 0x2e,
++    0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x03,
++    0x49, 0x19, 0x0e, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0b, 0x0b, 0x0c, 0x04,
++    0x41, 0x07, 0x04, 0x4b, 0x41, 0x13, 0x03, 0x59, 0x4b, 0x03, 0x1f, 0x1b, 0x14, 0x2e, 0x0b, 0x0b,
++    0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x13, 0x03, 0x59, 0x4b, 0x03, 0x1f, 0x1b, 0x14, 0x2e,
++    0x31, 0x56, 0x2e, 0x49, 0x03, 0x03, 0x04, 0x0b, 0x0b, 0x19, 0x0c, 0x1b, 0x0c, 0x23, 0x04, 0x49,
++    0x1b, 0x07, 0x04, 0x23, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x23, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x41,
++    0x06, 0x03, 0x03, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x03, 0x1e, 0x06, 0x03, 0x40, 0x40,
++    0x41, 0x29, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x29, 0x06, 0x23, 0x1c, 0x0f,
++    0x41, 0x1b, 0x11, 0x03, 0x41, 0x4f, 0x1c, 0x43, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5c, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4d, 0x40, 0x40, 0x40, 0x4d, 0x30,
++    0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x04,
++    0x49, 0x1a, 0x0e, 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0c, 0x0c, 0x0d, 0x05,
++    0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x21, 0x1c, 0x15, 0x30, 0x0c, 0x0c,
++    0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x21, 0x1c, 0x15, 0x30,
++    0x32, 0x56, 0x2e, 0x49, 0x04, 0x04, 0x05, 0x0c, 0x0c, 0x1a, 0x0d, 0x1c, 0x0d, 0x24, 0x05, 0x49,
++    0x1a, 0x07, 0x05, 0x24, 0x05, 0x49, 0x1a, 0x07, 0x05, 0x24, 0x05, 0x49, 0x1a, 0x07, 0x05, 0x41,
++    0x06, 0x02, 0x02, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x04, 0x1e, 0x06, 0x04, 0x40, 0x40,
++    0x41, 0x2a, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x2a, 0x06, 0x24, 0x1d, 0x0f,
++    0x41, 0x1a, 0x11, 0x02, 0x41, 0x51, 0x1d, 0x44, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5d, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x4e, 0x31,
++    0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x04,
++    0x49, 0x1b, 0x0e, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0c, 0x0c, 0x0d, 0x05,
++    0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x22, 0x1c, 0x15, 0x31, 0x0c, 0x0c,
++    0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x22, 0x1c, 0x15, 0x31,
++    0x33, 0x57, 0x2e, 0x49, 0x04, 0x04, 0x05, 0x0c, 0x0c, 0x1b, 0x0d, 0x1c, 0x0d, 0x24, 0x05, 0x49,
++    0x19, 0x07, 0x05, 0x24, 0x05, 0x49, 0x19, 0x07, 0x05, 0x24, 0x05, 0x49, 0x19, 0x07, 0x05, 0x41,
++    0x06, 0x01, 0x01, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x04, 0x1e, 0x06, 0x04, 0x40, 0x40,
++    0x41, 0x2b, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x2b, 0x06, 0x24, 0x1d, 0x0f,
++    0x41, 0x19, 0x10, 0x01, 0x41, 0x53, 0x1d, 0x45, 0x0e, 0x07, 0x1e, 0x08, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5d, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x4e, 0x33,
++    0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x05,
++    0x48, 0x1d, 0x0f, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0d, 0x0d, 0x0e, 0x06,
++    0x40, 0x07, 0x06, 0x49, 0x40, 0x15, 0x05, 0x58, 0x49, 0x05, 0x24, 0x1d, 0x16, 0x33, 0x0d, 0x0d,
++    0x0e, 0x06, 0x40, 0x07, 0x06, 0x49, 0x40, 0x15, 0x05, 0x58, 0x49, 0x05, 0x24, 0x1d, 0x16, 0x33,
++    0x35, 0x57, 0x2f, 0x48, 0x05, 0x05, 0x06, 0x0d, 0x0d, 0x1d, 0x0e, 0x1d, 0x0e, 0x25, 0x06, 0x48,
++    0x19, 0x07, 0x06, 0x25, 0x06, 0x48, 0x19, 0x07, 0x06, 0x25, 0x06, 0x48, 0x19, 0x07, 0x06, 0x40,
++    0x07, 0x01, 0x01, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x05, 0x1f, 0x07, 0x05, 0x40, 0x40,
++    0x40, 0x2d, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2d, 0x07, 0x25, 0x1e, 0x0f,
++    0x40, 0x19, 0x10, 0x01, 0x40, 0x54, 0x1e, 0x45, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5e, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x4f, 0x35,
++    0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x06,
++    0x48, 0x1e, 0x0f, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0e, 0x0e, 0x0f, 0x07,
++    0x40, 0x07, 0x07, 0x48, 0x40, 0x16, 0x06, 0x58, 0x48, 0x06, 0x26, 0x1e, 0x17, 0x35, 0x0e, 0x0e,
++    0x0f, 0x07, 0x40, 0x07, 0x07, 0x48, 0x40, 0x16, 0x06, 0x58, 0x48, 0x06, 0x26, 0x1e, 0x17, 0x35,
++    0x36, 0x57, 0x2f, 0x48, 0x06, 0x06, 0x07, 0x0e, 0x0e, 0x1e, 0x0f, 0x1e, 0x0f, 0x26, 0x07, 0x48,
++    0x18, 0x07, 0x07, 0x26, 0x07, 0x48, 0x18, 0x07, 0x07, 0x26, 0x07, 0x48, 0x18, 0x07, 0x07, 0x40,
++    0x07, 0x00, 0x00, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x06, 0x1f, 0x07, 0x06, 0x40, 0x40,
++    0x40, 0x2e, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2e, 0x07, 0x26, 0x1f, 0x0f,
++    0x40, 0x18, 0x10, 0x00, 0x40, 0x56, 0x1f, 0x46, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x5f, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x4f, 0x37,
++    0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x07,
++    0x48, 0x1f, 0x0f, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x07,
++    0x40, 0x07, 0x07, 0x48, 0x40, 0x17, 0x07, 0x58, 0x48, 0x07, 0x27, 0x1f, 0x17, 0x37, 0x0f, 0x0f,
++    0x0f, 0x07, 0x40, 0x07, 0x07, 0x48, 0x40, 0x17, 0x07, 0x58, 0x48, 0x07, 0x27, 0x1f, 0x17, 0x37,
++    0x37, 0x57, 0x2f, 0x48, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x1f, 0x0f, 0x1f, 0x0f, 0x27, 0x07, 0x48,
++    0x18, 0x07, 0x07, 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, 0x40,
++    0x07, 0x00, 0x00, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x07, 0x1f, 0x07, 0x07, 0x40, 0x40,
++    0x40, 0x2f, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2f, 0x07, 0x27, 0x1f, 0x0f,
++    0x40, 0x18, 0x10, 0x00, 0x40, 0x57, 0x1f, 0x47, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x07, 0x48, 0x48, 0x60, 0x40, 0x27, 0x07, 0x07, 0x27, 0x40, 0x48, 0x40, 0x40, 0x40, 0x0f,
++    0x48, 0x68, 0x60, 0x40, 0x68, 0x68, 0x68, 0x68, 0x68, 0x07, 0x07, 0x0f, 0x50, 0x40, 0x60, 0x07,
++    0x68, 0x27, 0x48, 0x17, 0x40, 0x50, 0x1f, 0x40, 0x40, 0x40, 0x48, 0x48, 0x58, 0x60, 0x60, 0x60,
++    0x68, 0x68, 0x58, 0x68, 0x60, 0x60, 0x60, 0x68, 0x68, 0x68, 0x60, 0x50, 0x48, 0x50, 0x58, 0x60,
++    0x60, 0x60, 0x68, 0x68, 0x58, 0x68, 0x60, 0x60, 0x60, 0x68, 0x68, 0x68, 0x60, 0x50, 0x48, 0x50,
++    0x07, 0x50, 0x58, 0x40, 0x48, 0x40, 0x48, 0x07, 0x48, 0x48, 0x48, 0x68, 0x07, 0x1f, 0x17, 0x50,
++    0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x40,
++    0x07, 0x48, 0x48, 0x48, 0x07, 0x48, 0x07, 0x17, 0x17, 0x17, 0x50, 0x17, 0x17, 0x50, 0x40, 0x40,
++    0x40, 0x2f, 0x2f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x1f, 0x27, 0x0f, 0x07, 0x07, 0x0f, 0x07,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x07, 0x1f, 0x48, 0x17, 0x48, 0x40, 0x48, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x07, 0x47, 0x47, 0x5f, 0x40, 0x27, 0x07, 0x07, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f,
++    0x47, 0x66, 0x5f, 0x00, 0x66, 0x66, 0x66, 0x65, 0x65, 0x07, 0x07, 0x0f, 0x4f, 0x00, 0x5e, 0x07,
++    0x67, 0x27, 0x47, 0x17, 0x40, 0x4f, 0x1f, 0x40, 0x40, 0x40, 0x47, 0x47, 0x57, 0x5f, 0x5e, 0x5f,
++    0x66, 0x66, 0x57, 0x67, 0x5f, 0x5e, 0x5f, 0x67, 0x67, 0x66, 0x5e, 0x4f, 0x47, 0x4f, 0x57, 0x5f,
++    0x5e, 0x5f, 0x66, 0x66, 0x57, 0x67, 0x5f, 0x5e, 0x5f, 0x67, 0x67, 0x66, 0x5e, 0x4f, 0x47, 0x4f,
++    0x08, 0x4f, 0x56, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x47, 0x47, 0x66, 0x07, 0x1f, 0x17, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x47, 0x47, 0x47, 0x08, 0x47, 0x08, 0x17, 0x17, 0x17, 0x4f, 0x17, 0x17, 0x4f, 0x40, 0x40,
++    0x40, 0x2f, 0x2f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x20, 0x27, 0x10, 0x07, 0x08, 0x10, 0x08,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1f, 0x47, 0x17, 0x46, 0x00, 0x47, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x06, 0x46, 0x47, 0x5e, 0x40, 0x26, 0x06, 0x06, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f,
++    0x47, 0x64, 0x5e, 0x01, 0x65, 0x64, 0x64, 0x63, 0x63, 0x07, 0x07, 0x0f, 0x4e, 0x00, 0x5d, 0x07,
++    0x66, 0x27, 0x46, 0x17, 0x40, 0x4f, 0x1e, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5e, 0x5d, 0x5e,
++    0x65, 0x64, 0x56, 0x66, 0x5e, 0x5c, 0x5e, 0x66, 0x66, 0x65, 0x5d, 0x4e, 0x46, 0x4e, 0x56, 0x5e,
++    0x5d, 0x5e, 0x65, 0x64, 0x56, 0x66, 0x5e, 0x5c, 0x5e, 0x66, 0x66, 0x65, 0x5d, 0x4e, 0x46, 0x4e,
++    0x09, 0x4f, 0x54, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x64, 0x07, 0x1f, 0x16, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x46, 0x46, 0x46, 0x09, 0x46, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40,
++    0x40, 0x2e, 0x2e, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x08,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1e, 0x46, 0x17, 0x45, 0x01, 0x46, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x06, 0x45, 0x47, 0x5e, 0x40, 0x25, 0x06, 0x05, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f,
++    0x47, 0x63, 0x5d, 0x01, 0x64, 0x63, 0x62, 0x60, 0x60, 0x07, 0x07, 0x0f, 0x4e, 0x00, 0x5c, 0x07,
++    0x65, 0x27, 0x45, 0x17, 0x40, 0x4f, 0x1d, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5d, 0x5c, 0x5d,
++    0x64, 0x63, 0x56, 0x65, 0x5d, 0x5b, 0x5d, 0x65, 0x65, 0x64, 0x5c, 0x4d, 0x46, 0x4d, 0x56, 0x5d,
++    0x5c, 0x5d, 0x64, 0x63, 0x56, 0x65, 0x5d, 0x5b, 0x5d, 0x65, 0x65, 0x64, 0x5c, 0x4d, 0x46, 0x4d,
++    0x09, 0x4f, 0x52, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x62, 0x07, 0x1f, 0x16, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x46, 0x46, 0x45, 0x09, 0x45, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40,
++    0x40, 0x2d, 0x2d, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x08,
++    0x07, 0x3d, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1e, 0x45, 0x17, 0x44, 0x01, 0x45, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x05, 0x44, 0x46, 0x5d, 0x40, 0x24, 0x05, 0x04, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f,
++    0x46, 0x61, 0x5c, 0x02, 0x63, 0x61, 0x60, 0x5e, 0x5e, 0x07, 0x07, 0x0e, 0x4d, 0x01, 0x5b, 0x07,
++    0x64, 0x27, 0x44, 0x16, 0x40, 0x4e, 0x1c, 0x40, 0x40, 0x40, 0x46, 0x46, 0x55, 0x5c, 0x5b, 0x5c,
++    0x63, 0x61, 0x55, 0x64, 0x5c, 0x59, 0x5c, 0x64, 0x64, 0x63, 0x5b, 0x4c, 0x45, 0x4c, 0x55, 0x5c,
++    0x5b, 0x5c, 0x63, 0x61, 0x55, 0x64, 0x5c, 0x59, 0x5c, 0x64, 0x64, 0x63, 0x5b, 0x4c, 0x45, 0x4c,
++    0x0a, 0x4e, 0x50, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x45, 0x45, 0x60, 0x07, 0x1e, 0x15, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x45, 0x45, 0x44, 0x0a, 0x44, 0x0a, 0x16, 0x17, 0x15, 0x4e, 0x17, 0x15, 0x4e, 0x40, 0x40,
++    0x40, 0x2c, 0x2c, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x1d, 0x21, 0x27, 0x11, 0x07, 0x0a, 0x11, 0x09,
++    0x06, 0x3c, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1d, 0x44, 0x16, 0x43, 0x02, 0x44, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x04, 0x43, 0x46, 0x5c, 0x40, 0x23, 0x04, 0x03, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f,
++    0x46, 0x60, 0x5b, 0x03, 0x61, 0x60, 0x5e, 0x5b, 0x5b, 0x07, 0x07, 0x0e, 0x4c, 0x01, 0x59, 0x07,
++    0x63, 0x27, 0x43, 0x16, 0x40, 0x4e, 0x1b, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5b, 0x59, 0x5b,
++    0x61, 0x60, 0x54, 0x63, 0x5b, 0x58, 0x5b, 0x63, 0x63, 0x61, 0x59, 0x4b, 0x44, 0x4b, 0x54, 0x5b,
++    0x59, 0x5b, 0x61, 0x60, 0x54, 0x63, 0x5b, 0x58, 0x5b, 0x63, 0x63, 0x61, 0x59, 0x4b, 0x44, 0x4b,
++    0x0b, 0x4e, 0x4e, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5e, 0x07, 0x1e, 0x14, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x44, 0x44, 0x43, 0x0b, 0x43, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40,
++    0x40, 0x2b, 0x2b, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x09,
++    0x06, 0x3b, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1c, 0x43, 0x16, 0x41, 0x03, 0x43, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x04, 0x42, 0x46, 0x5c, 0x40, 0x22, 0x04, 0x02, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f,
++    0x46, 0x5e, 0x5a, 0x03, 0x60, 0x5e, 0x5c, 0x59, 0x59, 0x07, 0x07, 0x0e, 0x4c, 0x01, 0x58, 0x07,
++    0x62, 0x27, 0x42, 0x16, 0x40, 0x4e, 0x1a, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5a, 0x58, 0x5a,
++    0x60, 0x5e, 0x54, 0x62, 0x5a, 0x56, 0x5a, 0x62, 0x62, 0x60, 0x58, 0x4a, 0x44, 0x4a, 0x54, 0x5a,
++    0x58, 0x5a, 0x60, 0x5e, 0x54, 0x62, 0x5a, 0x56, 0x5a, 0x62, 0x62, 0x60, 0x58, 0x4a, 0x44, 0x4a,
++    0x0b, 0x4e, 0x4c, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5c, 0x07, 0x1e, 0x14, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x44, 0x44, 0x42, 0x0b, 0x42, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40,
++    0x40, 0x2a, 0x2a, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x09,
++    0x06, 0x3a, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1c, 0x42, 0x16, 0x40, 0x03, 0x42, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x03, 0x41, 0x45, 0x5b, 0x40, 0x21, 0x03, 0x01, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f,
++    0x45, 0x5d, 0x59, 0x04, 0x5f, 0x5d, 0x5a, 0x56, 0x56, 0x07, 0x07, 0x0d, 0x4b, 0x02, 0x57, 0x07,
++    0x61, 0x27, 0x41, 0x15, 0x40, 0x4d, 0x19, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x59, 0x57, 0x59,
++    0x5f, 0x5d, 0x53, 0x61, 0x59, 0x55, 0x59, 0x61, 0x61, 0x5f, 0x57, 0x49, 0x43, 0x49, 0x53, 0x59,
++    0x57, 0x59, 0x5f, 0x5d, 0x53, 0x61, 0x59, 0x55, 0x59, 0x61, 0x61, 0x5f, 0x57, 0x49, 0x43, 0x49,
++    0x0c, 0x4d, 0x4a, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x5a, 0x07, 0x1d, 0x13, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x43, 0x43, 0x41, 0x0c, 0x41, 0x0c, 0x15, 0x17, 0x13, 0x4d, 0x17, 0x13, 0x4d, 0x40, 0x40,
++    0x40, 0x29, 0x29, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x1b, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x0a,
++    0x05, 0x39, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1b, 0x41, 0x15, 0x00, 0x04, 0x41, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x02, 0x40, 0x45, 0x5b, 0x40, 0x20, 0x02, 0x00, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f,
++    0x45, 0x5b, 0x58, 0x04, 0x5e, 0x5b, 0x59, 0x54, 0x54, 0x07, 0x07, 0x0d, 0x4b, 0x02, 0x56, 0x07,
++    0x60, 0x27, 0x40, 0x15, 0x40, 0x4d, 0x18, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x58, 0x56, 0x58,
++    0x5e, 0x5b, 0x53, 0x60, 0x58, 0x53, 0x58, 0x60, 0x60, 0x5e, 0x56, 0x48, 0x43, 0x48, 0x53, 0x58,
++    0x56, 0x58, 0x5e, 0x5b, 0x53, 0x60, 0x58, 0x53, 0x58, 0x60, 0x60, 0x5e, 0x56, 0x48, 0x43, 0x48,
++    0x0c, 0x4d, 0x49, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x59, 0x07, 0x1d, 0x12, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x43, 0x43, 0x40, 0x0c, 0x40, 0x0c, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40,
++    0x40, 0x28, 0x28, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x0a,
++    0x05, 0x38, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1a, 0x40, 0x15, 0x01, 0x04, 0x40, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x02, 0x00, 0x45, 0x5a, 0x40, 0x1f, 0x02, 0x40, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f,
++    0x45, 0x59, 0x57, 0x05, 0x5c, 0x59, 0x57, 0x51, 0x51, 0x07, 0x07, 0x0d, 0x4a, 0x02, 0x54, 0x07,
++    0x5f, 0x27, 0x00, 0x15, 0x40, 0x4d, 0x17, 0x40, 0x40, 0x40, 0x45, 0x45, 0x52, 0x57, 0x54, 0x57,
++    0x5c, 0x59, 0x52, 0x5f, 0x57, 0x51, 0x57, 0x5f, 0x5f, 0x5c, 0x54, 0x47, 0x42, 0x47, 0x52, 0x57,
++    0x54, 0x57, 0x5c, 0x59, 0x52, 0x5f, 0x57, 0x51, 0x57, 0x5f, 0x5f, 0x5c, 0x54, 0x47, 0x42, 0x47,
++    0x0d, 0x4d, 0x47, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x42, 0x42, 0x57, 0x07, 0x1d, 0x12, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x42, 0x42, 0x00, 0x0d, 0x00, 0x0d, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40,
++    0x40, 0x27, 0x27, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0d, 0x12, 0x0a,
++    0x05, 0x37, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1a, 0x00, 0x15, 0x03, 0x05, 0x00, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x01, 0x01, 0x44, 0x59, 0x40, 0x1e, 0x01, 0x41, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f,
++    0x44, 0x58, 0x56, 0x06, 0x5b, 0x58, 0x55, 0x4f, 0x4f, 0x07, 0x07, 0x0c, 0x49, 0x03, 0x53, 0x07,
++    0x5e, 0x27, 0x01, 0x14, 0x40, 0x4c, 0x16, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x56, 0x53, 0x56,
++    0x5b, 0x58, 0x51, 0x5e, 0x56, 0x50, 0x56, 0x5e, 0x5e, 0x5b, 0x53, 0x46, 0x41, 0x46, 0x51, 0x56,
++    0x53, 0x56, 0x5b, 0x58, 0x51, 0x5e, 0x56, 0x50, 0x56, 0x5e, 0x5e, 0x5b, 0x53, 0x46, 0x41, 0x46,
++    0x0e, 0x4c, 0x45, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x55, 0x07, 0x1c, 0x11, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x41, 0x41, 0x01, 0x0e, 0x01, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40,
++    0x40, 0x26, 0x26, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x0b,
++    0x04, 0x36, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x19, 0x01, 0x14, 0x04, 0x06, 0x01, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x01, 0x02, 0x44, 0x59, 0x40, 0x1d, 0x01, 0x42, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f,
++    0x44, 0x56, 0x55, 0x06, 0x5a, 0x56, 0x53, 0x4c, 0x4c, 0x07, 0x07, 0x0c, 0x49, 0x03, 0x52, 0x07,
++    0x5d, 0x27, 0x02, 0x14, 0x40, 0x4c, 0x15, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x55, 0x52, 0x55,
++    0x5a, 0x56, 0x51, 0x5d, 0x55, 0x4e, 0x55, 0x5d, 0x5d, 0x5a, 0x52, 0x45, 0x41, 0x45, 0x51, 0x55,
++    0x52, 0x55, 0x5a, 0x56, 0x51, 0x5d, 0x55, 0x4e, 0x55, 0x5d, 0x5d, 0x5a, 0x52, 0x45, 0x41, 0x45,
++    0x0e, 0x4c, 0x43, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x53, 0x07, 0x1c, 0x11, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x41, 0x41, 0x02, 0x0e, 0x02, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40,
++    0x40, 0x25, 0x25, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x0b,
++    0x04, 0x35, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x19, 0x02, 0x14, 0x05, 0x06, 0x02, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x00, 0x03, 0x44, 0x58, 0x40, 0x1c, 0x00, 0x43, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f,
++    0x44, 0x55, 0x54, 0x07, 0x59, 0x55, 0x51, 0x4a, 0x4a, 0x07, 0x07, 0x0c, 0x48, 0x03, 0x51, 0x07,
++    0x5c, 0x27, 0x03, 0x14, 0x40, 0x4c, 0x14, 0x40, 0x40, 0x40, 0x44, 0x44, 0x50, 0x54, 0x51, 0x54,
++    0x59, 0x55, 0x50, 0x5c, 0x54, 0x4d, 0x54, 0x5c, 0x5c, 0x59, 0x51, 0x44, 0x40, 0x44, 0x50, 0x54,
++    0x51, 0x54, 0x59, 0x55, 0x50, 0x5c, 0x54, 0x4d, 0x54, 0x5c, 0x5c, 0x59, 0x51, 0x44, 0x40, 0x44,
++    0x0f, 0x4c, 0x41, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x40, 0x40, 0x51, 0x07, 0x1c, 0x10, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x40, 0x40, 0x03, 0x0f, 0x03, 0x0f, 0x14, 0x17, 0x10, 0x4c, 0x17, 0x10, 0x4c, 0x40, 0x40,
++    0x40, 0x24, 0x24, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x18, 0x23, 0x27, 0x13, 0x07, 0x0f, 0x13, 0x0b,
++    0x04, 0x34, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x18, 0x03, 0x14, 0x06, 0x07, 0x03, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x40, 0x04, 0x43, 0x57, 0x40, 0x1b, 0x40, 0x44, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f,
++    0x43, 0x53, 0x53, 0x08, 0x57, 0x53, 0x4f, 0x47, 0x47, 0x07, 0x07, 0x0b, 0x47, 0x04, 0x4f, 0x07,
++    0x5b, 0x27, 0x04, 0x13, 0x40, 0x4b, 0x13, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x53, 0x4f, 0x53,
++    0x57, 0x53, 0x4f, 0x5b, 0x53, 0x4b, 0x53, 0x5b, 0x5b, 0x57, 0x4f, 0x43, 0x00, 0x43, 0x4f, 0x53,
++    0x4f, 0x53, 0x57, 0x53, 0x4f, 0x5b, 0x53, 0x4b, 0x53, 0x5b, 0x5b, 0x57, 0x4f, 0x43, 0x00, 0x43,
++    0x10, 0x4b, 0x00, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4f, 0x07, 0x1b, 0x0f, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x00, 0x00, 0x04, 0x10, 0x04, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40,
++    0x40, 0x23, 0x23, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x0c,
++    0x03, 0x33, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x17, 0x04, 0x13, 0x08, 0x08, 0x04, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x40, 0x05, 0x43, 0x57, 0x40, 0x1a, 0x40, 0x45, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f,
++    0x43, 0x52, 0x52, 0x08, 0x56, 0x52, 0x4d, 0x45, 0x45, 0x07, 0x07, 0x0b, 0x47, 0x04, 0x4e, 0x07,
++    0x5a, 0x27, 0x05, 0x13, 0x40, 0x4b, 0x12, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x52, 0x4e, 0x52,
++    0x56, 0x52, 0x4f, 0x5a, 0x52, 0x4a, 0x52, 0x5a, 0x5a, 0x56, 0x4e, 0x42, 0x00, 0x42, 0x4f, 0x52,
++    0x4e, 0x52, 0x56, 0x52, 0x4f, 0x5a, 0x52, 0x4a, 0x52, 0x5a, 0x5a, 0x56, 0x4e, 0x42, 0x00, 0x42,
++    0x10, 0x4b, 0x02, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4d, 0x07, 0x1b, 0x0f, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x00, 0x00, 0x05, 0x10, 0x05, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40,
++    0x40, 0x22, 0x22, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x0c,
++    0x03, 0x32, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x17, 0x05, 0x13, 0x09, 0x08, 0x05, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x41, 0x06, 0x43, 0x56, 0x40, 0x19, 0x41, 0x46, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f,
++    0x43, 0x50, 0x51, 0x09, 0x55, 0x50, 0x4b, 0x42, 0x42, 0x07, 0x07, 0x0b, 0x46, 0x04, 0x4d, 0x07,
++    0x59, 0x27, 0x06, 0x13, 0x40, 0x4b, 0x11, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x4d, 0x51,
++    0x55, 0x50, 0x4e, 0x59, 0x51, 0x48, 0x51, 0x59, 0x59, 0x55, 0x4d, 0x41, 0x01, 0x41, 0x4e, 0x51,
++    0x4d, 0x51, 0x55, 0x50, 0x4e, 0x59, 0x51, 0x48, 0x51, 0x59, 0x59, 0x55, 0x4d, 0x41, 0x01, 0x41,
++    0x11, 0x4b, 0x04, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4b, 0x07, 0x1b, 0x0e, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x01, 0x01, 0x06, 0x11, 0x06, 0x11, 0x13, 0x17, 0x0e, 0x4b, 0x17, 0x0e, 0x4b, 0x40, 0x40,
++    0x40, 0x21, 0x21, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x16, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x0c,
++    0x03, 0x31, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x16, 0x06, 0x13, 0x0a, 0x09, 0x06, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x42, 0x06, 0x43, 0x56, 0x40, 0x18, 0x42, 0x47, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f,
++    0x43, 0x4f, 0x51, 0x09, 0x54, 0x4f, 0x4a, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x46, 0x04, 0x4c, 0x07,
++    0x59, 0x27, 0x06, 0x12, 0x40, 0x4b, 0x10, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x4c, 0x51,
++    0x54, 0x4f, 0x4e, 0x59, 0x51, 0x47, 0x51, 0x59, 0x59, 0x54, 0x4c, 0x41, 0x01, 0x41, 0x4e, 0x51,
++    0x4c, 0x51, 0x54, 0x4f, 0x4e, 0x59, 0x51, 0x47, 0x51, 0x59, 0x59, 0x54, 0x4c, 0x41, 0x01, 0x41,
++    0x11, 0x4b, 0x05, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4a, 0x07, 0x1a, 0x0d, 0x4b,
++    0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x45,
++    0x07, 0x01, 0x01, 0x06, 0x11, 0x06, 0x11, 0x12, 0x17, 0x0d, 0x4b, 0x17, 0x0d, 0x4b, 0x40, 0x40,
++    0x40, 0x20, 0x20, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x0c,
++    0x02, 0x30, 0x1a, 0x12, 0x40, 0x12, 0x0c, 0x15, 0x06, 0x12, 0x0b, 0x09, 0x06, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x42, 0x07, 0x42, 0x55, 0x40, 0x18, 0x42, 0x47, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f,
++    0x42, 0x4d, 0x50, 0x0a, 0x52, 0x4d, 0x48, 0x02, 0x02, 0x07, 0x07, 0x0a, 0x45, 0x05, 0x4a, 0x07,
++    0x58, 0x27, 0x07, 0x12, 0x40, 0x4a, 0x10, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4d, 0x50, 0x4a, 0x50,
++    0x52, 0x4d, 0x4d, 0x58, 0x50, 0x45, 0x50, 0x58, 0x58, 0x52, 0x4a, 0x40, 0x02, 0x40, 0x4d, 0x50,
++    0x4a, 0x50, 0x52, 0x4d, 0x4d, 0x58, 0x50, 0x45, 0x50, 0x58, 0x58, 0x52, 0x4a, 0x40, 0x02, 0x40,
++    0x12, 0x4a, 0x07, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x02, 0x02, 0x48, 0x07, 0x1a, 0x0d, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x02, 0x02, 0x07, 0x12, 0x07, 0x12, 0x12, 0x17, 0x0d, 0x4a, 0x17, 0x0d, 0x4a, 0x40, 0x40,
++    0x40, 0x20, 0x20, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x25, 0x27, 0x15, 0x07, 0x12, 0x15, 0x0d,
++    0x02, 0x30, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x15, 0x07, 0x12, 0x0d, 0x0a, 0x07, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x43, 0x08, 0x42, 0x54, 0x40, 0x17, 0x43, 0x48, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f,
++    0x42, 0x4b, 0x4f, 0x0b, 0x51, 0x4b, 0x46, 0x04, 0x04, 0x07, 0x07, 0x0a, 0x44, 0x05, 0x49, 0x07,
++    0x57, 0x27, 0x08, 0x12, 0x40, 0x4a, 0x0f, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4f, 0x49, 0x4f,
++    0x51, 0x4b, 0x4c, 0x57, 0x4f, 0x43, 0x4f, 0x57, 0x57, 0x51, 0x49, 0x00, 0x03, 0x00, 0x4c, 0x4f,
++    0x49, 0x4f, 0x51, 0x4b, 0x4c, 0x57, 0x4f, 0x43, 0x4f, 0x57, 0x57, 0x51, 0x49, 0x00, 0x03, 0x00,
++    0x13, 0x4a, 0x09, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x46, 0x07, 0x1a, 0x0c, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x03, 0x03, 0x08, 0x13, 0x08, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40,
++    0x40, 0x1f, 0x1f, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0d,
++    0x02, 0x2f, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x14, 0x08, 0x12, 0x0e, 0x0b, 0x08, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x43, 0x09, 0x42, 0x54, 0x40, 0x16, 0x43, 0x49, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f,
++    0x42, 0x4a, 0x4e, 0x0b, 0x50, 0x4a, 0x44, 0x07, 0x07, 0x07, 0x07, 0x0a, 0x44, 0x05, 0x48, 0x07,
++    0x56, 0x27, 0x09, 0x12, 0x40, 0x4a, 0x0e, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4e, 0x48, 0x4e,
++    0x50, 0x4a, 0x4c, 0x56, 0x4e, 0x42, 0x4e, 0x56, 0x56, 0x50, 0x48, 0x01, 0x03, 0x01, 0x4c, 0x4e,
++    0x48, 0x4e, 0x50, 0x4a, 0x4c, 0x56, 0x4e, 0x42, 0x4e, 0x56, 0x56, 0x50, 0x48, 0x01, 0x03, 0x01,
++    0x13, 0x4a, 0x0b, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x44, 0x07, 0x1a, 0x0c, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x03, 0x03, 0x09, 0x13, 0x09, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40,
++    0x40, 0x1e, 0x1e, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0d,
++    0x02, 0x2e, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x14, 0x09, 0x12, 0x0f, 0x0b, 0x09, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x44, 0x0a, 0x41, 0x53, 0x40, 0x15, 0x44, 0x4a, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f,
++    0x41, 0x48, 0x4d, 0x0c, 0x4f, 0x48, 0x42, 0x09, 0x09, 0x07, 0x07, 0x09, 0x43, 0x06, 0x47, 0x07,
++    0x55, 0x27, 0x0a, 0x11, 0x40, 0x49, 0x0d, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4d, 0x47, 0x4d,
++    0x4f, 0x48, 0x4b, 0x55, 0x4d, 0x40, 0x4d, 0x55, 0x55, 0x4f, 0x47, 0x02, 0x04, 0x02, 0x4b, 0x4d,
++    0x47, 0x4d, 0x4f, 0x48, 0x4b, 0x55, 0x4d, 0x40, 0x4d, 0x55, 0x55, 0x4f, 0x47, 0x02, 0x04, 0x02,
++    0x14, 0x49, 0x0d, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x04, 0x04, 0x42, 0x07, 0x19, 0x0b, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x04, 0x04, 0x0a, 0x14, 0x0a, 0x14, 0x11, 0x17, 0x0b, 0x49, 0x17, 0x0b, 0x49, 0x40, 0x40,
++    0x40, 0x1d, 0x1d, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x13, 0x26, 0x27, 0x16, 0x07, 0x14, 0x16, 0x0e,
++    0x01, 0x2d, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x13, 0x0a, 0x11, 0x10, 0x0c, 0x0a, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x45, 0x0b, 0x41, 0x52, 0x40, 0x14, 0x45, 0x4b, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f,
++    0x41, 0x47, 0x4c, 0x0d, 0x4d, 0x47, 0x40, 0x0c, 0x0c, 0x07, 0x07, 0x09, 0x42, 0x06, 0x45, 0x07,
++    0x54, 0x27, 0x0b, 0x11, 0x40, 0x49, 0x0c, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4c, 0x45, 0x4c,
++    0x4d, 0x47, 0x4a, 0x54, 0x4c, 0x00, 0x4c, 0x54, 0x54, 0x4d, 0x45, 0x03, 0x05, 0x03, 0x4a, 0x4c,
++    0x45, 0x4c, 0x4d, 0x47, 0x4a, 0x54, 0x4c, 0x00, 0x4c, 0x54, 0x54, 0x4d, 0x45, 0x03, 0x05, 0x03,
++    0x15, 0x49, 0x0f, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x40, 0x07, 0x19, 0x0a, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x05, 0x05, 0x0b, 0x15, 0x0b, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40,
++    0x40, 0x1c, 0x1c, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0e,
++    0x01, 0x2c, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x12, 0x0b, 0x11, 0x12, 0x0d, 0x0b, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x45, 0x0c, 0x41, 0x52, 0x40, 0x13, 0x45, 0x4c, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f,
++    0x41, 0x45, 0x4b, 0x0d, 0x4c, 0x45, 0x01, 0x0e, 0x0e, 0x07, 0x07, 0x09, 0x42, 0x06, 0x44, 0x07,
++    0x53, 0x27, 0x0c, 0x11, 0x40, 0x49, 0x0b, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4b, 0x44, 0x4b,
++    0x4c, 0x45, 0x4a, 0x53, 0x4b, 0x02, 0x4b, 0x53, 0x53, 0x4c, 0x44, 0x04, 0x05, 0x04, 0x4a, 0x4b,
++    0x44, 0x4b, 0x4c, 0x45, 0x4a, 0x53, 0x4b, 0x02, 0x4b, 0x53, 0x53, 0x4c, 0x44, 0x04, 0x05, 0x04,
++    0x15, 0x49, 0x11, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x01, 0x07, 0x19, 0x0a, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x05, 0x05, 0x0c, 0x15, 0x0c, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40,
++    0x40, 0x1b, 0x1b, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0e,
++    0x01, 0x2b, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x12, 0x0c, 0x11, 0x13, 0x0d, 0x0c, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x46, 0x0d, 0x40, 0x51, 0x40, 0x12, 0x46, 0x4d, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f,
++    0x40, 0x44, 0x4a, 0x0e, 0x4b, 0x44, 0x03, 0x11, 0x11, 0x07, 0x07, 0x08, 0x41, 0x07, 0x43, 0x07,
++    0x52, 0x27, 0x0d, 0x10, 0x40, 0x48, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x4a, 0x43, 0x4a,
++    0x4b, 0x44, 0x49, 0x52, 0x4a, 0x03, 0x4a, 0x52, 0x52, 0x4b, 0x43, 0x05, 0x06, 0x05, 0x49, 0x4a,
++    0x43, 0x4a, 0x4b, 0x44, 0x49, 0x52, 0x4a, 0x03, 0x4a, 0x52, 0x52, 0x4b, 0x43, 0x05, 0x06, 0x05,
++    0x16, 0x48, 0x13, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x03, 0x07, 0x18, 0x09, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x06, 0x06, 0x0d, 0x16, 0x0d, 0x16, 0x10, 0x17, 0x09, 0x48, 0x17, 0x09, 0x48, 0x40, 0x40,
++    0x40, 0x1a, 0x1a, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x11, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0f,
++    0x00, 0x2a, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x11, 0x0d, 0x10, 0x14, 0x0e, 0x0d, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x47, 0x0e, 0x40, 0x51, 0x40, 0x11, 0x47, 0x4e, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f,
++    0x40, 0x42, 0x49, 0x0e, 0x4a, 0x42, 0x04, 0x13, 0x13, 0x07, 0x07, 0x08, 0x41, 0x07, 0x42, 0x07,
++    0x51, 0x27, 0x0e, 0x10, 0x40, 0x48, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x42, 0x49,
++    0x4a, 0x42, 0x49, 0x51, 0x49, 0x05, 0x49, 0x51, 0x51, 0x4a, 0x42, 0x06, 0x06, 0x06, 0x49, 0x49,
++    0x42, 0x49, 0x4a, 0x42, 0x49, 0x51, 0x49, 0x05, 0x49, 0x51, 0x51, 0x4a, 0x42, 0x06, 0x06, 0x06,
++    0x16, 0x48, 0x14, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x04, 0x07, 0x18, 0x08, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x06, 0x06, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40,
++    0x40, 0x19, 0x19, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0f,
++    0x00, 0x29, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x10, 0x0e, 0x10, 0x15, 0x0e, 0x0e, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x47, 0x0f, 0x40, 0x50, 0x40, 0x10, 0x47, 0x4f, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f,
++    0x40, 0x40, 0x48, 0x0f, 0x48, 0x40, 0x06, 0x16, 0x16, 0x07, 0x07, 0x08, 0x40, 0x07, 0x40, 0x07,
++    0x50, 0x27, 0x0f, 0x10, 0x40, 0x48, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48,
++    0x48, 0x40, 0x48, 0x50, 0x48, 0x07, 0x48, 0x50, 0x50, 0x48, 0x40, 0x07, 0x07, 0x07, 0x48, 0x48,
++    0x40, 0x48, 0x48, 0x40, 0x48, 0x50, 0x48, 0x07, 0x48, 0x50, 0x50, 0x48, 0x40, 0x07, 0x07, 0x07,
++    0x17, 0x48, 0x16, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x07, 0x07, 0x06, 0x07, 0x18, 0x08, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x07, 0x07, 0x0f, 0x17, 0x0f, 0x17, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40,
++    0x40, 0x18, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x17, 0x17, 0x0f,
++    0x00, 0x28, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x10, 0x0f, 0x10, 0x17, 0x0f, 0x0f, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x48, 0x10, 0x00, 0x4f, 0x40, 0x0f, 0x48, 0x50, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f,
++    0x00, 0x00, 0x47, 0x10, 0x47, 0x00, 0x08, 0x18, 0x18, 0x07, 0x07, 0x07, 0x00, 0x08, 0x00, 0x07,
++    0x4f, 0x27, 0x10, 0x0f, 0x40, 0x47, 0x07, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47,
++    0x47, 0x00, 0x47, 0x4f, 0x47, 0x08, 0x47, 0x4f, 0x4f, 0x47, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47,
++    0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x47, 0x08, 0x47, 0x4f, 0x4f, 0x47, 0x00, 0x08, 0x08, 0x08,
++    0x18, 0x47, 0x18, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x08, 0x07, 0x17, 0x07, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40,
++    0x40, 0x17, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10,
++    0x40, 0x27, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0f, 0x10, 0x0f, 0x18, 0x10, 0x10, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x48, 0x11, 0x00, 0x4f, 0x40, 0x0e, 0x48, 0x51, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f,
++    0x00, 0x02, 0x46, 0x10, 0x46, 0x02, 0x0a, 0x1b, 0x1b, 0x07, 0x07, 0x07, 0x00, 0x08, 0x01, 0x07,
++    0x4e, 0x27, 0x11, 0x0f, 0x40, 0x47, 0x06, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x46, 0x01, 0x46,
++    0x46, 0x02, 0x47, 0x4e, 0x46, 0x0a, 0x46, 0x4e, 0x4e, 0x46, 0x01, 0x09, 0x08, 0x09, 0x47, 0x46,
++    0x01, 0x46, 0x46, 0x02, 0x47, 0x4e, 0x46, 0x0a, 0x46, 0x4e, 0x4e, 0x46, 0x01, 0x09, 0x08, 0x09,
++    0x18, 0x47, 0x1a, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x0a, 0x07, 0x17, 0x07, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x08, 0x08, 0x11, 0x18, 0x11, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40,
++    0x40, 0x16, 0x16, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10,
++    0x40, 0x26, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0f, 0x11, 0x0f, 0x19, 0x10, 0x11, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x49, 0x12, 0x00, 0x4e, 0x40, 0x0d, 0x49, 0x52, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f,
++    0x00, 0x03, 0x45, 0x11, 0x45, 0x03, 0x0c, 0x1d, 0x1d, 0x07, 0x07, 0x07, 0x01, 0x08, 0x02, 0x07,
++    0x4d, 0x27, 0x12, 0x0f, 0x40, 0x47, 0x05, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x45, 0x02, 0x45,
++    0x45, 0x03, 0x46, 0x4d, 0x45, 0x0b, 0x45, 0x4d, 0x4d, 0x45, 0x02, 0x0a, 0x09, 0x0a, 0x46, 0x45,
++    0x02, 0x45, 0x45, 0x03, 0x46, 0x4d, 0x45, 0x0b, 0x45, 0x4d, 0x4d, 0x45, 0x02, 0x0a, 0x09, 0x0a,
++    0x19, 0x47, 0x1c, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x09, 0x09, 0x0c, 0x07, 0x17, 0x06, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x09, 0x09, 0x12, 0x19, 0x12, 0x19, 0x0f, 0x17, 0x06, 0x47, 0x17, 0x06, 0x47, 0x40, 0x40,
++    0x40, 0x15, 0x15, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x0e, 0x28, 0x27, 0x18, 0x07, 0x19, 0x18, 0x10,
++    0x40, 0x25, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0e, 0x12, 0x0f, 0x1a, 0x11, 0x12, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4a, 0x13, 0x01, 0x4d, 0x40, 0x0c, 0x4a, 0x53, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f,
++    0x01, 0x05, 0x44, 0x12, 0x43, 0x05, 0x0e, 0x20, 0x20, 0x07, 0x07, 0x06, 0x02, 0x09, 0x04, 0x07,
++    0x4c, 0x27, 0x13, 0x0e, 0x40, 0x46, 0x04, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x44, 0x04, 0x44,
++    0x43, 0x05, 0x45, 0x4c, 0x44, 0x0d, 0x44, 0x4c, 0x4c, 0x43, 0x04, 0x0b, 0x0a, 0x0b, 0x45, 0x44,
++    0x04, 0x44, 0x43, 0x05, 0x45, 0x4c, 0x44, 0x0d, 0x44, 0x4c, 0x4c, 0x43, 0x04, 0x0b, 0x0a, 0x0b,
++    0x1a, 0x46, 0x1e, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x0e, 0x07, 0x16, 0x05, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x0a, 0x0a, 0x13, 0x1a, 0x13, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40,
++    0x40, 0x14, 0x14, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x11,
++    0x41, 0x24, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0d, 0x13, 0x0e, 0x1c, 0x12, 0x13, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4a, 0x14, 0x01, 0x4d, 0x40, 0x0b, 0x4a, 0x54, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f,
++    0x01, 0x06, 0x43, 0x12, 0x42, 0x06, 0x10, 0x22, 0x22, 0x07, 0x07, 0x06, 0x02, 0x09, 0x05, 0x07,
++    0x4b, 0x27, 0x14, 0x0e, 0x40, 0x46, 0x03, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x43, 0x05, 0x43,
++    0x42, 0x06, 0x45, 0x4b, 0x43, 0x0e, 0x43, 0x4b, 0x4b, 0x42, 0x05, 0x0c, 0x0a, 0x0c, 0x45, 0x43,
++    0x05, 0x43, 0x42, 0x06, 0x45, 0x4b, 0x43, 0x0e, 0x43, 0x4b, 0x4b, 0x42, 0x05, 0x0c, 0x0a, 0x0c,
++    0x1a, 0x46, 0x20, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x10, 0x07, 0x16, 0x05, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x0a, 0x0a, 0x14, 0x1a, 0x14, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40,
++    0x40, 0x13, 0x13, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x11,
++    0x41, 0x23, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0d, 0x14, 0x0e, 0x1d, 0x12, 0x14, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4b, 0x15, 0x01, 0x4c, 0x40, 0x0a, 0x4b, 0x55, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f,
++    0x01, 0x08, 0x42, 0x13, 0x41, 0x08, 0x12, 0x25, 0x25, 0x07, 0x07, 0x06, 0x03, 0x09, 0x06, 0x07,
++    0x4a, 0x27, 0x15, 0x0e, 0x40, 0x46, 0x02, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x06, 0x42,
++    0x41, 0x08, 0x44, 0x4a, 0x42, 0x10, 0x42, 0x4a, 0x4a, 0x41, 0x06, 0x0d, 0x0b, 0x0d, 0x44, 0x42,
++    0x06, 0x42, 0x41, 0x08, 0x44, 0x4a, 0x42, 0x10, 0x42, 0x4a, 0x4a, 0x41, 0x06, 0x0d, 0x0b, 0x0d,
++    0x1b, 0x46, 0x22, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x12, 0x07, 0x16, 0x04, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x0b, 0x0b, 0x15, 0x1b, 0x15, 0x1b, 0x0e, 0x17, 0x04, 0x46, 0x17, 0x04, 0x46, 0x40, 0x40,
++    0x40, 0x12, 0x12, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x0c, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x11,
++    0x41, 0x22, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0c, 0x15, 0x0e, 0x1e, 0x13, 0x15, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4c, 0x15, 0x01, 0x4c, 0x40, 0x09, 0x4c, 0x56, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f,
++    0x01, 0x09, 0x42, 0x13, 0x40, 0x09, 0x13, 0x27, 0x27, 0x07, 0x07, 0x05, 0x03, 0x09, 0x07, 0x07,
++    0x4a, 0x27, 0x15, 0x0d, 0x40, 0x46, 0x01, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x07, 0x42,
++    0x40, 0x09, 0x44, 0x4a, 0x42, 0x11, 0x42, 0x4a, 0x4a, 0x40, 0x07, 0x0d, 0x0b, 0x0d, 0x44, 0x42,
++    0x07, 0x42, 0x40, 0x09, 0x44, 0x4a, 0x42, 0x11, 0x42, 0x4a, 0x4a, 0x40, 0x07, 0x0d, 0x0b, 0x0d,
++    0x1b, 0x46, 0x23, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x13, 0x07, 0x15, 0x03, 0x46,
++    0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x4a,
++    0x07, 0x0b, 0x0b, 0x15, 0x1b, 0x15, 0x1b, 0x0d, 0x17, 0x03, 0x46, 0x17, 0x03, 0x46, 0x40, 0x40,
++    0x40, 0x11, 0x11, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x11,
++    0x42, 0x21, 0x15, 0x0d, 0x40, 0x0d, 0x11, 0x0b, 0x15, 0x0d, 0x1f, 0x13, 0x15, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4c, 0x16, 0x02, 0x4b, 0x40, 0x09, 0x4c, 0x56, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f,
++    0x02, 0x0b, 0x41, 0x14, 0x01, 0x0b, 0x15, 0x2a, 0x2a, 0x07, 0x07, 0x05, 0x04, 0x0a, 0x09, 0x07,
++    0x49, 0x27, 0x16, 0x0d, 0x40, 0x45, 0x01, 0x40, 0x40, 0x40, 0x02, 0x02, 0x43, 0x41, 0x09, 0x41,
++    0x01, 0x0b, 0x43, 0x49, 0x41, 0x13, 0x41, 0x49, 0x49, 0x01, 0x09, 0x0e, 0x0c, 0x0e, 0x43, 0x41,
++    0x09, 0x41, 0x01, 0x0b, 0x43, 0x49, 0x41, 0x13, 0x41, 0x49, 0x49, 0x01, 0x09, 0x0e, 0x0c, 0x0e,
++    0x1c, 0x45, 0x25, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0c, 0x0c, 0x15, 0x07, 0x15, 0x03, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0c, 0x0c, 0x16, 0x1c, 0x16, 0x1c, 0x0d, 0x17, 0x03, 0x45, 0x17, 0x03, 0x45, 0x40, 0x40,
++    0x40, 0x11, 0x11, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x2a, 0x27, 0x1a, 0x07, 0x1c, 0x1a, 0x12,
++    0x42, 0x21, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0b, 0x16, 0x0d, 0x21, 0x14, 0x16, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4d, 0x17, 0x02, 0x4a, 0x40, 0x08, 0x4d, 0x57, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f,
++    0x02, 0x0d, 0x40, 0x15, 0x02, 0x0d, 0x17, 0x2c, 0x2c, 0x07, 0x07, 0x05, 0x05, 0x0a, 0x0a, 0x07,
++    0x48, 0x27, 0x17, 0x0d, 0x40, 0x45, 0x00, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x40, 0x0a, 0x40,
++    0x02, 0x0d, 0x42, 0x48, 0x40, 0x15, 0x40, 0x48, 0x48, 0x02, 0x0a, 0x0f, 0x0d, 0x0f, 0x42, 0x40,
++    0x0a, 0x40, 0x02, 0x0d, 0x42, 0x48, 0x40, 0x15, 0x40, 0x48, 0x48, 0x02, 0x0a, 0x0f, 0x0d, 0x0f,
++    0x1d, 0x45, 0x27, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x17, 0x07, 0x15, 0x02, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0d, 0x0d, 0x17, 0x1d, 0x17, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40,
++    0x40, 0x10, 0x10, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x12,
++    0x42, 0x20, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0a, 0x17, 0x0d, 0x22, 0x15, 0x17, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4d, 0x18, 0x02, 0x4a, 0x40, 0x07, 0x4d, 0x58, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f,
++    0x02, 0x0e, 0x00, 0x15, 0x03, 0x0e, 0x19, 0x2f, 0x2f, 0x07, 0x07, 0x05, 0x05, 0x0a, 0x0b, 0x07,
++    0x47, 0x27, 0x18, 0x0d, 0x40, 0x45, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x00, 0x0b, 0x00,
++    0x03, 0x0e, 0x42, 0x47, 0x00, 0x16, 0x00, 0x47, 0x47, 0x03, 0x0b, 0x10, 0x0d, 0x10, 0x42, 0x00,
++    0x0b, 0x00, 0x03, 0x0e, 0x42, 0x47, 0x00, 0x16, 0x00, 0x47, 0x47, 0x03, 0x0b, 0x10, 0x0d, 0x10,
++    0x1d, 0x45, 0x29, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x19, 0x07, 0x15, 0x02, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0d, 0x0d, 0x18, 0x1d, 0x18, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40,
++    0x40, 0x0f, 0x0f, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x12,
++    0x42, 0x1f, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0a, 0x18, 0x0d, 0x23, 0x15, 0x18, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4e, 0x19, 0x03, 0x49, 0x40, 0x06, 0x4e, 0x59, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f,
++    0x03, 0x10, 0x01, 0x16, 0x04, 0x10, 0x1b, 0x31, 0x31, 0x07, 0x07, 0x04, 0x06, 0x0b, 0x0c, 0x07,
++    0x46, 0x27, 0x19, 0x0c, 0x40, 0x44, 0x41, 0x40, 0x40, 0x40, 0x03, 0x03, 0x41, 0x01, 0x0c, 0x01,
++    0x04, 0x10, 0x41, 0x46, 0x01, 0x18, 0x01, 0x46, 0x46, 0x04, 0x0c, 0x11, 0x0e, 0x11, 0x41, 0x01,
++    0x0c, 0x01, 0x04, 0x10, 0x41, 0x46, 0x01, 0x18, 0x01, 0x46, 0x46, 0x04, 0x0c, 0x11, 0x0e, 0x11,
++    0x1e, 0x44, 0x2b, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0e, 0x0e, 0x1b, 0x07, 0x14, 0x01, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0e, 0x0e, 0x19, 0x1e, 0x19, 0x1e, 0x0c, 0x17, 0x01, 0x44, 0x17, 0x01, 0x44, 0x40, 0x40,
++    0x40, 0x0e, 0x0e, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x09, 0x2b, 0x27, 0x1b, 0x07, 0x1e, 0x1b, 0x13,
++    0x43, 0x1e, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x09, 0x19, 0x0c, 0x24, 0x16, 0x19, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4f, 0x1a, 0x03, 0x48, 0x40, 0x05, 0x4f, 0x5a, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f,
++    0x03, 0x11, 0x02, 0x17, 0x06, 0x11, 0x1d, 0x34, 0x34, 0x07, 0x07, 0x04, 0x07, 0x0b, 0x0e, 0x07,
++    0x45, 0x27, 0x1a, 0x0c, 0x40, 0x44, 0x42, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x02, 0x0e, 0x02,
++    0x06, 0x11, 0x40, 0x45, 0x02, 0x19, 0x02, 0x45, 0x45, 0x06, 0x0e, 0x12, 0x0f, 0x12, 0x40, 0x02,
++    0x0e, 0x02, 0x06, 0x11, 0x40, 0x45, 0x02, 0x19, 0x02, 0x45, 0x45, 0x06, 0x0e, 0x12, 0x0f, 0x12,
++    0x1f, 0x44, 0x2d, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1d, 0x07, 0x14, 0x00, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0f, 0x0f, 0x1a, 0x1f, 0x1a, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40,
++    0x40, 0x0d, 0x0d, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x13,
++    0x43, 0x1d, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x08, 0x1a, 0x0c, 0x26, 0x17, 0x1a, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x4f, 0x1b, 0x03, 0x48, 0x40, 0x04, 0x4f, 0x5b, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f,
++    0x03, 0x13, 0x03, 0x17, 0x07, 0x13, 0x1f, 0x36, 0x36, 0x07, 0x07, 0x04, 0x07, 0x0b, 0x0f, 0x07,
++    0x44, 0x27, 0x1b, 0x0c, 0x40, 0x44, 0x43, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x03, 0x0f, 0x03,
++    0x07, 0x13, 0x40, 0x44, 0x03, 0x1b, 0x03, 0x44, 0x44, 0x07, 0x0f, 0x13, 0x0f, 0x13, 0x40, 0x03,
++    0x0f, 0x03, 0x07, 0x13, 0x40, 0x44, 0x03, 0x1b, 0x03, 0x44, 0x44, 0x07, 0x0f, 0x13, 0x0f, 0x13,
++    0x1f, 0x44, 0x2f, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1f, 0x07, 0x14, 0x00, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0f, 0x0f, 0x1b, 0x1f, 0x1b, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40,
++    0x40, 0x0c, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x13,
++    0x43, 0x1c, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x08, 0x1b, 0x0c, 0x27, 0x17, 0x1b, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x50, 0x1c, 0x04, 0x47, 0x40, 0x03, 0x50, 0x5c, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f,
++    0x04, 0x14, 0x04, 0x18, 0x08, 0x14, 0x21, 0x39, 0x39, 0x07, 0x07, 0x03, 0x08, 0x0c, 0x10, 0x07,
++    0x43, 0x27, 0x1c, 0x0b, 0x40, 0x43, 0x44, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x04, 0x10, 0x04,
++    0x08, 0x14, 0x00, 0x43, 0x04, 0x1c, 0x04, 0x43, 0x43, 0x08, 0x10, 0x14, 0x10, 0x14, 0x00, 0x04,
++    0x10, 0x04, 0x08, 0x14, 0x00, 0x43, 0x04, 0x1c, 0x04, 0x43, 0x43, 0x08, 0x10, 0x14, 0x10, 0x14,
++    0x20, 0x43, 0x31, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x21, 0x07, 0x13, 0x40, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x10, 0x10, 0x1c, 0x20, 0x1c, 0x20, 0x0b, 0x17, 0x40, 0x43, 0x17, 0x40, 0x43, 0x40, 0x40,
++    0x40, 0x0b, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x07, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x14,
++    0x44, 0x1b, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x07, 0x1c, 0x0b, 0x28, 0x18, 0x1c, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x51, 0x1d, 0x04, 0x47, 0x40, 0x02, 0x51, 0x5d, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f,
++    0x04, 0x16, 0x05, 0x18, 0x09, 0x16, 0x22, 0x3b, 0x3b, 0x07, 0x07, 0x03, 0x08, 0x0c, 0x11, 0x07,
++    0x42, 0x27, 0x1d, 0x0b, 0x40, 0x43, 0x45, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x05, 0x11, 0x05,
++    0x09, 0x16, 0x00, 0x42, 0x05, 0x1e, 0x05, 0x42, 0x42, 0x09, 0x11, 0x15, 0x10, 0x15, 0x00, 0x05,
++    0x11, 0x05, 0x09, 0x16, 0x00, 0x42, 0x05, 0x1e, 0x05, 0x42, 0x42, 0x09, 0x11, 0x15, 0x10, 0x15,
++    0x20, 0x43, 0x32, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x22, 0x07, 0x13, 0x41, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x10, 0x10, 0x1d, 0x20, 0x1d, 0x20, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40,
++    0x40, 0x0a, 0x0a, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x14,
++    0x44, 0x1a, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x06, 0x1d, 0x0b, 0x29, 0x18, 0x1d, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x51, 0x1e, 0x04, 0x46, 0x40, 0x01, 0x51, 0x5e, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f,
++    0x04, 0x18, 0x06, 0x19, 0x0b, 0x18, 0x24, 0x3e, 0x3e, 0x07, 0x07, 0x03, 0x09, 0x0c, 0x13, 0x07,
++    0x41, 0x27, 0x1e, 0x0b, 0x40, 0x43, 0x46, 0x40, 0x40, 0x40, 0x04, 0x04, 0x01, 0x06, 0x13, 0x06,
++    0x0b, 0x18, 0x01, 0x41, 0x06, 0x20, 0x06, 0x41, 0x41, 0x0b, 0x13, 0x16, 0x11, 0x16, 0x01, 0x06,
++    0x13, 0x06, 0x0b, 0x18, 0x01, 0x41, 0x06, 0x20, 0x06, 0x41, 0x41, 0x0b, 0x13, 0x16, 0x11, 0x16,
++    0x21, 0x43, 0x34, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x11, 0x11, 0x24, 0x07, 0x13, 0x41, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x11, 0x11, 0x1e, 0x21, 0x1e, 0x21, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40,
++    0x40, 0x09, 0x09, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x21, 0x1c, 0x14,
++    0x44, 0x19, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x06, 0x1e, 0x0b, 0x2b, 0x19, 0x1e, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x52, 0x1f, 0x05, 0x45, 0x40, 0x00, 0x52, 0x5f, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f,
++    0x05, 0x19, 0x07, 0x1a, 0x0c, 0x19, 0x26, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0a, 0x0d, 0x14, 0x07,
++    0x40, 0x27, 0x1f, 0x0a, 0x40, 0x42, 0x47, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x07, 0x14, 0x07,
++    0x0c, 0x19, 0x02, 0x40, 0x07, 0x21, 0x07, 0x40, 0x40, 0x0c, 0x14, 0x17, 0x12, 0x17, 0x02, 0x07,
++    0x14, 0x07, 0x0c, 0x19, 0x02, 0x40, 0x07, 0x21, 0x07, 0x40, 0x40, 0x0c, 0x14, 0x17, 0x12, 0x17,
++    0x22, 0x42, 0x36, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x26, 0x07, 0x12, 0x42, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x12, 0x12, 0x1f, 0x22, 0x1f, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40,
++    0x40, 0x08, 0x08, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x15,
++    0x45, 0x18, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x05, 0x1f, 0x0a, 0x2c, 0x1a, 0x1f, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x52, 0x20, 0x05, 0x45, 0x40, 0x40, 0x52, 0x60, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f,
++    0x05, 0x1b, 0x08, 0x1a, 0x0d, 0x1b, 0x28, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0a, 0x0d, 0x15, 0x07,
++    0x00, 0x27, 0x20, 0x0a, 0x40, 0x42, 0x48, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x08, 0x15, 0x08,
++    0x0d, 0x1b, 0x02, 0x00, 0x08, 0x23, 0x08, 0x00, 0x00, 0x0d, 0x15, 0x18, 0x12, 0x18, 0x02, 0x08,
++    0x15, 0x08, 0x0d, 0x1b, 0x02, 0x00, 0x08, 0x23, 0x08, 0x00, 0x00, 0x0d, 0x15, 0x18, 0x12, 0x18,
++    0x22, 0x42, 0x38, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x28, 0x07, 0x12, 0x42, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x12, 0x12, 0x20, 0x22, 0x20, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40,
++    0x40, 0x07, 0x07, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x15,
++    0x45, 0x17, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x05, 0x20, 0x0a, 0x2d, 0x1a, 0x20, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x53, 0x21, 0x05, 0x44, 0x40, 0x41, 0x53, 0x61, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f,
++    0x05, 0x1c, 0x09, 0x1b, 0x0e, 0x1c, 0x2a, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0d, 0x16, 0x07,
++    0x01, 0x27, 0x21, 0x0a, 0x40, 0x42, 0x49, 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x16, 0x09,
++    0x0e, 0x1c, 0x03, 0x01, 0x09, 0x24, 0x09, 0x01, 0x01, 0x0e, 0x16, 0x19, 0x13, 0x19, 0x03, 0x09,
++    0x16, 0x09, 0x0e, 0x1c, 0x03, 0x01, 0x09, 0x24, 0x09, 0x01, 0x01, 0x0e, 0x16, 0x19, 0x13, 0x19,
++    0x23, 0x42, 0x3a, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x07, 0x12, 0x43, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x13, 0x13, 0x21, 0x23, 0x21, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, 0x40,
++    0x40, 0x06, 0x06, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, 0x1d, 0x15,
++    0x45, 0x16, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x04, 0x21, 0x0a, 0x2e, 0x1b, 0x21, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x54, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f,
++    0x06, 0x1e, 0x0a, 0x1c, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0c, 0x0e, 0x18, 0x07,
++    0x02, 0x27, 0x22, 0x09, 0x40, 0x41, 0x4a, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0a, 0x18, 0x0a,
++    0x10, 0x1e, 0x04, 0x02, 0x0a, 0x26, 0x0a, 0x02, 0x02, 0x10, 0x18, 0x1a, 0x14, 0x1a, 0x04, 0x0a,
++    0x18, 0x0a, 0x10, 0x1e, 0x04, 0x02, 0x0a, 0x26, 0x0a, 0x02, 0x02, 0x10, 0x18, 0x1a, 0x14, 0x1a,
++    0x24, 0x41, 0x3c, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2c, 0x07, 0x11, 0x44, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x14, 0x14, 0x22, 0x24, 0x22, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
++    0x40, 0x05, 0x05, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x16,
++    0x46, 0x15, 0x11, 0x09, 0x40, 0x09, 0x16, 0x03, 0x22, 0x09, 0x30, 0x1c, 0x22, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x54, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f,
++    0x06, 0x1f, 0x0b, 0x1c, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0c, 0x0e, 0x19, 0x07,
++    0x03, 0x27, 0x23, 0x09, 0x40, 0x41, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x19, 0x0b,
++    0x11, 0x1f, 0x04, 0x03, 0x0b, 0x27, 0x0b, 0x03, 0x03, 0x11, 0x19, 0x1b, 0x14, 0x1b, 0x04, 0x0b,
++    0x19, 0x0b, 0x11, 0x1f, 0x04, 0x03, 0x0b, 0x27, 0x0b, 0x03, 0x03, 0x11, 0x19, 0x1b, 0x14, 0x1b,
++    0x24, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, 0x07, 0x11, 0x44, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x14, 0x14, 0x23, 0x24, 0x23, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
++    0x40, 0x04, 0x04, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x16,
++    0x46, 0x14, 0x11, 0x09, 0x40, 0x09, 0x16, 0x03, 0x23, 0x09, 0x31, 0x1c, 0x23, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x55, 0x24, 0x06, 0x42, 0x40, 0x44, 0x55, 0x64, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f,
++    0x06, 0x21, 0x0c, 0x1d, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0d, 0x0e, 0x1a, 0x07,
++    0x04, 0x27, 0x24, 0x09, 0x40, 0x41, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x1a, 0x0c,
++    0x12, 0x21, 0x05, 0x04, 0x0c, 0x29, 0x0c, 0x04, 0x04, 0x12, 0x1a, 0x1c, 0x15, 0x1c, 0x05, 0x0c,
++    0x1a, 0x0c, 0x12, 0x21, 0x05, 0x04, 0x0c, 0x29, 0x0c, 0x04, 0x04, 0x12, 0x1a, 0x1c, 0x15, 0x1c,
++    0x25, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x07, 0x11, 0x45, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x15, 0x15, 0x24, 0x25, 0x24, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, 0x40, 0x40,
++    0x40, 0x03, 0x03, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x16,
++    0x46, 0x13, 0x11, 0x09, 0x40, 0x09, 0x16, 0x02, 0x24, 0x09, 0x32, 0x1d, 0x24, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x56, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f,
++    0x06, 0x22, 0x0c, 0x1d, 0x13, 0x22, 0x31, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0d, 0x0e, 0x1b, 0x07,
++    0x04, 0x27, 0x24, 0x08, 0x40, 0x41, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x1b, 0x0c,
++    0x13, 0x22, 0x05, 0x04, 0x0c, 0x2a, 0x0c, 0x04, 0x04, 0x13, 0x1b, 0x1c, 0x15, 0x1c, 0x05, 0x0c,
++    0x1b, 0x0c, 0x13, 0x22, 0x05, 0x04, 0x0c, 0x2a, 0x0c, 0x04, 0x04, 0x13, 0x1b, 0x1c, 0x15, 0x1c,
++    0x25, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x07, 0x10, 0x46, 0x41,
++    0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f,
++    0x07, 0x15, 0x15, 0x24, 0x25, 0x24, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40,
++    0x40, 0x02, 0x02, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x16,
++    0x47, 0x12, 0x10, 0x08, 0x40, 0x08, 0x16, 0x01, 0x24, 0x08, 0x33, 0x1d, 0x24, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x56, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f,
++    0x07, 0x24, 0x0d, 0x1e, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0e, 0x0f, 0x1d, 0x07,
++    0x05, 0x27, 0x25, 0x08, 0x40, 0x40, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x1d, 0x0d,
++    0x15, 0x24, 0x06, 0x05, 0x0d, 0x2c, 0x0d, 0x05, 0x05, 0x15, 0x1d, 0x1d, 0x16, 0x1d, 0x06, 0x0d,
++    0x1d, 0x0d, 0x15, 0x24, 0x06, 0x05, 0x0d, 0x2c, 0x0d, 0x05, 0x05, 0x15, 0x1d, 0x1d, 0x16, 0x1d,
++    0x26, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x07, 0x10, 0x46, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x16, 0x16, 0x25, 0x26, 0x25, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40,
++    0x40, 0x02, 0x02, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x17,
++    0x47, 0x12, 0x10, 0x08, 0x40, 0x08, 0x17, 0x01, 0x25, 0x08, 0x35, 0x1e, 0x25, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x57, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f,
++    0x07, 0x26, 0x0e, 0x1f, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0f, 0x0f, 0x1e, 0x07,
++    0x06, 0x27, 0x26, 0x08, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x1e, 0x0e,
++    0x16, 0x26, 0x07, 0x06, 0x0e, 0x2e, 0x0e, 0x06, 0x06, 0x16, 0x1e, 0x1e, 0x17, 0x1e, 0x07, 0x0e,
++    0x1e, 0x0e, 0x16, 0x26, 0x07, 0x06, 0x0e, 0x2e, 0x0e, 0x06, 0x06, 0x16, 0x1e, 0x1e, 0x17, 0x1e,
++    0x27, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x07, 0x10, 0x47, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x17, 0x17, 0x26, 0x27, 0x26, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
++    0x40, 0x01, 0x01, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x17,
++    0x47, 0x11, 0x10, 0x08, 0x40, 0x08, 0x17, 0x00, 0x26, 0x08, 0x36, 0x1f, 0x26, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x57, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f,
++    0x07, 0x27, 0x0f, 0x1f, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0f, 0x0f, 0x1f, 0x07,
++    0x07, 0x27, 0x27, 0x08, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x1f, 0x0f,
++    0x17, 0x27, 0x07, 0x07, 0x0f, 0x2f, 0x0f, 0x07, 0x07, 0x17, 0x1f, 0x1f, 0x17, 0x1f, 0x07, 0x0f,
++    0x1f, 0x0f, 0x17, 0x27, 0x07, 0x07, 0x0f, 0x2f, 0x0f, 0x07, 0x07, 0x17, 0x1f, 0x1f, 0x17, 0x1f,
++    0x27, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x07, 0x10, 0x47, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x17, 0x17, 0x27, 0x27, 0x27, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
++    0x40, 0x00, 0x00, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x17,
++    0x47, 0x10, 0x10, 0x08, 0x40, 0x08, 0x17, 0x00, 0x27, 0x08, 0x37, 0x1f, 0x27, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x48, 0x48, 0x60, 0x40, 0x27, 0x07, 0x07, 0x1f, 0x40, 0x48, 0x40, 0x40, 0x17, 0x0f,
++    0x48, 0x68, 0x40, 0x07, 0x68, 0x68, 0x68, 0x68, 0x68, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x40, 0x07,
++    0x68, 0x27, 0x50, 0x17, 0x40, 0x07, 0x1f, 0x40, 0x40, 0x40, 0x48, 0x48, 0x58, 0x60, 0x50, 0x60,
++    0x68, 0x60, 0x58, 0x68, 0x68, 0x68, 0x58, 0x60, 0x68, 0x68, 0x68, 0x50, 0x48, 0x58, 0x58, 0x60,
++    0x50, 0x60, 0x68, 0x60, 0x58, 0x68, 0x68, 0x68, 0x58, 0x60, 0x68, 0x68, 0x68, 0x50, 0x48, 0x58,
++    0x07, 0x50, 0x58, 0x40, 0x40, 0x40, 0x48, 0x07, 0x48, 0x48, 0x48, 0x68, 0x50, 0x1f, 0x17, 0x50,
++    0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x40,
++    0x07, 0x40, 0x40, 0x40, 0x07, 0x40, 0x07, 0x17, 0x17, 0x17, 0x50, 0x17, 0x17, 0x50, 0x40, 0x40,
++    0x40, 0x2f, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x1f, 0x27, 0x0f, 0x07, 0x07, 0x0f, 0x40,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x48, 0x17, 0x48, 0x48, 0x48, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x47, 0x47, 0x5f, 0x40, 0x27, 0x07, 0x07, 0x20, 0x40, 0x47, 0x40, 0x40, 0x17, 0x0f,
++    0x47, 0x66, 0x40, 0x08, 0x66, 0x66, 0x66, 0x65, 0x65, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x00, 0x07,
++    0x67, 0x27, 0x4e, 0x17, 0x40, 0x07, 0x1f, 0x40, 0x40, 0x40, 0x47, 0x47, 0x57, 0x5f, 0x4f, 0x5f,
++    0x66, 0x5e, 0x57, 0x67, 0x67, 0x66, 0x57, 0x5f, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x56, 0x57, 0x5f,
++    0x4f, 0x5f, 0x66, 0x5e, 0x57, 0x67, 0x67, 0x66, 0x57, 0x5f, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x56,
++    0x08, 0x4f, 0x56, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x47, 0x47, 0x66, 0x4f, 0x1f, 0x17, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x17, 0x17, 0x17, 0x4f, 0x17, 0x17, 0x4f, 0x40, 0x40,
++    0x40, 0x2f, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x20, 0x27, 0x10, 0x07, 0x08, 0x10, 0x00,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x47, 0x17, 0x46, 0x47, 0x47, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x46, 0x47, 0x5e, 0x40, 0x26, 0x06, 0x06, 0x20, 0x40, 0x47, 0x40, 0x40, 0x16, 0x0f,
++    0x47, 0x64, 0x40, 0x08, 0x65, 0x64, 0x64, 0x63, 0x63, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x01, 0x07,
++    0x66, 0x27, 0x4d, 0x17, 0x40, 0x07, 0x1e, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5e, 0x4e, 0x5e,
++    0x65, 0x5d, 0x56, 0x66, 0x66, 0x64, 0x56, 0x5e, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x55, 0x56, 0x5e,
++    0x4e, 0x5e, 0x65, 0x5d, 0x56, 0x66, 0x66, 0x64, 0x56, 0x5e, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x55,
++    0x09, 0x4f, 0x54, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x64, 0x4e, 0x1f, 0x16, 0x4f,
++    0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40,
++    0x07, 0x00, 0x00, 0x01, 0x09, 0x01, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40,
++    0x40, 0x2e, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x01,
++    0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x46, 0x17, 0x45, 0x46, 0x46, 0x17, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x45, 0x47, 0x5e, 0x40, 0x25, 0x06, 0x05, 0x20, 0x40, 0x47, 0x40, 0x40, 0x16, 0x0f,
++    0x47, 0x63, 0x40, 0x08, 0x64, 0x63, 0x62, 0x60, 0x60, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x01, 0x07,
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++    0x63, 0x5b, 0x55, 0x64, 0x64, 0x61, 0x55, 0x5d, 0x64, 0x64, 0x61, 0x4c, 0x45, 0x53, 0x55, 0x5c,
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++    0x0a, 0x4e, 0x50, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x45, 0x45, 0x60, 0x4d, 0x1e, 0x15, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x41,
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++    0x40, 0x2c, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x1d, 0x21, 0x27, 0x11, 0x07, 0x0a, 0x11, 0x02,
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++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x43, 0x46, 0x5c, 0x40, 0x23, 0x04, 0x03, 0x21, 0x40, 0x46, 0x40, 0x40, 0x14, 0x0f,
++    0x46, 0x60, 0x40, 0x09, 0x61, 0x60, 0x5e, 0x5b, 0x5b, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x03, 0x07,
++    0x63, 0x27, 0x49, 0x16, 0x40, 0x06, 0x1b, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5b, 0x4c, 0x5b,
++    0x61, 0x59, 0x54, 0x63, 0x63, 0x60, 0x54, 0x5c, 0x63, 0x63, 0x60, 0x4b, 0x44, 0x51, 0x54, 0x5b,
++    0x4c, 0x5b, 0x61, 0x59, 0x54, 0x63, 0x63, 0x60, 0x54, 0x5c, 0x63, 0x63, 0x60, 0x4b, 0x44, 0x51,
++    0x0b, 0x4e, 0x4e, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5e, 0x4c, 0x1e, 0x14, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x01, 0x01, 0x03, 0x0b, 0x03, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40,
++    0x40, 0x2b, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x03,
++    0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x43, 0x16, 0x41, 0x43, 0x43, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x42, 0x46, 0x5c, 0x40, 0x22, 0x04, 0x02, 0x21, 0x40, 0x46, 0x40, 0x40, 0x14, 0x0f,
++    0x46, 0x5e, 0x40, 0x09, 0x60, 0x5e, 0x5c, 0x59, 0x59, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x03, 0x07,
++    0x62, 0x27, 0x48, 0x16, 0x40, 0x06, 0x1a, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5a, 0x4c, 0x5a,
++    0x60, 0x58, 0x54, 0x62, 0x62, 0x5e, 0x54, 0x5c, 0x62, 0x62, 0x5e, 0x4a, 0x44, 0x50, 0x54, 0x5a,
++    0x4c, 0x5a, 0x60, 0x58, 0x54, 0x62, 0x62, 0x5e, 0x54, 0x5c, 0x62, 0x62, 0x5e, 0x4a, 0x44, 0x50,
++    0x0b, 0x4e, 0x4c, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5c, 0x4c, 0x1e, 0x14, 0x4e,
++    0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41,
++    0x07, 0x01, 0x01, 0x03, 0x0b, 0x03, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40,
++    0x40, 0x2a, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x03,
++    0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x42, 0x16, 0x40, 0x42, 0x42, 0x16, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x41, 0x45, 0x5b, 0x40, 0x21, 0x03, 0x01, 0x22, 0x40, 0x45, 0x40, 0x40, 0x13, 0x0f,
++    0x45, 0x5d, 0x40, 0x0a, 0x5f, 0x5d, 0x5a, 0x56, 0x56, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x04, 0x07,
++    0x61, 0x27, 0x47, 0x15, 0x40, 0x05, 0x19, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x59, 0x4b, 0x59,
++    0x5f, 0x57, 0x53, 0x61, 0x61, 0x5d, 0x53, 0x5b, 0x61, 0x61, 0x5d, 0x49, 0x43, 0x4f, 0x53, 0x59,
++    0x4b, 0x59, 0x5f, 0x57, 0x53, 0x61, 0x61, 0x5d, 0x53, 0x5b, 0x61, 0x61, 0x5d, 0x49, 0x43, 0x4f,
++    0x0c, 0x4d, 0x4a, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x5a, 0x4b, 0x1d, 0x13, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x02, 0x02, 0x04, 0x0c, 0x04, 0x0c, 0x15, 0x17, 0x13, 0x4d, 0x17, 0x13, 0x4d, 0x40, 0x40,
++    0x40, 0x29, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x1b, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x04,
++    0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x41, 0x15, 0x00, 0x41, 0x41, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x40, 0x45, 0x5b, 0x40, 0x20, 0x02, 0x00, 0x22, 0x40, 0x45, 0x40, 0x40, 0x12, 0x0f,
++    0x45, 0x5b, 0x40, 0x0a, 0x5e, 0x5b, 0x59, 0x54, 0x54, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x04, 0x07,
++    0x60, 0x27, 0x46, 0x15, 0x40, 0x05, 0x18, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x58, 0x4b, 0x58,
++    0x5e, 0x56, 0x53, 0x60, 0x60, 0x5b, 0x53, 0x5b, 0x60, 0x60, 0x5b, 0x48, 0x43, 0x4e, 0x53, 0x58,
++    0x4b, 0x58, 0x5e, 0x56, 0x53, 0x60, 0x60, 0x5b, 0x53, 0x5b, 0x60, 0x60, 0x5b, 0x48, 0x43, 0x4e,
++    0x0c, 0x4d, 0x49, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x59, 0x4b, 0x1d, 0x12, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x02, 0x02, 0x04, 0x0c, 0x04, 0x0c, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40,
++    0x40, 0x28, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x04,
++    0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x40, 0x15, 0x01, 0x40, 0x40, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x00, 0x45, 0x5a, 0x40, 0x1f, 0x02, 0x40, 0x22, 0x40, 0x45, 0x40, 0x40, 0x12, 0x0f,
++    0x45, 0x59, 0x40, 0x0a, 0x5c, 0x59, 0x57, 0x51, 0x51, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x05, 0x07,
++    0x5f, 0x27, 0x44, 0x15, 0x40, 0x05, 0x17, 0x40, 0x40, 0x40, 0x45, 0x45, 0x52, 0x57, 0x4a, 0x57,
++    0x5c, 0x54, 0x52, 0x5f, 0x5f, 0x59, 0x52, 0x5a, 0x5f, 0x5f, 0x59, 0x47, 0x42, 0x4c, 0x52, 0x57,
++    0x4a, 0x57, 0x5c, 0x54, 0x52, 0x5f, 0x5f, 0x59, 0x52, 0x5a, 0x5f, 0x5f, 0x59, 0x47, 0x42, 0x4c,
++    0x0d, 0x4d, 0x47, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x42, 0x42, 0x57, 0x4a, 0x1d, 0x12, 0x4d,
++    0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42,
++    0x07, 0x02, 0x02, 0x05, 0x0d, 0x05, 0x0d, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40,
++    0x40, 0x27, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0d, 0x12, 0x05,
++    0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x00, 0x15, 0x03, 0x00, 0x00, 0x15, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x01, 0x44, 0x59, 0x40, 0x1e, 0x01, 0x41, 0x23, 0x40, 0x44, 0x40, 0x40, 0x11, 0x0f,
++    0x44, 0x58, 0x40, 0x0b, 0x5b, 0x58, 0x55, 0x4f, 0x4f, 0x07, 0x07, 0x0c, 0x3e, 0x14, 0x06, 0x07,
++    0x5e, 0x27, 0x43, 0x14, 0x40, 0x04, 0x16, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x56, 0x49, 0x56,
++    0x5b, 0x53, 0x51, 0x5e, 0x5e, 0x58, 0x51, 0x59, 0x5e, 0x5e, 0x58, 0x46, 0x41, 0x4b, 0x51, 0x56,
++    0x49, 0x56, 0x5b, 0x53, 0x51, 0x5e, 0x5e, 0x58, 0x51, 0x59, 0x5e, 0x5e, 0x58, 0x46, 0x41, 0x4b,
++    0x0e, 0x4c, 0x45, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x55, 0x49, 0x1c, 0x11, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x03, 0x03, 0x06, 0x0e, 0x06, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40,
++    0x40, 0x26, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x06,
++    0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x01, 0x14, 0x04, 0x01, 0x01, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x02, 0x44, 0x59, 0x40, 0x1d, 0x01, 0x42, 0x23, 0x40, 0x44, 0x40, 0x40, 0x11, 0x0f,
++    0x44, 0x56, 0x40, 0x0b, 0x5a, 0x56, 0x53, 0x4c, 0x4c, 0x07, 0x07, 0x0c, 0x3e, 0x14, 0x06, 0x07,
++    0x5d, 0x27, 0x42, 0x14, 0x40, 0x04, 0x15, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x55, 0x49, 0x55,
++    0x5a, 0x52, 0x51, 0x5d, 0x5d, 0x56, 0x51, 0x59, 0x5d, 0x5d, 0x56, 0x45, 0x41, 0x4a, 0x51, 0x55,
++    0x49, 0x55, 0x5a, 0x52, 0x51, 0x5d, 0x5d, 0x56, 0x51, 0x59, 0x5d, 0x5d, 0x56, 0x45, 0x41, 0x4a,
++    0x0e, 0x4c, 0x43, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x53, 0x49, 0x1c, 0x11, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x03, 0x03, 0x06, 0x0e, 0x06, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40,
++    0x40, 0x25, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x06,
++    0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x02, 0x14, 0x05, 0x02, 0x02, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x03, 0x44, 0x58, 0x40, 0x1c, 0x00, 0x43, 0x23, 0x40, 0x44, 0x40, 0x40, 0x10, 0x0f,
++    0x44, 0x55, 0x40, 0x0b, 0x59, 0x55, 0x51, 0x4a, 0x4a, 0x07, 0x07, 0x0c, 0x3d, 0x14, 0x07, 0x07,
++    0x5c, 0x27, 0x41, 0x14, 0x40, 0x04, 0x14, 0x40, 0x40, 0x40, 0x44, 0x44, 0x50, 0x54, 0x48, 0x54,
++    0x59, 0x51, 0x50, 0x5c, 0x5c, 0x55, 0x50, 0x58, 0x5c, 0x5c, 0x55, 0x44, 0x40, 0x49, 0x50, 0x54,
++    0x48, 0x54, 0x59, 0x51, 0x50, 0x5c, 0x5c, 0x55, 0x50, 0x58, 0x5c, 0x5c, 0x55, 0x44, 0x40, 0x49,
++    0x0f, 0x4c, 0x41, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x40, 0x40, 0x51, 0x48, 0x1c, 0x10, 0x4c,
++    0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x43,
++    0x07, 0x03, 0x03, 0x07, 0x0f, 0x07, 0x0f, 0x14, 0x17, 0x10, 0x4c, 0x17, 0x10, 0x4c, 0x40, 0x40,
++    0x40, 0x24, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x18, 0x23, 0x27, 0x13, 0x07, 0x0f, 0x13, 0x07,
++    0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x03, 0x14, 0x06, 0x03, 0x03, 0x14, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x04, 0x43, 0x57, 0x40, 0x1b, 0x40, 0x44, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0f, 0x0f,
++    0x43, 0x53, 0x40, 0x0c, 0x57, 0x53, 0x4f, 0x47, 0x47, 0x07, 0x07, 0x0b, 0x3b, 0x13, 0x08, 0x07,
++    0x5b, 0x27, 0x00, 0x13, 0x40, 0x03, 0x13, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x53, 0x47, 0x53,
++    0x57, 0x4f, 0x4f, 0x5b, 0x5b, 0x53, 0x4f, 0x57, 0x5b, 0x5b, 0x53, 0x43, 0x00, 0x47, 0x4f, 0x53,
++    0x47, 0x53, 0x57, 0x4f, 0x4f, 0x5b, 0x5b, 0x53, 0x4f, 0x57, 0x5b, 0x5b, 0x53, 0x43, 0x00, 0x47,
++    0x10, 0x4b, 0x00, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4f, 0x47, 0x1b, 0x0f, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x04, 0x04, 0x08, 0x10, 0x08, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40,
++    0x40, 0x23, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x08,
++    0x03, 0x3e, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x04, 0x13, 0x08, 0x04, 0x04, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x05, 0x43, 0x57, 0x40, 0x1a, 0x40, 0x45, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0f, 0x0f,
++    0x43, 0x52, 0x40, 0x0c, 0x56, 0x52, 0x4d, 0x45, 0x45, 0x07, 0x07, 0x0b, 0x3a, 0x13, 0x08, 0x07,
++    0x5a, 0x27, 0x01, 0x13, 0x40, 0x03, 0x12, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x52, 0x47, 0x52,
++    0x56, 0x4e, 0x4f, 0x5a, 0x5a, 0x52, 0x4f, 0x57, 0x5a, 0x5a, 0x52, 0x42, 0x00, 0x46, 0x4f, 0x52,
++    0x47, 0x52, 0x56, 0x4e, 0x4f, 0x5a, 0x5a, 0x52, 0x4f, 0x57, 0x5a, 0x5a, 0x52, 0x42, 0x00, 0x46,
++    0x10, 0x4b, 0x02, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4d, 0x47, 0x1b, 0x0f, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x04, 0x04, 0x08, 0x10, 0x08, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40,
++    0x40, 0x22, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x08,
++    0x03, 0x3e, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x05, 0x13, 0x09, 0x05, 0x05, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x06, 0x43, 0x56, 0x40, 0x19, 0x41, 0x46, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0e, 0x0f,
++    0x43, 0x50, 0x40, 0x0c, 0x55, 0x50, 0x4b, 0x42, 0x42, 0x07, 0x07, 0x0b, 0x38, 0x13, 0x09, 0x07,
++    0x59, 0x27, 0x02, 0x13, 0x40, 0x03, 0x11, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x46, 0x51,
++    0x55, 0x4d, 0x4e, 0x59, 0x59, 0x50, 0x4e, 0x56, 0x59, 0x59, 0x50, 0x41, 0x01, 0x45, 0x4e, 0x51,
++    0x46, 0x51, 0x55, 0x4d, 0x4e, 0x59, 0x59, 0x50, 0x4e, 0x56, 0x59, 0x59, 0x50, 0x41, 0x01, 0x45,
++    0x11, 0x4b, 0x04, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4b, 0x46, 0x1b, 0x0e, 0x4b,
++    0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x44,
++    0x07, 0x04, 0x04, 0x09, 0x11, 0x09, 0x11, 0x13, 0x17, 0x0e, 0x4b, 0x17, 0x0e, 0x4b, 0x40, 0x40,
++    0x40, 0x21, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x16, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x09,
++    0x03, 0x3d, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x06, 0x13, 0x0a, 0x06, 0x06, 0x13, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x06, 0x43, 0x56, 0x40, 0x18, 0x42, 0x47, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0d, 0x0f,
++    0x43, 0x4f, 0x40, 0x0c, 0x54, 0x4f, 0x4a, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x36, 0x12, 0x09, 0x07,
++    0x59, 0x27, 0x03, 0x12, 0x40, 0x02, 0x10, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x46, 0x51,
++    0x54, 0x4c, 0x4e, 0x59, 0x59, 0x4f, 0x4e, 0x56, 0x59, 0x59, 0x4f, 0x41, 0x01, 0x44, 0x4e, 0x51,
++    0x46, 0x51, 0x54, 0x4c, 0x4e, 0x59, 0x59, 0x4f, 0x4e, 0x56, 0x59, 0x59, 0x4f, 0x41, 0x01, 0x44,
++    0x11, 0x4b, 0x05, 0x40, 0x45, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4a, 0x46, 0x1a, 0x0d, 0x4b,
++    0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x45,
++    0x07, 0x04, 0x04, 0x09, 0x11, 0x09, 0x11, 0x12, 0x17, 0x0d, 0x4b, 0x17, 0x0d, 0x4b, 0x40, 0x40,
++    0x40, 0x20, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x09,
++    0x02, 0x3b, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x06, 0x12, 0x0b, 0x06, 0x06, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x07, 0x42, 0x55, 0x40, 0x18, 0x42, 0x47, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0d, 0x0f,
++    0x42, 0x4d, 0x40, 0x0d, 0x52, 0x4d, 0x48, 0x02, 0x02, 0x07, 0x07, 0x0a, 0x35, 0x12, 0x0a, 0x07,
++    0x58, 0x27, 0x05, 0x12, 0x40, 0x02, 0x10, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4d, 0x50, 0x45, 0x50,
++    0x52, 0x4a, 0x4d, 0x58, 0x58, 0x4d, 0x4d, 0x55, 0x58, 0x58, 0x4d, 0x40, 0x02, 0x42, 0x4d, 0x50,
++    0x45, 0x50, 0x52, 0x4a, 0x4d, 0x58, 0x58, 0x4d, 0x4d, 0x55, 0x58, 0x58, 0x4d, 0x40, 0x02, 0x42,
++    0x12, 0x4a, 0x07, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x02, 0x02, 0x48, 0x45, 0x1a, 0x0d, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x05, 0x05, 0x0a, 0x12, 0x0a, 0x12, 0x12, 0x17, 0x0d, 0x4a, 0x17, 0x0d, 0x4a, 0x40, 0x40,
++    0x40, 0x20, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x25, 0x27, 0x15, 0x07, 0x12, 0x15, 0x0a,
++    0x02, 0x3a, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x07, 0x12, 0x0d, 0x07, 0x07, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x08, 0x42, 0x54, 0x40, 0x17, 0x43, 0x48, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0c, 0x0f,
++    0x42, 0x4b, 0x40, 0x0d, 0x51, 0x4b, 0x46, 0x04, 0x04, 0x07, 0x07, 0x0a, 0x33, 0x12, 0x0b, 0x07,
++    0x57, 0x27, 0x06, 0x12, 0x40, 0x02, 0x0f, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4f, 0x44, 0x4f,
++    0x51, 0x49, 0x4c, 0x57, 0x57, 0x4b, 0x4c, 0x54, 0x57, 0x57, 0x4b, 0x00, 0x03, 0x41, 0x4c, 0x4f,
++    0x44, 0x4f, 0x51, 0x49, 0x4c, 0x57, 0x57, 0x4b, 0x4c, 0x54, 0x57, 0x57, 0x4b, 0x00, 0x03, 0x41,
++    0x13, 0x4a, 0x09, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x46, 0x44, 0x1a, 0x0c, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x05, 0x05, 0x0b, 0x13, 0x0b, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40,
++    0x40, 0x1f, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0b,
++    0x02, 0x39, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x08, 0x12, 0x0e, 0x08, 0x08, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x09, 0x42, 0x54, 0x40, 0x16, 0x43, 0x49, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0c, 0x0f,
++    0x42, 0x4a, 0x40, 0x0d, 0x50, 0x4a, 0x44, 0x07, 0x07, 0x07, 0x07, 0x0a, 0x32, 0x12, 0x0b, 0x07,
++    0x56, 0x27, 0x07, 0x12, 0x40, 0x02, 0x0e, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4e, 0x44, 0x4e,
++    0x50, 0x48, 0x4c, 0x56, 0x56, 0x4a, 0x4c, 0x54, 0x56, 0x56, 0x4a, 0x01, 0x03, 0x40, 0x4c, 0x4e,
++    0x44, 0x4e, 0x50, 0x48, 0x4c, 0x56, 0x56, 0x4a, 0x4c, 0x54, 0x56, 0x56, 0x4a, 0x01, 0x03, 0x40,
++    0x13, 0x4a, 0x0b, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x44, 0x44, 0x1a, 0x0c, 0x4a,
++    0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45,
++    0x07, 0x05, 0x05, 0x0b, 0x13, 0x0b, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40,
++    0x40, 0x1e, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0b,
++    0x02, 0x38, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x09, 0x12, 0x0f, 0x09, 0x09, 0x12, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0a, 0x41, 0x53, 0x40, 0x15, 0x44, 0x4a, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0b, 0x0f,
++    0x41, 0x48, 0x40, 0x0e, 0x4f, 0x48, 0x42, 0x09, 0x09, 0x07, 0x07, 0x09, 0x30, 0x11, 0x0c, 0x07,
++    0x55, 0x27, 0x08, 0x11, 0x40, 0x01, 0x0d, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4d, 0x43, 0x4d,
++    0x4f, 0x47, 0x4b, 0x55, 0x55, 0x48, 0x4b, 0x53, 0x55, 0x55, 0x48, 0x02, 0x04, 0x00, 0x4b, 0x4d,
++    0x43, 0x4d, 0x4f, 0x47, 0x4b, 0x55, 0x55, 0x48, 0x4b, 0x53, 0x55, 0x55, 0x48, 0x02, 0x04, 0x00,
++    0x14, 0x49, 0x0d, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x04, 0x04, 0x42, 0x43, 0x19, 0x0b, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x06, 0x06, 0x0c, 0x14, 0x0c, 0x14, 0x11, 0x17, 0x0b, 0x49, 0x17, 0x0b, 0x49, 0x40, 0x40,
++    0x40, 0x1d, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x13, 0x26, 0x27, 0x16, 0x07, 0x14, 0x16, 0x0c,
++    0x01, 0x36, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x0a, 0x11, 0x10, 0x0a, 0x0a, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0b, 0x41, 0x52, 0x40, 0x14, 0x45, 0x4b, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0a, 0x0f,
++    0x41, 0x47, 0x40, 0x0e, 0x4d, 0x47, 0x40, 0x0c, 0x0c, 0x07, 0x07, 0x09, 0x2f, 0x11, 0x0d, 0x07,
++    0x54, 0x27, 0x0a, 0x11, 0x40, 0x01, 0x0c, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4c, 0x42, 0x4c,
++    0x4d, 0x45, 0x4a, 0x54, 0x54, 0x47, 0x4a, 0x52, 0x54, 0x54, 0x47, 0x03, 0x05, 0x02, 0x4a, 0x4c,
++    0x42, 0x4c, 0x4d, 0x45, 0x4a, 0x54, 0x54, 0x47, 0x4a, 0x52, 0x54, 0x54, 0x47, 0x03, 0x05, 0x02,
++    0x15, 0x49, 0x0f, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x40, 0x42, 0x19, 0x0a, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x06, 0x06, 0x0d, 0x15, 0x0d, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40,
++    0x40, 0x1c, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0d,
++    0x01, 0x35, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x0b, 0x11, 0x12, 0x0b, 0x0b, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0c, 0x41, 0x52, 0x40, 0x13, 0x45, 0x4c, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0a, 0x0f,
++    0x41, 0x45, 0x40, 0x0e, 0x4c, 0x45, 0x01, 0x0e, 0x0e, 0x07, 0x07, 0x09, 0x2d, 0x11, 0x0d, 0x07,
++    0x53, 0x27, 0x0b, 0x11, 0x40, 0x01, 0x0b, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4b, 0x42, 0x4b,
++    0x4c, 0x44, 0x4a, 0x53, 0x53, 0x45, 0x4a, 0x52, 0x53, 0x53, 0x45, 0x04, 0x05, 0x03, 0x4a, 0x4b,
++    0x42, 0x4b, 0x4c, 0x44, 0x4a, 0x53, 0x53, 0x45, 0x4a, 0x52, 0x53, 0x53, 0x45, 0x04, 0x05, 0x03,
++    0x15, 0x49, 0x11, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x01, 0x42, 0x19, 0x0a, 0x49,
++    0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46,
++    0x07, 0x06, 0x06, 0x0d, 0x15, 0x0d, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40,
++    0x40, 0x1b, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0d,
++    0x01, 0x34, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x0c, 0x11, 0x13, 0x0c, 0x0c, 0x11, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0d, 0x40, 0x51, 0x40, 0x12, 0x46, 0x4d, 0x27, 0x40, 0x40, 0x40, 0x40, 0x09, 0x0f,
++    0x40, 0x44, 0x40, 0x0f, 0x4b, 0x44, 0x03, 0x11, 0x11, 0x07, 0x07, 0x08, 0x2c, 0x10, 0x0e, 0x07,
++    0x52, 0x27, 0x0c, 0x10, 0x40, 0x00, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x4a, 0x41, 0x4a,
++    0x4b, 0x43, 0x49, 0x52, 0x52, 0x44, 0x49, 0x51, 0x52, 0x52, 0x44, 0x05, 0x06, 0x04, 0x49, 0x4a,
++    0x41, 0x4a, 0x4b, 0x43, 0x49, 0x52, 0x52, 0x44, 0x49, 0x51, 0x52, 0x52, 0x44, 0x05, 0x06, 0x04,
++    0x16, 0x48, 0x13, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x03, 0x41, 0x18, 0x09, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x07, 0x07, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x09, 0x48, 0x17, 0x09, 0x48, 0x40, 0x40,
++    0x40, 0x1a, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x11, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0e,
++    0x00, 0x33, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x0d, 0x10, 0x14, 0x0d, 0x0d, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0e, 0x40, 0x51, 0x40, 0x11, 0x47, 0x4e, 0x27, 0x40, 0x40, 0x40, 0x40, 0x08, 0x0f,
++    0x40, 0x42, 0x40, 0x0f, 0x4a, 0x42, 0x04, 0x13, 0x13, 0x07, 0x07, 0x08, 0x2a, 0x10, 0x0e, 0x07,
++    0x51, 0x27, 0x0d, 0x10, 0x40, 0x00, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x41, 0x49,
++    0x4a, 0x42, 0x49, 0x51, 0x51, 0x42, 0x49, 0x51, 0x51, 0x51, 0x42, 0x06, 0x06, 0x05, 0x49, 0x49,
++    0x41, 0x49, 0x4a, 0x42, 0x49, 0x51, 0x51, 0x42, 0x49, 0x51, 0x51, 0x51, 0x42, 0x06, 0x06, 0x05,
++    0x16, 0x48, 0x14, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x04, 0x41, 0x18, 0x08, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x07, 0x07, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40,
++    0x40, 0x19, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0e,
++    0x00, 0x31, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x0e, 0x10, 0x15, 0x0e, 0x0e, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x0f, 0x40, 0x50, 0x40, 0x10, 0x47, 0x4f, 0x27, 0x40, 0x40, 0x40, 0x40, 0x08, 0x0f,
++    0x40, 0x40, 0x40, 0x0f, 0x48, 0x40, 0x06, 0x16, 0x16, 0x07, 0x07, 0x08, 0x28, 0x10, 0x0f, 0x07,
++    0x50, 0x27, 0x0f, 0x10, 0x40, 0x00, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48,
++    0x48, 0x40, 0x48, 0x50, 0x50, 0x40, 0x48, 0x50, 0x50, 0x50, 0x40, 0x07, 0x07, 0x07, 0x48, 0x48,
++    0x40, 0x48, 0x48, 0x40, 0x48, 0x50, 0x50, 0x40, 0x48, 0x50, 0x50, 0x50, 0x40, 0x07, 0x07, 0x07,
++    0x17, 0x48, 0x16, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x07, 0x07, 0x06, 0x40, 0x18, 0x08, 0x48,
++    0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47,
++    0x07, 0x07, 0x07, 0x0f, 0x17, 0x0f, 0x17, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40,
++    0x40, 0x18, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x17, 0x17, 0x0f,
++    0x00, 0x30, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x0f, 0x10, 0x17, 0x0f, 0x0f, 0x10, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x10, 0x00, 0x4f, 0x40, 0x0f, 0x48, 0x50, 0x28, 0x40, 0x00, 0x40, 0x40, 0x07, 0x0f,
++    0x00, 0x00, 0x40, 0x10, 0x47, 0x00, 0x08, 0x18, 0x18, 0x07, 0x07, 0x07, 0x27, 0x0f, 0x10, 0x07,
++    0x4f, 0x27, 0x10, 0x0f, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47,
++    0x47, 0x00, 0x47, 0x4f, 0x4f, 0x00, 0x47, 0x4f, 0x4f, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47,
++    0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x4f, 0x00, 0x47, 0x4f, 0x4f, 0x4f, 0x00, 0x08, 0x08, 0x08,
++    0x18, 0x47, 0x18, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x08, 0x00, 0x17, 0x07, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40,
++    0x40, 0x17, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10,
++    0x40, 0x2f, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x10, 0x0f, 0x18, 0x10, 0x10, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x11, 0x00, 0x4f, 0x40, 0x0e, 0x48, 0x51, 0x28, 0x40, 0x00, 0x40, 0x40, 0x07, 0x0f,
++    0x00, 0x02, 0x40, 0x10, 0x46, 0x02, 0x0a, 0x1b, 0x1b, 0x07, 0x07, 0x07, 0x25, 0x0f, 0x10, 0x07,
++    0x4e, 0x27, 0x11, 0x0f, 0x40, 0x40, 0x06, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x46, 0x00, 0x46,
++    0x46, 0x01, 0x47, 0x4e, 0x4e, 0x02, 0x47, 0x4f, 0x4e, 0x4e, 0x02, 0x09, 0x08, 0x09, 0x47, 0x46,
++    0x00, 0x46, 0x46, 0x01, 0x47, 0x4e, 0x4e, 0x02, 0x47, 0x4f, 0x4e, 0x4e, 0x02, 0x09, 0x08, 0x09,
++    0x18, 0x47, 0x1a, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x0a, 0x00, 0x17, 0x07, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40,
++    0x40, 0x16, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10,
++    0x40, 0x2e, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x11, 0x0f, 0x19, 0x11, 0x11, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x12, 0x00, 0x4e, 0x40, 0x0d, 0x49, 0x52, 0x28, 0x40, 0x00, 0x40, 0x40, 0x06, 0x0f,
++    0x00, 0x03, 0x40, 0x10, 0x45, 0x03, 0x0c, 0x1d, 0x1d, 0x07, 0x07, 0x07, 0x24, 0x0f, 0x11, 0x07,
++    0x4d, 0x27, 0x12, 0x0f, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x45, 0x01, 0x45,
++    0x45, 0x02, 0x46, 0x4d, 0x4d, 0x03, 0x46, 0x4e, 0x4d, 0x4d, 0x03, 0x0a, 0x09, 0x0a, 0x46, 0x45,
++    0x01, 0x45, 0x45, 0x02, 0x46, 0x4d, 0x4d, 0x03, 0x46, 0x4e, 0x4d, 0x4d, 0x03, 0x0a, 0x09, 0x0a,
++    0x19, 0x47, 0x1c, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x09, 0x09, 0x0c, 0x01, 0x17, 0x06, 0x47,
++    0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x48,
++    0x07, 0x08, 0x08, 0x11, 0x19, 0x11, 0x19, 0x0f, 0x17, 0x06, 0x47, 0x17, 0x06, 0x47, 0x40, 0x40,
++    0x40, 0x15, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x0e, 0x28, 0x27, 0x18, 0x07, 0x19, 0x18, 0x11,
++    0x40, 0x2c, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x12, 0x0f, 0x1a, 0x12, 0x12, 0x0f, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x13, 0x01, 0x4d, 0x40, 0x0c, 0x4a, 0x53, 0x29, 0x40, 0x01, 0x40, 0x40, 0x05, 0x0f,
++    0x01, 0x05, 0x40, 0x11, 0x43, 0x05, 0x0e, 0x20, 0x20, 0x07, 0x07, 0x06, 0x22, 0x0e, 0x12, 0x07,
++    0x4c, 0x27, 0x14, 0x0e, 0x40, 0x41, 0x04, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x44, 0x02, 0x44,
++    0x43, 0x04, 0x45, 0x4c, 0x4c, 0x05, 0x45, 0x4d, 0x4c, 0x4c, 0x05, 0x0b, 0x0a, 0x0c, 0x45, 0x44,
++    0x02, 0x44, 0x43, 0x04, 0x45, 0x4c, 0x4c, 0x05, 0x45, 0x4d, 0x4c, 0x4c, 0x05, 0x0b, 0x0a, 0x0c,
++    0x1a, 0x46, 0x1e, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x0e, 0x02, 0x16, 0x05, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x09, 0x09, 0x12, 0x1a, 0x12, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40,
++    0x40, 0x14, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x12,
++    0x41, 0x2b, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x13, 0x0e, 0x1c, 0x13, 0x13, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x14, 0x01, 0x4d, 0x40, 0x0b, 0x4a, 0x54, 0x29, 0x40, 0x01, 0x40, 0x40, 0x05, 0x0f,
++    0x01, 0x06, 0x40, 0x11, 0x42, 0x06, 0x10, 0x22, 0x22, 0x07, 0x07, 0x06, 0x21, 0x0e, 0x12, 0x07,
++    0x4b, 0x27, 0x15, 0x0e, 0x40, 0x41, 0x03, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x43, 0x02, 0x43,
++    0x42, 0x05, 0x45, 0x4b, 0x4b, 0x06, 0x45, 0x4d, 0x4b, 0x4b, 0x06, 0x0c, 0x0a, 0x0d, 0x45, 0x43,
++    0x02, 0x43, 0x42, 0x05, 0x45, 0x4b, 0x4b, 0x06, 0x45, 0x4d, 0x4b, 0x4b, 0x06, 0x0c, 0x0a, 0x0d,
++    0x1a, 0x46, 0x20, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x10, 0x02, 0x16, 0x05, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x09, 0x09, 0x12, 0x1a, 0x12, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40,
++    0x40, 0x13, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x12,
++    0x41, 0x2a, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x14, 0x0e, 0x1d, 0x14, 0x14, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x15, 0x01, 0x4c, 0x40, 0x0a, 0x4b, 0x55, 0x29, 0x40, 0x01, 0x40, 0x40, 0x04, 0x0f,
++    0x01, 0x08, 0x40, 0x11, 0x41, 0x08, 0x12, 0x25, 0x25, 0x07, 0x07, 0x06, 0x1f, 0x0e, 0x13, 0x07,
++    0x4a, 0x27, 0x16, 0x0e, 0x40, 0x41, 0x02, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x03, 0x42,
++    0x41, 0x06, 0x44, 0x4a, 0x4a, 0x08, 0x44, 0x4c, 0x4a, 0x4a, 0x08, 0x0d, 0x0b, 0x0e, 0x44, 0x42,
++    0x03, 0x42, 0x41, 0x06, 0x44, 0x4a, 0x4a, 0x08, 0x44, 0x4c, 0x4a, 0x4a, 0x08, 0x0d, 0x0b, 0x0e,
++    0x1b, 0x46, 0x22, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x12, 0x03, 0x16, 0x04, 0x46,
++    0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x49,
++    0x07, 0x09, 0x09, 0x13, 0x1b, 0x13, 0x1b, 0x0e, 0x17, 0x04, 0x46, 0x17, 0x04, 0x46, 0x40, 0x40,
++    0x40, 0x12, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x0c, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x13,
++    0x41, 0x29, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x15, 0x0e, 0x1e, 0x15, 0x15, 0x0e, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x15, 0x01, 0x4c, 0x40, 0x09, 0x4c, 0x56, 0x29, 0x40, 0x01, 0x40, 0x40, 0x03, 0x0f,
++    0x01, 0x09, 0x40, 0x11, 0x40, 0x09, 0x13, 0x27, 0x27, 0x07, 0x07, 0x05, 0x1d, 0x0d, 0x13, 0x07,
++    0x4a, 0x27, 0x17, 0x0d, 0x40, 0x42, 0x01, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x03, 0x42,
++    0x40, 0x07, 0x44, 0x4a, 0x4a, 0x09, 0x44, 0x4c, 0x4a, 0x4a, 0x09, 0x0d, 0x0b, 0x0f, 0x44, 0x42,
++    0x03, 0x42, 0x40, 0x07, 0x44, 0x4a, 0x4a, 0x09, 0x44, 0x4c, 0x4a, 0x4a, 0x09, 0x0d, 0x0b, 0x0f,
++    0x1b, 0x46, 0x23, 0x40, 0x4a, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x13, 0x03, 0x15, 0x03, 0x46,
++    0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x4a,
++    0x07, 0x09, 0x09, 0x13, 0x1b, 0x13, 0x1b, 0x0d, 0x17, 0x03, 0x46, 0x17, 0x03, 0x46, 0x40, 0x40,
++    0x40, 0x11, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x13,
++    0x42, 0x27, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x15, 0x0d, 0x1f, 0x15, 0x15, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x16, 0x02, 0x4b, 0x40, 0x09, 0x4c, 0x56, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x03, 0x0f,
++    0x02, 0x0b, 0x40, 0x12, 0x01, 0x0b, 0x15, 0x2a, 0x2a, 0x07, 0x07, 0x05, 0x1c, 0x0d, 0x14, 0x07,
++    0x49, 0x27, 0x19, 0x0d, 0x40, 0x42, 0x01, 0x40, 0x40, 0x40, 0x02, 0x02, 0x43, 0x41, 0x04, 0x41,
++    0x01, 0x09, 0x43, 0x49, 0x49, 0x0b, 0x43, 0x4b, 0x49, 0x49, 0x0b, 0x0e, 0x0c, 0x11, 0x43, 0x41,
++    0x04, 0x41, 0x01, 0x09, 0x43, 0x49, 0x49, 0x0b, 0x43, 0x4b, 0x49, 0x49, 0x0b, 0x0e, 0x0c, 0x11,
++    0x1c, 0x45, 0x25, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0c, 0x0c, 0x15, 0x04, 0x15, 0x03, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0a, 0x0a, 0x14, 0x1c, 0x14, 0x1c, 0x0d, 0x17, 0x03, 0x45, 0x17, 0x03, 0x45, 0x40, 0x40,
++    0x40, 0x11, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x2a, 0x27, 0x1a, 0x07, 0x1c, 0x1a, 0x14,
++    0x42, 0x26, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x16, 0x0d, 0x21, 0x16, 0x16, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x17, 0x02, 0x4a, 0x40, 0x08, 0x4d, 0x57, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x02, 0x0f,
++    0x02, 0x0d, 0x40, 0x12, 0x02, 0x0d, 0x17, 0x2c, 0x2c, 0x07, 0x07, 0x05, 0x1a, 0x0d, 0x15, 0x07,
++    0x48, 0x27, 0x1a, 0x0d, 0x40, 0x42, 0x00, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x40, 0x05, 0x40,
++    0x02, 0x0a, 0x42, 0x48, 0x48, 0x0d, 0x42, 0x4a, 0x48, 0x48, 0x0d, 0x0f, 0x0d, 0x12, 0x42, 0x40,
++    0x05, 0x40, 0x02, 0x0a, 0x42, 0x48, 0x48, 0x0d, 0x42, 0x4a, 0x48, 0x48, 0x0d, 0x0f, 0x0d, 0x12,
++    0x1d, 0x45, 0x27, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x17, 0x05, 0x15, 0x02, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0a, 0x0a, 0x15, 0x1d, 0x15, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40,
++    0x40, 0x10, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x15,
++    0x42, 0x25, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x17, 0x0d, 0x22, 0x17, 0x17, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x18, 0x02, 0x4a, 0x40, 0x07, 0x4d, 0x58, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x02, 0x0f,
++    0x02, 0x0e, 0x40, 0x12, 0x03, 0x0e, 0x19, 0x2f, 0x2f, 0x07, 0x07, 0x05, 0x19, 0x0d, 0x15, 0x07,
++    0x47, 0x27, 0x1b, 0x0d, 0x40, 0x42, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x00, 0x05, 0x00,
++    0x03, 0x0b, 0x42, 0x47, 0x47, 0x0e, 0x42, 0x4a, 0x47, 0x47, 0x0e, 0x10, 0x0d, 0x13, 0x42, 0x00,
++    0x05, 0x00, 0x03, 0x0b, 0x42, 0x47, 0x47, 0x0e, 0x42, 0x4a, 0x47, 0x47, 0x0e, 0x10, 0x0d, 0x13,
++    0x1d, 0x45, 0x29, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x19, 0x05, 0x15, 0x02, 0x45,
++    0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a,
++    0x07, 0x0a, 0x0a, 0x15, 0x1d, 0x15, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40,
++    0x40, 0x0f, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x15,
++    0x42, 0x24, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x18, 0x0d, 0x23, 0x18, 0x18, 0x0d, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x19, 0x03, 0x49, 0x40, 0x06, 0x4e, 0x59, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x01, 0x0f,
++    0x03, 0x10, 0x40, 0x13, 0x04, 0x10, 0x1b, 0x31, 0x31, 0x07, 0x07, 0x04, 0x17, 0x0c, 0x16, 0x07,
++    0x46, 0x27, 0x1c, 0x0c, 0x40, 0x43, 0x41, 0x40, 0x40, 0x40, 0x03, 0x03, 0x41, 0x01, 0x06, 0x01,
++    0x04, 0x0c, 0x41, 0x46, 0x46, 0x10, 0x41, 0x49, 0x46, 0x46, 0x10, 0x11, 0x0e, 0x14, 0x41, 0x01,
++    0x06, 0x01, 0x04, 0x0c, 0x41, 0x46, 0x46, 0x10, 0x41, 0x49, 0x46, 0x46, 0x10, 0x11, 0x0e, 0x14,
++    0x1e, 0x44, 0x2b, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0e, 0x0e, 0x1b, 0x06, 0x14, 0x01, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0b, 0x0b, 0x16, 0x1e, 0x16, 0x1e, 0x0c, 0x17, 0x01, 0x44, 0x17, 0x01, 0x44, 0x40, 0x40,
++    0x40, 0x0e, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x09, 0x2b, 0x27, 0x1b, 0x07, 0x1e, 0x1b, 0x16,
++    0x43, 0x22, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x19, 0x0c, 0x24, 0x19, 0x19, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1a, 0x03, 0x48, 0x40, 0x05, 0x4f, 0x5a, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x00, 0x0f,
++    0x03, 0x11, 0x40, 0x13, 0x06, 0x11, 0x1d, 0x34, 0x34, 0x07, 0x07, 0x04, 0x16, 0x0c, 0x17, 0x07,
++    0x45, 0x27, 0x1e, 0x0c, 0x40, 0x43, 0x42, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x02, 0x07, 0x02,
++    0x06, 0x0e, 0x40, 0x45, 0x45, 0x11, 0x40, 0x48, 0x45, 0x45, 0x11, 0x12, 0x0f, 0x16, 0x40, 0x02,
++    0x07, 0x02, 0x06, 0x0e, 0x40, 0x45, 0x45, 0x11, 0x40, 0x48, 0x45, 0x45, 0x11, 0x12, 0x0f, 0x16,
++    0x1f, 0x44, 0x2d, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1d, 0x07, 0x14, 0x00, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0b, 0x0b, 0x17, 0x1f, 0x17, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40,
++    0x40, 0x0d, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x17,
++    0x43, 0x21, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x1a, 0x0c, 0x26, 0x1a, 0x1a, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1b, 0x03, 0x48, 0x40, 0x04, 0x4f, 0x5b, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x00, 0x0f,
++    0x03, 0x13, 0x40, 0x13, 0x07, 0x13, 0x1f, 0x36, 0x36, 0x07, 0x07, 0x04, 0x14, 0x0c, 0x17, 0x07,
++    0x44, 0x27, 0x1f, 0x0c, 0x40, 0x43, 0x43, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x03, 0x07, 0x03,
++    0x07, 0x0f, 0x40, 0x44, 0x44, 0x13, 0x40, 0x48, 0x44, 0x44, 0x13, 0x13, 0x0f, 0x17, 0x40, 0x03,
++    0x07, 0x03, 0x07, 0x0f, 0x40, 0x44, 0x44, 0x13, 0x40, 0x48, 0x44, 0x44, 0x13, 0x13, 0x0f, 0x17,
++    0x1f, 0x44, 0x2f, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1f, 0x07, 0x14, 0x00, 0x44,
++    0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b,
++    0x07, 0x0b, 0x0b, 0x17, 0x1f, 0x17, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40,
++    0x40, 0x0c, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x17,
++    0x43, 0x20, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x1b, 0x0c, 0x27, 0x1b, 0x1b, 0x0c, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1c, 0x04, 0x47, 0x40, 0x03, 0x50, 0x5c, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f,
++    0x04, 0x14, 0x40, 0x14, 0x08, 0x14, 0x21, 0x39, 0x39, 0x07, 0x07, 0x03, 0x13, 0x0b, 0x18, 0x07,
++    0x43, 0x27, 0x20, 0x0b, 0x40, 0x44, 0x44, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x04, 0x08, 0x04,
++    0x08, 0x10, 0x00, 0x43, 0x43, 0x14, 0x00, 0x47, 0x43, 0x43, 0x14, 0x14, 0x10, 0x18, 0x00, 0x04,
++    0x08, 0x04, 0x08, 0x10, 0x00, 0x43, 0x43, 0x14, 0x00, 0x47, 0x43, 0x43, 0x14, 0x14, 0x10, 0x18,
++    0x20, 0x43, 0x31, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x21, 0x08, 0x13, 0x40, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x0c, 0x0c, 0x18, 0x20, 0x18, 0x20, 0x0b, 0x17, 0x40, 0x43, 0x17, 0x40, 0x43, 0x40, 0x40,
++    0x40, 0x0b, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x07, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x18,
++    0x44, 0x1f, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x1c, 0x0b, 0x28, 0x1c, 0x1c, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1d, 0x04, 0x47, 0x40, 0x02, 0x51, 0x5d, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x41, 0x0f,
++    0x04, 0x16, 0x40, 0x14, 0x09, 0x16, 0x22, 0x3b, 0x3b, 0x07, 0x07, 0x03, 0x11, 0x0b, 0x18, 0x07,
++    0x42, 0x27, 0x21, 0x0b, 0x40, 0x44, 0x45, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x05, 0x08, 0x05,
++    0x09, 0x11, 0x00, 0x42, 0x42, 0x16, 0x00, 0x47, 0x42, 0x42, 0x16, 0x15, 0x10, 0x19, 0x00, 0x05,
++    0x08, 0x05, 0x09, 0x11, 0x00, 0x42, 0x42, 0x16, 0x00, 0x47, 0x42, 0x42, 0x16, 0x15, 0x10, 0x19,
++    0x20, 0x43, 0x32, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x22, 0x08, 0x13, 0x41, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x0c, 0x0c, 0x18, 0x20, 0x18, 0x20, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40,
++    0x40, 0x0a, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x18,
++    0x44, 0x1d, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x1d, 0x0b, 0x29, 0x1d, 0x1d, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1e, 0x04, 0x46, 0x40, 0x01, 0x51, 0x5e, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x41, 0x0f,
++    0x04, 0x18, 0x40, 0x14, 0x0b, 0x18, 0x24, 0x3e, 0x3e, 0x07, 0x07, 0x03, 0x0f, 0x0b, 0x19, 0x07,
++    0x41, 0x27, 0x23, 0x0b, 0x40, 0x44, 0x46, 0x40, 0x40, 0x40, 0x04, 0x04, 0x01, 0x06, 0x09, 0x06,
++    0x0b, 0x13, 0x01, 0x41, 0x41, 0x18, 0x01, 0x46, 0x41, 0x41, 0x18, 0x16, 0x11, 0x1b, 0x01, 0x06,
++    0x09, 0x06, 0x0b, 0x13, 0x01, 0x41, 0x41, 0x18, 0x01, 0x46, 0x41, 0x41, 0x18, 0x16, 0x11, 0x1b,
++    0x21, 0x43, 0x34, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x11, 0x11, 0x24, 0x09, 0x13, 0x41, 0x43,
++    0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c,
++    0x07, 0x0c, 0x0c, 0x19, 0x21, 0x19, 0x21, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40,
++    0x40, 0x09, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x21, 0x1c, 0x19,
++    0x44, 0x1c, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x1e, 0x0b, 0x2b, 0x1e, 0x1e, 0x0b, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x1f, 0x05, 0x45, 0x40, 0x00, 0x52, 0x5f, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x42, 0x0f,
++    0x05, 0x19, 0x40, 0x15, 0x0c, 0x19, 0x26, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0e, 0x0a, 0x1a, 0x07,
++    0x40, 0x27, 0x24, 0x0a, 0x40, 0x45, 0x47, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x07, 0x0a, 0x07,
++    0x0c, 0x14, 0x02, 0x40, 0x40, 0x19, 0x02, 0x45, 0x40, 0x40, 0x19, 0x17, 0x12, 0x1c, 0x02, 0x07,
++    0x0a, 0x07, 0x0c, 0x14, 0x02, 0x40, 0x40, 0x19, 0x02, 0x45, 0x40, 0x40, 0x19, 0x17, 0x12, 0x1c,
++    0x22, 0x42, 0x36, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x26, 0x0a, 0x12, 0x42, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x0d, 0x0d, 0x1a, 0x22, 0x1a, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40,
++    0x40, 0x08, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a,
++    0x45, 0x1b, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x1f, 0x0a, 0x2c, 0x1f, 0x1f, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x20, 0x05, 0x45, 0x40, 0x40, 0x52, 0x60, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x42, 0x0f,
++    0x05, 0x1b, 0x40, 0x15, 0x0d, 0x1b, 0x28, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0c, 0x0a, 0x1a, 0x07,
++    0x00, 0x27, 0x25, 0x0a, 0x40, 0x45, 0x48, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x08, 0x0a, 0x08,
++    0x0d, 0x15, 0x02, 0x00, 0x00, 0x1b, 0x02, 0x45, 0x00, 0x00, 0x1b, 0x18, 0x12, 0x1d, 0x02, 0x08,
++    0x0a, 0x08, 0x0d, 0x15, 0x02, 0x00, 0x00, 0x1b, 0x02, 0x45, 0x00, 0x00, 0x1b, 0x18, 0x12, 0x1d,
++    0x22, 0x42, 0x38, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x28, 0x0a, 0x12, 0x42, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x0d, 0x0d, 0x1a, 0x22, 0x1a, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40,
++    0x40, 0x07, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a,
++    0x45, 0x1a, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x20, 0x0a, 0x2d, 0x20, 0x20, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x21, 0x05, 0x44, 0x40, 0x41, 0x53, 0x61, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x43, 0x0f,
++    0x05, 0x1c, 0x40, 0x15, 0x0e, 0x1c, 0x2a, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0a, 0x1b, 0x07,
++    0x01, 0x27, 0x26, 0x0a, 0x40, 0x45, 0x49, 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x0b, 0x09,
++    0x0e, 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e, 0x03, 0x09,
++    0x0b, 0x09, 0x0e, 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e,
++    0x23, 0x42, 0x3a, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x0b, 0x12, 0x43, 0x42,
++    0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d,
++    0x07, 0x0d, 0x0d, 0x1b, 0x23, 0x1b, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, 0x40,
++    0x40, 0x06, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, 0x1d, 0x1b,
++    0x45, 0x18, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x21, 0x0a, 0x2e, 0x21, 0x21, 0x0a, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f,
++    0x06, 0x1e, 0x40, 0x16, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x09, 0x09, 0x1c, 0x07,
++    0x02, 0x27, 0x28, 0x09, 0x40, 0x46, 0x4a, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0a, 0x0c, 0x0a,
++    0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20, 0x04, 0x0a,
++    0x0c, 0x0a, 0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20,
++    0x24, 0x41, 0x3c, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2c, 0x0c, 0x11, 0x44, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
++    0x40, 0x05, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c,
++    0x46, 0x17, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x22, 0x09, 0x30, 0x22, 0x22, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f,
++    0x06, 0x1f, 0x40, 0x16, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x08, 0x09, 0x1c, 0x07,
++    0x03, 0x27, 0x29, 0x09, 0x40, 0x46, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x0c, 0x0b,
++    0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21, 0x04, 0x0b,
++    0x0c, 0x0b, 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21,
++    0x24, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, 0x0c, 0x11, 0x44, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
++    0x40, 0x04, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c,
++    0x46, 0x16, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x23, 0x09, 0x31, 0x23, 0x23, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x44, 0x55, 0x64, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x45, 0x0f,
++    0x06, 0x21, 0x40, 0x16, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x06, 0x09, 0x1d, 0x07,
++    0x04, 0x27, 0x2a, 0x09, 0x40, 0x46, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c,
++    0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22, 0x05, 0x0c,
++    0x0d, 0x0c, 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22,
++    0x25, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x0d, 0x11, 0x45, 0x41,
++    0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x4e,
++    0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, 0x40, 0x40,
++    0x40, 0x03, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d,
++    0x46, 0x15, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x24, 0x09, 0x32, 0x24, 0x24, 0x09, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x46, 0x0f,
++    0x06, 0x22, 0x40, 0x16, 0x13, 0x22, 0x31, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x04, 0x08, 0x1d, 0x07,
++    0x04, 0x27, 0x2b, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c,
++    0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x05, 0x0c,
++    0x0d, 0x0c, 0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23,
++    0x25, 0x41, 0x3e, 0x40, 0x4f, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x0d, 0x10, 0x46, 0x41,
++    0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f,
++    0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40,
++    0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d,
++    0x47, 0x13, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x24, 0x08, 0x33, 0x24, 0x24, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x46, 0x0f,
++    0x07, 0x24, 0x40, 0x17, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x03, 0x08, 0x1e, 0x07,
++    0x05, 0x27, 0x2d, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x0e, 0x0d,
++    0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, 0x06, 0x0d,
++    0x0e, 0x0d, 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25,
++    0x26, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x0e, 0x10, 0x46, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x0f, 0x0f, 0x1e, 0x26, 0x1e, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40,
++    0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x1e,
++    0x47, 0x12, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x25, 0x08, 0x35, 0x25, 0x25, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
++    0x07, 0x26, 0x40, 0x17, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x01, 0x08, 0x1f, 0x07,
++    0x06, 0x27, 0x2e, 0x08, 0x40, 0x47, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x0f, 0x0e,
++    0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26, 0x07, 0x0e,
++    0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26,
++    0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x0f, 0x10, 0x47, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
++    0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f,
++    0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++    0x07, 0x3e, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
++    0x07, 0x27, 0x40, 0x17, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07,
++    0x07, 0x27, 0x2f, 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f,
++    0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f,
++    0x0f, 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27,
++    0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, 0x40,
++    0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
++    0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
++    0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f,
++    0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, 0x27, 0x27, 0x08, 0x40, 0x40,
++    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++};
++
++static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
++{
++	u8 bit = field.offset % 32, word = field.offset / 32;
++	u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
++	u64 val = ((u64)value << bit) & mask;
++
++	buf[word] &= ~mask;
++	buf[word] |= val;
++	if (bit + field.len > 32) {
++		buf[word + 1] &= ~(mask >> 32);
++		buf[word + 1] |= val >> 32;
++	}
++}
++
++static void assemble_hw_pps(struct rkvdec_ctx *ctx,
++			    struct rkvdec_hevc_run *run)
++{
++	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
++	const struct v4l2_ctrl_hevc_sps *sps = run->sps;
++	const struct v4l2_ctrl_hevc_pps *pps = run->pps;
++	struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
++	struct rkvdec_sps_pps_packet *hw_ps;
++	u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
++	u32 log2_min_cu_qp_delta_size;
++	dma_addr_t scaling_list_address;
++	u32 scaling_distance;
++	int i;
++
++	/*
++	 * HW read the SPS/PPS information from PPS packet index by PPS id.
++	 * offset from the base can be calculated by PPS_id * 80 (size per PPS
++	 * packet unit). so the driver copy SPS/PPS information to the exact PPS
++	 * packet unit for HW accessing.
++	 */
++	hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
++	memset(hw_ps, 0, sizeof(*hw_ps));
++
++	min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
++	ctb_log2_size_y = min_cb_log2_size_y +
++	    sps->log2_diff_max_min_luma_coding_block_size;
++	ctb_size_y = 1 << ctb_log2_size_y;
++
++#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
++	/* write sps */
++	WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
++	WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
++	WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
++	WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
++	WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
++	WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
++	WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
++	WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
++		  LOG2_MAX_PIC_ORDER_CNT_LSB);
++	WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
++		  LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
++	WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
++		  LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
++	WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
++		  LOG2_MIN_TRANSFORM_BLOCK_SIZE);
++	WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
++		  LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
++	WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
++		  MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
++	WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
++		  MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
++		  SCALING_LIST_ENABLED_FLAG);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
++		  AMP_ENABLED_FLAG);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
++		  SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
++	if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
++		WRITE_PPS(1, PCM_ENABLED_FLAG);
++		WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1,
++			  PCM_SAMPLE_BIT_DEPTH_LUMA);
++		WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1,
++			  PCM_SAMPLE_BIT_DEPTH_CHROMA);
++		WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
++			  PCM_LOOP_FILTER_DISABLED_FLAG);
++		WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
++			  LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
++		WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3,
++			  LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
++	}
++	WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
++		  LONG_TERM_REF_PICS_PRESENT_FLAG);
++	WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
++		  SPS_TEMPORAL_MVP_ENABLED_FLAG);
++	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
++		  STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
++
++	/* write pps */
++	WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
++	WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
++		  DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
++		  OUTPUT_FLAG_PRESENT_FLAG);
++	WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
++		  SIGN_DATA_HIDING_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
++		  CABAC_INIT_PRESENT_FLAG);
++	WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
++		  NUM_REF_IDX_L0_DEFAULT_ACTIVE);
++	WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
++		  NUM_REF_IDX_L1_DEFAULT_ACTIVE);
++	WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
++		  CONSTRAINED_INTRA_PRED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
++		  TRANSFORM_SKIP_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
++		  CU_QP_DELTA_ENABLED_FLAG);
++
++	log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
++	WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
++
++	WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
++	WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
++		  PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
++		  WEIGHTED_PRED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
++		  WEIGHTED_BIPRED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
++		  TRANSQUANT_BYPASS_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
++		  TILES_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
++		  ENTROPY_CODING_SYNC_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
++		  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
++		  LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
++		  DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
++		  PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
++	WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
++	WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
++		  LISTS_MODIFICATION_PRESENT_FLAG);
++	WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
++	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
++		  SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
++	WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
++	WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
++
++	if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
++		for (i = 0; i <= pps->num_tile_columns_minus1; i++)
++			WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i));
++		for (i = 0; i <= pps->num_tile_rows_minus1; i++)
++			WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));
++	} else {
++		WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
++			  COLUMN_WIDTH(0));
++		WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
++			  ROW_HEIGHT(0));
++	}
++
++	scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
++	scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
++	WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
++}
++
++static void assemble_hw_rps(struct rkvdec_ctx *ctx,
++			    struct rkvdec_hevc_run *run)
++{
++	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
++	const struct v4l2_ctrl_hevc_slice_params *sl_params;
++	const struct v4l2_hevc_dpb_entry *dpb;
++	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
++	struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
++	struct rkvdec_rps_packet *hw_ps;
++	int i, j;
++	unsigned int lowdelay;
++
++#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
++
++#define REF_PIC_LONG_TERM_L0(i)			PS_FIELD(i * 5, 1)
++#define REF_PIC_IDX_L0(i)			PS_FIELD(1 + (i * 5), 4)
++#define REF_PIC_LONG_TERM_L1(i)			PS_FIELD((i < 5 ? 75 : 132) + (i * 5), 1)
++#define REF_PIC_IDX_L1(i)			PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4)
++
++#define LOWDELAY				PS_FIELD(182, 1)
++#define LONG_TERM_RPS_BIT_OFFSET		PS_FIELD(183, 10)
++#define SHORT_TERM_RPS_BIT_OFFSET		PS_FIELD(193, 9)
++#define NUM_RPS_POC				PS_FIELD(202, 4)
++
++	for (j = 0; j < run->num_slices; j++) {
++		sl_params = &run->slices_params[j];
++		dpb = decode_params->dpb;
++		lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1;
++
++		hw_ps = &priv_tbl->rps[j];
++		memset(hw_ps, 0, sizeof(*hw_ps));
++
++		for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) {
++			WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
++				  REF_PIC_LONG_TERM_L0(i));
++			WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
++
++			if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt)
++				lowdelay = 0;
++
++		}
++
++		for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) {
++			WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
++				  REF_PIC_LONG_TERM_L1(i));
++			WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
++
++			if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt)
++				lowdelay = 0;
++		}
++
++		WRITE_RPS(lowdelay, LOWDELAY);
++
++		WRITE_RPS(sl_params->long_term_ref_pic_set_size +
++			  sl_params->short_term_ref_pic_set_size,
++			  LONG_TERM_RPS_BIT_OFFSET);
++		WRITE_RPS(sl_params->short_term_ref_pic_set_size,
++			  SHORT_TERM_RPS_BIT_OFFSET);
++
++		WRITE_RPS(decode_params->num_poc_st_curr_before +
++			  decode_params->num_poc_st_curr_after +
++			  decode_params->num_poc_lt_curr,
++			  NUM_RPS_POC);
++	}
++}
++
++static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx,
++				     struct rkvdec_hevc_run *run)
++{
++	const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix;
++	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
++	struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
++	u8 *dst;
++	scalingList_t sl;
++	int i, j;
++
++	if (!memcmp((void*)&hevc_ctx->scaling_matrix_cache, scaling,
++		    sizeof(struct v4l2_ctrl_hevc_scaling_matrix)))
++		return;
++
++	memset(&sl, 0, sizeof(scalingList_t));
++
++	for (i = 0; i < 6; i++) {
++		for (j = 0; j < 16; j++)
++			sl.sl[0][i][j] = scaling->scaling_list_4x4[i][j];
++		for (j = 0; j < 64; j++) {
++			sl.sl[1][i][j] = scaling->scaling_list_8x8[i][j];
++			sl.sl[2][i][j] = scaling->scaling_list_16x16[i][j];
++		if (i < 2)
++			sl.sl[3][i][j] = scaling->scaling_list_32x32[i][j];
++		}
++		sl.sl_dc[0][i] = scaling->scaling_list_dc_coef_16x16[i];
++		if (i < 2)
++			sl.sl_dc[1][i] = scaling->scaling_list_dc_coef_32x32[i];
++	}
++
++	dst = tbl->scaling_list;
++	hal_record_scaling_list((scalingFactor_t *)dst, &sl);
++
++	memcpy((void*)&hevc_ctx->scaling_matrix_cache, scaling,
++	       sizeof(struct v4l2_ctrl_hevc_scaling_matrix));
++}
++
++static struct vb2_buffer *
++get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run,
++	    unsigned int dpb_idx)
++{
++	struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
++	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
++	const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
++	struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
++	struct vb2_buffer *vb2_buf = NULL;
++
++	if (dpb_idx < decode_params->num_active_dpb_entries)
++		vb2_buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp);
++
++	/*
++	 * If a DPB entry is unused or invalid, address of current destination
++	 * buffer is returned.
++	 */
++	if (!vb2_buf)
++		return &run->base.bufs.dst->vb2_buf;
++
++	return vb2_buf;
++}
++
++static void config_registers(struct rkvdec_ctx *ctx,
++			     struct rkvdec_hevc_run *run)
++{
++	struct rkvdec_dev *rkvdec = ctx->dev;
++	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
++	const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
++	const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
++	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
++	dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
++	const struct v4l2_pix_format_mplane *dst_fmt;
++	struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
++	struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
++	const struct v4l2_format *f;
++	dma_addr_t rlc_addr;
++	dma_addr_t refer_addr;
++	u32 rlc_len;
++	u32 hor_virstride;
++	u32 ver_virstride;
++	u32 y_virstride;
++	u32 uv_virstride;
++	u32 yuv_virstride;
++	u32 offset;
++	dma_addr_t dst_addr;
++	u32 reg, i;
++
++	reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
++
++	f = &ctx->decoded_fmt;
++	dst_fmt = &f->fmt.pix_mp;
++	hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
++	ver_virstride = dst_fmt->height;
++	y_virstride = hor_virstride * ver_virstride;
++	uv_virstride = y_virstride / 2;
++	yuv_virstride = y_virstride + uv_virstride;
++
++	reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
++	      RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
++	      RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
++
++	/* config rlc base address */
++	rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
++	writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
++
++	rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
++	reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
++
++	/* config cabac table */
++	offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
++	writel_relaxed(priv_start_addr + offset,
++		       rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
++
++	/* config output base address */
++	dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
++	writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
++
++	reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
++
++	reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
++
++	/* config ref pic address */
++	for (i = 0; i < 15; i++) {
++		struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
++
++		if (i < 4 && decode_params->num_active_dpb_entries) {
++			reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);
++			reg = (reg >> (i * 4)) & 0xf;
++		} else
++			reg = 0;
++
++		refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
++		writel_relaxed(refer_addr | reg,
++			       rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
++
++		reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0);
++		writel_relaxed(reg,
++			       rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
++	}
++
++	reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
++
++	/* config hw pps address */
++	offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
++	writel_relaxed(priv_start_addr + offset,
++		       rkvdec->regs + RKVDEC_REG_PPS_BASE);
++
++	/* config hw rps address */
++	offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
++	writel_relaxed(priv_start_addr + offset,
++		       rkvdec->regs + RKVDEC_REG_RPS_BASE);
++
++	reg = RKVDEC_AXI_DDR_RDATA(0);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
++
++	reg = RKVDEC_AXI_DDR_WDATA(0);
++	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
++}
++
++#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES		2
++
++static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx,
++				  struct v4l2_format *f)
++{
++	struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
++
++	fmt->num_planes = 1;
++	if (!fmt->plane_fmt[0].sizeimage)
++		fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
++					      RKVDEC_HEVC_MAX_DEPTH_IN_BYTES;
++	return 0;
++}
++
++static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx,
++				    const struct v4l2_ctrl_hevc_sps *sps)
++{
++	if (sps->chroma_format_idc > 1)
++		/* Only 4:0:0 and 4:2:0 are supported */
++		return -EINVAL;
++	if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
++		/* Luma and chroma bit depth mismatch */
++		return -EINVAL;
++	if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
++		/* Only 8-bit and 10-bit is supported */
++		return -EINVAL;
++
++	if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width ||
++	    sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height)
++		return -EINVAL;
++
++	return 0;
++}
++
++static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
++{
++	const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
++
++	if (sps->bit_depth_luma_minus8 == 2)
++		return V4L2_PIX_FMT_NV15;
++	else
++		return V4L2_PIX_FMT_NV12;
++}
++
++static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
++{
++	struct rkvdec_dev *rkvdec = ctx->dev;
++	struct rkvdec_hevc_priv_tbl *priv_tbl;
++	struct rkvdec_hevc_ctx *hevc_ctx;
++	struct v4l2_ctrl *ctrl;
++	int ret;
++
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_SPS);
++	if (!ctrl)
++		return -EINVAL;
++
++	ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
++	if (ret)
++		return ret;
++
++	hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL);
++	if (!hevc_ctx)
++		return -ENOMEM;
++
++
++	priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
++				      &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
++	if (!priv_tbl) {
++		ret = -ENOMEM;
++		goto err_free_ctx;
++	}
++
++	hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
++	hevc_ctx->priv_tbl.cpu = priv_tbl;
++	memset(priv_tbl, 0, sizeof(*priv_tbl));
++	memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table,
++	       sizeof(rkvdec_hevc_cabac_table));
++
++	ctx->priv = hevc_ctx;
++	return 0;
++
++err_free_ctx:
++	kfree(hevc_ctx);
++	return ret;
++}
++
++static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
++{
++	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
++	struct rkvdec_dev *rkvdec = ctx->dev;
++
++	dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
++			  hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
++	kfree(hevc_ctx);
++}
++
++static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx,
++				     struct rkvdec_hevc_run *run)
++{
++	struct v4l2_ctrl *ctrl;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
++	run->decode_params = ctrl ? ctrl->p_cur.p : NULL;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_SLICE_PARAMS);
++	run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
++	run->num_slices = ctrl->new_elems;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_SPS);
++	run->sps = ctrl ? ctrl->p_cur.p : NULL;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_PPS);
++	run->pps = ctrl ? ctrl->p_cur.p : NULL;
++	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
++			      V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
++	run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
++
++	rkvdec_run_preamble(ctx, &run->base);
++}
++
++static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
++{
++	struct rkvdec_dev *rkvdec = ctx->dev;
++	struct rkvdec_hevc_run run;
++
++	rkvdec_hevc_run_preamble(ctx, &run);
++
++	assemble_hw_scaling_list(ctx, &run);
++	assemble_hw_pps(ctx, &run);
++	assemble_hw_rps(ctx, &run);
++	config_registers(ctx, &run);
++
++	rkvdec_run_postamble(ctx, &run.base);
++
++	// sw_cabac_error_e - cabac error enable
++	writel_relaxed(0xfdfffffd, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
++	// slice end error enable = BIT(28)
++	// frame end error enable = BIT(29)
++	writel_relaxed(0x30000000, rkvdec->regs + RKVDEC_REG_H264_ERR_E);
++
++	schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
++
++	writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
++	writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
++
++	/* Start decoding! */
++	writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
++	       RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
++	       rkvdec->regs + RKVDEC_REG_INTERRUPT);
++
++	return 0;
++}
++
++static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
++{
++	if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS)
++		return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
++
++	return 0;
++}
++
++const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
++	.adjust_fmt = rkvdec_hevc_adjust_fmt,
++	.start = rkvdec_hevc_start,
++	.stop = rkvdec_hevc_stop,
++	.run = rkvdec_hevc_run,
++	.try_ctrl = rkvdec_hevc_try_ctrl,
++	.valid_fmt = rkvdec_hevc_valid_fmt,
++};
+diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
+index 265f5234f4eb..4319ee3ccbbc 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
+@@ -48,6 +48,7 @@
+ #define RKVDEC_RLC_MODE					BIT(11)
+ #define RKVDEC_STRM_START_BIT(x)			(((x) & 0x7f) << 12)
+ #define RKVDEC_MODE(x)					(((x) & 0x03) << 20)
++#define RKVDEC_MODE_HEVC				0
+ #define RKVDEC_MODE_H264				1
+ #define RKVDEC_MODE_VP9					2
+ #define RKVDEC_RPS_MODE					BIT(24)
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index f55abb7c377f..00a9bf583596 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
+ {
+ 	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
+ 
+-	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) {
++	if (!ctx->valid_fmt) {
+ 		ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl);
+ 		if (ctx->valid_fmt) {
+ 			struct v4l2_pix_format_mplane *pix_mp;
+@@ -134,6 +134,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
+ 	},
+ };
+ 
++static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS,
++		.cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY,
++		.cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS,
++		.cfg.dims = { 600 },
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_SPS,
++		.cfg.ops = &rkvdec_ctrl_ops,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_PPS,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
++		.cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
++		.cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
++		.cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
++	},
++	{
++		.cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE,
++		.cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
++		.cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
++		.cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
++	},
++	{
++		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
++		.cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
++		.cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
++		.cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
++	},
++	{
++		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
++		.cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
++		.cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
++	},
++};
++
++static const struct rkvdec_ctrls rkvdec_hevc_ctrls = {
++	.ctrls = rkvdec_hevc_ctrl_descs,
++	.num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs),
++};
++
++static const u32 rkvdec_hevc_decoded_fmts[] = {
++	V4L2_PIX_FMT_NV12,
++	V4L2_PIX_FMT_NV15,
++};
++
++
+ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
+ 	.ctrls = rkvdec_h264_ctrl_descs,
+ 	.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
+@@ -187,6 +243,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 		.decoded_fmts = rkvdec_h264_decoded_fmts,
+ 		.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+ 	},
++	{
++		.fourcc = V4L2_PIX_FMT_HEVC_SLICE,
++		.frmsize = {
++			.min_width = 64,
++			.max_width = 4096,
++			.step_width = 64,
++			.min_height = 64,
++			.max_height = 2304,
++			.step_height = 16,
++		},
++		.ctrls = &rkvdec_hevc_ctrls,
++		.ops = &rkvdec_hevc_fmt_ops,
++		.num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
++		.decoded_fmts = rkvdec_hevc_decoded_fmts,
++	},
+ 	{
+ 		.fourcc = V4L2_PIX_FMT_VP9_FRAME,
+ 		.frmsize = {
+diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
+index f02f79c405f0..d6222a2588be 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.h
++++ b/drivers/staging/media/rkvdec/rkvdec.h
+@@ -133,6 +133,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
+ void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
+ 
+ extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
++extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops;
+ extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
+ 
+ #endif /* RKVDEC_H_ */
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 30 Jan 2021 18:16:39 +0100
+Subject: [PATCH] media: rkvdec: add variants support
+
+rkvdec IP has different versions which among others differ in
+the supported decoding formats.
+This adds an variant implementation in order support other
+than the currently supported RK3399 version.
+
+Note: Since matching of supported codecs is index-based the
+available codec options have been reordered here: from
+supported by all versions to not commonly supported. This seems
+the better soultion than duplicatiing code for every newly added IP.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/staging/media/rkvdec/rkvdec.c | 105 ++++++++++++++++++--------
+ drivers/staging/media/rkvdec/rkvdec.h |  10 +++
+ 2 files changed, 85 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index 00a9bf583596..955c53afe20f 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -14,6 +14,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm.h>
+ #include <linux/pm_runtime.h>
+@@ -227,6 +228,22 @@ static const u32 rkvdec_vp9_decoded_fmts[] = {
+ };
+ 
+ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
++	{
++		.fourcc = V4L2_PIX_FMT_HEVC_SLICE,
++		.frmsize = {
++			.min_width = 64,
++			.max_width = 4096,
++			.step_width = 64,
++			.min_height = 64,
++			.max_height = 2304,
++			.step_height = 16,
++		},
++		.ctrls = &rkvdec_hevc_ctrls,
++		.ops = &rkvdec_hevc_fmt_ops,
++		.num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
++		.decoded_fmts = rkvdec_hevc_decoded_fmts,
++		.capability = RKVDEC_CAPABILITY_HEVC,
++	},
+ 	{
+ 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
+ 		.frmsize = {
+@@ -242,21 +259,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
+ 		.decoded_fmts = rkvdec_h264_decoded_fmts,
+ 		.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+-	},
+-	{
+-		.fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+-		.frmsize = {
+-			.min_width = 64,
+-			.max_width = 4096,
+-			.step_width = 64,
+-			.min_height = 64,
+-			.max_height = 2304,
+-			.step_height = 16,
+-		},
+-		.ctrls = &rkvdec_hevc_ctrls,
+-		.ops = &rkvdec_hevc_fmt_ops,
+-		.num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
+-		.decoded_fmts = rkvdec_hevc_decoded_fmts,
++		.capability = RKVDEC_CAPABILITY_H264,
+ 	},
+ 	{
+ 		.fourcc = V4L2_PIX_FMT_VP9_FRAME,
+@@ -272,16 +275,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ 		.ops = &rkvdec_vp9_fmt_ops,
+ 		.num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
+ 		.decoded_fmts = rkvdec_vp9_decoded_fmts,
+-	}
++		.capability = RKVDEC_CAPABILITY_VP9,
++	},
+ };
+ 
+ static const struct rkvdec_coded_fmt_desc *
+-rkvdec_find_coded_fmt_desc(u32 fourcc)
++rkvdec_default_coded_fmt_desc(unsigned int capabilities)
++{
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
++		if (rkvdec_coded_fmts[i].capability & capabilities)
++			return &rkvdec_coded_fmts[i];
++	}
++
++	return NULL;
++}
++
++static const struct rkvdec_coded_fmt_desc *
++rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities)
+ {
+ 	unsigned int i;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
+-		if (rkvdec_coded_fmts[i].fourcc == fourcc)
++		if (rkvdec_coded_fmts[i].fourcc == fourcc &&
++		    (rkvdec_coded_fmts[i].capability & capabilities))
+ 			return &rkvdec_coded_fmts[i];
+ 	}
+ 
+@@ -304,7 +322,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
+ {
+ 	struct v4l2_format *f = &ctx->coded_fmt;
+ 
+-	ctx->coded_fmt_desc = &rkvdec_coded_fmts[0];
++	ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
+ 	rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc);
+ 
+ 	f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+@@ -331,11 +349,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv,
+ 				  struct v4l2_frmsizeenum *fsize)
+ {
+ 	const struct rkvdec_coded_fmt_desc *fmt;
++	struct rkvdec_dev *rkvdec = video_drvdata(file);
+ 
+ 	if (fsize->index != 0)
+ 		return -EINVAL;
+ 
+-	fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format);
++	fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format,
++					 rkvdec->capabilities);
+ 	if (!fmt)
+ 		return -EINVAL;
+ 
+@@ -406,10 +426,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv,
+ 	struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
+ 	const struct rkvdec_coded_fmt_desc *desc;
+ 
+-	desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat);
++	desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat,
++					  ctx->dev->capabilities);
+ 	if (!desc) {
+-		pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc;
+-		desc = &rkvdec_coded_fmts[0];
++		desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
++		pix_mp->pixelformat = desc->fourcc;
+ 	}
+ 
+ 	v4l2_apply_frmsize_constraints(&pix_mp->width,
+@@ -487,7 +508,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv,
+ 	if (ret)
+ 		return ret;
+ 
+-	desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat);
++	desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat,
++					  ctx->dev->capabilities);
+ 	if (!desc)
+ 		return -EINVAL;
+ 	ctx->coded_fmt_desc = desc;
+@@ -538,7 +560,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv,
+ static int rkvdec_enum_output_fmt(struct file *file, void *priv,
+ 				  struct v4l2_fmtdesc *f)
+ {
+-	if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts))
++	struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
++
++	if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) ||
++	    !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability))
+ 		return -EINVAL;
+ 
+ 	f->pixelformat = rkvdec_coded_fmts[f->index].fourcc;
+@@ -946,14 +971,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx)
+ 	int ret;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++)
+-		nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
++		if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities)
++			nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
+ 
+ 	v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
+-		ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
+-		if (ret)
+-			goto err_free_handler;
++		if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) {
++			ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
++			if (ret)
++				goto err_free_handler;
++		}
+ 	}
+ 
+ 	ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
+@@ -1155,8 +1183,17 @@ static void rkvdec_watchdog_func(struct work_struct *work)
+ 	}
+ }
+ 
++static const struct rkvdec_variant rk3399_rkvdec_variant = {
++        .capabilities   = RKVDEC_CAPABILITY_H264 |
++		           RKVDEC_CAPABILITY_HEVC |
++			   RKVDEC_CAPABILITY_VP9
++};
++
+ static const struct of_device_id of_rkvdec_match[] = {
+-	{ .compatible = "rockchip,rk3399-vdec" },
++	{
++		.compatible = "rockchip,rk3399-vdec",
++		.data = &rk3399_rkvdec_variant,
++	},
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, of_rkvdec_match);
+@@ -1168,6 +1205,7 @@ static const char * const rkvdec_clk_names[] = {
+ static int rkvdec_probe(struct platform_device *pdev)
+ {
+ 	struct rkvdec_dev *rkvdec;
++	const struct rkvdec_variant *variant;
+ 	unsigned int i;
+ 	int ret, irq;
+ 
+@@ -1193,6 +1231,13 @@ static int rkvdec_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
++	variant = of_device_get_match_data(rkvdec->dev);
++	if (!variant)
++		return -EINVAL;
++
++	rkvdec->capabilities = variant->capabilities;
++
++
+ 	rkvdec->regs = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(rkvdec->regs))
+ 		return PTR_ERR(rkvdec->regs);
+diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
+index d6222a2588be..ad8e83884121 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.h
++++ b/drivers/staging/media/rkvdec/rkvdec.h
+@@ -29,6 +29,10 @@
+ 
+ #define RKVDEC_RESET_DELAY	5
+ 
++#define RKVDEC_CAPABILITY_H264	BIT(0)
++#define RKVDEC_CAPABILITY_HEVC	BIT(1)
++#define RKVDEC_CAPABILITY_VP9	BIT(2)
++
+ struct rkvdec_ctx;
+ 
+ struct rkvdec_ctrl_desc {
+@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
+ 			    base.vb.vb2_buf);
+ }
+ 
++struct rkvdec_variant {
++        unsigned int capabilities;
++};
++
+ struct rkvdec_coded_fmt_ops {
+ 	int (*adjust_fmt)(struct rkvdec_ctx *ctx,
+ 			  struct v4l2_format *f);
+@@ -91,6 +99,7 @@ struct rkvdec_coded_fmt_desc {
+ 	unsigned int num_decoded_fmts;
+ 	const u32 *decoded_fmts;
+ 	u32 subsystem_flags;
++	unsigned int capability;
+ };
+ 
+ struct rkvdec_dev {
+@@ -105,6 +114,7 @@ struct rkvdec_dev {
+ 	struct delayed_work watchdog_work;
+ 	struct reset_control *rstc;
+ 	u8 reset_mask;
++	unsigned int capabilities;
+ };
+ 
+ struct rkvdec_ctx {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 30 Jan 2021 18:21:59 +0100
+Subject: [PATCH] media: rkvdec: add RK3288 variant
+
+This adds RK3288 variant to rkvdec driver. In this earlier version
+of the IP only HEVC decoding is supported.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
+index 955c53afe20f..4e228cd82f21 100644
+--- a/drivers/staging/media/rkvdec/rkvdec.c
++++ b/drivers/staging/media/rkvdec/rkvdec.c
+@@ -1189,11 +1189,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = {
+ 			   RKVDEC_CAPABILITY_VP9
+ };
+ 
++static const struct rkvdec_variant rk3288_hevc_variant = {
++        .capabilities   = RKVDEC_CAPABILITY_HEVC
++};
++
+ static const struct of_device_id of_rkvdec_match[] = {
+ 	{
+ 		.compatible = "rockchip,rk3399-vdec",
+ 		.data = &rk3399_rkvdec_variant,
+ 	},
++	{
++		.compatible = "rockchip,rk3288-hevc",
++		.data = &rk3288_hevc_variant,
++	},
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, of_rkvdec_match);
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 30 Jan 2021 18:27:30 +0100
+Subject: [PATCH] ARM: dts: RK3288: add hevc node
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm/boot/dts/rockchip/rk3288.dtsi | 21 ++++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+index 7b2cde230b87..59fba3ac6aae 100644
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
+@@ -1248,6 +1248,25 @@ vpu_mmu: iommu@ff9a0800 {
+ 		power-domains = <&power RK3288_PD_VIDEO>;
+ 	};
+ 
++	hevc: hevc@ff9c0000 {
++		compatible = "rockchip,rk3288-hevc";
++		reg = <0x0 0xff9c0000 0x0 0x400>;
++		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "irq_dec";
++		clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>,
++			 <&cru SCLK_HEVC_CORE>;
++		clock-names = "axi", "ahb", "cabac", "core";
++		assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
++				   <&cru SCLK_HEVC_CORE>,
++				   <&cru SCLK_HEVC_CABAC>;
++		assigned-clock-rates = <400000000>, <100000000>,
++				       <300000000>, <300000000>;
++		iommus = <&hevc_mmu>;
++		power-domains = <&power RK3288_PD_HEVC>;
++		resets =  <&cru SRST_HEVC>;
++		reset-names = "video_core";
++	};
++
+ 	hevc_mmu: iommu@ff9c0440 {
+ 		compatible = "rockchip,iommu";
+ 		reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
+@@ -1255,7 +1274,7 @@ hevc_mmu: iommu@ff9c0440 {
+ 		clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
+ 		clock-names = "aclk", "iface";
+ 		#iommu-cells = <0>;
+-		status = "disabled";
++		power-domains = <&power RK3288_PD_HEVC>;
+ 	};
+ 
+ 	gpu: gpu@ffa30000 {
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+Date: Tue, 10 May 2022 14:37:29 -0400
+Subject: [PATCH] media: rkvdec: Fix HEVC RPS bit offsets
+
+The offsets from the uAPI need to be extended to include some bits
+that can be calculated from the parameters. This has been compared
+to match with the vendor bit sizes (which simply parse again the
+data to calcualte it).
+
+Fixed by this change:
+- LTRPSPS_A_Qualcomm_1
+- RPS_C_ericsson_5
+- RPS_D_ericsson_6
+- RPS_E_qualcomm_5
+
+Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+---
+ drivers/staging/media/rkvdec/rkvdec-hevc.c | 26 +++++++++++++++++++---
+ 1 file changed, 23 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+index 7a375a23eaf1..580073d49b6a 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+@@ -10,6 +10,7 @@
+  */
+ 
+ #include <media/v4l2-mem2mem.h>
++#include <linux/bitops.h>
+ 
+ #include "rkvdec.h"
+ #include "rkvdec-regs.h"
+@@ -2175,6 +2176,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ 			    struct rkvdec_hevc_run *run)
+ {
+ 	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
++	const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ 	const struct v4l2_ctrl_hevc_slice_params *sl_params;
+ 	const struct v4l2_hevc_dpb_entry *dpb;
+ 	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+@@ -2196,9 +2198,21 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ #define NUM_RPS_POC				PS_FIELD(202, 4)
+ 
+ 	for (j = 0; j < run->num_slices; j++) {
++		uint st_bit_offset = 0;
++
+ 		sl_params = &run->slices_params[j];
+ 		dpb = decode_params->dpb;
+-		lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1;
++
++		if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
++			num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
++
++			if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
++				num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
++
++			lowdelay = 1;
++		} else {
++			lowdelay = 0;
++		}
+ 
+ 		hw_ps = &priv_tbl->rps[j];
+ 		memset(hw_ps, 0, sizeof(*hw_ps));
+@@ -2224,8 +2238,14 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ 
+ 		WRITE_RPS(lowdelay, LOWDELAY);
+ 
+-		WRITE_RPS(sl_params->long_term_ref_pic_set_size +
+-			  sl_params->short_term_ref_pic_set_size,
++		if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
++			if (sl_params->short_term_ref_pic_set_size)
++				st_bit_offset = sl_params->short_term_ref_pic_set_size;
++			else if (sps->num_short_term_ref_pic_sets > 1)
++				st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
++		}
++
++		WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
+ 			  LONG_TERM_RPS_BIT_OFFSET);
+ 		WRITE_RPS(sl_params->short_term_ref_pic_set_size,
+ 			  SHORT_TERM_RPS_BIT_OFFSET);
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+Date: Tue, 10 May 2022 15:12:03 -0400
+Subject: [PATCH] media: rkvdec: Fix number of HEVC references being set in RPS
+
+The numbers from the bitstream are values between 1 - 16 (as they are
+the number - 1). The difference between 0 and 1 needs to be determined
+base on the slice type. I frames have no reference, P frames only have
+L0 reference, and B frames have both.
+
+Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+---
+ drivers/staging/media/rkvdec/rkvdec-hevc.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+index 580073d49b6a..ce15028918b2 100644
+--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
+@@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ 
+ 	for (j = 0; j < run->num_slices; j++) {
+ 		uint st_bit_offset = 0;
++		uint num_l0_refs = 0;
++		uint num_l1_refs = 0;
+ 
+ 		sl_params = &run->slices_params[j];
+ 		dpb = decode_params->dpb;
+@@ -2217,7 +2219,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ 		hw_ps = &priv_tbl->rps[j];
+ 		memset(hw_ps, 0, sizeof(*hw_ps));
+ 
+-		for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) {
++		for (i = 0; i < num_l0_refs; i++) {
+ 			WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
+ 				  REF_PIC_LONG_TERM_L0(i));
+ 			WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
+@@ -2227,7 +2229,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ 
+ 		}
+ 
+-		for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) {
++		for (i = 0; i < num_l1_refs; i++) {
+ 			WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
+ 				  REF_PIC_LONG_TERM_L1(i));
+ 			WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
diff --git a/patch/kernel/archive/rockchip64-6.10/general-workaround-broadcom-bt-serdev.patch b/patch/kernel/archive/rockchip64-6.10/general-workaround-broadcom-bt-serdev.patch
new file mode 100644
index 000000000000..7404b49d2f63
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/general-workaround-broadcom-bt-serdev.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 1 May 2021 12:41:14 +0000
+Subject: Workaround to make several broadcom bluetooth serdev devices work
+ even without proper MAC address
+
+---
+ drivers/bluetooth/btbcm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c
+index 0a5445ac5e1b..06b442260c94 100644
+--- a/drivers/bluetooth/btbcm.c
++++ b/drivers/bluetooth/btbcm.c
+@@ -134,7 +134,7 @@ int btbcm_check_bdaddr(struct hci_dev *hdev)
+ 		if (btbcm_set_bdaddr_from_efi(hdev) != 0) {
+ 			bt_dev_info(hdev, "BCM: Using default device address (%pMR)",
+ 				    &bda->bdaddr);
+-			set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks);
++			//set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks);
+ 		}
+ 	}
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/kernel-6.8-tools-cgroup-makefile.patch b/patch/kernel/archive/rockchip64-6.10/kernel-6.8-tools-cgroup-makefile.patch
new file mode 100644
index 000000000000..068fe83689d6
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/kernel-6.8-tools-cgroup-makefile.patch
@@ -0,0 +1,17 @@
+diff --git a/tools/cgroup/Makefile b/tools/cgroup/Makefile
+new file mode 100644
+index 000000000000..ffca068e4a76
+--- /dev/null
++++ b/tools/cgroup/Makefile
+@@ -0,0 +1,11 @@
++# SPDX-License-Identifier: GPL-2.0
++# Makefile for cgroup tools
++
++CFLAGS = -Wall -Wextra
++
++all: cgroup_event_listener
++%: %.c
++	$(CC) $(CFLAGS) -o $@ $^
++
++clean:
++	$(RM) cgroup_event_listener
diff --git a/patch/kernel/archive/rockchip64-6.10/media-0001-Add-rkvdec2-Support-v3.patch b/patch/kernel/archive/rockchip64-6.10/media-0001-Add-rkvdec2-Support-v3.patch
new file mode 120000
index 000000000000..2bf683db5fce
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/media-0001-Add-rkvdec2-Support-v3.patch
@@ -0,0 +1 @@
+../rockchip-rk3588-6.10/0027-RK3588-Add-rkvdec2-Support-v3.patch
\ No newline at end of file
diff --git a/patch/kernel/archive/rockchip64-6.10/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch b/patch/kernel/archive/rockchip64-6.10/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch
new file mode 120000
index 000000000000..7f8efa7efc63
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch
@@ -0,0 +1 @@
+../rockchip-rk3588-6.10/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch
\ No newline at end of file
diff --git a/patch/kernel/archive/rockchip64-6.10/media-0003-rk3568-disable-hantro-h264.patch b/patch/kernel/archive/rockchip64-6.10/media-0003-rk3568-disable-hantro-h264.patch
new file mode 100644
index 000000000000..b5bd91af5ad5
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/media-0003-rk3568-disable-hantro-h264.patch
@@ -0,0 +1,63 @@
+diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
+index 34b123daf..802a5dca1 100644
+--- a/drivers/media/platform/verisilicon/hantro_drv.c
++++ b/drivers/media/platform/verisilicon/hantro_drv.c
+@@ -721,7 +721,6 @@ static const struct of_device_id of_hantro_match[] = {
+ 	{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
+ 	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
+ 	{ .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
+-	{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
+ 	{ .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, },
+ #endif
+ #ifdef CONFIG_VIDEO_HANTRO_IMX8M
+diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h
+index 7737320cc..5aa048ef3 100644
+--- a/drivers/media/platform/verisilicon/hantro_hw.h
++++ b/drivers/media/platform/verisilicon/hantro_hw.h
+@@ -404,7 +404,6 @@ extern const struct hantro_variant rk3288_vpu_variant;
+ extern const struct hantro_variant rk3328_vpu_variant;
+ extern const struct hantro_variant rk3399_vpu_variant;
+ extern const struct hantro_variant rk3568_vepu_variant;
+-extern const struct hantro_variant rk3568_vpu_variant;
+ extern const struct hantro_variant rk3588_vpu981_variant;
+ extern const struct hantro_variant sama5d4_vdec_variant;
+ extern const struct hantro_variant sunxi_vpu_variant;
+diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+index f97527670..5707dce4b 100644
+--- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
++++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+@@ -719,10 +719,9 @@ const struct hantro_variant rk3288_vpu_variant = {
+ 
+ const struct hantro_variant rk3328_vpu_variant = {
+ 	.dec_offset = 0x400,
+-	.dec_fmts = rockchip_vdpu2_dec_fmts,
+-	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
+-	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
+-		 HANTRO_H264_DECODER,
++	.dec_fmts = rk3399_vpu_dec_fmts,
++	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
++	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,
+ 	.codec_ops = rk3399_vpu_codec_ops,
+ 	.irqs = rockchip_vdpu2_irqs,
+ 	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
+@@ -766,20 +765,6 @@ const struct hantro_variant rk3568_vepu_variant = {
+ 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
+ };
+ 
+-const struct hantro_variant rk3568_vpu_variant = {
+-	.dec_offset = 0x400,
+-	.dec_fmts = rockchip_vdpu2_dec_fmts,
+-	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
+-	.codec = HANTRO_MPEG2_DECODER |
+-		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
+-	.codec_ops = rk3399_vpu_codec_ops,
+-	.irqs = rockchip_vdpu2_irqs,
+-	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
+-	.init = rockchip_vpu_hw_init,
+-	.clk_names = rockchip_vpu_clk_names,
+-	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
+-};
+-
+ const struct hantro_variant px30_vpu_variant = {
+ 	.enc_offset = 0x0,
+ 	.enc_fmts = rockchip_vpu_enc_fmts,
diff --git a/patch/kernel/archive/rockchip64-6.10/net-usb-r8152-add-LED-configuration-from-OF.patch b/patch/kernel/archive/rockchip64-6.10/net-usb-r8152-add-LED-configuration-from-OF.patch
new file mode 100644
index 000000000000..5e331b1e7477
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/net-usb-r8152-add-LED-configuration-from-OF.patch
@@ -0,0 +1,79 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 26 Jul 2020 02:38:31 +0200
+Subject: net: usb: r8152: add LED configuration from OF
+
+This adds the ability to configure the LED configuration register using
+OF. This way, the correct value for board specific LED configuration can
+be determined.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/net/usb/r8152.c | 23 ++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
+index afb20c0ed688..f2fa63b5ad05 100644
+--- a/drivers/net/usb/r8152.c
++++ b/drivers/net/usb/r8152.c
+@@ -11,6 +11,7 @@
+ #include <linux/mii.h>
+ #include <linux/ethtool.h>
+ #include <linux/usb.h>
++#include <linux/of.h>
+ #include <linux/crc32.h>
+ #include <linux/if_vlan.h>
+ #include <linux/uaccess.h>
+@@ -6980,6 +6981,22 @@ static void rtl_tally_reset(struct r8152 *tp)
+ 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
+ }
+ 
++static int r8152_led_configuration(struct r8152 *tp)
++{
++	u32 led_data;
++	int ret;
++
++	ret = of_property_read_u32(tp->udev->dev.of_node, "realtek,led-data",
++								&led_data);
++
++	if (ret)
++		return ret;
++	
++	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data);
++
++	return 0;
++}
++
+ static void r8152b_init(struct r8152 *tp)
+ {
+ 	u32 ocp_data;
+@@ -7021,6 +7038,8 @@ static void r8152b_init(struct r8152 *tp)
+ 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
+ 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
+ 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153_init(struct r8152 *tp)
+@@ -7161,6 +7180,8 @@ static void r8153_init(struct r8152 *tp)
+ 		tp->coalesce = COALESCE_SLOW;
+ 		break;
+ 	}
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153b_init(struct r8152 *tp)
+@@ -7243,6 +7264,8 @@ static void r8153b_init(struct r8152 *tp)
+ 	rtl_tally_reset(tp);
+ 
+ 	tp->coalesce = 15000;	/* 15 us */
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153c_init(struct r8152 *tp)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/Makefile b/patch/kernel/archive/rockchip64-6.10/overlay/Makefile
new file mode 100644
index 000000000000..be8b1f59e69f
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/Makefile
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0
+dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
+	rk3308-s0-ext-antenna.dtbo \
+	rk3308-b@1.3ghz.dtbo \
+	rk3308-bs.dtbo rk3308-bs@1.3ghz.dtbo \
+	rk3308-emmc.dtbo \
+	rk3308-sdio@10mhz.dtbo rk3308-sdio@4mhz.dtbo \
+	rockchip-rockpi4cplus-usb-host.dtbo \
+	rockchip-rockpro64-lcd.dtbo \
+	rockchip-rk3318-box-cpu-hs.dtbo \
+	rockchip-rk3318-box-emmc-ddr.dtbo \
+	rockchip-rk3318-box-emmc-hs200.dtbo \
+	rockchip-rk3318-box-led-conf1.dtbo \
+	rockchip-rk3318-box-led-conf2.dtbo \
+	rockchip-rk3318-box-led-conf3.dtbo \
+	rockchip-rk3318-box-led-conf4.dtbo \
+	rockchip-rk3318-box-wlan-ap6330.dtbo \
+	rockchip-rk3318-box-wlan-ap6334.dtbo \
+	rockchip-rk3318-box-wlan-ext.dtbo \
+	rockchip-rk3328-i2c0.dtbo \
+	rockchip-rk3328-i2s1-pcm5102.dtbo \
+	rockchip-rk3328-opp-1.4ghz.dtbo \
+	rockchip-rk3328-opp-1.5ghz.dtbo \
+	rockchip-rk3328-spi-spidev.dtbo \
+	rockchip-rk3328-uart1.dtbo \
+	rockchip-rk3399-dwc3-0-host.dtbo \
+	rockchip-rk3399-i2c7.dtbo \
+	rockchip-rk3399-i2c8.dtbo \
+	rockchip-rk3399-opp-2ghz.dtbo \
+	rockchip-rk3399-pcie-gen2.dtbo \
+	rockchip-rk3399-spi-jedec-nor.dtbo \
+	rockchip-rk3399-spi-spidev.dtbo \
+	rockchip-rk3399-uart4.dtbo \
+	rockchip-rk3399-w1-gpio.dtbo \
+	rockchip-rk3566-sata2.dtbo \
+	rockchip-rk3568-nanopi-r5c-leds.dtbo \
+	rockchip-rk3568-nanopi-r5s-leds.dtbo \
+	rockchip-rk3568-hk-i2c0.dtbo \
+	rockchip-rk3568-hk-i2c1.dtbo \
+	rockchip-rk3568-hk-pwm1.dtbo \
+	rockchip-rk3568-hk-pwm2.dtbo \
+	rockchip-rk3568-hk-pwm9.dtbo \
+	rockchip-rk3568-hk-spi-spidev.dtbo \
+	rockchip-rk3568-hk-uart0.dtbo \
+	rockchip-rk3568-hk-uart0-rts_cts.dtbo \
+	rockchip-rk3568-hk-uart1.dtbo
+
+scr-$(CONFIG_ARCH_ROCKCHIP) += \
+       rockchip-fixup.scr
+
+dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \
+       README.rockchip-overlays
+
+dtb-y += $(dtbo-y) $(scr-y) $(dtbotxt-y)
+
+clean-files    := *.dtbo *.scr
+
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/README.rockchip-overlays b/patch/kernel/archive/rockchip64-6.10/overlay/README.rockchip-overlays
new file mode 100644
index 000000000000..983938425965
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/README.rockchip-overlays
@@ -0,0 +1,259 @@
+This document describes overlays provided in the kernel packages
+For generic Armbian overlays documentation please see
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
+
+### Platform:
+
+rockchip (Rockchip)
+
+### Provided overlays:
+
+- i2c7, i2c8, pcie-gen2, spi-spidev, uart4, w1-gpio
+
+for RK3308 (Rock PI-S)
+
+- rk3308bs rk3308bs-1.3ghz sdio-10mhz sdio-4mhz emmc
+
+### Overlay details:
+
+### i2c7
+
+Activates TWI/I2C bus 7
+
+I2C7 pins (SCL, SDA): GPIO2-B0, GPIO2-A7 GPIO1-C5, GPIO1-C4
+
+### i2c8
+
+Activates TWI/I2C bus 8
+
+I2C8 pins (SCL, SDA): GPIO1-C5, GPIO1-C4
+
+### pcie-gen2
+
+Enables PCIe Gen2 link speed on RK3399.
+WARNING! Not officially supported by Rockchip!!!
+
+### rk3328-i2c0
+
+Activates TWI/I2C bus 0
+
+I2C0 (SCL, SDA): GPIO2-D0, GPIO2-D1
+
+### rk3328-uart1
+
+Activates UART1
+
+UART1 pins (RX, TX): GPIO3_A6, GPIO3_A4
+
+### rk3328-opp-1.4ghz
+
+Adds the 1.4GHz opp for overclocking
+WARNING! Not officially supported by Rockchip!!!
+
+### rk3328-opp-1.5ghz
+
+Adds the 1.5GHz opp for overclocking
+WARNING! Not officially supported by Rockchip!!!
+
+### rk3399-opp-2ghz
+
+Adds the 2GHz big and 1.5 GHz LITTLE opps for overclocking
+WARNING! Not officially supported by Rockchip!!!
+
+### rockpi4cplus-usb-host
+
+Switches the top USB 3.0 port to host mode.
+WARNING! Not officially supported by Rockchip!!!
+
+### spi-jedec-nor
+
+Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
+supported by the kernel SPI NOR driver
+
+SPI 0 pins (MOSI, MISO, SCK, CS): GPIO3_A5, GPIO3_A4, GPIO3_A6, GPIO3_A7
+SPI 1 pins (MOSI, MISO, SCK, CS): GPIO1_A7, GPIO1_B0, GPIO1_B1, GPIO1_B2
+SPI 2 pins (MOSI, MISO, SCK, CS): GPIO1_C0, GPIO1_B7, GPIO1_C1, GPIO1_C2
+SPI 3 pins (MOSI, MISO, SCK, CS): GPIO2_B2, GPIO2_B1, GPIO2_B3, GPIO2_B4
+
+Parameters:
+
+param_spinor_spi_bus (int)
+	SPI bus to activate SPI NOR flash support on
+	Required
+	Supported values: 0, 1, 2
+
+param_spinor_max_freq (int)
+	Maximum SPI frequency
+	Optional
+	Default: 1000000
+	Range: 3000 - 100000000
+
+### spi-spidev
+
+Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
+where X is the bus number and Y is the CS number
+
+SPI 0 pins (MOSI, MISO, SCK, CS): GPIO3_A5, GPIO3_A4, GPIO3_A6, GPIO3_A7
+SPI 1 pins (MOSI, MISO, SCK, CS): GPIO1_A7, GPIO1_B0, GPIO1_B1, GPIO1_B2
+SPI 2 pins (MOSI, MISO, SCK, CS): GPIO1_C0, GPIO1_B7, GPIO1_C1, GPIO1_C2
+SPI 3 pins (MOSI, MISO, SCK, CS): GPIO2_B2, GPIO2_B1, GPIO2_B3, GPIO2_B4
+
+Parameters:
+
+param_spidev_spi_bus (int)
+	SPI bus to activate SPIdev support on
+	Required
+	Supported values: 0, 1
+
+param_spidev_spi_cs (int)
+	SPI chip select number
+	Optional
+	Default: 0
+	Supported values: 0, 1
+	Using chip select 1 requires using "spi-add-cs1" overlay
+
+param_spidev_max_freq (int)
+	Maximum SPIdev frequency
+	Optional
+	Default: 1000000
+	Range: 3000 - 100000000
+
+### uart4
+
+Activates UART4
+
+UART4 pins (RX, TX): GPIO1_A7, GPIO1_B0
+
+Notice: UART4 cannot be activated together with SPI1 - they share the sam pins.
+Enabling this overlay disables SPI1.
+
+### dwc3-0-host
+
+Forces port 0 of the DesignWare xHCI controller to host mode.
+
+This can be used on plaforms such as NanoPC-T4, where devices plugged into the
+USB-C port may not be detected otherwise.
+
+### w1-gpio
+
+Activates 1-Wire GPIO master
+Requires an external pull-up resistor on the data pin
+or enabling the internal pull-up
+
+### rk3318-box-led-conf1
+
+Activates led/gpio configuration for rk3318 tv box boards with signature
+YX_RK3328 and clones
+
+### rk3318-box-led-conf2
+
+Activates led/gpio configuration for rk3318 tv box boards withs signature
+X88_PRO_B and clones
+
+### rk3318-box-led-conf3
+
+This device tree overlay is suitable for MXQ-RK3328-D4_A board which
+has an integrated PMIC (RK805). The dtbo is very important to achieve
+1.3 Ghz speed for CPU and stable voltages for other parts of the
+system. Also enables gpio leds and keys.
+
+### rk3318-box-led-conf4
+
+Generic rk3318-box configuration but with sdio chip on sdmmc-ext connector
+
+### rk3318-box-emmc-ddr
+
+Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
+nowadays support DDR mode, but its reliability heavily depends upon the quality
+of board wiring
+
+### rk3318-box-emmc-hs200
+
+Activates eMMC HS200 capability for rk3318 tv box boards.
+It should in autodetect mode, but some board have faulty or cheap circuitry that
+enable the mode but then it doesn't work correctly.
+
+### rk3318-box-wlan-ap6334
+
+Set up additional device tree bits to properly support ap6334 (broadcom BCM4334)
+wifi chip and clones
+
+### rk3318-box-wlan-ext
+
+Use sdmmc_ext device for sdio devices, enabled wifi on some boards (notably
+X88 Pro) which have wifi chip attached to sdmmc_ext controller.
+
+### rk3318-box-wlan-ap6330
+
+Set up additional device tree bits properly support ap6330 (broaccom BCM4330)
+wifi + bt chip and clones.
+
+### rk3318-box-cpu-hs
+
+Enable additional cpu "high-speed" bins up to 1.3ghz
+
+**********************************
+Details for Rock Pi-S overlays  (2 Mar 2024):
+
+Older V1.1 and V1.2 boards use the B variant of the RK3308.
+Some V1.3 boards manufactured after October 2023 also use the B variant.
+To overclock the RK3308B, apply:
+###  rk3308-b@1.3ghz
+
+V1.3 boards produced during 2022 and most of 2023 use the lower voltage
+B-S variant of the RK3308.
+Per Radxa, these chips will be marked RK3308BS instead of RK3308B
+All boards utilizing the RK3308B-S part should apply the:
+###  rk3308-bs
+overlay to operate at the appropriate (lower) the core voltage.
+This overlay also enables operation at 1.1Ghz.
+
+Optionally, boards utilizing the RK3308B-S parts may add the
+###  rk3308-bs@1.3ghz
+to overclock the B-S CPU to 1.3Ghz.
+Apply the rk3308-bs@1.3Ghz overlay  *after applying*  rk3308-bs
+
+Applying the *-bs overlays to the B variant of the SOC may result in
+unstable operation due to undervolting.
+Applying the rk3308-b@1.3ghz to a BS variant chip consumes more power and
+has the potential to damage the SOC due to overvolting.
+
+=====  For Older Kernels  ======
+Install the following overlays only on older (unpatched) mainline kernels:
+
+Older mainline kernels disable the Rock Pi S built-in SDNAND (EMMC)
+###  rk3308-emmc
+enables your SDNAND chip.  It is OK to install for boards that lack the SDNAND.
+
+The legacy 4.4 and this mainline kernel drive the SDIO clock at 50Mhz to provide
+maximum WiFi throughput.  However...
+
+Older versions of the Mainline kernel drive the SDIO clock at only 1Mhz
+This reduces WiFi throughput to < 500kB/s !
+
+###  rk3308-sdio@10mhz
+increases the SDIO clock to 10Mhz, providing about 2.4MB/s WiFi throughput.
+
+###  rk3308-sdio@4mhz
+increases the SDIO clock to only 4Mhz, providing about 1MB/s WiFi throughput.
+use this only if 10Mhz SDIO clock is unstable
+
+Note that older mainline kernels cannot drive the SDIO clock faster than 10Mhz.
+
+
+**********************************
+Details for Rock S0 overlays  (10 Apr 2024):
+
+By default, the internal WiFi selects its internal chip antenna.
+This antenna is so noisy as to be nearly unusable.
+The external antenna, fortunately, works quite well.
+Connect an external WiFi antenna and select it with:
+###  rk3308-s0-ext-antenna
+
+All Rock S0 boards use the RK3308B chip.
+The:
+###  rk3308-b@1.3ghz
+overlay enables (overclocked) operation at 1.3ghz
+1.3Ghz operation appears stable on the two boards I've tested.
+
+The legacy kernel is not supported on the Rock S0
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-b@1.3ghz.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-b@1.3ghz.dtso
new file mode 100644
index 000000000000..4f022bd4a1a9
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-b@1.3ghz.dtso
@@ -0,0 +1,27 @@
+//Overclock the Rockchip RK3308-B suffix SOC to 1.3 Ghz
+//  THIS SHOULD NOT BE APPLIED to RK3308-B-S suffix chips
+//  because is will overvolt them
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&cpu0_opp_table>;
+		__overlay__ {
+			//the following are unsupported, overclocked operating points
+			opp-1200000000 {
+				opp-hz = /bits/ 64 <1200000000>;
+				opp-microvolt = <1250000 1250000 1340000>;
+				clock-latency-ns = <40000>;
+				status = "okay";
+			};
+			opp-1296000000 {
+				opp-hz = /bits/ 64 <1296000000>;
+				opp-microvolt = <1300000 1300000 1340000>;
+				clock-latency-ns = <40000>;
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-bs.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-bs.dtso
new file mode 100644
index 000000000000..978f67947380
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-bs.dtso
@@ -0,0 +1,39 @@
+//Adjustments for Rockchip RK3308-BS suffix SOC
+//https://dl.radxa.com/rockpis/docs/sw/RK3308B-S&RK3308H-S_Software_Compatibility_Introduction_V1.0.0_20211016.pdf
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&cpu0_opp_table>;
+		__overlay__ {
+			opp-408000000 {
+				opp-hz = /bits/ 64 <408000000>;
+				opp-microvolt = <850000 850000 1200000>;
+				clock-latency-ns = <40000>;
+				opp-suspend;
+			};
+			opp-600000000 {
+				opp-hz = /bits/ 64 <600000000>;
+				opp-microvolt = <900000 900000 1200000>;
+				clock-latency-ns = <40000>;
+			};
+			opp-816000000 {
+				opp-hz = /bits/ 64 <816000000>;
+				opp-microvolt = <1000000 1000000 1200000>;
+				clock-latency-ns = <40000>;
+			};
+			opp-1008000000 {
+				opp-hz = /bits/ 64 <1008000000>;
+				opp-microvolt = <1125000 1125000 1200000>;
+				clock-latency-ns = <40000>;
+			};
+			opp-1104000000 {
+				opp-hz = /bits/ 64 <1104000000>;
+				opp-microvolt = <1200000 1200000 1200000>;
+				clock-latency-ns = <40000>;
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-bs@1.3ghz.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-bs@1.3ghz.dtso
new file mode 100644
index 000000000000..3fae0dd2363f
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-bs@1.3ghz.dtso
@@ -0,0 +1,26 @@
+//Overclock the Rockchip RK3308-BS suffix SOC to 1.3 Ghz
+//  assumes rk3308bs-rock-pi-s.dts overlay has already been added
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&cpu0_opp_table>;
+		__overlay__ {
+			//the following are unsupported, overclocked operating points
+			opp-1200000000 {
+				opp-hz = /bits/ 64 <1200000000>;
+				opp-microvolt = <1200000 1200000 1200000>;
+				clock-latency-ns = <40000>;
+				status = "okay";
+			};
+			opp-1296000000 {
+				opp-hz = /bits/ 64 <1296000000>;
+				opp-microvolt = <1200000 1200000 1200000>;
+				clock-latency-ns = <40000>;
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-emmc.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-emmc.dtso
new file mode 100644
index 000000000000..4a4c3804d1aa
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-emmc.dtso
@@ -0,0 +1,13 @@
+//For RockPI-S:  enable SDnand chip
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&emmc>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-s0-ext-antenna.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-s0-ext-antenna.dtso
new file mode 100644
index 000000000000..7fa763840648
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-s0-ext-antenna.dtso
@@ -0,0 +1,48 @@
+//Select Rock S0's external WiFi antenna input
+//(instead of default internal WiFi antenna)
+
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+	fragment@0 {
+		target-path = "/";
+
+		__overlay__ {
+			ext_antenna: ext-antenna {
+				status = "okay";
+				compatible = "regulator-fixed";
+				enable-active-low;
+				gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+				regulator-always-on;
+				regulator-boot-on;
+				pinctrl-0 = <&ant_2>;
+				pinctrl-names = "default";
+				regulator-name = "ext_antenna";
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&board_antenna>;
+
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+	fragment@2 {
+		target = <&pinctrl>;
+
+		__overlay__ {
+			antenna {
+				ant_2: ant-2 {
+					rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
+				};
+			};
+		};
+	};
+};
+
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-sdio@10mhz.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-sdio@10mhz.dtso
new file mode 100644
index 000000000000..c7f2e280f7ae
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-sdio@10mhz.dtso
@@ -0,0 +1,14 @@
+//For RockPI-S:  Increase SDIO Max Frequency from 1Mhz to 10Mhz
+//Increases RTL8723-BS WiFi's throughput from 300KB/s to 2.4MB/s
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&sdio>;
+		__overlay__ {
+			max-frequency = <10000000>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-sdio@4mhz.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-sdio@4mhz.dtso
new file mode 100644
index 000000000000..efcc5c265284
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rk3308-sdio@4mhz.dtso
@@ -0,0 +1,14 @@
+//For RockPI-S:  Increase SDIO Max Frequency from 1Mhz to 4Mhz
+//Increases RTL8723-BS WiFi's throughput from 300KB/s to 1MB/s
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&sdio>;
+		__overlay__ {
+			max-frequency = <4000000>;
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-fixup.scr-cmd b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-fixup.scr-cmd
new file mode 100644
index 000000000000..c6cd5d8abde1
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-fixup.scr-cmd
@@ -0,0 +1,65 @@
+# overlays fixup script
+# implements (or rather substitutes) overlay arguments functionality
+# using u-boot scripting, environment variables and "fdt" command
+
+setenv decompose_pin 'setexpr tmp_pinctrl sub "GPIO(0|1|2|3|4)_\\S\\d+" "\\1";
+setexpr tmp_bank sub "GPIO\\d_(\\S)\\d+" "\\1";
+test "${tmp_bank}" = "A" && setenv tmp_bank 0;
+test "${tmp_bank}" = "B" && setenv tmp_bank 1;
+test "${tmp_bank}" = "C" && setenv tmp_bank 2;
+test "${tmp_bank}" = "D" && setenv tmp_bank 3;
+setexpr tmp_pin sub "GPIO\\d_\\S(\\d+)" "\\1";
+setexpr tmp_bank ${tmp_bank} * 8;
+setexpr tmp_pin ${tmp_bank} + ${tmp_pin}'
+
+if test -n "${param_spidev_max_freq}"; then
+    fdt set /spi@fe610000/spidev spi-max-frequency "<${param_spidev_max_freq}>"
+fi
+
+if test -n "${param_spinor_spi_bus}"; then
+	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@ff1c0000"
+	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@ff1d0000"
+	test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@ff1e0000"
+	test "${param_spinor_spi_bus}" = "3" && setenv tmp_spi_path "spi@ff1f0000"
+	fdt set /${tmp_spi_path} status "okay"
+	fdt set /${tmp_spi_path}/spiflash@0 status "okay"
+	if test -n "${param_spinor_max_freq}"; then
+		fdt set /${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
+	fi
+	if test "${param_spinor_spi_cs}" = "1"; then
+		fdt set /${tmp_spi_path}/spiflash@0 reg "<1>"
+	fi
+	env delete tmp_spi_path
+fi
+
+if test -n "${param_spidev_spi_bus}"; then
+	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@ff1c0000"
+	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@ff1d0000"
+	test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@ff1e0000"
+	test "${param_spidev_spi_bus}" = "3" && setenv tmp_spi_path "spi@ff1f0000"
+	fdt set /${tmp_spi_path} status "okay"
+	fdt set /${tmp_spi_path}/spidev status "okay"
+	if test -n "${param_spidev_max_freq}"; then
+		fdt set /${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
+	fi
+	if test "${param_spidev_spi_cs}" = "1"; then
+		fdt set /${tmp_spi_path}/spidev reg "<1>";
+	fi
+fi
+
+if test -n "${param_w1_pin}"; then
+	setenv tmp_pinctrl "${param_w1_pin}"
+	setenv tmp_bank "${param_w1_pin}"
+	setenv tmp_pin "${param_w1_pin}"
+	run decompose_pin
+	#echo "${param_w1_pin} ---> pinctrl = ${tmp_pinctrl}"
+	#echo "${param_w1_pin} ---> bank = ${tmp_bank}"
+	#echo "${param_w1_pin} ---> pin = ${tmp_pin}"
+	fdt get value tmp_pinctrl /__symbols__	gpio${tmp_pinctrl}
+	#echo "${param_w1_pin} ---> tmp_pinctrl = ${tmp_pinctrl}"
+	fdt get value tmp_phandle ${tmp_pinctrl} phandle
+	#echo "${param_w1_pin} ---> tmp_phandle = ${tmp_phandle}"
+	fdt set /onewire@0 gpios "<${tmp_phandle} 0x000000${tmp_pin} 0 0>"
+	env delete tmp_pinctrl tmp_bank tmp_pin tmp_phandle
+fi
+
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-cpu-hs.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-cpu-hs.dtso
new file mode 100644
index 000000000000..e6bc1adecae2
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-cpu-hs.dtso
@@ -0,0 +1,24 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target-path = "/opp_table0/opp-1200000000";
+		__overlay__ {
+
+			status = "okay";
+
+		};
+	};
+
+	fragment@1 {
+		target-path = "/opp_table0/opp-1296000000";
+		__overlay__ {
+
+			status = "okay";
+
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-emmc-ddr.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-emmc-ddr.dtso
new file mode 100644
index 000000000000..b8f139099871
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-emmc-ddr.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&emmc>;
+		__overlay__ {
+			status = "okay";
+			mmc-ddr-1_8v;
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-emmc-hs200.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-emmc-hs200.dtso
new file mode 100644
index 000000000000..55f8f7eb6a01
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-emmc-hs200.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+	fragment@0 {
+		target = <&emmc>;
+		__overlay__ {
+			status = "okay";
+			mmc-hs200-1_8v;
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf1.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf1.dtso
new file mode 100644
index 000000000000..26bfd7c634c0
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf1.dtso
@@ -0,0 +1,49 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/**
+ * Generic rk3318 board with base common configuration.
+ * Some boards with this configuration have signature: YX_RK3318 (circular board), RK3318_V1.x
+ */
+
+&gpio_led {
+
+	working {
+		gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>;
+		linux,default-trigger = "mmc2";
+	};
+
+	/*
+		* no auxiliary led on YX_RK3328 boards
+		*
+	auxiliary {
+		gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		label = "auxiliary";
+		linux,default-trigger = "mmc2";
+		default-state = "off";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_led_aux>;
+	};
+	*/
+
+};
+
+/*
+ * TODO: needs to find the GPIO for this
+ *
+&gpio_keys {
+
+	reset {
+		gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+		label = "reset";
+		linux,code = <KEY_RESTART>;
+		debounce-interval = <200>;
+		wakeup-source;
+	};
+
+};
+*/
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf2.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf2.dtso
new file mode 100644
index 000000000000..c5040e6a1f2e
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf2.dtso
@@ -0,0 +1,63 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+
+&gpio_led {
+
+	working {
+		gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
+		linux,default-trigger = "mmc2";
+	};
+
+	/*
+	 * no auxiliary led on X88_PRO_B boards
+	 *
+	auxiliary {
+		gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		label = "auxiliary";
+		linux,default-trigger = "mmc2";
+		default-state = "off";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_led_aux>;
+	};
+	*/
+
+};
+
+&vcc_otg_vbus {
+	gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+};
+
+&working_led {
+	rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none_2ma>;
+};
+
+&io_domains {
+	vccio6-supply = <&vcc_18>;
+};
+
+/*
+ * Following section enables the sdio bus on sdmmc_ext controller
+ */
+&sdio {
+	/delete-property/ mmc-pwrseq;
+	status = "disabled";
+};
+
+&sdio_ext {
+	mmc-pwrseq = <&sdio_pwrseq>;
+	status = "okay";
+};
+
+&sdmmc_ext {
+	status = "disabled";
+};
+
+&spdif {
+	pinctrl-0 = <&spdifm1_tx>;
+};
+
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf3.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf3.dtso
new file mode 100644
index 000000000000..a0d51304db8d
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf3.dtso
@@ -0,0 +1,305 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&{/regulators/regulator@0} {
+	status = "disabled";
+};
+
+&{/regulators/regulator@1} {
+	status = "disabled";
+};
+
+&{/vdd-arm} {
+	status = "disabled";
+};
+
+&{/vdd-log} {
+	status = "disabled";
+};
+
+&{/xin32k} {
+	status = "disabled";
+};
+
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	clock-frequency = <1000000>;
+	i2c-scl-rising-time-ns = <83>;
+	i2c-scl-falling-time-ns = <5>;
+	status = "okay";
+
+	rk805: rk805@18 {
+		compatible = "rockchip,rk805";
+		reg = <0x18>;
+		status = "okay";
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-parent = <&gpio2>;
+		interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk805-clkout2";
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc5-supply = <&rk805_vcc_io>;
+		vcc6-supply = <&rk805_vcc_io>;
+
+		rtc {
+			status = "okay";
+		};
+
+		pwrkey {
+			status = "okay";
+		};
+
+		gpio {
+			status = "okay";
+		};
+
+		regulators {
+			compatible = "rk805-regulator";
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <12500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vdd_arm: DCDC_REG2 {
+				regulator-name = "vdd_arm";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <12500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io: rk805_vcc_io: DCDC_REG4 {
+				regulator-name = "vccio_3v3";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vdd_18: vcc_18: LDO_REG1 {
+				regulator-name = "vccio_1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_18emmc: LDO_REG2 {
+				regulator-name = "vcc_18emmc";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_11: LDO_REG3 {
+				regulator-name = "vdd_11";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1100000>;
+				};
+			};
+		};
+	};
+
+};
+
+&pinctrl {
+
+	leds {
+		ir_led: ir-led {
+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+};
+
+&gpio_led {
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&ir_led>;
+
+	working {
+		gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
+		linux,default-trigger = "mmc2";
+		default-state = "off";
+		mode = <35>;
+	};
+
+	/*
+	 * These leds are described in the original dtb, but are not present on the board
+	auxiliary {
+		gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
+		linux,default-trigger = "mmc2";
+		default-state = "off";
+		mode = <5>;
+	};
+
+	ir {
+		gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+		linux,default-trigger = "ir";
+		default-state = "off";
+		mode = <0>;
+	};
+	*/
+
+};
+
+&io_domains {
+	vccio1-supply = <&vcc_io>;
+	vccio2-supply = <&vcc_18emmc>;
+	vccio3-supply = <&vcc_io>;
+	vccio4-supply = <&vdd_18>;
+	vccio5-supply = <&vcc_io>;
+	vccio6-supply = <&vcc_io>;
+	pmuio-supply = <&vcc_io>;
+};
+
+&{/} {
+	gpio_keys: gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power button";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&dmc {
+	center-supply = <&vdd_logic>;
+};
+
+&gpu {
+	mali-supply = <&vdd_logic>;
+};
+
+&vpu {
+	vcodec-supply = <&vdd_logic>;
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+
+&vcc_sd {
+	vin-supply = <&vcc_io>;
+};
+
+&emmc {
+	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc_18emmc>;
+};
+
+&saradc {
+	vref-supply = <&vcc_18>;
+};
+
+&pwm0 {
+	status = "disabled";
+};
+
+&pwm1 {
+	status = "disabled";
+};
+
+/*
+ * Following section enables the sdio bus on sdmmc_ext controller
+ */
+&sdio {
+	/delete-property/ mmc-pwrseq;
+	status = "disabled";
+};
+
+&sdio_ext {
+	rockchip,default-sample-phase = <112>; // Allows ssv6051 chips to be detected at 50 MHz
+	sd-uhs-sdr50;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	status = "okay";
+};
+
+&sdmmc_ext {
+	status = "disabled";
+};
+
+&spdif {
+	pinctrl-0 = <&spdifm1_tx>;
+};
+
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf4.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf4.dtso
new file mode 100644
index 000000000000..5d60f51069d8
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-led-conf4.dtso
@@ -0,0 +1,38 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/**
+ * Generic rk3318 board with sdio bus on sdmmc_ext connector
+ */
+
+&gpio_led {
+
+	working {
+		gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>;
+		linux,default-trigger = "mmc2";
+	};
+
+};
+
+/*
+ * Following section enables the sdio bus on sdmmc_ext controller
+ */
+&sdio {
+	/delete-property/ mmc-pwrseq;
+	status = "disabled";
+};
+
+&sdio_ext {
+	rockchip,default-sample-phase = <112>;
+	sd-uhs-sdr50;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	status = "okay";
+};
+
+&sdmmc_ext {
+	status = "disabled";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-wlan-ap6330.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-wlan-ap6330.dtso
new file mode 100644
index 000000000000..9bc02a2173e4
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-wlan-ap6330.dtso
@@ -0,0 +1,106 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+
+	fragment@0 {
+		target = <&sdio>;
+		__overlay__ {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			brcmf_sdio: wifi@1 {
+				reg = <1>;
+				compatible = "brcm,bcm4329-fmac";
+				//brcm,drive-strength = <2>;
+				interrupt-parent = <&gpio1>;
+				interrupt-names = "host_wake";
+				interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&sdio_host_wake>;
+			};
+
+		};
+	};
+
+	fragment@1 {
+		target = <&sdio_ext>;
+		__overlay__ {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			brcmf_ext: wifi@1 {
+				reg = <1>;
+				compatible = "brcm,bcm4329-fmac";
+				//brcm,drive-strength = <2>;
+				interrupt-parent = <&gpio3>;
+				interrupt-names = "host_wake";
+				interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&sdio_host_wake_ext>;
+			};
+
+		};
+	};
+
+	fragment@2 {
+		target = <&uart0>;
+		__overlay__ {
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+
+			bluetooth {
+				compatible = "brcm,bcm4330-bt";
+				max-speed = <4000000>;
+				shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+				device-wakeup-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
+				//host-wakeup-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+				vbat-supply = <&vcc_io>;
+				vddio-supply = <&vcc_18>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&bt_reg_on_h>, <&bt_host_wake_l>, <&bt_device_wake_l>;
+				/*
+				interrupt-names = "host-wakeup";
+				interrupt-parent = <&gpio1>;
+				interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+				*/
+				brcm,bt-pcm-int-params = [01 02 00 01 01];
+			};
+
+
+		};
+
+	};
+
+	fragment@3 {
+		target = <&pinctrl>;
+		__overlay__ {
+
+			bluetooth {
+
+
+				bt_reg_on_h: bt-enable {
+					rockchip,pins = <1 RK_PC5 0 &pcfg_pull_none>;
+				};
+
+				bt_device_wake_l: bt-device-wake {
+					rockchip,pins = <1 RK_PC7 0 &pcfg_pull_none>;
+				};
+
+				bt_host_wake_l: bt-host-wake {
+					rockchip,pins = <1 RK_PD2 0 &pcfg_pull_none>;
+				};
+
+			};
+
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-wlan-ap6334.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-wlan-ap6334.dtso
new file mode 100644
index 000000000000..b7befaaeb4c8
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-wlan-ap6334.dtso
@@ -0,0 +1,117 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+
+	fragment@0 {
+		target = <&sdio>;
+		__overlay__ {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+			sd-uhs-sdr104;
+			//sd-uhs-ddr50;
+
+			brcmf_sdio: wifi@1 {
+				reg = <1>;
+				compatible = "brcm,bcm4329-fmac";
+				//brcm,drive-strength = <4>;
+				interrupt-parent = <&gpio1>;
+				interrupt-names = "host_wake";
+				interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&sdio_host_wake>;
+			};
+
+		};
+	};
+
+	fragment@1 {
+		target = <&sdio_ext>;
+		__overlay__ {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+			sd-uhs-sdr104;
+			//sd-uhs-ddr50;
+
+			brcmf_ext: wifi@1 {
+				reg = <1>;
+				compatible = "brcm,bcm4329-fmac";
+				//brcm,drive-strength = <8>;
+				interrupt-parent = <&gpio3>;
+				interrupt-names = "host_wake";
+				interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&sdio_host_wake_ext>;
+			};
+
+		};
+	};
+
+	fragment@2 {
+		target = <&uart0>;
+		__overlay__ {
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+
+			bluetooth {
+				compatible = "brcm,bcm4334b0-bt", "brcm,bcm4330-bt";
+				max-speed = <4000000>;
+				shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+				device-wakeup-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
+				//host-wakeup-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+				vbat-supply = <&vcc_io>;
+				vddio-supply = <&vcc_18>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&bt_reg_on_h>, <&bt_host_wake_l>, <&bt_device_wake_l>;
+				/*
+				interrupt-names = "host-wakeup";
+				interrupt-parent = <&gpio1>;
+				interrupts = <RK_PD2 IRQ_TYPE_NONE>;
+				*/
+				brcm,bt-pcm-int-params = [01 02 00 01 01];
+			};
+
+		};
+
+	};
+
+	fragment@3 {
+		target = <&pinctrl>;
+		__overlay__ {
+
+			bluetooth {
+
+
+				bt_reg_on_h: bt-enable {
+					rockchip,pins = <1 RK_PC5 0 &pcfg_pull_down>;
+				};
+
+				bt_device_wake_l: bt-device-wake {
+					rockchip,pins = <1 RK_PC7 0 &pcfg_pull_none>;
+				};
+
+				bt_host_wake_l: bt-host-wake {
+					rockchip,pins = <1 RK_PD2 0 &pcfg_pull_none>;
+				};
+
+			};
+
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-wlan-ext.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-wlan-ext.dtso
new file mode 100644
index 000000000000..bf8a289d6b40
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3318-box-wlan-ext.dtso
@@ -0,0 +1,33 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+
+	fragment@0 {
+		target = <&sdio>;
+		__overlay__ {
+			mmc-pwrseq = <>;
+			status = "disabled";
+		};
+	};
+
+	fragment@1 {
+		target = <&sdio_ext>;
+		__overlay__ {
+			mmc-pwrseq = <&sdio_pwrseq>;
+			status = "okay";
+		};
+	};
+
+	fragment@2 {
+		target = <&sdmmc_ext>;
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-i2c0.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-i2c0.dtso
new file mode 100644
index 000000000000..af2d61ecd648
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-i2c0.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+	compatible = "rockchip,rk3328";
+
+	fragment@0 {
+		target-path = "/i2c@ff150000";
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-i2s1-pcm5102.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-i2s1-pcm5102.dtso
new file mode 100644
index 000000000000..5153440c0332
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-i2s1-pcm5102.dtso
@@ -0,0 +1,104 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/*
+ * Device tree overlay to disabled internal analog codec for
+ * rk3328 boards and enable external i2s, binding it to a
+ * pcm5102-based DAC.
+ * Tested on rock-pi E, but should be suitable for other
+ * similar boards
+ */
+
+&{/} {
+
+	pcm5102: pcm510x {
+		#sound-dai-cells = <0>;
+		compatible = "ti,pcm5102a";
+		pcm510x,format = "i2s";
+		status = "okay";
+	};
+
+	i2s_sound: i2s-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "I2S";
+		status = "okay";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&pcm5102>;
+		};
+	};
+
+};
+
+&analog_sound {
+	status = "disabled";
+};
+
+&codec {
+	status = "disabled";
+};
+
+&i2s1_mclk {
+	rockchip,pins = <2 RK_PB7 1 &pcfg_pull_down>;
+};
+
+&i2s1_sclk {
+	rockchip,pins = <2 RK_PC2 1 &pcfg_pull_down>;
+};
+
+&i2s1_lrckrx {
+	rockchip,pins = <2 RK_PC0 1 &pcfg_pull_up>;
+};
+
+&i2s1_lrcktx {
+	rockchip,pins = <2 RK_PC1 1 &pcfg_pull_up>;
+};
+
+&i2s1_sdi {
+	rockchip,pins = <2 RK_PC3 1 &pcfg_pull_up>;
+};
+
+&i2s1_sdo {
+	rockchip,pins = <2 RK_PC7 1 &pcfg_pull_up>;
+};
+
+&i2s1_sdio1 {
+	rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up>;
+};
+
+&i2s1_sdio2 {
+	rockchip,pins = <2 RK_PC5 1 &pcfg_pull_up>;
+};
+
+&i2s1_sdio3 {
+	rockchip,pins = <2 RK_PC6 1 &pcfg_pull_up>;
+};
+
+&i2s1_sleep {
+	rockchip,pins =
+	<2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
+	<2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
+	<2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
+	<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
+	<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
+	<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
+	<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
+	<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
+	<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
+};
+
+&i2s1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1_mclk>, <&i2s1_sclk>, <&i2s1_lrckrx>, <&i2s1_lrcktx>, <&i2s1_sdi>, <&i2s1_sdo>, <&i2s1_sdio1>, <&i2s1_sdio2>;
+	rockchip,playback-channels = <8>;
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-opp-1.4ghz.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-opp-1.4ghz.dtso
new file mode 100644
index 000000000000..5cc054074539
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-opp-1.4ghz.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+/ {
+    compatible = "rockchip,rk3328";
+    fragment@0 {
+        target-path = "/opp-table-0";
+        __overlay__ {
+		opp-1392000000 {
+			opp-hz = /bits/ 64 <1392000000>;
+			opp-microvolt = <1400000>;
+			clock-latency-ns = <40000>;
+		};
+        };
+    };
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-opp-1.5ghz.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-opp-1.5ghz.dtso
new file mode 100644
index 000000000000..497de74ee50b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-opp-1.5ghz.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+/ {
+    compatible = "rockchip,rk3328";
+    fragment@0 {
+        target-path = "/opp-table-0";
+        __overlay__ {
+		opp-1512000000 {
+			opp-hz = /bits/ 64 <1512000000>;
+			opp-microvolt = <1450000>;
+			clock-latency-ns = <40000>;
+		};
+        };
+    };
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-spi-spidev.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-spi-spidev.dtso
new file mode 100644
index 000000000000..9cc0238296de
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-spi-spidev.dtso
@@ -0,0 +1,33 @@
+/dts-v1/;
+
+/ {
+	compatible = "rockchip,rk3328";
+
+	fragment@0 {
+		target-path = "/aliases";
+
+		__overlay__ {
+			status = "okay";
+			spi0 = "/spi@ff190000";
+		};
+	};
+
+	fragment@1 {
+		target = <0xffffffff>;
+
+		__overlay__ {
+			status = "okay";
+
+			spidev {
+				compatible = "armbian,spi-dev";
+				status = "okay";
+				reg = <0x00>;
+				spi-max-frequency = <0x989680>;
+			};
+		};
+	};
+
+	__fixups__ {
+		spi0 = "/fragment@1:target:0";
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-uart1.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-uart1.dtso
new file mode 100644
index 000000000000..9ff6a0018ad2
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3328-uart1.dtso
@@ -0,0 +1,17 @@
+/dts-v1/;
+
+/ {
+	compatible = "rockchip,rk3328";
+
+	fragment@1 {
+		target = <0xffffffff>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	__fixups__ {
+		uart1 = "/fragment@1:target:0";
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-dwc3-0-host.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-dwc3-0-host.dtso
new file mode 100644
index 000000000000..be2f4a2736af
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-dwc3-0-host.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3399";
+
+	fragment@0 {
+		target = <&usbdrd_dwc3_0>;
+		__overlay__ {
+			dr_mode = "host";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-i2c7.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-i2c7.dtso
new file mode 100644
index 000000000000..f8c601550588
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-i2c7.dtso
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+    compatible = "rockchip,rk3399";
+    fragment@0 {
+        target-path = "/i2c@ff160000";
+        __overlay__ {
+            status = "okay";
+        };
+    };
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-i2c8.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-i2c8.dtso
new file mode 100644
index 000000000000..54bc8449eafd
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-i2c8.dtso
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+    compatible = "rockchip,rk3399";
+    fragment@0 {
+        target-path = "/i2c@ff3e0000";
+        __overlay__ {
+            status = "okay";
+        };
+    };
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-opp-2ghz.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-opp-2ghz.dtso
new file mode 100644
index 000000000000..5123c8498c56
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-opp-2ghz.dtso
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+/ {
+    compatible = "rockchip,rk3399";
+    fragment@0 {
+        target-path = "/opp-table-0";
+        __overlay__ {
+		opp06 {
+			opp-hz = /bits/ 64 <1512000000>;
+			opp-microvolt = <1200000>;
+		};
+        };
+    };
+
+    fragment@1 {
+        target-path = "/opp-table-1";
+        __overlay__ {
+		opp08 {
+			opp-hz = /bits/ 64 <2016000000>;
+			opp-microvolt = <1300000>;
+		};
+        };
+    };
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-pcie-gen2.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-pcie-gen2.dtso
new file mode 100644
index 000000000000..e8a51dca8f67
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-pcie-gen2.dtso
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+    compatible = "rockchip,rk3399";
+    fragment@0 {
+        target = <&pcie0>;
+        __overlay__ {
+            max-link-speed = <2>;
+        };
+    };
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-spi-jedec-nor.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-spi-jedec-nor.dtso
new file mode 100644
index 000000000000..c4b1f36f9b09
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-spi-jedec-nor.dtso
@@ -0,0 +1,72 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3399";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			spi0 = "/spi@ff1c0000";
+			spi1 = "/spi@ff1d0000";
+			spi2 = "/spi@ff1e0000";
+			spi3 = "/spi@ff1f0000";
+		};
+	};
+
+	fragment@1 {
+		target = <&spi0>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spiflash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <10000000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&spi1>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spiflash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <10000000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&spi2>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spiflash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <10000000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	fragment@4 {
+		target = <&spi3>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spiflash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <10000000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-spi-spidev.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-spi-spidev.dtso
new file mode 100644
index 000000000000..53f074096308
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-spi-spidev.dtso
@@ -0,0 +1,72 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3399";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			spi0 = "/spi@ff1c0000";
+			spi1 = "/spi@ff1d0000";
+			spi2 = "/spi@ff1e0000";
+			spi3 = "/spi@ff1f0000";
+		};
+	};
+
+	fragment@1 {
+		target = <&spi0>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev {
+				compatible = "armbian,spi-dev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <10000000>;
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&spi1>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev {
+				compatible = "armbian,spi-dev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <10000000>;
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&spi2>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev {
+				compatible = "armbian,spi-dev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <10000000>;
+			};
+		};
+	};
+
+	fragment@4 {
+		target = <&spi3>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev {
+				compatible = "armbian,spi-dev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <10000000>;
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-uart4.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-uart4.dtso
new file mode 100644
index 000000000000..305304ebcbf1
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-uart4.dtso
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3399";
+
+	fragment@0 {
+		target = <&spi1>;
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+	fragment@1 {
+		target = <&uart4>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-w1-gpio.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-w1-gpio.dtso
new file mode 100644
index 000000000000..bfbc16adcc9d
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3399-w1-gpio.dtso
@@ -0,0 +1,20 @@
+// Definitions for w1-gpio module (without external pullup)
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "rockchip,rk3399";
+
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+
+			w1: onewire@0 {
+				compatible = "w1-gpio";
+				pinctrl-names = "default";
+				gpios = <&gpio1 4 0 0xae>; // GPIO1_A4
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3566-sata2.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3566-sata2.dtso
new file mode 100644
index 000000000000..0505079ec09c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3566-sata2.dtso
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&pcie2x1>;
+
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+	fragment@1 {
+		target = <&sata2>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-i2c0.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-i2c0.dtso
new file mode 100644
index 000000000000..a6942df06650
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-i2c0.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		// i2c3 aliased with i2c0.
+		// This activates i2c3 but it will be named as i2c0 on the userspace.
+		target = <&i2c3>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-i2c1.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-i2c1.dtso
new file mode 100644
index 000000000000..344161c2d6db
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-i2c1.dtso
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&i2c1>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-pwm1.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-pwm1.dtso
new file mode 100644
index 000000000000..0b78ad96ba8b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-pwm1.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		// pwmchip0, pwm@fdd70010
+		target = <&pwm1>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-pwm2.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-pwm2.dtso
new file mode 100644
index 000000000000..c7f1898e5903
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-pwm2.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		// pwmchip1, pwm@fdd70020
+		target = <&pwm2>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-pwm9.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-pwm9.dtso
new file mode 100644
index 000000000000..7f52929e787c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-pwm9.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		// pwmchip3, pwm@fe6f0010
+		target = <&pwm9>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-spi-spidev.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-spi-spidev.dtso
new file mode 100644
index 000000000000..f25e855704ec
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-spi-spidev.dtso
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&spi0>;
+
+		__overlay__ {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			spidev: spidev@0 {
+				status = "okay";
+				compatible = "armbian,spi-dev";
+				reg = <0>;
+				/* spi default max clock 100Mhz */
+				spi-max-frequency = <100000000>;
+			};
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso
new file mode 100644
index 000000000000..fb855965f9ae
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		// uart1 aliased with serial0.
+		target = <&uart1>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "not_use_it", "default";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-uart0.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-uart0.dtso
new file mode 100644
index 000000000000..e57ba5499820
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-uart0.dtso
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		// uart1 aliased with serial0.
+		target = <&uart1>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-uart1.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-uart1.dtso
new file mode 100644
index 000000000000..cdc75c4f2873
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-hk-uart1.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		// uart0 aliased with serial1.
+		target = <&uart0>;
+
+		__overlay__ {
+			status = "okay";
+
+			dma-names = "tx", "rx";
+		};
+	};
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso
new file mode 100644
index 000000000000..b768f63f132a
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso
@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+
+&{/gpio-leds/led-lan} {
+        linux,default-trigger = "r8169-1-100:00:link";
+};
+
+&{/gpio-leds/led-wan} {
+        linux,default-trigger = "r8169-2-100:00:link";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso
new file mode 100644
index 000000000000..68bb3584845e
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+
+&{/gpio-leds/led-wan} {
+        linux,default-trigger = "stmmac-0:01:link";
+};
+
+&{/gpio-leds/led-lan1} {
+        linux,default-trigger = "r8169-0-100:00:link";
+};
+
+&{/gpio-leds/led-lan2} {
+        linux,default-trigger = "r8169-1-100:00:link";
+};
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rockpi4cplus-usb-host.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rockpi4cplus-usb-host.dtso
new file mode 100644
index 000000000000..654ae888f5c4
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rockpi4cplus-usb-host.dtso
@@ -0,0 +1,16 @@
+//For RockPI 4C+:  Change the top USB3.0 port to host mode
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "radxa,rockpi4c-plus", "radxa,rockpi4", "rockchip,rk3399";
+
+	fragment@0 {
+		target = <&usbdrd_dwc3_0>;
+		__overlay__ {
+			dr_mode = "host";
+		};
+	};
+};
+
diff --git a/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rockpro64-lcd.dtso b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rockpro64-lcd.dtso
new file mode 100644
index 000000000000..c9ce8f8b565d
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/overlay/rockchip-rockpro64-lcd.dtso
@@ -0,0 +1,58 @@
+//For RockPro64 7″ LCD TOUCH SCREEN PANEL
+
+/dts-v1/;
+/plugin/;
+
+/ {
+  compatible = "rockchip,rk3399";
+	
+  fragment@0 {
+    target=<&backlight>;
+    __overlay__ {
+      status = "okay";
+    };
+  };
+  
+  fragment@1 {
+    target=<&touch>;
+    __overlay__ {
+      status = "okay";
+    };
+  };
+  
+  fragment@2 {
+    target=<&mipi_dsi>;
+    __overlay__ {
+      status = "okay";
+    };
+  }; 
+  
+  fragment@3 {
+    target=<&vopl>;
+    __overlay__ {
+      status = "okay";
+    };
+  };
+
+  fragment@4 {
+    target=<&vopl_mmu>;
+    __overlay__ {
+      status = "okay";
+    };
+  };
+  
+  fragment@5 {
+    target=<&vopb>;
+    __overlay__ {
+      status = "okay";
+    };
+  };
+
+  fragment@6 {
+    target=<&vopb_mmu>;
+    __overlay__ {
+      status = "okay";
+    };
+  };
+};
+
diff --git a/patch/kernel/archive/rockchip64-6.10/pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch b/patch/kernel/archive/rockchip64-6.10/pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch
new file mode 100644
index 000000000000..bc751233a684
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch
@@ -0,0 +1,13 @@
+diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
+index 3f56991f5b89..f6da91941fbd 100644
+--- a/drivers/pinctrl/pinctrl-rockchip.c
++++ b/drivers/pinctrl/pinctrl-rockchip.c
+@@ -3813,7 +3813,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
+ 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
+ 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
+ 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
+-			     0,
++			     IOMUX_WIDTH_2BIT,
+ 			     IOMUX_WIDTH_3BIT,
+ 			     0),
+ 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
diff --git a/patch/kernel/archive/rockchip64-6.10/regulator-add-fan53200-driver.patch b/patch/kernel/archive/rockchip64-6.10/regulator-add-fan53200-driver.patch
new file mode 100644
index 000000000000..73d860e5c31c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/regulator-add-fan53200-driver.patch
@@ -0,0 +1,597 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Rock Shen <rock_shen@asus.com>
+Date: Tue, 27 Apr 2021 11:13:25 +0800
+Subject: regulator: add fan53200 regulator driver for Tinkerboard-2
+
+1. Add fan53200 regulator support for vdd_cpu_b & vdd_gpu
+2. By Tinker2 HW design, Vsel gpio pin polarity was reversed, switch
+   sleep_reg & vol_reg at fan53200_voltages_setup_fairchild
+3. Use vsel0 as suspend source, vsel1 as normal source
+
+- rpardini: hammered .probe and probe_type = PROBE_PREFER_ASYNCHRONOUS to
+  work on 6.6.y, after https://lore.kernel.org/all/20230505220218.1239542-1-u.kleine-koenig@pengutronix.de/
+
+Signed-off-by: Rock Shen <rock_shen@asus.com>
+Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
+---
+ arch/arm64/configs/defconfig |   1 +
+ drivers/regulator/Kconfig    |  11 +
+ drivers/regulator/Makefile   |   1 +
+ drivers/regulator/fan53200.c | 520 ++++++++++
+ 4 files changed, 533 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index a789119e6483..3337a1e1eb66 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -731,6 +731,7 @@ CONFIG_REGULATOR_BD718XX=y
+ CONFIG_REGULATOR_BD9571MWV=y
+ CONFIG_REGULATOR_CROS_EC=y
+ CONFIG_REGULATOR_FAN53555=y
++CONFIG_REGULATOR_FAN53200=y
+ CONFIG_REGULATOR_GPIO=y
+ CONFIG_REGULATOR_HI6421V530=y
+ CONFIG_REGULATOR_HI655X=y
+diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
+index 965d4f0c18a6..62c8aad24b38 100644
+--- a/drivers/regulator/Kconfig
++++ b/drivers/regulator/Kconfig
+@@ -393,6 +393,17 @@ config REGULATOR_FAN53880
+ 	  (PMIC), it is controlled by I2C and provides one BUCK, one BOOST
+ 	  and four LDO outputs.
+ 
++config REGULATOR_FAN53200
++	tristate "Fairchild FAN53200 Regulator"
++	depends on I2C
++	select REGMAP_I2C
++	help
++	  This driver supports Fairchild FAN53200 Digitally Programmable
++	  TinyBuck Regulator. The FAN53200 is a step-down switching voltage
++	  regulator that delivers a digitally programmable output from an
++	  input voltage supply of 2.5V to 5.5V. The output voltage is
++	  programmed through an I2C interface.
++
+ config REGULATOR_GPIO
+ 	tristate "GPIO regulator support"
+ 	depends on GPIOLIB || COMPILE_TEST
+diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
+index 23074714a81a..484fcc264cc7 100644
+--- a/drivers/regulator/Makefile
++++ b/drivers/regulator/Makefile
+@@ -47,6 +47,7 @@ obj-$(CONFIG_REGULATOR_DBX500_PRCMU) += dbx500-prcmu.o
+ obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
+ obj-$(CONFIG_REGULATOR_FAN53555) += fan53555.o
+ obj-$(CONFIG_REGULATOR_FAN53880) += fan53880.o
++obj-$(CONFIG_REGULATOR_FAN53555) += fan53200.o
+ obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o
+ obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o
+ obj-$(CONFIG_REGULATOR_HI6421V530) += hi6421v530-regulator.o
+diff --git a/drivers/regulator/fan53200.c b/drivers/regulator/fan53200.c
+new file mode 100644
+index 000000000000..f7e33e67f073
+--- /dev/null
++++ b/drivers/regulator/fan53200.c
+@@ -0,0 +1,520 @@
++/*
++ * FAN53200 Fairchild Digitally Programmable TinyBuck Regulator Driver.
++ *
++ * Supported Part Numbers:
++ * FAN53200UC35X/44X
++ *
++ * Copyright (c) 2021 ASUSTeK Computer Inc.
++ * Rock Shen <rock_shen@asus.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#include <linux/module.h>
++#include <linux/param.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/machine.h>
++#include <linux/regulator/of_regulator.h>
++#include <linux/of_device.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/regmap.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++
++/* Voltage setting */
++#define FAN53200_VSEL0		0x00
++#define FAN53200_VSEL1		0x01
++
++/* Control register */
++#define FAN53200_CONTROL	0x02
++/* IC Type */
++#define FAN53200_ID1		0x03
++/* IC mask version */
++#define FAN53200_ID2		0x04
++
++/* VSEL bit definitions */
++#define VSEL_BUCK_EN	(1 << 7)
++#define VSEL_MODE		(1 << 6)
++#define VSEL_NSEL_MASK	0x3F
++/* Chip ID and Verison */
++#define DIE_ID		0x0F	/* ID1 */
++#define DIE_REV		0x0F	/* ID2 */
++/* Control bit definitions */
++#define CTL_OUTPUT_DISCHG	(1 << 7)
++#define CTL_SLEW_MASK		(0x7 << 4)
++#define CTL_SLEW_SHIFT		4
++#define CTL_RESET			(1 << 2)
++
++#define TCS_VSEL_NSEL_MASK	0x7f
++#define TCS_VSEL0_MODE		(1 << 7)
++#define TCS_VSEL1_MODE		(1 << 6)
++
++#define TCS_SLEW_SHIFT		3
++#define TCS_SLEW_MASK		(0x3 < 3)
++
++#define FAN53200_NVOLTAGES	64	/* Numbers of voltages */
++
++enum fan53200_vendor {
++	FAN53200_VENDOR_FAIRCHILD = 0,
++};
++
++/* VSEL ID */
++enum {
++	FAN53200_VSEL_ID_0 = 0,
++	FAN53200_VSEL_ID_1,
++};
++
++enum {
++	FAN53200_CHIP_ID_00 = 0x8001,
++	FAN53200_CHIP_ID_01 = 0x8101,
++};
++
++struct fan53200_platform_data {
++	struct regulator_init_data *regulator;
++	unsigned int slew_rate;
++	/* Sleep VSEL ID */
++	unsigned int sleep_vsel_id;
++	struct gpio_desc *vsel_gpio;
++};
++
++struct fan53200_device_info {
++	enum fan53200_vendor vendor;
++	struct regmap *regmap;
++	struct device *dev;
++	struct regulator_desc desc;
++	struct regulator_dev *rdev;
++	struct regulator_init_data *regulator;
++	/* IC Type and Rev */
++	int chip_id;
++	int chip_rev;
++	/* Voltage setting register */
++	unsigned int vol_reg;
++	unsigned int sleep_reg;
++	unsigned int mode_reg;
++	unsigned int vol_mask;
++	unsigned int mode_mask;
++	unsigned int slew_reg;
++	unsigned int slew_mask;
++	unsigned int slew_shift;
++	/* Voltage range and step(linear) */
++	unsigned int vsel_min;
++	unsigned int vsel_step;
++	unsigned int n_voltages;
++	/* Voltage slew rate limiting */
++	unsigned int slew_rate;
++	/* Sleep voltage cache */
++	unsigned int sleep_vol_cache;
++	struct gpio_desc *vsel_gpio;
++	unsigned int sleep_vsel_id;
++};
++
++static unsigned int fan53200_map_mode(unsigned int mode)
++{
++	return mode == REGULATOR_MODE_FAST ?
++		REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL;
++}
++
++static int fan53200_set_suspend_voltage(struct regulator_dev *rdev, int uV)
++{
++	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
++	int ret;
++
++	if (di->sleep_vol_cache == uV)
++		return 0;
++	ret = regulator_map_voltage_linear(rdev, uV, uV);
++	if (ret < 0)
++		return ret;
++	ret = regmap_update_bits(di->regmap, di->sleep_reg,
++				 di->vol_mask, ret);
++	if (ret < 0)
++		return ret;
++	/* Cache the sleep voltage setting.
++	 * Might not be the real voltage which is rounded */
++	di->sleep_vol_cache = uV;
++
++	return 0;
++}
++
++static int fan53200_set_suspend_enable(struct regulator_dev *rdev)
++{
++	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
++
++	return regmap_update_bits(di->regmap, di->sleep_reg,
++				  VSEL_BUCK_EN, VSEL_BUCK_EN);
++}
++
++static int fan53200_set_suspend_disable(struct regulator_dev *rdev)
++{
++	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
++
++	return regmap_update_bits(di->regmap, di->sleep_reg,
++				  VSEL_BUCK_EN, 0);
++}
++
++static int fan53200_set_enable(struct regulator_dev *rdev)
++{
++	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
++
++	if (di->vsel_gpio) {
++		gpiod_set_raw_value(di->vsel_gpio, !di->sleep_vsel_id);
++		return 0;
++	}
++
++	return regmap_update_bits(di->regmap, di->vol_reg,
++				  VSEL_BUCK_EN, VSEL_BUCK_EN);
++}
++
++static int fan53200_set_disable(struct regulator_dev *rdev)
++{
++	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
++
++	if (di->vsel_gpio) {
++		gpiod_set_raw_value(di->vsel_gpio, di->sleep_vsel_id);
++		return 0;
++	}
++
++	return regmap_update_bits(di->regmap, di->vol_reg,
++				  VSEL_BUCK_EN, 0);
++}
++
++static int fan53200_is_enabled(struct regulator_dev *rdev)
++{
++	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
++	unsigned int val;
++	int ret = 0;
++
++	if (di->vsel_gpio) {
++		if (di->sleep_vsel_id)
++			return !gpiod_get_raw_value(di->vsel_gpio);
++		else
++			return gpiod_get_raw_value(di->vsel_gpio);
++	}
++
++	ret = regmap_read(di->regmap, di->vol_reg, &val);
++	if (ret < 0)
++		return ret;
++	if (val & VSEL_BUCK_EN)
++		return 1;
++	else
++		return 0;
++}
++
++static int fan53200_set_mode(struct regulator_dev *rdev, unsigned int mode)
++{
++	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
++
++	switch (mode) {
++	case REGULATOR_MODE_FAST:
++		regmap_update_bits(di->regmap, di->mode_reg,
++				   di->mode_mask, di->mode_mask);
++		break;
++	case REGULATOR_MODE_NORMAL:
++		regmap_update_bits(di->regmap, di->mode_reg, di->mode_mask, 0);
++		break;
++	default:
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static unsigned int fan53200_get_mode(struct regulator_dev *rdev)
++{
++	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
++	unsigned int val;
++	int ret = 0;
++
++	ret = regmap_read(di->regmap, di->mode_reg, &val);
++	if (ret < 0)
++		return ret;
++	if (val & di->mode_mask)
++		return REGULATOR_MODE_FAST;
++	else
++		return REGULATOR_MODE_NORMAL;
++}
++
++static const int slew_rates[] = {
++	80000,
++	40000,
++	20000,
++	10000,
++	5000,
++	2500,
++	1250,
++	625,
++};
++
++static int fan53200_set_ramp(struct regulator_dev *rdev, int ramp)
++{
++	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
++	int regval = -1, i;
++
++	for (i = 0; i < ARRAY_SIZE(slew_rates); i++) {
++		if (ramp <= slew_rates[i])
++			regval = i;
++		else
++			break;
++	}
++
++	if (regval < 0) {
++		dev_err(di->dev, "unsupported ramp value %d\n", ramp);
++		return -EINVAL;
++	}
++
++	return regmap_update_bits(di->regmap, di->slew_reg,
++				  di->slew_mask, regval << di->slew_shift);
++}
++
++static struct regulator_ops fan53200_regulator_ops = {
++	.set_voltage_sel = regulator_set_voltage_sel_regmap,
++	.get_voltage_sel = regulator_get_voltage_sel_regmap,
++	.set_voltage_time_sel = regulator_set_voltage_time_sel,
++	.map_voltage = regulator_map_voltage_linear,
++	.list_voltage = regulator_list_voltage_linear,
++	.set_suspend_voltage = fan53200_set_suspend_voltage,
++	.enable = fan53200_set_enable,
++	.disable = fan53200_set_disable,
++	.is_enabled = fan53200_is_enabled,
++	.set_mode = fan53200_set_mode,
++	.get_mode = fan53200_get_mode,
++	.set_ramp_delay = fan53200_set_ramp,
++	.set_suspend_enable = fan53200_set_suspend_enable,
++	.set_suspend_disable = fan53200_set_suspend_disable,
++};
++
++static int fan53200_voltages_setup_fairchild(struct fan53200_device_info *di)
++{
++
++	if (di->sleep_vsel_id) {
++		di->sleep_reg = FAN53200_VSEL0;
++		di->vol_reg = FAN53200_VSEL1;
++	} else {
++		di->sleep_reg = FAN53200_VSEL1;
++		di->vol_reg = FAN53200_VSEL0;
++	}
++
++	/* Init voltage range and step */
++	di->vsel_min = 600000;
++	di->vsel_step = 12500;
++	di->vol_mask = VSEL_NSEL_MASK;
++	di->mode_reg = di->vol_reg;
++	di->mode_mask = VSEL_MODE;
++	di->slew_reg = FAN53200_CONTROL;
++	di->slew_mask = CTL_SLEW_MASK;
++	di->slew_shift = CTL_SLEW_SHIFT;
++	di->n_voltages = FAN53200_NVOLTAGES;
++
++	return 0;
++}
++
++/* For 00,01,03,05 options:
++ * VOUT = 0.60V + NSELx * 10mV, from 0.60 to 1.23V.
++ * For 04 option:
++ * VOUT = 0.603V + NSELx * 12.826mV, from 0.603 to 1.411V.
++ * */
++static int fan53200_device_setup(struct fan53200_device_info *di,
++				struct fan53200_platform_data *pdata)
++{
++	int ret = 0;
++
++	ret = fan53200_voltages_setup_fairchild(di);
++
++	return ret;
++}
++
++static int fan53200_regulator_register(struct fan53200_device_info *di,
++			struct regulator_config *config)
++{
++	struct regulator_desc *rdesc = &di->desc;
++
++	rdesc->name = "fan53200-reg";
++	rdesc->supply_name = "vin";
++	rdesc->ops = &fan53200_regulator_ops;
++	rdesc->type = REGULATOR_VOLTAGE;
++	rdesc->n_voltages = di->n_voltages;
++	rdesc->enable_reg = di->vol_reg;
++	rdesc->enable_mask = VSEL_BUCK_EN;
++	rdesc->min_uV = di->vsel_min;
++	rdesc->uV_step = di->vsel_step;
++	rdesc->vsel_reg = di->vol_reg;
++	rdesc->vsel_mask = di->vol_mask;
++	rdesc->owner = THIS_MODULE;
++	rdesc->enable_time = 400;
++
++	di->rdev = devm_regulator_register(di->dev, &di->desc, config);
++	return PTR_ERR_OR_ZERO(di->rdev);
++}
++
++static const struct regmap_config fan53200_regmap_config = {
++	.reg_bits = 8,
++	.val_bits = 8,
++};
++
++static struct fan53200_platform_data *fan53200_parse_dt(struct device *dev,
++					      struct device_node *np,
++					      const struct regulator_desc *desc)
++{
++	struct fan53200_platform_data *pdata;
++	int ret, flag;
++	u32 tmp;
++
++	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
++	if (!pdata)
++		return NULL;
++
++	pdata->regulator = of_get_regulator_init_data(dev, np, desc);
++	pdata->regulator->constraints.initial_state = PM_SUSPEND_MEM;
++
++	ret = of_property_read_u32(np, "fcs,suspend-voltage-selector",
++				   &tmp);
++	if (!ret)
++		pdata->sleep_vsel_id = tmp;
++
++	if (pdata->sleep_vsel_id)
++		flag = GPIOD_OUT_LOW;
++	else
++		flag = GPIOD_OUT_HIGH;
++
++	pdata->vsel_gpio =
++		devm_gpiod_get_index_optional(dev, "vsel", 0,
++					      flag);
++	if (IS_ERR(pdata->vsel_gpio)) {
++		ret = PTR_ERR(pdata->vsel_gpio);
++		dev_err(dev, "failed to get vesl gpio (%d)\n", ret);
++	}
++
++	return pdata;
++}
++
++static const struct of_device_id fan53200_dt_ids[] = {
++	{
++		.compatible = "fcs,fan53200",
++		.data = (void *)FAN53200_VENDOR_FAIRCHILD,
++	},
++	{ }
++};
++MODULE_DEVICE_TABLE(of, fan53200_dt_ids);
++
++static int fan53200_regulator_probe(struct i2c_client *client)
++{
++	const struct i2c_device_id *id = i2c_client_get_device_id(client);
++	struct device_node *np = client->dev.of_node;
++	struct fan53200_device_info *di;
++	struct fan53200_platform_data *pdata;
++	struct regulator_config config = { };
++	unsigned int val;
++	int ret;
++
++	di = devm_kzalloc(&client->dev, sizeof(struct fan53200_device_info),
++					GFP_KERNEL);
++	if (!di)
++		return -ENOMEM;
++
++	di->desc.of_map_mode = fan53200_map_mode;
++
++	pdata = dev_get_platdata(&client->dev);
++	if (!pdata)
++		pdata = fan53200_parse_dt(&client->dev, np, &di->desc);
++
++	if (!pdata || !pdata->regulator) {
++		dev_err(&client->dev, "Platform data not found!\n");
++		return -ENODEV;
++	}
++
++	di->vsel_gpio = pdata->vsel_gpio;
++	di->sleep_vsel_id = pdata->sleep_vsel_id;
++
++	di->regulator = pdata->regulator;
++	if (client->dev.of_node) {
++		const struct of_device_id *match;
++
++		match = of_match_device(of_match_ptr(fan53200_dt_ids),
++					&client->dev);
++		if (!match)
++			return -ENODEV;
++
++		di->vendor = (unsigned long) match->data;
++	} else {
++		/* if no ramp constraint set, get the pdata ramp_delay */
++		if (!di->regulator->constraints.ramp_delay) {
++			int slew_idx = (pdata->slew_rate & 0x7)
++						? pdata->slew_rate : 0;
++
++			di->regulator->constraints.ramp_delay
++						= slew_rates[slew_idx];
++		}
++
++		di->vendor = id->driver_data;
++	}
++
++	di->regmap = devm_regmap_init_i2c(client, &fan53200_regmap_config);
++	if (IS_ERR(di->regmap)) {
++		dev_err(&client->dev, "Failed to allocate regmap!\n");
++		return PTR_ERR(di->regmap);
++	}
++	di->dev = &client->dev;
++	i2c_set_clientdata(client, di);
++	/* Get chip ID */
++	ret = regmap_read(di->regmap, FAN53200_ID1, &val);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed to get chip ID!\n");
++		return ret;
++	}
++	di->chip_id = val & DIE_ID;
++	/* Get chip revision */
++	ret = regmap_read(di->regmap, FAN53200_ID2, &val);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed to get chip Rev!\n");
++		return ret;
++	}
++	di->chip_rev = val & DIE_REV;
++	dev_info(&client->dev, "FAN53200 Option[%d] Rev[%d] Detected!\n",
++				di->chip_id, di->chip_rev);
++	/* Device init */
++	ret = fan53200_device_setup(di, pdata);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed to setup device!\n");
++		return ret;
++	}
++	/* Register regulator */
++	config.dev = di->dev;
++	config.init_data = di->regulator;
++	config.regmap = di->regmap;
++	config.driver_data = di;
++	config.of_node = np;
++
++	ret = fan53200_regulator_register(di, &config);
++	if (ret < 0)
++		dev_err(&client->dev, "Failed to register regulator!\n");
++	return ret;
++
++}
++
++static const struct i2c_device_id fan53200_id[] = {
++	{
++		.name = "fan53200",
++		.driver_data = FAN53200_VENDOR_FAIRCHILD
++	},
++	{ },
++};
++MODULE_DEVICE_TABLE(i2c, fan53200_id);
++
++static struct i2c_driver fan53200_regulator_driver = {
++	.driver = {
++		.name = "fan53200-regulator",
++		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
++		.of_match_table = of_match_ptr(fan53200_dt_ids),
++	},
++	.probe = fan53200_regulator_probe,
++	.id_table = fan53200_id,
++};
++
++module_i2c_driver(fan53200_regulator_driver);
++
++MODULE_AUTHOR("Rock Shen <rock_shen@asus.com>");
++MODULE_DESCRIPTION("FAN53200 regulator driver");
++MODULE_LICENSE("GPL v2");
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3308-0001-pinctrl-slew-mux.patch b/patch/kernel/archive/rockchip64-6.10/rk3308-0001-pinctrl-slew-mux.patch
new file mode 100644
index 000000000000..d7fda15627a6
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3308-0001-pinctrl-slew-mux.patch
@@ -0,0 +1,257 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: brentr <brent@mbari.org>
+Date: Thu, 13 Oct 2022 18:34:43 +0200
+Subject: [ARCHEOLOGY] Rockpis wifi fixes (#4008)
+
+> X-Git-Archeology: > recovered message: > * RockPI-S board has no video I/O
+> X-Git-Archeology: > recovered message: > * udev rule to fix MAC address of iface based on UUID
+> X-Git-Archeology: > recovered message: > Deals with WiFi chip lacking any EEPROM to store its unique Ethernet MAC address
+> X-Git-Archeology: > recovered message: > Generic mechanism -- could be utilized for other boards having similar issues
+> X-Git-Archeology: > recovered message: > * Handy Device Tree overlays for the RockPI S
+> X-Git-Archeology: > recovered message: > Use armbian-add-overlay to install these
+> X-Git-Archeology: > recovered message: > Reduce CPU voltage for the RK3308 B-S
+> X-Git-Archeology: > recovered message: > Option to overclock RK3308 B-S to 1.3Ghz
+> X-Git-Archeology: > recovered message: > Increase SDIO clock rate from 1Mhz to 10Mhz
+> X-Git-Archeology: > recovered message: > This increases WiFi throughput from 300K bytes/s to 2.4M bytes/s
+> X-Git-Archeology: > recovered message: > * corrected comment
+> X-Git-Archeology: > recovered message: > * No longer repeat standard opp's in this dts
+> X-Git-Archeology: > recovered message: > Require that the standard bs dts already be installed
+> X-Git-Archeology: > recovered message: > * User README for adding RockPI-S board variant specific dts overlays
+> X-Git-Archeology: > recovered message: > * "enabled" --> "okay"
+> X-Git-Archeology: > recovered message: > * added mention of sdnand.dts, fixed typo
+> X-Git-Archeology: > recovered message: > * added p2p0 to interfaces whose MAC address should be "fixed"
+> X-Git-Archeology: > recovered message: > * RK3308 CPU serial number in nvmem replaces UUID for derivation of fixed MAC addr
+> X-Git-Archeology: > recovered message: > Restored use of install utility
+> X-Git-Archeology: > recovered message: > * Use RK3308 specific CPU serial number
+> X-Git-Archeology: > recovered message: > rather than rootfs UUID
+> X-Git-Archeology: > recovered message: > * remove generic fixMACaddress
+> X-Git-Archeology: > recovered message: > * Install fixMACaddr file-by-file via install utility
+> X-Git-Archeology: > recovered message: > * Drive SDIO bus signals faster
+> X-Git-Archeology: > recovered message: > setting RK3308_SOC_CON0_VCCIO3 reduces signal rise/fall times to WiFi SDIO chip
+> X-Git-Archeology: > recovered message: > from 30ns to 5ns.
+> X-Git-Archeology: > recovered message: > This odd fix forward ported from legacy kernel.
+> X-Git-Archeology: > recovered message: > Allows Rock Pi-S WiFi to operate at full speed.
+> X-Git-Archeology: > recovered message: > * Set RK3308 I/O voltage domains before SDIO initializes
+> X-Git-Archeology: > recovered message: > This patch moves responibility form the io-domain to the pinctrl driver because
+> X-Git-Archeology: > recovered message: > the io-domain driver is probed after the SDIO devices are discovered.
+> X-Git-Archeology: > recovered message: > This was causing multiple SDIO I/O failures during boot.
+> X-Git-Archeology: > recovered message: > A new pinctrl property is added:
+> X-Git-Archeology: > recovered message: > io-1v8-domains
+> X-Git-Archeology: > recovered message: > is a u32 interpreted as a bit mask where each set bit corresponds to
+> X-Git-Archeology: > recovered message: > a 1.8V I/O domain (as opposed to the default of 3.3V for I/O)
+> X-Git-Archeology: > recovered message: > The mask is writted to the RK3308_SOC_CON0 GRF register
+> X-Git-Archeology: > recovered message: > (once) when the pinctrl driver starts
+> X-Git-Archeology: > recovered message: > The default mask is 0x10 where only I/O domain 4 runs at 1.8V
+> X-Git-Archeology: > recovered message: > This is necessary for the RockPI-S to run the SDIO clock at high (50Mhz) speed
+> X-Git-Archeology: > recovered message: > * align whitespace
+> X-Git-Archeology: > recovered message: > * factored rk3308bs overlays out up sdio speedup patch
+> X-Git-Archeology: > recovered message: > * factored dts for RK3308 iodomains and pinctrl patches out of speedup patch
+> X-Git-Archeology: > recovered message: > * remains of sdio speedup patch merely add iodomains support for rk3308
+> X-Git-Archeology: > recovered message: > * factored rockpis dts modification out from rk3308 io voltage domains
+> X-Git-Archeology: > recovered message: > replaced rk3308 support from iodomains with
+> X-Git-Archeology: > recovered message: > new io-voltage-domains property added to pinctrl
+> X-Git-Archeology: > recovered message: > io-voltage-domains specific to rk3308 for now, others SOCs may be added later.
+> X-Git-Archeology: > recovered message: > * add sequence numbering to names of rk3308 patches
+> X-Git-Archeology: > recovered message: > * corrected tab alignment
+> X-Git-Archeology: - Revision d3a3afe3850861ceaeb44f3631251c764a28cd43: https://github.com/armbian/build/commit/d3a3afe3850861ceaeb44f3631251c764a28cd43
+> X-Git-Archeology:   Date: Thu, 13 Oct 2022 18:34:43 +0200
+> X-Git-Archeology:   From: brentr <brent@mbari.org>
+> X-Git-Archeology:   Subject: Rockpis wifi fixes (#4008)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ drivers/pinctrl/pinconf-generic.c       |  1 +
+ drivers/pinctrl/pinctrl-rockchip.c      | 95 ++++++++++
+ drivers/pinctrl/pinctrl-rockchip.h      |  3 +
+ include/linux/pinctrl/pinconf-generic.h |  1 +
+ 4 files changed, 100 insertions(+)
+
+diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
+index 365c4b0ca465..bacc2987c55b 100644
+--- a/drivers/pinctrl/pinconf-generic.c
++++ b/drivers/pinctrl/pinconf-generic.c
+@@ -51,6 +51,7 @@ static const struct pin_config_item conf_items[] = {
+ 	PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
+ 	PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
+ 	PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true),
++	PCONFDUMP(PIN_CONFIG_MUX, "mux", NULL, true),
+ };
+ 
+ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
+diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
+index 45e416f68e74..94af47ad9667 100644
+--- a/drivers/pinctrl/pinctrl-rockchip.c
++++ b/drivers/pinctrl/pinctrl-rockchip.c
+@@ -2533,6 +2533,26 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
+ 	return ret;
+ }
+ 
++#define RK3308_SLEW_PINS_PER_REG	8
++#define RK3308_SLEW_BANK_STRIDE		16
++#define RK3308_SLEW_GRF_OFFSET		0x150
++
++static int rk3308_calc_slew_reg_and_bit(struct rockchip_pin_bank *bank,
++				    int pin_num, struct regmap **regmap,
++				    int *reg, u8 *bit)
++{
++	struct rockchip_pinctrl *info = bank->drvdata;
++
++	*regmap = info->regmap_base;
++	*reg = RK3308_SLEW_GRF_OFFSET;
++
++	*reg += bank->bank_num * RK3308_SLEW_BANK_STRIDE;
++	*reg += ((pin_num / RK3308_SLEW_PINS_PER_REG) * 4);
++	*bit = pin_num % RK3308_SLEW_PINS_PER_REG;
++
++	return 0;
++}
++
+ #define RK3328_SCHMITT_BITS_PER_PIN		1
+ #define RK3328_SCHMITT_PINS_PER_REG		16
+ #define RK3328_SCHMITT_BANK_STRIDE		8
+@@ -2646,6 +2666,51 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
+ 	return regmap_update_bits(regmap, reg, rmask, data);
+ }
+ 
++static int rockchip_get_slew_rate(struct rockchip_pin_bank *bank, int pin_num)
++{
++	struct rockchip_pinctrl *info = bank->drvdata;
++	struct rockchip_pin_ctrl *ctrl = info->ctrl;
++	struct regmap *regmap;
++	int reg, ret;
++	u8 bit;
++	u32 data;
++
++	ret = ctrl->slew_rate_calc_reg(bank, pin_num, &regmap, &reg, &bit);
++	if (ret)
++		return ret;
++
++	ret = regmap_read(regmap, reg, &data);
++	if (ret)
++		return ret;
++
++	data >>= bit;
++	return data & 0x1;
++}
++
++static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank,
++				  int pin_num, int speed)
++{
++	struct rockchip_pinctrl *info = bank->drvdata;
++	struct rockchip_pin_ctrl *ctrl = info->ctrl;
++	struct regmap *regmap;
++	int reg, ret;
++	u8 bit;
++	u32 data, rmask;
++
++	dev_dbg(info->dev, "setting slew rate of GPIO%d-%d to %d\n",
++		bank->bank_num, pin_num, speed);
++
++	ret = ctrl->slew_rate_calc_reg(bank, pin_num, &regmap, &reg, &bit);
++	if (ret)
++		return ret;
++
++	/* enable the write to the equivalent lower bits */
++	data = BIT(bit + 16) | (speed << bit);
++	rmask = BIT(bit + 16) | BIT(bit);
++
++	return regmap_update_bits(regmap, reg, rmask, data);
++}
++
+ /*
+  * Pinmux_ops handling
+  */
+@@ -2878,6 +2943,15 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ 			if (rc < 0)
+ 				return rc;
+ 			break;
++		case PIN_CONFIG_SLEW_RATE:
++			if (!info->ctrl->slew_rate_calc_reg)
++				return -ENOTSUPP;
++
++			rc = rockchip_set_slew_rate(bank,
++						    pin - bank->pin_base, arg);
++			if (rc < 0)
++				return rc;
++			break;
+ 		default:
+ 			return -ENOTSUPP;
+ 			break;
+@@ -2952,6 +3026,26 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ 		if (rc < 0)
+ 			return rc;
+ 
++		arg = rc;
++		break;
++	case PIN_CONFIG_SLEW_RATE:
++		if (!info->ctrl->slew_rate_calc_reg)
++			return -ENOTSUPP;
++
++		rc = rockchip_get_slew_rate(bank, pin - bank->pin_base);
++		if (rc < 0)
++			return rc;
++
++		arg = rc;
++		break;
++	case PIN_CONFIG_MUX:
++		if (!info->ctrl->schmitt_calc_reg)
++			return -ENOTSUPP;
++
++		rc = rockchip_get_mux(bank, pin - bank->pin_base);
++		if (rc < 0)
++			return rc;
++
+ 		arg = rc;
+ 		break;
+ 	default:
+@@ -3759,6 +3853,7 @@ static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
+ 		.pull_calc_reg		= rk3308_calc_pull_reg_and_bit,
+ 		.drv_calc_reg		= rk3308_calc_drv_reg_and_bit,
+ 		.schmitt_calc_reg	= rk3308_calc_schmitt_reg_and_bit,
++		.slew_rate_calc_reg	= rk3308_calc_slew_reg_and_bit,
+ };
+ 
+ static struct rockchip_pin_bank rk3328_pin_banks[] = {
+diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
+index 4759f336941e..785f48791631 100644
+--- a/drivers/pinctrl/pinctrl-rockchip.h
++++ b/drivers/pinctrl/pinctrl-rockchip.h
+@@ -406,6 +406,9 @@ struct rockchip_pin_ctrl {
+ 	int	(*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
+ 				    int pin_num, struct regmap **regmap,
+ 				    int *reg, u8 *bit);
++	int	(*slew_rate_calc_reg)(struct rockchip_pin_bank *bank,
++				      int pin_num, struct regmap **regmap,
++				      int *reg, u8 *bit);
+ };
+ 
+ struct rockchip_pin_config {
+diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
+index d74b7a4ea154..87bd22137988 100644
+--- a/include/linux/pinctrl/pinconf-generic.h
++++ b/include/linux/pinctrl/pinconf-generic.h
+@@ -142,6 +142,7 @@ enum pin_config_param {
+ 	PIN_CONFIG_SKEW_DELAY,
+ 	PIN_CONFIG_SLEEP_HARDWARE_STATE,
+ 	PIN_CONFIG_SLEW_RATE,
++	PIN_CONFIG_MUX,
+ 	PIN_CONFIG_END = 0x7F,
+ 	PIN_CONFIG_MAX = 0xFF,
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3308-0002-iodomains.patch b/patch/kernel/archive/rockchip64-6.10/rk3308-0002-iodomains.patch
new file mode 100644
index 000000000000..b78de78c4f8c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3308-0002-iodomains.patch
@@ -0,0 +1,159 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: brentr <brent@mbari.org>
+Date: Thu, 13 Oct 2022 18:34:43 +0200
+Subject: [ARCHEOLOGY] Rockpis wifi fixes (#4008)
+
+> X-Git-Archeology: > recovered message: > * RockPI-S board has no video I/O
+> X-Git-Archeology: > recovered message: > * udev rule to fix MAC address of iface based on UUID
+> X-Git-Archeology: > recovered message: > Deals with WiFi chip lacking any EEPROM to store its unique Ethernet MAC address
+> X-Git-Archeology: > recovered message: > Generic mechanism -- could be utilized for other boards having similar issues
+> X-Git-Archeology: > recovered message: > * Handy Device Tree overlays for the RockPI S
+> X-Git-Archeology: > recovered message: > Use armbian-add-overlay to install these
+> X-Git-Archeology: > recovered message: > Reduce CPU voltage for the RK3308 B-S
+> X-Git-Archeology: > recovered message: > Option to overclock RK3308 B-S to 1.3Ghz
+> X-Git-Archeology: > recovered message: > Increase SDIO clock rate from 1Mhz to 10Mhz
+> X-Git-Archeology: > recovered message: > This increases WiFi throughput from 300K bytes/s to 2.4M bytes/s
+> X-Git-Archeology: > recovered message: > * corrected comment
+> X-Git-Archeology: > recovered message: > * No longer repeat standard opp's in this dts
+> X-Git-Archeology: > recovered message: > Require that the standard bs dts already be installed
+> X-Git-Archeology: > recovered message: > * User README for adding RockPI-S board variant specific dts overlays
+> X-Git-Archeology: > recovered message: > * "enabled" --> "okay"
+> X-Git-Archeology: > recovered message: > * added mention of sdnand.dts, fixed typo
+> X-Git-Archeology: > recovered message: > * added p2p0 to interfaces whose MAC address should be "fixed"
+> X-Git-Archeology: > recovered message: > * RK3308 CPU serial number in nvmem replaces UUID for derivation of fixed MAC addr
+> X-Git-Archeology: > recovered message: > Restored use of install utility
+> X-Git-Archeology: > recovered message: > * Use RK3308 specific CPU serial number
+> X-Git-Archeology: > recovered message: > rather than rootfs UUID
+> X-Git-Archeology: > recovered message: > * remove generic fixMACaddress
+> X-Git-Archeology: > recovered message: > * Install fixMACaddr file-by-file via install utility
+> X-Git-Archeology: > recovered message: > * Drive SDIO bus signals faster
+> X-Git-Archeology: > recovered message: > setting RK3308_SOC_CON0_VCCIO3 reduces signal rise/fall times to WiFi SDIO chip
+> X-Git-Archeology: > recovered message: > from 30ns to 5ns.
+> X-Git-Archeology: > recovered message: > This odd fix forward ported from legacy kernel.
+> X-Git-Archeology: > recovered message: > Allows Rock Pi-S WiFi to operate at full speed.
+> X-Git-Archeology: > recovered message: > * Set RK3308 I/O voltage domains before SDIO initializes
+> X-Git-Archeology: > recovered message: > This patch moves responibility form the io-domain to the pinctrl driver because
+> X-Git-Archeology: > recovered message: > the io-domain driver is probed after the SDIO devices are discovered.
+> X-Git-Archeology: > recovered message: > This was causing multiple SDIO I/O failures during boot.
+> X-Git-Archeology: > recovered message: > A new pinctrl property is added:
+> X-Git-Archeology: > recovered message: > io-1v8-domains
+> X-Git-Archeology: > recovered message: > is a u32 interpreted as a bit mask where each set bit corresponds to
+> X-Git-Archeology: > recovered message: > a 1.8V I/O domain (as opposed to the default of 3.3V for I/O)
+> X-Git-Archeology: > recovered message: > The mask is writted to the RK3308_SOC_CON0 GRF register
+> X-Git-Archeology: > recovered message: > (once) when the pinctrl driver starts
+> X-Git-Archeology: > recovered message: > The default mask is 0x10 where only I/O domain 4 runs at 1.8V
+> X-Git-Archeology: > recovered message: > This is necessary for the RockPI-S to run the SDIO clock at high (50Mhz) speed
+> X-Git-Archeology: > recovered message: > * align whitespace
+> X-Git-Archeology: > recovered message: > * factored rk3308bs overlays out up sdio speedup patch
+> X-Git-Archeology: > recovered message: > * factored dts for RK3308 iodomains and pinctrl patches out of speedup patch
+> X-Git-Archeology: > recovered message: > * remains of sdio speedup patch merely add iodomains support for rk3308
+> X-Git-Archeology: > recovered message: > * factored rockpis dts modification out from rk3308 io voltage domains
+> X-Git-Archeology: > recovered message: > replaced rk3308 support from iodomains with
+> X-Git-Archeology: > recovered message: > new io-voltage-domains property added to pinctrl
+> X-Git-Archeology: > recovered message: > io-voltage-domains specific to rk3308 for now, others SOCs may be added later.
+> X-Git-Archeology: > recovered message: > * add sequence numbering to names of rk3308 patches
+> X-Git-Archeology: > recovered message: > * corrected tab alignment
+> X-Git-Archeology: - Revision d3a3afe3850861ceaeb44f3631251c764a28cd43: https://github.com/armbian/build/commit/d3a3afe3850861ceaeb44f3631251c764a28cd43
+> X-Git-Archeology:   Date: Thu, 13 Oct 2022 18:34:43 +0200
+> X-Git-Archeology:   From: brentr <brent@mbari.org>
+> X-Git-Archeology:   Subject: Rockpis wifi fixes (#4008)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ drivers/soc/rockchip/io-domain.c | 45 ++++++++++
+ 1 file changed, 45 insertions(+)
+
+diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c
+index 6619256c2d11..6ffaccd3ed80 100644
+--- a/drivers/soc/rockchip/io-domain.c
++++ b/drivers/soc/rockchip/io-domain.c
+@@ -39,6 +39,10 @@
+ #define RK3288_SOC_CON2_FLASH0		BIT(7)
+ #define RK3288_SOC_FLASH_SUPPLY_NUM	2
+ 
++#define RK3308_SOC_CON0			0x300
++#define RK3308_SOC_CON0_VCCIO3		BIT(8)
++#define RK3308_SOC_VCCIO3_SUPPLY_NUM	3
++
+ #define RK3328_SOC_CON4			0x410
+ #define RK3328_SOC_CON4_VCCIO2		BIT(7)
+ #define RK3328_SOC_VCCIO2_SUPPLY_NUM	1
+@@ -229,6 +233,30 @@ static void rk3288_iodomain_init(struct rockchip_iodomain *iod)
+ 		dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
+ }
+ 
++static void rk3308_iodomain_init(struct rockchip_iodomain *iod)
++{
++	int ret;
++	u32 val;
++
++	/* if no vccio3 supply we should leave things alone */
++	if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg)
++		return;
++
++	/*
++	 * vccio3 iodomain voltage should be determined by GPIO4 input state
++	 * RockPI-S uses this to drive the SDIO interface at 50Mhz
++	 * (otherwise SDIO clock will be limited to 10Mhz)
++	 *
++	 * Note that setting vccio4 [rather than vccio3] is observed to reduce
++	 * the rise time of SDIO-clk from 30ns to 5ns.
++	 * The CON0_VCCIO3 control bit appears to influence vccio4.
++	 */
++	val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16);
++	ret = regmap_write(iod->grf, RK3308_SOC_CON0, val);
++	if (ret < 0)
++		dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n");
++}
++
+ static void rk3328_iodomain_init(struct rockchip_iodomain *iod)
+ {
+ 	int ret;
+@@ -376,6 +404,19 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3288 = {
+ 	.init = rk3288_iodomain_init,
+ };
+ 
++static const struct rockchip_iodomain_soc_data soc_data_rk3308 = {
++	.grf_offset = 0x300,
++	.supply_names = {
++		"vccio0",
++		"vccio1",
++		"vccio2",
++		"vccio3",
++		"vccio4",
++		"vccio5",
++	},
++	.init = rk3308_iodomain_init,
++};
++
+ static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
+ 	.grf_offset = 0x410,
+ 	.supply_names = {
+@@ -528,6 +569,10 @@ static const struct of_device_id rockchip_iodomain_match[] = {
+ 		.compatible = "rockchip,rk3288-io-voltage-domain",
+ 		.data = &soc_data_rk3288
+ 	},
++	{
++		.compatible = "rockchip,rk3308-io-voltage-domain",
++		.data = &soc_data_rk3308
++	},
+ 	{
+ 		.compatible = "rockchip,rk3328-io-voltage-domain",
+ 		.data = &soc_data_rk3328
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3308-0003-pinctrl-io-voltage-domains.patch b/patch/kernel/archive/rockchip64-6.10/rk3308-0003-pinctrl-io-voltage-domains.patch
new file mode 100644
index 000000000000..d0cafa90ce57
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3308-0003-pinctrl-io-voltage-domains.patch
@@ -0,0 +1,202 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: brentr <brent@mbari.org>
+Date: Thu, 13 Oct 2022 18:34:43 +0200
+Subject: [ARCHEOLOGY] Rockpis wifi fixes (#4008)
+
+> X-Git-Archeology: > recovered message: > * RockPI-S board has no video I/O
+> X-Git-Archeology: > recovered message: > * udev rule to fix MAC address of iface based on UUID
+> X-Git-Archeology: > recovered message: > Deals with WiFi chip lacking any EEPROM to store its unique Ethernet MAC address
+> X-Git-Archeology: > recovered message: > Generic mechanism -- could be utilized for other boards having similar issues
+> X-Git-Archeology: > recovered message: > * Handy Device Tree overlays for the RockPI S
+> X-Git-Archeology: > recovered message: > Use armbian-add-overlay to install these
+> X-Git-Archeology: > recovered message: > Reduce CPU voltage for the RK3308 B-S
+> X-Git-Archeology: > recovered message: > Option to overclock RK3308 B-S to 1.3Ghz
+> X-Git-Archeology: > recovered message: > Increase SDIO clock rate from 1Mhz to 10Mhz
+> X-Git-Archeology: > recovered message: > This increases WiFi throughput from 300K bytes/s to 2.4M bytes/s
+> X-Git-Archeology: > recovered message: > * corrected comment
+> X-Git-Archeology: > recovered message: > * No longer repeat standard opp's in this dts
+> X-Git-Archeology: > recovered message: > Require that the standard bs dts already be installed
+> X-Git-Archeology: > recovered message: > * User README for adding RockPI-S board variant specific dts overlays
+> X-Git-Archeology: > recovered message: > * "enabled" --> "okay"
+> X-Git-Archeology: > recovered message: > * added mention of sdnand.dts, fixed typo
+> X-Git-Archeology: > recovered message: > * added p2p0 to interfaces whose MAC address should be "fixed"
+> X-Git-Archeology: > recovered message: > * RK3308 CPU serial number in nvmem replaces UUID for derivation of fixed MAC addr
+> X-Git-Archeology: > recovered message: > Restored use of install utility
+> X-Git-Archeology: > recovered message: > * Use RK3308 specific CPU serial number
+> X-Git-Archeology: > recovered message: > rather than rootfs UUID
+> X-Git-Archeology: > recovered message: > * remove generic fixMACaddress
+> X-Git-Archeology: > recovered message: > * Install fixMACaddr file-by-file via install utility
+> X-Git-Archeology: > recovered message: > * Drive SDIO bus signals faster
+> X-Git-Archeology: > recovered message: > setting RK3308_SOC_CON0_VCCIO3 reduces signal rise/fall times to WiFi SDIO chip
+> X-Git-Archeology: > recovered message: > from 30ns to 5ns.
+> X-Git-Archeology: > recovered message: > This odd fix forward ported from legacy kernel.
+> X-Git-Archeology: > recovered message: > Allows Rock Pi-S WiFi to operate at full speed.
+> X-Git-Archeology: > recovered message: > * Set RK3308 I/O voltage domains before SDIO initializes
+> X-Git-Archeology: > recovered message: > This patch moves responibility form the io-domain to the pinctrl driver because
+> X-Git-Archeology: > recovered message: > the io-domain driver is probed after the SDIO devices are discovered.
+> X-Git-Archeology: > recovered message: > This was causing multiple SDIO I/O failures during boot.
+> X-Git-Archeology: > recovered message: > A new pinctrl property is added:
+> X-Git-Archeology: > recovered message: > io-1v8-domains
+> X-Git-Archeology: > recovered message: > is a u32 interpreted as a bit mask where each set bit corresponds to
+> X-Git-Archeology: > recovered message: > a 1.8V I/O domain (as opposed to the default of 3.3V for I/O)
+> X-Git-Archeology: > recovered message: > The mask is writted to the RK3308_SOC_CON0 GRF register
+> X-Git-Archeology: > recovered message: > (once) when the pinctrl driver starts
+> X-Git-Archeology: > recovered message: > The default mask is 0x10 where only I/O domain 4 runs at 1.8V
+> X-Git-Archeology: > recovered message: > This is necessary for the RockPI-S to run the SDIO clock at high (50Mhz) speed
+> X-Git-Archeology: > recovered message: > * align whitespace
+> X-Git-Archeology: > recovered message: > * factored rk3308bs overlays out up sdio speedup patch
+> X-Git-Archeology: > recovered message: > * factored dts for RK3308 iodomains and pinctrl patches out of speedup patch
+> X-Git-Archeology: > recovered message: > * remains of sdio speedup patch merely add iodomains support for rk3308
+> X-Git-Archeology: > recovered message: > * factored rockpis dts modification out from rk3308 io voltage domains
+> X-Git-Archeology: > recovered message: > replaced rk3308 support from iodomains with
+> X-Git-Archeology: > recovered message: > new io-voltage-domains property added to pinctrl
+> X-Git-Archeology: > recovered message: > io-voltage-domains specific to rk3308 for now, others SOCs may be added later.
+> X-Git-Archeology: > recovered message: > * add sequence numbering to names of rk3308 patches
+> X-Git-Archeology: > recovered message: > * corrected tab alignment
+> X-Git-Archeology: - Revision d3a3afe3850861ceaeb44f3631251c764a28cd43: https://github.com/armbian/build/commit/d3a3afe3850861ceaeb44f3631251c764a28cd43
+> X-Git-Archeology:   Date: Thu, 13 Oct 2022 18:34:43 +0200
+> X-Git-Archeology:   From: brentr <brent@mbari.org>
+> X-Git-Archeology:   Subject: Rockpis wifi fixes (#4008)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ drivers/pinctrl/pinctrl-rockchip.c | 24 +++++
+ drivers/soc/rockchip/io-domain.c   | 45 ----------
+ 2 files changed, 24 insertions(+), 45 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
+index 94af47ad9667..9b9200634bb6 100644
+--- a/drivers/pinctrl/pinctrl-rockchip.c
++++ b/drivers/pinctrl/pinctrl-rockchip.c
+@@ -40,6 +40,12 @@
+ #include "pinconf.h"
+ #include "pinctrl-rockchip.h"
+ 
++#define RK3308_SOC_CON0			0x300
++#define RK3308_SOC_CON0_DOMAINS ((BIT(9)-1)-BIT(7))
++#define RK3308_SOC_CON0_DEFAULT 0x10  //default if no io_1v8_domains specified
++//note that this is supposed to be the reset value, but something early
++//in boot sets SOC_CON0 to zero
++
+ /*
+  * Generate a bitmask for setting a value (v) with a write mask bit in hiword
+  * register 31:16 area.
+@@ -3514,6 +3520,24 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
++	if (ctrl->type == RK3308) {
++	/*
++	 * Update GRF_SOC_CON0 early to reflect board's (fixed) I/O domain voltages
++	 * The io-1v8-domains property may be specified to override default value
++	 */
++		u32 ioVoltSelect = RK3308_SOC_CON0_DEFAULT;
++		device_property_read_u32(dev, "io-1v8-domains", &ioVoltSelect);
++		if (ioVoltSelect & ~RK3308_SOC_CON0_DOMAINS) {
++			dev_warn(dev, "ignored invalid io-1v8-domains\n");
++			ioVoltSelect = RK3308_SOC_CON0_DEFAULT;
++		}
++	  ret = regmap_write(info->regmap_base, RK3308_SOC_CON0,
++		ioVoltSelect | (RK3308_SOC_CON0_DOMAINS << 16));
++		dev_info(dev, "1.8V I/O domains assigned 0x%03x\n", ioVoltSelect);
++		if (ret < 0)
++			dev_warn(dev, "Couldn't update 1.8V I/O domains\n");
++	}
++
+ 	platform_set_drvdata(pdev, info);
+ 
+ 	ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
+diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c
+index 6ffaccd3ed80..6619256c2d11 100644
+--- a/drivers/soc/rockchip/io-domain.c
++++ b/drivers/soc/rockchip/io-domain.c
+@@ -39,10 +39,6 @@
+ #define RK3288_SOC_CON2_FLASH0		BIT(7)
+ #define RK3288_SOC_FLASH_SUPPLY_NUM	2
+ 
+-#define RK3308_SOC_CON0			0x300
+-#define RK3308_SOC_CON0_VCCIO3		BIT(8)
+-#define RK3308_SOC_VCCIO3_SUPPLY_NUM	3
+-
+ #define RK3328_SOC_CON4			0x410
+ #define RK3328_SOC_CON4_VCCIO2		BIT(7)
+ #define RK3328_SOC_VCCIO2_SUPPLY_NUM	1
+@@ -233,30 +229,6 @@ static void rk3288_iodomain_init(struct rockchip_iodomain *iod)
+ 		dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
+ }
+ 
+-static void rk3308_iodomain_init(struct rockchip_iodomain *iod)
+-{
+-	int ret;
+-	u32 val;
+-
+-	/* if no vccio3 supply we should leave things alone */
+-	if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg)
+-		return;
+-
+-	/*
+-	 * vccio3 iodomain voltage should be determined by GPIO4 input state
+-	 * RockPI-S uses this to drive the SDIO interface at 50Mhz
+-	 * (otherwise SDIO clock will be limited to 10Mhz)
+-	 *
+-	 * Note that setting vccio4 [rather than vccio3] is observed to reduce
+-	 * the rise time of SDIO-clk from 30ns to 5ns.
+-	 * The CON0_VCCIO3 control bit appears to influence vccio4.
+-	 */
+-	val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16);
+-	ret = regmap_write(iod->grf, RK3308_SOC_CON0, val);
+-	if (ret < 0)
+-		dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n");
+-}
+-
+ static void rk3328_iodomain_init(struct rockchip_iodomain *iod)
+ {
+ 	int ret;
+@@ -404,19 +376,6 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3288 = {
+ 	.init = rk3288_iodomain_init,
+ };
+ 
+-static const struct rockchip_iodomain_soc_data soc_data_rk3308 = {
+-	.grf_offset = 0x300,
+-	.supply_names = {
+-		"vccio0",
+-		"vccio1",
+-		"vccio2",
+-		"vccio3",
+-		"vccio4",
+-		"vccio5",
+-	},
+-	.init = rk3308_iodomain_init,
+-};
+-
+ static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
+ 	.grf_offset = 0x410,
+ 	.supply_names = {
+@@ -569,10 +528,6 @@ static const struct of_device_id rockchip_iodomain_match[] = {
+ 		.compatible = "rockchip,rk3288-io-voltage-domain",
+ 		.data = &soc_data_rk3288
+ 	},
+-	{
+-		.compatible = "rockchip,rk3308-io-voltage-domain",
+-		.data = &soc_data_rk3308
+-	},
+ 	{
+ 		.compatible = "rockchip,rk3328-io-voltage-domain",
+ 		.data = &soc_data_rk3328
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3308-add-missing-i2s-controllers.patch b/patch/kernel/archive/rockchip64-6.10/rk3308-add-missing-i2s-controllers.patch
new file mode 100644
index 000000000000..33577be68b2c
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3308-add-missing-i2s-controllers.patch
@@ -0,0 +1,82 @@
+From 8c92404a280aa7f35a311fb0939b8276371fcba3 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 21 Jul 2024 14:18:30 +0200
+Subject: [PATCH] add missing i2s controllers
+
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 59 ++++++++++++++++++++++++
+ 1 file changed, 59 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+index c00da150a22f..a9d1cb1debe9 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -578,6 +578,65 @@ dmac1: dma-controller@ff2d0000 {
+ 		#dma-cells = <1>;
+ 	};
+ 
++       i2s_8ch_0: i2s@ff300000 {
++		compatible = "rockchip,rk3308-i2s-tdm";
++		reg = <0x0 0xff300000 0x0 0x1000>;
++		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>,
++			<&cru SCLK_I2S0_8CH_TX_SRC>,
++			<&cru SCLK_I2S0_8CH_RX_SRC>,
++			<&cru PLL_VPLL0>,
++			<&cru PLL_VPLL1>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk",
++			      "mclk_tx_src", "mclk_rx_src",
++			      "mclk_root0", "mclk_root1";
++		dmas = <&dmac1 0>, <&dmac1 1>;
++		dma-names = "tx", "rx";
++		resets = <&cru SRST_I2S0_8CH_TX_M>, <&cru SRST_I2S0_8CH_RX_M>;
++		reset-names = "tx-m", "rx-m";
++		rockchip,cru = <&cru>;
++		rockchip,grf = <&grf>;
++		rockchip,mclk-calibrate;
++		pinctrl-names = "default";
++		pinctrl-0 = <&i2s_8ch_0_sclktx
++			&i2s_8ch_0_sclkrx
++			&i2s_8ch_0_lrcktx
++			&i2s_8ch_0_lrckrx
++			&i2s_8ch_0_sdi0
++			&i2s_8ch_0_sdi1
++			&i2s_8ch_0_sdi2
++			&i2s_8ch_0_sdi3
++			&i2s_8ch_0_sdo0
++			&i2s_8ch_0_sdo1
++			&i2s_8ch_0_sdo2
++			&i2s_8ch_0_sdo3
++			&i2s_8ch_0_mclk>;
++		status = "disabled";
++	};
++
++	i2s_8ch_1: i2s@ff310000 {
++		compatible = "rockchip,rk3308-i2s-tdm";
++		reg = <0x0 0xff310000 0x0 0x1000>;
++		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru SCLK_I2S1_8CH_TX>, <&cru SCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>,
++			 <&cru SCLK_I2S1_8CH_TX_SRC>,
++			 <&cru SCLK_I2S1_8CH_RX_SRC>,
++			 <&cru PLL_VPLL0>,
++			 <&cru PLL_VPLL1>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk",
++			      "mclk_tx_src", "mclk_rx_src",
++			      "mclk_root0", "mclk_root1";
++		dmas = <&dmac1 2>, <&dmac1 3>;
++		dma-names = "tx", "rx";
++		resets = <&cru SRST_I2S1_8CH_TX_M>, <&cru SRST_I2S1_8CH_RX_M>;
++		reset-names = "tx-m", "rx-m";
++		rockchip,cru = <&cru>;
++		rockchip,grf = <&grf>;
++		rockchip,mclk-calibrate;
++		rockchip,io-multiplex;
++		status = "disabled";
++	};
++
+ 	/*
+ 	 * - can be clock producer or consumer
+ 	 * - up to 8 capture channels and 2 playback channels
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3328-add-dmc-driver.patch b/patch/kernel/archive/rockchip64-6.10/rk3328-add-dmc-driver.patch
new file mode 100644
index 000000000000..96c0cbecdc95
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3328-add-dmc-driver.patch
@@ -0,0 +1,1901 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 12 Oct 2021 18:45:05 +0000
+Subject: rk3328 dmc driver
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi | 311 ++++
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi                     |  61 +
+ drivers/clk/rockchip/clk-ddr.c                               | 131 ++
+ drivers/clk/rockchip/clk-rk3328.c                            |  13 +-
+ drivers/clk/rockchip/clk.h                                   |   3 +-
+ drivers/devfreq/Kconfig                                      |  12 +
+ drivers/devfreq/Makefile                                     |   1 +
+ drivers/devfreq/event/rockchip-dfi.c                         | 554 +++++-
+ drivers/devfreq/rk3328_dmc.c                                 | 836 ++++++++++
+ include/dt-bindings/clock/rockchip-ddr.h                     |  63 +
+ include/dt-bindings/memory/rk3328-dram.h                     | 159 ++
+ include/soc/rockchip/rockchip_sip.h                          |  11 +
+ 12 files changed, 2099 insertions(+), 56 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
+new file mode 100644
+index 000000000000..a3f5ff4bdc47
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
+@@ -0,0 +1,311 @@
++/*
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++#include <dt-bindings/clock/rockchip-ddr.h>
++#include <dt-bindings/memory/rk3328-dram.h>
++
++/ {
++	ddr_timing: ddr_timing {
++		compatible = "rockchip,ddr-timing";
++		ddr3_speed_bin = <DDR3_DEFAULT>;
++		ddr4_speed_bin = <DDR4_DEFAULT>;
++		pd_idle = <0>;
++		sr_idle = <0>;
++		sr_mc_gate_idle = <0>;
++		srpd_lite_idle	= <0>;
++		standby_idle = <0>;
++
++		auto_pd_dis_freq = <1066>;
++		auto_sr_dis_freq = <800>;
++		ddr3_dll_dis_freq = <300>;
++		ddr4_dll_dis_freq = <625>;
++		phy_dll_dis_freq = <400>;
++
++		ddr3_odt_dis_freq = <100>;
++		phy_ddr3_odt_dis_freq = <100>;
++		ddr3_drv = <DDR3_DS_40ohm>;
++		ddr3_odt = <DDR3_ODT_120ohm>;
++		phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
++		phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
++		phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
++		phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
++
++		lpddr3_odt_dis_freq = <666>;
++		phy_lpddr3_odt_dis_freq = <666>;
++		lpddr3_drv = <LP3_DS_40ohm>;
++		lpddr3_odt = <LP3_ODT_240ohm>;
++		phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
++		phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
++		phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
++		phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
++
++		lpddr4_odt_dis_freq = <800>;
++		phy_lpddr4_odt_dis_freq = <800>;
++		lpddr4_drv = <LP4_PDDS_60ohm>;
++		lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
++		lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
++		phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
++		phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
++		phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
++		phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
++
++		ddr4_odt_dis_freq = <666>;
++		phy_ddr4_odt_dis_freq = <666>;
++		ddr4_drv = <DDR4_DS_34ohm>;
++		ddr4_odt = <DDR4_RTT_NOM_240ohm>;
++		phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
++		phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
++		phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
++		phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
++
++		/* CA de-skew, one step is 47.8ps, range 0-15 */
++		ddr3a1_ddr4a9_de-skew = <7>;
++		ddr3a0_ddr4a10_de-skew = <7>;
++		ddr3a3_ddr4a6_de-skew = <8>;
++		ddr3a2_ddr4a4_de-skew = <8>;
++		ddr3a5_ddr4a8_de-skew = <7>;
++		ddr3a4_ddr4a5_de-skew = <9>;
++		ddr3a7_ddr4a11_de-skew = <7>;
++		ddr3a6_ddr4a7_de-skew = <9>;
++		ddr3a9_ddr4a0_de-skew = <8>;
++		ddr3a8_ddr4a13_de-skew = <7>;
++		ddr3a11_ddr4a3_de-skew = <9>;
++		ddr3a10_ddr4cs0_de-skew = <7>;
++		ddr3a13_ddr4a2_de-skew = <8>;
++		ddr3a12_ddr4ba1_de-skew = <7>;
++		ddr3a15_ddr4odt0_de-skew = <7>;
++		ddr3a14_ddr4a1_de-skew = <8>;
++		ddr3ba1_ddr4a15_de-skew = <7>;
++		ddr3ba0_ddr4bg0_de-skew = <7>;
++		ddr3ras_ddr4cke_de-skew = <7>;
++		ddr3ba2_ddr4ba0_de-skew = <8>;
++		ddr3we_ddr4bg1_de-skew = <8>;
++		ddr3cas_ddr4a12_de-skew = <7>;
++		ddr3ckn_ddr4ckn_de-skew = <8>;
++		ddr3ckp_ddr4ckp_de-skew = <8>;
++		ddr3cke_ddr4a16_de-skew = <8>;
++		ddr3odt0_ddr4a14_de-skew = <7>;
++		ddr3cs0_ddr4act_de-skew = <8>;
++		ddr3reset_ddr4reset_de-skew = <7>;
++		ddr3cs1_ddr4cs1_de-skew = <7>;
++		ddr3odt1_ddr4odt1_de-skew = <7>;
++
++		/* DATA de-skew
++		 * RX one step is 25.1ps, range 0-15
++		 * TX one step is 47.8ps, range 0-15
++		 */
++		cs0_dm0_rx_de-skew = <7>;
++		cs0_dm0_tx_de-skew = <8>;
++		cs0_dq0_rx_de-skew = <7>;
++		cs0_dq0_tx_de-skew = <8>;
++		cs0_dq1_rx_de-skew = <7>;
++		cs0_dq1_tx_de-skew = <8>;
++		cs0_dq2_rx_de-skew = <7>;
++		cs0_dq2_tx_de-skew = <8>;
++		cs0_dq3_rx_de-skew = <7>;
++		cs0_dq3_tx_de-skew = <8>;
++		cs0_dq4_rx_de-skew = <7>;
++		cs0_dq4_tx_de-skew = <8>;
++		cs0_dq5_rx_de-skew = <7>;
++		cs0_dq5_tx_de-skew = <8>;
++		cs0_dq6_rx_de-skew = <7>;
++		cs0_dq6_tx_de-skew = <8>;
++		cs0_dq7_rx_de-skew = <7>;
++		cs0_dq7_tx_de-skew = <8>;
++		cs0_dqs0_rx_de-skew = <6>;
++		cs0_dqs0p_tx_de-skew = <9>;
++		cs0_dqs0n_tx_de-skew = <9>;
++
++		cs0_dm1_rx_de-skew = <7>;
++		cs0_dm1_tx_de-skew = <7>;
++		cs0_dq8_rx_de-skew = <7>;
++		cs0_dq8_tx_de-skew = <8>;
++		cs0_dq9_rx_de-skew = <7>;
++		cs0_dq9_tx_de-skew = <7>;
++		cs0_dq10_rx_de-skew = <7>;
++		cs0_dq10_tx_de-skew = <8>;
++		cs0_dq11_rx_de-skew = <7>;
++		cs0_dq11_tx_de-skew = <7>;
++		cs0_dq12_rx_de-skew = <7>;
++		cs0_dq12_tx_de-skew = <8>;
++		cs0_dq13_rx_de-skew = <7>;
++		cs0_dq13_tx_de-skew = <7>;
++		cs0_dq14_rx_de-skew = <7>;
++		cs0_dq14_tx_de-skew = <8>;
++		cs0_dq15_rx_de-skew = <7>;
++		cs0_dq15_tx_de-skew = <7>;
++		cs0_dqs1_rx_de-skew = <7>;
++		cs0_dqs1p_tx_de-skew = <9>;
++		cs0_dqs1n_tx_de-skew = <9>;
++
++		cs0_dm2_rx_de-skew = <7>;
++		cs0_dm2_tx_de-skew = <8>;
++		cs0_dq16_rx_de-skew = <7>;
++		cs0_dq16_tx_de-skew = <8>;
++		cs0_dq17_rx_de-skew = <7>;
++		cs0_dq17_tx_de-skew = <8>;
++		cs0_dq18_rx_de-skew = <7>;
++		cs0_dq18_tx_de-skew = <8>;
++		cs0_dq19_rx_de-skew = <7>;
++		cs0_dq19_tx_de-skew = <8>;
++		cs0_dq20_rx_de-skew = <7>;
++		cs0_dq20_tx_de-skew = <8>;
++		cs0_dq21_rx_de-skew = <7>;
++		cs0_dq21_tx_de-skew = <8>;
++		cs0_dq22_rx_de-skew = <7>;
++		cs0_dq22_tx_de-skew = <8>;
++		cs0_dq23_rx_de-skew = <7>;
++		cs0_dq23_tx_de-skew = <8>;
++		cs0_dqs2_rx_de-skew = <6>;
++		cs0_dqs2p_tx_de-skew = <9>;
++		cs0_dqs2n_tx_de-skew = <9>;
++
++		cs0_dm3_rx_de-skew = <7>;
++		cs0_dm3_tx_de-skew = <7>;
++		cs0_dq24_rx_de-skew = <7>;
++		cs0_dq24_tx_de-skew = <8>;
++		cs0_dq25_rx_de-skew = <7>;
++		cs0_dq25_tx_de-skew = <7>;
++		cs0_dq26_rx_de-skew = <7>;
++		cs0_dq26_tx_de-skew = <7>;
++		cs0_dq27_rx_de-skew = <7>;
++		cs0_dq27_tx_de-skew = <7>;
++		cs0_dq28_rx_de-skew = <7>;
++		cs0_dq28_tx_de-skew = <7>;
++		cs0_dq29_rx_de-skew = <7>;
++		cs0_dq29_tx_de-skew = <7>;
++		cs0_dq30_rx_de-skew = <7>;
++		cs0_dq30_tx_de-skew = <7>;
++		cs0_dq31_rx_de-skew = <7>;
++		cs0_dq31_tx_de-skew = <7>;
++		cs0_dqs3_rx_de-skew = <7>;
++		cs0_dqs3p_tx_de-skew = <9>;
++		cs0_dqs3n_tx_de-skew = <9>;
++
++		cs1_dm0_rx_de-skew = <7>;
++		cs1_dm0_tx_de-skew = <8>;
++		cs1_dq0_rx_de-skew = <7>;
++		cs1_dq0_tx_de-skew = <8>;
++		cs1_dq1_rx_de-skew = <7>;
++		cs1_dq1_tx_de-skew = <8>;
++		cs1_dq2_rx_de-skew = <7>;
++		cs1_dq2_tx_de-skew = <8>;
++		cs1_dq3_rx_de-skew = <7>;
++		cs1_dq3_tx_de-skew = <8>;
++		cs1_dq4_rx_de-skew = <7>;
++		cs1_dq4_tx_de-skew = <8>;
++		cs1_dq5_rx_de-skew = <7>;
++		cs1_dq5_tx_de-skew = <8>;
++		cs1_dq6_rx_de-skew = <7>;
++		cs1_dq6_tx_de-skew = <8>;
++		cs1_dq7_rx_de-skew = <7>;
++		cs1_dq7_tx_de-skew = <8>;
++		cs1_dqs0_rx_de-skew = <6>;
++		cs1_dqs0p_tx_de-skew = <9>;
++		cs1_dqs0n_tx_de-skew = <9>;
++
++		cs1_dm1_rx_de-skew = <7>;
++		cs1_dm1_tx_de-skew = <7>;
++		cs1_dq8_rx_de-skew = <7>;
++		cs1_dq8_tx_de-skew = <8>;
++		cs1_dq9_rx_de-skew = <7>;
++		cs1_dq9_tx_de-skew = <7>;
++		cs1_dq10_rx_de-skew = <7>;
++		cs1_dq10_tx_de-skew = <8>;
++		cs1_dq11_rx_de-skew = <7>;
++		cs1_dq11_tx_de-skew = <7>;
++		cs1_dq12_rx_de-skew = <7>;
++		cs1_dq12_tx_de-skew = <8>;
++		cs1_dq13_rx_de-skew = <7>;
++		cs1_dq13_tx_de-skew = <7>;
++		cs1_dq14_rx_de-skew = <7>;
++		cs1_dq14_tx_de-skew = <8>;
++		cs1_dq15_rx_de-skew = <7>;
++		cs1_dq15_tx_de-skew = <7>;
++		cs1_dqs1_rx_de-skew = <7>;
++		cs1_dqs1p_tx_de-skew = <9>;
++		cs1_dqs1n_tx_de-skew = <9>;
++
++		cs1_dm2_rx_de-skew = <7>;
++		cs1_dm2_tx_de-skew = <8>;
++		cs1_dq16_rx_de-skew = <7>;
++		cs1_dq16_tx_de-skew = <8>;
++		cs1_dq17_rx_de-skew = <7>;
++		cs1_dq17_tx_de-skew = <8>;
++		cs1_dq18_rx_de-skew = <7>;
++		cs1_dq18_tx_de-skew = <8>;
++		cs1_dq19_rx_de-skew = <7>;
++		cs1_dq19_tx_de-skew = <8>;
++		cs1_dq20_rx_de-skew = <7>;
++		cs1_dq20_tx_de-skew = <8>;
++		cs1_dq21_rx_de-skew = <7>;
++		cs1_dq21_tx_de-skew = <8>;
++		cs1_dq22_rx_de-skew = <7>;
++		cs1_dq22_tx_de-skew = <8>;
++		cs1_dq23_rx_de-skew = <7>;
++		cs1_dq23_tx_de-skew = <8>;
++		cs1_dqs2_rx_de-skew = <6>;
++		cs1_dqs2p_tx_de-skew = <9>;
++		cs1_dqs2n_tx_de-skew = <9>;
++
++		cs1_dm3_rx_de-skew = <7>;
++		cs1_dm3_tx_de-skew = <7>;
++		cs1_dq24_rx_de-skew = <7>;
++		cs1_dq24_tx_de-skew = <8>;
++		cs1_dq25_rx_de-skew = <7>;
++		cs1_dq25_tx_de-skew = <7>;
++		cs1_dq26_rx_de-skew = <7>;
++		cs1_dq26_tx_de-skew = <7>;
++		cs1_dq27_rx_de-skew = <7>;
++		cs1_dq27_tx_de-skew = <7>;
++		cs1_dq28_rx_de-skew = <7>;
++		cs1_dq28_tx_de-skew = <7>;
++		cs1_dq29_rx_de-skew = <7>;
++		cs1_dq29_tx_de-skew = <7>;
++		cs1_dq30_rx_de-skew = <7>;
++		cs1_dq30_tx_de-skew = <7>;
++		cs1_dq31_rx_de-skew = <7>;
++		cs1_dq31_tx_de-skew = <7>;
++		cs1_dqs3_rx_de-skew = <7>;
++		cs1_dqs3p_tx_de-skew = <9>;
++		cs1_dqs3n_tx_de-skew = <9>;
++	};
++};
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 303680413ed9..e3c8409c225f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -566,6 +566,67 @@ tsadc: tsadc@ff250000 {
+ 		status = "disabled";
+ 	};
+ 
++	dfi: dfi@ff790000 {
++		reg = <0x00 0xff790000 0x00 0x400>;
++		compatible = "rockchip,rk3328-dfi";
++		rockchip,grf = <&grf>;
++		status = "okay";
++	};
++
++	dmc: dmc@ff780000 {
++		reg = <0x00 0xff780000 0x00 0x400>;
++		compatible = "rockchip,rk3328-dmc";
++		devfreq-events = <&dfi>;
++		clocks = <&cru SCLK_DDRCLK>;
++		clock-names = "dmc_clk";
++		operating-points-v2 = <&dmc_opp_table>;
++		#cooling-cells = <2>;
++		status = "disabled";
++	};
++
++	dmc_opp_table: dmc-opp-table {
++		compatible = "operating-points-v2";
++
++		opp-600000000 {
++			opp-hz = /bits/ 64 <600000000>;
++			opp-microvolt = <1000000 1000000 1200000>;
++		};
++
++		opp-666000000 {
++			opp-hz = /bits/ 64 <666000000>;
++			opp-microvolt = <1025000 1025000 1200000>;
++		};
++
++		opp-786000000 {
++			opp-hz = /bits/ 64 <786000000>;
++			opp-microvolt = <1050000 1050000 1200000>;
++		};
++
++		opp-800000000 {
++			opp-hz = /bits/ 64 <800000000>;
++			opp-microvolt = <1050000 1050000 1200000>;
++			status = "disabled";
++		};
++
++		opp-850000000 {
++			opp-hz = /bits/ 64 <850000000>;
++			opp-microvolt = <1050000 1050000 1200000>; // Untested
++			status = "disabled";
++		};
++
++		opp-933000000 {
++			opp-hz = /bits/ 64 <933000000>;
++			opp-microvolt = <1100000 1100000 1200000>; // Untested
++			status = "disabled";
++		};
++
++		opp-1066000000 {
++			opp-hz = /bits/ 64 <1066000000>;
++			opp-microvolt = <1150000 1150000 1200000>; // Untested
++			status = "disabled";
++		};
++	};
++
+ 	efuse: efuse@ff260000 {
+ 		compatible = "rockchip,rk3328-efuse";
+ 		reg = <0x0 0xff260000 0x0 0x50>;
+diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
+index 86718c54e56b..08b313495e8c 100644
+--- a/drivers/clk/rockchip/clk-ddr.c
++++ b/drivers/clk/rockchip/clk-ddr.c
+@@ -87,6 +87,134 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = {
+ 	.get_parent = rockchip_ddrclk_get_parent,
+ };
+ 
++/* See v4.4/include/dt-bindings/display/rk_fb.h */
++#define SCREEN_NULL			0
++#define SCREEN_HDMI			6
++
++static inline int rk_drm_get_lcdc_type(void)
++{
++	return SCREEN_NULL;
++}
++
++struct share_params {
++	u32 hz;
++	u32 lcdc_type;
++	u32 vop;
++	u32 vop_dclk_mode;
++	u32 sr_idle_en;
++	u32 addr_mcu_el3;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag1;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag0;
++	u32 complt_hwirq;
++	 /* if need, add parameter after */
++};
++
++struct rockchip_ddrclk_data {
++	u32 inited_flag;
++	void __iomem *share_memory;
++};
++
++static struct rockchip_ddrclk_data ddr_data;
++
++static void rockchip_ddrclk_data_init(void)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
++		      1, SHARE_PAGE_TYPE_DDR, 0,
++		      0, 0, 0, 0, &res);
++
++	if (!res.a0) {
++		ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
++		ddr_data.inited_flag = 1;
++	}
++}
++
++static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
++					   unsigned long drate,
++					   unsigned long prate)
++{
++	struct share_params *p;
++	struct arm_smccc_res res;
++
++	if (!ddr_data.inited_flag)
++		rockchip_ddrclk_data_init();
++
++	p = (struct share_params *)ddr_data.share_memory;
++
++	p->hz = drate;
++	p->lcdc_type = rk_drm_get_lcdc_type();
++	p->wait_flag1 = 1;
++	p->wait_flag0 = 1;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0,
++		      ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
++		      0, 0, 0, 0, &res);
++
++	if ((int)res.a1 == -6) {
++		pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
++		/* TODO: rockchip_dmcfreq_wait_complete(); */
++	}
++
++	return res.a0;
++}
++
++static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
++			(struct clk_hw *hw, unsigned long parent_rate)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0,
++		      ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
++		      0, 0, 0, 0, &res);
++	if (!res.a0)
++		return res.a1;
++	else
++		return 0;
++}
++
++static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
++					      unsigned long rate,
++					      unsigned long *prate)
++{
++	struct share_params *p;
++	struct arm_smccc_res res;
++
++	if (!ddr_data.inited_flag)
++		rockchip_ddrclk_data_init();
++
++	p = (struct share_params *)ddr_data.share_memory;
++
++	p->hz = rate;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0,
++		      ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
++		      0, 0, 0, 0, &res);
++
++	if (!res.a0)
++		return res.a1;
++	else
++		return 0;
++}
++
++static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
++	.recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
++	.set_rate = rockchip_ddrclk_sip_set_rate_v2,
++	.round_rate = rockchip_ddrclk_sip_round_rate_v2,
++	.get_parent = rockchip_ddrclk_get_parent,
++};
++
+ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+ 					 const char *const *parent_names,
+ 					 u8 num_parents, int mux_offset,
+@@ -114,6 +242,9 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+ 	case ROCKCHIP_DDRCLK_SIP:
+ 		init.ops = &rockchip_ddrclk_sip_ops;
+ 		break;
++	case ROCKCHIP_DDRCLK_SIP_V2:
++		init.ops = &rockchip_ddrclk_sip_ops_v2;
++		break;
+ 	default:
+ 		pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
+ 		kfree(ddrclk);
+diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
+index 267ab54937d3..aa4afc8a17aa 100644
+--- a/drivers/clk/rockchip/clk-rk3328.c
++++ b/drivers/clk/rockchip/clk-rk3328.c
+@@ -315,14 +315,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
+ 			RK3328_CLKGATE_CON(14), 1, GFLAGS),
+ 
+ 	/* PD_DDR */
+-	COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+-			RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+-			RK3328_CLKGATE_CON(0), 4, GFLAGS),
+-	GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
++	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
++			RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
++			ROCKCHIP_DDRCLK_SIP_V2),
++
++	GATE(0, "clk_ddrmsch", "sclk_ddrc", CLK_IGNORE_UNUSED,
+ 			RK3328_CLKGATE_CON(18), 6, GFLAGS),
+-	GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
++	GATE(0, "clk_ddrupctl", "sclk_ddrc", CLK_IGNORE_UNUSED,
+ 			RK3328_CLKGATE_CON(18), 5, GFLAGS),
+-	GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
++	GATE(0, "aclk_ddrupctl", "sclk_ddrc", CLK_IGNORE_UNUSED,
+ 			RK3328_CLKGATE_CON(18), 4, GFLAGS),
+ 	GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
+ 			RK3328_CLKGATE_CON(0), 6, GFLAGS),
+diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
+index 758ebaf2236b..fe033ebcb62d 100644
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -486,7 +486,8 @@ struct clk *rockchip_clk_register_mmc(const char *name,
+  * DDRCLK flags, including method of setting the rate
+  * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
+  */
+-#define ROCKCHIP_DDRCLK_SIP		BIT(0)
++#define ROCKCHIP_DDRCLK_SIP		0x01
++#define ROCKCHIP_DDRCLK_SIP_V2		0x03
+ 
+ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+ 					 const char *const *parent_names,
+diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
+index 3c4862a752b5..ab0e2bd1c8de 100644
+--- a/drivers/devfreq/Kconfig
++++ b/drivers/devfreq/Kconfig
+@@ -129,6 +129,18 @@ config ARM_MEDIATEK_CCI_DEVFREQ
+ 	  buck voltages and update a proper CCI frequency. Use the notification
+ 	  to get the regulator status.
+ 
++config ARM_RK3328_DMC_DEVFREQ
++	tristate "ARM RK3328 DMC DEVFREQ Driver"
++	depends on ARCH_ROCKCHIP
++	select DEVFREQ_EVENT_ROCKCHIP_DFI
++	select DEVFREQ_GOV_SIMPLE_ONDEMAND
++	select PM_DEVFREQ_EVENT
++	select PM_OPP
++	help
++	  This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller).
++	  It sets the frequency for the memory controller and reads the usage counts
++	  from hardware.
++
+ config ARM_RK3399_DMC_DEVFREQ
+ 	tristate "ARM RK3399 DMC DEVFREQ Driver"
+ 	depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
+diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
+index bf40d04928d0..08c0738ae439 100644
+--- a/drivers/devfreq/Makefile
++++ b/drivers/devfreq/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ)	+= imx-bus.o
+ obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ)	+= imx8m-ddrc.o
+ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ)	+= mtk-cci-devfreq.o
+ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)	+= rk3399_dmc.o
++obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ)	+= rk3328_dmc.o
+ obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)	+= sun8i-a33-mbus.o
+ obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra30-devfreq.o
+ 
+diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
+index e2a1e4463b6f..fba3a958b352 100644
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -24,6 +24,8 @@
+ #include <linux/perf_event.h>
+ 
+ #include <soc/rockchip/rockchip_grf.h>
++#include <soc/rockchip/rk3228_grf.h>
++#include <soc/rockchip/rk3328_grf.h>
+ #include <soc/rockchip/rk3399_grf.h>
+ #include <soc/rockchip/rk3568_grf.h>
+ #include <soc/rockchip/rk3588_grf.h>
+@@ -99,6 +101,7 @@ struct rockchip_dfi {
+ 
+ 	struct device *dev;
+ 	void __iomem *regs;
++	struct regmap *regmap_grf;
+ 	struct regmap *regmap_pmu;
+ 	struct clk *clk;
+ 	int usecount;
+@@ -669,6 +672,46 @@ static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
+ }
+ #endif
+ 
++static int rk3228_dfi_init(struct rockchip_dfi *dfi)
++{
++	u32 val;
++
++	regmap_read(dfi->regmap_grf, RK3228_GRF_OS_REG2, &val);
++	dfi->ddr_type = FIELD_GET(RK3228_GRF_OS_REG2_DDRTYPE, val);
++
++	dfi->channel_mask = GENMASK(0, 0);
++	dfi->max_channels = 1;
++
++	dfi->buswidth[0] = 2;  // 16 bit bus width
++
++	dfi->ddrmon_stride = 0x0;  // single channel controller
++	dfi->ddrmon_ctrl_single = true;
++
++	dfi->clk = NULL;
++
++	return 0;
++}
++
++static int rk3328_dfi_init(struct rockchip_dfi *dfi)
++{
++	u32 val;
++
++	regmap_read(dfi->regmap_grf, RK3328_GRF_OS_REG2, &val);
++	dfi->ddr_type = FIELD_GET(RK3328_GRF_OS_REG2_DDRTYPE, val);
++
++	dfi->channel_mask = GENMASK(0, 0);
++	dfi->max_channels = 1;
++
++	dfi->buswidth[0] = 2;  // 16 bit bus width
++
++	dfi->ddrmon_stride = 0x0;  // single channel controller
++	dfi->ddrmon_ctrl_single = true;
++
++	dfi->clk = NULL;
++
++	return 0;
++}
++
+ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
+ {
+ 	struct regmap *regmap_pmu = dfi->regmap_pmu;
+@@ -757,6 +800,8 @@ static int rk3588_dfi_init(struct rockchip_dfi *dfi)
+ };
+ 
+ static const struct of_device_id rockchip_dfi_id_match[] = {
++	{ .compatible = "rockchip,rk3228-dfi", .data = rk3228_dfi_init },
++	{ .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
+ 	{ .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
+ 	{ .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
+ 	{ .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
+@@ -786,14 +831,30 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
+ 	if (IS_ERR(dfi->regs))
+ 		return PTR_ERR(dfi->regs);
+ 
+-	node = of_parse_phandle(np, "rockchip,pmu", 0);
+-	if (!node)
+-		return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
++	if (soc_init == rk3228_dfi_init ||
++	    soc_init == rk3328_dfi_init) {
++		node = of_parse_phandle(np, "rockchip,grf", 0);
++		if (!node)
++			return dev_err_probe(&pdev->dev, -ENODEV, "Can't find grf registers");
+ 
+-	dfi->regmap_pmu = syscon_node_to_regmap(node);
+-	of_node_put(node);
+-	if (IS_ERR(dfi->regmap_pmu))
+-		return PTR_ERR(dfi->regmap_pmu);
++		dfi->regmap_grf = syscon_node_to_regmap(node);
++		of_node_put(node);
++		if (IS_ERR(dfi->regmap_grf))
++			return PTR_ERR(dfi->regmap_grf);
++	}
++
++	if (soc_init == rk3399_dfi_init ||
++	    soc_init == rk3568_dfi_init ||
++	    soc_init == rk3588_dfi_init) {
++		node = of_parse_phandle(np, "rockchip,pmu", 0);
++		if (!node)
++			return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
++
++		dfi->regmap_pmu = syscon_node_to_regmap(node);
++		of_node_put(node);
++		if (IS_ERR(dfi->regmap_pmu))
++			return PTR_ERR(dfi->regmap_pmu);
++	}
+ 
+ 	dfi->dev = dev;
+ 	mutex_init(&dfi->mutex);
+@@ -818,6 +879,8 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
++	dev_notice(dfi->dev, "dfi initialized, dram type: 0x%x, channels: %d\n", dfi->ddr_type, dfi->max_channels);
++
+ 	platform_set_drvdata(pdev, dfi);
+ 
+ 	return 0;
+
+diff --git a/include/soc/rockchip/rk3228_grf.h b/include/soc/rockchip/rk3228_grf.h
+new file mode 100644
+index 000000000000..e37406814fad
+--- /dev/null
++++ b/include/soc/rockchip/rk3228_grf.h
+@@ -0,0 +1,14 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Rockchip General Register Files definitions for RK3228
++ *
++ * Author: Paolo Sabatino <paolo.sabatino@gmail.com>
++ */
++
++#ifndef __SOC_RK3228_GRF_H
++#define __SOC_RK3228_GRF_H
++
++#define RK3228_GRF_OS_REG2		0x5d0
++#define RK3228_GRF_OS_REG2_DDRTYPE	GENMASK(15, 13)
++
++#endif
+
+diff --git a/include/soc/rockchip/rk3328_grf.h b/include/soc/rockchip/rk3328_grf.h
+new file mode 100644
+index 000000000000..bf6d209be7e6
+--- /dev/null
++++ b/include/soc/rockchip/rk3328_grf.h
+@@ -0,0 +1,14 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Rockchip General Register Files definitions for RK3328
++ *
++ * Author: Paolo Sabatino <paolo.sabatino@gmail.com>
++ */
++
++#ifndef __SOC_RK3328_GRF_H
++#define __SOC_RK3328_GRF_H
++
++#define RK3328_GRF_OS_REG2		0x5d0
++#define RK3328_GRF_OS_REG2_DDRTYPE	GENMASK(15, 13)
++
++#endif
+
+diff --git a/drivers/devfreq/rk3328_dmc.c b/drivers/devfreq/rk3328_dmc.c
+new file mode 100644
+index 000000000000..7665526f0863
+--- /dev/null
++++ b/drivers/devfreq/rk3328_dmc.c
+@@ -0,0 +1,836 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
++ * Author: Lin Huang <hl@rock-chips.com>
++ */
++
++#include <linux/arm-smccc.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/devfreq.h>
++#include <linux/devfreq-event.h>
++#include <linux/devfreq_cooling.h>
++#include <linux/interrupt.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_opp.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++#include <linux/rwsem.h>
++#include <linux/suspend.h>
++
++#include <soc/rockchip/rockchip_sip.h>
++
++#define DTS_PAR_OFFSET		(4096)
++
++struct share_params {
++	u32 hz;
++	u32 lcdc_type;
++	u32 vop;
++	u32 vop_dclk_mode;
++	u32 sr_idle_en;
++	u32 addr_mcu_el3;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag1;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag0;
++	u32 complt_hwirq;
++	/* if need, add parameter after */
++};
++
++static struct share_params *ddr_psci_param;
++
++/* hope this define can adapt all future platform */
++static const char * const rk3328_dts_timing[] = {
++	"ddr3_speed_bin",
++	"ddr4_speed_bin",
++	"pd_idle",
++	"sr_idle",
++	"sr_mc_gate_idle",
++	"srpd_lite_idle",
++	"standby_idle",
++
++	"auto_pd_dis_freq",
++	"auto_sr_dis_freq",
++	"ddr3_dll_dis_freq",
++	"ddr4_dll_dis_freq",
++	"phy_dll_dis_freq",
++
++	"ddr3_odt_dis_freq",
++	"phy_ddr3_odt_dis_freq",
++	"ddr3_drv",
++	"ddr3_odt",
++	"phy_ddr3_ca_drv",
++	"phy_ddr3_ck_drv",
++	"phy_ddr3_dq_drv",
++	"phy_ddr3_odt",
++
++	"lpddr3_odt_dis_freq",
++	"phy_lpddr3_odt_dis_freq",
++	"lpddr3_drv",
++	"lpddr3_odt",
++	"phy_lpddr3_ca_drv",
++	"phy_lpddr3_ck_drv",
++	"phy_lpddr3_dq_drv",
++	"phy_lpddr3_odt",
++
++	"lpddr4_odt_dis_freq",
++	"phy_lpddr4_odt_dis_freq",
++	"lpddr4_drv",
++	"lpddr4_dq_odt",
++	"lpddr4_ca_odt",
++	"phy_lpddr4_ca_drv",
++	"phy_lpddr4_ck_cs_drv",
++	"phy_lpddr4_dq_drv",
++	"phy_lpddr4_odt",
++
++	"ddr4_odt_dis_freq",
++	"phy_ddr4_odt_dis_freq",
++	"ddr4_drv",
++	"ddr4_odt",
++	"phy_ddr4_ca_drv",
++	"phy_ddr4_ck_drv",
++	"phy_ddr4_dq_drv",
++	"phy_ddr4_odt",
++};
++
++static const char * const rk3328_dts_ca_timing[] = {
++	"ddr3a1_ddr4a9_de-skew",
++	"ddr3a0_ddr4a10_de-skew",
++	"ddr3a3_ddr4a6_de-skew",
++	"ddr3a2_ddr4a4_de-skew",
++	"ddr3a5_ddr4a8_de-skew",
++	"ddr3a4_ddr4a5_de-skew",
++	"ddr3a7_ddr4a11_de-skew",
++	"ddr3a6_ddr4a7_de-skew",
++	"ddr3a9_ddr4a0_de-skew",
++	"ddr3a8_ddr4a13_de-skew",
++	"ddr3a11_ddr4a3_de-skew",
++	"ddr3a10_ddr4cs0_de-skew",
++	"ddr3a13_ddr4a2_de-skew",
++	"ddr3a12_ddr4ba1_de-skew",
++	"ddr3a15_ddr4odt0_de-skew",
++	"ddr3a14_ddr4a1_de-skew",
++	"ddr3ba1_ddr4a15_de-skew",
++	"ddr3ba0_ddr4bg0_de-skew",
++	"ddr3ras_ddr4cke_de-skew",
++	"ddr3ba2_ddr4ba0_de-skew",
++	"ddr3we_ddr4bg1_de-skew",
++	"ddr3cas_ddr4a12_de-skew",
++	"ddr3ckn_ddr4ckn_de-skew",
++	"ddr3ckp_ddr4ckp_de-skew",
++	"ddr3cke_ddr4a16_de-skew",
++	"ddr3odt0_ddr4a14_de-skew",
++	"ddr3cs0_ddr4act_de-skew",
++	"ddr3reset_ddr4reset_de-skew",
++	"ddr3cs1_ddr4cs1_de-skew",
++	"ddr3odt1_ddr4odt1_de-skew",
++};
++
++static const char * const rk3328_dts_cs0_timing[] = {
++	"cs0_dm0_rx_de-skew",
++	"cs0_dm0_tx_de-skew",
++	"cs0_dq0_rx_de-skew",
++	"cs0_dq0_tx_de-skew",
++	"cs0_dq1_rx_de-skew",
++	"cs0_dq1_tx_de-skew",
++	"cs0_dq2_rx_de-skew",
++	"cs0_dq2_tx_de-skew",
++	"cs0_dq3_rx_de-skew",
++	"cs0_dq3_tx_de-skew",
++	"cs0_dq4_rx_de-skew",
++	"cs0_dq4_tx_de-skew",
++	"cs0_dq5_rx_de-skew",
++	"cs0_dq5_tx_de-skew",
++	"cs0_dq6_rx_de-skew",
++	"cs0_dq6_tx_de-skew",
++	"cs0_dq7_rx_de-skew",
++	"cs0_dq7_tx_de-skew",
++	"cs0_dqs0_rx_de-skew",
++	"cs0_dqs0p_tx_de-skew",
++	"cs0_dqs0n_tx_de-skew",
++
++	"cs0_dm1_rx_de-skew",
++	"cs0_dm1_tx_de-skew",
++	"cs0_dq8_rx_de-skew",
++	"cs0_dq8_tx_de-skew",
++	"cs0_dq9_rx_de-skew",
++	"cs0_dq9_tx_de-skew",
++	"cs0_dq10_rx_de-skew",
++	"cs0_dq10_tx_de-skew",
++	"cs0_dq11_rx_de-skew",
++	"cs0_dq11_tx_de-skew",
++	"cs0_dq12_rx_de-skew",
++	"cs0_dq12_tx_de-skew",
++	"cs0_dq13_rx_de-skew",
++	"cs0_dq13_tx_de-skew",
++	"cs0_dq14_rx_de-skew",
++	"cs0_dq14_tx_de-skew",
++	"cs0_dq15_rx_de-skew",
++	"cs0_dq15_tx_de-skew",
++	"cs0_dqs1_rx_de-skew",
++	"cs0_dqs1p_tx_de-skew",
++	"cs0_dqs1n_tx_de-skew",
++
++	"cs0_dm2_rx_de-skew",
++	"cs0_dm2_tx_de-skew",
++	"cs0_dq16_rx_de-skew",
++	"cs0_dq16_tx_de-skew",
++	"cs0_dq17_rx_de-skew",
++	"cs0_dq17_tx_de-skew",
++	"cs0_dq18_rx_de-skew",
++	"cs0_dq18_tx_de-skew",
++	"cs0_dq19_rx_de-skew",
++	"cs0_dq19_tx_de-skew",
++	"cs0_dq20_rx_de-skew",
++	"cs0_dq20_tx_de-skew",
++	"cs0_dq21_rx_de-skew",
++	"cs0_dq21_tx_de-skew",
++	"cs0_dq22_rx_de-skew",
++	"cs0_dq22_tx_de-skew",
++	"cs0_dq23_rx_de-skew",
++	"cs0_dq23_tx_de-skew",
++	"cs0_dqs2_rx_de-skew",
++	"cs0_dqs2p_tx_de-skew",
++	"cs0_dqs2n_tx_de-skew",
++
++	"cs0_dm3_rx_de-skew",
++	"cs0_dm3_tx_de-skew",
++	"cs0_dq24_rx_de-skew",
++	"cs0_dq24_tx_de-skew",
++	"cs0_dq25_rx_de-skew",
++	"cs0_dq25_tx_de-skew",
++	"cs0_dq26_rx_de-skew",
++	"cs0_dq26_tx_de-skew",
++	"cs0_dq27_rx_de-skew",
++	"cs0_dq27_tx_de-skew",
++	"cs0_dq28_rx_de-skew",
++	"cs0_dq28_tx_de-skew",
++	"cs0_dq29_rx_de-skew",
++	"cs0_dq29_tx_de-skew",
++	"cs0_dq30_rx_de-skew",
++	"cs0_dq30_tx_de-skew",
++	"cs0_dq31_rx_de-skew",
++	"cs0_dq31_tx_de-skew",
++	"cs0_dqs3_rx_de-skew",
++	"cs0_dqs3p_tx_de-skew",
++	"cs0_dqs3n_tx_de-skew",
++};
++
++static const char * const rk3328_dts_cs1_timing[] = {
++	"cs1_dm0_rx_de-skew",
++	"cs1_dm0_tx_de-skew",
++	"cs1_dq0_rx_de-skew",
++	"cs1_dq0_tx_de-skew",
++	"cs1_dq1_rx_de-skew",
++	"cs1_dq1_tx_de-skew",
++	"cs1_dq2_rx_de-skew",
++	"cs1_dq2_tx_de-skew",
++	"cs1_dq3_rx_de-skew",
++	"cs1_dq3_tx_de-skew",
++	"cs1_dq4_rx_de-skew",
++	"cs1_dq4_tx_de-skew",
++	"cs1_dq5_rx_de-skew",
++	"cs1_dq5_tx_de-skew",
++	"cs1_dq6_rx_de-skew",
++	"cs1_dq6_tx_de-skew",
++	"cs1_dq7_rx_de-skew",
++	"cs1_dq7_tx_de-skew",
++	"cs1_dqs0_rx_de-skew",
++	"cs1_dqs0p_tx_de-skew",
++	"cs1_dqs0n_tx_de-skew",
++
++	"cs1_dm1_rx_de-skew",
++	"cs1_dm1_tx_de-skew",
++	"cs1_dq8_rx_de-skew",
++	"cs1_dq8_tx_de-skew",
++	"cs1_dq9_rx_de-skew",
++	"cs1_dq9_tx_de-skew",
++	"cs1_dq10_rx_de-skew",
++	"cs1_dq10_tx_de-skew",
++	"cs1_dq11_rx_de-skew",
++	"cs1_dq11_tx_de-skew",
++	"cs1_dq12_rx_de-skew",
++	"cs1_dq12_tx_de-skew",
++	"cs1_dq13_rx_de-skew",
++	"cs1_dq13_tx_de-skew",
++	"cs1_dq14_rx_de-skew",
++	"cs1_dq14_tx_de-skew",
++	"cs1_dq15_rx_de-skew",
++	"cs1_dq15_tx_de-skew",
++	"cs1_dqs1_rx_de-skew",
++	"cs1_dqs1p_tx_de-skew",
++	"cs1_dqs1n_tx_de-skew",
++
++	"cs1_dm2_rx_de-skew",
++	"cs1_dm2_tx_de-skew",
++	"cs1_dq16_rx_de-skew",
++	"cs1_dq16_tx_de-skew",
++	"cs1_dq17_rx_de-skew",
++	"cs1_dq17_tx_de-skew",
++	"cs1_dq18_rx_de-skew",
++	"cs1_dq18_tx_de-skew",
++	"cs1_dq19_rx_de-skew",
++	"cs1_dq19_tx_de-skew",
++	"cs1_dq20_rx_de-skew",
++	"cs1_dq20_tx_de-skew",
++	"cs1_dq21_rx_de-skew",
++	"cs1_dq21_tx_de-skew",
++	"cs1_dq22_rx_de-skew",
++	"cs1_dq22_tx_de-skew",
++	"cs1_dq23_rx_de-skew",
++	"cs1_dq23_tx_de-skew",
++	"cs1_dqs2_rx_de-skew",
++	"cs1_dqs2p_tx_de-skew",
++	"cs1_dqs2n_tx_de-skew",
++
++	"cs1_dm3_rx_de-skew",
++	"cs1_dm3_tx_de-skew",
++	"cs1_dq24_rx_de-skew",
++	"cs1_dq24_tx_de-skew",
++	"cs1_dq25_rx_de-skew",
++	"cs1_dq25_tx_de-skew",
++	"cs1_dq26_rx_de-skew",
++	"cs1_dq26_tx_de-skew",
++	"cs1_dq27_rx_de-skew",
++	"cs1_dq27_tx_de-skew",
++	"cs1_dq28_rx_de-skew",
++	"cs1_dq28_tx_de-skew",
++	"cs1_dq29_rx_de-skew",
++	"cs1_dq29_tx_de-skew",
++	"cs1_dq30_rx_de-skew",
++	"cs1_dq30_tx_de-skew",
++	"cs1_dq31_rx_de-skew",
++	"cs1_dq31_tx_de-skew",
++	"cs1_dqs3_rx_de-skew",
++	"cs1_dqs3p_tx_de-skew",
++	"cs1_dqs3n_tx_de-skew",
++};
++
++struct rk3328_ddr_dts_config_timing {
++	unsigned int ddr3_speed_bin;
++	unsigned int ddr4_speed_bin;
++	unsigned int pd_idle;
++	unsigned int sr_idle;
++	unsigned int sr_mc_gate_idle;
++	unsigned int srpd_lite_idle;
++	unsigned int standby_idle;
++
++	unsigned int auto_pd_dis_freq;
++	unsigned int auto_sr_dis_freq;
++	/* for ddr3 only */
++	unsigned int ddr3_dll_dis_freq;
++	/* for ddr4 only */
++	unsigned int ddr4_dll_dis_freq;
++	unsigned int phy_dll_dis_freq;
++
++	unsigned int ddr3_odt_dis_freq;
++	unsigned int phy_ddr3_odt_dis_freq;
++	unsigned int ddr3_drv;
++	unsigned int ddr3_odt;
++	unsigned int phy_ddr3_ca_drv;
++	unsigned int phy_ddr3_ck_drv;
++	unsigned int phy_ddr3_dq_drv;
++	unsigned int phy_ddr3_odt;
++
++	unsigned int lpddr3_odt_dis_freq;
++	unsigned int phy_lpddr3_odt_dis_freq;
++	unsigned int lpddr3_drv;
++	unsigned int lpddr3_odt;
++	unsigned int phy_lpddr3_ca_drv;
++	unsigned int phy_lpddr3_ck_drv;
++	unsigned int phy_lpddr3_dq_drv;
++	unsigned int phy_lpddr3_odt;
++
++	unsigned int lpddr4_odt_dis_freq;
++	unsigned int phy_lpddr4_odt_dis_freq;
++	unsigned int lpddr4_drv;
++	unsigned int lpddr4_dq_odt;
++	unsigned int lpddr4_ca_odt;
++	unsigned int phy_lpddr4_ca_drv;
++	unsigned int phy_lpddr4_ck_cs_drv;
++	unsigned int phy_lpddr4_dq_drv;
++	unsigned int phy_lpddr4_odt;
++
++	unsigned int ddr4_odt_dis_freq;
++	unsigned int phy_ddr4_odt_dis_freq;
++	unsigned int ddr4_drv;
++	unsigned int ddr4_odt;
++	unsigned int phy_ddr4_ca_drv;
++	unsigned int phy_ddr4_ck_drv;
++	unsigned int phy_ddr4_dq_drv;
++	unsigned int phy_ddr4_odt;
++
++	unsigned int ca_skew[15];
++	unsigned int cs0_skew[44];
++	unsigned int cs1_skew[44];
++
++	unsigned int available;
++};
++
++struct rk3328_ddr_de_skew_setting {
++	unsigned int ca_de_skew[30];
++	unsigned int cs0_de_skew[84];
++	unsigned int cs1_de_skew[84];
++};
++
++struct rk3328_devfreq {
++	struct devfreq *devfreq;
++	struct thermal_cooling_device *cooling;
++};
++
++struct rk3328_dmcfreq {
++	struct device *dev;
++	//struct devfreq *devfreq;
++	struct devfreq_simple_ondemand_data ondemand_data;
++	struct clk *dmc_clk;
++	struct devfreq_event_dev *edev;
++	struct mutex lock;
++	struct regulator *vdd_center;
++	struct rk3328_devfreq devfreq;
++	unsigned long rate, target_rate;
++	unsigned long volt, target_volt;
++
++	int (*set_auto_self_refresh)(u32 en);
++};
++
++static void
++rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew,
++				  struct rk3328_ddr_dts_config_timing *tim)
++{
++	u32 n;
++	u32 offset;
++	u32 shift;
++
++	memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));
++	memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));
++	memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));
++
++	/* CA de-skew */
++	for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) {
++		offset = n / 2;
++		shift = n % 2;
++		/* 0 => 4; 1 => 0 */
++		shift = (shift == 0) ? 4 : 0;
++		tim->ca_skew[offset] &= ~(0xf << shift);
++		tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);
++	}
++
++	/* CS0 data de-skew */
++	for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) {
++		offset = ((n / 21) * 11) + ((n % 21) / 2);
++		shift = ((n % 21) % 2);
++		if ((n % 21) == 20)
++			shift = 0;
++		else
++			/* 0 => 4; 1 => 0 */
++			shift = (shift == 0) ? 4 : 0;
++		tim->cs0_skew[offset] &= ~(0xf << shift);
++		tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);
++	}
++
++	/* CS1 data de-skew */
++	for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) {
++		offset = ((n / 21) * 11) + ((n % 21) / 2);
++		shift = ((n % 21) % 2);
++		if ((n % 21) == 20)
++			shift = 0;
++		else
++			/* 0 => 4; 1 => 0 */
++			shift = (shift == 0) ? 4 : 0;
++		tim->cs1_skew[offset] &= ~(0xf << shift);
++		tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);
++	}
++}
++
++static void of_get_rk3328_timings(struct device *dev,
++				  struct device_node *np, uint32_t *timing)
++{
++	struct device_node *np_tim;
++	u32 *p;
++	struct rk3328_ddr_dts_config_timing *dts_timing;
++	struct rk3328_ddr_de_skew_setting *de_skew;
++	int ret = 0;
++	u32 i;
++
++	dts_timing =
++		(struct rk3328_ddr_dts_config_timing *)(timing +
++							DTS_PAR_OFFSET / 4);
++
++	np_tim = of_parse_phandle(np, "ddr_timing", 0);
++	if (!np_tim) {
++		ret = -EINVAL;
++		goto end;
++	}
++	de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL);
++	if (!de_skew) {
++		ret = -ENOMEM;
++		goto end;
++	}
++
++	p = (u32 *)dts_timing;
++	for (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) {
++		ret |= of_property_read_u32(np_tim, rk3328_dts_timing[i],
++					p + i);
++	}
++	p = (u32 *)de_skew->ca_de_skew;
++	for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) {
++		ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i],
++					p + i);
++	}
++	p = (u32 *)de_skew->cs0_de_skew;
++	for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) {
++		ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i],
++					p + i);
++	}
++	p = (u32 *)de_skew->cs1_de_skew;
++	for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) {
++		ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i],
++					p + i);
++	}
++	if (!ret)
++		rk3328_de_skew_setting_2_register(de_skew, dts_timing);
++
++	kfree(de_skew);
++end:
++	if (!ret) {
++		dts_timing->available = 1;
++	} else {
++		dts_timing->available = 0;
++		dev_err(dev, "of_get_ddr_timings: fail\n");
++	}
++
++	of_node_put(np_tim);
++}
++
++static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
++{
++	struct arm_smccc_res res;
++
++	ddr_psci_param->sr_idle_en = en;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR,
++		      0, 0, 0, 0, &res);
++
++	return res.a0;
++}
++
++static int rk3328_dmc_init(struct platform_device *pdev,
++			   struct rk3328_dmcfreq *dmcfreq)
++{
++	struct arm_smccc_res res;
++	u32 size, page_num;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION,
++		      0, 0, 0, 0, &res);
++	if (res.a0 || (res.a1 < 0x101)) {
++		dev_err(&pdev->dev,
++			"trusted firmware need to update or is invalid\n");
++		return -ENXIO;
++	}
++
++	dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1);
++
++	/*
++	 * first 4KB is used for interface parameters
++	 * after 4KB * N is dts parameters
++	 */
++	size = sizeof(struct rk3328_ddr_dts_config_timing);
++	page_num = DIV_ROUND_UP(size, 4096) + 1;
++
++	arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
++		      page_num, SHARE_PAGE_TYPE_DDR, 0,
++		      0, 0, 0, 0, &res);
++	if (res.a0 != 0) {
++		dev_err(&pdev->dev, "no ATF memory for init\n");
++		return -ENOMEM;
++	}
++
++	ddr_psci_param = ioremap(res.a1, page_num << 12);
++	of_get_rk3328_timings(&pdev->dev, pdev->dev.of_node,
++			      (uint32_t *)ddr_psci_param);
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT,
++		      0, 0, 0, 0, &res);
++	if (res.a0) {
++		dev_err(&pdev->dev, "Rockchip dram init error %lx\n", res.a0);
++		return -ENOMEM;
++	}
++
++	dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
++
++	return 0;
++}
++
++static int rk3328_dmcfreq_target(struct device *dev, unsigned long *freq,
++				 u32 flags)
++{
++	struct rk3328_dmcfreq *rdev = dev_get_drvdata(dev);
++	struct dev_pm_opp *opp;
++	int err;
++
++	opp = devfreq_recommended_opp(dev, freq, flags);
++	if (IS_ERR(opp))
++		return PTR_ERR(opp);
++	dev_pm_opp_put(opp);
++
++	err = dev_pm_opp_set_rate(dev, *freq);
++	if (err)
++		return err;
++
++	rdev->rate = *freq;
++
++	return 0;
++}
++
++static int rk3328_dmcfreq_get_dev_status(struct device *dev,
++					 struct devfreq_dev_status *stat)
++{
++	struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
++	struct devfreq_event_data edata;
++	int ret = 0;
++
++	ret = devfreq_event_get_event(dmcfreq->edev, &edata);
++	if (ret < 0)
++		return ret;
++
++	stat->current_frequency = dmcfreq->rate;
++	stat->busy_time = edata.load_count;
++	stat->total_time = edata.total_count;
++
++	return ret;
++}
++
++static int rk3328_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
++{
++	struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
++
++	*freq = dmcfreq->rate;
++
++	return 0;
++}
++
++static struct devfreq_dev_profile rk3328_devfreq_dmc_profile = {
++	.polling_ms	= 50,
++	.target		= rk3328_dmcfreq_target,
++	.get_dev_status	= rk3328_dmcfreq_get_dev_status,
++	.get_cur_freq	= rk3328_dmcfreq_get_cur_freq,
++};
++
++static __maybe_unused int rk3328_dmcfreq_suspend(struct device *dev)
++{
++	struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
++	int ret = 0;
++
++	ret = devfreq_event_disable_edev(dmcfreq->edev);
++	if (ret < 0) {
++		dev_err(dev, "failed to disable the devfreq-event devices\n");
++		return ret;
++	}
++
++	ret = devfreq_suspend_device(dmcfreq->devfreq.devfreq);
++	if (ret < 0) {
++		dev_err(dev, "failed to suspend the devfreq devices\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static __maybe_unused int rk3328_dmcfreq_resume(struct device *dev)
++{
++	struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
++	int ret = 0;
++
++	ret = devfreq_event_enable_edev(dmcfreq->edev);
++	if (ret < 0) {
++		dev_err(dev, "failed to enable the devfreq-event devices\n");
++		return ret;
++	}
++
++	ret = devfreq_resume_device(dmcfreq->devfreq.devfreq);
++	if (ret < 0) {
++		dev_err(dev, "failed to resume the devfreq devices\n");
++		return ret;
++	}
++	return ret;
++}
++
++static SIMPLE_DEV_PM_OPS(rk3328_dmcfreq_pm, rk3328_dmcfreq_suspend,
++			 rk3328_dmcfreq_resume);
++
++void rk3328_devfreq_fini(struct rk3328_dmcfreq *rdev)
++{
++	struct rk3328_devfreq *devfreq = &rdev->devfreq;
++
++	if (devfreq->cooling) {
++		devfreq_cooling_unregister(devfreq->cooling);
++		devfreq->cooling = NULL;
++	}
++
++	if (devfreq->devfreq) {
++		devm_devfreq_remove_device(rdev->dev, devfreq->devfreq);
++		devfreq->devfreq = NULL;
++	}
++
++}
++
++int rk3328_devfreq_init(struct rk3328_dmcfreq *rdev)
++{
++	struct thermal_cooling_device *cooling;
++	struct device *dev = rdev->dev;
++	struct devfreq *devfreq;
++	struct rk3328_devfreq *rdevfreq = &rdev->devfreq;
++	const char *regulator_names[] = { "center", NULL };
++	
++	struct dev_pm_opp *opp;
++	unsigned long cur_freq;
++	int ret;
++
++	if (!device_property_present(dev, "operating-points-v2"))
++		/* Optional, continue without devfreq */
++		return 0;
++
++	ret= devm_pm_opp_set_clkname(dev, "dmc_clk");
++	if (ret)
++		goto err_fini;
++
++	ret = devm_pm_opp_set_regulators(dev, regulator_names);
++	
++	if (ret) {
++		/* Continue if the optional regulator is missing */
++		if (ret != -ENODEV)
++			goto err_fini;
++	}
++
++	ret = devm_pm_opp_of_add_table(dev);
++	if (ret)
++		goto err_fini;
++
++	cur_freq = 0;
++
++	opp = devfreq_recommended_opp(dev, &cur_freq, 0);
++	if (IS_ERR(opp)) {
++		ret = PTR_ERR(opp);
++		goto err_fini;
++	}
++
++	rk3328_devfreq_dmc_profile.initial_freq = cur_freq;
++	dev_pm_opp_put(opp);
++
++	rdev->ondemand_data.upthreshold = 15;
++	rdev->ondemand_data.downdifferential = 5;
++
++	devfreq = devm_devfreq_add_device(dev, &rk3328_devfreq_dmc_profile,
++					  DEVFREQ_GOV_SIMPLE_ONDEMAND, &rdev->ondemand_data);
++	if (IS_ERR(devfreq)) {
++		dev_err(dev, "Couldn't initialize rk3328-dmc devfreq\n");
++		ret = PTR_ERR(devfreq);
++		goto err_fini;
++	}
++
++	rdevfreq->devfreq = devfreq;
++
++	cooling = of_devfreq_cooling_register(dev->of_node, devfreq);
++	if (IS_ERR(cooling))
++		dev_warn(dev, "Failed to register cooling device\n");
++	else
++		rdevfreq->cooling = cooling;
++
++	return 0;
++
++err_fini:
++	rk3328_devfreq_fini(rdev);
++	return ret;
++}
++
++static int rk3328_dmcfreq_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct rk3328_dmcfreq *data;
++	int ret;
++
++	data = devm_kzalloc(dev, sizeof(struct rk3328_dmcfreq), GFP_KERNEL);
++	if (!data)
++		return -ENOMEM;
++
++	mutex_init(&data->lock);
++
++	data->dev = dev;
++
++	data->dmc_clk = devm_clk_get(dev, "dmc_clk");
++	if (IS_ERR(data->dmc_clk)) {
++		if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++
++		dev_err(dev, "Cannot get the clk dmc_clk\n");
++		return PTR_ERR(data->dmc_clk);
++	}
++
++	data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
++	if (IS_ERR(data->edev))
++		return -EPROBE_DEFER;
++
++	ret = devfreq_event_enable_edev(data->edev);
++	if (ret < 0) {
++		dev_err(dev, "failed to enable devfreq-event devices\n");
++		return ret;
++	}
++
++	ret = rk3328_dmc_init(pdev, data);
++	if (ret)
++		return ret;
++
++	ret = rk3328_devfreq_init(data);
++	if (ret)
++		return ret;
++
++	platform_set_drvdata(pdev, data);
++
++	return 0;
++
++}
++
++static int rk3328_dmcfreq_remove(struct platform_device *pdev)
++{
++	struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
++
++	/*
++	 * Before remove the opp table we need to unregister the opp notifier.
++	 */
++	rk3328_devfreq_fini(dmcfreq);
++
++	return 0;
++}
++
++static const struct of_device_id rk3328dmc_devfreq_of_match[] = {
++	{ .compatible = "rockchip,rk3328-dmc" },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, rk3328dmc_devfreq_of_match);
++
++static struct platform_driver rk3328_dmcfreq_driver = {
++	.probe	= rk3328_dmcfreq_probe,
++	.remove = rk3328_dmcfreq_remove,
++	.driver = {
++		.name	= "rk3328-dmc",
++		.pm	= &rk3328_dmcfreq_pm,
++		.of_match_table = rk3328dmc_devfreq_of_match,
++	},
++};
++module_platform_driver(rk3328_dmcfreq_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
++MODULE_DESCRIPTION("RK3328 dmcfreq driver with devfreq framework");
+diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h
+new file mode 100644
+index 000000000000..b065432e7793
+--- /dev/null
++++ b/include/dt-bindings/clock/rockchip-ddr.h
+@@ -0,0 +1,63 @@
++/*
++ *
++ * Copyright (C) 2017 ROCKCHIP, Inc.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
++#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
++
++#define DDR2_DEFAULT	(0)
++
++#define DDR3_800D	(0)	/* 5-5-5 */
++#define DDR3_800E	(1)	/* 6-6-6 */
++#define DDR3_1066E	(2)	/* 6-6-6 */
++#define DDR3_1066F	(3)	/* 7-7-7 */
++#define DDR3_1066G	(4)	/* 8-8-8 */
++#define DDR3_1333F	(5)	/* 7-7-7 */
++#define DDR3_1333G	(6)	/* 8-8-8 */
++#define DDR3_1333H	(7)	/* 9-9-9 */
++#define DDR3_1333J	(8)	/* 10-10-10 */
++#define DDR3_1600G	(9)	/* 8-8-8 */
++#define DDR3_1600H	(10)	/* 9-9-9 */
++#define DDR3_1600J	(11)	/* 10-10-10 */
++#define DDR3_1600K	(12)	/* 11-11-11 */
++#define DDR3_1866J	(13)	/* 10-10-10 */
++#define DDR3_1866K	(14)	/* 11-11-11 */
++#define DDR3_1866L	(15)	/* 12-12-12 */
++#define DDR3_1866M	(16)	/* 13-13-13 */
++#define DDR3_2133K	(17)	/* 11-11-11 */
++#define DDR3_2133L	(18)	/* 12-12-12 */
++#define DDR3_2133M	(19)	/* 13-13-13 */
++#define DDR3_2133N	(20)	/* 14-14-14 */
++#define DDR3_DEFAULT	(21)
++#define DDR_DDR2	(22)
++#define DDR_LPDDR	(23)
++#define DDR_LPDDR2	(24)
++
++#define DDR4_1600J	(0)	/* 10-10-10 */
++#define DDR4_1600K	(1)	/* 11-11-11 */
++#define DDR4_1600L	(2)	/* 12-12-12 */
++#define DDR4_1866L	(3)	/* 12-12-12 */
++#define DDR4_1866M	(4)	/* 13-13-13 */
++#define DDR4_1866N	(5)	/* 14-14-14 */
++#define DDR4_2133N	(6)	/* 14-14-14 */
++#define DDR4_2133P	(7)	/* 15-15-15 */
++#define DDR4_2133R	(8)	/* 16-16-16 */
++#define DDR4_2400P	(9)	/* 15-15-15 */
++#define DDR4_2400R	(10)	/* 16-16-16 */
++#define DDR4_2400U	(11)	/* 18-18-18 */
++#define DDR4_DEFAULT	(12)
++
++#define PAUSE_CPU_STACK_SIZE	16
++
++#endif
+diff --git a/include/dt-bindings/memory/rk3328-dram.h b/include/dt-bindings/memory/rk3328-dram.h
+new file mode 100644
+index 000000000000..171f41c256d3
+--- /dev/null
++++ b/include/dt-bindings/memory/rk3328-dram.h
+@@ -0,0 +1,159 @@
++/*
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
++#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
++
++#define DDR3_DS_34ohm			(34)
++#define DDR3_DS_40ohm			(40)
++
++#define DDR3_ODT_DIS			(0)
++#define DDR3_ODT_40ohm			(40)
++#define DDR3_ODT_60ohm			(60)
++#define DDR3_ODT_120ohm			(120)
++
++#define LP2_DS_34ohm			(34)
++#define LP2_DS_40ohm			(40)
++#define LP2_DS_48ohm			(48)
++#define LP2_DS_60ohm			(60)
++#define LP2_DS_68_6ohm			(68)	/* optional */
++#define LP2_DS_80ohm			(80)
++#define LP2_DS_120ohm			(120)	/* optional */
++
++#define LP3_DS_34ohm			(34)
++#define LP3_DS_40ohm			(40)
++#define LP3_DS_48ohm			(48)
++#define LP3_DS_60ohm			(60)
++#define LP3_DS_80ohm			(80)
++#define LP3_DS_34D_40U			(3440)
++#define LP3_DS_40D_48U			(4048)
++#define LP3_DS_34D_48U			(3448)
++
++#define LP3_ODT_DIS			(0)
++#define LP3_ODT_60ohm			(60)
++#define LP3_ODT_120ohm			(120)
++#define LP3_ODT_240ohm			(240)
++
++#define LP4_PDDS_40ohm			(40)
++#define LP4_PDDS_48ohm			(48)
++#define LP4_PDDS_60ohm			(60)
++#define LP4_PDDS_80ohm			(80)
++#define LP4_PDDS_120ohm			(120)
++#define LP4_PDDS_240ohm			(240)
++
++#define LP4_DQ_ODT_40ohm		(40)
++#define LP4_DQ_ODT_48ohm		(48)
++#define LP4_DQ_ODT_60ohm		(60)
++#define LP4_DQ_ODT_80ohm		(80)
++#define LP4_DQ_ODT_120ohm		(120)
++#define LP4_DQ_ODT_240ohm		(240)
++#define LP4_DQ_ODT_DIS			(0)
++
++#define LP4_CA_ODT_40ohm		(40)
++#define LP4_CA_ODT_48ohm		(48)
++#define LP4_CA_ODT_60ohm		(60)
++#define LP4_CA_ODT_80ohm		(80)
++#define LP4_CA_ODT_120ohm		(120)
++#define LP4_CA_ODT_240ohm		(240)
++#define LP4_CA_ODT_DIS			(0)
++
++#define DDR4_DS_34ohm			(34)
++#define DDR4_DS_48ohm			(48)
++#define DDR4_RTT_NOM_DIS		(0)
++#define DDR4_RTT_NOM_60ohm		(60)
++#define DDR4_RTT_NOM_120ohm		(120)
++#define DDR4_RTT_NOM_40ohm		(40)
++#define DDR4_RTT_NOM_240ohm		(240)
++#define DDR4_RTT_NOM_48ohm		(48)
++#define DDR4_RTT_NOM_80ohm		(80)
++#define DDR4_RTT_NOM_34ohm		(34)
++
++#define PHY_DDR3_RON_RTT_DISABLE	(0)
++#define PHY_DDR3_RON_RTT_451ohm		(1)
++#define PHY_DDR3_RON_RTT_225ohm		(2)
++#define PHY_DDR3_RON_RTT_150ohm		(3)
++#define PHY_DDR3_RON_RTT_112ohm		(4)
++#define PHY_DDR3_RON_RTT_90ohm		(5)
++#define PHY_DDR3_RON_RTT_75ohm		(6)
++#define PHY_DDR3_RON_RTT_64ohm		(7)
++#define PHY_DDR3_RON_RTT_56ohm		(16)
++#define PHY_DDR3_RON_RTT_50ohm		(17)
++#define PHY_DDR3_RON_RTT_45ohm		(18)
++#define PHY_DDR3_RON_RTT_41ohm		(19)
++#define PHY_DDR3_RON_RTT_37ohm		(20)
++#define PHY_DDR3_RON_RTT_34ohm		(21)
++#define PHY_DDR3_RON_RTT_33ohm		(22)
++#define PHY_DDR3_RON_RTT_30ohm		(23)
++#define PHY_DDR3_RON_RTT_28ohm		(24)
++#define PHY_DDR3_RON_RTT_26ohm		(25)
++#define PHY_DDR3_RON_RTT_25ohm		(26)
++#define PHY_DDR3_RON_RTT_23ohm		(27)
++#define PHY_DDR3_RON_RTT_22ohm		(28)
++#define PHY_DDR3_RON_RTT_21ohm		(29)
++#define PHY_DDR3_RON_RTT_20ohm		(30)
++#define PHY_DDR3_RON_RTT_19ohm		(31)
++
++#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
++#define PHY_DDR4_LPDDR3_RON_RTT_480ohm	(1)
++#define PHY_DDR4_LPDDR3_RON_RTT_240ohm	(2)
++#define PHY_DDR4_LPDDR3_RON_RTT_160ohm	(3)
++#define PHY_DDR4_LPDDR3_RON_RTT_120ohm	(4)
++#define PHY_DDR4_LPDDR3_RON_RTT_96ohm	(5)
++#define PHY_DDR4_LPDDR3_RON_RTT_80ohm	(6)
++#define PHY_DDR4_LPDDR3_RON_RTT_68ohm	(7)
++#define PHY_DDR4_LPDDR3_RON_RTT_60ohm	(16)
++#define PHY_DDR4_LPDDR3_RON_RTT_53ohm	(17)
++#define PHY_DDR4_LPDDR3_RON_RTT_48ohm	(18)
++#define PHY_DDR4_LPDDR3_RON_RTT_43ohm	(19)
++#define PHY_DDR4_LPDDR3_RON_RTT_40ohm	(20)
++#define PHY_DDR4_LPDDR3_RON_RTT_37ohm	(21)
++#define PHY_DDR4_LPDDR3_RON_RTT_34ohm	(22)
++#define PHY_DDR4_LPDDR3_RON_RTT_32ohm	(23)
++#define PHY_DDR4_LPDDR3_RON_RTT_30ohm	(24)
++#define PHY_DDR4_LPDDR3_RON_RTT_28ohm	(25)
++#define PHY_DDR4_LPDDR3_RON_RTT_26ohm	(26)
++#define PHY_DDR4_LPDDR3_RON_RTT_25ohm	(27)
++#define PHY_DDR4_LPDDR3_RON_RTT_24ohm	(28)
++#define PHY_DDR4_LPDDR3_RON_RTT_22ohm	(29)
++#define PHY_DDR4_LPDDR3_RON_RTT_21ohm	(30)
++#define PHY_DDR4_LPDDR3_RON_RTT_20ohm	(31)
++
++#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/
+diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h
+index c46a9ae2a2ab..fa7e0a2d72cc 100644
+--- a/include/soc/rockchip/rockchip_sip.h
++++ b/include/soc/rockchip/rockchip_sip.h
+@@ -16,5 +16,16 @@
+ #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ	0x06
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM	0x07
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD	0x08
++#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION	0x08
++
++#define ROCKCHIP_SIP_SHARE_MEM			0x82000009
++
++/* Share mem page types */
++typedef enum {
++    SHARE_PAGE_TYPE_INVALID = 0,
++    SHARE_PAGE_TYPE_UARTDBG,
++    SHARE_PAGE_TYPE_DDR,
++    SHARE_PAGE_TYPE_MAX,
++} share_page_type_t;
+ 
+ #endif
+-- 
+Armbian
+
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3328-add-rga-node.patch b/patch/kernel/archive/rockchip64-6.10/rk3328-add-rga-node.patch
new file mode 100644
index 000000000000..076dc91a88f5
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3328-add-rga-node.patch
@@ -0,0 +1,37 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Thu, 21 Oct 2021 18:04:17 +0000
+Subject: rk3328: add RGA node
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index e3c8409c225f..3f7770d83748 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -783,6 +783,20 @@ vop_mmu: iommu@ff373f00 {
+ 		status = "disabled";
+ 	};
+ 
++	rga: rga@ff390000 {
++		compatible = "rockchip,rk3328-rga", "rockchip,rk3399-rga";
++		reg = <0x0 0xff390000 0x0 0x1000>;
++		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru ACLK_RGA>,
++			<&cru HCLK_RGA>,
++			<&cru SCLK_RGA>;
++		clock-names = "aclk", "hclk", "sclk";
++		resets = <&cru SRST_RGA>,
++			<&cru SRST_RGA_A>,
++			<&cru SRST_RGA_H>;
++		reset-names = "core", "axi", "ahb";
++	};
++
+ 	iep: iep@ff3a0000 {
+ 		compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep";
+ 		reg = <0x0 0xff3a0000 0x0 0x800>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-mali-opp-table.patch b/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-mali-opp-table.patch
new file mode 100644
index 000000000000..9785fdc721ed
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-mali-opp-table.patch
@@ -0,0 +1,48 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 25 Sep 2021 15:26:41 +0000
+Subject: gpu operating points
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 ++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 3f7770d83748..48c59e5ee235 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -684,6 +684,31 @@ gpu: gpu@ff300000 {
+ 		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+ 		clock-names = "bus", "core";
+ 		resets = <&cru SRST_GPU_A>;
++		operating-points-v2 = <&gpu_opp_table>;
++	};
++
++	gpu_opp_table: gpu-opp-table {
++		compatible = "operating-points-v2";
++
++		opp-200000000 {
++			opp-hz = /bits/ 64 <200000000>;
++			opp-microvolt = <1050000 950000 1200000>;
++		};
++
++		opp-300000000 {
++			opp-hz = /bits/ 64 <300000000>;
++			opp-microvolt = <1050000 950000 1200000>;
++		};
++
++		opp-400000000 {
++			opp-hz = /bits/ 64 <400000000>;
++			opp-microvolt = <1050000 950000 1200000>;
++		};
++
++		opp-500000000 {
++			opp-hz = /bits/ 64 <500000000>;
++			opp-microvolt = <1150000 950000 1200000>;
++		};
+ 	};
+ 
+ 	h265e_mmu: iommu@ff330200 {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-mmc-reset-properties.patch b/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-mmc-reset-properties.patch
new file mode 100644
index 000000000000..ff10e8be6ae8
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-mmc-reset-properties.patch
@@ -0,0 +1,43 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 25 Sep 2021 13:35:13 +0000
+Subject: mmc reset properties
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 48c59e5ee235..b2d517bf0082 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -993,6 +993,8 @@ sdmmc: mmc@ff500000 {
+ 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++		resets = <&cru SRST_MMC0>;
++		reset-names = "reset";
+ 		fifo-depth = <0x100>;
+ 		max-frequency = <150000000>;
+ 		status = "disabled";
+@@ -1005,6 +1007,8 @@ sdio: mmc@ff510000 {
+ 		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++		resets = <&cru SRST_SDIO>;
++		reset-names = "reset";
+ 		fifo-depth = <0x100>;
+ 		max-frequency = <150000000>;
+ 		status = "disabled";
+@@ -1017,6 +1021,8 @@ emmc: mmc@ff520000 {
+ 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++		resets = <&cru SRST_EMMC>;
++		reset-names = "reset";
+ 		fifo-depth = <0x100>;
+ 		max-frequency = <150000000>;
+ 		status = "disabled";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-sdmmc-ext-node.patch b/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-sdmmc-ext-node.patch
new file mode 100644
index 000000000000..e92c97144bf8
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-sdmmc-ext-node.patch
@@ -0,0 +1,37 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 25 Sep 2021 13:36:20 +0000
+Subject: sdmmc-ext node
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index b2d517bf0082..eb467c8586ab 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -1028,6 +1028,20 @@ emmc: mmc@ff520000 {
+ 		status = "disabled";
+ 	};
+ 
++	sdmmc_ext: dwmmc@ff5f0000 {
++		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
++		reg = <0x0 0xff5f0000 0x0 0x4000>;
++		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
++			 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
++		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++		fifo-depth = <0x100>;
++		max-frequency = <150000000>;
++		resets = <&cru SRST_SDMMCEXT>;
++		reset-names = "reset";
++		status = "disabled";
++	};
++
+ 	gmac2io: ethernet@ff540000 {
+ 		compatible = "rockchip,rk3328-gmac";
+ 		reg = <0x0 0xff540000 0x0 0x10000>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-spdif.patch b/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-spdif.patch
new file mode 100644
index 000000000000..fc4c48a3a910
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-spdif.patch
@@ -0,0 +1,128 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 26 Sep 2021 08:35:58 +0000
+Subject: [ARCHEOLOGY] rockchip64: tidy up rk3328 patches
+
+> X-Git-Archeology: > recovered message: > * remove 0-rever-rk3328.dtsi-.patch
+> X-Git-Archeology: > recovered message: > * split rk3328-dtsi-mmc-vdec-usb3-tweaks.patch into different specific patches (sdmmc-ext, mmc-reset, power domains, usb3 resets)
+> X-Git-Archeology: > recovered message: > * split rk3328-audio-and-renegade-supplies.patch into specific roc-cc audio and supplies patch and general rk3328 spdif patch
+> X-Git-Archeology: > recovered message: > * add "dtsi" infix to rk3328 patches that deal with dtsi files
+> X-Git-Archeology: > recovered message: > * add back mali gpu operating points patch
+> X-Git-Archeology: - Revision a71ef23575940b363e86a143d6ec781f95f1dbde: https://github.com/armbian/build/commit/a71ef23575940b363e86a143d6ec781f95f1dbde
+> X-Git-Archeology:   Date: Sun, 26 Sep 2021 08:35:58 +0000
+> X-Git-Archeology:   From: Paolo Sabatino <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64: tidy up rk3328 patches
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index eb467c8586ab..cb0c3fd179b4 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -195,6 +195,26 @@ psci {
+ 		method = "smc";
+ 	};
+ 
++	spdif_out: spdif-out {
++		compatible = "linux,spdif-dit";
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
++	spdif_sound: spdif-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "SPDIF";
++		status = "disabled";
++
++		simple-audio-card,cpu {
++			sound-dai = <&spdif>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&spdif_out>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+@@ -302,6 +322,10 @@ power: power-controller {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 
++			power-domain@RK3328_PD_GPU {
++				reg = <RK3328_PD_GPU>;
++				clocks = <&cru ACLK_GPU>;
++			};
+ 			power-domain@RK3328_PD_HEVC {
+ 				reg = <RK3328_PD_HEVC>;
+ 				#power-domain-cells = <0>;
+@@ -683,6 +707,7 @@ gpu: gpu@ff300000 {
+ 				  "ppmmu1";
+ 		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+ 		clock-names = "bus", "core";
++		power-domains = <&power RK3328_PD_GPU>;
+ 		resets = <&cru SRST_GPU_A>;
+ 		operating-points-v2 = <&gpu_opp_table>;
+ 	};
+@@ -925,6 +950,7 @@ cru: clock-controller@ff440000 {
+ 			<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
+ 			<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ 			<&cru HCLK_PERI>, <&cru PCLK_PERI>,
++			<&cru ACLK_GPU>,
+ 			<&cru SCLK_RTC32K>;
+ 		assigned-clock-parents =
+ 			<&cru HDMIPHY>, <&cru PLL_APLL>,
+@@ -946,6 +972,7 @@ cru: clock-controller@ff440000 {
+ 			<150000000>, <75000000>,
+ 			<75000000>, <150000000>,
+ 			<75000000>, <75000000>,
++			<500000000>,
+ 			<32768>;
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-usb3-reset-properties.patch b/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-usb3-reset-properties.patch
new file mode 100644
index 000000000000..fedb87415337
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3328-dtsi-usb3-reset-properties.patch
@@ -0,0 +1,25 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 25 Sep 2021 13:39:40 +0000
+Subject: usb3 reset properties
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index cb0c3fd179b4..3ff7408bf31b 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -1172,6 +1172,8 @@ usbdrd3: usb@ff600000 {
+ 			 <&cru ACLK_USB3OTG>;
+ 		clock-names = "ref_clk", "suspend_clk",
+ 			      "bus_clk";
++		resets = <&cru SRST_USB3OTG>;
++		reset-names = "usb3-otg";
+ 		dr_mode = "otg";
+ 		phy_type = "utmi_wide";
+ 		snps,dis-del-phy-power-chg-quirk;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3328-gpu-cooling-target.patch b/patch/kernel/archive/rockchip64-6.10/rk3328-gpu-cooling-target.patch
new file mode 100644
index 000000000000..902eb9ac94e3
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3328-gpu-cooling-target.patch
@@ -0,0 +1,37 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: tonymac32 <tonymckahan@gmail.com>
+Date: Wed, 4 Aug 2021 00:14:33 -0400
+Subject: rk3328-gpu-cooling-target
+
+Signed-off-by: tonymac32 <tonymckahan@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 3ff7408bf31b..94eae571006f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -565,6 +565,11 @@ map0 {
+ 							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ 					contribution = <4096>;
+ 				};
++				map1 {
++					trip = <&target>;
++					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++					contribution = <4096>;
++				};
+ 			};
+ 		};
+ 
+@@ -710,6 +715,7 @@ gpu: gpu@ff300000 {
+ 		power-domains = <&power RK3328_PD_GPU>;
+ 		resets = <&cru SRST_GPU_A>;
+ 		operating-points-v2 = <&gpu_opp_table>;
++		#cooling-cells = <2>;
+ 	};
+ 
+ 	gpu_opp_table: gpu-opp-table {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3328-roc-cc-add-missing-nodes.patch b/patch/kernel/archive/rockchip64-6.10/rk3328-roc-cc-add-missing-nodes.patch
new file mode 100644
index 000000000000..14ab270892cb
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3328-roc-cc-add-missing-nodes.patch
@@ -0,0 +1,79 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: tonymac32 <tonymckahan@gmail.com>
+Date: Sat, 28 Jan 2023 17:07:35 -0500
+Subject: rk3328-roc-cc add missing nodes
+
+Signed-off-by: tonymac32 <tonymckahan@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 32 ++++++++++
+ 1 file changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+old mode 100644
+new mode 100755
+index be5d064d6a93..c5ecfc3e581a
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -132,6 +132,14 @@ user_led: led-1 {
+ 			default-state = "off";
+ 		};
+ 	};
++
++	ir-receiver {
++		compatible = "gpio-ir-receiver";
++		gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
++		pinctrl-0 = <&ir_int>;
++		pinctrl-names = "default";
++	};
++
+ };
+ 
+ &analog_sound {
+@@ -202,6 +210,10 @@ &gmac2io {
+ 	status = "okay";
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_logic>;
++};
++
+ &hdmi {
+ 	status = "okay";
+ };
+@@ -344,6 +356,13 @@ &io_domains {
+ };
+ 
+ &pinctrl {
++
++	ir {
++		ir_int: ir-int {
++			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		pmic_int_l: pmic-int-l {
+ 			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+@@ -374,6 +393,19 @@ &sdmmc {
+ 	status = "okay";
+ };
+ 
++&spdif {
++	pinctrl-0 = <&spdifm0_tx>;
++	status = "okay";
++};
++
++&spdif_out {
++	status = "okay";
++};
++
++&spdif_sound {
++ 	status = "okay";
++};
++
+ &tsadc {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3399-add-sclk-i2sout-src-clock.patch b/patch/kernel/archive/rockchip64-6.10/rk3399-add-sclk-i2sout-src-clock.patch
new file mode 100644
index 000000000000..ca601a8c2305
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3399-add-sclk-i2sout-src-clock.patch
@@ -0,0 +1,98 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Piotr Szczepanik <piter75@gmail.com>
+Date: Sun, 5 Apr 2020 18:15:06 +0200
+Subject: [ARCHEOLOGY] Fixed sound from rt5651 on OrangePi 4 (#1870)
+
+> X-Git-Archeology: - Revision e14a61c229db1216fedc397e351c4bed15df820e: https://github.com/armbian/build/commit/e14a61c229db1216fedc397e351c4bed15df820e
+> X-Git-Archeology:   Date: Sun, 05 Apr 2020 18:15:06 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Fixed sound from rt5651 on OrangePi 4 (#1870)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ drivers/clk/rockchip/clk-rk3399.c      | 2 +-
+ include/dt-bindings/clock/rk3399-cru.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
+index 9ebd6c451b3d..4b9a3e1217aa 100644
+--- a/drivers/clk/rockchip/clk-rk3399.c
++++ b/drivers/clk/rockchip/clk-rk3399.c
+@@ -624,7 +624,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
+ 			RK3399_CLKGATE_CON(8), 11, GFLAGS),
+ 
+-	MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
++	MUX(SCLK_I2SOUT_SRC, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
+ 			RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
+ 	COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
+ 			RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
+diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
+index 39169d94a44e..8207557c1c5d 100644
+--- a/include/dt-bindings/clock/rk3399-cru.h
++++ b/include/dt-bindings/clock/rk3399-cru.h
+@@ -19,6 +19,7 @@
+ #define ARMCLKB				9
+ 
+ /* sclk gates (special clocks) */
++#define SCLK_I2SOUT_SRC			64
+ #define SCLK_I2C1			65
+ #define SCLK_I2C2			66
+ #define SCLK_I2C3			67
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3399-dmc-polling-rate.patch b/patch/kernel/archive/rockchip64-6.10/rk3399-dmc-polling-rate.patch
new file mode 100644
index 000000000000..54768827ab93
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3399-dmc-polling-rate.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Wed, 8 Mar 2023 11:12:41 +0100
+Subject: [ARCHEOLOGY] rockchip64: set poll rate 50ms for rk3399 dmc driver
+
+> X-Git-Archeology: - Revision 03a00c5ce49dadd0dd579980114b8595f144b763: https://github.com/armbian/build/commit/03a00c5ce49dadd0dd579980114b8595f144b763
+> X-Git-Archeology:   Date: Wed, 08 Mar 2023 11:12:41 +0100
+> X-Git-Archeology:   From: Paolo Sabatino <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64: set poll rate 50ms for rk3399 dmc driver
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ drivers/devfreq/rk3399_dmc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
+index daff40702615..62f4804134c2 100644
+--- a/drivers/devfreq/rk3399_dmc.c
++++ b/drivers/devfreq/rk3399_dmc.c
+@@ -430,7 +430,7 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
+ 	dev_pm_opp_put(opp);
+ 
+ 	data->profile = (struct devfreq_dev_profile) {
+-		.polling_ms	= 200,
++		.polling_ms	= 50,
+ 		.target		= rk3399_dmcfreq_target,
+ 		.get_dev_status	= rk3399_dmcfreq_get_dev_status,
+ 		.get_cur_freq	= rk3399_dmcfreq_get_cur_freq,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/archive/rockchip64-6.10/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch
new file mode 100644
index 000000000000..6304c4eff265
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch
@@ -0,0 +1,119 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Aditya Prayoga <aprayoga@users.noreply.github.com>
+Date: Fri, 22 Jan 2021 13:12:09 +0100
+Subject: [ARCHEOLOGY] Fix 2.5G Ethernet on Helios64 Mainline kernel (#2567)
+
+> X-Git-Archeology: > recovered message: > * rockchip64: Added XHCI HCD USB TRB ENT quirk
+> X-Git-Archeology: > recovered message: > On some xHCI controllers (e.g. Rockchip RK3399/RK3328/RK1808), they need
+> X-Git-Archeology: > recovered message: > to enable the ENT flag in the TRB data structure to force xHC to
+> X-Git-Archeology: > recovered message: > prefetch the next TRB of a TD.
+> X-Git-Archeology: > recovered message: > Enable the quirk on RK3399 through device tree node properties.
+> X-Git-Archeology: > recovered message: > Ported from Rockchip Linux 4.19
+> X-Git-Archeology: > recovered message: > * add to dev branch
+> X-Git-Archeology: - Revision 568d8472b3c2ab406fd3897e6b952c7a71a8165b: https://github.com/armbian/build/commit/568d8472b3c2ab406fd3897e6b952c7a71a8165b
+> X-Git-Archeology:   Date: Fri, 22 Jan 2021 13:12:09 +0100
+> X-Git-Archeology:   From: Aditya Prayoga <aprayoga@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Fix 2.5G Ethernet on Helios64 Mainline kernel (#2567)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 3b3d85e25c2ecde30df7b5274fc6f1b9c0299ea2: https://github.com/armbian/build/commit/3b3d85e25c2ecde30df7b5274fc6f1b9c0299ea2
+> X-Git-Archeology:   Date: Sat, 22 May 2021 17:08:44 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Upgrade EDGE to 5.12.y (#2825)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4
+> X-Git-Archeology:   Date: Tue, 11 Jan 2022 15:26:11 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel edge to 5.16 (#3387)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41
+> X-Git-Archeology:   Date: Sun, 20 Mar 2022 22:58:21 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: Adding Pine64 Quartz64a as WIP target (#3539)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c
+> X-Git-Archeology:   Date: Sun, 24 Apr 2022 22:33:47 +0200
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel media edge to 5.17 (#3704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 8aa038f5657a..90905af1a702 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -488,6 +488,7 @@ usbdrd_dwc3_0: usb@fe800000 {
+ 			snps,dis_u2_susphy_quirk;
+ 			snps,dis-del-phy-power-chg-quirk;
+ 			snps,dis-tx-ipgap-linecheck-quirk;
++			snps,xhci-trb-ent-quirk;
+ 			power-domains = <&power RK3399_PD_USB3>;
+ 			status = "disabled";
+ 		};
+@@ -524,6 +525,7 @@ usbdrd_dwc3_1: usb@fe900000 {
+ 			snps,dis_u2_susphy_quirk;
+ 			snps,dis-del-phy-power-chg-quirk;
+ 			snps,dis-tx-ipgap-linecheck-quirk;
++			snps,xhci-trb-ent-quirk;
+ 			power-domains = <&power RK3399_PD_USB3>;
+ 			status = "disabled";
+ 		};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3399-fix-pci-phy.patch b/patch/kernel/archive/rockchip64-6.10/rk3399-fix-pci-phy.patch
new file mode 100644
index 000000000000..21b02b310bdd
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3399-fix-pci-phy.patch
@@ -0,0 +1,47 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andrey Safonov <andrey.safonov@gmail.com>
+Date: Sat, 16 Dec 2023 22:46:35 +0300
+Subject: rk3399 PCIE PHY reset on probe
+
+Signed-off-by: Andrey Safonov <andrey.safonov@gmail.com>
+---
+ drivers/phy/rockchip/phy-rockchip-pcie.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
+index 8234b83fdd88..aa5ca6db0563 100644
+--- a/drivers/phy/rockchip/phy-rockchip-pcie.c
++++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
+@@ -344,6 +344,20 @@ static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
+ 
+ MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);
+ 
++static void rockchip_pcie_phy_reset(struct rockchip_pcie_phy *rk_phy)
++{
++	int i;
++
++	for (i = 0; i < PHY_MAX_LANE_NUM; i++)
++		regmap_write(rk_phy->reg_base,
++			     rk_phy->phy_data->pcie_laneoff,
++			     HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
++					   PHY_LANE_IDLE_MASK,
++					   PHY_LANE_IDLE_A_SHIFT + i));
++
++	reset_control_assert(rk_phy->phy_rst);
++}
++
+ static int rockchip_pcie_phy_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -394,6 +408,8 @@ static int rockchip_pcie_phy_probe(struct platform_device *pdev)
+ 	phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
+ 	dev_dbg(dev, "phy number is %d\n", phy_num);
+ 
++	rockchip_pcie_phy_reset(rk_phy);
++
+ 	for (i = 0; i < phy_num; i++) {
+ 		rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
+ 		if (IS_ERR(rk_phy->phys[i].phy)) {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3399-fix-usb-phy.patch b/patch/kernel/archive/rockchip64-6.10/rk3399-fix-usb-phy.patch
new file mode 100644
index 000000000000..122034b1b0a4
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3399-fix-usb-phy.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Mon, 4 Sep 2023 14:55:50 +0200
+Subject: increase timeout for usb3 type C phy init
+
+rockchip64: increase timeout for usb3 type C phy init
+---
+ drivers/phy/rockchip/phy-rockchip-typec.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
+index 6a641d9f752c..3862d7a4fcdb 100644
+--- a/drivers/phy/rockchip/phy-rockchip-typec.c
++++ b/drivers/phy/rockchip/phy-rockchip-typec.c
+@@ -904,7 +904,7 @@ static int rockchip_usb3_phy_power_on(struct phy *phy)
+ 			tcphy_cfg_usb3_to_usb2_only(tcphy, false);
+ 			goto unlock_ret;
+ 		}
+-		usleep_range(10, 20);
++		usleep_range(100, 200);
+ 	}
+ 
+ 	if (tcphy->mode == MODE_DISCONNECT)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch b/patch/kernel/archive/rockchip64-6.10/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch
new file mode 100644
index 000000000000..9d5c97ce9c03
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch
@@ -0,0 +1,181 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Dan Pasanen <dan.pasanen@gmail.com>
+Date: Thu, 16 Dec 2021 05:17:33 -0500
+Subject: [ARCHEOLOGY] rockchip-[current,edge]: add pcie hack and lsi scsi/sas
+ support (#3351)
+
+> X-Git-Archeology: > recovered message: > * build: kernel: rockchip64-[current,edge]: add pcie bus scan delay patches
+> X-Git-Archeology: > recovered message: > These are needed for cards like the LSI SAS2008 which needs a little
+> X-Git-Archeology: > recovered message: > extra time to initialize or they'll cause a kernel panic.
+> X-Git-Archeology: > recovered message: > References:
+> X-Git-Archeology: > recovered message: > https://gitlab.manjaro.org/manjaro-arm/packages/core/linux/-/blob/master/0013-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch
+> X-Git-Archeology: > recovered message: > https://gitlab.manjaro.org/manjaro-arm/packages/core/linux/-/blob/master/0022-arm64-dts-rockchip-Add-pcie-bus-scan-delay-to-rockpr.patch
+> X-Git-Archeology: > recovered message: > * config: linux-rockchip64-[current,edge]: enable lsi sata/sas support
+> X-Git-Archeology: - Revision 7be9e8b99590e32c0594365d00a2a2cfc3c4bd5a: https://github.com/armbian/build/commit/7be9e8b99590e32c0594365d00a2a2cfc3c4bd5a
+> X-Git-Archeology:   Date: Thu, 16 Dec 2021 05:17:33 -0500
+> X-Git-Archeology:   From: Dan Pasanen <dan.pasanen@gmail.com>
+> X-Git-Archeology:   Subject: rockchip-[current,edge]: add pcie hack and lsi scsi/sas support (#3351)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4
+> X-Git-Archeology:   Date: Tue, 11 Jan 2022 15:26:11 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel edge to 5.16 (#3387)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41
+> X-Git-Archeology:   Date: Sun, 20 Mar 2022 22:58:21 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: Adding Pine64 Quartz64a as WIP target (#3539)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c
+> X-Git-Archeology:   Date: Sun, 24 Apr 2022 22:33:47 +0200
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel media edge to 5.17 (#3704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ Documentation/admin-guide/kernel-parameters.txt |  8 +++
+ drivers/pci/controller/pcie-rockchip-host.c     | 25 ++++++++++
+ drivers/pci/controller/pcie-rockchip.c          |  6 +++
+ drivers/pci/controller/pcie-rockchip.h          |  2 +
+ 4 files changed, 41 insertions(+)
+
+diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
+index 0a1731a0f0ef..a47b48a8aaec 100644
+--- a/Documentation/admin-guide/kernel-parameters.txt
++++ b/Documentation/admin-guide/kernel-parameters.txt
+@@ -4485,6 +4485,14 @@
+ 		nomsi	Do not use MSI for native PCIe PME signaling (this makes
+ 			all PCIe root ports use INTx for all services).
+ 
++	pcie_rockchip_host.bus_scan_delay=	[PCIE] Delay in ms before
++			scanning PCIe bus in Rockchip PCIe host driver. Some PCIe
++			cards seem to need delays that can be several hundred ms.
++			If set to greater than or equal to 0 this parameter will
++			override delay that can be set in device tree.
++			Values less than 0 mean that this parameter is ignored.
++			default=-1
++
+ 	pcmv=		[HW,PCMCIA] BadgePAD 4
+ 
+ 	pd_ignore_unused
+diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
+index afbbdccd195d..f7fc4df0cee3 100644
+--- a/drivers/pci/controller/pcie-rockchip-host.c
++++ b/drivers/pci/controller/pcie-rockchip-host.c
+@@ -32,10 +32,14 @@
+ #include <linux/platform_device.h>
+ #include <linux/reset.h>
+ #include <linux/regmap.h>
++#include <linux/moduleparam.h>
+ 
+ #include "../pci.h"
+ #include "pcie-rockchip.h"
+ 
++static int bus_scan_delay = -1;
++module_param_named(bus_scan_delay, bus_scan_delay, int, S_IRUGO);
++
+ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
+ {
+ 	u32 status;
+@@ -930,6 +934,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct pci_host_bridge *bridge;
+ 	int err;
++	u32 delay = 0;
+ 
+ 	if (!dev->of_node)
+ 		return -ENODEV;
+@@ -979,6 +984,26 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
+ 	bridge->sysdata = rockchip;
+ 	bridge->ops = &rockchip_pcie_ops;
+ 
++	/* Checking if bus scan delay was given from command line and prefer
++	 * that over the value in device tree (which defaults to 0 if not set).
++	 */
++	if (bus_scan_delay >= 0) {
++		delay = bus_scan_delay;
++		dev_info(dev, "wait %u ms (from command-line) before bus scan\n", delay);
++	} else {
++		delay = rockchip->bus_scan_delay;
++		dev_info(dev, "wait %u ms (from device tree) before bus scan\n", delay);
++	}
++	/* Workaround for some devices crashing on pci_host_probe / pci_scan_root_bus_bridge
++	 * calls: sleep a bit before bus scan. Call trace gets to rockchip_pcie_rd_conf when
++	 * trying to read vendor id (pci_bus_generic_read_dev_vendor_id is in call stack)
++	 * before panicing. I have no idea why this works or what causes the panic. I just
++	 * found this hack by luck when trying to "make it break differently if possible".
++	 */
++	if (delay > 0) {
++		msleep(delay);
++	}
++
+ 	err = rockchip_pcie_setup_irq(rockchip);
+ 	if (err)
+ 		goto err_remove_irq_domain;
+diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
+index 0ef2e622d36e..7255c1234fed 100644
+--- a/drivers/pci/controller/pcie-rockchip.c
++++ b/drivers/pci/controller/pcie-rockchip.c
+@@ -151,6 +151,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
+ 		return PTR_ERR(rockchip->clk_pcie_pm);
+ 	}
+ 
++	err = of_property_read_u32(node, "bus-scan-delay-ms", &rockchip->bus_scan_delay);
++	if (err) {
++		dev_info(dev, "no bus scan delay, default to 0 ms\n");
++		rockchip->bus_scan_delay = 0;
++	}
++
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
+diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
+index 6111de35f84c..591d2f122051 100644
+--- a/drivers/pci/controller/pcie-rockchip.h
++++ b/drivers/pci/controller/pcie-rockchip.h
+@@ -318,6 +318,8 @@ struct rockchip_pcie {
+ 	phys_addr_t msg_bus_addr;
+ 	bool is_rc;
+ 	struct resource *mem_res;
++	/* Bus scan delay is a workaround for some pcie devices causing crashes */
++	u32 bus_scan_delay;
+ };
+ 
+ static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3399-sd-drive-level-8ma.patch b/patch/kernel/archive/rockchip64-6.10/rk3399-sd-drive-level-8ma.patch
new file mode 100644
index 000000000000..b36e193a465b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3399-sd-drive-level-8ma.patch
@@ -0,0 +1,159 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Martin Ayotte <martinayotte@yahoo.ca>
+Date: Thu, 3 Jan 2019 11:04:17 -0500
+Subject: [ARCHEOLOGY] add better strength on SDCard and put back previous
+ speed setting
+
+> X-Git-Archeology: - Revision 211c802f7cfedaac75a35f65d427910011c29242: https://github.com/armbian/build/commit/211c802f7cfedaac75a35f65d427910011c29242
+> X-Git-Archeology:   Date: Thu, 03 Jan 2019 11:04:17 -0500
+> X-Git-Archeology:   From: Martin Ayotte <martinayotte@yahoo.ca>
+> X-Git-Archeology:   Subject: add better strength on SDCard and put back previous speed setting
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f2e71dbc730eaf7f1e586dfd5951bc149cb827d2: https://github.com/armbian/build/commit/f2e71dbc730eaf7f1e586dfd5951bc149cb827d2
+> X-Git-Archeology:   Date: Fri, 04 Jan 2019 10:04:19 -0500
+> X-Git-Archeology:   From: Martin Ayotte <martinayotte@yahoo.ca>
+> X-Git-Archeology:   Subject: fix sdmmc-bus1 pin
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 005e8cf9fcba2922685f5ee49cef833be1465ec1: https://github.com/armbian/build/commit/005e8cf9fcba2922685f5ee49cef833be1465ec1
+> X-Git-Archeology:   Date: Sun, 27 Jan 2019 15:37:40 -0500
+> X-Git-Archeology:   From: Martin Ayotte <martinayotte@yahoo.ca>
+> X-Git-Archeology:   Subject: fxi SD-CD pullup
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 885111ab0e166f97338df63714ea47a5b554b698: https://github.com/armbian/build/commit/885111ab0e166f97338df63714ea47a5b554b698
+> X-Git-Archeology:   Date: Sat, 13 Jul 2019 11:25:27 -0400
+> X-Git-Archeology:   From: Martin Ayotte <martinayotte@yahoo.ca>
+> X-Git-Archeology:   Subject: switch rockchip64-dev and rk3399-dev to 5.2.y
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3
+> X-Git-Archeology:   Date: Tue, 19 Nov 2019 23:25:39 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Remove K<4, change branches, new features (#1586)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5: https://github.com/armbian/build/commit/4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5
+> X-Git-Archeology:   Date: Wed, 02 Sep 2020 23:22:09 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switched rockchip64 curent to kernel 5.8.y (#2175)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4
+> X-Git-Archeology:   Date: Tue, 11 Jan 2022 15:26:11 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel edge to 5.16 (#3387)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41
+> X-Git-Archeology:   Date: Sun, 20 Mar 2022 22:58:21 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: Adding Pine64 Quartz64a as WIP target (#3539)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c
+> X-Git-Archeology:   Date: Sun, 24 Apr 2022 22:33:47 +0200
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel media edge to 5.17 (#3704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 16 +++++-----
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 1eb5c63b468e..867a9f893b24 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -2592,25 +2592,25 @@ sdio0_int: sdio0-int {
+ 		sdmmc {
+ 			sdmmc_bus1: sdmmc-bus1 {
+ 				rockchip,pins =
+-					<4 RK_PB0 1 &pcfg_pull_up>;
++					<4 RK_PB0 1 &pcfg_pull_up_8ma>;
+ 			};
+ 
+ 			sdmmc_bus4: sdmmc-bus4 {
+ 				rockchip,pins =
+-					<4 RK_PB0 1 &pcfg_pull_up>,
+-					<4 RK_PB1 1 &pcfg_pull_up>,
+-					<4 RK_PB2 1 &pcfg_pull_up>,
+-					<4 RK_PB3 1 &pcfg_pull_up>;
++					<4 RK_PB0 1 &pcfg_pull_up_8ma>,
++					<4 RK_PB1 1 &pcfg_pull_up_8ma>,
++					<4 RK_PB2 1 &pcfg_pull_up_8ma>,
++					<4 RK_PB3 1 &pcfg_pull_up_8ma>;
+ 			};
+ 
+ 			sdmmc_clk: sdmmc-clk {
+ 				rockchip,pins =
+-					<4 RK_PB4 1 &pcfg_pull_none>;
++					<4 RK_PB4 1 &pcfg_pull_none_12ma>;
+ 			};
+ 
+ 			sdmmc_cmd: sdmmc-cmd {
+ 				rockchip,pins =
+-					<4 RK_PB5 1 &pcfg_pull_up>;
++					<4 RK_PB5 1 &pcfg_pull_up_8ma>;
+ 			};
+ 
+ 			sdmmc_cd: sdmmc-cd {
+@@ -2620,7 +2620,7 @@ sdmmc_cd: sdmmc-cd {
+ 
+ 			sdmmc_wp: sdmmc-wp {
+ 				rockchip,pins =
+-					<0 RK_PB0 1 &pcfg_pull_up>;
++					<0 RK_PB0 1 &pcfg_pull_up_8ma>;
+ 			};
+ 		};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3399-sd-pwr-pinctrl.patch b/patch/kernel/archive/rockchip64-6.10/rk3399-sd-pwr-pinctrl.patch
new file mode 100644
index 000000000000..c0be8a82a29b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3399-sd-pwr-pinctrl.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 21 May 2023 13:14:26 +0200
+Subject: rk3399: add sd power pin to pinctrl node
+
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 867a9f893b24..76239a58ab0b 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -2587,6 +2587,11 @@ sdio0_int: sdio0-int {
+ 				rockchip,pins =
+ 					<0 RK_PA4 1 &pcfg_pull_up>;
+ 			};
++
++			sdmmc_pwr: sdmmc-pwr {
++				rockchip,pins =
++					<0 RK_PA1 1 &pcfg_pull_up>;
++			};
+ 		};
+ 
+ 		sdmmc {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk3399-unlock-temperature.patch b/patch/kernel/archive/rockchip64-6.10/rk3399-unlock-temperature.patch
new file mode 100644
index 000000000000..dd305b6cf301
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk3399-unlock-temperature.patch
@@ -0,0 +1,127 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ThomasKaiser <github@kaiser-edv.de>
+Date: Sat, 13 Oct 2018 16:35:07 +0200
+Subject: [ARCHEOLOGY] Increase performance with rk3399-dev
+
+> X-Git-Archeology: - Revision b28fa47aa8b9864ccae8b90ebb3d46ae55103d6e: https://github.com/armbian/build/commit/b28fa47aa8b9864ccae8b90ebb3d46ae55103d6e
+> X-Git-Archeology:   Date: Sat, 13 Oct 2018 16:35:07 +0200
+> X-Git-Archeology:   From: ThomasKaiser <github@kaiser-edv.de>
+> X-Git-Archeology:   Subject: Increase performance with rk3399-dev
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f18360d1ef5d6487392ff4079301bca97945e704: https://github.com/armbian/build/commit/f18360d1ef5d6487392ff4079301bca97945e704
+> X-Git-Archeology:   Date: Wed, 24 Oct 2018 17:03:35 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: [rk3399-dev] Merging rk3399-DEV with rockchip64-DEV on sources, patches and config level. Leave family intact, add 1.5 OPP for RK3328, add upstream patch for rk3399-default
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3
+> X-Git-Archeology:   Date: Tue, 19 Nov 2019 23:25:39 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Remove K<4, change branches, new features (#1586)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070
+> X-Git-Archeology:   Date: Sun, 13 Dec 2020 22:13:03 -0500
+> X-Git-Archeology:   From: tonymac32 <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: [ rockchip64 ] Clean up patchset
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4
+> X-Git-Archeology:   Date: Tue, 11 Jan 2022 15:26:11 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel edge to 5.16 (#3387)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41
+> X-Git-Archeology:   Date: Sun, 20 Mar 2022 22:58:21 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: Adding Pine64 Quartz64a as WIP target (#3539)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c
+> X-Git-Archeology:   Date: Sun, 24 Apr 2022 22:33:47 +0200
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel media edge to 5.17 (#3704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 76239a58ab0b..a0441f640791 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -858,17 +858,17 @@ cpu_thermal: cpu-thermal {
+ 
+ 			trips {
+ 				cpu_alert0: cpu_alert0 {
+-					temperature = <70000>;
++					temperature = <85000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 				cpu_alert1: cpu_alert1 {
+-					temperature = <75000>;
++					temperature = <95000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 				cpu_crit: cpu_crit {
+-					temperature = <95000>;
++					temperature = <100000>;
+ 					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/rk356x-add-rkvdec2-support.patch b/patch/kernel/archive/rockchip64-6.10/rk356x-add-rkvdec2-support.patch
new file mode 100644
index 000000000000..eba682857401
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk356x-add-rkvdec2-support.patch
@@ -0,0 +1,59 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+index d8543b555..37141f416 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -449,6 +449,19 @@ usb2phy1_grf: syscon@fdca8000 {
+ 		reg = <0x0 0xfdca8000 0x0 0x8000>;
+ 	};
+ 
++	sram@fdcc0000 {
++		compatible = "mmio-sram";
++		reg = <0x0 0xfdcc0000 0x0 0xb000>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <0x0 0x0 0xfdcc0000 0xb000>;
++
++		vdec_sram: rkvdec-sram@0 {
++			reg = <0x0 0xb000>;
++			pool;
++		};
++	};
++
+ 	pmucru: clock-controller@fdd00000 {
+ 		compatible = "rockchip,rk3568-pmucru";
+ 		reg = <0x0 0xfdd00000 0x0 0x1000>;
+@@ -635,7 +648,7 @@ gpu: gpu@fde60000 {
+ 	};
+ 
+ 	vpu: video-codec@fdea0400 {
+-		compatible = "rockchip,rk3568-vpu";
++		compatible = "rockchip,rk3328-vpu";
+ 		reg = <0x0 0xfdea0000 0x0 0x800>;
+ 		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "vdpu";
+@@ -686,6 +699,25 @@ vepu_mmu: iommu@fdee0800 {
+ 		#iommu-cells = <0>;
+ 	};
+ 
++	vdec: video-codec@fdf80200 {
++		compatible = "rockchip,rk3588-vdec";
++		reg = <0x0 0xfdf80200 0x0 0x500>;
++		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_CA>,
++			 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
++		clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
++		assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CORE>,
++				  <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_HEVC_CA>;
++		assigned-clock-rates = <297000000>, <297000000>,
++				       <297000000>, <297000000>;
++		resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CA>,
++			 <&cru SRST_RKVDEC_CORE>, <&cru SRST_RKVDEC_HEVC_CA>;
++		reset-names = "rst_axi", "rst_ahb", "rst_cabac",
++			      "rst_core", "rst_hevc_cabac";
++		power-domains = <&power RK3568_PD_RKVDEC>;
++		sram = <&vdec_sram>;
++	};
++
+ 	sdmmc2: mmc@fe000000 {
+ 		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ 		reg = <0x0 0xfe000000 0x0 0x4000>;
diff --git a/patch/kernel/archive/rockchip64-6.10/rk35xx-montjoie-crypto-v2-rk35xx.patch b/patch/kernel/archive/rockchip64-6.10/rk35xx-montjoie-crypto-v2-rk35xx.patch
new file mode 100644
index 000000000000..804c21f281b0
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/rk35xx-montjoie-crypto-v2-rk35xx.patch
@@ -0,0 +1,2327 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe@baylibre.com>
+Date: Tue, 7 Nov 2023 15:55:27 +0000
+Subject: dt-bindings: crypto: add support for rockchip,crypto-rk3588
+
+Add device tree binding documentation for the Rockchip cryptographic
+offloader V2.
+
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+---
+ Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml | 65 ++++++++++
+ 1 file changed, 65 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
+new file mode 100644
+index 000000000000..c01963413260
+--- /dev/null
++++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
+@@ -0,0 +1,65 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/crypto/rockchip,rk3588-crypto.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip cryptographic offloader V2
++
++maintainers:
++  - Corentin Labbe <clabbe@baylibre.com>
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk3568-crypto
++      - rockchip,rk3588-crypto
++
++  reg:
++    maxItems: 1
++
++  interrupts:
++    maxItems: 1
++
++  clocks:
++    minItems: 3
++
++  clock-names:
++    items:
++      - const: core
++      - const: a
++      - const: h
++
++  resets:
++    minItems: 1
++
++  reset-names:
++    items:
++      - const: core
++
++required:
++  - compatible
++  - reg
++  - interrupts
++  - clocks
++  - clock-names
++  - resets
++  - reset-names
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
++    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
++    crypto@fe370000 {
++      compatible = "rockchip,rk3588-crypto";
++      reg = <0xfe370000 0x4000>;
++      interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
++      clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>,
++               <&scmi_clk SCMI_HCLK_SECURE_NS>;
++      clock-names = "core", "a", "h";
++      resets = <&scmi_reset SRST_CRYPTO_CORE>;
++      reset-names = "core";
++    };
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe@baylibre.com>
+Date: Tue, 7 Nov 2023 15:55:29 +0000
+Subject: ARM64: dts: rk3588: add crypto node
+
+The rk3588 has a crypto IP handled by the rk3588 crypto driver so adds a
+node for it.
+
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+index 75e279781cf6..ca2078f72801 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -2038,6 +2038,18 @@ sdhci: mmc@fe2e0000 {
+ 		status = "disabled";
+ 	};
+ 
++	crypto: crypto@fe370000 {
++		compatible = "rockchip,rk3588-crypto";
++		reg = <0x0 0xfe370000 0x0 0x2000>;
++		interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>,
++			 <&scmi_clk SCMI_HCLK_SECURE_NS>;
++		clock-names = "core", "aclk", "hclk";
++		resets = <&scmi_reset SRST_CRYPTO_CORE>;
++		reset-names = "core";
++		status = "okay";
++	};
++
+ 	i2s0_8ch: i2s@fe470000 {
+ 		compatible = "rockchip,rk3588-i2s-tdm";
+ 		reg = <0x0 0xfe470000 0x0 0x1000>;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe@baylibre.com>
+Date: Tue, 7 Nov 2023 15:55:30 +0000
+Subject: ARM64: dts: rk356x: add crypto node
+
+Both RK3566 and RK3568 have a crypto IP handled by the rk3588 crypto driver so adds a
+node for it.
+
+Tested-by: Ricardo Pardini <ricardo@pardini.net>
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+index c19c0f1b3778..d2764659d21b 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1070,6 +1070,18 @@ sdhci: mmc@fe310000 {
+ 		status = "disabled";
+ 	};
+ 
++	crypto: crypto@fe380000 {
++		compatible = "rockchip,rk3568-crypto";
++		reg = <0x0 0xfe380000 0x0 0x2000>;
++		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>,
++			 <&cru CLK_CRYPTO_NS_CORE>;
++		clock-names = "aclk", "hclk", "core";
++		resets = <&cru SRST_CRYPTO_NS_CORE>;
++		reset-names = "core";
++		status = "okay";
++	};
++
+ 	i2s0_8ch: i2s@fe400000 {
+ 		compatible = "rockchip,rk3568-i2s-tdm";
+ 		reg = <0x0 0xfe400000 0x0 0x1000>;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe@baylibre.com>
+Date: Tue, 7 Nov 2023 15:55:31 +0000
+Subject: reset: rockchip: secure reset must be used by SCMI
+
+While working on the rk3588 crypto driver, I loose lot of time
+understanding why resetting the IP failed.
+This is due to RK3588_SECURECRU_RESET_OFFSET being in the secure world,
+so impossible to operate on it from the kernel.
+All resets in this block must be handled via SCMI call.
+
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+---
+ drivers/clk/rockchip/rst-rk3588.c               | 42 ------
+ include/dt-bindings/reset/rockchip,rk3588-cru.h | 68 +++++-----
+ 2 files changed, 34 insertions(+), 76 deletions(-)
+
+diff --git a/drivers/clk/rockchip/rst-rk3588.c b/drivers/clk/rockchip/rst-rk3588.c
+index e855bb8d5413..6556d9d3c7ab 100644
+--- a/drivers/clk/rockchip/rst-rk3588.c
++++ b/drivers/clk/rockchip/rst-rk3588.c
+@@ -16,9 +16,6 @@
+ /* 0xFD7C8000 + 0x0A00 */
+ #define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
+ 
+-/* 0xFD7D0000 + 0x0A00 */
+-#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
+-
+ /* 0xFD7F0000 + 0x0A00 */
+ #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
+ 
+@@ -806,45 +803,6 @@ static const int rk3588_register_offset[] = {
+ 	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4),
+ 	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5),
+ 	RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6),
+-
+-	/* SECURECRU_SOFTRST_CON00 */
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15),
+-
+-	/* SECURECRU_SOFTRST_CON01 */
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15),
+-
+-	/* SECURECRU_SOFTRST_CON02 */
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15),
+-
+-	/* SECURECRU_SOFTRST_CON03 */
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5),
+-	RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6),
+ };
+ 
+ void rk3588_rst_init(struct device_node *np, void __iomem *reg_base)
+diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h
+index d4264db2a07f..c0d08ae78cd5 100644
+--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
++++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
+@@ -716,39 +716,39 @@
+ #define SRST_P_GPIO0			627
+ #define SRST_GPIO0			628
+ 
+-#define SRST_A_SECURE_NS_BIU		629
+-#define SRST_H_SECURE_NS_BIU		630
+-#define SRST_A_SECURE_S_BIU		631
+-#define SRST_H_SECURE_S_BIU		632
+-#define SRST_P_SECURE_S_BIU		633
+-#define SRST_CRYPTO_CORE		634
+-
+-#define SRST_CRYPTO_PKA			635
+-#define SRST_CRYPTO_RNG			636
+-#define SRST_A_CRYPTO			637
+-#define SRST_H_CRYPTO			638
+-#define SRST_KEYLADDER_CORE		639
+-#define SRST_KEYLADDER_RNG		640
+-#define SRST_A_KEYLADDER		641
+-#define SRST_H_KEYLADDER		642
+-#define SRST_P_OTPC_S			643
+-#define SRST_OTPC_S			644
+-#define SRST_WDT_S			645
+-
+-#define SRST_T_WDT_S			646
+-#define SRST_H_BOOTROM			647
+-#define SRST_A_DCF			648
+-#define SRST_P_DCF			649
+-#define SRST_H_BOOTROM_NS		650
+-#define SRST_P_KEYLADDER		651
+-#define SRST_H_TRNG_S			652
+-
+-#define SRST_H_TRNG_NS			653
+-#define SRST_D_SDMMC_BUFFER		654
+-#define SRST_H_SDMMC			655
+-#define SRST_H_SDMMC_BUFFER		656
+-#define SRST_SDMMC			657
+-#define SRST_P_TRNG_CHK			658
+-#define SRST_TRNG_S			659
++#define SRST_A_SECURE_NS_BIU		10
++#define SRST_H_SECURE_NS_BIU		11
++#define SRST_A_SECURE_S_BIU		12
++#define SRST_H_SECURE_S_BIU		13
++#define SRST_P_SECURE_S_BIU		14
++#define SRST_CRYPTO_CORE		15
++
++#define SRST_CRYPTO_PKA			16
++#define SRST_CRYPTO_RNG			17
++#define SRST_A_CRYPTO			18
++#define SRST_H_CRYPTO			19
++#define SRST_KEYLADDER_CORE		25
++#define SRST_KEYLADDER_RNG		26
++#define SRST_A_KEYLADDER		27
++#define SRST_H_KEYLADDER		28
++#define SRST_P_OTPC_S			29
++#define SRST_OTPC_S			30
++#define SRST_WDT_S			31
++
++#define SRST_T_WDT_S			32
++#define SRST_H_BOOTROM			33
++#define SRST_A_DCF			34
++#define SRST_P_DCF			35
++#define SRST_H_BOOTROM_NS		37
++#define SRST_P_KEYLADDER		46
++#define SRST_H_TRNG_S			47
++
++#define SRST_H_TRNG_NS			48
++#define SRST_D_SDMMC_BUFFER		49
++#define SRST_H_SDMMC			50
++#define SRST_H_SDMMC_BUFFER		51
++#define SRST_SDMMC			52
++#define SRST_P_TRNG_CHK			53
++#define SRST_TRNG_S			54
+ 
+ #endif
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe@baylibre.com>
+Date: Tue, 7 Nov 2023 15:55:32 +0000
+Subject: crypto: rockchip: add rk3588 driver
+
+RK3588 have a new crypto IP, this patch adds basic support for it.
+Only hashes and cipher are handled for the moment.
+
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+---
+ drivers/crypto/Kconfig                        |  29 +
+ drivers/crypto/rockchip/Makefile              |   5 +
+ drivers/crypto/rockchip/rk2_crypto.c          | 739 ++++++++++
+ drivers/crypto/rockchip/rk2_crypto.h          | 246 +++
+ drivers/crypto/rockchip/rk2_crypto_ahash.c    | 344 +++++
+ drivers/crypto/rockchip/rk2_crypto_skcipher.c | 576 ++++++++
+ 6 files changed, 1939 insertions(+)
+
+diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
+index 79c3bb9c99c3..b6a2027b1f9a 100644
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -660,6 +660,35 @@ config CRYPTO_DEV_ROCKCHIP_DEBUG
+ 	  the number of requests per algorithm and other internal stats.
+ 
+ 
++config CRYPTO_DEV_ROCKCHIP2
++	tristate "Rockchip's cryptographic offloader V2"
++	depends on OF && ARCH_ROCKCHIP
++	depends on PM
++	select CRYPTO_ECB
++	select CRYPTO_CBC
++	select CRYPTO_AES
++	select CRYPTO_MD5
++	select CRYPTO_SHA1
++	select CRYPTO_SHA256
++	select CRYPTO_SHA512
++	select CRYPTO_SM3_GENERIC
++	select CRYPTO_HASH
++	select CRYPTO_SKCIPHER
++	select CRYPTO_ENGINE
++
++	help
++	  This driver interfaces with the hardware crypto offloader present
++	  on RK3566, RK3568 and RK3588.
++
++config CRYPTO_DEV_ROCKCHIP2_DEBUG
++	bool "Enable Rockchip V2 crypto stats"
++	depends on CRYPTO_DEV_ROCKCHIP2
++	depends on DEBUG_FS
++	help
++	  Say y to enable Rockchip crypto debug stats.
++	  This will create /sys/kernel/debug/rk3588_crypto/stats for displaying
++	  the number of requests per algorithm and other internal stats.
++
+ config CRYPTO_DEV_ZYNQMP_AES
+ 	tristate "Support for Xilinx ZynqMP AES hw accelerator"
+ 	depends on ZYNQMP_FIRMWARE || COMPILE_TEST
+diff --git a/drivers/crypto/rockchip/Makefile b/drivers/crypto/rockchip/Makefile
+index 785277aca71e..452a12ff6538 100644
+--- a/drivers/crypto/rockchip/Makefile
++++ b/drivers/crypto/rockchip/Makefile
+@@ -3,3 +3,8 @@ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o
+ 		  rk3288_crypto_skcipher.o \
+ 		  rk3288_crypto_ahash.o
+ rk_crypto-$(CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG) += rk3288_crypto_trng.o
++
++obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP2) += rk_crypto2.o
++rk_crypto2-objs := rk2_crypto.o \
++		  rk2_crypto_skcipher.o \
++		  rk2_crypto_ahash.o
+diff --git a/drivers/crypto/rockchip/rk2_crypto.c b/drivers/crypto/rockchip/rk2_crypto.c
+new file mode 100644
+index 000000000000..79ed697d8ec5
+--- /dev/null
++++ b/drivers/crypto/rockchip/rk2_crypto.c
+@@ -0,0 +1,739 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * hardware cryptographic offloader for RK3568/RK3588 SoC
++ *
++ * Copyright (c) 2022-2023, Corentin Labbe <clabbe@baylibre.com>
++ */
++
++#include "rk2_crypto.h"
++#include <linux/clk.h>
++#include <linux/crypto.h>
++#include <linux/dma-mapping.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/reset.h>
++
++static struct rockchip_ip rocklist = {
++	.dev_list = LIST_HEAD_INIT(rocklist.dev_list),
++	.lock = __SPIN_LOCK_UNLOCKED(rocklist.lock),
++};
++
++struct rk2_crypto_dev *get_rk2_crypto(void)
++{
++	struct rk2_crypto_dev *first;
++
++	spin_lock(&rocklist.lock);
++	first = list_first_entry_or_null(&rocklist.dev_list,
++					 struct rk2_crypto_dev, list);
++	list_rotate_left(&rocklist.dev_list);
++	spin_unlock(&rocklist.lock);
++	return first;
++}
++
++static const struct rk2_variant rk3568_variant = {
++	.num_clks = 3,
++};
++
++static const struct rk2_variant rk3588_variant = {
++	.num_clks = 3,
++};
++
++static int rk2_crypto_get_clks(struct rk2_crypto_dev *dev)
++{
++	int i, j, err;
++	unsigned long cr;
++
++	dev->num_clks = devm_clk_bulk_get_all(dev->dev, &dev->clks);
++	if (dev->num_clks < dev->variant->num_clks) {
++		dev_err(dev->dev, "Missing clocks, got %d instead of %d\n",
++			dev->num_clks, dev->variant->num_clks);
++		return -EINVAL;
++	}
++
++	for (i = 0; i < dev->num_clks; i++) {
++		cr = clk_get_rate(dev->clks[i].clk);
++		for (j = 0; j < ARRAY_SIZE(dev->variant->rkclks); j++) {
++			if (dev->variant->rkclks[j].max == 0)
++				continue;
++			if (strcmp(dev->variant->rkclks[j].name, dev->clks[i].id))
++				continue;
++			if (cr > dev->variant->rkclks[j].max) {
++				err = clk_set_rate(dev->clks[i].clk,
++						   dev->variant->rkclks[j].max);
++				if (err)
++					dev_err(dev->dev, "Fail downclocking %s from %lu to %lu\n",
++						dev->variant->rkclks[j].name, cr,
++						dev->variant->rkclks[j].max);
++				else
++					dev_info(dev->dev, "Downclocking %s from %lu to %lu\n",
++						 dev->variant->rkclks[j].name, cr,
++						 dev->variant->rkclks[j].max);
++			}
++		}
++	}
++	return 0;
++}
++
++static int rk2_crypto_enable_clk(struct rk2_crypto_dev *dev)
++{
++	int err;
++
++	err = clk_bulk_prepare_enable(dev->num_clks, dev->clks);
++	if (err)
++		dev_err(dev->dev, "Could not enable clock clks\n");
++
++	return err;
++}
++
++static void rk2_crypto_disable_clk(struct rk2_crypto_dev *dev)
++{
++	clk_bulk_disable_unprepare(dev->num_clks, dev->clks);
++}
++
++/*
++ * Power management strategy: The device is suspended until a request
++ * is handled. For avoiding suspend/resume yoyo, the autosuspend is set to 2s.
++ */
++static int rk2_crypto_pm_suspend(struct device *dev)
++{
++	struct rk2_crypto_dev *rkdev = dev_get_drvdata(dev);
++
++	rk2_crypto_disable_clk(rkdev);
++	reset_control_assert(rkdev->rst);
++
++	return 0;
++}
++
++static int rk2_crypto_pm_resume(struct device *dev)
++{
++	struct rk2_crypto_dev *rkdev = dev_get_drvdata(dev);
++	int ret;
++
++	ret = rk2_crypto_enable_clk(rkdev);
++	if (ret)
++		return ret;
++
++	reset_control_deassert(rkdev->rst);
++	return 0;
++}
++
++static const struct dev_pm_ops rk2_crypto_pm_ops = {
++	SET_RUNTIME_PM_OPS(rk2_crypto_pm_suspend, rk2_crypto_pm_resume, NULL)
++};
++
++static int rk2_crypto_pm_init(struct rk2_crypto_dev *rkdev)
++{
++	int err;
++
++	pm_runtime_use_autosuspend(rkdev->dev);
++	pm_runtime_set_autosuspend_delay(rkdev->dev, 2000);
++
++	err = pm_runtime_set_suspended(rkdev->dev);
++	if (err)
++		return err;
++	pm_runtime_enable(rkdev->dev);
++	return err;
++}
++
++static void rk2_crypto_pm_exit(struct rk2_crypto_dev *rkdev)
++{
++	pm_runtime_disable(rkdev->dev);
++}
++
++static irqreturn_t rk2_crypto_irq_handle(int irq, void *dev_id)
++{
++	struct rk2_crypto_dev *rkc  = platform_get_drvdata(dev_id);
++	u32 v;
++
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_INT_ST);
++	writel(v, rkc->reg + RK2_CRYPTO_DMA_INT_ST);
++
++	rkc->status = 1;
++	if (v & 0xF8) {
++		dev_warn(rkc->dev, "DMA Error\n");
++		rkc->status = 0;
++	}
++	complete(&rkc->complete);
++
++	return IRQ_HANDLED;
++}
++
++static struct rk2_crypto_template rk2_crypto_algs[] = {
++	{
++		.type = CRYPTO_ALG_TYPE_SKCIPHER,
++		.rk2_mode = RK2_CRYPTO_AES_ECB,
++		.alg.skcipher.base = {
++			.base.cra_name		= "ecb(aes)",
++			.base.cra_driver_name	= "ecb-aes-rk2",
++			.base.cra_priority	= 300,
++			.base.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
++			.base.cra_blocksize	= AES_BLOCK_SIZE,
++			.base.cra_ctxsize	= sizeof(struct rk2_cipher_ctx),
++			.base.cra_alignmask	= 0x0f,
++			.base.cra_module	= THIS_MODULE,
++
++			.init			= rk2_cipher_tfm_init,
++			.exit			= rk2_cipher_tfm_exit,
++			.min_keysize		= AES_MIN_KEY_SIZE,
++			.max_keysize		= AES_MAX_KEY_SIZE,
++			.setkey			= rk2_aes_setkey,
++			.encrypt		= rk2_skcipher_encrypt,
++			.decrypt		= rk2_skcipher_decrypt,
++		},
++		.alg.skcipher.op = {
++			.do_one_request = rk2_cipher_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_SKCIPHER,
++		.rk2_mode = RK2_CRYPTO_AES_CBC,
++		.alg.skcipher.base = {
++			.base.cra_name		= "cbc(aes)",
++			.base.cra_driver_name	= "cbc-aes-rk2",
++			.base.cra_priority	= 300,
++			.base.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
++			.base.cra_blocksize	= AES_BLOCK_SIZE,
++			.base.cra_ctxsize	= sizeof(struct rk2_cipher_ctx),
++			.base.cra_alignmask	= 0x0f,
++			.base.cra_module	= THIS_MODULE,
++
++			.init			= rk2_cipher_tfm_init,
++			.exit			= rk2_cipher_tfm_exit,
++			.min_keysize		= AES_MIN_KEY_SIZE,
++			.max_keysize		= AES_MAX_KEY_SIZE,
++			.ivsize			= AES_BLOCK_SIZE,
++			.setkey			= rk2_aes_setkey,
++			.encrypt		= rk2_skcipher_encrypt,
++			.decrypt		= rk2_skcipher_decrypt,
++		},
++		.alg.skcipher.op = {
++			.do_one_request = rk2_cipher_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_SKCIPHER,
++		.rk2_mode = RK2_CRYPTO_AES_XTS,
++		.is_xts = true,
++		.alg.skcipher.base = {
++			.base.cra_name		= "xts(aes)",
++			.base.cra_driver_name	= "xts-aes-rk2",
++			.base.cra_priority	= 300,
++			.base.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
++			.base.cra_blocksize	= AES_BLOCK_SIZE,
++			.base.cra_ctxsize	= sizeof(struct rk2_cipher_ctx),
++			.base.cra_alignmask	= 0x0f,
++			.base.cra_module	= THIS_MODULE,
++
++			.init			= rk2_cipher_tfm_init,
++			.exit			= rk2_cipher_tfm_exit,
++			.min_keysize		= AES_MIN_KEY_SIZE * 2,
++			.max_keysize		= AES_MAX_KEY_SIZE * 2,
++			.ivsize			= AES_BLOCK_SIZE,
++			.setkey			= rk2_aes_xts_setkey,
++			.encrypt		= rk2_skcipher_encrypt,
++			.decrypt		= rk2_skcipher_decrypt,
++		},
++		.alg.skcipher.op = {
++			.do_one_request = rk2_cipher_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_MD5,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = MD5_DIGEST_SIZE,
++				.statesize = sizeof(struct md5_state),
++				.base = {
++					.cra_name = "md5",
++					.cra_driver_name = "rk2-md5",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_SHA1,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = SHA1_DIGEST_SIZE,
++				.statesize = sizeof(struct sha1_state),
++				.base = {
++					.cra_name = "sha1",
++					.cra_driver_name = "rk2-sha1",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = SHA1_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_SHA256,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = SHA256_DIGEST_SIZE,
++				.statesize = sizeof(struct sha256_state),
++				.base = {
++					.cra_name = "sha256",
++					.cra_driver_name = "rk2-sha256",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = SHA256_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_SHA384,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = SHA384_DIGEST_SIZE,
++				.statesize = sizeof(struct sha512_state),
++				.base = {
++					.cra_name = "sha384",
++					.cra_driver_name = "rk2-sha384",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = SHA384_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_SHA512,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = SHA512_DIGEST_SIZE,
++				.statesize = sizeof(struct sha512_state),
++				.base = {
++					.cra_name = "sha512",
++					.cra_driver_name = "rk2-sha512",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = SHA512_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++	},
++	{
++		.type = CRYPTO_ALG_TYPE_AHASH,
++		.rk2_mode = RK2_CRYPTO_SM3,
++		.alg.hash.base = {
++			.init = rk2_ahash_init,
++			.update = rk2_ahash_update,
++			.final = rk2_ahash_final,
++			.finup = rk2_ahash_finup,
++			.export = rk2_ahash_export,
++			.import = rk2_ahash_import,
++			.digest = rk2_ahash_digest,
++			.init_tfm = rk2_hash_init_tfm,
++			.exit_tfm = rk2_hash_exit_tfm,
++			.halg = {
++				.digestsize = SM3_DIGEST_SIZE,
++				.statesize = sizeof(struct sm3_state),
++				.base = {
++					.cra_name = "sm3",
++					.cra_driver_name = "rk2-sm3",
++					.cra_priority = 300,
++					.cra_flags = CRYPTO_ALG_ASYNC |
++						CRYPTO_ALG_NEED_FALLBACK,
++					.cra_blocksize = SM3_BLOCK_SIZE,
++					.cra_ctxsize = sizeof(struct rk2_ahash_ctx),
++					.cra_module = THIS_MODULE,
++				}
++			}
++		},
++		.alg.hash.op = {
++			.do_one_request = rk2_hash_run,
++		},
++	},
++};
++
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG
++static int rk2_crypto_debugfs_stats_show(struct seq_file *seq, void *v)
++{
++	struct rk2_crypto_dev *rkc;
++	unsigned int i;
++
++	spin_lock(&rocklist.lock);
++	list_for_each_entry(rkc, &rocklist.dev_list, list) {
++		seq_printf(seq, "%s %s requests: %lu\n",
++			   dev_driver_string(rkc->dev), dev_name(rkc->dev),
++			   rkc->nreq);
++	}
++	spin_unlock(&rocklist.lock);
++
++	for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) {
++		if (!rk2_crypto_algs[i].dev)
++			continue;
++		switch (rk2_crypto_algs[i].type) {
++		case CRYPTO_ALG_TYPE_SKCIPHER:
++			seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n",
++				   rk2_crypto_algs[i].alg.skcipher.base.base.cra_driver_name,
++				   rk2_crypto_algs[i].alg.skcipher.base.base.cra_name,
++				   rk2_crypto_algs[i].stat_req, rk2_crypto_algs[i].stat_fb);
++			seq_printf(seq, "\tfallback due to length: %lu\n",
++				   rk2_crypto_algs[i].stat_fb_len);
++			seq_printf(seq, "\tfallback due to alignment: %lu\n",
++				   rk2_crypto_algs[i].stat_fb_align);
++			seq_printf(seq, "\tfallback due to SGs: %lu\n",
++				   rk2_crypto_algs[i].stat_fb_sgdiff);
++			break;
++		case CRYPTO_ALG_TYPE_AHASH:
++			seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n",
++				   rk2_crypto_algs[i].alg.hash.base.halg.base.cra_driver_name,
++				   rk2_crypto_algs[i].alg.hash.base.halg.base.cra_name,
++				   rk2_crypto_algs[i].stat_req, rk2_crypto_algs[i].stat_fb);
++			break;
++		}
++	}
++	return 0;
++}
++
++static int rk2_crypto_debugfs_info_show(struct seq_file *seq, void *d)
++{
++	struct rk2_crypto_dev *rkc;
++	u32 v;
++
++	spin_lock(&rocklist.lock);
++	list_for_each_entry(rkc, &rocklist.dev_list, list) {
++		v = readl(rkc->reg + RK2_CRYPTO_CLK_CTL);
++		seq_printf(seq, "CRYPTO_CLK_CTL %x\n", v);
++		v = readl(rkc->reg + RK2_CRYPTO_RST_CTL);
++		seq_printf(seq, "CRYPTO_RST_CTL %x\n", v);
++
++		v = readl(rkc->reg + CRYPTO_AES_VERSION);
++		seq_printf(seq, "CRYPTO_AES_VERSION %x\n", v);
++		if (v & BIT(17))
++			seq_puts(seq, "AES 192\n");
++
++		v = readl(rkc->reg + CRYPTO_DES_VERSION);
++		seq_printf(seq, "CRYPTO_DES_VERSION %x\n", v);
++		v = readl(rkc->reg + CRYPTO_SM4_VERSION);
++		seq_printf(seq, "CRYPTO_SM4_VERSION %x\n", v);
++		v = readl(rkc->reg + CRYPTO_HASH_VERSION);
++		seq_printf(seq, "CRYPTO_HASH_VERSION %x\n", v);
++		v = readl(rkc->reg + CRYPTO_HMAC_VERSION);
++		seq_printf(seq, "CRYPTO_HMAC_VERSION %x\n", v);
++	v = readl(rkc->reg + CRYPTO_RNG_VERSION);
++	seq_printf(seq, "CRYPTO_RNG_VERSION %x\n", v);
++	v = readl(rkc->reg + CRYPTO_PKA_VERSION);
++	seq_printf(seq, "CRYPTO_PKA_VERSION %x\n", v);
++	v = readl(rkc->reg + CRYPTO_CRYPTO_VERSION);
++	seq_printf(seq, "CRYPTO_CRYPTO_VERSION %x\n", v);
++	}
++	spin_unlock(&rocklist.lock);
++
++	return 0;
++}
++
++DEFINE_SHOW_ATTRIBUTE(rk2_crypto_debugfs_stats);
++DEFINE_SHOW_ATTRIBUTE(rk2_crypto_debugfs_info);
++
++#endif
++
++static void register_debugfs(struct rk2_crypto_dev *crypto_dev)
++{
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG
++	/* Ignore error of debugfs */
++	rocklist.dbgfs_dir = debugfs_create_dir("rk2_crypto", NULL);
++	rocklist.dbgfs_stats = debugfs_create_file("stats", 0440,
++						   rocklist.dbgfs_dir,
++						   &rocklist,
++						   &rk2_crypto_debugfs_stats_fops);
++	rocklist.dbgfs_stats = debugfs_create_file("info", 0440,
++						   rocklist.dbgfs_dir,
++						   &rocklist,
++						   &rk2_crypto_debugfs_info_fops);
++#endif
++}
++
++static int rk2_crypto_register(struct rk2_crypto_dev *rkc)
++{
++	unsigned int i, k;
++	int err = 0;
++
++	for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) {
++		rk2_crypto_algs[i].dev = rkc;
++		switch (rk2_crypto_algs[i].type) {
++		case CRYPTO_ALG_TYPE_SKCIPHER:
++			dev_info(rkc->dev, "Register %s as %s\n",
++				 rk2_crypto_algs[i].alg.skcipher.base.base.cra_name,
++				 rk2_crypto_algs[i].alg.skcipher.base.base.cra_driver_name);
++			err = crypto_engine_register_skcipher(&rk2_crypto_algs[i].alg.skcipher);
++			break;
++		case CRYPTO_ALG_TYPE_AHASH:
++			dev_info(rkc->dev, "Register %s as %s %d\n",
++				 rk2_crypto_algs[i].alg.hash.base.halg.base.cra_name,
++				 rk2_crypto_algs[i].alg.hash.base.halg.base.cra_driver_name, i);
++			err = crypto_engine_register_ahash(&rk2_crypto_algs[i].alg.hash);
++			break;
++		default:
++			dev_err(rkc->dev, "unknown algorithm\n");
++		}
++		if (err)
++			goto err_cipher_algs;
++	}
++	return 0;
++
++err_cipher_algs:
++	for (k = 0; k < i; k++) {
++		if (rk2_crypto_algs[k].type == CRYPTO_ALG_TYPE_SKCIPHER)
++			crypto_engine_unregister_skcipher(&rk2_crypto_algs[k].alg.skcipher);
++		else
++			crypto_engine_unregister_ahash(&rk2_crypto_algs[k].alg.hash);
++	}
++	return err;
++}
++
++static void rk2_crypto_unregister(void)
++{
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) {
++		if (rk2_crypto_algs[i].type == CRYPTO_ALG_TYPE_SKCIPHER)
++			crypto_engine_unregister_skcipher(&rk2_crypto_algs[i].alg.skcipher);
++		else
++			crypto_engine_unregister_ahash(&rk2_crypto_algs[i].alg.hash);
++	}
++}
++
++static const struct of_device_id crypto_of_id_table[] = {
++	{ .compatible = "rockchip,rk3568-crypto",
++	  .data = &rk3568_variant,
++	},
++	{ .compatible = "rockchip,rk3588-crypto",
++	  .data = &rk3588_variant,
++	},
++	{}
++};
++MODULE_DEVICE_TABLE(of, crypto_of_id_table);
++
++static int rk2_crypto_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct rk2_crypto_dev *rkc, *first;
++	int err = 0;
++
++	rkc = devm_kzalloc(&pdev->dev, sizeof(*rkc), GFP_KERNEL);
++	if (!rkc) {
++		err = -ENOMEM;
++		goto err_crypto;
++	}
++
++	rkc->dev = &pdev->dev;
++	platform_set_drvdata(pdev, rkc);
++
++	rkc->variant = of_device_get_match_data(&pdev->dev);
++	if (!rkc->variant) {
++		dev_err(&pdev->dev, "Missing variant\n");
++		return -EINVAL;
++	}
++
++	rkc->rst = devm_reset_control_array_get_exclusive(dev);
++	if (IS_ERR(rkc->rst)) {
++		err = PTR_ERR(rkc->rst);
++		dev_err(&pdev->dev, "Fail to get resets err=%d\n", err);
++		goto err_crypto;
++	}
++
++	rkc->tl = dma_alloc_coherent(rkc->dev,
++				     sizeof(struct rk2_crypto_lli) * MAX_LLI,
++				     &rkc->t_phy, GFP_KERNEL);
++	if (!rkc->tl) {
++		dev_err(rkc->dev, "Cannot get DMA memory for task\n");
++		err = -ENOMEM;
++		goto err_crypto;
++	}
++
++	reset_control_assert(rkc->rst);
++	usleep_range(10, 20);
++	reset_control_deassert(rkc->rst);
++
++	rkc->reg = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(rkc->reg)) {
++		err = PTR_ERR(rkc->reg);
++		dev_err(&pdev->dev, "Fail to get resources\n");
++		goto err_crypto;
++	}
++
++	err = rk2_crypto_get_clks(rkc);
++	if (err)
++		goto err_crypto;
++
++	rkc->irq = platform_get_irq(pdev, 0);
++	if (rkc->irq < 0) {
++		dev_err(&pdev->dev, "control Interrupt is not available.\n");
++		err = rkc->irq;
++		goto err_crypto;
++	}
++
++	err = devm_request_irq(&pdev->dev, rkc->irq,
++			       rk2_crypto_irq_handle, IRQF_SHARED,
++			       "rk-crypto", pdev);
++
++	if (err) {
++		dev_err(&pdev->dev, "irq request failed.\n");
++		goto err_crypto;
++	}
++
++	rkc->engine = crypto_engine_alloc_init(&pdev->dev, true);
++	crypto_engine_start(rkc->engine);
++	init_completion(&rkc->complete);
++
++	err = rk2_crypto_pm_init(rkc);
++	if (err)
++		goto err_pm;
++
++	err = pm_runtime_resume_and_get(&pdev->dev);
++
++	spin_lock(&rocklist.lock);
++	first = list_first_entry_or_null(&rocklist.dev_list,
++					 struct rk2_crypto_dev, list);
++	list_add_tail(&rkc->list, &rocklist.dev_list);
++	spin_unlock(&rocklist.lock);
++
++	if (!first) {
++		dev_info(dev, "Registers crypto algos\n");
++		err = rk2_crypto_register(rkc);
++		if (err) {
++			dev_err(dev, "Fail to register crypto algorithms");
++			goto err_register_alg;
++		}
++
++		register_debugfs(rkc);
++	}
++
++	return 0;
++
++err_register_alg:
++	rk2_crypto_pm_exit(rkc);
++err_pm:
++	crypto_engine_exit(rkc->engine);
++err_crypto:
++	dev_err(dev, "Crypto Accelerator not successfully registered\n");
++	return err;
++}
++
++static int rk2_crypto_remove(struct platform_device *pdev)
++{
++	struct rk2_crypto_dev *rkc = platform_get_drvdata(pdev);
++	struct rk2_crypto_dev *first;
++
++	spin_lock_bh(&rocklist.lock);
++	list_del(&rkc->list);
++	first = list_first_entry_or_null(&rocklist.dev_list,
++					 struct rk2_crypto_dev, list);
++	spin_unlock_bh(&rocklist.lock);
++
++	if (!first) {
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG
++		debugfs_remove_recursive(rocklist.dbgfs_dir);
++#endif
++		rk2_crypto_unregister();
++	}
++	rk2_crypto_pm_exit(rkc);
++	crypto_engine_exit(rkc->engine);
++	return 0;
++}
++
++static struct platform_driver crypto_driver = {
++	.probe		= rk2_crypto_probe,
++	.remove		= rk2_crypto_remove,
++	.driver		= {
++		.name	= "rk2-crypto",
++		.pm		= &rk2_crypto_pm_ops,
++		.of_match_table	= crypto_of_id_table,
++	},
++};
++
++module_platform_driver(crypto_driver);
++
++MODULE_DESCRIPTION("Rockchip Crypto Engine cryptographic offloader");
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Corentin Labbe <clabbe@baylibre.com>");
+diff --git a/drivers/crypto/rockchip/rk2_crypto.h b/drivers/crypto/rockchip/rk2_crypto.h
+new file mode 100644
+index 000000000000..59cd8be59f70
+--- /dev/null
++++ b/drivers/crypto/rockchip/rk2_crypto.h
+@@ -0,0 +1,246 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#include <crypto/aes.h>
++#include <crypto/xts.h>
++#include <crypto/engine.h>
++#include <crypto/internal/des.h>
++#include <crypto/internal/hash.h>
++#include <crypto/internal/skcipher.h>
++#include <crypto/algapi.h>
++#include <crypto/md5.h>
++#include <crypto/sha1.h>
++#include <crypto/sha2.h>
++#include <crypto/sm3.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/debugfs.h>
++#include <linux/delay.h>
++#include <linux/pm_runtime.h>
++#include <linux/scatterlist.h>
++#include <linux/hw_random.h>
++
++#define RK2_CRYPTO_CLK_CTL	0x0000
++#define RK2_CRYPTO_RST_CTL	0x0004
++
++#define RK2_CRYPTO_DMA_INT_EN	0x0008
++/* values for RK2_CRYPTO_DMA_INT_EN */
++#define RK2_CRYPTO_DMA_INT_LISTDONE	BIT(0)
++
++#define RK2_CRYPTO_DMA_INT_ST	0x000C
++/* values in RK2_CRYPTO_DMA_INT_ST are the same than in RK2_CRYPTO_DMA_INT_EN */
++
++#define RK2_CRYPTO_DMA_CTL	0x0010
++#define RK2_CRYPTO_DMA_CTL_START	BIT(0)
++
++#define RK2_CRYPTO_DMA_LLI_ADDR	0x0014
++#define RK2_CRYPTO_DMA_ST	0x0018
++#define RK2_CRYPTO_DMA_STATE	0x001C
++#define RK2_CRYPTO_DMA_LLI_RADDR	0x0020
++#define RK2_CRYPTO_DMA_SRC_RADDR	0x0024
++#define RK2_CRYPTO_DMA_DST_WADDR	0x0028
++#define RK2_CRYPTO_DMA_ITEM_ID		0x002C
++
++#define RK2_CRYPTO_FIFO_CTL	0x0040
++
++#define RK2_CRYPTO_BC_CTL	0x0044
++#define RK2_CRYPTO_AES		(0 << 8)
++#define RK2_CRYPTO_MODE_ECB	(0 << 4)
++#define RK2_CRYPTO_MODE_CBC	(1 << 4)
++#define RK2_CRYPTO_XTS		(6 << 4)
++
++#define RK2_CRYPTO_HASH_CTL	0x0048
++#define RK2_CRYPTO_HW_PAD	BIT(2)
++#define RK2_CRYPTO_SHA1		(0 << 4)
++#define RK2_CRYPTO_MD5		(1 << 4)
++#define RK2_CRYPTO_SHA224	(3 << 4)
++#define RK2_CRYPTO_SHA256	(2 << 4)
++#define RK2_CRYPTO_SHA384	(9 << 4)
++#define RK2_CRYPTO_SHA512	(8 << 4)
++#define RK2_CRYPTO_SM3		(4 << 4)
++
++#define RK2_CRYPTO_AES_ECB		(RK2_CRYPTO_AES | RK2_CRYPTO_MODE_ECB)
++#define RK2_CRYPTO_AES_CBC		(RK2_CRYPTO_AES | RK2_CRYPTO_MODE_CBC)
++#define RK2_CRYPTO_AES_XTS		(RK2_CRYPTO_AES | RK2_CRYPTO_XTS)
++#define RK2_CRYPTO_AES_CTR_MODE		3
++#define RK2_CRYPTO_AES_128BIT_key	(0 << 2)
++#define RK2_CRYPTO_AES_192BIT_key	(1 << 2)
++#define RK2_CRYPTO_AES_256BIT_key	(2 << 2)
++
++#define RK2_CRYPTO_DEC			BIT(1)
++#define RK2_CRYPTO_ENABLE		BIT(0)
++
++#define RK2_CRYPTO_CIPHER_ST	0x004C
++#define RK2_CRYPTO_CIPHER_STATE	0x0050
++
++#define RK2_CRYPTO_CH0_IV_0		0x0100
++
++#define RK2_CRYPTO_KEY0			0x0180
++#define RK2_CRYPTO_KEY1			0x0184
++#define RK2_CRYPTO_KEY2			0x0188
++#define RK2_CRYPTO_KEY3			0x018C
++#define RK2_CRYPTO_KEY4			0x0190
++#define RK2_CRYPTO_KEY5			0x0194
++#define RK2_CRYPTO_KEY6			0x0198
++#define RK2_CRYPTO_KEY7			0x019C
++#define RK2_CRYPTO_CH4_KEY0		0x01c0
++
++#define RK2_CRYPTO_CH0_PC_LEN_0		0x0280
++
++#define RK2_CRYPTO_CH0_IV_LEN		0x0300
++
++#define RK2_CRYPTO_HASH_DOUT_0	0x03A0
++#define RK2_CRYPTO_HASH_VALID	0x03E4
++
++#define RK2_CRYPTO_TRNG_CTL	0x0400
++#define RK2_CRYPTO_TRNG_START	BIT(0)
++#define RK2_CRYPTO_TRNG_ENABLE	BIT(1)
++#define RK2_CRYPTO_TRNG_256	(0x3 << 4)
++#define RK2_CRYPTO_TRNG_SAMPLE_CNT	0x0404
++#define RK2_CRYPTO_TRNG_DOUT	0x0410
++
++#define CRYPTO_AES_VERSION	0x0680
++#define CRYPTO_DES_VERSION	0x0684
++#define CRYPTO_SM4_VERSION	0x0688
++#define CRYPTO_HASH_VERSION	0x068C
++#define CRYPTO_HMAC_VERSION	0x0690
++#define CRYPTO_RNG_VERSION	0x0694
++#define CRYPTO_PKA_VERSION	0x0698
++#define CRYPTO_CRYPTO_VERSION	0x06F0
++
++#define RK2_LLI_DMA_CTRL_SRC_INT		BIT(10)
++#define RK2_LLI_DMA_CTRL_DST_INT		BIT(9)
++#define RK2_LLI_DMA_CTRL_LIST_INT	BIT(8)
++#define RK2_LLI_DMA_CTRL_LAST		BIT(0)
++
++#define RK2_LLI_STRING_LAST		BIT(2)
++#define RK2_LLI_STRING_FIRST		BIT(1)
++#define RK2_LLI_CIPHER_START		BIT(0)
++
++#define RK2_MAX_CLKS 4
++
++#define MAX_LLI 20
++
++struct rk2_crypto_lli {
++	__le32 src_addr;
++	__le32 src_len;
++	__le32 dst_addr;
++	__le32 dst_len;
++	__le32 user;
++	__le32 iv;
++	__le32 dma_ctrl;
++	__le32 next;
++};
++
++/*
++ * struct rockchip_ip - struct for managing a list of RK crypto instance
++ * @dev_list:		Used for doing a list of rk2_crypto_dev
++ * @lock:		Control access to dev_list
++ * @dbgfs_dir:		Debugfs dentry for statistic directory
++ * @dbgfs_stats:	Debugfs dentry for statistic counters
++ */
++struct rockchip_ip {
++	struct list_head	dev_list;
++	spinlock_t		lock; /* Control access to dev_list */
++	struct dentry		*dbgfs_dir;
++	struct dentry		*dbgfs_stats;
++};
++
++struct rk2_clks {
++	const char *name;
++	unsigned long max;
++};
++
++struct rk2_variant {
++	int num_clks;
++	struct rk2_clks rkclks[RK2_MAX_CLKS];
++};
++
++struct rk2_crypto_dev {
++	struct list_head		list;
++	struct device			*dev;
++	struct clk_bulk_data		*clks;
++	int				num_clks;
++	struct reset_control		*rst;
++	void __iomem			*reg;
++	int				irq;
++	const struct rk2_variant *variant;
++	unsigned long nreq;
++	struct crypto_engine *engine;
++	struct completion complete;
++	int status;
++	struct rk2_crypto_lli *tl;
++	dma_addr_t t_phy;
++};
++
++/* the private variable of hash */
++struct rk2_ahash_ctx {
++	/* for fallback */
++	struct crypto_ahash		*fallback_tfm;
++};
++
++/* the private variable of hash for fallback */
++struct rk2_ahash_rctx {
++	struct rk2_crypto_dev		*dev;
++	struct ahash_request		fallback_req;
++	u32				mode;
++	int nrsgs;
++};
++
++/* the private variable of cipher */
++struct rk2_cipher_ctx {
++	unsigned int			keylen;
++	u8				key[AES_MAX_KEY_SIZE * 2];
++	u8				iv[AES_BLOCK_SIZE];
++	struct crypto_skcipher *fallback_tfm;
++};
++
++struct rk2_cipher_rctx {
++	struct rk2_crypto_dev		*dev;
++	u8 backup_iv[AES_BLOCK_SIZE];
++	u32				mode;
++	struct skcipher_request fallback_req;   // keep at the end
++};
++
++struct rk2_crypto_template {
++	u32 type;
++	u32 rk2_mode;
++	bool is_xts;
++	struct rk2_crypto_dev           *dev;
++	union {
++		struct skcipher_engine_alg	skcipher;
++		struct ahash_engine_alg	hash;
++	} alg;
++	unsigned long stat_req;
++	unsigned long stat_fb;
++	unsigned long stat_fb_len;
++	unsigned long stat_fb_sglen;
++	unsigned long stat_fb_align;
++	unsigned long stat_fb_sgdiff;
++};
++
++struct rk2_crypto_dev *get_rk2_crypto(void);
++int rk2_cipher_run(struct crypto_engine *engine, void *async_req);
++int rk2_hash_run(struct crypto_engine *engine, void *breq);
++
++int rk2_cipher_tfm_init(struct crypto_skcipher *tfm);
++void rk2_cipher_tfm_exit(struct crypto_skcipher *tfm);
++int rk2_aes_setkey(struct crypto_skcipher *cipher, const u8 *key,
++		   unsigned int keylen);
++int rk2_aes_xts_setkey(struct crypto_skcipher *cipher, const u8 *key,
++		       unsigned int keylen);
++int rk2_skcipher_encrypt(struct skcipher_request *req);
++int rk2_skcipher_decrypt(struct skcipher_request *req);
++int rk2_aes_ecb_encrypt(struct skcipher_request *req);
++int rk2_aes_ecb_decrypt(struct skcipher_request *req);
++int rk2_aes_cbc_encrypt(struct skcipher_request *req);
++int rk2_aes_cbc_decrypt(struct skcipher_request *req);
++
++int rk2_ahash_init(struct ahash_request *req);
++int rk2_ahash_update(struct ahash_request *req);
++int rk2_ahash_final(struct ahash_request *req);
++int rk2_ahash_finup(struct ahash_request *req);
++int rk2_ahash_import(struct ahash_request *req, const void *in);
++int rk2_ahash_export(struct ahash_request *req, void *out);
++int rk2_ahash_digest(struct ahash_request *req);
++int rk2_hash_init_tfm(struct crypto_ahash *tfm);
++void rk2_hash_exit_tfm(struct crypto_ahash *tfm);
+diff --git a/drivers/crypto/rockchip/rk2_crypto_ahash.c b/drivers/crypto/rockchip/rk2_crypto_ahash.c
+new file mode 100644
+index 000000000000..75b8d9893447
+--- /dev/null
++++ b/drivers/crypto/rockchip/rk2_crypto_ahash.c
+@@ -0,0 +1,344 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Crypto offloader support for Rockchip RK3568/RK3588
++ *
++ * Copyright (c) 2022-2023 Corentin Labbe <clabbe@baylibre.com>
++ */
++#include <asm/unaligned.h>
++#include <linux/iopoll.h>
++#include "rk2_crypto.h"
++
++static bool rk2_ahash_need_fallback(struct ahash_request *areq)
++{
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
++	struct ahash_alg *alg = crypto_ahash_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base);
++	struct scatterlist *sg;
++
++	sg = areq->src;
++	while (sg) {
++		if (!IS_ALIGNED(sg->offset, sizeof(u32))) {
++			algt->stat_fb_align++;
++			return true;
++		}
++		if (sg->length % 4) {
++			algt->stat_fb_sglen++;
++			return true;
++		}
++		sg = sg_next(sg);
++	}
++	return false;
++}
++
++static int rk2_ahash_digest_fb(struct ahash_request *areq)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
++	struct rk2_ahash_ctx *tfmctx = crypto_ahash_ctx(tfm);
++	struct ahash_alg *alg = crypto_ahash_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base);
++
++	algt->stat_fb++;
++
++	ahash_request_set_tfm(&rctx->fallback_req, tfmctx->fallback_tfm);
++	rctx->fallback_req.base.flags = areq->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++
++	rctx->fallback_req.nbytes = areq->nbytes;
++	rctx->fallback_req.src = areq->src;
++	rctx->fallback_req.result = areq->result;
++
++	return crypto_ahash_digest(&rctx->fallback_req);
++}
++
++static int zero_message_process(struct ahash_request *req)
++{
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct ahash_alg *alg = crypto_ahash_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base);
++	int digestsize = crypto_ahash_digestsize(tfm);
++
++	switch (algt->rk2_mode) {
++	case RK2_CRYPTO_SHA1:
++		memcpy(req->result, sha1_zero_message_hash, digestsize);
++		break;
++	case RK2_CRYPTO_SHA256:
++		memcpy(req->result, sha256_zero_message_hash, digestsize);
++		break;
++	case RK2_CRYPTO_SHA384:
++		memcpy(req->result, sha384_zero_message_hash, digestsize);
++		break;
++	case RK2_CRYPTO_SHA512:
++		memcpy(req->result, sha512_zero_message_hash, digestsize);
++		break;
++	case RK2_CRYPTO_MD5:
++		memcpy(req->result, md5_zero_message_hash, digestsize);
++		break;
++	case RK2_CRYPTO_SM3:
++		memcpy(req->result, sm3_zero_message_hash, digestsize);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++int rk2_ahash_init(struct ahash_request *req)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++
++	return crypto_ahash_init(&rctx->fallback_req);
++}
++
++int rk2_ahash_update(struct ahash_request *req)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++	rctx->fallback_req.nbytes = req->nbytes;
++	rctx->fallback_req.src = req->src;
++
++	return crypto_ahash_update(&rctx->fallback_req);
++}
++
++int rk2_ahash_final(struct ahash_request *req)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++	rctx->fallback_req.result = req->result;
++
++	return crypto_ahash_final(&rctx->fallback_req);
++}
++
++int rk2_ahash_finup(struct ahash_request *req)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++
++	rctx->fallback_req.nbytes = req->nbytes;
++	rctx->fallback_req.src = req->src;
++	rctx->fallback_req.result = req->result;
++
++	return crypto_ahash_finup(&rctx->fallback_req);
++}
++
++int rk2_ahash_import(struct ahash_request *req, const void *in)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++
++	return crypto_ahash_import(&rctx->fallback_req, in);
++}
++
++int rk2_ahash_export(struct ahash_request *req, void *out)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
++
++	ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
++	rctx->fallback_req.base.flags = req->base.flags &
++					CRYPTO_TFM_REQ_MAY_SLEEP;
++
++	return crypto_ahash_export(&rctx->fallback_req, out);
++}
++
++int rk2_ahash_digest(struct ahash_request *req)
++{
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(req);
++	struct rk2_crypto_dev *dev;
++	struct crypto_engine *engine;
++
++	if (rk2_ahash_need_fallback(req))
++		return rk2_ahash_digest_fb(req);
++
++	if (!req->nbytes)
++		return zero_message_process(req);
++
++	dev = get_rk2_crypto();
++
++	rctx->dev = dev;
++	engine = dev->engine;
++
++	return crypto_transfer_hash_request_to_engine(engine, req);
++}
++
++static int rk2_hash_prepare(struct crypto_engine *engine, void *breq)
++{
++	struct ahash_request *areq = container_of(breq, struct ahash_request, base);
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq);
++	struct rk2_crypto_dev *rkc = rctx->dev;
++	int ret;
++
++	ret = dma_map_sg(rkc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE);
++	if (ret <= 0)
++		return -EINVAL;
++
++	rctx->nrsgs = ret;
++
++	return 0;
++}
++
++static void rk2_hash_unprepare(struct crypto_engine *engine, void *breq)
++{
++	struct ahash_request *areq = container_of(breq, struct ahash_request, base);
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq);
++	struct rk2_crypto_dev *rkc = rctx->dev;
++
++	dma_unmap_sg(rkc->dev, areq->src, rctx->nrsgs, DMA_TO_DEVICE);
++}
++
++int rk2_hash_run(struct crypto_engine *engine, void *breq)
++{
++	struct ahash_request *areq = container_of(breq, struct ahash_request, base);
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
++	struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq);
++	struct ahash_alg *alg = crypto_ahash_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base);
++	struct scatterlist *sgs = areq->src;
++	struct rk2_crypto_dev *rkc = rctx->dev;
++	struct rk2_crypto_lli *dd = &rkc->tl[0];
++	int ddi = 0;
++	int err = 0;
++	unsigned int len = areq->nbytes;
++	unsigned int todo;
++	u32 v;
++	int i;
++
++	err = rk2_hash_prepare(engine, breq);
++
++	err = pm_runtime_resume_and_get(rkc->dev);
++	if (err)
++		return err;
++
++	dev_dbg(rkc->dev, "%s %s len=%d\n", __func__,
++		crypto_tfm_alg_name(areq->base.tfm), areq->nbytes);
++
++	algt->stat_req++;
++	rkc->nreq++;
++
++	rctx->mode = algt->rk2_mode;
++	rctx->mode |= 0xffff0000;
++	rctx->mode |= RK2_CRYPTO_ENABLE | RK2_CRYPTO_HW_PAD;
++	writel(rctx->mode, rkc->reg + RK2_CRYPTO_HASH_CTL);
++
++	while (sgs && len > 0) {
++		dd = &rkc->tl[ddi];
++
++		todo = min(sg_dma_len(sgs), len);
++		dd->src_addr = sg_dma_address(sgs);
++		dd->src_len = todo;
++		dd->dst_addr = 0;
++		dd->dst_len = 0;
++		dd->dma_ctrl = ddi << 24;
++		dd->iv = 0;
++		dd->next = rkc->t_phy + sizeof(struct rk2_crypto_lli) * (ddi + 1);
++
++		if (ddi == 0)
++			dd->user = RK2_LLI_CIPHER_START | RK2_LLI_STRING_FIRST;
++		else
++			dd->user = 0;
++
++		len -= todo;
++		dd->dma_ctrl |= RK2_LLI_DMA_CTRL_SRC_INT;
++		if (len == 0) {
++			dd->user |= RK2_LLI_STRING_LAST;
++			dd->dma_ctrl |= RK2_LLI_DMA_CTRL_LAST;
++		}
++		dev_dbg(rkc->dev, "HASH SG %d sglen=%d user=%x dma=%x mode=%x len=%d todo=%d phy=%llx\n",
++			ddi, sgs->length, dd->user, dd->dma_ctrl, rctx->mode, len, todo, rkc->t_phy);
++
++		sgs = sg_next(sgs);
++		ddi++;
++	}
++	dd->next = 1;
++	writel(RK2_CRYPTO_DMA_INT_LISTDONE | 0x7F, rkc->reg + RK2_CRYPTO_DMA_INT_EN);
++
++	writel(rkc->t_phy, rkc->reg + RK2_CRYPTO_DMA_LLI_ADDR);
++
++	reinit_completion(&rkc->complete);
++	rkc->status = 0;
++
++	writel(RK2_CRYPTO_DMA_CTL_START | RK2_CRYPTO_DMA_CTL_START << 16, rkc->reg + RK2_CRYPTO_DMA_CTL);
++
++	wait_for_completion_interruptible_timeout(&rkc->complete,
++						  msecs_to_jiffies(2000));
++	if (!rkc->status) {
++		dev_err(rkc->dev, "DMA timeout\n");
++		err = -EFAULT;
++		goto theend;
++	}
++
++	readl_poll_timeout_atomic(rkc->reg + RK2_CRYPTO_HASH_VALID, v, v == 1,
++				  10, 1000);
++
++	for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) {
++		v = readl(rkc->reg + RK2_CRYPTO_HASH_DOUT_0 + i * 4);
++		put_unaligned_le32(be32_to_cpu(v), areq->result + i * 4);
++	}
++
++theend:
++	pm_runtime_put_autosuspend(rkc->dev);
++
++	rk2_hash_unprepare(engine, breq);
++
++	local_bh_disable();
++	crypto_finalize_hash_request(engine, breq, err);
++	local_bh_enable();
++
++	return 0;
++}
++
++int rk2_hash_init_tfm(struct crypto_ahash *tfm)
++{
++	struct rk2_ahash_ctx *tctx = crypto_ahash_ctx(tfm);
++	const char *alg_name = crypto_ahash_alg_name(tfm);
++	struct ahash_alg *alg = crypto_ahash_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base);
++
++	/* for fallback */
++	tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0,
++						CRYPTO_ALG_NEED_FALLBACK);
++	if (IS_ERR(tctx->fallback_tfm)) {
++		dev_err(algt->dev->dev, "Could not load fallback driver.\n");
++		return PTR_ERR(tctx->fallback_tfm);
++	}
++
++	crypto_ahash_set_reqsize(tfm,
++				 sizeof(struct rk2_ahash_rctx) +
++				 crypto_ahash_reqsize(tctx->fallback_tfm));
++	return 0;
++}
++
++void rk2_hash_exit_tfm(struct crypto_ahash *tfm)
++{
++	struct rk2_ahash_ctx *tctx = crypto_ahash_ctx(tfm);
++
++	crypto_free_ahash(tctx->fallback_tfm);
++}
+diff --git a/drivers/crypto/rockchip/rk2_crypto_skcipher.c b/drivers/crypto/rockchip/rk2_crypto_skcipher.c
+new file mode 100644
+index 000000000000..3e8e44d84b47
+--- /dev/null
++++ b/drivers/crypto/rockchip/rk2_crypto_skcipher.c
+@@ -0,0 +1,576 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * hardware cryptographic offloader for RK3568/RK3588 SoC
++ *
++ * Copyright (c) 2022-2023 Corentin Labbe <clabbe@baylibre.com>
++ */
++#include <crypto/scatterwalk.h>
++#include "rk2_crypto.h"
++
++static void rk2_print(struct rk2_crypto_dev *rkc)
++{
++	u32 v;
++
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_ST);
++	dev_info(rkc->dev, "DMA_ST %x\n", v);
++	switch (v) {
++	case 0:
++		dev_info(rkc->dev, "DMA_ST: DMA IDLE\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "DMA_ST: DMA BUSY\n");
++		break;
++	default:
++		dev_err(rkc->dev, "DMA_ST: invalid value\n");
++	}
++
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_STATE);
++	dev_info(rkc->dev, "DMA_STATE %x\n", v);
++
++	switch (v & 0x3) {
++	case 0:
++		dev_info(rkc->dev, "DMA_STATE: DMA DST IDLE\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "DMA_STATE: DMA DST LOAD\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "DMA_STATE: DMA DST WORK\n");
++		break;
++	default:
++		dev_err(rkc->dev, "DMA DST invalid\n");
++		break;
++	}
++	switch (v & 0xC) {
++	case 0:
++		dev_info(rkc->dev, "DMA_STATE: DMA SRC IDLE\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "DMA_STATE: DMA SRC LOAD\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "DMA_STATE: DMA SRC WORK\n");
++		break;
++	default:
++		dev_err(rkc->dev, "DMA_STATE: DMA SRC invalid\n");
++		break;
++	}
++	switch (v & 0x30) {
++	case 0:
++		dev_info(rkc->dev, "DMA_STATE: DMA LLI IDLE\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "DMA_STATE: DMA LLI LOAD\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "DMA LLI WORK\n");
++		break;
++	default:
++		dev_err(rkc->dev, "DMA LLI invalid\n");
++		break;
++	}
++
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_LLI_RADDR);
++	dev_info(rkc->dev, "DMA_LLI_RADDR %x\n", v);
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_SRC_RADDR);
++	dev_info(rkc->dev, "DMA_SRC_RADDR %x\n", v);
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_DST_WADDR);
++	dev_info(rkc->dev, "DMA_LLI_WADDR %x\n", v);
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_ITEM_ID);
++	dev_info(rkc->dev, "DMA_LLI_ITEMID %x\n", v);
++
++	v = readl(rkc->reg + RK2_CRYPTO_CIPHER_ST);
++	dev_info(rkc->dev, "CIPHER_ST %x\n", v);
++	if (v & BIT(0))
++		dev_info(rkc->dev, "CIPHER_ST: BLOCK CIPHER BUSY\n");
++	else
++		dev_info(rkc->dev, "CIPHER_ST: BLOCK CIPHER IDLE\n");
++	if (v & BIT(2))
++		dev_info(rkc->dev, "CIPHER_ST: HASH BUSY\n");
++	else
++		dev_info(rkc->dev, "CIPHER_ST: HASH IDLE\n");
++	if (v & BIT(2))
++		dev_info(rkc->dev, "CIPHER_ST: OTP KEY VALID\n");
++	else
++		dev_info(rkc->dev, "CIPHER_ST: OTP KEY INVALID\n");
++
++	v = readl(rkc->reg + RK2_CRYPTO_CIPHER_STATE);
++	dev_info(rkc->dev, "CIPHER_STATE %x\n", v);
++	switch (v & 0x3) {
++	case 0:
++		dev_info(rkc->dev, "serial: IDLE state\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "serial: PRE state\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "serial: BULK state\n");
++		break;
++	default:
++		dev_info(rkc->dev, "serial: reserved state\n");
++		break;
++	}
++	switch (v & 0xC) {
++	case 0:
++		dev_info(rkc->dev, "mac_state: IDLE state\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "mac_state: PRE state\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "mac_state: BULK state\n");
++		break;
++	default:
++		dev_info(rkc->dev, "mac_state: reserved state\n");
++		break;
++	}
++	switch (v & 0x30) {
++	case 0:
++		dev_info(rkc->dev, "parallel_state: IDLE state\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "parallel_state: PRE state\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "parallel_state: BULK state\n");
++		break;
++	default:
++		dev_info(rkc->dev, "parallel_state: reserved state\n");
++		break;
++	}
++	switch (v & 0xC0) {
++	case 0:
++		dev_info(rkc->dev, "ccm_state: IDLE state\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "ccm_state: PRE state\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "ccm_state: NA state\n");
++		break;
++	default:
++		dev_info(rkc->dev, "ccm_state: reserved state\n");
++		break;
++	}
++	switch (v & 0xF00) {
++	case 0:
++		dev_info(rkc->dev, "gcm_state: IDLE state\n");
++		break;
++	case 1:
++		dev_info(rkc->dev, "gcm_state: PRE state\n");
++		break;
++	case 2:
++		dev_info(rkc->dev, "gcm_state: NA state\n");
++		break;
++	case 3:
++		dev_info(rkc->dev, "gcm_state: PC state\n");
++		break;
++	}
++	switch (v & 0xC00) {
++	case 0x1:
++		dev_info(rkc->dev, "hash_state: IDLE state\n");
++		break;
++	case 0x2:
++		dev_info(rkc->dev, "hash_state: IPAD state\n");
++		break;
++	case 0x4:
++		dev_info(rkc->dev, "hash_state: TEXT state\n");
++		break;
++	case 0x8:
++		dev_info(rkc->dev, "hash_state: OPAD state\n");
++		break;
++	case 0x10:
++		dev_info(rkc->dev, "hash_state: OPAD EXT state\n");
++		break;
++	default:
++		dev_info(rkc->dev, "hash_state: invalid state\n");
++		break;
++	}
++
++	v = readl(rkc->reg + RK2_CRYPTO_DMA_INT_ST);
++	dev_info(rkc->dev, "RK2_CRYPTO_DMA_INT_ST %x\n", v);
++}
++
++static int rk2_cipher_need_fallback(struct skcipher_request *req)
++{
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++	struct scatterlist *sgs, *sgd;
++	unsigned int stodo, dtodo, len;
++	unsigned int bs = crypto_skcipher_blocksize(tfm);
++
++	if (!req->cryptlen)
++		return true;
++
++	if (algt->is_xts) {
++		if (sg_nents_for_len(req->src, req->cryptlen) > 1)
++			return true;
++		if (sg_nents_for_len(req->dst, req->cryptlen) > 1)
++			return true;
++	}
++
++	len = req->cryptlen;
++	sgs = req->src;
++	sgd = req->dst;
++	while (sgs && sgd) {
++		if (!IS_ALIGNED(sgs->offset, sizeof(u32))) {
++			algt->stat_fb_align++;
++			return true;
++		}
++		if (!IS_ALIGNED(sgd->offset, sizeof(u32))) {
++			algt->stat_fb_align++;
++			return true;
++		}
++		stodo = min(len, sgs->length);
++		if (stodo % bs) {
++			algt->stat_fb_len++;
++			return true;
++		}
++		dtodo = min(len, sgd->length);
++		if (dtodo % bs) {
++			algt->stat_fb_len++;
++			return true;
++		}
++		if (stodo != dtodo) {
++			algt->stat_fb_sgdiff++;
++			return true;
++		}
++		len -= stodo;
++		sgs = sg_next(sgs);
++		sgd = sg_next(sgd);
++	}
++	return false;
++}
++
++static int rk2_cipher_fallback(struct skcipher_request *areq)
++{
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
++	struct rk2_cipher_ctx *op = crypto_skcipher_ctx(tfm);
++	struct rk2_cipher_rctx *rctx = skcipher_request_ctx(areq);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++	int err;
++
++	algt->stat_fb++;
++
++	skcipher_request_set_tfm(&rctx->fallback_req, op->fallback_tfm);
++	skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags,
++				      areq->base.complete, areq->base.data);
++	skcipher_request_set_crypt(&rctx->fallback_req, areq->src, areq->dst,
++				   areq->cryptlen, areq->iv);
++	if (rctx->mode & RK2_CRYPTO_DEC)
++		err = crypto_skcipher_decrypt(&rctx->fallback_req);
++	else
++		err = crypto_skcipher_encrypt(&rctx->fallback_req);
++	return err;
++}
++
++static int rk2_cipher_handle_req(struct skcipher_request *req)
++{
++	struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req);
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++	struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++	struct rk2_crypto_dev *rkc;
++	struct crypto_engine *engine;
++
++	if (ctx->keylen == AES_KEYSIZE_192 * 2)
++		return rk2_cipher_fallback(req);
++
++	if (rk2_cipher_need_fallback(req))
++		return rk2_cipher_fallback(req);
++
++	rkc = get_rk2_crypto();
++
++	engine = rkc->engine;
++	rctx->dev = rkc;
++
++	return crypto_transfer_skcipher_request_to_engine(engine, req);
++}
++
++int rk2_aes_xts_setkey(struct crypto_skcipher *cipher, const u8 *key,
++		       unsigned int keylen)
++{
++	struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher);
++	struct rk2_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
++	int err;
++
++	err = xts_verify_key(cipher, key, keylen);
++	if (err)
++		return err;
++
++	ctx->keylen = keylen;
++	memcpy(ctx->key, key, keylen);
++
++	return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen);
++}
++
++int rk2_aes_setkey(struct crypto_skcipher *cipher, const u8 *key,
++		   unsigned int keylen)
++{
++	struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher);
++	struct rk2_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
++
++	if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
++	    keylen != AES_KEYSIZE_256)
++		return -EINVAL;
++	ctx->keylen = keylen;
++	memcpy(ctx->key, key, keylen);
++
++	return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen);
++}
++
++int rk2_skcipher_encrypt(struct skcipher_request *req)
++{
++	struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req);
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++
++	rctx->mode = algt->rk2_mode;
++	return rk2_cipher_handle_req(req);
++}
++
++int rk2_skcipher_decrypt(struct skcipher_request *req)
++{
++	struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req);
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++
++	rctx->mode = algt->rk2_mode | RK2_CRYPTO_DEC;
++	return rk2_cipher_handle_req(req);
++}
++
++int rk2_cipher_run(struct crypto_engine *engine, void *async_req)
++{
++	struct skcipher_request *areq = container_of(async_req, struct skcipher_request, base);
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
++	struct rk2_cipher_rctx *rctx = skcipher_request_ctx(areq);
++	struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++	struct scatterlist *sgs, *sgd;
++	int err = 0;
++	int ivsize = crypto_skcipher_ivsize(tfm);
++	unsigned int len = areq->cryptlen;
++	unsigned int todo;
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++	struct rk2_crypto_dev *rkc = rctx->dev;
++	struct rk2_crypto_lli *dd = &rkc->tl[0];
++	u32 m, v;
++	u32 *rkey = (u32 *)ctx->key;
++	u32 *riv = (u32 *)areq->iv;
++	int i;
++	unsigned int offset;
++
++	algt->stat_req++;
++	rkc->nreq++;
++
++	m = rctx->mode | RK2_CRYPTO_ENABLE;
++	if (algt->is_xts) {
++		switch (ctx->keylen) {
++		case AES_KEYSIZE_128 * 2:
++			m |= RK2_CRYPTO_AES_128BIT_key;
++			break;
++		case AES_KEYSIZE_256 * 2:
++			m |= RK2_CRYPTO_AES_256BIT_key;
++			break;
++		default:
++			dev_err(rkc->dev, "Invalid key length %u\n", ctx->keylen);
++			return -EINVAL;
++		}
++	} else {
++		switch (ctx->keylen) {
++		case AES_KEYSIZE_128:
++			m |= RK2_CRYPTO_AES_128BIT_key;
++			break;
++		case AES_KEYSIZE_192:
++			m |= RK2_CRYPTO_AES_192BIT_key;
++			break;
++		case AES_KEYSIZE_256:
++			m |= RK2_CRYPTO_AES_256BIT_key;
++			break;
++		default:
++			dev_err(rkc->dev, "Invalid key length %u\n", ctx->keylen);
++			return -EINVAL;
++		}
++	}
++
++	err = pm_runtime_resume_and_get(rkc->dev);
++	if (err)
++		return err;
++
++	/* the upper bits are a write enable mask, so we need to write 1 to all
++	 * upper 16 bits to allow write to the 16 lower bits
++	 */
++	m |= 0xffff0000;
++
++	dev_dbg(rkc->dev, "%s %s len=%u keylen=%u mode=%x\n", __func__,
++		crypto_tfm_alg_name(areq->base.tfm),
++		areq->cryptlen, ctx->keylen, m);
++	sgs = areq->src;
++	sgd = areq->dst;
++
++	while (sgs && sgd && len) {
++		ivsize = crypto_skcipher_ivsize(tfm);
++		if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) {
++			if (rctx->mode & RK2_CRYPTO_DEC) {
++				offset = sgs->length - ivsize;
++				scatterwalk_map_and_copy(rctx->backup_iv, sgs,
++							 offset, ivsize, 0);
++			}
++		}
++
++		dev_dbg(rkc->dev, "SG len=%u mode=%x ivsize=%u\n", sgs->length, m, ivsize);
++
++		if (sgs == sgd) {
++			err = dma_map_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL);
++			if (err != 1) {
++				dev_err(rkc->dev, "Invalid sg number %d\n", err);
++				err = -EINVAL;
++				goto theend;
++			}
++		} else {
++			err = dma_map_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE);
++			if (err != 1) {
++				dev_err(rkc->dev, "Invalid sg number %d\n", err);
++				err = -EINVAL;
++				goto theend;
++			}
++			err = dma_map_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE);
++			if (err != 1) {
++				dev_err(rkc->dev, "Invalid sg number %d\n", err);
++				err = -EINVAL;
++				dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE);
++				goto theend;
++			}
++		}
++		err = 0;
++		writel(m, rkc->reg + RK2_CRYPTO_BC_CTL);
++
++		if (algt->is_xts) {
++			for (i = 0; i < ctx->keylen / 8; i++) {
++				v = cpu_to_be32(rkey[i]);
++				writel(v, rkc->reg + RK2_CRYPTO_KEY0 + i * 4);
++			}
++			for (i = 0; i < (ctx->keylen / 8); i++) {
++				v = cpu_to_be32(rkey[i + ctx->keylen / 8]);
++				writel(v, rkc->reg + RK2_CRYPTO_CH4_KEY0 + i * 4);
++			}
++		} else {
++			for (i = 0; i < ctx->keylen / 4; i++) {
++				v = cpu_to_be32(rkey[i]);
++				writel(v, rkc->reg + RK2_CRYPTO_KEY0 + i * 4);
++			}
++		}
++
++		if (ivsize) {
++			for (i = 0; i < ivsize / 4; i++)
++				writel(cpu_to_be32(riv[i]),
++				       rkc->reg + RK2_CRYPTO_CH0_IV_0 + i * 4);
++			writel(ivsize, rkc->reg + RK2_CRYPTO_CH0_IV_LEN);
++		}
++		if (!sgs->length) {
++			sgs = sg_next(sgs);
++			sgd = sg_next(sgd);
++			continue;
++		}
++
++		/* The hw support multiple descriptor, so why this driver use
++		 * only one descriptor ?
++		 * Using one descriptor per SG seems the way to do and it works
++		 * but only when doing encryption.
++		 * With decryption it always fail on second descriptor.
++		 * Probably the HW dont know how to use IV.
++		 */
++		todo = min(sg_dma_len(sgs), len);
++		len -= todo;
++		dd->src_addr = sg_dma_address(sgs);
++		dd->src_len = todo;
++		dd->dst_addr = sg_dma_address(sgd);
++		dd->dst_len = todo;
++		dd->iv = 0;
++		dd->next = 1;
++
++		dd->user = RK2_LLI_CIPHER_START | RK2_LLI_STRING_FIRST | RK2_LLI_STRING_LAST;
++		dd->dma_ctrl |= RK2_LLI_DMA_CTRL_DST_INT | RK2_LLI_DMA_CTRL_LAST;
++
++		writel(RK2_CRYPTO_DMA_INT_LISTDONE | 0x7F, rkc->reg + RK2_CRYPTO_DMA_INT_EN);
++
++		/*writel(0x00030000, rkc->reg + RK2_CRYPTO_FIFO_CTL);*/
++		writel(rkc->t_phy, rkc->reg + RK2_CRYPTO_DMA_LLI_ADDR);
++
++		reinit_completion(&rkc->complete);
++		rkc->status = 0;
++
++		writel(RK2_CRYPTO_DMA_CTL_START | 1 << 16, rkc->reg + RK2_CRYPTO_DMA_CTL);
++
++		wait_for_completion_interruptible_timeout(&rkc->complete,
++							  msecs_to_jiffies(10000));
++		if (sgs == sgd) {
++			dma_unmap_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL);
++		} else {
++			dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE);
++			dma_unmap_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE);
++		}
++
++		if (!rkc->status) {
++			dev_err(rkc->dev, "DMA timeout\n");
++			rk2_print(rkc);
++			err = -EFAULT;
++			goto theend;
++		}
++		if (areq->iv && ivsize > 0) {
++			offset = sgd->length - ivsize;
++			if (rctx->mode & RK2_CRYPTO_DEC) {
++				memcpy(areq->iv, rctx->backup_iv, ivsize);
++				memzero_explicit(rctx->backup_iv, ivsize);
++			} else {
++				scatterwalk_map_and_copy(areq->iv, sgd, offset,
++							 ivsize, 0);
++			}
++		}
++		sgs = sg_next(sgs);
++		sgd = sg_next(sgd);
++	}
++theend:
++	writel(0xffff0000, rkc->reg + RK2_CRYPTO_BC_CTL);
++	pm_runtime_put_autosuspend(rkc->dev);
++
++	local_bh_disable();
++	crypto_finalize_skcipher_request(engine, areq, err);
++	local_bh_enable();
++	return 0;
++}
++
++int rk2_cipher_tfm_init(struct crypto_skcipher *tfm)
++{
++	struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++	const char *name = crypto_tfm_alg_name(&tfm->base);
++	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++	struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base);
++
++	ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
++	if (IS_ERR(ctx->fallback_tfm)) {
++		dev_err(algt->dev->dev, "ERROR: Cannot allocate fallback for %s %ld\n",
++			name, PTR_ERR(ctx->fallback_tfm));
++		return PTR_ERR(ctx->fallback_tfm);
++	}
++
++	dev_info(algt->dev->dev, "Fallback for %s is %s\n",
++		 crypto_tfm_alg_driver_name(&tfm->base),
++		 crypto_tfm_alg_driver_name(crypto_skcipher_tfm(ctx->fallback_tfm)));
++
++	tfm->reqsize = sizeof(struct rk2_cipher_rctx) +
++		crypto_skcipher_reqsize(ctx->fallback_tfm);
++
++	return 0;
++}
++
++void rk2_cipher_tfm_exit(struct crypto_skcipher *tfm)
++{
++	struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++
++	memzero_explicit(ctx->key, ctx->keylen);
++	crypto_free_skcipher(ctx->fallback_tfm);
++}
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/wifi-4003-add-bcm43342-chip.patch b/patch/kernel/archive/rockchip64-6.10/wifi-4003-add-bcm43342-chip.patch
new file mode 100644
index 000000000000..e0307dc9c54b
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/wifi-4003-add-bcm43342-chip.patch
@@ -0,0 +1,45 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Thu, 10 Feb 2022 21:30:54 +0000
+Subject: add broadcom bcm43342 chip id
+
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c       | 2 ++
+ drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h | 1 +
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+index 6b38d9de71af..6a603d045103 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+@@ -609,6 +609,7 @@ BRCMF_FW_DEF(4329, "brcmfmac4329-sdio");
+ BRCMF_FW_DEF(4330, "brcmfmac4330-sdio");
+ BRCMF_FW_DEF(4334, "brcmfmac4334-sdio");
+ BRCMF_FW_DEF(43340, "brcmfmac43340-sdio");
++BRCMF_FW_DEF(43342, "brcmfmac43342-sdio");
+ BRCMF_FW_DEF(4335, "brcmfmac4335-sdio");
+ BRCMF_FW_DEF(43362, "brcmfmac43362-sdio");
+ BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
+@@ -642,6 +643,7 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
+ 	BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
++	BRCMF_FW_ENTRY(BRCM_CC_43342_CHIP_ID, 0xFFFFFFFF, 43342),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
+diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+index 44684bf1b9ac..bcf48de78d53 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
++++ b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+@@ -27,6 +27,7 @@
+ #define BRCM_CC_4334_CHIP_ID		0x4334
+ #define BRCM_CC_43340_CHIP_ID		43340
+ #define BRCM_CC_43341_CHIP_ID		43341
++#define BRCM_CC_43342_CHIP_ID		43342
+ #define BRCM_CC_43362_CHIP_ID		43362
+ #define BRCM_CC_4335_CHIP_ID		0x4335
+ #define BRCM_CC_4339_CHIP_ID		0x4339
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.10/wifi-4003-ssv-6051-driver.patch b/patch/kernel/archive/rockchip64-6.10/wifi-4003-ssv-6051-driver.patch
new file mode 100644
index 000000000000..ed72e2aa1320
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.10/wifi-4003-ssv-6051-driver.patch
@@ -0,0 +1,49482 @@
+From 3f30a652fb3e6ead83f65312d0240d5c9ea8c340 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Wed, 2 Nov 2022 15:40:06 +0000
+Subject: [PATCH] add ssv6xxx wifi driver
+
+---
+ drivers/net/wireless/Kconfig                  |     1 +
+ drivers/net/wireless/Makefile                 |     1 +
+ drivers/net/wireless/ssv6051/Kconfig          |    11 +
+ drivers/net/wireless/ssv6051/Makefile         |    26 +
+ drivers/net/wireless/ssv6051/Makefile.bak     |   107 +
+ .../ssv6051/firmware/ssv6051-wifi.cfg         |    91 +
+ drivers/net/wireless/ssv6051/hci/hctrl.h      |   178 +
+ drivers/net/wireless/ssv6051/hci/ssv_hci.c    |   967 +
+ drivers/net/wireless/ssv6051/hci/ssv_hci.h    |    77 +
+ drivers/net/wireless/ssv6051/hwif/hwif.h      |    84 +
+ drivers/net/wireless/ssv6051/hwif/sdio/sdio.c |  1254 ++
+ .../net/wireless/ssv6051/hwif/sdio/sdio_def.h |    80 +
+ drivers/net/wireless/ssv6051/include/cabrio.h |    28 +
+ .../net/wireless/ssv6051/include/ssv6200.h    |    76 +
+ .../wireless/ssv6051/include/ssv6200_aux.h    | 18221 ++++++++++++++++
+ .../wireless/ssv6051/include/ssv6200_common.h |   452 +
+ .../ssv6051/include/ssv6200_configuration.h   |   317 +
+ .../wireless/ssv6051/include/ssv6200_reg.h    |  9694 ++++++++
+ .../ssv6051/include/ssv6200_reg_sim.h         |   176 +
+ .../net/wireless/ssv6051/include/ssv_cfg.h    |    60 +
+ .../ssv6051/include/ssv_firmware_version.h    |    25 +
+ .../wireless/ssv6051/include/ssv_version.h    |    12 +
+ .../net/wireless/ssv6051/platform-config.mak  |    97 +
+ drivers/net/wireless/ssv6051/rules.mak        |    19 +
+ drivers/net/wireless/ssv6051/smac/ampdu.c     |  2111 ++
+ drivers/net/wireless/ssv6051/smac/ampdu.h     |   215 +
+ drivers/net/wireless/ssv6051/smac/ap.c        |   598 +
+ drivers/net/wireless/ssv6051/smac/ap.h        |    41 +
+ drivers/net/wireless/ssv6051/smac/dev.c       |  3880 ++++
+ drivers/net/wireless/ssv6051/smac/dev.h       |   445 +
+ drivers/net/wireless/ssv6051/smac/dev_tbl.h   |   141 +
+ drivers/net/wireless/ssv6051/smac/drv_comm.h  |    61 +
+ drivers/net/wireless/ssv6051/smac/efuse.c     |   334 +
+ drivers/net/wireless/ssv6051/smac/efuse.h     |    40 +
+ drivers/net/wireless/ssv6051/smac/init.c      |  1347 ++
+ drivers/net/wireless/ssv6051/smac/init.h      |    23 +
+ drivers/net/wireless/ssv6051/smac/lib.c       |    33 +
+ drivers/net/wireless/ssv6051/smac/lib.h       |    23 +
+ .../net/wireless/ssv6051/smac/linux_80211.h   |    24 +
+ drivers/net/wireless/ssv6051/smac/p2p.c       |   305 +
+ drivers/net/wireless/ssv6051/smac/p2p.h       |    58 +
+ drivers/net/wireless/ssv6051/smac/sar.c       |   208 +
+ drivers/net/wireless/ssv6051/smac/sar.h       |    63 +
+ drivers/net/wireless/ssv6051/smac/sec.h       |    52 +
+ drivers/net/wireless/ssv6051/smac/smartlink.c |   340 +
+ .../wireless/ssv6051/smac/ssv6xxx_debugfs.c   |   223 +
+ .../wireless/ssv6051/smac/ssv6xxx_debugfs.h   |    27 +
+ .../net/wireless/ssv6051/smac/ssv_cfgvendor.c |  1384 ++
+ .../net/wireless/ssv6051/smac/ssv_cfgvendor.h |   247 +
+ drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c |   546 +
+ drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h |    31 +
+ drivers/net/wireless/ssv6051/smac/ssv_pm.c    |    19 +
+ drivers/net/wireless/ssv6051/smac/ssv_pm.h    |    20 +
+ drivers/net/wireless/ssv6051/smac/ssv_rc.c    |  1716 ++
+ drivers/net/wireless/ssv6051/smac/ssv_rc.h    |    50 +
+ .../net/wireless/ssv6051/smac/ssv_rc_common.h |   175 +
+ .../wireless/ssv6051/ssv6051-generic-wlan.c   |    76 +
+ .../net/wireless/ssv6051/ssvdevice/ssv_cmd.c  |  1765 ++
+ .../net/wireless/ssv6051/ssvdevice/ssv_cmd.h  |    50 +
+ .../wireless/ssv6051/ssvdevice/ssvdevice.c    |   256 +
+ 60 files changed, 48983 insertions(+)
+ create mode 100644 drivers/net/wireless/ssv6051/Kconfig
+ create mode 100644 drivers/net/wireless/ssv6051/Makefile
+ create mode 100644 drivers/net/wireless/ssv6051/Makefile.bak
+ create mode 100644 drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
+ create mode 100644 drivers/net/wireless/ssv6051/hci/hctrl.h
+ create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.c
+ create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.h
+ create mode 100644 drivers/net/wireless/ssv6051/hwif/hwif.h
+ create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
+ create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/cabrio.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_aux.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_common.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv_cfg.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv_version.h
+ create mode 100644 drivers/net/wireless/ssv6051/platform-config.mak
+ create mode 100644 drivers/net/wireless/ssv6051/rules.mak
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ap.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ap.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/dev.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/dev.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/dev_tbl.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/drv_comm.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/init.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/init.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/lib.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/lib.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/linux_80211.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/sar.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/sar.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/sec.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/smartlink.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
+ create mode 100644 drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
+ create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
+ create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
+ create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
+
+diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
+index de5e37846397..aa2cac9abdd3 100644
+--- a/drivers/net/wireless/Kconfig
++++ b/drivers/net/wireless/Kconfig
+@@ -18,6 +18,7 @@ menuconfig WLAN
+ 
+ if WLAN
+ 
++source "drivers/net/wireless/ssv6051/Kconfig"
+ source "drivers/net/wireless/admtek/Kconfig"
+ source "drivers/net/wireless/ath/Kconfig"
+ source "drivers/net/wireless/atmel/Kconfig"
+diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
+index 92ffd2cef51c..8b56a42e97a6 100644
+--- a/drivers/net/wireless/Makefile
++++ b/drivers/net/wireless/Makefile
+@@ -3,6 +3,7 @@
+ # Makefile for the Linux Wireless network device drivers.
+ #
+ 
++obj-$(CONFIG_SSV6051) += ssv6051/
+ obj-$(CONFIG_WLAN_VENDOR_ADMTEK) += admtek/
+ obj-$(CONFIG_WLAN_VENDOR_ATH) += ath/
+ obj-$(CONFIG_WLAN_VENDOR_ATMEL) += atmel/
+diff --git a/drivers/net/wireless/ssv6051/Kconfig b/drivers/net/wireless/ssv6051/Kconfig
+new file mode 100644
+index 000000000000..7706ad52ed7b
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/Kconfig
+@@ -0,0 +1,11 @@
++# SPDX-License-Identifier: GPL-2.0-only
++config SSV6051
++        tristate "South Silicon Valley (ssv) 6051 family WLAN support"
++	depends on MAC80211
++	depends on (MMC = y)
++        default n
++	select FW_LOADER
++        help
++		Enable South Silicon Valley (SSV) 6051 family support.
++
++
+diff --git a/drivers/net/wireless/ssv6051/Makefile b/drivers/net/wireless/ssv6051/Makefile
+new file mode 100644
+index 000000000000..985d730f3d50
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/Makefile
+@@ -0,0 +1,26 @@
++# SPDX-License-Identifier: ISC
++
++include $(src)/platform-config.mak
++
++ccflags-y += \
++	-I $(srctree)/$(src) \
++        -I $(srctree)/$(src)/include
++
++obj-$(CONFIG_SSV6051) += ssv6051.o
++ssv6051-objs += \
++	ssv6051-generic-wlan.o \
++	ssvdevice/ssvdevice.o \
++	ssvdevice/ssv_cmd.o \
++	hci/ssv_hci.o \
++	smac/init.o \
++	smac/dev.o \
++	smac/ssv_rc.o \
++	smac/ssv_ht_rc.o \
++	smac/ap.o \
++	smac/ampdu.o \
++	smac/efuse.o \
++	smac/ssv_pm.o \
++	smac/sar.o \
++	smac/ssv_cfgvendor.o \
++	hwif/sdio/sdio.o
++
+diff --git a/drivers/net/wireless/ssv6051/Makefile.bak b/drivers/net/wireless/ssv6051/Makefile.bak
+new file mode 100644
+index 000000000000..2733fa4dd3b7
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/Makefile.bak
+@@ -0,0 +1,107 @@
++KMODULE_NAME=ssv6051
++
++KBUILD_TOP := $(PWD)
++
++ifeq ($(KERNELRELEASE),)
++
++KVERS_UNAME ?= $(shell uname -r)
++KVERS_ARCH ?= $(shell arch)
++
++KBUILD ?= $(shell readlink -f /lib/modules/$(KVERS_UNAME)/build)
++
++ifeq (,$(KBUILD))
++$(error kernel build tree not found - set KBUILD to configured kernel)
++endif
++
++#KCONFIG := $(KBUILD)/config
++#ifeq (,$(wildcard $(KCONFIG)))
++#$(error No .config found in $(KBUILD), set KBUILD to configured kernel)
++#endif
++
++ifneq (,$(wildcard $(KBUILD)/include/linux/version.h))
++ifneq (,$(wildcard $(KBUILD)/include/generated/uapi/linux/version.h))
++$(error Multiple copied of version.h found, clean build tree)
++endif
++endif
++
++# Kernel Makefile doesn't always know the exact kernel version, so we
++# get it from the kernel headers instead and pass it to make.
++VERSION_H := $(KBUILD)/include/generated/utsrelease.h
++ifeq (,$(wildcard $(VERSION_H)))
++VERSION_H := $(KBUILD)/include/linux/utsrelease.h
++endif
++ifeq (,$(wildcard $(VERSION_H)))
++VERSION_H := $(KBUILD)/include/linux/version.h
++endif
++ifeq (,$(wildcard $(VERSION_H)))
++$(error Please run 'make modules_prepare' in $(KBUILD))
++endif
++
++KVERS := $(shell sed -ne 's/"//g;s/^\#define UTS_RELEASE //p' $(VERSION_H))
++
++ifeq (,$(KVERS))
++$(error Cannot find UTS_RELEASE in $(VERSION_H), please report)
++endif
++
++INST_DIR = /lib/modules/$(KVERS)/misc
++
++#include $(KCONFIG)
++
++endif
++
++include $(KBUILD_TOP)/platform-config.mak
++
++EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include #-Wno-error=missing-attributes
++DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
++
++OBJS := ssvdevice/ssvdevice.c \
++	ssvdevice/ssv_cmd.c \
++	hci/ssv_hci.c \
++	smac/init.c \
++	smac/dev.c \
++	smac/ssv_rc.c \
++	smac/ssv_ht_rc.c \
++	smac/ap.c \
++	smac/ampdu.c \
++	smac/efuse.c \
++	smac/ssv_pm.c \
++	smac/sar.c \
++	hwif/sdio/sdio.c \
++	ssv6051-generic-wlan.c
++
++ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
++OBJS +=	smac/ssv6xxx_debugfs.c
++endif
++
++ifeq ($(findstring -DCONFIG_SSV_VENDOR_EXT_SUPPORT, $(ccflags-y)), -DCONFIG_SSV_VENDOR_EXT_SUPPORT)
++OBJS +=	smac/ssv_cfgvendor.c
++endif
++
++ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
++OBJS += smac/smartlink.c
++endif
++
++$(KMODULE_NAME)-y += $(ASMS:.S=.o)
++$(KMODULE_NAME)-y += $(OBJS:.c=.o)
++
++obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
++
++all: modules
++
++modules:
++	ARCH=arm $(MAKE) -C $(KBUILD) M=$(KBUILD_TOP)
++
++clean:
++	find -type f -iname '*.o' -exec rm {} \;
++	find -type f -iname '*.o.cmd' -exec rm {} \;
++	rm -f *.o *.ko .*.cmd *.mod.c *.symvers modules.order
++	rm -rf .tmp_versions
++
++install: modules
++	mkdir -p -m 755 $(DESTDIR)$(INST_DIR)
++	install -m 0644 $(KMODULE_NAME).ko $(DESTDIR)$(INST_DIR)
++ifndef DESTDIR
++	-/sbin/depmod -a $(KVERS)
++endif
++
++.PHONY: all modules clean install
+diff --git a/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
+new file mode 100644
+index 000000000000..c072960f6dea
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
+@@ -0,0 +1,91 @@
++############################################################
++# ROCKCHIP RK3X28 & RK322X
++# WIFI-CONFIGURATION
++##################################################
++
++##################################################
++# Firmware setting
++# Priority.1 insmod parameter "cfgfirmwarepath"
++# Priority.2 firmware_path
++# Priority.3 default firmware
++##################################################
++firmware_path = /vendor/etc/firmware/
++
++############################################################
++# MAC address
++#
++# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
++#
++# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
++#
++# Priority 3. From insert module parameter
++#
++# Priority 4. From external file path
++#   path only support some special charater "_" ":" "/" "." "-"
++#
++# Priority 5. Default[Software mode]
++#
++#   0. => 00:33:33:33:33:33
++#   1. => Always random
++#   2. => First random and write to file[Default path mac_output_path]
++#
++############################################################
++ignore_efuse_mac = 0
++#mac_address_path = /xxxx/xxxx
++mac_address_mode = 2
++mac_output_path = /data/wifimac
++
++##################################################
++# Hardware setting
++#
++#volt regulator(DCDC-0 LDO-1)
++#
++##################################################
++xtal_clock = 24
++volt_regulator = 1
++
++##################################################
++# Default channel after wifi on
++# value range: [1 ~ 14]
++##################################################
++def_chan = 6
++##################################################
++# Hardware Capability Settings:
++##################################################
++hw_cap_ht = on
++hw_cap_gf = off
++hw_cap_2ghz = on
++hw_cap_5ghz = off
++hw_cap_security = on
++hw_cap_sgi_20 = on
++hw_cap_sgi_40 = off
++hw_cap_ap = on
++hw_cap_p2p = on
++hw_cap_ampdu_rx = on
++hw_cap_ampdu_tx = on
++use_wpa2_only = 1
++##################################################
++# TX power level setting [0-14]
++# The larger the number the smaller the TX power
++# 0 - The maximum power
++# 1 level = -0.5db
++#
++# 6051Z .. 4 or 4
++# 6051Q .. 2 or 5
++# 6051P .. 0 or 0
++#
++##################################################
++#wifi_tx_gain_level_b = 2
++#wifi_tx_gain_level_gn = 5
++################################################
++# Signal strength control
++# rssi control
++#rssi_ctl = 10
++
++
++##################################################
++# Import extenal configuration(UP to 64 groups)
++# example:
++#    register = CE010010:91919191
++#    register = 00CC0010:00091919
++##################################################
+diff --git a/drivers/net/wireless/ssv6051/hci/hctrl.h b/drivers/net/wireless/ssv6051/hci/hctrl.h
+new file mode 100644
+index 000000000000..95218c8040e7
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hci/hctrl.h
+@@ -0,0 +1,178 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _HCTRL_H_
++#define _HCTRL_H_
++#define MAX_FRAME_SIZE 4096
++#define SSV6XXX_INT_RX 0x00000001
++#define SSV6XXX_INT_TX 0x00000002
++#define SSV6XXX_INT_SOC 0x00000004
++#define SSV6XXX_INT_LOW_EDCA_0 0x00000008
++#define SSV6XXX_INT_LOW_EDCA_1 0x00000010
++#define SSV6XXX_INT_LOW_EDCA_2 0x00000020
++#define SSV6XXX_INT_LOW_EDCA_3 0x00000040
++#define SSV6XXX_INT_RESOURCE_LOW 0x00000080
++#define IFDEV(_ct) ((_ct)->shi->dev)
++#define IFOPS(_ct) ((_ct)->shi->if_ops)
++#define HCI_REG_READ(_ct,_adr,_val) IFOPS(_ct)->readreg(IFDEV(_ct), _adr, _val)
++#define HCI_REG_WRITE(_ct,_adr,_val) IFOPS(_ct)->writereg(IFDEV(_ct), _adr, _val)
++#define HCI_REG_SET_BITS(_ct,_reg,_set,_clr) \
++{ \
++    u32 _regval; \
++    if(HCI_REG_READ(_ct, _reg, &_regval)); \
++    _regval &= ~(_clr); \
++    _regval |= (_set); \
++    if(HCI_REG_WRITE(_ct, _reg, _regval)); \
++}
++#define IF_SEND(_ct,_bf,_len,_qid) IFOPS(_ct)->write(IFDEV(_ct), _bf, _len, _qid)
++#define IF_RECV(ct,bf,len) IFOPS(ct)->read(IFDEV(ct), bf, len)
++#define HCI_LOAD_FW(ct,_bf,open) IFOPS(ct)->load_fw(IFDEV(ct), _bf, open)
++#define HCI_IFC_RESET(ct) IFOPS(ct)->interface_reset(IFDEV(ct))
++struct ssv6xxx_hci_ctrl {
++	struct ssv6xxx_hci_info *shi;
++	spinlock_t int_lock;
++	u32 int_status;
++	u32 int_mask;
++	struct mutex txq_mask_lock;
++	u32 txq_mask;
++	struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];
++	struct mutex hci_mutex;
++	bool hci_start;
++	struct sk_buff *rx_buf;
++	u32 rx_pkt;
++	struct workqueue_struct *hci_work_queue;
++	struct work_struct hci_rx_work;
++	struct work_struct hci_tx_work;
++	u32 read_rs0_info_fail;
++	u32 read_rs1_info_fail;
++	u32 rx_work_running;
++	u32 isr_running;
++	u32 xmit_running;
++	u32 isr_summary_eable;
++	u32 isr_routine_time;
++	u32 isr_tx_time;
++	u32 isr_rx_time;
++	u32 isr_idle_time;
++	u32 isr_rx_idle_time;
++	u32 isr_miss_cnt;
++	unsigned long prev_isr_jiffes;
++	unsigned long prev_rx_isr_jiffes;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++	u32 isr_mib_enable;
++	u32 isr_mib_reset;
++	long long isr_total_time;
++	long long isr_tx_io_time;
++	long long isr_rx_io_time;
++	u32 isr_rx_io_count;
++	u32 isr_tx_io_count;
++	long long isr_rx_proc_time;
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++	bool irq_enable;
++	u32 irq_count;
++	u32 invalid_irq_count;
++	u32 tx_irq_count;
++	u32 real_tx_irq_count;
++	u32 rx_irq_count;
++	u32 irq_rx_pkt_count;
++	u32 irq_tx_pkt_count;
++#endif
++#endif
++};
++struct ssv6xxx_hci_txq_info {
++	u32 tx_use_page:8;
++	u32 tx_use_id:6;
++	u32 txq0_size:4;
++	u32 txq1_size:4;
++	u32 txq2_size:5;
++	u32 txq3_size:5;
++};
++struct ssv6xxx_hci_txq_info2 {
++	u32 tx_use_page:9;
++	u32 tx_use_id:8;
++	u32 txq4_size:4;
++	u32 rsvd:11;
++};
++struct ssv6xxx_hw_resource {
++	u32 free_tx_page;
++	u32 free_tx_id;
++	int max_tx_frame[SSV_HW_TXQ_NUM];
++};
++static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl,
++					    irq_handler_t irq_handler)
++{
++	if (hctrl->shi->if_ops->irq_request)
++		hctrl->shi->if_ops->irq_request(IFDEV(hctrl), irq_handler,
++						hctrl);
++}
++
++static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->irq_enable)
++		hctrl->shi->if_ops->irq_enable(IFDEV(hctrl));
++}
++
++static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->irq_disable)
++		hctrl->shi->if_ops->irq_disable(IFDEV(hctrl), false);
++}
++
++static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl,
++					     int *status)
++{
++	if (hctrl->shi->if_ops->irq_getstatus)
++		return hctrl->shi->if_ops->irq_getstatus(IFDEV(hctrl), status);
++	return 0;
++}
++
++static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl,
++					    int mask)
++{
++	if (hctrl->shi->if_ops->irq_setmask)
++		hctrl->shi->if_ops->irq_setmask(IFDEV(hctrl), mask);
++}
++
++static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->irq_trigger)
++		hctrl->shi->if_ops->irq_trigger(IFDEV(hctrl));
++}
++
++static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->pmu_wakeup)
++		hctrl->shi->if_ops->pmu_wakeup(IFDEV(hctrl));
++}
++
++static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl,
++					  u32 addr, u8 * data, u32 size)
++{
++	if (hctrl->shi->if_ops->write_sram)
++		return hctrl->shi->if_ops->write_sram(IFDEV(hctrl), addr, data,
++						      size);
++	return 0;
++}
++
++#define HCI_IRQ_REQUEST(ct,hdle) ssv6xxx_hwif_irq_request(ct, hdle)
++#define HCI_IRQ_ENABLE(ct) ssv6xxx_hwif_irq_enable(ct)
++#define HCI_IRQ_DISABLE(ct) ssv6xxx_hwif_irq_disable(ct)
++#define HCI_IRQ_STATUS(ct,sts) ssv6xxx_hwif_irq_getstatus(ct, sts)
++#define HCI_IRQ_SET_MASK(ct,mk) ssv6xxx_hwif_irq_setmask(ct, mk)
++#define HCI_IRQ_TRIGGER(ct) ssv6xxx_hwif_irq_trigger(ct)
++#define HCI_PMU_WAKEUP(ct) ssv6xxx_hwif_pmu_wakeup(ct)
++#define HCI_SRAM_WRITE(_ct,_adr,_dat,_size) ssv6xxx_hwif_write_sram(_ct, _adr, _dat, _size);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.c b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
+new file mode 100644
+index 000000000000..9fedbeb55754
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
+@@ -0,0 +1,967 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/jiffies.h>
++#include <ssv6200.h>
++#include "hctrl.h"
++
++static struct ssv6xxx_hci_ctrl *ctrl_hci = NULL;
++
++struct sk_buff *ssv_skb_alloc(s32 len)
++{
++	struct sk_buff *skb;
++	skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
++	if (skb != NULL) {
++		skb_reserve(skb, SSV_SKB_info_size);
++	}
++	return skb;
++}
++
++void ssv_skb_free(struct sk_buff *skb)
++{
++	dev_kfree_skb_any(skb);
++}
++
++static int ssv6xxx_hci_irq_enable(void)
++{
++	HCI_IRQ_SET_MASK(ctrl_hci, ~(ctrl_hci->int_mask));
++	HCI_IRQ_ENABLE(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_irq_disable(void)
++{
++	HCI_IRQ_SET_MASK(ctrl_hci, 0xffffffff);
++	HCI_IRQ_DISABLE(ctrl_hci);
++	return 0;
++}
++
++static void ssv6xxx_hci_irq_register(u32 irq_mask)
++{
++	unsigned long flags;
++	u32 regval;
++	mutex_lock(&ctrl_hci->hci_mutex);
++	spin_lock_irqsave(&ctrl_hci->int_lock, flags);
++	ctrl_hci->int_mask |= irq_mask;
++	regval = ~ctrl_hci->int_mask;
++	spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++	smp_mb();
++	HCI_IRQ_SET_MASK(ctrl_hci, regval);
++	mutex_unlock(&ctrl_hci->hci_mutex);
++}
++
++static inline u32 ssv6xxx_hci_get_int_bitno(int txqid)
++{
++	if (txqid == SSV_HW_TXQ_NUM - 1)
++		return 1;
++	else
++		return txqid + 3;
++}
++
++static int ssv6xxx_hci_start(void)
++{
++	ssv6xxx_hci_irq_enable();
++	ctrl_hci->hci_start = true;
++	HCI_IRQ_TRIGGER(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_stop(void)
++{
++	ssv6xxx_hci_irq_disable();
++	ctrl_hci->hci_start = false;
++	return 0;
++}
++
++static int ssv6xxx_hci_read_word(u32 addr, u32 * regval)
++{
++	int ret = HCI_REG_READ(ctrl_hci, addr, regval);
++	return ret;
++}
++
++static int ssv6xxx_hci_write_word(u32 addr, u32 regval)
++{
++	return HCI_REG_WRITE(ctrl_hci, addr, regval);
++}
++
++static int ssv6xxx_hci_load_fw(u8 * firmware_name, u8 openfile)
++{
++	return HCI_LOAD_FW(ctrl_hci, firmware_name, openfile);
++}
++
++static int ssv6xxx_hci_write_sram(u32 addr, u8 * data, u32 size)
++{
++	return HCI_SRAM_WRITE(ctrl_hci, addr, data, size);
++}
++
++static int ssv6xxx_hci_pmu_wakeup(void)
++{
++	HCI_PMU_WAKEUP(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_interface_reset(void)
++{
++	HCI_IFC_RESET(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_send_cmd(struct sk_buff *skb)
++{
++	int ret;
++	ret = IF_SEND(ctrl_hci, (void *)skb->data, skb->len, 0);
++
++	if (ret < 0)
++		pr_warn("ssv6xxx_hci_send_cmd failed, ret=%d\n", ret);
++
++	return ret;
++}
++
++static int ssv6xxx_hci_enqueue(struct sk_buff *skb, int txqid, u32 tx_flags)
++{
++	struct ssv_hw_txq *hw_txq;
++	unsigned long flags;
++	u32 status;
++	int qlen = 0;
++	BUG_ON(txqid >= SSV_HW_TXQ_NUM || txqid < 0);
++	if (txqid >= SSV_HW_TXQ_NUM || txqid < 0)
++		return -1;
++	hw_txq = &ctrl_hci->hw_txq[txqid];
++	hw_txq->tx_flags = tx_flags;
++	if (tx_flags & HCI_FLAGS_ENQUEUE_HEAD)
++		skb_queue_head(&hw_txq->qhead, skb);
++	else
++		skb_queue_tail(&hw_txq->qhead, skb);
++	qlen = (int)skb_queue_len(&hw_txq->qhead);
++	if (!(tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
++		if (skb_queue_len(&hw_txq->qhead) >= hw_txq->max_qsize) {
++			ctrl_hci->shi->hci_tx_flow_ctrl_cb(ctrl_hci->
++							   shi->tx_fctrl_cb_args,
++							   hw_txq->txq_no, true,
++							   2000);
++		}
++	}
++
++	mutex_lock(&ctrl_hci->hci_mutex);
++	spin_lock_irqsave(&ctrl_hci->int_lock, flags);
++	status = ctrl_hci->int_mask;
++
++	if ((ctrl_hci->int_mask & SSV6XXX_INT_RESOURCE_LOW) == 0) {
++		if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) {
++			u32 regval;
++			ctrl_hci->int_mask |= SSV6XXX_INT_RESOURCE_LOW;
++			regval = ~ctrl_hci->int_mask;
++			spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++			HCI_IRQ_SET_MASK(ctrl_hci, regval);
++			mutex_unlock(&ctrl_hci->hci_mutex);
++		} else {
++			ctrl_hci->int_status |= SSV6XXX_INT_RESOURCE_LOW;
++			smp_mb();
++			spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++			mutex_unlock(&ctrl_hci->hci_mutex);
++			ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci->
++							     shi->dev);
++		}
++	} else {
++		spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++		mutex_unlock(&ctrl_hci->hci_mutex);
++	}
++
++	return qlen;
++}
++
++static bool ssv6xxx_hci_is_txq_empty(int txqid)
++{
++	struct ssv_hw_txq *hw_txq;
++	BUG_ON(txqid >= SSV_HW_TXQ_NUM);
++	if (txqid >= SSV_HW_TXQ_NUM)
++		return false;
++	hw_txq = &ctrl_hci->hw_txq[txqid];
++	if (skb_queue_len(&hw_txq->qhead) <= 0)
++		return true;
++	return false;
++}
++
++static int ssv6xxx_hci_txq_flush(u32 txq_mask)
++{
++	struct ssv_hw_txq *hw_txq;
++	struct sk_buff *skb = NULL;
++	int txqid;
++	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++		if ((txq_mask & (1 << txqid)) != 0)
++			continue;
++		hw_txq = &ctrl_hci->hw_txq[txqid];
++		while ((skb = skb_dequeue(&hw_txq->qhead))) {
++			ctrl_hci->shi->hci_tx_buf_free_cb(skb,
++							  ctrl_hci->
++							  shi->tx_buf_free_args);
++		}
++	}
++	return 0;
++}
++
++static int ssv6xxx_hci_txq_flush_by_sta(int aid)
++{
++	return 0;
++}
++
++static int ssv6xxx_hci_txq_pause(u32 txq_mask)
++{
++	struct ssv_hw_txq *hw_txq;
++	int txqid;
++	mutex_lock(&ctrl_hci->txq_mask_lock);
++	ctrl_hci->txq_mask |= (txq_mask & 0x1F);
++	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++		if ((ctrl_hci->txq_mask & (1 << txqid)) == 0)
++			continue;
++		hw_txq = &ctrl_hci->hw_txq[txqid];
++		hw_txq->paused = true;
++	}
++	HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
++			 (ctrl_hci->txq_mask << 16), (0x1F << 16));
++	mutex_unlock(&ctrl_hci->txq_mask_lock);
++	return 0;
++}
++
++static int ssv6xxx_hci_txq_resume(u32 txq_mask)
++{
++	struct ssv_hw_txq *hw_txq;
++	int txqid;
++	mutex_lock(&ctrl_hci->txq_mask_lock);
++	ctrl_hci->txq_mask &= ~(txq_mask & 0x1F);
++	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++		if ((ctrl_hci->txq_mask & (1 << txqid)) != 0)
++			continue;
++		hw_txq = &ctrl_hci->hw_txq[txqid];
++		hw_txq->paused = false;
++	}
++	HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
++			 (ctrl_hci->txq_mask << 16), (0x1F << 16));
++	mutex_unlock(&ctrl_hci->txq_mask_lock);
++	return 0;
++}
++
++static int ssv6xxx_hci_xmit(struct ssv_hw_txq *hw_txq, int max_count,
++			    struct ssv6xxx_hw_resource *phw_resource)
++{
++	struct sk_buff_head tx_cb_list;
++	struct sk_buff *skb = NULL;
++	int tx_count, ret, page_count;
++	struct ssv6200_tx_desc *tx_desc = NULL;
++	ctrl_hci->xmit_running = 1;
++	skb_queue_head_init(&tx_cb_list);
++	for (tx_count = 0; tx_count < max_count; tx_count++) {
++		if (ctrl_hci->hci_start == false) {
++			pr_debug("ssv6xxx_hci_xmit - hci_start = false\n");
++			goto xmit_out;
++		}
++		skb = skb_dequeue(&hw_txq->qhead);
++		if (!skb) {
++			pr_debug("ssv6xxx_hci_xmit - queue empty\n");
++			goto xmit_out;
++		}
++		page_count = (skb->len + SSV6200_ALLOC_RSVD);
++		if (page_count & HW_MMU_PAGE_MASK)
++			page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
++		else
++			page_count = page_count >> HW_MMU_PAGE_SHIFT;
++		if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
++			pr_err("Asking page %d(%d) exceeds resource limit %d.\n",
++			       page_count, skb->len,
++			       (SSV6200_PAGE_TX_THRESHOLD / 2));
++		if ((phw_resource->free_tx_page < page_count)
++		    || (phw_resource->free_tx_id <= 0)
++		    || (phw_resource->max_tx_frame[hw_txq->txq_no] <= 0)) {
++			skb_queue_head(&hw_txq->qhead, skb);
++			break;
++		}
++		phw_resource->free_tx_page -= page_count;
++		phw_resource->free_tx_id--;
++		phw_resource->max_tx_frame[hw_txq->txq_no]--;
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++
++		if (ctrl_hci->shi->hci_skb_update_cb != NULL
++		    && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
++			ctrl_hci->shi->hci_skb_update_cb(skb,
++							 ctrl_hci->
++							 shi->skb_update_args);
++		}
++
++		ret =
++		    IF_SEND(ctrl_hci, (void *)skb->data, skb->len,
++			    hw_txq->txq_no);
++		if (ret < 0) {
++			pr_err("ssv6xxx_hci_xmit failure\n");
++			skb_queue_head(&hw_txq->qhead, skb);
++			break;
++		}
++		if (tx_desc->reason != ID_TRAP_SW_TXTPUT)
++			skb_queue_tail(&tx_cb_list, skb);
++		else
++			ssv_skb_free(skb);
++		hw_txq->tx_pkt++;
++
++		if (!(hw_txq->tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
++			if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) {
++				ctrl_hci->shi->
++				    hci_tx_flow_ctrl_cb
++				    (ctrl_hci->shi->tx_fctrl_cb_args,
++				     hw_txq->txq_no, false, 2000);
++			}
++		}
++	}
++ xmit_out:
++	if (ctrl_hci->shi->hci_tx_cb && tx_desc
++	    && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
++		ctrl_hci->shi->hci_tx_cb(&tx_cb_list,
++					 ctrl_hci->shi->tx_cb_args);
++	}
++	ctrl_hci->xmit_running = 0;
++	return tx_count;
++}
++
++static int ssv6xxx_hci_tx_handler(void *dev, int max_count)
++{
++	struct ssv6xxx_hci_txq_info txq_info;
++	struct ssv6xxx_hci_txq_info2 txq_info2;
++	struct ssv6xxx_hw_resource hw_resource;
++	struct ssv_hw_txq *hw_txq = dev;
++	int ret, tx_count = 0;
++	max_count = skb_queue_len(&hw_txq->qhead);
++	if (max_count == 0)
++		return 0;
++	if (hw_txq->txq_no == 4) {
++		ret =
++		    HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2,
++				 (u32 *) & txq_info2);
++		if (ret < 0) {
++			ctrl_hci->read_rs1_info_fail++;
++			return 0;
++		}
++		//BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page);
++		//BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_id);
++		if (SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page)
++			return 0;
++		if (SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_page)
++			return 0;
++		hw_resource.free_tx_page =
++		    SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
++		hw_resource.free_tx_id =
++		    SSV6200_ID_TX_THRESHOLD - txq_info2.tx_use_id;
++		hw_resource.max_tx_frame[4] =
++		    SSV6200_ID_MANAGER_QUEUE - txq_info2.txq4_size;
++	} else {
++		ret =
++		    HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO,
++				 (u32 *) & txq_info);
++		if (ret < 0) {
++			ctrl_hci->read_rs0_info_fail++;
++			return 0;
++		}
++		//BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page);
++		//BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_id);
++		if (SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page)
++			return 0;
++		if (SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_page)
++			return 0;
++		hw_resource.free_tx_page =
++		    SSV6200_PAGE_TX_THRESHOLD - txq_info.tx_use_page;
++		hw_resource.free_tx_id =
++		    SSV6200_ID_TX_THRESHOLD - txq_info.tx_use_id;
++		hw_resource.max_tx_frame[0] =
++		    SSV6200_ID_AC_BK_OUT_QUEUE - txq_info.txq0_size;
++		hw_resource.max_tx_frame[1] =
++		    SSV6200_ID_AC_BE_OUT_QUEUE - txq_info.txq1_size;
++		hw_resource.max_tx_frame[2] =
++		    SSV6200_ID_AC_VI_OUT_QUEUE - txq_info.txq2_size;
++		hw_resource.max_tx_frame[3] =
++		    SSV6200_ID_AC_VO_OUT_QUEUE - txq_info.txq3_size;
++		BUG_ON(hw_resource.max_tx_frame[3] < 0);
++		BUG_ON(hw_resource.max_tx_frame[2] < 0);
++		BUG_ON(hw_resource.max_tx_frame[1] < 0);
++		BUG_ON(hw_resource.max_tx_frame[0] < 0);
++	}
++	{
++		tx_count = ssv6xxx_hci_xmit(hw_txq, max_count, &hw_resource);
++	}
++	if ((ctrl_hci->shi->hci_tx_q_empty_cb != NULL)
++	    && (skb_queue_len(&hw_txq->qhead) == 0)) {
++		ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no,
++						 ctrl_hci->
++						 shi->tx_q_empty_args);
++	}
++	return tx_count;
++}
++
++void ssv6xxx_hci_tx_work(struct work_struct *work)
++{
++	ssv6xxx_hci_irq_register(SSV6XXX_INT_RESOURCE_LOW);
++}
++
++static int _do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
++{
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	struct sk_buff_head rx_list;
++#endif
++	struct sk_buff *rx_mpdu;
++	int rx_cnt, ret = 0;
++	size_t dlen;
++	u32 status = isr_status;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
++	struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	skb_queue_head_init(&rx_list);
++#endif
++	for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&rx_io_start_time);
++#endif
++		ret = IF_RECV(hctl, hctl->rx_buf->data, &dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&rx_io_end_time);
++#endif
++		if (ret < 0 || dlen <= 0) {
++			pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
++			       __FUNCTION__, ret, (int)dlen);
++			if (ret != -84 || dlen > MAX_FRAME_SIZE)
++				break;
++		}
++		rx_mpdu = hctl->rx_buf;
++		hctl->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++		if (hctl->rx_buf == NULL) {
++			pr_err("RX buffer allocation failure!\n");
++			hctl->rx_buf = rx_mpdu;
++			break;
++		}
++		hctl->rx_pkt++;
++		skb_put(rx_mpdu, dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&rx_proc_start_time);
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++		__skb_queue_tail(&rx_list, rx_mpdu);
++#else
++		hctl->shi->hci_rx_cb(rx_mpdu, hctl->shi->rx_cb_args);
++#endif
++		HCI_IRQ_STATUS(hctl, &status);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable) {
++			getnstimeofday(&rx_proc_end_time);
++			hctl->isr_rx_io_count++;
++			rx_io_diff_time =
++			    timespec_sub(rx_io_end_time, rx_io_start_time);
++			hctl->isr_rx_io_time +=
++			    timespec_to_ns(&rx_io_diff_time);
++			rx_proc_diff_time =
++			    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++			hctl->isr_rx_proc_time +=
++			    timespec_to_ns(&rx_proc_diff_time);
++		}
++#endif
++	}
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (hctl->isr_mib_enable)
++		getnstimeofday(&rx_proc_start_time);
++#endif
++	hctl->shi->hci_rx_cb(&rx_list, hctl->shi->rx_cb_args);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (hctl->isr_mib_enable) {
++		getnstimeofday(&rx_proc_end_time);
++		rx_proc_diff_time =
++		    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++		hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
++	}
++#endif
++#endif
++	return ret;
++}
++
++static void ssv6xxx_hci_rx_work(struct work_struct *work)
++{
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	struct sk_buff_head rx_list;
++#endif
++	struct sk_buff *rx_mpdu;
++	int rx_cnt, ret;
++	size_t dlen;
++	u32 status;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
++	struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
++#endif
++	ctrl_hci->rx_work_running = 1;
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	skb_queue_head_init(&rx_list);
++#endif
++	status = SSV6XXX_INT_RX;
++	for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable)
++			getnstimeofday(&rx_io_start_time);
++#endif
++		ret = IF_RECV(ctrl_hci, ctrl_hci->rx_buf->data, &dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable)
++			getnstimeofday(&rx_io_end_time);
++#endif
++		if (ret < 0 || dlen <= 0) {
++			pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
++			       __FUNCTION__, ret, (int)dlen);
++			if (ret != -84 || dlen > MAX_FRAME_SIZE)
++				break;
++		}
++		rx_mpdu = ctrl_hci->rx_buf;
++		ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++		if (ctrl_hci->rx_buf == NULL) {
++			pr_err("RX buffer allocation failure!\n");
++			ctrl_hci->rx_buf = rx_mpdu;
++			break;
++		}
++		ctrl_hci->rx_pkt++;
++		skb_put(rx_mpdu, dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable)
++			getnstimeofday(&rx_proc_start_time);
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++		__skb_queue_tail(&rx_list, rx_mpdu);
++#else
++		ctrl_hci->shi->hci_rx_cb(rx_mpdu, ctrl_hci->shi->rx_cb_args);
++#endif
++		HCI_IRQ_STATUS(ctrl_hci, &status);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable) {
++			getnstimeofday(&rx_proc_end_time);
++			ctrl_hci->isr_rx_io_count++;
++			rx_io_diff_time =
++			    timespec_sub(rx_io_end_time, rx_io_start_time);
++			ctrl_hci->isr_rx_io_time +=
++			    timespec_to_ns(&rx_io_diff_time);
++			rx_proc_diff_time =
++			    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++			ctrl_hci->isr_rx_proc_time +=
++			    timespec_to_ns(&rx_proc_diff_time);
++		}
++#endif
++	}
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (ctrl_hci->isr_mib_enable)
++		getnstimeofday(&rx_proc_start_time);
++#endif
++	ctrl_hci->shi->hci_rx_cb(&rx_list, ctrl_hci->shi->rx_cb_args);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (ctrl_hci->isr_mib_enable) {
++		getnstimeofday(&rx_proc_end_time);
++		rx_proc_diff_time =
++		    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++		ctrl_hci->isr_rx_proc_time +=
++		    timespec_to_ns(&rx_proc_diff_time);
++	}
++#endif
++#endif
++	ctrl_hci->rx_work_running = 0;
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++static void ssv6xxx_isr_mib_reset(void)
++{
++	ctrl_hci->isr_mib_reset = 0;
++	ctrl_hci->isr_total_time = 0;
++	ctrl_hci->isr_rx_io_time = 0;
++	ctrl_hci->isr_tx_io_time = 0;
++	ctrl_hci->isr_rx_io_count = 0;
++	ctrl_hci->isr_tx_io_count = 0;
++	ctrl_hci->isr_rx_proc_time = 0;
++}
++
++static int hw_txq_len_open(struct inode *inode, struct file *filp)
++{
++	filp->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t hw_txq_len_read(struct file *filp, char __user * buffer,
++			       size_t count, loff_t * ppos)
++{
++	ssize_t ret;
++	struct ssv6xxx_hci_ctrl *hctl =
++	    (struct ssv6xxx_hci_ctrl *)filp->private_data;
++	char *summary_buf = kzalloc(1024, GFP_KERNEL);
++	char *prn_ptr = summary_buf;
++	int prt_size;
++	int buf_size = 1024;
++	int i = 0;
++	if (!summary_buf)
++		return -ENOMEM;
++	for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
++		prt_size =
++		    snprintf(prn_ptr, buf_size, "\n\rhw_txq%d_len: %d", i,
++			     skb_queue_len(&hctl->hw_txq[i].qhead));
++		prn_ptr += prt_size;
++		buf_size -= prt_size;
++	}
++	buf_size = 1024 - buf_size;
++	ret =
++	    simple_read_from_buffer(buffer, count, ppos, summary_buf, buf_size);
++	kfree(summary_buf);
++	return ret;
++}
++
++struct file_operations hw_txq_len_fops = {
++	.owner = THIS_MODULE,
++	.open = hw_txq_len_open,
++	.read = hw_txq_len_read,
++};
++
++bool ssv6xxx_hci_init_debugfs(struct dentry *dev_deugfs_dir)
++{
++	ctrl_hci->debugfs_dir = debugfs_create_dir("hci", dev_deugfs_dir);
++	if (ctrl_hci->debugfs_dir == NULL) {
++		dev_err(ctrl_hci->shi->dev,
++			"Failed to create HCI debugfs directory.\n");
++		return false;
++	}
++	debugfs_create_u32("TXQ_mask", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->txq_mask);
++	debugfs_create_u32("hci_isr_mib_enable", 00644, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_mib_enable);
++	debugfs_create_u32("hci_isr_mib_reset", 00644, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_mib_reset);
++	debugfs_create_u64("isr_total_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_total_time);
++	debugfs_create_u64("tx_io_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_tx_io_time);
++	debugfs_create_u64("rx_io_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_rx_io_time);
++	debugfs_create_u32("tx_io_count", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_tx_io_count);
++	debugfs_create_u32("rx_io_count", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_rx_io_count);
++	debugfs_create_u64("rx_proc_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_rx_proc_time);
++	debugfs_create_file("hw_txq_len", 00444, ctrl_hci->debugfs_dir,
++			    ctrl_hci, &hw_txq_len_fops);
++	return true;
++}
++
++void ssv6xxx_hci_deinit_debugfs(void)
++{
++	if (ctrl_hci->debugfs_dir == NULL)
++		return;
++	ctrl_hci->debugfs_dir = NULL;
++}
++#endif
++static int _isr_do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
++{
++	int status;
++	u32 before = jiffies;
++
++	if (hctl->isr_summary_eable && hctl->prev_rx_isr_jiffes) {
++		if (hctl->isr_rx_idle_time) {
++			hctl->isr_rx_idle_time +=
++			    (jiffies - hctl->prev_rx_isr_jiffes);
++			hctl->isr_rx_idle_time = hctl->isr_rx_idle_time >> 1;
++		} else {
++			hctl->isr_rx_idle_time +=
++			    (jiffies - hctl->prev_rx_isr_jiffes);
++		}
++	}
++	status = _do_rx(hctl, isr_status);
++	if (hctl->isr_summary_eable) {
++		if (hctl->isr_rx_time) {
++			hctl->isr_rx_time += (jiffies - before);
++			hctl->isr_rx_time = hctl->isr_rx_time >> 1;
++		} else {
++			hctl->isr_rx_time += (jiffies - before);
++		}
++		hctl->prev_rx_isr_jiffes = jiffies;
++	}
++	return status;
++}
++
++static int _do_tx(struct ssv6xxx_hci_ctrl *hctl, u32 status)
++{
++	int q_num;
++	int tx_count = 0;
++	u32 to_disable_int = 1;
++	unsigned long flags;
++	struct ssv_hw_txq *hw_txq;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time;
++#endif
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++	if ((!(status & SSV6XXX_INT_RX)) && htcl->irq_enable)
++		hctl->tx_irq_count++;
++#endif
++	if ((status & SSV6XXX_INT_RESOURCE_LOW) == 0)
++		return 0;
++	for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
++		u32 before = jiffies;
++		hw_txq = &hctl->hw_txq[q_num];
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&tx_io_start_time);
++#endif
++		tx_count += ssv6xxx_hci_tx_handler(hw_txq, 999);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable) {
++			getnstimeofday(&tx_io_end_time);
++			tx_io_diff_time =
++			    timespec_sub(tx_io_end_time, tx_io_start_time);
++			hctl->isr_tx_io_time +=
++			    timespec_to_ns(&tx_io_diff_time);
++		}
++#endif
++		if (hctl->isr_summary_eable) {
++			if (hctl->isr_tx_time) {
++				hctl->isr_tx_time += (jiffies - before);
++				hctl->isr_tx_time = hctl->isr_tx_time >> 1;
++			} else {
++				hctl->isr_tx_time += (jiffies - before);
++			}
++		}
++	}
++	mutex_lock(&hctl->hci_mutex);
++	spin_lock_irqsave(&hctl->int_lock, flags);
++	for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
++		hw_txq = &hctl->hw_txq[q_num];
++		if (skb_queue_len(&hw_txq->qhead) > 0) {
++			to_disable_int = 0;
++			break;
++		}
++	}
++	if (to_disable_int) {
++		u32 reg_val;
++		hctl->int_mask &= ~(SSV6XXX_INT_RESOURCE_LOW | SSV6XXX_INT_TX);
++		reg_val = ~hctl->int_mask;
++		spin_unlock_irqrestore(&hctl->int_lock, flags);
++		HCI_IRQ_SET_MASK(hctl, reg_val);
++	} else {
++		spin_unlock_irqrestore(&hctl->int_lock, flags);
++	}
++	mutex_unlock(&hctl->hci_mutex);
++	return tx_count;
++}
++
++irqreturn_t ssv6xxx_hci_isr(int irq, void *args)
++{
++	struct ssv6xxx_hci_ctrl *hctl = args;
++	u32 status;
++	unsigned long flags;
++	int ret = IRQ_HANDLED;
++	bool dbg_isr_miss = true;
++	if (ctrl_hci->isr_summary_eable && ctrl_hci->prev_isr_jiffes) {
++		if (ctrl_hci->isr_idle_time) {
++			ctrl_hci->isr_idle_time +=
++			    (jiffies - ctrl_hci->prev_isr_jiffes);
++			ctrl_hci->isr_idle_time = ctrl_hci->isr_idle_time >> 1;
++		} else {
++			ctrl_hci->isr_idle_time +=
++			    (jiffies - ctrl_hci->prev_isr_jiffes);
++		}
++	}
++	BUG_ON(!args);
++	do {
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		struct timespec start_time, end_time, diff_time;
++		if (hctl->isr_mib_reset)
++			ssv6xxx_isr_mib_reset();
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&start_time);
++#endif
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++		if (ctrl_hci->irq_enable)
++			ctrl_hci->irq_count++;
++#endif
++		mutex_lock(&hctl->hci_mutex);
++		if (hctl->int_status) {
++			u32 regval;
++			spin_lock_irqsave(&hctl->int_lock, flags);
++			hctl->int_mask |= hctl->int_status;
++			hctl->int_status = 0;
++			regval = ~ctrl_hci->int_mask;
++			smp_mb();
++			spin_unlock_irqrestore(&hctl->int_lock, flags);
++			HCI_IRQ_SET_MASK(hctl, regval);
++		}
++		ret = HCI_IRQ_STATUS(hctl, &status);
++		if ((ret < 0) || ((status & hctl->int_mask) == 0)) {
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++			if (ctrl_hci->irq_enable)
++				ctrl_hci->invalid_irq_count++;
++#endif
++			mutex_unlock(&hctl->hci_mutex);
++			ret = IRQ_NONE;
++			break;
++		}
++		spin_lock_irqsave(&hctl->int_lock, flags);
++		status &= hctl->int_mask;
++		spin_unlock_irqrestore(&hctl->int_lock, flags);
++		mutex_unlock(&hctl->hci_mutex);
++		ctrl_hci->isr_running = 1;
++		if (status & SSV6XXX_INT_RX) {
++			ret = _isr_do_rx(hctl, status);
++			if (ret < 0) {
++				ret = IRQ_NONE;
++				break;
++			}
++			dbg_isr_miss = false;
++		}
++		if (_do_tx(hctl, status)) {
++			dbg_isr_miss = false;
++		}
++		ctrl_hci->isr_running = 0;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable) {
++			getnstimeofday(&end_time);
++			diff_time = timespec_sub(end_time, start_time);
++			ctrl_hci->isr_total_time += timespec_to_ns(&diff_time);
++		}
++#endif
++	} while (1);
++	if (ctrl_hci->isr_summary_eable) {
++		if (dbg_isr_miss)
++			ctrl_hci->isr_miss_cnt++;
++		ctrl_hci->prev_isr_jiffes = jiffies;
++	}
++	return ret;
++}
++
++static struct ssv6xxx_hci_ops hci_ops = {
++	.hci_start = ssv6xxx_hci_start,
++	.hci_stop = ssv6xxx_hci_stop,
++	.hci_read_word = ssv6xxx_hci_read_word,
++	.hci_write_word = ssv6xxx_hci_write_word,
++	.hci_tx = ssv6xxx_hci_enqueue,
++	.hci_tx_pause = ssv6xxx_hci_txq_pause,
++	.hci_tx_resume = ssv6xxx_hci_txq_resume,
++	.hci_txq_flush = ssv6xxx_hci_txq_flush,
++	.hci_txq_flush_by_sta = ssv6xxx_hci_txq_flush_by_sta,
++	.hci_txq_empty = ssv6xxx_hci_is_txq_empty,
++	.hci_load_fw = ssv6xxx_hci_load_fw,
++	.hci_pmu_wakeup = ssv6xxx_hci_pmu_wakeup,
++	.hci_send_cmd = ssv6xxx_hci_send_cmd,
++	.hci_write_sram = ssv6xxx_hci_write_sram,
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	.hci_init_debugfs = ssv6xxx_hci_init_debugfs,
++	.hci_deinit_debugfs = ssv6xxx_hci_deinit_debugfs,
++#endif
++	.hci_interface_reset = ssv6xxx_hci_interface_reset,
++};
++
++int ssv6xxx_hci_deregister(void)
++{
++	u32 regval;
++	pr_debug("%s(): \n", __FUNCTION__);
++	if (ctrl_hci->shi == NULL)
++		return -1;
++	regval = 1;
++	ssv6xxx_hci_irq_disable();
++	flush_workqueue(ctrl_hci->hci_work_queue);
++	destroy_workqueue(ctrl_hci->hci_work_queue);
++	ctrl_hci->shi = NULL;
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_hci_deregister);
++int ssv6xxx_hci_register(struct ssv6xxx_hci_info *shi)
++{
++	int i;
++	if (shi == NULL || ctrl_hci->shi)
++		return -1;
++	shi->hci_ops = &hci_ops;
++	ctrl_hci->shi = shi;
++	ctrl_hci->txq_mask = 0;
++	mutex_init(&ctrl_hci->txq_mask_lock);
++	mutex_init(&ctrl_hci->hci_mutex);
++	spin_lock_init(&ctrl_hci->int_lock);
++
++	for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
++		memset(&ctrl_hci->hw_txq[i], 0, sizeof(struct ssv_hw_txq));
++		skb_queue_head_init(&ctrl_hci->hw_txq[i].qhead);
++		ctrl_hci->hw_txq[i].txq_no = (u32) i;
++		ctrl_hci->hw_txq[i].max_qsize = SSV_HW_TXQ_MAX_SIZE;
++		ctrl_hci->hw_txq[i].resum_thres = SSV_HW_TXQ_RESUME_THRES;
++	}
++	ctrl_hci->hci_work_queue =
++	    create_singlethread_workqueue("ssv6xxx_hci_wq");
++	INIT_WORK(&ctrl_hci->hci_rx_work, ssv6xxx_hci_rx_work);
++	INIT_WORK(&ctrl_hci->hci_tx_work, ssv6xxx_hci_tx_work);
++	ctrl_hci->int_mask = SSV6XXX_INT_RX | SSV6XXX_INT_RESOURCE_LOW;
++	ctrl_hci->int_status = 0;
++	HCI_IRQ_SET_MASK(ctrl_hci, 0xFFFFFFFF);
++	ssv6xxx_hci_irq_disable();
++	HCI_IRQ_REQUEST(ctrl_hci, ssv6xxx_hci_isr);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ctrl_hci->debugfs_dir = NULL;
++	ctrl_hci->isr_mib_enable = false;
++	ctrl_hci->isr_mib_reset = 0;
++	ctrl_hci->isr_total_time = 0;
++	ctrl_hci->isr_rx_io_time = 0;
++	ctrl_hci->isr_tx_io_time = 0;
++	ctrl_hci->isr_rx_io_count = 0;
++	ctrl_hci->isr_tx_io_count = 0;
++	ctrl_hci->isr_rx_proc_time = 0;
++#endif
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_hci_register);
++int ssv6xxx_hci_init(void)
++{
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
++#endif
++	ctrl_hci = kzalloc(sizeof(*ctrl_hci), GFP_KERNEL);
++	if (ctrl_hci == NULL)
++		return -ENOMEM;
++	memset((void *)ctrl_hci, 0, sizeof(*ctrl_hci));
++	ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++	if (ctrl_hci->rx_buf == NULL) {
++		kfree(ctrl_hci);
++		return -ENOMEM;
++	}
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	ssv_dbg_ctrl_hci = ctrl_hci;
++#endif
++	return 0;
++}
++
++void ssv6xxx_hci_exit(void)
++{
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
++#endif
++	kfree(ctrl_hci);
++	ctrl_hci = NULL;
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	ssv_dbg_ctrl_hci = NULL;
++#endif
++}
++
++EXPORT_SYMBOL(ssv6xxx_hci_init);
++EXPORT_SYMBOL(ssv6xxx_hci_exit);
+diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.h b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
+new file mode 100644
+index 000000000000..dd166c607d5d
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
+@@ -0,0 +1,77 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_HCI_H_
++#define _SSV_HCI_H_
++#define SSV_HW_TXQ_NUM 5
++#define SSV_HW_TXQ_MAX_SIZE 64
++#define SSV_HW_TXQ_RESUME_THRES ((SSV_HW_TXQ_MAX_SIZE >> 2) *3)
++#define HCI_FLAGS_ENQUEUE_HEAD 0x00000001
++#define HCI_FLAGS_NO_FLOWCTRL 0x00000002
++struct ssv_hw_txq {
++	u32 txq_no;
++	struct sk_buff_head qhead;
++	int max_qsize;
++	int resum_thres;
++	bool paused;
++	u32 tx_pkt;
++	u32 tx_flags;
++};
++struct ssv6xxx_hci_ops {
++	int (*hci_start)(void);
++	int (*hci_stop)(void);
++	int (*hci_read_word)(u32 addr, u32 * regval);
++	int (*hci_write_word)(u32 addr, u32 regval);
++	int (*hci_load_fw)(u8 * firmware_name, u8 openfile);
++	int (*hci_tx)(struct sk_buff *, int, u32);
++	int (*hci_tx_pause)(u32 txq_mask);
++	int (*hci_tx_resume)(u32 txq_mask);
++	int (*hci_txq_flush)(u32 txq_mask);
++	int (*hci_txq_flush_by_sta)(int aid);
++	bool (*hci_txq_empty)(int txqid);
++	int (*hci_pmu_wakeup)(void);
++	int (*hci_send_cmd)(struct sk_buff *);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	bool (*hci_init_debugfs)(struct dentry * dev_deugfs_dir);
++	void (*hci_deinit_debugfs)(void);
++#endif
++	int (*hci_write_sram)(u32 addr, u8 * data, u32 size);
++	int (*hci_interface_reset)(void);
++};
++struct ssv6xxx_hci_info {
++	struct device *dev;
++	struct ssv6xxx_hwif_ops *if_ops;
++	struct ssv6xxx_hci_ops *hci_ops;
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	int (*hci_rx_cb)(struct sk_buff_head *, void *);
++#else
++	int (*hci_rx_cb)(struct sk_buff *, void *);
++#endif
++	void *rx_cb_args;
++	void (*hci_tx_cb)(struct sk_buff_head *, void *);
++	void *tx_cb_args;
++	int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug);
++	void *tx_fctrl_cb_args;
++	void (*hci_tx_buf_free_cb)(struct sk_buff *, void *);
++	void *tx_buf_free_args;
++	void (*hci_skb_update_cb)(struct sk_buff *, void *);
++	void *skb_update_args;
++	void (*hci_tx_q_empty_cb)(u32 txq_no, void *);
++	void *tx_q_empty_args;
++};
++int ssv6xxx_hci_deregister(void);
++int ssv6xxx_hci_register(struct ssv6xxx_hci_info *);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/hwif/hwif.h b/drivers/net/wireless/ssv6051/hwif/hwif.h
+new file mode 100644
+index 000000000000..6b5263d157d8
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hwif/hwif.h
+@@ -0,0 +1,84 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _LINUX_SSVCABRIO_PLATFORM_H
++#define _LINUX_SSVCABRIO_PLATFORM_H 
++#include <linux/mmc/host.h>
++#include <hwif/sdio/sdio_def.h>
++#define SSVCABRIO_PLAT_EEP_MAX_WORDS 2048
++#define SSV_REG_WRITE(dev,reg,val) \
++        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
++#define SSV_REG_READ(dev,reg,buf) \
++        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
++#if 0
++#define SSV_REG_WRITE(sh,reg,val) \
++        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
++#define SSV_REG_READ(sh,reg,buf) \
++        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
++#define SSV_REG_CONFIRM(sh,reg,val) \
++{ \
++    u32 regval; \
++    SSV_REG_READ(sh, reg, &regval); \
++    if (regval != (val)) { \
++        printk("[0x%08x]: 0x%08x!=0x%08x\n",\
++        (reg), (val), regval); \
++        return -1; \
++    } \
++}
++#define SSV_REG_SET_BITS(sh,reg,set,clr) \
++{ \
++    u32 reg_val; \
++    SSV_REG_READ(sh, reg, &reg_val); \
++    reg_val &= ~(clr); \
++    reg_val |= (set); \
++    SSV_REG_WRITE(sh, reg, reg_val); \
++}
++#endif
++struct ssv6xxx_hwif_ops {
++    int __must_check (*read)(struct device *child, void *buf,size_t *size);
++    int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num);
++    int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf);
++    int __must_check (*writereg)(struct device *child, u32 addr, u32 buf);
++    int (*trigger_tx_rx)(struct device *child);
++    int (*irq_getmask)(struct device *child, u32 *mask);
++    void (*irq_setmask)(struct device *child,int mask);
++    void (*irq_enable)(struct device *child);
++    void (*irq_disable)(struct device *child,bool iswaitirq);
++    int (*irq_getstatus)(struct device *child,int *status);
++    void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev);
++    void (*irq_trigger)(struct device *child);
++    void (*pmu_wakeup)(struct device *child);
++    int __must_check (*load_fw)(struct device *child, u8 *firmware_name, u8 openfile);
++    int (*cmd52_read)(struct device *child, u32 addr, u32 *value);
++    int (*cmd52_write)(struct device *child, u32 addr, u32 value);
++    bool (*support_scatter)(struct device *child);
++    int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req);
++    bool (*is_ready)(struct device *child);
++    int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size);
++    void (*interface_reset)(struct device *child);
++};
++struct ssv6xxx_if_debug {
++    struct device *dev;
++    struct platform_device *pdev;
++};
++struct ssv6xxx_platform_data {
++    atomic_t irq_handling;
++    bool is_enabled;
++    unsigned short vendor;
++    unsigned short device;
++    struct ssv6xxx_hwif_ops *ops;
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
+new file mode 100644
+index 000000000000..273777cd0485
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
+@@ -0,0 +1,1254 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/vmalloc.h>
++#include <linux/platform_device.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/host.h>
++#include "sdio_def.h"
++#include <linux/pm_runtime.h>
++#include <linux/version.h>
++#include <linux/firmware.h>
++#include <linux/reboot.h>
++#include <ssv6200.h>
++#include <linux/skbuff.h>
++
++#define LOW_SPEED_SDIO_CLOCK (25000000)
++#define HIGH_SPEED_SDIO_CLOCK (37500000)
++#define MAX_RX_FRAME_SIZE 0x900
++#define SSV_VENDOR_ID 0x3030
++#define SSV_CABRIO_DEVID 0x3030
++#define ENABLE_FW_SELF_CHECK 1
++#define FW_BLOCK_SIZE 0x8000
++#define CHECKSUM_BLOCK_SIZE 1024
++#define FW_CHECKSUM_INIT (0x12345678)
++#define FW_STATUS_REG ADR_TX_SEG
++#define FW_STATUS_MASK (0x00FF0000)
++
++#define ret_if_not_ready(value) \
++    do { \
++    if ((wlan_data.is_enabled == false) || \
++        (glue == NULL) || (glue->dev_ready == false)) { \
++        pr_warn("ret_if_not_ready() called when not ready"); \
++        return value; }\
++    } while(0)
++
++static int ssv6xxx_sdio_trigger_pmu(struct device *dev);
++static void ssv6xxx_sdio_reset(struct device *child);
++
++static void ssv6xxx_high_sdio_clk(struct sdio_func *func);
++static void ssv6xxx_low_sdio_clk(struct sdio_func *func);
++extern void *ssv6xxx_ifdebug_info[];
++extern int ssv_devicetype;
++extern void ssv6xxx_deinit_prepare(void);
++
++static struct ssv6xxx_platform_data wlan_data;
++
++static int ssv6xxx_sdio_status = 0;
++u32 sdio_sr_bhvr = SUSPEND_RESUME_0;
++EXPORT_SYMBOL(sdio_sr_bhvr);
++
++u32 shutdown_flags = SSV_SYS_REBOOT;
++
++struct ssv6xxx_sdio_glue {
++	struct device *dev;
++	struct platform_device *core;
++	struct sk_buff *dma_skb;
++#ifdef CONFIG_PM
++	struct sk_buff *cmd_skb;
++#endif
++	unsigned int ioport_data;
++	unsigned int ioport_reg;
++	irq_handler_t irq_handler;
++	void *irq_dev;
++	bool dev_ready;
++};
++
++static const struct sdio_device_id ssv6xxx_sdio_devices[] = {
++	{SDIO_DEVICE(SSV_VENDOR_ID, SSV_CABRIO_DEVID)},
++	{}
++};
++
++MODULE_DEVICE_TABLE(sdio, ssv6xxx_sdio_devices);
++
++static bool ssv6xxx_is_ready(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++
++	ret_if_not_ready(false);
++
++	return true;
++}
++
++static int ssv6xxx_sdio_cmd52_read(struct device *child, u32 addr, u32 * value)
++{
++	int ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++	ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    *value = sdio_readb(func, addr, &ret);
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int ssv6xxx_sdio_cmd52_write(struct device *child, u32 addr, u32 value)
++{
++	int ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready(-1);
++
++	func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    sdio_writeb(func, value, addr, &ret);
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int __must_check
++ssv6xxx_sdio_read_reg(struct device *child, u32 addr, u32 * buf)
++{
++	int ret;
++
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	u32 data;
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++
++    sdio_claim_host(func);
++
++    data = addr;
++
++    sdio_writel(func, addr, glue->ioport_reg, &ret);
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read reg write address failed (%d)\n", ret);
++        goto io_err;
++    }
++
++    data = sdio_readl(func, glue->ioport_reg, &ret);
++
++    if (unlikely(ret)) {
++        *buf = 0xffffffff;
++        dev_err(child->parent, "sdio read reg from I/O failed (%d)\n", ret);
++        goto io_err;
++    }
++
++    *buf = data;
++
++io_err:
++    sdio_release_host(func);
++
++	return ret;
++}
++
++#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
++static int ssv6xxx_sdio_trigger_tx_rx(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	struct mmc_host *host;
++
++	if (glue == NULL)
++		return -1;
++
++	func = dev_to_sdio_func(glue->dev);
++	host = func->card->host;
++	mmc_signal_sdio_irq(host);
++
++	return 0;
++
++}
++#endif
++
++static int __must_check
++ssv6xxx_sdio_write_reg(struct device *child, u32 addr, u32 buf)
++{
++	int ret;
++
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    u32 data[2];
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++
++    sdio_claim_host(func);
++    data[0] = addr;
++    data[1] = buf;
++
++    ret = sdio_memcpy_toio(func, glue->ioport_reg, data, sizeof(data));
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int
++ssv6xxx_sdio_write_sram(struct device *child, u32 addr, u8 * data, u32 size)
++{
++	int ret = 0;
++	struct ssv6xxx_sdio_glue *glue;
++	struct sdio_func *func = NULL;
++	glue = dev_get_drvdata(child->parent);
++
++    ret_if_not_ready(-1);
++
++	func = dev_to_sdio_func(glue->dev);
++	sdio_claim_host(func);
++
++    ret |= ssv6xxx_sdio_write_reg(child, 0xc0000860, addr);
++    if (unlikely(ret))
++        goto out;
++
++    sdio_writeb(func, 0x2, REG_Fn1_STATUS, &ret);
++    if (unlikely(ret))
++        goto out;
++
++    ret = sdio_memcpy_toio(func, glue->ioport_data, data, size);
++    if (unlikely(ret))
++        goto out;
++
++    sdio_writeb(func, 0, REG_Fn1_STATUS, &ret);
++    if (unlikely(ret))
++        goto out;
++
++out:
++	sdio_release_host(func);
++	return ret;
++
++}
++
++struct file *ssv6xxx_open_firmware(char *user_mainfw)
++{
++	struct file *fp;
++	fp = filp_open(user_mainfw, O_RDONLY, 0);
++
++	if (IS_ERR(fp))
++		fp = NULL;
++
++	return fp;
++}
++
++int ssv6xxx_read_fw_block(char *buf, int len, struct file *fp)
++{
++
++	int read;
++	loff_t pos;
++
++	pos = fp->f_pos;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
++	read = kernel_read(fp, (void *)buf, len, &pos);
++#else
++	read = kernel_read(fp, pos, buf, len);
++#endif
++
++	if (read > 0)
++		fp->f_pos += read;
++
++	return read;
++
++}
++
++void ssv6xxx_close_firmware(struct file *fp)
++{
++	if (fp)
++		filp_close(fp, NULL);
++}
++
++static int
++ssv6xxx_sdio_upload_firmware(struct device *child, const u8 *firmware, u32 firmware_length)
++{
++	int ret;
++    u32 clk_en;
++	u32 word_count, i;
++    u32 block_size;
++	u8 *buffer;
++	u32 sram_ptr = 0;
++	u32 block_count = 0;
++    u32 firmware_ptr = 0;
++
++	u32 checksum = FW_CHECKSUM_INIT;
++	u32 fw_checksum, fw_blkcnt;
++
++	struct ssv6xxx_sdio_glue *glue;
++
++	glue = dev_get_drvdata(child->parent);
++
++    if ((wlan_data.is_enabled == false) &&
++        (glue == NULL) &&
++        (glue->dev_ready == false))
++        goto out;
++
++    buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL);
++    if (buffer == NULL) {
++        dev_err(child, "Failed to allocate buffer for firmware.\n");
++        ret = -ENOMEM;
++        goto out;
++    }
++
++    dev_dbg(child, "preparing registers and clock for firmware upload\n");
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x0);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_BOOT, 0x01);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_read_reg(child, ADR_PLATFORM_CLOCK_ENABLE, &clk_en);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_PLATFORM_CLOCK_ENABLE, clk_en | (1 << 2));
++    if (unlikely(ret))
++        goto out;
++
++    dev_dbg(child, "begin writing firmware\n");
++
++    while (firmware_length > 0) {
++
++        memset(buffer, 0xA5, FW_BLOCK_SIZE);
++
++        block_size = firmware_length;
++        if (block_size > FW_BLOCK_SIZE)
++            block_size = FW_BLOCK_SIZE;
++
++        memcpy(buffer, &firmware[firmware_ptr], block_size);
++
++        firmware_ptr += block_size;
++        firmware_length -= block_size;
++
++        /*
++         * Uploading to chip sram and checksumming happens in chunks of CHECKSUM_BLOCK_SIZE,
++         * so we round the block size accordingly and use that valueù
++         */
++        block_size = DIV_ROUND_UP(block_size, CHECKSUM_BLOCK_SIZE) * CHECKSUM_BLOCK_SIZE;
++        ret = ssv6xxx_sdio_write_sram(child, sram_ptr, (u8 *)buffer, block_size);
++
++        if (ret) {
++            dev_err(child, "firmware upload failed\n");
++            goto out;
++        }
++
++        sram_ptr += block_size;
++
++        word_count = block_size / sizeof(u32);
++        for (i = 0; i < word_count; i++)
++            checksum += ((u32 *)buffer)[i];
++
++    }
++
++    checksum = ((checksum >> 24) +
++                (checksum >> 16) +
++                (checksum >> 8) +
++                checksum) & 0x0FF;
++    checksum <<= 16;
++
++    block_count = DIV_ROUND_UP(sram_ptr, CHECKSUM_BLOCK_SIZE);
++    ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (block_count << 16));
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_blkcnt);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x1);
++    if (unlikely(ret))
++        goto out;
++
++    dev_info(child, "firmware upload complete (wrote %d blocks, verified %d blocks)\n", block_count, fw_blkcnt >> 16);
++
++    msleep(50);
++
++    ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_checksum);
++    fw_checksum = fw_checksum & FW_STATUS_MASK;
++
++    if (fw_checksum == checksum) {
++        dev_dbg(child, "firmware check ok, checksum=0x%x\n", checksum);
++        ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (~checksum & FW_STATUS_MASK));
++        if (unlikely(ret))
++            dev_warn(child, "could not clear checksum condition");
++    } else {
++        dev_err(child, "firmware checksum mismatch, local=0x%x, sram=0x%x\n", checksum, fw_checksum);
++    }
++
++    msleep(50);
++
++    ret = 0;
++
++ out:
++
++	if (buffer)
++		kfree(buffer);
++
++	return ret;
++
++}
++
++static int
++ssv6xxx_sdio_load_firmware(struct device *child, u8 *firmware_name, u8 openfile)
++{
++
++    int ret;
++    const struct firmware *firmware = NULL;
++    struct sdio_func *func;
++   	struct ssv6xxx_sdio_glue *glue;
++
++    glue = dev_get_drvdata(child->parent);
++
++    ret = request_firmware(&firmware, firmware_name, glue->dev);
++
++    if (ret) {
++        dev_err(child, "could not find firmware file %s, err=%d\n", firmware_name, ret);
++        goto out;
++    }
++
++    ret = ssv6xxx_sdio_upload_firmware(child, firmware->data, firmware->size);
++
++    if (ret) {
++        dev_err(child, "could not upload firmware to device, err=%d\n", ret);
++        goto out;
++    }
++
++    if (glue != NULL) {
++		func = dev_to_sdio_func(glue->dev);
++		ssv6xxx_high_sdio_clk(func);
++	}
++
++out:
++    if (firmware != NULL)
++        release_firmware(firmware);
++
++    return ret;
++
++}
++
++static int ssv6xxx_sdio_irq_getstatus(struct device *child, int *status)
++{
++	int ret = (-1);
++	struct ssv6xxx_sdio_glue *glue;
++	struct sdio_func *func;
++	glue = dev_get_drvdata(child->parent);
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    *status = sdio_readb(func, REG_INT_STATUS, &ret);
++    sdio_release_host(func);
++
++    return ret;
++
++}
++
++static int __must_check
++ssv6xxx_sdio_read(struct device *child, void *buf, size_t *size)
++{
++
++	int ret;
++    u32 data_size;
++
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++
++    data_size = sdio_readb(func, REG_CARD_PKT_LEN_0, &ret);
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read high byte len failed, ret=%d\n", ret);
++        goto out;
++    }
++
++    data_size = data_size | (sdio_readb(func, REG_CARD_PKT_LEN_1, &ret) << 0x8);
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read low len failed ret[%d]\n", ret);
++        goto out;
++    }
++
++    ret = sdio_memcpy_fromio(func, buf, glue->ioport_data, sdio_align_size(func, data_size));
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read failed size ret[%d]\n", ret);
++        goto out;
++    }
++    
++    *size = data_size;
++
++out:
++
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int __must_check
++ssv6xxx_sdio_write(struct device *child, void *buf, size_t len, u8 queue_num)
++{
++	int ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	void *ptr;
++
++    ret_if_not_ready(-1);
++
++#ifdef CONFIG_ARM64
++    if (((u64) buf) & 3) {
++#else
++    if (((u32) buf) & 3) {
++#endif
++        memcpy(glue->dma_skb->data, buf, len);
++        ptr = glue->dma_skb->data;
++    } else
++        ptr = buf;
++
++    func = dev_to_sdio_func(glue->dev);
++
++    sdio_claim_host(func);
++
++    len = sdio_align_size(func, len);
++    ret = sdio_memcpy_toio(func, glue->ioport_data, ptr, len);
++
++    if (unlikely(ret))
++        dev_err(glue->dev, "sdio write failed, ret=%d\n", ret);
++
++    sdio_release_host(func);
++
++    return ret;
++
++}
++
++static void ssv6xxx_sdio_irq_handler(struct sdio_func *func)
++{
++	int status;
++	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++
++    ret_if_not_ready();
++
++    if (glue->irq_handler == NULL)
++        return;
++
++    atomic_set(&pwlan_data->irq_handling, 1);
++    sdio_release_host(func);
++    if (glue->irq_handler != NULL)
++        status = glue->irq_handler(0, glue->irq_dev);
++    sdio_claim_host(func);
++    atomic_set(&pwlan_data->irq_handling, 0);
++
++}
++
++static void ssv6xxx_sdio_irq_setmask(struct device *child, int mask)
++{
++	int err_ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready();
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    sdio_writeb(func, mask, REG_INT_MASK, &err_ret);
++    sdio_release_host(func);
++
++}
++
++static void ssv6xxx_sdio_irq_trigger(struct device *child)
++{
++	int err_ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready();
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    sdio_writeb(func, 0x2, REG_INT_TRIGGER, &err_ret);
++    sdio_release_host(func);
++
++}
++
++static int ssv6xxx_sdio_irq_getmask(struct device *child, u32 * mask)
++{
++	u8 imask = 0;
++	int ret = (-1);
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    imask = sdio_readb(func, REG_INT_MASK, &ret);
++    *mask = imask;
++    sdio_release_host(func);
++
++	return ret;
++
++}
++
++static void ssv6xxx_sdio_irq_enable(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	int ret;
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++	if ((pwlan_data->is_enabled == false)
++	    || (glue == NULL) || (glue->dev_ready == false))
++		return;
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    ret = sdio_claim_irq(func, ssv6xxx_sdio_irq_handler);
++    if (ret)
++        dev_err(child->parent, "Failed to claim sdio irq: %d\n",
++            ret);
++    sdio_release_host(func);
++
++	dev_dbg(child, "ssv6xxx_sdio_irq_enable\n");
++
++}
++
++static void ssv6xxx_sdio_irq_disable(struct device *child, bool iswaitirq)
++{
++	struct ssv6xxx_sdio_glue *glue = NULL;
++	struct sdio_func *func;
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++	int ret;
++
++	dev_dbg(child, "ssv6xxx_sdio_irq_disable\n");
++
++	if ((wlan_data.is_enabled == false) || (child->parent == NULL))
++		return;
++
++	glue = dev_get_drvdata(child->parent);
++
++
++	if ((glue == NULL) || (glue->dev_ready == false)
++	    || (glue->dev == NULL))
++		return;
++
++    func = dev_to_sdio_func(glue->dev);
++
++    if (func == NULL) {
++        dev_dbg(child, "sdio func == NULL\n");
++        return;
++    }
++
++    sdio_claim_host(func);
++    while (atomic_read(&pwlan_data->irq_handling)) {
++        sdio_release_host(func);
++        schedule_timeout(HZ / 10);
++        sdio_claim_host(func);
++    }
++    ret = sdio_release_irq(func);
++
++    if (ret)
++        dev_err(child->parent,
++            "Failed to release sdio irq: %d\n", ret);
++
++    sdio_release_host(func);
++
++}
++
++static void
++ssv6xxx_sdio_irq_request(struct device *child, irq_handler_t irq_handler,
++			 void *irq_dev)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	bool isIrqEn = false;
++
++    ret_if_not_ready();
++
++    func = dev_to_sdio_func(glue->dev);
++    glue->irq_handler = irq_handler;
++    glue->irq_dev = irq_dev;
++    if (isIrqEn) {
++        ssv6xxx_sdio_irq_enable(child);
++    }
++
++}
++
++static void
++ssv6xxx_sdio_read_parameter(struct sdio_func *func,
++			    struct ssv6xxx_sdio_glue *glue)
++{
++	int err_ret;
++	sdio_claim_host(func);
++	glue->ioport_data = 0;
++	glue->ioport_data =
++	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret)
++				<< (8 * 0));
++	glue->ioport_data =
++	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret)
++				<< (8 * 1));
++	glue->ioport_data =
++	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret)
++				<< (8 * 2));
++	glue->ioport_reg = 0;
++	glue->ioport_reg =
++	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) <<
++			       (8 * 0));
++	glue->ioport_reg =
++	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) <<
++			       (8 * 1));
++	glue->ioport_reg =
++	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) <<
++			       (8 * 2));
++	dev_dbg(&func->dev, "ioport_data=0x%x ioport_reg=0x%x\n",
++		glue->ioport_data, glue->ioport_reg);
++	err_ret = sdio_set_block_size(func, CONFIG_PLATFORM_SDIO_BLOCK_SIZE);
++	if (err_ret != 0) {
++		dev_warn(&func->dev, "SDIO setting SDIO_DEF_BLOCK_SIZE fail!!\n");
++	}
++	sdio_writeb(func, CONFIG_PLATFORM_SDIO_OUTPUT_TIMING,
++		    REG_OUTPUT_TIMING_REG, &err_ret);
++	sdio_writeb(func, 0x00, REG_Fn1_STATUS, &err_ret);
++	sdio_release_host(func);
++}
++
++static void ssv6xxx_do_sdio_wakeup(struct sdio_func *func)
++{
++	int err_ret;
++	if (func != NULL) {
++		sdio_claim_host(func);
++		sdio_writeb(func, 0x01, REG_PMU_WAKEUP, &err_ret);
++		mdelay(10);
++		sdio_writeb(func, 0x00, REG_PMU_WAKEUP, &err_ret);
++		sdio_release_host(func);
++	}
++}
++
++static void ssv6xxx_sdio_pmu_wakeup(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	if (glue != NULL) {
++		func = dev_to_sdio_func(glue->dev);
++		ssv6xxx_do_sdio_wakeup(func);
++	}
++}
++
++static bool ssv6xxx_sdio_support_scatter(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    if (!glue) {
++        dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
++        return false;
++    }
++
++    func = dev_to_sdio_func(glue->dev);
++
++    if (func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
++        dev_err(child->parent,
++            "host controller only supports scatter of :%d entries, driver need: %d\n",
++            func->card->host->max_segs,
++            MAX_SCATTER_ENTRIES_PER_REQ);
++        return false;
++    }
++
++    return true;
++
++}
++
++static void
++ssv6xxx_sdio_setup_scat_data(struct sdio_scatter_req *scat_req,
++			     struct mmc_data *data)
++{
++	struct scatterlist *sg;
++	int i;
++	data->blksz = SDIO_DEF_BLOCK_SIZE;
++	data->blocks = scat_req->len / SDIO_DEF_BLOCK_SIZE;
++	pr_debug
++	    ("scatter: (%s)  (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
++	     (scat_req->req & SDIO_WRITE) ? "WR" : "RD", data->blksz,
++	     data->blocks, scat_req->len, scat_req->scat_entries);
++	data->flags =
++	    (scat_req->req & SDIO_WRITE) ? MMC_DATA_WRITE : MMC_DATA_READ;
++	sg = scat_req->sgentries;
++	sg_init_table(sg, scat_req->scat_entries);
++	for (i = 0; i < scat_req->scat_entries; i++, sg++) {
++		pr_debug("%d: addr:0x%p, len:%d\n",
++		       i, scat_req->scat_list[i].buf,
++		       scat_req->scat_list[i].len);
++		sg_set_buf(sg, scat_req->scat_list[i].buf,
++			   scat_req->scat_list[i].len);
++	}
++	data->sg = scat_req->sgentries;
++	data->sg_len = scat_req->scat_entries;
++}
++
++static inline void
++ssv6xxx_sdio_set_cmd53_arg(u32 * arg, u8 rw, u8 func,
++			   u8 mode, u8 opcode, u32 addr, u16 blksz)
++{
++	*arg = (((rw & 1) << 31) |
++		((func & 0x7) << 28) |
++		((mode & 1) << 27) |
++		((opcode & 1) << 26) | ((addr & 0x1FFFF) << 9) | (blksz &
++								  0x1FF));
++}
++
++static int
++ssv6xxx_sdio_rw_scatter(struct device *child, struct sdio_scatter_req *scat_req)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	struct mmc_request mmc_req;
++	struct mmc_command cmd;
++	struct mmc_data data;
++	u8 opcode, rw;
++	int status = 1;
++
++    if (!glue) {
++        dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
++        return 1;
++    }
++
++    func = dev_to_sdio_func(glue->dev);
++    memset(&mmc_req, 0, sizeof(struct mmc_request));
++    memset(&cmd, 0, sizeof(struct mmc_command));
++    memset(&data, 0, sizeof(struct mmc_data));
++    ssv6xxx_sdio_setup_scat_data(scat_req, &data);
++    opcode = 0;
++    rw = (scat_req->req & SDIO_WRITE) ? CMD53_ARG_WRITE :
++        CMD53_ARG_READ;
++    ssv6xxx_sdio_set_cmd53_arg(&cmd.arg, rw, func->num,
++                    CMD53_ARG_BLOCK_BASIS, opcode,
++                    glue->ioport_data, data.blocks);
++    cmd.opcode = SD_IO_RW_EXTENDED;
++    cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
++    mmc_req.cmd = &cmd;
++    mmc_req.data = &data;
++    mmc_set_data_timeout(&data, func->card);
++    mmc_wait_for_req(func->card->host, &mmc_req);
++
++    status = cmd.error ? cmd.error : data.error;
++
++    if (cmd.error)
++        return cmd.error;
++
++    if (data.error)
++        return data.error;
++
++    return status;
++
++}
++
++static void ssv6xxx_set_sdio_clk(struct sdio_func *func, u32 sdio_hz)
++{
++	struct mmc_host *host;
++	host = func->card->host;
++	if (sdio_hz < host->f_min)
++		sdio_hz = host->f_min;
++	else if (sdio_hz > host->f_max)
++		sdio_hz = host->f_max;
++	dev_dbg(&func->dev, "%s:set sdio clk %dHz\n", __FUNCTION__, sdio_hz);
++	sdio_claim_host(func);
++	host->ios.clock = sdio_hz;
++	host->ops->set_ios(host, &host->ios);
++	mdelay(20);
++	sdio_release_host(func);
++}
++
++static void ssv6xxx_low_sdio_clk(struct sdio_func *func)
++{
++	ssv6xxx_set_sdio_clk(func, LOW_SPEED_SDIO_CLOCK);
++}
++
++static void ssv6xxx_high_sdio_clk(struct sdio_func *func)
++{
++#ifndef SDIO_USE_SLOW_CLOCK
++	ssv6xxx_set_sdio_clk(func, HIGH_SPEED_SDIO_CLOCK);
++#endif
++}
++
++static struct ssv6xxx_hwif_ops sdio_ops = {
++	.read = ssv6xxx_sdio_read,
++	.write = ssv6xxx_sdio_write,
++	.readreg = ssv6xxx_sdio_read_reg,
++	.writereg = ssv6xxx_sdio_write_reg,
++#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
++	.trigger_tx_rx = ssv6xxx_sdio_trigger_tx_rx,
++#endif
++	.irq_getmask = ssv6xxx_sdio_irq_getmask,
++	.irq_setmask = ssv6xxx_sdio_irq_setmask,
++	.irq_enable = ssv6xxx_sdio_irq_enable,
++	.irq_disable = ssv6xxx_sdio_irq_disable,
++	.irq_getstatus = ssv6xxx_sdio_irq_getstatus,
++	.irq_request = ssv6xxx_sdio_irq_request,
++	.irq_trigger = ssv6xxx_sdio_irq_trigger,
++	.pmu_wakeup = ssv6xxx_sdio_pmu_wakeup,
++	.load_fw = ssv6xxx_sdio_load_firmware,
++	.cmd52_read = ssv6xxx_sdio_cmd52_read,
++	.cmd52_write = ssv6xxx_sdio_cmd52_write,
++	.support_scatter = ssv6xxx_sdio_support_scatter,
++	.rw_scatter = ssv6xxx_sdio_rw_scatter,
++	.is_ready = ssv6xxx_is_ready,
++	.write_sram = ssv6xxx_sdio_write_sram,
++	.interface_reset = ssv6xxx_sdio_reset,
++};
++
++static int
++ssv6xxx_sdio_power_on(struct ssv6xxx_platform_data *pdata,
++		      struct sdio_func *func)
++{
++	int ret = 0;
++	if (pdata->is_enabled == true)
++		return 0;
++
++	dev_dbg(&func->dev, "ssv6xxx_sdio_power_on\n");
++
++	sdio_claim_host(func);
++	ret = sdio_enable_func(func);
++	sdio_release_host(func);
++
++	if (ret) {
++		dev_err(&func->dev, "Unable to enable sdio func: %d)\n", ret);
++		return ret;
++	}
++
++	msleep(10);
++	pdata->is_enabled = true;
++
++	return ret;
++}
++
++static int
++ssv6xxx_sdio_power_off(struct ssv6xxx_platform_data *pdata,
++		       struct sdio_func *func)
++{
++	int ret;
++	if (pdata->is_enabled == false)
++		return 0;
++	dev_dbg(&func->dev, "ssv6xxx_sdio_power_off\n");
++	sdio_claim_host(func);
++	ret = sdio_disable_func(func);
++	sdio_release_host(func);
++	if (ret)
++		return ret;
++	pdata->is_enabled = false;
++	return ret;
++}
++
++int ssv6xxx_get_dev_status(void)
++{
++	return ssv6xxx_sdio_status;
++}
++
++EXPORT_SYMBOL(ssv6xxx_get_dev_status);
++
++static int
++ssv6xxx_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id)
++{
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++	struct ssv6xxx_sdio_glue *glue;
++	int ret;
++	const char *chip_family = "ssv6200";
++
++	if (ssv_devicetype != 0) {
++		dev_info(&func->dev, "Not using SSV6200 normal SDIO driver.\n");
++		return -ENODEV;
++	}
++
++	if (func->num != 0x01)
++		return -ENODEV;
++
++	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
++
++	if (!glue) {
++		dev_err(&func->dev, "can't allocate glue\n");
++		return -ENOMEM;
++	}
++
++	ssv6xxx_sdio_status = 1;
++	ssv6xxx_low_sdio_clk(func);
++
++	glue->dma_skb = __dev_alloc_skb(SDIO_DMA_BUFFER_LEN, GFP_KERNEL);
++
++#ifdef CONFIG_PM
++	glue->cmd_skb = __dev_alloc_skb(SDIO_COMMAND_BUFFER_LEN, GFP_KERNEL);
++#endif
++	memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data));
++	atomic_set(&pwlan_data->irq_handling, 0);
++	glue->dev = &func->dev;
++	func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
++	func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
++	glue->dev_ready = true;
++	pwlan_data->vendor = func->vendor;
++	pwlan_data->device = func->device;
++	dev_info(glue->dev, "device id: %x:%x\n", pwlan_data->vendor,
++		pwlan_data->device);
++	pwlan_data->ops = &sdio_ops;
++	sdio_set_drvdata(func, glue);
++#ifdef CONFIG_PM
++	ssv6xxx_do_sdio_wakeup(func);
++#endif
++	ssv6xxx_sdio_power_on(pwlan_data, func);
++	ssv6xxx_sdio_read_parameter(func, glue);
++	glue->core = platform_device_alloc(chip_family, -1);
++
++	if (!glue->core) {
++		dev_err(glue->dev, "can't allocate platform_device");
++		ret = -ENOMEM;
++		goto out_free_glue;
++	}
++
++	glue->core->dev.parent = &func->dev;
++
++	ret = platform_device_add_data(glue->core, pwlan_data,
++				       sizeof(*pwlan_data));
++
++	if (ret) {
++		dev_err(glue->dev, "can't add platform data\n");
++		goto out_dev_put;
++	}
++
++	ret = platform_device_add(glue->core);
++
++	if (ret) {
++		dev_err(glue->dev, "can't add platform device\n");
++		goto out_dev_put;
++	}
++
++	ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
++
++	ssv6xxx_ifdebug_info[0] = (void *)&glue->core->dev;
++	ssv6xxx_ifdebug_info[1] = (void *)glue->core;
++	ssv6xxx_ifdebug_info[2] = (void *)&sdio_ops;
++	return 0;
++
++ out_dev_put:
++	platform_device_put(glue->core);
++ out_free_glue:
++	kfree(glue);
++
++	return ret;
++
++}
++
++static void ssv6xxx_sdio_remove(struct sdio_func *func)
++{
++	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++
++	dev_dbg(&func->dev, "ssv6xxx_sdio_remove enter\n");
++
++	ssv6xxx_sdio_status = 0;
++
++	if (glue) {
++		dev_dbg(&func->dev, "ssv6xxx_sdio_remove - ssv6xxx_sdio_irq_disable\n");
++		ssv6xxx_sdio_irq_disable(&glue->core->dev, false);
++		glue->dev_ready = false;
++		ssv6xxx_low_sdio_clk(func);
++
++		if (glue->dma_skb != NULL)
++			dev_kfree_skb(glue->dma_skb);
++
++		dev_dbg(&func->dev, "ssv6xxx_sdio_remove - disable mask\n");
++		ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
++#ifdef CONFIG_PM
++		ssv6xxx_sdio_trigger_pmu(glue->dev);
++		if (glue->cmd_skb != NULL)
++			dev_kfree_skb(glue->cmd_skb);
++#endif
++		ssv6xxx_sdio_power_off(pwlan_data, func);
++		dev_dbg(&func->dev, "platform_device_del \n");
++		platform_device_del(glue->core);
++		dev_dbg(&func->dev, "platform_device_put \n");
++		platform_device_put(glue->core);
++		kfree(glue);
++	}
++
++	sdio_set_drvdata(func, NULL);
++	dev_dbg(&func->dev, "ssv6xxx_sdio_remove leave\n");
++
++}
++
++static int ssv6xxx_sdio_trigger_pmu(struct device *dev)
++{
++
++	int ret = 0;
++
++#ifdef CONFIG_PM
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
++	struct cfg_host_cmd *host_cmd;
++	int writesize;
++	void *tempPointer;
++
++	if (ssv6xxx_sdio_write_reg
++	    (dev, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
++	if (ssv6xxx_sdio_write_reg
++	    (dev, ADR_RX_FLOW_DATA, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
++	if (ssv6xxx_sdio_write_reg
++	    (dev, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
++
++	host_cmd = (struct cfg_host_cmd *)glue->cmd_skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->RSVD0 = 0;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
++	host_cmd->len = sizeof(struct cfg_host_cmd);
++
++	host_cmd->dummy = 0;
++
++	{
++		tempPointer = glue->cmd_skb->data;
++		sdio_claim_host(func);
++		writesize = sdio_align_size(func, sizeof(struct cfg_host_cmd));
++		do {
++			ret =
++			    sdio_memcpy_toio(func, glue->ioport_data,
++					     tempPointer, writesize);
++			if (ret == -EILSEQ || ret == -ETIMEDOUT) {
++				ret = -1;
++				break;
++			} else {
++				if (ret)
++					dev_err(glue->dev,
++						"Unexpected return value ret=[%d]\n",
++						ret);
++			}
++		}
++		while (ret == -EILSEQ || ret == -ETIMEDOUT);
++		sdio_release_host(func);
++		if (ret)
++			dev_err(glue->dev, "sdio write failed (%d)\n", ret);
++	}
++
++#endif
++
++	return ret;
++
++}
++
++static void ssv6xxx_sdio_reset(struct device *child)
++{
++
++#ifdef CONFIG_PM
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func = dev_to_sdio_func(glue->dev);
++	dev_dbg(child, "%s\n", __FUNCTION__);
++	if (glue == NULL || glue->dev == NULL || func == NULL)
++		return;
++	ssv6xxx_sdio_trigger_pmu(glue->dev);
++	ssv6xxx_do_sdio_wakeup(func);
++#endif
++
++	return;
++
++}
++
++#ifdef CONFIG_PM
++static int ssv6xxx_sdio_suspend(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	mmc_pm_flag_t flags = sdio_get_host_pm_caps(func);
++	{
++		int ret = 0;
++		dev_info(dev, "%s: suspend: PM flags = 0x%x\n",
++			 sdio_func_id(func), flags);
++		ssv6xxx_low_sdio_clk(func);
++		ret = ssv6xxx_sdio_trigger_pmu(dev);
++		if (ret)
++			dev_warn(dev, "ssv6xxx_sdio_trigger_pmu fail!!\n");
++		if (!(flags & MMC_PM_KEEP_POWER)) {
++			dev_err(dev,
++				"%s: cannot remain alive while host is suspended\n",
++				sdio_func_id(func));
++		}
++		ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
++		if (ret)
++			return ret;
++		mdelay(10);
++		return ret;
++	}
++}
++
++static int ssv6xxx_sdio_resume(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	{
++		dev_dbg(dev, "ssv6xxx_sdio_resume\n");
++		{
++			ssv6xxx_do_sdio_wakeup(func);
++			mdelay(10);
++			ssv6xxx_high_sdio_clk(func);
++			mdelay(10);
++		}
++	}
++	return 0;
++}
++
++static const struct dev_pm_ops ssv6xxx_sdio_pm_ops = {
++	.suspend = ssv6xxx_sdio_suspend,
++	.resume = ssv6xxx_sdio_resume,
++};
++#endif
++
++struct sdio_driver ssv6xxx_sdio_driver = {
++	.name = "ssv6051",
++	.id_table = ssv6xxx_sdio_devices,
++	.probe = ssv6xxx_sdio_probe,
++	.remove = ssv6xxx_sdio_remove,
++#ifdef CONFIG_PM
++	.drv = {
++		.pm = &ssv6xxx_sdio_pm_ops,
++		},
++#endif
++};
++
++EXPORT_SYMBOL(ssv6xxx_sdio_driver);
++
++int ssv6xxx_sdio_init(void)
++{
++	return sdio_register_driver(&ssv6xxx_sdio_driver);
++}
++
++void ssv6xxx_sdio_exit(void)
++{
++	pr_info("ssv6xxx_sdio_exit\n");
++	sdio_unregister_driver(&ssv6xxx_sdio_driver);
++}
++
++EXPORT_SYMBOL(ssv6xxx_sdio_init);
++EXPORT_SYMBOL(ssv6xxx_sdio_exit);
+diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
+new file mode 100644
+index 000000000000..57aefd3bf9fa
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SDIO_DEF_H_
++#define _SDIO_DEF_H_
++#include <linux/scatterlist.h>
++#define BASE_SDIO 0
++#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00)
++#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01)
++#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02)
++#define REG_INT_MASK (BASE_SDIO + 0x04)
++#define REG_INT_STATUS (BASE_SDIO + 0x08)
++#define REG_INT_TRIGGER (BASE_SDIO + 0x09)
++#define REG_Fn1_STATUS (BASE_SDIO + 0x0c)
++#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10)
++#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11)
++#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12)
++#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13)
++#define REG_CARD_RCA_0 (BASE_SDIO + 0x20)
++#define REG_CARD_RCA_1 (BASE_SDIO + 0x21)
++#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24)
++#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25)
++#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55)
++#define REG_PMU_WAKEUP (BASE_SDIO + 0x67)
++#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70)
++#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71)
++#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72)
++#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98)
++#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99)
++#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a)
++#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c)
++#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d)
++#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e)
++#define SDIO_DEF_BLOCK_SIZE 0x80
++#if (SDIO_DEF_BLOCK_SIZE % 8)
++#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
++#endif
++#define SDIO_DEF_OUTPUT_TIMING 0
++#define SDIO_DEF_BLOCK_MODE_THRD 128
++#if (SDIO_DEF_BLOCK_MODE_THRD % 8)
++#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
++#endif
++#define SDIO_DEF_FORCE_BLOCK_MODE 0
++#define MAX_SCATTER_ENTRIES_PER_REQ 8
++struct sdio_scatter_item {
++	u8 *buf;
++	int len;
++};
++struct sdio_scatter_req {
++	u32 req;
++	u32 len;
++	int scat_entries;
++	struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];
++	struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
++};
++#define SDIO_READ 0x00000001
++#define SDIO_WRITE 0x00000002
++#define CMD53_ARG_READ 0
++#define CMD53_ARG_WRITE 1
++#define CMD53_ARG_BLOCK_BASIS 1
++#define CMD53_ARG_FIXED_ADDRESS 0
++#define CMD53_ARG_INCR_ADDRESS 1
++#define SDIO_DMA_BUFFER_LEN 2048
++#ifdef CONFIG_PM
++#define SDIO_COMMAND_BUFFER_LEN 256
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/cabrio.h b/drivers/net/wireless/ssv6051/include/cabrio.h
+new file mode 100644
+index 000000000000..0b1327865c6b
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/cabrio.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef CABRIO_H
++#define CABRIO_H
++#define SSV_VENDOR_ID 0x3030
++#define SSV_CABRIO_DEVID 0x3030
++#define SSV_SUBVENDOR_ID_NOG 0x0e11
++#define SSV_SUBVENDOR_ID_NEW_A 0x7065
++#define SSV_CABRIO_MAGIC 0x19641014
++#define SSV_AMPDU_LIMIT_MAX (64 * 1024 - 1)
++#define SSV_DEFAULT_NOISE_FLOOR -95
++#define SSVCABRIO_RSSI_BAD -128
++#define SSVCABRIO_NUM_CHANNELS 38
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200.h b/drivers/net/wireless/ssv6051/include/ssv6200.h
+new file mode 100644
+index 000000000000..22eaceaf285d
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200.h
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV6200_H_
++#define _SSV6200_H_
++#include <linux/device.h>
++#include <linux/interrupt.h>
++#include <net/mac80211.h>
++#ifdef ECLIPSE
++#include <ssv_mod_conf.h>
++#endif
++#include <ssv6200_reg.h>
++#include <ssv6200_aux.h>
++#include <hwif/hwif.h>
++#include <hci/ssv_hci.h>
++#include "ssv6200_common.h"
++#define SSV6200_TOTAL_ID 128
++#ifndef HUW_DRV
++#define SSV6200_ID_TX_THRESHOLD 19
++#define SSV6200_ID_RX_THRESHOLD 60
++#define SSV6200_PAGE_TX_THRESHOLD 115
++#define SSV6200_PAGE_RX_THRESHOLD 115
++#define SSV6XXX_AMPDU_DIVIDER (2)
++#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6XXX_AMPDU_DIVIDER))
++#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
++#else
++#undef SSV6200_ID_TX_THRESHOLD
++#undef SSV6200_ID_RX_THRESHOLD
++#undef SSV6200_PAGE_TX_THRESHOLD
++#undef SSV6200_PAGE_RX_THRESHOLD
++#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
++#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
++#define SSV6200_ID_TX_THRESHOLD 31
++#define SSV6200_ID_RX_THRESHOLD 31
++#define SSV6200_PAGE_TX_THRESHOLD 61
++#define SSV6200_PAGE_RX_THRESHOLD 61
++#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
++#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
++#endif
++#define SSV6200_ID_NUMBER (128)
++#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
++#define SSV6200_ID_AC_RESERVED 1
++#define SSV6200_ID_AC_BK_OUT_QUEUE 8
++#define SSV6200_ID_AC_BE_OUT_QUEUE 15
++#define SSV6200_ID_AC_VI_OUT_QUEUE 16
++#define SSV6200_ID_AC_VO_OUT_QUEUE 16
++#define SSV6200_ID_MANAGER_QUEUE 8
++#define HW_MMU_PAGE_SHIFT 0x8
++#define HW_MMU_PAGE_MASK 0xff
++#define SSV6200_BT_PRI_SMP_TIME 0
++#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0)
++#define SSV6200_WLAN_REMAIN_TIME 0
++#define BT_2WIRE_EN_MSK 0x00000400
++struct txResourceControl {
++	u32 txUsePage:8;
++	u32 txUseID:6;
++	u32 edca0:4;
++	u32 edca1:4;
++	u32 edca2:5;
++	u32 edca3:5;
++};
++#include <ssv_cfg.h>
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_aux.h b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
+new file mode 100644
+index 000000000000..03ec3f07d330
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
+@@ -0,0 +1,18221 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define MCU_ENABLE_MSK 0x00000001
++#define MCU_ENABLE_I_MSK 0xfffffffe
++#define MCU_ENABLE_SFT 0
++#define MCU_ENABLE_HI 0
++#define MCU_ENABLE_SZ 1
++#define MAC_SW_RST_MSK 0x00000002
++#define MAC_SW_RST_I_MSK 0xfffffffd
++#define MAC_SW_RST_SFT 1
++#define MAC_SW_RST_HI 1
++#define MAC_SW_RST_SZ 1
++#define MCU_SW_RST_MSK 0x00000004
++#define MCU_SW_RST_I_MSK 0xfffffffb
++#define MCU_SW_RST_SFT 2
++#define MCU_SW_RST_HI 2
++#define MCU_SW_RST_SZ 1
++#define SDIO_SW_RST_MSK 0x00000008
++#define SDIO_SW_RST_I_MSK 0xfffffff7
++#define SDIO_SW_RST_SFT 3
++#define SDIO_SW_RST_HI 3
++#define SDIO_SW_RST_SZ 1
++#define SPI_SLV_SW_RST_MSK 0x00000010
++#define SPI_SLV_SW_RST_I_MSK 0xffffffef
++#define SPI_SLV_SW_RST_SFT 4
++#define SPI_SLV_SW_RST_HI 4
++#define SPI_SLV_SW_RST_SZ 1
++#define UART_SW_RST_MSK 0x00000020
++#define UART_SW_RST_I_MSK 0xffffffdf
++#define UART_SW_RST_SFT 5
++#define UART_SW_RST_HI 5
++#define UART_SW_RST_SZ 1
++#define DMA_SW_RST_MSK 0x00000040
++#define DMA_SW_RST_I_MSK 0xffffffbf
++#define DMA_SW_RST_SFT 6
++#define DMA_SW_RST_HI 6
++#define DMA_SW_RST_SZ 1
++#define WDT_SW_RST_MSK 0x00000080
++#define WDT_SW_RST_I_MSK 0xffffff7f
++#define WDT_SW_RST_SFT 7
++#define WDT_SW_RST_HI 7
++#define WDT_SW_RST_SZ 1
++#define I2C_SLV_SW_RST_MSK 0x00000100
++#define I2C_SLV_SW_RST_I_MSK 0xfffffeff
++#define I2C_SLV_SW_RST_SFT 8
++#define I2C_SLV_SW_RST_HI 8
++#define I2C_SLV_SW_RST_SZ 1
++#define INT_CTL_SW_RST_MSK 0x00000200
++#define INT_CTL_SW_RST_I_MSK 0xfffffdff
++#define INT_CTL_SW_RST_SFT 9
++#define INT_CTL_SW_RST_HI 9
++#define INT_CTL_SW_RST_SZ 1
++#define BTCX_SW_RST_MSK 0x00000400
++#define BTCX_SW_RST_I_MSK 0xfffffbff
++#define BTCX_SW_RST_SFT 10
++#define BTCX_SW_RST_HI 10
++#define BTCX_SW_RST_SZ 1
++#define GPIO_SW_RST_MSK 0x00000800
++#define GPIO_SW_RST_I_MSK 0xfffff7ff
++#define GPIO_SW_RST_SFT 11
++#define GPIO_SW_RST_HI 11
++#define GPIO_SW_RST_SZ 1
++#define US0TMR_SW_RST_MSK 0x00001000
++#define US0TMR_SW_RST_I_MSK 0xffffefff
++#define US0TMR_SW_RST_SFT 12
++#define US0TMR_SW_RST_HI 12
++#define US0TMR_SW_RST_SZ 1
++#define US1TMR_SW_RST_MSK 0x00002000
++#define US1TMR_SW_RST_I_MSK 0xffffdfff
++#define US1TMR_SW_RST_SFT 13
++#define US1TMR_SW_RST_HI 13
++#define US1TMR_SW_RST_SZ 1
++#define US2TMR_SW_RST_MSK 0x00004000
++#define US2TMR_SW_RST_I_MSK 0xffffbfff
++#define US2TMR_SW_RST_SFT 14
++#define US2TMR_SW_RST_HI 14
++#define US2TMR_SW_RST_SZ 1
++#define US3TMR_SW_RST_MSK 0x00008000
++#define US3TMR_SW_RST_I_MSK 0xffff7fff
++#define US3TMR_SW_RST_SFT 15
++#define US3TMR_SW_RST_HI 15
++#define US3TMR_SW_RST_SZ 1
++#define MS0TMR_SW_RST_MSK 0x00010000
++#define MS0TMR_SW_RST_I_MSK 0xfffeffff
++#define MS0TMR_SW_RST_SFT 16
++#define MS0TMR_SW_RST_HI 16
++#define MS0TMR_SW_RST_SZ 1
++#define MS1TMR_SW_RST_MSK 0x00020000
++#define MS1TMR_SW_RST_I_MSK 0xfffdffff
++#define MS1TMR_SW_RST_SFT 17
++#define MS1TMR_SW_RST_HI 17
++#define MS1TMR_SW_RST_SZ 1
++#define MS2TMR_SW_RST_MSK 0x00040000
++#define MS2TMR_SW_RST_I_MSK 0xfffbffff
++#define MS2TMR_SW_RST_SFT 18
++#define MS2TMR_SW_RST_HI 18
++#define MS2TMR_SW_RST_SZ 1
++#define MS3TMR_SW_RST_MSK 0x00080000
++#define MS3TMR_SW_RST_I_MSK 0xfff7ffff
++#define MS3TMR_SW_RST_SFT 19
++#define MS3TMR_SW_RST_HI 19
++#define MS3TMR_SW_RST_SZ 1
++#define RF_BB_SW_RST_MSK 0x00100000
++#define RF_BB_SW_RST_I_MSK 0xffefffff
++#define RF_BB_SW_RST_SFT 20
++#define RF_BB_SW_RST_HI 20
++#define RF_BB_SW_RST_SZ 1
++#define SYS_ALL_RST_MSK 0x00200000
++#define SYS_ALL_RST_I_MSK 0xffdfffff
++#define SYS_ALL_RST_SFT 21
++#define SYS_ALL_RST_HI 21
++#define SYS_ALL_RST_SZ 1
++#define DAT_UART_SW_RST_MSK 0x00400000
++#define DAT_UART_SW_RST_I_MSK 0xffbfffff
++#define DAT_UART_SW_RST_SFT 22
++#define DAT_UART_SW_RST_HI 22
++#define DAT_UART_SW_RST_SZ 1
++#define I2C_MST_SW_RST_MSK 0x00800000
++#define I2C_MST_SW_RST_I_MSK 0xff7fffff
++#define I2C_MST_SW_RST_SFT 23
++#define I2C_MST_SW_RST_HI 23
++#define I2C_MST_SW_RST_SZ 1
++#define RG_REBOOT_MSK 0x00000001
++#define RG_REBOOT_I_MSK 0xfffffffe
++#define RG_REBOOT_SFT 0
++#define RG_REBOOT_HI 0
++#define RG_REBOOT_SZ 1
++#define TRAP_IMG_FLS_MSK 0x00010000
++#define TRAP_IMG_FLS_I_MSK 0xfffeffff
++#define TRAP_IMG_FLS_SFT 16
++#define TRAP_IMG_FLS_HI 16
++#define TRAP_IMG_FLS_SZ 1
++#define TRAP_REBOOT_MSK 0x00020000
++#define TRAP_REBOOT_I_MSK 0xfffdffff
++#define TRAP_REBOOT_SFT 17
++#define TRAP_REBOOT_HI 17
++#define TRAP_REBOOT_SZ 1
++#define TRAP_BOOT_FLS_MSK 0x00040000
++#define TRAP_BOOT_FLS_I_MSK 0xfffbffff
++#define TRAP_BOOT_FLS_SFT 18
++#define TRAP_BOOT_FLS_HI 18
++#define TRAP_BOOT_FLS_SZ 1
++#define CHIP_ID_31_0_MSK 0xffffffff
++#define CHIP_ID_31_0_I_MSK 0x00000000
++#define CHIP_ID_31_0_SFT 0
++#define CHIP_ID_31_0_HI 31
++#define CHIP_ID_31_0_SZ 32
++#define CHIP_ID_63_32_MSK 0xffffffff
++#define CHIP_ID_63_32_I_MSK 0x00000000
++#define CHIP_ID_63_32_SFT 0
++#define CHIP_ID_63_32_HI 31
++#define CHIP_ID_63_32_SZ 32
++#define CHIP_ID_95_64_MSK 0xffffffff
++#define CHIP_ID_95_64_I_MSK 0x00000000
++#define CHIP_ID_95_64_SFT 0
++#define CHIP_ID_95_64_HI 31
++#define CHIP_ID_95_64_SZ 32
++#define CHIP_ID_127_96_MSK 0xffffffff
++#define CHIP_ID_127_96_I_MSK 0x00000000
++#define CHIP_ID_127_96_SFT 0
++#define CHIP_ID_127_96_HI 31
++#define CHIP_ID_127_96_SZ 32
++#define CK_SEL_1_0_MSK 0x00000003
++#define CK_SEL_1_0_I_MSK 0xfffffffc
++#define CK_SEL_1_0_SFT 0
++#define CK_SEL_1_0_HI 1
++#define CK_SEL_1_0_SZ 2
++#define CK_SEL_2_MSK 0x00000004
++#define CK_SEL_2_I_MSK 0xfffffffb
++#define CK_SEL_2_SFT 2
++#define CK_SEL_2_HI 2
++#define CK_SEL_2_SZ 1
++#define SYS_CLK_EN_MSK 0x00000001
++#define SYS_CLK_EN_I_MSK 0xfffffffe
++#define SYS_CLK_EN_SFT 0
++#define SYS_CLK_EN_HI 0
++#define SYS_CLK_EN_SZ 1
++#define MAC_CLK_EN_MSK 0x00000002
++#define MAC_CLK_EN_I_MSK 0xfffffffd
++#define MAC_CLK_EN_SFT 1
++#define MAC_CLK_EN_HI 1
++#define MAC_CLK_EN_SZ 1
++#define MCU_CLK_EN_MSK 0x00000004
++#define MCU_CLK_EN_I_MSK 0xfffffffb
++#define MCU_CLK_EN_SFT 2
++#define MCU_CLK_EN_HI 2
++#define MCU_CLK_EN_SZ 1
++#define SDIO_CLK_EN_MSK 0x00000008
++#define SDIO_CLK_EN_I_MSK 0xfffffff7
++#define SDIO_CLK_EN_SFT 3
++#define SDIO_CLK_EN_HI 3
++#define SDIO_CLK_EN_SZ 1
++#define SPI_SLV_CLK_EN_MSK 0x00000010
++#define SPI_SLV_CLK_EN_I_MSK 0xffffffef
++#define SPI_SLV_CLK_EN_SFT 4
++#define SPI_SLV_CLK_EN_HI 4
++#define SPI_SLV_CLK_EN_SZ 1
++#define UART_CLK_EN_MSK 0x00000020
++#define UART_CLK_EN_I_MSK 0xffffffdf
++#define UART_CLK_EN_SFT 5
++#define UART_CLK_EN_HI 5
++#define UART_CLK_EN_SZ 1
++#define DMA_CLK_EN_MSK 0x00000040
++#define DMA_CLK_EN_I_MSK 0xffffffbf
++#define DMA_CLK_EN_SFT 6
++#define DMA_CLK_EN_HI 6
++#define DMA_CLK_EN_SZ 1
++#define WDT_CLK_EN_MSK 0x00000080
++#define WDT_CLK_EN_I_MSK 0xffffff7f
++#define WDT_CLK_EN_SFT 7
++#define WDT_CLK_EN_HI 7
++#define WDT_CLK_EN_SZ 1
++#define I2C_SLV_CLK_EN_MSK 0x00000100
++#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff
++#define I2C_SLV_CLK_EN_SFT 8
++#define I2C_SLV_CLK_EN_HI 8
++#define I2C_SLV_CLK_EN_SZ 1
++#define INT_CTL_CLK_EN_MSK 0x00000200
++#define INT_CTL_CLK_EN_I_MSK 0xfffffdff
++#define INT_CTL_CLK_EN_SFT 9
++#define INT_CTL_CLK_EN_HI 9
++#define INT_CTL_CLK_EN_SZ 1
++#define BTCX_CLK_EN_MSK 0x00000400
++#define BTCX_CLK_EN_I_MSK 0xfffffbff
++#define BTCX_CLK_EN_SFT 10
++#define BTCX_CLK_EN_HI 10
++#define BTCX_CLK_EN_SZ 1
++#define GPIO_CLK_EN_MSK 0x00000800
++#define GPIO_CLK_EN_I_MSK 0xfffff7ff
++#define GPIO_CLK_EN_SFT 11
++#define GPIO_CLK_EN_HI 11
++#define GPIO_CLK_EN_SZ 1
++#define US0TMR_CLK_EN_MSK 0x00001000
++#define US0TMR_CLK_EN_I_MSK 0xffffefff
++#define US0TMR_CLK_EN_SFT 12
++#define US0TMR_CLK_EN_HI 12
++#define US0TMR_CLK_EN_SZ 1
++#define US1TMR_CLK_EN_MSK 0x00002000
++#define US1TMR_CLK_EN_I_MSK 0xffffdfff
++#define US1TMR_CLK_EN_SFT 13
++#define US1TMR_CLK_EN_HI 13
++#define US1TMR_CLK_EN_SZ 1
++#define US2TMR_CLK_EN_MSK 0x00004000
++#define US2TMR_CLK_EN_I_MSK 0xffffbfff
++#define US2TMR_CLK_EN_SFT 14
++#define US2TMR_CLK_EN_HI 14
++#define US2TMR_CLK_EN_SZ 1
++#define US3TMR_CLK_EN_MSK 0x00008000
++#define US3TMR_CLK_EN_I_MSK 0xffff7fff
++#define US3TMR_CLK_EN_SFT 15
++#define US3TMR_CLK_EN_HI 15
++#define US3TMR_CLK_EN_SZ 1
++#define MS0TMR_CLK_EN_MSK 0x00010000
++#define MS0TMR_CLK_EN_I_MSK 0xfffeffff
++#define MS0TMR_CLK_EN_SFT 16
++#define MS0TMR_CLK_EN_HI 16
++#define MS0TMR_CLK_EN_SZ 1
++#define MS1TMR_CLK_EN_MSK 0x00020000
++#define MS1TMR_CLK_EN_I_MSK 0xfffdffff
++#define MS1TMR_CLK_EN_SFT 17
++#define MS1TMR_CLK_EN_HI 17
++#define MS1TMR_CLK_EN_SZ 1
++#define MS2TMR_CLK_EN_MSK 0x00040000
++#define MS2TMR_CLK_EN_I_MSK 0xfffbffff
++#define MS2TMR_CLK_EN_SFT 18
++#define MS2TMR_CLK_EN_HI 18
++#define MS2TMR_CLK_EN_SZ 1
++#define MS3TMR_CLK_EN_MSK 0x00080000
++#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff
++#define MS3TMR_CLK_EN_SFT 19
++#define MS3TMR_CLK_EN_HI 19
++#define MS3TMR_CLK_EN_SZ 1
++#define BIST_CLK_EN_MSK 0x00100000
++#define BIST_CLK_EN_I_MSK 0xffefffff
++#define BIST_CLK_EN_SFT 20
++#define BIST_CLK_EN_HI 20
++#define BIST_CLK_EN_SZ 1
++#define I2C_MST_CLK_EN_MSK 0x00800000
++#define I2C_MST_CLK_EN_I_MSK 0xff7fffff
++#define I2C_MST_CLK_EN_SFT 23
++#define I2C_MST_CLK_EN_HI 23
++#define I2C_MST_CLK_EN_SZ 1
++#define BTCX_CSR_CLK_EN_MSK 0x00000400
++#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff
++#define BTCX_CSR_CLK_EN_SFT 10
++#define BTCX_CSR_CLK_EN_HI 10
++#define BTCX_CSR_CLK_EN_SZ 1
++#define MCU_DBG_SEL_MSK 0x0000003f
++#define MCU_DBG_SEL_I_MSK 0xffffffc0
++#define MCU_DBG_SEL_SFT 0
++#define MCU_DBG_SEL_HI 5
++#define MCU_DBG_SEL_SZ 6
++#define MCU_STOP_NOGRANT_MSK 0x00000100
++#define MCU_STOP_NOGRANT_I_MSK 0xfffffeff
++#define MCU_STOP_NOGRANT_SFT 8
++#define MCU_STOP_NOGRANT_HI 8
++#define MCU_STOP_NOGRANT_SZ 1
++#define MCU_STOP_ANYTIME_MSK 0x00000200
++#define MCU_STOP_ANYTIME_I_MSK 0xfffffdff
++#define MCU_STOP_ANYTIME_SFT 9
++#define MCU_STOP_ANYTIME_HI 9
++#define MCU_STOP_ANYTIME_SZ 1
++#define MCU_DBG_DATA_MSK 0xffffffff
++#define MCU_DBG_DATA_I_MSK 0x00000000
++#define MCU_DBG_DATA_SFT 0
++#define MCU_DBG_DATA_HI 31
++#define MCU_DBG_DATA_SZ 32
++#define AHB_SW_RST_MSK 0x00000001
++#define AHB_SW_RST_I_MSK 0xfffffffe
++#define AHB_SW_RST_SFT 0
++#define AHB_SW_RST_HI 0
++#define AHB_SW_RST_SZ 1
++#define AHB_ERR_RST_MSK 0x00000002
++#define AHB_ERR_RST_I_MSK 0xfffffffd
++#define AHB_ERR_RST_SFT 1
++#define AHB_ERR_RST_HI 1
++#define AHB_ERR_RST_SZ 1
++#define REG_AHB_DEBUG_MX_MSK 0x00000030
++#define REG_AHB_DEBUG_MX_I_MSK 0xffffffcf
++#define REG_AHB_DEBUG_MX_SFT 4
++#define REG_AHB_DEBUG_MX_HI 5
++#define REG_AHB_DEBUG_MX_SZ 2
++#define REG_PKT_W_NBRT_MSK 0x00000100
++#define REG_PKT_W_NBRT_I_MSK 0xfffffeff
++#define REG_PKT_W_NBRT_SFT 8
++#define REG_PKT_W_NBRT_HI 8
++#define REG_PKT_W_NBRT_SZ 1
++#define REG_PKT_R_NBRT_MSK 0x00000200
++#define REG_PKT_R_NBRT_I_MSK 0xfffffdff
++#define REG_PKT_R_NBRT_SFT 9
++#define REG_PKT_R_NBRT_HI 9
++#define REG_PKT_R_NBRT_SZ 1
++#define IQ_SRAM_SEL_0_MSK 0x00001000
++#define IQ_SRAM_SEL_0_I_MSK 0xffffefff
++#define IQ_SRAM_SEL_0_SFT 12
++#define IQ_SRAM_SEL_0_HI 12
++#define IQ_SRAM_SEL_0_SZ 1
++#define IQ_SRAM_SEL_1_MSK 0x00002000
++#define IQ_SRAM_SEL_1_I_MSK 0xffffdfff
++#define IQ_SRAM_SEL_1_SFT 13
++#define IQ_SRAM_SEL_1_HI 13
++#define IQ_SRAM_SEL_1_SZ 1
++#define IQ_SRAM_SEL_2_MSK 0x00004000
++#define IQ_SRAM_SEL_2_I_MSK 0xffffbfff
++#define IQ_SRAM_SEL_2_SFT 14
++#define IQ_SRAM_SEL_2_HI 14
++#define IQ_SRAM_SEL_2_SZ 1
++#define AHB_STATUS_MSK 0xffff0000
++#define AHB_STATUS_I_MSK 0x0000ffff
++#define AHB_STATUS_SFT 16
++#define AHB_STATUS_HI 31
++#define AHB_STATUS_SZ 16
++#define PARALLEL_DR_MSK 0x00000001
++#define PARALLEL_DR_I_MSK 0xfffffffe
++#define PARALLEL_DR_SFT 0
++#define PARALLEL_DR_HI 0
++#define PARALLEL_DR_SZ 1
++#define MBRUN_MSK 0x00000010
++#define MBRUN_I_MSK 0xffffffef
++#define MBRUN_SFT 4
++#define MBRUN_HI 4
++#define MBRUN_SZ 1
++#define SHIFT_DR_MSK 0x00000100
++#define SHIFT_DR_I_MSK 0xfffffeff
++#define SHIFT_DR_SFT 8
++#define SHIFT_DR_HI 8
++#define SHIFT_DR_SZ 1
++#define MODE_REG_SI_MSK 0x00000200
++#define MODE_REG_SI_I_MSK 0xfffffdff
++#define MODE_REG_SI_SFT 9
++#define MODE_REG_SI_HI 9
++#define MODE_REG_SI_SZ 1
++#define SIMULATION_MODE_MSK 0x00000400
++#define SIMULATION_MODE_I_MSK 0xfffffbff
++#define SIMULATION_MODE_SFT 10
++#define SIMULATION_MODE_HI 10
++#define SIMULATION_MODE_SZ 1
++#define DBIST_MODE_MSK 0x00000800
++#define DBIST_MODE_I_MSK 0xfffff7ff
++#define DBIST_MODE_SFT 11
++#define DBIST_MODE_HI 11
++#define DBIST_MODE_SZ 1
++#define MODE_REG_IN_MSK 0x001fffff
++#define MODE_REG_IN_I_MSK 0xffe00000
++#define MODE_REG_IN_SFT 0
++#define MODE_REG_IN_HI 20
++#define MODE_REG_IN_SZ 21
++#define MODE_REG_OUT_MCU_MSK 0x001fffff
++#define MODE_REG_OUT_MCU_I_MSK 0xffe00000
++#define MODE_REG_OUT_MCU_SFT 0
++#define MODE_REG_OUT_MCU_HI 20
++#define MODE_REG_OUT_MCU_SZ 21
++#define MODE_REG_SO_MCU_MSK 0x80000000
++#define MODE_REG_SO_MCU_I_MSK 0x7fffffff
++#define MODE_REG_SO_MCU_SFT 31
++#define MODE_REG_SO_MCU_HI 31
++#define MODE_REG_SO_MCU_SZ 1
++#define MONITOR_BUS_MCU_31_0_MSK 0xffffffff
++#define MONITOR_BUS_MCU_31_0_I_MSK 0x00000000
++#define MONITOR_BUS_MCU_31_0_SFT 0
++#define MONITOR_BUS_MCU_31_0_HI 31
++#define MONITOR_BUS_MCU_31_0_SZ 32
++#define MONITOR_BUS_MCU_33_32_MSK 0x00000003
++#define MONITOR_BUS_MCU_33_32_I_MSK 0xfffffffc
++#define MONITOR_BUS_MCU_33_32_SFT 0
++#define MONITOR_BUS_MCU_33_32_HI 1
++#define MONITOR_BUS_MCU_33_32_SZ 2
++#define TB_ADR_SEL_MSK 0x0000ffff
++#define TB_ADR_SEL_I_MSK 0xffff0000
++#define TB_ADR_SEL_SFT 0
++#define TB_ADR_SEL_HI 15
++#define TB_ADR_SEL_SZ 16
++#define TB_CS_MSK 0x80000000
++#define TB_CS_I_MSK 0x7fffffff
++#define TB_CS_SFT 31
++#define TB_CS_HI 31
++#define TB_CS_SZ 1
++#define TB_RDATA_MSK 0xffffffff
++#define TB_RDATA_I_MSK 0x00000000
++#define TB_RDATA_SFT 0
++#define TB_RDATA_HI 31
++#define TB_RDATA_SZ 32
++#define UART_W2B_EN_MSK 0x00000001
++#define UART_W2B_EN_I_MSK 0xfffffffe
++#define UART_W2B_EN_SFT 0
++#define UART_W2B_EN_HI 0
++#define UART_W2B_EN_SZ 1
++#define DATA_UART_W2B_EN_MSK 0x00000010
++#define DATA_UART_W2B_EN_I_MSK 0xffffffef
++#define DATA_UART_W2B_EN_SFT 4
++#define DATA_UART_W2B_EN_HI 4
++#define DATA_UART_W2B_EN_SZ 1
++#define AHB_ILL_ADDR_MSK 0xffffffff
++#define AHB_ILL_ADDR_I_MSK 0x00000000
++#define AHB_ILL_ADDR_SFT 0
++#define AHB_ILL_ADDR_HI 31
++#define AHB_ILL_ADDR_SZ 32
++#define AHB_FEN_ADDR_MSK 0xffffffff
++#define AHB_FEN_ADDR_I_MSK 0x00000000
++#define AHB_FEN_ADDR_SFT 0
++#define AHB_FEN_ADDR_HI 31
++#define AHB_FEN_ADDR_SZ 32
++#define ILL_ADDR_CLR_MSK 0x00000001
++#define ILL_ADDR_CLR_I_MSK 0xfffffffe
++#define ILL_ADDR_CLR_SFT 0
++#define ILL_ADDR_CLR_HI 0
++#define ILL_ADDR_CLR_SZ 1
++#define FENCE_HIT_CLR_MSK 0x00000002
++#define FENCE_HIT_CLR_I_MSK 0xfffffffd
++#define FENCE_HIT_CLR_SFT 1
++#define FENCE_HIT_CLR_HI 1
++#define FENCE_HIT_CLR_SZ 1
++#define ILL_ADDR_INT_MSK 0x00000010
++#define ILL_ADDR_INT_I_MSK 0xffffffef
++#define ILL_ADDR_INT_SFT 4
++#define ILL_ADDR_INT_HI 4
++#define ILL_ADDR_INT_SZ 1
++#define FENCE_HIT_INT_MSK 0x00000020
++#define FENCE_HIT_INT_I_MSK 0xffffffdf
++#define FENCE_HIT_INT_SFT 5
++#define FENCE_HIT_INT_HI 5
++#define FENCE_HIT_INT_SZ 1
++#define PWM_INI_VALUE_P_A_MSK 0x000000ff
++#define PWM_INI_VALUE_P_A_I_MSK 0xffffff00
++#define PWM_INI_VALUE_P_A_SFT 0
++#define PWM_INI_VALUE_P_A_HI 7
++#define PWM_INI_VALUE_P_A_SZ 8
++#define PWM_INI_VALUE_N_A_MSK 0x0000ff00
++#define PWM_INI_VALUE_N_A_I_MSK 0xffff00ff
++#define PWM_INI_VALUE_N_A_SFT 8
++#define PWM_INI_VALUE_N_A_HI 15
++#define PWM_INI_VALUE_N_A_SZ 8
++#define PWM_POST_SCALER_A_MSK 0x000f0000
++#define PWM_POST_SCALER_A_I_MSK 0xfff0ffff
++#define PWM_POST_SCALER_A_SFT 16
++#define PWM_POST_SCALER_A_HI 19
++#define PWM_POST_SCALER_A_SZ 4
++#define PWM_ALWAYSON_A_MSK 0x20000000
++#define PWM_ALWAYSON_A_I_MSK 0xdfffffff
++#define PWM_ALWAYSON_A_SFT 29
++#define PWM_ALWAYSON_A_HI 29
++#define PWM_ALWAYSON_A_SZ 1
++#define PWM_INVERT_A_MSK 0x40000000
++#define PWM_INVERT_A_I_MSK 0xbfffffff
++#define PWM_INVERT_A_SFT 30
++#define PWM_INVERT_A_HI 30
++#define PWM_INVERT_A_SZ 1
++#define PWM_ENABLE_A_MSK 0x80000000
++#define PWM_ENABLE_A_I_MSK 0x7fffffff
++#define PWM_ENABLE_A_SFT 31
++#define PWM_ENABLE_A_HI 31
++#define PWM_ENABLE_A_SZ 1
++#define PWM_INI_VALUE_P_B_MSK 0x000000ff
++#define PWM_INI_VALUE_P_B_I_MSK 0xffffff00
++#define PWM_INI_VALUE_P_B_SFT 0
++#define PWM_INI_VALUE_P_B_HI 7
++#define PWM_INI_VALUE_P_B_SZ 8
++#define PWM_INI_VALUE_N_B_MSK 0x0000ff00
++#define PWM_INI_VALUE_N_B_I_MSK 0xffff00ff
++#define PWM_INI_VALUE_N_B_SFT 8
++#define PWM_INI_VALUE_N_B_HI 15
++#define PWM_INI_VALUE_N_B_SZ 8
++#define PWM_POST_SCALER_B_MSK 0x000f0000
++#define PWM_POST_SCALER_B_I_MSK 0xfff0ffff
++#define PWM_POST_SCALER_B_SFT 16
++#define PWM_POST_SCALER_B_HI 19
++#define PWM_POST_SCALER_B_SZ 4
++#define PWM_ALWAYSON_B_MSK 0x20000000
++#define PWM_ALWAYSON_B_I_MSK 0xdfffffff
++#define PWM_ALWAYSON_B_SFT 29
++#define PWM_ALWAYSON_B_HI 29
++#define PWM_ALWAYSON_B_SZ 1
++#define PWM_INVERT_B_MSK 0x40000000
++#define PWM_INVERT_B_I_MSK 0xbfffffff
++#define PWM_INVERT_B_SFT 30
++#define PWM_INVERT_B_HI 30
++#define PWM_INVERT_B_SZ 1
++#define PWM_ENABLE_B_MSK 0x80000000
++#define PWM_ENABLE_B_I_MSK 0x7fffffff
++#define PWM_ENABLE_B_SFT 31
++#define PWM_ENABLE_B_HI 31
++#define PWM_ENABLE_B_SZ 1
++#define HBUSREQ_LOCK_MSK 0x00001fff
++#define HBUSREQ_LOCK_I_MSK 0xffffe000
++#define HBUSREQ_LOCK_SFT 0
++#define HBUSREQ_LOCK_HI 12
++#define HBUSREQ_LOCK_SZ 13
++#define HBURST_LOCK_MSK 0x00001fff
++#define HBURST_LOCK_I_MSK 0xffffe000
++#define HBURST_LOCK_SFT 0
++#define HBURST_LOCK_HI 12
++#define HBURST_LOCK_SZ 13
++#define PRESCALER_USTIMER_MSK 0x000001ff
++#define PRESCALER_USTIMER_I_MSK 0xfffffe00
++#define PRESCALER_USTIMER_SFT 0
++#define PRESCALER_USTIMER_HI 8
++#define PRESCALER_USTIMER_SZ 9
++#define MODE_REG_IN_MMU_MSK 0x0000ffff
++#define MODE_REG_IN_MMU_I_MSK 0xffff0000
++#define MODE_REG_IN_MMU_SFT 0
++#define MODE_REG_IN_MMU_HI 15
++#define MODE_REG_IN_MMU_SZ 16
++#define MODE_REG_OUT_MMU_MSK 0x0000ffff
++#define MODE_REG_OUT_MMU_I_MSK 0xffff0000
++#define MODE_REG_OUT_MMU_SFT 0
++#define MODE_REG_OUT_MMU_HI 15
++#define MODE_REG_OUT_MMU_SZ 16
++#define MODE_REG_SO_MMU_MSK 0x80000000
++#define MODE_REG_SO_MMU_I_MSK 0x7fffffff
++#define MODE_REG_SO_MMU_SFT 31
++#define MODE_REG_SO_MMU_HI 31
++#define MODE_REG_SO_MMU_SZ 1
++#define MONITOR_BUS_MMU_MSK 0x0007ffff
++#define MONITOR_BUS_MMU_I_MSK 0xfff80000
++#define MONITOR_BUS_MMU_SFT 0
++#define MONITOR_BUS_MMU_HI 18
++#define MONITOR_BUS_MMU_SZ 19
++#define TEST_MODE0_MSK 0x00000001
++#define TEST_MODE0_I_MSK 0xfffffffe
++#define TEST_MODE0_SFT 0
++#define TEST_MODE0_HI 0
++#define TEST_MODE0_SZ 1
++#define TEST_MODE1_MSK 0x00000002
++#define TEST_MODE1_I_MSK 0xfffffffd
++#define TEST_MODE1_SFT 1
++#define TEST_MODE1_HI 1
++#define TEST_MODE1_SZ 1
++#define TEST_MODE2_MSK 0x00000004
++#define TEST_MODE2_I_MSK 0xfffffffb
++#define TEST_MODE2_SFT 2
++#define TEST_MODE2_HI 2
++#define TEST_MODE2_SZ 1
++#define TEST_MODE3_MSK 0x00000008
++#define TEST_MODE3_I_MSK 0xfffffff7
++#define TEST_MODE3_SFT 3
++#define TEST_MODE3_HI 3
++#define TEST_MODE3_SZ 1
++#define TEST_MODE4_MSK 0x00000010
++#define TEST_MODE4_I_MSK 0xffffffef
++#define TEST_MODE4_SFT 4
++#define TEST_MODE4_HI 4
++#define TEST_MODE4_SZ 1
++#define TEST_MODE_ALL_MSK 0x00000020
++#define TEST_MODE_ALL_I_MSK 0xffffffdf
++#define TEST_MODE_ALL_SFT 5
++#define TEST_MODE_ALL_HI 5
++#define TEST_MODE_ALL_SZ 1
++#define WDT_INIT_MSK 0x00000001
++#define WDT_INIT_I_MSK 0xfffffffe
++#define WDT_INIT_SFT 0
++#define WDT_INIT_HI 0
++#define WDT_INIT_SZ 1
++#define SD_HOST_INIT_MSK 0x00000002
++#define SD_HOST_INIT_I_MSK 0xfffffffd
++#define SD_HOST_INIT_SFT 1
++#define SD_HOST_INIT_HI 1
++#define SD_HOST_INIT_SZ 1
++#define ALLOW_SD_RESET_MSK 0x00000001
++#define ALLOW_SD_RESET_I_MSK 0xfffffffe
++#define ALLOW_SD_RESET_SFT 0
++#define ALLOW_SD_RESET_HI 0
++#define ALLOW_SD_RESET_SZ 1
++#define UART_NRTS_MSK 0x00000001
++#define UART_NRTS_I_MSK 0xfffffffe
++#define UART_NRTS_SFT 0
++#define UART_NRTS_HI 0
++#define UART_NRTS_SZ 1
++#define UART_NCTS_MSK 0x00000002
++#define UART_NCTS_I_MSK 0xfffffffd
++#define UART_NCTS_SFT 1
++#define UART_NCTS_HI 1
++#define UART_NCTS_SZ 1
++#define TU0_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU0_TM_INIT_VALUE_SFT 0
++#define TU0_TM_INIT_VALUE_HI 15
++#define TU0_TM_INIT_VALUE_SZ 16
++#define TU0_TM_MODE_MSK 0x00010000
++#define TU0_TM_MODE_I_MSK 0xfffeffff
++#define TU0_TM_MODE_SFT 16
++#define TU0_TM_MODE_HI 16
++#define TU0_TM_MODE_SZ 1
++#define TU0_TM_INT_STS_DONE_MSK 0x00020000
++#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU0_TM_INT_STS_DONE_SFT 17
++#define TU0_TM_INT_STS_DONE_HI 17
++#define TU0_TM_INT_STS_DONE_SZ 1
++#define TU0_TM_INT_MASK_MSK 0x00040000
++#define TU0_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU0_TM_INT_MASK_SFT 18
++#define TU0_TM_INT_MASK_HI 18
++#define TU0_TM_INT_MASK_SZ 1
++#define TU0_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU0_TM_CUR_VALUE_SFT 0
++#define TU0_TM_CUR_VALUE_HI 15
++#define TU0_TM_CUR_VALUE_SZ 16
++#define TU1_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU1_TM_INIT_VALUE_SFT 0
++#define TU1_TM_INIT_VALUE_HI 15
++#define TU1_TM_INIT_VALUE_SZ 16
++#define TU1_TM_MODE_MSK 0x00010000
++#define TU1_TM_MODE_I_MSK 0xfffeffff
++#define TU1_TM_MODE_SFT 16
++#define TU1_TM_MODE_HI 16
++#define TU1_TM_MODE_SZ 1
++#define TU1_TM_INT_STS_DONE_MSK 0x00020000
++#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU1_TM_INT_STS_DONE_SFT 17
++#define TU1_TM_INT_STS_DONE_HI 17
++#define TU1_TM_INT_STS_DONE_SZ 1
++#define TU1_TM_INT_MASK_MSK 0x00040000
++#define TU1_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU1_TM_INT_MASK_SFT 18
++#define TU1_TM_INT_MASK_HI 18
++#define TU1_TM_INT_MASK_SZ 1
++#define TU1_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU1_TM_CUR_VALUE_SFT 0
++#define TU1_TM_CUR_VALUE_HI 15
++#define TU1_TM_CUR_VALUE_SZ 16
++#define TU2_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU2_TM_INIT_VALUE_SFT 0
++#define TU2_TM_INIT_VALUE_HI 15
++#define TU2_TM_INIT_VALUE_SZ 16
++#define TU2_TM_MODE_MSK 0x00010000
++#define TU2_TM_MODE_I_MSK 0xfffeffff
++#define TU2_TM_MODE_SFT 16
++#define TU2_TM_MODE_HI 16
++#define TU2_TM_MODE_SZ 1
++#define TU2_TM_INT_STS_DONE_MSK 0x00020000
++#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU2_TM_INT_STS_DONE_SFT 17
++#define TU2_TM_INT_STS_DONE_HI 17
++#define TU2_TM_INT_STS_DONE_SZ 1
++#define TU2_TM_INT_MASK_MSK 0x00040000
++#define TU2_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU2_TM_INT_MASK_SFT 18
++#define TU2_TM_INT_MASK_HI 18
++#define TU2_TM_INT_MASK_SZ 1
++#define TU2_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU2_TM_CUR_VALUE_SFT 0
++#define TU2_TM_CUR_VALUE_HI 15
++#define TU2_TM_CUR_VALUE_SZ 16
++#define TU3_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU3_TM_INIT_VALUE_SFT 0
++#define TU3_TM_INIT_VALUE_HI 15
++#define TU3_TM_INIT_VALUE_SZ 16
++#define TU3_TM_MODE_MSK 0x00010000
++#define TU3_TM_MODE_I_MSK 0xfffeffff
++#define TU3_TM_MODE_SFT 16
++#define TU3_TM_MODE_HI 16
++#define TU3_TM_MODE_SZ 1
++#define TU3_TM_INT_STS_DONE_MSK 0x00020000
++#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU3_TM_INT_STS_DONE_SFT 17
++#define TU3_TM_INT_STS_DONE_HI 17
++#define TU3_TM_INT_STS_DONE_SZ 1
++#define TU3_TM_INT_MASK_MSK 0x00040000
++#define TU3_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU3_TM_INT_MASK_SFT 18
++#define TU3_TM_INT_MASK_HI 18
++#define TU3_TM_INT_MASK_SZ 1
++#define TU3_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU3_TM_CUR_VALUE_SFT 0
++#define TU3_TM_CUR_VALUE_HI 15
++#define TU3_TM_CUR_VALUE_SZ 16
++#define TM0_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM0_TM_INIT_VALUE_SFT 0
++#define TM0_TM_INIT_VALUE_HI 15
++#define TM0_TM_INIT_VALUE_SZ 16
++#define TM0_TM_MODE_MSK 0x00010000
++#define TM0_TM_MODE_I_MSK 0xfffeffff
++#define TM0_TM_MODE_SFT 16
++#define TM0_TM_MODE_HI 16
++#define TM0_TM_MODE_SZ 1
++#define TM0_TM_INT_STS_DONE_MSK 0x00020000
++#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM0_TM_INT_STS_DONE_SFT 17
++#define TM0_TM_INT_STS_DONE_HI 17
++#define TM0_TM_INT_STS_DONE_SZ 1
++#define TM0_TM_INT_MASK_MSK 0x00040000
++#define TM0_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM0_TM_INT_MASK_SFT 18
++#define TM0_TM_INT_MASK_HI 18
++#define TM0_TM_INT_MASK_SZ 1
++#define TM0_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM0_TM_CUR_VALUE_SFT 0
++#define TM0_TM_CUR_VALUE_HI 15
++#define TM0_TM_CUR_VALUE_SZ 16
++#define TM1_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM1_TM_INIT_VALUE_SFT 0
++#define TM1_TM_INIT_VALUE_HI 15
++#define TM1_TM_INIT_VALUE_SZ 16
++#define TM1_TM_MODE_MSK 0x00010000
++#define TM1_TM_MODE_I_MSK 0xfffeffff
++#define TM1_TM_MODE_SFT 16
++#define TM1_TM_MODE_HI 16
++#define TM1_TM_MODE_SZ 1
++#define TM1_TM_INT_STS_DONE_MSK 0x00020000
++#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM1_TM_INT_STS_DONE_SFT 17
++#define TM1_TM_INT_STS_DONE_HI 17
++#define TM1_TM_INT_STS_DONE_SZ 1
++#define TM1_TM_INT_MASK_MSK 0x00040000
++#define TM1_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM1_TM_INT_MASK_SFT 18
++#define TM1_TM_INT_MASK_HI 18
++#define TM1_TM_INT_MASK_SZ 1
++#define TM1_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM1_TM_CUR_VALUE_SFT 0
++#define TM1_TM_CUR_VALUE_HI 15
++#define TM1_TM_CUR_VALUE_SZ 16
++#define TM2_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM2_TM_INIT_VALUE_SFT 0
++#define TM2_TM_INIT_VALUE_HI 15
++#define TM2_TM_INIT_VALUE_SZ 16
++#define TM2_TM_MODE_MSK 0x00010000
++#define TM2_TM_MODE_I_MSK 0xfffeffff
++#define TM2_TM_MODE_SFT 16
++#define TM2_TM_MODE_HI 16
++#define TM2_TM_MODE_SZ 1
++#define TM2_TM_INT_STS_DONE_MSK 0x00020000
++#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM2_TM_INT_STS_DONE_SFT 17
++#define TM2_TM_INT_STS_DONE_HI 17
++#define TM2_TM_INT_STS_DONE_SZ 1
++#define TM2_TM_INT_MASK_MSK 0x00040000
++#define TM2_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM2_TM_INT_MASK_SFT 18
++#define TM2_TM_INT_MASK_HI 18
++#define TM2_TM_INT_MASK_SZ 1
++#define TM2_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM2_TM_CUR_VALUE_SFT 0
++#define TM2_TM_CUR_VALUE_HI 15
++#define TM2_TM_CUR_VALUE_SZ 16
++#define TM3_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM3_TM_INIT_VALUE_SFT 0
++#define TM3_TM_INIT_VALUE_HI 15
++#define TM3_TM_INIT_VALUE_SZ 16
++#define TM3_TM_MODE_MSK 0x00010000
++#define TM3_TM_MODE_I_MSK 0xfffeffff
++#define TM3_TM_MODE_SFT 16
++#define TM3_TM_MODE_HI 16
++#define TM3_TM_MODE_SZ 1
++#define TM3_TM_INT_STS_DONE_MSK 0x00020000
++#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM3_TM_INT_STS_DONE_SFT 17
++#define TM3_TM_INT_STS_DONE_HI 17
++#define TM3_TM_INT_STS_DONE_SZ 1
++#define TM3_TM_INT_MASK_MSK 0x00040000
++#define TM3_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM3_TM_INT_MASK_SFT 18
++#define TM3_TM_INT_MASK_HI 18
++#define TM3_TM_INT_MASK_SZ 1
++#define TM3_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM3_TM_CUR_VALUE_SFT 0
++#define TM3_TM_CUR_VALUE_HI 15
++#define TM3_TM_CUR_VALUE_SZ 16
++#define MCU_WDT_TIME_CNT_MSK 0x0000ffff
++#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000
++#define MCU_WDT_TIME_CNT_SFT 0
++#define MCU_WDT_TIME_CNT_HI 15
++#define MCU_WDT_TIME_CNT_SZ 16
++#define MCU_WDT_STATUS_MSK 0x00020000
++#define MCU_WDT_STATUS_I_MSK 0xfffdffff
++#define MCU_WDT_STATUS_SFT 17
++#define MCU_WDT_STATUS_HI 17
++#define MCU_WDT_STATUS_SZ 1
++#define MCU_WDOG_ENA_MSK 0x80000000
++#define MCU_WDOG_ENA_I_MSK 0x7fffffff
++#define MCU_WDOG_ENA_SFT 31
++#define MCU_WDOG_ENA_HI 31
++#define MCU_WDOG_ENA_SZ 1
++#define SYS_WDT_TIME_CNT_MSK 0x0000ffff
++#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000
++#define SYS_WDT_TIME_CNT_SFT 0
++#define SYS_WDT_TIME_CNT_HI 15
++#define SYS_WDT_TIME_CNT_SZ 16
++#define SYS_WDT_STATUS_MSK 0x00020000
++#define SYS_WDT_STATUS_I_MSK 0xfffdffff
++#define SYS_WDT_STATUS_SFT 17
++#define SYS_WDT_STATUS_HI 17
++#define SYS_WDT_STATUS_SZ 1
++#define SYS_WDOG_ENA_MSK 0x80000000
++#define SYS_WDOG_ENA_I_MSK 0x7fffffff
++#define SYS_WDOG_ENA_SFT 31
++#define SYS_WDOG_ENA_HI 31
++#define SYS_WDOG_ENA_SZ 1
++#define XLNA_EN_O_OE_MSK 0x00000001
++#define XLNA_EN_O_OE_I_MSK 0xfffffffe
++#define XLNA_EN_O_OE_SFT 0
++#define XLNA_EN_O_OE_HI 0
++#define XLNA_EN_O_OE_SZ 1
++#define XLNA_EN_O_PE_MSK 0x00000002
++#define XLNA_EN_O_PE_I_MSK 0xfffffffd
++#define XLNA_EN_O_PE_SFT 1
++#define XLNA_EN_O_PE_HI 1
++#define XLNA_EN_O_PE_SZ 1
++#define PAD6_IE_MSK 0x00000008
++#define PAD6_IE_I_MSK 0xfffffff7
++#define PAD6_IE_SFT 3
++#define PAD6_IE_HI 3
++#define PAD6_IE_SZ 1
++#define PAD6_SEL_I_MSK 0x00000030
++#define PAD6_SEL_I_I_MSK 0xffffffcf
++#define PAD6_SEL_I_SFT 4
++#define PAD6_SEL_I_HI 5
++#define PAD6_SEL_I_SZ 2
++#define PAD6_OD_MSK 0x00000100
++#define PAD6_OD_I_MSK 0xfffffeff
++#define PAD6_OD_SFT 8
++#define PAD6_OD_HI 8
++#define PAD6_OD_SZ 1
++#define PAD6_SEL_O_MSK 0x00001000
++#define PAD6_SEL_O_I_MSK 0xffffefff
++#define PAD6_SEL_O_SFT 12
++#define PAD6_SEL_O_HI 12
++#define PAD6_SEL_O_SZ 1
++#define XLNA_EN_O_C_MSK 0x10000000
++#define XLNA_EN_O_C_I_MSK 0xefffffff
++#define XLNA_EN_O_C_SFT 28
++#define XLNA_EN_O_C_HI 28
++#define XLNA_EN_O_C_SZ 1
++#define WIFI_TX_SW_O_OE_MSK 0x00000001
++#define WIFI_TX_SW_O_OE_I_MSK 0xfffffffe
++#define WIFI_TX_SW_O_OE_SFT 0
++#define WIFI_TX_SW_O_OE_HI 0
++#define WIFI_TX_SW_O_OE_SZ 1
++#define WIFI_TX_SW_O_PE_MSK 0x00000002
++#define WIFI_TX_SW_O_PE_I_MSK 0xfffffffd
++#define WIFI_TX_SW_O_PE_SFT 1
++#define WIFI_TX_SW_O_PE_HI 1
++#define WIFI_TX_SW_O_PE_SZ 1
++#define PAD7_IE_MSK 0x00000008
++#define PAD7_IE_I_MSK 0xfffffff7
++#define PAD7_IE_SFT 3
++#define PAD7_IE_HI 3
++#define PAD7_IE_SZ 1
++#define PAD7_SEL_I_MSK 0x00000030
++#define PAD7_SEL_I_I_MSK 0xffffffcf
++#define PAD7_SEL_I_SFT 4
++#define PAD7_SEL_I_HI 5
++#define PAD7_SEL_I_SZ 2
++#define PAD7_OD_MSK 0x00000100
++#define PAD7_OD_I_MSK 0xfffffeff
++#define PAD7_OD_SFT 8
++#define PAD7_OD_HI 8
++#define PAD7_OD_SZ 1
++#define PAD7_SEL_O_MSK 0x00001000
++#define PAD7_SEL_O_I_MSK 0xffffefff
++#define PAD7_SEL_O_SFT 12
++#define PAD7_SEL_O_HI 12
++#define PAD7_SEL_O_SZ 1
++#define WIFI_TX_SW_O_C_MSK 0x10000000
++#define WIFI_TX_SW_O_C_I_MSK 0xefffffff
++#define WIFI_TX_SW_O_C_SFT 28
++#define WIFI_TX_SW_O_C_HI 28
++#define WIFI_TX_SW_O_C_SZ 1
++#define WIFI_RX_SW_O_OE_MSK 0x00000001
++#define WIFI_RX_SW_O_OE_I_MSK 0xfffffffe
++#define WIFI_RX_SW_O_OE_SFT 0
++#define WIFI_RX_SW_O_OE_HI 0
++#define WIFI_RX_SW_O_OE_SZ 1
++#define WIFI_RX_SW_O_PE_MSK 0x00000002
++#define WIFI_RX_SW_O_PE_I_MSK 0xfffffffd
++#define WIFI_RX_SW_O_PE_SFT 1
++#define WIFI_RX_SW_O_PE_HI 1
++#define WIFI_RX_SW_O_PE_SZ 1
++#define PAD8_IE_MSK 0x00000008
++#define PAD8_IE_I_MSK 0xfffffff7
++#define PAD8_IE_SFT 3
++#define PAD8_IE_HI 3
++#define PAD8_IE_SZ 1
++#define PAD8_SEL_I_MSK 0x00000030
++#define PAD8_SEL_I_I_MSK 0xffffffcf
++#define PAD8_SEL_I_SFT 4
++#define PAD8_SEL_I_HI 5
++#define PAD8_SEL_I_SZ 2
++#define PAD8_OD_MSK 0x00000100
++#define PAD8_OD_I_MSK 0xfffffeff
++#define PAD8_OD_SFT 8
++#define PAD8_OD_HI 8
++#define PAD8_OD_SZ 1
++#define WIFI_RX_SW_O_C_MSK 0x10000000
++#define WIFI_RX_SW_O_C_I_MSK 0xefffffff
++#define WIFI_RX_SW_O_C_SFT 28
++#define WIFI_RX_SW_O_C_HI 28
++#define WIFI_RX_SW_O_C_SZ 1
++#define BT_SW_O_OE_MSK 0x00000001
++#define BT_SW_O_OE_I_MSK 0xfffffffe
++#define BT_SW_O_OE_SFT 0
++#define BT_SW_O_OE_HI 0
++#define BT_SW_O_OE_SZ 1
++#define BT_SW_O_PE_MSK 0x00000002
++#define BT_SW_O_PE_I_MSK 0xfffffffd
++#define BT_SW_O_PE_SFT 1
++#define BT_SW_O_PE_HI 1
++#define BT_SW_O_PE_SZ 1
++#define PAD9_IE_MSK 0x00000008
++#define PAD9_IE_I_MSK 0xfffffff7
++#define PAD9_IE_SFT 3
++#define PAD9_IE_HI 3
++#define PAD9_IE_SZ 1
++#define PAD9_SEL_I_MSK 0x00000030
++#define PAD9_SEL_I_I_MSK 0xffffffcf
++#define PAD9_SEL_I_SFT 4
++#define PAD9_SEL_I_HI 5
++#define PAD9_SEL_I_SZ 2
++#define PAD9_OD_MSK 0x00000100
++#define PAD9_OD_I_MSK 0xfffffeff
++#define PAD9_OD_SFT 8
++#define PAD9_OD_HI 8
++#define PAD9_OD_SZ 1
++#define PAD9_SEL_O_MSK 0x00001000
++#define PAD9_SEL_O_I_MSK 0xffffefff
++#define PAD9_SEL_O_SFT 12
++#define PAD9_SEL_O_HI 12
++#define PAD9_SEL_O_SZ 1
++#define BT_SW_O_C_MSK 0x10000000
++#define BT_SW_O_C_I_MSK 0xefffffff
++#define BT_SW_O_C_SFT 28
++#define BT_SW_O_C_HI 28
++#define BT_SW_O_C_SZ 1
++#define XPA_EN_O_OE_MSK 0x00000001
++#define XPA_EN_O_OE_I_MSK 0xfffffffe
++#define XPA_EN_O_OE_SFT 0
++#define XPA_EN_O_OE_HI 0
++#define XPA_EN_O_OE_SZ 1
++#define XPA_EN_O_PE_MSK 0x00000002
++#define XPA_EN_O_PE_I_MSK 0xfffffffd
++#define XPA_EN_O_PE_SFT 1
++#define XPA_EN_O_PE_HI 1
++#define XPA_EN_O_PE_SZ 1
++#define PAD11_IE_MSK 0x00000008
++#define PAD11_IE_I_MSK 0xfffffff7
++#define PAD11_IE_SFT 3
++#define PAD11_IE_HI 3
++#define PAD11_IE_SZ 1
++#define PAD11_SEL_I_MSK 0x00000030
++#define PAD11_SEL_I_I_MSK 0xffffffcf
++#define PAD11_SEL_I_SFT 4
++#define PAD11_SEL_I_HI 5
++#define PAD11_SEL_I_SZ 2
++#define PAD11_OD_MSK 0x00000100
++#define PAD11_OD_I_MSK 0xfffffeff
++#define PAD11_OD_SFT 8
++#define PAD11_OD_HI 8
++#define PAD11_OD_SZ 1
++#define PAD11_SEL_O_MSK 0x00001000
++#define PAD11_SEL_O_I_MSK 0xffffefff
++#define PAD11_SEL_O_SFT 12
++#define PAD11_SEL_O_HI 12
++#define PAD11_SEL_O_SZ 1
++#define XPA_EN_O_C_MSK 0x10000000
++#define XPA_EN_O_C_I_MSK 0xefffffff
++#define XPA_EN_O_C_SFT 28
++#define XPA_EN_O_C_HI 28
++#define XPA_EN_O_C_SZ 1
++#define PAD15_OE_MSK 0x00000001
++#define PAD15_OE_I_MSK 0xfffffffe
++#define PAD15_OE_SFT 0
++#define PAD15_OE_HI 0
++#define PAD15_OE_SZ 1
++#define PAD15_PE_MSK 0x00000002
++#define PAD15_PE_I_MSK 0xfffffffd
++#define PAD15_PE_SFT 1
++#define PAD15_PE_HI 1
++#define PAD15_PE_SZ 1
++#define PAD15_DS_MSK 0x00000004
++#define PAD15_DS_I_MSK 0xfffffffb
++#define PAD15_DS_SFT 2
++#define PAD15_DS_HI 2
++#define PAD15_DS_SZ 1
++#define PAD15_IE_MSK 0x00000008
++#define PAD15_IE_I_MSK 0xfffffff7
++#define PAD15_IE_SFT 3
++#define PAD15_IE_HI 3
++#define PAD15_IE_SZ 1
++#define PAD15_SEL_I_MSK 0x00000030
++#define PAD15_SEL_I_I_MSK 0xffffffcf
++#define PAD15_SEL_I_SFT 4
++#define PAD15_SEL_I_HI 5
++#define PAD15_SEL_I_SZ 2
++#define PAD15_OD_MSK 0x00000100
++#define PAD15_OD_I_MSK 0xfffffeff
++#define PAD15_OD_SFT 8
++#define PAD15_OD_HI 8
++#define PAD15_OD_SZ 1
++#define PAD15_SEL_O_MSK 0x00001000
++#define PAD15_SEL_O_I_MSK 0xffffefff
++#define PAD15_SEL_O_SFT 12
++#define PAD15_SEL_O_HI 12
++#define PAD15_SEL_O_SZ 1
++#define TEST_1_ID_MSK 0x10000000
++#define TEST_1_ID_I_MSK 0xefffffff
++#define TEST_1_ID_SFT 28
++#define TEST_1_ID_HI 28
++#define TEST_1_ID_SZ 1
++#define PAD16_OE_MSK 0x00000001
++#define PAD16_OE_I_MSK 0xfffffffe
++#define PAD16_OE_SFT 0
++#define PAD16_OE_HI 0
++#define PAD16_OE_SZ 1
++#define PAD16_PE_MSK 0x00000002
++#define PAD16_PE_I_MSK 0xfffffffd
++#define PAD16_PE_SFT 1
++#define PAD16_PE_HI 1
++#define PAD16_PE_SZ 1
++#define PAD16_DS_MSK 0x00000004
++#define PAD16_DS_I_MSK 0xfffffffb
++#define PAD16_DS_SFT 2
++#define PAD16_DS_HI 2
++#define PAD16_DS_SZ 1
++#define PAD16_IE_MSK 0x00000008
++#define PAD16_IE_I_MSK 0xfffffff7
++#define PAD16_IE_SFT 3
++#define PAD16_IE_HI 3
++#define PAD16_IE_SZ 1
++#define PAD16_SEL_I_MSK 0x00000030
++#define PAD16_SEL_I_I_MSK 0xffffffcf
++#define PAD16_SEL_I_SFT 4
++#define PAD16_SEL_I_HI 5
++#define PAD16_SEL_I_SZ 2
++#define PAD16_OD_MSK 0x00000100
++#define PAD16_OD_I_MSK 0xfffffeff
++#define PAD16_OD_SFT 8
++#define PAD16_OD_HI 8
++#define PAD16_OD_SZ 1
++#define PAD16_SEL_O_MSK 0x00001000
++#define PAD16_SEL_O_I_MSK 0xffffefff
++#define PAD16_SEL_O_SFT 12
++#define PAD16_SEL_O_HI 12
++#define PAD16_SEL_O_SZ 1
++#define TEST_2_ID_MSK 0x10000000
++#define TEST_2_ID_I_MSK 0xefffffff
++#define TEST_2_ID_SFT 28
++#define TEST_2_ID_HI 28
++#define TEST_2_ID_SZ 1
++#define PAD17_OE_MSK 0x00000001
++#define PAD17_OE_I_MSK 0xfffffffe
++#define PAD17_OE_SFT 0
++#define PAD17_OE_HI 0
++#define PAD17_OE_SZ 1
++#define PAD17_PE_MSK 0x00000002
++#define PAD17_PE_I_MSK 0xfffffffd
++#define PAD17_PE_SFT 1
++#define PAD17_PE_HI 1
++#define PAD17_PE_SZ 1
++#define PAD17_DS_MSK 0x00000004
++#define PAD17_DS_I_MSK 0xfffffffb
++#define PAD17_DS_SFT 2
++#define PAD17_DS_HI 2
++#define PAD17_DS_SZ 1
++#define PAD17_IE_MSK 0x00000008
++#define PAD17_IE_I_MSK 0xfffffff7
++#define PAD17_IE_SFT 3
++#define PAD17_IE_HI 3
++#define PAD17_IE_SZ 1
++#define PAD17_SEL_I_MSK 0x00000030
++#define PAD17_SEL_I_I_MSK 0xffffffcf
++#define PAD17_SEL_I_SFT 4
++#define PAD17_SEL_I_HI 5
++#define PAD17_SEL_I_SZ 2
++#define PAD17_OD_MSK 0x00000100
++#define PAD17_OD_I_MSK 0xfffffeff
++#define PAD17_OD_SFT 8
++#define PAD17_OD_HI 8
++#define PAD17_OD_SZ 1
++#define PAD17_SEL_O_MSK 0x00001000
++#define PAD17_SEL_O_I_MSK 0xffffefff
++#define PAD17_SEL_O_SFT 12
++#define PAD17_SEL_O_HI 12
++#define PAD17_SEL_O_SZ 1
++#define TEST_3_ID_MSK 0x10000000
++#define TEST_3_ID_I_MSK 0xefffffff
++#define TEST_3_ID_SFT 28
++#define TEST_3_ID_HI 28
++#define TEST_3_ID_SZ 1
++#define PAD18_OE_MSK 0x00000001
++#define PAD18_OE_I_MSK 0xfffffffe
++#define PAD18_OE_SFT 0
++#define PAD18_OE_HI 0
++#define PAD18_OE_SZ 1
++#define PAD18_PE_MSK 0x00000002
++#define PAD18_PE_I_MSK 0xfffffffd
++#define PAD18_PE_SFT 1
++#define PAD18_PE_HI 1
++#define PAD18_PE_SZ 1
++#define PAD18_DS_MSK 0x00000004
++#define PAD18_DS_I_MSK 0xfffffffb
++#define PAD18_DS_SFT 2
++#define PAD18_DS_HI 2
++#define PAD18_DS_SZ 1
++#define PAD18_IE_MSK 0x00000008
++#define PAD18_IE_I_MSK 0xfffffff7
++#define PAD18_IE_SFT 3
++#define PAD18_IE_HI 3
++#define PAD18_IE_SZ 1
++#define PAD18_SEL_I_MSK 0x00000030
++#define PAD18_SEL_I_I_MSK 0xffffffcf
++#define PAD18_SEL_I_SFT 4
++#define PAD18_SEL_I_HI 5
++#define PAD18_SEL_I_SZ 2
++#define PAD18_OD_MSK 0x00000100
++#define PAD18_OD_I_MSK 0xfffffeff
++#define PAD18_OD_SFT 8
++#define PAD18_OD_HI 8
++#define PAD18_OD_SZ 1
++#define PAD18_SEL_O_MSK 0x00003000
++#define PAD18_SEL_O_I_MSK 0xffffcfff
++#define PAD18_SEL_O_SFT 12
++#define PAD18_SEL_O_HI 13
++#define PAD18_SEL_O_SZ 2
++#define TEST_4_ID_MSK 0x10000000
++#define TEST_4_ID_I_MSK 0xefffffff
++#define TEST_4_ID_SFT 28
++#define TEST_4_ID_HI 28
++#define TEST_4_ID_SZ 1
++#define PAD19_OE_MSK 0x00000001
++#define PAD19_OE_I_MSK 0xfffffffe
++#define PAD19_OE_SFT 0
++#define PAD19_OE_HI 0
++#define PAD19_OE_SZ 1
++#define PAD19_PE_MSK 0x00000002
++#define PAD19_PE_I_MSK 0xfffffffd
++#define PAD19_PE_SFT 1
++#define PAD19_PE_HI 1
++#define PAD19_PE_SZ 1
++#define PAD19_DS_MSK 0x00000004
++#define PAD19_DS_I_MSK 0xfffffffb
++#define PAD19_DS_SFT 2
++#define PAD19_DS_HI 2
++#define PAD19_DS_SZ 1
++#define PAD19_IE_MSK 0x00000008
++#define PAD19_IE_I_MSK 0xfffffff7
++#define PAD19_IE_SFT 3
++#define PAD19_IE_HI 3
++#define PAD19_IE_SZ 1
++#define PAD19_SEL_I_MSK 0x00000030
++#define PAD19_SEL_I_I_MSK 0xffffffcf
++#define PAD19_SEL_I_SFT 4
++#define PAD19_SEL_I_HI 5
++#define PAD19_SEL_I_SZ 2
++#define PAD19_OD_MSK 0x00000100
++#define PAD19_OD_I_MSK 0xfffffeff
++#define PAD19_OD_SFT 8
++#define PAD19_OD_HI 8
++#define PAD19_OD_SZ 1
++#define PAD19_SEL_O_MSK 0x00007000
++#define PAD19_SEL_O_I_MSK 0xffff8fff
++#define PAD19_SEL_O_SFT 12
++#define PAD19_SEL_O_HI 14
++#define PAD19_SEL_O_SZ 3
++#define SHORT_TO_20_ID_MSK 0x10000000
++#define SHORT_TO_20_ID_I_MSK 0xefffffff
++#define SHORT_TO_20_ID_SFT 28
++#define SHORT_TO_20_ID_HI 28
++#define SHORT_TO_20_ID_SZ 1
++#define PAD20_OE_MSK 0x00000001
++#define PAD20_OE_I_MSK 0xfffffffe
++#define PAD20_OE_SFT 0
++#define PAD20_OE_HI 0
++#define PAD20_OE_SZ 1
++#define PAD20_PE_MSK 0x00000002
++#define PAD20_PE_I_MSK 0xfffffffd
++#define PAD20_PE_SFT 1
++#define PAD20_PE_HI 1
++#define PAD20_PE_SZ 1
++#define PAD20_DS_MSK 0x00000004
++#define PAD20_DS_I_MSK 0xfffffffb
++#define PAD20_DS_SFT 2
++#define PAD20_DS_HI 2
++#define PAD20_DS_SZ 1
++#define PAD20_IE_MSK 0x00000008
++#define PAD20_IE_I_MSK 0xfffffff7
++#define PAD20_IE_SFT 3
++#define PAD20_IE_HI 3
++#define PAD20_IE_SZ 1
++#define PAD20_SEL_I_MSK 0x000000f0
++#define PAD20_SEL_I_I_MSK 0xffffff0f
++#define PAD20_SEL_I_SFT 4
++#define PAD20_SEL_I_HI 7
++#define PAD20_SEL_I_SZ 4
++#define PAD20_OD_MSK 0x00000100
++#define PAD20_OD_I_MSK 0xfffffeff
++#define PAD20_OD_SFT 8
++#define PAD20_OD_HI 8
++#define PAD20_OD_SZ 1
++#define PAD20_SEL_O_MSK 0x00003000
++#define PAD20_SEL_O_I_MSK 0xffffcfff
++#define PAD20_SEL_O_SFT 12
++#define PAD20_SEL_O_HI 13
++#define PAD20_SEL_O_SZ 2
++#define STRAP0_MSK 0x08000000
++#define STRAP0_I_MSK 0xf7ffffff
++#define STRAP0_SFT 27
++#define STRAP0_HI 27
++#define STRAP0_SZ 1
++#define GPIO_TEST_1_ID_MSK 0x10000000
++#define GPIO_TEST_1_ID_I_MSK 0xefffffff
++#define GPIO_TEST_1_ID_SFT 28
++#define GPIO_TEST_1_ID_HI 28
++#define GPIO_TEST_1_ID_SZ 1
++#define PAD21_OE_MSK 0x00000001
++#define PAD21_OE_I_MSK 0xfffffffe
++#define PAD21_OE_SFT 0
++#define PAD21_OE_HI 0
++#define PAD21_OE_SZ 1
++#define PAD21_PE_MSK 0x00000002
++#define PAD21_PE_I_MSK 0xfffffffd
++#define PAD21_PE_SFT 1
++#define PAD21_PE_HI 1
++#define PAD21_PE_SZ 1
++#define PAD21_DS_MSK 0x00000004
++#define PAD21_DS_I_MSK 0xfffffffb
++#define PAD21_DS_SFT 2
++#define PAD21_DS_HI 2
++#define PAD21_DS_SZ 1
++#define PAD21_IE_MSK 0x00000008
++#define PAD21_IE_I_MSK 0xfffffff7
++#define PAD21_IE_SFT 3
++#define PAD21_IE_HI 3
++#define PAD21_IE_SZ 1
++#define PAD21_SEL_I_MSK 0x00000070
++#define PAD21_SEL_I_I_MSK 0xffffff8f
++#define PAD21_SEL_I_SFT 4
++#define PAD21_SEL_I_HI 6
++#define PAD21_SEL_I_SZ 3
++#define PAD21_OD_MSK 0x00000100
++#define PAD21_OD_I_MSK 0xfffffeff
++#define PAD21_OD_SFT 8
++#define PAD21_OD_HI 8
++#define PAD21_OD_SZ 1
++#define PAD21_SEL_O_MSK 0x00003000
++#define PAD21_SEL_O_I_MSK 0xffffcfff
++#define PAD21_SEL_O_SFT 12
++#define PAD21_SEL_O_HI 13
++#define PAD21_SEL_O_SZ 2
++#define STRAP3_MSK 0x08000000
++#define STRAP3_I_MSK 0xf7ffffff
++#define STRAP3_SFT 27
++#define STRAP3_HI 27
++#define STRAP3_SZ 1
++#define GPIO_TEST_2_ID_MSK 0x10000000
++#define GPIO_TEST_2_ID_I_MSK 0xefffffff
++#define GPIO_TEST_2_ID_SFT 28
++#define GPIO_TEST_2_ID_HI 28
++#define GPIO_TEST_2_ID_SZ 1
++#define PAD22_OE_MSK 0x00000001
++#define PAD22_OE_I_MSK 0xfffffffe
++#define PAD22_OE_SFT 0
++#define PAD22_OE_HI 0
++#define PAD22_OE_SZ 1
++#define PAD22_PE_MSK 0x00000002
++#define PAD22_PE_I_MSK 0xfffffffd
++#define PAD22_PE_SFT 1
++#define PAD22_PE_HI 1
++#define PAD22_PE_SZ 1
++#define PAD22_DS_MSK 0x00000004
++#define PAD22_DS_I_MSK 0xfffffffb
++#define PAD22_DS_SFT 2
++#define PAD22_DS_HI 2
++#define PAD22_DS_SZ 1
++#define PAD22_IE_MSK 0x00000008
++#define PAD22_IE_I_MSK 0xfffffff7
++#define PAD22_IE_SFT 3
++#define PAD22_IE_HI 3
++#define PAD22_IE_SZ 1
++#define PAD22_SEL_I_MSK 0x00000070
++#define PAD22_SEL_I_I_MSK 0xffffff8f
++#define PAD22_SEL_I_SFT 4
++#define PAD22_SEL_I_HI 6
++#define PAD22_SEL_I_SZ 3
++#define PAD22_OD_MSK 0x00000100
++#define PAD22_OD_I_MSK 0xfffffeff
++#define PAD22_OD_SFT 8
++#define PAD22_OD_HI 8
++#define PAD22_OD_SZ 1
++#define PAD22_SEL_O_MSK 0x00007000
++#define PAD22_SEL_O_I_MSK 0xffff8fff
++#define PAD22_SEL_O_SFT 12
++#define PAD22_SEL_O_HI 14
++#define PAD22_SEL_O_SZ 3
++#define PAD22_SEL_OE_MSK 0x00100000
++#define PAD22_SEL_OE_I_MSK 0xffefffff
++#define PAD22_SEL_OE_SFT 20
++#define PAD22_SEL_OE_HI 20
++#define PAD22_SEL_OE_SZ 1
++#define GPIO_TEST_3_ID_MSK 0x10000000
++#define GPIO_TEST_3_ID_I_MSK 0xefffffff
++#define GPIO_TEST_3_ID_SFT 28
++#define GPIO_TEST_3_ID_HI 28
++#define GPIO_TEST_3_ID_SZ 1
++#define PAD24_OE_MSK 0x00000001
++#define PAD24_OE_I_MSK 0xfffffffe
++#define PAD24_OE_SFT 0
++#define PAD24_OE_HI 0
++#define PAD24_OE_SZ 1
++#define PAD24_PE_MSK 0x00000002
++#define PAD24_PE_I_MSK 0xfffffffd
++#define PAD24_PE_SFT 1
++#define PAD24_PE_HI 1
++#define PAD24_PE_SZ 1
++#define PAD24_DS_MSK 0x00000004
++#define PAD24_DS_I_MSK 0xfffffffb
++#define PAD24_DS_SFT 2
++#define PAD24_DS_HI 2
++#define PAD24_DS_SZ 1
++#define PAD24_IE_MSK 0x00000008
++#define PAD24_IE_I_MSK 0xfffffff7
++#define PAD24_IE_SFT 3
++#define PAD24_IE_HI 3
++#define PAD24_IE_SZ 1
++#define PAD24_SEL_I_MSK 0x00000030
++#define PAD24_SEL_I_I_MSK 0xffffffcf
++#define PAD24_SEL_I_SFT 4
++#define PAD24_SEL_I_HI 5
++#define PAD24_SEL_I_SZ 2
++#define PAD24_OD_MSK 0x00000100
++#define PAD24_OD_I_MSK 0xfffffeff
++#define PAD24_OD_SFT 8
++#define PAD24_OD_HI 8
++#define PAD24_OD_SZ 1
++#define PAD24_SEL_O_MSK 0x00007000
++#define PAD24_SEL_O_I_MSK 0xffff8fff
++#define PAD24_SEL_O_SFT 12
++#define PAD24_SEL_O_HI 14
++#define PAD24_SEL_O_SZ 3
++#define GPIO_TEST_4_ID_MSK 0x10000000
++#define GPIO_TEST_4_ID_I_MSK 0xefffffff
++#define GPIO_TEST_4_ID_SFT 28
++#define GPIO_TEST_4_ID_HI 28
++#define GPIO_TEST_4_ID_SZ 1
++#define PAD25_OE_MSK 0x00000001
++#define PAD25_OE_I_MSK 0xfffffffe
++#define PAD25_OE_SFT 0
++#define PAD25_OE_HI 0
++#define PAD25_OE_SZ 1
++#define PAD25_PE_MSK 0x00000002
++#define PAD25_PE_I_MSK 0xfffffffd
++#define PAD25_PE_SFT 1
++#define PAD25_PE_HI 1
++#define PAD25_PE_SZ 1
++#define PAD25_DS_MSK 0x00000004
++#define PAD25_DS_I_MSK 0xfffffffb
++#define PAD25_DS_SFT 2
++#define PAD25_DS_HI 2
++#define PAD25_DS_SZ 1
++#define PAD25_IE_MSK 0x00000008
++#define PAD25_IE_I_MSK 0xfffffff7
++#define PAD25_IE_SFT 3
++#define PAD25_IE_HI 3
++#define PAD25_IE_SZ 1
++#define PAD25_SEL_I_MSK 0x00000070
++#define PAD25_SEL_I_I_MSK 0xffffff8f
++#define PAD25_SEL_I_SFT 4
++#define PAD25_SEL_I_HI 6
++#define PAD25_SEL_I_SZ 3
++#define PAD25_OD_MSK 0x00000100
++#define PAD25_OD_I_MSK 0xfffffeff
++#define PAD25_OD_SFT 8
++#define PAD25_OD_HI 8
++#define PAD25_OD_SZ 1
++#define PAD25_SEL_O_MSK 0x00007000
++#define PAD25_SEL_O_I_MSK 0xffff8fff
++#define PAD25_SEL_O_SFT 12
++#define PAD25_SEL_O_HI 14
++#define PAD25_SEL_O_SZ 3
++#define PAD25_SEL_OE_MSK 0x00100000
++#define PAD25_SEL_OE_I_MSK 0xffefffff
++#define PAD25_SEL_OE_SFT 20
++#define PAD25_SEL_OE_HI 20
++#define PAD25_SEL_OE_SZ 1
++#define STRAP1_MSK 0x08000000
++#define STRAP1_I_MSK 0xf7ffffff
++#define STRAP1_SFT 27
++#define STRAP1_HI 27
++#define STRAP1_SZ 1
++#define GPIO_1_ID_MSK 0x10000000
++#define GPIO_1_ID_I_MSK 0xefffffff
++#define GPIO_1_ID_SFT 28
++#define GPIO_1_ID_HI 28
++#define GPIO_1_ID_SZ 1
++#define PAD27_OE_MSK 0x00000001
++#define PAD27_OE_I_MSK 0xfffffffe
++#define PAD27_OE_SFT 0
++#define PAD27_OE_HI 0
++#define PAD27_OE_SZ 1
++#define PAD27_PE_MSK 0x00000002
++#define PAD27_PE_I_MSK 0xfffffffd
++#define PAD27_PE_SFT 1
++#define PAD27_PE_HI 1
++#define PAD27_PE_SZ 1
++#define PAD27_DS_MSK 0x00000004
++#define PAD27_DS_I_MSK 0xfffffffb
++#define PAD27_DS_SFT 2
++#define PAD27_DS_HI 2
++#define PAD27_DS_SZ 1
++#define PAD27_IE_MSK 0x00000008
++#define PAD27_IE_I_MSK 0xfffffff7
++#define PAD27_IE_SFT 3
++#define PAD27_IE_HI 3
++#define PAD27_IE_SZ 1
++#define PAD27_SEL_I_MSK 0x00000070
++#define PAD27_SEL_I_I_MSK 0xffffff8f
++#define PAD27_SEL_I_SFT 4
++#define PAD27_SEL_I_HI 6
++#define PAD27_SEL_I_SZ 3
++#define PAD27_OD_MSK 0x00000100
++#define PAD27_OD_I_MSK 0xfffffeff
++#define PAD27_OD_SFT 8
++#define PAD27_OD_HI 8
++#define PAD27_OD_SZ 1
++#define PAD27_SEL_O_MSK 0x00007000
++#define PAD27_SEL_O_I_MSK 0xffff8fff
++#define PAD27_SEL_O_SFT 12
++#define PAD27_SEL_O_HI 14
++#define PAD27_SEL_O_SZ 3
++#define GPIO_2_ID_MSK 0x10000000
++#define GPIO_2_ID_I_MSK 0xefffffff
++#define GPIO_2_ID_SFT 28
++#define GPIO_2_ID_HI 28
++#define GPIO_2_ID_SZ 1
++#define PAD28_OE_MSK 0x00000001
++#define PAD28_OE_I_MSK 0xfffffffe
++#define PAD28_OE_SFT 0
++#define PAD28_OE_HI 0
++#define PAD28_OE_SZ 1
++#define PAD28_PE_MSK 0x00000002
++#define PAD28_PE_I_MSK 0xfffffffd
++#define PAD28_PE_SFT 1
++#define PAD28_PE_HI 1
++#define PAD28_PE_SZ 1
++#define PAD28_DS_MSK 0x00000004
++#define PAD28_DS_I_MSK 0xfffffffb
++#define PAD28_DS_SFT 2
++#define PAD28_DS_HI 2
++#define PAD28_DS_SZ 1
++#define PAD28_IE_MSK 0x00000008
++#define PAD28_IE_I_MSK 0xfffffff7
++#define PAD28_IE_SFT 3
++#define PAD28_IE_HI 3
++#define PAD28_IE_SZ 1
++#define PAD28_SEL_I_MSK 0x00000070
++#define PAD28_SEL_I_I_MSK 0xffffff8f
++#define PAD28_SEL_I_SFT 4
++#define PAD28_SEL_I_HI 6
++#define PAD28_SEL_I_SZ 3
++#define PAD28_OD_MSK 0x00000100
++#define PAD28_OD_I_MSK 0xfffffeff
++#define PAD28_OD_SFT 8
++#define PAD28_OD_HI 8
++#define PAD28_OD_SZ 1
++#define PAD28_SEL_O_MSK 0x0000f000
++#define PAD28_SEL_O_I_MSK 0xffff0fff
++#define PAD28_SEL_O_SFT 12
++#define PAD28_SEL_O_HI 15
++#define PAD28_SEL_O_SZ 4
++#define PAD28_SEL_OE_MSK 0x00100000
++#define PAD28_SEL_OE_I_MSK 0xffefffff
++#define PAD28_SEL_OE_SFT 20
++#define PAD28_SEL_OE_HI 20
++#define PAD28_SEL_OE_SZ 1
++#define GPIO_3_ID_MSK 0x10000000
++#define GPIO_3_ID_I_MSK 0xefffffff
++#define GPIO_3_ID_SFT 28
++#define GPIO_3_ID_HI 28
++#define GPIO_3_ID_SZ 1
++#define PAD29_OE_MSK 0x00000001
++#define PAD29_OE_I_MSK 0xfffffffe
++#define PAD29_OE_SFT 0
++#define PAD29_OE_HI 0
++#define PAD29_OE_SZ 1
++#define PAD29_PE_MSK 0x00000002
++#define PAD29_PE_I_MSK 0xfffffffd
++#define PAD29_PE_SFT 1
++#define PAD29_PE_HI 1
++#define PAD29_PE_SZ 1
++#define PAD29_DS_MSK 0x00000004
++#define PAD29_DS_I_MSK 0xfffffffb
++#define PAD29_DS_SFT 2
++#define PAD29_DS_HI 2
++#define PAD29_DS_SZ 1
++#define PAD29_IE_MSK 0x00000008
++#define PAD29_IE_I_MSK 0xfffffff7
++#define PAD29_IE_SFT 3
++#define PAD29_IE_HI 3
++#define PAD29_IE_SZ 1
++#define PAD29_SEL_I_MSK 0x00000070
++#define PAD29_SEL_I_I_MSK 0xffffff8f
++#define PAD29_SEL_I_SFT 4
++#define PAD29_SEL_I_HI 6
++#define PAD29_SEL_I_SZ 3
++#define PAD29_OD_MSK 0x00000100
++#define PAD29_OD_I_MSK 0xfffffeff
++#define PAD29_OD_SFT 8
++#define PAD29_OD_HI 8
++#define PAD29_OD_SZ 1
++#define PAD29_SEL_O_MSK 0x00007000
++#define PAD29_SEL_O_I_MSK 0xffff8fff
++#define PAD29_SEL_O_SFT 12
++#define PAD29_SEL_O_HI 14
++#define PAD29_SEL_O_SZ 3
++#define GPIO_TEST_5_ID_MSK 0x10000000
++#define GPIO_TEST_5_ID_I_MSK 0xefffffff
++#define GPIO_TEST_5_ID_SFT 28
++#define GPIO_TEST_5_ID_HI 28
++#define GPIO_TEST_5_ID_SZ 1
++#define PAD30_OE_MSK 0x00000001
++#define PAD30_OE_I_MSK 0xfffffffe
++#define PAD30_OE_SFT 0
++#define PAD30_OE_HI 0
++#define PAD30_OE_SZ 1
++#define PAD30_PE_MSK 0x00000002
++#define PAD30_PE_I_MSK 0xfffffffd
++#define PAD30_PE_SFT 1
++#define PAD30_PE_HI 1
++#define PAD30_PE_SZ 1
++#define PAD30_DS_MSK 0x00000004
++#define PAD30_DS_I_MSK 0xfffffffb
++#define PAD30_DS_SFT 2
++#define PAD30_DS_HI 2
++#define PAD30_DS_SZ 1
++#define PAD30_IE_MSK 0x00000008
++#define PAD30_IE_I_MSK 0xfffffff7
++#define PAD30_IE_SFT 3
++#define PAD30_IE_HI 3
++#define PAD30_IE_SZ 1
++#define PAD30_SEL_I_MSK 0x00000030
++#define PAD30_SEL_I_I_MSK 0xffffffcf
++#define PAD30_SEL_I_SFT 4
++#define PAD30_SEL_I_HI 5
++#define PAD30_SEL_I_SZ 2
++#define PAD30_OD_MSK 0x00000100
++#define PAD30_OD_I_MSK 0xfffffeff
++#define PAD30_OD_SFT 8
++#define PAD30_OD_HI 8
++#define PAD30_OD_SZ 1
++#define PAD30_SEL_O_MSK 0x00003000
++#define PAD30_SEL_O_I_MSK 0xffffcfff
++#define PAD30_SEL_O_SFT 12
++#define PAD30_SEL_O_HI 13
++#define PAD30_SEL_O_SZ 2
++#define TEST_6_ID_MSK 0x10000000
++#define TEST_6_ID_I_MSK 0xefffffff
++#define TEST_6_ID_SFT 28
++#define TEST_6_ID_HI 28
++#define TEST_6_ID_SZ 1
++#define PAD31_OE_MSK 0x00000001
++#define PAD31_OE_I_MSK 0xfffffffe
++#define PAD31_OE_SFT 0
++#define PAD31_OE_HI 0
++#define PAD31_OE_SZ 1
++#define PAD31_PE_MSK 0x00000002
++#define PAD31_PE_I_MSK 0xfffffffd
++#define PAD31_PE_SFT 1
++#define PAD31_PE_HI 1
++#define PAD31_PE_SZ 1
++#define PAD31_DS_MSK 0x00000004
++#define PAD31_DS_I_MSK 0xfffffffb
++#define PAD31_DS_SFT 2
++#define PAD31_DS_HI 2
++#define PAD31_DS_SZ 1
++#define PAD31_IE_MSK 0x00000008
++#define PAD31_IE_I_MSK 0xfffffff7
++#define PAD31_IE_SFT 3
++#define PAD31_IE_HI 3
++#define PAD31_IE_SZ 1
++#define PAD31_SEL_I_MSK 0x00000030
++#define PAD31_SEL_I_I_MSK 0xffffffcf
++#define PAD31_SEL_I_SFT 4
++#define PAD31_SEL_I_HI 5
++#define PAD31_SEL_I_SZ 2
++#define PAD31_OD_MSK 0x00000100
++#define PAD31_OD_I_MSK 0xfffffeff
++#define PAD31_OD_SFT 8
++#define PAD31_OD_HI 8
++#define PAD31_OD_SZ 1
++#define PAD31_SEL_O_MSK 0x00003000
++#define PAD31_SEL_O_I_MSK 0xffffcfff
++#define PAD31_SEL_O_SFT 12
++#define PAD31_SEL_O_HI 13
++#define PAD31_SEL_O_SZ 2
++#define TEST_7_ID_MSK 0x10000000
++#define TEST_7_ID_I_MSK 0xefffffff
++#define TEST_7_ID_SFT 28
++#define TEST_7_ID_HI 28
++#define TEST_7_ID_SZ 1
++#define PAD32_OE_MSK 0x00000001
++#define PAD32_OE_I_MSK 0xfffffffe
++#define PAD32_OE_SFT 0
++#define PAD32_OE_HI 0
++#define PAD32_OE_SZ 1
++#define PAD32_PE_MSK 0x00000002
++#define PAD32_PE_I_MSK 0xfffffffd
++#define PAD32_PE_SFT 1
++#define PAD32_PE_HI 1
++#define PAD32_PE_SZ 1
++#define PAD32_DS_MSK 0x00000004
++#define PAD32_DS_I_MSK 0xfffffffb
++#define PAD32_DS_SFT 2
++#define PAD32_DS_HI 2
++#define PAD32_DS_SZ 1
++#define PAD32_IE_MSK 0x00000008
++#define PAD32_IE_I_MSK 0xfffffff7
++#define PAD32_IE_SFT 3
++#define PAD32_IE_HI 3
++#define PAD32_IE_SZ 1
++#define PAD32_SEL_I_MSK 0x00000030
++#define PAD32_SEL_I_I_MSK 0xffffffcf
++#define PAD32_SEL_I_SFT 4
++#define PAD32_SEL_I_HI 5
++#define PAD32_SEL_I_SZ 2
++#define PAD32_OD_MSK 0x00000100
++#define PAD32_OD_I_MSK 0xfffffeff
++#define PAD32_OD_SFT 8
++#define PAD32_OD_HI 8
++#define PAD32_OD_SZ 1
++#define PAD32_SEL_O_MSK 0x00003000
++#define PAD32_SEL_O_I_MSK 0xffffcfff
++#define PAD32_SEL_O_SFT 12
++#define PAD32_SEL_O_HI 13
++#define PAD32_SEL_O_SZ 2
++#define TEST_8_ID_MSK 0x10000000
++#define TEST_8_ID_I_MSK 0xefffffff
++#define TEST_8_ID_SFT 28
++#define TEST_8_ID_HI 28
++#define TEST_8_ID_SZ 1
++#define PAD33_OE_MSK 0x00000001
++#define PAD33_OE_I_MSK 0xfffffffe
++#define PAD33_OE_SFT 0
++#define PAD33_OE_HI 0
++#define PAD33_OE_SZ 1
++#define PAD33_PE_MSK 0x00000002
++#define PAD33_PE_I_MSK 0xfffffffd
++#define PAD33_PE_SFT 1
++#define PAD33_PE_HI 1
++#define PAD33_PE_SZ 1
++#define PAD33_DS_MSK 0x00000004
++#define PAD33_DS_I_MSK 0xfffffffb
++#define PAD33_DS_SFT 2
++#define PAD33_DS_HI 2
++#define PAD33_DS_SZ 1
++#define PAD33_IE_MSK 0x00000008
++#define PAD33_IE_I_MSK 0xfffffff7
++#define PAD33_IE_SFT 3
++#define PAD33_IE_HI 3
++#define PAD33_IE_SZ 1
++#define PAD33_SEL_I_MSK 0x00000030
++#define PAD33_SEL_I_I_MSK 0xffffffcf
++#define PAD33_SEL_I_SFT 4
++#define PAD33_SEL_I_HI 5
++#define PAD33_SEL_I_SZ 2
++#define PAD33_OD_MSK 0x00000100
++#define PAD33_OD_I_MSK 0xfffffeff
++#define PAD33_OD_SFT 8
++#define PAD33_OD_HI 8
++#define PAD33_OD_SZ 1
++#define PAD33_SEL_O_MSK 0x00003000
++#define PAD33_SEL_O_I_MSK 0xffffcfff
++#define PAD33_SEL_O_SFT 12
++#define PAD33_SEL_O_HI 13
++#define PAD33_SEL_O_SZ 2
++#define TEST_9_ID_MSK 0x10000000
++#define TEST_9_ID_I_MSK 0xefffffff
++#define TEST_9_ID_SFT 28
++#define TEST_9_ID_HI 28
++#define TEST_9_ID_SZ 1
++#define PAD34_OE_MSK 0x00000001
++#define PAD34_OE_I_MSK 0xfffffffe
++#define PAD34_OE_SFT 0
++#define PAD34_OE_HI 0
++#define PAD34_OE_SZ 1
++#define PAD34_PE_MSK 0x00000002
++#define PAD34_PE_I_MSK 0xfffffffd
++#define PAD34_PE_SFT 1
++#define PAD34_PE_HI 1
++#define PAD34_PE_SZ 1
++#define PAD34_DS_MSK 0x00000004
++#define PAD34_DS_I_MSK 0xfffffffb
++#define PAD34_DS_SFT 2
++#define PAD34_DS_HI 2
++#define PAD34_DS_SZ 1
++#define PAD34_IE_MSK 0x00000008
++#define PAD34_IE_I_MSK 0xfffffff7
++#define PAD34_IE_SFT 3
++#define PAD34_IE_HI 3
++#define PAD34_IE_SZ 1
++#define PAD34_SEL_I_MSK 0x00000030
++#define PAD34_SEL_I_I_MSK 0xffffffcf
++#define PAD34_SEL_I_SFT 4
++#define PAD34_SEL_I_HI 5
++#define PAD34_SEL_I_SZ 2
++#define PAD34_OD_MSK 0x00000100
++#define PAD34_OD_I_MSK 0xfffffeff
++#define PAD34_OD_SFT 8
++#define PAD34_OD_HI 8
++#define PAD34_OD_SZ 1
++#define PAD34_SEL_O_MSK 0x00003000
++#define PAD34_SEL_O_I_MSK 0xffffcfff
++#define PAD34_SEL_O_SFT 12
++#define PAD34_SEL_O_HI 13
++#define PAD34_SEL_O_SZ 2
++#define TEST_10_ID_MSK 0x10000000
++#define TEST_10_ID_I_MSK 0xefffffff
++#define TEST_10_ID_SFT 28
++#define TEST_10_ID_HI 28
++#define TEST_10_ID_SZ 1
++#define PAD42_OE_MSK 0x00000001
++#define PAD42_OE_I_MSK 0xfffffffe
++#define PAD42_OE_SFT 0
++#define PAD42_OE_HI 0
++#define PAD42_OE_SZ 1
++#define PAD42_PE_MSK 0x00000002
++#define PAD42_PE_I_MSK 0xfffffffd
++#define PAD42_PE_SFT 1
++#define PAD42_PE_HI 1
++#define PAD42_PE_SZ 1
++#define PAD42_DS_MSK 0x00000004
++#define PAD42_DS_I_MSK 0xfffffffb
++#define PAD42_DS_SFT 2
++#define PAD42_DS_HI 2
++#define PAD42_DS_SZ 1
++#define PAD42_IE_MSK 0x00000008
++#define PAD42_IE_I_MSK 0xfffffff7
++#define PAD42_IE_SFT 3
++#define PAD42_IE_HI 3
++#define PAD42_IE_SZ 1
++#define PAD42_SEL_I_MSK 0x00000030
++#define PAD42_SEL_I_I_MSK 0xffffffcf
++#define PAD42_SEL_I_SFT 4
++#define PAD42_SEL_I_HI 5
++#define PAD42_SEL_I_SZ 2
++#define PAD42_OD_MSK 0x00000100
++#define PAD42_OD_I_MSK 0xfffffeff
++#define PAD42_OD_SFT 8
++#define PAD42_OD_HI 8
++#define PAD42_OD_SZ 1
++#define PAD42_SEL_O_MSK 0x00001000
++#define PAD42_SEL_O_I_MSK 0xffffefff
++#define PAD42_SEL_O_SFT 12
++#define PAD42_SEL_O_HI 12
++#define PAD42_SEL_O_SZ 1
++#define TEST_11_ID_MSK 0x10000000
++#define TEST_11_ID_I_MSK 0xefffffff
++#define TEST_11_ID_SFT 28
++#define TEST_11_ID_HI 28
++#define TEST_11_ID_SZ 1
++#define PAD43_OE_MSK 0x00000001
++#define PAD43_OE_I_MSK 0xfffffffe
++#define PAD43_OE_SFT 0
++#define PAD43_OE_HI 0
++#define PAD43_OE_SZ 1
++#define PAD43_PE_MSK 0x00000002
++#define PAD43_PE_I_MSK 0xfffffffd
++#define PAD43_PE_SFT 1
++#define PAD43_PE_HI 1
++#define PAD43_PE_SZ 1
++#define PAD43_DS_MSK 0x00000004
++#define PAD43_DS_I_MSK 0xfffffffb
++#define PAD43_DS_SFT 2
++#define PAD43_DS_HI 2
++#define PAD43_DS_SZ 1
++#define PAD43_IE_MSK 0x00000008
++#define PAD43_IE_I_MSK 0xfffffff7
++#define PAD43_IE_SFT 3
++#define PAD43_IE_HI 3
++#define PAD43_IE_SZ 1
++#define PAD43_SEL_I_MSK 0x00000030
++#define PAD43_SEL_I_I_MSK 0xffffffcf
++#define PAD43_SEL_I_SFT 4
++#define PAD43_SEL_I_HI 5
++#define PAD43_SEL_I_SZ 2
++#define PAD43_OD_MSK 0x00000100
++#define PAD43_OD_I_MSK 0xfffffeff
++#define PAD43_OD_SFT 8
++#define PAD43_OD_HI 8
++#define PAD43_OD_SZ 1
++#define PAD43_SEL_O_MSK 0x00001000
++#define PAD43_SEL_O_I_MSK 0xffffefff
++#define PAD43_SEL_O_SFT 12
++#define PAD43_SEL_O_HI 12
++#define PAD43_SEL_O_SZ 1
++#define TEST_12_ID_MSK 0x10000000
++#define TEST_12_ID_I_MSK 0xefffffff
++#define TEST_12_ID_SFT 28
++#define TEST_12_ID_HI 28
++#define TEST_12_ID_SZ 1
++#define PAD44_OE_MSK 0x00000001
++#define PAD44_OE_I_MSK 0xfffffffe
++#define PAD44_OE_SFT 0
++#define PAD44_OE_HI 0
++#define PAD44_OE_SZ 1
++#define PAD44_PE_MSK 0x00000002
++#define PAD44_PE_I_MSK 0xfffffffd
++#define PAD44_PE_SFT 1
++#define PAD44_PE_HI 1
++#define PAD44_PE_SZ 1
++#define PAD44_DS_MSK 0x00000004
++#define PAD44_DS_I_MSK 0xfffffffb
++#define PAD44_DS_SFT 2
++#define PAD44_DS_HI 2
++#define PAD44_DS_SZ 1
++#define PAD44_IE_MSK 0x00000008
++#define PAD44_IE_I_MSK 0xfffffff7
++#define PAD44_IE_SFT 3
++#define PAD44_IE_HI 3
++#define PAD44_IE_SZ 1
++#define PAD44_SEL_I_MSK 0x00000030
++#define PAD44_SEL_I_I_MSK 0xffffffcf
++#define PAD44_SEL_I_SFT 4
++#define PAD44_SEL_I_HI 5
++#define PAD44_SEL_I_SZ 2
++#define PAD44_OD_MSK 0x00000100
++#define PAD44_OD_I_MSK 0xfffffeff
++#define PAD44_OD_SFT 8
++#define PAD44_OD_HI 8
++#define PAD44_OD_SZ 1
++#define PAD44_SEL_O_MSK 0x00003000
++#define PAD44_SEL_O_I_MSK 0xffffcfff
++#define PAD44_SEL_O_SFT 12
++#define PAD44_SEL_O_HI 13
++#define PAD44_SEL_O_SZ 2
++#define TEST_13_ID_MSK 0x10000000
++#define TEST_13_ID_I_MSK 0xefffffff
++#define TEST_13_ID_SFT 28
++#define TEST_13_ID_HI 28
++#define TEST_13_ID_SZ 1
++#define PAD45_OE_MSK 0x00000001
++#define PAD45_OE_I_MSK 0xfffffffe
++#define PAD45_OE_SFT 0
++#define PAD45_OE_HI 0
++#define PAD45_OE_SZ 1
++#define PAD45_PE_MSK 0x00000002
++#define PAD45_PE_I_MSK 0xfffffffd
++#define PAD45_PE_SFT 1
++#define PAD45_PE_HI 1
++#define PAD45_PE_SZ 1
++#define PAD45_DS_MSK 0x00000004
++#define PAD45_DS_I_MSK 0xfffffffb
++#define PAD45_DS_SFT 2
++#define PAD45_DS_HI 2
++#define PAD45_DS_SZ 1
++#define PAD45_IE_MSK 0x00000008
++#define PAD45_IE_I_MSK 0xfffffff7
++#define PAD45_IE_SFT 3
++#define PAD45_IE_HI 3
++#define PAD45_IE_SZ 1
++#define PAD45_SEL_I_MSK 0x00000030
++#define PAD45_SEL_I_I_MSK 0xffffffcf
++#define PAD45_SEL_I_SFT 4
++#define PAD45_SEL_I_HI 5
++#define PAD45_SEL_I_SZ 2
++#define PAD45_OD_MSK 0x00000100
++#define PAD45_OD_I_MSK 0xfffffeff
++#define PAD45_OD_SFT 8
++#define PAD45_OD_HI 8
++#define PAD45_OD_SZ 1
++#define PAD45_SEL_O_MSK 0x00003000
++#define PAD45_SEL_O_I_MSK 0xffffcfff
++#define PAD45_SEL_O_SFT 12
++#define PAD45_SEL_O_HI 13
++#define PAD45_SEL_O_SZ 2
++#define TEST_14_ID_MSK 0x10000000
++#define TEST_14_ID_I_MSK 0xefffffff
++#define TEST_14_ID_SFT 28
++#define TEST_14_ID_HI 28
++#define TEST_14_ID_SZ 1
++#define PAD46_OE_MSK 0x00000001
++#define PAD46_OE_I_MSK 0xfffffffe
++#define PAD46_OE_SFT 0
++#define PAD46_OE_HI 0
++#define PAD46_OE_SZ 1
++#define PAD46_PE_MSK 0x00000002
++#define PAD46_PE_I_MSK 0xfffffffd
++#define PAD46_PE_SFT 1
++#define PAD46_PE_HI 1
++#define PAD46_PE_SZ 1
++#define PAD46_DS_MSK 0x00000004
++#define PAD46_DS_I_MSK 0xfffffffb
++#define PAD46_DS_SFT 2
++#define PAD46_DS_HI 2
++#define PAD46_DS_SZ 1
++#define PAD46_IE_MSK 0x00000008
++#define PAD46_IE_I_MSK 0xfffffff7
++#define PAD46_IE_SFT 3
++#define PAD46_IE_HI 3
++#define PAD46_IE_SZ 1
++#define PAD46_SEL_I_MSK 0x00000030
++#define PAD46_SEL_I_I_MSK 0xffffffcf
++#define PAD46_SEL_I_SFT 4
++#define PAD46_SEL_I_HI 5
++#define PAD46_SEL_I_SZ 2
++#define PAD46_OD_MSK 0x00000100
++#define PAD46_OD_I_MSK 0xfffffeff
++#define PAD46_OD_SFT 8
++#define PAD46_OD_HI 8
++#define PAD46_OD_SZ 1
++#define PAD46_SEL_O_MSK 0x00003000
++#define PAD46_SEL_O_I_MSK 0xffffcfff
++#define PAD46_SEL_O_SFT 12
++#define PAD46_SEL_O_HI 13
++#define PAD46_SEL_O_SZ 2
++#define TEST_15_ID_MSK 0x10000000
++#define TEST_15_ID_I_MSK 0xefffffff
++#define TEST_15_ID_SFT 28
++#define TEST_15_ID_HI 28
++#define TEST_15_ID_SZ 1
++#define PAD47_OE_MSK 0x00000001
++#define PAD47_OE_I_MSK 0xfffffffe
++#define PAD47_OE_SFT 0
++#define PAD47_OE_HI 0
++#define PAD47_OE_SZ 1
++#define PAD47_PE_MSK 0x00000002
++#define PAD47_PE_I_MSK 0xfffffffd
++#define PAD47_PE_SFT 1
++#define PAD47_PE_HI 1
++#define PAD47_PE_SZ 1
++#define PAD47_DS_MSK 0x00000004
++#define PAD47_DS_I_MSK 0xfffffffb
++#define PAD47_DS_SFT 2
++#define PAD47_DS_HI 2
++#define PAD47_DS_SZ 1
++#define PAD47_SEL_I_MSK 0x00000030
++#define PAD47_SEL_I_I_MSK 0xffffffcf
++#define PAD47_SEL_I_SFT 4
++#define PAD47_SEL_I_HI 5
++#define PAD47_SEL_I_SZ 2
++#define PAD47_OD_MSK 0x00000100
++#define PAD47_OD_I_MSK 0xfffffeff
++#define PAD47_OD_SFT 8
++#define PAD47_OD_HI 8
++#define PAD47_OD_SZ 1
++#define PAD47_SEL_O_MSK 0x00003000
++#define PAD47_SEL_O_I_MSK 0xffffcfff
++#define PAD47_SEL_O_SFT 12
++#define PAD47_SEL_O_HI 13
++#define PAD47_SEL_O_SZ 2
++#define PAD47_SEL_OE_MSK 0x00100000
++#define PAD47_SEL_OE_I_MSK 0xffefffff
++#define PAD47_SEL_OE_SFT 20
++#define PAD47_SEL_OE_HI 20
++#define PAD47_SEL_OE_SZ 1
++#define GPIO_9_ID_MSK 0x10000000
++#define GPIO_9_ID_I_MSK 0xefffffff
++#define GPIO_9_ID_SFT 28
++#define GPIO_9_ID_HI 28
++#define GPIO_9_ID_SZ 1
++#define PAD48_OE_MSK 0x00000001
++#define PAD48_OE_I_MSK 0xfffffffe
++#define PAD48_OE_SFT 0
++#define PAD48_OE_HI 0
++#define PAD48_OE_SZ 1
++#define PAD48_PE_MSK 0x00000002
++#define PAD48_PE_I_MSK 0xfffffffd
++#define PAD48_PE_SFT 1
++#define PAD48_PE_HI 1
++#define PAD48_PE_SZ 1
++#define PAD48_DS_MSK 0x00000004
++#define PAD48_DS_I_MSK 0xfffffffb
++#define PAD48_DS_SFT 2
++#define PAD48_DS_HI 2
++#define PAD48_DS_SZ 1
++#define PAD48_IE_MSK 0x00000008
++#define PAD48_IE_I_MSK 0xfffffff7
++#define PAD48_IE_SFT 3
++#define PAD48_IE_HI 3
++#define PAD48_IE_SZ 1
++#define PAD48_SEL_I_MSK 0x00000070
++#define PAD48_SEL_I_I_MSK 0xffffff8f
++#define PAD48_SEL_I_SFT 4
++#define PAD48_SEL_I_HI 6
++#define PAD48_SEL_I_SZ 3
++#define PAD48_OD_MSK 0x00000100
++#define PAD48_OD_I_MSK 0xfffffeff
++#define PAD48_OD_SFT 8
++#define PAD48_OD_HI 8
++#define PAD48_OD_SZ 1
++#define PAD48_PE_SEL_MSK 0x00000800
++#define PAD48_PE_SEL_I_MSK 0xfffff7ff
++#define PAD48_PE_SEL_SFT 11
++#define PAD48_PE_SEL_HI 11
++#define PAD48_PE_SEL_SZ 1
++#define PAD48_SEL_O_MSK 0x00003000
++#define PAD48_SEL_O_I_MSK 0xffffcfff
++#define PAD48_SEL_O_SFT 12
++#define PAD48_SEL_O_HI 13
++#define PAD48_SEL_O_SZ 2
++#define PAD48_SEL_OE_MSK 0x00100000
++#define PAD48_SEL_OE_I_MSK 0xffefffff
++#define PAD48_SEL_OE_SFT 20
++#define PAD48_SEL_OE_HI 20
++#define PAD48_SEL_OE_SZ 1
++#define GPIO_10_ID_MSK 0x10000000
++#define GPIO_10_ID_I_MSK 0xefffffff
++#define GPIO_10_ID_SFT 28
++#define GPIO_10_ID_HI 28
++#define GPIO_10_ID_SZ 1
++#define PAD49_OE_MSK 0x00000001
++#define PAD49_OE_I_MSK 0xfffffffe
++#define PAD49_OE_SFT 0
++#define PAD49_OE_HI 0
++#define PAD49_OE_SZ 1
++#define PAD49_PE_MSK 0x00000002
++#define PAD49_PE_I_MSK 0xfffffffd
++#define PAD49_PE_SFT 1
++#define PAD49_PE_HI 1
++#define PAD49_PE_SZ 1
++#define PAD49_DS_MSK 0x00000004
++#define PAD49_DS_I_MSK 0xfffffffb
++#define PAD49_DS_SFT 2
++#define PAD49_DS_HI 2
++#define PAD49_DS_SZ 1
++#define PAD49_IE_MSK 0x00000008
++#define PAD49_IE_I_MSK 0xfffffff7
++#define PAD49_IE_SFT 3
++#define PAD49_IE_HI 3
++#define PAD49_IE_SZ 1
++#define PAD49_SEL_I_MSK 0x00000070
++#define PAD49_SEL_I_I_MSK 0xffffff8f
++#define PAD49_SEL_I_SFT 4
++#define PAD49_SEL_I_HI 6
++#define PAD49_SEL_I_SZ 3
++#define PAD49_OD_MSK 0x00000100
++#define PAD49_OD_I_MSK 0xfffffeff
++#define PAD49_OD_SFT 8
++#define PAD49_OD_HI 8
++#define PAD49_OD_SZ 1
++#define PAD49_SEL_O_MSK 0x00003000
++#define PAD49_SEL_O_I_MSK 0xffffcfff
++#define PAD49_SEL_O_SFT 12
++#define PAD49_SEL_O_HI 13
++#define PAD49_SEL_O_SZ 2
++#define PAD49_SEL_OE_MSK 0x00100000
++#define PAD49_SEL_OE_I_MSK 0xffefffff
++#define PAD49_SEL_OE_SFT 20
++#define PAD49_SEL_OE_HI 20
++#define PAD49_SEL_OE_SZ 1
++#define GPIO_11_ID_MSK 0x10000000
++#define GPIO_11_ID_I_MSK 0xefffffff
++#define GPIO_11_ID_SFT 28
++#define GPIO_11_ID_HI 28
++#define GPIO_11_ID_SZ 1
++#define PAD50_OE_MSK 0x00000001
++#define PAD50_OE_I_MSK 0xfffffffe
++#define PAD50_OE_SFT 0
++#define PAD50_OE_HI 0
++#define PAD50_OE_SZ 1
++#define PAD50_PE_MSK 0x00000002
++#define PAD50_PE_I_MSK 0xfffffffd
++#define PAD50_PE_SFT 1
++#define PAD50_PE_HI 1
++#define PAD50_PE_SZ 1
++#define PAD50_DS_MSK 0x00000004
++#define PAD50_DS_I_MSK 0xfffffffb
++#define PAD50_DS_SFT 2
++#define PAD50_DS_HI 2
++#define PAD50_DS_SZ 1
++#define PAD50_IE_MSK 0x00000008
++#define PAD50_IE_I_MSK 0xfffffff7
++#define PAD50_IE_SFT 3
++#define PAD50_IE_HI 3
++#define PAD50_IE_SZ 1
++#define PAD50_SEL_I_MSK 0x00000070
++#define PAD50_SEL_I_I_MSK 0xffffff8f
++#define PAD50_SEL_I_SFT 4
++#define PAD50_SEL_I_HI 6
++#define PAD50_SEL_I_SZ 3
++#define PAD50_OD_MSK 0x00000100
++#define PAD50_OD_I_MSK 0xfffffeff
++#define PAD50_OD_SFT 8
++#define PAD50_OD_HI 8
++#define PAD50_OD_SZ 1
++#define PAD50_SEL_O_MSK 0x00003000
++#define PAD50_SEL_O_I_MSK 0xffffcfff
++#define PAD50_SEL_O_SFT 12
++#define PAD50_SEL_O_HI 13
++#define PAD50_SEL_O_SZ 2
++#define PAD50_SEL_OE_MSK 0x00100000
++#define PAD50_SEL_OE_I_MSK 0xffefffff
++#define PAD50_SEL_OE_SFT 20
++#define PAD50_SEL_OE_HI 20
++#define PAD50_SEL_OE_SZ 1
++#define GPIO_12_ID_MSK 0x10000000
++#define GPIO_12_ID_I_MSK 0xefffffff
++#define GPIO_12_ID_SFT 28
++#define GPIO_12_ID_HI 28
++#define GPIO_12_ID_SZ 1
++#define PAD51_OE_MSK 0x00000001
++#define PAD51_OE_I_MSK 0xfffffffe
++#define PAD51_OE_SFT 0
++#define PAD51_OE_HI 0
++#define PAD51_OE_SZ 1
++#define PAD51_PE_MSK 0x00000002
++#define PAD51_PE_I_MSK 0xfffffffd
++#define PAD51_PE_SFT 1
++#define PAD51_PE_HI 1
++#define PAD51_PE_SZ 1
++#define PAD51_DS_MSK 0x00000004
++#define PAD51_DS_I_MSK 0xfffffffb
++#define PAD51_DS_SFT 2
++#define PAD51_DS_HI 2
++#define PAD51_DS_SZ 1
++#define PAD51_IE_MSK 0x00000008
++#define PAD51_IE_I_MSK 0xfffffff7
++#define PAD51_IE_SFT 3
++#define PAD51_IE_HI 3
++#define PAD51_IE_SZ 1
++#define PAD51_SEL_I_MSK 0x00000030
++#define PAD51_SEL_I_I_MSK 0xffffffcf
++#define PAD51_SEL_I_SFT 4
++#define PAD51_SEL_I_HI 5
++#define PAD51_SEL_I_SZ 2
++#define PAD51_OD_MSK 0x00000100
++#define PAD51_OD_I_MSK 0xfffffeff
++#define PAD51_OD_SFT 8
++#define PAD51_OD_HI 8
++#define PAD51_OD_SZ 1
++#define PAD51_SEL_O_MSK 0x00001000
++#define PAD51_SEL_O_I_MSK 0xffffefff
++#define PAD51_SEL_O_SFT 12
++#define PAD51_SEL_O_HI 12
++#define PAD51_SEL_O_SZ 1
++#define PAD51_SEL_OE_MSK 0x00100000
++#define PAD51_SEL_OE_I_MSK 0xffefffff
++#define PAD51_SEL_OE_SFT 20
++#define PAD51_SEL_OE_HI 20
++#define PAD51_SEL_OE_SZ 1
++#define GPIO_13_ID_MSK 0x10000000
++#define GPIO_13_ID_I_MSK 0xefffffff
++#define GPIO_13_ID_SFT 28
++#define GPIO_13_ID_HI 28
++#define GPIO_13_ID_SZ 1
++#define PAD52_OE_MSK 0x00000001
++#define PAD52_OE_I_MSK 0xfffffffe
++#define PAD52_OE_SFT 0
++#define PAD52_OE_HI 0
++#define PAD52_OE_SZ 1
++#define PAD52_PE_MSK 0x00000002
++#define PAD52_PE_I_MSK 0xfffffffd
++#define PAD52_PE_SFT 1
++#define PAD52_PE_HI 1
++#define PAD52_PE_SZ 1
++#define PAD52_DS_MSK 0x00000004
++#define PAD52_DS_I_MSK 0xfffffffb
++#define PAD52_DS_SFT 2
++#define PAD52_DS_HI 2
++#define PAD52_DS_SZ 1
++#define PAD52_SEL_I_MSK 0x00000030
++#define PAD52_SEL_I_I_MSK 0xffffffcf
++#define PAD52_SEL_I_SFT 4
++#define PAD52_SEL_I_HI 5
++#define PAD52_SEL_I_SZ 2
++#define PAD52_OD_MSK 0x00000100
++#define PAD52_OD_I_MSK 0xfffffeff
++#define PAD52_OD_SFT 8
++#define PAD52_OD_HI 8
++#define PAD52_OD_SZ 1
++#define PAD52_SEL_O_MSK 0x00001000
++#define PAD52_SEL_O_I_MSK 0xffffefff
++#define PAD52_SEL_O_SFT 12
++#define PAD52_SEL_O_HI 12
++#define PAD52_SEL_O_SZ 1
++#define PAD52_SEL_OE_MSK 0x00100000
++#define PAD52_SEL_OE_I_MSK 0xffefffff
++#define PAD52_SEL_OE_SFT 20
++#define PAD52_SEL_OE_HI 20
++#define PAD52_SEL_OE_SZ 1
++#define GPIO_14_ID_MSK 0x10000000
++#define GPIO_14_ID_I_MSK 0xefffffff
++#define GPIO_14_ID_SFT 28
++#define GPIO_14_ID_HI 28
++#define GPIO_14_ID_SZ 1
++#define PAD53_OE_MSK 0x00000001
++#define PAD53_OE_I_MSK 0xfffffffe
++#define PAD53_OE_SFT 0
++#define PAD53_OE_HI 0
++#define PAD53_OE_SZ 1
++#define PAD53_PE_MSK 0x00000002
++#define PAD53_PE_I_MSK 0xfffffffd
++#define PAD53_PE_SFT 1
++#define PAD53_PE_HI 1
++#define PAD53_PE_SZ 1
++#define PAD53_DS_MSK 0x00000004
++#define PAD53_DS_I_MSK 0xfffffffb
++#define PAD53_DS_SFT 2
++#define PAD53_DS_HI 2
++#define PAD53_DS_SZ 1
++#define PAD53_IE_MSK 0x00000008
++#define PAD53_IE_I_MSK 0xfffffff7
++#define PAD53_IE_SFT 3
++#define PAD53_IE_HI 3
++#define PAD53_IE_SZ 1
++#define PAD53_SEL_I_MSK 0x00000030
++#define PAD53_SEL_I_I_MSK 0xffffffcf
++#define PAD53_SEL_I_SFT 4
++#define PAD53_SEL_I_HI 5
++#define PAD53_SEL_I_SZ 2
++#define PAD53_OD_MSK 0x00000100
++#define PAD53_OD_I_MSK 0xfffffeff
++#define PAD53_OD_SFT 8
++#define PAD53_OD_HI 8
++#define PAD53_OD_SZ 1
++#define PAD53_SEL_O_MSK 0x00001000
++#define PAD53_SEL_O_I_MSK 0xffffefff
++#define PAD53_SEL_O_SFT 12
++#define PAD53_SEL_O_HI 12
++#define PAD53_SEL_O_SZ 1
++#define JTAG_TMS_ID_MSK 0x10000000
++#define JTAG_TMS_ID_I_MSK 0xefffffff
++#define JTAG_TMS_ID_SFT 28
++#define JTAG_TMS_ID_HI 28
++#define JTAG_TMS_ID_SZ 1
++#define PAD54_OE_MSK 0x00000001
++#define PAD54_OE_I_MSK 0xfffffffe
++#define PAD54_OE_SFT 0
++#define PAD54_OE_HI 0
++#define PAD54_OE_SZ 1
++#define PAD54_PE_MSK 0x00000002
++#define PAD54_PE_I_MSK 0xfffffffd
++#define PAD54_PE_SFT 1
++#define PAD54_PE_HI 1
++#define PAD54_PE_SZ 1
++#define PAD54_DS_MSK 0x00000004
++#define PAD54_DS_I_MSK 0xfffffffb
++#define PAD54_DS_SFT 2
++#define PAD54_DS_HI 2
++#define PAD54_DS_SZ 1
++#define PAD54_OD_MSK 0x00000100
++#define PAD54_OD_I_MSK 0xfffffeff
++#define PAD54_OD_SFT 8
++#define PAD54_OD_HI 8
++#define PAD54_OD_SZ 1
++#define PAD54_SEL_O_MSK 0x00003000
++#define PAD54_SEL_O_I_MSK 0xffffcfff
++#define PAD54_SEL_O_SFT 12
++#define PAD54_SEL_O_HI 13
++#define PAD54_SEL_O_SZ 2
++#define JTAG_TCK_ID_MSK 0x10000000
++#define JTAG_TCK_ID_I_MSK 0xefffffff
++#define JTAG_TCK_ID_SFT 28
++#define JTAG_TCK_ID_HI 28
++#define JTAG_TCK_ID_SZ 1
++#define PAD56_PE_MSK 0x00000002
++#define PAD56_PE_I_MSK 0xfffffffd
++#define PAD56_PE_SFT 1
++#define PAD56_PE_HI 1
++#define PAD56_PE_SZ 1
++#define PAD56_DS_MSK 0x00000004
++#define PAD56_DS_I_MSK 0xfffffffb
++#define PAD56_DS_SFT 2
++#define PAD56_DS_HI 2
++#define PAD56_DS_SZ 1
++#define PAD56_SEL_I_MSK 0x00000010
++#define PAD56_SEL_I_I_MSK 0xffffffef
++#define PAD56_SEL_I_SFT 4
++#define PAD56_SEL_I_HI 4
++#define PAD56_SEL_I_SZ 1
++#define PAD56_OD_MSK 0x00000100
++#define PAD56_OD_I_MSK 0xfffffeff
++#define PAD56_OD_SFT 8
++#define PAD56_OD_HI 8
++#define PAD56_OD_SZ 1
++#define JTAG_TDI_ID_MSK 0x10000000
++#define JTAG_TDI_ID_I_MSK 0xefffffff
++#define JTAG_TDI_ID_SFT 28
++#define JTAG_TDI_ID_HI 28
++#define JTAG_TDI_ID_SZ 1
++#define PAD57_OE_MSK 0x00000001
++#define PAD57_OE_I_MSK 0xfffffffe
++#define PAD57_OE_SFT 0
++#define PAD57_OE_HI 0
++#define PAD57_OE_SZ 1
++#define PAD57_PE_MSK 0x00000002
++#define PAD57_PE_I_MSK 0xfffffffd
++#define PAD57_PE_SFT 1
++#define PAD57_PE_HI 1
++#define PAD57_PE_SZ 1
++#define PAD57_DS_MSK 0x00000004
++#define PAD57_DS_I_MSK 0xfffffffb
++#define PAD57_DS_SFT 2
++#define PAD57_DS_HI 2
++#define PAD57_DS_SZ 1
++#define PAD57_IE_MSK 0x00000008
++#define PAD57_IE_I_MSK 0xfffffff7
++#define PAD57_IE_SFT 3
++#define PAD57_IE_HI 3
++#define PAD57_IE_SZ 1
++#define PAD57_SEL_I_MSK 0x00000030
++#define PAD57_SEL_I_I_MSK 0xffffffcf
++#define PAD57_SEL_I_SFT 4
++#define PAD57_SEL_I_HI 5
++#define PAD57_SEL_I_SZ 2
++#define PAD57_OD_MSK 0x00000100
++#define PAD57_OD_I_MSK 0xfffffeff
++#define PAD57_OD_SFT 8
++#define PAD57_OD_HI 8
++#define PAD57_OD_SZ 1
++#define PAD57_SEL_O_MSK 0x00003000
++#define PAD57_SEL_O_I_MSK 0xffffcfff
++#define PAD57_SEL_O_SFT 12
++#define PAD57_SEL_O_HI 13
++#define PAD57_SEL_O_SZ 2
++#define PAD57_SEL_OE_MSK 0x00100000
++#define PAD57_SEL_OE_I_MSK 0xffefffff
++#define PAD57_SEL_OE_SFT 20
++#define PAD57_SEL_OE_HI 20
++#define PAD57_SEL_OE_SZ 1
++#define JTAG_TDO_ID_MSK 0x10000000
++#define JTAG_TDO_ID_I_MSK 0xefffffff
++#define JTAG_TDO_ID_SFT 28
++#define JTAG_TDO_ID_HI 28
++#define JTAG_TDO_ID_SZ 1
++#define PAD58_OE_MSK 0x00000001
++#define PAD58_OE_I_MSK 0xfffffffe
++#define PAD58_OE_SFT 0
++#define PAD58_OE_HI 0
++#define PAD58_OE_SZ 1
++#define PAD58_PE_MSK 0x00000002
++#define PAD58_PE_I_MSK 0xfffffffd
++#define PAD58_PE_SFT 1
++#define PAD58_PE_HI 1
++#define PAD58_PE_SZ 1
++#define PAD58_DS_MSK 0x00000004
++#define PAD58_DS_I_MSK 0xfffffffb
++#define PAD58_DS_SFT 2
++#define PAD58_DS_HI 2
++#define PAD58_DS_SZ 1
++#define PAD58_IE_MSK 0x00000008
++#define PAD58_IE_I_MSK 0xfffffff7
++#define PAD58_IE_SFT 3
++#define PAD58_IE_HI 3
++#define PAD58_IE_SZ 1
++#define PAD58_SEL_I_MSK 0x00000030
++#define PAD58_SEL_I_I_MSK 0xffffffcf
++#define PAD58_SEL_I_SFT 4
++#define PAD58_SEL_I_HI 5
++#define PAD58_SEL_I_SZ 2
++#define PAD58_OD_MSK 0x00000100
++#define PAD58_OD_I_MSK 0xfffffeff
++#define PAD58_OD_SFT 8
++#define PAD58_OD_HI 8
++#define PAD58_OD_SZ 1
++#define PAD58_SEL_O_MSK 0x00001000
++#define PAD58_SEL_O_I_MSK 0xffffefff
++#define PAD58_SEL_O_SFT 12
++#define PAD58_SEL_O_HI 12
++#define PAD58_SEL_O_SZ 1
++#define TEST_16_ID_MSK 0x10000000
++#define TEST_16_ID_I_MSK 0xefffffff
++#define TEST_16_ID_SFT 28
++#define TEST_16_ID_HI 28
++#define TEST_16_ID_SZ 1
++#define PAD59_OE_MSK 0x00000001
++#define PAD59_OE_I_MSK 0xfffffffe
++#define PAD59_OE_SFT 0
++#define PAD59_OE_HI 0
++#define PAD59_OE_SZ 1
++#define PAD59_PE_MSK 0x00000002
++#define PAD59_PE_I_MSK 0xfffffffd
++#define PAD59_PE_SFT 1
++#define PAD59_PE_HI 1
++#define PAD59_PE_SZ 1
++#define PAD59_DS_MSK 0x00000004
++#define PAD59_DS_I_MSK 0xfffffffb
++#define PAD59_DS_SFT 2
++#define PAD59_DS_HI 2
++#define PAD59_DS_SZ 1
++#define PAD59_IE_MSK 0x00000008
++#define PAD59_IE_I_MSK 0xfffffff7
++#define PAD59_IE_SFT 3
++#define PAD59_IE_HI 3
++#define PAD59_IE_SZ 1
++#define PAD59_SEL_I_MSK 0x00000030
++#define PAD59_SEL_I_I_MSK 0xffffffcf
++#define PAD59_SEL_I_SFT 4
++#define PAD59_SEL_I_HI 5
++#define PAD59_SEL_I_SZ 2
++#define PAD59_OD_MSK 0x00000100
++#define PAD59_OD_I_MSK 0xfffffeff
++#define PAD59_OD_SFT 8
++#define PAD59_OD_HI 8
++#define PAD59_OD_SZ 1
++#define PAD59_SEL_O_MSK 0x00001000
++#define PAD59_SEL_O_I_MSK 0xffffefff
++#define PAD59_SEL_O_SFT 12
++#define PAD59_SEL_O_HI 12
++#define PAD59_SEL_O_SZ 1
++#define TEST_17_ID_MSK 0x10000000
++#define TEST_17_ID_I_MSK 0xefffffff
++#define TEST_17_ID_SFT 28
++#define TEST_17_ID_HI 28
++#define TEST_17_ID_SZ 1
++#define PAD60_OE_MSK 0x00000001
++#define PAD60_OE_I_MSK 0xfffffffe
++#define PAD60_OE_SFT 0
++#define PAD60_OE_HI 0
++#define PAD60_OE_SZ 1
++#define PAD60_PE_MSK 0x00000002
++#define PAD60_PE_I_MSK 0xfffffffd
++#define PAD60_PE_SFT 1
++#define PAD60_PE_HI 1
++#define PAD60_PE_SZ 1
++#define PAD60_DS_MSK 0x00000004
++#define PAD60_DS_I_MSK 0xfffffffb
++#define PAD60_DS_SFT 2
++#define PAD60_DS_HI 2
++#define PAD60_DS_SZ 1
++#define PAD60_IE_MSK 0x00000008
++#define PAD60_IE_I_MSK 0xfffffff7
++#define PAD60_IE_SFT 3
++#define PAD60_IE_HI 3
++#define PAD60_IE_SZ 1
++#define PAD60_SEL_I_MSK 0x00000030
++#define PAD60_SEL_I_I_MSK 0xffffffcf
++#define PAD60_SEL_I_SFT 4
++#define PAD60_SEL_I_HI 5
++#define PAD60_SEL_I_SZ 2
++#define PAD60_OD_MSK 0x00000100
++#define PAD60_OD_I_MSK 0xfffffeff
++#define PAD60_OD_SFT 8
++#define PAD60_OD_HI 8
++#define PAD60_OD_SZ 1
++#define PAD60_SEL_O_MSK 0x00001000
++#define PAD60_SEL_O_I_MSK 0xffffefff
++#define PAD60_SEL_O_SFT 12
++#define PAD60_SEL_O_HI 12
++#define PAD60_SEL_O_SZ 1
++#define TEST_18_ID_MSK 0x10000000
++#define TEST_18_ID_I_MSK 0xefffffff
++#define TEST_18_ID_SFT 28
++#define TEST_18_ID_HI 28
++#define TEST_18_ID_SZ 1
++#define PAD61_OE_MSK 0x00000001
++#define PAD61_OE_I_MSK 0xfffffffe
++#define PAD61_OE_SFT 0
++#define PAD61_OE_HI 0
++#define PAD61_OE_SZ 1
++#define PAD61_PE_MSK 0x00000002
++#define PAD61_PE_I_MSK 0xfffffffd
++#define PAD61_PE_SFT 1
++#define PAD61_PE_HI 1
++#define PAD61_PE_SZ 1
++#define PAD61_DS_MSK 0x00000004
++#define PAD61_DS_I_MSK 0xfffffffb
++#define PAD61_DS_SFT 2
++#define PAD61_DS_HI 2
++#define PAD61_DS_SZ 1
++#define PAD61_IE_MSK 0x00000008
++#define PAD61_IE_I_MSK 0xfffffff7
++#define PAD61_IE_SFT 3
++#define PAD61_IE_HI 3
++#define PAD61_IE_SZ 1
++#define PAD61_SEL_I_MSK 0x00000010
++#define PAD61_SEL_I_I_MSK 0xffffffef
++#define PAD61_SEL_I_SFT 4
++#define PAD61_SEL_I_HI 4
++#define PAD61_SEL_I_SZ 1
++#define PAD61_OD_MSK 0x00000100
++#define PAD61_OD_I_MSK 0xfffffeff
++#define PAD61_OD_SFT 8
++#define PAD61_OD_HI 8
++#define PAD61_OD_SZ 1
++#define PAD61_SEL_O_MSK 0x00003000
++#define PAD61_SEL_O_I_MSK 0xffffcfff
++#define PAD61_SEL_O_SFT 12
++#define PAD61_SEL_O_HI 13
++#define PAD61_SEL_O_SZ 2
++#define TEST_19_ID_MSK 0x10000000
++#define TEST_19_ID_I_MSK 0xefffffff
++#define TEST_19_ID_SFT 28
++#define TEST_19_ID_HI 28
++#define TEST_19_ID_SZ 1
++#define PAD62_OE_MSK 0x00000001
++#define PAD62_OE_I_MSK 0xfffffffe
++#define PAD62_OE_SFT 0
++#define PAD62_OE_HI 0
++#define PAD62_OE_SZ 1
++#define PAD62_PE_MSK 0x00000002
++#define PAD62_PE_I_MSK 0xfffffffd
++#define PAD62_PE_SFT 1
++#define PAD62_PE_HI 1
++#define PAD62_PE_SZ 1
++#define PAD62_DS_MSK 0x00000004
++#define PAD62_DS_I_MSK 0xfffffffb
++#define PAD62_DS_SFT 2
++#define PAD62_DS_HI 2
++#define PAD62_DS_SZ 1
++#define PAD62_IE_MSK 0x00000008
++#define PAD62_IE_I_MSK 0xfffffff7
++#define PAD62_IE_SFT 3
++#define PAD62_IE_HI 3
++#define PAD62_IE_SZ 1
++#define PAD62_SEL_I_MSK 0x00000010
++#define PAD62_SEL_I_I_MSK 0xffffffef
++#define PAD62_SEL_I_SFT 4
++#define PAD62_SEL_I_HI 4
++#define PAD62_SEL_I_SZ 1
++#define PAD62_OD_MSK 0x00000100
++#define PAD62_OD_I_MSK 0xfffffeff
++#define PAD62_OD_SFT 8
++#define PAD62_OD_HI 8
++#define PAD62_OD_SZ 1
++#define PAD62_SEL_O_MSK 0x00001000
++#define PAD62_SEL_O_I_MSK 0xffffefff
++#define PAD62_SEL_O_SFT 12
++#define PAD62_SEL_O_HI 12
++#define PAD62_SEL_O_SZ 1
++#define TEST_20_ID_MSK 0x10000000
++#define TEST_20_ID_I_MSK 0xefffffff
++#define TEST_20_ID_SFT 28
++#define TEST_20_ID_HI 28
++#define TEST_20_ID_SZ 1
++#define PAD64_OE_MSK 0x00000001
++#define PAD64_OE_I_MSK 0xfffffffe
++#define PAD64_OE_SFT 0
++#define PAD64_OE_HI 0
++#define PAD64_OE_SZ 1
++#define PAD64_PE_MSK 0x00000002
++#define PAD64_PE_I_MSK 0xfffffffd
++#define PAD64_PE_SFT 1
++#define PAD64_PE_HI 1
++#define PAD64_PE_SZ 1
++#define PAD64_DS_MSK 0x00000004
++#define PAD64_DS_I_MSK 0xfffffffb
++#define PAD64_DS_SFT 2
++#define PAD64_DS_HI 2
++#define PAD64_DS_SZ 1
++#define PAD64_IE_MSK 0x00000008
++#define PAD64_IE_I_MSK 0xfffffff7
++#define PAD64_IE_SFT 3
++#define PAD64_IE_HI 3
++#define PAD64_IE_SZ 1
++#define PAD64_SEL_I_MSK 0x00000070
++#define PAD64_SEL_I_I_MSK 0xffffff8f
++#define PAD64_SEL_I_SFT 4
++#define PAD64_SEL_I_HI 6
++#define PAD64_SEL_I_SZ 3
++#define PAD64_OD_MSK 0x00000100
++#define PAD64_OD_I_MSK 0xfffffeff
++#define PAD64_OD_SFT 8
++#define PAD64_OD_HI 8
++#define PAD64_OD_SZ 1
++#define PAD64_SEL_O_MSK 0x00003000
++#define PAD64_SEL_O_I_MSK 0xffffcfff
++#define PAD64_SEL_O_SFT 12
++#define PAD64_SEL_O_HI 13
++#define PAD64_SEL_O_SZ 2
++#define PAD64_SEL_OE_MSK 0x00100000
++#define PAD64_SEL_OE_I_MSK 0xffefffff
++#define PAD64_SEL_OE_SFT 20
++#define PAD64_SEL_OE_HI 20
++#define PAD64_SEL_OE_SZ 1
++#define GPIO_15_IP_ID_MSK 0x10000000
++#define GPIO_15_IP_ID_I_MSK 0xefffffff
++#define GPIO_15_IP_ID_SFT 28
++#define GPIO_15_IP_ID_HI 28
++#define GPIO_15_IP_ID_SZ 1
++#define PAD65_OE_MSK 0x00000001
++#define PAD65_OE_I_MSK 0xfffffffe
++#define PAD65_OE_SFT 0
++#define PAD65_OE_HI 0
++#define PAD65_OE_SZ 1
++#define PAD65_PE_MSK 0x00000002
++#define PAD65_PE_I_MSK 0xfffffffd
++#define PAD65_PE_SFT 1
++#define PAD65_PE_HI 1
++#define PAD65_PE_SZ 1
++#define PAD65_DS_MSK 0x00000004
++#define PAD65_DS_I_MSK 0xfffffffb
++#define PAD65_DS_SFT 2
++#define PAD65_DS_HI 2
++#define PAD65_DS_SZ 1
++#define PAD65_IE_MSK 0x00000008
++#define PAD65_IE_I_MSK 0xfffffff7
++#define PAD65_IE_SFT 3
++#define PAD65_IE_HI 3
++#define PAD65_IE_SZ 1
++#define PAD65_SEL_I_MSK 0x00000070
++#define PAD65_SEL_I_I_MSK 0xffffff8f
++#define PAD65_SEL_I_SFT 4
++#define PAD65_SEL_I_HI 6
++#define PAD65_SEL_I_SZ 3
++#define PAD65_OD_MSK 0x00000100
++#define PAD65_OD_I_MSK 0xfffffeff
++#define PAD65_OD_SFT 8
++#define PAD65_OD_HI 8
++#define PAD65_OD_SZ 1
++#define PAD65_SEL_O_MSK 0x00001000
++#define PAD65_SEL_O_I_MSK 0xffffefff
++#define PAD65_SEL_O_SFT 12
++#define PAD65_SEL_O_HI 12
++#define PAD65_SEL_O_SZ 1
++#define GPIO_TEST_7_IN_ID_MSK 0x10000000
++#define GPIO_TEST_7_IN_ID_I_MSK 0xefffffff
++#define GPIO_TEST_7_IN_ID_SFT 28
++#define GPIO_TEST_7_IN_ID_HI 28
++#define GPIO_TEST_7_IN_ID_SZ 1
++#define PAD66_OE_MSK 0x00000001
++#define PAD66_OE_I_MSK 0xfffffffe
++#define PAD66_OE_SFT 0
++#define PAD66_OE_HI 0
++#define PAD66_OE_SZ 1
++#define PAD66_PE_MSK 0x00000002
++#define PAD66_PE_I_MSK 0xfffffffd
++#define PAD66_PE_SFT 1
++#define PAD66_PE_HI 1
++#define PAD66_PE_SZ 1
++#define PAD66_DS_MSK 0x00000004
++#define PAD66_DS_I_MSK 0xfffffffb
++#define PAD66_DS_SFT 2
++#define PAD66_DS_HI 2
++#define PAD66_DS_SZ 1
++#define PAD66_IE_MSK 0x00000008
++#define PAD66_IE_I_MSK 0xfffffff7
++#define PAD66_IE_SFT 3
++#define PAD66_IE_HI 3
++#define PAD66_IE_SZ 1
++#define PAD66_SEL_I_MSK 0x00000030
++#define PAD66_SEL_I_I_MSK 0xffffffcf
++#define PAD66_SEL_I_SFT 4
++#define PAD66_SEL_I_HI 5
++#define PAD66_SEL_I_SZ 2
++#define PAD66_OD_MSK 0x00000100
++#define PAD66_OD_I_MSK 0xfffffeff
++#define PAD66_OD_SFT 8
++#define PAD66_OD_HI 8
++#define PAD66_OD_SZ 1
++#define PAD66_SEL_O_MSK 0x00003000
++#define PAD66_SEL_O_I_MSK 0xffffcfff
++#define PAD66_SEL_O_SFT 12
++#define PAD66_SEL_O_HI 13
++#define PAD66_SEL_O_SZ 2
++#define GPIO_17_QP_ID_MSK 0x10000000
++#define GPIO_17_QP_ID_I_MSK 0xefffffff
++#define GPIO_17_QP_ID_SFT 28
++#define GPIO_17_QP_ID_HI 28
++#define GPIO_17_QP_ID_SZ 1
++#define PAD68_OE_MSK 0x00000001
++#define PAD68_OE_I_MSK 0xfffffffe
++#define PAD68_OE_SFT 0
++#define PAD68_OE_HI 0
++#define PAD68_OE_SZ 1
++#define PAD68_PE_MSK 0x00000002
++#define PAD68_PE_I_MSK 0xfffffffd
++#define PAD68_PE_SFT 1
++#define PAD68_PE_HI 1
++#define PAD68_PE_SZ 1
++#define PAD68_DS_MSK 0x00000004
++#define PAD68_DS_I_MSK 0xfffffffb
++#define PAD68_DS_SFT 2
++#define PAD68_DS_HI 2
++#define PAD68_DS_SZ 1
++#define PAD68_IE_MSK 0x00000008
++#define PAD68_IE_I_MSK 0xfffffff7
++#define PAD68_IE_SFT 3
++#define PAD68_IE_HI 3
++#define PAD68_IE_SZ 1
++#define PAD68_OD_MSK 0x00000100
++#define PAD68_OD_I_MSK 0xfffffeff
++#define PAD68_OD_SFT 8
++#define PAD68_OD_HI 8
++#define PAD68_OD_SZ 1
++#define PAD68_SEL_O_MSK 0x00001000
++#define PAD68_SEL_O_I_MSK 0xffffefff
++#define PAD68_SEL_O_SFT 12
++#define PAD68_SEL_O_HI 12
++#define PAD68_SEL_O_SZ 1
++#define GPIO_19_ID_MSK 0x10000000
++#define GPIO_19_ID_I_MSK 0xefffffff
++#define GPIO_19_ID_SFT 28
++#define GPIO_19_ID_HI 28
++#define GPIO_19_ID_SZ 1
++#define PAD67_OE_MSK 0x00000001
++#define PAD67_OE_I_MSK 0xfffffffe
++#define PAD67_OE_SFT 0
++#define PAD67_OE_HI 0
++#define PAD67_OE_SZ 1
++#define PAD67_PE_MSK 0x00000002
++#define PAD67_PE_I_MSK 0xfffffffd
++#define PAD67_PE_SFT 1
++#define PAD67_PE_HI 1
++#define PAD67_PE_SZ 1
++#define PAD67_DS_MSK 0x00000004
++#define PAD67_DS_I_MSK 0xfffffffb
++#define PAD67_DS_SFT 2
++#define PAD67_DS_HI 2
++#define PAD67_DS_SZ 1
++#define PAD67_IE_MSK 0x00000008
++#define PAD67_IE_I_MSK 0xfffffff7
++#define PAD67_IE_SFT 3
++#define PAD67_IE_HI 3
++#define PAD67_IE_SZ 1
++#define PAD67_SEL_I_MSK 0x00000070
++#define PAD67_SEL_I_I_MSK 0xffffff8f
++#define PAD67_SEL_I_SFT 4
++#define PAD67_SEL_I_HI 6
++#define PAD67_SEL_I_SZ 3
++#define PAD67_OD_MSK 0x00000100
++#define PAD67_OD_I_MSK 0xfffffeff
++#define PAD67_OD_SFT 8
++#define PAD67_OD_HI 8
++#define PAD67_OD_SZ 1
++#define PAD67_SEL_O_MSK 0x00003000
++#define PAD67_SEL_O_I_MSK 0xffffcfff
++#define PAD67_SEL_O_SFT 12
++#define PAD67_SEL_O_HI 13
++#define PAD67_SEL_O_SZ 2
++#define GPIO_TEST_8_QN_ID_MSK 0x10000000
++#define GPIO_TEST_8_QN_ID_I_MSK 0xefffffff
++#define GPIO_TEST_8_QN_ID_SFT 28
++#define GPIO_TEST_8_QN_ID_HI 28
++#define GPIO_TEST_8_QN_ID_SZ 1
++#define PAD69_OE_MSK 0x00000001
++#define PAD69_OE_I_MSK 0xfffffffe
++#define PAD69_OE_SFT 0
++#define PAD69_OE_HI 0
++#define PAD69_OE_SZ 1
++#define PAD69_PE_MSK 0x00000002
++#define PAD69_PE_I_MSK 0xfffffffd
++#define PAD69_PE_SFT 1
++#define PAD69_PE_HI 1
++#define PAD69_PE_SZ 1
++#define PAD69_DS_MSK 0x00000004
++#define PAD69_DS_I_MSK 0xfffffffb
++#define PAD69_DS_SFT 2
++#define PAD69_DS_HI 2
++#define PAD69_DS_SZ 1
++#define PAD69_IE_MSK 0x00000008
++#define PAD69_IE_I_MSK 0xfffffff7
++#define PAD69_IE_SFT 3
++#define PAD69_IE_HI 3
++#define PAD69_IE_SZ 1
++#define PAD69_SEL_I_MSK 0x00000030
++#define PAD69_SEL_I_I_MSK 0xffffffcf
++#define PAD69_SEL_I_SFT 4
++#define PAD69_SEL_I_HI 5
++#define PAD69_SEL_I_SZ 2
++#define PAD69_OD_MSK 0x00000100
++#define PAD69_OD_I_MSK 0xfffffeff
++#define PAD69_OD_SFT 8
++#define PAD69_OD_HI 8
++#define PAD69_OD_SZ 1
++#define PAD69_SEL_O_MSK 0x00001000
++#define PAD69_SEL_O_I_MSK 0xffffefff
++#define PAD69_SEL_O_SFT 12
++#define PAD69_SEL_O_HI 12
++#define PAD69_SEL_O_SZ 1
++#define STRAP2_MSK 0x08000000
++#define STRAP2_I_MSK 0xf7ffffff
++#define STRAP2_SFT 27
++#define STRAP2_HI 27
++#define STRAP2_SZ 1
++#define GPIO_20_ID_MSK 0x10000000
++#define GPIO_20_ID_I_MSK 0xefffffff
++#define GPIO_20_ID_SFT 28
++#define GPIO_20_ID_HI 28
++#define GPIO_20_ID_SZ 1
++#define PAD70_OE_MSK 0x00000001
++#define PAD70_OE_I_MSK 0xfffffffe
++#define PAD70_OE_SFT 0
++#define PAD70_OE_HI 0
++#define PAD70_OE_SZ 1
++#define PAD70_PE_MSK 0x00000002
++#define PAD70_PE_I_MSK 0xfffffffd
++#define PAD70_PE_SFT 1
++#define PAD70_PE_HI 1
++#define PAD70_PE_SZ 1
++#define PAD70_DS_MSK 0x00000004
++#define PAD70_DS_I_MSK 0xfffffffb
++#define PAD70_DS_SFT 2
++#define PAD70_DS_HI 2
++#define PAD70_DS_SZ 1
++#define PAD70_IE_MSK 0x00000008
++#define PAD70_IE_I_MSK 0xfffffff7
++#define PAD70_IE_SFT 3
++#define PAD70_IE_HI 3
++#define PAD70_IE_SZ 1
++#define PAD70_SEL_I_MSK 0x00000030
++#define PAD70_SEL_I_I_MSK 0xffffffcf
++#define PAD70_SEL_I_SFT 4
++#define PAD70_SEL_I_HI 5
++#define PAD70_SEL_I_SZ 2
++#define PAD70_OD_MSK 0x00000100
++#define PAD70_OD_I_MSK 0xfffffeff
++#define PAD70_OD_SFT 8
++#define PAD70_OD_HI 8
++#define PAD70_OD_SZ 1
++#define PAD70_SEL_O_MSK 0x00007000
++#define PAD70_SEL_O_I_MSK 0xffff8fff
++#define PAD70_SEL_O_SFT 12
++#define PAD70_SEL_O_HI 14
++#define PAD70_SEL_O_SZ 3
++#define GPIO_21_ID_MSK 0x10000000
++#define GPIO_21_ID_I_MSK 0xefffffff
++#define GPIO_21_ID_SFT 28
++#define GPIO_21_ID_HI 28
++#define GPIO_21_ID_SZ 1
++#define PAD231_OE_MSK 0x00000001
++#define PAD231_OE_I_MSK 0xfffffffe
++#define PAD231_OE_SFT 0
++#define PAD231_OE_HI 0
++#define PAD231_OE_SZ 1
++#define PAD231_PE_MSK 0x00000002
++#define PAD231_PE_I_MSK 0xfffffffd
++#define PAD231_PE_SFT 1
++#define PAD231_PE_HI 1
++#define PAD231_PE_SZ 1
++#define PAD231_DS_MSK 0x00000004
++#define PAD231_DS_I_MSK 0xfffffffb
++#define PAD231_DS_SFT 2
++#define PAD231_DS_HI 2
++#define PAD231_DS_SZ 1
++#define PAD231_IE_MSK 0x00000008
++#define PAD231_IE_I_MSK 0xfffffff7
++#define PAD231_IE_SFT 3
++#define PAD231_IE_HI 3
++#define PAD231_IE_SZ 1
++#define PAD231_OD_MSK 0x00000100
++#define PAD231_OD_I_MSK 0xfffffeff
++#define PAD231_OD_SFT 8
++#define PAD231_OD_HI 8
++#define PAD231_OD_SZ 1
++#define PIN_40_OR_56_ID_MSK 0x10000000
++#define PIN_40_OR_56_ID_I_MSK 0xefffffff
++#define PIN_40_OR_56_ID_SFT 28
++#define PIN_40_OR_56_ID_HI 28
++#define PIN_40_OR_56_ID_SZ 1
++#define MP_PHY2RX_DATA__0_SEL_MSK 0x00000001
++#define MP_PHY2RX_DATA__0_SEL_I_MSK 0xfffffffe
++#define MP_PHY2RX_DATA__0_SEL_SFT 0
++#define MP_PHY2RX_DATA__0_SEL_HI 0
++#define MP_PHY2RX_DATA__0_SEL_SZ 1
++#define MP_PHY2RX_DATA__1_SEL_MSK 0x00000002
++#define MP_PHY2RX_DATA__1_SEL_I_MSK 0xfffffffd
++#define MP_PHY2RX_DATA__1_SEL_SFT 1
++#define MP_PHY2RX_DATA__1_SEL_HI 1
++#define MP_PHY2RX_DATA__1_SEL_SZ 1
++#define MP_TX_FF_RPTR__1_SEL_MSK 0x00000004
++#define MP_TX_FF_RPTR__1_SEL_I_MSK 0xfffffffb
++#define MP_TX_FF_RPTR__1_SEL_SFT 2
++#define MP_TX_FF_RPTR__1_SEL_HI 2
++#define MP_TX_FF_RPTR__1_SEL_SZ 1
++#define MP_RX_FF_WPTR__2_SEL_MSK 0x00000008
++#define MP_RX_FF_WPTR__2_SEL_I_MSK 0xfffffff7
++#define MP_RX_FF_WPTR__2_SEL_SFT 3
++#define MP_RX_FF_WPTR__2_SEL_HI 3
++#define MP_RX_FF_WPTR__2_SEL_SZ 1
++#define MP_RX_FF_WPTR__1_SEL_MSK 0x00000010
++#define MP_RX_FF_WPTR__1_SEL_I_MSK 0xffffffef
++#define MP_RX_FF_WPTR__1_SEL_SFT 4
++#define MP_RX_FF_WPTR__1_SEL_HI 4
++#define MP_RX_FF_WPTR__1_SEL_SZ 1
++#define MP_RX_FF_WPTR__0_SEL_MSK 0x00000020
++#define MP_RX_FF_WPTR__0_SEL_I_MSK 0xffffffdf
++#define MP_RX_FF_WPTR__0_SEL_SFT 5
++#define MP_RX_FF_WPTR__0_SEL_HI 5
++#define MP_RX_FF_WPTR__0_SEL_SZ 1
++#define MP_PHY2RX_DATA__2_SEL_MSK 0x00000040
++#define MP_PHY2RX_DATA__2_SEL_I_MSK 0xffffffbf
++#define MP_PHY2RX_DATA__2_SEL_SFT 6
++#define MP_PHY2RX_DATA__2_SEL_HI 6
++#define MP_PHY2RX_DATA__2_SEL_SZ 1
++#define MP_PHY2RX_DATA__4_SEL_MSK 0x00000080
++#define MP_PHY2RX_DATA__4_SEL_I_MSK 0xffffff7f
++#define MP_PHY2RX_DATA__4_SEL_SFT 7
++#define MP_PHY2RX_DATA__4_SEL_HI 7
++#define MP_PHY2RX_DATA__4_SEL_SZ 1
++#define I2CM_SDA_ID_SEL_MSK 0x00000300
++#define I2CM_SDA_ID_SEL_I_MSK 0xfffffcff
++#define I2CM_SDA_ID_SEL_SFT 8
++#define I2CM_SDA_ID_SEL_HI 9
++#define I2CM_SDA_ID_SEL_SZ 2
++#define CRYSTAL_OUT_REQ_SEL_MSK 0x00000400
++#define CRYSTAL_OUT_REQ_SEL_I_MSK 0xfffffbff
++#define CRYSTAL_OUT_REQ_SEL_SFT 10
++#define CRYSTAL_OUT_REQ_SEL_HI 10
++#define CRYSTAL_OUT_REQ_SEL_SZ 1
++#define MP_PHY2RX_DATA__5_SEL_MSK 0x00000800
++#define MP_PHY2RX_DATA__5_SEL_I_MSK 0xfffff7ff
++#define MP_PHY2RX_DATA__5_SEL_SFT 11
++#define MP_PHY2RX_DATA__5_SEL_HI 11
++#define MP_PHY2RX_DATA__5_SEL_SZ 1
++#define MP_PHY2RX_DATA__3_SEL_MSK 0x00001000
++#define MP_PHY2RX_DATA__3_SEL_I_MSK 0xffffefff
++#define MP_PHY2RX_DATA__3_SEL_SFT 12
++#define MP_PHY2RX_DATA__3_SEL_HI 12
++#define MP_PHY2RX_DATA__3_SEL_SZ 1
++#define UART_RXD_SEL_MSK 0x00006000
++#define UART_RXD_SEL_I_MSK 0xffff9fff
++#define UART_RXD_SEL_SFT 13
++#define UART_RXD_SEL_HI 14
++#define UART_RXD_SEL_SZ 2
++#define MP_PHY2RX_DATA__6_SEL_MSK 0x00008000
++#define MP_PHY2RX_DATA__6_SEL_I_MSK 0xffff7fff
++#define MP_PHY2RX_DATA__6_SEL_SFT 15
++#define MP_PHY2RX_DATA__6_SEL_HI 15
++#define MP_PHY2RX_DATA__6_SEL_SZ 1
++#define DAT_UART_NCTS_SEL_MSK 0x00010000
++#define DAT_UART_NCTS_SEL_I_MSK 0xfffeffff
++#define DAT_UART_NCTS_SEL_SFT 16
++#define DAT_UART_NCTS_SEL_HI 16
++#define DAT_UART_NCTS_SEL_SZ 1
++#define GPIO_LOG_STOP_SEL_MSK 0x000e0000
++#define GPIO_LOG_STOP_SEL_I_MSK 0xfff1ffff
++#define GPIO_LOG_STOP_SEL_SFT 17
++#define GPIO_LOG_STOP_SEL_HI 19
++#define GPIO_LOG_STOP_SEL_SZ 3
++#define MP_TX_FF_RPTR__0_SEL_MSK 0x00100000
++#define MP_TX_FF_RPTR__0_SEL_I_MSK 0xffefffff
++#define MP_TX_FF_RPTR__0_SEL_SFT 20
++#define MP_TX_FF_RPTR__0_SEL_HI 20
++#define MP_TX_FF_RPTR__0_SEL_SZ 1
++#define MP_PHY_RX_WRST_N_SEL_MSK 0x00200000
++#define MP_PHY_RX_WRST_N_SEL_I_MSK 0xffdfffff
++#define MP_PHY_RX_WRST_N_SEL_SFT 21
++#define MP_PHY_RX_WRST_N_SEL_HI 21
++#define MP_PHY_RX_WRST_N_SEL_SZ 1
++#define EXT_32K_SEL_MSK 0x00c00000
++#define EXT_32K_SEL_I_MSK 0xff3fffff
++#define EXT_32K_SEL_SFT 22
++#define EXT_32K_SEL_HI 23
++#define EXT_32K_SEL_SZ 2
++#define MP_PHY2RX_DATA__7_SEL_MSK 0x01000000
++#define MP_PHY2RX_DATA__7_SEL_I_MSK 0xfeffffff
++#define MP_PHY2RX_DATA__7_SEL_SFT 24
++#define MP_PHY2RX_DATA__7_SEL_HI 24
++#define MP_PHY2RX_DATA__7_SEL_SZ 1
++#define MP_TX_FF_RPTR__2_SEL_MSK 0x02000000
++#define MP_TX_FF_RPTR__2_SEL_I_MSK 0xfdffffff
++#define MP_TX_FF_RPTR__2_SEL_SFT 25
++#define MP_TX_FF_RPTR__2_SEL_HI 25
++#define MP_TX_FF_RPTR__2_SEL_SZ 1
++#define PMUINT_WAKE_SEL_MSK 0x1c000000
++#define PMUINT_WAKE_SEL_I_MSK 0xe3ffffff
++#define PMUINT_WAKE_SEL_SFT 26
++#define PMUINT_WAKE_SEL_HI 28
++#define PMUINT_WAKE_SEL_SZ 3
++#define I2CM_SCL_ID_SEL_MSK 0x20000000
++#define I2CM_SCL_ID_SEL_I_MSK 0xdfffffff
++#define I2CM_SCL_ID_SEL_SFT 29
++#define I2CM_SCL_ID_SEL_HI 29
++#define I2CM_SCL_ID_SEL_SZ 1
++#define MP_MRX_RX_EN_SEL_MSK 0x40000000
++#define MP_MRX_RX_EN_SEL_I_MSK 0xbfffffff
++#define MP_MRX_RX_EN_SEL_SFT 30
++#define MP_MRX_RX_EN_SEL_HI 30
++#define MP_MRX_RX_EN_SEL_SZ 1
++#define DAT_UART_RXD_SEL_0_MSK 0x80000000
++#define DAT_UART_RXD_SEL_0_I_MSK 0x7fffffff
++#define DAT_UART_RXD_SEL_0_SFT 31
++#define DAT_UART_RXD_SEL_0_HI 31
++#define DAT_UART_RXD_SEL_0_SZ 1
++#define DAT_UART_RXD_SEL_1_MSK 0x00000001
++#define DAT_UART_RXD_SEL_1_I_MSK 0xfffffffe
++#define DAT_UART_RXD_SEL_1_SFT 0
++#define DAT_UART_RXD_SEL_1_HI 0
++#define DAT_UART_RXD_SEL_1_SZ 1
++#define SPI_DI_SEL_MSK 0x00000002
++#define SPI_DI_SEL_I_MSK 0xfffffffd
++#define SPI_DI_SEL_SFT 1
++#define SPI_DI_SEL_HI 1
++#define SPI_DI_SEL_SZ 1
++#define IO_PORT_REG_MSK 0x0001ffff
++#define IO_PORT_REG_I_MSK 0xfffe0000
++#define IO_PORT_REG_SFT 0
++#define IO_PORT_REG_HI 16
++#define IO_PORT_REG_SZ 17
++#define MASK_RX_INT_MSK 0x00000001
++#define MASK_RX_INT_I_MSK 0xfffffffe
++#define MASK_RX_INT_SFT 0
++#define MASK_RX_INT_HI 0
++#define MASK_RX_INT_SZ 1
++#define MASK_TX_INT_MSK 0x00000002
++#define MASK_TX_INT_I_MSK 0xfffffffd
++#define MASK_TX_INT_SFT 1
++#define MASK_TX_INT_HI 1
++#define MASK_TX_INT_SZ 1
++#define MASK_SOC_SYSTEM_INT_MSK 0x00000004
++#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb
++#define MASK_SOC_SYSTEM_INT_SFT 2
++#define MASK_SOC_SYSTEM_INT_HI 2
++#define MASK_SOC_SYSTEM_INT_SZ 1
++#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008
++#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7
++#define EDCA0_LOW_THR_INT_MASK_SFT 3
++#define EDCA0_LOW_THR_INT_MASK_HI 3
++#define EDCA0_LOW_THR_INT_MASK_SZ 1
++#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010
++#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef
++#define EDCA1_LOW_THR_INT_MASK_SFT 4
++#define EDCA1_LOW_THR_INT_MASK_HI 4
++#define EDCA1_LOW_THR_INT_MASK_SZ 1
++#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020
++#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf
++#define EDCA2_LOW_THR_INT_MASK_SFT 5
++#define EDCA2_LOW_THR_INT_MASK_HI 5
++#define EDCA2_LOW_THR_INT_MASK_SZ 1
++#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040
++#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf
++#define EDCA3_LOW_THR_INT_MASK_SFT 6
++#define EDCA3_LOW_THR_INT_MASK_HI 6
++#define EDCA3_LOW_THR_INT_MASK_SZ 1
++#define TX_LIMIT_INT_MASK_MSK 0x00000080
++#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f
++#define TX_LIMIT_INT_MASK_SFT 7
++#define TX_LIMIT_INT_MASK_HI 7
++#define TX_LIMIT_INT_MASK_SZ 1
++#define RX_INT_MSK 0x00000001
++#define RX_INT_I_MSK 0xfffffffe
++#define RX_INT_SFT 0
++#define RX_INT_HI 0
++#define RX_INT_SZ 1
++#define TX_COMPLETE_INT_MSK 0x00000002
++#define TX_COMPLETE_INT_I_MSK 0xfffffffd
++#define TX_COMPLETE_INT_SFT 1
++#define TX_COMPLETE_INT_HI 1
++#define TX_COMPLETE_INT_SZ 1
++#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004
++#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb
++#define SOC_SYSTEM_INT_STATUS_SFT 2
++#define SOC_SYSTEM_INT_STATUS_HI 2
++#define SOC_SYSTEM_INT_STATUS_SZ 1
++#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008
++#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7
++#define EDCA0_LOW_THR_INT_STS_SFT 3
++#define EDCA0_LOW_THR_INT_STS_HI 3
++#define EDCA0_LOW_THR_INT_STS_SZ 1
++#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010
++#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef
++#define EDCA1_LOW_THR_INT_STS_SFT 4
++#define EDCA1_LOW_THR_INT_STS_HI 4
++#define EDCA1_LOW_THR_INT_STS_SZ 1
++#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020
++#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf
++#define EDCA2_LOW_THR_INT_STS_SFT 5
++#define EDCA2_LOW_THR_INT_STS_HI 5
++#define EDCA2_LOW_THR_INT_STS_SZ 1
++#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040
++#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf
++#define EDCA3_LOW_THR_INT_STS_SFT 6
++#define EDCA3_LOW_THR_INT_STS_HI 6
++#define EDCA3_LOW_THR_INT_STS_SZ 1
++#define TX_LIMIT_INT_STS_MSK 0x00000080
++#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f
++#define TX_LIMIT_INT_STS_SFT 7
++#define TX_LIMIT_INT_STS_HI 7
++#define TX_LIMIT_INT_STS_SZ 1
++#define HOST_TRIGGERED_RX_INT_MSK 0x00000100
++#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff
++#define HOST_TRIGGERED_RX_INT_SFT 8
++#define HOST_TRIGGERED_RX_INT_HI 8
++#define HOST_TRIGGERED_RX_INT_SZ 1
++#define HOST_TRIGGERED_TX_INT_MSK 0x00000200
++#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff
++#define HOST_TRIGGERED_TX_INT_SFT 9
++#define HOST_TRIGGERED_TX_INT_HI 9
++#define HOST_TRIGGERED_TX_INT_SZ 1
++#define SOC_TRIGGER_RX_INT_MSK 0x00000400
++#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff
++#define SOC_TRIGGER_RX_INT_SFT 10
++#define SOC_TRIGGER_RX_INT_HI 10
++#define SOC_TRIGGER_RX_INT_SZ 1
++#define SOC_TRIGGER_TX_INT_MSK 0x00000800
++#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff
++#define SOC_TRIGGER_TX_INT_SFT 11
++#define SOC_TRIGGER_TX_INT_HI 11
++#define SOC_TRIGGER_TX_INT_SZ 1
++#define RDY_FOR_TX_RX_MSK 0x00000001
++#define RDY_FOR_TX_RX_I_MSK 0xfffffffe
++#define RDY_FOR_TX_RX_SFT 0
++#define RDY_FOR_TX_RX_HI 0
++#define RDY_FOR_TX_RX_SZ 1
++#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002
++#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd
++#define RDY_FOR_FW_DOWNLOAD_SFT 1
++#define RDY_FOR_FW_DOWNLOAD_HI 1
++#define RDY_FOR_FW_DOWNLOAD_SZ 1
++#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004
++#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb
++#define ILLEGAL_CMD_RESP_OPTION_SFT 2
++#define ILLEGAL_CMD_RESP_OPTION_HI 2
++#define ILLEGAL_CMD_RESP_OPTION_SZ 1
++#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008
++#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7
++#define SDIO_TRX_DATA_SEQUENCE_SFT 3
++#define SDIO_TRX_DATA_SEQUENCE_HI 3
++#define SDIO_TRX_DATA_SEQUENCE_SZ 1
++#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010
++#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef
++#define GPIO_INT_TRIGGER_OPTION_SFT 4
++#define GPIO_INT_TRIGGER_OPTION_HI 4
++#define GPIO_INT_TRIGGER_OPTION_SZ 1
++#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060
++#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f
++#define TRIGGER_FUNCTION_SETTING_SFT 5
++#define TRIGGER_FUNCTION_SETTING_HI 6
++#define TRIGGER_FUNCTION_SETTING_SZ 2
++#define CMD52_ABORT_RESPONSE_MSK 0x00000080
++#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f
++#define CMD52_ABORT_RESPONSE_SFT 7
++#define CMD52_ABORT_RESPONSE_HI 7
++#define CMD52_ABORT_RESPONSE_SZ 1
++#define RX_PACKET_LENGTH_MSK 0x0000ffff
++#define RX_PACKET_LENGTH_I_MSK 0xffff0000
++#define RX_PACKET_LENGTH_SFT 0
++#define RX_PACKET_LENGTH_HI 15
++#define RX_PACKET_LENGTH_SZ 16
++#define CARD_FW_DL_STATUS_MSK 0x00ff0000
++#define CARD_FW_DL_STATUS_I_MSK 0xff00ffff
++#define CARD_FW_DL_STATUS_SFT 16
++#define CARD_FW_DL_STATUS_HI 23
++#define CARD_FW_DL_STATUS_SZ 8
++#define TX_RX_LOOP_BACK_TEST_MSK 0x01000000
++#define TX_RX_LOOP_BACK_TEST_I_MSK 0xfeffffff
++#define TX_RX_LOOP_BACK_TEST_SFT 24
++#define TX_RX_LOOP_BACK_TEST_HI 24
++#define TX_RX_LOOP_BACK_TEST_SZ 1
++#define SDIO_LOOP_BACK_TEST_MSK 0x02000000
++#define SDIO_LOOP_BACK_TEST_I_MSK 0xfdffffff
++#define SDIO_LOOP_BACK_TEST_SFT 25
++#define SDIO_LOOP_BACK_TEST_HI 25
++#define SDIO_LOOP_BACK_TEST_SZ 1
++#define CMD52_ABORT_ACTIVE_MSK 0x10000000
++#define CMD52_ABORT_ACTIVE_I_MSK 0xefffffff
++#define CMD52_ABORT_ACTIVE_SFT 28
++#define CMD52_ABORT_ACTIVE_HI 28
++#define CMD52_ABORT_ACTIVE_SZ 1
++#define CMD52_RESET_ACTIVE_MSK 0x20000000
++#define CMD52_RESET_ACTIVE_I_MSK 0xdfffffff
++#define CMD52_RESET_ACTIVE_SFT 29
++#define CMD52_RESET_ACTIVE_HI 29
++#define CMD52_RESET_ACTIVE_SZ 1
++#define SDIO_PARTIAL_RESET_ACTIVE_MSK 0x40000000
++#define SDIO_PARTIAL_RESET_ACTIVE_I_MSK 0xbfffffff
++#define SDIO_PARTIAL_RESET_ACTIVE_SFT 30
++#define SDIO_PARTIAL_RESET_ACTIVE_HI 30
++#define SDIO_PARTIAL_RESET_ACTIVE_SZ 1
++#define SDIO_ALL_RESE_ACTIVE_MSK 0x80000000
++#define SDIO_ALL_RESE_ACTIVE_I_MSK 0x7fffffff
++#define SDIO_ALL_RESE_ACTIVE_SFT 31
++#define SDIO_ALL_RESE_ACTIVE_HI 31
++#define SDIO_ALL_RESE_ACTIVE_SZ 1
++#define RX_PACKET_LENGTH2_MSK 0x0000ffff
++#define RX_PACKET_LENGTH2_I_MSK 0xffff0000
++#define RX_PACKET_LENGTH2_SFT 0
++#define RX_PACKET_LENGTH2_HI 15
++#define RX_PACKET_LENGTH2_SZ 16
++#define RX_INT1_MSK 0x00010000
++#define RX_INT1_I_MSK 0xfffeffff
++#define RX_INT1_SFT 16
++#define RX_INT1_HI 16
++#define RX_INT1_SZ 1
++#define TX_DONE_MSK 0x00020000
++#define TX_DONE_I_MSK 0xfffdffff
++#define TX_DONE_SFT 17
++#define TX_DONE_HI 17
++#define TX_DONE_SZ 1
++#define HCI_TRX_FINISH_MSK 0x00040000
++#define HCI_TRX_FINISH_I_MSK 0xfffbffff
++#define HCI_TRX_FINISH_SFT 18
++#define HCI_TRX_FINISH_HI 18
++#define HCI_TRX_FINISH_SZ 1
++#define ALLOCATE_STATUS_MSK 0x00080000
++#define ALLOCATE_STATUS_I_MSK 0xfff7ffff
++#define ALLOCATE_STATUS_SFT 19
++#define ALLOCATE_STATUS_HI 19
++#define ALLOCATE_STATUS_SZ 1
++#define HCI_INPUT_FF_CNT_MSK 0x00f00000
++#define HCI_INPUT_FF_CNT_I_MSK 0xff0fffff
++#define HCI_INPUT_FF_CNT_SFT 20
++#define HCI_INPUT_FF_CNT_HI 23
++#define HCI_INPUT_FF_CNT_SZ 4
++#define HCI_OUTPUT_FF_CNT_MSK 0x1f000000
++#define HCI_OUTPUT_FF_CNT_I_MSK 0xe0ffffff
++#define HCI_OUTPUT_FF_CNT_SFT 24
++#define HCI_OUTPUT_FF_CNT_HI 28
++#define HCI_OUTPUT_FF_CNT_SZ 5
++#define AHB_HANG4_MSK 0x20000000
++#define AHB_HANG4_I_MSK 0xdfffffff
++#define AHB_HANG4_SFT 29
++#define AHB_HANG4_HI 29
++#define AHB_HANG4_SZ 1
++#define HCI_IN_QUE_EMPTY_MSK 0x40000000
++#define HCI_IN_QUE_EMPTY_I_MSK 0xbfffffff
++#define HCI_IN_QUE_EMPTY_SFT 30
++#define HCI_IN_QUE_EMPTY_HI 30
++#define HCI_IN_QUE_EMPTY_SZ 1
++#define SYSTEM_INT_MSK 0x80000000
++#define SYSTEM_INT_I_MSK 0x7fffffff
++#define SYSTEM_INT_SFT 31
++#define SYSTEM_INT_HI 31
++#define SYSTEM_INT_SZ 1
++#define CARD_RCA_REG_MSK 0x0000ffff
++#define CARD_RCA_REG_I_MSK 0xffff0000
++#define CARD_RCA_REG_SFT 0
++#define CARD_RCA_REG_HI 15
++#define CARD_RCA_REG_SZ 16
++#define SDIO_FIFO_WR_THLD_REG_MSK 0x000001ff
++#define SDIO_FIFO_WR_THLD_REG_I_MSK 0xfffffe00
++#define SDIO_FIFO_WR_THLD_REG_SFT 0
++#define SDIO_FIFO_WR_THLD_REG_HI 8
++#define SDIO_FIFO_WR_THLD_REG_SZ 9
++#define SDIO_FIFO_WR_LIMIT_REG_MSK 0x000001ff
++#define SDIO_FIFO_WR_LIMIT_REG_I_MSK 0xfffffe00
++#define SDIO_FIFO_WR_LIMIT_REG_SFT 0
++#define SDIO_FIFO_WR_LIMIT_REG_HI 8
++#define SDIO_FIFO_WR_LIMIT_REG_SZ 9
++#define SDIO_TX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
++#define SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
++#define SDIO_TX_DATA_BATCH_SIZE_REG_SFT 0
++#define SDIO_TX_DATA_BATCH_SIZE_REG_HI 8
++#define SDIO_TX_DATA_BATCH_SIZE_REG_SZ 9
++#define SDIO_THLD_FOR_CMD53RD_REG_MSK 0x000001ff
++#define SDIO_THLD_FOR_CMD53RD_REG_I_MSK 0xfffffe00
++#define SDIO_THLD_FOR_CMD53RD_REG_SFT 0
++#define SDIO_THLD_FOR_CMD53RD_REG_HI 8
++#define SDIO_THLD_FOR_CMD53RD_REG_SZ 9
++#define SDIO_RX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
++#define SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
++#define SDIO_RX_DATA_BATCH_SIZE_REG_SFT 0
++#define SDIO_RX_DATA_BATCH_SIZE_REG_HI 8
++#define SDIO_RX_DATA_BATCH_SIZE_REG_SZ 9
++#define START_BYTE_VALUE_MSK 0x000000ff
++#define START_BYTE_VALUE_I_MSK 0xffffff00
++#define START_BYTE_VALUE_SFT 0
++#define START_BYTE_VALUE_HI 7
++#define START_BYTE_VALUE_SZ 8
++#define END_BYTE_VALUE_MSK 0x0000ff00
++#define END_BYTE_VALUE_I_MSK 0xffff00ff
++#define END_BYTE_VALUE_SFT 8
++#define END_BYTE_VALUE_HI 15
++#define END_BYTE_VALUE_SZ 8
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8
++#define SDIO_LAST_CMD_INDEX_REG_MSK 0x0000003f
++#define SDIO_LAST_CMD_INDEX_REG_I_MSK 0xffffffc0
++#define SDIO_LAST_CMD_INDEX_REG_SFT 0
++#define SDIO_LAST_CMD_INDEX_REG_HI 5
++#define SDIO_LAST_CMD_INDEX_REG_SZ 6
++#define SDIO_LAST_CMD_CRC_REG_MSK 0x00007f00
++#define SDIO_LAST_CMD_CRC_REG_I_MSK 0xffff80ff
++#define SDIO_LAST_CMD_CRC_REG_SFT 8
++#define SDIO_LAST_CMD_CRC_REG_HI 14
++#define SDIO_LAST_CMD_CRC_REG_SZ 7
++#define SDIO_LAST_CMD_ARG_REG_MSK 0xffffffff
++#define SDIO_LAST_CMD_ARG_REG_I_MSK 0x00000000
++#define SDIO_LAST_CMD_ARG_REG_SFT 0
++#define SDIO_LAST_CMD_ARG_REG_HI 31
++#define SDIO_LAST_CMD_ARG_REG_SZ 32
++#define SDIO_BUS_STATE_REG_MSK 0x0000001f
++#define SDIO_BUS_STATE_REG_I_MSK 0xffffffe0
++#define SDIO_BUS_STATE_REG_SFT 0
++#define SDIO_BUS_STATE_REG_HI 4
++#define SDIO_BUS_STATE_REG_SZ 5
++#define SDIO_BUSY_LONG_CNT_MSK 0xffff0000
++#define SDIO_BUSY_LONG_CNT_I_MSK 0x0000ffff
++#define SDIO_BUSY_LONG_CNT_SFT 16
++#define SDIO_BUSY_LONG_CNT_HI 31
++#define SDIO_BUSY_LONG_CNT_SZ 16
++#define SDIO_CARD_STATUS_REG_MSK 0xffffffff
++#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000
++#define SDIO_CARD_STATUS_REG_SFT 0
++#define SDIO_CARD_STATUS_REG_HI 31
++#define SDIO_CARD_STATUS_REG_SZ 32
++#define R5_RESPONSE_FLAG_MSK 0x000000ff
++#define R5_RESPONSE_FLAG_I_MSK 0xffffff00
++#define R5_RESPONSE_FLAG_SFT 0
++#define R5_RESPONSE_FLAG_HI 7
++#define R5_RESPONSE_FLAG_SZ 8
++#define RESP_OUT_EDGE_MSK 0x00000100
++#define RESP_OUT_EDGE_I_MSK 0xfffffeff
++#define RESP_OUT_EDGE_SFT 8
++#define RESP_OUT_EDGE_HI 8
++#define RESP_OUT_EDGE_SZ 1
++#define DAT_OUT_EDGE_MSK 0x00000200
++#define DAT_OUT_EDGE_I_MSK 0xfffffdff
++#define DAT_OUT_EDGE_SFT 9
++#define DAT_OUT_EDGE_HI 9
++#define DAT_OUT_EDGE_SZ 1
++#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000
++#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff
++#define MCU_TO_SDIO_INFO_MASK_SFT 16
++#define MCU_TO_SDIO_INFO_MASK_HI 16
++#define MCU_TO_SDIO_INFO_MASK_SZ 1
++#define INT_THROUGH_PIN_MSK 0x00020000
++#define INT_THROUGH_PIN_I_MSK 0xfffdffff
++#define INT_THROUGH_PIN_SFT 17
++#define INT_THROUGH_PIN_HI 17
++#define INT_THROUGH_PIN_SZ 1
++#define WRITE_DATA_MSK 0x000000ff
++#define WRITE_DATA_I_MSK 0xffffff00
++#define WRITE_DATA_SFT 0
++#define WRITE_DATA_HI 7
++#define WRITE_DATA_SZ 8
++#define WRITE_ADDRESS_MSK 0x0000ff00
++#define WRITE_ADDRESS_I_MSK 0xffff00ff
++#define WRITE_ADDRESS_SFT 8
++#define WRITE_ADDRESS_HI 15
++#define WRITE_ADDRESS_SZ 8
++#define READ_DATA_MSK 0x00ff0000
++#define READ_DATA_I_MSK 0xff00ffff
++#define READ_DATA_SFT 16
++#define READ_DATA_HI 23
++#define READ_DATA_SZ 8
++#define READ_ADDRESS_MSK 0xff000000
++#define READ_ADDRESS_I_MSK 0x00ffffff
++#define READ_ADDRESS_SFT 24
++#define READ_ADDRESS_HI 31
++#define READ_ADDRESS_SZ 8
++#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff
++#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000
++#define FN1_DMA_START_ADDR_REG_SFT 0
++#define FN1_DMA_START_ADDR_REG_HI 31
++#define FN1_DMA_START_ADDR_REG_SZ 32
++#define SDIO_TO_MCU_INFO_MSK 0x000000ff
++#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00
++#define SDIO_TO_MCU_INFO_SFT 0
++#define SDIO_TO_MCU_INFO_HI 7
++#define SDIO_TO_MCU_INFO_SZ 8
++#define SDIO_PARTIAL_RESET_MSK 0x00000100
++#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff
++#define SDIO_PARTIAL_RESET_SFT 8
++#define SDIO_PARTIAL_RESET_HI 8
++#define SDIO_PARTIAL_RESET_SZ 1
++#define SDIO_ALL_RESET_MSK 0x00000200
++#define SDIO_ALL_RESET_I_MSK 0xfffffdff
++#define SDIO_ALL_RESET_SFT 9
++#define SDIO_ALL_RESET_HI 9
++#define SDIO_ALL_RESET_SZ 1
++#define PERI_MAC_ALL_RESET_MSK 0x00000400
++#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff
++#define PERI_MAC_ALL_RESET_SFT 10
++#define PERI_MAC_ALL_RESET_HI 10
++#define PERI_MAC_ALL_RESET_SZ 1
++#define MAC_ALL_RESET_MSK 0x00000800
++#define MAC_ALL_RESET_I_MSK 0xfffff7ff
++#define MAC_ALL_RESET_SFT 11
++#define MAC_ALL_RESET_HI 11
++#define MAC_ALL_RESET_SZ 1
++#define AHB_BRIDGE_RESET_MSK 0x00001000
++#define AHB_BRIDGE_RESET_I_MSK 0xffffefff
++#define AHB_BRIDGE_RESET_SFT 12
++#define AHB_BRIDGE_RESET_HI 12
++#define AHB_BRIDGE_RESET_SZ 1
++#define IO_REG_PORT_REG_MSK 0x0001ffff
++#define IO_REG_PORT_REG_I_MSK 0xfffe0000
++#define IO_REG_PORT_REG_SFT 0
++#define IO_REG_PORT_REG_HI 16
++#define IO_REG_PORT_REG_SZ 17
++#define SDIO_FIFO_EMPTY_CNT_MSK 0x0000ffff
++#define SDIO_FIFO_EMPTY_CNT_I_MSK 0xffff0000
++#define SDIO_FIFO_EMPTY_CNT_SFT 0
++#define SDIO_FIFO_EMPTY_CNT_HI 15
++#define SDIO_FIFO_EMPTY_CNT_SZ 16
++#define SDIO_FIFO_FULL_CNT_MSK 0xffff0000
++#define SDIO_FIFO_FULL_CNT_I_MSK 0x0000ffff
++#define SDIO_FIFO_FULL_CNT_SFT 16
++#define SDIO_FIFO_FULL_CNT_HI 31
++#define SDIO_FIFO_FULL_CNT_SZ 16
++#define SDIO_CRC7_ERROR_CNT_MSK 0x0000ffff
++#define SDIO_CRC7_ERROR_CNT_I_MSK 0xffff0000
++#define SDIO_CRC7_ERROR_CNT_SFT 0
++#define SDIO_CRC7_ERROR_CNT_HI 15
++#define SDIO_CRC7_ERROR_CNT_SZ 16
++#define SDIO_CRC16_ERROR_CNT_MSK 0xffff0000
++#define SDIO_CRC16_ERROR_CNT_I_MSK 0x0000ffff
++#define SDIO_CRC16_ERROR_CNT_SFT 16
++#define SDIO_CRC16_ERROR_CNT_HI 31
++#define SDIO_CRC16_ERROR_CNT_SZ 16
++#define SDIO_RD_BLOCK_CNT_MSK 0x000001ff
++#define SDIO_RD_BLOCK_CNT_I_MSK 0xfffffe00
++#define SDIO_RD_BLOCK_CNT_SFT 0
++#define SDIO_RD_BLOCK_CNT_HI 8
++#define SDIO_RD_BLOCK_CNT_SZ 9
++#define SDIO_WR_BLOCK_CNT_MSK 0x01ff0000
++#define SDIO_WR_BLOCK_CNT_I_MSK 0xfe00ffff
++#define SDIO_WR_BLOCK_CNT_SFT 16
++#define SDIO_WR_BLOCK_CNT_HI 24
++#define SDIO_WR_BLOCK_CNT_SZ 9
++#define CMD52_RD_ABORT_CNT_MSK 0x000f0000
++#define CMD52_RD_ABORT_CNT_I_MSK 0xfff0ffff
++#define CMD52_RD_ABORT_CNT_SFT 16
++#define CMD52_RD_ABORT_CNT_HI 19
++#define CMD52_RD_ABORT_CNT_SZ 4
++#define CMD52_WR_ABORT_CNT_MSK 0x00f00000
++#define CMD52_WR_ABORT_CNT_I_MSK 0xff0fffff
++#define CMD52_WR_ABORT_CNT_SFT 20
++#define CMD52_WR_ABORT_CNT_HI 23
++#define CMD52_WR_ABORT_CNT_SZ 4
++#define SDIO_FIFO_WR_PTR_REG_MSK 0x000000ff
++#define SDIO_FIFO_WR_PTR_REG_I_MSK 0xffffff00
++#define SDIO_FIFO_WR_PTR_REG_SFT 0
++#define SDIO_FIFO_WR_PTR_REG_HI 7
++#define SDIO_FIFO_WR_PTR_REG_SZ 8
++#define SDIO_FIFO_RD_PTR_REG_MSK 0x0000ff00
++#define SDIO_FIFO_RD_PTR_REG_I_MSK 0xffff00ff
++#define SDIO_FIFO_RD_PTR_REG_SFT 8
++#define SDIO_FIFO_RD_PTR_REG_HI 15
++#define SDIO_FIFO_RD_PTR_REG_SZ 8
++#define SDIO_READ_DATA_CTRL_MSK 0x00010000
++#define SDIO_READ_DATA_CTRL_I_MSK 0xfffeffff
++#define SDIO_READ_DATA_CTRL_SFT 16
++#define SDIO_READ_DATA_CTRL_HI 16
++#define SDIO_READ_DATA_CTRL_SZ 1
++#define TX_SIZE_BEFORE_SHIFT_MSK 0x000000ff
++#define TX_SIZE_BEFORE_SHIFT_I_MSK 0xffffff00
++#define TX_SIZE_BEFORE_SHIFT_SFT 0
++#define TX_SIZE_BEFORE_SHIFT_HI 7
++#define TX_SIZE_BEFORE_SHIFT_SZ 8
++#define TX_SIZE_SHIFT_BITS_MSK 0x00000700
++#define TX_SIZE_SHIFT_BITS_I_MSK 0xfffff8ff
++#define TX_SIZE_SHIFT_BITS_SFT 8
++#define TX_SIZE_SHIFT_BITS_HI 10
++#define TX_SIZE_SHIFT_BITS_SZ 3
++#define SDIO_TX_ALLOC_STATE_MSK 0x00001000
++#define SDIO_TX_ALLOC_STATE_I_MSK 0xffffefff
++#define SDIO_TX_ALLOC_STATE_SFT 12
++#define SDIO_TX_ALLOC_STATE_HI 12
++#define SDIO_TX_ALLOC_STATE_SZ 1
++#define ALLOCATE_STATUS2_MSK 0x00010000
++#define ALLOCATE_STATUS2_I_MSK 0xfffeffff
++#define ALLOCATE_STATUS2_SFT 16
++#define ALLOCATE_STATUS2_HI 16
++#define ALLOCATE_STATUS2_SZ 1
++#define NO_ALLOCATE_SEND_ERROR_MSK 0x00020000
++#define NO_ALLOCATE_SEND_ERROR_I_MSK 0xfffdffff
++#define NO_ALLOCATE_SEND_ERROR_SFT 17
++#define NO_ALLOCATE_SEND_ERROR_HI 17
++#define NO_ALLOCATE_SEND_ERROR_SZ 1
++#define DOUBLE_ALLOCATE_ERROR_MSK 0x00040000
++#define DOUBLE_ALLOCATE_ERROR_I_MSK 0xfffbffff
++#define DOUBLE_ALLOCATE_ERROR_SFT 18
++#define DOUBLE_ALLOCATE_ERROR_HI 18
++#define DOUBLE_ALLOCATE_ERROR_SZ 1
++#define TX_DONE_STATUS_MSK 0x00080000
++#define TX_DONE_STATUS_I_MSK 0xfff7ffff
++#define TX_DONE_STATUS_SFT 19
++#define TX_DONE_STATUS_HI 19
++#define TX_DONE_STATUS_SZ 1
++#define AHB_HANG2_MSK 0x00100000
++#define AHB_HANG2_I_MSK 0xffefffff
++#define AHB_HANG2_SFT 20
++#define AHB_HANG2_HI 20
++#define AHB_HANG2_SZ 1
++#define HCI_TRX_FINISH2_MSK 0x00200000
++#define HCI_TRX_FINISH2_I_MSK 0xffdfffff
++#define HCI_TRX_FINISH2_SFT 21
++#define HCI_TRX_FINISH2_HI 21
++#define HCI_TRX_FINISH2_SZ 1
++#define INTR_RX_MSK 0x00400000
++#define INTR_RX_I_MSK 0xffbfffff
++#define INTR_RX_SFT 22
++#define INTR_RX_HI 22
++#define INTR_RX_SZ 1
++#define HCI_INPUT_QUEUE_FULL_MSK 0x00800000
++#define HCI_INPUT_QUEUE_FULL_I_MSK 0xff7fffff
++#define HCI_INPUT_QUEUE_FULL_SFT 23
++#define HCI_INPUT_QUEUE_FULL_HI 23
++#define HCI_INPUT_QUEUE_FULL_SZ 1
++#define ALLOCATESTATUS_MSK 0x00000001
++#define ALLOCATESTATUS_I_MSK 0xfffffffe
++#define ALLOCATESTATUS_SFT 0
++#define ALLOCATESTATUS_HI 0
++#define ALLOCATESTATUS_SZ 1
++#define HCI_TRX_FINISH3_MSK 0x00000002
++#define HCI_TRX_FINISH3_I_MSK 0xfffffffd
++#define HCI_TRX_FINISH3_SFT 1
++#define HCI_TRX_FINISH3_HI 1
++#define HCI_TRX_FINISH3_SZ 1
++#define HCI_IN_QUE_EMPTY2_MSK 0x00000004
++#define HCI_IN_QUE_EMPTY2_I_MSK 0xfffffffb
++#define HCI_IN_QUE_EMPTY2_SFT 2
++#define HCI_IN_QUE_EMPTY2_HI 2
++#define HCI_IN_QUE_EMPTY2_SZ 1
++#define MTX_MNG_UPTHOLD_INT_MSK 0x00000008
++#define MTX_MNG_UPTHOLD_INT_I_MSK 0xfffffff7
++#define MTX_MNG_UPTHOLD_INT_SFT 3
++#define MTX_MNG_UPTHOLD_INT_HI 3
++#define MTX_MNG_UPTHOLD_INT_SZ 1
++#define EDCA0_UPTHOLD_INT_MSK 0x00000010
++#define EDCA0_UPTHOLD_INT_I_MSK 0xffffffef
++#define EDCA0_UPTHOLD_INT_SFT 4
++#define EDCA0_UPTHOLD_INT_HI 4
++#define EDCA0_UPTHOLD_INT_SZ 1
++#define EDCA1_UPTHOLD_INT_MSK 0x00000020
++#define EDCA1_UPTHOLD_INT_I_MSK 0xffffffdf
++#define EDCA1_UPTHOLD_INT_SFT 5
++#define EDCA1_UPTHOLD_INT_HI 5
++#define EDCA1_UPTHOLD_INT_SZ 1
++#define EDCA2_UPTHOLD_INT_MSK 0x00000040
++#define EDCA2_UPTHOLD_INT_I_MSK 0xffffffbf
++#define EDCA2_UPTHOLD_INT_SFT 6
++#define EDCA2_UPTHOLD_INT_HI 6
++#define EDCA2_UPTHOLD_INT_SZ 1
++#define EDCA3_UPTHOLD_INT_MSK 0x00000080
++#define EDCA3_UPTHOLD_INT_I_MSK 0xffffff7f
++#define EDCA3_UPTHOLD_INT_SFT 7
++#define EDCA3_UPTHOLD_INT_HI 7
++#define EDCA3_UPTHOLD_INT_SZ 1
++#define TX_PAGE_REMAIN2_MSK 0x0000ff00
++#define TX_PAGE_REMAIN2_I_MSK 0xffff00ff
++#define TX_PAGE_REMAIN2_SFT 8
++#define TX_PAGE_REMAIN2_HI 15
++#define TX_PAGE_REMAIN2_SZ 8
++#define TX_ID_REMAIN3_MSK 0x007f0000
++#define TX_ID_REMAIN3_I_MSK 0xff80ffff
++#define TX_ID_REMAIN3_SFT 16
++#define TX_ID_REMAIN3_HI 22
++#define TX_ID_REMAIN3_SZ 7
++#define HCI_OUTPUT_FF_CNT_0_MSK 0x00800000
++#define HCI_OUTPUT_FF_CNT_0_I_MSK 0xff7fffff
++#define HCI_OUTPUT_FF_CNT_0_SFT 23
++#define HCI_OUTPUT_FF_CNT_0_HI 23
++#define HCI_OUTPUT_FF_CNT_0_SZ 1
++#define HCI_OUTPUT_FF_CNT2_MSK 0x0f000000
++#define HCI_OUTPUT_FF_CNT2_I_MSK 0xf0ffffff
++#define HCI_OUTPUT_FF_CNT2_SFT 24
++#define HCI_OUTPUT_FF_CNT2_HI 27
++#define HCI_OUTPUT_FF_CNT2_SZ 4
++#define HCI_INPUT_FF_CNT2_MSK 0xf0000000
++#define HCI_INPUT_FF_CNT2_I_MSK 0x0fffffff
++#define HCI_INPUT_FF_CNT2_SFT 28
++#define HCI_INPUT_FF_CNT2_HI 31
++#define HCI_INPUT_FF_CNT2_SZ 4
++#define F1_BLOCK_SIZE_0_REG_MSK 0x00000fff
++#define F1_BLOCK_SIZE_0_REG_I_MSK 0xfffff000
++#define F1_BLOCK_SIZE_0_REG_SFT 0
++#define F1_BLOCK_SIZE_0_REG_HI 11
++#define F1_BLOCK_SIZE_0_REG_SZ 12
++#define START_BYTE_VALUE2_MSK 0x000000ff
++#define START_BYTE_VALUE2_I_MSK 0xffffff00
++#define START_BYTE_VALUE2_SFT 0
++#define START_BYTE_VALUE2_HI 7
++#define START_BYTE_VALUE2_SZ 8
++#define COMMAND_COUNTER_MSK 0x0000ff00
++#define COMMAND_COUNTER_I_MSK 0xffff00ff
++#define COMMAND_COUNTER_SFT 8
++#define COMMAND_COUNTER_HI 15
++#define COMMAND_COUNTER_SZ 8
++#define CMD_LOG_PART1_MSK 0xffff0000
++#define CMD_LOG_PART1_I_MSK 0x0000ffff
++#define CMD_LOG_PART1_SFT 16
++#define CMD_LOG_PART1_HI 31
++#define CMD_LOG_PART1_SZ 16
++#define CMD_LOG_PART2_MSK 0x00ffffff
++#define CMD_LOG_PART2_I_MSK 0xff000000
++#define CMD_LOG_PART2_SFT 0
++#define CMD_LOG_PART2_HI 23
++#define CMD_LOG_PART2_SZ 24
++#define END_BYTE_VALUE2_MSK 0xff000000
++#define END_BYTE_VALUE2_I_MSK 0x00ffffff
++#define END_BYTE_VALUE2_SFT 24
++#define END_BYTE_VALUE2_HI 31
++#define END_BYTE_VALUE2_SZ 8
++#define RX_PACKET_LENGTH3_MSK 0x0000ffff
++#define RX_PACKET_LENGTH3_I_MSK 0xffff0000
++#define RX_PACKET_LENGTH3_SFT 0
++#define RX_PACKET_LENGTH3_HI 15
++#define RX_PACKET_LENGTH3_SZ 16
++#define RX_INT3_MSK 0x00010000
++#define RX_INT3_I_MSK 0xfffeffff
++#define RX_INT3_SFT 16
++#define RX_INT3_HI 16
++#define RX_INT3_SZ 1
++#define TX_ID_REMAIN2_MSK 0x00fe0000
++#define TX_ID_REMAIN2_I_MSK 0xff01ffff
++#define TX_ID_REMAIN2_SFT 17
++#define TX_ID_REMAIN2_HI 23
++#define TX_ID_REMAIN2_SZ 7
++#define TX_PAGE_REMAIN3_MSK 0xff000000
++#define TX_PAGE_REMAIN3_I_MSK 0x00ffffff
++#define TX_PAGE_REMAIN3_SFT 24
++#define TX_PAGE_REMAIN3_HI 31
++#define TX_PAGE_REMAIN3_SZ 8
++#define CCCR_00H_REG_MSK 0x000000ff
++#define CCCR_00H_REG_I_MSK 0xffffff00
++#define CCCR_00H_REG_SFT 0
++#define CCCR_00H_REG_HI 7
++#define CCCR_00H_REG_SZ 8
++#define CCCR_02H_REG_MSK 0x00ff0000
++#define CCCR_02H_REG_I_MSK 0xff00ffff
++#define CCCR_02H_REG_SFT 16
++#define CCCR_02H_REG_HI 23
++#define CCCR_02H_REG_SZ 8
++#define CCCR_03H_REG_MSK 0xff000000
++#define CCCR_03H_REG_I_MSK 0x00ffffff
++#define CCCR_03H_REG_SFT 24
++#define CCCR_03H_REG_HI 31
++#define CCCR_03H_REG_SZ 8
++#define CCCR_04H_REG_MSK 0x000000ff
++#define CCCR_04H_REG_I_MSK 0xffffff00
++#define CCCR_04H_REG_SFT 0
++#define CCCR_04H_REG_HI 7
++#define CCCR_04H_REG_SZ 8
++#define CCCR_05H_REG_MSK 0x0000ff00
++#define CCCR_05H_REG_I_MSK 0xffff00ff
++#define CCCR_05H_REG_SFT 8
++#define CCCR_05H_REG_HI 15
++#define CCCR_05H_REG_SZ 8
++#define CCCR_06H_REG_MSK 0x000f0000
++#define CCCR_06H_REG_I_MSK 0xfff0ffff
++#define CCCR_06H_REG_SFT 16
++#define CCCR_06H_REG_HI 19
++#define CCCR_06H_REG_SZ 4
++#define CCCR_07H_REG_MSK 0xff000000
++#define CCCR_07H_REG_I_MSK 0x00ffffff
++#define CCCR_07H_REG_SFT 24
++#define CCCR_07H_REG_HI 31
++#define CCCR_07H_REG_SZ 8
++#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001
++#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe
++#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0
++#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0
++#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1
++#define SUPPORT_READ_WAIT_MSK 0x00000004
++#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb
++#define SUPPORT_READ_WAIT_SFT 2
++#define SUPPORT_READ_WAIT_HI 2
++#define SUPPORT_READ_WAIT_SZ 1
++#define SUPPORT_BUS_CONTROL_MSK 0x00000008
++#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7
++#define SUPPORT_BUS_CONTROL_SFT 3
++#define SUPPORT_BUS_CONTROL_HI 3
++#define SUPPORT_BUS_CONTROL_SZ 1
++#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010
++#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef
++#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4
++#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4
++#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1
++#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020
++#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf
++#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5
++#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5
++#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1
++#define LOW_SPEED_CARD_MSK 0x00000040
++#define LOW_SPEED_CARD_I_MSK 0xffffffbf
++#define LOW_SPEED_CARD_SFT 6
++#define LOW_SPEED_CARD_HI 6
++#define LOW_SPEED_CARD_SZ 1
++#define LOW_SPEED_CARD_4BIT_MSK 0x00000080
++#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f
++#define LOW_SPEED_CARD_4BIT_SFT 7
++#define LOW_SPEED_CARD_4BIT_HI 7
++#define LOW_SPEED_CARD_4BIT_SZ 1
++#define COMMON_CIS_PONTER_MSK 0x01ffff00
++#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff
++#define COMMON_CIS_PONTER_SFT 8
++#define COMMON_CIS_PONTER_HI 24
++#define COMMON_CIS_PONTER_SZ 17
++#define SUPPORT_HIGH_SPEED_MSK 0x01000000
++#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff
++#define SUPPORT_HIGH_SPEED_SFT 24
++#define SUPPORT_HIGH_SPEED_HI 24
++#define SUPPORT_HIGH_SPEED_SZ 1
++#define BSS_MSK 0x0e000000
++#define BSS_I_MSK 0xf1ffffff
++#define BSS_SFT 25
++#define BSS_HI 27
++#define BSS_SZ 3
++#define FBR_100H_REG_MSK 0x0000000f
++#define FBR_100H_REG_I_MSK 0xfffffff0
++#define FBR_100H_REG_SFT 0
++#define FBR_100H_REG_HI 3
++#define FBR_100H_REG_SZ 4
++#define CSASUPPORT_MSK 0x00000040
++#define CSASUPPORT_I_MSK 0xffffffbf
++#define CSASUPPORT_SFT 6
++#define CSASUPPORT_HI 6
++#define CSASUPPORT_SZ 1
++#define ENABLECSA_MSK 0x00000080
++#define ENABLECSA_I_MSK 0xffffff7f
++#define ENABLECSA_SFT 7
++#define ENABLECSA_HI 7
++#define ENABLECSA_SZ 1
++#define FBR_101H_REG_MSK 0x0000ff00
++#define FBR_101H_REG_I_MSK 0xffff00ff
++#define FBR_101H_REG_SFT 8
++#define FBR_101H_REG_HI 15
++#define FBR_101H_REG_SZ 8
++#define FBR_109H_REG_MSK 0x01ffff00
++#define FBR_109H_REG_I_MSK 0xfe0000ff
++#define FBR_109H_REG_SFT 8
++#define FBR_109H_REG_HI 24
++#define FBR_109H_REG_SZ 17
++#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_31_0_SFT 0
++#define F0_CIS_CONTENT_REG_31_0_HI 31
++#define F0_CIS_CONTENT_REG_31_0_SZ 32
++#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_63_32_SFT 0
++#define F0_CIS_CONTENT_REG_63_32_HI 31
++#define F0_CIS_CONTENT_REG_63_32_SZ 32
++#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_95_64_SFT 0
++#define F0_CIS_CONTENT_REG_95_64_HI 31
++#define F0_CIS_CONTENT_REG_95_64_SZ 32
++#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_127_96_SFT 0
++#define F0_CIS_CONTENT_REG_127_96_HI 31
++#define F0_CIS_CONTENT_REG_127_96_SZ 32
++#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_159_128_SFT 0
++#define F0_CIS_CONTENT_REG_159_128_HI 31
++#define F0_CIS_CONTENT_REG_159_128_SZ 32
++#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_191_160_SFT 0
++#define F0_CIS_CONTENT_REG_191_160_HI 31
++#define F0_CIS_CONTENT_REG_191_160_SZ 32
++#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_223_192_SFT 0
++#define F0_CIS_CONTENT_REG_223_192_HI 31
++#define F0_CIS_CONTENT_REG_223_192_SZ 32
++#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_255_224_SFT 0
++#define F0_CIS_CONTENT_REG_255_224_HI 31
++#define F0_CIS_CONTENT_REG_255_224_SZ 32
++#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_287_256_SFT 0
++#define F0_CIS_CONTENT_REG_287_256_HI 31
++#define F0_CIS_CONTENT_REG_287_256_SZ 32
++#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_319_288_SFT 0
++#define F0_CIS_CONTENT_REG_319_288_HI 31
++#define F0_CIS_CONTENT_REG_319_288_SZ 32
++#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_351_320_SFT 0
++#define F0_CIS_CONTENT_REG_351_320_HI 31
++#define F0_CIS_CONTENT_REG_351_320_SZ 32
++#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_383_352_SFT 0
++#define F0_CIS_CONTENT_REG_383_352_HI 31
++#define F0_CIS_CONTENT_REG_383_352_SZ 32
++#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_415_384_SFT 0
++#define F0_CIS_CONTENT_REG_415_384_HI 31
++#define F0_CIS_CONTENT_REG_415_384_SZ 32
++#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_447_416_SFT 0
++#define F0_CIS_CONTENT_REG_447_416_HI 31
++#define F0_CIS_CONTENT_REG_447_416_SZ 32
++#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_479_448_SFT 0
++#define F0_CIS_CONTENT_REG_479_448_HI 31
++#define F0_CIS_CONTENT_REG_479_448_SZ 32
++#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_511_480_SFT 0
++#define F0_CIS_CONTENT_REG_511_480_HI 31
++#define F0_CIS_CONTENT_REG_511_480_SZ 32
++#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_31_0_SFT 0
++#define F1_CIS_CONTENT_REG_31_0_HI 31
++#define F1_CIS_CONTENT_REG_31_0_SZ 32
++#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_63_32_SFT 0
++#define F1_CIS_CONTENT_REG_63_32_HI 31
++#define F1_CIS_CONTENT_REG_63_32_SZ 32
++#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_95_64_SFT 0
++#define F1_CIS_CONTENT_REG_95_64_HI 31
++#define F1_CIS_CONTENT_REG_95_64_SZ 32
++#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_127_96_SFT 0
++#define F1_CIS_CONTENT_REG_127_96_HI 31
++#define F1_CIS_CONTENT_REG_127_96_SZ 32
++#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_159_128_SFT 0
++#define F1_CIS_CONTENT_REG_159_128_HI 31
++#define F1_CIS_CONTENT_REG_159_128_SZ 32
++#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_191_160_SFT 0
++#define F1_CIS_CONTENT_REG_191_160_HI 31
++#define F1_CIS_CONTENT_REG_191_160_SZ 32
++#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_223_192_SFT 0
++#define F1_CIS_CONTENT_REG_223_192_HI 31
++#define F1_CIS_CONTENT_REG_223_192_SZ 32
++#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_255_224_SFT 0
++#define F1_CIS_CONTENT_REG_255_224_HI 31
++#define F1_CIS_CONTENT_REG_255_224_SZ 32
++#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_287_256_SFT 0
++#define F1_CIS_CONTENT_REG_287_256_HI 31
++#define F1_CIS_CONTENT_REG_287_256_SZ 32
++#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_319_288_SFT 0
++#define F1_CIS_CONTENT_REG_319_288_HI 31
++#define F1_CIS_CONTENT_REG_319_288_SZ 32
++#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_351_320_SFT 0
++#define F1_CIS_CONTENT_REG_351_320_HI 31
++#define F1_CIS_CONTENT_REG_351_320_SZ 32
++#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_383_352_SFT 0
++#define F1_CIS_CONTENT_REG_383_352_HI 31
++#define F1_CIS_CONTENT_REG_383_352_SZ 32
++#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_415_384_SFT 0
++#define F1_CIS_CONTENT_REG_415_384_HI 31
++#define F1_CIS_CONTENT_REG_415_384_SZ 32
++#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_447_416_SFT 0
++#define F1_CIS_CONTENT_REG_447_416_HI 31
++#define F1_CIS_CONTENT_REG_447_416_SZ 32
++#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_479_448_SFT 0
++#define F1_CIS_CONTENT_REG_479_448_HI 31
++#define F1_CIS_CONTENT_REG_479_448_SZ 32
++#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_511_480_SFT 0
++#define F1_CIS_CONTENT_REG_511_480_HI 31
++#define F1_CIS_CONTENT_REG_511_480_SZ 32
++#define SPI_MODE_MSK 0xffffffff
++#define SPI_MODE_I_MSK 0x00000000
++#define SPI_MODE_SFT 0
++#define SPI_MODE_HI 31
++#define SPI_MODE_SZ 32
++#define RX_QUOTA_MSK 0x0000ffff
++#define RX_QUOTA_I_MSK 0xffff0000
++#define RX_QUOTA_SFT 0
++#define RX_QUOTA_HI 15
++#define RX_QUOTA_SZ 16
++#define CONDI_NUM_MSK 0x000000ff
++#define CONDI_NUM_I_MSK 0xffffff00
++#define CONDI_NUM_SFT 0
++#define CONDI_NUM_HI 7
++#define CONDI_NUM_SZ 8
++#define HOST_PATH_MSK 0x00000001
++#define HOST_PATH_I_MSK 0xfffffffe
++#define HOST_PATH_SFT 0
++#define HOST_PATH_HI 0
++#define HOST_PATH_SZ 1
++#define TX_SEG_MSK 0xffffffff
++#define TX_SEG_I_MSK 0x00000000
++#define TX_SEG_SFT 0
++#define TX_SEG_HI 31
++#define TX_SEG_SZ 32
++#define BRST_MODE_MSK 0x00000001
++#define BRST_MODE_I_MSK 0xfffffffe
++#define BRST_MODE_SFT 0
++#define BRST_MODE_HI 0
++#define BRST_MODE_SZ 1
++#define CLK_WIDTH_MSK 0x0000ffff
++#define CLK_WIDTH_I_MSK 0xffff0000
++#define CLK_WIDTH_SFT 0
++#define CLK_WIDTH_HI 15
++#define CLK_WIDTH_SZ 16
++#define CSN_INTER_MSK 0xffff0000
++#define CSN_INTER_I_MSK 0x0000ffff
++#define CSN_INTER_SFT 16
++#define CSN_INTER_HI 31
++#define CSN_INTER_SZ 16
++#define BACK_DLY_MSK 0x0000ffff
++#define BACK_DLY_I_MSK 0xffff0000
++#define BACK_DLY_SFT 0
++#define BACK_DLY_HI 15
++#define BACK_DLY_SZ 16
++#define FRONT_DLY_MSK 0xffff0000
++#define FRONT_DLY_I_MSK 0x0000ffff
++#define FRONT_DLY_SFT 16
++#define FRONT_DLY_HI 31
++#define FRONT_DLY_SZ 16
++#define RX_FIFO_FAIL_MSK 0x00000002
++#define RX_FIFO_FAIL_I_MSK 0xfffffffd
++#define RX_FIFO_FAIL_SFT 1
++#define RX_FIFO_FAIL_HI 1
++#define RX_FIFO_FAIL_SZ 1
++#define RX_HOST_FAIL_MSK 0x00000004
++#define RX_HOST_FAIL_I_MSK 0xfffffffb
++#define RX_HOST_FAIL_SFT 2
++#define RX_HOST_FAIL_HI 2
++#define RX_HOST_FAIL_SZ 1
++#define TX_FIFO_FAIL_MSK 0x00000008
++#define TX_FIFO_FAIL_I_MSK 0xfffffff7
++#define TX_FIFO_FAIL_SFT 3
++#define TX_FIFO_FAIL_HI 3
++#define TX_FIFO_FAIL_SZ 1
++#define TX_HOST_FAIL_MSK 0x00000010
++#define TX_HOST_FAIL_I_MSK 0xffffffef
++#define TX_HOST_FAIL_SFT 4
++#define TX_HOST_FAIL_HI 4
++#define TX_HOST_FAIL_SZ 1
++#define SPI_DOUBLE_ALLOC_MSK 0x00000020
++#define SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
++#define SPI_DOUBLE_ALLOC_SFT 5
++#define SPI_DOUBLE_ALLOC_HI 5
++#define SPI_DOUBLE_ALLOC_SZ 1
++#define SPI_TX_NO_ALLOC_MSK 0x00000040
++#define SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
++#define SPI_TX_NO_ALLOC_SFT 6
++#define SPI_TX_NO_ALLOC_HI 6
++#define SPI_TX_NO_ALLOC_SZ 1
++#define RDATA_RDY_MSK 0x00000080
++#define RDATA_RDY_I_MSK 0xffffff7f
++#define RDATA_RDY_SFT 7
++#define RDATA_RDY_HI 7
++#define RDATA_RDY_SZ 1
++#define SPI_ALLOC_STATUS_MSK 0x00000100
++#define SPI_ALLOC_STATUS_I_MSK 0xfffffeff
++#define SPI_ALLOC_STATUS_SFT 8
++#define SPI_ALLOC_STATUS_HI 8
++#define SPI_ALLOC_STATUS_SZ 1
++#define SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
++#define SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
++#define SPI_DBG_WR_FIFO_FULL_SFT 9
++#define SPI_DBG_WR_FIFO_FULL_HI 9
++#define SPI_DBG_WR_FIFO_FULL_SZ 1
++#define RX_LEN_MSK 0xffff0000
++#define RX_LEN_I_MSK 0x0000ffff
++#define RX_LEN_SFT 16
++#define RX_LEN_HI 31
++#define RX_LEN_SZ 16
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
++#define SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
++#define SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
++#define SPI_HOST_TX_ALLOC_PKBUF_SFT 8
++#define SPI_HOST_TX_ALLOC_PKBUF_HI 8
++#define SPI_HOST_TX_ALLOC_PKBUF_SZ 1
++#define SPI_TX_ALLOC_SIZE_MSK 0x000000ff
++#define SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
++#define SPI_TX_ALLOC_SIZE_SFT 0
++#define SPI_TX_ALLOC_SIZE_HI 7
++#define SPI_TX_ALLOC_SIZE_SZ 8
++#define RD_DAT_CNT_MSK 0x0000ffff
++#define RD_DAT_CNT_I_MSK 0xffff0000
++#define RD_DAT_CNT_SFT 0
++#define RD_DAT_CNT_HI 15
++#define RD_DAT_CNT_SZ 16
++#define RD_STS_CNT_MSK 0xffff0000
++#define RD_STS_CNT_I_MSK 0x0000ffff
++#define RD_STS_CNT_SFT 16
++#define RD_STS_CNT_HI 31
++#define RD_STS_CNT_SZ 16
++#define JUDGE_CNT_MSK 0x0000ffff
++#define JUDGE_CNT_I_MSK 0xffff0000
++#define JUDGE_CNT_SFT 0
++#define JUDGE_CNT_HI 15
++#define JUDGE_CNT_SZ 16
++#define RD_STS_CNT_CLR_MSK 0x00010000
++#define RD_STS_CNT_CLR_I_MSK 0xfffeffff
++#define RD_STS_CNT_CLR_SFT 16
++#define RD_STS_CNT_CLR_HI 16
++#define RD_STS_CNT_CLR_SZ 1
++#define RD_DAT_CNT_CLR_MSK 0x00020000
++#define RD_DAT_CNT_CLR_I_MSK 0xfffdffff
++#define RD_DAT_CNT_CLR_SFT 17
++#define RD_DAT_CNT_CLR_HI 17
++#define RD_DAT_CNT_CLR_SZ 1
++#define JUDGE_CNT_CLR_MSK 0x00040000
++#define JUDGE_CNT_CLR_I_MSK 0xfffbffff
++#define JUDGE_CNT_CLR_SFT 18
++#define JUDGE_CNT_CLR_HI 18
++#define JUDGE_CNT_CLR_SZ 1
++#define TX_DONE_CNT_MSK 0x0000ffff
++#define TX_DONE_CNT_I_MSK 0xffff0000
++#define TX_DONE_CNT_SFT 0
++#define TX_DONE_CNT_HI 15
++#define TX_DONE_CNT_SZ 16
++#define TX_DISCARD_CNT_MSK 0xffff0000
++#define TX_DISCARD_CNT_I_MSK 0x0000ffff
++#define TX_DISCARD_CNT_SFT 16
++#define TX_DISCARD_CNT_HI 31
++#define TX_DISCARD_CNT_SZ 16
++#define TX_SET_CNT_MSK 0x0000ffff
++#define TX_SET_CNT_I_MSK 0xffff0000
++#define TX_SET_CNT_SFT 0
++#define TX_SET_CNT_HI 15
++#define TX_SET_CNT_SZ 16
++#define TX_DISCARD_CNT_CLR_MSK 0x00010000
++#define TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
++#define TX_DISCARD_CNT_CLR_SFT 16
++#define TX_DISCARD_CNT_CLR_HI 16
++#define TX_DISCARD_CNT_CLR_SZ 1
++#define TX_DONE_CNT_CLR_MSK 0x00020000
++#define TX_DONE_CNT_CLR_I_MSK 0xfffdffff
++#define TX_DONE_CNT_CLR_SFT 17
++#define TX_DONE_CNT_CLR_HI 17
++#define TX_DONE_CNT_CLR_SZ 1
++#define TX_SET_CNT_CLR_MSK 0x00040000
++#define TX_SET_CNT_CLR_I_MSK 0xfffbffff
++#define TX_SET_CNT_CLR_SFT 18
++#define TX_SET_CNT_CLR_HI 18
++#define TX_SET_CNT_CLR_SZ 1
++#define DAT_MODE_OFF_MSK 0x00080000
++#define DAT_MODE_OFF_I_MSK 0xfff7ffff
++#define DAT_MODE_OFF_SFT 19
++#define DAT_MODE_OFF_HI 19
++#define DAT_MODE_OFF_SZ 1
++#define TX_FIFO_RESIDUE_MSK 0x00700000
++#define TX_FIFO_RESIDUE_I_MSK 0xff8fffff
++#define TX_FIFO_RESIDUE_SFT 20
++#define TX_FIFO_RESIDUE_HI 22
++#define TX_FIFO_RESIDUE_SZ 3
++#define RX_FIFO_RESIDUE_MSK 0x07000000
++#define RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
++#define RX_FIFO_RESIDUE_SFT 24
++#define RX_FIFO_RESIDUE_HI 26
++#define RX_FIFO_RESIDUE_SZ 3
++#define RX_RDY_MSK 0x00000001
++#define RX_RDY_I_MSK 0xfffffffe
++#define RX_RDY_SFT 0
++#define RX_RDY_HI 0
++#define RX_RDY_SZ 1
++#define SDIO_SYS_INT_MSK 0x00000004
++#define SDIO_SYS_INT_I_MSK 0xfffffffb
++#define SDIO_SYS_INT_SFT 2
++#define SDIO_SYS_INT_HI 2
++#define SDIO_SYS_INT_SZ 1
++#define EDCA0_LOWTHOLD_INT_MSK 0x00000008
++#define EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
++#define EDCA0_LOWTHOLD_INT_SFT 3
++#define EDCA0_LOWTHOLD_INT_HI 3
++#define EDCA0_LOWTHOLD_INT_SZ 1
++#define EDCA1_LOWTHOLD_INT_MSK 0x00000010
++#define EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
++#define EDCA1_LOWTHOLD_INT_SFT 4
++#define EDCA1_LOWTHOLD_INT_HI 4
++#define EDCA1_LOWTHOLD_INT_SZ 1
++#define EDCA2_LOWTHOLD_INT_MSK 0x00000020
++#define EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
++#define EDCA2_LOWTHOLD_INT_SFT 5
++#define EDCA2_LOWTHOLD_INT_HI 5
++#define EDCA2_LOWTHOLD_INT_SZ 1
++#define EDCA3_LOWTHOLD_INT_MSK 0x00000040
++#define EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
++#define EDCA3_LOWTHOLD_INT_SFT 6
++#define EDCA3_LOWTHOLD_INT_HI 6
++#define EDCA3_LOWTHOLD_INT_SZ 1
++#define TX_LIMIT_INT_IN_MSK 0x00000080
++#define TX_LIMIT_INT_IN_I_MSK 0xffffff7f
++#define TX_LIMIT_INT_IN_SFT 7
++#define TX_LIMIT_INT_IN_HI 7
++#define TX_LIMIT_INT_IN_SZ 1
++#define SPI_FN1_MSK 0x00007f00
++#define SPI_FN1_I_MSK 0xffff80ff
++#define SPI_FN1_SFT 8
++#define SPI_FN1_HI 14
++#define SPI_FN1_SZ 7
++#define SPI_CLK_EN_INT_MSK 0x00008000
++#define SPI_CLK_EN_INT_I_MSK 0xffff7fff
++#define SPI_CLK_EN_INT_SFT 15
++#define SPI_CLK_EN_INT_HI 15
++#define SPI_CLK_EN_INT_SZ 1
++#define SPI_HOST_MASK_MSK 0x00ff0000
++#define SPI_HOST_MASK_I_MSK 0xff00ffff
++#define SPI_HOST_MASK_SFT 16
++#define SPI_HOST_MASK_HI 23
++#define SPI_HOST_MASK_SZ 8
++#define I2CM_INT_WDONE_MSK 0x00000001
++#define I2CM_INT_WDONE_I_MSK 0xfffffffe
++#define I2CM_INT_WDONE_SFT 0
++#define I2CM_INT_WDONE_HI 0
++#define I2CM_INT_WDONE_SZ 1
++#define I2CM_INT_RDONE_MSK 0x00000002
++#define I2CM_INT_RDONE_I_MSK 0xfffffffd
++#define I2CM_INT_RDONE_SFT 1
++#define I2CM_INT_RDONE_HI 1
++#define I2CM_INT_RDONE_SZ 1
++#define I2CM_IDLE_MSK 0x00000004
++#define I2CM_IDLE_I_MSK 0xfffffffb
++#define I2CM_IDLE_SFT 2
++#define I2CM_IDLE_HI 2
++#define I2CM_IDLE_SZ 1
++#define I2CM_INT_MISMATCH_MSK 0x00000008
++#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7
++#define I2CM_INT_MISMATCH_SFT 3
++#define I2CM_INT_MISMATCH_HI 3
++#define I2CM_INT_MISMATCH_SZ 1
++#define I2CM_PSCL_MSK 0x00003ff0
++#define I2CM_PSCL_I_MSK 0xffffc00f
++#define I2CM_PSCL_SFT 4
++#define I2CM_PSCL_HI 13
++#define I2CM_PSCL_SZ 10
++#define I2CM_MANUAL_MODE_MSK 0x00010000
++#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff
++#define I2CM_MANUAL_MODE_SFT 16
++#define I2CM_MANUAL_MODE_HI 16
++#define I2CM_MANUAL_MODE_SZ 1
++#define I2CM_INT_WDATA_NEED_MSK 0x00020000
++#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff
++#define I2CM_INT_WDATA_NEED_SFT 17
++#define I2CM_INT_WDATA_NEED_HI 17
++#define I2CM_INT_WDATA_NEED_SZ 1
++#define I2CM_INT_RDATA_NEED_MSK 0x00040000
++#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff
++#define I2CM_INT_RDATA_NEED_SFT 18
++#define I2CM_INT_RDATA_NEED_HI 18
++#define I2CM_INT_RDATA_NEED_SZ 1
++#define I2CM_DEV_A_MSK 0x000003ff
++#define I2CM_DEV_A_I_MSK 0xfffffc00
++#define I2CM_DEV_A_SFT 0
++#define I2CM_DEV_A_HI 9
++#define I2CM_DEV_A_SZ 10
++#define I2CM_DEV_A10B_MSK 0x00004000
++#define I2CM_DEV_A10B_I_MSK 0xffffbfff
++#define I2CM_DEV_A10B_SFT 14
++#define I2CM_DEV_A10B_HI 14
++#define I2CM_DEV_A10B_SZ 1
++#define I2CM_RX_MSK 0x00008000
++#define I2CM_RX_I_MSK 0xffff7fff
++#define I2CM_RX_SFT 15
++#define I2CM_RX_HI 15
++#define I2CM_RX_SZ 1
++#define I2CM_LEN_MSK 0x0000ffff
++#define I2CM_LEN_I_MSK 0xffff0000
++#define I2CM_LEN_SFT 0
++#define I2CM_LEN_HI 15
++#define I2CM_LEN_SZ 16
++#define I2CM_T_LEFT_MSK 0x00070000
++#define I2CM_T_LEFT_I_MSK 0xfff8ffff
++#define I2CM_T_LEFT_SFT 16
++#define I2CM_T_LEFT_HI 18
++#define I2CM_T_LEFT_SZ 3
++#define I2CM_R_GET_MSK 0x07000000
++#define I2CM_R_GET_I_MSK 0xf8ffffff
++#define I2CM_R_GET_SFT 24
++#define I2CM_R_GET_HI 26
++#define I2CM_R_GET_SZ 3
++#define I2CM_WDAT_MSK 0xffffffff
++#define I2CM_WDAT_I_MSK 0x00000000
++#define I2CM_WDAT_SFT 0
++#define I2CM_WDAT_HI 31
++#define I2CM_WDAT_SZ 32
++#define I2CM_RDAT_MSK 0xffffffff
++#define I2CM_RDAT_I_MSK 0x00000000
++#define I2CM_RDAT_SFT 0
++#define I2CM_RDAT_HI 31
++#define I2CM_RDAT_SZ 32
++#define I2CM_SR_LEN_MSK 0x0000ffff
++#define I2CM_SR_LEN_I_MSK 0xffff0000
++#define I2CM_SR_LEN_SFT 0
++#define I2CM_SR_LEN_HI 15
++#define I2CM_SR_LEN_SZ 16
++#define I2CM_SR_RX_MSK 0x00010000
++#define I2CM_SR_RX_I_MSK 0xfffeffff
++#define I2CM_SR_RX_SFT 16
++#define I2CM_SR_RX_HI 16
++#define I2CM_SR_RX_SZ 1
++#define I2CM_REPEAT_START_MSK 0x00020000
++#define I2CM_REPEAT_START_I_MSK 0xfffdffff
++#define I2CM_REPEAT_START_SFT 17
++#define I2CM_REPEAT_START_HI 17
++#define I2CM_REPEAT_START_SZ 1
++#define UART_DATA_MSK 0x000000ff
++#define UART_DATA_I_MSK 0xffffff00
++#define UART_DATA_SFT 0
++#define UART_DATA_HI 7
++#define UART_DATA_SZ 8
++#define DATA_RDY_IE_MSK 0x00000001
++#define DATA_RDY_IE_I_MSK 0xfffffffe
++#define DATA_RDY_IE_SFT 0
++#define DATA_RDY_IE_HI 0
++#define DATA_RDY_IE_SZ 1
++#define THR_EMPTY_IE_MSK 0x00000002
++#define THR_EMPTY_IE_I_MSK 0xfffffffd
++#define THR_EMPTY_IE_SFT 1
++#define THR_EMPTY_IE_HI 1
++#define THR_EMPTY_IE_SZ 1
++#define RX_LINESTS_IE_MSK 0x00000004
++#define RX_LINESTS_IE_I_MSK 0xfffffffb
++#define RX_LINESTS_IE_SFT 2
++#define RX_LINESTS_IE_HI 2
++#define RX_LINESTS_IE_SZ 1
++#define MDM_STS_IE_MSK 0x00000008
++#define MDM_STS_IE_I_MSK 0xfffffff7
++#define MDM_STS_IE_SFT 3
++#define MDM_STS_IE_HI 3
++#define MDM_STS_IE_SZ 1
++#define DMA_RXEND_IE_MSK 0x00000040
++#define DMA_RXEND_IE_I_MSK 0xffffffbf
++#define DMA_RXEND_IE_SFT 6
++#define DMA_RXEND_IE_HI 6
++#define DMA_RXEND_IE_SZ 1
++#define DMA_TXEND_IE_MSK 0x00000080
++#define DMA_TXEND_IE_I_MSK 0xffffff7f
++#define DMA_TXEND_IE_SFT 7
++#define DMA_TXEND_IE_HI 7
++#define DMA_TXEND_IE_SZ 1
++#define FIFO_EN_MSK 0x00000001
++#define FIFO_EN_I_MSK 0xfffffffe
++#define FIFO_EN_SFT 0
++#define FIFO_EN_HI 0
++#define FIFO_EN_SZ 1
++#define RXFIFO_RST_MSK 0x00000002
++#define RXFIFO_RST_I_MSK 0xfffffffd
++#define RXFIFO_RST_SFT 1
++#define RXFIFO_RST_HI 1
++#define RXFIFO_RST_SZ 1
++#define TXFIFO_RST_MSK 0x00000004
++#define TXFIFO_RST_I_MSK 0xfffffffb
++#define TXFIFO_RST_SFT 2
++#define TXFIFO_RST_HI 2
++#define TXFIFO_RST_SZ 1
++#define DMA_MODE_MSK 0x00000008
++#define DMA_MODE_I_MSK 0xfffffff7
++#define DMA_MODE_SFT 3
++#define DMA_MODE_HI 3
++#define DMA_MODE_SZ 1
++#define EN_AUTO_RTS_MSK 0x00000010
++#define EN_AUTO_RTS_I_MSK 0xffffffef
++#define EN_AUTO_RTS_SFT 4
++#define EN_AUTO_RTS_HI 4
++#define EN_AUTO_RTS_SZ 1
++#define EN_AUTO_CTS_MSK 0x00000020
++#define EN_AUTO_CTS_I_MSK 0xffffffdf
++#define EN_AUTO_CTS_SFT 5
++#define EN_AUTO_CTS_HI 5
++#define EN_AUTO_CTS_SZ 1
++#define RXFIFO_TRGLVL_MSK 0x000000c0
++#define RXFIFO_TRGLVL_I_MSK 0xffffff3f
++#define RXFIFO_TRGLVL_SFT 6
++#define RXFIFO_TRGLVL_HI 7
++#define RXFIFO_TRGLVL_SZ 2
++#define WORD_LEN_MSK 0x00000003
++#define WORD_LEN_I_MSK 0xfffffffc
++#define WORD_LEN_SFT 0
++#define WORD_LEN_HI 1
++#define WORD_LEN_SZ 2
++#define STOP_BIT_MSK 0x00000004
++#define STOP_BIT_I_MSK 0xfffffffb
++#define STOP_BIT_SFT 2
++#define STOP_BIT_HI 2
++#define STOP_BIT_SZ 1
++#define PARITY_EN_MSK 0x00000008
++#define PARITY_EN_I_MSK 0xfffffff7
++#define PARITY_EN_SFT 3
++#define PARITY_EN_HI 3
++#define PARITY_EN_SZ 1
++#define EVEN_PARITY_MSK 0x00000010
++#define EVEN_PARITY_I_MSK 0xffffffef
++#define EVEN_PARITY_SFT 4
++#define EVEN_PARITY_HI 4
++#define EVEN_PARITY_SZ 1
++#define FORCE_PARITY_MSK 0x00000020
++#define FORCE_PARITY_I_MSK 0xffffffdf
++#define FORCE_PARITY_SFT 5
++#define FORCE_PARITY_HI 5
++#define FORCE_PARITY_SZ 1
++#define SET_BREAK_MSK 0x00000040
++#define SET_BREAK_I_MSK 0xffffffbf
++#define SET_BREAK_SFT 6
++#define SET_BREAK_HI 6
++#define SET_BREAK_SZ 1
++#define DLAB_MSK 0x00000080
++#define DLAB_I_MSK 0xffffff7f
++#define DLAB_SFT 7
++#define DLAB_HI 7
++#define DLAB_SZ 1
++#define DTR_MSK 0x00000001
++#define DTR_I_MSK 0xfffffffe
++#define DTR_SFT 0
++#define DTR_HI 0
++#define DTR_SZ 1
++#define RTS_MSK 0x00000002
++#define RTS_I_MSK 0xfffffffd
++#define RTS_SFT 1
++#define RTS_HI 1
++#define RTS_SZ 1
++#define OUT_1_MSK 0x00000004
++#define OUT_1_I_MSK 0xfffffffb
++#define OUT_1_SFT 2
++#define OUT_1_HI 2
++#define OUT_1_SZ 1
++#define OUT_2_MSK 0x00000008
++#define OUT_2_I_MSK 0xfffffff7
++#define OUT_2_SFT 3
++#define OUT_2_HI 3
++#define OUT_2_SZ 1
++#define LOOP_BACK_MSK 0x00000010
++#define LOOP_BACK_I_MSK 0xffffffef
++#define LOOP_BACK_SFT 4
++#define LOOP_BACK_HI 4
++#define LOOP_BACK_SZ 1
++#define DATA_RDY_MSK 0x00000001
++#define DATA_RDY_I_MSK 0xfffffffe
++#define DATA_RDY_SFT 0
++#define DATA_RDY_HI 0
++#define DATA_RDY_SZ 1
++#define OVERRUN_ERR_MSK 0x00000002
++#define OVERRUN_ERR_I_MSK 0xfffffffd
++#define OVERRUN_ERR_SFT 1
++#define OVERRUN_ERR_HI 1
++#define OVERRUN_ERR_SZ 1
++#define PARITY_ERR_MSK 0x00000004
++#define PARITY_ERR_I_MSK 0xfffffffb
++#define PARITY_ERR_SFT 2
++#define PARITY_ERR_HI 2
++#define PARITY_ERR_SZ 1
++#define FRAMING_ERR_MSK 0x00000008
++#define FRAMING_ERR_I_MSK 0xfffffff7
++#define FRAMING_ERR_SFT 3
++#define FRAMING_ERR_HI 3
++#define FRAMING_ERR_SZ 1
++#define BREAK_INT_MSK 0x00000010
++#define BREAK_INT_I_MSK 0xffffffef
++#define BREAK_INT_SFT 4
++#define BREAK_INT_HI 4
++#define BREAK_INT_SZ 1
++#define THR_EMPTY_MSK 0x00000020
++#define THR_EMPTY_I_MSK 0xffffffdf
++#define THR_EMPTY_SFT 5
++#define THR_EMPTY_HI 5
++#define THR_EMPTY_SZ 1
++#define TX_EMPTY_MSK 0x00000040
++#define TX_EMPTY_I_MSK 0xffffffbf
++#define TX_EMPTY_SFT 6
++#define TX_EMPTY_HI 6
++#define TX_EMPTY_SZ 1
++#define FIFODATA_ERR_MSK 0x00000080
++#define FIFODATA_ERR_I_MSK 0xffffff7f
++#define FIFODATA_ERR_SFT 7
++#define FIFODATA_ERR_HI 7
++#define FIFODATA_ERR_SZ 1
++#define DELTA_CTS_MSK 0x00000001
++#define DELTA_CTS_I_MSK 0xfffffffe
++#define DELTA_CTS_SFT 0
++#define DELTA_CTS_HI 0
++#define DELTA_CTS_SZ 1
++#define DELTA_DSR_MSK 0x00000002
++#define DELTA_DSR_I_MSK 0xfffffffd
++#define DELTA_DSR_SFT 1
++#define DELTA_DSR_HI 1
++#define DELTA_DSR_SZ 1
++#define TRAILEDGE_RI_MSK 0x00000004
++#define TRAILEDGE_RI_I_MSK 0xfffffffb
++#define TRAILEDGE_RI_SFT 2
++#define TRAILEDGE_RI_HI 2
++#define TRAILEDGE_RI_SZ 1
++#define DELTA_CD_MSK 0x00000008
++#define DELTA_CD_I_MSK 0xfffffff7
++#define DELTA_CD_SFT 3
++#define DELTA_CD_HI 3
++#define DELTA_CD_SZ 1
++#define CTS_MSK 0x00000010
++#define CTS_I_MSK 0xffffffef
++#define CTS_SFT 4
++#define CTS_HI 4
++#define CTS_SZ 1
++#define DSR_MSK 0x00000020
++#define DSR_I_MSK 0xffffffdf
++#define DSR_SFT 5
++#define DSR_HI 5
++#define DSR_SZ 1
++#define RI_MSK 0x00000040
++#define RI_I_MSK 0xffffffbf
++#define RI_SFT 6
++#define RI_HI 6
++#define RI_SZ 1
++#define CD_MSK 0x00000080
++#define CD_I_MSK 0xffffff7f
++#define CD_SFT 7
++#define CD_HI 7
++#define CD_SZ 1
++#define BRDC_DIV_MSK 0x0000ffff
++#define BRDC_DIV_I_MSK 0xffff0000
++#define BRDC_DIV_SFT 0
++#define BRDC_DIV_HI 15
++#define BRDC_DIV_SZ 16
++#define RTHR_L_MSK 0x0000000f
++#define RTHR_L_I_MSK 0xfffffff0
++#define RTHR_L_SFT 0
++#define RTHR_L_HI 3
++#define RTHR_L_SZ 4
++#define RTHR_H_MSK 0x000000f0
++#define RTHR_H_I_MSK 0xffffff0f
++#define RTHR_H_SFT 4
++#define RTHR_H_HI 7
++#define RTHR_H_SZ 4
++#define INT_IDCODE_MSK 0x0000000f
++#define INT_IDCODE_I_MSK 0xfffffff0
++#define INT_IDCODE_SFT 0
++#define INT_IDCODE_HI 3
++#define INT_IDCODE_SZ 4
++#define FIFOS_ENABLED_MSK 0x000000c0
++#define FIFOS_ENABLED_I_MSK 0xffffff3f
++#define FIFOS_ENABLED_SFT 6
++#define FIFOS_ENABLED_HI 7
++#define FIFOS_ENABLED_SZ 2
++#define DAT_UART_DATA_MSK 0x000000ff
++#define DAT_UART_DATA_I_MSK 0xffffff00
++#define DAT_UART_DATA_SFT 0
++#define DAT_UART_DATA_HI 7
++#define DAT_UART_DATA_SZ 8
++#define DAT_DATA_RDY_IE_MSK 0x00000001
++#define DAT_DATA_RDY_IE_I_MSK 0xfffffffe
++#define DAT_DATA_RDY_IE_SFT 0
++#define DAT_DATA_RDY_IE_HI 0
++#define DAT_DATA_RDY_IE_SZ 1
++#define DAT_THR_EMPTY_IE_MSK 0x00000002
++#define DAT_THR_EMPTY_IE_I_MSK 0xfffffffd
++#define DAT_THR_EMPTY_IE_SFT 1
++#define DAT_THR_EMPTY_IE_HI 1
++#define DAT_THR_EMPTY_IE_SZ 1
++#define DAT_RX_LINESTS_IE_MSK 0x00000004
++#define DAT_RX_LINESTS_IE_I_MSK 0xfffffffb
++#define DAT_RX_LINESTS_IE_SFT 2
++#define DAT_RX_LINESTS_IE_HI 2
++#define DAT_RX_LINESTS_IE_SZ 1
++#define DAT_MDM_STS_IE_MSK 0x00000008
++#define DAT_MDM_STS_IE_I_MSK 0xfffffff7
++#define DAT_MDM_STS_IE_SFT 3
++#define DAT_MDM_STS_IE_HI 3
++#define DAT_MDM_STS_IE_SZ 1
++#define DAT_DMA_RXEND_IE_MSK 0x00000040
++#define DAT_DMA_RXEND_IE_I_MSK 0xffffffbf
++#define DAT_DMA_RXEND_IE_SFT 6
++#define DAT_DMA_RXEND_IE_HI 6
++#define DAT_DMA_RXEND_IE_SZ 1
++#define DAT_DMA_TXEND_IE_MSK 0x00000080
++#define DAT_DMA_TXEND_IE_I_MSK 0xffffff7f
++#define DAT_DMA_TXEND_IE_SFT 7
++#define DAT_DMA_TXEND_IE_HI 7
++#define DAT_DMA_TXEND_IE_SZ 1
++#define DAT_FIFO_EN_MSK 0x00000001
++#define DAT_FIFO_EN_I_MSK 0xfffffffe
++#define DAT_FIFO_EN_SFT 0
++#define DAT_FIFO_EN_HI 0
++#define DAT_FIFO_EN_SZ 1
++#define DAT_RXFIFO_RST_MSK 0x00000002
++#define DAT_RXFIFO_RST_I_MSK 0xfffffffd
++#define DAT_RXFIFO_RST_SFT 1
++#define DAT_RXFIFO_RST_HI 1
++#define DAT_RXFIFO_RST_SZ 1
++#define DAT_TXFIFO_RST_MSK 0x00000004
++#define DAT_TXFIFO_RST_I_MSK 0xfffffffb
++#define DAT_TXFIFO_RST_SFT 2
++#define DAT_TXFIFO_RST_HI 2
++#define DAT_TXFIFO_RST_SZ 1
++#define DAT_DMA_MODE_MSK 0x00000008
++#define DAT_DMA_MODE_I_MSK 0xfffffff7
++#define DAT_DMA_MODE_SFT 3
++#define DAT_DMA_MODE_HI 3
++#define DAT_DMA_MODE_SZ 1
++#define DAT_EN_AUTO_RTS_MSK 0x00000010
++#define DAT_EN_AUTO_RTS_I_MSK 0xffffffef
++#define DAT_EN_AUTO_RTS_SFT 4
++#define DAT_EN_AUTO_RTS_HI 4
++#define DAT_EN_AUTO_RTS_SZ 1
++#define DAT_EN_AUTO_CTS_MSK 0x00000020
++#define DAT_EN_AUTO_CTS_I_MSK 0xffffffdf
++#define DAT_EN_AUTO_CTS_SFT 5
++#define DAT_EN_AUTO_CTS_HI 5
++#define DAT_EN_AUTO_CTS_SZ 1
++#define DAT_RXFIFO_TRGLVL_MSK 0x000000c0
++#define DAT_RXFIFO_TRGLVL_I_MSK 0xffffff3f
++#define DAT_RXFIFO_TRGLVL_SFT 6
++#define DAT_RXFIFO_TRGLVL_HI 7
++#define DAT_RXFIFO_TRGLVL_SZ 2
++#define DAT_WORD_LEN_MSK 0x00000003
++#define DAT_WORD_LEN_I_MSK 0xfffffffc
++#define DAT_WORD_LEN_SFT 0
++#define DAT_WORD_LEN_HI 1
++#define DAT_WORD_LEN_SZ 2
++#define DAT_STOP_BIT_MSK 0x00000004
++#define DAT_STOP_BIT_I_MSK 0xfffffffb
++#define DAT_STOP_BIT_SFT 2
++#define DAT_STOP_BIT_HI 2
++#define DAT_STOP_BIT_SZ 1
++#define DAT_PARITY_EN_MSK 0x00000008
++#define DAT_PARITY_EN_I_MSK 0xfffffff7
++#define DAT_PARITY_EN_SFT 3
++#define DAT_PARITY_EN_HI 3
++#define DAT_PARITY_EN_SZ 1
++#define DAT_EVEN_PARITY_MSK 0x00000010
++#define DAT_EVEN_PARITY_I_MSK 0xffffffef
++#define DAT_EVEN_PARITY_SFT 4
++#define DAT_EVEN_PARITY_HI 4
++#define DAT_EVEN_PARITY_SZ 1
++#define DAT_FORCE_PARITY_MSK 0x00000020
++#define DAT_FORCE_PARITY_I_MSK 0xffffffdf
++#define DAT_FORCE_PARITY_SFT 5
++#define DAT_FORCE_PARITY_HI 5
++#define DAT_FORCE_PARITY_SZ 1
++#define DAT_SET_BREAK_MSK 0x00000040
++#define DAT_SET_BREAK_I_MSK 0xffffffbf
++#define DAT_SET_BREAK_SFT 6
++#define DAT_SET_BREAK_HI 6
++#define DAT_SET_BREAK_SZ 1
++#define DAT_DLAB_MSK 0x00000080
++#define DAT_DLAB_I_MSK 0xffffff7f
++#define DAT_DLAB_SFT 7
++#define DAT_DLAB_HI 7
++#define DAT_DLAB_SZ 1
++#define DAT_DTR_MSK 0x00000001
++#define DAT_DTR_I_MSK 0xfffffffe
++#define DAT_DTR_SFT 0
++#define DAT_DTR_HI 0
++#define DAT_DTR_SZ 1
++#define DAT_RTS_MSK 0x00000002
++#define DAT_RTS_I_MSK 0xfffffffd
++#define DAT_RTS_SFT 1
++#define DAT_RTS_HI 1
++#define DAT_RTS_SZ 1
++#define DAT_OUT_1_MSK 0x00000004
++#define DAT_OUT_1_I_MSK 0xfffffffb
++#define DAT_OUT_1_SFT 2
++#define DAT_OUT_1_HI 2
++#define DAT_OUT_1_SZ 1
++#define DAT_OUT_2_MSK 0x00000008
++#define DAT_OUT_2_I_MSK 0xfffffff7
++#define DAT_OUT_2_SFT 3
++#define DAT_OUT_2_HI 3
++#define DAT_OUT_2_SZ 1
++#define DAT_LOOP_BACK_MSK 0x00000010
++#define DAT_LOOP_BACK_I_MSK 0xffffffef
++#define DAT_LOOP_BACK_SFT 4
++#define DAT_LOOP_BACK_HI 4
++#define DAT_LOOP_BACK_SZ 1
++#define DAT_DATA_RDY_MSK 0x00000001
++#define DAT_DATA_RDY_I_MSK 0xfffffffe
++#define DAT_DATA_RDY_SFT 0
++#define DAT_DATA_RDY_HI 0
++#define DAT_DATA_RDY_SZ 1
++#define DAT_OVERRUN_ERR_MSK 0x00000002
++#define DAT_OVERRUN_ERR_I_MSK 0xfffffffd
++#define DAT_OVERRUN_ERR_SFT 1
++#define DAT_OVERRUN_ERR_HI 1
++#define DAT_OVERRUN_ERR_SZ 1
++#define DAT_PARITY_ERR_MSK 0x00000004
++#define DAT_PARITY_ERR_I_MSK 0xfffffffb
++#define DAT_PARITY_ERR_SFT 2
++#define DAT_PARITY_ERR_HI 2
++#define DAT_PARITY_ERR_SZ 1
++#define DAT_FRAMING_ERR_MSK 0x00000008
++#define DAT_FRAMING_ERR_I_MSK 0xfffffff7
++#define DAT_FRAMING_ERR_SFT 3
++#define DAT_FRAMING_ERR_HI 3
++#define DAT_FRAMING_ERR_SZ 1
++#define DAT_BREAK_INT_MSK 0x00000010
++#define DAT_BREAK_INT_I_MSK 0xffffffef
++#define DAT_BREAK_INT_SFT 4
++#define DAT_BREAK_INT_HI 4
++#define DAT_BREAK_INT_SZ 1
++#define DAT_THR_EMPTY_MSK 0x00000020
++#define DAT_THR_EMPTY_I_MSK 0xffffffdf
++#define DAT_THR_EMPTY_SFT 5
++#define DAT_THR_EMPTY_HI 5
++#define DAT_THR_EMPTY_SZ 1
++#define DAT_TX_EMPTY_MSK 0x00000040
++#define DAT_TX_EMPTY_I_MSK 0xffffffbf
++#define DAT_TX_EMPTY_SFT 6
++#define DAT_TX_EMPTY_HI 6
++#define DAT_TX_EMPTY_SZ 1
++#define DAT_FIFODATA_ERR_MSK 0x00000080
++#define DAT_FIFODATA_ERR_I_MSK 0xffffff7f
++#define DAT_FIFODATA_ERR_SFT 7
++#define DAT_FIFODATA_ERR_HI 7
++#define DAT_FIFODATA_ERR_SZ 1
++#define DAT_DELTA_CTS_MSK 0x00000001
++#define DAT_DELTA_CTS_I_MSK 0xfffffffe
++#define DAT_DELTA_CTS_SFT 0
++#define DAT_DELTA_CTS_HI 0
++#define DAT_DELTA_CTS_SZ 1
++#define DAT_DELTA_DSR_MSK 0x00000002
++#define DAT_DELTA_DSR_I_MSK 0xfffffffd
++#define DAT_DELTA_DSR_SFT 1
++#define DAT_DELTA_DSR_HI 1
++#define DAT_DELTA_DSR_SZ 1
++#define DAT_TRAILEDGE_RI_MSK 0x00000004
++#define DAT_TRAILEDGE_RI_I_MSK 0xfffffffb
++#define DAT_TRAILEDGE_RI_SFT 2
++#define DAT_TRAILEDGE_RI_HI 2
++#define DAT_TRAILEDGE_RI_SZ 1
++#define DAT_DELTA_CD_MSK 0x00000008
++#define DAT_DELTA_CD_I_MSK 0xfffffff7
++#define DAT_DELTA_CD_SFT 3
++#define DAT_DELTA_CD_HI 3
++#define DAT_DELTA_CD_SZ 1
++#define DAT_CTS_MSK 0x00000010
++#define DAT_CTS_I_MSK 0xffffffef
++#define DAT_CTS_SFT 4
++#define DAT_CTS_HI 4
++#define DAT_CTS_SZ 1
++#define DAT_DSR_MSK 0x00000020
++#define DAT_DSR_I_MSK 0xffffffdf
++#define DAT_DSR_SFT 5
++#define DAT_DSR_HI 5
++#define DAT_DSR_SZ 1
++#define DAT_RI_MSK 0x00000040
++#define DAT_RI_I_MSK 0xffffffbf
++#define DAT_RI_SFT 6
++#define DAT_RI_HI 6
++#define DAT_RI_SZ 1
++#define DAT_CD_MSK 0x00000080
++#define DAT_CD_I_MSK 0xffffff7f
++#define DAT_CD_SFT 7
++#define DAT_CD_HI 7
++#define DAT_CD_SZ 1
++#define DAT_BRDC_DIV_MSK 0x0000ffff
++#define DAT_BRDC_DIV_I_MSK 0xffff0000
++#define DAT_BRDC_DIV_SFT 0
++#define DAT_BRDC_DIV_HI 15
++#define DAT_BRDC_DIV_SZ 16
++#define DAT_RTHR_L_MSK 0x0000000f
++#define DAT_RTHR_L_I_MSK 0xfffffff0
++#define DAT_RTHR_L_SFT 0
++#define DAT_RTHR_L_HI 3
++#define DAT_RTHR_L_SZ 4
++#define DAT_RTHR_H_MSK 0x000000f0
++#define DAT_RTHR_H_I_MSK 0xffffff0f
++#define DAT_RTHR_H_SFT 4
++#define DAT_RTHR_H_HI 7
++#define DAT_RTHR_H_SZ 4
++#define DAT_INT_IDCODE_MSK 0x0000000f
++#define DAT_INT_IDCODE_I_MSK 0xfffffff0
++#define DAT_INT_IDCODE_SFT 0
++#define DAT_INT_IDCODE_HI 3
++#define DAT_INT_IDCODE_SZ 4
++#define DAT_FIFOS_ENABLED_MSK 0x000000c0
++#define DAT_FIFOS_ENABLED_I_MSK 0xffffff3f
++#define DAT_FIFOS_ENABLED_SFT 6
++#define DAT_FIFOS_ENABLED_HI 7
++#define DAT_FIFOS_ENABLED_SZ 2
++#define MASK_TOP_MSK 0xffffffff
++#define MASK_TOP_I_MSK 0x00000000
++#define MASK_TOP_SFT 0
++#define MASK_TOP_HI 31
++#define MASK_TOP_SZ 32
++#define INT_MODE_MSK 0xffffffff
++#define INT_MODE_I_MSK 0x00000000
++#define INT_MODE_SFT 0
++#define INT_MODE_HI 31
++#define INT_MODE_SZ 32
++#define IRQ_PHY_0_MSK 0x00000001
++#define IRQ_PHY_0_I_MSK 0xfffffffe
++#define IRQ_PHY_0_SFT 0
++#define IRQ_PHY_0_HI 0
++#define IRQ_PHY_0_SZ 1
++#define IRQ_PHY_1_MSK 0x00000002
++#define IRQ_PHY_1_I_MSK 0xfffffffd
++#define IRQ_PHY_1_SFT 1
++#define IRQ_PHY_1_HI 1
++#define IRQ_PHY_1_SZ 1
++#define IRQ_SDIO_MSK 0x00000004
++#define IRQ_SDIO_I_MSK 0xfffffffb
++#define IRQ_SDIO_SFT 2
++#define IRQ_SDIO_HI 2
++#define IRQ_SDIO_SZ 1
++#define IRQ_BEACON_DONE_MSK 0x00000008
++#define IRQ_BEACON_DONE_I_MSK 0xfffffff7
++#define IRQ_BEACON_DONE_SFT 3
++#define IRQ_BEACON_DONE_HI 3
++#define IRQ_BEACON_DONE_SZ 1
++#define IRQ_BEACON_MSK 0x00000010
++#define IRQ_BEACON_I_MSK 0xffffffef
++#define IRQ_BEACON_SFT 4
++#define IRQ_BEACON_HI 4
++#define IRQ_BEACON_SZ 1
++#define IRQ_PRE_BEACON_MSK 0x00000020
++#define IRQ_PRE_BEACON_I_MSK 0xffffffdf
++#define IRQ_PRE_BEACON_SFT 5
++#define IRQ_PRE_BEACON_HI 5
++#define IRQ_PRE_BEACON_SZ 1
++#define IRQ_EDCA0_TX_DONE_MSK 0x00000040
++#define IRQ_EDCA0_TX_DONE_I_MSK 0xffffffbf
++#define IRQ_EDCA0_TX_DONE_SFT 6
++#define IRQ_EDCA0_TX_DONE_HI 6
++#define IRQ_EDCA0_TX_DONE_SZ 1
++#define IRQ_EDCA1_TX_DONE_MSK 0x00000080
++#define IRQ_EDCA1_TX_DONE_I_MSK 0xffffff7f
++#define IRQ_EDCA1_TX_DONE_SFT 7
++#define IRQ_EDCA1_TX_DONE_HI 7
++#define IRQ_EDCA1_TX_DONE_SZ 1
++#define IRQ_EDCA2_TX_DONE_MSK 0x00000100
++#define IRQ_EDCA2_TX_DONE_I_MSK 0xfffffeff
++#define IRQ_EDCA2_TX_DONE_SFT 8
++#define IRQ_EDCA2_TX_DONE_HI 8
++#define IRQ_EDCA2_TX_DONE_SZ 1
++#define IRQ_EDCA3_TX_DONE_MSK 0x00000200
++#define IRQ_EDCA3_TX_DONE_I_MSK 0xfffffdff
++#define IRQ_EDCA3_TX_DONE_SFT 9
++#define IRQ_EDCA3_TX_DONE_HI 9
++#define IRQ_EDCA3_TX_DONE_SZ 1
++#define IRQ_EDCA4_TX_DONE_MSK 0x00000400
++#define IRQ_EDCA4_TX_DONE_I_MSK 0xfffffbff
++#define IRQ_EDCA4_TX_DONE_SFT 10
++#define IRQ_EDCA4_TX_DONE_HI 10
++#define IRQ_EDCA4_TX_DONE_SZ 1
++#define IRQ_BEACON_DTIM_MSK 0x00001000
++#define IRQ_BEACON_DTIM_I_MSK 0xffffefff
++#define IRQ_BEACON_DTIM_SFT 12
++#define IRQ_BEACON_DTIM_HI 12
++#define IRQ_BEACON_DTIM_SZ 1
++#define IRQ_EDCA0_LOWTHOLD_INT_MSK 0x00002000
++#define IRQ_EDCA0_LOWTHOLD_INT_I_MSK 0xffffdfff
++#define IRQ_EDCA0_LOWTHOLD_INT_SFT 13
++#define IRQ_EDCA0_LOWTHOLD_INT_HI 13
++#define IRQ_EDCA0_LOWTHOLD_INT_SZ 1
++#define IRQ_EDCA1_LOWTHOLD_INT_MSK 0x00004000
++#define IRQ_EDCA1_LOWTHOLD_INT_I_MSK 0xffffbfff
++#define IRQ_EDCA1_LOWTHOLD_INT_SFT 14
++#define IRQ_EDCA1_LOWTHOLD_INT_HI 14
++#define IRQ_EDCA1_LOWTHOLD_INT_SZ 1
++#define IRQ_EDCA2_LOWTHOLD_INT_MSK 0x00008000
++#define IRQ_EDCA2_LOWTHOLD_INT_I_MSK 0xffff7fff
++#define IRQ_EDCA2_LOWTHOLD_INT_SFT 15
++#define IRQ_EDCA2_LOWTHOLD_INT_HI 15
++#define IRQ_EDCA2_LOWTHOLD_INT_SZ 1
++#define IRQ_EDCA3_LOWTHOLD_INT_MSK 0x00010000
++#define IRQ_EDCA3_LOWTHOLD_INT_I_MSK 0xfffeffff
++#define IRQ_EDCA3_LOWTHOLD_INT_SFT 16
++#define IRQ_EDCA3_LOWTHOLD_INT_HI 16
++#define IRQ_EDCA3_LOWTHOLD_INT_SZ 1
++#define IRQ_FENCE_HIT_INT_MSK 0x00020000
++#define IRQ_FENCE_HIT_INT_I_MSK 0xfffdffff
++#define IRQ_FENCE_HIT_INT_SFT 17
++#define IRQ_FENCE_HIT_INT_HI 17
++#define IRQ_FENCE_HIT_INT_SZ 1
++#define IRQ_ILL_ADDR_INT_MSK 0x00040000
++#define IRQ_ILL_ADDR_INT_I_MSK 0xfffbffff
++#define IRQ_ILL_ADDR_INT_SFT 18
++#define IRQ_ILL_ADDR_INT_HI 18
++#define IRQ_ILL_ADDR_INT_SZ 1
++#define IRQ_MBOX_MSK 0x00080000
++#define IRQ_MBOX_I_MSK 0xfff7ffff
++#define IRQ_MBOX_SFT 19
++#define IRQ_MBOX_HI 19
++#define IRQ_MBOX_SZ 1
++#define IRQ_US_TIMER0_MSK 0x00100000
++#define IRQ_US_TIMER0_I_MSK 0xffefffff
++#define IRQ_US_TIMER0_SFT 20
++#define IRQ_US_TIMER0_HI 20
++#define IRQ_US_TIMER0_SZ 1
++#define IRQ_US_TIMER1_MSK 0x00200000
++#define IRQ_US_TIMER1_I_MSK 0xffdfffff
++#define IRQ_US_TIMER1_SFT 21
++#define IRQ_US_TIMER1_HI 21
++#define IRQ_US_TIMER1_SZ 1
++#define IRQ_US_TIMER2_MSK 0x00400000
++#define IRQ_US_TIMER2_I_MSK 0xffbfffff
++#define IRQ_US_TIMER2_SFT 22
++#define IRQ_US_TIMER2_HI 22
++#define IRQ_US_TIMER2_SZ 1
++#define IRQ_US_TIMER3_MSK 0x00800000
++#define IRQ_US_TIMER3_I_MSK 0xff7fffff
++#define IRQ_US_TIMER3_SFT 23
++#define IRQ_US_TIMER3_HI 23
++#define IRQ_US_TIMER3_SZ 1
++#define IRQ_MS_TIMER0_MSK 0x01000000
++#define IRQ_MS_TIMER0_I_MSK 0xfeffffff
++#define IRQ_MS_TIMER0_SFT 24
++#define IRQ_MS_TIMER0_HI 24
++#define IRQ_MS_TIMER0_SZ 1
++#define IRQ_MS_TIMER1_MSK 0x02000000
++#define IRQ_MS_TIMER1_I_MSK 0xfdffffff
++#define IRQ_MS_TIMER1_SFT 25
++#define IRQ_MS_TIMER1_HI 25
++#define IRQ_MS_TIMER1_SZ 1
++#define IRQ_MS_TIMER2_MSK 0x04000000
++#define IRQ_MS_TIMER2_I_MSK 0xfbffffff
++#define IRQ_MS_TIMER2_SFT 26
++#define IRQ_MS_TIMER2_HI 26
++#define IRQ_MS_TIMER2_SZ 1
++#define IRQ_MS_TIMER3_MSK 0x08000000
++#define IRQ_MS_TIMER3_I_MSK 0xf7ffffff
++#define IRQ_MS_TIMER3_SFT 27
++#define IRQ_MS_TIMER3_HI 27
++#define IRQ_MS_TIMER3_SZ 1
++#define IRQ_TX_LIMIT_INT_MSK 0x10000000
++#define IRQ_TX_LIMIT_INT_I_MSK 0xefffffff
++#define IRQ_TX_LIMIT_INT_SFT 28
++#define IRQ_TX_LIMIT_INT_HI 28
++#define IRQ_TX_LIMIT_INT_SZ 1
++#define IRQ_DMA0_MSK 0x20000000
++#define IRQ_DMA0_I_MSK 0xdfffffff
++#define IRQ_DMA0_SFT 29
++#define IRQ_DMA0_HI 29
++#define IRQ_DMA0_SZ 1
++#define IRQ_CO_DMA_MSK 0x40000000
++#define IRQ_CO_DMA_I_MSK 0xbfffffff
++#define IRQ_CO_DMA_SFT 30
++#define IRQ_CO_DMA_HI 30
++#define IRQ_CO_DMA_SZ 1
++#define IRQ_PERI_GROUP_MSK 0x80000000
++#define IRQ_PERI_GROUP_I_MSK 0x7fffffff
++#define IRQ_PERI_GROUP_SFT 31
++#define IRQ_PERI_GROUP_HI 31
++#define IRQ_PERI_GROUP_SZ 1
++#define FIQ_STATUS_MSK 0xffffffff
++#define FIQ_STATUS_I_MSK 0x00000000
++#define FIQ_STATUS_SFT 0
++#define FIQ_STATUS_HI 31
++#define FIQ_STATUS_SZ 32
++#define IRQ_RAW_MSK 0xffffffff
++#define IRQ_RAW_I_MSK 0x00000000
++#define IRQ_RAW_SFT 0
++#define IRQ_RAW_HI 31
++#define IRQ_RAW_SZ 32
++#define FIQ_RAW_MSK 0xffffffff
++#define FIQ_RAW_I_MSK 0x00000000
++#define FIQ_RAW_SFT 0
++#define FIQ_RAW_HI 31
++#define FIQ_RAW_SZ 32
++#define INT_PERI_MASK_MSK 0xffffffff
++#define INT_PERI_MASK_I_MSK 0x00000000
++#define INT_PERI_MASK_SFT 0
++#define INT_PERI_MASK_HI 31
++#define INT_PERI_MASK_SZ 32
++#define PERI_RTC_MSK 0x00000001
++#define PERI_RTC_I_MSK 0xfffffffe
++#define PERI_RTC_SFT 0
++#define PERI_RTC_HI 0
++#define PERI_RTC_SZ 1
++#define IRQ_UART0_TX_MSK 0x00000002
++#define IRQ_UART0_TX_I_MSK 0xfffffffd
++#define IRQ_UART0_TX_SFT 1
++#define IRQ_UART0_TX_HI 1
++#define IRQ_UART0_TX_SZ 1
++#define IRQ_UART0_RX_MSK 0x00000004
++#define IRQ_UART0_RX_I_MSK 0xfffffffb
++#define IRQ_UART0_RX_SFT 2
++#define IRQ_UART0_RX_HI 2
++#define IRQ_UART0_RX_SZ 1
++#define PERI_GPI_2_MSK 0x00000008
++#define PERI_GPI_2_I_MSK 0xfffffff7
++#define PERI_GPI_2_SFT 3
++#define PERI_GPI_2_HI 3
++#define PERI_GPI_2_SZ 1
++#define IRQ_SPI_IPC_MSK 0x00000010
++#define IRQ_SPI_IPC_I_MSK 0xffffffef
++#define IRQ_SPI_IPC_SFT 4
++#define IRQ_SPI_IPC_HI 4
++#define IRQ_SPI_IPC_SZ 1
++#define PERI_GPI_1_0_MSK 0x00000060
++#define PERI_GPI_1_0_I_MSK 0xffffff9f
++#define PERI_GPI_1_0_SFT 5
++#define PERI_GPI_1_0_HI 6
++#define PERI_GPI_1_0_SZ 2
++#define SCRT_INT_1_MSK 0x00000080
++#define SCRT_INT_1_I_MSK 0xffffff7f
++#define SCRT_INT_1_SFT 7
++#define SCRT_INT_1_HI 7
++#define SCRT_INT_1_SZ 1
++#define MMU_ALC_ERR_MSK 0x00000100
++#define MMU_ALC_ERR_I_MSK 0xfffffeff
++#define MMU_ALC_ERR_SFT 8
++#define MMU_ALC_ERR_HI 8
++#define MMU_ALC_ERR_SZ 1
++#define MMU_RLS_ERR_MSK 0x00000200
++#define MMU_RLS_ERR_I_MSK 0xfffffdff
++#define MMU_RLS_ERR_SFT 9
++#define MMU_RLS_ERR_HI 9
++#define MMU_RLS_ERR_SZ 1
++#define ID_MNG_INT_1_MSK 0x00000400
++#define ID_MNG_INT_1_I_MSK 0xfffffbff
++#define ID_MNG_INT_1_SFT 10
++#define ID_MNG_INT_1_HI 10
++#define ID_MNG_INT_1_SZ 1
++#define MBOX_INT_1_MSK 0x00000800
++#define MBOX_INT_1_I_MSK 0xfffff7ff
++#define MBOX_INT_1_SFT 11
++#define MBOX_INT_1_HI 11
++#define MBOX_INT_1_SZ 1
++#define MBOX_INT_2_MSK 0x00001000
++#define MBOX_INT_2_I_MSK 0xffffefff
++#define MBOX_INT_2_SFT 12
++#define MBOX_INT_2_HI 12
++#define MBOX_INT_2_SZ 1
++#define MBOX_INT_3_MSK 0x00002000
++#define MBOX_INT_3_I_MSK 0xffffdfff
++#define MBOX_INT_3_SFT 13
++#define MBOX_INT_3_HI 13
++#define MBOX_INT_3_SZ 1
++#define HCI_INT_1_MSK 0x00004000
++#define HCI_INT_1_I_MSK 0xffffbfff
++#define HCI_INT_1_SFT 14
++#define HCI_INT_1_HI 14
++#define HCI_INT_1_SZ 1
++#define UART_RX_TIMEOUT_MSK 0x00008000
++#define UART_RX_TIMEOUT_I_MSK 0xffff7fff
++#define UART_RX_TIMEOUT_SFT 15
++#define UART_RX_TIMEOUT_HI 15
++#define UART_RX_TIMEOUT_SZ 1
++#define UART_MULTI_IRQ_MSK 0x00010000
++#define UART_MULTI_IRQ_I_MSK 0xfffeffff
++#define UART_MULTI_IRQ_SFT 16
++#define UART_MULTI_IRQ_HI 16
++#define UART_MULTI_IRQ_SZ 1
++#define ID_MNG_INT_2_MSK 0x00020000
++#define ID_MNG_INT_2_I_MSK 0xfffdffff
++#define ID_MNG_INT_2_SFT 17
++#define ID_MNG_INT_2_HI 17
++#define ID_MNG_INT_2_SZ 1
++#define DMN_NOHIT_INT_MSK 0x00040000
++#define DMN_NOHIT_INT_I_MSK 0xfffbffff
++#define DMN_NOHIT_INT_SFT 18
++#define DMN_NOHIT_INT_HI 18
++#define DMN_NOHIT_INT_SZ 1
++#define ID_THOLD_RX_MSK 0x00080000
++#define ID_THOLD_RX_I_MSK 0xfff7ffff
++#define ID_THOLD_RX_SFT 19
++#define ID_THOLD_RX_HI 19
++#define ID_THOLD_RX_SZ 1
++#define ID_THOLD_TX_MSK 0x00100000
++#define ID_THOLD_TX_I_MSK 0xffefffff
++#define ID_THOLD_TX_SFT 20
++#define ID_THOLD_TX_HI 20
++#define ID_THOLD_TX_SZ 1
++#define ID_DOUBLE_RLS_MSK 0x00200000
++#define ID_DOUBLE_RLS_I_MSK 0xffdfffff
++#define ID_DOUBLE_RLS_SFT 21
++#define ID_DOUBLE_RLS_HI 21
++#define ID_DOUBLE_RLS_SZ 1
++#define RX_ID_LEN_THOLD_MSK 0x00400000
++#define RX_ID_LEN_THOLD_I_MSK 0xffbfffff
++#define RX_ID_LEN_THOLD_SFT 22
++#define RX_ID_LEN_THOLD_HI 22
++#define RX_ID_LEN_THOLD_SZ 1
++#define TX_ID_LEN_THOLD_MSK 0x00800000
++#define TX_ID_LEN_THOLD_I_MSK 0xff7fffff
++#define TX_ID_LEN_THOLD_SFT 23
++#define TX_ID_LEN_THOLD_HI 23
++#define TX_ID_LEN_THOLD_SZ 1
++#define ALL_ID_LEN_THOLD_MSK 0x01000000
++#define ALL_ID_LEN_THOLD_I_MSK 0xfeffffff
++#define ALL_ID_LEN_THOLD_SFT 24
++#define ALL_ID_LEN_THOLD_HI 24
++#define ALL_ID_LEN_THOLD_SZ 1
++#define DMN_MCU_INT_MSK 0x02000000
++#define DMN_MCU_INT_I_MSK 0xfdffffff
++#define DMN_MCU_INT_SFT 25
++#define DMN_MCU_INT_HI 25
++#define DMN_MCU_INT_SZ 1
++#define IRQ_DAT_UART_TX_MSK 0x04000000
++#define IRQ_DAT_UART_TX_I_MSK 0xfbffffff
++#define IRQ_DAT_UART_TX_SFT 26
++#define IRQ_DAT_UART_TX_HI 26
++#define IRQ_DAT_UART_TX_SZ 1
++#define IRQ_DAT_UART_RX_MSK 0x08000000
++#define IRQ_DAT_UART_RX_I_MSK 0xf7ffffff
++#define IRQ_DAT_UART_RX_SFT 27
++#define IRQ_DAT_UART_RX_HI 27
++#define IRQ_DAT_UART_RX_SZ 1
++#define DAT_UART_RX_TIMEOUT_MSK 0x10000000
++#define DAT_UART_RX_TIMEOUT_I_MSK 0xefffffff
++#define DAT_UART_RX_TIMEOUT_SFT 28
++#define DAT_UART_RX_TIMEOUT_HI 28
++#define DAT_UART_RX_TIMEOUT_SZ 1
++#define DAT_UART_MULTI_IRQ_MSK 0x20000000
++#define DAT_UART_MULTI_IRQ_I_MSK 0xdfffffff
++#define DAT_UART_MULTI_IRQ_SFT 29
++#define DAT_UART_MULTI_IRQ_HI 29
++#define DAT_UART_MULTI_IRQ_SZ 1
++#define ALR_ABT_NOCHG_INT_IRQ_MSK 0x40000000
++#define ALR_ABT_NOCHG_INT_IRQ_I_MSK 0xbfffffff
++#define ALR_ABT_NOCHG_INT_IRQ_SFT 30
++#define ALR_ABT_NOCHG_INT_IRQ_HI 30
++#define ALR_ABT_NOCHG_INT_IRQ_SZ 1
++#define TBLNEQ_MNGPKT_INT_IRQ_MSK 0x80000000
++#define TBLNEQ_MNGPKT_INT_IRQ_I_MSK 0x7fffffff
++#define TBLNEQ_MNGPKT_INT_IRQ_SFT 31
++#define TBLNEQ_MNGPKT_INT_IRQ_HI 31
++#define TBLNEQ_MNGPKT_INT_IRQ_SZ 1
++#define INTR_PERI_RAW_MSK 0xffffffff
++#define INTR_PERI_RAW_I_MSK 0x00000000
++#define INTR_PERI_RAW_SFT 0
++#define INTR_PERI_RAW_HI 31
++#define INTR_PERI_RAW_SZ 32
++#define INTR_GPI00_CFG_MSK 0x00000003
++#define INTR_GPI00_CFG_I_MSK 0xfffffffc
++#define INTR_GPI00_CFG_SFT 0
++#define INTR_GPI00_CFG_HI 1
++#define INTR_GPI00_CFG_SZ 2
++#define INTR_GPI01_CFG_MSK 0x0000000c
++#define INTR_GPI01_CFG_I_MSK 0xfffffff3
++#define INTR_GPI01_CFG_SFT 2
++#define INTR_GPI01_CFG_HI 3
++#define INTR_GPI01_CFG_SZ 2
++#define SYS_RST_INT_MSK 0x00000001
++#define SYS_RST_INT_I_MSK 0xfffffffe
++#define SYS_RST_INT_SFT 0
++#define SYS_RST_INT_HI 0
++#define SYS_RST_INT_SZ 1
++#define SPI_IPC_ADDR_MSK 0xffffffff
++#define SPI_IPC_ADDR_I_MSK 0x00000000
++#define SPI_IPC_ADDR_SFT 0
++#define SPI_IPC_ADDR_HI 31
++#define SPI_IPC_ADDR_SZ 32
++#define SD_MASK_TOP_MSK 0xffffffff
++#define SD_MASK_TOP_I_MSK 0x00000000
++#define SD_MASK_TOP_SFT 0
++#define SD_MASK_TOP_HI 31
++#define SD_MASK_TOP_SZ 32
++#define IRQ_PHY_0_SD_MSK 0x00000001
++#define IRQ_PHY_0_SD_I_MSK 0xfffffffe
++#define IRQ_PHY_0_SD_SFT 0
++#define IRQ_PHY_0_SD_HI 0
++#define IRQ_PHY_0_SD_SZ 1
++#define IRQ_PHY_1_SD_MSK 0x00000002
++#define IRQ_PHY_1_SD_I_MSK 0xfffffffd
++#define IRQ_PHY_1_SD_SFT 1
++#define IRQ_PHY_1_SD_HI 1
++#define IRQ_PHY_1_SD_SZ 1
++#define IRQ_SDIO_SD_MSK 0x00000004
++#define IRQ_SDIO_SD_I_MSK 0xfffffffb
++#define IRQ_SDIO_SD_SFT 2
++#define IRQ_SDIO_SD_HI 2
++#define IRQ_SDIO_SD_SZ 1
++#define IRQ_BEACON_DONE_SD_MSK 0x00000008
++#define IRQ_BEACON_DONE_SD_I_MSK 0xfffffff7
++#define IRQ_BEACON_DONE_SD_SFT 3
++#define IRQ_BEACON_DONE_SD_HI 3
++#define IRQ_BEACON_DONE_SD_SZ 1
++#define IRQ_BEACON_SD_MSK 0x00000010
++#define IRQ_BEACON_SD_I_MSK 0xffffffef
++#define IRQ_BEACON_SD_SFT 4
++#define IRQ_BEACON_SD_HI 4
++#define IRQ_BEACON_SD_SZ 1
++#define IRQ_PRE_BEACON_SD_MSK 0x00000020
++#define IRQ_PRE_BEACON_SD_I_MSK 0xffffffdf
++#define IRQ_PRE_BEACON_SD_SFT 5
++#define IRQ_PRE_BEACON_SD_HI 5
++#define IRQ_PRE_BEACON_SD_SZ 1
++#define IRQ_EDCA0_TX_DONE_SD_MSK 0x00000040
++#define IRQ_EDCA0_TX_DONE_SD_I_MSK 0xffffffbf
++#define IRQ_EDCA0_TX_DONE_SD_SFT 6
++#define IRQ_EDCA0_TX_DONE_SD_HI 6
++#define IRQ_EDCA0_TX_DONE_SD_SZ 1
++#define IRQ_EDCA1_TX_DONE_SD_MSK 0x00000080
++#define IRQ_EDCA1_TX_DONE_SD_I_MSK 0xffffff7f
++#define IRQ_EDCA1_TX_DONE_SD_SFT 7
++#define IRQ_EDCA1_TX_DONE_SD_HI 7
++#define IRQ_EDCA1_TX_DONE_SD_SZ 1
++#define IRQ_EDCA2_TX_DONE_SD_MSK 0x00000100
++#define IRQ_EDCA2_TX_DONE_SD_I_MSK 0xfffffeff
++#define IRQ_EDCA2_TX_DONE_SD_SFT 8
++#define IRQ_EDCA2_TX_DONE_SD_HI 8
++#define IRQ_EDCA2_TX_DONE_SD_SZ 1
++#define IRQ_EDCA3_TX_DONE_SD_MSK 0x00000200
++#define IRQ_EDCA3_TX_DONE_SD_I_MSK 0xfffffdff
++#define IRQ_EDCA3_TX_DONE_SD_SFT 9
++#define IRQ_EDCA3_TX_DONE_SD_HI 9
++#define IRQ_EDCA3_TX_DONE_SD_SZ 1
++#define IRQ_EDCA4_TX_DONE_SD_MSK 0x00000400
++#define IRQ_EDCA4_TX_DONE_SD_I_MSK 0xfffffbff
++#define IRQ_EDCA4_TX_DONE_SD_SFT 10
++#define IRQ_EDCA4_TX_DONE_SD_HI 10
++#define IRQ_EDCA4_TX_DONE_SD_SZ 1
++#define IRQ_BEACON_DTIM_SD_MSK 0x00001000
++#define IRQ_BEACON_DTIM_SD_I_MSK 0xffffefff
++#define IRQ_BEACON_DTIM_SD_SFT 12
++#define IRQ_BEACON_DTIM_SD_HI 12
++#define IRQ_BEACON_DTIM_SD_SZ 1
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_MSK 0x00002000
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK 0xffffdfff
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_SFT 13
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_HI 13
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_MSK 0x00004000
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK 0xffffbfff
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_SFT 14
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_HI 14
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_MSK 0x00008000
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK 0xffff7fff
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_SFT 15
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_HI 15
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_MSK 0x00010000
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK 0xfffeffff
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_SFT 16
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_HI 16
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_FENCE_HIT_INT_SD_MSK 0x00020000
++#define IRQ_FENCE_HIT_INT_SD_I_MSK 0xfffdffff
++#define IRQ_FENCE_HIT_INT_SD_SFT 17
++#define IRQ_FENCE_HIT_INT_SD_HI 17
++#define IRQ_FENCE_HIT_INT_SD_SZ 1
++#define IRQ_ILL_ADDR_INT_SD_MSK 0x00040000
++#define IRQ_ILL_ADDR_INT_SD_I_MSK 0xfffbffff
++#define IRQ_ILL_ADDR_INT_SD_SFT 18
++#define IRQ_ILL_ADDR_INT_SD_HI 18
++#define IRQ_ILL_ADDR_INT_SD_SZ 1
++#define IRQ_MBOX_SD_MSK 0x00080000
++#define IRQ_MBOX_SD_I_MSK 0xfff7ffff
++#define IRQ_MBOX_SD_SFT 19
++#define IRQ_MBOX_SD_HI 19
++#define IRQ_MBOX_SD_SZ 1
++#define IRQ_US_TIMER0_SD_MSK 0x00100000
++#define IRQ_US_TIMER0_SD_I_MSK 0xffefffff
++#define IRQ_US_TIMER0_SD_SFT 20
++#define IRQ_US_TIMER0_SD_HI 20
++#define IRQ_US_TIMER0_SD_SZ 1
++#define IRQ_US_TIMER1_SD_MSK 0x00200000
++#define IRQ_US_TIMER1_SD_I_MSK 0xffdfffff
++#define IRQ_US_TIMER1_SD_SFT 21
++#define IRQ_US_TIMER1_SD_HI 21
++#define IRQ_US_TIMER1_SD_SZ 1
++#define IRQ_US_TIMER2_SD_MSK 0x00400000
++#define IRQ_US_TIMER2_SD_I_MSK 0xffbfffff
++#define IRQ_US_TIMER2_SD_SFT 22
++#define IRQ_US_TIMER2_SD_HI 22
++#define IRQ_US_TIMER2_SD_SZ 1
++#define IRQ_US_TIMER3_SD_MSK 0x00800000
++#define IRQ_US_TIMER3_SD_I_MSK 0xff7fffff
++#define IRQ_US_TIMER3_SD_SFT 23
++#define IRQ_US_TIMER3_SD_HI 23
++#define IRQ_US_TIMER3_SD_SZ 1
++#define IRQ_MS_TIMER0_SD_MSK 0x01000000
++#define IRQ_MS_TIMER0_SD_I_MSK 0xfeffffff
++#define IRQ_MS_TIMER0_SD_SFT 24
++#define IRQ_MS_TIMER0_SD_HI 24
++#define IRQ_MS_TIMER0_SD_SZ 1
++#define IRQ_MS_TIMER1_SD_MSK 0x02000000
++#define IRQ_MS_TIMER1_SD_I_MSK 0xfdffffff
++#define IRQ_MS_TIMER1_SD_SFT 25
++#define IRQ_MS_TIMER1_SD_HI 25
++#define IRQ_MS_TIMER1_SD_SZ 1
++#define IRQ_MS_TIMER2_SD_MSK 0x04000000
++#define IRQ_MS_TIMER2_SD_I_MSK 0xfbffffff
++#define IRQ_MS_TIMER2_SD_SFT 26
++#define IRQ_MS_TIMER2_SD_HI 26
++#define IRQ_MS_TIMER2_SD_SZ 1
++#define IRQ_MS_TIMER3_SD_MSK 0x08000000
++#define IRQ_MS_TIMER3_SD_I_MSK 0xf7ffffff
++#define IRQ_MS_TIMER3_SD_SFT 27
++#define IRQ_MS_TIMER3_SD_HI 27
++#define IRQ_MS_TIMER3_SD_SZ 1
++#define IRQ_TX_LIMIT_INT_SD_MSK 0x10000000
++#define IRQ_TX_LIMIT_INT_SD_I_MSK 0xefffffff
++#define IRQ_TX_LIMIT_INT_SD_SFT 28
++#define IRQ_TX_LIMIT_INT_SD_HI 28
++#define IRQ_TX_LIMIT_INT_SD_SZ 1
++#define IRQ_DMA0_SD_MSK 0x20000000
++#define IRQ_DMA0_SD_I_MSK 0xdfffffff
++#define IRQ_DMA0_SD_SFT 29
++#define IRQ_DMA0_SD_HI 29
++#define IRQ_DMA0_SD_SZ 1
++#define IRQ_CO_DMA_SD_MSK 0x40000000
++#define IRQ_CO_DMA_SD_I_MSK 0xbfffffff
++#define IRQ_CO_DMA_SD_SFT 30
++#define IRQ_CO_DMA_SD_HI 30
++#define IRQ_CO_DMA_SD_SZ 1
++#define IRQ_PERI_GROUP_SD_MSK 0x80000000
++#define IRQ_PERI_GROUP_SD_I_MSK 0x7fffffff
++#define IRQ_PERI_GROUP_SD_SFT 31
++#define IRQ_PERI_GROUP_SD_HI 31
++#define IRQ_PERI_GROUP_SD_SZ 1
++#define INT_PERI_MASK_SD_MSK 0xffffffff
++#define INT_PERI_MASK_SD_I_MSK 0x00000000
++#define INT_PERI_MASK_SD_SFT 0
++#define INT_PERI_MASK_SD_HI 31
++#define INT_PERI_MASK_SD_SZ 32
++#define PERI_RTC_SD_MSK 0x00000001
++#define PERI_RTC_SD_I_MSK 0xfffffffe
++#define PERI_RTC_SD_SFT 0
++#define PERI_RTC_SD_HI 0
++#define PERI_RTC_SD_SZ 1
++#define IRQ_UART0_TX_SD_MSK 0x00000002
++#define IRQ_UART0_TX_SD_I_MSK 0xfffffffd
++#define IRQ_UART0_TX_SD_SFT 1
++#define IRQ_UART0_TX_SD_HI 1
++#define IRQ_UART0_TX_SD_SZ 1
++#define IRQ_UART0_RX_SD_MSK 0x00000004
++#define IRQ_UART0_RX_SD_I_MSK 0xfffffffb
++#define IRQ_UART0_RX_SD_SFT 2
++#define IRQ_UART0_RX_SD_HI 2
++#define IRQ_UART0_RX_SD_SZ 1
++#define PERI_GPI_SD_2_MSK 0x00000008
++#define PERI_GPI_SD_2_I_MSK 0xfffffff7
++#define PERI_GPI_SD_2_SFT 3
++#define PERI_GPI_SD_2_HI 3
++#define PERI_GPI_SD_2_SZ 1
++#define IRQ_SPI_IPC_SD_MSK 0x00000010
++#define IRQ_SPI_IPC_SD_I_MSK 0xffffffef
++#define IRQ_SPI_IPC_SD_SFT 4
++#define IRQ_SPI_IPC_SD_HI 4
++#define IRQ_SPI_IPC_SD_SZ 1
++#define PERI_GPI_SD_1_0_MSK 0x00000060
++#define PERI_GPI_SD_1_0_I_MSK 0xffffff9f
++#define PERI_GPI_SD_1_0_SFT 5
++#define PERI_GPI_SD_1_0_HI 6
++#define PERI_GPI_SD_1_0_SZ 2
++#define SCRT_INT_1_SD_MSK 0x00000080
++#define SCRT_INT_1_SD_I_MSK 0xffffff7f
++#define SCRT_INT_1_SD_SFT 7
++#define SCRT_INT_1_SD_HI 7
++#define SCRT_INT_1_SD_SZ 1
++#define MMU_ALC_ERR_SD_MSK 0x00000100
++#define MMU_ALC_ERR_SD_I_MSK 0xfffffeff
++#define MMU_ALC_ERR_SD_SFT 8
++#define MMU_ALC_ERR_SD_HI 8
++#define MMU_ALC_ERR_SD_SZ 1
++#define MMU_RLS_ERR_SD_MSK 0x00000200
++#define MMU_RLS_ERR_SD_I_MSK 0xfffffdff
++#define MMU_RLS_ERR_SD_SFT 9
++#define MMU_RLS_ERR_SD_HI 9
++#define MMU_RLS_ERR_SD_SZ 1
++#define ID_MNG_INT_1_SD_MSK 0x00000400
++#define ID_MNG_INT_1_SD_I_MSK 0xfffffbff
++#define ID_MNG_INT_1_SD_SFT 10
++#define ID_MNG_INT_1_SD_HI 10
++#define ID_MNG_INT_1_SD_SZ 1
++#define MBOX_INT_1_SD_MSK 0x00000800
++#define MBOX_INT_1_SD_I_MSK 0xfffff7ff
++#define MBOX_INT_1_SD_SFT 11
++#define MBOX_INT_1_SD_HI 11
++#define MBOX_INT_1_SD_SZ 1
++#define MBOX_INT_2_SD_MSK 0x00001000
++#define MBOX_INT_2_SD_I_MSK 0xffffefff
++#define MBOX_INT_2_SD_SFT 12
++#define MBOX_INT_2_SD_HI 12
++#define MBOX_INT_2_SD_SZ 1
++#define MBOX_INT_3_SD_MSK 0x00002000
++#define MBOX_INT_3_SD_I_MSK 0xffffdfff
++#define MBOX_INT_3_SD_SFT 13
++#define MBOX_INT_3_SD_HI 13
++#define MBOX_INT_3_SD_SZ 1
++#define HCI_INT_1_SD_MSK 0x00004000
++#define HCI_INT_1_SD_I_MSK 0xffffbfff
++#define HCI_INT_1_SD_SFT 14
++#define HCI_INT_1_SD_HI 14
++#define HCI_INT_1_SD_SZ 1
++#define UART_RX_TIMEOUT_SD_MSK 0x00008000
++#define UART_RX_TIMEOUT_SD_I_MSK 0xffff7fff
++#define UART_RX_TIMEOUT_SD_SFT 15
++#define UART_RX_TIMEOUT_SD_HI 15
++#define UART_RX_TIMEOUT_SD_SZ 1
++#define UART_MULTI_IRQ_SD_MSK 0x00010000
++#define UART_MULTI_IRQ_SD_I_MSK 0xfffeffff
++#define UART_MULTI_IRQ_SD_SFT 16
++#define UART_MULTI_IRQ_SD_HI 16
++#define UART_MULTI_IRQ_SD_SZ 1
++#define ID_MNG_INT_2_SD_MSK 0x00020000
++#define ID_MNG_INT_2_SD_I_MSK 0xfffdffff
++#define ID_MNG_INT_2_SD_SFT 17
++#define ID_MNG_INT_2_SD_HI 17
++#define ID_MNG_INT_2_SD_SZ 1
++#define DMN_NOHIT_INT_SD_MSK 0x00040000
++#define DMN_NOHIT_INT_SD_I_MSK 0xfffbffff
++#define DMN_NOHIT_INT_SD_SFT 18
++#define DMN_NOHIT_INT_SD_HI 18
++#define DMN_NOHIT_INT_SD_SZ 1
++#define ID_THOLD_RX_SD_MSK 0x00080000
++#define ID_THOLD_RX_SD_I_MSK 0xfff7ffff
++#define ID_THOLD_RX_SD_SFT 19
++#define ID_THOLD_RX_SD_HI 19
++#define ID_THOLD_RX_SD_SZ 1
++#define ID_THOLD_TX_SD_MSK 0x00100000
++#define ID_THOLD_TX_SD_I_MSK 0xffefffff
++#define ID_THOLD_TX_SD_SFT 20
++#define ID_THOLD_TX_SD_HI 20
++#define ID_THOLD_TX_SD_SZ 1
++#define ID_DOUBLE_RLS_SD_MSK 0x00200000
++#define ID_DOUBLE_RLS_SD_I_MSK 0xffdfffff
++#define ID_DOUBLE_RLS_SD_SFT 21
++#define ID_DOUBLE_RLS_SD_HI 21
++#define ID_DOUBLE_RLS_SD_SZ 1
++#define RX_ID_LEN_THOLD_SD_MSK 0x00400000
++#define RX_ID_LEN_THOLD_SD_I_MSK 0xffbfffff
++#define RX_ID_LEN_THOLD_SD_SFT 22
++#define RX_ID_LEN_THOLD_SD_HI 22
++#define RX_ID_LEN_THOLD_SD_SZ 1
++#define TX_ID_LEN_THOLD_SD_MSK 0x00800000
++#define TX_ID_LEN_THOLD_SD_I_MSK 0xff7fffff
++#define TX_ID_LEN_THOLD_SD_SFT 23
++#define TX_ID_LEN_THOLD_SD_HI 23
++#define TX_ID_LEN_THOLD_SD_SZ 1
++#define ALL_ID_LEN_THOLD_SD_MSK 0x01000000
++#define ALL_ID_LEN_THOLD_SD_I_MSK 0xfeffffff
++#define ALL_ID_LEN_THOLD_SD_SFT 24
++#define ALL_ID_LEN_THOLD_SD_HI 24
++#define ALL_ID_LEN_THOLD_SD_SZ 1
++#define DMN_MCU_INT_SD_MSK 0x02000000
++#define DMN_MCU_INT_SD_I_MSK 0xfdffffff
++#define DMN_MCU_INT_SD_SFT 25
++#define DMN_MCU_INT_SD_HI 25
++#define DMN_MCU_INT_SD_SZ 1
++#define IRQ_DAT_UART_TX_SD_MSK 0x04000000
++#define IRQ_DAT_UART_TX_SD_I_MSK 0xfbffffff
++#define IRQ_DAT_UART_TX_SD_SFT 26
++#define IRQ_DAT_UART_TX_SD_HI 26
++#define IRQ_DAT_UART_TX_SD_SZ 1
++#define IRQ_DAT_UART_RX_SD_MSK 0x08000000
++#define IRQ_DAT_UART_RX_SD_I_MSK 0xf7ffffff
++#define IRQ_DAT_UART_RX_SD_SFT 27
++#define IRQ_DAT_UART_RX_SD_HI 27
++#define IRQ_DAT_UART_RX_SD_SZ 1
++#define DAT_UART_RX_TIMEOUT_SD_MSK 0x10000000
++#define DAT_UART_RX_TIMEOUT_SD_I_MSK 0xefffffff
++#define DAT_UART_RX_TIMEOUT_SD_SFT 28
++#define DAT_UART_RX_TIMEOUT_SD_HI 28
++#define DAT_UART_RX_TIMEOUT_SD_SZ 1
++#define DAT_UART_MULTI_IRQ_SD_MSK 0x20000000
++#define DAT_UART_MULTI_IRQ_SD_I_MSK 0xdfffffff
++#define DAT_UART_MULTI_IRQ_SD_SFT 29
++#define DAT_UART_MULTI_IRQ_SD_HI 29
++#define DAT_UART_MULTI_IRQ_SD_SZ 1
++#define ALR_ABT_NOCHG_INT_IRQ_SD_MSK 0x40000000
++#define ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK 0xbfffffff
++#define ALR_ABT_NOCHG_INT_IRQ_SD_SFT 30
++#define ALR_ABT_NOCHG_INT_IRQ_SD_HI 30
++#define ALR_ABT_NOCHG_INT_IRQ_SD_SZ 1
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_MSK 0x80000000
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK 0x7fffffff
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_SFT 31
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_HI 31
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_SZ 1
++#define DBG_SPI_MODE_MSK 0xffffffff
++#define DBG_SPI_MODE_I_MSK 0x00000000
++#define DBG_SPI_MODE_SFT 0
++#define DBG_SPI_MODE_HI 31
++#define DBG_SPI_MODE_SZ 32
++#define DBG_RX_QUOTA_MSK 0x0000ffff
++#define DBG_RX_QUOTA_I_MSK 0xffff0000
++#define DBG_RX_QUOTA_SFT 0
++#define DBG_RX_QUOTA_HI 15
++#define DBG_RX_QUOTA_SZ 16
++#define DBG_CONDI_NUM_MSK 0x000000ff
++#define DBG_CONDI_NUM_I_MSK 0xffffff00
++#define DBG_CONDI_NUM_SFT 0
++#define DBG_CONDI_NUM_HI 7
++#define DBG_CONDI_NUM_SZ 8
++#define DBG_HOST_PATH_MSK 0x00000001
++#define DBG_HOST_PATH_I_MSK 0xfffffffe
++#define DBG_HOST_PATH_SFT 0
++#define DBG_HOST_PATH_HI 0
++#define DBG_HOST_PATH_SZ 1
++#define DBG_TX_SEG_MSK 0xffffffff
++#define DBG_TX_SEG_I_MSK 0x00000000
++#define DBG_TX_SEG_SFT 0
++#define DBG_TX_SEG_HI 31
++#define DBG_TX_SEG_SZ 32
++#define DBG_BRST_MODE_MSK 0x00000001
++#define DBG_BRST_MODE_I_MSK 0xfffffffe
++#define DBG_BRST_MODE_SFT 0
++#define DBG_BRST_MODE_HI 0
++#define DBG_BRST_MODE_SZ 1
++#define DBG_CLK_WIDTH_MSK 0x0000ffff
++#define DBG_CLK_WIDTH_I_MSK 0xffff0000
++#define DBG_CLK_WIDTH_SFT 0
++#define DBG_CLK_WIDTH_HI 15
++#define DBG_CLK_WIDTH_SZ 16
++#define DBG_CSN_INTER_MSK 0xffff0000
++#define DBG_CSN_INTER_I_MSK 0x0000ffff
++#define DBG_CSN_INTER_SFT 16
++#define DBG_CSN_INTER_HI 31
++#define DBG_CSN_INTER_SZ 16
++#define DBG_BACK_DLY_MSK 0x0000ffff
++#define DBG_BACK_DLY_I_MSK 0xffff0000
++#define DBG_BACK_DLY_SFT 0
++#define DBG_BACK_DLY_HI 15
++#define DBG_BACK_DLY_SZ 16
++#define DBG_FRONT_DLY_MSK 0xffff0000
++#define DBG_FRONT_DLY_I_MSK 0x0000ffff
++#define DBG_FRONT_DLY_SFT 16
++#define DBG_FRONT_DLY_HI 31
++#define DBG_FRONT_DLY_SZ 16
++#define DBG_RX_FIFO_FAIL_MSK 0x00000002
++#define DBG_RX_FIFO_FAIL_I_MSK 0xfffffffd
++#define DBG_RX_FIFO_FAIL_SFT 1
++#define DBG_RX_FIFO_FAIL_HI 1
++#define DBG_RX_FIFO_FAIL_SZ 1
++#define DBG_RX_HOST_FAIL_MSK 0x00000004
++#define DBG_RX_HOST_FAIL_I_MSK 0xfffffffb
++#define DBG_RX_HOST_FAIL_SFT 2
++#define DBG_RX_HOST_FAIL_HI 2
++#define DBG_RX_HOST_FAIL_SZ 1
++#define DBG_TX_FIFO_FAIL_MSK 0x00000008
++#define DBG_TX_FIFO_FAIL_I_MSK 0xfffffff7
++#define DBG_TX_FIFO_FAIL_SFT 3
++#define DBG_TX_FIFO_FAIL_HI 3
++#define DBG_TX_FIFO_FAIL_SZ 1
++#define DBG_TX_HOST_FAIL_MSK 0x00000010
++#define DBG_TX_HOST_FAIL_I_MSK 0xffffffef
++#define DBG_TX_HOST_FAIL_SFT 4
++#define DBG_TX_HOST_FAIL_HI 4
++#define DBG_TX_HOST_FAIL_SZ 1
++#define DBG_SPI_DOUBLE_ALLOC_MSK 0x00000020
++#define DBG_SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
++#define DBG_SPI_DOUBLE_ALLOC_SFT 5
++#define DBG_SPI_DOUBLE_ALLOC_HI 5
++#define DBG_SPI_DOUBLE_ALLOC_SZ 1
++#define DBG_SPI_TX_NO_ALLOC_MSK 0x00000040
++#define DBG_SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
++#define DBG_SPI_TX_NO_ALLOC_SFT 6
++#define DBG_SPI_TX_NO_ALLOC_HI 6
++#define DBG_SPI_TX_NO_ALLOC_SZ 1
++#define DBG_RDATA_RDY_MSK 0x00000080
++#define DBG_RDATA_RDY_I_MSK 0xffffff7f
++#define DBG_RDATA_RDY_SFT 7
++#define DBG_RDATA_RDY_HI 7
++#define DBG_RDATA_RDY_SZ 1
++#define DBG_SPI_ALLOC_STATUS_MSK 0x00000100
++#define DBG_SPI_ALLOC_STATUS_I_MSK 0xfffffeff
++#define DBG_SPI_ALLOC_STATUS_SFT 8
++#define DBG_SPI_ALLOC_STATUS_HI 8
++#define DBG_SPI_ALLOC_STATUS_SZ 1
++#define DBG_SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
++#define DBG_SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
++#define DBG_SPI_DBG_WR_FIFO_FULL_SFT 9
++#define DBG_SPI_DBG_WR_FIFO_FULL_HI 9
++#define DBG_SPI_DBG_WR_FIFO_FULL_SZ 1
++#define DBG_RX_LEN_MSK 0xffff0000
++#define DBG_RX_LEN_I_MSK 0x0000ffff
++#define DBG_RX_LEN_SFT 16
++#define DBG_RX_LEN_HI 31
++#define DBG_RX_LEN_SZ 16
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT 8
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_HI 8
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ 1
++#define DBG_SPI_TX_ALLOC_SIZE_MSK 0x000000ff
++#define DBG_SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
++#define DBG_SPI_TX_ALLOC_SIZE_SFT 0
++#define DBG_SPI_TX_ALLOC_SIZE_HI 7
++#define DBG_SPI_TX_ALLOC_SIZE_SZ 8
++#define DBG_RD_DAT_CNT_MSK 0x0000ffff
++#define DBG_RD_DAT_CNT_I_MSK 0xffff0000
++#define DBG_RD_DAT_CNT_SFT 0
++#define DBG_RD_DAT_CNT_HI 15
++#define DBG_RD_DAT_CNT_SZ 16
++#define DBG_RD_STS_CNT_MSK 0xffff0000
++#define DBG_RD_STS_CNT_I_MSK 0x0000ffff
++#define DBG_RD_STS_CNT_SFT 16
++#define DBG_RD_STS_CNT_HI 31
++#define DBG_RD_STS_CNT_SZ 16
++#define DBG_JUDGE_CNT_MSK 0x0000ffff
++#define DBG_JUDGE_CNT_I_MSK 0xffff0000
++#define DBG_JUDGE_CNT_SFT 0
++#define DBG_JUDGE_CNT_HI 15
++#define DBG_JUDGE_CNT_SZ 16
++#define DBG_RD_STS_CNT_CLR_MSK 0x00010000
++#define DBG_RD_STS_CNT_CLR_I_MSK 0xfffeffff
++#define DBG_RD_STS_CNT_CLR_SFT 16
++#define DBG_RD_STS_CNT_CLR_HI 16
++#define DBG_RD_STS_CNT_CLR_SZ 1
++#define DBG_RD_DAT_CNT_CLR_MSK 0x00020000
++#define DBG_RD_DAT_CNT_CLR_I_MSK 0xfffdffff
++#define DBG_RD_DAT_CNT_CLR_SFT 17
++#define DBG_RD_DAT_CNT_CLR_HI 17
++#define DBG_RD_DAT_CNT_CLR_SZ 1
++#define DBG_JUDGE_CNT_CLR_MSK 0x00040000
++#define DBG_JUDGE_CNT_CLR_I_MSK 0xfffbffff
++#define DBG_JUDGE_CNT_CLR_SFT 18
++#define DBG_JUDGE_CNT_CLR_HI 18
++#define DBG_JUDGE_CNT_CLR_SZ 1
++#define DBG_TX_DONE_CNT_MSK 0x0000ffff
++#define DBG_TX_DONE_CNT_I_MSK 0xffff0000
++#define DBG_TX_DONE_CNT_SFT 0
++#define DBG_TX_DONE_CNT_HI 15
++#define DBG_TX_DONE_CNT_SZ 16
++#define DBG_TX_DISCARD_CNT_MSK 0xffff0000
++#define DBG_TX_DISCARD_CNT_I_MSK 0x0000ffff
++#define DBG_TX_DISCARD_CNT_SFT 16
++#define DBG_TX_DISCARD_CNT_HI 31
++#define DBG_TX_DISCARD_CNT_SZ 16
++#define DBG_TX_SET_CNT_MSK 0x0000ffff
++#define DBG_TX_SET_CNT_I_MSK 0xffff0000
++#define DBG_TX_SET_CNT_SFT 0
++#define DBG_TX_SET_CNT_HI 15
++#define DBG_TX_SET_CNT_SZ 16
++#define DBG_TX_DISCARD_CNT_CLR_MSK 0x00010000
++#define DBG_TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
++#define DBG_TX_DISCARD_CNT_CLR_SFT 16
++#define DBG_TX_DISCARD_CNT_CLR_HI 16
++#define DBG_TX_DISCARD_CNT_CLR_SZ 1
++#define DBG_TX_DONE_CNT_CLR_MSK 0x00020000
++#define DBG_TX_DONE_CNT_CLR_I_MSK 0xfffdffff
++#define DBG_TX_DONE_CNT_CLR_SFT 17
++#define DBG_TX_DONE_CNT_CLR_HI 17
++#define DBG_TX_DONE_CNT_CLR_SZ 1
++#define DBG_TX_SET_CNT_CLR_MSK 0x00040000
++#define DBG_TX_SET_CNT_CLR_I_MSK 0xfffbffff
++#define DBG_TX_SET_CNT_CLR_SFT 18
++#define DBG_TX_SET_CNT_CLR_HI 18
++#define DBG_TX_SET_CNT_CLR_SZ 1
++#define DBG_DAT_MODE_OFF_MSK 0x00080000
++#define DBG_DAT_MODE_OFF_I_MSK 0xfff7ffff
++#define DBG_DAT_MODE_OFF_SFT 19
++#define DBG_DAT_MODE_OFF_HI 19
++#define DBG_DAT_MODE_OFF_SZ 1
++#define DBG_TX_FIFO_RESIDUE_MSK 0x00700000
++#define DBG_TX_FIFO_RESIDUE_I_MSK 0xff8fffff
++#define DBG_TX_FIFO_RESIDUE_SFT 20
++#define DBG_TX_FIFO_RESIDUE_HI 22
++#define DBG_TX_FIFO_RESIDUE_SZ 3
++#define DBG_RX_FIFO_RESIDUE_MSK 0x07000000
++#define DBG_RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
++#define DBG_RX_FIFO_RESIDUE_SFT 24
++#define DBG_RX_FIFO_RESIDUE_HI 26
++#define DBG_RX_FIFO_RESIDUE_SZ 3
++#define DBG_RX_RDY_MSK 0x00000001
++#define DBG_RX_RDY_I_MSK 0xfffffffe
++#define DBG_RX_RDY_SFT 0
++#define DBG_RX_RDY_HI 0
++#define DBG_RX_RDY_SZ 1
++#define DBG_SDIO_SYS_INT_MSK 0x00000004
++#define DBG_SDIO_SYS_INT_I_MSK 0xfffffffb
++#define DBG_SDIO_SYS_INT_SFT 2
++#define DBG_SDIO_SYS_INT_HI 2
++#define DBG_SDIO_SYS_INT_SZ 1
++#define DBG_EDCA0_LOWTHOLD_INT_MSK 0x00000008
++#define DBG_EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
++#define DBG_EDCA0_LOWTHOLD_INT_SFT 3
++#define DBG_EDCA0_LOWTHOLD_INT_HI 3
++#define DBG_EDCA0_LOWTHOLD_INT_SZ 1
++#define DBG_EDCA1_LOWTHOLD_INT_MSK 0x00000010
++#define DBG_EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
++#define DBG_EDCA1_LOWTHOLD_INT_SFT 4
++#define DBG_EDCA1_LOWTHOLD_INT_HI 4
++#define DBG_EDCA1_LOWTHOLD_INT_SZ 1
++#define DBG_EDCA2_LOWTHOLD_INT_MSK 0x00000020
++#define DBG_EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
++#define DBG_EDCA2_LOWTHOLD_INT_SFT 5
++#define DBG_EDCA2_LOWTHOLD_INT_HI 5
++#define DBG_EDCA2_LOWTHOLD_INT_SZ 1
++#define DBG_EDCA3_LOWTHOLD_INT_MSK 0x00000040
++#define DBG_EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
++#define DBG_EDCA3_LOWTHOLD_INT_SFT 6
++#define DBG_EDCA3_LOWTHOLD_INT_HI 6
++#define DBG_EDCA3_LOWTHOLD_INT_SZ 1
++#define DBG_TX_LIMIT_INT_IN_MSK 0x00000080
++#define DBG_TX_LIMIT_INT_IN_I_MSK 0xffffff7f
++#define DBG_TX_LIMIT_INT_IN_SFT 7
++#define DBG_TX_LIMIT_INT_IN_HI 7
++#define DBG_TX_LIMIT_INT_IN_SZ 1
++#define DBG_SPI_FN1_MSK 0x00007f00
++#define DBG_SPI_FN1_I_MSK 0xffff80ff
++#define DBG_SPI_FN1_SFT 8
++#define DBG_SPI_FN1_HI 14
++#define DBG_SPI_FN1_SZ 7
++#define DBG_SPI_CLK_EN_INT_MSK 0x00008000
++#define DBG_SPI_CLK_EN_INT_I_MSK 0xffff7fff
++#define DBG_SPI_CLK_EN_INT_SFT 15
++#define DBG_SPI_CLK_EN_INT_HI 15
++#define DBG_SPI_CLK_EN_INT_SZ 1
++#define DBG_SPI_HOST_MASK_MSK 0x00ff0000
++#define DBG_SPI_HOST_MASK_I_MSK 0xff00ffff
++#define DBG_SPI_HOST_MASK_SFT 16
++#define DBG_SPI_HOST_MASK_HI 23
++#define DBG_SPI_HOST_MASK_SZ 8
++#define BOOT_ADDR_MSK 0x00ffffff
++#define BOOT_ADDR_I_MSK 0xff000000
++#define BOOT_ADDR_SFT 0
++#define BOOT_ADDR_HI 23
++#define BOOT_ADDR_SZ 24
++#define CHECK_SUM_FAIL_MSK 0x80000000
++#define CHECK_SUM_FAIL_I_MSK 0x7fffffff
++#define CHECK_SUM_FAIL_SFT 31
++#define CHECK_SUM_FAIL_HI 31
++#define CHECK_SUM_FAIL_SZ 1
++#define VERIFY_DATA_MSK 0xffffffff
++#define VERIFY_DATA_I_MSK 0x00000000
++#define VERIFY_DATA_SFT 0
++#define VERIFY_DATA_HI 31
++#define VERIFY_DATA_SZ 32
++#define FLASH_ADDR_MSK 0x00ffffff
++#define FLASH_ADDR_I_MSK 0xff000000
++#define FLASH_ADDR_SFT 0
++#define FLASH_ADDR_HI 23
++#define FLASH_ADDR_SZ 24
++#define FLASH_CMD_CLR_MSK 0x10000000
++#define FLASH_CMD_CLR_I_MSK 0xefffffff
++#define FLASH_CMD_CLR_SFT 28
++#define FLASH_CMD_CLR_HI 28
++#define FLASH_CMD_CLR_SZ 1
++#define FLASH_DMA_CLR_MSK 0x20000000
++#define FLASH_DMA_CLR_I_MSK 0xdfffffff
++#define FLASH_DMA_CLR_SFT 29
++#define FLASH_DMA_CLR_HI 29
++#define FLASH_DMA_CLR_SZ 1
++#define DMA_EN_MSK 0x40000000
++#define DMA_EN_I_MSK 0xbfffffff
++#define DMA_EN_SFT 30
++#define DMA_EN_HI 30
++#define DMA_EN_SZ 1
++#define DMA_BUSY_MSK 0x80000000
++#define DMA_BUSY_I_MSK 0x7fffffff
++#define DMA_BUSY_SFT 31
++#define DMA_BUSY_HI 31
++#define DMA_BUSY_SZ 1
++#define SRAM_ADDR_MSK 0xffffffff
++#define SRAM_ADDR_I_MSK 0x00000000
++#define SRAM_ADDR_SFT 0
++#define SRAM_ADDR_HI 31
++#define SRAM_ADDR_SZ 32
++#define FLASH_DMA_LEN_MSK 0xffffffff
++#define FLASH_DMA_LEN_I_MSK 0x00000000
++#define FLASH_DMA_LEN_SFT 0
++#define FLASH_DMA_LEN_HI 31
++#define FLASH_DMA_LEN_SZ 32
++#define FLASH_FRONT_DLY_MSK 0x0000ffff
++#define FLASH_FRONT_DLY_I_MSK 0xffff0000
++#define FLASH_FRONT_DLY_SFT 0
++#define FLASH_FRONT_DLY_HI 15
++#define FLASH_FRONT_DLY_SZ 16
++#define FLASH_BACK_DLY_MSK 0xffff0000
++#define FLASH_BACK_DLY_I_MSK 0x0000ffff
++#define FLASH_BACK_DLY_SFT 16
++#define FLASH_BACK_DLY_HI 31
++#define FLASH_BACK_DLY_SZ 16
++#define FLASH_CLK_WIDTH_MSK 0x0000ffff
++#define FLASH_CLK_WIDTH_I_MSK 0xffff0000
++#define FLASH_CLK_WIDTH_SFT 0
++#define FLASH_CLK_WIDTH_HI 15
++#define FLASH_CLK_WIDTH_SZ 16
++#define SPI_BUSY_MSK 0x00010000
++#define SPI_BUSY_I_MSK 0xfffeffff
++#define SPI_BUSY_SFT 16
++#define SPI_BUSY_HI 16
++#define SPI_BUSY_SZ 1
++#define FLS_REMAP_MSK 0x00020000
++#define FLS_REMAP_I_MSK 0xfffdffff
++#define FLS_REMAP_SFT 17
++#define FLS_REMAP_HI 17
++#define FLS_REMAP_SZ 1
++#define PBUS_SWP_MSK 0x00040000
++#define PBUS_SWP_I_MSK 0xfffbffff
++#define PBUS_SWP_SFT 18
++#define PBUS_SWP_HI 18
++#define PBUS_SWP_SZ 1
++#define BIT_MODE1_MSK 0x00080000
++#define BIT_MODE1_I_MSK 0xfff7ffff
++#define BIT_MODE1_SFT 19
++#define BIT_MODE1_HI 19
++#define BIT_MODE1_SZ 1
++#define BIT_MODE2_MSK 0x00100000
++#define BIT_MODE2_I_MSK 0xffefffff
++#define BIT_MODE2_SFT 20
++#define BIT_MODE2_HI 20
++#define BIT_MODE2_SZ 1
++#define BIT_MODE4_MSK 0x00200000
++#define BIT_MODE4_I_MSK 0xffdfffff
++#define BIT_MODE4_SFT 21
++#define BIT_MODE4_HI 21
++#define BIT_MODE4_SZ 1
++#define BOOT_CHECK_SUM_MSK 0xffffffff
++#define BOOT_CHECK_SUM_I_MSK 0x00000000
++#define BOOT_CHECK_SUM_SFT 0
++#define BOOT_CHECK_SUM_HI 31
++#define BOOT_CHECK_SUM_SZ 32
++#define CHECK_SUM_TAG_MSK 0xffffffff
++#define CHECK_SUM_TAG_I_MSK 0x00000000
++#define CHECK_SUM_TAG_SFT 0
++#define CHECK_SUM_TAG_HI 31
++#define CHECK_SUM_TAG_SZ 32
++#define CMD_LEN_MSK 0x0000ffff
++#define CMD_LEN_I_MSK 0xffff0000
++#define CMD_LEN_SFT 0
++#define CMD_LEN_HI 15
++#define CMD_LEN_SZ 16
++#define CMD_ADDR_MSK 0xffffffff
++#define CMD_ADDR_I_MSK 0x00000000
++#define CMD_ADDR_SFT 0
++#define CMD_ADDR_HI 31
++#define CMD_ADDR_SZ 32
++#define DMA_ADR_SRC_MSK 0xffffffff
++#define DMA_ADR_SRC_I_MSK 0x00000000
++#define DMA_ADR_SRC_SFT 0
++#define DMA_ADR_SRC_HI 31
++#define DMA_ADR_SRC_SZ 32
++#define DMA_ADR_DST_MSK 0xffffffff
++#define DMA_ADR_DST_I_MSK 0x00000000
++#define DMA_ADR_DST_SFT 0
++#define DMA_ADR_DST_HI 31
++#define DMA_ADR_DST_SZ 32
++#define DMA_SRC_SIZE_MSK 0x00000007
++#define DMA_SRC_SIZE_I_MSK 0xfffffff8
++#define DMA_SRC_SIZE_SFT 0
++#define DMA_SRC_SIZE_HI 2
++#define DMA_SRC_SIZE_SZ 3
++#define DMA_SRC_INC_MSK 0x00000008
++#define DMA_SRC_INC_I_MSK 0xfffffff7
++#define DMA_SRC_INC_SFT 3
++#define DMA_SRC_INC_HI 3
++#define DMA_SRC_INC_SZ 1
++#define DMA_DST_SIZE_MSK 0x00000070
++#define DMA_DST_SIZE_I_MSK 0xffffff8f
++#define DMA_DST_SIZE_SFT 4
++#define DMA_DST_SIZE_HI 6
++#define DMA_DST_SIZE_SZ 3
++#define DMA_DST_INC_MSK 0x00000080
++#define DMA_DST_INC_I_MSK 0xffffff7f
++#define DMA_DST_INC_SFT 7
++#define DMA_DST_INC_HI 7
++#define DMA_DST_INC_SZ 1
++#define DMA_FAST_FILL_MSK 0x00000100
++#define DMA_FAST_FILL_I_MSK 0xfffffeff
++#define DMA_FAST_FILL_SFT 8
++#define DMA_FAST_FILL_HI 8
++#define DMA_FAST_FILL_SZ 1
++#define DMA_SDIO_KICK_MSK 0x00001000
++#define DMA_SDIO_KICK_I_MSK 0xffffefff
++#define DMA_SDIO_KICK_SFT 12
++#define DMA_SDIO_KICK_HI 12
++#define DMA_SDIO_KICK_SZ 1
++#define DMA_BADR_EN_MSK 0x00002000
++#define DMA_BADR_EN_I_MSK 0xffffdfff
++#define DMA_BADR_EN_SFT 13
++#define DMA_BADR_EN_HI 13
++#define DMA_BADR_EN_SZ 1
++#define DMA_LEN_MSK 0xffff0000
++#define DMA_LEN_I_MSK 0x0000ffff
++#define DMA_LEN_SFT 16
++#define DMA_LEN_HI 31
++#define DMA_LEN_SZ 16
++#define DMA_INT_MASK_MSK 0x00000001
++#define DMA_INT_MASK_I_MSK 0xfffffffe
++#define DMA_INT_MASK_SFT 0
++#define DMA_INT_MASK_HI 0
++#define DMA_INT_MASK_SZ 1
++#define DMA_STS_MSK 0x00000100
++#define DMA_STS_I_MSK 0xfffffeff
++#define DMA_STS_SFT 8
++#define DMA_STS_HI 8
++#define DMA_STS_SZ 1
++#define DMA_FINISH_MSK 0x80000000
++#define DMA_FINISH_I_MSK 0x7fffffff
++#define DMA_FINISH_SFT 31
++#define DMA_FINISH_HI 31
++#define DMA_FINISH_SZ 1
++#define DMA_CONST_MSK 0xffffffff
++#define DMA_CONST_I_MSK 0x00000000
++#define DMA_CONST_SFT 0
++#define DMA_CONST_HI 31
++#define DMA_CONST_SZ 32
++#define SLEEP_WAKE_CNT_MSK 0x00ffffff
++#define SLEEP_WAKE_CNT_I_MSK 0xff000000
++#define SLEEP_WAKE_CNT_SFT 0
++#define SLEEP_WAKE_CNT_HI 23
++#define SLEEP_WAKE_CNT_SZ 24
++#define RG_DLDO_LEVEL_MSK 0x07000000
++#define RG_DLDO_LEVEL_I_MSK 0xf8ffffff
++#define RG_DLDO_LEVEL_SFT 24
++#define RG_DLDO_LEVEL_HI 26
++#define RG_DLDO_LEVEL_SZ 3
++#define RG_DLDO_BOOST_IQ_MSK 0x08000000
++#define RG_DLDO_BOOST_IQ_I_MSK 0xf7ffffff
++#define RG_DLDO_BOOST_IQ_SFT 27
++#define RG_DLDO_BOOST_IQ_HI 27
++#define RG_DLDO_BOOST_IQ_SZ 1
++#define RG_BUCK_LEVEL_MSK 0x70000000
++#define RG_BUCK_LEVEL_I_MSK 0x8fffffff
++#define RG_BUCK_LEVEL_SFT 28
++#define RG_BUCK_LEVEL_HI 30
++#define RG_BUCK_LEVEL_SZ 3
++#define RG_BUCK_VREF_SEL_MSK 0x80000000
++#define RG_BUCK_VREF_SEL_I_MSK 0x7fffffff
++#define RG_BUCK_VREF_SEL_SFT 31
++#define RG_BUCK_VREF_SEL_HI 31
++#define RG_BUCK_VREF_SEL_SZ 1
++#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x000003ff
++#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xfffffc00
++#define RG_RTC_OSC_RES_SW_MANUAL_SFT 0
++#define RG_RTC_OSC_RES_SW_MANUAL_HI 9
++#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10
++#define RG_RTC_OSC_RES_SW_MSK 0x03ff0000
++#define RG_RTC_OSC_RES_SW_I_MSK 0xfc00ffff
++#define RG_RTC_OSC_RES_SW_SFT 16
++#define RG_RTC_OSC_RES_SW_HI 25
++#define RG_RTC_OSC_RES_SW_SZ 10
++#define RTC_OSC_CAL_RES_RDY_MSK 0x80000000
++#define RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff
++#define RTC_OSC_CAL_RES_RDY_SFT 31
++#define RTC_OSC_CAL_RES_RDY_HI 31
++#define RTC_OSC_CAL_RES_RDY_SZ 1
++#define RG_DCDC_MODE_MSK 0x00000001
++#define RG_DCDC_MODE_I_MSK 0xfffffffe
++#define RG_DCDC_MODE_SFT 0
++#define RG_DCDC_MODE_HI 0
++#define RG_DCDC_MODE_SZ 1
++#define RG_BUCK_EN_PSM_MSK 0x00000010
++#define RG_BUCK_EN_PSM_I_MSK 0xffffffef
++#define RG_BUCK_EN_PSM_SFT 4
++#define RG_BUCK_EN_PSM_HI 4
++#define RG_BUCK_EN_PSM_SZ 1
++#define RG_BUCK_PSM_VTH_MSK 0x00000100
++#define RG_BUCK_PSM_VTH_I_MSK 0xfffffeff
++#define RG_BUCK_PSM_VTH_SFT 8
++#define RG_BUCK_PSM_VTH_HI 8
++#define RG_BUCK_PSM_VTH_SZ 1
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00001000
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xffffefff
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 12
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 12
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
++#define RG_RTC_RDY_DEGLITCH_TIMER_MSK 0x00006000
++#define RG_RTC_RDY_DEGLITCH_TIMER_I_MSK 0xffff9fff
++#define RG_RTC_RDY_DEGLITCH_TIMER_SFT 13
++#define RG_RTC_RDY_DEGLITCH_TIMER_HI 14
++#define RG_RTC_RDY_DEGLITCH_TIMER_SZ 2
++#define RTC_CAL_ENA_MSK 0x00010000
++#define RTC_CAL_ENA_I_MSK 0xfffeffff
++#define RTC_CAL_ENA_SFT 16
++#define RTC_CAL_ENA_HI 16
++#define RTC_CAL_ENA_SZ 1
++#define PMU_WAKE_TRIG_EVENT_MSK 0x00000003
++#define PMU_WAKE_TRIG_EVENT_I_MSK 0xfffffffc
++#define PMU_WAKE_TRIG_EVENT_SFT 0
++#define PMU_WAKE_TRIG_EVENT_HI 1
++#define PMU_WAKE_TRIG_EVENT_SZ 2
++#define DIGI_TOP_POR_MASK_MSK 0x00000010
++#define DIGI_TOP_POR_MASK_I_MSK 0xffffffef
++#define DIGI_TOP_POR_MASK_SFT 4
++#define DIGI_TOP_POR_MASK_HI 4
++#define DIGI_TOP_POR_MASK_SZ 1
++#define PMU_ENTER_SLEEP_MODE_MSK 0x00000100
++#define PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffeff
++#define PMU_ENTER_SLEEP_MODE_SFT 8
++#define PMU_ENTER_SLEEP_MODE_HI 8
++#define PMU_ENTER_SLEEP_MODE_SZ 1
++#define RG_RTC_DUMMIES_MSK 0xffff0000
++#define RG_RTC_DUMMIES_I_MSK 0x0000ffff
++#define RG_RTC_DUMMIES_SFT 16
++#define RG_RTC_DUMMIES_HI 31
++#define RG_RTC_DUMMIES_SZ 16
++#define RTC_EN_MSK 0x00000001
++#define RTC_EN_I_MSK 0xfffffffe
++#define RTC_EN_SFT 0
++#define RTC_EN_HI 0
++#define RTC_EN_SZ 1
++#define RTC_SRC_MSK 0x00000002
++#define RTC_SRC_I_MSK 0xfffffffd
++#define RTC_SRC_SFT 1
++#define RTC_SRC_HI 1
++#define RTC_SRC_SZ 1
++#define RTC_TICK_CNT_MSK 0x7fff0000
++#define RTC_TICK_CNT_I_MSK 0x8000ffff
++#define RTC_TICK_CNT_SFT 16
++#define RTC_TICK_CNT_HI 30
++#define RTC_TICK_CNT_SZ 15
++#define RTC_INT_SEC_MASK_MSK 0x00000001
++#define RTC_INT_SEC_MASK_I_MSK 0xfffffffe
++#define RTC_INT_SEC_MASK_SFT 0
++#define RTC_INT_SEC_MASK_HI 0
++#define RTC_INT_SEC_MASK_SZ 1
++#define RTC_INT_ALARM_MASK_MSK 0x00000002
++#define RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
++#define RTC_INT_ALARM_MASK_SFT 1
++#define RTC_INT_ALARM_MASK_HI 1
++#define RTC_INT_ALARM_MASK_SZ 1
++#define RTC_INT_SEC_MSK 0x00010000
++#define RTC_INT_SEC_I_MSK 0xfffeffff
++#define RTC_INT_SEC_SFT 16
++#define RTC_INT_SEC_HI 16
++#define RTC_INT_SEC_SZ 1
++#define RTC_INT_ALARM_MSK 0x00020000
++#define RTC_INT_ALARM_I_MSK 0xfffdffff
++#define RTC_INT_ALARM_SFT 17
++#define RTC_INT_ALARM_HI 17
++#define RTC_INT_ALARM_SZ 1
++#define RTC_SEC_START_CNT_MSK 0xffffffff
++#define RTC_SEC_START_CNT_I_MSK 0x00000000
++#define RTC_SEC_START_CNT_SFT 0
++#define RTC_SEC_START_CNT_HI 31
++#define RTC_SEC_START_CNT_SZ 32
++#define RTC_SEC_CNT_MSK 0xffffffff
++#define RTC_SEC_CNT_I_MSK 0x00000000
++#define RTC_SEC_CNT_SFT 0
++#define RTC_SEC_CNT_HI 31
++#define RTC_SEC_CNT_SZ 32
++#define RTC_SEC_ALARM_VALUE_MSK 0xffffffff
++#define RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
++#define RTC_SEC_ALARM_VALUE_SFT 0
++#define RTC_SEC_ALARM_VALUE_HI 31
++#define RTC_SEC_ALARM_VALUE_SZ 32
++#define D2_DMA_ADR_SRC_MSK 0xffffffff
++#define D2_DMA_ADR_SRC_I_MSK 0x00000000
++#define D2_DMA_ADR_SRC_SFT 0
++#define D2_DMA_ADR_SRC_HI 31
++#define D2_DMA_ADR_SRC_SZ 32
++#define D2_DMA_ADR_DST_MSK 0xffffffff
++#define D2_DMA_ADR_DST_I_MSK 0x00000000
++#define D2_DMA_ADR_DST_SFT 0
++#define D2_DMA_ADR_DST_HI 31
++#define D2_DMA_ADR_DST_SZ 32
++#define D2_DMA_SRC_SIZE_MSK 0x00000007
++#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8
++#define D2_DMA_SRC_SIZE_SFT 0
++#define D2_DMA_SRC_SIZE_HI 2
++#define D2_DMA_SRC_SIZE_SZ 3
++#define D2_DMA_SRC_INC_MSK 0x00000008
++#define D2_DMA_SRC_INC_I_MSK 0xfffffff7
++#define D2_DMA_SRC_INC_SFT 3
++#define D2_DMA_SRC_INC_HI 3
++#define D2_DMA_SRC_INC_SZ 1
++#define D2_DMA_DST_SIZE_MSK 0x00000070
++#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f
++#define D2_DMA_DST_SIZE_SFT 4
++#define D2_DMA_DST_SIZE_HI 6
++#define D2_DMA_DST_SIZE_SZ 3
++#define D2_DMA_DST_INC_MSK 0x00000080
++#define D2_DMA_DST_INC_I_MSK 0xffffff7f
++#define D2_DMA_DST_INC_SFT 7
++#define D2_DMA_DST_INC_HI 7
++#define D2_DMA_DST_INC_SZ 1
++#define D2_DMA_FAST_FILL_MSK 0x00000100
++#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff
++#define D2_DMA_FAST_FILL_SFT 8
++#define D2_DMA_FAST_FILL_HI 8
++#define D2_DMA_FAST_FILL_SZ 1
++#define D2_DMA_SDIO_KICK_MSK 0x00001000
++#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff
++#define D2_DMA_SDIO_KICK_SFT 12
++#define D2_DMA_SDIO_KICK_HI 12
++#define D2_DMA_SDIO_KICK_SZ 1
++#define D2_DMA_BADR_EN_MSK 0x00002000
++#define D2_DMA_BADR_EN_I_MSK 0xffffdfff
++#define D2_DMA_BADR_EN_SFT 13
++#define D2_DMA_BADR_EN_HI 13
++#define D2_DMA_BADR_EN_SZ 1
++#define D2_DMA_LEN_MSK 0xffff0000
++#define D2_DMA_LEN_I_MSK 0x0000ffff
++#define D2_DMA_LEN_SFT 16
++#define D2_DMA_LEN_HI 31
++#define D2_DMA_LEN_SZ 16
++#define D2_DMA_INT_MASK_MSK 0x00000001
++#define D2_DMA_INT_MASK_I_MSK 0xfffffffe
++#define D2_DMA_INT_MASK_SFT 0
++#define D2_DMA_INT_MASK_HI 0
++#define D2_DMA_INT_MASK_SZ 1
++#define D2_DMA_STS_MSK 0x00000100
++#define D2_DMA_STS_I_MSK 0xfffffeff
++#define D2_DMA_STS_SFT 8
++#define D2_DMA_STS_HI 8
++#define D2_DMA_STS_SZ 1
++#define D2_DMA_FINISH_MSK 0x80000000
++#define D2_DMA_FINISH_I_MSK 0x7fffffff
++#define D2_DMA_FINISH_SFT 31
++#define D2_DMA_FINISH_HI 31
++#define D2_DMA_FINISH_SZ 1
++#define D2_DMA_CONST_MSK 0xffffffff
++#define D2_DMA_CONST_I_MSK 0x00000000
++#define D2_DMA_CONST_SFT 0
++#define D2_DMA_CONST_HI 31
++#define D2_DMA_CONST_SZ 32
++#define TRAP_UNKNOWN_TYPE_MSK 0x00000001
++#define TRAP_UNKNOWN_TYPE_I_MSK 0xfffffffe
++#define TRAP_UNKNOWN_TYPE_SFT 0
++#define TRAP_UNKNOWN_TYPE_HI 0
++#define TRAP_UNKNOWN_TYPE_SZ 1
++#define TX_ON_DEMAND_ENA_MSK 0x00000002
++#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd
++#define TX_ON_DEMAND_ENA_SFT 1
++#define TX_ON_DEMAND_ENA_HI 1
++#define TX_ON_DEMAND_ENA_SZ 1
++#define RX_2_HOST_MSK 0x00000004
++#define RX_2_HOST_I_MSK 0xfffffffb
++#define RX_2_HOST_SFT 2
++#define RX_2_HOST_HI 2
++#define RX_2_HOST_SZ 1
++#define AUTO_SEQNO_MSK 0x00000008
++#define AUTO_SEQNO_I_MSK 0xfffffff7
++#define AUTO_SEQNO_SFT 3
++#define AUTO_SEQNO_HI 3
++#define AUTO_SEQNO_SZ 1
++#define BYPASSS_TX_PARSER_ENCAP_MSK 0x00000010
++#define BYPASSS_TX_PARSER_ENCAP_I_MSK 0xffffffef
++#define BYPASSS_TX_PARSER_ENCAP_SFT 4
++#define BYPASSS_TX_PARSER_ENCAP_HI 4
++#define BYPASSS_TX_PARSER_ENCAP_SZ 1
++#define HDR_STRIP_MSK 0x00000020
++#define HDR_STRIP_I_MSK 0xffffffdf
++#define HDR_STRIP_SFT 5
++#define HDR_STRIP_HI 5
++#define HDR_STRIP_SZ 1
++#define ERP_PROTECT_MSK 0x000000c0
++#define ERP_PROTECT_I_MSK 0xffffff3f
++#define ERP_PROTECT_SFT 6
++#define ERP_PROTECT_HI 7
++#define ERP_PROTECT_SZ 2
++#define PRO_VER_MSK 0x00000300
++#define PRO_VER_I_MSK 0xfffffcff
++#define PRO_VER_SFT 8
++#define PRO_VER_HI 9
++#define PRO_VER_SZ 2
++#define TXQ_ID0_MSK 0x00007000
++#define TXQ_ID0_I_MSK 0xffff8fff
++#define TXQ_ID0_SFT 12
++#define TXQ_ID0_HI 14
++#define TXQ_ID0_SZ 3
++#define TXQ_ID1_MSK 0x00070000
++#define TXQ_ID1_I_MSK 0xfff8ffff
++#define TXQ_ID1_SFT 16
++#define TXQ_ID1_HI 18
++#define TXQ_ID1_SZ 3
++#define TX_ETHER_TRAP_EN_MSK 0x00100000
++#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff
++#define TX_ETHER_TRAP_EN_SFT 20
++#define TX_ETHER_TRAP_EN_HI 20
++#define TX_ETHER_TRAP_EN_SZ 1
++#define RX_ETHER_TRAP_EN_MSK 0x00200000
++#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff
++#define RX_ETHER_TRAP_EN_SFT 21
++#define RX_ETHER_TRAP_EN_HI 21
++#define RX_ETHER_TRAP_EN_SZ 1
++#define RX_NULL_TRAP_EN_MSK 0x00400000
++#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff
++#define RX_NULL_TRAP_EN_SFT 22
++#define RX_NULL_TRAP_EN_HI 22
++#define RX_NULL_TRAP_EN_SZ 1
++#define RX_GET_TX_QUEUE_EN_MSK 0x02000000
++#define RX_GET_TX_QUEUE_EN_I_MSK 0xfdffffff
++#define RX_GET_TX_QUEUE_EN_SFT 25
++#define RX_GET_TX_QUEUE_EN_HI 25
++#define RX_GET_TX_QUEUE_EN_SZ 1
++#define HCI_INQ_SEL_MSK 0x04000000
++#define HCI_INQ_SEL_I_MSK 0xfbffffff
++#define HCI_INQ_SEL_SFT 26
++#define HCI_INQ_SEL_HI 26
++#define HCI_INQ_SEL_SZ 1
++#define TRX_DEBUG_CNT_ENA_MSK 0x10000000
++#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff
++#define TRX_DEBUG_CNT_ENA_SFT 28
++#define TRX_DEBUG_CNT_ENA_HI 28
++#define TRX_DEBUG_CNT_ENA_SZ 1
++#define WAKE_SOON_WITH_SCK_MSK 0x00000001
++#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe
++#define WAKE_SOON_WITH_SCK_SFT 0
++#define WAKE_SOON_WITH_SCK_HI 0
++#define WAKE_SOON_WITH_SCK_SZ 1
++#define TX_FLOW_CTRL_MSK 0x0000ffff
++#define TX_FLOW_CTRL_I_MSK 0xffff0000
++#define TX_FLOW_CTRL_SFT 0
++#define TX_FLOW_CTRL_HI 15
++#define TX_FLOW_CTRL_SZ 16
++#define TX_FLOW_MGMT_MSK 0xffff0000
++#define TX_FLOW_MGMT_I_MSK 0x0000ffff
++#define TX_FLOW_MGMT_SFT 16
++#define TX_FLOW_MGMT_HI 31
++#define TX_FLOW_MGMT_SZ 16
++#define TX_FLOW_DATA_MSK 0xffffffff
++#define TX_FLOW_DATA_I_MSK 0x00000000
++#define TX_FLOW_DATA_SFT 0
++#define TX_FLOW_DATA_HI 31
++#define TX_FLOW_DATA_SZ 32
++#define DOT11RTSTHRESHOLD_MSK 0xffff0000
++#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff
++#define DOT11RTSTHRESHOLD_SFT 16
++#define DOT11RTSTHRESHOLD_HI 31
++#define DOT11RTSTHRESHOLD_SZ 16
++#define TXF_ID_MSK 0x0000003f
++#define TXF_ID_I_MSK 0xffffffc0
++#define TXF_ID_SFT 0
++#define TXF_ID_HI 5
++#define TXF_ID_SZ 6
++#define SEQ_CTRL_MSK 0x0000ffff
++#define SEQ_CTRL_I_MSK 0xffff0000
++#define SEQ_CTRL_SFT 0
++#define SEQ_CTRL_HI 15
++#define SEQ_CTRL_SZ 16
++#define TX_PBOFFSET_MSK 0x000000ff
++#define TX_PBOFFSET_I_MSK 0xffffff00
++#define TX_PBOFFSET_SFT 0
++#define TX_PBOFFSET_HI 7
++#define TX_PBOFFSET_SZ 8
++#define TX_INFO_SIZE_MSK 0x0000ff00
++#define TX_INFO_SIZE_I_MSK 0xffff00ff
++#define TX_INFO_SIZE_SFT 8
++#define TX_INFO_SIZE_HI 15
++#define TX_INFO_SIZE_SZ 8
++#define RX_INFO_SIZE_MSK 0x00ff0000
++#define RX_INFO_SIZE_I_MSK 0xff00ffff
++#define RX_INFO_SIZE_SFT 16
++#define RX_INFO_SIZE_HI 23
++#define RX_INFO_SIZE_SZ 8
++#define RX_LAST_PHY_SIZE_MSK 0xff000000
++#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff
++#define RX_LAST_PHY_SIZE_SFT 24
++#define RX_LAST_PHY_SIZE_HI 31
++#define RX_LAST_PHY_SIZE_SZ 8
++#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f
++#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0
++#define TX_INFO_CLEAR_SIZE_SFT 0
++#define TX_INFO_CLEAR_SIZE_HI 5
++#define TX_INFO_CLEAR_SIZE_SZ 6
++#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100
++#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff
++#define TX_INFO_CLEAR_ENABLE_SFT 8
++#define TX_INFO_CLEAR_ENABLE_HI 8
++#define TX_INFO_CLEAR_ENABLE_SZ 1
++#define TXTRAP_ETHTYPE1_MSK 0x0000ffff
++#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000
++#define TXTRAP_ETHTYPE1_SFT 0
++#define TXTRAP_ETHTYPE1_HI 15
++#define TXTRAP_ETHTYPE1_SZ 16
++#define TXTRAP_ETHTYPE0_MSK 0xffff0000
++#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff
++#define TXTRAP_ETHTYPE0_SFT 16
++#define TXTRAP_ETHTYPE0_HI 31
++#define TXTRAP_ETHTYPE0_SZ 16
++#define RXTRAP_ETHTYPE1_MSK 0x0000ffff
++#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000
++#define RXTRAP_ETHTYPE1_SFT 0
++#define RXTRAP_ETHTYPE1_HI 15
++#define RXTRAP_ETHTYPE1_SZ 16
++#define RXTRAP_ETHTYPE0_MSK 0xffff0000
++#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff
++#define RXTRAP_ETHTYPE0_SFT 16
++#define RXTRAP_ETHTYPE0_HI 31
++#define RXTRAP_ETHTYPE0_SZ 16
++#define TX_PKT_COUNTER_MSK 0xffffffff
++#define TX_PKT_COUNTER_I_MSK 0x00000000
++#define TX_PKT_COUNTER_SFT 0
++#define TX_PKT_COUNTER_HI 31
++#define TX_PKT_COUNTER_SZ 32
++#define RX_PKT_COUNTER_MSK 0xffffffff
++#define RX_PKT_COUNTER_I_MSK 0x00000000
++#define RX_PKT_COUNTER_SFT 0
++#define RX_PKT_COUNTER_HI 31
++#define RX_PKT_COUNTER_SZ 32
++#define HOST_CMD_COUNTER_MSK 0x000000ff
++#define HOST_CMD_COUNTER_I_MSK 0xffffff00
++#define HOST_CMD_COUNTER_SFT 0
++#define HOST_CMD_COUNTER_HI 7
++#define HOST_CMD_COUNTER_SZ 8
++#define HOST_EVENT_COUNTER_MSK 0x000000ff
++#define HOST_EVENT_COUNTER_I_MSK 0xffffff00
++#define HOST_EVENT_COUNTER_SFT 0
++#define HOST_EVENT_COUNTER_HI 7
++#define HOST_EVENT_COUNTER_SZ 8
++#define TX_PKT_DROP_COUNTER_MSK 0x000000ff
++#define TX_PKT_DROP_COUNTER_I_MSK 0xffffff00
++#define TX_PKT_DROP_COUNTER_SFT 0
++#define TX_PKT_DROP_COUNTER_HI 7
++#define TX_PKT_DROP_COUNTER_SZ 8
++#define RX_PKT_DROP_COUNTER_MSK 0x000000ff
++#define RX_PKT_DROP_COUNTER_I_MSK 0xffffff00
++#define RX_PKT_DROP_COUNTER_SFT 0
++#define RX_PKT_DROP_COUNTER_HI 7
++#define RX_PKT_DROP_COUNTER_SZ 8
++#define TX_PKT_TRAP_COUNTER_MSK 0x000000ff
++#define TX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
++#define TX_PKT_TRAP_COUNTER_SFT 0
++#define TX_PKT_TRAP_COUNTER_HI 7
++#define TX_PKT_TRAP_COUNTER_SZ 8
++#define RX_PKT_TRAP_COUNTER_MSK 0x000000ff
++#define RX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
++#define RX_PKT_TRAP_COUNTER_SFT 0
++#define RX_PKT_TRAP_COUNTER_HI 7
++#define RX_PKT_TRAP_COUNTER_SZ 8
++#define HOST_TX_FAIL_COUNTER_MSK 0x000000ff
++#define HOST_TX_FAIL_COUNTER_I_MSK 0xffffff00
++#define HOST_TX_FAIL_COUNTER_SFT 0
++#define HOST_TX_FAIL_COUNTER_HI 7
++#define HOST_TX_FAIL_COUNTER_SZ 8
++#define HOST_RX_FAIL_COUNTER_MSK 0x000000ff
++#define HOST_RX_FAIL_COUNTER_I_MSK 0xffffff00
++#define HOST_RX_FAIL_COUNTER_SFT 0
++#define HOST_RX_FAIL_COUNTER_HI 7
++#define HOST_RX_FAIL_COUNTER_SZ 8
++#define HCI_STATE_MONITOR_MSK 0xffffffff
++#define HCI_STATE_MONITOR_I_MSK 0x00000000
++#define HCI_STATE_MONITOR_SFT 0
++#define HCI_STATE_MONITOR_HI 31
++#define HCI_STATE_MONITOR_SZ 32
++#define HCI_ST_TIMEOUT_MONITOR_MSK 0xffffffff
++#define HCI_ST_TIMEOUT_MONITOR_I_MSK 0x00000000
++#define HCI_ST_TIMEOUT_MONITOR_SFT 0
++#define HCI_ST_TIMEOUT_MONITOR_HI 31
++#define HCI_ST_TIMEOUT_MONITOR_SZ 32
++#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff
++#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000
++#define TX_ON_DEMAND_LENGTH_SFT 0
++#define TX_ON_DEMAND_LENGTH_HI 31
++#define TX_ON_DEMAND_LENGTH_SZ 32
++#define HCI_MONITOR_REG1_MSK 0xffffffff
++#define HCI_MONITOR_REG1_I_MSK 0x00000000
++#define HCI_MONITOR_REG1_SFT 0
++#define HCI_MONITOR_REG1_HI 31
++#define HCI_MONITOR_REG1_SZ 32
++#define HCI_MONITOR_REG2_MSK 0xffffffff
++#define HCI_MONITOR_REG2_I_MSK 0x00000000
++#define HCI_MONITOR_REG2_SFT 0
++#define HCI_MONITOR_REG2_HI 31
++#define HCI_MONITOR_REG2_SZ 32
++#define HCI_TX_ALLOC_TIME_31_0_MSK 0xffffffff
++#define HCI_TX_ALLOC_TIME_31_0_I_MSK 0x00000000
++#define HCI_TX_ALLOC_TIME_31_0_SFT 0
++#define HCI_TX_ALLOC_TIME_31_0_HI 31
++#define HCI_TX_ALLOC_TIME_31_0_SZ 32
++#define HCI_TX_ALLOC_TIME_47_32_MSK 0x0000ffff
++#define HCI_TX_ALLOC_TIME_47_32_I_MSK 0xffff0000
++#define HCI_TX_ALLOC_TIME_47_32_SFT 0
++#define HCI_TX_ALLOC_TIME_47_32_HI 15
++#define HCI_TX_ALLOC_TIME_47_32_SZ 16
++#define HCI_MB_MAX_CNT_MSK 0x00ff0000
++#define HCI_MB_MAX_CNT_I_MSK 0xff00ffff
++#define HCI_MB_MAX_CNT_SFT 16
++#define HCI_MB_MAX_CNT_HI 23
++#define HCI_MB_MAX_CNT_SZ 8
++#define HCI_TX_ALLOC_CNT_31_0_MSK 0xffffffff
++#define HCI_TX_ALLOC_CNT_31_0_I_MSK 0x00000000
++#define HCI_TX_ALLOC_CNT_31_0_SFT 0
++#define HCI_TX_ALLOC_CNT_31_0_HI 31
++#define HCI_TX_ALLOC_CNT_31_0_SZ 32
++#define HCI_TX_ALLOC_CNT_47_32_MSK 0x0000ffff
++#define HCI_TX_ALLOC_CNT_47_32_I_MSK 0xffff0000
++#define HCI_TX_ALLOC_CNT_47_32_SFT 0
++#define HCI_TX_ALLOC_CNT_47_32_HI 15
++#define HCI_TX_ALLOC_CNT_47_32_SZ 16
++#define HCI_PROC_CNT_MSK 0x00ff0000
++#define HCI_PROC_CNT_I_MSK 0xff00ffff
++#define HCI_PROC_CNT_SFT 16
++#define HCI_PROC_CNT_HI 23
++#define HCI_PROC_CNT_SZ 8
++#define SDIO_TRANS_CNT_MSK 0xff000000
++#define SDIO_TRANS_CNT_I_MSK 0x00ffffff
++#define SDIO_TRANS_CNT_SFT 24
++#define SDIO_TRANS_CNT_HI 31
++#define SDIO_TRANS_CNT_SZ 8
++#define SDIO_TX_INVALID_CNT_31_0_MSK 0xffffffff
++#define SDIO_TX_INVALID_CNT_31_0_I_MSK 0x00000000
++#define SDIO_TX_INVALID_CNT_31_0_SFT 0
++#define SDIO_TX_INVALID_CNT_31_0_HI 31
++#define SDIO_TX_INVALID_CNT_31_0_SZ 32
++#define SDIO_TX_INVALID_CNT_47_32_MSK 0x0000ffff
++#define SDIO_TX_INVALID_CNT_47_32_I_MSK 0xffff0000
++#define SDIO_TX_INVALID_CNT_47_32_SFT 0
++#define SDIO_TX_INVALID_CNT_47_32_HI 15
++#define SDIO_TX_INVALID_CNT_47_32_SZ 16
++#define CS_START_ADDR_MSK 0x0000ffff
++#define CS_START_ADDR_I_MSK 0xffff0000
++#define CS_START_ADDR_SFT 0
++#define CS_START_ADDR_HI 15
++#define CS_START_ADDR_SZ 16
++#define CS_PKT_ID_MSK 0x007f0000
++#define CS_PKT_ID_I_MSK 0xff80ffff
++#define CS_PKT_ID_SFT 16
++#define CS_PKT_ID_HI 22
++#define CS_PKT_ID_SZ 7
++#define ADD_LEN_MSK 0x0000ffff
++#define ADD_LEN_I_MSK 0xffff0000
++#define ADD_LEN_SFT 0
++#define ADD_LEN_HI 15
++#define ADD_LEN_SZ 16
++#define CS_ADDER_EN_MSK 0x00000001
++#define CS_ADDER_EN_I_MSK 0xfffffffe
++#define CS_ADDER_EN_SFT 0
++#define CS_ADDER_EN_HI 0
++#define CS_ADDER_EN_SZ 1
++#define PSEUDO_MSK 0x00000002
++#define PSEUDO_I_MSK 0xfffffffd
++#define PSEUDO_SFT 1
++#define PSEUDO_HI 1
++#define PSEUDO_SZ 1
++#define CALCULATE_MSK 0xffffffff
++#define CALCULATE_I_MSK 0x00000000
++#define CALCULATE_SFT 0
++#define CALCULATE_HI 31
++#define CALCULATE_SZ 32
++#define L4_LEN_MSK 0x0000ffff
++#define L4_LEN_I_MSK 0xffff0000
++#define L4_LEN_SFT 0
++#define L4_LEN_HI 15
++#define L4_LEN_SZ 16
++#define L4_PROTOL_MSK 0x00ff0000
++#define L4_PROTOL_I_MSK 0xff00ffff
++#define L4_PROTOL_SFT 16
++#define L4_PROTOL_HI 23
++#define L4_PROTOL_SZ 8
++#define CHECK_SUM_MSK 0x0000ffff
++#define CHECK_SUM_I_MSK 0xffff0000
++#define CHECK_SUM_SFT 0
++#define CHECK_SUM_HI 15
++#define CHECK_SUM_SZ 16
++#define RAND_EN_MSK 0x00000001
++#define RAND_EN_I_MSK 0xfffffffe
++#define RAND_EN_SFT 0
++#define RAND_EN_HI 0
++#define RAND_EN_SZ 1
++#define RAND_NUM_MSK 0xffffffff
++#define RAND_NUM_I_MSK 0x00000000
++#define RAND_NUM_SFT 0
++#define RAND_NUM_HI 31
++#define RAND_NUM_SZ 32
++#define MUL_OP1_MSK 0xffffffff
++#define MUL_OP1_I_MSK 0x00000000
++#define MUL_OP1_SFT 0
++#define MUL_OP1_HI 31
++#define MUL_OP1_SZ 32
++#define MUL_OP2_MSK 0xffffffff
++#define MUL_OP2_I_MSK 0x00000000
++#define MUL_OP2_SFT 0
++#define MUL_OP2_HI 31
++#define MUL_OP2_SZ 32
++#define MUL_ANS0_MSK 0xffffffff
++#define MUL_ANS0_I_MSK 0x00000000
++#define MUL_ANS0_SFT 0
++#define MUL_ANS0_HI 31
++#define MUL_ANS0_SZ 32
++#define MUL_ANS1_MSK 0xffffffff
++#define MUL_ANS1_I_MSK 0x00000000
++#define MUL_ANS1_SFT 0
++#define MUL_ANS1_HI 31
++#define MUL_ANS1_SZ 32
++#define RD_ADDR_MSK 0x0000ffff
++#define RD_ADDR_I_MSK 0xffff0000
++#define RD_ADDR_SFT 0
++#define RD_ADDR_HI 15
++#define RD_ADDR_SZ 16
++#define RD_ID_MSK 0x007f0000
++#define RD_ID_I_MSK 0xff80ffff
++#define RD_ID_SFT 16
++#define RD_ID_HI 22
++#define RD_ID_SZ 7
++#define WR_ADDR_MSK 0x0000ffff
++#define WR_ADDR_I_MSK 0xffff0000
++#define WR_ADDR_SFT 0
++#define WR_ADDR_HI 15
++#define WR_ADDR_SZ 16
++#define WR_ID_MSK 0x007f0000
++#define WR_ID_I_MSK 0xff80ffff
++#define WR_ID_SFT 16
++#define WR_ID_HI 22
++#define WR_ID_SZ 7
++#define LEN_MSK 0x0000ffff
++#define LEN_I_MSK 0xffff0000
++#define LEN_SFT 0
++#define LEN_HI 15
++#define LEN_SZ 16
++#define CLR_MSK 0x00000001
++#define CLR_I_MSK 0xfffffffe
++#define CLR_SFT 0
++#define CLR_HI 0
++#define CLR_SZ 1
++#define PHY_MODE_MSK 0x00000003
++#define PHY_MODE_I_MSK 0xfffffffc
++#define PHY_MODE_SFT 0
++#define PHY_MODE_HI 1
++#define PHY_MODE_SZ 2
++#define SHRT_PREAM_MSK 0x00000004
++#define SHRT_PREAM_I_MSK 0xfffffffb
++#define SHRT_PREAM_SFT 2
++#define SHRT_PREAM_HI 2
++#define SHRT_PREAM_SZ 1
++#define SHRT_GI_MSK 0x00000008
++#define SHRT_GI_I_MSK 0xfffffff7
++#define SHRT_GI_SFT 3
++#define SHRT_GI_HI 3
++#define SHRT_GI_SZ 1
++#define DATA_RATE_MSK 0x000007f0
++#define DATA_RATE_I_MSK 0xfffff80f
++#define DATA_RATE_SFT 4
++#define DATA_RATE_HI 10
++#define DATA_RATE_SZ 7
++#define MCS_MSK 0x00007000
++#define MCS_I_MSK 0xffff8fff
++#define MCS_SFT 12
++#define MCS_HI 14
++#define MCS_SZ 3
++#define FRAME_LEN_MSK 0xffff0000
++#define FRAME_LEN_I_MSK 0x0000ffff
++#define FRAME_LEN_SFT 16
++#define FRAME_LEN_HI 31
++#define FRAME_LEN_SZ 16
++#define DURATION_MSK 0x0000ffff
++#define DURATION_I_MSK 0xffff0000
++#define DURATION_SFT 0
++#define DURATION_HI 15
++#define DURATION_SZ 16
++#define SHA_DST_ADDR_MSK 0xffffffff
++#define SHA_DST_ADDR_I_MSK 0x00000000
++#define SHA_DST_ADDR_SFT 0
++#define SHA_DST_ADDR_HI 31
++#define SHA_DST_ADDR_SZ 32
++#define SHA_SRC_ADDR_MSK 0xffffffff
++#define SHA_SRC_ADDR_I_MSK 0x00000000
++#define SHA_SRC_ADDR_SFT 0
++#define SHA_SRC_ADDR_HI 31
++#define SHA_SRC_ADDR_SZ 32
++#define SHA_BUSY_MSK 0x00000001
++#define SHA_BUSY_I_MSK 0xfffffffe
++#define SHA_BUSY_SFT 0
++#define SHA_BUSY_HI 0
++#define SHA_BUSY_SZ 1
++#define SHA_ENDIAN_MSK 0x00000002
++#define SHA_ENDIAN_I_MSK 0xfffffffd
++#define SHA_ENDIAN_SFT 1
++#define SHA_ENDIAN_HI 1
++#define SHA_ENDIAN_SZ 1
++#define EFS_CLKFREQ_MSK 0x00000fff
++#define EFS_CLKFREQ_I_MSK 0xfffff000
++#define EFS_CLKFREQ_SFT 0
++#define EFS_CLKFREQ_HI 11
++#define EFS_CLKFREQ_SZ 12
++#define LOW_ACTIVE_MSK 0x00010000
++#define LOW_ACTIVE_I_MSK 0xfffeffff
++#define LOW_ACTIVE_SFT 16
++#define LOW_ACTIVE_HI 16
++#define LOW_ACTIVE_SZ 1
++#define EFS_CLKFREQ_RD_MSK 0x0ff00000
++#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff
++#define EFS_CLKFREQ_RD_SFT 20
++#define EFS_CLKFREQ_RD_HI 27
++#define EFS_CLKFREQ_RD_SZ 8
++#define EFS_PRE_RD_MSK 0xf0000000
++#define EFS_PRE_RD_I_MSK 0x0fffffff
++#define EFS_PRE_RD_SFT 28
++#define EFS_PRE_RD_HI 31
++#define EFS_PRE_RD_SZ 4
++#define EFS_LDO_ON_MSK 0x0000ffff
++#define EFS_LDO_ON_I_MSK 0xffff0000
++#define EFS_LDO_ON_SFT 0
++#define EFS_LDO_ON_HI 15
++#define EFS_LDO_ON_SZ 16
++#define EFS_LDO_OFF_MSK 0xffff0000
++#define EFS_LDO_OFF_I_MSK 0x0000ffff
++#define EFS_LDO_OFF_SFT 16
++#define EFS_LDO_OFF_HI 31
++#define EFS_LDO_OFF_SZ 16
++#define EFS_RDATA_0_MSK 0xffffffff
++#define EFS_RDATA_0_I_MSK 0x00000000
++#define EFS_RDATA_0_SFT 0
++#define EFS_RDATA_0_HI 31
++#define EFS_RDATA_0_SZ 32
++#define EFS_WDATA_0_MSK 0xffffffff
++#define EFS_WDATA_0_I_MSK 0x00000000
++#define EFS_WDATA_0_SFT 0
++#define EFS_WDATA_0_HI 31
++#define EFS_WDATA_0_SZ 32
++#define EFS_RDATA_1_MSK 0xffffffff
++#define EFS_RDATA_1_I_MSK 0x00000000
++#define EFS_RDATA_1_SFT 0
++#define EFS_RDATA_1_HI 31
++#define EFS_RDATA_1_SZ 32
++#define EFS_WDATA_1_MSK 0xffffffff
++#define EFS_WDATA_1_I_MSK 0x00000000
++#define EFS_WDATA_1_SFT 0
++#define EFS_WDATA_1_HI 31
++#define EFS_WDATA_1_SZ 32
++#define EFS_RDATA_2_MSK 0xffffffff
++#define EFS_RDATA_2_I_MSK 0x00000000
++#define EFS_RDATA_2_SFT 0
++#define EFS_RDATA_2_HI 31
++#define EFS_RDATA_2_SZ 32
++#define EFS_WDATA_2_MSK 0xffffffff
++#define EFS_WDATA_2_I_MSK 0x00000000
++#define EFS_WDATA_2_SFT 0
++#define EFS_WDATA_2_HI 31
++#define EFS_WDATA_2_SZ 32
++#define EFS_RDATA_3_MSK 0xffffffff
++#define EFS_RDATA_3_I_MSK 0x00000000
++#define EFS_RDATA_3_SFT 0
++#define EFS_RDATA_3_HI 31
++#define EFS_RDATA_3_SZ 32
++#define EFS_WDATA_3_MSK 0xffffffff
++#define EFS_WDATA_3_I_MSK 0x00000000
++#define EFS_WDATA_3_SFT 0
++#define EFS_WDATA_3_HI 31
++#define EFS_WDATA_3_SZ 32
++#define EFS_RDATA_4_MSK 0xffffffff
++#define EFS_RDATA_4_I_MSK 0x00000000
++#define EFS_RDATA_4_SFT 0
++#define EFS_RDATA_4_HI 31
++#define EFS_RDATA_4_SZ 32
++#define EFS_WDATA_4_MSK 0xffffffff
++#define EFS_WDATA_4_I_MSK 0x00000000
++#define EFS_WDATA_4_SFT 0
++#define EFS_WDATA_4_HI 31
++#define EFS_WDATA_4_SZ 32
++#define EFS_RDATA_5_MSK 0xffffffff
++#define EFS_RDATA_5_I_MSK 0x00000000
++#define EFS_RDATA_5_SFT 0
++#define EFS_RDATA_5_HI 31
++#define EFS_RDATA_5_SZ 32
++#define EFS_WDATA_5_MSK 0xffffffff
++#define EFS_WDATA_5_I_MSK 0x00000000
++#define EFS_WDATA_5_SFT 0
++#define EFS_WDATA_5_HI 31
++#define EFS_WDATA_5_SZ 32
++#define EFS_RDATA_6_MSK 0xffffffff
++#define EFS_RDATA_6_I_MSK 0x00000000
++#define EFS_RDATA_6_SFT 0
++#define EFS_RDATA_6_HI 31
++#define EFS_RDATA_6_SZ 32
++#define EFS_WDATA_6_MSK 0xffffffff
++#define EFS_WDATA_6_I_MSK 0x00000000
++#define EFS_WDATA_6_SFT 0
++#define EFS_WDATA_6_HI 31
++#define EFS_WDATA_6_SZ 32
++#define EFS_RDATA_7_MSK 0xffffffff
++#define EFS_RDATA_7_I_MSK 0x00000000
++#define EFS_RDATA_7_SFT 0
++#define EFS_RDATA_7_HI 31
++#define EFS_RDATA_7_SZ 32
++#define EFS_WDATA_7_MSK 0xffffffff
++#define EFS_WDATA_7_I_MSK 0x00000000
++#define EFS_WDATA_7_SFT 0
++#define EFS_WDATA_7_HI 31
++#define EFS_WDATA_7_SZ 32
++#define EFS_SPI_RD0_EN_MSK 0x00000001
++#define EFS_SPI_RD0_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD0_EN_SFT 0
++#define EFS_SPI_RD0_EN_HI 0
++#define EFS_SPI_RD0_EN_SZ 1
++#define EFS_SPI_RD1_EN_MSK 0x00000001
++#define EFS_SPI_RD1_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD1_EN_SFT 0
++#define EFS_SPI_RD1_EN_HI 0
++#define EFS_SPI_RD1_EN_SZ 1
++#define EFS_SPI_RD2_EN_MSK 0x00000001
++#define EFS_SPI_RD2_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD2_EN_SFT 0
++#define EFS_SPI_RD2_EN_HI 0
++#define EFS_SPI_RD2_EN_SZ 1
++#define EFS_SPI_RD3_EN_MSK 0x00000001
++#define EFS_SPI_RD3_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD3_EN_SFT 0
++#define EFS_SPI_RD3_EN_HI 0
++#define EFS_SPI_RD3_EN_SZ 1
++#define EFS_SPI_RD4_EN_MSK 0x00000001
++#define EFS_SPI_RD4_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD4_EN_SFT 0
++#define EFS_SPI_RD4_EN_HI 0
++#define EFS_SPI_RD4_EN_SZ 1
++#define EFS_SPI_RD5_EN_MSK 0x00000001
++#define EFS_SPI_RD5_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD5_EN_SFT 0
++#define EFS_SPI_RD5_EN_HI 0
++#define EFS_SPI_RD5_EN_SZ 1
++#define EFS_SPI_RD6_EN_MSK 0x00000001
++#define EFS_SPI_RD6_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD6_EN_SFT 0
++#define EFS_SPI_RD6_EN_HI 0
++#define EFS_SPI_RD6_EN_SZ 1
++#define EFS_SPI_RD7_EN_MSK 0x00000001
++#define EFS_SPI_RD7_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD7_EN_SFT 0
++#define EFS_SPI_RD7_EN_HI 0
++#define EFS_SPI_RD7_EN_SZ 1
++#define EFS_SPI_RBUSY_MSK 0x00000001
++#define EFS_SPI_RBUSY_I_MSK 0xfffffffe
++#define EFS_SPI_RBUSY_SFT 0
++#define EFS_SPI_RBUSY_HI 0
++#define EFS_SPI_RBUSY_SZ 1
++#define EFS_SPI_RDATA_0_MSK 0xffffffff
++#define EFS_SPI_RDATA_0_I_MSK 0x00000000
++#define EFS_SPI_RDATA_0_SFT 0
++#define EFS_SPI_RDATA_0_HI 31
++#define EFS_SPI_RDATA_0_SZ 32
++#define EFS_SPI_RDATA_1_MSK 0xffffffff
++#define EFS_SPI_RDATA_1_I_MSK 0x00000000
++#define EFS_SPI_RDATA_1_SFT 0
++#define EFS_SPI_RDATA_1_HI 31
++#define EFS_SPI_RDATA_1_SZ 32
++#define EFS_SPI_RDATA_2_MSK 0xffffffff
++#define EFS_SPI_RDATA_2_I_MSK 0x00000000
++#define EFS_SPI_RDATA_2_SFT 0
++#define EFS_SPI_RDATA_2_HI 31
++#define EFS_SPI_RDATA_2_SZ 32
++#define EFS_SPI_RDATA_3_MSK 0xffffffff
++#define EFS_SPI_RDATA_3_I_MSK 0x00000000
++#define EFS_SPI_RDATA_3_SFT 0
++#define EFS_SPI_RDATA_3_HI 31
++#define EFS_SPI_RDATA_3_SZ 32
++#define EFS_SPI_RDATA_4_MSK 0xffffffff
++#define EFS_SPI_RDATA_4_I_MSK 0x00000000
++#define EFS_SPI_RDATA_4_SFT 0
++#define EFS_SPI_RDATA_4_HI 31
++#define EFS_SPI_RDATA_4_SZ 32
++#define EFS_SPI_RDATA_5_MSK 0xffffffff
++#define EFS_SPI_RDATA_5_I_MSK 0x00000000
++#define EFS_SPI_RDATA_5_SFT 0
++#define EFS_SPI_RDATA_5_HI 31
++#define EFS_SPI_RDATA_5_SZ 32
++#define EFS_SPI_RDATA_6_MSK 0xffffffff
++#define EFS_SPI_RDATA_6_I_MSK 0x00000000
++#define EFS_SPI_RDATA_6_SFT 0
++#define EFS_SPI_RDATA_6_HI 31
++#define EFS_SPI_RDATA_6_SZ 32
++#define EFS_SPI_RDATA_7_MSK 0xffffffff
++#define EFS_SPI_RDATA_7_I_MSK 0x00000000
++#define EFS_SPI_RDATA_7_SFT 0
++#define EFS_SPI_RDATA_7_HI 31
++#define EFS_SPI_RDATA_7_SZ 32
++#define GET_RK_MSK 0x00000001
++#define GET_RK_I_MSK 0xfffffffe
++#define GET_RK_SFT 0
++#define GET_RK_HI 0
++#define GET_RK_SZ 1
++#define FORCE_GET_RK_MSK 0x00000002
++#define FORCE_GET_RK_I_MSK 0xfffffffd
++#define FORCE_GET_RK_SFT 1
++#define FORCE_GET_RK_HI 1
++#define FORCE_GET_RK_SZ 1
++#define SMS4_DESCRY_EN_MSK 0x00000010
++#define SMS4_DESCRY_EN_I_MSK 0xffffffef
++#define SMS4_DESCRY_EN_SFT 4
++#define SMS4_DESCRY_EN_HI 4
++#define SMS4_DESCRY_EN_SZ 1
++#define DEC_DOUT_MSB_MSK 0x00000001
++#define DEC_DOUT_MSB_I_MSK 0xfffffffe
++#define DEC_DOUT_MSB_SFT 0
++#define DEC_DOUT_MSB_HI 0
++#define DEC_DOUT_MSB_SZ 1
++#define DEC_DIN_MSB_MSK 0x00000002
++#define DEC_DIN_MSB_I_MSK 0xfffffffd
++#define DEC_DIN_MSB_SFT 1
++#define DEC_DIN_MSB_HI 1
++#define DEC_DIN_MSB_SZ 1
++#define ENC_DOUT_MSB_MSK 0x00000004
++#define ENC_DOUT_MSB_I_MSK 0xfffffffb
++#define ENC_DOUT_MSB_SFT 2
++#define ENC_DOUT_MSB_HI 2
++#define ENC_DOUT_MSB_SZ 1
++#define ENC_DIN_MSB_MSK 0x00000008
++#define ENC_DIN_MSB_I_MSK 0xfffffff7
++#define ENC_DIN_MSB_SFT 3
++#define ENC_DIN_MSB_HI 3
++#define ENC_DIN_MSB_SZ 1
++#define KEY_DIN_MSB_MSK 0x00000010
++#define KEY_DIN_MSB_I_MSK 0xffffffef
++#define KEY_DIN_MSB_SFT 4
++#define KEY_DIN_MSB_HI 4
++#define KEY_DIN_MSB_SZ 1
++#define SMS4_CBC_EN_MSK 0x00000001
++#define SMS4_CBC_EN_I_MSK 0xfffffffe
++#define SMS4_CBC_EN_SFT 0
++#define SMS4_CBC_EN_HI 0
++#define SMS4_CBC_EN_SZ 1
++#define SMS4_CFB_EN_MSK 0x00000002
++#define SMS4_CFB_EN_I_MSK 0xfffffffd
++#define SMS4_CFB_EN_SFT 1
++#define SMS4_CFB_EN_HI 1
++#define SMS4_CFB_EN_SZ 1
++#define SMS4_OFB_EN_MSK 0x00000004
++#define SMS4_OFB_EN_I_MSK 0xfffffffb
++#define SMS4_OFB_EN_SFT 2
++#define SMS4_OFB_EN_HI 2
++#define SMS4_OFB_EN_SZ 1
++#define SMS4_START_TRIG_MSK 0x00000001
++#define SMS4_START_TRIG_I_MSK 0xfffffffe
++#define SMS4_START_TRIG_SFT 0
++#define SMS4_START_TRIG_HI 0
++#define SMS4_START_TRIG_SZ 1
++#define SMS4_BUSY_MSK 0x00000001
++#define SMS4_BUSY_I_MSK 0xfffffffe
++#define SMS4_BUSY_SFT 0
++#define SMS4_BUSY_HI 0
++#define SMS4_BUSY_SZ 1
++#define SMS4_DONE_MSK 0x00000001
++#define SMS4_DONE_I_MSK 0xfffffffe
++#define SMS4_DONE_SFT 0
++#define SMS4_DONE_HI 0
++#define SMS4_DONE_SZ 1
++#define SMS4_DATAIN_0_MSK 0xffffffff
++#define SMS4_DATAIN_0_I_MSK 0x00000000
++#define SMS4_DATAIN_0_SFT 0
++#define SMS4_DATAIN_0_HI 31
++#define SMS4_DATAIN_0_SZ 32
++#define SMS4_DATAIN_1_MSK 0xffffffff
++#define SMS4_DATAIN_1_I_MSK 0x00000000
++#define SMS4_DATAIN_1_SFT 0
++#define SMS4_DATAIN_1_HI 31
++#define SMS4_DATAIN_1_SZ 32
++#define SMS4_DATAIN_2_MSK 0xffffffff
++#define SMS4_DATAIN_2_I_MSK 0x00000000
++#define SMS4_DATAIN_2_SFT 0
++#define SMS4_DATAIN_2_HI 31
++#define SMS4_DATAIN_2_SZ 32
++#define SMS4_DATAIN_3_MSK 0xffffffff
++#define SMS4_DATAIN_3_I_MSK 0x00000000
++#define SMS4_DATAIN_3_SFT 0
++#define SMS4_DATAIN_3_HI 31
++#define SMS4_DATAIN_3_SZ 32
++#define SMS4_DATAOUT_0_MSK 0xffffffff
++#define SMS4_DATAOUT_0_I_MSK 0x00000000
++#define SMS4_DATAOUT_0_SFT 0
++#define SMS4_DATAOUT_0_HI 31
++#define SMS4_DATAOUT_0_SZ 32
++#define SMS4_DATAOUT_1_MSK 0xffffffff
++#define SMS4_DATAOUT_1_I_MSK 0x00000000
++#define SMS4_DATAOUT_1_SFT 0
++#define SMS4_DATAOUT_1_HI 31
++#define SMS4_DATAOUT_1_SZ 32
++#define SMS4_DATAOUT_2_MSK 0xffffffff
++#define SMS4_DATAOUT_2_I_MSK 0x00000000
++#define SMS4_DATAOUT_2_SFT 0
++#define SMS4_DATAOUT_2_HI 31
++#define SMS4_DATAOUT_2_SZ 32
++#define SMS4_DATAOUT_3_MSK 0xffffffff
++#define SMS4_DATAOUT_3_I_MSK 0x00000000
++#define SMS4_DATAOUT_3_SFT 0
++#define SMS4_DATAOUT_3_HI 31
++#define SMS4_DATAOUT_3_SZ 32
++#define SMS4_KEY_0_MSK 0xffffffff
++#define SMS4_KEY_0_I_MSK 0x00000000
++#define SMS4_KEY_0_SFT 0
++#define SMS4_KEY_0_HI 31
++#define SMS4_KEY_0_SZ 32
++#define SMS4_KEY_1_MSK 0xffffffff
++#define SMS4_KEY_1_I_MSK 0x00000000
++#define SMS4_KEY_1_SFT 0
++#define SMS4_KEY_1_HI 31
++#define SMS4_KEY_1_SZ 32
++#define SMS4_KEY_2_MSK 0xffffffff
++#define SMS4_KEY_2_I_MSK 0x00000000
++#define SMS4_KEY_2_SFT 0
++#define SMS4_KEY_2_HI 31
++#define SMS4_KEY_2_SZ 32
++#define SMS4_KEY_3_MSK 0xffffffff
++#define SMS4_KEY_3_I_MSK 0x00000000
++#define SMS4_KEY_3_SFT 0
++#define SMS4_KEY_3_HI 31
++#define SMS4_KEY_3_SZ 32
++#define SMS4_MODE_IV0_MSK 0xffffffff
++#define SMS4_MODE_IV0_I_MSK 0x00000000
++#define SMS4_MODE_IV0_SFT 0
++#define SMS4_MODE_IV0_HI 31
++#define SMS4_MODE_IV0_SZ 32
++#define SMS4_MODE_IV1_MSK 0xffffffff
++#define SMS4_MODE_IV1_I_MSK 0x00000000
++#define SMS4_MODE_IV1_SFT 0
++#define SMS4_MODE_IV1_HI 31
++#define SMS4_MODE_IV1_SZ 32
++#define SMS4_MODE_IV2_MSK 0xffffffff
++#define SMS4_MODE_IV2_I_MSK 0x00000000
++#define SMS4_MODE_IV2_SFT 0
++#define SMS4_MODE_IV2_HI 31
++#define SMS4_MODE_IV2_SZ 32
++#define SMS4_MODE_IV3_MSK 0xffffffff
++#define SMS4_MODE_IV3_I_MSK 0x00000000
++#define SMS4_MODE_IV3_SFT 0
++#define SMS4_MODE_IV3_HI 31
++#define SMS4_MODE_IV3_SZ 32
++#define SMS4_OFB_ENC0_MSK 0xffffffff
++#define SMS4_OFB_ENC0_I_MSK 0x00000000
++#define SMS4_OFB_ENC0_SFT 0
++#define SMS4_OFB_ENC0_HI 31
++#define SMS4_OFB_ENC0_SZ 32
++#define SMS4_OFB_ENC1_MSK 0xffffffff
++#define SMS4_OFB_ENC1_I_MSK 0x00000000
++#define SMS4_OFB_ENC1_SFT 0
++#define SMS4_OFB_ENC1_HI 31
++#define SMS4_OFB_ENC1_SZ 32
++#define SMS4_OFB_ENC2_MSK 0xffffffff
++#define SMS4_OFB_ENC2_I_MSK 0x00000000
++#define SMS4_OFB_ENC2_SFT 0
++#define SMS4_OFB_ENC2_HI 31
++#define SMS4_OFB_ENC2_SZ 32
++#define SMS4_OFB_ENC3_MSK 0xffffffff
++#define SMS4_OFB_ENC3_I_MSK 0x00000000
++#define SMS4_OFB_ENC3_SFT 0
++#define SMS4_OFB_ENC3_HI 31
++#define SMS4_OFB_ENC3_SZ 32
++#define MRX_MCAST_TB0_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB0_31_0_SFT 0
++#define MRX_MCAST_TB0_31_0_HI 31
++#define MRX_MCAST_TB0_31_0_SZ 32
++#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB0_47_32_SFT 0
++#define MRX_MCAST_TB0_47_32_HI 15
++#define MRX_MCAST_TB0_47_32_SZ 16
++#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK0_31_0_SFT 0
++#define MRX_MCAST_MASK0_31_0_HI 31
++#define MRX_MCAST_MASK0_31_0_SZ 32
++#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK0_47_32_SFT 0
++#define MRX_MCAST_MASK0_47_32_HI 15
++#define MRX_MCAST_MASK0_47_32_SZ 16
++#define MRX_MCAST_CTRL_0_MSK 0x00000003
++#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_0_SFT 0
++#define MRX_MCAST_CTRL_0_HI 1
++#define MRX_MCAST_CTRL_0_SZ 2
++#define MRX_MCAST_TB1_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB1_31_0_SFT 0
++#define MRX_MCAST_TB1_31_0_HI 31
++#define MRX_MCAST_TB1_31_0_SZ 32
++#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB1_47_32_SFT 0
++#define MRX_MCAST_TB1_47_32_HI 15
++#define MRX_MCAST_TB1_47_32_SZ 16
++#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK1_31_0_SFT 0
++#define MRX_MCAST_MASK1_31_0_HI 31
++#define MRX_MCAST_MASK1_31_0_SZ 32
++#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK1_47_32_SFT 0
++#define MRX_MCAST_MASK1_47_32_HI 15
++#define MRX_MCAST_MASK1_47_32_SZ 16
++#define MRX_MCAST_CTRL_1_MSK 0x00000003
++#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_1_SFT 0
++#define MRX_MCAST_CTRL_1_HI 1
++#define MRX_MCAST_CTRL_1_SZ 2
++#define MRX_MCAST_TB2_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB2_31_0_SFT 0
++#define MRX_MCAST_TB2_31_0_HI 31
++#define MRX_MCAST_TB2_31_0_SZ 32
++#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB2_47_32_SFT 0
++#define MRX_MCAST_TB2_47_32_HI 15
++#define MRX_MCAST_TB2_47_32_SZ 16
++#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK2_31_0_SFT 0
++#define MRX_MCAST_MASK2_31_0_HI 31
++#define MRX_MCAST_MASK2_31_0_SZ 32
++#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK2_47_32_SFT 0
++#define MRX_MCAST_MASK2_47_32_HI 15
++#define MRX_MCAST_MASK2_47_32_SZ 16
++#define MRX_MCAST_CTRL_2_MSK 0x00000003
++#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_2_SFT 0
++#define MRX_MCAST_CTRL_2_HI 1
++#define MRX_MCAST_CTRL_2_SZ 2
++#define MRX_MCAST_TB3_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB3_31_0_SFT 0
++#define MRX_MCAST_TB3_31_0_HI 31
++#define MRX_MCAST_TB3_31_0_SZ 32
++#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB3_47_32_SFT 0
++#define MRX_MCAST_TB3_47_32_HI 15
++#define MRX_MCAST_TB3_47_32_SZ 16
++#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK3_31_0_SFT 0
++#define MRX_MCAST_MASK3_31_0_HI 31
++#define MRX_MCAST_MASK3_31_0_SZ 32
++#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK3_47_32_SFT 0
++#define MRX_MCAST_MASK3_47_32_HI 15
++#define MRX_MCAST_MASK3_47_32_SZ 16
++#define MRX_MCAST_CTRL_3_MSK 0x00000003
++#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_3_SFT 0
++#define MRX_MCAST_CTRL_3_HI 1
++#define MRX_MCAST_CTRL_3_SZ 2
++#define MRX_PHY_INFO_MSK 0xffffffff
++#define MRX_PHY_INFO_I_MSK 0x00000000
++#define MRX_PHY_INFO_SFT 0
++#define MRX_PHY_INFO_HI 31
++#define MRX_PHY_INFO_SZ 32
++#define DBG_BA_TYPE_MSK 0x0000003f
++#define DBG_BA_TYPE_I_MSK 0xffffffc0
++#define DBG_BA_TYPE_SFT 0
++#define DBG_BA_TYPE_HI 5
++#define DBG_BA_TYPE_SZ 6
++#define DBG_BA_SEQ_MSK 0x000fff00
++#define DBG_BA_SEQ_I_MSK 0xfff000ff
++#define DBG_BA_SEQ_SFT 8
++#define DBG_BA_SEQ_HI 19
++#define DBG_BA_SEQ_SZ 12
++#define MRX_FLT_TB0_MSK 0x00007fff
++#define MRX_FLT_TB0_I_MSK 0xffff8000
++#define MRX_FLT_TB0_SFT 0
++#define MRX_FLT_TB0_HI 14
++#define MRX_FLT_TB0_SZ 15
++#define MRX_FLT_TB1_MSK 0x00007fff
++#define MRX_FLT_TB1_I_MSK 0xffff8000
++#define MRX_FLT_TB1_SFT 0
++#define MRX_FLT_TB1_HI 14
++#define MRX_FLT_TB1_SZ 15
++#define MRX_FLT_TB2_MSK 0x00007fff
++#define MRX_FLT_TB2_I_MSK 0xffff8000
++#define MRX_FLT_TB2_SFT 0
++#define MRX_FLT_TB2_HI 14
++#define MRX_FLT_TB2_SZ 15
++#define MRX_FLT_TB3_MSK 0x00007fff
++#define MRX_FLT_TB3_I_MSK 0xffff8000
++#define MRX_FLT_TB3_SFT 0
++#define MRX_FLT_TB3_HI 14
++#define MRX_FLT_TB3_SZ 15
++#define MRX_FLT_TB4_MSK 0x00007fff
++#define MRX_FLT_TB4_I_MSK 0xffff8000
++#define MRX_FLT_TB4_SFT 0
++#define MRX_FLT_TB4_HI 14
++#define MRX_FLT_TB4_SZ 15
++#define MRX_FLT_TB5_MSK 0x00007fff
++#define MRX_FLT_TB5_I_MSK 0xffff8000
++#define MRX_FLT_TB5_SFT 0
++#define MRX_FLT_TB5_HI 14
++#define MRX_FLT_TB5_SZ 15
++#define MRX_FLT_TB6_MSK 0x00007fff
++#define MRX_FLT_TB6_I_MSK 0xffff8000
++#define MRX_FLT_TB6_SFT 0
++#define MRX_FLT_TB6_HI 14
++#define MRX_FLT_TB6_SZ 15
++#define MRX_FLT_TB7_MSK 0x00007fff
++#define MRX_FLT_TB7_I_MSK 0xffff8000
++#define MRX_FLT_TB7_SFT 0
++#define MRX_FLT_TB7_HI 14
++#define MRX_FLT_TB7_SZ 15
++#define MRX_FLT_TB8_MSK 0x00007fff
++#define MRX_FLT_TB8_I_MSK 0xffff8000
++#define MRX_FLT_TB8_SFT 0
++#define MRX_FLT_TB8_HI 14
++#define MRX_FLT_TB8_SZ 15
++#define MRX_FLT_TB9_MSK 0x00007fff
++#define MRX_FLT_TB9_I_MSK 0xffff8000
++#define MRX_FLT_TB9_SFT 0
++#define MRX_FLT_TB9_HI 14
++#define MRX_FLT_TB9_SZ 15
++#define MRX_FLT_TB10_MSK 0x00007fff
++#define MRX_FLT_TB10_I_MSK 0xffff8000
++#define MRX_FLT_TB10_SFT 0
++#define MRX_FLT_TB10_HI 14
++#define MRX_FLT_TB10_SZ 15
++#define MRX_FLT_TB11_MSK 0x00007fff
++#define MRX_FLT_TB11_I_MSK 0xffff8000
++#define MRX_FLT_TB11_SFT 0
++#define MRX_FLT_TB11_HI 14
++#define MRX_FLT_TB11_SZ 15
++#define MRX_FLT_TB12_MSK 0x00007fff
++#define MRX_FLT_TB12_I_MSK 0xffff8000
++#define MRX_FLT_TB12_SFT 0
++#define MRX_FLT_TB12_HI 14
++#define MRX_FLT_TB12_SZ 15
++#define MRX_FLT_TB13_MSK 0x00007fff
++#define MRX_FLT_TB13_I_MSK 0xffff8000
++#define MRX_FLT_TB13_SFT 0
++#define MRX_FLT_TB13_HI 14
++#define MRX_FLT_TB13_SZ 15
++#define MRX_FLT_TB14_MSK 0x00007fff
++#define MRX_FLT_TB14_I_MSK 0xffff8000
++#define MRX_FLT_TB14_SFT 0
++#define MRX_FLT_TB14_HI 14
++#define MRX_FLT_TB14_SZ 15
++#define MRX_FLT_TB15_MSK 0x00007fff
++#define MRX_FLT_TB15_I_MSK 0xffff8000
++#define MRX_FLT_TB15_SFT 0
++#define MRX_FLT_TB15_HI 14
++#define MRX_FLT_TB15_SZ 15
++#define MRX_FLT_EN0_MSK 0x0000ffff
++#define MRX_FLT_EN0_I_MSK 0xffff0000
++#define MRX_FLT_EN0_SFT 0
++#define MRX_FLT_EN0_HI 15
++#define MRX_FLT_EN0_SZ 16
++#define MRX_FLT_EN1_MSK 0x0000ffff
++#define MRX_FLT_EN1_I_MSK 0xffff0000
++#define MRX_FLT_EN1_SFT 0
++#define MRX_FLT_EN1_HI 15
++#define MRX_FLT_EN1_SZ 16
++#define MRX_FLT_EN2_MSK 0x0000ffff
++#define MRX_FLT_EN2_I_MSK 0xffff0000
++#define MRX_FLT_EN2_SFT 0
++#define MRX_FLT_EN2_HI 15
++#define MRX_FLT_EN2_SZ 16
++#define MRX_FLT_EN3_MSK 0x0000ffff
++#define MRX_FLT_EN3_I_MSK 0xffff0000
++#define MRX_FLT_EN3_SFT 0
++#define MRX_FLT_EN3_HI 15
++#define MRX_FLT_EN3_SZ 16
++#define MRX_FLT_EN4_MSK 0x0000ffff
++#define MRX_FLT_EN4_I_MSK 0xffff0000
++#define MRX_FLT_EN4_SFT 0
++#define MRX_FLT_EN4_HI 15
++#define MRX_FLT_EN4_SZ 16
++#define MRX_FLT_EN5_MSK 0x0000ffff
++#define MRX_FLT_EN5_I_MSK 0xffff0000
++#define MRX_FLT_EN5_SFT 0
++#define MRX_FLT_EN5_HI 15
++#define MRX_FLT_EN5_SZ 16
++#define MRX_FLT_EN6_MSK 0x0000ffff
++#define MRX_FLT_EN6_I_MSK 0xffff0000
++#define MRX_FLT_EN6_SFT 0
++#define MRX_FLT_EN6_HI 15
++#define MRX_FLT_EN6_SZ 16
++#define MRX_FLT_EN7_MSK 0x0000ffff
++#define MRX_FLT_EN7_I_MSK 0xffff0000
++#define MRX_FLT_EN7_SFT 0
++#define MRX_FLT_EN7_HI 15
++#define MRX_FLT_EN7_SZ 16
++#define MRX_FLT_EN8_MSK 0x0000ffff
++#define MRX_FLT_EN8_I_MSK 0xffff0000
++#define MRX_FLT_EN8_SFT 0
++#define MRX_FLT_EN8_HI 15
++#define MRX_FLT_EN8_SZ 16
++#define MRX_LEN_FLT_MSK 0x0000ffff
++#define MRX_LEN_FLT_I_MSK 0xffff0000
++#define MRX_LEN_FLT_SFT 0
++#define MRX_LEN_FLT_HI 15
++#define MRX_LEN_FLT_SZ 16
++#define RX_FLOW_DATA_MSK 0xffffffff
++#define RX_FLOW_DATA_I_MSK 0x00000000
++#define RX_FLOW_DATA_SFT 0
++#define RX_FLOW_DATA_HI 31
++#define RX_FLOW_DATA_SZ 32
++#define RX_FLOW_MNG_MSK 0x0000ffff
++#define RX_FLOW_MNG_I_MSK 0xffff0000
++#define RX_FLOW_MNG_SFT 0
++#define RX_FLOW_MNG_HI 15
++#define RX_FLOW_MNG_SZ 16
++#define RX_FLOW_CTRL_MSK 0x0000ffff
++#define RX_FLOW_CTRL_I_MSK 0xffff0000
++#define RX_FLOW_CTRL_SFT 0
++#define RX_FLOW_CTRL_HI 15
++#define RX_FLOW_CTRL_SZ 16
++#define MRX_STP_EN_MSK 0x00000001
++#define MRX_STP_EN_I_MSK 0xfffffffe
++#define MRX_STP_EN_SFT 0
++#define MRX_STP_EN_HI 0
++#define MRX_STP_EN_SZ 1
++#define MRX_STP_OFST_MSK 0x0000ff00
++#define MRX_STP_OFST_I_MSK 0xffff00ff
++#define MRX_STP_OFST_SFT 8
++#define MRX_STP_OFST_HI 15
++#define MRX_STP_OFST_SZ 8
++#define DBG_FF_FULL_MSK 0x0000ffff
++#define DBG_FF_FULL_I_MSK 0xffff0000
++#define DBG_FF_FULL_SFT 0
++#define DBG_FF_FULL_HI 15
++#define DBG_FF_FULL_SZ 16
++#define DBG_FF_FULL_CLR_MSK 0x80000000
++#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff
++#define DBG_FF_FULL_CLR_SFT 31
++#define DBG_FF_FULL_CLR_HI 31
++#define DBG_FF_FULL_CLR_SZ 1
++#define DBG_WFF_FULL_MSK 0x0000ffff
++#define DBG_WFF_FULL_I_MSK 0xffff0000
++#define DBG_WFF_FULL_SFT 0
++#define DBG_WFF_FULL_HI 15
++#define DBG_WFF_FULL_SZ 16
++#define DBG_WFF_FULL_CLR_MSK 0x80000000
++#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff
++#define DBG_WFF_FULL_CLR_SFT 31
++#define DBG_WFF_FULL_CLR_HI 31
++#define DBG_WFF_FULL_CLR_SZ 1
++#define DBG_MB_FULL_MSK 0x0000ffff
++#define DBG_MB_FULL_I_MSK 0xffff0000
++#define DBG_MB_FULL_SFT 0
++#define DBG_MB_FULL_HI 15
++#define DBG_MB_FULL_SZ 16
++#define DBG_MB_FULL_CLR_MSK 0x80000000
++#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff
++#define DBG_MB_FULL_CLR_SFT 31
++#define DBG_MB_FULL_CLR_HI 31
++#define DBG_MB_FULL_CLR_SZ 1
++#define BA_CTRL_MSK 0x00000003
++#define BA_CTRL_I_MSK 0xfffffffc
++#define BA_CTRL_SFT 0
++#define BA_CTRL_HI 1
++#define BA_CTRL_SZ 2
++#define BA_DBG_EN_MSK 0x00000004
++#define BA_DBG_EN_I_MSK 0xfffffffb
++#define BA_DBG_EN_SFT 2
++#define BA_DBG_EN_HI 2
++#define BA_DBG_EN_SZ 1
++#define BA_AGRE_EN_MSK 0x00000008
++#define BA_AGRE_EN_I_MSK 0xfffffff7
++#define BA_AGRE_EN_SFT 3
++#define BA_AGRE_EN_HI 3
++#define BA_AGRE_EN_SZ 1
++#define BA_TA_31_0_MSK 0xffffffff
++#define BA_TA_31_0_I_MSK 0x00000000
++#define BA_TA_31_0_SFT 0
++#define BA_TA_31_0_HI 31
++#define BA_TA_31_0_SZ 32
++#define BA_TA_47_32_MSK 0x0000ffff
++#define BA_TA_47_32_I_MSK 0xffff0000
++#define BA_TA_47_32_SFT 0
++#define BA_TA_47_32_HI 15
++#define BA_TA_47_32_SZ 16
++#define BA_TID_MSK 0x0000000f
++#define BA_TID_I_MSK 0xfffffff0
++#define BA_TID_SFT 0
++#define BA_TID_HI 3
++#define BA_TID_SZ 4
++#define BA_ST_SEQ_MSK 0x00000fff
++#define BA_ST_SEQ_I_MSK 0xfffff000
++#define BA_ST_SEQ_SFT 0
++#define BA_ST_SEQ_HI 11
++#define BA_ST_SEQ_SZ 12
++#define BA_SB0_MSK 0xffffffff
++#define BA_SB0_I_MSK 0x00000000
++#define BA_SB0_SFT 0
++#define BA_SB0_HI 31
++#define BA_SB0_SZ 32
++#define BA_SB1_MSK 0xffffffff
++#define BA_SB1_I_MSK 0x00000000
++#define BA_SB1_SFT 0
++#define BA_SB1_HI 31
++#define BA_SB1_SZ 32
++#define MRX_WD_MSK 0x0001ffff
++#define MRX_WD_I_MSK 0xfffe0000
++#define MRX_WD_SFT 0
++#define MRX_WD_HI 16
++#define MRX_WD_SZ 17
++#define ACK_GEN_EN_MSK 0x00000001
++#define ACK_GEN_EN_I_MSK 0xfffffffe
++#define ACK_GEN_EN_SFT 0
++#define ACK_GEN_EN_HI 0
++#define ACK_GEN_EN_SZ 1
++#define BA_GEN_EN_MSK 0x00000002
++#define BA_GEN_EN_I_MSK 0xfffffffd
++#define BA_GEN_EN_SFT 1
++#define BA_GEN_EN_HI 1
++#define BA_GEN_EN_SZ 1
++#define ACK_GEN_DUR_MSK 0x0000ffff
++#define ACK_GEN_DUR_I_MSK 0xffff0000
++#define ACK_GEN_DUR_SFT 0
++#define ACK_GEN_DUR_HI 15
++#define ACK_GEN_DUR_SZ 16
++#define ACK_GEN_INFO_MSK 0x003f0000
++#define ACK_GEN_INFO_I_MSK 0xffc0ffff
++#define ACK_GEN_INFO_SFT 16
++#define ACK_GEN_INFO_HI 21
++#define ACK_GEN_INFO_SZ 6
++#define ACK_GEN_RA_31_0_MSK 0xffffffff
++#define ACK_GEN_RA_31_0_I_MSK 0x00000000
++#define ACK_GEN_RA_31_0_SFT 0
++#define ACK_GEN_RA_31_0_HI 31
++#define ACK_GEN_RA_31_0_SZ 32
++#define ACK_GEN_RA_47_32_MSK 0x0000ffff
++#define ACK_GEN_RA_47_32_I_MSK 0xffff0000
++#define ACK_GEN_RA_47_32_SFT 0
++#define ACK_GEN_RA_47_32_HI 15
++#define ACK_GEN_RA_47_32_SZ 16
++#define MIB_LEN_FAIL_MSK 0x0000ffff
++#define MIB_LEN_FAIL_I_MSK 0xffff0000
++#define MIB_LEN_FAIL_SFT 0
++#define MIB_LEN_FAIL_HI 15
++#define MIB_LEN_FAIL_SZ 16
++#define TRAP_HW_ID_MSK 0x0000000f
++#define TRAP_HW_ID_I_MSK 0xfffffff0
++#define TRAP_HW_ID_SFT 0
++#define TRAP_HW_ID_HI 3
++#define TRAP_HW_ID_SZ 4
++#define ID_IN_USE_MSK 0x000000ff
++#define ID_IN_USE_I_MSK 0xffffff00
++#define ID_IN_USE_SFT 0
++#define ID_IN_USE_HI 7
++#define ID_IN_USE_SZ 8
++#define MRX_ERR_MSK 0xffffffff
++#define MRX_ERR_I_MSK 0x00000000
++#define MRX_ERR_SFT 0
++#define MRX_ERR_HI 31
++#define MRX_ERR_SZ 32
++#define W0_T0_SEQ_MSK 0x0000ffff
++#define W0_T0_SEQ_I_MSK 0xffff0000
++#define W0_T0_SEQ_SFT 0
++#define W0_T0_SEQ_HI 15
++#define W0_T0_SEQ_SZ 16
++#define W0_T1_SEQ_MSK 0x0000ffff
++#define W0_T1_SEQ_I_MSK 0xffff0000
++#define W0_T1_SEQ_SFT 0
++#define W0_T1_SEQ_HI 15
++#define W0_T1_SEQ_SZ 16
++#define W0_T2_SEQ_MSK 0x0000ffff
++#define W0_T2_SEQ_I_MSK 0xffff0000
++#define W0_T2_SEQ_SFT 0
++#define W0_T2_SEQ_HI 15
++#define W0_T2_SEQ_SZ 16
++#define W0_T3_SEQ_MSK 0x0000ffff
++#define W0_T3_SEQ_I_MSK 0xffff0000
++#define W0_T3_SEQ_SFT 0
++#define W0_T3_SEQ_HI 15
++#define W0_T3_SEQ_SZ 16
++#define W0_T4_SEQ_MSK 0x0000ffff
++#define W0_T4_SEQ_I_MSK 0xffff0000
++#define W0_T4_SEQ_SFT 0
++#define W0_T4_SEQ_HI 15
++#define W0_T4_SEQ_SZ 16
++#define W0_T5_SEQ_MSK 0x0000ffff
++#define W0_T5_SEQ_I_MSK 0xffff0000
++#define W0_T5_SEQ_SFT 0
++#define W0_T5_SEQ_HI 15
++#define W0_T5_SEQ_SZ 16
++#define W0_T6_SEQ_MSK 0x0000ffff
++#define W0_T6_SEQ_I_MSK 0xffff0000
++#define W0_T6_SEQ_SFT 0
++#define W0_T6_SEQ_HI 15
++#define W0_T6_SEQ_SZ 16
++#define W0_T7_SEQ_MSK 0x0000ffff
++#define W0_T7_SEQ_I_MSK 0xffff0000
++#define W0_T7_SEQ_SFT 0
++#define W0_T7_SEQ_HI 15
++#define W0_T7_SEQ_SZ 16
++#define W1_T0_SEQ_MSK 0x0000ffff
++#define W1_T0_SEQ_I_MSK 0xffff0000
++#define W1_T0_SEQ_SFT 0
++#define W1_T0_SEQ_HI 15
++#define W1_T0_SEQ_SZ 16
++#define W1_T1_SEQ_MSK 0x0000ffff
++#define W1_T1_SEQ_I_MSK 0xffff0000
++#define W1_T1_SEQ_SFT 0
++#define W1_T1_SEQ_HI 15
++#define W1_T1_SEQ_SZ 16
++#define W1_T2_SEQ_MSK 0x0000ffff
++#define W1_T2_SEQ_I_MSK 0xffff0000
++#define W1_T2_SEQ_SFT 0
++#define W1_T2_SEQ_HI 15
++#define W1_T2_SEQ_SZ 16
++#define W1_T3_SEQ_MSK 0x0000ffff
++#define W1_T3_SEQ_I_MSK 0xffff0000
++#define W1_T3_SEQ_SFT 0
++#define W1_T3_SEQ_HI 15
++#define W1_T3_SEQ_SZ 16
++#define W1_T4_SEQ_MSK 0x0000ffff
++#define W1_T4_SEQ_I_MSK 0xffff0000
++#define W1_T4_SEQ_SFT 0
++#define W1_T4_SEQ_HI 15
++#define W1_T4_SEQ_SZ 16
++#define W1_T5_SEQ_MSK 0x0000ffff
++#define W1_T5_SEQ_I_MSK 0xffff0000
++#define W1_T5_SEQ_SFT 0
++#define W1_T5_SEQ_HI 15
++#define W1_T5_SEQ_SZ 16
++#define W1_T6_SEQ_MSK 0x0000ffff
++#define W1_T6_SEQ_I_MSK 0xffff0000
++#define W1_T6_SEQ_SFT 0
++#define W1_T6_SEQ_HI 15
++#define W1_T6_SEQ_SZ 16
++#define W1_T7_SEQ_MSK 0x0000ffff
++#define W1_T7_SEQ_I_MSK 0xffff0000
++#define W1_T7_SEQ_SFT 0
++#define W1_T7_SEQ_HI 15
++#define W1_T7_SEQ_SZ 16
++#define ADDR1A_SEL_MSK 0x00000003
++#define ADDR1A_SEL_I_MSK 0xfffffffc
++#define ADDR1A_SEL_SFT 0
++#define ADDR1A_SEL_HI 1
++#define ADDR1A_SEL_SZ 2
++#define ADDR2A_SEL_MSK 0x0000000c
++#define ADDR2A_SEL_I_MSK 0xfffffff3
++#define ADDR2A_SEL_SFT 2
++#define ADDR2A_SEL_HI 3
++#define ADDR2A_SEL_SZ 2
++#define ADDR3A_SEL_MSK 0x00000030
++#define ADDR3A_SEL_I_MSK 0xffffffcf
++#define ADDR3A_SEL_SFT 4
++#define ADDR3A_SEL_HI 5
++#define ADDR3A_SEL_SZ 2
++#define ADDR1B_SEL_MSK 0x000000c0
++#define ADDR1B_SEL_I_MSK 0xffffff3f
++#define ADDR1B_SEL_SFT 6
++#define ADDR1B_SEL_HI 7
++#define ADDR1B_SEL_SZ 2
++#define ADDR2B_SEL_MSK 0x00000300
++#define ADDR2B_SEL_I_MSK 0xfffffcff
++#define ADDR2B_SEL_SFT 8
++#define ADDR2B_SEL_HI 9
++#define ADDR2B_SEL_SZ 2
++#define ADDR3B_SEL_MSK 0x00000c00
++#define ADDR3B_SEL_I_MSK 0xfffff3ff
++#define ADDR3B_SEL_SFT 10
++#define ADDR3B_SEL_HI 11
++#define ADDR3B_SEL_SZ 2
++#define ADDR3C_SEL_MSK 0x00003000
++#define ADDR3C_SEL_I_MSK 0xffffcfff
++#define ADDR3C_SEL_SFT 12
++#define ADDR3C_SEL_HI 13
++#define ADDR3C_SEL_SZ 2
++#define FRM_CTRL_MSK 0x0000003f
++#define FRM_CTRL_I_MSK 0xffffffc0
++#define FRM_CTRL_SFT 0
++#define FRM_CTRL_HI 5
++#define FRM_CTRL_SZ 6
++#define CSR_PHY_INFO_MSK 0x00007fff
++#define CSR_PHY_INFO_I_MSK 0xffff8000
++#define CSR_PHY_INFO_SFT 0
++#define CSR_PHY_INFO_HI 14
++#define CSR_PHY_INFO_SZ 15
++#define AMPDU_SIG_MSK 0x000000ff
++#define AMPDU_SIG_I_MSK 0xffffff00
++#define AMPDU_SIG_SFT 0
++#define AMPDU_SIG_HI 7
++#define AMPDU_SIG_SZ 8
++#define MIB_AMPDU_MSK 0xffffffff
++#define MIB_AMPDU_I_MSK 0x00000000
++#define MIB_AMPDU_SFT 0
++#define MIB_AMPDU_HI 31
++#define MIB_AMPDU_SZ 32
++#define LEN_FLT_MSK 0x0000ffff
++#define LEN_FLT_I_MSK 0xffff0000
++#define LEN_FLT_SFT 0
++#define LEN_FLT_HI 15
++#define LEN_FLT_SZ 16
++#define MIB_DELIMITER_MSK 0x0000ffff
++#define MIB_DELIMITER_I_MSK 0xffff0000
++#define MIB_DELIMITER_SFT 0
++#define MIB_DELIMITER_HI 15
++#define MIB_DELIMITER_SZ 16
++#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000
++#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
++#define MTX_INT_Q0_Q_EMPTY_SFT 16
++#define MTX_INT_Q0_Q_EMPTY_HI 16
++#define MTX_INT_Q0_Q_EMPTY_SZ 1
++#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
++#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
++#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17
++#define MTX_INT_Q0_TXOP_RUNOUT_HI 17
++#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000
++#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
++#define MTX_INT_Q1_Q_EMPTY_SFT 18
++#define MTX_INT_Q1_Q_EMPTY_HI 18
++#define MTX_INT_Q1_Q_EMPTY_SZ 1
++#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
++#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
++#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19
++#define MTX_INT_Q1_TXOP_RUNOUT_HI 19
++#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000
++#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
++#define MTX_INT_Q2_Q_EMPTY_SFT 20
++#define MTX_INT_Q2_Q_EMPTY_HI 20
++#define MTX_INT_Q2_Q_EMPTY_SZ 1
++#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
++#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
++#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21
++#define MTX_INT_Q2_TXOP_RUNOUT_HI 21
++#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000
++#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
++#define MTX_INT_Q3_Q_EMPTY_SFT 22
++#define MTX_INT_Q3_Q_EMPTY_HI 22
++#define MTX_INT_Q3_Q_EMPTY_SZ 1
++#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
++#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
++#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23
++#define MTX_INT_Q3_TXOP_RUNOUT_HI 23
++#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000
++#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
++#define MTX_INT_Q4_Q_EMPTY_SFT 24
++#define MTX_INT_Q4_Q_EMPTY_HI 24
++#define MTX_INT_Q4_Q_EMPTY_SZ 1
++#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
++#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
++#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25
++#define MTX_INT_Q4_TXOP_RUNOUT_HI 25
++#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000
++#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
++#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16
++#define MTX_EN_INT_Q0_Q_EMPTY_HI 16
++#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000
++#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
++#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18
++#define MTX_EN_INT_Q1_Q_EMPTY_HI 18
++#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000
++#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
++#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20
++#define MTX_EN_INT_Q2_Q_EMPTY_HI 20
++#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000
++#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
++#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22
++#define MTX_EN_INT_Q3_Q_EMPTY_HI 22
++#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000
++#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
++#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24
++#define MTX_EN_INT_Q4_Q_EMPTY_HI 24
++#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1
++#define MTX_MTX2PHY_SLOW_MSK 0x00000001
++#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe
++#define MTX_MTX2PHY_SLOW_SFT 0
++#define MTX_MTX2PHY_SLOW_HI 0
++#define MTX_MTX2PHY_SLOW_SZ 1
++#define MTX_M2M_SLOW_PRD_MSK 0x0000000e
++#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1
++#define MTX_M2M_SLOW_PRD_SFT 1
++#define MTX_M2M_SLOW_PRD_HI 3
++#define MTX_M2M_SLOW_PRD_SZ 3
++#define MTX_AMPDU_CRC_AUTO_MSK 0x00000020
++#define MTX_AMPDU_CRC_AUTO_I_MSK 0xffffffdf
++#define MTX_AMPDU_CRC_AUTO_SFT 5
++#define MTX_AMPDU_CRC_AUTO_HI 5
++#define MTX_AMPDU_CRC_AUTO_SZ 1
++#define MTX_FAST_RSP_MODE_MSK 0x00000040
++#define MTX_FAST_RSP_MODE_I_MSK 0xffffffbf
++#define MTX_FAST_RSP_MODE_SFT 6
++#define MTX_FAST_RSP_MODE_HI 6
++#define MTX_FAST_RSP_MODE_SZ 1
++#define MTX_RAW_DATA_MODE_MSK 0x00000080
++#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f
++#define MTX_RAW_DATA_MODE_SFT 7
++#define MTX_RAW_DATA_MODE_HI 7
++#define MTX_RAW_DATA_MODE_SZ 1
++#define MTX_ACK_DUR0_MSK 0x00000100
++#define MTX_ACK_DUR0_I_MSK 0xfffffeff
++#define MTX_ACK_DUR0_SFT 8
++#define MTX_ACK_DUR0_HI 8
++#define MTX_ACK_DUR0_SZ 1
++#define MTX_TSF_AUTO_BCN_MSK 0x00000400
++#define MTX_TSF_AUTO_BCN_I_MSK 0xfffffbff
++#define MTX_TSF_AUTO_BCN_SFT 10
++#define MTX_TSF_AUTO_BCN_HI 10
++#define MTX_TSF_AUTO_BCN_SZ 1
++#define MTX_TSF_AUTO_MISC_MSK 0x00000800
++#define MTX_TSF_AUTO_MISC_I_MSK 0xfffff7ff
++#define MTX_TSF_AUTO_MISC_SFT 11
++#define MTX_TSF_AUTO_MISC_HI 11
++#define MTX_TSF_AUTO_MISC_SZ 1
++#define MTX_FORCE_CS_IDLE_MSK 0x00001000
++#define MTX_FORCE_CS_IDLE_I_MSK 0xffffefff
++#define MTX_FORCE_CS_IDLE_SFT 12
++#define MTX_FORCE_CS_IDLE_HI 12
++#define MTX_FORCE_CS_IDLE_SZ 1
++#define MTX_FORCE_BKF_RXEN0_MSK 0x00002000
++#define MTX_FORCE_BKF_RXEN0_I_MSK 0xffffdfff
++#define MTX_FORCE_BKF_RXEN0_SFT 13
++#define MTX_FORCE_BKF_RXEN0_HI 13
++#define MTX_FORCE_BKF_RXEN0_SZ 1
++#define MTX_FORCE_DMA_RXEN0_MSK 0x00004000
++#define MTX_FORCE_DMA_RXEN0_I_MSK 0xffffbfff
++#define MTX_FORCE_DMA_RXEN0_SFT 14
++#define MTX_FORCE_DMA_RXEN0_HI 14
++#define MTX_FORCE_DMA_RXEN0_SZ 1
++#define MTX_FORCE_RXEN0_MSK 0x00008000
++#define MTX_FORCE_RXEN0_I_MSK 0xffff7fff
++#define MTX_FORCE_RXEN0_SFT 15
++#define MTX_FORCE_RXEN0_HI 15
++#define MTX_FORCE_RXEN0_SZ 1
++#define MTX_HALT_Q_MB_MSK 0x003f0000
++#define MTX_HALT_Q_MB_I_MSK 0xffc0ffff
++#define MTX_HALT_Q_MB_SFT 16
++#define MTX_HALT_Q_MB_HI 21
++#define MTX_HALT_Q_MB_SZ 6
++#define MTX_CTS_SET_DIF_MSK 0x00400000
++#define MTX_CTS_SET_DIF_I_MSK 0xffbfffff
++#define MTX_CTS_SET_DIF_SFT 22
++#define MTX_CTS_SET_DIF_HI 22
++#define MTX_CTS_SET_DIF_SZ 1
++#define MTX_AMPDU_SET_DIF_MSK 0x00800000
++#define MTX_AMPDU_SET_DIF_I_MSK 0xff7fffff
++#define MTX_AMPDU_SET_DIF_SFT 23
++#define MTX_AMPDU_SET_DIF_HI 23
++#define MTX_AMPDU_SET_DIF_SZ 1
++#define MTX_EDCCA_TOUT_MSK 0x000003ff
++#define MTX_EDCCA_TOUT_I_MSK 0xfffffc00
++#define MTX_EDCCA_TOUT_SFT 0
++#define MTX_EDCCA_TOUT_HI 9
++#define MTX_EDCCA_TOUT_SZ 10
++#define MTX_INT_BCN_MSK 0x00000002
++#define MTX_INT_BCN_I_MSK 0xfffffffd
++#define MTX_INT_BCN_SFT 1
++#define MTX_INT_BCN_HI 1
++#define MTX_INT_BCN_SZ 1
++#define MTX_INT_DTIM_MSK 0x00000008
++#define MTX_INT_DTIM_I_MSK 0xfffffff7
++#define MTX_INT_DTIM_SFT 3
++#define MTX_INT_DTIM_HI 3
++#define MTX_INT_DTIM_SZ 1
++#define MTX_EN_INT_BCN_MSK 0x00000002
++#define MTX_EN_INT_BCN_I_MSK 0xfffffffd
++#define MTX_EN_INT_BCN_SFT 1
++#define MTX_EN_INT_BCN_HI 1
++#define MTX_EN_INT_BCN_SZ 1
++#define MTX_EN_INT_DTIM_MSK 0x00000008
++#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7
++#define MTX_EN_INT_DTIM_SFT 3
++#define MTX_EN_INT_DTIM_HI 3
++#define MTX_EN_INT_DTIM_SZ 1
++#define MTX_BCN_TIMER_EN_MSK 0x00000001
++#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe
++#define MTX_BCN_TIMER_EN_SFT 0
++#define MTX_BCN_TIMER_EN_HI 0
++#define MTX_BCN_TIMER_EN_SZ 1
++#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002
++#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd
++#define MTX_TIME_STAMP_AUTO_FILL_SFT 1
++#define MTX_TIME_STAMP_AUTO_FILL_HI 1
++#define MTX_TIME_STAMP_AUTO_FILL_SZ 1
++#define MTX_TSF_TIMER_EN_MSK 0x00000020
++#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf
++#define MTX_TSF_TIMER_EN_SFT 5
++#define MTX_TSF_TIMER_EN_HI 5
++#define MTX_TSF_TIMER_EN_SZ 1
++#define MTX_HALT_MNG_UNTIL_DTIM_MSK 0x00000040
++#define MTX_HALT_MNG_UNTIL_DTIM_I_MSK 0xffffffbf
++#define MTX_HALT_MNG_UNTIL_DTIM_SFT 6
++#define MTX_HALT_MNG_UNTIL_DTIM_HI 6
++#define MTX_HALT_MNG_UNTIL_DTIM_SZ 1
++#define MTX_INT_DTIM_NUM_MSK 0x0000ff00
++#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff
++#define MTX_INT_DTIM_NUM_SFT 8
++#define MTX_INT_DTIM_NUM_HI 15
++#define MTX_INT_DTIM_NUM_SZ 8
++#define MTX_AUTO_FLUSH_Q4_MSK 0x00010000
++#define MTX_AUTO_FLUSH_Q4_I_MSK 0xfffeffff
++#define MTX_AUTO_FLUSH_Q4_SFT 16
++#define MTX_AUTO_FLUSH_Q4_HI 16
++#define MTX_AUTO_FLUSH_Q4_SZ 1
++#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001
++#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe
++#define MTX_BCN_PKTID_CH_LOCK_SFT 0
++#define MTX_BCN_PKTID_CH_LOCK_HI 0
++#define MTX_BCN_PKTID_CH_LOCK_SZ 1
++#define MTX_BCN_CFG_VLD_MSK 0x00000006
++#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9
++#define MTX_BCN_CFG_VLD_SFT 1
++#define MTX_BCN_CFG_VLD_HI 2
++#define MTX_BCN_CFG_VLD_SZ 2
++#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008
++#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7
++#define MTX_AUTO_BCN_ONGOING_SFT 3
++#define MTX_AUTO_BCN_ONGOING_HI 3
++#define MTX_AUTO_BCN_ONGOING_SZ 1
++#define MTX_BCN_TIMER_MSK 0xffff0000
++#define MTX_BCN_TIMER_I_MSK 0x0000ffff
++#define MTX_BCN_TIMER_SFT 16
++#define MTX_BCN_TIMER_HI 31
++#define MTX_BCN_TIMER_SZ 16
++#define MTX_BCN_PERIOD_MSK 0x0000ffff
++#define MTX_BCN_PERIOD_I_MSK 0xffff0000
++#define MTX_BCN_PERIOD_SFT 0
++#define MTX_BCN_PERIOD_HI 15
++#define MTX_BCN_PERIOD_SZ 16
++#define MTX_DTIM_NUM_MSK 0xff000000
++#define MTX_DTIM_NUM_I_MSK 0x00ffffff
++#define MTX_DTIM_NUM_SFT 24
++#define MTX_DTIM_NUM_HI 31
++#define MTX_DTIM_NUM_SZ 8
++#define MTX_BCN_TSF_L_MSK 0xffffffff
++#define MTX_BCN_TSF_L_I_MSK 0x00000000
++#define MTX_BCN_TSF_L_SFT 0
++#define MTX_BCN_TSF_L_HI 31
++#define MTX_BCN_TSF_L_SZ 32
++#define MTX_BCN_TSF_U_MSK 0xffffffff
++#define MTX_BCN_TSF_U_I_MSK 0x00000000
++#define MTX_BCN_TSF_U_SFT 0
++#define MTX_BCN_TSF_U_HI 31
++#define MTX_BCN_TSF_U_SZ 32
++#define MTX_BCN_PKT_ID0_MSK 0x0000007f
++#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80
++#define MTX_BCN_PKT_ID0_SFT 0
++#define MTX_BCN_PKT_ID0_HI 6
++#define MTX_BCN_PKT_ID0_SZ 7
++#define MTX_DTIM_OFST0_MSK 0x03ff0000
++#define MTX_DTIM_OFST0_I_MSK 0xfc00ffff
++#define MTX_DTIM_OFST0_SFT 16
++#define MTX_DTIM_OFST0_HI 25
++#define MTX_DTIM_OFST0_SZ 10
++#define MTX_BCN_PKT_ID1_MSK 0x0000007f
++#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80
++#define MTX_BCN_PKT_ID1_SFT 0
++#define MTX_BCN_PKT_ID1_HI 6
++#define MTX_BCN_PKT_ID1_SZ 7
++#define MTX_DTIM_OFST1_MSK 0x03ff0000
++#define MTX_DTIM_OFST1_I_MSK 0xfc00ffff
++#define MTX_DTIM_OFST1_SFT 16
++#define MTX_DTIM_OFST1_HI 25
++#define MTX_DTIM_OFST1_SZ 10
++#define MTX_CCA_MSK 0x00000001
++#define MTX_CCA_I_MSK 0xfffffffe
++#define MTX_CCA_SFT 0
++#define MTX_CCA_HI 0
++#define MTX_CCA_SZ 1
++#define MRX_CCA_MSK 0x00000002
++#define MRX_CCA_I_MSK 0xfffffffd
++#define MRX_CCA_SFT 1
++#define MRX_CCA_HI 1
++#define MRX_CCA_SZ 1
++#define MTX_DMA_FSM_MSK 0x0000001c
++#define MTX_DMA_FSM_I_MSK 0xffffffe3
++#define MTX_DMA_FSM_SFT 2
++#define MTX_DMA_FSM_HI 4
++#define MTX_DMA_FSM_SZ 3
++#define CH_ST_FSM_MSK 0x000000e0
++#define CH_ST_FSM_I_MSK 0xffffff1f
++#define CH_ST_FSM_SFT 5
++#define CH_ST_FSM_HI 7
++#define CH_ST_FSM_SZ 3
++#define MTX_GNT_LOCK_MSK 0x00000100
++#define MTX_GNT_LOCK_I_MSK 0xfffffeff
++#define MTX_GNT_LOCK_SFT 8
++#define MTX_GNT_LOCK_HI 8
++#define MTX_GNT_LOCK_SZ 1
++#define MTX_DMA_REQ_MSK 0x00000200
++#define MTX_DMA_REQ_I_MSK 0xfffffdff
++#define MTX_DMA_REQ_SFT 9
++#define MTX_DMA_REQ_HI 9
++#define MTX_DMA_REQ_SZ 1
++#define MTX_Q_REQ_MSK 0x00000400
++#define MTX_Q_REQ_I_MSK 0xfffffbff
++#define MTX_Q_REQ_SFT 10
++#define MTX_Q_REQ_HI 10
++#define MTX_Q_REQ_SZ 1
++#define MTX_TX_EN_MSK 0x00000800
++#define MTX_TX_EN_I_MSK 0xfffff7ff
++#define MTX_TX_EN_SFT 11
++#define MTX_TX_EN_HI 11
++#define MTX_TX_EN_SZ 1
++#define MRX_RX_EN_MSK 0x00001000
++#define MRX_RX_EN_I_MSK 0xffffefff
++#define MRX_RX_EN_SFT 12
++#define MRX_RX_EN_HI 12
++#define MRX_RX_EN_SZ 1
++#define DBG_PRTC_PRD_MSK 0x00002000
++#define DBG_PRTC_PRD_I_MSK 0xffffdfff
++#define DBG_PRTC_PRD_SFT 13
++#define DBG_PRTC_PRD_HI 13
++#define DBG_PRTC_PRD_SZ 1
++#define DBG_DMA_RDY_MSK 0x00004000
++#define DBG_DMA_RDY_I_MSK 0xffffbfff
++#define DBG_DMA_RDY_SFT 14
++#define DBG_DMA_RDY_HI 14
++#define DBG_DMA_RDY_SZ 1
++#define DBG_WAIT_RSP_MSK 0x00008000
++#define DBG_WAIT_RSP_I_MSK 0xffff7fff
++#define DBG_WAIT_RSP_SFT 15
++#define DBG_WAIT_RSP_HI 15
++#define DBG_WAIT_RSP_SZ 1
++#define DBG_CFRM_BUSY_MSK 0x00010000
++#define DBG_CFRM_BUSY_I_MSK 0xfffeffff
++#define DBG_CFRM_BUSY_SFT 16
++#define DBG_CFRM_BUSY_HI 16
++#define DBG_CFRM_BUSY_SZ 1
++#define DBG_RST_MSK 0x00000001
++#define DBG_RST_I_MSK 0xfffffffe
++#define DBG_RST_SFT 0
++#define DBG_RST_HI 0
++#define DBG_RST_SZ 1
++#define DBG_MODE_MSK 0x00000002
++#define DBG_MODE_I_MSK 0xfffffffd
++#define DBG_MODE_SFT 1
++#define DBG_MODE_HI 1
++#define DBG_MODE_SZ 1
++#define MB_REQ_DUR_MSK 0x0000ffff
++#define MB_REQ_DUR_I_MSK 0xffff0000
++#define MB_REQ_DUR_SFT 0
++#define MB_REQ_DUR_HI 15
++#define MB_REQ_DUR_SZ 16
++#define RX_EN_DUR_MSK 0xffff0000
++#define RX_EN_DUR_I_MSK 0x0000ffff
++#define RX_EN_DUR_SFT 16
++#define RX_EN_DUR_HI 31
++#define RX_EN_DUR_SZ 16
++#define RX_CS_DUR_MSK 0x0000ffff
++#define RX_CS_DUR_I_MSK 0xffff0000
++#define RX_CS_DUR_SFT 0
++#define RX_CS_DUR_HI 15
++#define RX_CS_DUR_SZ 16
++#define TX_CCA_DUR_MSK 0xffff0000
++#define TX_CCA_DUR_I_MSK 0x0000ffff
++#define TX_CCA_DUR_SFT 16
++#define TX_CCA_DUR_HI 31
++#define TX_CCA_DUR_SZ 16
++#define Q_REQ_DUR_MSK 0x0000ffff
++#define Q_REQ_DUR_I_MSK 0xffff0000
++#define Q_REQ_DUR_SFT 0
++#define Q_REQ_DUR_HI 15
++#define Q_REQ_DUR_SZ 16
++#define CH_STA0_DUR_MSK 0xffff0000
++#define CH_STA0_DUR_I_MSK 0x0000ffff
++#define CH_STA0_DUR_SFT 16
++#define CH_STA0_DUR_HI 31
++#define CH_STA0_DUR_SZ 16
++#define MTX_DUR_RSP_TOUT_B_MSK 0x000000ff
++#define MTX_DUR_RSP_TOUT_B_I_MSK 0xffffff00
++#define MTX_DUR_RSP_TOUT_B_SFT 0
++#define MTX_DUR_RSP_TOUT_B_HI 7
++#define MTX_DUR_RSP_TOUT_B_SZ 8
++#define MTX_DUR_RSP_TOUT_G_MSK 0x0000ff00
++#define MTX_DUR_RSP_TOUT_G_I_MSK 0xffff00ff
++#define MTX_DUR_RSP_TOUT_G_SFT 8
++#define MTX_DUR_RSP_TOUT_G_HI 15
++#define MTX_DUR_RSP_TOUT_G_SZ 8
++#define MTX_DUR_RSP_SIFS_MSK 0x000000ff
++#define MTX_DUR_RSP_SIFS_I_MSK 0xffffff00
++#define MTX_DUR_RSP_SIFS_SFT 0
++#define MTX_DUR_RSP_SIFS_HI 7
++#define MTX_DUR_RSP_SIFS_SZ 8
++#define MTX_DUR_BURST_SIFS_MSK 0x0000ff00
++#define MTX_DUR_BURST_SIFS_I_MSK 0xffff00ff
++#define MTX_DUR_BURST_SIFS_SFT 8
++#define MTX_DUR_BURST_SIFS_HI 15
++#define MTX_DUR_BURST_SIFS_SZ 8
++#define MTX_DUR_SLOT_MSK 0x003f0000
++#define MTX_DUR_SLOT_I_MSK 0xffc0ffff
++#define MTX_DUR_SLOT_SFT 16
++#define MTX_DUR_SLOT_HI 21
++#define MTX_DUR_SLOT_SZ 6
++#define MTX_DUR_RSP_EIFS_MSK 0xffc00000
++#define MTX_DUR_RSP_EIFS_I_MSK 0x003fffff
++#define MTX_DUR_RSP_EIFS_SFT 22
++#define MTX_DUR_RSP_EIFS_HI 31
++#define MTX_DUR_RSP_EIFS_SZ 10
++#define MTX_DUR_RSP_SIFS_G_MSK 0x000000ff
++#define MTX_DUR_RSP_SIFS_G_I_MSK 0xffffff00
++#define MTX_DUR_RSP_SIFS_G_SFT 0
++#define MTX_DUR_RSP_SIFS_G_HI 7
++#define MTX_DUR_RSP_SIFS_G_SZ 8
++#define MTX_DUR_BURST_SIFS_G_MSK 0x0000ff00
++#define MTX_DUR_BURST_SIFS_G_I_MSK 0xffff00ff
++#define MTX_DUR_BURST_SIFS_G_SFT 8
++#define MTX_DUR_BURST_SIFS_G_HI 15
++#define MTX_DUR_BURST_SIFS_G_SZ 8
++#define MTX_DUR_SLOT_G_MSK 0x003f0000
++#define MTX_DUR_SLOT_G_I_MSK 0xffc0ffff
++#define MTX_DUR_SLOT_G_SFT 16
++#define MTX_DUR_SLOT_G_HI 21
++#define MTX_DUR_SLOT_G_SZ 6
++#define MTX_DUR_RSP_EIFS_G_MSK 0xffc00000
++#define MTX_DUR_RSP_EIFS_G_I_MSK 0x003fffff
++#define MTX_DUR_RSP_EIFS_G_SFT 22
++#define MTX_DUR_RSP_EIFS_G_HI 31
++#define MTX_DUR_RSP_EIFS_G_SZ 10
++#define CH_STA1_DUR_MSK 0x0000ffff
++#define CH_STA1_DUR_I_MSK 0xffff0000
++#define CH_STA1_DUR_SFT 0
++#define CH_STA1_DUR_HI 15
++#define CH_STA1_DUR_SZ 16
++#define CH_STA2_DUR_MSK 0xffff0000
++#define CH_STA2_DUR_I_MSK 0x0000ffff
++#define CH_STA2_DUR_SFT 16
++#define CH_STA2_DUR_HI 31
++#define CH_STA2_DUR_SZ 16
++#define MTX_NAV_MSK 0x0000ffff
++#define MTX_NAV_I_MSK 0xffff0000
++#define MTX_NAV_SFT 0
++#define MTX_NAV_HI 15
++#define MTX_NAV_SZ 16
++#define MTX_MIB_CNT0_MSK 0x3fffffff
++#define MTX_MIB_CNT0_I_MSK 0xc0000000
++#define MTX_MIB_CNT0_SFT 0
++#define MTX_MIB_CNT0_HI 29
++#define MTX_MIB_CNT0_SZ 30
++#define MTX_MIB_EN0_MSK 0x40000000
++#define MTX_MIB_EN0_I_MSK 0xbfffffff
++#define MTX_MIB_EN0_SFT 30
++#define MTX_MIB_EN0_HI 30
++#define MTX_MIB_EN0_SZ 1
++#define MTX_MIB_CNT1_MSK 0x3fffffff
++#define MTX_MIB_CNT1_I_MSK 0xc0000000
++#define MTX_MIB_CNT1_SFT 0
++#define MTX_MIB_CNT1_HI 29
++#define MTX_MIB_CNT1_SZ 30
++#define MTX_MIB_EN1_MSK 0x40000000
++#define MTX_MIB_EN1_I_MSK 0xbfffffff
++#define MTX_MIB_EN1_SFT 30
++#define MTX_MIB_EN1_HI 30
++#define MTX_MIB_EN1_SZ 1
++#define CH_STA3_DUR_MSK 0x0000ffff
++#define CH_STA3_DUR_I_MSK 0xffff0000
++#define CH_STA3_DUR_SFT 0
++#define CH_STA3_DUR_HI 15
++#define CH_STA3_DUR_SZ 16
++#define CH_STA4_DUR_MSK 0xffff0000
++#define CH_STA4_DUR_I_MSK 0x0000ffff
++#define CH_STA4_DUR_SFT 16
++#define CH_STA4_DUR_HI 31
++#define CH_STA4_DUR_SZ 16
++#define TXQ0_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ0_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ0_MTX_Q_PRE_LD_SFT 1
++#define TXQ0_MTX_Q_PRE_LD_HI 1
++#define TXQ0_MTX_Q_PRE_LD_SZ 1
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ0_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ0_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ0_MTX_Q_RND_MODE_SFT 6
++#define TXQ0_MTX_Q_RND_MODE_HI 7
++#define TXQ0_MTX_Q_RND_MODE_SZ 2
++#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ0_MTX_Q_AIFSN_SFT 0
++#define TXQ0_MTX_Q_AIFSN_HI 3
++#define TXQ0_MTX_Q_AIFSN_SZ 4
++#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ0_MTX_Q_ECWMIN_SFT 8
++#define TXQ0_MTX_Q_ECWMIN_HI 11
++#define TXQ0_MTX_Q_ECWMIN_SZ 4
++#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ0_MTX_Q_ECWMAX_SFT 12
++#define TXQ0_MTX_Q_ECWMAX_HI 15
++#define TXQ0_MTX_Q_ECWMAX_SZ 4
++#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ0_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ0_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ0_MTX_Q_BKF_CNT_SFT 0
++#define TXQ0_MTX_Q_BKF_CNT_HI 15
++#define TXQ0_MTX_Q_BKF_CNT_SZ 16
++#define TXQ0_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ0_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ0_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ0_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ0_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ0_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ0_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ0_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ0_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ0_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ0_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ0_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ0_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ0_MTX_Q_ID_MAP_L_HI 31
++#define TXQ0_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ0_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ0_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ0_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ0_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ0_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ0_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ0_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ0_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ0_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ0_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ1_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ1_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ1_MTX_Q_PRE_LD_SFT 1
++#define TXQ1_MTX_Q_PRE_LD_HI 1
++#define TXQ1_MTX_Q_PRE_LD_SZ 1
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ1_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ1_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ1_MTX_Q_RND_MODE_SFT 6
++#define TXQ1_MTX_Q_RND_MODE_HI 7
++#define TXQ1_MTX_Q_RND_MODE_SZ 2
++#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ1_MTX_Q_AIFSN_SFT 0
++#define TXQ1_MTX_Q_AIFSN_HI 3
++#define TXQ1_MTX_Q_AIFSN_SZ 4
++#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ1_MTX_Q_ECWMIN_SFT 8
++#define TXQ1_MTX_Q_ECWMIN_HI 11
++#define TXQ1_MTX_Q_ECWMIN_SZ 4
++#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ1_MTX_Q_ECWMAX_SFT 12
++#define TXQ1_MTX_Q_ECWMAX_HI 15
++#define TXQ1_MTX_Q_ECWMAX_SZ 4
++#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ1_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ1_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ1_MTX_Q_BKF_CNT_SFT 0
++#define TXQ1_MTX_Q_BKF_CNT_HI 15
++#define TXQ1_MTX_Q_BKF_CNT_SZ 16
++#define TXQ1_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ1_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ1_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ1_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ1_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ1_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ1_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ1_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ1_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ1_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ1_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ1_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ1_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ1_MTX_Q_ID_MAP_L_HI 31
++#define TXQ1_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ1_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ1_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ1_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ1_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ1_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ1_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ1_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ1_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ1_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ1_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ2_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ2_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ2_MTX_Q_PRE_LD_SFT 1
++#define TXQ2_MTX_Q_PRE_LD_HI 1
++#define TXQ2_MTX_Q_PRE_LD_SZ 1
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ2_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ2_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ2_MTX_Q_RND_MODE_SFT 6
++#define TXQ2_MTX_Q_RND_MODE_HI 7
++#define TXQ2_MTX_Q_RND_MODE_SZ 2
++#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ2_MTX_Q_AIFSN_SFT 0
++#define TXQ2_MTX_Q_AIFSN_HI 3
++#define TXQ2_MTX_Q_AIFSN_SZ 4
++#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ2_MTX_Q_ECWMIN_SFT 8
++#define TXQ2_MTX_Q_ECWMIN_HI 11
++#define TXQ2_MTX_Q_ECWMIN_SZ 4
++#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ2_MTX_Q_ECWMAX_SFT 12
++#define TXQ2_MTX_Q_ECWMAX_HI 15
++#define TXQ2_MTX_Q_ECWMAX_SZ 4
++#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ2_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ2_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ2_MTX_Q_BKF_CNT_SFT 0
++#define TXQ2_MTX_Q_BKF_CNT_HI 15
++#define TXQ2_MTX_Q_BKF_CNT_SZ 16
++#define TXQ2_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ2_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ2_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ2_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ2_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ2_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ2_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ2_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ2_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ2_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ2_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ2_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ2_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ2_MTX_Q_ID_MAP_L_HI 31
++#define TXQ2_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ2_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ2_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ2_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ2_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ2_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ2_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ2_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ2_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ2_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ2_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ3_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ3_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ3_MTX_Q_PRE_LD_SFT 1
++#define TXQ3_MTX_Q_PRE_LD_HI 1
++#define TXQ3_MTX_Q_PRE_LD_SZ 1
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ3_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ3_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ3_MTX_Q_RND_MODE_SFT 6
++#define TXQ3_MTX_Q_RND_MODE_HI 7
++#define TXQ3_MTX_Q_RND_MODE_SZ 2
++#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ3_MTX_Q_AIFSN_SFT 0
++#define TXQ3_MTX_Q_AIFSN_HI 3
++#define TXQ3_MTX_Q_AIFSN_SZ 4
++#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ3_MTX_Q_ECWMIN_SFT 8
++#define TXQ3_MTX_Q_ECWMIN_HI 11
++#define TXQ3_MTX_Q_ECWMIN_SZ 4
++#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ3_MTX_Q_ECWMAX_SFT 12
++#define TXQ3_MTX_Q_ECWMAX_HI 15
++#define TXQ3_MTX_Q_ECWMAX_SZ 4
++#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ3_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ3_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ3_MTX_Q_BKF_CNT_SFT 0
++#define TXQ3_MTX_Q_BKF_CNT_HI 15
++#define TXQ3_MTX_Q_BKF_CNT_SZ 16
++#define TXQ3_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ3_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ3_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ3_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ3_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ3_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ3_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ3_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ3_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ3_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ3_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ3_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ3_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ3_MTX_Q_ID_MAP_L_HI 31
++#define TXQ3_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ3_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ3_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ3_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ3_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ3_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ3_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ3_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ3_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ3_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ3_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ4_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ4_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ4_MTX_Q_PRE_LD_SFT 1
++#define TXQ4_MTX_Q_PRE_LD_HI 1
++#define TXQ4_MTX_Q_PRE_LD_SZ 1
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ4_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ4_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ4_MTX_Q_RND_MODE_SFT 6
++#define TXQ4_MTX_Q_RND_MODE_HI 7
++#define TXQ4_MTX_Q_RND_MODE_SZ 2
++#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ4_MTX_Q_AIFSN_SFT 0
++#define TXQ4_MTX_Q_AIFSN_HI 3
++#define TXQ4_MTX_Q_AIFSN_SZ 4
++#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ4_MTX_Q_ECWMIN_SFT 8
++#define TXQ4_MTX_Q_ECWMIN_HI 11
++#define TXQ4_MTX_Q_ECWMIN_SZ 4
++#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ4_MTX_Q_ECWMAX_SFT 12
++#define TXQ4_MTX_Q_ECWMAX_HI 15
++#define TXQ4_MTX_Q_ECWMAX_SZ 4
++#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ4_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ4_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ4_MTX_Q_BKF_CNT_SFT 0
++#define TXQ4_MTX_Q_BKF_CNT_HI 15
++#define TXQ4_MTX_Q_BKF_CNT_SZ 16
++#define TXQ4_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ4_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ4_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ4_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ4_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ4_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ4_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ4_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ4_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ4_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ4_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ4_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ4_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ4_MTX_Q_ID_MAP_L_HI 31
++#define TXQ4_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ4_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ4_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ4_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ4_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ4_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ4_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ4_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ4_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ4_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ4_MTX_Q_TXOP_OV_THD_SZ 16
++#define VALID0_MSK 0x00000001
++#define VALID0_I_MSK 0xfffffffe
++#define VALID0_SFT 0
++#define VALID0_HI 0
++#define VALID0_SZ 1
++#define PEER_QOS_EN0_MSK 0x00000002
++#define PEER_QOS_EN0_I_MSK 0xfffffffd
++#define PEER_QOS_EN0_SFT 1
++#define PEER_QOS_EN0_HI 1
++#define PEER_QOS_EN0_SZ 1
++#define PEER_OP_MODE0_MSK 0x0000000c
++#define PEER_OP_MODE0_I_MSK 0xfffffff3
++#define PEER_OP_MODE0_SFT 2
++#define PEER_OP_MODE0_HI 3
++#define PEER_OP_MODE0_SZ 2
++#define PEER_HT_MODE0_MSK 0x00000030
++#define PEER_HT_MODE0_I_MSK 0xffffffcf
++#define PEER_HT_MODE0_SFT 4
++#define PEER_HT_MODE0_HI 5
++#define PEER_HT_MODE0_SZ 2
++#define PEER_MAC0_31_0_MSK 0xffffffff
++#define PEER_MAC0_31_0_I_MSK 0x00000000
++#define PEER_MAC0_31_0_SFT 0
++#define PEER_MAC0_31_0_HI 31
++#define PEER_MAC0_31_0_SZ 32
++#define PEER_MAC0_47_32_MSK 0x0000ffff
++#define PEER_MAC0_47_32_I_MSK 0xffff0000
++#define PEER_MAC0_47_32_SFT 0
++#define PEER_MAC0_47_32_HI 15
++#define PEER_MAC0_47_32_SZ 16
++#define TX_ACK_POLICY_0_0_MSK 0x00000003
++#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_0_SFT 0
++#define TX_ACK_POLICY_0_0_HI 1
++#define TX_ACK_POLICY_0_0_SZ 2
++#define TX_SEQ_CTRL_0_0_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_0_SFT 0
++#define TX_SEQ_CTRL_0_0_HI 11
++#define TX_SEQ_CTRL_0_0_SZ 12
++#define TX_ACK_POLICY_0_1_MSK 0x00000003
++#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_1_SFT 0
++#define TX_ACK_POLICY_0_1_HI 1
++#define TX_ACK_POLICY_0_1_SZ 2
++#define TX_SEQ_CTRL_0_1_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_1_SFT 0
++#define TX_SEQ_CTRL_0_1_HI 11
++#define TX_SEQ_CTRL_0_1_SZ 12
++#define TX_ACK_POLICY_0_2_MSK 0x00000003
++#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_2_SFT 0
++#define TX_ACK_POLICY_0_2_HI 1
++#define TX_ACK_POLICY_0_2_SZ 2
++#define TX_SEQ_CTRL_0_2_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_2_SFT 0
++#define TX_SEQ_CTRL_0_2_HI 11
++#define TX_SEQ_CTRL_0_2_SZ 12
++#define TX_ACK_POLICY_0_3_MSK 0x00000003
++#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_3_SFT 0
++#define TX_ACK_POLICY_0_3_HI 1
++#define TX_ACK_POLICY_0_3_SZ 2
++#define TX_SEQ_CTRL_0_3_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_3_SFT 0
++#define TX_SEQ_CTRL_0_3_HI 11
++#define TX_SEQ_CTRL_0_3_SZ 12
++#define TX_ACK_POLICY_0_4_MSK 0x00000003
++#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_4_SFT 0
++#define TX_ACK_POLICY_0_4_HI 1
++#define TX_ACK_POLICY_0_4_SZ 2
++#define TX_SEQ_CTRL_0_4_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_4_SFT 0
++#define TX_SEQ_CTRL_0_4_HI 11
++#define TX_SEQ_CTRL_0_4_SZ 12
++#define TX_ACK_POLICY_0_5_MSK 0x00000003
++#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_5_SFT 0
++#define TX_ACK_POLICY_0_5_HI 1
++#define TX_ACK_POLICY_0_5_SZ 2
++#define TX_SEQ_CTRL_0_5_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_5_SFT 0
++#define TX_SEQ_CTRL_0_5_HI 11
++#define TX_SEQ_CTRL_0_5_SZ 12
++#define TX_ACK_POLICY_0_6_MSK 0x00000003
++#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_6_SFT 0
++#define TX_ACK_POLICY_0_6_HI 1
++#define TX_ACK_POLICY_0_6_SZ 2
++#define TX_SEQ_CTRL_0_6_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_6_SFT 0
++#define TX_SEQ_CTRL_0_6_HI 11
++#define TX_SEQ_CTRL_0_6_SZ 12
++#define TX_ACK_POLICY_0_7_MSK 0x00000003
++#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_7_SFT 0
++#define TX_ACK_POLICY_0_7_HI 1
++#define TX_ACK_POLICY_0_7_SZ 2
++#define TX_SEQ_CTRL_0_7_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_7_SFT 0
++#define TX_SEQ_CTRL_0_7_HI 11
++#define TX_SEQ_CTRL_0_7_SZ 12
++#define VALID1_MSK 0x00000001
++#define VALID1_I_MSK 0xfffffffe
++#define VALID1_SFT 0
++#define VALID1_HI 0
++#define VALID1_SZ 1
++#define PEER_QOS_EN1_MSK 0x00000002
++#define PEER_QOS_EN1_I_MSK 0xfffffffd
++#define PEER_QOS_EN1_SFT 1
++#define PEER_QOS_EN1_HI 1
++#define PEER_QOS_EN1_SZ 1
++#define PEER_OP_MODE1_MSK 0x0000000c
++#define PEER_OP_MODE1_I_MSK 0xfffffff3
++#define PEER_OP_MODE1_SFT 2
++#define PEER_OP_MODE1_HI 3
++#define PEER_OP_MODE1_SZ 2
++#define PEER_HT_MODE1_MSK 0x00000030
++#define PEER_HT_MODE1_I_MSK 0xffffffcf
++#define PEER_HT_MODE1_SFT 4
++#define PEER_HT_MODE1_HI 5
++#define PEER_HT_MODE1_SZ 2
++#define PEER_MAC1_31_0_MSK 0xffffffff
++#define PEER_MAC1_31_0_I_MSK 0x00000000
++#define PEER_MAC1_31_0_SFT 0
++#define PEER_MAC1_31_0_HI 31
++#define PEER_MAC1_31_0_SZ 32
++#define PEER_MAC1_47_32_MSK 0x0000ffff
++#define PEER_MAC1_47_32_I_MSK 0xffff0000
++#define PEER_MAC1_47_32_SFT 0
++#define PEER_MAC1_47_32_HI 15
++#define PEER_MAC1_47_32_SZ 16
++#define TX_ACK_POLICY_1_0_MSK 0x00000003
++#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_0_SFT 0
++#define TX_ACK_POLICY_1_0_HI 1
++#define TX_ACK_POLICY_1_0_SZ 2
++#define TX_SEQ_CTRL_1_0_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_0_SFT 0
++#define TX_SEQ_CTRL_1_0_HI 11
++#define TX_SEQ_CTRL_1_0_SZ 12
++#define TX_ACK_POLICY_1_1_MSK 0x00000003
++#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_1_SFT 0
++#define TX_ACK_POLICY_1_1_HI 1
++#define TX_ACK_POLICY_1_1_SZ 2
++#define TX_SEQ_CTRL_1_1_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_1_SFT 0
++#define TX_SEQ_CTRL_1_1_HI 11
++#define TX_SEQ_CTRL_1_1_SZ 12
++#define TX_ACK_POLICY_1_2_MSK 0x00000003
++#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_2_SFT 0
++#define TX_ACK_POLICY_1_2_HI 1
++#define TX_ACK_POLICY_1_2_SZ 2
++#define TX_SEQ_CTRL_1_2_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_2_SFT 0
++#define TX_SEQ_CTRL_1_2_HI 11
++#define TX_SEQ_CTRL_1_2_SZ 12
++#define TX_ACK_POLICY_1_3_MSK 0x00000003
++#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_3_SFT 0
++#define TX_ACK_POLICY_1_3_HI 1
++#define TX_ACK_POLICY_1_3_SZ 2
++#define TX_SEQ_CTRL_1_3_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_3_SFT 0
++#define TX_SEQ_CTRL_1_3_HI 11
++#define TX_SEQ_CTRL_1_3_SZ 12
++#define TX_ACK_POLICY_1_4_MSK 0x00000003
++#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_4_SFT 0
++#define TX_ACK_POLICY_1_4_HI 1
++#define TX_ACK_POLICY_1_4_SZ 2
++#define TX_SEQ_CTRL_1_4_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_4_SFT 0
++#define TX_SEQ_CTRL_1_4_HI 11
++#define TX_SEQ_CTRL_1_4_SZ 12
++#define TX_ACK_POLICY_1_5_MSK 0x00000003
++#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_5_SFT 0
++#define TX_ACK_POLICY_1_5_HI 1
++#define TX_ACK_POLICY_1_5_SZ 2
++#define TX_SEQ_CTRL_1_5_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_5_SFT 0
++#define TX_SEQ_CTRL_1_5_HI 11
++#define TX_SEQ_CTRL_1_5_SZ 12
++#define TX_ACK_POLICY_1_6_MSK 0x00000003
++#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_6_SFT 0
++#define TX_ACK_POLICY_1_6_HI 1
++#define TX_ACK_POLICY_1_6_SZ 2
++#define TX_SEQ_CTRL_1_6_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_6_SFT 0
++#define TX_SEQ_CTRL_1_6_HI 11
++#define TX_SEQ_CTRL_1_6_SZ 12
++#define TX_ACK_POLICY_1_7_MSK 0x00000003
++#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_7_SFT 0
++#define TX_ACK_POLICY_1_7_HI 1
++#define TX_ACK_POLICY_1_7_SZ 2
++#define TX_SEQ_CTRL_1_7_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_7_SFT 0
++#define TX_SEQ_CTRL_1_7_HI 11
++#define TX_SEQ_CTRL_1_7_SZ 12
++#define INFO0_MSK 0xffffffff
++#define INFO0_I_MSK 0x00000000
++#define INFO0_SFT 0
++#define INFO0_HI 31
++#define INFO0_SZ 32
++#define INFO1_MSK 0xffffffff
++#define INFO1_I_MSK 0x00000000
++#define INFO1_SFT 0
++#define INFO1_HI 31
++#define INFO1_SZ 32
++#define INFO2_MSK 0xffffffff
++#define INFO2_I_MSK 0x00000000
++#define INFO2_SFT 0
++#define INFO2_HI 31
++#define INFO2_SZ 32
++#define INFO3_MSK 0xffffffff
++#define INFO3_I_MSK 0x00000000
++#define INFO3_SFT 0
++#define INFO3_HI 31
++#define INFO3_SZ 32
++#define INFO4_MSK 0xffffffff
++#define INFO4_I_MSK 0x00000000
++#define INFO4_SFT 0
++#define INFO4_HI 31
++#define INFO4_SZ 32
++#define INFO5_MSK 0xffffffff
++#define INFO5_I_MSK 0x00000000
++#define INFO5_SFT 0
++#define INFO5_HI 31
++#define INFO5_SZ 32
++#define INFO6_MSK 0xffffffff
++#define INFO6_I_MSK 0x00000000
++#define INFO6_SFT 0
++#define INFO6_HI 31
++#define INFO6_SZ 32
++#define INFO7_MSK 0xffffffff
++#define INFO7_I_MSK 0x00000000
++#define INFO7_SFT 0
++#define INFO7_HI 31
++#define INFO7_SZ 32
++#define INFO8_MSK 0xffffffff
++#define INFO8_I_MSK 0x00000000
++#define INFO8_SFT 0
++#define INFO8_HI 31
++#define INFO8_SZ 32
++#define INFO9_MSK 0xffffffff
++#define INFO9_I_MSK 0x00000000
++#define INFO9_SFT 0
++#define INFO9_HI 31
++#define INFO9_SZ 32
++#define INFO10_MSK 0xffffffff
++#define INFO10_I_MSK 0x00000000
++#define INFO10_SFT 0
++#define INFO10_HI 31
++#define INFO10_SZ 32
++#define INFO11_MSK 0xffffffff
++#define INFO11_I_MSK 0x00000000
++#define INFO11_SFT 0
++#define INFO11_HI 31
++#define INFO11_SZ 32
++#define INFO12_MSK 0xffffffff
++#define INFO12_I_MSK 0x00000000
++#define INFO12_SFT 0
++#define INFO12_HI 31
++#define INFO12_SZ 32
++#define INFO13_MSK 0xffffffff
++#define INFO13_I_MSK 0x00000000
++#define INFO13_SFT 0
++#define INFO13_HI 31
++#define INFO13_SZ 32
++#define INFO14_MSK 0xffffffff
++#define INFO14_I_MSK 0x00000000
++#define INFO14_SFT 0
++#define INFO14_HI 31
++#define INFO14_SZ 32
++#define INFO15_MSK 0xffffffff
++#define INFO15_I_MSK 0x00000000
++#define INFO15_SFT 0
++#define INFO15_HI 31
++#define INFO15_SZ 32
++#define INFO16_MSK 0xffffffff
++#define INFO16_I_MSK 0x00000000
++#define INFO16_SFT 0
++#define INFO16_HI 31
++#define INFO16_SZ 32
++#define INFO17_MSK 0xffffffff
++#define INFO17_I_MSK 0x00000000
++#define INFO17_SFT 0
++#define INFO17_HI 31
++#define INFO17_SZ 32
++#define INFO18_MSK 0xffffffff
++#define INFO18_I_MSK 0x00000000
++#define INFO18_SFT 0
++#define INFO18_HI 31
++#define INFO18_SZ 32
++#define INFO19_MSK 0xffffffff
++#define INFO19_I_MSK 0x00000000
++#define INFO19_SFT 0
++#define INFO19_HI 31
++#define INFO19_SZ 32
++#define INFO20_MSK 0xffffffff
++#define INFO20_I_MSK 0x00000000
++#define INFO20_SFT 0
++#define INFO20_HI 31
++#define INFO20_SZ 32
++#define INFO21_MSK 0xffffffff
++#define INFO21_I_MSK 0x00000000
++#define INFO21_SFT 0
++#define INFO21_HI 31
++#define INFO21_SZ 32
++#define INFO22_MSK 0xffffffff
++#define INFO22_I_MSK 0x00000000
++#define INFO22_SFT 0
++#define INFO22_HI 31
++#define INFO22_SZ 32
++#define INFO23_MSK 0xffffffff
++#define INFO23_I_MSK 0x00000000
++#define INFO23_SFT 0
++#define INFO23_HI 31
++#define INFO23_SZ 32
++#define INFO24_MSK 0xffffffff
++#define INFO24_I_MSK 0x00000000
++#define INFO24_SFT 0
++#define INFO24_HI 31
++#define INFO24_SZ 32
++#define INFO25_MSK 0xffffffff
++#define INFO25_I_MSK 0x00000000
++#define INFO25_SFT 0
++#define INFO25_HI 31
++#define INFO25_SZ 32
++#define INFO26_MSK 0xffffffff
++#define INFO26_I_MSK 0x00000000
++#define INFO26_SFT 0
++#define INFO26_HI 31
++#define INFO26_SZ 32
++#define INFO27_MSK 0xffffffff
++#define INFO27_I_MSK 0x00000000
++#define INFO27_SFT 0
++#define INFO27_HI 31
++#define INFO27_SZ 32
++#define INFO28_MSK 0xffffffff
++#define INFO28_I_MSK 0x00000000
++#define INFO28_SFT 0
++#define INFO28_HI 31
++#define INFO28_SZ 32
++#define INFO29_MSK 0xffffffff
++#define INFO29_I_MSK 0x00000000
++#define INFO29_SFT 0
++#define INFO29_HI 31
++#define INFO29_SZ 32
++#define INFO30_MSK 0xffffffff
++#define INFO30_I_MSK 0x00000000
++#define INFO30_SFT 0
++#define INFO30_HI 31
++#define INFO30_SZ 32
++#define INFO31_MSK 0xffffffff
++#define INFO31_I_MSK 0x00000000
++#define INFO31_SFT 0
++#define INFO31_HI 31
++#define INFO31_SZ 32
++#define INFO32_MSK 0xffffffff
++#define INFO32_I_MSK 0x00000000
++#define INFO32_SFT 0
++#define INFO32_HI 31
++#define INFO32_SZ 32
++#define INFO33_MSK 0xffffffff
++#define INFO33_I_MSK 0x00000000
++#define INFO33_SFT 0
++#define INFO33_HI 31
++#define INFO33_SZ 32
++#define INFO34_MSK 0xffffffff
++#define INFO34_I_MSK 0x00000000
++#define INFO34_SFT 0
++#define INFO34_HI 31
++#define INFO34_SZ 32
++#define INFO35_MSK 0xffffffff
++#define INFO35_I_MSK 0x00000000
++#define INFO35_SFT 0
++#define INFO35_HI 31
++#define INFO35_SZ 32
++#define INFO36_MSK 0xffffffff
++#define INFO36_I_MSK 0x00000000
++#define INFO36_SFT 0
++#define INFO36_HI 31
++#define INFO36_SZ 32
++#define INFO37_MSK 0xffffffff
++#define INFO37_I_MSK 0x00000000
++#define INFO37_SFT 0
++#define INFO37_HI 31
++#define INFO37_SZ 32
++#define INFO38_MSK 0xffffffff
++#define INFO38_I_MSK 0x00000000
++#define INFO38_SFT 0
++#define INFO38_HI 31
++#define INFO38_SZ 32
++#define INFO_MASK_MSK 0xffffffff
++#define INFO_MASK_I_MSK 0x00000000
++#define INFO_MASK_SFT 0
++#define INFO_MASK_HI 31
++#define INFO_MASK_SZ 32
++#define INFO_DEF_RATE_MSK 0x0000003f
++#define INFO_DEF_RATE_I_MSK 0xffffffc0
++#define INFO_DEF_RATE_SFT 0
++#define INFO_DEF_RATE_HI 5
++#define INFO_DEF_RATE_SZ 6
++#define INFO_MRX_OFFSET_MSK 0x000f0000
++#define INFO_MRX_OFFSET_I_MSK 0xfff0ffff
++#define INFO_MRX_OFFSET_SFT 16
++#define INFO_MRX_OFFSET_HI 19
++#define INFO_MRX_OFFSET_SZ 4
++#define BCAST_RATEUNKNOW_MSK 0x3f000000
++#define BCAST_RATEUNKNOW_I_MSK 0xc0ffffff
++#define BCAST_RATEUNKNOW_SFT 24
++#define BCAST_RATEUNKNOW_HI 29
++#define BCAST_RATEUNKNOW_SZ 6
++#define INFO_IDX_TBL_ADDR_MSK 0xffffffff
++#define INFO_IDX_TBL_ADDR_I_MSK 0x00000000
++#define INFO_IDX_TBL_ADDR_SFT 0
++#define INFO_IDX_TBL_ADDR_HI 31
++#define INFO_IDX_TBL_ADDR_SZ 32
++#define INFO_LEN_TBL_ADDR_MSK 0xffffffff
++#define INFO_LEN_TBL_ADDR_I_MSK 0x00000000
++#define INFO_LEN_TBL_ADDR_SFT 0
++#define INFO_LEN_TBL_ADDR_HI 31
++#define INFO_LEN_TBL_ADDR_SZ 32
++#define IC_TAG_31_0_MSK 0xffffffff
++#define IC_TAG_31_0_I_MSK 0x00000000
++#define IC_TAG_31_0_SFT 0
++#define IC_TAG_31_0_HI 31
++#define IC_TAG_31_0_SZ 32
++#define IC_TAG_63_32_MSK 0xffffffff
++#define IC_TAG_63_32_I_MSK 0x00000000
++#define IC_TAG_63_32_SFT 0
++#define IC_TAG_63_32_HI 31
++#define IC_TAG_63_32_SZ 32
++#define CH1_PRI_MSK 0x00000003
++#define CH1_PRI_I_MSK 0xfffffffc
++#define CH1_PRI_SFT 0
++#define CH1_PRI_HI 1
++#define CH1_PRI_SZ 2
++#define CH2_PRI_MSK 0x00000300
++#define CH2_PRI_I_MSK 0xfffffcff
++#define CH2_PRI_SFT 8
++#define CH2_PRI_HI 9
++#define CH2_PRI_SZ 2
++#define CH3_PRI_MSK 0x00030000
++#define CH3_PRI_I_MSK 0xfffcffff
++#define CH3_PRI_SFT 16
++#define CH3_PRI_HI 17
++#define CH3_PRI_SZ 2
++#define RG_MAC_LPBK_MSK 0x00000001
++#define RG_MAC_LPBK_I_MSK 0xfffffffe
++#define RG_MAC_LPBK_SFT 0
++#define RG_MAC_LPBK_HI 0
++#define RG_MAC_LPBK_SZ 1
++#define RG_MAC_M2M_MSK 0x00000002
++#define RG_MAC_M2M_I_MSK 0xfffffffd
++#define RG_MAC_M2M_SFT 1
++#define RG_MAC_M2M_HI 1
++#define RG_MAC_M2M_SZ 1
++#define RG_PHY_LPBK_MSK 0x00000004
++#define RG_PHY_LPBK_I_MSK 0xfffffffb
++#define RG_PHY_LPBK_SFT 2
++#define RG_PHY_LPBK_HI 2
++#define RG_PHY_LPBK_SZ 1
++#define RG_LPBK_RX_EN_MSK 0x00000008
++#define RG_LPBK_RX_EN_I_MSK 0xfffffff7
++#define RG_LPBK_RX_EN_SFT 3
++#define RG_LPBK_RX_EN_HI 3
++#define RG_LPBK_RX_EN_SZ 1
++#define EXT_MAC_MODE_MSK 0x00000010
++#define EXT_MAC_MODE_I_MSK 0xffffffef
++#define EXT_MAC_MODE_SFT 4
++#define EXT_MAC_MODE_HI 4
++#define EXT_MAC_MODE_SZ 1
++#define EXT_PHY_MODE_MSK 0x00000020
++#define EXT_PHY_MODE_I_MSK 0xffffffdf
++#define EXT_PHY_MODE_SFT 5
++#define EXT_PHY_MODE_HI 5
++#define EXT_PHY_MODE_SZ 1
++#define ASIC_TAG_MSK 0xff000000
++#define ASIC_TAG_I_MSK 0x00ffffff
++#define ASIC_TAG_SFT 24
++#define ASIC_TAG_HI 31
++#define ASIC_TAG_SZ 8
++#define HCI_SW_RST_MSK 0x00000001
++#define HCI_SW_RST_I_MSK 0xfffffffe
++#define HCI_SW_RST_SFT 0
++#define HCI_SW_RST_HI 0
++#define HCI_SW_RST_SZ 1
++#define CO_PROC_SW_RST_MSK 0x00000002
++#define CO_PROC_SW_RST_I_MSK 0xfffffffd
++#define CO_PROC_SW_RST_SFT 1
++#define CO_PROC_SW_RST_HI 1
++#define CO_PROC_SW_RST_SZ 1
++#define MTX_MISC_SW_RST_MSK 0x00000008
++#define MTX_MISC_SW_RST_I_MSK 0xfffffff7
++#define MTX_MISC_SW_RST_SFT 3
++#define MTX_MISC_SW_RST_HI 3
++#define MTX_MISC_SW_RST_SZ 1
++#define MTX_QUE_SW_RST_MSK 0x00000010
++#define MTX_QUE_SW_RST_I_MSK 0xffffffef
++#define MTX_QUE_SW_RST_SFT 4
++#define MTX_QUE_SW_RST_HI 4
++#define MTX_QUE_SW_RST_SZ 1
++#define MTX_CHST_SW_RST_MSK 0x00000020
++#define MTX_CHST_SW_RST_I_MSK 0xffffffdf
++#define MTX_CHST_SW_RST_SFT 5
++#define MTX_CHST_SW_RST_HI 5
++#define MTX_CHST_SW_RST_SZ 1
++#define MTX_BCN_SW_RST_MSK 0x00000040
++#define MTX_BCN_SW_RST_I_MSK 0xffffffbf
++#define MTX_BCN_SW_RST_SFT 6
++#define MTX_BCN_SW_RST_HI 6
++#define MTX_BCN_SW_RST_SZ 1
++#define MRX_SW_RST_MSK 0x00000080
++#define MRX_SW_RST_I_MSK 0xffffff7f
++#define MRX_SW_RST_SFT 7
++#define MRX_SW_RST_HI 7
++#define MRX_SW_RST_SZ 1
++#define AMPDU_SW_RST_MSK 0x00000100
++#define AMPDU_SW_RST_I_MSK 0xfffffeff
++#define AMPDU_SW_RST_SFT 8
++#define AMPDU_SW_RST_HI 8
++#define AMPDU_SW_RST_SZ 1
++#define MMU_SW_RST_MSK 0x00000200
++#define MMU_SW_RST_I_MSK 0xfffffdff
++#define MMU_SW_RST_SFT 9
++#define MMU_SW_RST_HI 9
++#define MMU_SW_RST_SZ 1
++#define ID_MNG_SW_RST_MSK 0x00000800
++#define ID_MNG_SW_RST_I_MSK 0xfffff7ff
++#define ID_MNG_SW_RST_SFT 11
++#define ID_MNG_SW_RST_HI 11
++#define ID_MNG_SW_RST_SZ 1
++#define MBOX_SW_RST_MSK 0x00001000
++#define MBOX_SW_RST_I_MSK 0xffffefff
++#define MBOX_SW_RST_SFT 12
++#define MBOX_SW_RST_HI 12
++#define MBOX_SW_RST_SZ 1
++#define SCRT_SW_RST_MSK 0x00002000
++#define SCRT_SW_RST_I_MSK 0xffffdfff
++#define SCRT_SW_RST_SFT 13
++#define SCRT_SW_RST_HI 13
++#define SCRT_SW_RST_SZ 1
++#define MIC_SW_RST_MSK 0x00004000
++#define MIC_SW_RST_I_MSK 0xffffbfff
++#define MIC_SW_RST_SFT 14
++#define MIC_SW_RST_HI 14
++#define MIC_SW_RST_SZ 1
++#define CO_PROC_ENG_RST_MSK 0x00000002
++#define CO_PROC_ENG_RST_I_MSK 0xfffffffd
++#define CO_PROC_ENG_RST_SFT 1
++#define CO_PROC_ENG_RST_HI 1
++#define CO_PROC_ENG_RST_SZ 1
++#define MTX_MISC_ENG_RST_MSK 0x00000008
++#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7
++#define MTX_MISC_ENG_RST_SFT 3
++#define MTX_MISC_ENG_RST_HI 3
++#define MTX_MISC_ENG_RST_SZ 1
++#define MTX_QUE_ENG_RST_MSK 0x00000010
++#define MTX_QUE_ENG_RST_I_MSK 0xffffffef
++#define MTX_QUE_ENG_RST_SFT 4
++#define MTX_QUE_ENG_RST_HI 4
++#define MTX_QUE_ENG_RST_SZ 1
++#define MTX_CHST_ENG_RST_MSK 0x00000020
++#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf
++#define MTX_CHST_ENG_RST_SFT 5
++#define MTX_CHST_ENG_RST_HI 5
++#define MTX_CHST_ENG_RST_SZ 1
++#define MTX_BCN_ENG_RST_MSK 0x00000040
++#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf
++#define MTX_BCN_ENG_RST_SFT 6
++#define MTX_BCN_ENG_RST_HI 6
++#define MTX_BCN_ENG_RST_SZ 1
++#define MRX_ENG_RST_MSK 0x00000080
++#define MRX_ENG_RST_I_MSK 0xffffff7f
++#define MRX_ENG_RST_SFT 7
++#define MRX_ENG_RST_HI 7
++#define MRX_ENG_RST_SZ 1
++#define AMPDU_ENG_RST_MSK 0x00000100
++#define AMPDU_ENG_RST_I_MSK 0xfffffeff
++#define AMPDU_ENG_RST_SFT 8
++#define AMPDU_ENG_RST_HI 8
++#define AMPDU_ENG_RST_SZ 1
++#define ID_MNG_ENG_RST_MSK 0x00004000
++#define ID_MNG_ENG_RST_I_MSK 0xffffbfff
++#define ID_MNG_ENG_RST_SFT 14
++#define ID_MNG_ENG_RST_HI 14
++#define ID_MNG_ENG_RST_SZ 1
++#define MBOX_ENG_RST_MSK 0x00008000
++#define MBOX_ENG_RST_I_MSK 0xffff7fff
++#define MBOX_ENG_RST_SFT 15
++#define MBOX_ENG_RST_HI 15
++#define MBOX_ENG_RST_SZ 1
++#define SCRT_ENG_RST_MSK 0x00010000
++#define SCRT_ENG_RST_I_MSK 0xfffeffff
++#define SCRT_ENG_RST_SFT 16
++#define SCRT_ENG_RST_HI 16
++#define SCRT_ENG_RST_SZ 1
++#define MIC_ENG_RST_MSK 0x00020000
++#define MIC_ENG_RST_I_MSK 0xfffdffff
++#define MIC_ENG_RST_SFT 17
++#define MIC_ENG_RST_HI 17
++#define MIC_ENG_RST_SZ 1
++#define CO_PROC_CSR_RST_MSK 0x00000002
++#define CO_PROC_CSR_RST_I_MSK 0xfffffffd
++#define CO_PROC_CSR_RST_SFT 1
++#define CO_PROC_CSR_RST_HI 1
++#define CO_PROC_CSR_RST_SZ 1
++#define MTX_MISC_CSR_RST_MSK 0x00000008
++#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7
++#define MTX_MISC_CSR_RST_SFT 3
++#define MTX_MISC_CSR_RST_HI 3
++#define MTX_MISC_CSR_RST_SZ 1
++#define MTX_QUE0_CSR_RST_MSK 0x00000010
++#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef
++#define MTX_QUE0_CSR_RST_SFT 4
++#define MTX_QUE0_CSR_RST_HI 4
++#define MTX_QUE0_CSR_RST_SZ 1
++#define MTX_QUE1_CSR_RST_MSK 0x00000020
++#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf
++#define MTX_QUE1_CSR_RST_SFT 5
++#define MTX_QUE1_CSR_RST_HI 5
++#define MTX_QUE1_CSR_RST_SZ 1
++#define MTX_QUE2_CSR_RST_MSK 0x00000040
++#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf
++#define MTX_QUE2_CSR_RST_SFT 6
++#define MTX_QUE2_CSR_RST_HI 6
++#define MTX_QUE2_CSR_RST_SZ 1
++#define MTX_QUE3_CSR_RST_MSK 0x00000080
++#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f
++#define MTX_QUE3_CSR_RST_SFT 7
++#define MTX_QUE3_CSR_RST_HI 7
++#define MTX_QUE3_CSR_RST_SZ 1
++#define MTX_QUE4_CSR_RST_MSK 0x00000100
++#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff
++#define MTX_QUE4_CSR_RST_SFT 8
++#define MTX_QUE4_CSR_RST_HI 8
++#define MTX_QUE4_CSR_RST_SZ 1
++#define MTX_QUE5_CSR_RST_MSK 0x00000200
++#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff
++#define MTX_QUE5_CSR_RST_SFT 9
++#define MTX_QUE5_CSR_RST_HI 9
++#define MTX_QUE5_CSR_RST_SZ 1
++#define MRX_CSR_RST_MSK 0x00000400
++#define MRX_CSR_RST_I_MSK 0xfffffbff
++#define MRX_CSR_RST_SFT 10
++#define MRX_CSR_RST_HI 10
++#define MRX_CSR_RST_SZ 1
++#define AMPDU_CSR_RST_MSK 0x00000800
++#define AMPDU_CSR_RST_I_MSK 0xfffff7ff
++#define AMPDU_CSR_RST_SFT 11
++#define AMPDU_CSR_RST_HI 11
++#define AMPDU_CSR_RST_SZ 1
++#define SCRT_CSR_RST_MSK 0x00002000
++#define SCRT_CSR_RST_I_MSK 0xffffdfff
++#define SCRT_CSR_RST_SFT 13
++#define SCRT_CSR_RST_HI 13
++#define SCRT_CSR_RST_SZ 1
++#define ID_MNG_CSR_RST_MSK 0x00004000
++#define ID_MNG_CSR_RST_I_MSK 0xffffbfff
++#define ID_MNG_CSR_RST_SFT 14
++#define ID_MNG_CSR_RST_HI 14
++#define ID_MNG_CSR_RST_SZ 1
++#define MBOX_CSR_RST_MSK 0x00008000
++#define MBOX_CSR_RST_I_MSK 0xffff7fff
++#define MBOX_CSR_RST_SFT 15
++#define MBOX_CSR_RST_HI 15
++#define MBOX_CSR_RST_SZ 1
++#define HCI_CLK_EN_MSK 0x00000001
++#define HCI_CLK_EN_I_MSK 0xfffffffe
++#define HCI_CLK_EN_SFT 0
++#define HCI_CLK_EN_HI 0
++#define HCI_CLK_EN_SZ 1
++#define CO_PROC_CLK_EN_MSK 0x00000002
++#define CO_PROC_CLK_EN_I_MSK 0xfffffffd
++#define CO_PROC_CLK_EN_SFT 1
++#define CO_PROC_CLK_EN_HI 1
++#define CO_PROC_CLK_EN_SZ 1
++#define MTX_MISC_CLK_EN_MSK 0x00000008
++#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7
++#define MTX_MISC_CLK_EN_SFT 3
++#define MTX_MISC_CLK_EN_HI 3
++#define MTX_MISC_CLK_EN_SZ 1
++#define MTX_QUE_CLK_EN_MSK 0x00000010
++#define MTX_QUE_CLK_EN_I_MSK 0xffffffef
++#define MTX_QUE_CLK_EN_SFT 4
++#define MTX_QUE_CLK_EN_HI 4
++#define MTX_QUE_CLK_EN_SZ 1
++#define MRX_CLK_EN_MSK 0x00000020
++#define MRX_CLK_EN_I_MSK 0xffffffdf
++#define MRX_CLK_EN_SFT 5
++#define MRX_CLK_EN_HI 5
++#define MRX_CLK_EN_SZ 1
++#define AMPDU_CLK_EN_MSK 0x00000040
++#define AMPDU_CLK_EN_I_MSK 0xffffffbf
++#define AMPDU_CLK_EN_SFT 6
++#define AMPDU_CLK_EN_HI 6
++#define AMPDU_CLK_EN_SZ 1
++#define MMU_CLK_EN_MSK 0x00000080
++#define MMU_CLK_EN_I_MSK 0xffffff7f
++#define MMU_CLK_EN_SFT 7
++#define MMU_CLK_EN_HI 7
++#define MMU_CLK_EN_SZ 1
++#define ID_MNG_CLK_EN_MSK 0x00000200
++#define ID_MNG_CLK_EN_I_MSK 0xfffffdff
++#define ID_MNG_CLK_EN_SFT 9
++#define ID_MNG_CLK_EN_HI 9
++#define ID_MNG_CLK_EN_SZ 1
++#define MBOX_CLK_EN_MSK 0x00000400
++#define MBOX_CLK_EN_I_MSK 0xfffffbff
++#define MBOX_CLK_EN_SFT 10
++#define MBOX_CLK_EN_HI 10
++#define MBOX_CLK_EN_SZ 1
++#define SCRT_CLK_EN_MSK 0x00000800
++#define SCRT_CLK_EN_I_MSK 0xfffff7ff
++#define SCRT_CLK_EN_SFT 11
++#define SCRT_CLK_EN_HI 11
++#define SCRT_CLK_EN_SZ 1
++#define MIC_CLK_EN_MSK 0x00001000
++#define MIC_CLK_EN_I_MSK 0xffffefff
++#define MIC_CLK_EN_SFT 12
++#define MIC_CLK_EN_HI 12
++#define MIC_CLK_EN_SZ 1
++#define MIB_CLK_EN_MSK 0x00002000
++#define MIB_CLK_EN_I_MSK 0xffffdfff
++#define MIB_CLK_EN_SFT 13
++#define MIB_CLK_EN_HI 13
++#define MIB_CLK_EN_SZ 1
++#define HCI_ENG_CLK_EN_MSK 0x00000001
++#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe
++#define HCI_ENG_CLK_EN_SFT 0
++#define HCI_ENG_CLK_EN_HI 0
++#define HCI_ENG_CLK_EN_SZ 1
++#define CO_PROC_ENG_CLK_EN_MSK 0x00000002
++#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd
++#define CO_PROC_ENG_CLK_EN_SFT 1
++#define CO_PROC_ENG_CLK_EN_HI 1
++#define CO_PROC_ENG_CLK_EN_SZ 1
++#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008
++#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7
++#define MTX_MISC_ENG_CLK_EN_SFT 3
++#define MTX_MISC_ENG_CLK_EN_HI 3
++#define MTX_MISC_ENG_CLK_EN_SZ 1
++#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010
++#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef
++#define MTX_QUE_ENG_CLK_EN_SFT 4
++#define MTX_QUE_ENG_CLK_EN_HI 4
++#define MTX_QUE_ENG_CLK_EN_SZ 1
++#define MRX_ENG_CLK_EN_MSK 0x00000020
++#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf
++#define MRX_ENG_CLK_EN_SFT 5
++#define MRX_ENG_CLK_EN_HI 5
++#define MRX_ENG_CLK_EN_SZ 1
++#define AMPDU_ENG_CLK_EN_MSK 0x00000040
++#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf
++#define AMPDU_ENG_CLK_EN_SFT 6
++#define AMPDU_ENG_CLK_EN_HI 6
++#define AMPDU_ENG_CLK_EN_SZ 1
++#define ID_MNG_ENG_CLK_EN_MSK 0x00001000
++#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff
++#define ID_MNG_ENG_CLK_EN_SFT 12
++#define ID_MNG_ENG_CLK_EN_HI 12
++#define ID_MNG_ENG_CLK_EN_SZ 1
++#define MBOX_ENG_CLK_EN_MSK 0x00002000
++#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff
++#define MBOX_ENG_CLK_EN_SFT 13
++#define MBOX_ENG_CLK_EN_HI 13
++#define MBOX_ENG_CLK_EN_SZ 1
++#define SCRT_ENG_CLK_EN_MSK 0x00004000
++#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff
++#define SCRT_ENG_CLK_EN_SFT 14
++#define SCRT_ENG_CLK_EN_HI 14
++#define SCRT_ENG_CLK_EN_SZ 1
++#define MIC_ENG_CLK_EN_MSK 0x00008000
++#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff
++#define MIC_ENG_CLK_EN_SFT 15
++#define MIC_ENG_CLK_EN_HI 15
++#define MIC_ENG_CLK_EN_SZ 1
++#define CO_PROC_CSR_CLK_EN_MSK 0x00000002
++#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd
++#define CO_PROC_CSR_CLK_EN_SFT 1
++#define CO_PROC_CSR_CLK_EN_HI 1
++#define CO_PROC_CSR_CLK_EN_SZ 1
++#define MRX_CSR_CLK_EN_MSK 0x00000400
++#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff
++#define MRX_CSR_CLK_EN_SFT 10
++#define MRX_CSR_CLK_EN_HI 10
++#define MRX_CSR_CLK_EN_SZ 1
++#define AMPDU_CSR_CLK_EN_MSK 0x00000800
++#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff
++#define AMPDU_CSR_CLK_EN_SFT 11
++#define AMPDU_CSR_CLK_EN_HI 11
++#define AMPDU_CSR_CLK_EN_SZ 1
++#define SCRT_CSR_CLK_EN_MSK 0x00002000
++#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff
++#define SCRT_CSR_CLK_EN_SFT 13
++#define SCRT_CSR_CLK_EN_HI 13
++#define SCRT_CSR_CLK_EN_SZ 1
++#define ID_MNG_CSR_CLK_EN_MSK 0x00004000
++#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff
++#define ID_MNG_CSR_CLK_EN_SFT 14
++#define ID_MNG_CSR_CLK_EN_HI 14
++#define ID_MNG_CSR_CLK_EN_SZ 1
++#define MBOX_CSR_CLK_EN_MSK 0x00008000
++#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff
++#define MBOX_CSR_CLK_EN_SFT 15
++#define MBOX_CSR_CLK_EN_HI 15
++#define MBOX_CSR_CLK_EN_SZ 1
++#define OP_MODE_MSK 0x00000003
++#define OP_MODE_I_MSK 0xfffffffc
++#define OP_MODE_SFT 0
++#define OP_MODE_HI 1
++#define OP_MODE_SZ 2
++#define HT_MODE_MSK 0x0000000c
++#define HT_MODE_I_MSK 0xfffffff3
++#define HT_MODE_SFT 2
++#define HT_MODE_HI 3
++#define HT_MODE_SZ 2
++#define QOS_EN_MSK 0x00000010
++#define QOS_EN_I_MSK 0xffffffef
++#define QOS_EN_SFT 4
++#define QOS_EN_HI 4
++#define QOS_EN_SZ 1
++#define PB_OFFSET_MSK 0x0000ff00
++#define PB_OFFSET_I_MSK 0xffff00ff
++#define PB_OFFSET_SFT 8
++#define PB_OFFSET_HI 15
++#define PB_OFFSET_SZ 8
++#define SNIFFER_MODE_MSK 0x00010000
++#define SNIFFER_MODE_I_MSK 0xfffeffff
++#define SNIFFER_MODE_SFT 16
++#define SNIFFER_MODE_HI 16
++#define SNIFFER_MODE_SZ 1
++#define DUP_FLT_MSK 0x00020000
++#define DUP_FLT_I_MSK 0xfffdffff
++#define DUP_FLT_SFT 17
++#define DUP_FLT_HI 17
++#define DUP_FLT_SZ 1
++#define TX_PKT_RSVD_MSK 0x001c0000
++#define TX_PKT_RSVD_I_MSK 0xffe3ffff
++#define TX_PKT_RSVD_SFT 18
++#define TX_PKT_RSVD_HI 20
++#define TX_PKT_RSVD_SZ 3
++#define AMPDU_SNIFFER_MSK 0x00200000
++#define AMPDU_SNIFFER_I_MSK 0xffdfffff
++#define AMPDU_SNIFFER_SFT 21
++#define AMPDU_SNIFFER_HI 21
++#define AMPDU_SNIFFER_SZ 1
++#define REASON_TRAP0_MSK 0xffffffff
++#define REASON_TRAP0_I_MSK 0x00000000
++#define REASON_TRAP0_SFT 0
++#define REASON_TRAP0_HI 31
++#define REASON_TRAP0_SZ 32
++#define REASON_TRAP1_MSK 0xffffffff
++#define REASON_TRAP1_I_MSK 0x00000000
++#define REASON_TRAP1_SFT 0
++#define REASON_TRAP1_HI 31
++#define REASON_TRAP1_SZ 32
++#define BSSID_31_0_MSK 0xffffffff
++#define BSSID_31_0_I_MSK 0x00000000
++#define BSSID_31_0_SFT 0
++#define BSSID_31_0_HI 31
++#define BSSID_31_0_SZ 32
++#define BSSID_47_32_MSK 0x0000ffff
++#define BSSID_47_32_I_MSK 0xffff0000
++#define BSSID_47_32_SFT 0
++#define BSSID_47_32_HI 15
++#define BSSID_47_32_SZ 16
++#define SCRT_STATE_MSK 0x0000000f
++#define SCRT_STATE_I_MSK 0xfffffff0
++#define SCRT_STATE_SFT 0
++#define SCRT_STATE_HI 3
++#define SCRT_STATE_SZ 4
++#define STA_MAC_31_0_MSK 0xffffffff
++#define STA_MAC_31_0_I_MSK 0x00000000
++#define STA_MAC_31_0_SFT 0
++#define STA_MAC_31_0_HI 31
++#define STA_MAC_31_0_SZ 32
++#define STA_MAC_47_32_MSK 0x0000ffff
++#define STA_MAC_47_32_I_MSK 0xffff0000
++#define STA_MAC_47_32_SFT 0
++#define STA_MAC_47_32_HI 15
++#define STA_MAC_47_32_SZ 16
++#define PAIR_SCRT_MSK 0x00000007
++#define PAIR_SCRT_I_MSK 0xfffffff8
++#define PAIR_SCRT_SFT 0
++#define PAIR_SCRT_HI 2
++#define PAIR_SCRT_SZ 3
++#define GRP_SCRT_MSK 0x00000038
++#define GRP_SCRT_I_MSK 0xffffffc7
++#define GRP_SCRT_SFT 3
++#define GRP_SCRT_HI 5
++#define GRP_SCRT_SZ 3
++#define SCRT_PKT_ID_MSK 0x00001fc0
++#define SCRT_PKT_ID_I_MSK 0xffffe03f
++#define SCRT_PKT_ID_SFT 6
++#define SCRT_PKT_ID_HI 12
++#define SCRT_PKT_ID_SZ 7
++#define SCRT_RPLY_IGNORE_MSK 0x00010000
++#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff
++#define SCRT_RPLY_IGNORE_SFT 16
++#define SCRT_RPLY_IGNORE_HI 16
++#define SCRT_RPLY_IGNORE_SZ 1
++#define COEXIST_EN_MSK 0x00000001
++#define COEXIST_EN_I_MSK 0xfffffffe
++#define COEXIST_EN_SFT 0
++#define COEXIST_EN_HI 0
++#define COEXIST_EN_SZ 1
++#define WIRE_MODE_MSK 0x0000000e
++#define WIRE_MODE_I_MSK 0xfffffff1
++#define WIRE_MODE_SFT 1
++#define WIRE_MODE_HI 3
++#define WIRE_MODE_SZ 3
++#define WL_RX_PRI_MSK 0x00000010
++#define WL_RX_PRI_I_MSK 0xffffffef
++#define WL_RX_PRI_SFT 4
++#define WL_RX_PRI_HI 4
++#define WL_RX_PRI_SZ 1
++#define WL_TX_PRI_MSK 0x00000020
++#define WL_TX_PRI_I_MSK 0xffffffdf
++#define WL_TX_PRI_SFT 5
++#define WL_TX_PRI_HI 5
++#define WL_TX_PRI_SZ 1
++#define GURAN_USE_EN_MSK 0x00000100
++#define GURAN_USE_EN_I_MSK 0xfffffeff
++#define GURAN_USE_EN_SFT 8
++#define GURAN_USE_EN_HI 8
++#define GURAN_USE_EN_SZ 1
++#define GURAN_USE_CTRL_MSK 0x00000200
++#define GURAN_USE_CTRL_I_MSK 0xfffffdff
++#define GURAN_USE_CTRL_SFT 9
++#define GURAN_USE_CTRL_HI 9
++#define GURAN_USE_CTRL_SZ 1
++#define BEACON_TIMEOUT_EN_MSK 0x00000400
++#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff
++#define BEACON_TIMEOUT_EN_SFT 10
++#define BEACON_TIMEOUT_EN_HI 10
++#define BEACON_TIMEOUT_EN_SZ 1
++#define WLAN_ACT_POL_MSK 0x00000800
++#define WLAN_ACT_POL_I_MSK 0xfffff7ff
++#define WLAN_ACT_POL_SFT 11
++#define WLAN_ACT_POL_HI 11
++#define WLAN_ACT_POL_SZ 1
++#define DUAL_ANT_EN_MSK 0x00001000
++#define DUAL_ANT_EN_I_MSK 0xffffefff
++#define DUAL_ANT_EN_SFT 12
++#define DUAL_ANT_EN_HI 12
++#define DUAL_ANT_EN_SZ 1
++#define TRSW_PHY_POL_MSK 0x00010000
++#define TRSW_PHY_POL_I_MSK 0xfffeffff
++#define TRSW_PHY_POL_SFT 16
++#define TRSW_PHY_POL_HI 16
++#define TRSW_PHY_POL_SZ 1
++#define WIFI_TX_SW_POL_MSK 0x00020000
++#define WIFI_TX_SW_POL_I_MSK 0xfffdffff
++#define WIFI_TX_SW_POL_SFT 17
++#define WIFI_TX_SW_POL_HI 17
++#define WIFI_TX_SW_POL_SZ 1
++#define WIFI_RX_SW_POL_MSK 0x00040000
++#define WIFI_RX_SW_POL_I_MSK 0xfffbffff
++#define WIFI_RX_SW_POL_SFT 18
++#define WIFI_RX_SW_POL_HI 18
++#define WIFI_RX_SW_POL_SZ 1
++#define BT_SW_POL_MSK 0x00080000
++#define BT_SW_POL_I_MSK 0xfff7ffff
++#define BT_SW_POL_SFT 19
++#define BT_SW_POL_HI 19
++#define BT_SW_POL_SZ 1
++#define BT_PRI_SMP_TIME_MSK 0x000000ff
++#define BT_PRI_SMP_TIME_I_MSK 0xffffff00
++#define BT_PRI_SMP_TIME_SFT 0
++#define BT_PRI_SMP_TIME_HI 7
++#define BT_PRI_SMP_TIME_SZ 8
++#define BT_STA_SMP_TIME_MSK 0x0000ff00
++#define BT_STA_SMP_TIME_I_MSK 0xffff00ff
++#define BT_STA_SMP_TIME_SFT 8
++#define BT_STA_SMP_TIME_HI 15
++#define BT_STA_SMP_TIME_SZ 8
++#define BEACON_TIMEOUT_MSK 0x00ff0000
++#define BEACON_TIMEOUT_I_MSK 0xff00ffff
++#define BEACON_TIMEOUT_SFT 16
++#define BEACON_TIMEOUT_HI 23
++#define BEACON_TIMEOUT_SZ 8
++#define WLAN_REMAIN_TIME_MSK 0xff000000
++#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff
++#define WLAN_REMAIN_TIME_SFT 24
++#define WLAN_REMAIN_TIME_HI 31
++#define WLAN_REMAIN_TIME_SZ 8
++#define SW_MANUAL_EN_MSK 0x00000001
++#define SW_MANUAL_EN_I_MSK 0xfffffffe
++#define SW_MANUAL_EN_SFT 0
++#define SW_MANUAL_EN_HI 0
++#define SW_MANUAL_EN_SZ 1
++#define SW_WL_TX_MSK 0x00000002
++#define SW_WL_TX_I_MSK 0xfffffffd
++#define SW_WL_TX_SFT 1
++#define SW_WL_TX_HI 1
++#define SW_WL_TX_SZ 1
++#define SW_WL_RX_MSK 0x00000004
++#define SW_WL_RX_I_MSK 0xfffffffb
++#define SW_WL_RX_SFT 2
++#define SW_WL_RX_HI 2
++#define SW_WL_RX_SZ 1
++#define SW_BT_TRX_MSK 0x00000008
++#define SW_BT_TRX_I_MSK 0xfffffff7
++#define SW_BT_TRX_SFT 3
++#define SW_BT_TRX_HI 3
++#define SW_BT_TRX_SZ 1
++#define BT_TXBAR_MANUAL_EN_MSK 0x00000010
++#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef
++#define BT_TXBAR_MANUAL_EN_SFT 4
++#define BT_TXBAR_MANUAL_EN_HI 4
++#define BT_TXBAR_MANUAL_EN_SZ 1
++#define BT_TXBAR_SET_MSK 0x00000020
++#define BT_TXBAR_SET_I_MSK 0xffffffdf
++#define BT_TXBAR_SET_SFT 5
++#define BT_TXBAR_SET_HI 5
++#define BT_TXBAR_SET_SZ 1
++#define BT_BUSY_MANUAL_EN_MSK 0x00000100
++#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff
++#define BT_BUSY_MANUAL_EN_SFT 8
++#define BT_BUSY_MANUAL_EN_HI 8
++#define BT_BUSY_MANUAL_EN_SZ 1
++#define BT_BUSY_SET_MSK 0x00000200
++#define BT_BUSY_SET_I_MSK 0xfffffdff
++#define BT_BUSY_SET_SFT 9
++#define BT_BUSY_SET_HI 9
++#define BT_BUSY_SET_SZ 1
++#define G0_PKT_CLS_MIB_EN_MSK 0x00000004
++#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb
++#define G0_PKT_CLS_MIB_EN_SFT 2
++#define G0_PKT_CLS_MIB_EN_HI 2
++#define G0_PKT_CLS_MIB_EN_SZ 1
++#define G0_PKT_CLS_ONGOING_MSK 0x00000008
++#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7
++#define G0_PKT_CLS_ONGOING_SFT 3
++#define G0_PKT_CLS_ONGOING_HI 3
++#define G0_PKT_CLS_ONGOING_SZ 1
++#define G1_PKT_CLS_MIB_EN_MSK 0x00000010
++#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef
++#define G1_PKT_CLS_MIB_EN_SFT 4
++#define G1_PKT_CLS_MIB_EN_HI 4
++#define G1_PKT_CLS_MIB_EN_SZ 1
++#define G1_PKT_CLS_ONGOING_MSK 0x00000020
++#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf
++#define G1_PKT_CLS_ONGOING_SFT 5
++#define G1_PKT_CLS_ONGOING_HI 5
++#define G1_PKT_CLS_ONGOING_SZ 1
++#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040
++#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf
++#define Q0_PKT_CLS_MIB_EN_SFT 6
++#define Q0_PKT_CLS_MIB_EN_HI 6
++#define Q0_PKT_CLS_MIB_EN_SZ 1
++#define Q0_PKT_CLS_ONGOING_MSK 0x00000080
++#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f
++#define Q0_PKT_CLS_ONGOING_SFT 7
++#define Q0_PKT_CLS_ONGOING_HI 7
++#define Q0_PKT_CLS_ONGOING_SZ 1
++#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100
++#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff
++#define Q1_PKT_CLS_MIB_EN_SFT 8
++#define Q1_PKT_CLS_MIB_EN_HI 8
++#define Q1_PKT_CLS_MIB_EN_SZ 1
++#define Q1_PKT_CLS_ONGOING_MSK 0x00000200
++#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff
++#define Q1_PKT_CLS_ONGOING_SFT 9
++#define Q1_PKT_CLS_ONGOING_HI 9
++#define Q1_PKT_CLS_ONGOING_SZ 1
++#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400
++#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff
++#define Q2_PKT_CLS_MIB_EN_SFT 10
++#define Q2_PKT_CLS_MIB_EN_HI 10
++#define Q2_PKT_CLS_MIB_EN_SZ 1
++#define Q2_PKT_CLS_ONGOING_MSK 0x00000800
++#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff
++#define Q2_PKT_CLS_ONGOING_SFT 11
++#define Q2_PKT_CLS_ONGOING_HI 11
++#define Q2_PKT_CLS_ONGOING_SZ 1
++#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000
++#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff
++#define Q3_PKT_CLS_MIB_EN_SFT 12
++#define Q3_PKT_CLS_MIB_EN_HI 12
++#define Q3_PKT_CLS_MIB_EN_SZ 1
++#define Q3_PKT_CLS_ONGOING_MSK 0x00002000
++#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff
++#define Q3_PKT_CLS_ONGOING_SFT 13
++#define Q3_PKT_CLS_ONGOING_HI 13
++#define Q3_PKT_CLS_ONGOING_SZ 1
++#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000
++#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff
++#define SCRT_PKT_CLS_MIB_EN_SFT 14
++#define SCRT_PKT_CLS_MIB_EN_HI 14
++#define SCRT_PKT_CLS_MIB_EN_SZ 1
++#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000
++#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff
++#define SCRT_PKT_CLS_ONGOING_SFT 15
++#define SCRT_PKT_CLS_ONGOING_HI 15
++#define SCRT_PKT_CLS_ONGOING_SZ 1
++#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000
++#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff
++#define MISC_PKT_CLS_MIB_EN_SFT 16
++#define MISC_PKT_CLS_MIB_EN_HI 16
++#define MISC_PKT_CLS_MIB_EN_SZ 1
++#define MISC_PKT_CLS_ONGOING_MSK 0x00020000
++#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff
++#define MISC_PKT_CLS_ONGOING_SFT 17
++#define MISC_PKT_CLS_ONGOING_HI 17
++#define MISC_PKT_CLS_ONGOING_SZ 1
++#define MTX_WSID0_SUCC_MSK 0x0000ffff
++#define MTX_WSID0_SUCC_I_MSK 0xffff0000
++#define MTX_WSID0_SUCC_SFT 0
++#define MTX_WSID0_SUCC_HI 15
++#define MTX_WSID0_SUCC_SZ 16
++#define MTX_WSID0_FRM_MSK 0x0000ffff
++#define MTX_WSID0_FRM_I_MSK 0xffff0000
++#define MTX_WSID0_FRM_SFT 0
++#define MTX_WSID0_FRM_HI 15
++#define MTX_WSID0_FRM_SZ 16
++#define MTX_WSID0_RETRY_MSK 0x0000ffff
++#define MTX_WSID0_RETRY_I_MSK 0xffff0000
++#define MTX_WSID0_RETRY_SFT 0
++#define MTX_WSID0_RETRY_HI 15
++#define MTX_WSID0_RETRY_SZ 16
++#define MTX_WSID0_TOTAL_MSK 0x0000ffff
++#define MTX_WSID0_TOTAL_I_MSK 0xffff0000
++#define MTX_WSID0_TOTAL_SFT 0
++#define MTX_WSID0_TOTAL_HI 15
++#define MTX_WSID0_TOTAL_SZ 16
++#define MTX_GRP_MSK 0x000fffff
++#define MTX_GRP_I_MSK 0xfff00000
++#define MTX_GRP_SFT 0
++#define MTX_GRP_HI 19
++#define MTX_GRP_SZ 20
++#define MTX_FAIL_MSK 0x0000ffff
++#define MTX_FAIL_I_MSK 0xffff0000
++#define MTX_FAIL_SFT 0
++#define MTX_FAIL_HI 15
++#define MTX_FAIL_SZ 16
++#define MTX_RETRY_MSK 0x000fffff
++#define MTX_RETRY_I_MSK 0xfff00000
++#define MTX_RETRY_SFT 0
++#define MTX_RETRY_HI 19
++#define MTX_RETRY_SZ 20
++#define MTX_MULTI_RETRY_MSK 0x000fffff
++#define MTX_MULTI_RETRY_I_MSK 0xfff00000
++#define MTX_MULTI_RETRY_SFT 0
++#define MTX_MULTI_RETRY_HI 19
++#define MTX_MULTI_RETRY_SZ 20
++#define MTX_RTS_SUCC_MSK 0x0000ffff
++#define MTX_RTS_SUCC_I_MSK 0xffff0000
++#define MTX_RTS_SUCC_SFT 0
++#define MTX_RTS_SUCC_HI 15
++#define MTX_RTS_SUCC_SZ 16
++#define MTX_RTS_FAIL_MSK 0x0000ffff
++#define MTX_RTS_FAIL_I_MSK 0xffff0000
++#define MTX_RTS_FAIL_SFT 0
++#define MTX_RTS_FAIL_HI 15
++#define MTX_RTS_FAIL_SZ 16
++#define MTX_ACK_FAIL_MSK 0x0000ffff
++#define MTX_ACK_FAIL_I_MSK 0xffff0000
++#define MTX_ACK_FAIL_SFT 0
++#define MTX_ACK_FAIL_HI 15
++#define MTX_ACK_FAIL_SZ 16
++#define MTX_FRM_MSK 0x000fffff
++#define MTX_FRM_I_MSK 0xfff00000
++#define MTX_FRM_SFT 0
++#define MTX_FRM_HI 19
++#define MTX_FRM_SZ 20
++#define MTX_ACK_TX_MSK 0x0000ffff
++#define MTX_ACK_TX_I_MSK 0xffff0000
++#define MTX_ACK_TX_SFT 0
++#define MTX_ACK_TX_HI 15
++#define MTX_ACK_TX_SZ 16
++#define MTX_CTS_TX_MSK 0x0000ffff
++#define MTX_CTS_TX_I_MSK 0xffff0000
++#define MTX_CTS_TX_SFT 0
++#define MTX_CTS_TX_HI 15
++#define MTX_CTS_TX_SZ 16
++#define MRX_DUP_MSK 0x0000ffff
++#define MRX_DUP_I_MSK 0xffff0000
++#define MRX_DUP_SFT 0
++#define MRX_DUP_HI 15
++#define MRX_DUP_SZ 16
++#define MRX_FRG_MSK 0x000fffff
++#define MRX_FRG_I_MSK 0xfff00000
++#define MRX_FRG_SFT 0
++#define MRX_FRG_HI 19
++#define MRX_FRG_SZ 20
++#define MRX_GRP_MSK 0x000fffff
++#define MRX_GRP_I_MSK 0xfff00000
++#define MRX_GRP_SFT 0
++#define MRX_GRP_HI 19
++#define MRX_GRP_SZ 20
++#define MRX_FCS_ERR_MSK 0x0000ffff
++#define MRX_FCS_ERR_I_MSK 0xffff0000
++#define MRX_FCS_ERR_SFT 0
++#define MRX_FCS_ERR_HI 15
++#define MRX_FCS_ERR_SZ 16
++#define MRX_FCS_SUC_MSK 0x0000ffff
++#define MRX_FCS_SUC_I_MSK 0xffff0000
++#define MRX_FCS_SUC_SFT 0
++#define MRX_FCS_SUC_HI 15
++#define MRX_FCS_SUC_SZ 16
++#define MRX_MISS_MSK 0x0000ffff
++#define MRX_MISS_I_MSK 0xffff0000
++#define MRX_MISS_SFT 0
++#define MRX_MISS_HI 15
++#define MRX_MISS_SZ 16
++#define MRX_ALC_FAIL_MSK 0x0000ffff
++#define MRX_ALC_FAIL_I_MSK 0xffff0000
++#define MRX_ALC_FAIL_SFT 0
++#define MRX_ALC_FAIL_HI 15
++#define MRX_ALC_FAIL_SZ 16
++#define MRX_DAT_NTF_MSK 0x0000ffff
++#define MRX_DAT_NTF_I_MSK 0xffff0000
++#define MRX_DAT_NTF_SFT 0
++#define MRX_DAT_NTF_HI 15
++#define MRX_DAT_NTF_SZ 16
++#define MRX_RTS_NTF_MSK 0x0000ffff
++#define MRX_RTS_NTF_I_MSK 0xffff0000
++#define MRX_RTS_NTF_SFT 0
++#define MRX_RTS_NTF_HI 15
++#define MRX_RTS_NTF_SZ 16
++#define MRX_CTS_NTF_MSK 0x0000ffff
++#define MRX_CTS_NTF_I_MSK 0xffff0000
++#define MRX_CTS_NTF_SFT 0
++#define MRX_CTS_NTF_HI 15
++#define MRX_CTS_NTF_SZ 16
++#define MRX_ACK_NTF_MSK 0x0000ffff
++#define MRX_ACK_NTF_I_MSK 0xffff0000
++#define MRX_ACK_NTF_SFT 0
++#define MRX_ACK_NTF_HI 15
++#define MRX_ACK_NTF_SZ 16
++#define MRX_BA_NTF_MSK 0x0000ffff
++#define MRX_BA_NTF_I_MSK 0xffff0000
++#define MRX_BA_NTF_SFT 0
++#define MRX_BA_NTF_HI 15
++#define MRX_BA_NTF_SZ 16
++#define MRX_DATA_NTF_MSK 0x0000ffff
++#define MRX_DATA_NTF_I_MSK 0xffff0000
++#define MRX_DATA_NTF_SFT 0
++#define MRX_DATA_NTF_HI 15
++#define MRX_DATA_NTF_SZ 16
++#define MRX_MNG_NTF_MSK 0x0000ffff
++#define MRX_MNG_NTF_I_MSK 0xffff0000
++#define MRX_MNG_NTF_SFT 0
++#define MRX_MNG_NTF_HI 15
++#define MRX_MNG_NTF_SZ 16
++#define MRX_DAT_CRC_NTF_MSK 0x0000ffff
++#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000
++#define MRX_DAT_CRC_NTF_SFT 0
++#define MRX_DAT_CRC_NTF_HI 15
++#define MRX_DAT_CRC_NTF_SZ 16
++#define MRX_BAR_NTF_MSK 0x0000ffff
++#define MRX_BAR_NTF_I_MSK 0xffff0000
++#define MRX_BAR_NTF_SFT 0
++#define MRX_BAR_NTF_HI 15
++#define MRX_BAR_NTF_SZ 16
++#define MRX_MB_MISS_MSK 0x0000ffff
++#define MRX_MB_MISS_I_MSK 0xffff0000
++#define MRX_MB_MISS_SFT 0
++#define MRX_MB_MISS_HI 15
++#define MRX_MB_MISS_SZ 16
++#define MRX_NIDLE_MISS_MSK 0x0000ffff
++#define MRX_NIDLE_MISS_I_MSK 0xffff0000
++#define MRX_NIDLE_MISS_SFT 0
++#define MRX_NIDLE_MISS_HI 15
++#define MRX_NIDLE_MISS_SZ 16
++#define MRX_CSR_NTF_MSK 0x0000ffff
++#define MRX_CSR_NTF_I_MSK 0xffff0000
++#define MRX_CSR_NTF_SFT 0
++#define MRX_CSR_NTF_HI 15
++#define MRX_CSR_NTF_SZ 16
++#define DBG_Q0_SUCC_MSK 0x0000ffff
++#define DBG_Q0_SUCC_I_MSK 0xffff0000
++#define DBG_Q0_SUCC_SFT 0
++#define DBG_Q0_SUCC_HI 15
++#define DBG_Q0_SUCC_SZ 16
++#define DBG_Q0_FAIL_MSK 0x0000ffff
++#define DBG_Q0_FAIL_I_MSK 0xffff0000
++#define DBG_Q0_FAIL_SFT 0
++#define DBG_Q0_FAIL_HI 15
++#define DBG_Q0_FAIL_SZ 16
++#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q0_ACK_SUCC_SFT 0
++#define DBG_Q0_ACK_SUCC_HI 15
++#define DBG_Q0_ACK_SUCC_SZ 16
++#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q0_ACK_FAIL_SFT 0
++#define DBG_Q0_ACK_FAIL_HI 15
++#define DBG_Q0_ACK_FAIL_SZ 16
++#define DBG_Q1_SUCC_MSK 0x0000ffff
++#define DBG_Q1_SUCC_I_MSK 0xffff0000
++#define DBG_Q1_SUCC_SFT 0
++#define DBG_Q1_SUCC_HI 15
++#define DBG_Q1_SUCC_SZ 16
++#define DBG_Q1_FAIL_MSK 0x0000ffff
++#define DBG_Q1_FAIL_I_MSK 0xffff0000
++#define DBG_Q1_FAIL_SFT 0
++#define DBG_Q1_FAIL_HI 15
++#define DBG_Q1_FAIL_SZ 16
++#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q1_ACK_SUCC_SFT 0
++#define DBG_Q1_ACK_SUCC_HI 15
++#define DBG_Q1_ACK_SUCC_SZ 16
++#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q1_ACK_FAIL_SFT 0
++#define DBG_Q1_ACK_FAIL_HI 15
++#define DBG_Q1_ACK_FAIL_SZ 16
++#define DBG_Q2_SUCC_MSK 0x0000ffff
++#define DBG_Q2_SUCC_I_MSK 0xffff0000
++#define DBG_Q2_SUCC_SFT 0
++#define DBG_Q2_SUCC_HI 15
++#define DBG_Q2_SUCC_SZ 16
++#define DBG_Q2_FAIL_MSK 0x0000ffff
++#define DBG_Q2_FAIL_I_MSK 0xffff0000
++#define DBG_Q2_FAIL_SFT 0
++#define DBG_Q2_FAIL_HI 15
++#define DBG_Q2_FAIL_SZ 16
++#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q2_ACK_SUCC_SFT 0
++#define DBG_Q2_ACK_SUCC_HI 15
++#define DBG_Q2_ACK_SUCC_SZ 16
++#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q2_ACK_FAIL_SFT 0
++#define DBG_Q2_ACK_FAIL_HI 15
++#define DBG_Q2_ACK_FAIL_SZ 16
++#define DBG_Q3_SUCC_MSK 0x0000ffff
++#define DBG_Q3_SUCC_I_MSK 0xffff0000
++#define DBG_Q3_SUCC_SFT 0
++#define DBG_Q3_SUCC_HI 15
++#define DBG_Q3_SUCC_SZ 16
++#define DBG_Q3_FAIL_MSK 0x0000ffff
++#define DBG_Q3_FAIL_I_MSK 0xffff0000
++#define DBG_Q3_FAIL_SFT 0
++#define DBG_Q3_FAIL_HI 15
++#define DBG_Q3_FAIL_SZ 16
++#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q3_ACK_SUCC_SFT 0
++#define DBG_Q3_ACK_SUCC_HI 15
++#define DBG_Q3_ACK_SUCC_SZ 16
++#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q3_ACK_FAIL_SFT 0
++#define DBG_Q3_ACK_FAIL_HI 15
++#define DBG_Q3_ACK_FAIL_SZ 16
++#define SCRT_TKIP_CERR_MSK 0x000fffff
++#define SCRT_TKIP_CERR_I_MSK 0xfff00000
++#define SCRT_TKIP_CERR_SFT 0
++#define SCRT_TKIP_CERR_HI 19
++#define SCRT_TKIP_CERR_SZ 20
++#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff
++#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000
++#define SCRT_TKIP_MIC_ERR_SFT 0
++#define SCRT_TKIP_MIC_ERR_HI 19
++#define SCRT_TKIP_MIC_ERR_SZ 20
++#define SCRT_TKIP_RPLY_MSK 0x000fffff
++#define SCRT_TKIP_RPLY_I_MSK 0xfff00000
++#define SCRT_TKIP_RPLY_SFT 0
++#define SCRT_TKIP_RPLY_HI 19
++#define SCRT_TKIP_RPLY_SZ 20
++#define SCRT_CCMP_RPLY_MSK 0x000fffff
++#define SCRT_CCMP_RPLY_I_MSK 0xfff00000
++#define SCRT_CCMP_RPLY_SFT 0
++#define SCRT_CCMP_RPLY_HI 19
++#define SCRT_CCMP_RPLY_SZ 20
++#define SCRT_CCMP_CERR_MSK 0x000fffff
++#define SCRT_CCMP_CERR_I_MSK 0xfff00000
++#define SCRT_CCMP_CERR_SFT 0
++#define SCRT_CCMP_CERR_HI 19
++#define SCRT_CCMP_CERR_SZ 20
++#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff
++#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000
++#define DBG_LEN_CRC_FAIL_SFT 0
++#define DBG_LEN_CRC_FAIL_HI 15
++#define DBG_LEN_CRC_FAIL_SZ 16
++#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff
++#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000
++#define DBG_LEN_ALC_FAIL_SFT 0
++#define DBG_LEN_ALC_FAIL_HI 15
++#define DBG_LEN_ALC_FAIL_SZ 16
++#define DBG_AMPDU_PASS_MSK 0x0000ffff
++#define DBG_AMPDU_PASS_I_MSK 0xffff0000
++#define DBG_AMPDU_PASS_SFT 0
++#define DBG_AMPDU_PASS_HI 15
++#define DBG_AMPDU_PASS_SZ 16
++#define DBG_AMPDU_FAIL_MSK 0x0000ffff
++#define DBG_AMPDU_FAIL_I_MSK 0xffff0000
++#define DBG_AMPDU_FAIL_SFT 0
++#define DBG_AMPDU_FAIL_HI 15
++#define DBG_AMPDU_FAIL_SZ 16
++#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff
++#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000
++#define RXID_ALC_CNT_FAIL_SFT 0
++#define RXID_ALC_CNT_FAIL_HI 15
++#define RXID_ALC_CNT_FAIL_SZ 16
++#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff
++#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000
++#define RXID_ALC_LEN_FAIL_SFT 0
++#define RXID_ALC_LEN_FAIL_HI 15
++#define RXID_ALC_LEN_FAIL_SZ 16
++#define CBR_RG_EN_MANUAL_MSK 0x00000001
++#define CBR_RG_EN_MANUAL_I_MSK 0xfffffffe
++#define CBR_RG_EN_MANUAL_SFT 0
++#define CBR_RG_EN_MANUAL_HI 0
++#define CBR_RG_EN_MANUAL_SZ 1
++#define CBR_RG_TX_EN_MSK 0x00000002
++#define CBR_RG_TX_EN_I_MSK 0xfffffffd
++#define CBR_RG_TX_EN_SFT 1
++#define CBR_RG_TX_EN_HI 1
++#define CBR_RG_TX_EN_SZ 1
++#define CBR_RG_TX_PA_EN_MSK 0x00000004
++#define CBR_RG_TX_PA_EN_I_MSK 0xfffffffb
++#define CBR_RG_TX_PA_EN_SFT 2
++#define CBR_RG_TX_PA_EN_HI 2
++#define CBR_RG_TX_PA_EN_SZ 1
++#define CBR_RG_TX_DAC_EN_MSK 0x00000008
++#define CBR_RG_TX_DAC_EN_I_MSK 0xfffffff7
++#define CBR_RG_TX_DAC_EN_SFT 3
++#define CBR_RG_TX_DAC_EN_HI 3
++#define CBR_RG_TX_DAC_EN_SZ 1
++#define CBR_RG_RX_AGC_MSK 0x00000010
++#define CBR_RG_RX_AGC_I_MSK 0xffffffef
++#define CBR_RG_RX_AGC_SFT 4
++#define CBR_RG_RX_AGC_HI 4
++#define CBR_RG_RX_AGC_SZ 1
++#define CBR_RG_RX_GAIN_MANUAL_MSK 0x00000020
++#define CBR_RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
++#define CBR_RG_RX_GAIN_MANUAL_SFT 5
++#define CBR_RG_RX_GAIN_MANUAL_HI 5
++#define CBR_RG_RX_GAIN_MANUAL_SZ 1
++#define CBR_RG_RFG_MSK 0x000000c0
++#define CBR_RG_RFG_I_MSK 0xffffff3f
++#define CBR_RG_RFG_SFT 6
++#define CBR_RG_RFG_HI 7
++#define CBR_RG_RFG_SZ 2
++#define CBR_RG_PGAG_MSK 0x00000f00
++#define CBR_RG_PGAG_I_MSK 0xfffff0ff
++#define CBR_RG_PGAG_SFT 8
++#define CBR_RG_PGAG_HI 11
++#define CBR_RG_PGAG_SZ 4
++#define CBR_RG_MODE_MSK 0x00003000
++#define CBR_RG_MODE_I_MSK 0xffffcfff
++#define CBR_RG_MODE_SFT 12
++#define CBR_RG_MODE_HI 13
++#define CBR_RG_MODE_SZ 2
++#define CBR_RG_EN_TX_TRSW_MSK 0x00004000
++#define CBR_RG_EN_TX_TRSW_I_MSK 0xffffbfff
++#define CBR_RG_EN_TX_TRSW_SFT 14
++#define CBR_RG_EN_TX_TRSW_HI 14
++#define CBR_RG_EN_TX_TRSW_SZ 1
++#define CBR_RG_EN_SX_MSK 0x00008000
++#define CBR_RG_EN_SX_I_MSK 0xffff7fff
++#define CBR_RG_EN_SX_SFT 15
++#define CBR_RG_EN_SX_HI 15
++#define CBR_RG_EN_SX_SZ 1
++#define CBR_RG_EN_RX_LNA_MSK 0x00010000
++#define CBR_RG_EN_RX_LNA_I_MSK 0xfffeffff
++#define CBR_RG_EN_RX_LNA_SFT 16
++#define CBR_RG_EN_RX_LNA_HI 16
++#define CBR_RG_EN_RX_LNA_SZ 1
++#define CBR_RG_EN_RX_MIXER_MSK 0x00020000
++#define CBR_RG_EN_RX_MIXER_I_MSK 0xfffdffff
++#define CBR_RG_EN_RX_MIXER_SFT 17
++#define CBR_RG_EN_RX_MIXER_HI 17
++#define CBR_RG_EN_RX_MIXER_SZ 1
++#define CBR_RG_EN_RX_DIV2_MSK 0x00040000
++#define CBR_RG_EN_RX_DIV2_I_MSK 0xfffbffff
++#define CBR_RG_EN_RX_DIV2_SFT 18
++#define CBR_RG_EN_RX_DIV2_HI 18
++#define CBR_RG_EN_RX_DIV2_SZ 1
++#define CBR_RG_EN_RX_LOBUF_MSK 0x00080000
++#define CBR_RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
++#define CBR_RG_EN_RX_LOBUF_SFT 19
++#define CBR_RG_EN_RX_LOBUF_HI 19
++#define CBR_RG_EN_RX_LOBUF_SZ 1
++#define CBR_RG_EN_RX_TZ_MSK 0x00100000
++#define CBR_RG_EN_RX_TZ_I_MSK 0xffefffff
++#define CBR_RG_EN_RX_TZ_SFT 20
++#define CBR_RG_EN_RX_TZ_HI 20
++#define CBR_RG_EN_RX_TZ_SZ 1
++#define CBR_RG_EN_RX_FILTER_MSK 0x00200000
++#define CBR_RG_EN_RX_FILTER_I_MSK 0xffdfffff
++#define CBR_RG_EN_RX_FILTER_SFT 21
++#define CBR_RG_EN_RX_FILTER_HI 21
++#define CBR_RG_EN_RX_FILTER_SZ 1
++#define CBR_RG_EN_RX_HPF_MSK 0x00400000
++#define CBR_RG_EN_RX_HPF_I_MSK 0xffbfffff
++#define CBR_RG_EN_RX_HPF_SFT 22
++#define CBR_RG_EN_RX_HPF_HI 22
++#define CBR_RG_EN_RX_HPF_SZ 1
++#define CBR_RG_EN_RX_RSSI_MSK 0x00800000
++#define CBR_RG_EN_RX_RSSI_I_MSK 0xff7fffff
++#define CBR_RG_EN_RX_RSSI_SFT 23
++#define CBR_RG_EN_RX_RSSI_HI 23
++#define CBR_RG_EN_RX_RSSI_SZ 1
++#define CBR_RG_EN_ADC_MSK 0x01000000
++#define CBR_RG_EN_ADC_I_MSK 0xfeffffff
++#define CBR_RG_EN_ADC_SFT 24
++#define CBR_RG_EN_ADC_HI 24
++#define CBR_RG_EN_ADC_SZ 1
++#define CBR_RG_EN_TX_MOD_MSK 0x02000000
++#define CBR_RG_EN_TX_MOD_I_MSK 0xfdffffff
++#define CBR_RG_EN_TX_MOD_SFT 25
++#define CBR_RG_EN_TX_MOD_HI 25
++#define CBR_RG_EN_TX_MOD_SZ 1
++#define CBR_RG_EN_TX_DIV2_MSK 0x04000000
++#define CBR_RG_EN_TX_DIV2_I_MSK 0xfbffffff
++#define CBR_RG_EN_TX_DIV2_SFT 26
++#define CBR_RG_EN_TX_DIV2_HI 26
++#define CBR_RG_EN_TX_DIV2_SZ 1
++#define CBR_RG_EN_TX_DIV2_BUF_MSK 0x08000000
++#define CBR_RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
++#define CBR_RG_EN_TX_DIV2_BUF_SFT 27
++#define CBR_RG_EN_TX_DIV2_BUF_HI 27
++#define CBR_RG_EN_TX_DIV2_BUF_SZ 1
++#define CBR_RG_EN_TX_LOBF_MSK 0x10000000
++#define CBR_RG_EN_TX_LOBF_I_MSK 0xefffffff
++#define CBR_RG_EN_TX_LOBF_SFT 28
++#define CBR_RG_EN_TX_LOBF_HI 28
++#define CBR_RG_EN_TX_LOBF_SZ 1
++#define CBR_RG_EN_RX_LOBF_MSK 0x20000000
++#define CBR_RG_EN_RX_LOBF_I_MSK 0xdfffffff
++#define CBR_RG_EN_RX_LOBF_SFT 29
++#define CBR_RG_EN_RX_LOBF_HI 29
++#define CBR_RG_EN_RX_LOBF_SZ 1
++#define CBR_RG_SEL_DPLL_CLK_MSK 0x40000000
++#define CBR_RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
++#define CBR_RG_SEL_DPLL_CLK_SFT 30
++#define CBR_RG_SEL_DPLL_CLK_HI 30
++#define CBR_RG_SEL_DPLL_CLK_SZ 1
++#define CBR_RG_EN_TX_DPD_MSK 0x00000001
++#define CBR_RG_EN_TX_DPD_I_MSK 0xfffffffe
++#define CBR_RG_EN_TX_DPD_SFT 0
++#define CBR_RG_EN_TX_DPD_HI 0
++#define CBR_RG_EN_TX_DPD_SZ 1
++#define CBR_RG_EN_TX_TSSI_MSK 0x00000002
++#define CBR_RG_EN_TX_TSSI_I_MSK 0xfffffffd
++#define CBR_RG_EN_TX_TSSI_SFT 1
++#define CBR_RG_EN_TX_TSSI_HI 1
++#define CBR_RG_EN_TX_TSSI_SZ 1
++#define CBR_RG_EN_RX_IQCAL_MSK 0x00000004
++#define CBR_RG_EN_RX_IQCAL_I_MSK 0xfffffffb
++#define CBR_RG_EN_RX_IQCAL_SFT 2
++#define CBR_RG_EN_RX_IQCAL_HI 2
++#define CBR_RG_EN_RX_IQCAL_SZ 1
++#define CBR_RG_EN_TX_DAC_CAL_MSK 0x00000008
++#define CBR_RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
++#define CBR_RG_EN_TX_DAC_CAL_SFT 3
++#define CBR_RG_EN_TX_DAC_CAL_HI 3
++#define CBR_RG_EN_TX_DAC_CAL_SZ 1
++#define CBR_RG_EN_TX_SELF_MIXER_MSK 0x00000010
++#define CBR_RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
++#define CBR_RG_EN_TX_SELF_MIXER_SFT 4
++#define CBR_RG_EN_TX_SELF_MIXER_HI 4
++#define CBR_RG_EN_TX_SELF_MIXER_SZ 1
++#define CBR_RG_EN_TX_DAC_OUT_MSK 0x00000020
++#define CBR_RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
++#define CBR_RG_EN_TX_DAC_OUT_SFT 5
++#define CBR_RG_EN_TX_DAC_OUT_HI 5
++#define CBR_RG_EN_TX_DAC_OUT_SZ 1
++#define CBR_RG_EN_LDO_RX_FE_MSK 0x00000040
++#define CBR_RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
++#define CBR_RG_EN_LDO_RX_FE_SFT 6
++#define CBR_RG_EN_LDO_RX_FE_HI 6
++#define CBR_RG_EN_LDO_RX_FE_SZ 1
++#define CBR_RG_EN_LDO_ABB_MSK 0x00000080
++#define CBR_RG_EN_LDO_ABB_I_MSK 0xffffff7f
++#define CBR_RG_EN_LDO_ABB_SFT 7
++#define CBR_RG_EN_LDO_ABB_HI 7
++#define CBR_RG_EN_LDO_ABB_SZ 1
++#define CBR_RG_EN_LDO_AFE_MSK 0x00000100
++#define CBR_RG_EN_LDO_AFE_I_MSK 0xfffffeff
++#define CBR_RG_EN_LDO_AFE_SFT 8
++#define CBR_RG_EN_LDO_AFE_HI 8
++#define CBR_RG_EN_LDO_AFE_SZ 1
++#define CBR_RG_EN_SX_CHPLDO_MSK 0x00000200
++#define CBR_RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
++#define CBR_RG_EN_SX_CHPLDO_SFT 9
++#define CBR_RG_EN_SX_CHPLDO_HI 9
++#define CBR_RG_EN_SX_CHPLDO_SZ 1
++#define CBR_RG_EN_SX_LOBFLDO_MSK 0x00000400
++#define CBR_RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
++#define CBR_RG_EN_SX_LOBFLDO_SFT 10
++#define CBR_RG_EN_SX_LOBFLDO_HI 10
++#define CBR_RG_EN_SX_LOBFLDO_SZ 1
++#define CBR_RG_EN_IREF_RX_MSK 0x00000800
++#define CBR_RG_EN_IREF_RX_I_MSK 0xfffff7ff
++#define CBR_RG_EN_IREF_RX_SFT 11
++#define CBR_RG_EN_IREF_RX_HI 11
++#define CBR_RG_EN_IREF_RX_SZ 1
++#define CBR_RG_DCDC_MODE_MSK 0x00001000
++#define CBR_RG_DCDC_MODE_I_MSK 0xffffefff
++#define CBR_RG_DCDC_MODE_SFT 12
++#define CBR_RG_DCDC_MODE_HI 12
++#define CBR_RG_DCDC_MODE_SZ 1
++#define CBR_RG_LDO_LEVEL_RX_FE_MSK 0x00000007
++#define CBR_RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
++#define CBR_RG_LDO_LEVEL_RX_FE_SFT 0
++#define CBR_RG_LDO_LEVEL_RX_FE_HI 2
++#define CBR_RG_LDO_LEVEL_RX_FE_SZ 3
++#define CBR_RG_LDO_LEVEL_ABB_MSK 0x00000038
++#define CBR_RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
++#define CBR_RG_LDO_LEVEL_ABB_SFT 3
++#define CBR_RG_LDO_LEVEL_ABB_HI 5
++#define CBR_RG_LDO_LEVEL_ABB_SZ 3
++#define CBR_RG_LDO_LEVEL_AFE_MSK 0x000001c0
++#define CBR_RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
++#define CBR_RG_LDO_LEVEL_AFE_SFT 6
++#define CBR_RG_LDO_LEVEL_AFE_HI 8
++#define CBR_RG_LDO_LEVEL_AFE_SZ 3
++#define CBR_RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
++#define CBR_RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
++#define CBR_RG_SX_LDO_CHP_LEVEL_SFT 9
++#define CBR_RG_SX_LDO_CHP_LEVEL_HI 11
++#define CBR_RG_SX_LDO_CHP_LEVEL_SZ 3
++#define CBR_RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
++#define CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
++#define CBR_RG_SX_LDO_LOBF_LEVEL_SFT 12
++#define CBR_RG_SX_LDO_LOBF_LEVEL_HI 14
++#define CBR_RG_SX_LDO_LOBF_LEVEL_SZ 3
++#define CBR_RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
++#define CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
++#define CBR_RG_SX_LDO_XOSC_LEVEL_SFT 15
++#define CBR_RG_SX_LDO_XOSC_LEVEL_HI 17
++#define CBR_RG_SX_LDO_XOSC_LEVEL_SZ 3
++#define CBR_RG_DP_LDO_LEVEL_MSK 0x001c0000
++#define CBR_RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
++#define CBR_RG_DP_LDO_LEVEL_SFT 18
++#define CBR_RG_DP_LDO_LEVEL_HI 20
++#define CBR_RG_DP_LDO_LEVEL_SZ 3
++#define CBR_RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
++#define CBR_RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
++#define CBR_RG_SX_LDO_VCO_LEVEL_SFT 21
++#define CBR_RG_SX_LDO_VCO_LEVEL_HI 23
++#define CBR_RG_SX_LDO_VCO_LEVEL_SZ 3
++#define CBR_RG_TX_LDO_TX_LEVEL_MSK 0x07000000
++#define CBR_RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
++#define CBR_RG_TX_LDO_TX_LEVEL_SFT 24
++#define CBR_RG_TX_LDO_TX_LEVEL_HI 26
++#define CBR_RG_TX_LDO_TX_LEVEL_SZ 3
++#define CBR_RG_BUCK_LEVEL_MSK 0x38000000
++#define CBR_RG_BUCK_LEVEL_I_MSK 0xc7ffffff
++#define CBR_RG_BUCK_LEVEL_SFT 27
++#define CBR_RG_BUCK_LEVEL_HI 29
++#define CBR_RG_BUCK_LEVEL_SZ 3
++#define CBR_RG_EN_RX_PADSW_MSK 0x00000001
++#define CBR_RG_EN_RX_PADSW_I_MSK 0xfffffffe
++#define CBR_RG_EN_RX_PADSW_SFT 0
++#define CBR_RG_EN_RX_PADSW_HI 0
++#define CBR_RG_EN_RX_PADSW_SZ 1
++#define CBR_RG_EN_RX_TESTNODE_MSK 0x00000002
++#define CBR_RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
++#define CBR_RG_EN_RX_TESTNODE_SFT 1
++#define CBR_RG_EN_RX_TESTNODE_HI 1
++#define CBR_RG_EN_RX_TESTNODE_SZ 1
++#define CBR_RG_RX_ABBCFIX_MSK 0x00000004
++#define CBR_RG_RX_ABBCFIX_I_MSK 0xfffffffb
++#define CBR_RG_RX_ABBCFIX_SFT 2
++#define CBR_RG_RX_ABBCFIX_HI 2
++#define CBR_RG_RX_ABBCFIX_SZ 1
++#define CBR_RG_RX_ABBCTUNE_MSK 0x000001f8
++#define CBR_RG_RX_ABBCTUNE_I_MSK 0xfffffe07
++#define CBR_RG_RX_ABBCTUNE_SFT 3
++#define CBR_RG_RX_ABBCTUNE_HI 8
++#define CBR_RG_RX_ABBCTUNE_SZ 6
++#define CBR_RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
++#define CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
++#define CBR_RG_RX_ABBOUT_TRI_STATE_SFT 9
++#define CBR_RG_RX_ABBOUT_TRI_STATE_HI 9
++#define CBR_RG_RX_ABBOUT_TRI_STATE_SZ 1
++#define CBR_RG_RX_ABB_N_MODE_MSK 0x00000400
++#define CBR_RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
++#define CBR_RG_RX_ABB_N_MODE_SFT 10
++#define CBR_RG_RX_ABB_N_MODE_HI 10
++#define CBR_RG_RX_ABB_N_MODE_SZ 1
++#define CBR_RG_RX_EN_LOOPA_MSK 0x00000800
++#define CBR_RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
++#define CBR_RG_RX_EN_LOOPA_SFT 11
++#define CBR_RG_RX_EN_LOOPA_HI 11
++#define CBR_RG_RX_EN_LOOPA_SZ 1
++#define CBR_RG_RX_FILTERI1ST_MSK 0x00003000
++#define CBR_RG_RX_FILTERI1ST_I_MSK 0xffffcfff
++#define CBR_RG_RX_FILTERI1ST_SFT 12
++#define CBR_RG_RX_FILTERI1ST_HI 13
++#define CBR_RG_RX_FILTERI1ST_SZ 2
++#define CBR_RG_RX_FILTERI2ND_MSK 0x0000c000
++#define CBR_RG_RX_FILTERI2ND_I_MSK 0xffff3fff
++#define CBR_RG_RX_FILTERI2ND_SFT 14
++#define CBR_RG_RX_FILTERI2ND_HI 15
++#define CBR_RG_RX_FILTERI2ND_SZ 2
++#define CBR_RG_RX_FILTERI3RD_MSK 0x00030000
++#define CBR_RG_RX_FILTERI3RD_I_MSK 0xfffcffff
++#define CBR_RG_RX_FILTERI3RD_SFT 16
++#define CBR_RG_RX_FILTERI3RD_HI 17
++#define CBR_RG_RX_FILTERI3RD_SZ 2
++#define CBR_RG_RX_FILTERI_COURSE_MSK 0x000c0000
++#define CBR_RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
++#define CBR_RG_RX_FILTERI_COURSE_SFT 18
++#define CBR_RG_RX_FILTERI_COURSE_HI 19
++#define CBR_RG_RX_FILTERI_COURSE_SZ 2
++#define CBR_RG_RX_FILTERVCM_MSK 0x00300000
++#define CBR_RG_RX_FILTERVCM_I_MSK 0xffcfffff
++#define CBR_RG_RX_FILTERVCM_SFT 20
++#define CBR_RG_RX_FILTERVCM_HI 21
++#define CBR_RG_RX_FILTERVCM_SZ 2
++#define CBR_RG_RX_HPF3M_MSK 0x00400000
++#define CBR_RG_RX_HPF3M_I_MSK 0xffbfffff
++#define CBR_RG_RX_HPF3M_SFT 22
++#define CBR_RG_RX_HPF3M_HI 22
++#define CBR_RG_RX_HPF3M_SZ 1
++#define CBR_RG_RX_HPF300K_MSK 0x00800000
++#define CBR_RG_RX_HPF300K_I_MSK 0xff7fffff
++#define CBR_RG_RX_HPF300K_SFT 23
++#define CBR_RG_RX_HPF300K_HI 23
++#define CBR_RG_RX_HPF300K_SZ 1
++#define CBR_RG_RX_HPFI_MSK 0x03000000
++#define CBR_RG_RX_HPFI_I_MSK 0xfcffffff
++#define CBR_RG_RX_HPFI_SFT 24
++#define CBR_RG_RX_HPFI_HI 25
++#define CBR_RG_RX_HPFI_SZ 2
++#define CBR_RG_RX_HPF_FINALCORNER_MSK 0x0c000000
++#define CBR_RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
++#define CBR_RG_RX_HPF_FINALCORNER_SFT 26
++#define CBR_RG_RX_HPF_FINALCORNER_HI 27
++#define CBR_RG_RX_HPF_FINALCORNER_SZ 2
++#define CBR_RG_RX_HPF_SETTLE1_C_MSK 0x30000000
++#define CBR_RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
++#define CBR_RG_RX_HPF_SETTLE1_C_SFT 28
++#define CBR_RG_RX_HPF_SETTLE1_C_HI 29
++#define CBR_RG_RX_HPF_SETTLE1_C_SZ 2
++#define CBR_RG_RX_HPF_SETTLE1_R_MSK 0x00000003
++#define CBR_RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
++#define CBR_RG_RX_HPF_SETTLE1_R_SFT 0
++#define CBR_RG_RX_HPF_SETTLE1_R_HI 1
++#define CBR_RG_RX_HPF_SETTLE1_R_SZ 2
++#define CBR_RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
++#define CBR_RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
++#define CBR_RG_RX_HPF_SETTLE2_C_SFT 2
++#define CBR_RG_RX_HPF_SETTLE2_C_HI 3
++#define CBR_RG_RX_HPF_SETTLE2_C_SZ 2
++#define CBR_RG_RX_HPF_SETTLE2_R_MSK 0x00000030
++#define CBR_RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
++#define CBR_RG_RX_HPF_SETTLE2_R_SFT 4
++#define CBR_RG_RX_HPF_SETTLE2_R_HI 5
++#define CBR_RG_RX_HPF_SETTLE2_R_SZ 2
++#define CBR_RG_RX_HPF_VCMCON2_MSK 0x000000c0
++#define CBR_RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
++#define CBR_RG_RX_HPF_VCMCON2_SFT 6
++#define CBR_RG_RX_HPF_VCMCON2_HI 7
++#define CBR_RG_RX_HPF_VCMCON2_SZ 2
++#define CBR_RG_RX_HPF_VCMCON_MSK 0x00000300
++#define CBR_RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
++#define CBR_RG_RX_HPF_VCMCON_SFT 8
++#define CBR_RG_RX_HPF_VCMCON_HI 9
++#define CBR_RG_RX_HPF_VCMCON_SZ 2
++#define CBR_RG_RX_OUTVCM_MSK 0x00000c00
++#define CBR_RG_RX_OUTVCM_I_MSK 0xfffff3ff
++#define CBR_RG_RX_OUTVCM_SFT 10
++#define CBR_RG_RX_OUTVCM_HI 11
++#define CBR_RG_RX_OUTVCM_SZ 2
++#define CBR_RG_RX_TZI_MSK 0x00003000
++#define CBR_RG_RX_TZI_I_MSK 0xffffcfff
++#define CBR_RG_RX_TZI_SFT 12
++#define CBR_RG_RX_TZI_HI 13
++#define CBR_RG_RX_TZI_SZ 2
++#define CBR_RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
++#define CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
++#define CBR_RG_RX_TZ_OUT_TRISTATE_SFT 14
++#define CBR_RG_RX_TZ_OUT_TRISTATE_HI 14
++#define CBR_RG_RX_TZ_OUT_TRISTATE_SZ 1
++#define CBR_RG_RX_TZ_VCM_MSK 0x00018000
++#define CBR_RG_RX_TZ_VCM_I_MSK 0xfffe7fff
++#define CBR_RG_RX_TZ_VCM_SFT 15
++#define CBR_RG_RX_TZ_VCM_HI 16
++#define CBR_RG_RX_TZ_VCM_SZ 2
++#define CBR_RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
++#define CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
++#define CBR_RG_EN_RX_RSSI_TESTNODE_SFT 17
++#define CBR_RG_EN_RX_RSSI_TESTNODE_HI 19
++#define CBR_RG_EN_RX_RSSI_TESTNODE_SZ 3
++#define CBR_RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
++#define CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
++#define CBR_RG_RX_ADCRSSI_CLKSEL_SFT 20
++#define CBR_RG_RX_ADCRSSI_CLKSEL_HI 20
++#define CBR_RG_RX_ADCRSSI_CLKSEL_SZ 1
++#define CBR_RG_RX_ADCRSSI_VCM_MSK 0x00600000
++#define CBR_RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
++#define CBR_RG_RX_ADCRSSI_VCM_SFT 21
++#define CBR_RG_RX_ADCRSSI_VCM_HI 22
++#define CBR_RG_RX_ADCRSSI_VCM_SZ 2
++#define CBR_RG_RX_REC_LPFCORNER_MSK 0x01800000
++#define CBR_RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
++#define CBR_RG_RX_REC_LPFCORNER_SFT 23
++#define CBR_RG_RX_REC_LPFCORNER_HI 24
++#define CBR_RG_RX_REC_LPFCORNER_SZ 2
++#define CBR_RG_RSSI_CLOCK_GATING_MSK 0x02000000
++#define CBR_RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
++#define CBR_RG_RSSI_CLOCK_GATING_SFT 25
++#define CBR_RG_RSSI_CLOCK_GATING_HI 25
++#define CBR_RG_RSSI_CLOCK_GATING_SZ 1
++#define CBR_RG_TXPGA_CAPSW_MSK 0x00000003
++#define CBR_RG_TXPGA_CAPSW_I_MSK 0xfffffffc
++#define CBR_RG_TXPGA_CAPSW_SFT 0
++#define CBR_RG_TXPGA_CAPSW_HI 1
++#define CBR_RG_TXPGA_CAPSW_SZ 2
++#define CBR_RG_TXPGA_MAIN_MSK 0x000000fc
++#define CBR_RG_TXPGA_MAIN_I_MSK 0xffffff03
++#define CBR_RG_TXPGA_MAIN_SFT 2
++#define CBR_RG_TXPGA_MAIN_HI 7
++#define CBR_RG_TXPGA_MAIN_SZ 6
++#define CBR_RG_TXPGA_STEER_MSK 0x00003f00
++#define CBR_RG_TXPGA_STEER_I_MSK 0xffffc0ff
++#define CBR_RG_TXPGA_STEER_SFT 8
++#define CBR_RG_TXPGA_STEER_HI 13
++#define CBR_RG_TXPGA_STEER_SZ 6
++#define CBR_RG_TXMOD_GMCELL_MSK 0x0000c000
++#define CBR_RG_TXMOD_GMCELL_I_MSK 0xffff3fff
++#define CBR_RG_TXMOD_GMCELL_SFT 14
++#define CBR_RG_TXMOD_GMCELL_HI 15
++#define CBR_RG_TXMOD_GMCELL_SZ 2
++#define CBR_RG_TXLPF_GMCELL_MSK 0x00030000
++#define CBR_RG_TXLPF_GMCELL_I_MSK 0xfffcffff
++#define CBR_RG_TXLPF_GMCELL_SFT 16
++#define CBR_RG_TXLPF_GMCELL_HI 17
++#define CBR_RG_TXLPF_GMCELL_SZ 2
++#define CBR_RG_PACELL_EN_MSK 0x001c0000
++#define CBR_RG_PACELL_EN_I_MSK 0xffe3ffff
++#define CBR_RG_PACELL_EN_SFT 18
++#define CBR_RG_PACELL_EN_HI 20
++#define CBR_RG_PACELL_EN_SZ 3
++#define CBR_RG_PABIAS_CTRL_MSK 0x01e00000
++#define CBR_RG_PABIAS_CTRL_I_MSK 0xfe1fffff
++#define CBR_RG_PABIAS_CTRL_SFT 21
++#define CBR_RG_PABIAS_CTRL_HI 24
++#define CBR_RG_PABIAS_CTRL_SZ 4
++#define CBR_RG_PABIAS_AB_MSK 0x02000000
++#define CBR_RG_PABIAS_AB_I_MSK 0xfdffffff
++#define CBR_RG_PABIAS_AB_SFT 25
++#define CBR_RG_PABIAS_AB_HI 25
++#define CBR_RG_PABIAS_AB_SZ 1
++#define CBR_RG_TX_DIV_VSET_MSK 0x0c000000
++#define CBR_RG_TX_DIV_VSET_I_MSK 0xf3ffffff
++#define CBR_RG_TX_DIV_VSET_SFT 26
++#define CBR_RG_TX_DIV_VSET_HI 27
++#define CBR_RG_TX_DIV_VSET_SZ 2
++#define CBR_RG_TX_LOBUF_VSET_MSK 0x30000000
++#define CBR_RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
++#define CBR_RG_TX_LOBUF_VSET_SFT 28
++#define CBR_RG_TX_LOBUF_VSET_HI 29
++#define CBR_RG_TX_LOBUF_VSET_SZ 2
++#define CBR_RG_RX_SQDC_MSK 0x00000007
++#define CBR_RG_RX_SQDC_I_MSK 0xfffffff8
++#define CBR_RG_RX_SQDC_SFT 0
++#define CBR_RG_RX_SQDC_HI 2
++#define CBR_RG_RX_SQDC_SZ 3
++#define CBR_RG_RX_DIV2_CORE_MSK 0x00000018
++#define CBR_RG_RX_DIV2_CORE_I_MSK 0xffffffe7
++#define CBR_RG_RX_DIV2_CORE_SFT 3
++#define CBR_RG_RX_DIV2_CORE_HI 4
++#define CBR_RG_RX_DIV2_CORE_SZ 2
++#define CBR_RG_RX_LOBUF_MSK 0x00000060
++#define CBR_RG_RX_LOBUF_I_MSK 0xffffff9f
++#define CBR_RG_RX_LOBUF_SFT 5
++#define CBR_RG_RX_LOBUF_HI 6
++#define CBR_RG_RX_LOBUF_SZ 2
++#define CBR_RG_TX_DPDGM_BIAS_MSK 0x00000780
++#define CBR_RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
++#define CBR_RG_TX_DPDGM_BIAS_SFT 7
++#define CBR_RG_TX_DPDGM_BIAS_HI 10
++#define CBR_RG_TX_DPDGM_BIAS_SZ 4
++#define CBR_RG_TX_DPD_DIV_MSK 0x00007800
++#define CBR_RG_TX_DPD_DIV_I_MSK 0xffff87ff
++#define CBR_RG_TX_DPD_DIV_SFT 11
++#define CBR_RG_TX_DPD_DIV_HI 14
++#define CBR_RG_TX_DPD_DIV_SZ 4
++#define CBR_RG_TX_TSSI_BIAS_MSK 0x00038000
++#define CBR_RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
++#define CBR_RG_TX_TSSI_BIAS_SFT 15
++#define CBR_RG_TX_TSSI_BIAS_HI 17
++#define CBR_RG_TX_TSSI_BIAS_SZ 3
++#define CBR_RG_TX_TSSI_DIV_MSK 0x001c0000
++#define CBR_RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
++#define CBR_RG_TX_TSSI_DIV_SFT 18
++#define CBR_RG_TX_TSSI_DIV_HI 20
++#define CBR_RG_TX_TSSI_DIV_SZ 3
++#define CBR_RG_TX_TSSI_TESTMODE_MSK 0x00200000
++#define CBR_RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
++#define CBR_RG_TX_TSSI_TESTMODE_SFT 21
++#define CBR_RG_TX_TSSI_TESTMODE_HI 21
++#define CBR_RG_TX_TSSI_TESTMODE_SZ 1
++#define CBR_RG_TX_TSSI_TEST_MSK 0x00c00000
++#define CBR_RG_TX_TSSI_TEST_I_MSK 0xff3fffff
++#define CBR_RG_TX_TSSI_TEST_SFT 22
++#define CBR_RG_TX_TSSI_TEST_HI 23
++#define CBR_RG_TX_TSSI_TEST_SZ 2
++#define CBR_RG_RX_HG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_HG_LNA_GC_SFT 0
++#define CBR_RG_RX_HG_LNA_GC_HI 1
++#define CBR_RG_RX_HG_LNA_GC_SZ 2
++#define CBR_RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_HG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_HG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_HG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_HG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_HG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_HG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_HG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_HG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_HG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_HG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_HG_TZ_GC_SFT 14
++#define CBR_RG_RX_HG_TZ_GC_HI 15
++#define CBR_RG_RX_HG_TZ_GC_SZ 2
++#define CBR_RG_RX_HG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_HG_TZ_CAP_SFT 16
++#define CBR_RG_RX_HG_TZ_CAP_HI 18
++#define CBR_RG_RX_HG_TZ_CAP_SZ 3
++#define CBR_RG_RX_MG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_MG_LNA_GC_SFT 0
++#define CBR_RG_RX_MG_LNA_GC_HI 1
++#define CBR_RG_RX_MG_LNA_GC_SZ 2
++#define CBR_RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_MG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_MG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_MG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_MG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_MG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_MG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_MG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_MG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_MG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_MG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_MG_TZ_GC_SFT 14
++#define CBR_RG_RX_MG_TZ_GC_HI 15
++#define CBR_RG_RX_MG_TZ_GC_SZ 2
++#define CBR_RG_RX_MG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_MG_TZ_CAP_SFT 16
++#define CBR_RG_RX_MG_TZ_CAP_HI 18
++#define CBR_RG_RX_MG_TZ_CAP_SZ 3
++#define CBR_RG_RX_LG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_LG_LNA_GC_SFT 0
++#define CBR_RG_RX_LG_LNA_GC_HI 1
++#define CBR_RG_RX_LG_LNA_GC_SZ 2
++#define CBR_RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_LG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_LG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_LG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_LG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_LG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_LG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_LG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_LG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_LG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_LG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_LG_TZ_GC_SFT 14
++#define CBR_RG_RX_LG_TZ_GC_HI 15
++#define CBR_RG_RX_LG_TZ_GC_SZ 2
++#define CBR_RG_RX_LG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_LG_TZ_CAP_SFT 16
++#define CBR_RG_RX_LG_TZ_CAP_HI 18
++#define CBR_RG_RX_LG_TZ_CAP_SZ 3
++#define CBR_RG_RX_ULG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_ULG_LNA_GC_SFT 0
++#define CBR_RG_RX_ULG_LNA_GC_HI 1
++#define CBR_RG_RX_ULG_LNA_GC_SZ 2
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_ULG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_ULG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_ULG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_ULG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_ULG_TZ_GC_SFT 14
++#define CBR_RG_RX_ULG_TZ_GC_HI 15
++#define CBR_RG_RX_ULG_TZ_GC_SZ 2
++#define CBR_RG_RX_ULG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_ULG_TZ_CAP_SFT 16
++#define CBR_RG_RX_ULG_TZ_CAP_HI 18
++#define CBR_RG_RX_ULG_TZ_CAP_SZ 3
++#define CBR_RG_HPF1_FAST_SET_X_MSK 0x00000001
++#define CBR_RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
++#define CBR_RG_HPF1_FAST_SET_X_SFT 0
++#define CBR_RG_HPF1_FAST_SET_X_HI 0
++#define CBR_RG_HPF1_FAST_SET_X_SZ 1
++#define CBR_RG_HPF1_FAST_SET_Y_MSK 0x00000002
++#define CBR_RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
++#define CBR_RG_HPF1_FAST_SET_Y_SFT 1
++#define CBR_RG_HPF1_FAST_SET_Y_HI 1
++#define CBR_RG_HPF1_FAST_SET_Y_SZ 1
++#define CBR_RG_HPF1_FAST_SET_Z_MSK 0x00000004
++#define CBR_RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
++#define CBR_RG_HPF1_FAST_SET_Z_SFT 2
++#define CBR_RG_HPF1_FAST_SET_Z_HI 2
++#define CBR_RG_HPF1_FAST_SET_Z_SZ 1
++#define CBR_RG_HPF_T1A_MSK 0x00000018
++#define CBR_RG_HPF_T1A_I_MSK 0xffffffe7
++#define CBR_RG_HPF_T1A_SFT 3
++#define CBR_RG_HPF_T1A_HI 4
++#define CBR_RG_HPF_T1A_SZ 2
++#define CBR_RG_HPF_T1B_MSK 0x00000060
++#define CBR_RG_HPF_T1B_I_MSK 0xffffff9f
++#define CBR_RG_HPF_T1B_SFT 5
++#define CBR_RG_HPF_T1B_HI 6
++#define CBR_RG_HPF_T1B_SZ 2
++#define CBR_RG_HPF_T1C_MSK 0x00000180
++#define CBR_RG_HPF_T1C_I_MSK 0xfffffe7f
++#define CBR_RG_HPF_T1C_SFT 7
++#define CBR_RG_HPF_T1C_HI 8
++#define CBR_RG_HPF_T1C_SZ 2
++#define CBR_RG_RX_LNA_TRI_SEL_MSK 0x00000600
++#define CBR_RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
++#define CBR_RG_RX_LNA_TRI_SEL_SFT 9
++#define CBR_RG_RX_LNA_TRI_SEL_HI 10
++#define CBR_RG_RX_LNA_TRI_SEL_SZ 2
++#define CBR_RG_RX_LNA_SETTLE_MSK 0x00001800
++#define CBR_RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
++#define CBR_RG_RX_LNA_SETTLE_SFT 11
++#define CBR_RG_RX_LNA_SETTLE_HI 12
++#define CBR_RG_RX_LNA_SETTLE_SZ 2
++#define CBR_RG_ADC_CLKSEL_MSK 0x00000001
++#define CBR_RG_ADC_CLKSEL_I_MSK 0xfffffffe
++#define CBR_RG_ADC_CLKSEL_SFT 0
++#define CBR_RG_ADC_CLKSEL_HI 0
++#define CBR_RG_ADC_CLKSEL_SZ 1
++#define CBR_RG_ADC_DIBIAS_MSK 0x00000006
++#define CBR_RG_ADC_DIBIAS_I_MSK 0xfffffff9
++#define CBR_RG_ADC_DIBIAS_SFT 1
++#define CBR_RG_ADC_DIBIAS_HI 2
++#define CBR_RG_ADC_DIBIAS_SZ 2
++#define CBR_RG_ADC_DIVR_MSK 0x00000008
++#define CBR_RG_ADC_DIVR_I_MSK 0xfffffff7
++#define CBR_RG_ADC_DIVR_SFT 3
++#define CBR_RG_ADC_DIVR_HI 3
++#define CBR_RG_ADC_DIVR_SZ 1
++#define CBR_RG_ADC_DVCMI_MSK 0x00000030
++#define CBR_RG_ADC_DVCMI_I_MSK 0xffffffcf
++#define CBR_RG_ADC_DVCMI_SFT 4
++#define CBR_RG_ADC_DVCMI_HI 5
++#define CBR_RG_ADC_DVCMI_SZ 2
++#define CBR_RG_ADC_SAMSEL_MSK 0x000003c0
++#define CBR_RG_ADC_SAMSEL_I_MSK 0xfffffc3f
++#define CBR_RG_ADC_SAMSEL_SFT 6
++#define CBR_RG_ADC_SAMSEL_HI 9
++#define CBR_RG_ADC_SAMSEL_SZ 4
++#define CBR_RG_ADC_STNBY_MSK 0x00000400
++#define CBR_RG_ADC_STNBY_I_MSK 0xfffffbff
++#define CBR_RG_ADC_STNBY_SFT 10
++#define CBR_RG_ADC_STNBY_HI 10
++#define CBR_RG_ADC_STNBY_SZ 1
++#define CBR_RG_ADC_TESTMODE_MSK 0x00000800
++#define CBR_RG_ADC_TESTMODE_I_MSK 0xfffff7ff
++#define CBR_RG_ADC_TESTMODE_SFT 11
++#define CBR_RG_ADC_TESTMODE_HI 11
++#define CBR_RG_ADC_TESTMODE_SZ 1
++#define CBR_RG_ADC_TSEL_MSK 0x0000f000
++#define CBR_RG_ADC_TSEL_I_MSK 0xffff0fff
++#define CBR_RG_ADC_TSEL_SFT 12
++#define CBR_RG_ADC_TSEL_HI 15
++#define CBR_RG_ADC_TSEL_SZ 4
++#define CBR_RG_ADC_VRSEL_MSK 0x00030000
++#define CBR_RG_ADC_VRSEL_I_MSK 0xfffcffff
++#define CBR_RG_ADC_VRSEL_SFT 16
++#define CBR_RG_ADC_VRSEL_HI 17
++#define CBR_RG_ADC_VRSEL_SZ 2
++#define CBR_RG_DICMP_MSK 0x000c0000
++#define CBR_RG_DICMP_I_MSK 0xfff3ffff
++#define CBR_RG_DICMP_SFT 18
++#define CBR_RG_DICMP_HI 19
++#define CBR_RG_DICMP_SZ 2
++#define CBR_RG_DIOP_MSK 0x00300000
++#define CBR_RG_DIOP_I_MSK 0xffcfffff
++#define CBR_RG_DIOP_SFT 20
++#define CBR_RG_DIOP_HI 21
++#define CBR_RG_DIOP_SZ 2
++#define CBR_RG_DACI1ST_MSK 0x00000003
++#define CBR_RG_DACI1ST_I_MSK 0xfffffffc
++#define CBR_RG_DACI1ST_SFT 0
++#define CBR_RG_DACI1ST_HI 1
++#define CBR_RG_DACI1ST_SZ 2
++#define CBR_RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
++#define CBR_RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
++#define CBR_RG_TX_DACLPF_ICOURSE_SFT 2
++#define CBR_RG_TX_DACLPF_ICOURSE_HI 3
++#define CBR_RG_TX_DACLPF_ICOURSE_SZ 2
++#define CBR_RG_TX_DACLPF_IFINE_MSK 0x00000030
++#define CBR_RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
++#define CBR_RG_TX_DACLPF_IFINE_SFT 4
++#define CBR_RG_TX_DACLPF_IFINE_HI 5
++#define CBR_RG_TX_DACLPF_IFINE_SZ 2
++#define CBR_RG_TX_DACLPF_VCM_MSK 0x000000c0
++#define CBR_RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
++#define CBR_RG_TX_DACLPF_VCM_SFT 6
++#define CBR_RG_TX_DACLPF_VCM_HI 7
++#define CBR_RG_TX_DACLPF_VCM_SZ 2
++#define CBR_RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
++#define CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
++#define CBR_RG_TX_DAC_CKEDGE_SEL_SFT 8
++#define CBR_RG_TX_DAC_CKEDGE_SEL_HI 8
++#define CBR_RG_TX_DAC_CKEDGE_SEL_SZ 1
++#define CBR_RG_TX_DAC_IBIAS_MSK 0x00000600
++#define CBR_RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
++#define CBR_RG_TX_DAC_IBIAS_SFT 9
++#define CBR_RG_TX_DAC_IBIAS_HI 10
++#define CBR_RG_TX_DAC_IBIAS_SZ 2
++#define CBR_RG_TX_DAC_OS_MSK 0x00003800
++#define CBR_RG_TX_DAC_OS_I_MSK 0xffffc7ff
++#define CBR_RG_TX_DAC_OS_SFT 11
++#define CBR_RG_TX_DAC_OS_HI 13
++#define CBR_RG_TX_DAC_OS_SZ 3
++#define CBR_RG_TX_DAC_RCAL_MSK 0x0000c000
++#define CBR_RG_TX_DAC_RCAL_I_MSK 0xffff3fff
++#define CBR_RG_TX_DAC_RCAL_SFT 14
++#define CBR_RG_TX_DAC_RCAL_HI 15
++#define CBR_RG_TX_DAC_RCAL_SZ 2
++#define CBR_RG_TX_DAC_TSEL_MSK 0x000f0000
++#define CBR_RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
++#define CBR_RG_TX_DAC_TSEL_SFT 16
++#define CBR_RG_TX_DAC_TSEL_HI 19
++#define CBR_RG_TX_DAC_TSEL_SZ 4
++#define CBR_RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
++#define CBR_RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
++#define CBR_RG_TX_EN_VOLTAGE_IN_SFT 20
++#define CBR_RG_TX_EN_VOLTAGE_IN_HI 20
++#define CBR_RG_TX_EN_VOLTAGE_IN_SZ 1
++#define CBR_RG_TXLPF_BYPASS_MSK 0x00200000
++#define CBR_RG_TXLPF_BYPASS_I_MSK 0xffdfffff
++#define CBR_RG_TXLPF_BYPASS_SFT 21
++#define CBR_RG_TXLPF_BYPASS_HI 21
++#define CBR_RG_TXLPF_BYPASS_SZ 1
++#define CBR_RG_TXLPF_BOOSTI_MSK 0x00400000
++#define CBR_RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
++#define CBR_RG_TXLPF_BOOSTI_SFT 22
++#define CBR_RG_TXLPF_BOOSTI_HI 22
++#define CBR_RG_TXLPF_BOOSTI_SZ 1
++#define CBR_RG_EN_SX_R3_MSK 0x00000001
++#define CBR_RG_EN_SX_R3_I_MSK 0xfffffffe
++#define CBR_RG_EN_SX_R3_SFT 0
++#define CBR_RG_EN_SX_R3_HI 0
++#define CBR_RG_EN_SX_R3_SZ 1
++#define CBR_RG_EN_SX_CH_MSK 0x00000002
++#define CBR_RG_EN_SX_CH_I_MSK 0xfffffffd
++#define CBR_RG_EN_SX_CH_SFT 1
++#define CBR_RG_EN_SX_CH_HI 1
++#define CBR_RG_EN_SX_CH_SZ 1
++#define CBR_RG_EN_SX_CHP_MSK 0x00000004
++#define CBR_RG_EN_SX_CHP_I_MSK 0xfffffffb
++#define CBR_RG_EN_SX_CHP_SFT 2
++#define CBR_RG_EN_SX_CHP_HI 2
++#define CBR_RG_EN_SX_CHP_SZ 1
++#define CBR_RG_EN_SX_DIVCK_MSK 0x00000008
++#define CBR_RG_EN_SX_DIVCK_I_MSK 0xfffffff7
++#define CBR_RG_EN_SX_DIVCK_SFT 3
++#define CBR_RG_EN_SX_DIVCK_HI 3
++#define CBR_RG_EN_SX_DIVCK_SZ 1
++#define CBR_RG_EN_SX_VCOBF_MSK 0x00000010
++#define CBR_RG_EN_SX_VCOBF_I_MSK 0xffffffef
++#define CBR_RG_EN_SX_VCOBF_SFT 4
++#define CBR_RG_EN_SX_VCOBF_HI 4
++#define CBR_RG_EN_SX_VCOBF_SZ 1
++#define CBR_RG_EN_SX_VCO_MSK 0x00000020
++#define CBR_RG_EN_SX_VCO_I_MSK 0xffffffdf
++#define CBR_RG_EN_SX_VCO_SFT 5
++#define CBR_RG_EN_SX_VCO_HI 5
++#define CBR_RG_EN_SX_VCO_SZ 1
++#define CBR_RG_EN_SX_MOD_MSK 0x00000040
++#define CBR_RG_EN_SX_MOD_I_MSK 0xffffffbf
++#define CBR_RG_EN_SX_MOD_SFT 6
++#define CBR_RG_EN_SX_MOD_HI 6
++#define CBR_RG_EN_SX_MOD_SZ 1
++#define CBR_RG_EN_SX_LCK_MSK 0x00000080
++#define CBR_RG_EN_SX_LCK_I_MSK 0xffffff7f
++#define CBR_RG_EN_SX_LCK_SFT 7
++#define CBR_RG_EN_SX_LCK_HI 7
++#define CBR_RG_EN_SX_LCK_SZ 1
++#define CBR_RG_EN_SX_DITHER_MSK 0x00000100
++#define CBR_RG_EN_SX_DITHER_I_MSK 0xfffffeff
++#define CBR_RG_EN_SX_DITHER_SFT 8
++#define CBR_RG_EN_SX_DITHER_HI 8
++#define CBR_RG_EN_SX_DITHER_SZ 1
++#define CBR_RG_EN_SX_DELCAL_MSK 0x00000200
++#define CBR_RG_EN_SX_DELCAL_I_MSK 0xfffffdff
++#define CBR_RG_EN_SX_DELCAL_SFT 9
++#define CBR_RG_EN_SX_DELCAL_HI 9
++#define CBR_RG_EN_SX_DELCAL_SZ 1
++#define CBR_RG_EN_SX_PC_BYPASS_MSK 0x00000400
++#define CBR_RG_EN_SX_PC_BYPASS_I_MSK 0xfffffbff
++#define CBR_RG_EN_SX_PC_BYPASS_SFT 10
++#define CBR_RG_EN_SX_PC_BYPASS_HI 10
++#define CBR_RG_EN_SX_PC_BYPASS_SZ 1
++#define CBR_RG_EN_SX_VT_MON_MSK 0x00000800
++#define CBR_RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
++#define CBR_RG_EN_SX_VT_MON_SFT 11
++#define CBR_RG_EN_SX_VT_MON_HI 11
++#define CBR_RG_EN_SX_VT_MON_SZ 1
++#define CBR_RG_EN_SX_VT_MON_DG_MSK 0x00001000
++#define CBR_RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
++#define CBR_RG_EN_SX_VT_MON_DG_SFT 12
++#define CBR_RG_EN_SX_VT_MON_DG_HI 12
++#define CBR_RG_EN_SX_VT_MON_DG_SZ 1
++#define CBR_RG_EN_SX_DIV_MSK 0x00002000
++#define CBR_RG_EN_SX_DIV_I_MSK 0xffffdfff
++#define CBR_RG_EN_SX_DIV_SFT 13
++#define CBR_RG_EN_SX_DIV_HI 13
++#define CBR_RG_EN_SX_DIV_SZ 1
++#define CBR_RG_EN_SX_LPF_MSK 0x00004000
++#define CBR_RG_EN_SX_LPF_I_MSK 0xffffbfff
++#define CBR_RG_EN_SX_LPF_SFT 14
++#define CBR_RG_EN_SX_LPF_HI 14
++#define CBR_RG_EN_SX_LPF_SZ 1
++#define CBR_RG_SX_RFCTRL_F_MSK 0x00ffffff
++#define CBR_RG_SX_RFCTRL_F_I_MSK 0xff000000
++#define CBR_RG_SX_RFCTRL_F_SFT 0
++#define CBR_RG_SX_RFCTRL_F_HI 23
++#define CBR_RG_SX_RFCTRL_F_SZ 24
++#define CBR_RG_SX_SEL_CP_MSK 0x0f000000
++#define CBR_RG_SX_SEL_CP_I_MSK 0xf0ffffff
++#define CBR_RG_SX_SEL_CP_SFT 24
++#define CBR_RG_SX_SEL_CP_HI 27
++#define CBR_RG_SX_SEL_CP_SZ 4
++#define CBR_RG_SX_SEL_CS_MSK 0xf0000000
++#define CBR_RG_SX_SEL_CS_I_MSK 0x0fffffff
++#define CBR_RG_SX_SEL_CS_SFT 28
++#define CBR_RG_SX_SEL_CS_HI 31
++#define CBR_RG_SX_SEL_CS_SZ 4
++#define CBR_RG_SX_RFCTRL_CH_MSK 0x000007ff
++#define CBR_RG_SX_RFCTRL_CH_I_MSK 0xfffff800
++#define CBR_RG_SX_RFCTRL_CH_SFT 0
++#define CBR_RG_SX_RFCTRL_CH_HI 10
++#define CBR_RG_SX_RFCTRL_CH_SZ 11
++#define CBR_RG_SX_SEL_C3_MSK 0x00007800
++#define CBR_RG_SX_SEL_C3_I_MSK 0xffff87ff
++#define CBR_RG_SX_SEL_C3_SFT 11
++#define CBR_RG_SX_SEL_C3_HI 14
++#define CBR_RG_SX_SEL_C3_SZ 4
++#define CBR_RG_SX_SEL_RS_MSK 0x000f8000
++#define CBR_RG_SX_SEL_RS_I_MSK 0xfff07fff
++#define CBR_RG_SX_SEL_RS_SFT 15
++#define CBR_RG_SX_SEL_RS_HI 19
++#define CBR_RG_SX_SEL_RS_SZ 5
++#define CBR_RG_SX_SEL_R3_MSK 0x01f00000
++#define CBR_RG_SX_SEL_R3_I_MSK 0xfe0fffff
++#define CBR_RG_SX_SEL_R3_SFT 20
++#define CBR_RG_SX_SEL_R3_HI 24
++#define CBR_RG_SX_SEL_R3_SZ 5
++#define CBR_RG_SX_SEL_ICHP_MSK 0x0000001f
++#define CBR_RG_SX_SEL_ICHP_I_MSK 0xffffffe0
++#define CBR_RG_SX_SEL_ICHP_SFT 0
++#define CBR_RG_SX_SEL_ICHP_HI 4
++#define CBR_RG_SX_SEL_ICHP_SZ 5
++#define CBR_RG_SX_SEL_PCHP_MSK 0x000003e0
++#define CBR_RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
++#define CBR_RG_SX_SEL_PCHP_SFT 5
++#define CBR_RG_SX_SEL_PCHP_HI 9
++#define CBR_RG_SX_SEL_PCHP_SZ 5
++#define CBR_RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
++#define CBR_RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
++#define CBR_RG_SX_SEL_CHP_REGOP_SFT 10
++#define CBR_RG_SX_SEL_CHP_REGOP_HI 13
++#define CBR_RG_SX_SEL_CHP_REGOP_SZ 4
++#define CBR_RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
++#define CBR_RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
++#define CBR_RG_SX_SEL_CHP_UNIOP_SFT 14
++#define CBR_RG_SX_SEL_CHP_UNIOP_HI 17
++#define CBR_RG_SX_SEL_CHP_UNIOP_SZ 4
++#define CBR_RG_SX_CHP_IOST_POL_MSK 0x00040000
++#define CBR_RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
++#define CBR_RG_SX_CHP_IOST_POL_SFT 18
++#define CBR_RG_SX_CHP_IOST_POL_HI 18
++#define CBR_RG_SX_CHP_IOST_POL_SZ 1
++#define CBR_RG_SX_CHP_IOST_MSK 0x00380000
++#define CBR_RG_SX_CHP_IOST_I_MSK 0xffc7ffff
++#define CBR_RG_SX_CHP_IOST_SFT 19
++#define CBR_RG_SX_CHP_IOST_HI 21
++#define CBR_RG_SX_CHP_IOST_SZ 3
++#define CBR_RG_SX_PFDSEL_MSK 0x00400000
++#define CBR_RG_SX_PFDSEL_I_MSK 0xffbfffff
++#define CBR_RG_SX_PFDSEL_SFT 22
++#define CBR_RG_SX_PFDSEL_HI 22
++#define CBR_RG_SX_PFDSEL_SZ 1
++#define CBR_RG_SX_PFD_SET_MSK 0x00800000
++#define CBR_RG_SX_PFD_SET_I_MSK 0xff7fffff
++#define CBR_RG_SX_PFD_SET_SFT 23
++#define CBR_RG_SX_PFD_SET_HI 23
++#define CBR_RG_SX_PFD_SET_SZ 1
++#define CBR_RG_SX_PFD_SET1_MSK 0x01000000
++#define CBR_RG_SX_PFD_SET1_I_MSK 0xfeffffff
++#define CBR_RG_SX_PFD_SET1_SFT 24
++#define CBR_RG_SX_PFD_SET1_HI 24
++#define CBR_RG_SX_PFD_SET1_SZ 1
++#define CBR_RG_SX_PFD_SET2_MSK 0x02000000
++#define CBR_RG_SX_PFD_SET2_I_MSK 0xfdffffff
++#define CBR_RG_SX_PFD_SET2_SFT 25
++#define CBR_RG_SX_PFD_SET2_HI 25
++#define CBR_RG_SX_PFD_SET2_SZ 1
++#define CBR_RG_SX_VBNCAS_SEL_MSK 0x04000000
++#define CBR_RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
++#define CBR_RG_SX_VBNCAS_SEL_SFT 26
++#define CBR_RG_SX_VBNCAS_SEL_HI 26
++#define CBR_RG_SX_VBNCAS_SEL_SZ 1
++#define CBR_RG_SX_PFD_RST_H_MSK 0x08000000
++#define CBR_RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
++#define CBR_RG_SX_PFD_RST_H_SFT 27
++#define CBR_RG_SX_PFD_RST_H_HI 27
++#define CBR_RG_SX_PFD_RST_H_SZ 1
++#define CBR_RG_SX_PFD_TRUP_MSK 0x10000000
++#define CBR_RG_SX_PFD_TRUP_I_MSK 0xefffffff
++#define CBR_RG_SX_PFD_TRUP_SFT 28
++#define CBR_RG_SX_PFD_TRUP_HI 28
++#define CBR_RG_SX_PFD_TRUP_SZ 1
++#define CBR_RG_SX_PFD_TRDN_MSK 0x20000000
++#define CBR_RG_SX_PFD_TRDN_I_MSK 0xdfffffff
++#define CBR_RG_SX_PFD_TRDN_SFT 29
++#define CBR_RG_SX_PFD_TRDN_HI 29
++#define CBR_RG_SX_PFD_TRDN_SZ 1
++#define CBR_RG_SX_PFD_TRSEL_MSK 0x40000000
++#define CBR_RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
++#define CBR_RG_SX_PFD_TRSEL_SFT 30
++#define CBR_RG_SX_PFD_TRSEL_HI 30
++#define CBR_RG_SX_PFD_TRSEL_SZ 1
++#define CBR_RG_SX_VCOBA_R_MSK 0x00000007
++#define CBR_RG_SX_VCOBA_R_I_MSK 0xfffffff8
++#define CBR_RG_SX_VCOBA_R_SFT 0
++#define CBR_RG_SX_VCOBA_R_HI 2
++#define CBR_RG_SX_VCOBA_R_SZ 3
++#define CBR_RG_SX_VCORSEL_MSK 0x000000f8
++#define CBR_RG_SX_VCORSEL_I_MSK 0xffffff07
++#define CBR_RG_SX_VCORSEL_SFT 3
++#define CBR_RG_SX_VCORSEL_HI 7
++#define CBR_RG_SX_VCORSEL_SZ 5
++#define CBR_RG_SX_VCOCUSEL_MSK 0x00000f00
++#define CBR_RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
++#define CBR_RG_SX_VCOCUSEL_SFT 8
++#define CBR_RG_SX_VCOCUSEL_HI 11
++#define CBR_RG_SX_VCOCUSEL_SZ 4
++#define CBR_RG_SX_RXBFSEL_MSK 0x0000f000
++#define CBR_RG_SX_RXBFSEL_I_MSK 0xffff0fff
++#define CBR_RG_SX_RXBFSEL_SFT 12
++#define CBR_RG_SX_RXBFSEL_HI 15
++#define CBR_RG_SX_RXBFSEL_SZ 4
++#define CBR_RG_SX_TXBFSEL_MSK 0x000f0000
++#define CBR_RG_SX_TXBFSEL_I_MSK 0xfff0ffff
++#define CBR_RG_SX_TXBFSEL_SFT 16
++#define CBR_RG_SX_TXBFSEL_HI 19
++#define CBR_RG_SX_TXBFSEL_SZ 4
++#define CBR_RG_SX_VCOBFSEL_MSK 0x00f00000
++#define CBR_RG_SX_VCOBFSEL_I_MSK 0xff0fffff
++#define CBR_RG_SX_VCOBFSEL_SFT 20
++#define CBR_RG_SX_VCOBFSEL_HI 23
++#define CBR_RG_SX_VCOBFSEL_SZ 4
++#define CBR_RG_SX_DIVBFSEL_MSK 0x0f000000
++#define CBR_RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
++#define CBR_RG_SX_DIVBFSEL_SFT 24
++#define CBR_RG_SX_DIVBFSEL_HI 27
++#define CBR_RG_SX_DIVBFSEL_SZ 4
++#define CBR_RG_SX_GNDR_SEL_MSK 0xf0000000
++#define CBR_RG_SX_GNDR_SEL_I_MSK 0x0fffffff
++#define CBR_RG_SX_GNDR_SEL_SFT 28
++#define CBR_RG_SX_GNDR_SEL_HI 31
++#define CBR_RG_SX_GNDR_SEL_SZ 4
++#define CBR_RG_SX_DITHER_WEIGHT_MSK 0x00000003
++#define CBR_RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
++#define CBR_RG_SX_DITHER_WEIGHT_SFT 0
++#define CBR_RG_SX_DITHER_WEIGHT_HI 1
++#define CBR_RG_SX_DITHER_WEIGHT_SZ 2
++#define CBR_RG_SX_MOD_ERRCMP_MSK 0x0000000c
++#define CBR_RG_SX_MOD_ERRCMP_I_MSK 0xfffffff3
++#define CBR_RG_SX_MOD_ERRCMP_SFT 2
++#define CBR_RG_SX_MOD_ERRCMP_HI 3
++#define CBR_RG_SX_MOD_ERRCMP_SZ 2
++#define CBR_RG_SX_MOD_ORDER_MSK 0x00000030
++#define CBR_RG_SX_MOD_ORDER_I_MSK 0xffffffcf
++#define CBR_RG_SX_MOD_ORDER_SFT 4
++#define CBR_RG_SX_MOD_ORDER_HI 5
++#define CBR_RG_SX_MOD_ORDER_SZ 2
++#define CBR_RG_SX_SDM_D1_MSK 0x00000040
++#define CBR_RG_SX_SDM_D1_I_MSK 0xffffffbf
++#define CBR_RG_SX_SDM_D1_SFT 6
++#define CBR_RG_SX_SDM_D1_HI 6
++#define CBR_RG_SX_SDM_D1_SZ 1
++#define CBR_RG_SX_SDM_D2_MSK 0x00000080
++#define CBR_RG_SX_SDM_D2_I_MSK 0xffffff7f
++#define CBR_RG_SX_SDM_D2_SFT 7
++#define CBR_RG_SX_SDM_D2_HI 7
++#define CBR_RG_SX_SDM_D2_SZ 1
++#define CBR_RG_SDM_PASS_MSK 0x00000100
++#define CBR_RG_SDM_PASS_I_MSK 0xfffffeff
++#define CBR_RG_SDM_PASS_SFT 8
++#define CBR_RG_SDM_PASS_HI 8
++#define CBR_RG_SDM_PASS_SZ 1
++#define CBR_RG_SX_RST_H_DIV_MSK 0x00000200
++#define CBR_RG_SX_RST_H_DIV_I_MSK 0xfffffdff
++#define CBR_RG_SX_RST_H_DIV_SFT 9
++#define CBR_RG_SX_RST_H_DIV_HI 9
++#define CBR_RG_SX_RST_H_DIV_SZ 1
++#define CBR_RG_SX_SDM_EDGE_MSK 0x00000400
++#define CBR_RG_SX_SDM_EDGE_I_MSK 0xfffffbff
++#define CBR_RG_SX_SDM_EDGE_SFT 10
++#define CBR_RG_SX_SDM_EDGE_HI 10
++#define CBR_RG_SX_SDM_EDGE_SZ 1
++#define CBR_RG_SX_XO_GM_MSK 0x00001800
++#define CBR_RG_SX_XO_GM_I_MSK 0xffffe7ff
++#define CBR_RG_SX_XO_GM_SFT 11
++#define CBR_RG_SX_XO_GM_HI 12
++#define CBR_RG_SX_XO_GM_SZ 2
++#define CBR_RG_SX_REFBYTWO_MSK 0x00002000
++#define CBR_RG_SX_REFBYTWO_I_MSK 0xffffdfff
++#define CBR_RG_SX_REFBYTWO_SFT 13
++#define CBR_RG_SX_REFBYTWO_HI 13
++#define CBR_RG_SX_REFBYTWO_SZ 1
++#define CBR_RG_SX_XO_SWCAP_MSK 0x0003c000
++#define CBR_RG_SX_XO_SWCAP_I_MSK 0xfffc3fff
++#define CBR_RG_SX_XO_SWCAP_SFT 14
++#define CBR_RG_SX_XO_SWCAP_HI 17
++#define CBR_RG_SX_XO_SWCAP_SZ 4
++#define CBR_RG_SX_SDMLUT_INV_MSK 0x00040000
++#define CBR_RG_SX_SDMLUT_INV_I_MSK 0xfffbffff
++#define CBR_RG_SX_SDMLUT_INV_SFT 18
++#define CBR_RG_SX_SDMLUT_INV_HI 18
++#define CBR_RG_SX_SDMLUT_INV_SZ 1
++#define CBR_RG_SX_LCKEN_MSK 0x00080000
++#define CBR_RG_SX_LCKEN_I_MSK 0xfff7ffff
++#define CBR_RG_SX_LCKEN_SFT 19
++#define CBR_RG_SX_LCKEN_HI 19
++#define CBR_RG_SX_LCKEN_SZ 1
++#define CBR_RG_SX_PREVDD_MSK 0x00f00000
++#define CBR_RG_SX_PREVDD_I_MSK 0xff0fffff
++#define CBR_RG_SX_PREVDD_SFT 20
++#define CBR_RG_SX_PREVDD_HI 23
++#define CBR_RG_SX_PREVDD_SZ 4
++#define CBR_RG_SX_PSCONTERVDD_MSK 0x0f000000
++#define CBR_RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
++#define CBR_RG_SX_PSCONTERVDD_SFT 24
++#define CBR_RG_SX_PSCONTERVDD_HI 27
++#define CBR_RG_SX_PSCONTERVDD_SZ 4
++#define CBR_RG_SX_MOD_ERR_DELAY_MSK 0x30000000
++#define CBR_RG_SX_MOD_ERR_DELAY_I_MSK 0xcfffffff
++#define CBR_RG_SX_MOD_ERR_DELAY_SFT 28
++#define CBR_RG_SX_MOD_ERR_DELAY_HI 29
++#define CBR_RG_SX_MOD_ERR_DELAY_SZ 2
++#define CBR_RG_SX_MODDB_MSK 0x40000000
++#define CBR_RG_SX_MODDB_I_MSK 0xbfffffff
++#define CBR_RG_SX_MODDB_SFT 30
++#define CBR_RG_SX_MODDB_HI 30
++#define CBR_RG_SX_MODDB_SZ 1
++#define CBR_RG_SX_CV_CURVE_SEL_MSK 0x00000003
++#define CBR_RG_SX_CV_CURVE_SEL_I_MSK 0xfffffffc
++#define CBR_RG_SX_CV_CURVE_SEL_SFT 0
++#define CBR_RG_SX_CV_CURVE_SEL_HI 1
++#define CBR_RG_SX_CV_CURVE_SEL_SZ 2
++#define CBR_RG_SX_SEL_DELAY_MSK 0x0000007c
++#define CBR_RG_SX_SEL_DELAY_I_MSK 0xffffff83
++#define CBR_RG_SX_SEL_DELAY_SFT 2
++#define CBR_RG_SX_SEL_DELAY_HI 6
++#define CBR_RG_SX_SEL_DELAY_SZ 5
++#define CBR_RG_SX_REF_CYCLE_MSK 0x00000780
++#define CBR_RG_SX_REF_CYCLE_I_MSK 0xfffff87f
++#define CBR_RG_SX_REF_CYCLE_SFT 7
++#define CBR_RG_SX_REF_CYCLE_HI 10
++#define CBR_RG_SX_REF_CYCLE_SZ 4
++#define CBR_RG_SX_VCOBY16_MSK 0x00000800
++#define CBR_RG_SX_VCOBY16_I_MSK 0xfffff7ff
++#define CBR_RG_SX_VCOBY16_SFT 11
++#define CBR_RG_SX_VCOBY16_HI 11
++#define CBR_RG_SX_VCOBY16_SZ 1
++#define CBR_RG_SX_VCOBY32_MSK 0x00001000
++#define CBR_RG_SX_VCOBY32_I_MSK 0xffffefff
++#define CBR_RG_SX_VCOBY32_SFT 12
++#define CBR_RG_SX_VCOBY32_HI 12
++#define CBR_RG_SX_VCOBY32_SZ 1
++#define CBR_RG_SX_PH_MSK 0x00002000
++#define CBR_RG_SX_PH_I_MSK 0xffffdfff
++#define CBR_RG_SX_PH_SFT 13
++#define CBR_RG_SX_PH_HI 13
++#define CBR_RG_SX_PH_SZ 1
++#define CBR_RG_SX_PL_MSK 0x00004000
++#define CBR_RG_SX_PL_I_MSK 0xffffbfff
++#define CBR_RG_SX_PL_SFT 14
++#define CBR_RG_SX_PL_HI 14
++#define CBR_RG_SX_PL_SZ 1
++#define CBR_RG_SX_VT_MON_MODE_MSK 0x00000001
++#define CBR_RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
++#define CBR_RG_SX_VT_MON_MODE_SFT 0
++#define CBR_RG_SX_VT_MON_MODE_HI 0
++#define CBR_RG_SX_VT_MON_MODE_SZ 1
++#define CBR_RG_SX_VT_TH_HI_MSK 0x00000006
++#define CBR_RG_SX_VT_TH_HI_I_MSK 0xfffffff9
++#define CBR_RG_SX_VT_TH_HI_SFT 1
++#define CBR_RG_SX_VT_TH_HI_HI 2
++#define CBR_RG_SX_VT_TH_HI_SZ 2
++#define CBR_RG_SX_VT_TH_LO_MSK 0x00000018
++#define CBR_RG_SX_VT_TH_LO_I_MSK 0xffffffe7
++#define CBR_RG_SX_VT_TH_LO_SFT 3
++#define CBR_RG_SX_VT_TH_LO_HI 4
++#define CBR_RG_SX_VT_TH_LO_SZ 2
++#define CBR_RG_SX_VT_SET_MSK 0x00000020
++#define CBR_RG_SX_VT_SET_I_MSK 0xffffffdf
++#define CBR_RG_SX_VT_SET_SFT 5
++#define CBR_RG_SX_VT_SET_HI 5
++#define CBR_RG_SX_VT_SET_SZ 1
++#define CBR_RG_SX_VT_MON_TMR_MSK 0x00007fc0
++#define CBR_RG_SX_VT_MON_TMR_I_MSK 0xffff803f
++#define CBR_RG_SX_VT_MON_TMR_SFT 6
++#define CBR_RG_SX_VT_MON_TMR_HI 14
++#define CBR_RG_SX_VT_MON_TMR_SZ 9
++#define CBR_RG_IDEAL_CYCLE_MSK 0x0fff8000
++#define CBR_RG_IDEAL_CYCLE_I_MSK 0xf0007fff
++#define CBR_RG_IDEAL_CYCLE_SFT 15
++#define CBR_RG_IDEAL_CYCLE_HI 27
++#define CBR_RG_IDEAL_CYCLE_SZ 13
++#define CBR_RG_EN_DP_VT_MON_MSK 0x00000001
++#define CBR_RG_EN_DP_VT_MON_I_MSK 0xfffffffe
++#define CBR_RG_EN_DP_VT_MON_SFT 0
++#define CBR_RG_EN_DP_VT_MON_HI 0
++#define CBR_RG_EN_DP_VT_MON_SZ 1
++#define CBR_RG_DP_VT_TH_HI_MSK 0x00000006
++#define CBR_RG_DP_VT_TH_HI_I_MSK 0xfffffff9
++#define CBR_RG_DP_VT_TH_HI_SFT 1
++#define CBR_RG_DP_VT_TH_HI_HI 2
++#define CBR_RG_DP_VT_TH_HI_SZ 2
++#define CBR_RG_DP_VT_TH_LO_MSK 0x00000018
++#define CBR_RG_DP_VT_TH_LO_I_MSK 0xffffffe7
++#define CBR_RG_DP_VT_TH_LO_SFT 3
++#define CBR_RG_DP_VT_TH_LO_HI 4
++#define CBR_RG_DP_VT_TH_LO_SZ 2
++#define CBR_RG_DP_VT_MON_TMR_MSK 0x00003fe0
++#define CBR_RG_DP_VT_MON_TMR_I_MSK 0xffffc01f
++#define CBR_RG_DP_VT_MON_TMR_SFT 5
++#define CBR_RG_DP_VT_MON_TMR_HI 13
++#define CBR_RG_DP_VT_MON_TMR_SZ 9
++#define CBR_RG_DP_CK320BY2_MSK 0x00004000
++#define CBR_RG_DP_CK320BY2_I_MSK 0xffffbfff
++#define CBR_RG_DP_CK320BY2_SFT 14
++#define CBR_RG_DP_CK320BY2_HI 14
++#define CBR_RG_DP_CK320BY2_SZ 1
++#define CBR_RG_SX_DELCTRL_MSK 0x001f8000
++#define CBR_RG_SX_DELCTRL_I_MSK 0xffe07fff
++#define CBR_RG_SX_DELCTRL_SFT 15
++#define CBR_RG_SX_DELCTRL_HI 20
++#define CBR_RG_SX_DELCTRL_SZ 6
++#define CBR_RG_DP_OD_TEST_MSK 0x00200000
++#define CBR_RG_DP_OD_TEST_I_MSK 0xffdfffff
++#define CBR_RG_DP_OD_TEST_SFT 21
++#define CBR_RG_DP_OD_TEST_HI 21
++#define CBR_RG_DP_OD_TEST_SZ 1
++#define CBR_RG_DP_BBPLL_BP_MSK 0x00000001
++#define CBR_RG_DP_BBPLL_BP_I_MSK 0xfffffffe
++#define CBR_RG_DP_BBPLL_BP_SFT 0
++#define CBR_RG_DP_BBPLL_BP_HI 0
++#define CBR_RG_DP_BBPLL_BP_SZ 1
++#define CBR_RG_DP_BBPLL_ICP_MSK 0x00000006
++#define CBR_RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
++#define CBR_RG_DP_BBPLL_ICP_SFT 1
++#define CBR_RG_DP_BBPLL_ICP_HI 2
++#define CBR_RG_DP_BBPLL_ICP_SZ 2
++#define CBR_RG_DP_BBPLL_IDUAL_MSK 0x00000018
++#define CBR_RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
++#define CBR_RG_DP_BBPLL_IDUAL_SFT 3
++#define CBR_RG_DP_BBPLL_IDUAL_HI 4
++#define CBR_RG_DP_BBPLL_IDUAL_SZ 2
++#define CBR_RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
++#define CBR_RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
++#define CBR_RG_DP_BBPLL_OD_TEST_SFT 5
++#define CBR_RG_DP_BBPLL_OD_TEST_HI 8
++#define CBR_RG_DP_BBPLL_OD_TEST_SZ 4
++#define CBR_RG_DP_BBPLL_PD_MSK 0x00000200
++#define CBR_RG_DP_BBPLL_PD_I_MSK 0xfffffdff
++#define CBR_RG_DP_BBPLL_PD_SFT 9
++#define CBR_RG_DP_BBPLL_PD_HI 9
++#define CBR_RG_DP_BBPLL_PD_SZ 1
++#define CBR_RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
++#define CBR_RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
++#define CBR_RG_DP_BBPLL_TESTSEL_SFT 10
++#define CBR_RG_DP_BBPLL_TESTSEL_HI 12
++#define CBR_RG_DP_BBPLL_TESTSEL_SZ 3
++#define CBR_RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
++#define CBR_RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
++#define CBR_RG_DP_BBPLL_PFD_DLY_SFT 13
++#define CBR_RG_DP_BBPLL_PFD_DLY_HI 14
++#define CBR_RG_DP_BBPLL_PFD_DLY_SZ 2
++#define CBR_RG_DP_RP_MSK 0x00038000
++#define CBR_RG_DP_RP_I_MSK 0xfffc7fff
++#define CBR_RG_DP_RP_SFT 15
++#define CBR_RG_DP_RP_HI 17
++#define CBR_RG_DP_RP_SZ 3
++#define CBR_RG_DP_RHP_MSK 0x000c0000
++#define CBR_RG_DP_RHP_I_MSK 0xfff3ffff
++#define CBR_RG_DP_RHP_SFT 18
++#define CBR_RG_DP_RHP_HI 19
++#define CBR_RG_DP_RHP_SZ 2
++#define CBR_RG_DP_DR3_MSK 0x00700000
++#define CBR_RG_DP_DR3_I_MSK 0xff8fffff
++#define CBR_RG_DP_DR3_SFT 20
++#define CBR_RG_DP_DR3_HI 22
++#define CBR_RG_DP_DR3_SZ 3
++#define CBR_RG_DP_DCP_MSK 0x07800000
++#define CBR_RG_DP_DCP_I_MSK 0xf87fffff
++#define CBR_RG_DP_DCP_SFT 23
++#define CBR_RG_DP_DCP_HI 26
++#define CBR_RG_DP_DCP_SZ 4
++#define CBR_RG_DP_DCS_MSK 0x78000000
++#define CBR_RG_DP_DCS_I_MSK 0x87ffffff
++#define CBR_RG_DP_DCS_SFT 27
++#define CBR_RG_DP_DCS_HI 30
++#define CBR_RG_DP_DCS_SZ 4
++#define CBR_RG_DP_FBDIV_MSK 0x00000fff
++#define CBR_RG_DP_FBDIV_I_MSK 0xfffff000
++#define CBR_RG_DP_FBDIV_SFT 0
++#define CBR_RG_DP_FBDIV_HI 11
++#define CBR_RG_DP_FBDIV_SZ 12
++#define CBR_RG_DP_FODIV_MSK 0x003ff000
++#define CBR_RG_DP_FODIV_I_MSK 0xffc00fff
++#define CBR_RG_DP_FODIV_SFT 12
++#define CBR_RG_DP_FODIV_HI 21
++#define CBR_RG_DP_FODIV_SZ 10
++#define CBR_RG_DP_REFDIV_MSK 0xffc00000
++#define CBR_RG_DP_REFDIV_I_MSK 0x003fffff
++#define CBR_RG_DP_REFDIV_SFT 22
++#define CBR_RG_DP_REFDIV_HI 31
++#define CBR_RG_DP_REFDIV_SZ 10
++#define CBR_RG_IDACAI_PGAG15_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG15_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG15_SFT 0
++#define CBR_RG_IDACAI_PGAG15_HI 5
++#define CBR_RG_IDACAI_PGAG15_SZ 6
++#define CBR_RG_IDACAQ_PGAG15_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG15_SFT 6
++#define CBR_RG_IDACAQ_PGAG15_HI 11
++#define CBR_RG_IDACAQ_PGAG15_SZ 6
++#define CBR_RG_IDACAI_PGAG14_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG14_SFT 12
++#define CBR_RG_IDACAI_PGAG14_HI 17
++#define CBR_RG_IDACAI_PGAG14_SZ 6
++#define CBR_RG_IDACAQ_PGAG14_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG14_SFT 18
++#define CBR_RG_IDACAQ_PGAG14_HI 23
++#define CBR_RG_IDACAQ_PGAG14_SZ 6
++#define CBR_RG_IDACAI_PGAG13_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG13_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG13_SFT 0
++#define CBR_RG_IDACAI_PGAG13_HI 5
++#define CBR_RG_IDACAI_PGAG13_SZ 6
++#define CBR_RG_IDACAQ_PGAG13_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG13_SFT 6
++#define CBR_RG_IDACAQ_PGAG13_HI 11
++#define CBR_RG_IDACAQ_PGAG13_SZ 6
++#define CBR_RG_IDACAI_PGAG12_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG12_SFT 12
++#define CBR_RG_IDACAI_PGAG12_HI 17
++#define CBR_RG_IDACAI_PGAG12_SZ 6
++#define CBR_RG_IDACAQ_PGAG12_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG12_SFT 18
++#define CBR_RG_IDACAQ_PGAG12_HI 23
++#define CBR_RG_IDACAQ_PGAG12_SZ 6
++#define CBR_RG_IDACAI_PGAG11_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG11_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG11_SFT 0
++#define CBR_RG_IDACAI_PGAG11_HI 5
++#define CBR_RG_IDACAI_PGAG11_SZ 6
++#define CBR_RG_IDACAQ_PGAG11_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG11_SFT 6
++#define CBR_RG_IDACAQ_PGAG11_HI 11
++#define CBR_RG_IDACAQ_PGAG11_SZ 6
++#define CBR_RG_IDACAI_PGAG10_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG10_SFT 12
++#define CBR_RG_IDACAI_PGAG10_HI 17
++#define CBR_RG_IDACAI_PGAG10_SZ 6
++#define CBR_RG_IDACAQ_PGAG10_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG10_SFT 18
++#define CBR_RG_IDACAQ_PGAG10_HI 23
++#define CBR_RG_IDACAQ_PGAG10_SZ 6
++#define CBR_RG_IDACAI_PGAG9_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG9_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG9_SFT 0
++#define CBR_RG_IDACAI_PGAG9_HI 5
++#define CBR_RG_IDACAI_PGAG9_SZ 6
++#define CBR_RG_IDACAQ_PGAG9_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG9_SFT 6
++#define CBR_RG_IDACAQ_PGAG9_HI 11
++#define CBR_RG_IDACAQ_PGAG9_SZ 6
++#define CBR_RG_IDACAI_PGAG8_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG8_SFT 12
++#define CBR_RG_IDACAI_PGAG8_HI 17
++#define CBR_RG_IDACAI_PGAG8_SZ 6
++#define CBR_RG_IDACAQ_PGAG8_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG8_SFT 18
++#define CBR_RG_IDACAQ_PGAG8_HI 23
++#define CBR_RG_IDACAQ_PGAG8_SZ 6
++#define CBR_RG_IDACAI_PGAG7_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG7_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG7_SFT 0
++#define CBR_RG_IDACAI_PGAG7_HI 5
++#define CBR_RG_IDACAI_PGAG7_SZ 6
++#define CBR_RG_IDACAQ_PGAG7_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG7_SFT 6
++#define CBR_RG_IDACAQ_PGAG7_HI 11
++#define CBR_RG_IDACAQ_PGAG7_SZ 6
++#define CBR_RG_IDACAI_PGAG6_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG6_SFT 12
++#define CBR_RG_IDACAI_PGAG6_HI 17
++#define CBR_RG_IDACAI_PGAG6_SZ 6
++#define CBR_RG_IDACAQ_PGAG6_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG6_SFT 18
++#define CBR_RG_IDACAQ_PGAG6_HI 23
++#define CBR_RG_IDACAQ_PGAG6_SZ 6
++#define CBR_RG_IDACAI_PGAG5_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG5_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG5_SFT 0
++#define CBR_RG_IDACAI_PGAG5_HI 5
++#define CBR_RG_IDACAI_PGAG5_SZ 6
++#define CBR_RG_IDACAQ_PGAG5_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG5_SFT 6
++#define CBR_RG_IDACAQ_PGAG5_HI 11
++#define CBR_RG_IDACAQ_PGAG5_SZ 6
++#define CBR_RG_IDACAI_PGAG4_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG4_SFT 12
++#define CBR_RG_IDACAI_PGAG4_HI 17
++#define CBR_RG_IDACAI_PGAG4_SZ 6
++#define CBR_RG_IDACAQ_PGAG4_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG4_SFT 18
++#define CBR_RG_IDACAQ_PGAG4_HI 23
++#define CBR_RG_IDACAQ_PGAG4_SZ 6
++#define CBR_RG_IDACAI_PGAG3_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG3_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG3_SFT 0
++#define CBR_RG_IDACAI_PGAG3_HI 5
++#define CBR_RG_IDACAI_PGAG3_SZ 6
++#define CBR_RG_IDACAQ_PGAG3_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG3_SFT 6
++#define CBR_RG_IDACAQ_PGAG3_HI 11
++#define CBR_RG_IDACAQ_PGAG3_SZ 6
++#define CBR_RG_IDACAI_PGAG2_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG2_SFT 12
++#define CBR_RG_IDACAI_PGAG2_HI 17
++#define CBR_RG_IDACAI_PGAG2_SZ 6
++#define CBR_RG_IDACAQ_PGAG2_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG2_SFT 18
++#define CBR_RG_IDACAQ_PGAG2_HI 23
++#define CBR_RG_IDACAQ_PGAG2_SZ 6
++#define CBR_RG_IDACAI_PGAG1_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG1_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG1_SFT 0
++#define CBR_RG_IDACAI_PGAG1_HI 5
++#define CBR_RG_IDACAI_PGAG1_SZ 6
++#define CBR_RG_IDACAQ_PGAG1_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG1_SFT 6
++#define CBR_RG_IDACAQ_PGAG1_HI 11
++#define CBR_RG_IDACAQ_PGAG1_SZ 6
++#define CBR_RG_IDACAI_PGAG0_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG0_SFT 12
++#define CBR_RG_IDACAI_PGAG0_HI 17
++#define CBR_RG_IDACAI_PGAG0_SZ 6
++#define CBR_RG_IDACAQ_PGAG0_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG0_SFT 18
++#define CBR_RG_IDACAQ_PGAG0_HI 23
++#define CBR_RG_IDACAQ_PGAG0_SZ 6
++#define CBR_RG_EN_RCAL_MSK 0x00000001
++#define CBR_RG_EN_RCAL_I_MSK 0xfffffffe
++#define CBR_RG_EN_RCAL_SFT 0
++#define CBR_RG_EN_RCAL_HI 0
++#define CBR_RG_EN_RCAL_SZ 1
++#define CBR_RG_RCAL_SPD_MSK 0x00000002
++#define CBR_RG_RCAL_SPD_I_MSK 0xfffffffd
++#define CBR_RG_RCAL_SPD_SFT 1
++#define CBR_RG_RCAL_SPD_HI 1
++#define CBR_RG_RCAL_SPD_SZ 1
++#define CBR_RG_RCAL_TMR_MSK 0x000001fc
++#define CBR_RG_RCAL_TMR_I_MSK 0xfffffe03
++#define CBR_RG_RCAL_TMR_SFT 2
++#define CBR_RG_RCAL_TMR_HI 8
++#define CBR_RG_RCAL_TMR_SZ 7
++#define CBR_RG_RCAL_CODE_CWR_MSK 0x00000200
++#define CBR_RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
++#define CBR_RG_RCAL_CODE_CWR_SFT 9
++#define CBR_RG_RCAL_CODE_CWR_HI 9
++#define CBR_RG_RCAL_CODE_CWR_SZ 1
++#define CBR_RG_RCAL_CODE_CWD_MSK 0x00007c00
++#define CBR_RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
++#define CBR_RG_RCAL_CODE_CWD_SFT 10
++#define CBR_RG_RCAL_CODE_CWD_HI 14
++#define CBR_RG_RCAL_CODE_CWD_SZ 5
++#define CBR_RG_SX_SUB_SEL_CWR_MSK 0x00000001
++#define CBR_RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
++#define CBR_RG_SX_SUB_SEL_CWR_SFT 0
++#define CBR_RG_SX_SUB_SEL_CWR_HI 0
++#define CBR_RG_SX_SUB_SEL_CWR_SZ 1
++#define CBR_RG_SX_SUB_SEL_CWD_MSK 0x000000fe
++#define CBR_RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
++#define CBR_RG_SX_SUB_SEL_CWD_SFT 1
++#define CBR_RG_SX_SUB_SEL_CWD_HI 7
++#define CBR_RG_SX_SUB_SEL_CWD_SZ 7
++#define CBR_RG_DP_BBPLL_BS_CWR_MSK 0x00000100
++#define CBR_RG_DP_BBPLL_BS_CWR_I_MSK 0xfffffeff
++#define CBR_RG_DP_BBPLL_BS_CWR_SFT 8
++#define CBR_RG_DP_BBPLL_BS_CWR_HI 8
++#define CBR_RG_DP_BBPLL_BS_CWR_SZ 1
++#define CBR_RG_DP_BBPLL_BS_CWD_MSK 0x00007e00
++#define CBR_RG_DP_BBPLL_BS_CWD_I_MSK 0xffff81ff
++#define CBR_RG_DP_BBPLL_BS_CWD_SFT 9
++#define CBR_RG_DP_BBPLL_BS_CWD_HI 14
++#define CBR_RG_DP_BBPLL_BS_CWD_SZ 6
++#define CBR_RCAL_RDY_MSK 0x00000001
++#define CBR_RCAL_RDY_I_MSK 0xfffffffe
++#define CBR_RCAL_RDY_SFT 0
++#define CBR_RCAL_RDY_HI 0
++#define CBR_RCAL_RDY_SZ 1
++#define CBR_DA_LCK_RDY_MSK 0x00000002
++#define CBR_DA_LCK_RDY_I_MSK 0xfffffffd
++#define CBR_DA_LCK_RDY_SFT 1
++#define CBR_DA_LCK_RDY_HI 1
++#define CBR_DA_LCK_RDY_SZ 1
++#define CBR_VT_MON_RDY_MSK 0x00000004
++#define CBR_VT_MON_RDY_I_MSK 0xfffffffb
++#define CBR_VT_MON_RDY_SFT 2
++#define CBR_VT_MON_RDY_HI 2
++#define CBR_VT_MON_RDY_SZ 1
++#define CBR_DP_VT_MON_RDY_MSK 0x00000008
++#define CBR_DP_VT_MON_RDY_I_MSK 0xfffffff7
++#define CBR_DP_VT_MON_RDY_SFT 3
++#define CBR_DP_VT_MON_RDY_HI 3
++#define CBR_DP_VT_MON_RDY_SZ 1
++#define CBR_CH_RDY_MSK 0x00000010
++#define CBR_CH_RDY_I_MSK 0xffffffef
++#define CBR_CH_RDY_SFT 4
++#define CBR_CH_RDY_HI 4
++#define CBR_CH_RDY_SZ 1
++#define CBR_DA_R_CODE_LUT_MSK 0x000007c0
++#define CBR_DA_R_CODE_LUT_I_MSK 0xfffff83f
++#define CBR_DA_R_CODE_LUT_SFT 6
++#define CBR_DA_R_CODE_LUT_HI 10
++#define CBR_DA_R_CODE_LUT_SZ 5
++#define CBR_AD_SX_VT_MON_Q_MSK 0x00001800
++#define CBR_AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
++#define CBR_AD_SX_VT_MON_Q_SFT 11
++#define CBR_AD_SX_VT_MON_Q_HI 12
++#define CBR_AD_SX_VT_MON_Q_SZ 2
++#define CBR_AD_DP_VT_MON_Q_MSK 0x00006000
++#define CBR_AD_DP_VT_MON_Q_I_MSK 0xffff9fff
++#define CBR_AD_DP_VT_MON_Q_SFT 13
++#define CBR_AD_DP_VT_MON_Q_HI 14
++#define CBR_AD_DP_VT_MON_Q_SZ 2
++#define CBR_DA_R_CAL_CODE_MSK 0x0000001f
++#define CBR_DA_R_CAL_CODE_I_MSK 0xffffffe0
++#define CBR_DA_R_CAL_CODE_SFT 0
++#define CBR_DA_R_CAL_CODE_HI 4
++#define CBR_DA_R_CAL_CODE_SZ 5
++#define CBR_DA_SX_SUB_SEL_MSK 0x00000fe0
++#define CBR_DA_SX_SUB_SEL_I_MSK 0xfffff01f
++#define CBR_DA_SX_SUB_SEL_SFT 5
++#define CBR_DA_SX_SUB_SEL_HI 11
++#define CBR_DA_SX_SUB_SEL_SZ 7
++#define CBR_DA_DP_BBPLL_BS_MSK 0x0003f000
++#define CBR_DA_DP_BBPLL_BS_I_MSK 0xfffc0fff
++#define CBR_DA_DP_BBPLL_BS_SFT 12
++#define CBR_DA_DP_BBPLL_BS_HI 17
++#define CBR_DA_DP_BBPLL_BS_SZ 6
++#define CBR_TX_EN_MSK 0x00000001
++#define CBR_TX_EN_I_MSK 0xfffffffe
++#define CBR_TX_EN_SFT 0
++#define CBR_TX_EN_HI 0
++#define CBR_TX_EN_SZ 1
++#define CBR_TX_CNT_RST_MSK 0x00000002
++#define CBR_TX_CNT_RST_I_MSK 0xfffffffd
++#define CBR_TX_CNT_RST_SFT 1
++#define CBR_TX_CNT_RST_HI 1
++#define CBR_TX_CNT_RST_SZ 1
++#define CBR_IFS_TIME_MSK 0x000000fc
++#define CBR_IFS_TIME_I_MSK 0xffffff03
++#define CBR_IFS_TIME_SFT 2
++#define CBR_IFS_TIME_HI 7
++#define CBR_IFS_TIME_SZ 6
++#define CBR_LENGTH_TARGET_MSK 0x000fff00
++#define CBR_LENGTH_TARGET_I_MSK 0xfff000ff
++#define CBR_LENGTH_TARGET_SFT 8
++#define CBR_LENGTH_TARGET_HI 19
++#define CBR_LENGTH_TARGET_SZ 12
++#define CBR_TX_CNT_TARGET_MSK 0xff000000
++#define CBR_TX_CNT_TARGET_I_MSK 0x00ffffff
++#define CBR_TX_CNT_TARGET_SFT 24
++#define CBR_TX_CNT_TARGET_HI 31
++#define CBR_TX_CNT_TARGET_SZ 8
++#define CBR_TC_CNT_TARGET_MSK 0x00ffffff
++#define CBR_TC_CNT_TARGET_I_MSK 0xff000000
++#define CBR_TC_CNT_TARGET_SFT 0
++#define CBR_TC_CNT_TARGET_HI 23
++#define CBR_TC_CNT_TARGET_SZ 24
++#define CBR_PLCP_PSDU_DATA_MEM_MSK 0x000000ff
++#define CBR_PLCP_PSDU_DATA_MEM_I_MSK 0xffffff00
++#define CBR_PLCP_PSDU_DATA_MEM_SFT 0
++#define CBR_PLCP_PSDU_DATA_MEM_HI 7
++#define CBR_PLCP_PSDU_DATA_MEM_SZ 8
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK 0x00000100
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK 0xfffffeff
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT 8
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_HI 8
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ 1
++#define CBR_PLCP_BYTE_LENGTH_MSK 0x001ffe00
++#define CBR_PLCP_BYTE_LENGTH_I_MSK 0xffe001ff
++#define CBR_PLCP_BYTE_LENGTH_SFT 9
++#define CBR_PLCP_BYTE_LENGTH_HI 20
++#define CBR_PLCP_BYTE_LENGTH_SZ 12
++#define CBR_PLCP_PSDU_RATE_MSK 0x00600000
++#define CBR_PLCP_PSDU_RATE_I_MSK 0xff9fffff
++#define CBR_PLCP_PSDU_RATE_SFT 21
++#define CBR_PLCP_PSDU_RATE_HI 22
++#define CBR_PLCP_PSDU_RATE_SZ 2
++#define CBR_TAIL_TIME_MSK 0x1f800000
++#define CBR_TAIL_TIME_I_MSK 0xe07fffff
++#define CBR_TAIL_TIME_SFT 23
++#define CBR_TAIL_TIME_HI 28
++#define CBR_TAIL_TIME_SZ 6
++#define CBR_RG_O_PAD_PD_MSK 0x00000001
++#define CBR_RG_O_PAD_PD_I_MSK 0xfffffffe
++#define CBR_RG_O_PAD_PD_SFT 0
++#define CBR_RG_O_PAD_PD_HI 0
++#define CBR_RG_O_PAD_PD_SZ 1
++#define CBR_RG_I_PAD_PD_MSK 0x00000002
++#define CBR_RG_I_PAD_PD_I_MSK 0xfffffffd
++#define CBR_RG_I_PAD_PD_SFT 1
++#define CBR_RG_I_PAD_PD_HI 1
++#define CBR_RG_I_PAD_PD_SZ 1
++#define CBR_SEL_ADCKP_INV_MSK 0x00000004
++#define CBR_SEL_ADCKP_INV_I_MSK 0xfffffffb
++#define CBR_SEL_ADCKP_INV_SFT 2
++#define CBR_SEL_ADCKP_INV_HI 2
++#define CBR_SEL_ADCKP_INV_SZ 1
++#define CBR_RG_PAD_DS_MSK 0x00000008
++#define CBR_RG_PAD_DS_I_MSK 0xfffffff7
++#define CBR_RG_PAD_DS_SFT 3
++#define CBR_RG_PAD_DS_HI 3
++#define CBR_RG_PAD_DS_SZ 1
++#define CBR_SEL_ADCKP_MUX_MSK 0x00000010
++#define CBR_SEL_ADCKP_MUX_I_MSK 0xffffffef
++#define CBR_SEL_ADCKP_MUX_SFT 4
++#define CBR_SEL_ADCKP_MUX_HI 4
++#define CBR_SEL_ADCKP_MUX_SZ 1
++#define CBR_RG_PAD_DS_CLK_MSK 0x00000020
++#define CBR_RG_PAD_DS_CLK_I_MSK 0xffffffdf
++#define CBR_RG_PAD_DS_CLK_SFT 5
++#define CBR_RG_PAD_DS_CLK_HI 5
++#define CBR_RG_PAD_DS_CLK_SZ 1
++#define CBR_INTP_SEL_MSK 0x00000200
++#define CBR_INTP_SEL_I_MSK 0xfffffdff
++#define CBR_INTP_SEL_SFT 9
++#define CBR_INTP_SEL_HI 9
++#define CBR_INTP_SEL_SZ 1
++#define CBR_IQ_SWP_MSK 0x00000400
++#define CBR_IQ_SWP_I_MSK 0xfffffbff
++#define CBR_IQ_SWP_SFT 10
++#define CBR_IQ_SWP_HI 10
++#define CBR_IQ_SWP_SZ 1
++#define CBR_RG_EN_EXT_DA_MSK 0x00000800
++#define CBR_RG_EN_EXT_DA_I_MSK 0xfffff7ff
++#define CBR_RG_EN_EXT_DA_SFT 11
++#define CBR_RG_EN_EXT_DA_HI 11
++#define CBR_RG_EN_EXT_DA_SZ 1
++#define CBR_RG_DIS_DA_OFFSET_MSK 0x00001000
++#define CBR_RG_DIS_DA_OFFSET_I_MSK 0xffffefff
++#define CBR_RG_DIS_DA_OFFSET_SFT 12
++#define CBR_RG_DIS_DA_OFFSET_HI 12
++#define CBR_RG_DIS_DA_OFFSET_SZ 1
++#define CBR_DBG_SEL_MSK 0x000f0000
++#define CBR_DBG_SEL_I_MSK 0xfff0ffff
++#define CBR_DBG_SEL_SFT 16
++#define CBR_DBG_SEL_HI 19
++#define CBR_DBG_SEL_SZ 4
++#define CBR_DBG_EN_MSK 0x00100000
++#define CBR_DBG_EN_I_MSK 0xffefffff
++#define CBR_DBG_EN_SFT 20
++#define CBR_DBG_EN_HI 20
++#define CBR_DBG_EN_SZ 1
++#define CBR_RG_PKT_GEN_TX_CNT_MSK 0xffffffff
++#define CBR_RG_PKT_GEN_TX_CNT_I_MSK 0x00000000
++#define CBR_RG_PKT_GEN_TX_CNT_SFT 0
++#define CBR_RG_PKT_GEN_TX_CNT_HI 31
++#define CBR_RG_PKT_GEN_TX_CNT_SZ 32
++#define CBR_TP_SEL_MSK 0x0000001f
++#define CBR_TP_SEL_I_MSK 0xffffffe0
++#define CBR_TP_SEL_SFT 0
++#define CBR_TP_SEL_HI 4
++#define CBR_TP_SEL_SZ 5
++#define CBR_IDEAL_IQ_EN_MSK 0x00000020
++#define CBR_IDEAL_IQ_EN_I_MSK 0xffffffdf
++#define CBR_IDEAL_IQ_EN_SFT 5
++#define CBR_IDEAL_IQ_EN_HI 5
++#define CBR_IDEAL_IQ_EN_SZ 1
++#define CBR_DATA_OUT_SEL_MSK 0x000001c0
++#define CBR_DATA_OUT_SEL_I_MSK 0xfffffe3f
++#define CBR_DATA_OUT_SEL_SFT 6
++#define CBR_DATA_OUT_SEL_HI 8
++#define CBR_DATA_OUT_SEL_SZ 3
++#define CBR_TWO_TONE_EN_MSK 0x00000200
++#define CBR_TWO_TONE_EN_I_MSK 0xfffffdff
++#define CBR_TWO_TONE_EN_SFT 9
++#define CBR_TWO_TONE_EN_HI 9
++#define CBR_TWO_TONE_EN_SZ 1
++#define CBR_FREQ_SEL_MSK 0x00ff0000
++#define CBR_FREQ_SEL_I_MSK 0xff00ffff
++#define CBR_FREQ_SEL_SFT 16
++#define CBR_FREQ_SEL_HI 23
++#define CBR_FREQ_SEL_SZ 8
++#define CBR_IQ_SCALE_MSK 0xff000000
++#define CBR_IQ_SCALE_I_MSK 0x00ffffff
++#define CBR_IQ_SCALE_SFT 24
++#define CBR_IQ_SCALE_HI 31
++#define CBR_IQ_SCALE_SZ 8
++#define CPU_QUE_POP_MSK 0x00000001
++#define CPU_QUE_POP_I_MSK 0xfffffffe
++#define CPU_QUE_POP_SFT 0
++#define CPU_QUE_POP_HI 0
++#define CPU_QUE_POP_SZ 1
++#define CPU_INT_MSK 0x00000004
++#define CPU_INT_I_MSK 0xfffffffb
++#define CPU_INT_SFT 2
++#define CPU_INT_HI 2
++#define CPU_INT_SZ 1
++#define CPU_ID_TB0_MSK 0xffffffff
++#define CPU_ID_TB0_I_MSK 0x00000000
++#define CPU_ID_TB0_SFT 0
++#define CPU_ID_TB0_HI 31
++#define CPU_ID_TB0_SZ 32
++#define CPU_ID_TB1_MSK 0xffffffff
++#define CPU_ID_TB1_I_MSK 0x00000000
++#define CPU_ID_TB1_SFT 0
++#define CPU_ID_TB1_HI 31
++#define CPU_ID_TB1_SZ 32
++#define HW_PKTID_MSK 0x000007ff
++#define HW_PKTID_I_MSK 0xfffff800
++#define HW_PKTID_SFT 0
++#define HW_PKTID_HI 10
++#define HW_PKTID_SZ 11
++#define CH0_INT_ADDR_MSK 0xffffffff
++#define CH0_INT_ADDR_I_MSK 0x00000000
++#define CH0_INT_ADDR_SFT 0
++#define CH0_INT_ADDR_HI 31
++#define CH0_INT_ADDR_SZ 32
++#define PRI_HW_PKTID_MSK 0x000007ff
++#define PRI_HW_PKTID_I_MSK 0xfffff800
++#define PRI_HW_PKTID_SFT 0
++#define PRI_HW_PKTID_HI 10
++#define PRI_HW_PKTID_SZ 11
++#define CH0_FULL_MSK 0x00000001
++#define CH0_FULL_I_MSK 0xfffffffe
++#define CH0_FULL_SFT 0
++#define CH0_FULL_HI 0
++#define CH0_FULL_SZ 1
++#define FF0_EMPTY_MSK 0x00000002
++#define FF0_EMPTY_I_MSK 0xfffffffd
++#define FF0_EMPTY_SFT 1
++#define FF0_EMPTY_HI 1
++#define FF0_EMPTY_SZ 1
++#define RLS_BUSY_MSK 0x00000200
++#define RLS_BUSY_I_MSK 0xfffffdff
++#define RLS_BUSY_SFT 9
++#define RLS_BUSY_HI 9
++#define RLS_BUSY_SZ 1
++#define RLS_COUNT_CLR_MSK 0x00000400
++#define RLS_COUNT_CLR_I_MSK 0xfffffbff
++#define RLS_COUNT_CLR_SFT 10
++#define RLS_COUNT_CLR_HI 10
++#define RLS_COUNT_CLR_SZ 1
++#define RTN_COUNT_CLR_MSK 0x00000800
++#define RTN_COUNT_CLR_I_MSK 0xfffff7ff
++#define RTN_COUNT_CLR_SFT 11
++#define RTN_COUNT_CLR_HI 11
++#define RTN_COUNT_CLR_SZ 1
++#define RLS_COUNT_MSK 0x00ff0000
++#define RLS_COUNT_I_MSK 0xff00ffff
++#define RLS_COUNT_SFT 16
++#define RLS_COUNT_HI 23
++#define RLS_COUNT_SZ 8
++#define RTN_COUNT_MSK 0xff000000
++#define RTN_COUNT_I_MSK 0x00ffffff
++#define RTN_COUNT_SFT 24
++#define RTN_COUNT_HI 31
++#define RTN_COUNT_SZ 8
++#define FF0_CNT_MSK 0x0000001f
++#define FF0_CNT_I_MSK 0xffffffe0
++#define FF0_CNT_SFT 0
++#define FF0_CNT_HI 4
++#define FF0_CNT_SZ 5
++#define FF1_CNT_MSK 0x000001e0
++#define FF1_CNT_I_MSK 0xfffffe1f
++#define FF1_CNT_SFT 5
++#define FF1_CNT_HI 8
++#define FF1_CNT_SZ 4
++#define FF3_CNT_MSK 0x00003800
++#define FF3_CNT_I_MSK 0xffffc7ff
++#define FF3_CNT_SFT 11
++#define FF3_CNT_HI 13
++#define FF3_CNT_SZ 3
++#define FF5_CNT_MSK 0x000e0000
++#define FF5_CNT_I_MSK 0xfff1ffff
++#define FF5_CNT_SFT 17
++#define FF5_CNT_HI 19
++#define FF5_CNT_SZ 3
++#define FF6_CNT_MSK 0x00700000
++#define FF6_CNT_I_MSK 0xff8fffff
++#define FF6_CNT_SFT 20
++#define FF6_CNT_HI 22
++#define FF6_CNT_SZ 3
++#define FF7_CNT_MSK 0x03800000
++#define FF7_CNT_I_MSK 0xfc7fffff
++#define FF7_CNT_SFT 23
++#define FF7_CNT_HI 25
++#define FF7_CNT_SZ 3
++#define FF8_CNT_MSK 0x1c000000
++#define FF8_CNT_I_MSK 0xe3ffffff
++#define FF8_CNT_SFT 26
++#define FF8_CNT_HI 28
++#define FF8_CNT_SZ 3
++#define FF9_CNT_MSK 0xe0000000
++#define FF9_CNT_I_MSK 0x1fffffff
++#define FF9_CNT_SFT 29
++#define FF9_CNT_HI 31
++#define FF9_CNT_SZ 3
++#define FF10_CNT_MSK 0x00000007
++#define FF10_CNT_I_MSK 0xfffffff8
++#define FF10_CNT_SFT 0
++#define FF10_CNT_HI 2
++#define FF10_CNT_SZ 3
++#define FF11_CNT_MSK 0x00000038
++#define FF11_CNT_I_MSK 0xffffffc7
++#define FF11_CNT_SFT 3
++#define FF11_CNT_HI 5
++#define FF11_CNT_SZ 3
++#define FF12_CNT_MSK 0x000001c0
++#define FF12_CNT_I_MSK 0xfffffe3f
++#define FF12_CNT_SFT 6
++#define FF12_CNT_HI 8
++#define FF12_CNT_SZ 3
++#define FF13_CNT_MSK 0x00000600
++#define FF13_CNT_I_MSK 0xfffff9ff
++#define FF13_CNT_SFT 9
++#define FF13_CNT_HI 10
++#define FF13_CNT_SZ 2
++#define FF14_CNT_MSK 0x00001800
++#define FF14_CNT_I_MSK 0xffffe7ff
++#define FF14_CNT_SFT 11
++#define FF14_CNT_HI 12
++#define FF14_CNT_SZ 2
++#define FF15_CNT_MSK 0x00006000
++#define FF15_CNT_I_MSK 0xffff9fff
++#define FF15_CNT_SFT 13
++#define FF15_CNT_HI 14
++#define FF15_CNT_SZ 2
++#define FF4_CNT_MSK 0x000f8000
++#define FF4_CNT_I_MSK 0xfff07fff
++#define FF4_CNT_SFT 15
++#define FF4_CNT_HI 19
++#define FF4_CNT_SZ 5
++#define FF2_CNT_MSK 0x00700000
++#define FF2_CNT_I_MSK 0xff8fffff
++#define FF2_CNT_SFT 20
++#define FF2_CNT_HI 22
++#define FF2_CNT_SZ 3
++#define CH1_FULL_MSK 0x00000002
++#define CH1_FULL_I_MSK 0xfffffffd
++#define CH1_FULL_SFT 1
++#define CH1_FULL_HI 1
++#define CH1_FULL_SZ 1
++#define CH2_FULL_MSK 0x00000004
++#define CH2_FULL_I_MSK 0xfffffffb
++#define CH2_FULL_SFT 2
++#define CH2_FULL_HI 2
++#define CH2_FULL_SZ 1
++#define CH3_FULL_MSK 0x00000008
++#define CH3_FULL_I_MSK 0xfffffff7
++#define CH3_FULL_SFT 3
++#define CH3_FULL_HI 3
++#define CH3_FULL_SZ 1
++#define CH4_FULL_MSK 0x00000010
++#define CH4_FULL_I_MSK 0xffffffef
++#define CH4_FULL_SFT 4
++#define CH4_FULL_HI 4
++#define CH4_FULL_SZ 1
++#define CH5_FULL_MSK 0x00000020
++#define CH5_FULL_I_MSK 0xffffffdf
++#define CH5_FULL_SFT 5
++#define CH5_FULL_HI 5
++#define CH5_FULL_SZ 1
++#define CH6_FULL_MSK 0x00000040
++#define CH6_FULL_I_MSK 0xffffffbf
++#define CH6_FULL_SFT 6
++#define CH6_FULL_HI 6
++#define CH6_FULL_SZ 1
++#define CH7_FULL_MSK 0x00000080
++#define CH7_FULL_I_MSK 0xffffff7f
++#define CH7_FULL_SFT 7
++#define CH7_FULL_HI 7
++#define CH7_FULL_SZ 1
++#define CH8_FULL_MSK 0x00000100
++#define CH8_FULL_I_MSK 0xfffffeff
++#define CH8_FULL_SFT 8
++#define CH8_FULL_HI 8
++#define CH8_FULL_SZ 1
++#define CH9_FULL_MSK 0x00000200
++#define CH9_FULL_I_MSK 0xfffffdff
++#define CH9_FULL_SFT 9
++#define CH9_FULL_HI 9
++#define CH9_FULL_SZ 1
++#define CH10_FULL_MSK 0x00000400
++#define CH10_FULL_I_MSK 0xfffffbff
++#define CH10_FULL_SFT 10
++#define CH10_FULL_HI 10
++#define CH10_FULL_SZ 1
++#define CH11_FULL_MSK 0x00000800
++#define CH11_FULL_I_MSK 0xfffff7ff
++#define CH11_FULL_SFT 11
++#define CH11_FULL_HI 11
++#define CH11_FULL_SZ 1
++#define CH12_FULL_MSK 0x00001000
++#define CH12_FULL_I_MSK 0xffffefff
++#define CH12_FULL_SFT 12
++#define CH12_FULL_HI 12
++#define CH12_FULL_SZ 1
++#define CH13_FULL_MSK 0x00002000
++#define CH13_FULL_I_MSK 0xffffdfff
++#define CH13_FULL_SFT 13
++#define CH13_FULL_HI 13
++#define CH13_FULL_SZ 1
++#define CH14_FULL_MSK 0x00004000
++#define CH14_FULL_I_MSK 0xffffbfff
++#define CH14_FULL_SFT 14
++#define CH14_FULL_HI 14
++#define CH14_FULL_SZ 1
++#define CH15_FULL_MSK 0x00008000
++#define CH15_FULL_I_MSK 0xffff7fff
++#define CH15_FULL_SFT 15
++#define CH15_FULL_HI 15
++#define CH15_FULL_SZ 1
++#define HALT_CH0_MSK 0x00000001
++#define HALT_CH0_I_MSK 0xfffffffe
++#define HALT_CH0_SFT 0
++#define HALT_CH0_HI 0
++#define HALT_CH0_SZ 1
++#define HALT_CH1_MSK 0x00000002
++#define HALT_CH1_I_MSK 0xfffffffd
++#define HALT_CH1_SFT 1
++#define HALT_CH1_HI 1
++#define HALT_CH1_SZ 1
++#define HALT_CH2_MSK 0x00000004
++#define HALT_CH2_I_MSK 0xfffffffb
++#define HALT_CH2_SFT 2
++#define HALT_CH2_HI 2
++#define HALT_CH2_SZ 1
++#define HALT_CH3_MSK 0x00000008
++#define HALT_CH3_I_MSK 0xfffffff7
++#define HALT_CH3_SFT 3
++#define HALT_CH3_HI 3
++#define HALT_CH3_SZ 1
++#define HALT_CH4_MSK 0x00000010
++#define HALT_CH4_I_MSK 0xffffffef
++#define HALT_CH4_SFT 4
++#define HALT_CH4_HI 4
++#define HALT_CH4_SZ 1
++#define HALT_CH5_MSK 0x00000020
++#define HALT_CH5_I_MSK 0xffffffdf
++#define HALT_CH5_SFT 5
++#define HALT_CH5_HI 5
++#define HALT_CH5_SZ 1
++#define HALT_CH6_MSK 0x00000040
++#define HALT_CH6_I_MSK 0xffffffbf
++#define HALT_CH6_SFT 6
++#define HALT_CH6_HI 6
++#define HALT_CH6_SZ 1
++#define HALT_CH7_MSK 0x00000080
++#define HALT_CH7_I_MSK 0xffffff7f
++#define HALT_CH7_SFT 7
++#define HALT_CH7_HI 7
++#define HALT_CH7_SZ 1
++#define HALT_CH8_MSK 0x00000100
++#define HALT_CH8_I_MSK 0xfffffeff
++#define HALT_CH8_SFT 8
++#define HALT_CH8_HI 8
++#define HALT_CH8_SZ 1
++#define HALT_CH9_MSK 0x00000200
++#define HALT_CH9_I_MSK 0xfffffdff
++#define HALT_CH9_SFT 9
++#define HALT_CH9_HI 9
++#define HALT_CH9_SZ 1
++#define HALT_CH10_MSK 0x00000400
++#define HALT_CH10_I_MSK 0xfffffbff
++#define HALT_CH10_SFT 10
++#define HALT_CH10_HI 10
++#define HALT_CH10_SZ 1
++#define HALT_CH11_MSK 0x00000800
++#define HALT_CH11_I_MSK 0xfffff7ff
++#define HALT_CH11_SFT 11
++#define HALT_CH11_HI 11
++#define HALT_CH11_SZ 1
++#define HALT_CH12_MSK 0x00001000
++#define HALT_CH12_I_MSK 0xffffefff
++#define HALT_CH12_SFT 12
++#define HALT_CH12_HI 12
++#define HALT_CH12_SZ 1
++#define HALT_CH13_MSK 0x00002000
++#define HALT_CH13_I_MSK 0xffffdfff
++#define HALT_CH13_SFT 13
++#define HALT_CH13_HI 13
++#define HALT_CH13_SZ 1
++#define HALT_CH14_MSK 0x00004000
++#define HALT_CH14_I_MSK 0xffffbfff
++#define HALT_CH14_SFT 14
++#define HALT_CH14_HI 14
++#define HALT_CH14_SZ 1
++#define HALT_CH15_MSK 0x00008000
++#define HALT_CH15_I_MSK 0xffff7fff
++#define HALT_CH15_SFT 15
++#define HALT_CH15_HI 15
++#define HALT_CH15_SZ 1
++#define STOP_MBOX_MSK 0x00010000
++#define STOP_MBOX_I_MSK 0xfffeffff
++#define STOP_MBOX_SFT 16
++#define STOP_MBOX_HI 16
++#define STOP_MBOX_SZ 1
++#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000
++#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff
++#define MB_ERR_AUTO_HALT_EN_SFT 20
++#define MB_ERR_AUTO_HALT_EN_HI 20
++#define MB_ERR_AUTO_HALT_EN_SZ 1
++#define MB_EXCEPT_CLR_MSK 0x00200000
++#define MB_EXCEPT_CLR_I_MSK 0xffdfffff
++#define MB_EXCEPT_CLR_SFT 21
++#define MB_EXCEPT_CLR_HI 21
++#define MB_EXCEPT_CLR_SZ 1
++#define MB_EXCEPT_CASE_MSK 0xff000000
++#define MB_EXCEPT_CASE_I_MSK 0x00ffffff
++#define MB_EXCEPT_CASE_SFT 24
++#define MB_EXCEPT_CASE_HI 31
++#define MB_EXCEPT_CASE_SZ 8
++#define MB_DBG_TIME_STEP_MSK 0x0000ffff
++#define MB_DBG_TIME_STEP_I_MSK 0xffff0000
++#define MB_DBG_TIME_STEP_SFT 0
++#define MB_DBG_TIME_STEP_HI 15
++#define MB_DBG_TIME_STEP_SZ 16
++#define DBG_TYPE_MSK 0x00030000
++#define DBG_TYPE_I_MSK 0xfffcffff
++#define DBG_TYPE_SFT 16
++#define DBG_TYPE_HI 17
++#define DBG_TYPE_SZ 2
++#define MB_DBG_CLR_MSK 0x00040000
++#define MB_DBG_CLR_I_MSK 0xfffbffff
++#define MB_DBG_CLR_SFT 18
++#define MB_DBG_CLR_HI 18
++#define MB_DBG_CLR_SZ 1
++#define DBG_ALC_LOG_EN_MSK 0x00080000
++#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff
++#define DBG_ALC_LOG_EN_SFT 19
++#define DBG_ALC_LOG_EN_HI 19
++#define DBG_ALC_LOG_EN_SZ 1
++#define MB_DBG_COUNTER_EN_MSK 0x01000000
++#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff
++#define MB_DBG_COUNTER_EN_SFT 24
++#define MB_DBG_COUNTER_EN_HI 24
++#define MB_DBG_COUNTER_EN_SZ 1
++#define MB_DBG_EN_MSK 0x80000000
++#define MB_DBG_EN_I_MSK 0x7fffffff
++#define MB_DBG_EN_SFT 31
++#define MB_DBG_EN_HI 31
++#define MB_DBG_EN_SZ 1
++#define MB_DBG_RECORD_CNT_MSK 0x0000ffff
++#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000
++#define MB_DBG_RECORD_CNT_SFT 0
++#define MB_DBG_RECORD_CNT_HI 15
++#define MB_DBG_RECORD_CNT_SZ 16
++#define MB_DBG_LENGTH_MSK 0xffff0000
++#define MB_DBG_LENGTH_I_MSK 0x0000ffff
++#define MB_DBG_LENGTH_SFT 16
++#define MB_DBG_LENGTH_HI 31
++#define MB_DBG_LENGTH_SZ 16
++#define MB_DBG_CFG_ADDR_MSK 0xffffffff
++#define MB_DBG_CFG_ADDR_I_MSK 0x00000000
++#define MB_DBG_CFG_ADDR_SFT 0
++#define MB_DBG_CFG_ADDR_HI 31
++#define MB_DBG_CFG_ADDR_SZ 32
++#define DBG_HWID0_WR_EN_MSK 0x00000001
++#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe
++#define DBG_HWID0_WR_EN_SFT 0
++#define DBG_HWID0_WR_EN_HI 0
++#define DBG_HWID0_WR_EN_SZ 1
++#define DBG_HWID1_WR_EN_MSK 0x00000002
++#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd
++#define DBG_HWID1_WR_EN_SFT 1
++#define DBG_HWID1_WR_EN_HI 1
++#define DBG_HWID1_WR_EN_SZ 1
++#define DBG_HWID2_WR_EN_MSK 0x00000004
++#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb
++#define DBG_HWID2_WR_EN_SFT 2
++#define DBG_HWID2_WR_EN_HI 2
++#define DBG_HWID2_WR_EN_SZ 1
++#define DBG_HWID3_WR_EN_MSK 0x00000008
++#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7
++#define DBG_HWID3_WR_EN_SFT 3
++#define DBG_HWID3_WR_EN_HI 3
++#define DBG_HWID3_WR_EN_SZ 1
++#define DBG_HWID4_WR_EN_MSK 0x00000010
++#define DBG_HWID4_WR_EN_I_MSK 0xffffffef
++#define DBG_HWID4_WR_EN_SFT 4
++#define DBG_HWID4_WR_EN_HI 4
++#define DBG_HWID4_WR_EN_SZ 1
++#define DBG_HWID5_WR_EN_MSK 0x00000020
++#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf
++#define DBG_HWID5_WR_EN_SFT 5
++#define DBG_HWID5_WR_EN_HI 5
++#define DBG_HWID5_WR_EN_SZ 1
++#define DBG_HWID6_WR_EN_MSK 0x00000040
++#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf
++#define DBG_HWID6_WR_EN_SFT 6
++#define DBG_HWID6_WR_EN_HI 6
++#define DBG_HWID6_WR_EN_SZ 1
++#define DBG_HWID7_WR_EN_MSK 0x00000080
++#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f
++#define DBG_HWID7_WR_EN_SFT 7
++#define DBG_HWID7_WR_EN_HI 7
++#define DBG_HWID7_WR_EN_SZ 1
++#define DBG_HWID8_WR_EN_MSK 0x00000100
++#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff
++#define DBG_HWID8_WR_EN_SFT 8
++#define DBG_HWID8_WR_EN_HI 8
++#define DBG_HWID8_WR_EN_SZ 1
++#define DBG_HWID9_WR_EN_MSK 0x00000200
++#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff
++#define DBG_HWID9_WR_EN_SFT 9
++#define DBG_HWID9_WR_EN_HI 9
++#define DBG_HWID9_WR_EN_SZ 1
++#define DBG_HWID10_WR_EN_MSK 0x00000400
++#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff
++#define DBG_HWID10_WR_EN_SFT 10
++#define DBG_HWID10_WR_EN_HI 10
++#define DBG_HWID10_WR_EN_SZ 1
++#define DBG_HWID11_WR_EN_MSK 0x00000800
++#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff
++#define DBG_HWID11_WR_EN_SFT 11
++#define DBG_HWID11_WR_EN_HI 11
++#define DBG_HWID11_WR_EN_SZ 1
++#define DBG_HWID12_WR_EN_MSK 0x00001000
++#define DBG_HWID12_WR_EN_I_MSK 0xffffefff
++#define DBG_HWID12_WR_EN_SFT 12
++#define DBG_HWID12_WR_EN_HI 12
++#define DBG_HWID12_WR_EN_SZ 1
++#define DBG_HWID13_WR_EN_MSK 0x00002000
++#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff
++#define DBG_HWID13_WR_EN_SFT 13
++#define DBG_HWID13_WR_EN_HI 13
++#define DBG_HWID13_WR_EN_SZ 1
++#define DBG_HWID14_WR_EN_MSK 0x00004000
++#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff
++#define DBG_HWID14_WR_EN_SFT 14
++#define DBG_HWID14_WR_EN_HI 14
++#define DBG_HWID14_WR_EN_SZ 1
++#define DBG_HWID15_WR_EN_MSK 0x00008000
++#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff
++#define DBG_HWID15_WR_EN_SFT 15
++#define DBG_HWID15_WR_EN_HI 15
++#define DBG_HWID15_WR_EN_SZ 1
++#define DBG_HWID0_RD_EN_MSK 0x00010000
++#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff
++#define DBG_HWID0_RD_EN_SFT 16
++#define DBG_HWID0_RD_EN_HI 16
++#define DBG_HWID0_RD_EN_SZ 1
++#define DBG_HWID1_RD_EN_MSK 0x00020000
++#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff
++#define DBG_HWID1_RD_EN_SFT 17
++#define DBG_HWID1_RD_EN_HI 17
++#define DBG_HWID1_RD_EN_SZ 1
++#define DBG_HWID2_RD_EN_MSK 0x00040000
++#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff
++#define DBG_HWID2_RD_EN_SFT 18
++#define DBG_HWID2_RD_EN_HI 18
++#define DBG_HWID2_RD_EN_SZ 1
++#define DBG_HWID3_RD_EN_MSK 0x00080000
++#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff
++#define DBG_HWID3_RD_EN_SFT 19
++#define DBG_HWID3_RD_EN_HI 19
++#define DBG_HWID3_RD_EN_SZ 1
++#define DBG_HWID4_RD_EN_MSK 0x00100000
++#define DBG_HWID4_RD_EN_I_MSK 0xffefffff
++#define DBG_HWID4_RD_EN_SFT 20
++#define DBG_HWID4_RD_EN_HI 20
++#define DBG_HWID4_RD_EN_SZ 1
++#define DBG_HWID5_RD_EN_MSK 0x00200000
++#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff
++#define DBG_HWID5_RD_EN_SFT 21
++#define DBG_HWID5_RD_EN_HI 21
++#define DBG_HWID5_RD_EN_SZ 1
++#define DBG_HWID6_RD_EN_MSK 0x00400000
++#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff
++#define DBG_HWID6_RD_EN_SFT 22
++#define DBG_HWID6_RD_EN_HI 22
++#define DBG_HWID6_RD_EN_SZ 1
++#define DBG_HWID7_RD_EN_MSK 0x00800000
++#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff
++#define DBG_HWID7_RD_EN_SFT 23
++#define DBG_HWID7_RD_EN_HI 23
++#define DBG_HWID7_RD_EN_SZ 1
++#define DBG_HWID8_RD_EN_MSK 0x01000000
++#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff
++#define DBG_HWID8_RD_EN_SFT 24
++#define DBG_HWID8_RD_EN_HI 24
++#define DBG_HWID8_RD_EN_SZ 1
++#define DBG_HWID9_RD_EN_MSK 0x02000000
++#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff
++#define DBG_HWID9_RD_EN_SFT 25
++#define DBG_HWID9_RD_EN_HI 25
++#define DBG_HWID9_RD_EN_SZ 1
++#define DBG_HWID10_RD_EN_MSK 0x04000000
++#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff
++#define DBG_HWID10_RD_EN_SFT 26
++#define DBG_HWID10_RD_EN_HI 26
++#define DBG_HWID10_RD_EN_SZ 1
++#define DBG_HWID11_RD_EN_MSK 0x08000000
++#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff
++#define DBG_HWID11_RD_EN_SFT 27
++#define DBG_HWID11_RD_EN_HI 27
++#define DBG_HWID11_RD_EN_SZ 1
++#define DBG_HWID12_RD_EN_MSK 0x10000000
++#define DBG_HWID12_RD_EN_I_MSK 0xefffffff
++#define DBG_HWID12_RD_EN_SFT 28
++#define DBG_HWID12_RD_EN_HI 28
++#define DBG_HWID12_RD_EN_SZ 1
++#define DBG_HWID13_RD_EN_MSK 0x20000000
++#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff
++#define DBG_HWID13_RD_EN_SFT 29
++#define DBG_HWID13_RD_EN_HI 29
++#define DBG_HWID13_RD_EN_SZ 1
++#define DBG_HWID14_RD_EN_MSK 0x40000000
++#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff
++#define DBG_HWID14_RD_EN_SFT 30
++#define DBG_HWID14_RD_EN_HI 30
++#define DBG_HWID14_RD_EN_SZ 1
++#define DBG_HWID15_RD_EN_MSK 0x80000000
++#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff
++#define DBG_HWID15_RD_EN_SFT 31
++#define DBG_HWID15_RD_EN_HI 31
++#define DBG_HWID15_RD_EN_SZ 1
++#define MB_OUT_QUEUE_EN_MSK 0x00000002
++#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd
++#define MB_OUT_QUEUE_EN_SFT 1
++#define MB_OUT_QUEUE_EN_HI 1
++#define MB_OUT_QUEUE_EN_SZ 1
++#define CH0_QUEUE_FLUSH_MSK 0x00000001
++#define CH0_QUEUE_FLUSH_I_MSK 0xfffffffe
++#define CH0_QUEUE_FLUSH_SFT 0
++#define CH0_QUEUE_FLUSH_HI 0
++#define CH0_QUEUE_FLUSH_SZ 1
++#define CH1_QUEUE_FLUSH_MSK 0x00000002
++#define CH1_QUEUE_FLUSH_I_MSK 0xfffffffd
++#define CH1_QUEUE_FLUSH_SFT 1
++#define CH1_QUEUE_FLUSH_HI 1
++#define CH1_QUEUE_FLUSH_SZ 1
++#define CH2_QUEUE_FLUSH_MSK 0x00000004
++#define CH2_QUEUE_FLUSH_I_MSK 0xfffffffb
++#define CH2_QUEUE_FLUSH_SFT 2
++#define CH2_QUEUE_FLUSH_HI 2
++#define CH2_QUEUE_FLUSH_SZ 1
++#define CH3_QUEUE_FLUSH_MSK 0x00000008
++#define CH3_QUEUE_FLUSH_I_MSK 0xfffffff7
++#define CH3_QUEUE_FLUSH_SFT 3
++#define CH3_QUEUE_FLUSH_HI 3
++#define CH3_QUEUE_FLUSH_SZ 1
++#define CH4_QUEUE_FLUSH_MSK 0x00000010
++#define CH4_QUEUE_FLUSH_I_MSK 0xffffffef
++#define CH4_QUEUE_FLUSH_SFT 4
++#define CH4_QUEUE_FLUSH_HI 4
++#define CH4_QUEUE_FLUSH_SZ 1
++#define CH5_QUEUE_FLUSH_MSK 0x00000020
++#define CH5_QUEUE_FLUSH_I_MSK 0xffffffdf
++#define CH5_QUEUE_FLUSH_SFT 5
++#define CH5_QUEUE_FLUSH_HI 5
++#define CH5_QUEUE_FLUSH_SZ 1
++#define CH6_QUEUE_FLUSH_MSK 0x00000040
++#define CH6_QUEUE_FLUSH_I_MSK 0xffffffbf
++#define CH6_QUEUE_FLUSH_SFT 6
++#define CH6_QUEUE_FLUSH_HI 6
++#define CH6_QUEUE_FLUSH_SZ 1
++#define CH7_QUEUE_FLUSH_MSK 0x00000080
++#define CH7_QUEUE_FLUSH_I_MSK 0xffffff7f
++#define CH7_QUEUE_FLUSH_SFT 7
++#define CH7_QUEUE_FLUSH_HI 7
++#define CH7_QUEUE_FLUSH_SZ 1
++#define CH8_QUEUE_FLUSH_MSK 0x00000100
++#define CH8_QUEUE_FLUSH_I_MSK 0xfffffeff
++#define CH8_QUEUE_FLUSH_SFT 8
++#define CH8_QUEUE_FLUSH_HI 8
++#define CH8_QUEUE_FLUSH_SZ 1
++#define CH9_QUEUE_FLUSH_MSK 0x00000200
++#define CH9_QUEUE_FLUSH_I_MSK 0xfffffdff
++#define CH9_QUEUE_FLUSH_SFT 9
++#define CH9_QUEUE_FLUSH_HI 9
++#define CH9_QUEUE_FLUSH_SZ 1
++#define CH10_QUEUE_FLUSH_MSK 0x00000400
++#define CH10_QUEUE_FLUSH_I_MSK 0xfffffbff
++#define CH10_QUEUE_FLUSH_SFT 10
++#define CH10_QUEUE_FLUSH_HI 10
++#define CH10_QUEUE_FLUSH_SZ 1
++#define CH11_QUEUE_FLUSH_MSK 0x00000800
++#define CH11_QUEUE_FLUSH_I_MSK 0xfffff7ff
++#define CH11_QUEUE_FLUSH_SFT 11
++#define CH11_QUEUE_FLUSH_HI 11
++#define CH11_QUEUE_FLUSH_SZ 1
++#define CH12_QUEUE_FLUSH_MSK 0x00001000
++#define CH12_QUEUE_FLUSH_I_MSK 0xffffefff
++#define CH12_QUEUE_FLUSH_SFT 12
++#define CH12_QUEUE_FLUSH_HI 12
++#define CH12_QUEUE_FLUSH_SZ 1
++#define CH13_QUEUE_FLUSH_MSK 0x00002000
++#define CH13_QUEUE_FLUSH_I_MSK 0xffffdfff
++#define CH13_QUEUE_FLUSH_SFT 13
++#define CH13_QUEUE_FLUSH_HI 13
++#define CH13_QUEUE_FLUSH_SZ 1
++#define CH14_QUEUE_FLUSH_MSK 0x00004000
++#define CH14_QUEUE_FLUSH_I_MSK 0xffffbfff
++#define CH14_QUEUE_FLUSH_SFT 14
++#define CH14_QUEUE_FLUSH_HI 14
++#define CH14_QUEUE_FLUSH_SZ 1
++#define CH15_QUEUE_FLUSH_MSK 0x00008000
++#define CH15_QUEUE_FLUSH_I_MSK 0xffff7fff
++#define CH15_QUEUE_FLUSH_SFT 15
++#define CH15_QUEUE_FLUSH_HI 15
++#define CH15_QUEUE_FLUSH_SZ 1
++#define FFO0_CNT_MSK 0x0000001f
++#define FFO0_CNT_I_MSK 0xffffffe0
++#define FFO0_CNT_SFT 0
++#define FFO0_CNT_HI 4
++#define FFO0_CNT_SZ 5
++#define FFO1_CNT_MSK 0x000003e0
++#define FFO1_CNT_I_MSK 0xfffffc1f
++#define FFO1_CNT_SFT 5
++#define FFO1_CNT_HI 9
++#define FFO1_CNT_SZ 5
++#define FFO2_CNT_MSK 0x00000c00
++#define FFO2_CNT_I_MSK 0xfffff3ff
++#define FFO2_CNT_SFT 10
++#define FFO2_CNT_HI 11
++#define FFO2_CNT_SZ 2
++#define FFO3_CNT_MSK 0x000f8000
++#define FFO3_CNT_I_MSK 0xfff07fff
++#define FFO3_CNT_SFT 15
++#define FFO3_CNT_HI 19
++#define FFO3_CNT_SZ 5
++#define FFO4_CNT_MSK 0x00300000
++#define FFO4_CNT_I_MSK 0xffcfffff
++#define FFO4_CNT_SFT 20
++#define FFO4_CNT_HI 21
++#define FFO4_CNT_SZ 2
++#define FFO5_CNT_MSK 0x0e000000
++#define FFO5_CNT_I_MSK 0xf1ffffff
++#define FFO5_CNT_SFT 25
++#define FFO5_CNT_HI 27
++#define FFO5_CNT_SZ 3
++#define FFO6_CNT_MSK 0x0000000f
++#define FFO6_CNT_I_MSK 0xfffffff0
++#define FFO6_CNT_SFT 0
++#define FFO6_CNT_HI 3
++#define FFO6_CNT_SZ 4
++#define FFO7_CNT_MSK 0x000003e0
++#define FFO7_CNT_I_MSK 0xfffffc1f
++#define FFO7_CNT_SFT 5
++#define FFO7_CNT_HI 9
++#define FFO7_CNT_SZ 5
++#define FFO8_CNT_MSK 0x00007c00
++#define FFO8_CNT_I_MSK 0xffff83ff
++#define FFO8_CNT_SFT 10
++#define FFO8_CNT_HI 14
++#define FFO8_CNT_SZ 5
++#define FFO9_CNT_MSK 0x000f8000
++#define FFO9_CNT_I_MSK 0xfff07fff
++#define FFO9_CNT_SFT 15
++#define FFO9_CNT_HI 19
++#define FFO9_CNT_SZ 5
++#define FFO10_CNT_MSK 0x00f00000
++#define FFO10_CNT_I_MSK 0xff0fffff
++#define FFO10_CNT_SFT 20
++#define FFO10_CNT_HI 23
++#define FFO10_CNT_SZ 4
++#define FFO11_CNT_MSK 0x3e000000
++#define FFO11_CNT_I_MSK 0xc1ffffff
++#define FFO11_CNT_SFT 25
++#define FFO11_CNT_HI 29
++#define FFO11_CNT_SZ 5
++#define FFO12_CNT_MSK 0x00000007
++#define FFO12_CNT_I_MSK 0xfffffff8
++#define FFO12_CNT_SFT 0
++#define FFO12_CNT_HI 2
++#define FFO12_CNT_SZ 3
++#define FFO13_CNT_MSK 0x00000060
++#define FFO13_CNT_I_MSK 0xffffff9f
++#define FFO13_CNT_SFT 5
++#define FFO13_CNT_HI 6
++#define FFO13_CNT_SZ 2
++#define FFO14_CNT_MSK 0x00000c00
++#define FFO14_CNT_I_MSK 0xfffff3ff
++#define FFO14_CNT_SFT 10
++#define FFO14_CNT_HI 11
++#define FFO14_CNT_SZ 2
++#define FFO15_CNT_MSK 0x001f8000
++#define FFO15_CNT_I_MSK 0xffe07fff
++#define FFO15_CNT_SFT 15
++#define FFO15_CNT_HI 20
++#define FFO15_CNT_SZ 6
++#define CH0_FFO_FULL_MSK 0x00000001
++#define CH0_FFO_FULL_I_MSK 0xfffffffe
++#define CH0_FFO_FULL_SFT 0
++#define CH0_FFO_FULL_HI 0
++#define CH0_FFO_FULL_SZ 1
++#define CH1_FFO_FULL_MSK 0x00000002
++#define CH1_FFO_FULL_I_MSK 0xfffffffd
++#define CH1_FFO_FULL_SFT 1
++#define CH1_FFO_FULL_HI 1
++#define CH1_FFO_FULL_SZ 1
++#define CH2_FFO_FULL_MSK 0x00000004
++#define CH2_FFO_FULL_I_MSK 0xfffffffb
++#define CH2_FFO_FULL_SFT 2
++#define CH2_FFO_FULL_HI 2
++#define CH2_FFO_FULL_SZ 1
++#define CH3_FFO_FULL_MSK 0x00000008
++#define CH3_FFO_FULL_I_MSK 0xfffffff7
++#define CH3_FFO_FULL_SFT 3
++#define CH3_FFO_FULL_HI 3
++#define CH3_FFO_FULL_SZ 1
++#define CH4_FFO_FULL_MSK 0x00000010
++#define CH4_FFO_FULL_I_MSK 0xffffffef
++#define CH4_FFO_FULL_SFT 4
++#define CH4_FFO_FULL_HI 4
++#define CH4_FFO_FULL_SZ 1
++#define CH5_FFO_FULL_MSK 0x00000020
++#define CH5_FFO_FULL_I_MSK 0xffffffdf
++#define CH5_FFO_FULL_SFT 5
++#define CH5_FFO_FULL_HI 5
++#define CH5_FFO_FULL_SZ 1
++#define CH6_FFO_FULL_MSK 0x00000040
++#define CH6_FFO_FULL_I_MSK 0xffffffbf
++#define CH6_FFO_FULL_SFT 6
++#define CH6_FFO_FULL_HI 6
++#define CH6_FFO_FULL_SZ 1
++#define CH7_FFO_FULL_MSK 0x00000080
++#define CH7_FFO_FULL_I_MSK 0xffffff7f
++#define CH7_FFO_FULL_SFT 7
++#define CH7_FFO_FULL_HI 7
++#define CH7_FFO_FULL_SZ 1
++#define CH8_FFO_FULL_MSK 0x00000100
++#define CH8_FFO_FULL_I_MSK 0xfffffeff
++#define CH8_FFO_FULL_SFT 8
++#define CH8_FFO_FULL_HI 8
++#define CH8_FFO_FULL_SZ 1
++#define CH9_FFO_FULL_MSK 0x00000200
++#define CH9_FFO_FULL_I_MSK 0xfffffdff
++#define CH9_FFO_FULL_SFT 9
++#define CH9_FFO_FULL_HI 9
++#define CH9_FFO_FULL_SZ 1
++#define CH10_FFO_FULL_MSK 0x00000400
++#define CH10_FFO_FULL_I_MSK 0xfffffbff
++#define CH10_FFO_FULL_SFT 10
++#define CH10_FFO_FULL_HI 10
++#define CH10_FFO_FULL_SZ 1
++#define CH11_FFO_FULL_MSK 0x00000800
++#define CH11_FFO_FULL_I_MSK 0xfffff7ff
++#define CH11_FFO_FULL_SFT 11
++#define CH11_FFO_FULL_HI 11
++#define CH11_FFO_FULL_SZ 1
++#define CH12_FFO_FULL_MSK 0x00001000
++#define CH12_FFO_FULL_I_MSK 0xffffefff
++#define CH12_FFO_FULL_SFT 12
++#define CH12_FFO_FULL_HI 12
++#define CH12_FFO_FULL_SZ 1
++#define CH13_FFO_FULL_MSK 0x00002000
++#define CH13_FFO_FULL_I_MSK 0xffffdfff
++#define CH13_FFO_FULL_SFT 13
++#define CH13_FFO_FULL_HI 13
++#define CH13_FFO_FULL_SZ 1
++#define CH14_FFO_FULL_MSK 0x00004000
++#define CH14_FFO_FULL_I_MSK 0xffffbfff
++#define CH14_FFO_FULL_SFT 14
++#define CH14_FFO_FULL_HI 14
++#define CH14_FFO_FULL_SZ 1
++#define CH15_FFO_FULL_MSK 0x00008000
++#define CH15_FFO_FULL_I_MSK 0xffff7fff
++#define CH15_FFO_FULL_SFT 15
++#define CH15_FFO_FULL_HI 15
++#define CH15_FFO_FULL_SZ 1
++#define CH0_LOWTHOLD_INT_MSK 0x00000001
++#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe
++#define CH0_LOWTHOLD_INT_SFT 0
++#define CH0_LOWTHOLD_INT_HI 0
++#define CH0_LOWTHOLD_INT_SZ 1
++#define CH1_LOWTHOLD_INT_MSK 0x00000002
++#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd
++#define CH1_LOWTHOLD_INT_SFT 1
++#define CH1_LOWTHOLD_INT_HI 1
++#define CH1_LOWTHOLD_INT_SZ 1
++#define CH2_LOWTHOLD_INT_MSK 0x00000004
++#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb
++#define CH2_LOWTHOLD_INT_SFT 2
++#define CH2_LOWTHOLD_INT_HI 2
++#define CH2_LOWTHOLD_INT_SZ 1
++#define CH3_LOWTHOLD_INT_MSK 0x00000008
++#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7
++#define CH3_LOWTHOLD_INT_SFT 3
++#define CH3_LOWTHOLD_INT_HI 3
++#define CH3_LOWTHOLD_INT_SZ 1
++#define CH4_LOWTHOLD_INT_MSK 0x00000010
++#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef
++#define CH4_LOWTHOLD_INT_SFT 4
++#define CH4_LOWTHOLD_INT_HI 4
++#define CH4_LOWTHOLD_INT_SZ 1
++#define CH5_LOWTHOLD_INT_MSK 0x00000020
++#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf
++#define CH5_LOWTHOLD_INT_SFT 5
++#define CH5_LOWTHOLD_INT_HI 5
++#define CH5_LOWTHOLD_INT_SZ 1
++#define CH6_LOWTHOLD_INT_MSK 0x00000040
++#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf
++#define CH6_LOWTHOLD_INT_SFT 6
++#define CH6_LOWTHOLD_INT_HI 6
++#define CH6_LOWTHOLD_INT_SZ 1
++#define CH7_LOWTHOLD_INT_MSK 0x00000080
++#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f
++#define CH7_LOWTHOLD_INT_SFT 7
++#define CH7_LOWTHOLD_INT_HI 7
++#define CH7_LOWTHOLD_INT_SZ 1
++#define CH8_LOWTHOLD_INT_MSK 0x00000100
++#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff
++#define CH8_LOWTHOLD_INT_SFT 8
++#define CH8_LOWTHOLD_INT_HI 8
++#define CH8_LOWTHOLD_INT_SZ 1
++#define CH9_LOWTHOLD_INT_MSK 0x00000200
++#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff
++#define CH9_LOWTHOLD_INT_SFT 9
++#define CH9_LOWTHOLD_INT_HI 9
++#define CH9_LOWTHOLD_INT_SZ 1
++#define CH10_LOWTHOLD_INT_MSK 0x00000400
++#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff
++#define CH10_LOWTHOLD_INT_SFT 10
++#define CH10_LOWTHOLD_INT_HI 10
++#define CH10_LOWTHOLD_INT_SZ 1
++#define CH11_LOWTHOLD_INT_MSK 0x00000800
++#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff
++#define CH11_LOWTHOLD_INT_SFT 11
++#define CH11_LOWTHOLD_INT_HI 11
++#define CH11_LOWTHOLD_INT_SZ 1
++#define CH12_LOWTHOLD_INT_MSK 0x00001000
++#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff
++#define CH12_LOWTHOLD_INT_SFT 12
++#define CH12_LOWTHOLD_INT_HI 12
++#define CH12_LOWTHOLD_INT_SZ 1
++#define CH13_LOWTHOLD_INT_MSK 0x00002000
++#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff
++#define CH13_LOWTHOLD_INT_SFT 13
++#define CH13_LOWTHOLD_INT_HI 13
++#define CH13_LOWTHOLD_INT_SZ 1
++#define CH14_LOWTHOLD_INT_MSK 0x00004000
++#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff
++#define CH14_LOWTHOLD_INT_SFT 14
++#define CH14_LOWTHOLD_INT_HI 14
++#define CH14_LOWTHOLD_INT_SZ 1
++#define CH15_LOWTHOLD_INT_MSK 0x00008000
++#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff
++#define CH15_LOWTHOLD_INT_SFT 15
++#define CH15_LOWTHOLD_INT_HI 15
++#define CH15_LOWTHOLD_INT_SZ 1
++#define MB_LOW_THOLD_EN_MSK 0x80000000
++#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff
++#define MB_LOW_THOLD_EN_SFT 31
++#define MB_LOW_THOLD_EN_HI 31
++#define MB_LOW_THOLD_EN_SZ 1
++#define CH0_LOWTHOLD_MSK 0x0000001f
++#define CH0_LOWTHOLD_I_MSK 0xffffffe0
++#define CH0_LOWTHOLD_SFT 0
++#define CH0_LOWTHOLD_HI 4
++#define CH0_LOWTHOLD_SZ 5
++#define CH1_LOWTHOLD_MSK 0x00001f00
++#define CH1_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH1_LOWTHOLD_SFT 8
++#define CH1_LOWTHOLD_HI 12
++#define CH1_LOWTHOLD_SZ 5
++#define CH2_LOWTHOLD_MSK 0x001f0000
++#define CH2_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH2_LOWTHOLD_SFT 16
++#define CH2_LOWTHOLD_HI 20
++#define CH2_LOWTHOLD_SZ 5
++#define CH3_LOWTHOLD_MSK 0x1f000000
++#define CH3_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH3_LOWTHOLD_SFT 24
++#define CH3_LOWTHOLD_HI 28
++#define CH3_LOWTHOLD_SZ 5
++#define CH4_LOWTHOLD_MSK 0x0000001f
++#define CH4_LOWTHOLD_I_MSK 0xffffffe0
++#define CH4_LOWTHOLD_SFT 0
++#define CH4_LOWTHOLD_HI 4
++#define CH4_LOWTHOLD_SZ 5
++#define CH5_LOWTHOLD_MSK 0x00001f00
++#define CH5_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH5_LOWTHOLD_SFT 8
++#define CH5_LOWTHOLD_HI 12
++#define CH5_LOWTHOLD_SZ 5
++#define CH6_LOWTHOLD_MSK 0x001f0000
++#define CH6_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH6_LOWTHOLD_SFT 16
++#define CH6_LOWTHOLD_HI 20
++#define CH6_LOWTHOLD_SZ 5
++#define CH7_LOWTHOLD_MSK 0x1f000000
++#define CH7_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH7_LOWTHOLD_SFT 24
++#define CH7_LOWTHOLD_HI 28
++#define CH7_LOWTHOLD_SZ 5
++#define CH8_LOWTHOLD_MSK 0x0000001f
++#define CH8_LOWTHOLD_I_MSK 0xffffffe0
++#define CH8_LOWTHOLD_SFT 0
++#define CH8_LOWTHOLD_HI 4
++#define CH8_LOWTHOLD_SZ 5
++#define CH9_LOWTHOLD_MSK 0x00001f00
++#define CH9_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH9_LOWTHOLD_SFT 8
++#define CH9_LOWTHOLD_HI 12
++#define CH9_LOWTHOLD_SZ 5
++#define CH10_LOWTHOLD_MSK 0x001f0000
++#define CH10_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH10_LOWTHOLD_SFT 16
++#define CH10_LOWTHOLD_HI 20
++#define CH10_LOWTHOLD_SZ 5
++#define CH11_LOWTHOLD_MSK 0x1f000000
++#define CH11_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH11_LOWTHOLD_SFT 24
++#define CH11_LOWTHOLD_HI 28
++#define CH11_LOWTHOLD_SZ 5
++#define CH12_LOWTHOLD_MSK 0x0000001f
++#define CH12_LOWTHOLD_I_MSK 0xffffffe0
++#define CH12_LOWTHOLD_SFT 0
++#define CH12_LOWTHOLD_HI 4
++#define CH12_LOWTHOLD_SZ 5
++#define CH13_LOWTHOLD_MSK 0x00001f00
++#define CH13_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH13_LOWTHOLD_SFT 8
++#define CH13_LOWTHOLD_HI 12
++#define CH13_LOWTHOLD_SZ 5
++#define CH14_LOWTHOLD_MSK 0x001f0000
++#define CH14_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH14_LOWTHOLD_SFT 16
++#define CH14_LOWTHOLD_HI 20
++#define CH14_LOWTHOLD_SZ 5
++#define CH15_LOWTHOLD_MSK 0x1f000000
++#define CH15_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH15_LOWTHOLD_SFT 24
++#define CH15_LOWTHOLD_HI 28
++#define CH15_LOWTHOLD_SZ 5
++#define TRASH_TIMEOUT_EN_MSK 0x00000001
++#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe
++#define TRASH_TIMEOUT_EN_SFT 0
++#define TRASH_TIMEOUT_EN_HI 0
++#define TRASH_TIMEOUT_EN_SZ 1
++#define TRASH_CAN_INT_MSK 0x00000002
++#define TRASH_CAN_INT_I_MSK 0xfffffffd
++#define TRASH_CAN_INT_SFT 1
++#define TRASH_CAN_INT_HI 1
++#define TRASH_CAN_INT_SZ 1
++#define TRASH_INT_ID_MSK 0x000007f0
++#define TRASH_INT_ID_I_MSK 0xfffff80f
++#define TRASH_INT_ID_SFT 4
++#define TRASH_INT_ID_HI 10
++#define TRASH_INT_ID_SZ 7
++#define TRASH_TIMEOUT_MSK 0x03ff0000
++#define TRASH_TIMEOUT_I_MSK 0xfc00ffff
++#define TRASH_TIMEOUT_SFT 16
++#define TRASH_TIMEOUT_HI 25
++#define TRASH_TIMEOUT_SZ 10
++#define CH0_WRFF_FLUSH_MSK 0x00000001
++#define CH0_WRFF_FLUSH_I_MSK 0xfffffffe
++#define CH0_WRFF_FLUSH_SFT 0
++#define CH0_WRFF_FLUSH_HI 0
++#define CH0_WRFF_FLUSH_SZ 1
++#define CH1_WRFF_FLUSH_MSK 0x00000002
++#define CH1_WRFF_FLUSH_I_MSK 0xfffffffd
++#define CH1_WRFF_FLUSH_SFT 1
++#define CH1_WRFF_FLUSH_HI 1
++#define CH1_WRFF_FLUSH_SZ 1
++#define CH2_WRFF_FLUSH_MSK 0x00000004
++#define CH2_WRFF_FLUSH_I_MSK 0xfffffffb
++#define CH2_WRFF_FLUSH_SFT 2
++#define CH2_WRFF_FLUSH_HI 2
++#define CH2_WRFF_FLUSH_SZ 1
++#define CH3_WRFF_FLUSH_MSK 0x00000008
++#define CH3_WRFF_FLUSH_I_MSK 0xfffffff7
++#define CH3_WRFF_FLUSH_SFT 3
++#define CH3_WRFF_FLUSH_HI 3
++#define CH3_WRFF_FLUSH_SZ 1
++#define CH4_WRFF_FLUSH_MSK 0x00000010
++#define CH4_WRFF_FLUSH_I_MSK 0xffffffef
++#define CH4_WRFF_FLUSH_SFT 4
++#define CH4_WRFF_FLUSH_HI 4
++#define CH4_WRFF_FLUSH_SZ 1
++#define CH5_WRFF_FLUSH_MSK 0x00000020
++#define CH5_WRFF_FLUSH_I_MSK 0xffffffdf
++#define CH5_WRFF_FLUSH_SFT 5
++#define CH5_WRFF_FLUSH_HI 5
++#define CH5_WRFF_FLUSH_SZ 1
++#define CH6_WRFF_FLUSH_MSK 0x00000040
++#define CH6_WRFF_FLUSH_I_MSK 0xffffffbf
++#define CH6_WRFF_FLUSH_SFT 6
++#define CH6_WRFF_FLUSH_HI 6
++#define CH6_WRFF_FLUSH_SZ 1
++#define CH7_WRFF_FLUSH_MSK 0x00000080
++#define CH7_WRFF_FLUSH_I_MSK 0xffffff7f
++#define CH7_WRFF_FLUSH_SFT 7
++#define CH7_WRFF_FLUSH_HI 7
++#define CH7_WRFF_FLUSH_SZ 1
++#define CH8_WRFF_FLUSH_MSK 0x00000100
++#define CH8_WRFF_FLUSH_I_MSK 0xfffffeff
++#define CH8_WRFF_FLUSH_SFT 8
++#define CH8_WRFF_FLUSH_HI 8
++#define CH8_WRFF_FLUSH_SZ 1
++#define CH9_WRFF_FLUSH_MSK 0x00000200
++#define CH9_WRFF_FLUSH_I_MSK 0xfffffdff
++#define CH9_WRFF_FLUSH_SFT 9
++#define CH9_WRFF_FLUSH_HI 9
++#define CH9_WRFF_FLUSH_SZ 1
++#define CH10_WRFF_FLUSH_MSK 0x00000400
++#define CH10_WRFF_FLUSH_I_MSK 0xfffffbff
++#define CH10_WRFF_FLUSH_SFT 10
++#define CH10_WRFF_FLUSH_HI 10
++#define CH10_WRFF_FLUSH_SZ 1
++#define CH11_WRFF_FLUSH_MSK 0x00000800
++#define CH11_WRFF_FLUSH_I_MSK 0xfffff7ff
++#define CH11_WRFF_FLUSH_SFT 11
++#define CH11_WRFF_FLUSH_HI 11
++#define CH11_WRFF_FLUSH_SZ 1
++#define CH12_WRFF_FLUSH_MSK 0x00001000
++#define CH12_WRFF_FLUSH_I_MSK 0xffffefff
++#define CH12_WRFF_FLUSH_SFT 12
++#define CH12_WRFF_FLUSH_HI 12
++#define CH12_WRFF_FLUSH_SZ 1
++#define CH13_WRFF_FLUSH_MSK 0x00002000
++#define CH13_WRFF_FLUSH_I_MSK 0xffffdfff
++#define CH13_WRFF_FLUSH_SFT 13
++#define CH13_WRFF_FLUSH_HI 13
++#define CH13_WRFF_FLUSH_SZ 1
++#define CH14_WRFF_FLUSH_MSK 0x00004000
++#define CH14_WRFF_FLUSH_I_MSK 0xffffbfff
++#define CH14_WRFF_FLUSH_SFT 14
++#define CH14_WRFF_FLUSH_HI 14
++#define CH14_WRFF_FLUSH_SZ 1
++#define CPU_ID_TB2_MSK 0xffffffff
++#define CPU_ID_TB2_I_MSK 0x00000000
++#define CPU_ID_TB2_SFT 0
++#define CPU_ID_TB2_HI 31
++#define CPU_ID_TB2_SZ 32
++#define CPU_ID_TB3_MSK 0xffffffff
++#define CPU_ID_TB3_I_MSK 0x00000000
++#define CPU_ID_TB3_SFT 0
++#define CPU_ID_TB3_HI 31
++#define CPU_ID_TB3_SZ 32
++#define IQ_LOG_EN_MSK 0x00000001
++#define IQ_LOG_EN_I_MSK 0xfffffffe
++#define IQ_LOG_EN_SFT 0
++#define IQ_LOG_EN_HI 0
++#define IQ_LOG_EN_SZ 1
++#define IQ_LOG_STOP_MODE_MSK 0x00000001
++#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe
++#define IQ_LOG_STOP_MODE_SFT 0
++#define IQ_LOG_STOP_MODE_HI 0
++#define IQ_LOG_STOP_MODE_SZ 1
++#define GPIO_STOP_EN_MSK 0x00000010
++#define GPIO_STOP_EN_I_MSK 0xffffffef
++#define GPIO_STOP_EN_SFT 4
++#define GPIO_STOP_EN_HI 4
++#define GPIO_STOP_EN_SZ 1
++#define GPIO_STOP_POL_MSK 0x00000020
++#define GPIO_STOP_POL_I_MSK 0xffffffdf
++#define GPIO_STOP_POL_SFT 5
++#define GPIO_STOP_POL_HI 5
++#define GPIO_STOP_POL_SZ 1
++#define IQ_LOG_TIMER_MSK 0xffff0000
++#define IQ_LOG_TIMER_I_MSK 0x0000ffff
++#define IQ_LOG_TIMER_SFT 16
++#define IQ_LOG_TIMER_HI 31
++#define IQ_LOG_TIMER_SZ 16
++#define IQ_LOG_LEN_MSK 0x0000ffff
++#define IQ_LOG_LEN_I_MSK 0xffff0000
++#define IQ_LOG_LEN_SFT 0
++#define IQ_LOG_LEN_HI 15
++#define IQ_LOG_LEN_SZ 16
++#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff
++#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000
++#define IQ_LOG_TAIL_ADR_SFT 0
++#define IQ_LOG_TAIL_ADR_HI 15
++#define IQ_LOG_TAIL_ADR_SZ 16
++#define ALC_LENG_MSK 0x0003ffff
++#define ALC_LENG_I_MSK 0xfffc0000
++#define ALC_LENG_SFT 0
++#define ALC_LENG_HI 17
++#define ALC_LENG_SZ 18
++#define CH0_DYN_PRI_MSK 0x00300000
++#define CH0_DYN_PRI_I_MSK 0xffcfffff
++#define CH0_DYN_PRI_SFT 20
++#define CH0_DYN_PRI_HI 21
++#define CH0_DYN_PRI_SZ 2
++#define MCU_PKTID_MSK 0xffffffff
++#define MCU_PKTID_I_MSK 0x00000000
++#define MCU_PKTID_SFT 0
++#define MCU_PKTID_HI 31
++#define MCU_PKTID_SZ 32
++#define CH0_STA_PRI_MSK 0x00000003
++#define CH0_STA_PRI_I_MSK 0xfffffffc
++#define CH0_STA_PRI_SFT 0
++#define CH0_STA_PRI_HI 1
++#define CH0_STA_PRI_SZ 2
++#define CH1_STA_PRI_MSK 0x00000030
++#define CH1_STA_PRI_I_MSK 0xffffffcf
++#define CH1_STA_PRI_SFT 4
++#define CH1_STA_PRI_HI 5
++#define CH1_STA_PRI_SZ 2
++#define CH2_STA_PRI_MSK 0x00000300
++#define CH2_STA_PRI_I_MSK 0xfffffcff
++#define CH2_STA_PRI_SFT 8
++#define CH2_STA_PRI_HI 9
++#define CH2_STA_PRI_SZ 2
++#define CH3_STA_PRI_MSK 0x00003000
++#define CH3_STA_PRI_I_MSK 0xffffcfff
++#define CH3_STA_PRI_SFT 12
++#define CH3_STA_PRI_HI 13
++#define CH3_STA_PRI_SZ 2
++#define ID_TB0_MSK 0xffffffff
++#define ID_TB0_I_MSK 0x00000000
++#define ID_TB0_SFT 0
++#define ID_TB0_HI 31
++#define ID_TB0_SZ 32
++#define ID_TB1_MSK 0xffffffff
++#define ID_TB1_I_MSK 0x00000000
++#define ID_TB1_SFT 0
++#define ID_TB1_HI 31
++#define ID_TB1_SZ 32
++#define ID_MNG_HALT_MSK 0x00000010
++#define ID_MNG_HALT_I_MSK 0xffffffef
++#define ID_MNG_HALT_SFT 4
++#define ID_MNG_HALT_HI 4
++#define ID_MNG_HALT_SZ 1
++#define ID_MNG_ERR_HALT_EN_MSK 0x00000020
++#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf
++#define ID_MNG_ERR_HALT_EN_SFT 5
++#define ID_MNG_ERR_HALT_EN_HI 5
++#define ID_MNG_ERR_HALT_EN_SZ 1
++#define ID_EXCEPT_FLG_CLR_MSK 0x00000040
++#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf
++#define ID_EXCEPT_FLG_CLR_SFT 6
++#define ID_EXCEPT_FLG_CLR_HI 6
++#define ID_EXCEPT_FLG_CLR_SZ 1
++#define ID_EXCEPT_FLG_MSK 0x00000080
++#define ID_EXCEPT_FLG_I_MSK 0xffffff7f
++#define ID_EXCEPT_FLG_SFT 7
++#define ID_EXCEPT_FLG_HI 7
++#define ID_EXCEPT_FLG_SZ 1
++#define ID_FULL_MSK 0x00000001
++#define ID_FULL_I_MSK 0xfffffffe
++#define ID_FULL_SFT 0
++#define ID_FULL_HI 0
++#define ID_FULL_SZ 1
++#define ID_MNG_BUSY_MSK 0x00000002
++#define ID_MNG_BUSY_I_MSK 0xfffffffd
++#define ID_MNG_BUSY_SFT 1
++#define ID_MNG_BUSY_HI 1
++#define ID_MNG_BUSY_SZ 1
++#define REQ_LOCK_MSK 0x00000004
++#define REQ_LOCK_I_MSK 0xfffffffb
++#define REQ_LOCK_SFT 2
++#define REQ_LOCK_HI 2
++#define REQ_LOCK_SZ 1
++#define CH0_REQ_LOCK_MSK 0x00000010
++#define CH0_REQ_LOCK_I_MSK 0xffffffef
++#define CH0_REQ_LOCK_SFT 4
++#define CH0_REQ_LOCK_HI 4
++#define CH0_REQ_LOCK_SZ 1
++#define CH1_REQ_LOCK_MSK 0x00000020
++#define CH1_REQ_LOCK_I_MSK 0xffffffdf
++#define CH1_REQ_LOCK_SFT 5
++#define CH1_REQ_LOCK_HI 5
++#define CH1_REQ_LOCK_SZ 1
++#define CH2_REQ_LOCK_MSK 0x00000040
++#define CH2_REQ_LOCK_I_MSK 0xffffffbf
++#define CH2_REQ_LOCK_SFT 6
++#define CH2_REQ_LOCK_HI 6
++#define CH2_REQ_LOCK_SZ 1
++#define CH3_REQ_LOCK_MSK 0x00000080
++#define CH3_REQ_LOCK_I_MSK 0xffffff7f
++#define CH3_REQ_LOCK_SFT 7
++#define CH3_REQ_LOCK_HI 7
++#define CH3_REQ_LOCK_SZ 1
++#define REQ_LOCK_INT_EN_MSK 0x00000100
++#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff
++#define REQ_LOCK_INT_EN_SFT 8
++#define REQ_LOCK_INT_EN_HI 8
++#define REQ_LOCK_INT_EN_SZ 1
++#define REQ_LOCK_INT_MSK 0x00000200
++#define REQ_LOCK_INT_I_MSK 0xfffffdff
++#define REQ_LOCK_INT_SFT 9
++#define REQ_LOCK_INT_HI 9
++#define REQ_LOCK_INT_SZ 1
++#define MCU_ALC_READY_MSK 0x00000001
++#define MCU_ALC_READY_I_MSK 0xfffffffe
++#define MCU_ALC_READY_SFT 0
++#define MCU_ALC_READY_HI 0
++#define MCU_ALC_READY_SZ 1
++#define ALC_FAIL_MSK 0x00000002
++#define ALC_FAIL_I_MSK 0xfffffffd
++#define ALC_FAIL_SFT 1
++#define ALC_FAIL_HI 1
++#define ALC_FAIL_SZ 1
++#define ALC_BUSY_MSK 0x00000004
++#define ALC_BUSY_I_MSK 0xfffffffb
++#define ALC_BUSY_SFT 2
++#define ALC_BUSY_HI 2
++#define ALC_BUSY_SZ 1
++#define CH0_NVLD_MSK 0x00000010
++#define CH0_NVLD_I_MSK 0xffffffef
++#define CH0_NVLD_SFT 4
++#define CH0_NVLD_HI 4
++#define CH0_NVLD_SZ 1
++#define CH1_NVLD_MSK 0x00000020
++#define CH1_NVLD_I_MSK 0xffffffdf
++#define CH1_NVLD_SFT 5
++#define CH1_NVLD_HI 5
++#define CH1_NVLD_SZ 1
++#define CH2_NVLD_MSK 0x00000040
++#define CH2_NVLD_I_MSK 0xffffffbf
++#define CH2_NVLD_SFT 6
++#define CH2_NVLD_HI 6
++#define CH2_NVLD_SZ 1
++#define CH3_NVLD_MSK 0x00000080
++#define CH3_NVLD_I_MSK 0xffffff7f
++#define CH3_NVLD_SFT 7
++#define CH3_NVLD_HI 7
++#define CH3_NVLD_SZ 1
++#define ALC_INT_ID_MSK 0x00007f00
++#define ALC_INT_ID_I_MSK 0xffff80ff
++#define ALC_INT_ID_SFT 8
++#define ALC_INT_ID_HI 14
++#define ALC_INT_ID_SZ 7
++#define ALC_TIMEOUT_MSK 0x03ff0000
++#define ALC_TIMEOUT_I_MSK 0xfc00ffff
++#define ALC_TIMEOUT_SFT 16
++#define ALC_TIMEOUT_HI 25
++#define ALC_TIMEOUT_SZ 10
++#define ALC_TIMEOUT_INT_EN_MSK 0x40000000
++#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff
++#define ALC_TIMEOUT_INT_EN_SFT 30
++#define ALC_TIMEOUT_INT_EN_HI 30
++#define ALC_TIMEOUT_INT_EN_SZ 1
++#define ALC_TIMEOUT_INT_MSK 0x80000000
++#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff
++#define ALC_TIMEOUT_INT_SFT 31
++#define ALC_TIMEOUT_INT_HI 31
++#define ALC_TIMEOUT_INT_SZ 1
++#define TX_ID_COUNT_MSK 0x000000ff
++#define TX_ID_COUNT_I_MSK 0xffffff00
++#define TX_ID_COUNT_SFT 0
++#define TX_ID_COUNT_HI 7
++#define TX_ID_COUNT_SZ 8
++#define RX_ID_COUNT_MSK 0x0000ff00
++#define RX_ID_COUNT_I_MSK 0xffff00ff
++#define RX_ID_COUNT_SFT 8
++#define RX_ID_COUNT_HI 15
++#define RX_ID_COUNT_SZ 8
++#define TX_ID_THOLD_MSK 0x000000ff
++#define TX_ID_THOLD_I_MSK 0xffffff00
++#define TX_ID_THOLD_SFT 0
++#define TX_ID_THOLD_HI 7
++#define TX_ID_THOLD_SZ 8
++#define RX_ID_THOLD_MSK 0x0000ff00
++#define RX_ID_THOLD_I_MSK 0xffff00ff
++#define RX_ID_THOLD_SFT 8
++#define RX_ID_THOLD_HI 15
++#define RX_ID_THOLD_SZ 8
++#define ID_THOLD_RX_INT_MSK 0x00010000
++#define ID_THOLD_RX_INT_I_MSK 0xfffeffff
++#define ID_THOLD_RX_INT_SFT 16
++#define ID_THOLD_RX_INT_HI 16
++#define ID_THOLD_RX_INT_SZ 1
++#define RX_INT_CH_MSK 0x000e0000
++#define RX_INT_CH_I_MSK 0xfff1ffff
++#define RX_INT_CH_SFT 17
++#define RX_INT_CH_HI 19
++#define RX_INT_CH_SZ 3
++#define ID_THOLD_TX_INT_MSK 0x00100000
++#define ID_THOLD_TX_INT_I_MSK 0xffefffff
++#define ID_THOLD_TX_INT_SFT 20
++#define ID_THOLD_TX_INT_HI 20
++#define ID_THOLD_TX_INT_SZ 1
++#define TX_INT_CH_MSK 0x00e00000
++#define TX_INT_CH_I_MSK 0xff1fffff
++#define TX_INT_CH_SFT 21
++#define TX_INT_CH_HI 23
++#define TX_INT_CH_SZ 3
++#define ID_THOLD_INT_EN_MSK 0x01000000
++#define ID_THOLD_INT_EN_I_MSK 0xfeffffff
++#define ID_THOLD_INT_EN_SFT 24
++#define ID_THOLD_INT_EN_HI 24
++#define ID_THOLD_INT_EN_SZ 1
++#define TX_ID_TB0_MSK 0xffffffff
++#define TX_ID_TB0_I_MSK 0x00000000
++#define TX_ID_TB0_SFT 0
++#define TX_ID_TB0_HI 31
++#define TX_ID_TB0_SZ 32
++#define TX_ID_TB1_MSK 0xffffffff
++#define TX_ID_TB1_I_MSK 0x00000000
++#define TX_ID_TB1_SFT 0
++#define TX_ID_TB1_HI 31
++#define TX_ID_TB1_SZ 32
++#define RX_ID_TB0_MSK 0xffffffff
++#define RX_ID_TB0_I_MSK 0x00000000
++#define RX_ID_TB0_SFT 0
++#define RX_ID_TB0_HI 31
++#define RX_ID_TB0_SZ 32
++#define RX_ID_TB1_MSK 0xffffffff
++#define RX_ID_TB1_I_MSK 0x00000000
++#define RX_ID_TB1_SFT 0
++#define RX_ID_TB1_HI 31
++#define RX_ID_TB1_SZ 32
++#define DOUBLE_RLS_INT_EN_MSK 0x00000001
++#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe
++#define DOUBLE_RLS_INT_EN_SFT 0
++#define DOUBLE_RLS_INT_EN_HI 0
++#define DOUBLE_RLS_INT_EN_SZ 1
++#define ID_DOUBLE_RLS_INT_MSK 0x00000002
++#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd
++#define ID_DOUBLE_RLS_INT_SFT 1
++#define ID_DOUBLE_RLS_INT_HI 1
++#define ID_DOUBLE_RLS_INT_SZ 1
++#define DOUBLE_RLS_ID_MSK 0x00007f00
++#define DOUBLE_RLS_ID_I_MSK 0xffff80ff
++#define DOUBLE_RLS_ID_SFT 8
++#define DOUBLE_RLS_ID_HI 14
++#define DOUBLE_RLS_ID_SZ 7
++#define ID_LEN_THOLD_INT_EN_MSK 0x00000001
++#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe
++#define ID_LEN_THOLD_INT_EN_SFT 0
++#define ID_LEN_THOLD_INT_EN_HI 0
++#define ID_LEN_THOLD_INT_EN_SZ 1
++#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002
++#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd
++#define ALL_ID_LEN_THOLD_INT_SFT 1
++#define ALL_ID_LEN_THOLD_INT_HI 1
++#define ALL_ID_LEN_THOLD_INT_SZ 1
++#define TX_ID_LEN_THOLD_INT_MSK 0x00000004
++#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb
++#define TX_ID_LEN_THOLD_INT_SFT 2
++#define TX_ID_LEN_THOLD_INT_HI 2
++#define TX_ID_LEN_THOLD_INT_SZ 1
++#define RX_ID_LEN_THOLD_INT_MSK 0x00000008
++#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7
++#define RX_ID_LEN_THOLD_INT_SFT 3
++#define RX_ID_LEN_THOLD_INT_HI 3
++#define RX_ID_LEN_THOLD_INT_SZ 1
++#define ID_TX_LEN_THOLD_MSK 0x00001ff0
++#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f
++#define ID_TX_LEN_THOLD_SFT 4
++#define ID_TX_LEN_THOLD_HI 12
++#define ID_TX_LEN_THOLD_SZ 9
++#define ID_RX_LEN_THOLD_MSK 0x003fe000
++#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff
++#define ID_RX_LEN_THOLD_SFT 13
++#define ID_RX_LEN_THOLD_HI 21
++#define ID_RX_LEN_THOLD_SZ 9
++#define ID_LEN_THOLD_MSK 0x7fc00000
++#define ID_LEN_THOLD_I_MSK 0x803fffff
++#define ID_LEN_THOLD_SFT 22
++#define ID_LEN_THOLD_HI 30
++#define ID_LEN_THOLD_SZ 9
++#define ALL_ID_ALC_LEN_MSK 0x000001ff
++#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00
++#define ALL_ID_ALC_LEN_SFT 0
++#define ALL_ID_ALC_LEN_HI 8
++#define ALL_ID_ALC_LEN_SZ 9
++#define TX_ID_ALC_LEN_MSK 0x0003fe00
++#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff
++#define TX_ID_ALC_LEN_SFT 9
++#define TX_ID_ALC_LEN_HI 17
++#define TX_ID_ALC_LEN_SZ 9
++#define RX_ID_ALC_LEN_MSK 0x07fc0000
++#define RX_ID_ALC_LEN_I_MSK 0xf803ffff
++#define RX_ID_ALC_LEN_SFT 18
++#define RX_ID_ALC_LEN_HI 26
++#define RX_ID_ALC_LEN_SZ 9
++#define CH_ARB_EN_MSK 0x00000001
++#define CH_ARB_EN_I_MSK 0xfffffffe
++#define CH_ARB_EN_SFT 0
++#define CH_ARB_EN_HI 0
++#define CH_ARB_EN_SZ 1
++#define CH_PRI1_MSK 0x00000030
++#define CH_PRI1_I_MSK 0xffffffcf
++#define CH_PRI1_SFT 4
++#define CH_PRI1_HI 5
++#define CH_PRI1_SZ 2
++#define CH_PRI2_MSK 0x00000300
++#define CH_PRI2_I_MSK 0xfffffcff
++#define CH_PRI2_SFT 8
++#define CH_PRI2_HI 9
++#define CH_PRI2_SZ 2
++#define CH_PRI3_MSK 0x00003000
++#define CH_PRI3_I_MSK 0xffffcfff
++#define CH_PRI3_SFT 12
++#define CH_PRI3_HI 13
++#define CH_PRI3_SZ 2
++#define CH_PRI4_MSK 0x00030000
++#define CH_PRI4_I_MSK 0xfffcffff
++#define CH_PRI4_SFT 16
++#define CH_PRI4_HI 17
++#define CH_PRI4_SZ 2
++#define TX_ID_REMAIN_MSK 0x0000007f
++#define TX_ID_REMAIN_I_MSK 0xffffff80
++#define TX_ID_REMAIN_SFT 0
++#define TX_ID_REMAIN_HI 6
++#define TX_ID_REMAIN_SZ 7
++#define TX_PAGE_REMAIN_MSK 0x0001ff00
++#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff
++#define TX_PAGE_REMAIN_SFT 8
++#define TX_PAGE_REMAIN_HI 16
++#define TX_PAGE_REMAIN_SZ 9
++#define ID_PAGE_MAX_SIZE_MSK 0x000001ff
++#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00
++#define ID_PAGE_MAX_SIZE_SFT 0
++#define ID_PAGE_MAX_SIZE_HI 8
++#define ID_PAGE_MAX_SIZE_SZ 9
++#define TX_PAGE_LIMIT_MSK 0x000001ff
++#define TX_PAGE_LIMIT_I_MSK 0xfffffe00
++#define TX_PAGE_LIMIT_SFT 0
++#define TX_PAGE_LIMIT_HI 8
++#define TX_PAGE_LIMIT_SZ 9
++#define TX_COUNT_LIMIT_MSK 0x00ff0000
++#define TX_COUNT_LIMIT_I_MSK 0xff00ffff
++#define TX_COUNT_LIMIT_SFT 16
++#define TX_COUNT_LIMIT_HI 23
++#define TX_COUNT_LIMIT_SZ 8
++#define TX_LIMIT_INT_MSK 0x40000000
++#define TX_LIMIT_INT_I_MSK 0xbfffffff
++#define TX_LIMIT_INT_SFT 30
++#define TX_LIMIT_INT_HI 30
++#define TX_LIMIT_INT_SZ 1
++#define TX_LIMIT_INT_EN_MSK 0x80000000
++#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff
++#define TX_LIMIT_INT_EN_SFT 31
++#define TX_LIMIT_INT_EN_HI 31
++#define TX_LIMIT_INT_EN_SZ 1
++#define TX_PAGE_USE_7_0_MSK 0x000000ff
++#define TX_PAGE_USE_7_0_I_MSK 0xffffff00
++#define TX_PAGE_USE_7_0_SFT 0
++#define TX_PAGE_USE_7_0_HI 7
++#define TX_PAGE_USE_7_0_SZ 8
++#define TX_ID_USE_5_0_MSK 0x00003f00
++#define TX_ID_USE_5_0_I_MSK 0xffffc0ff
++#define TX_ID_USE_5_0_SFT 8
++#define TX_ID_USE_5_0_HI 13
++#define TX_ID_USE_5_0_SZ 6
++#define EDCA0_FFO_CNT_MSK 0x0003c000
++#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff
++#define EDCA0_FFO_CNT_SFT 14
++#define EDCA0_FFO_CNT_HI 17
++#define EDCA0_FFO_CNT_SZ 4
++#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000
++#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff
++#define EDCA1_FFO_CNT_3_0_SFT 18
++#define EDCA1_FFO_CNT_3_0_HI 21
++#define EDCA1_FFO_CNT_3_0_SZ 4
++#define EDCA2_FFO_CNT_MSK 0x07c00000
++#define EDCA2_FFO_CNT_I_MSK 0xf83fffff
++#define EDCA2_FFO_CNT_SFT 22
++#define EDCA2_FFO_CNT_HI 26
++#define EDCA2_FFO_CNT_SZ 5
++#define EDCA3_FFO_CNT_MSK 0xf8000000
++#define EDCA3_FFO_CNT_I_MSK 0x07ffffff
++#define EDCA3_FFO_CNT_SFT 27
++#define EDCA3_FFO_CNT_HI 31
++#define EDCA3_FFO_CNT_SZ 5
++#define ID_TB2_MSK 0xffffffff
++#define ID_TB2_I_MSK 0x00000000
++#define ID_TB2_SFT 0
++#define ID_TB2_HI 31
++#define ID_TB2_SZ 32
++#define ID_TB3_MSK 0xffffffff
++#define ID_TB3_I_MSK 0x00000000
++#define ID_TB3_SFT 0
++#define ID_TB3_HI 31
++#define ID_TB3_SZ 32
++#define TX_ID_TB2_MSK 0xffffffff
++#define TX_ID_TB2_I_MSK 0x00000000
++#define TX_ID_TB2_SFT 0
++#define TX_ID_TB2_HI 31
++#define TX_ID_TB2_SZ 32
++#define TX_ID_TB3_MSK 0xffffffff
++#define TX_ID_TB3_I_MSK 0x00000000
++#define TX_ID_TB3_SFT 0
++#define TX_ID_TB3_HI 31
++#define TX_ID_TB3_SZ 32
++#define RX_ID_TB2_MSK 0xffffffff
++#define RX_ID_TB2_I_MSK 0x00000000
++#define RX_ID_TB2_SFT 0
++#define RX_ID_TB2_HI 31
++#define RX_ID_TB2_SZ 32
++#define RX_ID_TB3_MSK 0xffffffff
++#define RX_ID_TB3_I_MSK 0x00000000
++#define RX_ID_TB3_SFT 0
++#define RX_ID_TB3_HI 31
++#define RX_ID_TB3_SZ 32
++#define TX_PAGE_USE2_MSK 0x000001ff
++#define TX_PAGE_USE2_I_MSK 0xfffffe00
++#define TX_PAGE_USE2_SFT 0
++#define TX_PAGE_USE2_HI 8
++#define TX_PAGE_USE2_SZ 9
++#define TX_ID_USE2_MSK 0x0001fe00
++#define TX_ID_USE2_I_MSK 0xfffe01ff
++#define TX_ID_USE2_SFT 9
++#define TX_ID_USE2_HI 16
++#define TX_ID_USE2_SZ 8
++#define EDCA4_FFO_CNT_MSK 0x001e0000
++#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff
++#define EDCA4_FFO_CNT_SFT 17
++#define EDCA4_FFO_CNT_HI 20
++#define EDCA4_FFO_CNT_SZ 4
++#define TX_PAGE_USE3_MSK 0x000001ff
++#define TX_PAGE_USE3_I_MSK 0xfffffe00
++#define TX_PAGE_USE3_SFT 0
++#define TX_PAGE_USE3_HI 8
++#define TX_PAGE_USE3_SZ 9
++#define TX_ID_USE3_MSK 0x0001fe00
++#define TX_ID_USE3_I_MSK 0xfffe01ff
++#define TX_ID_USE3_SFT 9
++#define TX_ID_USE3_HI 16
++#define TX_ID_USE3_SZ 8
++#define EDCA1_FFO_CNT2_MSK 0x03e00000
++#define EDCA1_FFO_CNT2_I_MSK 0xfc1fffff
++#define EDCA1_FFO_CNT2_SFT 21
++#define EDCA1_FFO_CNT2_HI 25
++#define EDCA1_FFO_CNT2_SZ 5
++#define EDCA4_FFO_CNT2_MSK 0x3c000000
++#define EDCA4_FFO_CNT2_I_MSK 0xc3ffffff
++#define EDCA4_FFO_CNT2_SFT 26
++#define EDCA4_FFO_CNT2_HI 29
++#define EDCA4_FFO_CNT2_SZ 4
++#define TX_PAGE_USE4_MSK 0x000001ff
++#define TX_PAGE_USE4_I_MSK 0xfffffe00
++#define TX_PAGE_USE4_SFT 0
++#define TX_PAGE_USE4_HI 8
++#define TX_PAGE_USE4_SZ 9
++#define TX_ID_USE4_MSK 0x0001fe00
++#define TX_ID_USE4_I_MSK 0xfffe01ff
++#define TX_ID_USE4_SFT 9
++#define TX_ID_USE4_HI 16
++#define TX_ID_USE4_SZ 8
++#define EDCA2_FFO_CNT2_MSK 0x003e0000
++#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff
++#define EDCA2_FFO_CNT2_SFT 17
++#define EDCA2_FFO_CNT2_HI 21
++#define EDCA2_FFO_CNT2_SZ 5
++#define EDCA3_FFO_CNT2_MSK 0x07c00000
++#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff
++#define EDCA3_FFO_CNT2_SFT 22
++#define EDCA3_FFO_CNT2_HI 26
++#define EDCA3_FFO_CNT2_SZ 5
++#define TX_ID_IFO_LEN_MSK 0x000001ff
++#define TX_ID_IFO_LEN_I_MSK 0xfffffe00
++#define TX_ID_IFO_LEN_SFT 0
++#define TX_ID_IFO_LEN_HI 8
++#define TX_ID_IFO_LEN_SZ 9
++#define RX_ID_IFO_LEN_MSK 0x01ff0000
++#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff
++#define RX_ID_IFO_LEN_SFT 16
++#define RX_ID_IFO_LEN_HI 24
++#define RX_ID_IFO_LEN_SZ 9
++#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff
++#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00
++#define MAX_ALL_ALC_ID_CNT_SFT 0
++#define MAX_ALL_ALC_ID_CNT_HI 7
++#define MAX_ALL_ALC_ID_CNT_SZ 8
++#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00
++#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff
++#define MAX_TX_ALC_ID_CNT_SFT 8
++#define MAX_TX_ALC_ID_CNT_HI 15
++#define MAX_TX_ALC_ID_CNT_SZ 8
++#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000
++#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff
++#define MAX_RX_ALC_ID_CNT_SFT 16
++#define MAX_RX_ALC_ID_CNT_HI 23
++#define MAX_RX_ALC_ID_CNT_SZ 8
++#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff
++#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00
++#define MAX_ALL_ID_ALC_LEN_SFT 0
++#define MAX_ALL_ID_ALC_LEN_HI 8
++#define MAX_ALL_ID_ALC_LEN_SZ 9
++#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00
++#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff
++#define MAX_TX_ID_ALC_LEN_SFT 9
++#define MAX_TX_ID_ALC_LEN_HI 17
++#define MAX_TX_ID_ALC_LEN_SZ 9
++#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000
++#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff
++#define MAX_RX_ID_ALC_LEN_SFT 18
++#define MAX_RX_ID_ALC_LEN_HI 26
++#define MAX_RX_ID_ALC_LEN_SZ 9
++#define RG_PMDLBK_MSK 0x00000001
++#define RG_PMDLBK_I_MSK 0xfffffffe
++#define RG_PMDLBK_SFT 0
++#define RG_PMDLBK_HI 0
++#define RG_PMDLBK_SZ 1
++#define RG_RDYACK_SEL_MSK 0x00000006
++#define RG_RDYACK_SEL_I_MSK 0xfffffff9
++#define RG_RDYACK_SEL_SFT 1
++#define RG_RDYACK_SEL_HI 2
++#define RG_RDYACK_SEL_SZ 2
++#define RG_ADEDGE_SEL_MSK 0x00000008
++#define RG_ADEDGE_SEL_I_MSK 0xfffffff7
++#define RG_ADEDGE_SEL_SFT 3
++#define RG_ADEDGE_SEL_HI 3
++#define RG_ADEDGE_SEL_SZ 1
++#define RG_SIGN_SWAP_MSK 0x00000010
++#define RG_SIGN_SWAP_I_MSK 0xffffffef
++#define RG_SIGN_SWAP_SFT 4
++#define RG_SIGN_SWAP_HI 4
++#define RG_SIGN_SWAP_SZ 1
++#define RG_IQ_SWAP_MSK 0x00000020
++#define RG_IQ_SWAP_I_MSK 0xffffffdf
++#define RG_IQ_SWAP_SFT 5
++#define RG_IQ_SWAP_HI 5
++#define RG_IQ_SWAP_SZ 1
++#define RG_Q_INV_MSK 0x00000040
++#define RG_Q_INV_I_MSK 0xffffffbf
++#define RG_Q_INV_SFT 6
++#define RG_Q_INV_HI 6
++#define RG_Q_INV_SZ 1
++#define RG_I_INV_MSK 0x00000080
++#define RG_I_INV_I_MSK 0xffffff7f
++#define RG_I_INV_SFT 7
++#define RG_I_INV_HI 7
++#define RG_I_INV_SZ 1
++#define RG_BYPASS_ACI_MSK 0x00000100
++#define RG_BYPASS_ACI_I_MSK 0xfffffeff
++#define RG_BYPASS_ACI_SFT 8
++#define RG_BYPASS_ACI_HI 8
++#define RG_BYPASS_ACI_SZ 1
++#define RG_LBK_ANA_PATH_MSK 0x00000200
++#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff
++#define RG_LBK_ANA_PATH_SFT 9
++#define RG_LBK_ANA_PATH_HI 9
++#define RG_LBK_ANA_PATH_SZ 1
++#define RG_SPECTRUM_LEAKY_FACTOR_MSK 0x00000c00
++#define RG_SPECTRUM_LEAKY_FACTOR_I_MSK 0xfffff3ff
++#define RG_SPECTRUM_LEAKY_FACTOR_SFT 10
++#define RG_SPECTRUM_LEAKY_FACTOR_HI 11
++#define RG_SPECTRUM_LEAKY_FACTOR_SZ 2
++#define RG_SPECTRUM_BW_MSK 0x00003000
++#define RG_SPECTRUM_BW_I_MSK 0xffffcfff
++#define RG_SPECTRUM_BW_SFT 12
++#define RG_SPECTRUM_BW_HI 13
++#define RG_SPECTRUM_BW_SZ 2
++#define RG_SPECTRUM_FREQ_MANUAL_MSK 0x00004000
++#define RG_SPECTRUM_FREQ_MANUAL_I_MSK 0xffffbfff
++#define RG_SPECTRUM_FREQ_MANUAL_SFT 14
++#define RG_SPECTRUM_FREQ_MANUAL_HI 14
++#define RG_SPECTRUM_FREQ_MANUAL_SZ 1
++#define RG_SPECTRUM_EN_MSK 0x00008000
++#define RG_SPECTRUM_EN_I_MSK 0xffff7fff
++#define RG_SPECTRUM_EN_SFT 15
++#define RG_SPECTRUM_EN_HI 15
++#define RG_SPECTRUM_EN_SZ 1
++#define RG_TXPWRLVL_SET_MSK 0x00ff0000
++#define RG_TXPWRLVL_SET_I_MSK 0xff00ffff
++#define RG_TXPWRLVL_SET_SFT 16
++#define RG_TXPWRLVL_SET_HI 23
++#define RG_TXPWRLVL_SET_SZ 8
++#define RG_TXPWRLVL_SEL_MSK 0x01000000
++#define RG_TXPWRLVL_SEL_I_MSK 0xfeffffff
++#define RG_TXPWRLVL_SEL_SFT 24
++#define RG_TXPWRLVL_SEL_HI 24
++#define RG_TXPWRLVL_SEL_SZ 1
++#define RG_RF_BB_CLK_SEL_MSK 0x80000000
++#define RG_RF_BB_CLK_SEL_I_MSK 0x7fffffff
++#define RG_RF_BB_CLK_SEL_SFT 31
++#define RG_RF_BB_CLK_SEL_HI 31
++#define RG_RF_BB_CLK_SEL_SZ 1
++#define RG_PHY_MD_EN_MSK 0x00000001
++#define RG_PHY_MD_EN_I_MSK 0xfffffffe
++#define RG_PHY_MD_EN_SFT 0
++#define RG_PHY_MD_EN_HI 0
++#define RG_PHY_MD_EN_SZ 1
++#define RG_PHYRX_MD_EN_MSK 0x00000002
++#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd
++#define RG_PHYRX_MD_EN_SFT 1
++#define RG_PHYRX_MD_EN_HI 1
++#define RG_PHYRX_MD_EN_SZ 1
++#define RG_PHYTX_MD_EN_MSK 0x00000004
++#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb
++#define RG_PHYTX_MD_EN_SFT 2
++#define RG_PHYTX_MD_EN_HI 2
++#define RG_PHYTX_MD_EN_SZ 1
++#define RG_PHY11GN_MD_EN_MSK 0x00000008
++#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7
++#define RG_PHY11GN_MD_EN_SFT 3
++#define RG_PHY11GN_MD_EN_HI 3
++#define RG_PHY11GN_MD_EN_SZ 1
++#define RG_PHY11B_MD_EN_MSK 0x00000010
++#define RG_PHY11B_MD_EN_I_MSK 0xffffffef
++#define RG_PHY11B_MD_EN_SFT 4
++#define RG_PHY11B_MD_EN_HI 4
++#define RG_PHY11B_MD_EN_SZ 1
++#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020
++#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf
++#define RG_PHYRXFIFO_MD_EN_SFT 5
++#define RG_PHYRXFIFO_MD_EN_HI 5
++#define RG_PHYRXFIFO_MD_EN_SZ 1
++#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040
++#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf
++#define RG_PHYTXFIFO_MD_EN_SFT 6
++#define RG_PHYTXFIFO_MD_EN_HI 6
++#define RG_PHYTXFIFO_MD_EN_SZ 1
++#define RG_PHY11BGN_MD_EN_MSK 0x00000100
++#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff
++#define RG_PHY11BGN_MD_EN_SFT 8
++#define RG_PHY11BGN_MD_EN_HI 8
++#define RG_PHY11BGN_MD_EN_SZ 1
++#define RG_FORCE_11GN_EN_MSK 0x00001000
++#define RG_FORCE_11GN_EN_I_MSK 0xffffefff
++#define RG_FORCE_11GN_EN_SFT 12
++#define RG_FORCE_11GN_EN_HI 12
++#define RG_FORCE_11GN_EN_SZ 1
++#define RG_FORCE_11B_EN_MSK 0x00002000
++#define RG_FORCE_11B_EN_I_MSK 0xffffdfff
++#define RG_FORCE_11B_EN_SFT 13
++#define RG_FORCE_11B_EN_HI 13
++#define RG_FORCE_11B_EN_SZ 1
++#define RG_FFT_MEM_CLK_EN_RX_MSK 0x00004000
++#define RG_FFT_MEM_CLK_EN_RX_I_MSK 0xffffbfff
++#define RG_FFT_MEM_CLK_EN_RX_SFT 14
++#define RG_FFT_MEM_CLK_EN_RX_HI 14
++#define RG_FFT_MEM_CLK_EN_RX_SZ 1
++#define RG_FFT_MEM_CLK_EN_TX_MSK 0x00008000
++#define RG_FFT_MEM_CLK_EN_TX_I_MSK 0xffff7fff
++#define RG_FFT_MEM_CLK_EN_TX_SFT 15
++#define RG_FFT_MEM_CLK_EN_TX_HI 15
++#define RG_FFT_MEM_CLK_EN_TX_SZ 1
++#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000
++#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff
++#define RG_PHY_IQ_TRIG_SEL_SFT 16
++#define RG_PHY_IQ_TRIG_SEL_HI 19
++#define RG_PHY_IQ_TRIG_SEL_SZ 4
++#define RG_SPECTRUM_FREQ_MSK 0x3ff00000
++#define RG_SPECTRUM_FREQ_I_MSK 0xc00fffff
++#define RG_SPECTRUM_FREQ_SFT 20
++#define RG_SPECTRUM_FREQ_HI 29
++#define RG_SPECTRUM_FREQ_SZ 10
++#define SVN_VERSION_MSK 0xffffffff
++#define SVN_VERSION_I_MSK 0x00000000
++#define SVN_VERSION_SFT 0
++#define SVN_VERSION_HI 31
++#define SVN_VERSION_SZ 32
++#define RG_LENGTH_MSK 0x0000ffff
++#define RG_LENGTH_I_MSK 0xffff0000
++#define RG_LENGTH_SFT 0
++#define RG_LENGTH_HI 15
++#define RG_LENGTH_SZ 16
++#define RG_PKT_MODE_MSK 0x00070000
++#define RG_PKT_MODE_I_MSK 0xfff8ffff
++#define RG_PKT_MODE_SFT 16
++#define RG_PKT_MODE_HI 18
++#define RG_PKT_MODE_SZ 3
++#define RG_CH_BW_MSK 0x00380000
++#define RG_CH_BW_I_MSK 0xffc7ffff
++#define RG_CH_BW_SFT 19
++#define RG_CH_BW_HI 21
++#define RG_CH_BW_SZ 3
++#define RG_PRM_MSK 0x00400000
++#define RG_PRM_I_MSK 0xffbfffff
++#define RG_PRM_SFT 22
++#define RG_PRM_HI 22
++#define RG_PRM_SZ 1
++#define RG_SHORTGI_MSK 0x00800000
++#define RG_SHORTGI_I_MSK 0xff7fffff
++#define RG_SHORTGI_SFT 23
++#define RG_SHORTGI_HI 23
++#define RG_SHORTGI_SZ 1
++#define RG_RATE_MSK 0x7f000000
++#define RG_RATE_I_MSK 0x80ffffff
++#define RG_RATE_SFT 24
++#define RG_RATE_HI 30
++#define RG_RATE_SZ 7
++#define RG_L_LENGTH_MSK 0x00000fff
++#define RG_L_LENGTH_I_MSK 0xfffff000
++#define RG_L_LENGTH_SFT 0
++#define RG_L_LENGTH_HI 11
++#define RG_L_LENGTH_SZ 12
++#define RG_L_RATE_MSK 0x00007000
++#define RG_L_RATE_I_MSK 0xffff8fff
++#define RG_L_RATE_SFT 12
++#define RG_L_RATE_HI 14
++#define RG_L_RATE_SZ 3
++#define RG_SERVICE_MSK 0xffff0000
++#define RG_SERVICE_I_MSK 0x0000ffff
++#define RG_SERVICE_SFT 16
++#define RG_SERVICE_HI 31
++#define RG_SERVICE_SZ 16
++#define RG_SMOOTHING_MSK 0x00000001
++#define RG_SMOOTHING_I_MSK 0xfffffffe
++#define RG_SMOOTHING_SFT 0
++#define RG_SMOOTHING_HI 0
++#define RG_SMOOTHING_SZ 1
++#define RG_NO_SOUND_MSK 0x00000002
++#define RG_NO_SOUND_I_MSK 0xfffffffd
++#define RG_NO_SOUND_SFT 1
++#define RG_NO_SOUND_HI 1
++#define RG_NO_SOUND_SZ 1
++#define RG_AGGREGATE_MSK 0x00000004
++#define RG_AGGREGATE_I_MSK 0xfffffffb
++#define RG_AGGREGATE_SFT 2
++#define RG_AGGREGATE_HI 2
++#define RG_AGGREGATE_SZ 1
++#define RG_STBC_MSK 0x00000018
++#define RG_STBC_I_MSK 0xffffffe7
++#define RG_STBC_SFT 3
++#define RG_STBC_HI 4
++#define RG_STBC_SZ 2
++#define RG_FEC_MSK 0x00000020
++#define RG_FEC_I_MSK 0xffffffdf
++#define RG_FEC_SFT 5
++#define RG_FEC_HI 5
++#define RG_FEC_SZ 1
++#define RG_N_ESS_MSK 0x000000c0
++#define RG_N_ESS_I_MSK 0xffffff3f
++#define RG_N_ESS_SFT 6
++#define RG_N_ESS_HI 7
++#define RG_N_ESS_SZ 2
++#define RG_TXPWRLVL_MSK 0x0000ff00
++#define RG_TXPWRLVL_I_MSK 0xffff00ff
++#define RG_TXPWRLVL_SFT 8
++#define RG_TXPWRLVL_HI 15
++#define RG_TXPWRLVL_SZ 8
++#define RG_TX_START_MSK 0x00000001
++#define RG_TX_START_I_MSK 0xfffffffe
++#define RG_TX_START_SFT 0
++#define RG_TX_START_HI 0
++#define RG_TX_START_SZ 1
++#define RG_IFS_TIME_MSK 0x000000fc
++#define RG_IFS_TIME_I_MSK 0xffffff03
++#define RG_IFS_TIME_SFT 2
++#define RG_IFS_TIME_HI 7
++#define RG_IFS_TIME_SZ 6
++#define RG_CONTINUOUS_DATA_MSK 0x00000100
++#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff
++#define RG_CONTINUOUS_DATA_SFT 8
++#define RG_CONTINUOUS_DATA_HI 8
++#define RG_CONTINUOUS_DATA_SZ 1
++#define RG_DATA_SEL_MSK 0x00000600
++#define RG_DATA_SEL_I_MSK 0xfffff9ff
++#define RG_DATA_SEL_SFT 9
++#define RG_DATA_SEL_HI 10
++#define RG_DATA_SEL_SZ 2
++#define RG_TX_D_MSK 0x00ff0000
++#define RG_TX_D_I_MSK 0xff00ffff
++#define RG_TX_D_SFT 16
++#define RG_TX_D_HI 23
++#define RG_TX_D_SZ 8
++#define RG_TX_CNT_TARGET_MSK 0xffffffff
++#define RG_TX_CNT_TARGET_I_MSK 0x00000000
++#define RG_TX_CNT_TARGET_SFT 0
++#define RG_TX_CNT_TARGET_HI 31
++#define RG_TX_CNT_TARGET_SZ 32
++#define RG_FFT_IFFT_MODE_MSK 0x000000c0
++#define RG_FFT_IFFT_MODE_I_MSK 0xffffff3f
++#define RG_FFT_IFFT_MODE_SFT 6
++#define RG_FFT_IFFT_MODE_HI 7
++#define RG_FFT_IFFT_MODE_SZ 2
++#define RG_DAC_DBG_MODE_MSK 0x00000100
++#define RG_DAC_DBG_MODE_I_MSK 0xfffffeff
++#define RG_DAC_DBG_MODE_SFT 8
++#define RG_DAC_DBG_MODE_HI 8
++#define RG_DAC_DBG_MODE_SZ 1
++#define RG_DAC_SGN_SWAP_MSK 0x00000200
++#define RG_DAC_SGN_SWAP_I_MSK 0xfffffdff
++#define RG_DAC_SGN_SWAP_SFT 9
++#define RG_DAC_SGN_SWAP_HI 9
++#define RG_DAC_SGN_SWAP_SZ 1
++#define RG_TXD_SEL_MSK 0x00000c00
++#define RG_TXD_SEL_I_MSK 0xfffff3ff
++#define RG_TXD_SEL_SFT 10
++#define RG_TXD_SEL_HI 11
++#define RG_TXD_SEL_SZ 2
++#define RG_UP8X_MSK 0x00ff0000
++#define RG_UP8X_I_MSK 0xff00ffff
++#define RG_UP8X_SFT 16
++#define RG_UP8X_HI 23
++#define RG_UP8X_SZ 8
++#define RG_IQ_DC_BYP_MSK 0x01000000
++#define RG_IQ_DC_BYP_I_MSK 0xfeffffff
++#define RG_IQ_DC_BYP_SFT 24
++#define RG_IQ_DC_BYP_HI 24
++#define RG_IQ_DC_BYP_SZ 1
++#define RG_IQ_DC_LEAKY_FACTOR_MSK 0x30000000
++#define RG_IQ_DC_LEAKY_FACTOR_I_MSK 0xcfffffff
++#define RG_IQ_DC_LEAKY_FACTOR_SFT 28
++#define RG_IQ_DC_LEAKY_FACTOR_HI 29
++#define RG_IQ_DC_LEAKY_FACTOR_SZ 2
++#define RG_DAC_DCEN_MSK 0x00000001
++#define RG_DAC_DCEN_I_MSK 0xfffffffe
++#define RG_DAC_DCEN_SFT 0
++#define RG_DAC_DCEN_HI 0
++#define RG_DAC_DCEN_SZ 1
++#define RG_DAC_DCQ_MSK 0x00003ff0
++#define RG_DAC_DCQ_I_MSK 0xffffc00f
++#define RG_DAC_DCQ_SFT 4
++#define RG_DAC_DCQ_HI 13
++#define RG_DAC_DCQ_SZ 10
++#define RG_DAC_DCI_MSK 0x03ff0000
++#define RG_DAC_DCI_I_MSK 0xfc00ffff
++#define RG_DAC_DCI_SFT 16
++#define RG_DAC_DCI_HI 25
++#define RG_DAC_DCI_SZ 10
++#define RG_PGA_REFDB_SAT_MSK 0x0000007f
++#define RG_PGA_REFDB_SAT_I_MSK 0xffffff80
++#define RG_PGA_REFDB_SAT_SFT 0
++#define RG_PGA_REFDB_SAT_HI 6
++#define RG_PGA_REFDB_SAT_SZ 7
++#define RG_PGA_REFDB_TOP_MSK 0x00007f00
++#define RG_PGA_REFDB_TOP_I_MSK 0xffff80ff
++#define RG_PGA_REFDB_TOP_SFT 8
++#define RG_PGA_REFDB_TOP_HI 14
++#define RG_PGA_REFDB_TOP_SZ 7
++#define RG_PGA_REF_UND_MSK 0x03ff0000
++#define RG_PGA_REF_UND_I_MSK 0xfc00ffff
++#define RG_PGA_REF_UND_SFT 16
++#define RG_PGA_REF_UND_HI 25
++#define RG_PGA_REF_UND_SZ 10
++#define RG_RF_REF_SAT_MSK 0xf0000000
++#define RG_RF_REF_SAT_I_MSK 0x0fffffff
++#define RG_RF_REF_SAT_SFT 28
++#define RG_RF_REF_SAT_HI 31
++#define RG_RF_REF_SAT_SZ 4
++#define RG_PGAGC_SET_MSK 0x0000000f
++#define RG_PGAGC_SET_I_MSK 0xfffffff0
++#define RG_PGAGC_SET_SFT 0
++#define RG_PGAGC_SET_HI 3
++#define RG_PGAGC_SET_SZ 4
++#define RG_PGAGC_OW_MSK 0x00000010
++#define RG_PGAGC_OW_I_MSK 0xffffffef
++#define RG_PGAGC_OW_SFT 4
++#define RG_PGAGC_OW_HI 4
++#define RG_PGAGC_OW_SZ 1
++#define RG_RFGC_SET_MSK 0x00000060
++#define RG_RFGC_SET_I_MSK 0xffffff9f
++#define RG_RFGC_SET_SFT 5
++#define RG_RFGC_SET_HI 6
++#define RG_RFGC_SET_SZ 2
++#define RG_RFGC_OW_MSK 0x00000080
++#define RG_RFGC_OW_I_MSK 0xffffff7f
++#define RG_RFGC_OW_SFT 7
++#define RG_RFGC_OW_HI 7
++#define RG_RFGC_OW_SZ 1
++#define RG_WAIT_T_RXAGC_MSK 0x00003f00
++#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff
++#define RG_WAIT_T_RXAGC_SFT 8
++#define RG_WAIT_T_RXAGC_HI 13
++#define RG_WAIT_T_RXAGC_SZ 6
++#define RG_RXAGC_SET_MSK 0x00004000
++#define RG_RXAGC_SET_I_MSK 0xffffbfff
++#define RG_RXAGC_SET_SFT 14
++#define RG_RXAGC_SET_HI 14
++#define RG_RXAGC_SET_SZ 1
++#define RG_RXAGC_OW_MSK 0x00008000
++#define RG_RXAGC_OW_I_MSK 0xffff7fff
++#define RG_RXAGC_OW_SFT 15
++#define RG_RXAGC_OW_HI 15
++#define RG_RXAGC_OW_SZ 1
++#define RG_WAIT_T_FINAL_MSK 0x003f0000
++#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff
++#define RG_WAIT_T_FINAL_SFT 16
++#define RG_WAIT_T_FINAL_HI 21
++#define RG_WAIT_T_FINAL_SZ 6
++#define RG_WAIT_T_MSK 0x3f000000
++#define RG_WAIT_T_I_MSK 0xc0ffffff
++#define RG_WAIT_T_SFT 24
++#define RG_WAIT_T_HI 29
++#define RG_WAIT_T_SZ 6
++#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f
++#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0
++#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0
++#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3
++#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4
++#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0
++#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f
++#define RG_LG_PGA_UND_PGA_GAIN_SFT 4
++#define RG_LG_PGA_UND_PGA_GAIN_HI 7
++#define RG_LG_PGA_UND_PGA_GAIN_SZ 4
++#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00
++#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff
++#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8
++#define RG_LG_PGA_SAT_PGA_GAIN_HI 11
++#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4
++#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000
++#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff
++#define RG_LG_RF_SAT_PGA_GAIN_SFT 12
++#define RG_LG_RF_SAT_PGA_GAIN_HI 15
++#define RG_LG_RF_SAT_PGA_GAIN_SZ 4
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4
++#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000
++#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff
++#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20
++#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23
++#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4
++#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000
++#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff
++#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24
++#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27
++#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4
++#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000
++#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff
++#define RG_HG_RF_SAT_PGA_GAIN_SFT 28
++#define RG_HG_RF_SAT_PGA_GAIN_HI 31
++#define RG_HG_RF_SAT_PGA_GAIN_SZ 4
++#define RG_MG_PGA_JB_TH_MSK 0x0000000f
++#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0
++#define RG_MG_PGA_JB_TH_SFT 0
++#define RG_MG_PGA_JB_TH_HI 3
++#define RG_MG_PGA_JB_TH_SZ 4
++#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000
++#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff
++#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16
++#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20
++#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5
++#define RG_WR_RFGC_INIT_SET_MSK 0x00600000
++#define RG_WR_RFGC_INIT_SET_I_MSK 0xff9fffff
++#define RG_WR_RFGC_INIT_SET_SFT 21
++#define RG_WR_RFGC_INIT_SET_HI 22
++#define RG_WR_RFGC_INIT_SET_SZ 2
++#define RG_WR_RFGC_INIT_EN_MSK 0x00800000
++#define RG_WR_RFGC_INIT_EN_I_MSK 0xff7fffff
++#define RG_WR_RFGC_INIT_EN_SFT 23
++#define RG_WR_RFGC_INIT_EN_HI 23
++#define RG_WR_RFGC_INIT_EN_SZ 1
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5
++#define RG_AGC_THRESHOLD_MSK 0x00003fff
++#define RG_AGC_THRESHOLD_I_MSK 0xffffc000
++#define RG_AGC_THRESHOLD_SFT 0
++#define RG_AGC_THRESHOLD_HI 13
++#define RG_AGC_THRESHOLD_SZ 14
++#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000
++#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff
++#define RG_ACI_POINT_CNT_LMT_11B_SFT 16
++#define RG_ACI_POINT_CNT_LMT_11B_HI 22
++#define RG_ACI_POINT_CNT_LMT_11B_SZ 7
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2
++#define RG_WR_ACI_GAIN_INI_SEL_11B_MSK 0x000000ff
++#define RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK 0xffffff00
++#define RG_WR_ACI_GAIN_INI_SEL_11B_SFT 0
++#define RG_WR_ACI_GAIN_INI_SEL_11B_HI 7
++#define RG_WR_ACI_GAIN_INI_SEL_11B_SZ 8
++#define RG_WR_ACI_GAIN_SEL_11B_MSK 0x0000ff00
++#define RG_WR_ACI_GAIN_SEL_11B_I_MSK 0xffff00ff
++#define RG_WR_ACI_GAIN_SEL_11B_SFT 8
++#define RG_WR_ACI_GAIN_SEL_11B_HI 15
++#define RG_WR_ACI_GAIN_SEL_11B_SZ 8
++#define RG_ACI_DAGC_SET_VALUE_11B_MSK 0x007f0000
++#define RG_ACI_DAGC_SET_VALUE_11B_I_MSK 0xff80ffff
++#define RG_ACI_DAGC_SET_VALUE_11B_SFT 16
++#define RG_ACI_DAGC_SET_VALUE_11B_HI 22
++#define RG_ACI_DAGC_SET_VALUE_11B_SZ 7
++#define RG_WR_ACI_GAIN_OW_11B_MSK 0x80000000
++#define RG_WR_ACI_GAIN_OW_11B_I_MSK 0x7fffffff
++#define RG_WR_ACI_GAIN_OW_11B_SFT 31
++#define RG_WR_ACI_GAIN_OW_11B_HI 31
++#define RG_WR_ACI_GAIN_OW_11B_SZ 1
++#define RG_ACI_POINT_CNT_LMT_11GN_MSK 0x000000ff
++#define RG_ACI_POINT_CNT_LMT_11GN_I_MSK 0xffffff00
++#define RG_ACI_POINT_CNT_LMT_11GN_SFT 0
++#define RG_ACI_POINT_CNT_LMT_11GN_HI 7
++#define RG_ACI_POINT_CNT_LMT_11GN_SZ 8
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK 0x00000300
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK 0xfffffcff
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT 8
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI 9
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ 2
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8
++#define RG_ACI_DAGC_SET_VALUE_11GN_MSK 0x0000007f
++#define RG_ACI_DAGC_SET_VALUE_11GN_I_MSK 0xffffff80
++#define RG_ACI_DAGC_SET_VALUE_11GN_SFT 0
++#define RG_ACI_DAGC_SET_VALUE_11GN_HI 6
++#define RG_ACI_DAGC_SET_VALUE_11GN_SZ 7
++#define RG_ACI_GAIN_INI_VAL_11GN_MSK 0x0000ff00
++#define RG_ACI_GAIN_INI_VAL_11GN_I_MSK 0xffff00ff
++#define RG_ACI_GAIN_INI_VAL_11GN_SFT 8
++#define RG_ACI_GAIN_INI_VAL_11GN_HI 15
++#define RG_ACI_GAIN_INI_VAL_11GN_SZ 8
++#define RG_ACI_GAIN_OW_VAL_11GN_MSK 0x00ff0000
++#define RG_ACI_GAIN_OW_VAL_11GN_I_MSK 0xff00ffff
++#define RG_ACI_GAIN_OW_VAL_11GN_SFT 16
++#define RG_ACI_GAIN_OW_VAL_11GN_HI 23
++#define RG_ACI_GAIN_OW_VAL_11GN_SZ 8
++#define RG_ACI_GAIN_OW_11GN_MSK 0x80000000
++#define RG_ACI_GAIN_OW_11GN_I_MSK 0x7fffffff
++#define RG_ACI_GAIN_OW_11GN_SFT 31
++#define RG_ACI_GAIN_OW_11GN_HI 31
++#define RG_ACI_GAIN_OW_11GN_SZ 1
++#define RO_CCA_PWR_MA_11GN_MSK 0x0000007f
++#define RO_CCA_PWR_MA_11GN_I_MSK 0xffffff80
++#define RO_CCA_PWR_MA_11GN_SFT 0
++#define RO_CCA_PWR_MA_11GN_HI 6
++#define RO_CCA_PWR_MA_11GN_SZ 7
++#define RO_ED_STATE_MSK 0x00008000
++#define RO_ED_STATE_I_MSK 0xffff7fff
++#define RO_ED_STATE_SFT 15
++#define RO_ED_STATE_HI 15
++#define RO_ED_STATE_SZ 1
++#define RO_CCA_PWR_MA_11B_MSK 0x007f0000
++#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff
++#define RO_CCA_PWR_MA_11B_SFT 16
++#define RO_CCA_PWR_MA_11B_HI 22
++#define RO_CCA_PWR_MA_11B_SZ 7
++#define RO_PGA_PWR_FF1_MSK 0x00003fff
++#define RO_PGA_PWR_FF1_I_MSK 0xffffc000
++#define RO_PGA_PWR_FF1_SFT 0
++#define RO_PGA_PWR_FF1_HI 13
++#define RO_PGA_PWR_FF1_SZ 14
++#define RO_RF_PWR_FF1_MSK 0x000f0000
++#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff
++#define RO_RF_PWR_FF1_SFT 16
++#define RO_RF_PWR_FF1_HI 19
++#define RO_RF_PWR_FF1_SZ 4
++#define RO_PGAGC_FF1_MSK 0x0f000000
++#define RO_PGAGC_FF1_I_MSK 0xf0ffffff
++#define RO_PGAGC_FF1_SFT 24
++#define RO_PGAGC_FF1_HI 27
++#define RO_PGAGC_FF1_SZ 4
++#define RO_RFGC_FF1_MSK 0x30000000
++#define RO_RFGC_FF1_I_MSK 0xcfffffff
++#define RO_RFGC_FF1_SFT 28
++#define RO_RFGC_FF1_HI 29
++#define RO_RFGC_FF1_SZ 2
++#define RO_PGA_PWR_FF2_MSK 0x00003fff
++#define RO_PGA_PWR_FF2_I_MSK 0xffffc000
++#define RO_PGA_PWR_FF2_SFT 0
++#define RO_PGA_PWR_FF2_HI 13
++#define RO_PGA_PWR_FF2_SZ 14
++#define RO_RF_PWR_FF2_MSK 0x000f0000
++#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff
++#define RO_RF_PWR_FF2_SFT 16
++#define RO_RF_PWR_FF2_HI 19
++#define RO_RF_PWR_FF2_SZ 4
++#define RO_PGAGC_FF2_MSK 0x0f000000
++#define RO_PGAGC_FF2_I_MSK 0xf0ffffff
++#define RO_PGAGC_FF2_SFT 24
++#define RO_PGAGC_FF2_HI 27
++#define RO_PGAGC_FF2_SZ 4
++#define RO_RFGC_FF2_MSK 0x30000000
++#define RO_RFGC_FF2_I_MSK 0xcfffffff
++#define RO_RFGC_FF2_SFT 28
++#define RO_RFGC_FF2_HI 29
++#define RO_RFGC_FF2_SZ 2
++#define RO_PGA_PWR_FF3_MSK 0x00003fff
++#define RO_PGA_PWR_FF3_I_MSK 0xffffc000
++#define RO_PGA_PWR_FF3_SFT 0
++#define RO_PGA_PWR_FF3_HI 13
++#define RO_PGA_PWR_FF3_SZ 14
++#define RO_RF_PWR_FF3_MSK 0x000f0000
++#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff
++#define RO_RF_PWR_FF3_SFT 16
++#define RO_RF_PWR_FF3_HI 19
++#define RO_RF_PWR_FF3_SZ 4
++#define RO_PGAGC_FF3_MSK 0x0f000000
++#define RO_PGAGC_FF3_I_MSK 0xf0ffffff
++#define RO_PGAGC_FF3_SFT 24
++#define RO_PGAGC_FF3_HI 27
++#define RO_PGAGC_FF3_SZ 4
++#define RO_RFGC_FF3_MSK 0x30000000
++#define RO_RFGC_FF3_I_MSK 0xcfffffff
++#define RO_RFGC_FF3_SFT 28
++#define RO_RFGC_FF3_HI 29
++#define RO_RFGC_FF3_SZ 2
++#define RG_TX_DES_RATE_MSK 0x0000001f
++#define RG_TX_DES_RATE_I_MSK 0xffffffe0
++#define RG_TX_DES_RATE_SFT 0
++#define RG_TX_DES_RATE_HI 4
++#define RG_TX_DES_RATE_SZ 5
++#define RG_TX_DES_MODE_MSK 0x00001f00
++#define RG_TX_DES_MODE_I_MSK 0xffffe0ff
++#define RG_TX_DES_MODE_SFT 8
++#define RG_TX_DES_MODE_HI 12
++#define RG_TX_DES_MODE_SZ 5
++#define RG_TX_DES_LEN_LO_MSK 0x001f0000
++#define RG_TX_DES_LEN_LO_I_MSK 0xffe0ffff
++#define RG_TX_DES_LEN_LO_SFT 16
++#define RG_TX_DES_LEN_LO_HI 20
++#define RG_TX_DES_LEN_LO_SZ 5
++#define RG_TX_DES_LEN_UP_MSK 0x1f000000
++#define RG_TX_DES_LEN_UP_I_MSK 0xe0ffffff
++#define RG_TX_DES_LEN_UP_SFT 24
++#define RG_TX_DES_LEN_UP_HI 28
++#define RG_TX_DES_LEN_UP_SZ 5
++#define RG_TX_DES_SRVC_UP_MSK 0x0000001f
++#define RG_TX_DES_SRVC_UP_I_MSK 0xffffffe0
++#define RG_TX_DES_SRVC_UP_SFT 0
++#define RG_TX_DES_SRVC_UP_HI 4
++#define RG_TX_DES_SRVC_UP_SZ 5
++#define RG_TX_DES_L_LEN_LO_MSK 0x00001f00
++#define RG_TX_DES_L_LEN_LO_I_MSK 0xffffe0ff
++#define RG_TX_DES_L_LEN_LO_SFT 8
++#define RG_TX_DES_L_LEN_LO_HI 12
++#define RG_TX_DES_L_LEN_LO_SZ 5
++#define RG_TX_DES_L_LEN_UP_MSK 0x001f0000
++#define RG_TX_DES_L_LEN_UP_I_MSK 0xffe0ffff
++#define RG_TX_DES_L_LEN_UP_SFT 16
++#define RG_TX_DES_L_LEN_UP_HI 20
++#define RG_TX_DES_L_LEN_UP_SZ 5
++#define RG_TX_DES_TYPE_MSK 0x1f000000
++#define RG_TX_DES_TYPE_I_MSK 0xe0ffffff
++#define RG_TX_DES_TYPE_SFT 24
++#define RG_TX_DES_TYPE_HI 28
++#define RG_TX_DES_TYPE_SZ 5
++#define RG_TX_DES_L_LEN_UP_COMB_MSK 0x00000001
++#define RG_TX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
++#define RG_TX_DES_L_LEN_UP_COMB_SFT 0
++#define RG_TX_DES_L_LEN_UP_COMB_HI 0
++#define RG_TX_DES_L_LEN_UP_COMB_SZ 1
++#define RG_TX_DES_TYPE_COMB_MSK 0x00000010
++#define RG_TX_DES_TYPE_COMB_I_MSK 0xffffffef
++#define RG_TX_DES_TYPE_COMB_SFT 4
++#define RG_TX_DES_TYPE_COMB_HI 4
++#define RG_TX_DES_TYPE_COMB_SZ 1
++#define RG_TX_DES_RATE_COMB_MSK 0x00000100
++#define RG_TX_DES_RATE_COMB_I_MSK 0xfffffeff
++#define RG_TX_DES_RATE_COMB_SFT 8
++#define RG_TX_DES_RATE_COMB_HI 8
++#define RG_TX_DES_RATE_COMB_SZ 1
++#define RG_TX_DES_MODE_COMB_MSK 0x00001000
++#define RG_TX_DES_MODE_COMB_I_MSK 0xffffefff
++#define RG_TX_DES_MODE_COMB_SFT 12
++#define RG_TX_DES_MODE_COMB_HI 12
++#define RG_TX_DES_MODE_COMB_SZ 1
++#define RG_TX_DES_PWRLVL_MSK 0x001f0000
++#define RG_TX_DES_PWRLVL_I_MSK 0xffe0ffff
++#define RG_TX_DES_PWRLVL_SFT 16
++#define RG_TX_DES_PWRLVL_HI 20
++#define RG_TX_DES_PWRLVL_SZ 5
++#define RG_TX_DES_SRVC_LO_MSK 0x1f000000
++#define RG_TX_DES_SRVC_LO_I_MSK 0xe0ffffff
++#define RG_TX_DES_SRVC_LO_SFT 24
++#define RG_TX_DES_SRVC_LO_HI 28
++#define RG_TX_DES_SRVC_LO_SZ 5
++#define RG_RX_DES_RATE_MSK 0x0000003f
++#define RG_RX_DES_RATE_I_MSK 0xffffffc0
++#define RG_RX_DES_RATE_SFT 0
++#define RG_RX_DES_RATE_HI 5
++#define RG_RX_DES_RATE_SZ 6
++#define RG_RX_DES_MODE_MSK 0x00003f00
++#define RG_RX_DES_MODE_I_MSK 0xffffc0ff
++#define RG_RX_DES_MODE_SFT 8
++#define RG_RX_DES_MODE_HI 13
++#define RG_RX_DES_MODE_SZ 6
++#define RG_RX_DES_LEN_LO_MSK 0x003f0000
++#define RG_RX_DES_LEN_LO_I_MSK 0xffc0ffff
++#define RG_RX_DES_LEN_LO_SFT 16
++#define RG_RX_DES_LEN_LO_HI 21
++#define RG_RX_DES_LEN_LO_SZ 6
++#define RG_RX_DES_LEN_UP_MSK 0x3f000000
++#define RG_RX_DES_LEN_UP_I_MSK 0xc0ffffff
++#define RG_RX_DES_LEN_UP_SFT 24
++#define RG_RX_DES_LEN_UP_HI 29
++#define RG_RX_DES_LEN_UP_SZ 6
++#define RG_RX_DES_SRVC_UP_MSK 0x0000003f
++#define RG_RX_DES_SRVC_UP_I_MSK 0xffffffc0
++#define RG_RX_DES_SRVC_UP_SFT 0
++#define RG_RX_DES_SRVC_UP_HI 5
++#define RG_RX_DES_SRVC_UP_SZ 6
++#define RG_RX_DES_L_LEN_LO_MSK 0x00003f00
++#define RG_RX_DES_L_LEN_LO_I_MSK 0xffffc0ff
++#define RG_RX_DES_L_LEN_LO_SFT 8
++#define RG_RX_DES_L_LEN_LO_HI 13
++#define RG_RX_DES_L_LEN_LO_SZ 6
++#define RG_RX_DES_L_LEN_UP_MSK 0x003f0000
++#define RG_RX_DES_L_LEN_UP_I_MSK 0xffc0ffff
++#define RG_RX_DES_L_LEN_UP_SFT 16
++#define RG_RX_DES_L_LEN_UP_HI 21
++#define RG_RX_DES_L_LEN_UP_SZ 6
++#define RG_RX_DES_TYPE_MSK 0x3f000000
++#define RG_RX_DES_TYPE_I_MSK 0xc0ffffff
++#define RG_RX_DES_TYPE_SFT 24
++#define RG_RX_DES_TYPE_HI 29
++#define RG_RX_DES_TYPE_SZ 6
++#define RG_RX_DES_L_LEN_UP_COMB_MSK 0x00000001
++#define RG_RX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
++#define RG_RX_DES_L_LEN_UP_COMB_SFT 0
++#define RG_RX_DES_L_LEN_UP_COMB_HI 0
++#define RG_RX_DES_L_LEN_UP_COMB_SZ 1
++#define RG_RX_DES_TYPE_COMB_MSK 0x00000010
++#define RG_RX_DES_TYPE_COMB_I_MSK 0xffffffef
++#define RG_RX_DES_TYPE_COMB_SFT 4
++#define RG_RX_DES_TYPE_COMB_HI 4
++#define RG_RX_DES_TYPE_COMB_SZ 1
++#define RG_RX_DES_RATE_COMB_MSK 0x00000100
++#define RG_RX_DES_RATE_COMB_I_MSK 0xfffffeff
++#define RG_RX_DES_RATE_COMB_SFT 8
++#define RG_RX_DES_RATE_COMB_HI 8
++#define RG_RX_DES_RATE_COMB_SZ 1
++#define RG_RX_DES_MODE_COMB_MSK 0x00001000
++#define RG_RX_DES_MODE_COMB_I_MSK 0xffffefff
++#define RG_RX_DES_MODE_COMB_SFT 12
++#define RG_RX_DES_MODE_COMB_HI 12
++#define RG_RX_DES_MODE_COMB_SZ 1
++#define RG_RX_DES_SNR_MSK 0x000f0000
++#define RG_RX_DES_SNR_I_MSK 0xfff0ffff
++#define RG_RX_DES_SNR_SFT 16
++#define RG_RX_DES_SNR_HI 19
++#define RG_RX_DES_SNR_SZ 4
++#define RG_RX_DES_RCPI_MSK 0x00f00000
++#define RG_RX_DES_RCPI_I_MSK 0xff0fffff
++#define RG_RX_DES_RCPI_SFT 20
++#define RG_RX_DES_RCPI_HI 23
++#define RG_RX_DES_RCPI_SZ 4
++#define RG_RX_DES_SRVC_LO_MSK 0x3f000000
++#define RG_RX_DES_SRVC_LO_I_MSK 0xc0ffffff
++#define RG_RX_DES_SRVC_LO_SFT 24
++#define RG_RX_DES_SRVC_LO_HI 29
++#define RG_RX_DES_SRVC_LO_SZ 6
++#define RO_TX_DES_EXCP_RATE_CNT_MSK 0x000000ff
++#define RO_TX_DES_EXCP_RATE_CNT_I_MSK 0xffffff00
++#define RO_TX_DES_EXCP_RATE_CNT_SFT 0
++#define RO_TX_DES_EXCP_RATE_CNT_HI 7
++#define RO_TX_DES_EXCP_RATE_CNT_SZ 8
++#define RO_TX_DES_EXCP_CH_BW_CNT_MSK 0x0000ff00
++#define RO_TX_DES_EXCP_CH_BW_CNT_I_MSK 0xffff00ff
++#define RO_TX_DES_EXCP_CH_BW_CNT_SFT 8
++#define RO_TX_DES_EXCP_CH_BW_CNT_HI 15
++#define RO_TX_DES_EXCP_CH_BW_CNT_SZ 8
++#define RO_TX_DES_EXCP_MODE_CNT_MSK 0x00ff0000
++#define RO_TX_DES_EXCP_MODE_CNT_I_MSK 0xff00ffff
++#define RO_TX_DES_EXCP_MODE_CNT_SFT 16
++#define RO_TX_DES_EXCP_MODE_CNT_HI 23
++#define RO_TX_DES_EXCP_MODE_CNT_SZ 8
++#define RG_TX_DES_EXCP_RATE_DEFAULT_MSK 0x07000000
++#define RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK 0xf8ffffff
++#define RG_TX_DES_EXCP_RATE_DEFAULT_SFT 24
++#define RG_TX_DES_EXCP_RATE_DEFAULT_HI 26
++#define RG_TX_DES_EXCP_RATE_DEFAULT_SZ 3
++#define RG_TX_DES_EXCP_MODE_DEFAULT_MSK 0x70000000
++#define RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK 0x8fffffff
++#define RG_TX_DES_EXCP_MODE_DEFAULT_SFT 28
++#define RG_TX_DES_EXCP_MODE_DEFAULT_HI 30
++#define RG_TX_DES_EXCP_MODE_DEFAULT_SZ 3
++#define RG_TX_DES_EXCP_CLR_MSK 0x80000000
++#define RG_TX_DES_EXCP_CLR_I_MSK 0x7fffffff
++#define RG_TX_DES_EXCP_CLR_SFT 31
++#define RG_TX_DES_EXCP_CLR_HI 31
++#define RG_TX_DES_EXCP_CLR_SZ 1
++#define RG_TX_DES_ACK_WIDTH_MSK 0x00000001
++#define RG_TX_DES_ACK_WIDTH_I_MSK 0xfffffffe
++#define RG_TX_DES_ACK_WIDTH_SFT 0
++#define RG_TX_DES_ACK_WIDTH_HI 0
++#define RG_TX_DES_ACK_WIDTH_SZ 1
++#define RG_TX_DES_ACK_PRD_MSK 0x0000000e
++#define RG_TX_DES_ACK_PRD_I_MSK 0xfffffff1
++#define RG_TX_DES_ACK_PRD_SFT 1
++#define RG_TX_DES_ACK_PRD_HI 3
++#define RG_TX_DES_ACK_PRD_SZ 3
++#define RG_RX_DES_SNR_GN_MSK 0x003f0000
++#define RG_RX_DES_SNR_GN_I_MSK 0xffc0ffff
++#define RG_RX_DES_SNR_GN_SFT 16
++#define RG_RX_DES_SNR_GN_HI 21
++#define RG_RX_DES_SNR_GN_SZ 6
++#define RG_RX_DES_RCPI_GN_MSK 0x3f000000
++#define RG_RX_DES_RCPI_GN_I_MSK 0xc0ffffff
++#define RG_RX_DES_RCPI_GN_SFT 24
++#define RG_RX_DES_RCPI_GN_HI 29
++#define RG_RX_DES_RCPI_GN_SZ 6
++#define RG_TST_TBUS_SEL_MSK 0x0000000f
++#define RG_TST_TBUS_SEL_I_MSK 0xfffffff0
++#define RG_TST_TBUS_SEL_SFT 0
++#define RG_TST_TBUS_SEL_HI 3
++#define RG_TST_TBUS_SEL_SZ 4
++#define RG_RSSI_OFFSET_MSK 0x00ff0000
++#define RG_RSSI_OFFSET_I_MSK 0xff00ffff
++#define RG_RSSI_OFFSET_SFT 16
++#define RG_RSSI_OFFSET_HI 23
++#define RG_RSSI_OFFSET_SZ 8
++#define RG_RSSI_INV_MSK 0x01000000
++#define RG_RSSI_INV_I_MSK 0xfeffffff
++#define RG_RSSI_INV_SFT 24
++#define RG_RSSI_INV_HI 24
++#define RG_RSSI_INV_SZ 1
++#define RG_TST_ADC_ON_MSK 0x40000000
++#define RG_TST_ADC_ON_I_MSK 0xbfffffff
++#define RG_TST_ADC_ON_SFT 30
++#define RG_TST_ADC_ON_HI 30
++#define RG_TST_ADC_ON_SZ 1
++#define RG_TST_EXT_GAIN_MSK 0x80000000
++#define RG_TST_EXT_GAIN_I_MSK 0x7fffffff
++#define RG_TST_EXT_GAIN_SFT 31
++#define RG_TST_EXT_GAIN_HI 31
++#define RG_TST_EXT_GAIN_SZ 1
++#define RG_DAC_Q_SET_MSK 0x000003ff
++#define RG_DAC_Q_SET_I_MSK 0xfffffc00
++#define RG_DAC_Q_SET_SFT 0
++#define RG_DAC_Q_SET_HI 9
++#define RG_DAC_Q_SET_SZ 10
++#define RG_DAC_I_SET_MSK 0x003ff000
++#define RG_DAC_I_SET_I_MSK 0xffc00fff
++#define RG_DAC_I_SET_SFT 12
++#define RG_DAC_I_SET_HI 21
++#define RG_DAC_I_SET_SZ 10
++#define RG_DAC_EN_MAN_MSK 0x10000000
++#define RG_DAC_EN_MAN_I_MSK 0xefffffff
++#define RG_DAC_EN_MAN_SFT 28
++#define RG_DAC_EN_MAN_HI 28
++#define RG_DAC_EN_MAN_SZ 1
++#define RG_IQC_FFT_EN_MSK 0x20000000
++#define RG_IQC_FFT_EN_I_MSK 0xdfffffff
++#define RG_IQC_FFT_EN_SFT 29
++#define RG_IQC_FFT_EN_HI 29
++#define RG_IQC_FFT_EN_SZ 1
++#define RG_DAC_MAN_Q_EN_MSK 0x40000000
++#define RG_DAC_MAN_Q_EN_I_MSK 0xbfffffff
++#define RG_DAC_MAN_Q_EN_SFT 30
++#define RG_DAC_MAN_Q_EN_HI 30
++#define RG_DAC_MAN_Q_EN_SZ 1
++#define RG_DAC_MAN_I_EN_MSK 0x80000000
++#define RG_DAC_MAN_I_EN_I_MSK 0x7fffffff
++#define RG_DAC_MAN_I_EN_SFT 31
++#define RG_DAC_MAN_I_EN_HI 31
++#define RG_DAC_MAN_I_EN_SZ 1
++#define RO_MRX_EN_CNT_MSK 0x0000ffff
++#define RO_MRX_EN_CNT_I_MSK 0xffff0000
++#define RO_MRX_EN_CNT_SFT 0
++#define RO_MRX_EN_CNT_HI 15
++#define RO_MRX_EN_CNT_SZ 16
++#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000
++#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff
++#define RG_MRX_EN_CNT_RST_N_SFT 31
++#define RG_MRX_EN_CNT_RST_N_HI 31
++#define RG_MRX_EN_CNT_RST_N_SZ 1
++#define RG_PA_RISE_TIME_MSK 0x000000ff
++#define RG_PA_RISE_TIME_I_MSK 0xffffff00
++#define RG_PA_RISE_TIME_SFT 0
++#define RG_PA_RISE_TIME_HI 7
++#define RG_PA_RISE_TIME_SZ 8
++#define RG_RFTX_RISE_TIME_MSK 0x0000ff00
++#define RG_RFTX_RISE_TIME_I_MSK 0xffff00ff
++#define RG_RFTX_RISE_TIME_SFT 8
++#define RG_RFTX_RISE_TIME_HI 15
++#define RG_RFTX_RISE_TIME_SZ 8
++#define RG_DAC_RISE_TIME_MSK 0x00ff0000
++#define RG_DAC_RISE_TIME_I_MSK 0xff00ffff
++#define RG_DAC_RISE_TIME_SFT 16
++#define RG_DAC_RISE_TIME_HI 23
++#define RG_DAC_RISE_TIME_SZ 8
++#define RG_SW_RISE_TIME_MSK 0xff000000
++#define RG_SW_RISE_TIME_I_MSK 0x00ffffff
++#define RG_SW_RISE_TIME_SFT 24
++#define RG_SW_RISE_TIME_HI 31
++#define RG_SW_RISE_TIME_SZ 8
++#define RG_PA_FALL_TIME_MSK 0x000000ff
++#define RG_PA_FALL_TIME_I_MSK 0xffffff00
++#define RG_PA_FALL_TIME_SFT 0
++#define RG_PA_FALL_TIME_HI 7
++#define RG_PA_FALL_TIME_SZ 8
++#define RG_RFTX_FALL_TIME_MSK 0x0000ff00
++#define RG_RFTX_FALL_TIME_I_MSK 0xffff00ff
++#define RG_RFTX_FALL_TIME_SFT 8
++#define RG_RFTX_FALL_TIME_HI 15
++#define RG_RFTX_FALL_TIME_SZ 8
++#define RG_DAC_FALL_TIME_MSK 0x00ff0000
++#define RG_DAC_FALL_TIME_I_MSK 0xff00ffff
++#define RG_DAC_FALL_TIME_SFT 16
++#define RG_DAC_FALL_TIME_HI 23
++#define RG_DAC_FALL_TIME_SZ 8
++#define RG_SW_FALL_TIME_MSK 0xff000000
++#define RG_SW_FALL_TIME_I_MSK 0x00ffffff
++#define RG_SW_FALL_TIME_SFT 24
++#define RG_SW_FALL_TIME_HI 31
++#define RG_SW_FALL_TIME_SZ 8
++#define RG_ANT_SW_0_MSK 0x00000007
++#define RG_ANT_SW_0_I_MSK 0xfffffff8
++#define RG_ANT_SW_0_SFT 0
++#define RG_ANT_SW_0_HI 2
++#define RG_ANT_SW_0_SZ 3
++#define RG_ANT_SW_1_MSK 0x00000038
++#define RG_ANT_SW_1_I_MSK 0xffffffc7
++#define RG_ANT_SW_1_SFT 3
++#define RG_ANT_SW_1_HI 5
++#define RG_ANT_SW_1_SZ 3
++#define RG_MTX_LEN_LOWER_TH_0_MSK 0x00001fff
++#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffffe000
++#define RG_MTX_LEN_LOWER_TH_0_SFT 0
++#define RG_MTX_LEN_LOWER_TH_0_HI 12
++#define RG_MTX_LEN_LOWER_TH_0_SZ 13
++#define RG_MTX_LEN_UPPER_TH_0_MSK 0x1fff0000
++#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
++#define RG_MTX_LEN_UPPER_TH_0_SFT 16
++#define RG_MTX_LEN_UPPER_TH_0_HI 28
++#define RG_MTX_LEN_UPPER_TH_0_SZ 13
++#define RG_MTX_LEN_CNT_EN_0_MSK 0x80000000
++#define RG_MTX_LEN_CNT_EN_0_I_MSK 0x7fffffff
++#define RG_MTX_LEN_CNT_EN_0_SFT 31
++#define RG_MTX_LEN_CNT_EN_0_HI 31
++#define RG_MTX_LEN_CNT_EN_0_SZ 1
++#define RG_MTX_LEN_LOWER_TH_1_MSK 0x00001fff
++#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffffe000
++#define RG_MTX_LEN_LOWER_TH_1_SFT 0
++#define RG_MTX_LEN_LOWER_TH_1_HI 12
++#define RG_MTX_LEN_LOWER_TH_1_SZ 13
++#define RG_MTX_LEN_UPPER_TH_1_MSK 0x1fff0000
++#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
++#define RG_MTX_LEN_UPPER_TH_1_SFT 16
++#define RG_MTX_LEN_UPPER_TH_1_HI 28
++#define RG_MTX_LEN_UPPER_TH_1_SZ 13
++#define RG_MTX_LEN_CNT_EN_1_MSK 0x80000000
++#define RG_MTX_LEN_CNT_EN_1_I_MSK 0x7fffffff
++#define RG_MTX_LEN_CNT_EN_1_SFT 31
++#define RG_MTX_LEN_CNT_EN_1_HI 31
++#define RG_MTX_LEN_CNT_EN_1_SZ 1
++#define RG_MRX_LEN_LOWER_TH_0_MSK 0x00001fff
++#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffffe000
++#define RG_MRX_LEN_LOWER_TH_0_SFT 0
++#define RG_MRX_LEN_LOWER_TH_0_HI 12
++#define RG_MRX_LEN_LOWER_TH_0_SZ 13
++#define RG_MRX_LEN_UPPER_TH_0_MSK 0x1fff0000
++#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
++#define RG_MRX_LEN_UPPER_TH_0_SFT 16
++#define RG_MRX_LEN_UPPER_TH_0_HI 28
++#define RG_MRX_LEN_UPPER_TH_0_SZ 13
++#define RG_MRX_LEN_CNT_EN_0_MSK 0x80000000
++#define RG_MRX_LEN_CNT_EN_0_I_MSK 0x7fffffff
++#define RG_MRX_LEN_CNT_EN_0_SFT 31
++#define RG_MRX_LEN_CNT_EN_0_HI 31
++#define RG_MRX_LEN_CNT_EN_0_SZ 1
++#define RG_MRX_LEN_LOWER_TH_1_MSK 0x00001fff
++#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffffe000
++#define RG_MRX_LEN_LOWER_TH_1_SFT 0
++#define RG_MRX_LEN_LOWER_TH_1_HI 12
++#define RG_MRX_LEN_LOWER_TH_1_SZ 13
++#define RG_MRX_LEN_UPPER_TH_1_MSK 0x1fff0000
++#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
++#define RG_MRX_LEN_UPPER_TH_1_SFT 16
++#define RG_MRX_LEN_UPPER_TH_1_HI 28
++#define RG_MRX_LEN_UPPER_TH_1_SZ 13
++#define RG_MRX_LEN_CNT_EN_1_MSK 0x80000000
++#define RG_MRX_LEN_CNT_EN_1_I_MSK 0x7fffffff
++#define RG_MRX_LEN_CNT_EN_1_SFT 31
++#define RG_MRX_LEN_CNT_EN_1_HI 31
++#define RG_MRX_LEN_CNT_EN_1_SZ 1
++#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff
++#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000
++#define RO_MTX_LEN_CNT_1_SFT 0
++#define RO_MTX_LEN_CNT_1_HI 15
++#define RO_MTX_LEN_CNT_1_SZ 16
++#define RO_MTX_LEN_CNT_0_MSK 0xffff0000
++#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff
++#define RO_MTX_LEN_CNT_0_SFT 16
++#define RO_MTX_LEN_CNT_0_HI 31
++#define RO_MTX_LEN_CNT_0_SZ 16
++#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff
++#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000
++#define RO_MRX_LEN_CNT_1_SFT 0
++#define RO_MRX_LEN_CNT_1_HI 15
++#define RO_MRX_LEN_CNT_1_SZ 16
++#define RO_MRX_LEN_CNT_0_MSK 0xffff0000
++#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff
++#define RO_MRX_LEN_CNT_0_SFT 16
++#define RO_MRX_LEN_CNT_0_HI 31
++#define RO_MRX_LEN_CNT_0_SZ 16
++#define RG_MODE_REG_IN_16_MSK 0x0000ffff
++#define RG_MODE_REG_IN_16_I_MSK 0xffff0000
++#define RG_MODE_REG_IN_16_SFT 0
++#define RG_MODE_REG_IN_16_HI 15
++#define RG_MODE_REG_IN_16_SZ 16
++#define RG_PARALLEL_DR_16_MSK 0x00100000
++#define RG_PARALLEL_DR_16_I_MSK 0xffefffff
++#define RG_PARALLEL_DR_16_SFT 20
++#define RG_PARALLEL_DR_16_HI 20
++#define RG_PARALLEL_DR_16_SZ 1
++#define RG_MBRUN_16_MSK 0x01000000
++#define RG_MBRUN_16_I_MSK 0xfeffffff
++#define RG_MBRUN_16_SFT 24
++#define RG_MBRUN_16_HI 24
++#define RG_MBRUN_16_SZ 1
++#define RG_SHIFT_DR_16_MSK 0x10000000
++#define RG_SHIFT_DR_16_I_MSK 0xefffffff
++#define RG_SHIFT_DR_16_SFT 28
++#define RG_SHIFT_DR_16_HI 28
++#define RG_SHIFT_DR_16_SZ 1
++#define RG_MODE_REG_SI_16_MSK 0x20000000
++#define RG_MODE_REG_SI_16_I_MSK 0xdfffffff
++#define RG_MODE_REG_SI_16_SFT 29
++#define RG_MODE_REG_SI_16_HI 29
++#define RG_MODE_REG_SI_16_SZ 1
++#define RG_SIMULATION_MODE_16_MSK 0x40000000
++#define RG_SIMULATION_MODE_16_I_MSK 0xbfffffff
++#define RG_SIMULATION_MODE_16_SFT 30
++#define RG_SIMULATION_MODE_16_HI 30
++#define RG_SIMULATION_MODE_16_SZ 1
++#define RG_DBIST_MODE_16_MSK 0x80000000
++#define RG_DBIST_MODE_16_I_MSK 0x7fffffff
++#define RG_DBIST_MODE_16_SFT 31
++#define RG_DBIST_MODE_16_HI 31
++#define RG_DBIST_MODE_16_SZ 1
++#define RO_MODE_REG_OUT_16_MSK 0x0000ffff
++#define RO_MODE_REG_OUT_16_I_MSK 0xffff0000
++#define RO_MODE_REG_OUT_16_SFT 0
++#define RO_MODE_REG_OUT_16_HI 15
++#define RO_MODE_REG_OUT_16_SZ 16
++#define RO_MODE_REG_SO_16_MSK 0x01000000
++#define RO_MODE_REG_SO_16_I_MSK 0xfeffffff
++#define RO_MODE_REG_SO_16_SFT 24
++#define RO_MODE_REG_SO_16_HI 24
++#define RO_MODE_REG_SO_16_SZ 1
++#define RO_MONITOR_BUS_16_MSK 0x0007ffff
++#define RO_MONITOR_BUS_16_I_MSK 0xfff80000
++#define RO_MONITOR_BUS_16_SFT 0
++#define RO_MONITOR_BUS_16_HI 18
++#define RO_MONITOR_BUS_16_SZ 19
++#define RG_MRX_TYPE_1_MSK 0x000000ff
++#define RG_MRX_TYPE_1_I_MSK 0xffffff00
++#define RG_MRX_TYPE_1_SFT 0
++#define RG_MRX_TYPE_1_HI 7
++#define RG_MRX_TYPE_1_SZ 8
++#define RG_MRX_TYPE_0_MSK 0x0000ff00
++#define RG_MRX_TYPE_0_I_MSK 0xffff00ff
++#define RG_MRX_TYPE_0_SFT 8
++#define RG_MRX_TYPE_0_HI 15
++#define RG_MRX_TYPE_0_SZ 8
++#define RG_MTX_TYPE_1_MSK 0x00ff0000
++#define RG_MTX_TYPE_1_I_MSK 0xff00ffff
++#define RG_MTX_TYPE_1_SFT 16
++#define RG_MTX_TYPE_1_HI 23
++#define RG_MTX_TYPE_1_SZ 8
++#define RG_MTX_TYPE_0_MSK 0xff000000
++#define RG_MTX_TYPE_0_I_MSK 0x00ffffff
++#define RG_MTX_TYPE_0_SFT 24
++#define RG_MTX_TYPE_0_HI 31
++#define RG_MTX_TYPE_0_SZ 8
++#define RO_MTX_TYPE_CNT_1_MSK 0x0000ffff
++#define RO_MTX_TYPE_CNT_1_I_MSK 0xffff0000
++#define RO_MTX_TYPE_CNT_1_SFT 0
++#define RO_MTX_TYPE_CNT_1_HI 15
++#define RO_MTX_TYPE_CNT_1_SZ 16
++#define RO_MTX_TYPE_CNT_0_MSK 0xffff0000
++#define RO_MTX_TYPE_CNT_0_I_MSK 0x0000ffff
++#define RO_MTX_TYPE_CNT_0_SFT 16
++#define RO_MTX_TYPE_CNT_0_HI 31
++#define RO_MTX_TYPE_CNT_0_SZ 16
++#define RO_MRX_TYPE_CNT_1_MSK 0x0000ffff
++#define RO_MRX_TYPE_CNT_1_I_MSK 0xffff0000
++#define RO_MRX_TYPE_CNT_1_SFT 0
++#define RO_MRX_TYPE_CNT_1_HI 15
++#define RO_MRX_TYPE_CNT_1_SZ 16
++#define RO_MRX_TYPE_CNT_0_MSK 0xffff0000
++#define RO_MRX_TYPE_CNT_0_I_MSK 0x0000ffff
++#define RO_MRX_TYPE_CNT_0_SFT 16
++#define RO_MRX_TYPE_CNT_0_HI 31
++#define RO_MRX_TYPE_CNT_0_SZ 16
++#define RG_HB_COEF0_MSK 0x00000fff
++#define RG_HB_COEF0_I_MSK 0xfffff000
++#define RG_HB_COEF0_SFT 0
++#define RG_HB_COEF0_HI 11
++#define RG_HB_COEF0_SZ 12
++#define RG_HB_COEF1_MSK 0x0fff0000
++#define RG_HB_COEF1_I_MSK 0xf000ffff
++#define RG_HB_COEF1_SFT 16
++#define RG_HB_COEF1_HI 27
++#define RG_HB_COEF1_SZ 12
++#define RG_HB_COEF2_MSK 0x00000fff
++#define RG_HB_COEF2_I_MSK 0xfffff000
++#define RG_HB_COEF2_SFT 0
++#define RG_HB_COEF2_HI 11
++#define RG_HB_COEF2_SZ 12
++#define RG_HB_COEF3_MSK 0x0fff0000
++#define RG_HB_COEF3_I_MSK 0xf000ffff
++#define RG_HB_COEF3_SFT 16
++#define RG_HB_COEF3_HI 27
++#define RG_HB_COEF3_SZ 12
++#define RG_HB_COEF4_MSK 0x00000fff
++#define RG_HB_COEF4_I_MSK 0xfffff000
++#define RG_HB_COEF4_SFT 0
++#define RG_HB_COEF4_HI 11
++#define RG_HB_COEF4_SZ 12
++#define RO_TBUS_O_MSK 0x000fffff
++#define RO_TBUS_O_I_MSK 0xfff00000
++#define RO_TBUS_O_SFT 0
++#define RO_TBUS_O_HI 19
++#define RO_TBUS_O_SZ 20
++#define RG_LPF4_00_MSK 0x00001fff
++#define RG_LPF4_00_I_MSK 0xffffe000
++#define RG_LPF4_00_SFT 0
++#define RG_LPF4_00_HI 12
++#define RG_LPF4_00_SZ 13
++#define RG_LPF4_01_MSK 0x00001fff
++#define RG_LPF4_01_I_MSK 0xffffe000
++#define RG_LPF4_01_SFT 0
++#define RG_LPF4_01_HI 12
++#define RG_LPF4_01_SZ 13
++#define RG_LPF4_02_MSK 0x00001fff
++#define RG_LPF4_02_I_MSK 0xffffe000
++#define RG_LPF4_02_SFT 0
++#define RG_LPF4_02_HI 12
++#define RG_LPF4_02_SZ 13
++#define RG_LPF4_03_MSK 0x00001fff
++#define RG_LPF4_03_I_MSK 0xffffe000
++#define RG_LPF4_03_SFT 0
++#define RG_LPF4_03_HI 12
++#define RG_LPF4_03_SZ 13
++#define RG_LPF4_04_MSK 0x00001fff
++#define RG_LPF4_04_I_MSK 0xffffe000
++#define RG_LPF4_04_SFT 0
++#define RG_LPF4_04_HI 12
++#define RG_LPF4_04_SZ 13
++#define RG_LPF4_05_MSK 0x00001fff
++#define RG_LPF4_05_I_MSK 0xffffe000
++#define RG_LPF4_05_SFT 0
++#define RG_LPF4_05_HI 12
++#define RG_LPF4_05_SZ 13
++#define RG_LPF4_06_MSK 0x00001fff
++#define RG_LPF4_06_I_MSK 0xffffe000
++#define RG_LPF4_06_SFT 0
++#define RG_LPF4_06_HI 12
++#define RG_LPF4_06_SZ 13
++#define RG_LPF4_07_MSK 0x00001fff
++#define RG_LPF4_07_I_MSK 0xffffe000
++#define RG_LPF4_07_SFT 0
++#define RG_LPF4_07_HI 12
++#define RG_LPF4_07_SZ 13
++#define RG_LPF4_08_MSK 0x00001fff
++#define RG_LPF4_08_I_MSK 0xffffe000
++#define RG_LPF4_08_SFT 0
++#define RG_LPF4_08_HI 12
++#define RG_LPF4_08_SZ 13
++#define RG_LPF4_09_MSK 0x00001fff
++#define RG_LPF4_09_I_MSK 0xffffe000
++#define RG_LPF4_09_SFT 0
++#define RG_LPF4_09_HI 12
++#define RG_LPF4_09_SZ 13
++#define RG_LPF4_10_MSK 0x00001fff
++#define RG_LPF4_10_I_MSK 0xffffe000
++#define RG_LPF4_10_SFT 0
++#define RG_LPF4_10_HI 12
++#define RG_LPF4_10_SZ 13
++#define RG_LPF4_11_MSK 0x00001fff
++#define RG_LPF4_11_I_MSK 0xffffe000
++#define RG_LPF4_11_SFT 0
++#define RG_LPF4_11_HI 12
++#define RG_LPF4_11_SZ 13
++#define RG_LPF4_12_MSK 0x00001fff
++#define RG_LPF4_12_I_MSK 0xffffe000
++#define RG_LPF4_12_SFT 0
++#define RG_LPF4_12_HI 12
++#define RG_LPF4_12_SZ 13
++#define RG_LPF4_13_MSK 0x00001fff
++#define RG_LPF4_13_I_MSK 0xffffe000
++#define RG_LPF4_13_SFT 0
++#define RG_LPF4_13_HI 12
++#define RG_LPF4_13_SZ 13
++#define RG_LPF4_14_MSK 0x00001fff
++#define RG_LPF4_14_I_MSK 0xffffe000
++#define RG_LPF4_14_SFT 0
++#define RG_LPF4_14_HI 12
++#define RG_LPF4_14_SZ 13
++#define RG_LPF4_15_MSK 0x00001fff
++#define RG_LPF4_15_I_MSK 0xffffe000
++#define RG_LPF4_15_SFT 0
++#define RG_LPF4_15_HI 12
++#define RG_LPF4_15_SZ 13
++#define RG_LPF4_16_MSK 0x00001fff
++#define RG_LPF4_16_I_MSK 0xffffe000
++#define RG_LPF4_16_SFT 0
++#define RG_LPF4_16_HI 12
++#define RG_LPF4_16_SZ 13
++#define RG_LPF4_17_MSK 0x00001fff
++#define RG_LPF4_17_I_MSK 0xffffe000
++#define RG_LPF4_17_SFT 0
++#define RG_LPF4_17_HI 12
++#define RG_LPF4_17_SZ 13
++#define RG_LPF4_18_MSK 0x00001fff
++#define RG_LPF4_18_I_MSK 0xffffe000
++#define RG_LPF4_18_SFT 0
++#define RG_LPF4_18_HI 12
++#define RG_LPF4_18_SZ 13
++#define RG_LPF4_19_MSK 0x00001fff
++#define RG_LPF4_19_I_MSK 0xffffe000
++#define RG_LPF4_19_SFT 0
++#define RG_LPF4_19_HI 12
++#define RG_LPF4_19_SZ 13
++#define RG_LPF4_20_MSK 0x00001fff
++#define RG_LPF4_20_I_MSK 0xffffe000
++#define RG_LPF4_20_SFT 0
++#define RG_LPF4_20_HI 12
++#define RG_LPF4_20_SZ 13
++#define RG_LPF4_21_MSK 0x00001fff
++#define RG_LPF4_21_I_MSK 0xffffe000
++#define RG_LPF4_21_SFT 0
++#define RG_LPF4_21_HI 12
++#define RG_LPF4_21_SZ 13
++#define RG_LPF4_22_MSK 0x00001fff
++#define RG_LPF4_22_I_MSK 0xffffe000
++#define RG_LPF4_22_SFT 0
++#define RG_LPF4_22_HI 12
++#define RG_LPF4_22_SZ 13
++#define RG_LPF4_23_MSK 0x00001fff
++#define RG_LPF4_23_I_MSK 0xffffe000
++#define RG_LPF4_23_SFT 0
++#define RG_LPF4_23_HI 12
++#define RG_LPF4_23_SZ 13
++#define RG_LPF4_24_MSK 0x00001fff
++#define RG_LPF4_24_I_MSK 0xffffe000
++#define RG_LPF4_24_SFT 0
++#define RG_LPF4_24_HI 12
++#define RG_LPF4_24_SZ 13
++#define RG_LPF4_25_MSK 0x00001fff
++#define RG_LPF4_25_I_MSK 0xffffe000
++#define RG_LPF4_25_SFT 0
++#define RG_LPF4_25_HI 12
++#define RG_LPF4_25_SZ 13
++#define RG_LPF4_26_MSK 0x00001fff
++#define RG_LPF4_26_I_MSK 0xffffe000
++#define RG_LPF4_26_SFT 0
++#define RG_LPF4_26_HI 12
++#define RG_LPF4_26_SZ 13
++#define RG_LPF4_27_MSK 0x00001fff
++#define RG_LPF4_27_I_MSK 0xffffe000
++#define RG_LPF4_27_SFT 0
++#define RG_LPF4_27_HI 12
++#define RG_LPF4_27_SZ 13
++#define RG_LPF4_28_MSK 0x00001fff
++#define RG_LPF4_28_I_MSK 0xffffe000
++#define RG_LPF4_28_SFT 0
++#define RG_LPF4_28_HI 12
++#define RG_LPF4_28_SZ 13
++#define RG_LPF4_29_MSK 0x00001fff
++#define RG_LPF4_29_I_MSK 0xffffe000
++#define RG_LPF4_29_SFT 0
++#define RG_LPF4_29_HI 12
++#define RG_LPF4_29_SZ 13
++#define RG_LPF4_30_MSK 0x00001fff
++#define RG_LPF4_30_I_MSK 0xffffe000
++#define RG_LPF4_30_SFT 0
++#define RG_LPF4_30_HI 12
++#define RG_LPF4_30_SZ 13
++#define RG_LPF4_31_MSK 0x00001fff
++#define RG_LPF4_31_I_MSK 0xffffe000
++#define RG_LPF4_31_SFT 0
++#define RG_LPF4_31_HI 12
++#define RG_LPF4_31_SZ 13
++#define RG_LPF4_32_MSK 0x00001fff
++#define RG_LPF4_32_I_MSK 0xffffe000
++#define RG_LPF4_32_SFT 0
++#define RG_LPF4_32_HI 12
++#define RG_LPF4_32_SZ 13
++#define RG_LPF4_33_MSK 0x00001fff
++#define RG_LPF4_33_I_MSK 0xffffe000
++#define RG_LPF4_33_SFT 0
++#define RG_LPF4_33_HI 12
++#define RG_LPF4_33_SZ 13
++#define RG_LPF4_34_MSK 0x00001fff
++#define RG_LPF4_34_I_MSK 0xffffe000
++#define RG_LPF4_34_SFT 0
++#define RG_LPF4_34_HI 12
++#define RG_LPF4_34_SZ 13
++#define RG_LPF4_35_MSK 0x00001fff
++#define RG_LPF4_35_I_MSK 0xffffe000
++#define RG_LPF4_35_SFT 0
++#define RG_LPF4_35_HI 12
++#define RG_LPF4_35_SZ 13
++#define RG_LPF4_36_MSK 0x00001fff
++#define RG_LPF4_36_I_MSK 0xffffe000
++#define RG_LPF4_36_SFT 0
++#define RG_LPF4_36_HI 12
++#define RG_LPF4_36_SZ 13
++#define RG_LPF4_37_MSK 0x00001fff
++#define RG_LPF4_37_I_MSK 0xffffe000
++#define RG_LPF4_37_SFT 0
++#define RG_LPF4_37_HI 12
++#define RG_LPF4_37_SZ 13
++#define RG_LPF4_38_MSK 0x00001fff
++#define RG_LPF4_38_I_MSK 0xffffe000
++#define RG_LPF4_38_SFT 0
++#define RG_LPF4_38_HI 12
++#define RG_LPF4_38_SZ 13
++#define RG_LPF4_39_MSK 0x00001fff
++#define RG_LPF4_39_I_MSK 0xffffe000
++#define RG_LPF4_39_SFT 0
++#define RG_LPF4_39_HI 12
++#define RG_LPF4_39_SZ 13
++#define RG_LPF4_40_MSK 0x00001fff
++#define RG_LPF4_40_I_MSK 0xffffe000
++#define RG_LPF4_40_SFT 0
++#define RG_LPF4_40_HI 12
++#define RG_LPF4_40_SZ 13
++#define RG_BP_SMB_MSK 0x00002000
++#define RG_BP_SMB_I_MSK 0xffffdfff
++#define RG_BP_SMB_SFT 13
++#define RG_BP_SMB_HI 13
++#define RG_BP_SMB_SZ 1
++#define RG_EN_SRVC_MSK 0x00004000
++#define RG_EN_SRVC_I_MSK 0xffffbfff
++#define RG_EN_SRVC_SFT 14
++#define RG_EN_SRVC_HI 14
++#define RG_EN_SRVC_SZ 1
++#define RG_DES_SPD_MSK 0x00030000
++#define RG_DES_SPD_I_MSK 0xfffcffff
++#define RG_DES_SPD_SFT 16
++#define RG_DES_SPD_HI 17
++#define RG_DES_SPD_SZ 2
++#define RG_BB_11B_RISE_TIME_MSK 0x000000ff
++#define RG_BB_11B_RISE_TIME_I_MSK 0xffffff00
++#define RG_BB_11B_RISE_TIME_SFT 0
++#define RG_BB_11B_RISE_TIME_HI 7
++#define RG_BB_11B_RISE_TIME_SZ 8
++#define RG_BB_11B_FALL_TIME_MSK 0x0000ff00
++#define RG_BB_11B_FALL_TIME_I_MSK 0xffff00ff
++#define RG_BB_11B_FALL_TIME_SFT 8
++#define RG_BB_11B_FALL_TIME_HI 15
++#define RG_BB_11B_FALL_TIME_SZ 8
++#define RG_WR_TX_EN_CNT_RST_N_MSK 0x00000001
++#define RG_WR_TX_EN_CNT_RST_N_I_MSK 0xfffffffe
++#define RG_WR_TX_EN_CNT_RST_N_SFT 0
++#define RG_WR_TX_EN_CNT_RST_N_HI 0
++#define RG_WR_TX_EN_CNT_RST_N_SZ 1
++#define RO_TX_EN_CNT_MSK 0x0000ffff
++#define RO_TX_EN_CNT_I_MSK 0xffff0000
++#define RO_TX_EN_CNT_SFT 0
++#define RO_TX_EN_CNT_HI 15
++#define RO_TX_EN_CNT_SZ 16
++#define RO_TX_CNT_MSK 0xffffffff
++#define RO_TX_CNT_I_MSK 0x00000000
++#define RO_TX_CNT_SFT 0
++#define RO_TX_CNT_HI 31
++#define RO_TX_CNT_SZ 32
++#define RG_POS_DES_11B_L_EXT_MSK 0x0000000f
++#define RG_POS_DES_11B_L_EXT_I_MSK 0xfffffff0
++#define RG_POS_DES_11B_L_EXT_SFT 0
++#define RG_POS_DES_11B_L_EXT_HI 3
++#define RG_POS_DES_11B_L_EXT_SZ 4
++#define RG_PRE_DES_11B_DLY_MSK 0x000000f0
++#define RG_PRE_DES_11B_DLY_I_MSK 0xffffff0f
++#define RG_PRE_DES_11B_DLY_SFT 4
++#define RG_PRE_DES_11B_DLY_HI 7
++#define RG_PRE_DES_11B_DLY_SZ 4
++#define RG_CNT_CCA_LMT_MSK 0x000f0000
++#define RG_CNT_CCA_LMT_I_MSK 0xfff0ffff
++#define RG_CNT_CCA_LMT_SFT 16
++#define RG_CNT_CCA_LMT_HI 19
++#define RG_CNT_CCA_LMT_SZ 4
++#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000
++#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff
++#define RG_BYPASS_DESCRAMBLER_SFT 29
++#define RG_BYPASS_DESCRAMBLER_HI 29
++#define RG_BYPASS_DESCRAMBLER_SZ 1
++#define RG_BYPASS_AGC_MSK 0x80000000
++#define RG_BYPASS_AGC_I_MSK 0x7fffffff
++#define RG_BYPASS_AGC_SFT 31
++#define RG_BYPASS_AGC_HI 31
++#define RG_BYPASS_AGC_SZ 1
++#define RG_CCA_BIT_CNT_LMT_RX_MSK 0x000000f0
++#define RG_CCA_BIT_CNT_LMT_RX_I_MSK 0xffffff0f
++#define RG_CCA_BIT_CNT_LMT_RX_SFT 4
++#define RG_CCA_BIT_CNT_LMT_RX_HI 7
++#define RG_CCA_BIT_CNT_LMT_RX_SZ 4
++#define RG_CCA_SCALE_BF_MSK 0x007f0000
++#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff
++#define RG_CCA_SCALE_BF_SFT 16
++#define RG_CCA_SCALE_BF_HI 22
++#define RG_CCA_SCALE_BF_SZ 7
++#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000
++#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff
++#define RG_PEAK_IDX_CNT_SEL_SFT 28
++#define RG_PEAK_IDX_CNT_SEL_HI 29
++#define RG_PEAK_IDX_CNT_SEL_SZ 2
++#define RG_TR_KI_T2_MSK 0x00000007
++#define RG_TR_KI_T2_I_MSK 0xfffffff8
++#define RG_TR_KI_T2_SFT 0
++#define RG_TR_KI_T2_HI 2
++#define RG_TR_KI_T2_SZ 3
++#define RG_TR_KP_T2_MSK 0x00000070
++#define RG_TR_KP_T2_I_MSK 0xffffff8f
++#define RG_TR_KP_T2_SFT 4
++#define RG_TR_KP_T2_HI 6
++#define RG_TR_KP_T2_SZ 3
++#define RG_TR_KI_T1_MSK 0x00000700
++#define RG_TR_KI_T1_I_MSK 0xfffff8ff
++#define RG_TR_KI_T1_SFT 8
++#define RG_TR_KI_T1_HI 10
++#define RG_TR_KI_T1_SZ 3
++#define RG_TR_KP_T1_MSK 0x00007000
++#define RG_TR_KP_T1_I_MSK 0xffff8fff
++#define RG_TR_KP_T1_SFT 12
++#define RG_TR_KP_T1_HI 14
++#define RG_TR_KP_T1_SZ 3
++#define RG_CR_KI_T1_MSK 0x00070000
++#define RG_CR_KI_T1_I_MSK 0xfff8ffff
++#define RG_CR_KI_T1_SFT 16
++#define RG_CR_KI_T1_HI 18
++#define RG_CR_KI_T1_SZ 3
++#define RG_CR_KP_T1_MSK 0x00700000
++#define RG_CR_KP_T1_I_MSK 0xff8fffff
++#define RG_CR_KP_T1_SFT 20
++#define RG_CR_KP_T1_HI 22
++#define RG_CR_KP_T1_SZ 3
++#define RG_CHIP_CNT_SLICER_MSK 0x0000001f
++#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0
++#define RG_CHIP_CNT_SLICER_SFT 0
++#define RG_CHIP_CNT_SLICER_HI 4
++#define RG_CHIP_CNT_SLICER_SZ 5
++#define RG_CE_T4_CNT_LMT_MSK 0x0000ff00
++#define RG_CE_T4_CNT_LMT_I_MSK 0xffff00ff
++#define RG_CE_T4_CNT_LMT_SFT 8
++#define RG_CE_T4_CNT_LMT_HI 15
++#define RG_CE_T4_CNT_LMT_SZ 8
++#define RG_CE_T3_CNT_LMT_MSK 0x00ff0000
++#define RG_CE_T3_CNT_LMT_I_MSK 0xff00ffff
++#define RG_CE_T3_CNT_LMT_SFT 16
++#define RG_CE_T3_CNT_LMT_HI 23
++#define RG_CE_T3_CNT_LMT_SZ 8
++#define RG_CE_T2_CNT_LMT_MSK 0xff000000
++#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff
++#define RG_CE_T2_CNT_LMT_SFT 24
++#define RG_CE_T2_CNT_LMT_HI 31
++#define RG_CE_T2_CNT_LMT_SZ 8
++#define RG_CE_MU_T1_MSK 0x00000007
++#define RG_CE_MU_T1_I_MSK 0xfffffff8
++#define RG_CE_MU_T1_SFT 0
++#define RG_CE_MU_T1_HI 2
++#define RG_CE_MU_T1_SZ 3
++#define RG_CE_DLY_SEL_MSK 0x003f0000
++#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff
++#define RG_CE_DLY_SEL_SFT 16
++#define RG_CE_DLY_SEL_HI 21
++#define RG_CE_DLY_SEL_SZ 6
++#define RG_CE_MU_T8_MSK 0x00000007
++#define RG_CE_MU_T8_I_MSK 0xfffffff8
++#define RG_CE_MU_T8_SFT 0
++#define RG_CE_MU_T8_HI 2
++#define RG_CE_MU_T8_SZ 3
++#define RG_CE_MU_T7_MSK 0x00000070
++#define RG_CE_MU_T7_I_MSK 0xffffff8f
++#define RG_CE_MU_T7_SFT 4
++#define RG_CE_MU_T7_HI 6
++#define RG_CE_MU_T7_SZ 3
++#define RG_CE_MU_T6_MSK 0x00000700
++#define RG_CE_MU_T6_I_MSK 0xfffff8ff
++#define RG_CE_MU_T6_SFT 8
++#define RG_CE_MU_T6_HI 10
++#define RG_CE_MU_T6_SZ 3
++#define RG_CE_MU_T5_MSK 0x00007000
++#define RG_CE_MU_T5_I_MSK 0xffff8fff
++#define RG_CE_MU_T5_SFT 12
++#define RG_CE_MU_T5_HI 14
++#define RG_CE_MU_T5_SZ 3
++#define RG_CE_MU_T4_MSK 0x00070000
++#define RG_CE_MU_T4_I_MSK 0xfff8ffff
++#define RG_CE_MU_T4_SFT 16
++#define RG_CE_MU_T4_HI 18
++#define RG_CE_MU_T4_SZ 3
++#define RG_CE_MU_T3_MSK 0x00700000
++#define RG_CE_MU_T3_I_MSK 0xff8fffff
++#define RG_CE_MU_T3_SFT 20
++#define RG_CE_MU_T3_HI 22
++#define RG_CE_MU_T3_SZ 3
++#define RG_CE_MU_T2_MSK 0x07000000
++#define RG_CE_MU_T2_I_MSK 0xf8ffffff
++#define RG_CE_MU_T2_SFT 24
++#define RG_CE_MU_T2_HI 26
++#define RG_CE_MU_T2_SZ 3
++#define RG_EQ_MU_FB_T2_MSK 0x0000000f
++#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0
++#define RG_EQ_MU_FB_T2_SFT 0
++#define RG_EQ_MU_FB_T2_HI 3
++#define RG_EQ_MU_FB_T2_SZ 4
++#define RG_EQ_MU_FF_T2_MSK 0x000000f0
++#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f
++#define RG_EQ_MU_FF_T2_SFT 4
++#define RG_EQ_MU_FF_T2_HI 7
++#define RG_EQ_MU_FF_T2_SZ 4
++#define RG_EQ_MU_FB_T1_MSK 0x000f0000
++#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff
++#define RG_EQ_MU_FB_T1_SFT 16
++#define RG_EQ_MU_FB_T1_HI 19
++#define RG_EQ_MU_FB_T1_SZ 4
++#define RG_EQ_MU_FF_T1_MSK 0x00f00000
++#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff
++#define RG_EQ_MU_FF_T1_SFT 20
++#define RG_EQ_MU_FF_T1_HI 23
++#define RG_EQ_MU_FF_T1_SZ 4
++#define RG_EQ_MU_FB_T4_MSK 0x0000000f
++#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0
++#define RG_EQ_MU_FB_T4_SFT 0
++#define RG_EQ_MU_FB_T4_HI 3
++#define RG_EQ_MU_FB_T4_SZ 4
++#define RG_EQ_MU_FF_T4_MSK 0x000000f0
++#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f
++#define RG_EQ_MU_FF_T4_SFT 4
++#define RG_EQ_MU_FF_T4_HI 7
++#define RG_EQ_MU_FF_T4_SZ 4
++#define RG_EQ_MU_FB_T3_MSK 0x000f0000
++#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff
++#define RG_EQ_MU_FB_T3_SFT 16
++#define RG_EQ_MU_FB_T3_HI 19
++#define RG_EQ_MU_FB_T3_SZ 4
++#define RG_EQ_MU_FF_T3_MSK 0x00f00000
++#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff
++#define RG_EQ_MU_FF_T3_SFT 20
++#define RG_EQ_MU_FF_T3_HI 23
++#define RG_EQ_MU_FF_T3_SZ 4
++#define RG_EQ_KI_T2_MSK 0x00000700
++#define RG_EQ_KI_T2_I_MSK 0xfffff8ff
++#define RG_EQ_KI_T2_SFT 8
++#define RG_EQ_KI_T2_HI 10
++#define RG_EQ_KI_T2_SZ 3
++#define RG_EQ_KP_T2_MSK 0x00007000
++#define RG_EQ_KP_T2_I_MSK 0xffff8fff
++#define RG_EQ_KP_T2_SFT 12
++#define RG_EQ_KP_T2_HI 14
++#define RG_EQ_KP_T2_SZ 3
++#define RG_EQ_KI_T1_MSK 0x00070000
++#define RG_EQ_KI_T1_I_MSK 0xfff8ffff
++#define RG_EQ_KI_T1_SFT 16
++#define RG_EQ_KI_T1_HI 18
++#define RG_EQ_KI_T1_SZ 3
++#define RG_EQ_KP_T1_MSK 0x00700000
++#define RG_EQ_KP_T1_I_MSK 0xff8fffff
++#define RG_EQ_KP_T1_SFT 20
++#define RG_EQ_KP_T1_HI 22
++#define RG_EQ_KP_T1_SZ 3
++#define RG_TR_LPF_RATE_MSK 0x003fffff
++#define RG_TR_LPF_RATE_I_MSK 0xffc00000
++#define RG_TR_LPF_RATE_SFT 0
++#define RG_TR_LPF_RATE_HI 21
++#define RG_TR_LPF_RATE_SZ 22
++#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f
++#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80
++#define RG_CE_BIT_CNT_LMT_SFT 0
++#define RG_CE_BIT_CNT_LMT_HI 6
++#define RG_CE_BIT_CNT_LMT_SZ 7
++#define RG_CE_CH_MAIN_SET_MSK 0x00000080
++#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f
++#define RG_CE_CH_MAIN_SET_SFT 7
++#define RG_CE_CH_MAIN_SET_HI 7
++#define RG_CE_CH_MAIN_SET_SZ 1
++#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00
++#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff
++#define RG_TC_BIT_CNT_LMT_SFT 8
++#define RG_TC_BIT_CNT_LMT_HI 14
++#define RG_TC_BIT_CNT_LMT_SZ 7
++#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000
++#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff
++#define RG_CR_BIT_CNT_LMT_SFT 16
++#define RG_CR_BIT_CNT_LMT_HI 22
++#define RG_CR_BIT_CNT_LMT_SZ 7
++#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000
++#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff
++#define RG_TR_BIT_CNT_LMT_SFT 24
++#define RG_TR_BIT_CNT_LMT_HI 30
++#define RG_TR_BIT_CNT_LMT_SZ 7
++#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001
++#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe
++#define RG_EQ_MAIN_TAP_MAN_SFT 0
++#define RG_EQ_MAIN_TAP_MAN_HI 0
++#define RG_EQ_MAIN_TAP_MAN_SZ 1
++#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000
++#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff
++#define RG_EQ_MAIN_TAP_COEF_SFT 16
++#define RG_EQ_MAIN_TAP_COEF_HI 26
++#define RG_EQ_MAIN_TAP_COEF_SZ 11
++#define RG_PWRON_DLY_TH_11B_MSK 0x000000ff
++#define RG_PWRON_DLY_TH_11B_I_MSK 0xffffff00
++#define RG_PWRON_DLY_TH_11B_SFT 0
++#define RG_PWRON_DLY_TH_11B_HI 7
++#define RG_PWRON_DLY_TH_11B_SZ 8
++#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000
++#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff
++#define RG_SFD_BIT_CNT_LMT_SFT 16
++#define RG_SFD_BIT_CNT_LMT_HI 23
++#define RG_SFD_BIT_CNT_LMT_SZ 8
++#define RG_CCA_PWR_TH_RX_MSK 0x00007fff
++#define RG_CCA_PWR_TH_RX_I_MSK 0xffff8000
++#define RG_CCA_PWR_TH_RX_SFT 0
++#define RG_CCA_PWR_TH_RX_HI 14
++#define RG_CCA_PWR_TH_RX_SZ 15
++#define RG_CCA_PWR_CNT_TH_MSK 0x001f0000
++#define RG_CCA_PWR_CNT_TH_I_MSK 0xffe0ffff
++#define RG_CCA_PWR_CNT_TH_SFT 16
++#define RG_CCA_PWR_CNT_TH_HI 20
++#define RG_CCA_PWR_CNT_TH_SZ 5
++#define B_FREQ_OS_MSK 0x000007ff
++#define B_FREQ_OS_I_MSK 0xfffff800
++#define B_FREQ_OS_SFT 0
++#define B_FREQ_OS_HI 10
++#define B_FREQ_OS_SZ 11
++#define B_SNR_MSK 0x0000007f
++#define B_SNR_I_MSK 0xffffff80
++#define B_SNR_SFT 0
++#define B_SNR_HI 6
++#define B_SNR_SZ 7
++#define B_RCPI_MSK 0x007f0000
++#define B_RCPI_I_MSK 0xff80ffff
++#define B_RCPI_SFT 16
++#define B_RCPI_HI 22
++#define B_RCPI_SZ 7
++#define CRC_CNT_MSK 0x0000ffff
++#define CRC_CNT_I_MSK 0xffff0000
++#define CRC_CNT_SFT 0
++#define CRC_CNT_HI 15
++#define CRC_CNT_SZ 16
++#define SFD_CNT_MSK 0xffff0000
++#define SFD_CNT_I_MSK 0x0000ffff
++#define SFD_CNT_SFT 16
++#define SFD_CNT_HI 31
++#define SFD_CNT_SZ 16
++#define B_PACKET_ERR_CNT_MSK 0x0000ffff
++#define B_PACKET_ERR_CNT_I_MSK 0xffff0000
++#define B_PACKET_ERR_CNT_SFT 0
++#define B_PACKET_ERR_CNT_HI 15
++#define B_PACKET_ERR_CNT_SZ 16
++#define PACKET_ERR_MSK 0x00010000
++#define PACKET_ERR_I_MSK 0xfffeffff
++#define PACKET_ERR_SFT 16
++#define PACKET_ERR_HI 16
++#define PACKET_ERR_SZ 1
++#define B_PACKET_CNT_MSK 0x0000ffff
++#define B_PACKET_CNT_I_MSK 0xffff0000
++#define B_PACKET_CNT_SFT 0
++#define B_PACKET_CNT_HI 15
++#define B_PACKET_CNT_SZ 16
++#define B_CCA_CNT_MSK 0xffff0000
++#define B_CCA_CNT_I_MSK 0x0000ffff
++#define B_CCA_CNT_SFT 16
++#define B_CCA_CNT_HI 31
++#define B_CCA_CNT_SZ 16
++#define B_LENGTH_FIELD_MSK 0x0000ffff
++#define B_LENGTH_FIELD_I_MSK 0xffff0000
++#define B_LENGTH_FIELD_SFT 0
++#define B_LENGTH_FIELD_HI 15
++#define B_LENGTH_FIELD_SZ 16
++#define SFD_FIELD_MSK 0xffff0000
++#define SFD_FIELD_I_MSK 0x0000ffff
++#define SFD_FIELD_SFT 16
++#define SFD_FIELD_HI 31
++#define SFD_FIELD_SZ 16
++#define SIGNAL_FIELD_MSK 0x000000ff
++#define SIGNAL_FIELD_I_MSK 0xffffff00
++#define SIGNAL_FIELD_SFT 0
++#define SIGNAL_FIELD_HI 7
++#define SIGNAL_FIELD_SZ 8
++#define B_SERVICE_FIELD_MSK 0x0000ff00
++#define B_SERVICE_FIELD_I_MSK 0xffff00ff
++#define B_SERVICE_FIELD_SFT 8
++#define B_SERVICE_FIELD_HI 15
++#define B_SERVICE_FIELD_SZ 8
++#define CRC_CORRECT_MSK 0x00010000
++#define CRC_CORRECT_I_MSK 0xfffeffff
++#define CRC_CORRECT_SFT 16
++#define CRC_CORRECT_HI 16
++#define CRC_CORRECT_SZ 1
++#define DEBUG_SEL_MSK 0x0000000f
++#define DEBUG_SEL_I_MSK 0xfffffff0
++#define DEBUG_SEL_SFT 0
++#define DEBUG_SEL_HI 3
++#define DEBUG_SEL_SZ 4
++#define RG_PACKET_STAT_EN_11B_MSK 0x00100000
++#define RG_PACKET_STAT_EN_11B_I_MSK 0xffefffff
++#define RG_PACKET_STAT_EN_11B_SFT 20
++#define RG_PACKET_STAT_EN_11B_HI 20
++#define RG_PACKET_STAT_EN_11B_SZ 1
++#define RG_BIT_REVERSE_MSK 0x00200000
++#define RG_BIT_REVERSE_I_MSK 0xffdfffff
++#define RG_BIT_REVERSE_SFT 21
++#define RG_BIT_REVERSE_HI 21
++#define RG_BIT_REVERSE_SZ 1
++#define RX_PHY_11B_SOFT_RST_N_MSK 0x00000001
++#define RX_PHY_11B_SOFT_RST_N_I_MSK 0xfffffffe
++#define RX_PHY_11B_SOFT_RST_N_SFT 0
++#define RX_PHY_11B_SOFT_RST_N_HI 0
++#define RX_PHY_11B_SOFT_RST_N_SZ 1
++#define RG_CE_BYPASS_TAP_MSK 0x000000f0
++#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f
++#define RG_CE_BYPASS_TAP_SFT 4
++#define RG_CE_BYPASS_TAP_HI 7
++#define RG_CE_BYPASS_TAP_SZ 4
++#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00
++#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff
++#define RG_EQ_BYPASS_FBW_TAP_SFT 8
++#define RG_EQ_BYPASS_FBW_TAP_HI 11
++#define RG_EQ_BYPASS_FBW_TAP_SZ 4
++#define RG_BB_11GN_RISE_TIME_MSK 0x000000ff
++#define RG_BB_11GN_RISE_TIME_I_MSK 0xffffff00
++#define RG_BB_11GN_RISE_TIME_SFT 0
++#define RG_BB_11GN_RISE_TIME_HI 7
++#define RG_BB_11GN_RISE_TIME_SZ 8
++#define RG_BB_11GN_FALL_TIME_MSK 0x0000ff00
++#define RG_BB_11GN_FALL_TIME_I_MSK 0xffff00ff
++#define RG_BB_11GN_FALL_TIME_SFT 8
++#define RG_BB_11GN_FALL_TIME_HI 15
++#define RG_BB_11GN_FALL_TIME_SZ 8
++#define RG_HTCARR52_FFT_SCALE_MSK 0x000003ff
++#define RG_HTCARR52_FFT_SCALE_I_MSK 0xfffffc00
++#define RG_HTCARR52_FFT_SCALE_SFT 0
++#define RG_HTCARR52_FFT_SCALE_HI 9
++#define RG_HTCARR52_FFT_SCALE_SZ 10
++#define RG_HTCARR56_FFT_SCALE_MSK 0x003ff000
++#define RG_HTCARR56_FFT_SCALE_I_MSK 0xffc00fff
++#define RG_HTCARR56_FFT_SCALE_SFT 12
++#define RG_HTCARR56_FFT_SCALE_HI 21
++#define RG_HTCARR56_FFT_SCALE_SZ 10
++#define RG_PACKET_STAT_EN_MSK 0x00800000
++#define RG_PACKET_STAT_EN_I_MSK 0xff7fffff
++#define RG_PACKET_STAT_EN_SFT 23
++#define RG_PACKET_STAT_EN_HI 23
++#define RG_PACKET_STAT_EN_SZ 1
++#define RG_SMB_DEF_MSK 0x7f000000
++#define RG_SMB_DEF_I_MSK 0x80ffffff
++#define RG_SMB_DEF_SFT 24
++#define RG_SMB_DEF_HI 30
++#define RG_SMB_DEF_SZ 7
++#define RG_CONTINUOUS_DATA_11GN_MSK 0x80000000
++#define RG_CONTINUOUS_DATA_11GN_I_MSK 0x7fffffff
++#define RG_CONTINUOUS_DATA_11GN_SFT 31
++#define RG_CONTINUOUS_DATA_11GN_HI 31
++#define RG_CONTINUOUS_DATA_11GN_SZ 1
++#define RO_TX_CNT_R_MSK 0xffffffff
++#define RO_TX_CNT_R_I_MSK 0x00000000
++#define RO_TX_CNT_R_SFT 0
++#define RO_TX_CNT_R_HI 31
++#define RO_TX_CNT_R_SZ 32
++#define RO_PACKET_ERR_CNT_MSK 0x0000ffff
++#define RO_PACKET_ERR_CNT_I_MSK 0xffff0000
++#define RO_PACKET_ERR_CNT_SFT 0
++#define RO_PACKET_ERR_CNT_HI 15
++#define RO_PACKET_ERR_CNT_SZ 16
++#define RG_POS_DES_11GN_L_EXT_MSK 0x0000000f
++#define RG_POS_DES_11GN_L_EXT_I_MSK 0xfffffff0
++#define RG_POS_DES_11GN_L_EXT_SFT 0
++#define RG_POS_DES_11GN_L_EXT_HI 3
++#define RG_POS_DES_11GN_L_EXT_SZ 4
++#define RG_PRE_DES_11GN_DLY_MSK 0x000000f0
++#define RG_PRE_DES_11GN_DLY_I_MSK 0xffffff0f
++#define RG_PRE_DES_11GN_DLY_SFT 4
++#define RG_PRE_DES_11GN_DLY_HI 7
++#define RG_PRE_DES_11GN_DLY_SZ 4
++#define RG_TR_LPF_KI_G_T1_MSK 0x0000000f
++#define RG_TR_LPF_KI_G_T1_I_MSK 0xfffffff0
++#define RG_TR_LPF_KI_G_T1_SFT 0
++#define RG_TR_LPF_KI_G_T1_HI 3
++#define RG_TR_LPF_KI_G_T1_SZ 4
++#define RG_TR_LPF_KP_G_T1_MSK 0x000000f0
++#define RG_TR_LPF_KP_G_T1_I_MSK 0xffffff0f
++#define RG_TR_LPF_KP_G_T1_SFT 4
++#define RG_TR_LPF_KP_G_T1_HI 7
++#define RG_TR_LPF_KP_G_T1_SZ 4
++#define RG_TR_CNT_T1_MSK 0x0000ff00
++#define RG_TR_CNT_T1_I_MSK 0xffff00ff
++#define RG_TR_CNT_T1_SFT 8
++#define RG_TR_CNT_T1_HI 15
++#define RG_TR_CNT_T1_SZ 8
++#define RG_TR_LPF_KI_G_T0_MSK 0x000f0000
++#define RG_TR_LPF_KI_G_T0_I_MSK 0xfff0ffff
++#define RG_TR_LPF_KI_G_T0_SFT 16
++#define RG_TR_LPF_KI_G_T0_HI 19
++#define RG_TR_LPF_KI_G_T0_SZ 4
++#define RG_TR_LPF_KP_G_T0_MSK 0x00f00000
++#define RG_TR_LPF_KP_G_T0_I_MSK 0xff0fffff
++#define RG_TR_LPF_KP_G_T0_SFT 20
++#define RG_TR_LPF_KP_G_T0_HI 23
++#define RG_TR_LPF_KP_G_T0_SZ 4
++#define RG_TR_CNT_T0_MSK 0xff000000
++#define RG_TR_CNT_T0_I_MSK 0x00ffffff
++#define RG_TR_CNT_T0_SFT 24
++#define RG_TR_CNT_T0_HI 31
++#define RG_TR_CNT_T0_SZ 8
++#define RG_TR_LPF_KI_G_T2_MSK 0x0000000f
++#define RG_TR_LPF_KI_G_T2_I_MSK 0xfffffff0
++#define RG_TR_LPF_KI_G_T2_SFT 0
++#define RG_TR_LPF_KI_G_T2_HI 3
++#define RG_TR_LPF_KI_G_T2_SZ 4
++#define RG_TR_LPF_KP_G_T2_MSK 0x000000f0
++#define RG_TR_LPF_KP_G_T2_I_MSK 0xffffff0f
++#define RG_TR_LPF_KP_G_T2_SFT 4
++#define RG_TR_LPF_KP_G_T2_HI 7
++#define RG_TR_LPF_KP_G_T2_SZ 4
++#define RG_TR_CNT_T2_MSK 0x0000ff00
++#define RG_TR_CNT_T2_I_MSK 0xffff00ff
++#define RG_TR_CNT_T2_SFT 8
++#define RG_TR_CNT_T2_HI 15
++#define RG_TR_CNT_T2_SZ 8
++#define RG_TR_LPF_KI_G_MSK 0x0000000f
++#define RG_TR_LPF_KI_G_I_MSK 0xfffffff0
++#define RG_TR_LPF_KI_G_SFT 0
++#define RG_TR_LPF_KI_G_HI 3
++#define RG_TR_LPF_KI_G_SZ 4
++#define RG_TR_LPF_KP_G_MSK 0x000000f0
++#define RG_TR_LPF_KP_G_I_MSK 0xffffff0f
++#define RG_TR_LPF_KP_G_SFT 4
++#define RG_TR_LPF_KP_G_HI 7
++#define RG_TR_LPF_KP_G_SZ 4
++#define RG_TR_LPF_RATE_G_MSK 0x3fffff00
++#define RG_TR_LPF_RATE_G_I_MSK 0xc00000ff
++#define RG_TR_LPF_RATE_G_SFT 8
++#define RG_TR_LPF_RATE_G_HI 29
++#define RG_TR_LPF_RATE_G_SZ 22
++#define RG_CR_LPF_KI_G_MSK 0x00000007
++#define RG_CR_LPF_KI_G_I_MSK 0xfffffff8
++#define RG_CR_LPF_KI_G_SFT 0
++#define RG_CR_LPF_KI_G_HI 2
++#define RG_CR_LPF_KI_G_SZ 3
++#define RG_SYM_BOUND_CNT_MSK 0x00007f00
++#define RG_SYM_BOUND_CNT_I_MSK 0xffff80ff
++#define RG_SYM_BOUND_CNT_SFT 8
++#define RG_SYM_BOUND_CNT_HI 14
++#define RG_SYM_BOUND_CNT_SZ 7
++#define RG_XSCOR32_RATIO_MSK 0x007f0000
++#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff
++#define RG_XSCOR32_RATIO_SFT 16
++#define RG_XSCOR32_RATIO_HI 22
++#define RG_XSCOR32_RATIO_SZ 7
++#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000
++#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff
++#define RG_ATCOR64_CNT_LMT_SFT 24
++#define RG_ATCOR64_CNT_LMT_HI 30
++#define RG_ATCOR64_CNT_LMT_SZ 7
++#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00
++#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff
++#define RG_ATCOR16_CNT_LMT2_SFT 8
++#define RG_ATCOR16_CNT_LMT2_HI 14
++#define RG_ATCOR16_CNT_LMT2_SZ 7
++#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000
++#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff
++#define RG_ATCOR16_CNT_LMT1_SFT 16
++#define RG_ATCOR16_CNT_LMT1_HI 22
++#define RG_ATCOR16_CNT_LMT1_SZ 7
++#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000
++#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff
++#define RG_ATCOR16_RATIO_SB_SFT 24
++#define RG_ATCOR16_RATIO_SB_HI 30
++#define RG_ATCOR16_RATIO_SB_SZ 7
++#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000
++#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff
++#define RG_XSCOR64_CNT_LMT2_SFT 16
++#define RG_XSCOR64_CNT_LMT2_HI 22
++#define RG_XSCOR64_CNT_LMT2_SZ 7
++#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000
++#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff
++#define RG_XSCOR64_CNT_LMT1_SFT 24
++#define RG_XSCOR64_CNT_LMT1_HI 30
++#define RG_XSCOR64_CNT_LMT1_SZ 7
++#define RG_RX_FFT_SCALE_MSK 0x000003ff
++#define RG_RX_FFT_SCALE_I_MSK 0xfffffc00
++#define RG_RX_FFT_SCALE_SFT 0
++#define RG_RX_FFT_SCALE_HI 9
++#define RG_RX_FFT_SCALE_SZ 10
++#define RG_VITERBI_AB_SWAP_MSK 0x00010000
++#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff
++#define RG_VITERBI_AB_SWAP_SFT 16
++#define RG_VITERBI_AB_SWAP_HI 16
++#define RG_VITERBI_AB_SWAP_SZ 1
++#define RG_ATCOR16_CNT_TH_MSK 0x0f000000
++#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff
++#define RG_ATCOR16_CNT_TH_SFT 24
++#define RG_ATCOR16_CNT_TH_HI 27
++#define RG_ATCOR16_CNT_TH_SZ 4
++#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff
++#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00
++#define RG_NORMSQUARE_LOW_SNR_7_SFT 0
++#define RG_NORMSQUARE_LOW_SNR_7_HI 7
++#define RG_NORMSQUARE_LOW_SNR_7_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00
++#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff
++#define RG_NORMSQUARE_LOW_SNR_6_SFT 8
++#define RG_NORMSQUARE_LOW_SNR_6_HI 15
++#define RG_NORMSQUARE_LOW_SNR_6_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000
++#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff
++#define RG_NORMSQUARE_LOW_SNR_5_SFT 16
++#define RG_NORMSQUARE_LOW_SNR_5_HI 23
++#define RG_NORMSQUARE_LOW_SNR_5_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000
++#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_LOW_SNR_4_SFT 24
++#define RG_NORMSQUARE_LOW_SNR_4_HI 31
++#define RG_NORMSQUARE_LOW_SNR_4_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000
++#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_LOW_SNR_8_SFT 24
++#define RG_NORMSQUARE_LOW_SNR_8_HI 31
++#define RG_NORMSQUARE_LOW_SNR_8_SZ 8
++#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff
++#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00
++#define RG_NORMSQUARE_SNR_3_SFT 0
++#define RG_NORMSQUARE_SNR_3_HI 7
++#define RG_NORMSQUARE_SNR_3_SZ 8
++#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00
++#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff
++#define RG_NORMSQUARE_SNR_2_SFT 8
++#define RG_NORMSQUARE_SNR_2_HI 15
++#define RG_NORMSQUARE_SNR_2_SZ 8
++#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000
++#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff
++#define RG_NORMSQUARE_SNR_1_SFT 16
++#define RG_NORMSQUARE_SNR_1_HI 23
++#define RG_NORMSQUARE_SNR_1_SZ 8
++#define RG_NORMSQUARE_SNR_0_MSK 0xff000000
++#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_SNR_0_SFT 24
++#define RG_NORMSQUARE_SNR_0_HI 31
++#define RG_NORMSQUARE_SNR_0_SZ 8
++#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff
++#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00
++#define RG_NORMSQUARE_SNR_7_SFT 0
++#define RG_NORMSQUARE_SNR_7_HI 7
++#define RG_NORMSQUARE_SNR_7_SZ 8
++#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00
++#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff
++#define RG_NORMSQUARE_SNR_6_SFT 8
++#define RG_NORMSQUARE_SNR_6_HI 15
++#define RG_NORMSQUARE_SNR_6_SZ 8
++#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000
++#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff
++#define RG_NORMSQUARE_SNR_5_SFT 16
++#define RG_NORMSQUARE_SNR_5_HI 23
++#define RG_NORMSQUARE_SNR_5_SZ 8
++#define RG_NORMSQUARE_SNR_4_MSK 0xff000000
++#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_SNR_4_SFT 24
++#define RG_NORMSQUARE_SNR_4_HI 31
++#define RG_NORMSQUARE_SNR_4_SZ 8
++#define RG_NORMSQUARE_SNR_8_MSK 0xff000000
++#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_SNR_8_SFT 24
++#define RG_NORMSQUARE_SNR_8_HI 31
++#define RG_NORMSQUARE_SNR_8_SZ 8
++#define RG_SNR_TH_64QAM_MSK 0x0000007f
++#define RG_SNR_TH_64QAM_I_MSK 0xffffff80
++#define RG_SNR_TH_64QAM_SFT 0
++#define RG_SNR_TH_64QAM_HI 6
++#define RG_SNR_TH_64QAM_SZ 7
++#define RG_SNR_TH_16QAM_MSK 0x00007f00
++#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff
++#define RG_SNR_TH_16QAM_SFT 8
++#define RG_SNR_TH_16QAM_HI 14
++#define RG_SNR_TH_16QAM_SZ 7
++#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f
++#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80
++#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0
++#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6
++#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7
++#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00
++#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff
++#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8
++#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14
++#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7
++#define RG_SYM_BOUND_METHOD_MSK 0x00030000
++#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff
++#define RG_SYM_BOUND_METHOD_SFT 16
++#define RG_SYM_BOUND_METHOD_HI 17
++#define RG_SYM_BOUND_METHOD_SZ 2
++#define RG_PWRON_DLY_TH_11GN_MSK 0x000000ff
++#define RG_PWRON_DLY_TH_11GN_I_MSK 0xffffff00
++#define RG_PWRON_DLY_TH_11GN_SFT 0
++#define RG_PWRON_DLY_TH_11GN_HI 7
++#define RG_PWRON_DLY_TH_11GN_SZ 8
++#define RG_SB_START_CNT_MSK 0x00007f00
++#define RG_SB_START_CNT_I_MSK 0xffff80ff
++#define RG_SB_START_CNT_SFT 8
++#define RG_SB_START_CNT_HI 14
++#define RG_SB_START_CNT_SZ 7
++#define RG_POW16_CNT_TH_MSK 0x000000f0
++#define RG_POW16_CNT_TH_I_MSK 0xffffff0f
++#define RG_POW16_CNT_TH_SFT 4
++#define RG_POW16_CNT_TH_HI 7
++#define RG_POW16_CNT_TH_SZ 4
++#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700
++#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff
++#define RG_POW16_SHORT_CNT_LMT_SFT 8
++#define RG_POW16_SHORT_CNT_LMT_HI 10
++#define RG_POW16_SHORT_CNT_LMT_SZ 3
++#define RG_POW16_TH_L_MSK 0x7f000000
++#define RG_POW16_TH_L_I_MSK 0x80ffffff
++#define RG_POW16_TH_L_SFT 24
++#define RG_POW16_TH_L_HI 30
++#define RG_POW16_TH_L_SZ 7
++#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007
++#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8
++#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0
++#define RG_XSCOR16_SHORT_CNT_LMT_HI 2
++#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3
++#define RG_XSCOR16_RATIO_MSK 0x00007f00
++#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff
++#define RG_XSCOR16_RATIO_SFT 8
++#define RG_XSCOR16_RATIO_HI 14
++#define RG_XSCOR16_RATIO_SZ 7
++#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000
++#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff
++#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16
++#define RG_ATCOR16_SHORT_CNT_LMT_HI 18
++#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3
++#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000
++#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff
++#define RG_ATCOR16_RATIO_CCD_SFT 24
++#define RG_ATCOR16_RATIO_CCD_HI 30
++#define RG_ATCOR16_RATIO_CCD_SZ 7
++#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f
++#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80
++#define RG_ATCOR64_ACC_LMT_SFT 0
++#define RG_ATCOR64_ACC_LMT_HI 6
++#define RG_ATCOR64_ACC_LMT_SZ 7
++#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000
++#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff
++#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16
++#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18
++#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3
++#define RG_VITERBI_TB_BITS_MSK 0xff000000
++#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff
++#define RG_VITERBI_TB_BITS_SFT 24
++#define RG_VITERBI_TB_BITS_HI 31
++#define RG_VITERBI_TB_BITS_SZ 8
++#define RG_CR_CNT_UPDATE_MSK 0x000000ff
++#define RG_CR_CNT_UPDATE_I_MSK 0xffffff00
++#define RG_CR_CNT_UPDATE_SFT 0
++#define RG_CR_CNT_UPDATE_HI 7
++#define RG_CR_CNT_UPDATE_SZ 8
++#define RG_TR_CNT_UPDATE_MSK 0x00ff0000
++#define RG_TR_CNT_UPDATE_I_MSK 0xff00ffff
++#define RG_TR_CNT_UPDATE_SFT 16
++#define RG_TR_CNT_UPDATE_HI 23
++#define RG_TR_CNT_UPDATE_SZ 8
++#define RG_BYPASS_CPE_MA_MSK 0x00000010
++#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef
++#define RG_BYPASS_CPE_MA_SFT 4
++#define RG_BYPASS_CPE_MA_HI 4
++#define RG_BYPASS_CPE_MA_SZ 1
++#define RG_PILOT_BNDRY_SHIFT_MSK 0x00000700
++#define RG_PILOT_BNDRY_SHIFT_I_MSK 0xfffff8ff
++#define RG_PILOT_BNDRY_SHIFT_SFT 8
++#define RG_PILOT_BNDRY_SHIFT_HI 10
++#define RG_PILOT_BNDRY_SHIFT_SZ 3
++#define RG_EQ_SHORT_GI_SHIFT_MSK 0x00007000
++#define RG_EQ_SHORT_GI_SHIFT_I_MSK 0xffff8fff
++#define RG_EQ_SHORT_GI_SHIFT_SFT 12
++#define RG_EQ_SHORT_GI_SHIFT_HI 14
++#define RG_EQ_SHORT_GI_SHIFT_SZ 3
++#define RG_FFT_WDW_SHORT_SHIFT_MSK 0x00070000
++#define RG_FFT_WDW_SHORT_SHIFT_I_MSK 0xfff8ffff
++#define RG_FFT_WDW_SHORT_SHIFT_SFT 16
++#define RG_FFT_WDW_SHORT_SHIFT_HI 18
++#define RG_FFT_WDW_SHORT_SHIFT_SZ 3
++#define RG_CHSMTH_COEF_MSK 0x00030000
++#define RG_CHSMTH_COEF_I_MSK 0xfffcffff
++#define RG_CHSMTH_COEF_SFT 16
++#define RG_CHSMTH_COEF_HI 17
++#define RG_CHSMTH_COEF_SZ 2
++#define RG_CHSMTH_EN_MSK 0x00040000
++#define RG_CHSMTH_EN_I_MSK 0xfffbffff
++#define RG_CHSMTH_EN_SFT 18
++#define RG_CHSMTH_EN_HI 18
++#define RG_CHSMTH_EN_SZ 1
++#define RG_CHEST_DD_FACTOR_MSK 0x07000000
++#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff
++#define RG_CHEST_DD_FACTOR_SFT 24
++#define RG_CHEST_DD_FACTOR_HI 26
++#define RG_CHEST_DD_FACTOR_SZ 3
++#define RG_CH_UPDATE_MSK 0x80000000
++#define RG_CH_UPDATE_I_MSK 0x7fffffff
++#define RG_CH_UPDATE_SFT 31
++#define RG_CH_UPDATE_HI 31
++#define RG_CH_UPDATE_SZ 1
++#define RG_FMT_DET_MM_TH_MSK 0x000000ff
++#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00
++#define RG_FMT_DET_MM_TH_SFT 0
++#define RG_FMT_DET_MM_TH_HI 7
++#define RG_FMT_DET_MM_TH_SZ 8
++#define RG_FMT_DET_GF_TH_MSK 0x0000ff00
++#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff
++#define RG_FMT_DET_GF_TH_SFT 8
++#define RG_FMT_DET_GF_TH_HI 15
++#define RG_FMT_DET_GF_TH_SZ 8
++#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000
++#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff
++#define RG_DO_NOT_CHECK_L_RATE_SFT 25
++#define RG_DO_NOT_CHECK_L_RATE_HI 25
++#define RG_DO_NOT_CHECK_L_RATE_SZ 1
++#define RG_FMT_DET_LENGTH_TH_MSK 0x0000ffff
++#define RG_FMT_DET_LENGTH_TH_I_MSK 0xffff0000
++#define RG_FMT_DET_LENGTH_TH_SFT 0
++#define RG_FMT_DET_LENGTH_TH_HI 15
++#define RG_FMT_DET_LENGTH_TH_SZ 16
++#define RG_L_LENGTH_MAX_MSK 0xffff0000
++#define RG_L_LENGTH_MAX_I_MSK 0x0000ffff
++#define RG_L_LENGTH_MAX_SFT 16
++#define RG_L_LENGTH_MAX_HI 31
++#define RG_L_LENGTH_MAX_SZ 16
++#define RG_TX_TIME_EXT_MSK 0x000000ff
++#define RG_TX_TIME_EXT_I_MSK 0xffffff00
++#define RG_TX_TIME_EXT_SFT 0
++#define RG_TX_TIME_EXT_HI 7
++#define RG_TX_TIME_EXT_SZ 8
++#define RG_MAC_DES_SPACE_MSK 0x00f00000
++#define RG_MAC_DES_SPACE_I_MSK 0xff0fffff
++#define RG_MAC_DES_SPACE_SFT 20
++#define RG_MAC_DES_SPACE_HI 23
++#define RG_MAC_DES_SPACE_SZ 4
++#define RG_TR_LPF_STBC_GF_KI_G_MSK 0x0000000f
++#define RG_TR_LPF_STBC_GF_KI_G_I_MSK 0xfffffff0
++#define RG_TR_LPF_STBC_GF_KI_G_SFT 0
++#define RG_TR_LPF_STBC_GF_KI_G_HI 3
++#define RG_TR_LPF_STBC_GF_KI_G_SZ 4
++#define RG_TR_LPF_STBC_GF_KP_G_MSK 0x000000f0
++#define RG_TR_LPF_STBC_GF_KP_G_I_MSK 0xffffff0f
++#define RG_TR_LPF_STBC_GF_KP_G_SFT 4
++#define RG_TR_LPF_STBC_GF_KP_G_HI 7
++#define RG_TR_LPF_STBC_GF_KP_G_SZ 4
++#define RG_TR_LPF_STBC_MF_KI_G_MSK 0x00000f00
++#define RG_TR_LPF_STBC_MF_KI_G_I_MSK 0xfffff0ff
++#define RG_TR_LPF_STBC_MF_KI_G_SFT 8
++#define RG_TR_LPF_STBC_MF_KI_G_HI 11
++#define RG_TR_LPF_STBC_MF_KI_G_SZ 4
++#define RG_TR_LPF_STBC_MF_KP_G_MSK 0x0000f000
++#define RG_TR_LPF_STBC_MF_KP_G_I_MSK 0xffff0fff
++#define RG_TR_LPF_STBC_MF_KP_G_SFT 12
++#define RG_TR_LPF_STBC_MF_KP_G_HI 15
++#define RG_TR_LPF_STBC_MF_KP_G_SZ 4
++#define RG_MODE_REG_IN_80_MSK 0x0001ffff
++#define RG_MODE_REG_IN_80_I_MSK 0xfffe0000
++#define RG_MODE_REG_IN_80_SFT 0
++#define RG_MODE_REG_IN_80_HI 16
++#define RG_MODE_REG_IN_80_SZ 17
++#define RG_PARALLEL_DR_80_MSK 0x00100000
++#define RG_PARALLEL_DR_80_I_MSK 0xffefffff
++#define RG_PARALLEL_DR_80_SFT 20
++#define RG_PARALLEL_DR_80_HI 20
++#define RG_PARALLEL_DR_80_SZ 1
++#define RG_MBRUN_80_MSK 0x01000000
++#define RG_MBRUN_80_I_MSK 0xfeffffff
++#define RG_MBRUN_80_SFT 24
++#define RG_MBRUN_80_HI 24
++#define RG_MBRUN_80_SZ 1
++#define RG_SHIFT_DR_80_MSK 0x10000000
++#define RG_SHIFT_DR_80_I_MSK 0xefffffff
++#define RG_SHIFT_DR_80_SFT 28
++#define RG_SHIFT_DR_80_HI 28
++#define RG_SHIFT_DR_80_SZ 1
++#define RG_MODE_REG_SI_80_MSK 0x20000000
++#define RG_MODE_REG_SI_80_I_MSK 0xdfffffff
++#define RG_MODE_REG_SI_80_SFT 29
++#define RG_MODE_REG_SI_80_HI 29
++#define RG_MODE_REG_SI_80_SZ 1
++#define RG_SIMULATION_MODE_80_MSK 0x40000000
++#define RG_SIMULATION_MODE_80_I_MSK 0xbfffffff
++#define RG_SIMULATION_MODE_80_SFT 30
++#define RG_SIMULATION_MODE_80_HI 30
++#define RG_SIMULATION_MODE_80_SZ 1
++#define RG_DBIST_MODE_80_MSK 0x80000000
++#define RG_DBIST_MODE_80_I_MSK 0x7fffffff
++#define RG_DBIST_MODE_80_SFT 31
++#define RG_DBIST_MODE_80_HI 31
++#define RG_DBIST_MODE_80_SZ 1
++#define RG_MODE_REG_IN_64_MSK 0x0000ffff
++#define RG_MODE_REG_IN_64_I_MSK 0xffff0000
++#define RG_MODE_REG_IN_64_SFT 0
++#define RG_MODE_REG_IN_64_HI 15
++#define RG_MODE_REG_IN_64_SZ 16
++#define RG_PARALLEL_DR_64_MSK 0x00100000
++#define RG_PARALLEL_DR_64_I_MSK 0xffefffff
++#define RG_PARALLEL_DR_64_SFT 20
++#define RG_PARALLEL_DR_64_HI 20
++#define RG_PARALLEL_DR_64_SZ 1
++#define RG_MBRUN_64_MSK 0x01000000
++#define RG_MBRUN_64_I_MSK 0xfeffffff
++#define RG_MBRUN_64_SFT 24
++#define RG_MBRUN_64_HI 24
++#define RG_MBRUN_64_SZ 1
++#define RG_SHIFT_DR_64_MSK 0x10000000
++#define RG_SHIFT_DR_64_I_MSK 0xefffffff
++#define RG_SHIFT_DR_64_SFT 28
++#define RG_SHIFT_DR_64_HI 28
++#define RG_SHIFT_DR_64_SZ 1
++#define RG_MODE_REG_SI_64_MSK 0x20000000
++#define RG_MODE_REG_SI_64_I_MSK 0xdfffffff
++#define RG_MODE_REG_SI_64_SFT 29
++#define RG_MODE_REG_SI_64_HI 29
++#define RG_MODE_REG_SI_64_SZ 1
++#define RG_SIMULATION_MODE_64_MSK 0x40000000
++#define RG_SIMULATION_MODE_64_I_MSK 0xbfffffff
++#define RG_SIMULATION_MODE_64_SFT 30
++#define RG_SIMULATION_MODE_64_HI 30
++#define RG_SIMULATION_MODE_64_SZ 1
++#define RG_DBIST_MODE_64_MSK 0x80000000
++#define RG_DBIST_MODE_64_I_MSK 0x7fffffff
++#define RG_DBIST_MODE_64_SFT 31
++#define RG_DBIST_MODE_64_HI 31
++#define RG_DBIST_MODE_64_SZ 1
++#define RO_MODE_REG_OUT_80_MSK 0x0001ffff
++#define RO_MODE_REG_OUT_80_I_MSK 0xfffe0000
++#define RO_MODE_REG_OUT_80_SFT 0
++#define RO_MODE_REG_OUT_80_HI 16
++#define RO_MODE_REG_OUT_80_SZ 17
++#define RO_MODE_REG_SO_80_MSK 0x01000000
++#define RO_MODE_REG_SO_80_I_MSK 0xfeffffff
++#define RO_MODE_REG_SO_80_SFT 24
++#define RO_MODE_REG_SO_80_HI 24
++#define RO_MODE_REG_SO_80_SZ 1
++#define RO_MONITOR_BUS_80_MSK 0x003fffff
++#define RO_MONITOR_BUS_80_I_MSK 0xffc00000
++#define RO_MONITOR_BUS_80_SFT 0
++#define RO_MONITOR_BUS_80_HI 21
++#define RO_MONITOR_BUS_80_SZ 22
++#define RO_MODE_REG_OUT_64_MSK 0x0000ffff
++#define RO_MODE_REG_OUT_64_I_MSK 0xffff0000
++#define RO_MODE_REG_OUT_64_SFT 0
++#define RO_MODE_REG_OUT_64_HI 15
++#define RO_MODE_REG_OUT_64_SZ 16
++#define RO_MODE_REG_SO_64_MSK 0x01000000
++#define RO_MODE_REG_SO_64_I_MSK 0xfeffffff
++#define RO_MODE_REG_SO_64_SFT 24
++#define RO_MODE_REG_SO_64_HI 24
++#define RO_MODE_REG_SO_64_SZ 1
++#define RO_MONITOR_BUS_64_MSK 0x0007ffff
++#define RO_MONITOR_BUS_64_I_MSK 0xfff80000
++#define RO_MONITOR_BUS_64_SFT 0
++#define RO_MONITOR_BUS_64_HI 18
++#define RO_MONITOR_BUS_64_SZ 19
++#define RO_SPECTRUM_DATA_MSK 0xffffffff
++#define RO_SPECTRUM_DATA_I_MSK 0x00000000
++#define RO_SPECTRUM_DATA_SFT 0
++#define RO_SPECTRUM_DATA_HI 31
++#define RO_SPECTRUM_DATA_SZ 32
++#define GN_SNR_MSK 0x0000007f
++#define GN_SNR_I_MSK 0xffffff80
++#define GN_SNR_SFT 0
++#define GN_SNR_HI 6
++#define GN_SNR_SZ 7
++#define GN_NOISE_PWR_MSK 0x00007f00
++#define GN_NOISE_PWR_I_MSK 0xffff80ff
++#define GN_NOISE_PWR_SFT 8
++#define GN_NOISE_PWR_HI 14
++#define GN_NOISE_PWR_SZ 7
++#define GN_RCPI_MSK 0x007f0000
++#define GN_RCPI_I_MSK 0xff80ffff
++#define GN_RCPI_SFT 16
++#define GN_RCPI_HI 22
++#define GN_RCPI_SZ 7
++#define GN_SIGNAL_PWR_MSK 0x7f000000
++#define GN_SIGNAL_PWR_I_MSK 0x80ffffff
++#define GN_SIGNAL_PWR_SFT 24
++#define GN_SIGNAL_PWR_HI 30
++#define GN_SIGNAL_PWR_SZ 7
++#define RO_FREQ_OS_LTS_MSK 0x00007fff
++#define RO_FREQ_OS_LTS_I_MSK 0xffff8000
++#define RO_FREQ_OS_LTS_SFT 0
++#define RO_FREQ_OS_LTS_HI 14
++#define RO_FREQ_OS_LTS_SZ 15
++#define CSTATE_MSK 0x000f0000
++#define CSTATE_I_MSK 0xfff0ffff
++#define CSTATE_SFT 16
++#define CSTATE_HI 19
++#define CSTATE_SZ 4
++#define SIGNAL_FIELD0_MSK 0x00ffffff
++#define SIGNAL_FIELD0_I_MSK 0xff000000
++#define SIGNAL_FIELD0_SFT 0
++#define SIGNAL_FIELD0_HI 23
++#define SIGNAL_FIELD0_SZ 24
++#define SIGNAL_FIELD1_MSK 0x00ffffff
++#define SIGNAL_FIELD1_I_MSK 0xff000000
++#define SIGNAL_FIELD1_SFT 0
++#define SIGNAL_FIELD1_HI 23
++#define SIGNAL_FIELD1_SZ 24
++#define GN_PACKET_ERR_CNT_MSK 0x0000ffff
++#define GN_PACKET_ERR_CNT_I_MSK 0xffff0000
++#define GN_PACKET_ERR_CNT_SFT 0
++#define GN_PACKET_ERR_CNT_HI 15
++#define GN_PACKET_ERR_CNT_SZ 16
++#define GN_PACKET_CNT_MSK 0x0000ffff
++#define GN_PACKET_CNT_I_MSK 0xffff0000
++#define GN_PACKET_CNT_SFT 0
++#define GN_PACKET_CNT_HI 15
++#define GN_PACKET_CNT_SZ 16
++#define GN_CCA_CNT_MSK 0xffff0000
++#define GN_CCA_CNT_I_MSK 0x0000ffff
++#define GN_CCA_CNT_SFT 16
++#define GN_CCA_CNT_HI 31
++#define GN_CCA_CNT_SZ 16
++#define GN_LENGTH_FIELD_MSK 0x0000ffff
++#define GN_LENGTH_FIELD_I_MSK 0xffff0000
++#define GN_LENGTH_FIELD_SFT 0
++#define GN_LENGTH_FIELD_HI 15
++#define GN_LENGTH_FIELD_SZ 16
++#define GN_SERVICE_FIELD_MSK 0xffff0000
++#define GN_SERVICE_FIELD_I_MSK 0x0000ffff
++#define GN_SERVICE_FIELD_SFT 16
++#define GN_SERVICE_FIELD_HI 31
++#define GN_SERVICE_FIELD_SZ 16
++#define RO_HT_MCS_40M_MSK 0x0000007f
++#define RO_HT_MCS_40M_I_MSK 0xffffff80
++#define RO_HT_MCS_40M_SFT 0
++#define RO_HT_MCS_40M_HI 6
++#define RO_HT_MCS_40M_SZ 7
++#define RO_L_RATE_40M_MSK 0x00003f00
++#define RO_L_RATE_40M_I_MSK 0xffffc0ff
++#define RO_L_RATE_40M_SFT 8
++#define RO_L_RATE_40M_HI 13
++#define RO_L_RATE_40M_SZ 6
++#define RG_DAGC_CNT_TH_MSK 0x00000003
++#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc
++#define RG_DAGC_CNT_TH_SFT 0
++#define RG_DAGC_CNT_TH_HI 1
++#define RG_DAGC_CNT_TH_SZ 2
++#define RG_PACKET_STAT_EN_11GN_MSK 0x00100000
++#define RG_PACKET_STAT_EN_11GN_I_MSK 0xffefffff
++#define RG_PACKET_STAT_EN_11GN_SFT 20
++#define RG_PACKET_STAT_EN_11GN_HI 20
++#define RG_PACKET_STAT_EN_11GN_SZ 1
++#define RX_PHY_11GN_SOFT_RST_N_MSK 0x00000001
++#define RX_PHY_11GN_SOFT_RST_N_I_MSK 0xfffffffe
++#define RX_PHY_11GN_SOFT_RST_N_SFT 0
++#define RX_PHY_11GN_SOFT_RST_N_HI 0
++#define RX_PHY_11GN_SOFT_RST_N_SZ 1
++#define RG_RIFS_EN_MSK 0x00000002
++#define RG_RIFS_EN_I_MSK 0xfffffffd
++#define RG_RIFS_EN_SFT 1
++#define RG_RIFS_EN_HI 1
++#define RG_RIFS_EN_SZ 1
++#define RG_STBC_EN_MSK 0x00000004
++#define RG_STBC_EN_I_MSK 0xfffffffb
++#define RG_STBC_EN_SFT 2
++#define RG_STBC_EN_HI 2
++#define RG_STBC_EN_SZ 1
++#define RG_COR_SEL_MSK 0x00000008
++#define RG_COR_SEL_I_MSK 0xfffffff7
++#define RG_COR_SEL_SFT 3
++#define RG_COR_SEL_HI 3
++#define RG_COR_SEL_SZ 1
++#define RG_INI_PHASE_MSK 0x00000030
++#define RG_INI_PHASE_I_MSK 0xffffffcf
++#define RG_INI_PHASE_SFT 4
++#define RG_INI_PHASE_HI 5
++#define RG_INI_PHASE_SZ 2
++#define RG_HT_LTF_SEL_EQ_MSK 0x00000040
++#define RG_HT_LTF_SEL_EQ_I_MSK 0xffffffbf
++#define RG_HT_LTF_SEL_EQ_SFT 6
++#define RG_HT_LTF_SEL_EQ_HI 6
++#define RG_HT_LTF_SEL_EQ_SZ 1
++#define RG_HT_LTF_SEL_PILOT_MSK 0x00000080
++#define RG_HT_LTF_SEL_PILOT_I_MSK 0xffffff7f
++#define RG_HT_LTF_SEL_PILOT_SFT 7
++#define RG_HT_LTF_SEL_PILOT_HI 7
++#define RG_HT_LTF_SEL_PILOT_SZ 1
++#define RG_CCA_PWR_SEL_MSK 0x00000200
++#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff
++#define RG_CCA_PWR_SEL_SFT 9
++#define RG_CCA_PWR_SEL_HI 9
++#define RG_CCA_PWR_SEL_SZ 1
++#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400
++#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff
++#define RG_CCA_XSCOR_PWR_SEL_SFT 10
++#define RG_CCA_XSCOR_PWR_SEL_HI 10
++#define RG_CCA_XSCOR_PWR_SEL_SZ 1
++#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800
++#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff
++#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11
++#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11
++#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1
++#define RG_DEBUG_SEL_MSK 0x0000f000
++#define RG_DEBUG_SEL_I_MSK 0xffff0fff
++#define RG_DEBUG_SEL_SFT 12
++#define RG_DEBUG_SEL_HI 15
++#define RG_DEBUG_SEL_SZ 4
++#define RG_POST_CLK_EN_MSK 0x00010000
++#define RG_POST_CLK_EN_I_MSK 0xfffeffff
++#define RG_POST_CLK_EN_SFT 16
++#define RG_POST_CLK_EN_HI 16
++#define RG_POST_CLK_EN_SZ 1
++#define IQCAL_RF_TX_EN_MSK 0x00000001
++#define IQCAL_RF_TX_EN_I_MSK 0xfffffffe
++#define IQCAL_RF_TX_EN_SFT 0
++#define IQCAL_RF_TX_EN_HI 0
++#define IQCAL_RF_TX_EN_SZ 1
++#define IQCAL_RF_TX_PA_EN_MSK 0x00000002
++#define IQCAL_RF_TX_PA_EN_I_MSK 0xfffffffd
++#define IQCAL_RF_TX_PA_EN_SFT 1
++#define IQCAL_RF_TX_PA_EN_HI 1
++#define IQCAL_RF_TX_PA_EN_SZ 1
++#define IQCAL_RF_TX_DAC_EN_MSK 0x00000004
++#define IQCAL_RF_TX_DAC_EN_I_MSK 0xfffffffb
++#define IQCAL_RF_TX_DAC_EN_SFT 2
++#define IQCAL_RF_TX_DAC_EN_HI 2
++#define IQCAL_RF_TX_DAC_EN_SZ 1
++#define IQCAL_RF_RX_AGC_MSK 0x00000008
++#define IQCAL_RF_RX_AGC_I_MSK 0xfffffff7
++#define IQCAL_RF_RX_AGC_SFT 3
++#define IQCAL_RF_RX_AGC_HI 3
++#define IQCAL_RF_RX_AGC_SZ 1
++#define IQCAL_RF_PGAG_MSK 0x00000f00
++#define IQCAL_RF_PGAG_I_MSK 0xfffff0ff
++#define IQCAL_RF_PGAG_SFT 8
++#define IQCAL_RF_PGAG_HI 11
++#define IQCAL_RF_PGAG_SZ 4
++#define IQCAL_RF_RFG_MSK 0x00003000
++#define IQCAL_RF_RFG_I_MSK 0xffffcfff
++#define IQCAL_RF_RFG_SFT 12
++#define IQCAL_RF_RFG_HI 13
++#define IQCAL_RF_RFG_SZ 2
++#define RG_TONEGEN_FREQ_MSK 0x007f0000
++#define RG_TONEGEN_FREQ_I_MSK 0xff80ffff
++#define RG_TONEGEN_FREQ_SFT 16
++#define RG_TONEGEN_FREQ_HI 22
++#define RG_TONEGEN_FREQ_SZ 7
++#define RG_TONEGEN_EN_MSK 0x00800000
++#define RG_TONEGEN_EN_I_MSK 0xff7fffff
++#define RG_TONEGEN_EN_SFT 23
++#define RG_TONEGEN_EN_HI 23
++#define RG_TONEGEN_EN_SZ 1
++#define RG_TONEGEN_INIT_PH_MSK 0x7f000000
++#define RG_TONEGEN_INIT_PH_I_MSK 0x80ffffff
++#define RG_TONEGEN_INIT_PH_SFT 24
++#define RG_TONEGEN_INIT_PH_HI 30
++#define RG_TONEGEN_INIT_PH_SZ 7
++#define RG_TONEGEN2_FREQ_MSK 0x0000007f
++#define RG_TONEGEN2_FREQ_I_MSK 0xffffff80
++#define RG_TONEGEN2_FREQ_SFT 0
++#define RG_TONEGEN2_FREQ_HI 6
++#define RG_TONEGEN2_FREQ_SZ 7
++#define RG_TONEGEN2_EN_MSK 0x00000080
++#define RG_TONEGEN2_EN_I_MSK 0xffffff7f
++#define RG_TONEGEN2_EN_SFT 7
++#define RG_TONEGEN2_EN_HI 7
++#define RG_TONEGEN2_EN_SZ 1
++#define RG_TONEGEN2_SCALE_MSK 0x0000ff00
++#define RG_TONEGEN2_SCALE_I_MSK 0xffff00ff
++#define RG_TONEGEN2_SCALE_SFT 8
++#define RG_TONEGEN2_SCALE_HI 15
++#define RG_TONEGEN2_SCALE_SZ 8
++#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff
++#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00
++#define RG_TXIQ_CLP_THD_I_SFT 0
++#define RG_TXIQ_CLP_THD_I_HI 9
++#define RG_TXIQ_CLP_THD_I_SZ 10
++#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000
++#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff
++#define RG_TXIQ_CLP_THD_Q_SFT 16
++#define RG_TXIQ_CLP_THD_Q_HI 25
++#define RG_TXIQ_CLP_THD_Q_SZ 10
++#define RG_TX_I_SCALE_MSK 0x000000ff
++#define RG_TX_I_SCALE_I_MSK 0xffffff00
++#define RG_TX_I_SCALE_SFT 0
++#define RG_TX_I_SCALE_HI 7
++#define RG_TX_I_SCALE_SZ 8
++#define RG_TX_Q_SCALE_MSK 0x0000ff00
++#define RG_TX_Q_SCALE_I_MSK 0xffff00ff
++#define RG_TX_Q_SCALE_SFT 8
++#define RG_TX_Q_SCALE_HI 15
++#define RG_TX_Q_SCALE_SZ 8
++#define RG_TX_IQ_SWP_MSK 0x00010000
++#define RG_TX_IQ_SWP_I_MSK 0xfffeffff
++#define RG_TX_IQ_SWP_SFT 16
++#define RG_TX_IQ_SWP_HI 16
++#define RG_TX_IQ_SWP_SZ 1
++#define RG_TX_SGN_OUT_MSK 0x00020000
++#define RG_TX_SGN_OUT_I_MSK 0xfffdffff
++#define RG_TX_SGN_OUT_SFT 17
++#define RG_TX_SGN_OUT_HI 17
++#define RG_TX_SGN_OUT_SZ 1
++#define RG_TXIQ_EMU_IDX_MSK 0x003c0000
++#define RG_TXIQ_EMU_IDX_I_MSK 0xffc3ffff
++#define RG_TXIQ_EMU_IDX_SFT 18
++#define RG_TXIQ_EMU_IDX_HI 21
++#define RG_TXIQ_EMU_IDX_SZ 4
++#define RG_TX_IQ_SRC_MSK 0x03000000
++#define RG_TX_IQ_SRC_I_MSK 0xfcffffff
++#define RG_TX_IQ_SRC_SFT 24
++#define RG_TX_IQ_SRC_HI 25
++#define RG_TX_IQ_SRC_SZ 2
++#define RG_TX_I_DC_MSK 0x000003ff
++#define RG_TX_I_DC_I_MSK 0xfffffc00
++#define RG_TX_I_DC_SFT 0
++#define RG_TX_I_DC_HI 9
++#define RG_TX_I_DC_SZ 10
++#define RG_TX_Q_DC_MSK 0x03ff0000
++#define RG_TX_Q_DC_I_MSK 0xfc00ffff
++#define RG_TX_Q_DC_SFT 16
++#define RG_TX_Q_DC_HI 25
++#define RG_TX_Q_DC_SZ 10
++#define RG_TX_IQ_THETA_MSK 0x0000001f
++#define RG_TX_IQ_THETA_I_MSK 0xffffffe0
++#define RG_TX_IQ_THETA_SFT 0
++#define RG_TX_IQ_THETA_HI 4
++#define RG_TX_IQ_THETA_SZ 5
++#define RG_TX_IQ_ALPHA_MSK 0x00001f00
++#define RG_TX_IQ_ALPHA_I_MSK 0xffffe0ff
++#define RG_TX_IQ_ALPHA_SFT 8
++#define RG_TX_IQ_ALPHA_HI 12
++#define RG_TX_IQ_ALPHA_SZ 5
++#define RG_TXIQ_NOSHRINK_MSK 0x00002000
++#define RG_TXIQ_NOSHRINK_I_MSK 0xffffdfff
++#define RG_TXIQ_NOSHRINK_SFT 13
++#define RG_TXIQ_NOSHRINK_HI 13
++#define RG_TXIQ_NOSHRINK_SZ 1
++#define RG_TX_I_OFFSET_MSK 0x00ff0000
++#define RG_TX_I_OFFSET_I_MSK 0xff00ffff
++#define RG_TX_I_OFFSET_SFT 16
++#define RG_TX_I_OFFSET_HI 23
++#define RG_TX_I_OFFSET_SZ 8
++#define RG_TX_Q_OFFSET_MSK 0xff000000
++#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff
++#define RG_TX_Q_OFFSET_SFT 24
++#define RG_TX_Q_OFFSET_HI 31
++#define RG_TX_Q_OFFSET_SZ 8
++#define RG_RX_IQ_THETA_MSK 0x0000001f
++#define RG_RX_IQ_THETA_I_MSK 0xffffffe0
++#define RG_RX_IQ_THETA_SFT 0
++#define RG_RX_IQ_THETA_HI 4
++#define RG_RX_IQ_THETA_SZ 5
++#define RG_RX_IQ_ALPHA_MSK 0x00001f00
++#define RG_RX_IQ_ALPHA_I_MSK 0xffffe0ff
++#define RG_RX_IQ_ALPHA_SFT 8
++#define RG_RX_IQ_ALPHA_HI 12
++#define RG_RX_IQ_ALPHA_SZ 5
++#define RG_RXIQ_NOSHRINK_MSK 0x00002000
++#define RG_RXIQ_NOSHRINK_I_MSK 0xffffdfff
++#define RG_RXIQ_NOSHRINK_SFT 13
++#define RG_RXIQ_NOSHRINK_HI 13
++#define RG_RXIQ_NOSHRINK_SZ 1
++#define RG_MA_DPTH_MSK 0x0000000f
++#define RG_MA_DPTH_I_MSK 0xfffffff0
++#define RG_MA_DPTH_SFT 0
++#define RG_MA_DPTH_HI 3
++#define RG_MA_DPTH_SZ 4
++#define RG_INTG_PH_MSK 0x000003f0
++#define RG_INTG_PH_I_MSK 0xfffffc0f
++#define RG_INTG_PH_SFT 4
++#define RG_INTG_PH_HI 9
++#define RG_INTG_PH_SZ 6
++#define RG_INTG_PRD_MSK 0x00001c00
++#define RG_INTG_PRD_I_MSK 0xffffe3ff
++#define RG_INTG_PRD_SFT 10
++#define RG_INTG_PRD_HI 12
++#define RG_INTG_PRD_SZ 3
++#define RG_INTG_MU_MSK 0x00006000
++#define RG_INTG_MU_I_MSK 0xffff9fff
++#define RG_INTG_MU_SFT 13
++#define RG_INTG_MU_HI 14
++#define RG_INTG_MU_SZ 2
++#define RG_IQCAL_SPRM_SELQ_MSK 0x00010000
++#define RG_IQCAL_SPRM_SELQ_I_MSK 0xfffeffff
++#define RG_IQCAL_SPRM_SELQ_SFT 16
++#define RG_IQCAL_SPRM_SELQ_HI 16
++#define RG_IQCAL_SPRM_SELQ_SZ 1
++#define RG_IQCAL_SPRM_EN_MSK 0x00020000
++#define RG_IQCAL_SPRM_EN_I_MSK 0xfffdffff
++#define RG_IQCAL_SPRM_EN_SFT 17
++#define RG_IQCAL_SPRM_EN_HI 17
++#define RG_IQCAL_SPRM_EN_SZ 1
++#define RG_IQCAL_SPRM_FREQ_MSK 0x00fc0000
++#define RG_IQCAL_SPRM_FREQ_I_MSK 0xff03ffff
++#define RG_IQCAL_SPRM_FREQ_SFT 18
++#define RG_IQCAL_SPRM_FREQ_HI 23
++#define RG_IQCAL_SPRM_FREQ_SZ 6
++#define RG_IQCAL_IQCOL_EN_MSK 0x01000000
++#define RG_IQCAL_IQCOL_EN_I_MSK 0xfeffffff
++#define RG_IQCAL_IQCOL_EN_SFT 24
++#define RG_IQCAL_IQCOL_EN_HI 24
++#define RG_IQCAL_IQCOL_EN_SZ 1
++#define RG_IQCAL_ALPHA_ESTM_EN_MSK 0x02000000
++#define RG_IQCAL_ALPHA_ESTM_EN_I_MSK 0xfdffffff
++#define RG_IQCAL_ALPHA_ESTM_EN_SFT 25
++#define RG_IQCAL_ALPHA_ESTM_EN_HI 25
++#define RG_IQCAL_ALPHA_ESTM_EN_SZ 1
++#define RG_IQCAL_DC_EN_MSK 0x04000000
++#define RG_IQCAL_DC_EN_I_MSK 0xfbffffff
++#define RG_IQCAL_DC_EN_SFT 26
++#define RG_IQCAL_DC_EN_HI 26
++#define RG_IQCAL_DC_EN_SZ 1
++#define RG_PHEST_STBY_MSK 0x08000000
++#define RG_PHEST_STBY_I_MSK 0xf7ffffff
++#define RG_PHEST_STBY_SFT 27
++#define RG_PHEST_STBY_HI 27
++#define RG_PHEST_STBY_SZ 1
++#define RG_PHEST_EN_MSK 0x10000000
++#define RG_PHEST_EN_I_MSK 0xefffffff
++#define RG_PHEST_EN_SFT 28
++#define RG_PHEST_EN_HI 28
++#define RG_PHEST_EN_SZ 1
++#define RG_GP_DIV_EN_MSK 0x20000000
++#define RG_GP_DIV_EN_I_MSK 0xdfffffff
++#define RG_GP_DIV_EN_SFT 29
++#define RG_GP_DIV_EN_HI 29
++#define RG_GP_DIV_EN_SZ 1
++#define RG_DPD_GAIN_EST_EN_MSK 0x40000000
++#define RG_DPD_GAIN_EST_EN_I_MSK 0xbfffffff
++#define RG_DPD_GAIN_EST_EN_SFT 30
++#define RG_DPD_GAIN_EST_EN_HI 30
++#define RG_DPD_GAIN_EST_EN_SZ 1
++#define RG_IQCAL_MULT_OP0_MSK 0x000003ff
++#define RG_IQCAL_MULT_OP0_I_MSK 0xfffffc00
++#define RG_IQCAL_MULT_OP0_SFT 0
++#define RG_IQCAL_MULT_OP0_HI 9
++#define RG_IQCAL_MULT_OP0_SZ 10
++#define RG_IQCAL_MULT_OP1_MSK 0x03ff0000
++#define RG_IQCAL_MULT_OP1_I_MSK 0xfc00ffff
++#define RG_IQCAL_MULT_OP1_SFT 16
++#define RG_IQCAL_MULT_OP1_HI 25
++#define RG_IQCAL_MULT_OP1_SZ 10
++#define RO_IQCAL_O_MSK 0x000fffff
++#define RO_IQCAL_O_I_MSK 0xfff00000
++#define RO_IQCAL_O_SFT 0
++#define RO_IQCAL_O_HI 19
++#define RO_IQCAL_O_SZ 20
++#define RO_IQCAL_SPRM_RDY_MSK 0x00100000
++#define RO_IQCAL_SPRM_RDY_I_MSK 0xffefffff
++#define RO_IQCAL_SPRM_RDY_SFT 20
++#define RO_IQCAL_SPRM_RDY_HI 20
++#define RO_IQCAL_SPRM_RDY_SZ 1
++#define RO_IQCAL_IQCOL_RDY_MSK 0x00200000
++#define RO_IQCAL_IQCOL_RDY_I_MSK 0xffdfffff
++#define RO_IQCAL_IQCOL_RDY_SFT 21
++#define RO_IQCAL_IQCOL_RDY_HI 21
++#define RO_IQCAL_IQCOL_RDY_SZ 1
++#define RO_IQCAL_ALPHA_ESTM_RDY_MSK 0x00400000
++#define RO_IQCAL_ALPHA_ESTM_RDY_I_MSK 0xffbfffff
++#define RO_IQCAL_ALPHA_ESTM_RDY_SFT 22
++#define RO_IQCAL_ALPHA_ESTM_RDY_HI 22
++#define RO_IQCAL_ALPHA_ESTM_RDY_SZ 1
++#define RO_IQCAL_DC_RDY_MSK 0x00800000
++#define RO_IQCAL_DC_RDY_I_MSK 0xff7fffff
++#define RO_IQCAL_DC_RDY_SFT 23
++#define RO_IQCAL_DC_RDY_HI 23
++#define RO_IQCAL_DC_RDY_SZ 1
++#define RO_IQCAL_MULT_RDY_MSK 0x01000000
++#define RO_IQCAL_MULT_RDY_I_MSK 0xfeffffff
++#define RO_IQCAL_MULT_RDY_SFT 24
++#define RO_IQCAL_MULT_RDY_HI 24
++#define RO_IQCAL_MULT_RDY_SZ 1
++#define RO_FFT_ENRG_RDY_MSK 0x02000000
++#define RO_FFT_ENRG_RDY_I_MSK 0xfdffffff
++#define RO_FFT_ENRG_RDY_SFT 25
++#define RO_FFT_ENRG_RDY_HI 25
++#define RO_FFT_ENRG_RDY_SZ 1
++#define RO_PHEST_RDY_MSK 0x04000000
++#define RO_PHEST_RDY_I_MSK 0xfbffffff
++#define RO_PHEST_RDY_SFT 26
++#define RO_PHEST_RDY_HI 26
++#define RO_PHEST_RDY_SZ 1
++#define RO_GP_DIV_RDY_MSK 0x08000000
++#define RO_GP_DIV_RDY_I_MSK 0xf7ffffff
++#define RO_GP_DIV_RDY_SFT 27
++#define RO_GP_DIV_RDY_HI 27
++#define RO_GP_DIV_RDY_SZ 1
++#define RO_GAIN_EST_RDY_MSK 0x10000000
++#define RO_GAIN_EST_RDY_I_MSK 0xefffffff
++#define RO_GAIN_EST_RDY_SFT 28
++#define RO_GAIN_EST_RDY_HI 28
++#define RO_GAIN_EST_RDY_SZ 1
++#define RO_AMP_O_MSK 0x000001ff
++#define RO_AMP_O_I_MSK 0xfffffe00
++#define RO_AMP_O_SFT 0
++#define RO_AMP_O_HI 8
++#define RO_AMP_O_SZ 9
++#define RG_RX_I_SCALE_MSK 0x000000ff
++#define RG_RX_I_SCALE_I_MSK 0xffffff00
++#define RG_RX_I_SCALE_SFT 0
++#define RG_RX_I_SCALE_HI 7
++#define RG_RX_I_SCALE_SZ 8
++#define RG_RX_Q_SCALE_MSK 0x0000ff00
++#define RG_RX_Q_SCALE_I_MSK 0xffff00ff
++#define RG_RX_Q_SCALE_SFT 8
++#define RG_RX_Q_SCALE_HI 15
++#define RG_RX_Q_SCALE_SZ 8
++#define RG_RX_I_OFFSET_MSK 0x00ff0000
++#define RG_RX_I_OFFSET_I_MSK 0xff00ffff
++#define RG_RX_I_OFFSET_SFT 16
++#define RG_RX_I_OFFSET_HI 23
++#define RG_RX_I_OFFSET_SZ 8
++#define RG_RX_Q_OFFSET_MSK 0xff000000
++#define RG_RX_Q_OFFSET_I_MSK 0x00ffffff
++#define RG_RX_Q_OFFSET_SFT 24
++#define RG_RX_Q_OFFSET_HI 31
++#define RG_RX_Q_OFFSET_SZ 8
++#define RG_RX_IQ_SWP_MSK 0x00000001
++#define RG_RX_IQ_SWP_I_MSK 0xfffffffe
++#define RG_RX_IQ_SWP_SFT 0
++#define RG_RX_IQ_SWP_HI 0
++#define RG_RX_IQ_SWP_SZ 1
++#define RG_RX_SGN_IN_MSK 0x00000002
++#define RG_RX_SGN_IN_I_MSK 0xfffffffd
++#define RG_RX_SGN_IN_SFT 1
++#define RG_RX_SGN_IN_HI 1
++#define RG_RX_SGN_IN_SZ 1
++#define RG_RX_IQ_SRC_MSK 0x0000000c
++#define RG_RX_IQ_SRC_I_MSK 0xfffffff3
++#define RG_RX_IQ_SRC_SFT 2
++#define RG_RX_IQ_SRC_HI 3
++#define RG_RX_IQ_SRC_SZ 2
++#define RG_ACI_GAIN_MSK 0x00000ff0
++#define RG_ACI_GAIN_I_MSK 0xfffff00f
++#define RG_ACI_GAIN_SFT 4
++#define RG_ACI_GAIN_HI 11
++#define RG_ACI_GAIN_SZ 8
++#define RG_FFT_EN_MSK 0x00001000
++#define RG_FFT_EN_I_MSK 0xffffefff
++#define RG_FFT_EN_SFT 12
++#define RG_FFT_EN_HI 12
++#define RG_FFT_EN_SZ 1
++#define RG_FFT_MOD_MSK 0x00002000
++#define RG_FFT_MOD_I_MSK 0xffffdfff
++#define RG_FFT_MOD_SFT 13
++#define RG_FFT_MOD_HI 13
++#define RG_FFT_MOD_SZ 1
++#define RG_FFT_SCALE_MSK 0x00ffc000
++#define RG_FFT_SCALE_I_MSK 0xff003fff
++#define RG_FFT_SCALE_SFT 14
++#define RG_FFT_SCALE_HI 23
++#define RG_FFT_SCALE_SZ 10
++#define RG_FFT_ENRG_FREQ_MSK 0x3f000000
++#define RG_FFT_ENRG_FREQ_I_MSK 0xc0ffffff
++#define RG_FFT_ENRG_FREQ_SFT 24
++#define RG_FFT_ENRG_FREQ_HI 29
++#define RG_FFT_ENRG_FREQ_SZ 6
++#define RG_FPGA_80M_PH_UP_MSK 0x40000000
++#define RG_FPGA_80M_PH_UP_I_MSK 0xbfffffff
++#define RG_FPGA_80M_PH_UP_SFT 30
++#define RG_FPGA_80M_PH_UP_HI 30
++#define RG_FPGA_80M_PH_UP_SZ 1
++#define RG_FPGA_80M_PH_STP_MSK 0x80000000
++#define RG_FPGA_80M_PH_STP_I_MSK 0x7fffffff
++#define RG_FPGA_80M_PH_STP_SFT 31
++#define RG_FPGA_80M_PH_STP_HI 31
++#define RG_FPGA_80M_PH_STP_SZ 1
++#define RG_ADC2LA_SEL_MSK 0x00000001
++#define RG_ADC2LA_SEL_I_MSK 0xfffffffe
++#define RG_ADC2LA_SEL_SFT 0
++#define RG_ADC2LA_SEL_HI 0
++#define RG_ADC2LA_SEL_SZ 1
++#define RG_ADC2LA_CLKPH_MSK 0x00000002
++#define RG_ADC2LA_CLKPH_I_MSK 0xfffffffd
++#define RG_ADC2LA_CLKPH_SFT 1
++#define RG_ADC2LA_CLKPH_HI 1
++#define RG_ADC2LA_CLKPH_SZ 1
++#define RG_RXIQ_EMU_IDX_MSK 0x0000000f
++#define RG_RXIQ_EMU_IDX_I_MSK 0xfffffff0
++#define RG_RXIQ_EMU_IDX_SFT 0
++#define RG_RXIQ_EMU_IDX_HI 3
++#define RG_RXIQ_EMU_IDX_SZ 4
++#define RG_IQCAL_BP_ACI_MSK 0x00000010
++#define RG_IQCAL_BP_ACI_I_MSK 0xffffffef
++#define RG_IQCAL_BP_ACI_SFT 4
++#define RG_IQCAL_BP_ACI_HI 4
++#define RG_IQCAL_BP_ACI_SZ 1
++#define RG_DPD_AM_EN_MSK 0x00000001
++#define RG_DPD_AM_EN_I_MSK 0xfffffffe
++#define RG_DPD_AM_EN_SFT 0
++#define RG_DPD_AM_EN_HI 0
++#define RG_DPD_AM_EN_SZ 1
++#define RG_DPD_PM_EN_MSK 0x00000002
++#define RG_DPD_PM_EN_I_MSK 0xfffffffd
++#define RG_DPD_PM_EN_SFT 1
++#define RG_DPD_PM_EN_HI 1
++#define RG_DPD_PM_EN_SZ 1
++#define RG_DPD_PM_AMSEL_MSK 0x00000004
++#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb
++#define RG_DPD_PM_AMSEL_SFT 2
++#define RG_DPD_PM_AMSEL_HI 2
++#define RG_DPD_PM_AMSEL_SZ 1
++#define RG_DPD_020_GAIN_MSK 0x000003ff
++#define RG_DPD_020_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_020_GAIN_SFT 0
++#define RG_DPD_020_GAIN_HI 9
++#define RG_DPD_020_GAIN_SZ 10
++#define RG_DPD_040_GAIN_MSK 0x03ff0000
++#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_040_GAIN_SFT 16
++#define RG_DPD_040_GAIN_HI 25
++#define RG_DPD_040_GAIN_SZ 10
++#define RG_DPD_060_GAIN_MSK 0x000003ff
++#define RG_DPD_060_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_060_GAIN_SFT 0
++#define RG_DPD_060_GAIN_HI 9
++#define RG_DPD_060_GAIN_SZ 10
++#define RG_DPD_080_GAIN_MSK 0x03ff0000
++#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_080_GAIN_SFT 16
++#define RG_DPD_080_GAIN_HI 25
++#define RG_DPD_080_GAIN_SZ 10
++#define RG_DPD_0A0_GAIN_MSK 0x000003ff
++#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_0A0_GAIN_SFT 0
++#define RG_DPD_0A0_GAIN_HI 9
++#define RG_DPD_0A0_GAIN_SZ 10
++#define RG_DPD_0C0_GAIN_MSK 0x03ff0000
++#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_0C0_GAIN_SFT 16
++#define RG_DPD_0C0_GAIN_HI 25
++#define RG_DPD_0C0_GAIN_SZ 10
++#define RG_DPD_0D0_GAIN_MSK 0x000003ff
++#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_0D0_GAIN_SFT 0
++#define RG_DPD_0D0_GAIN_HI 9
++#define RG_DPD_0D0_GAIN_SZ 10
++#define RG_DPD_0E0_GAIN_MSK 0x03ff0000
++#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_0E0_GAIN_SFT 16
++#define RG_DPD_0E0_GAIN_HI 25
++#define RG_DPD_0E0_GAIN_SZ 10
++#define RG_DPD_0F0_GAIN_MSK 0x000003ff
++#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_0F0_GAIN_SFT 0
++#define RG_DPD_0F0_GAIN_HI 9
++#define RG_DPD_0F0_GAIN_SZ 10
++#define RG_DPD_100_GAIN_MSK 0x03ff0000
++#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_100_GAIN_SFT 16
++#define RG_DPD_100_GAIN_HI 25
++#define RG_DPD_100_GAIN_SZ 10
++#define RG_DPD_110_GAIN_MSK 0x000003ff
++#define RG_DPD_110_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_110_GAIN_SFT 0
++#define RG_DPD_110_GAIN_HI 9
++#define RG_DPD_110_GAIN_SZ 10
++#define RG_DPD_120_GAIN_MSK 0x03ff0000
++#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_120_GAIN_SFT 16
++#define RG_DPD_120_GAIN_HI 25
++#define RG_DPD_120_GAIN_SZ 10
++#define RG_DPD_130_GAIN_MSK 0x000003ff
++#define RG_DPD_130_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_130_GAIN_SFT 0
++#define RG_DPD_130_GAIN_HI 9
++#define RG_DPD_130_GAIN_SZ 10
++#define RG_DPD_140_GAIN_MSK 0x03ff0000
++#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_140_GAIN_SFT 16
++#define RG_DPD_140_GAIN_HI 25
++#define RG_DPD_140_GAIN_SZ 10
++#define RG_DPD_150_GAIN_MSK 0x000003ff
++#define RG_DPD_150_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_150_GAIN_SFT 0
++#define RG_DPD_150_GAIN_HI 9
++#define RG_DPD_150_GAIN_SZ 10
++#define RG_DPD_160_GAIN_MSK 0x03ff0000
++#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_160_GAIN_SFT 16
++#define RG_DPD_160_GAIN_HI 25
++#define RG_DPD_160_GAIN_SZ 10
++#define RG_DPD_170_GAIN_MSK 0x000003ff
++#define RG_DPD_170_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_170_GAIN_SFT 0
++#define RG_DPD_170_GAIN_HI 9
++#define RG_DPD_170_GAIN_SZ 10
++#define RG_DPD_180_GAIN_MSK 0x03ff0000
++#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_180_GAIN_SFT 16
++#define RG_DPD_180_GAIN_HI 25
++#define RG_DPD_180_GAIN_SZ 10
++#define RG_DPD_190_GAIN_MSK 0x000003ff
++#define RG_DPD_190_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_190_GAIN_SFT 0
++#define RG_DPD_190_GAIN_HI 9
++#define RG_DPD_190_GAIN_SZ 10
++#define RG_DPD_1A0_GAIN_MSK 0x03ff0000
++#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_1A0_GAIN_SFT 16
++#define RG_DPD_1A0_GAIN_HI 25
++#define RG_DPD_1A0_GAIN_SZ 10
++#define RG_DPD_1B0_GAIN_MSK 0x000003ff
++#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_1B0_GAIN_SFT 0
++#define RG_DPD_1B0_GAIN_HI 9
++#define RG_DPD_1B0_GAIN_SZ 10
++#define RG_DPD_1C0_GAIN_MSK 0x03ff0000
++#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_1C0_GAIN_SFT 16
++#define RG_DPD_1C0_GAIN_HI 25
++#define RG_DPD_1C0_GAIN_SZ 10
++#define RG_DPD_1D0_GAIN_MSK 0x000003ff
++#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_1D0_GAIN_SFT 0
++#define RG_DPD_1D0_GAIN_HI 9
++#define RG_DPD_1D0_GAIN_SZ 10
++#define RG_DPD_1E0_GAIN_MSK 0x03ff0000
++#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_1E0_GAIN_SFT 16
++#define RG_DPD_1E0_GAIN_HI 25
++#define RG_DPD_1E0_GAIN_SZ 10
++#define RG_DPD_1F0_GAIN_MSK 0x000003ff
++#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_1F0_GAIN_SFT 0
++#define RG_DPD_1F0_GAIN_HI 9
++#define RG_DPD_1F0_GAIN_SZ 10
++#define RG_DPD_200_GAIN_MSK 0x03ff0000
++#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_200_GAIN_SFT 16
++#define RG_DPD_200_GAIN_HI 25
++#define RG_DPD_200_GAIN_SZ 10
++#define RG_DPD_020_PH_MSK 0x00001fff
++#define RG_DPD_020_PH_I_MSK 0xffffe000
++#define RG_DPD_020_PH_SFT 0
++#define RG_DPD_020_PH_HI 12
++#define RG_DPD_020_PH_SZ 13
++#define RG_DPD_040_PH_MSK 0x1fff0000
++#define RG_DPD_040_PH_I_MSK 0xe000ffff
++#define RG_DPD_040_PH_SFT 16
++#define RG_DPD_040_PH_HI 28
++#define RG_DPD_040_PH_SZ 13
++#define RG_DPD_060_PH_MSK 0x00001fff
++#define RG_DPD_060_PH_I_MSK 0xffffe000
++#define RG_DPD_060_PH_SFT 0
++#define RG_DPD_060_PH_HI 12
++#define RG_DPD_060_PH_SZ 13
++#define RG_DPD_080_PH_MSK 0x1fff0000
++#define RG_DPD_080_PH_I_MSK 0xe000ffff
++#define RG_DPD_080_PH_SFT 16
++#define RG_DPD_080_PH_HI 28
++#define RG_DPD_080_PH_SZ 13
++#define RG_DPD_0A0_PH_MSK 0x00001fff
++#define RG_DPD_0A0_PH_I_MSK 0xffffe000
++#define RG_DPD_0A0_PH_SFT 0
++#define RG_DPD_0A0_PH_HI 12
++#define RG_DPD_0A0_PH_SZ 13
++#define RG_DPD_0C0_PH_MSK 0x1fff0000
++#define RG_DPD_0C0_PH_I_MSK 0xe000ffff
++#define RG_DPD_0C0_PH_SFT 16
++#define RG_DPD_0C0_PH_HI 28
++#define RG_DPD_0C0_PH_SZ 13
++#define RG_DPD_0D0_PH_MSK 0x00001fff
++#define RG_DPD_0D0_PH_I_MSK 0xffffe000
++#define RG_DPD_0D0_PH_SFT 0
++#define RG_DPD_0D0_PH_HI 12
++#define RG_DPD_0D0_PH_SZ 13
++#define RG_DPD_0E0_PH_MSK 0x1fff0000
++#define RG_DPD_0E0_PH_I_MSK 0xe000ffff
++#define RG_DPD_0E0_PH_SFT 16
++#define RG_DPD_0E0_PH_HI 28
++#define RG_DPD_0E0_PH_SZ 13
++#define RG_DPD_0F0_PH_MSK 0x00001fff
++#define RG_DPD_0F0_PH_I_MSK 0xffffe000
++#define RG_DPD_0F0_PH_SFT 0
++#define RG_DPD_0F0_PH_HI 12
++#define RG_DPD_0F0_PH_SZ 13
++#define RG_DPD_100_PH_MSK 0x1fff0000
++#define RG_DPD_100_PH_I_MSK 0xe000ffff
++#define RG_DPD_100_PH_SFT 16
++#define RG_DPD_100_PH_HI 28
++#define RG_DPD_100_PH_SZ 13
++#define RG_DPD_110_PH_MSK 0x00001fff
++#define RG_DPD_110_PH_I_MSK 0xffffe000
++#define RG_DPD_110_PH_SFT 0
++#define RG_DPD_110_PH_HI 12
++#define RG_DPD_110_PH_SZ 13
++#define RG_DPD_120_PH_MSK 0x1fff0000
++#define RG_DPD_120_PH_I_MSK 0xe000ffff
++#define RG_DPD_120_PH_SFT 16
++#define RG_DPD_120_PH_HI 28
++#define RG_DPD_120_PH_SZ 13
++#define RG_DPD_130_PH_MSK 0x00001fff
++#define RG_DPD_130_PH_I_MSK 0xffffe000
++#define RG_DPD_130_PH_SFT 0
++#define RG_DPD_130_PH_HI 12
++#define RG_DPD_130_PH_SZ 13
++#define RG_DPD_140_PH_MSK 0x1fff0000
++#define RG_DPD_140_PH_I_MSK 0xe000ffff
++#define RG_DPD_140_PH_SFT 16
++#define RG_DPD_140_PH_HI 28
++#define RG_DPD_140_PH_SZ 13
++#define RG_DPD_150_PH_MSK 0x00001fff
++#define RG_DPD_150_PH_I_MSK 0xffffe000
++#define RG_DPD_150_PH_SFT 0
++#define RG_DPD_150_PH_HI 12
++#define RG_DPD_150_PH_SZ 13
++#define RG_DPD_160_PH_MSK 0x1fff0000
++#define RG_DPD_160_PH_I_MSK 0xe000ffff
++#define RG_DPD_160_PH_SFT 16
++#define RG_DPD_160_PH_HI 28
++#define RG_DPD_160_PH_SZ 13
++#define RG_DPD_170_PH_MSK 0x00001fff
++#define RG_DPD_170_PH_I_MSK 0xffffe000
++#define RG_DPD_170_PH_SFT 0
++#define RG_DPD_170_PH_HI 12
++#define RG_DPD_170_PH_SZ 13
++#define RG_DPD_180_PH_MSK 0x1fff0000
++#define RG_DPD_180_PH_I_MSK 0xe000ffff
++#define RG_DPD_180_PH_SFT 16
++#define RG_DPD_180_PH_HI 28
++#define RG_DPD_180_PH_SZ 13
++#define RG_DPD_190_PH_MSK 0x00001fff
++#define RG_DPD_190_PH_I_MSK 0xffffe000
++#define RG_DPD_190_PH_SFT 0
++#define RG_DPD_190_PH_HI 12
++#define RG_DPD_190_PH_SZ 13
++#define RG_DPD_1A0_PH_MSK 0x1fff0000
++#define RG_DPD_1A0_PH_I_MSK 0xe000ffff
++#define RG_DPD_1A0_PH_SFT 16
++#define RG_DPD_1A0_PH_HI 28
++#define RG_DPD_1A0_PH_SZ 13
++#define RG_DPD_1B0_PH_MSK 0x00001fff
++#define RG_DPD_1B0_PH_I_MSK 0xffffe000
++#define RG_DPD_1B0_PH_SFT 0
++#define RG_DPD_1B0_PH_HI 12
++#define RG_DPD_1B0_PH_SZ 13
++#define RG_DPD_1C0_PH_MSK 0x1fff0000
++#define RG_DPD_1C0_PH_I_MSK 0xe000ffff
++#define RG_DPD_1C0_PH_SFT 16
++#define RG_DPD_1C0_PH_HI 28
++#define RG_DPD_1C0_PH_SZ 13
++#define RG_DPD_1D0_PH_MSK 0x00001fff
++#define RG_DPD_1D0_PH_I_MSK 0xffffe000
++#define RG_DPD_1D0_PH_SFT 0
++#define RG_DPD_1D0_PH_HI 12
++#define RG_DPD_1D0_PH_SZ 13
++#define RG_DPD_1E0_PH_MSK 0x1fff0000
++#define RG_DPD_1E0_PH_I_MSK 0xe000ffff
++#define RG_DPD_1E0_PH_SFT 16
++#define RG_DPD_1E0_PH_HI 28
++#define RG_DPD_1E0_PH_SZ 13
++#define RG_DPD_1F0_PH_MSK 0x00001fff
++#define RG_DPD_1F0_PH_I_MSK 0xffffe000
++#define RG_DPD_1F0_PH_SFT 0
++#define RG_DPD_1F0_PH_HI 12
++#define RG_DPD_1F0_PH_SZ 13
++#define RG_DPD_200_PH_MSK 0x1fff0000
++#define RG_DPD_200_PH_I_MSK 0xe000ffff
++#define RG_DPD_200_PH_SFT 16
++#define RG_DPD_200_PH_HI 28
++#define RG_DPD_200_PH_SZ 13
++#define RG_DPD_GAIN_EST_Y0_MSK 0x000001ff
++#define RG_DPD_GAIN_EST_Y0_I_MSK 0xfffffe00
++#define RG_DPD_GAIN_EST_Y0_SFT 0
++#define RG_DPD_GAIN_EST_Y0_HI 8
++#define RG_DPD_GAIN_EST_Y0_SZ 9
++#define RG_DPD_GAIN_EST_Y1_MSK 0x01ff0000
++#define RG_DPD_GAIN_EST_Y1_I_MSK 0xfe00ffff
++#define RG_DPD_GAIN_EST_Y1_SFT 16
++#define RG_DPD_GAIN_EST_Y1_HI 24
++#define RG_DPD_GAIN_EST_Y1_SZ 9
++#define RG_DPD_LOOP_GAIN_MSK 0x000003ff
++#define RG_DPD_LOOP_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_LOOP_GAIN_SFT 0
++#define RG_DPD_LOOP_GAIN_HI 9
++#define RG_DPD_LOOP_GAIN_SZ 10
++#define RG_DPD_GAIN_EST_X0_MSK 0x000001ff
++#define RG_DPD_GAIN_EST_X0_I_MSK 0xfffffe00
++#define RG_DPD_GAIN_EST_X0_SFT 0
++#define RG_DPD_GAIN_EST_X0_HI 8
++#define RG_DPD_GAIN_EST_X0_SZ 9
++#define RO_DPD_GAIN_MSK 0x03ff0000
++#define RO_DPD_GAIN_I_MSK 0xfc00ffff
++#define RO_DPD_GAIN_SFT 16
++#define RO_DPD_GAIN_HI 25
++#define RO_DPD_GAIN_SZ 10
++#define TX_SCALE_11B_MSK 0x000000ff
++#define TX_SCALE_11B_I_MSK 0xffffff00
++#define TX_SCALE_11B_SFT 0
++#define TX_SCALE_11B_HI 7
++#define TX_SCALE_11B_SZ 8
++#define TX_SCALE_11B_P0D5_MSK 0x0000ff00
++#define TX_SCALE_11B_P0D5_I_MSK 0xffff00ff
++#define TX_SCALE_11B_P0D5_SFT 8
++#define TX_SCALE_11B_P0D5_HI 15
++#define TX_SCALE_11B_P0D5_SZ 8
++#define TX_SCALE_11G_MSK 0x00ff0000
++#define TX_SCALE_11G_I_MSK 0xff00ffff
++#define TX_SCALE_11G_SFT 16
++#define TX_SCALE_11G_HI 23
++#define TX_SCALE_11G_SZ 8
++#define TX_SCALE_11G_P0D5_MSK 0xff000000
++#define TX_SCALE_11G_P0D5_I_MSK 0x00ffffff
++#define TX_SCALE_11G_P0D5_SFT 24
++#define TX_SCALE_11G_P0D5_HI 31
++#define TX_SCALE_11G_P0D5_SZ 8
++#define RG_EN_MANUAL_MSK 0x00000001
++#define RG_EN_MANUAL_I_MSK 0xfffffffe
++#define RG_EN_MANUAL_SFT 0
++#define RG_EN_MANUAL_HI 0
++#define RG_EN_MANUAL_SZ 1
++#define RG_TX_EN_MSK 0x00000002
++#define RG_TX_EN_I_MSK 0xfffffffd
++#define RG_TX_EN_SFT 1
++#define RG_TX_EN_HI 1
++#define RG_TX_EN_SZ 1
++#define RG_TX_PA_EN_MSK 0x00000004
++#define RG_TX_PA_EN_I_MSK 0xfffffffb
++#define RG_TX_PA_EN_SFT 2
++#define RG_TX_PA_EN_HI 2
++#define RG_TX_PA_EN_SZ 1
++#define RG_TX_DAC_EN_MSK 0x00000008
++#define RG_TX_DAC_EN_I_MSK 0xfffffff7
++#define RG_TX_DAC_EN_SFT 3
++#define RG_TX_DAC_EN_HI 3
++#define RG_TX_DAC_EN_SZ 1
++#define RG_RX_AGC_MSK 0x00000010
++#define RG_RX_AGC_I_MSK 0xffffffef
++#define RG_RX_AGC_SFT 4
++#define RG_RX_AGC_HI 4
++#define RG_RX_AGC_SZ 1
++#define RG_RX_GAIN_MANUAL_MSK 0x00000020
++#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
++#define RG_RX_GAIN_MANUAL_SFT 5
++#define RG_RX_GAIN_MANUAL_HI 5
++#define RG_RX_GAIN_MANUAL_SZ 1
++#define RG_RFG_MSK 0x000000c0
++#define RG_RFG_I_MSK 0xffffff3f
++#define RG_RFG_SFT 6
++#define RG_RFG_HI 7
++#define RG_RFG_SZ 2
++#define RG_PGAG_MSK 0x00000f00
++#define RG_PGAG_I_MSK 0xfffff0ff
++#define RG_PGAG_SFT 8
++#define RG_PGAG_HI 11
++#define RG_PGAG_SZ 4
++#define RG_MODE_MSK 0x00003000
++#define RG_MODE_I_MSK 0xffffcfff
++#define RG_MODE_SFT 12
++#define RG_MODE_HI 13
++#define RG_MODE_SZ 2
++#define RG_EN_TX_TRSW_MSK 0x00004000
++#define RG_EN_TX_TRSW_I_MSK 0xffffbfff
++#define RG_EN_TX_TRSW_SFT 14
++#define RG_EN_TX_TRSW_HI 14
++#define RG_EN_TX_TRSW_SZ 1
++#define RG_EN_SX_MSK 0x00008000
++#define RG_EN_SX_I_MSK 0xffff7fff
++#define RG_EN_SX_SFT 15
++#define RG_EN_SX_HI 15
++#define RG_EN_SX_SZ 1
++#define RG_EN_RX_LNA_MSK 0x00010000
++#define RG_EN_RX_LNA_I_MSK 0xfffeffff
++#define RG_EN_RX_LNA_SFT 16
++#define RG_EN_RX_LNA_HI 16
++#define RG_EN_RX_LNA_SZ 1
++#define RG_EN_RX_MIXER_MSK 0x00020000
++#define RG_EN_RX_MIXER_I_MSK 0xfffdffff
++#define RG_EN_RX_MIXER_SFT 17
++#define RG_EN_RX_MIXER_HI 17
++#define RG_EN_RX_MIXER_SZ 1
++#define RG_EN_RX_DIV2_MSK 0x00040000
++#define RG_EN_RX_DIV2_I_MSK 0xfffbffff
++#define RG_EN_RX_DIV2_SFT 18
++#define RG_EN_RX_DIV2_HI 18
++#define RG_EN_RX_DIV2_SZ 1
++#define RG_EN_RX_LOBUF_MSK 0x00080000
++#define RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
++#define RG_EN_RX_LOBUF_SFT 19
++#define RG_EN_RX_LOBUF_HI 19
++#define RG_EN_RX_LOBUF_SZ 1
++#define RG_EN_RX_TZ_MSK 0x00100000
++#define RG_EN_RX_TZ_I_MSK 0xffefffff
++#define RG_EN_RX_TZ_SFT 20
++#define RG_EN_RX_TZ_HI 20
++#define RG_EN_RX_TZ_SZ 1
++#define RG_EN_RX_FILTER_MSK 0x00200000
++#define RG_EN_RX_FILTER_I_MSK 0xffdfffff
++#define RG_EN_RX_FILTER_SFT 21
++#define RG_EN_RX_FILTER_HI 21
++#define RG_EN_RX_FILTER_SZ 1
++#define RG_EN_RX_HPF_MSK 0x00400000
++#define RG_EN_RX_HPF_I_MSK 0xffbfffff
++#define RG_EN_RX_HPF_SFT 22
++#define RG_EN_RX_HPF_HI 22
++#define RG_EN_RX_HPF_SZ 1
++#define RG_EN_RX_RSSI_MSK 0x00800000
++#define RG_EN_RX_RSSI_I_MSK 0xff7fffff
++#define RG_EN_RX_RSSI_SFT 23
++#define RG_EN_RX_RSSI_HI 23
++#define RG_EN_RX_RSSI_SZ 1
++#define RG_EN_ADC_MSK 0x01000000
++#define RG_EN_ADC_I_MSK 0xfeffffff
++#define RG_EN_ADC_SFT 24
++#define RG_EN_ADC_HI 24
++#define RG_EN_ADC_SZ 1
++#define RG_EN_TX_MOD_MSK 0x02000000
++#define RG_EN_TX_MOD_I_MSK 0xfdffffff
++#define RG_EN_TX_MOD_SFT 25
++#define RG_EN_TX_MOD_HI 25
++#define RG_EN_TX_MOD_SZ 1
++#define RG_EN_TX_DIV2_MSK 0x04000000
++#define RG_EN_TX_DIV2_I_MSK 0xfbffffff
++#define RG_EN_TX_DIV2_SFT 26
++#define RG_EN_TX_DIV2_HI 26
++#define RG_EN_TX_DIV2_SZ 1
++#define RG_EN_TX_DIV2_BUF_MSK 0x08000000
++#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
++#define RG_EN_TX_DIV2_BUF_SFT 27
++#define RG_EN_TX_DIV2_BUF_HI 27
++#define RG_EN_TX_DIV2_BUF_SZ 1
++#define RG_EN_TX_LOBF_MSK 0x10000000
++#define RG_EN_TX_LOBF_I_MSK 0xefffffff
++#define RG_EN_TX_LOBF_SFT 28
++#define RG_EN_TX_LOBF_HI 28
++#define RG_EN_TX_LOBF_SZ 1
++#define RG_EN_RX_LOBF_MSK 0x20000000
++#define RG_EN_RX_LOBF_I_MSK 0xdfffffff
++#define RG_EN_RX_LOBF_SFT 29
++#define RG_EN_RX_LOBF_HI 29
++#define RG_EN_RX_LOBF_SZ 1
++#define RG_SEL_DPLL_CLK_MSK 0x40000000
++#define RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
++#define RG_SEL_DPLL_CLK_SFT 30
++#define RG_SEL_DPLL_CLK_HI 30
++#define RG_SEL_DPLL_CLK_SZ 1
++#define RG_EN_CLK_960MBY13_UART_MSK 0x80000000
++#define RG_EN_CLK_960MBY13_UART_I_MSK 0x7fffffff
++#define RG_EN_CLK_960MBY13_UART_SFT 31
++#define RG_EN_CLK_960MBY13_UART_HI 31
++#define RG_EN_CLK_960MBY13_UART_SZ 1
++#define RG_EN_TX_DPD_MSK 0x00000001
++#define RG_EN_TX_DPD_I_MSK 0xfffffffe
++#define RG_EN_TX_DPD_SFT 0
++#define RG_EN_TX_DPD_HI 0
++#define RG_EN_TX_DPD_SZ 1
++#define RG_EN_TX_TSSI_MSK 0x00000002
++#define RG_EN_TX_TSSI_I_MSK 0xfffffffd
++#define RG_EN_TX_TSSI_SFT 1
++#define RG_EN_TX_TSSI_HI 1
++#define RG_EN_TX_TSSI_SZ 1
++#define RG_EN_RX_IQCAL_MSK 0x00000004
++#define RG_EN_RX_IQCAL_I_MSK 0xfffffffb
++#define RG_EN_RX_IQCAL_SFT 2
++#define RG_EN_RX_IQCAL_HI 2
++#define RG_EN_RX_IQCAL_SZ 1
++#define RG_EN_TX_DAC_CAL_MSK 0x00000008
++#define RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
++#define RG_EN_TX_DAC_CAL_SFT 3
++#define RG_EN_TX_DAC_CAL_HI 3
++#define RG_EN_TX_DAC_CAL_SZ 1
++#define RG_EN_TX_SELF_MIXER_MSK 0x00000010
++#define RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
++#define RG_EN_TX_SELF_MIXER_SFT 4
++#define RG_EN_TX_SELF_MIXER_HI 4
++#define RG_EN_TX_SELF_MIXER_SZ 1
++#define RG_EN_TX_DAC_OUT_MSK 0x00000020
++#define RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
++#define RG_EN_TX_DAC_OUT_SFT 5
++#define RG_EN_TX_DAC_OUT_HI 5
++#define RG_EN_TX_DAC_OUT_SZ 1
++#define RG_EN_LDO_RX_FE_MSK 0x00000040
++#define RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
++#define RG_EN_LDO_RX_FE_SFT 6
++#define RG_EN_LDO_RX_FE_HI 6
++#define RG_EN_LDO_RX_FE_SZ 1
++#define RG_EN_LDO_ABB_MSK 0x00000080
++#define RG_EN_LDO_ABB_I_MSK 0xffffff7f
++#define RG_EN_LDO_ABB_SFT 7
++#define RG_EN_LDO_ABB_HI 7
++#define RG_EN_LDO_ABB_SZ 1
++#define RG_EN_LDO_AFE_MSK 0x00000100
++#define RG_EN_LDO_AFE_I_MSK 0xfffffeff
++#define RG_EN_LDO_AFE_SFT 8
++#define RG_EN_LDO_AFE_HI 8
++#define RG_EN_LDO_AFE_SZ 1
++#define RG_EN_SX_CHPLDO_MSK 0x00000200
++#define RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
++#define RG_EN_SX_CHPLDO_SFT 9
++#define RG_EN_SX_CHPLDO_HI 9
++#define RG_EN_SX_CHPLDO_SZ 1
++#define RG_EN_SX_LOBFLDO_MSK 0x00000400
++#define RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
++#define RG_EN_SX_LOBFLDO_SFT 10
++#define RG_EN_SX_LOBFLDO_HI 10
++#define RG_EN_SX_LOBFLDO_SZ 1
++#define RG_EN_IREF_RX_MSK 0x00000800
++#define RG_EN_IREF_RX_I_MSK 0xfffff7ff
++#define RG_EN_IREF_RX_SFT 11
++#define RG_EN_IREF_RX_HI 11
++#define RG_EN_IREF_RX_SZ 1
++#define RG_EN_TX_DAC_VOUT_MSK 0x00002000
++#define RG_EN_TX_DAC_VOUT_I_MSK 0xffffdfff
++#define RG_EN_TX_DAC_VOUT_SFT 13
++#define RG_EN_TX_DAC_VOUT_HI 13
++#define RG_EN_TX_DAC_VOUT_SZ 1
++#define RG_EN_SX_LCK_BIN_MSK 0x00004000
++#define RG_EN_SX_LCK_BIN_I_MSK 0xffffbfff
++#define RG_EN_SX_LCK_BIN_SFT 14
++#define RG_EN_SX_LCK_BIN_HI 14
++#define RG_EN_SX_LCK_BIN_SZ 1
++#define RG_RTC_CAL_MODE_MSK 0x00010000
++#define RG_RTC_CAL_MODE_I_MSK 0xfffeffff
++#define RG_RTC_CAL_MODE_SFT 16
++#define RG_RTC_CAL_MODE_HI 16
++#define RG_RTC_CAL_MODE_SZ 1
++#define RG_EN_IQPAD_IOSW_MSK 0x00020000
++#define RG_EN_IQPAD_IOSW_I_MSK 0xfffdffff
++#define RG_EN_IQPAD_IOSW_SFT 17
++#define RG_EN_IQPAD_IOSW_HI 17
++#define RG_EN_IQPAD_IOSW_SZ 1
++#define RG_EN_TESTPAD_IOSW_MSK 0x00040000
++#define RG_EN_TESTPAD_IOSW_I_MSK 0xfffbffff
++#define RG_EN_TESTPAD_IOSW_SFT 18
++#define RG_EN_TESTPAD_IOSW_HI 18
++#define RG_EN_TESTPAD_IOSW_SZ 1
++#define RG_EN_TRXBF_BYPASS_MSK 0x00080000
++#define RG_EN_TRXBF_BYPASS_I_MSK 0xfff7ffff
++#define RG_EN_TRXBF_BYPASS_SFT 19
++#define RG_EN_TRXBF_BYPASS_HI 19
++#define RG_EN_TRXBF_BYPASS_SZ 1
++#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007
++#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
++#define RG_LDO_LEVEL_RX_FE_SFT 0
++#define RG_LDO_LEVEL_RX_FE_HI 2
++#define RG_LDO_LEVEL_RX_FE_SZ 3
++#define RG_LDO_LEVEL_ABB_MSK 0x00000038
++#define RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
++#define RG_LDO_LEVEL_ABB_SFT 3
++#define RG_LDO_LEVEL_ABB_HI 5
++#define RG_LDO_LEVEL_ABB_SZ 3
++#define RG_LDO_LEVEL_AFE_MSK 0x000001c0
++#define RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
++#define RG_LDO_LEVEL_AFE_SFT 6
++#define RG_LDO_LEVEL_AFE_HI 8
++#define RG_LDO_LEVEL_AFE_SZ 3
++#define RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
++#define RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
++#define RG_SX_LDO_CHP_LEVEL_SFT 9
++#define RG_SX_LDO_CHP_LEVEL_HI 11
++#define RG_SX_LDO_CHP_LEVEL_SZ 3
++#define RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
++#define RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
++#define RG_SX_LDO_LOBF_LEVEL_SFT 12
++#define RG_SX_LDO_LOBF_LEVEL_HI 14
++#define RG_SX_LDO_LOBF_LEVEL_SZ 3
++#define RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
++#define RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
++#define RG_SX_LDO_XOSC_LEVEL_SFT 15
++#define RG_SX_LDO_XOSC_LEVEL_HI 17
++#define RG_SX_LDO_XOSC_LEVEL_SZ 3
++#define RG_DP_LDO_LEVEL_MSK 0x001c0000
++#define RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
++#define RG_DP_LDO_LEVEL_SFT 18
++#define RG_DP_LDO_LEVEL_HI 20
++#define RG_DP_LDO_LEVEL_SZ 3
++#define RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
++#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
++#define RG_SX_LDO_VCO_LEVEL_SFT 21
++#define RG_SX_LDO_VCO_LEVEL_HI 23
++#define RG_SX_LDO_VCO_LEVEL_SZ 3
++#define RG_TX_LDO_TX_LEVEL_MSK 0x07000000
++#define RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
++#define RG_TX_LDO_TX_LEVEL_SFT 24
++#define RG_TX_LDO_TX_LEVEL_HI 26
++#define RG_TX_LDO_TX_LEVEL_SZ 3
++#define RG_EN_RX_PADSW_MSK 0x00000001
++#define RG_EN_RX_PADSW_I_MSK 0xfffffffe
++#define RG_EN_RX_PADSW_SFT 0
++#define RG_EN_RX_PADSW_HI 0
++#define RG_EN_RX_PADSW_SZ 1
++#define RG_EN_RX_TESTNODE_MSK 0x00000002
++#define RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
++#define RG_EN_RX_TESTNODE_SFT 1
++#define RG_EN_RX_TESTNODE_HI 1
++#define RG_EN_RX_TESTNODE_SZ 1
++#define RG_RX_ABBCFIX_MSK 0x00000004
++#define RG_RX_ABBCFIX_I_MSK 0xfffffffb
++#define RG_RX_ABBCFIX_SFT 2
++#define RG_RX_ABBCFIX_HI 2
++#define RG_RX_ABBCFIX_SZ 1
++#define RG_RX_ABBCTUNE_MSK 0x000001f8
++#define RG_RX_ABBCTUNE_I_MSK 0xfffffe07
++#define RG_RX_ABBCTUNE_SFT 3
++#define RG_RX_ABBCTUNE_HI 8
++#define RG_RX_ABBCTUNE_SZ 6
++#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
++#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
++#define RG_RX_ABBOUT_TRI_STATE_SFT 9
++#define RG_RX_ABBOUT_TRI_STATE_HI 9
++#define RG_RX_ABBOUT_TRI_STATE_SZ 1
++#define RG_RX_ABB_N_MODE_MSK 0x00000400
++#define RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
++#define RG_RX_ABB_N_MODE_SFT 10
++#define RG_RX_ABB_N_MODE_HI 10
++#define RG_RX_ABB_N_MODE_SZ 1
++#define RG_RX_EN_LOOPA_MSK 0x00000800
++#define RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
++#define RG_RX_EN_LOOPA_SFT 11
++#define RG_RX_EN_LOOPA_HI 11
++#define RG_RX_EN_LOOPA_SZ 1
++#define RG_RX_FILTERI1ST_MSK 0x00003000
++#define RG_RX_FILTERI1ST_I_MSK 0xffffcfff
++#define RG_RX_FILTERI1ST_SFT 12
++#define RG_RX_FILTERI1ST_HI 13
++#define RG_RX_FILTERI1ST_SZ 2
++#define RG_RX_FILTERI2ND_MSK 0x0000c000
++#define RG_RX_FILTERI2ND_I_MSK 0xffff3fff
++#define RG_RX_FILTERI2ND_SFT 14
++#define RG_RX_FILTERI2ND_HI 15
++#define RG_RX_FILTERI2ND_SZ 2
++#define RG_RX_FILTERI3RD_MSK 0x00030000
++#define RG_RX_FILTERI3RD_I_MSK 0xfffcffff
++#define RG_RX_FILTERI3RD_SFT 16
++#define RG_RX_FILTERI3RD_HI 17
++#define RG_RX_FILTERI3RD_SZ 2
++#define RG_RX_FILTERI_COURSE_MSK 0x000c0000
++#define RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
++#define RG_RX_FILTERI_COURSE_SFT 18
++#define RG_RX_FILTERI_COURSE_HI 19
++#define RG_RX_FILTERI_COURSE_SZ 2
++#define RG_RX_FILTERVCM_MSK 0x00300000
++#define RG_RX_FILTERVCM_I_MSK 0xffcfffff
++#define RG_RX_FILTERVCM_SFT 20
++#define RG_RX_FILTERVCM_HI 21
++#define RG_RX_FILTERVCM_SZ 2
++#define RG_RX_HPF3M_MSK 0x00400000
++#define RG_RX_HPF3M_I_MSK 0xffbfffff
++#define RG_RX_HPF3M_SFT 22
++#define RG_RX_HPF3M_HI 22
++#define RG_RX_HPF3M_SZ 1
++#define RG_RX_HPF300K_MSK 0x00800000
++#define RG_RX_HPF300K_I_MSK 0xff7fffff
++#define RG_RX_HPF300K_SFT 23
++#define RG_RX_HPF300K_HI 23
++#define RG_RX_HPF300K_SZ 1
++#define RG_RX_HPFI_MSK 0x03000000
++#define RG_RX_HPFI_I_MSK 0xfcffffff
++#define RG_RX_HPFI_SFT 24
++#define RG_RX_HPFI_HI 25
++#define RG_RX_HPFI_SZ 2
++#define RG_RX_HPF_FINALCORNER_MSK 0x0c000000
++#define RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
++#define RG_RX_HPF_FINALCORNER_SFT 26
++#define RG_RX_HPF_FINALCORNER_HI 27
++#define RG_RX_HPF_FINALCORNER_SZ 2
++#define RG_RX_HPF_SETTLE1_C_MSK 0x30000000
++#define RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
++#define RG_RX_HPF_SETTLE1_C_SFT 28
++#define RG_RX_HPF_SETTLE1_C_HI 29
++#define RG_RX_HPF_SETTLE1_C_SZ 2
++#define RG_RX_HPF_SETTLE1_R_MSK 0x00000003
++#define RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
++#define RG_RX_HPF_SETTLE1_R_SFT 0
++#define RG_RX_HPF_SETTLE1_R_HI 1
++#define RG_RX_HPF_SETTLE1_R_SZ 2
++#define RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
++#define RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
++#define RG_RX_HPF_SETTLE2_C_SFT 2
++#define RG_RX_HPF_SETTLE2_C_HI 3
++#define RG_RX_HPF_SETTLE2_C_SZ 2
++#define RG_RX_HPF_SETTLE2_R_MSK 0x00000030
++#define RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
++#define RG_RX_HPF_SETTLE2_R_SFT 4
++#define RG_RX_HPF_SETTLE2_R_HI 5
++#define RG_RX_HPF_SETTLE2_R_SZ 2
++#define RG_RX_HPF_VCMCON2_MSK 0x000000c0
++#define RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
++#define RG_RX_HPF_VCMCON2_SFT 6
++#define RG_RX_HPF_VCMCON2_HI 7
++#define RG_RX_HPF_VCMCON2_SZ 2
++#define RG_RX_HPF_VCMCON_MSK 0x00000300
++#define RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
++#define RG_RX_HPF_VCMCON_SFT 8
++#define RG_RX_HPF_VCMCON_HI 9
++#define RG_RX_HPF_VCMCON_SZ 2
++#define RG_RX_OUTVCM_MSK 0x00000c00
++#define RG_RX_OUTVCM_I_MSK 0xfffff3ff
++#define RG_RX_OUTVCM_SFT 10
++#define RG_RX_OUTVCM_HI 11
++#define RG_RX_OUTVCM_SZ 2
++#define RG_RX_TZI_MSK 0x00003000
++#define RG_RX_TZI_I_MSK 0xffffcfff
++#define RG_RX_TZI_SFT 12
++#define RG_RX_TZI_HI 13
++#define RG_RX_TZI_SZ 2
++#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
++#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
++#define RG_RX_TZ_OUT_TRISTATE_SFT 14
++#define RG_RX_TZ_OUT_TRISTATE_HI 14
++#define RG_RX_TZ_OUT_TRISTATE_SZ 1
++#define RG_RX_TZ_VCM_MSK 0x00018000
++#define RG_RX_TZ_VCM_I_MSK 0xfffe7fff
++#define RG_RX_TZ_VCM_SFT 15
++#define RG_RX_TZ_VCM_HI 16
++#define RG_RX_TZ_VCM_SZ 2
++#define RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
++#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
++#define RG_EN_RX_RSSI_TESTNODE_SFT 17
++#define RG_EN_RX_RSSI_TESTNODE_HI 19
++#define RG_EN_RX_RSSI_TESTNODE_SZ 3
++#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
++#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
++#define RG_RX_ADCRSSI_CLKSEL_SFT 20
++#define RG_RX_ADCRSSI_CLKSEL_HI 20
++#define RG_RX_ADCRSSI_CLKSEL_SZ 1
++#define RG_RX_ADCRSSI_VCM_MSK 0x00600000
++#define RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
++#define RG_RX_ADCRSSI_VCM_SFT 21
++#define RG_RX_ADCRSSI_VCM_HI 22
++#define RG_RX_ADCRSSI_VCM_SZ 2
++#define RG_RX_REC_LPFCORNER_MSK 0x01800000
++#define RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
++#define RG_RX_REC_LPFCORNER_SFT 23
++#define RG_RX_REC_LPFCORNER_HI 24
++#define RG_RX_REC_LPFCORNER_SZ 2
++#define RG_RSSI_CLOCK_GATING_MSK 0x02000000
++#define RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
++#define RG_RSSI_CLOCK_GATING_SFT 25
++#define RG_RSSI_CLOCK_GATING_HI 25
++#define RG_RSSI_CLOCK_GATING_SZ 1
++#define RG_TXPGA_CAPSW_MSK 0x00000003
++#define RG_TXPGA_CAPSW_I_MSK 0xfffffffc
++#define RG_TXPGA_CAPSW_SFT 0
++#define RG_TXPGA_CAPSW_HI 1
++#define RG_TXPGA_CAPSW_SZ 2
++#define RG_TXPGA_MAIN_MSK 0x000000fc
++#define RG_TXPGA_MAIN_I_MSK 0xffffff03
++#define RG_TXPGA_MAIN_SFT 2
++#define RG_TXPGA_MAIN_HI 7
++#define RG_TXPGA_MAIN_SZ 6
++#define RG_TXPGA_STEER_MSK 0x00003f00
++#define RG_TXPGA_STEER_I_MSK 0xffffc0ff
++#define RG_TXPGA_STEER_SFT 8
++#define RG_TXPGA_STEER_HI 13
++#define RG_TXPGA_STEER_SZ 6
++#define RG_TXMOD_GMCELL_MSK 0x0000c000
++#define RG_TXMOD_GMCELL_I_MSK 0xffff3fff
++#define RG_TXMOD_GMCELL_SFT 14
++#define RG_TXMOD_GMCELL_HI 15
++#define RG_TXMOD_GMCELL_SZ 2
++#define RG_TXLPF_GMCELL_MSK 0x00030000
++#define RG_TXLPF_GMCELL_I_MSK 0xfffcffff
++#define RG_TXLPF_GMCELL_SFT 16
++#define RG_TXLPF_GMCELL_HI 17
++#define RG_TXLPF_GMCELL_SZ 2
++#define RG_PACELL_EN_MSK 0x001c0000
++#define RG_PACELL_EN_I_MSK 0xffe3ffff
++#define RG_PACELL_EN_SFT 18
++#define RG_PACELL_EN_HI 20
++#define RG_PACELL_EN_SZ 3
++#define RG_PABIAS_CTRL_MSK 0x01e00000
++#define RG_PABIAS_CTRL_I_MSK 0xfe1fffff
++#define RG_PABIAS_CTRL_SFT 21
++#define RG_PABIAS_CTRL_HI 24
++#define RG_PABIAS_CTRL_SZ 4
++#define RG_TX_DIV_VSET_MSK 0x0c000000
++#define RG_TX_DIV_VSET_I_MSK 0xf3ffffff
++#define RG_TX_DIV_VSET_SFT 26
++#define RG_TX_DIV_VSET_HI 27
++#define RG_TX_DIV_VSET_SZ 2
++#define RG_TX_LOBUF_VSET_MSK 0x30000000
++#define RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
++#define RG_TX_LOBUF_VSET_SFT 28
++#define RG_TX_LOBUF_VSET_HI 29
++#define RG_TX_LOBUF_VSET_SZ 2
++#define RG_RX_SQDC_MSK 0x00000007
++#define RG_RX_SQDC_I_MSK 0xfffffff8
++#define RG_RX_SQDC_SFT 0
++#define RG_RX_SQDC_HI 2
++#define RG_RX_SQDC_SZ 3
++#define RG_RX_DIV2_CORE_MSK 0x00000018
++#define RG_RX_DIV2_CORE_I_MSK 0xffffffe7
++#define RG_RX_DIV2_CORE_SFT 3
++#define RG_RX_DIV2_CORE_HI 4
++#define RG_RX_DIV2_CORE_SZ 2
++#define RG_RX_LOBUF_MSK 0x00000060
++#define RG_RX_LOBUF_I_MSK 0xffffff9f
++#define RG_RX_LOBUF_SFT 5
++#define RG_RX_LOBUF_HI 6
++#define RG_RX_LOBUF_SZ 2
++#define RG_TX_DPDGM_BIAS_MSK 0x00000780
++#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
++#define RG_TX_DPDGM_BIAS_SFT 7
++#define RG_TX_DPDGM_BIAS_HI 10
++#define RG_TX_DPDGM_BIAS_SZ 4
++#define RG_TX_DPD_DIV_MSK 0x00007800
++#define RG_TX_DPD_DIV_I_MSK 0xffff87ff
++#define RG_TX_DPD_DIV_SFT 11
++#define RG_TX_DPD_DIV_HI 14
++#define RG_TX_DPD_DIV_SZ 4
++#define RG_TX_TSSI_BIAS_MSK 0x00038000
++#define RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
++#define RG_TX_TSSI_BIAS_SFT 15
++#define RG_TX_TSSI_BIAS_HI 17
++#define RG_TX_TSSI_BIAS_SZ 3
++#define RG_TX_TSSI_DIV_MSK 0x001c0000
++#define RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
++#define RG_TX_TSSI_DIV_SFT 18
++#define RG_TX_TSSI_DIV_HI 20
++#define RG_TX_TSSI_DIV_SZ 3
++#define RG_TX_TSSI_TESTMODE_MSK 0x00200000
++#define RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
++#define RG_TX_TSSI_TESTMODE_SFT 21
++#define RG_TX_TSSI_TESTMODE_HI 21
++#define RG_TX_TSSI_TESTMODE_SZ 1
++#define RG_TX_TSSI_TEST_MSK 0x00c00000
++#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff
++#define RG_TX_TSSI_TEST_SFT 22
++#define RG_TX_TSSI_TEST_HI 23
++#define RG_TX_TSSI_TEST_SZ 2
++#define RG_PACASCODE_CTRL_MSK 0x07000000
++#define RG_PACASCODE_CTRL_I_MSK 0xf8ffffff
++#define RG_PACASCODE_CTRL_SFT 24
++#define RG_PACASCODE_CTRL_HI 26
++#define RG_PACASCODE_CTRL_SZ 3
++#define RG_RX_HG_LNA_GC_MSK 0x00000003
++#define RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_HG_LNA_GC_SFT 0
++#define RG_RX_HG_LNA_GC_HI 1
++#define RG_RX_HG_LNA_GC_SZ 2
++#define RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_HG_LNAHGN_BIAS_SFT 2
++#define RG_RX_HG_LNAHGN_BIAS_HI 5
++#define RG_RX_HG_LNAHGN_BIAS_SZ 4
++#define RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_HG_LNAHGP_BIAS_SFT 6
++#define RG_RX_HG_LNAHGP_BIAS_HI 9
++#define RG_RX_HG_LNAHGP_BIAS_SZ 4
++#define RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_HG_LNALG_BIAS_SFT 10
++#define RG_RX_HG_LNALG_BIAS_HI 13
++#define RG_RX_HG_LNALG_BIAS_SZ 4
++#define RG_RX_HG_TZ_GC_MSK 0x0000c000
++#define RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_HG_TZ_GC_SFT 14
++#define RG_RX_HG_TZ_GC_HI 15
++#define RG_RX_HG_TZ_GC_SZ 2
++#define RG_RX_HG_TZ_CAP_MSK 0x00070000
++#define RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_HG_TZ_CAP_SFT 16
++#define RG_RX_HG_TZ_CAP_HI 18
++#define RG_RX_HG_TZ_CAP_SZ 3
++#define RG_RX_MG_LNA_GC_MSK 0x00000003
++#define RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_MG_LNA_GC_SFT 0
++#define RG_RX_MG_LNA_GC_HI 1
++#define RG_RX_MG_LNA_GC_SZ 2
++#define RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_MG_LNAHGN_BIAS_SFT 2
++#define RG_RX_MG_LNAHGN_BIAS_HI 5
++#define RG_RX_MG_LNAHGN_BIAS_SZ 4
++#define RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_MG_LNAHGP_BIAS_SFT 6
++#define RG_RX_MG_LNAHGP_BIAS_HI 9
++#define RG_RX_MG_LNAHGP_BIAS_SZ 4
++#define RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_MG_LNALG_BIAS_SFT 10
++#define RG_RX_MG_LNALG_BIAS_HI 13
++#define RG_RX_MG_LNALG_BIAS_SZ 4
++#define RG_RX_MG_TZ_GC_MSK 0x0000c000
++#define RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_MG_TZ_GC_SFT 14
++#define RG_RX_MG_TZ_GC_HI 15
++#define RG_RX_MG_TZ_GC_SZ 2
++#define RG_RX_MG_TZ_CAP_MSK 0x00070000
++#define RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_MG_TZ_CAP_SFT 16
++#define RG_RX_MG_TZ_CAP_HI 18
++#define RG_RX_MG_TZ_CAP_SZ 3
++#define RG_RX_LG_LNA_GC_MSK 0x00000003
++#define RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_LG_LNA_GC_SFT 0
++#define RG_RX_LG_LNA_GC_HI 1
++#define RG_RX_LG_LNA_GC_SZ 2
++#define RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_LG_LNAHGN_BIAS_SFT 2
++#define RG_RX_LG_LNAHGN_BIAS_HI 5
++#define RG_RX_LG_LNAHGN_BIAS_SZ 4
++#define RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_LG_LNAHGP_BIAS_SFT 6
++#define RG_RX_LG_LNAHGP_BIAS_HI 9
++#define RG_RX_LG_LNAHGP_BIAS_SZ 4
++#define RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_LG_LNALG_BIAS_SFT 10
++#define RG_RX_LG_LNALG_BIAS_HI 13
++#define RG_RX_LG_LNALG_BIAS_SZ 4
++#define RG_RX_LG_TZ_GC_MSK 0x0000c000
++#define RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_LG_TZ_GC_SFT 14
++#define RG_RX_LG_TZ_GC_HI 15
++#define RG_RX_LG_TZ_GC_SZ 2
++#define RG_RX_LG_TZ_CAP_MSK 0x00070000
++#define RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_LG_TZ_CAP_SFT 16
++#define RG_RX_LG_TZ_CAP_HI 18
++#define RG_RX_LG_TZ_CAP_SZ 3
++#define RG_RX_ULG_LNA_GC_MSK 0x00000003
++#define RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_ULG_LNA_GC_SFT 0
++#define RG_RX_ULG_LNA_GC_HI 1
++#define RG_RX_ULG_LNA_GC_SZ 2
++#define RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_ULG_LNAHGN_BIAS_SFT 2
++#define RG_RX_ULG_LNAHGN_BIAS_HI 5
++#define RG_RX_ULG_LNAHGN_BIAS_SZ 4
++#define RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_ULG_LNAHGP_BIAS_SFT 6
++#define RG_RX_ULG_LNAHGP_BIAS_HI 9
++#define RG_RX_ULG_LNAHGP_BIAS_SZ 4
++#define RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_ULG_LNALG_BIAS_SFT 10
++#define RG_RX_ULG_LNALG_BIAS_HI 13
++#define RG_RX_ULG_LNALG_BIAS_SZ 4
++#define RG_RX_ULG_TZ_GC_MSK 0x0000c000
++#define RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_ULG_TZ_GC_SFT 14
++#define RG_RX_ULG_TZ_GC_HI 15
++#define RG_RX_ULG_TZ_GC_SZ 2
++#define RG_RX_ULG_TZ_CAP_MSK 0x00070000
++#define RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_ULG_TZ_CAP_SFT 16
++#define RG_RX_ULG_TZ_CAP_HI 18
++#define RG_RX_ULG_TZ_CAP_SZ 3
++#define RG_HPF1_FAST_SET_X_MSK 0x00000001
++#define RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
++#define RG_HPF1_FAST_SET_X_SFT 0
++#define RG_HPF1_FAST_SET_X_HI 0
++#define RG_HPF1_FAST_SET_X_SZ 1
++#define RG_HPF1_FAST_SET_Y_MSK 0x00000002
++#define RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
++#define RG_HPF1_FAST_SET_Y_SFT 1
++#define RG_HPF1_FAST_SET_Y_HI 1
++#define RG_HPF1_FAST_SET_Y_SZ 1
++#define RG_HPF1_FAST_SET_Z_MSK 0x00000004
++#define RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
++#define RG_HPF1_FAST_SET_Z_SFT 2
++#define RG_HPF1_FAST_SET_Z_HI 2
++#define RG_HPF1_FAST_SET_Z_SZ 1
++#define RG_HPF_T1A_MSK 0x00000018
++#define RG_HPF_T1A_I_MSK 0xffffffe7
++#define RG_HPF_T1A_SFT 3
++#define RG_HPF_T1A_HI 4
++#define RG_HPF_T1A_SZ 2
++#define RG_HPF_T1B_MSK 0x00000060
++#define RG_HPF_T1B_I_MSK 0xffffff9f
++#define RG_HPF_T1B_SFT 5
++#define RG_HPF_T1B_HI 6
++#define RG_HPF_T1B_SZ 2
++#define RG_HPF_T1C_MSK 0x00000180
++#define RG_HPF_T1C_I_MSK 0xfffffe7f
++#define RG_HPF_T1C_SFT 7
++#define RG_HPF_T1C_HI 8
++#define RG_HPF_T1C_SZ 2
++#define RG_RX_LNA_TRI_SEL_MSK 0x00000600
++#define RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
++#define RG_RX_LNA_TRI_SEL_SFT 9
++#define RG_RX_LNA_TRI_SEL_HI 10
++#define RG_RX_LNA_TRI_SEL_SZ 2
++#define RG_RX_LNA_SETTLE_MSK 0x00001800
++#define RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
++#define RG_RX_LNA_SETTLE_SFT 11
++#define RG_RX_LNA_SETTLE_HI 12
++#define RG_RX_LNA_SETTLE_SZ 2
++#define RG_TXGAIN_PHYCTRL_MSK 0x00002000
++#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffdfff
++#define RG_TXGAIN_PHYCTRL_SFT 13
++#define RG_TXGAIN_PHYCTRL_HI 13
++#define RG_TXGAIN_PHYCTRL_SZ 1
++#define RG_TX_GAIN_MSK 0x003fc000
++#define RG_TX_GAIN_I_MSK 0xffc03fff
++#define RG_TX_GAIN_SFT 14
++#define RG_TX_GAIN_HI 21
++#define RG_TX_GAIN_SZ 8
++#define RG_TXGAIN_MANUAL_MSK 0x00400000
++#define RG_TXGAIN_MANUAL_I_MSK 0xffbfffff
++#define RG_TXGAIN_MANUAL_SFT 22
++#define RG_TXGAIN_MANUAL_HI 22
++#define RG_TXGAIN_MANUAL_SZ 1
++#define RG_TX_GAIN_OFFSET_MSK 0x07800000
++#define RG_TX_GAIN_OFFSET_I_MSK 0xf87fffff
++#define RG_TX_GAIN_OFFSET_SFT 23
++#define RG_TX_GAIN_OFFSET_HI 26
++#define RG_TX_GAIN_OFFSET_SZ 4
++#define RG_ADC_CLKSEL_MSK 0x00000001
++#define RG_ADC_CLKSEL_I_MSK 0xfffffffe
++#define RG_ADC_CLKSEL_SFT 0
++#define RG_ADC_CLKSEL_HI 0
++#define RG_ADC_CLKSEL_SZ 1
++#define RG_ADC_DIBIAS_MSK 0x00000006
++#define RG_ADC_DIBIAS_I_MSK 0xfffffff9
++#define RG_ADC_DIBIAS_SFT 1
++#define RG_ADC_DIBIAS_HI 2
++#define RG_ADC_DIBIAS_SZ 2
++#define RG_ADC_DIVR_MSK 0x00000008
++#define RG_ADC_DIVR_I_MSK 0xfffffff7
++#define RG_ADC_DIVR_SFT 3
++#define RG_ADC_DIVR_HI 3
++#define RG_ADC_DIVR_SZ 1
++#define RG_ADC_DVCMI_MSK 0x00000030
++#define RG_ADC_DVCMI_I_MSK 0xffffffcf
++#define RG_ADC_DVCMI_SFT 4
++#define RG_ADC_DVCMI_HI 5
++#define RG_ADC_DVCMI_SZ 2
++#define RG_ADC_SAMSEL_MSK 0x000003c0
++#define RG_ADC_SAMSEL_I_MSK 0xfffffc3f
++#define RG_ADC_SAMSEL_SFT 6
++#define RG_ADC_SAMSEL_HI 9
++#define RG_ADC_SAMSEL_SZ 4
++#define RG_ADC_STNBY_MSK 0x00000400
++#define RG_ADC_STNBY_I_MSK 0xfffffbff
++#define RG_ADC_STNBY_SFT 10
++#define RG_ADC_STNBY_HI 10
++#define RG_ADC_STNBY_SZ 1
++#define RG_ADC_TESTMODE_MSK 0x00000800
++#define RG_ADC_TESTMODE_I_MSK 0xfffff7ff
++#define RG_ADC_TESTMODE_SFT 11
++#define RG_ADC_TESTMODE_HI 11
++#define RG_ADC_TESTMODE_SZ 1
++#define RG_ADC_TSEL_MSK 0x0000f000
++#define RG_ADC_TSEL_I_MSK 0xffff0fff
++#define RG_ADC_TSEL_SFT 12
++#define RG_ADC_TSEL_HI 15
++#define RG_ADC_TSEL_SZ 4
++#define RG_ADC_VRSEL_MSK 0x00030000
++#define RG_ADC_VRSEL_I_MSK 0xfffcffff
++#define RG_ADC_VRSEL_SFT 16
++#define RG_ADC_VRSEL_HI 17
++#define RG_ADC_VRSEL_SZ 2
++#define RG_DICMP_MSK 0x000c0000
++#define RG_DICMP_I_MSK 0xfff3ffff
++#define RG_DICMP_SFT 18
++#define RG_DICMP_HI 19
++#define RG_DICMP_SZ 2
++#define RG_DIOP_MSK 0x00300000
++#define RG_DIOP_I_MSK 0xffcfffff
++#define RG_DIOP_SFT 20
++#define RG_DIOP_HI 21
++#define RG_DIOP_SZ 2
++#define RG_SARADC_VRSEL_MSK 0x00c00000
++#define RG_SARADC_VRSEL_I_MSK 0xff3fffff
++#define RG_SARADC_VRSEL_SFT 22
++#define RG_SARADC_VRSEL_HI 23
++#define RG_SARADC_VRSEL_SZ 2
++#define RG_EN_SAR_TEST_MSK 0x03000000
++#define RG_EN_SAR_TEST_I_MSK 0xfcffffff
++#define RG_EN_SAR_TEST_SFT 24
++#define RG_EN_SAR_TEST_HI 25
++#define RG_EN_SAR_TEST_SZ 2
++#define RG_SARADC_THERMAL_MSK 0x04000000
++#define RG_SARADC_THERMAL_I_MSK 0xfbffffff
++#define RG_SARADC_THERMAL_SFT 26
++#define RG_SARADC_THERMAL_HI 26
++#define RG_SARADC_THERMAL_SZ 1
++#define RG_SARADC_TSSI_MSK 0x08000000
++#define RG_SARADC_TSSI_I_MSK 0xf7ffffff
++#define RG_SARADC_TSSI_SFT 27
++#define RG_SARADC_TSSI_HI 27
++#define RG_SARADC_TSSI_SZ 1
++#define RG_CLK_SAR_SEL_MSK 0x30000000
++#define RG_CLK_SAR_SEL_I_MSK 0xcfffffff
++#define RG_CLK_SAR_SEL_SFT 28
++#define RG_CLK_SAR_SEL_HI 29
++#define RG_CLK_SAR_SEL_SZ 2
++#define RG_EN_SARADC_MSK 0x40000000
++#define RG_EN_SARADC_I_MSK 0xbfffffff
++#define RG_EN_SARADC_SFT 30
++#define RG_EN_SARADC_HI 30
++#define RG_EN_SARADC_SZ 1
++#define RG_DACI1ST_MSK 0x00000003
++#define RG_DACI1ST_I_MSK 0xfffffffc
++#define RG_DACI1ST_SFT 0
++#define RG_DACI1ST_HI 1
++#define RG_DACI1ST_SZ 2
++#define RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
++#define RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
++#define RG_TX_DACLPF_ICOURSE_SFT 2
++#define RG_TX_DACLPF_ICOURSE_HI 3
++#define RG_TX_DACLPF_ICOURSE_SZ 2
++#define RG_TX_DACLPF_IFINE_MSK 0x00000030
++#define RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
++#define RG_TX_DACLPF_IFINE_SFT 4
++#define RG_TX_DACLPF_IFINE_HI 5
++#define RG_TX_DACLPF_IFINE_SZ 2
++#define RG_TX_DACLPF_VCM_MSK 0x000000c0
++#define RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
++#define RG_TX_DACLPF_VCM_SFT 6
++#define RG_TX_DACLPF_VCM_HI 7
++#define RG_TX_DACLPF_VCM_SZ 2
++#define RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
++#define RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
++#define RG_TX_DAC_CKEDGE_SEL_SFT 8
++#define RG_TX_DAC_CKEDGE_SEL_HI 8
++#define RG_TX_DAC_CKEDGE_SEL_SZ 1
++#define RG_TX_DAC_IBIAS_MSK 0x00000600
++#define RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
++#define RG_TX_DAC_IBIAS_SFT 9
++#define RG_TX_DAC_IBIAS_HI 10
++#define RG_TX_DAC_IBIAS_SZ 2
++#define RG_TX_DAC_OS_MSK 0x00003800
++#define RG_TX_DAC_OS_I_MSK 0xffffc7ff
++#define RG_TX_DAC_OS_SFT 11
++#define RG_TX_DAC_OS_HI 13
++#define RG_TX_DAC_OS_SZ 3
++#define RG_TX_DAC_RCAL_MSK 0x0000c000
++#define RG_TX_DAC_RCAL_I_MSK 0xffff3fff
++#define RG_TX_DAC_RCAL_SFT 14
++#define RG_TX_DAC_RCAL_HI 15
++#define RG_TX_DAC_RCAL_SZ 2
++#define RG_TX_DAC_TSEL_MSK 0x000f0000
++#define RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
++#define RG_TX_DAC_TSEL_SFT 16
++#define RG_TX_DAC_TSEL_HI 19
++#define RG_TX_DAC_TSEL_SZ 4
++#define RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
++#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
++#define RG_TX_EN_VOLTAGE_IN_SFT 20
++#define RG_TX_EN_VOLTAGE_IN_HI 20
++#define RG_TX_EN_VOLTAGE_IN_SZ 1
++#define RG_TXLPF_BYPASS_MSK 0x00200000
++#define RG_TXLPF_BYPASS_I_MSK 0xffdfffff
++#define RG_TXLPF_BYPASS_SFT 21
++#define RG_TXLPF_BYPASS_HI 21
++#define RG_TXLPF_BYPASS_SZ 1
++#define RG_TXLPF_BOOSTI_MSK 0x00400000
++#define RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
++#define RG_TXLPF_BOOSTI_SFT 22
++#define RG_TXLPF_BOOSTI_HI 22
++#define RG_TXLPF_BOOSTI_SZ 1
++#define RG_TX_DAC_IOFFSET_MSK 0x07800000
++#define RG_TX_DAC_IOFFSET_I_MSK 0xf87fffff
++#define RG_TX_DAC_IOFFSET_SFT 23
++#define RG_TX_DAC_IOFFSET_HI 26
++#define RG_TX_DAC_IOFFSET_SZ 4
++#define RG_TX_DAC_QOFFSET_MSK 0x78000000
++#define RG_TX_DAC_QOFFSET_I_MSK 0x87ffffff
++#define RG_TX_DAC_QOFFSET_SFT 27
++#define RG_TX_DAC_QOFFSET_HI 30
++#define RG_TX_DAC_QOFFSET_SZ 4
++#define RG_EN_SX_R3_MSK 0x00000001
++#define RG_EN_SX_R3_I_MSK 0xfffffffe
++#define RG_EN_SX_R3_SFT 0
++#define RG_EN_SX_R3_HI 0
++#define RG_EN_SX_R3_SZ 1
++#define RG_EN_SX_CH_MSK 0x00000002
++#define RG_EN_SX_CH_I_MSK 0xfffffffd
++#define RG_EN_SX_CH_SFT 1
++#define RG_EN_SX_CH_HI 1
++#define RG_EN_SX_CH_SZ 1
++#define RG_EN_SX_CHP_MSK 0x00000004
++#define RG_EN_SX_CHP_I_MSK 0xfffffffb
++#define RG_EN_SX_CHP_SFT 2
++#define RG_EN_SX_CHP_HI 2
++#define RG_EN_SX_CHP_SZ 1
++#define RG_EN_SX_DIVCK_MSK 0x00000008
++#define RG_EN_SX_DIVCK_I_MSK 0xfffffff7
++#define RG_EN_SX_DIVCK_SFT 3
++#define RG_EN_SX_DIVCK_HI 3
++#define RG_EN_SX_DIVCK_SZ 1
++#define RG_EN_SX_VCOBF_MSK 0x00000010
++#define RG_EN_SX_VCOBF_I_MSK 0xffffffef
++#define RG_EN_SX_VCOBF_SFT 4
++#define RG_EN_SX_VCOBF_HI 4
++#define RG_EN_SX_VCOBF_SZ 1
++#define RG_EN_SX_VCO_MSK 0x00000020
++#define RG_EN_SX_VCO_I_MSK 0xffffffdf
++#define RG_EN_SX_VCO_SFT 5
++#define RG_EN_SX_VCO_HI 5
++#define RG_EN_SX_VCO_SZ 1
++#define RG_EN_SX_MOD_MSK 0x00000040
++#define RG_EN_SX_MOD_I_MSK 0xffffffbf
++#define RG_EN_SX_MOD_SFT 6
++#define RG_EN_SX_MOD_HI 6
++#define RG_EN_SX_MOD_SZ 1
++#define RG_EN_SX_DITHER_MSK 0x00000100
++#define RG_EN_SX_DITHER_I_MSK 0xfffffeff
++#define RG_EN_SX_DITHER_SFT 8
++#define RG_EN_SX_DITHER_HI 8
++#define RG_EN_SX_DITHER_SZ 1
++#define RG_EN_SX_VT_MON_MSK 0x00000800
++#define RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
++#define RG_EN_SX_VT_MON_SFT 11
++#define RG_EN_SX_VT_MON_HI 11
++#define RG_EN_SX_VT_MON_SZ 1
++#define RG_EN_SX_VT_MON_DG_MSK 0x00001000
++#define RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
++#define RG_EN_SX_VT_MON_DG_SFT 12
++#define RG_EN_SX_VT_MON_DG_HI 12
++#define RG_EN_SX_VT_MON_DG_SZ 1
++#define RG_EN_SX_DIV_MSK 0x00002000
++#define RG_EN_SX_DIV_I_MSK 0xffffdfff
++#define RG_EN_SX_DIV_SFT 13
++#define RG_EN_SX_DIV_HI 13
++#define RG_EN_SX_DIV_SZ 1
++#define RG_EN_SX_LPF_MSK 0x00004000
++#define RG_EN_SX_LPF_I_MSK 0xffffbfff
++#define RG_EN_SX_LPF_SFT 14
++#define RG_EN_SX_LPF_HI 14
++#define RG_EN_SX_LPF_SZ 1
++#define RG_EN_DPL_MOD_MSK 0x00008000
++#define RG_EN_DPL_MOD_I_MSK 0xffff7fff
++#define RG_EN_DPL_MOD_SFT 15
++#define RG_EN_DPL_MOD_HI 15
++#define RG_EN_DPL_MOD_SZ 1
++#define RG_DPL_MOD_ORDER_MSK 0x00030000
++#define RG_DPL_MOD_ORDER_I_MSK 0xfffcffff
++#define RG_DPL_MOD_ORDER_SFT 16
++#define RG_DPL_MOD_ORDER_HI 17
++#define RG_DPL_MOD_ORDER_SZ 2
++#define RG_SX_RFCTRL_F_MSK 0x00ffffff
++#define RG_SX_RFCTRL_F_I_MSK 0xff000000
++#define RG_SX_RFCTRL_F_SFT 0
++#define RG_SX_RFCTRL_F_HI 23
++#define RG_SX_RFCTRL_F_SZ 24
++#define RG_SX_SEL_CP_MSK 0x0f000000
++#define RG_SX_SEL_CP_I_MSK 0xf0ffffff
++#define RG_SX_SEL_CP_SFT 24
++#define RG_SX_SEL_CP_HI 27
++#define RG_SX_SEL_CP_SZ 4
++#define RG_SX_SEL_CS_MSK 0xf0000000
++#define RG_SX_SEL_CS_I_MSK 0x0fffffff
++#define RG_SX_SEL_CS_SFT 28
++#define RG_SX_SEL_CS_HI 31
++#define RG_SX_SEL_CS_SZ 4
++#define RG_SX_RFCTRL_CH_MSK 0x000007ff
++#define RG_SX_RFCTRL_CH_I_MSK 0xfffff800
++#define RG_SX_RFCTRL_CH_SFT 0
++#define RG_SX_RFCTRL_CH_HI 10
++#define RG_SX_RFCTRL_CH_SZ 11
++#define RG_SX_SEL_C3_MSK 0x00007800
++#define RG_SX_SEL_C3_I_MSK 0xffff87ff
++#define RG_SX_SEL_C3_SFT 11
++#define RG_SX_SEL_C3_HI 14
++#define RG_SX_SEL_C3_SZ 4
++#define RG_SX_SEL_RS_MSK 0x000f8000
++#define RG_SX_SEL_RS_I_MSK 0xfff07fff
++#define RG_SX_SEL_RS_SFT 15
++#define RG_SX_SEL_RS_HI 19
++#define RG_SX_SEL_RS_SZ 5
++#define RG_SX_SEL_R3_MSK 0x01f00000
++#define RG_SX_SEL_R3_I_MSK 0xfe0fffff
++#define RG_SX_SEL_R3_SFT 20
++#define RG_SX_SEL_R3_HI 24
++#define RG_SX_SEL_R3_SZ 5
++#define RG_SX_SEL_ICHP_MSK 0x0000001f
++#define RG_SX_SEL_ICHP_I_MSK 0xffffffe0
++#define RG_SX_SEL_ICHP_SFT 0
++#define RG_SX_SEL_ICHP_HI 4
++#define RG_SX_SEL_ICHP_SZ 5
++#define RG_SX_SEL_PCHP_MSK 0x000003e0
++#define RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
++#define RG_SX_SEL_PCHP_SFT 5
++#define RG_SX_SEL_PCHP_HI 9
++#define RG_SX_SEL_PCHP_SZ 5
++#define RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
++#define RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
++#define RG_SX_SEL_CHP_REGOP_SFT 10
++#define RG_SX_SEL_CHP_REGOP_HI 13
++#define RG_SX_SEL_CHP_REGOP_SZ 4
++#define RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
++#define RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
++#define RG_SX_SEL_CHP_UNIOP_SFT 14
++#define RG_SX_SEL_CHP_UNIOP_HI 17
++#define RG_SX_SEL_CHP_UNIOP_SZ 4
++#define RG_SX_CHP_IOST_POL_MSK 0x00040000
++#define RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
++#define RG_SX_CHP_IOST_POL_SFT 18
++#define RG_SX_CHP_IOST_POL_HI 18
++#define RG_SX_CHP_IOST_POL_SZ 1
++#define RG_SX_CHP_IOST_MSK 0x00380000
++#define RG_SX_CHP_IOST_I_MSK 0xffc7ffff
++#define RG_SX_CHP_IOST_SFT 19
++#define RG_SX_CHP_IOST_HI 21
++#define RG_SX_CHP_IOST_SZ 3
++#define RG_SX_PFDSEL_MSK 0x00400000
++#define RG_SX_PFDSEL_I_MSK 0xffbfffff
++#define RG_SX_PFDSEL_SFT 22
++#define RG_SX_PFDSEL_HI 22
++#define RG_SX_PFDSEL_SZ 1
++#define RG_SX_PFD_SET_MSK 0x00800000
++#define RG_SX_PFD_SET_I_MSK 0xff7fffff
++#define RG_SX_PFD_SET_SFT 23
++#define RG_SX_PFD_SET_HI 23
++#define RG_SX_PFD_SET_SZ 1
++#define RG_SX_PFD_SET1_MSK 0x01000000
++#define RG_SX_PFD_SET1_I_MSK 0xfeffffff
++#define RG_SX_PFD_SET1_SFT 24
++#define RG_SX_PFD_SET1_HI 24
++#define RG_SX_PFD_SET1_SZ 1
++#define RG_SX_PFD_SET2_MSK 0x02000000
++#define RG_SX_PFD_SET2_I_MSK 0xfdffffff
++#define RG_SX_PFD_SET2_SFT 25
++#define RG_SX_PFD_SET2_HI 25
++#define RG_SX_PFD_SET2_SZ 1
++#define RG_SX_VBNCAS_SEL_MSK 0x04000000
++#define RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
++#define RG_SX_VBNCAS_SEL_SFT 26
++#define RG_SX_VBNCAS_SEL_HI 26
++#define RG_SX_VBNCAS_SEL_SZ 1
++#define RG_SX_PFD_RST_H_MSK 0x08000000
++#define RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
++#define RG_SX_PFD_RST_H_SFT 27
++#define RG_SX_PFD_RST_H_HI 27
++#define RG_SX_PFD_RST_H_SZ 1
++#define RG_SX_PFD_TRUP_MSK 0x10000000
++#define RG_SX_PFD_TRUP_I_MSK 0xefffffff
++#define RG_SX_PFD_TRUP_SFT 28
++#define RG_SX_PFD_TRUP_HI 28
++#define RG_SX_PFD_TRUP_SZ 1
++#define RG_SX_PFD_TRDN_MSK 0x20000000
++#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff
++#define RG_SX_PFD_TRDN_SFT 29
++#define RG_SX_PFD_TRDN_HI 29
++#define RG_SX_PFD_TRDN_SZ 1
++#define RG_SX_PFD_TRSEL_MSK 0x40000000
++#define RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
++#define RG_SX_PFD_TRSEL_SFT 30
++#define RG_SX_PFD_TRSEL_HI 30
++#define RG_SX_PFD_TRSEL_SZ 1
++#define RG_SX_VCOBA_R_MSK 0x00000007
++#define RG_SX_VCOBA_R_I_MSK 0xfffffff8
++#define RG_SX_VCOBA_R_SFT 0
++#define RG_SX_VCOBA_R_HI 2
++#define RG_SX_VCOBA_R_SZ 3
++#define RG_SX_VCORSEL_MSK 0x000000f8
++#define RG_SX_VCORSEL_I_MSK 0xffffff07
++#define RG_SX_VCORSEL_SFT 3
++#define RG_SX_VCORSEL_HI 7
++#define RG_SX_VCORSEL_SZ 5
++#define RG_SX_VCOCUSEL_MSK 0x00000f00
++#define RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
++#define RG_SX_VCOCUSEL_SFT 8
++#define RG_SX_VCOCUSEL_HI 11
++#define RG_SX_VCOCUSEL_SZ 4
++#define RG_SX_RXBFSEL_MSK 0x0000f000
++#define RG_SX_RXBFSEL_I_MSK 0xffff0fff
++#define RG_SX_RXBFSEL_SFT 12
++#define RG_SX_RXBFSEL_HI 15
++#define RG_SX_RXBFSEL_SZ 4
++#define RG_SX_TXBFSEL_MSK 0x000f0000
++#define RG_SX_TXBFSEL_I_MSK 0xfff0ffff
++#define RG_SX_TXBFSEL_SFT 16
++#define RG_SX_TXBFSEL_HI 19
++#define RG_SX_TXBFSEL_SZ 4
++#define RG_SX_VCOBFSEL_MSK 0x00f00000
++#define RG_SX_VCOBFSEL_I_MSK 0xff0fffff
++#define RG_SX_VCOBFSEL_SFT 20
++#define RG_SX_VCOBFSEL_HI 23
++#define RG_SX_VCOBFSEL_SZ 4
++#define RG_SX_DIVBFSEL_MSK 0x0f000000
++#define RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
++#define RG_SX_DIVBFSEL_SFT 24
++#define RG_SX_DIVBFSEL_HI 27
++#define RG_SX_DIVBFSEL_SZ 4
++#define RG_SX_GNDR_SEL_MSK 0xf0000000
++#define RG_SX_GNDR_SEL_I_MSK 0x0fffffff
++#define RG_SX_GNDR_SEL_SFT 28
++#define RG_SX_GNDR_SEL_HI 31
++#define RG_SX_GNDR_SEL_SZ 4
++#define RG_SX_DITHER_WEIGHT_MSK 0x00000003
++#define RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
++#define RG_SX_DITHER_WEIGHT_SFT 0
++#define RG_SX_DITHER_WEIGHT_HI 1
++#define RG_SX_DITHER_WEIGHT_SZ 2
++#define RG_SX_MOD_ORDER_MSK 0x00000030
++#define RG_SX_MOD_ORDER_I_MSK 0xffffffcf
++#define RG_SX_MOD_ORDER_SFT 4
++#define RG_SX_MOD_ORDER_HI 5
++#define RG_SX_MOD_ORDER_SZ 2
++#define RG_SX_RST_H_DIV_MSK 0x00000200
++#define RG_SX_RST_H_DIV_I_MSK 0xfffffdff
++#define RG_SX_RST_H_DIV_SFT 9
++#define RG_SX_RST_H_DIV_HI 9
++#define RG_SX_RST_H_DIV_SZ 1
++#define RG_SX_SDM_EDGE_MSK 0x00000400
++#define RG_SX_SDM_EDGE_I_MSK 0xfffffbff
++#define RG_SX_SDM_EDGE_SFT 10
++#define RG_SX_SDM_EDGE_HI 10
++#define RG_SX_SDM_EDGE_SZ 1
++#define RG_SX_XO_GM_MSK 0x00001800
++#define RG_SX_XO_GM_I_MSK 0xffffe7ff
++#define RG_SX_XO_GM_SFT 11
++#define RG_SX_XO_GM_HI 12
++#define RG_SX_XO_GM_SZ 2
++#define RG_SX_REFBYTWO_MSK 0x00002000
++#define RG_SX_REFBYTWO_I_MSK 0xffffdfff
++#define RG_SX_REFBYTWO_SFT 13
++#define RG_SX_REFBYTWO_HI 13
++#define RG_SX_REFBYTWO_SZ 1
++#define RG_SX_LCKEN_MSK 0x00080000
++#define RG_SX_LCKEN_I_MSK 0xfff7ffff
++#define RG_SX_LCKEN_SFT 19
++#define RG_SX_LCKEN_HI 19
++#define RG_SX_LCKEN_SZ 1
++#define RG_SX_PREVDD_MSK 0x00f00000
++#define RG_SX_PREVDD_I_MSK 0xff0fffff
++#define RG_SX_PREVDD_SFT 20
++#define RG_SX_PREVDD_HI 23
++#define RG_SX_PREVDD_SZ 4
++#define RG_SX_PSCONTERVDD_MSK 0x0f000000
++#define RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
++#define RG_SX_PSCONTERVDD_SFT 24
++#define RG_SX_PSCONTERVDD_HI 27
++#define RG_SX_PSCONTERVDD_SZ 4
++#define RG_SX_PH_MSK 0x00002000
++#define RG_SX_PH_I_MSK 0xffffdfff
++#define RG_SX_PH_SFT 13
++#define RG_SX_PH_HI 13
++#define RG_SX_PH_SZ 1
++#define RG_SX_PL_MSK 0x00004000
++#define RG_SX_PL_I_MSK 0xffffbfff
++#define RG_SX_PL_SFT 14
++#define RG_SX_PL_HI 14
++#define RG_SX_PL_SZ 1
++#define RG_XOSC_CBANK_XO_MSK 0x00078000
++#define RG_XOSC_CBANK_XO_I_MSK 0xfff87fff
++#define RG_XOSC_CBANK_XO_SFT 15
++#define RG_XOSC_CBANK_XO_HI 18
++#define RG_XOSC_CBANK_XO_SZ 4
++#define RG_XOSC_CBANK_XI_MSK 0x00780000
++#define RG_XOSC_CBANK_XI_I_MSK 0xff87ffff
++#define RG_XOSC_CBANK_XI_SFT 19
++#define RG_XOSC_CBANK_XI_HI 22
++#define RG_XOSC_CBANK_XI_SZ 4
++#define RG_SX_VT_MON_MODE_MSK 0x00000001
++#define RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
++#define RG_SX_VT_MON_MODE_SFT 0
++#define RG_SX_VT_MON_MODE_HI 0
++#define RG_SX_VT_MON_MODE_SZ 1
++#define RG_SX_VT_TH_HI_MSK 0x00000006
++#define RG_SX_VT_TH_HI_I_MSK 0xfffffff9
++#define RG_SX_VT_TH_HI_SFT 1
++#define RG_SX_VT_TH_HI_HI 2
++#define RG_SX_VT_TH_HI_SZ 2
++#define RG_SX_VT_TH_LO_MSK 0x00000018
++#define RG_SX_VT_TH_LO_I_MSK 0xffffffe7
++#define RG_SX_VT_TH_LO_SFT 3
++#define RG_SX_VT_TH_LO_HI 4
++#define RG_SX_VT_TH_LO_SZ 2
++#define RG_SX_VT_SET_MSK 0x00000020
++#define RG_SX_VT_SET_I_MSK 0xffffffdf
++#define RG_SX_VT_SET_SFT 5
++#define RG_SX_VT_SET_HI 5
++#define RG_SX_VT_SET_SZ 1
++#define RG_SX_VT_MON_TMR_MSK 0x00007fc0
++#define RG_SX_VT_MON_TMR_I_MSK 0xffff803f
++#define RG_SX_VT_MON_TMR_SFT 6
++#define RG_SX_VT_MON_TMR_HI 14
++#define RG_SX_VT_MON_TMR_SZ 9
++#define RG_EN_DP_VT_MON_MSK 0x00000001
++#define RG_EN_DP_VT_MON_I_MSK 0xfffffffe
++#define RG_EN_DP_VT_MON_SFT 0
++#define RG_EN_DP_VT_MON_HI 0
++#define RG_EN_DP_VT_MON_SZ 1
++#define RG_DP_VT_TH_HI_MSK 0x00000006
++#define RG_DP_VT_TH_HI_I_MSK 0xfffffff9
++#define RG_DP_VT_TH_HI_SFT 1
++#define RG_DP_VT_TH_HI_HI 2
++#define RG_DP_VT_TH_HI_SZ 2
++#define RG_DP_VT_TH_LO_MSK 0x00000018
++#define RG_DP_VT_TH_LO_I_MSK 0xffffffe7
++#define RG_DP_VT_TH_LO_SFT 3
++#define RG_DP_VT_TH_LO_HI 4
++#define RG_DP_VT_TH_LO_SZ 2
++#define RG_DP_CK320BY2_MSK 0x00004000
++#define RG_DP_CK320BY2_I_MSK 0xffffbfff
++#define RG_DP_CK320BY2_SFT 14
++#define RG_DP_CK320BY2_HI 14
++#define RG_DP_CK320BY2_SZ 1
++#define RG_DP_OD_TEST_MSK 0x00200000
++#define RG_DP_OD_TEST_I_MSK 0xffdfffff
++#define RG_DP_OD_TEST_SFT 21
++#define RG_DP_OD_TEST_HI 21
++#define RG_DP_OD_TEST_SZ 1
++#define RG_DP_BBPLL_BP_MSK 0x00000001
++#define RG_DP_BBPLL_BP_I_MSK 0xfffffffe
++#define RG_DP_BBPLL_BP_SFT 0
++#define RG_DP_BBPLL_BP_HI 0
++#define RG_DP_BBPLL_BP_SZ 1
++#define RG_DP_BBPLL_ICP_MSK 0x00000006
++#define RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
++#define RG_DP_BBPLL_ICP_SFT 1
++#define RG_DP_BBPLL_ICP_HI 2
++#define RG_DP_BBPLL_ICP_SZ 2
++#define RG_DP_BBPLL_IDUAL_MSK 0x00000018
++#define RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
++#define RG_DP_BBPLL_IDUAL_SFT 3
++#define RG_DP_BBPLL_IDUAL_HI 4
++#define RG_DP_BBPLL_IDUAL_SZ 2
++#define RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
++#define RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
++#define RG_DP_BBPLL_OD_TEST_SFT 5
++#define RG_DP_BBPLL_OD_TEST_HI 8
++#define RG_DP_BBPLL_OD_TEST_SZ 4
++#define RG_DP_BBPLL_PD_MSK 0x00000200
++#define RG_DP_BBPLL_PD_I_MSK 0xfffffdff
++#define RG_DP_BBPLL_PD_SFT 9
++#define RG_DP_BBPLL_PD_HI 9
++#define RG_DP_BBPLL_PD_SZ 1
++#define RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
++#define RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
++#define RG_DP_BBPLL_TESTSEL_SFT 10
++#define RG_DP_BBPLL_TESTSEL_HI 12
++#define RG_DP_BBPLL_TESTSEL_SZ 3
++#define RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
++#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
++#define RG_DP_BBPLL_PFD_DLY_SFT 13
++#define RG_DP_BBPLL_PFD_DLY_HI 14
++#define RG_DP_BBPLL_PFD_DLY_SZ 2
++#define RG_DP_RP_MSK 0x00038000
++#define RG_DP_RP_I_MSK 0xfffc7fff
++#define RG_DP_RP_SFT 15
++#define RG_DP_RP_HI 17
++#define RG_DP_RP_SZ 3
++#define RG_DP_RHP_MSK 0x000c0000
++#define RG_DP_RHP_I_MSK 0xfff3ffff
++#define RG_DP_RHP_SFT 18
++#define RG_DP_RHP_HI 19
++#define RG_DP_RHP_SZ 2
++#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000
++#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
++#define RG_DP_BBPLL_SDM_EDGE_SFT 31
++#define RG_DP_BBPLL_SDM_EDGE_HI 31
++#define RG_DP_BBPLL_SDM_EDGE_SZ 1
++#define RG_DP_FODIV_MSK 0x0007f000
++#define RG_DP_FODIV_I_MSK 0xfff80fff
++#define RG_DP_FODIV_SFT 12
++#define RG_DP_FODIV_HI 18
++#define RG_DP_FODIV_SZ 7
++#define RG_DP_REFDIV_MSK 0x1fc00000
++#define RG_DP_REFDIV_I_MSK 0xe03fffff
++#define RG_DP_REFDIV_SFT 22
++#define RG_DP_REFDIV_HI 28
++#define RG_DP_REFDIV_SZ 7
++#define RG_IDACAI_PGAG15_MSK 0x0000003f
++#define RG_IDACAI_PGAG15_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG15_SFT 0
++#define RG_IDACAI_PGAG15_HI 5
++#define RG_IDACAI_PGAG15_SZ 6
++#define RG_IDACAQ_PGAG15_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG15_SFT 6
++#define RG_IDACAQ_PGAG15_HI 11
++#define RG_IDACAQ_PGAG15_SZ 6
++#define RG_IDACAI_PGAG14_MSK 0x0003f000
++#define RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG14_SFT 12
++#define RG_IDACAI_PGAG14_HI 17
++#define RG_IDACAI_PGAG14_SZ 6
++#define RG_IDACAQ_PGAG14_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG14_SFT 18
++#define RG_IDACAQ_PGAG14_HI 23
++#define RG_IDACAQ_PGAG14_SZ 6
++#define RG_DP_BBPLL_BS_MSK 0x3f000000
++#define RG_DP_BBPLL_BS_I_MSK 0xc0ffffff
++#define RG_DP_BBPLL_BS_SFT 24
++#define RG_DP_BBPLL_BS_HI 29
++#define RG_DP_BBPLL_BS_SZ 6
++#define RG_IDACAI_PGAG13_MSK 0x0000003f
++#define RG_IDACAI_PGAG13_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG13_SFT 0
++#define RG_IDACAI_PGAG13_HI 5
++#define RG_IDACAI_PGAG13_SZ 6
++#define RG_IDACAQ_PGAG13_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG13_SFT 6
++#define RG_IDACAQ_PGAG13_HI 11
++#define RG_IDACAQ_PGAG13_SZ 6
++#define RG_IDACAI_PGAG12_MSK 0x0003f000
++#define RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG12_SFT 12
++#define RG_IDACAI_PGAG12_HI 17
++#define RG_IDACAI_PGAG12_SZ 6
++#define RG_IDACAQ_PGAG12_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG12_SFT 18
++#define RG_IDACAQ_PGAG12_HI 23
++#define RG_IDACAQ_PGAG12_SZ 6
++#define RG_IDACAI_PGAG11_MSK 0x0000003f
++#define RG_IDACAI_PGAG11_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG11_SFT 0
++#define RG_IDACAI_PGAG11_HI 5
++#define RG_IDACAI_PGAG11_SZ 6
++#define RG_IDACAQ_PGAG11_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG11_SFT 6
++#define RG_IDACAQ_PGAG11_HI 11
++#define RG_IDACAQ_PGAG11_SZ 6
++#define RG_IDACAI_PGAG10_MSK 0x0003f000
++#define RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG10_SFT 12
++#define RG_IDACAI_PGAG10_HI 17
++#define RG_IDACAI_PGAG10_SZ 6
++#define RG_IDACAQ_PGAG10_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG10_SFT 18
++#define RG_IDACAQ_PGAG10_HI 23
++#define RG_IDACAQ_PGAG10_SZ 6
++#define RG_IDACAI_PGAG9_MSK 0x0000003f
++#define RG_IDACAI_PGAG9_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG9_SFT 0
++#define RG_IDACAI_PGAG9_HI 5
++#define RG_IDACAI_PGAG9_SZ 6
++#define RG_IDACAQ_PGAG9_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG9_SFT 6
++#define RG_IDACAQ_PGAG9_HI 11
++#define RG_IDACAQ_PGAG9_SZ 6
++#define RG_IDACAI_PGAG8_MSK 0x0003f000
++#define RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG8_SFT 12
++#define RG_IDACAI_PGAG8_HI 17
++#define RG_IDACAI_PGAG8_SZ 6
++#define RG_IDACAQ_PGAG8_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG8_SFT 18
++#define RG_IDACAQ_PGAG8_HI 23
++#define RG_IDACAQ_PGAG8_SZ 6
++#define RG_IDACAI_PGAG7_MSK 0x0000003f
++#define RG_IDACAI_PGAG7_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG7_SFT 0
++#define RG_IDACAI_PGAG7_HI 5
++#define RG_IDACAI_PGAG7_SZ 6
++#define RG_IDACAQ_PGAG7_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG7_SFT 6
++#define RG_IDACAQ_PGAG7_HI 11
++#define RG_IDACAQ_PGAG7_SZ 6
++#define RG_IDACAI_PGAG6_MSK 0x0003f000
++#define RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG6_SFT 12
++#define RG_IDACAI_PGAG6_HI 17
++#define RG_IDACAI_PGAG6_SZ 6
++#define RG_IDACAQ_PGAG6_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG6_SFT 18
++#define RG_IDACAQ_PGAG6_HI 23
++#define RG_IDACAQ_PGAG6_SZ 6
++#define RG_IDACAI_PGAG5_MSK 0x0000003f
++#define RG_IDACAI_PGAG5_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG5_SFT 0
++#define RG_IDACAI_PGAG5_HI 5
++#define RG_IDACAI_PGAG5_SZ 6
++#define RG_IDACAQ_PGAG5_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG5_SFT 6
++#define RG_IDACAQ_PGAG5_HI 11
++#define RG_IDACAQ_PGAG5_SZ 6
++#define RG_IDACAI_PGAG4_MSK 0x0003f000
++#define RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG4_SFT 12
++#define RG_IDACAI_PGAG4_HI 17
++#define RG_IDACAI_PGAG4_SZ 6
++#define RG_IDACAQ_PGAG4_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG4_SFT 18
++#define RG_IDACAQ_PGAG4_HI 23
++#define RG_IDACAQ_PGAG4_SZ 6
++#define RG_IDACAI_PGAG3_MSK 0x0000003f
++#define RG_IDACAI_PGAG3_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG3_SFT 0
++#define RG_IDACAI_PGAG3_HI 5
++#define RG_IDACAI_PGAG3_SZ 6
++#define RG_IDACAQ_PGAG3_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG3_SFT 6
++#define RG_IDACAQ_PGAG3_HI 11
++#define RG_IDACAQ_PGAG3_SZ 6
++#define RG_IDACAI_PGAG2_MSK 0x0003f000
++#define RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG2_SFT 12
++#define RG_IDACAI_PGAG2_HI 17
++#define RG_IDACAI_PGAG2_SZ 6
++#define RG_IDACAQ_PGAG2_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG2_SFT 18
++#define RG_IDACAQ_PGAG2_HI 23
++#define RG_IDACAQ_PGAG2_SZ 6
++#define RG_IDACAI_PGAG1_MSK 0x0000003f
++#define RG_IDACAI_PGAG1_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG1_SFT 0
++#define RG_IDACAI_PGAG1_HI 5
++#define RG_IDACAI_PGAG1_SZ 6
++#define RG_IDACAQ_PGAG1_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG1_SFT 6
++#define RG_IDACAQ_PGAG1_HI 11
++#define RG_IDACAQ_PGAG1_SZ 6
++#define RG_IDACAI_PGAG0_MSK 0x0003f000
++#define RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG0_SFT 12
++#define RG_IDACAI_PGAG0_HI 17
++#define RG_IDACAI_PGAG0_SZ 6
++#define RG_IDACAQ_PGAG0_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG0_SFT 18
++#define RG_IDACAQ_PGAG0_HI 23
++#define RG_IDACAQ_PGAG0_SZ 6
++#define RG_EN_RCAL_MSK 0x00000001
++#define RG_EN_RCAL_I_MSK 0xfffffffe
++#define RG_EN_RCAL_SFT 0
++#define RG_EN_RCAL_HI 0
++#define RG_EN_RCAL_SZ 1
++#define RG_RCAL_SPD_MSK 0x00000002
++#define RG_RCAL_SPD_I_MSK 0xfffffffd
++#define RG_RCAL_SPD_SFT 1
++#define RG_RCAL_SPD_HI 1
++#define RG_RCAL_SPD_SZ 1
++#define RG_RCAL_TMR_MSK 0x000001fc
++#define RG_RCAL_TMR_I_MSK 0xfffffe03
++#define RG_RCAL_TMR_SFT 2
++#define RG_RCAL_TMR_HI 8
++#define RG_RCAL_TMR_SZ 7
++#define RG_RCAL_CODE_CWR_MSK 0x00000200
++#define RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
++#define RG_RCAL_CODE_CWR_SFT 9
++#define RG_RCAL_CODE_CWR_HI 9
++#define RG_RCAL_CODE_CWR_SZ 1
++#define RG_RCAL_CODE_CWD_MSK 0x00007c00
++#define RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
++#define RG_RCAL_CODE_CWD_SFT 10
++#define RG_RCAL_CODE_CWD_HI 14
++#define RG_RCAL_CODE_CWD_SZ 5
++#define RG_SX_SUB_SEL_CWR_MSK 0x00000001
++#define RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
++#define RG_SX_SUB_SEL_CWR_SFT 0
++#define RG_SX_SUB_SEL_CWR_HI 0
++#define RG_SX_SUB_SEL_CWR_SZ 1
++#define RG_SX_SUB_SEL_CWD_MSK 0x000000fe
++#define RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
++#define RG_SX_SUB_SEL_CWD_SFT 1
++#define RG_SX_SUB_SEL_CWD_HI 7
++#define RG_SX_SUB_SEL_CWD_SZ 7
++#define RG_SX_LCK_BIN_OFFSET_MSK 0x00078000
++#define RG_SX_LCK_BIN_OFFSET_I_MSK 0xfff87fff
++#define RG_SX_LCK_BIN_OFFSET_SFT 15
++#define RG_SX_LCK_BIN_OFFSET_HI 18
++#define RG_SX_LCK_BIN_OFFSET_SZ 4
++#define RG_SX_LCK_BIN_PRECISION_MSK 0x00080000
++#define RG_SX_LCK_BIN_PRECISION_I_MSK 0xfff7ffff
++#define RG_SX_LCK_BIN_PRECISION_SFT 19
++#define RG_SX_LCK_BIN_PRECISION_HI 19
++#define RG_SX_LCK_BIN_PRECISION_SZ 1
++#define RG_SX_LOCK_EN_N_MSK 0x00100000
++#define RG_SX_LOCK_EN_N_I_MSK 0xffefffff
++#define RG_SX_LOCK_EN_N_SFT 20
++#define RG_SX_LOCK_EN_N_HI 20
++#define RG_SX_LOCK_EN_N_SZ 1
++#define RG_SX_LOCK_MANUAL_MSK 0x00200000
++#define RG_SX_LOCK_MANUAL_I_MSK 0xffdfffff
++#define RG_SX_LOCK_MANUAL_SFT 21
++#define RG_SX_LOCK_MANUAL_HI 21
++#define RG_SX_LOCK_MANUAL_SZ 1
++#define RG_SX_SUB_MANUAL_MSK 0x00400000
++#define RG_SX_SUB_MANUAL_I_MSK 0xffbfffff
++#define RG_SX_SUB_MANUAL_SFT 22
++#define RG_SX_SUB_MANUAL_HI 22
++#define RG_SX_SUB_MANUAL_SZ 1
++#define RG_SX_SUB_SEL_MSK 0x3f800000
++#define RG_SX_SUB_SEL_I_MSK 0xc07fffff
++#define RG_SX_SUB_SEL_SFT 23
++#define RG_SX_SUB_SEL_HI 29
++#define RG_SX_SUB_SEL_SZ 7
++#define RG_SX_MUX_SEL_VTH_BINL_MSK 0x40000000
++#define RG_SX_MUX_SEL_VTH_BINL_I_MSK 0xbfffffff
++#define RG_SX_MUX_SEL_VTH_BINL_SFT 30
++#define RG_SX_MUX_SEL_VTH_BINL_HI 30
++#define RG_SX_MUX_SEL_VTH_BINL_SZ 1
++#define RG_TRX_DUMMMY_MSK 0xffffffff
++#define RG_TRX_DUMMMY_I_MSK 0x00000000
++#define RG_TRX_DUMMMY_SFT 0
++#define RG_TRX_DUMMMY_HI 31
++#define RG_TRX_DUMMMY_SZ 32
++#define RG_SX_DUMMMY_MSK 0xffffffff
++#define RG_SX_DUMMMY_I_MSK 0x00000000
++#define RG_SX_DUMMMY_SFT 0
++#define RG_SX_DUMMMY_HI 31
++#define RG_SX_DUMMMY_SZ 32
++#define RCAL_RDY_MSK 0x00000001
++#define RCAL_RDY_I_MSK 0xfffffffe
++#define RCAL_RDY_SFT 0
++#define RCAL_RDY_HI 0
++#define RCAL_RDY_SZ 1
++#define LCK_BIN_RDY_MSK 0x00000002
++#define LCK_BIN_RDY_I_MSK 0xfffffffd
++#define LCK_BIN_RDY_SFT 1
++#define LCK_BIN_RDY_HI 1
++#define LCK_BIN_RDY_SZ 1
++#define VT_MON_RDY_MSK 0x00000004
++#define VT_MON_RDY_I_MSK 0xfffffffb
++#define VT_MON_RDY_SFT 2
++#define VT_MON_RDY_HI 2
++#define VT_MON_RDY_SZ 1
++#define DA_R_CODE_LUT_MSK 0x000007c0
++#define DA_R_CODE_LUT_I_MSK 0xfffff83f
++#define DA_R_CODE_LUT_SFT 6
++#define DA_R_CODE_LUT_HI 10
++#define DA_R_CODE_LUT_SZ 5
++#define AD_SX_VT_MON_Q_MSK 0x00001800
++#define AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
++#define AD_SX_VT_MON_Q_SFT 11
++#define AD_SX_VT_MON_Q_HI 12
++#define AD_SX_VT_MON_Q_SZ 2
++#define AD_DP_VT_MON_Q_MSK 0x00006000
++#define AD_DP_VT_MON_Q_I_MSK 0xffff9fff
++#define AD_DP_VT_MON_Q_SFT 13
++#define AD_DP_VT_MON_Q_HI 14
++#define AD_DP_VT_MON_Q_SZ 2
++#define RTC_CAL_RDY_MSK 0x00008000
++#define RTC_CAL_RDY_I_MSK 0xffff7fff
++#define RTC_CAL_RDY_SFT 15
++#define RTC_CAL_RDY_HI 15
++#define RTC_CAL_RDY_SZ 1
++#define RG_SARADC_BIT_MSK 0x003f0000
++#define RG_SARADC_BIT_I_MSK 0xffc0ffff
++#define RG_SARADC_BIT_SFT 16
++#define RG_SARADC_BIT_HI 21
++#define RG_SARADC_BIT_SZ 6
++#define SAR_ADC_FSM_RDY_MSK 0x00400000
++#define SAR_ADC_FSM_RDY_I_MSK 0xffbfffff
++#define SAR_ADC_FSM_RDY_SFT 22
++#define SAR_ADC_FSM_RDY_HI 22
++#define SAR_ADC_FSM_RDY_SZ 1
++#define AD_CIRCUIT_VERSION_MSK 0x07800000
++#define AD_CIRCUIT_VERSION_I_MSK 0xf87fffff
++#define AD_CIRCUIT_VERSION_SFT 23
++#define AD_CIRCUIT_VERSION_HI 26
++#define AD_CIRCUIT_VERSION_SZ 4
++#define DA_R_CAL_CODE_MSK 0x0000001f
++#define DA_R_CAL_CODE_I_MSK 0xffffffe0
++#define DA_R_CAL_CODE_SFT 0
++#define DA_R_CAL_CODE_HI 4
++#define DA_R_CAL_CODE_SZ 5
++#define DA_SX_SUB_SEL_MSK 0x00000fe0
++#define DA_SX_SUB_SEL_I_MSK 0xfffff01f
++#define DA_SX_SUB_SEL_SFT 5
++#define DA_SX_SUB_SEL_HI 11
++#define DA_SX_SUB_SEL_SZ 7
++#define RG_DPL_RFCTRL_CH_MSK 0x000007ff
++#define RG_DPL_RFCTRL_CH_I_MSK 0xfffff800
++#define RG_DPL_RFCTRL_CH_SFT 0
++#define RG_DPL_RFCTRL_CH_HI 10
++#define RG_DPL_RFCTRL_CH_SZ 11
++#define RG_RSSIADC_RO_BIT_MSK 0x00007800
++#define RG_RSSIADC_RO_BIT_I_MSK 0xffff87ff
++#define RG_RSSIADC_RO_BIT_SFT 11
++#define RG_RSSIADC_RO_BIT_HI 14
++#define RG_RSSIADC_RO_BIT_SZ 4
++#define RG_RX_ADC_I_RO_BIT_MSK 0x007f8000
++#define RG_RX_ADC_I_RO_BIT_I_MSK 0xff807fff
++#define RG_RX_ADC_I_RO_BIT_SFT 15
++#define RG_RX_ADC_I_RO_BIT_HI 22
++#define RG_RX_ADC_I_RO_BIT_SZ 8
++#define RG_RX_ADC_Q_RO_BIT_MSK 0x7f800000
++#define RG_RX_ADC_Q_RO_BIT_I_MSK 0x807fffff
++#define RG_RX_ADC_Q_RO_BIT_SFT 23
++#define RG_RX_ADC_Q_RO_BIT_HI 30
++#define RG_RX_ADC_Q_RO_BIT_SZ 8
++#define RG_DPL_RFCTRL_F_MSK 0x00ffffff
++#define RG_DPL_RFCTRL_F_I_MSK 0xff000000
++#define RG_DPL_RFCTRL_F_SFT 0
++#define RG_DPL_RFCTRL_F_HI 23
++#define RG_DPL_RFCTRL_F_SZ 24
++#define RG_SX_TARGET_CNT_MSK 0x00001fff
++#define RG_SX_TARGET_CNT_I_MSK 0xffffe000
++#define RG_SX_TARGET_CNT_SFT 0
++#define RG_SX_TARGET_CNT_HI 12
++#define RG_SX_TARGET_CNT_SZ 13
++#define RG_RTC_OFFSET_MSK 0x000000ff
++#define RG_RTC_OFFSET_I_MSK 0xffffff00
++#define RG_RTC_OFFSET_SFT 0
++#define RG_RTC_OFFSET_HI 7
++#define RG_RTC_OFFSET_SZ 8
++#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
++#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
++#define RG_RTC_CAL_TARGET_COUNT_SFT 8
++#define RG_RTC_CAL_TARGET_COUNT_HI 19
++#define RG_RTC_CAL_TARGET_COUNT_SZ 12
++#define RG_RF_D_REG_MSK 0x0000ffff
++#define RG_RF_D_REG_I_MSK 0xffff0000
++#define RG_RF_D_REG_SFT 0
++#define RG_RF_D_REG_HI 15
++#define RG_RF_D_REG_SZ 16
++#define DIRECT_MODE_MSK 0x00000001
++#define DIRECT_MODE_I_MSK 0xfffffffe
++#define DIRECT_MODE_SFT 0
++#define DIRECT_MODE_HI 0
++#define DIRECT_MODE_SZ 1
++#define TAG_INTERLEAVE_MD_MSK 0x00000002
++#define TAG_INTERLEAVE_MD_I_MSK 0xfffffffd
++#define TAG_INTERLEAVE_MD_SFT 1
++#define TAG_INTERLEAVE_MD_HI 1
++#define TAG_INTERLEAVE_MD_SZ 1
++#define DIS_DEMAND_MSK 0x00000004
++#define DIS_DEMAND_I_MSK 0xfffffffb
++#define DIS_DEMAND_SFT 2
++#define DIS_DEMAND_HI 2
++#define DIS_DEMAND_SZ 1
++#define SAME_ID_ALLOC_MD_MSK 0x00000008
++#define SAME_ID_ALLOC_MD_I_MSK 0xfffffff7
++#define SAME_ID_ALLOC_MD_SFT 3
++#define SAME_ID_ALLOC_MD_HI 3
++#define SAME_ID_ALLOC_MD_SZ 1
++#define HS_ACCESS_MD_MSK 0x00000010
++#define HS_ACCESS_MD_I_MSK 0xffffffef
++#define HS_ACCESS_MD_SFT 4
++#define HS_ACCESS_MD_HI 4
++#define HS_ACCESS_MD_SZ 1
++#define SRAM_ACCESS_MD_MSK 0x00000020
++#define SRAM_ACCESS_MD_I_MSK 0xffffffdf
++#define SRAM_ACCESS_MD_SFT 5
++#define SRAM_ACCESS_MD_HI 5
++#define SRAM_ACCESS_MD_SZ 1
++#define NOHIT_RPASS_MD_MSK 0x00000040
++#define NOHIT_RPASS_MD_I_MSK 0xffffffbf
++#define NOHIT_RPASS_MD_SFT 6
++#define NOHIT_RPASS_MD_HI 6
++#define NOHIT_RPASS_MD_SZ 1
++#define DMN_FLAG_CLR_MSK 0x00000080
++#define DMN_FLAG_CLR_I_MSK 0xffffff7f
++#define DMN_FLAG_CLR_SFT 7
++#define DMN_FLAG_CLR_HI 7
++#define DMN_FLAG_CLR_SZ 1
++#define ERR_SW_RST_N_MSK 0x00000100
++#define ERR_SW_RST_N_I_MSK 0xfffffeff
++#define ERR_SW_RST_N_SFT 8
++#define ERR_SW_RST_N_HI 8
++#define ERR_SW_RST_N_SZ 1
++#define ALR_SW_RST_N_MSK 0x00000200
++#define ALR_SW_RST_N_I_MSK 0xfffffdff
++#define ALR_SW_RST_N_SFT 9
++#define ALR_SW_RST_N_HI 9
++#define ALR_SW_RST_N_SZ 1
++#define MCH_SW_RST_N_MSK 0x00000400
++#define MCH_SW_RST_N_I_MSK 0xfffffbff
++#define MCH_SW_RST_N_SFT 10
++#define MCH_SW_RST_N_HI 10
++#define MCH_SW_RST_N_SZ 1
++#define TAG_SW_RST_N_MSK 0x00000800
++#define TAG_SW_RST_N_I_MSK 0xfffff7ff
++#define TAG_SW_RST_N_SFT 11
++#define TAG_SW_RST_N_HI 11
++#define TAG_SW_RST_N_SZ 1
++#define ABT_SW_RST_N_MSK 0x00001000
++#define ABT_SW_RST_N_I_MSK 0xffffefff
++#define ABT_SW_RST_N_SFT 12
++#define ABT_SW_RST_N_HI 12
++#define ABT_SW_RST_N_SZ 1
++#define MMU_VER_MSK 0x0000e000
++#define MMU_VER_I_MSK 0xffff1fff
++#define MMU_VER_SFT 13
++#define MMU_VER_HI 15
++#define MMU_VER_SZ 3
++#define MMU_SHARE_MCU_MSK 0x00ff0000
++#define MMU_SHARE_MCU_I_MSK 0xff00ffff
++#define MMU_SHARE_MCU_SFT 16
++#define MMU_SHARE_MCU_HI 23
++#define MMU_SHARE_MCU_SZ 8
++#define HS_WR_MSK 0x00000001
++#define HS_WR_I_MSK 0xfffffffe
++#define HS_WR_SFT 0
++#define HS_WR_HI 0
++#define HS_WR_SZ 1
++#define HS_FLAG_MSK 0x00000010
++#define HS_FLAG_I_MSK 0xffffffef
++#define HS_FLAG_SFT 4
++#define HS_FLAG_HI 4
++#define HS_FLAG_SZ 1
++#define HS_ID_MSK 0x00007f00
++#define HS_ID_I_MSK 0xffff80ff
++#define HS_ID_SFT 8
++#define HS_ID_HI 14
++#define HS_ID_SZ 7
++#define HS_CHANNEL_MSK 0x000f0000
++#define HS_CHANNEL_I_MSK 0xfff0ffff
++#define HS_CHANNEL_SFT 16
++#define HS_CHANNEL_HI 19
++#define HS_CHANNEL_SZ 4
++#define HS_PAGE_MSK 0x00f00000
++#define HS_PAGE_I_MSK 0xff0fffff
++#define HS_PAGE_SFT 20
++#define HS_PAGE_HI 23
++#define HS_PAGE_SZ 4
++#define HS_DATA_MSK 0xff000000
++#define HS_DATA_I_MSK 0x00ffffff
++#define HS_DATA_SFT 24
++#define HS_DATA_HI 31
++#define HS_DATA_SZ 8
++#define CPU_POR0_MSK 0x0000000f
++#define CPU_POR0_I_MSK 0xfffffff0
++#define CPU_POR0_SFT 0
++#define CPU_POR0_HI 3
++#define CPU_POR0_SZ 4
++#define CPU_POR1_MSK 0x000000f0
++#define CPU_POR1_I_MSK 0xffffff0f
++#define CPU_POR1_SFT 4
++#define CPU_POR1_HI 7
++#define CPU_POR1_SZ 4
++#define CPU_POR2_MSK 0x00000f00
++#define CPU_POR2_I_MSK 0xfffff0ff
++#define CPU_POR2_SFT 8
++#define CPU_POR2_HI 11
++#define CPU_POR2_SZ 4
++#define CPU_POR3_MSK 0x0000f000
++#define CPU_POR3_I_MSK 0xffff0fff
++#define CPU_POR3_SFT 12
++#define CPU_POR3_HI 15
++#define CPU_POR3_SZ 4
++#define CPU_POR4_MSK 0x000f0000
++#define CPU_POR4_I_MSK 0xfff0ffff
++#define CPU_POR4_SFT 16
++#define CPU_POR4_HI 19
++#define CPU_POR4_SZ 4
++#define CPU_POR5_MSK 0x00f00000
++#define CPU_POR5_I_MSK 0xff0fffff
++#define CPU_POR5_SFT 20
++#define CPU_POR5_HI 23
++#define CPU_POR5_SZ 4
++#define CPU_POR6_MSK 0x0f000000
++#define CPU_POR6_I_MSK 0xf0ffffff
++#define CPU_POR6_SFT 24
++#define CPU_POR6_HI 27
++#define CPU_POR6_SZ 4
++#define CPU_POR7_MSK 0xf0000000
++#define CPU_POR7_I_MSK 0x0fffffff
++#define CPU_POR7_SFT 28
++#define CPU_POR7_HI 31
++#define CPU_POR7_SZ 4
++#define CPU_POR8_MSK 0x0000000f
++#define CPU_POR8_I_MSK 0xfffffff0
++#define CPU_POR8_SFT 0
++#define CPU_POR8_HI 3
++#define CPU_POR8_SZ 4
++#define CPU_POR9_MSK 0x000000f0
++#define CPU_POR9_I_MSK 0xffffff0f
++#define CPU_POR9_SFT 4
++#define CPU_POR9_HI 7
++#define CPU_POR9_SZ 4
++#define CPU_PORA_MSK 0x00000f00
++#define CPU_PORA_I_MSK 0xfffff0ff
++#define CPU_PORA_SFT 8
++#define CPU_PORA_HI 11
++#define CPU_PORA_SZ 4
++#define CPU_PORB_MSK 0x0000f000
++#define CPU_PORB_I_MSK 0xffff0fff
++#define CPU_PORB_SFT 12
++#define CPU_PORB_HI 15
++#define CPU_PORB_SZ 4
++#define CPU_PORC_MSK 0x000f0000
++#define CPU_PORC_I_MSK 0xfff0ffff
++#define CPU_PORC_SFT 16
++#define CPU_PORC_HI 19
++#define CPU_PORC_SZ 4
++#define CPU_PORD_MSK 0x00f00000
++#define CPU_PORD_I_MSK 0xff0fffff
++#define CPU_PORD_SFT 20
++#define CPU_PORD_HI 23
++#define CPU_PORD_SZ 4
++#define CPU_PORE_MSK 0x0f000000
++#define CPU_PORE_I_MSK 0xf0ffffff
++#define CPU_PORE_SFT 24
++#define CPU_PORE_HI 27
++#define CPU_PORE_SZ 4
++#define CPU_PORF_MSK 0xf0000000
++#define CPU_PORF_I_MSK 0x0fffffff
++#define CPU_PORF_SFT 28
++#define CPU_PORF_HI 31
++#define CPU_PORF_SZ 4
++#define ACC_WR_LEN_MSK 0x0000003f
++#define ACC_WR_LEN_I_MSK 0xffffffc0
++#define ACC_WR_LEN_SFT 0
++#define ACC_WR_LEN_HI 5
++#define ACC_WR_LEN_SZ 6
++#define ACC_RD_LEN_MSK 0x00003f00
++#define ACC_RD_LEN_I_MSK 0xffffc0ff
++#define ACC_RD_LEN_SFT 8
++#define ACC_RD_LEN_HI 13
++#define ACC_RD_LEN_SZ 6
++#define REQ_NACK_CLR_MSK 0x00008000
++#define REQ_NACK_CLR_I_MSK 0xffff7fff
++#define REQ_NACK_CLR_SFT 15
++#define REQ_NACK_CLR_HI 15
++#define REQ_NACK_CLR_SZ 1
++#define NACK_FLAG_BUS_MSK 0xffff0000
++#define NACK_FLAG_BUS_I_MSK 0x0000ffff
++#define NACK_FLAG_BUS_SFT 16
++#define NACK_FLAG_BUS_HI 31
++#define NACK_FLAG_BUS_SZ 16
++#define DMN_R_PASS_MSK 0x0000ffff
++#define DMN_R_PASS_I_MSK 0xffff0000
++#define DMN_R_PASS_SFT 0
++#define DMN_R_PASS_HI 15
++#define DMN_R_PASS_SZ 16
++#define PARA_ALC_RLS_MSK 0x00010000
++#define PARA_ALC_RLS_I_MSK 0xfffeffff
++#define PARA_ALC_RLS_SFT 16
++#define PARA_ALC_RLS_HI 16
++#define PARA_ALC_RLS_SZ 1
++#define REQ_PORNS_CHGEN_MSK 0x01000000
++#define REQ_PORNS_CHGEN_I_MSK 0xfeffffff
++#define REQ_PORNS_CHGEN_SFT 24
++#define REQ_PORNS_CHGEN_HI 24
++#define REQ_PORNS_CHGEN_SZ 1
++#define ALC_ABT_ID_MSK 0x0000007f
++#define ALC_ABT_ID_I_MSK 0xffffff80
++#define ALC_ABT_ID_SFT 0
++#define ALC_ABT_ID_HI 6
++#define ALC_ABT_ID_SZ 7
++#define ALC_ABT_INT_MSK 0x00008000
++#define ALC_ABT_INT_I_MSK 0xffff7fff
++#define ALC_ABT_INT_SFT 15
++#define ALC_ABT_INT_HI 15
++#define ALC_ABT_INT_SZ 1
++#define RLS_ABT_ID_MSK 0x007f0000
++#define RLS_ABT_ID_I_MSK 0xff80ffff
++#define RLS_ABT_ID_SFT 16
++#define RLS_ABT_ID_HI 22
++#define RLS_ABT_ID_SZ 7
++#define RLS_ABT_INT_MSK 0x80000000
++#define RLS_ABT_INT_I_MSK 0x7fffffff
++#define RLS_ABT_INT_SFT 31
++#define RLS_ABT_INT_HI 31
++#define RLS_ABT_INT_SZ 1
++#define DEBUG_CTL_MSK 0x000000ff
++#define DEBUG_CTL_I_MSK 0xffffff00
++#define DEBUG_CTL_SFT 0
++#define DEBUG_CTL_HI 7
++#define DEBUG_CTL_SZ 8
++#define DEBUG_H16_MSK 0x00000100
++#define DEBUG_H16_I_MSK 0xfffffeff
++#define DEBUG_H16_SFT 8
++#define DEBUG_H16_HI 8
++#define DEBUG_H16_SZ 1
++#define DEBUG_OUT_MSK 0xffffffff
++#define DEBUG_OUT_I_MSK 0x00000000
++#define DEBUG_OUT_SFT 0
++#define DEBUG_OUT_HI 31
++#define DEBUG_OUT_SZ 32
++#define ALC_ERR_MSK 0x00000001
++#define ALC_ERR_I_MSK 0xfffffffe
++#define ALC_ERR_SFT 0
++#define ALC_ERR_HI 0
++#define ALC_ERR_SZ 1
++#define RLS_ERR_MSK 0x00000002
++#define RLS_ERR_I_MSK 0xfffffffd
++#define RLS_ERR_SFT 1
++#define RLS_ERR_HI 1
++#define RLS_ERR_SZ 1
++#define AL_STATE_MSK 0x00000700
++#define AL_STATE_I_MSK 0xfffff8ff
++#define AL_STATE_SFT 8
++#define AL_STATE_HI 10
++#define AL_STATE_SZ 3
++#define RL_STATE_MSK 0x00007000
++#define RL_STATE_I_MSK 0xffff8fff
++#define RL_STATE_SFT 12
++#define RL_STATE_HI 14
++#define RL_STATE_SZ 3
++#define ALC_ERR_ID_MSK 0x007f0000
++#define ALC_ERR_ID_I_MSK 0xff80ffff
++#define ALC_ERR_ID_SFT 16
++#define ALC_ERR_ID_HI 22
++#define ALC_ERR_ID_SZ 7
++#define RLS_ERR_ID_MSK 0x7f000000
++#define RLS_ERR_ID_I_MSK 0x80ffffff
++#define RLS_ERR_ID_SFT 24
++#define RLS_ERR_ID_HI 30
++#define RLS_ERR_ID_SZ 7
++#define DMN_NOHIT_FLAG_MSK 0x00000001
++#define DMN_NOHIT_FLAG_I_MSK 0xfffffffe
++#define DMN_NOHIT_FLAG_SFT 0
++#define DMN_NOHIT_FLAG_HI 0
++#define DMN_NOHIT_FLAG_SZ 1
++#define DMN_FLAG_MSK 0x00000002
++#define DMN_FLAG_I_MSK 0xfffffffd
++#define DMN_FLAG_SFT 1
++#define DMN_FLAG_HI 1
++#define DMN_FLAG_SZ 1
++#define DMN_WR_MSK 0x00000008
++#define DMN_WR_I_MSK 0xfffffff7
++#define DMN_WR_SFT 3
++#define DMN_WR_HI 3
++#define DMN_WR_SZ 1
++#define DMN_PORT_MSK 0x000000f0
++#define DMN_PORT_I_MSK 0xffffff0f
++#define DMN_PORT_SFT 4
++#define DMN_PORT_HI 7
++#define DMN_PORT_SZ 4
++#define DMN_NHIT_ID_MSK 0x00007f00
++#define DMN_NHIT_ID_I_MSK 0xffff80ff
++#define DMN_NHIT_ID_SFT 8
++#define DMN_NHIT_ID_HI 14
++#define DMN_NHIT_ID_SZ 7
++#define DMN_NHIT_ADDR_MSK 0xffff0000
++#define DMN_NHIT_ADDR_I_MSK 0x0000ffff
++#define DMN_NHIT_ADDR_SFT 16
++#define DMN_NHIT_ADDR_HI 31
++#define DMN_NHIT_ADDR_SZ 16
++#define TX_MOUNT_MSK 0x000000ff
++#define TX_MOUNT_I_MSK 0xffffff00
++#define TX_MOUNT_SFT 0
++#define TX_MOUNT_HI 7
++#define TX_MOUNT_SZ 8
++#define RX_MOUNT_MSK 0x0000ff00
++#define RX_MOUNT_I_MSK 0xffff00ff
++#define RX_MOUNT_SFT 8
++#define RX_MOUNT_HI 15
++#define RX_MOUNT_SZ 8
++#define AVA_TAG_MSK 0x01ff0000
++#define AVA_TAG_I_MSK 0xfe00ffff
++#define AVA_TAG_SFT 16
++#define AVA_TAG_HI 24
++#define AVA_TAG_SZ 9
++#define PKTBUF_FULL_MSK 0x80000000
++#define PKTBUF_FULL_I_MSK 0x7fffffff
++#define PKTBUF_FULL_SFT 31
++#define PKTBUF_FULL_HI 31
++#define PKTBUF_FULL_SZ 1
++#define DMN_NOHIT_MCU_MSK 0x00000001
++#define DMN_NOHIT_MCU_I_MSK 0xfffffffe
++#define DMN_NOHIT_MCU_SFT 0
++#define DMN_NOHIT_MCU_HI 0
++#define DMN_NOHIT_MCU_SZ 1
++#define DMN_MCU_FLAG_MSK 0x00000002
++#define DMN_MCU_FLAG_I_MSK 0xfffffffd
++#define DMN_MCU_FLAG_SFT 1
++#define DMN_MCU_FLAG_HI 1
++#define DMN_MCU_FLAG_SZ 1
++#define DMN_MCU_WR_MSK 0x00000008
++#define DMN_MCU_WR_I_MSK 0xfffffff7
++#define DMN_MCU_WR_SFT 3
++#define DMN_MCU_WR_HI 3
++#define DMN_MCU_WR_SZ 1
++#define DMN_MCU_PORT_MSK 0x000000f0
++#define DMN_MCU_PORT_I_MSK 0xffffff0f
++#define DMN_MCU_PORT_SFT 4
++#define DMN_MCU_PORT_HI 7
++#define DMN_MCU_PORT_SZ 4
++#define DMN_MCU_ID_MSK 0x00007f00
++#define DMN_MCU_ID_I_MSK 0xffff80ff
++#define DMN_MCU_ID_SFT 8
++#define DMN_MCU_ID_HI 14
++#define DMN_MCU_ID_SZ 7
++#define DMN_MCU_ADDR_MSK 0xffff0000
++#define DMN_MCU_ADDR_I_MSK 0x0000ffff
++#define DMN_MCU_ADDR_SFT 16
++#define DMN_MCU_ADDR_HI 31
++#define DMN_MCU_ADDR_SZ 16
++#define MB_IDTBL_31_0_MSK 0xffffffff
++#define MB_IDTBL_31_0_I_MSK 0x00000000
++#define MB_IDTBL_31_0_SFT 0
++#define MB_IDTBL_31_0_HI 31
++#define MB_IDTBL_31_0_SZ 32
++#define MB_IDTBL_63_32_MSK 0xffffffff
++#define MB_IDTBL_63_32_I_MSK 0x00000000
++#define MB_IDTBL_63_32_SFT 0
++#define MB_IDTBL_63_32_HI 31
++#define MB_IDTBL_63_32_SZ 32
++#define MB_IDTBL_95_64_MSK 0xffffffff
++#define MB_IDTBL_95_64_I_MSK 0x00000000
++#define MB_IDTBL_95_64_SFT 0
++#define MB_IDTBL_95_64_HI 31
++#define MB_IDTBL_95_64_SZ 32
++#define MB_IDTBL_127_96_MSK 0xffffffff
++#define MB_IDTBL_127_96_I_MSK 0x00000000
++#define MB_IDTBL_127_96_SFT 0
++#define MB_IDTBL_127_96_HI 31
++#define MB_IDTBL_127_96_SZ 32
++#define PKT_IDTBL_31_0_MSK 0xffffffff
++#define PKT_IDTBL_31_0_I_MSK 0x00000000
++#define PKT_IDTBL_31_0_SFT 0
++#define PKT_IDTBL_31_0_HI 31
++#define PKT_IDTBL_31_0_SZ 32
++#define PKT_IDTBL_63_32_MSK 0xffffffff
++#define PKT_IDTBL_63_32_I_MSK 0x00000000
++#define PKT_IDTBL_63_32_SFT 0
++#define PKT_IDTBL_63_32_HI 31
++#define PKT_IDTBL_63_32_SZ 32
++#define PKT_IDTBL_95_64_MSK 0xffffffff
++#define PKT_IDTBL_95_64_I_MSK 0x00000000
++#define PKT_IDTBL_95_64_SFT 0
++#define PKT_IDTBL_95_64_HI 31
++#define PKT_IDTBL_95_64_SZ 32
++#define PKT_IDTBL_127_96_MSK 0xffffffff
++#define PKT_IDTBL_127_96_I_MSK 0x00000000
++#define PKT_IDTBL_127_96_SFT 0
++#define PKT_IDTBL_127_96_HI 31
++#define PKT_IDTBL_127_96_SZ 32
++#define DMN_IDTBL_31_0_MSK 0xffffffff
++#define DMN_IDTBL_31_0_I_MSK 0x00000000
++#define DMN_IDTBL_31_0_SFT 0
++#define DMN_IDTBL_31_0_HI 31
++#define DMN_IDTBL_31_0_SZ 32
++#define DMN_IDTBL_63_32_MSK 0xffffffff
++#define DMN_IDTBL_63_32_I_MSK 0x00000000
++#define DMN_IDTBL_63_32_SFT 0
++#define DMN_IDTBL_63_32_HI 31
++#define DMN_IDTBL_63_32_SZ 32
++#define DMN_IDTBL_95_64_MSK 0xffffffff
++#define DMN_IDTBL_95_64_I_MSK 0x00000000
++#define DMN_IDTBL_95_64_SFT 0
++#define DMN_IDTBL_95_64_HI 31
++#define DMN_IDTBL_95_64_SZ 32
++#define DMN_IDTBL_127_96_MSK 0xffffffff
++#define DMN_IDTBL_127_96_I_MSK 0x00000000
++#define DMN_IDTBL_127_96_SFT 0
++#define DMN_IDTBL_127_96_HI 31
++#define DMN_IDTBL_127_96_SZ 32
++#define NEQ_MB_ID_31_0_MSK 0xffffffff
++#define NEQ_MB_ID_31_0_I_MSK 0x00000000
++#define NEQ_MB_ID_31_0_SFT 0
++#define NEQ_MB_ID_31_0_HI 31
++#define NEQ_MB_ID_31_0_SZ 32
++#define NEQ_MB_ID_63_32_MSK 0xffffffff
++#define NEQ_MB_ID_63_32_I_MSK 0x00000000
++#define NEQ_MB_ID_63_32_SFT 0
++#define NEQ_MB_ID_63_32_HI 31
++#define NEQ_MB_ID_63_32_SZ 32
++#define NEQ_MB_ID_95_64_MSK 0xffffffff
++#define NEQ_MB_ID_95_64_I_MSK 0x00000000
++#define NEQ_MB_ID_95_64_SFT 0
++#define NEQ_MB_ID_95_64_HI 31
++#define NEQ_MB_ID_95_64_SZ 32
++#define NEQ_MB_ID_127_96_MSK 0xffffffff
++#define NEQ_MB_ID_127_96_I_MSK 0x00000000
++#define NEQ_MB_ID_127_96_SFT 0
++#define NEQ_MB_ID_127_96_HI 31
++#define NEQ_MB_ID_127_96_SZ 32
++#define NEQ_PKT_ID_31_0_MSK 0xffffffff
++#define NEQ_PKT_ID_31_0_I_MSK 0x00000000
++#define NEQ_PKT_ID_31_0_SFT 0
++#define NEQ_PKT_ID_31_0_HI 31
++#define NEQ_PKT_ID_31_0_SZ 32
++#define NEQ_PKT_ID_63_32_MSK 0xffffffff
++#define NEQ_PKT_ID_63_32_I_MSK 0x00000000
++#define NEQ_PKT_ID_63_32_SFT 0
++#define NEQ_PKT_ID_63_32_HI 31
++#define NEQ_PKT_ID_63_32_SZ 32
++#define NEQ_PKT_ID_95_64_MSK 0xffffffff
++#define NEQ_PKT_ID_95_64_I_MSK 0x00000000
++#define NEQ_PKT_ID_95_64_SFT 0
++#define NEQ_PKT_ID_95_64_HI 31
++#define NEQ_PKT_ID_95_64_SZ 32
++#define NEQ_PKT_ID_127_96_MSK 0xffffffff
++#define NEQ_PKT_ID_127_96_I_MSK 0x00000000
++#define NEQ_PKT_ID_127_96_SFT 0
++#define NEQ_PKT_ID_127_96_HI 31
++#define NEQ_PKT_ID_127_96_SZ 32
++#define ALC_NOCHG_ID_MSK 0x0000007f
++#define ALC_NOCHG_ID_I_MSK 0xffffff80
++#define ALC_NOCHG_ID_SFT 0
++#define ALC_NOCHG_ID_HI 6
++#define ALC_NOCHG_ID_SZ 7
++#define ALC_NOCHG_INT_MSK 0x00008000
++#define ALC_NOCHG_INT_I_MSK 0xffff7fff
++#define ALC_NOCHG_INT_SFT 15
++#define ALC_NOCHG_INT_HI 15
++#define ALC_NOCHG_INT_SZ 1
++#define NEQ_PKT_FLAG_MSK 0x00010000
++#define NEQ_PKT_FLAG_I_MSK 0xfffeffff
++#define NEQ_PKT_FLAG_SFT 16
++#define NEQ_PKT_FLAG_HI 16
++#define NEQ_PKT_FLAG_SZ 1
++#define NEQ_MB_FLAG_MSK 0x01000000
++#define NEQ_MB_FLAG_I_MSK 0xfeffffff
++#define NEQ_MB_FLAG_SFT 24
++#define NEQ_MB_FLAG_HI 24
++#define NEQ_MB_FLAG_SZ 1
++#define SRAM_TAG_0_MSK 0x0000ffff
++#define SRAM_TAG_0_I_MSK 0xffff0000
++#define SRAM_TAG_0_SFT 0
++#define SRAM_TAG_0_HI 15
++#define SRAM_TAG_0_SZ 16
++#define SRAM_TAG_1_MSK 0xffff0000
++#define SRAM_TAG_1_I_MSK 0x0000ffff
++#define SRAM_TAG_1_SFT 16
++#define SRAM_TAG_1_HI 31
++#define SRAM_TAG_1_SZ 16
++#define SRAM_TAG_2_MSK 0x0000ffff
++#define SRAM_TAG_2_I_MSK 0xffff0000
++#define SRAM_TAG_2_SFT 0
++#define SRAM_TAG_2_HI 15
++#define SRAM_TAG_2_SZ 16
++#define SRAM_TAG_3_MSK 0xffff0000
++#define SRAM_TAG_3_I_MSK 0x0000ffff
++#define SRAM_TAG_3_SFT 16
++#define SRAM_TAG_3_HI 31
++#define SRAM_TAG_3_SZ 16
++#define SRAM_TAG_4_MSK 0x0000ffff
++#define SRAM_TAG_4_I_MSK 0xffff0000
++#define SRAM_TAG_4_SFT 0
++#define SRAM_TAG_4_HI 15
++#define SRAM_TAG_4_SZ 16
++#define SRAM_TAG_5_MSK 0xffff0000
++#define SRAM_TAG_5_I_MSK 0x0000ffff
++#define SRAM_TAG_5_SFT 16
++#define SRAM_TAG_5_HI 31
++#define SRAM_TAG_5_SZ 16
++#define SRAM_TAG_6_MSK 0x0000ffff
++#define SRAM_TAG_6_I_MSK 0xffff0000
++#define SRAM_TAG_6_SFT 0
++#define SRAM_TAG_6_HI 15
++#define SRAM_TAG_6_SZ 16
++#define SRAM_TAG_7_MSK 0xffff0000
++#define SRAM_TAG_7_I_MSK 0x0000ffff
++#define SRAM_TAG_7_SFT 16
++#define SRAM_TAG_7_HI 31
++#define SRAM_TAG_7_SZ 16
++#define SRAM_TAG_8_MSK 0x0000ffff
++#define SRAM_TAG_8_I_MSK 0xffff0000
++#define SRAM_TAG_8_SFT 0
++#define SRAM_TAG_8_HI 15
++#define SRAM_TAG_8_SZ 16
++#define SRAM_TAG_9_MSK 0xffff0000
++#define SRAM_TAG_9_I_MSK 0x0000ffff
++#define SRAM_TAG_9_SFT 16
++#define SRAM_TAG_9_HI 31
++#define SRAM_TAG_9_SZ 16
++#define SRAM_TAG_10_MSK 0x0000ffff
++#define SRAM_TAG_10_I_MSK 0xffff0000
++#define SRAM_TAG_10_SFT 0
++#define SRAM_TAG_10_HI 15
++#define SRAM_TAG_10_SZ 16
++#define SRAM_TAG_11_MSK 0xffff0000
++#define SRAM_TAG_11_I_MSK 0x0000ffff
++#define SRAM_TAG_11_SFT 16
++#define SRAM_TAG_11_HI 31
++#define SRAM_TAG_11_SZ 16
++#define SRAM_TAG_12_MSK 0x0000ffff
++#define SRAM_TAG_12_I_MSK 0xffff0000
++#define SRAM_TAG_12_SFT 0
++#define SRAM_TAG_12_HI 15
++#define SRAM_TAG_12_SZ 16
++#define SRAM_TAG_13_MSK 0xffff0000
++#define SRAM_TAG_13_I_MSK 0x0000ffff
++#define SRAM_TAG_13_SFT 16
++#define SRAM_TAG_13_HI 31
++#define SRAM_TAG_13_SZ 16
++#define SRAM_TAG_14_MSK 0x0000ffff
++#define SRAM_TAG_14_I_MSK 0xffff0000
++#define SRAM_TAG_14_SFT 0
++#define SRAM_TAG_14_HI 15
++#define SRAM_TAG_14_SZ 16
++#define SRAM_TAG_15_MSK 0xffff0000
++#define SRAM_TAG_15_I_MSK 0x0000ffff
++#define SRAM_TAG_15_SFT 16
++#define SRAM_TAG_15_HI 31
++#define SRAM_TAG_15_SZ 16
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_common.h b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
+new file mode 100644
+index 000000000000..e6d30f3714f7
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
+@@ -0,0 +1,452 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV6200_COMMON_H_
++#define _SSV6200_COMMON_H_
++#define FW_VERSION_REG ADR_TX_SEG
++#define M_ENG_CPU 0x00
++#define M_ENG_HWHCI 0x01
++#define M_ENG_EMPTY 0x02
++#define M_ENG_ENCRYPT 0x03
++#define M_ENG_MACRX 0x04
++#define M_ENG_MIC 0x05
++#define M_ENG_TX_EDCA0 0x06
++#define M_ENG_TX_EDCA1 0x07
++#define M_ENG_TX_EDCA2 0x08
++#define M_ENG_TX_EDCA3 0x09
++#define M_ENG_TX_MNG 0x0A
++#define M_ENG_ENCRYPT_SEC 0x0B
++#define M_ENG_MIC_SEC 0x0C
++#define M_ENG_RESERVED_1 0x0D
++#define M_ENG_RESERVED_2 0x0E
++#define M_ENG_TRASH_CAN 0x0F
++#define M_ENG_MAX (M_ENG_TRASH_CAN+1)
++#define M_CPU_HWENG 0x00
++#define M_CPU_TXL34CS 0x01
++#define M_CPU_RXL34CS 0x02
++#define M_CPU_DEFRAG 0x03
++#define M_CPU_EDCATX 0x04
++#define M_CPU_RXDATA 0x05
++#define M_CPU_RXMGMT 0x06
++#define M_CPU_RXCTRL 0x07
++#define M_CPU_FRAG 0x08
++#define M_CPU_TXTPUT 0x09
++#ifndef ID_TRAP_SW_TXTPUT
++#define ID_TRAP_SW_TXTPUT 50
++#endif
++#define M0_TXREQ 0
++#define M1_TXREQ 1
++#define M2_TXREQ 2
++#define M0_RXEVENT 3
++#define M2_RXEVENT 4
++#define HOST_CMD 5
++#define HOST_EVENT 6
++#define TEST_CMD 7
++#define SSV6XXX_RX_DESC_LEN \
++        (sizeof(struct ssv6200_rx_desc) + \
++         sizeof(struct ssv6200_rxphy_info))
++#define SSV6XXX_TX_DESC_LEN \
++        (sizeof(struct ssv6200_tx_desc) + 0)
++#define TXPB_OFFSET 80
++#define RXPB_OFFSET 80
++#define SSV6200_TX_PKT_RSVD_SETTING 0x3
++#define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16
++#define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD
++#define SSV62XX_TX_MAX_RATES 3
++
++enum ssv6xxx_sr_bhvr {
++	SUSPEND_RESUME_0,
++	SUSPEND_RESUME_1,
++	SUSPEND_RESUME_MAX
++};
++
++enum ssv6xxx_reboot_bhvr {
++	SSV_SYS_REBOOT = 1,
++	SSV_SYS_HALF,
++	SSV_SYS_POWER_OFF
++};
++
++struct fw_rc_retry_params {
++	u32 count:4;
++	u32 drate:6;
++	u32 crate:6;
++	u32 rts_cts_nav:16;
++	u32 frame_consume_time:10;
++	u32 dl_length:12;
++	u32 RSVD:10;
++} __attribute__((packed));
++struct ssv6200_tx_desc {
++	u32 len:16;
++	u32 c_type:3;
++	u32 f80211:1;
++	u32 qos:1;
++	u32 ht:1;
++	u32 use_4addr:1;
++	u32 RSVD_0:3;
++	u32 bc_que:1;
++	u32 security:1;
++	u32 more_data:1;
++	u32 stype_b5b4:2;
++	u32 extra_info:1;
++	u32 fCmd;
++	u32 hdr_offset:8;
++	u32 frag:1;
++	u32 unicast:1;
++	u32 hdr_len:6;
++	u32 tx_report:1;
++	u32 tx_burst:1;
++	u32 ack_policy:2;
++	u32 aggregation:1;
++	u32 RSVD_1:3;
++	u32 do_rts_cts:2;
++	u32 reason:6;
++	u32 payload_offset:8;
++	u32 RSVD_4:7;
++	u32 RSVD_2:1;
++	u32 fCmdIdx:3;
++	u32 wsid:4;
++	u32 txq_idx:3;
++	u32 TxF_ID:6;
++	u32 rts_cts_nav:16;
++	u32 frame_consume_time:10;
++	u32 crate_idx:6;
++	u32 drate_idx:6;
++	u32 dl_length:12;
++	u32 RSVD_3:14;
++	u32 RESERVED[8];
++	struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];
++};
++struct ssv6200_rx_desc {
++	u32 len:16;
++	u32 c_type:3;
++	u32 f80211:1;
++	u32 qos:1;
++	u32 ht:1;
++	u32 use_4addr:1;
++	u32 l3cs_err:1;
++	u32 l4cs_err:1;
++	u32 align2:1;
++	u32 RSVD_0:2;
++	u32 psm:1;
++	u32 stype_b5b4:2;
++	u32 extra_info:1;
++	u32 edca0_used:4;
++	u32 edca1_used:5;
++	u32 edca2_used:5;
++	u32 edca3_used:5;
++	u32 mng_used:4;
++	u32 tx_page_used:9;
++	u32 hdr_offset:8;
++	u32 frag:1;
++	u32 unicast:1;
++	u32 hdr_len:6;
++	u32 RxResult:8;
++	u32 wildcard_bssid:1;
++	u32 RSVD_1:1;
++	u32 reason:6;
++	u32 payload_offset:8;
++	u32 tx_id_used:8;
++	u32 fCmdIdx:3;
++	u32 wsid:4;
++	u32 RSVD_3:3;
++	u32 rate_idx:6;
++};
++struct ssv6200_rxphy_info {
++	u32 len:16;
++	u32 rsvd0:16;
++	u32 mode:3;
++	u32 ch_bw:3;
++	u32 preamble:1;
++	u32 ht_short_gi:1;
++	u32 rate:7;
++	u32 rsvd1:1;
++	u32 smoothing:1;
++	u32 no_sounding:1;
++	u32 aggregate:1;
++	u32 stbc:2;
++	u32 fec:1;
++	u32 n_ess:2;
++	u32 rsvd2:8;
++	u32 l_length:12;
++	u32 l_rate:3;
++	u32 rsvd3:17;
++	u32 rsvd4;
++	u32 rpci:8;
++	u32 snr:8;
++	u32 service:16;
++};
++struct ssv6200_rxphy_info_padding {
++	u32 rpci:8;
++	u32 snr:8;
++	u32 RSVD:16;
++};
++struct ssv6200_txphy_info {
++	u32 rsvd[7];
++};
++#ifdef CONFIG_P2P_NOA
++struct ssv6xxx_p2p_noa_param {
++	u32 duration;
++	u32 interval;
++	u32 start_time;
++	u32 enable:8;
++	u32 count:8;
++	u8 addr[6];
++	u8 vif_id;
++} __attribute__((packed));
++#endif
++typedef struct cfg_host_cmd {
++	u32 len:16;
++	u32 c_type:3;
++	u32 RSVD0:5;
++	u32 h_cmd:8;
++	u32 cmd_seq_no;
++	union {
++		u32 dummy;
++		u8 dat8[0];
++		u16 dat16[0];
++		u32 dat32[0];
++	};
++} HDR_HostCmd;
++#define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U)
++struct sdio_rxtput_cfg {
++	u32 size_per_frame;
++	u32 total_frames;
++};
++typedef enum {
++	SSV6XXX_HOST_CMD_START = 0,
++	SSV6XXX_HOST_CMD_LOG,
++	SSV6XXX_HOST_CMD_PS,
++	SSV6XXX_HOST_CMD_INIT_CALI,
++	SSV6XXX_HOST_CMD_RX_TPUT,
++	SSV6XXX_HOST_CMD_TX_TPUT,
++	SSV6XXX_HOST_CMD_WATCHDOG_START,
++	SSV6XXX_HOST_CMD_WATCHDOG_STOP,
++	SSV6XXX_HOST_CMD_WSID_OP,
++#ifdef CONFIG_P2P_NOA
++	SSV6XXX_HOST_CMD_SET_NOA,
++#endif
++	SSV6XXX_HOST_SOC_CMD_MAXID,
++} ssv6xxx_host_cmd_id;
++#define SSV_NUM_HW_STA 2
++typedef struct cfg_host_event {
++	u32 len:16;
++	u32 c_type:3;
++	u32 RSVD0:5;
++	u32 h_event:8;
++	u32 evt_seq_no;
++	u8 dat[0];
++} HDR_HostEvent;
++typedef enum {
++#ifdef USE_CMD_RESP
++	SOC_EVT_CMD_RESP,
++	SOC_EVT_SCAN_RESULT,
++	SOC_EVT_DEAUTH,
++#else
++	SOC_EVT_GET_REG_RESP,
++#endif
++	SOC_EVT_NO_BA,
++	SOC_EVT_RC_MPDU_REPORT,
++	SOC_EVT_RC_AMPDU_REPORT,
++	SOC_EVT_LOG,
++#ifdef CONFIG_P2P_NOA
++	SOC_EVT_NOA,
++#endif
++	SOC_EVT_USER_END,
++	SOC_EVT_SDIO_TEST_COMMAND,
++	SOC_EVT_RESET_HOST,
++	SOC_EVT_SDIO_TXTPUT_RESULT,
++	SOC_EVT_WATCHDOG_TRIGGER,
++	SOC_EVT_TXLOOPBK_RESULT,
++	SOC_EVT_MAXID,
++} ssv6xxx_soc_event;
++#ifdef CONFIG_P2P_NOA
++typedef enum {
++	SSV6XXX_NOA_START = 0,
++	SSV6XXX_NOA_STOP,
++} ssv6xxx_host_noa_event;
++struct ssv62xx_noa_evt {
++	u8 evt_id;
++	u8 vif;
++} __attribute__((packed));
++#endif
++typedef enum {
++	SSV6XXX_RC_COUNTER_CLEAR = 1,
++	SSV6XXX_RC_REPORT,
++} ssv6xxx_host_rate_control_event;
++#define MAX_AGGR_NUM (24)
++struct ssv62xx_tx_rate {
++	s8 data_rate;
++	u8 count;
++} __attribute__((packed));
++struct ampdu_ba_notify_data {
++	u8 wsid;
++	struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];
++	u16 seq_no[MAX_AGGR_NUM];
++} __attribute__((packed));
++struct firmware_rate_control_report_data {
++	u8 wsid;
++	struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];
++	u16 ampdu_len;
++	u16 ampdu_ack_len;
++	int ack_signal;
++} __attribute__((packed));
++#define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES)
++#define SSV_RC_RATE_MAX 39
++enum SSV6XXX_WSID_OPS {
++	SSV6XXX_WSID_OPS_ADD,
++	SSV6XXX_WSID_OPS_DEL,
++	SSV6XXX_WSID_OPS_RESETALL,
++	SSV6XXX_WSID_OPS_ENABLE_CAPS,
++	SSV6XXX_WSID_OPS_DISABLE_CAPS,
++	SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE,
++	SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE,
++	SSV6XXX_WSID_OPS_MAX
++};
++enum SSV6XXX_WSID_SEC {
++	SSV6XXX_WSID_SEC_NONE = 0,
++	SSV6XXX_WSID_SEC_PAIRWISE = 1 << 0,
++	SSV6XXX_WSID_SEC_GROUP = 1 << 1,
++};
++enum SSV6XXX_WSID_SEC_TYPE {
++	SSV6XXX_WSID_SEC_SW,
++	SSV6XXX_WSID_SEC_HW,
++	SSV6XXX_WSID_SEC_TYPE_MAX
++};
++enum SSV6XXX_RETURN_STATE {
++	SSV6XXX_STATE_OK,
++	SSV6XXX_STATE_NG,
++	SSV6XXX_STATE_MAX
++};
++struct ssv6xxx_wsid_params {
++	u8 cmd;
++	u8 wsid_idx;
++	u8 target_wsid[6];
++	u8 hw_security;
++};
++struct ssv6xxx_iqk_cfg {
++	u32 cfg_xtal:8;
++	u32 cfg_pa:8;
++	u32 cfg_pabias_ctrl:8;
++	u32 cfg_pacascode_ctrl:8;
++	u32 cfg_tssi_trgt:8;
++	u32 cfg_tssi_div:8;
++	u32 cfg_def_tx_scale_11b:8;
++	u32 cfg_def_tx_scale_11b_p0d5:8;
++	u32 cfg_def_tx_scale_11g:8;
++	u32 cfg_def_tx_scale_11g_p0d5:8;
++	u32 cmd_sel;
++	union {
++		u32 fx_sel;
++		u32 argv;
++	};
++	u32 phy_tbl_size;
++	u32 rf_tbl_size;
++};
++#define PHY_SETTING_SIZE sizeof(phy_setting)
++struct ssv6xxx_ch_cfg {
++	u32 reg_addr;
++	u32 ch1_12_value;
++	u32 ch13_14_value;
++};
++#define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg))
++#define RF_SETTING_SIZE (sizeof(asic_rf_setting))
++#define MAX_PHY_SETTING_TABLE_SIZE 1920
++#define MAX_RF_SETTING_TABLE_SIZE 512
++typedef enum {
++	SSV6XXX_VOLT_DCDC_CONVERT = 0,
++	SSV6XXX_VOLT_LDO_CONVERT,
++} ssv6xxx_cfg_volt;
++typedef enum {
++	SSV6XXX_VOLT_33V = 0,
++	SSV6XXX_VOLT_42V,
++} ssv6xxx_cfg_volt_value;
++typedef enum {
++	SSV6XXX_IQK_CFG_XTAL_26M = 0,
++	SSV6XXX_IQK_CFG_XTAL_40M,
++	SSV6XXX_IQK_CFG_XTAL_24M,
++	SSV6XXX_IQK_CFG_XTAL_MAX,
++} ssv6xxx_iqk_cfg_xtal;
++typedef enum {
++	SSV6XXX_IQK_CFG_PA_DEF = 0,
++	SSV6XXX_IQK_CFG_PA_LI_MPB,
++	SSV6XXX_IQK_CFG_PA_LI_EVB,
++	SSV6XXX_IQK_CFG_PA_HP,
++} ssv6xxx_iqk_cfg_pa;
++typedef enum {
++	SSV6XXX_IQK_CMD_INIT_CALI = 0,
++	SSV6XXX_IQK_CMD_RTBL_LOAD,
++	SSV6XXX_IQK_CMD_RTBL_LOAD_DEF,
++	SSV6XXX_IQK_CMD_RTBL_RESET,
++	SSV6XXX_IQK_CMD_RTBL_SET,
++	SSV6XXX_IQK_CMD_RTBL_EXPORT,
++	SSV6XXX_IQK_CMD_TK_EVM,
++	SSV6XXX_IQK_CMD_TK_TONE,
++	SSV6XXX_IQK_CMD_TK_CHCH,
++} ssv6xxx_iqk_cmd_sel;
++#define SSV6XXX_IQK_TEMPERATURE 0x00000004
++#define SSV6XXX_IQK_RXDC 0x00000008
++#define SSV6XXX_IQK_RXRC 0x00000010
++#define SSV6XXX_IQK_TXDC 0x00000020
++#define SSV6XXX_IQK_TXIQ 0x00000040
++#define SSV6XXX_IQK_RXIQ 0x00000080
++#define SSV6XXX_IQK_TSSI 0x00000100
++#define SSV6XXX_IQK_PAPD 0x00000200
++typedef struct ssv_cabrio_reg_st {
++	u32 address;
++	u32 data;
++} ssv_cabrio_reg;
++typedef enum __PBuf_Type_E {
++	NOTYPE_BUF = 0,
++	TX_BUF = 1,
++	RX_BUF = 2
++} PBuf_Type_E;
++struct SKB_info_st {
++	struct ieee80211_sta *sta;
++	u16 mpdu_retry_counter;
++	unsigned long aggr_timestamp;
++	u16 ampdu_tx_status;
++	u16 ampdu_tx_final_retry_count;
++	u16 lowest_rate;
++	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++	ktime_t timestamp;
++#endif
++};
++typedef struct SKB_info_st SKB_info;
++typedef struct SKB_info_st *p_SKB_info;
++#define SSV_SKB_info_size (sizeof(struct SKB_info_st))
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++#define SKB_DURATION_TIMEOUT_MS 100
++enum ssv_debug_skb_timestamp {
++	SKB_DURATION_STAGE_TX_ENQ,
++	SKB_DURATION_STAGE_TO_SDIO,
++	SKB_DURATION_STAGE_IN_HWQ,
++	SKB_DURATION_STAGE_END
++};
++#endif
++#define SSV6051Q_P1 0x00000000
++#define SSV6051Q_P2 0x70000000
++#define SSV6051Z 0x71000000
++#define SSV6051Q 0x73000000
++#define SSV6051P 0x75000000
++struct ssv6xxx_tx_loopback {
++	u32 reg;
++	u32 val;
++	u32 restore_val;
++	u8 restore;
++	u8 delay_ms;
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
+new file mode 100644
+index 000000000000..0327393de3f5
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
+@@ -0,0 +1,317 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++static ssv_cabrio_reg phy_setting[] = {
++	{0xce0071bc, 0x565B565B},
++	{0xce000008, 0x0000006a},
++	{0xce00000c, 0x00000064},
++	{0xce000010, 0x00007FFF},
++	{0xce000014, 0x00000003},
++	{0xce000018, 0x0055003C},
++	{0xce00001c, 0x00000064},
++	{0xce000020, 0x20000000},
++	{0xce00002c, 0x00000000},
++	{0xce000030, 0x80046072},
++	{0xce000034, 0x1f300f6f},
++	{0xce000038, 0x660F36D0},
++	{0xce00003c, 0x106C0004},
++	{0xce000040, 0x01601400},
++	{0xce000044, 0x00600008},
++	{0xce000048, 0xff000160},
++	{0xce00004c, 0x00000840},
++	{0xce000060, 0x01000405},
++	{0xce000064, 0x06090813},
++	{0xce000068, 0x12070000},
++	{0xce00006c, 0x01000405},
++	{0xce000070, 0x06090813},
++	{0xce000074, 0x12010000},
++	{0xce000078, 0x00000000},
++	{0xce00007c, 0x10110003},
++	{0xce000080, 0x0110000F},
++	{0xce000084, 0x00000000},
++	{0xce000088, 0x00000000},
++	{0xce000094, 0x01012425},
++	{0xce000098, 0x01010101},
++	{0xce00009c, 0x00000011},
++	{0xce0000a0, 0x1fff0000},
++	{0xce0000a4, 0x1fff0000},
++	{0xce0000a8, 0x1fff0000},
++	{0xce0000ac, 0x1fff0000},
++	{0xce0000b8, 0x0000fe3e},
++	{0xce0000fc, 0xffffffff},
++	{0xce000108, 0x0ead04f5},
++	{0xce00010c, 0x0fd60080},
++	{0xce000110, 0x00000009},
++	{0xce0010a4, 0x0000002c},
++	{0xce0010b4, 0x00003001},
++	{0xce0010d4, 0x00000001},
++	{0xce002000, 0x00000044},
++	{0xce002004, 0x00040000},
++	{0xce002008, 0x20300050},
++	{0xce00200c, 0x00003467},
++	{0xce002010, 0x00430000},
++	{0xce002014, 0x20304015},
++	{0xce002018, 0x00390005},
++	{0xce00201c, 0x05555555},
++	{0xce002020, 0x00570057},
++	{0xce002024, 0x00570057},
++	{0xce002028, 0x00236700},
++	{0xce00202c, 0x000d1746},
++	{0xce002030, 0x05061787},
++	{0xce002034, 0x07800000},
++	{0xce00209c, 0x00900008},
++	{0xce0020a0, 0x00000000},
++	{0xce0023f8, 0x00000000},
++	{0xce0023fc, 0x00000001},
++	{0xce0030a4, 0x00001901},
++	{0xce0030b8, 0x5d08908e},
++	{0xce004000, 0x00000044},
++	{0xce004004, 0x00750075},
++	{0xce004008, 0x00000075},
++	{0xce00400c, 0x10000075},
++	{0xce004010, 0x3F384905},
++	{0xce004014, 0x40182000},
++	{0xce004018, 0x20600000},
++	{0xce00401c, 0x0C010120},
++	{0xce004020, 0x50505050},
++	{0xce004024, 0x50000000},
++	{0xce004028, 0x50505050},
++	{0xce00402c, 0x506070A0},
++	{0xce004030, 0xF0000000},
++	{0xce004034, 0x00002424},
++	{0xce004038, 0x00001420},
++	{0xce00409c, 0x0000300A},
++	{0xce0040c0, 0x20000280},
++	{0xce0040c4, 0x30023002},
++	{0xce0040c8, 0x0000003a},
++	{0xce004130, 0x40000000},
++	{0xce004164, 0x009C007E},
++	{0xce004180, 0x00044400},
++	{0xce004188, 0x82000000},
++	{0xce004190, 0x00000000},
++	{0xce004194, 0xffffffff},
++	{0xce004380, 0x00700010},
++	{0xce004384, 0x00007575},
++	{0xce004388, 0x0001fe3e},
++	{0xce00438c, 0x0000fe3e},
++	{0xce0043f8, 0x00000001},
++	{0xce007000, 0x00000000},
++	{0xce007004, 0x00008000},
++	{0xce007008, 0x00000000},
++	{0xce00700c, 0x00000000},
++	{0xce007010, 0x00000000},
++	{0xce007014, 0x00000000},
++	{0xce007018, 0x00000000},
++	{0xce00701c, 0x00000000},
++	{0xce007020, 0x00000000},
++	{0xce007024, 0x00000000},
++	{0xce007028, 0x00000000},
++	{0xce00702c, 0x00000000},
++	{0xce007030, 0x00000000},
++	{0xce007034, 0x00000000},
++	{0xce007038, 0x00000000},
++	{0xce00703c, 0x00000000},
++	{0xce007040, 0x02000200},
++	{0xce007048, 0x00000000},
++	{0xce00704c, 0x00000000},
++	{0xce007050, 0x00000000},
++	{0xce007054, 0x00000000},
++	{0xce007058, 0x000028ff},
++	{0xce00705c, 0x00000000},
++	{0xce007060, 0x00000000},
++	{0xce007064, 0x00000000},
++	{0xce007068, 0x00000000},
++	{0xce00706c, 0x00000202},
++	{0xce007070, 0x80ffc200},
++	{0xce007074, 0x00000000},
++	{0xce007078, 0x00000000},
++	{0xce00707c, 0x00000000},
++	{0xce007080, 0x00000000},
++	{0xce007084, 0x00000000},
++	{0xce007088, 0x00000000},
++	{0xce00708c, 0x00000000},
++	{0xce007090, 0x00000000},
++	{0xce007094, 0x00000000},
++	{0xce007098, 0x00000000},
++	{0xce00709c, 0x00000000},
++	{0xce0070a0, 0x00000000},
++	{0xce0070a4, 0x00000000},
++	{0xce0070a8, 0x00000000},
++	{0xce0070ac, 0x00000000},
++	{0xce0070b0, 0x00000000},
++	{0xce0070b4, 0x00000000},
++	{0xce0070b8, 0x00000000},
++	{0xce0070bc, 0x00000000},
++	{0xce0070c0, 0x00000000},
++	{0xce0070c4, 0x00000000},
++	{0xce0070c8, 0x00000000},
++	{0xce0070cc, 0x00000000},
++	{0xce0070d0, 0x00000000},
++	{0xce0070d4, 0x00000000},
++	{0xce0070d8, 0x00000000},
++	{0xce0070dc, 0x00000000},
++	{0xce0070e0, 0x00000000},
++	{0xce0070e4, 0x00000000},
++	{0xce0070e8, 0x00000000},
++	{0xce0070ec, 0x00000000},
++	{0xce0070f0, 0x00000000},
++	{0xce0070f4, 0x00000000},
++	{0xce0070f8, 0x00000000},
++	{0xce0070fc, 0x00000000},
++	{0xce007100, 0x00000000},
++	{0xce007104, 0x00000000},
++	{0xce007108, 0x00000000},
++	{0xce00710c, 0x00000000},
++	{0xce007110, 0x00000000},
++	{0xce007114, 0x00000000},
++	{0xce007118, 0x00000000},
++	{0xce00711c, 0x00000000},
++	{0xce007120, 0x02000200},
++	{0xce007124, 0x02000200},
++	{0xce007128, 0x02000200},
++	{0xce00712c, 0x02000200},
++	{0xce007130, 0x02000200},
++	{0xce007134, 0x02000200},
++	{0xce007138, 0x02000200},
++	{0xce00713c, 0x02000200},
++	{0xce007140, 0x02000200},
++	{0xce007144, 0x02000200},
++	{0xce007148, 0x02000200},
++	{0xce00714c, 0x02000200},
++	{0xce007150, 0x02000200},
++	{0xce007154, 0x02000200},
++	{0xce007158, 0x00000000},
++	{0xce00715c, 0x00000000},
++	{0xce007160, 0x00000000},
++	{0xce007164, 0x00000000},
++	{0xce007168, 0x00000000},
++	{0xce00716c, 0x00000000},
++	{0xce007170, 0x00000000},
++	{0xce007174, 0x00000000},
++	{0xce007178, 0x00000000},
++	{0xce00717c, 0x00000000},
++	{0xce007180, 0x00000000},
++	{0xce007184, 0x00000000},
++	{0xce007188, 0x00000000},
++	{0xce00718c, 0x00000000},
++	{0xce007190, 0x00000000},
++	{0xce007194, 0x00000000},
++	{0xce007198, 0x00000000},
++	{0xce00719c, 0x00000000},
++	{0xce0071a0, 0x00000000},
++	{0xce0071a4, 0x00000000},
++	{0xce0071a8, 0x00000000},
++	{0xce0071ac, 0x00000000},
++	{0xce0071b0, 0x00000000},
++	{0xce0071b4, 0x00000100},
++	{0xce0071b8, 0x00000000},
++	{0xce0071c0, 0x00000000},
++	{0xce0071c4, 0x00000000},
++	{0xce0071c8, 0x00000000},
++	{0xce0071cc, 0x00000000},
++	{0xce0071d0, 0x00000000},
++	{0xce0071d4, 0x00000000},
++	{0xce0071d8, 0x00000000},
++	{0xce0071dc, 0x00000000},
++	{0xce0071e0, 0x00000000},
++	{0xce0071e4, 0x00000000},
++	{0xce0071e8, 0x00000000},
++	{0xce0071ec, 0x00000000},
++	{0xce0071f0, 0x00000000},
++	{0xce0071f4, 0x00000000},
++	{0xce0071f8, 0x00000000},
++	{0xce0071fc, 0x00000000},
++	{0xce0043fc, 0x000104E5},
++	{0xce007044, 0x00028080},
++	{0xce000000, 0x80000016},
++};
++
++static const u32 wifi_tx_gain[] = {
++	0x79807980,
++	0x72797279,
++	0x6C726C72,
++	0x666C666C,
++	0x60666066,
++	0x5B605B60,
++	0x565B565B,
++	0x51565156,
++	0x4C514C51,
++	0x484C484C,
++	0x44484448,
++	0x40444044,
++	0x3C403C40,
++	0x3A3D3A3D,
++	0x36393639,
++};
++
++static ssv_cabrio_reg asic_rf_setting[] = {
++	{0xCE010038, 0x0003E07C},
++	{0xCE010060, 0x00406000},
++	{0xCE01009C, 0x00000024},
++	{0xCE0100A0, 0x00EC4CC5},
++	{0xCE010000, 0x40002000},
++	{0xCE010004, 0x00020FC0},
++	{0xCE010008, 0x000DF69B},
++	{0xCE010014, 0x3D3E84FE},
++	{0xCE010018, 0x01457D79},
++	{0xCE01001C, 0x000103A7},
++	{0xCE010020, 0x000103A6},
++	{0xCE01002C, 0x00032CA8},
++	{0xCE010048, 0xFCCCCF27},
++	{0xCE010050, 0x00444000},
++	{0xCE01000C, 0x151558C5},
++	{0xCE010010, 0x01011A88},
++	{0xCE010024, 0x00012001},
++	{0xCE010028, 0x00036000},
++	{0xCE010030, 0x20EA0224},
++	{0xCE010034, 0x44000755},
++	{0xCE01003C, 0x55D89D8A},
++	{0xCE010040, 0x005508BB},
++	{0xCE010044, 0x07C08BFF},
++	{0xCE01004C, 0x07700830},
++	{0xCE010054, 0x00007FF4},
++	{0xCE010058, 0x0000000E},
++	{0xCE01005C, 0x00088018},
++	{0xCE010064, 0x08820820},
++	{0xCE010068, 0x00820820},
++	{0xCE01006C, 0x00820820},
++	{0xCE010070, 0x00820820},
++	{0xCE010074, 0x00820820},
++	{0xCE010078, 0x00820820},
++	{0xCE01007C, 0x00820820},
++	{0xCE010080, 0x00820820},
++	{0xCE010084, 0x00004080},
++	{0xCE010088, 0x200800FE},
++	{0xCE01008C, 0xAAAAAAAA},
++	{0xCE010090, 0xAAAAAAAA},
++	{0xCE010094, 0x0000A487},
++	{0xCE010098, 0x0000070E},
++	{0xCE0100A4, 0x00000F43},
++	{0xCE0100A8, 0x00098900},
++	{0xCE0100AC, 0x00000000},
++	{0xC00003AC, 0x00000000},
++	{0xC00003B0, 0x00000000},
++	{0xC00003B4, 0x00000000},
++	{0xC00003BC, 0x00000000},
++	{0xC0001D00, 0x5E000040},
++	{0xC0001D04, 0x015D015D},
++	{0xC0001D08, 0x00000001},
++	{0xC0001D0C, 0x55550000},
++	{0xC0001D20, 0x7FFF0000},
++	{0xC0001D24, 0x00000003},
++	{0xC0001D28, 0x00000000},
++	{0xC0001D2C, 0x00000000},
++};
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
+new file mode 100644
+index 000000000000..d4a99b25d61f
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
+@@ -0,0 +1,9694 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define SYS_REG_BASE 0xc0000000
++#define WBOOT_REG_BASE 0xc0000100
++#define TU0_US_REG_BASE 0xc0000200
++#define TU1_US_REG_BASE 0xc0000210
++#define TU2_US_REG_BASE 0xc0000220
++#define TU3_US_REG_BASE 0xc0000230
++#define TM0_MS_REG_BASE 0xc0000240
++#define TM1_MS_REG_BASE 0xc0000250
++#define TM2_MS_REG_BASE 0xc0000260
++#define TM3_MS_REG_BASE 0xc0000270
++#define MCU_WDT_REG_BASE 0xc0000280
++#define SYS_WDT_REG_BASE 0xc0000284
++#define GPIO_REG_BASE 0xc0000300
++#define SD_REG_BASE 0xc0000800
++#define SPI_REG_BASE 0xc0000a00
++#define CSR_I2C_MST_BASE 0xc0000b00
++#define UART_REG_BASE 0xc0000c00
++#define DAT_UART_REG_BASE 0xc0000d00
++#define INT_REG_BASE 0xc0000e00
++#define DBG_SPI_REG_BASE 0xc0000f00
++#define FLASH_SPI_REG_BASE 0xc0001000
++#define DMA_REG_BASE 0xc0001c00
++#define CSR_PMU_BASE 0xc0001d00
++#define CSR_RTC_BASE 0xc0001d20
++#define RTC_RAM_BASE 0xc0001d80
++#define D2_DMA_REG_BASE 0xc0001e00
++#define HCI_REG_BASE 0xc1000000
++#define CO_REG_BASE 0xc2000000
++#define EFS_REG_BASE 0xc2000100
++#define SMS4_REG_BASE 0xc3000000
++#define MRX_REG_BASE 0xc6000000
++#define AMPDU_REG_BASE 0xc6001000
++#define MT_REG_CSR_BASE 0xc6002000
++#define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100
++#define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200
++#define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300
++#define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400
++#define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500
++#define HIF_INFO_BASE 0xca000000
++#define PHY_RATE_INFO_BASE 0xca000200
++#define MAC_GLB_SET_BASE 0xca000300
++#define BTCX_REG_BASE 0xca000400
++#define MIB_REG_BASE 0xca000800
++#define CBR_A_REG_BASE 0xcb000000
++#define MB_REG_BASE 0xcd000000
++#define ID_MNG_REG_BASE 0xcd010000
++#define CSR_PHY_BASE 0xce000000
++#define CSR_RF_BASE 0xce010000
++#define MMU_REG_BASE 0xcf000000
++#define SYS_REG_BANK_SIZE 0x000000b4
++#define WBOOT_REG_BANK_SIZE 0x0000000c
++#define TU0_US_REG_BANK_SIZE 0x00000010
++#define TU1_US_REG_BANK_SIZE 0x00000010
++#define TU2_US_REG_BANK_SIZE 0x00000010
++#define TU3_US_REG_BANK_SIZE 0x00000010
++#define TM0_MS_REG_BANK_SIZE 0x00000010
++#define TM1_MS_REG_BANK_SIZE 0x00000010
++#define TM2_MS_REG_BANK_SIZE 0x00000010
++#define TM3_MS_REG_BANK_SIZE 0x00000010
++#define MCU_WDT_REG_BANK_SIZE 0x00000004
++#define SYS_WDT_REG_BANK_SIZE 0x00000004
++#define GPIO_REG_BANK_SIZE 0x000000d4
++#define SD_REG_BANK_SIZE 0x00000180
++#define SPI_REG_BANK_SIZE 0x00000040
++#define CSR_I2C_MST_BANK_SIZE 0x00000018
++#define UART_REG_BANK_SIZE 0x00000028
++#define DAT_UART_REG_BANK_SIZE 0x00000028
++#define INT_REG_BANK_SIZE 0x0000004c
++#define DBG_SPI_REG_BANK_SIZE 0x00000040
++#define FLASH_SPI_REG_BANK_SIZE 0x0000002c
++#define DMA_REG_BANK_SIZE 0x00000014
++#define CSR_PMU_BANK_SIZE 0x00000100
++#define CSR_RTC_BANK_SIZE 0x000000e0
++#define RTC_RAM_BANK_SIZE 0x00000080
++#define D2_DMA_REG_BANK_SIZE 0x00000014
++#define HCI_REG_BANK_SIZE 0x000000cc
++#define CO_REG_BANK_SIZE 0x000000ac
++#define EFS_REG_BANK_SIZE 0x0000006c
++#define SMS4_REG_BANK_SIZE 0x00000070
++#define MRX_REG_BANK_SIZE 0x00000198
++#define AMPDU_REG_BANK_SIZE 0x00000014
++#define MT_REG_CSR_BANK_SIZE 0x00000100
++#define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define HIF_INFO_BANK_SIZE 0x0000009c
++#define PHY_RATE_INFO_BANK_SIZE 0x000000b8
++#define MAC_GLB_SET_BANK_SIZE 0x0000003c
++#define BTCX_REG_BANK_SIZE 0x0000000c
++#define MIB_REG_BANK_SIZE 0x00000480
++#define CBR_A_REG_BANK_SIZE 0x001203fc
++#define MB_REG_BANK_SIZE 0x000000a0
++#define ID_MNG_REG_BANK_SIZE 0x00000084
++#define CSR_PHY_BANK_SIZE 0x000071c0
++#define CSR_RF_BANK_SIZE 0x000000b0
++#define MMU_REG_BANK_SIZE 0x000000c0
++#define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000)
++#define ADR_BOOT (SYS_REG_BASE+0x00000004)
++#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
++#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
++#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
++#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
++#define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018)
++#define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c)
++#define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020)
++#define ADR_MCU_DBG_SEL (SYS_REG_BASE+0x00000024)
++#define ADR_MCU_DBG_DATA (SYS_REG_BASE+0x00000028)
++#define ADR_AHB_BRG_STATUS (SYS_REG_BASE+0x0000002c)
++#define ADR_BIST_BIST_CTRL (SYS_REG_BASE+0x00000030)
++#define ADR_BIST_MODE_REG_IN (SYS_REG_BASE+0x00000034)
++#define ADR_BIST_MODE_REG_OUT (SYS_REG_BASE+0x00000038)
++#define ADR_BIST_MONITOR_BUS_LSB (SYS_REG_BASE+0x0000003c)
++#define ADR_BIST_MONITOR_BUS_MSB (SYS_REG_BASE+0x00000040)
++#define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044)
++#define ADR_TB_RDATA (SYS_REG_BASE+0x00000048)
++#define ADR_UART_W2B (SYS_REG_BASE+0x0000004c)
++#define ADR_AHB_ILL_ADDR (SYS_REG_BASE+0x00000050)
++#define ADR_AHB_FEN_ADDR (SYS_REG_BASE+0x00000054)
++#define ADR_AHB_ILLFEN_STATUS (SYS_REG_BASE+0x00000058)
++#define ADR_PWM_A (SYS_REG_BASE+0x00000080)
++#define ADR_PWM_B (SYS_REG_BASE+0x00000084)
++#define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090)
++#define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094)
++#define ADR_PRESCALER_USTIMER (SYS_REG_BASE+0x000000a0)
++#define ADR_BIST_MODE_REG_IN_MMU (SYS_REG_BASE+0x000000a4)
++#define ADR_BIST_MODE_REG_OUT_MMU (SYS_REG_BASE+0x000000a8)
++#define ADR_BIST_MONITOR_BUS_MMU (SYS_REG_BASE+0x000000ac)
++#define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0)
++#define ADR_BOOT_INFO (WBOOT_REG_BASE+0x00000000)
++#define ADR_SD_INIT_CFG (WBOOT_REG_BASE+0x00000004)
++#define ADR_SPARE_UART_INFO (WBOOT_REG_BASE+0x00000008)
++#define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000)
++#define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004)
++#define ADR_TU0_DUMMY_BIT_0 (TU0_US_REG_BASE+0x00000008)
++#define ADR_TU0_DUMMY_BIT_1 (TU0_US_REG_BASE+0x0000000c)
++#define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000)
++#define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004)
++#define ADR_TU1_DUMMY_BIT_0 (TU1_US_REG_BASE+0x00000008)
++#define ADR_TU1_DUMMY_BIT_1 (TU1_US_REG_BASE+0x0000000c)
++#define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000)
++#define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004)
++#define ADR_TU2_DUMMY_BIT_0 (TU2_US_REG_BASE+0x00000008)
++#define ADR_TU2_DUMMY_BIT_1 (TU2_US_REG_BASE+0x0000000c)
++#define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000)
++#define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004)
++#define ADR_TU3_DUMMY_BIT_0 (TU3_US_REG_BASE+0x00000008)
++#define ADR_TU3_DUMMY_BIT_1 (TU3_US_REG_BASE+0x0000000c)
++#define ADR_TM0_MILISECOND_TIMER (TM0_MS_REG_BASE+0x00000000)
++#define ADR_TM0_CURRENT_MILISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004)
++#define ADR_TM0_DUMMY_BIT_0 (TM0_MS_REG_BASE+0x00000008)
++#define ADR_TM0_DUMMY_BIT_1 (TM0_MS_REG_BASE+0x0000000c)
++#define ADR_TM1_MILISECOND_TIMER (TM1_MS_REG_BASE+0x00000000)
++#define ADR_TM1_CURRENT_MILISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004)
++#define ADR_TM1_DUMMY_BIT_0 (TM1_MS_REG_BASE+0x00000008)
++#define ADR_TM1_DUMMY_BIT_1 (TM1_MS_REG_BASE+0x0000000c)
++#define ADR_TM2_MILISECOND_TIMER (TM2_MS_REG_BASE+0x00000000)
++#define ADR_TM2_CURRENT_MILISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004)
++#define ADR_TM2_DUMMY_BIT_0 (TM2_MS_REG_BASE+0x00000008)
++#define ADR_TM2_DUMMY_BIT_1 (TM2_MS_REG_BASE+0x0000000c)
++#define ADR_TM3_MILISECOND_TIMER (TM3_MS_REG_BASE+0x00000000)
++#define ADR_TM3_CURRENT_MILISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004)
++#define ADR_TM3_DUMMY_BIT_0 (TM3_MS_REG_BASE+0x00000008)
++#define ADR_TM3_DUMMY_BIT_1 (TM3_MS_REG_BASE+0x0000000c)
++#define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000)
++#define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000)
++#define ADR_PAD6 (GPIO_REG_BASE+0x00000000)
++#define ADR_PAD7 (GPIO_REG_BASE+0x00000004)
++#define ADR_PAD8 (GPIO_REG_BASE+0x00000008)
++#define ADR_PAD9 (GPIO_REG_BASE+0x0000000c)
++#define ADR_PAD11 (GPIO_REG_BASE+0x00000010)
++#define ADR_PAD15 (GPIO_REG_BASE+0x00000014)
++#define ADR_PAD16 (GPIO_REG_BASE+0x00000018)
++#define ADR_PAD17 (GPIO_REG_BASE+0x0000001c)
++#define ADR_PAD18 (GPIO_REG_BASE+0x00000020)
++#define ADR_PAD19 (GPIO_REG_BASE+0x00000024)
++#define ADR_PAD20 (GPIO_REG_BASE+0x00000028)
++#define ADR_PAD21 (GPIO_REG_BASE+0x0000002c)
++#define ADR_PAD22 (GPIO_REG_BASE+0x00000030)
++#define ADR_PAD24 (GPIO_REG_BASE+0x00000034)
++#define ADR_PAD25 (GPIO_REG_BASE+0x00000038)
++#define ADR_PAD27 (GPIO_REG_BASE+0x0000003c)
++#define ADR_PAD28 (GPIO_REG_BASE+0x00000040)
++#define ADR_PAD29 (GPIO_REG_BASE+0x00000044)
++#define ADR_PAD30 (GPIO_REG_BASE+0x00000048)
++#define ADR_PAD31 (GPIO_REG_BASE+0x0000004c)
++#define ADR_PAD32 (GPIO_REG_BASE+0x00000050)
++#define ADR_PAD33 (GPIO_REG_BASE+0x00000054)
++#define ADR_PAD34 (GPIO_REG_BASE+0x00000058)
++#define ADR_PAD42 (GPIO_REG_BASE+0x0000005c)
++#define ADR_PAD43 (GPIO_REG_BASE+0x00000060)
++#define ADR_PAD44 (GPIO_REG_BASE+0x00000064)
++#define ADR_PAD45 (GPIO_REG_BASE+0x00000068)
++#define ADR_PAD46 (GPIO_REG_BASE+0x0000006c)
++#define ADR_PAD47 (GPIO_REG_BASE+0x00000070)
++#define ADR_PAD48 (GPIO_REG_BASE+0x00000074)
++#define ADR_PAD49 (GPIO_REG_BASE+0x00000078)
++#define ADR_PAD50 (GPIO_REG_BASE+0x0000007c)
++#define ADR_PAD51 (GPIO_REG_BASE+0x00000080)
++#define ADR_PAD52 (GPIO_REG_BASE+0x00000084)
++#define ADR_PAD53 (GPIO_REG_BASE+0x00000088)
++#define ADR_PAD54 (GPIO_REG_BASE+0x0000008c)
++#define ADR_PAD56 (GPIO_REG_BASE+0x00000090)
++#define ADR_PAD57 (GPIO_REG_BASE+0x00000094)
++#define ADR_PAD58 (GPIO_REG_BASE+0x00000098)
++#define ADR_PAD59 (GPIO_REG_BASE+0x0000009c)
++#define ADR_PAD60 (GPIO_REG_BASE+0x000000a0)
++#define ADR_PAD61 (GPIO_REG_BASE+0x000000a4)
++#define ADR_PAD62 (GPIO_REG_BASE+0x000000a8)
++#define ADR_PAD64 (GPIO_REG_BASE+0x000000ac)
++#define ADR_PAD65 (GPIO_REG_BASE+0x000000b0)
++#define ADR_PAD66 (GPIO_REG_BASE+0x000000b4)
++#define ADR_PAD68 (GPIO_REG_BASE+0x000000b8)
++#define ADR_PAD67 (GPIO_REG_BASE+0x000000bc)
++#define ADR_PAD69 (GPIO_REG_BASE+0x000000c0)
++#define ADR_PAD70 (GPIO_REG_BASE+0x000000c4)
++#define ADR_PAD231 (GPIO_REG_BASE+0x000000c8)
++#define ADR_PIN_SEL_0 (GPIO_REG_BASE+0x000000cc)
++#define ADR_PIN_SEL_1 (GPIO_REG_BASE+0x000000d0)
++#define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000)
++#define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004)
++#define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008)
++#define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c)
++#define ADR_CARD_PKT_STATUS_TEST (SD_REG_BASE+0x00000010)
++#define ADR_SYSTEM_INFORMATION_REG (SD_REG_BASE+0x0000001c)
++#define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020)
++#define ADR_SDIO_FIFO_WR_THLD_REG (SD_REG_BASE+0x00000024)
++#define ADR_SDIO_FIFO_WR_LIMIT_REG (SD_REG_BASE+0x00000028)
++#define ADR_SDIO_TX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x0000002c)
++#define ADR_SDIO_THLD_FOR_CMD53RD_REG (SD_REG_BASE+0x00000030)
++#define ADR_SDIO_RX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x00000034)
++#define ADR_SDIO_LOG_START_END_DATA_REG (SD_REG_BASE+0x00000038)
++#define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040)
++#define ADR_SDIO_LAST_CMD_INDEX_CRC_REG (SD_REG_BASE+0x00000044)
++#define ADR_SDIO_LAST_CMD_ARG_REG (SD_REG_BASE+0x00000048)
++#define ADR_SDIO_BUS_STATE_DEBUG_MONITOR (SD_REG_BASE+0x0000004c)
++#define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050)
++#define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054)
++#define ADR_CMD52_DATA_FOR_LAST_TIME (SD_REG_BASE+0x0000005c)
++#define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060)
++#define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064)
++#define ADR_IO_REG_PORT_REG (SD_REG_BASE+0x00000070)
++#define ADR_SDIO_FIFO_ERROR_CNT (SD_REG_BASE+0x0000007c)
++#define ADR_SDIO_CRC7_CRC16_ERROR_REG (SD_REG_BASE+0x00000080)
++#define ADR_SDIO_BLOCK_CNT_INFO (SD_REG_BASE+0x00000084)
++#define ADR_RX_DATA_CMD52_ABORT_COUNT (SD_REG_BASE+0x0000008c)
++#define ADR_FIFO_PTR_READ_BLOCK_CNT (SD_REG_BASE+0x00000090)
++#define ADR_TX_TIME_OUT_READ_CTRL (SD_REG_BASE+0x00000094)
++#define ADR_SDIO_TX_ALLOC_REG (SD_REG_BASE+0x00000098)
++#define ADR_SDIO_TX_INFORM (SD_REG_BASE+0x0000009c)
++#define ADR_F1_BLOCK_SIZE_0_REG (SD_REG_BASE+0x000000a0)
++#define ADR_SDIO_COMMAND_LOG_DATA_31_0 (SD_REG_BASE+0x000000b0)
++#define ADR_SDIO_COMMAND_LOG_DATA_63_32 (SD_REG_BASE+0x000000b4)
++#define ADR_SYSTEM_INFORMATION_REGISTER (SD_REG_BASE+0x000000bc)
++#define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0)
++#define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4)
++#define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8)
++#define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0)
++#define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0)
++#define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8)
++#define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100)
++#define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104)
++#define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108)
++#define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c)
++#define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110)
++#define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114)
++#define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118)
++#define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c)
++#define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120)
++#define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124)
++#define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128)
++#define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c)
++#define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130)
++#define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134)
++#define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138)
++#define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c)
++#define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140)
++#define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144)
++#define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148)
++#define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c)
++#define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150)
++#define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154)
++#define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158)
++#define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c)
++#define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160)
++#define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164)
++#define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168)
++#define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c)
++#define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170)
++#define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174)
++#define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178)
++#define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c)
++#define ADR_SPI_MODE (SPI_REG_BASE+0x00000000)
++#define ADR_RX_QUOTA (SPI_REG_BASE+0x00000004)
++#define ADR_CONDITION_NUMBER (SPI_REG_BASE+0x00000008)
++#define ADR_HOST_PATH (SPI_REG_BASE+0x0000000c)
++#define ADR_TX_SEG (SPI_REG_BASE+0x00000010)
++#define ADR_DEBUG_BURST_MODE (SPI_REG_BASE+0x00000014)
++#define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018)
++#define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c)
++#define ADR_SPI_STS (SPI_REG_BASE+0x00000020)
++#define ADR_TX_ALLOC_SET (SPI_REG_BASE+0x00000024)
++#define ADR_TX_ALLOC (SPI_REG_BASE+0x00000028)
++#define ADR_DBG_CNT (SPI_REG_BASE+0x0000002c)
++#define ADR_DBG_CNT2 (SPI_REG_BASE+0x00000030)
++#define ADR_DBG_CNT3 (SPI_REG_BASE+0x00000034)
++#define ADR_DBG_CNT4 (SPI_REG_BASE+0x00000038)
++#define ADR_INT_TAG (SPI_REG_BASE+0x0000003c)
++#define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000000)
++#define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000004)
++#define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x00000008)
++#define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x0000000c)
++#define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000010)
++#define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000014)
++#define ADR_UART_DATA (UART_REG_BASE+0x00000000)
++#define ADR_UART_IER (UART_REG_BASE+0x00000004)
++#define ADR_UART_FCR (UART_REG_BASE+0x00000008)
++#define ADR_UART_LCR (UART_REG_BASE+0x0000000c)
++#define ADR_UART_MCR (UART_REG_BASE+0x00000010)
++#define ADR_UART_LSR (UART_REG_BASE+0x00000014)
++#define ADR_UART_MSR (UART_REG_BASE+0x00000018)
++#define ADR_UART_SPR (UART_REG_BASE+0x0000001c)
++#define ADR_UART_RTHR (UART_REG_BASE+0x00000020)
++#define ADR_UART_ISR (UART_REG_BASE+0x00000024)
++#define ADR_DAT_UART_DATA (DAT_UART_REG_BASE+0x00000000)
++#define ADR_DAT_UART_IER (DAT_UART_REG_BASE+0x00000004)
++#define ADR_DAT_UART_FCR (DAT_UART_REG_BASE+0x00000008)
++#define ADR_DAT_UART_LCR (DAT_UART_REG_BASE+0x0000000c)
++#define ADR_DAT_UART_MCR (DAT_UART_REG_BASE+0x00000010)
++#define ADR_DAT_UART_LSR (DAT_UART_REG_BASE+0x00000014)
++#define ADR_DAT_UART_MSR (DAT_UART_REG_BASE+0x00000018)
++#define ADR_DAT_UART_SPR (DAT_UART_REG_BASE+0x0000001c)
++#define ADR_DAT_UART_RTHR (DAT_UART_REG_BASE+0x00000020)
++#define ADR_DAT_UART_ISR (DAT_UART_REG_BASE+0x00000024)
++#define ADR_INT_MASK (INT_REG_BASE+0x00000000)
++#define ADR_INT_MODE (INT_REG_BASE+0x00000004)
++#define ADR_INT_IRQ_STS (INT_REG_BASE+0x00000008)
++#define ADR_INT_FIQ_STS (INT_REG_BASE+0x0000000c)
++#define ADR_INT_IRQ_RAW (INT_REG_BASE+0x00000010)
++#define ADR_INT_FIQ_RAW (INT_REG_BASE+0x00000014)
++#define ADR_INT_PERI_MASK (INT_REG_BASE+0x00000018)
++#define ADR_INT_PERI_STS (INT_REG_BASE+0x0000001c)
++#define ADR_INT_PERI_RAW (INT_REG_BASE+0x00000020)
++#define ADR_INT_GPI_CFG (INT_REG_BASE+0x00000024)
++#define ADR_SYS_INT_FOR_HOST (INT_REG_BASE+0x00000028)
++#define ADR_SPI_IPC (INT_REG_BASE+0x00000034)
++#define ADR_SDIO_IPC (INT_REG_BASE+0x00000038)
++#define ADR_SDIO_MASK (INT_REG_BASE+0x0000003c)
++#define ADR_SDIO_IRQ_STS (INT_REG_BASE+0x00000040)
++#define ADR_SD_PERI_MASK (INT_REG_BASE+0x00000044)
++#define ADR_SD_PERI_STS (INT_REG_BASE+0x00000048)
++#define ADR_DBG_SPI_MODE (DBG_SPI_REG_BASE+0x00000000)
++#define ADR_DBG_RX_QUOTA (DBG_SPI_REG_BASE+0x00000004)
++#define ADR_DBG_CONDITION_NUMBER (DBG_SPI_REG_BASE+0x00000008)
++#define ADR_DBG_HOST_PATH (DBG_SPI_REG_BASE+0x0000000c)
++#define ADR_DBG_TX_SEG (DBG_SPI_REG_BASE+0x00000010)
++#define ADR_DBG_DEBUG_BURST_MODE (DBG_SPI_REG_BASE+0x00000014)
++#define ADR_DBG_SPI_TO_PHY_PARAM1 (DBG_SPI_REG_BASE+0x00000018)
++#define ADR_DBG_SPI_TO_PHY_PARAM2 (DBG_SPI_REG_BASE+0x0000001c)
++#define ADR_DBG_SPI_STS (DBG_SPI_REG_BASE+0x00000020)
++#define ADR_DBG_TX_ALLOC_SET (DBG_SPI_REG_BASE+0x00000024)
++#define ADR_DBG_TX_ALLOC (DBG_SPI_REG_BASE+0x00000028)
++#define ADR_DBG_DBG_CNT (DBG_SPI_REG_BASE+0x0000002c)
++#define ADR_DBG_DBG_CNT2 (DBG_SPI_REG_BASE+0x00000030)
++#define ADR_DBG_DBG_CNT3 (DBG_SPI_REG_BASE+0x00000034)
++#define ADR_DBG_DBG_CNT4 (DBG_SPI_REG_BASE+0x00000038)
++#define ADR_DBG_INT_TAG (DBG_SPI_REG_BASE+0x0000003c)
++#define ADR_BOOT_ADDR (FLASH_SPI_REG_BASE+0x00000000)
++#define ADR_VERIFY_DATA (FLASH_SPI_REG_BASE+0x00000004)
++#define ADR_FLASH_ADDR (FLASH_SPI_REG_BASE+0x00000008)
++#define ADR_SRAM_ADDR (FLASH_SPI_REG_BASE+0x0000000c)
++#define ADR_LEN (FLASH_SPI_REG_BASE+0x00000010)
++#define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000014)
++#define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x00000018)
++#define ADR_CHECK_SUM_RESULT (FLASH_SPI_REG_BASE+0x0000001c)
++#define ADR_CHECK_SUM_IN_FILE (FLASH_SPI_REG_BASE+0x00000020)
++#define ADR_COMMAND_LEN (FLASH_SPI_REG_BASE+0x00000024)
++#define ADR_COMMAND_ADDR (FLASH_SPI_REG_BASE+0x00000028)
++#define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000)
++#define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004)
++#define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008)
++#define ADR_DMA_INT (DMA_REG_BASE+0x0000000c)
++#define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010)
++#define ADR_PMU_0 (CSR_PMU_BASE+0x00000000)
++#define ADR_PMU_1 (CSR_PMU_BASE+0x00000004)
++#define ADR_PMU_2 (CSR_PMU_BASE+0x00000008)
++#define ADR_PMU_3 (CSR_PMU_BASE+0x0000000c)
++#define ADR_RTC_1 (CSR_RTC_BASE+0x00000000)
++#define ADR_RTC_2 (CSR_RTC_BASE+0x00000004)
++#define ADR_RTC_3W (CSR_RTC_BASE+0x00000008)
++#define ADR_RTC_3R (CSR_RTC_BASE+0x00000008)
++#define ADR_RTC_4 (CSR_RTC_BASE+0x0000000c)
++#define ADR_RTC_RAM (RTC_RAM_BASE+0x00000000)
++#define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000)
++#define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004)
++#define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008)
++#define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c)
++#define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010)
++#define ADR_CONTROL (HCI_REG_BASE+0x00000000)
++#define ADR_SDIO_WAKE_MODE (HCI_REG_BASE+0x00000004)
++#define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008)
++#define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c)
++#define ADR_THREASHOLD (HCI_REG_BASE+0x00000018)
++#define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020)
++#define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028)
++#define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030)
++#define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034)
++#define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050)
++#define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054)
++#define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060)
++#define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064)
++#define ADR_PACKET_COUNTER_INFO_0 (HCI_REG_BASE+0x00000070)
++#define ADR_PACKET_COUNTER_INFO_1 (HCI_REG_BASE+0x00000074)
++#define ADR_PACKET_COUNTER_INFO_2 (HCI_REG_BASE+0x00000078)
++#define ADR_PACKET_COUNTER_INFO_3 (HCI_REG_BASE+0x0000007c)
++#define ADR_PACKET_COUNTER_INFO_4 (HCI_REG_BASE+0x00000080)
++#define ADR_PACKET_COUNTER_INFO_5 (HCI_REG_BASE+0x00000084)
++#define ADR_PACKET_COUNTER_INFO_6 (HCI_REG_BASE+0x00000088)
++#define ADR_PACKET_COUNTER_INFO_7 (HCI_REG_BASE+0x0000008c)
++#define ADR_SDIO_TX_RX_FAIL_COUNTER_0 (HCI_REG_BASE+0x00000090)
++#define ADR_SDIO_TX_RX_FAIL_COUNTER_1 (HCI_REG_BASE+0x00000094)
++#define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a0)
++#define ADR_HCI_STATE_DEBUG_MODE_1 (HCI_REG_BASE+0x000000a4)
++#define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000a8)
++#define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000ac)
++#define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b0)
++#define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000b4)
++#define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000b8)
++#define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000bc)
++#define ADR_HCI_STATE_DEBUG_MODE_8 (HCI_REG_BASE+0x000000c0)
++#define ADR_HCI_STATE_DEBUG_MODE_9 (HCI_REG_BASE+0x000000c4)
++#define ADR_HCI_STATE_DEBUG_MODE_10 (HCI_REG_BASE+0x000000c8)
++#define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000)
++#define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004)
++#define ADR_CS_CMD (CO_REG_BASE+0x00000008)
++#define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c)
++#define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010)
++#define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014)
++#define ADR_RAND_EN (CO_REG_BASE+0x00000018)
++#define ADR_RAND_NUM (CO_REG_BASE+0x0000001c)
++#define ADR_MUL_OP1 (CO_REG_BASE+0x00000060)
++#define ADR_MUL_OP2 (CO_REG_BASE+0x00000064)
++#define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068)
++#define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c)
++#define ADR_DMA_RDATA (CO_REG_BASE+0x00000070)
++#define ADR_DMA_WDATA (CO_REG_BASE+0x00000074)
++#define ADR_DMA_LEN (CO_REG_BASE+0x00000078)
++#define ADR_DMA_CLR (CO_REG_BASE+0x0000007c)
++#define ADR_NAV_DATA (CO_REG_BASE+0x00000080)
++#define ADR_CO_NAV (CO_REG_BASE+0x00000084)
++#define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0)
++#define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4)
++#define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8)
++#define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000)
++#define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004)
++#define ADR_EFUSE_AHB_RDATA_0 (EFS_REG_BASE+0x00000008)
++#define ADR_EFUSE_WDATA_0 (EFS_REG_BASE+0x00000008)
++#define ADR_EFUSE_AHB_RDATA_1 (EFS_REG_BASE+0x0000000c)
++#define ADR_EFUSE_WDATA_1 (EFS_REG_BASE+0x0000000c)
++#define ADR_EFUSE_AHB_RDATA_2 (EFS_REG_BASE+0x00000010)
++#define ADR_EFUSE_WDATA_2 (EFS_REG_BASE+0x00000010)
++#define ADR_EFUSE_AHB_RDATA_3 (EFS_REG_BASE+0x00000014)
++#define ADR_EFUSE_WDATA_3 (EFS_REG_BASE+0x00000014)
++#define ADR_EFUSE_AHB_RDATA_4 (EFS_REG_BASE+0x00000018)
++#define ADR_EFUSE_WDATA_4 (EFS_REG_BASE+0x00000018)
++#define ADR_EFUSE_AHB_RDATA_5 (EFS_REG_BASE+0x0000001c)
++#define ADR_EFUSE_WDATA_5 (EFS_REG_BASE+0x0000001c)
++#define ADR_EFUSE_AHB_RDATA_6 (EFS_REG_BASE+0x00000020)
++#define ADR_EFUSE_WDATA_6 (EFS_REG_BASE+0x00000020)
++#define ADR_EFUSE_AHB_RDATA_7 (EFS_REG_BASE+0x00000024)
++#define ADR_EFUSE_WDATA_7 (EFS_REG_BASE+0x00000024)
++#define ADR_EFUSE_SPI_RD0_EN (EFS_REG_BASE+0x00000028)
++#define ADR_EFUSE_SPI_RD1_EN (EFS_REG_BASE+0x0000002c)
++#define ADR_EFUSE_SPI_RD2_EN (EFS_REG_BASE+0x00000030)
++#define ADR_EFUSE_SPI_RD3_EN (EFS_REG_BASE+0x00000034)
++#define ADR_EFUSE_SPI_RD4_EN (EFS_REG_BASE+0x00000038)
++#define ADR_EFUSE_SPI_RD5_EN (EFS_REG_BASE+0x0000003c)
++#define ADR_EFUSE_SPI_RD6_EN (EFS_REG_BASE+0x00000040)
++#define ADR_EFUSE_SPI_RD7_EN (EFS_REG_BASE+0x00000044)
++#define ADR_EFUSE_SPI_BUSY (EFS_REG_BASE+0x00000048)
++#define ADR_EFUSE_SPI_RDATA_0 (EFS_REG_BASE+0x0000004c)
++#define ADR_EFUSE_SPI_RDATA_1 (EFS_REG_BASE+0x00000050)
++#define ADR_EFUSE_SPI_RDATA_2 (EFS_REG_BASE+0x00000054)
++#define ADR_EFUSE_SPI_RDATA_3 (EFS_REG_BASE+0x00000058)
++#define ADR_EFUSE_SPI_RDATA_4 (EFS_REG_BASE+0x0000005c)
++#define ADR_EFUSE_SPI_RDATA_5 (EFS_REG_BASE+0x00000060)
++#define ADR_EFUSE_SPI_RDATA_6 (EFS_REG_BASE+0x00000064)
++#define ADR_EFUSE_SPI_RDATA_7 (EFS_REG_BASE+0x00000068)
++#define ADR_SMS4_CFG1 (SMS4_REG_BASE+0x00000000)
++#define ADR_SMS4_CFG2 (SMS4_REG_BASE+0x00000004)
++#define ADR_SMS4_MODE1 (SMS4_REG_BASE+0x00000008)
++#define ADR_SMS4_TRIG (SMS4_REG_BASE+0x00000010)
++#define ADR_SMS4_STATUS1 (SMS4_REG_BASE+0x00000014)
++#define ADR_SMS4_STATUS2 (SMS4_REG_BASE+0x00000018)
++#define ADR_SMS4_DATA_IN0 (SMS4_REG_BASE+0x00000020)
++#define ADR_SMS4_DATA_IN1 (SMS4_REG_BASE+0x00000024)
++#define ADR_SMS4_DATA_IN2 (SMS4_REG_BASE+0x00000028)
++#define ADR_SMS4_DATA_IN3 (SMS4_REG_BASE+0x0000002c)
++#define ADR_SMS4_DATA_OUT0 (SMS4_REG_BASE+0x00000030)
++#define ADR_SMS4_DATA_OUT1 (SMS4_REG_BASE+0x00000034)
++#define ADR_SMS4_DATA_OUT2 (SMS4_REG_BASE+0x00000038)
++#define ADR_SMS4_DATA_OUT3 (SMS4_REG_BASE+0x0000003c)
++#define ADR_SMS4_KEY_0 (SMS4_REG_BASE+0x00000040)
++#define ADR_SMS4_KEY_1 (SMS4_REG_BASE+0x00000044)
++#define ADR_SMS4_KEY_2 (SMS4_REG_BASE+0x00000048)
++#define ADR_SMS4_KEY_3 (SMS4_REG_BASE+0x0000004c)
++#define ADR_SMS4_MODE_IV0 (SMS4_REG_BASE+0x00000050)
++#define ADR_SMS4_MODE_IV1 (SMS4_REG_BASE+0x00000054)
++#define ADR_SMS4_MODE_IV2 (SMS4_REG_BASE+0x00000058)
++#define ADR_SMS4_MODE_IV3 (SMS4_REG_BASE+0x0000005c)
++#define ADR_SMS4_OFB_ENC0 (SMS4_REG_BASE+0x00000060)
++#define ADR_SMS4_OFB_ENC1 (SMS4_REG_BASE+0x00000064)
++#define ADR_SMS4_OFB_ENC2 (SMS4_REG_BASE+0x00000068)
++#define ADR_SMS4_OFB_ENC3 (SMS4_REG_BASE+0x0000006c)
++#define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000)
++#define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004)
++#define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008)
++#define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c)
++#define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010)
++#define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014)
++#define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018)
++#define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c)
++#define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020)
++#define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024)
++#define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028)
++#define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c)
++#define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030)
++#define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034)
++#define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038)
++#define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c)
++#define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040)
++#define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044)
++#define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048)
++#define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c)
++#define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050)
++#define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054)
++#define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070)
++#define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074)
++#define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078)
++#define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c)
++#define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080)
++#define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084)
++#define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088)
++#define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c)
++#define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090)
++#define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094)
++#define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098)
++#define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c)
++#define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0)
++#define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4)
++#define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8)
++#define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac)
++#define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0)
++#define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4)
++#define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8)
++#define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc)
++#define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0)
++#define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4)
++#define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8)
++#define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc)
++#define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0)
++#define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4)
++#define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0)
++#define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4)
++#define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8)
++#define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec)
++#define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0)
++#define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4)
++#define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8)
++#define ADR_BA_CTRL (MRX_REG_BASE+0x00000100)
++#define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104)
++#define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108)
++#define ADR_BA_TID (MRX_REG_BASE+0x0000010c)
++#define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110)
++#define ADR_BA_SB0 (MRX_REG_BASE+0x00000114)
++#define ADR_BA_SB1 (MRX_REG_BASE+0x00000118)
++#define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c)
++#define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120)
++#define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124)
++#define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128)
++#define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c)
++#define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130)
++#define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134)
++#define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138)
++#define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c)
++#define ADR_WSID0_TID0_RX_SEQ (MRX_REG_BASE+0x00000140)
++#define ADR_WSID0_TID1_RX_SEQ (MRX_REG_BASE+0x00000144)
++#define ADR_WSID0_TID2_RX_SEQ (MRX_REG_BASE+0x00000148)
++#define ADR_WSID0_TID3_RX_SEQ (MRX_REG_BASE+0x0000014c)
++#define ADR_WSID0_TID4_RX_SEQ (MRX_REG_BASE+0x00000150)
++#define ADR_WSID0_TID5_RX_SEQ (MRX_REG_BASE+0x00000154)
++#define ADR_WSID0_TID6_RX_SEQ (MRX_REG_BASE+0x00000158)
++#define ADR_WSID0_TID7_RX_SEQ (MRX_REG_BASE+0x0000015c)
++#define ADR_WSID1_TID0_RX_SEQ (MRX_REG_BASE+0x00000170)
++#define ADR_WSID1_TID1_RX_SEQ (MRX_REG_BASE+0x00000174)
++#define ADR_WSID1_TID2_RX_SEQ (MRX_REG_BASE+0x00000178)
++#define ADR_WSID1_TID3_RX_SEQ (MRX_REG_BASE+0x0000017c)
++#define ADR_WSID1_TID4_RX_SEQ (MRX_REG_BASE+0x00000180)
++#define ADR_WSID1_TID5_RX_SEQ (MRX_REG_BASE+0x00000184)
++#define ADR_WSID1_TID6_RX_SEQ (MRX_REG_BASE+0x00000188)
++#define ADR_WSID1_TID7_RX_SEQ (MRX_REG_BASE+0x0000018c)
++#define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000190)
++#define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000194)
++#define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000)
++#define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004)
++#define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008)
++#define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c)
++#define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010)
++#define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000)
++#define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004)
++#define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008)
++#define ADR_MTX_EDCCA_TOUT (MT_REG_CSR_BASE+0x00000010)
++#define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0)
++#define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4)
++#define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8)
++#define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac)
++#define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0)
++#define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4)
++#define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8)
++#define ADR_MTX_BCN_CFG0 (MT_REG_CSR_BASE+0x000000bc)
++#define ADR_MTX_BCN_CFG1 (MT_REG_CSR_BASE+0x000000c0)
++#define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc)
++#define ADR_MTX_DBG_CTRL (MT_REG_CSR_BASE+0x000000d0)
++#define ADR_MTX_DBG_DAT0 (MT_REG_CSR_BASE+0x000000d4)
++#define ADR_MTX_DBG_DAT1 (MT_REG_CSR_BASE+0x000000d8)
++#define ADR_MTX_DBG_DAT2 (MT_REG_CSR_BASE+0x000000dc)
++#define ADR_MTX_DUR_TOUT (MT_REG_CSR_BASE+0x000000e0)
++#define ADR_MTX_DUR_IFS (MT_REG_CSR_BASE+0x000000e4)
++#define ADR_MTX_DUR_SIFS_G (MT_REG_CSR_BASE+0x000000e8)
++#define ADR_MTX_DBG_DAT3 (MT_REG_CSR_BASE+0x000000ec)
++#define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0)
++#define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x000000f4)
++#define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x000000f8)
++#define ADR_MTX_DBG_DAT4 (MT_REG_CSR_BASE+0x000000fc)
++#define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ0_MTX_Q_BKF_CNT (TXQ0_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ0_MTX_Q_RC_LIMIT (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ0_MTX_Q_ID_MAP_L (TXQ0_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ0_MTX_Q_TXOP_CH_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ0_MTX_Q_TXOP_OV_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ1_MTX_Q_BKF_CNT (TXQ1_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ1_MTX_Q_RC_LIMIT (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ1_MTX_Q_ID_MAP_L (TXQ1_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ1_MTX_Q_TXOP_CH_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ1_MTX_Q_TXOP_OV_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ2_MTX_Q_BKF_CNT (TXQ2_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ2_MTX_Q_RC_LIMIT (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ2_MTX_Q_ID_MAP_L (TXQ2_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ2_MTX_Q_TXOP_CH_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ2_MTX_Q_TXOP_OV_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ3_MTX_Q_BKF_CNT (TXQ3_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ3_MTX_Q_RC_LIMIT (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ3_MTX_Q_ID_MAP_L (TXQ3_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ3_MTX_Q_TXOP_CH_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ3_MTX_Q_TXOP_OV_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ4_MTX_Q_BKF_CNT (TXQ4_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ4_MTX_Q_RC_LIMIT (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ4_MTX_Q_ID_MAP_L (TXQ4_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ4_MTX_Q_TXOP_CH_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ4_MTX_Q_TXOP_OV_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_WSID0 (HIF_INFO_BASE+0x00000000)
++#define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004)
++#define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008)
++#define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c)
++#define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010)
++#define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014)
++#define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018)
++#define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c)
++#define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020)
++#define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024)
++#define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028)
++#define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c)
++#define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030)
++#define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034)
++#define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038)
++#define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c)
++#define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040)
++#define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044)
++#define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048)
++#define ADR_WSID1 (HIF_INFO_BASE+0x00000050)
++#define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054)
++#define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058)
++#define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c)
++#define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060)
++#define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064)
++#define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068)
++#define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c)
++#define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070)
++#define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074)
++#define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078)
++#define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c)
++#define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080)
++#define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084)
++#define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088)
++#define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c)
++#define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090)
++#define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094)
++#define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098)
++#define ADR_INFO0 (PHY_RATE_INFO_BASE+0x00000000)
++#define ADR_INFO1 (PHY_RATE_INFO_BASE+0x00000004)
++#define ADR_INFO2 (PHY_RATE_INFO_BASE+0x00000008)
++#define ADR_INFO3 (PHY_RATE_INFO_BASE+0x0000000c)
++#define ADR_INFO4 (PHY_RATE_INFO_BASE+0x00000010)
++#define ADR_INFO5 (PHY_RATE_INFO_BASE+0x00000014)
++#define ADR_INFO6 (PHY_RATE_INFO_BASE+0x00000018)
++#define ADR_INFO7 (PHY_RATE_INFO_BASE+0x0000001c)
++#define ADR_INFO8 (PHY_RATE_INFO_BASE+0x00000020)
++#define ADR_INFO9 (PHY_RATE_INFO_BASE+0x00000024)
++#define ADR_INFO10 (PHY_RATE_INFO_BASE+0x00000028)
++#define ADR_INFO11 (PHY_RATE_INFO_BASE+0x0000002c)
++#define ADR_INFO12 (PHY_RATE_INFO_BASE+0x00000030)
++#define ADR_INFO13 (PHY_RATE_INFO_BASE+0x00000034)
++#define ADR_INFO14 (PHY_RATE_INFO_BASE+0x00000038)
++#define ADR_INFO15 (PHY_RATE_INFO_BASE+0x0000003c)
++#define ADR_INFO16 (PHY_RATE_INFO_BASE+0x00000040)
++#define ADR_INFO17 (PHY_RATE_INFO_BASE+0x00000044)
++#define ADR_INFO18 (PHY_RATE_INFO_BASE+0x00000048)
++#define ADR_INFO19 (PHY_RATE_INFO_BASE+0x0000004c)
++#define ADR_INFO20 (PHY_RATE_INFO_BASE+0x00000050)
++#define ADR_INFO21 (PHY_RATE_INFO_BASE+0x00000054)
++#define ADR_INFO22 (PHY_RATE_INFO_BASE+0x00000058)
++#define ADR_INFO23 (PHY_RATE_INFO_BASE+0x0000005c)
++#define ADR_INFO24 (PHY_RATE_INFO_BASE+0x00000060)
++#define ADR_INFO25 (PHY_RATE_INFO_BASE+0x00000064)
++#define ADR_INFO26 (PHY_RATE_INFO_BASE+0x00000068)
++#define ADR_INFO27 (PHY_RATE_INFO_BASE+0x0000006c)
++#define ADR_INFO28 (PHY_RATE_INFO_BASE+0x00000070)
++#define ADR_INFO29 (PHY_RATE_INFO_BASE+0x00000074)
++#define ADR_INFO30 (PHY_RATE_INFO_BASE+0x00000078)
++#define ADR_INFO31 (PHY_RATE_INFO_BASE+0x0000007c)
++#define ADR_INFO32 (PHY_RATE_INFO_BASE+0x00000080)
++#define ADR_INFO33 (PHY_RATE_INFO_BASE+0x00000084)
++#define ADR_INFO34 (PHY_RATE_INFO_BASE+0x00000088)
++#define ADR_INFO35 (PHY_RATE_INFO_BASE+0x0000008c)
++#define ADR_INFO36 (PHY_RATE_INFO_BASE+0x00000090)
++#define ADR_INFO37 (PHY_RATE_INFO_BASE+0x00000094)
++#define ADR_INFO38 (PHY_RATE_INFO_BASE+0x00000098)
++#define ADR_INFO_MASK (PHY_RATE_INFO_BASE+0x0000009c)
++#define ADR_INFO_RATE_OFFSET (PHY_RATE_INFO_BASE+0x000000a0)
++#define ADR_INFO_IDX_ADDR (PHY_RATE_INFO_BASE+0x000000a4)
++#define ADR_INFO_LEN_ADDR (PHY_RATE_INFO_BASE+0x000000a8)
++#define ADR_IC_TIME_TAG_0 (PHY_RATE_INFO_BASE+0x000000ac)
++#define ADR_IC_TIME_TAG_1 (PHY_RATE_INFO_BASE+0x000000b0)
++#define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x000000b4)
++#define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000)
++#define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004)
++#define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008)
++#define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c)
++#define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010)
++#define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014)
++#define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018)
++#define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c)
++#define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020)
++#define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024)
++#define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028)
++#define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c)
++#define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000002c)
++#define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030)
++#define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034)
++#define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038)
++#define ADR_BTCX0 (BTCX_REG_BASE+0x00000000)
++#define ADR_BTCX1 (BTCX_REG_BASE+0x00000004)
++#define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008)
++#define ADR_MIB_EN (MIB_REG_BASE+0x00000000)
++#define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118)
++#define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128)
++#define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138)
++#define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148)
++#define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c)
++#define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170)
++#define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174)
++#define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178)
++#define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c)
++#define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180)
++#define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184)
++#define ADR_MTX_FRM (MIB_REG_BASE+0x00000188)
++#define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c)
++#define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190)
++#define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194)
++#define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198)
++#define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c)
++#define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0)
++#define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4)
++#define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8)
++#define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac)
++#define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0)
++#define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4)
++#define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8)
++#define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc)
++#define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0)
++#define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4)
++#define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8)
++#define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc)
++#define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0)
++#define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4)
++#define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8)
++#define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc)
++#define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218)
++#define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c)
++#define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220)
++#define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224)
++#define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268)
++#define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c)
++#define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270)
++#define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274)
++#define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318)
++#define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c)
++#define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320)
++#define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324)
++#define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368)
++#define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c)
++#define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370)
++#define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374)
++#define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418)
++#define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c)
++#define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420)
++#define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424)
++#define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428)
++#define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468)
++#define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c)
++#define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470)
++#define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474)
++#define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478)
++#define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c)
++#define ADR_CBR_HARD_WIRE_PIN_REGISTER (CBR_A_REG_BASE+0x00110000)
++#define ADR_CBR_MANUAL_ENABLE_REGISTER (CBR_A_REG_BASE+0x00110004)
++#define ADR_CBR_LDO_REGISTER (CBR_A_REG_BASE+0x00110008)
++#define ADR_CBR_ABB_REGISTER_1 (CBR_A_REG_BASE+0x0011000c)
++#define ADR_CBR_ABB_REGISTER_2 (CBR_A_REG_BASE+0x00110010)
++#define ADR_CBR_TX_FE_REGISTER (CBR_A_REG_BASE+0x00110014)
++#define ADR_CBR_RX_FE_REGISTER_1 (CBR_A_REG_BASE+0x00110018)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1 (CBR_A_REG_BASE+0x0011001c)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2 (CBR_A_REG_BASE+0x00110020)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3 (CBR_A_REG_BASE+0x00110024)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4 (CBR_A_REG_BASE+0x00110028)
++#define ADR_CBR_RX_FSM_REGISTER (CBR_A_REG_BASE+0x0011002c)
++#define ADR_CBR_RX_ADC_REGISTER (CBR_A_REG_BASE+0x00110030)
++#define ADR_CBR_TX_DAC_REGISTER (CBR_A_REG_BASE+0x00110034)
++#define ADR_CBR_SX_ENABLE_RGISTER (CBR_A_REG_BASE+0x00110038)
++#define ADR_CBR_SYN_RGISTER_1 (CBR_A_REG_BASE+0x0011003c)
++#define ADR_CBR_SYN_RGISTER_2 (CBR_A_REG_BASE+0x00110040)
++#define ADR_CBR_SYN_PFD_CHP (CBR_A_REG_BASE+0x00110044)
++#define ADR_CBR_SYN_VCO_LOBF (CBR_A_REG_BASE+0x00110048)
++#define ADR_CBR_SYN_DIV_SDM_XOSC (CBR_A_REG_BASE+0x0011004c)
++#define ADR_CBR_SYN_LCK1 (CBR_A_REG_BASE+0x00110050)
++#define ADR_CBR_SYN_LCK2 (CBR_A_REG_BASE+0x00110054)
++#define ADR_CBR_DPLL_VCO_REGISTER (CBR_A_REG_BASE+0x00110058)
++#define ADR_CBR_DPLL_CP_PFD_REGISTER (CBR_A_REG_BASE+0x0011005c)
++#define ADR_CBR_DPLL_DIVIDER_REGISTER (CBR_A_REG_BASE+0x00110060)
++#define ADR_CBR_DCOC_IDAC_REGISTER1 (CBR_A_REG_BASE+0x00110064)
++#define ADR_CBR_DCOC_IDAC_REGISTER2 (CBR_A_REG_BASE+0x00110068)
++#define ADR_CBR_DCOC_IDAC_REGISTER3 (CBR_A_REG_BASE+0x0011006c)
++#define ADR_CBR_DCOC_IDAC_REGISTER4 (CBR_A_REG_BASE+0x00110070)
++#define ADR_CBR_DCOC_IDAC_REGISTER5 (CBR_A_REG_BASE+0x00110074)
++#define ADR_CBR_DCOC_IDAC_REGISTER6 (CBR_A_REG_BASE+0x00110078)
++#define ADR_CBR_DCOC_IDAC_REGISTER7 (CBR_A_REG_BASE+0x0011007c)
++#define ADR_CBR_DCOC_IDAC_REGISTER8 (CBR_A_REG_BASE+0x00110080)
++#define ADR_CBR_RCAL_REGISTER (CBR_A_REG_BASE+0x00110084)
++#define ADR_CBR_MANUAL_REGISTER (CBR_A_REG_BASE+0x00110088)
++#define ADR_CBR_TRX_DUMMY_REGISTER (CBR_A_REG_BASE+0x0011008c)
++#define ADR_CBR_SX_DUMMY_REGISTER (CBR_A_REG_BASE+0x00110090)
++#define ADR_CBR_READ_ONLY_FLAGS_1 (CBR_A_REG_BASE+0x00110094)
++#define ADR_CBR_READ_ONLY_FLAGS_2 (CBR_A_REG_BASE+0x00110098)
++#define ADR_CBR_RG_PKT_GEN_0 (CBR_A_REG_BASE+0x00120080)
++#define ADR_CBR_RG_PKT_GEN_1 (CBR_A_REG_BASE+0x00120084)
++#define ADR_CBR_RG_PKT_GEN_2 (CBR_A_REG_BASE+0x00120088)
++#define ADR_CBR_RG_INTEGRATION (CBR_A_REG_BASE+0x00120090)
++#define ADR_CBR_RG_PKT_GEN_TXCNT (CBR_A_REG_BASE+0x00120094)
++#define ADR_CBR_PATTERN_GEN (CBR_A_REG_BASE+0x001203f8)
++#define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004)
++#define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008)
++#define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c)
++#define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010)
++#define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010)
++#define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014)
++#define ADR_MCU_STATUS (MB_REG_BASE+0x00000018)
++#define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c)
++#define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020)
++#define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024)
++#define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c)
++#define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030)
++#define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034)
++#define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038)
++#define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c)
++#define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040)
++#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044)
++#define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048)
++#define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c)
++#define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050)
++#define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054)
++#define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c)
++#define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070)
++#define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074)
++#define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078)
++#define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c)
++#define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080)
++#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084)
++#define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088)
++#define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c)
++#define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090)
++#define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094)
++#define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098)
++#define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c)
++#define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000)
++#define ADR_GETID (ID_MNG_REG_BASE+0x00000000)
++#define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004)
++#define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008)
++#define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c)
++#define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010)
++#define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014)
++#define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018)
++#define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c)
++#define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020)
++#define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024)
++#define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028)
++#define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c)
++#define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030)
++#define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034)
++#define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038)
++#define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c)
++#define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040)
++#define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044)
++#define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048)
++#define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c)
++#define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050)
++#define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054)
++#define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058)
++#define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c)
++#define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060)
++#define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064)
++#define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068)
++#define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c)
++#define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070)
++#define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074)
++#define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078)
++#define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c)
++#define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080)
++#define ADR_PHY_EN_0 (CSR_PHY_BASE+0x00000000)
++#define ADR_PHY_EN_1 (CSR_PHY_BASE+0x00000004)
++#define ADR_SVN_VERSION_REG (CSR_PHY_BASE+0x00000008)
++#define ADR_PHY_PKT_GEN_0 (CSR_PHY_BASE+0x0000000c)
++#define ADR_PHY_PKT_GEN_1 (CSR_PHY_BASE+0x00000010)
++#define ADR_PHY_PKT_GEN_2 (CSR_PHY_BASE+0x00000014)
++#define ADR_PHY_PKT_GEN_3 (CSR_PHY_BASE+0x00000018)
++#define ADR_PHY_PKT_GEN_4 (CSR_PHY_BASE+0x0000001c)
++#define ADR_PHY_REG_00 (CSR_PHY_BASE+0x00000020)
++#define ADR_PHY_REG_01 (CSR_PHY_BASE+0x0000002c)
++#define ADR_PHY_REG_02_AGC (CSR_PHY_BASE+0x00000030)
++#define ADR_PHY_REG_03_AGC (CSR_PHY_BASE+0x00000034)
++#define ADR_PHY_REG_04_AGC (CSR_PHY_BASE+0x00000038)
++#define ADR_PHY_REG_05_AGC (CSR_PHY_BASE+0x0000003c)
++#define ADR_PHY_REG_06_11B_DAGC (CSR_PHY_BASE+0x00000040)
++#define ADR_PHY_REG_07_11B_DAGC (CSR_PHY_BASE+0x00000044)
++#define ADR_PHY_REG_08_11GN_DAGC (CSR_PHY_BASE+0x00000048)
++#define ADR_PHY_REG_09_11GN_DAGC (CSR_PHY_BASE+0x0000004c)
++#define ADR_PHY_READ_REG_00_DIG_PWR (CSR_PHY_BASE+0x00000050)
++#define ADR_PHY_READ_REG_01_RF_GAIN_PWR (CSR_PHY_BASE+0x00000054)
++#define ADR_PHY_READ_REG_02_RF_GAIN_PWR (CSR_PHY_BASE+0x00000058)
++#define ADR_PHY_READ_REG_03_RF_GAIN_PWR (CSR_PHY_BASE+0x0000005c)
++#define ADR_PHY_REG_10_TX_DES (CSR_PHY_BASE+0x00000060)
++#define ADR_PHY_REG_11_TX_DES (CSR_PHY_BASE+0x00000064)
++#define ADR_PHY_REG_12_TX_DES (CSR_PHY_BASE+0x00000068)
++#define ADR_PHY_REG_13_RX_DES (CSR_PHY_BASE+0x0000006c)
++#define ADR_PHY_REG_14_RX_DES (CSR_PHY_BASE+0x00000070)
++#define ADR_PHY_REG_15_RX_DES (CSR_PHY_BASE+0x00000074)
++#define ADR_PHY_REG_16_TX_DES_EXCP (CSR_PHY_BASE+0x00000078)
++#define ADR_PHY_REG_17_TX_DES_EXCP (CSR_PHY_BASE+0x0000007c)
++#define ADR_PHY_REG_18_RSSI_SNR (CSR_PHY_BASE+0x00000080)
++#define ADR_PHY_REG_19_DAC_MANUAL (CSR_PHY_BASE+0x00000084)
++#define ADR_PHY_REG_20_MRX_CNT (CSR_PHY_BASE+0x00000088)
++#define ADR_PHY_REG_21_TRX_RAMP (CSR_PHY_BASE+0x00000094)
++#define ADR_PHY_REG_22_TRX_RAMP (CSR_PHY_BASE+0x00000098)
++#define ADR_PHY_REG_23_ANT (CSR_PHY_BASE+0x0000009c)
++#define ADR_PHY_REG_24_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a0)
++#define ADR_PHY_REG_25_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a4)
++#define ADR_PHY_REG_26_MRX_LEN_CNT (CSR_PHY_BASE+0x000000a8)
++#define ADR_PHY_REG_27_MRX_LEN_CNT (CSR_PHY_BASE+0x000000ac)
++#define ADR_PHY_READ_REG_04 (CSR_PHY_BASE+0x000000b0)
++#define ADR_PHY_READ_REG_05 (CSR_PHY_BASE+0x000000b4)
++#define ADR_PHY_REG_28_BIST (CSR_PHY_BASE+0x000000b8)
++#define ADR_PHY_READ_REG_06_BIST (CSR_PHY_BASE+0x000000d8)
++#define ADR_PHY_READ_REG_07_BIST (CSR_PHY_BASE+0x000000f0)
++#define ADR_PHY_REG_29_MTRX_MAC (CSR_PHY_BASE+0x000000fc)
++#define ADR_PHY_READ_REG_08_MTRX_MAC (CSR_PHY_BASE+0x00000100)
++#define ADR_PHY_READ_REG_09_MTRX_MAC (CSR_PHY_BASE+0x00000104)
++#define ADR_PHY_REG_30_TX_UP_FIL (CSR_PHY_BASE+0x00000108)
++#define ADR_PHY_REG_31_TX_UP_FIL (CSR_PHY_BASE+0x0000010c)
++#define ADR_PHY_REG_32_TX_UP_FIL (CSR_PHY_BASE+0x00000110)
++#define ADR_PHY_READ_TBUS (CSR_PHY_BASE+0x000003fc)
++#define ADR_TX_11B_FIL_COEF_00 (CSR_PHY_BASE+0x00001000)
++#define ADR_TX_11B_FIL_COEF_01 (CSR_PHY_BASE+0x00001004)
++#define ADR_TX_11B_FIL_COEF_02 (CSR_PHY_BASE+0x00001008)
++#define ADR_TX_11B_FIL_COEF_03 (CSR_PHY_BASE+0x0000100c)
++#define ADR_TX_11B_FIL_COEF_04 (CSR_PHY_BASE+0x00001010)
++#define ADR_TX_11B_FIL_COEF_05 (CSR_PHY_BASE+0x00001014)
++#define ADR_TX_11B_FIL_COEF_06 (CSR_PHY_BASE+0x00001018)
++#define ADR_TX_11B_FIL_COEF_07 (CSR_PHY_BASE+0x0000101c)
++#define ADR_TX_11B_FIL_COEF_08 (CSR_PHY_BASE+0x00001020)
++#define ADR_TX_11B_FIL_COEF_09 (CSR_PHY_BASE+0x00001024)
++#define ADR_TX_11B_FIL_COEF_10 (CSR_PHY_BASE+0x00001028)
++#define ADR_TX_11B_FIL_COEF_11 (CSR_PHY_BASE+0x0000102c)
++#define ADR_TX_11B_FIL_COEF_12 (CSR_PHY_BASE+0x00001030)
++#define ADR_TX_11B_FIL_COEF_13 (CSR_PHY_BASE+0x00001034)
++#define ADR_TX_11B_FIL_COEF_14 (CSR_PHY_BASE+0x00001038)
++#define ADR_TX_11B_FIL_COEF_15 (CSR_PHY_BASE+0x0000103c)
++#define ADR_TX_11B_FIL_COEF_16 (CSR_PHY_BASE+0x00001040)
++#define ADR_TX_11B_FIL_COEF_17 (CSR_PHY_BASE+0x00001044)
++#define ADR_TX_11B_FIL_COEF_18 (CSR_PHY_BASE+0x00001048)
++#define ADR_TX_11B_FIL_COEF_19 (CSR_PHY_BASE+0x0000104c)
++#define ADR_TX_11B_FIL_COEF_20 (CSR_PHY_BASE+0x00001050)
++#define ADR_TX_11B_FIL_COEF_21 (CSR_PHY_BASE+0x00001054)
++#define ADR_TX_11B_FIL_COEF_22 (CSR_PHY_BASE+0x00001058)
++#define ADR_TX_11B_FIL_COEF_23 (CSR_PHY_BASE+0x0000105c)
++#define ADR_TX_11B_FIL_COEF_24 (CSR_PHY_BASE+0x00001060)
++#define ADR_TX_11B_FIL_COEF_25 (CSR_PHY_BASE+0x00001064)
++#define ADR_TX_11B_FIL_COEF_26 (CSR_PHY_BASE+0x00001068)
++#define ADR_TX_11B_FIL_COEF_27 (CSR_PHY_BASE+0x0000106c)
++#define ADR_TX_11B_FIL_COEF_28 (CSR_PHY_BASE+0x00001070)
++#define ADR_TX_11B_FIL_COEF_29 (CSR_PHY_BASE+0x00001074)
++#define ADR_TX_11B_FIL_COEF_30 (CSR_PHY_BASE+0x00001078)
++#define ADR_TX_11B_FIL_COEF_31 (CSR_PHY_BASE+0x0000107c)
++#define ADR_TX_11B_FIL_COEF_32 (CSR_PHY_BASE+0x00001080)
++#define ADR_TX_11B_FIL_COEF_33 (CSR_PHY_BASE+0x00001084)
++#define ADR_TX_11B_FIL_COEF_34 (CSR_PHY_BASE+0x00001088)
++#define ADR_TX_11B_FIL_COEF_35 (CSR_PHY_BASE+0x0000108c)
++#define ADR_TX_11B_FIL_COEF_36 (CSR_PHY_BASE+0x00001090)
++#define ADR_TX_11B_FIL_COEF_37 (CSR_PHY_BASE+0x00001094)
++#define ADR_TX_11B_FIL_COEF_38 (CSR_PHY_BASE+0x00001098)
++#define ADR_TX_11B_FIL_COEF_39 (CSR_PHY_BASE+0x0000109c)
++#define ADR_TX_11B_FIL_COEF_40 (CSR_PHY_BASE+0x000010a0)
++#define ADR_TX_11B_PLCP (CSR_PHY_BASE+0x000010a4)
++#define ADR_TX_11B_RAMP (CSR_PHY_BASE+0x000010b4)
++#define ADR_TX_11B_EN_CNT_RST_N (CSR_PHY_BASE+0x000010d4)
++#define ADR_TX_11B_EN_CNT (CSR_PHY_BASE+0x000010d8)
++#define ADR_TX_11B_PKT_GEN_CNT (CSR_PHY_BASE+0x00001c00)
++#define ADR_RX_11B_DES_DLY (CSR_PHY_BASE+0x00002000)
++#define ADR_RX_11B_CCA_0 (CSR_PHY_BASE+0x00002004)
++#define ADR_RX_11B_CCA_1 (CSR_PHY_BASE+0x00002008)
++#define ADR_RX_11B_TR_KP_KI_0 (CSR_PHY_BASE+0x0000200c)
++#define ADR_RX_11B_TR_KP_KI_1 (CSR_PHY_BASE+0x00002010)
++#define ADR_RX_11B_CE_CNT_THRESHOLD (CSR_PHY_BASE+0x00002014)
++#define ADR_RX_11B_CE_MU_0 (CSR_PHY_BASE+0x00002018)
++#define ADR_RX_11B_CE_MU_1 (CSR_PHY_BASE+0x0000201c)
++#define ADR_RX_11B_EQ_MU_0 (CSR_PHY_BASE+0x00002020)
++#define ADR_RX_11B_EQ_MU_1 (CSR_PHY_BASE+0x00002024)
++#define ADR_RX_11B_EQ_CR_KP_KI (CSR_PHY_BASE+0x00002028)
++#define ADR_RX_11B_LPF_RATE (CSR_PHY_BASE+0x0000202c)
++#define ADR_RX_11B_CIT_CNT_THRESHOLD (CSR_PHY_BASE+0x00002030)
++#define ADR_RX_11B_EQ_CH_MAIN_TAP (CSR_PHY_BASE+0x00002034)
++#define ADR_RX_11B_SEARCH_CNT_TH (CSR_PHY_BASE+0x0000209c)
++#define ADR_RX_11B_CCA_CONTROL (CSR_PHY_BASE+0x000020a0)
++#define ADR_RX_11B_FREQUENCY_OFFSET (CSR_PHY_BASE+0x000023d4)
++#define ADR_RX_11B_SNR_RSSI (CSR_PHY_BASE+0x000023d8)
++#define ADR_RX_11B_SFD_CRC_CNT (CSR_PHY_BASE+0x000023e4)
++#define ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT (CSR_PHY_BASE+0x000023e8)
++#define ADR_RX_11B_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000023ec)
++#define ADR_RX_11B_SFD_FILED_0 (CSR_PHY_BASE+0x000023f0)
++#define ADR_RX_11B_SFD_FIELD_1 (CSR_PHY_BASE+0x000023f4)
++#define ADR_RX_11B_PKT_STAT_EN (CSR_PHY_BASE+0x000023f8)
++#define ADR_RX_11B_SOFT_RST (CSR_PHY_BASE+0x000023fc)
++#define ADR_TX_11GN_RAMP (CSR_PHY_BASE+0x000030a4)
++#define ADR_TX_11GN_PLCP (CSR_PHY_BASE+0x000030b8)
++#define ADR_TX_11GN_PKT_GEN_CNT (CSR_PHY_BASE+0x00003c00)
++#define ADR_TX_11GN_PLCP_CRC_ERR_CNT (CSR_PHY_BASE+0x00003c08)
++#define ADR_RX_11GN_DES_DLY (CSR_PHY_BASE+0x00004000)
++#define ADR_RX_11GN_TR_0 (CSR_PHY_BASE+0x00004004)
++#define ADR_RX_11GN_TR_1 (CSR_PHY_BASE+0x00004008)
++#define ADR_RX_11GN_TR_2 (CSR_PHY_BASE+0x0000400c)
++#define ADR_RX_11GN_CCA_0 (CSR_PHY_BASE+0x00004010)
++#define ADR_RX_11GN_CCA_1 (CSR_PHY_BASE+0x00004014)
++#define ADR_RX_11GN_CCA_2 (CSR_PHY_BASE+0x00004018)
++#define ADR_RX_11GN_CCA_FFT_SCALE (CSR_PHY_BASE+0x0000401c)
++#define ADR_RX_11GN_SOFT_DEMAP_0 (CSR_PHY_BASE+0x00004020)
++#define ADR_RX_11GN_SOFT_DEMAP_1 (CSR_PHY_BASE+0x00004024)
++#define ADR_RX_11GN_SOFT_DEMAP_2 (CSR_PHY_BASE+0x00004028)
++#define ADR_RX_11GN_SOFT_DEMAP_3 (CSR_PHY_BASE+0x0000402c)
++#define ADR_RX_11GN_SOFT_DEMAP_4 (CSR_PHY_BASE+0x00004030)
++#define ADR_RX_11GN_SOFT_DEMAP_5 (CSR_PHY_BASE+0x00004034)
++#define ADR_RX_11GN_SYM_BOUND_0 (CSR_PHY_BASE+0x00004038)
++#define ADR_RX_11GN_SYM_BOUND_1 (CSR_PHY_BASE+0x0000409c)
++#define ADR_RX_11GN_CCA_PWR (CSR_PHY_BASE+0x000040c0)
++#define ADR_RX_11GN_CCA_CNT (CSR_PHY_BASE+0x000040c4)
++#define ADR_RX_11GN_CCA_ATCOR_RE_CHECK (CSR_PHY_BASE+0x000040c8)
++#define ADR_RX_11GN_VTB_TB (CSR_PHY_BASE+0x00004130)
++#define ADR_RX_11GN_ERR_UPDATE (CSR_PHY_BASE+0x00004164)
++#define ADR_RX_11GN_SHORT_GI (CSR_PHY_BASE+0x00004180)
++#define ADR_RX_11GN_CHANNEL_UPDATE (CSR_PHY_BASE+0x00004188)
++#define ADR_RX_11GN_PKT_FORMAT_0 (CSR_PHY_BASE+0x00004190)
++#define ADR_RX_11GN_PKT_FORMAT_1 (CSR_PHY_BASE+0x00004194)
++#define ADR_RX_11GN_TX_TIME (CSR_PHY_BASE+0x00004380)
++#define ADR_RX_11GN_STBC_TR_KP_KI (CSR_PHY_BASE+0x00004384)
++#define ADR_RX_11GN_BIST_0 (CSR_PHY_BASE+0x00004388)
++#define ADR_RX_11GN_BIST_1 (CSR_PHY_BASE+0x0000438c)
++#define ADR_RX_11GN_BIST_2 (CSR_PHY_BASE+0x000043c0)
++#define ADR_RX_11GN_BIST_3 (CSR_PHY_BASE+0x000043c4)
++#define ADR_RX_11GN_BIST_4 (CSR_PHY_BASE+0x000043c8)
++#define ADR_RX_11GN_BIST_5 (CSR_PHY_BASE+0x000043cc)
++#define ADR_RX_11GN_SPECTRUM_ANALYZER (CSR_PHY_BASE+0x000043d4)
++#define ADR_RX_11GN_READ_0 (CSR_PHY_BASE+0x000043d8)
++#define ADR_RX_11GN_FREQ_OFFSET (CSR_PHY_BASE+0x000043dc)
++#define ADR_RX_11GN_SIGNAL_FIELD_0 (CSR_PHY_BASE+0x000043e0)
++#define ADR_RX_11GN_SIGNAL_FIELD_1 (CSR_PHY_BASE+0x000043e4)
++#define ADR_RX_11GN_PKT_ERR_CNT (CSR_PHY_BASE+0x000043e8)
++#define ADR_RX_11GN_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000043ec)
++#define ADR_RX_11GN_SERVICE_LENGTH_FIELD (CSR_PHY_BASE+0x000043f0)
++#define ADR_RX_11GN_RATE (CSR_PHY_BASE+0x000043f4)
++#define ADR_RX_11GN_STAT_EN (CSR_PHY_BASE+0x000043f8)
++#define ADR_RX_11GN_SOFT_RST (CSR_PHY_BASE+0x000043fc)
++#define ADR_RF_CONTROL_0 (CSR_PHY_BASE+0x00007000)
++#define ADR_RF_CONTROL_1 (CSR_PHY_BASE+0x00007004)
++#define ADR_TX_IQ_CONTROL_0 (CSR_PHY_BASE+0x00007040)
++#define ADR_TX_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007044)
++#define ADR_TX_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007048)
++#define ADR_TX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x0000704c)
++#define ADR_RX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x00007050)
++#define ADR_RX_OBSERVATION_CIRCUIT_0 (CSR_PHY_BASE+0x00007058)
++#define ADR_RX_OBSERVATION_CIRCUIT_1 (CSR_PHY_BASE+0x0000705c)
++#define ADR_RX_OBSERVATION_CIRCUIT_2 (CSR_PHY_BASE+0x00007060)
++#define ADR_RX_OBSERVATION_CIRCUIT_3 (CSR_PHY_BASE+0x00007064)
++#define ADR_RF_IQ_CONTROL_0 (CSR_PHY_BASE+0x0000706c)
++#define ADR_RF_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007070)
++#define ADR_RF_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007074)
++#define ADR_RF_IQ_CONTROL_3 (CSR_PHY_BASE+0x00007078)
++#define ADR_DPD_CONTROL (CSR_PHY_BASE+0x0000711c)
++#define ADR_DPD_GAIN_TABLE_0 (CSR_PHY_BASE+0x00007120)
++#define ADR_DPD_GAIN_TABLE_1 (CSR_PHY_BASE+0x00007124)
++#define ADR_DPD_GAIN_TABLE_2 (CSR_PHY_BASE+0x00007128)
++#define ADR_DPD_GAIN_TABLE_3 (CSR_PHY_BASE+0x00007130)
++#define ADR_DPD_GAIN_TABLE_4 (CSR_PHY_BASE+0x00007134)
++#define ADR_DPD_GAIN_TABLE_5 (CSR_PHY_BASE+0x00007138)
++#define ADR_DPD_GAIN_TABLE_6 (CSR_PHY_BASE+0x0000713c)
++#define ADR_DPD_GAIN_TABLE_7 (CSR_PHY_BASE+0x00007140)
++#define ADR_DPD_GAIN_TABLE_8 (CSR_PHY_BASE+0x00007144)
++#define ADR_DPD_GAIN_TABLE_9 (CSR_PHY_BASE+0x00007148)
++#define ADR_DPD_GAIN_TABLE_A (CSR_PHY_BASE+0x0000714c)
++#define ADR_DPD_GAIN_TABLE_B (CSR_PHY_BASE+0x00007150)
++#define ADR_DPD_GAIN_TABLE_C (CSR_PHY_BASE+0x00007154)
++#define ADR_DPD_PH_TABLE_0 (CSR_PHY_BASE+0x00007170)
++#define ADR_DPD_PH_TABLE_1 (CSR_PHY_BASE+0x00007174)
++#define ADR_DPD_PH_TABLE_2 (CSR_PHY_BASE+0x00007178)
++#define ADR_DPD_PH_TABLE_3 (CSR_PHY_BASE+0x00007180)
++#define ADR_DPD_PH_TABLE_4 (CSR_PHY_BASE+0x00007184)
++#define ADR_DPD_PH_TABLE_5 (CSR_PHY_BASE+0x00007188)
++#define ADR_DPD_PH_TABLE_6 (CSR_PHY_BASE+0x0000718c)
++#define ADR_DPD_PH_TABLE_7 (CSR_PHY_BASE+0x00007190)
++#define ADR_DPD_PH_TABLE_8 (CSR_PHY_BASE+0x00007194)
++#define ADR_DPD_PH_TABLE_9 (CSR_PHY_BASE+0x00007198)
++#define ADR_DPD_PH_TABLE_A (CSR_PHY_BASE+0x0000719c)
++#define ADR_DPD_PH_TABLE_B (CSR_PHY_BASE+0x000071a0)
++#define ADR_DPD_PH_TABLE_C (CSR_PHY_BASE+0x000071a4)
++#define ADR_DPD_GAIN_ESTIMATION_0 (CSR_PHY_BASE+0x000071b0)
++#define ADR_DPD_GAIN_ESTIMATION_1 (CSR_PHY_BASE+0x000071b4)
++#define ADR_DPD_GAIN_ESTIMATION_2 (CSR_PHY_BASE+0x000071b8)
++#define ADR_TX_GAIN_FACTOR (CSR_PHY_BASE+0x000071bc)
++#define ADR_HARD_WIRE_PIN_REGISTER (CSR_RF_BASE+0x00000000)
++#define ADR_MANUAL_ENABLE_REGISTER (CSR_RF_BASE+0x00000004)
++#define ADR_LDO_REGISTER (CSR_RF_BASE+0x00000008)
++#define ADR_ABB_REGISTER_1 (CSR_RF_BASE+0x0000000c)
++#define ADR_ABB_REGISTER_2 (CSR_RF_BASE+0x00000010)
++#define ADR_TX_FE_REGISTER (CSR_RF_BASE+0x00000014)
++#define ADR_RX_FE_REGISTER_1 (CSR_RF_BASE+0x00000018)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_1 (CSR_RF_BASE+0x0000001c)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_2 (CSR_RF_BASE+0x00000020)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_3 (CSR_RF_BASE+0x00000024)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_4 (CSR_RF_BASE+0x00000028)
++#define ADR_RX_TX_FSM_REGISTER (CSR_RF_BASE+0x0000002c)
++#define ADR_RX_ADC_REGISTER (CSR_RF_BASE+0x00000030)
++#define ADR_TX_DAC_REGISTER (CSR_RF_BASE+0x00000034)
++#define ADR_SX_ENABLE_REGISTER (CSR_RF_BASE+0x00000038)
++#define ADR_SYN_REGISTER_1 (CSR_RF_BASE+0x0000003c)
++#define ADR_SYN_REGISTER_2 (CSR_RF_BASE+0x00000040)
++#define ADR_SYN_PFD_CHP (CSR_RF_BASE+0x00000044)
++#define ADR_SYN_VCO_LOBF (CSR_RF_BASE+0x00000048)
++#define ADR_SYN_DIV_SDM_XOSC (CSR_RF_BASE+0x0000004c)
++#define ADR_SYN_KVCO_XO_FINE_TUNE_CBANK (CSR_RF_BASE+0x00000050)
++#define ADR_SYN_LCK_VT (CSR_RF_BASE+0x00000054)
++#define ADR_DPLL_VCO_REGISTER (CSR_RF_BASE+0x00000058)
++#define ADR_DPLL_CP_PFD_REGISTER (CSR_RF_BASE+0x0000005c)
++#define ADR_DPLL_DIVIDER_REGISTER (CSR_RF_BASE+0x00000060)
++#define ADR_DCOC_IDAC_REGISTER1 (CSR_RF_BASE+0x00000064)
++#define ADR_DCOC_IDAC_REGISTER2 (CSR_RF_BASE+0x00000068)
++#define ADR_DCOC_IDAC_REGISTER3 (CSR_RF_BASE+0x0000006c)
++#define ADR_DCOC_IDAC_REGISTER4 (CSR_RF_BASE+0x00000070)
++#define ADR_DCOC_IDAC_REGISTER5 (CSR_RF_BASE+0x00000074)
++#define ADR_DCOC_IDAC_REGISTER6 (CSR_RF_BASE+0x00000078)
++#define ADR_DCOC_IDAC_REGISTER7 (CSR_RF_BASE+0x0000007c)
++#define ADR_DCOC_IDAC_REGISTER8 (CSR_RF_BASE+0x00000080)
++#define ADR_RCAL_REGISTER (CSR_RF_BASE+0x00000084)
++#define ADR_SX_LCK_BIN_REGISTERS_I (CSR_RF_BASE+0x00000088)
++#define ADR_TRX_DUMMY_REGISTER (CSR_RF_BASE+0x0000008c)
++#define ADR_SX_DUMMY_REGISTER (CSR_RF_BASE+0x00000090)
++#define ADR_READ_ONLY_FLAGS_1 (CSR_RF_BASE+0x00000094)
++#define ADR_READ_ONLY_FLAGS_2 (CSR_RF_BASE+0x00000098)
++#define ADR_DPLL_FB_DIVIDER_REGISTERS_I (CSR_RF_BASE+0x0000009c)
++#define ADR_DPLL_FB_DIVIDER_REGISTERS_II (CSR_RF_BASE+0x000000a0)
++#define ADR_SX_LCK_BIN_REGISTERS_II (CSR_RF_BASE+0x000000a4)
++#define ADR_RC_OSC_32K_CAL_REGISTERS (CSR_RF_BASE+0x000000a8)
++#define ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER (CSR_RF_BASE+0x000000ac)
++#define ADR_MMU_CTRL (MMU_REG_BASE+0x00000000)
++#define ADR_HS_CTRL (MMU_REG_BASE+0x00000004)
++#define ADR_CPU_POR0_7 (MMU_REG_BASE+0x00000008)
++#define ADR_CPU_POR8_F (MMU_REG_BASE+0x0000000c)
++#define ADR_REG_LEN_CTRL (MMU_REG_BASE+0x00000010)
++#define ADR_DMN_READ_BYPASS (MMU_REG_BASE+0x00000014)
++#define ADR_ALC_RLS_ABORT (MMU_REG_BASE+0x00000018)
++#define ADR_DEBUG_CTL (MMU_REG_BASE+0x00000020)
++#define ADR_DEBUG_OUT (MMU_REG_BASE+0x00000024)
++#define ADR_MMU_STATUS (MMU_REG_BASE+0x00000028)
++#define ADR_DMN_STATUS (MMU_REG_BASE+0x0000002c)
++#define ADR_TAG_STATUS (MMU_REG_BASE+0x00000030)
++#define ADR_DMN_MCU_STATUS (MMU_REG_BASE+0x00000034)
++#define ADR_MB_IDTBL_0_STATUS (MMU_REG_BASE+0x00000040)
++#define ADR_MB_IDTBL_1_STATUS (MMU_REG_BASE+0x00000044)
++#define ADR_MB_IDTBL_2_STATUS (MMU_REG_BASE+0x00000048)
++#define ADR_MB_IDTBL_3_STATUS (MMU_REG_BASE+0x0000004c)
++#define ADR_PKT_IDTBL_0_STATUS (MMU_REG_BASE+0x00000050)
++#define ADR_PKT_IDTBL_1_STATUS (MMU_REG_BASE+0x00000054)
++#define ADR_PKT_IDTBL_2_STATUS (MMU_REG_BASE+0x00000058)
++#define ADR_PKT_IDTBL_3_STATUS (MMU_REG_BASE+0x0000005c)
++#define ADR_DMN_IDTBL_0_STATUS (MMU_REG_BASE+0x00000060)
++#define ADR_DMN_IDTBL_1_STATUS (MMU_REG_BASE+0x00000064)
++#define ADR_DMN_IDTBL_2_STATUS (MMU_REG_BASE+0x00000068)
++#define ADR_DMN_IDTBL_3_STATUS (MMU_REG_BASE+0x0000006c)
++#define ADR_MB_NEQID_0_STATUS (MMU_REG_BASE+0x00000070)
++#define ADR_MB_NEQID_1_STATUS (MMU_REG_BASE+0x00000074)
++#define ADR_MB_NEQID_2_STATUS (MMU_REG_BASE+0x00000078)
++#define ADR_MB_NEQID_3_STATUS (MMU_REG_BASE+0x0000007c)
++#define ADR_PKT_NEQID_0_STATUS (MMU_REG_BASE+0x00000080)
++#define ADR_PKT_NEQID_1_STATUS (MMU_REG_BASE+0x00000084)
++#define ADR_PKT_NEQID_2_STATUS (MMU_REG_BASE+0x00000088)
++#define ADR_PKT_NEQID_3_STATUS (MMU_REG_BASE+0x0000008c)
++#define ADR_ALC_NOCHG_ID_STATUS (MMU_REG_BASE+0x00000090)
++#define ADR_TAG_SRAM0_F_STATUS_0 (MMU_REG_BASE+0x000000a0)
++#define ADR_TAG_SRAM0_F_STATUS_1 (MMU_REG_BASE+0x000000a4)
++#define ADR_TAG_SRAM0_F_STATUS_2 (MMU_REG_BASE+0x000000a8)
++#define ADR_TAG_SRAM0_F_STATUS_3 (MMU_REG_BASE+0x000000ac)
++#define ADR_TAG_SRAM0_F_STATUS_4 (MMU_REG_BASE+0x000000b0)
++#define ADR_TAG_SRAM0_F_STATUS_5 (MMU_REG_BASE+0x000000b4)
++#define ADR_TAG_SRAM0_F_STATUS_6 (MMU_REG_BASE+0x000000b8)
++#define ADR_TAG_SRAM0_F_STATUS_7 (MMU_REG_BASE+0x000000bc)
++#define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0)
++#define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1)
++#define GET_MCU_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2)
++#define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3)
++#define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4)
++#define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5)
++#define GET_DMA_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000040 ) >> 6)
++#define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7)
++#define GET_I2C_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000100 ) >> 8)
++#define GET_INT_CTL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000200 ) >> 9)
++#define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10)
++#define GET_GPIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000800 ) >> 11)
++#define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12)
++#define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13)
++#define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14)
++#define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15)
++#define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16)
++#define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17)
++#define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18)
++#define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19)
++#define GET_RF_BB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20)
++#define GET_SYS_ALL_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21)
++#define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22)
++#define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23)
++#define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0)
++#define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16)
++#define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17)
++#define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18)
++#define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0)
++#define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0)
++#define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0)
++#define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0)
++#define GET_CK_SEL_1_0 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000003 ) >> 0)
++#define GET_CK_SEL_2 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000004 ) >> 2)
++#define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
++#define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MCU_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2)
++#define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
++#define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
++#define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
++#define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
++#define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
++#define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8)
++#define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
++#define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_GPIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
++#define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
++#define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
++#define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
++#define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16)
++#define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17)
++#define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18)
++#define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19)
++#define GET_BIST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20)
++#define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23)
++#define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_MCU_DBG_SEL (((REG32(ADR_MCU_DBG_SEL)) & 0x0000003f ) >> 0)
++#define GET_MCU_STOP_NOGRANT (((REG32(ADR_MCU_DBG_SEL)) & 0x00000100 ) >> 8)
++#define GET_MCU_STOP_ANYTIME (((REG32(ADR_MCU_DBG_SEL)) & 0x00000200 ) >> 9)
++#define GET_MCU_DBG_DATA (((REG32(ADR_MCU_DBG_DATA)) & 0xffffffff ) >> 0)
++#define GET_AHB_SW_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000001 ) >> 0)
++#define GET_AHB_ERR_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000002 ) >> 1)
++#define GET_REG_AHB_DEBUG_MX (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000030 ) >> 4)
++#define GET_REG_PKT_W_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000100 ) >> 8)
++#define GET_REG_PKT_R_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000200 ) >> 9)
++#define GET_IQ_SRAM_SEL_0 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00001000 ) >> 12)
++#define GET_IQ_SRAM_SEL_1 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00002000 ) >> 13)
++#define GET_IQ_SRAM_SEL_2 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00004000 ) >> 14)
++#define GET_AHB_STATUS (((REG32(ADR_AHB_BRG_STATUS)) & 0xffff0000 ) >> 16)
++#define GET_PARALLEL_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000001 ) >> 0)
++#define GET_MBRUN (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000010 ) >> 4)
++#define GET_SHIFT_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000100 ) >> 8)
++#define GET_MODE_REG_SI (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000200 ) >> 9)
++#define GET_SIMULATION_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000400 ) >> 10)
++#define GET_DBIST_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000800 ) >> 11)
++#define GET_MODE_REG_IN (((REG32(ADR_BIST_MODE_REG_IN)) & 0x001fffff ) >> 0)
++#define GET_MODE_REG_OUT_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x001fffff ) >> 0)
++#define GET_MODE_REG_SO_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x80000000 ) >> 31)
++#define GET_MONITOR_BUS_MCU_31_0 (((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0xffffffff ) >> 0)
++#define GET_MONITOR_BUS_MCU_33_32 (((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0x00000003 ) >> 0)
++#define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0)
++#define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31)
++#define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0)
++#define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0)
++#define GET_DATA_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000010 ) >> 4)
++#define GET_AHB_ILL_ADDR (((REG32(ADR_AHB_ILL_ADDR)) & 0xffffffff ) >> 0)
++#define GET_AHB_FEN_ADDR (((REG32(ADR_AHB_FEN_ADDR)) & 0xffffffff ) >> 0)
++#define GET_ILL_ADDR_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000001 ) >> 0)
++#define GET_FENCE_HIT_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000002 ) >> 1)
++#define GET_ILL_ADDR_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000010 ) >> 4)
++#define GET_FENCE_HIT_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000020 ) >> 5)
++#define GET_PWM_INI_VALUE_P_A (((REG32(ADR_PWM_A)) & 0x000000ff ) >> 0)
++#define GET_PWM_INI_VALUE_N_A (((REG32(ADR_PWM_A)) & 0x0000ff00 ) >> 8)
++#define GET_PWM_POST_SCALER_A (((REG32(ADR_PWM_A)) & 0x000f0000 ) >> 16)
++#define GET_PWM_ALWAYSON_A (((REG32(ADR_PWM_A)) & 0x20000000 ) >> 29)
++#define GET_PWM_INVERT_A (((REG32(ADR_PWM_A)) & 0x40000000 ) >> 30)
++#define GET_PWM_ENABLE_A (((REG32(ADR_PWM_A)) & 0x80000000 ) >> 31)
++#define GET_PWM_INI_VALUE_P_B (((REG32(ADR_PWM_B)) & 0x000000ff ) >> 0)
++#define GET_PWM_INI_VALUE_N_B (((REG32(ADR_PWM_B)) & 0x0000ff00 ) >> 8)
++#define GET_PWM_POST_SCALER_B (((REG32(ADR_PWM_B)) & 0x000f0000 ) >> 16)
++#define GET_PWM_ALWAYSON_B (((REG32(ADR_PWM_B)) & 0x20000000 ) >> 29)
++#define GET_PWM_INVERT_B (((REG32(ADR_PWM_B)) & 0x40000000 ) >> 30)
++#define GET_PWM_ENABLE_B (((REG32(ADR_PWM_B)) & 0x80000000 ) >> 31)
++#define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0)
++#define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0)
++#define GET_PRESCALER_USTIMER (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0)
++#define GET_MODE_REG_IN_MMU (((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0x0000ffff ) >> 0)
++#define GET_MODE_REG_OUT_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x0000ffff ) >> 0)
++#define GET_MODE_REG_SO_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x80000000 ) >> 31)
++#define GET_MONITOR_BUS_MMU (((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0x0007ffff ) >> 0)
++#define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0)
++#define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1)
++#define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2)
++#define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3)
++#define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4)
++#define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5)
++#define GET_WDT_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0)
++#define GET_SD_HOST_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1)
++#define GET_ALLOW_SD_RESET (((REG32(ADR_SD_INIT_CFG)) & 0x00000001 ) >> 0)
++#define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0)
++#define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1)
++#define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0)
++#define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x00020000 ) >> 17)
++#define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31)
++#define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0)
++#define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x00020000 ) >> 17)
++#define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31)
++#define GET_XLNA_EN_O_OE (((REG32(ADR_PAD6)) & 0x00000001 ) >> 0)
++#define GET_XLNA_EN_O_PE (((REG32(ADR_PAD6)) & 0x00000002 ) >> 1)
++#define GET_PAD6_IE (((REG32(ADR_PAD6)) & 0x00000008 ) >> 3)
++#define GET_PAD6_SEL_I (((REG32(ADR_PAD6)) & 0x00000030 ) >> 4)
++#define GET_PAD6_OD (((REG32(ADR_PAD6)) & 0x00000100 ) >> 8)
++#define GET_PAD6_SEL_O (((REG32(ADR_PAD6)) & 0x00001000 ) >> 12)
++#define GET_XLNA_EN_O_C (((REG32(ADR_PAD6)) & 0x10000000 ) >> 28)
++#define GET_WIFI_TX_SW_O_OE (((REG32(ADR_PAD7)) & 0x00000001 ) >> 0)
++#define GET_WIFI_TX_SW_O_PE (((REG32(ADR_PAD7)) & 0x00000002 ) >> 1)
++#define GET_PAD7_IE (((REG32(ADR_PAD7)) & 0x00000008 ) >> 3)
++#define GET_PAD7_SEL_I (((REG32(ADR_PAD7)) & 0x00000030 ) >> 4)
++#define GET_PAD7_OD (((REG32(ADR_PAD7)) & 0x00000100 ) >> 8)
++#define GET_PAD7_SEL_O (((REG32(ADR_PAD7)) & 0x00001000 ) >> 12)
++#define GET_WIFI_TX_SW_O_C (((REG32(ADR_PAD7)) & 0x10000000 ) >> 28)
++#define GET_WIFI_RX_SW_O_OE (((REG32(ADR_PAD8)) & 0x00000001 ) >> 0)
++#define GET_WIFI_RX_SW_O_PE (((REG32(ADR_PAD8)) & 0x00000002 ) >> 1)
++#define GET_PAD8_IE (((REG32(ADR_PAD8)) & 0x00000008 ) >> 3)
++#define GET_PAD8_SEL_I (((REG32(ADR_PAD8)) & 0x00000030 ) >> 4)
++#define GET_PAD8_OD (((REG32(ADR_PAD8)) & 0x00000100 ) >> 8)
++#define GET_WIFI_RX_SW_O_C (((REG32(ADR_PAD8)) & 0x10000000 ) >> 28)
++#define GET_BT_SW_O_OE (((REG32(ADR_PAD9)) & 0x00000001 ) >> 0)
++#define GET_BT_SW_O_PE (((REG32(ADR_PAD9)) & 0x00000002 ) >> 1)
++#define GET_PAD9_IE (((REG32(ADR_PAD9)) & 0x00000008 ) >> 3)
++#define GET_PAD9_SEL_I (((REG32(ADR_PAD9)) & 0x00000030 ) >> 4)
++#define GET_PAD9_OD (((REG32(ADR_PAD9)) & 0x00000100 ) >> 8)
++#define GET_PAD9_SEL_O (((REG32(ADR_PAD9)) & 0x00001000 ) >> 12)
++#define GET_BT_SW_O_C (((REG32(ADR_PAD9)) & 0x10000000 ) >> 28)
++#define GET_XPA_EN_O_OE (((REG32(ADR_PAD11)) & 0x00000001 ) >> 0)
++#define GET_XPA_EN_O_PE (((REG32(ADR_PAD11)) & 0x00000002 ) >> 1)
++#define GET_PAD11_IE (((REG32(ADR_PAD11)) & 0x00000008 ) >> 3)
++#define GET_PAD11_SEL_I (((REG32(ADR_PAD11)) & 0x00000030 ) >> 4)
++#define GET_PAD11_OD (((REG32(ADR_PAD11)) & 0x00000100 ) >> 8)
++#define GET_PAD11_SEL_O (((REG32(ADR_PAD11)) & 0x00001000 ) >> 12)
++#define GET_XPA_EN_O_C (((REG32(ADR_PAD11)) & 0x10000000 ) >> 28)
++#define GET_PAD15_OE (((REG32(ADR_PAD15)) & 0x00000001 ) >> 0)
++#define GET_PAD15_PE (((REG32(ADR_PAD15)) & 0x00000002 ) >> 1)
++#define GET_PAD15_DS (((REG32(ADR_PAD15)) & 0x00000004 ) >> 2)
++#define GET_PAD15_IE (((REG32(ADR_PAD15)) & 0x00000008 ) >> 3)
++#define GET_PAD15_SEL_I (((REG32(ADR_PAD15)) & 0x00000030 ) >> 4)
++#define GET_PAD15_OD (((REG32(ADR_PAD15)) & 0x00000100 ) >> 8)
++#define GET_PAD15_SEL_O (((REG32(ADR_PAD15)) & 0x00001000 ) >> 12)
++#define GET_TEST_1_ID (((REG32(ADR_PAD15)) & 0x10000000 ) >> 28)
++#define GET_PAD16_OE (((REG32(ADR_PAD16)) & 0x00000001 ) >> 0)
++#define GET_PAD16_PE (((REG32(ADR_PAD16)) & 0x00000002 ) >> 1)
++#define GET_PAD16_DS (((REG32(ADR_PAD16)) & 0x00000004 ) >> 2)
++#define GET_PAD16_IE (((REG32(ADR_PAD16)) & 0x00000008 ) >> 3)
++#define GET_PAD16_SEL_I (((REG32(ADR_PAD16)) & 0x00000030 ) >> 4)
++#define GET_PAD16_OD (((REG32(ADR_PAD16)) & 0x00000100 ) >> 8)
++#define GET_PAD16_SEL_O (((REG32(ADR_PAD16)) & 0x00001000 ) >> 12)
++#define GET_TEST_2_ID (((REG32(ADR_PAD16)) & 0x10000000 ) >> 28)
++#define GET_PAD17_OE (((REG32(ADR_PAD17)) & 0x00000001 ) >> 0)
++#define GET_PAD17_PE (((REG32(ADR_PAD17)) & 0x00000002 ) >> 1)
++#define GET_PAD17_DS (((REG32(ADR_PAD17)) & 0x00000004 ) >> 2)
++#define GET_PAD17_IE (((REG32(ADR_PAD17)) & 0x00000008 ) >> 3)
++#define GET_PAD17_SEL_I (((REG32(ADR_PAD17)) & 0x00000030 ) >> 4)
++#define GET_PAD17_OD (((REG32(ADR_PAD17)) & 0x00000100 ) >> 8)
++#define GET_PAD17_SEL_O (((REG32(ADR_PAD17)) & 0x00001000 ) >> 12)
++#define GET_TEST_3_ID (((REG32(ADR_PAD17)) & 0x10000000 ) >> 28)
++#define GET_PAD18_OE (((REG32(ADR_PAD18)) & 0x00000001 ) >> 0)
++#define GET_PAD18_PE (((REG32(ADR_PAD18)) & 0x00000002 ) >> 1)
++#define GET_PAD18_DS (((REG32(ADR_PAD18)) & 0x00000004 ) >> 2)
++#define GET_PAD18_IE (((REG32(ADR_PAD18)) & 0x00000008 ) >> 3)
++#define GET_PAD18_SEL_I (((REG32(ADR_PAD18)) & 0x00000030 ) >> 4)
++#define GET_PAD18_OD (((REG32(ADR_PAD18)) & 0x00000100 ) >> 8)
++#define GET_PAD18_SEL_O (((REG32(ADR_PAD18)) & 0x00003000 ) >> 12)
++#define GET_TEST_4_ID (((REG32(ADR_PAD18)) & 0x10000000 ) >> 28)
++#define GET_PAD19_OE (((REG32(ADR_PAD19)) & 0x00000001 ) >> 0)
++#define GET_PAD19_PE (((REG32(ADR_PAD19)) & 0x00000002 ) >> 1)
++#define GET_PAD19_DS (((REG32(ADR_PAD19)) & 0x00000004 ) >> 2)
++#define GET_PAD19_IE (((REG32(ADR_PAD19)) & 0x00000008 ) >> 3)
++#define GET_PAD19_SEL_I (((REG32(ADR_PAD19)) & 0x00000030 ) >> 4)
++#define GET_PAD19_OD (((REG32(ADR_PAD19)) & 0x00000100 ) >> 8)
++#define GET_PAD19_SEL_O (((REG32(ADR_PAD19)) & 0x00007000 ) >> 12)
++#define GET_SHORT_TO_20_ID (((REG32(ADR_PAD19)) & 0x10000000 ) >> 28)
++#define GET_PAD20_OE (((REG32(ADR_PAD20)) & 0x00000001 ) >> 0)
++#define GET_PAD20_PE (((REG32(ADR_PAD20)) & 0x00000002 ) >> 1)
++#define GET_PAD20_DS (((REG32(ADR_PAD20)) & 0x00000004 ) >> 2)
++#define GET_PAD20_IE (((REG32(ADR_PAD20)) & 0x00000008 ) >> 3)
++#define GET_PAD20_SEL_I (((REG32(ADR_PAD20)) & 0x000000f0 ) >> 4)
++#define GET_PAD20_OD (((REG32(ADR_PAD20)) & 0x00000100 ) >> 8)
++#define GET_PAD20_SEL_O (((REG32(ADR_PAD20)) & 0x00003000 ) >> 12)
++#define GET_STRAP0 (((REG32(ADR_PAD20)) & 0x08000000 ) >> 27)
++#define GET_GPIO_TEST_1_ID (((REG32(ADR_PAD20)) & 0x10000000 ) >> 28)
++#define GET_PAD21_OE (((REG32(ADR_PAD21)) & 0x00000001 ) >> 0)
++#define GET_PAD21_PE (((REG32(ADR_PAD21)) & 0x00000002 ) >> 1)
++#define GET_PAD21_DS (((REG32(ADR_PAD21)) & 0x00000004 ) >> 2)
++#define GET_PAD21_IE (((REG32(ADR_PAD21)) & 0x00000008 ) >> 3)
++#define GET_PAD21_SEL_I (((REG32(ADR_PAD21)) & 0x00000070 ) >> 4)
++#define GET_PAD21_OD (((REG32(ADR_PAD21)) & 0x00000100 ) >> 8)
++#define GET_PAD21_SEL_O (((REG32(ADR_PAD21)) & 0x00003000 ) >> 12)
++#define GET_STRAP3 (((REG32(ADR_PAD21)) & 0x08000000 ) >> 27)
++#define GET_GPIO_TEST_2_ID (((REG32(ADR_PAD21)) & 0x10000000 ) >> 28)
++#define GET_PAD22_OE (((REG32(ADR_PAD22)) & 0x00000001 ) >> 0)
++#define GET_PAD22_PE (((REG32(ADR_PAD22)) & 0x00000002 ) >> 1)
++#define GET_PAD22_DS (((REG32(ADR_PAD22)) & 0x00000004 ) >> 2)
++#define GET_PAD22_IE (((REG32(ADR_PAD22)) & 0x00000008 ) >> 3)
++#define GET_PAD22_SEL_I (((REG32(ADR_PAD22)) & 0x00000070 ) >> 4)
++#define GET_PAD22_OD (((REG32(ADR_PAD22)) & 0x00000100 ) >> 8)
++#define GET_PAD22_SEL_O (((REG32(ADR_PAD22)) & 0x00007000 ) >> 12)
++#define GET_PAD22_SEL_OE (((REG32(ADR_PAD22)) & 0x00100000 ) >> 20)
++#define GET_GPIO_TEST_3_ID (((REG32(ADR_PAD22)) & 0x10000000 ) >> 28)
++#define GET_PAD24_OE (((REG32(ADR_PAD24)) & 0x00000001 ) >> 0)
++#define GET_PAD24_PE (((REG32(ADR_PAD24)) & 0x00000002 ) >> 1)
++#define GET_PAD24_DS (((REG32(ADR_PAD24)) & 0x00000004 ) >> 2)
++#define GET_PAD24_IE (((REG32(ADR_PAD24)) & 0x00000008 ) >> 3)
++#define GET_PAD24_SEL_I (((REG32(ADR_PAD24)) & 0x00000030 ) >> 4)
++#define GET_PAD24_OD (((REG32(ADR_PAD24)) & 0x00000100 ) >> 8)
++#define GET_PAD24_SEL_O (((REG32(ADR_PAD24)) & 0x00007000 ) >> 12)
++#define GET_GPIO_TEST_4_ID (((REG32(ADR_PAD24)) & 0x10000000 ) >> 28)
++#define GET_PAD25_OE (((REG32(ADR_PAD25)) & 0x00000001 ) >> 0)
++#define GET_PAD25_PE (((REG32(ADR_PAD25)) & 0x00000002 ) >> 1)
++#define GET_PAD25_DS (((REG32(ADR_PAD25)) & 0x00000004 ) >> 2)
++#define GET_PAD25_IE (((REG32(ADR_PAD25)) & 0x00000008 ) >> 3)
++#define GET_PAD25_SEL_I (((REG32(ADR_PAD25)) & 0x00000070 ) >> 4)
++#define GET_PAD25_OD (((REG32(ADR_PAD25)) & 0x00000100 ) >> 8)
++#define GET_PAD25_SEL_O (((REG32(ADR_PAD25)) & 0x00007000 ) >> 12)
++#define GET_PAD25_SEL_OE (((REG32(ADR_PAD25)) & 0x00100000 ) >> 20)
++#define GET_STRAP1 (((REG32(ADR_PAD25)) & 0x08000000 ) >> 27)
++#define GET_GPIO_1_ID (((REG32(ADR_PAD25)) & 0x10000000 ) >> 28)
++#define GET_PAD27_OE (((REG32(ADR_PAD27)) & 0x00000001 ) >> 0)
++#define GET_PAD27_PE (((REG32(ADR_PAD27)) & 0x00000002 ) >> 1)
++#define GET_PAD27_DS (((REG32(ADR_PAD27)) & 0x00000004 ) >> 2)
++#define GET_PAD27_IE (((REG32(ADR_PAD27)) & 0x00000008 ) >> 3)
++#define GET_PAD27_SEL_I (((REG32(ADR_PAD27)) & 0x00000070 ) >> 4)
++#define GET_PAD27_OD (((REG32(ADR_PAD27)) & 0x00000100 ) >> 8)
++#define GET_PAD27_SEL_O (((REG32(ADR_PAD27)) & 0x00007000 ) >> 12)
++#define GET_GPIO_2_ID (((REG32(ADR_PAD27)) & 0x10000000 ) >> 28)
++#define GET_PAD28_OE (((REG32(ADR_PAD28)) & 0x00000001 ) >> 0)
++#define GET_PAD28_PE (((REG32(ADR_PAD28)) & 0x00000002 ) >> 1)
++#define GET_PAD28_DS (((REG32(ADR_PAD28)) & 0x00000004 ) >> 2)
++#define GET_PAD28_IE (((REG32(ADR_PAD28)) & 0x00000008 ) >> 3)
++#define GET_PAD28_SEL_I (((REG32(ADR_PAD28)) & 0x00000070 ) >> 4)
++#define GET_PAD28_OD (((REG32(ADR_PAD28)) & 0x00000100 ) >> 8)
++#define GET_PAD28_SEL_O (((REG32(ADR_PAD28)) & 0x0000f000 ) >> 12)
++#define GET_PAD28_SEL_OE (((REG32(ADR_PAD28)) & 0x00100000 ) >> 20)
++#define GET_GPIO_3_ID (((REG32(ADR_PAD28)) & 0x10000000 ) >> 28)
++#define GET_PAD29_OE (((REG32(ADR_PAD29)) & 0x00000001 ) >> 0)
++#define GET_PAD29_PE (((REG32(ADR_PAD29)) & 0x00000002 ) >> 1)
++#define GET_PAD29_DS (((REG32(ADR_PAD29)) & 0x00000004 ) >> 2)
++#define GET_PAD29_IE (((REG32(ADR_PAD29)) & 0x00000008 ) >> 3)
++#define GET_PAD29_SEL_I (((REG32(ADR_PAD29)) & 0x00000070 ) >> 4)
++#define GET_PAD29_OD (((REG32(ADR_PAD29)) & 0x00000100 ) >> 8)
++#define GET_PAD29_SEL_O (((REG32(ADR_PAD29)) & 0x00007000 ) >> 12)
++#define GET_GPIO_TEST_5_ID (((REG32(ADR_PAD29)) & 0x10000000 ) >> 28)
++#define GET_PAD30_OE (((REG32(ADR_PAD30)) & 0x00000001 ) >> 0)
++#define GET_PAD30_PE (((REG32(ADR_PAD30)) & 0x00000002 ) >> 1)
++#define GET_PAD30_DS (((REG32(ADR_PAD30)) & 0x00000004 ) >> 2)
++#define GET_PAD30_IE (((REG32(ADR_PAD30)) & 0x00000008 ) >> 3)
++#define GET_PAD30_SEL_I (((REG32(ADR_PAD30)) & 0x00000030 ) >> 4)
++#define GET_PAD30_OD (((REG32(ADR_PAD30)) & 0x00000100 ) >> 8)
++#define GET_PAD30_SEL_O (((REG32(ADR_PAD30)) & 0x00003000 ) >> 12)
++#define GET_TEST_6_ID (((REG32(ADR_PAD30)) & 0x10000000 ) >> 28)
++#define GET_PAD31_OE (((REG32(ADR_PAD31)) & 0x00000001 ) >> 0)
++#define GET_PAD31_PE (((REG32(ADR_PAD31)) & 0x00000002 ) >> 1)
++#define GET_PAD31_DS (((REG32(ADR_PAD31)) & 0x00000004 ) >> 2)
++#define GET_PAD31_IE (((REG32(ADR_PAD31)) & 0x00000008 ) >> 3)
++#define GET_PAD31_SEL_I (((REG32(ADR_PAD31)) & 0x00000030 ) >> 4)
++#define GET_PAD31_OD (((REG32(ADR_PAD31)) & 0x00000100 ) >> 8)
++#define GET_PAD31_SEL_O (((REG32(ADR_PAD31)) & 0x00003000 ) >> 12)
++#define GET_TEST_7_ID (((REG32(ADR_PAD31)) & 0x10000000 ) >> 28)
++#define GET_PAD32_OE (((REG32(ADR_PAD32)) & 0x00000001 ) >> 0)
++#define GET_PAD32_PE (((REG32(ADR_PAD32)) & 0x00000002 ) >> 1)
++#define GET_PAD32_DS (((REG32(ADR_PAD32)) & 0x00000004 ) >> 2)
++#define GET_PAD32_IE (((REG32(ADR_PAD32)) & 0x00000008 ) >> 3)
++#define GET_PAD32_SEL_I (((REG32(ADR_PAD32)) & 0x00000030 ) >> 4)
++#define GET_PAD32_OD (((REG32(ADR_PAD32)) & 0x00000100 ) >> 8)
++#define GET_PAD32_SEL_O (((REG32(ADR_PAD32)) & 0x00003000 ) >> 12)
++#define GET_TEST_8_ID (((REG32(ADR_PAD32)) & 0x10000000 ) >> 28)
++#define GET_PAD33_OE (((REG32(ADR_PAD33)) & 0x00000001 ) >> 0)
++#define GET_PAD33_PE (((REG32(ADR_PAD33)) & 0x00000002 ) >> 1)
++#define GET_PAD33_DS (((REG32(ADR_PAD33)) & 0x00000004 ) >> 2)
++#define GET_PAD33_IE (((REG32(ADR_PAD33)) & 0x00000008 ) >> 3)
++#define GET_PAD33_SEL_I (((REG32(ADR_PAD33)) & 0x00000030 ) >> 4)
++#define GET_PAD33_OD (((REG32(ADR_PAD33)) & 0x00000100 ) >> 8)
++#define GET_PAD33_SEL_O (((REG32(ADR_PAD33)) & 0x00003000 ) >> 12)
++#define GET_TEST_9_ID (((REG32(ADR_PAD33)) & 0x10000000 ) >> 28)
++#define GET_PAD34_OE (((REG32(ADR_PAD34)) & 0x00000001 ) >> 0)
++#define GET_PAD34_PE (((REG32(ADR_PAD34)) & 0x00000002 ) >> 1)
++#define GET_PAD34_DS (((REG32(ADR_PAD34)) & 0x00000004 ) >> 2)
++#define GET_PAD34_IE (((REG32(ADR_PAD34)) & 0x00000008 ) >> 3)
++#define GET_PAD34_SEL_I (((REG32(ADR_PAD34)) & 0x00000030 ) >> 4)
++#define GET_PAD34_OD (((REG32(ADR_PAD34)) & 0x00000100 ) >> 8)
++#define GET_PAD34_SEL_O (((REG32(ADR_PAD34)) & 0x00003000 ) >> 12)
++#define GET_TEST_10_ID (((REG32(ADR_PAD34)) & 0x10000000 ) >> 28)
++#define GET_PAD42_OE (((REG32(ADR_PAD42)) & 0x00000001 ) >> 0)
++#define GET_PAD42_PE (((REG32(ADR_PAD42)) & 0x00000002 ) >> 1)
++#define GET_PAD42_DS (((REG32(ADR_PAD42)) & 0x00000004 ) >> 2)
++#define GET_PAD42_IE (((REG32(ADR_PAD42)) & 0x00000008 ) >> 3)
++#define GET_PAD42_SEL_I (((REG32(ADR_PAD42)) & 0x00000030 ) >> 4)
++#define GET_PAD42_OD (((REG32(ADR_PAD42)) & 0x00000100 ) >> 8)
++#define GET_PAD42_SEL_O (((REG32(ADR_PAD42)) & 0x00001000 ) >> 12)
++#define GET_TEST_11_ID (((REG32(ADR_PAD42)) & 0x10000000 ) >> 28)
++#define GET_PAD43_OE (((REG32(ADR_PAD43)) & 0x00000001 ) >> 0)
++#define GET_PAD43_PE (((REG32(ADR_PAD43)) & 0x00000002 ) >> 1)
++#define GET_PAD43_DS (((REG32(ADR_PAD43)) & 0x00000004 ) >> 2)
++#define GET_PAD43_IE (((REG32(ADR_PAD43)) & 0x00000008 ) >> 3)
++#define GET_PAD43_SEL_I (((REG32(ADR_PAD43)) & 0x00000030 ) >> 4)
++#define GET_PAD43_OD (((REG32(ADR_PAD43)) & 0x00000100 ) >> 8)
++#define GET_PAD43_SEL_O (((REG32(ADR_PAD43)) & 0x00001000 ) >> 12)
++#define GET_TEST_12_ID (((REG32(ADR_PAD43)) & 0x10000000 ) >> 28)
++#define GET_PAD44_OE (((REG32(ADR_PAD44)) & 0x00000001 ) >> 0)
++#define GET_PAD44_PE (((REG32(ADR_PAD44)) & 0x00000002 ) >> 1)
++#define GET_PAD44_DS (((REG32(ADR_PAD44)) & 0x00000004 ) >> 2)
++#define GET_PAD44_IE (((REG32(ADR_PAD44)) & 0x00000008 ) >> 3)
++#define GET_PAD44_SEL_I (((REG32(ADR_PAD44)) & 0x00000030 ) >> 4)
++#define GET_PAD44_OD (((REG32(ADR_PAD44)) & 0x00000100 ) >> 8)
++#define GET_PAD44_SEL_O (((REG32(ADR_PAD44)) & 0x00003000 ) >> 12)
++#define GET_TEST_13_ID (((REG32(ADR_PAD44)) & 0x10000000 ) >> 28)
++#define GET_PAD45_OE (((REG32(ADR_PAD45)) & 0x00000001 ) >> 0)
++#define GET_PAD45_PE (((REG32(ADR_PAD45)) & 0x00000002 ) >> 1)
++#define GET_PAD45_DS (((REG32(ADR_PAD45)) & 0x00000004 ) >> 2)
++#define GET_PAD45_IE (((REG32(ADR_PAD45)) & 0x00000008 ) >> 3)
++#define GET_PAD45_SEL_I (((REG32(ADR_PAD45)) & 0x00000030 ) >> 4)
++#define GET_PAD45_OD (((REG32(ADR_PAD45)) & 0x00000100 ) >> 8)
++#define GET_PAD45_SEL_O (((REG32(ADR_PAD45)) & 0x00003000 ) >> 12)
++#define GET_TEST_14_ID (((REG32(ADR_PAD45)) & 0x10000000 ) >> 28)
++#define GET_PAD46_OE (((REG32(ADR_PAD46)) & 0x00000001 ) >> 0)
++#define GET_PAD46_PE (((REG32(ADR_PAD46)) & 0x00000002 ) >> 1)
++#define GET_PAD46_DS (((REG32(ADR_PAD46)) & 0x00000004 ) >> 2)
++#define GET_PAD46_IE (((REG32(ADR_PAD46)) & 0x00000008 ) >> 3)
++#define GET_PAD46_SEL_I (((REG32(ADR_PAD46)) & 0x00000030 ) >> 4)
++#define GET_PAD46_OD (((REG32(ADR_PAD46)) & 0x00000100 ) >> 8)
++#define GET_PAD46_SEL_O (((REG32(ADR_PAD46)) & 0x00003000 ) >> 12)
++#define GET_TEST_15_ID (((REG32(ADR_PAD46)) & 0x10000000 ) >> 28)
++#define GET_PAD47_OE (((REG32(ADR_PAD47)) & 0x00000001 ) >> 0)
++#define GET_PAD47_PE (((REG32(ADR_PAD47)) & 0x00000002 ) >> 1)
++#define GET_PAD47_DS (((REG32(ADR_PAD47)) & 0x00000004 ) >> 2)
++#define GET_PAD47_SEL_I (((REG32(ADR_PAD47)) & 0x00000030 ) >> 4)
++#define GET_PAD47_OD (((REG32(ADR_PAD47)) & 0x00000100 ) >> 8)
++#define GET_PAD47_SEL_O (((REG32(ADR_PAD47)) & 0x00003000 ) >> 12)
++#define GET_PAD47_SEL_OE (((REG32(ADR_PAD47)) & 0x00100000 ) >> 20)
++#define GET_GPIO_9_ID (((REG32(ADR_PAD47)) & 0x10000000 ) >> 28)
++#define GET_PAD48_OE (((REG32(ADR_PAD48)) & 0x00000001 ) >> 0)
++#define GET_PAD48_PE (((REG32(ADR_PAD48)) & 0x00000002 ) >> 1)
++#define GET_PAD48_DS (((REG32(ADR_PAD48)) & 0x00000004 ) >> 2)
++#define GET_PAD48_IE (((REG32(ADR_PAD48)) & 0x00000008 ) >> 3)
++#define GET_PAD48_SEL_I (((REG32(ADR_PAD48)) & 0x00000070 ) >> 4)
++#define GET_PAD48_OD (((REG32(ADR_PAD48)) & 0x00000100 ) >> 8)
++#define GET_PAD48_PE_SEL (((REG32(ADR_PAD48)) & 0x00000800 ) >> 11)
++#define GET_PAD48_SEL_O (((REG32(ADR_PAD48)) & 0x00003000 ) >> 12)
++#define GET_PAD48_SEL_OE (((REG32(ADR_PAD48)) & 0x00100000 ) >> 20)
++#define GET_GPIO_10_ID (((REG32(ADR_PAD48)) & 0x10000000 ) >> 28)
++#define GET_PAD49_OE (((REG32(ADR_PAD49)) & 0x00000001 ) >> 0)
++#define GET_PAD49_PE (((REG32(ADR_PAD49)) & 0x00000002 ) >> 1)
++#define GET_PAD49_DS (((REG32(ADR_PAD49)) & 0x00000004 ) >> 2)
++#define GET_PAD49_IE (((REG32(ADR_PAD49)) & 0x00000008 ) >> 3)
++#define GET_PAD49_SEL_I (((REG32(ADR_PAD49)) & 0x00000070 ) >> 4)
++#define GET_PAD49_OD (((REG32(ADR_PAD49)) & 0x00000100 ) >> 8)
++#define GET_PAD49_SEL_O (((REG32(ADR_PAD49)) & 0x00003000 ) >> 12)
++#define GET_PAD49_SEL_OE (((REG32(ADR_PAD49)) & 0x00100000 ) >> 20)
++#define GET_GPIO_11_ID (((REG32(ADR_PAD49)) & 0x10000000 ) >> 28)
++#define GET_PAD50_OE (((REG32(ADR_PAD50)) & 0x00000001 ) >> 0)
++#define GET_PAD50_PE (((REG32(ADR_PAD50)) & 0x00000002 ) >> 1)
++#define GET_PAD50_DS (((REG32(ADR_PAD50)) & 0x00000004 ) >> 2)
++#define GET_PAD50_IE (((REG32(ADR_PAD50)) & 0x00000008 ) >> 3)
++#define GET_PAD50_SEL_I (((REG32(ADR_PAD50)) & 0x00000070 ) >> 4)
++#define GET_PAD50_OD (((REG32(ADR_PAD50)) & 0x00000100 ) >> 8)
++#define GET_PAD50_SEL_O (((REG32(ADR_PAD50)) & 0x00003000 ) >> 12)
++#define GET_PAD50_SEL_OE (((REG32(ADR_PAD50)) & 0x00100000 ) >> 20)
++#define GET_GPIO_12_ID (((REG32(ADR_PAD50)) & 0x10000000 ) >> 28)
++#define GET_PAD51_OE (((REG32(ADR_PAD51)) & 0x00000001 ) >> 0)
++#define GET_PAD51_PE (((REG32(ADR_PAD51)) & 0x00000002 ) >> 1)
++#define GET_PAD51_DS (((REG32(ADR_PAD51)) & 0x00000004 ) >> 2)
++#define GET_PAD51_IE (((REG32(ADR_PAD51)) & 0x00000008 ) >> 3)
++#define GET_PAD51_SEL_I (((REG32(ADR_PAD51)) & 0x00000030 ) >> 4)
++#define GET_PAD51_OD (((REG32(ADR_PAD51)) & 0x00000100 ) >> 8)
++#define GET_PAD51_SEL_O (((REG32(ADR_PAD51)) & 0x00001000 ) >> 12)
++#define GET_PAD51_SEL_OE (((REG32(ADR_PAD51)) & 0x00100000 ) >> 20)
++#define GET_GPIO_13_ID (((REG32(ADR_PAD51)) & 0x10000000 ) >> 28)
++#define GET_PAD52_OE (((REG32(ADR_PAD52)) & 0x00000001 ) >> 0)
++#define GET_PAD52_PE (((REG32(ADR_PAD52)) & 0x00000002 ) >> 1)
++#define GET_PAD52_DS (((REG32(ADR_PAD52)) & 0x00000004 ) >> 2)
++#define GET_PAD52_SEL_I (((REG32(ADR_PAD52)) & 0x00000030 ) >> 4)
++#define GET_PAD52_OD (((REG32(ADR_PAD52)) & 0x00000100 ) >> 8)
++#define GET_PAD52_SEL_O (((REG32(ADR_PAD52)) & 0x00001000 ) >> 12)
++#define GET_PAD52_SEL_OE (((REG32(ADR_PAD52)) & 0x00100000 ) >> 20)
++#define GET_GPIO_14_ID (((REG32(ADR_PAD52)) & 0x10000000 ) >> 28)
++#define GET_PAD53_OE (((REG32(ADR_PAD53)) & 0x00000001 ) >> 0)
++#define GET_PAD53_PE (((REG32(ADR_PAD53)) & 0x00000002 ) >> 1)
++#define GET_PAD53_DS (((REG32(ADR_PAD53)) & 0x00000004 ) >> 2)
++#define GET_PAD53_IE (((REG32(ADR_PAD53)) & 0x00000008 ) >> 3)
++#define GET_PAD53_SEL_I (((REG32(ADR_PAD53)) & 0x00000030 ) >> 4)
++#define GET_PAD53_OD (((REG32(ADR_PAD53)) & 0x00000100 ) >> 8)
++#define GET_PAD53_SEL_O (((REG32(ADR_PAD53)) & 0x00001000 ) >> 12)
++#define GET_JTAG_TMS_ID (((REG32(ADR_PAD53)) & 0x10000000 ) >> 28)
++#define GET_PAD54_OE (((REG32(ADR_PAD54)) & 0x00000001 ) >> 0)
++#define GET_PAD54_PE (((REG32(ADR_PAD54)) & 0x00000002 ) >> 1)
++#define GET_PAD54_DS (((REG32(ADR_PAD54)) & 0x00000004 ) >> 2)
++#define GET_PAD54_OD (((REG32(ADR_PAD54)) & 0x00000100 ) >> 8)
++#define GET_PAD54_SEL_O (((REG32(ADR_PAD54)) & 0x00003000 ) >> 12)
++#define GET_JTAG_TCK_ID (((REG32(ADR_PAD54)) & 0x10000000 ) >> 28)
++#define GET_PAD56_PE (((REG32(ADR_PAD56)) & 0x00000002 ) >> 1)
++#define GET_PAD56_DS (((REG32(ADR_PAD56)) & 0x00000004 ) >> 2)
++#define GET_PAD56_SEL_I (((REG32(ADR_PAD56)) & 0x00000010 ) >> 4)
++#define GET_PAD56_OD (((REG32(ADR_PAD56)) & 0x00000100 ) >> 8)
++#define GET_JTAG_TDI_ID (((REG32(ADR_PAD56)) & 0x10000000 ) >> 28)
++#define GET_PAD57_OE (((REG32(ADR_PAD57)) & 0x00000001 ) >> 0)
++#define GET_PAD57_PE (((REG32(ADR_PAD57)) & 0x00000002 ) >> 1)
++#define GET_PAD57_DS (((REG32(ADR_PAD57)) & 0x00000004 ) >> 2)
++#define GET_PAD57_IE (((REG32(ADR_PAD57)) & 0x00000008 ) >> 3)
++#define GET_PAD57_SEL_I (((REG32(ADR_PAD57)) & 0x00000030 ) >> 4)
++#define GET_PAD57_OD (((REG32(ADR_PAD57)) & 0x00000100 ) >> 8)
++#define GET_PAD57_SEL_O (((REG32(ADR_PAD57)) & 0x00003000 ) >> 12)
++#define GET_PAD57_SEL_OE (((REG32(ADR_PAD57)) & 0x00100000 ) >> 20)
++#define GET_JTAG_TDO_ID (((REG32(ADR_PAD57)) & 0x10000000 ) >> 28)
++#define GET_PAD58_OE (((REG32(ADR_PAD58)) & 0x00000001 ) >> 0)
++#define GET_PAD58_PE (((REG32(ADR_PAD58)) & 0x00000002 ) >> 1)
++#define GET_PAD58_DS (((REG32(ADR_PAD58)) & 0x00000004 ) >> 2)
++#define GET_PAD58_IE (((REG32(ADR_PAD58)) & 0x00000008 ) >> 3)
++#define GET_PAD58_SEL_I (((REG32(ADR_PAD58)) & 0x00000030 ) >> 4)
++#define GET_PAD58_OD (((REG32(ADR_PAD58)) & 0x00000100 ) >> 8)
++#define GET_PAD58_SEL_O (((REG32(ADR_PAD58)) & 0x00001000 ) >> 12)
++#define GET_TEST_16_ID (((REG32(ADR_PAD58)) & 0x10000000 ) >> 28)
++#define GET_PAD59_OE (((REG32(ADR_PAD59)) & 0x00000001 ) >> 0)
++#define GET_PAD59_PE (((REG32(ADR_PAD59)) & 0x00000002 ) >> 1)
++#define GET_PAD59_DS (((REG32(ADR_PAD59)) & 0x00000004 ) >> 2)
++#define GET_PAD59_IE (((REG32(ADR_PAD59)) & 0x00000008 ) >> 3)
++#define GET_PAD59_SEL_I (((REG32(ADR_PAD59)) & 0x00000030 ) >> 4)
++#define GET_PAD59_OD (((REG32(ADR_PAD59)) & 0x00000100 ) >> 8)
++#define GET_PAD59_SEL_O (((REG32(ADR_PAD59)) & 0x00001000 ) >> 12)
++#define GET_TEST_17_ID (((REG32(ADR_PAD59)) & 0x10000000 ) >> 28)
++#define GET_PAD60_OE (((REG32(ADR_PAD60)) & 0x00000001 ) >> 0)
++#define GET_PAD60_PE (((REG32(ADR_PAD60)) & 0x00000002 ) >> 1)
++#define GET_PAD60_DS (((REG32(ADR_PAD60)) & 0x00000004 ) >> 2)
++#define GET_PAD60_IE (((REG32(ADR_PAD60)) & 0x00000008 ) >> 3)
++#define GET_PAD60_SEL_I (((REG32(ADR_PAD60)) & 0x00000030 ) >> 4)
++#define GET_PAD60_OD (((REG32(ADR_PAD60)) & 0x00000100 ) >> 8)
++#define GET_PAD60_SEL_O (((REG32(ADR_PAD60)) & 0x00001000 ) >> 12)
++#define GET_TEST_18_ID (((REG32(ADR_PAD60)) & 0x10000000 ) >> 28)
++#define GET_PAD61_OE (((REG32(ADR_PAD61)) & 0x00000001 ) >> 0)
++#define GET_PAD61_PE (((REG32(ADR_PAD61)) & 0x00000002 ) >> 1)
++#define GET_PAD61_DS (((REG32(ADR_PAD61)) & 0x00000004 ) >> 2)
++#define GET_PAD61_IE (((REG32(ADR_PAD61)) & 0x00000008 ) >> 3)
++#define GET_PAD61_SEL_I (((REG32(ADR_PAD61)) & 0x00000010 ) >> 4)
++#define GET_PAD61_OD (((REG32(ADR_PAD61)) & 0x00000100 ) >> 8)
++#define GET_PAD61_SEL_O (((REG32(ADR_PAD61)) & 0x00003000 ) >> 12)
++#define GET_TEST_19_ID (((REG32(ADR_PAD61)) & 0x10000000 ) >> 28)
++#define GET_PAD62_OE (((REG32(ADR_PAD62)) & 0x00000001 ) >> 0)
++#define GET_PAD62_PE (((REG32(ADR_PAD62)) & 0x00000002 ) >> 1)
++#define GET_PAD62_DS (((REG32(ADR_PAD62)) & 0x00000004 ) >> 2)
++#define GET_PAD62_IE (((REG32(ADR_PAD62)) & 0x00000008 ) >> 3)
++#define GET_PAD62_SEL_I (((REG32(ADR_PAD62)) & 0x00000010 ) >> 4)
++#define GET_PAD62_OD (((REG32(ADR_PAD62)) & 0x00000100 ) >> 8)
++#define GET_PAD62_SEL_O (((REG32(ADR_PAD62)) & 0x00001000 ) >> 12)
++#define GET_TEST_20_ID (((REG32(ADR_PAD62)) & 0x10000000 ) >> 28)
++#define GET_PAD64_OE (((REG32(ADR_PAD64)) & 0x00000001 ) >> 0)
++#define GET_PAD64_PE (((REG32(ADR_PAD64)) & 0x00000002 ) >> 1)
++#define GET_PAD64_DS (((REG32(ADR_PAD64)) & 0x00000004 ) >> 2)
++#define GET_PAD64_IE (((REG32(ADR_PAD64)) & 0x00000008 ) >> 3)
++#define GET_PAD64_SEL_I (((REG32(ADR_PAD64)) & 0x00000070 ) >> 4)
++#define GET_PAD64_OD (((REG32(ADR_PAD64)) & 0x00000100 ) >> 8)
++#define GET_PAD64_SEL_O (((REG32(ADR_PAD64)) & 0x00003000 ) >> 12)
++#define GET_PAD64_SEL_OE (((REG32(ADR_PAD64)) & 0x00100000 ) >> 20)
++#define GET_GPIO_15_IP_ID (((REG32(ADR_PAD64)) & 0x10000000 ) >> 28)
++#define GET_PAD65_OE (((REG32(ADR_PAD65)) & 0x00000001 ) >> 0)
++#define GET_PAD65_PE (((REG32(ADR_PAD65)) & 0x00000002 ) >> 1)
++#define GET_PAD65_DS (((REG32(ADR_PAD65)) & 0x00000004 ) >> 2)
++#define GET_PAD65_IE (((REG32(ADR_PAD65)) & 0x00000008 ) >> 3)
++#define GET_PAD65_SEL_I (((REG32(ADR_PAD65)) & 0x00000070 ) >> 4)
++#define GET_PAD65_OD (((REG32(ADR_PAD65)) & 0x00000100 ) >> 8)
++#define GET_PAD65_SEL_O (((REG32(ADR_PAD65)) & 0x00001000 ) >> 12)
++#define GET_GPIO_TEST_7_IN_ID (((REG32(ADR_PAD65)) & 0x10000000 ) >> 28)
++#define GET_PAD66_OE (((REG32(ADR_PAD66)) & 0x00000001 ) >> 0)
++#define GET_PAD66_PE (((REG32(ADR_PAD66)) & 0x00000002 ) >> 1)
++#define GET_PAD66_DS (((REG32(ADR_PAD66)) & 0x00000004 ) >> 2)
++#define GET_PAD66_IE (((REG32(ADR_PAD66)) & 0x00000008 ) >> 3)
++#define GET_PAD66_SEL_I (((REG32(ADR_PAD66)) & 0x00000030 ) >> 4)
++#define GET_PAD66_OD (((REG32(ADR_PAD66)) & 0x00000100 ) >> 8)
++#define GET_PAD66_SEL_O (((REG32(ADR_PAD66)) & 0x00003000 ) >> 12)
++#define GET_GPIO_17_QP_ID (((REG32(ADR_PAD66)) & 0x10000000 ) >> 28)
++#define GET_PAD68_OE (((REG32(ADR_PAD68)) & 0x00000001 ) >> 0)
++#define GET_PAD68_PE (((REG32(ADR_PAD68)) & 0x00000002 ) >> 1)
++#define GET_PAD68_DS (((REG32(ADR_PAD68)) & 0x00000004 ) >> 2)
++#define GET_PAD68_IE (((REG32(ADR_PAD68)) & 0x00000008 ) >> 3)
++#define GET_PAD68_OD (((REG32(ADR_PAD68)) & 0x00000100 ) >> 8)
++#define GET_PAD68_SEL_O (((REG32(ADR_PAD68)) & 0x00001000 ) >> 12)
++#define GET_GPIO_19_ID (((REG32(ADR_PAD68)) & 0x10000000 ) >> 28)
++#define GET_PAD67_OE (((REG32(ADR_PAD67)) & 0x00000001 ) >> 0)
++#define GET_PAD67_PE (((REG32(ADR_PAD67)) & 0x00000002 ) >> 1)
++#define GET_PAD67_DS (((REG32(ADR_PAD67)) & 0x00000004 ) >> 2)
++#define GET_PAD67_IE (((REG32(ADR_PAD67)) & 0x00000008 ) >> 3)
++#define GET_PAD67_SEL_I (((REG32(ADR_PAD67)) & 0x00000070 ) >> 4)
++#define GET_PAD67_OD (((REG32(ADR_PAD67)) & 0x00000100 ) >> 8)
++#define GET_PAD67_SEL_O (((REG32(ADR_PAD67)) & 0x00003000 ) >> 12)
++#define GET_GPIO_TEST_8_QN_ID (((REG32(ADR_PAD67)) & 0x10000000 ) >> 28)
++#define GET_PAD69_OE (((REG32(ADR_PAD69)) & 0x00000001 ) >> 0)
++#define GET_PAD69_PE (((REG32(ADR_PAD69)) & 0x00000002 ) >> 1)
++#define GET_PAD69_DS (((REG32(ADR_PAD69)) & 0x00000004 ) >> 2)
++#define GET_PAD69_IE (((REG32(ADR_PAD69)) & 0x00000008 ) >> 3)
++#define GET_PAD69_SEL_I (((REG32(ADR_PAD69)) & 0x00000030 ) >> 4)
++#define GET_PAD69_OD (((REG32(ADR_PAD69)) & 0x00000100 ) >> 8)
++#define GET_PAD69_SEL_O (((REG32(ADR_PAD69)) & 0x00001000 ) >> 12)
++#define GET_STRAP2 (((REG32(ADR_PAD69)) & 0x08000000 ) >> 27)
++#define GET_GPIO_20_ID (((REG32(ADR_PAD69)) & 0x10000000 ) >> 28)
++#define GET_PAD70_OE (((REG32(ADR_PAD70)) & 0x00000001 ) >> 0)
++#define GET_PAD70_PE (((REG32(ADR_PAD70)) & 0x00000002 ) >> 1)
++#define GET_PAD70_DS (((REG32(ADR_PAD70)) & 0x00000004 ) >> 2)
++#define GET_PAD70_IE (((REG32(ADR_PAD70)) & 0x00000008 ) >> 3)
++#define GET_PAD70_SEL_I (((REG32(ADR_PAD70)) & 0x00000030 ) >> 4)
++#define GET_PAD70_OD (((REG32(ADR_PAD70)) & 0x00000100 ) >> 8)
++#define GET_PAD70_SEL_O (((REG32(ADR_PAD70)) & 0x00007000 ) >> 12)
++#define GET_GPIO_21_ID (((REG32(ADR_PAD70)) & 0x10000000 ) >> 28)
++#define GET_PAD231_OE (((REG32(ADR_PAD231)) & 0x00000001 ) >> 0)
++#define GET_PAD231_PE (((REG32(ADR_PAD231)) & 0x00000002 ) >> 1)
++#define GET_PAD231_DS (((REG32(ADR_PAD231)) & 0x00000004 ) >> 2)
++#define GET_PAD231_IE (((REG32(ADR_PAD231)) & 0x00000008 ) >> 3)
++#define GET_PAD231_OD (((REG32(ADR_PAD231)) & 0x00000100 ) >> 8)
++#define GET_PIN_40_OR_56_ID (((REG32(ADR_PAD231)) & 0x10000000 ) >> 28)
++#define GET_MP_PHY2RX_DATA__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000001 ) >> 0)
++#define GET_MP_PHY2RX_DATA__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000002 ) >> 1)
++#define GET_MP_TX_FF_RPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000004 ) >> 2)
++#define GET_MP_RX_FF_WPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000008 ) >> 3)
++#define GET_MP_RX_FF_WPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000010 ) >> 4)
++#define GET_MP_RX_FF_WPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000020 ) >> 5)
++#define GET_MP_PHY2RX_DATA__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000040 ) >> 6)
++#define GET_MP_PHY2RX_DATA__4_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000080 ) >> 7)
++#define GET_I2CM_SDA_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000300 ) >> 8)
++#define GET_CRYSTAL_OUT_REQ_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000400 ) >> 10)
++#define GET_MP_PHY2RX_DATA__5_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000800 ) >> 11)
++#define GET_MP_PHY2RX_DATA__3_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00001000 ) >> 12)
++#define GET_UART_RXD_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00006000 ) >> 13)
++#define GET_MP_PHY2RX_DATA__6_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00008000 ) >> 15)
++#define GET_DAT_UART_NCTS_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00010000 ) >> 16)
++#define GET_GPIO_LOG_STOP_SEL (((REG32(ADR_PIN_SEL_0)) & 0x000e0000 ) >> 17)
++#define GET_MP_TX_FF_RPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00100000 ) >> 20)
++#define GET_MP_PHY_RX_WRST_N_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00200000 ) >> 21)
++#define GET_EXT_32K_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00c00000 ) >> 22)
++#define GET_MP_PHY2RX_DATA__7_SEL (((REG32(ADR_PIN_SEL_0)) & 0x01000000 ) >> 24)
++#define GET_MP_TX_FF_RPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x02000000 ) >> 25)
++#define GET_PMUINT_WAKE_SEL (((REG32(ADR_PIN_SEL_0)) & 0x1c000000 ) >> 26)
++#define GET_I2CM_SCL_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x20000000 ) >> 29)
++#define GET_MP_MRX_RX_EN_SEL (((REG32(ADR_PIN_SEL_0)) & 0x40000000 ) >> 30)
++#define GET_DAT_UART_RXD_SEL_0 (((REG32(ADR_PIN_SEL_0)) & 0x80000000 ) >> 31)
++#define GET_DAT_UART_RXD_SEL_1 (((REG32(ADR_PIN_SEL_1)) & 0x00000001 ) >> 0)
++#define GET_SPI_DI_SEL (((REG32(ADR_PIN_SEL_1)) & 0x00000002 ) >> 1)
++#define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0)
++#define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0)
++#define GET_MASK_TX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1)
++#define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2)
++#define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3)
++#define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4)
++#define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5)
++#define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6)
++#define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7)
++#define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0)
++#define GET_TX_COMPLETE_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1)
++#define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2)
++#define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3)
++#define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4)
++#define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5)
++#define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6)
++#define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7)
++#define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8)
++#define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9)
++#define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10)
++#define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11)
++#define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0)
++#define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1)
++#define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2)
++#define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3)
++#define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4)
++#define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5)
++#define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7)
++#define GET_RX_PACKET_LENGTH (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x0000ffff ) >> 0)
++#define GET_CARD_FW_DL_STATUS (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x00ff0000 ) >> 16)
++#define GET_TX_RX_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x01000000 ) >> 24)
++#define GET_SDIO_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x02000000 ) >> 25)
++#define GET_CMD52_ABORT_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x10000000 ) >> 28)
++#define GET_CMD52_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x20000000 ) >> 29)
++#define GET_SDIO_PARTIAL_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x40000000 ) >> 30)
++#define GET_SDIO_ALL_RESE_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x80000000 ) >> 31)
++#define GET_RX_PACKET_LENGTH2 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x0000ffff ) >> 0)
++#define GET_RX_INT1 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00010000 ) >> 16)
++#define GET_TX_DONE (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00020000 ) >> 17)
++#define GET_HCI_TRX_FINISH (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00040000 ) >> 18)
++#define GET_ALLOCATE_STATUS (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00080000 ) >> 19)
++#define GET_HCI_INPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00f00000 ) >> 20)
++#define GET_HCI_OUTPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x1f000000 ) >> 24)
++#define GET_AHB_HANG4 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x20000000 ) >> 29)
++#define GET_HCI_IN_QUE_EMPTY (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x40000000 ) >> 30)
++#define GET_SYSTEM_INT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x80000000 ) >> 31)
++#define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0)
++#define GET_SDIO_FIFO_WR_THLD_REG (((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_FIFO_WR_LIMIT_REG (((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_TX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_THLD_FOR_CMD53RD_REG (((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_RX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
++#define GET_START_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x000000ff ) >> 0)
++#define GET_END_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x0000ff00 ) >> 8)
++#define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0)
++#define GET_SDIO_LAST_CMD_INDEX_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x0000003f ) >> 0)
++#define GET_SDIO_LAST_CMD_CRC_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x00007f00 ) >> 8)
++#define GET_SDIO_LAST_CMD_ARG_REG (((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0xffffffff ) >> 0)
++#define GET_SDIO_BUS_STATE_REG (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000001f ) >> 0)
++#define GET_SDIO_BUSY_LONG_CNT (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffff0000 ) >> 16)
++#define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0)
++#define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0)
++#define GET_RESP_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000100 ) >> 8)
++#define GET_DAT_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000200 ) >> 9)
++#define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16)
++#define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17)
++#define GET_WRITE_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x000000ff ) >> 0)
++#define GET_WRITE_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x0000ff00 ) >> 8)
++#define GET_READ_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ff0000 ) >> 16)
++#define GET_READ_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff000000 ) >> 24)
++#define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0)
++#define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0)
++#define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8)
++#define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9)
++#define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10)
++#define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11)
++#define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12)
++#define GET_IO_REG_PORT_REG (((REG32(ADR_IO_REG_PORT_REG)) & 0x0001ffff ) >> 0)
++#define GET_SDIO_FIFO_EMPTY_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_SDIO_FIFO_FULL_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000 ) >> 16)
++#define GET_SDIO_CRC7_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff ) >> 0)
++#define GET_SDIO_CRC16_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000 ) >> 16)
++#define GET_SDIO_RD_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x000001ff ) >> 0)
++#define GET_SDIO_WR_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x01ff0000 ) >> 16)
++#define GET_CMD52_RD_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x000f0000 ) >> 16)
++#define GET_CMD52_WR_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x00f00000 ) >> 20)
++#define GET_SDIO_FIFO_WR_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x000000ff ) >> 0)
++#define GET_SDIO_FIFO_RD_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x0000ff00 ) >> 8)
++#define GET_SDIO_READ_DATA_CTRL (((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0x00010000 ) >> 16)
++#define GET_TX_SIZE_BEFORE_SHIFT (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x000000ff ) >> 0)
++#define GET_TX_SIZE_SHIFT_BITS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00000700 ) >> 8)
++#define GET_SDIO_TX_ALLOC_STATE (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00001000 ) >> 12)
++#define GET_ALLOCATE_STATUS2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00010000 ) >> 16)
++#define GET_NO_ALLOCATE_SEND_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00020000 ) >> 17)
++#define GET_DOUBLE_ALLOCATE_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00040000 ) >> 18)
++#define GET_TX_DONE_STATUS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00080000 ) >> 19)
++#define GET_AHB_HANG2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00100000 ) >> 20)
++#define GET_HCI_TRX_FINISH2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00200000 ) >> 21)
++#define GET_INTR_RX (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00400000 ) >> 22)
++#define GET_HCI_INPUT_QUEUE_FULL (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00800000 ) >> 23)
++#define GET_ALLOCATESTATUS (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000001 ) >> 0)
++#define GET_HCI_TRX_FINISH3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000002 ) >> 1)
++#define GET_HCI_IN_QUE_EMPTY2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000004 ) >> 2)
++#define GET_MTX_MNG_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000008 ) >> 3)
++#define GET_EDCA0_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000010 ) >> 4)
++#define GET_EDCA1_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000020 ) >> 5)
++#define GET_EDCA2_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000040 ) >> 6)
++#define GET_EDCA3_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000080 ) >> 7)
++#define GET_TX_PAGE_REMAIN2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0000ff00 ) >> 8)
++#define GET_TX_ID_REMAIN3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x007f0000 ) >> 16)
++#define GET_HCI_OUTPUT_FF_CNT_0 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00800000 ) >> 23)
++#define GET_HCI_OUTPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0f000000 ) >> 24)
++#define GET_HCI_INPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0xf0000000 ) >> 28)
++#define GET_F1_BLOCK_SIZE_0_REG (((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0x00000fff ) >> 0)
++#define GET_START_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x000000ff ) >> 0)
++#define GET_COMMAND_COUNTER (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ff00 ) >> 8)
++#define GET_CMD_LOG_PART1 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff0000 ) >> 16)
++#define GET_CMD_LOG_PART2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff ) >> 0)
++#define GET_END_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000 ) >> 24)
++#define GET_RX_PACKET_LENGTH3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x0000ffff ) >> 0)
++#define GET_RX_INT3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_TX_ID_REMAIN2 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00fe0000 ) >> 17)
++#define GET_TX_PAGE_REMAIN3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff000000 ) >> 24)
++#define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0)
++#define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16)
++#define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24)
++#define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0)
++#define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8)
++#define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16)
++#define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24)
++#define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0)
++#define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1)
++#define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2)
++#define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3)
++#define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4)
++#define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5)
++#define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6)
++#define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7)
++#define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8)
++#define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24)
++#define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25)
++#define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0)
++#define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6)
++#define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7)
++#define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8)
++#define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8)
++#define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
++#define GET_SPI_MODE (((REG32(ADR_SPI_MODE)) & 0xffffffff ) >> 0)
++#define GET_RX_QUOTA (((REG32(ADR_RX_QUOTA)) & 0x0000ffff ) >> 0)
++#define GET_CONDI_NUM (((REG32(ADR_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
++#define GET_HOST_PATH (((REG32(ADR_HOST_PATH)) & 0x00000001 ) >> 0)
++#define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0)
++#define GET_BRST_MODE (((REG32(ADR_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
++#define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
++#define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
++#define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
++#define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
++#define GET_RX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000002 ) >> 1)
++#define GET_RX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000004 ) >> 2)
++#define GET_TX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000008 ) >> 3)
++#define GET_TX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000010 ) >> 4)
++#define GET_SPI_DOUBLE_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000020 ) >> 5)
++#define GET_SPI_TX_NO_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000040 ) >> 6)
++#define GET_RDATA_RDY (((REG32(ADR_SPI_STS)) & 0x00000080 ) >> 7)
++#define GET_SPI_ALLOC_STATUS (((REG32(ADR_SPI_STS)) & 0x00000100 ) >> 8)
++#define GET_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_SPI_STS)) & 0x00000200 ) >> 9)
++#define GET_RX_LEN (((REG32(ADR_SPI_STS)) & 0xffff0000 ) >> 16)
++#define GET_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
++#define GET_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
++#define GET_SPI_TX_ALLOC_SIZE (((REG32(ADR_TX_ALLOC)) & 0x000000ff ) >> 0)
++#define GET_RD_DAT_CNT (((REG32(ADR_DBG_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RD_STS_CNT (((REG32(ADR_DBG_CNT)) & 0xffff0000 ) >> 16)
++#define GET_JUDGE_CNT (((REG32(ADR_DBG_CNT2)) & 0x0000ffff ) >> 0)
++#define GET_RD_STS_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00010000 ) >> 16)
++#define GET_RD_DAT_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00020000 ) >> 17)
++#define GET_JUDGE_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00040000 ) >> 18)
++#define GET_TX_DONE_CNT (((REG32(ADR_DBG_CNT3)) & 0x0000ffff ) >> 0)
++#define GET_TX_DISCARD_CNT (((REG32(ADR_DBG_CNT3)) & 0xffff0000 ) >> 16)
++#define GET_TX_SET_CNT (((REG32(ADR_DBG_CNT4)) & 0x0000ffff ) >> 0)
++#define GET_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00010000 ) >> 16)
++#define GET_TX_DONE_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00020000 ) >> 17)
++#define GET_TX_SET_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00040000 ) >> 18)
++#define GET_DAT_MODE_OFF (((REG32(ADR_DBG_CNT4)) & 0x00080000 ) >> 19)
++#define GET_TX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x00700000 ) >> 20)
++#define GET_RX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x07000000 ) >> 24)
++#define GET_RX_RDY (((REG32(ADR_INT_TAG)) & 0x00000001 ) >> 0)
++#define GET_SDIO_SYS_INT (((REG32(ADR_INT_TAG)) & 0x00000004 ) >> 2)
++#define GET_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000008 ) >> 3)
++#define GET_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000010 ) >> 4)
++#define GET_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000020 ) >> 5)
++#define GET_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000040 ) >> 6)
++#define GET_TX_LIMIT_INT_IN (((REG32(ADR_INT_TAG)) & 0x00000080 ) >> 7)
++#define GET_SPI_FN1 (((REG32(ADR_INT_TAG)) & 0x00007f00 ) >> 8)
++#define GET_SPI_CLK_EN_INT (((REG32(ADR_INT_TAG)) & 0x00008000 ) >> 15)
++#define GET_SPI_HOST_MASK (((REG32(ADR_INT_TAG)) & 0x00ff0000 ) >> 16)
++#define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0)
++#define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1)
++#define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2)
++#define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3)
++#define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4)
++#define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16)
++#define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17)
++#define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18)
++#define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0)
++#define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14)
++#define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15)
++#define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0)
++#define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16)
++#define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24)
++#define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0)
++#define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0)
++#define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0)
++#define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16)
++#define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17)
++#define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0)
++#define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0)
++#define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1)
++#define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2)
++#define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3)
++#define GET_DMA_RXEND_IE (((REG32(ADR_UART_IER)) & 0x00000040 ) >> 6)
++#define GET_DMA_TXEND_IE (((REG32(ADR_UART_IER)) & 0x00000080 ) >> 7)
++#define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0)
++#define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1)
++#define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2)
++#define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3)
++#define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4)
++#define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5)
++#define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6)
++#define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0)
++#define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2)
++#define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3)
++#define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4)
++#define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5)
++#define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6)
++#define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7)
++#define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0)
++#define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1)
++#define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2)
++#define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3)
++#define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4)
++#define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0)
++#define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1)
++#define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2)
++#define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3)
++#define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4)
++#define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5)
++#define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6)
++#define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7)
++#define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0)
++#define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1)
++#define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2)
++#define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3)
++#define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4)
++#define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5)
++#define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6)
++#define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7)
++#define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0)
++#define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0)
++#define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4)
++#define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0)
++#define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6)
++#define GET_DAT_UART_DATA (((REG32(ADR_DAT_UART_DATA)) & 0x000000ff ) >> 0)
++#define GET_DAT_DATA_RDY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000001 ) >> 0)
++#define GET_DAT_THR_EMPTY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000002 ) >> 1)
++#define GET_DAT_RX_LINESTS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000004 ) >> 2)
++#define GET_DAT_MDM_STS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000008 ) >> 3)
++#define GET_DAT_DMA_RXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000040 ) >> 6)
++#define GET_DAT_DMA_TXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000080 ) >> 7)
++#define GET_DAT_FIFO_EN (((REG32(ADR_DAT_UART_FCR)) & 0x00000001 ) >> 0)
++#define GET_DAT_RXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000002 ) >> 1)
++#define GET_DAT_TXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000004 ) >> 2)
++#define GET_DAT_DMA_MODE (((REG32(ADR_DAT_UART_FCR)) & 0x00000008 ) >> 3)
++#define GET_DAT_EN_AUTO_RTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000010 ) >> 4)
++#define GET_DAT_EN_AUTO_CTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000020 ) >> 5)
++#define GET_DAT_RXFIFO_TRGLVL (((REG32(ADR_DAT_UART_FCR)) & 0x000000c0 ) >> 6)
++#define GET_DAT_WORD_LEN (((REG32(ADR_DAT_UART_LCR)) & 0x00000003 ) >> 0)
++#define GET_DAT_STOP_BIT (((REG32(ADR_DAT_UART_LCR)) & 0x00000004 ) >> 2)
++#define GET_DAT_PARITY_EN (((REG32(ADR_DAT_UART_LCR)) & 0x00000008 ) >> 3)
++#define GET_DAT_EVEN_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000010 ) >> 4)
++#define GET_DAT_FORCE_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000020 ) >> 5)
++#define GET_DAT_SET_BREAK (((REG32(ADR_DAT_UART_LCR)) & 0x00000040 ) >> 6)
++#define GET_DAT_DLAB (((REG32(ADR_DAT_UART_LCR)) & 0x00000080 ) >> 7)
++#define GET_DAT_DTR (((REG32(ADR_DAT_UART_MCR)) & 0x00000001 ) >> 0)
++#define GET_DAT_RTS (((REG32(ADR_DAT_UART_MCR)) & 0x00000002 ) >> 1)
++#define GET_DAT_OUT_1 (((REG32(ADR_DAT_UART_MCR)) & 0x00000004 ) >> 2)
++#define GET_DAT_OUT_2 (((REG32(ADR_DAT_UART_MCR)) & 0x00000008 ) >> 3)
++#define GET_DAT_LOOP_BACK (((REG32(ADR_DAT_UART_MCR)) & 0x00000010 ) >> 4)
++#define GET_DAT_DATA_RDY (((REG32(ADR_DAT_UART_LSR)) & 0x00000001 ) >> 0)
++#define GET_DAT_OVERRUN_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000002 ) >> 1)
++#define GET_DAT_PARITY_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000004 ) >> 2)
++#define GET_DAT_FRAMING_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000008 ) >> 3)
++#define GET_DAT_BREAK_INT (((REG32(ADR_DAT_UART_LSR)) & 0x00000010 ) >> 4)
++#define GET_DAT_THR_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000020 ) >> 5)
++#define GET_DAT_TX_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000040 ) >> 6)
++#define GET_DAT_FIFODATA_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000080 ) >> 7)
++#define GET_DAT_DELTA_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000001 ) >> 0)
++#define GET_DAT_DELTA_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000002 ) >> 1)
++#define GET_DAT_TRAILEDGE_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000004 ) >> 2)
++#define GET_DAT_DELTA_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000008 ) >> 3)
++#define GET_DAT_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000010 ) >> 4)
++#define GET_DAT_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000020 ) >> 5)
++#define GET_DAT_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000040 ) >> 6)
++#define GET_DAT_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000080 ) >> 7)
++#define GET_DAT_BRDC_DIV (((REG32(ADR_DAT_UART_SPR)) & 0x0000ffff ) >> 0)
++#define GET_DAT_RTHR_L (((REG32(ADR_DAT_UART_RTHR)) & 0x0000000f ) >> 0)
++#define GET_DAT_RTHR_H (((REG32(ADR_DAT_UART_RTHR)) & 0x000000f0 ) >> 4)
++#define GET_DAT_INT_IDCODE (((REG32(ADR_DAT_UART_ISR)) & 0x0000000f ) >> 0)
++#define GET_DAT_FIFOS_ENABLED (((REG32(ADR_DAT_UART_ISR)) & 0x000000c0 ) >> 6)
++#define GET_MASK_TOP (((REG32(ADR_INT_MASK)) & 0xffffffff ) >> 0)
++#define GET_INT_MODE (((REG32(ADR_INT_MODE)) & 0xffffffff ) >> 0)
++#define GET_IRQ_PHY_0 (((REG32(ADR_INT_IRQ_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_PHY_1 (((REG32(ADR_INT_IRQ_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_SDIO (((REG32(ADR_INT_IRQ_STS)) & 0x00000004 ) >> 2)
++#define GET_IRQ_BEACON_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000010 ) >> 4)
++#define GET_IRQ_PRE_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000020 ) >> 5)
++#define GET_IRQ_EDCA0_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000040 ) >> 6)
++#define GET_IRQ_EDCA1_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000080 ) >> 7)
++#define GET_IRQ_EDCA2_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000100 ) >> 8)
++#define GET_IRQ_EDCA3_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000200 ) >> 9)
++#define GET_IRQ_EDCA4_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000400 ) >> 10)
++#define GET_IRQ_BEACON_DTIM (((REG32(ADR_INT_IRQ_STS)) & 0x00001000 ) >> 12)
++#define GET_IRQ_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00002000 ) >> 13)
++#define GET_IRQ_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00004000 ) >> 14)
++#define GET_IRQ_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00008000 ) >> 15)
++#define GET_IRQ_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00010000 ) >> 16)
++#define GET_IRQ_FENCE_HIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00020000 ) >> 17)
++#define GET_IRQ_ILL_ADDR_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00040000 ) >> 18)
++#define GET_IRQ_MBOX (((REG32(ADR_INT_IRQ_STS)) & 0x00080000 ) >> 19)
++#define GET_IRQ_US_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x00100000 ) >> 20)
++#define GET_IRQ_US_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x00200000 ) >> 21)
++#define GET_IRQ_US_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x00400000 ) >> 22)
++#define GET_IRQ_US_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x00800000 ) >> 23)
++#define GET_IRQ_MS_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x01000000 ) >> 24)
++#define GET_IRQ_MS_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_MS_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_MS_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x08000000 ) >> 27)
++#define GET_IRQ_TX_LIMIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x10000000 ) >> 28)
++#define GET_IRQ_DMA0 (((REG32(ADR_INT_IRQ_STS)) & 0x20000000 ) >> 29)
++#define GET_IRQ_CO_DMA (((REG32(ADR_INT_IRQ_STS)) & 0x40000000 ) >> 30)
++#define GET_IRQ_PERI_GROUP (((REG32(ADR_INT_IRQ_STS)) & 0x80000000 ) >> 31)
++#define GET_FIQ_STATUS (((REG32(ADR_INT_FIQ_STS)) & 0xffffffff ) >> 0)
++#define GET_IRQ_RAW (((REG32(ADR_INT_IRQ_RAW)) & 0xffffffff ) >> 0)
++#define GET_FIQ_RAW (((REG32(ADR_INT_FIQ_RAW)) & 0xffffffff ) >> 0)
++#define GET_INT_PERI_MASK (((REG32(ADR_INT_PERI_MASK)) & 0xffffffff ) >> 0)
++#define GET_PERI_RTC (((REG32(ADR_INT_PERI_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_UART0_TX (((REG32(ADR_INT_PERI_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_UART0_RX (((REG32(ADR_INT_PERI_STS)) & 0x00000004 ) >> 2)
++#define GET_PERI_GPI_2 (((REG32(ADR_INT_PERI_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_SPI_IPC (((REG32(ADR_INT_PERI_STS)) & 0x00000010 ) >> 4)
++#define GET_PERI_GPI_1_0 (((REG32(ADR_INT_PERI_STS)) & 0x00000060 ) >> 5)
++#define GET_SCRT_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000080 ) >> 7)
++#define GET_MMU_ALC_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000100 ) >> 8)
++#define GET_MMU_RLS_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000200 ) >> 9)
++#define GET_ID_MNG_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000400 ) >> 10)
++#define GET_MBOX_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000800 ) >> 11)
++#define GET_MBOX_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00001000 ) >> 12)
++#define GET_MBOX_INT_3 (((REG32(ADR_INT_PERI_STS)) & 0x00002000 ) >> 13)
++#define GET_HCI_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00004000 ) >> 14)
++#define GET_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x00008000 ) >> 15)
++#define GET_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x00010000 ) >> 16)
++#define GET_ID_MNG_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00020000 ) >> 17)
++#define GET_DMN_NOHIT_INT (((REG32(ADR_INT_PERI_STS)) & 0x00040000 ) >> 18)
++#define GET_ID_THOLD_RX (((REG32(ADR_INT_PERI_STS)) & 0x00080000 ) >> 19)
++#define GET_ID_THOLD_TX (((REG32(ADR_INT_PERI_STS)) & 0x00100000 ) >> 20)
++#define GET_ID_DOUBLE_RLS (((REG32(ADR_INT_PERI_STS)) & 0x00200000 ) >> 21)
++#define GET_RX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00400000 ) >> 22)
++#define GET_TX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00800000 ) >> 23)
++#define GET_ALL_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x01000000 ) >> 24)
++#define GET_DMN_MCU_INT (((REG32(ADR_INT_PERI_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_DAT_UART_TX (((REG32(ADR_INT_PERI_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_DAT_UART_RX (((REG32(ADR_INT_PERI_STS)) & 0x08000000 ) >> 27)
++#define GET_DAT_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x10000000 ) >> 28)
++#define GET_DAT_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x20000000 ) >> 29)
++#define GET_ALR_ABT_NOCHG_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x40000000 ) >> 30)
++#define GET_TBLNEQ_MNGPKT_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x80000000 ) >> 31)
++#define GET_INTR_PERI_RAW (((REG32(ADR_INT_PERI_RAW)) & 0xffffffff ) >> 0)
++#define GET_INTR_GPI00_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x00000003 ) >> 0)
++#define GET_INTR_GPI01_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x0000000c ) >> 2)
++#define GET_SYS_RST_INT (((REG32(ADR_SYS_INT_FOR_HOST)) & 0x00000001 ) >> 0)
++#define GET_SPI_IPC_ADDR (((REG32(ADR_SPI_IPC)) & 0xffffffff ) >> 0)
++#define GET_SD_MASK_TOP (((REG32(ADR_SDIO_MASK)) & 0xffffffff ) >> 0)
++#define GET_IRQ_PHY_0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_PHY_1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_SDIO_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000004 ) >> 2)
++#define GET_IRQ_BEACON_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000010 ) >> 4)
++#define GET_IRQ_PRE_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000020 ) >> 5)
++#define GET_IRQ_EDCA0_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000040 ) >> 6)
++#define GET_IRQ_EDCA1_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000080 ) >> 7)
++#define GET_IRQ_EDCA2_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000100 ) >> 8)
++#define GET_IRQ_EDCA3_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000200 ) >> 9)
++#define GET_IRQ_EDCA4_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000400 ) >> 10)
++#define GET_IRQ_BEACON_DTIM_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00001000 ) >> 12)
++#define GET_IRQ_EDCA0_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00002000 ) >> 13)
++#define GET_IRQ_EDCA1_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00004000 ) >> 14)
++#define GET_IRQ_EDCA2_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00008000 ) >> 15)
++#define GET_IRQ_EDCA3_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00010000 ) >> 16)
++#define GET_IRQ_FENCE_HIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00020000 ) >> 17)
++#define GET_IRQ_ILL_ADDR_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00040000 ) >> 18)
++#define GET_IRQ_MBOX_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00080000 ) >> 19)
++#define GET_IRQ_US_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00100000 ) >> 20)
++#define GET_IRQ_US_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00200000 ) >> 21)
++#define GET_IRQ_US_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00400000 ) >> 22)
++#define GET_IRQ_US_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00800000 ) >> 23)
++#define GET_IRQ_MS_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x01000000 ) >> 24)
++#define GET_IRQ_MS_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_MS_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_MS_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x08000000 ) >> 27)
++#define GET_IRQ_TX_LIMIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x10000000 ) >> 28)
++#define GET_IRQ_DMA0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x20000000 ) >> 29)
++#define GET_IRQ_CO_DMA_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x40000000 ) >> 30)
++#define GET_IRQ_PERI_GROUP_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x80000000 ) >> 31)
++#define GET_INT_PERI_MASK_SD (((REG32(ADR_SD_PERI_MASK)) & 0xffffffff ) >> 0)
++#define GET_PERI_RTC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_UART0_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_UART0_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000004 ) >> 2)
++#define GET_PERI_GPI_SD_2 (((REG32(ADR_SD_PERI_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_SPI_IPC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000010 ) >> 4)
++#define GET_PERI_GPI_SD_1_0 (((REG32(ADR_SD_PERI_STS)) & 0x00000060 ) >> 5)
++#define GET_SCRT_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000080 ) >> 7)
++#define GET_MMU_ALC_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000100 ) >> 8)
++#define GET_MMU_RLS_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000200 ) >> 9)
++#define GET_ID_MNG_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000400 ) >> 10)
++#define GET_MBOX_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000800 ) >> 11)
++#define GET_MBOX_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00001000 ) >> 12)
++#define GET_MBOX_INT_3_SD (((REG32(ADR_SD_PERI_STS)) & 0x00002000 ) >> 13)
++#define GET_HCI_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00004000 ) >> 14)
++#define GET_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00008000 ) >> 15)
++#define GET_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x00010000 ) >> 16)
++#define GET_ID_MNG_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00020000 ) >> 17)
++#define GET_DMN_NOHIT_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00040000 ) >> 18)
++#define GET_ID_THOLD_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00080000 ) >> 19)
++#define GET_ID_THOLD_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00100000 ) >> 20)
++#define GET_ID_DOUBLE_RLS_SD (((REG32(ADR_SD_PERI_STS)) & 0x00200000 ) >> 21)
++#define GET_RX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00400000 ) >> 22)
++#define GET_TX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00800000 ) >> 23)
++#define GET_ALL_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x01000000 ) >> 24)
++#define GET_DMN_MCU_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_DAT_UART_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_DAT_UART_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x08000000 ) >> 27)
++#define GET_DAT_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x10000000 ) >> 28)
++#define GET_DAT_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x20000000 ) >> 29)
++#define GET_ALR_ABT_NOCHG_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x40000000 ) >> 30)
++#define GET_TBLNEQ_MNGPKT_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x80000000 ) >> 31)
++#define GET_DBG_SPI_MODE (((REG32(ADR_DBG_SPI_MODE)) & 0xffffffff ) >> 0)
++#define GET_DBG_RX_QUOTA (((REG32(ADR_DBG_RX_QUOTA)) & 0x0000ffff ) >> 0)
++#define GET_DBG_CONDI_NUM (((REG32(ADR_DBG_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
++#define GET_DBG_HOST_PATH (((REG32(ADR_DBG_HOST_PATH)) & 0x00000001 ) >> 0)
++#define GET_DBG_TX_SEG (((REG32(ADR_DBG_TX_SEG)) & 0xffffffff ) >> 0)
++#define GET_DBG_BRST_MODE (((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
++#define GET_DBG_CLK_WIDTH (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
++#define GET_DBG_CSN_INTER (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
++#define GET_DBG_BACK_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
++#define GET_DBG_FRONT_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
++#define GET_DBG_RX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000002 ) >> 1)
++#define GET_DBG_RX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000004 ) >> 2)
++#define GET_DBG_TX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000008 ) >> 3)
++#define GET_DBG_TX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000010 ) >> 4)
++#define GET_DBG_SPI_DOUBLE_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000020 ) >> 5)
++#define GET_DBG_SPI_TX_NO_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000040 ) >> 6)
++#define GET_DBG_RDATA_RDY (((REG32(ADR_DBG_SPI_STS)) & 0x00000080 ) >> 7)
++#define GET_DBG_SPI_ALLOC_STATUS (((REG32(ADR_DBG_SPI_STS)) & 0x00000100 ) >> 8)
++#define GET_DBG_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_DBG_SPI_STS)) & 0x00000200 ) >> 9)
++#define GET_DBG_RX_LEN (((REG32(ADR_DBG_SPI_STS)) & 0xffff0000 ) >> 16)
++#define GET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
++#define GET_DBG_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
++#define GET_DBG_SPI_TX_ALLOC_SIZE (((REG32(ADR_DBG_TX_ALLOC)) & 0x000000ff ) >> 0)
++#define GET_DBG_RD_DAT_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff ) >> 0)
++#define GET_DBG_RD_STS_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000 ) >> 16)
++#define GET_DBG_JUDGE_CNT (((REG32(ADR_DBG_DBG_CNT2)) & 0x0000ffff ) >> 0)
++#define GET_DBG_RD_STS_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00010000 ) >> 16)
++#define GET_DBG_RD_DAT_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00020000 ) >> 17)
++#define GET_DBG_JUDGE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00040000 ) >> 18)
++#define GET_DBG_TX_DONE_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff ) >> 0)
++#define GET_DBG_TX_DISCARD_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000 ) >> 16)
++#define GET_DBG_TX_SET_CNT (((REG32(ADR_DBG_DBG_CNT4)) & 0x0000ffff ) >> 0)
++#define GET_DBG_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00010000 ) >> 16)
++#define GET_DBG_TX_DONE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00020000 ) >> 17)
++#define GET_DBG_TX_SET_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00040000 ) >> 18)
++#define GET_DBG_DAT_MODE_OFF (((REG32(ADR_DBG_DBG_CNT4)) & 0x00080000 ) >> 19)
++#define GET_DBG_TX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x00700000 ) >> 20)
++#define GET_DBG_RX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x07000000 ) >> 24)
++#define GET_DBG_RX_RDY (((REG32(ADR_DBG_INT_TAG)) & 0x00000001 ) >> 0)
++#define GET_DBG_SDIO_SYS_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000004 ) >> 2)
++#define GET_DBG_EDCA0_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000008 ) >> 3)
++#define GET_DBG_EDCA1_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000010 ) >> 4)
++#define GET_DBG_EDCA2_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000020 ) >> 5)
++#define GET_DBG_EDCA3_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000040 ) >> 6)
++#define GET_DBG_TX_LIMIT_INT_IN (((REG32(ADR_DBG_INT_TAG)) & 0x00000080 ) >> 7)
++#define GET_DBG_SPI_FN1 (((REG32(ADR_DBG_INT_TAG)) & 0x00007f00 ) >> 8)
++#define GET_DBG_SPI_CLK_EN_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00008000 ) >> 15)
++#define GET_DBG_SPI_HOST_MASK (((REG32(ADR_DBG_INT_TAG)) & 0x00ff0000 ) >> 16)
++#define GET_BOOT_ADDR (((REG32(ADR_BOOT_ADDR)) & 0x00ffffff ) >> 0)
++#define GET_CHECK_SUM_FAIL (((REG32(ADR_BOOT_ADDR)) & 0x80000000 ) >> 31)
++#define GET_VERIFY_DATA (((REG32(ADR_VERIFY_DATA)) & 0xffffffff ) >> 0)
++#define GET_FLASH_ADDR (((REG32(ADR_FLASH_ADDR)) & 0x00ffffff ) >> 0)
++#define GET_FLASH_CMD_CLR (((REG32(ADR_FLASH_ADDR)) & 0x10000000 ) >> 28)
++#define GET_FLASH_DMA_CLR (((REG32(ADR_FLASH_ADDR)) & 0x20000000 ) >> 29)
++#define GET_DMA_EN (((REG32(ADR_FLASH_ADDR)) & 0x40000000 ) >> 30)
++#define GET_DMA_BUSY (((REG32(ADR_FLASH_ADDR)) & 0x80000000 ) >> 31)
++#define GET_SRAM_ADDR (((REG32(ADR_SRAM_ADDR)) & 0xffffffff ) >> 0)
++#define GET_FLASH_DMA_LEN (((REG32(ADR_LEN)) & 0xffffffff ) >> 0)
++#define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000ffff ) >> 0)
++#define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0xffff0000 ) >> 16)
++#define GET_FLASH_CLK_WIDTH (((REG32(ADR_SPI_PARAM2)) & 0x0000ffff ) >> 0)
++#define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00010000 ) >> 16)
++#define GET_FLS_REMAP (((REG32(ADR_SPI_PARAM2)) & 0x00020000 ) >> 17)
++#define GET_PBUS_SWP (((REG32(ADR_SPI_PARAM2)) & 0x00040000 ) >> 18)
++#define GET_BIT_MODE1 (((REG32(ADR_SPI_PARAM2)) & 0x00080000 ) >> 19)
++#define GET_BIT_MODE2 (((REG32(ADR_SPI_PARAM2)) & 0x00100000 ) >> 20)
++#define GET_BIT_MODE4 (((REG32(ADR_SPI_PARAM2)) & 0x00200000 ) >> 21)
++#define GET_BOOT_CHECK_SUM (((REG32(ADR_CHECK_SUM_RESULT)) & 0xffffffff ) >> 0)
++#define GET_CHECK_SUM_TAG (((REG32(ADR_CHECK_SUM_IN_FILE)) & 0xffffffff ) >> 0)
++#define GET_CMD_LEN (((REG32(ADR_COMMAND_LEN)) & 0x0000ffff ) >> 0)
++#define GET_CMD_ADDR (((REG32(ADR_COMMAND_ADDR)) & 0xffffffff ) >> 0)
++#define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
++#define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0)
++#define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0)
++#define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3)
++#define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4)
++#define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7)
++#define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8)
++#define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12)
++#define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13)
++#define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16)
++#define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0)
++#define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8)
++#define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31)
++#define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
++#define GET_SLEEP_WAKE_CNT (((REG32(ADR_PMU_0)) & 0x00ffffff ) >> 0)
++#define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_0)) & 0x07000000 ) >> 24)
++#define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_0)) & 0x08000000 ) >> 27)
++#define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_0)) & 0x70000000 ) >> 28)
++#define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_0)) & 0x80000000 ) >> 31)
++#define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_1)) & 0x000003ff ) >> 0)
++#define GET_RG_RTC_OSC_RES_SW (((REG32(ADR_PMU_1)) & 0x03ff0000 ) >> 16)
++#define GET_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_1)) & 0x80000000 ) >> 31)
++#define GET_RG_DCDC_MODE (((REG32(ADR_PMU_2)) & 0x00000001 ) >> 0)
++#define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_2)) & 0x00000010 ) >> 4)
++#define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_2)) & 0x00000100 ) >> 8)
++#define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_2)) & 0x00001000 ) >> 12)
++#define GET_RG_RTC_RDY_DEGLITCH_TIMER (((REG32(ADR_PMU_2)) & 0x00006000 ) >> 13)
++#define GET_RTC_CAL_ENA (((REG32(ADR_PMU_2)) & 0x00010000 ) >> 16)
++#define GET_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_3)) & 0x00000003 ) >> 0)
++#define GET_DIGI_TOP_POR_MASK (((REG32(ADR_PMU_3)) & 0x00000010 ) >> 4)
++#define GET_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_3)) & 0x00000100 ) >> 8)
++#define GET_RG_RTC_DUMMIES (((REG32(ADR_PMU_3)) & 0xffff0000 ) >> 16)
++#define GET_RTC_EN (((REG32(ADR_RTC_1)) & 0x00000001 ) >> 0)
++#define GET_RTC_SRC (((REG32(ADR_RTC_1)) & 0x00000002 ) >> 1)
++#define GET_RTC_TICK_CNT (((REG32(ADR_RTC_1)) & 0x7fff0000 ) >> 16)
++#define GET_RTC_INT_SEC_MASK (((REG32(ADR_RTC_2)) & 0x00000001 ) >> 0)
++#define GET_RTC_INT_ALARM_MASK (((REG32(ADR_RTC_2)) & 0x00000002 ) >> 1)
++#define GET_RTC_INT_SEC (((REG32(ADR_RTC_2)) & 0x00010000 ) >> 16)
++#define GET_RTC_INT_ALARM (((REG32(ADR_RTC_2)) & 0x00020000 ) >> 17)
++#define GET_RTC_SEC_START_CNT (((REG32(ADR_RTC_3W)) & 0xffffffff ) >> 0)
++#define GET_RTC_SEC_CNT (((REG32(ADR_RTC_3R)) & 0xffffffff ) >> 0)
++#define GET_RTC_SEC_ALARM_VALUE (((REG32(ADR_RTC_4)) & 0xffffffff ) >> 0)
++#define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
++#define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0)
++#define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0)
++#define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3)
++#define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4)
++#define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7)
++#define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8)
++#define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12)
++#define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13)
++#define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16)
++#define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0)
++#define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8)
++#define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31)
++#define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
++#define GET_TRAP_UNKNOWN_TYPE (((REG32(ADR_CONTROL)) & 0x00000001 ) >> 0)
++#define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1)
++#define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2)
++#define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3)
++#define GET_BYPASSS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4)
++#define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5)
++#define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6)
++#define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8)
++#define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12)
++#define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16)
++#define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20)
++#define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21)
++#define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22)
++#define GET_RX_GET_TX_QUEUE_EN (((REG32(ADR_CONTROL)) & 0x02000000 ) >> 25)
++#define GET_HCI_INQ_SEL (((REG32(ADR_CONTROL)) & 0x04000000 ) >> 26)
++#define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28)
++#define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_WAKE_MODE)) & 0x00000001 ) >> 0)
++#define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0)
++#define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16)
++#define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0)
++#define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THREASHOLD)) & 0xffff0000 ) >> 16)
++#define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0)
++#define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0)
++#define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0)
++#define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8)
++#define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16)
++#define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24)
++#define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0)
++#define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8)
++#define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
++#define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
++#define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
++#define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
++#define GET_TX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0xffffffff ) >> 0)
++#define GET_RX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0xffffffff ) >> 0)
++#define GET_HOST_CMD_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0x000000ff ) >> 0)
++#define GET_HOST_EVENT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0x000000ff ) >> 0)
++#define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0x000000ff ) >> 0)
++#define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0x000000ff ) >> 0)
++#define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0x000000ff ) >> 0)
++#define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0x000000ff ) >> 0)
++#define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0x000000ff ) >> 0)
++#define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0x000000ff ) >> 0)
++#define GET_HCI_STATE_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0)
++#define GET_HCI_ST_TIMEOUT_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0xffffffff ) >> 0)
++#define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0)
++#define GET_HCI_MONITOR_REG1 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0)
++#define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0)
++#define GET_HCI_TX_ALLOC_TIME_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0)
++#define GET_HCI_TX_ALLOC_TIME_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x0000ffff ) >> 0)
++#define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x00ff0000 ) >> 16)
++#define GET_HCI_TX_ALLOC_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0xffffffff ) >> 0)
++#define GET_HCI_TX_ALLOC_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x0000ffff ) >> 0)
++#define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ff0000 ) >> 16)
++#define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff000000 ) >> 24)
++#define GET_SDIO_TX_INVALID_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0xffffffff ) >> 0)
++#define GET_SDIO_TX_INVALID_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0x0000ffff ) >> 0)
++#define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0)
++#define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16)
++#define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0)
++#define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0)
++#define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1)
++#define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0)
++#define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0)
++#define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16)
++#define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0)
++#define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0)
++#define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0)
++#define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0)
++#define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0)
++#define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0)
++#define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0)
++#define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0)
++#define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16)
++#define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0)
++#define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16)
++#define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0)
++#define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0)
++#define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0)
++#define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2)
++#define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3)
++#define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4)
++#define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12)
++#define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16)
++#define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0)
++#define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0)
++#define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0)
++#define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0)
++#define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1)
++#define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0)
++#define GET_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16)
++#define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20)
++#define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28)
++#define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0)
++#define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16)
++#define GET_EFS_RDATA_0 (((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_0 (((REG32(ADR_EFUSE_WDATA_0)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_1 (((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_1 (((REG32(ADR_EFUSE_WDATA_1)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_2 (((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_2 (((REG32(ADR_EFUSE_WDATA_2)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_3 (((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_3 (((REG32(ADR_EFUSE_WDATA_3)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_4 (((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_4 (((REG32(ADR_EFUSE_WDATA_4)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_5 (((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_5 (((REG32(ADR_EFUSE_WDATA_5)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_6 (((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_6 (((REG32(ADR_EFUSE_WDATA_6)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_7 (((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_7 (((REG32(ADR_EFUSE_WDATA_7)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RD0_EN (((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD1_EN (((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD2_EN (((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD3_EN (((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD4_EN (((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD5_EN (((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD6_EN (((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD7_EN (((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RBUSY (((REG32(ADR_EFUSE_SPI_BUSY)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RDATA_0 (((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_1 (((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_2 (((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_3 (((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_4 (((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_5 (((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_6 (((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_7 (((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0xffffffff ) >> 0)
++#define GET_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000001 ) >> 0)
++#define GET_FORCE_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000002 ) >> 1)
++#define GET_SMS4_DESCRY_EN (((REG32(ADR_SMS4_CFG1)) & 0x00000010 ) >> 4)
++#define GET_DEC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000001 ) >> 0)
++#define GET_DEC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000002 ) >> 1)
++#define GET_ENC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000004 ) >> 2)
++#define GET_ENC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000008 ) >> 3)
++#define GET_KEY_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000010 ) >> 4)
++#define GET_SMS4_CBC_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000001 ) >> 0)
++#define GET_SMS4_CFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000002 ) >> 1)
++#define GET_SMS4_OFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000004 ) >> 2)
++#define GET_SMS4_START_TRIG (((REG32(ADR_SMS4_TRIG)) & 0x00000001 ) >> 0)
++#define GET_SMS4_BUSY (((REG32(ADR_SMS4_STATUS1)) & 0x00000001 ) >> 0)
++#define GET_SMS4_DONE (((REG32(ADR_SMS4_STATUS2)) & 0x00000001 ) >> 0)
++#define GET_SMS4_DATAIN_0 (((REG32(ADR_SMS4_DATA_IN0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAIN_1 (((REG32(ADR_SMS4_DATA_IN1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAIN_2 (((REG32(ADR_SMS4_DATA_IN2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAIN_3 (((REG32(ADR_SMS4_DATA_IN3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_0 (((REG32(ADR_SMS4_DATA_OUT0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_1 (((REG32(ADR_SMS4_DATA_OUT1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_2 (((REG32(ADR_SMS4_DATA_OUT2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_3 (((REG32(ADR_SMS4_DATA_OUT3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_0 (((REG32(ADR_SMS4_KEY_0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_1 (((REG32(ADR_SMS4_KEY_1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_2 (((REG32(ADR_SMS4_KEY_2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_3 (((REG32(ADR_SMS4_KEY_3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV0 (((REG32(ADR_SMS4_MODE_IV0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV1 (((REG32(ADR_SMS4_MODE_IV1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV2 (((REG32(ADR_SMS4_MODE_IV2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV3 (((REG32(ADR_SMS4_MODE_IV3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC0 (((REG32(ADR_SMS4_OFB_ENC0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC1 (((REG32(ADR_SMS4_OFB_ENC1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC2 (((REG32(ADR_SMS4_OFB_ENC2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC3 (((REG32(ADR_SMS4_OFB_ENC3)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0)
++#define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0)
++#define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0)
++#define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0)
++#define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0)
++#define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0)
++#define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8)
++#define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0)
++#define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0)
++#define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0)
++#define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0)
++#define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0)
++#define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0)
++#define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8)
++#define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31)
++#define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31)
++#define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31)
++#define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0)
++#define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2)
++#define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3)
++#define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0)
++#define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0)
++#define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0)
++#define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0)
++#define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0)
++#define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0)
++#define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0)
++#define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0)
++#define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1)
++#define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0)
++#define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x003f0000 ) >> 16)
++#define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0)
++#define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0)
++#define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0)
++#define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0)
++#define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0)
++#define GET_W0_T0_SEQ (((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T1_SEQ (((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T2_SEQ (((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T3_SEQ (((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T4_SEQ (((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T5_SEQ (((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T6_SEQ (((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T7_SEQ (((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T0_SEQ (((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T1_SEQ (((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T2_SEQ (((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T3_SEQ (((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T4_SEQ (((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T5_SEQ (((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T6_SEQ (((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T7_SEQ (((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0)
++#define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2)
++#define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4)
++#define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6)
++#define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8)
++#define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10)
++#define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12)
++#define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0)
++#define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0)
++#define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0)
++#define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0)
++#define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0)
++#define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0)
++#define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16)
++#define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17)
++#define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18)
++#define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19)
++#define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20)
++#define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21)
++#define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22)
++#define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23)
++#define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24)
++#define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25)
++#define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16)
++#define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17)
++#define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18)
++#define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19)
++#define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20)
++#define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21)
++#define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22)
++#define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23)
++#define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24)
++#define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25)
++#define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0)
++#define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1)
++#define GET_MTX_AMPDU_CRC_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_MTX_FAST_RSP_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6)
++#define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7)
++#define GET_MTX_ACK_DUR0 (((REG32(ADR_MTX_MISC_EN)) & 0x00000100 ) >> 8)
++#define GET_MTX_TSF_AUTO_BCN (((REG32(ADR_MTX_MISC_EN)) & 0x00000400 ) >> 10)
++#define GET_MTX_TSF_AUTO_MISC (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11)
++#define GET_MTX_FORCE_CS_IDLE (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12)
++#define GET_MTX_FORCE_BKF_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13)
++#define GET_MTX_FORCE_DMA_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14)
++#define GET_MTX_FORCE_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15)
++#define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x003f0000 ) >> 16)
++#define GET_MTX_CTS_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00400000 ) >> 22)
++#define GET_MTX_AMPDU_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00800000 ) >> 23)
++#define GET_MTX_EDCCA_TOUT (((REG32(ADR_MTX_EDCCA_TOUT)) & 0x000003ff ) >> 0)
++#define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000002 ) >> 1)
++#define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000008 ) >> 3)
++#define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1)
++#define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3)
++#define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0)
++#define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1)
++#define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5)
++#define GET_MTX_HALT_MNG_UNTIL_DTIM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000040 ) >> 6)
++#define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_AUTO_FLUSH_Q4 (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16)
++#define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0)
++#define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1)
++#define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3)
++#define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16)
++#define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0)
++#define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_PRD)) & 0xff000000 ) >> 24)
++#define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0)
++#define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0)
++#define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x0000007f ) >> 0)
++#define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x03ff0000 ) >> 16)
++#define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x0000007f ) >> 0)
++#define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x03ff0000 ) >> 16)
++#define GET_MTX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000001 ) >> 0)
++#define GET_MRX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000002 ) >> 1)
++#define GET_MTX_DMA_FSM (((REG32(ADR_MTX_STATUS)) & 0x0000001c ) >> 2)
++#define GET_CH_ST_FSM (((REG32(ADR_MTX_STATUS)) & 0x000000e0 ) >> 5)
++#define GET_MTX_GNT_LOCK (((REG32(ADR_MTX_STATUS)) & 0x00000100 ) >> 8)
++#define GET_MTX_DMA_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000200 ) >> 9)
++#define GET_MTX_Q_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000400 ) >> 10)
++#define GET_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00000800 ) >> 11)
++#define GET_MRX_RX_EN (((REG32(ADR_MTX_STATUS)) & 0x00001000 ) >> 12)
++#define GET_DBG_PRTC_PRD (((REG32(ADR_MTX_STATUS)) & 0x00002000 ) >> 13)
++#define GET_DBG_DMA_RDY (((REG32(ADR_MTX_STATUS)) & 0x00004000 ) >> 14)
++#define GET_DBG_WAIT_RSP (((REG32(ADR_MTX_STATUS)) & 0x00008000 ) >> 15)
++#define GET_DBG_CFRM_BUSY (((REG32(ADR_MTX_STATUS)) & 0x00010000 ) >> 16)
++#define GET_DBG_RST (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000001 ) >> 0)
++#define GET_DBG_MODE (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000002 ) >> 1)
++#define GET_MB_REQ_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff ) >> 0)
++#define GET_RX_EN_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000 ) >> 16)
++#define GET_RX_CS_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff ) >> 0)
++#define GET_TX_CCA_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000 ) >> 16)
++#define GET_Q_REQ_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff ) >> 0)
++#define GET_CH_STA0_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000 ) >> 16)
++#define GET_MTX_DUR_RSP_TOUT_B (((REG32(ADR_MTX_DUR_TOUT)) & 0x000000ff ) >> 0)
++#define GET_MTX_DUR_RSP_TOUT_G (((REG32(ADR_MTX_DUR_TOUT)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_DUR_RSP_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x000000ff ) >> 0)
++#define GET_MTX_DUR_BURST_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_DUR_SLOT (((REG32(ADR_MTX_DUR_IFS)) & 0x003f0000 ) >> 16)
++#define GET_MTX_DUR_RSP_EIFS (((REG32(ADR_MTX_DUR_IFS)) & 0xffc00000 ) >> 22)
++#define GET_MTX_DUR_RSP_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x000000ff ) >> 0)
++#define GET_MTX_DUR_BURST_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_DUR_SLOT_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003f0000 ) >> 16)
++#define GET_MTX_DUR_RSP_EIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc00000 ) >> 22)
++#define GET_CH_STA1_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff ) >> 0)
++#define GET_CH_STA2_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000 ) >> 16)
++#define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0)
++#define GET_MTX_MIB_CNT0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x3fffffff ) >> 0)
++#define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30)
++#define GET_MTX_MIB_CNT1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x3fffffff ) >> 0)
++#define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30)
++#define GET_CH_STA3_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff ) >> 0)
++#define GET_CH_STA4_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000 ) >> 16)
++#define GET_TXQ0_MTX_Q_PRE_LD (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ0_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ0_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ0_MTX_Q_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ0_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ0_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ0_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ0_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ0_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ1_MTX_Q_PRE_LD (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ1_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ1_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ1_MTX_Q_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ1_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ1_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ1_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ1_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ1_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ2_MTX_Q_PRE_LD (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ2_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ2_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ2_MTX_Q_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ2_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ2_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ2_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ2_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ2_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ3_MTX_Q_PRE_LD (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ3_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ3_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ3_MTX_Q_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ3_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ3_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ3_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ3_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ3_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ4_MTX_Q_PRE_LD (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ4_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ4_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ4_MTX_Q_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ4_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ4_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ4_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ4_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ4_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0)
++#define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1)
++#define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2)
++#define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4)
++#define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0)
++#define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0)
++#define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0)
++#define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0)
++#define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1)
++#define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2)
++#define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4)
++#define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0)
++#define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0)
++#define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0)
++#define GET_INFO0 (((REG32(ADR_INFO0)) & 0xffffffff ) >> 0)
++#define GET_INFO1 (((REG32(ADR_INFO1)) & 0xffffffff ) >> 0)
++#define GET_INFO2 (((REG32(ADR_INFO2)) & 0xffffffff ) >> 0)
++#define GET_INFO3 (((REG32(ADR_INFO3)) & 0xffffffff ) >> 0)
++#define GET_INFO4 (((REG32(ADR_INFO4)) & 0xffffffff ) >> 0)
++#define GET_INFO5 (((REG32(ADR_INFO5)) & 0xffffffff ) >> 0)
++#define GET_INFO6 (((REG32(ADR_INFO6)) & 0xffffffff ) >> 0)
++#define GET_INFO7 (((REG32(ADR_INFO7)) & 0xffffffff ) >> 0)
++#define GET_INFO8 (((REG32(ADR_INFO8)) & 0xffffffff ) >> 0)
++#define GET_INFO9 (((REG32(ADR_INFO9)) & 0xffffffff ) >> 0)
++#define GET_INFO10 (((REG32(ADR_INFO10)) & 0xffffffff ) >> 0)
++#define GET_INFO11 (((REG32(ADR_INFO11)) & 0xffffffff ) >> 0)
++#define GET_INFO12 (((REG32(ADR_INFO12)) & 0xffffffff ) >> 0)
++#define GET_INFO13 (((REG32(ADR_INFO13)) & 0xffffffff ) >> 0)
++#define GET_INFO14 (((REG32(ADR_INFO14)) & 0xffffffff ) >> 0)
++#define GET_INFO15 (((REG32(ADR_INFO15)) & 0xffffffff ) >> 0)
++#define GET_INFO16 (((REG32(ADR_INFO16)) & 0xffffffff ) >> 0)
++#define GET_INFO17 (((REG32(ADR_INFO17)) & 0xffffffff ) >> 0)
++#define GET_INFO18 (((REG32(ADR_INFO18)) & 0xffffffff ) >> 0)
++#define GET_INFO19 (((REG32(ADR_INFO19)) & 0xffffffff ) >> 0)
++#define GET_INFO20 (((REG32(ADR_INFO20)) & 0xffffffff ) >> 0)
++#define GET_INFO21 (((REG32(ADR_INFO21)) & 0xffffffff ) >> 0)
++#define GET_INFO22 (((REG32(ADR_INFO22)) & 0xffffffff ) >> 0)
++#define GET_INFO23 (((REG32(ADR_INFO23)) & 0xffffffff ) >> 0)
++#define GET_INFO24 (((REG32(ADR_INFO24)) & 0xffffffff ) >> 0)
++#define GET_INFO25 (((REG32(ADR_INFO25)) & 0xffffffff ) >> 0)
++#define GET_INFO26 (((REG32(ADR_INFO26)) & 0xffffffff ) >> 0)
++#define GET_INFO27 (((REG32(ADR_INFO27)) & 0xffffffff ) >> 0)
++#define GET_INFO28 (((REG32(ADR_INFO28)) & 0xffffffff ) >> 0)
++#define GET_INFO29 (((REG32(ADR_INFO29)) & 0xffffffff ) >> 0)
++#define GET_INFO30 (((REG32(ADR_INFO30)) & 0xffffffff ) >> 0)
++#define GET_INFO31 (((REG32(ADR_INFO31)) & 0xffffffff ) >> 0)
++#define GET_INFO32 (((REG32(ADR_INFO32)) & 0xffffffff ) >> 0)
++#define GET_INFO33 (((REG32(ADR_INFO33)) & 0xffffffff ) >> 0)
++#define GET_INFO34 (((REG32(ADR_INFO34)) & 0xffffffff ) >> 0)
++#define GET_INFO35 (((REG32(ADR_INFO35)) & 0xffffffff ) >> 0)
++#define GET_INFO36 (((REG32(ADR_INFO36)) & 0xffffffff ) >> 0)
++#define GET_INFO37 (((REG32(ADR_INFO37)) & 0xffffffff ) >> 0)
++#define GET_INFO38 (((REG32(ADR_INFO38)) & 0xffffffff ) >> 0)
++#define GET_INFO_MASK (((REG32(ADR_INFO_MASK)) & 0xffffffff ) >> 0)
++#define GET_INFO_DEF_RATE (((REG32(ADR_INFO_RATE_OFFSET)) & 0x0000003f ) >> 0)
++#define GET_INFO_MRX_OFFSET (((REG32(ADR_INFO_RATE_OFFSET)) & 0x000f0000 ) >> 16)
++#define GET_BCAST_RATEUNKNOW (((REG32(ADR_INFO_RATE_OFFSET)) & 0x3f000000 ) >> 24)
++#define GET_INFO_IDX_TBL_ADDR (((REG32(ADR_INFO_IDX_ADDR)) & 0xffffffff ) >> 0)
++#define GET_INFO_LEN_TBL_ADDR (((REG32(ADR_INFO_LEN_ADDR)) & 0xffffffff ) >> 0)
++#define GET_IC_TAG_31_0 (((REG32(ADR_IC_TIME_TAG_0)) & 0xffffffff ) >> 0)
++#define GET_IC_TAG_63_32 (((REG32(ADR_IC_TIME_TAG_1)) & 0xffffffff ) >> 0)
++#define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0)
++#define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8)
++#define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16)
++#define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0)
++#define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1)
++#define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2)
++#define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3)
++#define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4)
++#define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5)
++#define GET_ASIC_TAG (((REG32(ADR_MAC_MODE)) & 0xff000000 ) >> 24)
++#define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0)
++#define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
++#define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
++#define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
++#define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
++#define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
++#define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
++#define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
++#define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12)
++#define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
++#define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
++#define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
++#define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
++#define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
++#define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
++#define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
++#define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
++#define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
++#define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16)
++#define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17)
++#define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
++#define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
++#define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
++#define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
++#define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
++#define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
++#define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10)
++#define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
++#define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
++#define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
++#define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
++#define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
++#define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
++#define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
++#define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
++#define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
++#define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
++#define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
++#define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
++#define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
++#define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
++#define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
++#define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
++#define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
++#define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
++#define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
++#define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
++#define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
++#define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
++#define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0)
++#define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2)
++#define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4)
++#define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8)
++#define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16)
++#define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17)
++#define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18)
++#define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21)
++#define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0)
++#define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0)
++#define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0)
++#define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0)
++#define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0)
++#define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0)
++#define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0)
++#define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0)
++#define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3)
++#define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6)
++#define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16)
++#define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0)
++#define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1)
++#define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4)
++#define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5)
++#define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8)
++#define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9)
++#define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10)
++#define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11)
++#define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12)
++#define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16)
++#define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17)
++#define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18)
++#define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19)
++#define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0)
++#define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8)
++#define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16)
++#define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24)
++#define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0)
++#define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1)
++#define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2)
++#define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3)
++#define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4)
++#define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5)
++#define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8)
++#define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9)
++#define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2)
++#define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3)
++#define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4)
++#define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5)
++#define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6)
++#define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7)
++#define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8)
++#define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9)
++#define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10)
++#define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11)
++#define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12)
++#define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13)
++#define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14)
++#define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15)
++#define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16)
++#define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17)
++#define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0)
++#define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0)
++#define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0)
++#define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0)
++#define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0)
++#define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0)
++#define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0)
++#define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0)
++#define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0)
++#define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0)
++#define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0)
++#define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0)
++#define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0)
++#define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0)
++#define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0)
++#define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0)
++#define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0)
++#define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0)
++#define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0)
++#define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0)
++#define GET_CBR_RG_EN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_TX_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_TX_PA_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_TX_DAC_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_RX_AGC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_RX_GAIN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_RFG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_CBR_RG_PGAG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
++#define GET_CBR_RG_MODE (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
++#define GET_CBR_RG_EN_TX_TRSW (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_EN_SX (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
++#define GET_CBR_RG_EN_RX_LNA (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_CBR_RG_EN_RX_MIXER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
++#define GET_CBR_RG_EN_RX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
++#define GET_CBR_RG_EN_RX_LOBUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
++#define GET_CBR_RG_EN_RX_TZ (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_EN_RX_FILTER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_EN_RX_HPF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_EN_RX_RSSI (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
++#define GET_CBR_RG_EN_ADC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
++#define GET_CBR_RG_EN_TX_MOD (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_EN_TX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
++#define GET_CBR_RG_EN_TX_DIV2_BUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
++#define GET_CBR_RG_EN_TX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
++#define GET_CBR_RG_EN_RX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
++#define GET_CBR_RG_SEL_DPLL_CLK (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
++#define GET_CBR_RG_EN_TX_DPD (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_EN_TX_TSSI (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_EN_RX_IQCAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_EN_TX_DAC_CAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_EN_TX_SELF_MIXER (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_EN_TX_DAC_OUT (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_EN_LDO_RX_FE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
++#define GET_CBR_RG_EN_LDO_ABB (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
++#define GET_CBR_RG_EN_LDO_AFE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_EN_SX_CHPLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_EN_SX_LOBFLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_EN_IREF_RX (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_DCDC_MODE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
++#define GET_CBR_RG_LDO_LEVEL_RX_FE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000007 ) >> 0)
++#define GET_CBR_RG_LDO_LEVEL_ABB (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000038 ) >> 3)
++#define GET_CBR_RG_LDO_LEVEL_AFE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
++#define GET_CBR_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
++#define GET_CBR_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00007000 ) >> 12)
++#define GET_CBR_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_CBR_RG_DP_LDO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_CBR_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
++#define GET_CBR_RG_TX_LDO_TX_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x07000000 ) >> 24)
++#define GET_CBR_RG_BUCK_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x38000000 ) >> 27)
++#define GET_CBR_RG_EN_RX_PADSW (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_EN_RX_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_RX_ABBCFIX (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_RX_ABBCTUNE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
++#define GET_CBR_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_RX_ABB_N_MODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_RX_EN_LOOPA (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_RX_FILTERI1ST (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
++#define GET_CBR_RG_RX_FILTERI2ND (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_FILTERI3RD (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
++#define GET_CBR_RG_RX_FILTERI_COURSE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
++#define GET_CBR_RG_RX_FILTERVCM (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
++#define GET_CBR_RG_RX_HPF3M (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_RX_HPF300K (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
++#define GET_CBR_RG_RX_HPFI (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
++#define GET_CBR_RG_RX_HPF_FINALCORNER (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
++#define GET_CBR_RG_RX_HPF_SETTLE1_C (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
++#define GET_CBR_RG_RX_HPF_SETTLE1_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_HPF_SETTLE2_C (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
++#define GET_CBR_RG_RX_HPF_SETTLE2_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_RX_HPF_VCMCON2 (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
++#define GET_CBR_RG_RX_HPF_VCMCON (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
++#define GET_CBR_RG_RX_OUTVCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
++#define GET_CBR_RG_RX_TZI (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
++#define GET_CBR_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_RX_TZ_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
++#define GET_CBR_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
++#define GET_CBR_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_RX_ADCRSSI_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
++#define GET_CBR_RG_RX_REC_LPFCORNER (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
++#define GET_CBR_RG_RSSI_CLOCK_GATING (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_TXPGA_CAPSW (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_TXPGA_MAIN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
++#define GET_CBR_RG_TXPGA_STEER (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
++#define GET_CBR_RG_TXMOD_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_TXLPF_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_CBR_RG_PACELL_EN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_CBR_RG_PABIAS_CTRL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
++#define GET_CBR_RG_PABIAS_AB (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_TX_DIV_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
++#define GET_CBR_RG_TX_LOBUF_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
++#define GET_CBR_RG_RX_SQDC (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
++#define GET_CBR_RG_RX_DIV2_CORE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_RX_LOBUF (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
++#define GET_CBR_RG_TX_DPDGM_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
++#define GET_CBR_RG_TX_DPD_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
++#define GET_CBR_RG_TX_TSSI_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
++#define GET_CBR_RG_TX_TSSI_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
++#define GET_CBR_RG_TX_TSSI_TESTMODE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_TX_TSSI_TEST (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
++#define GET_CBR_RG_RX_HG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_HG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_HG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_HG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_RX_MG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_MG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_MG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_MG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_RX_LG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_LG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_LG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_LG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_RX_ULG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_ULG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_ULG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_HPF1_FAST_SET_X (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_HPF1_FAST_SET_Y (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_HPF1_FAST_SET_Z (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_HPF_T1A (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_HPF_T1B (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000060 ) >> 5)
++#define GET_CBR_RG_HPF_T1C (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000180 ) >> 7)
++#define GET_CBR_RG_RX_LNA_TRI_SEL (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_CBR_RG_RX_LNA_SETTLE (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00001800 ) >> 11)
++#define GET_CBR_RG_ADC_CLKSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_ADC_DIBIAS (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_ADC_DIVR (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_ADC_DVCMI (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_ADC_SAMSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_ADC_STNBY (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_ADC_TESTMODE (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_ADC_TSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
++#define GET_CBR_RG_ADC_VRSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_CBR_RG_DICMP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_CBR_RG_DIOP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
++#define GET_CBR_RG_DACI1ST (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_TX_DACLPF_ICOURSE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
++#define GET_CBR_RG_TX_DACLPF_IFINE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_TX_DACLPF_VCM (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_CBR_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_TX_DAC_IBIAS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_CBR_RG_TX_DAC_OS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
++#define GET_CBR_RG_TX_DAC_RCAL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_TX_DAC_TSEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
++#define GET_CBR_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_TXLPF_BYPASS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_TXLPF_BOOSTI (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_EN_SX_R3 (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_EN_SX_CH (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_EN_SX_CHP (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_EN_SX_DIVCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_EN_SX_VCOBF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_EN_SX_VCO (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_EN_SX_MOD (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000040 ) >> 6)
++#define GET_CBR_RG_EN_SX_LCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000080 ) >> 7)
++#define GET_CBR_RG_EN_SX_DITHER (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_EN_SX_DELCAL (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_EN_SX_PC_BYPASS (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_EN_SX_VT_MON (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_EN_SX_VT_MON_DG (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00001000 ) >> 12)
++#define GET_CBR_RG_EN_SX_DIV (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00002000 ) >> 13)
++#define GET_CBR_RG_EN_SX_LPF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_SX_RFCTRL_F (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x00ffffff ) >> 0)
++#define GET_CBR_RG_SX_SEL_CP (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0f000000 ) >> 24)
++#define GET_CBR_RG_SX_SEL_CS (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0000000 ) >> 28)
++#define GET_CBR_RG_SX_RFCTRL_CH (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000007ff ) >> 0)
++#define GET_CBR_RG_SX_SEL_C3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x00007800 ) >> 11)
++#define GET_CBR_RG_SX_SEL_RS (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000f8000 ) >> 15)
++#define GET_CBR_RG_SX_SEL_R3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x01f00000 ) >> 20)
++#define GET_CBR_RG_SX_SEL_ICHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
++#define GET_CBR_RG_SX_SEL_PCHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
++#define GET_CBR_RG_SX_SEL_CHP_REGOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
++#define GET_CBR_RG_SX_CHP_IOST_POL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
++#define GET_CBR_RG_SX_CHP_IOST (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
++#define GET_CBR_RG_SX_PFDSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_SX_PFD_SET (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
++#define GET_CBR_RG_SX_PFD_SET1 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
++#define GET_CBR_RG_SX_PFD_SET2 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_SX_VBNCAS_SEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
++#define GET_CBR_RG_SX_PFD_RST_H (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
++#define GET_CBR_RG_SX_PFD_TRUP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
++#define GET_CBR_RG_SX_PFD_TRDN (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
++#define GET_CBR_RG_SX_PFD_TRSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
++#define GET_CBR_RG_SX_VCOBA_R (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
++#define GET_CBR_RG_SX_VCORSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
++#define GET_CBR_RG_SX_VCOCUSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
++#define GET_CBR_RG_SX_RXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
++#define GET_CBR_RG_SX_TXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
++#define GET_CBR_RG_SX_VCOBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
++#define GET_CBR_RG_SX_DIVBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
++#define GET_CBR_RG_SX_GNDR_SEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
++#define GET_CBR_RG_SX_DITHER_WEIGHT (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_SX_MOD_ERRCMP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0000000c ) >> 2)
++#define GET_CBR_RG_SX_MOD_ORDER (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_SX_SDM_D1 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000040 ) >> 6)
++#define GET_CBR_RG_SX_SDM_D2 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000080 ) >> 7)
++#define GET_CBR_RG_SDM_PASS (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_SX_RST_H_DIV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_SX_SDM_EDGE (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_SX_XO_GM (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
++#define GET_CBR_RG_SX_REFBYTWO (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
++#define GET_CBR_RG_SX_XO_SWCAP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0003c000 ) >> 14)
++#define GET_CBR_RG_SX_SDMLUT_INV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00040000 ) >> 18)
++#define GET_CBR_RG_SX_LCKEN (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
++#define GET_CBR_RG_SX_PREVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
++#define GET_CBR_RG_SX_PSCONTERVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
++#define GET_CBR_RG_SX_MOD_ERR_DELAY (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x30000000 ) >> 28)
++#define GET_CBR_RG_SX_MODDB (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x40000000 ) >> 30)
++#define GET_CBR_RG_SX_CV_CURVE_SEL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_SX_SEL_DELAY (((REG32(ADR_CBR_SYN_LCK1)) & 0x0000007c ) >> 2)
++#define GET_CBR_RG_SX_REF_CYCLE (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000780 ) >> 7)
++#define GET_CBR_RG_SX_VCOBY16 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_SX_VCOBY32 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00001000 ) >> 12)
++#define GET_CBR_RG_SX_PH (((REG32(ADR_CBR_SYN_LCK1)) & 0x00002000 ) >> 13)
++#define GET_CBR_RG_SX_PL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_SX_VT_MON_MODE (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_SX_VT_TH_HI (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_SX_VT_TH_LO (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_SX_VT_SET (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_SX_VT_MON_TMR (((REG32(ADR_CBR_SYN_LCK2)) & 0x00007fc0 ) >> 6)
++#define GET_CBR_RG_IDEAL_CYCLE (((REG32(ADR_CBR_SYN_LCK2)) & 0x0fff8000 ) >> 15)
++#define GET_CBR_RG_EN_DP_VT_MON (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_DP_VT_TH_HI (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_DP_VT_TH_LO (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_DP_VT_MON_TMR (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00003fe0 ) >> 5)
++#define GET_CBR_RG_DP_CK320BY2 (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_SX_DELCTRL (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x001f8000 ) >> 15)
++#define GET_CBR_RG_DP_OD_TEST (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_DP_BBPLL_BP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_DP_BBPLL_ICP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_DP_BBPLL_IDUAL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_DP_BBPLL_OD_TEST (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
++#define GET_CBR_RG_DP_BBPLL_PD (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_DP_BBPLL_TESTSEL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
++#define GET_CBR_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
++#define GET_CBR_RG_DP_RP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_CBR_RG_DP_RHP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_CBR_RG_DP_DR3 (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00700000 ) >> 20)
++#define GET_CBR_RG_DP_DCP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x07800000 ) >> 23)
++#define GET_CBR_RG_DP_DCS (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x78000000 ) >> 27)
++#define GET_CBR_RG_DP_FBDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x00000fff ) >> 0)
++#define GET_CBR_RG_DP_FODIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003ff000 ) >> 12)
++#define GET_CBR_RG_DP_REFDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00000 ) >> 22)
++#define GET_CBR_RG_IDACAI_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_EN_RCAL (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_RCAL_SPD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_RCAL_TMR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
++#define GET_CBR_RG_RCAL_CODE_CWR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_RCAL_CODE_CWD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
++#define GET_CBR_RG_SX_SUB_SEL_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_SX_SUB_SEL_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x000000fe ) >> 1)
++#define GET_CBR_RG_DP_BBPLL_BS_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_DP_BBPLL_BS_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00007e00 ) >> 9)
++#define GET_CBR_RCAL_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
++#define GET_CBR_DA_LCK_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
++#define GET_CBR_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
++#define GET_CBR_DP_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000008 ) >> 3)
++#define GET_CBR_CH_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000010 ) >> 4)
++#define GET_CBR_DA_R_CODE_LUT (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
++#define GET_CBR_AD_SX_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
++#define GET_CBR_AD_DP_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
++#define GET_CBR_DA_R_CAL_CODE (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
++#define GET_CBR_DA_SX_SUB_SEL (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
++#define GET_CBR_DA_DP_BBPLL_BS (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0003f000 ) >> 12)
++#define GET_CBR_TX_EN (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000001 ) >> 0)
++#define GET_CBR_TX_CNT_RST (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000002 ) >> 1)
++#define GET_CBR_IFS_TIME (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000000fc ) >> 2)
++#define GET_CBR_LENGTH_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000fff00 ) >> 8)
++#define GET_CBR_TX_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xff000000 ) >> 24)
++#define GET_CBR_TC_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0x00ffffff ) >> 0)
++#define GET_CBR_PLCP_PSDU_DATA_MEM (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x000000ff ) >> 0)
++#define GET_CBR_PLCP_PSDU_PREAMBLE_SHORT (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00000100 ) >> 8)
++#define GET_CBR_PLCP_BYTE_LENGTH (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x001ffe00 ) >> 9)
++#define GET_CBR_PLCP_PSDU_RATE (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00600000 ) >> 21)
++#define GET_CBR_TAIL_TIME (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x1f800000 ) >> 23)
++#define GET_CBR_RG_O_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_I_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000002 ) >> 1)
++#define GET_CBR_SEL_ADCKP_INV (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_PAD_DS (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000008 ) >> 3)
++#define GET_CBR_SEL_ADCKP_MUX (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_PAD_DS_CLK (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000020 ) >> 5)
++#define GET_CBR_INTP_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000200 ) >> 9)
++#define GET_CBR_IQ_SWP (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_EN_EXT_DA (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_DIS_DA_OFFSET (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00001000 ) >> 12)
++#define GET_CBR_DBG_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x000f0000 ) >> 16)
++#define GET_CBR_DBG_EN (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_PKT_GEN_TX_CNT (((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0xffffffff ) >> 0)
++#define GET_CBR_TP_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x0000001f ) >> 0)
++#define GET_CBR_IDEAL_IQ_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000020 ) >> 5)
++#define GET_CBR_DATA_OUT_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x000001c0 ) >> 6)
++#define GET_CBR_TWO_TONE_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000200 ) >> 9)
++#define GET_CBR_FREQ_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ff0000 ) >> 16)
++#define GET_CBR_IQ_SCALE (((REG32(ADR_CBR_PATTERN_GEN)) & 0xff000000 ) >> 24)
++#define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0)
++#define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2)
++#define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0)
++#define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0)
++#define GET_HW_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x000007ff ) >> 0)
++#define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0)
++#define GET_PRI_HW_PKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x000007ff ) >> 0)
++#define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0)
++#define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1)
++#define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9)
++#define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10)
++#define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11)
++#define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16)
++#define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24)
++#define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0)
++#define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5)
++#define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11)
++#define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17)
++#define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20)
++#define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23)
++#define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26)
++#define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29)
++#define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0)
++#define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3)
++#define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6)
++#define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000600 ) >> 9)
++#define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00001800 ) >> 11)
++#define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00006000 ) >> 13)
++#define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000f8000 ) >> 15)
++#define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00700000 ) >> 20)
++#define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1)
++#define GET_CH2_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2)
++#define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3)
++#define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4)
++#define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5)
++#define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6)
++#define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7)
++#define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8)
++#define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9)
++#define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10)
++#define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11)
++#define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12)
++#define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13)
++#define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14)
++#define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15)
++#define GET_HALT_CH0 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000001 ) >> 0)
++#define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1)
++#define GET_HALT_CH2 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000004 ) >> 2)
++#define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3)
++#define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4)
++#define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5)
++#define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6)
++#define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7)
++#define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8)
++#define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9)
++#define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10)
++#define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11)
++#define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12)
++#define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13)
++#define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14)
++#define GET_HALT_CH15 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00008000 ) >> 15)
++#define GET_STOP_MBOX (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16)
++#define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20)
++#define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21)
++#define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_CFG)) & 0xff000000 ) >> 24)
++#define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0)
++#define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16)
++#define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18)
++#define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19)
++#define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24)
++#define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31)
++#define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0)
++#define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16)
++#define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0)
++#define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0)
++#define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1)
++#define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2)
++#define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3)
++#define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4)
++#define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5)
++#define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6)
++#define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7)
++#define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8)
++#define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9)
++#define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10)
++#define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11)
++#define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12)
++#define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13)
++#define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14)
++#define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15)
++#define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16)
++#define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17)
++#define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18)
++#define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19)
++#define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20)
++#define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21)
++#define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22)
++#define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23)
++#define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24)
++#define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25)
++#define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26)
++#define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27)
++#define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28)
++#define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29)
++#define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30)
++#define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31)
++#define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1)
++#define GET_CH0_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000001 ) >> 0)
++#define GET_CH1_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000002 ) >> 1)
++#define GET_CH2_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000004 ) >> 2)
++#define GET_CH3_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000008 ) >> 3)
++#define GET_CH4_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000010 ) >> 4)
++#define GET_CH5_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000020 ) >> 5)
++#define GET_CH6_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000040 ) >> 6)
++#define GET_CH7_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000080 ) >> 7)
++#define GET_CH8_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000100 ) >> 8)
++#define GET_CH9_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000200 ) >> 9)
++#define GET_CH10_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000400 ) >> 10)
++#define GET_CH11_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000800 ) >> 11)
++#define GET_CH12_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00001000 ) >> 12)
++#define GET_CH13_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00002000 ) >> 13)
++#define GET_CH14_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00004000 ) >> 14)
++#define GET_CH15_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00008000 ) >> 15)
++#define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0)
++#define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5)
++#define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00000c00 ) >> 10)
++#define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15)
++#define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20)
++#define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25)
++#define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0)
++#define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5)
++#define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10)
++#define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15)
++#define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20)
++#define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25)
++#define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0)
++#define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5)
++#define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000c00 ) >> 10)
++#define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x001f8000 ) >> 15)
++#define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0)
++#define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1)
++#define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2)
++#define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3)
++#define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4)
++#define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5)
++#define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6)
++#define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7)
++#define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8)
++#define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9)
++#define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10)
++#define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11)
++#define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12)
++#define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13)
++#define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14)
++#define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15)
++#define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0)
++#define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1)
++#define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2)
++#define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3)
++#define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4)
++#define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5)
++#define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6)
++#define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7)
++#define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8)
++#define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9)
++#define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10)
++#define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11)
++#define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12)
++#define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13)
++#define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14)
++#define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15)
++#define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31)
++#define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0)
++#define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8)
++#define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16)
++#define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24)
++#define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0)
++#define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8)
++#define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16)
++#define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24)
++#define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0)
++#define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8)
++#define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16)
++#define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24)
++#define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0)
++#define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8)
++#define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16)
++#define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24)
++#define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0)
++#define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1)
++#define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4)
++#define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16)
++#define GET_CH0_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000001 ) >> 0)
++#define GET_CH1_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000002 ) >> 1)
++#define GET_CH2_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000004 ) >> 2)
++#define GET_CH3_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000008 ) >> 3)
++#define GET_CH4_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000010 ) >> 4)
++#define GET_CH5_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000020 ) >> 5)
++#define GET_CH6_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000040 ) >> 6)
++#define GET_CH7_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000080 ) >> 7)
++#define GET_CH8_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000100 ) >> 8)
++#define GET_CH9_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000200 ) >> 9)
++#define GET_CH10_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000400 ) >> 10)
++#define GET_CH11_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000800 ) >> 11)
++#define GET_CH12_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00001000 ) >> 12)
++#define GET_CH13_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00002000 ) >> 13)
++#define GET_CH14_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00004000 ) >> 14)
++#define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0)
++#define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0)
++#define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0)
++#define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0)
++#define GET_GPIO_STOP_EN (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000010 ) >> 4)
++#define GET_GPIO_STOP_POL (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000020 ) >> 5)
++#define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16)
++#define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0)
++#define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0)
++#define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0)
++#define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20)
++#define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0)
++#define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0)
++#define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4)
++#define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8)
++#define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12)
++#define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0)
++#define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0)
++#define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4)
++#define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5)
++#define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6)
++#define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7)
++#define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0)
++#define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1)
++#define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2)
++#define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4)
++#define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5)
++#define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6)
++#define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7)
++#define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8)
++#define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9)
++#define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0)
++#define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1)
++#define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2)
++#define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4)
++#define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5)
++#define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6)
++#define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7)
++#define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8)
++#define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16)
++#define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30)
++#define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31)
++#define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0)
++#define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8)
++#define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0)
++#define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8)
++#define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16)
++#define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17)
++#define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20)
++#define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21)
++#define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24)
++#define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0)
++#define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0)
++#define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0)
++#define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1)
++#define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8)
++#define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0)
++#define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1)
++#define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2)
++#define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3)
++#define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4)
++#define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13)
++#define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22)
++#define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9)
++#define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18)
++#define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0)
++#define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4)
++#define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8)
++#define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12)
++#define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16)
++#define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0)
++#define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8)
++#define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0)
++#define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0)
++#define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16)
++#define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30)
++#define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31)
++#define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0)
++#define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8)
++#define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14)
++#define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18)
++#define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22)
++#define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27)
++#define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0)
++#define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0)
++#define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0)
++#define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0)
++#define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9)
++#define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17)
++#define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9)
++#define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x03e00000 ) >> 21)
++#define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x3c000000 ) >> 26)
++#define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9)
++#define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17)
++#define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22)
++#define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0)
++#define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16)
++#define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0)
++#define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8)
++#define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16)
++#define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0)
++#define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9)
++#define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18)
++#define GET_RG_PMDLBK (((REG32(ADR_PHY_EN_0)) & 0x00000001 ) >> 0)
++#define GET_RG_RDYACK_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000006 ) >> 1)
++#define GET_RG_ADEDGE_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000008 ) >> 3)
++#define GET_RG_SIGN_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000010 ) >> 4)
++#define GET_RG_IQ_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000020 ) >> 5)
++#define GET_RG_Q_INV (((REG32(ADR_PHY_EN_0)) & 0x00000040 ) >> 6)
++#define GET_RG_I_INV (((REG32(ADR_PHY_EN_0)) & 0x00000080 ) >> 7)
++#define GET_RG_BYPASS_ACI (((REG32(ADR_PHY_EN_0)) & 0x00000100 ) >> 8)
++#define GET_RG_LBK_ANA_PATH (((REG32(ADR_PHY_EN_0)) & 0x00000200 ) >> 9)
++#define GET_RG_SPECTRUM_LEAKY_FACTOR (((REG32(ADR_PHY_EN_0)) & 0x00000c00 ) >> 10)
++#define GET_RG_SPECTRUM_BW (((REG32(ADR_PHY_EN_0)) & 0x00003000 ) >> 12)
++#define GET_RG_SPECTRUM_FREQ_MANUAL (((REG32(ADR_PHY_EN_0)) & 0x00004000 ) >> 14)
++#define GET_RG_SPECTRUM_EN (((REG32(ADR_PHY_EN_0)) & 0x00008000 ) >> 15)
++#define GET_RG_TXPWRLVL_SET (((REG32(ADR_PHY_EN_0)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TXPWRLVL_SEL (((REG32(ADR_PHY_EN_0)) & 0x01000000 ) >> 24)
++#define GET_RG_RF_BB_CLK_SEL (((REG32(ADR_PHY_EN_0)) & 0x80000000 ) >> 31)
++#define GET_RG_PHY_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000001 ) >> 0)
++#define GET_RG_PHYRX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000002 ) >> 1)
++#define GET_RG_PHYTX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000004 ) >> 2)
++#define GET_RG_PHY11GN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000008 ) >> 3)
++#define GET_RG_PHY11B_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000010 ) >> 4)
++#define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000020 ) >> 5)
++#define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000040 ) >> 6)
++#define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000100 ) >> 8)
++#define GET_RG_FORCE_11GN_EN (((REG32(ADR_PHY_EN_1)) & 0x00001000 ) >> 12)
++#define GET_RG_FORCE_11B_EN (((REG32(ADR_PHY_EN_1)) & 0x00002000 ) >> 13)
++#define GET_RG_FFT_MEM_CLK_EN_RX (((REG32(ADR_PHY_EN_1)) & 0x00004000 ) >> 14)
++#define GET_RG_FFT_MEM_CLK_EN_TX (((REG32(ADR_PHY_EN_1)) & 0x00008000 ) >> 15)
++#define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_PHY_EN_1)) & 0x000f0000 ) >> 16)
++#define GET_RG_SPECTRUM_FREQ (((REG32(ADR_PHY_EN_1)) & 0x3ff00000 ) >> 20)
++#define GET_SVN_VERSION (((REG32(ADR_SVN_VERSION_REG)) & 0xffffffff ) >> 0)
++#define GET_RG_LENGTH (((REG32(ADR_PHY_PKT_GEN_0)) & 0x0000ffff ) >> 0)
++#define GET_RG_PKT_MODE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00070000 ) >> 16)
++#define GET_RG_CH_BW (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00380000 ) >> 19)
++#define GET_RG_PRM (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00400000 ) >> 22)
++#define GET_RG_SHORTGI (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00800000 ) >> 23)
++#define GET_RG_RATE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x7f000000 ) >> 24)
++#define GET_RG_L_LENGTH (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00000fff ) >> 0)
++#define GET_RG_L_RATE (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00007000 ) >> 12)
++#define GET_RG_SERVICE (((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff0000 ) >> 16)
++#define GET_RG_SMOOTHING (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000001 ) >> 0)
++#define GET_RG_NO_SOUND (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000002 ) >> 1)
++#define GET_RG_AGGREGATE (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000004 ) >> 2)
++#define GET_RG_STBC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000018 ) >> 3)
++#define GET_RG_FEC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000020 ) >> 5)
++#define GET_RG_N_ESS (((REG32(ADR_PHY_PKT_GEN_2)) & 0x000000c0 ) >> 6)
++#define GET_RG_TXPWRLVL (((REG32(ADR_PHY_PKT_GEN_2)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TX_START (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000001 ) >> 0)
++#define GET_RG_IFS_TIME (((REG32(ADR_PHY_PKT_GEN_3)) & 0x000000fc ) >> 2)
++#define GET_RG_CONTINUOUS_DATA (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000100 ) >> 8)
++#define GET_RG_DATA_SEL (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000600 ) >> 9)
++#define GET_RG_TX_D (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TX_CNT_TARGET (((REG32(ADR_PHY_PKT_GEN_4)) & 0xffffffff ) >> 0)
++#define GET_RG_FFT_IFFT_MODE (((REG32(ADR_PHY_REG_00)) & 0x000000c0 ) >> 6)
++#define GET_RG_DAC_DBG_MODE (((REG32(ADR_PHY_REG_00)) & 0x00000100 ) >> 8)
++#define GET_RG_DAC_SGN_SWAP (((REG32(ADR_PHY_REG_00)) & 0x00000200 ) >> 9)
++#define GET_RG_TXD_SEL (((REG32(ADR_PHY_REG_00)) & 0x00000c00 ) >> 10)
++#define GET_RG_UP8X (((REG32(ADR_PHY_REG_00)) & 0x00ff0000 ) >> 16)
++#define GET_RG_IQ_DC_BYP (((REG32(ADR_PHY_REG_00)) & 0x01000000 ) >> 24)
++#define GET_RG_IQ_DC_LEAKY_FACTOR (((REG32(ADR_PHY_REG_00)) & 0x30000000 ) >> 28)
++#define GET_RG_DAC_DCEN (((REG32(ADR_PHY_REG_01)) & 0x00000001 ) >> 0)
++#define GET_RG_DAC_DCQ (((REG32(ADR_PHY_REG_01)) & 0x00003ff0 ) >> 4)
++#define GET_RG_DAC_DCI (((REG32(ADR_PHY_REG_01)) & 0x03ff0000 ) >> 16)
++#define GET_RG_PGA_REFDB_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0x0000007f ) >> 0)
++#define GET_RG_PGA_REFDB_TOP (((REG32(ADR_PHY_REG_02_AGC)) & 0x00007f00 ) >> 8)
++#define GET_RG_PGA_REF_UND (((REG32(ADR_PHY_REG_02_AGC)) & 0x03ff0000 ) >> 16)
++#define GET_RG_RF_REF_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0xf0000000 ) >> 28)
++#define GET_RG_PGAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x0000000f ) >> 0)
++#define GET_RG_PGAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000010 ) >> 4)
++#define GET_RG_RFGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000060 ) >> 5)
++#define GET_RG_RFGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000080 ) >> 7)
++#define GET_RG_WAIT_T_RXAGC (((REG32(ADR_PHY_REG_03_AGC)) & 0x00003f00 ) >> 8)
++#define GET_RG_RXAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00004000 ) >> 14)
++#define GET_RG_RXAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00008000 ) >> 15)
++#define GET_RG_WAIT_T_FINAL (((REG32(ADR_PHY_REG_03_AGC)) & 0x003f0000 ) >> 16)
++#define GET_RG_WAIT_T (((REG32(ADR_PHY_REG_03_AGC)) & 0x3f000000 ) >> 24)
++#define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000000f ) >> 0)
++#define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000000f0 ) >> 4)
++#define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00000f00 ) >> 8)
++#define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000f000 ) >> 12)
++#define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000f0000 ) >> 16)
++#define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00f00000 ) >> 20)
++#define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0f000000 ) >> 24)
++#define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0xf0000000 ) >> 28)
++#define GET_RG_MG_PGA_JB_TH (((REG32(ADR_PHY_REG_05_AGC)) & 0x0000000f ) >> 0)
++#define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x001f0000 ) >> 16)
++#define GET_RG_WR_RFGC_INIT_SET (((REG32(ADR_PHY_REG_05_AGC)) & 0x00600000 ) >> 21)
++#define GET_RG_WR_RFGC_INIT_EN (((REG32(ADR_PHY_REG_05_AGC)) & 0x00800000 ) >> 23)
++#define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x1f000000 ) >> 24)
++#define GET_RG_AGC_THRESHOLD (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x00003fff ) >> 0)
++#define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x007f0000 ) >> 16)
++#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x03000000 ) >> 24)
++#define GET_RG_WR_ACI_GAIN_INI_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x000000ff ) >> 0)
++#define GET_RG_WR_ACI_GAIN_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x0000ff00 ) >> 8)
++#define GET_RG_ACI_DAGC_SET_VALUE_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x007f0000 ) >> 16)
++#define GET_RG_WR_ACI_GAIN_OW_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x80000000 ) >> 31)
++#define GET_RG_ACI_POINT_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x000000ff ) >> 0)
++#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00000300 ) >> 8)
++#define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xff000000 ) >> 24)
++#define GET_RG_ACI_DAGC_SET_VALUE_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000007f ) >> 0)
++#define GET_RG_ACI_GAIN_INI_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000ff00 ) >> 8)
++#define GET_RG_ACI_GAIN_OW_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x00ff0000 ) >> 16)
++#define GET_RG_ACI_GAIN_OW_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x80000000 ) >> 31)
++#define GET_RO_CCA_PWR_MA_11GN (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x0000007f ) >> 0)
++#define GET_RO_ED_STATE (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x00008000 ) >> 15)
++#define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x007f0000 ) >> 16)
++#define GET_RO_PGA_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
++#define GET_RO_RF_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
++#define GET_RO_PGAGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
++#define GET_RO_RFGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
++#define GET_RO_PGA_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
++#define GET_RO_RF_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
++#define GET_RO_PGAGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
++#define GET_RO_RFGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
++#define GET_RO_PGA_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
++#define GET_RO_RF_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
++#define GET_RO_PGAGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
++#define GET_RO_RFGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
++#define GET_RG_TX_DES_RATE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x0000001f ) >> 0)
++#define GET_RG_TX_DES_MODE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x00001f00 ) >> 8)
++#define GET_RG_TX_DES_LEN_LO (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x001f0000 ) >> 16)
++#define GET_RG_TX_DES_LEN_UP (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x1f000000 ) >> 24)
++#define GET_RG_TX_DES_SRVC_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x0000001f ) >> 0)
++#define GET_RG_TX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x00001f00 ) >> 8)
++#define GET_RG_TX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x001f0000 ) >> 16)
++#define GET_RG_TX_DES_TYPE (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x1f000000 ) >> 24)
++#define GET_RG_TX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000001 ) >> 0)
++#define GET_RG_TX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000010 ) >> 4)
++#define GET_RG_TX_DES_RATE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000100 ) >> 8)
++#define GET_RG_TX_DES_MODE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00001000 ) >> 12)
++#define GET_RG_TX_DES_PWRLVL (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x001f0000 ) >> 16)
++#define GET_RG_TX_DES_SRVC_LO (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x1f000000 ) >> 24)
++#define GET_RG_RX_DES_RATE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x0000003f ) >> 0)
++#define GET_RG_RX_DES_MODE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x00003f00 ) >> 8)
++#define GET_RG_RX_DES_LEN_LO (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x003f0000 ) >> 16)
++#define GET_RG_RX_DES_LEN_UP (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x3f000000 ) >> 24)
++#define GET_RG_RX_DES_SRVC_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x0000003f ) >> 0)
++#define GET_RG_RX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x00003f00 ) >> 8)
++#define GET_RG_RX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x003f0000 ) >> 16)
++#define GET_RG_RX_DES_TYPE (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x3f000000 ) >> 24)
++#define GET_RG_RX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000001 ) >> 0)
++#define GET_RG_RX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000010 ) >> 4)
++#define GET_RG_RX_DES_RATE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000100 ) >> 8)
++#define GET_RG_RX_DES_MODE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00001000 ) >> 12)
++#define GET_RG_RX_DES_SNR (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x000f0000 ) >> 16)
++#define GET_RG_RX_DES_RCPI (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00f00000 ) >> 20)
++#define GET_RG_RX_DES_SRVC_LO (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x3f000000 ) >> 24)
++#define GET_RO_TX_DES_EXCP_RATE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x000000ff ) >> 0)
++#define GET_RO_TX_DES_EXCP_CH_BW_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x0000ff00 ) >> 8)
++#define GET_RO_TX_DES_EXCP_MODE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TX_DES_EXCP_RATE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x07000000 ) >> 24)
++#define GET_RG_TX_DES_EXCP_MODE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x70000000 ) >> 28)
++#define GET_RG_TX_DES_EXCP_CLR (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x80000000 ) >> 31)
++#define GET_RG_TX_DES_ACK_WIDTH (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x00000001 ) >> 0)
++#define GET_RG_TX_DES_ACK_PRD (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x0000000e ) >> 1)
++#define GET_RG_RX_DES_SNR_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x003f0000 ) >> 16)
++#define GET_RG_RX_DES_RCPI_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x3f000000 ) >> 24)
++#define GET_RG_TST_TBUS_SEL (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x0000000f ) >> 0)
++#define GET_RG_RSSI_OFFSET (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x00ff0000 ) >> 16)
++#define GET_RG_RSSI_INV (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x01000000 ) >> 24)
++#define GET_RG_TST_ADC_ON (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x40000000 ) >> 30)
++#define GET_RG_TST_EXT_GAIN (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x80000000 ) >> 31)
++#define GET_RG_DAC_Q_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x000003ff ) >> 0)
++#define GET_RG_DAC_I_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x003ff000 ) >> 12)
++#define GET_RG_DAC_EN_MAN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x10000000 ) >> 28)
++#define GET_RG_IQC_FFT_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x20000000 ) >> 29)
++#define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x40000000 ) >> 30)
++#define GET_RG_DAC_MAN_I_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x80000000 ) >> 31)
++#define GET_RO_MRX_EN_CNT (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_PA_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_RFTX_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_DAC_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ff0000 ) >> 16)
++#define GET_RG_SW_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff000000 ) >> 24)
++#define GET_RG_PA_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_RFTX_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_DAC_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ff0000 ) >> 16)
++#define GET_RG_SW_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff000000 ) >> 24)
++#define GET_RG_ANT_SW_0 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000007 ) >> 0)
++#define GET_RG_ANT_SW_1 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000038 ) >> 3)
++#define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MTX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MTX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MRX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MRX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff ) >> 0)
++#define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000 ) >> 16)
++#define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff ) >> 0)
++#define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000 ) >> 16)
++#define GET_RG_MODE_REG_IN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x0000ffff ) >> 0)
++#define GET_RG_PARALLEL_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x00100000 ) >> 20)
++#define GET_RG_MBRUN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x01000000 ) >> 24)
++#define GET_RG_SHIFT_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x10000000 ) >> 28)
++#define GET_RG_MODE_REG_SI_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x20000000 ) >> 29)
++#define GET_RG_SIMULATION_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x40000000 ) >> 30)
++#define GET_RG_DBIST_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x80000000 ) >> 31)
++#define GET_RO_MODE_REG_OUT_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x0000ffff ) >> 0)
++#define GET_RO_MODE_REG_SO_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x01000000 ) >> 24)
++#define GET_RO_MONITOR_BUS_16 (((REG32(ADR_PHY_READ_REG_07_BIST)) & 0x0007ffff ) >> 0)
++#define GET_RG_MRX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x000000ff ) >> 0)
++#define GET_RG_MRX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x0000ff00 ) >> 8)
++#define GET_RG_MTX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ff0000 ) >> 16)
++#define GET_RG_MTX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff000000 ) >> 24)
++#define GET_RO_MTX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff ) >> 0)
++#define GET_RO_MTX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000 ) >> 16)
++#define GET_RO_MRX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff ) >> 0)
++#define GET_RO_MRX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000 ) >> 16)
++#define GET_RG_HB_COEF0 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x00000fff ) >> 0)
++#define GET_RG_HB_COEF1 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
++#define GET_RG_HB_COEF2 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x00000fff ) >> 0)
++#define GET_RG_HB_COEF3 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
++#define GET_RG_HB_COEF4 (((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0x00000fff ) >> 0)
++#define GET_RO_TBUS_O (((REG32(ADR_PHY_READ_TBUS)) & 0x000fffff ) >> 0)
++#define GET_RG_LPF4_00 (((REG32(ADR_TX_11B_FIL_COEF_00)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_01 (((REG32(ADR_TX_11B_FIL_COEF_01)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_02 (((REG32(ADR_TX_11B_FIL_COEF_02)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_03 (((REG32(ADR_TX_11B_FIL_COEF_03)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_04 (((REG32(ADR_TX_11B_FIL_COEF_04)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_05 (((REG32(ADR_TX_11B_FIL_COEF_05)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_06 (((REG32(ADR_TX_11B_FIL_COEF_06)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_07 (((REG32(ADR_TX_11B_FIL_COEF_07)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_08 (((REG32(ADR_TX_11B_FIL_COEF_08)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_09 (((REG32(ADR_TX_11B_FIL_COEF_09)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_10 (((REG32(ADR_TX_11B_FIL_COEF_10)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_11 (((REG32(ADR_TX_11B_FIL_COEF_11)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_12 (((REG32(ADR_TX_11B_FIL_COEF_12)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_13 (((REG32(ADR_TX_11B_FIL_COEF_13)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_14 (((REG32(ADR_TX_11B_FIL_COEF_14)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_15 (((REG32(ADR_TX_11B_FIL_COEF_15)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_16 (((REG32(ADR_TX_11B_FIL_COEF_16)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_17 (((REG32(ADR_TX_11B_FIL_COEF_17)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_18 (((REG32(ADR_TX_11B_FIL_COEF_18)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_19 (((REG32(ADR_TX_11B_FIL_COEF_19)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_20 (((REG32(ADR_TX_11B_FIL_COEF_20)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_21 (((REG32(ADR_TX_11B_FIL_COEF_21)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_22 (((REG32(ADR_TX_11B_FIL_COEF_22)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_23 (((REG32(ADR_TX_11B_FIL_COEF_23)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_24 (((REG32(ADR_TX_11B_FIL_COEF_24)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_25 (((REG32(ADR_TX_11B_FIL_COEF_25)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_26 (((REG32(ADR_TX_11B_FIL_COEF_26)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_27 (((REG32(ADR_TX_11B_FIL_COEF_27)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_28 (((REG32(ADR_TX_11B_FIL_COEF_28)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_29 (((REG32(ADR_TX_11B_FIL_COEF_29)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_30 (((REG32(ADR_TX_11B_FIL_COEF_30)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_31 (((REG32(ADR_TX_11B_FIL_COEF_31)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_32 (((REG32(ADR_TX_11B_FIL_COEF_32)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_33 (((REG32(ADR_TX_11B_FIL_COEF_33)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_34 (((REG32(ADR_TX_11B_FIL_COEF_34)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_35 (((REG32(ADR_TX_11B_FIL_COEF_35)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_36 (((REG32(ADR_TX_11B_FIL_COEF_36)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_37 (((REG32(ADR_TX_11B_FIL_COEF_37)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_38 (((REG32(ADR_TX_11B_FIL_COEF_38)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_39 (((REG32(ADR_TX_11B_FIL_COEF_39)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_40 (((REG32(ADR_TX_11B_FIL_COEF_40)) & 0x00001fff ) >> 0)
++#define GET_RG_BP_SMB (((REG32(ADR_TX_11B_PLCP)) & 0x00002000 ) >> 13)
++#define GET_RG_EN_SRVC (((REG32(ADR_TX_11B_PLCP)) & 0x00004000 ) >> 14)
++#define GET_RG_DES_SPD (((REG32(ADR_TX_11B_PLCP)) & 0x00030000 ) >> 16)
++#define GET_RG_BB_11B_RISE_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_BB_11B_FALL_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_WR_TX_EN_CNT_RST_N (((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0x00000001 ) >> 0)
++#define GET_RO_TX_EN_CNT (((REG32(ADR_TX_11B_EN_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RO_TX_CNT (((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
++#define GET_RG_POS_DES_11B_L_EXT (((REG32(ADR_RX_11B_DES_DLY)) & 0x0000000f ) >> 0)
++#define GET_RG_PRE_DES_11B_DLY (((REG32(ADR_RX_11B_DES_DLY)) & 0x000000f0 ) >> 4)
++#define GET_RG_CNT_CCA_LMT (((REG32(ADR_RX_11B_CCA_0)) & 0x000f0000 ) >> 16)
++#define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_RX_11B_CCA_0)) & 0x20000000 ) >> 29)
++#define GET_RG_BYPASS_AGC (((REG32(ADR_RX_11B_CCA_0)) & 0x80000000 ) >> 31)
++#define GET_RG_CCA_BIT_CNT_LMT_RX (((REG32(ADR_RX_11B_CCA_1)) & 0x000000f0 ) >> 4)
++#define GET_RG_CCA_SCALE_BF (((REG32(ADR_RX_11B_CCA_1)) & 0x007f0000 ) >> 16)
++#define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_RX_11B_CCA_1)) & 0x30000000 ) >> 28)
++#define GET_RG_TR_KI_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000007 ) >> 0)
++#define GET_RG_TR_KP_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000070 ) >> 4)
++#define GET_RG_TR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000700 ) >> 8)
++#define GET_RG_TR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00007000 ) >> 12)
++#define GET_RG_CR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00070000 ) >> 16)
++#define GET_RG_CR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00700000 ) >> 20)
++#define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000001f ) >> 0)
++#define GET_RG_CE_T4_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000ff00 ) >> 8)
++#define GET_RG_CE_T3_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ff0000 ) >> 16)
++#define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff000000 ) >> 24)
++#define GET_RG_CE_MU_T1 (((REG32(ADR_RX_11B_CE_MU_0)) & 0x00000007 ) >> 0)
++#define GET_RG_CE_DLY_SEL (((REG32(ADR_RX_11B_CE_MU_0)) & 0x003f0000 ) >> 16)
++#define GET_RG_CE_MU_T8 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000007 ) >> 0)
++#define GET_RG_CE_MU_T7 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000070 ) >> 4)
++#define GET_RG_CE_MU_T6 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000700 ) >> 8)
++#define GET_RG_CE_MU_T5 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00007000 ) >> 12)
++#define GET_RG_CE_MU_T4 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00070000 ) >> 16)
++#define GET_RG_CE_MU_T3 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00700000 ) >> 20)
++#define GET_RG_CE_MU_T2 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x07000000 ) >> 24)
++#define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x0000000f ) >> 0)
++#define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000000f0 ) >> 4)
++#define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000f0000 ) >> 16)
++#define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x00f00000 ) >> 20)
++#define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x0000000f ) >> 0)
++#define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000000f0 ) >> 4)
++#define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000f0000 ) >> 16)
++#define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x00f00000 ) >> 20)
++#define GET_RG_EQ_KI_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00000700 ) >> 8)
++#define GET_RG_EQ_KP_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00007000 ) >> 12)
++#define GET_RG_EQ_KI_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00070000 ) >> 16)
++#define GET_RG_EQ_KP_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00700000 ) >> 20)
++#define GET_RG_TR_LPF_RATE (((REG32(ADR_RX_11B_LPF_RATE)) & 0x003fffff ) >> 0)
++#define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x0000007f ) >> 0)
++#define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00000080 ) >> 7)
++#define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00007f00 ) >> 8)
++#define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x007f0000 ) >> 16)
++#define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x7f000000 ) >> 24)
++#define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x00000001 ) >> 0)
++#define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x07ff0000 ) >> 16)
++#define GET_RG_PWRON_DLY_TH_11B (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x000000ff ) >> 0)
++#define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x00ff0000 ) >> 16)
++#define GET_RG_CCA_PWR_TH_RX (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x00007fff ) >> 0)
++#define GET_RG_CCA_PWR_CNT_TH (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x001f0000 ) >> 16)
++#define GET_B_FREQ_OS (((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0x000007ff ) >> 0)
++#define GET_B_SNR (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x0000007f ) >> 0)
++#define GET_B_RCPI (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x007f0000 ) >> 16)
++#define GET_CRC_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff ) >> 0)
++#define GET_SFD_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000 ) >> 16)
++#define GET_B_PACKET_ERR_CNT (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_PACKET_ERR (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x00010000 ) >> 16)
++#define GET_B_PACKET_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
++#define GET_B_CCA_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
++#define GET_B_LENGTH_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff ) >> 0)
++#define GET_SFD_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000 ) >> 16)
++#define GET_SIGNAL_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x000000ff ) >> 0)
++#define GET_B_SERVICE_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x0000ff00 ) >> 8)
++#define GET_CRC_CORRECT (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x00010000 ) >> 16)
++#define GET_DEBUG_SEL (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x0000000f ) >> 0)
++#define GET_RG_PACKET_STAT_EN_11B (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00100000 ) >> 20)
++#define GET_RG_BIT_REVERSE (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00200000 ) >> 21)
++#define GET_RX_PHY_11B_SOFT_RST_N (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000001 ) >> 0)
++#define GET_RG_CE_BYPASS_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x000000f0 ) >> 4)
++#define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000f00 ) >> 8)
++#define GET_RG_BB_11GN_RISE_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_BB_11GN_FALL_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_HTCARR52_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x000003ff ) >> 0)
++#define GET_RG_HTCARR56_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x003ff000 ) >> 12)
++#define GET_RG_PACKET_STAT_EN (((REG32(ADR_TX_11GN_PLCP)) & 0x00800000 ) >> 23)
++#define GET_RG_SMB_DEF (((REG32(ADR_TX_11GN_PLCP)) & 0x7f000000 ) >> 24)
++#define GET_RG_CONTINUOUS_DATA_11GN (((REG32(ADR_TX_11GN_PLCP)) & 0x80000000 ) >> 31)
++#define GET_RO_TX_CNT_R (((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
++#define GET_RO_PACKET_ERR_CNT (((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RG_POS_DES_11GN_L_EXT (((REG32(ADR_RX_11GN_DES_DLY)) & 0x0000000f ) >> 0)
++#define GET_RG_PRE_DES_11GN_DLY (((REG32(ADR_RX_11GN_DES_DLY)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_LPF_KI_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_KP_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_CNT_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TR_LPF_KI_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x000f0000 ) >> 16)
++#define GET_RG_TR_LPF_KP_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x00f00000 ) >> 20)
++#define GET_RG_TR_CNT_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0xff000000 ) >> 24)
++#define GET_RG_TR_LPF_KI_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_KP_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_CNT_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TR_LPF_KI_G (((REG32(ADR_RX_11GN_TR_2)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_KP_G (((REG32(ADR_RX_11GN_TR_2)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_LPF_RATE_G (((REG32(ADR_RX_11GN_TR_2)) & 0x3fffff00 ) >> 8)
++#define GET_RG_CR_LPF_KI_G (((REG32(ADR_RX_11GN_CCA_0)) & 0x00000007 ) >> 0)
++#define GET_RG_SYM_BOUND_CNT (((REG32(ADR_RX_11GN_CCA_0)) & 0x00007f00 ) >> 8)
++#define GET_RG_XSCOR32_RATIO (((REG32(ADR_RX_11GN_CCA_0)) & 0x007f0000 ) >> 16)
++#define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_RX_11GN_CCA_0)) & 0x7f000000 ) >> 24)
++#define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_1)) & 0x00007f00 ) >> 8)
++#define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_1)) & 0x007f0000 ) >> 16)
++#define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_RX_11GN_CCA_1)) & 0x7f000000 ) >> 24)
++#define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_2)) & 0x007f0000 ) >> 16)
++#define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_2)) & 0x7f000000 ) >> 24)
++#define GET_RG_RX_FFT_SCALE (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x000003ff ) >> 0)
++#define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x00010000 ) >> 16)
++#define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x0f000000 ) >> 24)
++#define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x000000ff ) >> 0)
++#define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ff0000 ) >> 16)
++#define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x000000ff ) >> 0)
++#define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x0000ff00 ) >> 8)
++#define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ff0000 ) >> 16)
++#define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x000000ff ) >> 0)
++#define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x0000ff00 ) >> 8)
++#define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ff0000 ) >> 16)
++#define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0xff000000 ) >> 24)
++#define GET_RG_SNR_TH_64QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x0000007f ) >> 0)
++#define GET_RG_SNR_TH_16QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x00007f00 ) >> 8)
++#define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x0000007f ) >> 0)
++#define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00007f00 ) >> 8)
++#define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00030000 ) >> 16)
++#define GET_RG_PWRON_DLY_TH_11GN (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x000000ff ) >> 0)
++#define GET_RG_SB_START_CNT (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x00007f00 ) >> 8)
++#define GET_RG_POW16_CNT_TH (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x000000f0 ) >> 4)
++#define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x00000700 ) >> 8)
++#define GET_RG_POW16_TH_L (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x7f000000 ) >> 24)
++#define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00000007 ) >> 0)
++#define GET_RG_XSCOR16_RATIO (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00007f00 ) >> 8)
++#define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00070000 ) >> 16)
++#define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x7f000000 ) >> 24)
++#define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x0000007f ) >> 0)
++#define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x00070000 ) >> 16)
++#define GET_RG_VITERBI_TB_BITS (((REG32(ADR_RX_11GN_VTB_TB)) & 0xff000000 ) >> 24)
++#define GET_RG_CR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x000000ff ) >> 0)
++#define GET_RG_TR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x00ff0000 ) >> 16)
++#define GET_RG_BYPASS_CPE_MA (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000010 ) >> 4)
++#define GET_RG_PILOT_BNDRY_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000700 ) >> 8)
++#define GET_RG_EQ_SHORT_GI_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00007000 ) >> 12)
++#define GET_RG_FFT_WDW_SHORT_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00070000 ) >> 16)
++#define GET_RG_CHSMTH_COEF (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00030000 ) >> 16)
++#define GET_RG_CHSMTH_EN (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00040000 ) >> 18)
++#define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x07000000 ) >> 24)
++#define GET_RG_CH_UPDATE (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x80000000 ) >> 31)
++#define GET_RG_FMT_DET_MM_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x000000ff ) >> 0)
++#define GET_RG_FMT_DET_GF_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x02000000 ) >> 25)
++#define GET_RG_FMT_DET_LENGTH_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff ) >> 0)
++#define GET_RG_L_LENGTH_MAX (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000 ) >> 16)
++#define GET_RG_TX_TIME_EXT (((REG32(ADR_RX_11GN_TX_TIME)) & 0x000000ff ) >> 0)
++#define GET_RG_MAC_DES_SPACE (((REG32(ADR_RX_11GN_TX_TIME)) & 0x00f00000 ) >> 20)
++#define GET_RG_TR_LPF_STBC_GF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_STBC_GF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_LPF_STBC_MF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x00000f00 ) >> 8)
++#define GET_RG_TR_LPF_STBC_MF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000f000 ) >> 12)
++#define GET_RG_MODE_REG_IN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x0001ffff ) >> 0)
++#define GET_RG_PARALLEL_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x00100000 ) >> 20)
++#define GET_RG_MBRUN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x01000000 ) >> 24)
++#define GET_RG_SHIFT_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x10000000 ) >> 28)
++#define GET_RG_MODE_REG_SI_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x20000000 ) >> 29)
++#define GET_RG_SIMULATION_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x40000000 ) >> 30)
++#define GET_RG_DBIST_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x80000000 ) >> 31)
++#define GET_RG_MODE_REG_IN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x0000ffff ) >> 0)
++#define GET_RG_PARALLEL_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x00100000 ) >> 20)
++#define GET_RG_MBRUN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x01000000 ) >> 24)
++#define GET_RG_SHIFT_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x10000000 ) >> 28)
++#define GET_RG_MODE_REG_SI_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x20000000 ) >> 29)
++#define GET_RG_SIMULATION_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x40000000 ) >> 30)
++#define GET_RG_DBIST_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x80000000 ) >> 31)
++#define GET_RO_MODE_REG_OUT_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x0001ffff ) >> 0)
++#define GET_RO_MODE_REG_SO_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x01000000 ) >> 24)
++#define GET_RO_MONITOR_BUS_80 (((REG32(ADR_RX_11GN_BIST_3)) & 0x003fffff ) >> 0)
++#define GET_RO_MODE_REG_OUT_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x0000ffff ) >> 0)
++#define GET_RO_MODE_REG_SO_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x01000000 ) >> 24)
++#define GET_RO_MONITOR_BUS_64 (((REG32(ADR_RX_11GN_BIST_5)) & 0x0007ffff ) >> 0)
++#define GET_RO_SPECTRUM_DATA (((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0xffffffff ) >> 0)
++#define GET_GN_SNR (((REG32(ADR_RX_11GN_READ_0)) & 0x0000007f ) >> 0)
++#define GET_GN_NOISE_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x00007f00 ) >> 8)
++#define GET_GN_RCPI (((REG32(ADR_RX_11GN_READ_0)) & 0x007f0000 ) >> 16)
++#define GET_GN_SIGNAL_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x7f000000 ) >> 24)
++#define GET_RO_FREQ_OS_LTS (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x00007fff ) >> 0)
++#define GET_CSTATE (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x000f0000 ) >> 16)
++#define GET_SIGNAL_FIELD0 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0x00ffffff ) >> 0)
++#define GET_SIGNAL_FIELD1 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0x00ffffff ) >> 0)
++#define GET_GN_PACKET_ERR_CNT (((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_GN_PACKET_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
++#define GET_GN_CCA_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
++#define GET_GN_LENGTH_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff ) >> 0)
++#define GET_GN_SERVICE_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000 ) >> 16)
++#define GET_RO_HT_MCS_40M (((REG32(ADR_RX_11GN_RATE)) & 0x0000007f ) >> 0)
++#define GET_RO_L_RATE_40M (((REG32(ADR_RX_11GN_RATE)) & 0x00003f00 ) >> 8)
++#define GET_RG_DAGC_CNT_TH (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00000003 ) >> 0)
++#define GET_RG_PACKET_STAT_EN_11GN (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00100000 ) >> 20)
++#define GET_RX_PHY_11GN_SOFT_RST_N (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000001 ) >> 0)
++#define GET_RG_RIFS_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000002 ) >> 1)
++#define GET_RG_STBC_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000004 ) >> 2)
++#define GET_RG_COR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000008 ) >> 3)
++#define GET_RG_INI_PHASE (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000030 ) >> 4)
++#define GET_RG_HT_LTF_SEL_EQ (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000040 ) >> 6)
++#define GET_RG_HT_LTF_SEL_PILOT (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000080 ) >> 7)
++#define GET_RG_CCA_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000200 ) >> 9)
++#define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000400 ) >> 10)
++#define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000800 ) >> 11)
++#define GET_RG_DEBUG_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x0000f000 ) >> 12)
++#define GET_RG_POST_CLK_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00010000 ) >> 16)
++#define GET_IQCAL_RF_TX_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000001 ) >> 0)
++#define GET_IQCAL_RF_TX_PA_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000002 ) >> 1)
++#define GET_IQCAL_RF_TX_DAC_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000004 ) >> 2)
++#define GET_IQCAL_RF_RX_AGC (((REG32(ADR_RF_CONTROL_0)) & 0x00000008 ) >> 3)
++#define GET_IQCAL_RF_PGAG (((REG32(ADR_RF_CONTROL_0)) & 0x00000f00 ) >> 8)
++#define GET_IQCAL_RF_RFG (((REG32(ADR_RF_CONTROL_0)) & 0x00003000 ) >> 12)
++#define GET_RG_TONEGEN_FREQ (((REG32(ADR_RF_CONTROL_0)) & 0x007f0000 ) >> 16)
++#define GET_RG_TONEGEN_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00800000 ) >> 23)
++#define GET_RG_TONEGEN_INIT_PH (((REG32(ADR_RF_CONTROL_0)) & 0x7f000000 ) >> 24)
++#define GET_RG_TONEGEN2_FREQ (((REG32(ADR_RF_CONTROL_1)) & 0x0000007f ) >> 0)
++#define GET_RG_TONEGEN2_EN (((REG32(ADR_RF_CONTROL_1)) & 0x00000080 ) >> 7)
++#define GET_RG_TONEGEN2_SCALE (((REG32(ADR_RF_CONTROL_1)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x000003ff ) >> 0)
++#define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x03ff0000 ) >> 16)
++#define GET_RG_TX_I_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x000000ff ) >> 0)
++#define GET_RG_TX_Q_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TX_IQ_SWP (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00010000 ) >> 16)
++#define GET_RG_TX_SGN_OUT (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00020000 ) >> 17)
++#define GET_RG_TXIQ_EMU_IDX (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x003c0000 ) >> 18)
++#define GET_RG_TX_IQ_SRC (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x03000000 ) >> 24)
++#define GET_RG_TX_I_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x000003ff ) >> 0)
++#define GET_RG_TX_Q_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x03ff0000 ) >> 16)
++#define GET_RG_TX_IQ_THETA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
++#define GET_RG_TX_IQ_ALPHA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
++#define GET_RG_TXIQ_NOSHRINK (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
++#define GET_RG_TX_I_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TX_Q_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff000000 ) >> 24)
++#define GET_RG_RX_IQ_THETA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
++#define GET_RG_RX_IQ_ALPHA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
++#define GET_RG_RXIQ_NOSHRINK (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
++#define GET_RG_MA_DPTH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x0000000f ) >> 0)
++#define GET_RG_INTG_PH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x000003f0 ) >> 4)
++#define GET_RG_INTG_PRD (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00001c00 ) >> 10)
++#define GET_RG_INTG_MU (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00006000 ) >> 13)
++#define GET_RG_IQCAL_SPRM_SELQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00010000 ) >> 16)
++#define GET_RG_IQCAL_SPRM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00020000 ) >> 17)
++#define GET_RG_IQCAL_SPRM_FREQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IQCAL_IQCOL_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x01000000 ) >> 24)
++#define GET_RG_IQCAL_ALPHA_ESTM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x02000000 ) >> 25)
++#define GET_RG_IQCAL_DC_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x04000000 ) >> 26)
++#define GET_RG_PHEST_STBY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x08000000 ) >> 27)
++#define GET_RG_PHEST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x10000000 ) >> 28)
++#define GET_RG_GP_DIV_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x20000000 ) >> 29)
++#define GET_RG_DPD_GAIN_EST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x40000000 ) >> 30)
++#define GET_RG_IQCAL_MULT_OP0 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x000003ff ) >> 0)
++#define GET_RG_IQCAL_MULT_OP1 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x03ff0000 ) >> 16)
++#define GET_RO_IQCAL_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x000fffff ) >> 0)
++#define GET_RO_IQCAL_SPRM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00100000 ) >> 20)
++#define GET_RO_IQCAL_IQCOL_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00200000 ) >> 21)
++#define GET_RO_IQCAL_ALPHA_ESTM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00400000 ) >> 22)
++#define GET_RO_IQCAL_DC_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00800000 ) >> 23)
++#define GET_RO_IQCAL_MULT_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x01000000 ) >> 24)
++#define GET_RO_FFT_ENRG_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x02000000 ) >> 25)
++#define GET_RO_PHEST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x04000000 ) >> 26)
++#define GET_RO_GP_DIV_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x08000000 ) >> 27)
++#define GET_RO_GAIN_EST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x10000000 ) >> 28)
++#define GET_RO_AMP_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0x000001ff ) >> 0)
++#define GET_RG_RX_I_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x000000ff ) >> 0)
++#define GET_RG_RX_Q_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_RX_I_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ff0000 ) >> 16)
++#define GET_RG_RX_Q_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff000000 ) >> 24)
++#define GET_RG_RX_IQ_SWP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000001 ) >> 0)
++#define GET_RG_RX_SGN_IN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000002 ) >> 1)
++#define GET_RG_RX_IQ_SRC (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x0000000c ) >> 2)
++#define GET_RG_ACI_GAIN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000ff0 ) >> 4)
++#define GET_RG_FFT_EN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00001000 ) >> 12)
++#define GET_RG_FFT_MOD (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00002000 ) >> 13)
++#define GET_RG_FFT_SCALE (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00ffc000 ) >> 14)
++#define GET_RG_FFT_ENRG_FREQ (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x3f000000 ) >> 24)
++#define GET_RG_FPGA_80M_PH_UP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x40000000 ) >> 30)
++#define GET_RG_FPGA_80M_PH_STP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x80000000 ) >> 31)
++#define GET_RG_ADC2LA_SEL (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000001 ) >> 0)
++#define GET_RG_ADC2LA_CLKPH (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000002 ) >> 1)
++#define GET_RG_RXIQ_EMU_IDX (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x0000000f ) >> 0)
++#define GET_RG_IQCAL_BP_ACI (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x00000010 ) >> 4)
++#define GET_RG_DPD_AM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000001 ) >> 0)
++#define GET_RG_DPD_PM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000002 ) >> 1)
++#define GET_RG_DPD_PM_AMSEL (((REG32(ADR_DPD_CONTROL)) & 0x00000004 ) >> 2)
++#define GET_RG_DPD_020_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_040_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_060_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_080_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_0A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_0C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_0D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_0E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_0F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_100_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_110_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_120_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_130_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_140_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_150_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_160_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_170_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_180_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_190_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_1A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_1B0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_1C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_1D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_1E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_1F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_200_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_020_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_040_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_060_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_080_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_0A0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_0C0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_0D0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_0E0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_0F0_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_100_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_110_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_120_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_130_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_140_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_150_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_160_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_170_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_180_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_190_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_1A0_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_1B0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_1C0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_1D0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_1E0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_1F0_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_200_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_GAIN_EST_Y0 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x000001ff ) >> 0)
++#define GET_RG_DPD_GAIN_EST_Y1 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x01ff0000 ) >> 16)
++#define GET_RG_DPD_LOOP_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_GAIN_EST_X0 (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x000001ff ) >> 0)
++#define GET_RO_DPD_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x03ff0000 ) >> 16)
++#define GET_TX_SCALE_11B (((REG32(ADR_TX_GAIN_FACTOR)) & 0x000000ff ) >> 0)
++#define GET_TX_SCALE_11B_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0x0000ff00 ) >> 8)
++#define GET_TX_SCALE_11G (((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ff0000 ) >> 16)
++#define GET_TX_SCALE_11G_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0xff000000 ) >> 24)
++#define GET_RG_EN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_TX_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_TX_PA_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_TX_DAC_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_RX_AGC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_RG_RFG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_RG_PGAG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
++#define GET_RG_MODE (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
++#define GET_RG_EN_TX_TRSW (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_EN_SX (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
++#define GET_RG_EN_RX_LNA (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_RG_EN_RX_MIXER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
++#define GET_RG_EN_RX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
++#define GET_RG_EN_RX_LOBUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
++#define GET_RG_EN_RX_TZ (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_RG_EN_RX_FILTER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_RG_EN_RX_HPF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_RG_EN_RX_RSSI (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
++#define GET_RG_EN_ADC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
++#define GET_RG_EN_TX_MOD (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
++#define GET_RG_EN_TX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
++#define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
++#define GET_RG_EN_TX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
++#define GET_RG_EN_RX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
++#define GET_RG_SEL_DPLL_CLK (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
++#define GET_RG_EN_CLK_960MBY13_UART (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x80000000 ) >> 31)
++#define GET_RG_EN_TX_DPD (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_EN_TX_TSSI (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_EN_RX_IQCAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_RG_EN_LDO_RX_FE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
++#define GET_RG_EN_LDO_ABB (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
++#define GET_RG_EN_LDO_AFE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_RG_EN_SX_CHPLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_RG_EN_SX_LOBFLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_RG_EN_IREF_RX (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
++#define GET_RG_EN_SX_LCK_BIN (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_RTC_CAL_MODE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_RG_EN_IQPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
++#define GET_RG_EN_TESTPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
++#define GET_RG_EN_TRXBF_BYPASS (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
++#define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_LDO_REGISTER)) & 0x00000007 ) >> 0)
++#define GET_RG_LDO_LEVEL_ABB (((REG32(ADR_LDO_REGISTER)) & 0x00000038 ) >> 3)
++#define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
++#define GET_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
++#define GET_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00007000 ) >> 12)
++#define GET_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_RG_DP_LDO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
++#define GET_RG_TX_LDO_TX_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x07000000 ) >> 24)
++#define GET_RG_EN_RX_PADSW (((REG32(ADR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
++#define GET_RG_EN_RX_TESTNODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
++#define GET_RG_RX_ABBCFIX (((REG32(ADR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
++#define GET_RG_RX_ABBCTUNE (((REG32(ADR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
++#define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
++#define GET_RG_RX_ABB_N_MODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
++#define GET_RG_RX_EN_LOOPA (((REG32(ADR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
++#define GET_RG_RX_FILTERI1ST (((REG32(ADR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
++#define GET_RG_RX_FILTERI2ND (((REG32(ADR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_FILTERI3RD (((REG32(ADR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
++#define GET_RG_RX_FILTERI_COURSE (((REG32(ADR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
++#define GET_RG_RX_FILTERVCM (((REG32(ADR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
++#define GET_RG_RX_HPF3M (((REG32(ADR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
++#define GET_RG_RX_HPF300K (((REG32(ADR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
++#define GET_RG_RX_HPFI (((REG32(ADR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
++#define GET_RG_RX_HPF_FINALCORNER (((REG32(ADR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
++#define GET_RG_RX_HPF_SETTLE1_C (((REG32(ADR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
++#define GET_RG_RX_HPF_SETTLE1_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_HPF_SETTLE2_C (((REG32(ADR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
++#define GET_RG_RX_HPF_SETTLE2_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
++#define GET_RG_RX_HPF_VCMCON2 (((REG32(ADR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
++#define GET_RG_RX_HPF_VCMCON (((REG32(ADR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
++#define GET_RG_RX_OUTVCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
++#define GET_RG_RX_TZI (((REG32(ADR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
++#define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
++#define GET_RG_RX_TZ_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
++#define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
++#define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
++#define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
++#define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
++#define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
++#define GET_RG_TXPGA_CAPSW (((REG32(ADR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_RG_TXPGA_MAIN (((REG32(ADR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
++#define GET_RG_TXPGA_STEER (((REG32(ADR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
++#define GET_RG_TXMOD_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_RG_TXLPF_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_RG_PACELL_EN (((REG32(ADR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_RG_PABIAS_CTRL (((REG32(ADR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
++#define GET_RG_TX_DIV_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
++#define GET_RG_TX_LOBUF_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
++#define GET_RG_RX_SQDC (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
++#define GET_RG_RX_DIV2_CORE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
++#define GET_RG_RX_LOBUF (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
++#define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
++#define GET_RG_TX_DPD_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
++#define GET_RG_TX_TSSI_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
++#define GET_RG_TX_TSSI_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
++#define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
++#define GET_RG_TX_TSSI_TEST (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
++#define GET_RG_PACASCODE_CTRL (((REG32(ADR_RX_FE_REGISTER_1)) & 0x07000000 ) >> 24)
++#define GET_RG_RX_HG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_HG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_HG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_HG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
++#define GET_RG_RX_MG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_MG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_MG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_MG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
++#define GET_RG_RX_LG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_LG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_LG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_LG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
++#define GET_RG_RX_ULG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_ULG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_ULG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
++#define GET_RG_HPF1_FAST_SET_X (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_HPF1_FAST_SET_Y (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_HPF1_FAST_SET_Z (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_HPF_T1A (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_RG_HPF_T1B (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000060 ) >> 5)
++#define GET_RG_HPF_T1C (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000180 ) >> 7)
++#define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_RG_RX_LNA_SETTLE (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00001800 ) >> 11)
++#define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00002000 ) >> 13)
++#define GET_RG_TX_GAIN (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x003fc000 ) >> 14)
++#define GET_RG_TXGAIN_MANUAL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_RG_TX_GAIN_OFFSET (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x07800000 ) >> 23)
++#define GET_RG_ADC_CLKSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_ADC_DIBIAS (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_RG_ADC_DIVR (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_ADC_DVCMI (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_RG_ADC_SAMSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
++#define GET_RG_ADC_STNBY (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_RG_ADC_TESTMODE (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_RG_ADC_TSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
++#define GET_RG_ADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_RG_DICMP (((REG32(ADR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_RG_DIOP (((REG32(ADR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
++#define GET_RG_SARADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00c00000 ) >> 22)
++#define GET_RG_EN_SAR_TEST (((REG32(ADR_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
++#define GET_RG_SARADC_THERMAL (((REG32(ADR_RX_ADC_REGISTER)) & 0x04000000 ) >> 26)
++#define GET_RG_SARADC_TSSI (((REG32(ADR_RX_ADC_REGISTER)) & 0x08000000 ) >> 27)
++#define GET_RG_CLK_SAR_SEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x30000000 ) >> 28)
++#define GET_RG_EN_SARADC (((REG32(ADR_RX_ADC_REGISTER)) & 0x40000000 ) >> 30)
++#define GET_RG_DACI1ST (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_RG_TX_DACLPF_ICOURSE (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
++#define GET_RG_TX_DACLPF_IFINE (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_RG_TX_DACLPF_VCM (((REG32(ADR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_RG_TX_DAC_IBIAS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_RG_TX_DAC_OS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
++#define GET_RG_TX_DAC_RCAL (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_RG_TX_DAC_TSEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
++#define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_RG_TXLPF_BYPASS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_RG_TXLPF_BOOSTI (((REG32(ADR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_RG_TX_DAC_IOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x07800000 ) >> 23)
++#define GET_RG_TX_DAC_QOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x78000000 ) >> 27)
++#define GET_RG_EN_SX_R3 (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_EN_SX_CH (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_EN_SX_CHP (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_EN_SX_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_EN_SX_VCOBF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_RG_EN_SX_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
++#define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_RG_EN_SX_VT_MON (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_RG_EN_SX_VT_MON_DG (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
++#define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
++#define GET_RG_EN_SX_LPF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_EN_DPL_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
++#define GET_RG_DPL_MOD_ORDER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_RG_SX_RFCTRL_F (((REG32(ADR_SYN_REGISTER_1)) & 0x00ffffff ) >> 0)
++#define GET_RG_SX_SEL_CP (((REG32(ADR_SYN_REGISTER_1)) & 0x0f000000 ) >> 24)
++#define GET_RG_SX_SEL_CS (((REG32(ADR_SYN_REGISTER_1)) & 0xf0000000 ) >> 28)
++#define GET_RG_SX_RFCTRL_CH (((REG32(ADR_SYN_REGISTER_2)) & 0x000007ff ) >> 0)
++#define GET_RG_SX_SEL_C3 (((REG32(ADR_SYN_REGISTER_2)) & 0x00007800 ) >> 11)
++#define GET_RG_SX_SEL_RS (((REG32(ADR_SYN_REGISTER_2)) & 0x000f8000 ) >> 15)
++#define GET_RG_SX_SEL_R3 (((REG32(ADR_SYN_REGISTER_2)) & 0x01f00000 ) >> 20)
++#define GET_RG_SX_SEL_ICHP (((REG32(ADR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
++#define GET_RG_SX_SEL_PCHP (((REG32(ADR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
++#define GET_RG_SX_SEL_CHP_REGOP (((REG32(ADR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
++#define GET_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
++#define GET_RG_SX_CHP_IOST_POL (((REG32(ADR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
++#define GET_RG_SX_CHP_IOST (((REG32(ADR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
++#define GET_RG_SX_PFDSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
++#define GET_RG_SX_PFD_SET (((REG32(ADR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
++#define GET_RG_SX_PFD_SET1 (((REG32(ADR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
++#define GET_RG_SX_PFD_SET2 (((REG32(ADR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
++#define GET_RG_SX_VBNCAS_SEL (((REG32(ADR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
++#define GET_RG_SX_PFD_RST_H (((REG32(ADR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
++#define GET_RG_SX_PFD_TRUP (((REG32(ADR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
++#define GET_RG_SX_PFD_TRDN (((REG32(ADR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
++#define GET_RG_SX_PFD_TRSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
++#define GET_RG_SX_VCOBA_R (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
++#define GET_RG_SX_VCORSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
++#define GET_RG_SX_VCOCUSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
++#define GET_RG_SX_RXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
++#define GET_RG_SX_TXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
++#define GET_RG_SX_VCOBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
++#define GET_RG_SX_DIVBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
++#define GET_RG_SX_GNDR_SEL (((REG32(ADR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
++#define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
++#define GET_RG_SX_MOD_ORDER (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
++#define GET_RG_SX_RST_H_DIV (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
++#define GET_RG_SX_SDM_EDGE (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
++#define GET_RG_SX_XO_GM (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
++#define GET_RG_SX_REFBYTWO (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
++#define GET_RG_SX_LCKEN (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
++#define GET_RG_SX_PREVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
++#define GET_RG_SX_PSCONTERVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
++#define GET_RG_SX_PH (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00002000 ) >> 13)
++#define GET_RG_SX_PL (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00004000 ) >> 14)
++#define GET_RG_XOSC_CBANK_XO (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00078000 ) >> 15)
++#define GET_RG_XOSC_CBANK_XI (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00780000 ) >> 19)
++#define GET_RG_SX_VT_MON_MODE (((REG32(ADR_SYN_LCK_VT)) & 0x00000001 ) >> 0)
++#define GET_RG_SX_VT_TH_HI (((REG32(ADR_SYN_LCK_VT)) & 0x00000006 ) >> 1)
++#define GET_RG_SX_VT_TH_LO (((REG32(ADR_SYN_LCK_VT)) & 0x00000018 ) >> 3)
++#define GET_RG_SX_VT_SET (((REG32(ADR_SYN_LCK_VT)) & 0x00000020 ) >> 5)
++#define GET_RG_SX_VT_MON_TMR (((REG32(ADR_SYN_LCK_VT)) & 0x00007fc0 ) >> 6)
++#define GET_RG_EN_DP_VT_MON (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_DP_VT_TH_HI (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_RG_DP_VT_TH_LO (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_RG_DP_CK320BY2 (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_DP_OD_TEST (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_RG_DP_BBPLL_BP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_DP_BBPLL_ICP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_RG_DP_BBPLL_OD_TEST (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
++#define GET_RG_DP_BBPLL_PD (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
++#define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
++#define GET_RG_DP_RP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_RG_DP_RHP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x80000000 ) >> 31)
++#define GET_RG_DP_FODIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x0007f000 ) >> 12)
++#define GET_RG_DP_REFDIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x1fc00000 ) >> 22)
++#define GET_RG_IDACAI_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
++#define GET_RG_DP_BBPLL_BS (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
++#define GET_RG_IDACAI_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
++#define GET_RG_EN_RCAL (((REG32(ADR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_RCAL_SPD (((REG32(ADR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_RCAL_TMR (((REG32(ADR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
++#define GET_RG_RCAL_CODE_CWR (((REG32(ADR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_RG_RCAL_CODE_CWD (((REG32(ADR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
++#define GET_RG_SX_SUB_SEL_CWR (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00000001 ) >> 0)
++#define GET_RG_SX_SUB_SEL_CWD (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x000000fe ) >> 1)
++#define GET_RG_SX_LCK_BIN_OFFSET (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00078000 ) >> 15)
++#define GET_RG_SX_LCK_BIN_PRECISION (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00080000 ) >> 19)
++#define GET_RG_SX_LOCK_EN_N (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00100000 ) >> 20)
++#define GET_RG_SX_LOCK_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00200000 ) >> 21)
++#define GET_RG_SX_SUB_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00400000 ) >> 22)
++#define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x3f800000 ) >> 23)
++#define GET_RG_SX_MUX_SEL_VTH_BINL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x40000000 ) >> 30)
++#define GET_RG_TRX_DUMMMY (((REG32(ADR_TRX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
++#define GET_RG_SX_DUMMMY (((REG32(ADR_SX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
++#define GET_RCAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
++#define GET_LCK_BIN_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
++#define GET_VT_MON_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
++#define GET_DA_R_CODE_LUT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
++#define GET_AD_SX_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
++#define GET_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
++#define GET_RTC_CAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00008000 ) >> 15)
++#define GET_RG_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x003f0000 ) >> 16)
++#define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00400000 ) >> 22)
++#define GET_AD_CIRCUIT_VERSION (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x07800000 ) >> 23)
++#define GET_DA_R_CAL_CODE (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
++#define GET_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
++#define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x000007ff ) >> 0)
++#define GET_RG_RSSIADC_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x00007800 ) >> 11)
++#define GET_RG_RX_ADC_I_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x007f8000 ) >> 15)
++#define GET_RG_RX_ADC_Q_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x7f800000 ) >> 23)
++#define GET_RG_DPL_RFCTRL_F (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0x00ffffff ) >> 0)
++#define GET_RG_SX_TARGET_CNT (((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0x00001fff ) >> 0)
++#define GET_RG_RTC_OFFSET (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000000ff ) >> 0)
++#define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000fff00 ) >> 8)
++#define GET_RG_RF_D_REG (((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0x0000ffff ) >> 0)
++#define GET_DIRECT_MODE (((REG32(ADR_MMU_CTRL)) & 0x00000001 ) >> 0)
++#define GET_TAG_INTERLEAVE_MD (((REG32(ADR_MMU_CTRL)) & 0x00000002 ) >> 1)
++#define GET_DIS_DEMAND (((REG32(ADR_MMU_CTRL)) & 0x00000004 ) >> 2)
++#define GET_SAME_ID_ALLOC_MD (((REG32(ADR_MMU_CTRL)) & 0x00000008 ) >> 3)
++#define GET_HS_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000010 ) >> 4)
++#define GET_SRAM_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000020 ) >> 5)
++#define GET_NOHIT_RPASS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000040 ) >> 6)
++#define GET_DMN_FLAG_CLR (((REG32(ADR_MMU_CTRL)) & 0x00000080 ) >> 7)
++#define GET_ERR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000100 ) >> 8)
++#define GET_ALR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000200 ) >> 9)
++#define GET_MCH_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000400 ) >> 10)
++#define GET_TAG_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000800 ) >> 11)
++#define GET_ABT_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00001000 ) >> 12)
++#define GET_MMU_VER (((REG32(ADR_MMU_CTRL)) & 0x0000e000 ) >> 13)
++#define GET_MMU_SHARE_MCU (((REG32(ADR_MMU_CTRL)) & 0x00ff0000 ) >> 16)
++#define GET_HS_WR (((REG32(ADR_HS_CTRL)) & 0x00000001 ) >> 0)
++#define GET_HS_FLAG (((REG32(ADR_HS_CTRL)) & 0x00000010 ) >> 4)
++#define GET_HS_ID (((REG32(ADR_HS_CTRL)) & 0x00007f00 ) >> 8)
++#define GET_HS_CHANNEL (((REG32(ADR_HS_CTRL)) & 0x000f0000 ) >> 16)
++#define GET_HS_PAGE (((REG32(ADR_HS_CTRL)) & 0x00f00000 ) >> 20)
++#define GET_HS_DATA (((REG32(ADR_HS_CTRL)) & 0xff000000 ) >> 24)
++#define GET_CPU_POR0 (((REG32(ADR_CPU_POR0_7)) & 0x0000000f ) >> 0)
++#define GET_CPU_POR1 (((REG32(ADR_CPU_POR0_7)) & 0x000000f0 ) >> 4)
++#define GET_CPU_POR2 (((REG32(ADR_CPU_POR0_7)) & 0x00000f00 ) >> 8)
++#define GET_CPU_POR3 (((REG32(ADR_CPU_POR0_7)) & 0x0000f000 ) >> 12)
++#define GET_CPU_POR4 (((REG32(ADR_CPU_POR0_7)) & 0x000f0000 ) >> 16)
++#define GET_CPU_POR5 (((REG32(ADR_CPU_POR0_7)) & 0x00f00000 ) >> 20)
++#define GET_CPU_POR6 (((REG32(ADR_CPU_POR0_7)) & 0x0f000000 ) >> 24)
++#define GET_CPU_POR7 (((REG32(ADR_CPU_POR0_7)) & 0xf0000000 ) >> 28)
++#define GET_CPU_POR8 (((REG32(ADR_CPU_POR8_F)) & 0x0000000f ) >> 0)
++#define GET_CPU_POR9 (((REG32(ADR_CPU_POR8_F)) & 0x000000f0 ) >> 4)
++#define GET_CPU_PORA (((REG32(ADR_CPU_POR8_F)) & 0x00000f00 ) >> 8)
++#define GET_CPU_PORB (((REG32(ADR_CPU_POR8_F)) & 0x0000f000 ) >> 12)
++#define GET_CPU_PORC (((REG32(ADR_CPU_POR8_F)) & 0x000f0000 ) >> 16)
++#define GET_CPU_PORD (((REG32(ADR_CPU_POR8_F)) & 0x00f00000 ) >> 20)
++#define GET_CPU_PORE (((REG32(ADR_CPU_POR8_F)) & 0x0f000000 ) >> 24)
++#define GET_CPU_PORF (((REG32(ADR_CPU_POR8_F)) & 0xf0000000 ) >> 28)
++#define GET_ACC_WR_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x0000003f ) >> 0)
++#define GET_ACC_RD_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x00003f00 ) >> 8)
++#define GET_REQ_NACK_CLR (((REG32(ADR_REG_LEN_CTRL)) & 0x00008000 ) >> 15)
++#define GET_NACK_FLAG_BUS (((REG32(ADR_REG_LEN_CTRL)) & 0xffff0000 ) >> 16)
++#define GET_DMN_R_PASS (((REG32(ADR_DMN_READ_BYPASS)) & 0x0000ffff ) >> 0)
++#define GET_PARA_ALC_RLS (((REG32(ADR_DMN_READ_BYPASS)) & 0x00010000 ) >> 16)
++#define GET_REQ_PORNS_CHGEN (((REG32(ADR_DMN_READ_BYPASS)) & 0x01000000 ) >> 24)
++#define GET_ALC_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x0000007f ) >> 0)
++#define GET_ALC_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x00008000 ) >> 15)
++#define GET_RLS_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x007f0000 ) >> 16)
++#define GET_RLS_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x80000000 ) >> 31)
++#define GET_DEBUG_CTL (((REG32(ADR_DEBUG_CTL)) & 0x000000ff ) >> 0)
++#define GET_DEBUG_H16 (((REG32(ADR_DEBUG_CTL)) & 0x00000100 ) >> 8)
++#define GET_DEBUG_OUT (((REG32(ADR_DEBUG_OUT)) & 0xffffffff ) >> 0)
++#define GET_ALC_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000001 ) >> 0)
++#define GET_RLS_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000002 ) >> 1)
++#define GET_AL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00000700 ) >> 8)
++#define GET_RL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00007000 ) >> 12)
++#define GET_ALC_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x007f0000 ) >> 16)
++#define GET_RLS_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x7f000000 ) >> 24)
++#define GET_DMN_NOHIT_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0)
++#define GET_DMN_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1)
++#define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000008 ) >> 3)
++#define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4)
++#define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8)
++#define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0xffff0000 ) >> 16)
++#define GET_TX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x000000ff ) >> 0)
++#define GET_RX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x0000ff00 ) >> 8)
++#define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x01ff0000 ) >> 16)
++#define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x80000000 ) >> 31)
++#define GET_DMN_NOHIT_MCU (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000001 ) >> 0)
++#define GET_DMN_MCU_FLAG (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000002 ) >> 1)
++#define GET_DMN_MCU_WR (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000008 ) >> 3)
++#define GET_DMN_MCU_PORT (((REG32(ADR_DMN_MCU_STATUS)) & 0x000000f0 ) >> 4)
++#define GET_DMN_MCU_ID (((REG32(ADR_DMN_MCU_STATUS)) & 0x00007f00 ) >> 8)
++#define GET_DMN_MCU_ADDR (((REG32(ADR_DMN_MCU_STATUS)) & 0xffff0000 ) >> 16)
++#define GET_MB_IDTBL_31_0 (((REG32(ADR_MB_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_MB_IDTBL_63_32 (((REG32(ADR_MB_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_MB_IDTBL_95_64 (((REG32(ADR_MB_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_MB_IDTBL_127_96 (((REG32(ADR_MB_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_31_0 (((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_63_32 (((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_95_64 (((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_127_96 (((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_31_0 (((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_63_32 (((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_95_64 (((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_127_96 (((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_31_0 (((REG32(ADR_MB_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_63_32 (((REG32(ADR_MB_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_95_64 (((REG32(ADR_MB_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_127_96 (((REG32(ADR_MB_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_31_0 (((REG32(ADR_PKT_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_63_32 (((REG32(ADR_PKT_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_95_64 (((REG32(ADR_PKT_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_127_96 (((REG32(ADR_PKT_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_ALC_NOCHG_ID (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x0000007f ) >> 0)
++#define GET_ALC_NOCHG_INT (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00008000 ) >> 15)
++#define GET_NEQ_PKT_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00010000 ) >> 16)
++#define GET_NEQ_MB_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x01000000 ) >> 24)
++#define GET_SRAM_TAG_0 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_1 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_2 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_3 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_4 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_5 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_6 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_7 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_8 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_9 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_10 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_11 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_12 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_13 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_14 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_15 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000 ) >> 16)
++#define SET_MCU_ENABLE(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 0) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffe))
++#define SET_MAC_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 1) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffd))
++#define SET_MCU_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 2) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffb))
++#define SET_SDIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 3) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffff7))
++#define SET_SPI_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 4) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffef))
++#define SET_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 5) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffdf))
++#define SET_DMA_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 6) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffbf))
++#define SET_WDT_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 7) | ((REG32(ADR_BRG_SW_RST)) & 0xffffff7f))
++#define SET_I2C_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 8) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffeff))
++#define SET_INT_CTL_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 9) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffdff))
++#define SET_BTCX_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 10) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffbff))
++#define SET_GPIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 11) | ((REG32(ADR_BRG_SW_RST)) & 0xfffff7ff))
++#define SET_US0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 12) | ((REG32(ADR_BRG_SW_RST)) & 0xffffefff))
++#define SET_US1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 13) | ((REG32(ADR_BRG_SW_RST)) & 0xffffdfff))
++#define SET_US2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 14) | ((REG32(ADR_BRG_SW_RST)) & 0xffffbfff))
++#define SET_US3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 15) | ((REG32(ADR_BRG_SW_RST)) & 0xffff7fff))
++#define SET_MS0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 16) | ((REG32(ADR_BRG_SW_RST)) & 0xfffeffff))
++#define SET_MS1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 17) | ((REG32(ADR_BRG_SW_RST)) & 0xfffdffff))
++#define SET_MS2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 18) | ((REG32(ADR_BRG_SW_RST)) & 0xfffbffff))
++#define SET_MS3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 19) | ((REG32(ADR_BRG_SW_RST)) & 0xfff7ffff))
++#define SET_RF_BB_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 20) | ((REG32(ADR_BRG_SW_RST)) & 0xffefffff))
++#define SET_SYS_ALL_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 21) | ((REG32(ADR_BRG_SW_RST)) & 0xffdfffff))
++#define SET_DAT_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 22) | ((REG32(ADR_BRG_SW_RST)) & 0xffbfffff))
++#define SET_I2C_MST_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 23) | ((REG32(ADR_BRG_SW_RST)) & 0xff7fffff))
++#define SET_RG_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT)) & 0xfffffffe))
++#define SET_TRAP_IMG_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 16) | ((REG32(ADR_BOOT)) & 0xfffeffff))
++#define SET_TRAP_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 17) | ((REG32(ADR_BOOT)) & 0xfffdffff))
++#define SET_TRAP_BOOT_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 18) | ((REG32(ADR_BOOT)) & 0xfffbffff))
++#define SET_CHIP_ID_31_0(_VAL_) (REG32(ADR_CHIP_ID_0)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_0)) & 0x00000000))
++#define SET_CHIP_ID_63_32(_VAL_) (REG32(ADR_CHIP_ID_1)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_1)) & 0x00000000))
++#define SET_CHIP_ID_95_64(_VAL_) (REG32(ADR_CHIP_ID_2)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_2)) & 0x00000000))
++#define SET_CHIP_ID_127_96(_VAL_) (REG32(ADR_CHIP_ID_3)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_3)) & 0x00000000))
++#define SET_CK_SEL_1_0(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 0) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffc))
++#define SET_CK_SEL_2(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 2) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffb))
++#define SET_SYS_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffe))
++#define SET_MAC_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MCU_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 2) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffb))
++#define SET_SDIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffff7))
++#define SET_SPI_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffef))
++#define SET_UART_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffdf))
++#define SET_DMA_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffbf))
++#define SET_WDT_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffff7f))
++#define SET_I2C_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 8) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffeff))
++#define SET_INT_CTL_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffdff))
++#define SET_BTCX_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_GPIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffff7ff))
++#define SET_US0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffefff))
++#define SET_US1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_US2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffbfff))
++#define SET_US3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffff7fff))
++#define SET_MS0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 16) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffeffff))
++#define SET_MS1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 17) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffdffff))
++#define SET_MS2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 18) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffbffff))
++#define SET_MS3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 19) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfff7ffff))
++#define SET_BIST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 20) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffefffff))
++#define SET_I2C_MST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 23) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xff7fffff))
++#define SET_BTCX_CSR_CLK_EN(_VAL_) (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_MCU_DBG_SEL(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_SEL)) & 0xffffffc0))
++#define SET_MCU_STOP_NOGRANT(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffeff))
++#define SET_MCU_STOP_ANYTIME(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffdff))
++#define SET_MCU_DBG_DATA(_VAL_) (REG32(ADR_MCU_DBG_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_DATA)) & 0x00000000))
++#define SET_AHB_SW_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffe))
++#define SET_AHB_ERR_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffd))
++#define SET_REG_AHB_DEBUG_MX(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffffcf))
++#define SET_REG_PKT_W_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffeff))
++#define SET_REG_PKT_R_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffdff))
++#define SET_IQ_SRAM_SEL_0(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffefff))
++#define SET_IQ_SRAM_SEL_1(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffdfff))
++#define SET_IQ_SRAM_SEL_2(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffbfff))
++#define SET_AHB_STATUS(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_AHB_BRG_STATUS)) & 0x0000ffff))
++#define SET_PARALLEL_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffffe))
++#define SET_MBRUN(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xffffffef))
++#define SET_SHIFT_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffeff))
++#define SET_MODE_REG_SI(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffdff))
++#define SET_SIMULATION_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffbff))
++#define SET_DBIST_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffff7ff))
++#define SET_MODE_REG_IN(_VAL_) (REG32(ADR_BIST_MODE_REG_IN)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN)) & 0xffe00000))
++#define SET_MODE_REG_OUT_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0xffe00000))
++#define SET_MODE_REG_SO_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0x7fffffff))
++#define SET_MONITOR_BUS_MCU_31_0(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0x00000000))
++#define SET_MONITOR_BUS_MCU_33_32(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0xfffffffc))
++#define SET_TB_ADR_SEL(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_TB_ADR_SEL)) & 0xffff0000))
++#define SET_TB_CS(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 31) | ((REG32(ADR_TB_ADR_SEL)) & 0x7fffffff))
++#define SET_TB_RDATA(_VAL_) (REG32(ADR_TB_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_TB_RDATA)) & 0x00000000))
++#define SET_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 0) | ((REG32(ADR_UART_W2B)) & 0xfffffffe))
++#define SET_DATA_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 4) | ((REG32(ADR_UART_W2B)) & 0xffffffef))
++#define SET_AHB_ILL_ADDR(_VAL_) (REG32(ADR_AHB_ILL_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILL_ADDR)) & 0x00000000))
++#define SET_AHB_FEN_ADDR(_VAL_) (REG32(ADR_AHB_FEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_FEN_ADDR)) & 0x00000000))
++#define SET_ILL_ADDR_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffe))
++#define SET_FENCE_HIT_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffd))
++#define SET_ILL_ADDR_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffef))
++#define SET_FENCE_HIT_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffdf))
++#define SET_PWM_INI_VALUE_P_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_A)) & 0xffffff00))
++#define SET_PWM_INI_VALUE_N_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_A)) & 0xffff00ff))
++#define SET_PWM_POST_SCALER_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_A)) & 0xfff0ffff))
++#define SET_PWM_ALWAYSON_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_A)) & 0xdfffffff))
++#define SET_PWM_INVERT_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_A)) & 0xbfffffff))
++#define SET_PWM_ENABLE_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_A)) & 0x7fffffff))
++#define SET_PWM_INI_VALUE_P_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_B)) & 0xffffff00))
++#define SET_PWM_INI_VALUE_N_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_B)) & 0xffff00ff))
++#define SET_PWM_POST_SCALER_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_B)) & 0xfff0ffff))
++#define SET_PWM_ALWAYSON_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_B)) & 0xdfffffff))
++#define SET_PWM_INVERT_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_B)) & 0xbfffffff))
++#define SET_PWM_ENABLE_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_B)) & 0x7fffffff))
++#define SET_HBUSREQ_LOCK(_VAL_) (REG32(ADR_HBUSREQ_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBUSREQ_LOCK)) & 0xffffe000))
++#define SET_HBURST_LOCK(_VAL_) (REG32(ADR_HBURST_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBURST_LOCK)) & 0xffffe000))
++#define SET_PRESCALER_USTIMER(_VAL_) (REG32(ADR_PRESCALER_USTIMER)) = (((_VAL_) << 0) | ((REG32(ADR_PRESCALER_USTIMER)) & 0xfffffe00))
++#define SET_MODE_REG_IN_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0xffff0000))
++#define SET_MODE_REG_OUT_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0xffff0000))
++#define SET_MODE_REG_SO_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x7fffffff))
++#define SET_MONITOR_BUS_MMU(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0xfff80000))
++#define SET_TEST_MODE0(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_TEST_MODE)) & 0xfffffffe))
++#define SET_TEST_MODE1(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_TEST_MODE)) & 0xfffffffd))
++#define SET_TEST_MODE2(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_TEST_MODE)) & 0xfffffffb))
++#define SET_TEST_MODE3(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_TEST_MODE)) & 0xfffffff7))
++#define SET_TEST_MODE4(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_TEST_MODE)) & 0xffffffef))
++#define SET_TEST_MODE_ALL(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_TEST_MODE)) & 0xffffffdf))
++#define SET_WDT_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffe))
++#define SET_SD_HOST_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffd))
++#define SET_ALLOW_SD_RESET(_VAL_) (REG32(ADR_SD_INIT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_SD_INIT_CFG)) & 0xfffffffe))
++#define SET_UART_NRTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffe))
++#define SET_UART_NCTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffd))
++#define SET_TU0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU0_TM_MODE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU0_TM_INT_MASK(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TU1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU1_TM_MODE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU1_TM_INT_MASK(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TU2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU2_TM_MODE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU2_TM_INT_MASK(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TU3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU3_TM_MODE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU3_TM_INT_MASK(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM0_TM_MODE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM0_TM_INT_MASK(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM1_TM_MODE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM1_TM_INT_MASK(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM2_TM_MODE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM2_TM_INT_MASK(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM3_TM_MODE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM3_TM_INT_MASK(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_MCU_WDT_TIME_CNT(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_WDOG_REG)) & 0xffff0000))
++#define SET_MCU_WDT_STATUS(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_MCU_WDOG_REG)) & 0xfffdffff))
++#define SET_MCU_WDOG_ENA(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_MCU_WDOG_REG)) & 0x7fffffff))
++#define SET_SYS_WDT_TIME_CNT(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_WDOG_REG)) & 0xffff0000))
++#define SET_SYS_WDT_STATUS(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYS_WDOG_REG)) & 0xfffdffff))
++#define SET_SYS_WDOG_ENA(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYS_WDOG_REG)) & 0x7fffffff))
++#define SET_XLNA_EN_O_OE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 0) | ((REG32(ADR_PAD6)) & 0xfffffffe))
++#define SET_XLNA_EN_O_PE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 1) | ((REG32(ADR_PAD6)) & 0xfffffffd))
++#define SET_PAD6_IE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 3) | ((REG32(ADR_PAD6)) & 0xfffffff7))
++#define SET_PAD6_SEL_I(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 4) | ((REG32(ADR_PAD6)) & 0xffffffcf))
++#define SET_PAD6_OD(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 8) | ((REG32(ADR_PAD6)) & 0xfffffeff))
++#define SET_PAD6_SEL_O(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 12) | ((REG32(ADR_PAD6)) & 0xffffefff))
++#define SET_XLNA_EN_O_C(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 28) | ((REG32(ADR_PAD6)) & 0xefffffff))
++#define SET_WIFI_TX_SW_O_OE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 0) | ((REG32(ADR_PAD7)) & 0xfffffffe))
++#define SET_WIFI_TX_SW_O_PE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 1) | ((REG32(ADR_PAD7)) & 0xfffffffd))
++#define SET_PAD7_IE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 3) | ((REG32(ADR_PAD7)) & 0xfffffff7))
++#define SET_PAD7_SEL_I(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 4) | ((REG32(ADR_PAD7)) & 0xffffffcf))
++#define SET_PAD7_OD(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 8) | ((REG32(ADR_PAD7)) & 0xfffffeff))
++#define SET_PAD7_SEL_O(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 12) | ((REG32(ADR_PAD7)) & 0xffffefff))
++#define SET_WIFI_TX_SW_O_C(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 28) | ((REG32(ADR_PAD7)) & 0xefffffff))
++#define SET_WIFI_RX_SW_O_OE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 0) | ((REG32(ADR_PAD8)) & 0xfffffffe))
++#define SET_WIFI_RX_SW_O_PE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 1) | ((REG32(ADR_PAD8)) & 0xfffffffd))
++#define SET_PAD8_IE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 3) | ((REG32(ADR_PAD8)) & 0xfffffff7))
++#define SET_PAD8_SEL_I(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 4) | ((REG32(ADR_PAD8)) & 0xffffffcf))
++#define SET_PAD8_OD(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 8) | ((REG32(ADR_PAD8)) & 0xfffffeff))
++#define SET_WIFI_RX_SW_O_C(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 28) | ((REG32(ADR_PAD8)) & 0xefffffff))
++#define SET_BT_SW_O_OE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 0) | ((REG32(ADR_PAD9)) & 0xfffffffe))
++#define SET_BT_SW_O_PE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 1) | ((REG32(ADR_PAD9)) & 0xfffffffd))
++#define SET_PAD9_IE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 3) | ((REG32(ADR_PAD9)) & 0xfffffff7))
++#define SET_PAD9_SEL_I(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 4) | ((REG32(ADR_PAD9)) & 0xffffffcf))
++#define SET_PAD9_OD(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 8) | ((REG32(ADR_PAD9)) & 0xfffffeff))
++#define SET_PAD9_SEL_O(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 12) | ((REG32(ADR_PAD9)) & 0xffffefff))
++#define SET_BT_SW_O_C(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 28) | ((REG32(ADR_PAD9)) & 0xefffffff))
++#define SET_XPA_EN_O_OE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 0) | ((REG32(ADR_PAD11)) & 0xfffffffe))
++#define SET_XPA_EN_O_PE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 1) | ((REG32(ADR_PAD11)) & 0xfffffffd))
++#define SET_PAD11_IE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 3) | ((REG32(ADR_PAD11)) & 0xfffffff7))
++#define SET_PAD11_SEL_I(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 4) | ((REG32(ADR_PAD11)) & 0xffffffcf))
++#define SET_PAD11_OD(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 8) | ((REG32(ADR_PAD11)) & 0xfffffeff))
++#define SET_PAD11_SEL_O(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 12) | ((REG32(ADR_PAD11)) & 0xffffefff))
++#define SET_XPA_EN_O_C(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 28) | ((REG32(ADR_PAD11)) & 0xefffffff))
++#define SET_PAD15_OE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 0) | ((REG32(ADR_PAD15)) & 0xfffffffe))
++#define SET_PAD15_PE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 1) | ((REG32(ADR_PAD15)) & 0xfffffffd))
++#define SET_PAD15_DS(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 2) | ((REG32(ADR_PAD15)) & 0xfffffffb))
++#define SET_PAD15_IE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 3) | ((REG32(ADR_PAD15)) & 0xfffffff7))
++#define SET_PAD15_SEL_I(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 4) | ((REG32(ADR_PAD15)) & 0xffffffcf))
++#define SET_PAD15_OD(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 8) | ((REG32(ADR_PAD15)) & 0xfffffeff))
++#define SET_PAD15_SEL_O(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 12) | ((REG32(ADR_PAD15)) & 0xffffefff))
++#define SET_TEST_1_ID(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 28) | ((REG32(ADR_PAD15)) & 0xefffffff))
++#define SET_PAD16_OE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 0) | ((REG32(ADR_PAD16)) & 0xfffffffe))
++#define SET_PAD16_PE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 1) | ((REG32(ADR_PAD16)) & 0xfffffffd))
++#define SET_PAD16_DS(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 2) | ((REG32(ADR_PAD16)) & 0xfffffffb))
++#define SET_PAD16_IE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 3) | ((REG32(ADR_PAD16)) & 0xfffffff7))
++#define SET_PAD16_SEL_I(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 4) | ((REG32(ADR_PAD16)) & 0xffffffcf))
++#define SET_PAD16_OD(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 8) | ((REG32(ADR_PAD16)) & 0xfffffeff))
++#define SET_PAD16_SEL_O(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 12) | ((REG32(ADR_PAD16)) & 0xffffefff))
++#define SET_TEST_2_ID(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 28) | ((REG32(ADR_PAD16)) & 0xefffffff))
++#define SET_PAD17_OE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 0) | ((REG32(ADR_PAD17)) & 0xfffffffe))
++#define SET_PAD17_PE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 1) | ((REG32(ADR_PAD17)) & 0xfffffffd))
++#define SET_PAD17_DS(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 2) | ((REG32(ADR_PAD17)) & 0xfffffffb))
++#define SET_PAD17_IE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 3) | ((REG32(ADR_PAD17)) & 0xfffffff7))
++#define SET_PAD17_SEL_I(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 4) | ((REG32(ADR_PAD17)) & 0xffffffcf))
++#define SET_PAD17_OD(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 8) | ((REG32(ADR_PAD17)) & 0xfffffeff))
++#define SET_PAD17_SEL_O(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 12) | ((REG32(ADR_PAD17)) & 0xffffefff))
++#define SET_TEST_3_ID(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 28) | ((REG32(ADR_PAD17)) & 0xefffffff))
++#define SET_PAD18_OE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 0) | ((REG32(ADR_PAD18)) & 0xfffffffe))
++#define SET_PAD18_PE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 1) | ((REG32(ADR_PAD18)) & 0xfffffffd))
++#define SET_PAD18_DS(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 2) | ((REG32(ADR_PAD18)) & 0xfffffffb))
++#define SET_PAD18_IE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 3) | ((REG32(ADR_PAD18)) & 0xfffffff7))
++#define SET_PAD18_SEL_I(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 4) | ((REG32(ADR_PAD18)) & 0xffffffcf))
++#define SET_PAD18_OD(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 8) | ((REG32(ADR_PAD18)) & 0xfffffeff))
++#define SET_PAD18_SEL_O(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 12) | ((REG32(ADR_PAD18)) & 0xffffcfff))
++#define SET_TEST_4_ID(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 28) | ((REG32(ADR_PAD18)) & 0xefffffff))
++#define SET_PAD19_OE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 0) | ((REG32(ADR_PAD19)) & 0xfffffffe))
++#define SET_PAD19_PE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 1) | ((REG32(ADR_PAD19)) & 0xfffffffd))
++#define SET_PAD19_DS(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 2) | ((REG32(ADR_PAD19)) & 0xfffffffb))
++#define SET_PAD19_IE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 3) | ((REG32(ADR_PAD19)) & 0xfffffff7))
++#define SET_PAD19_SEL_I(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 4) | ((REG32(ADR_PAD19)) & 0xffffffcf))
++#define SET_PAD19_OD(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 8) | ((REG32(ADR_PAD19)) & 0xfffffeff))
++#define SET_PAD19_SEL_O(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 12) | ((REG32(ADR_PAD19)) & 0xffff8fff))
++#define SET_SHORT_TO_20_ID(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 28) | ((REG32(ADR_PAD19)) & 0xefffffff))
++#define SET_PAD20_OE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 0) | ((REG32(ADR_PAD20)) & 0xfffffffe))
++#define SET_PAD20_PE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 1) | ((REG32(ADR_PAD20)) & 0xfffffffd))
++#define SET_PAD20_DS(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 2) | ((REG32(ADR_PAD20)) & 0xfffffffb))
++#define SET_PAD20_IE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 3) | ((REG32(ADR_PAD20)) & 0xfffffff7))
++#define SET_PAD20_SEL_I(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 4) | ((REG32(ADR_PAD20)) & 0xffffff0f))
++#define SET_PAD20_OD(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 8) | ((REG32(ADR_PAD20)) & 0xfffffeff))
++#define SET_PAD20_SEL_O(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 12) | ((REG32(ADR_PAD20)) & 0xffffcfff))
++#define SET_STRAP0(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 27) | ((REG32(ADR_PAD20)) & 0xf7ffffff))
++#define SET_GPIO_TEST_1_ID(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 28) | ((REG32(ADR_PAD20)) & 0xefffffff))
++#define SET_PAD21_OE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 0) | ((REG32(ADR_PAD21)) & 0xfffffffe))
++#define SET_PAD21_PE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 1) | ((REG32(ADR_PAD21)) & 0xfffffffd))
++#define SET_PAD21_DS(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 2) | ((REG32(ADR_PAD21)) & 0xfffffffb))
++#define SET_PAD21_IE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 3) | ((REG32(ADR_PAD21)) & 0xfffffff7))
++#define SET_PAD21_SEL_I(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 4) | ((REG32(ADR_PAD21)) & 0xffffff8f))
++#define SET_PAD21_OD(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 8) | ((REG32(ADR_PAD21)) & 0xfffffeff))
++#define SET_PAD21_SEL_O(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 12) | ((REG32(ADR_PAD21)) & 0xffffcfff))
++#define SET_STRAP3(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 27) | ((REG32(ADR_PAD21)) & 0xf7ffffff))
++#define SET_GPIO_TEST_2_ID(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 28) | ((REG32(ADR_PAD21)) & 0xefffffff))
++#define SET_PAD22_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 0) | ((REG32(ADR_PAD22)) & 0xfffffffe))
++#define SET_PAD22_PE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 1) | ((REG32(ADR_PAD22)) & 0xfffffffd))
++#define SET_PAD22_DS(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 2) | ((REG32(ADR_PAD22)) & 0xfffffffb))
++#define SET_PAD22_IE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 3) | ((REG32(ADR_PAD22)) & 0xfffffff7))
++#define SET_PAD22_SEL_I(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 4) | ((REG32(ADR_PAD22)) & 0xffffff8f))
++#define SET_PAD22_OD(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 8) | ((REG32(ADR_PAD22)) & 0xfffffeff))
++#define SET_PAD22_SEL_O(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 12) | ((REG32(ADR_PAD22)) & 0xffff8fff))
++#define SET_PAD22_SEL_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 20) | ((REG32(ADR_PAD22)) & 0xffefffff))
++#define SET_GPIO_TEST_3_ID(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 28) | ((REG32(ADR_PAD22)) & 0xefffffff))
++#define SET_PAD24_OE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 0) | ((REG32(ADR_PAD24)) & 0xfffffffe))
++#define SET_PAD24_PE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 1) | ((REG32(ADR_PAD24)) & 0xfffffffd))
++#define SET_PAD24_DS(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 2) | ((REG32(ADR_PAD24)) & 0xfffffffb))
++#define SET_PAD24_IE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 3) | ((REG32(ADR_PAD24)) & 0xfffffff7))
++#define SET_PAD24_SEL_I(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 4) | ((REG32(ADR_PAD24)) & 0xffffffcf))
++#define SET_PAD24_OD(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 8) | ((REG32(ADR_PAD24)) & 0xfffffeff))
++#define SET_PAD24_SEL_O(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 12) | ((REG32(ADR_PAD24)) & 0xffff8fff))
++#define SET_GPIO_TEST_4_ID(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 28) | ((REG32(ADR_PAD24)) & 0xefffffff))
++#define SET_PAD25_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 0) | ((REG32(ADR_PAD25)) & 0xfffffffe))
++#define SET_PAD25_PE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 1) | ((REG32(ADR_PAD25)) & 0xfffffffd))
++#define SET_PAD25_DS(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 2) | ((REG32(ADR_PAD25)) & 0xfffffffb))
++#define SET_PAD25_IE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 3) | ((REG32(ADR_PAD25)) & 0xfffffff7))
++#define SET_PAD25_SEL_I(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 4) | ((REG32(ADR_PAD25)) & 0xffffff8f))
++#define SET_PAD25_OD(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 8) | ((REG32(ADR_PAD25)) & 0xfffffeff))
++#define SET_PAD25_SEL_O(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 12) | ((REG32(ADR_PAD25)) & 0xffff8fff))
++#define SET_PAD25_SEL_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 20) | ((REG32(ADR_PAD25)) & 0xffefffff))
++#define SET_STRAP1(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 27) | ((REG32(ADR_PAD25)) & 0xf7ffffff))
++#define SET_GPIO_1_ID(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 28) | ((REG32(ADR_PAD25)) & 0xefffffff))
++#define SET_PAD27_OE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 0) | ((REG32(ADR_PAD27)) & 0xfffffffe))
++#define SET_PAD27_PE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 1) | ((REG32(ADR_PAD27)) & 0xfffffffd))
++#define SET_PAD27_DS(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 2) | ((REG32(ADR_PAD27)) & 0xfffffffb))
++#define SET_PAD27_IE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 3) | ((REG32(ADR_PAD27)) & 0xfffffff7))
++#define SET_PAD27_SEL_I(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 4) | ((REG32(ADR_PAD27)) & 0xffffff8f))
++#define SET_PAD27_OD(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 8) | ((REG32(ADR_PAD27)) & 0xfffffeff))
++#define SET_PAD27_SEL_O(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 12) | ((REG32(ADR_PAD27)) & 0xffff8fff))
++#define SET_GPIO_2_ID(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 28) | ((REG32(ADR_PAD27)) & 0xefffffff))
++#define SET_PAD28_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 0) | ((REG32(ADR_PAD28)) & 0xfffffffe))
++#define SET_PAD28_PE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 1) | ((REG32(ADR_PAD28)) & 0xfffffffd))
++#define SET_PAD28_DS(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 2) | ((REG32(ADR_PAD28)) & 0xfffffffb))
++#define SET_PAD28_IE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 3) | ((REG32(ADR_PAD28)) & 0xfffffff7))
++#define SET_PAD28_SEL_I(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 4) | ((REG32(ADR_PAD28)) & 0xffffff8f))
++#define SET_PAD28_OD(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 8) | ((REG32(ADR_PAD28)) & 0xfffffeff))
++#define SET_PAD28_SEL_O(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 12) | ((REG32(ADR_PAD28)) & 0xffff0fff))
++#define SET_PAD28_SEL_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 20) | ((REG32(ADR_PAD28)) & 0xffefffff))
++#define SET_GPIO_3_ID(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 28) | ((REG32(ADR_PAD28)) & 0xefffffff))
++#define SET_PAD29_OE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 0) | ((REG32(ADR_PAD29)) & 0xfffffffe))
++#define SET_PAD29_PE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 1) | ((REG32(ADR_PAD29)) & 0xfffffffd))
++#define SET_PAD29_DS(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 2) | ((REG32(ADR_PAD29)) & 0xfffffffb))
++#define SET_PAD29_IE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 3) | ((REG32(ADR_PAD29)) & 0xfffffff7))
++#define SET_PAD29_SEL_I(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 4) | ((REG32(ADR_PAD29)) & 0xffffff8f))
++#define SET_PAD29_OD(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 8) | ((REG32(ADR_PAD29)) & 0xfffffeff))
++#define SET_PAD29_SEL_O(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 12) | ((REG32(ADR_PAD29)) & 0xffff8fff))
++#define SET_GPIO_TEST_5_ID(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 28) | ((REG32(ADR_PAD29)) & 0xefffffff))
++#define SET_PAD30_OE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 0) | ((REG32(ADR_PAD30)) & 0xfffffffe))
++#define SET_PAD30_PE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 1) | ((REG32(ADR_PAD30)) & 0xfffffffd))
++#define SET_PAD30_DS(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 2) | ((REG32(ADR_PAD30)) & 0xfffffffb))
++#define SET_PAD30_IE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 3) | ((REG32(ADR_PAD30)) & 0xfffffff7))
++#define SET_PAD30_SEL_I(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 4) | ((REG32(ADR_PAD30)) & 0xffffffcf))
++#define SET_PAD30_OD(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 8) | ((REG32(ADR_PAD30)) & 0xfffffeff))
++#define SET_PAD30_SEL_O(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 12) | ((REG32(ADR_PAD30)) & 0xffffcfff))
++#define SET_TEST_6_ID(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 28) | ((REG32(ADR_PAD30)) & 0xefffffff))
++#define SET_PAD31_OE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 0) | ((REG32(ADR_PAD31)) & 0xfffffffe))
++#define SET_PAD31_PE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 1) | ((REG32(ADR_PAD31)) & 0xfffffffd))
++#define SET_PAD31_DS(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 2) | ((REG32(ADR_PAD31)) & 0xfffffffb))
++#define SET_PAD31_IE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 3) | ((REG32(ADR_PAD31)) & 0xfffffff7))
++#define SET_PAD31_SEL_I(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 4) | ((REG32(ADR_PAD31)) & 0xffffffcf))
++#define SET_PAD31_OD(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 8) | ((REG32(ADR_PAD31)) & 0xfffffeff))
++#define SET_PAD31_SEL_O(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 12) | ((REG32(ADR_PAD31)) & 0xffffcfff))
++#define SET_TEST_7_ID(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 28) | ((REG32(ADR_PAD31)) & 0xefffffff))
++#define SET_PAD32_OE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 0) | ((REG32(ADR_PAD32)) & 0xfffffffe))
++#define SET_PAD32_PE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 1) | ((REG32(ADR_PAD32)) & 0xfffffffd))
++#define SET_PAD32_DS(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 2) | ((REG32(ADR_PAD32)) & 0xfffffffb))
++#define SET_PAD32_IE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 3) | ((REG32(ADR_PAD32)) & 0xfffffff7))
++#define SET_PAD32_SEL_I(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 4) | ((REG32(ADR_PAD32)) & 0xffffffcf))
++#define SET_PAD32_OD(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 8) | ((REG32(ADR_PAD32)) & 0xfffffeff))
++#define SET_PAD32_SEL_O(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 12) | ((REG32(ADR_PAD32)) & 0xffffcfff))
++#define SET_TEST_8_ID(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 28) | ((REG32(ADR_PAD32)) & 0xefffffff))
++#define SET_PAD33_OE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 0) | ((REG32(ADR_PAD33)) & 0xfffffffe))
++#define SET_PAD33_PE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 1) | ((REG32(ADR_PAD33)) & 0xfffffffd))
++#define SET_PAD33_DS(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 2) | ((REG32(ADR_PAD33)) & 0xfffffffb))
++#define SET_PAD33_IE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 3) | ((REG32(ADR_PAD33)) & 0xfffffff7))
++#define SET_PAD33_SEL_I(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 4) | ((REG32(ADR_PAD33)) & 0xffffffcf))
++#define SET_PAD33_OD(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 8) | ((REG32(ADR_PAD33)) & 0xfffffeff))
++#define SET_PAD33_SEL_O(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 12) | ((REG32(ADR_PAD33)) & 0xffffcfff))
++#define SET_TEST_9_ID(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 28) | ((REG32(ADR_PAD33)) & 0xefffffff))
++#define SET_PAD34_OE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 0) | ((REG32(ADR_PAD34)) & 0xfffffffe))
++#define SET_PAD34_PE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 1) | ((REG32(ADR_PAD34)) & 0xfffffffd))
++#define SET_PAD34_DS(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 2) | ((REG32(ADR_PAD34)) & 0xfffffffb))
++#define SET_PAD34_IE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 3) | ((REG32(ADR_PAD34)) & 0xfffffff7))
++#define SET_PAD34_SEL_I(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 4) | ((REG32(ADR_PAD34)) & 0xffffffcf))
++#define SET_PAD34_OD(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 8) | ((REG32(ADR_PAD34)) & 0xfffffeff))
++#define SET_PAD34_SEL_O(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 12) | ((REG32(ADR_PAD34)) & 0xffffcfff))
++#define SET_TEST_10_ID(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 28) | ((REG32(ADR_PAD34)) & 0xefffffff))
++#define SET_PAD42_OE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 0) | ((REG32(ADR_PAD42)) & 0xfffffffe))
++#define SET_PAD42_PE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 1) | ((REG32(ADR_PAD42)) & 0xfffffffd))
++#define SET_PAD42_DS(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 2) | ((REG32(ADR_PAD42)) & 0xfffffffb))
++#define SET_PAD42_IE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 3) | ((REG32(ADR_PAD42)) & 0xfffffff7))
++#define SET_PAD42_SEL_I(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 4) | ((REG32(ADR_PAD42)) & 0xffffffcf))
++#define SET_PAD42_OD(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 8) | ((REG32(ADR_PAD42)) & 0xfffffeff))
++#define SET_PAD42_SEL_O(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 12) | ((REG32(ADR_PAD42)) & 0xffffefff))
++#define SET_TEST_11_ID(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 28) | ((REG32(ADR_PAD42)) & 0xefffffff))
++#define SET_PAD43_OE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 0) | ((REG32(ADR_PAD43)) & 0xfffffffe))
++#define SET_PAD43_PE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 1) | ((REG32(ADR_PAD43)) & 0xfffffffd))
++#define SET_PAD43_DS(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 2) | ((REG32(ADR_PAD43)) & 0xfffffffb))
++#define SET_PAD43_IE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 3) | ((REG32(ADR_PAD43)) & 0xfffffff7))
++#define SET_PAD43_SEL_I(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 4) | ((REG32(ADR_PAD43)) & 0xffffffcf))
++#define SET_PAD43_OD(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 8) | ((REG32(ADR_PAD43)) & 0xfffffeff))
++#define SET_PAD43_SEL_O(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 12) | ((REG32(ADR_PAD43)) & 0xffffefff))
++#define SET_TEST_12_ID(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 28) | ((REG32(ADR_PAD43)) & 0xefffffff))
++#define SET_PAD44_OE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 0) | ((REG32(ADR_PAD44)) & 0xfffffffe))
++#define SET_PAD44_PE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 1) | ((REG32(ADR_PAD44)) & 0xfffffffd))
++#define SET_PAD44_DS(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 2) | ((REG32(ADR_PAD44)) & 0xfffffffb))
++#define SET_PAD44_IE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 3) | ((REG32(ADR_PAD44)) & 0xfffffff7))
++#define SET_PAD44_SEL_I(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 4) | ((REG32(ADR_PAD44)) & 0xffffffcf))
++#define SET_PAD44_OD(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 8) | ((REG32(ADR_PAD44)) & 0xfffffeff))
++#define SET_PAD44_SEL_O(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 12) | ((REG32(ADR_PAD44)) & 0xffffcfff))
++#define SET_TEST_13_ID(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 28) | ((REG32(ADR_PAD44)) & 0xefffffff))
++#define SET_PAD45_OE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 0) | ((REG32(ADR_PAD45)) & 0xfffffffe))
++#define SET_PAD45_PE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 1) | ((REG32(ADR_PAD45)) & 0xfffffffd))
++#define SET_PAD45_DS(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 2) | ((REG32(ADR_PAD45)) & 0xfffffffb))
++#define SET_PAD45_IE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 3) | ((REG32(ADR_PAD45)) & 0xfffffff7))
++#define SET_PAD45_SEL_I(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 4) | ((REG32(ADR_PAD45)) & 0xffffffcf))
++#define SET_PAD45_OD(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 8) | ((REG32(ADR_PAD45)) & 0xfffffeff))
++#define SET_PAD45_SEL_O(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 12) | ((REG32(ADR_PAD45)) & 0xffffcfff))
++#define SET_TEST_14_ID(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 28) | ((REG32(ADR_PAD45)) & 0xefffffff))
++#define SET_PAD46_OE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 0) | ((REG32(ADR_PAD46)) & 0xfffffffe))
++#define SET_PAD46_PE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 1) | ((REG32(ADR_PAD46)) & 0xfffffffd))
++#define SET_PAD46_DS(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 2) | ((REG32(ADR_PAD46)) & 0xfffffffb))
++#define SET_PAD46_IE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 3) | ((REG32(ADR_PAD46)) & 0xfffffff7))
++#define SET_PAD46_SEL_I(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 4) | ((REG32(ADR_PAD46)) & 0xffffffcf))
++#define SET_PAD46_OD(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 8) | ((REG32(ADR_PAD46)) & 0xfffffeff))
++#define SET_PAD46_SEL_O(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 12) | ((REG32(ADR_PAD46)) & 0xffffcfff))
++#define SET_TEST_15_ID(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 28) | ((REG32(ADR_PAD46)) & 0xefffffff))
++#define SET_PAD47_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 0) | ((REG32(ADR_PAD47)) & 0xfffffffe))
++#define SET_PAD47_PE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 1) | ((REG32(ADR_PAD47)) & 0xfffffffd))
++#define SET_PAD47_DS(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 2) | ((REG32(ADR_PAD47)) & 0xfffffffb))
++#define SET_PAD47_SEL_I(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 4) | ((REG32(ADR_PAD47)) & 0xffffffcf))
++#define SET_PAD47_OD(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 8) | ((REG32(ADR_PAD47)) & 0xfffffeff))
++#define SET_PAD47_SEL_O(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 12) | ((REG32(ADR_PAD47)) & 0xffffcfff))
++#define SET_PAD47_SEL_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 20) | ((REG32(ADR_PAD47)) & 0xffefffff))
++#define SET_GPIO_9_ID(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 28) | ((REG32(ADR_PAD47)) & 0xefffffff))
++#define SET_PAD48_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 0) | ((REG32(ADR_PAD48)) & 0xfffffffe))
++#define SET_PAD48_PE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 1) | ((REG32(ADR_PAD48)) & 0xfffffffd))
++#define SET_PAD48_DS(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 2) | ((REG32(ADR_PAD48)) & 0xfffffffb))
++#define SET_PAD48_IE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 3) | ((REG32(ADR_PAD48)) & 0xfffffff7))
++#define SET_PAD48_SEL_I(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 4) | ((REG32(ADR_PAD48)) & 0xffffff8f))
++#define SET_PAD48_OD(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 8) | ((REG32(ADR_PAD48)) & 0xfffffeff))
++#define SET_PAD48_PE_SEL(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 11) | ((REG32(ADR_PAD48)) & 0xfffff7ff))
++#define SET_PAD48_SEL_O(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 12) | ((REG32(ADR_PAD48)) & 0xffffcfff))
++#define SET_PAD48_SEL_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 20) | ((REG32(ADR_PAD48)) & 0xffefffff))
++#define SET_GPIO_10_ID(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 28) | ((REG32(ADR_PAD48)) & 0xefffffff))
++#define SET_PAD49_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 0) | ((REG32(ADR_PAD49)) & 0xfffffffe))
++#define SET_PAD49_PE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 1) | ((REG32(ADR_PAD49)) & 0xfffffffd))
++#define SET_PAD49_DS(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 2) | ((REG32(ADR_PAD49)) & 0xfffffffb))
++#define SET_PAD49_IE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 3) | ((REG32(ADR_PAD49)) & 0xfffffff7))
++#define SET_PAD49_SEL_I(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 4) | ((REG32(ADR_PAD49)) & 0xffffff8f))
++#define SET_PAD49_OD(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 8) | ((REG32(ADR_PAD49)) & 0xfffffeff))
++#define SET_PAD49_SEL_O(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 12) | ((REG32(ADR_PAD49)) & 0xffffcfff))
++#define SET_PAD49_SEL_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 20) | ((REG32(ADR_PAD49)) & 0xffefffff))
++#define SET_GPIO_11_ID(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 28) | ((REG32(ADR_PAD49)) & 0xefffffff))
++#define SET_PAD50_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 0) | ((REG32(ADR_PAD50)) & 0xfffffffe))
++#define SET_PAD50_PE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 1) | ((REG32(ADR_PAD50)) & 0xfffffffd))
++#define SET_PAD50_DS(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 2) | ((REG32(ADR_PAD50)) & 0xfffffffb))
++#define SET_PAD50_IE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 3) | ((REG32(ADR_PAD50)) & 0xfffffff7))
++#define SET_PAD50_SEL_I(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 4) | ((REG32(ADR_PAD50)) & 0xffffff8f))
++#define SET_PAD50_OD(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 8) | ((REG32(ADR_PAD50)) & 0xfffffeff))
++#define SET_PAD50_SEL_O(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 12) | ((REG32(ADR_PAD50)) & 0xffffcfff))
++#define SET_PAD50_SEL_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 20) | ((REG32(ADR_PAD50)) & 0xffefffff))
++#define SET_GPIO_12_ID(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 28) | ((REG32(ADR_PAD50)) & 0xefffffff))
++#define SET_PAD51_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 0) | ((REG32(ADR_PAD51)) & 0xfffffffe))
++#define SET_PAD51_PE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 1) | ((REG32(ADR_PAD51)) & 0xfffffffd))
++#define SET_PAD51_DS(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 2) | ((REG32(ADR_PAD51)) & 0xfffffffb))
++#define SET_PAD51_IE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 3) | ((REG32(ADR_PAD51)) & 0xfffffff7))
++#define SET_PAD51_SEL_I(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 4) | ((REG32(ADR_PAD51)) & 0xffffffcf))
++#define SET_PAD51_OD(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 8) | ((REG32(ADR_PAD51)) & 0xfffffeff))
++#define SET_PAD51_SEL_O(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 12) | ((REG32(ADR_PAD51)) & 0xffffefff))
++#define SET_PAD51_SEL_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 20) | ((REG32(ADR_PAD51)) & 0xffefffff))
++#define SET_GPIO_13_ID(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 28) | ((REG32(ADR_PAD51)) & 0xefffffff))
++#define SET_PAD52_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 0) | ((REG32(ADR_PAD52)) & 0xfffffffe))
++#define SET_PAD52_PE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 1) | ((REG32(ADR_PAD52)) & 0xfffffffd))
++#define SET_PAD52_DS(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 2) | ((REG32(ADR_PAD52)) & 0xfffffffb))
++#define SET_PAD52_SEL_I(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 4) | ((REG32(ADR_PAD52)) & 0xffffffcf))
++#define SET_PAD52_OD(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 8) | ((REG32(ADR_PAD52)) & 0xfffffeff))
++#define SET_PAD52_SEL_O(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 12) | ((REG32(ADR_PAD52)) & 0xffffefff))
++#define SET_PAD52_SEL_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 20) | ((REG32(ADR_PAD52)) & 0xffefffff))
++#define SET_GPIO_14_ID(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 28) | ((REG32(ADR_PAD52)) & 0xefffffff))
++#define SET_PAD53_OE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 0) | ((REG32(ADR_PAD53)) & 0xfffffffe))
++#define SET_PAD53_PE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 1) | ((REG32(ADR_PAD53)) & 0xfffffffd))
++#define SET_PAD53_DS(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 2) | ((REG32(ADR_PAD53)) & 0xfffffffb))
++#define SET_PAD53_IE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 3) | ((REG32(ADR_PAD53)) & 0xfffffff7))
++#define SET_PAD53_SEL_I(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 4) | ((REG32(ADR_PAD53)) & 0xffffffcf))
++#define SET_PAD53_OD(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 8) | ((REG32(ADR_PAD53)) & 0xfffffeff))
++#define SET_PAD53_SEL_O(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 12) | ((REG32(ADR_PAD53)) & 0xffffefff))
++#define SET_JTAG_TMS_ID(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 28) | ((REG32(ADR_PAD53)) & 0xefffffff))
++#define SET_PAD54_OE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 0) | ((REG32(ADR_PAD54)) & 0xfffffffe))
++#define SET_PAD54_PE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 1) | ((REG32(ADR_PAD54)) & 0xfffffffd))
++#define SET_PAD54_DS(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 2) | ((REG32(ADR_PAD54)) & 0xfffffffb))
++#define SET_PAD54_OD(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 8) | ((REG32(ADR_PAD54)) & 0xfffffeff))
++#define SET_PAD54_SEL_O(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 12) | ((REG32(ADR_PAD54)) & 0xffffcfff))
++#define SET_JTAG_TCK_ID(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 28) | ((REG32(ADR_PAD54)) & 0xefffffff))
++#define SET_PAD56_PE(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 1) | ((REG32(ADR_PAD56)) & 0xfffffffd))
++#define SET_PAD56_DS(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 2) | ((REG32(ADR_PAD56)) & 0xfffffffb))
++#define SET_PAD56_SEL_I(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 4) | ((REG32(ADR_PAD56)) & 0xffffffef))
++#define SET_PAD56_OD(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 8) | ((REG32(ADR_PAD56)) & 0xfffffeff))
++#define SET_JTAG_TDI_ID(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 28) | ((REG32(ADR_PAD56)) & 0xefffffff))
++#define SET_PAD57_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 0) | ((REG32(ADR_PAD57)) & 0xfffffffe))
++#define SET_PAD57_PE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 1) | ((REG32(ADR_PAD57)) & 0xfffffffd))
++#define SET_PAD57_DS(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 2) | ((REG32(ADR_PAD57)) & 0xfffffffb))
++#define SET_PAD57_IE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 3) | ((REG32(ADR_PAD57)) & 0xfffffff7))
++#define SET_PAD57_SEL_I(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 4) | ((REG32(ADR_PAD57)) & 0xffffffcf))
++#define SET_PAD57_OD(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 8) | ((REG32(ADR_PAD57)) & 0xfffffeff))
++#define SET_PAD57_SEL_O(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 12) | ((REG32(ADR_PAD57)) & 0xffffcfff))
++#define SET_PAD57_SEL_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 20) | ((REG32(ADR_PAD57)) & 0xffefffff))
++#define SET_JTAG_TDO_ID(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 28) | ((REG32(ADR_PAD57)) & 0xefffffff))
++#define SET_PAD58_OE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 0) | ((REG32(ADR_PAD58)) & 0xfffffffe))
++#define SET_PAD58_PE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 1) | ((REG32(ADR_PAD58)) & 0xfffffffd))
++#define SET_PAD58_DS(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 2) | ((REG32(ADR_PAD58)) & 0xfffffffb))
++#define SET_PAD58_IE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 3) | ((REG32(ADR_PAD58)) & 0xfffffff7))
++#define SET_PAD58_SEL_I(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 4) | ((REG32(ADR_PAD58)) & 0xffffffcf))
++#define SET_PAD58_OD(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 8) | ((REG32(ADR_PAD58)) & 0xfffffeff))
++#define SET_PAD58_SEL_O(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 12) | ((REG32(ADR_PAD58)) & 0xffffefff))
++#define SET_TEST_16_ID(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 28) | ((REG32(ADR_PAD58)) & 0xefffffff))
++#define SET_PAD59_OE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 0) | ((REG32(ADR_PAD59)) & 0xfffffffe))
++#define SET_PAD59_PE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 1) | ((REG32(ADR_PAD59)) & 0xfffffffd))
++#define SET_PAD59_DS(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 2) | ((REG32(ADR_PAD59)) & 0xfffffffb))
++#define SET_PAD59_IE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 3) | ((REG32(ADR_PAD59)) & 0xfffffff7))
++#define SET_PAD59_SEL_I(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 4) | ((REG32(ADR_PAD59)) & 0xffffffcf))
++#define SET_PAD59_OD(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 8) | ((REG32(ADR_PAD59)) & 0xfffffeff))
++#define SET_PAD59_SEL_O(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 12) | ((REG32(ADR_PAD59)) & 0xffffefff))
++#define SET_TEST_17_ID(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 28) | ((REG32(ADR_PAD59)) & 0xefffffff))
++#define SET_PAD60_OE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 0) | ((REG32(ADR_PAD60)) & 0xfffffffe))
++#define SET_PAD60_PE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 1) | ((REG32(ADR_PAD60)) & 0xfffffffd))
++#define SET_PAD60_DS(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 2) | ((REG32(ADR_PAD60)) & 0xfffffffb))
++#define SET_PAD60_IE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 3) | ((REG32(ADR_PAD60)) & 0xfffffff7))
++#define SET_PAD60_SEL_I(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 4) | ((REG32(ADR_PAD60)) & 0xffffffcf))
++#define SET_PAD60_OD(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 8) | ((REG32(ADR_PAD60)) & 0xfffffeff))
++#define SET_PAD60_SEL_O(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 12) | ((REG32(ADR_PAD60)) & 0xffffefff))
++#define SET_TEST_18_ID(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 28) | ((REG32(ADR_PAD60)) & 0xefffffff))
++#define SET_PAD61_OE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 0) | ((REG32(ADR_PAD61)) & 0xfffffffe))
++#define SET_PAD61_PE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 1) | ((REG32(ADR_PAD61)) & 0xfffffffd))
++#define SET_PAD61_DS(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 2) | ((REG32(ADR_PAD61)) & 0xfffffffb))
++#define SET_PAD61_IE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 3) | ((REG32(ADR_PAD61)) & 0xfffffff7))
++#define SET_PAD61_SEL_I(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 4) | ((REG32(ADR_PAD61)) & 0xffffffef))
++#define SET_PAD61_OD(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 8) | ((REG32(ADR_PAD61)) & 0xfffffeff))
++#define SET_PAD61_SEL_O(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 12) | ((REG32(ADR_PAD61)) & 0xffffcfff))
++#define SET_TEST_19_ID(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 28) | ((REG32(ADR_PAD61)) & 0xefffffff))
++#define SET_PAD62_OE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 0) | ((REG32(ADR_PAD62)) & 0xfffffffe))
++#define SET_PAD62_PE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 1) | ((REG32(ADR_PAD62)) & 0xfffffffd))
++#define SET_PAD62_DS(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 2) | ((REG32(ADR_PAD62)) & 0xfffffffb))
++#define SET_PAD62_IE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 3) | ((REG32(ADR_PAD62)) & 0xfffffff7))
++#define SET_PAD62_SEL_I(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 4) | ((REG32(ADR_PAD62)) & 0xffffffef))
++#define SET_PAD62_OD(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 8) | ((REG32(ADR_PAD62)) & 0xfffffeff))
++#define SET_PAD62_SEL_O(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 12) | ((REG32(ADR_PAD62)) & 0xffffefff))
++#define SET_TEST_20_ID(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 28) | ((REG32(ADR_PAD62)) & 0xefffffff))
++#define SET_PAD64_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 0) | ((REG32(ADR_PAD64)) & 0xfffffffe))
++#define SET_PAD64_PE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 1) | ((REG32(ADR_PAD64)) & 0xfffffffd))
++#define SET_PAD64_DS(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 2) | ((REG32(ADR_PAD64)) & 0xfffffffb))
++#define SET_PAD64_IE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 3) | ((REG32(ADR_PAD64)) & 0xfffffff7))
++#define SET_PAD64_SEL_I(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 4) | ((REG32(ADR_PAD64)) & 0xffffff8f))
++#define SET_PAD64_OD(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 8) | ((REG32(ADR_PAD64)) & 0xfffffeff))
++#define SET_PAD64_SEL_O(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 12) | ((REG32(ADR_PAD64)) & 0xffffcfff))
++#define SET_PAD64_SEL_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 20) | ((REG32(ADR_PAD64)) & 0xffefffff))
++#define SET_GPIO_15_IP_ID(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 28) | ((REG32(ADR_PAD64)) & 0xefffffff))
++#define SET_PAD65_OE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 0) | ((REG32(ADR_PAD65)) & 0xfffffffe))
++#define SET_PAD65_PE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 1) | ((REG32(ADR_PAD65)) & 0xfffffffd))
++#define SET_PAD65_DS(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 2) | ((REG32(ADR_PAD65)) & 0xfffffffb))
++#define SET_PAD65_IE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 3) | ((REG32(ADR_PAD65)) & 0xfffffff7))
++#define SET_PAD65_SEL_I(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 4) | ((REG32(ADR_PAD65)) & 0xffffff8f))
++#define SET_PAD65_OD(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 8) | ((REG32(ADR_PAD65)) & 0xfffffeff))
++#define SET_PAD65_SEL_O(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 12) | ((REG32(ADR_PAD65)) & 0xffffefff))
++#define SET_GPIO_TEST_7_IN_ID(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 28) | ((REG32(ADR_PAD65)) & 0xefffffff))
++#define SET_PAD66_OE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 0) | ((REG32(ADR_PAD66)) & 0xfffffffe))
++#define SET_PAD66_PE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 1) | ((REG32(ADR_PAD66)) & 0xfffffffd))
++#define SET_PAD66_DS(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 2) | ((REG32(ADR_PAD66)) & 0xfffffffb))
++#define SET_PAD66_IE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 3) | ((REG32(ADR_PAD66)) & 0xfffffff7))
++#define SET_PAD66_SEL_I(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 4) | ((REG32(ADR_PAD66)) & 0xffffffcf))
++#define SET_PAD66_OD(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 8) | ((REG32(ADR_PAD66)) & 0xfffffeff))
++#define SET_PAD66_SEL_O(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 12) | ((REG32(ADR_PAD66)) & 0xffffcfff))
++#define SET_GPIO_17_QP_ID(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 28) | ((REG32(ADR_PAD66)) & 0xefffffff))
++#define SET_PAD68_OE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 0) | ((REG32(ADR_PAD68)) & 0xfffffffe))
++#define SET_PAD68_PE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 1) | ((REG32(ADR_PAD68)) & 0xfffffffd))
++#define SET_PAD68_DS(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 2) | ((REG32(ADR_PAD68)) & 0xfffffffb))
++#define SET_PAD68_IE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 3) | ((REG32(ADR_PAD68)) & 0xfffffff7))
++#define SET_PAD68_OD(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 8) | ((REG32(ADR_PAD68)) & 0xfffffeff))
++#define SET_PAD68_SEL_O(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 12) | ((REG32(ADR_PAD68)) & 0xffffefff))
++#define SET_GPIO_19_ID(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 28) | ((REG32(ADR_PAD68)) & 0xefffffff))
++#define SET_PAD67_OE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 0) | ((REG32(ADR_PAD67)) & 0xfffffffe))
++#define SET_PAD67_PE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 1) | ((REG32(ADR_PAD67)) & 0xfffffffd))
++#define SET_PAD67_DS(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 2) | ((REG32(ADR_PAD67)) & 0xfffffffb))
++#define SET_PAD67_IE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 3) | ((REG32(ADR_PAD67)) & 0xfffffff7))
++#define SET_PAD67_SEL_I(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 4) | ((REG32(ADR_PAD67)) & 0xffffff8f))
++#define SET_PAD67_OD(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 8) | ((REG32(ADR_PAD67)) & 0xfffffeff))
++#define SET_PAD67_SEL_O(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 12) | ((REG32(ADR_PAD67)) & 0xffffcfff))
++#define SET_GPIO_TEST_8_QN_ID(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 28) | ((REG32(ADR_PAD67)) & 0xefffffff))
++#define SET_PAD69_OE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 0) | ((REG32(ADR_PAD69)) & 0xfffffffe))
++#define SET_PAD69_PE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 1) | ((REG32(ADR_PAD69)) & 0xfffffffd))
++#define SET_PAD69_DS(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 2) | ((REG32(ADR_PAD69)) & 0xfffffffb))
++#define SET_PAD69_IE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 3) | ((REG32(ADR_PAD69)) & 0xfffffff7))
++#define SET_PAD69_SEL_I(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 4) | ((REG32(ADR_PAD69)) & 0xffffffcf))
++#define SET_PAD69_OD(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 8) | ((REG32(ADR_PAD69)) & 0xfffffeff))
++#define SET_PAD69_SEL_O(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 12) | ((REG32(ADR_PAD69)) & 0xffffefff))
++#define SET_STRAP2(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 27) | ((REG32(ADR_PAD69)) & 0xf7ffffff))
++#define SET_GPIO_20_ID(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 28) | ((REG32(ADR_PAD69)) & 0xefffffff))
++#define SET_PAD70_OE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 0) | ((REG32(ADR_PAD70)) & 0xfffffffe))
++#define SET_PAD70_PE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 1) | ((REG32(ADR_PAD70)) & 0xfffffffd))
++#define SET_PAD70_DS(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 2) | ((REG32(ADR_PAD70)) & 0xfffffffb))
++#define SET_PAD70_IE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 3) | ((REG32(ADR_PAD70)) & 0xfffffff7))
++#define SET_PAD70_SEL_I(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 4) | ((REG32(ADR_PAD70)) & 0xffffffcf))
++#define SET_PAD70_OD(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 8) | ((REG32(ADR_PAD70)) & 0xfffffeff))
++#define SET_PAD70_SEL_O(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 12) | ((REG32(ADR_PAD70)) & 0xffff8fff))
++#define SET_GPIO_21_ID(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 28) | ((REG32(ADR_PAD70)) & 0xefffffff))
++#define SET_PAD231_OE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 0) | ((REG32(ADR_PAD231)) & 0xfffffffe))
++#define SET_PAD231_PE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 1) | ((REG32(ADR_PAD231)) & 0xfffffffd))
++#define SET_PAD231_DS(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 2) | ((REG32(ADR_PAD231)) & 0xfffffffb))
++#define SET_PAD231_IE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 3) | ((REG32(ADR_PAD231)) & 0xfffffff7))
++#define SET_PAD231_OD(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 8) | ((REG32(ADR_PAD231)) & 0xfffffeff))
++#define SET_PIN_40_OR_56_ID(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 28) | ((REG32(ADR_PAD231)) & 0xefffffff))
++#define SET_MP_PHY2RX_DATA__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffe))
++#define SET_MP_PHY2RX_DATA__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffd))
++#define SET_MP_TX_FF_RPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 2) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffb))
++#define SET_MP_RX_FF_WPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 3) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffff7))
++#define SET_MP_RX_FF_WPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 4) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffef))
++#define SET_MP_RX_FF_WPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 5) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffdf))
++#define SET_MP_PHY2RX_DATA__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 6) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffbf))
++#define SET_MP_PHY2RX_DATA__4_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 7) | ((REG32(ADR_PIN_SEL_0)) & 0xffffff7f))
++#define SET_I2CM_SDA_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 8) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffcff))
++#define SET_CRYSTAL_OUT_REQ_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 10) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffbff))
++#define SET_MP_PHY2RX_DATA__5_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 11) | ((REG32(ADR_PIN_SEL_0)) & 0xfffff7ff))
++#define SET_MP_PHY2RX_DATA__3_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 12) | ((REG32(ADR_PIN_SEL_0)) & 0xffffefff))
++#define SET_UART_RXD_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 13) | ((REG32(ADR_PIN_SEL_0)) & 0xffff9fff))
++#define SET_MP_PHY2RX_DATA__6_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 15) | ((REG32(ADR_PIN_SEL_0)) & 0xffff7fff))
++#define SET_DAT_UART_NCTS_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 16) | ((REG32(ADR_PIN_SEL_0)) & 0xfffeffff))
++#define SET_GPIO_LOG_STOP_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 17) | ((REG32(ADR_PIN_SEL_0)) & 0xfff1ffff))
++#define SET_MP_TX_FF_RPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 20) | ((REG32(ADR_PIN_SEL_0)) & 0xffefffff))
++#define SET_MP_PHY_RX_WRST_N_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 21) | ((REG32(ADR_PIN_SEL_0)) & 0xffdfffff))
++#define SET_EXT_32K_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 22) | ((REG32(ADR_PIN_SEL_0)) & 0xff3fffff))
++#define SET_MP_PHY2RX_DATA__7_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 24) | ((REG32(ADR_PIN_SEL_0)) & 0xfeffffff))
++#define SET_MP_TX_FF_RPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 25) | ((REG32(ADR_PIN_SEL_0)) & 0xfdffffff))
++#define SET_PMUINT_WAKE_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 26) | ((REG32(ADR_PIN_SEL_0)) & 0xe3ffffff))
++#define SET_I2CM_SCL_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 29) | ((REG32(ADR_PIN_SEL_0)) & 0xdfffffff))
++#define SET_MP_MRX_RX_EN_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 30) | ((REG32(ADR_PIN_SEL_0)) & 0xbfffffff))
++#define SET_DAT_UART_RXD_SEL_0(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 31) | ((REG32(ADR_PIN_SEL_0)) & 0x7fffffff))
++#define SET_DAT_UART_RXD_SEL_1(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffe))
++#define SET_SPI_DI_SEL(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffd))
++#define SET_IO_PORT_REG(_VAL_) (REG32(ADR_IO_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_PORT_REG)) & 0xfffe0000))
++#define SET_MASK_RX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffe))
++#define SET_MASK_TX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffd))
++#define SET_MASK_SOC_SYSTEM_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffb))
++#define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffff7))
++#define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffef))
++#define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffdf))
++#define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffbf))
++#define SET_TX_LIMIT_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_MASK_REG)) & 0xffffff7f))
++#define SET_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffe))
++#define SET_TX_COMPLETE_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffd))
++#define SET_SOC_SYSTEM_INT_STATUS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffb))
++#define SET_EDCA0_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffff7))
++#define SET_EDCA1_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffef))
++#define SET_EDCA2_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffdf))
++#define SET_EDCA3_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffbf))
++#define SET_TX_LIMIT_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffff7f))
++#define SET_HOST_TRIGGERED_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffeff))
++#define SET_HOST_TRIGGERED_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 9) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffdff))
++#define SET_SOC_TRIGGER_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 10) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffbff))
++#define SET_SOC_TRIGGER_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 11) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffff7ff))
++#define SET_RDY_FOR_TX_RX(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffe))
++#define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffd))
++#define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffb))
++#define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffff7))
++#define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffffef))
++#define SET_TRIGGER_FUNCTION_SETTING(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff9f))
++#define SET_CMD52_ABORT_RESPONSE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff7f))
++#define SET_RX_PACKET_LENGTH(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xffff0000))
++#define SET_CARD_FW_DL_STATUS(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 16) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xff00ffff))
++#define SET_TX_RX_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 24) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfeffffff))
++#define SET_SDIO_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 25) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfdffffff))
++#define SET_CMD52_ABORT_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 28) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xefffffff))
++#define SET_CMD52_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 29) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xdfffffff))
++#define SET_SDIO_PARTIAL_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 30) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xbfffffff))
++#define SET_SDIO_ALL_RESE_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 31) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x7fffffff))
++#define SET_RX_PACKET_LENGTH2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xffff0000))
++#define SET_RX_INT1(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffeffff))
++#define SET_TX_DONE(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffdffff))
++#define SET_HCI_TRX_FINISH(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffbffff))
++#define SET_ALLOCATE_STATUS(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfff7ffff))
++#define SET_HCI_INPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xff0fffff))
++#define SET_HCI_OUTPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xe0ffffff))
++#define SET_AHB_HANG4(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 29) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xdfffffff))
++#define SET_HCI_IN_QUE_EMPTY(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 30) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xbfffffff))
++#define SET_SYSTEM_INT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x7fffffff))
++#define SET_CARD_RCA_REG(_VAL_) (REG32(ADR_CARD_RCA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_RCA_REG)) & 0xffff0000))
++#define SET_SDIO_FIFO_WR_THLD_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0xfffffe00))
++#define SET_SDIO_FIFO_WR_LIMIT_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0xfffffe00))
++#define SET_SDIO_TX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
++#define SET_SDIO_THLD_FOR_CMD53RD_REG(_VAL_) (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0xfffffe00))
++#define SET_SDIO_RX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
++#define SET_START_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffffff00))
++#define SET_END_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffff00ff))
++#define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0xffffff00))
++#define SET_SDIO_LAST_CMD_INDEX_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffffffc0))
++#define SET_SDIO_LAST_CMD_CRC_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffff80ff))
++#define SET_SDIO_LAST_CMD_ARG_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0x00000000))
++#define SET_SDIO_BUS_STATE_REG(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffffffe0))
++#define SET_SDIO_BUSY_LONG_CNT(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000ffff))
++#define SET_SDIO_CARD_STATUS_REG(_VAL_) (REG32(ADR_SDIO_CARD_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0x00000000))
++#define SET_R5_RESPONSE_FLAG(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 0) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xffffff00))
++#define SET_RESP_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 8) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffeff))
++#define SET_DAT_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 9) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffdff))
++#define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 16) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffeffff))
++#define SET_INT_THROUGH_PIN(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 17) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffdffff))
++#define SET_WRITE_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffffff00))
++#define SET_WRITE_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 8) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffff00ff))
++#define SET_READ_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff00ffff))
++#define SET_READ_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 24) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ffffff))
++#define SET_FN1_DMA_START_ADDR_REG(_VAL_) (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0x00000000))
++#define SET_SDIO_TO_MCU_INFO(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffff00))
++#define SET_SDIO_PARTIAL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffeff))
++#define SET_SDIO_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffdff))
++#define SET_PERI_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffbff))
++#define SET_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffff7ff))
++#define SET_AHB_BRIDGE_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffefff))
++#define SET_IO_REG_PORT_REG(_VAL_) (REG32(ADR_IO_REG_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_REG_PORT_REG)) & 0xfffe0000))
++#define SET_SDIO_FIFO_EMPTY_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000))
++#define SET_SDIO_FIFO_FULL_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff))
++#define SET_SDIO_CRC7_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000))
++#define SET_SDIO_CRC16_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff))
++#define SET_SDIO_RD_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfffffe00))
++#define SET_SDIO_WR_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfe00ffff))
++#define SET_CMD52_RD_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xfff0ffff))
++#define SET_CMD52_WR_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 20) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xff0fffff))
++#define SET_SDIO_FIFO_WR_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffffff00))
++#define SET_SDIO_FIFO_RD_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffff00ff))
++#define SET_SDIO_READ_DATA_CTRL(_VAL_) (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0xfffeffff))
++#define SET_TX_SIZE_BEFORE_SHIFT(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffff00))
++#define SET_TX_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffff8ff))
++#define SET_SDIO_TX_ALLOC_STATE(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffefff))
++#define SET_ALLOCATE_STATUS2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffeffff))
++#define SET_NO_ALLOCATE_SEND_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffdffff))
++#define SET_DOUBLE_ALLOCATE_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffbffff))
++#define SET_TX_DONE_STATUS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfff7ffff))
++#define SET_AHB_HANG2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffefffff))
++#define SET_HCI_TRX_FINISH2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffdfffff))
++#define SET_INTR_RX(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffbfffff))
++#define SET_HCI_INPUT_QUEUE_FULL(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xff7fffff))
++#define SET_ALLOCATESTATUS(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffe))
++#define SET_HCI_TRX_FINISH3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffd))
++#define SET_HCI_IN_QUE_EMPTY2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffb))
++#define SET_MTX_MNG_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffff7))
++#define SET_EDCA0_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffef))
++#define SET_EDCA1_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffdf))
++#define SET_EDCA2_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffbf))
++#define SET_EDCA3_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffff7f))
++#define SET_TX_PAGE_REMAIN2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffff00ff))
++#define SET_TX_ID_REMAIN3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff80ffff))
++#define SET_HCI_OUTPUT_FF_CNT_0(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff7fffff))
++#define SET_HCI_OUTPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xf0ffffff))
++#define SET_HCI_INPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_TX_INFORM)) & 0x0fffffff))
++#define SET_F1_BLOCK_SIZE_0_REG(_VAL_) (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (((_VAL_) << 0) | ((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0xfffff000))
++#define SET_START_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffffff00))
++#define SET_COMMAND_COUNTER(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff00ff))
++#define SET_CMD_LOG_PART1(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ffff))
++#define SET_CMD_LOG_PART2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000))
++#define SET_END_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff))
++#define SET_RX_PACKET_LENGTH3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xffff0000))
++#define SET_RX_INT3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xfffeffff))
++#define SET_TX_ID_REMAIN2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff01ffff))
++#define SET_TX_PAGE_REMAIN3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00ffffff))
++#define SET_CCCR_00H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_00H_REG)) & 0xffffff00))
++#define SET_CCCR_02H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_00H_REG)) & 0xff00ffff))
++#define SET_CCCR_03H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_00H_REG)) & 0x00ffffff))
++#define SET_CCCR_04H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_04H_REG)) & 0xffffff00))
++#define SET_CCCR_05H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_04H_REG)) & 0xffff00ff))
++#define SET_CCCR_06H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_04H_REG)) & 0xfff0ffff))
++#define SET_CCCR_07H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_04H_REG)) & 0x00ffffff))
++#define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffe))
++#define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 1) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffd))
++#define SET_SUPPORT_READ_WAIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 2) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffb))
++#define SET_SUPPORT_BUS_CONTROL(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 3) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffff7))
++#define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 4) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffef))
++#define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 5) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffdf))
++#define SET_LOW_SPEED_CARD(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffbf))
++#define SET_LOW_SPEED_CARD_4BIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffff7f))
++#define SET_COMMON_CIS_PONTER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_08H_REG)) & 0xfe0000ff))
++#define SET_SUPPORT_HIGH_SPEED(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_13H_REG)) & 0xfeffffff))
++#define SET_BSS(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 25) | ((REG32(ADR_CCCR_13H_REG)) & 0xf1ffffff))
++#define SET_FBR_100H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FBR_100H_REG)) & 0xfffffff0))
++#define SET_CSASUPPORT(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_FBR_100H_REG)) & 0xffffffbf))
++#define SET_ENABLECSA(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FBR_100H_REG)) & 0xffffff7f))
++#define SET_FBR_101H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_100H_REG)) & 0xffff00ff))
++#define SET_FBR_109H_REG(_VAL_) (REG32(ADR_FBR_109H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_109H_REG)) & 0xfe0000ff))
++#define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0x00000000))
++#define SET_SPI_MODE(_VAL_) (REG32(ADR_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_MODE)) & 0x00000000))
++#define SET_RX_QUOTA(_VAL_) (REG32(ADR_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_QUOTA)) & 0xffff0000))
++#define SET_CONDI_NUM(_VAL_) (REG32(ADR_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_CONDITION_NUMBER)) & 0xffffff00))
++#define SET_HOST_PATH(_VAL_) (REG32(ADR_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_HOST_PATH)) & 0xfffffffe))
++#define SET_TX_SEG(_VAL_) (REG32(ADR_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEG)) & 0x00000000))
++#define SET_BRST_MODE(_VAL_) (REG32(ADR_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_BURST_MODE)) & 0xfffffffe))
++#define SET_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000))
++#define SET_CSN_INTER(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
++#define SET_BACK_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000))
++#define SET_FRONT_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
++#define SET_RX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SPI_STS)) & 0xfffffffd))
++#define SET_RX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SPI_STS)) & 0xfffffffb))
++#define SET_TX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SPI_STS)) & 0xfffffff7))
++#define SET_TX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SPI_STS)) & 0xffffffef))
++#define SET_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SPI_STS)) & 0xffffffdf))
++#define SET_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SPI_STS)) & 0xffffffbf))
++#define SET_RDATA_RDY(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SPI_STS)) & 0xffffff7f))
++#define SET_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SPI_STS)) & 0xfffffeff))
++#define SET_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SPI_STS)) & 0xfffffdff))
++#define SET_RX_LEN(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_STS)) & 0x0000ffff))
++#define SET_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffff8))
++#define SET_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffeff))
++#define SET_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC)) & 0xffffff00))
++#define SET_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT)) & 0xffff0000))
++#define SET_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT)) & 0x0000ffff))
++#define SET_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT2)) & 0xffff0000))
++#define SET_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT2)) & 0xfffeffff))
++#define SET_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT2)) & 0xfffdffff))
++#define SET_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT2)) & 0xfffbffff))
++#define SET_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT3)) & 0xffff0000))
++#define SET_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT3)) & 0x0000ffff))
++#define SET_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT4)) & 0xffff0000))
++#define SET_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT4)) & 0xfffeffff))
++#define SET_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT4)) & 0xfffdffff))
++#define SET_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT4)) & 0xfffbffff))
++#define SET_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_CNT4)) & 0xfff7ffff))
++#define SET_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_CNT4)) & 0xff8fffff))
++#define SET_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_CNT4)) & 0xf8ffffff))
++#define SET_RX_RDY(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_TAG)) & 0xfffffffe))
++#define SET_SDIO_SYS_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_TAG)) & 0xfffffffb))
++#define SET_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_TAG)) & 0xfffffff7))
++#define SET_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_TAG)) & 0xffffffef))
++#define SET_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_TAG)) & 0xffffffdf))
++#define SET_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_TAG)) & 0xffffffbf))
++#define SET_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_TAG)) & 0xffffff7f))
++#define SET_SPI_FN1(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_TAG)) & 0xffff80ff))
++#define SET_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_INT_TAG)) & 0xffff7fff))
++#define SET_SPI_HOST_MASK(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_INT_TAG)) & 0xff00ffff))
++#define SET_I2CM_INT_WDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN)) & 0xfffffffe))
++#define SET_I2CM_INT_RDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 1) | ((REG32(ADR_I2CM_EN)) & 0xfffffffd))
++#define SET_I2CM_IDLE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 2) | ((REG32(ADR_I2CM_EN)) & 0xfffffffb))
++#define SET_I2CM_INT_MISMATCH(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 3) | ((REG32(ADR_I2CM_EN)) & 0xfffffff7))
++#define SET_I2CM_PSCL(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 4) | ((REG32(ADR_I2CM_EN)) & 0xffffc00f))
++#define SET_I2CM_MANUAL_MODE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN)) & 0xfffeffff))
++#define SET_I2CM_INT_WDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN)) & 0xfffdffff))
++#define SET_I2CM_INT_RDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 18) | ((REG32(ADR_I2CM_EN)) & 0xfffbffff))
++#define SET_I2CM_DEV_A(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_DEV_A)) & 0xfffffc00))
++#define SET_I2CM_DEV_A10B(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 14) | ((REG32(ADR_I2CM_DEV_A)) & 0xffffbfff))
++#define SET_I2CM_RX(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 15) | ((REG32(ADR_I2CM_DEV_A)) & 0xffff7fff))
++#define SET_I2CM_LEN(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_LEN)) & 0xffff0000))
++#define SET_I2CM_T_LEFT(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_LEN)) & 0xfff8ffff))
++#define SET_I2CM_R_GET(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 24) | ((REG32(ADR_I2CM_LEN)) & 0xf8ffffff))
++#define SET_I2CM_WDAT(_VAL_) (REG32(ADR_I2CM_WDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_WDAT)) & 0x00000000))
++#define SET_I2CM_RDAT(_VAL_) (REG32(ADR_I2CM_RDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_RDAT)) & 0x00000000))
++#define SET_I2CM_SR_LEN(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN_2)) & 0xffff0000))
++#define SET_I2CM_SR_RX(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN_2)) & 0xfffeffff))
++#define SET_I2CM_REPEAT_START(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN_2)) & 0xfffdffff))
++#define SET_UART_DATA(_VAL_) (REG32(ADR_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_UART_DATA)) & 0xffffff00))
++#define SET_DATA_RDY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_UART_IER)) & 0xfffffffe))
++#define SET_THR_EMPTY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_UART_IER)) & 0xfffffffd))
++#define SET_RX_LINESTS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_UART_IER)) & 0xfffffffb))
++#define SET_MDM_STS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_UART_IER)) & 0xfffffff7))
++#define SET_DMA_RXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_UART_IER)) & 0xffffffbf))
++#define SET_DMA_TXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_UART_IER)) & 0xffffff7f))
++#define SET_FIFO_EN(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_FCR)) & 0xfffffffe))
++#define SET_RXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_FCR)) & 0xfffffffd))
++#define SET_TXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_FCR)) & 0xfffffffb))
++#define SET_DMA_MODE(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_FCR)) & 0xfffffff7))
++#define SET_EN_AUTO_RTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_FCR)) & 0xffffffef))
++#define SET_EN_AUTO_CTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_FCR)) & 0xffffffdf))
++#define SET_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_FCR)) & 0xffffff3f))
++#define SET_WORD_LEN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LCR)) & 0xfffffffc))
++#define SET_STOP_BIT(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LCR)) & 0xfffffffb))
++#define SET_PARITY_EN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LCR)) & 0xfffffff7))
++#define SET_EVEN_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LCR)) & 0xffffffef))
++#define SET_FORCE_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LCR)) & 0xffffffdf))
++#define SET_SET_BREAK(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LCR)) & 0xffffffbf))
++#define SET_DLAB(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LCR)) & 0xffffff7f))
++#define SET_DTR(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MCR)) & 0xfffffffe))
++#define SET_RTS(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MCR)) & 0xfffffffd))
++#define SET_OUT_1(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MCR)) & 0xfffffffb))
++#define SET_OUT_2(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MCR)) & 0xfffffff7))
++#define SET_LOOP_BACK(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MCR)) & 0xffffffef))
++#define SET_DATA_RDY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LSR)) & 0xfffffffe))
++#define SET_OVERRUN_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_LSR)) & 0xfffffffd))
++#define SET_PARITY_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LSR)) & 0xfffffffb))
++#define SET_FRAMING_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LSR)) & 0xfffffff7))
++#define SET_BREAK_INT(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LSR)) & 0xffffffef))
++#define SET_THR_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LSR)) & 0xffffffdf))
++#define SET_TX_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LSR)) & 0xffffffbf))
++#define SET_FIFODATA_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LSR)) & 0xffffff7f))
++#define SET_DELTA_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MSR)) & 0xfffffffe))
++#define SET_DELTA_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MSR)) & 0xfffffffd))
++#define SET_TRAILEDGE_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MSR)) & 0xfffffffb))
++#define SET_DELTA_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MSR)) & 0xfffffff7))
++#define SET_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MSR)) & 0xffffffef))
++#define SET_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_MSR)) & 0xffffffdf))
++#define SET_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_MSR)) & 0xffffffbf))
++#define SET_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_MSR)) & 0xffffff7f))
++#define SET_BRDC_DIV(_VAL_) (REG32(ADR_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_SPR)) & 0xffff0000))
++#define SET_RTHR_L(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_RTHR)) & 0xfffffff0))
++#define SET_RTHR_H(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_RTHR)) & 0xffffff0f))
++#define SET_INT_IDCODE(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_ISR)) & 0xfffffff0))
++#define SET_FIFOS_ENABLED(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_ISR)) & 0xffffff3f))
++#define SET_DAT_UART_DATA(_VAL_) (REG32(ADR_DAT_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_DATA)) & 0xffffff00))
++#define SET_DAT_DATA_RDY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffe))
++#define SET_DAT_THR_EMPTY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffd))
++#define SET_DAT_RX_LINESTS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffb))
++#define SET_DAT_MDM_STS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffff7))
++#define SET_DAT_DMA_RXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_IER)) & 0xffffffbf))
++#define SET_DAT_DMA_TXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_IER)) & 0xffffff7f))
++#define SET_DAT_FIFO_EN(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffe))
++#define SET_DAT_RXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffd))
++#define SET_DAT_TXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffb))
++#define SET_DAT_DMA_MODE(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffff7))
++#define SET_DAT_EN_AUTO_RTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffef))
++#define SET_DAT_EN_AUTO_CTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffdf))
++#define SET_DAT_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffff3f))
++#define SET_DAT_WORD_LEN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffc))
++#define SET_DAT_STOP_BIT(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffb))
++#define SET_DAT_PARITY_EN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffff7))
++#define SET_DAT_EVEN_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffef))
++#define SET_DAT_FORCE_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffdf))
++#define SET_DAT_SET_BREAK(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffbf))
++#define SET_DAT_DLAB(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffff7f))
++#define SET_DAT_DTR(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffe))
++#define SET_DAT_RTS(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffd))
++#define SET_DAT_OUT_1(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffb))
++#define SET_DAT_OUT_2(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffff7))
++#define SET_DAT_LOOP_BACK(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MCR)) & 0xffffffef))
++#define SET_DAT_DATA_RDY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffe))
++#define SET_DAT_OVERRUN_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffd))
++#define SET_DAT_PARITY_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffb))
++#define SET_DAT_FRAMING_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffff7))
++#define SET_DAT_BREAK_INT(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffef))
++#define SET_DAT_THR_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffdf))
++#define SET_DAT_TX_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffbf))
++#define SET_DAT_FIFODATA_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffff7f))
++#define SET_DAT_DELTA_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffe))
++#define SET_DAT_DELTA_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffd))
++#define SET_DAT_TRAILEDGE_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffb))
++#define SET_DAT_DELTA_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffff7))
++#define SET_DAT_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffef))
++#define SET_DAT_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffdf))
++#define SET_DAT_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffbf))
++#define SET_DAT_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffff7f))
++#define SET_DAT_BRDC_DIV(_VAL_) (REG32(ADR_DAT_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_SPR)) & 0xffff0000))
++#define SET_DAT_RTHR_L(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_RTHR)) & 0xfffffff0))
++#define SET_DAT_RTHR_H(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_RTHR)) & 0xffffff0f))
++#define SET_DAT_INT_IDCODE(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_ISR)) & 0xfffffff0))
++#define SET_DAT_FIFOS_ENABLED(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_ISR)) & 0xffffff3f))
++#define SET_MASK_TOP(_VAL_) (REG32(ADR_INT_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK)) & 0x00000000))
++#define SET_INT_MODE(_VAL_) (REG32(ADR_INT_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MODE)) & 0x00000000))
++#define SET_IRQ_PHY_0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffe))
++#define SET_IRQ_PHY_1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffd))
++#define SET_IRQ_SDIO(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffb))
++#define SET_IRQ_BEACON_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffff7))
++#define SET_IRQ_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffef))
++#define SET_IRQ_PRE_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffdf))
++#define SET_IRQ_EDCA0_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffbf))
++#define SET_IRQ_EDCA1_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffff7f))
++#define SET_IRQ_EDCA2_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffeff))
++#define SET_IRQ_EDCA3_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffdff))
++#define SET_IRQ_EDCA4_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffbff))
++#define SET_IRQ_BEACON_DTIM(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffefff))
++#define SET_IRQ_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffdfff))
++#define SET_IRQ_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffbfff))
++#define SET_IRQ_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_IRQ_STS)) & 0xffff7fff))
++#define SET_IRQ_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffeffff))
++#define SET_IRQ_FENCE_HIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffdffff))
++#define SET_IRQ_ILL_ADDR_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffbffff))
++#define SET_IRQ_MBOX(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_IRQ_STS)) & 0xfff7ffff))
++#define SET_IRQ_US_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_IRQ_STS)) & 0xffefffff))
++#define SET_IRQ_US_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_IRQ_STS)) & 0xffdfffff))
++#define SET_IRQ_US_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_IRQ_STS)) & 0xffbfffff))
++#define SET_IRQ_US_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_IRQ_STS)) & 0xff7fffff))
++#define SET_IRQ_MS_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_IRQ_STS)) & 0xfeffffff))
++#define SET_IRQ_MS_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_IRQ_STS)) & 0xfdffffff))
++#define SET_IRQ_MS_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_IRQ_STS)) & 0xfbffffff))
++#define SET_IRQ_MS_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_IRQ_STS)) & 0xf7ffffff))
++#define SET_IRQ_TX_LIMIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_IRQ_STS)) & 0xefffffff))
++#define SET_IRQ_DMA0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_IRQ_STS)) & 0xdfffffff))
++#define SET_IRQ_CO_DMA(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_IRQ_STS)) & 0xbfffffff))
++#define SET_IRQ_PERI_GROUP(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_IRQ_STS)) & 0x7fffffff))
++#define SET_FIQ_STATUS(_VAL_) (REG32(ADR_INT_FIQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_STS)) & 0x00000000))
++#define SET_IRQ_RAW(_VAL_) (REG32(ADR_INT_IRQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_RAW)) & 0x00000000))
++#define SET_FIQ_RAW(_VAL_) (REG32(ADR_INT_FIQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_RAW)) & 0x00000000))
++#define SET_INT_PERI_MASK(_VAL_) (REG32(ADR_INT_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_MASK)) & 0x00000000))
++#define SET_PERI_RTC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffe))
++#define SET_IRQ_UART0_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffd))
++#define SET_IRQ_UART0_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffb))
++#define SET_PERI_GPI_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffff7))
++#define SET_IRQ_SPI_IPC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_PERI_STS)) & 0xffffffef))
++#define SET_PERI_GPI_1_0(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff9f))
++#define SET_SCRT_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff7f))
++#define SET_MMU_ALC_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffeff))
++#define SET_MMU_RLS_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffdff))
++#define SET_ID_MNG_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffbff))
++#define SET_MBOX_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_INT_PERI_STS)) & 0xfffff7ff))
++#define SET_MBOX_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_PERI_STS)) & 0xffffefff))
++#define SET_MBOX_INT_3(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_PERI_STS)) & 0xffffdfff))
++#define SET_HCI_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_PERI_STS)) & 0xffffbfff))
++#define SET_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_PERI_STS)) & 0xffff7fff))
++#define SET_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_PERI_STS)) & 0xfffeffff))
++#define SET_ID_MNG_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_PERI_STS)) & 0xfffdffff))
++#define SET_DMN_NOHIT_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_PERI_STS)) & 0xfffbffff))
++#define SET_ID_THOLD_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_PERI_STS)) & 0xfff7ffff))
++#define SET_ID_THOLD_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_PERI_STS)) & 0xffefffff))
++#define SET_ID_DOUBLE_RLS(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_PERI_STS)) & 0xffdfffff))
++#define SET_RX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_PERI_STS)) & 0xffbfffff))
++#define SET_TX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_PERI_STS)) & 0xff7fffff))
++#define SET_ALL_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_PERI_STS)) & 0xfeffffff))
++#define SET_DMN_MCU_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_PERI_STS)) & 0xfdffffff))
++#define SET_IRQ_DAT_UART_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_PERI_STS)) & 0xfbffffff))
++#define SET_IRQ_DAT_UART_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_PERI_STS)) & 0xf7ffffff))
++#define SET_DAT_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_PERI_STS)) & 0xefffffff))
++#define SET_DAT_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_PERI_STS)) & 0xdfffffff))
++#define SET_ALR_ABT_NOCHG_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_PERI_STS)) & 0xbfffffff))
++#define SET_TBLNEQ_MNGPKT_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_PERI_STS)) & 0x7fffffff))
++#define SET_INTR_PERI_RAW(_VAL_) (REG32(ADR_INT_PERI_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_RAW)) & 0x00000000))
++#define SET_INTR_GPI00_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffffc))
++#define SET_INTR_GPI01_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffff3))
++#define SET_SYS_RST_INT(_VAL_) (REG32(ADR_SYS_INT_FOR_HOST)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_INT_FOR_HOST)) & 0xfffffffe))
++#define SET_SPI_IPC_ADDR(_VAL_) (REG32(ADR_SPI_IPC)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_IPC)) & 0x00000000))
++#define SET_SD_MASK_TOP(_VAL_) (REG32(ADR_SDIO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_MASK)) & 0x00000000))
++#define SET_IRQ_PHY_0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffe))
++#define SET_IRQ_PHY_1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffd))
++#define SET_IRQ_SDIO_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffb))
++#define SET_IRQ_BEACON_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffff7))
++#define SET_IRQ_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffef))
++#define SET_IRQ_PRE_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffdf))
++#define SET_IRQ_EDCA0_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffbf))
++#define SET_IRQ_EDCA1_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffff7f))
++#define SET_IRQ_EDCA2_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffeff))
++#define SET_IRQ_EDCA3_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffdff))
++#define SET_IRQ_EDCA4_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffbff))
++#define SET_IRQ_BEACON_DTIM_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffefff))
++#define SET_IRQ_EDCA0_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffdfff))
++#define SET_IRQ_EDCA1_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffbfff))
++#define SET_IRQ_EDCA2_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffff7fff))
++#define SET_IRQ_EDCA3_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffeffff))
++#define SET_IRQ_FENCE_HIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffdffff))
++#define SET_IRQ_ILL_ADDR_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffbffff))
++#define SET_IRQ_MBOX_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfff7ffff))
++#define SET_IRQ_US_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffefffff))
++#define SET_IRQ_US_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffdfffff))
++#define SET_IRQ_US_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffbfffff))
++#define SET_IRQ_US_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xff7fffff))
++#define SET_IRQ_MS_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfeffffff))
++#define SET_IRQ_MS_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfdffffff))
++#define SET_IRQ_MS_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfbffffff))
++#define SET_IRQ_MS_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xf7ffffff))
++#define SET_IRQ_TX_LIMIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xefffffff))
++#define SET_IRQ_DMA0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xdfffffff))
++#define SET_IRQ_CO_DMA_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xbfffffff))
++#define SET_IRQ_PERI_GROUP_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SDIO_IRQ_STS)) & 0x7fffffff))
++#define SET_INT_PERI_MASK_SD(_VAL_) (REG32(ADR_SD_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_MASK)) & 0x00000000))
++#define SET_PERI_RTC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffe))
++#define SET_IRQ_UART0_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffd))
++#define SET_IRQ_UART0_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffb))
++#define SET_PERI_GPI_SD_2(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffff7))
++#define SET_IRQ_SPI_IPC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SD_PERI_STS)) & 0xffffffef))
++#define SET_PERI_GPI_SD_1_0(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff9f))
++#define SET_SCRT_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff7f))
++#define SET_MMU_ALC_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffeff))
++#define SET_MMU_RLS_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffdff))
++#define SET_ID_MNG_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffbff))
++#define SET_MBOX_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_SD_PERI_STS)) & 0xfffff7ff))
++#define SET_MBOX_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SD_PERI_STS)) & 0xffffefff))
++#define SET_MBOX_INT_3_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SD_PERI_STS)) & 0xffffdfff))
++#define SET_HCI_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SD_PERI_STS)) & 0xffffbfff))
++#define SET_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SD_PERI_STS)) & 0xffff7fff))
++#define SET_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SD_PERI_STS)) & 0xfffeffff))
++#define SET_ID_MNG_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SD_PERI_STS)) & 0xfffdffff))
++#define SET_DMN_NOHIT_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SD_PERI_STS)) & 0xfffbffff))
++#define SET_ID_THOLD_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SD_PERI_STS)) & 0xfff7ffff))
++#define SET_ID_THOLD_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SD_PERI_STS)) & 0xffefffff))
++#define SET_ID_DOUBLE_RLS_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SD_PERI_STS)) & 0xffdfffff))
++#define SET_RX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SD_PERI_STS)) & 0xffbfffff))
++#define SET_TX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SD_PERI_STS)) & 0xff7fffff))
++#define SET_ALL_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SD_PERI_STS)) & 0xfeffffff))
++#define SET_DMN_MCU_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SD_PERI_STS)) & 0xfdffffff))
++#define SET_IRQ_DAT_UART_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SD_PERI_STS)) & 0xfbffffff))
++#define SET_IRQ_DAT_UART_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SD_PERI_STS)) & 0xf7ffffff))
++#define SET_DAT_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SD_PERI_STS)) & 0xefffffff))
++#define SET_DAT_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SD_PERI_STS)) & 0xdfffffff))
++#define SET_ALR_ABT_NOCHG_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SD_PERI_STS)) & 0xbfffffff))
++#define SET_TBLNEQ_MNGPKT_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SD_PERI_STS)) & 0x7fffffff))
++#define SET_DBG_SPI_MODE(_VAL_) (REG32(ADR_DBG_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_MODE)) & 0x00000000))
++#define SET_DBG_RX_QUOTA(_VAL_) (REG32(ADR_DBG_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_RX_QUOTA)) & 0xffff0000))
++#define SET_DBG_CONDI_NUM(_VAL_) (REG32(ADR_DBG_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CONDITION_NUMBER)) & 0xffffff00))
++#define SET_DBG_HOST_PATH(_VAL_) (REG32(ADR_DBG_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_HOST_PATH)) & 0xfffffffe))
++#define SET_DBG_TX_SEG(_VAL_) (REG32(ADR_DBG_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_SEG)) & 0x00000000))
++#define SET_DBG_BRST_MODE(_VAL_) (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0xfffffffe))
++#define SET_DBG_CLK_WIDTH(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000))
++#define SET_DBG_CSN_INTER(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
++#define SET_DBG_BACK_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000))
++#define SET_DBG_FRONT_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
++#define SET_DBG_RX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffd))
++#define SET_DBG_RX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffb))
++#define SET_DBG_TX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffff7))
++#define SET_DBG_TX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffef))
++#define SET_DBG_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffdf))
++#define SET_DBG_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffbf))
++#define SET_DBG_RDATA_RDY(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffff7f))
++#define SET_DBG_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffeff))
++#define SET_DBG_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffdff))
++#define SET_DBG_RX_LEN(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_STS)) & 0x0000ffff))
++#define SET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffff8))
++#define SET_DBG_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffeff))
++#define SET_DBG_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_DBG_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC)) & 0xffffff00))
++#define SET_DBG_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000))
++#define SET_DBG_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff))
++#define SET_DBG_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xffff0000))
++#define SET_DBG_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffeffff))
++#define SET_DBG_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffdffff))
++#define SET_DBG_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffbffff))
++#define SET_DBG_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000))
++#define SET_DBG_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff))
++#define SET_DBG_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xffff0000))
++#define SET_DBG_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffeffff))
++#define SET_DBG_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffdffff))
++#define SET_DBG_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffbffff))
++#define SET_DBG_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfff7ffff))
++#define SET_DBG_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xff8fffff))
++#define SET_DBG_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xf8ffffff))
++#define SET_DBG_RX_RDY(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffe))
++#define SET_DBG_SDIO_SYS_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffb))
++#define SET_DBG_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffff7))
++#define SET_DBG_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffef))
++#define SET_DBG_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffdf))
++#define SET_DBG_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffbf))
++#define SET_DBG_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffff7f))
++#define SET_DBG_SPI_FN1(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff80ff))
++#define SET_DBG_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff7fff))
++#define SET_DBG_SPI_HOST_MASK(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_INT_TAG)) & 0xff00ffff))
++#define SET_BOOT_ADDR(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_ADDR)) & 0xff000000))
++#define SET_CHECK_SUM_FAIL(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_BOOT_ADDR)) & 0x7fffffff))
++#define SET_VERIFY_DATA(_VAL_) (REG32(ADR_VERIFY_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_VERIFY_DATA)) & 0x00000000))
++#define SET_FLASH_ADDR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_FLASH_ADDR)) & 0xff000000))
++#define SET_FLASH_CMD_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 28) | ((REG32(ADR_FLASH_ADDR)) & 0xefffffff))
++#define SET_FLASH_DMA_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 29) | ((REG32(ADR_FLASH_ADDR)) & 0xdfffffff))
++#define SET_DMA_EN(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 30) | ((REG32(ADR_FLASH_ADDR)) & 0xbfffffff))
++#define SET_DMA_BUSY(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_FLASH_ADDR)) & 0x7fffffff))
++#define SET_SRAM_ADDR(_VAL_) (REG32(ADR_SRAM_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SRAM_ADDR)) & 0x00000000))
++#define SET_FLASH_DMA_LEN(_VAL_) (REG32(ADR_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_LEN)) & 0x00000000))
++#define SET_FLASH_FRONT_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM)) & 0xffff0000))
++#define SET_FLASH_BACK_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM)) & 0x0000ffff))
++#define SET_FLASH_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM2)) & 0xffff0000))
++#define SET_SPI_BUSY(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM2)) & 0xfffeffff))
++#define SET_FLS_REMAP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 17) | ((REG32(ADR_SPI_PARAM2)) & 0xfffdffff))
++#define SET_PBUS_SWP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 18) | ((REG32(ADR_SPI_PARAM2)) & 0xfffbffff))
++#define SET_BIT_MODE1(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 19) | ((REG32(ADR_SPI_PARAM2)) & 0xfff7ffff))
++#define SET_BIT_MODE2(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 20) | ((REG32(ADR_SPI_PARAM2)) & 0xffefffff))
++#define SET_BIT_MODE4(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 21) | ((REG32(ADR_SPI_PARAM2)) & 0xffdfffff))
++#define SET_BOOT_CHECK_SUM(_VAL_) (REG32(ADR_CHECK_SUM_RESULT)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_RESULT)) & 0x00000000))
++#define SET_CHECK_SUM_TAG(_VAL_) (REG32(ADR_CHECK_SUM_IN_FILE)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_IN_FILE)) & 0x00000000))
++#define SET_CMD_LEN(_VAL_) (REG32(ADR_COMMAND_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_LEN)) & 0xffff0000))
++#define SET_CMD_ADDR(_VAL_) (REG32(ADR_COMMAND_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_ADDR)) & 0x00000000))
++#define SET_DMA_ADR_SRC(_VAL_) (REG32(ADR_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_SRC)) & 0x00000000))
++#define SET_DMA_ADR_DST(_VAL_) (REG32(ADR_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_DST)) & 0x00000000))
++#define SET_DMA_SRC_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff8))
++#define SET_DMA_SRC_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff7))
++#define SET_DMA_DST_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_DMA_CTRL)) & 0xffffff8f))
++#define SET_DMA_DST_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_DMA_CTRL)) & 0xffffff7f))
++#define SET_DMA_FAST_FILL(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_CTRL)) & 0xfffffeff))
++#define SET_DMA_SDIO_KICK(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_DMA_CTRL)) & 0xffffefff))
++#define SET_DMA_BADR_EN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_DMA_CTRL)) & 0xffffdfff))
++#define SET_DMA_LEN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_CTRL)) & 0x0000ffff))
++#define SET_DMA_INT_MASK(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_INT)) & 0xfffffffe))
++#define SET_DMA_STS(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_INT)) & 0xfffffeff))
++#define SET_DMA_FINISH(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_DMA_INT)) & 0x7fffffff))
++#define SET_DMA_CONST(_VAL_) (REG32(ADR_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_FILL_CONST)) & 0x00000000))
++#define SET_SLEEP_WAKE_CNT(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_0)) & 0xff000000))
++#define SET_RG_DLDO_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 24) | ((REG32(ADR_PMU_0)) & 0xf8ffffff))
++#define SET_RG_DLDO_BOOST_IQ(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 27) | ((REG32(ADR_PMU_0)) & 0xf7ffffff))
++#define SET_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 28) | ((REG32(ADR_PMU_0)) & 0x8fffffff))
++#define SET_RG_BUCK_VREF_SEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_0)) & 0x7fffffff))
++#define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_1)) & 0xfffffc00))
++#define SET_RG_RTC_OSC_RES_SW(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_1)) & 0xfc00ffff))
++#define SET_RTC_OSC_CAL_RES_RDY(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_1)) & 0x7fffffff))
++#define SET_RG_DCDC_MODE(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_2)) & 0xfffffffe))
++#define SET_RG_BUCK_EN_PSM(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_2)) & 0xffffffef))
++#define SET_RG_BUCK_PSM_VTH(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_2)) & 0xfffffeff))
++#define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 12) | ((REG32(ADR_PMU_2)) & 0xffffefff))
++#define SET_RG_RTC_RDY_DEGLITCH_TIMER(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 13) | ((REG32(ADR_PMU_2)) & 0xffff9fff))
++#define SET_RTC_CAL_ENA(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_2)) & 0xfffeffff))
++#define SET_PMU_WAKE_TRIG_EVENT(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_3)) & 0xfffffffc))
++#define SET_DIGI_TOP_POR_MASK(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_3)) & 0xffffffef))
++#define SET_PMU_ENTER_SLEEP_MODE(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_3)) & 0xfffffeff))
++#define SET_RG_RTC_DUMMIES(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_3)) & 0x0000ffff))
++#define SET_RTC_EN(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_1)) & 0xfffffffe))
++#define SET_RTC_SRC(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_1)) & 0xfffffffd))
++#define SET_RTC_TICK_CNT(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_1)) & 0x8000ffff))
++#define SET_RTC_INT_SEC_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_2)) & 0xfffffffe))
++#define SET_RTC_INT_ALARM_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_2)) & 0xfffffffd))
++#define SET_RTC_INT_SEC(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_2)) & 0xfffeffff))
++#define SET_RTC_INT_ALARM(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 17) | ((REG32(ADR_RTC_2)) & 0xfffdffff))
++#define SET_RTC_SEC_START_CNT(_VAL_) (REG32(ADR_RTC_3W)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3W)) & 0x00000000))
++#define SET_RTC_SEC_CNT(_VAL_) (REG32(ADR_RTC_3R)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3R)) & 0x00000000))
++#define SET_RTC_SEC_ALARM_VALUE(_VAL_) (REG32(ADR_RTC_4)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_4)) & 0x00000000))
++#define SET_D2_DMA_ADR_SRC(_VAL_) (REG32(ADR_D2_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_SRC)) & 0x00000000))
++#define SET_D2_DMA_ADR_DST(_VAL_) (REG32(ADR_D2_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_DST)) & 0x00000000))
++#define SET_D2_DMA_SRC_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff8))
++#define SET_D2_DMA_SRC_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff7))
++#define SET_D2_DMA_DST_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff8f))
++#define SET_D2_DMA_DST_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff7f))
++#define SET_D2_DMA_FAST_FILL(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffeff))
++#define SET_D2_DMA_SDIO_KICK(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffefff))
++#define SET_D2_DMA_BADR_EN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffdfff))
++#define SET_D2_DMA_LEN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_D2_DMA_CTRL)) & 0x0000ffff))
++#define SET_D2_DMA_INT_MASK(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffffe))
++#define SET_D2_DMA_STS(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffeff))
++#define SET_D2_DMA_FINISH(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_D2_DMA_INT)) & 0x7fffffff))
++#define SET_D2_DMA_CONST(_VAL_) (REG32(ADR_D2_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_FILL_CONST)) & 0x00000000))
++#define SET_TRAP_UNKNOWN_TYPE(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_CONTROL)) & 0xfffffffe))
++#define SET_TX_ON_DEMAND_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_CONTROL)) & 0xfffffffd))
++#define SET_RX_2_HOST(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_CONTROL)) & 0xfffffffb))
++#define SET_AUTO_SEQNO(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 3) | ((REG32(ADR_CONTROL)) & 0xfffffff7))
++#define SET_BYPASSS_TX_PARSER_ENCAP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 4) | ((REG32(ADR_CONTROL)) & 0xffffffef))
++#define SET_HDR_STRIP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 5) | ((REG32(ADR_CONTROL)) & 0xffffffdf))
++#define SET_ERP_PROTECT(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 6) | ((REG32(ADR_CONTROL)) & 0xffffff3f))
++#define SET_PRO_VER(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_CONTROL)) & 0xfffffcff))
++#define SET_TXQ_ID0(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 12) | ((REG32(ADR_CONTROL)) & 0xffff8fff))
++#define SET_TXQ_ID1(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_CONTROL)) & 0xfff8ffff))
++#define SET_TX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 20) | ((REG32(ADR_CONTROL)) & 0xffefffff))
++#define SET_RX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 21) | ((REG32(ADR_CONTROL)) & 0xffdfffff))
++#define SET_RX_NULL_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 22) | ((REG32(ADR_CONTROL)) & 0xffbfffff))
++#define SET_RX_GET_TX_QUEUE_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 25) | ((REG32(ADR_CONTROL)) & 0xfdffffff))
++#define SET_HCI_INQ_SEL(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 26) | ((REG32(ADR_CONTROL)) & 0xfbffffff))
++#define SET_TRX_DEBUG_CNT_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 28) | ((REG32(ADR_CONTROL)) & 0xefffffff))
++#define SET_WAKE_SOON_WITH_SCK(_VAL_) (REG32(ADR_SDIO_WAKE_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_WAKE_MODE)) & 0xfffffffe))
++#define SET_TX_FLOW_CTRL(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_0)) & 0xffff0000))
++#define SET_TX_FLOW_MGMT(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FLOW_0)) & 0x0000ffff))
++#define SET_TX_FLOW_DATA(_VAL_) (REG32(ADR_TX_FLOW_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_1)) & 0x00000000))
++#define SET_DOT11RTSTHRESHOLD(_VAL_) (REG32(ADR_THREASHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_THREASHOLD)) & 0x0000ffff))
++#define SET_TXF_ID(_VAL_) (REG32(ADR_TXFID_INCREASE)) = (((_VAL_) << 0) | ((REG32(ADR_TXFID_INCREASE)) & 0xffffffc0))
++#define SET_SEQ_CTRL(_VAL_) (REG32(ADR_GLOBAL_SEQUENCE)) = (((_VAL_) << 0) | ((REG32(ADR_GLOBAL_SEQUENCE)) & 0xffff0000))
++#define SET_TX_PBOFFSET(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffffff00))
++#define SET_TX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffff00ff))
++#define SET_RX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff00ffff))
++#define SET_RX_LAST_PHY_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ffffff))
++#define SET_TX_INFO_CLEAR_SIZE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xffffffc0))
++#define SET_TX_INFO_CLEAR_ENABLE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xfffffeff))
++#define SET_TXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000))
++#define SET_TXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff))
++#define SET_RXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000))
++#define SET_RXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff))
++#define SET_TX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_0)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0x00000000))
++#define SET_RX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_1)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0x00000000))
++#define SET_HOST_CMD_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_2)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0xffffff00))
++#define SET_HOST_EVENT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_3)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0xffffff00))
++#define SET_TX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_4)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0xffffff00))
++#define SET_RX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_5)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0xffffff00))
++#define SET_TX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_6)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0xffffff00))
++#define SET_RX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_7)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0xffffff00))
++#define SET_HOST_TX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0xffffff00))
++#define SET_HOST_RX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0xffffff00))
++#define SET_HCI_STATE_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0x00000000))
++#define SET_HCI_ST_TIMEOUT_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0x00000000))
++#define SET_TX_ON_DEMAND_LENGTH(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0x00000000))
++#define SET_HCI_MONITOR_REG1(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0x00000000))
++#define SET_HCI_MONITOR_REG2(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0x00000000))
++#define SET_HCI_TX_ALLOC_TIME_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0x00000000))
++#define SET_HCI_TX_ALLOC_TIME_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffff0000))
++#define SET_HCI_MB_MAX_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xff00ffff))
++#define SET_HCI_TX_ALLOC_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00000000))
++#define SET_HCI_TX_ALLOC_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xffff0000))
++#define SET_HCI_PROC_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff00ffff))
++#define SET_SDIO_TRANS_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ffffff))
++#define SET_SDIO_TX_INVALID_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0x00000000))
++#define SET_SDIO_TX_INVALID_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0xffff0000))
++#define SET_CS_START_ADDR(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_CS_START_ADDR)) & 0xffff0000))
++#define SET_CS_PKT_ID(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 16) | ((REG32(ADR_CS_START_ADDR)) & 0xff80ffff))
++#define SET_ADD_LEN(_VAL_) (REG32(ADR_CS_ADD_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_CS_ADD_LEN)) & 0xffff0000))
++#define SET_CS_ADDER_EN(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CMD)) & 0xfffffffe))
++#define SET_PSEUDO(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 1) | ((REG32(ADR_CS_CMD)) & 0xfffffffd))
++#define SET_CALCULATE(_VAL_) (REG32(ADR_CS_INI_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_INI_BUF)) & 0x00000000))
++#define SET_L4_LEN(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xffff0000))
++#define SET_L4_PROTOL(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 16) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xff00ffff))
++#define SET_CHECK_SUM(_VAL_) (REG32(ADR_CS_CHECK_SUM)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CHECK_SUM)) & 0xffff0000))
++#define SET_RAND_EN(_VAL_) (REG32(ADR_RAND_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_EN)) & 0xfffffffe))
++#define SET_RAND_NUM(_VAL_) (REG32(ADR_RAND_NUM)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_NUM)) & 0x00000000))
++#define SET_MUL_OP1(_VAL_) (REG32(ADR_MUL_OP1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP1)) & 0x00000000))
++#define SET_MUL_OP2(_VAL_) (REG32(ADR_MUL_OP2)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP2)) & 0x00000000))
++#define SET_MUL_ANS0(_VAL_) (REG32(ADR_MUL_ANS0)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS0)) & 0x00000000))
++#define SET_MUL_ANS1(_VAL_) (REG32(ADR_MUL_ANS1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS1)) & 0x00000000))
++#define SET_RD_ADDR(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_RDATA)) & 0xffff0000))
++#define SET_RD_ID(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_RDATA)) & 0xff80ffff))
++#define SET_WR_ADDR(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_WDATA)) & 0xffff0000))
++#define SET_WR_ID(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_WDATA)) & 0xff80ffff))
++#define SET_LEN(_VAL_) (REG32(ADR_DMA_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_LEN)) & 0xffff0000))
++#define SET_CLR(_VAL_) (REG32(ADR_DMA_CLR)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CLR)) & 0xfffffffe))
++#define SET_PHY_MODE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_NAV_DATA)) & 0xfffffffc))
++#define SET_SHRT_PREAM(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 2) | ((REG32(ADR_NAV_DATA)) & 0xfffffffb))
++#define SET_SHRT_GI(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 3) | ((REG32(ADR_NAV_DATA)) & 0xfffffff7))
++#define SET_DATA_RATE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 4) | ((REG32(ADR_NAV_DATA)) & 0xfffff80f))
++#define SET_MCS(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 12) | ((REG32(ADR_NAV_DATA)) & 0xffff8fff))
++#define SET_FRAME_LEN(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 16) | ((REG32(ADR_NAV_DATA)) & 0x0000ffff))
++#define SET_DURATION(_VAL_) (REG32(ADR_CO_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_CO_NAV)) & 0xffff0000))
++#define SET_SHA_DST_ADDR(_VAL_) (REG32(ADR_SHA_DST_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_DST_ADDR)) & 0x00000000))
++#define SET_SHA_SRC_ADDR(_VAL_) (REG32(ADR_SHA_SRC_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SRC_ADDR)) & 0x00000000))
++#define SET_SHA_BUSY(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffe))
++#define SET_SHA_ENDIAN(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 1) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffd))
++#define SET_EFS_CLKFREQ(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffff000))
++#define SET_LOW_ACTIVE(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffeffff))
++#define SET_EFS_CLKFREQ_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 20) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf00fffff))
++#define SET_EFS_PRE_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 28) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0fffffff))
++#define SET_EFS_LDO_ON(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000))
++#define SET_EFS_LDO_OFF(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff))
++#define SET_EFS_RDATA_0(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0x00000000))
++#define SET_EFS_WDATA_0(_VAL_) (REG32(ADR_EFUSE_WDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_0)) & 0x00000000))
++#define SET_EFS_RDATA_1(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0x00000000))
++#define SET_EFS_WDATA_1(_VAL_) (REG32(ADR_EFUSE_WDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_1)) & 0x00000000))
++#define SET_EFS_RDATA_2(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0x00000000))
++#define SET_EFS_WDATA_2(_VAL_) (REG32(ADR_EFUSE_WDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_2)) & 0x00000000))
++#define SET_EFS_RDATA_3(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0x00000000))
++#define SET_EFS_WDATA_3(_VAL_) (REG32(ADR_EFUSE_WDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_3)) & 0x00000000))
++#define SET_EFS_RDATA_4(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0x00000000))
++#define SET_EFS_WDATA_4(_VAL_) (REG32(ADR_EFUSE_WDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_4)) & 0x00000000))
++#define SET_EFS_RDATA_5(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0x00000000))
++#define SET_EFS_WDATA_5(_VAL_) (REG32(ADR_EFUSE_WDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_5)) & 0x00000000))
++#define SET_EFS_RDATA_6(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0x00000000))
++#define SET_EFS_WDATA_6(_VAL_) (REG32(ADR_EFUSE_WDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_6)) & 0x00000000))
++#define SET_EFS_RDATA_7(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0x00000000))
++#define SET_EFS_WDATA_7(_VAL_) (REG32(ADR_EFUSE_WDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_7)) & 0x00000000))
++#define SET_EFS_SPI_RD0_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD0_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD1_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD1_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD2_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD2_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD3_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD3_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD4_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD4_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD5_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD5_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD6_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD6_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD7_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD7_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RBUSY(_VAL_) (REG32(ADR_EFUSE_SPI_BUSY)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_BUSY)) & 0xfffffffe))
++#define SET_EFS_SPI_RDATA_0(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_1(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_2(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_3(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_4(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_5(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_6(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_7(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0x00000000))
++#define SET_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffe))
++#define SET_FORCE_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffd))
++#define SET_SMS4_DESCRY_EN(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG1)) & 0xffffffef))
++#define SET_DEC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffe))
++#define SET_DEC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffd))
++#define SET_ENC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffb))
++#define SET_ENC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 3) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffff7))
++#define SET_KEY_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG2)) & 0xffffffef))
++#define SET_SMS4_CBC_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffe))
++#define SET_SMS4_CFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffd))
++#define SET_SMS4_OFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffb))
++#define SET_SMS4_START_TRIG(_VAL_) (REG32(ADR_SMS4_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_TRIG)) & 0xfffffffe))
++#define SET_SMS4_BUSY(_VAL_) (REG32(ADR_SMS4_STATUS1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS1)) & 0xfffffffe))
++#define SET_SMS4_DONE(_VAL_) (REG32(ADR_SMS4_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS2)) & 0xfffffffe))
++#define SET_SMS4_DATAIN_0(_VAL_) (REG32(ADR_SMS4_DATA_IN0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN0)) & 0x00000000))
++#define SET_SMS4_DATAIN_1(_VAL_) (REG32(ADR_SMS4_DATA_IN1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN1)) & 0x00000000))
++#define SET_SMS4_DATAIN_2(_VAL_) (REG32(ADR_SMS4_DATA_IN2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN2)) & 0x00000000))
++#define SET_SMS4_DATAIN_3(_VAL_) (REG32(ADR_SMS4_DATA_IN3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN3)) & 0x00000000))
++#define SET_SMS4_DATAOUT_0(_VAL_) (REG32(ADR_SMS4_DATA_OUT0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT0)) & 0x00000000))
++#define SET_SMS4_DATAOUT_1(_VAL_) (REG32(ADR_SMS4_DATA_OUT1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT1)) & 0x00000000))
++#define SET_SMS4_DATAOUT_2(_VAL_) (REG32(ADR_SMS4_DATA_OUT2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT2)) & 0x00000000))
++#define SET_SMS4_DATAOUT_3(_VAL_) (REG32(ADR_SMS4_DATA_OUT3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT3)) & 0x00000000))
++#define SET_SMS4_KEY_0(_VAL_) (REG32(ADR_SMS4_KEY_0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_0)) & 0x00000000))
++#define SET_SMS4_KEY_1(_VAL_) (REG32(ADR_SMS4_KEY_1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_1)) & 0x00000000))
++#define SET_SMS4_KEY_2(_VAL_) (REG32(ADR_SMS4_KEY_2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_2)) & 0x00000000))
++#define SET_SMS4_KEY_3(_VAL_) (REG32(ADR_SMS4_KEY_3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_3)) & 0x00000000))
++#define SET_SMS4_MODE_IV0(_VAL_) (REG32(ADR_SMS4_MODE_IV0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV0)) & 0x00000000))
++#define SET_SMS4_MODE_IV1(_VAL_) (REG32(ADR_SMS4_MODE_IV1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV1)) & 0x00000000))
++#define SET_SMS4_MODE_IV2(_VAL_) (REG32(ADR_SMS4_MODE_IV2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV2)) & 0x00000000))
++#define SET_SMS4_MODE_IV3(_VAL_) (REG32(ADR_SMS4_MODE_IV3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV3)) & 0x00000000))
++#define SET_SMS4_OFB_ENC0(_VAL_) (REG32(ADR_SMS4_OFB_ENC0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC0)) & 0x00000000))
++#define SET_SMS4_OFB_ENC1(_VAL_) (REG32(ADR_SMS4_OFB_ENC1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC1)) & 0x00000000))
++#define SET_SMS4_OFB_ENC2(_VAL_) (REG32(ADR_SMS4_OFB_ENC2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC2)) & 0x00000000))
++#define SET_SMS4_OFB_ENC3(_VAL_) (REG32(ADR_SMS4_OFB_ENC3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC3)) & 0x00000000))
++#define SET_MRX_MCAST_TB0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_0(_VAL_) (REG32(ADR_MRX_MCAST_CTRL0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL0)) & 0xfffffffc))
++#define SET_MRX_MCAST_TB1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_1(_VAL_) (REG32(ADR_MRX_MCAST_CTRL1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL1)) & 0xfffffffc))
++#define SET_MRX_MCAST_TB2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_2(_VAL_) (REG32(ADR_MRX_MCAST_CTRL2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL2)) & 0xfffffffc))
++#define SET_MRX_MCAST_TB3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_3(_VAL_) (REG32(ADR_MRX_MCAST_CTRL3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL3)) & 0xfffffffc))
++#define SET_MRX_PHY_INFO(_VAL_) (REG32(ADR_MRX_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_PHY_INFO)) & 0x00000000))
++#define SET_DBG_BA_TYPE(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_DBG)) & 0xffffffc0))
++#define SET_DBG_BA_SEQ(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 8) | ((REG32(ADR_MRX_BA_DBG)) & 0xfff000ff))
++#define SET_MRX_FLT_TB0(_VAL_) (REG32(ADR_MRX_FLT_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB0)) & 0xffff8000))
++#define SET_MRX_FLT_TB1(_VAL_) (REG32(ADR_MRX_FLT_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB1)) & 0xffff8000))
++#define SET_MRX_FLT_TB2(_VAL_) (REG32(ADR_MRX_FLT_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB2)) & 0xffff8000))
++#define SET_MRX_FLT_TB3(_VAL_) (REG32(ADR_MRX_FLT_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB3)) & 0xffff8000))
++#define SET_MRX_FLT_TB4(_VAL_) (REG32(ADR_MRX_FLT_TB4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB4)) & 0xffff8000))
++#define SET_MRX_FLT_TB5(_VAL_) (REG32(ADR_MRX_FLT_TB5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB5)) & 0xffff8000))
++#define SET_MRX_FLT_TB6(_VAL_) (REG32(ADR_MRX_FLT_TB6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB6)) & 0xffff8000))
++#define SET_MRX_FLT_TB7(_VAL_) (REG32(ADR_MRX_FLT_TB7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB7)) & 0xffff8000))
++#define SET_MRX_FLT_TB8(_VAL_) (REG32(ADR_MRX_FLT_TB8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB8)) & 0xffff8000))
++#define SET_MRX_FLT_TB9(_VAL_) (REG32(ADR_MRX_FLT_TB9)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB9)) & 0xffff8000))
++#define SET_MRX_FLT_TB10(_VAL_) (REG32(ADR_MRX_FLT_TB10)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB10)) & 0xffff8000))
++#define SET_MRX_FLT_TB11(_VAL_) (REG32(ADR_MRX_FLT_TB11)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB11)) & 0xffff8000))
++#define SET_MRX_FLT_TB12(_VAL_) (REG32(ADR_MRX_FLT_TB12)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB12)) & 0xffff8000))
++#define SET_MRX_FLT_TB13(_VAL_) (REG32(ADR_MRX_FLT_TB13)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB13)) & 0xffff8000))
++#define SET_MRX_FLT_TB14(_VAL_) (REG32(ADR_MRX_FLT_TB14)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB14)) & 0xffff8000))
++#define SET_MRX_FLT_TB15(_VAL_) (REG32(ADR_MRX_FLT_TB15)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB15)) & 0xffff8000))
++#define SET_MRX_FLT_EN0(_VAL_) (REG32(ADR_MRX_FLT_EN0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN0)) & 0xffff0000))
++#define SET_MRX_FLT_EN1(_VAL_) (REG32(ADR_MRX_FLT_EN1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN1)) & 0xffff0000))
++#define SET_MRX_FLT_EN2(_VAL_) (REG32(ADR_MRX_FLT_EN2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN2)) & 0xffff0000))
++#define SET_MRX_FLT_EN3(_VAL_) (REG32(ADR_MRX_FLT_EN3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN3)) & 0xffff0000))
++#define SET_MRX_FLT_EN4(_VAL_) (REG32(ADR_MRX_FLT_EN4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN4)) & 0xffff0000))
++#define SET_MRX_FLT_EN5(_VAL_) (REG32(ADR_MRX_FLT_EN5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN5)) & 0xffff0000))
++#define SET_MRX_FLT_EN6(_VAL_) (REG32(ADR_MRX_FLT_EN6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN6)) & 0xffff0000))
++#define SET_MRX_FLT_EN7(_VAL_) (REG32(ADR_MRX_FLT_EN7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN7)) & 0xffff0000))
++#define SET_MRX_FLT_EN8(_VAL_) (REG32(ADR_MRX_FLT_EN8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN8)) & 0xffff0000))
++#define SET_MRX_LEN_FLT(_VAL_) (REG32(ADR_MRX_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_LEN_FLT)) & 0xffff0000))
++#define SET_RX_FLOW_DATA(_VAL_) (REG32(ADR_RX_FLOW_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_DATA)) & 0x00000000))
++#define SET_RX_FLOW_MNG(_VAL_) (REG32(ADR_RX_FLOW_MNG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_MNG)) & 0xffff0000))
++#define SET_RX_FLOW_CTRL(_VAL_) (REG32(ADR_RX_FLOW_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_CTRL)) & 0xffff0000))
++#define SET_MRX_STP_EN(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xfffffffe))
++#define SET_MRX_STP_OFST(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xffff00ff))
++#define SET_DBG_FF_FULL(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_FF_FULL)) & 0xffff0000))
++#define SET_DBG_FF_FULL_CLR(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_FF_FULL)) & 0x7fffffff))
++#define SET_DBG_WFF_FULL(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_WFF_FULL)) & 0xffff0000))
++#define SET_DBG_WFF_FULL_CLR(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_WFF_FULL)) & 0x7fffffff))
++#define SET_DBG_MB_FULL(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_MB_FULL)) & 0xffff0000))
++#define SET_DBG_MB_FULL_CLR(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_MB_FULL)) & 0x7fffffff))
++#define SET_BA_CTRL(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BA_CTRL)) & 0xfffffffc))
++#define SET_BA_DBG_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_BA_CTRL)) & 0xfffffffb))
++#define SET_BA_AGRE_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_BA_CTRL)) & 0xfffffff7))
++#define SET_BA_TA_31_0(_VAL_) (REG32(ADR_BA_TA_0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_0)) & 0x00000000))
++#define SET_BA_TA_47_32(_VAL_) (REG32(ADR_BA_TA_1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_1)) & 0xffff0000))
++#define SET_BA_TID(_VAL_) (REG32(ADR_BA_TID)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TID)) & 0xfffffff0))
++#define SET_BA_ST_SEQ(_VAL_) (REG32(ADR_BA_ST_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_BA_ST_SEQ)) & 0xfffff000))
++#define SET_BA_SB0(_VAL_) (REG32(ADR_BA_SB0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB0)) & 0x00000000))
++#define SET_BA_SB1(_VAL_) (REG32(ADR_BA_SB1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB1)) & 0x00000000))
++#define SET_MRX_WD(_VAL_) (REG32(ADR_MRX_WATCH_DOG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_WATCH_DOG)) & 0xfffe0000))
++#define SET_ACK_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffe))
++#define SET_BA_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 1) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffd))
++#define SET_ACK_GEN_DUR(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffff0000))
++#define SET_ACK_GEN_INFO(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 16) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffc0ffff))
++#define SET_ACK_GEN_RA_31_0(_VAL_) (REG32(ADR_ACK_GEN_RA_0)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_0)) & 0x00000000))
++#define SET_ACK_GEN_RA_47_32(_VAL_) (REG32(ADR_ACK_GEN_RA_1)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_1)) & 0xffff0000))
++#define SET_MIB_LEN_FAIL(_VAL_) (REG32(ADR_MIB_LEN_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_LEN_FAIL)) & 0xffff0000))
++#define SET_TRAP_HW_ID(_VAL_) (REG32(ADR_TRAP_HW_ID)) = (((_VAL_) << 0) | ((REG32(ADR_TRAP_HW_ID)) & 0xfffffff0))
++#define SET_ID_IN_USE(_VAL_) (REG32(ADR_ID_IN_USE)) = (((_VAL_) << 0) | ((REG32(ADR_ID_IN_USE)) & 0xffffff00))
++#define SET_MRX_ERR(_VAL_) (REG32(ADR_MRX_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ERR)) & 0x00000000))
++#define SET_W0_T0_SEQ(_VAL_) (REG32(ADR_WSID0_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T1_SEQ(_VAL_) (REG32(ADR_WSID0_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T2_SEQ(_VAL_) (REG32(ADR_WSID0_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T3_SEQ(_VAL_) (REG32(ADR_WSID0_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T4_SEQ(_VAL_) (REG32(ADR_WSID0_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T5_SEQ(_VAL_) (REG32(ADR_WSID0_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T6_SEQ(_VAL_) (REG32(ADR_WSID0_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T7_SEQ(_VAL_) (REG32(ADR_WSID0_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T0_SEQ(_VAL_) (REG32(ADR_WSID1_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T1_SEQ(_VAL_) (REG32(ADR_WSID1_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T2_SEQ(_VAL_) (REG32(ADR_WSID1_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T3_SEQ(_VAL_) (REG32(ADR_WSID1_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T4_SEQ(_VAL_) (REG32(ADR_WSID1_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T5_SEQ(_VAL_) (REG32(ADR_WSID1_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T6_SEQ(_VAL_) (REG32(ADR_WSID1_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T7_SEQ(_VAL_) (REG32(ADR_WSID1_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0xffff0000))
++#define SET_ADDR1A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffffc))
++#define SET_ADDR2A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 2) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffff3))
++#define SET_ADDR3A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 4) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffffcf))
++#define SET_ADDR1B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 6) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffff3f))
++#define SET_ADDR2B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffcff))
++#define SET_ADDR3B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 10) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffff3ff))
++#define SET_ADDR3C_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 12) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffcfff))
++#define SET_FRM_CTRL(_VAL_) (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (((_VAL_) << 0) | ((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0xffffffc0))
++#define SET_CSR_PHY_INFO(_VAL_) (REG32(ADR_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_INFO)) & 0xffff8000))
++#define SET_AMPDU_SIG(_VAL_) (REG32(ADR_AMPDU_SIG)) = (((_VAL_) << 0) | ((REG32(ADR_AMPDU_SIG)) & 0xffffff00))
++#define SET_MIB_AMPDU(_VAL_) (REG32(ADR_MIB_AMPDU)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_AMPDU)) & 0x00000000))
++#define SET_LEN_FLT(_VAL_) (REG32(ADR_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_LEN_FLT)) & 0xffff0000))
++#define SET_MIB_DELIMITER(_VAL_) (REG32(ADR_MIB_DELIMITER)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_DELIMITER)) & 0xffff0000))
++#define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_STS)) & 0xfffeffff))
++#define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_STS)) & 0xfffdffff))
++#define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_STS)) & 0xfffbffff))
++#define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_STS)) & 0xfff7ffff))
++#define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_STS)) & 0xffefffff))
++#define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_STS)) & 0xffdfffff))
++#define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_STS)) & 0xffbfffff))
++#define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_STS)) & 0xff7fffff))
++#define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_STS)) & 0xfeffffff))
++#define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_STS)) & 0xfdffffff))
++#define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_EN)) & 0xfffeffff))
++#define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_EN)) & 0xfffdffff))
++#define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_EN)) & 0xfffbffff))
++#define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_EN)) & 0xfff7ffff))
++#define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_EN)) & 0xffefffff))
++#define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_EN)) & 0xffdfffff))
++#define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_EN)) & 0xffbfffff))
++#define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_EN)) & 0xff7fffff))
++#define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_EN)) & 0xfeffffff))
++#define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_EN)) & 0xfdffffff))
++#define SET_MTX_MTX2PHY_SLOW(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffffe))
++#define SET_MTX_M2M_SLOW_PRD(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffff1))
++#define SET_MTX_AMPDU_CRC_AUTO(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffdf))
++#define SET_MTX_FAST_RSP_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffbf))
++#define SET_MTX_RAW_DATA_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffff7f))
++#define SET_MTX_ACK_DUR0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffeff))
++#define SET_MTX_TSF_AUTO_BCN(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffbff))
++#define SET_MTX_TSF_AUTO_MISC(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffff7ff))
++#define SET_MTX_FORCE_CS_IDLE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffefff))
++#define SET_MTX_FORCE_BKF_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffdfff))
++#define SET_MTX_FORCE_DMA_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffbfff))
++#define SET_MTX_FORCE_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_MISC_EN)) & 0xffff7fff))
++#define SET_MTX_HALT_Q_MB(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_MISC_EN)) & 0xffc0ffff))
++#define SET_MTX_CTS_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_MISC_EN)) & 0xffbfffff))
++#define SET_MTX_AMPDU_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_MISC_EN)) & 0xff7fffff))
++#define SET_MTX_EDCCA_TOUT(_VAL_) (REG32(ADR_MTX_EDCCA_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_EDCCA_TOUT)) & 0xfffffc00))
++#define SET_MTX_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffffd))
++#define SET_MTX_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffff7))
++#define SET_MTX_EN_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffffd))
++#define SET_MTX_EN_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffff7))
++#define SET_MTX_BCN_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffe))
++#define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffd))
++#define SET_MTX_TSF_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffdf))
++#define SET_MTX_HALT_MNG_UNTIL_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffbf))
++#define SET_MTX_INT_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffff00ff))
++#define SET_MTX_AUTO_FLUSH_Q4(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffeffff))
++#define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffffe))
++#define SET_MTX_BCN_CFG_VLD(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff9))
++#define SET_MTX_AUTO_BCN_ONGOING(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff7))
++#define SET_MTX_BCN_TIMER(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_MISC)) & 0x0000ffff))
++#define SET_MTX_BCN_PERIOD(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_PRD)) & 0xffff0000))
++#define SET_MTX_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_BCN_PRD)) & 0x00ffffff))
++#define SET_MTX_BCN_TSF_L(_VAL_) (REG32(ADR_MTX_BCN_TSF_L)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_L)) & 0x00000000))
++#define SET_MTX_BCN_TSF_U(_VAL_) (REG32(ADR_MTX_BCN_TSF_U)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_U)) & 0x00000000))
++#define SET_MTX_BCN_PKT_ID0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xffffff80))
++#define SET_MTX_DTIM_OFST0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xfc00ffff))
++#define SET_MTX_BCN_PKT_ID1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xffffff80))
++#define SET_MTX_DTIM_OFST1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xfc00ffff))
++#define SET_MTX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffe))
++#define SET_MRX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffd))
++#define SET_MTX_DMA_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 2) | ((REG32(ADR_MTX_STATUS)) & 0xffffffe3))
++#define SET_CH_ST_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_STATUS)) & 0xffffff1f))
++#define SET_MTX_GNT_LOCK(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_STATUS)) & 0xfffffeff))
++#define SET_MTX_DMA_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MTX_STATUS)) & 0xfffffdff))
++#define SET_MTX_Q_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_STATUS)) & 0xfffffbff))
++#define SET_MTX_TX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_STATUS)) & 0xfffff7ff))
++#define SET_MRX_RX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_STATUS)) & 0xffffefff))
++#define SET_DBG_PRTC_PRD(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_STATUS)) & 0xffffdfff))
++#define SET_DBG_DMA_RDY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_STATUS)) & 0xffffbfff))
++#define SET_DBG_WAIT_RSP(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_STATUS)) & 0xffff7fff))
++#define SET_DBG_CFRM_BUSY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_STATUS)) & 0xfffeffff))
++#define SET_DBG_RST(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffe))
++#define SET_DBG_MODE(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffd))
++#define SET_MB_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000))
++#define SET_RX_EN_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff))
++#define SET_RX_CS_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000))
++#define SET_TX_CCA_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff))
++#define SET_Q_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000))
++#define SET_CH_STA0_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff))
++#define SET_MTX_DUR_RSP_TOUT_B(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffffff00))
++#define SET_MTX_DUR_RSP_TOUT_G(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffff00ff))
++#define SET_MTX_DUR_RSP_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffffff00))
++#define SET_MTX_DUR_BURST_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffff00ff))
++#define SET_MTX_DUR_SLOT(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffc0ffff))
++#define SET_MTX_DUR_RSP_EIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_IFS)) & 0x003fffff))
++#define SET_MTX_DUR_RSP_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffffff00))
++#define SET_MTX_DUR_BURST_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffff00ff))
++#define SET_MTX_DUR_SLOT_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc0ffff))
++#define SET_MTX_DUR_RSP_EIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003fffff))
++#define SET_CH_STA1_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000))
++#define SET_CH_STA2_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff))
++#define SET_MTX_NAV(_VAL_) (REG32(ADR_MTX_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_NAV)) & 0xffff0000))
++#define SET_MTX_MIB_CNT0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xc0000000))
++#define SET_MTX_MIB_EN0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xbfffffff))
++#define SET_MTX_MIB_CNT1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xc0000000))
++#define SET_MTX_MIB_EN1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xbfffffff))
++#define SET_CH_STA3_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000))
++#define SET_CH_STA4_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff))
++#define SET_TXQ0_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ0_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ0_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ0_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ0_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ0_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ0_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ0_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ0_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ0_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ1_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ1_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ1_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ1_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ1_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ1_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ1_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ1_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ1_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ1_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ2_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ2_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ2_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ2_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ2_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ2_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ2_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ2_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ2_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ2_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ3_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ3_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ3_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ3_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ3_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ3_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ3_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ3_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ3_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ3_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ4_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ4_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ4_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ4_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ4_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ4_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ4_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ4_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ4_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ4_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_VALID0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0)) & 0xfffffffe))
++#define SET_PEER_QOS_EN0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 1) | ((REG32(ADR_WSID0)) & 0xfffffffd))
++#define SET_PEER_OP_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 2) | ((REG32(ADR_WSID0)) & 0xfffffff3))
++#define SET_PEER_HT_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 4) | ((REG32(ADR_WSID0)) & 0xffffffcf))
++#define SET_PEER_MAC0_31_0(_VAL_) (REG32(ADR_PEER_MAC0_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_0)) & 0x00000000))
++#define SET_PEER_MAC0_47_32(_VAL_) (REG32(ADR_PEER_MAC0_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_1)) & 0xffff0000))
++#define SET_TX_ACK_POLICY_0_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_0)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_1)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_2)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_3)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_4)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_5)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_6)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_7)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0xfffff000))
++#define SET_VALID1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1)) & 0xfffffffe))
++#define SET_PEER_QOS_EN1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 1) | ((REG32(ADR_WSID1)) & 0xfffffffd))
++#define SET_PEER_OP_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 2) | ((REG32(ADR_WSID1)) & 0xfffffff3))
++#define SET_PEER_HT_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 4) | ((REG32(ADR_WSID1)) & 0xffffffcf))
++#define SET_PEER_MAC1_31_0(_VAL_) (REG32(ADR_PEER_MAC1_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_0)) & 0x00000000))
++#define SET_PEER_MAC1_47_32(_VAL_) (REG32(ADR_PEER_MAC1_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_1)) & 0xffff0000))
++#define SET_TX_ACK_POLICY_1_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_0)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_1)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_2)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_3)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_4)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_5)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_6)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_7)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0xfffff000))
++#define SET_INFO0(_VAL_) (REG32(ADR_INFO0)) = (((_VAL_) << 0) | ((REG32(ADR_INFO0)) & 0x00000000))
++#define SET_INFO1(_VAL_) (REG32(ADR_INFO1)) = (((_VAL_) << 0) | ((REG32(ADR_INFO1)) & 0x00000000))
++#define SET_INFO2(_VAL_) (REG32(ADR_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_INFO2)) & 0x00000000))
++#define SET_INFO3(_VAL_) (REG32(ADR_INFO3)) = (((_VAL_) << 0) | ((REG32(ADR_INFO3)) & 0x00000000))
++#define SET_INFO4(_VAL_) (REG32(ADR_INFO4)) = (((_VAL_) << 0) | ((REG32(ADR_INFO4)) & 0x00000000))
++#define SET_INFO5(_VAL_) (REG32(ADR_INFO5)) = (((_VAL_) << 0) | ((REG32(ADR_INFO5)) & 0x00000000))
++#define SET_INFO6(_VAL_) (REG32(ADR_INFO6)) = (((_VAL_) << 0) | ((REG32(ADR_INFO6)) & 0x00000000))
++#define SET_INFO7(_VAL_) (REG32(ADR_INFO7)) = (((_VAL_) << 0) | ((REG32(ADR_INFO7)) & 0x00000000))
++#define SET_INFO8(_VAL_) (REG32(ADR_INFO8)) = (((_VAL_) << 0) | ((REG32(ADR_INFO8)) & 0x00000000))
++#define SET_INFO9(_VAL_) (REG32(ADR_INFO9)) = (((_VAL_) << 0) | ((REG32(ADR_INFO9)) & 0x00000000))
++#define SET_INFO10(_VAL_) (REG32(ADR_INFO10)) = (((_VAL_) << 0) | ((REG32(ADR_INFO10)) & 0x00000000))
++#define SET_INFO11(_VAL_) (REG32(ADR_INFO11)) = (((_VAL_) << 0) | ((REG32(ADR_INFO11)) & 0x00000000))
++#define SET_INFO12(_VAL_) (REG32(ADR_INFO12)) = (((_VAL_) << 0) | ((REG32(ADR_INFO12)) & 0x00000000))
++#define SET_INFO13(_VAL_) (REG32(ADR_INFO13)) = (((_VAL_) << 0) | ((REG32(ADR_INFO13)) & 0x00000000))
++#define SET_INFO14(_VAL_) (REG32(ADR_INFO14)) = (((_VAL_) << 0) | ((REG32(ADR_INFO14)) & 0x00000000))
++#define SET_INFO15(_VAL_) (REG32(ADR_INFO15)) = (((_VAL_) << 0) | ((REG32(ADR_INFO15)) & 0x00000000))
++#define SET_INFO16(_VAL_) (REG32(ADR_INFO16)) = (((_VAL_) << 0) | ((REG32(ADR_INFO16)) & 0x00000000))
++#define SET_INFO17(_VAL_) (REG32(ADR_INFO17)) = (((_VAL_) << 0) | ((REG32(ADR_INFO17)) & 0x00000000))
++#define SET_INFO18(_VAL_) (REG32(ADR_INFO18)) = (((_VAL_) << 0) | ((REG32(ADR_INFO18)) & 0x00000000))
++#define SET_INFO19(_VAL_) (REG32(ADR_INFO19)) = (((_VAL_) << 0) | ((REG32(ADR_INFO19)) & 0x00000000))
++#define SET_INFO20(_VAL_) (REG32(ADR_INFO20)) = (((_VAL_) << 0) | ((REG32(ADR_INFO20)) & 0x00000000))
++#define SET_INFO21(_VAL_) (REG32(ADR_INFO21)) = (((_VAL_) << 0) | ((REG32(ADR_INFO21)) & 0x00000000))
++#define SET_INFO22(_VAL_) (REG32(ADR_INFO22)) = (((_VAL_) << 0) | ((REG32(ADR_INFO22)) & 0x00000000))
++#define SET_INFO23(_VAL_) (REG32(ADR_INFO23)) = (((_VAL_) << 0) | ((REG32(ADR_INFO23)) & 0x00000000))
++#define SET_INFO24(_VAL_) (REG32(ADR_INFO24)) = (((_VAL_) << 0) | ((REG32(ADR_INFO24)) & 0x00000000))
++#define SET_INFO25(_VAL_) (REG32(ADR_INFO25)) = (((_VAL_) << 0) | ((REG32(ADR_INFO25)) & 0x00000000))
++#define SET_INFO26(_VAL_) (REG32(ADR_INFO26)) = (((_VAL_) << 0) | ((REG32(ADR_INFO26)) & 0x00000000))
++#define SET_INFO27(_VAL_) (REG32(ADR_INFO27)) = (((_VAL_) << 0) | ((REG32(ADR_INFO27)) & 0x00000000))
++#define SET_INFO28(_VAL_) (REG32(ADR_INFO28)) = (((_VAL_) << 0) | ((REG32(ADR_INFO28)) & 0x00000000))
++#define SET_INFO29(_VAL_) (REG32(ADR_INFO29)) = (((_VAL_) << 0) | ((REG32(ADR_INFO29)) & 0x00000000))
++#define SET_INFO30(_VAL_) (REG32(ADR_INFO30)) = (((_VAL_) << 0) | ((REG32(ADR_INFO30)) & 0x00000000))
++#define SET_INFO31(_VAL_) (REG32(ADR_INFO31)) = (((_VAL_) << 0) | ((REG32(ADR_INFO31)) & 0x00000000))
++#define SET_INFO32(_VAL_) (REG32(ADR_INFO32)) = (((_VAL_) << 0) | ((REG32(ADR_INFO32)) & 0x00000000))
++#define SET_INFO33(_VAL_) (REG32(ADR_INFO33)) = (((_VAL_) << 0) | ((REG32(ADR_INFO33)) & 0x00000000))
++#define SET_INFO34(_VAL_) (REG32(ADR_INFO34)) = (((_VAL_) << 0) | ((REG32(ADR_INFO34)) & 0x00000000))
++#define SET_INFO35(_VAL_) (REG32(ADR_INFO35)) = (((_VAL_) << 0) | ((REG32(ADR_INFO35)) & 0x00000000))
++#define SET_INFO36(_VAL_) (REG32(ADR_INFO36)) = (((_VAL_) << 0) | ((REG32(ADR_INFO36)) & 0x00000000))
++#define SET_INFO37(_VAL_) (REG32(ADR_INFO37)) = (((_VAL_) << 0) | ((REG32(ADR_INFO37)) & 0x00000000))
++#define SET_INFO38(_VAL_) (REG32(ADR_INFO38)) = (((_VAL_) << 0) | ((REG32(ADR_INFO38)) & 0x00000000))
++#define SET_INFO_MASK(_VAL_) (REG32(ADR_INFO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_MASK)) & 0x00000000))
++#define SET_INFO_DEF_RATE(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xffffffc0))
++#define SET_INFO_MRX_OFFSET(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xfff0ffff))
++#define SET_BCAST_RATEUNKNOW(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 24) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xc0ffffff))
++#define SET_INFO_IDX_TBL_ADDR(_VAL_) (REG32(ADR_INFO_IDX_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_IDX_ADDR)) & 0x00000000))
++#define SET_INFO_LEN_TBL_ADDR(_VAL_) (REG32(ADR_INFO_LEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_LEN_ADDR)) & 0x00000000))
++#define SET_IC_TAG_31_0(_VAL_) (REG32(ADR_IC_TIME_TAG_0)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_0)) & 0x00000000))
++#define SET_IC_TAG_63_32(_VAL_) (REG32(ADR_IC_TIME_TAG_1)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_1)) & 0x00000000))
++#define SET_CH1_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffffc))
++#define SET_CH2_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 8) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffcff))
++#define SET_CH3_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 16) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffcffff))
++#define SET_RG_MAC_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_MODE)) & 0xfffffffe))
++#define SET_RG_MAC_M2M(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_MODE)) & 0xfffffffd))
++#define SET_RG_PHY_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_MAC_MODE)) & 0xfffffffb))
++#define SET_RG_LPBK_RX_EN(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_MODE)) & 0xfffffff7))
++#define SET_EXT_MAC_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_MODE)) & 0xffffffef))
++#define SET_EXT_PHY_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_MODE)) & 0xffffffdf))
++#define SET_ASIC_TAG(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 24) | ((REG32(ADR_MAC_MODE)) & 0x00ffffff))
++#define SET_HCI_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffe))
++#define SET_CO_PROC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffd))
++#define SET_MTX_MISC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffff7))
++#define SET_MTX_QUE_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffef))
++#define SET_MTX_CHST_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffdf))
++#define SET_MTX_BCN_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffbf))
++#define SET_MRX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffff7f))
++#define SET_AMPDU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffeff))
++#define SET_MMU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffdff))
++#define SET_ID_MNG_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffff7ff))
++#define SET_MBOX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffefff))
++#define SET_SCRT_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffdfff))
++#define SET_MIC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffbfff))
++#define SET_CO_PROC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffffd))
++#define SET_MTX_MISC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffff7))
++#define SET_MTX_QUE_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffef))
++#define SET_MTX_CHST_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffdf))
++#define SET_MTX_BCN_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffbf))
++#define SET_MRX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffff7f))
++#define SET_AMPDU_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffeff))
++#define SET_ID_MNG_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffbfff))
++#define SET_MBOX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffff7fff))
++#define SET_SCRT_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 16) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffeffff))
++#define SET_MIC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 17) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffdffff))
++#define SET_CO_PROC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffffd))
++#define SET_MTX_MISC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffff7))
++#define SET_MTX_QUE0_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffef))
++#define SET_MTX_QUE1_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffdf))
++#define SET_MTX_QUE2_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffbf))
++#define SET_MTX_QUE3_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffff7f))
++#define SET_MTX_QUE4_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffeff))
++#define SET_MTX_QUE5_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffdff))
++#define SET_MRX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffbff))
++#define SET_AMPDU_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffff7ff))
++#define SET_SCRT_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffdfff))
++#define SET_ID_MNG_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffbfff))
++#define SET_MBOX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffff7fff))
++#define SET_HCI_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffe))
++#define SET_CO_PROC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MTX_MISC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffff7))
++#define SET_MTX_QUE_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffef))
++#define SET_MRX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffdf))
++#define SET_AMPDU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffbf))
++#define SET_MMU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffff7f))
++#define SET_ID_MNG_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffdff))
++#define SET_MBOX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_SCRT_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffff7ff))
++#define SET_MIC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffefff))
++#define SET_MIB_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_HCI_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffe))
++#define SET_CO_PROC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MTX_MISC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffff7))
++#define SET_MTX_QUE_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffef))
++#define SET_MRX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffdf))
++#define SET_AMPDU_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffbf))
++#define SET_ID_MNG_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffefff))
++#define SET_MBOX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_SCRT_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffbfff))
++#define SET_MIC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffff7fff))
++#define SET_CO_PROC_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MRX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_AMPDU_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffff7ff))
++#define SET_SCRT_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_ID_MNG_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffbfff))
++#define SET_MBOX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffff7fff))
++#define SET_OP_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 0) | ((REG32(ADR_GLBLE_SET)) & 0xfffffffc))
++#define SET_HT_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 2) | ((REG32(ADR_GLBLE_SET)) & 0xfffffff3))
++#define SET_QOS_EN(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 4) | ((REG32(ADR_GLBLE_SET)) & 0xffffffef))
++#define SET_PB_OFFSET(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 8) | ((REG32(ADR_GLBLE_SET)) & 0xffff00ff))
++#define SET_SNIFFER_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 16) | ((REG32(ADR_GLBLE_SET)) & 0xfffeffff))
++#define SET_DUP_FLT(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 17) | ((REG32(ADR_GLBLE_SET)) & 0xfffdffff))
++#define SET_TX_PKT_RSVD(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 18) | ((REG32(ADR_GLBLE_SET)) & 0xffe3ffff))
++#define SET_AMPDU_SNIFFER(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 21) | ((REG32(ADR_GLBLE_SET)) & 0xffdfffff))
++#define SET_REASON_TRAP0(_VAL_) (REG32(ADR_REASON_TRAP0)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP0)) & 0x00000000))
++#define SET_REASON_TRAP1(_VAL_) (REG32(ADR_REASON_TRAP1)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP1)) & 0x00000000))
++#define SET_BSSID_31_0(_VAL_) (REG32(ADR_BSSID_0)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_0)) & 0x00000000))
++#define SET_BSSID_47_32(_VAL_) (REG32(ADR_BSSID_1)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_1)) & 0xffff0000))
++#define SET_SCRT_STATE(_VAL_) (REG32(ADR_SCRT_STATE)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_STATE)) & 0xfffffff0))
++#define SET_STA_MAC_31_0(_VAL_) (REG32(ADR_STA_MAC_0)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_0)) & 0x00000000))
++#define SET_STA_MAC_47_32(_VAL_) (REG32(ADR_STA_MAC_1)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_1)) & 0xffff0000))
++#define SET_PAIR_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_SET)) & 0xfffffff8))
++#define SET_GRP_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 3) | ((REG32(ADR_SCRT_SET)) & 0xffffffc7))
++#define SET_SCRT_PKT_ID(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 6) | ((REG32(ADR_SCRT_SET)) & 0xffffe03f))
++#define SET_SCRT_RPLY_IGNORE(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 16) | ((REG32(ADR_SCRT_SET)) & 0xfffeffff))
++#define SET_COEXIST_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX0)) & 0xfffffffe))
++#define SET_WIRE_MODE(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 1) | ((REG32(ADR_BTCX0)) & 0xfffffff1))
++#define SET_WL_RX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 4) | ((REG32(ADR_BTCX0)) & 0xffffffef))
++#define SET_WL_TX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 5) | ((REG32(ADR_BTCX0)) & 0xffffffdf))
++#define SET_GURAN_USE_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX0)) & 0xfffffeff))
++#define SET_GURAN_USE_CTRL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 9) | ((REG32(ADR_BTCX0)) & 0xfffffdff))
++#define SET_BEACON_TIMEOUT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 10) | ((REG32(ADR_BTCX0)) & 0xfffffbff))
++#define SET_WLAN_ACT_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 11) | ((REG32(ADR_BTCX0)) & 0xfffff7ff))
++#define SET_DUAL_ANT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 12) | ((REG32(ADR_BTCX0)) & 0xffffefff))
++#define SET_TRSW_PHY_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX0)) & 0xfffeffff))
++#define SET_WIFI_TX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 17) | ((REG32(ADR_BTCX0)) & 0xfffdffff))
++#define SET_WIFI_RX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 18) | ((REG32(ADR_BTCX0)) & 0xfffbffff))
++#define SET_BT_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 19) | ((REG32(ADR_BTCX0)) & 0xfff7ffff))
++#define SET_BT_PRI_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX1)) & 0xffffff00))
++#define SET_BT_STA_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX1)) & 0xffff00ff))
++#define SET_BEACON_TIMEOUT(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX1)) & 0xff00ffff))
++#define SET_WLAN_REMAIN_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 24) | ((REG32(ADR_BTCX1)) & 0x00ffffff))
++#define SET_SW_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffe))
++#define SET_SW_WL_TX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 1) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffd))
++#define SET_SW_WL_RX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 2) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffb))
++#define SET_SW_BT_TRX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 3) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffff7))
++#define SET_BT_TXBAR_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 4) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffef))
++#define SET_BT_TXBAR_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 5) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffdf))
++#define SET_BT_BUSY_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffeff))
++#define SET_BT_BUSY_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 9) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffdff))
++#define SET_G0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 2) | ((REG32(ADR_MIB_EN)) & 0xfffffffb))
++#define SET_G0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 3) | ((REG32(ADR_MIB_EN)) & 0xfffffff7))
++#define SET_G1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 4) | ((REG32(ADR_MIB_EN)) & 0xffffffef))
++#define SET_G1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MIB_EN)) & 0xffffffdf))
++#define SET_Q0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MIB_EN)) & 0xffffffbf))
++#define SET_Q0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MIB_EN)) & 0xffffff7f))
++#define SET_Q1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MIB_EN)) & 0xfffffeff))
++#define SET_Q1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 9) | ((REG32(ADR_MIB_EN)) & 0xfffffdff))
++#define SET_Q2_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MIB_EN)) & 0xfffffbff))
++#define SET_Q2_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MIB_EN)) & 0xfffff7ff))
++#define SET_Q3_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MIB_EN)) & 0xffffefff))
++#define SET_Q3_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MIB_EN)) & 0xffffdfff))
++#define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MIB_EN)) & 0xffffbfff))
++#define SET_SCRT_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MIB_EN)) & 0xffff7fff))
++#define SET_MISC_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MIB_EN)) & 0xfffeffff))
++#define SET_MISC_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MIB_EN)) & 0xfffdffff))
++#define SET_MTX_WSID0_SUCC(_VAL_) (REG32(ADR_MTX_WSID0_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_SUCC)) & 0xffff0000))
++#define SET_MTX_WSID0_FRM(_VAL_) (REG32(ADR_MTX_WSID0_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_FRM)) & 0xffff0000))
++#define SET_MTX_WSID0_RETRY(_VAL_) (REG32(ADR_MTX_WSID0_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_RETRY)) & 0xffff0000))
++#define SET_MTX_WSID0_TOTAL(_VAL_) (REG32(ADR_MTX_WSID0_TOTAL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_TOTAL)) & 0xffff0000))
++#define SET_MTX_GRP(_VAL_) (REG32(ADR_MTX_GROUP)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_GROUP)) & 0xfff00000))
++#define SET_MTX_FAIL(_VAL_) (REG32(ADR_MTX_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FAIL)) & 0xffff0000))
++#define SET_MTX_RETRY(_VAL_) (REG32(ADR_MTX_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RETRY)) & 0xfff00000))
++#define SET_MTX_MULTI_RETRY(_VAL_) (REG32(ADR_MTX_MULTI_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MULTI_RETRY)) & 0xfff00000))
++#define SET_MTX_RTS_SUCC(_VAL_) (REG32(ADR_MTX_RTS_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_SUCCESS)) & 0xffff0000))
++#define SET_MTX_RTS_FAIL(_VAL_) (REG32(ADR_MTX_RTS_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_FAIL)) & 0xffff0000))
++#define SET_MTX_ACK_FAIL(_VAL_) (REG32(ADR_MTX_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_FAIL)) & 0xffff0000))
++#define SET_MTX_FRM(_VAL_) (REG32(ADR_MTX_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FRM)) & 0xfff00000))
++#define SET_MTX_ACK_TX(_VAL_) (REG32(ADR_MTX_ACK_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_TX)) & 0xffff0000))
++#define SET_MTX_CTS_TX(_VAL_) (REG32(ADR_MTX_CTS_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_CTS_TX)) & 0xffff0000))
++#define SET_MRX_DUP(_VAL_) (REG32(ADR_MRX_DUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DUP_FRM)) & 0xffff0000))
++#define SET_MRX_FRG(_VAL_) (REG32(ADR_MRX_FRG_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FRG_FRM)) & 0xfff00000))
++#define SET_MRX_GRP(_VAL_) (REG32(ADR_MRX_GROUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_GROUP_FRM)) & 0xfff00000))
++#define SET_MRX_FCS_ERR(_VAL_) (REG32(ADR_MRX_FCS_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_ERR)) & 0xffff0000))
++#define SET_MRX_FCS_SUC(_VAL_) (REG32(ADR_MRX_FCS_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_SUCC)) & 0xffff0000))
++#define SET_MRX_MISS(_VAL_) (REG32(ADR_MRX_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MISS)) & 0xffff0000))
++#define SET_MRX_ALC_FAIL(_VAL_) (REG32(ADR_MRX_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ALC_FAIL)) & 0xffff0000))
++#define SET_MRX_DAT_NTF(_VAL_) (REG32(ADR_MRX_DAT_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_NTF)) & 0xffff0000))
++#define SET_MRX_RTS_NTF(_VAL_) (REG32(ADR_MRX_RTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_RTS_NTF)) & 0xffff0000))
++#define SET_MRX_CTS_NTF(_VAL_) (REG32(ADR_MRX_CTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CTS_NTF)) & 0xffff0000))
++#define SET_MRX_ACK_NTF(_VAL_) (REG32(ADR_MRX_ACK_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ACK_NTF)) & 0xffff0000))
++#define SET_MRX_BA_NTF(_VAL_) (REG32(ADR_MRX_BA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_NTF)) & 0xffff0000))
++#define SET_MRX_DATA_NTF(_VAL_) (REG32(ADR_MRX_DATA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DATA_NTF)) & 0xffff0000))
++#define SET_MRX_MNG_NTF(_VAL_) (REG32(ADR_MRX_MNG_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MNG_NTF)) & 0xffff0000))
++#define SET_MRX_DAT_CRC_NTF(_VAL_) (REG32(ADR_MRX_DAT_CRC_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_CRC_NTF)) & 0xffff0000))
++#define SET_MRX_BAR_NTF(_VAL_) (REG32(ADR_MRX_BAR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BAR_NTF)) & 0xffff0000))
++#define SET_MRX_MB_MISS(_VAL_) (REG32(ADR_MRX_MB_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MB_MISS)) & 0xffff0000))
++#define SET_MRX_NIDLE_MISS(_VAL_) (REG32(ADR_MRX_NIDLE_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_NIDLE_MISS)) & 0xffff0000))
++#define SET_MRX_CSR_NTF(_VAL_) (REG32(ADR_MRX_CSR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CSR_NTF)) & 0xffff0000))
++#define SET_DBG_Q0_SUCC(_VAL_) (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q0_FAIL(_VAL_) (REG32(ADR_DBG_Q0_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q0_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q0_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q0_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0xffff0000))
++#define SET_DBG_Q1_SUCC(_VAL_) (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q1_FAIL(_VAL_) (REG32(ADR_DBG_Q1_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q1_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q1_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q1_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0xffff0000))
++#define SET_DBG_Q2_SUCC(_VAL_) (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q2_FAIL(_VAL_) (REG32(ADR_DBG_Q2_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q2_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q2_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q2_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0xffff0000))
++#define SET_DBG_Q3_SUCC(_VAL_) (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q3_FAIL(_VAL_) (REG32(ADR_DBG_Q3_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q3_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q3_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q3_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0xffff0000))
++#define SET_SCRT_TKIP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP0)) & 0xfff00000))
++#define SET_SCRT_TKIP_MIC_ERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP1)) & 0xfff00000))
++#define SET_SCRT_TKIP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_TKIP2)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP2)) & 0xfff00000))
++#define SET_SCRT_CCMP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_CCMP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP0)) & 0xfff00000))
++#define SET_SCRT_CCMP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_CCMP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP1)) & 0xfff00000))
++#define SET_DBG_LEN_CRC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_CRC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0xffff0000))
++#define SET_DBG_LEN_ALC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0xffff0000))
++#define SET_DBG_AMPDU_PASS(_VAL_) (REG32(ADR_DBG_AMPDU_PASS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_PASS)) & 0xffff0000))
++#define SET_DBG_AMPDU_FAIL(_VAL_) (REG32(ADR_DBG_AMPDU_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_FAIL)) & 0xffff0000))
++#define SET_RXID_ALC_CNT_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL1)) & 0xffff0000))
++#define SET_RXID_ALC_LEN_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL2)) & 0xffff0000))
++#define SET_CBR_RG_EN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_TX_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_TX_PA_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_TX_DAC_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_RX_AGC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
++#define SET_CBR_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
++#define SET_CBR_RG_RFG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
++#define SET_CBR_RG_PGAG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
++#define SET_CBR_RG_MODE(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
++#define SET_CBR_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
++#define SET_CBR_RG_EN_SX(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
++#define SET_CBR_RG_EN_RX_LNA(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
++#define SET_CBR_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
++#define SET_CBR_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
++#define SET_CBR_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
++#define SET_CBR_RG_EN_RX_TZ(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
++#define SET_CBR_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
++#define SET_CBR_RG_EN_RX_HPF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
++#define SET_CBR_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
++#define SET_CBR_RG_EN_ADC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
++#define SET_CBR_RG_EN_TX_MOD(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
++#define SET_CBR_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
++#define SET_CBR_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
++#define SET_CBR_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
++#define SET_CBR_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
++#define SET_CBR_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
++#define SET_CBR_RG_EN_TX_DPD(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
++#define SET_CBR_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
++#define SET_CBR_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
++#define SET_CBR_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
++#define SET_CBR_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
++#define SET_CBR_RG_EN_IREF_RX(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
++#define SET_CBR_RG_DCDC_MODE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffefff))
++#define SET_CBR_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffff8))
++#define SET_CBR_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffffffc7))
++#define SET_CBR_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffe3f))
++#define SET_CBR_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffff1ff))
++#define SET_CBR_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffff8fff))
++#define SET_CBR_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffc7fff))
++#define SET_CBR_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffe3ffff))
++#define SET_CBR_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xff1fffff))
++#define SET_CBR_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xf8ffffff))
++#define SET_CBR_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xc7ffffff))
++#define SET_CBR_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffe))
++#define SET_CBR_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffd))
++#define SET_CBR_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffb))
++#define SET_CBR_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffe07))
++#define SET_CBR_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffdff))
++#define SET_CBR_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffbff))
++#define SET_CBR_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffff7ff))
++#define SET_CBR_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffffcfff))
++#define SET_CBR_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffff3fff))
++#define SET_CBR_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffcffff))
++#define SET_CBR_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfff3ffff))
++#define SET_CBR_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffcfffff))
++#define SET_CBR_RG_RX_HPF3M(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffbfffff))
++#define SET_CBR_RG_RX_HPF300K(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xff7fffff))
++#define SET_CBR_RG_RX_HPFI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfcffffff))
++#define SET_CBR_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xf3ffffff))
++#define SET_CBR_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xcfffffff))
++#define SET_CBR_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffffc))
++#define SET_CBR_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffff3))
++#define SET_CBR_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffffcf))
++#define SET_CBR_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffff3f))
++#define SET_CBR_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffcff))
++#define SET_CBR_RG_RX_OUTVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffff3ff))
++#define SET_CBR_RG_RX_TZI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffcfff))
++#define SET_CBR_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffbfff))
++#define SET_CBR_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffe7fff))
++#define SET_CBR_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfff1ffff))
++#define SET_CBR_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffefffff))
++#define SET_CBR_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xff9fffff))
++#define SET_CBR_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfe7fffff))
++#define SET_CBR_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfdffffff))
++#define SET_CBR_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffffffc))
++#define SET_CBR_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffff03))
++#define SET_CBR_RG_TXPGA_STEER(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffc0ff))
++#define SET_CBR_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffff3fff))
++#define SET_CBR_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffcffff))
++#define SET_CBR_RG_PACELL_EN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffe3ffff))
++#define SET_CBR_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfe1fffff))
++#define SET_CBR_RG_PABIAS_AB(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfdffffff))
++#define SET_CBR_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xf3ffffff))
++#define SET_CBR_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xcfffffff))
++#define SET_CBR_RG_RX_SQDC(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffffff8))
++#define SET_CBR_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffffe7))
++#define SET_CBR_RG_RX_LOBUF(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffff9f))
++#define SET_CBR_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffff87f))
++#define SET_CBR_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffff87ff))
++#define SET_CBR_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffc7fff))
++#define SET_CBR_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffe3ffff))
++#define SET_CBR_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffdfffff))
++#define SET_CBR_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xff3fffff))
++#define SET_CBR_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
++#define SET_CBR_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
++#define SET_CBR_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
++#define SET_CBR_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
++#define SET_CBR_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
++#define SET_CBR_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
++#define SET_CBR_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
++#define SET_CBR_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
++#define SET_CBR_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
++#define SET_CBR_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
++#define SET_CBR_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
++#define SET_CBR_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
++#define SET_CBR_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
++#define SET_CBR_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
++#define SET_CBR_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
++#define SET_CBR_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
++#define SET_CBR_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_HPF_T1A(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffffe7))
++#define SET_CBR_RG_HPF_T1B(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffff9f))
++#define SET_CBR_RG_HPF_T1C(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffe7f))
++#define SET_CBR_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffff9ff))
++#define SET_CBR_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffe7ff))
++#define SET_CBR_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff9))
++#define SET_CBR_RG_ADC_DIVR(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_ADC_DVCMI(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffffffcf))
++#define SET_CBR_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffc3f))
++#define SET_CBR_RG_ADC_STNBY(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffbff))
++#define SET_CBR_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffff7ff))
++#define SET_CBR_RG_ADC_TSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffff0fff))
++#define SET_CBR_RG_ADC_VRSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffcffff))
++#define SET_CBR_RG_DICMP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfff3ffff))
++#define SET_CBR_RG_DIOP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffcfffff))
++#define SET_CBR_RG_DACI1ST(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffffc))
++#define SET_CBR_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffff3))
++#define SET_CBR_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffffcf))
++#define SET_CBR_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffff3f))
++#define SET_CBR_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffff9ff))
++#define SET_CBR_RG_TX_DAC_OS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffc7ff))
++#define SET_CBR_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffff3fff))
++#define SET_CBR_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfff0ffff))
++#define SET_CBR_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffefffff))
++#define SET_CBR_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffdfffff))
++#define SET_CBR_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffbfffff))
++#define SET_CBR_RG_EN_SX_R3(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_EN_SX_CH(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_EN_SX_CHP(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffef))
++#define SET_CBR_RG_EN_SX_VCO(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffdf))
++#define SET_CBR_RG_EN_SX_MOD(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffbf))
++#define SET_CBR_RG_EN_SX_LCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffff7f))
++#define SET_CBR_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_EN_SX_DELCAL(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_EN_SX_PC_BYPASS(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffbff))
++#define SET_CBR_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffff7ff))
++#define SET_CBR_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffefff))
++#define SET_CBR_RG_EN_SX_DIV(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffdfff))
++#define SET_CBR_RG_EN_SX_LPF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffbfff))
++#define SET_CBR_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xff000000))
++#define SET_CBR_RG_SX_SEL_CP(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0ffffff))
++#define SET_CBR_RG_SX_SEL_CS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0fffffff))
++#define SET_CBR_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfffff800))
++#define SET_CBR_RG_SX_SEL_C3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xffff87ff))
++#define SET_CBR_RG_SX_SEL_RS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfff07fff))
++#define SET_CBR_RG_SX_SEL_R3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfe0fffff))
++#define SET_CBR_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffffe0))
++#define SET_CBR_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffffc1f))
++#define SET_CBR_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffc3ff))
++#define SET_CBR_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffc3fff))
++#define SET_CBR_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffbffff))
++#define SET_CBR_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffc7ffff))
++#define SET_CBR_RG_SX_PFDSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffbfffff))
++#define SET_CBR_RG_SX_PFD_SET(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xff7fffff))
++#define SET_CBR_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfeffffff))
++#define SET_CBR_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfdffffff))
++#define SET_CBR_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfbffffff))
++#define SET_CBR_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xf7ffffff))
++#define SET_CBR_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xefffffff))
++#define SET_CBR_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xdfffffff))
++#define SET_CBR_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xbfffffff))
++#define SET_CBR_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffffff8))
++#define SET_CBR_RG_SX_VCORSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffffff07))
++#define SET_CBR_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffff0ff))
++#define SET_CBR_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffff0fff))
++#define SET_CBR_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfff0ffff))
++#define SET_CBR_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xff0fffff))
++#define SET_CBR_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0ffffff))
++#define SET_CBR_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0fffffff))
++#define SET_CBR_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
++#define SET_CBR_RG_SX_MOD_ERRCMP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffff3))
++#define SET_CBR_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
++#define SET_CBR_RG_SX_SDM_D1(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffbf))
++#define SET_CBR_RG_SX_SDM_D2(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffff7f))
++#define SET_CBR_RG_SDM_PASS(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffeff))
++#define SET_CBR_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
++#define SET_CBR_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
++#define SET_CBR_RG_SX_XO_GM(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
++#define SET_CBR_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
++#define SET_CBR_RG_SX_XO_SWCAP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffc3fff))
++#define SET_CBR_RG_SX_SDMLUT_INV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffbffff))
++#define SET_CBR_RG_SX_LCKEN(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
++#define SET_CBR_RG_SX_PREVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
++#define SET_CBR_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
++#define SET_CBR_RG_SX_MOD_ERR_DELAY(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xcfffffff))
++#define SET_CBR_RG_SX_MODDB(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xbfffffff))
++#define SET_CBR_RG_SX_CV_CURVE_SEL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffffffc))
++#define SET_CBR_RG_SX_SEL_DELAY(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffff83))
++#define SET_CBR_RG_SX_REF_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff87f))
++#define SET_CBR_RG_SX_VCOBY16(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff7ff))
++#define SET_CBR_RG_SX_VCOBY32(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffefff))
++#define SET_CBR_RG_SX_PH(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffdfff))
++#define SET_CBR_RG_SX_PL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffbfff))
++#define SET_CBR_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffffe))
++#define SET_CBR_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffff9))
++#define SET_CBR_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffe7))
++#define SET_CBR_RG_SX_VT_SET(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffdf))
++#define SET_CBR_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffff803f))
++#define SET_CBR_RG_IDEAL_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xf0007fff))
++#define SET_CBR_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffff9))
++#define SET_CBR_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffffe7))
++#define SET_CBR_RG_DP_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffc01f))
++#define SET_CBR_RG_DP_CK320BY2(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffbfff))
++#define SET_CBR_RG_SX_DELCTRL(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffe07fff))
++#define SET_CBR_RG_DP_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffdfffff))
++#define SET_CBR_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
++#define SET_CBR_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
++#define SET_CBR_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
++#define SET_CBR_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
++#define SET_CBR_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
++#define SET_CBR_RG_DP_RP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
++#define SET_CBR_RG_DP_RHP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
++#define SET_CBR_RG_DP_DR3(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xff8fffff))
++#define SET_CBR_RG_DP_DCP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xf87fffff))
++#define SET_CBR_RG_DP_DCS(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x87ffffff))
++#define SET_CBR_RG_DP_FBDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xfffff000))
++#define SET_CBR_RG_DP_FODIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00fff))
++#define SET_CBR_RG_DP_REFDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003fffff))
++#define SET_CBR_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
++#define SET_CBR_RG_EN_RCAL(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_RCAL_SPD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_RCAL_TMR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffe03))
++#define SET_CBR_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xffff83ff))
++#define SET_CBR_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffffff01))
++#define SET_CBR_RG_DP_BBPLL_BS_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_DP_BBPLL_BS_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffff81ff))
++#define SET_CBR_RCAL_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
++#define SET_CBR_DA_LCK_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
++#define SET_CBR_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
++#define SET_CBR_DP_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffff7))
++#define SET_CBR_CH_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffffef))
++#define SET_CBR_DA_R_CODE_LUT(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
++#define SET_CBR_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
++#define SET_CBR_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
++#define SET_CBR_DA_R_CAL_CODE(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
++#define SET_CBR_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
++#define SET_CBR_DA_DP_BBPLL_BS(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffc0fff))
++#define SET_CBR_TX_EN(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffe))
++#define SET_CBR_TX_CNT_RST(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffd))
++#define SET_CBR_IFS_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xffffff03))
++#define SET_CBR_LENGTH_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfff000ff))
++#define SET_CBR_TX_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00ffffff))
++#define SET_CBR_TC_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0xff000000))
++#define SET_CBR_PLCP_PSDU_DATA_MEM(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffffff00))
++#define SET_CBR_PLCP_PSDU_PREAMBLE_SHORT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xfffffeff))
++#define SET_CBR_PLCP_BYTE_LENGTH(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffe001ff))
++#define SET_CBR_PLCP_PSDU_RATE(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xff9fffff))
++#define SET_CBR_TAIL_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xe07fffff))
++#define SET_CBR_RG_O_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffe))
++#define SET_CBR_RG_I_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffd))
++#define SET_CBR_SEL_ADCKP_INV(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffb))
++#define SET_CBR_RG_PAD_DS(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffff7))
++#define SET_CBR_SEL_ADCKP_MUX(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffef))
++#define SET_CBR_RG_PAD_DS_CLK(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffdf))
++#define SET_CBR_INTP_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffdff))
++#define SET_CBR_IQ_SWP(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffbff))
++#define SET_CBR_RG_EN_EXT_DA(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffff7ff))
++#define SET_CBR_RG_DIS_DA_OFFSET(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffefff))
++#define SET_CBR_DBG_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfff0ffff))
++#define SET_CBR_DBG_EN(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffefffff))
++#define SET_CBR_RG_PKT_GEN_TX_CNT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0x00000000))
++#define SET_CBR_TP_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffe0))
++#define SET_CBR_IDEAL_IQ_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffdf))
++#define SET_CBR_DATA_OUT_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffe3f))
++#define SET_CBR_TWO_TONE_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffdff))
++#define SET_CBR_FREQ_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xff00ffff))
++#define SET_CBR_IQ_SCALE(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ffffff))
++#define SET_CPU_QUE_POP(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 0) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffe))
++#define SET_CPU_INT(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 2) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffb))
++#define SET_CPU_ID_TB0(_VAL_) (REG32(ADR_CPU_ID_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB0)) & 0x00000000))
++#define SET_CPU_ID_TB1(_VAL_) (REG32(ADR_CPU_ID_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB1)) & 0x00000000))
++#define SET_HW_PKTID(_VAL_) (REG32(ADR_CH0_TRIG_1)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_1)) & 0xfffff800))
++#define SET_CH0_INT_ADDR(_VAL_) (REG32(ADR_CH0_TRIG_0)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_0)) & 0x00000000))
++#define SET_PRI_HW_PKTID(_VAL_) (REG32(ADR_CH0_PRI_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_PRI_TRIG)) & 0xfffff800))
++#define SET_CH0_FULL(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffe))
++#define SET_FF0_EMPTY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffd))
++#define SET_RLS_BUSY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_STATUS)) & 0xfffffdff))
++#define SET_RLS_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MCU_STATUS)) & 0xfffffbff))
++#define SET_RTN_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MCU_STATUS)) & 0xfffff7ff))
++#define SET_RLS_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MCU_STATUS)) & 0xff00ffff))
++#define SET_RTN_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MCU_STATUS)) & 0x00ffffff))
++#define SET_FF0_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffffe0))
++#define SET_FF1_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfffffe1f))
++#define SET_FF3_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffc7ff))
++#define SET_FF5_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 17) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfff1ffff))
++#define SET_FF6_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xff8fffff))
++#define SET_FF7_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 23) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfc7fffff))
++#define SET_FF8_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 26) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xe3ffffff))
++#define SET_FF9_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 29) | ((REG32(ADR_RD_IN_FFCNT1)) & 0x1fffffff))
++#define SET_FF10_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffff8))
++#define SET_FF11_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 3) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffffc7))
++#define SET_FF12_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 6) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffe3f))
++#define SET_FF13_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 9) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffff9ff))
++#define SET_FF14_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffe7ff))
++#define SET_FF15_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 13) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffff9fff))
++#define SET_FF4_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfff07fff))
++#define SET_FF2_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xff8fffff))
++#define SET_CH1_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffd))
++#define SET_CH2_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffb))
++#define SET_CH3_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffff7))
++#define SET_CH4_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffef))
++#define SET_CH5_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffdf))
++#define SET_CH6_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffbf))
++#define SET_CH7_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffff7f))
++#define SET_CH8_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffeff))
++#define SET_CH9_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffdff))
++#define SET_CH10_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffbff))
++#define SET_CH11_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffff7ff))
++#define SET_CH12_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffefff))
++#define SET_CH13_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffdfff))
++#define SET_CH14_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffbfff))
++#define SET_CH15_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffff7fff))
++#define SET_HALT_CH0(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffe))
++#define SET_HALT_CH1(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffd))
++#define SET_HALT_CH2(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffb))
++#define SET_HALT_CH3(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 3) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffff7))
++#define SET_HALT_CH4(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffef))
++#define SET_HALT_CH5(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffdf))
++#define SET_HALT_CH6(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffbf))
++#define SET_HALT_CH7(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffff7f))
++#define SET_HALT_CH8(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffeff))
++#define SET_HALT_CH9(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 9) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffdff))
++#define SET_HALT_CH10(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 10) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffbff))
++#define SET_HALT_CH11(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 11) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffff7ff))
++#define SET_HALT_CH12(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 12) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffefff))
++#define SET_HALT_CH13(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 13) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffdfff))
++#define SET_HALT_CH14(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 14) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffbfff))
++#define SET_HALT_CH15(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 15) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffff7fff))
++#define SET_STOP_MBOX(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffeffff))
++#define SET_MB_ERR_AUTO_HALT_EN(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 20) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffefffff))
++#define SET_MB_EXCEPT_CLR(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 21) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffdfffff))
++#define SET_MB_EXCEPT_CASE(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 24) | ((REG32(ADR_MBOX_HALT_CFG)) & 0x00ffffff))
++#define SET_MB_DBG_TIME_STEP(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG1)) & 0xffff0000))
++#define SET_DBG_TYPE(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffcffff))
++#define SET_MB_DBG_CLR(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffbffff))
++#define SET_DBG_ALC_LOG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfff7ffff))
++#define SET_MB_DBG_COUNTER_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfeffffff))
++#define SET_MB_DBG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG1)) & 0x7fffffff))
++#define SET_MB_DBG_RECORD_CNT(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000))
++#define SET_MB_DBG_LENGTH(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff))
++#define SET_MB_DBG_CFG_ADDR(_VAL_) (REG32(ADR_MB_DBG_CFG3)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG3)) & 0x00000000))
++#define SET_DBG_HWID0_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffe))
++#define SET_DBG_HWID1_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 1) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffd))
++#define SET_DBG_HWID2_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 2) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffb))
++#define SET_DBG_HWID3_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 3) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffff7))
++#define SET_DBG_HWID4_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 4) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffef))
++#define SET_DBG_HWID5_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 5) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffdf))
++#define SET_DBG_HWID6_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 6) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffbf))
++#define SET_DBG_HWID7_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 7) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffff7f))
++#define SET_DBG_HWID8_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 8) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffeff))
++#define SET_DBG_HWID9_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 9) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffdff))
++#define SET_DBG_HWID10_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 10) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffbff))
++#define SET_DBG_HWID11_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 11) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffff7ff))
++#define SET_DBG_HWID12_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 12) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffefff))
++#define SET_DBG_HWID13_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 13) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffdfff))
++#define SET_DBG_HWID14_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 14) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffbfff))
++#define SET_DBG_HWID15_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 15) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffff7fff))
++#define SET_DBG_HWID0_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffeffff))
++#define SET_DBG_HWID1_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 17) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffdffff))
++#define SET_DBG_HWID2_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffbffff))
++#define SET_DBG_HWID3_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfff7ffff))
++#define SET_DBG_HWID4_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 20) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffefffff))
++#define SET_DBG_HWID5_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 21) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffdfffff))
++#define SET_DBG_HWID6_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 22) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffbfffff))
++#define SET_DBG_HWID7_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 23) | ((REG32(ADR_MB_DBG_CFG4)) & 0xff7fffff))
++#define SET_DBG_HWID8_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfeffffff))
++#define SET_DBG_HWID9_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 25) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfdffffff))
++#define SET_DBG_HWID10_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 26) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfbffffff))
++#define SET_DBG_HWID11_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 27) | ((REG32(ADR_MB_DBG_CFG4)) & 0xf7ffffff))
++#define SET_DBG_HWID12_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 28) | ((REG32(ADR_MB_DBG_CFG4)) & 0xefffffff))
++#define SET_DBG_HWID13_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 29) | ((REG32(ADR_MB_DBG_CFG4)) & 0xdfffffff))
++#define SET_DBG_HWID14_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 30) | ((REG32(ADR_MB_DBG_CFG4)) & 0xbfffffff))
++#define SET_DBG_HWID15_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG4)) & 0x7fffffff))
++#define SET_MB_OUT_QUEUE_EN(_VAL_) (REG32(ADR_MB_OUT_QUEUE_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0xfffffffd))
++#define SET_CH0_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffe))
++#define SET_CH1_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffd))
++#define SET_CH2_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffb))
++#define SET_CH3_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffff7))
++#define SET_CH4_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffef))
++#define SET_CH5_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffdf))
++#define SET_CH6_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffbf))
++#define SET_CH7_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffff7f))
++#define SET_CH8_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffeff))
++#define SET_CH9_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffdff))
++#define SET_CH10_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffbff))
++#define SET_CH11_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffff7ff))
++#define SET_CH12_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffefff))
++#define SET_CH13_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffdfff))
++#define SET_CH14_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffbfff))
++#define SET_CH15_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 15) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffff7fff))
++#define SET_FFO0_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffffffe0))
++#define SET_FFO1_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffffc1f))
++#define SET_FFO2_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffff3ff))
++#define SET_FFO3_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfff07fff))
++#define SET_FFO4_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffcfffff))
++#define SET_FFO5_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xf1ffffff))
++#define SET_FFO6_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffff0))
++#define SET_FFO7_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffc1f))
++#define SET_FFO8_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xffff83ff))
++#define SET_FFO9_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfff07fff))
++#define SET_FFO10_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xff0fffff))
++#define SET_FFO11_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xc1ffffff))
++#define SET_FFO12_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffffff8))
++#define SET_FFO13_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffffff9f))
++#define SET_FFO14_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffff3ff))
++#define SET_FFO15_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffe07fff))
++#define SET_CH0_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffe))
++#define SET_CH1_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffd))
++#define SET_CH2_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffb))
++#define SET_CH3_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffff7))
++#define SET_CH4_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffef))
++#define SET_CH5_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffdf))
++#define SET_CH6_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffbf))
++#define SET_CH7_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffff7f))
++#define SET_CH8_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffeff))
++#define SET_CH9_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffdff))
++#define SET_CH10_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffbff))
++#define SET_CH11_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffff7ff))
++#define SET_CH12_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffefff))
++#define SET_CH13_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffdfff))
++#define SET_CH14_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffbfff))
++#define SET_CH15_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffff7fff))
++#define SET_CH0_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffe))
++#define SET_CH1_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 1) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffd))
++#define SET_CH2_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 2) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffb))
++#define SET_CH3_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 3) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffff7))
++#define SET_CH4_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 4) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffef))
++#define SET_CH5_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 5) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffdf))
++#define SET_CH6_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 6) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffbf))
++#define SET_CH7_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 7) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffff7f))
++#define SET_CH8_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffeff))
++#define SET_CH9_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 9) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffdff))
++#define SET_CH10_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 10) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffbff))
++#define SET_CH11_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 11) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffff7ff))
++#define SET_CH12_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 12) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffefff))
++#define SET_CH13_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 13) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffdfff))
++#define SET_CH14_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 14) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffbfff))
++#define SET_CH15_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 15) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffff7fff))
++#define SET_MB_LOW_THOLD_EN(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 31) | ((REG32(ADR_MB_THRESHOLD6)) & 0x7fffffff))
++#define SET_CH0_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffffe0))
++#define SET_CH1_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffe0ff))
++#define SET_CH2_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffe0ffff))
++#define SET_CH3_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD7)) & 0xe0ffffff))
++#define SET_CH4_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffffe0))
++#define SET_CH5_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffe0ff))
++#define SET_CH6_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffe0ffff))
++#define SET_CH7_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD8)) & 0xe0ffffff))
++#define SET_CH8_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffffe0))
++#define SET_CH9_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffe0ff))
++#define SET_CH10_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffe0ffff))
++#define SET_CH11_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD9)) & 0xe0ffffff))
++#define SET_CH12_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffffe0))
++#define SET_CH13_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffe0ff))
++#define SET_CH14_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffe0ffff))
++#define SET_CH15_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD10)) & 0xe0ffffff))
++#define SET_TRASH_TIMEOUT_EN(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffe))
++#define SET_TRASH_CAN_INT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffd))
++#define SET_TRASH_INT_ID(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffff80f))
++#define SET_TRASH_TIMEOUT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfc00ffff))
++#define SET_CH0_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffe))
++#define SET_CH1_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffd))
++#define SET_CH2_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffb))
++#define SET_CH3_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffff7))
++#define SET_CH4_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffef))
++#define SET_CH5_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffdf))
++#define SET_CH6_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffbf))
++#define SET_CH7_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffff7f))
++#define SET_CH8_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffeff))
++#define SET_CH9_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffdff))
++#define SET_CH10_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffbff))
++#define SET_CH11_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffff7ff))
++#define SET_CH12_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffefff))
++#define SET_CH13_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffdfff))
++#define SET_CH14_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffbfff))
++#define SET_CPU_ID_TB2(_VAL_) (REG32(ADR_CPU_ID_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB2)) & 0x00000000))
++#define SET_CPU_ID_TB3(_VAL_) (REG32(ADR_CPU_ID_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB3)) & 0x00000000))
++#define SET_IQ_LOG_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0xfffffffe))
++#define SET_IQ_LOG_STOP_MODE(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xfffffffe))
++#define SET_GPIO_STOP_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffef))
++#define SET_GPIO_STOP_POL(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffdf))
++#define SET_IQ_LOG_TIMER(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x0000ffff))
++#define SET_IQ_LOG_LEN(_VAL_) (REG32(ADR_PHY_IQ_LOG_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000))
++#define SET_IQ_LOG_TAIL_ADR(_VAL_) (REG32(ADR_PHY_IQ_LOG_PTR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_PTR)) & 0xffff0000))
++#define SET_ALC_LENG(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 0) | ((REG32(ADR_WR_ALC)) & 0xfffc0000))
++#define SET_CH0_DYN_PRI(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 20) | ((REG32(ADR_WR_ALC)) & 0xffcfffff))
++#define SET_MCU_PKTID(_VAL_) (REG32(ADR_GETID)) = (((_VAL_) << 0) | ((REG32(ADR_GETID)) & 0x00000000))
++#define SET_CH0_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffffc))
++#define SET_CH1_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_STA_PRI)) & 0xffffffcf))
++#define SET_CH2_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffcff))
++#define SET_CH3_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_STA_PRI)) & 0xffffcfff))
++#define SET_ID_TB0(_VAL_) (REG32(ADR_RD_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID0)) & 0x00000000))
++#define SET_ID_TB1(_VAL_) (REG32(ADR_RD_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID1)) & 0x00000000))
++#define SET_ID_MNG_HALT(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_CFG)) & 0xffffffef))
++#define SET_ID_MNG_ERR_HALT_EN(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_CFG)) & 0xffffffdf))
++#define SET_ID_EXCEPT_FLG_CLR(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_CFG)) & 0xffffffbf))
++#define SET_ID_EXCEPT_FLG(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_CFG)) & 0xffffff7f))
++#define SET_ID_FULL(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 0) | ((REG32(ADR_IMD_STA)) & 0xfffffffe))
++#define SET_ID_MNG_BUSY(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 1) | ((REG32(ADR_IMD_STA)) & 0xfffffffd))
++#define SET_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 2) | ((REG32(ADR_IMD_STA)) & 0xfffffffb))
++#define SET_CH0_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_STA)) & 0xffffffef))
++#define SET_CH1_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_STA)) & 0xffffffdf))
++#define SET_CH2_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_STA)) & 0xffffffbf))
++#define SET_CH3_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_STA)) & 0xffffff7f))
++#define SET_REQ_LOCK_INT_EN(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 8) | ((REG32(ADR_IMD_STA)) & 0xfffffeff))
++#define SET_REQ_LOCK_INT(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 9) | ((REG32(ADR_IMD_STA)) & 0xfffffdff))
++#define SET_MCU_ALC_READY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_STA)) & 0xfffffffe))
++#define SET_ALC_FAIL(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 1) | ((REG32(ADR_ALC_STA)) & 0xfffffffd))
++#define SET_ALC_BUSY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 2) | ((REG32(ADR_ALC_STA)) & 0xfffffffb))
++#define SET_CH0_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 4) | ((REG32(ADR_ALC_STA)) & 0xffffffef))
++#define SET_CH1_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 5) | ((REG32(ADR_ALC_STA)) & 0xffffffdf))
++#define SET_CH2_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 6) | ((REG32(ADR_ALC_STA)) & 0xffffffbf))
++#define SET_CH3_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 7) | ((REG32(ADR_ALC_STA)) & 0xffffff7f))
++#define SET_ALC_INT_ID(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_STA)) & 0xffff80ff))
++#define SET_ALC_TIMEOUT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_STA)) & 0xfc00ffff))
++#define SET_ALC_TIMEOUT_INT_EN(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 30) | ((REG32(ADR_ALC_STA)) & 0xbfffffff))
++#define SET_ALC_TIMEOUT_INT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_STA)) & 0x7fffffff))
++#define SET_TX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffffff00))
++#define SET_RX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffff00ff))
++#define SET_TX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffffff00))
++#define SET_RX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffff00ff))
++#define SET_ID_THOLD_RX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfffeffff))
++#define SET_RX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 17) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfff1ffff))
++#define SET_ID_THOLD_TX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 20) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffefffff))
++#define SET_TX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 21) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xff1fffff))
++#define SET_ID_THOLD_INT_EN(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfeffffff))
++#define SET_TX_ID_TB0(_VAL_) (REG32(ADR_TX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID0)) & 0x00000000))
++#define SET_TX_ID_TB1(_VAL_) (REG32(ADR_TX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID1)) & 0x00000000))
++#define SET_RX_ID_TB0(_VAL_) (REG32(ADR_RX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID0)) & 0x00000000))
++#define SET_RX_ID_TB1(_VAL_) (REG32(ADR_RX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID1)) & 0x00000000))
++#define SET_DOUBLE_RLS_INT_EN(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 0) | ((REG32(ADR_RTN_STA)) & 0xfffffffe))
++#define SET_ID_DOUBLE_RLS_INT(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 1) | ((REG32(ADR_RTN_STA)) & 0xfffffffd))
++#define SET_DOUBLE_RLS_ID(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 8) | ((REG32(ADR_RTN_STA)) & 0xffff80ff))
++#define SET_ID_LEN_THOLD_INT_EN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffe))
++#define SET_ALL_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 1) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffd))
++#define SET_TX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 2) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffb))
++#define SET_RX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 3) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffff7))
++#define SET_ID_TX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 4) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffffe00f))
++#define SET_ID_RX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 13) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffc01fff))
++#define SET_ID_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 22) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x803fffff))
++#define SET_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffffe00))
++#define SET_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 9) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffc01ff))
++#define SET_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 18) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xf803ffff))
++#define SET_CH_ARB_EN(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffffe))
++#define SET_CH_PRI1(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffffcf))
++#define SET_CH_PRI2(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffcff))
++#define SET_CH_PRI3(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffcfff))
++#define SET_CH_PRI4(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 16) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffcffff))
++#define SET_TX_ID_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xffffff80))
++#define SET_TX_PAGE_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xfffe00ff))
++#define SET_ID_PAGE_MAX_SIZE(_VAL_) (REG32(ADR_ID_INFO_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ID_INFO_STA)) & 0xfffffe00))
++#define SET_TX_PAGE_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xfffffe00))
++#define SET_TX_COUNT_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xff00ffff))
++#define SET_TX_LIMIT_INT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 30) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xbfffffff))
++#define SET_TX_LIMIT_INT_EN(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 31) | ((REG32(ADR_TX_LIMIT_INTR)) & 0x7fffffff))
++#define SET_TX_PAGE_USE_7_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffff00))
++#define SET_TX_ID_USE_5_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffc0ff))
++#define SET_EDCA0_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 14) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xfffc3fff))
++#define SET_EDCA1_FFO_CNT_3_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 18) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffc3ffff))
++#define SET_EDCA2_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xf83fffff))
++#define SET_EDCA3_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 27) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0x07ffffff))
++#define SET_ID_TB2(_VAL_) (REG32(ADR_RD_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID2)) & 0x00000000))
++#define SET_ID_TB3(_VAL_) (REG32(ADR_RD_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID3)) & 0x00000000))
++#define SET_TX_ID_TB2(_VAL_) (REG32(ADR_TX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID2)) & 0x00000000))
++#define SET_TX_ID_TB3(_VAL_) (REG32(ADR_TX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID3)) & 0x00000000))
++#define SET_RX_ID_TB2(_VAL_) (REG32(ADR_RX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID2)) & 0x00000000))
++#define SET_RX_ID_TB3(_VAL_) (REG32(ADR_RX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID3)) & 0x00000000))
++#define SET_TX_PAGE_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffffe00))
++#define SET_TX_ID_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffe01ff))
++#define SET_EDCA4_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xffe1ffff))
++#define SET_TX_PAGE_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffffe00))
++#define SET_TX_ID_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffe01ff))
++#define SET_EDCA1_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 21) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfc1fffff))
++#define SET_EDCA4_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 26) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xc3ffffff))
++#define SET_TX_PAGE_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffffe00))
++#define SET_TX_ID_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffe01ff))
++#define SET_EDCA2_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xffc1ffff))
++#define SET_EDCA3_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xf83fffff))
++#define SET_TX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfffffe00))
++#define SET_RX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfe00ffff))
++#define SET_MAX_ALL_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INFO)) & 0xffffff00))
++#define SET_MAX_TX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_ID_INFO)) & 0xffff00ff))
++#define SET_MAX_RX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_ID_INFO)) & 0xff00ffff))
++#define SET_MAX_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffffe00))
++#define SET_MAX_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 9) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffc01ff))
++#define SET_MAX_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 18) | ((REG32(ADR_ALC_ID_INF1)) & 0xf803ffff))
++#define SET_RG_PMDLBK(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_0)) & 0xfffffffe))
++#define SET_RG_RDYACK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff9))
++#define SET_RG_ADEDGE_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff7))
++#define SET_RG_SIGN_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_0)) & 0xffffffef))
++#define SET_RG_IQ_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_0)) & 0xffffffdf))
++#define SET_RG_Q_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_0)) & 0xffffffbf))
++#define SET_RG_I_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_EN_0)) & 0xffffff7f))
++#define SET_RG_BYPASS_ACI(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_0)) & 0xfffffeff))
++#define SET_RG_LBK_ANA_PATH(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_EN_0)) & 0xfffffdff))
++#define SET_RG_SPECTRUM_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_EN_0)) & 0xfffff3ff))
++#define SET_RG_SPECTRUM_BW(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_0)) & 0xffffcfff))
++#define SET_RG_SPECTRUM_FREQ_MANUAL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_0)) & 0xffffbfff))
++#define SET_RG_SPECTRUM_EN(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_0)) & 0xffff7fff))
++#define SET_RG_TXPWRLVL_SET(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_0)) & 0xff00ffff))
++#define SET_RG_TXPWRLVL_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_EN_0)) & 0xfeffffff))
++#define SET_RG_RF_BB_CLK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_EN_0)) & 0x7fffffff))
++#define SET_RG_PHY_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffe))
++#define SET_RG_PHYRX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffd))
++#define SET_RG_PHYTX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffb))
++#define SET_RG_PHY11GN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_1)) & 0xfffffff7))
++#define SET_RG_PHY11B_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_1)) & 0xffffffef))
++#define SET_RG_PHYRXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_1)) & 0xffffffdf))
++#define SET_RG_PHYTXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_1)) & 0xffffffbf))
++#define SET_RG_PHY11BGN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_1)) & 0xfffffeff))
++#define SET_RG_FORCE_11GN_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_1)) & 0xffffefff))
++#define SET_RG_FORCE_11B_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 13) | ((REG32(ADR_PHY_EN_1)) & 0xffffdfff))
++#define SET_RG_FFT_MEM_CLK_EN_RX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_1)) & 0xffffbfff))
++#define SET_RG_FFT_MEM_CLK_EN_TX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_1)) & 0xffff7fff))
++#define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_1)) & 0xfff0ffff))
++#define SET_RG_SPECTRUM_FREQ(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_EN_1)) & 0xc00fffff))
++#define SET_SVN_VERSION(_VAL_) (REG32(ADR_SVN_VERSION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SVN_VERSION_REG)) & 0x00000000))
++#define SET_RG_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffff0000))
++#define SET_RG_PKT_MODE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xfff8ffff))
++#define SET_RG_CH_BW(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 19) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffc7ffff))
++#define SET_RG_PRM(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 22) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffbfffff))
++#define SET_RG_SHORTGI(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xff7fffff))
++#define SET_RG_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0x80ffffff))
++#define SET_RG_L_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xfffff000))
++#define SET_RG_L_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff8fff))
++#define SET_RG_SERVICE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0x0000ffff))
++#define SET_RG_SMOOTHING(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffe))
++#define SET_RG_NO_SOUND(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffd))
++#define SET_RG_AGGREGATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffb))
++#define SET_RG_STBC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffe7))
++#define SET_RG_FEC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffdf))
++#define SET_RG_N_ESS(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffff3f))
++#define SET_RG_TXPWRLVL(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffff00ff))
++#define SET_RG_TX_START(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffffe))
++#define SET_RG_IFS_TIME(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xffffff03))
++#define SET_RG_CONTINUOUS_DATA(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffeff))
++#define SET_RG_DATA_SEL(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffff9ff))
++#define SET_RG_TX_D(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xff00ffff))
++#define SET_RG_TX_CNT_TARGET(_VAL_) (REG32(ADR_PHY_PKT_GEN_4)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_4)) & 0x00000000))
++#define SET_RG_FFT_IFFT_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_REG_00)) & 0xffffff3f))
++#define SET_RG_DAC_DBG_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_00)) & 0xfffffeff))
++#define SET_RG_DAC_SGN_SWAP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_REG_00)) & 0xfffffdff))
++#define SET_RG_TXD_SEL(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_REG_00)) & 0xfffff3ff))
++#define SET_RG_UP8X(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_00)) & 0xff00ffff))
++#define SET_RG_IQ_DC_BYP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_00)) & 0xfeffffff))
++#define SET_RG_IQ_DC_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_00)) & 0xcfffffff))
++#define SET_RG_DAC_DCEN(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_01)) & 0xfffffffe))
++#define SET_RG_DAC_DCQ(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_01)) & 0xffffc00f))
++#define SET_RG_DAC_DCI(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_01)) & 0xfc00ffff))
++#define SET_RG_PGA_REFDB_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffffff80))
++#define SET_RG_PGA_REFDB_TOP(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffff80ff))
++#define SET_RG_PGA_REF_UND(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xfc00ffff))
++#define SET_RG_RF_REF_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_02_AGC)) & 0x0fffffff))
++#define SET_RG_PGAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xfffffff0))
++#define SET_RG_PGAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffffef))
++#define SET_RG_RFGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff9f))
++#define SET_RG_RFGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff7f))
++#define SET_RG_WAIT_T_RXAGC(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffc0ff))
++#define SET_RG_RXAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffbfff))
++#define SET_RG_RXAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffff7fff))
++#define SET_RG_WAIT_T_FINAL(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffc0ffff))
++#define SET_RG_WAIT_T(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xc0ffffff))
++#define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffffff0))
++#define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffffff0f))
++#define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffff0ff))
++#define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffff0fff))
++#define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfff0ffff))
++#define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xff0fffff))
++#define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xf0ffffff))
++#define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_04_AGC)) & 0x0fffffff))
++#define SET_RG_MG_PGA_JB_TH(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xfffffff0))
++#define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xffe0ffff))
++#define SET_RG_WR_RFGC_INIT_SET(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 21) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff9fffff))
++#define SET_RG_WR_RFGC_INIT_EN(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff7fffff))
++#define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xe0ffffff))
++#define SET_RG_AGC_THRESHOLD(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xffffc000))
++#define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xff80ffff))
++#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xfcffffff))
++#define SET_RG_WR_ACI_GAIN_INI_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffffff00))
++#define SET_RG_WR_ACI_GAIN_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffff00ff))
++#define SET_RG_ACI_DAGC_SET_VALUE_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xff80ffff))
++#define SET_RG_WR_ACI_GAIN_OW_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x7fffffff))
++#define SET_RG_ACI_POINT_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xffffff00))
++#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xfffffcff))
++#define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00ffffff))
++#define SET_RG_ACI_DAGC_SET_VALUE_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffffff80))
++#define SET_RG_ACI_GAIN_INI_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffff00ff))
++#define SET_RG_ACI_GAIN_OW_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xff00ffff))
++#define SET_RG_ACI_GAIN_OW_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x7fffffff))
++#define SET_RO_CCA_PWR_MA_11GN(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffffff80))
++#define SET_RO_ED_STATE(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffff7fff))
++#define SET_RO_CCA_PWR_MA_11B(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xff80ffff))
++#define SET_RO_PGA_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xffffc000))
++#define SET_RO_RF_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xfff0ffff))
++#define SET_RO_PGAGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xf0ffffff))
++#define SET_RO_RFGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xcfffffff))
++#define SET_RO_PGA_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xffffc000))
++#define SET_RO_RF_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xfff0ffff))
++#define SET_RO_PGAGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xf0ffffff))
++#define SET_RO_RFGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xcfffffff))
++#define SET_RO_PGA_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xffffc000))
++#define SET_RO_RF_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xfff0ffff))
++#define SET_RO_PGAGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xf0ffffff))
++#define SET_RO_RFGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xcfffffff))
++#define SET_RG_TX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffffe0))
++#define SET_RG_TX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffe0ff))
++#define SET_RG_TX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffe0ffff))
++#define SET_RG_TX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xe0ffffff))
++#define SET_RG_TX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffffe0))
++#define SET_RG_TX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffe0ff))
++#define SET_RG_TX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffe0ffff))
++#define SET_RG_TX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xe0ffffff))
++#define SET_RG_TX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffffe))
++#define SET_RG_TX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffffef))
++#define SET_RG_TX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffeff))
++#define SET_RG_TX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffefff))
++#define SET_RG_TX_DES_PWRLVL(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffe0ffff))
++#define SET_RG_TX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xe0ffffff))
++#define SET_RG_RX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffffc0))
++#define SET_RG_RX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffc0ff))
++#define SET_RG_RX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffc0ffff))
++#define SET_RG_RX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xc0ffffff))
++#define SET_RG_RX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffffc0))
++#define SET_RG_RX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffc0ff))
++#define SET_RG_RX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffc0ffff))
++#define SET_RG_RX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xc0ffffff))
++#define SET_RG_RX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffffe))
++#define SET_RG_RX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffffef))
++#define SET_RG_RX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffeff))
++#define SET_RG_RX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffefff))
++#define SET_RG_RX_DES_SNR(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfff0ffff))
++#define SET_RG_RX_DES_RCPI(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xff0fffff))
++#define SET_RG_RX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xc0ffffff))
++#define SET_RO_TX_DES_EXCP_RATE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffffff00))
++#define SET_RO_TX_DES_EXCP_CH_BW_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffff00ff))
++#define SET_RO_TX_DES_EXCP_MODE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xff00ffff))
++#define SET_RG_TX_DES_EXCP_RATE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xf8ffffff))
++#define SET_RG_TX_DES_EXCP_MODE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x8fffffff))
++#define SET_RG_TX_DES_EXCP_CLR(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x7fffffff))
++#define SET_RG_TX_DES_ACK_WIDTH(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffffe))
++#define SET_RG_TX_DES_ACK_PRD(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffff1))
++#define SET_RG_RX_DES_SNR_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xffc0ffff))
++#define SET_RG_RX_DES_RCPI_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xc0ffffff))
++#define SET_RG_TST_TBUS_SEL(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfffffff0))
++#define SET_RG_RSSI_OFFSET(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xff00ffff))
++#define SET_RG_RSSI_INV(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfeffffff))
++#define SET_RG_TST_ADC_ON(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xbfffffff))
++#define SET_RG_TST_EXT_GAIN(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x7fffffff))
++#define SET_RG_DAC_Q_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xfffffc00))
++#define SET_RG_DAC_I_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xffc00fff))
++#define SET_RG_DAC_EN_MAN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xefffffff))
++#define SET_RG_IQC_FFT_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xdfffffff))
++#define SET_RG_DAC_MAN_Q_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xbfffffff))
++#define SET_RG_DAC_MAN_I_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x7fffffff))
++#define SET_RO_MRX_EN_CNT(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0xffff0000))
++#define SET_RG_MRX_EN_CNT_RST_N(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x7fffffff))
++#define SET_RG_PA_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffffff00))
++#define SET_RG_RFTX_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffff00ff))
++#define SET_RG_DAC_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff00ffff))
++#define SET_RG_SW_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ffffff))
++#define SET_RG_PA_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffffff00))
++#define SET_RG_RFTX_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffff00ff))
++#define SET_RG_DAC_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff00ffff))
++#define SET_RG_SW_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ffffff))
++#define SET_RG_ANT_SW_0(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xfffffff8))
++#define SET_RG_ANT_SW_1(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xffffffc7))
++#define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MTX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x7fffffff))
++#define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MTX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x7fffffff))
++#define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MRX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x7fffffff))
++#define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MRX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x7fffffff))
++#define SET_RO_MTX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000))
++#define SET_RO_MTX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff))
++#define SET_RO_MRX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000))
++#define SET_RO_MRX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff))
++#define SET_RG_MODE_REG_IN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffff0000))
++#define SET_RG_PARALLEL_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffefffff))
++#define SET_RG_MBRUN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xfeffffff))
++#define SET_RG_SHIFT_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xefffffff))
++#define SET_RG_MODE_REG_SI_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xdfffffff))
++#define SET_RG_SIMULATION_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xbfffffff))
++#define SET_RG_DBIST_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_28_BIST)) & 0x7fffffff))
++#define SET_RO_MODE_REG_OUT_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xffff0000))
++#define SET_RO_MODE_REG_SO_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xfeffffff))
++#define SET_RO_MONITOR_BUS_16(_VAL_) (REG32(ADR_PHY_READ_REG_07_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_07_BIST)) & 0xfff80000))
++#define SET_RG_MRX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffffff00))
++#define SET_RG_MRX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffff00ff))
++#define SET_RG_MTX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff00ffff))
++#define SET_RG_MTX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ffffff))
++#define SET_RO_MTX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000))
++#define SET_RO_MTX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff))
++#define SET_RO_MRX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000))
++#define SET_RO_MRX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff))
++#define SET_RG_HB_COEF0(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xfffff000))
++#define SET_RG_HB_COEF1(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xf000ffff))
++#define SET_RG_HB_COEF2(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xfffff000))
++#define SET_RG_HB_COEF3(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xf000ffff))
++#define SET_RG_HB_COEF4(_VAL_) (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0xfffff000))
++#define SET_RO_TBUS_O(_VAL_) (REG32(ADR_PHY_READ_TBUS)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_TBUS)) & 0xfff00000))
++#define SET_RG_LPF4_00(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_00)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_00)) & 0xffffe000))
++#define SET_RG_LPF4_01(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_01)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_01)) & 0xffffe000))
++#define SET_RG_LPF4_02(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_02)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_02)) & 0xffffe000))
++#define SET_RG_LPF4_03(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_03)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_03)) & 0xffffe000))
++#define SET_RG_LPF4_04(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_04)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_04)) & 0xffffe000))
++#define SET_RG_LPF4_05(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_05)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_05)) & 0xffffe000))
++#define SET_RG_LPF4_06(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_06)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_06)) & 0xffffe000))
++#define SET_RG_LPF4_07(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_07)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_07)) & 0xffffe000))
++#define SET_RG_LPF4_08(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_08)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_08)) & 0xffffe000))
++#define SET_RG_LPF4_09(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_09)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_09)) & 0xffffe000))
++#define SET_RG_LPF4_10(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_10)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_10)) & 0xffffe000))
++#define SET_RG_LPF4_11(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_11)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_11)) & 0xffffe000))
++#define SET_RG_LPF4_12(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_12)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_12)) & 0xffffe000))
++#define SET_RG_LPF4_13(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_13)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_13)) & 0xffffe000))
++#define SET_RG_LPF4_14(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_14)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_14)) & 0xffffe000))
++#define SET_RG_LPF4_15(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_15)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_15)) & 0xffffe000))
++#define SET_RG_LPF4_16(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_16)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_16)) & 0xffffe000))
++#define SET_RG_LPF4_17(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_17)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_17)) & 0xffffe000))
++#define SET_RG_LPF4_18(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_18)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_18)) & 0xffffe000))
++#define SET_RG_LPF4_19(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_19)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_19)) & 0xffffe000))
++#define SET_RG_LPF4_20(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_20)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_20)) & 0xffffe000))
++#define SET_RG_LPF4_21(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_21)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_21)) & 0xffffe000))
++#define SET_RG_LPF4_22(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_22)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_22)) & 0xffffe000))
++#define SET_RG_LPF4_23(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_23)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_23)) & 0xffffe000))
++#define SET_RG_LPF4_24(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_24)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_24)) & 0xffffe000))
++#define SET_RG_LPF4_25(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_25)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_25)) & 0xffffe000))
++#define SET_RG_LPF4_26(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_26)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_26)) & 0xffffe000))
++#define SET_RG_LPF4_27(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_27)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_27)) & 0xffffe000))
++#define SET_RG_LPF4_28(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_28)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_28)) & 0xffffe000))
++#define SET_RG_LPF4_29(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_29)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_29)) & 0xffffe000))
++#define SET_RG_LPF4_30(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_30)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_30)) & 0xffffe000))
++#define SET_RG_LPF4_31(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_31)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_31)) & 0xffffe000))
++#define SET_RG_LPF4_32(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_32)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_32)) & 0xffffe000))
++#define SET_RG_LPF4_33(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_33)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_33)) & 0xffffe000))
++#define SET_RG_LPF4_34(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_34)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_34)) & 0xffffe000))
++#define SET_RG_LPF4_35(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_35)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_35)) & 0xffffe000))
++#define SET_RG_LPF4_36(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_36)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_36)) & 0xffffe000))
++#define SET_RG_LPF4_37(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_37)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_37)) & 0xffffe000))
++#define SET_RG_LPF4_38(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_38)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_38)) & 0xffffe000))
++#define SET_RG_LPF4_39(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_39)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_39)) & 0xffffe000))
++#define SET_RG_LPF4_40(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_40)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_40)) & 0xffffe000))
++#define SET_RG_BP_SMB(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 13) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffdfff))
++#define SET_RG_EN_SRVC(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 14) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffbfff))
++#define SET_RG_DES_SPD(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 16) | ((REG32(ADR_TX_11B_PLCP)) & 0xfffcffff))
++#define SET_RG_BB_11B_RISE_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_RAMP)) & 0xffffff00))
++#define SET_RG_BB_11B_FALL_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11B_RAMP)) & 0xffff00ff))
++#define SET_RG_WR_TX_EN_CNT_RST_N(_VAL_) (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0xfffffffe))
++#define SET_RO_TX_EN_CNT(_VAL_) (REG32(ADR_TX_11B_EN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT)) & 0xffff0000))
++#define SET_RO_TX_CNT(_VAL_) (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0x00000000))
++#define SET_RG_POS_DES_11B_L_EXT(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xfffffff0))
++#define SET_RG_PRE_DES_11B_DLY(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xffffff0f))
++#define SET_RG_CNT_CCA_LMT(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_0)) & 0xfff0ffff))
++#define SET_RG_BYPASS_DESCRAMBLER(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11B_CCA_0)) & 0xdfffffff))
++#define SET_RG_BYPASS_AGC(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11B_CCA_0)) & 0x7fffffff))
++#define SET_RG_CCA_BIT_CNT_LMT_RX(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CCA_1)) & 0xffffff0f))
++#define SET_RG_CCA_SCALE_BF(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_1)) & 0xff80ffff))
++#define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11B_CCA_1)) & 0xcfffffff))
++#define SET_RG_TR_KI_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffffff8))
++#define SET_RG_TR_KP_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffffff8f))
++#define SET_RG_TR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffff8ff))
++#define SET_RG_TR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffff8fff))
++#define SET_RG_CR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xfff8ffff))
++#define SET_RG_CR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xff8fffff))
++#define SET_RG_CHIP_CNT_SLICER(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffffffe0))
++#define SET_RG_CE_T4_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffff00ff))
++#define SET_RG_CE_T3_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff00ffff))
++#define SET_RG_CE_T2_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ffffff))
++#define SET_RG_CE_MU_T1(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xfffffff8))
++#define SET_RG_CE_DLY_SEL(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xffc0ffff))
++#define SET_RG_CE_MU_T8(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffffff8))
++#define SET_RG_CE_MU_T7(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffffff8f))
++#define SET_RG_CE_MU_T6(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffff8ff))
++#define SET_RG_CE_MU_T5(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffff8fff))
++#define SET_RG_CE_MU_T4(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfff8ffff))
++#define SET_RG_CE_MU_T3(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xff8fffff))
++#define SET_RG_CE_MU_T2(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xf8ffffff))
++#define SET_RG_EQ_MU_FB_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfffffff0))
++#define SET_RG_EQ_MU_FF_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xffffff0f))
++#define SET_RG_EQ_MU_FB_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfff0ffff))
++#define SET_RG_EQ_MU_FF_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xff0fffff))
++#define SET_RG_EQ_MU_FB_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfffffff0))
++#define SET_RG_EQ_MU_FF_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xffffff0f))
++#define SET_RG_EQ_MU_FB_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfff0ffff))
++#define SET_RG_EQ_MU_FF_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xff0fffff))
++#define SET_RG_EQ_KI_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfffff8ff))
++#define SET_RG_EQ_KP_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xffff8fff))
++#define SET_RG_EQ_KI_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfff8ffff))
++#define SET_RG_EQ_KP_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xff8fffff))
++#define SET_RG_TR_LPF_RATE(_VAL_) (REG32(ADR_RX_11B_LPF_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_LPF_RATE)) & 0xffc00000))
++#define SET_RG_CE_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff80))
++#define SET_RG_CE_CH_MAIN_SET(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff7f))
++#define SET_RG_TC_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffff80ff))
++#define SET_RG_CR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xff80ffff))
++#define SET_RG_TR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x80ffffff))
++#define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xfffffffe))
++#define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xf800ffff))
++#define SET_RG_PWRON_DLY_TH_11B(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xffffff00))
++#define SET_RG_SFD_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xff00ffff))
++#define SET_RG_CCA_PWR_TH_RX(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffff8000))
++#define SET_RG_CCA_PWR_CNT_TH(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffe0ffff))
++#define SET_B_FREQ_OS(_VAL_) (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0xfffff800))
++#define SET_B_SNR(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xffffff80))
++#define SET_B_RCPI(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xff80ffff))
++#define SET_CRC_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000))
++#define SET_SFD_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff))
++#define SET_B_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xffff0000))
++#define SET_PACKET_ERR(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xfffeffff))
++#define SET_B_PACKET_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
++#define SET_B_CCA_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
++#define SET_B_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000))
++#define SET_SFD_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff))
++#define SET_SIGNAL_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffffff00))
++#define SET_B_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffff00ff))
++#define SET_CRC_CORRECT(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xfffeffff))
++#define SET_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xfffffff0))
++#define SET_RG_PACKET_STAT_EN_11B(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffefffff))
++#define SET_RG_BIT_REVERSE(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffdfffff))
++#define SET_RX_PHY_11B_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffffffe))
++#define SET_RG_CE_BYPASS_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xffffff0f))
++#define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffff0ff))
++#define SET_RG_BB_11GN_RISE_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffffff00))
++#define SET_RG_BB_11GN_FALL_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffff00ff))
++#define SET_RG_HTCARR52_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP)) & 0xfffffc00))
++#define SET_RG_HTCARR56_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 12) | ((REG32(ADR_TX_11GN_PLCP)) & 0xffc00fff))
++#define SET_RG_PACKET_STAT_EN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 23) | ((REG32(ADR_TX_11GN_PLCP)) & 0xff7fffff))
++#define SET_RG_SMB_DEF(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 24) | ((REG32(ADR_TX_11GN_PLCP)) & 0x80ffffff))
++#define SET_RG_CONTINUOUS_DATA_11GN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 31) | ((REG32(ADR_TX_11GN_PLCP)) & 0x7fffffff))
++#define SET_RO_TX_CNT_R(_VAL_) (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0x00000000))
++#define SET_RO_PACKET_ERR_CNT(_VAL_) (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0xffff0000))
++#define SET_RG_POS_DES_11GN_L_EXT(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xfffffff0))
++#define SET_RG_PRE_DES_11GN_DLY(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xffffff0f))
++#define SET_RG_TR_LPF_KI_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfffffff0))
++#define SET_RG_TR_LPF_KP_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffffff0f))
++#define SET_RG_TR_CNT_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffff00ff))
++#define SET_RG_TR_LPF_KI_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfff0ffff))
++#define SET_RG_TR_LPF_KP_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TR_0)) & 0xff0fffff))
++#define SET_RG_TR_CNT_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_TR_0)) & 0x00ffffff))
++#define SET_RG_TR_LPF_KI_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_1)) & 0xfffffff0))
++#define SET_RG_TR_LPF_KP_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffffff0f))
++#define SET_RG_TR_CNT_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffff00ff))
++#define SET_RG_TR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_2)) & 0xfffffff0))
++#define SET_RG_TR_LPF_KP_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_2)) & 0xffffff0f))
++#define SET_RG_TR_LPF_RATE_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_2)) & 0xc00000ff))
++#define SET_RG_CR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xfffffff8))
++#define SET_RG_SYM_BOUND_CNT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xffff80ff))
++#define SET_RG_XSCOR32_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xff80ffff))
++#define SET_RG_ATCOR64_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_0)) & 0x80ffffff))
++#define SET_RG_ATCOR16_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xffff80ff))
++#define SET_RG_ATCOR16_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xff80ffff))
++#define SET_RG_ATCOR16_RATIO_SB(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_1)) & 0x80ffffff))
++#define SET_RG_XSCOR64_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_2)) & 0xff80ffff))
++#define SET_RG_XSCOR64_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_2)) & 0x80ffffff))
++#define SET_RG_RX_FFT_SCALE(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffffc00))
++#define SET_RG_VITERBI_AB_SWAP(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffeffff))
++#define SET_RG_ATCOR16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xf0ffffff))
++#define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffffff00))
++#define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffff00ff))
++#define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff00ffff))
++#define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_SNR_3(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffffff00))
++#define SET_RG_NORMSQUARE_SNR_2(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffff00ff))
++#define SET_RG_NORMSQUARE_SNR_1(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff00ffff))
++#define SET_RG_NORMSQUARE_SNR_0(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffffff00))
++#define SET_RG_NORMSQUARE_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffff00ff))
++#define SET_RG_NORMSQUARE_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff00ffff))
++#define SET_RG_NORMSQUARE_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0x00ffffff))
++#define SET_RG_SNR_TH_64QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffffff80))
++#define SET_RG_SNR_TH_16QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffff80ff))
++#define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffffff80))
++#define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffff80ff))
++#define SET_RG_SYM_BOUND_METHOD(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xfffcffff))
++#define SET_RG_PWRON_DLY_TH_11GN(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffffff00))
++#define SET_RG_SB_START_CNT(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffff80ff))
++#define SET_RG_POW16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xffffff0f))
++#define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xfffff8ff))
++#define SET_RG_POW16_TH_L(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0x80ffffff))
++#define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfffffff8))
++#define SET_RG_XSCOR16_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xffff80ff))
++#define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfff8ffff))
++#define SET_RG_ATCOR16_RATIO_CCD(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0x80ffffff))
++#define SET_RG_ATCOR64_ACC_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xffffff80))
++#define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xfff8ffff))
++#define SET_RG_VITERBI_TB_BITS(_VAL_) (REG32(ADR_RX_11GN_VTB_TB)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_VTB_TB)) & 0x00ffffff))
++#define SET_RG_CR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xffffff00))
++#define SET_RG_TR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xff00ffff))
++#define SET_RG_BYPASS_CPE_MA(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffffffef))
++#define SET_RG_PILOT_BNDRY_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfffff8ff))
++#define SET_RG_EQ_SHORT_GI_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffff8fff))
++#define SET_RG_FFT_WDW_SHORT_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfff8ffff))
++#define SET_RG_CHSMTH_COEF(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffcffff))
++#define SET_RG_CHSMTH_EN(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 18) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffbffff))
++#define SET_RG_CHEST_DD_FACTOR(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xf8ffffff))
++#define SET_RG_CH_UPDATE(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x7fffffff))
++#define SET_RG_FMT_DET_MM_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffffff00))
++#define SET_RG_FMT_DET_GF_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffff00ff))
++#define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xfdffffff))
++#define SET_RG_FMT_DET_LENGTH_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000))
++#define SET_RG_L_LENGTH_MAX(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff))
++#define SET_RG_TX_TIME_EXT(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xffffff00))
++#define SET_RG_MAC_DES_SPACE(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xff0fffff))
++#define SET_RG_TR_LPF_STBC_GF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffffff0))
++#define SET_RG_TR_LPF_STBC_GF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffffff0f))
++#define SET_RG_TR_LPF_STBC_MF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffff0ff))
++#define SET_RG_TR_LPF_STBC_MF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffff0fff))
++#define SET_RG_MODE_REG_IN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfffe0000))
++#define SET_RG_PARALLEL_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xffefffff))
++#define SET_RG_MBRUN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfeffffff))
++#define SET_RG_SHIFT_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xefffffff))
++#define SET_RG_MODE_REG_SI_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xdfffffff))
++#define SET_RG_SIMULATION_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xbfffffff))
++#define SET_RG_DBIST_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_0)) & 0x7fffffff))
++#define SET_RG_MODE_REG_IN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffff0000))
++#define SET_RG_PARALLEL_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffefffff))
++#define SET_RG_MBRUN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xfeffffff))
++#define SET_RG_SHIFT_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xefffffff))
++#define SET_RG_MODE_REG_SI_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xdfffffff))
++#define SET_RG_SIMULATION_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xbfffffff))
++#define SET_RG_DBIST_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_1)) & 0x7fffffff))
++#define SET_RO_MODE_REG_OUT_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfffe0000))
++#define SET_RO_MODE_REG_SO_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfeffffff))
++#define SET_RO_MONITOR_BUS_80(_VAL_) (REG32(ADR_RX_11GN_BIST_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_3)) & 0xffc00000))
++#define SET_RO_MODE_REG_OUT_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xffff0000))
++#define SET_RO_MODE_REG_SO_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xfeffffff))
++#define SET_RO_MONITOR_BUS_64(_VAL_) (REG32(ADR_RX_11GN_BIST_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_5)) & 0xfff80000))
++#define SET_RO_SPECTRUM_DATA(_VAL_) (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0x00000000))
++#define SET_GN_SNR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffffff80))
++#define SET_GN_NOISE_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffff80ff))
++#define SET_GN_RCPI(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_READ_0)) & 0xff80ffff))
++#define SET_GN_SIGNAL_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_READ_0)) & 0x80ffffff))
++#define SET_RO_FREQ_OS_LTS(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xffff8000))
++#define SET_CSTATE(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xfff0ffff))
++#define SET_SIGNAL_FIELD0(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0xff000000))
++#define SET_SIGNAL_FIELD1(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0xff000000))
++#define SET_GN_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0xffff0000))
++#define SET_GN_PACKET_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
++#define SET_GN_CCA_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
++#define SET_GN_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000))
++#define SET_GN_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff))
++#define SET_RO_HT_MCS_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffff80))
++#define SET_RO_L_RATE_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffc0ff))
++#define SET_RG_DAGC_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xfffffffc))
++#define SET_RG_PACKET_STAT_EN_11GN(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xffefffff))
++#define SET_RX_PHY_11GN_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffe))
++#define SET_RG_RIFS_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 1) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffd))
++#define SET_RG_STBC_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 2) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffb))
++#define SET_RG_COR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 3) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffff7))
++#define SET_RG_INI_PHASE(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffcf))
++#define SET_RG_HT_LTF_SEL_EQ(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 6) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffbf))
++#define SET_RG_HT_LTF_SEL_PILOT(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffff7f))
++#define SET_RG_CCA_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 9) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffdff))
++#define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 10) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffbff))
++#define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 11) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffff7ff))
++#define SET_RG_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffff0fff))
++#define SET_RG_POST_CLK_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffeffff))
++#define SET_IQCAL_RF_TX_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffe))
++#define SET_IQCAL_RF_TX_PA_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 1) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffd))
++#define SET_IQCAL_RF_TX_DAC_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 2) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffb))
++#define SET_IQCAL_RF_RX_AGC(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 3) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffff7))
++#define SET_IQCAL_RF_PGAG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffff0ff))
++#define SET_IQCAL_RF_RFG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 12) | ((REG32(ADR_RF_CONTROL_0)) & 0xffffcfff))
++#define SET_RG_TONEGEN_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_CONTROL_0)) & 0xff80ffff))
++#define SET_RG_TONEGEN_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 23) | ((REG32(ADR_RF_CONTROL_0)) & 0xff7fffff))
++#define SET_RG_TONEGEN_INIT_PH(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_CONTROL_0)) & 0x80ffffff))
++#define SET_RG_TONEGEN2_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff80))
++#define SET_RG_TONEGEN2_EN(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 7) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff7f))
++#define SET_RG_TONEGEN2_SCALE(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_1)) & 0xffff00ff))
++#define SET_RG_TXIQ_CLP_THD_I(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfffffc00))
++#define SET_RG_TXIQ_CLP_THD_Q(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfc00ffff))
++#define SET_RG_TX_I_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffffff00))
++#define SET_RG_TX_Q_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffff00ff))
++#define SET_RG_TX_IQ_SWP(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffeffff))
++#define SET_RG_TX_SGN_OUT(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 17) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffdffff))
++#define SET_RG_TXIQ_EMU_IDX(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 18) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffc3ffff))
++#define SET_RG_TX_IQ_SRC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfcffffff))
++#define SET_RG_TX_I_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfffffc00))
++#define SET_RG_TX_Q_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfc00ffff))
++#define SET_RG_TX_IQ_THETA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffffe0))
++#define SET_RG_TX_IQ_ALPHA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffe0ff))
++#define SET_RG_TXIQ_NOSHRINK(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffdfff))
++#define SET_RG_TX_I_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff00ffff))
++#define SET_RG_TX_Q_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 24) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ffffff))
++#define SET_RG_RX_IQ_THETA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffffe0))
++#define SET_RG_RX_IQ_ALPHA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffe0ff))
++#define SET_RG_RXIQ_NOSHRINK(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffdfff))
++#define SET_RG_MA_DPTH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffff0))
++#define SET_RG_INTG_PH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffc0f))
++#define SET_RG_INTG_PRD(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 10) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffffe3ff))
++#define SET_RG_INTG_MU(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 13) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffff9fff))
++#define SET_RG_IQCAL_SPRM_SELQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffeffff))
++#define SET_RG_IQCAL_SPRM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 17) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffdffff))
++#define SET_RG_IQCAL_SPRM_FREQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 18) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xff03ffff))
++#define SET_RG_IQCAL_IQCOL_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfeffffff))
++#define SET_RG_IQCAL_ALPHA_ESTM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfdffffff))
++#define SET_RG_IQCAL_DC_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfbffffff))
++#define SET_RG_PHEST_STBY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xf7ffffff))
++#define SET_RG_PHEST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xefffffff))
++#define SET_RG_GP_DIV_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xdfffffff))
++#define SET_RG_DPD_GAIN_EST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xbfffffff))
++#define SET_RG_IQCAL_MULT_OP0(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfffffc00))
++#define SET_RG_IQCAL_MULT_OP1(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfc00ffff))
++#define SET_RO_IQCAL_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfff00000))
++#define SET_RO_IQCAL_SPRM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 20) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffefffff))
++#define SET_RO_IQCAL_IQCOL_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 21) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffdfffff))
++#define SET_RO_IQCAL_ALPHA_ESTM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 22) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffbfffff))
++#define SET_RO_IQCAL_DC_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 23) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xff7fffff))
++#define SET_RO_IQCAL_MULT_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfeffffff))
++#define SET_RO_FFT_ENRG_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfdffffff))
++#define SET_RO_PHEST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfbffffff))
++#define SET_RO_GP_DIV_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xf7ffffff))
++#define SET_RO_GAIN_EST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xefffffff))
++#define SET_RO_AMP_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0xfffffe00))
++#define SET_RG_RX_I_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffffff00))
++#define SET_RG_RX_Q_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffff00ff))
++#define SET_RG_RX_I_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff00ffff))
++#define SET_RG_RX_Q_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ffffff))
++#define SET_RG_RX_IQ_SWP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffe))
++#define SET_RG_RX_SGN_IN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffd))
++#define SET_RG_RX_IQ_SRC(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 2) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffff3))
++#define SET_RG_ACI_GAIN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffff00f))
++#define SET_RG_FFT_EN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 12) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffefff))
++#define SET_RG_FFT_MOD(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 13) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffdfff))
++#define SET_RG_FFT_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 14) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xff003fff))
++#define SET_RG_FFT_ENRG_FREQ(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xc0ffffff))
++#define SET_RG_FPGA_80M_PH_UP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 30) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xbfffffff))
++#define SET_RG_FPGA_80M_PH_STP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 31) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0x7fffffff))
++#define SET_RG_ADC2LA_SEL(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffe))
++#define SET_RG_ADC2LA_CLKPH(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffd))
++#define SET_RG_RXIQ_EMU_IDX(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xfffffff0))
++#define SET_RG_IQCAL_BP_ACI(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xffffffef))
++#define SET_RG_DPD_AM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffe))
++#define SET_RG_DPD_PM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffd))
++#define SET_RG_DPD_PM_AMSEL(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffb))
++#define SET_RG_DPD_020_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfffffc00))
++#define SET_RG_DPD_040_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfc00ffff))
++#define SET_RG_DPD_060_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfffffc00))
++#define SET_RG_DPD_080_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfc00ffff))
++#define SET_RG_DPD_0A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfffffc00))
++#define SET_RG_DPD_0C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfc00ffff))
++#define SET_RG_DPD_0D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfffffc00))
++#define SET_RG_DPD_0E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfc00ffff))
++#define SET_RG_DPD_0F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfffffc00))
++#define SET_RG_DPD_100_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfc00ffff))
++#define SET_RG_DPD_110_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfffffc00))
++#define SET_RG_DPD_120_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfc00ffff))
++#define SET_RG_DPD_130_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfffffc00))
++#define SET_RG_DPD_140_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfc00ffff))
++#define SET_RG_DPD_150_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfffffc00))
++#define SET_RG_DPD_160_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfc00ffff))
++#define SET_RG_DPD_170_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfffffc00))
++#define SET_RG_DPD_180_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfc00ffff))
++#define SET_RG_DPD_190_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfffffc00))
++#define SET_RG_DPD_1A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfc00ffff))
++#define SET_RG_DPD_1B0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfffffc00))
++#define SET_RG_DPD_1C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfc00ffff))
++#define SET_RG_DPD_1D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfffffc00))
++#define SET_RG_DPD_1E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfc00ffff))
++#define SET_RG_DPD_1F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfffffc00))
++#define SET_RG_DPD_200_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfc00ffff))
++#define SET_RG_DPD_020_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xffffe000))
++#define SET_RG_DPD_040_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xe000ffff))
++#define SET_RG_DPD_060_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xffffe000))
++#define SET_RG_DPD_080_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xe000ffff))
++#define SET_RG_DPD_0A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xffffe000))
++#define SET_RG_DPD_0C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xe000ffff))
++#define SET_RG_DPD_0D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xffffe000))
++#define SET_RG_DPD_0E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xe000ffff))
++#define SET_RG_DPD_0F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xffffe000))
++#define SET_RG_DPD_100_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xe000ffff))
++#define SET_RG_DPD_110_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xffffe000))
++#define SET_RG_DPD_120_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xe000ffff))
++#define SET_RG_DPD_130_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xffffe000))
++#define SET_RG_DPD_140_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xe000ffff))
++#define SET_RG_DPD_150_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xffffe000))
++#define SET_RG_DPD_160_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xe000ffff))
++#define SET_RG_DPD_170_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xffffe000))
++#define SET_RG_DPD_180_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xe000ffff))
++#define SET_RG_DPD_190_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xffffe000))
++#define SET_RG_DPD_1A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xe000ffff))
++#define SET_RG_DPD_1B0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xffffe000))
++#define SET_RG_DPD_1C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xe000ffff))
++#define SET_RG_DPD_1D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xffffe000))
++#define SET_RG_DPD_1E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xe000ffff))
++#define SET_RG_DPD_1F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xffffe000))
++#define SET_RG_DPD_200_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xe000ffff))
++#define SET_RG_DPD_GAIN_EST_Y0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfffffe00))
++#define SET_RG_DPD_GAIN_EST_Y1(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfe00ffff))
++#define SET_RG_DPD_LOOP_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0xfffffc00))
++#define SET_RG_DPD_GAIN_EST_X0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfffffe00))
++#define SET_RO_DPD_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfc00ffff))
++#define SET_TX_SCALE_11B(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffffff00))
++#define SET_TX_SCALE_11B_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 8) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffff00ff))
++#define SET_TX_SCALE_11G(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xff00ffff))
++#define SET_TX_SCALE_11G_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 24) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ffffff))
++#define SET_RG_EN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
++#define SET_RG_TX_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
++#define SET_RG_TX_PA_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
++#define SET_RG_TX_DAC_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
++#define SET_RG_RX_AGC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
++#define SET_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
++#define SET_RG_RFG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
++#define SET_RG_PGAG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
++#define SET_RG_MODE(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
++#define SET_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
++#define SET_RG_EN_SX(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
++#define SET_RG_EN_RX_LNA(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
++#define SET_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
++#define SET_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
++#define SET_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
++#define SET_RG_EN_RX_TZ(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
++#define SET_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
++#define SET_RG_EN_RX_HPF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
++#define SET_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
++#define SET_RG_EN_ADC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
++#define SET_RG_EN_TX_MOD(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
++#define SET_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
++#define SET_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
++#define SET_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
++#define SET_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
++#define SET_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
++#define SET_RG_EN_CLK_960MBY13_UART(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x7fffffff))
++#define SET_RG_EN_TX_DPD(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
++#define SET_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
++#define SET_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
++#define SET_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
++#define SET_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
++#define SET_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
++#define SET_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
++#define SET_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
++#define SET_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
++#define SET_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
++#define SET_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
++#define SET_RG_EN_IREF_RX(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
++#define SET_RG_EN_TX_DAC_VOUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffdfff))
++#define SET_RG_EN_SX_LCK_BIN(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffbfff))
++#define SET_RG_RTC_CAL_MODE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffeffff))
++#define SET_RG_EN_IQPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffdffff))
++#define SET_RG_EN_TESTPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffbffff))
++#define SET_RG_EN_TRXBF_BYPASS(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfff7ffff))
++#define SET_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffff8))
++#define SET_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_LDO_REGISTER)) & 0xffffffc7))
++#define SET_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffe3f))
++#define SET_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_LDO_REGISTER)) & 0xfffff1ff))
++#define SET_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_LDO_REGISTER)) & 0xffff8fff))
++#define SET_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_LDO_REGISTER)) & 0xfffc7fff))
++#define SET_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_LDO_REGISTER)) & 0xffe3ffff))
++#define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_LDO_REGISTER)) & 0xff1fffff))
++#define SET_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_LDO_REGISTER)) & 0xf8ffffff))
++#define SET_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffe))
++#define SET_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffd))
++#define SET_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffb))
++#define SET_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffe07))
++#define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffdff))
++#define SET_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffbff))
++#define SET_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffff7ff))
++#define SET_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffffcfff))
++#define SET_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffff3fff))
++#define SET_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffcffff))
++#define SET_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfff3ffff))
++#define SET_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffcfffff))
++#define SET_RG_RX_HPF3M(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffbfffff))
++#define SET_RG_RX_HPF300K(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_1)) & 0xff7fffff))
++#define SET_RG_RX_HPFI(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfcffffff))
++#define SET_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_ABB_REGISTER_1)) & 0xf3ffffff))
++#define SET_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_ABB_REGISTER_1)) & 0xcfffffff))
++#define SET_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffffc))
++#define SET_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffff3))
++#define SET_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffffcf))
++#define SET_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffff3f))
++#define SET_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffcff))
++#define SET_RG_RX_OUTVCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffff3ff))
++#define SET_RG_RX_TZI(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffcfff))
++#define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffbfff))
++#define SET_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffe7fff))
++#define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfff1ffff))
++#define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffefffff))
++#define SET_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_ABB_REGISTER_2)) & 0xff9fffff))
++#define SET_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfe7fffff))
++#define SET_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfdffffff))
++#define SET_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffffffc))
++#define SET_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffff03))
++#define SET_RG_TXPGA_STEER(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffc0ff))
++#define SET_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffff3fff))
++#define SET_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffcffff))
++#define SET_RG_PACELL_EN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffe3ffff))
++#define SET_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfe1fffff))
++#define SET_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_TX_FE_REGISTER)) & 0xf3ffffff))
++#define SET_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_TX_FE_REGISTER)) & 0xcfffffff))
++#define SET_RG_RX_SQDC(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffffff8))
++#define SET_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffffe7))
++#define SET_RG_RX_LOBUF(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffff9f))
++#define SET_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffff87f))
++#define SET_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffff87ff))
++#define SET_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffc7fff))
++#define SET_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffe3ffff))
++#define SET_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffdfffff))
++#define SET_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xff3fffff))
++#define SET_RG_PACASCODE_CTRL(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xf8ffffff))
++#define SET_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
++#define SET_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
++#define SET_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
++#define SET_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
++#define SET_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
++#define SET_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
++#define SET_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
++#define SET_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
++#define SET_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
++#define SET_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
++#define SET_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
++#define SET_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
++#define SET_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
++#define SET_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
++#define SET_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
++#define SET_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
++#define SET_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
++#define SET_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
++#define SET_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
++#define SET_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
++#define SET_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
++#define SET_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
++#define SET_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
++#define SET_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
++#define SET_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffe))
++#define SET_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffd))
++#define SET_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffb))
++#define SET_RG_HPF_T1A(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffffe7))
++#define SET_RG_HPF_T1B(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffff9f))
++#define SET_RG_HPF_T1C(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffe7f))
++#define SET_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffff9ff))
++#define SET_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffe7ff))
++#define SET_RG_TXGAIN_PHYCTRL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffdfff))
++#define SET_RG_TX_GAIN(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffc03fff))
++#define SET_RG_TXGAIN_MANUAL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffbfffff))
++#define SET_RG_TX_GAIN_OFFSET(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xf87fffff))
++#define SET_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffffe))
++#define SET_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff9))
++#define SET_RG_ADC_DIVR(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff7))
++#define SET_RG_ADC_DVCMI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffffffcf))
++#define SET_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffc3f))
++#define SET_RG_ADC_STNBY(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffbff))
++#define SET_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffff7ff))
++#define SET_RG_ADC_TSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffff0fff))
++#define SET_RG_ADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffcffff))
++#define SET_RG_DICMP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfff3ffff))
++#define SET_RG_DIOP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffcfffff))
++#define SET_RG_SARADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xff3fffff))
++#define SET_RG_EN_SAR_TEST(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfcffffff))
++#define SET_RG_SARADC_THERMAL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfbffffff))
++#define SET_RG_SARADC_TSSI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xf7ffffff))
++#define SET_RG_CLK_SAR_SEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xcfffffff))
++#define SET_RG_EN_SARADC(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xbfffffff))
++#define SET_RG_DACI1ST(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffffc))
++#define SET_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffff3))
++#define SET_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffffcf))
++#define SET_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffff3f))
++#define SET_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffeff))
++#define SET_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffff9ff))
++#define SET_RG_TX_DAC_OS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffc7ff))
++#define SET_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffff3fff))
++#define SET_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfff0ffff))
++#define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffefffff))
++#define SET_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffdfffff))
++#define SET_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffbfffff))
++#define SET_RG_TX_DAC_IOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xf87fffff))
++#define SET_RG_TX_DAC_QOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_TX_DAC_REGISTER)) & 0x87ffffff))
++#define SET_RG_EN_SX_R3(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffe))
++#define SET_RG_EN_SX_CH(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffd))
++#define SET_RG_EN_SX_CHP(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffb))
++#define SET_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffff7))
++#define SET_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffef))
++#define SET_RG_EN_SX_VCO(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffdf))
++#define SET_RG_EN_SX_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffbf))
++#define SET_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffeff))
++#define SET_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffff7ff))
++#define SET_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffefff))
++#define SET_RG_EN_SX_DIV(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffdfff))
++#define SET_RG_EN_SX_LPF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffbfff))
++#define SET_RG_EN_DPL_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffff7fff))
++#define SET_RG_DPL_MOD_ORDER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffcffff))
++#define SET_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_1)) & 0xff000000))
++#define SET_RG_SX_SEL_CP(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_REGISTER_1)) & 0xf0ffffff))
++#define SET_RG_SX_SEL_CS(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_REGISTER_1)) & 0x0fffffff))
++#define SET_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfffff800))
++#define SET_RG_SX_SEL_C3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_REGISTER_2)) & 0xffff87ff))
++#define SET_RG_SX_SEL_RS(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfff07fff))
++#define SET_RG_SX_SEL_R3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfe0fffff))
++#define SET_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffffe0))
++#define SET_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffffc1f))
++#define SET_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffc3ff))
++#define SET_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffc3fff))
++#define SET_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffbffff))
++#define SET_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffc7ffff))
++#define SET_RG_SX_PFDSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffbfffff))
++#define SET_RG_SX_PFD_SET(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_SYN_PFD_CHP)) & 0xff7fffff))
++#define SET_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfeffffff))
++#define SET_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfdffffff))
++#define SET_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfbffffff))
++#define SET_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_SYN_PFD_CHP)) & 0xf7ffffff))
++#define SET_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_PFD_CHP)) & 0xefffffff))
++#define SET_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_SYN_PFD_CHP)) & 0xdfffffff))
++#define SET_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_SYN_PFD_CHP)) & 0xbfffffff))
++#define SET_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffffff8))
++#define SET_RG_SX_VCORSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffffff07))
++#define SET_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffff0ff))
++#define SET_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffff0fff))
++#define SET_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfff0ffff))
++#define SET_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xff0fffff))
++#define SET_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xf0ffffff))
++#define SET_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_VCO_LOBF)) & 0x0fffffff))
++#define SET_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
++#define SET_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
++#define SET_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
++#define SET_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
++#define SET_RG_SX_XO_GM(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
++#define SET_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
++#define SET_RG_SX_LCKEN(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
++#define SET_RG_SX_PREVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
++#define SET_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
++#define SET_RG_SX_PH(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffdfff))
++#define SET_RG_SX_PL(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffbfff))
++#define SET_RG_XOSC_CBANK_XO(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xfff87fff))
++#define SET_RG_XOSC_CBANK_XI(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xff87ffff))
++#define SET_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffffe))
++#define SET_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 1) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffff9))
++#define SET_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffe7))
++#define SET_RG_SX_VT_SET(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffdf))
++#define SET_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 6) | ((REG32(ADR_SYN_LCK_VT)) & 0xffff803f))
++#define SET_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffffe))
++#define SET_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffff9))
++#define SET_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffffe7))
++#define SET_RG_DP_CK320BY2(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffbfff))
++#define SET_RG_DP_OD_TEST(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffdfffff))
++#define SET_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
++#define SET_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
++#define SET_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
++#define SET_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
++#define SET_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
++#define SET_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
++#define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
++#define SET_RG_DP_RP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
++#define SET_RG_DP_RHP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
++#define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x7fffffff))
++#define SET_RG_DP_FODIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xfff80fff))
++#define SET_RG_DP_REFDIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xe03fffff))
++#define SET_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
++#define SET_RG_DP_BBPLL_BS(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 24) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xc0ffffff))
++#define SET_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
++#define SET_RG_EN_RCAL(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffe))
++#define SET_RG_RCAL_SPD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffd))
++#define SET_RG_RCAL_TMR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffe03))
++#define SET_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffdff))
++#define SET_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RCAL_REGISTER)) & 0xffff83ff))
++#define SET_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfffffffe))
++#define SET_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 1) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffffff01))
++#define SET_RG_SX_LCK_BIN_OFFSET(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff87fff))
++#define SET_RG_SX_LCK_BIN_PRECISION(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 19) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff7ffff))
++#define SET_RG_SX_LOCK_EN_N(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 20) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffefffff))
++#define SET_RG_SX_LOCK_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 21) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffdfffff))
++#define SET_RG_SX_SUB_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 22) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffbfffff))
++#define SET_RG_SX_SUB_SEL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xc07fffff))
++#define SET_RG_SX_MUX_SEL_VTH_BINL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 30) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xbfffffff))
++#define SET_RG_TRX_DUMMMY(_VAL_) (REG32(ADR_TRX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_DUMMY_REGISTER)) & 0x00000000))
++#define SET_RG_SX_DUMMMY(_VAL_) (REG32(ADR_SX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_DUMMY_REGISTER)) & 0x00000000))
++#define SET_RCAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
++#define SET_LCK_BIN_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
++#define SET_VT_MON_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
++#define SET_DA_R_CODE_LUT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
++#define SET_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
++#define SET_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
++#define SET_RTC_CAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 15) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff7fff))
++#define SET_RG_SARADC_BIT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 16) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffc0ffff))
++#define SET_SAR_ADC_FSM_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 22) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffbfffff))
++#define SET_AD_CIRCUIT_VERSION(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 23) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xf87fffff))
++#define SET_DA_R_CAL_CODE(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
++#define SET_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
++#define SET_RG_DPL_RFCTRL_CH(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xfffff800))
++#define SET_RG_RSSIADC_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 11) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xffff87ff))
++#define SET_RG_RX_ADC_I_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xff807fff))
++#define SET_RG_RX_ADC_Q_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x807fffff))
++#define SET_RG_DPL_RFCTRL_F(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0xff000000))
++#define SET_RG_SX_TARGET_CNT(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0xffffe000))
++#define SET_RG_RTC_OFFSET(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 0) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xffffff00))
++#define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 8) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xfff000ff))
++#define SET_RG_RF_D_REG(_VAL_) (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0xffff0000))
++#define SET_DIRECT_MODE(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffe))
++#define SET_TAG_INTERLEAVE_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffd))
++#define SET_DIS_DEMAND(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffb))
++#define SET_SAME_ID_ALLOC_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_MMU_CTRL)) & 0xfffffff7))
++#define SET_HS_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_MMU_CTRL)) & 0xffffffef))
++#define SET_SRAM_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 5) | ((REG32(ADR_MMU_CTRL)) & 0xffffffdf))
++#define SET_NOHIT_RPASS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 6) | ((REG32(ADR_MMU_CTRL)) & 0xffffffbf))
++#define SET_DMN_FLAG_CLR(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_MMU_CTRL)) & 0xffffff7f))
++#define SET_ERR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_CTRL)) & 0xfffffeff))
++#define SET_ALR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_MMU_CTRL)) & 0xfffffdff))
++#define SET_MCH_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_MMU_CTRL)) & 0xfffffbff))
++#define SET_TAG_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_MMU_CTRL)) & 0xfffff7ff))
++#define SET_ABT_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_CTRL)) & 0xffffefff))
++#define SET_MMU_VER(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_MMU_CTRL)) & 0xffff1fff))
++#define SET_MMU_SHARE_MCU(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_CTRL)) & 0xff00ffff))
++#define SET_HS_WR(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_HS_CTRL)) & 0xfffffffe))
++#define SET_HS_FLAG(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_HS_CTRL)) & 0xffffffef))
++#define SET_HS_ID(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_HS_CTRL)) & 0xffff80ff))
++#define SET_HS_CHANNEL(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_HS_CTRL)) & 0xfff0ffff))
++#define SET_HS_PAGE(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 20) | ((REG32(ADR_HS_CTRL)) & 0xff0fffff))
++#define SET_HS_DATA(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 24) | ((REG32(ADR_HS_CTRL)) & 0x00ffffff))
++#define SET_CPU_POR0(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR0_7)) & 0xfffffff0))
++#define SET_CPU_POR1(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR0_7)) & 0xffffff0f))
++#define SET_CPU_POR2(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR0_7)) & 0xfffff0ff))
++#define SET_CPU_POR3(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR0_7)) & 0xffff0fff))
++#define SET_CPU_POR4(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR0_7)) & 0xfff0ffff))
++#define SET_CPU_POR5(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR0_7)) & 0xff0fffff))
++#define SET_CPU_POR6(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR0_7)) & 0xf0ffffff))
++#define SET_CPU_POR7(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR0_7)) & 0x0fffffff))
++#define SET_CPU_POR8(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR8_F)) & 0xfffffff0))
++#define SET_CPU_POR9(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR8_F)) & 0xffffff0f))
++#define SET_CPU_PORA(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR8_F)) & 0xfffff0ff))
++#define SET_CPU_PORB(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR8_F)) & 0xffff0fff))
++#define SET_CPU_PORC(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR8_F)) & 0xfff0ffff))
++#define SET_CPU_PORD(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR8_F)) & 0xff0fffff))
++#define SET_CPU_PORE(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR8_F)) & 0xf0ffffff))
++#define SET_CPU_PORF(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR8_F)) & 0x0fffffff))
++#define SET_ACC_WR_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffffc0))
++#define SET_ACC_RD_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffc0ff))
++#define SET_REQ_NACK_CLR(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 15) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffff7fff))
++#define SET_NACK_FLAG_BUS(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_REG_LEN_CTRL)) & 0x0000ffff))
++#define SET_DMN_R_PASS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xffff0000))
++#define SET_PARA_ALC_RLS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfffeffff))
++#define SET_REQ_PORNS_CHGEN(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 24) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfeffffff))
++#define SET_ALC_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffffff80))
++#define SET_ALC_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffff7fff))
++#define SET_RLS_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xff80ffff))
++#define SET_RLS_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_RLS_ABORT)) & 0x7fffffff))
++#define SET_DEBUG_CTL(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_CTL)) & 0xffffff00))
++#define SET_DEBUG_H16(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_DEBUG_CTL)) & 0xfffffeff))
++#define SET_DEBUG_OUT(_VAL_) (REG32(ADR_DEBUG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_OUT)) & 0x00000000))
++#define SET_ALC_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffe))
++#define SET_RLS_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffd))
++#define SET_AL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_STATUS)) & 0xfffff8ff))
++#define SET_RL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_STATUS)) & 0xffff8fff))
++#define SET_ALC_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_STATUS)) & 0xff80ffff))
++#define SET_RLS_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MMU_STATUS)) & 0x80ffffff))
++#define SET_DMN_NOHIT_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffe))
++#define SET_DMN_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffd))
++#define SET_DMN_WR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_STATUS)) & 0xfffffff7))
++#define SET_DMN_PORT(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_STATUS)) & 0xffffff0f))
++#define SET_DMN_NHIT_ID(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_STATUS)) & 0xffff80ff))
++#define SET_DMN_NHIT_ADDR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_STATUS)) & 0x0000ffff))
++#define SET_TX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_STATUS)) & 0xffffff00))
++#define SET_RX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TAG_STATUS)) & 0xffff00ff))
++#define SET_AVA_TAG(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_STATUS)) & 0xfe00ffff))
++#define SET_PKTBUF_FULL(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 31) | ((REG32(ADR_TAG_STATUS)) & 0x7fffffff))
++#define SET_DMN_NOHIT_MCU(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffe))
++#define SET_DMN_MCU_FLAG(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffd))
++#define SET_DMN_MCU_WR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffff7))
++#define SET_DMN_MCU_PORT(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffffff0f))
++#define SET_DMN_MCU_ID(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffff80ff))
++#define SET_DMN_MCU_ADDR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_MCU_STATUS)) & 0x0000ffff))
++#define SET_MB_IDTBL_31_0(_VAL_) (REG32(ADR_MB_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_0_STATUS)) & 0x00000000))
++#define SET_MB_IDTBL_63_32(_VAL_) (REG32(ADR_MB_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_1_STATUS)) & 0x00000000))
++#define SET_MB_IDTBL_95_64(_VAL_) (REG32(ADR_MB_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_2_STATUS)) & 0x00000000))
++#define SET_MB_IDTBL_127_96(_VAL_) (REG32(ADR_MB_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_3_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_31_0(_VAL_) (REG32(ADR_PKT_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_63_32(_VAL_) (REG32(ADR_PKT_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_95_64(_VAL_) (REG32(ADR_PKT_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_127_96(_VAL_) (REG32(ADR_PKT_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_31_0(_VAL_) (REG32(ADR_DMN_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_63_32(_VAL_) (REG32(ADR_DMN_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_95_64(_VAL_) (REG32(ADR_DMN_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_127_96(_VAL_) (REG32(ADR_DMN_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_31_0(_VAL_) (REG32(ADR_MB_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_0_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_63_32(_VAL_) (REG32(ADR_MB_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_1_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_95_64(_VAL_) (REG32(ADR_MB_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_2_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_127_96(_VAL_) (REG32(ADR_MB_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_3_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_31_0(_VAL_) (REG32(ADR_PKT_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_0_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_63_32(_VAL_) (REG32(ADR_PKT_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_1_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_95_64(_VAL_) (REG32(ADR_PKT_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_2_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_127_96(_VAL_) (REG32(ADR_PKT_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_3_STATUS)) & 0x00000000))
++#define SET_ALC_NOCHG_ID(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffffff80))
++#define SET_ALC_NOCHG_INT(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffff7fff))
++#define SET_NEQ_PKT_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfffeffff))
++#define SET_NEQ_MB_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfeffffff))
++#define SET_SRAM_TAG_0(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000))
++#define SET_SRAM_TAG_1(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff))
++#define SET_SRAM_TAG_2(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000))
++#define SET_SRAM_TAG_3(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff))
++#define SET_SRAM_TAG_4(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000))
++#define SET_SRAM_TAG_5(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff))
++#define SET_SRAM_TAG_6(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000))
++#define SET_SRAM_TAG_7(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff))
++#define SET_SRAM_TAG_8(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000))
++#define SET_SRAM_TAG_9(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff))
++#define SET_SRAM_TAG_10(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000))
++#define SET_SRAM_TAG_11(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff))
++#define SET_SRAM_TAG_12(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000))
++#define SET_SRAM_TAG_13(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff))
++#define SET_SRAM_TAG_14(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000))
++#define SET_SRAM_TAG_15(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff))
++#define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000)
++#define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000)
++#define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x31333131)
++#define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x322d3230)
++#define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x32303041)
++#define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636)
++#define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000000)
++#define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x008fffff)
++#define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000400)
++#define DEF_MCU_DBG_SEL() (REG32(ADR_MCU_DBG_SEL)) = (0x00000000)
++#define DEF_MCU_DBG_DATA() (REG32(ADR_MCU_DBG_DATA)) = (0x00000000)
++#define DEF_AHB_BRG_STATUS() (REG32(ADR_AHB_BRG_STATUS)) = (0x00000000)
++#define DEF_BIST_BIST_CTRL() (REG32(ADR_BIST_BIST_CTRL)) = (0x00000000)
++#define DEF_BIST_MODE_REG_IN() (REG32(ADR_BIST_MODE_REG_IN)) = (0x001ffe3e)
++#define DEF_BIST_MODE_REG_OUT() (REG32(ADR_BIST_MODE_REG_OUT)) = (0x00000000)
++#define DEF_BIST_MONITOR_BUS_LSB() (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (0x00000000)
++#define DEF_BIST_MONITOR_BUS_MSB() (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (0x00000000)
++#define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000)
++#define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000)
++#define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000)
++#define DEF_AHB_ILL_ADDR() (REG32(ADR_AHB_ILL_ADDR)) = (0x00000000)
++#define DEF_AHB_FEN_ADDR() (REG32(ADR_AHB_FEN_ADDR)) = (0x00000000)
++#define DEF_AHB_ILLFEN_STATUS() (REG32(ADR_AHB_ILLFEN_STATUS)) = (0x00000000)
++#define DEF_PWM_A() (REG32(ADR_PWM_A)) = (0x400a1010)
++#define DEF_PWM_B() (REG32(ADR_PWM_B)) = (0x400a1010)
++#define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd)
++#define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000)
++#define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028)
++#define DEF_BIST_MODE_REG_IN_MMU() (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (0x0000fe3e)
++#define DEF_BIST_MODE_REG_OUT_MMU() (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (0x00000000)
++#define DEF_BIST_MONITOR_BUS_MMU() (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (0x00000000)
++#define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000)
++#define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000)
++#define DEF_SD_INIT_CFG() (REG32(ADR_SD_INIT_CFG)) = (0x00000000)
++#define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000)
++#define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU0_DUMMY_BIT_0() (REG32(ADR_TU0_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU0_DUMMY_BIT_1() (REG32(ADR_TU0_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU1_DUMMY_BIT_0() (REG32(ADR_TU1_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU1_DUMMY_BIT_1() (REG32(ADR_TU1_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU2_DUMMY_BIT_0() (REG32(ADR_TU2_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU2_DUMMY_BIT_1() (REG32(ADR_TU2_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU3_DUMMY_BIT_0() (REG32(ADR_TU3_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU3_DUMMY_BIT_1() (REG32(ADR_TU3_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM0_MILISECOND_TIMER() (REG32(ADR_TM0_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM0_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM0_DUMMY_BIT_0() (REG32(ADR_TM0_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM0_DUMMY_BIT_1() (REG32(ADR_TM0_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM1_MILISECOND_TIMER() (REG32(ADR_TM1_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM1_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM1_DUMMY_BIT_0() (REG32(ADR_TM1_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM1_DUMMY_BIT_1() (REG32(ADR_TM1_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM2_MILISECOND_TIMER() (REG32(ADR_TM2_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM2_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM2_DUMMY_BIT_0() (REG32(ADR_TM2_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM2_DUMMY_BIT_1() (REG32(ADR_TM2_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM3_MILISECOND_TIMER() (REG32(ADR_TM3_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM3_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM3_DUMMY_BIT_0() (REG32(ADR_TM3_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM3_DUMMY_BIT_1() (REG32(ADR_TM3_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00000000)
++#define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00000000)
++#define DEF_PAD6() (REG32(ADR_PAD6)) = (0x00000008)
++#define DEF_PAD7() (REG32(ADR_PAD7)) = (0x00000008)
++#define DEF_PAD8() (REG32(ADR_PAD8)) = (0x00000008)
++#define DEF_PAD9() (REG32(ADR_PAD9)) = (0x00000008)
++#define DEF_PAD11() (REG32(ADR_PAD11)) = (0x00000008)
++#define DEF_PAD15() (REG32(ADR_PAD15)) = (0x0000000a)
++#define DEF_PAD16() (REG32(ADR_PAD16)) = (0x0000000a)
++#define DEF_PAD17() (REG32(ADR_PAD17)) = (0x0000000a)
++#define DEF_PAD18() (REG32(ADR_PAD18)) = (0x0000000a)
++#define DEF_PAD19() (REG32(ADR_PAD19)) = (0x00007000)
++#define DEF_PAD20() (REG32(ADR_PAD20)) = (0x0000000a)
++#define DEF_PAD21() (REG32(ADR_PAD21)) = (0x0000000a)
++#define DEF_PAD22() (REG32(ADR_PAD22)) = (0x00000009)
++#define DEF_PAD24() (REG32(ADR_PAD24)) = (0x00000008)
++#define DEF_PAD25() (REG32(ADR_PAD25)) = (0x0000000b)
++#define DEF_PAD27() (REG32(ADR_PAD27)) = (0x00000008)
++#define DEF_PAD28() (REG32(ADR_PAD28)) = (0x00000008)
++#define DEF_PAD29() (REG32(ADR_PAD29)) = (0x00000009)
++#define DEF_PAD30() (REG32(ADR_PAD30)) = (0x0000000a)
++#define DEF_PAD31() (REG32(ADR_PAD31)) = (0x0000000a)
++#define DEF_PAD32() (REG32(ADR_PAD32)) = (0x0000000a)
++#define DEF_PAD33() (REG32(ADR_PAD33)) = (0x0000000a)
++#define DEF_PAD34() (REG32(ADR_PAD34)) = (0x0000000a)
++#define DEF_PAD42() (REG32(ADR_PAD42)) = (0x0000000a)
++#define DEF_PAD43() (REG32(ADR_PAD43)) = (0x0000000a)
++#define DEF_PAD44() (REG32(ADR_PAD44)) = (0x0000000a)
++#define DEF_PAD45() (REG32(ADR_PAD45)) = (0x0000000a)
++#define DEF_PAD46() (REG32(ADR_PAD46)) = (0x0000000a)
++#define DEF_PAD47() (REG32(ADR_PAD47)) = (0x00100000)
++#define DEF_PAD48() (REG32(ADR_PAD48)) = (0x00100808)
++#define DEF_PAD49() (REG32(ADR_PAD49)) = (0x00100008)
++#define DEF_PAD50() (REG32(ADR_PAD50)) = (0x00100008)
++#define DEF_PAD51() (REG32(ADR_PAD51)) = (0x00100008)
++#define DEF_PAD52() (REG32(ADR_PAD52)) = (0x00100000)
++#define DEF_PAD53() (REG32(ADR_PAD53)) = (0x0000000a)
++#define DEF_PAD54() (REG32(ADR_PAD54)) = (0x00000000)
++#define DEF_PAD56() (REG32(ADR_PAD56)) = (0x00000000)
++#define DEF_PAD57() (REG32(ADR_PAD57)) = (0x00000008)
++#define DEF_PAD58() (REG32(ADR_PAD58)) = (0x0000000a)
++#define DEF_PAD59() (REG32(ADR_PAD59)) = (0x0000000a)
++#define DEF_PAD60() (REG32(ADR_PAD60)) = (0x0000000a)
++#define DEF_PAD61() (REG32(ADR_PAD61)) = (0x0000000a)
++#define DEF_PAD62() (REG32(ADR_PAD62)) = (0x0000000a)
++#define DEF_PAD64() (REG32(ADR_PAD64)) = (0x00000009)
++#define DEF_PAD65() (REG32(ADR_PAD65)) = (0x00000009)
++#define DEF_PAD66() (REG32(ADR_PAD66)) = (0x00000008)
++#define DEF_PAD68() (REG32(ADR_PAD68)) = (0x00000008)
++#define DEF_PAD67() (REG32(ADR_PAD67)) = (0x00000159)
++#define DEF_PAD69() (REG32(ADR_PAD69)) = (0x0000000b)
++#define DEF_PAD70() (REG32(ADR_PAD70)) = (0x00000008)
++#define DEF_PAD231() (REG32(ADR_PAD231)) = (0x00000008)
++#define DEF_PIN_SEL_0() (REG32(ADR_PIN_SEL_0)) = (0x00000000)
++#define DEF_PIN_SEL_1() (REG32(ADR_PIN_SEL_1)) = (0x00000000)
++#define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000)
++#define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff)
++#define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000)
++#define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000)
++#define DEF_CARD_PKT_STATUS_TEST() (REG32(ADR_CARD_PKT_STATUS_TEST)) = (0x00000000)
++#define DEF_SYSTEM_INFORMATION_REG() (REG32(ADR_SYSTEM_INFORMATION_REG)) = (0x00000000)
++#define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000)
++#define DEF_SDIO_FIFO_WR_THLD_REG() (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (0x00000000)
++#define DEF_SDIO_FIFO_WR_LIMIT_REG() (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (0x00000000)
++#define DEF_SDIO_TX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (0x00000000)
++#define DEF_SDIO_THLD_FOR_CMD53RD_REG() (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (0x00000000)
++#define DEF_SDIO_RX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (0x00000000)
++#define DEF_SDIO_LOG_START_END_DATA_REG() (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (0x00000000)
++#define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000)
++#define DEF_SDIO_LAST_CMD_INDEX_CRC_REG() (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (0x00000000)
++#define DEF_SDIO_LAST_CMD_ARG_REG() (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (0x00000000)
++#define DEF_SDIO_BUS_STATE_DEBUG_MONITOR() (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (0x00000000)
++#define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000)
++#define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00000000)
++#define DEF_CMD52_DATA_FOR_LAST_TIME() (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (0x00000000)
++#define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000)
++#define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000)
++#define DEF_IO_REG_PORT_REG() (REG32(ADR_IO_REG_PORT_REG)) = (0x00010020)
++#define DEF_SDIO_FIFO_ERROR_CNT() (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (0x00000000)
++#define DEF_SDIO_CRC7_CRC16_ERROR_REG() (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (0x00000000)
++#define DEF_SDIO_BLOCK_CNT_INFO() (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (0x00000000)
++#define DEF_RX_DATA_CMD52_ABORT_COUNT() (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (0x00000000)
++#define DEF_FIFO_PTR_READ_BLOCK_CNT() (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (0x00000000)
++#define DEF_TX_TIME_OUT_READ_CTRL() (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (0x00000000)
++#define DEF_SDIO_TX_ALLOC_REG() (REG32(ADR_SDIO_TX_ALLOC_REG)) = (0x00000000)
++#define DEF_SDIO_TX_INFORM() (REG32(ADR_SDIO_TX_INFORM)) = (0x00000000)
++#define DEF_F1_BLOCK_SIZE_0_REG() (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (0x00000000)
++#define DEF_SDIO_COMMAND_LOG_DATA_31_0() (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (0x000000ec)
++#define DEF_SDIO_COMMAND_LOG_DATA_63_32() (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (0xce000000)
++#define DEF_SYSTEM_INFORMATION_REGISTER() (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (0x00000000)
++#define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000)
++#define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000)
++#define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000)
++#define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x00000000)
++#define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000)
++#define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000)
++#define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000)
++#define DEF_RX_QUOTA() (REG32(ADR_RX_QUOTA)) = (0x00000000)
++#define DEF_CONDITION_NUMBER() (REG32(ADR_CONDITION_NUMBER)) = (0x00000004)
++#define DEF_HOST_PATH() (REG32(ADR_HOST_PATH)) = (0x00000001)
++#define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000)
++#define DEF_DEBUG_BURST_MODE() (REG32(ADR_DEBUG_BURST_MODE)) = (0x00000000)
++#define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006)
++#define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e)
++#define DEF_SPI_STS() (REG32(ADR_SPI_STS)) = (0x00000000)
++#define DEF_TX_ALLOC_SET() (REG32(ADR_TX_ALLOC_SET)) = (0x00000000)
++#define DEF_TX_ALLOC() (REG32(ADR_TX_ALLOC)) = (0x00000000)
++#define DEF_DBG_CNT() (REG32(ADR_DBG_CNT)) = (0x00000000)
++#define DEF_DBG_CNT2() (REG32(ADR_DBG_CNT2)) = (0x00000000)
++#define DEF_DBG_CNT3() (REG32(ADR_DBG_CNT3)) = (0x00000000)
++#define DEF_DBG_CNT4() (REG32(ADR_DBG_CNT4)) = (0x00000000)
++#define DEF_INT_TAG() (REG32(ADR_INT_TAG)) = (0x00000000)
++#define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x00000074)
++#define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000)
++#define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000)
++#define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000)
++#define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000)
++#define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000)
++#define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000)
++#define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000)
++#define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001)
++#define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003)
++#define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000)
++#define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000)
++#define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000)
++#define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x00000000)
++#define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8)
++#define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1)
++#define DEF_DAT_UART_DATA() (REG32(ADR_DAT_UART_DATA)) = (0x00000000)
++#define DEF_DAT_UART_IER() (REG32(ADR_DAT_UART_IER)) = (0x00000000)
++#define DEF_DAT_UART_FCR() (REG32(ADR_DAT_UART_FCR)) = (0x00000001)
++#define DEF_DAT_UART_LCR() (REG32(ADR_DAT_UART_LCR)) = (0x00000003)
++#define DEF_DAT_UART_MCR() (REG32(ADR_DAT_UART_MCR)) = (0x00000000)
++#define DEF_DAT_UART_LSR() (REG32(ADR_DAT_UART_LSR)) = (0x00000000)
++#define DEF_DAT_UART_MSR() (REG32(ADR_DAT_UART_MSR)) = (0x00000000)
++#define DEF_DAT_UART_SPR() (REG32(ADR_DAT_UART_SPR)) = (0x00000000)
++#define DEF_DAT_UART_RTHR() (REG32(ADR_DAT_UART_RTHR)) = (0x000000c8)
++#define DEF_DAT_UART_ISR() (REG32(ADR_DAT_UART_ISR)) = (0x000000c1)
++#define DEF_INT_MASK() (REG32(ADR_INT_MASK)) = (0xffffffff)
++#define DEF_INT_MODE() (REG32(ADR_INT_MODE)) = (0x00000000)
++#define DEF_INT_IRQ_STS() (REG32(ADR_INT_IRQ_STS)) = (0x00000000)
++#define DEF_INT_FIQ_STS() (REG32(ADR_INT_FIQ_STS)) = (0x00000000)
++#define DEF_INT_IRQ_RAW() (REG32(ADR_INT_IRQ_RAW)) = (0x00000000)
++#define DEF_INT_FIQ_RAW() (REG32(ADR_INT_FIQ_RAW)) = (0x00000000)
++#define DEF_INT_PERI_MASK() (REG32(ADR_INT_PERI_MASK)) = (0xffffffff)
++#define DEF_INT_PERI_STS() (REG32(ADR_INT_PERI_STS)) = (0x00000000)
++#define DEF_INT_PERI_RAW() (REG32(ADR_INT_PERI_RAW)) = (0x00000000)
++#define DEF_INT_GPI_CFG() (REG32(ADR_INT_GPI_CFG)) = (0x00000000)
++#define DEF_SYS_INT_FOR_HOST() (REG32(ADR_SYS_INT_FOR_HOST)) = (0x00000001)
++#define DEF_SPI_IPC() (REG32(ADR_SPI_IPC)) = (0x00000000)
++#define DEF_SDIO_IPC() (REG32(ADR_SDIO_IPC)) = (0x00000000)
++#define DEF_SDIO_MASK() (REG32(ADR_SDIO_MASK)) = (0xffffffff)
++#define DEF_SDIO_IRQ_STS() (REG32(ADR_SDIO_IRQ_STS)) = (0x00000000)
++#define DEF_SD_PERI_MASK() (REG32(ADR_SD_PERI_MASK)) = (0xffffffff)
++#define DEF_SD_PERI_STS() (REG32(ADR_SD_PERI_STS)) = (0x00000000)
++#define DEF_DBG_SPI_MODE() (REG32(ADR_DBG_SPI_MODE)) = (0x00000000)
++#define DEF_DBG_RX_QUOTA() (REG32(ADR_DBG_RX_QUOTA)) = (0x00000000)
++#define DEF_DBG_CONDITION_NUMBER() (REG32(ADR_DBG_CONDITION_NUMBER)) = (0x00000004)
++#define DEF_DBG_HOST_PATH() (REG32(ADR_DBG_HOST_PATH)) = (0x00000001)
++#define DEF_DBG_TX_SEG() (REG32(ADR_DBG_TX_SEG)) = (0x00000000)
++#define DEF_DBG_DEBUG_BURST_MODE() (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (0x00000000)
++#define DEF_DBG_SPI_TO_PHY_PARAM1() (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (0x000e0006)
++#define DEF_DBG_SPI_TO_PHY_PARAM2() (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (0x000e000e)
++#define DEF_DBG_SPI_STS() (REG32(ADR_DBG_SPI_STS)) = (0x00000000)
++#define DEF_DBG_TX_ALLOC_SET() (REG32(ADR_DBG_TX_ALLOC_SET)) = (0x00000000)
++#define DEF_DBG_TX_ALLOC() (REG32(ADR_DBG_TX_ALLOC)) = (0x00000000)
++#define DEF_DBG_DBG_CNT() (REG32(ADR_DBG_DBG_CNT)) = (0x00000000)
++#define DEF_DBG_DBG_CNT2() (REG32(ADR_DBG_DBG_CNT2)) = (0x00000000)
++#define DEF_DBG_DBG_CNT3() (REG32(ADR_DBG_DBG_CNT3)) = (0x00000000)
++#define DEF_DBG_DBG_CNT4() (REG32(ADR_DBG_DBG_CNT4)) = (0x00000000)
++#define DEF_DBG_INT_TAG() (REG32(ADR_DBG_INT_TAG)) = (0x00000000)
++#define DEF_BOOT_ADDR() (REG32(ADR_BOOT_ADDR)) = (0x00000000)
++#define DEF_VERIFY_DATA() (REG32(ADR_VERIFY_DATA)) = (0x5e11aa11)
++#define DEF_FLASH_ADDR() (REG32(ADR_FLASH_ADDR)) = (0x00000000)
++#define DEF_SRAM_ADDR() (REG32(ADR_SRAM_ADDR)) = (0x00000000)
++#define DEF_LEN() (REG32(ADR_LEN)) = (0x00000000)
++#define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x000f000f)
++#define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00040001)
++#define DEF_CHECK_SUM_RESULT() (REG32(ADR_CHECK_SUM_RESULT)) = (0x00000000)
++#define DEF_CHECK_SUM_IN_FILE() (REG32(ADR_CHECK_SUM_IN_FILE)) = (0x00000000)
++#define DEF_COMMAND_LEN() (REG32(ADR_COMMAND_LEN)) = (0x00000000)
++#define DEF_COMMAND_ADDR() (REG32(ADR_COMMAND_ADDR)) = (0x00000000)
++#define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000)
++#define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000)
++#define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa)
++#define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001)
++#define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000)
++#define DEF_PMU_0() (REG32(ADR_PMU_0)) = (0x0f000040)
++#define DEF_PMU_1() (REG32(ADR_PMU_1)) = (0x015d015d)
++#define DEF_PMU_2() (REG32(ADR_PMU_2)) = (0x00000000)
++#define DEF_PMU_3() (REG32(ADR_PMU_3)) = (0x55550000)
++#define DEF_RTC_1() (REG32(ADR_RTC_1)) = (0x7fff0000)
++#define DEF_RTC_2() (REG32(ADR_RTC_2)) = (0x00000003)
++#define DEF_RTC_3W() (REG32(ADR_RTC_3W)) = (0x00000000)
++#define DEF_RTC_3R() (REG32(ADR_RTC_3R)) = (0x00000000)
++#define DEF_RTC_4() (REG32(ADR_RTC_4)) = (0x00000000)
++#define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000)
++#define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000)
++#define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa)
++#define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001)
++#define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000)
++#define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x02700008)
++#define DEF_SDIO_WAKE_MODE() (REG32(ADR_SDIO_WAKE_MODE)) = (0x00000000)
++#define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000)
++#define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000)
++#define DEF_THREASHOLD() (REG32(ADR_THREASHOLD)) = (0x09000000)
++#define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000)
++#define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000)
++#define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450)
++#define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008)
++#define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000)
++#define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000)
++#define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000)
++#define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_0() (REG32(ADR_PACKET_COUNTER_INFO_0)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_1() (REG32(ADR_PACKET_COUNTER_INFO_1)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_2() (REG32(ADR_PACKET_COUNTER_INFO_2)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_3() (REG32(ADR_PACKET_COUNTER_INFO_3)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_4() (REG32(ADR_PACKET_COUNTER_INFO_4)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_5() (REG32(ADR_PACKET_COUNTER_INFO_5)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_6() (REG32(ADR_PACKET_COUNTER_INFO_6)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_7() (REG32(ADR_PACKET_COUNTER_INFO_7)) = (0x00000000)
++#define DEF_SDIO_TX_RX_FAIL_COUNTER_0() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (0x00000000)
++#define DEF_SDIO_TX_RX_FAIL_COUNTER_1() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_1() (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_8() (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_9() (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_10() (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (0x00000000)
++#define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000)
++#define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000)
++#define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000)
++#define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000)
++#define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000)
++#define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000)
++#define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000)
++#define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000)
++#define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000)
++#define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000)
++#define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000)
++#define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000)
++#define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000)
++#define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000)
++#define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000)
++#define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000)
++#define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000)
++#define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000)
++#define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000)
++#define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000)
++#define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002)
++#define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0)
++#define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002)
++#define DEF_EFUSE_AHB_RDATA_0() (REG32(ADR_EFUSE_AHB_RDATA_0)) = (0x00000000)
++#define DEF_EFUSE_WDATA_0() (REG32(ADR_EFUSE_WDATA_0)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_1() (REG32(ADR_EFUSE_AHB_RDATA_1)) = (0x00000000)
++#define DEF_EFUSE_WDATA_1() (REG32(ADR_EFUSE_WDATA_1)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_2() (REG32(ADR_EFUSE_AHB_RDATA_2)) = (0x00000000)
++#define DEF_EFUSE_WDATA_2() (REG32(ADR_EFUSE_WDATA_2)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_3() (REG32(ADR_EFUSE_AHB_RDATA_3)) = (0x00000000)
++#define DEF_EFUSE_WDATA_3() (REG32(ADR_EFUSE_WDATA_3)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_4() (REG32(ADR_EFUSE_AHB_RDATA_4)) = (0x00000000)
++#define DEF_EFUSE_WDATA_4() (REG32(ADR_EFUSE_WDATA_4)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_5() (REG32(ADR_EFUSE_AHB_RDATA_5)) = (0x00000000)
++#define DEF_EFUSE_WDATA_5() (REG32(ADR_EFUSE_WDATA_5)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_6() (REG32(ADR_EFUSE_AHB_RDATA_6)) = (0x00000000)
++#define DEF_EFUSE_WDATA_6() (REG32(ADR_EFUSE_WDATA_6)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_7() (REG32(ADR_EFUSE_AHB_RDATA_7)) = (0x00000000)
++#define DEF_EFUSE_WDATA_7() (REG32(ADR_EFUSE_WDATA_7)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD0_EN() (REG32(ADR_EFUSE_SPI_RD0_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD1_EN() (REG32(ADR_EFUSE_SPI_RD1_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD2_EN() (REG32(ADR_EFUSE_SPI_RD2_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD3_EN() (REG32(ADR_EFUSE_SPI_RD3_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD4_EN() (REG32(ADR_EFUSE_SPI_RD4_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD5_EN() (REG32(ADR_EFUSE_SPI_RD5_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD6_EN() (REG32(ADR_EFUSE_SPI_RD6_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD7_EN() (REG32(ADR_EFUSE_SPI_RD7_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_BUSY() (REG32(ADR_EFUSE_SPI_BUSY)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_0() (REG32(ADR_EFUSE_SPI_RDATA_0)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_1() (REG32(ADR_EFUSE_SPI_RDATA_1)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_2() (REG32(ADR_EFUSE_SPI_RDATA_2)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_3() (REG32(ADR_EFUSE_SPI_RDATA_3)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_4() (REG32(ADR_EFUSE_SPI_RDATA_4)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_5() (REG32(ADR_EFUSE_SPI_RDATA_5)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_6() (REG32(ADR_EFUSE_SPI_RDATA_6)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_7() (REG32(ADR_EFUSE_SPI_RDATA_7)) = (0x00000000)
++#define DEF_SMS4_CFG1() (REG32(ADR_SMS4_CFG1)) = (0x00000002)
++#define DEF_SMS4_CFG2() (REG32(ADR_SMS4_CFG2)) = (0x00000000)
++#define DEF_SMS4_MODE1() (REG32(ADR_SMS4_MODE1)) = (0x00000000)
++#define DEF_SMS4_TRIG() (REG32(ADR_SMS4_TRIG)) = (0x00000000)
++#define DEF_SMS4_STATUS1() (REG32(ADR_SMS4_STATUS1)) = (0x00000000)
++#define DEF_SMS4_STATUS2() (REG32(ADR_SMS4_STATUS2)) = (0x00000000)
++#define DEF_SMS4_DATA_IN0() (REG32(ADR_SMS4_DATA_IN0)) = (0x00000000)
++#define DEF_SMS4_DATA_IN1() (REG32(ADR_SMS4_DATA_IN1)) = (0x00000000)
++#define DEF_SMS4_DATA_IN2() (REG32(ADR_SMS4_DATA_IN2)) = (0x00000000)
++#define DEF_SMS4_DATA_IN3() (REG32(ADR_SMS4_DATA_IN3)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT0() (REG32(ADR_SMS4_DATA_OUT0)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT1() (REG32(ADR_SMS4_DATA_OUT1)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT2() (REG32(ADR_SMS4_DATA_OUT2)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT3() (REG32(ADR_SMS4_DATA_OUT3)) = (0x00000000)
++#define DEF_SMS4_KEY_0() (REG32(ADR_SMS4_KEY_0)) = (0x00000000)
++#define DEF_SMS4_KEY_1() (REG32(ADR_SMS4_KEY_1)) = (0x00000000)
++#define DEF_SMS4_KEY_2() (REG32(ADR_SMS4_KEY_2)) = (0x00000000)
++#define DEF_SMS4_KEY_3() (REG32(ADR_SMS4_KEY_3)) = (0x00000000)
++#define DEF_SMS4_MODE_IV0() (REG32(ADR_SMS4_MODE_IV0)) = (0x00000000)
++#define DEF_SMS4_MODE_IV1() (REG32(ADR_SMS4_MODE_IV1)) = (0x00000000)
++#define DEF_SMS4_MODE_IV2() (REG32(ADR_SMS4_MODE_IV2)) = (0x00000000)
++#define DEF_SMS4_MODE_IV3() (REG32(ADR_SMS4_MODE_IV3)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC0() (REG32(ADR_SMS4_OFB_ENC0)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC1() (REG32(ADR_SMS4_OFB_ENC1)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC2() (REG32(ADR_SMS4_OFB_ENC2)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC3() (REG32(ADR_SMS4_OFB_ENC3)) = (0x00000000)
++#define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000)
++#define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000)
++#define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000)
++#define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000)
++#define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000)
++#define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5)
++#define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6)
++#define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9)
++#define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1)
++#define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9)
++#define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1)
++#define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe)
++#define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe)
++#define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000)
++#define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000)
++#define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000)
++#define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006)
++#define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001)
++#define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003)
++#define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005)
++#define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007)
++#define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008)
++#define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001)
++#define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808)
++#define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000)
++#define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008)
++#define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e)
++#define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838)
++#define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008)
++#define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008)
++#define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000)
++#define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034)
++#define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004)
++#define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004)
++#define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00)
++#define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000)
++#define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000)
++#define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000)
++#define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008)
++#define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000)
++#define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000)
++#define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000)
++#define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000)
++#define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000)
++#define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000)
++#define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff)
++#define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000)
++#define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000)
++#define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000)
++#define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000)
++#define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000)
++#define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000)
++#define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000)
++#define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000)
++#define DEF_WSID0_TID0_RX_SEQ() (REG32(ADR_WSID0_TID0_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID1_RX_SEQ() (REG32(ADR_WSID0_TID1_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID2_RX_SEQ() (REG32(ADR_WSID0_TID2_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID3_RX_SEQ() (REG32(ADR_WSID0_TID3_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID4_RX_SEQ() (REG32(ADR_WSID0_TID4_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID5_RX_SEQ() (REG32(ADR_WSID0_TID5_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID6_RX_SEQ() (REG32(ADR_WSID0_TID6_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID7_RX_SEQ() (REG32(ADR_WSID0_TID7_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID0_RX_SEQ() (REG32(ADR_WSID1_TID0_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID1_RX_SEQ() (REG32(ADR_WSID1_TID1_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID2_RX_SEQ() (REG32(ADR_WSID1_TID2_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID3_RX_SEQ() (REG32(ADR_WSID1_TID3_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID4_RX_SEQ() (REG32(ADR_WSID1_TID4_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID5_RX_SEQ() (REG32(ADR_WSID1_TID5_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID6_RX_SEQ() (REG32(ADR_WSID1_TID6_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID7_RX_SEQ() (REG32(ADR_WSID1_TID7_RX_SEQ)) = (0x00000000)
++#define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79)
++#define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000)
++#define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000)
++#define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e)
++#define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000)
++#define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000)
++#define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000)
++#define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000)
++#define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000)
++#define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00c00c00)
++#define DEF_MTX_EDCCA_TOUT() (REG32(ADR_MTX_EDCCA_TOUT)) = (0x00000200)
++#define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000)
++#define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000)
++#define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x00000042)
++#define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000)
++#define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064)
++#define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000)
++#define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000)
++#define DEF_MTX_BCN_CFG0() (REG32(ADR_MTX_BCN_CFG0)) = (0x00000000)
++#define DEF_MTX_BCN_CFG1() (REG32(ADR_MTX_BCN_CFG1)) = (0x00000000)
++#define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000)
++#define DEF_MTX_DBG_CTRL() (REG32(ADR_MTX_DBG_CTRL)) = (0x00000000)
++#define DEF_MTX_DBG_DAT0() (REG32(ADR_MTX_DBG_DAT0)) = (0x00000000)
++#define DEF_MTX_DBG_DAT1() (REG32(ADR_MTX_DBG_DAT1)) = (0x00000000)
++#define DEF_MTX_DBG_DAT2() (REG32(ADR_MTX_DBG_DAT2)) = (0x00000000)
++#define DEF_MTX_DUR_TOUT() (REG32(ADR_MTX_DUR_TOUT)) = (0x00002c2c)
++#define DEF_MTX_DUR_IFS() (REG32(ADR_MTX_DUR_IFS)) = (0x12d40a05)
++#define DEF_MTX_DUR_SIFS_G() (REG32(ADR_MTX_DUR_SIFS_G)) = (0x12c90100)
++#define DEF_MTX_DBG_DAT3() (REG32(ADR_MTX_DBG_DAT3)) = (0x00000000)
++#define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000)
++#define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000)
++#define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000)
++#define DEF_MTX_DBG_DAT4() (REG32(ADR_MTX_DBG_DAT4)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ0_MTX_Q_BKF_CNT() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ0_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ1_MTX_Q_BKF_CNT() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ1_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ2_MTX_Q_BKF_CNT() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ2_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ3_MTX_Q_BKF_CNT() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ3_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ4_MTX_Q_BKF_CNT() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ4_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000)
++#define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000)
++#define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000)
++#define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000)
++#define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000)
++#define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000)
++#define DEF_INFO0() (REG32(ADR_INFO0)) = (0x00000000)
++#define DEF_INFO1() (REG32(ADR_INFO1)) = (0x00000100)
++#define DEF_INFO2() (REG32(ADR_INFO2)) = (0x00000200)
++#define DEF_INFO3() (REG32(ADR_INFO3)) = (0x00000300)
++#define DEF_INFO4() (REG32(ADR_INFO4)) = (0x00000140)
++#define DEF_INFO5() (REG32(ADR_INFO5)) = (0x00000240)
++#define DEF_INFO6() (REG32(ADR_INFO6)) = (0x00000340)
++#define DEF_INFO7() (REG32(ADR_INFO7)) = (0x00000001)
++#define DEF_INFO8() (REG32(ADR_INFO8)) = (0x00000101)
++#define DEF_INFO9() (REG32(ADR_INFO9)) = (0x00000201)
++#define DEF_INFO10() (REG32(ADR_INFO10)) = (0x00000301)
++#define DEF_INFO11() (REG32(ADR_INFO11)) = (0x00000401)
++#define DEF_INFO12() (REG32(ADR_INFO12)) = (0x00000501)
++#define DEF_INFO13() (REG32(ADR_INFO13)) = (0x00000601)
++#define DEF_INFO14() (REG32(ADR_INFO14)) = (0x00000701)
++#define DEF_INFO15() (REG32(ADR_INFO15)) = (0x00030002)
++#define DEF_INFO16() (REG32(ADR_INFO16)) = (0x00030102)
++#define DEF_INFO17() (REG32(ADR_INFO17)) = (0x00030202)
++#define DEF_INFO18() (REG32(ADR_INFO18)) = (0x00030302)
++#define DEF_INFO19() (REG32(ADR_INFO19)) = (0x00030402)
++#define DEF_INFO20() (REG32(ADR_INFO20)) = (0x00030502)
++#define DEF_INFO21() (REG32(ADR_INFO21)) = (0x00030602)
++#define DEF_INFO22() (REG32(ADR_INFO22)) = (0x00030702)
++#define DEF_INFO23() (REG32(ADR_INFO23)) = (0x00030082)
++#define DEF_INFO24() (REG32(ADR_INFO24)) = (0x00030182)
++#define DEF_INFO25() (REG32(ADR_INFO25)) = (0x00030282)
++#define DEF_INFO26() (REG32(ADR_INFO26)) = (0x00030382)
++#define DEF_INFO27() (REG32(ADR_INFO27)) = (0x00030482)
++#define DEF_INFO28() (REG32(ADR_INFO28)) = (0x00030582)
++#define DEF_INFO29() (REG32(ADR_INFO29)) = (0x00030682)
++#define DEF_INFO30() (REG32(ADR_INFO30)) = (0x00030782)
++#define DEF_INFO31() (REG32(ADR_INFO31)) = (0x00030042)
++#define DEF_INFO32() (REG32(ADR_INFO32)) = (0x00030142)
++#define DEF_INFO33() (REG32(ADR_INFO33)) = (0x00030242)
++#define DEF_INFO34() (REG32(ADR_INFO34)) = (0x00030342)
++#define DEF_INFO35() (REG32(ADR_INFO35)) = (0x00030442)
++#define DEF_INFO36() (REG32(ADR_INFO36)) = (0x00030542)
++#define DEF_INFO37() (REG32(ADR_INFO37)) = (0x00030642)
++#define DEF_INFO38() (REG32(ADR_INFO38)) = (0x00030742)
++#define DEF_INFO_MASK() (REG32(ADR_INFO_MASK)) = (0x00007fc7)
++#define DEF_INFO_RATE_OFFSET() (REG32(ADR_INFO_RATE_OFFSET)) = (0x00040000)
++#define DEF_INFO_IDX_ADDR() (REG32(ADR_INFO_IDX_ADDR)) = (0x00000000)
++#define DEF_INFO_LEN_ADDR() (REG32(ADR_INFO_LEN_ADDR)) = (0x00000000)
++#define DEF_IC_TIME_TAG_0() (REG32(ADR_IC_TIME_TAG_0)) = (0x00000000)
++#define DEF_IC_TIME_TAG_1() (REG32(ADR_IC_TIME_TAG_1)) = (0x00000000)
++#define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000)
++#define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000)
++#define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000)
++#define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000)
++#define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000)
++#define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb)
++#define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b)
++#define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02)
++#define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000)
++#define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000)
++#define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000)
++#define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000)
++#define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000)
++#define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000)
++#define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000)
++#define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000)
++#define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000)
++#define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006)
++#define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000)
++#define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000)
++#define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000)
++#define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000)
++#define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000)
++#define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000)
++#define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000)
++#define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000)
++#define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000)
++#define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000)
++#define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000)
++#define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000)
++#define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000)
++#define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000)
++#define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000)
++#define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000)
++#define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000)
++#define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000)
++#define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000)
++#define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000)
++#define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000)
++#define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000)
++#define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000)
++#define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000)
++#define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000)
++#define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000)
++#define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000)
++#define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000)
++#define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000)
++#define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000)
++#define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000)
++#define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000)
++#define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000)
++#define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000)
++#define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000)
++#define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000)
++#define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000)
++#define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000)
++#define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000)
++#define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000)
++#define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000)
++#define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000)
++#define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000)
++#define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000)
++#define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000)
++#define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000)
++#define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000)
++#define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000)
++#define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000)
++#define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000)
++#define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000)
++#define DEF_CBR_HARD_WIRE_PIN_REGISTER() (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
++#define DEF_CBR_MANUAL_ENABLE_REGISTER() (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (0x00001fc0)
++#define DEF_CBR_LDO_REGISTER() (REG32(ADR_CBR_LDO_REGISTER)) = (0x2496db1b)
++#define DEF_CBR_ABB_REGISTER_1() (REG32(ADR_CBR_ABB_REGISTER_1)) = (0x151558dd)
++#define DEF_CBR_ABB_REGISTER_2() (REG32(ADR_CBR_ABB_REGISTER_2)) = (0x01011a88)
++#define DEF_CBR_TX_FE_REGISTER() (REG32(ADR_CBR_TX_FE_REGISTER)) = (0x3cbe84fe)
++#define DEF_CBR_RX_FE_REGISTER_1() (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (0x00657579)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
++#define DEF_CBR_RX_FSM_REGISTER() (REG32(ADR_CBR_RX_FSM_REGISTER)) = (0x00000ca8)
++#define DEF_CBR_RX_ADC_REGISTER() (REG32(ADR_CBR_RX_ADC_REGISTER)) = (0x002a0224)
++#define DEF_CBR_TX_DAC_REGISTER() (REG32(ADR_CBR_TX_DAC_REGISTER)) = (0x00002655)
++#define DEF_CBR_SX_ENABLE_RGISTER() (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (0x0000647c)
++#define DEF_CBR_SYN_RGISTER_1() (REG32(ADR_CBR_SYN_RGISTER_1)) = (0xaa800000)
++#define DEF_CBR_SYN_RGISTER_2() (REG32(ADR_CBR_SYN_RGISTER_2)) = (0x00550800)
++#define DEF_CBR_SYN_PFD_CHP() (REG32(ADR_CBR_SYN_PFD_CHP)) = (0x07c0894a)
++#define DEF_CBR_SYN_VCO_LOBF() (REG32(ADR_CBR_SYN_VCO_LOBF)) = (0xfcccca27)
++#define DEF_CBR_SYN_DIV_SDM_XOSC() (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (0x2773c93c)
++#define DEF_CBR_SYN_LCK1() (REG32(ADR_CBR_SYN_LCK1)) = (0x00000a7c)
++#define DEF_CBR_SYN_LCK2() (REG32(ADR_CBR_SYN_LCK2)) = (0x01c67ff4)
++#define DEF_CBR_DPLL_VCO_REGISTER() (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (0x00103014)
++#define DEF_CBR_DPLL_CP_PFD_REGISTER() (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (0x0001848c)
++#define DEF_CBR_DPLL_DIVIDER_REGISTER() (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (0x034061e0)
++#define DEF_CBR_DCOC_IDAC_REGISTER1() (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER2() (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER3() (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER4() (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER5() (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER6() (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER7() (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER8() (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (0x00820820)
++#define DEF_CBR_RCAL_REGISTER() (REG32(ADR_CBR_RCAL_REGISTER)) = (0x00004080)
++#define DEF_CBR_MANUAL_REGISTER() (REG32(ADR_CBR_MANUAL_REGISTER)) = (0x00003e7e)
++#define DEF_CBR_TRX_DUMMY_REGISTER() (REG32(ADR_CBR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_CBR_SX_DUMMY_REGISTER() (REG32(ADR_CBR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_CBR_RG_PKT_GEN_0() (REG32(ADR_CBR_RG_PKT_GEN_0)) = (0x00000000)
++#define DEF_CBR_RG_PKT_GEN_1() (REG32(ADR_CBR_RG_PKT_GEN_1)) = (0x00000000)
++#define DEF_CBR_RG_PKT_GEN_2() (REG32(ADR_CBR_RG_PKT_GEN_2)) = (0x00000000)
++#define DEF_CBR_RG_INTEGRATION() (REG32(ADR_CBR_RG_INTEGRATION)) = (0x00000000)
++#define DEF_CBR_RG_PKT_GEN_TXCNT() (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (0x00000000)
++#define DEF_CBR_PATTERN_GEN() (REG32(ADR_CBR_PATTERN_GEN)) = (0xff000000)
++#define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000)
++#define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000)
++#define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000)
++#define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000)
++#define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000)
++#define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000)
++#define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000)
++#define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000)
++#define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000)
++#define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000)
++#define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000)
++#define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000)
++#define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000)
++#define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000)
++#define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff)
++#define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002)
++#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000)
++#define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000)
++#define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000)
++#define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000)
++#define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000)
++#define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000)
++#define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000)
++#define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000)
++#define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000)
++#define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000)
++#define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001)
++#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000)
++#define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000)
++#define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000)
++#define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000)
++#define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000)
++#define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000)
++#define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000)
++#define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000)
++#define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000)
++#define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213)
++#define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000)
++#define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000)
++#define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000)
++#define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000)
++#define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000)
++#define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000)
++#define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c)
++#define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000)
++#define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000)
++#define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000)
++#define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000)
++#define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001)
++#define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641)
++#define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000)
++#define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201)
++#define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000)
++#define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100)
++#define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000)
++#define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000)
++#define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000)
++#define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000)
++#define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000)
++#define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000)
++#define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000)
++#define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100)
++#define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000)
++#define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000)
++#define DEF_PHY_EN_0() (REG32(ADR_PHY_EN_0)) = (0x00000014)
++#define DEF_PHY_EN_1() (REG32(ADR_PHY_EN_1)) = (0x00000000)
++#define DEF_SVN_VERSION_REG() (REG32(ADR_SVN_VERSION_REG)) = (0x00000000)
++#define DEF_PHY_PKT_GEN_0() (REG32(ADR_PHY_PKT_GEN_0)) = (0x00000064)
++#define DEF_PHY_PKT_GEN_1() (REG32(ADR_PHY_PKT_GEN_1)) = (0x00000fff)
++#define DEF_PHY_PKT_GEN_2() (REG32(ADR_PHY_PKT_GEN_2)) = (0x00000003)
++#define DEF_PHY_PKT_GEN_3() (REG32(ADR_PHY_PKT_GEN_3)) = (0x005a0220)
++#define DEF_PHY_PKT_GEN_4() (REG32(ADR_PHY_PKT_GEN_4)) = (0x00000001)
++#define DEF_PHY_REG_00() (REG32(ADR_PHY_REG_00)) = (0x10000000)
++#define DEF_PHY_REG_01() (REG32(ADR_PHY_REG_01)) = (0x00000000)
++#define DEF_PHY_REG_02_AGC() (REG32(ADR_PHY_REG_02_AGC)) = (0x80046771)
++#define DEF_PHY_REG_03_AGC() (REG32(ADR_PHY_REG_03_AGC)) = (0x1f300f6f)
++#define DEF_PHY_REG_04_AGC() (REG32(ADR_PHY_REG_04_AGC)) = (0x663f36d0)
++#define DEF_PHY_REG_05_AGC() (REG32(ADR_PHY_REG_05_AGC)) = (0x106c0000)
++#define DEF_PHY_REG_06_11B_DAGC() (REG32(ADR_PHY_REG_06_11B_DAGC)) = (0x01603fff)
++#define DEF_PHY_REG_07_11B_DAGC() (REG32(ADR_PHY_REG_07_11B_DAGC)) = (0x00600808)
++#define DEF_PHY_REG_08_11GN_DAGC() (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (0xff000160)
++#define DEF_PHY_REG_09_11GN_DAGC() (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (0x00080840)
++#define DEF_PHY_READ_REG_00_DIG_PWR() (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (0x00000000)
++#define DEF_PHY_READ_REG_01_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (0x00000000)
++#define DEF_PHY_READ_REG_02_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (0x00000000)
++#define DEF_PHY_READ_REG_03_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (0x00000000)
++#define DEF_PHY_REG_10_TX_DES() (REG32(ADR_PHY_REG_10_TX_DES)) = (0x00010405)
++#define DEF_PHY_REG_11_TX_DES() (REG32(ADR_PHY_REG_11_TX_DES)) = (0x06090813)
++#define DEF_PHY_REG_12_TX_DES() (REG32(ADR_PHY_REG_12_TX_DES)) = (0x12070000)
++#define DEF_PHY_REG_13_RX_DES() (REG32(ADR_PHY_REG_13_RX_DES)) = (0x01000405)
++#define DEF_PHY_REG_14_RX_DES() (REG32(ADR_PHY_REG_14_RX_DES)) = (0x06090813)
++#define DEF_PHY_REG_15_RX_DES() (REG32(ADR_PHY_REG_15_RX_DES)) = (0x12010000)
++#define DEF_PHY_REG_16_TX_DES_EXCP() (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (0x00000000)
++#define DEF_PHY_REG_17_TX_DES_EXCP() (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (0x10110000)
++#define DEF_PHY_REG_18_RSSI_SNR() (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (0x00fc000f)
++#define DEF_PHY_REG_19_DAC_MANUAL() (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (0x00000000)
++#define DEF_PHY_REG_20_MRX_CNT() (REG32(ADR_PHY_REG_20_MRX_CNT)) = (0x00000000)
++#define DEF_PHY_REG_21_TRX_RAMP() (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (0x3c012801)
++#define DEF_PHY_REG_22_TRX_RAMP() (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (0x24243724)
++#define DEF_PHY_REG_23_ANT() (REG32(ADR_PHY_REG_23_ANT)) = (0x00000011)
++#define DEF_PHY_REG_24_MTX_LEN_CNT() (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_REG_25_MTX_LEN_CNT() (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_REG_26_MRX_LEN_CNT() (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_REG_27_MRX_LEN_CNT() (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_READ_REG_04() (REG32(ADR_PHY_READ_REG_04)) = (0x00000000)
++#define DEF_PHY_READ_REG_05() (REG32(ADR_PHY_READ_REG_05)) = (0x00000000)
++#define DEF_PHY_REG_28_BIST() (REG32(ADR_PHY_REG_28_BIST)) = (0x0000fe3e)
++#define DEF_PHY_READ_REG_06_BIST() (REG32(ADR_PHY_READ_REG_06_BIST)) = (0x00000000)
++#define DEF_PHY_READ_REG_07_BIST() (REG32(ADR_PHY_READ_REG_07_BIST)) = (0x00000000)
++#define DEF_PHY_REG_29_MTRX_MAC() (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (0xffffffff)
++#define DEF_PHY_READ_REG_08_MTRX_MAC() (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (0x00000000)
++#define DEF_PHY_READ_REG_09_MTRX_MAC() (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (0x00000000)
++#define DEF_PHY_REG_30_TX_UP_FIL() (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (0x0ead04f5)
++#define DEF_PHY_REG_31_TX_UP_FIL() (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (0x0fd60080)
++#define DEF_PHY_REG_32_TX_UP_FIL() (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (0x00000009)
++#define DEF_PHY_READ_TBUS() (REG32(ADR_PHY_READ_TBUS)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_00() (REG32(ADR_TX_11B_FIL_COEF_00)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_01() (REG32(ADR_TX_11B_FIL_COEF_01)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_02() (REG32(ADR_TX_11B_FIL_COEF_02)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_03() (REG32(ADR_TX_11B_FIL_COEF_03)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_04() (REG32(ADR_TX_11B_FIL_COEF_04)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_05() (REG32(ADR_TX_11B_FIL_COEF_05)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_06() (REG32(ADR_TX_11B_FIL_COEF_06)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_07() (REG32(ADR_TX_11B_FIL_COEF_07)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_08() (REG32(ADR_TX_11B_FIL_COEF_08)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_09() (REG32(ADR_TX_11B_FIL_COEF_09)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_10() (REG32(ADR_TX_11B_FIL_COEF_10)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_11() (REG32(ADR_TX_11B_FIL_COEF_11)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_12() (REG32(ADR_TX_11B_FIL_COEF_12)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_13() (REG32(ADR_TX_11B_FIL_COEF_13)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_14() (REG32(ADR_TX_11B_FIL_COEF_14)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_15() (REG32(ADR_TX_11B_FIL_COEF_15)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_16() (REG32(ADR_TX_11B_FIL_COEF_16)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_17() (REG32(ADR_TX_11B_FIL_COEF_17)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_18() (REG32(ADR_TX_11B_FIL_COEF_18)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_19() (REG32(ADR_TX_11B_FIL_COEF_19)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_20() (REG32(ADR_TX_11B_FIL_COEF_20)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_21() (REG32(ADR_TX_11B_FIL_COEF_21)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_22() (REG32(ADR_TX_11B_FIL_COEF_22)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_23() (REG32(ADR_TX_11B_FIL_COEF_23)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_24() (REG32(ADR_TX_11B_FIL_COEF_24)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_25() (REG32(ADR_TX_11B_FIL_COEF_25)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_26() (REG32(ADR_TX_11B_FIL_COEF_26)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_27() (REG32(ADR_TX_11B_FIL_COEF_27)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_28() (REG32(ADR_TX_11B_FIL_COEF_28)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_29() (REG32(ADR_TX_11B_FIL_COEF_29)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_30() (REG32(ADR_TX_11B_FIL_COEF_30)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_31() (REG32(ADR_TX_11B_FIL_COEF_31)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_32() (REG32(ADR_TX_11B_FIL_COEF_32)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_33() (REG32(ADR_TX_11B_FIL_COEF_33)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_34() (REG32(ADR_TX_11B_FIL_COEF_34)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_35() (REG32(ADR_TX_11B_FIL_COEF_35)) = (0x00000005)
++#define DEF_TX_11B_FIL_COEF_36() (REG32(ADR_TX_11B_FIL_COEF_36)) = (0x0000003d)
++#define DEF_TX_11B_FIL_COEF_37() (REG32(ADR_TX_11B_FIL_COEF_37)) = (0x00000162)
++#define DEF_TX_11B_FIL_COEF_38() (REG32(ADR_TX_11B_FIL_COEF_38)) = (0x00000400)
++#define DEF_TX_11B_FIL_COEF_39() (REG32(ADR_TX_11B_FIL_COEF_39)) = (0x00000699)
++#define DEF_TX_11B_FIL_COEF_40() (REG32(ADR_TX_11B_FIL_COEF_40)) = (0x00000787)
++#define DEF_TX_11B_PLCP() (REG32(ADR_TX_11B_PLCP)) = (0x00000000)
++#define DEF_TX_11B_RAMP() (REG32(ADR_TX_11B_RAMP)) = (0x0000403c)
++#define DEF_TX_11B_EN_CNT_RST_N() (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (0x00000001)
++#define DEF_TX_11B_EN_CNT() (REG32(ADR_TX_11B_EN_CNT)) = (0x00000000)
++#define DEF_TX_11B_PKT_GEN_CNT() (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (0x00000000)
++#define DEF_RX_11B_DES_DLY() (REG32(ADR_RX_11B_DES_DLY)) = (0x00000044)
++#define DEF_RX_11B_CCA_0() (REG32(ADR_RX_11B_CCA_0)) = (0x00040000)
++#define DEF_RX_11B_CCA_1() (REG32(ADR_RX_11B_CCA_1)) = (0x00400040)
++#define DEF_RX_11B_TR_KP_KI_0() (REG32(ADR_RX_11B_TR_KP_KI_0)) = (0x00003467)
++#define DEF_RX_11B_TR_KP_KI_1() (REG32(ADR_RX_11B_TR_KP_KI_1)) = (0x00540000)
++#define DEF_RX_11B_CE_CNT_THRESHOLD() (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (0x12243615)
++#define DEF_RX_11B_CE_MU_0() (REG32(ADR_RX_11B_CE_MU_0)) = (0x00390002)
++#define DEF_RX_11B_CE_MU_1() (REG32(ADR_RX_11B_CE_MU_1)) = (0x03456777)
++#define DEF_RX_11B_EQ_MU_0() (REG32(ADR_RX_11B_EQ_MU_0)) = (0x00350046)
++#define DEF_RX_11B_EQ_MU_1() (REG32(ADR_RX_11B_EQ_MU_1)) = (0x00570057)
++#define DEF_RX_11B_EQ_CR_KP_KI() (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (0x00236700)
++#define DEF_RX_11B_LPF_RATE() (REG32(ADR_RX_11B_LPF_RATE)) = (0x000d1746)
++#define DEF_RX_11B_CIT_CNT_THRESHOLD() (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (0x04061787)
++#define DEF_RX_11B_EQ_CH_MAIN_TAP() (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (0x07800000)
++#define DEF_RX_11B_SEARCH_CNT_TH() (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (0x00c0000a)
++#define DEF_RX_11B_CCA_CONTROL() (REG32(ADR_RX_11B_CCA_CONTROL)) = (0x00000000)
++#define DEF_RX_11B_FREQUENCY_OFFSET() (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (0x00000000)
++#define DEF_RX_11B_SNR_RSSI() (REG32(ADR_RX_11B_SNR_RSSI)) = (0x00000000)
++#define DEF_RX_11B_SFD_CRC_CNT() (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (0x00000000)
++#define DEF_RX_11B_PKT_ERR_AND_PKT_ERR_CNT() (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (0x00000000)
++#define DEF_RX_11B_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
++#define DEF_RX_11B_SFD_FILED_0() (REG32(ADR_RX_11B_SFD_FILED_0)) = (0x00000000)
++#define DEF_RX_11B_SFD_FIELD_1() (REG32(ADR_RX_11B_SFD_FIELD_1)) = (0x00000000)
++#define DEF_RX_11B_PKT_STAT_EN() (REG32(ADR_RX_11B_PKT_STAT_EN)) = (0x00100000)
++#define DEF_RX_11B_SOFT_RST() (REG32(ADR_RX_11B_SOFT_RST)) = (0x00000001)
++#define DEF_TX_11GN_RAMP() (REG32(ADR_TX_11GN_RAMP)) = (0x0000233c)
++#define DEF_TX_11GN_PLCP() (REG32(ADR_TX_11GN_PLCP)) = (0x5d08908e)
++#define DEF_TX_11GN_PKT_GEN_CNT() (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (0x00000000)
++#define DEF_TX_11GN_PLCP_CRC_ERR_CNT() (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (0x00000000)
++#define DEF_RX_11GN_DES_DLY() (REG32(ADR_RX_11GN_DES_DLY)) = (0x00000044)
++#define DEF_RX_11GN_TR_0() (REG32(ADR_RX_11GN_TR_0)) = (0x00750075)
++#define DEF_RX_11GN_TR_1() (REG32(ADR_RX_11GN_TR_1)) = (0x00000075)
++#define DEF_RX_11GN_TR_2() (REG32(ADR_RX_11GN_TR_2)) = (0x10000075)
++#define DEF_RX_11GN_CCA_0() (REG32(ADR_RX_11GN_CCA_0)) = (0x38324705)
++#define DEF_RX_11GN_CCA_1() (REG32(ADR_RX_11GN_CCA_1)) = (0x30182000)
++#define DEF_RX_11GN_CCA_2() (REG32(ADR_RX_11GN_CCA_2)) = (0x20600000)
++#define DEF_RX_11GN_CCA_FFT_SCALE() (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (0x0a010100)
++#define DEF_RX_11GN_SOFT_DEMAP_0() (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (0x50505050)
++#define DEF_RX_11GN_SOFT_DEMAP_1() (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (0x50000000)
++#define DEF_RX_11GN_SOFT_DEMAP_2() (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (0x50505050)
++#define DEF_RX_11GN_SOFT_DEMAP_3() (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (0x50505050)
++#define DEF_RX_11GN_SOFT_DEMAP_4() (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (0x50000000)
++#define DEF_RX_11GN_SOFT_DEMAP_5() (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (0x00000000)
++#define DEF_RX_11GN_SYM_BOUND_0() (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (0x00001420)
++#define DEF_RX_11GN_SYM_BOUND_1() (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (0x0000200a)
++#define DEF_RX_11GN_CCA_PWR() (REG32(ADR_RX_11GN_CCA_PWR)) = (0x30000280)
++#define DEF_RX_11GN_CCA_CNT() (REG32(ADR_RX_11GN_CCA_CNT)) = (0x30023002)
++#define DEF_RX_11GN_CCA_ATCOR_RE_CHECK() (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (0x0000003a)
++#define DEF_RX_11GN_VTB_TB() (REG32(ADR_RX_11GN_VTB_TB)) = (0x40000000)
++#define DEF_RX_11GN_ERR_UPDATE() (REG32(ADR_RX_11GN_ERR_UPDATE)) = (0x009e007e)
++#define DEF_RX_11GN_SHORT_GI() (REG32(ADR_RX_11GN_SHORT_GI)) = (0x00044400)
++#define DEF_RX_11GN_CHANNEL_UPDATE() (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (0x82000000)
++#define DEF_RX_11GN_PKT_FORMAT_0() (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (0x02003030)
++#define DEF_RX_11GN_PKT_FORMAT_1() (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (0x092a092a)
++#define DEF_RX_11GN_TX_TIME() (REG32(ADR_RX_11GN_TX_TIME)) = (0x00700010)
++#define DEF_RX_11GN_STBC_TR_KP_KI() (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (0x00007575)
++#define DEF_RX_11GN_BIST_0() (REG32(ADR_RX_11GN_BIST_0)) = (0x0001fe3e)
++#define DEF_RX_11GN_BIST_1() (REG32(ADR_RX_11GN_BIST_1)) = (0x0000fe3e)
++#define DEF_RX_11GN_BIST_2() (REG32(ADR_RX_11GN_BIST_2)) = (0x00000000)
++#define DEF_RX_11GN_BIST_3() (REG32(ADR_RX_11GN_BIST_3)) = (0x00000000)
++#define DEF_RX_11GN_BIST_4() (REG32(ADR_RX_11GN_BIST_4)) = (0x00000000)
++#define DEF_RX_11GN_BIST_5() (REG32(ADR_RX_11GN_BIST_5)) = (0x00000000)
++#define DEF_RX_11GN_SPECTRUM_ANALYZER() (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (0x00000000)
++#define DEF_RX_11GN_READ_0() (REG32(ADR_RX_11GN_READ_0)) = (0x00000000)
++#define DEF_RX_11GN_FREQ_OFFSET() (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (0x00000000)
++#define DEF_RX_11GN_SIGNAL_FIELD_0() (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (0x00000000)
++#define DEF_RX_11GN_SIGNAL_FIELD_1() (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (0x00000000)
++#define DEF_RX_11GN_PKT_ERR_CNT() (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (0x00000000)
++#define DEF_RX_11GN_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
++#define DEF_RX_11GN_SERVICE_LENGTH_FIELD() (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (0x00000000)
++#define DEF_RX_11GN_RATE() (REG32(ADR_RX_11GN_RATE)) = (0x00000000)
++#define DEF_RX_11GN_STAT_EN() (REG32(ADR_RX_11GN_STAT_EN)) = (0x00100001)
++#define DEF_RX_11GN_SOFT_RST() (REG32(ADR_RX_11GN_SOFT_RST)) = (0x00000001)
++#define DEF_RF_CONTROL_0() (REG32(ADR_RF_CONTROL_0)) = (0x00000000)
++#define DEF_RF_CONTROL_1() (REG32(ADR_RF_CONTROL_1)) = (0x00008000)
++#define DEF_TX_IQ_CONTROL_0() (REG32(ADR_TX_IQ_CONTROL_0)) = (0x00200020)
++#define DEF_TX_IQ_CONTROL_1() (REG32(ADR_TX_IQ_CONTROL_1)) = (0x00028080)
++#define DEF_TX_IQ_CONTROL_2() (REG32(ADR_TX_IQ_CONTROL_2)) = (0x00000000)
++#define DEF_TX_COMPENSATION_CONTROL() (REG32(ADR_TX_COMPENSATION_CONTROL)) = (0x00000000)
++#define DEF_RX_COMPENSATION_CONTROL() (REG32(ADR_RX_COMPENSATION_CONTROL)) = (0x00000000)
++#define DEF_RX_OBSERVATION_CIRCUIT_0() (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (0x000028ff)
++#define DEF_RX_OBSERVATION_CIRCUIT_1() (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (0x00000000)
++#define DEF_RX_OBSERVATION_CIRCUIT_2() (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (0x00000000)
++#define DEF_RX_OBSERVATION_CIRCUIT_3() (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (0x00000000)
++#define DEF_RF_IQ_CONTROL_0() (REG32(ADR_RF_IQ_CONTROL_0)) = (0x00000202)
++#define DEF_RF_IQ_CONTROL_1() (REG32(ADR_RF_IQ_CONTROL_1)) = (0x00ffc200)
++#define DEF_RF_IQ_CONTROL_2() (REG32(ADR_RF_IQ_CONTROL_2)) = (0x00000000)
++#define DEF_RF_IQ_CONTROL_3() (REG32(ADR_RF_IQ_CONTROL_3)) = (0x00000000)
++#define DEF_DPD_CONTROL() (REG32(ADR_DPD_CONTROL)) = (0x00000000)
++#define DEF_DPD_GAIN_TABLE_0() (REG32(ADR_DPD_GAIN_TABLE_0)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_1() (REG32(ADR_DPD_GAIN_TABLE_1)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_2() (REG32(ADR_DPD_GAIN_TABLE_2)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_3() (REG32(ADR_DPD_GAIN_TABLE_3)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_4() (REG32(ADR_DPD_GAIN_TABLE_4)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_5() (REG32(ADR_DPD_GAIN_TABLE_5)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_6() (REG32(ADR_DPD_GAIN_TABLE_6)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_7() (REG32(ADR_DPD_GAIN_TABLE_7)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_8() (REG32(ADR_DPD_GAIN_TABLE_8)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_9() (REG32(ADR_DPD_GAIN_TABLE_9)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_A() (REG32(ADR_DPD_GAIN_TABLE_A)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_B() (REG32(ADR_DPD_GAIN_TABLE_B)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_C() (REG32(ADR_DPD_GAIN_TABLE_C)) = (0x02000200)
++#define DEF_DPD_PH_TABLE_0() (REG32(ADR_DPD_PH_TABLE_0)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_1() (REG32(ADR_DPD_PH_TABLE_1)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_2() (REG32(ADR_DPD_PH_TABLE_2)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_3() (REG32(ADR_DPD_PH_TABLE_3)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_4() (REG32(ADR_DPD_PH_TABLE_4)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_5() (REG32(ADR_DPD_PH_TABLE_5)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_6() (REG32(ADR_DPD_PH_TABLE_6)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_7() (REG32(ADR_DPD_PH_TABLE_7)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_8() (REG32(ADR_DPD_PH_TABLE_8)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_9() (REG32(ADR_DPD_PH_TABLE_9)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_A() (REG32(ADR_DPD_PH_TABLE_A)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_B() (REG32(ADR_DPD_PH_TABLE_B)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_C() (REG32(ADR_DPD_PH_TABLE_C)) = (0x00000000)
++#define DEF_DPD_GAIN_ESTIMATION_0() (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (0x00000000)
++#define DEF_DPD_GAIN_ESTIMATION_1() (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (0x00000100)
++#define DEF_DPD_GAIN_ESTIMATION_2() (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (0x00000000)
++#define DEF_TX_GAIN_FACTOR() (REG32(ADR_TX_GAIN_FACTOR)) = (0x80808080)
++#define DEF_HARD_WIRE_PIN_REGISTER() (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
++#define DEF_MANUAL_ENABLE_REGISTER() (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (0x00000fc0)
++#define DEF_LDO_REGISTER() (REG32(ADR_LDO_REGISTER)) = (0x000db71b)
++#define DEF_ABB_REGISTER_1() (REG32(ADR_ABB_REGISTER_1)) = (0x151558dd)
++#define DEF_ABB_REGISTER_2() (REG32(ADR_ABB_REGISTER_2)) = (0x01011a88)
++#define DEF_TX_FE_REGISTER() (REG32(ADR_TX_FE_REGISTER)) = (0x3d3e84fe)
++#define DEF_RX_FE_REGISTER_1() (REG32(ADR_RX_FE_REGISTER_1)) = (0x03457579)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
++#define DEF_RX_TX_FSM_REGISTER() (REG32(ADR_RX_TX_FSM_REGISTER)) = (0x00030ca8)
++#define DEF_RX_ADC_REGISTER() (REG32(ADR_RX_ADC_REGISTER)) = (0x20ea0224)
++#define DEF_TX_DAC_REGISTER() (REG32(ADR_TX_DAC_REGISTER)) = (0x44000655)
++#define DEF_SX_ENABLE_REGISTER() (REG32(ADR_SX_ENABLE_REGISTER)) = (0x0003e07c)
++#define DEF_SYN_REGISTER_1() (REG32(ADR_SYN_REGISTER_1)) = (0xaa800000)
++#define DEF_SYN_REGISTER_2() (REG32(ADR_SYN_REGISTER_2)) = (0x00550800)
++#define DEF_SYN_PFD_CHP() (REG32(ADR_SYN_PFD_CHP)) = (0x07c0894a)
++#define DEF_SYN_VCO_LOBF() (REG32(ADR_SYN_VCO_LOBF)) = (0xfcccca27)
++#define DEF_SYN_DIV_SDM_XOSC() (REG32(ADR_SYN_DIV_SDM_XOSC)) = (0x07700830)
++#define DEF_SYN_KVCO_XO_FINE_TUNE_CBANK() (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (0x00440000)
++#define DEF_SYN_LCK_VT() (REG32(ADR_SYN_LCK_VT)) = (0x00007ff4)
++#define DEF_DPLL_VCO_REGISTER() (REG32(ADR_DPLL_VCO_REGISTER)) = (0x0000000e)
++#define DEF_DPLL_CP_PFD_REGISTER() (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (0x00088008)
++#define DEF_DPLL_DIVIDER_REGISTER() (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (0x00406000)
++#define DEF_DCOC_IDAC_REGISTER1() (REG32(ADR_DCOC_IDAC_REGISTER1)) = (0x08820820)
++#define DEF_DCOC_IDAC_REGISTER2() (REG32(ADR_DCOC_IDAC_REGISTER2)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER3() (REG32(ADR_DCOC_IDAC_REGISTER3)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER4() (REG32(ADR_DCOC_IDAC_REGISTER4)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER5() (REG32(ADR_DCOC_IDAC_REGISTER5)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER6() (REG32(ADR_DCOC_IDAC_REGISTER6)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER7() (REG32(ADR_DCOC_IDAC_REGISTER7)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER8() (REG32(ADR_DCOC_IDAC_REGISTER8)) = (0x00820820)
++#define DEF_RCAL_REGISTER() (REG32(ADR_RCAL_REGISTER)) = (0x00004080)
++#define DEF_SX_LCK_BIN_REGISTERS_I() (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (0x20080080)
++#define DEF_TRX_DUMMY_REGISTER() (REG32(ADR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_SX_DUMMY_REGISTER() (REG32(ADR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_DPLL_FB_DIVIDER_REGISTERS_II() (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (0x00ec2ec5)
++#define DEF_SX_LCK_BIN_REGISTERS_II() (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (0x00000f13)
++#define DEF_RC_OSC_32K_CAL_REGISTERS() (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (0x00098900)
++#define DEF_RF_D_DIGITAL_DEBUG_PORT_REGISTER() (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (0x00000000)
++#define DEF_MMU_CTRL() (REG32(ADR_MMU_CTRL)) = (0x00002042)
++#define DEF_HS_CTRL() (REG32(ADR_HS_CTRL)) = (0x00000000)
++#define DEF_CPU_POR0_7() (REG32(ADR_CPU_POR0_7)) = (0x00000000)
++#define DEF_CPU_POR8_F() (REG32(ADR_CPU_POR8_F)) = (0x00000000)
++#define DEF_REG_LEN_CTRL() (REG32(ADR_REG_LEN_CTRL)) = (0x00000f0f)
++#define DEF_DMN_READ_BYPASS() (REG32(ADR_DMN_READ_BYPASS)) = (0x0000ffff)
++#define DEF_ALC_RLS_ABORT() (REG32(ADR_ALC_RLS_ABORT)) = (0x00000000)
++#define DEF_DEBUG_CTL() (REG32(ADR_DEBUG_CTL)) = (0x00000000)
++#define DEF_DEBUG_OUT() (REG32(ADR_DEBUG_OUT)) = (0x00000000)
++#define DEF_MMU_STATUS() (REG32(ADR_MMU_STATUS)) = (0x00000000)
++#define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00000000)
++#define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000)
++#define DEF_DMN_MCU_STATUS() (REG32(ADR_DMN_MCU_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_0_STATUS() (REG32(ADR_MB_IDTBL_0_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_1_STATUS() (REG32(ADR_MB_IDTBL_1_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_2_STATUS() (REG32(ADR_MB_IDTBL_2_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_3_STATUS() (REG32(ADR_MB_IDTBL_3_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_0_STATUS() (REG32(ADR_PKT_IDTBL_0_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_1_STATUS() (REG32(ADR_PKT_IDTBL_1_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_2_STATUS() (REG32(ADR_PKT_IDTBL_2_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_3_STATUS() (REG32(ADR_PKT_IDTBL_3_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_0_STATUS() (REG32(ADR_DMN_IDTBL_0_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_1_STATUS() (REG32(ADR_DMN_IDTBL_1_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_2_STATUS() (REG32(ADR_DMN_IDTBL_2_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_3_STATUS() (REG32(ADR_DMN_IDTBL_3_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_0_STATUS() (REG32(ADR_MB_NEQID_0_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_1_STATUS() (REG32(ADR_MB_NEQID_1_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_2_STATUS() (REG32(ADR_MB_NEQID_2_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_3_STATUS() (REG32(ADR_MB_NEQID_3_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_0_STATUS() (REG32(ADR_PKT_NEQID_0_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_1_STATUS() (REG32(ADR_PKT_NEQID_1_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_2_STATUS() (REG32(ADR_PKT_NEQID_2_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_3_STATUS() (REG32(ADR_PKT_NEQID_3_STATUS)) = (0x00000000)
++#define DEF_ALC_NOCHG_ID_STATUS() (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_0() (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_1() (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_2() (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_3() (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_4() (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_5() (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_6() (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_7() (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (0x00000000)
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
+new file mode 100644
+index 000000000000..e15a481ba300
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
+@@ -0,0 +1,176 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "ssv6200_reg.h"
++#define BANK_COUNT 49
++static const u32 BASE_BANK_SSV6200[] = {
++	SYS_REG_BASE,
++	WBOOT_REG_BASE,
++	TU0_US_REG_BASE,
++	TU1_US_REG_BASE,
++	TU2_US_REG_BASE,
++	TU3_US_REG_BASE,
++	TM0_MS_REG_BASE,
++	TM1_MS_REG_BASE,
++	TM2_MS_REG_BASE,
++	TM3_MS_REG_BASE,
++	MCU_WDT_REG_BASE,
++	SYS_WDT_REG_BASE,
++	GPIO_REG_BASE,
++	SD_REG_BASE,
++	SPI_REG_BASE,
++	CSR_I2C_MST_BASE,
++	UART_REG_BASE,
++	DAT_UART_REG_BASE,
++	INT_REG_BASE,
++	DBG_SPI_REG_BASE,
++	FLASH_SPI_REG_BASE,
++	DMA_REG_BASE,
++	CSR_PMU_BASE,
++	CSR_RTC_BASE,
++	RTC_RAM_BASE,
++	D2_DMA_REG_BASE,
++	HCI_REG_BASE,
++	CO_REG_BASE,
++	EFS_REG_BASE,
++	SMS4_REG_BASE,
++	MRX_REG_BASE,
++	AMPDU_REG_BASE,
++	MT_REG_CSR_BASE,
++	TXQ0_MT_Q_REG_CSR_BASE,
++	TXQ1_MT_Q_REG_CSR_BASE,
++	TXQ2_MT_Q_REG_CSR_BASE,
++	TXQ3_MT_Q_REG_CSR_BASE,
++	TXQ4_MT_Q_REG_CSR_BASE,
++	HIF_INFO_BASE,
++	PHY_RATE_INFO_BASE,
++	MAC_GLB_SET_BASE,
++	BTCX_REG_BASE,
++	MIB_REG_BASE,
++	CBR_A_REG_BASE,
++	MB_REG_BASE,
++	ID_MNG_REG_BASE,
++	CSR_PHY_BASE,
++	CSR_RF_BASE,
++	MMU_REG_BASE,
++	0x00000000
++};
++
++static const char *STR_BANK_SSV6200[] = {
++	"SYS_REG",
++	"WBOOT_REG",
++	"TU0_US_REG",
++	"TU1_US_REG",
++	"TU2_US_REG",
++	"TU3_US_REG",
++	"TM0_MS_REG",
++	"TM1_MS_REG",
++	"TM2_MS_REG",
++	"TM3_MS_REG",
++	"MCU_WDT_REG",
++	"SYS_WDT_REG",
++	"GPIO_REG",
++	"SD_REG",
++	"SPI_REG",
++	"CSR_I2C_MST",
++	"UART_REG",
++	"DAT_UART_REG",
++	"INT_REG",
++	"DBG_SPI_REG",
++	"FLASH_SPI_REG",
++	"DMA_REG",
++	"CSR_PMU",
++	"CSR_RTC",
++	"RTC_RAM",
++	"D2_DMA_REG",
++	"HCI_REG",
++	"CO_REG",
++	"EFS_REG",
++	"SMS4_REG",
++	"MRX_REG",
++	"AMPDU_REG",
++	"MT_REG_CSR",
++	"TXQ0_MT_Q_REG_CSR",
++	"TXQ1_MT_Q_REG_CSR",
++	"TXQ2_MT_Q_REG_CSR",
++	"TXQ3_MT_Q_REG_CSR",
++	"TXQ4_MT_Q_REG_CSR",
++	"HIF_INFO",
++	"PHY_RATE_INFO",
++	"MAC_GLB_SET",
++	"BTCX_REG",
++	"MIB_REG",
++	"CBR_A_REG",
++	"MB_REG",
++	"ID_MNG_REG",
++	"CSR_PHY",
++	"CSR_RF",
++	"MMU_REG",
++	""
++};
++
++static const u32 SIZE_BANK_SSV6200[] = {
++	SYS_REG_BANK_SIZE,
++	WBOOT_REG_BANK_SIZE,
++	TU0_US_REG_BANK_SIZE,
++	TU1_US_REG_BANK_SIZE,
++	TU2_US_REG_BANK_SIZE,
++	TU3_US_REG_BANK_SIZE,
++	TM0_MS_REG_BANK_SIZE,
++	TM1_MS_REG_BANK_SIZE,
++	TM2_MS_REG_BANK_SIZE,
++	TM3_MS_REG_BANK_SIZE,
++	MCU_WDT_REG_BANK_SIZE,
++	SYS_WDT_REG_BANK_SIZE,
++	GPIO_REG_BANK_SIZE,
++	SD_REG_BANK_SIZE,
++	SPI_REG_BANK_SIZE,
++	CSR_I2C_MST_BANK_SIZE,
++	UART_REG_BANK_SIZE,
++	DAT_UART_REG_BANK_SIZE,
++	INT_REG_BANK_SIZE,
++	DBG_SPI_REG_BANK_SIZE,
++	FLASH_SPI_REG_BANK_SIZE,
++	DMA_REG_BANK_SIZE,
++	CSR_PMU_BANK_SIZE,
++	CSR_RTC_BANK_SIZE,
++	RTC_RAM_BANK_SIZE,
++	D2_DMA_REG_BANK_SIZE,
++	HCI_REG_BANK_SIZE,
++	CO_REG_BANK_SIZE,
++	EFS_REG_BANK_SIZE,
++	SMS4_REG_BANK_SIZE,
++	MRX_REG_BANK_SIZE,
++	AMPDU_REG_BANK_SIZE,
++	MT_REG_CSR_BANK_SIZE,
++	TXQ0_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ1_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ2_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ3_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ4_MT_Q_REG_CSR_BANK_SIZE,
++	HIF_INFO_BANK_SIZE,
++	PHY_RATE_INFO_BANK_SIZE,
++	MAC_GLB_SET_BANK_SIZE,
++	BTCX_REG_BANK_SIZE,
++	MIB_REG_BANK_SIZE,
++	CBR_A_REG_BANK_SIZE,
++	MB_REG_BANK_SIZE,
++	ID_MNG_REG_BANK_SIZE,
++	CSR_PHY_BANK_SIZE,
++	CSR_RF_BANK_SIZE,
++	MMU_REG_BANK_SIZE,
++	0x00000000
++};
+diff --git a/drivers/net/wireless/ssv6051/include/ssv_cfg.h b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
+new file mode 100644
+index 000000000000..79b75619936e
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
+@@ -0,0 +1,60 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_CFG_H_
++#define _SSV_CFG_H_
++#define SSV6200_HW_CAP_HT 0x00000001
++#define SSV6200_HW_CAP_GF 0x00000002
++#define SSV6200_HW_CAP_2GHZ 0x00000004
++#define SSV6200_HW_CAP_5GHZ 0x00000008
++#define SSV6200_HW_CAP_SECURITY 0x00000010
++#define SSV6200_HT_CAP_SGI_20 0x00000020
++#define SSV6200_HT_CAP_SGI_40 0x00000040
++#define SSV6200_HW_CAP_AP 0x00000080
++#define SSV6200_HW_CAP_P2P 0x00000100
++#define SSV6200_HW_CAP_AMPDU_RX 0x00000200
++#define SSV6200_HW_CAP_AMPDU_TX 0x00000400
++#define SSV6200_HW_CAP_TDLS 0x00000800
++#define EXTERNEL_CONFIG_SUPPORT 64
++struct ssv6xxx_cfg {
++	u32 hw_caps;
++	u32 def_chan;
++	u32 crystal_type;
++	u32 volt_regulator;
++	u32 force_chip_identity;
++	u8 maddr[2][6];
++	u32 n_maddr;
++	u32 use_wpa2_only;
++	u32 ignore_reset_in_ap;
++	u32 r_calbration_result;
++	u32 sar_result;
++	u32 crystal_frequency_offset;
++	u32 tx_power_index_1;
++	u32 tx_power_index_2;
++	u32 chip_identity;
++	u32 wifi_tx_gain_level_gn;
++	u32 wifi_tx_gain_level_b;
++	u32 rssi_ctl;
++	u32 sr_bhvr;
++	u32 configuration[EXTERNEL_CONFIG_SUPPORT + 1][2];
++	u8 firmware_path[128];
++	u8 flash_bin_path[128];
++	u8 mac_address_path[128];
++	u8 mac_output_path[128];
++	u32 ignore_efuse_mac;
++	u32 mac_address_mode;
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
+new file mode 100644
+index 000000000000..7fabbe308f9d
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
+@@ -0,0 +1,25 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_FIRMWARE_VERSION_H_
++#define _SSV_FIRMWARE_VERSION_H_
++static u32 ssv_firmware_version = 16380;
++#define SSV_FIRMWARE_URl "http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/6051.Q0.1009.21.000000/ssv6xxx/smac/firmware"
++#define FIRMWARE_COMPILERHOST "ssv-ThinkPad-X230"
++#define FIRMWARE_COMPILERDATE "11-06-2017-09:17:18"
++#define FIRMWARE_COMPILEROS "linux"
++#define FIRMWARE_COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv_version.h b/drivers/net/wireless/ssv6051/include/ssv_version.h
+new file mode 100644
+index 000000000000..99be5354f783
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv_version.h
+@@ -0,0 +1,12 @@
++#ifndef _SSV_VERSION_H_
++#define _SSV_VERSION_H_
++
++static u32 ssv_root_version = 16529;
++
++#define SSV_ROOT_URl "http://192.168.15.30/svn/software/project/release/android/box/rk3x28/6051.Q0.1009.21.400401/ssv6xxx"
++#define COMPILERHOST "icomm-buildserver-T320"
++#define COMPILERDATE "12-08-2017-10:34:54"
++#define COMPILEROS "linux"
++#define COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
++
++#endif
+diff --git a/drivers/net/wireless/ssv6051/platform-config.mak b/drivers/net/wireless/ssv6051/platform-config.mak
+new file mode 100644
+index 000000000000..b1b6f0510d28
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/platform-config.mak
+@@ -0,0 +1,97 @@
++
++ccflags-y += -DCONFIG_SSV6200_CORE
++
++###########################################################################
++# Compiler options                                                        #
++###########################################################################
++
++# Enable -g to help debug. Deassembly from .o to .S would help to track to 
++# the problomatic line from call stack dump.
++#ccflags-y += -g
++ccflags += -Os
++
++############################################################
++# If you change the settings, please change the file synchronization
++# smac\firmware\include\config.h & compiler firmware
++############################################################
++#ccflags-y += -DCONFIG_SSV_CABRIO_A
++ccflags-y += -DCONFIG_SSV_CABRIO_E
++
++#CONFIG_SSV_SUPPORT_BTCX=y
++
++#ccflags-y += -DDEBUG
++ccflags-y += -DCONFIG_SSV6200_CLI_ENABLE
++
++#PADPD
++#ccflags-y += -DCONFIG_SSV_DPD
++
++#ccflags-y += -DCONFIG_SSV_CABRIO_MB_DEBUG
++#ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS
++
++#SDIO
++ccflags-y += -DCONFIG_SSV_TX_LOWTHRESHOLD
++
++ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
++ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
++ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
++#ccflags-y += -DMULTI_THREAD_ENCRYPT
++#ccflags-y += -DKTHREAD_BIND
++#ccflags-y += -DROCKCHIP_WIFI_AUTO_SUPPORT
++ccflags-y += -DCONFIG_SSV_RSSI
++ccflags-y += -DCONFIG_SSV_VENDOR_EXT_SUPPORT
++
++############################################################
++# Rate control update for MPDU.
++############################################################
++ccflags-y += -DRATE_CONTROL_REALTIME_UPDATA
++
++#workaround
++#ccflags-y += -DCONFIG_SSV_CABRIO_EXT_PA
++
++############################################################
++# NOTE:
++#    Only one of the following flags could be turned on.
++# It also turned off the following flags. In this case, 
++# pure software security or pure hardware security is used.
++#
++############################################################
++#ccflags-y += -DCONFIG_SSV_SW_ENCRYPT_HW_DECRYPT
++#ccflags-y += -DCONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
++
++# FOR WFA
++#ccflags-y += -DWIFI_CERTIFIED
++
++#ccflags-y += -DCONFIG_SSV_SDIO_EXT_INT
++
++#######################################################
++ccflags-y += -DCONFIG_SSV6200_HAS_RX_WORKQUEUE
++#ccflags-y += -DUSE_THREAD_RX
++ccflags-y += -DUSE_THREAD_TX
++ccflags-y += -DENABLE_AGGREGATE_IN_TIME
++ccflags-y += -DENABLE_INCREMENTAL_AGGREGATION
++
++# Generic decision table applicable to both AP and STA modes.
++ccflags-y += -DUSE_GENERIC_DECI_TBL
++
++#ccflags-y += -DCONFIG_SSV_WAPI
++
++ccflags-y += -DFW_WSID_WATCH_LIST
++#ccflags-y += -DUSE_BATCH_RX
++#ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT
++
++ccflags-y += -DSSV6200_ECO
++#ccflags-y += -DENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
++ccflags-y += -DHAS_CRYPTO_LOCK
++ccflags-y += -DENABLE_TX_Q_FLOW_CONTROL
++
++#ccflags-y += -DCONFIG_DEBUG_SKB_TIMESTAMP
++
++
++#enable p2p client to parse GO broadcast noa
++#ccflags-y += -DCONFIG_P2P_NOA
++
++#enable rx management frame check
++#ccflags-y += -DCONFIG_RX_MGMT_CHECK
++
++#force SW Broadcast/Multicast decryption
++ccflags-y += -DUSE_MAC80211_DECRYPT_BROADCAST
+\ No newline at end of file
+diff --git a/drivers/net/wireless/ssv6051/rules.mak b/drivers/net/wireless/ssv6051/rules.mak
+new file mode 100644
+index 000000000000..b3262852249c
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/rules.mak
+@@ -0,0 +1,19 @@
++
++
++$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
++obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
++
++
++.PHONY: all clean install
++
++all:
++	@$(MAKE) -C /lib/modules/$(KVERSION)/build \
++		SUBDIRS=$(KBUILD_DIR) CONFIG_DEBUG_SECTION_MISMATCH=y \
++		modules
++
++clean:
++	@$(MAKE) -C /lib/modules/$(KVERSION)/build SUBDIRS=$(KBUILD_DIR) clean
++
++install:
++	@$(MAKE) INSTALL_MOD_DIR=$(DRVPATH) -C /lib/modules/$(KVERSION)/build \
++	        M=$(KBUILD_DIR) modules_install
+diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.c b/drivers/net/wireless/ssv6051/smac/ampdu.c
+new file mode 100644
+index 000000000000..846830f3d209
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ampdu.c
+@@ -0,0 +1,2111 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ap.h"
++#include "sec.h"
++#include "ssv_rc_common.h"
++#include "ssv_ht_rc.h"
++extern struct ieee80211_ops ssv6200_ops;
++
++// Hack: redefine MAX_AMPDU_BUF because buf_size here is a 8-bit char
++// and mainline kernel value is 0x100, which overflows
++#ifdef IEEE80211_MAX_AMPDU_BUF
++#undef IEEE80211_MAX_AMPDU_BUF
++#endif
++#define IEEE80211_MAX_AMPDU_BUF 0x40
++
++#define BA_WAIT_TIMEOUT (800)
++#define AMPDU_BA_FRAME_LEN (68)
++#define ampdu_skb_hdr(skb) ((struct ieee80211_hdr*)((u8*)((skb)->data)+AMPDU_DELIMITER_LEN))
++#define ampdu_skb_ssn(skb) ((ampdu_skb_hdr(skb)->seq_ctrl)>>SSV_SEQ_NUM_SHIFT)
++#define ampdu_hdr_ssn(hdr) ((hdr)->seq_ctrl>>SSV_SEQ_NUM_SHIFT)
++#undef prn_aggr_dbg
++#define prn_aggr_dbg(fmt,...)
++static void void_func(const char *fmt, ...)
++{
++}
++
++#define prn_aggr_err(fmt,...) \
++    do { \
++        void_func(KERN_ERR fmt, ##__VA_ARGS__);\
++    } while (0)
++#define get_tid_aggr_len(agg_len,tid_data) \
++    ({ \
++        u32 agg_max_num = (tid_data)->agg_num_max; \
++        u32 to_agg_len = (agg_len); \
++        (agg_len >= agg_max_num) ? agg_max_num : to_agg_len; \
++    })
++#define INDEX_PKT_BY_SSN(tid,ssn) \
++    ((tid)->aggr_pkts[(ssn) % SSV_AMPDU_BA_WINDOW_SIZE])
++#define NEXT_PKT_SN(sn) \
++    ({ (sn + 1) % SSV_AMPDU_MAX_SSN; })
++#define INC_PKT_SN(sn) \
++    ({ \
++        sn = NEXT_PKT_SN(sn); \
++        sn; \
++    })
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++static ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
++				 char *mib_str, ssize_t length);
++static int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb);
++#endif
++static struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
++					struct AMPDU_TID_st *cur_AMPDU_TID,
++					struct sk_buff_head *retry_queue,
++					u32 max_aggr_len);
++static int _dump_BA_notification(char *buf,
++				 struct ampdu_ba_notify_data *ba_notification);
++static struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
++					struct AMPDU_TID_st *ampdu_tid,
++					u32 len);
++static bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid,
++				struct sk_buff *ampdu_skb, bool retry);
++static void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu);
++static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb);
++static u32 _flush_early_ampdu_q(struct ssv_softc *sc,
++				struct AMPDU_TID_st *ampdu_tid);
++static bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb);
++static void _aggr_ampdu_tx_q(struct ieee80211_hw *hw,
++			     struct AMPDU_TID_st *ampdu_tid);
++static void _queue_early_ampdu(struct ssv_softc *sc,
++			       struct AMPDU_TID_st *ampdu_tid,
++			       struct sk_buff *ampdu_skb);
++static int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb);
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage)
++{
++	unsigned int timeout;
++	SKB_info *mpdu_skb_info;
++	u16 ssn = 0;
++	struct sk_buff *mpdu = NULL;
++	struct ampdu_hdr_st *ampdu_hdr = NULL;
++	ktime_t current_ktime;
++	ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++	ssn = ampdu_hdr->ssn[0];
++	mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
++	if (mpdu == NULL)
++		return 0;
++	mpdu_skb_info = (SKB_info *) (mpdu->head);
++	current_ktime = ktime_get();
++	timeout =
++	    (unsigned int)
++	    ktime_to_ms(ktime_sub(current_ktime, mpdu_skb_info->timestamp));
++	if (timeout > SKB_DURATION_TIMEOUT_MS) {
++		if (stage == SKB_DURATION_STAGE_TO_SDIO)
++			pr_debug("*a_to_sdio: %ums\n", timeout);
++		else if (stage == SKB_DURATION_STAGE_TX_ENQ)
++			pr_debug("*a_to_txenqueue: %ums\n", timeout);
++		else
++			pr_debug("*a_in_hwq: %ums\n", timeout);
++	}
++	return timeout;
++}
++#endif
++static u8 _cal_ampdu_delm_half_crc(u8 value)
++{
++	u32 c32 = value, v32 = value;
++	c32 ^= (v32 >> 1) | (v32 << 7);
++	c32 ^= (v32 >> 2);
++	if (v32 & 2)
++		c32 ^= (0xC0);
++	c32 ^= ((v32 << 4) & 0x30);
++	return (u8) c32;
++}
++
++static u8 _cal_ampdu_delm_crc(u8 * pointer)
++{
++	u8 crc = 0xCF;
++	crc ^= _cal_ampdu_delm_half_crc(*pointer++);
++	crc =
++	    _cal_ampdu_delm_half_crc(crc) ^ _cal_ampdu_delm_half_crc(*pointer);
++	return ~crc;
++}
++
++static bool ssv6200_ampdu_add_delimiter_and_crc32(struct sk_buff *mpdu)
++{
++	p_AMPDU_DELIMITER delimiter_p;
++	struct ieee80211_hdr *mpdu_hdr;
++	int ret;
++	u32 orig_mpdu_len = mpdu->len;
++	u32 pad = (4 - (orig_mpdu_len % 4)) % 4;
++	mpdu_hdr = (struct ieee80211_hdr *)(mpdu->data);
++	mpdu_hdr->duration_id = AMPDU_TX_NAV_MCS_567;
++	ret = skb_padto(mpdu, mpdu->len + (AMPDU_FCS_LEN + pad));
++	if (ret) {
++		pr_err("Failed to extand skb for aggregation\n");
++		return false;
++	}
++	skb_put(mpdu, AMPDU_FCS_LEN + pad);
++	skb_push(mpdu, AMPDU_DELIMITER_LEN);
++	delimiter_p = (p_AMPDU_DELIMITER) mpdu->data;
++	delimiter_p->reserved = 0;
++	delimiter_p->length = orig_mpdu_len + AMPDU_FCS_LEN;
++	delimiter_p->signature = AMPDU_SIGNATURE;
++	delimiter_p->crc = _cal_ampdu_delm_crc((u8 *) (delimiter_p));
++	return true;
++}
++
++static void ssv6200_ampdu_hw_init(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	u32 temp32;
++	SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
++	temp32 |= (0x1 << MTX_AMPDU_CRC_AUTO_SFT);
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_MISC_EN, temp32);
++	SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
++}
++
++bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid, struct sk_buff *ampdu,
++			 bool retry)
++{
++	struct sk_buff **pp_aggr_pkt;
++	struct sk_buff *p_aggr_pkt;
++	unsigned long flags;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++	struct sk_buff *mpdu;
++	u32 first_ssn = SSV_ILLEGAL_SN;
++	u32 old_aggr_pkt_num;
++	u32 old_baw_head;
++	u32 sync_num = skb_queue_len(&ampdu_hdr->mpdu_q);
++	bool ret = true;
++	spin_lock_irqsave(&ampdu_tid->pkt_array_lock, flags);
++	old_baw_head = ampdu_tid->ssv_baw_head;
++	old_aggr_pkt_num = ampdu_tid->aggr_pkt_num;
++	ampdu_tid->mib.ampdu_mib_ampdu_counter += 1;
++	ampdu_tid->mib.ampdu_mib_dist[sync_num] += 1;
++	do {
++		if (!retry) {
++			ampdu_tid->mib.ampdu_mib_mpdu_counter += sync_num;
++			mpdu = skb_peek_tail(&ampdu_hdr->mpdu_q);
++			if (mpdu == NULL) {
++				ret = false;
++				break;
++			} else {
++				u32 ssn = ampdu_skb_ssn(mpdu);
++				p_aggr_pkt = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++				if (p_aggr_pkt != NULL) {
++					char msg[256];
++					u32 sn = ampdu_skb_ssn(mpdu);
++					skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
++						sn = ampdu_skb_ssn(mpdu);
++						sprintf(msg, " %d", sn);
++					}
++					prn_aggr_err("ES %d -> %d (%s)\n",
++						     ssn,
++						     ampdu_skb_ssn(p_aggr_pkt),
++						     msg);
++					ret = false;
++					break;
++				}
++			}
++		} else
++			ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
++		skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
++			u32 ssn = ampdu_skb_ssn(mpdu);
++			SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
++			if (first_ssn == SSV_ILLEGAL_SN)
++				first_ssn = ssn;
++			pp_aggr_pkt = &INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++			p_aggr_pkt = *pp_aggr_pkt;
++			*pp_aggr_pkt = mpdu;
++			if (!retry)
++				ampdu_tid->aggr_pkt_num++;
++			mpdu_skb_info->ampdu_tx_status = AMPDU_ST_AGGREGATED;
++			if (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN) {
++				ampdu_tid->ssv_baw_head = ssn;
++			}
++			if ((p_aggr_pkt != NULL) && (mpdu != p_aggr_pkt))
++				prn_aggr_err("%d -> %d (H%d, N%d, Q%d)\n",
++					     ssn, ampdu_skb_ssn(p_aggr_pkt),
++					     old_baw_head, old_aggr_pkt_num,
++					     sync_num);
++		}
++	} while (0);
++	spin_unlock_irqrestore(&ampdu_tid->pkt_array_lock, flags);
++	{
++		u32 page_count = (ampdu->len + SSV6200_ALLOC_RSVD);
++		if (page_count & HW_MMU_PAGE_MASK)
++			page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
++		else
++			page_count = page_count >> HW_MMU_PAGE_SHIFT;
++		if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
++			pr_err("AMPDU requires pages %d(%d-%d-%d) exceeds resource limit %d.\n",
++			       page_count, ampdu->len, ampdu_hdr->max_size,
++			       ampdu_hdr->size,
++			       (SSV6200_PAGE_TX_THRESHOLD / 2));
++	}
++	return ret;
++}
++
++struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
++				 struct AMPDU_TID_st *ampdu_tid,
++				 struct sk_buff_head *retry_queue,
++				 u32 max_aggr_len)
++{
++	struct sk_buff *retry_mpdu;
++	struct sk_buff *new_ampdu_skb;
++	u32 num_retry_mpdu;
++	u32 temp_i;
++	u32 total_skb_size;
++	unsigned long flags;
++	u16 head_ssn = ampdu_tid->ssv_baw_head;
++	struct ampdu_hdr_st *ampdu_hdr;
++	BUG_ON(head_ssn == SSV_ILLEGAL_SN);
++	num_retry_mpdu = skb_queue_len(retry_queue);
++	if (num_retry_mpdu == 0)
++		return NULL;
++	new_ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, max_aggr_len);
++	if (new_ampdu_skb == 0)
++		return NULL;
++	ampdu_hdr = (struct ampdu_hdr_st *)new_ampdu_skb->head;
++	total_skb_size = 0;
++	spin_lock_irqsave(&retry_queue->lock, flags);
++	for (temp_i = 0; temp_i < ampdu_tid->agg_num_max; temp_i++) {
++		struct ieee80211_hdr *mpdu_hdr;
++		u16 mpdu_sn;
++		u16 diff;
++		u32 new_total_skb_size;
++		retry_mpdu = skb_peek(retry_queue);
++		if (retry_mpdu == NULL) {
++			break;
++		}
++		mpdu_hdr = ampdu_skb_hdr(retry_mpdu);
++		mpdu_sn = ampdu_hdr_ssn(mpdu_hdr);
++		diff = SSV_AMPDU_SN_a_minus_b(head_ssn, mpdu_sn);
++		if ((head_ssn != SSV_ILLEGAL_SN)
++		    && (diff > 0)
++		    && (diff <= ampdu_tid->ssv_baw_size)) {
++			struct SKB_info_st *skb_info;
++			prn_aggr_err("Z. release skb (s %d, h %d, d %d)\n",
++				     mpdu_sn, head_ssn, diff);
++			skb_info = (struct SKB_info_st *)(retry_mpdu->head);
++			skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
++			ampdu_tid->mib.ampdu_mib_discard_counter++;
++			continue;
++		}
++		new_total_skb_size = total_skb_size + retry_mpdu->len;
++		if (new_total_skb_size > ampdu_hdr->max_size)
++			break;
++		total_skb_size = new_total_skb_size;
++		retry_mpdu = __skb_dequeue(retry_queue);
++		_put_mpdu_to_ampdu(new_ampdu_skb, retry_mpdu);
++		ampdu_tid->mib.ampdu_mib_retry_counter++;
++	}
++	ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
++	ampdu_tid->mib.ampdu_mib_dist[temp_i] += 1;
++	spin_unlock_irqrestore(&retry_queue->lock, flags);
++	if (ampdu_hdr->mpdu_num == 0) {
++		dev_kfree_skb_any(new_ampdu_skb);
++		return NULL;
++	}
++	return new_ampdu_skb;
++}
++
++static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
++{
++	struct ssv6200_tx_desc *tx_desc;
++	ssv6xxx_add_txinfo(sc, ampdu_skb);
++	tx_desc = (struct ssv6200_tx_desc *)ampdu_skb->data;
++	tx_desc->tx_report = 1;
++}
++
++void _send_hci_skb(struct ssv_softc *sc, struct sk_buff *skb, u32 tx_flag)
++{
++	struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	int ret = AMPDU_HCI_SEND(sc->sh, skb, tx_desc->txq_idx, tx_flag);
++	if ((tx_desc->txq_idx > 3) && (ret <= 0)) {
++		prn_aggr_err("BUG!! %d %d\n", tx_desc->txq_idx, ret);
++	}
++}
++
++static void ssv6200_ampdu_add_txinfo_and_send_HCI(struct ssv_softc *sc,
++						  struct sk_buff *ampdu_skb,
++						  u32 tx_flag)
++{
++	_add_ampdu_txinfo(sc, ampdu_skb);
++	_send_hci_skb(sc, ampdu_skb, tx_flag);
++}
++
++static void ssv6200_ampdu_send_retry(struct ieee80211_hw *hw,
++				     AMPDU_TID * cur_ampdu_tid,
++				     struct sk_buff_head
++				     *ampdu_skb_retry_queue_p,
++				     bool send_aggr_tx)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct sk_buff *ampdu_retry_skb;
++	u32 ampdu_skb_retry_queue_len;
++	u32 max_agg_len;
++	u16 lowest_rate;
++	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
++	ampdu_skb_retry_queue_len = skb_queue_len(ampdu_skb_retry_queue_p);
++	if (ampdu_skb_retry_queue_len == 0)
++		return;
++	ampdu_retry_skb = skb_peek(ampdu_skb_retry_queue_p);
++	lowest_rate = ssv62xx_ht_rate_update(ampdu_retry_skb, sc, rates);
++	max_agg_len = ampdu_max_transmit_length[lowest_rate];
++	if (max_agg_len > 0) {
++		u32 cur_ampdu_max_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
++		if (max_agg_len >= cur_ampdu_max_size)
++			max_agg_len = cur_ampdu_max_size;
++		while (ampdu_skb_retry_queue_len > 0) {
++			struct sk_buff *retry_mpdu =
++			    skb_peek(ampdu_skb_retry_queue_p);
++			SKB_info *mpdu_skb_info =
++			    (SKB_info *) (retry_mpdu->head);
++			mpdu_skb_info->lowest_rate = lowest_rate;
++			memcpy(mpdu_skb_info->rates, rates, sizeof(rates));
++			ampdu_retry_skb =
++			    _aggr_retry_mpdu(sc, cur_ampdu_tid,
++					     ampdu_skb_retry_queue_p,
++					     max_agg_len);
++			if (ampdu_retry_skb != NULL) {
++				_sync_ampdu_pkt_arr(cur_ampdu_tid,
++						    ampdu_retry_skb, true);
++				ssv6200_ampdu_add_txinfo_and_send_HCI(sc,
++								      ampdu_retry_skb,
++								      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
++			} else {
++				prn_aggr_err("AMPDU retry failed.\n");
++				return;
++			}
++			ampdu_skb_retry_queue_len =
++			    skb_queue_len(ampdu_skb_retry_queue_p);
++		}
++	} else {
++		struct ieee80211_tx_rate rates[IEEE80211_TX_MAX_RATES];
++		struct ieee80211_tx_info *info =
++		    IEEE80211_SKB_CB(ampdu_retry_skb);
++		memcpy(rates, info->control.rates, sizeof(info->control.rates));
++		while ((ampdu_retry_skb =
++			__skb_dequeue_tail(ampdu_skb_retry_queue_p)) != NULL) {
++			struct ieee80211_tx_info *info =
++			    IEEE80211_SKB_CB(ampdu_retry_skb);
++			info->flags &= ~IEEE80211_TX_CTL_AMPDU;
++			memcpy(info->control.rates, rates,
++			       sizeof(info->control.rates));
++			ssv6xxx_update_txinfo(sc, ampdu_retry_skb);
++			_send_hci_skb(sc, ampdu_retry_skb,
++				      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
++		}
++	}
++}
++
++void ssv6200_ampdu_init(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	ssv6200_ampdu_hw_init(hw);
++	sc->tx.ampdu_tx_group_id = 0;
++#ifdef USE_ENCRYPT_WORK
++	INIT_WORK(&sc->ampdu_tx_encry_work, encry_work);
++	INIT_WORK(&sc->sync_hwkey_work, sync_hw_key_work);
++#endif
++}
++
++void ssv6200_ampdu_deinit(struct ieee80211_hw *hw)
++{
++}
++
++void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw)
++{
++	ieee80211_free_txskb(hw, skb);
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++struct mib_dump_data {
++	char *prt_buff;
++	size_t buff_size;
++	size_t prt_len;
++};
++#define AMPDU_TX_MIB_SUMMARY_BUF_SIZE (4096)
++static ssize_t ampdu_tx_mib_summary_read(struct file *file,
++					 char __user * user_buf, size_t count,
++					 loff_t * ppos)
++{
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)file->private_data;
++	char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
++	ssize_t summary_size;
++	ssize_t ret;
++	if (!summary_buf)
++		return -ENOMEM;
++	summary_size = ampdu_tx_mib_dump(ssv_sta_priv, summary_buf,
++					 AMPDU_TX_MIB_SUMMARY_BUF_SIZE);
++	ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
++				      summary_size);
++	kfree(summary_buf);
++	return ret;
++}
++
++static int ampdu_tx_mib_summary_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static const struct file_operations mib_summary_fops = {.read =
++	    ampdu_tx_mib_summary_read,.open = ampdu_tx_mib_summary_open,
++};
++
++static ssize_t ampdu_tx_tid_window_read(struct file *file,
++					char __user * user_buf, size_t count,
++					loff_t * ppos)
++{
++	struct AMPDU_TID_st *ampdu_tid =
++	    (struct AMPDU_TID_st *)file->private_data;
++	char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
++	ssize_t ret;
++	char *prn_ptr = summary_buf;
++	int prt_size;
++	int buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE;
++	int i;
++	struct sk_buff *ba_skb, *tmp_ba_skb;
++	if (!summary_buf)
++		return -ENOMEM;
++	prt_size = snprintf(prn_ptr, buf_size, "\nWMM_TID %d:\n"
++			    "\tWindow:", ampdu_tid->tidno);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i++) {
++		struct sk_buff *skb = ampdu_tid->aggr_pkts[i];
++		if ((i % 8) == 0) {
++			prt_size = snprintf(prn_ptr, buf_size, "\n\t\t");
++			prn_ptr += prt_size;
++			buf_size -= prt_size;
++		}
++		if (skb == NULL)
++			prt_size = snprintf(prn_ptr, buf_size, " %s", "NULL ");
++		else {
++			struct SKB_info_st *skb_info =
++			    (struct SKB_info_st *)(skb->head);
++			const char status_symbol[] = { 'N',
++				'A',
++				'S',
++				'R',
++				'P',
++				'D'
++			};
++			prt_size =
++			    snprintf(prn_ptr, buf_size, " %4d%c",
++				     ampdu_skb_ssn(skb),
++				     ((skb_info->ampdu_tx_status <=
++				       AMPDU_ST_DONE)
++				      ? status_symbol[skb_info->ampdu_tx_status]
++				      : 'X'));
++		}
++		prn_ptr += prt_size;
++		buf_size -= prt_size;
++	}
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\n\tEarly aggregated #: %d\n",
++		     ampdu_tid->early_aggr_skb_num);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\tBAW skb #: %d\n",
++		     ampdu_tid->aggr_pkt_num);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\tBAW head: %d\n",
++		     ampdu_tid->ssv_baw_head);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\tState: %d\n", ampdu_tid->state);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size = snprintf(prn_ptr, buf_size, "\tBA:\n");
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	skb_queue_walk_safe(&ampdu_tid->ba_q, ba_skb, tmp_ba_skb) {
++		prt_size = _dump_ba_skb(prn_ptr, buf_size, ba_skb);
++		prn_ptr += prt_size;
++		buf_size -= prt_size;
++	}
++	buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE - buf_size;
++	ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
++				      buf_size);
++	kfree(summary_buf);
++	return ret;
++}
++
++static int ampdu_tx_tid_window_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static const struct file_operations tid_window_fops = {.read =
++	    ampdu_tx_tid_window_read,.open = ampdu_tx_tid_window_open,
++};
++
++static int ampdu_tx_mib_reset_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t ampdu_tx_mib_reset_read(struct file *file,
++				       char __user * user_buf, size_t count,
++				       loff_t * ppos)
++{
++	char *reset_buf = kzalloc(64, GFP_KERNEL);
++	ssize_t ret;
++	u32 reset_size;
++	if (!reset_buf)
++		return -ENOMEM;
++	reset_size = snprintf(reset_buf, 63, "%d", 0);
++	ret = simple_read_from_buffer(user_buf, count, ppos, reset_buf,
++				      reset_size);
++	kfree(reset_buf);
++	return ret;
++}
++
++static ssize_t ampdu_tx_mib_reset_write(struct file *file,
++					const char __user * buffer,
++					size_t count, loff_t * pos)
++{
++	struct AMPDU_TID_st *ampdu_tid =
++	    (struct AMPDU_TID_st *)file->private_data;
++	memset(&ampdu_tid->mib, 0, sizeof(struct AMPDU_MIB_st));
++	return count;
++}
++
++static const struct file_operations mib_reset_fops
++    = {.read = ampdu_tx_mib_reset_read,
++	.open = ampdu_tx_mib_reset_open,
++	.write = ampdu_tx_mib_reset_write
++};
++
++static void ssv6200_ampdu_tx_init_debugfs(struct ssv_softc *sc,
++					  struct ssv_sta_priv_data
++					  *ssv_sta_priv)
++{
++	struct ssv_sta_info *sta_info = ssv_sta_priv->sta_info;
++	int i;
++	struct dentry *sta_debugfs_dir = sta_info->debugfs_dir;
++	dev_info(sc->dev, "Creating AMPDU TX debugfs.\n");
++	if (sta_debugfs_dir == NULL) {
++		dev_err(sc->dev, "No STA debugfs.\n");
++		return;
++	}
++	debugfs_create_file("ampdu_tx_summary", 00444, sta_debugfs_dir,
++			    ssv_sta_priv, &mib_summary_fops);
++	debugfs_create_u32("total_BA", 00644, sta_debugfs_dir,
++			   &ssv_sta_priv->ampdu_mib_total_BA_counter);
++	for (i = 0; i < WMM_TID_NUM; i++) {
++		char debugfs_name[20];
++		struct dentry *ampdu_tx_debugfs_dir;
++		int j;
++		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
++		struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
++		snprintf(debugfs_name, sizeof(debugfs_name), "ampdu_tx_%d", i);
++		ampdu_tx_debugfs_dir = debugfs_create_dir(debugfs_name,
++							  sta_debugfs_dir);
++		if (ampdu_tx_debugfs_dir == NULL) {
++			dev_err(sc->dev,
++				"Failed to create debugfs for AMPDU TX TID %d: %s\n",
++				i, debugfs_name);
++			continue;
++		}
++		ssv_sta_priv->ampdu_tid[i].debugfs_dir = ampdu_tx_debugfs_dir;
++		debugfs_create_file("baw_status", 00444, ampdu_tx_debugfs_dir,
++				    ampdu_tid, &tid_window_fops);
++		debugfs_create_file("reset", 00644, ampdu_tx_debugfs_dir,
++				    ampdu_tid, &mib_reset_fops);
++		debugfs_create_u32("total", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_ampdu_counter);
++		debugfs_create_u32("retry", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_retry_counter);
++		debugfs_create_u32("aggr_retry", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_aggr_retry_counter);
++		debugfs_create_u32("BAR", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_bar_counter);
++		debugfs_create_u32("Discarded", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_discard_counter);
++		debugfs_create_u32("BA", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_BA_counter);
++		debugfs_create_u32("Pass", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_pass_counter);
++		for (j = 0; j <= SSV_AMPDU_aggr_num_max; j++) {
++			char dist_dbg_name[10];
++			snprintf(dist_dbg_name, sizeof(dist_dbg_name),
++				 "aggr_%d", j);
++			debugfs_create_u32(dist_dbg_name, 00444,
++					   ampdu_tx_debugfs_dir,
++					   &ampdu_mib->ampdu_mib_dist[j]);
++		}
++		skb_queue_head_init(&ssv_sta_priv->ampdu_tid[i].ba_q);
++	}
++}
++#endif
++void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
++			      struct ieee80211_sta *sta)
++{
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	struct ssv_softc *sc;
++	u32 temp_i;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	sc = (struct ssv_softc *)hw->priv;
++	for (temp_i = 0; temp_i < WMM_TID_NUM; temp_i++) {
++		ssv_sta_priv->ampdu_tid[temp_i].sta = sta;
++		ssv_sta_priv->ampdu_tid[temp_i].state = AMPDU_STATE_STOP;
++		spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].
++			       ampdu_skb_tx_queue_lock);
++		spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].pkt_array_lock);
++	}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6200_ampdu_tx_init_debugfs(sc, ssv_sta_priv);
++#endif
++}
++
++void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
++			    struct ieee80211_hw *hw, u16 * ssn)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	struct AMPDU_TID_st *ampdu_tid;
++	int i;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ampdu_tid = &ssv_sta_priv->ampdu_tid[tid];
++	ampdu_tid->ssv_baw_head = SSV_ILLEGAL_SN;
++#ifdef DEBUG_AMPDU_FLUSH
++	pr_debug("Adding %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
++	       sta->addr[0], sta->addr[1], sta->addr[2],
++	       sta->addr[3], sta->addr[4], sta->addr[5],
++	       ampdu_tid->tidno, ampdu_tid);
++	{
++		int j;
++		for (j = 0; j <= MAX_TID; j++) {
++			if (sc->tid[j] == 0)
++				break;
++		}
++		if (j == MAX_TID) {
++			dev_err(sc->dev, "No room for new TID.\n");
++		} else
++			sc->tid[j] = ampdu_tid;
++	}
++#endif
++	list_add_tail_rcu(&ampdu_tid->list, &sc->tx.ampdu_tx_que);
++	skb_queue_head_init(&ampdu_tid->ampdu_skb_tx_queue);
++	skb_queue_head_init(&ampdu_tid->early_aggr_ampdu_q);
++	ampdu_tid->early_aggr_skb_num = 0;
++	skb_queue_head_init(&ampdu_tid->ampdu_skb_wait_encry_queue);
++	skb_queue_head_init(&ampdu_tid->retry_queue);
++	skb_queue_head_init(&ampdu_tid->release_queue);
++	for (i = 0;
++	     i <
++	     (sizeof(ampdu_tid->aggr_pkts) / sizeof(ampdu_tid->aggr_pkts[0]));
++	     i++)
++		ampdu_tid->aggr_pkts[i] = 0;
++	ampdu_tid->aggr_pkt_num = 0;
++	ampdu_tid->cur_ampdu_pkt = _alloc_ampdu_skb(sc, ampdu_tid, 0);
++#ifdef AMPDU_CHECK_SKB_SEQNO
++	ssv_sta_priv->ampdu_tid[tid].last_seqno = (-1);
++#endif
++	ssv_sta_priv->ampdu_mib_total_BA_counter = 0;
++	memset(&ssv_sta_priv->ampdu_tid[tid].mib, 0,
++	       sizeof(struct AMPDU_MIB_st));
++	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_START;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	skb_queue_head_init(&ssv_sta_priv->ampdu_tid[tid].ba_q);
++#endif
++}
++
++void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
++				struct ieee80211_hw *hw, u8 buffer_size)
++{
++    struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ssv_sta_priv->ampdu_tid[tid].tidno = tid;
++	ssv_sta_priv->ampdu_tid[tid].sta = sta;
++	ssv_sta_priv->ampdu_tid[tid].agg_num_max = MAX_AGGR_NUM;
++	if (buffer_size > IEEE80211_MAX_AMPDU_BUF) {
++		buffer_size = IEEE80211_MAX_AMPDU_BUF;
++	}
++	dev_info(sc->dev, "AMPDU buffer_size=%d\n", buffer_size);
++	ssv_sta_priv->ampdu_tid[tid].ssv_baw_size = SSV_AMPDU_WINDOW_SIZE;
++	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_OPERATION;
++}
++
++static void _clear_mpdu_q(struct ieee80211_hw *hw, struct sk_buff_head *q,
++			  bool aggregated_mpdu)
++{
++	struct sk_buff *skb;
++	while (1) {
++		skb = skb_dequeue(q);
++		if (!skb)
++			break;
++		if (aggregated_mpdu)
++			skb_pull(skb, AMPDU_DELIMITER_LEN);
++		ieee80211_tx_status_skb(hw, skb);
++	}
++}
++
++void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
++			   struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	if (ssv_sta_priv->ampdu_tid[tid].state == AMPDU_STATE_STOP)
++		return;
++	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_STOP;
++	dev_dbg(sc->dev, "ssv6200_ampdu_tx_stop\n");
++	if (!list_empty(&sc->tx.ampdu_tx_que)) {
++#ifdef DEBUG_AMPDU_FLUSH
++		{
++			int j;
++			struct AMPDU_TID_st *ampdu_tid =
++			    &ssv_sta_priv->ampdu_tid[tid];
++			for (j = 0; j <= MAX_TID; j++) {
++				if (sc->tid[j] == ampdu_tid)
++					break;
++			}
++			if (j == MAX_TID) {
++				dev_dbg(sc->dev, "No TID found when deleting it.\n");
++			} else
++				sc->tid[j] = NULL;
++			dev_dbg(sc->dev, "Deleting %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
++			       sta->addr[0], sta->addr[1], sta->addr[2],
++			       sta->addr[3], sta->addr[4], sta->addr[5],
++			       ampdu_tid->tidno, ampdu_tid);
++		}
++#endif
++		list_del_rcu(&ssv_sta_priv->ampdu_tid[tid].list);
++	}
++	dev_dbg(sc->dev, "clear tx q len=%d\n",
++	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue));
++	_clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue,
++		      true);
++	dev_dbg(sc->dev, "clear retry q len=%d\n",
++	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].retry_queue));
++	_clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].retry_queue, true);
++#ifdef USE_ENCRYPT_WORK
++	dev_dbg(sc->dev, "clear encrypt q len=%d\n",
++	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].
++			     ampdu_skb_wait_encry_queue));
++	_clear_mpdu_q(sc->hw,
++		      &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_wait_encry_queue,
++		      false);
++#endif
++	if (ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt != NULL) {
++		dev_kfree_skb_any(ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt);
++		ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt = NULL;
++	}
++	ssv6200_tx_flow_control((void *)sc,
++				sc->tx.hw_txqid[ssv_sta_priv->ampdu_tid[tid].
++						ac], false, 1000);
++}
++
++static void ssv6200_ampdu_tx_state_stop_func(struct ssv_softc *sc,
++					     struct ieee80211_sta *sta,
++					     struct sk_buff *skb,
++					     struct AMPDU_TID_st *cur_AMPDU_TID)
++{
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++	u8 *skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
++	u8 tid_no = skb_qos_ctl[0] & 0xf;
++	if ((sta->deflink.ht_cap.ht_supported == true)
++	    && (!!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
++		ieee80211_start_tx_ba_session(sta, tid_no, 0);
++		ampdu_db_log("start ampdu_tx(rc) : tid_no = %d\n", tid_no);
++	}
++}
++
++static void ssv6200_ampdu_tx_state_operation_func(struct ssv_softc *sc,
++						  struct ieee80211_sta *sta,
++						  struct sk_buff *skb,
++						  struct AMPDU_TID_st
++						  *cur_AMPDU_TID)
++{
++}
++
++void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
++				   struct sk_buff *skb)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)priv;
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++	u8 *skb_qos_ctl;
++	u8 tid_no;
++	{
++		skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
++		tid_no = skb_qos_ctl[0] & 0xf;
++		switch (ssv_sta_priv->ampdu_tid[tid_no].state) {
++		case AMPDU_STATE_STOP:
++			ssv6200_ampdu_tx_state_stop_func(sc, sta, skb,
++							 &(ssv_sta_priv->
++							   ampdu_tid[tid_no]));
++			break;
++		case AMPDU_STATE_START:
++			break;
++		case AMPDU_STATE_OPERATION:
++			ssv6200_ampdu_tx_state_operation_func(sc, sta, skb,
++							      &(ssv_sta_priv->
++								ampdu_tid
++								[tid_no]));
++			break;
++		default:
++			break;
++		}
++	}
++}
++
++void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu)
++{
++	bool is_empty_ampdu = (ampdu->len == 0);
++	unsigned char *data_dest;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++	BUG_ON(skb_tailroom(ampdu) < mpdu->len);
++	data_dest = skb_tail_pointer(ampdu);
++	skb_put(ampdu, mpdu->len);
++	if (is_empty_ampdu) {
++		struct ieee80211_tx_info *ampdu_info = IEEE80211_SKB_CB(ampdu);
++		struct ieee80211_tx_info *mpdu_info = IEEE80211_SKB_CB(mpdu);
++		SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
++		u32 max_size_for_rate =
++		    ampdu_max_transmit_length[mpdu_skb_info->lowest_rate];
++		BUG_ON(max_size_for_rate == 0);
++		memcpy(ampdu_info, mpdu_info, sizeof(struct ieee80211_tx_info));
++		skb_set_queue_mapping(ampdu, skb_get_queue_mapping(mpdu));
++		ampdu_hdr->first_sn = ampdu_skb_ssn(mpdu);
++		ampdu_hdr->sta = ((struct SKB_info_st *)mpdu->head)->sta;
++		if (ampdu_hdr->max_size > max_size_for_rate)
++			ampdu_hdr->max_size = max_size_for_rate;
++		memcpy(ampdu_hdr->rates, mpdu_skb_info->rates,
++		       sizeof(ampdu_hdr->rates));
++	}
++	memcpy(data_dest, mpdu->data, mpdu->len);
++	__skb_queue_tail(&ampdu_hdr->mpdu_q, mpdu);
++	ampdu_hdr->ssn[ampdu_hdr->mpdu_num++] = ampdu_skb_ssn(mpdu);
++	ampdu_hdr->size += mpdu->len;
++	BUG_ON(ampdu_hdr->size > ampdu_hdr->max_size);
++}
++
++u32 _flush_early_ampdu_q(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid)
++{
++	u32 flushed_ampdu = 0;
++	unsigned long flags;
++	struct sk_buff_head *early_aggr_ampdu_q =
++	    &ampdu_tid->early_aggr_ampdu_q;
++	spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++	while (skb_queue_len(early_aggr_ampdu_q)) {
++		struct sk_buff *head_ampdu;
++		struct ampdu_hdr_st *head_ampdu_hdr;
++		u32 ampdu_aggr_num;
++		head_ampdu = skb_peek(early_aggr_ampdu_q);
++		head_ampdu_hdr = (struct ampdu_hdr_st *)head_ampdu->head;
++		ampdu_aggr_num = skb_queue_len(&head_ampdu_hdr->mpdu_q);
++		if ((SSV_AMPDU_BA_WINDOW_SIZE - ampdu_tid->aggr_pkt_num)
++		    < ampdu_aggr_num)
++			break;
++		if (_sync_ampdu_pkt_arr(ampdu_tid, head_ampdu, false)) {
++			head_ampdu = __skb_dequeue(early_aggr_ampdu_q);
++			ampdu_tid->early_aggr_skb_num -= ampdu_aggr_num;
++#ifdef SSV_AMPDU_FLOW_CONTROL
++			if (ampdu_tid->early_aggr_skb_num
++			    <= SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND) {
++				ssv6200_tx_flow_control((void *)sc,
++							sc->tx.
++							hw_txqid[ampdu_tid->ac],
++							false, 1000);
++			}
++#endif
++			if ((skb_queue_len(early_aggr_ampdu_q) == 0)
++			    && (ampdu_tid->early_aggr_skb_num > 0)) {
++				dev_warn(sc->dev, "Empty early Q w. %d.\n",
++				       ampdu_tid->early_aggr_skb_num);
++			}
++			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
++					       flags);
++			_send_hci_skb(sc, head_ampdu,
++				      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
++			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++			flushed_ampdu++;
++		} else
++			break;
++	}
++	spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
++	return flushed_ampdu;
++}
++
++volatile int max_aggr_num = 24;
++void _aggr_ampdu_tx_q(struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct sk_buff *ampdu_skb = ampdu_tid->cur_ampdu_pkt;
++	while (skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue)) {
++		u32 aggr_len;
++		struct sk_buff *mpdu_skb;
++		struct ampdu_hdr_st *ampdu_hdr;
++		bool is_aggr_full = false;
++		if (ampdu_skb == NULL) {
++			ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, 0);
++			if (ampdu_skb == NULL)
++				break;
++			ampdu_tid->cur_ampdu_pkt = ampdu_skb;
++		}
++		ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++		aggr_len = skb_queue_len(&ampdu_hdr->mpdu_q);
++		do {
++			struct sk_buff_head *tx_q =
++			    &ampdu_tid->ampdu_skb_tx_queue;
++			unsigned long flags;
++			spin_lock_irqsave(&tx_q->lock, flags);
++			mpdu_skb = skb_peek(&ampdu_tid->ampdu_skb_tx_queue);
++			if (mpdu_skb == NULL) {
++				spin_unlock_irqrestore(&tx_q->lock, flags);
++				break;
++			}
++			if ((mpdu_skb->len + ampdu_hdr->size) >
++			    ampdu_hdr->max_size) {
++				is_aggr_full = true;
++				spin_unlock_irqrestore(&tx_q->lock, flags);
++				break;
++			}
++			mpdu_skb =
++			    __skb_dequeue(&ampdu_tid->ampdu_skb_tx_queue);
++			spin_unlock_irqrestore(&tx_q->lock, flags);
++			_put_mpdu_to_ampdu(ampdu_skb, mpdu_skb);
++		} while (++aggr_len < max_aggr_num);
++		if ((is_aggr_full || (aggr_len >= max_aggr_num))
++		    || ((aggr_len > 0)
++			&& (skb_queue_len(&ampdu_tid->early_aggr_ampdu_q) == 0)
++			&& (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN)
++			&& _is_skb_q_empty(sc, ampdu_skb))) {
++			_add_ampdu_txinfo(sc, ampdu_skb);
++			_queue_early_ampdu(sc, ampdu_tid, ampdu_skb);
++			ampdu_tid->cur_ampdu_pkt = ampdu_skb = NULL;
++		}
++		_flush_early_ampdu_q(sc, ampdu_tid);
++	}
++}
++
++void _queue_early_ampdu(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid,
++			struct sk_buff *ampdu_skb)
++{
++	unsigned long flags;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++	spin_lock_irqsave(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
++	__skb_queue_tail(&ampdu_tid->early_aggr_ampdu_q, ampdu_skb);
++	ampdu_tid->early_aggr_skb_num += skb_queue_len(&ampdu_hdr->mpdu_q);
++#ifdef SSV_AMPDU_FLOW_CONTROL
++	if (ampdu_tid->early_aggr_skb_num >= SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND) {
++		ssv6200_tx_flow_control((void *)sc,
++					sc->tx.hw_txqid[ampdu_tid->ac], true,
++					1000);
++	}
++#endif
++	spin_unlock_irqrestore(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
++}
++
++void _flush_mpdu(struct ssv_softc *sc, struct ieee80211_sta *sta)
++{
++	unsigned long flags;
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	int i;
++	for (i = 0;
++	     i <
++	     (sizeof(ssv_sta_priv->ampdu_tid) /
++	      sizeof(ssv_sta_priv->ampdu_tid[0])); i++) {
++		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
++		struct sk_buff_head *early_aggr_ampdu_q;
++		struct sk_buff *ampdu;
++		struct ampdu_hdr_st *ampdu_hdr;
++		struct sk_buff_head *mpdu_q;
++		struct sk_buff *mpdu;
++		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++			continue;
++		early_aggr_ampdu_q = &ampdu_tid->early_aggr_ampdu_q;
++		spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++		while ((ampdu = __skb_dequeue(early_aggr_ampdu_q)) != NULL) {
++			ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++			mpdu_q = &ampdu_hdr->mpdu_q;
++			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
++					       flags);
++			while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
++				_send_hci_skb(sc, mpdu,
++					      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
++			}
++			ssv6200_ampdu_release_skb(ampdu, sc->hw);
++			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++		}
++		if (ampdu_tid->cur_ampdu_pkt != NULL) {
++			ampdu_hdr =
++			    (struct ampdu_hdr_st *)ampdu_tid->cur_ampdu_pkt->
++			    head;
++			mpdu_q = &ampdu_hdr->mpdu_q;
++			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
++					       flags);
++			while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
++				_send_hci_skb(sc, mpdu,
++					      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
++			}
++			ssv6200_ampdu_release_skb(ampdu_tid->cur_ampdu_pkt,
++						  sc->hw);
++			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++			ampdu_tid->cur_ampdu_pkt = NULL;
++		}
++		spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
++	}
++}
++
++bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++#ifdef REPORT_TX_STATUS_DIRECTLY
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct sk_buff *tx_skb = skb;
++	struct sk_buff *copy_skb = NULL;
++#endif
++	struct SKB_info_st *mpdu_skb_info_p = (SKB_info *) (skb->head);
++	struct ieee80211_sta *sta = mpdu_skb_info_p->sta;
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	u8 tidno;
++	struct AMPDU_TID_st *ampdu_tid;
++	if (sta == NULL) {
++		WARN_ON(1);
++		return false;
++	}
++	tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
++	ampdu_db_log("tidno = %d\n", tidno);
++	ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
++	if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++		return false;
++#ifdef AMPDU_CHECK_SKB_SEQNO
++	{
++		u32 skb_seqno = ((struct ieee80211_hdr *)(skb->data))->seq_ctrl
++		    >> SSV_SEQ_NUM_SHIFT;
++		u32 tid_seqno = ampdu_tid->last_seqno;
++		if ((tid_seqno != (-1))
++		    && (skb_seqno != NEXT_PKT_SN(tid_seqno))) {
++			prn_aggr_err("Non continueous seq no: %d - %d\n",
++				     tid_seqno, skb_seqno);
++			return false;
++		}
++		ampdu_tid->last_seqno = skb_seqno;
++	}
++#endif
++	mpdu_skb_info_p->lowest_rate =
++	    ssv62xx_ht_rate_update(skb, sc, mpdu_skb_info_p->rates);
++	if (ampdu_max_transmit_length[mpdu_skb_info_p->lowest_rate] == 0) {
++		_flush_mpdu(sc, sta);
++		return false;
++	}
++	mpdu_skb_info_p = (SKB_info *) (skb->head);
++	mpdu_skb_info_p->mpdu_retry_counter = 0;
++	mpdu_skb_info_p->ampdu_tx_status = AMPDU_ST_NON_AMPDU;
++	mpdu_skb_info_p->ampdu_tx_final_retry_count = 0;
++	ssv_sta_priv->ampdu_tid[tidno].ac = skb_get_queue_mapping(skb);
++#ifdef REPORT_TX_STATUS_DIRECTLY
++	info->flags |= IEEE80211_TX_STAT_ACK;
++	copy_skb = skb_copy(tx_skb, GFP_ATOMIC);
++	if (!copy_skb) {
++		dev_err(sc->dev, "create TX skb copy failed!\n");
++		return false;
++	}
++	ieee80211_tx_status_skb(sc->hw, tx_skb);
++	skb = copy_skb;
++#endif
++	{
++		bool ret;
++		ret = ssv6200_ampdu_add_delimiter_and_crc32(skb);
++		if (ret == false) {
++			ssv6200_ampdu_release_skb(skb, hw);
++			return false;
++		}
++		skb_queue_tail(&ssv_sta_priv->ampdu_tid[tidno].
++			       ampdu_skb_tx_queue, skb);
++		ssv_sta_priv->ampdu_tid[tidno].timestamp = jiffies;
++	}
++	_aggr_ampdu_tx_q(hw, &ssv_sta_priv->ampdu_tid[tidno]);
++	return true;
++}
++
++u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct AMPDU_TID_st *cur_AMPDU_TID;
++	u32 flushed_ampdu = 0;
++	u32 tid_idx = 0;
++	if (!list_empty(&sc->tx.ampdu_tx_que)) {
++		list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
++					list) {
++			tid_idx++;
++#ifdef DEBUG_AMPDU_FLUSH
++			{
++				int i = 0;
++				for (i = 0; i < MAX_TID; i++)
++					if (sc->tid[i] == cur_AMPDU_TID)
++						break;
++				if (i == MAX_TID) {
++					dev_err(sc->dev, "No matching TID (%d) found! %p\n",
++					       tid_idx, cur_AMPDU_TID);
++					continue;
++				}
++			}
++#endif
++			if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION) {
++				struct ieee80211_sta *sta = cur_AMPDU_TID->sta;
++				struct ssv_sta_priv_data *sta_priv =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++				dev_dbg(sc->dev, "STA %d TID %d is @%d\n",
++					sta_priv->sta_idx, cur_AMPDU_TID->tidno,
++					cur_AMPDU_TID->state);
++				continue;
++			}
++			if ((cur_AMPDU_TID->state == AMPDU_STATE_OPERATION)
++			    &&
++			    (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q)
++			     == 0)
++			    && (cur_AMPDU_TID->cur_ampdu_pkt != NULL)) {
++				struct ampdu_hdr_st *ampdu_hdr =
++				    (struct ampdu_hdr_st *)(cur_AMPDU_TID->
++							    cur_ampdu_pkt->
++							    head);
++				u32 aggr_len =
++				    skb_queue_len(&ampdu_hdr->mpdu_q);
++				if (aggr_len) {
++					struct sk_buff *ampdu_skb =
++					    cur_AMPDU_TID->cur_ampdu_pkt;
++					cur_AMPDU_TID->cur_ampdu_pkt = NULL;
++					_add_ampdu_txinfo(sc, ampdu_skb);
++					_queue_early_ampdu(sc, cur_AMPDU_TID,
++							   ampdu_skb);
++				}
++			}
++			if (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q) >
++			    0)
++				flushed_ampdu +=
++				    _flush_early_ampdu_q(sc, cur_AMPDU_TID);
++		}
++	}
++	return flushed_ampdu;
++}
++
++int _dump_BA_notification(char *buf,
++			  struct ampdu_ba_notify_data *ba_notification)
++{
++	int i;
++	char *orig_buf = buf;
++	for (i = 0; i < MAX_AGGR_NUM; i++) {
++		if (ba_notification->seq_no[i] == (u16) (-1))
++			break;
++		buf += sprintf(buf, " %d", ba_notification->seq_no[i]);
++	}
++	return ((size_t)buf - (size_t)orig_buf);
++}
++
++int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb)
++{
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(ba_skb->data
++							     +
++							     SSV6XXX_RX_DESC_LEN);
++	AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
++	u32 ssn = BA_frame->BA_ssn;
++	struct ampdu_ba_notify_data *ba_notification =
++	    (struct ampdu_ba_notify_data *)(ba_skb->data + ba_skb->len
++					    -
++					    sizeof(struct
++						   ampdu_ba_notify_data));
++	int prt_size;
++	prt_size = snprintf(buf, buf_size, "\n\t\t%04d %08X %08X -",
++			    ssn, BA_frame->BA_sn_bit_map[0],
++			    BA_frame->BA_sn_bit_map[1]);
++	buf_size -= prt_size;
++	buf += prt_size;
++	prt_size = prt_size + _dump_BA_notification(buf, ba_notification);
++	return prt_size;
++}
++
++static bool _ssn_to_bit_idx(u32 start_ssn, u32 mpdu_ssn, u32 * word_idx,
++			    u32 * bit_idx)
++{
++	u32 ret_bit_idx, ret_word_idx = 0;
++	s32 diff = mpdu_ssn - start_ssn;
++	if (diff >= 0) {
++		if (diff >= SSV_AMPDU_BA_WINDOW_SIZE) {
++			return false;
++		}
++		ret_bit_idx = diff;
++	} else {
++		diff = -diff;
++		if (diff <= (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
++			*word_idx = 0;
++			*bit_idx = 0;
++			return false;
++		}
++		ret_bit_idx = SSV_AMPDU_MAX_SSN - diff;
++	}
++	if (ret_bit_idx >= 32) {
++		ret_bit_idx -= 32;
++		ret_word_idx = 1;
++	}
++	*bit_idx = ret_bit_idx;
++	*word_idx = ret_word_idx;
++	return true;
++}
++
++static bool _inc_bit_idx(u32 ssn_1st, u32 ssn_next, u32 * word_idx,
++			 u32 * bit_idx)
++{
++	u32 ret_word_idx = *word_idx, ret_bit_idx = *bit_idx;
++	s32 diff = (s32) ssn_1st - (s32) ssn_next;
++	if (diff > 0) {
++		if (diff < (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
++			prn_aggr_err
++			    ("Irrational SN distance in AMPDU: %d %d.\n",
++			     ssn_1st, ssn_next);
++			return false;
++		}
++		diff = SSV_AMPDU_MAX_SSN - diff;
++	} else {
++		diff = -diff;
++	}
++	if (diff > SSV_AMPDU_MAX_SSN)
++		prn_aggr_err("DF %d - %d = %d\n", ssn_1st, ssn_next, diff);
++	ret_bit_idx += diff;
++	if (ret_bit_idx >= 32) {
++		ret_bit_idx -= 32;
++		ret_word_idx++;
++	}
++	*word_idx = ret_word_idx;
++	*bit_idx = ret_bit_idx;
++	return true;
++}
++
++static void _release_frames(struct AMPDU_TID_st *ampdu_tid)
++{
++	u32 head_ssn, head_ssn_before, last_ssn;
++	struct sk_buff **skb;
++	struct SKB_info_st *skb_info;
++	spin_lock_bh(&ampdu_tid->pkt_array_lock);
++	head_ssn_before = ampdu_tid->ssv_baw_head;
++	if (head_ssn_before >= SSV_AMPDU_MAX_SSN) {
++		spin_unlock_bh(&ampdu_tid->pkt_array_lock);
++		prn_aggr_err("l x.x %d\n", head_ssn_before);
++		return;
++	}
++	head_ssn = ampdu_tid->ssv_baw_head;
++	last_ssn = head_ssn;
++	do {
++		skb = &INDEX_PKT_BY_SSN(ampdu_tid, head_ssn);
++		if (*skb == NULL) {
++			head_ssn = SSV_ILLEGAL_SN;
++			{
++				int i;
++				char sn_str[66 * 5] = "";
++				char *str = sn_str;
++				for (i = 0; i < 64; i++)
++					if (ampdu_tid->aggr_pkts[i] != NULL) {
++						str += sprintf(str, "%d ",
++							       ampdu_skb_ssn
++							       (ampdu_tid->
++								aggr_pkts[i]));
++					}
++				*str = 0;
++				if (str == sn_str) {
++				} else
++					prn_aggr_err("ILL %d %d - %d (%s)\n",
++						     head_ssn_before, last_ssn,
++						     ampdu_tid->aggr_pkt_num,
++						     sn_str);
++			}
++			break;
++		}
++		skb_info = (struct SKB_info_st *)((*skb)->head);
++		if ((skb_info->ampdu_tx_status == AMPDU_ST_DONE)
++		    || (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)) {
++			__skb_queue_tail(&ampdu_tid->release_queue, *skb);
++			*skb = NULL;
++			last_ssn = head_ssn;
++			INC_PKT_SN(head_ssn);
++			ampdu_tid->aggr_pkt_num--;
++			if (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)
++				ampdu_tid->mib.ampdu_mib_discard_counter++;
++		} else {
++			break;
++		}
++	} while (1);
++	ampdu_tid->ssv_baw_head = head_ssn;
++	spin_unlock_bh(&ampdu_tid->pkt_array_lock);
++}
++
++static int _collect_retry_frames(struct AMPDU_TID_st *ampdu_tid)
++{
++	u16 ssn, head_ssn, end_ssn;
++	int num_retry = 0;
++	int timeout_check = 1;
++	unsigned long check_jiffies = jiffies;
++	head_ssn = ampdu_tid->ssv_baw_head;
++	ssn = head_ssn;
++	if (ssn == SSV_ILLEGAL_SN)
++		return 0;
++	end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
++	do {
++		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		struct SKB_info_st *skb_info;
++		int timeout_retry = 0;
++		if (skb == NULL)
++			break;
++		skb_info = (SKB_info *) (skb->head);
++		if (timeout_check
++		    && (skb_info->ampdu_tx_status == AMPDU_ST_SENT)) {
++			unsigned long cur_jiffies = jiffies;
++			unsigned long timeout_jiffies = skb_info->aggr_timestamp
++			    + msecs_to_jiffies(BA_WAIT_TIMEOUT);
++			u32 delta_ms;
++			if (time_before(cur_jiffies, timeout_jiffies)) {
++				timeout_check = 0;
++				continue;
++			}
++			_mark_skb_retry(skb_info, skb);
++			delta_ms =
++			    jiffies_to_msecs(cur_jiffies -
++					     skb_info->aggr_timestamp);
++			prn_aggr_err("t S%d-T%d-%d (%u)\n",
++				     ((struct ssv_sta_priv_data *)skb_info->
++				      sta->drv_priv)->sta_idx, ampdu_tid->tidno,
++				     ssn, delta_ms);
++			if (delta_ms > 1000) {
++				prn_aggr_err("Last checktime %lu - %lu = %u\n",
++					     check_jiffies,
++					     ampdu_tid->timestamp,
++					     jiffies_to_msecs(check_jiffies -
++							      ampdu_tid->
++							      timestamp));
++			}
++			timeout_retry = 1;
++		}
++		if (skb_info->ampdu_tx_status == AMPDU_ST_RETRY) {
++			skb_queue_tail(&ampdu_tid->retry_queue, skb);
++			ampdu_tid->mib.ampdu_mib_retry_counter++;
++			num_retry++;
++		}
++		INC_PKT_SN(ssn);
++	} while (ssn != end_ssn);
++	ampdu_tid->timestamp = check_jiffies;
++	return num_retry;
++}
++
++int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb)
++{
++	if (skb_info->mpdu_retry_counter < SSV_AMPDU_retry_counter_max) {
++		if (skb_info->mpdu_retry_counter == 0) {
++			struct ieee80211_hdr *skb_hdr = ampdu_skb_hdr(skb);
++			skb_hdr->frame_control |=
++			    cpu_to_le16(IEEE80211_FCTL_RETRY);
++		}
++		skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
++		skb_info->mpdu_retry_counter++;
++		return 1;
++	} else {
++		skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
++		prn_aggr_err("p %d\n", ampdu_skb_ssn(skb));
++		return 0;
++	}
++}
++
++static u32 _ba_map_walker(struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,
++			  u32 sn_bit_map[2],
++			  struct ampdu_ba_notify_data *ba_notify_data,
++			  u32 * p_acked_num)
++{
++	int i = 0;
++	u32 ssn = ba_notify_data->seq_no[0];
++	u32 word_idx = (-1), bit_idx = (-1);
++	bool found = _ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx);
++	bool first_found = found;
++	u32 aggr_num = 0;
++	u32 acked_num = 0;
++	if (found && (word_idx >= 2 || bit_idx >= 32))
++		prn_aggr_err("idx error 1: %d %d %d %d\n",
++			     start_ssn, ssn, word_idx, bit_idx);
++	while ((i < MAX_AGGR_NUM) && (ssn < SSV_AMPDU_MAX_SSN)) {
++		u32 cur_ssn;
++		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		u32 skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
++		struct SKB_info_st *skb_info;
++		aggr_num++;
++		if (skb_ssn != ssn) {
++			prn_aggr_err("Unmatched SSN packet: %d - %d - %d\n",
++				     ssn, skb_ssn, start_ssn);
++		} else {
++			skb_info = (struct SKB_info_st *)(skb->head);
++			if (found && (sn_bit_map[word_idx] & (1 << bit_idx))) {
++				if (skb_info->ampdu_tx_status != AMPDU_ST_SENT) {
++					pr_err("BA marks a MPDU of status %d!\n",
++					       skb_info->ampdu_tx_status);
++				}
++				skb_info->ampdu_tx_status = AMPDU_ST_DONE;
++				acked_num++;
++			} else {
++				_mark_skb_retry(skb_info, skb);
++			}
++		}
++		cur_ssn = ssn;
++		if (++i >= MAX_AGGR_NUM)
++			break;
++		ssn = ba_notify_data->seq_no[i];
++		if (ssn >= SSV_AMPDU_MAX_SSN)
++			break;
++		if (first_found) {
++			u32 old_word_idx = word_idx, old_bit_idx = bit_idx;
++			found = _inc_bit_idx(cur_ssn, ssn, &word_idx, &bit_idx);
++			if (found && (word_idx >= 2 || bit_idx >= 32)) {
++				prn_aggr_err
++				    ("idx error 2: %d 0x%08X 0X%08X %d %d (%d %d) (%d %d)\n",
++				     start_ssn, sn_bit_map[1], sn_bit_map[0],
++				     cur_ssn, ssn, word_idx, bit_idx,
++				     old_word_idx, old_bit_idx);
++				found = false;
++			} else if (!found) {
++				char strbuf[256];
++				_dump_BA_notification(strbuf, ba_notify_data);
++				prn_aggr_err("SN out-of-order: %d\n%s\n",
++					     start_ssn, strbuf);
++			}
++		} else {
++			found =
++			    _ssn_to_bit_idx(start_ssn, ssn, &word_idx,
++					    &bit_idx);
++			first_found = found;
++			if (found && (word_idx >= 2 || bit_idx >= 32))
++				prn_aggr_err("idx error 3: %d %d %d %d\n",
++					     cur_ssn, ssn, word_idx, bit_idx);
++		}
++	}
++	_release_frames(ampdu_tid);
++	if (p_acked_num != NULL)
++		*p_acked_num = acked_num;
++	return aggr_num;
++}
++
++static void _flush_release_queue(struct ieee80211_hw *hw,
++				 struct sk_buff_head *release_queue)
++{
++	do {
++		struct sk_buff *ampdu_skb = __skb_dequeue(release_queue);
++		struct ieee80211_tx_info *tx_info;
++		struct SKB_info_st *skb_info;
++		if (ampdu_skb == NULL)
++			break;
++		skb_info = (struct SKB_info_st *)(ampdu_skb->head);
++		skb_pull(ampdu_skb, AMPDU_DELIMITER_LEN);
++		tx_info = IEEE80211_SKB_CB(ampdu_skb);
++		ieee80211_tx_info_clear_status(tx_info);
++		tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
++		if (skb_info->ampdu_tx_status == AMPDU_ST_DONE)
++			tx_info->flags |= IEEE80211_TX_STAT_ACK;
++		tx_info->status.ampdu_len = 1;
++		tx_info->status.ampdu_ack_len = 1;
++#ifdef REPORT_TX_STATUS_DIRECTLY
++		dev_kfree_skb_any(ampdu_skb);
++#else
++#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_TX_DATA)
++		ieee80211_tx_status_skb(hw, ampdu_skb);
++#else
++		ieee80211_tx_status_irqsafe(hw, ampdu_skb);
++#endif
++#endif
++	} while (1);
++}
++
++void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct cfg_host_event *host_event = (struct cfg_host_event *)skb->data;
++	struct ampdu_ba_notify_data *ba_notification =
++	    (struct ampdu_ba_notify_data *)&host_event->dat[0];
++	struct ieee80211_hdr *hdr =
++	    (struct ieee80211_hdr *)(ba_notification + 1);
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_sta *sta = ssv6xxx_find_sta_by_addr(sc, hdr->addr1);
++	u8 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	char seq_str[256];
++	struct AMPDU_TID_st *ampdu_tid;
++	int i;
++	u16 aggr_num = 0;
++	struct firmware_rate_control_report_data *report_data;
++	if (sta == NULL) {
++		prn_aggr_err
++		    ("NO BA for %d to unmatched STA %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
++		     tidno, hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
++		     hdr->addr1[3], hdr->addr1[4], hdr->addr1[5], seq_str);
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	_dump_BA_notification(seq_str, ba_notification);
++	prn_aggr_err("NO BA for %d to %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
++		     tidno, sta->addr[0], sta->addr[1], sta->addr[2],
++		     sta->addr[3], sta->addr[4], sta->addr[5], seq_str);
++	ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
++	if (ampdu_tid->state != AMPDU_STATE_OPERATION) {
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	for (i = 0; i < MAX_AGGR_NUM; i++) {
++		u32 ssn = ba_notification->seq_no[i];
++		struct sk_buff *skb;
++		u32 skb_ssn;
++		struct SKB_info_st *skb_info;
++		if (ssn >= (4096))
++			break;
++		aggr_num++;
++		skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
++		if (skb_ssn != ssn) {
++			prn_aggr_err("Unmatched SSN packet: %d - %d\n", ssn,
++				     skb_ssn);
++			continue;
++		}
++		skb_info = (struct SKB_info_st *)(skb->head);
++		if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
++			if (skb_info->mpdu_retry_counter <
++			    SSV_AMPDU_retry_counter_max) {
++				if (skb_info->mpdu_retry_counter == 0) {
++					struct ieee80211_hdr *skb_hdr =
++					    ampdu_skb_hdr(skb);
++					skb_hdr->frame_control |=
++					    cpu_to_le16(IEEE80211_FCTL_RETRY);
++				}
++				skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
++				skb_info->mpdu_retry_counter++;
++			} else {
++				skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
++				prn_aggr_err("p %d\n", skb_ssn);
++			}
++		} else {
++			prn_aggr_err("S %d %d\n", skb_ssn,
++				     skb_info->ampdu_tx_status);
++		}
++	}
++	_release_frames(ampdu_tid);
++	host_event->h_event = SOC_EVT_RC_AMPDU_REPORT;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
++	report_data->ampdu_len = aggr_num;
++	report_data->ampdu_ack_len = 0;
++	report_data->wsid = ssv_sta_priv->sta_info->hw_wsid;
++	skb_queue_tail(&sc->rc_report_queue, skb);
++	if (sc->rc_sample_sechedule == 0)
++		queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
++}
++
++void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data
++							     +
++							     SSV6XXX_RX_DESC_LEN);
++	AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
++	struct ieee80211_sta *sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	struct ampdu_ba_notify_data *ba_notification;
++	u32 ssn, aggr_num = 0, acked_num = 0;
++	u8 tid_no;
++	u32 sn_bit_map[2];
++	struct firmware_rate_control_report_data *report_data;
++	HDR_HostEvent *host_evt;
++	sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
++	if (sta == NULL) {
++		if (skb->len > AMPDU_BA_FRAME_LEN) {
++			char strbuf[256];
++			struct ampdu_ba_notify_data *ba_notification =
++			    (struct ampdu_ba_notify_data *)(skb->data + skb->len
++							    -
++							    sizeof(struct
++								   ampdu_ba_notify_data));
++			_dump_BA_notification(strbuf, ba_notification);
++			prn_aggr_err
++			    ("BA from not connected STA (%02X-%02X-%02X-%02X-%02X-%02X) (%s)\n",
++			     BA_frame->ta_addr[0], BA_frame->ta_addr[1],
++			     BA_frame->ta_addr[2], BA_frame->ta_addr[3],
++			     BA_frame->ta_addr[4], BA_frame->ta_addr[5],
++			     strbuf);
++		}
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ssn = BA_frame->BA_ssn;
++	sn_bit_map[0] = BA_frame->BA_sn_bit_map[0];
++	sn_bit_map[1] = BA_frame->BA_sn_bit_map[1];
++	tid_no = BA_frame->tid_info;
++	ssv_sta_priv->ampdu_mib_total_BA_counter++;
++	if (ssv_sta_priv->ampdu_tid[tid_no].state == AMPDU_STATE_STOP) {
++		prn_aggr_err
++		    ("ssv6200_ampdu_BA_handler state == AMPDU_STATE_STOP.\n");
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ssv_sta_priv->ampdu_tid[tid_no].mib.ampdu_mib_BA_counter++;
++	if (skb->len <= AMPDU_BA_FRAME_LEN) {
++		prn_aggr_err("b %d\n", ssn);
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ba_notification =
++	    (struct ampdu_ba_notify_data *)(skb->data + skb->len
++					    -
++					    sizeof(struct
++						   ampdu_ba_notify_data));
++	aggr_num =
++	    _ba_map_walker(&(ssv_sta_priv->ampdu_tid[tid_no]), ssn, sn_bit_map,
++			   ba_notification, &acked_num);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (ssv_sta_priv->ampdu_tid[tid_no].debugfs_dir) {
++		struct sk_buff *dup_skb;
++		if (skb_queue_len(&ssv_sta_priv->ampdu_tid[tid_no].ba_q) > 24) {
++			struct sk_buff *ba_skb =
++			    skb_dequeue(&ssv_sta_priv->ampdu_tid[tid_no].ba_q);
++			if (ba_skb)
++				dev_kfree_skb_any(ba_skb);
++		}
++		dup_skb = skb_clone(skb, GFP_ATOMIC);
++		if (dup_skb)
++			skb_queue_tail(&ssv_sta_priv->ampdu_tid[tid_no].ba_q,
++				       dup_skb);
++	}
++#endif
++	skb_trim(skb, skb->len - sizeof(struct ampdu_ba_notify_data));
++	host_evt = (HDR_HostEvent *) skb->data;
++	host_evt->h_event = SOC_EVT_RC_AMPDU_REPORT;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_evt->dat[0];
++	memcpy(report_data, ba_notification,
++	       sizeof(struct firmware_rate_control_report_data));
++	report_data->ampdu_len = aggr_num;
++	report_data->ampdu_ack_len = acked_num;
++#ifdef RATE_CONTROL_HT_PERCENTAGE_TRACE
++	if ((acked_num) && (acked_num != aggr_num)) {
++		int i;
++		for (i = 0; i < SSV62XX_TX_MAX_RATES; i++) {
++			if (report_data->rates[i].data_rate == -1)
++				break;
++			if (report_data->rates[i].count == 0)
++                dev_err(sc->dev, "illegal HT report\n");
++
++			dev_dbg(sc->dev, "i=[%d] rate[%d] count[%d]\n", i,
++			       report_data->rates[i].data_rate,
++			       report_data->rates[i].count);
++		}
++		dev_dbg(sc->dev, "AMPDU percentage = %d%% \n",
++		       acked_num * 100 / aggr_num);
++	} else if (acked_num == 0) {
++		dev_dbg(sc->dev, "AMPDU percentage = 0%% aggr_num=%d acked_num=%d\n",
++		       aggr_num, acked_num);
++	}
++#endif
++	skb_queue_tail(&sc->rc_report_queue, skb);
++	if (sc->rc_sample_sechedule == 0)
++		queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
++}
++
++static void _postprocess_BA(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
++			    void *param)
++{
++	int j;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	if ((sta_info->sta == NULL)
++	    || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
++		return;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	for (j = 0; j < WMM_TID_NUM; j++) {
++		AMPDU_TID *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
++		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++			continue;
++		_collect_retry_frames(ampdu_tid);
++		ssv6200_ampdu_send_retry(sc->hw, ampdu_tid,
++					 &ampdu_tid->retry_queue, true);
++		_flush_early_ampdu_q(sc, ampdu_tid);
++		_flush_release_queue(sc->hw, &ampdu_tid->release_queue);
++	}
++}
++
++void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	ssv6xxx_foreach_sta(sc, _postprocess_BA, NULL);
++}
++
++static void ssv6200_hw_set_rx_ba_session(struct ssv_hw *sh, bool on, u8 * ta,
++					 u16 tid, u16 ssn, u8 buf_size)
++{
++	if (on) {
++		u32 u32ta;
++		u32ta = 0;
++		u32ta |= (ta[0] & 0xff) << (8 * 0);
++		u32ta |= (ta[1] & 0xff) << (8 * 1);
++		u32ta |= (ta[2] & 0xff) << (8 * 2);
++		u32ta |= (ta[3] & 0xff) << (8 * 3);
++		SMAC_REG_WRITE(sh, ADR_BA_TA_0, u32ta);
++		u32ta = 0;
++		u32ta |= (ta[4] & 0xff) << (8 * 0);
++		u32ta |= (ta[5] & 0xff) << (8 * 1);
++		SMAC_REG_WRITE(sh, ADR_BA_TA_1, u32ta);
++		SMAC_REG_WRITE(sh, ADR_BA_TID, tid);
++		SMAC_REG_WRITE(sh, ADR_BA_ST_SEQ, ssn);
++		SMAC_REG_WRITE(sh, ADR_BA_SB0, 0);
++		SMAC_REG_WRITE(sh, ADR_BA_SB1, 0);
++		SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0xb);
++	} else {
++		SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0x0);
++	}
++}
++
++void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work)
++{
++	struct ssv_softc
++	*sc = container_of(work, struct ssv_softc, set_ampdu_rx_add_work);
++	ssv6200_hw_set_rx_ba_session(sc->sh, true, sc->ba_ra_addr, sc->ba_tid,
++				     sc->ba_ssn, 64);
++}
++
++void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work)
++{
++	struct ssv_softc *sc = container_of(work, struct ssv_softc,
++					    set_ampdu_rx_del_work);
++	u8 addr[6] = { 0 };
++	ssv6200_hw_set_rx_ba_session(sc->sh, false, addr, 0, 0, 0);
++}
++
++static void _reset_ampdu_mib(struct ssv_softc *sc,
++			     struct ssv_sta_info *sta_info, void *param)
++{
++	struct ieee80211_sta *sta = sta_info->sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	int i;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	for (i = 0; i < WMM_TID_NUM; i++) {
++		ssv_sta_priv->ampdu_tid[i].ampdu_mib_reset = 1;
++	}
++}
++
++void ssv6xxx_ampdu_mib_reset(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	if (sc == NULL)
++		return;
++	ssv6xxx_foreach_sta(sc, _reset_ampdu_mib, NULL);
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
++			  char *mib_str, ssize_t length)
++{
++	ssize_t buf_size = length;
++	ssize_t prt_size;
++	int j;
++	struct ssv_sta_info *ssv_sta = ssv_sta_priv->sta_info;
++	if (ssv_sta->sta == NULL) {
++		prt_size = snprintf(mib_str, buf_size, "\n    NULL STA.\n");
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		goto mib_dump_exit;
++	}
++	for (j = 0; j < WMM_TID_NUM; j++) {
++		int k;
++		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
++		struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
++		prt_size =
++		    snprintf(mib_str, buf_size, "\n    WMM_TID %d@%d\n", j,
++			     ampdu_tid->state);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++			continue;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        BA window size: %d\n",
++			     ampdu_tid->ssv_baw_size);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        BA window head: %d\n",
++			     ampdu_tid->ssv_baw_head);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Sending aggregated #: %d\n",
++				    ampdu_tid->aggr_pkt_num);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Waiting #: %d\n",
++			     skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue));
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Early aggregated %d\n",
++			     ampdu_tid->early_aggr_skb_num);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        MPDU: %d\n",
++				    ampdu_mib->ampdu_mib_mpdu_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Passed: %d\n",
++				    ampdu_mib->ampdu_mib_pass_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Retry: %d\n",
++				    ampdu_mib->ampdu_mib_retry_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        AMPDU: %d\n",
++				    ampdu_mib->ampdu_mib_ampdu_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Retry AMPDU: %d\n",
++				    ampdu_mib->ampdu_mib_aggr_retry_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        BAR count: %d\n",
++				    ampdu_mib->ampdu_mib_bar_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Discard count: %d\n",
++				    ampdu_mib->ampdu_mib_discard_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        BA count: %d\n",
++				    ampdu_mib->ampdu_mib_BA_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Total BA count: %d\n",
++			     ssv_sta_priv->ampdu_mib_total_BA_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Aggr # count:\n");
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		for (k = 0; k <= SSV_AMPDU_aggr_num_max; k++) {
++			prt_size =
++			    snprintf(mib_str, buf_size, "            %d: %d\n",
++				     k, ampdu_mib->ampdu_mib_dist[k]);
++			mib_str += prt_size;
++			buf_size -= prt_size;
++		}
++	}
++ mib_dump_exit:
++	return (length - buf_size);
++}
++
++static void _dump_ampdu_mib(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
++			    void *param)
++{
++	struct mib_dump_data *dump_data = (struct mib_dump_data *)param;
++	struct ieee80211_sta *sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	ssize_t buf_size;
++	ssize_t prt_size;
++	char *mib_str = dump_data->prt_buff;
++	if (param == NULL)
++		return;
++	buf_size = dump_data->buff_size - 1;
++	sta = sta_info->sta;
++	if ((sta == NULL) || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
++		return;
++	prt_size = snprintf(mib_str, buf_size,
++			    "STA: %02X-%02X-%02X-%02X-%02X-%02X:\n",
++			    sta->addr[0], sta->addr[1], sta->addr[2],
++			    sta->addr[3], sta->addr[4], sta->addr[5]);
++	mib_str += prt_size;
++	buf_size -= prt_size;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	prt_size = ampdu_tx_mib_dump(ssv_sta_priv, mib_str, buf_size);
++	mib_str += prt_size;
++	buf_size -= prt_size;
++	dump_data->prt_len = (dump_data->buff_size - 1 - buf_size);
++	dump_data->prt_buff = mib_str;
++	dump_data->buff_size = buf_size;
++}
++
++ssize_t ssv6xxx_ampdu_mib_dump(struct ieee80211_hw *hw, char *mib_str,
++			       ssize_t length)
++{
++	struct ssv_softc *sc = hw->priv;
++	ssize_t buf_size = length - 1;
++	struct mib_dump_data dump_data = { mib_str, buf_size, 0 };
++	if (sc == NULL)
++		return 0;
++	ssv6xxx_foreach_sta(sc, _dump_ampdu_mib, &dump_data);
++	return dump_data.prt_len;
++}
++#endif
++struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
++				 struct AMPDU_TID_st *ampdu_tid, u32 len)
++{
++	unsigned char *payload_addr;
++	u32 headroom = sc->hw->extra_tx_headroom;
++	u32 offset;
++	u32 cur_max_ampdu_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
++	u32 extra_room = sc->sh->tx_desc_len * 2 + 48;
++	u32 max_physical_len = (len
++				&& ((len + extra_room) < cur_max_ampdu_size))
++	    ? (len + extra_room)
++	    : cur_max_ampdu_size;
++	u32 skb_len = max_physical_len + headroom + 3;
++	struct sk_buff *ampdu_skb = __dev_alloc_skb(skb_len, GFP_KERNEL);
++	struct ampdu_hdr_st *ampdu_hdr;
++	if (ampdu_skb == NULL) {
++		dev_err(sc->dev, "AMPDU allocation of size %d(%d) failed\n",
++			len, skb_len);
++		return NULL;
++	}
++	payload_addr = ampdu_skb->data + headroom - sc->sh->tx_desc_len;
++	offset = ((size_t)payload_addr) % 4U;
++	if (offset) {
++		dev_dbg(sc->dev, "Align AMPDU data %d\n", offset);
++		skb_reserve(ampdu_skb, headroom + 4 - offset);
++	} else
++		skb_reserve(ampdu_skb, headroom);
++	ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++	skb_queue_head_init(&ampdu_hdr->mpdu_q);
++	ampdu_hdr->max_size = max_physical_len - extra_room;
++	ampdu_hdr->size = 0;
++	ampdu_hdr->ampdu_tid = ampdu_tid;
++	memset(ampdu_hdr->ssn, 0xFF, sizeof(ampdu_hdr->ssn));
++	ampdu_hdr->mpdu_num = 0;
++	return ampdu_skb;
++}
++
++bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	u32 ac = skb_get_queue_mapping(skb);
++	u32 hw_txqid = sc->tx.hw_txqid[ac];
++	return AMPDU_HCI_Q_EMPTY(sc->sh, hw_txqid);
++}
++
++static u32 _check_timeout(struct AMPDU_TID_st *ampdu_tid)
++{
++	u16 ssn, head_ssn, end_ssn;
++	unsigned long check_jiffies = jiffies;
++	u32 has_retry = 0;
++	head_ssn = ampdu_tid->ssv_baw_head;
++	ssn = head_ssn;
++	if (ssn == SSV_ILLEGAL_SN)
++		return 0;
++	end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
++	do {
++		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		struct SKB_info_st *skb_info;
++		unsigned long cur_jiffies;
++		unsigned long timeout_jiffies;
++		u32 delta_ms;
++		if (skb == NULL)
++			break;
++		skb_info = (SKB_info *) (skb->head);
++		cur_jiffies = jiffies;
++		timeout_jiffies =
++		    skb_info->aggr_timestamp +
++		    msecs_to_jiffies(BA_WAIT_TIMEOUT);
++		if ((skb_info->ampdu_tx_status != AMPDU_ST_SENT)
++		    || time_before(cur_jiffies, timeout_jiffies))
++			break;
++		delta_ms =
++		    jiffies_to_msecs(cur_jiffies - skb_info->aggr_timestamp);
++		prn_aggr_err("rt S%d-T%d-%d (%u)\n",
++			     ((struct ssv_sta_priv_data *)skb_info->sta->
++			      drv_priv)->sta_idx, ampdu_tid->tidno, ssn,
++			     delta_ms);
++		if (delta_ms > 1000) {
++			prn_aggr_err("Last checktime %lu - %lu = %u\n",
++				     check_jiffies, ampdu_tid->timestamp,
++				     jiffies_to_msecs(check_jiffies -
++						      ampdu_tid->timestamp));
++		}
++		has_retry += _mark_skb_retry(skb_info, skb);
++		INC_PKT_SN(ssn);
++	} while (ssn != end_ssn);
++	ampdu_tid->timestamp = check_jiffies;
++	return has_retry;
++}
++
++void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct AMPDU_TID_st *cur_AMPDU_TID;
++	if (!list_empty(&sc->tx.ampdu_tx_que)) {
++		list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
++					list) {
++			u32 has_retry;
++			if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION)
++				continue;
++			has_retry = _check_timeout(cur_AMPDU_TID);
++			if (has_retry) {
++				_collect_retry_frames(cur_AMPDU_TID);
++				ssv6200_ampdu_send_retry(sc->hw, cur_AMPDU_TID,
++							 &cur_AMPDU_TID->
++							 retry_queue, true);
++			}
++		}
++	}
++}
++
++void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++	struct sk_buff *mpdu;
++	unsigned long cur_jiffies = jiffies;
++	int i;
++	SKB_info *mpdu_skb_info;
++	u16 ssn;
++	if (ampdu_hdr->ampdu_tid->state != AMPDU_STATE_OPERATION)
++		return;
++	spin_lock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
++	for (i = 0; i < ampdu_hdr->mpdu_num; i++) {
++		ssn = ampdu_hdr->ssn[i];
++		mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
++		if (mpdu == NULL) {
++			dev_err(sc->dev, "T%d-%d is a NULL MPDU.\n",
++				ampdu_hdr->ampdu_tid->tidno, ssn);
++			continue;
++		}
++		if (ampdu_skb_ssn(mpdu) != ssn) {
++			dev_err(sc->dev, "T%d-%d does not match %d MPDU.\n",
++				ampdu_hdr->ampdu_tid->tidno, ssn,
++				ampdu_skb_ssn(mpdu));
++			continue;
++		}
++		mpdu_skb_info = (SKB_info *) (mpdu->head);
++		mpdu_skb_info->aggr_timestamp = cur_jiffies;
++		mpdu_skb_info->ampdu_tx_status = AMPDU_ST_SENT;
++	}
++	spin_unlock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.h b/drivers/net/wireless/ssv6051/smac/ampdu.h
+new file mode 100644
+index 000000000000..faa61c4f9297
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ampdu.h
+@@ -0,0 +1,215 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _AMPDU_H_
++#define _AMPDU_H_
++#include <linux/version.h>
++#include <ssv6200_common.h>
++#define Enable_ampdu_debug_log (0)
++#define Enable_AMPDU_Live_Time (0)
++#define Enable_HW_AUTO_CRC_32 (1)
++#define Enable_AMPDU_Rx (1)
++#define Enable_AMPDU_Tx (1)
++#define Enable_AMPDU_FW_Retry (1)
++#define Enable_AMPDU_delay_work (1)
++#define USE_FLUSH_RETRY
++#define USE_AMPDU_TX_STATUS_ARRAY
++#define SSV_AMPDU_FLOW_CONTROL
++#define AMPDU_CHECK_SKB_SEQNO
++#define REPORT_TX_STATUS_DIRECTLY
++#define SSV_AMPDU_aggr_num_max MAX_AGGR_NUM
++#define SSV_AMPDU_seq_num_max (4096)
++#define SSV_AMPDU_retry_counter_max (3)
++#define SSV_AMPDU_tx_group_id_max (64)
++#define SSV_AMPDU_MAX_SSN (4096)
++#define SSV_AMPDU_BA_WINDOW_SIZE (64)
++#define SSV_AMPDU_WINDOW_SIZE (64)
++#define SSV_GET_MAX_AMPDU_SIZE(sh) (((sh)->tx_page_available/(sh)->ampdu_divider) << HW_MMU_PAGE_SHIFT)
++#define SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND (64)
++#define SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND (48)
++#define SSV_AMPDU_timer_period (50)
++#define SSV_AMPDU_TX_TIME_THRESHOLD (50)
++#define SSV_AMPDU_MPDU_LIVE_TIME (SSV_AMPDU_retry_counter_max*8)
++#define SSV_AMPDU_BA_TIME (50)
++#define SSV_ILLEGAL_SN (0xffff)
++#define AMPDU_BUFFER_SIZE (32*1024)
++#define AMPDU_SIGNATURE (0x4E)
++#define AMPDU_DELIMITER_LEN (4)
++#define AMPDU_FCS_LEN (4)
++#define AMPDU_RESERVED_LEN (3)
++#define AMPDU_TX_NAV_MCS_567 (48)
++#define SSV_SEQ_NUM_SHIFT (4)
++#define SSV_RETRY_BIT_SHIFT (11)
++#define IEEE80211_SEQ_SEQ_SHIFT (4)
++#define IEEE80211_AMPDU_BA_LEN (34)
++#define SSV6200_AMPDU_TRIGGER_INDEX 0
++#define SSV_SN_STATUS_Release (0xaa)
++#define SSV_SN_STATUS_Retry (0xbb)
++#define SSV_SN_STATUS_Wait_BA (0xcc)
++#define SSV_SN_STATUS_Discard (0xdd)
++#define AMPDU_HCI_SEND_TAIL_WITH_FLOWCTRL (0)
++#define AMPDU_HCI_SEND_HEAD_WITH_FLOWCTRL (1)
++#define AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL (2)
++#define AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL (3)
++#define SSV_BAR_CTRL_ACK_POLICY_NORMAL (0x0000)
++#define SSV_BAR_CTRL_CBMTID_COMPRESSED_BA (0x0004)
++#define SSV_BAR_CTRL_TID_INFO_SHIFT (12)
++#define AMPDU_STATE_START BIT(0)
++#define AMPDU_STATE_OPERATION BIT(1)
++#define AMPDU_STATE_STOP BIT(2)
++typedef enum {
++	AMPDU_REKEY_PAUSE_STOP = 0,
++	AMPDU_REKEY_PAUSE_START,
++	AMPDU_REKEY_PAUSE_ONGOING,
++	AMPDU_REKEY_PAUSE_DEFER,
++	AMPDU_REKEY_PAUSE_HWKEY_SYNC,
++} AMPDU_REKEY_PAUSE_STATE;
++#define SSV_a_minus_b_in_c(a,b,c) (((a)>=(b))?((a)-(b)):((c)-(b)+(a)))
++#define SSV_AMPDU_SN_a_minus_b(a,b) (SSV_a_minus_b_in_c((a), (b), SSV_AMPDU_seq_num_max))
++#define AMPDU_HCI_SEND(_sh,_sk,_q,_flag) (_sh)->hci.hci_ops->hci_tx((_sk), (_q), (_flag))
++#define AMPDU_HCI_Q_EMPTY(_sh,_q) (_sh)->hci.hci_ops->hci_txq_empty((_q))
++struct ampdu_hdr_st {
++	u32 first_sn;
++	struct sk_buff_head mpdu_q;
++	u32 max_size;
++	u32 size;
++	struct AMPDU_TID_st *ampdu_tid;
++	u16 ssn[MAX_AGGR_NUM];
++	u16 mpdu_num;
++	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
++	struct ieee80211_sta *sta;
++};
++enum AMPDU_TX_STATUS_E {
++	AMPDU_ST_NON_AMPDU,
++	AMPDU_ST_AGGREGATED,
++	AMPDU_ST_SENT,
++	AMPDU_ST_RETRY,
++	AMPDU_ST_DROPPED,
++	AMPDU_ST_DONE,
++};
++typedef struct AMPDU_MIB_st {
++	u32 ampdu_mib_mpdu_counter;
++	u32 ampdu_mib_retry_counter;
++	u32 ampdu_mib_ampdu_counter;
++	u32 ampdu_mib_aggr_retry_counter;
++	u32 ampdu_mib_bar_counter;
++	u32 ampdu_mib_discard_counter;
++	u32 ampdu_mib_total_BA_counter;
++	u32 ampdu_mib_BA_counter;
++	u32 ampdu_mib_pass_counter;
++	u32 ampdu_mib_dist[SSV_AMPDU_aggr_num_max + 1];
++} AMPDU_MIB;
++typedef struct AMPDU_TID_st {
++	struct list_head list;
++	volatile unsigned long timestamp;
++	u32 tidno;
++	u16 ac;
++	struct ieee80211_sta *sta;
++	u16 ssv_baw_size;
++	u8 agg_num_max;
++	u8 state;
++#ifdef AMPDU_CHECK_SKB_SEQNO
++	u32 last_seqno;
++#endif
++	struct sk_buff_head ampdu_skb_tx_queue;
++	spinlock_t ampdu_skb_tx_queue_lock;
++	struct sk_buff_head retry_queue;
++	struct sk_buff_head release_queue;
++	struct sk_buff *aggr_pkts[SSV_AMPDU_BA_WINDOW_SIZE];
++	volatile u32 aggr_pkt_num;
++	volatile u16 ssv_baw_head;
++	spinlock_t pkt_array_lock;
++	struct sk_buff *cur_ampdu_pkt;
++	struct sk_buff_head early_aggr_ampdu_q;
++	u32 early_aggr_skb_num;
++	struct sk_buff_head ampdu_skb_wait_encry_queue;
++	u32 ampdu_mib_reset;
++	struct AMPDU_MIB_st mib;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++	struct sk_buff_head ba_q;
++#endif
++} AMPDU_TID, *p_AMPDU_TID;
++typedef struct AMPDU_DELIMITER_st {
++	u16 reserved:4;
++	u16 length:12;
++	u8 crc;
++	u8 signature;
++} AMPDU_DELIMITER, *p_AMPDU_DELIMITER;
++typedef struct AMPDU_BLOCKACK_st {
++	u16 frame_control;
++	u16 duration;
++	u8 ra_addr[ETH_ALEN];
++	u8 ta_addr[ETH_ALEN];
++	u16 BA_ack_ploicy:1;
++	u16 multi_tid:1;
++	u16 compress_bitmap:1;
++	u16 reserved:9;
++	u16 tid_info:4;
++	u16 BA_fragment_sn:4;
++	u16 BA_ssn:12;
++	u32 BA_sn_bit_map[2];
++} AMPDU_BLOCKACK, *p_AMPDU_BLOCKACK;
++struct ssv_bar {
++	unsigned short frame_control;
++	unsigned short duration;
++	unsigned char ra[6];
++	unsigned char ta[6];
++	unsigned short control;
++	unsigned short start_seq_num;
++} __packed;
++#if Enable_ampdu_debug_log
++#define ampdu_db_log(format, args...) printk("~~~ampdu [%s:%d] "format, __FUNCTION__, __LINE__, ##args)
++#define ampdu_db_log_simple(format, args...) printk(format, ##args)
++#else
++#define ampdu_db_log(...) do {} while (0)
++#define ampdu_db_log_simple(...) do {} while (0)
++#endif
++#if Enable_AMPDU_delay_work
++void ssv6200_ampdu_delayed_work_callback_func(struct work_struct *work);
++#else
++void ssv6200_ampdu_timer_callback_func(unsigned long data);
++#endif
++void ssv6200_ampdu_init(struct ieee80211_hw *hw);
++void ssv6200_ampdu_deinit(struct ieee80211_hw *hw);
++void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw);
++void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
++			    struct ieee80211_hw *hw, u16 * ssn);
++void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
++				struct ieee80211_hw *hw, u8 buffer_size);
++void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
++			   struct ieee80211_hw *hw);
++bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
++u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw);
++void ssv6200_ampdu_timeout_tx(struct ieee80211_hw *hw);
++struct cfg_host_event;
++void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
++void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
++void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
++				   struct sk_buff *skb);
++void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
++			      struct ieee80211_sta *sta);
++void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw);
++void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw);
++void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu);
++extern void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work);
++extern void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work);
++void ssv6xxx_mib_reset(struct ieee80211_hw *hw);
++ssize_t ssv6xxx_mib_dump(struct ieee80211_hw *hw, char *mib_str,
++			 ssize_t length);
++void encry_work(struct work_struct *work);
++void sync_hw_key_work(struct work_struct *work);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ap.c b/drivers/net/wireless/ssv6051/smac/ap.c
+new file mode 100644
+index 000000000000..0f2ba6a31a05
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ap.c
+@@ -0,0 +1,598 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <linux/sched.h>
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "lib.h"
++#include "dev.h"
++#include "ap.h"
++#include "ssv_rc_common.h"
++#include "ssv_rc.h"
++int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
++#define IS_EQUAL(a,b) ( (a) == (b) )
++#define SET_BIT(v,b) ( (v) |= (0x01<<b) )
++#define CLEAR_BIT(v,b) ( (v) &= ~(0x01<<b) )
++#define IS_BIT_SET(v,b) ( (v) & (0x01<<(b) ) )
++#define PBUF_BASE_ADDR 0x80000000
++#define PBUF_ADDR_SHIFT 16
++#define PBUF_MapPkttoID(_PKT) (((u32)_PKT&0x0FFF0000)>>PBUF_ADDR_SHIFT)
++#define PBUF_MapIDtoPkt(_ID) (PBUF_BASE_ADDR|((_ID)<<PBUF_ADDR_SHIFT))
++#define SSV6xxx_BEACON_MAX_ALLOCATE_CNT 10
++#define MTX_BCN_PKTID_CH_LOCK_SHIFT MTX_BCN_PKTID_CH_LOCK_SFT
++#define MTX_BCN_CFG_VLD_SHIFT MTX_BCN_CFG_VLD_SFT
++#define MTX_BCN_CFG_VLD_MASK MTX_BCN_CFG_VLD_MSK
++#define AUTO_BCN_ONGOING_MASK MTX_AUTO_BCN_ONGOING_MSK
++#define AUTO_BCN_ONGOING_SHIFT MTX_AUTO_BCN_ONGOING_SFT
++#define MTX_BCN_TIMER_EN_SHIFT MTX_BCN_TIMER_EN_SFT
++#define MTX_TSF_TIMER_EN_SHIFT MTX_TSF_TIMER_EN_SFT
++#define MTX_HALT_MNG_UNTIL_DTIM_SHIFT MTX_HALT_MNG_UNTIL_DTIM_SFT
++#define MTX_BCN_ENABLE_MASK (MTX_BCN_TIMER_EN_I_MSK)
++#define MTX_BCN_PERIOD_SHIFT MTX_BCN_PERIOD_SFT
++#define MTX_DTIM_NUM_SHIFT MTX_DTIM_NUM_SFT
++#define MTX_DTIM_OFST0 MTX_DTIM_OFST0_SFT
++enum ssv6xxx_beacon_type {
++	SSV6xxx_BEACON_0,
++	SSV6xxx_BEACON_1,
++};
++static const u32 ssv6xxx_beacon_adr[] = {
++	ADR_MTX_BCN_CFG0,
++	ADR_MTX_BCN_CFG1,
++};
++
++void ssv6xxx_beacon_reg_lock(struct ssv_softc *sc, bool block)
++{
++	u32 val;
++	val = block << MTX_BCN_PKTID_CH_LOCK_SHIFT;
++#ifdef BEACON_DEBUG
++	printk("ssv6xxx_beacon_reg_lock   val[0x:%08x]\n ", val);
++#endif
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_MISC, val);
++}
++
++void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
++			     u8 dtim_cnt)
++{
++	u32 val;
++	if (beacon_interval == 0)
++		beacon_interval = 100;
++#ifdef BEACON_DEBUG
++	printk("[A] BSS_CHANGED_BEACON_INT beacon_int[%d] dtim_cnt[%d]\n",
++	       beacon_interval, (dtim_cnt));
++#endif
++	val =
++	    (beacon_interval << MTX_BCN_PERIOD_SHIFT) | (dtim_cnt <<
++							 MTX_DTIM_NUM_SHIFT);
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_PRD, val);
++}
++
++bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable)
++{
++	u32 regval = 0;
++	int ret = 0;
++	if (bEnable && !sc->beacon_usage) {
++		printk
++		    ("[A] Reject to set beacon!!!.        ssv6xxx_beacon_enable bEnable[%d] sc->beacon_usage[%d]\n",
++		     bEnable, sc->beacon_usage);
++		sc->enable_beacon = BEACON_WAITING_ENABLED;
++		return 0;
++	}
++	if ((bEnable && (BEACON_ENABLED & sc->enable_beacon)) ||
++	    (!bEnable && !sc->enable_beacon)) {
++		printk
++		    ("[A] ssv6xxx_beacon_enable bEnable[%d] and sc->enable_beacon[%d] are the same. no need to execute.\n",
++		     bEnable, sc->enable_beacon);
++		if (bEnable) {
++			printk("        Ignore enable beacon cmd!!!!\n");
++			return 0;
++		}
++	}
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
++#endif
++	regval &= MTX_BCN_ENABLE_MASK;
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
++#endif
++	regval |= (bEnable << MTX_BCN_TIMER_EN_SHIFT);
++	ret = SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
++#endif
++	sc->enable_beacon = (bEnable == true) ? BEACON_ENABLED : 0;
++	return ret;
++}
++
++int ssv6xxx_beacon_fill_content(struct ssv_softc *sc, u32 regaddr, u8 * beacon,
++				int size)
++{
++	u32 i, val;
++	u32 *ptr = (u32 *) beacon;
++	size = size / 4;
++	for (i = 0; i < size; i++) {
++		val = (u32) (*(ptr + i));
++#ifdef BEACON_DEBUG
++		printk("[%08x] ", val);
++#endif
++		SMAC_REG_WRITE(sc->sh, regaddr + i * 4, val);
++	}
++#ifdef BEACON_DEBUG
++	printk("\n");
++#endif
++	return 0;
++}
++
++void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc,
++				 struct sk_buff *beacon_skb)
++{
++	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(beacon_skb);
++	struct ssv6200_tx_desc *tx_desc;
++	u16 pb_offset = TXPB_OFFSET;
++	struct ssv_rate_info ssv_rate;
++	skb_push(beacon_skb, pb_offset);
++	tx_desc = (struct ssv6200_tx_desc *)beacon_skb->data;
++	memset(tx_desc, 0, pb_offset);
++	ssv6xxx_rc_hw_rate_idx(sc, tx_info, &ssv_rate);
++	tx_desc->len = beacon_skb->len - pb_offset;
++	tx_desc->c_type = M2_TXREQ;
++	tx_desc->f80211 = 1;
++	tx_desc->ack_policy = 1;
++	tx_desc->hdr_offset = pb_offset;
++	tx_desc->hdr_len = 24;
++	tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
++	tx_desc->crate_idx = ssv_rate.crate_hw_idx;
++	tx_desc->drate_idx = ssv_rate.drate_hw_idx;
++	skb_put(beacon_skb, 4);
++}
++
++inline enum ssv6xxx_beacon_type ssv6xxx_beacon_get_valid_reg(struct ssv_softc
++							     *sc)
++{
++	u32 regval = 0;
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
++	regval &= MTX_BCN_CFG_VLD_MASK;
++	regval = regval >> MTX_BCN_CFG_VLD_SHIFT;
++	if (regval == 0x2 || regval == 0x0)
++		return SSV6xxx_BEACON_0;
++	else if (regval == 0x1)
++		return SSV6xxx_BEACON_1;
++	else
++		printk("=============>ERROR!!drv_bcn_reg_available\n");
++	return SSV6xxx_BEACON_0;
++}
++
++bool ssv6xxx_beacon_set(struct ssv_softc *sc, struct sk_buff *beacon_skb,
++			int dtim_offset)
++{
++	u32 reg_tx_beacon_adr = ADR_MTX_BCN_CFG0;
++	enum ssv6xxx_beacon_type avl_bcn_type = SSV6xxx_BEACON_0;
++	bool ret = true;
++	int val;
++	ssv6xxx_beacon_reg_lock(sc, 1);
++	avl_bcn_type = ssv6xxx_beacon_get_valid_reg(sc);
++	if (avl_bcn_type == SSV6xxx_BEACON_1)
++		reg_tx_beacon_adr = ADR_MTX_BCN_CFG1;
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_set avl_bcn_type[%d]\n", avl_bcn_type);
++#endif
++	do {
++		if (IS_BIT_SET(sc->beacon_usage, avl_bcn_type)) {
++#ifdef BEACON_DEBUG
++			printk
++			    ("[A] beacon has already been set old len[%d] new len[%d]\n",
++			     sc->beacon_info[avl_bcn_type].len,
++			     beacon_skb->len);
++#endif
++			if (sc->beacon_info[avl_bcn_type].len >=
++			    beacon_skb->len) {
++				break;
++			} else {
++				if (false ==
++				    ssv6xxx_pbuf_free(sc,
++						      sc->
++						      beacon_info[avl_bcn_type].
++						      pubf_addr)) {
++#ifdef BEACON_DEBUG
++					printk
++					    ("=============>ERROR!!Intend to allcoate beacon from ASIC fail.\n");
++#endif
++					ret = false;
++					goto out;
++				}
++				CLEAR_BIT(sc->beacon_usage, avl_bcn_type);
++			}
++		}
++		sc->beacon_info[avl_bcn_type].pubf_addr =
++		    ssv6xxx_pbuf_alloc(sc, beacon_skb->len, TX_BUF);
++		sc->beacon_info[avl_bcn_type].len = beacon_skb->len;
++		if (sc->beacon_info[avl_bcn_type].pubf_addr == 0) {
++			ret = false;
++			goto out;
++		}
++		SET_BIT(sc->beacon_usage, avl_bcn_type);
++#ifdef BEACON_DEBUG
++		printk
++		    ("[A] beacon type[%d] usage[%d] allocate new beacon addr[%08x] \n",
++		     avl_bcn_type, sc->beacon_usage,
++		     sc->beacon_info[avl_bcn_type].pubf_addr);
++#endif
++	} while (0);
++	ssv6xxx_beacon_fill_content(sc, sc->beacon_info[avl_bcn_type].pubf_addr,
++				    beacon_skb->data, beacon_skb->len);
++	val =
++	    (PBUF_MapPkttoID(sc->beacon_info[avl_bcn_type].pubf_addr)) |
++	    (dtim_offset << MTX_DTIM_OFST0);
++	SMAC_REG_WRITE(sc->sh, reg_tx_beacon_adr, val);
++#ifdef BEACON_DEBUG
++	printk("[A] update to register reg_tx_beacon_adr[%08x] val[%08x]\n",
++	       reg_tx_beacon_adr, val);
++#endif
++ out:
++	ssv6xxx_beacon_reg_lock(sc, 0);
++	if (sc->beacon_usage && (sc->enable_beacon & BEACON_WAITING_ENABLED)) {
++		printk("[A] enable beacon for BEACON_WAITING_ENABLED flags\n");
++		ssv6xxx_beacon_enable(sc, true);
++	}
++	return ret;
++}
++
++inline bool ssv6xxx_auto_bcn_ongoing(struct ssv_softc *sc)
++{
++	u32 regval;
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
++	return ((AUTO_BCN_ONGOING_MASK & regval) >> AUTO_BCN_ONGOING_SHIFT);
++}
++
++void ssv6xxx_beacon_release(struct ssv_softc *sc)
++{
++	int cnt = 10;
++	printk("[A] ssv6xxx_beacon_release Enter\n");
++	cancel_work_sync(&sc->set_tim_work);
++	do {
++		if (ssv6xxx_auto_bcn_ongoing(sc))
++			ssv6xxx_beacon_enable(sc, false);
++		else
++			break;
++		cnt--;
++		if (cnt <= 0)
++			break;
++	} while (1);
++	if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_0)) {
++		ssv6xxx_pbuf_free(sc,
++				  sc->beacon_info[SSV6xxx_BEACON_0].pubf_addr);
++		CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_0);
++	}
++	if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_1)) {
++		ssv6xxx_pbuf_free(sc,
++				  sc->beacon_info[SSV6xxx_BEACON_1].pubf_addr);
++		CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_1);
++	}
++	sc->enable_beacon = 0;
++	if (sc->beacon_buf) {
++		dev_kfree_skb_any(sc->beacon_buf);
++		sc->beacon_buf = NULL;
++	}
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_release leave\n");
++#endif
++}
++
++void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, bool aid0_bit_set)
++{
++	struct sk_buff *skb;
++	struct sk_buff *old_skb = NULL;
++	u16 tim_offset, tim_length;
++	if (sc == NULL || hw == NULL || vif == NULL) {
++		printk("[Error]........ssv6xxx_beacon_change input error\n");
++		return;
++	}
++	do {
++		skb = ieee80211_beacon_get_tim(hw, vif,
++					       &tim_offset, &tim_length, 0);
++		if (skb == NULL) {
++			printk("[Error]........skb is NULL\n");
++			break;
++		}
++		if (tim_offset && tim_length >= 6) {
++			skb->data[tim_offset + 2] = 0;
++			if (aid0_bit_set)
++				skb->data[tim_offset + 4] |= 1;
++			else
++				skb->data[tim_offset + 4] &= ~1;
++		}
++#ifdef BEACON_DEBUG
++		printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
++		       tim_offset);
++#endif
++		ssv6xxx_beacon_fill_tx_desc(sc, skb);
++#ifdef BEACON_DEBUG
++		printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
++		       tim_offset);
++#endif
++		if (sc->beacon_buf) {
++			if (memcmp
++			    (sc->beacon_buf->data, skb->data,
++			     (skb->len - FCS_LEN)) == 0) {
++				old_skb = skb;
++				break;
++			} else {
++				old_skb = sc->beacon_buf;
++				sc->beacon_buf = skb;
++			}
++		} else {
++			sc->beacon_buf = skb;
++		}
++		tim_offset += 2;
++		if (ssv6xxx_beacon_set(sc, skb, tim_offset)) {
++			u8 dtim_cnt = vif->bss_conf.dtim_period - 1;
++			if (sc->beacon_dtim_cnt != dtim_cnt) {
++				sc->beacon_dtim_cnt = dtim_cnt;
++#ifdef BEACON_DEBUG
++				printk("[A] beacon_dtim_cnt [%d]\n",
++				       sc->beacon_dtim_cnt);
++#endif
++				ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
++							sc->beacon_dtim_cnt);
++			}
++		}
++	} while (0);
++	if (old_skb)
++		dev_kfree_skb_any(old_skb);
++}
++
++void ssv6200_set_tim_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, set_tim_work);
++#ifdef BROADCAST_DEBUG
++	printk("%s() enter\n", __FUNCTION__);
++#endif
++	ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
++#ifdef BROADCAST_DEBUG
++	printk("%s() leave\n", __FUNCTION__);
++#endif
++}
++
++int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq)
++{
++	u32 len;
++	unsigned long flags;
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	len = bcast_txq->cur_qsize;
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++	return len;
++}
++
++struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
++				      u8 * remain_len)
++{
++	struct sk_buff *skb = NULL;
++	unsigned long flags;
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	if (bcast_txq->cur_qsize) {
++		bcast_txq->cur_qsize--;
++		if (remain_len)
++			*remain_len = bcast_txq->cur_qsize;
++		skb = __skb_dequeue(&bcast_txq->qhead);
++	}
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++	return skb;
++}
++
++int ssv6200_bcast_enqueue(struct ssv_softc *sc,
++			  struct ssv6xxx_bcast_txq *bcast_txq,
++			  struct sk_buff *skb)
++{
++	unsigned long flags;
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	if (bcast_txq->cur_qsize >= SSV6200_MAX_BCAST_QUEUE_LEN) {
++		struct sk_buff *old_skb;
++		old_skb = __skb_dequeue(&bcast_txq->qhead);
++		bcast_txq->cur_qsize--;
++		ssv6xxx_txbuf_free_skb(old_skb, (void *)sc);
++		printk("[B] ssv6200_bcast_enqueue - remove oldest queue\n");
++	}
++	__skb_queue_tail(&bcast_txq->qhead, skb);
++	bcast_txq->cur_qsize++;
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++	return bcast_txq->cur_qsize;
++}
++
++void ssv6200_bcast_flush(struct ssv_softc *sc,
++			 struct ssv6xxx_bcast_txq *bcast_txq)
++{
++	struct sk_buff *skb;
++	unsigned long flags;
++#ifdef BCAST_DEBUG
++	printk("ssv6200_bcast_flush\n");
++#endif
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	while (bcast_txq->cur_qsize > 0) {
++		skb = __skb_dequeue(&bcast_txq->qhead);
++		bcast_txq->cur_qsize--;
++		ssv6xxx_txbuf_free_skb(skb, (void *)sc);
++	}
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++}
++
++static int queue_block_cnt = 0;
++void ssv6200_bcast_tx_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, bcast_tx_work.work);
++	struct sk_buff *skb;
++	int i;
++	u8 remain_size;
++	unsigned long flags;
++	bool needtimer = true;
++	long tmo = sc->bcast_interval;
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	do {
++#ifdef BCAST_DEBUG
++		printk
++		    ("[B] bcast_timer: hw_mng_used[%d] HCI_TXQ_EMPTY[%d] bcast_queue_len[%d].....................\n",
++		     sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4),
++		     ssv6200_bcast_queue_len(&sc->bcast_txq));
++#endif
++		if (sc->hw_mng_used != 0 || false == HCI_TXQ_EMPTY(sc->sh, 4)) {
++#ifdef BCAST_DEBUG
++			printk
++			    ("HW queue still have frames insdide. skip this one hw_mng_used[%d] bEmptyTXQ4[%d]\n",
++			     sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4));
++#endif
++			queue_block_cnt++;
++			if (queue_block_cnt > 5) {
++				queue_block_cnt = 0;
++				ssv6200_bcast_flush(sc, &sc->bcast_txq);
++				needtimer = false;
++			}
++			break;
++		}
++		queue_block_cnt = 0;
++		for (i = 0; i < SSV6200_ID_MANAGER_QUEUE; i++) {
++			skb =
++			    ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
++			if (!skb) {
++				needtimer = false;
++				break;
++			}
++			if ((0 != remain_size) &&
++			    (SSV6200_ID_MANAGER_QUEUE - 1) != i) {
++				struct ieee80211_hdr *hdr;
++				struct ssv6200_tx_desc *tx_desc =
++				    (struct ssv6200_tx_desc *)skb->data;
++				hdr =
++				    (struct ieee80211_hdr *)((u8 *) tx_desc +
++							     tx_desc->
++							     hdr_offset);
++				hdr->frame_control |=
++				    cpu_to_le16(IEEE80211_FCTL_MOREDATA);
++			}
++#ifdef BCAST_DEBUG
++			printk("[B] bcast_timer:tx remain_size[%d] i[%d]\n",
++			       remain_size, i);
++#endif
++			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++			if (HCI_SEND(sc->sh, skb, 4) < 0) {
++				printk("bcast_timer send fail!!!!!!! \n");
++				ssv6xxx_txbuf_free_skb(skb, (void *)sc);
++				BUG_ON(1);
++			}
++			spin_lock_irqsave(&sc->ps_state_lock, flags);
++		}
++	} while (0);
++	if (needtimer) {
++#ifdef BCAST_DEBUG
++		printk
++		    ("[B] bcast_timer:need more timer to tx bcast frame time[%d]\n",
++		     sc->bcast_interval);
++#endif
++		queue_delayed_work(sc->config_wq, &sc->bcast_tx_work, tmo);
++	} else {
++#ifdef BCAST_DEBUG
++		printk("[B] bcast_timer: ssv6200_bcast_stop\n");
++#endif
++		ssv6200_bcast_stop(sc);
++	}
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++#ifdef BCAST_DEBUG
++	printk("[B] bcast_timer: leave.....................\n");
++#endif
++}
++
++void ssv6200_bcast_start_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, bcast_start_work);
++#ifdef BCAST_DEBUG
++	printk("[B] ssv6200_bcast_start_work==\n");
++#endif
++	sc->bcast_interval = (sc->beacon_dtim_cnt + 1) *
++	    (sc->beacon_interval + 20) * HZ / 1000;
++	if (!sc->aid0_bit_set) {
++		sc->aid0_bit_set = true;
++		ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
++		queue_delayed_work(sc->config_wq,
++				   &sc->bcast_tx_work, sc->bcast_interval);
++#ifdef BCAST_DEBUG
++		printk("[B] bcast_start_work: Modify timer to DTIM[%d]ms==\n",
++		       (sc->beacon_dtim_cnt + 1) * (sc->beacon_interval + 20));
++#endif
++	}
++}
++
++void ssv6200_bcast_stop_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, bcast_stop_work.work);
++	long tmo = HZ / 100;
++#ifdef BCAST_DEBUG
++	printk("[B] ssv6200_bcast_stop_work\n");
++#endif
++	if (sc->aid0_bit_set) {
++		if (0 == ssv6200_bcast_queue_len(&sc->bcast_txq)) {
++			cancel_delayed_work_sync(&sc->bcast_tx_work);
++			sc->aid0_bit_set = false;
++			ssv6xxx_beacon_change(sc, sc->hw,
++					      sc->ap_vif, sc->aid0_bit_set);
++#ifdef BCAST_DEBUG
++			printk("remove group bit in DTIM\n");
++#endif
++		} else {
++#ifdef BCAST_DEBUG
++			printk
++			    ("bcast_stop_work: bcast queue still have data. just modify timer to 10ms\n");
++#endif
++			queue_delayed_work(sc->config_wq,
++					   &sc->bcast_tx_work, tmo);
++		}
++	}
++}
++
++void ssv6200_bcast_stop(struct ssv_softc *sc)
++{
++	queue_delayed_work(sc->config_wq,
++			   &sc->bcast_stop_work,
++			   sc->beacon_interval * HZ / 1024);
++}
++
++void ssv6200_bcast_start(struct ssv_softc *sc)
++{
++	queue_work(sc->config_wq, &sc->bcast_start_work);
++}
++
++void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif)
++{
++	unsigned long flags;
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	priv_vif->sta_asleep_mask = 0;
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++	cancel_work_sync(&sc->bcast_start_work);
++	cancel_delayed_work_sync(&sc->bcast_stop_work);
++	ssv6200_bcast_flush(sc, &sc->bcast_txq);
++	cancel_delayed_work_sync(&sc->bcast_tx_work);
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ap.h b/drivers/net/wireless/ssv6051/smac/ap.h
+new file mode 100644
+index 000000000000..93b5275715b5
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ap.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _AP_H_
++#define _AP_H_
++#define BEACON_WAITING_ENABLED 1<<0
++#define BEACON_ENABLED 1<<1
++void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, bool aid0_bit_set);
++void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
++			     u8 dtim_cnt);
++bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable);
++void ssv6xxx_beacon_release(struct ssv_softc *sc);
++void ssv6200_set_tim_work(struct work_struct *work);
++void ssv6200_bcast_start_work(struct work_struct *work);
++void ssv6200_bcast_stop_work(struct work_struct *work);
++void ssv6200_bcast_tx_work(struct work_struct *work);
++int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
++struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
++				      u8 * remain_len);
++int ssv6200_bcast_enqueue(struct ssv_softc *sc,
++			  struct ssv6xxx_bcast_txq *bcast_txq,
++			  struct sk_buff *skb);
++void ssv6200_bcast_start(struct ssv_softc *sc);
++void ssv6200_bcast_stop(struct ssv_softc *sc);
++void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/dev.c b/drivers/net/wireless/ssv6051/smac/dev.c
+new file mode 100644
+index 000000000000..214e93fae460
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/dev.c
+@@ -0,0 +1,3881 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <linux/kthread.h>
++#include <linux/ktime.h>
++
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include <hci/hctrl.h>
++#include "linux_80211.h"
++#include "lib.h"
++#include "ssv_rc.h"
++#include "ssv_ht_rc.h"
++#include "dev.h"
++#include "ap.h"
++#include "init.h"
++#include "p2p.h"
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++#include "ssv6xxx_debugfs.h"
++#endif
++struct rssi_res_st rssi_res, *p_rssi_res;
++#define NO_USE_RXQ_LOCK
++#ifndef WLAN_CIPHER_SUITE_SMS4
++#define WLAN_CIPHER_SUITE_SMS4 0x00147201
++#endif
++#define MAX_TX_Q_LEN (64)
++#define LOW_TX_Q_LEN (MAX_TX_Q_LEN/2)
++static u16 bits_per_symbol[][2] = {
++	{26, 54},
++	{52, 108},
++	{78, 162},
++	{104, 216},
++	{156, 324},
++	{208, 432},
++	{234, 486},
++	{260, 540},
++};
++
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
++extern unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage);
++#endif
++struct ssv6xxx_calib_table {
++	u16 channel_id;
++	u32 rf_ctrl_N;
++	u32 rf_ctrl_F;
++	u16 rf_precision_default;
++};
++static void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
++			  spinlock_t * rx_q_lock);
++static u32 _process_tx_done(struct ssv_softc *sc);
++
++void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)args;
++	if (!skb)
++		return;
++	ieee80211_free_txskb(sc->hw, skb);
++}
++
++#define ADDRESS_OFFSET 16
++#define HW_ID_OFFSET 7
++#define CH0_FULL_MASK CH0_FULL_MSK
++#define MAX_FAIL_COUNT 100
++#define MAX_RETRY_COUNT 20
++inline bool ssv6xxx_mcu_input_full(struct ssv_softc *sc)
++{
++	u32 regval = 0;
++	SMAC_REG_READ(sc->sh, ADR_MCU_STATUS, &regval);
++	return CH0_FULL_MASK & regval;
++}
++
++u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type)
++{
++	u32 regval, pad;
++	int cnt = MAX_RETRY_COUNT;
++	int page_cnt =
++	    (size + ((1 << HW_MMU_PAGE_SHIFT) - 1)) >> HW_MMU_PAGE_SHIFT;
++	regval = 0;
++	mutex_lock(&sc->mem_mutex);
++	pad = size % 4;
++	size += pad;
++	do {
++		SMAC_REG_WRITE(sc->sh, ADR_WR_ALC, (size | (type << 16)));
++		SMAC_REG_READ(sc->sh, ADR_WR_ALC, &regval);
++		if (regval == 0) {
++			cnt--;
++			msleep(1);
++		} else
++			break;
++	} while (cnt);
++	if (type == TX_BUF) {
++		sc->sh->tx_page_available -= page_cnt;
++		sc->sh->page_count[PACKET_ADDR_2_ID(regval)] = page_cnt;
++	}
++	mutex_unlock(&sc->mem_mutex);
++	if (regval == 0)
++		dev_err(sc->dev,
++			"Failed to allocate packet buffer of %d bytes in %d type.",
++			size, type);
++	else {
++		dev_dbg(sc->dev,
++			"Allocated %d type packet buffer of size %d (%d) at address %x.\n",
++			type, size, page_cnt, regval);
++	}
++	return regval;
++}
++
++bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr)
++{
++	u32 regval = 0;
++	u16 failCount = 0;
++	u8 *p_tx_page_cnt = &sc->sh->page_count[PACKET_ADDR_2_ID(pbuf_addr)];
++	while (ssv6xxx_mcu_input_full(sc)) {
++		if (failCount++ < 1000)
++			continue;
++		dev_err(sc->dev, "Error in mailbox block after %d iterations\n", failCount);
++		return false;
++	}
++	mutex_lock(&sc->mem_mutex);
++	regval =
++	    ((M_ENG_TRASH_CAN << HW_ID_OFFSET) | (pbuf_addr >> ADDRESS_OFFSET));
++	SMAC_REG_WRITE(sc->sh, ADR_CH0_TRIG_1, regval);
++	if (*p_tx_page_cnt) {
++		sc->sh->tx_page_available += *p_tx_page_cnt;
++		*p_tx_page_cnt = 0;
++	}
++	mutex_unlock(&sc->mem_mutex);
++	return true;
++}
++
++static const struct ssv6xxx_calib_table vt_tbl[SSV6XXX_IQK_CFG_XTAL_MAX][14] = {
++	{
++	 {1, 0xB9, 0x89D89E, 3859},
++	 {2, 0xB9, 0xEC4EC5, 3867},
++	 {3, 0xBA, 0x4EC4EC, 3875},
++	 {4, 0xBA, 0xB13B14, 3883},
++	 {5, 0xBB, 0x13B13B, 3891},
++	 {6, 0xBB, 0x762762, 3899},
++	 {7, 0xBB, 0xD89D8A, 3907},
++	 {8, 0xBC, 0x3B13B1, 3915},
++	 {9, 0xBC, 0x9D89D9, 3923},
++	 {10, 0xBD, 0x000000, 3931},
++	 {11, 0xBD, 0x627627, 3939},
++	 {12, 0xBD, 0xC4EC4F, 3947},
++	 {13, 0xBE, 0x276276, 3955},
++	 {14, 0xBF, 0x13B13B, 3974},
++	 },
++	{
++	 {1, 0xf1, 0x333333, 3859},
++	 {2, 0xf1, 0xB33333, 3867},
++	 {3, 0xf2, 0x333333, 3875},
++	 {4, 0xf2, 0xB33333, 3883},
++	 {5, 0xf3, 0x333333, 3891},
++	 {6, 0xf3, 0xB33333, 3899},
++	 {7, 0xf4, 0x333333, 3907},
++	 {8, 0xf4, 0xB33333, 3915},
++	 {9, 0xf5, 0x333333, 3923},
++	 {10, 0xf5, 0xB33333, 3931},
++	 {11, 0xf6, 0x333333, 3939},
++	 {12, 0xf6, 0xB33333, 3947},
++	 {13, 0xf7, 0x333333, 3955},
++	 {14, 0xf8, 0x666666, 3974},
++	 },
++	{
++	 {1, 0xC9, 0x000000, 3859},
++	 {2, 0xC9, 0x6AAAAB, 3867},
++	 {3, 0xC9, 0xD55555, 3875},
++	 {4, 0xCA, 0x400000, 3883},
++	 {5, 0xCA, 0xAAAAAB, 3891},
++	 {6, 0xCB, 0x155555, 3899},
++	 {7, 0xCB, 0x800000, 3907},
++	 {8, 0xCB, 0xEAAAAB, 3915},
++	 {9, 0xCC, 0x555555, 3923},
++	 {10, 0xCC, 0xC00000, 3931},
++	 {11, 0xCD, 0x2AAAAB, 3939},
++	 {12, 0xCD, 0x955555, 3947},
++	 {13, 0xCE, 0x000000, 3955},
++	 {14, 0xCF, 0x000000, 3974},
++	 }
++};
++
++#define FAIL_MAX 100
++#define RETRY_MAX 20
++int ssv6xxx_set_channel(struct ssv_softc *sc, int ch)
++{
++	struct ssv_hw *sh = sc->sh;
++	int retry_cnt, fail_cnt = 0;
++	u32 regval;
++	int ret = -1;
++	int chidx;
++	bool chidx_vld = 0;
++	dev_dbg(sc->dev, "Setting channel to %d\n", ch);
++	if ((sh->cfg.chip_identity == SSV6051Z)
++	    || (sc->sh->cfg.chip_identity == SSV6051P)) {
++		if ((ch == 13) || (ch == 14)) {
++			if (sh->ipd_channel_touch == 0) {
++				for (chidx = 0; chidx < sh->ch_cfg_size;
++				     chidx++) {
++					SMAC_REG_WRITE(sh,
++						       sh->p_ch_cfg[chidx].
++						       reg_addr,
++						       sh->p_ch_cfg[chidx].
++						       ch13_14_value);
++				}
++				sh->ipd_channel_touch = 1;
++			}
++		} else {
++			if (sh->ipd_channel_touch) {
++				for (chidx = 0; chidx < sh->ch_cfg_size;
++				     chidx++) {
++					SMAC_REG_WRITE(sh,
++						       sh->p_ch_cfg[chidx].
++						       reg_addr,
++						       sh->p_ch_cfg[chidx].
++						       ch1_12_value);
++				}
++				sh->ipd_channel_touch = 0;
++			}
++		}
++	}
++	for (chidx = 0; chidx < 14; chidx++) {
++		if (vt_tbl[sh->cfg.crystal_type][chidx].channel_id == ch) {
++			chidx_vld = 1;
++			break;
++		}
++	}
++	if (chidx_vld == 0) {
++		dev_dbg(sc->dev, "%s(): fail! channel_id not found in vt_tbl\n",
++			__FUNCTION__);
++		goto exit;
++	}
++	if ((ret = ssv6xxx_rf_disable(sc->sh)) != 0)
++		goto exit;
++	do {
++		if ((sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M)
++		    || (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M)) {
++			if ((ret =
++			     SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
++					       (0x00 << 13),
++					       (0x01 << 13))) != 0)
++				break;
++		} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
++			if ((ret =
++			     SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
++					       (0x01 << 13),
++					       (0x01 << 13))) != 0)
++				break;
++		} else {
++			dev_warn(sc->dev, "Illegal crystal setting in ssv6xxx_set_channel\n");
++			BUG_ON(1);
++		}
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
++					     (0x01 << 19), (0x01 << 19))) != 0)
++			break;
++		regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_F;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_1,
++					     (regval << 0),
++					     (0x00ffffff << 0))) != 0)
++			break;
++		regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_N;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_2,
++					     (regval << 0),
++					     (0x07ff << 0))) != 0)
++			break;
++		if ((ret =
++		     SMAC_REG_READ(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
++				   &regval)) != 0)
++			break;
++		regval =
++		    vt_tbl[sh->cfg.crystal_type][chidx].rf_precision_default;
++		if ((ret =
++		     SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_II,
++				       (regval << 0), (0x1fff << 0))) != 0)
++			break;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
++					     (0x00 << 14), (0x01 << 14))) != 0)
++			break;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
++					     (0x01 << 14), (0x01 << 14))) != 0)
++			break;
++		retry_cnt = 0;
++		do {
++			mdelay(1);
++			if ((ret =
++			     SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1,
++					   &regval)) != 0)
++				break;
++			if (regval & 0x00000002) {
++				if ((ret =
++				     SMAC_REG_READ(sc->sh,
++						   ADR_READ_ONLY_FLAGS_2,
++						   &regval)) != 0)
++					break;
++				ret = ssv6xxx_rf_enable(sc->sh);
++				//dev_info(sc->dev, "Lock to channel %d ([0xce010098]=%x)!!\n", vt_tbl[sh->cfg.crystal_type][chidx].channel_id, regval);
++				sc->hw_chan = ch;
++				goto exit;
++			}
++			retry_cnt++;
++		}
++		while (retry_cnt < RETRY_MAX);
++		fail_cnt++;
++		dev_warn(sc->dev, "calibation fail after %d iterations\n", fail_cnt);
++	}
++	while ((fail_cnt < FAIL_MAX) && (ret == 0));
++ exit:
++	if (ch == 14 && regval == 0xff0) {
++		SMAC_IFC_RESET(sc->sh);
++		ssv6xxx_restart_hw(sc);
++	}
++	if (ch <= 7) {
++		if (sh->cfg.tx_power_index_1) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			regval |=
++			    (sh->cfg.tx_power_index_1 << RG_TX_GAIN_OFFSET_SFT);
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		} else if (sh->cfg.tx_power_index_2) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		}
++	} else {
++		if (sh->cfg.tx_power_index_2) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			regval |=
++			    (sh->cfg.tx_power_index_2 << RG_TX_GAIN_OFFSET_SFT);
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		} else if (sh->cfg.tx_power_index_1) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		}
++	}
++	return ret;
++}
++
++#ifdef CONFIG_SSV_SMARTLINK
++int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch)
++{
++	*pch = sc->hw_chan;
++	return 0;
++}
++
++int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept)
++{
++	u32 val = 0;
++	if (accept) {
++		val = 0x2;
++	} else {
++		val = 0x3;
++	}
++	SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB13, val);
++	return 0;
++}
++
++int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept)
++{
++	u32 val = 0;
++	SMAC_REG_READ(sc->sh, ADR_MRX_FLT_TB13, &val);
++	if (val == 0x2) {
++		*paccept = 1;
++	} else {
++		*paccept = 0;
++	}
++	return 0;
++}
++#endif
++int ssv6xxx_rf_enable(struct ssv_hw *sh)
++{
++	return SMAC_REG_SET_BITS(sh, 0xce010000, (0x02 << 12), (0x03 << 12)
++	    );
++}
++
++int ssv6xxx_rf_disable(struct ssv_hw *sh)
++{
++	return SMAC_REG_SET_BITS(sh, 0xce010000, (0x01 << 12), (0x03 << 12)
++	    );
++}
++
++int ssv6xxx_update_decision_table(struct ssv_softc *sc)
++{
++	int i;
++	for (i = 0; i < MAC_DECITBL1_SIZE; i++) {
++		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
++			       sc->mac_deci_tbl[i]);
++		SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
++				 sc->mac_deci_tbl[i]);
++	}
++	for (i = 0; i < MAC_DECITBL2_SIZE; i++) {
++		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
++			       sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
++		SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
++				 sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
++	}
++	return 0;
++}
++
++static int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht)
++{
++#define CTRL_FRAME_INDEX(fc) ((hdr->frame_control-IEEE80211_STYPE_BACK_REQ)>>4)
++	u16 fc, CTRL_FLEN[] = { 16, 16, 16, 16, 10, 10, 16, 16 };
++	int hdr_len = 24;
++	fc = hdr->frame_control;
++	if (ieee80211_is_ctl(fc))
++		hdr_len = CTRL_FLEN[CTRL_FRAME_INDEX(fc)];
++	else if (ieee80211_is_mgmt(fc)) {
++		if (ieee80211_has_order(fc))
++			hdr_len += ((is_ht == 1) ? 4 : 0);
++	} else {
++		if (ieee80211_has_a4(fc))
++			hdr_len += 6;
++		if (ieee80211_is_data_qos(fc)) {
++			hdr_len += 2;
++			if (ieee80211_has_order(hdr->frame_control) &&
++			    is_ht == true)
++				hdr_len += 4;
++		}
++	}
++	return hdr_len;
++}
++
++static u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width,
++			     int half_gi, bool is_gf)
++{
++	u32 nbits, nsymbits, duration, nsymbols;
++	int streams;
++	streams = 1;
++	nbits = (pktlen << 3) + OFDM_PLCP_BITS;
++	nsymbits = bits_per_symbol[rix % 8][width] * streams;
++	nsymbols = (nbits + nsymbits - 1) / nsymbits;
++	if (!half_gi)
++		duration = SYMBOL_TIME(nsymbols);
++	else {
++		if (!is_gf)
++			duration =
++			    DIV_ROUND_UP(SYMBOL_TIME_HALFGI(nsymbols), 4) << 2;
++		else
++			duration = SYMBOL_TIME_HALFGI(nsymbols);
++	}
++	duration +=
++	    L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams) +
++	    HT_SIGNAL_EXT;
++	if (is_gf)
++		duration -= 12;
++	duration += HT_SIFS_TIME;
++	return duration;
++}
++
++static u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps,
++				 u32 frameLen, bool shortPreamble)
++{
++	u32 bits_per_symbol, num_bits, num_symbols;
++	u32 phy_time, tx_time;
++	if (kbps == 0)
++		return 0;
++	switch (phy) {
++	case WLAN_RC_PHY_CCK:
++		phy_time = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
++		if (shortPreamble)
++			phy_time >>= 1;
++		num_bits = frameLen << 3;
++		tx_time = CCK_SIFS_TIME + phy_time + ((num_bits * 1000) / kbps);
++		break;
++	case WLAN_RC_PHY_OFDM:
++		bits_per_symbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
++		num_bits = OFDM_PLCP_BITS + (frameLen << 3);
++		num_symbols = DIV_ROUND_UP(num_bits, bits_per_symbol);
++		tx_time = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
++		    + (num_symbols * OFDM_SYMBOL_TIME);
++		break;
++	default:
++		pr_err("ssv6051: unknown phy %u\n", phy);
++		BUG_ON(1);
++		tx_time = 0;
++		break;
++	}
++	return tx_time;
++}
++
++static u32 ssv6xxx_set_frame_duration(struct ieee80211_tx_info *info,
++				      struct ssv_rate_info *ssv_rate, u16 len,
++				      struct ssv6200_tx_desc *tx_desc,
++				      struct fw_rc_retry_params *rc_params,
++				      struct ssv_softc *sc)
++{
++	struct ieee80211_tx_rate *tx_drate;
++	u32 frame_time = 0, ack_time = 0, rts_cts_nav = 0, frame_consume_time =
++	    0;
++	u32 l_length = 0, drate_kbps = 0, crate_kbps = 0;
++	bool ctrl_short_preamble = false, is_sgi, is_ht40;
++	bool is_ht, is_gf;
++	int d_phy, c_phy, nRCParams, mcsidx;
++	struct ssv_rate_ctrl *ssv_rc = NULL;
++	tx_drate = &info->control.rates[0];
++	is_sgi = !!(tx_drate->flags & IEEE80211_TX_RC_SHORT_GI);
++	is_ht40 = !!(tx_drate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
++	is_ht = !!(tx_drate->flags & IEEE80211_TX_RC_MCS);
++	is_gf = !!(tx_drate->flags & IEEE80211_TX_RC_GREEN_FIELD);
++	if ((info->control.short_preamble) ||
++	    (tx_drate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
++		ctrl_short_preamble = true;
++	pr_debug("mcs = %d, data rate idx=%d\n", tx_drate->idx, tx_drate[3].count);
++	for (nRCParams = 0; (nRCParams < SSV62XX_TX_MAX_RATES); nRCParams++) {
++		if ((rc_params == NULL) || (sc == NULL)) {
++			mcsidx = tx_drate->idx;
++			drate_kbps = ssv_rate->drate_kbps;
++			crate_kbps = ssv_rate->crate_kbps;
++		} else {
++			if (rc_params[nRCParams].count == 0) {
++				break;
++			}
++			ssv_rc = sc->rc;
++			mcsidx =
++			    (rc_params[nRCParams].drate -
++			     SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES;
++			drate_kbps =
++			    ssv_rc->rc_table[rc_params[nRCParams].drate].
++			    rate_kbps;
++			crate_kbps =
++			    ssv_rc->rc_table[rc_params[nRCParams].crate].
++			    rate_kbps;
++		}
++		if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
++			frame_time = ssv6xxx_ht_txtime(mcsidx,
++						       len, is_ht40, is_sgi,
++						       is_gf);
++			d_phy = 0;
++		} else {
++			if ((info->band == INDEX_80211_BAND_2GHZ) &&
++			    !(ssv_rate->d_flags & IEEE80211_RATE_ERP_G))
++				d_phy = WLAN_RC_PHY_CCK;
++			else
++				d_phy = WLAN_RC_PHY_OFDM;
++			frame_time = ssv6xxx_non_ht_txtime(d_phy, drate_kbps,
++							   len,
++							   ctrl_short_preamble);
++		}
++		if ((info->band == INDEX_80211_BAND_2GHZ) &&
++		    !(ssv_rate->c_flags & IEEE80211_RATE_ERP_G))
++			c_phy = WLAN_RC_PHY_CCK;
++		else
++			c_phy = WLAN_RC_PHY_OFDM;
++		if (tx_desc->unicast) {
++			if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++				ack_time = ssv6xxx_non_ht_txtime(c_phy,
++								 crate_kbps,
++								 BA_LEN,
++								 ctrl_short_preamble);
++			} else {
++				ack_time = ssv6xxx_non_ht_txtime(c_phy,
++								 crate_kbps,
++								 ACK_LEN,
++								 ctrl_short_preamble);
++			}
++		}
++		if (tx_desc->do_rts_cts & IEEE80211_TX_RC_USE_RTS_CTS) {
++			rts_cts_nav = frame_time;
++			rts_cts_nav += ack_time;
++			rts_cts_nav += ssv6xxx_non_ht_txtime(c_phy,
++							     crate_kbps,
++							     CTS_LEN,
++							     ctrl_short_preamble);
++			frame_consume_time = rts_cts_nav;
++			frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
++								    crate_kbps,
++								    RTS_LEN,
++								    ctrl_short_preamble);
++		} else if (tx_desc->
++			   do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
++			rts_cts_nav = frame_time;
++			rts_cts_nav += ack_time;
++			frame_consume_time = rts_cts_nav;
++			frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
++								    crate_kbps,
++								    CTS_LEN,
++								    ctrl_short_preamble);
++		} else {;
++		}
++		if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
++			l_length = frame_time - HT_SIFS_TIME;
++			l_length = ((l_length - (HT_SIGNAL_EXT + 20)) + 3) >> 2;
++			l_length += ((l_length << 1) - 3);
++		}
++		if ((rc_params == NULL) || (sc == NULL)) {
++			tx_desc->rts_cts_nav = rts_cts_nav;
++			tx_desc->frame_consume_time =
++			    (frame_consume_time >> 5) + 1;;
++			tx_desc->dl_length = l_length;
++			break;
++		} else {
++			rc_params[nRCParams].rts_cts_nav = rts_cts_nav;
++			rc_params[nRCParams].frame_consume_time =
++			    (frame_consume_time >> 5) + 1;
++			rc_params[nRCParams].dl_length = l_length;
++			if (nRCParams == 0) {
++				tx_desc->drate_idx = rc_params[nRCParams].drate;
++				tx_desc->crate_idx = rc_params[nRCParams].crate;
++				tx_desc->rts_cts_nav =
++				    rc_params[nRCParams].rts_cts_nav;
++				tx_desc->frame_consume_time =
++				    rc_params[nRCParams].frame_consume_time;
++				tx_desc->dl_length =
++				    rc_params[nRCParams].dl_length;
++			}
++		}
++	}
++	return ack_time;
++}
++
++static void ssv6200_hw_set_pair_type(struct ssv_hw *sh, u8 type)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp = (temp & PAIR_SCRT_I_MSK);
++	temp |= (type << PAIR_SCRT_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++	dev_dbg(sh->sc->dev, "==>%s: write cipher type %d into hw\n", __func__, type);
++}
++
++static u32 ssv6200_hw_get_pair_type(struct ssv_hw *sh)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp &= PAIR_SCRT_MSK;
++	temp = (temp >> PAIR_SCRT_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++	dev_dbg(sh->sc->dev, "==>%s: read cipher type %d from hw\n", __func__, temp);
++	return temp;
++}
++
++static void ssv6200_hw_set_group_type(struct ssv_hw *sh, u8 type)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp = temp & GRP_SCRT_I_MSK;
++	temp |= (type << GRP_SCRT_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++	dev_dbg(sh->sc->dev, "Set group key type %d\n", type);
++}
++
++void ssv6xxx_reset_sec_module(struct ssv_softc *sc)
++{
++	ssv6200_hw_set_group_type(sc->sh, ME_NONE);
++	ssv6200_hw_set_pair_type(sc->sh, ME_NONE);
++}
++
++static int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
++				struct ssv_sta_info *sta_info, int sta_idx,
++				int rx_hw_sec, int ops)
++{
++	int ret = 0;
++	int retry_cnt = 20;
++	struct sk_buff *skb = NULL;
++	struct cfg_host_cmd *host_cmd;
++	struct ssv6xxx_wsid_params *ptr;
++	dev_dbg(sc->dev, "cmd=%d for fw wsid list, wsid %d \n", ops, sta_idx);
++	skb =
++	    ssv_skb_alloc(HOST_CMD_HDR_LEN +
++			  sizeof(struct ssv6xxx_wsid_params));
++	if (skb == NULL || sta_info == NULL || sc == NULL)
++		return -1;
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_wsid_params);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_WSID_OP;
++	host_cmd->len = skb->data_len;
++	ptr = (struct ssv6xxx_wsid_params *)host_cmd->dat8;
++	ptr->cmd = ops;
++	ptr->hw_security = rx_hw_sec;
++	if ((ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE)
++	    && (ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE)) {
++		ptr->wsid_idx = (u8) (sta_idx - SSV_NUM_HW_STA);
++	} else {
++		ptr->wsid_idx = (u8) (sta_idx);
++	};
++	memcpy(&ptr->target_wsid, &sta->addr[0], 6);
++	while (((sc->sh->hci.hci_ops->hci_send_cmd(skb)) != 0) && (retry_cnt)) {
++		dev_dbg(sc->dev, "WSID cmd=%d retry=%d!!\n", ops, retry_cnt);
++		retry_cnt--;
++	}
++	dev_dbg(sc->dev, "%s: wsid_idx = %u\n", __FUNCTION__, ptr->wsid_idx);
++	ssv_skb_free(skb);
++	if (ops == SSV6XXX_WSID_OPS_ADD)
++		sta_info->hw_wsid = sta_idx;
++	return ret;
++}
++
++static void hw_crypto_key_clear(struct ieee80211_hw *hw, int index,
++				struct ieee80211_key_conf *key,
++				struct ssv_vif_priv_data *vif_priv,
++				struct ssv_sta_priv_data *sta_priv)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info = NULL;
++	if ((index == 0) && (sta_priv == NULL))
++		return;
++	if ((index < 0) || (index >= 4))
++		return;
++	if (index > 0) {
++		if (vif_priv)
++			vif_priv->group_key_idx = 0;
++		if (sta_priv)
++			sta_priv->group_key_idx = 0;
++	}
++	if (sta_priv) {
++		sta_info = &sc->sta_info[sta_priv->sta_idx];
++		if ((index == 0) && (sta_priv->has_hw_decrypt == true)
++		    && (sta_info->hw_wsid >= SSV_NUM_HW_STA)) {
++			hw_update_watch_wsid(sc, sta_info->sta, sta_info,
++					     sta_priv->sta_idx,
++					     SSV6XXX_WSID_SEC_PAIRWISE,
++					     SSV6XXX_WSID_OPS_DISABLE_CAPS);
++		}
++	}
++	if (vif_priv) {
++		if ((index != 0) && !list_empty(&vif_priv->sta_list)) {
++			struct ssv_sta_priv_data *sta_priv_iter;
++			list_for_each_entry(sta_priv_iter, &vif_priv->sta_list,
++					    list) {
++				if (((sta_priv_iter->sta_info->
++				      s_flags & STA_FLAG_VALID) == 0)
++				    || (sta_priv_iter->sta_info->hw_wsid <
++					SSV_NUM_HW_STA))
++					continue;
++				hw_update_watch_wsid(sc,
++						     sta_priv_iter->sta_info->
++						     sta,
++						     sta_priv_iter->sta_info,
++						     sta_priv_iter->sta_idx,
++						     SSV6XXX_WSID_SEC_GROUP,
++						     SSV6XXX_WSID_OPS_DISABLE_CAPS);
++			}
++		}
++	}
++}
++
++static void _set_wep_sw_crypto_key(struct ssv_softc *sc,
++				   struct ssv_vif_info *vif_info,
++				   struct ssv_sta_info *sta_info, void *param)
++{
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
++	sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
++	sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
++	sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
++}
++
++static void _set_wep_hw_crypto_pair_key(struct ssv_softc *sc,
++					struct ssv_vif_info *vif_info,
++					struct ssv_sta_info *sta_info,
++					void *param)
++{
++	int wsid = sta_info->hw_wsid;
++	struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
++	int address = 0;
++	int *pointer = NULL;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 sec_key_tbl = sec_key_tbl_base;
++	int i;
++	u8 *key = sram_key->sta_key[0].pair.key;
++	u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	if (wsid == (-1))
++		return;
++	sram_key->sta_key[wsid].pair_key_idx = 0;
++	sram_key->sta_key[wsid].group_key_idx = 0;
++	sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
++	sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
++	sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
++	sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
++	if (wsid != 0)
++		memcpy(sram_key->sta_key[wsid].pair.key, key, key_len);
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + wsid * sizeof(struct ssv6xxx_hw_sta_key);
++	address += (0x10000 * wsid);
++	pointer = (int *)&sram_key->sta_key[wsid];
++	for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
++		SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
++}
++
++static void _set_wep_hw_crypto_group_key(struct ssv_softc *sc,
++					 struct ssv_vif_info *vif_info,
++					 struct ssv_sta_info *sta_info,
++					 void *param)
++{
++	int wsid = sta_info->hw_wsid;
++	struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
++	int address = 0;
++	int *pointer = NULL;
++	u32 key_idx = sram_key->sta_key[0].pair_key_idx;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
++	u8 *key = sram_key->group_key[key_idx - 1].key;
++	u32 sec_key_tbl = sec_key_tbl_base;
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	if (wsid == (-1))
++		return;
++	if (wsid != 0) {
++		sram_key->sta_key[wsid].pair_key_idx = key_idx;
++		sram_key->sta_key[wsid].group_key_idx = key_idx;
++		sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
++		sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
++		sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
++		sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
++	}
++	if (wsid != 0)
++		memcpy(sram_key->group_key[key_idx - 1].key, key, key_len);
++	sec_key_tbl += (0x10000 * wsid);
++	address = sec_key_tbl + ((key_idx - 1) * sizeof(struct ssv6xxx_hw_key));
++	pointer = (int *)&sram_key->group_key[key_idx - 1];
++	{
++		int i;
++		for (i = 0; i < (sizeof(struct ssv6xxx_hw_key) / 4); i++)
++			SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
++	}
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
++	pointer = (int *)&sram_key->sta_key[wsid];
++	SMAC_REG_WRITE(sc->sh, address, *(pointer));
++}
++
++static int hw_crypto_key_write_wep(struct ieee80211_hw *hw,
++				   struct ieee80211_key_conf *key,
++				   u8 algorithm, struct ssv_vif_info *vif_info)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
++	if (key->keyidx == 0) {
++		ssv6xxx_foreach_vif_sta(sc, vif_info,
++					_set_wep_hw_crypto_pair_key, sramKey);
++	} else {
++		ssv6xxx_foreach_vif_sta(sc, vif_info,
++					_set_wep_hw_crypto_group_key, sramKey);
++	}
++	return 0;
++}
++
++static void _set_aes_tkip_hw_crypto_group_key(struct ssv_softc *sc,
++					      struct ssv_vif_info *vif_info,
++					      struct ssv_sta_info *sta_info,
++					      void *param)
++{
++	int wsid = sta_info->hw_wsid;
++	int j;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 sec_key_tbl = sec_key_tbl_base;
++	int address = 0;
++	int *pointer = 0;
++	struct ssv6xxx_hw_sec *sramKey = &(vif_info->sramKey);
++	int index = *(u8 *) param;
++	if (wsid == (-1))
++		return;
++	BUG_ON(index == 0);
++	sramKey->sta_key[wsid].group_key_idx = index;
++	sec_key_tbl += (0x10000 * wsid);
++	address = sec_key_tbl + ((index - 1) * sizeof(struct ssv6xxx_hw_key));
++	if (vif_info->vif_priv != NULL)
++		dev_dbg(sc->dev, "Write group key %d to VIF %d to %08X\n",
++			index, vif_info->vif_priv->vif_idx, address);
++	else
++		dev_err(sc->dev, "NULL VIF.\n");
++	pointer = (int *)&sramKey->group_key[index - 1];
++	for (j = 0; j < (sizeof(struct ssv6xxx_hw_key) / 4); j++)
++		SMAC_REG_WRITE(sc->sh, address + (j * 4), *(pointer++));
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
++	pointer = (int *)&sramKey->sta_key[wsid];
++	SMAC_REG_WRITE(sc->sh, address, *(pointer));
++	if (wsid >= SSV_NUM_HW_STA) {
++		hw_update_watch_wsid(sc, sta_info->sta, sta_info,
++				     wsid, SSV6XXX_WSID_SEC_GROUP,
++				     SSV6XXX_WSID_OPS_ENABLE_CAPS);
++	}
++}
++
++static int _write_pairwise_key_to_hw(struct ssv_softc *sc,
++				     int index, u8 algorithm,
++				     const u8 * key, int key_len,
++				     struct ieee80211_key_conf *keyconf,
++				     struct ssv_vif_priv_data *vif_priv,
++				     struct ssv_sta_priv_data *sta_priv)
++{
++	int i;
++	struct ssv6xxx_hw_sec *sramKey;
++	int address = 0;
++	int *pointer = NULL;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 sec_key_tbl;
++	int wsid = (-1);
++	if (sta_priv == NULL) {
++		dev_err(sc->dev, "Set pair-wise key with NULL STA.\n");
++		return -EOPNOTSUPP;
++	}
++	wsid = sta_priv->sta_info->hw_wsid;
++	if ((wsid < 0) || (wsid >= SSV_NUM_STA)) {
++		dev_err(sc->dev, "Set pair-wise key to invalid WSID %d.\n",
++			wsid);
++		return -EOPNOTSUPP;
++	}
++	dev_dbg(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid,
++		key_len);
++	sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
++	sramKey->sta_key[wsid].pair_key_idx = 0;
++	sramKey->sta_key[wsid].group_key_idx = vif_priv->group_key_idx;
++	memcpy(sramKey->sta_key[wsid].pair.key, key, key_len);
++	sec_key_tbl = sec_key_tbl_base;
++	sec_key_tbl += (0x10000 * wsid);
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + wsid * sizeof(struct ssv6xxx_hw_sta_key);
++	pointer = (int *)&sramKey->sta_key[wsid];
++	for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
++		SMAC_REG_WRITE(sc->sh, (address + (i * 4)), *(pointer++));
++	if (wsid >= SSV_NUM_HW_STA) {
++		hw_update_watch_wsid(sc, sta_priv->sta_info->sta,
++				     sta_priv->sta_info, sta_priv->sta_idx,
++				     SSV6XXX_WSID_SEC_PAIRWISE,
++				     SSV6XXX_WSID_OPS_ENABLE_CAPS);
++	}
++	return 0;
++}
++
++static int _write_group_key_to_hw(struct ssv_softc *sc,
++				  int index, u8 algorithm,
++				  const u8 * key, int key_len,
++				  struct ieee80211_key_conf *keyconf,
++				  struct ssv_vif_priv_data *vif_priv,
++				  struct ssv_sta_priv_data *sta_priv)
++{
++	struct ssv6xxx_hw_sec *sramKey;
++	int wsid = sta_priv ? sta_priv->sta_info->hw_wsid : (-1);
++	int ret = 0;
++	if (vif_priv == NULL) {
++		dev_err(sc->dev, "Setting group key to NULL VIF\n");
++		return -EOPNOTSUPP;
++	}
++	dev_dbg(sc->dev,
++		"Setting VIF %d group key %d of length %d to WSID %d.\n",
++		vif_priv->vif_idx, index, key_len, wsid);
++	sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
++	vif_priv->group_key_idx = index;
++	if (sta_priv)
++		sta_priv->group_key_idx = index;
++	memcpy(sramKey->group_key[index - 1].key, key, key_len);
++	WARN_ON(sc->vif_info[vif_priv->vif_idx].vif_priv == NULL);
++	ssv6xxx_foreach_vif_sta(sc, &sc->vif_info[vif_priv->vif_idx],
++				_set_aes_tkip_hw_crypto_group_key, &index);
++	ret = 0;
++	return ret;
++}
++
++static enum SSV_CIPHER_E _prepare_key(struct ieee80211_key_conf *key)
++{
++	enum SSV_CIPHER_E cipher;
++	switch (key->cipher) {
++	case WLAN_CIPHER_SUITE_WEP40:
++		cipher = SSV_CIPHER_WEP40;
++		break;
++	case WLAN_CIPHER_SUITE_WEP104:
++		cipher = SSV_CIPHER_WEP104;
++		break;
++	case WLAN_CIPHER_SUITE_TKIP:
++		key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
++		cipher = SSV_CIPHER_TKIP;
++		break;
++	case WLAN_CIPHER_SUITE_CCMP:
++		key->flags |=
++		    (IEEE80211_KEY_FLAG_SW_MGMT_TX |
++		     IEEE80211_KEY_FLAG_RX_MGMT);
++		cipher = SSV_CIPHER_CCMP;
++		break;
++	default:
++		cipher = SSV_CIPHER_INVALID;
++		break;
++	}
++	return cipher;
++}
++int _set_key_wep(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
++		 struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
++		 struct ieee80211_key_conf *key)
++{
++	int ret = 0;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	struct ssv6xxx_hw_sec *sram_key = &vif_info->sramKey;
++	sram_key->sta_key[0].pair_key_idx = key->keyidx;
++	sram_key->sta_key[0].group_key_idx = key->keyidx;
++	*(u16 *) & sram_key->sta_key[0].reserve[0] = key->keylen;
++	dev_dbg(sc->dev, "Set WEP %02X %02X %02X %02X %02X %02X %02X %02X... (%d %d)\n",
++	       key->key[0], key->key[1], key->key[2], key->key[3], key->key[4],
++	       key->key[5], key->key[6], key->key[7], key->keyidx, key->keylen);
++	if (key->keyidx == 0) {
++		memcpy(sram_key->sta_key[0].pair.key, key->key, key->keylen);
++	} else {
++		memcpy(sram_key->group_key[key->keyidx - 1].key, key->key,
++		       key->keylen);
++	}
++	if (sc->sh->cfg.use_wpa2_only) {
++		dev_warn(sc->dev, "WEP: use WPA2 HW security mode only.\n");
++	}
++	if ((sc->sh->cfg.use_wpa2_only == 0)
++	    && vif_priv->vif_idx == 0) {
++		vif_priv->has_hw_decrypt = true;
++		vif_priv->has_hw_encrypt = true;
++		vif_priv->need_sw_decrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = false;
++		ssv6200_hw_set_pair_type(sc->sh, cipher);
++		ssv6200_hw_set_group_type(sc->sh, cipher);
++		hw_crypto_key_write_wep(sc->hw, key, cipher,
++					&sc->vif_info[vif_priv->vif_idx]);
++	} else {
++		vif_priv->has_hw_decrypt = false;
++		vif_priv->has_hw_encrypt = false;
++		vif_priv->need_sw_decrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = true;
++		ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_sw_crypto_key,
++					NULL);
++		ret = -EOPNOTSUPP;
++	}
++	vif_priv->pair_cipher = vif_priv->group_cipher = cipher;
++	vif_priv->is_security_valid = true;
++	return ret;
++}
++
++static int _set_pairwise_key_tkip_ccmp(struct ssv_softc *sc,
++				       struct ssv_vif_priv_data *vif_priv,
++				       struct ssv_sta_priv_data *sta_priv,
++				       enum SSV_CIPHER_E cipher,
++				       struct ieee80211_key_conf *key)
++{
++	int ret = 0;
++	const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	bool tdls_link = false, tdls_use_sw_cipher = false, tkip_use_sw_cipher =
++	    false;
++	bool use_non_ccmp = false;
++	int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
++	struct ssv_vif_priv_data *another_vif_priv =
++	    (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv;
++	if (sta_priv == NULL) {
++		dev_err(sc->dev,
++			"Setting pairwise TKIP/CCMP key to NULL STA.\n");
++		return -EOPNOTSUPP;
++	}
++	if (sc->sh->cfg.use_wpa2_only) {
++		dev_warn(sc->dev, "Pairwise TKIP/CCMP: use WPA2 HW security mode only.\n");
++	}
++	if (vif_info->if_type == NL80211_IFTYPE_STATION) {
++		struct ssv_sta_priv_data *first_sta_priv =
++		    list_first_entry(&vif_priv->sta_list,
++				     struct ssv_sta_priv_data, list);
++		if (first_sta_priv->sta_idx != sta_priv->sta_idx) {
++			tdls_link = true;
++		}
++		dev_dbg(sc->dev, "first sta idx %d, current sta idx %d\n",
++		       first_sta_priv->sta_idx, sta_priv->sta_idx);
++	}
++	if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
++	    && (sc->sh->cfg.use_wpa2_only == false)) {
++		tdls_use_sw_cipher = true;
++	}
++	if (another_vif_priv != NULL) {
++		if ((another_vif_priv->pair_cipher != SSV_CIPHER_CCMP)
++		    && (another_vif_priv->pair_cipher != SSV_CIPHER_NONE)) {
++			use_non_ccmp = true;
++			dev_dbg(sc->dev, "another vif use none ccmp\n");
++		}
++	}
++	if ((((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP))
++	     || (use_non_ccmp))
++	    && (sc->sh->cfg.use_wpa2_only == 1) && (cipher == SSV_CIPHER_CCMP)) {
++		u32 val;
++		SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
++		if (((val >> 4) & 0xF) != M_ENG_CPU) {
++			SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++				       ((val & 0xf) | (M_ENG_CPU << 4)
++					| (val & 0xfffffff0) << 4));
++			dev_dbg(sc->dev,
++				"orginal Rx_Flow %x , modified flow %x \n", val,
++				((val & 0xf) | (M_ENG_CPU << 4) |
++				 (val & 0xfffffff0) << 4));
++		}
++	}
++	if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
++		tkip_use_sw_cipher = true;
++	}
++	if (tkip_use_sw_cipher == true)
++		dev_info(sc->dev, "Using software TKIP cipher\n");
++	if ((((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false)
++	      && (tkip_use_sw_cipher == false)))
++	    || ((cipher == SSV_CIPHER_CCMP)
++		&& (sc->sh->cfg.use_wpa2_only == 1))) {
++		sta_priv->has_hw_decrypt = true;
++		sta_priv->need_sw_decrypt = false;
++		if ((cipher == SSV_CIPHER_TKIP)
++		    || ((!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX) ||
++			 (sta_priv->sta_info->sta->deflink.ht_cap.ht_supported ==
++			  false))
++			&& (vif_priv->force_sw_encrypt == false))) {
++			dev_dbg(sc->dev,
++				"STA %d uses HW encrypter for pairwise.\n",
++				sta_priv->sta_idx);
++			sta_priv->has_hw_encrypt = true;
++			sta_priv->need_sw_encrypt = false;
++			sta_priv->use_mac80211_decrypt = false;
++			ret = 0;
++		} else {
++			sta_priv->has_hw_encrypt = false;
++			sta_priv->need_sw_encrypt = false;
++			sta_priv->use_mac80211_decrypt = true;
++			ret = -EOPNOTSUPP;
++		}
++	} else {
++		sta_priv->has_hw_encrypt = false;
++		sta_priv->has_hw_decrypt = false;
++		dev_err(sc->dev, "STA %d MAC80211's %s cipher.\n",
++			sta_priv->sta_idx, cipher_name);
++		sta_priv->need_sw_encrypt = false;
++		sta_priv->need_sw_decrypt = false;
++		sta_priv->use_mac80211_decrypt = true;
++		ret = -EOPNOTSUPP;
++	}
++	if (sta_priv->has_hw_encrypt || sta_priv->has_hw_decrypt) {
++		ssv6200_hw_set_pair_type(sc->sh, cipher);
++		_write_pairwise_key_to_hw(sc, key->keyidx, cipher,
++					  key->key, key->keylen, key,
++					  vif_priv, sta_priv);
++	}
++	if ((vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt)
++	    && (vif_priv->group_key_idx > 0)) {
++		_set_aes_tkip_hw_crypto_group_key(sc,
++						  &sc->vif_info[vif_priv->
++								vif_idx],
++						  sta_priv->sta_info,
++						  &vif_priv->group_key_idx);
++	}
++	return ret;
++}
++
++static int _set_group_key_tkip_ccmp(struct ssv_softc *sc,
++				    struct ssv_vif_priv_data *vif_priv,
++				    struct ssv_sta_priv_data *sta_priv,
++				    enum SSV_CIPHER_E cipher,
++				    struct ieee80211_key_conf *key)
++{
++	int ret = 0;
++	const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
++	bool tkip_use_sw_cipher = false;
++	vif_priv->group_cipher = cipher;
++	if (sc->sh->cfg.use_wpa2_only) {
++		dev_warn(sc->dev, "Group TKIP/CCMP: use WPA2 HW security mode only.\n");
++	}
++	if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
++		tkip_use_sw_cipher = true;
++	}
++	if (((vif_priv->vif_idx == 0) && (tkip_use_sw_cipher == false))
++	    || ((cipher == SSV_CIPHER_CCMP)
++		&& (sc->sh->cfg.use_wpa2_only == 1))) {
++		dev_dbg(sc->dev, "VIF %d uses HW %s cipher for group.\n",
++			vif_priv->vif_idx, cipher_name);
++#ifdef USE_MAC80211_DECRYPT_BROADCAST
++		vif_priv->has_hw_decrypt = false;
++		ret = -EOPNOTSUPP;
++#else
++		vif_priv->has_hw_decrypt = true;
++#endif
++		vif_priv->has_hw_encrypt = true;
++		vif_priv->need_sw_decrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = false;
++	} else {
++		vif_priv->has_hw_decrypt = false;
++		vif_priv->has_hw_encrypt = false;
++		dev_err(sc->dev, "VIF %d uses MAC80211's %s cipher.\n",
++			vif_priv->vif_idx, cipher_name);
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = true;
++		ret = -EOPNOTSUPP;
++	}
++	if (vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt) {
++#ifdef USE_MAC80211_DECRYPT_BROADCAST
++		ssv6200_hw_set_group_type(sc->sh, ME_NONE);
++#else
++		ssv6200_hw_set_group_type(sc->sh, cipher);
++#endif
++		key->hw_key_idx = key->keyidx;
++		_write_group_key_to_hw(sc, key->keyidx, cipher,
++				       key->key, key->keylen, key,
++				       vif_priv, sta_priv);
++	}
++	vif_priv->is_security_valid = true;
++	{
++		int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
++		struct ssv_vif_priv_data *another_vif_priv =
++		    (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].
++		    vif_priv;
++		if (another_vif_priv != NULL) {
++			if (((SSV6XXX_USE_SW_DECRYPT(vif_priv)
++			      && SSV6XXX_USE_HW_DECRYPT(another_vif_priv)))
++			    || ((SSV6XXX_USE_HW_DECRYPT(vif_priv)
++				 &&
++				 (SSV6XXX_USE_SW_DECRYPT(another_vif_priv))))) {
++				u32 val;
++				SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
++				if (((val >> 4) & 0xF) != M_ENG_CPU) {
++					SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++						       ((val & 0xf) |
++							(M_ENG_CPU << 4)
++							| (val & 0xfffffff0) <<
++							4));
++					dev_dbg(sc->dev,
++						"orginal Rx_Flow %x , modified flow %x \n",
++						val,
++						((val & 0xf) | (M_ENG_CPU << 4)
++						 | (val & 0xfffffff0) << 4));
++				} else {
++					dev_dbg(sc->dev, " doesn't need to change rx flow\n");
++				}
++			}
++		}
++	}
++	return ret;
++}
++
++static int _set_key_tkip_ccmp(struct ssv_softc *sc,
++			      struct ssv_vif_priv_data *vif_priv,
++			      struct ssv_sta_priv_data *sta_priv,
++			      enum SSV_CIPHER_E cipher,
++			      struct ieee80211_key_conf *key)
++{
++	if (key->keyidx == 0)
++		return _set_pairwise_key_tkip_ccmp(sc, vif_priv, sta_priv,
++						   cipher, key);
++	else
++		return _set_group_key_tkip_ccmp(sc, vif_priv, sta_priv, cipher,
++						key);
++}
++
++static int ssv6200_set_key(struct ieee80211_hw *hw,
++			   enum set_key_cmd cmd,
++			   struct ieee80211_vif *vif,
++			   struct ieee80211_sta *sta,
++			   struct ieee80211_key_conf *key)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	enum SSV_CIPHER_E cipher = SSV_CIPHER_NONE;
++	int sta_idx = (-1);
++	struct ssv_sta_info *sta_info = NULL;
++	struct ssv_sta_priv_data *sta_priv = NULL;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	if (sta) {
++		sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		sta_idx = sta_priv->sta_idx;
++		sta_info = sta_priv->sta_info;
++	}
++	BUG_ON((cmd != SET_KEY) && (cmd != DISABLE_KEY));
++	if (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_SECURITY)) {
++		dev_warn(sc->dev, "HW does not support security.\n");
++		return -EOPNOTSUPP;
++	}
++	if (sta_info && (sta_info->hw_wsid == (-1))) {
++		dev_warn(sc->dev,
++			 "Add STA without HW resource. Use MAC80211's solution.\n");
++		return -EOPNOTSUPP;
++	}
++	cipher = _prepare_key(key);
++	dev_dbg(sc->dev,
++		"Set key VIF %d VIF type %d STA %d algorithm = %d, key->keyidx = %d, cmd = %d\n",
++		vif_priv->vif_idx, vif->type, sta_idx, cipher, key->keyidx,
++		cmd);
++	if (cipher == SSV_CIPHER_INVALID) {
++		dev_warn(sc->dev, "Unsupported cipher type.\n");
++		return -EOPNOTSUPP;
++	}
++	mutex_lock(&sc->mutex);
++	switch (cmd) {
++	case SET_KEY:
++		{
++			switch (cipher) {
++			case SSV_CIPHER_WEP40:
++			case SSV_CIPHER_WEP104:
++				ret =
++				    _set_key_wep(sc, vif_priv, sta_priv, cipher,
++						 key);
++				break;
++			case SSV_CIPHER_TKIP:
++			case SSV_CIPHER_CCMP:
++				ret =
++				    _set_key_tkip_ccmp(sc, vif_priv, sta_priv,
++						       cipher, key);
++				break;
++			default:
++				break;
++			}
++			if (sta) {
++				struct ssv_sta_priv_data *first_sta_priv =
++				    list_first_entry(&vif_priv->sta_list,
++						     struct ssv_sta_priv_data,
++						     list);
++				if (first_sta_priv->sta_idx ==
++				    sta_priv->sta_idx) {
++					vif_priv->pair_cipher = cipher;
++				}
++				if (SSV6200_USE_HW_WSID(sta_idx)) {
++					if (SSV6XXX_USE_SW_DECRYPT(sta_priv)) {
++						u32 cipher_setting;
++						cipher_setting =
++						    ssv6200_hw_get_pair_type
++						    (sc->sh);
++						if (cipher_setting != ME_NONE) {
++							u32 val;
++							SMAC_REG_READ(sc->sh,
++								      ADR_RX_FLOW_DATA,
++								      &val);
++							if (((val >> 4) & 0xF)
++							    != M_ENG_CPU) {
++								SMAC_REG_WRITE
++								    (sc->sh,
++								     ADR_RX_FLOW_DATA,
++								     ((val &
++								       0xf) |
++								      (M_ENG_CPU
++								       << 4)
++								      | (val &
++									 0xfffffff0)
++								      << 4));
++								dev_dbg(sc->dev,
++									"orginal Rx_Flow %x , modified flow %x \n",
++									val,
++									((val &
++									  0xf) |
++									 (M_ENG_CPU
++									  << 4)
++									 | (val
++									    &
++									    0xfffffff0)
++									 << 4));
++							} else {
++								dev_dbg(sc->dev, " doesn't need to change rx flow\n");
++							}
++						}
++					}
++					if (sta_priv->has_hw_decrypt) {
++						hw_update_watch_wsid(sc, sta,
++								     sta_info,
++								     sta_idx,
++								     SSV6XXX_WSID_SEC_HW,
++								     SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
++						dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for pairwise key\n", sta_idx);
++					}
++				}
++			} else {
++				if (vif_info->if_type == NL80211_IFTYPE_STATION) {
++					struct ssv_sta_priv_data *first_sta_priv
++					    =
++					    list_first_entry(&vif_priv->
++							     sta_list,
++							     struct
++							     ssv_sta_priv_data,
++							     list);
++					if (SSV6200_USE_HW_WSID
++					    (first_sta_priv->sta_idx)) {
++						if (vif_priv->has_hw_decrypt) {
++							hw_update_watch_wsid(sc,
++									     sta,
++									     sta_info,
++									     first_sta_priv->
++									     sta_idx,
++									     SSV6XXX_WSID_SEC_HW,
++									     SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
++							dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for group key\n", first_sta_priv->sta_idx);
++						}
++					}
++				}
++			}
++		}
++		break;
++	case DISABLE_KEY:
++		{
++			int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
++			struct ssv_vif_priv_data *another_vif_priv =
++			    (struct ssv_vif_priv_data *)sc->
++			    vif_info[another_vif_idx].vif_priv;
++			if (another_vif_priv != NULL) {
++				struct ssv_vif_info *vif_info =
++				    &sc->vif_info[vif_priv->vif_idx];
++				if (vif_info->if_type != NL80211_IFTYPE_AP) {
++					if ((SSV6XXX_USE_SW_DECRYPT(vif_priv)
++					     &&
++					     SSV6XXX_USE_HW_DECRYPT
++					     (another_vif_priv))
++					    ||
++					    (SSV6XXX_USE_SW_DECRYPT
++					     (another_vif_priv)
++					     &&
++					     SSV6XXX_USE_HW_DECRYPT(vif_priv)))
++					{
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_FLOW_DATA,
++							       M_ENG_MACRX |
++							       (M_ENG_ENCRYPT_SEC
++								<< 4) |
++							       (M_ENG_HWHCI <<
++								8));
++						dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
++					}
++				} else {
++					if (sta == NULL) {
++						if (SSV6XXX_USE_SW_DECRYPT
++						    (another_vif_priv)
++						    &&
++						    SSV6XXX_USE_HW_DECRYPT
++						    (vif_priv)) {
++							SMAC_REG_WRITE(sc->sh,
++								       ADR_RX_FLOW_DATA,
++								       M_ENG_MACRX
++								       |
++								       (M_ENG_ENCRYPT_SEC
++									<< 4) |
++								       (M_ENG_HWHCI
++									<< 8));
++							dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
++						}
++					}
++				}
++			}
++			if (sta == NULL) {
++				vif_priv->group_cipher = ME_NONE;
++				if ((another_vif_priv == NULL)
++				    || ((another_vif_priv != NULL)
++					&&
++					(!SSV6XXX_USE_HW_DECRYPT
++					 (another_vif_priv)))) {
++					ssv6200_hw_set_group_type(sc->sh,
++								  ME_NONE);
++				}
++			} else {
++				struct ssv_vif_info *vif_info =
++				    &sc->vif_info[vif_priv->vif_idx];
++				if ((vif_info->if_type != NL80211_IFTYPE_AP)
++				    && (another_vif_priv == NULL)) {
++					struct ssv_sta_priv_data *first_sta_priv
++					    =
++					    list_first_entry(&vif_priv->
++							     sta_list,
++							     struct
++							     ssv_sta_priv_data,
++							     list);
++					if (sta_priv == first_sta_priv) {
++						ssv6200_hw_set_pair_type(sc->sh,
++									 ME_NONE);
++					}
++				}
++				vif_priv->pair_cipher = ME_NONE;
++			}
++			if ((cipher == ME_TKIP) || (cipher == ME_CCMP)) {
++				dev_dbg(sc->dev, "Clear key %d VIF %d, STA %d\n",
++				       key->keyidx, (vif != NULL),
++				       (sta != NULL));
++				hw_crypto_key_clear(hw, key->keyidx, key,
++						    vif_priv, sta_priv);
++			}
++			{
++				if ((key->keyidx == 0) && (sta_priv != NULL)) {
++					sta_priv->has_hw_decrypt = false;
++					sta_priv->has_hw_encrypt = false;
++					sta_priv->need_sw_encrypt = false;
++					sta_priv->use_mac80211_decrypt = false;
++				}
++				if ((vif_priv->is_security_valid)
++				    && (key->keyidx != 0)) {
++					vif_priv->is_security_valid = false;
++				}
++			}
++			ret = 0;
++		}
++		break;
++	default:
++		ret = -EINVAL;
++	}
++	mutex_unlock(&sc->mutex);
++	if (sta_priv != NULL) {
++		dev_info(sc->dev, "station mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d\n",
++		       (sta_priv->has_hw_encrypt == true),
++		       (sta_priv->has_hw_decrypt == true),
++		       (sta_priv->need_sw_encrypt == true),
++		       (sta_priv->need_sw_decrypt == true));
++	}
++	if (vif_priv) {
++		dev_info
++		    (sc->dev, "vif mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d, mac80211 decrypt: %d, valid:%d\n",
++		     (vif_priv->has_hw_encrypt == true),
++		     (vif_priv->has_hw_decrypt == true),
++		     (vif_priv->need_sw_encrypt == true),
++		     (vif_priv->need_sw_decrypt == true),
++		     (vif_priv->use_mac80211_decrypt == true),
++		     (vif_priv->is_security_valid == true));
++	}
++	if (vif_priv->force_sw_encrypt
++	    || (sta_info && (sta_info->hw_wsid != 1)
++		&& (sta_info->hw_wsid != 0))) {
++		if (vif_priv->force_sw_encrypt == false)
++			vif_priv->force_sw_encrypt = true;
++		ret = -EOPNOTSUPP;
++	}
++	dev_dbg(sc->dev, "SET KEY %d\n", ret);
++	return ret;
++}
++
++u32 _process_tx_done(struct ssv_softc *sc)
++{
++	struct ieee80211_tx_info *tx_info;
++	struct sk_buff *skb;
++	while ((skb = skb_dequeue(&sc->tx_done_q))) {
++		struct ssv6200_tx_desc *tx_desc;
++		tx_info = IEEE80211_SKB_CB(skb);
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		if (tx_desc->c_type > M2_TXREQ) {
++			ssv_skb_free(skb);
++			dev_dbg(sc->dev, "free cmd skb!\n");
++			continue;
++		}
++		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
++			ssv6200_ampdu_release_skb(skb, sc->hw);
++			continue;
++		}
++		skb_pull(skb, SSV6XXX_TX_DESC_LEN);
++		ieee80211_tx_info_clear_status(tx_info);
++		tx_info->flags |= IEEE80211_TX_STAT_ACK;
++		tx_info->status.ack_signal = 100;
++#ifdef REPORT_TX_DONE_IN_IRQ
++		ieee80211_tx_status_irqsafe(sc->hw, skb);
++#else
++		ieee80211_tx_status_skb(sc->hw, skb);
++		if (skb_queue_len(&sc->rx_skb_q))
++			break;
++#endif
++	}
++	return skb_queue_len(&sc->tx_done_q);
++}
++
++#ifdef REPORT_TX_DONE_IN_IRQ
++void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)args;
++	_process_tx_done *(sc);
++}
++#else
++void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)args;
++	struct sk_buff *skb;
++	while ((skb = skb_dequeue(skb_head))) {
++		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++		struct ssv6200_tx_desc *tx_desc;
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		if (tx_desc->c_type > M2_TXREQ) {
++			ssv_skb_free(skb);
++			dev_dbg(sc->dev, "free cmd skb!\n");
++			continue;
++		}
++		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
++			ssv6xxx_ampdu_sent(sc->hw, skb);
++		skb_queue_tail(&sc->tx_done_q, skb);
++	}
++	wake_up_interruptible(&sc->rx_wait_q);
++}
++#endif
++void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args)
++{
++	struct ieee80211_hdr *hdr;
++	struct ssv_softc *sc = args;
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ssv6200_tx_desc *tx_desc;
++	struct ssv_rate_info ssv_rate;
++	u32 nav = 0;
++	int ret = 0;
++	tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	if (tx_desc->c_type > M2_TXREQ)
++		return;
++	if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) {
++		hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_TX_DESC_LEN);
++		if ((ieee80211_is_data_qos(hdr->frame_control)
++		     || ieee80211_is_data(hdr->frame_control))
++		    && (tx_desc->wsid < SSV_RC_MAX_HARDWARE_SUPPORT)) {
++			ret =
++			    ssv6xxx_rc_hw_rate_update_check(skb, sc,
++							    tx_desc->
++							    do_rts_cts);
++			if (ret & RC_FIRMWARE_REPORT_FLAG) {
++				{
++					tx_desc->RSVD_0 = SSV6XXX_RC_REPORT;
++					tx_desc->tx_report = 1;
++				}
++				ret &= 0xf;
++			}
++			if (ret) {
++				ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
++				tx_desc->crate_idx = ssv_rate.crate_hw_idx;
++				tx_desc->drate_idx = ssv_rate.drate_hw_idx;
++				nav =
++				    ssv6xxx_set_frame_duration(info, &ssv_rate,
++							       skb->len +
++							       FCS_LEN, tx_desc,
++							       NULL, NULL);
++				if (tx_desc->tx_burst == 0) {
++					if (tx_desc->ack_policy != 0x01)
++						hdr->duration_id = nav;
++				}
++			}
++		}
++	} else {
++	}
++	return;
++}
++
++void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct ieee80211_hdr *hdr;
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_sta *sta;
++	struct ssv_sta_info *sta_info = NULL;
++	struct ssv_sta_priv_data *ssv_sta_priv = NULL;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
++	struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	struct ieee80211_tx_rate *tx_drate;
++	struct ssv_rate_info ssv_rate;
++	int ac, hw_txqid;
++	u32 nav = 0;
++	if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++		struct ampdu_hdr_st *ampdu_hdr =
++		    (struct ampdu_hdr_st *)skb->head;
++		sta = ampdu_hdr->ampdu_tid->sta;
++		hdr =
++		    (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET +
++					     AMPDU_DELIMITER_LEN);
++	} else {
++		struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++		sta = skb_info->sta;
++		hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET);
++	}
++	if (sta) {
++		ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		sta_info = ssv_sta_priv->sta_info;
++	}
++	if ((!sc->bq4_dtim) &&
++	    (ieee80211_is_mgmt(hdr->frame_control) ||
++	     ieee80211_is_nullfunc(hdr->frame_control) ||
++	     ieee80211_is_qos_nullfunc(hdr->frame_control))) {
++		ac = 4;
++		hw_txqid = 4;
++	} else if ((sc->bq4_dtim) &&
++		   info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
++		hw_txqid = 4;
++		ac = 4;
++	} else {
++		ac = skb_get_queue_mapping(skb);
++		hw_txqid = sc->tx.hw_txqid[ac];
++	}
++	tx_drate = &info->control.rates[0];
++	ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
++	tx_desc->len = skb->len;
++	tx_desc->c_type = M2_TXREQ;
++	tx_desc->f80211 = 1;
++	tx_desc->qos = (ieee80211_is_data_qos(hdr->frame_control)) ? 1 : 0;
++	if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
++		if (ieee80211_is_mgmt(hdr->frame_control) &&
++		    ieee80211_has_order(hdr->frame_control))
++			tx_desc->ht = 1;
++	}
++	tx_desc->use_4addr = (ieee80211_has_a4(hdr->frame_control)) ? 1 : 0;
++	tx_desc->more_data =
++	    (ieee80211_has_morefrags(hdr->frame_control)) ? 1 : 0;
++	tx_desc->stype_b5b4 = (cpu_to_le16(hdr->frame_control) >> 4) & 0x3;
++	tx_desc->frag = (tx_desc->more_data || (hdr->seq_ctrl & 0xf)) ? 1 : 0;
++	tx_desc->unicast = (is_multicast_ether_addr(hdr->addr1)) ? 0 : 1;
++	tx_desc->tx_burst = (tx_desc->frag) ? 1 : 0;
++	tx_desc->wsid = (!sta_info
++			 || (sta_info->hw_wsid < 0)) ? 0x0F : sta_info->hw_wsid;
++	tx_desc->txq_idx = hw_txqid;
++	tx_desc->hdr_offset = TXPB_OFFSET;
++	tx_desc->hdr_len = ssv6xxx_frame_hdrlen(hdr, tx_desc->ht);
++	tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
++	if (info->control.use_rts)
++		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
++	else if (info->control.use_cts_prot)
++		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_CTS_PROTECT;
++	if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT)
++		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
++	if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT) {
++		tx_desc->crate_idx = 0;
++	} else
++		tx_desc->crate_idx = ssv_rate.crate_hw_idx;
++	tx_desc->drate_idx = ssv_rate.drate_hw_idx;
++	if (tx_desc->unicast == 0)
++		tx_desc->ack_policy = 1;
++	else if (tx_desc->qos == 1)
++		tx_desc->ack_policy = (*ieee80211_get_qos_ctl(hdr) & 0x60) >> 5;
++	else if (ieee80211_is_ctl(hdr->frame_control))
++		tx_desc->ack_policy = 1;
++	tx_desc->security = 0;
++	tx_desc->fCmdIdx = 0;
++	tx_desc->fCmd = (hw_txqid + M_ENG_TX_EDCA0);
++	if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++#ifdef AMPDU_HAS_LEADING_FRAME
++		tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_CPU;
++#else
++		tx_desc->RSVD_1 = 1;
++#endif
++		tx_desc->aggregation = 1;
++		tx_desc->ack_policy = 0x01;
++		if ((tx_desc->do_rts_cts == 0)
++		    && ((sc->hw->wiphy->rts_threshold == (-1))
++			|| ((skb->len - sc->sh->tx_desc_len) >
++			    sc->hw->wiphy->rts_threshold))) {
++			tx_drate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
++			tx_desc->do_rts_cts = 1;
++		}
++	}
++	if (ieee80211_has_protected(hdr->frame_control)
++	    && (ieee80211_is_data_qos(hdr->frame_control)
++		|| ieee80211_is_data(hdr->frame_control))) {
++		if ((tx_desc->unicast && ssv_sta_priv
++		     && ssv_sta_priv->has_hw_encrypt)
++		    || (!tx_desc->unicast && vif_priv
++			&& vif_priv->has_hw_encrypt)) {
++			if (!tx_desc->unicast
++			    && !list_empty(&vif_priv->sta_list)) {
++				struct ssv_sta_priv_data *one_sta_priv;
++				int hw_wsid;
++				one_sta_priv =
++				    list_first_entry(&vif_priv->sta_list,
++						     struct ssv_sta_priv_data,
++						     list);
++				hw_wsid = one_sta_priv->sta_info->hw_wsid;
++				if (hw_wsid != (-1)) {
++					tx_desc->wsid = hw_wsid;
++				}
++			}
++			tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_ENCRYPT;
++		} else if (ssv_sta_priv->need_sw_encrypt) {
++		} else {
++		}
++	} else {
++	}
++	tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_HWHCI;
++	if (tx_desc->aggregation == 1) {
++		struct ampdu_hdr_st *ampdu_hdr =
++		    (struct ampdu_hdr_st *)skb->head;
++		memcpy(&tx_desc->rc_params[0], ampdu_hdr->rates,
++		       sizeof(tx_desc->rc_params));
++		nav =
++		    ssv6xxx_set_frame_duration(info, &ssv_rate,
++					       (skb->len + FCS_LEN), tx_desc,
++					       &tx_desc->rc_params[0], sc);
++#ifdef FW_RC_RETRY_DEBUG
++		{
++			dev_dbg
++			    (sc->dev, "[FW_RC]:param[0]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
++			     tx_desc->rc_params[0].drate,
++			     tx_desc->rc_params[0].count,
++			     tx_desc->rc_params[0].crate,
++			     tx_desc->rc_params[0].dl_length,
++			     tx_desc->rc_params[0].frame_consume_time,
++			     tx_desc->rc_params[0].rts_cts_nav);
++			dev_dbg
++			    (sc->dev, "[FW_RC]:param[1]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
++			     tx_desc->rc_params[1].drate,
++			     tx_desc->rc_params[1].count,
++			     tx_desc->rc_params[1].crate,
++			     tx_desc->rc_params[1].dl_length,
++			     tx_desc->rc_params[1].frame_consume_time,
++			     tx_desc->rc_params[1].rts_cts_nav);
++			dev_dbg
++			    (sc->dev, "[FW_RC]:param[2]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
++			     tx_desc->rc_params[2].drate,
++			     tx_desc->rc_params[2].count,
++			     tx_desc->rc_params[2].crate,
++			     tx_desc->rc_params[2].dl_length,
++			     tx_desc->rc_params[2].frame_consume_time,
++			     tx_desc->rc_params[2].rts_cts_nav);
++		}
++#endif
++	} else {
++		nav =
++		    ssv6xxx_set_frame_duration(info, &ssv_rate,
++					       (skb->len + FCS_LEN), tx_desc,
++					       NULL, NULL);
++	}
++	if ((tx_desc->aggregation == 0)) {
++		if (tx_desc->tx_burst == 0) {
++			if (tx_desc->ack_policy != 0x01)
++				hdr->duration_id = nav;
++		} else {
++		}
++	}
++}
++
++void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct ssv6200_tx_desc *tx_desc;
++	skb_push(skb, sc->sh->tx_desc_len);
++	tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	memset((void *)tx_desc, 0, sc->sh->tx_desc_len);
++	ssv6xxx_update_txinfo(sc, skb);
++}
++
++int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_tx_rate *tx_drate;
++	struct ssv_rate_info ssv_rate;
++	tx_drate = &info->control.rates[0];
++	ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
++	return ssv_rate.drate_hw_idx;
++}
++
++static void _ssv6xxx_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_vif *vif = info->control.vif;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++	struct ssv6200_tx_desc *tx_desc;
++	int ret;
++	unsigned long flags;
++	bool send_hci = false;
++	do {
++		if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
++			if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
++				sc->tx.seq_no += 0x10;
++			hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
++			hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
++		}
++		if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++			if (ssv6xxx_get_real_index(sc, skb) <
++			    SSV62XX_RATE_MCS_INDEX) {
++				info->flags &= (~IEEE80211_TX_CTL_AMPDU);
++				goto tx_mpdu;
++			}
++			if (ssv6200_ampdu_tx_handler(hw, skb)) {
++				break;
++			} else {
++				info->flags &= (~IEEE80211_TX_CTL_AMPDU);
++			}
++		}
++ tx_mpdu:
++		ssv6xxx_add_txinfo(sc, skb);
++		if (vif &&
++		    vif->type == NL80211_IFTYPE_AP &&
++		    (sc->bq4_dtim) &&
++		    info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
++			struct ssv_vif_priv_data *priv_vif =
++			    (struct ssv_vif_priv_data *)vif->drv_priv;
++			u8 buffered = 0;
++			spin_lock_irqsave(&sc->ps_state_lock, flags);
++			if (priv_vif->sta_asleep_mask) {
++				buffered =
++				    ssv6200_bcast_enqueue(sc, &sc->bcast_txq,
++							  skb);
++				if (1 == buffered) {
++					dev_dbg(sc->dev, "ssv6200_tx:ssv6200_bcast_start\n");
++					ssv6200_bcast_start(sc);
++				}
++			}
++			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++			if (buffered)
++				break;
++		}
++		if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
++			struct ssv_vif_priv_data *vif_priv =
++			    (struct ssv_vif_priv_data *)vif->drv_priv;
++			dev_dbg(sc->dev, "vif[%d] sc->bq4_dtim[%d]\n",
++				vif_priv->vif_idx, sc->bq4_dtim);
++		}
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		ret = HCI_SEND(sc->sh, skb, tx_desc->txq_idx);
++		send_hci = true;
++	} while (0);
++	if ((skb_queue_len(&sc->tx_skb_q) < LOW_TX_Q_LEN)
++	    ) {
++		if (sc->tx.flow_ctrl_status != 0) {
++			int ac;
++			for (ac = 0; ac < sc->hw->queues; ac++) {
++				if ((sc->tx.flow_ctrl_status & BIT(ac)) == 0)
++					ieee80211_wake_queue(sc->hw, ac);
++			}
++		} else {
++			ieee80211_wake_queues(sc->hw);
++		}
++	}
++}
++
++static void ssv6200_tx(struct ieee80211_hw *hw,
++		       struct ieee80211_tx_control *control,
++		       struct sk_buff *skb)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)hw->priv;
++	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++	skb_info->sta = control ? control->sta : NULL;
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++	skb_info->timestamp = ktime_get();
++#endif
++	skb_queue_tail(&sc->tx_skb_q, skb);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (sc->max_tx_skb_q_len < skb_queue_len(&sc->tx_skb_q))
++		sc->max_tx_skb_q_len = skb_queue_len(&sc->tx_skb_q);
++#endif
++	wake_up_interruptible(&sc->tx_wait_q);
++	do {
++		if (skb_queue_len(&sc->tx_skb_q) >= MAX_TX_Q_LEN)
++			ieee80211_stop_queues(sc->hw);
++	} while (0);
++}
++
++int ssv6xxx_tx_task(void *data)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)data;
++	u32 wait_period = SSV_AMPDU_timer_period / 2;
++	dev_info(sc->dev, "TX Task started\n");
++	while (!kthread_should_stop()) {
++		u32 before_timeout = (-1);
++		set_current_state(TASK_INTERRUPTIBLE);
++		before_timeout = wait_event_interruptible_timeout(sc->tx_wait_q,
++								  (skb_queue_len
++								   (&sc->
++								    tx_skb_q)
++								   ||
++								   kthread_should_stop
++								   ()
++								   || sc->
++								   tx_q_empty),
++								  msecs_to_jiffies
++								  (wait_period));
++		if (kthread_should_stop()) {
++			dev_dbg(sc->dev, "Quit TX task loop...\n");
++			break;
++		}
++		set_current_state(TASK_RUNNING);
++		do {
++			struct sk_buff *tx_skb = skb_dequeue(&sc->tx_skb_q);
++			if (tx_skb == NULL)
++				break;
++			_ssv6xxx_tx(sc->hw, tx_skb);
++		} while (1);
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++		{
++			struct ssv_hw_txq *hw_txq = NULL;
++			struct ieee80211_tx_info *tx_info = NULL;
++			struct sk_buff *skb = NULL;
++			int txqid;
++			unsigned int timeout;
++			u32 status;
++			for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++				hw_txq = &ssv_dbg_ctrl_hci->hw_txq[txqid];
++				skb = skb_peek(&hw_txq->qhead);
++				if (skb != NULL) {
++					tx_info = IEEE80211_SKB_CB(skb);
++					if (tx_info->
++					    flags & IEEE80211_TX_CTL_AMPDU)
++						timeout =
++						    cal_duration_of_ampdu(skb,
++									  SKB_DURATION_STAGE_IN_HWQ);
++					else
++						timeout =
++						    cal_duration_of_mpdu(skb);
++					if (timeout > SKB_DURATION_TIMEOUT_MS) {
++						HCI_IRQ_STATUS(ssv_dbg_ctrl_hci,
++							       &status);
++						dev_dbg(sc->dev, "hci int_mask: %08x\n",
++						       ssv_dbg_ctrl_hci->
++						       int_mask);
++						dev_dbg(sc->dev, "sdio status: %08x\n",
++						       status);
++						dev_dbg(sc->dev, "hwq%d len: %d\n", txqid,
++						       skb_queue_len(&hw_txq->
++								     qhead));
++					}
++				}
++			}
++		}
++#endif
++		if (sc->tx_q_empty || (before_timeout == 0)) {
++			u32 flused_ampdu = ssv6xxx_ampdu_flush(sc->hw);
++			sc->tx_q_empty = false;
++			if (flused_ampdu == 0 && before_timeout == 0) {
++				wait_period *= 2;
++				if (wait_period > 1000)
++					wait_period = 1000;
++			}
++		} else
++			wait_period = SSV_AMPDU_timer_period / 2;
++	}
++	return 0;
++}
++
++int ssv6xxx_rx_task(void *data)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)data;
++	unsigned long wait_period = msecs_to_jiffies(200);
++	unsigned long last_timeout_check_jiffies = jiffies;
++	unsigned long cur_jiffies;
++	dev_info(sc->dev, "RX Task started\n");
++	while (!kthread_should_stop()) {
++		u32 before_timeout = (-1);
++		set_current_state(TASK_INTERRUPTIBLE);
++		before_timeout = wait_event_interruptible_timeout(sc->rx_wait_q,
++								  (skb_queue_len
++								   (&sc->
++								    rx_skb_q)
++								   ||
++								   skb_queue_len
++								   (&sc->
++								    tx_done_q)
++								   ||
++								   kthread_should_stop
++								   ()),
++								  wait_period);
++		if (kthread_should_stop()) {
++			dev_dbg(sc->dev, "Quit RX task loop...\n");
++			break;
++		}
++		set_current_state(TASK_RUNNING);
++		cur_jiffies = jiffies;
++		if ((before_timeout == 0)
++		    || time_before((last_timeout_check_jiffies + wait_period),
++				   cur_jiffies)) {
++			ssv6xxx_ampdu_check_timeout(sc->hw);
++			last_timeout_check_jiffies = cur_jiffies;
++		}
++		if (skb_queue_len(&sc->rx_skb_q))
++			_process_rx_q(sc, &sc->rx_skb_q, NULL);
++		if (skb_queue_len(&sc->tx_done_q))
++			_process_tx_done(sc);
++	}
++	return 0;
++}
++
++struct ssv6xxx_iqk_cfg init_iqk_cfg = {
++	SSV6XXX_IQK_CFG_XTAL_26M,
++#ifdef CONFIG_SSV_DPD
++	SSV6XXX_IQK_CFG_PA_LI_MPB,
++#else
++	SSV6XXX_IQK_CFG_PA_DEF,
++#endif
++	0,
++	0,
++	26,
++	3,
++	0x75,
++	0x75,
++	0x80,
++	0x80,
++	SSV6XXX_IQK_CMD_INIT_CALI,
++	{SSV6XXX_IQK_TEMPERATURE
++	 + SSV6XXX_IQK_RXDC
++	 + SSV6XXX_IQK_RXRC
++	 + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ
++#ifdef CONFIG_SSV_DPD
++	 + SSV6XXX_IQK_PAPD
++#endif
++	 },
++};
++
++static int ssv6200_start(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_hw *sh = sc->sh;
++	struct ieee80211_channel *chan;
++    int ret;
++    
++	mutex_lock(&sc->mutex);
++    ret = ssv6xxx_init_mac(sc->sh);
++	if (ret != 0) {
++		dev_err(sc->dev, "Failed to initialize mac, ret=%d\n", ret);
++		ssv6xxx_deinit_mac(sc);
++		mutex_unlock(&sc->mutex);
++		return -1;
++	}
++#ifdef CONFIG_P2P_NOA
++	ssv6xxx_noa_reset(sc);
++#endif
++	HCI_START(sh);
++	ieee80211_wake_queues(hw);
++	ssv6200_ampdu_init(hw);
++	sc->watchdog_flag = WD_KICKED;
++	mutex_unlock(&sc->mutex);
++	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++#ifdef CONFIG_SSV_SMARTLINK
++	{
++		extern int ksmartlink_init(void);
++		(void)ksmartlink_init();
++	}
++#endif
++    ret = ssv6xxx_do_iq_calib(sc->sh, &init_iqk_cfg);
++    if (ret != 0) {
++        dev_err(sc->dev, "IQ Calibration failed, ret=%d\n", ret);
++        return ret;
++    }
++
++	dev_info(sc->dev, "Calibration successful\n");
++
++	SMAC_REG_WRITE(sc->sh, ADR_PHY_EN_1, 0x217f);
++	if ((sh->cfg.chip_identity == SSV6051Z)
++	    || (sc->sh->cfg.chip_identity == SSV6051P)) {
++		int i;
++		for (i = 0; i < sh->ch_cfg_size; i++) {
++			SMAC_REG_READ(sh, sh->p_ch_cfg[i].reg_addr,
++				      &sh->p_ch_cfg[i].ch1_12_value);
++		}
++	}
++	chan = hw->conf.chandef.chan;
++	sc->cur_channel = chan;
++	dev_dbg(sc->dev, "%s(): current channel: %d,sc->ps_status=%d\n", __FUNCTION__,
++	       sc->cur_channel->hw_value, sc->ps_status);
++	ssv6xxx_set_channel(sc, chan->hw_value);
++	ssv6xxx_rf_enable(sh);
++	return 0;
++}
++
++static void ssv6200_stop(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	u32 count = 0;
++	struct rssi_res_st *rssi_tmp0, *rssi_tmp1;
++	dev_dbg(sc->dev, "%s(): sc->ps_status=%d\n", __FUNCTION__,
++	       sc->ps_status);
++	mutex_lock(&sc->mutex);
++	list_for_each_entry_safe(rssi_tmp0, rssi_tmp1, &rssi_res.rssi_list,
++				 rssi_list) {
++		list_del(&rssi_tmp0->rssi_list);
++		kfree(rssi_tmp0);
++	}
++	ssv6200_ampdu_deinit(hw);
++	ssv6xxx_rf_disable(sc->sh);
++	HCI_STOP(sc->sh);
++#ifndef NO_USE_RXQ_LOCK
++	while (0) {
++#else
++	while (skb_queue_len(&sc->rx.rxq_head)) {
++#endif
++		dev_dbg(sc->dev, "sc->rx.rxq_count=%d\n", sc->rx.rxq_count);
++		count++;
++		if (count > 90000000) {
++			dev_err(sc->dev, "Could not empty RX queue during shutdown\n");
++			break;
++		}
++	}
++	HCI_TXQ_FLUSH(sc->sh, (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2 |
++			       TXQ_EDCA_3 | TXQ_MGMT));
++	if ((sc->ps_status == PWRSV_PREPARE) || (sc->ps_status == PWRSV_ENABLE)) {
++		ssv6xxx_enable_ps(sc);
++		ssv6xxx_rf_enable(sc->sh);
++	}
++	sc->watchdog_flag = WD_SLEEP;
++	mutex_unlock(&sc->mutex);
++	del_timer_sync(&sc->watchdog_timeout);
++#ifdef CONFIG_SSV_SMARTLINK
++	{
++		extern void ksmartlink_exit(void);
++		ksmartlink_exit();
++	}
++#endif
++	dev_dbg(sc->dev, "%s(): leave\n", __FUNCTION__);
++}
++
++void inline ssv62xxx_set_bssid(struct ssv_softc *sc, u8 * bssid)
++{
++	memcpy(sc->bssid, bssid, 6);
++	SMAC_REG_WRITE(sc->sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
++	SMAC_REG_WRITE(sc->sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
++}
++
++struct ssv_vif_priv_data *ssv6xxx_config_vif_res(struct ssv_softc *sc,
++						 struct ieee80211_vif *vif)
++{
++	int i;
++	struct ssv_vif_priv_data *priv_vif;
++	struct ssv_vif_info *vif_info;
++	lockdep_assert_held(&sc->mutex);
++	for (i = 0; i < SSV6200_MAX_VIF; i++) {
++		if (sc->vif_info[i].vif == NULL)
++			break;
++	}
++	BUG_ON(i >= SSV6200_MAX_VIF);
++	dev_dbg(sc->dev, "ssv6xxx_config_vif_res id[%d].\n", i);
++	priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
++	memset(priv_vif, 0, sizeof(struct ssv_vif_priv_data));
++	priv_vif->vif_idx = i;
++	memset(&sc->vif_info[i], 0, sizeof(sc->vif_info[0]));
++	sc->vif_info[i].vif = vif;
++	sc->vif_info[i].vif_priv = priv_vif;
++	INIT_LIST_HEAD(&priv_vif->sta_list);
++	priv_vif->pair_cipher = SSV_CIPHER_NONE;
++	priv_vif->group_cipher = SSV_CIPHER_NONE;
++	priv_vif->has_hw_decrypt = false;
++	priv_vif->has_hw_encrypt = false;
++	priv_vif->need_sw_encrypt = false;
++	priv_vif->need_sw_decrypt = false;
++	priv_vif->use_mac80211_decrypt = false;
++	priv_vif->is_security_valid = false;
++	priv_vif->force_sw_encrypt = (vif->type == NL80211_IFTYPE_AP);
++	vif_info = &sc->vif_info[priv_vif->vif_idx];
++	vif_info->if_type = vif->type;
++	vif_info->vif = vif;
++	return priv_vif;
++}
++
++static int ssv6200_add_interface(struct ieee80211_hw *hw,
++				 struct ieee80211_vif *vif)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	struct ssv_vif_priv_data *vif_priv = NULL;
++	dev_dbg(sc->dev, "[I] %s(): vif->type = %d, NL80211_IFTYPE_AP=%d\n", __FUNCTION__,
++	       vif->type, NL80211_IFTYPE_AP);
++	if ((sc->nvif >= SSV6200_MAX_VIF)
++	    || (((vif->type == NL80211_IFTYPE_AP)
++		 || (vif->p2p))
++		&& (sc->ap_vif != NULL))) {
++		dev_err(sc->dev, "Add interface of type %d (p2p: %d) failed.\n",
++			vif->type, vif->p2p);
++		return -EOPNOTSUPP;
++	}
++	mutex_lock(&sc->mutex);
++	vif_priv = ssv6xxx_config_vif_res(sc, vif);
++	if ((vif_priv->vif_idx == 0) && (vif->p2p == 0)
++	    && (vif->type == NL80211_IFTYPE_AP)) {
++		dev_dbg(sc->dev, "VIF[0] set bssid and config opmode to ap\n");
++		ssv62xxx_set_bssid(sc, sc->sh->cfg.maddr[0]);
++		SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_AP,
++				  OP_MODE_MSK);
++	}
++	if (vif->type == NL80211_IFTYPE_AP) {
++		BUG_ON(sc->ap_vif != NULL);
++		sc->ap_vif = vif;
++		if (!vif->p2p && (vif_priv->vif_idx == 0)) {
++			dev_dbg(sc->dev, "Normal AP mode. Config Q4 to DTIM Q.\n");
++			SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
++					  MTX_HALT_MNG_UNTIL_DTIM_MSK,
++					  MTX_HALT_MNG_UNTIL_DTIM_MSK);
++			sc->bq4_dtim = true;
++		}
++	}
++	sc->nvif++;
++	dev_dbg(sc->dev,
++		"VIF %02x:%02x:%02x:%02x:%02x:%02x of type %d is added.\n",
++		vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
++		vif->addr[4], vif->addr[5], vif->type);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_debugfs_add_interface(sc, vif);
++#endif
++	mutex_unlock(&sc->mutex);
++	return ret;
++}
++
++static void ssv6200_remove_interface(struct ieee80211_hw *hw,
++				     struct ieee80211_vif *vif)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	dev_err(sc->dev,
++		"Removing interface %02x:%02x:%02x:%02x:%02x:%02x. PS=%d\n",
++		vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
++		vif->addr[4], vif->addr[5], sc->ps_status);
++	mutex_lock(&sc->mutex);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_debugfs_remove_interface(sc, vif);
++#endif
++	if (vif->type == NL80211_IFTYPE_AP) {
++		if (sc->bq4_dtim) {
++			sc->bq4_dtim = false;
++			ssv6200_release_bcast_frame_res(sc, vif);
++			SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
++					  0, MTX_HALT_MNG_UNTIL_DTIM_MSK);
++			dev_dbg(sc->dev, "Config Q4 to normal Q \n");
++		}
++		ssv6xxx_beacon_release(sc);
++		sc->ap_vif = NULL;
++	}
++	memset(&sc->vif_info[vif_priv->vif_idx], 0,
++	       sizeof(struct ssv_vif_info));
++	sc->nvif--;
++	mutex_unlock(&sc->mutex);
++}
++
++static int ssv6200_change_interface(struct ieee80211_hw *dev,
++				    struct ieee80211_vif *vif,
++				    enum nl80211_iftype new_type, bool p2p)
++{
++    struct ssv_softc *sc = dev->priv;
++	int ret = 0;
++    
++	dev_dbg(sc->dev, "change_interface new: %d (%d), old: %d (%d)\n", new_type,
++	       p2p, vif->type, vif->p2p);
++
++	if (new_type != vif->type || vif->p2p != p2p) {
++		ssv6200_remove_interface(dev, vif);
++		vif->type = new_type;
++		vif->p2p = p2p;
++		ret = ssv6200_add_interface(dev, vif);
++	}
++
++	return ret;
++}
++
++void ssv6xxx_ps_callback_func(unsigned long data)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)data;
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int retry_cnt = 20;
++#ifdef SSV_WAKEUP_HOST
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++	SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
++		       (sc->mac_deci_tbl[6] | 1));
++#else
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
++#endif
++	skb = ssv_skb_alloc(sizeof(struct cfg_host_cmd));
++	skb->data_len = sizeof(struct cfg_host_cmd);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->RSVD0 = 0;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
++	host_cmd->len = skb->data_len;
++#ifdef SSV_WAKEUP_HOST
++	host_cmd->dummy = sc->ps_aid;
++#else
++	host_cmd->dummy = 0;
++#endif
++	sc->ps_aid = 0;
++	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
++		dev_warn(sc->dev, "PS cmd retry=%d!!\n", retry_cnt);
++		retry_cnt--;
++	}
++	ssv_skb_free(skb);
++	dev_dbg(sc->dev, "SSV6XXX_HOST_CMD_PS,ps_aid = %d,len=%d,tabl=0x%x\n",
++	       host_cmd->dummy, skb->len, (sc->mac_deci_tbl[6] | 1));
++}
++
++void ssv6xxx_enable_ps(struct ssv_softc *sc)
++{
++	sc->ps_status = PWRSV_ENABLE;
++}
++
++void ssv6xxx_disable_ps(struct ssv_softc *sc)
++{
++	sc->ps_status = PWRSV_DISABLE;
++	dev_info(sc->dev, "Power saving disabled\n");
++}
++
++int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int ret = 0;
++	dev_dbg(sh->sc->dev, "ssv6xxx_watchdog_controller %d\n", flag);
++	skb = ssv_skb_alloc(HOST_CMD_HDR_LEN);
++	if (skb == NULL) {
++		dev_warn(sh->sc->dev, "init ssv6xxx_watchdog_controller fail!!!\n");
++		return (-1);
++	}
++	skb->data_len = HOST_CMD_HDR_LEN;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) flag;
++	host_cmd->len = skb->data_len;
++	sh->hci.hci_ops->hci_send_cmd(skb);
++	ssv_skb_free(skb);
++	return ret;
++}
++
++static int ssv6200_config(struct ieee80211_hw *hw, u32 changed)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	mutex_lock(&sc->mutex);
++	if (changed & IEEE80211_CONF_CHANGE_PS) {
++		struct ieee80211_conf *conf = &hw->conf;
++		if (conf->flags & IEEE80211_CONF_PS) {
++			dev_dbg(sc->dev, "Enable IEEE80211_CONF_PS ps_aid=%d\n",
++			       sc->ps_aid);
++		} else {
++			dev_dbg(sc->dev, "Disable IEEE80211_CONF_PS ps_aid=%d\n",
++			       sc->ps_aid);
++		}
++	}
++	if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
++		struct ieee80211_channel *chan;
++		chan = hw->conf.chandef.chan;
++#ifdef CONFIG_P2P_NOA
++		if (sc->p2p_noa.active_noa_vif) {
++			dev_dbg(sc->dev, "NOA operating-active vif[%02x] skip scan\n",
++			       sc->p2p_noa.active_noa_vif);
++			goto out;
++		}
++#endif
++		if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) {
++			if ((sc->ap_vif == NULL)
++			    ||
++			    list_empty(&
++				       ((struct ssv_vif_priv_data *)sc->ap_vif->
++					drv_priv)->sta_list)) {
++				HCI_PAUSE(sc->sh,
++					  (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
++					   | TXQ_EDCA_3 | TXQ_MGMT));
++				sc->sc_flags |= SC_OP_OFFCHAN;
++				ssv6xxx_set_channel(sc, chan->hw_value);
++				sc->hw_chan = chan->hw_value;
++				HCI_RESUME(sc->sh, TXQ_MGMT);
++			} else {
++				dev_dbg(sc->dev,
++					"Off-channel to %d is ignored when AP mode enabled.\n",
++					chan->hw_value);
++			}
++		} else {
++			if ((sc->cur_channel == NULL)
++			    || (sc->sc_flags & SC_OP_OFFCHAN)
++			    || (sc->hw_chan != chan->hw_value)) {
++				HCI_PAUSE(sc->sh,
++					  (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
++					   | TXQ_EDCA_3 | TXQ_MGMT));
++				ssv6xxx_set_channel(sc, chan->hw_value);
++				sc->cur_channel = chan;
++				HCI_RESUME(sc->sh,
++					   (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
++					    | TXQ_EDCA_3 | TXQ_MGMT));
++				sc->sc_flags &= ~SC_OP_OFFCHAN;
++			} else {
++				dev_dbg(sc->dev,
++					"Change to the same channel %d\n",
++					chan->hw_value);
++			}
++		}
++	}
++#ifdef CONFIG_P2P_NOA
++ out:
++#endif
++	mutex_unlock(&sc->mutex);
++	return ret;
++}
++
++#define SUPPORTED_FILTERS \
++    (FIF_ALLMULTI | \
++    FIF_CONTROL | \
++    FIF_PSPOLL | \
++    FIF_OTHER_BSS | \
++    FIF_BCN_PRBRESP_PROMISC | \
++    FIF_PROBE_REQ | \
++    FIF_FCSFAIL)
++static void ssv6200_config_filter(struct ieee80211_hw *hw,
++				  unsigned int changed_flags,
++				  unsigned int *total_flags, u64 multicast)
++{
++	changed_flags &= SUPPORTED_FILTERS;
++	*total_flags &= SUPPORTED_FILTERS;
++}
++
++static void ssv6200_bss_info_changed(struct ieee80211_hw *hw,
++				     struct ieee80211_vif *vif,
++				     struct ieee80211_bss_conf *info,
++				     u64 changed)
++{
++	struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_softc *sc = hw->priv;
++#ifdef CONFIG_P2P_NOA
++	u8 null_address[6] = { 0 };
++#endif
++	mutex_lock(&sc->mutex);
++	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
++		dev_dbg(sc->dev, "BSS Changed use_short_preamble[%d]\n",
++		       info->use_short_preamble);
++		if (info->use_short_preamble)
++			sc->sc_flags |= SC_OP_SHORT_PREAMBLE;
++		else
++			sc->sc_flags &= ~SC_OP_SHORT_PREAMBLE;
++	}
++	if (!priv_vif->vif_idx) {
++		if (changed & BSS_CHANGED_BSSID) {
++#ifdef CONFIG_P2P_NOA
++			struct ssv_vif_priv_data *vif_priv;
++			vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
++#endif
++			ssv62xxx_set_bssid(sc, (u8 *) info->bssid);
++			dev_dbg(sc->dev, "BSS_CHANGED_BSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
++			     info->bssid[0], info->bssid[1], info->bssid[2],
++			     info->bssid[3], info->bssid[4], info->bssid[5]);
++#ifdef CONFIG_P2P_NOA
++			if (memcmp(info->bssid, null_address, 6))
++				ssv6xxx_noa_hdl_bss_change(sc,
++							   MONITOR_NOA_CONF_ADD,
++							   vif_priv->vif_idx);
++			else
++				ssv6xxx_noa_hdl_bss_change(sc,
++							   MONITOR_NOA_CONF_REMOVE,
++							   vif_priv->vif_idx);
++#endif
++		}
++		if (changed & BSS_CHANGED_ERP_SLOT) {
++			u32 regval = 0;
++			dev_dbg(sc->dev, "BSS_CHANGED_ERP_SLOT: use_short_slot[%d]\n",
++			       info->use_short_slot);
++			if (info->use_short_slot) {
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
++				regval = regval & MTX_DUR_SLOT_I_MSK;
++				regval |= 9 << MTX_DUR_SLOT_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
++					      &regval);
++				regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
++				regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
++				regval = regval & MTX_DUR_SLOT_G_I_MSK;
++				regval |= 9 << MTX_DUR_SLOT_G_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
++					       regval);
++			} else {
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
++				regval = regval & MTX_DUR_SLOT_I_MSK;
++				regval |= 20 << MTX_DUR_SLOT_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
++					      &regval);
++				regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
++				regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
++				regval = regval & MTX_DUR_SLOT_G_I_MSK;
++				regval |= 20 << MTX_DUR_SLOT_G_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
++					       regval);
++			}
++		}
++	}
++	if (changed & BSS_CHANGED_HT) {
++		dev_dbg(sc->dev, "BSS_CHANGED_HT: Untreated!!\n");
++	}
++	if (changed & BSS_CHANGED_BASIC_RATES) {
++		dev_dbg(sc->dev, "ssv6xxx_rc_update_basic_rate!!\n");
++		ssv6xxx_rc_update_basic_rate(sc, info->basic_rates);
++	}
++	if (vif->type == NL80211_IFTYPE_STATION) {
++		dev_dbg(sc->dev, "NL80211_IFTYPE_STATION!!\n");
++		if ((changed & BSS_CHANGED_ASSOC) && (vif->p2p == 0)) {
++			sc->isAssoc = vif->cfg.assoc;
++			if (!sc->isAssoc) {
++				sc->channel_center_freq = 0;
++				sc->ps_aid = 0;
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
++#endif
++				SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL,
++					       0x0);
++			} else {
++				struct ieee80211_channel *curchan;
++				curchan = hw->conf.chandef.chan;
++				sc->channel_center_freq = curchan->center_freq;
++				dev_dbg(sc->dev, "info->aid = %d\n", vif->cfg.aid);
++				sc->ps_aid = vif->cfg.aid;
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
++#endif
++			}
++		}
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++		else if ((changed & BSS_CHANGED_ASSOC) && vif->p2p == 1) {
++			if (info->assoc)
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
++			else if (sc->ps_aid != 0)
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
++		}
++#endif
++	}
++	if (vif->type == NL80211_IFTYPE_AP) {
++		if (changed & (BSS_CHANGED_BEACON
++			       | BSS_CHANGED_SSID
++			       | BSS_CHANGED_BSSID | BSS_CHANGED_BASIC_RATES)) {
++#ifdef BROADCAST_DEBUG
++			dev_dbg(sc->dev, "[A] ssv6200_bss_info_changed:beacon changed\n");
++#endif
++			queue_work(sc->config_wq, &sc->set_tim_work);
++		}
++		if (changed & BSS_CHANGED_BEACON_INT) {
++			dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_INT beacon_interval(%d)\n",
++			     info->beacon_int);
++			if (sc->beacon_interval != info->beacon_int) {
++				sc->beacon_interval = info->beacon_int;
++				ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
++							sc->beacon_dtim_cnt);
++			}
++		}
++		if (changed & BSS_CHANGED_BEACON_ENABLED) {
++#ifdef BEACON_DEBUG
++			dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_ENABLED (0x%x)\n",
++			       info->enable_beacon);
++#endif
++			if (0 != ssv6xxx_beacon_enable(sc, info->enable_beacon)) {
++				dev_err(sc->dev, "Beacon enable %d error.\n",
++					info->enable_beacon);
++			}
++		}
++	}
++	mutex_unlock(&sc->mutex);
++	dev_dbg(sc->dev, "[I] %s(): leave\n", __FUNCTION__);
++}
++
++static int ssv6200_sta_add(struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, struct ieee80211_sta *sta)
++{
++	struct ssv_sta_priv_data *sta_priv_dat = NULL;
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info;
++	u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
++	int s, i;
++	u32 reg_wsid_tid0[] = { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
++	u32 reg_wsid_tid7[] = { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
++	unsigned long flags;
++	int ret = 0;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	int fw_sec_caps = SSV6XXX_WSID_SEC_NONE;
++	bool tdls_use_sw_cipher = false, tdls_link = false;
++	dev_dbg(sc->dev, "[I] %s(): vif[%d] ", __FUNCTION__, vif_priv->vif_idx);
++	if (sc->force_triger_reset == true) {
++		vif_priv->sta_asleep_mask = 0;
++		do {
++			spin_lock_irqsave(&sc->ps_state_lock, flags);
++			for (s = 0; s < SSV_NUM_STA; s++, sta_info++) {
++				sta_info = &sc->sta_info[s];
++				if ((sta_info->s_flags & STA_FLAG_VALID)) {
++					if (sta_info->sta == sta) {
++						dev_dbg
++						    (sc->dev, "search stat %02x:%02x:%02x:%02x:%02x:%02x to  wsid=%d\n",
++						     sta->addr[0], sta->addr[1],
++						     sta->addr[2], sta->addr[3],
++						     sta->addr[4], sta->addr[5],
++						     sta_info->hw_wsid);
++						spin_unlock_irqrestore(&sc->
++								       ps_state_lock,
++								       flags);
++						return ret;
++					}
++				}
++			}
++			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++			if (s >= SSV_NUM_STA) {
++				break;
++			}
++		} while (0);
++	}
++	do {
++		spin_lock_irqsave(&sc->ps_state_lock, flags);
++		if (!list_empty(&vif_priv->sta_list)
++		    && vif->type == NL80211_IFTYPE_STATION) {
++			tdls_link = true;
++		}
++		if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_NONE)
++		    && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
++		    && (sc->sh->cfg.use_wpa2_only == false)) {
++			tdls_use_sw_cipher = true;
++		}
++		if (((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false))
++		    || sc->sh->cfg.use_wpa2_only)
++			s = 0;
++		else
++			s = 2;
++		for (; s < SSV_NUM_STA; s++) {
++			sta_info = &sc->sta_info[s];
++			if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
++				sta_info->aid = sta->aid;
++				sta_info->sta = sta;
++				sta_info->vif = vif;
++				sta_info->s_flags = STA_FLAG_VALID;
++				sta_priv_dat =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++				sta_priv_dat->sta_idx = s;
++				sta_priv_dat->sta_info = sta_info;
++				sta_priv_dat->has_hw_encrypt = false;
++				sta_priv_dat->has_hw_decrypt = false;
++				sta_priv_dat->need_sw_decrypt = false;
++				sta_priv_dat->need_sw_encrypt = false;
++				sta_priv_dat->use_mac80211_decrypt = false;
++				if ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
++				    || (vif_priv->pair_cipher ==
++					SSV_CIPHER_WEP104)) {
++					sta_priv_dat->has_hw_encrypt =
++					    vif_priv->has_hw_encrypt;
++					sta_priv_dat->has_hw_decrypt =
++					    vif_priv->has_hw_decrypt;
++					sta_priv_dat->need_sw_encrypt =
++					    vif_priv->need_sw_encrypt;
++					sta_priv_dat->need_sw_decrypt =
++					    vif_priv->need_sw_decrypt;
++				}
++				list_add_tail(&sta_priv_dat->list,
++					      &vif_priv->sta_list);
++				break;
++			}
++		}
++		spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++		if (s >= SSV_NUM_STA) {
++			dev_err(sc->dev,
++				"Number of STA exceeds driver limitation %d\n.",
++				SSV_NUM_STA);
++			ret = -1;
++			break;
++		}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		ssv6xxx_debugfs_add_sta(sc, sta_info);
++#endif
++		sta_info->hw_wsid = -1;
++		if (sta_priv_dat->sta_idx < SSV_NUM_HW_STA) {
++			SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 4,
++				       *((u32 *) & sta->addr[0]));
++			SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 8,
++				       *((u32 *) & sta->addr[4]));
++			SMAC_REG_WRITE(sc->sh, reg_wsid[s], 1);
++			for (i = reg_wsid_tid0[s]; i <= reg_wsid_tid7[s];
++			     i += 4)
++				SMAC_REG_WRITE(sc->sh, i, 0);
++			ssv6xxx_rc_hw_reset(sc, sta_priv_dat->rc_idx, s);
++			sta_info->hw_wsid = sta_priv_dat->sta_idx;
++		} else if ((vif_priv->vif_idx == 0)
++			   || sc->sh->cfg.use_wpa2_only) {
++			sta_info->hw_wsid = sta_priv_dat->sta_idx;
++		}
++		if ((sta_priv_dat->has_hw_encrypt
++		     || sta_priv_dat->has_hw_decrypt)
++		    && ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
++			|| (vif_priv->pair_cipher == SSV_CIPHER_WEP104))) {
++			struct ssv_vif_info *vif_info =
++			    &sc->vif_info[vif_priv->vif_idx];
++			struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
++			_set_wep_hw_crypto_pair_key(sc, vif_info, sta_info,
++						    (void *)sramKey);
++			if (sramKey->sta_key[0].pair_key_idx != 0) {
++				_set_wep_hw_crypto_group_key(sc, vif_info,
++							     sta_info,
++							     (void *)sramKey);
++			}
++		}
++		ssv6200_ampdu_tx_add_sta(hw, sta);
++		if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
++			if (sta_priv_dat->has_hw_decrypt)
++				fw_sec_caps = SSV6XXX_WSID_SEC_PAIRWISE;
++			if (vif_priv->has_hw_decrypt)
++				fw_sec_caps |= SSV6XXX_WSID_SEC_GROUP;
++			hw_update_watch_wsid(sc, sta, sta_info,
++					     sta_priv_dat->sta_idx, fw_sec_caps,
++					     SSV6XXX_WSID_OPS_ADD);
++		} else if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)) {
++			hw_update_watch_wsid(sc, sta, sta_info,
++					     sta_priv_dat->sta_idx,
++					     SSV6XXX_WSID_SEC_SW,
++					     SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
++			hw_update_watch_wsid(sc, sta, sta_info,
++					     sta_priv_dat->sta_idx,
++					     SSV6XXX_WSID_SEC_SW,
++					     SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
++		}
++		dev_dbg
++		    (sc->dev, "Add %02x:%02x:%02x:%02x:%02x:%02x to VIF %d sw_idx=%d, wsid=%d\n",
++		     sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		     sta->addr[4], sta->addr[5], vif_priv->vif_idx,
++		     sta_priv_dat->sta_idx, sta_info->hw_wsid);
++	} while (0);
++	return ret;
++}
++
++void ssv6200_rx_flow_check(struct ssv_sta_priv_data *sta_priv_dat,
++			   struct ssv_softc *sc)
++{
++	if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)
++	    && (sta_priv_dat->need_sw_decrypt)) {
++		int other_hw_wsid = (sta_priv_dat->sta_idx + 1) & 1;
++		struct ssv_sta_info *sta_info = &sc->sta_info[other_hw_wsid];
++		struct ieee80211_sta *sta = sta_info->sta;
++		struct ssv_sta_priv_data *sta_priv =
++		    (struct ssv_sta_priv_data *)sta->drv_priv;
++		mutex_lock(&sc->mutex);
++		if ((sta_info->s_flags == 0)
++		    || ((sta_info->s_flags && STA_FLAG_VALID)
++			&& (sta_priv->has_hw_decrypt))) {
++			SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++				       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
++				       (M_ENG_HWHCI << 8));
++			dev_dbg(sc->dev, "redirect Rx flow for sta %d disconnect\n",
++			       sta_priv_dat->sta_idx);
++		}
++		mutex_unlock(&sc->mutex);
++	}
++}
++
++static int ssv6200_sta_remove(struct ieee80211_hw *hw,
++			      struct ieee80211_vif *vif,
++			      struct ieee80211_sta *sta)
++{
++	u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
++	struct ssv_sta_priv_data *sta_priv_dat =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info = sta_priv_dat->sta_info;
++	unsigned long flags;
++	u32 bit;
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	u8 hw_wsid = -1;
++	BUG_ON(sta_priv_dat->sta_idx >= SSV_NUM_STA);
++	dev_notice(sc->dev,
++		   "Removing STA %d (%02X:%02X:%02X:%02X:%02X:%02X) from VIF %d\n.",
++		   sta_priv_dat->sta_idx, sta->addr[0], sta->addr[1],
++		   sta->addr[2], sta->addr[3], sta->addr[4], sta->addr[5],
++		   priv_vif->vif_idx);
++	ssv6200_rx_flow_check(sta_priv_dat, sc);
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	bit = BIT(sta_priv_dat->sta_idx);
++	priv_vif->sta_asleep_mask &= ~bit;
++	if (sta_info->hw_wsid != -1) {
++		hw_wsid = sta_info->hw_wsid;
++	}
++	if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
++		spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++		hw_update_watch_wsid(sc, sta, sta_info, sta_info->hw_wsid, 0,
++				     SSV6XXX_WSID_OPS_DEL);
++		spin_lock_irqsave(&sc->ps_state_lock, flags);
++	}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	{
++		ssv6xxx_debugfs_remove_sta(sc, sta_info);
++	}
++#endif
++	memset(sta_info, 0, sizeof(*sta_info));
++	sta_priv_dat->sta_idx = -1;
++	list_del(&sta_priv_dat->list);
++	if (list_empty(&priv_vif->sta_list)
++	    && vif->type == NL80211_IFTYPE_STATION) {
++		priv_vif->pair_cipher = 0;
++		priv_vif->group_cipher = 0;
++	}
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++	if ((hw_wsid != -1) && (hw_wsid < SSV_NUM_HW_STA))
++		SMAC_REG_WRITE(sc->sh, reg_wsid[hw_wsid], 0x00);
++	return 0;
++}
++
++static void ssv6200_sta_notify(struct ieee80211_hw *hw,
++			       struct ieee80211_vif *vif,
++			       enum sta_notify_cmd cmd,
++			       struct ieee80211_sta *sta)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_sta_priv_data *sta_priv_dat =
++	    sta != NULL ? (struct ssv_sta_priv_data *)sta->drv_priv : NULL;
++	struct ssv_sta_info *sta_info;
++	u32 bit, prev;
++	unsigned long flags;
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	if (sta_priv_dat != NULL) {
++		bit = BIT(sta_priv_dat->sta_idx);
++		prev = priv_vif->sta_asleep_mask & bit;
++		sta_info = sta_priv_dat->sta_info;
++		switch (cmd) {
++		case STA_NOTIFY_SLEEP:
++			if (!prev) {
++				sta_info->sleeping = true;
++				if ((vif->type == NL80211_IFTYPE_AP)
++				    && sc->bq4_dtim
++				    && !priv_vif->sta_asleep_mask
++				    && ssv6200_bcast_queue_len(&sc->
++							       bcast_txq)) {
++					dev_dbg(sc->dev, "%s(): ssv6200_bcast_start\n", __FUNCTION__);
++					ssv6200_bcast_start(sc);
++				}
++				priv_vif->sta_asleep_mask |= bit;
++			}
++			break;
++		case STA_NOTIFY_AWAKE:
++			if (prev) {
++				sta_info->sleeping = false;
++				priv_vif->sta_asleep_mask &= ~bit;
++			}
++			break;
++		default:
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++}
++
++static u64 ssv6200_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
++{
++	return jiffies * 1000 * 1000 / HZ;
++}
++
++static u64 ssv6200_get_systime_us(void)
++{
++#if LINUX_VERSION_CODE > KERNEL_VERSION(4,19,0)
++	struct timespec64 ts;
++	ktime_get_boottime_ts64(&ts);
++#else
++	struct timespec ts;
++	get_monotonic_boottime(&ts);
++#endif
++	return ((u64) ts.tv_sec * 1000000) + ts.tv_nsec / 1000;
++}
++
++static u32 pre_11b_cca_control;
++static u32 pre_11b_cca_1;
++static void ssv6200_sw_scan_start(struct ieee80211_hw *hw,
++				  struct ieee80211_vif *vif,
++				  const u8 * mac_addr)
++{
++	((struct ssv_softc *)(hw->priv))->bScanning = true;
++	SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh,
++		      ADR_RX_11B_CCA_CONTROL, &pre_11b_cca_control);
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
++		       ADR_RX_11B_CCA_CONTROL, 0x0);
++	SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
++		      &pre_11b_cca_1);
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
++		       RX_11B_CCA_IN_SCAN);
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_MRX_FLT_EN3,
++		       0x0400);
++#endif
++}
++
++static void ssv6200_sw_scan_complete(struct ieee80211_hw *hw,
++				     struct ieee80211_vif *vif)
++{
++
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++	bool is_p2p_assoc;
++#endif
++	((struct ssv_softc *)(hw->priv))->bScanning = false;
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
++		       ADR_RX_11B_CCA_CONTROL, pre_11b_cca_control);
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
++		       pre_11b_cca_1);
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++	is_p2p_assoc =
++	    ((struct ssv_softc *)(hw->priv))->vif_info[1].vif->bss_conf.assoc;
++	if (((struct ssv_softc *)(hw->priv))->ps_aid != 0 && (!is_p2p_assoc))
++		SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
++			       ADR_MRX_FLT_EN3, 0x1000);
++#endif
++}
++
++static int ssv6200_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
++			   bool set)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info = sta
++	    ? ((struct ssv_sta_priv_data *)sta->drv_priv)->sta_info : NULL;
++	if (sta_info && (sta_info->tim_set ^ set)) {
++        dev_dbg(sc->dev, "[I] [A] ssvcabrio_set_tim");
++		sta_info->tim_set = set;
++		queue_work(sc->config_wq, &sc->set_tim_work);
++	}
++	return 0;
++}
++
++static int ssv6200_conf_tx(struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, u32 link_id, u16 queue,
++			   const struct ieee80211_tx_queue_params *params)
++{
++	struct ssv_softc *sc = hw->priv;
++	u32 cw;
++	u8 hw_txqid = sc->tx.hw_txqid[queue];
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	dev_dbg
++	    (sc->dev, "[I] sv6200_conf_tx vif[%d] qos[%d] queue[%d] aifsn[%d] cwmin[%d] cwmax[%d] txop[%d] \n",
++	     priv_vif->vif_idx, vif->bss_conf.qos, queue, params->aifs,
++	     params->cw_min, params->cw_max, params->txop);
++	if (queue > NL80211_TXQ_Q_BK)
++		return 1;
++	if (priv_vif->vif_idx != 0) {
++		dev_warn(sc->dev,
++			 "WMM setting applicable to primary interface only.\n");
++		return 1;
++	}
++	mutex_lock(&sc->mutex);
++	SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET,
++			  (vif->bss_conf.qos << QOS_EN_SFT), QOS_EN_MSK);
++	cw = (params->aifs - 1) & 0xf;
++	cw |= ((ilog2(params->cw_min + 1)) & 0xf) << TXQ1_MTX_Q_ECWMIN_SFT;
++	cw |= ((ilog2(params->cw_max + 1)) & 0xf) << TXQ1_MTX_Q_ECWMAX_SFT;
++	cw |= ((params->txop) & 0xff) << TXQ1_MTX_Q_TXOP_LIMIT_SFT;
++	SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_AIFSN + 0x100 * hw_txqid, cw);
++	mutex_unlock(&sc->mutex);
++	return 0;
++}
++
++static int ssv6200_ampdu_action(struct ieee80211_hw *hw,
++				struct ieee80211_vif *vif,
++				struct ieee80211_ampdu_params *params)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	struct ieee80211_sta *sta = params->sta;
++	enum ieee80211_ampdu_mlme_action action = params->action;
++	u16 tid = params->tid;
++	u16 *ssn = &(params->ssn);
++	u8 buf_size = params->buf_size;
++	if (sta == NULL)
++		return ret;
++#if (!Enable_AMPDU_Rx)
++	if (action == IEEE80211_AMPDU_RX_START
++	    || action == IEEE80211_AMPDU_RX_STOP) {
++		ampdu_db_log("Disable AMPDU_RX for test(1).\n");
++		return -EOPNOTSUPP;
++	}
++#endif
++#if (!Enable_AMPDU_Tx)
++	if (action == IEEE80211_AMPDU_TX_START
++	    || action == IEEE80211_AMPDU_TX_STOP
++	    || action == IEEE80211_AMPDU_TX_OPERATIONAL) {
++		ampdu_db_log("Disable AMPDU_TX for test(1).\n");
++		return -EOPNOTSUPP;
++	}
++#endif
++	if ((action == IEEE80211_AMPDU_RX_START
++	     || action == IEEE80211_AMPDU_RX_STOP)
++	    && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX))) {
++		ampdu_db_log("Disable AMPDU_RX(2).\n");
++		return -EOPNOTSUPP;
++	}
++	if ((action == IEEE80211_AMPDU_TX_START
++	     || action == IEEE80211_AMPDU_TX_STOP_CONT
++	     || action == IEEE80211_AMPDU_TX_STOP_FLUSH
++	     || action == IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
++	     || action == IEEE80211_AMPDU_TX_OPERATIONAL)
++	    && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
++		ampdu_db_log("Disable AMPDU_TX(2).\n");
++		return -EOPNOTSUPP;
++	}
++	switch (action) {
++	case IEEE80211_AMPDU_RX_START:
++#ifdef WIFI_CERTIFIED
++		if (sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS) {
++			ieee80211_stop_rx_ba_session(vif,
++						     (1 << (sc->ba_tid)),
++						     sc->ba_ra_addr);
++			sc->rx_ba_session_count--;
++		}
++#else
++		if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
++		    && (sc->rx_ba_sta != sta)) {
++			ret = -EBUSY;
++			break;
++		} else
++		    if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
++			&& (sc->rx_ba_sta == sta)) {
++			ieee80211_stop_rx_ba_session(vif, (1 << (sc->ba_tid)),
++						     sc->ba_ra_addr);
++			sc->rx_ba_session_count--;
++		}
++#endif
++		dev_dbg(sc->dev, "IEEE80211_AMPDU_RX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		sc->rx_ba_session_count++;
++		sc->rx_ba_sta = sta;
++		sc->ba_tid = tid;
++		sc->ba_ssn = *ssn;
++		memcpy(sc->ba_ra_addr, sta->addr, ETH_ALEN);
++		queue_work(sc->config_wq, &sc->set_ampdu_rx_add_work);
++		break;
++	case IEEE80211_AMPDU_RX_STOP:
++		sc->rx_ba_session_count--;
++		if (sc->rx_ba_session_count == 0)
++			sc->rx_ba_sta = NULL;
++		queue_work(sc->config_wq, &sc->set_ampdu_rx_del_work);
++		break;
++	case IEEE80211_AMPDU_TX_START:
++		dev_dbg(sc->dev, "AMPDU_TX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		ssv6200_ampdu_tx_start(tid, sta, hw, ssn);
++		ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
++		break;
++	case IEEE80211_AMPDU_TX_STOP_CONT:
++	case IEEE80211_AMPDU_TX_STOP_FLUSH:
++	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
++		dev_dbg(sc->dev, "AMPDU_TX_STOP %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		ssv6200_ampdu_tx_stop(tid, sta, hw);
++		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
++		break;
++	case IEEE80211_AMPDU_TX_OPERATIONAL:
++		dev_dbg(sc->dev, "AMPDU_TX_OPERATIONAL %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		ssv6200_ampdu_tx_operation(tid, sta, hw, buf_size);
++		break;
++	default:
++		ret = -EOPNOTSUPP;
++		break;
++	}
++	return ret;
++}
++
++#ifdef CONFIG_PM
++int ssv6xxx_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
++{
++	return 0;
++}
++
++int ssv6xxx_resume(struct ieee80211_hw *hw)
++{
++	return 0;
++}
++#endif
++struct ieee80211_ops ssv6200_ops = {
++	.tx = ssv6200_tx,
++	.start = ssv6200_start,
++	.stop = ssv6200_stop,
++	.add_interface = ssv6200_add_interface,
++	.remove_interface = ssv6200_remove_interface,
++	.change_interface = ssv6200_change_interface,
++	.config = ssv6200_config,
++	.configure_filter = ssv6200_config_filter,
++	.bss_info_changed = ssv6200_bss_info_changed,
++	.sta_add = ssv6200_sta_add,
++	.sta_remove = ssv6200_sta_remove,
++	.sta_notify = ssv6200_sta_notify,
++	.set_key = ssv6200_set_key,
++	.sw_scan_start = ssv6200_sw_scan_start,
++	.sw_scan_complete = ssv6200_sw_scan_complete,
++	.get_tsf = ssv6200_get_tsf,
++	.set_tim = ssv6200_set_tim,
++	.conf_tx = ssv6200_conf_tx,
++	.ampdu_action = ssv6200_ampdu_action,
++	.wake_tx_queue = ieee80211_handle_wake_tx_queue,
++#ifdef CONFIG_PM
++	.suspend = ssv6xxx_suspend,
++	.resume = ssv6xxx_resume,
++#endif
++};
++
++int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug)
++{
++	struct ssv_softc *sc = dev;
++	int ac;
++	BUG_ON(hw_txqid > 4);
++	if (hw_txqid == 4)
++		return 0;
++	ac = sc->tx.ac_txqid[hw_txqid];
++	if (fc_en == false) {
++		if (sc->tx.flow_ctrl_status & (1 << ac)) {
++			ieee80211_wake_queue(sc->hw, ac);
++			sc->tx.flow_ctrl_status &= ~(1 << ac);
++		} else {
++		}
++	} else {
++		if ((sc->tx.flow_ctrl_status & (1 << ac)) == 0) {
++			ieee80211_stop_queue(sc->hw, ac);
++			sc->tx.flow_ctrl_status |= (1 << ac);
++		} else {
++		}
++	}
++	return 0;
++}
++
++void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *cb_data)
++{
++	struct ssv_softc *sc = cb_data;
++	BUG_ON(sc == NULL);
++	sc->tx_q_empty = true;
++	smp_mb();
++	wake_up_interruptible(&sc->tx_wait_q);
++}
++
++struct ssv6xxx_b_cca_control {
++	u32 down_level;
++	u32 upper_level;
++	u32 adjust_cca_control;
++	u32 adjust_cca_1;
++};
++struct ssv6xxx_b_cca_control adjust_cci[] = {
++	{0, 43, 0x00162000, 0x20380050},
++	{40, 48, 0x00161000, 0x20380050},
++	{45, 53, 0x00160800, 0x20380050},
++	{50, 63, 0x00160400, 0x20380050},
++	{60, 68, 0x00160200, 0x20380050},
++	{65, 73, 0x00160100, 0x20380050},
++	{70, 128, 0x00000000, 0x20300050},
++};
++
++#define MAX_CCI_LEVEL 128
++static unsigned long last_jiffies = INITIAL_JIFFIES;
++static s32 size = sizeof(adjust_cci) / sizeof(adjust_cci[0]);
++static u32 current_level = MAX_CCI_LEVEL;
++static u32 current_gate = (sizeof(adjust_cci) / sizeof(adjust_cci[0])) - 1;
++void mitigate_cci(struct ssv_softc *sc, u32 input_level)
++{
++	s32 i;
++	if (input_level > MAX_CCI_LEVEL) {
++		dev_dbg(sc->dev, "mitigate_cci input error[%d]!!\n", input_level);
++		return;
++	}
++	if (time_after(jiffies, last_jiffies + msecs_to_jiffies(3000))) {
++		dev_dbg(sc->dev, "jiffies=%lu, input_level=%d\n", jiffies, input_level);
++		last_jiffies = jiffies;
++		if ((input_level >= adjust_cci[current_gate].down_level)
++		    && (input_level <= adjust_cci[current_gate].upper_level)) {
++			current_level = input_level;
++#ifdef DEBUG_MITIGATE_CCI
++			dev_dbg(sc->dev, "Keep the 0xce0020a0[%x] 0xce002008[%x]!!\n",
++			       adjust_cci[current_gate].adjust_cca_control,
++			       adjust_cci[current_gate].adjust_cca_1);
++#endif
++		} else {
++			if (current_level < input_level) {
++				for (i = 0; i < size; i++) {
++					if (input_level <=
++					    adjust_cci[i].upper_level) {
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].upper_level=%d, value=%08x\n",
++						     current_gate, input_level,
++						     i,
++						     adjust_cci[i].upper_level,
++						     adjust_cci[i].
++						     adjust_cca_control);
++#endif
++						current_level = input_level;
++						current_gate = i;
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_CONTROL,
++							       adjust_cci[i].
++							       adjust_cca_control);
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_1,
++							       adjust_cci[i].
++							       adjust_cca_1);
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
++						     adjust_cci[current_gate].
++						     adjust_cca_control,
++						     adjust_cci[current_gate].
++						     adjust_cca_1);
++#endif
++						return;
++					}
++				}
++			} else {
++				for (i = (size - 1); i >= 0; i--) {
++					if (input_level >=
++					    adjust_cci[i].down_level) {
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].down_level=%d, value=%08x\n",
++						     current_gate, input_level,
++						     i,
++						     adjust_cci[i].down_level,
++						     adjust_cci[i].
++						     adjust_cca_control);
++#endif
++						current_level = input_level;
++						current_gate = i;
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_CONTROL,
++							       adjust_cci[i].
++							       adjust_cca_control);
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_1,
++							       adjust_cci[i].
++							       adjust_cca_1);
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
++						     adjust_cci[current_gate].
++						     adjust_cca_control,
++						     adjust_cci[current_gate].
++						     adjust_cca_1);
++#endif
++						return;
++					}
++				}
++			}
++		}
++	}
++}
++
++#define RSSI_SMOOTHING_SHIFT 5
++#define RSSI_DECIMAL_POINT_SHIFT 6
++static void _proc_data_rx_skb(struct ssv_softc *sc, struct sk_buff *rx_skb)
++{
++	struct ieee80211_rx_status *rxs;
++	struct ieee80211_hdr *hdr;
++	__le16 fc;
++	struct ssv6200_rx_desc *rxdesc;
++	struct ssv6200_rxphy_info_padding *rxphypad;
++	struct ssv6200_rxphy_info *rxphy;
++	struct ieee80211_channel *chan;
++	struct ieee80211_vif *vif = NULL;
++	struct ieee80211_sta *sta = NULL;
++	bool rx_hw_dec = false;
++	bool do_sw_dec = false;
++	struct ssv_sta_priv_data *sta_priv = NULL;
++	struct ssv_vif_priv_data *vif_priv = NULL;
++	SKB_info *skb_info = NULL;
++	u8 is_beacon;
++	u8 is_probe_resp;
++	s32 found = 0;
++#ifdef CONFIG_SSV_SMARTLINK
++	{
++		extern int ksmartlink_smartlink_started(void);
++		void smartlink_nl_send_msg(struct sk_buff *skb);
++		if (unlikely(ksmartlink_smartlink_started())) {
++			skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
++			skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
++			smartlink_nl_send_msg(rx_skb);
++			return;
++		}
++	}
++#endif
++	rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
++	rxphy = (struct ssv6200_rxphy_info *)(rx_skb->data + sizeof(*rxdesc));
++	rxphypad =
++	    (struct ssv6200_rxphy_info_padding *)(rx_skb->data + rx_skb->len -
++						  sizeof(struct
++							 ssv6200_rxphy_info_padding));
++	hdr = (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
++	fc = hdr->frame_control;
++	skb_info = (SKB_info *) rx_skb->head;
++	if (rxdesc->wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
++		if ((ieee80211_is_data(hdr->frame_control))
++		    && (!(ieee80211_is_nullfunc(hdr->frame_control)))) {
++			ssv6xxx_rc_rx_data_handler(sc->hw, rx_skb,
++						   rxdesc->rate_idx);
++		}
++	}
++	rxs = IEEE80211_SKB_RXCB(rx_skb);
++	memset(rxs, 0, sizeof(struct ieee80211_rx_status));
++	ssv6xxx_rc_mac8011_rate_idx(sc, rxdesc->rate_idx, rxs);
++
++	rxs->mactime = *((u32 *) & rx_skb->data[28]);
++	chan = sc->hw->conf.chandef.chan;
++	rxs->band = chan->band;
++	rxs->freq = chan->center_freq;
++	rxs->antenna = 1;
++	is_beacon = ieee80211_is_beacon(hdr->frame_control);
++	is_probe_resp = ieee80211_is_probe_resp(hdr->frame_control);
++	if (is_beacon)		//+++
++	{
++		struct ieee80211_mgmt *mgmt_tmp = NULL;
++		mgmt_tmp =
++		    (struct ieee80211_mgmt *)(rx_skb->data +
++					      SSV6XXX_RX_DESC_LEN);
++		mgmt_tmp->u.beacon.timestamp =
++		    cpu_to_le64(ssv6200_get_systime_us());
++	}
++	if (is_probe_resp) {
++		struct ieee80211_mgmt *mgmt_tmp = NULL;
++		mgmt_tmp =
++		    (struct ieee80211_mgmt *)(rx_skb->data +
++					      SSV6XXX_RX_DESC_LEN);
++		mgmt_tmp->u.probe_resp.timestamp =
++		    cpu_to_le64(ssv6200_get_systime_us());
++	}
++
++	if (rxdesc->rate_idx < SSV62XX_G_RATE_INDEX && rxphypad->RSVD == 0) {
++		if (is_beacon || is_probe_resp) {
++			sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++			if (sta) {
++				sta_priv =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "b_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
++				       hdr->addr2[0], hdr->addr2[1],
++				       hdr->addr2[2], hdr->addr2[3],
++				       hdr->addr2[4], hdr->addr2[5],
++				       rxphypad->rpci, rxphypad->snr);
++#endif
++				if (sta_priv->beacon_rssi) {
++					sta_priv->beacon_rssi =
++					    ((rxphypad->
++					      rpci << RSSI_DECIMAL_POINT_SHIFT)
++					     +
++					     ((sta_priv->
++					       beacon_rssi <<
++					       RSSI_SMOOTHING_SHIFT) -
++					      sta_priv->
++					      beacon_rssi)) >>
++					    RSSI_SMOOTHING_SHIFT;
++					rxphypad->rpci =
++					    (sta_priv->
++					     beacon_rssi >>
++					     RSSI_DECIMAL_POINT_SHIFT);
++				} else
++					sta_priv->beacon_rssi =
++					    (rxphypad->
++					     rpci << RSSI_DECIMAL_POINT_SHIFT);
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphypad->rpci);
++#endif
++				mitigate_cci(sc, rxphypad->rpci);
++			} else {
++				mutex_lock(&sc->mutex);
++				list_for_each_entry(p_rssi_res,
++						    &rssi_res.rssi_list,
++						    rssi_list) {
++					if (!memcmp
++					    (p_rssi_res->bssid, hdr->addr2,
++					     ETH_ALEN)) {
++						{
++							p_rssi_res->rssi =
++							    ((rxphypad->
++							      rpci <<
++							      RSSI_DECIMAL_POINT_SHIFT)
++							     +
++							     ((p_rssi_res->
++							       rssi <<
++							       RSSI_SMOOTHING_SHIFT)
++							      -
++							      p_rssi_res->
++							      rssi)) >>
++							    RSSI_SMOOTHING_SHIFT;
++							rxphypad->rpci =
++							    (p_rssi_res->
++							     rssi >>
++							     RSSI_DECIMAL_POINT_SHIFT);
++						}
++						p_rssi_res->cache_jiffies =
++						    jiffies;
++						found = 1;
++						break;
++					} else {
++						if (p_rssi_res->rssi) {
++							if (time_after
++							    (jiffies,
++							     p_rssi_res->
++							     cache_jiffies +
++							     msecs_to_jiffies
++							     (40000))) {
++								p_rssi_res->
++								    timeout = 1;
++							}
++						}
++					}
++				}
++				if (!found) {
++					p_rssi_res =
++					    kmalloc(sizeof(struct rssi_res_st),
++						    GFP_KERNEL);
++					memcpy(p_rssi_res->bssid, hdr->addr2,
++					       ETH_ALEN);
++					p_rssi_res->cache_jiffies = jiffies;
++					p_rssi_res->rssi =
++					    (rxphypad->
++					     rpci << RSSI_DECIMAL_POINT_SHIFT);
++					p_rssi_res->timeout = 0;
++					INIT_LIST_HEAD(&p_rssi_res->rssi_list);
++					list_add_tail_rcu(&
++							  (p_rssi_res->
++							   rssi_list),
++							  &(rssi_res.
++							    rssi_list));
++				}
++				mutex_unlock(&sc->mutex);
++			}
++			if (rxphypad->rpci > 88)
++				rxphypad->rpci = 88;
++		}
++		if (sc->sh->cfg.rssi_ctl) {
++			rxs->signal = (-rxphypad->rpci) + sc->sh->cfg.rssi_ctl;
++		} else {
++			rxs->signal = (-rxphypad->rpci);
++		}
++	} else if (rxdesc->rate_idx >= SSV62XX_G_RATE_INDEX
++		   && rxphy->service == 0) {
++		if (is_beacon || is_probe_resp) {
++			sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++			if (sta) {
++				sta_priv =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "gn_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
++				     hdr->addr2[0], hdr->addr2[1],
++				     hdr->addr2[2], hdr->addr2[3],
++				     hdr->addr2[4], hdr->addr2[5], rxphy->rpci,
++				     rxphy->snr);
++#endif
++				if (sta_priv->beacon_rssi) {
++					sta_priv->beacon_rssi =
++					    ((rxphy->
++					      rpci << RSSI_DECIMAL_POINT_SHIFT)
++					     +
++					     ((sta_priv->
++					       beacon_rssi <<
++					       RSSI_SMOOTHING_SHIFT) -
++					      sta_priv->
++					      beacon_rssi)) >>
++					    RSSI_SMOOTHING_SHIFT;
++					rxphy->rpci =
++					    (sta_priv->
++					     beacon_rssi >>
++					     RSSI_DECIMAL_POINT_SHIFT);
++				} else
++					sta_priv->beacon_rssi =
++					    (rxphy->
++					     rpci << RSSI_DECIMAL_POINT_SHIFT);
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphy->rpci);
++#endif
++			}
++			if (rxphy->rpci > 88)
++				rxphy->rpci = 88;
++		}
++		if (sc->sh->cfg.rssi_ctl) {
++			rxs->signal = (-rxphy->rpci) + sc->sh->cfg.rssi_ctl;
++		} else {
++			rxs->signal = (-rxphy->rpci);
++		}
++	} else {
++#ifdef SSV_RSSI_DEBUG
++		dev_dbg(sc->dev, "########unicast: %d, b_rssi/snr: %d/%d, gn_rssi/snr: %d/%d, rate:%d###############\n",
++		     rxdesc->unicast, (-rxphy->rpci), rxphy->snr,
++		     (-rxphypad->rpci), rxphypad->snr, rxdesc->rate_idx);
++		dev_dbg(sc->dev, "RSSI, %d, rate_idx, %d\n", rxs->signal,
++		       rxdesc->rate_idx);
++		dev_dbg(sc->dev, "rxdesc->RxResult = %x,rxdesc->wsid = %d\n",
++		       rxdesc->RxResult, rxdesc->wsid);
++#endif
++		sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++		if (sta) {
++			sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++			rxs->signal =
++			    -(sta_priv->
++			      beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
++		}
++#ifdef SSV_RSSI_DEBUG
++		dev_dbg(sc->dev, "Others signal %d\n", rxs->signal);
++#endif
++	}
++//    rxs->flag = RX_FLAG_MACTIME_START;          //+++
++	rxs->rx_flags = 0;
++	if (rxphy->aggregate)
++		rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
++	sc->hw_mng_used = rxdesc->mng_used;
++	if ((ieee80211_is_data(fc) || ieee80211_is_data_qos(fc))
++	    && ieee80211_has_protected(fc)) {
++		sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++		if (sta == NULL)
++			goto drop_rx;
++		sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		vif = sta_priv->sta_info->vif;
++		if (vif == NULL)
++			goto drop_rx;
++		if (is_broadcast_ether_addr(hdr->addr1) || is_multicast_ether_addr(hdr->addr1)) {
++			vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
++			rx_hw_dec = vif_priv->has_hw_decrypt;
++			do_sw_dec = vif_priv->need_sw_decrypt;
++		} else {
++			rx_hw_dec = sta_priv->has_hw_decrypt;
++			do_sw_dec = sta_priv->need_sw_decrypt;
++		}
++	}
++	skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
++	skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
++#ifdef CONFIG_P2P_NOA
++	if (is_beacon)
++		ssv6xxx_noa_detect(sc, hdr, rx_skb->len);
++#endif
++	if (rx_hw_dec || do_sw_dec) {
++		hdr = (struct ieee80211_hdr *)rx_skb->data;
++		rxs = IEEE80211_SKB_RXCB(rx_skb);
++		hdr->frame_control =
++		    hdr->
++		    frame_control & ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED));
++		rxs->flag |= (RX_FLAG_DECRYPTED | RX_FLAG_IV_STRIPPED);
++	}
++#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_RX_DATA)
++	local_bh_disable();
++	ieee80211_rx(sc->hw, rx_skb);
++	local_bh_enable();
++#else
++	ieee80211_rx_irqsafe(sc->hw, rx_skb);
++#endif
++	return;
++ drop_rx:
++	dev_kfree_skb_any(rx_skb);
++}
++
++#ifdef IRQ_PROC_RX_DATA
++static struct sk_buff *_proc_rx_skb(struct ssv_softc *sc,
++				    struct sk_buff *rx_skb)
++{
++	struct ieee80211_hdr *hdr =
++	    (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
++	struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
++	if (ieee80211_is_back(hdr->frame_control)
++	    || (rxdesc->c_type == HOST_EVENT))
++		return rx_skb;
++	_proc_data_rx_skb(sc, rx_skb);
++	return NULL;
++}
++#endif
++void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
++		   spinlock_t * rx_q_lock)
++{
++	struct sk_buff *skb;
++	struct ieee80211_hdr *hdr;
++	struct ssv6200_rx_desc *rxdesc;
++	unsigned long flags = 0;
++#ifdef USE_FLUSH_RETRY
++	bool has_ba_processed = false;
++#endif
++	while (1) {
++		if (rx_q_lock != NULL) {
++			spin_lock_irqsave(rx_q_lock, flags);
++			skb = __skb_dequeue(rx_q);
++		} else
++			skb = skb_dequeue(rx_q);
++		if (!skb) {
++			if (rx_q_lock != NULL)
++				spin_unlock_irqrestore(rx_q_lock, flags);
++			break;
++		}
++		sc->rx.rxq_count--;
++		if (rx_q_lock != NULL)
++			spin_unlock_irqrestore(rx_q_lock, flags);
++		rxdesc = (struct ssv6200_rx_desc *)skb->data;
++		if (rxdesc->c_type == HOST_EVENT) {
++			struct cfg_host_event *h_evt =
++			    (struct cfg_host_event *)rxdesc;
++			if (h_evt->h_event == SOC_EVT_NO_BA) {
++				ssv6200_ampdu_no_BA_handler(sc->hw, skb);
++#ifdef USE_FLUSH_RETRY
++				has_ba_processed = true;
++#endif
++			} else if (h_evt->h_event == SOC_EVT_RC_MPDU_REPORT) {
++				skb_queue_tail(&sc->rc_report_queue, skb);
++				if (sc->rc_sample_sechedule == 0)
++					queue_work(sc->rc_sample_workqueue,
++						   &sc->rc_sample_work);
++			} else if (h_evt->h_event == SOC_EVT_SDIO_TEST_COMMAND) {
++				if (h_evt->evt_seq_no == 0) {
++					dev_dbg(sc->dev, "SOC_EVT_SDIO_TEST_COMMAND\n");
++					sc->sdio_rx_evt_size = h_evt->len;
++					sc->sdio_throughput_timestamp = jiffies;
++				} else {
++					sc->sdio_rx_evt_size += h_evt->len;
++					if (time_after
++					    (jiffies,
++					     sc->sdio_throughput_timestamp +
++					     msecs_to_jiffies(1000))) {
++						dev_dbg(sc->dev, "data[%ld] SDIO RX throughput %ld Kbps\n",
++						     sc->sdio_rx_evt_size,
++						     (sc->
++						      sdio_rx_evt_size << 3) /
++						     jiffies_to_msecs(jiffies -
++								      sc->
++								      sdio_throughput_timestamp));
++						sc->sdio_throughput_timestamp =
++						    jiffies;
++						sc->sdio_rx_evt_size = 0;
++					}
++				}
++				dev_kfree_skb_any(skb);
++			} else if (h_evt->h_event == SOC_EVT_WATCHDOG_TRIGGER) {
++				dev_kfree_skb_any(skb);
++//              if(sc->watchdog_flag != WD_SLEEP)     //+++
++				sc->watchdog_flag = WD_KICKED;
++			} else if (h_evt->h_event == SOC_EVT_RESET_HOST) {
++				dev_kfree_skb_any(skb);
++				if ((sc->ap_vif == NULL)
++				    || !(sc->sh->cfg.ignore_reset_in_ap)) {
++					ssv6xxx_restart_hw(sc);
++				} else {
++					dev_warn(sc->dev,
++						 "Reset event ignored.\n");
++				}
++			}
++#ifdef CONFIG_P2P_NOA
++			else if (h_evt->h_event == SOC_EVT_NOA) {
++				ssv6xxx_process_noa_event(sc, skb);
++				dev_kfree_skb_any(skb);
++			}
++#endif
++			else if (h_evt->h_event == SOC_EVT_SDIO_TXTPUT_RESULT) {
++				dev_dbg(sc->dev, "data SDIO TX throughput %d Kbps\n",
++				       h_evt->evt_seq_no);
++				dev_kfree_skb_any(skb);
++			} else if (h_evt->h_event == SOC_EVT_TXLOOPBK_RESULT) {
++				if (h_evt->evt_seq_no == SSV6XXX_STATE_OK) {
++					dev_dbg(sc->dev, "FW TX LOOPBACK OK\n");
++					sc->iq_cali_done = IQ_CALI_OK;
++				} else {
++					dev_dbg(sc->dev, "FW TX LOOPBACK FAILED\n");
++					sc->iq_cali_done = IQ_CALI_FAILED;
++				}
++				dev_kfree_skb_any(skb);
++				wake_up_interruptible(&sc->fw_wait_q);
++			} else {
++				dev_warn(sc->dev, "Unkown event %d received\n",
++					 h_evt->h_event);
++				dev_kfree_skb_any(skb);
++			}
++			continue;
++		}
++		hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
++		if (ieee80211_is_back(hdr->frame_control)) {
++			ssv6200_ampdu_BA_handler(sc->hw, skb);
++#ifdef USE_FLUSH_RETRY
++			has_ba_processed = true;
++#endif
++			continue;
++		}
++		_proc_data_rx_skb(sc, skb);
++	}
++#ifdef USE_FLUSH_RETRY
++	if (has_ba_processed) {
++		ssv6xxx_ampdu_postprocess_BA(sc->hw);
++	}
++#endif
++}
++
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args)
++#else
++int ssv6200_rx(struct sk_buff *rx_skb, void *args)
++#endif
++{
++	struct ssv_softc *sc = args;
++#ifdef IRQ_PROC_RX_DATA
++	struct sk_buff *skb;
++	skb = _proc_rx_skb(sc, rx_skb);
++	if (skb == NULL)
++		return 0;
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	{
++		unsigned long flags;
++		spin_lock_irqsave(&sc->rx_skb_q.lock, flags);
++		while (skb_queue_len(rx_skb_q))
++			__skb_queue_tail(&sc->rx_skb_q,
++					 __skb_dequeue(rx_skb_q));
++		spin_unlock_irqrestore(&sc->rx_skb_q.lock, flags);
++	}
++#else
++	skb_queue_tail(&sc->rx_skb_q, rx_skb);
++#endif
++	wake_up_interruptible(&sc->rx_wait_q);
++	return 0;
++}
++
++struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
++						 struct sk_buff *skb)
++{
++	struct ieee80211_hdr *hdr =
++	    (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
++	struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)skb->data;;
++	if ((rxdesc->wsid >= 0) && (rxdesc->wsid < SSV_NUM_STA))
++		return sc->sta_info[rxdesc->wsid].sta;
++	else
++		return ssv6xxx_find_sta_by_addr(sc, hdr->addr2);
++}
++
++struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc, u8 addr[6])
++{
++	struct ieee80211_sta *sta;
++	int i;
++	for (i = 0; i < SSV6200_MAX_VIF; i++) {
++		if (sc->vif_info[i].vif == NULL)
++			continue;
++		sta = ieee80211_find_sta(sc->vif_info[i].vif, addr);
++		if (sta != NULL)
++			return sta;
++	}
++	return NULL;
++}
++
++void ssv6xxx_foreach_sta(struct ssv_softc *sc,
++			 void (*sta_func)(struct ssv_softc *,
++					  struct ssv_sta_info *, void *),
++			 void *param)
++{
++	int i;
++	BUG_ON(sta_func == NULL);
++	for (i = 0; i < SSV_NUM_STA; i++) {
++		if ((sc->sta_info[i].s_flags & STA_FLAG_VALID) == 0)
++			continue;
++		(*sta_func) (sc, &sc->sta_info[i], param);
++	}
++}
++
++void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
++			     struct ssv_vif_info *vif_info,
++			     void (*sta_func)(struct ssv_softc *,
++					      struct ssv_vif_info *,
++					      struct ssv_sta_info *,
++					      void *), void *param)
++{
++	struct ssv_vif_priv_data *vif_priv;
++	struct ssv_sta_priv_data *sta_priv_iter;
++	BUG_ON(vif_info == NULL);
++	BUG_ON((size_t)vif_info < 0x30000);
++	vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	BUG_ON((size_t)vif_info->vif < 0x30000);
++	BUG_ON((size_t)vif_priv < 0x30000);
++	list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
++		BUG_ON(sta_priv_iter == NULL);
++		BUG_ON((size_t)sta_priv_iter < 0x30000);
++		BUG_ON(sta_priv_iter->sta_info == NULL);
++		BUG_ON((size_t)sta_priv_iter->sta_info < 0x30000);
++		if ((sta_priv_iter->sta_info->s_flags & STA_FLAG_VALID) == 0)
++			continue;
++		(*sta_func) (sc, vif_info, sta_priv_iter->sta_info, param);
++	}
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
++				     ssize_t length)
++{
++	ssize_t buf_size = length;
++	ssize_t prt_size;
++	prt_size =
++	    snprintf(status_buf, buf_size, "\nSMAC driver queue status:.\n");
++	status_buf += prt_size;
++	buf_size -= prt_size;
++	prt_size = snprintf(status_buf, buf_size, "\tTX queue: %d\n",
++			    skb_queue_len(&sc->tx_skb_q));
++	status_buf += prt_size;
++	buf_size -= prt_size;
++	prt_size = snprintf(status_buf, buf_size, "\tMax TX queue: %d\n",
++			    sc->max_tx_skb_q_len);
++	status_buf += prt_size;
++	buf_size -= prt_size;
++	return (length - buf_size);
++}
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/dev.h b/drivers/net/wireless/ssv6051/smac/dev.h
+new file mode 100644
+index 000000000000..0a6357624b1c
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/dev.h
+@@ -0,0 +1,445 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _DEV_H_
++#define _DEV_H_
++#include <linux/version.h>
++#include <linux/device.h>
++#include <linux/interrupt.h>
++#include <net/mac80211.h>
++#include "ampdu.h"
++#include "ssv_rc_common.h"
++#include "drv_comm.h"
++#include "sec.h"
++#include "p2p.h"
++#include <linux/kthread.h>
++#define SSV6200_MAX_HW_MAC_ADDR 2
++#define SSV6200_MAX_VIF 2
++#define SSV6200_RX_BA_MAX_SESSIONS 1
++#define SSV6200_OPMODE_STA 0
++#define SSV6200_OPMODE_AP 1
++#define SSV6200_OPMODE_IBSS 2
++#define SSV6200_OPMODE_WDS 3
++#define SSV6200_USE_HW_WSID(_sta_idx) ((_sta_idx == 0) || (_sta_idx == 1))
++#define HW_MAX_RATE_TRIES 7
++#define MAC_DECITBL1_SIZE 16
++#define MAC_DECITBL2_SIZE 9
++#define RX_11B_CCA_IN_SCAN 0x20230050
++//#define WATCHDOG_TIMEOUT (10*HZ)
++#define WATCHDOG_TIMEOUT (99999*HZ)
++extern u16 generic_deci_tbl[];
++#define ap_deci_tbl generic_deci_tbl
++#define sta_deci_tbl generic_deci_tbl
++#define HT_SIGNAL_EXT 6
++#define HT_SIFS_TIME 10
++#define BITS_PER_BYTE 8
++#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
++#define ACK_LEN (14)
++#define BA_LEN (32)
++#define RTS_LEN (20)
++#define CTS_LEN (14)
++#define L_STF 8
++#define L_LTF 8
++#define L_SIG 4
++#define HT_SIG 8
++#define HT_STF 4
++#define HT_LTF(_ns) (4 * (_ns))
++#define SYMBOL_TIME(_ns) ((_ns) << 2)
++#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)
++#define CCK_SIFS_TIME 10
++#define CCK_PREAMBLE_BITS 144
++#define CCK_PLCP_BITS 48
++#define OFDM_SIFS_TIME 16
++#define OFDM_PREAMBLE_TIME 20
++#define OFDM_PLCP_BITS 22
++#define OFDM_SYMBOL_TIME 4
++#define WMM_AC_VO 0
++#define WMM_AC_VI 1
++#define WMM_AC_BE 2
++#define WMM_AC_BK 3
++#define WMM_NUM_AC 4
++#define WMM_TID_NUM 8
++#define TXQ_EDCA_0 0x01
++#define TXQ_EDCA_1 0x02
++#define TXQ_EDCA_2 0x04
++#define TXQ_EDCA_3 0x08
++#define TXQ_MGMT 0x10
++#define IS_SSV_HT(dsc) ((dsc)->rate_idx >= 15)
++#define IS_SSV_SHORT_GI(dsc) ((dsc)->rate_idx>=23 && (dsc)->rate_idx<=30)
++#define IS_SSV_HT_GF(dsc) ((dsc)->rate_idx >= 31)
++#define IS_SSV_SHORT_PRE(dsc) ((dsc)->rate_idx>=4 && (dsc)->rate_idx<=14)
++#define SMAC_REG_WRITE(_s,_r,_v) \
++        (_s)->hci.hci_ops->hci_write_word(_r,_v)
++#define SMAC_REG_READ(_s,_r,_v) \
++        (_s)->hci.hci_ops->hci_read_word(_r, _v)
++#define SMAC_LOAD_FW(_s,_r,_v) \
++        (_s)->hci.hci_ops->hci_load_fw(_r, _v)
++#define SMAC_IFC_RESET(_s) (_s)->hci.hci_ops->hci_interface_reset()
++#define SMAC_REG_CONFIRM(_s,_r,_v) \
++{ \
++    u32 _regval; \
++    SMAC_REG_READ(_s, _r, &_regval); \
++    if (_regval != (_v)) { \
++        printk("ERROR!!Please check interface!\n"); \
++        printk("[0x%08x]: 0x%08x!=0x%08x\n", \
++        (_r), (_v), _regval); \
++        printk("SOS!SOS!\n"); \
++        return -1; \
++    } \
++}
++#define SMAC_REG_SET_BITS(_sh,_reg,_set,_clr) \
++({ \
++    int ret; \
++    u32 _regval; \
++    ret = SMAC_REG_READ(_sh, _reg, &_regval); \
++    _regval &= ~(_clr); \
++    _regval |= (_set); \
++    if (ret == 0) \
++        ret = SMAC_REG_WRITE(_sh, _reg, _regval); \
++    ret; \
++})
++#define HCI_START(_sh) \
++    (_sh)->hci.hci_ops->hci_start()
++#define HCI_STOP(_sh) \
++    (_sh)->hci.hci_ops->hci_stop()
++#define HCI_SEND(_sh,_sk,_q) \
++    (_sh)->hci.hci_ops->hci_tx(_sk, _q, 0)
++#define HCI_PAUSE(_sh,_mk) \
++    (_sh)->hci.hci_ops->hci_tx_pause(_mk)
++#define HCI_RESUME(_sh,_mk) \
++    (_sh)->hci.hci_ops->hci_tx_resume(_mk)
++#define HCI_TXQ_FLUSH(_sh,_mk) \
++    (_sh)->hci.hci_ops->hci_txq_flush(_mk)
++#define HCI_TXQ_FLUSH_BY_STA(_sh,_aid) \
++  (_sh)->hci.hci_ops->hci_txq_flush_by_sta(_aid)
++#define HCI_TXQ_EMPTY(_sh,_txqid) \
++  (_sh)->hci.hci_ops->hci_txq_empty(_txqid)
++#define HCI_WAKEUP_PMU(_sh) \
++    (_sh)->hci.hci_ops->hci_pmu_wakeup()
++#define HCI_SEND_CMD(_sh,_sk) \
++        (_sh)->hci.hci_ops->hci_send_cmd(_sk)
++#define SSV6XXX_SET_HW_TABLE(sh_,tbl_) \
++({ \
++    int ret = 0; \
++    u32 i=0; \
++    for(; i<sizeof(tbl_)/sizeof(struct ssv6xxx_dev_table); i++) { \
++        ret = SMAC_REG_WRITE(sh_, tbl_[i].address, tbl_[i].data); \
++        if (ret) break; \
++    } \
++    ret; \
++})
++#define SSV6XXX_USE_HW_DECRYPT(_priv) (_priv->has_hw_decrypt)
++#define SSV6XXX_USE_SW_DECRYPT(_priv) (SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) || SSV6XXX_USE_MAC80211_DECRYPT(_priv))
++#define SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) (_priv->need_sw_decrypt)
++#define SSV6XXX_USE_MAC80211_DECRYPT(_priv) (_priv->use_mac80211_decrypt)
++struct ssv_softc;
++#ifdef CONFIG_P2P_NOA
++struct ssv_p2p_noa;
++#endif
++#define SSV6200_HT_TX_STREAMS 1
++#define SSV6200_HT_RX_STREAMS 1
++#define SSV6200_RX_HIGHEST_RATE 72
++enum PWRSV_STATUS {
++	PWRSV_DISABLE,
++	PWRSV_ENABLE,
++	PWRSV_PREPARE,
++};
++struct rssi_res_st {
++	struct list_head rssi_list;
++	unsigned long cache_jiffies;
++	s32 rssi;
++	s32 timeout;
++	u8 bssid[ETH_ALEN];
++};
++struct ssv_hw {
++	struct ssv_softc *sc;
++	struct ssv6xxx_platform_data *priv;
++	struct ssv6xxx_hci_info hci;
++	char chip_id[24];
++	u64 chip_tag;
++	u32 tx_desc_len;
++	u32 rx_desc_len;
++	u32 rx_pinfo_pad;
++	u32 tx_page_available;
++	u32 ampdu_divider;
++	u8 page_count[SSV6200_ID_NUMBER];
++	u32 hw_buf_ptr[SSV_RC_MAX_STA];
++	u32 hw_sec_key[SSV_RC_MAX_STA];
++	u32 hw_pinfo;
++	struct ssv6xxx_cfg cfg;
++	u32 n_addresses;
++	struct mac_address maddr[SSV6200_MAX_HW_MAC_ADDR];
++	u8 ipd_channel_touch;
++	struct ssv6xxx_ch_cfg *p_ch_cfg;
++	u32 ch_cfg_size;
++};
++struct ssv_tx {
++	u16 seq_no;
++	int hw_txqid[WMM_NUM_AC];
++	int ac_txqid[WMM_NUM_AC];
++	u32 flow_ctrl_status;
++	u32 tx_pkt[SSV_HW_TXQ_NUM];
++	u32 tx_frag[SSV_HW_TXQ_NUM];
++	struct list_head ampdu_tx_que;
++	spinlock_t ampdu_tx_que_lock;
++	u16 ampdu_tx_group_id;
++};
++struct ssv_rx {
++	struct sk_buff *rx_buf;
++	spinlock_t rxq_lock;
++	struct sk_buff_head rxq_head;
++	u32 rxq_count;
++};
++#define SSV6XXX_GET_STA_INFO(_sc,_s) \
++    &(_sc)->sta_info[((struct ssv_sta_priv_data *)((_s)->drv_priv))->sta_idx]
++#define STA_FLAG_VALID 0x00001
++#define STA_FLAG_QOS 0x00002
++#define STA_FLAG_AMPDU 0x00004
++#define STA_FLAG_ENCRYPT 0x00008
++struct ssv_sta_info {
++	u16 aid;
++	u16 s_flags;
++	int hw_wsid;
++	struct ieee80211_sta *sta;
++	struct ieee80211_vif *vif;
++	bool sleeping;
++	bool tim_set;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++#endif
++};
++struct ssv_vif_info {
++	struct ieee80211_vif *vif;
++	struct ssv_vif_priv_data *vif_priv;
++	enum nl80211_iftype if_type;
++	struct ssv6xxx_hw_sec sramKey;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++#endif
++};
++struct ssv_sta_priv_data {
++	int sta_idx;
++	int rc_idx;
++	int rx_data_rate;
++	struct ssv_sta_info *sta_info;
++	struct list_head list;
++	u32 ampdu_mib_total_BA_counter;
++	AMPDU_TID ampdu_tid[WMM_TID_NUM];
++	bool has_hw_encrypt;
++	bool need_sw_encrypt;
++	bool has_hw_decrypt;
++	bool need_sw_decrypt;
++	bool use_mac80211_decrypt;
++	u8 group_key_idx;
++	u32 beacon_rssi;
++};
++struct ssv_vif_priv_data {
++	int vif_idx;
++	struct list_head sta_list;
++	u32 sta_asleep_mask;
++	u32 pair_cipher;
++	u32 group_cipher;
++	bool is_security_valid;
++	bool has_hw_encrypt;
++	bool need_sw_encrypt;
++	bool has_hw_decrypt;
++	bool need_sw_decrypt;
++	bool use_mac80211_decrypt;
++	bool force_sw_encrypt;
++	u8 group_key_idx;
++};
++#define SC_OP_INVALID 0x00000001
++#define SC_OP_HW_RESET 0x00000002
++#define SC_OP_OFFCHAN 0x00000004
++#define SC_OP_FIXED_RATE 0x00000008
++#define SC_OP_SHORT_PREAMBLE 0x00000010
++struct ssv6xxx_beacon_info {
++	u32 pubf_addr;
++	u16 len;
++	u8 tim_offset;
++	u8 tim_cnt;
++};
++#define SSV6200_MAX_BCAST_QUEUE_LEN 16
++struct ssv6xxx_bcast_txq {
++	spinlock_t txq_lock;
++	struct sk_buff_head qhead;
++	int cur_qsize;
++};
++#ifdef DEBUG_AMPDU_FLUSH
++typedef struct AMPDU_TID_st AMPDU_TID;
++#define MAX_TID (24)
++#endif
++struct ssv_softc {
++	struct ieee80211_hw *hw;
++	struct device *dev;
++	u32 restart_counter;
++	bool force_triger_reset;
++	unsigned long sdio_throughput_timestamp;
++	unsigned long sdio_rx_evt_size;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
++	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
++#else
++	struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
++#endif
++	struct ieee80211_channel *cur_channel;
++	u16 hw_chan;
++	struct mutex mutex;
++	struct ssv_hw *sh;
++	struct ssv_tx tx;
++	struct ssv_rx rx;
++	struct ssv_vif_info vif_info[SSV_NUM_VIF];
++	struct ssv_sta_info sta_info[SSV_NUM_STA];
++	struct ieee80211_vif *ap_vif;
++	u8 nvif;
++	u32 sc_flags;
++	void *rc;
++	int max_rate_idx;
++	struct workqueue_struct *rc_sample_workqueue;
++	struct sk_buff_head rc_report_queue;
++	struct work_struct rc_sample_work;
++#ifdef DEBUG_AMPDU_FLUSH
++	struct AMPDU_TID_st *tid[MAX_TID];
++#endif
++	u16 rc_sample_sechedule;
++	u16 *mac_deci_tbl;
++	struct workqueue_struct *config_wq;
++	bool bq4_dtim;
++	struct work_struct set_tim_work;
++	u8 enable_beacon;
++	u8 beacon_interval;
++	u8 beacon_dtim_cnt;
++	u8 beacon_usage;
++	struct ssv6xxx_beacon_info beacon_info[2];
++	struct sk_buff *beacon_buf;
++	struct work_struct bcast_start_work;
++	struct delayed_work bcast_stop_work;
++	struct delayed_work bcast_tx_work;
++	struct delayed_work thermal_monitor_work;
++	struct workqueue_struct *thermal_wq;
++	int is_sar_enabled;
++	bool aid0_bit_set;
++	u8 hw_mng_used;
++	struct ssv6xxx_bcast_txq bcast_txq;
++	int bcast_interval;
++	u8 bssid[6];
++	struct mutex mem_mutex;
++	spinlock_t ps_state_lock;
++	u8 hw_wsid_bit;
++	int rx_ba_session_count;
++	struct ieee80211_sta *rx_ba_sta;
++	u8 rx_ba_bitmap;
++	u8 ba_ra_addr[ETH_ALEN];
++	u16 ba_tid;
++	u16 ba_ssn;
++	struct work_struct set_ampdu_rx_add_work;
++	struct work_struct set_ampdu_rx_del_work;
++	bool isAssoc;
++	u16 channel_center_freq;
++	bool bScanning;
++	int ps_status;
++	u16 ps_aid;
++	u16 tx_wait_q_woken;
++	wait_queue_head_t tx_wait_q;
++	struct sk_buff_head tx_skb_q;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	u32 max_tx_skb_q_len;
++#endif
++	struct task_struct *tx_task;
++	bool tx_q_empty;
++	struct sk_buff_head tx_done_q;
++	u16 rx_wait_q_woken;
++	wait_queue_head_t rx_wait_q;
++	struct sk_buff_head rx_skb_q;
++	struct task_struct *rx_task;
++	bool dbg_rx_frame;
++	bool dbg_tx_frame;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++#endif
++#ifdef CONFIG_P2P_NOA
++	struct ssv_p2p_noa p2p_noa;
++#endif
++	struct timer_list watchdog_timeout;
++	u32 watchdog_flag;
++	wait_queue_head_t fw_wait_q;
++	u32 iq_cali_done;
++	u32 sr_bhvr;
++};
++enum {
++	IQ_CALI_RUNNING,
++	IQ_CALI_OK,
++	IQ_CALI_FAILED
++};
++enum {
++	WD_SLEEP,
++	WD_BARKING,
++	WD_KICKED,
++	WD_MAX
++};
++void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args);
++void ssv6200_rx_process(struct work_struct *work);
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args);
++#else
++int ssv6200_rx(struct sk_buff *rx_skb, void *args);
++#endif
++void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args);
++void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args);
++int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug);
++void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *);
++int ssv6xxx_rf_disable(struct ssv_hw *sh);
++int ssv6xxx_rf_enable(struct ssv_hw *sh);
++int ssv6xxx_set_channel(struct ssv_softc *sc, int ch);
++#ifdef CONFIG_SSV_SMARTLINK
++int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch);
++int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept);
++int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept);
++#endif
++int ssv6xxx_tx_task(void *data);
++int ssv6xxx_rx_task(void *data);
++u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type);
++bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr);
++void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
++void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
++int ssv6xxx_update_decision_table(struct ssv_softc *sc);
++void ssv6xxx_ps_callback_func(unsigned long data);
++void ssv6xxx_enable_ps(struct ssv_softc *sc);
++void ssv6xxx_disable_ps(struct ssv_softc *sc);
++int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag);
++int ssv6xxx_skb_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc);
++int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta,
++			struct ssv_softc *sc);
++void ssv6200_sync_hw_key_sequence(struct ssv_softc *sc,
++				  struct ssv_sta_info *sta_info, bool bWrite);
++struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
++						 struct sk_buff *skb);
++struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc,
++					       u8 addr[6]);
++void ssv6xxx_foreach_sta(struct ssv_softc *sc,
++			 void (*sta_func)(struct ssv_softc *,
++					  struct ssv_sta_info *, void *),
++			 void *param);
++void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
++			     struct ssv_vif_info *vif_info,
++			     void (*sta_func)(struct ssv_softc *,
++					      struct ssv_vif_info *,
++					      struct ssv_sta_info *, void *),
++			     void *param);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
++				     ssize_t buf_size);
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/dev_tbl.h b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
+new file mode 100644
+index 000000000000..5c49d0bde6a6
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
+@@ -0,0 +1,141 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _DEV_TBL_H_
++#define _DEV_TBL_H_
++#include "ssv6200_configuration.h"
++#include "drv_comm.h"
++struct ssv6xxx_dev_table {
++	u32 address;
++	u32 data;
++};
++#define ssv6200_phy_tbl phy_setting
++#define ssv6200_rf_tbl asic_rf_setting
++#define ACTION_DO_NOTHING 0
++#define ACTION_UPDATE_NAV 1
++#define ACTION_RESET_NAV 2
++#define ACTION_SIGNAL_ACK 3
++#define FRAME_ACCEPT 0
++#define FRAME_DROP 1
++#define SET_DEC_TBL(_type,_mask,_action,_drop) \
++    (_type<<9| \
++    _mask <<3| \
++    _action<<1| \
++    _drop)
++u16 generic_deci_tbl[] = {
++	SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP),
++	SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x1a, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT),
++	SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP),
++	0,
++	0,
++	0,
++	SET_DEC_TBL(0x05, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x0b, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x01, 0x3d, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT),
++	SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP),
++	SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP),
++	SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP),
++	SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP),
++	0x2008,
++	0x1001,
++	0x0400,
++	0x0400,
++	0x2000,
++	0x800E,
++	0x0800,
++	0x0B88,
++	0x0800,
++};
++
++#define SET_PHY_INFO(_ctsdur,_ba_rate_idx,_ack_rate_idx,_llength_idx,_llength_enable) \
++         (_ctsdur<<16| \
++         _ba_rate_idx <<10| \
++         _ack_rate_idx<<4| \
++         _llength_idx<<1| \
++         _llength_enable)
++#define SET_PHY_L_LENGTH(_l_ba,_l_rts,_l_cts_ack) (_l_ba<<12|_l_rts<<6 |_l_cts_ack)
++static u32 phy_info_6051z[] = {
++	0x18000000, 0x18000100, 0x18000200, 0x18000300, 0x18000140,
++	0x18000240, 0x18000340, 0x0C000001, 0x0C000101, 0x0C000201,
++	0x0C000301, 0x18000401, 0x18000501, 0x18000601, 0x18000701,
++	0x0C030002, 0x0C030102, 0x0C030202, 0x18030302, 0x18030402,
++	0x18030502, 0x18030602, 0x1C030702, 0x0C030082, 0x0C030182,
++	0x0C030282, 0x18030382, 0x18030482, 0x18030582, 0x18030682,
++	0x1C030782, 0x0C030042, 0x0C030142, 0x0C030242, 0x18030342,
++	0x18030442, 0x18030542, 0x18030642, 0x1C030742
++};
++
++static u32 phy_info_tbl[] = {
++	0x0C000000, 0x0C000100, 0x0C000200, 0x0C000300, 0x0C000140,
++	0x0C000240, 0x0C000340, 0x00000001, 0x00000101, 0x00000201,
++	0x00000301, 0x0C000401, 0x0C000501, 0x0C000601, 0x0C000701,
++	0x00030002, 0x00030102, 0x00030202, 0x0C030302, 0x0C030402,
++	0x0C030502, 0x0C030602, 0x10030702, 0x00030082, 0x00030182,
++	0x00030282, 0x0C030382, 0x0C030482, 0x0C030582, 0x0C030682,
++	0x10030782, 0x00030042, 0x00030142, 0x00030242, 0x0C030342,
++	0x0C030442, 0x0C030542, 0x0C030642, 0x10030742,
++	SET_PHY_INFO(314, 0, 0, 0, 0),
++	SET_PHY_INFO(258, 0, 1, 0, 0),
++	SET_PHY_INFO(223, 0, 1, 0, 0),
++	SET_PHY_INFO(213, 0, 1, 0, 0),
++	SET_PHY_INFO(162, 0, 4, 0, 0),
++	SET_PHY_INFO(127, 0, 4, 0, 0),
++	SET_PHY_INFO(117, 0, 4, 0, 0),
++	SET_PHY_INFO(60, 7, 7, 0, 0),
++	SET_PHY_INFO(52, 7, 7, 0, 0),
++	SET_PHY_INFO(48, 9, 9, 0, 0),
++	SET_PHY_INFO(44, 9, 9, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(40, 11, 11, 0, 0),
++	SET_PHY_INFO(40, 11, 11, 0, 0),
++	SET_PHY_INFO(40, 11, 11, 0, 0),
++	SET_PHY_INFO(76, 7, 7, 0, 1),
++	SET_PHY_INFO(64, 9, 9, 1, 1),
++	SET_PHY_INFO(60, 9, 9, 2, 1),
++	SET_PHY_INFO(60, 11, 11, 3, 1),
++	SET_PHY_INFO(56, 11, 11, 4, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(76, 7, 7, 6, 1),
++	SET_PHY_INFO(64, 9, 9, 1, 1),
++	SET_PHY_INFO(60, 9, 9, 2, 1),
++	SET_PHY_INFO(60, 11, 11, 3, 1),
++	SET_PHY_INFO(56, 11, 11, 4, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(64, 7, 7, 0, 0),
++	SET_PHY_INFO(52, 9, 9, 0, 0),
++	SET_PHY_INFO(48, 9, 9, 0, 0),
++	SET_PHY_INFO(48, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_L_LENGTH(50, 38, 35),
++	SET_PHY_L_LENGTH(35, 29, 26),
++	SET_PHY_L_LENGTH(29, 26, 23),
++	SET_PHY_L_LENGTH(26, 23, 23),
++	SET_PHY_L_LENGTH(23, 23, 20),
++	SET_PHY_L_LENGTH(23, 20, 20),
++	SET_PHY_L_LENGTH(47, 38, 35),
++	SET_PHY_L_LENGTH(0, 0, 0),
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/drv_comm.h b/drivers/net/wireless/ssv6051/smac/drv_comm.h
+new file mode 100644
+index 000000000000..f04fbae004c3
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/drv_comm.h
+@@ -0,0 +1,61 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _DRV_COMM_H_
++#define _DRV_COMM_H_
++#define PHY_INFO_TBL1_SIZE 39
++#define PHY_INFO_TBL2_SIZE 39
++#define PHY_INFO_TBL3_SIZE 8
++#define ampdu_fw_rate_info_status_no_use BIT(0)
++#define ampdu_fw_rate_info_status_in_use BIT(1)
++#define ampdu_fw_rate_info_status_reset BIT(2)
++#define SSV_NUM_STA 8
++#define SSV_NUM_VIF 2
++#define SECURITY_KEY_LEN (32)
++enum SSV_CIPHER_E {
++	SSV_CIPHER_NONE,
++	SSV_CIPHER_WEP40,
++	SSV_CIPHER_WEP104,
++	SSV_CIPHER_TKIP,
++	SSV_CIPHER_CCMP,
++	SSV_CIPHER_SMS4,
++	SSV_CIPHER_INVALID = (-1)
++};
++#define ME_NONE 0
++#define ME_WEP40 1
++#define ME_WEP104 2
++#define ME_TKIP 3
++#define ME_CCMP 4
++#define ME_SMS4 5
++struct ssv6xxx_hw_key {
++	u8 key[SECURITY_KEY_LEN];
++	u32 tx_pn_l;
++	u32 tx_pn_h;
++	u32 rx_pn_l;
++	u32 rx_pn_h;
++} __attribute__((packed));
++struct ssv6xxx_hw_sta_key {
++	u8 pair_key_idx:4;
++	u8 group_key_idx:4;
++	u8 valid;
++	u8 reserve[2];
++	struct ssv6xxx_hw_key pair;
++} __attribute__((packed));
++struct ssv6xxx_hw_sec {
++	struct ssv6xxx_hw_key group_key[3];
++	struct ssv6xxx_hw_sta_key sta_key[8];
++} __attribute__((packed));
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/efuse.c b/drivers/net/wireless/ssv6051/smac/efuse.c
+new file mode 100644
+index 000000000000..9a1f3f5488f2
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/efuse.c
+@@ -0,0 +1,334 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/etherdevice.h>
++#include <ssv6200.h>
++#include "efuse.h"
++
++struct file *openFile(char *path, int flag, int mode)
++{
++	struct file *fp = NULL;
++	fp = filp_open(path, flag, 0);
++	if (IS_ERR(fp))
++		return NULL;
++	else
++		return fp;
++}
++
++int readFile(struct file *fp, char *buf, int readlen)
++{
++	if (fp->f_op && fp->f_op->read)
++		return fp->f_op->read(fp, buf, readlen, &fp->f_pos);
++	else
++		return -1;
++}
++
++int closeFile(struct file *fp)
++{
++	filp_close(fp, NULL);
++	return 0;
++}
++
++void initKernelEnv(void)
++{
++}
++
++void parseMac(char *mac, u_int8_t addr[])
++{
++	long b;
++	int i;
++	for (i = 0; i < 6; i++) {
++		b = simple_strtol(mac + (3 * i), (char **)NULL, 16);
++		addr[i] = (char)b;
++	}
++}
++
++static int readfile_mac(u8 * path, u8 * mac_addr)
++{
++	char buf[128];
++	struct file *fp = NULL;
++	int ret = 0;
++	fp = openFile(path, O_RDONLY, 0);
++	if (fp != NULL) {
++		initKernelEnv();
++		memset(buf, 0, 128);
++		if ((ret = readFile(fp, buf, 128)) > 0) {
++			parseMac(buf, (uint8_t *) mac_addr);
++		} else
++			pr_err("read file error %d=[%s]\n", ret, path);
++		closeFile(fp);
++	} else
++		pr_err("Read open File fail[%s]!!!! \n", path);
++	return ret;
++}
++
++static int write_mac_to_file(u8 * mac_path, u8 * mac_addr)
++{
++	char buf[128];
++	struct file *fp = NULL;
++	int ret = 0, len;
++	fp = openFile(mac_path, O_WRONLY | O_CREAT, 0640);
++	if (fp != NULL) {
++		initKernelEnv();
++		memset(buf, 0, 128);
++		sprintf(buf, "%x:%x:%x:%x:%x:%x", mac_addr[0], mac_addr[1],
++			mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
++		len = strlen(buf) + 1;
++		fp->f_op->write(fp, (char *)buf, len, &fp->f_pos);
++		closeFile(fp);
++	} else
++		pr_err("Write open File fail!!!![%s] \n", mac_path);
++	return ret;
++}
++
++static struct efuse_map SSV_EFUSE_ITEM_TABLE[] = {
++	{4, 0, 0},
++	{4, 8, 0},
++	{4, 8, 0},
++	{4, 48, 0},
++	{4, 8, 0},
++	{4, 8, 0},
++	{4, 8, 0},
++};
++
++static u8 read_efuse(struct ssv_hw *sh, u8 * pbuf)
++{
++	extern struct ssv6xxx_cfg ssv_cfg;
++	u32 val, i;
++	u32 *temp = (u32 *) pbuf;
++	SMAC_REG_WRITE(sh, 0xC0000328, 0x11);
++	SMAC_REG_WRITE(sh, SSV_EFUSE_ID_READ_SWITCH, 0x1);
++	SMAC_REG_READ(sh, SSV_EFUSE_ID_RAW_DATA_BASE, &val);
++	ssv_cfg.chip_identity = val;
++	SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH, 0x1);
++	SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE, &val);
++	if (val == 0x00) {
++		return 0;
++	}
++	for (i = 0; i < (EFUSE_MAX_SECTION_MAP); i++) {
++		SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH + i * 4, 0x1);
++		SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE + i * 4, &val);
++		*temp++ = val;
++	}
++	SMAC_REG_WRITE(sh, 0xC0000328, 0x1800000a);
++	return 1;
++}
++
++static u16 parser_efuse(u8 * pbuf, u8 * mac_addr)
++{
++	u8 *rtemp8, idx = 0;
++	u16 shift = 0, i;
++	u16 efuse_real_content_len = 0;
++	rtemp8 = pbuf;
++	if (*rtemp8 == 0x00) {
++		return efuse_real_content_len;
++	}
++	do {
++		idx = (*(rtemp8) >> shift) & 0xf;
++		switch (idx) {
++		case EFUSE_R_CALIBRATION_RESULT:
++		case EFUSE_CRYSTAL_FREQUENCY_OFFSET:
++		case EFUSE_TX_POWER_INDEX_1:
++		case EFUSE_TX_POWER_INDEX_2:
++		case EFUSE_SAR_RESULT:
++			if (shift) {
++				rtemp8++;
++				SSV_EFUSE_ITEM_TABLE[idx].value =
++				    (u16) ((u8) (*((u16 *) rtemp8)) &
++					   ((1 <<
++					     SSV_EFUSE_ITEM_TABLE
++					     [idx].byte_cnts) - 1));
++			} else {
++				SSV_EFUSE_ITEM_TABLE[idx].value =
++				    (u16) ((u8) (*((u16 *) rtemp8) >> 4) &
++					   ((1 <<
++					     SSV_EFUSE_ITEM_TABLE
++					     [idx].byte_cnts) - 1));
++			}
++			efuse_real_content_len +=
++			    (SSV_EFUSE_ITEM_TABLE[idx].offset +
++			     SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
++			break;
++		case EFUSE_MAC:
++			if (shift) {
++				rtemp8++;
++				memcpy(mac_addr, rtemp8, 6);
++			} else {
++				for (i = 0; i < 6; i++) {
++					mac_addr[i] =
++					    (u16) (*((u16 *) rtemp8) >> 4) &
++					    0xff;
++					rtemp8++;
++				}
++			}
++			efuse_real_content_len +=
++			    (SSV_EFUSE_ITEM_TABLE[idx].offset +
++			     SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
++			break;
++		default:
++			idx = 0;
++			break;
++		}
++		shift = efuse_real_content_len % 8;
++		rtemp8 = &pbuf[efuse_real_content_len / 8];
++	} while (idx != 0);
++	return efuse_real_content_len;
++}
++
++void addr_increase_copy(u8 * dst, u8 * src)
++{
++	u8 *a = (u8 *) dst;
++	const u8 *b = (const u8 *)src;
++	a[0] = b[0];
++	a[1] = b[1];
++	a[2] = b[2];
++	a[3] = b[3];
++	a[4] = b[4];
++	if (b[5] & 0x1)
++		a[5] = b[5] - 1;
++	else
++		a[5] = b[5] + 1;
++}
++
++static u8 key_char2num(u8 ch)
++{
++	if ((ch >= '0') && (ch <= '9'))
++		return ch - '0';
++	else if ((ch >= 'a') && (ch <= 'f'))
++		return ch - 'a' + 10;
++	else if ((ch >= 'A') && (ch <= 'F'))
++		return ch - 'A' + 10;
++	else
++		return 0xff;
++}
++
++u8 key_2char2num(u8 hch, u8 lch)
++{
++	return ((key_char2num(hch) << 4) | key_char2num(lch));
++}
++
++extern struct ssv6xxx_cfg ssv_cfg;
++extern char *ssv_initmac;
++void efuse_read_all_map(struct ssv_hw *sh)
++{
++	u8 mac[ETH_ALEN] = { 0 };
++	int jj, kk;
++	u8 efuse_mapping_table[EFUSE_HWSET_MAX_SIZE / 8];
++#ifndef CONFIG_SSV_RANDOM_MAC
++	u8 pseudo_mac0[ETH_ALEN] = { 0x00, 0x33, 0x33, 0x33, 0x33, 0x33 };
++#endif
++	u8 rom_mac0[ETH_ALEN];
++	memset(rom_mac0, 0x00, ETH_ALEN);
++	memset(efuse_mapping_table, 0x00, EFUSE_HWSET_MAX_SIZE / 8);
++	read_efuse(sh, efuse_mapping_table);
++	parser_efuse(efuse_mapping_table, rom_mac0);
++	ssv_cfg.r_calbration_result =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_R_CALIBRATION_RESULT].value;
++	ssv_cfg.sar_result = (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_SAR_RESULT].value;
++	ssv_cfg.crystal_frequency_offset =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_CRYSTAL_FREQUENCY_OFFSET].value;
++	ssv_cfg.tx_power_index_1 =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_1].value;
++	ssv_cfg.tx_power_index_2 =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_2].value;
++	if (!is_valid_ether_addr(&sh->cfg.maddr[0][0])) {
++		if (!sh->cfg.ignore_efuse_mac) {
++			if (is_valid_ether_addr(rom_mac0)) {
++				dev_info(sh->sc->dev, "Using MAC address from e-fuse\n");
++				memcpy(&sh->cfg.maddr[0][0], rom_mac0,
++				       ETH_ALEN);
++				addr_increase_copy(&sh->cfg.maddr[1][0],
++						   rom_mac0);
++				goto Done;
++			}
++		}
++		if (ssv_initmac != NULL) {
++			for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) {
++				mac[jj] =
++				    key_2char2num(ssv_initmac[kk],
++						  ssv_initmac[kk + 1]);
++			}
++			if (is_valid_ether_addr(mac)) {
++				dev_info(sh->sc->dev, "Using MAC address from module option\n");
++				memcpy(&sh->cfg.maddr[0][0], mac, ETH_ALEN);
++				addr_increase_copy(&sh->cfg.maddr[1][0], mac);
++				goto Done;
++			}
++		}
++		if (sh->cfg.mac_address_path[0] != 0x00) {
++			if ((readfile_mac
++			     (sh->cfg.mac_address_path, &sh->cfg.maddr[0][0]))
++			    && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
++				dev_info
++				    (sh->sc->dev, "Using MAC address from configuration file\n");
++				addr_increase_copy(&sh->cfg.maddr[1][0],
++						   &sh->cfg.maddr[0][0]);
++				goto Done;
++			}
++		}
++		switch (sh->cfg.mac_address_mode) {
++		case 1:
++			get_random_bytes(&sh->cfg.maddr[0][0], ETH_ALEN);
++			sh->cfg.maddr[0][0] = sh->cfg.maddr[0][0] & 0xF0;
++			addr_increase_copy(&sh->cfg.maddr[1][0],
++					   &sh->cfg.maddr[0][0]);
++			break;
++		case 2:
++			if ((readfile_mac
++			     (sh->cfg.mac_output_path, &sh->cfg.maddr[0][0]))
++			    && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
++				addr_increase_copy(&sh->cfg.maddr[1][0],
++						   &sh->cfg.maddr[0][0]);
++			} else {
++				{
++					get_random_bytes(&sh->cfg.maddr[0][0],
++							 ETH_ALEN);
++					sh->cfg.maddr[0][0] =
++					    sh->cfg.maddr[0][0] & 0xF0;
++					addr_increase_copy(&sh->cfg.maddr[1][0],
++							   &sh->
++							   cfg.maddr[0][0]);
++					if (sh->cfg.mac_output_path[0] != 0x00)
++						write_mac_to_file(sh->
++								  cfg.mac_output_path,
++								  &sh->
++								  cfg.maddr[0]
++								  [0]);
++				}
++			}
++			break;
++		default:
++			memcpy(&sh->cfg.maddr[0][0], pseudo_mac0, ETH_ALEN);
++			addr_increase_copy(&sh->cfg.maddr[1][0], pseudo_mac0);
++			break;
++		}
++		dev_info(sh->sc->dev, "MAC address from Software MAC mode[%d]\n",
++			sh->cfg.mac_address_mode);
++	}
++ Done:
++	dev_info(sh->sc->dev, "Chip identity from efuse: %08x\n", ssv_cfg.chip_identity);
++	dev_dbg(sh->sc->dev, "r_calbration_result- %x\n", ssv_cfg.r_calbration_result);
++	dev_dbg(sh->sc->dev, "sar_result- %x\n", ssv_cfg.sar_result);
++	dev_dbg(sh->sc->dev, "crystal_frequency_offset- %x\n",
++		 ssv_cfg.crystal_frequency_offset);
++	dev_dbg(sh->sc->dev, "tx_power_index_1- %x\n", ssv_cfg.tx_power_index_1);
++	dev_dbg(sh->sc->dev, "tx_power_index_2- %x\n", ssv_cfg.tx_power_index_2);
++	dev_dbg(sh->sc->dev, "MAC address - %pM\n", rom_mac0);
++	sh->cfg.crystal_frequency_offset = ssv_cfg.crystal_frequency_offset;
++	sh->cfg.tx_power_index_1 = ssv_cfg.tx_power_index_1;
++	sh->cfg.tx_power_index_2 = ssv_cfg.tx_power_index_2;
++	sh->cfg.chip_identity = ssv_cfg.chip_identity;
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/efuse.h b/drivers/net/wireless/ssv6051/smac/efuse.h
+new file mode 100644
+index 000000000000..c25280c5abad
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/efuse.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_EFUSE_H_
++#define _SSV_EFUSE_H_
++#include "dev.h"
++struct efuse_map {
++	u8 offset;
++	u8 byte_cnts;
++	u16 value;
++};
++enum efuse_data_item {
++	EFUSE_R_CALIBRATION_RESULT = 1,
++	EFUSE_SAR_RESULT,
++	EFUSE_MAC,
++	EFUSE_CRYSTAL_FREQUENCY_OFFSET,
++	EFUSE_TX_POWER_INDEX_1,
++	EFUSE_TX_POWER_INDEX_2
++};
++#define EFUSE_HWSET_MAX_SIZE (256-32)
++#define EFUSE_MAX_SECTION_MAP (EFUSE_HWSET_MAX_SIZE>>5)
++#define SSV_EFUSE_ID_READ_SWITCH 0xC2000128
++#define SSV_EFUSE_ID_RAW_DATA_BASE 0xC200014C
++#define SSV_EFUSE_READ_SWITCH 0xC200012C
++#define SSV_EFUSE_RAW_DATA_BASE 0xC2000150
++void efuse_read_all_map(struct ssv_hw *sh);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/init.c b/drivers/net/wireless/ssv6051/smac/init.c
+new file mode 100644
+index 000000000000..592c52a28381
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/init.c
+@@ -0,0 +1,1347 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/nl80211.h>
++#include <linux/kthread.h>
++#include <linux/etherdevice.h>
++#include <linux/version.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
++#include <crypto/hash.h>
++#else
++#include <linux/crypto.h>
++#endif
++#include <ssv6200.h>
++#include <hci/hctrl.h>
++#include <ssv_firmware_version.h>
++#include "dev_tbl.h"
++#include "dev.h"
++#include "lib.h"
++#include "ssv_rc.h"
++#include "ap.h"
++#include "efuse.h"
++#include "sar.h"
++#include "ssv_cfgvendor.h"
++
++#include "linux_80211.h"
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++#include "ssv6xxx_debugfs.h"
++#endif
++
++#define WIFI_FIRMWARE_NAME "ssv6051-sw.bin"
++static const struct ieee80211_iface_limit ssv6xxx_p2p_limits[] = {
++	{
++	 .max = 2,
++	 .types = BIT(NL80211_IFTYPE_STATION),
++	 },
++	{
++	 .max = 1,
++	 .types = BIT(NL80211_IFTYPE_P2P_GO) |
++	 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_AP),
++	 },
++};
++
++static const struct ieee80211_iface_combination
++ ssv6xxx_iface_combinations_p2p[] = {
++	{.num_different_channels = 1,
++	 .max_interfaces = SSV6200_MAX_VIF,
++	 .beacon_int_infra_match = true,
++	 .limits = ssv6xxx_p2p_limits,
++	 .n_limits = ARRAY_SIZE(ssv6xxx_p2p_limits),
++	 },
++};
++
++#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
++    (((a) & 0xff00ff00) >> 8))
++#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
++#define CHAN2G(_freq,_idx) { \
++    .band = INDEX_80211_BAND_2GHZ, \
++    .center_freq = (_freq), \
++    .hw_value = (_idx), \
++    .max_power = 20, \
++}
++#ifndef WLAN_CIPHER_SUITE_SMS4
++#define WLAN_CIPHER_SUITE_SMS4 0x00147201
++#endif
++#define SHPCHECK(__hw_rate,__flags) \
++    ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate +3 ) : 0)
++#define RATE(_bitrate,_hw_rate,_flags) { \
++    .bitrate = (_bitrate), \
++    .flags = (_flags), \
++    .hw_value = (_hw_rate), \
++    .hw_value_short = SHPCHECK(_hw_rate,_flags) \
++}
++extern struct ssv6xxx_cfg ssv_cfg;
++static const struct ieee80211_channel ssv6200_2ghz_chantable[] = {
++	CHAN2G(2412, 1),
++	CHAN2G(2417, 2),
++	CHAN2G(2422, 3),
++	CHAN2G(2427, 4),
++	CHAN2G(2432, 5),
++	CHAN2G(2437, 6),
++	CHAN2G(2442, 7),
++	CHAN2G(2447, 8),
++	CHAN2G(2452, 9),
++	CHAN2G(2457, 10),
++	CHAN2G(2462, 11),
++	CHAN2G(2467, 12),
++	CHAN2G(2472, 13),
++	CHAN2G(2484, 14),
++};
++
++static struct ieee80211_rate ssv6200_legacy_rates[] = {
++	RATE(10, 0x00, 0),
++	RATE(20, 0x01, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATE(55, 0x02, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATE(110, 0x03, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATE(60, 0x07, 0),
++	RATE(90, 0x08, 0),
++	RATE(120, 0x09, 0),
++	RATE(180, 0x0a, 0),
++	RATE(240, 0x0b, 0),
++	RATE(360, 0x0c, 0),
++	RATE(480, 0x0d, 0),
++	RATE(540, 0x0e, 0),
++};
++
++struct ssv6xxx_ch_cfg ch_cfg_z[] = {
++	{ADR_ABB_REGISTER_1, 0, 0x151559fc},
++	{ADR_LDO_REGISTER, 0, 0x00eb7c1c},
++	{ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
++};
++
++struct ssv6xxx_ch_cfg ch_cfg_p[] = {
++	{ADR_ABB_REGISTER_1, 0, 0x151559fc},
++	{ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
++};
++
++int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int ret = 0;
++	dev_dbg(sh->sc->dev, "# Do init_cali (iq)\n");
++	skb =
++	    ssv_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE +
++			  RF_SETTING_SIZE);
++	if (skb == NULL) {
++		dev_err(sh->sc->dev, "init ssv6xxx_do_iq_calib failure\n");
++		return (-1);
++	}
++	if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
++	    (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
++		dev_warn(sh->sc->dev, "wrong RF or PHY table size\n");
++		WARN_ON(1);
++		return (-1);
++	}
++	skb->data_len =
++	    HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
++	host_cmd->len = skb->data_len;
++	p_cfg->phy_tbl_size = PHY_SETTING_SIZE;
++	p_cfg->rf_tbl_size = RF_SETTING_SIZE;
++	memcpy(host_cmd->dat32, p_cfg, IQK_CFG_LEN);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, ssv6200_rf_tbl,
++	       RF_SETTING_SIZE);
++	sh->hci.hci_ops->hci_send_cmd(skb);
++	ssv_skb_free(skb);
++	{
++		u32 timeout;
++		sh->sc->iq_cali_done = IQ_CALI_RUNNING;
++		set_current_state(TASK_INTERRUPTIBLE);
++		timeout = wait_event_interruptible_timeout(sh->sc->fw_wait_q,
++							   sh->sc->iq_cali_done,
++							   msecs_to_jiffies
++							   (500));
++		set_current_state(TASK_RUNNING);
++		if (timeout == 0)
++			return -ETIME;
++		if (sh->sc->iq_cali_done != IQ_CALI_OK)
++			return (-1);
++	}
++	return ret;
++}
++
++#define HT_CAP_RX_STBC_ONE_STREAM 0x1
++#if defined(CONFIG_PM)
++static const struct wiphy_wowlan_support wowlan_support = {
++#ifdef SSV_WAKEUP_HOST
++	.flags = WIPHY_WOWLAN_ANY,
++#else
++	.flags = WIPHY_WOWLAN_DISCONNECT,
++#endif
++	.n_patterns = 0,
++	.pattern_max_len = 0,
++	.pattern_min_len = 0,
++	.max_pkt_offset = 0,
++};
++#endif
++static void ssv6xxx_set_80211_hw_capab(struct ssv_softc *sc)
++{
++	struct ieee80211_hw *hw = sc->hw;
++	struct ssv_hw *sh = sc->sh;
++	struct ieee80211_sta_ht_cap *ht_info;
++	ieee80211_hw_set(hw, SIGNAL_DBM);
++	hw->rate_control_algorithm = "ssv6xxx_rate_control";
++	//hw->rate_control_algorithm = NULL; // NULL selects default
++	ht_info = &sc->sbands[INDEX_80211_BAND_2GHZ].ht_cap;
++	ampdu_db_log("sh->cfg.hw_caps = 0x%x\n", sh->cfg.hw_caps);
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_HT) {
++		if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX) {
++			ieee80211_hw_set(hw, AMPDU_AGGREGATION);
++			ampdu_db_log("set IEEE80211_HW_AMPDU_AGGREGATION(%d)\n",
++				     ieee80211_hw_check(hw, AMPDU_AGGREGATION));
++		}
++		ht_info->cap = IEEE80211_HT_CAP_SM_PS;
++		if (sh->cfg.hw_caps & SSV6200_HW_CAP_GF) {
++			ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
++			ht_info->cap |=
++			    HT_CAP_RX_STBC_ONE_STREAM <<
++			    IEEE80211_HT_CAP_RX_STBC_SHIFT;
++		}
++		if (sh->cfg.hw_caps & SSV6200_HT_CAP_SGI_20)
++			ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
++		ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_32K;
++		ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
++		memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
++		ht_info->mcs.rx_mask[0] = 0xff;
++		ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
++		ht_info->mcs.rx_highest = cpu_to_le16(SSV6200_RX_HIGHEST_RATE);
++		ht_info->ht_supported = true;
++	}
++	hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
++		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_CLIENT);
++		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_GO);
++		hw->wiphy->iface_combinations = ssv6xxx_iface_combinations_p2p;
++		hw->wiphy->n_iface_combinations =
++		    ARRAY_SIZE(ssv6xxx_iface_combinations_p2p);
++	}
++	hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_AP) {
++		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
++		hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
++	}
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_TDLS) {
++		hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
++		hw->wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
++		dev_info(sc->dev, "TDLS function enabled in sta.cfg\n");
++	}
++	hw->queues = 4;
++	hw->max_rates = 4;
++	hw->max_listen_interval = 1;
++	hw->max_rate_tries = HW_MAX_RATE_TRIES;
++	hw->extra_tx_headroom = TXPB_OFFSET + AMPDU_DELIMITER_LEN;
++	if (sizeof(struct ampdu_hdr_st) > SSV_SKB_info_size)
++		hw->extra_tx_headroom += sizeof(struct ampdu_hdr_st);
++	else
++		hw->extra_tx_headroom += SSV_SKB_info_size;
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
++		hw->wiphy->bands[INDEX_80211_BAND_2GHZ] =
++		    &sc->sbands[INDEX_80211_BAND_2GHZ];
++	}
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)
++#ifdef PREFER_RX
++		hw->max_rx_aggregation_subframes = 64;
++#else
++		hw->max_rx_aggregation_subframes = 16;
++#endif
++	else
++		hw->max_rx_aggregation_subframes = 12;
++	hw->max_tx_aggregation_subframes = 64;
++	hw->sta_data_size = sizeof(struct ssv_sta_priv_data);
++	hw->vif_data_size = sizeof(struct ssv_vif_priv_data);
++	memcpy(sh->maddr[0].addr, &sh->cfg.maddr[0][0], ETH_ALEN);
++	hw->wiphy->addresses = sh->maddr;
++	hw->wiphy->n_addresses = 1;
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
++		int i;
++		for (i = 1; i < SSV6200_MAX_HW_MAC_ADDR; i++) {
++			memcpy(sh->maddr[i].addr, sh->maddr[i - 1].addr,
++			       ETH_ALEN);
++			sh->maddr[i].addr[5]++;
++			hw->wiphy->n_addresses++;
++		}
++	}
++	if (!is_zero_ether_addr(sh->cfg.maddr[1])) {
++		memcpy(sh->maddr[1].addr, sh->cfg.maddr[1], ETH_ALEN);
++		if (hw->wiphy->n_addresses < 2)
++			hw->wiphy->n_addresses = 2;
++	}
++#if defined(CONFIG_PM)
++	hw->wiphy->wowlan = &wowlan_support;
++#endif
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) && defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
++    {
++        int err = 0;
++        struct ssv_softc *softc = (struct ssv_softc *)hw->priv;
++        if (softc)
++        {
++            set_wiphy_dev(hw->wiphy, softc->dev);
++            *((struct ssv_softc **)wiphy_priv(hw->wiphy)) = softc;
++        }
++       	dev_dbg(sc->dev, "Registering Vendor80211\n");
++       	err = ssv_cfgvendor_attach(hw->wiphy);
++       	if (unlikely(err < 0)) {
++       		dev_err(sc->dev, "Couldn not attach vendor commands (%d)\n", err);
++       	}
++    }
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
++}
++
++void ssv6xxx_watchdog_restart_hw(struct ssv_softc *sc)
++{
++	dev_dbg(sc->dev, "%s()\n", __FUNCTION__);
++	sc->restart_counter++;
++	sc->force_triger_reset = true;
++	sc->beacon_info[0].pubf_addr = 0x00;
++	sc->beacon_info[1].pubf_addr = 0x00;
++	ieee80211_restart_hw(sc->hw);
++}
++
++extern struct rssi_res_st rssi_res;
++void ssv6200_watchdog_timeout(struct timer_list *t)
++{
++	static u32 count = 0;
++	struct rssi_res_st *rssi_tmp0 = NULL, *rssi_tmp1 = NULL;
++	struct ssv_softc *sc = from_timer(sc, t, watchdog_timeout);
++	if (sc->watchdog_flag == WD_BARKING) {
++		ssv6xxx_watchdog_restart_hw(sc);
++		mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++		return;
++	}
++	if (sc->watchdog_flag != WD_SLEEP)
++		sc->watchdog_flag = WD_BARKING;
++	count++;
++	if (count == 6) {
++		count = 0;
++		if (list_empty(&rssi_res.rssi_list)) {
++			return;
++		}
++		list_for_each_entry_safe(rssi_tmp0, rssi_tmp1,
++					 &rssi_res.rssi_list, rssi_list) {
++			if (rssi_tmp0->timeout) {
++				list_del_rcu(&rssi_tmp0->rssi_list);
++				kfree(rssi_tmp0);
++			}
++		}
++	}
++	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++	return;
++}
++
++static void ssv6xxx_preload_sw_cipher(void)
++{
++}
++
++static int ssv6xxx_init_softc(struct ssv_softc *sc)
++{
++	void *channels;
++	int ret = 0;
++	sc->sc_flags = SC_OP_INVALID;
++	mutex_init(&sc->mutex);
++	mutex_init(&sc->mem_mutex);
++	sc->config_wq = create_singlethread_workqueue("ssv6xxx_cong_wq");
++	sc->thermal_wq = create_singlethread_workqueue("ssv6xxx_thermal_wq");
++	INIT_DELAYED_WORK(&sc->thermal_monitor_work, thermal_monitor);
++	INIT_WORK(&sc->set_tim_work, ssv6200_set_tim_work);
++	INIT_WORK(&sc->bcast_start_work, ssv6200_bcast_start_work);
++	INIT_DELAYED_WORK(&sc->bcast_stop_work, ssv6200_bcast_stop_work);
++	INIT_DELAYED_WORK(&sc->bcast_tx_work, ssv6200_bcast_tx_work);
++	INIT_WORK(&sc->set_ampdu_rx_add_work, ssv6xxx_set_ampdu_rx_add_work);
++	INIT_WORK(&sc->set_ampdu_rx_del_work, ssv6xxx_set_ampdu_rx_del_work);
++	sc->mac_deci_tbl = sta_deci_tbl;
++	memset((void *)&sc->tx, 0, sizeof(struct ssv_tx));
++	sc->tx.hw_txqid[WMM_AC_VO] = 3;
++	sc->tx.ac_txqid[3] = WMM_AC_VO;
++	sc->tx.hw_txqid[WMM_AC_VI] = 2;
++	sc->tx.ac_txqid[2] = WMM_AC_VI;
++	sc->tx.hw_txqid[WMM_AC_BE] = 1;
++	sc->tx.ac_txqid[1] = WMM_AC_BE;
++	sc->tx.hw_txqid[WMM_AC_BK] = 0;
++	sc->tx.ac_txqid[0] = WMM_AC_BK;
++	INIT_LIST_HEAD(&sc->tx.ampdu_tx_que);
++	spin_lock_init(&sc->tx.ampdu_tx_que_lock);
++	memset((void *)&sc->rx, 0, sizeof(struct ssv_rx));
++	spin_lock_init(&sc->rx.rxq_lock);
++	skb_queue_head_init(&sc->rx.rxq_head);
++	sc->rx.rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++	if (sc->rx.rx_buf == NULL)
++		return -ENOMEM;
++	memset(&sc->bcast_txq, 0, sizeof(struct ssv6xxx_bcast_txq));
++	spin_lock_init(&sc->bcast_txq.txq_lock);
++	skb_queue_head_init(&sc->bcast_txq.qhead);
++	spin_lock_init(&sc->ps_state_lock);
++#ifdef CONFIG_P2P_NOA
++	spin_lock_init(&sc->p2p_noa.p2p_config_lock);
++#endif
++	if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
++		channels = kmemdup(ssv6200_2ghz_chantable,
++				   sizeof(ssv6200_2ghz_chantable), GFP_KERNEL);
++		if (!channels) {
++			kfree(sc->rx.rx_buf);
++			return -ENOMEM;
++		}
++		sc->sbands[INDEX_80211_BAND_2GHZ].channels = channels;
++		sc->sbands[INDEX_80211_BAND_2GHZ].band = INDEX_80211_BAND_2GHZ;
++		sc->sbands[INDEX_80211_BAND_2GHZ].n_channels =
++		    ARRAY_SIZE(ssv6200_2ghz_chantable);
++		sc->sbands[INDEX_80211_BAND_2GHZ].bitrates =
++		    ssv6200_legacy_rates;
++		sc->sbands[INDEX_80211_BAND_2GHZ].n_bitrates =
++		    ARRAY_SIZE(ssv6200_legacy_rates);
++	}
++	sc->cur_channel = NULL;
++	sc->hw_chan = (-1);
++	ssv6xxx_set_80211_hw_capab(sc);
++	ret = ssv6xxx_rate_control_register();
++	if (ret != 0) {
++		dev_warn(sc->dev, "%s(): Failed to register rc algorithm.\n",__FUNCTION__);
++	}
++	init_waitqueue_head(&sc->tx_wait_q);
++	sc->tx_wait_q_woken = 0;
++	skb_queue_head_init(&sc->tx_skb_q);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	sc->max_tx_skb_q_len = 0;
++#endif
++	sc->tx_task = kthread_run(ssv6xxx_tx_task, sc, "ssv6xxx_tx_task");
++	sc->tx_q_empty = false;
++	skb_queue_head_init(&sc->tx_done_q);
++	init_waitqueue_head(&sc->rx_wait_q);
++	sc->rx_wait_q_woken = 0;
++	skb_queue_head_init(&sc->rx_skb_q);
++	sc->rx_task = kthread_run(ssv6xxx_rx_task, sc, "ssv6xxx_rx_task");
++	ssv6xxx_preload_sw_cipher();
++	timer_setup(&sc->watchdog_timeout, ssv6200_watchdog_timeout, 0);
++	init_waitqueue_head(&sc->fw_wait_q);
++	INIT_LIST_HEAD(&rssi_res.rssi_list);
++	rssi_res.rssi = 0;
++	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++	//add_timer(&sc->watchdog_timeout);
++	//if(get_flash_info(sc) == 1)
++	sc->is_sar_enabled = get_flash_info(sc);
++	if (sc->is_sar_enabled)
++		queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
++				   THERMAL_MONITOR_TIME);
++	//schedule_delayed_work(&sc->thermal_monitor_work, THERMAL_MONITOR_TIME);
++	return ret;
++}
++
++static int ssv6xxx_deinit_softc(struct ssv_softc *sc)
++{
++	void *channels;
++	struct sk_buff *skb;
++	u8 remain_size;
++	dev_dbg(sc->dev, "%s():\n", __FUNCTION__);
++	if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
++		channels = sc->sbands[INDEX_80211_BAND_2GHZ].channels;
++		kfree(channels);
++	}
++	ssv_skb_free(sc->rx.rx_buf);
++	sc->rx.rx_buf = NULL;
++	ssv6xxx_rate_control_unregister();
++	cancel_delayed_work_sync(&sc->bcast_tx_work);
++	//ssv6xxx_watchdog_controller(sc->sh ,(u8)SSV6XXX_HOST_CMD_WATCHDOG_STOP);
++	del_timer_sync(&sc->watchdog_timeout);
++	cancel_delayed_work(&sc->thermal_monitor_work);
++	sc->ps_status = PWRSV_PREPARE;
++	flush_workqueue(sc->thermal_wq);
++	destroy_workqueue(sc->thermal_wq);
++	do {
++		skb = ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
++		if (skb)
++			ssv6xxx_txbuf_free_skb(skb, (void *)sc);
++		else
++			break;
++	} while (remain_size);
++	if (sc->tx_task != NULL) {
++		dev_dbg(sc->dev, "Stopping TX task...\n");
++		kthread_stop(sc->tx_task);
++		sc->tx_task = NULL;
++		dev_dbg(sc->dev, "Stopped TX task.\n");
++	}
++	if (sc->rx_task != NULL) {
++		dev_dbg(sc->dev, "Stopping RX task...\n");
++		kthread_stop(sc->rx_task);
++		sc->rx_task = NULL;
++		dev_dbg(sc->dev, "Stopped RX task.\n");
++	}
++	destroy_workqueue(sc->config_wq);
++	return 0;
++}
++
++static void ssv6xxx_hw_set_replay_ignore(struct ssv_hw *sh, u8 ignore)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp = temp & SCRT_RPLY_IGNORE_I_MSK;
++	temp |= (ignore << SCRT_RPLY_IGNORE_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++}
++
++int ssv6xxx_init_mac(struct ssv_hw *sh)
++{
++	struct ssv_softc *sc = sh->sc;
++	int i = 0, ret = 0;
++
++	u32 *ptr, id_len, regval, temp[0x8];
++	char *chip_id = sh->chip_id;
++	SMAC_REG_READ(sh, ADR_IC_TIME_TAG_1, &regval);
++	sh->chip_tag = ((u64) regval << 32);
++	SMAC_REG_READ(sh, ADR_IC_TIME_TAG_0, &regval);
++	sh->chip_tag |= (regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_3, &regval);
++	*((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_2, &regval);
++	*((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_1, &regval);
++	*((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_0, &regval);
++	*((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
++	chip_id[12 + sizeof(u32)] = 0;
++	dev_info(sh->sc->dev, "chip id: %s, tag: %llx\n", chip_id, sh->chip_tag);
++	if (sc->ps_status == PWRSV_ENABLE) {
++		SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
++			       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
++			       (M_ENG_HWHCI << 8));
++		SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++			       M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#if Enable_AMPDU_FW_Retry
++		SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
++			       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI <<
++								 8));
++#else
++		SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
++			       M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#endif
++		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
++			       (sc->mac_deci_tbl[6]));
++		return ret;
++	}
++	SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (0 << RG_PHY_MD_EN_SFT),
++			  RG_PHY_MD_EN_MSK);
++	SMAC_REG_WRITE(sh, ADR_BRG_SW_RST, 1 << MAC_SW_RST_SFT);
++	do {
++		SMAC_REG_READ(sh, ADR_BRG_SW_RST, &regval);
++		i++;
++		if (i > 10000) {
++			dev_err(sh->sc->dev, "MAC reset fail !!!!\n");
++			WARN_ON(1);
++			ret = 1;
++			goto exit;
++		}
++	} while (regval != 0);
++	SMAC_REG_WRITE(sc->sh, ADR_TXQ4_MTX_Q_AIFSN, 0xffff2101);
++	SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC, 0,
++			  MTX_HALT_MNG_UNTIL_DTIM_MSK);
++	SMAC_REG_WRITE(sh, ADR_CONTROL, 0x12000006);
++	SMAC_REG_WRITE(sh, ADR_RX_TIME_STAMP_CFG,
++		       ((28 << MRX_STP_OFST_SFT) | 0x01));
++	SMAC_REG_WRITE(sh, ADR_HCI_TX_RX_INFO_SIZE,
++		       ((u32) (TXPB_OFFSET) << TX_PBOFFSET_SFT) |
++		       ((u32) (sh->tx_desc_len) << TX_INFO_SIZE_SFT) |
++		       ((u32) (sh->rx_desc_len) << RX_INFO_SIZE_SFT) |
++		       ((u32) (sh->rx_pinfo_pad) << RX_LAST_PHY_SIZE_SFT)
++	    );
++	SMAC_REG_READ(sh, ADR_MMU_CTRL, &regval);
++	regval |= (0xff << MMU_SHARE_MCU_SFT);
++	SMAC_REG_WRITE(sh, ADR_MMU_CTRL, regval);
++	SMAC_REG_READ(sh, ADR_MRX_WATCH_DOG, &regval);
++	regval &= 0xfffffff0;
++	SMAC_REG_WRITE(sh, ADR_MRX_WATCH_DOG, regval);
++	SMAC_REG_READ(sh, ADR_TRX_ID_THRESHOLD, &id_len);
++	id_len = (id_len & 0xffff0000) |
++	    (SSV6200_ID_TX_THRESHOLD << TX_ID_THOLD_SFT) |
++	    (SSV6200_ID_RX_THRESHOLD << RX_ID_THOLD_SFT);
++	SMAC_REG_WRITE(sh, ADR_TRX_ID_THRESHOLD, id_len);
++	SMAC_REG_READ(sh, ADR_ID_LEN_THREADSHOLD1, &id_len);
++	id_len = (id_len & 0x0f) |
++	    (SSV6200_PAGE_TX_THRESHOLD << ID_TX_LEN_THOLD_SFT) |
++	    (SSV6200_PAGE_RX_THRESHOLD << ID_RX_LEN_THOLD_SFT);
++	SMAC_REG_WRITE(sh, ADR_ID_LEN_THREADSHOLD1, id_len);
++#ifdef CONFIG_SSV_CABRIO_MB_DEBUG
++	SMAC_REG_READ(sh, ADR_MB_DBG_CFG3, &regval);
++	regval |= (debug_buffer << 0);
++	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG3, regval);
++	SMAC_REG_READ(sh, ADR_MB_DBG_CFG2, &regval);
++	regval |= (DEBUG_SIZE << 16);
++	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG2, regval);
++	SMAC_REG_READ(sh, ADR_MB_DBG_CFG1, &regval);
++	regval |= (1 << MB_DBG_EN_SFT);
++	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG1, regval);
++	SMAC_REG_READ(sh, ADR_MBOX_HALT_CFG, &regval);
++	regval |= (1 << MB_ERR_AUTO_HALT_EN_SFT);
++	SMAC_REG_WRITE(sh, ADR_MBOX_HALT_CFG, regval);
++#endif
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
++	regval |= (1 << MTX_TSF_TIMER_EN_SFT);
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
++	SMAC_REG_WRITE(sh, 0xcd010004, 0x1213);
++	for (i = 0; i < SSV_RC_MAX_STA; i++) {
++		if (i == 0) {
++			sh->hw_buf_ptr[i] =
++			    ssv6xxx_pbuf_alloc(sc,
++					       sizeof(phy_info_tbl) +
++					       sizeof(struct ssv6xxx_hw_sec),
++					       NOTYPE_BUF);
++			if ((sh->hw_buf_ptr[i] >> 28) != 8) {
++				dev_err(sh->sc->dev, "opps allocate pbuf error\n");
++				WARN_ON(1);
++				ret = 1;
++				goto exit;
++			}
++		} else {
++			sh->hw_buf_ptr[i] =
++			    ssv6xxx_pbuf_alloc(sc,
++					       sizeof(struct ssv6xxx_hw_sec),
++					       NOTYPE_BUF);
++			if ((sh->hw_buf_ptr[i] >> 28) != 8) {
++				dev_err(sh->sc->dev, "opps allocate pbuf error\n");
++				WARN_ON(1);
++				ret = 1;
++				goto exit;
++			}
++		}
++	}
++	for (i = 0; i < 0x8; i++) {
++		temp[i] = 0;
++		temp[i] = ssv6xxx_pbuf_alloc(sc, 256, NOTYPE_BUF);
++	}
++	for (i = 0; i < 0x8; i++) {
++		if (temp[i] == 0x800e0000)
++			dev_dbg(sh->sc->dev, "Found 0x800e0000 at position %d\n", i);
++		else
++			ssv6xxx_pbuf_free(sc, temp[i]);
++	}
++	for (i = 0; i < SSV_RC_MAX_STA; i++)
++		sh->hw_sec_key[i] = sh->hw_buf_ptr[i];
++	for (i = 0; i < SSV_RC_MAX_STA; i++) {
++		int x;
++		for (x = 0; x < sizeof(struct ssv6xxx_hw_sec); x += 4) {
++			SMAC_REG_WRITE(sh, sh->hw_sec_key[i] + x, 0);
++		}
++	}
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &regval);
++	regval &= SCRT_PKT_ID_I_MSK;
++	regval |= ((sh->hw_sec_key[0] >> 16) << SCRT_PKT_ID_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, regval);
++	sh->hw_pinfo = sh->hw_sec_key[0] + sizeof(struct ssv6xxx_hw_sec);
++	for (i = 0, ptr = phy_info_tbl; i < PHY_INFO_TBL1_SIZE; i++, ptr++) {
++		SMAC_REG_WRITE(sh, ADR_INFO0 + i * 4, *ptr);
++		SMAC_REG_CONFIRM(sh, ADR_INFO0 + i * 4, *ptr);
++	}
++	for (i = 0; i < PHY_INFO_TBL2_SIZE; i++, ptr++) {
++		SMAC_REG_WRITE(sh, sh->hw_pinfo + i * 4, *ptr);
++		SMAC_REG_CONFIRM(sh, sh->hw_pinfo + i * 4, *ptr);
++	}
++	for (i = 0; i < PHY_INFO_TBL3_SIZE; i++, ptr++) {
++		SMAC_REG_WRITE(sh, sh->hw_pinfo +
++			       (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
++		SMAC_REG_CONFIRM(sh, sh->hw_pinfo +
++				 (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
++	}
++	SMAC_REG_WRITE(sh, ADR_INFO_RATE_OFFSET, 0x00040000);
++	SMAC_REG_WRITE(sh, ADR_INFO_IDX_ADDR, sh->hw_pinfo);
++	SMAC_REG_WRITE(sh, ADR_INFO_LEN_ADDR,
++		       sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
++	dev_dbg(sh->sc->dev, "ADR_INFO_IDX_ADDR[%08x] ADR_INFO_LEN_ADDR[%08x]\n",
++	       sh->hw_pinfo, sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
++	SMAC_REG_WRITE(sh, ADR_GLBLE_SET,
++		       (0 << OP_MODE_SFT) | (0 << SNIFFER_MODE_SFT) | (1 <<
++								       DUP_FLT_SFT)
++		       | (SSV6200_TX_PKT_RSVD_SETTING << TX_PKT_RSVD_SFT) |
++		       ((u32) (RXPB_OFFSET) << PB_OFFSET_SFT)
++	    );
++	SMAC_REG_WRITE(sh, ADR_STA_MAC_0, *((u32 *) & sh->cfg.maddr[0][0]));
++	SMAC_REG_WRITE(sh, ADR_STA_MAC_1, *((u32 *) & sh->cfg.maddr[0][4]));
++	SMAC_REG_WRITE(sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
++	SMAC_REG_WRITE(sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
++	SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_0, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_1, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_0, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_1, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_REASON_TRAP0, 0x7FBC7F87);
++	SMAC_REG_WRITE(sh, ADR_REASON_TRAP1, 0x0000003F);
++	SMAC_REG_WRITE(sh, ADR_TRAP_HW_ID, M_ENG_CPU);
++	SMAC_REG_WRITE(sh, ADR_WSID0, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_WSID1, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
++		       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) | (M_ENG_HWHCI <<
++								 8));
++#if defined(CONFIG_P2P_NOA) || defined(CONFIG_RX_MGMT_CHECK)
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++#else
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#endif
++#if Enable_AMPDU_FW_Retry
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++#else
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#endif
++	ssv6xxx_hw_set_replay_ignore(sh, 1);
++	ssv6xxx_update_decision_table(sc);
++	SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_STA,
++			  OP_MODE_MSK);
++	SMAC_REG_WRITE(sh, ADR_SDIO_MASK, 0xfffe1fff);
++	SMAC_REG_WRITE(sh, ADR_TX_LIMIT_INTR, 0x80000000 |
++		       SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER << 16 |
++		       SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER);
++#ifdef CONFIG_SSV_SUPPORT_BTCX
++	SMAC_REG_WRITE(sh, ADR_BTCX0,
++		       COEXIST_EN_MSK | (WIRE_MODE_SZ << WIRE_MODE_SFT)
++		       | WIFI_TX_SW_POL_MSK | BT_SW_POL_MSK);
++	SMAC_REG_WRITE(sh, ADR_BTCX1,
++		       SSV6200_BT_PRI_SMP_TIME | (SSV6200_BT_STA_SMP_TIME <<
++						  BT_STA_SMP_TIME_SFT)
++		       | (SSV6200_WLAN_REMAIN_TIME << WLAN_REMAIN_TIME_SFT));
++	SMAC_REG_WRITE(sh, ADR_SWITCH_CTL, BT_2WIRE_EN_MSK);
++	SMAC_REG_WRITE(sh, ADR_PAD7, 1);
++	SMAC_REG_WRITE(sh, ADR_PAD8, 0);
++	SMAC_REG_WRITE(sh, ADR_PAD9, 1);
++	SMAC_REG_WRITE(sh, ADR_PAD25, 1);
++	SMAC_REG_WRITE(sh, ADR_PAD27, 8);
++	SMAC_REG_WRITE(sh, ADR_PAD28, 8);
++#endif
++	dev_info(sh->sc->dev, "attempt to load firmware %s\n", WIFI_FIRMWARE_NAME);
++	ret = SMAC_LOAD_FW(sh, WIFI_FIRMWARE_NAME, 0);
++
++	SMAC_REG_READ(sh, FW_VERSION_REG, &regval);
++	if (regval == ssv_firmware_version) {
++		SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (1 << RG_PHY_MD_EN_SFT),
++				  RG_PHY_MD_EN_MSK);
++		dev_info(sh->sc->dev, "Firmware version %d\n", regval);
++	} else {
++		dev_err(sh->sc->dev, "Firmware version not mapping %d\n", regval);
++		ret = -1;
++	}
++	ssv6xxx_watchdog_controller(sh, (u8) SSV6XXX_HOST_CMD_WATCHDOG_START);
++ exit:
++	return ret;
++}
++
++void ssv6xxx_deinit_mac(struct ssv_softc *sc)
++{
++	int i;
++	for (i = 0; i < SSV_RC_MAX_STA; i++) {
++		if (sc->sh->hw_buf_ptr[i])
++			ssv6xxx_pbuf_free(sc, sc->sh->hw_buf_ptr[i]);
++	}
++}
++
++void inline ssv6xxx_deinit_hw(struct ssv_softc *sc)
++{
++	dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
++	ssv6xxx_deinit_mac(sc);
++}
++
++void ssv6xxx_restart_hw(struct ssv_softc *sc)
++{
++	dev_info(sc->dev, "Software MAC reset\n");
++	sc->restart_counter++;
++	sc->force_triger_reset = true;
++	HCI_STOP(sc->sh);
++	SMAC_REG_WRITE(sc->sh, 0xce000004, 0x0);
++	sc->beacon_info[0].pubf_addr = 0x00;
++	sc->beacon_info[1].pubf_addr = 0x00;
++	ieee80211_restart_hw(sc->hw);
++}
++
++extern struct ssv6xxx_iqk_cfg init_iqk_cfg;
++static int ssv6xxx_init_hw(struct ssv_hw *sh)
++{
++	int ret = 0, i = 0, x = 0;
++	u32 regval;
++	sh->tx_desc_len = SSV6XXX_TX_DESC_LEN;
++	sh->rx_desc_len = SSV6XXX_RX_DESC_LEN;
++	sh->rx_pinfo_pad = 0x04;
++	sh->tx_page_available = SSV6200_PAGE_TX_THRESHOLD;
++	sh->ampdu_divider = SSV6XXX_AMPDU_DIVIDER;
++	memset(sh->page_count, 0, sizeof(sh->page_count));
++	if (sh->cfg.force_chip_identity) {
++		dev_info(sh->sc->dev, "Force use external RF setting [%08x]\n",
++		       sh->cfg.force_chip_identity);
++		sh->cfg.chip_identity = sh->cfg.force_chip_identity;
++	}
++	if (sh->cfg.chip_identity == SSV6051Z) {
++		sh->p_ch_cfg = &ch_cfg_z[0];
++		sh->ch_cfg_size =
++		    sizeof(ch_cfg_z) / sizeof(struct ssv6xxx_ch_cfg);
++		memcpy(phy_info_tbl, phy_info_6051z, sizeof(phy_info_6051z));
++	} else if (sh->cfg.chip_identity == SSV6051P) {
++		sh->p_ch_cfg = &ch_cfg_p[0];
++		sh->ch_cfg_size =
++		    sizeof(ch_cfg_p) / sizeof(struct ssv6xxx_ch_cfg);
++	}
++	switch (sh->cfg.chip_identity) {
++	case SSV6051Q_P1:
++	case SSV6051Q_P2:
++	case SSV6051Q:
++		dev_info(sh->sc->dev, "Using SSV6051Q setting\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == 0xCE010008)
++				ssv6200_rf_tbl[i].data = 0x008DF61B;
++			if (ssv6200_rf_tbl[i].address == 0xCE010014)
++				ssv6200_rf_tbl[i].data = 0x3D3E84FE;
++			if (ssv6200_rf_tbl[i].address == 0xCE010018)
++				ssv6200_rf_tbl[i].data = 0x01457D79;
++			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
++				ssv6200_rf_tbl[i].data = 0x000103A7;
++			if (ssv6200_rf_tbl[i].address == 0xCE010020)
++				ssv6200_rf_tbl[i].data = 0x000103A6;
++			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
++				ssv6200_rf_tbl[i].data = 0x00032CA8;
++			if (ssv6200_rf_tbl[i].address == 0xCE010048)
++				ssv6200_rf_tbl[i].data = 0xFCCCCF27;
++			if (ssv6200_rf_tbl[i].address == 0xCE010050)
++				ssv6200_rf_tbl[i].data = 0x0047C000;
++		}
++		break;
++	case SSV6051Z:
++		dev_info(sh->sc->dev, "Using SSV6051Z setting\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == 0xCE010008)
++				ssv6200_rf_tbl[i].data = 0x004D561C;
++			if (ssv6200_rf_tbl[i].address == 0xCE010014)
++				ssv6200_rf_tbl[i].data = 0x3D9E84FE;
++			if (ssv6200_rf_tbl[i].address == 0xCE010018)
++				ssv6200_rf_tbl[i].data = 0x00457D79;
++			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
++				ssv6200_rf_tbl[i].data = 0x000103EB;
++			if (ssv6200_rf_tbl[i].address == 0xCE010020)
++				ssv6200_rf_tbl[i].data = 0x000103EA;
++			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
++				ssv6200_rf_tbl[i].data = 0x00062CA8;
++			if (ssv6200_rf_tbl[i].address == 0xCE010048)
++				ssv6200_rf_tbl[i].data = 0xFCCCCF27;
++			if (ssv6200_rf_tbl[i].address == 0xCE010050)
++				ssv6200_rf_tbl[i].data = 0x0047C000;
++		}
++		break;
++	case SSV6051P:
++		dev_info(sh->sc->dev, "Using SSV6051P setting\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == 0xCE010008)
++				ssv6200_rf_tbl[i].data = 0x008B7C1C;
++			if (ssv6200_rf_tbl[i].address == 0xCE010014)
++				ssv6200_rf_tbl[i].data = 0x3D7E84FE;
++			if (ssv6200_rf_tbl[i].address == 0xCE010018)
++				ssv6200_rf_tbl[i].data = 0x01457D79;
++			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
++				ssv6200_rf_tbl[i].data = 0x000103EB;
++			if (ssv6200_rf_tbl[i].address == 0xCE010020)
++				ssv6200_rf_tbl[i].data = 0x000103EA;
++			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
++				ssv6200_rf_tbl[i].data = 0x00032CA8;
++			if (ssv6200_rf_tbl[i].address == 0xCE010048)
++				ssv6200_rf_tbl[i].data = 0xFCCCCC27;
++			if (ssv6200_rf_tbl[i].address == 0xCE010050)
++				ssv6200_rf_tbl[i].data = 0x0047C000;
++			if (ssv6200_rf_tbl[i].address == 0xC0001D00)
++				ssv6200_rf_tbl[i].data = 0x5E000040;
++		}
++		break;
++	default:
++		dev_err(sh->sc->dev, "No RF setting\n");
++		break;
++	}
++	if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M) {
++		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_26M;
++		dev_info(sh->sc->dev, "Crystal frequency: 26 Mhz\n");
++	} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
++		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_40M;
++		dev_info(sh->sc->dev, "Crystal frequency: 40 Mhz\n");
++	} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M) {
++		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_24M;
++		dev_info(sh->sc->dev, "Crystal frequency: 24 Mhz\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == ADR_SX_ENABLE_REGISTER)
++				ssv6200_rf_tbl[i].data = 0x0003E07C;
++			if (ssv6200_rf_tbl[i].address ==
++			    ADR_DPLL_DIVIDER_REGISTER)
++				ssv6200_rf_tbl[i].data = 0x00406000;
++			if (ssv6200_rf_tbl[i].address ==
++			    ADR_DPLL_FB_DIVIDER_REGISTERS_I)
++				ssv6200_rf_tbl[i].data = 0x00000028;
++			if (ssv6200_rf_tbl[i].address ==
++			    ADR_DPLL_FB_DIVIDER_REGISTERS_II)
++				ssv6200_rf_tbl[i].data = 0x00000000;
++		}
++	} else {
++		dev_warn(sh->sc->dev, "Illegal crystal setting, using default value of 26 Mhz\n");
++	}
++	for (i = 0;
++	     i < sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++	     i++) {
++		if (ssv6200_rf_tbl[i].address ==
++		    ADR_SYN_KVCO_XO_FINE_TUNE_CBANK) {
++			if (sh->cfg.crystal_frequency_offset) {
++				ssv6200_rf_tbl[i].data &=
++				    RG_XOSC_CBANK_XO_I_MSK;
++				ssv6200_rf_tbl[i].data |=
++				    (sh->cfg.
++				     crystal_frequency_offset <<
++				     RG_XOSC_CBANK_XO_SFT);
++			}
++		}
++	}
++	for (i = 0; i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
++	     i++) {
++		if (phy_setting[i].address == ADR_TX_GAIN_FACTOR) {
++			switch (sh->cfg.chip_identity) {
++			case SSV6051Q_P1:
++			case SSV6051Q_P2:
++			case SSV6051Q:
++				dev_dbg(sh->sc->dev, "SSV6051Q setting [0x5B606C72]\n");
++				phy_setting[i].data = 0x5B606C72;
++				break;
++			case SSV6051Z:
++				dev_dbg(sh->sc->dev, "SSV6051Z setting [0x60606060]\n");
++				phy_setting[i].data = 0x60606060;
++				break;
++			case SSV6051P:
++				dev_dbg(sh->sc->dev, "SSV6051P setting [0x6C726C72]\n");
++				phy_setting[i].data = 0x6C726C72;
++				break;
++			default:
++				dev_dbg(sh->sc->dev, "Use default power setting\n");
++				break;
++			}
++			if (sh->cfg.wifi_tx_gain_level_b) {
++				phy_setting[i].data &= 0xffff0000;
++				phy_setting[i].data |=
++				    wifi_tx_gain[sh->cfg.
++						 wifi_tx_gain_level_b] &
++				    0x0000ffff;
++			}
++			if (sh->cfg.wifi_tx_gain_level_gn) {
++				phy_setting[i].data &= 0x0000ffff;
++				phy_setting[i].data |=
++				    wifi_tx_gain[sh->cfg.
++						 wifi_tx_gain_level_gn] &
++				    0xffff0000;
++			}
++			dev_dbg(sh->sc->dev, "TX power setting 0x%x\n", phy_setting[i].data);
++			init_iqk_cfg.cfg_def_tx_scale_11b =
++			    (phy_setting[i].data >> 0) & 0xff;
++			init_iqk_cfg.cfg_def_tx_scale_11b_p0d5 =
++			    (phy_setting[i].data >> 8) & 0xff;
++			init_iqk_cfg.cfg_def_tx_scale_11g =
++			    (phy_setting[i].data >> 16) & 0xff;
++			init_iqk_cfg.cfg_def_tx_scale_11g_p0d5 =
++			    (phy_setting[i].data >> 24) & 0xff;
++			break;
++		}
++	}
++	if (sh->cfg.volt_regulator == SSV6XXX_VOLT_LDO_CONVERT) {
++		dev_info(sh->sc->dev, "Using LDO voltage regulator\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
++				ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
++				ssv6200_rf_tbl[i].data |= 0x00000000;
++			}
++		}
++	} else if (sh->cfg.volt_regulator == SSV6XXX_VOLT_DCDC_CONVERT) {
++		dev_info(sh->sc->dev, "Using DCDC buck regulator\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
++				ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
++				ssv6200_rf_tbl[i].data |= 0x00000001;
++			}
++		}
++	} else {
++		dev_warn(sh->sc->dev, "Illegal regulator setting, using DCDC buck as default\n");
++	}
++	while (ssv_cfg.configuration[x][0]) {
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address ==
++			    ssv_cfg.configuration[x][0]) {
++				ssv6200_rf_tbl[i].data =
++				    ssv_cfg.configuration[x][1];
++				break;
++			}
++		}
++		for (i = 0;
++		     i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (phy_setting[i].address ==
++			    ssv_cfg.configuration[x][0]) {
++				phy_setting[i].data =
++				    ssv_cfg.configuration[x][1];
++				break;
++			}
++		}
++		x++;
++	};
++	if (ret == 0)
++		ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_rf_tbl);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1, 0x00000000);
++	SMAC_REG_READ(sh, ADR_PHY_EN_0, &regval);
++	if (regval & (1 << RG_RF_BB_CLK_SEL_SFT)) {
++		dev_dbg(sh->sc->dev, "already do clock switch\n");
++	} else {
++		dev_dbg(sh->sc->dev, "reset PLL\n");
++		SMAC_REG_READ(sh, ADR_DPLL_CP_PFD_REGISTER, &regval);
++		regval |=
++		    ((1 << RG_DP_BBPLL_PD_SFT) |
++		     (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
++		SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
++		regval &=
++		    ~((1 << RG_DP_BBPLL_PD_SFT) |
++		      (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
++		SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
++		mdelay(10);
++	}
++	if (ret == 0)
++		ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_phy_tbl);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xEAAAAAAA);
++	SMAC_REG_READ(sh, ADR_TRX_DUMMY_REGISTER, &regval);
++	if (regval != 0xEAAAAAAA) {
++		dev_warn(sh->sc->dev, "Unexpected register value\n");
++		WARN_ON(1);
++	}
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PAD53, 0x21);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PAD54, 0x3000);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PIN_SEL_0, 0x4000);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, 0xc0000304, 0x01);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, 0xc0000308, 0x01);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_CLOCK_SELECTION, 0x3);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xAAAAAAAA);
++	if ((ret = ssv6xxx_set_channel(sh->sc, sh->cfg.def_chan)))
++		return ret;
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1,
++				     (RG_PHYRX_MD_EN_MSK | RG_PHYTX_MD_EN_MSK |
++				      RG_PHY11GN_MD_EN_MSK | RG_PHY11B_MD_EN_MSK
++				      | RG_PHYRXFIFO_MD_EN_MSK |
++				      RG_PHYTXFIFO_MD_EN_MSK |
++				      RG_PHY11BGN_MD_EN_MSK));
++	return ret;
++}
++
++static void ssv6xxx_check_mac2(struct ssv_hw *sh)
++{
++	const u8 addr_mask[6] = { 0xfd, 0xff, 0xff, 0xff, 0xff, 0xfc };
++	u8 i;
++	bool invalid = false;
++	for (i = 0; i < 6; i++) {
++		if ((ssv_cfg.maddr[0][i] & addr_mask[i]) !=
++		    (ssv_cfg.maddr[1][i] & addr_mask[i])) {
++			invalid = true;
++			dev_dbg(sh->sc->dev, " i %d , mac1[i] %x, mac2[i] %x, mask %x \n", i,
++			       ssv_cfg.maddr[0][i], ssv_cfg.maddr[1][i],
++			       addr_mask[i]);
++			break;
++		}
++	}
++	if (invalid) {
++		memcpy(&ssv_cfg.maddr[1][0], &ssv_cfg.maddr[0][0], 6);
++		ssv_cfg.maddr[1][5] ^= 0x01;
++		if (ssv_cfg.maddr[1][5] < ssv_cfg.maddr[0][5]) {
++			u8 temp;
++			temp = ssv_cfg.maddr[0][5];
++			ssv_cfg.maddr[0][5] = ssv_cfg.maddr[1][5];
++			ssv_cfg.maddr[1][5] = temp;
++			sh->cfg.maddr[0][5] = ssv_cfg.maddr[0][5];
++		}
++		dev_warn(sh->sc->dev, "MAC 2 address invalid!!\n");
++		dev_warn(sh->sc->dev, "After modification, MAC1 %pM, MAC2 %pM\n",
++		       ssv_cfg.maddr[0], ssv_cfg.maddr[1]);
++	}
++}
++
++static int ssv6xxx_read_configuration(struct ssv_hw *sh)
++{
++	extern u32 sdio_sr_bhvr;
++	if (is_valid_ether_addr(&ssv_cfg.maddr[0][0]))
++		memcpy(&sh->cfg.maddr[0][0], &ssv_cfg.maddr[0][0], ETH_ALEN);
++	if (is_valid_ether_addr(&ssv_cfg.maddr[1][0])) {
++		ssv6xxx_check_mac2(sh);
++		memcpy(&sh->cfg.maddr[1][0], &ssv_cfg.maddr[1][0], ETH_ALEN);
++	}
++	if (ssv_cfg.hw_caps)
++		sh->cfg.hw_caps = ssv_cfg.hw_caps;
++	else
++		sh->cfg.hw_caps = SSV6200_HW_CAP_HT |
++		    SSV6200_HW_CAP_2GHZ |
++		    SSV6200_HW_CAP_SECURITY |
++		    SSV6200_HW_CAP_P2P |
++		    SSV6200_HT_CAP_SGI_20 |
++		    SSV6200_HW_CAP_AMPDU_RX |
++		    SSV6200_HW_CAP_AMPDU_TX | SSV6200_HW_CAP_AP;
++	if (ssv_cfg.def_chan)
++		sh->cfg.def_chan = ssv_cfg.def_chan;
++	else
++		sh->cfg.def_chan = 6;
++	sh->cfg.use_wpa2_only = ssv_cfg.use_wpa2_only;
++	if (ssv_cfg.crystal_type == 26)
++		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_26M;
++	else if (ssv_cfg.crystal_type == 40)
++		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_40M;
++	else if (ssv_cfg.crystal_type == 24)
++		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_24M;
++	else {
++		dev_warn(sh->sc->dev, "Please redefine xtal_clock(wifi.cfg)!!\n");
++		WARN_ON(1);
++		return 1;
++	}
++	if (ssv_cfg.volt_regulator < 2)
++		sh->cfg.volt_regulator = ssv_cfg.volt_regulator;
++	else {
++		dev_warn(sh->sc->dev, "Please redefine volt_regulator(wifi.cfg)!!\n");
++		WARN_ON(1);
++		return 1;
++	}
++	sh->cfg.wifi_tx_gain_level_gn = ssv_cfg.wifi_tx_gain_level_gn;
++	sh->cfg.wifi_tx_gain_level_b = ssv_cfg.wifi_tx_gain_level_b;
++	sh->cfg.rssi_ctl = ssv_cfg.rssi_ctl;
++	sh->cfg.sr_bhvr = ssv_cfg.sr_bhvr;
++	sdio_sr_bhvr = ssv_cfg.sr_bhvr;
++	sh->cfg.force_chip_identity = ssv_cfg.force_chip_identity;
++	strncpy(sh->cfg.firmware_path, ssv_cfg.firmware_path,
++		sizeof(sh->cfg.firmware_path) - 1);
++	strncpy(sh->cfg.flash_bin_path, ssv_cfg.flash_bin_path,
++		sizeof(sh->cfg.flash_bin_path) - 1);
++	strncpy(sh->cfg.mac_address_path, ssv_cfg.mac_address_path,
++		sizeof(sh->cfg.mac_address_path) - 1);
++	strncpy(sh->cfg.mac_output_path, ssv_cfg.mac_output_path,
++		sizeof(sh->cfg.mac_output_path) - 1);
++	sh->cfg.ignore_efuse_mac = ssv_cfg.ignore_efuse_mac;
++	sh->cfg.mac_address_mode = ssv_cfg.mac_address_mode;
++	return 0;
++}
++
++static int ssv6xxx_read_hw_info(struct ssv_softc *sc)
++{
++	struct ssv_hw *sh;
++	sh = kzalloc(sizeof(struct ssv_hw), GFP_KERNEL);
++	if (sh == NULL)
++		return -ENOMEM;
++	memset((void *)sh, 0, sizeof(struct ssv_hw));
++	sc->sh = sh;
++	sh->sc = sc;
++	sh->priv = sc->dev->platform_data;
++	if (ssv6xxx_read_configuration(sh))
++		return -ENOMEM;
++	sh->hci.dev = sc->dev;
++	sh->hci.hci_ops = NULL;
++	sh->hci.hci_rx_cb = ssv6200_rx;
++	sh->hci.rx_cb_args = (void *)sc;
++	sh->hci.hci_tx_cb = ssv6xxx_tx_cb;
++	sh->hci.tx_cb_args = (void *)sc;
++	sh->hci.hci_skb_update_cb = ssv6xxx_tx_rate_update;
++	sh->hci.skb_update_args = (void *)sc;
++	sh->hci.hci_tx_flow_ctrl_cb = ssv6200_tx_flow_control;
++	sh->hci.tx_fctrl_cb_args = (void *)sc;
++	sh->hci.hci_tx_q_empty_cb = ssv6xxx_tx_q_empty_cb;
++	sh->hci.tx_q_empty_args = (void *)sc;
++	sh->hci.if_ops = sh->priv->ops;
++	sh->hci.hci_tx_buf_free_cb = ssv6xxx_txbuf_free_skb;
++	sh->hci.tx_buf_free_args = (void *)sc;
++	return 0;
++}
++
++static int ssv6xxx_init_device(struct ssv_softc *sc, const char *name)
++{
++	struct ieee80211_hw *hw = sc->hw;
++	struct ssv_hw *sh;
++	int error = 0;
++	BUG_ON(!sc->dev->platform_data);
++	if ((error = ssv6xxx_read_hw_info(sc)) != 0) {
++		return error;
++	}
++	sh = sc->sh;
++	if (sh->cfg.hw_caps == 0)
++		return -1;
++	ssv6xxx_hci_register(&sh->hci);
++	efuse_read_all_map(sh);
++	if ((error = ssv6xxx_init_softc(sc)) != 0) {
++		ssv6xxx_deinit_softc(sc);
++		ssv6xxx_hci_deregister();
++		kfree(sh);
++		return error;
++	}
++	if ((error = ssv6xxx_init_hw(sc->sh)) != 0) {
++		ssv6xxx_deinit_hw(sc);
++		ssv6xxx_deinit_softc(sc);
++		ssv6xxx_hci_deregister();
++		kfree(sh);
++		return error;
++	}
++	if ((error = ieee80211_register_hw(hw)) != 0) {
++		dev_err(sc->dev, "Failed to register ieee80211 wireless device. ret=%d.\n", error);
++		ssv6xxx_deinit_hw(sc);
++		ssv6xxx_deinit_softc(sc);
++		ssv6xxx_hci_deregister();
++		kfree(sh);
++		return error;
++	}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_init_debugfs(sc, name);
++#endif
++	return 0;
++}
++
++static void ssv6xxx_deinit_device(struct ssv_softc *sc)
++{
++	dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_deinit_debugfs(sc);
++#endif
++	ssv6xxx_rf_disable(sc->sh);
++	ieee80211_unregister_hw(sc->hw);
++	ssv6xxx_deinit_hw(sc);
++	ssv6xxx_deinit_softc(sc);
++	ssv6xxx_hci_deregister();
++	kfree(sc->sh);
++}
++
++extern struct ieee80211_ops ssv6200_ops;
++int ssv6xxx_dev_probe(struct platform_device *pdev)
++{
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	extern struct ssv_softc *ssv_dbg_sc;
++#endif
++#ifdef CONFIG_SSV_SMARTLINK
++	extern struct ssv_softc *ssv_smartlink_sc;
++#endif
++	struct ssv_softc *softc;
++	struct ieee80211_hw *hw;
++	int ret;
++	if (!pdev->dev.platform_data) {
++		dev_err(&pdev->dev, "no platform data specified!\n");
++		return -EINVAL;
++	}
++	hw = ieee80211_alloc_hw(sizeof(struct ssv_softc), &ssv6200_ops);
++	if (hw == NULL) {
++		dev_err(&pdev->dev, "Could not allocate memory for ieee80211 wireless device\n");
++		return -ENOMEM;
++	}
++	SET_IEEE80211_DEV(hw, &pdev->dev);
++	dev_set_drvdata(&pdev->dev, hw);
++	memset((void *)hw->priv, 0, sizeof(struct ssv_softc));
++	softc = hw->priv;
++	softc->hw = hw;
++	softc->dev = &pdev->dev;
++	//SET_IEEE80211_PERM_ADDR(hw, (const u8 *)&softc->sh->maddr[0]);
++	ret = ssv6xxx_init_device(softc, pdev->name);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to initialize device\n");
++		ieee80211_free_hw(hw);
++		return ret;
++	}
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	ssv_dbg_sc = softc;
++#endif
++#ifdef CONFIG_SSV_SMARTLINK
++	ssv_smartlink_sc = softc;
++#endif
++	wiphy_info(hw->wiphy, "%s\n", "SSV6200 of South Silicon Valley");
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_dev_probe);
++int ssv6xxx_dev_remove(struct platform_device *pdev)
++{
++	struct ieee80211_hw *hw = dev_get_drvdata(&pdev->dev);
++	struct ssv_softc *softc = hw->priv;
++	dev_dbg(&pdev->dev, "ssv6xxx_dev_remove(): pdev=%p, hw=%p\n", pdev, hw);
++	ssv6xxx_deinit_device(softc);
++	dev_dbg(&pdev->dev, "ieee80211_free_hw(): \n");
++	ieee80211_free_hw(hw);
++	dev_info(&pdev->dev, "driver unloaded\n");
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_dev_remove);
++static const struct platform_device_id ssv6xxx_id_table[] = {
++	{
++	 .name = "ssv6200",
++	 .driver_data = 0x00,
++	 },
++	{},
++};
++
++MODULE_DEVICE_TABLE(platform, ssv6xxx_id_table);
++static struct platform_driver ssv6xxx_driver = {
++	.probe = ssv6xxx_dev_probe,
++	.remove = ssv6xxx_dev_remove,
++	.id_table = ssv6xxx_id_table,
++	.driver = {
++		   .name = "SSV WLAN driver",
++		   .owner = THIS_MODULE,
++		   }
++};
++
++int ssv6xxx_init(void)
++{
++	extern void *ssv_dbg_phy_table;
++	extern u32 ssv_dbg_phy_len;
++	extern void *ssv_dbg_rf_table;
++	extern u32 ssv_dbg_rf_len;
++	ssv_dbg_phy_table = (void *)ssv6200_phy_tbl;
++	ssv_dbg_phy_len =
++	    sizeof(ssv6200_phy_tbl) / sizeof(struct ssv6xxx_dev_table);
++	ssv_dbg_rf_table = (void *)ssv6200_rf_tbl;
++	ssv_dbg_rf_len =
++	    sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++	return platform_driver_register(&ssv6xxx_driver);
++}
++
++void ssv6xxx_exit(void)
++{
++	platform_driver_unregister(&ssv6xxx_driver);
++}
++
++EXPORT_SYMBOL(ssv6xxx_init);
++EXPORT_SYMBOL(ssv6xxx_exit);
+diff --git a/drivers/net/wireless/ssv6051/smac/init.h b/drivers/net/wireless/ssv6051/smac/init.h
+new file mode 100644
+index 000000000000..97994d00d4da
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/init.h
+@@ -0,0 +1,23 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _INIT_H_
++#define _INIT_H_
++int ssv6xxx_init_mac(struct ssv_hw *sh);
++int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);
++void ssv6xxx_deinit_mac(struct ssv_softc *sc);
++void ssv6xxx_restart_hw(struct ssv_softc *sc);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/lib.c b/drivers/net/wireless/ssv6051/smac/lib.c
+new file mode 100644
+index 000000000000..ccf0974b0f20
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/lib.c
+@@ -0,0 +1,33 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include "lib.h"
++struct sk_buff *ssv_skb_alloc(s32 len)
++{
++	struct sk_buff *skb;
++	skb = __dev_alloc_skb(len + 128, GFP_KERNEL);
++	if (skb != NULL) {
++		skb_put(skb, 0x20);
++		skb_pull(skb, 0x20);
++	}
++	return skb;
++}
++
++void ssv_skb_free(struct sk_buff *skb)
++{
++	dev_kfree_skb_any(skb);
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/lib.h b/drivers/net/wireless/ssv6051/smac/lib.h
+new file mode 100644
+index 000000000000..266cf7afac95
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/lib.h
+@@ -0,0 +1,23 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _LIB_H_
++#define _LIB_H_
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++struct sk_buff *ssv_skb_alloc(s32 len);
++void ssv_skb_free(struct sk_buff *skb);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/linux_80211.h b/drivers/net/wireless/ssv6051/smac/linux_80211.h
+new file mode 100644
+index 000000000000..e268808e3c93
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/linux_80211.h
+@@ -0,0 +1,24 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _LINUX_80211_H_
++#define _LINUX_80211_H_
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
++#define INDEX_80211_BAND_2GHZ IEEE80211_BAND_2GHZ
++#else
++#define INDEX_80211_BAND_2GHZ NL80211_BAND_2GHZ
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/p2p.c b/drivers/net/wireless/ssv6051/smac/p2p.c
+new file mode 100644
+index 000000000000..60fd8effd6ec
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/p2p.c
+@@ -0,0 +1,305 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include <linux/types.h>
++#include <linux/nl80211.h>
++#include <net/mac80211.h>
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <linux/kthread.h>
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "p2p.h"
++#include "dev.h"
++#include "lib.h"
++#ifdef CONFIG_P2P_NOA
++#define P2P_IE_VENDOR_TYPE 0x506f9a09
++#define P2P_NOA_DETECT_INTERVAL (5 * HZ)
++#ifndef MAC2STR
++#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
++#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
++#define COMPACT_MACSTR "%02x%02x%02x%02x%02x%02x"
++#endif
++void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
++			  struct ssv6xxx_p2p_noa_param *p2p_noa_param);
++static inline u32 WPA_GET_BE32(const u8 * a)
++{
++	return (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3];
++}
++
++static inline u16 WPA_GET_LE16(const u8 * a)
++{
++	return (a[1] << 8) | a[0];
++}
++
++static inline u32 WPA_GET_LE32(const u8 * a)
++{
++	return (a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0];
++}
++
++#define IEEE80211_HDRLEN 24
++enum p2p_attr_id {
++	P2P_ATTR_STATUS = 0,
++	P2P_ATTR_MINOR_REASON_CODE = 1,
++	P2P_ATTR_CAPABILITY = 2,
++	P2P_ATTR_DEVICE_ID = 3,
++	P2P_ATTR_GROUP_OWNER_INTENT = 4,
++	P2P_ATTR_CONFIGURATION_TIMEOUT = 5,
++	P2P_ATTR_LISTEN_CHANNEL = 6,
++	P2P_ATTR_GROUP_BSSID = 7,
++	P2P_ATTR_EXT_LISTEN_TIMING = 8,
++	P2P_ATTR_INTENDED_INTERFACE_ADDR = 9,
++	P2P_ATTR_MANAGEABILITY = 10,
++	P2P_ATTR_CHANNEL_LIST = 11,
++	P2P_ATTR_NOTICE_OF_ABSENCE = 12,
++	P2P_ATTR_DEVICE_INFO = 13,
++	P2P_ATTR_GROUP_INFO = 14,
++	P2P_ATTR_GROUP_ID = 15,
++	P2P_ATTR_INTERFACE = 16,
++	P2P_ATTR_OPERATING_CHANNEL = 17,
++	P2P_ATTR_INVITATION_FLAGS = 18,
++	P2P_ATTR_OOB_GO_NEG_CHANNEL = 19,
++	P2P_ATTR_VENDOR_SPECIFIC = 221
++};
++struct ssv6xxx_p2p_noa_attribute {
++	u8 index;
++	u16 ctwindows_oppps;
++	struct ssv6xxx_p2p_noa_param noa_param;
++};
++extern void _ssv6xxx_hexdump(const char *title, const u8 * buf, size_t len);
++bool p2p_find_noa(const u8 * ies, struct ssv6xxx_p2p_noa_attribute *noa_attr)
++{
++	const u8 *end, *pos, *ie;
++	u32 len;
++	len = ie[1] - 4;
++	pos = ie + 6;
++	end = pos + len;
++	while (pos < end) {
++		u16 attr_len;
++		if (pos + 2 >= end) {
++			return false;
++		}
++		attr_len = WPA_GET_LE16(pos + 1);
++		if (pos + 3 + attr_len > end) {
++			return false;
++		}
++		if (pos[0] != P2P_ATTR_NOTICE_OF_ABSENCE) {
++			pos += 3 + attr_len;
++			continue;
++		}
++		if (attr_len < 15) {
++			printk
++			    ("*********************NOA descriptor does not exist len[%d]\n",
++			     attr_len);
++			break;
++		}
++		if (attr_len > 15)
++			printk("More than one NOA descriptor\n");
++		noa_attr->index = pos[3];
++		noa_attr->ctwindows_oppps = pos[4];
++		noa_attr->noa_param.count = pos[5];
++		noa_attr->noa_param.duration = WPA_GET_LE32(&pos[6]);
++		noa_attr->noa_param.interval = WPA_GET_LE32(&pos[10]);
++		noa_attr->noa_param.start_time = WPA_GET_LE32(&pos[14]);
++		return true;
++	}
++	return false;
++}
++
++bool p2p_get_attribute_noa(const u8 * ies, u32 oui_type,
++			   struct ssv6xxx_p2p_noa_attribute *noa_attr)
++{
++	const u8 *end, *pos, *ie;
++	u32 len;
++	pos = ies;
++	end = ies + ies_len;
++	ie = NULL;
++	while (pos + 1 < end) {
++		if (pos + 2 + pos[1] > end)
++			return false;
++		if (pos[0] == WLAN_EID_VENDOR_SPECIFIC && pos[1] >= 4 &&
++		    WPA_GET_BE32(&pos[2]) == oui_type) {
++			ie = pos;
++			if (p2p_find_noa(ie, 0, noa_attr) == true)
++				return true;
++		}
++		pos += 2 + pos[1];
++	}
++	return false;
++}
++
++void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct cfg_host_event *host_event;
++	struct ssv62xx_noa_evt *noa_evt;
++	host_event = (struct cfg_host_event *)skb->data;
++	noa_evt = (struct ssv62xx_noa_evt *)&host_event->dat[0];
++	switch (noa_evt->evt_id) {
++	case SSV6XXX_NOA_START:
++		sc->p2p_noa.active_noa_vif |= (1 << noa_evt->vif);
++		printk("SSV6XXX_NOA_START===>[%08x]\n",
++		       sc->p2p_noa.active_noa_vif);
++		break;
++	case SSV6XXX_NOA_STOP:
++		sc->p2p_noa.active_noa_vif &= ~(1 << noa_evt->vif);
++		printk("SSV6XXX_NOA_STOP===>[%08x]\n",
++		       sc->p2p_noa.active_noa_vif);
++		break;
++	default:
++		printk("--------->NOA wrong command<---------\n");
++		break;
++	}
++}
++
++void ssv6xxx_noa_reset(struct ssv_softc *sc)
++{
++	unsigned long flags;
++	printk("Reset NOA param...\n");
++	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
++	memset(&sc->p2p_noa.noa_detect, 0,
++	       sizeof(struct ssv_p2p_noa_detect) * SSV_NUM_VIF);
++	sc->p2p_noa.active_noa_vif = 0;
++	sc->p2p_noa.monitor_noa_vif = 0;
++	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
++}
++
++void ssv6xxx_noa_host_stop_noa(struct ssv_softc *sc, u8 vif_id)
++{
++	struct ssv6xxx_p2p_noa_attribute noa_attr;
++	if (sc->p2p_noa.noa_detect[vif_id].p2p_noa_index >= 0) {
++		sc->p2p_noa.noa_detect[vif_id].p2p_noa_index = -1;
++		sc->p2p_noa.active_noa_vif &= ~(1 << vif_id);
++		memset(&sc->p2p_noa.noa_detect[vif_id].noa_param_cmd, 0,
++		       sizeof(struct ssv6xxx_p2p_noa_param));
++		printk("->remove NOA operating vif[%d]\n", vif_id);
++		noa_attr.noa_param.enable = 0;
++		noa_attr.noa_param.vif_id = vif_id;
++		ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
++	}
++}
++
++void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
++			u32 len)
++{
++	int i;
++	unsigned long flags;
++	struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
++	struct ssv6xxx_p2p_noa_attribute noa_attr;
++	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
++	if (sc->p2p_noa.monitor_noa_vif == 0)
++		goto out;
++	for (i = 0; i < SSV_NUM_VIF; i++) {
++		if (sc->p2p_noa.noa_detect[i].noa_addr == NULL)
++			continue;
++		if (memcmp(mgmt->bssid, sc->p2p_noa.noa_detect[i].noa_addr, 6)
++		    != 0)
++			continue;
++		if (sc->p2p_noa.active_noa_vif &&
++		    ((sc->p2p_noa.active_noa_vif & 1 << i) == 0))
++			continue;
++		sc->p2p_noa.noa_detect[i].last_rx = jiffies;
++		if (p2p_get_attribute_noa((const u8 *)mgmt->u.beacon.variable,
++					  len - (IEEE80211_HDRLEN +
++						 sizeof(mgmt->u.beacon)),
++					  P2P_IE_VENDOR_TYPE,
++					  &noa_attr) == false) {
++			continue;
++		}
++		if (sc->p2p_noa.noa_detect[i].p2p_noa_index == noa_attr.index) {
++			goto out;
++		}
++		printk(MACSTR "->set NOA element\n", MAC2STR(mgmt->bssid));
++		sc->p2p_noa.active_noa_vif |= (1 << i);
++		sc->p2p_noa.noa_detect[i].p2p_noa_index = noa_attr.index;
++		memcpy(&sc->p2p_noa.noa_detect[i].noa_param_cmd,
++		       &noa_attr.noa_param,
++		       sizeof(struct ssv6xxx_p2p_noa_param));
++		noa_attr.noa_param.enable = 1;
++		noa_attr.noa_param.vif_id = i;
++		memcpy(noa_attr.noa_param.addr, hdr->addr2, 6);
++		ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
++	}
++ out:
++	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
++}
++
++void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
++				enum ssv6xxx_noa_conf conf, u8 vif_idx)
++{
++	unsigned long flags;
++	if (sc->vif_info[vif_idx].vif->type != NL80211_IFTYPE_STATION ||
++	    sc->vif_info[vif_idx].vif->p2p != true)
++		return;
++	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
++	printk("====>[NOA]ssv6xxx_noa_hdl_bss_change conf[%d] vif_idx[%d]\n",
++	       conf, vif_idx);
++	switch (conf) {
++	case MONITOR_NOA_CONF_ADD:
++		memset(&sc->p2p_noa.noa_detect[vif_idx], 0,
++		       sizeof(struct ssv_p2p_noa_detect));
++		sc->p2p_noa.noa_detect[vif_idx].noa_addr =
++		    sc->vif_info[vif_idx].vif->bss_conf.bssid;
++		sc->p2p_noa.noa_detect[vif_idx].p2p_noa_index = -1;
++		sc->p2p_noa.noa_detect[vif_idx].last_rx = jiffies;
++		sc->p2p_noa.monitor_noa_vif |= 1 << vif_idx;
++		break;
++	case MONITOR_NOA_CONF_REMOVE:
++		sc->p2p_noa.monitor_noa_vif &= ~(1 << vif_idx);
++		sc->p2p_noa.noa_detect[vif_idx].noa_addr = NULL;
++		ssv6xxx_noa_host_stop_noa(sc, vif_idx);
++		break;
++	default:
++		break;
++	}
++	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
++}
++
++void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
++			  struct ssv6xxx_p2p_noa_param *p2p_noa_param)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int retry_cnt = 5;
++	skb =
++	    ssv_skb_alloc(HOST_CMD_HDR_LEN +
++			  sizeof(struct ssv6xxx_p2p_noa_param));
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, p2p_noa_param,
++	       sizeof(struct ssv6xxx_p2p_noa_param));
++	printk
++	    ("Noa cmd NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]vif[%d]\n\n",
++	     p2p_noa_param->enable, p2p_noa_param->interval,
++	     p2p_noa_param->duration, p2p_noa_param->start_time,
++	     p2p_noa_param->count, p2p_noa_param->addr[0],
++	     p2p_noa_param->addr[1], p2p_noa_param->addr[2],
++	     p2p_noa_param->addr[3], p2p_noa_param->addr[4],
++	     p2p_noa_param->addr[5], p2p_noa_param->vif_id);
++	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
++		printk(KERN_INFO "NOA cmd retry=%d!!\n", retry_cnt);
++		retry_cnt--;
++	}
++	ssv_skb_free(skb);
++}
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/p2p.h b/drivers/net/wireless/ssv6051/smac/p2p.h
+new file mode 100644
+index 000000000000..a5bb99c61bb0
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/p2p.h
+@@ -0,0 +1,58 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _P2P_H_
++#define _P2P_H_
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "drv_comm.h"
++#ifdef CONFIG_P2P_NOA
++#define P2P_MAX_NOA_INTERFACE 1
++struct ssv_p2p_noa_detect {
++	const u8 *noa_addr;
++	s16 p2p_noa_index;
++	unsigned long last_rx;
++	struct ssv6xxx_p2p_noa_param noa_param_cmd;
++};
++struct ssv_p2p_noa {
++	spinlock_t p2p_config_lock;
++	struct ssv_p2p_noa_detect noa_detect[SSV_NUM_VIF];
++	u8 active_noa_vif;
++	u8 monitor_noa_vif;
++};
++enum ssv_cmd_state {
++	SSC_CMD_STATE_IDLE,
++	SSC_CMD_STATE_WAIT_RSP,
++};
++struct ssv_cmd_Info {
++	struct sk_buff_head cmd_que;
++	struct sk_buff_head evt_que;
++	enum ssv_cmd_state state;
++};
++enum ssv6xxx_noa_conf {
++	MONITOR_NOA_CONF_ADD,
++	MONITOR_NOA_CONF_REMOVE,
++};
++struct ssv_softc;
++void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
++void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
++				enum ssv6xxx_noa_conf conf, u8 vif_idx);
++void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
++void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
++			u32 len);
++void ssv6xxx_noa_reset(struct ssv_softc *sc);
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/sar.c b/drivers/net/wireless/ssv6051/smac/sar.c
+new file mode 100644
+index 000000000000..44a47a5c7a0f
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/sar.c
+@@ -0,0 +1,208 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200_reg.h>
++#include <ssv6200_aux.h>
++#include <linux/fs.h>
++#include "dev.h"
++#include "sar.h"
++
++WIFI_FLASH_CCFG flash_cfg = {
++	//16bytes
++	0x6051, 0x3009, 0x20170519, 0x1, 0x0, 0x0,
++	{			//16bytes
++	 {0x47c000, 0x47c000, 0x47c000, 0x9, 0x1d, 0x0},
++	 //16bytes
++	 {0x79807980, 0x79807980, 0x79807980, 0x9, 0x1d, 0x0}
++	 }
++};
++
++WIFI_FLASH_CCFG *pflash_cfg;
++
++struct t_sar_info sar_info[] = {
++	{SAR_LVL_INVALID, 0x0047c000, NULL},
++	{SAR_LVL_INVALID, 0x79807980, NULL}
++};
++
++int sar_info_size = sizeof(sar_info) / sizeof(sar_info[0]);
++
++static u8 get_sar_lvl(u32 sar)
++{
++	static u32 prev_sar = 0;
++	int i;
++	u8 changed = 0x0;
++
++	if (sar == prev_sar)
++		return changed;
++
++	pr_debug("[thermal_sar] %d\n", (int)sar);
++
++	for (i = 0; i < sar_info_size; i++) {
++		if (sar_info[i].lvl == SAR_LVL_INVALID) {	//if driver loaded under LT/HT env, it would cause wrong settings at this time.
++			sar_info[i].lvl = SAR_LVL_RT;
++			sar_info[i].value = sar_info[i].p->rt;
++			changed |= BIT(i);
++		} else if (sar_info[i].lvl == SAR_LVL_RT) {
++			if (sar < prev_sar) {
++				if (sar <= (u32) (sar_info[i].p->lt_ts - 2)) {	//we need check if (g_tt_lt - 1) < SAR_MIN
++					sar_info[i].lvl = SAR_LVL_LT;
++					sar_info[i].value = sar_info[i].p->lt;
++					changed |= BIT(i);
++				}
++			} else if (sar > prev_sar) {
++				if (sar >= (u32) (sar_info[i].p->ht_ts + 2)) {	//we need check if (g_tt_lt + 1) > SAR_MAX
++					sar_info[i].lvl = SAR_LVL_HT;
++					sar_info[i].value = sar_info[i].p->ht;
++					changed |= BIT(i);
++				}
++			}
++		} else if (sar_info[i].lvl == SAR_LVL_LT) {
++			if (sar >= (u32) (sar_info[i].p->lt_ts + 2)) {
++				sar_info[i].lvl = SAR_LVL_RT;
++				sar_info[i].value = sar_info[i].p->rt;
++				changed |= BIT(i);
++			}
++		} else if (sar_info[i].lvl == SAR_LVL_HT) {
++			if (sar <= (u32) (sar_info[i].p->ht_ts - 2)) {
++				sar_info[i].lvl = SAR_LVL_RT;
++				sar_info[i].value = sar_info[i].p->rt;
++				changed |= BIT(i);
++			}
++		}
++	}
++	if (changed) {
++		pr_debug("changed: 0x%x\n", changed);
++	}
++	prev_sar = sar;
++	return changed;
++}
++
++void sar_monitor(u32 curr_sar, struct ssv_softc *sc)
++{
++	//static u32 prev_sar_lvl = SAR_LVL_INVALID; //sar = 0, temparature < -25C
++	u8 changed;
++	changed = get_sar_lvl(curr_sar);
++
++	if (changed & BIT(SAR_TXGAIN_INDEX)) {
++		dev_dbg(sc->dev, "TXGAIN: 0x%08x\n", sar_info[SAR_TXGAIN_INDEX].value);
++		SMAC_REG_WRITE(sc->sh, ADR_TX_GAIN_FACTOR,
++			       sar_info[SAR_TXGAIN_INDEX].value);
++	}
++	if (changed & BIT(SAR_XTAL_INDEX)) {
++		dev_dbg(sc->dev, "XTAL: 0x%08x\n", sar_info[SAR_XTAL_INDEX].value);
++		SMAC_REG_WRITE(sc->sh, ADR_SYN_KVCO_XO_FINE_TUNE_CBANK,
++			       sar_info[SAR_XTAL_INDEX].value);
++	}
++}
++
++/*
++    SET_RG_SARADC_THERMAL(1);     //ce010030[26]
++    SET_RG_EN_SARADC(1);          //ce010030[30]
++    while(!GET_SAR_ADC_FSM_RDY);  //ce010094[23]
++    sar_code = GET_RG_SARADC_BIT; //ce010094[21:16]
++    SET_RG_SARADC_THERMAL(0);
++    SET_RG_EN_SARADC(0);
++*/
++void thermal_monitor(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, thermal_monitor_work.work);
++	u32 curr_sar;
++
++	u32 temp;
++	if (sc->ps_status == PWRSV_PREPARE) {
++		dev_dbg(sc->dev, "sar PWRSV_PREPARE\n");
++		return;
++	}
++
++	mutex_lock(&sc->mutex);
++	SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_1, &temp);
++	if (temp == RX_11B_CCA_IN_SCAN) {
++		dev_dbg(sc->dev, "in scan\n");
++		mutex_unlock(&sc->mutex);
++		queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
++				   THERMAL_MONITOR_TIME);
++		return;
++	}
++	SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
++	//printk("ori %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
++			  (1 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (1 << RG_EN_SARADC_SFT),
++			  RG_EN_SARADC_MSK);
++
++	do {
++		msleep(1);
++		SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1, &temp);
++	} while (((temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT) != 1);
++	//printk("SAR_ADC_FSM_RDY_STAT %d\n", (temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT);
++	curr_sar = (temp & RG_SARADC_BIT_MSK) >> RG_SARADC_BIT_SFT;
++	SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
++
++	//printk("new %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
++
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
++			  (0 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (0 << RG_EN_SARADC_SFT),
++			  RG_EN_SARADC_MSK);
++	sar_monitor(curr_sar, sc);
++
++	mutex_unlock(&sc->mutex);
++
++	queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
++			   THERMAL_MONITOR_TIME);
++}
++
++int get_flash_info(struct ssv_softc *sc)
++{
++	struct file *fp = (struct file *)NULL;
++	int i, ret;
++
++	pflash_cfg = &flash_cfg;
++
++	if (sc->sh->cfg.flash_bin_path[0] != 0x00) {
++		fp = filp_open(sc->sh->cfg.flash_bin_path, O_RDONLY, 0);
++		if (IS_ERR(fp) || fp == NULL) {
++			fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
++		}
++	} else {
++		fp = filp_open(DEFAULT_CFG_BIN_NAME, O_RDONLY, 0);
++		if (IS_ERR(fp) || fp == NULL) {
++			fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
++		}
++	}
++	if (IS_ERR(fp) || fp == NULL) {
++		dev_info(sc->dev, "flash_file %s not found, disable sar\n",
++		       DEFAULT_CFG_BIN_NAME);
++		//WARN_ON(1);
++		ret = 0;
++		return ret;
++	}
++
++	fp->f_op->read(fp, (char *)pflash_cfg, sizeof(flash_cfg), &fp->f_pos);
++
++	filp_close(fp, NULL);
++	ret = 1;
++
++	for (i = 0; i < sar_info_size; i++) {
++		sar_info[i].p = &flash_cfg.sar_rlh[i];
++		dev_dbg(sc->dev, "rt = %x, lt = %x, ht = %x\n", sar_info[i].p->rt,
++		       sar_info[i].p->lt, sar_info[i].p->ht);
++		dev_dbg(sc->dev, "lt_ts = %x, ht_ts = %x\n", sar_info[i].p->lt_ts,
++		       sar_info[i].p->ht_ts);
++	}
++	return ret;
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/sar.h b/drivers/net/wireless/ssv6051/smac/sar.h
+new file mode 100644
+index 000000000000..291d58f236eb
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/sar.h
+@@ -0,0 +1,63 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _CFG_H_
++#define _CFG_H_
++#include <linux/kthread.h>
++
++#define SAR_XTAL_INDEX     (0)
++#define SAR_TXGAIN_INDEX    (1)
++#define THERMAL_MONITOR_TIME (10 * HZ)
++#define DEFAULT_CFG_BIN_NAME "/lib/firmware/ssv6051_sar.bin"
++#define SEC_CFG_BIN_NAME "/lib/firmware/ssv6xxx_sar.bin"
++enum {
++	SAR_LVL_LT,
++	SAR_LVL_RT,
++	SAR_LVL_HT,
++	SAR_LVL_INVALID
++};
++
++struct flash_thermal_info {
++	u32 rt;
++	u32 lt;
++	u32 ht;
++	u8 lt_ts;
++	u8 ht_ts;
++	u16 reserve;
++};
++typedef struct t_WIFI_FLASH_CCFG {
++	//16bytes
++	u16 chip_id;
++	u16 sid;
++	u32 date;
++	u16 version;
++	u16 reserve_1;
++	u32 reserve_2;
++	//16bytes
++	struct flash_thermal_info sar_rlh[2];
++} WIFI_FLASH_CCFG;
++
++struct t_sar_info {
++	u32 lvl;
++	u32 value;
++	struct flash_thermal_info *p;
++};
++
++void thermal_monitor(struct work_struct *work);
++int get_flash_info(struct ssv_softc *sc);
++void flash_hexdump(void);
++
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/sec.h b/drivers/net/wireless/ssv6051/smac/sec.h
+new file mode 100644
+index 000000000000..04a0f47c8ce2
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/sec.h
+@@ -0,0 +1,52 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef SEC_H
++#define SEC_H
++#include <linux/types.h>
++#include <linux/ieee80211.h>
++#include <net/mac80211.h>
++#define CCMP_TK_LEN 16
++#define TKIP_KEY_LEN 32
++#define WEP_KEY_LEN 13
++struct ssv_crypto_ops {
++	const char *name;
++	struct list_head list;
++	void *(*init)(int keyidx);
++	void (*deinit)(void *priv);
++	int (*encrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
++	int (*decrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
++	int (*encrypt_msdu)(struct sk_buff * skb, int hdr_len, void *priv);
++	int (*decrypt_msdu)(struct sk_buff * skb, int keyidx, int hdr_len,
++			    void *priv);
++	int (*set_tx_pn)(u8 * seq, void *priv);
++	int (*set_key)(void *key, int len, u8 * seq, void *priv);
++	int (*get_key)(void *key, int len, u8 * seq, void *priv);
++	char *(*print_stats)(char *p, void *priv);
++	unsigned long (*get_flags)(void *priv);
++	unsigned long (*set_flags)(unsigned long flags, void *priv);
++	int extra_mpdu_prefix_len, extra_mpdu_postfix_len;
++	int extra_msdu_prefix_len, extra_msdu_postfix_len;
++};
++struct ssv_crypto_data {
++	struct ssv_crypto_ops *ops;
++	void *priv;
++	rwlock_t lock;
++};
++struct ssv_crypto_ops *get_crypto_ccmp_ops(void);
++struct ssv_crypto_ops *get_crypto_tkip_ops(void);
++struct ssv_crypto_ops *get_crypto_wep_ops(void);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/smartlink.c b/drivers/net/wireless/ssv6051/smac/smartlink.c
+new file mode 100644
+index 000000000000..69e8d5118e09
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/smartlink.c
+@@ -0,0 +1,340 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <net/sock.h>
++#include <linux/socket.h>
++#include <linux/net.h>
++#include <asm/types.h>
++#include <linux/netlink.h>
++#include <linux/skbuff.h>
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "lib.h"
++#include "dev.h"
++#define NETLINK_SMARTLINK (31)
++#define MAX_PAYLOAD (2048)
++static struct sock *nl_sk = NULL;
++struct ssv_softc *ssv_smartlink_sc = NULL;
++EXPORT_SYMBOL(ssv_smartlink_sc);
++u32 ssv_smartlink_status = 0;
++static int _ksmartlink_start_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				       u32 * pOutBufLen)
++{
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	ssv_smartlink_status = 1;
++	*pOutBufLen = 0;
++	return 0;
++}
++
++int ksmartlink_smartlink_started(void)
++{
++	return ssv_smartlink_status;
++}
++
++EXPORT_SYMBOL(ksmartlink_smartlink_started);
++static int _ksmartlink_stop_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				      u32 * pOutBufLen)
++{
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	ssv_smartlink_status = 0;
++	*pOutBufLen = 0;
++	return 0;
++}
++
++static int _ksmartlink_set_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int ch = (int)(*pInBuf);
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_set_channel(sc, ch);
++	mutex_unlock(&sc->mutex);
++	*pOutBufLen = 0;
++ out:
++	return ret;
++}
++
++static int _ksmartlink_get_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int ch = 0;
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_get_channel(sc, &ch);
++	mutex_unlock(&sc->mutex);
++	*pOutBuf = ch;
++	*pOutBufLen = 1;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
++#endif
++ out:
++	return ret;
++}
++
++static int _ksmartlink_set_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int accept = (int)(*pInBuf);
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_set_promisc(sc, accept);
++	mutex_unlock(&sc->mutex);
++	*pOutBufLen = 0;
++ out:
++	return ret;
++}
++
++static int _ksmartlink_get_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int accept = (int)(*pInBuf);
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_get_promisc(sc, &accept);
++	mutex_unlock(&sc->mutex);
++	*pOutBuf = accept;
++	*pOutBufLen = 1;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
++#endif
++ out:
++	return ret;
++}
++
++#define SMARTLINK_CMD_FIXED_LEN (10)
++#define SMARTLINK_CMD_FIXED_TOT_LEN (SMARTLINK_CMD_FIXED_LEN+1)
++#define SMARTLINK_RES_FIXED_LEN (SMARTLINK_CMD_FIXED_LEN)
++#define SMARTLINK_RES_FIXED_TOT_LEN (SMARTLINK_RES_FIXED_LEN+2)
++struct ksmartlink_cmd {
++	char *cmd;
++	int (*process_func)(u8 *, u32, u8 *, u32 *);
++};
++static struct ksmartlink_cmd _ksmartlink_cmd_table[] = {
++	{"startairki", _ksmartlink_start_smartlink},
++	{"stopairkis", _ksmartlink_stop_smartlink},
++	{"setchannel", _ksmartlink_set_channel},
++	{"getchannel", _ksmartlink_get_channel},
++	{"setpromisc", _ksmartlink_set_promisc},
++	{"getpromisc", _ksmartlink_get_promisc},
++};
++
++static u32 _ksmartlink_cmd_table_size =
++    sizeof(_ksmartlink_cmd_table) / sizeof(struct ksmartlink_cmd);
++#ifdef KSMARTLINK_DEBUG
++static void _ksmartlink_hex_dump(u8 * pInBuf, u32 inBufLen)
++{
++	u32 i = 0;
++	printk(KERN_INFO "\nKernel Hex Dump(len=%d):\n", inBufLen);
++	printk(KERN_INFO ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
++	for (i = 0; i < inBufLen; i++) {
++		if ((i) && ((i & 0xf) == 0)) {
++			printk("\n");
++		}
++		printk("%02x ", pInBuf[i]);
++	}
++	printk(KERN_INFO "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
++}
++#endif
++static int _ksmartlink_process_msg(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = 0;
++	u32 i = 0;
++	struct ksmartlink_cmd *pCmd;
++	if (!pInBuf || !pOutBuf || !pOutBufLen) {
++		printk(KERN_ERR "NULL pointer\n");
++		return -1;
++	}
++	for (i = 0; i < _ksmartlink_cmd_table_size; i++) {
++		if (!strncmp
++		    (_ksmartlink_cmd_table[i].cmd, pInBuf,
++		     SMARTLINK_CMD_FIXED_LEN)) {
++			break;
++		}
++	}
++	if (i < _ksmartlink_cmd_table_size) {
++		pCmd = &_ksmartlink_cmd_table[i];
++		if (!pCmd->process_func) {
++			printk(KERN_ERR "CMD %s has NULL process_func\n",
++			       pCmd->cmd);
++			return -3;
++		}
++		ret =
++		    pCmd->process_func(pInBuf + SMARTLINK_CMD_FIXED_LEN,
++				       inBufLen, pOutBuf, pOutBufLen);
++#ifdef CONFIG_SSV_NETLINK_RESPONSE
++		if (ret < 0) {
++			*pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
++		} else {
++			if (*pOutBufLen > 0) {
++				pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
++				pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = *pOutBuf;
++			} else {
++				pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
++				pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = 0;
++			}
++			*pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
++		}
++		memcpy(pOutBuf, pCmd->cmd, SMARTLINK_RES_FIXED_LEN);
++#else
++		(void)pOutBuf;
++		(void)pOutBufLen;
++#endif
++		return 0;
++	} else {
++		printk(KERN_INFO "Unknow CMD or Packet?\n");
++	}
++	return 0;
++}
++static u8 gkBuf[MAX_PAYLOAD] = { 0 };
++
++static int ssv_usr_pid = 0;
++void smartlink_nl_recv_msg(struct sk_buff *skb)
++{
++	struct nlmsghdr *nlh;
++#ifdef CONFIG_SSV_NETLINK_RESPONSE
++	struct sk_buff *skb_out;
++#endif
++	int ret = 0;
++	u8 *pInBuf = NULL;
++	u32 inBufLen = 0;
++	u32 outBufLen = 0;
++	nlh = (struct nlmsghdr *)skb->data;
++	ssv_usr_pid = nlh->nlmsg_pid;
++	pInBuf = (u8 *) nlmsg_data(nlh);
++	inBufLen = nlmsg_len(nlh);
++#ifdef KSMARTLINK_DEBUG
++	_ksmartlink_hex_dump(pInBuf, inBufLen);
++#endif
++	outBufLen = 0;
++	memset(gkBuf, 0, MAX_PAYLOAD);
++	ret = _ksmartlink_process_msg(pInBuf, inBufLen, gkBuf, &outBufLen);
++#ifdef CONFIG_SSV_NETLINK_RESPONSE
++	if (outBufLen == 0) {
++		memcpy(gkBuf, "Nothing", 8);
++		outBufLen = strlen(gkBuf);
++	}
++	skb_out = nlmsg_new(outBufLen, 0);
++	if (!skb_out) {
++		printk(KERN_ERR "Failed to allocate new skb\n");
++		return;
++	}
++	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
++	NETLINK_CB(skb_out).dst_group = 0;
++	memcpy(nlmsg_data(nlh), gkBuf, outBufLen);
++	ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
++	if (ret < 0) {
++		printk(KERN_ERR "Error while sending bak to user\n");
++	}
++#endif
++	return;
++}
++
++void smartlink_nl_send_msg(struct sk_buff *skb)
++{
++	struct nlmsghdr *nlh;
++	struct sk_buff *skb_out;
++	int ret = 0;
++	u8 *pOutBuf = skb->data;
++	u32 outBufLen = skb->len;
++#ifdef KSMARTLINK_DEBUG
++#endif
++	skb_out = nlmsg_new(outBufLen, 0);
++	if (!skb_out) {
++		printk(KERN_ERR "Allocate new skb failed!\n");
++		return;
++	}
++	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
++	NETLINK_CB(skb_out).dst_group = 0;
++	memcpy(nlmsg_data(nlh), pOutBuf, outBufLen);
++	ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
++	if (ret < 0) {
++		printk(KERN_ERR "nlmsg_unicast failed!\n");
++	}
++	kfree_skb(skb);
++	return;
++}
++
++EXPORT_SYMBOL(smartlink_nl_send_msg);
++int ksmartlink_init(void)
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)
++	nl_sk = netlink_kernel_create(&init_net,
++				      NETLINK_SMARTLINK,
++				      0,
++				      smartlink_nl_recv_msg, NULL, THIS_MODULE);
++#else
++	struct netlink_kernel_cfg cfg = {
++		.groups = 0,
++		.input = smartlink_nl_recv_msg,
++	};
++	nl_sk = netlink_kernel_create(&init_net, NETLINK_SMARTLINK, &cfg);
++#endif
++	printk(KERN_INFO "***************SmartLink Init-S**************\n");
++	if (!nl_sk) {
++		printk(KERN_ERR "Error creating socket.\n");
++		return -10;
++	}
++	printk(KERN_INFO "***************SmartLink Init-E**************\n");
++	return 0;
++}
++
++void ksmartlink_exit(void)
++{
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++	if (nl_sk) {
++		netlink_kernel_release(nl_sk);
++		nl_sk = NULL;
++	}
++}
++
++EXPORT_SYMBOL(ksmartlink_init);
++EXPORT_SYMBOL(ksmartlink_exit);
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
+new file mode 100644
+index 000000000000..9be5ea96e7f9
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
+@@ -0,0 +1,223 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ssv6xxx_debugfs.h"
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++#define QUEUE_STATUS_BUF_SIZE (4096)
++static ssize_t queue_status_read(struct file *file,
++				 char __user * user_buf, size_t count,
++				 loff_t * ppos)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)file->private_data;
++	char *status_buf = kzalloc(QUEUE_STATUS_BUF_SIZE, GFP_KERNEL);
++	ssize_t status_size;
++	ssize_t ret;
++	if (!status_buf)
++		return -ENOMEM;
++	status_size = ssv6xxx_tx_queue_status_dump(sc, status_buf,
++						   QUEUE_STATUS_BUF_SIZE);
++	ret = simple_read_from_buffer(user_buf, count, ppos, status_buf,
++				      status_size);
++	kfree(status_buf);
++	return ret;
++}
++
++static int queue_status_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static const struct file_operations queue_status_fops
++    = {.read = queue_status_read,
++	.open = queue_status_open
++};
++#endif
++int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ieee80211_hw *hw = sc->hw;
++	struct dentry *phy_debugfs_dir = hw->wiphy->debugfsdir;
++	struct dentry *drv_debugfs_dir;
++	drv_debugfs_dir = debugfs_create_dir(name, phy_debugfs_dir);
++	if (!drv_debugfs_dir) {
++		dev_err(sc->dev, "Failed to create debugfs.\n");
++		return -ENOMEM;
++	}
++	sc->debugfs_dir = drv_debugfs_dir;
++	sc->sh->hci.hci_ops->hci_init_debugfs(sc->debugfs_dir);
++	debugfs_create_file("queue_status", 00444, drv_debugfs_dir,
++			    sc, &queue_status_fops);
++#endif
++	return 0;
++}
++
++void ssv6xxx_deinit_debugfs(struct ssv_softc *sc)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (!sc->debugfs_dir)
++		return;
++	sc->sh->hci.hci_ops->hci_deinit_debugfs();
++	debugfs_remove_recursive(sc->debugfs_dir);
++	sc->debugfs_dir = NULL;
++#endif
++}
++
++int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
++				  struct ieee80211_vif *vif)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *drv_debugfs_dir = sc->debugfs_dir;
++	struct dentry *vif_debugfs_dir;
++	char vif_addr[18];
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	snprintf(vif_addr, sizeof(vif_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
++		 vif->addr[0], vif->addr[1], vif->addr[2],
++		 vif->addr[3], vif->addr[4], vif->addr[5]);
++	vif_debugfs_dir = debugfs_create_dir(vif_addr, drv_debugfs_dir);
++	if (!vif_debugfs_dir) {
++		dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
++			vif_addr);
++		return -ENOMEM;
++	}
++	sc->debugfs_dir = drv_debugfs_dir;
++	vif_info->debugfs_dir = vif_debugfs_dir;
++#endif
++	return 0;
++}
++
++int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	if ((vif_info->debugfs_dir == NULL) || (sc->debugfs_dir == NULL))
++		return 0;
++	debugfs_remove_recursive(vif_info->debugfs_dir);
++	vif_info->debugfs_dir = NULL;
++#endif
++	return 0;
++}
++
++int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)sta->vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	if ((sc->debugfs_dir == NULL) || (vif_info->debugfs_dir == NULL)
++	    || (sta->debugfs_dir == NULL))
++		return 0;
++	debugfs_remove_recursive(sta->debugfs_dir);
++	sta->debugfs_dir = NULL;
++#endif
++	return 0;
++}
++
++int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)sta->vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	struct dentry *vif_debugfs_dir = vif_info->debugfs_dir;
++	struct dentry *sta_debugfs_dir;
++	char sta_addr[18];
++	if (vif_debugfs_dir == NULL)
++		return 0;
++	snprintf(sta_addr, sizeof(sta_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
++		 sta->sta->addr[0], sta->sta->addr[1], sta->sta->addr[2],
++		 sta->sta->addr[3], sta->sta->addr[4], sta->sta->addr[5]);
++	sta_debugfs_dir = debugfs_create_dir(sta_addr, vif_debugfs_dir);
++	if (!sta_debugfs_dir) {
++		dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
++			sta_addr);
++		return -ENOMEM;
++	}
++	sta->debugfs_dir = sta_debugfs_dir;
++#endif
++	return 0;
++}
++
++#define DEBUGFS_ADD_FILE(name,parent,mode) do { \
++    if (!debugfs_create_file(#name, mode, parent, priv, \
++                 &ssv_dbgfs_##name##_ops)) \
++        goto err; \
++} while (0)
++#define DEBUGFS_ADD_BOOL(name,parent,ptr) do { \
++    struct dentry *__tmp; \
++    __tmp = debugfs_create_bool(#name, S_IWUSR | S_IRUSR, \
++                    parent, ptr); \
++    if (IS_ERR(__tmp) || !__tmp) \
++        goto err; \
++} while (0)
++#define DEBUGFS_ADD_X32(name,parent,ptr) do { \
++    struct dentry *__tmp; \
++    __tmp = debugfs_create_x32(#name, S_IWUSR | S_IRUSR, \
++                   parent, ptr); \
++    if (IS_ERR(__tmp) || !__tmp) \
++        goto err; \
++} while (0)
++#define DEBUGFS_ADD_U32(name,parent,ptr,mode) do { \
++    struct dentry *__tmp; \
++    __tmp = debugfs_create_u32(#name, mode, \
++                   parent, ptr); \
++    if (IS_ERR(__tmp) || !__tmp) \
++        goto err; \
++} while (0)
++#define DEBUGFS_READ_FUNC(name) \
++static ssize_t ssv_dbgfs_##name##_read(struct file *file, \
++                    char __user *user_buf, \
++                    size_t count, loff_t *ppos);
++#define DEBUGFS_WRITE_FUNC(name) \
++static ssize_t ssv_dbgfs_##name##_write(struct file *file, \
++                    const char __user *user_buf, \
++                    size_t count, loff_t *ppos);
++#define DEBUGFS_READ_FILE_OPS(name) \
++    DEBUGFS_READ_FUNC(name); \
++static const struct file_operations ssv_dbgfs_##name##_ops = { \
++    .read = ssv_dbgfs_##name##_read, \
++    .open = ssv_dbgfs_open_file_generic, \
++    .llseek = generic_file_llseek, \
++};
++#define DEBUGFS_WRITE_FILE_OPS(name) \
++    DEBUGFS_WRITE_FUNC(name); \
++static const struct file_operations ssv_dbgfs_##name##_ops = { \
++    .write = ssv_dbgfs_##name##_write, \
++    .open = ssv_dbgfs_open_file_generic, \
++    .llseek = generic_file_llseek, \
++};
++#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
++    DEBUGFS_READ_FUNC(name); \
++    DEBUGFS_WRITE_FUNC(name); \
++static const struct file_operations ssv_dbgfs_##name##_ops = { \
++    .write = ssv_dbgfs_##name##_write, \
++    .read = ssv_dbgfs_##name##_read, \
++    .open = ssv_dbgfs_open_file_generic, \
++    .llseek = generic_file_llseek, \
++};
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
+new file mode 100644
+index 000000000000..39caceadda4a
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __SSV6XXX_DBGFS_H__
++#define __SSV6XXX_DBGFS_H__
++int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name);
++void ssv6xxx_deinit_debugfs(struct ssv_softc *sc);
++int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif);
++int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
++				  struct ieee80211_vif *vif);
++int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
++int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
+new file mode 100644
+index 000000000000..f0135447b1f3
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
+@@ -0,0 +1,1384 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2018 icomm Corporation. All rights reserved.
++ *                                        
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#include "dev.h"
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
++
++#include <linux/kernel.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#include <linux/sched.h>
++#include <linux/etherdevice.h>
++#include <linux/wireless.h>
++#include <linux/ieee80211.h>
++#include <linux/wait.h>
++#include <net/cfg80211.h>
++
++#include <net/rtnetlink.h>
++#include "ssv_cfgvendor.h"
++
++#define wiphy_to_softc(x) (*((struct ssv_softc**)wiphy_priv(x)))
++#define FUNC_NDEV_FMT "%s"
++#define FUNC_NDEV_ARG(ndev) __func__
++
++#define _drv_always_		1
++#define _drv_emerg_			2
++#define _drv_alert_			3
++#define _drv_crit_			4
++#define _drv_err_			5
++#define _drv_warning_		6
++#define _drv_notice_		7
++#define _drv_info_			8
++#define _drv_dump_			9
++#define _drv_debug_			10
++
++struct sk_buff *ssv_cfg80211_vendor_event_alloc(struct wiphy *wiphy, int len,
++						int event_id, gfp_t gfp)
++{
++	struct sk_buff *skb;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
++	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len, event_id, gfp);
++#endif
++	return skb;
++}
++
++#define ssv_cfg80211_vendor_event(skb, gfp) \
++	cfg80211_vendor_event(skb, gfp)
++
++#define ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
++	cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len)
++
++#define ssv_cfg80211_vendor_cmd_reply(skb) \
++	cfg80211_vendor_cmd_reply(skb)
++
++/*
++ * This API is to be used for asynchronous vendor events. This
++ * shouldn't be used in response to a vendor command from its
++ * do_it handler context (instead ssv_cfgvendor_send_cmd_reply should
++ * be used).
++ */
++int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
++				   struct net_device *dev, int event_id,
++				   const void *data, int len)
++{
++	u16 kflags;
++	struct sk_buff *skb;
++
++	kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_event_alloc(wiphy, len, event_id, kflags);
++	if (!skb) {
++		dev_err(&wiphy->dev, "skb alloc failed\n");
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	ssv_cfg80211_vendor_event(skb, kflags);
++
++	return 0;
++}
++
++static int ssv_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
++					struct net_device *dev,
++					const void *data, int len)
++{
++	struct sk_buff *skb;
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
++	if (unlikely(!skb)) {
++		dev_err(&wiphy->dev, "skb alloc failed");
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	return ssv_cfg80211_vendor_cmd_reply(skb);
++}
++
++#define WIFI_FEATURE_INFRA              0x0001	/* Basic infrastructure mode        */
++#define WIFI_FEATURE_INFRA_5G           0x0002	/* Support for 5 GHz Band           */
++#define WIFI_FEATURE_HOTSPOT            0x0004	/* Support for GAS/ANQP             */
++#define WIFI_FEATURE_P2P                0x0008	/* Wifi-Direct                      */
++#define WIFI_FEATURE_SOFT_AP            0x0010	/* Soft AP                          */
++#define WIFI_FEATURE_GSCAN              0x0020	/* Google-Scan APIs                 */
++#define WIFI_FEATURE_NAN                0x0040	/* Neighbor Awareness Networking    */
++#define WIFI_FEATURE_D2D_RTT            0x0080	/* Device-to-device RTT             */
++#define WIFI_FEATURE_D2AP_RTT           0x0100	/* Device-to-AP RTT                 */
++#define WIFI_FEATURE_BATCH_SCAN         0x0200	/* Batched Scan (legacy)            */
++#define WIFI_FEATURE_PNO                0x0400	/* Preferred network offload        */
++#define WIFI_FEATURE_ADDITIONAL_STA     0x0800	/* Support for two STAs             */
++#define WIFI_FEATURE_TDLS               0x1000	/* Tunnel directed link setup       */
++#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000	/* Support for TDLS off channel     */
++#define WIFI_FEATURE_EPR                0x4000	/* Enhanced power reporting         */
++#define WIFI_FEATURE_AP_STA             0x8000	/* Support for AP STA Concurrency   */
++
++#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3
++
++int ssv_dev_get_feature_set(struct net_device *dev)
++{
++	int feature_set = 0;
++
++	feature_set |= WIFI_FEATURE_INFRA;
++
++	feature_set |= WIFI_FEATURE_P2P;
++	feature_set |= WIFI_FEATURE_SOFT_AP;
++
++#if defined(GSCAN_SUPPORT)
++	feature_set |= WIFI_FEATURE_GSCAN;
++#endif
++
++#if defined(RTT_SUPPORT)
++	feature_set |= WIFI_FEATURE_NAN;
++	feature_set |= WIFI_FEATURE_D2D_RTT;
++	feature_set |= WIFI_FEATURE_D2AP_RTT;
++#endif
++
++	return feature_set;
++}
++
++int *ssv_dev_get_feature_set_matrix(struct net_device *dev, int *num)
++{
++	int feature_set_full, mem_needed;
++	int *ret;
++
++	*num = 0;
++	mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;
++	ret =
++	    (int *)kmalloc(mem_needed, in_interrupt()? GFP_ATOMIC : GFP_KERNEL);
++
++	if (!ret) {
++		dev_err(&dev->dev, "failed to allocate %d bytes\n", mem_needed);
++		return ret;
++	}
++
++	feature_set_full = ssv_dev_get_feature_set(dev);
++
++	ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	    (feature_set_full & WIFI_FEATURE_NAN) |
++	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	    (feature_set_full & WIFI_FEATURE_PNO) |
++	    (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
++	    (feature_set_full & WIFI_FEATURE_GSCAN) |
++	    (feature_set_full & WIFI_FEATURE_HOTSPOT) |
++	    (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |
++	    (feature_set_full & WIFI_FEATURE_EPR);
++
++	ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	    /* Not yet verified NAN with P2P */
++	    /* (feature_set_full & WIFI_FEATURE_NAN) | */
++	    (feature_set_full & WIFI_FEATURE_P2P) |
++	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	    (feature_set_full & WIFI_FEATURE_EPR);
++
++	ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	    (feature_set_full & WIFI_FEATURE_NAN) |
++	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	    (feature_set_full & WIFI_FEATURE_TDLS) |
++	    (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |
++	    (feature_set_full & WIFI_FEATURE_EPR);
++	*num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;
++
++	return ret;
++}
++
++#define wdev_to_ndev(wdev) NULL
++
++static int ssv_cfgvendor_get_feature_set(struct wiphy *wiphy,
++					 struct wireless_dev *wdev,
++					 const void *data, int len)
++{
++	int err = 0;
++	int reply;
++
++	reply = ssv_dev_get_feature_set(wdev_to_ndev(wdev));
++
++	err =
++	    ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply,
++					 sizeof(int));
++
++	if (unlikely(err))
++		dev_err(&wiphy->dev, "vendor Command reply failed, ret:%d\n", err);
++
++	return err;
++}
++
++static int ssv_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
++						struct wireless_dev *wdev,
++						const void *data, int len)
++{
++	int err = 0;
++	struct sk_buff *skb;
++	int *reply;
++	int num, mem_needed, i;
++
++	reply = ssv_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num);
++
++	if (!reply) {
++		dev_err(&wiphy->dev, "could not get feature list matrix\n");
++		err = -EINVAL;
++		return err;
++	}
++
++	mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +
++	    ATTRIBUTE_U32_LEN;
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		dev_err(&wiphy->dev, "skb alloc failed\n");
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);
++	for (i = 0; i < num; i++) {
++		nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);
++	}
++
++	err = ssv_cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err))
++		dev_err(&wiphy->dev, "vendor Command reply failed, ret=%d\n", err);
++ exit:
++	kfree((void *)reply);
++	return err;
++}
++
++#if defined(GSCAN_SUPPORT) && 0
++int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++				    struct net_device *dev, void *data, int len,
++				    wl_vendor_event_t event)
++{
++	u16 kflags;
++	const void *ptr;
++	struct sk_buff *skb;
++	int malloc_len, total, iter_cnt_to_send, cnt;
++	gscan_results_cache_t *cache = (gscan_results_cache_t *) data;
++
++	total = len / sizeof(wifi_gscan_result_t);
++	while (total > 0) {
++		malloc_len =
++		    (total * sizeof(wifi_gscan_result_t)) +
++		    VENDOR_DATA_OVERHEAD;
++		if (malloc_len > NLMSG_DEFAULT_SIZE) {
++			malloc_len = NLMSG_DEFAULT_SIZE;
++		}
++		iter_cnt_to_send =
++		    (malloc_len -
++		     VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t);
++		total = total - iter_cnt_to_send;
++
++		kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
++
++		/* Alloc the SKB for vendor_event */
++		skb =
++		    ssv_cfg80211_vendor_event_alloc(wiphy, malloc_len, event,
++						    kflags);
++		if (!skb) {
++			WL_ERR(("skb alloc failed"));
++			return -ENOMEM;
++		}
++
++		while (cache && iter_cnt_to_send) {
++			ptr =
++			    (const void *)&cache->results[cache->tot_consumed];
++
++			if (iter_cnt_to_send <
++			    (cache->tot_count - cache->tot_consumed))
++				cnt = iter_cnt_to_send;
++			else
++				cnt = (cache->tot_count - cache->tot_consumed);
++
++			iter_cnt_to_send -= cnt;
++			cache->tot_consumed += cnt;
++			/* Push the data to the skb */
++			nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
++			if (cache->tot_consumed == cache->tot_count)
++				cache = cache->next;
++
++		}
++
++		ssv_cfg80211_vendor_event(skb, kflags);
++	}
++
++	return 0;
++}
++
++static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
++					       struct wireless_dev *wdev,
++					       const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pno_gscan_capabilities_t *reply = NULL;
++	uint32 reply_len = 0;
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_GET_CAPABILITIES, NULL,
++				      &reply_len);
++	if (!reply) {
++		WL_ERR(("Could not get capabilities\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++					   reply, reply_len);
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++
++	kfree(reply);
++	return err;
++}
++
++static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
++					       struct wireless_dev *wdev,
++					       const void *data, int len)
++{
++	int err = 0, type, band;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	uint16 *reply = NULL;
++	uint32 reply_len = 0, num_channels, mem_needed;
++	struct sk_buff *skb;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_BAND) {
++		band = nla_get_u32(data);
++	} else {
++		return -1;
++	}
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_GET_CHANNEL_LIST, &band,
++				      &reply_len);
++
++	if (!reply) {
++		WL_ERR(("Could not get channel list\n"));
++		err = -EINVAL;
++		return err;
++	}
++	num_channels = reply_len / sizeof(uint32);
++	mem_needed =
++	    reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
++	nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
++
++	err = ssv_cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++ exit:
++	kfree(reply);
++	return err;
++}
++
++static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
++						struct wireless_dev *wdev,
++						const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_results_cache_t *results, *iter;
++	uint32 reply_len, complete = 0, num_results_iter;
++	int32 mem_needed;
++	wifi_gscan_result_t *ptr;
++	uint16 num_scan_ids, num_results;
++	struct sk_buff *skb;
++	struct nlattr *scan_hdr;
++
++	dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
++	dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++	results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++					DHD_PNO_GET_BATCH_RESULTS, NULL,
++					&reply_len);
++
++	if (!results) {
++		WL_ERR(("No results to send %d\n", err));
++		err =
++		    ssv_cfgvendor_send_cmd_reply(wiphy,
++						 bcmcfg_to_prmry_ndev(cfg),
++						 results, 0);
++
++		if (unlikely(err))
++			WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
++							(cfg));
++		return err;
++	}
++	num_scan_ids = reply_len & 0xFFFF;
++	num_results = (reply_len & 0xFFFF0000) >> 16;
++	mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
++	    (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
++	    VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
++
++	if (mem_needed > (int32) NLMSG_DEFAULT_SIZE) {
++		mem_needed = (int32) NLMSG_DEFAULT_SIZE;
++		complete = 0;
++	} else {
++		complete = 1;
++	}
++
++	WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete,
++		  mem_needed, (int)NLMSG_DEFAULT_SIZE));
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
++							(cfg));
++		return -ENOMEM;
++	}
++	iter = results;
++
++	nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete);
++
++	mem_needed =
++	    mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN +
++			  VENDOR_REPLY_OVERHEAD);
++
++	while (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) > 0)) {
++		scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
++		nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
++		num_results_iter =
++		    (mem_needed -
++		     GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t);
++
++		if ((iter->tot_count - iter->tot_consumed) < num_results_iter)
++			num_results_iter = iter->tot_count - iter->tot_consumed;
++
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS,
++			    num_results_iter);
++		if (num_results_iter) {
++			ptr = &iter->results[iter->tot_consumed];
++			iter->tot_consumed += num_results_iter;
++			nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
++				num_results_iter * sizeof(wifi_gscan_result_t),
++				ptr);
++		}
++		nla_nest_end(skb, scan_hdr);
++		mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
++		    (num_results_iter * sizeof(wifi_gscan_result_t));
++		iter = iter->next;
++	}
++
++	dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
++	dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++
++	return ssv_cfg80211_vendor_cmd_reply(skb);
++}
++
++static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy,
++				       struct wireless_dev *wdev,
++				       const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type, tmp = len;
++	int run = 0xFF;
++	int flush = 0;
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
++			run = nla_get_u32(iter);
++		else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
++			flush = nla_get_u32(iter);
++	}
++
++	if (run != 0xFF) {
++		err =
++		    dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run,
++					  flush);
++
++		if (unlikely(err))
++			WL_ERR(("Could not run gscan:%d \n", err));
++		return err;
++	} else {
++		return -1;
++	}
++
++}
++
++static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
++						struct wireless_dev *wdev,
++						const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	bool real_time = FALSE;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
++		real_time = nla_get_u32(data);
++
++		err =
++		    dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev
++							(cfg), real_time);
++
++		if (unlikely(err))
++			WL_ERR(("Could not run gscan:%d \n", err));
++
++	} else {
++		err = -1;
++	}
++
++	return err;
++}
++
++static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy,
++				     struct wireless_dev *wdev,
++				     const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_scan_params_t *scan_param;
++	int j = 0;
++	int type, tmp, tmp1, tmp2, k = 0;
++	const struct nlattr *iter, *iter1, *iter2;
++	struct dhd_pno_gscan_channel_bucket *ch_bucket;
++
++	scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
++	if (!scan_param) {
++		WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
++		err = -EINVAL;
++		return err;
++
++	}
++
++	scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		if (j >= GSCAN_MAX_CH_BUCKETS)
++			break;
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_BASE_PERIOD:
++			scan_param->scan_fr = nla_get_u32(iter) / 1000;
++			break;
++		case GSCAN_ATTRIBUTE_NUM_BUCKETS:
++			scan_param->nchannel_buckets = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_CH_BUCKET_1:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_2:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_3:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_4:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_5:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_6:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_7:
++			nla_for_each_nested(iter1, iter, tmp1) {
++				type = nla_type(iter1);
++				ch_bucket = scan_param->channel_bucket;
++
++				switch (type) {
++				case GSCAN_ATTRIBUTE_BUCKET_ID:
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
++					ch_bucket[j].bucket_freq_multiple =
++					    nla_get_u32(iter1) / 1000;
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
++					ch_bucket[j].num_channels =
++					    nla_get_u32(iter1);
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
++					nla_for_each_nested(iter2, iter1, tmp2) {
++						if (k >=
++						    PFN_SWC_RSSI_WINDOW_MAX)
++							break;
++						ch_bucket[j].chan_list[k] =
++						    nla_get_u32(iter2);
++						k++;
++					}
++					k = 0;
++					break;
++				case GSCAN_ATTRIBUTE_BUCKETS_BAND:
++					ch_bucket[j].band = (uint16)
++					    nla_get_u32(iter1);
++					break;
++				case GSCAN_ATTRIBUTE_REPORT_EVENTS:
++					ch_bucket[j].report_flag = (uint8)
++					    nla_get_u32(iter1);
++					break;
++				}
++			}
++			j++;
++			break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {
++		WL_ERR(("Could not set GSCAN scan cfg\n"));
++		err = -EINVAL;
++	}
++
++	kfree(scan_param);
++	return err;
++
++}
++
++static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
++				    struct wireless_dev *wdev, const void *data,
++				    int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_hotlist_scan_params_t *hotlist_params;
++	int tmp, tmp1, tmp2, type, j = 0, dummy;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0;
++	struct bssid_t *pbssid;
++
++	hotlist_params =
++	    (gscan_hotlist_scan_params_t *) kzalloc(len, GFP_KERNEL);
++	if (!hotlist_params) {
++		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
++		return -1;
++	}
++
++	hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++		case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
++			pbssid = hotlist_params->bssid;
++			nla_for_each_nested(outer, iter, tmp) {
++				nla_for_each_nested(inner, outer, tmp1) {
++					type = nla_type(inner);
++
++					switch (type) {
++					case GSCAN_ATTRIBUTE_BSSID:
++						memcpy(&(pbssid[j].macaddr),
++						       nla_data(inner),
++						       ETHER_ADDR_LEN);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_LOW:
++						pbssid[j].
++						    rssi_reporting_threshold =
++						    (int8) nla_get_u8(inner);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_HIGH:
++						dummy =
++						    (int8) nla_get_u8(inner);
++						break;
++					}
++				}
++				j++;
++			}
++			hotlist_params->nbssid = j;
++			break;
++		case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
++			flush = nla_get_u8(iter);
++			break;
++		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++			hotlist_params->lost_ap_window = nla_get_u32(iter);
++			break;
++		}
++
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_GEOFENCE_SCAN_CFG_ID,
++				      hotlist_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN HOTLIST cfg\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++ exit:
++	kfree(hotlist_params);
++	return err;
++}
++
++static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
++					   struct wireless_dev *wdev,
++					   const void *data, int len)
++{
++	int err = 0, tmp, type;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_batch_params_t batch_param;
++	const struct nlattr *iter;
++
++	batch_param.mscan = batch_param.bestn = 0;
++	batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
++			batch_param.bestn = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
++			batch_param.mscan = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
++			batch_param.buffer_threshold = nla_get_u32(iter);
++			break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param,
++				      0) < 0) {
++		WL_ERR(("Could not set batch cfg\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	return err;
++}
++
++static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy,
++					       struct wireless_dev *wdev,
++					       const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_swc_params_t *significant_params;
++	int tmp, tmp1, tmp2, type, j = 0;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0;
++	wl_pfn_significant_bssid_t *pbssid;
++
++	significant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL);
++	if (!significant_params) {
++		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
++		return -1;
++	}
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:
++			flush = nla_get_u8(iter);
++			break;
++		case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:
++			significant_params->rssi_window = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++			significant_params->lost_ap_window = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_MIN_BREACHING:
++			significant_params->swc_threshold = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:
++			pbssid = significant_params->bssid_elem_list;
++			nla_for_each_nested(outer, iter, tmp) {
++				nla_for_each_nested(inner, outer, tmp1) {
++					switch (nla_type(inner)) {
++					case GSCAN_ATTRIBUTE_BSSID:
++						memcpy(&(pbssid[j].macaddr),
++						       nla_data(inner),
++						       ETHER_ADDR_LEN);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_HIGH:
++						pbssid[j].rssi_high_threshold =
++						    (int8) nla_get_u8(inner);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_LOW:
++						pbssid[j].rssi_low_threshold =
++						    (int8) nla_get_u8(inner);
++						break;
++					}
++				}
++				j++;
++			}
++			break;
++		}
++	}
++	significant_params->nbssid = j;
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_SIGNIFICANT_SCAN_CFG_ID,
++				      significant_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN significant cfg\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++ exit:
++	kfree(significant_params);
++	return err;
++}
++#endif				/* GSCAN_SUPPORT */
++
++#if defined(RTT_SUPPORT) && 0
++void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
++{
++	struct wireless_dev *wdev = (struct wireless_dev *)ctx;
++	struct wiphy *wiphy;
++	struct sk_buff *skb;
++	uint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0;
++	gfp_t kflags;
++	rtt_report_t *rtt_report = NULL;
++	rtt_result_t *rtt_result = NULL;
++	struct list_head *rtt_list;
++	wiphy = wdev->wiphy;
++
++	WL_DBG(("In\n"));
++	/* Push the data to the skb */
++	if (!rtt_data) {
++		WL_ERR(("rtt_data is NULL\n"));
++		goto exit;
++	}
++	rtt_list = (struct list_head *)rtt_data;
++	kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
++	/* Alloc the SKB for vendor_event */
++	skb =
++	    ssv_cfg80211_vendor_event_alloc(wiphy, tot_len,
++					    GOOGLE_RTT_COMPLETE_EVENT, kflags);
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		goto exit;
++	}
++	/* fill in the rtt results on each entry */
++	list_for_each_entry(rtt_result, rtt_list, list) {
++		entry_len = 0;
++		if (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) {
++			entry_len = sizeof(rtt_report_t);
++			rtt_report = kzalloc(entry_len, kflags);
++			if (!rtt_report) {
++				WL_ERR(("rtt_report alloc failed"));
++				goto exit;
++			}
++			rtt_report->addr = rtt_result->peer_mac;
++			rtt_report->num_measurement = 1;	/* ONE SHOT */
++			rtt_report->status = rtt_result->err_code;
++			rtt_report->type =
++			    (rtt_result->TOF_type ==
++			     TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY;
++			rtt_report->peer = rtt_result->target_info->peer;
++			rtt_report->channel = rtt_result->target_info->channel;
++			rtt_report->rssi = rtt_result->avg_rssi;
++			/* tx_rate */
++			rtt_report->tx_rate = rtt_result->tx_rate;
++			/* RTT */
++			rtt_report->rtt = rtt_result->meanrtt;
++			rtt_report->rtt_sd = rtt_result->sdrtt;
++			/* convert to centi meter */
++			if (rtt_result->distance != 0xffffffff)
++				rtt_report->distance =
++				    (rtt_result->distance >> 2) * 25;
++			else	/* invalid distance */
++				rtt_report->distance = -1;
++
++			rtt_report->ts = rtt_result->ts;
++			nla_append(skb, entry_len, rtt_report);
++			kfree(rtt_report);
++		}
++	}
++	ssv_cfg80211_vendor_event(skb, kflags);
++ exit:
++	return;
++}
++
++static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy,
++				       struct wireless_dev *wdev,
++				       const void *data, int len)
++{
++	int err = 0, rem, rem1, rem2, type;
++	rtt_config_params_t rtt_param;
++	rtt_target_info_t *rtt_target = NULL;
++	const struct nlattr *iter, *iter1, *iter2;
++	int8 eabuf[ETHER_ADDR_STR_LEN];
++	int8 chanbuf[CHANSPEC_STR_LEN];
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	WL_DBG(("In\n"));
++	err =
++	    dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev,
++					       wl_cfgvendor_rtt_evt);
++	if (err < 0) {
++		WL_ERR(("failed to register rtt_noti_callback\n"));
++		goto exit;
++	}
++	memset(&rtt_param, 0, sizeof(rtt_param));
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			rtt_param.rtt_target_cnt = nla_get_u8(iter);
++			if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {
++				WL_ERR(("exceed max target count : %d\n",
++					rtt_param.rtt_target_cnt));
++				err = BCME_RANGE;
++			}
++			break;
++		case RTT_ATTRIBUTE_TARGET_INFO:
++			rtt_target = rtt_param.target_info;
++			nla_for_each_nested(iter1, iter, rem1) {
++				nla_for_each_nested(iter2, iter1, rem2) {
++					type = nla_type(iter2);
++					switch (type) {
++					case RTT_ATTRIBUTE_TARGET_MAC:
++						memcpy(&rtt_target->addr,
++						       nla_data(iter2),
++						       ETHER_ADDR_LEN);
++						break;
++					case RTT_ATTRIBUTE_TARGET_TYPE:
++						rtt_target->type =
++						    nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_PEER:
++						rtt_target->peer =
++						    nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_CHAN:
++						memcpy(&rtt_target->channel,
++						       nla_data(iter2),
++						       sizeof(rtt_target->
++							      channel));
++						break;
++					case RTT_ATTRIBUTE_TARGET_MODE:
++						rtt_target->continuous =
++						    nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_INTERVAL:
++						rtt_target->interval =
++						    nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT:
++						rtt_target->measure_cnt =
++						    nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_PKT:
++						rtt_target->ftm_cnt =
++						    nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_RETRY:
++						rtt_target->retry_cnt =
++						    nla_get_u32(iter2);
++					}
++				}
++				/* convert to chanspec value */
++				rtt_target->chanspec =
++				    dhd_rtt_convert_to_chspec(rtt_target->
++							      channel);
++				if (rtt_target->chanspec == 0) {
++					WL_ERR(("Channel is not valid \n"));
++					goto exit;
++				}
++				WL_INFORM(("Target addr %s, Channel : %s for RTT \n", bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf), wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
++				rtt_target++;
++			}
++			break;
++		}
++	}
++	WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
++	if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
++		WL_ERR(("Could not set RTT configuration\n"));
++		err = -EINVAL;
++	}
++ exit:
++	return err;
++}
++
++static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy,
++					  struct wireless_dev *wdev,
++					  const void *data, int len)
++{
++	int err = 0, rem, type, target_cnt = 0;
++	const struct nlattr *iter;
++	struct ether_addr *mac_list = NULL, *mac_addr = NULL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			target_cnt = nla_get_u8(iter);
++			mac_list =
++			    (struct ether_addr *)kzalloc(target_cnt *
++							 ETHER_ADDR_LEN,
++							 GFP_KERNEL);
++			if (mac_list == NULL) {
++				WL_ERR(("failed to allocate mem for mac list\n"));
++				goto exit;
++			}
++			mac_addr = &mac_list[0];
++			break;
++		case RTT_ATTRIBUTE_TARGET_MAC:
++			if (mac_addr)
++				memcpy(mac_addr++, nla_data(iter),
++				       ETHER_ADDR_LEN);
++			else {
++				WL_ERR(("mac_list is NULL\n"));
++				goto exit;
++			}
++			break;
++		}
++		if (dhd_dev_rtt_cancel_cfg
++		    (bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
++			WL_ERR(("Could not cancel RTT configuration\n"));
++			err = -EINVAL;
++			goto exit;
++		}
++	}
++ exit:
++	if (mac_list)
++		kfree(mac_list);
++	return err;
++}
++
++static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy,
++					   struct wireless_dev *wdev,
++					   const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	rtt_capabilities_t capability;
++
++	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		goto exit;
++	}
++	err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++					   &capability, sizeof(capability));
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++	}
++ exit:
++	return err;
++}
++
++#endif				/* RTT_SUPPORT */
++static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy,
++					    struct wireless_dev *wdev,
++					    const void *data, int len)
++{
++	int err = 0;
++	u8 resp[1] = { '\0' };
++
++	dev_dbg(&wiphy->dev, "%s\n", (char *)data);
++	err = ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), resp, 1);
++	if (unlikely(err))
++		dev_err(&wiphy->dev, "vendor Command reply failed, ret=:%d\n", err);
++
++	return err;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
++static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
++	{
++	 {
++	  .vendor_id = OUI_SSV,
++	  .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_priv_string_handler,
++	 .policy = VENDOR_CMD_RAW_DATA},
++#if defined(GSCAN_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_capabilities,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_scan_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_batch_scan_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_initiate_gscan,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_enable_full_scan_result,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_hotlist_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_significant_change_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_batch_results,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_channel_list,
++	 .policy = VENDOR_CMD_RAW_DATA},
++#endif				/* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_set_config,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_cancel_config,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_GETCAPABILITY},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_get_capability,
++	 .policy = VENDOR_CMD_RAW_DATA},
++#endif				/* RTT_SUPPORT */
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set_matrix,
++	 .policy = VENDOR_CMD_RAW_DATA}
++};
++#else
++static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
++	{
++	 {
++	  .vendor_id = OUI_SSV,
++	  .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_priv_string_handler
++	},
++#if defined(GSCAN_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_capabilities
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_scan_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_batch_scan_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_initiate_gscan
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_enable_full_scan_result
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_hotlist_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_significant_change_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_batch_results
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_channel_list
++	},
++#endif				/* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_set_config
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_cancel_config
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_GETCAPABILITY},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_get_capability
++	},
++#endif				/* RTT_SUPPORT */
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set_matrix
++	}
++};
++#endif
++
++static const struct nl80211_vendor_cmd_info ssv_vendor_events[] = {
++	{OUI_SSV, RTK_VENDOR_EVENT_UNSPEC},
++	{OUI_SSV, RTK_VENDOR_EVENT_PRIV_STR},
++#if defined(GSCAN_SUPPORT) && 0
++	{OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT},
++	{OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT},
++	{OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT},
++	{OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT},
++#endif				/* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT},
++#endif				/* RTT_SUPPORT */
++#if defined(GSCAN_SUPPORT) && 0
++	{OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT},
++	{OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT}
++#endif				/* GSCAN_SUPPORT */
++};
++
++int ssv_cfgvendor_attach(struct wiphy *wiphy)
++{
++
++	dev_info(&wiphy->dev, "register SSV cfg80211 vendor cmd(0x%x) interface\n",
++		NL80211_CMD_VENDOR);
++
++	wiphy->vendor_commands = ssv_vendor_cmds;
++	wiphy->n_vendor_commands = ARRAY_SIZE(ssv_vendor_cmds);
++	wiphy->vendor_events = ssv_vendor_events;
++	wiphy->n_vendor_events = ARRAY_SIZE(ssv_vendor_events);
++
++	return 0;
++}
++
++int ssv_cfgvendor_detach(struct wiphy *wiphy)
++{
++	dev_info(&wiphy->dev, "unregister SSV cfg80211 vendor interface\n");
++
++	wiphy->vendor_commands = NULL;
++	wiphy->vendor_events = NULL;
++	wiphy->n_vendor_commands = 0;
++	wiphy->n_vendor_events = 0;
++
++	return 0;
++}
++#endif				/* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT) */
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
+new file mode 100644
+index 000000000000..6d8696fcd220
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
+@@ -0,0 +1,247 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved.
++ *                                        
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#ifndef _RTW_CFGVENDOR_H_
++#define _RTW_CFGVENDOR_H_
++
++#define OUI_SSV		0x00E04C
++#define OUI_GOOGLE	0x001A11
++#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)
++#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN
++#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN
++#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)
++
++#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN
++#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)
++#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN
++#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN
++#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN
++#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)
++#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
++									SCAN_FLAGS_HDR_LEN + \
++							        GSCAN_NUM_RESULTS_HDR_LEN + \
++									GSCAN_RESULTS_HDR_LEN)
++
++#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \
++									VENDOR_SUBCMD_OVERHEAD + \
++									VENDOR_DATA_OVERHEAD)
++typedef enum {
++	/* don't use 0 as a valid subcommand */
++	VENDOR_NL80211_SUBCMD_UNSPECIFIED,
++
++	/* define all vendor startup commands between 0x0 and 0x0FFF */
++	VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
++	VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF,
++
++	/* define all GScan related commands between 0x1000 and 0x10FF */
++	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
++	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF,
++
++	/* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */
++	ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,
++	ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF,
++
++	/* define all RTT related commands between 0x1100 and 0x11FF */
++	ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
++	ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF,
++
++	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
++	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF,
++
++	ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300,
++	ANDROID_NL80211_SUBCMD_TDLS_RANGE_END = 0x13FF,
++	/* This is reserved for future usage */
++
++} ANDROID_VENDOR_SUB_COMMAND;
++
++enum wl_vendor_subcmd {
++	RTK_VENDOR_SCMD_UNSPEC,
++	RTK_VENDOR_SCMD_PRIV_STR,
++	GSCAN_SUBCMD_GET_CAPABILITIES =
++	    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
++	GSCAN_SUBCMD_SET_CONFIG,
++	GSCAN_SUBCMD_SET_SCAN_CONFIG,
++	GSCAN_SUBCMD_ENABLE_GSCAN,
++	GSCAN_SUBCMD_GET_SCAN_RESULTS,
++	GSCAN_SUBCMD_SCAN_RESULTS,
++	GSCAN_SUBCMD_SET_HOTLIST,
++	GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,
++	GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,
++	GSCAN_SUBCMD_GET_CHANNEL_LIST,
++	ANDR_WIFI_SUBCMD_GET_FEATURE_SET,
++	ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,
++	RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
++	RTT_SUBCMD_CANCEL_CONFIG,
++	RTT_SUBCMD_GETCAPABILITY,
++	/* Add more sub commands here */
++	VENDOR_SUBCMD_MAX
++};
++
++enum gscan_attributes {
++	GSCAN_ATTRIBUTE_NUM_BUCKETS = 10,
++	GSCAN_ATTRIBUTE_BASE_PERIOD,
++	GSCAN_ATTRIBUTE_BUCKETS_BAND,
++	GSCAN_ATTRIBUTE_BUCKET_ID,
++	GSCAN_ATTRIBUTE_BUCKET_PERIOD,
++	GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
++	GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
++	GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
++	GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
++	GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
++	GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
++
++	GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,
++	GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
++	GSCAN_ATTRIBUTE_FLUSH_FEATURE,
++	GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
++	GSCAN_ATTRIBUTE_REPORT_EVENTS,
++	/* remaining reserved for additional attributes */
++	GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,
++	GSCAN_ATTRIBUTE_FLUSH_RESULTS,
++	GSCAN_ATTRIBUTE_SCAN_RESULTS,	/* flat array of wifi_scan_result */
++	GSCAN_ATTRIBUTE_SCAN_ID,	/* indicates scan number */
++	GSCAN_ATTRIBUTE_SCAN_FLAGS,	/* indicates if scan was aborted */
++	GSCAN_ATTRIBUTE_AP_FLAGS,	/* flags on significant change event */
++	GSCAN_ATTRIBUTE_NUM_CHANNELS,
++	GSCAN_ATTRIBUTE_CHANNEL_LIST,
++
++	/* remaining reserved for additional attributes */
++
++	GSCAN_ATTRIBUTE_SSID = 40,
++	GSCAN_ATTRIBUTE_BSSID,
++	GSCAN_ATTRIBUTE_CHANNEL,
++	GSCAN_ATTRIBUTE_RSSI,
++	GSCAN_ATTRIBUTE_TIMESTAMP,
++	GSCAN_ATTRIBUTE_RTT,
++	GSCAN_ATTRIBUTE_RTTSD,
++
++	/* remaining reserved for additional attributes */
++
++	GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50,
++	GSCAN_ATTRIBUTE_RSSI_LOW,
++	GSCAN_ATTRIBUTE_RSSI_HIGH,
++	GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
++	GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
++
++	/* remaining reserved for additional attributes */
++	GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60,
++	GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
++	GSCAN_ATTRIBUTE_MIN_BREACHING,
++	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
++	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
++	GSCAN_ATTRIBUTE_MAX
++};
++
++enum gscan_bucket_attributes {
++	GSCAN_ATTRIBUTE_CH_BUCKET_1,
++	GSCAN_ATTRIBUTE_CH_BUCKET_2,
++	GSCAN_ATTRIBUTE_CH_BUCKET_3,
++	GSCAN_ATTRIBUTE_CH_BUCKET_4,
++	GSCAN_ATTRIBUTE_CH_BUCKET_5,
++	GSCAN_ATTRIBUTE_CH_BUCKET_6,
++	GSCAN_ATTRIBUTE_CH_BUCKET_7
++};
++
++enum gscan_ch_attributes {
++	GSCAN_ATTRIBUTE_CH_ID_1,
++	GSCAN_ATTRIBUTE_CH_ID_2,
++	GSCAN_ATTRIBUTE_CH_ID_3,
++	GSCAN_ATTRIBUTE_CH_ID_4,
++	GSCAN_ATTRIBUTE_CH_ID_5,
++	GSCAN_ATTRIBUTE_CH_ID_6,
++	GSCAN_ATTRIBUTE_CH_ID_7
++};
++
++enum rtt_attributes {
++	RTT_ATTRIBUTE_TARGET_CNT,
++	RTT_ATTRIBUTE_TARGET_INFO,
++	RTT_ATTRIBUTE_TARGET_MAC,
++	RTT_ATTRIBUTE_TARGET_TYPE,
++	RTT_ATTRIBUTE_TARGET_PEER,
++	RTT_ATTRIBUTE_TARGET_CHAN,
++	RTT_ATTRIBUTE_TARGET_MODE,
++	RTT_ATTRIBUTE_TARGET_INTERVAL,
++	RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT,
++	RTT_ATTRIBUTE_TARGET_NUM_PKT,
++	RTT_ATTRIBUTE_TARGET_NUM_RETRY
++};
++
++typedef enum wl_vendor_event {
++	RTK_VENDOR_EVENT_UNSPEC,
++	RTK_VENDOR_EVENT_PRIV_STR,
++	GOOGLE_GSCAN_SIGNIFICANT_EVENT,
++	GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT,
++	GOOGLE_GSCAN_BATCH_SCAN_EVENT,
++	GOOGLE_SCAN_FULL_RESULTS_EVENT,
++	GOOGLE_RTT_COMPLETE_EVENT,
++	GOOGLE_SCAN_COMPLETE_EVENT,
++	GOOGLE_GSCAN_GEOFENCE_LOST_EVENT
++} wl_vendor_event_t;
++
++enum andr_wifi_feature_set_attr {
++	ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
++	ANDR_WIFI_ATTRIBUTE_FEATURE_SET
++};
++
++typedef enum wl_vendor_gscan_attribute {
++	ATTR_START_GSCAN,
++	ATTR_STOP_GSCAN,
++	ATTR_SET_SCAN_BATCH_CFG_ID,	/* set batch scan params */
++	ATTR_SET_SCAN_GEOFENCE_CFG_ID,	/* set list of bssids to track */
++	ATTR_SET_SCAN_SIGNIFICANT_CFG_ID,	/* set list of bssids, rssi threshold etc.. */
++	ATTR_SET_SCAN_CFG_ID,	/* set common scan config params here */
++	ATTR_GET_GSCAN_CAPABILITIES_ID,
++	/* Add more sub commands here */
++	ATTR_GSCAN_MAX
++} wl_vendor_gscan_attribute_t;
++
++typedef enum gscan_batch_attribute {
++	ATTR_GSCAN_BATCH_BESTN,
++	ATTR_GSCAN_BATCH_MSCAN,
++	ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
++} gscan_batch_attribute_t;
++
++typedef enum gscan_geofence_attribute {
++	ATTR_GSCAN_NUM_HOTLIST_BSSID,
++	ATTR_GSCAN_HOTLIST_BSSID
++} gscan_geofence_attribute_t;
++
++typedef enum gscan_complete_event {
++	WIFI_SCAN_BUFFER_FULL,
++	WIFI_SCAN_COMPLETE
++} gscan_complete_event_t;
++
++/* Capture the RTK_VENDOR_SUBCMD_PRIV_STRINGS* here */
++#define RTK_VENDOR_SCMD_CAPA	"cap"
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT)
++extern int ssv_cfgvendor_attach(struct wiphy *wiphy);
++extern int ssv_cfgvendor_detach(struct wiphy *wiphy);
++extern int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
++					  struct net_device *dev, int event_id,
++					  const void *data, int len);
++#if defined(GSCAN_SUPPORT) && 0
++extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++					   struct net_device *dev, void *data,
++					   int len, wl_vendor_event_t event);
++#endif
++#endif				/* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
++
++#endif				/* _RTW_CFGVENDOR_H_ */
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
+new file mode 100644
+index 000000000000..fae819c43400
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
+@@ -0,0 +1,546 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ssv_ht_rc.h"
++#include "ssv_rc.h"
++#define SAMPLE_COUNT 4
++#define HT_CW_MIN 15
++#define HT_SEGMENT_SIZE 6000
++#define AVG_PKT_SIZE 12000
++#define SAMPLE_COLUMNS 10
++#define EWMA_LEVEL 75
++#define MCS_NBITS (AVG_PKT_SIZE << 3)
++#define MCS_NSYMS(bps) ((MCS_NBITS + (bps) - 1) / (bps))
++#define MCS_SYMBOL_TIME(sgi,syms) \
++    (sgi ? \
++      ((syms) * 18 + 4) / 5 : \
++      (syms) << 2 \
++    )
++#define MCS_DURATION(streams,sgi,bps) MCS_SYMBOL_TIME(sgi, MCS_NSYMS((streams) * (bps)))
++#define MCS_GROUP(_streams,_sgi,_ht40) { \
++    .duration = { \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 54 : 26), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 108 : 52), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 162 : 78), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 216 : 104), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 324 : 156), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 432 : 208), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 486 : 234), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 540 : 260) \
++    } \
++}
++const struct mcs_group minstrel_mcs_groups_ssv[] = {
++	MCS_GROUP(1, 0, 0),
++	MCS_GROUP(1, 1, 0),
++};
++
++const u16 ampdu_max_transmit_length[RATE_TABLE_SIZE] = {
++	0, 0, 0, 0, 0, 0, 0,
++	0, 0, 0, 0, 0, 0, 0, 0,
++	4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200,
++	5100, 10200, 15400, 20500, 30800, 41100, 46200, 51300,
++	4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200
++};
++
++static u8 sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES];
++static int minstrel_ewma(int old, int new, int weight)
++{
++	return (new * (100 - weight) + old * weight) / 100;
++}
++
++static inline struct minstrel_rate_stats *minstrel_get_ratestats(struct
++								 ssv62xx_ht *mi,
++								 int index)
++{
++	return &mi->groups.rates[index % MCS_GROUP_RATES];
++}
++
++static void minstrel_calc_rate_ewma(struct minstrel_rate_stats *mr)
++{
++	if (unlikely(mr->attempts > 0)) {
++		mr->sample_skipped = 0;
++		mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts);
++		if (!mr->att_hist)
++			mr->probability = mr->cur_prob;
++		else
++			mr->probability = minstrel_ewma(mr->probability,
++							mr->cur_prob,
++							EWMA_LEVEL);
++		mr->att_hist += mr->attempts;
++		mr->succ_hist += mr->success;
++	} else {
++		mr->sample_skipped++;
++	}
++	mr->last_success = mr->success;
++	mr->last_attempts = mr->attempts;
++	mr->success = 0;
++	mr->attempts = 0;
++}
++
++static void minstrel_ht_calc_tp(struct ssv62xx_ht *mi,
++				struct ssv_sta_rc_info *rc_sta, int rate)
++{
++	struct minstrel_rate_stats *mr;
++	unsigned int usecs, group_id;
++	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
++		group_id = 0;
++	else
++		group_id = 1;
++	mr = &mi->groups.rates[rate];
++	if (mr->probability < MINSTREL_FRAC(1, 10)) {
++		mr->cur_tp = 0;
++		return;
++	}
++	usecs = mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
++	usecs += minstrel_mcs_groups_ssv[group_id].duration[rate];
++	mr->cur_tp = MINSTREL_TRUNC((1000000 / usecs) * mr->probability);
++}
++
++static void rate_control_ht_sample(struct ssv62xx_ht *mi,
++				   struct ssv_sta_rc_info *rc_sta)
++{
++	struct minstrel_mcs_group_data *mg;
++	struct minstrel_rate_stats *mr;
++	int cur_prob, cur_prob_tp, cur_tp, cur_tp2;
++	int i, index;
++	if (mi->ampdu_packets > 0) {
++		mi->avg_ampdu_len = minstrel_ewma(mi->avg_ampdu_len,
++						  MINSTREL_FRAC(mi->ampdu_len,
++								mi->
++								ampdu_packets),
++						  EWMA_LEVEL);
++		mi->ampdu_len = 0;
++		mi->ampdu_packets = 0;
++	} else
++		return;
++	mi->sample_slow = 0;
++	mi->sample_count = 0;
++	{
++		cur_prob = 0;
++		cur_prob_tp = 0;
++		cur_tp = 0;
++		cur_tp2 = 0;
++		mg = &mi->groups;
++		mg->max_tp_rate = 0;
++		mg->max_tp_rate2 = 0;
++		mg->max_prob_rate = 0;
++		for (i = 0; i < MCS_GROUP_RATES; i++) {
++			if (!(rc_sta->ht_supp_rates & BIT(i)))
++				continue;
++			mr = &mg->rates[i];
++			index = i;
++			minstrel_calc_rate_ewma(mr);
++			minstrel_ht_calc_tp(mi, rc_sta, i);
++#ifdef RATE_CONTROL_HT_PARAMETER_DEBUG
++			if (mr->cur_prob)
++				pr_debug
++				    ("rate[%d]probability[%08d]cur_prob[%08d]TP[%04d]\n",
++				     i, mr->probability, mr->cur_prob,
++				     mr->cur_tp);
++#endif
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			pr_debug
++			    ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
++			     mg->max_tp_rate, mg->max_tp_rate2,
++			     mg->max_prob_rate);
++			pr_debug("rate[%d]probability[%08d]TP[%d]\n", i,
++			       mr->probability, mr->cur_tp);
++#endif
++			if (!mr->cur_tp)
++				continue;
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			pr_debug("HT--1 mr->cur_tp[%d]cur_prob_tp[%d]\n",
++			       mr->cur_tp, cur_prob_tp);
++#endif
++			if ((mr->cur_tp > cur_prob_tp && mr->probability >
++			     MINSTREL_FRAC(3, 4))
++			    || mr->probability > cur_prob) {
++				mg->max_prob_rate = index;
++				cur_prob = mr->probability;
++				cur_prob_tp = mr->cur_tp;
++			}
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			pr_debug("HT--2 mr->cur_tp[%d]cur_tp[%d]\n", mr->cur_tp,
++			       cur_tp);
++#endif
++			if (mr->cur_tp > cur_tp) {
++				swap(index, mg->max_tp_rate);
++				cur_tp = mr->cur_tp;
++				mr = minstrel_get_ratestats(mi, index);
++			}
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			if (index != i)
++				pr_debug
++				    ("HT--3 index[%d]i[%d]mg->max_tp_rate[%d]\n",
++				     index, i, mg->max_tp_rate);
++#endif
++			if (index >= mg->max_tp_rate)
++				continue;
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			if (index != i)
++				pr_debug("HT--4 mr->cur_tp[%d]cur_tp2[%d]\n",
++				       mr->cur_tp, cur_tp2);
++#endif
++			if (mr->cur_tp > cur_tp2) {
++				mg->max_tp_rate2 = index;
++				cur_tp2 = mr->cur_tp;
++			}
++		}
++	}
++	mi->sample_count = SAMPLE_COUNT;
++	mi->max_tp_rate = mg->max_tp_rate;
++	mi->max_tp_rate2 = mg->max_tp_rate2;
++	mi->max_prob_rate = mg->max_prob_rate;
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++	pr_debug
++	    ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
++	     mi->max_tp_rate, mi->max_tp_rate2, mi->max_prob_rate);
++#endif
++	mi->stats_update = jiffies;
++}
++
++static void minstrel_ht_set_rate(struct ssv62xx_ht *mi,
++				 struct fw_rc_retry_params *rate, int index,
++				 bool sample, bool rtscts,
++				 struct ssv_sta_rc_info *rc_sta,
++				 struct ssv_rate_ctrl *ssv_rc)
++{
++	struct minstrel_rate_stats *mr;
++	mr = minstrel_get_ratestats(mi, index);
++	rate->drate = ssv_rc->rc_table[mr->rc_index].hw_rate_idx;
++	rate->crate = ssv_rc->rc_table[mr->rc_index].ctrl_rate_idx;
++}
++
++static inline int minstrel_get_duration(int index,
++					struct ssv_sta_rc_info *rc_sta)
++{
++	unsigned int group_id;
++	const struct mcs_group *group;
++	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
++		group_id = 0;
++	else
++		group_id = 1;
++	group = &minstrel_mcs_groups_ssv[group_id];
++	return group->duration[index % MCS_GROUP_RATES];
++}
++
++static void minstrel_next_sample_idx(struct ssv62xx_ht *mi)
++{
++	struct minstrel_mcs_group_data *mg;
++	for (;;) {
++		mg = &mi->groups;
++		if (++mg->index >= MCS_GROUP_RATES) {
++			mg->index = 0;
++			if (++mg->column >= ARRAY_SIZE(sample_table))
++				mg->column = 0;
++		}
++		break;
++	}
++}
++
++static int minstrel_get_sample_rate(struct ssv62xx_ht *mi,
++				    struct ssv_sta_rc_info *rc_sta)
++{
++	struct minstrel_rate_stats *mr;
++	struct minstrel_mcs_group_data *mg;
++	int sample_idx = 0;
++	if (mi->sample_wait > 0) {
++		mi->sample_wait--;
++		return -1;
++	}
++	if (!mi->sample_tries)
++		return -1;
++	mi->sample_tries--;
++	mg = &mi->groups;
++	sample_idx = sample_table[mg->column][mg->index];
++	mr = &mg->rates[sample_idx];
++	minstrel_next_sample_idx(mi);
++	if (minstrel_get_duration(sample_idx, rc_sta) >
++	    minstrel_get_duration(mi->max_tp_rate, rc_sta)) {
++		if (mr->sample_skipped < 20) {
++			return -1;
++		}
++		if (mi->sample_slow++ > 2) {
++			return -1;
++		}
++	}
++	return sample_idx;
++}
++
++static void _fill_txinfo_rates(struct ssv_rate_ctrl *ssv_rc,
++			       struct sk_buff *skb,
++			       struct fw_rc_retry_params *ar)
++{
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	info->control.rates[0].idx =
++	    ssv_rc->rc_table[ar[0].drate].dot11_rate_idx;
++	info->control.rates[0].count = 1;
++	info->control.rates[SSV_DRATE_IDX].count = ar[0].drate;
++	info->control.rates[SSV_CRATE_IDX].count = ar[0].crate;
++}
++
++extern const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13];
++s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
++			   struct fw_rc_retry_params *ar)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++	struct ieee80211_sta *sta = skb_info->sta;
++	struct ssv62xx_ht *mi = NULL;
++	int sample_idx;
++	bool sample = false;
++	struct ssv_sta_rc_info *rc_sta;
++	struct ssv_sta_priv_data *sta_priv;
++	struct rc_pid_sta_info *spinfo;
++	int ret = 0;
++	if (sc->sc_flags & SC_OP_FIXED_RATE) {
++		ar[0].count = 3;
++		ar[0].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++		ar[0].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
++		ar[1].count = 2;
++		ar[1].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++		ar[1].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
++		ar[2].count = 2;
++		ar[2].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++		ar[2].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
++		_fill_txinfo_rates(ssv_rc, skb, ar);
++		return ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++	}
++	if (sta == NULL) {
++		dev_err(sc->dev, "Station NULL\n");
++		BUG_ON(1);
++	}
++	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
++	spinfo = &rc_sta->spinfo;
++	if ((rc_sta->rc_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT)
++	    || (rc_sta->rc_wsid < 0)) {
++		struct ssv_sta_priv_data *ssv_sta_priv;
++		int rateidx = 99;
++		ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		{
++			if ((rc_sta->ht_rc_type >= RC_TYPE_HT_SGI_20) &&
++			    (ssv_sta_priv->rx_data_rate <
++			     SSV62XX_RATE_MCS_INDEX)) {
++				if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0]
++				    == 12)
++					rateidx =
++					    (int)rc_sta->pinfo.rinfo[4].
++					    rc_index;
++				else
++					rateidx =
++					    (int)rc_sta->pinfo.rinfo[0].
++					    rc_index;
++			} else {
++				rateidx = (int)ssv_sta_priv->rx_data_rate;
++				rateidx -= SSV62XX_RATE_MCS_INDEX;
++				rateidx %= 8;
++				if (rc_sta->ht_rc_type == RC_TYPE_HT_SGI_20)
++					rateidx += SSV62XX_RATE_MCS_SGI_INDEX;
++				else if (rc_sta->ht_rc_type ==
++					 RC_TYPE_HT_LGI_20)
++					rateidx += SSV62XX_RATE_MCS_LGI_INDEX;
++				else
++					rateidx +=
++					    SSV62XX_RATE_MCS_GREENFIELD_INDEX;
++			}
++		}
++		ar[0].count = 3;
++		ar[2].drate = ar[1].drate = ar[0].drate =
++		    ssv_rc->rc_table[rateidx].hw_rate_idx;
++		ar[2].crate = ar[1].crate = ar[0].crate =
++		    ssv_rc->rc_table[rateidx].ctrl_rate_idx;
++		ar[1].count = 2;
++		ar[2].count = 2;
++		_fill_txinfo_rates(ssv_rc, skb, ar);
++		return rateidx;
++	}
++	mi = &rc_sta->ht;
++	sample_idx = minstrel_get_sample_rate(mi, rc_sta);
++	if (sample_idx >= 0) {
++		sample = true;
++		minstrel_ht_set_rate(mi, &ar[0], sample_idx,
++				     true, false, rc_sta, ssv_rc);
++	} else {
++		minstrel_ht_set_rate(mi, &ar[0], mi->max_tp_rate,
++				     false, false, rc_sta, ssv_rc);
++	}
++	ar[0].count = mi->first_try_count;
++	ret = ar[0].drate;
++	{
++		if (sample_idx >= 0)
++			minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate,
++					     false, false, rc_sta, ssv_rc);
++		else
++			minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate2,
++					     false, true, rc_sta, ssv_rc);
++		ar[1].count = mi->second_try_count;
++		if (ret > ar[1].drate)
++			ret = ar[1].drate;
++		minstrel_ht_set_rate(mi, &ar[2], mi->max_prob_rate,
++				     false, !sample, rc_sta, ssv_rc);
++		ar[2].count = mi->other_try_count;
++		if (ret > ar[2].drate)
++			ret = ar[2].drate;
++	}
++	mi->total_packets++;
++	if (mi->total_packets == ~0) {
++		mi->total_packets = 0;
++		mi->sample_packets = 0;
++	}
++	if (spinfo->real_hw_index < SSV62XX_RATE_MCS_INDEX)
++		return spinfo->real_hw_index;
++	_fill_txinfo_rates(ssv_rc, skb, ar);
++	return ret;
++}
++
++static void init_sample_table(void)
++{
++	int col, i, new_idx;
++	u8 rnd[MCS_GROUP_RATES];
++	memset(sample_table, 0xff, sizeof(sample_table));
++	for (col = 0; col < SAMPLE_COLUMNS; col++) {
++		for (i = 0; i < MCS_GROUP_RATES; i++) {
++			get_random_bytes(rnd, sizeof(rnd));
++			new_idx = (i + rnd[i]) % MCS_GROUP_RATES;
++			while (sample_table[col][new_idx] != 0xff)
++				new_idx = (new_idx + 1) % MCS_GROUP_RATES;
++			sample_table[col][new_idx] = i;
++		}
++	}
++}
++
++void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
++			struct ssv_sta_rc_info *rc_sta)
++{
++	struct ssv62xx_ht *mi = &rc_sta->ht;
++	int ack_dur;
++	int i;
++	unsigned int group_id;
++	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
++		group_id = 0;
++	else
++		group_id = 1;
++	for (i = 0; i < MCS_GROUP_RATES; i++) {
++		pr_debug("[RC]HT duration[%d][%d]\n", i,
++		       minstrel_mcs_groups_ssv[group_id].duration[i]);
++	}
++	init_sample_table();
++	memset(mi, 0, sizeof(*mi));
++	mi->stats_update = jiffies;
++	ack_dur = pide_frame_duration(10, 60, 0, 0);
++	mi->overhead = pide_frame_duration(0, 60, 0, 0) + ack_dur;
++	mi->overhead_rtscts = mi->overhead + 2 * ack_dur;
++	mi->avg_ampdu_len = MINSTREL_FRAC(1, 1);
++	mi->sample_count = 16;
++	mi->sample_wait = 0;
++	mi->sample_tries = 4;
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++	mi->max_tp_rate = MCS_GROUP_RATES - 1;
++	mi->max_tp_rate2 = MCS_GROUP_RATES - 1;
++	mi->max_prob_rate = MCS_GROUP_RATES - 1;
++#endif
++#if (HW_MAX_RATE_TRIES == 7)
++	{
++		mi->first_try_count = 3;
++		mi->second_try_count = 2;
++		mi->other_try_count = 2;
++	}
++#else
++	{
++		mi->first_try_count = 2;
++		mi->second_try_count = 1;
++		mi->other_try_count = 1;
++	}
++#endif
++	for (i = 0; i < MCS_GROUP_RATES; i++) {
++		mi->groups.rates[i].rc_index =
++		    ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][i + 1];
++	}
++}
++
++static bool minstrel_ht_txstat_valid(struct ssv62xx_tx_rate *rate)
++{
++	if (!rate->count)
++		return false;
++	if (rate->data_rate < 0)
++		return false;
++	return true;
++}
++
++void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
++			       struct ssv_sta_rc_info *rc_sta)
++{
++	struct cfg_host_event *host_event;
++	struct firmware_rate_control_report_data *report_data;
++	struct ssv62xx_ht *mi;
++	struct minstrel_rate_stats *rate;
++	bool last = false;
++	int i = 0;
++	u16 report_ampdu_packets = 0;
++	unsigned long period;
++	host_event = (struct cfg_host_event *)skb->data;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
++	if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
++		report_ampdu_packets = 1;
++	} else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
++		report_data->ampdu_len = 1;
++		report_ampdu_packets = report_data->ampdu_len;
++	} else {
++		dev_warn(sc->dev, "rate control report handler got garbage\n");
++		return;
++	}
++	mi = &rc_sta->ht;
++	mi->ampdu_packets += report_ampdu_packets;
++	mi->ampdu_len += report_data->ampdu_len;
++	if (!mi->sample_wait && !mi->sample_tries && mi->sample_count > 0) {
++		mi->sample_wait = 16 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len);
++		mi->sample_tries = 2;
++		mi->sample_count--;
++	}
++	for (i = 0; !last; i++) {
++		last = (i == SSV62XX_TX_MAX_RATES - 1) ||
++		    !minstrel_ht_txstat_valid(&report_data->rates[i + 1]);
++		if (!minstrel_ht_txstat_valid(&report_data->rates[i]))
++			break;
++#ifdef RATE_CONTROL_DEBUG
++		if ((report_data->rates[i].data_rate < SSV62XX_RATE_MCS_INDEX)
++		    || (report_data->rates[i].data_rate >=
++			SSV62XX_RATE_MCS_GREENFIELD_INDEX)) {
++			dev_dbg
++			    (sc->dev, "[RC]ssv6xxx_ht_report_handler get error report rate[%d]\n",
++			     report_data->rates[i].data_rate);
++			break;
++		}
++#endif
++		rate =
++		    &mi->groups.
++		    rates[(report_data->rates[i].data_rate -
++			   SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES];
++		if (last)
++			rate->success += report_data->ampdu_ack_len;
++		rate->attempts +=
++		    report_data->rates[i].count * report_data->ampdu_len;
++	}
++	period = msecs_to_jiffies(SSV_RC_HT_INTERVAL / 2);
++	if (time_after(jiffies, mi->stats_update + period)) {
++		rate_control_ht_sample(mi, rc_sta);
++	}
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
+new file mode 100644
+index 000000000000..275c3356e036
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
+@@ -0,0 +1,31 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_RC_HT_H_
++#define _SSV_RC_HT_H_
++#include "ssv_rc_common.h"
++#define MINSTREL_SCALE 16
++#define MINSTREL_FRAC(val,div) (((val) << MINSTREL_SCALE) / div)
++#define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE)
++#define SSV_RC_HT_INTERVAL 100
++extern const u16 ampdu_max_transmit_length[];
++s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
++			   struct fw_rc_retry_params *ar);
++void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
++			struct ssv_sta_rc_info *rc_sta);
++void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
++			       struct ssv_sta_rc_info *rc_sta);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.c b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
+new file mode 100644
+index 000000000000..fc3be2013f61
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
+@@ -0,0 +1,19 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include "dev.h"
++#include "sar.h"
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.h b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
+new file mode 100644
+index 000000000000..9be260dd904e
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
+@@ -0,0 +1,20 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_PM_H_
++#define _SSV_PM_H_
++#include <linux/version.h>
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
+new file mode 100644
+index 000000000000..9c3574285364
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
+@@ -0,0 +1,1716 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ssv_ht_rc.h"
++#include "ssv_rc.h"
++#include "ssv_rc_common.h"
++static struct ssv_rc_rate ssv_11bgn_rate_table[] = {
++	[0] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 1000,
++	       .dot11_rate_idx = 0,
++	       .ctrl_rate_idx = 0,
++	       .hw_rate_idx = 0,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[1] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 2000,
++	       .dot11_rate_idx = 1,
++	       .ctrl_rate_idx = 1,
++	       .hw_rate_idx = 1,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[2] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 5500,
++	       .dot11_rate_idx = 2,
++	       .ctrl_rate_idx = 1,
++	       .hw_rate_idx = 2,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[3] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 11000,
++	       .dot11_rate_idx = 3,
++	       .ctrl_rate_idx = 1,
++	       .hw_rate_idx = 3,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[4] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 2000,
++	       .dot11_rate_idx = 1,
++	       .ctrl_rate_idx = 4,
++	       .hw_rate_idx = 4,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[5] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 5500,
++	       .dot11_rate_idx = 2,
++	       .ctrl_rate_idx = 4,
++	       .hw_rate_idx = 5,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[6] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 11000,
++	       .dot11_rate_idx = 3,
++	       .ctrl_rate_idx = 4,
++	       .hw_rate_idx = 6,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[7] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_OFDM,
++	       .rate_kbps = 6000,
++	       .dot11_rate_idx = 4,
++	       .ctrl_rate_idx = 7,
++	       .hw_rate_idx = 7,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[8] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_OFDM,
++	       .rate_kbps = 9000,
++	       .dot11_rate_idx = 5,
++	       .ctrl_rate_idx = 7,
++	       .hw_rate_idx = 8,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[9] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_OFDM,
++	       .rate_kbps = 12000,
++	       .dot11_rate_idx = 6,
++	       .ctrl_rate_idx = 9,
++	       .hw_rate_idx = 9,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[10] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 18000,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 10,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[11] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 24000,
++		.dot11_rate_idx = 8,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 11,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[12] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 36000,
++		.dot11_rate_idx = 9,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 12,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[13] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 48000,
++		.dot11_rate_idx = 10,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 13,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[14] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 54000,
++		.dot11_rate_idx = 11,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 14,
++		.arith_shift = 8,
++		.target_pf = 8},
++	[15] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 6500,
++		.dot11_rate_idx = 0,
++		.ctrl_rate_idx = 7,
++		.hw_rate_idx = 15,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[16] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 13000,
++		.dot11_rate_idx = 1,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 16,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[17] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 19500,
++		.dot11_rate_idx = 2,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 17,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[18] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 26000,
++		.dot11_rate_idx = 3,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 18,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[19] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 39000,
++		.dot11_rate_idx = 4,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 19,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[20] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 52000,
++		.dot11_rate_idx = 5,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 20,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[21] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 58500,
++		.dot11_rate_idx = 6,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 21,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[22] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 65000,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 22,
++		.arith_shift = 8,
++		.target_pf = 8},
++	[23] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 7200,
++		.dot11_rate_idx = 0,
++		.ctrl_rate_idx = 7,
++		.hw_rate_idx = 23,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[24] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 14400,
++		.dot11_rate_idx = 1,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 24,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[25] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 21700,
++		.dot11_rate_idx = 2,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 25,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[26] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 28900,
++		.dot11_rate_idx = 3,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 26,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[27] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 43300,
++		.dot11_rate_idx = 4,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 27,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[28] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 57800,
++		.dot11_rate_idx = 5,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 28,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[29] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 65000,
++		.dot11_rate_idx = 6,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 29,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[30] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 72200,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 30,
++		.arith_shift = 8,
++		.target_pf = 8},
++	[31] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 6500,
++		.dot11_rate_idx = 0,
++		.ctrl_rate_idx = 7,
++		.hw_rate_idx = 31,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[32] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 13000,
++		.dot11_rate_idx = 1,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 32,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[33] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 19500,
++		.dot11_rate_idx = 2,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 33,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[34] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 26000,
++		.dot11_rate_idx = 3,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 34,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[35] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 39000,
++		.dot11_rate_idx = 4,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 35,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[36] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 52000,
++		.dot11_rate_idx = 5,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 36,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[37] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 58500,
++		.dot11_rate_idx = 6,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 37,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[38] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 65000,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 38,
++		.arith_shift = 8,
++		.target_pf = 8},
++};
++
++const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13] = {
++	[RC_TYPE_B_ONLY] = {4, 0, 1, 2, 3},
++	[RC_TYPE_LEGACY_GB] = {12, 0, 1, 2, 7, 8, 3, 9, 10, 11, 12, 13, 14},
++	[RC_TYPE_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
++	[RC_TYPE_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
++	[RC_TYPE_HT_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
++	[RC_TYPE_HT_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
++	[RC_TYPE_HT_GF] = {8, 31, 32, 33, 34, 35, 36, 37, 38},
++};
++
++static u32 ssv6xxx_rate_supported(struct ssv_sta_rc_info *rc_sta, u32 index)
++{
++	return (rc_sta->rc_supp_rates & BIT(index));
++}
++
++static u8 ssv6xxx_rate_lowest_index(struct ssv_sta_rc_info *rc_sta)
++{
++	int i;
++	for (i = 0; i < rc_sta->rc_num_rate; i++)
++		if (ssv6xxx_rate_supported(rc_sta, i))
++			return i;
++	return 0;
++}
++
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++static u8 ssv6xxx_rate_highest_index(struct ssv_sta_rc_info *rc_sta)
++{
++	int i;
++	for (i = rc_sta->rc_num_rate - 1; i >= 0; i--)
++		if (ssv6xxx_rate_supported(rc_sta, i))
++			return i;
++	return 0;
++}
++#endif
++static void rate_control_pid_adjust_rate(struct ssv_sta_rc_info *rc_sta,
++					 struct rc_pid_sta_info *spinfo,
++					 int adj, struct rc_pid_rateinfo *rinfo)
++{
++	int cur_sorted, new_sorted, probe, tmp, n_bitrates;
++	int cur = spinfo->txrate_idx;
++	n_bitrates = rc_sta->rc_num_rate;
++	cur_sorted = rinfo[cur].index;
++	new_sorted = cur_sorted + adj;
++	if (new_sorted < 0)
++		new_sorted = rinfo[0].index;
++	else if (new_sorted >= n_bitrates)
++		new_sorted = rinfo[n_bitrates - 1].index;
++	tmp = new_sorted;
++	if (adj < 0) {
++		for (probe = cur_sorted; probe >= new_sorted; probe--)
++			if (rinfo[probe].diff <= rinfo[cur_sorted].diff &&
++			    ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
++				tmp = probe;
++	} else {
++		for (probe = new_sorted + 1; probe < n_bitrates; probe++)
++			if (rinfo[probe].diff <= rinfo[new_sorted].diff &&
++			    ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
++				tmp = probe;
++	}
++	BUG_ON(tmp < 0 || tmp >= n_bitrates);
++	do {
++		if (ssv6xxx_rate_supported(rc_sta, rinfo[tmp].index)) {
++			spinfo->tmp_rate_idx = rinfo[tmp].index;
++			break;
++		}
++		if (adj < 0)
++			tmp--;
++		else
++			tmp++;
++	} while (tmp < n_bitrates && tmp >= 0);
++	spinfo->oldrate = spinfo->txrate_idx;
++	if (spinfo->tmp_rate_idx != spinfo->txrate_idx) {
++		spinfo->monitoring = 1;
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++		pr_debug("Trigger monitor tmp_rate_idx=[%d]\n",
++		       spinfo->tmp_rate_idx);
++#endif
++		spinfo->probe_cnt = MAXPROBES;
++	}
++}
++
++static void rate_control_pid_normalize(struct rc_pid_info *pinfo, int l)
++{
++	int i, norm_offset = RC_PID_NORM_OFFSET;
++	struct rc_pid_rateinfo *r = pinfo->rinfo;
++	if (r[0].diff > norm_offset)
++		r[0].diff -= norm_offset;
++	else if (r[0].diff < -norm_offset)
++		r[0].diff += norm_offset;
++	for (i = 0; i < l - 1; i++)
++		if (r[i + 1].diff > r[i].diff + norm_offset)
++			r[i + 1].diff -= norm_offset;
++		else if (r[i + 1].diff <= r[i].diff)
++			r[i + 1].diff += norm_offset;
++}
++
++#ifdef RATE_CONTROL_DEBUG
++unsigned int txrate_dlr = 0;
++#endif
++static void rate_control_pid_sample(struct ssv_rate_ctrl *ssv_rc,
++				    struct rc_pid_info *pinfo,
++				    struct ssv_sta_rc_info *rc_sta,
++				    struct rc_pid_sta_info *spinfo)
++{
++	struct rc_pid_rateinfo *rinfo = pinfo->rinfo;
++	u8 pf;
++	s32 err_avg;
++	s32 err_prop;
++	s32 err_int;
++	s32 err_der;
++	int adj, i, j, tmp;
++	struct ssv_rc_rate *rc_table;
++	unsigned int dlr;
++	unsigned int perfect_time = 0;
++	unsigned int this_thp, ewma_thp;
++	struct rc_pid_rateinfo *rate;
++	if (!spinfo->monitoring) {
++		if (spinfo->tx_num_xmit == 0)
++			return;
++		spinfo->last_sample = jiffies;
++		pf = spinfo->tx_num_failed * 100 / spinfo->tx_num_xmit;
++		if (pinfo->rinfo[spinfo->txrate_idx].this_attempt > 0) {
++			rate = &pinfo->rinfo[spinfo->txrate_idx];
++			rc_table = &ssv_rc->rc_table[spinfo->txrate_idx];
++			dlr = 100 - rate->this_fail * 100 / rate->this_attempt;
++			perfect_time = rate->perfect_tx_time;
++			if (!perfect_time)
++				perfect_time = 1000000;
++			this_thp = dlr * (1000000 / perfect_time);
++			ewma_thp = rate->throughput;
++			if (ewma_thp == 0)
++				rate->throughput = this_thp;
++			else
++				rate->throughput = (ewma_thp + this_thp) >> 1;
++			rate->attempt += rate->this_attempt;
++			rate->success += rate->this_success;
++			rate->fail += rate->this_fail;
++			spinfo->tx_num_xmit = 0;
++			spinfo->tx_num_failed = 0;
++			rate->this_fail = 0;
++			rate->this_success = 0;
++			rate->this_attempt = 0;
++			if (pinfo->oldrate < 0
++			    || pinfo->oldrate >= rc_sta->rc_num_rate) {
++				WARN_ON(1);
++			}
++			if (spinfo->txrate_idx < 0
++			    || spinfo->txrate_idx >= rc_sta->rc_num_rate) {
++				WARN_ON(1);
++			}
++			if (pinfo->oldrate != spinfo->txrate_idx) {
++				i = rinfo[pinfo->oldrate].index;
++				j = rinfo[spinfo->txrate_idx].index;
++				tmp = (pf - spinfo->last_pf);
++				tmp =
++				    RC_PID_DO_ARITH_RIGHT_SHIFT(tmp,
++								rc_table->arith_shift);
++				rinfo[j].diff = rinfo[i].diff + tmp;
++				pinfo->oldrate = spinfo->txrate_idx;
++			}
++			rate_control_pid_normalize(pinfo, rc_sta->rc_num_rate);
++			err_prop =
++			    (rc_table->target_pf - pf) << rc_table->arith_shift;
++			err_avg = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
++			spinfo->err_avg_sc =
++			    spinfo->err_avg_sc - err_avg + err_prop;
++			err_int = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
++			err_der = pf - spinfo->last_pf;
++			spinfo->last_pf = pf;
++			spinfo->last_dlr = dlr;
++			spinfo->oldrate = spinfo->txrate_idx;
++			adj =
++			    (err_prop * RC_PID_COEFF_P +
++			     err_int * RC_PID_COEFF_I +
++			     err_der * RC_PID_COEFF_D);
++			adj =
++			    RC_PID_DO_ARITH_RIGHT_SHIFT(adj,
++							rc_table->arith_shift <<
++							1);
++			if (adj) {
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++				if ((spinfo->txrate_idx != 11)
++				    || ((spinfo->txrate_idx == 11)
++					&& (adj < 0)))
++					pr_debug
++					    ("[RC]Probe adjust[%d] dlr[%d%%] this_thp[%d] ewma_thp[%d] index[%d]\n",
++					     adj, dlr, this_thp, ewma_thp,
++					     spinfo->txrate_idx);
++#endif
++				rate_control_pid_adjust_rate(rc_sta, spinfo,
++							     adj, rinfo);
++			}
++		}
++	} else {
++		if ((spinfo->feedback_probes >= MAXPROBES)
++		    || (spinfo->feedback_probes && spinfo->probe_cnt)) {
++			rate = &pinfo->rinfo[spinfo->txrate_idx];
++			spinfo->last_sample = jiffies;
++			if (rate->this_attempt > 0) {
++				dlr =
++				    100 -
++				    rate->this_fail * 100 / rate->this_attempt;
++#ifdef RATE_CONTROL_DEBUG
++#ifdef PROBE
++				txrate_dlr = dlr;
++#endif
++#endif
++				spinfo->last_dlr = dlr;
++				perfect_time = rate->perfect_tx_time;
++				if (!perfect_time)
++					perfect_time = 1000000;
++				this_thp = dlr * (1000000 / perfect_time);
++				ewma_thp = rate->throughput;
++				if (ewma_thp == 0)
++					rate->throughput = this_thp;
++				else
++					rate->throughput =
++					    (ewma_thp + this_thp) >> 1;
++				rate->attempt += rate->this_attempt;
++				rate->success += rate->this_success;
++				rinfo[spinfo->txrate_idx].fail +=
++				    rate->this_fail;
++				rate->this_fail = 0;
++				rate->this_success = 0;
++				rate->this_attempt = 0;
++			} else {
++#ifdef RATE_CONTROL_DEBUG
++#ifdef PROBE
++				txrate_dlr = 0;
++#endif
++#endif
++			}
++			rate = &pinfo->rinfo[spinfo->tmp_rate_idx];
++			if (rate->this_attempt > 0) {
++				dlr =
++				    100 -
++				    ((rate->this_fail * 100) /
++				     rate->this_attempt);
++				{
++					perfect_time = rate->perfect_tx_time;
++					if (!perfect_time)
++						perfect_time = 1000000;
++					if (dlr)
++						this_thp =
++						    dlr * (1000000 /
++							   perfect_time);
++					else
++						this_thp = 0;
++					ewma_thp = rate->throughput;
++					if (ewma_thp == 0)
++						rate->throughput = this_thp;
++					else
++						rate->throughput =
++						    (ewma_thp + this_thp) >> 1;
++					if (rate->throughput >
++					    pinfo->rinfo[spinfo->
++							 txrate_idx].throughput)
++					{
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++						pr_debug
++						    ("[RC]UPDATE probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
++						     spinfo->tmp_rate_idx,
++						     rate->throughput, dlr,
++						     spinfo->txrate_idx,
++						     pinfo->
++						     rinfo
++						     [spinfo->txrate_idx].throughput,
++						     txrate_dlr,
++						     spinfo->feedback_probes);
++#endif
++						spinfo->txrate_idx =
++						    spinfo->tmp_rate_idx;
++					} else {
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++						pr_debug
++						    ("[RC]Fail probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
++						     spinfo->tmp_rate_idx,
++						     rate->throughput, dlr,
++						     spinfo->txrate_idx,
++						     pinfo->
++						     rinfo
++						     [spinfo->txrate_idx].throughput,
++						     txrate_dlr,
++						     spinfo->feedback_probes);
++#endif
++						;
++					}
++					rate->attempt += rate->this_attempt;
++					rate->success += rate->this_success;
++					rate->fail += rate->this_fail;
++					rate->this_fail = 0;
++					rate->this_success = 0;
++					rate->this_attempt = 0;
++					spinfo->oldrate = spinfo->txrate_idx;
++				}
++			}
++#ifdef RATE_CONTROL_DEBUG
++			else
++				pr_err("Unexpected error\n");
++#endif
++			spinfo->feedback_probes = 0;
++			spinfo->tx_num_xmit = 0;
++			spinfo->tx_num_failed = 0;
++			spinfo->monitoring = 0;
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++			pr_debug("Disable monitor\n");
++#endif
++			spinfo->probe_report_flag = 0;
++			spinfo->probe_wating_times = 0;
++		} else {
++			spinfo->probe_wating_times++;
++#ifdef RATE_CONTROL_DEBUG
++			if (spinfo->probe_wating_times > 3) {
++				pr_debug
++				    ("[RC]@@@@@ PROBE LOSE @@@@@ feedback=[%d] need=[%d] probe_cnt=[%d] wating times[%d]\n",
++				     spinfo->feedback_probes, MAXPROBES,
++				     spinfo->probe_cnt,
++				     spinfo->probe_wating_times);
++				spinfo->feedback_probes = 0;
++				spinfo->tx_num_xmit = 0;
++				spinfo->tx_num_failed = 0;
++				spinfo->monitoring = 0;
++				spinfo->probe_report_flag = 0;
++				spinfo->probe_wating_times = 0;
++			}
++#else
++			if (spinfo->probe_wating_times > 3) {
++				spinfo->feedback_probes = 0;
++				spinfo->tx_num_xmit = 0;
++				spinfo->tx_num_failed = 0;
++				spinfo->monitoring = 0;
++				spinfo->probe_report_flag = 0;
++				spinfo->probe_wating_times = 0;
++			}
++#endif
++		}
++	}
++}
++
++#ifdef RATE_CONTROL_PERCENTAGE_TRACE
++int percentage = 0;
++int percentageCounter = 0;
++#endif
++void ssv6xxx_legacy_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
++				   struct ssv_sta_rc_info *rc_sta)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct cfg_host_event *host_event;
++	struct firmware_rate_control_report_data *report_data;
++	struct rc_pid_info *pinfo;
++	struct rc_pid_sta_info *spinfo;
++	struct rc_pid_rateinfo *pidrate;
++	struct rc_pid_rateinfo *rate;
++	s32 report_data_index = 0;
++	unsigned long period;
++	host_event = (struct cfg_host_event *)skb->data;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
++	if ((report_data->wsid != (-1))
++	    && sc->sta_info[report_data->wsid].sta == NULL) {
++		dev_warn(sc->dev, "RC report has no valid STA.(%d)\n",
++			 report_data->wsid);
++		return;
++	}
++	pinfo = &rc_sta->pinfo;
++	spinfo = &rc_sta->spinfo;
++	pidrate = rc_sta->pinfo.rinfo;
++	if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
++		period = msecs_to_jiffies(HT_RC_UPDATE_INTERVAL);
++		if (time_after(jiffies, spinfo->last_sample + period)) {
++			if (rc_sta->rc_num_rate == 12)
++				spinfo->txrate_idx = rc_sta->ht.max_tp_rate + 4;
++			else
++				spinfo->txrate_idx = rc_sta->ht.max_tp_rate;
++#ifdef RATE_CONTROL_DEBUG
++			pr_debug("MPDU rate update time txrate_idx[%d]!!\n",
++			       spinfo->txrate_idx);
++#endif
++			spinfo->last_sample = jiffies;
++		}
++		return;
++	} else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
++		;
++	} else {
++		dev_warn(sc->dev, "RC report handler got garbage\n");
++		return;
++	}
++	if (report_data->rates[0].data_rate < 7) {
++		if (report_data->rates[0].data_rate > 3) {
++			report_data->rates[0].data_rate -= 3;
++		}
++	}
++	if (ssv_rc->
++	    rc_table[rc_sta->pinfo.rinfo[spinfo->txrate_idx].
++		     rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
++		report_data_index =
++		    rc_sta->pinfo.rinfo[spinfo->txrate_idx].index;
++	} else
++	    if (ssv_rc->rc_table
++		[rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].
++		 rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
++		report_data_index =
++		    rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].index;
++	}
++	if ((report_data_index != spinfo->tmp_rate_idx)
++	    && (report_data_index != spinfo->txrate_idx)) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg
++		    (sc->dev, "Rate control report mismatch report_rate_idx[%d] tmp_rate_idx[%d]rate[%d] txrate_idx[%d]rate[%d]!!\n",
++		     report_data->rates[0].data_rate, spinfo->tmp_rate_idx,
++		     ssv_rc->rc_table[rc_sta->pinfo.
++				      rinfo[spinfo->tmp_rate_idx].rc_index].
++		     hw_rate_idx, spinfo->txrate_idx,
++		     ssv_rc->rc_table[rc_sta->pinfo.
++				      rinfo[spinfo->txrate_idx].rc_index].
++		     hw_rate_idx);
++#endif
++		return;
++	}
++	if (report_data_index == spinfo->txrate_idx) {
++		spinfo->tx_num_xmit += report_data->rates[0].count;
++		spinfo->tx_num_failed +=
++		    (report_data->rates[0].count - report_data->ampdu_ack_len);
++		rate = &pidrate[spinfo->txrate_idx];
++		rate->this_fail +=
++		    (report_data->rates[0].count - report_data->ampdu_ack_len);
++		rate->this_attempt += report_data->rates[0].count;
++		rate->this_success += report_data->ampdu_ack_len;
++	}
++	if (report_data_index != spinfo->txrate_idx
++	    && report_data_index == spinfo->tmp_rate_idx) {
++		spinfo->feedback_probes += report_data->ampdu_len;
++		rate = &pidrate[spinfo->tmp_rate_idx];
++		rate->this_fail +=
++		    (report_data->rates[0].count - report_data->ampdu_ack_len);
++		rate->this_attempt += report_data->rates[0].count;
++		rate->this_success += report_data->ampdu_ack_len;
++	}
++	period = msecs_to_jiffies(RC_PID_INTERVAL);
++	if (time_after(jiffies, spinfo->last_sample + period)) {
++#ifdef RATE_CONTROL_PERCENTAGE_TRACE
++		rate = &pidrate[spinfo->txrate_idx];
++		if (rate->this_success > rate->this_attempt) {
++			dev_dbg(sc->dev, "this_success[%ld] this_attempt[%ld]\n",
++			       rate->this_success, rate->this_attempt);
++		} else {
++			if (percentage == 0)
++				percentage =
++				    (int)((rate->this_success * 100) /
++					  rate->this_attempt);
++			else
++				percentage =
++				    (percentage +
++				     (int)((rate->this_success * 100) /
++					   rate->this_attempt)) / 2;
++			deb_dbg(sc->dev, "Percentage[%d]\n", percentage);
++			if ((percentageCounter % 16) == 1)
++				percentage = 0;
++		}
++#endif
++#ifdef RATE_CONTROL_STUPID_DEBUG
++		if (spinfo->txrate_idx != spinfo->tmp_rate_idx) {
++			rate = &pidrate[spinfo->tmp_rate_idx];
++			if (spinfo->monitoring && ((rate->this_attempt == 0)
++						   || (rate->this_attempt !=
++						       MAXPROBES))) {
++				dev_dbg(sc->dev, "Probe result a[%ld]s[%ld]f[%ld]",
++				       rate->this_attempt, rate->this_success,
++				       rate->this_fail);
++			}
++			rate = &pidrate[spinfo->txrate_idx];
++			dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
++			       rate->this_success, rate->this_fail);
++		} else {
++			rate = &pidrate[spinfo->txrate_idx];
++			dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
++			       rate->this_success, rate->this_fail);
++		}
++		dev_dbg(sc->dev, "w[%d]x%03d-f%03d\n", rc_sta->rc_wsid,
++		       spinfo->tx_num_xmit, spinfo->tx_num_failed);
++#endif
++		rate_control_pid_sample(sc->rc, pinfo, rc_sta, spinfo);
++	}
++}
++
++void ssv6xxx_sample_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, rc_sample_work);
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct sk_buff *skb;
++	struct cfg_host_event *host_event;
++	struct ssv_sta_rc_info *rc_sta = NULL;
++	struct firmware_rate_control_report_data *report_data;
++	struct ssv_sta_info *ssv_sta;
++	u8 hw_wsid = 0;
++	sc->rc_sample_sechedule = 1;
++	while (1) {
++		skb = skb_dequeue(&sc->rc_report_queue);
++		if (skb == NULL)
++			break;
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++		{
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++#endif
++		host_event = (struct cfg_host_event *)skb->data;
++		if ((host_event->h_event == SOC_EVT_RC_AMPDU_REPORT)
++		    || (host_event->h_event == SOC_EVT_RC_MPDU_REPORT)) {
++			report_data =
++			    (struct firmware_rate_control_report_data *)
++			    &host_event->dat[0];
++			hw_wsid = report_data->wsid;
++		} else {
++			dev_warn(sc->dev, "rate control sampling got garbage\n");
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		if (hw_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
++#ifdef RATE_CONTROL_DEBUG
++			dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-0!!\n");
++#endif
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		ssv_sta = &sc->sta_info[hw_wsid];
++		if (ssv_sta->sta == NULL) {
++			dev_err(sc->dev, "Null STA %d for RC report.\n",
++				hw_wsid);
++			rc_sta = NULL;
++		} else {
++			struct ssv_sta_priv_data *ssv_sta_priv =
++			    (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv;
++			rc_sta = &ssv_rc->sta_rc_info[ssv_sta_priv->rc_idx];
++			if (rc_sta->rc_wsid != hw_wsid) {
++				rc_sta = NULL;
++			}
++		}
++		if (rc_sta == NULL) {
++			dev_err(sc->dev,
++				"[RC]rc_sta is NULL pointer Check-1!!\n");
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		if (rc_sta == NULL) {
++#ifdef RATE_CONTROL_DEBUG
++			dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-2!!\n");
++#endif
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		if (rc_sta->is_ht) {
++			ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
++			ssv6xxx_ht_report_handler(sc, skb, rc_sta);
++		} else
++			ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
++		dev_kfree_skb_any(skb);
++	}
++	sc->rc_sample_sechedule = 0;
++}
++
++static void ssv6xxx_tx_status(void *priv,
++			      struct ieee80211_supported_band *sband,
++			      struct ieee80211_sta *sta, void *priv_sta,
++			      struct sk_buff *skb)
++{
++	struct ssv_softc *sc;
++	struct ieee80211_hdr *hdr;
++	__le16 fc;
++	hdr = (struct ieee80211_hdr *)skb->data;
++	fc = hdr->frame_control;
++	if (!priv_sta || !ieee80211_is_data_qos(fc))
++		return;
++	sc = (struct ssv_softc *)priv;
++	if (conf_is_ht(&sc->hw->conf)
++	    && (!(skb->protocol == cpu_to_be16(ETH_P_PAE)))) {
++		if (skb_get_queue_mapping(skb) != IEEE80211_AC_VO)
++			ssv6200_ampdu_tx_update_state(priv, sta, skb);
++	}
++	return;
++}
++
++static void rateControlGetRate(u8 rateIndex, char *pointer)
++{
++	switch (rateIndex) {
++	case 0:
++		sprintf(pointer, "1Mbps");
++		return;
++	case 1:
++	case 4:
++		sprintf(pointer, "2Mbps");
++		return;
++	case 2:
++	case 5:
++		sprintf(pointer, "5.5Mbps");
++		return;
++	case 3:
++	case 6:
++		sprintf(pointer, "11Mbps");
++		return;
++	case 7:
++		sprintf(pointer, "6Mbps");
++		return;
++	case 8:
++		sprintf(pointer, "9Mbps");
++		return;
++	case 9:
++		sprintf(pointer, "12Mbps");
++		return;
++	case 10:
++		sprintf(pointer, "18Mbps");
++		return;
++	case 11:
++		sprintf(pointer, "24Mbps");
++		return;
++	case 12:
++		sprintf(pointer, "36Mbps");
++		return;
++	case 13:
++		sprintf(pointer, "48Mbps");
++		return;
++	case 14:
++		sprintf(pointer, "54Mbps");
++		return;
++	case 15:
++	case 31:
++		sprintf(pointer, "MCS0-l");
++		return;
++	case 16:
++	case 32:
++		sprintf(pointer, "MCS1-l");
++		return;
++	case 17:
++	case 33:
++		sprintf(pointer, "MCS2-l");
++		return;
++	case 18:
++	case 34:
++		sprintf(pointer, "MCS3-l");
++		return;
++	case 19:
++	case 35:
++		sprintf(pointer, "MCS4-l");
++		return;
++	case 20:
++	case 36:
++		sprintf(pointer, "MCS5-l");
++		return;
++	case 21:
++	case 37:
++		sprintf(pointer, "MCS6-l");
++		return;
++	case 22:
++	case 38:
++		sprintf(pointer, "MCS7-l");
++		return;
++	case 23:
++		sprintf(pointer, "MCS0-s");
++		return;
++	case 24:
++		sprintf(pointer, "MCS1-s");
++		return;
++	case 25:
++		sprintf(pointer, "MCS2-s");
++		return;
++	case 26:
++		sprintf(pointer, "MCS3-s");
++		return;
++	case 27:
++		sprintf(pointer, "MCS4-s");
++		return;
++	case 28:
++		sprintf(pointer, "MCS5-s");
++		return;
++	case 29:
++		sprintf(pointer, "MCS6-s");
++		return;
++	case 30:
++		sprintf(pointer, "MCS7-s");
++		return;
++	default:
++		sprintf(pointer, "Unknow");
++		return;
++	};
++}
++
++static void ssv6xxx_get_rate(void *priv, struct ieee80211_sta *sta,
++			     void *priv_sta,
++			     struct ieee80211_tx_rate_control *txrc)
++{
++	struct ssv_softc *sc = priv;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ssv_sta_rc_info *rc_sta = priv_sta;
++	struct sk_buff *skb = txrc->skb;
++	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_tx_rate *rates = tx_info->control.rates;
++	struct rc_pid_sta_info *spinfo = &rc_sta->spinfo;
++	struct ssv_rc_rate *rc_rate = NULL;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	int rateidx = 99;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0)
++	if (rate_control_send_low(sta, priv_sta, txrc)) {
++		int i = 0;
++		int total_rates =
++		    (sizeof(ssv_11bgn_rate_table) /
++		     sizeof(ssv_11bgn_rate_table[0]));
++#if 1
++		if ((txrc->rate_idx_mask & (1 << rates[0].idx)) == 0) {
++			u32 rate_idx = rates[0].idx + 1;
++			u32 rate_idx_mask = txrc->rate_idx_mask >> rate_idx;
++			while (rate_idx_mask && (rate_idx_mask & 1) == 0) {
++				rate_idx_mask >>= 1;
++				rate_idx++;
++			}
++			if (rate_idx_mask)
++				rates[0].idx = rate_idx;
++			else {
++				WARN_ON(rate_idx_mask == 0);
++			}
++		}
++#endif
++		for (i = 0; i < total_rates; i++) {
++			if (rates[0].idx ==
++			    ssv_11bgn_rate_table[i].dot11_rate_idx) {
++				break;
++			}
++		}
++		if (i < total_rates)
++			rc_rate = &ssv_rc->rc_table[i];
++		else {
++			WARN_ON("Failed to find matching low rate.");
++		}
++	}
++#endif
++	if (rc_rate == NULL) {
++		if (conf_is_ht(&sc->hw->conf) &&
++		    (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
++			tx_info->flags |= IEEE80211_TX_CTL_LDPC;
++		if (conf_is_ht(&sc->hw->conf) &&
++		    (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_TX_STBC))
++			tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT);
++		if (sc->sc_flags & SC_OP_FIXED_RATE) {
++			rateidx = sc->max_rate_idx;
++		} else {
++			if (rc_sta->rc_valid == false) {
++				rateidx = 0;
++			} else {
++				if ((rc_sta->rc_wsid >=
++				     SSV_RC_MAX_HARDWARE_SUPPORT)
++				    || (rc_sta->rc_wsid < 0)) {
++					ssv_sta_priv =
++					    (struct ssv_sta_priv_data *)
++					    sta->drv_priv;
++					{
++						if ((rc_sta->ht_rc_type >=
++						     RC_TYPE_HT_SGI_20)
++						    &&
++						    (ssv_sta_priv->rx_data_rate
++						     <
++						     SSV62XX_RATE_MCS_INDEX)) {
++							rateidx =
++							    rc_sta->
++							    pinfo.rinfo
++							    [spinfo->txrate_idx].rc_index;
++						} else {
++							rateidx =
++							    ssv_sta_priv->rx_data_rate;
++						}
++					}
++				} else {
++					if (rc_sta->is_ht) {
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++						rateidx =
++						    rc_sta->ht.
++						    groups.rates[MCS_GROUP_RATES
++								 - 1].rc_index;
++#else
++						rateidx =
++						    rc_sta->pinfo.
++						    rinfo
++						    [spinfo->txrate_idx].rc_index;
++#endif
++					} else {
++						{
++							BUG_ON
++							    (spinfo->txrate_idx
++							     >=
++							     rc_sta->rc_num_rate);
++							rateidx =
++							    rc_sta->
++							    pinfo.rinfo
++							    [spinfo->txrate_idx].rc_index;
++						}
++						if (rateidx < 4) {
++							if (rateidx) {
++								if ((sc->sc_flags & SC_OP_SHORT_PREAMBLE)
++								    ||
++								    (txrc->short_preamble))
++								{
++									rateidx
++									    +=
++									    3;
++								}
++							}
++						}
++					}
++				}
++			}
++		}
++		rc_rate = &ssv_rc->rc_table[rateidx];
++		if (spinfo->real_hw_index != rc_rate->hw_rate_idx) {
++			char string[24];
++			rateControlGetRate(rc_rate->hw_rate_idx, string);
++		}
++		spinfo->real_hw_index = rc_rate->hw_rate_idx;
++		rates[0].count = 4;
++		rates[0].idx = rc_rate->dot11_rate_idx;
++		tx_info->control.rts_cts_rate_idx =
++		    ssv_rc->rc_table[rc_rate->ctrl_rate_idx].dot11_rate_idx;
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
++		if (rc_rate->rc_flags & RC_FLAG_HT) {
++			rates[0].flags |= IEEE80211_TX_RC_MCS;
++			if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++				rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
++			if (rc_rate->rc_flags & RC_FLAG_HT_GF)
++				rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
++		}
++	}
++	rates[1].count = 0;
++	rates[1].idx = -1;
++	rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
++	rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
++	rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
++}
++
++int pide_frame_duration(size_t len, int rate, int short_preamble, int flags)
++{
++	int dur = 0;
++	if (flags == WLAN_RC_PHY_CCK) {
++		dur = 10;
++		dur += short_preamble ? (72 + 24) : (144 + 48);
++		dur += DIV_ROUND_UP(8 * (len + 4) * 10, rate);
++	} else {
++		dur = 16;
++		dur += 16;
++		dur += 4;
++		dur += 4 * DIV_ROUND_UP((16 + 8 * (len + 4) + 6) * 10,
++					4 * rate);
++	}
++	return dur;
++}
++
++static void ssv62xx_rc_caps(struct ssv_sta_rc_info *rc_sta)
++{
++	struct rc_pid_sta_info *spinfo;
++	struct rc_pid_info *pinfo;
++	struct rc_pid_rateinfo *rinfo;
++	int i;
++	spinfo = &rc_sta->spinfo;
++	pinfo = &rc_sta->pinfo;
++	memset(spinfo, 0, sizeof(struct rc_pid_sta_info));
++	memset(pinfo, 0, sizeof(struct rc_pid_info));
++	rinfo = rc_sta->pinfo.rinfo;
++	for (i = 0; i < rc_sta->rc_num_rate; i++) {
++		rinfo[i].rc_index = ssv6xxx_rc_rate_set[rc_sta->rc_type][i + 1];
++		rinfo[i].diff = i * RC_PID_NORM_OFFSET;
++		rinfo[i].index = (u16) i;
++		rinfo[i].perfect_tx_time =
++		    TDIFS + (TSLOT * 15 >> 1) + pide_frame_duration(1530,
++								    ssv_11bgn_rate_table
++								    [rinfo
++								     [i].rc_index].rate_kbps
++								    / 100, 1,
++								    ssv_11bgn_rate_table
++								    [rinfo
++								     [i].rc_index].phy_type)
++		    + pide_frame_duration(10,
++					  ssv_11bgn_rate_table[rinfo[i].
++							       rc_index].rate_kbps
++					  / 100, 1,
++					  ssv_11bgn_rate_table[rinfo[i].
++							       rc_index].phy_type);
++		pr_debug("[RC]Init perfect_tx_time[%d][%d]\n", i,
++		       rinfo[i].perfect_tx_time);
++		rinfo[i].throughput = 0;
++	}
++	if (rc_sta->is_ht) {
++		if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0] == 12)
++			spinfo->txrate_idx = 4;
++		else
++			spinfo->txrate_idx = 0;
++	} else {
++		spinfo->txrate_idx = ssv6xxx_rate_lowest_index(rc_sta);
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++		spinfo->txrate_idx = ssv6xxx_rate_highest_index(rc_sta);
++#endif
++	}
++	spinfo->real_hw_index = 0;
++	spinfo->probe_cnt = MAXPROBES;
++	spinfo->tmp_rate_idx = spinfo->txrate_idx;
++	spinfo->oldrate = spinfo->txrate_idx;
++	spinfo->last_sample = jiffies;
++	spinfo->last_report = jiffies;
++}
++
++static void ssv6xxx_rate_update_rc_type(void *priv,
++					struct ieee80211_supported_band *sband,
++					struct ieee80211_sta *sta,
++					void *priv_sta)
++{
++	struct ssv_softc *sc = priv;
++	struct ssv_hw *sh = sc->sh;
++	struct ssv_sta_rc_info *rc_sta = priv_sta;
++	int i;
++	u32 ht_supp_rates = 0;
++	BUG_ON(rc_sta->rc_valid == false);
++	dev_dbg(sc->dev, "[I] %s(): \n", __FUNCTION__);
++	rc_sta->ht_supp_rates = 0;
++	rc_sta->rc_supp_rates = 0;
++	rc_sta->is_ht = 0;
++#ifndef CONFIG_CH14_SUPPORT_GN_MODE
++	if (sc->cur_channel->hw_value == 14) {
++		dev_dbg(sc->dev, "[RC init ]Channel 14 support\n");
++		if ((sta->deflink.supp_rates[sband->band] & (~0xfL)) == 0x0) {
++			dev_dbg(sc->dev, "[RC init ]B only mode\n");
++			rc_sta->rc_type = RC_TYPE_B_ONLY;
++		} else {
++			dev_dbg(sc->dev, "[RC init ]GB mode\n");
++			rc_sta->rc_type = RC_TYPE_LEGACY_GB;
++		}
++	} else
++#endif
++	if (sta->deflink.ht_cap.ht_supported == true) {
++		dev_dbg(sc->dev, "[RC init ]HT support wsid\n");
++		for (i = 0; i < SSV_HT_RATE_MAX; i++) {
++			if (sta->deflink.ht_cap.mcs.rx_mask[i /
++						    MCS_GROUP_RATES] & (1 << (i
++									      %
++									      MCS_GROUP_RATES)))
++				ht_supp_rates |= BIT(i);
++		}
++		rc_sta->ht_supp_rates = ht_supp_rates;
++		if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD) {
++			rc_sta->rc_type = RC_TYPE_HT_GF;
++			rc_sta->ht_rc_type = RC_TYPE_HT_GF;
++		} else if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) {
++			rc_sta->rc_type = RC_TYPE_SGI_20;
++			rc_sta->ht_rc_type = RC_TYPE_HT_SGI_20;
++		} else {
++			rc_sta->rc_type = RC_TYPE_LGI_20;
++			rc_sta->ht_rc_type = RC_TYPE_HT_LGI_20;
++		}
++	} else {
++		if ((sta->deflink.supp_rates[sband->band] & (~0xfL)) == 0x0) {
++			rc_sta->rc_type = RC_TYPE_B_ONLY;
++			dev_dbg(sc->dev, "[RC init ]B only mode\n");
++		} else {
++			rc_sta->rc_type = RC_TYPE_LEGACY_GB;
++			dev_dbg(sc->dev, "[RC init ]legacy G mode\n");
++		}
++	}
++#ifdef CONFIG_SSV_DPD
++	if (rc_sta->rc_type == RC_TYPE_B_ONLY) {
++		SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3D3E84FE);
++		SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x1457D79);
++		SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x0);
++	} else {
++		SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3CBE84FE);
++		SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x4507F9);
++		SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x3);
++	}
++#endif
++	if ((rc_sta->rc_type != RC_TYPE_B_ONLY)
++	    && (rc_sta->rc_type != RC_TYPE_LEGACY_GB)) {
++		if ((sta->deflink.ht_cap.ht_supported)
++		    && (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)) {
++			rc_sta->is_ht = 1;
++			ssv62xx_ht_rc_caps(ssv6xxx_rc_rate_set, rc_sta);
++		}
++	}
++	{
++		rc_sta->rc_num_rate =
++		    (u8) ssv6xxx_rc_rate_set[rc_sta->rc_type][0];
++		if ((rc_sta->rc_type == RC_TYPE_HT_GF)
++		    || (rc_sta->rc_type == RC_TYPE_LGI_20)
++		    || (rc_sta->rc_type == RC_TYPE_SGI_20)) {
++			if (rc_sta->rc_num_rate == 12) {
++				rc_sta->rc_supp_rates =
++				    sta->deflink.supp_rates[sband->band] & 0xfL;
++				rc_sta->rc_supp_rates |= (ht_supp_rates << 4);
++			} else
++				rc_sta->rc_supp_rates = ht_supp_rates;
++		} else if (rc_sta->rc_type == RC_TYPE_LEGACY_GB)
++			rc_sta->rc_supp_rates = sta->deflink.supp_rates[sband->band];
++		else if (rc_sta->rc_type == RC_TYPE_B_ONLY)
++			rc_sta->rc_supp_rates =
++			    sta->deflink.supp_rates[sband->band] & 0xfL;
++		ssv62xx_rc_caps(rc_sta);
++	}
++}
++
++static void ssv6xxx_rate_update(void *priv,
++				struct ieee80211_supported_band *sband,
++				struct cfg80211_chan_def *chandef,
++				struct ieee80211_sta *sta, void *priv_sta,
++				u32 changed)
++{
++	pr_debug("%s: changed=%d\n", __FUNCTION__, changed);
++	return;
++}
++
++static void ssv6xxx_rate_init(void *priv,
++			      struct ieee80211_supported_band *sband,
++			      struct cfg80211_chan_def *chandef,
++			      struct ieee80211_sta *sta, void *priv_sta)
++{
++	ssv6xxx_rate_update_rc_type(priv, sband, sta, priv_sta);
++}
++
++static void *ssv6xxx_rate_alloc_sta(void *priv, struct ieee80211_sta *sta,
++				    gfp_t gfp)
++{
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++#ifndef RC_STA_DIRECT_MAP
++	struct ssv_softc *sc = priv;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	int s;
++	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	for (s = 0; s < SSV_RC_MAX_STA; s++) {
++		if (ssv_rc->sta_rc_info[s].rc_valid == false) {
++			dev_dbg(sc->dev, "%s(): use index %d\n", __FUNCTION__, s);
++			memset(&ssv_rc->sta_rc_info[s], 0,
++			       sizeof(struct ssv_sta_rc_info));
++			ssv_rc->sta_rc_info[s].rc_valid = true;
++			ssv_rc->sta_rc_info[s].rc_wsid = -1;
++			sta_priv->rc_idx = s;
++			return &ssv_rc->sta_rc_info[s];
++		}
++	}
++	return NULL;
++#else
++	sta_priv->rc_idx = (-1);
++	return sta_priv;
++#endif
++}
++
++static void ssv6xxx_rate_free_sta(void *priv, struct ieee80211_sta *sta,
++				  void *priv_sta)
++{
++	struct ssv_sta_rc_info *rc_sta = priv_sta;
++	rc_sta->rc_valid = false;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
++static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw)
++#else
++static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw,
++				struct dentry *debugfsdir)
++#endif
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_rate_ctrl *ssv_rc;
++	sc->rc = kzalloc(sizeof(struct ssv_rate_ctrl), GFP_KERNEL);
++	if (!sc->rc) {
++		pr_err("%s(): Unable to allocate RC structure !\n",
++		       __FUNCTION__);
++		return NULL;
++	}
++	memset(sc->rc, 0, sizeof(struct ssv_rate_ctrl));
++	ssv_rc = (struct ssv_rate_ctrl *)sc->rc;
++	ssv_rc->rc_table = ssv_11bgn_rate_table;
++	skb_queue_head_init(&sc->rc_report_queue);
++	INIT_WORK(&sc->rc_sample_work, ssv6xxx_sample_work);
++	sc->rc_sample_workqueue = create_workqueue("ssv6xxx_rc_sample");
++	sc->rc_sample_sechedule = 0;
++	return hw->priv;
++}
++
++static void ssv6xxx_rate_free(void *priv)
++{
++	struct ssv_softc *sc = priv;
++	if (sc->rc) {
++		kfree(sc->rc);
++		sc->rc = NULL;
++	}
++	sc->rc_sample_sechedule = 0;
++	cancel_work_sync(&sc->rc_sample_work);
++	flush_workqueue(sc->rc_sample_workqueue);
++	destroy_workqueue(sc->rc_sample_workqueue);
++}
++
++static struct rate_control_ops ssv_rate_ops = {
++	.name = "ssv6xxx_rate_control",
++	.tx_status = ssv6xxx_tx_status,
++	.get_rate = ssv6xxx_get_rate,
++	.rate_init = ssv6xxx_rate_init,
++	.rate_update = ssv6xxx_rate_update,
++	.alloc = ssv6xxx_rate_alloc,
++	.free = ssv6xxx_rate_free,
++	.alloc_sta = ssv6xxx_rate_alloc_sta,
++	.free_sta = ssv6xxx_rate_free_sta,
++};
++
++void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc,
++				 int hw_rate_idx,
++				 struct ieee80211_rx_status *rxs)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ssv_rc_rate *rc_rate;
++	BUG_ON(hw_rate_idx >= RATE_TABLE_SIZE && hw_rate_idx < 0);
++	rc_rate = &ssv_rc->rc_table[hw_rate_idx];
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)
++	if (rc_rate->rc_flags & RC_FLAG_HT) {
++		// rxs->flag |= RC_FLAG_HT;
++		if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++			rxs->enc_flags |= RX_ENC_FLAG_SHORT_GI;
++	} else {
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rxs->enc_flags |= RX_ENC_FLAG_SHORTPRE;
++	}
++#else
++	if (rc_rate->rc_flags & RC_FLAG_HT) {
++		rxs->flag |= RC_FLAG_HT;
++		if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++			rxs->flag |= RX_FLAG_SHORT_GI;
++	} else {
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rxs->flag |= RX_FLAG_SHORTPRE;
++	}
++#endif
++	rxs->rate_idx = rc_rate->dot11_rate_idx;
++}
++
++void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
++			    struct ieee80211_tx_info *info,
++			    struct ssv_rate_info *sr)
++{
++	struct ieee80211_tx_rate *tx_rate;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	tx_rate = &info->control.rates[0];
++	sr->d_flags =
++	    (ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].phy_type ==
++	     WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
++	sr->d_flags |=
++	    (ssv_rc->
++	     rc_table[tx_rate[SSV_DRATE_IDX].
++		      count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
++	    IEEE80211_RATE_SHORT_PREAMBLE : 0;
++	sr->c_flags =
++	    (ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].phy_type ==
++	     WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
++	sr->c_flags |=
++	    (ssv_rc->
++	     rc_table[tx_rate[SSV_CRATE_IDX].
++		      count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
++	    IEEE80211_RATE_SHORT_PREAMBLE : 0;
++	sr->drate_kbps =
++	    ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].rate_kbps;
++	sr->drate_hw_idx = tx_rate[SSV_DRATE_IDX].count;
++	sr->crate_kbps =
++	    ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].rate_kbps;
++	sr->crate_hw_idx = tx_rate[SSV_CRATE_IDX].count;
++}
++
++u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
++				   u32 do_rts_cts)
++{
++	int ret = 0;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++	struct ieee80211_sta *sta = skb_info->sta;
++	struct ieee80211_tx_rate *rates = &tx_info->control.rates[0];
++	struct ssv_rc_rate *rc_rate = NULL;
++	u8 rateidx = 0;
++	struct ssv_sta_rc_info *rc_sta = NULL;
++	struct rc_pid_sta_info *spinfo;
++	struct ssv_sta_priv_data *sta_priv = NULL;
++	unsigned long period = 0;
++	if (sc->sc_flags & SC_OP_FIXED_RATE)
++		return ret;
++	if (sta == NULL)
++		return ret;
++	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	if (sta_priv == NULL) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg(rc->dev, "%s sta_priv == NULL \n\r", __FUNCTION__);
++#endif
++		return ret;
++	}
++	if ((sta_priv->rc_idx < 0) || (sta_priv->rc_idx >= SSV_RC_MAX_STA)) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg(sc->dev, "%s rc_idx %x illegal \n\r", __FUNCTION__,
++		       sta_priv->rc_idx);
++#endif
++		return ret;
++	}
++	rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
++	if (rc_sta->rc_valid == false) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg(sc->dev, "%s rc_valid false \n\r", __FUNCTION__);
++#endif
++		return ret;
++	}
++	spinfo = &rc_sta->spinfo;
++	period = msecs_to_jiffies(RC_PID_REPORT_INTERVAL);
++	if (time_after(jiffies, spinfo->last_report + period)) {
++		ret |= RC_FIRMWARE_REPORT_FLAG;
++		spinfo->last_report = jiffies;
++	}
++	{
++		if (spinfo->monitoring) {
++			if (spinfo->probe_report_flag == 0) {
++				ret |= RC_FIRMWARE_REPORT_FLAG;
++				spinfo->last_report = jiffies;
++				spinfo->probe_report_flag = 1;
++				rateidx = spinfo->real_hw_index;
++			} else if (spinfo->probe_cnt > 0
++				   && spinfo->probe_report_flag) {
++				rateidx =
++				    rc_sta->pinfo.rinfo[spinfo->
++							tmp_rate_idx].rc_index;
++				spinfo->probe_cnt--;
++				if (spinfo->probe_cnt == 0) {
++					ret |= RC_FIRMWARE_REPORT_FLAG;
++					spinfo->last_report = jiffies;
++				}
++			} else
++				rateidx = spinfo->real_hw_index;
++		} else
++			rateidx = spinfo->real_hw_index;
++	}
++	if (rateidx >= RATE_TABLE_SIZE) {
++		dev_err(sc->dev, "rateidx over range\n");
++		return 0;
++	}
++	rc_rate = &ssv_rc->rc_table[rateidx];
++#ifdef RATE_CONTROL_STUPID_DEBUG
++	if (spinfo->monitoring && (spinfo->probe_cnt)) {
++		char string[24];
++		rateControlGetRate(rc_rate->hw_rate_idx, string);
++		dev_dbg(sc->dev, "[RC]Probe rate[%s]\n", string);
++	}
++#endif
++	if (rc_rate == NULL)
++		return ret;
++	if (rc_rate->hw_rate_idx != rates[SSV_DRATE_IDX].count) {
++		rates[0].flags = 0;
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
++		if (rc_rate->rc_flags & RC_FLAG_HT) {
++			rates[0].flags |= IEEE80211_TX_RC_MCS;
++			if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++				rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
++			if (rc_rate->rc_flags & RC_FLAG_HT_GF)
++				rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
++		}
++		rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
++		if (do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
++			rates[SSV_CRATE_IDX].count = 0;
++		} else {
++			rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
++			rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
++		}
++		ret |= 0x1;
++	}
++	return ret;
++}
++
++void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ssv_sta_rc_info *rc_sta;
++	u32 rc_hw_reg[] = { ADR_MTX_MIB_WSID0, ADR_MTX_MIB_WSID1 };
++	BUG_ON(rc_idx >= SSV_RC_MAX_STA);
++	rc_sta = &ssv_rc->sta_rc_info[rc_idx];
++	if (hwidx >= 0 && hwidx < SSV_NUM_HW_STA) {
++		rc_sta->rc_wsid = hwidx;
++		dev_dbg(sc->dev, "rc_wsid[%d] rc_idx[%d]\n", rc_sta[rc_idx].rc_wsid,
++		       rc_idx);
++		SMAC_REG_WRITE(sc->sh, rc_hw_reg[hwidx], 0x40000000);
++	} else {
++		rc_sta->rc_wsid = -1;
++	}
++}
++
++#define UPDATE_PHY_INFO_ACK_RATE(_phy_info,_ack_rate_idx) ( _phy_info = (_phy_info&0xfffffc0f)|(_ack_rate_idx<<4))
++int ssv6xxx_rc_update_bmode_ctrl_rate(struct ssv_softc *sc, int rate_tbl_idx,
++				      int ctrl_rate_idx)
++{
++	u32 temp32;
++	struct ssv_hw *sh = sc->sh;
++	u32 addr;
++	addr = sh->hw_pinfo + rate_tbl_idx * 4;
++	ssv_11bgn_rate_table[rate_tbl_idx].ctrl_rate_idx = ctrl_rate_idx;
++	SMAC_REG_READ(sh, addr, &temp32);
++	UPDATE_PHY_INFO_ACK_RATE(temp32, ctrl_rate_idx);
++	SMAC_REG_WRITE(sh, addr, temp32);
++	SMAC_REG_CONFIRM(sh, addr, temp32);
++	return 0;
++}
++
++void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates)
++{
++	int i;
++	int rate_idx, pre_rate_idx = 0;
++	for (i = 0; i < 4; i++) {
++		if (((basic_rates >> i) & 0x01)) {
++			rate_idx = i;
++			pre_rate_idx = i;
++		} else
++			rate_idx = pre_rate_idx;
++		ssv6xxx_rc_update_bmode_ctrl_rate(sc, i, rate_idx);
++		if (i)
++			ssv6xxx_rc_update_bmode_ctrl_rate(sc, i + 3, rate_idx);
++	}
++}
++
++int ssv6xxx_rate_control_register(void)
++{
++	return ieee80211_rate_control_register(&ssv_rate_ops);
++}
++
++void ssv6xxx_rate_control_unregister(void)
++{
++	ieee80211_rate_control_unregister(&ssv_rate_ops);
++}
++
++void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
++				u32 rate_index)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_sta *sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
++	if (sta == NULL) {
++		return;
++	}
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ssv_sta_priv->rx_data_rate = rate_index;
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
+new file mode 100644
+index 000000000000..911c182897fa
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
+@@ -0,0 +1,50 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_RC_H_
++#define _SSV_RC_H_
++#include "ssv_rc_common.h"
++#define RC_PID_REPORT_INTERVAL 40
++#define RC_PID_INTERVAL 125
++#define RC_PID_DO_ARITH_RIGHT_SHIFT(x,y) \
++ ((x) < 0 ? -((-(x)) >> (y)) : (x) >> (y))
++#define RC_PID_NORM_OFFSET 3
++#define RC_PID_SMOOTHING_SHIFT 1
++#define RC_PID_SMOOTHING (1 << RC_PID_SMOOTHING_SHIFT)
++#define RC_PID_COEFF_P 15
++#define RC_PID_COEFF_I 15
++#define RC_PID_COEFF_D 5
++#define MAXPROBES 3
++#define SSV_DRATE_IDX (2)
++#define SSV_CRATE_IDX (3)
++
++struct ssv_softc;
++struct ssv_rc_rate *ssv6xxx_rc_get_rate(int rc_index);
++void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
++			    struct ieee80211_tx_info *info,
++			    struct ssv_rate_info *sr);
++u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
++				   u32 do_rts_cts);
++void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc, int hw_rate_idx,
++				 struct ieee80211_rx_status *rxs);
++void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx);
++void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates);
++int ssv6xxx_rate_control_register(void);
++void ssv6xxx_rate_control_unregister(void);
++void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
++				u32 rate_index);
++int pide_frame_duration(size_t len, int rate, int short_preamble, int flags);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
+new file mode 100644
+index 000000000000..13f3fdd8072b
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
+@@ -0,0 +1,175 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_RC_COM_H_
++#define _SSV_RC_COM_H_
++#define SSV_RC_MAX_STA 8
++#define MCS_GROUP_RATES 8
++#define SSV_HT_RATE_MAX 8
++#define TDIFS 34
++#define TSLOT 9
++#define SSV_RC_MAX_HARDWARE_SUPPORT 2
++#define RC_FIRMWARE_REPORT_FLAG 0x80
++#define RC_FLAG_INVALID 0x00000001
++#define RC_FLAG_LEGACY 0x00000002
++#define RC_FLAG_HT 0x00000004
++#define RC_FLAG_HT_SGI 0x00000008
++#define RC_FLAG_HT_GF 0x00000010
++#define RC_FLAG_SHORT_PREAMBLE 0x00000020
++enum ssv6xxx_rc_phy_type {
++	WLAN_RC_PHY_CCK,
++	WLAN_RC_PHY_OFDM,
++	WLAN_RC_PHY_HT_20_SS_LGI,
++	WLAN_RC_PHY_HT_20_SS_SGI,
++	WLAN_RC_PHY_HT_20_SS_GF,
++};
++#define RATE_TABLE_SIZE 39
++#define RC_STA_VALID 0x00000001
++#define RC_STA_CAP_HT 0x00000002
++#define RC_STA_CAP_GF 0x00000004
++#define RC_STA_CAP_SGI_20 0x00000008
++#define RC_STA_CAP_SHORT_PREAMBLE 0x00000010
++#define SSV62XX_G_RATE_INDEX 7
++#define SSV62XX_RATE_MCS_INDEX 15
++#define SSV62XX_RATE_MCS_LGI_INDEX 15
++#define SSV62XX_RATE_MCS_SGI_INDEX 23
++#define SSV62XX_RATE_MCS_GREENFIELD_INDEX 31
++enum ssv_rc_rate_type {
++	RC_TYPE_B_ONLY = 0,
++	RC_TYPE_LEGACY_GB,
++	RC_TYPE_SGI_20,
++	RC_TYPE_LGI_20,
++	RC_TYPE_HT_SGI_20,
++	RC_TYPE_HT_LGI_20,
++	RC_TYPE_HT_GF,
++	RC_TYPE_MAX,
++};
++struct ssv_rate_info {
++	int crate_kbps;
++	int crate_hw_idx;
++	int drate_kbps;
++	int drate_hw_idx;
++	u32 d_flags;
++	u32 c_flags;
++};
++struct ssv_rc_rate {
++	u32 rc_flags;
++	u16 phy_type;
++	u32 rate_kbps;
++	u8 dot11_rate_idx;
++	u8 ctrl_rate_idx;
++	u8 hw_rate_idx;
++	u8 arith_shift;
++	u8 target_pf;
++};
++struct rc_pid_sta_info {
++	unsigned long last_sample;
++	unsigned long last_report;
++	u16 tx_num_failed;
++	u16 tx_num_xmit;
++	u8 probe_report_flag;
++	u8 probe_wating_times;
++	u8 real_hw_index;
++	int txrate_idx;
++	u8 last_pf;
++	s32 err_avg_sc;
++	int last_dlr;
++	u8 feedback_probes;
++	u8 monitoring;
++	u8 oldrate;
++	u8 tmp_rate_idx;
++	u8 probe_cnt;
++};
++struct rc_pid_rateinfo {
++	u16 rc_index;
++	u16 index;
++	s32 diff;
++	u16 perfect_tx_time;
++	u32 throughput;
++	unsigned long this_attempt;
++	unsigned long this_success;
++	unsigned long this_fail;
++	u64 attempt;
++	u64 success;
++	u64 fail;
++};
++struct rc_pid_info {
++	unsigned int target;
++	int oldrate;
++	struct rc_pid_rateinfo rinfo[12];
++};
++struct mcs_group {
++	unsigned int duration[MCS_GROUP_RATES];
++};
++struct minstrel_rate_stats {
++	u16 rc_index;
++	unsigned int attempts, last_attempts;
++	unsigned int success, last_success;
++	u64 att_hist, succ_hist;
++	unsigned int cur_tp;
++	unsigned int cur_prob, probability;
++	unsigned int retry_count;
++	unsigned int retry_count_rtscts;
++	u8 sample_skipped;
++};
++struct minstrel_mcs_group_data {
++	u8 index;
++	u8 column;
++	unsigned int max_tp_rate;
++	unsigned int max_tp_rate2;
++	unsigned int max_prob_rate;
++	struct minstrel_rate_stats rates[MCS_GROUP_RATES];
++};
++struct ssv62xx_ht {
++	unsigned int ampdu_len;
++	unsigned int ampdu_packets;
++	unsigned int avg_ampdu_len;
++	unsigned int max_tp_rate;
++	unsigned int max_tp_rate2;
++	unsigned int max_prob_rate;
++	int first_try_count;
++	int second_try_count;
++	int other_try_count;
++	unsigned long stats_update;
++	unsigned int overhead;
++	unsigned int overhead_rtscts;
++	unsigned int total_packets;
++	unsigned int sample_packets;
++	u8 sample_wait;
++	u8 sample_tries;
++	u8 sample_count;
++	u8 sample_slow;
++	struct minstrel_mcs_group_data groups;
++};
++struct ssv_sta_rc_info {
++	u8 rc_valid;
++	u8 rc_type;
++	u8 rc_num_rate;
++	s8 rc_wsid;
++	u8 ht_rc_type;
++	u8 is_ht;
++	u32 rc_supp_rates;
++	u32 ht_supp_rates;
++	struct rc_pid_info pinfo;
++	struct rc_pid_sta_info spinfo;
++	struct ssv62xx_ht ht;
++};
++struct ssv_rate_ctrl {
++	struct ssv_rc_rate *rc_table;
++	struct ssv_sta_rc_info sta_rc_info[SSV_RC_MAX_STA];
++};
++#define HT_RC_UPDATE_INTERVAL 1000
++#endif
+diff --git a/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
+new file mode 100644
+index 000000000000..10a9a77081db
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/irq.h>
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/vmalloc.h>
++#include <linux/gpio.h>
++#include <linux/mmc/host.h>
++#include <linux/delay.h>
++#include <linux/regulator/consumer.h>
++#include <asm/io.h>
++#include <linux/printk.h>
++#include <linux/err.h>
++
++static int g_wifidev_registered = 0;
++extern int ssvdevice_init(void);
++extern void ssvdevice_exit(void);
++extern int ssv6xxx_get_dev_status(void);
++
++static __init int ssv_init_module(void)
++{
++	int ret = 0;
++	int time = 5;
++
++	msleep(120);
++
++	g_wifidev_registered = 1;
++	ret = ssvdevice_init();
++
++	while(time-- > 0){
++		msleep(500);
++		if(ssv6xxx_get_dev_status() == 1)
++			break;
++		pr_info("%s : Retry to carddetect\n",__func__);
++	}
++
++	return ret;
++
++}
++static __exit void ssv_exit_module(void)
++{
++
++	if (g_wifidev_registered)
++    {
++        ssvdevice_exit();
++        msleep(50);
++        g_wifidev_registered = 0;
++    }
++
++    return;
++
++}
++
++module_init(ssv_init_module);
++module_exit(ssv_exit_module);
++
++MODULE_AUTHOR("iComm Semiconductor Co., Ltd");
++MODULE_FIRMWARE("ssv*-sw.bin");
++MODULE_FIRMWARE("ssv*-wifi.cfg");
++MODULE_DESCRIPTION("Shared library for SSV wireless LAN cards.");
++MODULE_LICENSE("Dual BSD/GPL");
++
+diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
+new file mode 100644
+index 000000000000..503df1ea6dc3
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
+@@ -0,0 +1,1765 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/export.h>
++#include <linux/platform_device.h>
++#include <linux/string.h>
++#include <ssv6200_reg.h>
++#include <ssv6200.h>
++#include <hci/hctrl.h>
++#include <smac/dev.h>
++#include "ssv_cmd.h"
++#include <ssv_version.h>
++#include <ssv6200_configuration.h>
++#define SSV_CMD_PRINTF()
++struct ssv6xxx_dev_table {
++	u32 address;
++	u32 val;
++};
++struct ssv6xxx_debug {
++	struct device *dev;
++	struct platform_device *pdev;
++	struct ssv6xxx_hwif_ops *ifops;
++};
++static struct ssv6xxx_debug *ssv6xxx_debug_ifops;
++static char sg_cmd_buffer[CLI_BUFFER_SIZE + 1];
++static char *sg_argv[CLI_ARG_SIZE];
++static u32 sg_argc;
++extern char *ssv6xxx_result_buf;
++#if defined (CONFIG_ARM64) || defined (__x86_64__)
++u64 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
++#else
++u32 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
++#endif
++EXPORT_SYMBOL(ssv6xxx_ifdebug_info);
++struct sk_buff *ssvdevice_skb_alloc(s32 len)
++{
++	struct sk_buff *skb;
++	skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
++	if (skb != NULL) {
++		skb_put(skb, 0x20);
++		skb_pull(skb, 0x20);
++	}
++	return skb;
++}
++
++void ssvdevice_skb_free(struct sk_buff *skb)
++{
++	dev_kfree_skb_any(skb);
++}
++
++static int ssv_cmd_help(int argc, char *argv[])
++{
++	extern struct ssv_cmd_table cmd_table[];
++	struct ssv_cmd_table *sc_tbl;
++	char tmpbf[161];
++	int total_cmd = 0;
++	{
++		sprintf(ssv6xxx_result_buf, "Usage:\n");
++		for (sc_tbl = &cmd_table[3]; sc_tbl->cmd; sc_tbl++) {
++			sprintf(tmpbf, "%-20s\t\t%s\n", sc_tbl->cmd,
++				sc_tbl->usage);
++			strcat(ssv6xxx_result_buf, tmpbf);
++			total_cmd++;
++		}
++		sprintf(tmpbf,
++			"Total CMDs: %d\n\nType cli help [CMD] for more detail command.\n\n",
++			total_cmd);
++		strcat(ssv6xxx_result_buf, tmpbf);
++	}
++	return 0;
++}
++
++static int ssv_cmd_reg(int argc, char *argv[])
++{
++	u32 addr, value, count;
++	char tmpbf[64], *endp;
++	int s;
++	if (argc == 4 && strcmp(argv[1], "w") == 0) {
++		addr = simple_strtoul(argv[2], &endp, 16);
++		value = simple_strtoul(argv[3], &endp, 16);
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
++		sprintf(ssv6xxx_result_buf, " => write [0x%08x]: 0x%08x\n",
++			addr, value);
++		return 0;
++	} else if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
++		count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
++		addr = simple_strtoul(argv[2], &endp, 16);
++		sprintf(ssv6xxx_result_buf, "ADDRESS: 0x%08x\n", addr);
++		for (s = 0; s < count; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++			sprintf(tmpbf, "%08x ", value);
++			strcat(ssv6xxx_result_buf, tmpbf);
++			if (((s + 1) & 0x07) == 0)
++				strcat(ssv6xxx_result_buf, "\n");
++		}
++		strcat(ssv6xxx_result_buf, "\n");
++		return 0;
++	} else {
++		sprintf(tmpbf, "reg [r|w] [address] [value|word-count]\n\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	return -1;
++}
++
++struct ssv6xxx_cfg ssv_cfg;
++EXPORT_SYMBOL(ssv_cfg);
++static int __string2u32(u8 * u8str, void *val, u32 arg)
++{
++	char *endp;
++	int base = 10;
++	if (u8str[0] == '0' && ((u8str[1] == 'x') || (u8str[1] == 'X')))
++		base = 16;
++	*(u32 *) val = simple_strtoul(u8str, &endp, base);
++	return 0;
++}
++
++static int __string2flag32(u8 * flag_str, void *flag, u32 arg)
++{
++	u32 *val = (u32 *) flag;
++	if (arg >= (sizeof(u32) << 3))
++		return -1;
++	if (strcmp(flag_str, "on") == 0) {
++		*val |= (1 << arg);
++		return 0;
++	}
++	if (strcmp(flag_str, "off") == 0) {
++		*val &= ~(1 << arg);
++		return 0;
++	}
++	return -1;
++}
++
++static int __string2mac(u8 * mac_str, void *val, u32 arg)
++{
++	int s, macaddr[6];
++	u8 *mac = (u8 *) val;
++	s = sscanf(mac_str, "%02x:%02x:%02x:%02x:%02x:%02x",
++		   &macaddr[0], &macaddr[1], &macaddr[2],
++		   &macaddr[3], &macaddr[4], &macaddr[5]);
++	if (s != 6)
++		return -1;
++	mac[0] = (u8) macaddr[0], mac[1] = (u8) macaddr[1];
++	mac[2] = (u8) macaddr[2], mac[3] = (u8) macaddr[3];
++	mac[4] = (u8) macaddr[4], mac[5] = (u8) macaddr[5];
++	return 0;
++}
++
++static int __string2str(u8 * path, void *val, u32 arg)
++{
++	u8 *temp = (u8 *) val;
++	sprintf(temp, "%s", path);
++	return 0;
++}
++
++static int __string2configuration(u8 * mac_str, void *val, u32 arg)
++{
++	unsigned int address, value;
++	int i;
++	i = sscanf(mac_str, "%08x:%08x", &address, &value);
++	if (i != 2)
++		return -1;
++	for (i = 0; i < EXTERNEL_CONFIG_SUPPORT; i++) {
++		if (ssv_cfg.configuration[i][0] == 0x0) {
++			ssv_cfg.configuration[i][0] = address;
++			ssv_cfg.configuration[i][1] = value;
++			return 0;
++		}
++	}
++	return 0;
++}
++
++struct ssv6xxx_cfg_cmd_table cfg_cmds[] = {
++	{"hw_mac", (void *)&ssv_cfg.maddr[0][0], 0, __string2mac},
++	{"hw_mac_2", (void *)&ssv_cfg.maddr[1][0], 0, __string2mac},
++	{"def_chan", (void *)&ssv_cfg.def_chan, 0, __string2u32},
++	{"hw_cap_ht", (void *)&ssv_cfg.hw_caps, 0, __string2flag32},
++	{"hw_cap_gf", (void *)&ssv_cfg.hw_caps, 1, __string2flag32},
++	{"hw_cap_2ghz", (void *)&ssv_cfg.hw_caps, 2, __string2flag32},
++	{"hw_cap_5ghz", (void *)&ssv_cfg.hw_caps, 3, __string2flag32},
++	{"hw_cap_security", (void *)&ssv_cfg.hw_caps, 4, __string2flag32},
++	{"hw_cap_sgi_20", (void *)&ssv_cfg.hw_caps, 5, __string2flag32},
++	{"hw_cap_sgi_40", (void *)&ssv_cfg.hw_caps, 6, __string2flag32},
++	{"hw_cap_ap", (void *)&ssv_cfg.hw_caps, 7, __string2flag32},
++	{"hw_cap_p2p", (void *)&ssv_cfg.hw_caps, 8, __string2flag32},
++	{"hw_cap_ampdu_rx", (void *)&ssv_cfg.hw_caps, 9, __string2flag32},
++	{"hw_cap_ampdu_tx", (void *)&ssv_cfg.hw_caps, 10, __string2flag32},
++	{"hw_cap_tdls", (void *)&ssv_cfg.hw_caps, 11, __string2flag32},
++	{"use_wpa2_only", (void *)&ssv_cfg.use_wpa2_only, 0, __string2u32},
++	{"wifi_tx_gain_level_gn", (void *)&ssv_cfg.wifi_tx_gain_level_gn, 0,
++	 __string2u32},
++	{"wifi_tx_gain_level_b", (void *)&ssv_cfg.wifi_tx_gain_level_b, 0,
++	 __string2u32},
++	{"rssi_ctl", (void *)&ssv_cfg.rssi_ctl, 0, __string2u32},
++	{"xtal_clock", (void *)&ssv_cfg.crystal_type, 0, __string2u32},
++	{"volt_regulator", (void *)&ssv_cfg.volt_regulator, 0, __string2u32},
++	{"force_chip_identity", (void *)&ssv_cfg.force_chip_identity, 0,
++	 __string2u32},
++	{"firmware_path", (void *)&ssv_cfg.firmware_path[0], 0, __string2str},
++	{"flash_bin_path", (void *)&ssv_cfg.flash_bin_path[0], 0, __string2str},
++	{"mac_address_path", (void *)&ssv_cfg.mac_address_path[0], 0,
++	 __string2str},
++	{"mac_output_path", (void *)&ssv_cfg.mac_output_path[0], 0,
++	 __string2str},
++	{"ignore_efuse_mac", (void *)&ssv_cfg.ignore_efuse_mac, 0,
++	 __string2u32},
++	{"mac_address_mode", (void *)&ssv_cfg.mac_address_mode, 0,
++	 __string2u32},
++	{"sr_bhvr", (void *)&ssv_cfg.sr_bhvr, 0, __string2u32},
++	{"register", NULL, 0, __string2configuration},
++	{NULL, NULL, 0, NULL},
++};
++
++EXPORT_SYMBOL(cfg_cmds);
++static int ssv_cmd_cfg(int argc, char *argv[])
++{
++	char temp_buf[64];
++	int s;
++	if (argc == 2 && strcmp(argv[1], "reset") == 0) {
++		memset(&ssv_cfg, 0, sizeof(ssv_cfg));
++		return 0;
++	} else if (argc == 2 && strcmp(argv[1], "show") == 0) {
++		strcpy(ssv6xxx_result_buf, ">> ssv6xxx config:\n");
++		sprintf(temp_buf, "    hw_caps = 0x%08x\n", ssv_cfg.hw_caps);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    def_chan = %d\n", ssv_cfg.def_chan);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    wifi_tx_gain_level_gn = %d\n",
++			ssv_cfg.wifi_tx_gain_level_gn);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    wifi_tx_gain_level_b = %d\n",
++			ssv_cfg.wifi_tx_gain_level_b);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    rssi_ctl = %d\n", ssv_cfg.rssi_ctl);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    sr_bhvr = %d\n", ssv_cfg.sr_bhvr);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    sta-mac = %02x:%02x:%02x:%02x:%02x:%02x",
++			ssv_cfg.maddr[0][0], ssv_cfg.maddr[0][1],
++			ssv_cfg.maddr[0][2], ssv_cfg.maddr[0][3],
++			ssv_cfg.maddr[0][4], ssv_cfg.maddr[0][5]);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		strcat(ssv6xxx_result_buf, "\n");
++		return 0;
++	}
++	if (argc != 4)
++		return -1;
++	for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
++		if (strcmp(cfg_cmds[s].cfg_cmd, argv[1]) == 0) {
++			cfg_cmds[s].translate_func(argv[3],
++						   cfg_cmds[s].var,
++						   cfg_cmds[s].arg);
++			strcpy(ssv6xxx_result_buf, "");
++			return 0;
++		}
++	}
++	return -1;
++}
++
++void *ssv_dbg_phy_table = NULL;
++EXPORT_SYMBOL(ssv_dbg_phy_table);
++u32 ssv_dbg_phy_len = 0;
++EXPORT_SYMBOL(ssv_dbg_phy_len);
++void *ssv_dbg_rf_table = NULL;
++EXPORT_SYMBOL(ssv_dbg_rf_table);
++u32 ssv_dbg_rf_len = 0;
++EXPORT_SYMBOL(ssv_dbg_rf_len);
++struct ssv_softc *ssv_dbg_sc = NULL;
++EXPORT_SYMBOL(ssv_dbg_sc);
++struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci = NULL;
++EXPORT_SYMBOL(ssv_dbg_ctrl_hci);
++struct Dump_Sta_Info {
++	char *dump_buf;
++	int sta_idx;
++};
++static void _dump_sta_info(struct ssv_softc *sc,
++			   struct ssv_vif_info *vif_info,
++			   struct ssv_sta_info *sta_info, void *param)
++{
++	char tmpbf[128];
++	struct Dump_Sta_Info *dump_sta_info = (struct Dump_Sta_Info *)param;
++	struct ssv_sta_priv_data *priv_sta =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	if ((sta_info->s_flags & STA_FLAG_VALID) == 0)
++		sprintf(tmpbf,
++			"        Station %d: %d is not valid\n",
++			dump_sta_info->sta_idx, priv_sta->sta_idx);
++	else
++		sprintf(tmpbf,
++			"        Station %d: %d\n"
++			"             Address: %02X:%02X:%02X:%02X:%02X:%02X\n"
++			"             WISD: %d\n"
++			"             AID: %d\n"
++			"             Sleep: %d\n",
++			dump_sta_info->sta_idx, priv_sta->sta_idx,
++			sta_info->sta->addr[0], sta_info->sta->addr[1],
++			sta_info->sta->addr[2], sta_info->sta->addr[3],
++			sta_info->sta->addr[4], sta_info->sta->addr[5],
++			sta_info->hw_wsid, sta_info->aid, sta_info->sleeping);
++	dump_sta_info->sta_idx++;
++	strcat(dump_sta_info->dump_buf, tmpbf);
++}
++
++void ssv6xxx_dump_sta_info(struct ssv_softc *sc, char *target_buf)
++{
++	int j;
++	char tmpbf[128];
++	struct Dump_Sta_Info dump_sta_info = { target_buf, 0 };
++	sprintf(tmpbf, "  >>>> bcast queue len[%d]\n", sc->bcast_txq.cur_qsize);
++	strcat(target_buf, tmpbf);
++	for (j = 0; j < SSV6200_MAX_VIF; j++) {
++		struct ieee80211_vif *vif = sc->vif_info[j].vif;
++		struct ssv_vif_priv_data *priv_vif;
++		struct ssv_sta_priv_data *sta_priv_iter;
++		if (vif == NULL) {
++			sprintf(tmpbf, "    VIF: %d is not used.\n", j);
++			strcat(target_buf, tmpbf);
++			continue;
++		}
++		sprintf(tmpbf,
++			"    VIF: %d - [%02X:%02X:%02X:%02X:%02X:%02X] type[%d] p2p[%d]\n",
++			j, vif->addr[0], vif->addr[1], vif->addr[2],
++			vif->addr[3], vif->addr[4], vif->addr[5], vif->type,
++			vif->p2p);
++		strcat(target_buf, tmpbf);
++		priv_vif = (struct ssv_vif_priv_data *)(vif->drv_priv);
++		list_for_each_entry(sta_priv_iter, &priv_vif->sta_list, list) {
++			if ((sta_priv_iter->sta_info->
++			     s_flags & STA_FLAG_VALID) == 0) {
++				sprintf(tmpbf, "    VIF: %d  is not valid.\n",
++					j);
++				strcat(target_buf, tmpbf);
++				continue;
++			}
++			_dump_sta_info(sc, &sc->vif_info[priv_vif->vif_idx],
++				       sta_priv_iter->sta_info, &dump_sta_info);
++		}
++	}
++}
++
++static int ssv_cmd_sta(int argc, char *argv[])
++{
++	if (argc >= 2 && strcmp(argv[1], "show") == 0)
++		ssv6xxx_dump_sta_info(ssv_dbg_sc, ssv6xxx_result_buf);
++	else
++		strcat(ssv6xxx_result_buf, "sta show\n\n");
++	return 0;
++}
++
++static int ssv_cmd_dump(int argc, char *argv[])
++{
++	u32 addr, regval;
++	char tmpbf[64];
++	int s;
++	if (!ssv6xxx_result_buf) {
++		pr_warn("ssv6xxx_result_buf = NULL!!\n");
++		return -1;
++	}
++	if (argc != 2) {
++		sprintf(tmpbf,
++			"dump [wsid|decision|phy-info|phy-reg|rf-reg]\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	if (strcmp(argv[1], "wsid") == 0) {
++		const u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
++		const u32 reg_wsid_tid0[] =
++		    { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
++		const u32 reg_wsid_tid7[] =
++		    { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
++		const u8 *op_mode_str[] = { "STA", "AP", "AD-HOC", "WDS" };
++		const u8 *ht_mode_str[] =
++		    { "Non-HT", "HT-MF", "HT-GF", "RSVD" };
++		for (s = 0; s < SSV_NUM_HW_STA; s++) {
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, reg_wsid[s], &regval)) ;
++			sprintf(tmpbf,
++				"==>WSID[%d]\n\tvalid[%d] qos[%d] op_mode[%s] ht_mode[%s]\n",
++				s, regval & 0x1, (regval >> 1) & 0x1,
++				op_mode_str[((regval >> 2) & 3)],
++				ht_mode_str[((regval >> 4) & 3)]);
++			strcat(ssv6xxx_result_buf, tmpbf);
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, reg_wsid[s] + 4, &regval)) ;
++			sprintf(tmpbf, "\tMAC[%02x:%02x:%02x:%02x:",
++				(regval & 0xff), ((regval >> 8) & 0xff),
++				((regval >> 16) & 0xff),
++				((regval >> 24) & 0xff));
++			strcat(ssv6xxx_result_buf, tmpbf);
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, reg_wsid[s] + 8, &regval)) ;
++			sprintf(tmpbf, "%02x:%02x]\n", (regval & 0xff),
++				((regval >> 8) & 0xff));
++			strcat(ssv6xxx_result_buf, tmpbf);
++			for (addr = reg_wsid_tid0[s]; addr <= reg_wsid_tid7[s];
++			     addr += 4) {
++				if (SSV_REG_READ1
++				    (ssv6xxx_debug_ifops, addr, &regval)) ;
++				sprintf(tmpbf, "\trx_seq%d[%d]\n",
++					((addr - reg_wsid_tid0[s]) >> 2),
++					((regval) & 0xffff));
++				strcat(ssv6xxx_result_buf, tmpbf);
++			}
++		}
++		return 0;
++	}
++	if (strcmp(argv[1], "decision") == 0) {
++		strcpy(ssv6xxx_result_buf, ">> Decision Table:\n");
++		for (s = 0, addr = ADR_MRX_FLT_TB0; s < 16; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
++			sprintf(tmpbf, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
++				s, addr, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n>> Decision Mask:\n");
++		for (s = 0, addr = ADR_MRX_FLT_EN0; s < 9; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
++			sprintf(tmpbf, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
++				s, addr, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n");
++		return 0;
++	}
++	if (strcmp(argv[1], "phy-info") == 0) {
++		return 0;
++	}
++	if (strcmp(argv[1], "phy-reg") == 0) {
++		struct ssv6xxx_dev_table *raw;
++		raw = (struct ssv6xxx_dev_table *)ssv_dbg_phy_table;
++		strcpy(ssv6xxx_result_buf, ">> PHY Register Table:\n");
++		for (s = 0; s < ssv_dbg_phy_len; s++, raw++) {
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, raw->address, &regval)) ;
++			sprintf(tmpbf, "   ADDR[0x%08x] = 0x%08x\n",
++				raw->address, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n");
++		return 0;
++	}
++	if (strcmp(argv[1], "rf-reg") == 0) {
++		struct ssv6xxx_dev_table *raw;
++		raw = (struct ssv6xxx_dev_table *)ssv_dbg_rf_table;
++		strcpy(ssv6xxx_result_buf, ">> RF Register Table:\n");
++		for (s = 0; s < ssv_dbg_rf_len; s++, raw++) {
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, raw->address, &regval)) ;
++			sprintf(tmpbf, "   ADDR[0x%08x] = 0x%08x\n",
++				raw->address, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n");
++		return 0;
++	}
++	return -1;
++}
++
++static int ssv_cmd_irq(int argc, char *argv[])
++{
++	char *endp;
++	u32 irq_sts;
++	if (argc >= 3 && strcmp(argv[1], "set") == 0) {
++		if (strcmp(argv[2], "mask") == 0 && argc == 4) {
++			irq_sts = simple_strtoul(argv[3], &endp, 16);
++			if (!ssv6xxx_debug_ifops->ifops->irq_setmask) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_setmask operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_setmask(ssv6xxx_debug_ifops->dev, irq_sts);
++			sprintf(ssv6xxx_result_buf,
++				"set sdio irq mask to 0x%08x\n", irq_sts);
++			return 0;
++		}
++		if (strcmp(argv[2], "enable") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_enable) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_enable operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_enable(ssv6xxx_debug_ifops->dev);
++			strcpy(ssv6xxx_result_buf, "enable sdio irq.\n");
++			return 0;
++		}
++		if (strcmp(argv[2], "disable") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_disable) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_disable operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_disable(ssv6xxx_debug_ifops->dev, false);
++			strcpy(ssv6xxx_result_buf, "disable sdio irq.\n");
++			return 0;
++		}
++		return -1;
++	} else if (argc == 3 && strcmp(argv[1], "get") == 0) {
++		if (strcmp(argv[2], "mask") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_getmask) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_getmask operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_getmask(ssv6xxx_debug_ifops->dev, &irq_sts);
++			sprintf(ssv6xxx_result_buf,
++				"sdio irq mask: 0x%08x, int_mask=0x%08x\n",
++				irq_sts, ssv_dbg_ctrl_hci->int_mask);
++			return 0;
++		}
++		if (strcmp(argv[2], "status") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_getstatus) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_getstatus operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_getstatus(ssv6xxx_debug_ifops->dev, &irq_sts);
++			sprintf(ssv6xxx_result_buf, "sdio irq status: 0x%08x\n",
++				irq_sts);
++			return 0;
++		}
++		return -1;
++	} else {
++		sprintf(ssv6xxx_result_buf,
++			"irq [set|get] [mask|enable|disable|status]\n");
++	}
++	return 0;
++}
++
++static int ssv_cmd_mac(int argc, char *argv[])
++{
++	char temp_str[128], *endp;
++	u32 s;
++	int i;
++	if (argc == 3 && !strcmp(argv[1], "wsid") && !strcmp(argv[2], "show")) {
++		for (s = 0; s < SSV_NUM_HW_STA; s++) {
++		}
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "rx")) {
++		if (!strcmp(argv[2], "enable")) {
++			ssv_dbg_sc->dbg_rx_frame = 1;
++		} else {
++			ssv_dbg_sc->dbg_rx_frame = 0;
++		}
++		sprintf(temp_str, "  dbg_rx_frame %d\n",
++			ssv_dbg_sc->dbg_rx_frame);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "tx")) {
++		if (!strcmp(argv[2], "enable")) {
++			ssv_dbg_sc->dbg_tx_frame = 1;
++		} else {
++			ssv_dbg_sc->dbg_tx_frame = 0;
++		}
++		sprintf(temp_str, "  dbg_tx_frame %d\n",
++			ssv_dbg_sc->dbg_tx_frame);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "rxq")
++		   && !strcmp(argv[2], "show")) {
++		sprintf(temp_str, ">> MAC RXQ: (%s)\n    cur_qsize=%d\n",
++			((ssv_dbg_sc->
++			  sc_flags & SC_OP_OFFCHAN) ? "off channel" :
++			 "on channel"), ssv_dbg_sc->rx.rxq_count);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 4 && !strcmp(argv[1], "set")
++		   && !strcmp(argv[2], "rate")) {
++		if (strcmp(argv[3], "auto") == 0) {
++			ssv_dbg_sc->sc_flags &= ~SC_OP_FIXED_RATE;
++			return 0;
++		}
++		i = simple_strtoul(argv[3], &endp, 10);
++		if (i < 0 || i > 38) {
++			strcpy(ssv6xxx_result_buf, " Invalid rat index !!\n");
++			return -1;
++		}
++		ssv_dbg_sc->max_rate_idx = i;
++		ssv_dbg_sc->sc_flags |= SC_OP_FIXED_RATE;
++		sprintf(temp_str, " Set rate to index %d\n", i);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "get")
++		   && !strcmp(argv[2], "rate")) {
++		if (ssv_dbg_sc->sc_flags & SC_OP_FIXED_RATE)
++			sprintf(temp_str, " Current Rate Index: %d\n",
++				ssv_dbg_sc->max_rate_idx);
++		else
++			sprintf(temp_str, "  Current Rate Index: auto\n");
++		strcpy(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else {
++		sprintf(temp_str, "mac [security|wsid|rxq]  [show]\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "mac [set|get] [rate] [auto|idx]\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "mac [rx|tx] [eable|disable]\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	}
++	return 0;
++}
++
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++void print_irq_count(void)
++{
++	char temp_str[512];
++	sprintf(temp_str, "irq debug (%s)\n",
++		ssv_dbg_ctrl_hci->irq_enable ? "enable" : "disable");
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "total irq (%d)\n", ssv_dbg_ctrl_hci->irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "invalid irq (%d)\n",
++		ssv_dbg_ctrl_hci->invalid_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "rx irq (%d)\n", ssv_dbg_ctrl_hci->rx_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "tx irq (%d)\n", ssv_dbg_ctrl_hci->tx_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "real tx count irq (%d)\n",
++		ssv_dbg_ctrl_hci->real_tx_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "tx  packet count (%d)\n",
++		ssv_dbg_ctrl_hci->irq_tx_pkt_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "rx packet (%d)\n",
++		ssv_dbg_ctrl_hci->irq_rx_pkt_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++}
++#endif
++void print_isr_info(void)
++{
++	char temp_str[512];
++	sprintf(temp_str, ">>>> HCI Calculate ISR TIME(%s) unit:us\n",
++		((ssv_dbg_ctrl_hci->isr_summary_eable) ? "enable" : "disable"));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_routine_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_routine_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_tx_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_tx_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_rx_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_idle_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_idle_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_rx_idle_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_idle_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_miss_cnt(%d)\n", ssv_dbg_ctrl_hci->isr_miss_cnt);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "prev_isr_jiffes(%lu)\n",
++		ssv_dbg_ctrl_hci->prev_isr_jiffes);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "prev_rx_isr_jiffes(%lu)\n",
++		ssv_dbg_ctrl_hci->prev_rx_isr_jiffes);
++	strcat(ssv6xxx_result_buf, temp_str);
++}
++
++static int ssv_cmd_hci(int argc, char *argv[])
++{
++	struct ssv_hw_txq *txq;
++	char temp_str[512];
++	int s, ac = 0;
++	if (argc == 3 && !strcmp(argv[1], "txq") && !strcmp(argv[2], "show")) {
++		for (s = 0; s < WMM_NUM_AC; s++) {
++			if (ssv_dbg_sc != NULL)
++				ac = ssv_dbg_sc->tx.ac_txqid[s];
++			txq = &ssv_dbg_ctrl_hci->hw_txq[s];
++			sprintf(temp_str, ">> txq[%d]", txq->txq_no);
++			if (ssv_dbg_sc != NULL)
++				sprintf(temp_str, "(%s): ",
++					((ssv_dbg_sc->
++					  sc_flags & SC_OP_OFFCHAN) ?
++					 "off channel" : "on channel"));
++			sprintf(temp_str, "cur_qsize=%d\n",
++				skb_queue_len(&txq->qhead));
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str,
++				"            max_qsize=%d, pause=%d, resume_thres=%d",
++				txq->max_qsize, txq->paused, txq->resum_thres);
++			if (ssv_dbg_sc != NULL)
++				sprintf(temp_str, " flow_control[%d]\n",
++					!!(ssv_dbg_sc->tx.
++					   flow_ctrl_status & (1 << ac)));
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "            Total %d frame sent\n",
++				txq->tx_pkt);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		sprintf(temp_str,
++			">> HCI Debug Counters:\n    read_rs0_info_fail=%d, read_rs1_info_fail=%d\n",
++			ssv_dbg_ctrl_hci->read_rs0_info_fail,
++			ssv_dbg_ctrl_hci->read_rs1_info_fail);
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str,
++			"    rx_work_running=%d, isr_running=%d, xmit_running=%d\n",
++			ssv_dbg_ctrl_hci->rx_work_running,
++			ssv_dbg_ctrl_hci->isr_running,
++			ssv_dbg_ctrl_hci->xmit_running);
++		strcat(ssv6xxx_result_buf, temp_str);
++		if (ssv_dbg_sc != NULL)
++			sprintf(temp_str, "    flow_ctrl_status=%08x\n",
++				ssv_dbg_sc->tx.flow_ctrl_status);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "rxq")
++		   && !strcmp(argv[2], "show")) {
++		sprintf(temp_str, ">> HCI RX Queue (%s): cur_qsize=%d\n",
++			((ssv_dbg_sc->
++			  sc_flags & SC_OP_OFFCHAN) ? "off channel" :
++			 "on channel"), ssv_dbg_ctrl_hci->rx_pkt);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
++		   && !strcmp(argv[2], "start")) {
++		ssv_dbg_ctrl_hci->isr_summary_eable = 1;
++		ssv_dbg_ctrl_hci->isr_routine_time = 0;
++		ssv_dbg_ctrl_hci->isr_tx_time = 0;
++		ssv_dbg_ctrl_hci->isr_rx_time = 0;
++		ssv_dbg_ctrl_hci->isr_idle_time = 0;
++		ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
++		ssv_dbg_ctrl_hci->isr_miss_cnt = 0;
++		ssv_dbg_ctrl_hci->prev_isr_jiffes = 0;
++		ssv_dbg_ctrl_hci->prev_rx_isr_jiffes = 0;
++		print_isr_info();
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
++		   && !strcmp(argv[2], "stop")) {
++		ssv_dbg_ctrl_hci->isr_summary_eable = 0;
++		print_isr_info();
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
++		   && !strcmp(argv[2], "show")) {
++		print_isr_info();
++		return 0;
++	}
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++	else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		 && !strcmp(argv[2], "reset")) {
++		ssv_dbg_ctrl_hci->irq_enable = 0;
++		ssv_dbg_ctrl_hci->irq_count = 0;
++		ssv_dbg_ctrl_hci->invalid_irq_count = 0;
++		ssv_dbg_ctrl_hci->tx_irq_count = 0;
++		ssv_dbg_ctrl_hci->real_tx_irq_count = 0;
++		ssv_dbg_ctrl_hci->rx_irq_count = 0;
++		ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
++		ssv_dbg_ctrl_hci->irq_rx_pkt_count = 0;
++		ssv_dbg_ctrl_hci->irq_tx_pkt_count = 0;
++		strcat(ssv6xxx_result_buf, "irq debug reset count\n");
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		   && !strcmp(argv[2], "show")) {
++		print_irq_count();
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		   && !strcmp(argv[2], "stop")) {
++		ssv_dbg_ctrl_hci->irq_enable = 0;
++		strcat(ssv6xxx_result_buf, "irq debug stop\n");
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		   && !strcmp(argv[2], "start")) {
++		ssv_dbg_ctrl_hci->irq_enable = 1;
++		strcat(ssv6xxx_result_buf, "irq debug start\n");
++		return 0;
++	}
++#endif
++	else {
++		strcat(ssv6xxx_result_buf,
++		       "hci [txq|rxq] [show]\nhci [isr_time] [start|stop|show]\n\n");
++		return 0;
++	}
++	return -1;
++}
++
++static int ssv_cmd_hwq(int argc, char *argv[])
++{
++#undef GET_FFO0_CNT
++#undef GET_FFO1_CNT
++#undef GET_FFO2_CNT
++#undef GET_FFO3_CNT
++#undef GET_FFO4_CNT
++#undef GET_FFO5_CNT
++#undef GET_FFO6_CNT
++#undef GET_FFO7_CNT
++#undef GET_FFO8_CNT
++#undef GET_FFO9_CNT
++#undef GET_FFO10_CNT
++#undef GET_FFO11_CNT
++#undef GET_FFO12_CNT
++#undef GET_FFO13_CNT
++#undef GET_FFO14_CNT
++#undef GET_FFO15_CNT
++#undef GET_FF0_CNT
++#undef GET_FF1_CNT
++#undef GET_FF3_CNT
++#undef GET_FF5_CNT
++#undef GET_FF6_CNT
++#undef GET_FF7_CNT
++#undef GET_FF8_CNT
++#undef GET_FF9_CNT
++#undef GET_FF10_CNT
++#undef GET_FF11_CNT
++#undef GET_FF12_CNT
++#undef GET_FF13_CNT
++#undef GET_FF14_CNT
++#undef GET_FF15_CNT
++#undef GET_FF4_CNT
++#undef GET_FF2_CNT
++#undef GET_TX_ID_ALC_LEN
++#undef GET_RX_ID_ALC_LEN
++#undef GET_AVA_TAG
++#define GET_FFO0_CNT ((value & 0x0000001f ) >> 0)
++#define GET_FFO1_CNT ((value & 0x000003e0 ) >> 5)
++#define GET_FFO2_CNT ((value & 0x00000c00 ) >> 10)
++#define GET_FFO3_CNT ((value & 0x000f8000 ) >> 15)
++#define GET_FFO4_CNT ((value & 0x00300000 ) >> 20)
++#define GET_FFO5_CNT ((value & 0x0e000000 ) >> 25)
++#define GET_FFO6_CNT ((value1 & 0x0000000f ) >> 0)
++#define GET_FFO7_CNT ((value1 & 0x000003e0 ) >> 5)
++#define GET_FFO8_CNT ((value1 & 0x00007c00 ) >> 10)
++#define GET_FFO9_CNT ((value1 & 0x000f8000 ) >> 15)
++#define GET_FFO10_CNT ((value1 & 0x00f00000 ) >> 20)
++#define GET_FFO11_CNT ((value1 & 0x3e000000 ) >> 25)
++#define GET_FFO12_CNT ((value2 & 0x00000007 ) >> 0)
++#define GET_FFO13_CNT ((value2 & 0x00000060 ) >> 5)
++#define GET_FFO14_CNT ((value2 & 0x00000c00 ) >> 10)
++#define GET_FFO15_CNT ((value2 & 0x001f8000 ) >> 15)
++#define GET_FF0_CNT ((value & 0x0000001f ) >> 0)
++#define GET_FF1_CNT ((value & 0x000001e0 ) >> 5)
++#define GET_FF3_CNT ((value & 0x00003800 ) >> 11)
++#define GET_FF5_CNT ((value & 0x000e0000 ) >> 17)
++#define GET_FF6_CNT ((value & 0x00700000 ) >> 20)
++#define GET_FF7_CNT ((value & 0x03800000 ) >> 23)
++#define GET_FF8_CNT ((value & 0x1c000000 ) >> 26)
++#define GET_FF9_CNT ((value & 0xe0000000 ) >> 29)
++#define GET_FF10_CNT ((value1 & 0x00000007 ) >> 0)
++#define GET_FF11_CNT ((value1 & 0x00000038 ) >> 3)
++#define GET_FF12_CNT ((value1 & 0x000001c0 ) >> 6)
++#define GET_FF13_CNT ((value1 & 0x00000600 ) >> 9)
++#define GET_FF14_CNT ((value1 & 0x00001800 ) >> 11)
++#define GET_FF15_CNT ((value1 & 0x00006000 ) >> 13)
++#define GET_FF4_CNT ((value1 & 0x000f8000 ) >> 15)
++#define GET_FF2_CNT ((value1 & 0x00700000 ) >> 20)
++#define GET_TX_ID_ALC_LEN ((value & 0x0003fe00 ) >> 9)
++#define GET_RX_ID_ALC_LEN ((value & 0x07fc0000 ) >> 18)
++#define GET_AVA_TAG ((value1 & 0x01ff0000 ) >> 16)
++	u32 addr, value, value1, value2;
++	char temp_str[512];
++	addr = ADR_RD_FFOUT_CNT1;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++	addr = ADR_RD_FFOUT_CNT2;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
++	addr = ADR_RD_FFOUT_CNT3;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value2)) ;
++	sprintf(temp_str,
++		"\n[TAG]  MCU - HCI - SEC -  RX - MIC - TX0 - TX1 - TX2 - TX3 - TX4 - SEC - MIC - TSH\n");
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str,
++		"OUTPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
++		GET_FFO0_CNT, GET_FFO1_CNT, GET_FFO3_CNT, GET_FFO4_CNT,
++		GET_FFO5_CNT, GET_FFO6_CNT, GET_FFO7_CNT, GET_FFO8_CNT,
++		GET_FFO9_CNT, GET_FFO10_CNT, GET_FFO11_CNT, GET_FFO12_CNT,
++		GET_FFO15_CNT);
++	strcat(ssv6xxx_result_buf, temp_str);
++	addr = ADR_RD_IN_FFCNT1;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++	addr = ADR_RD_IN_FFCNT2;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
++	sprintf(temp_str,
++		"INPUT  %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
++		GET_FF0_CNT, GET_FF1_CNT, GET_FF3_CNT, GET_FF4_CNT, GET_FF5_CNT,
++		GET_FF6_CNT, GET_FF7_CNT, GET_FF8_CNT, GET_FF9_CNT,
++		GET_FF10_CNT, GET_FF11_CNT, GET_FF12_CNT, GET_FF15_CNT);
++	strcat(ssv6xxx_result_buf, temp_str);
++	addr = ADR_ID_LEN_THREADSHOLD2;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++	addr = ADR_TAG_STATUS;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
++	sprintf(temp_str, "TX[%d]RX[%d]AVA[%d]\n", GET_TX_ID_ALC_LEN,
++		GET_RX_ID_ALC_LEN, GET_AVA_TAG);
++	strcat(ssv6xxx_result_buf, temp_str);
++	return 0;
++}
++
++#ifdef CONFIG_P2P_NOA
++static struct ssv6xxx_p2p_noa_param cmd_noa_param = {
++	50,
++	100,
++	0x12345678,
++	1,
++	255,
++	{0x4c, 0xe6, 0x76, 0xa2, 0x4e, 0x7c}
++};
++
++void noa_dump(char *temp_str)
++{
++	sprintf(temp_str,
++		"NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]\n",
++		cmd_noa_param.enable, cmd_noa_param.interval,
++		cmd_noa_param.duration, cmd_noa_param.start_time,
++		cmd_noa_param.count, cmd_noa_param.addr[0],
++		cmd_noa_param.addr[1], cmd_noa_param.addr[2],
++		cmd_noa_param.addr[3], cmd_noa_param.addr[4],
++		cmd_noa_param.addr[5]);
++	strcat(ssv6xxx_result_buf, temp_str);
++}
++
++void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
++			  struct ssv6xxx_p2p_noa_param *p2p_noa_param)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int retry_cnt = 5;
++	skb =
++	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
++				sizeof(struct ssv6xxx_p2p_noa_param));
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, p2p_noa_param,
++	       sizeof(struct ssv6xxx_p2p_noa_param));
++	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
++		pr_debug("NOA cmd retry=%d\n", retry_cnt);
++		retry_cnt--;
++	}
++	ssvdevice_skb_free(skb);
++}
++
++static int ssv_cmd_noa(int argc, char *argv[])
++{
++	char temp_str[512];
++	char *endp;
++	if (argc == 2 && !strcmp(argv[1], "show")) {
++		;
++	} else if (argc == 3 && !strcmp(argv[1], "duration")) {
++		cmd_noa_param.duration = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "interval")) {
++		cmd_noa_param.interval = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "start")) {
++		cmd_noa_param.start_time = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "enable")) {
++		cmd_noa_param.enable = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "count")) {
++		cmd_noa_param.count = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 8 && !strcmp(argv[1], "addr")) {
++		cmd_noa_param.addr[0] = simple_strtoul(argv[2], &endp, 16);
++		cmd_noa_param.addr[1] = simple_strtoul(argv[3], &endp, 16);
++		cmd_noa_param.addr[2] = simple_strtoul(argv[4], &endp, 16);
++		cmd_noa_param.addr[3] = simple_strtoul(argv[5], &endp, 16);
++		cmd_noa_param.addr[4] = simple_strtoul(argv[6], &endp, 16);
++		cmd_noa_param.addr[5] = simple_strtoul(argv[7], &endp, 16);
++	} else if (argc == 2 && !strcmp(argv[1], "send")) {
++		ssv6xxx_send_noa_cmd(ssv_dbg_sc, &cmd_noa_param);
++	} else {
++		sprintf(temp_str, "## wrong command\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	}
++	noa_dump(temp_str);
++	return 0;
++}
++#endif
++static int ssv_cmd_mib(int argc, char *argv[])
++{
++	u32 addr, value;
++	char temp_str[512];
++	int i;
++	if (argc == 2 && !strcmp(argv[1], "reset")) {
++		addr = MIB_REG_BASE;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
++		value = 0xffffffff;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
++		value = 0x100000;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
++		value = 0x100000;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
++		value = 0x80000000;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
++		sprintf(temp_str, " => MIB reseted\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if (argc == 2 && !strcmp(argv[1], "list")) {
++		addr = MIB_REG_BASE;
++		for (i = 0; i < 120; i++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++			sprintf(temp_str, "%08x ", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			if (((i + 1) & 0x07) == 0)
++				strcat(ssv6xxx_result_buf, "\n");
++		}
++		strcat(ssv6xxx_result_buf, "\n");
++	} else if (argc == 2 && strcmp(argv[1], "rx") == 0) {
++		sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t\t%-10s\n",
++			"MRX_FCS_SUCC", "MRX_FCS_ERR", "MRX_ALC_FAIL",
++			"MRX_MISS");
++		strcat(ssv6xxx_result_buf, temp_str);
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_MRX_FCS_SUCC, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_FCS_ERR, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_MRX_ALC_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MISS, &value)) {
++			sprintf(temp_str, "[%08x]\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t%-10s\n",
++				"MRX_MB_MISS", "MRX_NIDLE_MISS",
++				"DBG_LEN_ALC_FAIL", "DBG_LEN_CRC_FAIL");
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MB_MISS, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_MRX_NIDLE_MISS, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_LEN_ALC_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_LEN_CRC_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\n\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_PASS, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL1, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL2, &value)) {
++			sprintf(temp_str, "[%08x]\n\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "PHY B mode:\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
++				"CRC error", "CCA", "counter");
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023E8, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023EC, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "PHY G/N mode:\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
++				"CRC error", "CCA", "counter");
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043E8, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043EC, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++	} else {
++		sprintf(temp_str, "mib [reset|list|rx]\n\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	}
++	return 0;
++}
++
++static int ssv_cmd_sdio(int argc, char *argv[])
++{
++	u32 addr, value;
++	char temp_str[512], *endp;
++	int ret = 0;
++	if (argc == 4 && !strcmp(argv[1], "reg") && !strcmp(argv[2], "r")) {
++		addr = simple_strtoul(argv[3], &endp, 16);
++		if (!ssv6xxx_debug_ifops->ifops->cmd52_read) {
++			sprintf(temp_str,
++				"The interface doesn't provide cmd52 read\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++		ret =
++		    ssv6xxx_debug_ifops->ifops->cmd52_read(ssv6xxx_debug_ifops->
++							   dev, addr, &value);
++		if (ret >= 0) {
++			sprintf(temp_str, "  ==> %x\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++	} else if (argc == 5 && !strcmp(argv[1], "reg")
++		   && !strcmp(argv[2], "w")) {
++		addr = simple_strtoul(argv[3], &endp, 16);
++		value = simple_strtoul(argv[4], &endp, 16);
++		if (!ssv6xxx_debug_ifops->ifops->cmd52_write) {
++			sprintf(temp_str,
++				"The interface doesn't provide cmd52 write\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++		ret =
++		    ssv6xxx_debug_ifops->ifops->
++		    cmd52_write(ssv6xxx_debug_ifops->dev, addr, value);
++		if (ret >= 0) {
++			sprintf(temp_str, "  ==> write odne.\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++	}
++	sprintf(temp_str, "sdio cmd52 fail: %d\n", ret);
++	strcat(ssv6xxx_result_buf, temp_str);
++	return 0;
++}
++
++static struct ssv6xxx_iqk_cfg cmd_iqk_cfg = {
++	SSV6XXX_IQK_CFG_XTAL_26M,
++	SSV6XXX_IQK_CFG_PA_DEF,
++	0,
++	0,
++	26,
++	3,
++	0x75,
++	0x75,
++	0x80,
++	0x80,
++	SSV6XXX_IQK_CMD_INIT_CALI,
++	{SSV6XXX_IQK_TEMPERATURE
++	 + SSV6XXX_IQK_RXDC
++	 + SSV6XXX_IQK_RXRC
++	 + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ},
++};
++
++static int ssv_cmd_iqk(int argc, char *argv[])
++{
++	char temp_str[512], *endp;
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	u32 rxcnt_total, rxcnt_error;
++	sprintf(temp_str, "# got iqk command\n");
++	strcat(ssv6xxx_result_buf, temp_str);
++	if ((argc == 3) && (strcmp(argv[1], "cfg-pa") == 0)) {
++		cmd_iqk_cfg.cfg_pa = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## set cfg_pa as %d\n", cmd_iqk_cfg.cfg_pa);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if ((argc == 3) && (strcmp(argv[1], "cfg-tssi-trgt") == 0)) {
++		cmd_iqk_cfg.cfg_tssi_trgt = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## set cfg_tssi_trgt as %d\n",
++			cmd_iqk_cfg.cfg_tssi_trgt);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if ((argc == 3) && (strcmp(argv[1], "init-cali") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_INIT_CALI;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do init-cali\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-load") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-load\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-load-def") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD_DEF;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-load\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-reset") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_RESET;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-reset\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-set") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_SET;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-set\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-export") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_EXPORT;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-export\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "tk-evm") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_EVM;
++		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do tk-evm\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "tk-tone") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_TONE;
++		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do tk-tone\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "channel") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_CHCH;
++		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do change channel\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 2) && (strcmp(argv[1], "tk-rxcnt-report") == 0)) {
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0043E8, &rxcnt_error)) ;
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0043EC, &rxcnt_total)) ;
++		sprintf(temp_str, "## GN Rx error rate = (%06d/%06d)\n",
++			rxcnt_error, rxcnt_total);
++		strcat(ssv6xxx_result_buf, temp_str);
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0023E8, &rxcnt_error)) ;
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0023EC, &rxcnt_total)) ;
++		sprintf(temp_str, "## B Rx error rate = (%06d/%06d)\n",
++			rxcnt_error, rxcnt_total);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else {
++		sprintf(temp_str, "## invalid iqk command\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "## cmd: cfg-pa/cfg-tssi-trgt\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str,
++			"## cmd: init-cali/rtbl-load/rtbl-load-def/rtbl-reset/rtbl-set/rtbl-export/tk-evm/tk-tone/tk-channel\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "## fx_sel: 0x0008: RXDC\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0010: RXRC\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0020: TXDC\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0040: TXIQ\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0080: RXIQ\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0100: TSSI\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0200: PAPD\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	}
++	skb =
++	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN +
++				PHY_SETTING_SIZE + RF_SETTING_SIZE);
++	if (skb == NULL) {
++		pr_err("ssv command ssvdevice_skb_alloc failure\n");
++		return 0;
++	}
++	if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
++	    (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
++		pr_err("Please check RF or PHY table size\n");
++		BUG_ON(1);
++		return 0;
++	}
++	skb->data_len =
++	    HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
++	host_cmd->len = skb->data_len;
++	cmd_iqk_cfg.phy_tbl_size = PHY_SETTING_SIZE;
++	cmd_iqk_cfg.rf_tbl_size = RF_SETTING_SIZE;
++	memcpy(host_cmd->dat32, &cmd_iqk_cfg, IQK_CFG_LEN);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, asic_rf_setting,
++	       RF_SETTING_SIZE);
++	if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
++		sprintf(temp_str, "## hci send cmd success\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else {
++		sprintf(temp_str, "## hci send cmd fail\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	}
++	ssvdevice_skb_free(skb);
++	return 0;
++}
++
++#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
++    (((a) & 0xff00ff00) >> 8))
++#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
++static int ssv_cmd_version(int argc, char *argv[])
++{
++	char temp_str[256];
++	u32 regval;
++	u64 chip_tag = 0;
++	char chip_id[24] = "";
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_1, &regval)) ;
++	chip_tag = ((u64) regval << 32);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_0, &regval)) ;
++	chip_tag |= (regval);
++	sprintf(temp_str, "CHIP TAG: %llx \n", chip_tag);
++	strcat(ssv6xxx_result_buf, temp_str);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_3, &regval)) ;
++	*((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_2, &regval)) ;
++	*((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_1, &regval)) ;
++	*((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_0, &regval)) ;
++	*((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
++	sprintf(temp_str, "CHIP ID: %s \n", chip_id);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "# current Software mac version: %d\n",
++		ssv_root_version);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "SVN ROOT URL %s \n", SSV_ROOT_URl);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER HOST %s \n", COMPILERHOST);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER DATE %s \n", COMPILERDATE);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER OS %s \n", COMPILEROS);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER OS ARCH %s \n", COMPILEROSARCH);
++	strcat(ssv6xxx_result_buf, temp_str);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, FW_VERSION_REG, &regval)) ;
++	sprintf(temp_str, "Firmware image version: %d\n", regval);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "\n[Compiler Option!!]\n");
++	strcat(ssv6xxx_result_buf, temp_str);
++	return 0;
++}
++
++static int ssv_cmd_tool(int argc, char *argv[])
++{
++	u32 addr, value, count;
++	char tmpbf[12], *endp;
++	int s;
++	if (argc == 4 && strcmp(argv[1], "w") == 0) {
++		addr = simple_strtoul(argv[2], &endp, 16);
++		value = simple_strtoul(argv[3], &endp, 16);
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
++		sprintf(ssv6xxx_result_buf, "ok");
++		return 0;
++	}
++	if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
++		count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
++		addr = simple_strtoul(argv[2], &endp, 16);
++		for (s = 0; s < count; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++			sprintf(tmpbf, "%08x\n", value);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		return 0;
++	}
++	return -1;
++}
++
++struct _ssv6xxx_txtput {
++	struct task_struct *txtput_tsk;
++	struct sk_buff *skb;
++	u32 size_per_frame;
++	u32 loop_times;
++	u32 occupied_tx_pages;
++};
++struct _ssv6xxx_txtput *ssv6xxx_txtput;
++struct _ssv6xxx_txtput ssv_txtput = { NULL, NULL, 0, 0, 0 };
++
++static int txtput_thread_m2(void *data)
++{
++#define Q_DELAY_MS 20
++	struct sk_buff *skb = NULL;
++	struct ssv6200_tx_desc *tx_desc;
++	int qlen = 0, max_qlen, q_delay_urange[2];
++	max_qlen =
++	    (200 * 1000 / 8 * Q_DELAY_MS) / ssv6xxx_txtput->size_per_frame;
++	q_delay_urange[0] = Q_DELAY_MS * 1000;
++	q_delay_urange[1] = q_delay_urange[0] + 1000;
++	pr_debug("max_qlen: %d\n", max_qlen);
++	while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
++		ssv6xxx_txtput->loop_times--;
++		skb = ssvdevice_skb_alloc(ssv6xxx_txtput->size_per_frame);
++		if (skb == NULL) {
++			pr_debug("ssv command txtput_generate_m2 "
++			       "ssvdevice_skb_alloc fail!!!\n");
++			goto end;
++		}
++		skb->data_len = ssv6xxx_txtput->size_per_frame;
++		skb->len = ssv6xxx_txtput->size_per_frame;
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		memset((void *)tx_desc, 0xff, SSV6XXX_TX_DESC_LEN);
++		tx_desc->len = skb->len;
++		tx_desc->c_type = M2_TXREQ;
++		tx_desc->fCmd = (M_ENG_CPU << 4) | M_ENG_HWHCI;
++		tx_desc->reason = ID_TRAP_SW_TXTPUT;
++		qlen = ssv_dbg_ctrl_hci->shi->hci_ops->hci_tx(skb, 0, 0);
++		if (qlen >= max_qlen) {
++			usleep_range(q_delay_urange[0], q_delay_urange[1]);
++		}
++	}
++ end:
++	ssv6xxx_txtput->txtput_tsk = NULL;
++	return 0;
++}
++
++static int txtput_thread(void *data)
++{
++	struct sk_buff *skb = ssv6xxx_txtput->skb;
++	struct ssv6xxx_hci_txq_info2 txq_info2;
++	u32 ret = 0, free_tx_page;
++	int send_cnt;
++	unsigned long start_time, end_time, throughput, time_elapse;
++	throughput =
++	    ssv6xxx_txtput->loop_times * ssv6xxx_txtput->size_per_frame * 8;
++	start_time = jiffies;
++	while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
++		ret =
++		    SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_TX_ID_ALL_INFO2,
++				  (u32 *) & txq_info2);
++		if (ret < 0) {
++			pr_debug("%s, read ADR_TX_ID_ALL_INFO2 failed\n",
++			       __func__);
++			goto end;
++		}
++		free_tx_page =
++		    SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
++		send_cnt = free_tx_page / ssv6xxx_txtput->occupied_tx_pages;
++		while (send_cnt > 0 && ssv6xxx_txtput->loop_times > 0) {
++			send_cnt--;
++			ssv6xxx_txtput->loop_times--;
++			ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb);
++		}
++	}
++	end_time = jiffies;
++	ssvdevice_skb_free(skb);
++	time_elapse = ((end_time - start_time) * 1000) / HZ;
++	if (time_elapse > 0) {
++		throughput = throughput / time_elapse;
++		pr_debug("duration %ldms, avg. throughput %d Kbps\n", time_elapse,
++		       (int)throughput);
++	}
++ end:
++	ssv6xxx_txtput->txtput_tsk = NULL;
++	return 0;
++}
++
++int txtput_generate_m2(u32 size_per_frame, u32 loop_times)
++{
++	ssv6xxx_txtput->size_per_frame = size_per_frame;
++	ssv6xxx_txtput->loop_times = loop_times;
++	ssv6xxx_txtput->txtput_tsk =
++	    kthread_run(txtput_thread_m2, NULL, "txtput_thread_m2");
++	return 0;
++}
++
++int txtput_generate_host_cmd(u32 size_per_frame, u32 loop_times)
++{
++#define PAGESIZE 256
++	struct cfg_host_cmd *host_cmd;
++	struct sk_buff *skb;
++	skb = ssvdevice_skb_alloc(size_per_frame);
++	if (skb == NULL) {
++		pr_debug
++		    ("ssv command txtput_generate_host_cmd ssvdevice_skb_alloc fail!!!\n");
++		return 0;
++	}
++	skb->data_len = size_per_frame;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = TEST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_TX_TPUT;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, skb->data, size_per_frame);
++	ssv6xxx_txtput->occupied_tx_pages =
++	    (size_per_frame / PAGESIZE) + ((size_per_frame % PAGESIZE) != 0);
++	ssv6xxx_txtput->size_per_frame = size_per_frame;
++	ssv6xxx_txtput->loop_times = loop_times;
++	ssv6xxx_txtput->skb = skb;
++	ssv6xxx_txtput->txtput_tsk =
++	    kthread_run(txtput_thread, NULL, "txtput_thread");
++	return 0;
++}
++
++int txtput_tsk_cleanup(void)
++{
++	int ret = 0;
++	if (ssv6xxx_txtput->txtput_tsk) {
++		ret = kthread_stop(ssv6xxx_txtput->txtput_tsk);
++		ssv6xxx_txtput->txtput_tsk = NULL;
++	}
++	return ret;
++}
++
++int watchdog_controller(struct ssv_hw *sh, u8 flag)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int ret = 0;
++	pr_debug("watchdog_controller %d\n", flag);
++	skb = ssvdevice_skb_alloc(HOST_CMD_HDR_LEN);
++	if (skb == NULL) {
++		pr_err("init watchdog_controller failure\n");
++		return (-1);
++	}
++	skb->data_len = HOST_CMD_HDR_LEN;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) flag;
++	host_cmd->len = skb->data_len;
++	sh->hci.hci_ops->hci_send_cmd(skb);
++	ssvdevice_skb_free(skb);
++	return ret;
++}
++
++static int ssv_cmd_txtput(int argc, char *argv[])
++{
++	char tmpbf[64], *endp;
++	u32 size_per_frame, loop_times, pkt_type;
++	ssv6xxx_txtput = &ssv_txtput;
++	if (argc == 2 && !strcmp(argv[1], "stop")) {
++		txtput_tsk_cleanup();
++		return 0;
++	}
++	if (argc != 4) {
++		sprintf(tmpbf, "* txtput stop\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "* txtput [type] [size] [frames]\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "    type(packet type):\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "         0 = host_cmd\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "         1 = m2_type \n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, " EX: txtput 1 14000 9999 \n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	pkt_type = simple_strtoul(argv[1], &endp, 10);
++	size_per_frame = simple_strtoul(argv[2], &endp, 10);
++	loop_times = simple_strtoul(argv[3], &endp, 10);
++	sprintf(tmpbf, "type&size&frames:%d&%d&%d\n", pkt_type, size_per_frame,
++		loop_times);
++	strcat(ssv6xxx_result_buf, tmpbf);
++	if (ssv6xxx_txtput->txtput_tsk) {
++		sprintf(tmpbf, "txtput already in progress\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
++			    (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
++	((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
++	if (pkt_type)
++		txtput_generate_m2(size_per_frame + SSV6XXX_TX_DESC_LEN,
++				   loop_times);
++	else
++		txtput_generate_host_cmd(size_per_frame + HOST_CMD_HDR_LEN,
++					 loop_times);
++	return 0;
++}
++
++static int ssv_cmd_rxtput(int argc, char *argv[])
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	struct sdio_rxtput_cfg cmd_rxtput_cfg;
++	char tmpbf[32], *endp;
++	if (argc != 3) {
++		sprintf(ssv6xxx_result_buf, "rxtput [size] [frames]\n");
++		return 0;
++	}
++	skb =
++	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
++				sizeof(struct sdio_rxtput_cfg));
++	if (skb == NULL) {
++		pr_err("ssv command ssvdevice_skb_alloc fail\n");
++		return 0;
++	}
++	watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
++			    (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
++	((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
++	cmd_rxtput_cfg.size_per_frame = simple_strtoul(argv[1], &endp, 10);
++	cmd_rxtput_cfg.total_frames = simple_strtoul(argv[2], &endp, 10);
++	sprintf(tmpbf, "size&frames:%d&%d\n", cmd_rxtput_cfg.size_per_frame,
++		cmd_rxtput_cfg.total_frames);
++	strcat(ssv6xxx_result_buf, tmpbf);
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct sdio_rxtput_cfg);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_RX_TPUT;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, &cmd_rxtput_cfg,
++	       sizeof(struct sdio_rxtput_cfg));
++	if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
++		strcat(ssv6xxx_result_buf,
++		       "## hci cmd was sent successfully\n");
++	} else {
++		strcat(ssv6xxx_result_buf, "## hci cmd was sent failed\n");
++	}
++	ssvdevice_skb_free(skb);
++	return 0;
++}
++
++static int ssv_cmd_check(int argc, char *argv[])
++{
++	u32 size, i, j, x, y, id, value, address, id_value;
++	char *endp;
++	u32 id_base_address[4];
++	id_base_address[0] = 0xcd010008;
++	id_base_address[1] = 0xcd01000c;
++	id_base_address[2] = 0xcd010054;
++	id_base_address[3] = 0xcd010058;
++	if (argc != 2) {
++		sprintf(ssv6xxx_result_buf, "check [packet size]\n");
++		return 0;
++	}
++	size = simple_strtoul(argv[1], &endp, 10);
++	size = size >> 2;
++	for (x = 0; x < 4; x++) {
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, id_base_address[x], &id_value)) ;
++		for (y = 0; y < 32 && id_value; y++, id_value >>= 1) {
++			if (id_value & 0x1) {
++				id = 32 * x + y;
++				address = 0x80000000 + (id << 16);
++				{
++					for (i = 0; i < size; i += 8) {
++						if (SSV_REG_READ1
++						    (ssv6xxx_debug_ifops,
++						     address, &value)) ;
++						address += 4;
++						for (j = 1; j < 8; j++) {
++							if (SSV_REG_READ1
++							    (ssv6xxx_debug_ifops,
++							     address, &value)) ;
++							address += 4;
++						}
++					}
++				}
++			}
++		}
++	}
++	return 0;
++}
++
++struct ssv_cmd_table cmd_table[] = {
++	{"help", ssv_cmd_help, "ssv6200 command usage."},
++	{"-h", ssv_cmd_help, "ssv6200 command usage."},
++	{"--help", ssv_cmd_help, "ssv6200 command usage."},
++	{"reg", ssv_cmd_reg, "ssv6200 register read/write."},
++	{"cfg", ssv_cmd_cfg, "ssv6200 configuration."},
++	{"sta", ssv_cmd_sta, "svv6200 station info."},
++	{"dump", ssv_cmd_dump, "dump ssv6200 tables."},
++	{"hwq", ssv_cmd_hwq, "hardware queue staus"},
++#ifdef CONFIG_P2P_NOA
++	{"noa", ssv_cmd_noa, "config noa param"},
++#endif
++	{"irq", ssv_cmd_irq, "get sdio irq status."},
++	{"mac", ssv_cmd_mac, "ieee80211 swmac."},
++	{"hci", ssv_cmd_hci, "HCI command."},
++	{"sdio", ssv_cmd_sdio, "SDIO command."},
++	{"iqk", ssv_cmd_iqk, "iqk command"},
++	{"version", ssv_cmd_version, "version information"},
++	{"mib", ssv_cmd_mib, "mib counter related"},
++	{"tool", ssv_cmd_tool, "ssv6200 tool register read/write."},
++	{"rxtput", ssv_cmd_rxtput, "test rx sdio throughput"},
++	{"txtput", ssv_cmd_txtput, "test tx sdio throughput"},
++	{"check", ssv_cmd_check, "dump all allocate packet buffer"},
++	{NULL, NULL, NULL},
++};
++
++int ssv_cmd_submit(char *cmd)
++{
++	struct ssv_cmd_table *sc_tbl;
++	char *pch, ch;
++	int ret;
++	ssv6xxx_debug_ifops = (void *)ssv6xxx_ifdebug_info;
++	strcpy(sg_cmd_buffer, cmd);
++	for (sg_argc = 0, ch = 0, pch = sg_cmd_buffer;
++	     (*pch != 0x00) && (sg_argc < CLI_ARG_SIZE); pch++) {
++		if ((ch == 0) && (*pch != ' ')) {
++			ch = 1;
++			sg_argv[sg_argc] = pch;
++		}
++		if ((ch == 1) && (*pch == ' ')) {
++			*pch = 0x00;
++			ch = 0;
++			sg_argc++;
++		}
++	}
++	if (ch == 1) {
++		sg_argc++;
++	} else if (sg_argc > 0) {
++		*(pch - 1) = ' ';
++	}
++	if (sg_argc > 0) {
++		for (sc_tbl = cmd_table; sc_tbl->cmd; sc_tbl++) {
++			if (!strcmp(sg_argv[0], sc_tbl->cmd)) {
++				if ((sc_tbl->cmd_func_ptr != ssv_cmd_cfg) &&
++				    (!ssv6xxx_debug_ifops->dev ||
++				     !ssv6xxx_debug_ifops->ifops ||
++				     !ssv6xxx_debug_ifops->pdev)) {
++					strcpy(ssv6xxx_result_buf,
++					       "Member of ssv6xxx_ifdebug_info is NULL !\n");
++					return -1;
++				}
++				ssv6xxx_result_buf[0] = 0x00;
++				ret = sc_tbl->cmd_func_ptr(sg_argc, sg_argv);
++				if (ret < 0) {
++					strcpy(ssv6xxx_result_buf,
++					       "Invalid command !\n");
++				}
++				return 0;
++			}
++		}
++		strcpy(ssv6xxx_result_buf, "Command not found !\n");
++	} else {
++		strcpy(ssv6xxx_result_buf, "./cli -h\n");
++	}
++	return 0;
++}
+diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
+new file mode 100644
+index 000000000000..d96bfcc54954
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
+@@ -0,0 +1,50 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_CMD_H_
++#define _SSV_CMD_H_
++#define CLI_BUFFER_SIZE 256
++#define CLI_ARG_SIZE 10
++#define CLI_RESULT_BUF_SIZE (4096)
++#define DEBUG_DIR_ENTRY "ssv"
++#define DEBUG_DEVICETYPE_ENTRY "ssv_devicetype"
++#define DEBUG_CMD_ENTRY "ssv_cmd"
++#define MAX_CHARS_PER_LINE 256
++struct ssv_cmd_table {
++	const char *cmd;
++	int (*cmd_func_ptr)(int, char **);
++	const char *usage;
++};
++struct ssv6xxx_cfg_cmd_table {
++	u8 *cfg_cmd;
++	void *var;
++	u32 arg;
++	int (*translate_func)(u8 *, void *, u32);
++};
++#define SSV_REG_READ1(ops,reg,val) \
++        (ops)->ifops->readreg((ops)->dev, reg, val)
++#define SSV_REG_WRITE1(ops,reg,val) \
++        (ops)->ifops->writereg((ops)->dev, reg, val)
++#define SSV_REG_SET_BITS1(ops,reg,set,clr) \
++    { \
++        u32 reg_val; \
++        SSV_REG_READ(ops, reg, &reg_val); \
++        reg_val &= ~(clr); \
++        reg_val |= (set); \
++        SSV_REG_WRITE(ops, reg, reg_val); \
++    }
++int ssv_cmd_submit(char *cmd);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
+new file mode 100644
+index 000000000000..eb848553798f
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
+@@ -0,0 +1,256 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify 
++ * it under the terms of the GNU General Public License as published by 
++ * the Free Software Foundation, either version 3 of the License, or 
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but 
++ * WITHOUT ANY WARRANTY; without even the implied warranty of 
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License 
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/slab.h>
++#include <asm/uaccess.h>
++#include <linux/errno.h>
++#include "ssv_cmd.h"
++#include "ssv_cfg.h"
++#include <linux/fs.h>
++#include <asm/uaccess.h>
++#include <linux/buffer_head.h>
++#include <linux/ctype.h>
++
++#ifdef CONFIG_DEBUG_FS
++#include <linux/debugfs.h>
++#endif
++
++char *ssv_initmac = NULL;
++EXPORT_SYMBOL(ssv_initmac);
++module_param(ssv_initmac, charp, 0644);
++MODULE_PARM_DESC(ssv_initmac, "Wi-Fi MAC address");
++
++u32 ssv_devicetype = 0;
++EXPORT_SYMBOL(ssv_devicetype);
++
++#ifdef CONFIG_DEBUG_FS
++static struct dentry *debugfs;
++#endif
++
++struct proc_dir_entry *procfs;
++static char *ssv6xxx_cmd_buf;
++char *ssv6xxx_result_buf;
++extern struct ssv6xxx_cfg_cmd_table cfg_cmds[];
++extern struct ssv6xxx_cfg ssv_cfg;
++char DEFAULT_CFG_PATH[] = "/lib/firmware/ssv6051-wifi.cfg";
++static int ssv6xxx_dbg_open(struct inode *inode, struct file *filp)
++{
++	filp->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t ssv6xxx_dbg_read(struct file *filp, char __user * buffer,
++				size_t count, loff_t * ppos)
++{
++	int len;
++	if (*ppos != 0)
++		return 0;
++	len = strlen(ssv6xxx_result_buf) + 1;
++	if (len == 1)
++		return 0;
++	if (copy_to_user(buffer, ssv6xxx_result_buf, len))
++		return -EFAULT;
++	ssv6xxx_result_buf[0] = 0x00;
++	return len;
++}
++
++static ssize_t ssv6xxx_dbg_write(struct file *filp, const char __user * buffer,
++				 size_t count, loff_t * ppos)
++{
++	if (*ppos != 0 || count > 255)
++		return 0;
++	if (copy_from_user(ssv6xxx_cmd_buf, buffer, count))
++		return -EFAULT;
++	ssv6xxx_cmd_buf[count - 1] = 0x00;
++	ssv_cmd_submit(ssv6xxx_cmd_buf);
++	return count;
++}
++
++size_t read_line(struct file * fp, char *buf, size_t size)
++{
++	size_t num_read = 0;
++	size_t total_read = 0;
++	char *buffer;
++	char ch;
++	size_t start_ignore = 0;
++	if (size <= 0 || buf == NULL) {
++		total_read = -EINVAL;
++		return -EINVAL;
++	}
++	buffer = buf;
++	for (;;) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
++		num_read = kernel_read(fp, &ch, 1, &fp->f_pos);
++#else
++		mm_segment_t fs;
++		fs = get_fs();
++		set_fs(KERNEL_DS);
++		num_read = vfs_read(fp, &ch, 1, &fp->f_pos);
++		set_fs(fs);
++#endif
++		if (num_read < 0) {
++			if (num_read == EINTR)
++				continue;
++			else
++				return -1;
++		} else if (num_read == 0) {
++			if (total_read == 0)
++				return 0;
++			else
++				break;
++		} else {
++			if (ch == '#')
++				start_ignore = 1;
++			if (total_read < size - 1) {
++				total_read++;
++				if (start_ignore)
++					*buffer++ = '\0';
++				else
++					*buffer++ = ch;
++			}
++			if (ch == '\n')
++				break;
++		}
++	}
++	*buffer = '\0';
++	return total_read;
++}
++
++int ischar(char *c)
++{
++	int is_char = 1;
++	while (*c) {
++		if (isalpha(*c) || isdigit(*c) || *c == '_' || *c == ':'
++		    || *c == '/' || *c == '.' || *c == '-')
++			c++;
++		else {
++			is_char = 0;
++			break;
++		}
++	}
++	return is_char;
++}
++
++void sta_cfg_set(void)
++{
++	struct file *fp = (struct file *)NULL;
++	char buf[MAX_CHARS_PER_LINE], cfg_cmd[32], cfg_value[32];
++	size_t s, read_len = 0, is_cmd_support = 0;
++
++	memset(&ssv_cfg, 0, sizeof(ssv_cfg));
++	memset(buf, 0, sizeof(buf));
++	fp = filp_open(DEFAULT_CFG_PATH, O_RDONLY, 0);
++	if (IS_ERR(fp) || fp == NULL) {
++		WARN_ON(1);
++		return;
++	}
++	if (fp->f_path.dentry == NULL) {
++		WARN_ON(1);
++		return;
++	}
++	do {
++		memset(cfg_cmd, '\0', sizeof(cfg_cmd));
++		memset(cfg_value, '\0', sizeof(cfg_value));
++		read_len = read_line(fp, buf, MAX_CHARS_PER_LINE);
++		sscanf(buf, "%s = %s", cfg_cmd, cfg_value);
++		if (!ischar(cfg_cmd) || !ischar(cfg_value)) {
++			pr_warn("Invalid configuration parameter: %s\n", buf);
++			continue;
++		}
++		is_cmd_support = 0;
++		for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
++			if (strcmp(cfg_cmds[s].cfg_cmd, cfg_cmd) == 0) {
++				cfg_cmds[s].translate_func(cfg_value,
++							   cfg_cmds[s].var,
++							   cfg_cmds[s].arg);
++				is_cmd_support = 1;
++				break;
++			}
++		}
++		if (!is_cmd_support && strlen(cfg_cmd) > 0) {
++			pr_warn("Unsupported configuration command: %s", cfg_cmd);
++		}
++	} while (read_len > 0);
++	filp_close(fp, NULL);
++}
++
++static const struct file_operations ssv6xxx_dbg_fops = {
++	.owner = THIS_MODULE,
++	.open = ssv6xxx_dbg_open,
++	.read = ssv6xxx_dbg_read,
++	.write = ssv6xxx_dbg_write,
++};
++
++extern int ssv6xxx_hci_init(void);
++extern void ssv6xxx_hci_exit(void);
++extern int ssv6xxx_init(void);
++extern void ssv6xxx_exit(void);
++extern int ssv6xxx_sdio_init(void);
++extern void ssv6xxx_sdio_exit(void);
++
++int ssvdevice_init(void)
++{
++	ssv6xxx_cmd_buf =
++	    (char *)kzalloc(CLI_BUFFER_SIZE + CLI_RESULT_BUF_SIZE, GFP_KERNEL);
++	if (!ssv6xxx_cmd_buf)
++		return -ENOMEM;
++	ssv6xxx_result_buf = ssv6xxx_cmd_buf + CLI_BUFFER_SIZE;
++	ssv6xxx_cmd_buf[0] = 0x00;
++	ssv6xxx_result_buf[0] = 0x00;
++#ifdef CONFIG_DEBUG_FS
++	debugfs = debugfs_create_dir(DEBUG_DIR_ENTRY, NULL);
++	if (!debugfs)
++		return -ENOMEM;
++	debugfs_create_u32(DEBUG_DEVICETYPE_ENTRY, S_IRUGO | S_IWUSR, debugfs,
++			   &ssv_devicetype);
++	debugfs_create_file(DEBUG_CMD_ENTRY, S_IRUGO | S_IWUSR, debugfs, NULL,
++			    &ssv6xxx_dbg_fops);
++#endif
++	sta_cfg_set();
++	{
++		int ret;
++		ret = ssv6xxx_hci_init();
++		if (!ret) {
++			ret = ssv6xxx_init();
++		}
++		if (!ret) {
++			ret = ssv6xxx_sdio_init();
++		}
++		return ret;
++	}
++
++	return 0;
++}
++
++void ssvdevice_exit(void)
++{
++
++	ssv6xxx_exit();
++	ssv6xxx_hci_exit();
++	ssv6xxx_sdio_exit();
++
++#ifdef CONFIG_DEBUG_FS
++	debugfs_remove_recursive(debugfs);
++#endif
++	kfree(ssv6xxx_cmd_buf);
++}
++
++EXPORT_SYMBOL(ssvdevice_init);
++EXPORT_SYMBOL(ssvdevice_exit);
+-- 
+2.34.1
+
diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0001-arm64-dts.patch.disabled b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0001-arm64-dts.patch.disabled
new file mode 100644
index 000000000000..438dd52d3b55
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0001-arm64-dts.patch.disabled
@@ -0,0 +1,406 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: brentr <brent@mbari.org>
+Date: Fri, 23 Dec 2022 21:57:53 +0100
+Subject: [ARCHEOLOGY] Rockpis devtree mainlined (#4603)
+
+> X-Git-Archeology: > recovered message: > * moved rockpro64 patch out of rockpis patch sequence
+> X-Git-Archeology: > recovered message: > It had been misnamed
+> X-Git-Archeology: > recovered message: > * patch new mainline devtree for Rock Pi-S instead of overwritting it.
+> X-Git-Archeology: > recovered message: > Also restores lost bluetooth compatibility items on UART4
+> X-Git-Archeology: - Revision 588c2ec17e709dec19304fa50522459702ebfadd: https://github.com/armbian/build/commit/588c2ec17e709dec19304fa50522459702ebfadd
+> X-Git-Archeology:   Date: Fri, 23 Dec 2022 21:57:53 +0100
+> X-Git-Archeology:   From: brentr <brent@mbari.org>
+> X-Git-Archeology:   Subject: Rockpis devtree mainlined (#4603)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 240 +++++++---
+ 1 file changed, 164 insertions(+), 76 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+index e9810d2f0407..0d917658d24a 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+@@ -2,6 +2,7 @@
+ /*
+  * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
+  * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
++ * Revised: 2022 Brent Roman <brent@mbari.org>
+  */
+ 
+ /dts-v1/;
+@@ -11,12 +12,6 @@ / {
+ 	model = "Radxa ROCK Pi S";
+ 	compatible = "radxa,rockpis", "rockchip,rk3308";
+ 
+-	aliases {
+-		ethernet0 = &gmac;
+-		mmc0 = &emmc;
+-		mmc1 = &sdmmc;
+-	};
+-
+ 	chosen {
+ 		stdout-path = "serial0:1500000n8";
+ 	};
+@@ -27,48 +22,106 @@ leds {
+ 		pinctrl-0 = <&green_led>, <&heartbeat_led>;
+ 
+ 		green-led {
+ 			color = <LED_COLOR_ID_GREEN>;
+-			default-state = "on";
+ 			function = LED_FUNCTION_POWER;
+-			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ 			label = "rockpis:green:power";
++			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ 			linux,default-trigger = "default-on";
++			default-state = "on";
+ 		};
+ 
+ 		blue-led {
+ 			color = <LED_COLOR_ID_BLUE>;
+-			default-state = "on";
+ 			function = LED_FUNCTION_HEARTBEAT;
+-			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ 			label = "rockpis:blue:user";
++			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ 			linux,default-trigger = "heartbeat";
++			default-state = "on";
+ 		};
+ 	};
+ 
++	codec: acodec-sound {
++			compatible = "simple-audio-card";
++			simple-audio-card,format = "i2s";
++			simple-audio-card,name = "rockchip,rk3308-acodec";
++			simple-audio-card,mclk-fs = <256>;
++			simple-audio-card,codec-hp-det;
++			simple-audio-card,widgets =
++				"Headphone", "Headphones";
++			simple-audio-card,cpu {
++				sound-dai = <&i2s_8ch_2>;
++			};
++			simple-audio-card,codec {
++				sound-dai = <&acodec>;
++			};
++	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,name = "i2s_8ch_0";
++
++		simple-audio-card,dai-link@1 {
++			format = "i2s";
++			cpu {
++				sound-dai = <&i2s_8ch_0>;
++			};
++
++			codec {
++				sound-dai = <&pcm5102a>;
++			};
++		};
++	};
++
++	pcm5102a: pcm5102a {
++			#sound-dai-cells = <0>;
++			compatible = "ti,pcm5102a";
++			pcm510x,format = "i2s";
++	};
++
+ 	sdio_pwrseq: sdio-pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		pinctrl-0 = <&wifi_enable_h>;
+ 		pinctrl-names = "default";
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
+ 		reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ 	};
+ 
+-	vcc_1v8: vcc-1v8 {
++	vcc5v0_sys: vcc5v0-sys {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vcc_1v8";
++		regulator-name = "vcc5v0_sys";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		regulator-min-microvolt = <1800000>;
+-		regulator-max-microvolt = <1800000>;
+-		vin-supply = <&vcc_io>;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
+ 	};
+ 
+-	vcc_io: vcc-io {
++	vdd_core: vdd-core {
++		compatible = "pwm-regulator";
++		pwms = <&pwm0 0 5000 1>;
++		regulator-name = "vdd_core";
++		regulator-min-microvolt = <827000>;
++		regulator-max-microvolt = <1340000>;
++		regulator-init-microvolt = <1015000>;
++		regulator-settling-time-up-us = <250>;
++		regulator-always-on;
++		regulator-boot-on;
++		pwm-supply = <&vcc5v0_sys>;
++	};
++
++	vdd_log: vdd-log {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vcc_io";
++		regulator-name = "vdd_log";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
++		regulator-min-microvolt = <1050000>;
++		regulator-max-microvolt = <1050000>;
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
+ 
+@@ -78,49 +131,50 @@ vcc_ddr: vcc-ddr {
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
+ 
+-	vcc5v0_otg: vcc5v0-otg {
++	vcc_1v8: vcc-1v8 {
+ 		compatible = "regulator-fixed";
+-		enable-active-high;
+-		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&otg_vbus_drv>;
+-		regulator-name = "vcc5v0_otg";
++		regulator-name = "vcc_1v8";
+ 		regulator-always-on;
+-		vin-supply = <&vcc5v0_sys>;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_io>;
+ 	};
+ 
+-	vcc5v0_sys: vcc5v0-sys {
++	vcc_io: vcc-io {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vcc5v0_sys";
++		regulator-name = "vcc_io";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		regulator-min-microvolt = <5000000>;
+-		regulator-max-microvolt = <5000000>;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
+ 	};
+ 
+-	vdd_core: vdd-core {
+-		compatible = "pwm-regulator";
+-		pwms = <&pwm0 0 5000 1>;
+-		pwm-supply = <&vcc5v0_sys>;
+-		regulator-name = "vdd_core";
+-		regulator-min-microvolt = <827000>;
+-		regulator-max-microvolt = <1340000>;
+-		regulator-settling-time-up-us = <250>;
++  vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_phy";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+ 	};
+ 
+-	vdd_log: vdd-log {
++	vcc5v0_otg: vcc5v0-otg {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vdd_log";
++		regulator-name = "vcc5v0_otg";
+ 		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <1050000>;
+-		regulator-max-microvolt = <1050000>;
++		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++		pinctrl-names = "default";
++		pinctrl-0 = <&otg_vbus_drv>;
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
+ };
+ 
++&acodec {
++	status = "okay";
++	#sound-dai-cells = <0>;
++};
++
+ &cpu0 {
+ 	cpu-supply = <&vdd_core>;
+ };
+@@ -138,21 +138,59 @@
+ 	non-removable;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+-	vmmc-supply = <&vcc_io>;
+ 	status = "okay";
+ };
+ 
++&sdmmc {
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
++	card-detect-delay = <800>;
++	status = "okay";
++};
++
++&sdio {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	no-mmc;
++	status = "okay";
++
++	rtl8723ds: wifi@1 {
++			interrupt-parent = <&gpio0>;
++			interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
++			interrupt-names = "host-wake";
++			pinctrl-names = "default";
++			pinctrl-0 = <&wifi_host_wake>;
++	};
++};
++
+ &gmac {
++	phy-supply = <&vcc_phy>;
+ 	clock_in_out = "output";
+-	phy-supply = <&vcc_io>;
++	assigned-clocks = <&cru SCLK_MAC>;
++	assigned-clock-parents = <&cru SCLK_MAC_SRC>;
+ 	snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ 	snps,reset-active-low;
+ 	snps,reset-delays-us = <0 50000 50000>;
+ 	status = "okay";
+ };
+ 
+-&i2c1 {
++&i2s_8ch_0 {
++	assigned-clocks = <&cru SCLK_I2S0_8CH_RX>;
++	assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>;
++	rockchip,clk-trcm = <1>;
++	#sound-dai-cells = <0>;
++};
++
++&i2s_8ch_2 {
+ 	status = "okay";
++	#sound-dai-cells = <0>;
+ };
+ 
+ &pinctrl {
+@@ -171,7 +262,9 @@ sdio-pwrseq {
+ 		wifi_enable_h: wifi-enable-h {
+ 			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++	};
+ 
++	wifi {
+ 		wifi_host_wake: wifi-host-wake {
+ 			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ 		};
+@@ -188,42 +281,29 @@ &saradc {
+ 	status = "okay";
+ };
+ 
+-&sdio {
+-	#address-cells = <1>;
+-	#size-cells = <0>;
+-	cap-sd-highspeed;
+-	cap-sdio-irq;
+-	keep-power-in-suspend;
+-	max-frequency = <1000000>;
+-	mmc-pwrseq = <&sdio_pwrseq>;
+-	non-removable;
+-	sd-uhs-sdr104;
++&tsadc {
++	rockchip,hw-tshut-mode = <0>;		/* 0:CRU */
++	rockchip,hw-tshut-polarity = <1>;	/* 1:HIGH */
+ 	status = "okay";
+ };
+ 
+-&sdmmc {
+-	cap-sd-highspeed;
++&i2c1 {
+ 	status = "okay";
+ };
+ 
+-&u2phy {
+-	status = "okay";
+-
+-	u2phy_host: host-port {
+-		phy-supply = <&vcc5v0_otg>;
+-		status = "okay";
+-	};
+-
+-	u2phy_otg: otg-port {
+-		phy-supply = <&vcc5v0_otg>;
+-		status = "okay";
+-	};
++&spi2 {
++//	status = "okay";  //conflicts with UART2
++	max-freq = <10000000>;
+ };
+ 
+ &uart0 {
+ 	status = "okay";
+ };
+ 
++&uart2 {
++	status = "okay";
++};
++
+ &uart4 {
+ 	status = "okay";
+ 
+@@ -234,19 +314,27 @@ bluetooth {
+ 	};
+ };
+ 
+-&usb_host_ehci {
++&u2phy {
+ 	status = "okay";
++
++	u2phy_host: host-port {
++		phy-supply = <&vcc5v0_otg>;
++		status = "okay";
++	};
++
++	u2phy_otg: otg-port {
++		status = "okay";
++	};
+ };
+ 
+-&usb_host_ohci {
++&usb20_otg {
+ 	status = "okay";
+ };
+ 
+-&usb20_otg {
+-	dr_mode = "peripheral";
++&usb_host_ehci {
+ 	status = "okay";
+ };
+ 
+-&wdt {
++&usb_host_ohci{
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/rockchip64-6.6/board-station-p2.patch b/patch/kernel/archive/rockchip64-6.6/board-station-p2.patch
new file mode 100644
index 000000000000..670c56d8fea3
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.6/board-station-p2.patch
@@ -0,0 +1,580 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
+@@ -48,17 +48,15 @@
+ 		#clock-cells = <0>;
+ 	};
+ 
+-	leds {
++	firefly_leds: leds {
+ 		compatible = "gpio-leds";
+-
+-		led-user {
+-			label = "user-led";
++		power_led: power {
++			label = "firefly:blue:power";
++			linux,default-trigger = "ir-power-click";
+ 			default-state = "on";
+ 			gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+-			linux,default-trigger = "heartbeat";
+ 			pinctrl-names = "default";
+-			pinctrl-0 = <&user_led_enable_h>;
+-			retain-state-suspended;
++			pinctrl-0 = <&led_power>;
+ 		};
+ 	};
+ 
+@@ -126,41 +124,134 @@
+ 		vin-supply = <&dc_12v>;
+ 	};
+ 
+-	vcc5v0_usb: vcc5v0-usb-regulator {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc5v0_usb";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <5000000>;
+-		regulator-max-microvolt = <5000000>;
+-		vin-supply = <&vcc5v0_sys>;
+-	};
+-
+ 	vcc5v0_host: vcc5v0-host-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc5v0_host";
+ 		enable-active-high;
+-		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&vcc5v0_host_en>;
+ 		regulator-always-on;
+-		vin-supply = <&vcc5v0_usb>;
+ 	};
+ 
+ 	vcc5v0_otg: vcc5v0-otg-regulator {
+ 		compatible = "regulator-fixed";
+-		regulator-name = "vcc5v0_otg";
+ 		enable-active-high;
+ 		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&vcc5v0_otg_en>;
+-		vin-supply = <&vcc5v0_usb>;
++		regulator-name = "vcc5v0_otg";
+ 	};
+-};
+ 
+-&combphy0 {
+-	/* used for USB3 */
+-	status = "okay";
++	vcc2v5_sys: vcc2v5-ddr-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc2v5-sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <2500000>;
++		regulator-max-microvolt = <2500000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vcc_hub_power: vcc-hub-power-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc_hub_power_en>;
++		regulator-name = "vcc_hub_power_en";
++		regulator-always-on;
++	};
++
++	vcc_hub_reset: vcc-hub-reset-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc_hub_reset_en>;
++		regulator-name = "vcc_hub_reset_en";
++		regulator-always-on;
++	};
++
++	pcie_pi6c_oe: pcie-pi6c-oe-regulator {
++		compatible = "regulator-fixed";
++		//enable-active-high;
++		gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_pi6c_oe_en>;
++		regulator-name = "pcie_pi6c_oe_en";
++		regulator-always-on;
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		status = "okay";
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk809 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;
++		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
++		post-power-on-delay-ms = <100>;
++	};
++
++	wireless_wlan: wireless-wlan {
++		compatible = "wlan-platdata";
++		rockchip,grf = <&grf>;
++		wifi_chip_type = "ap6275s";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_host_wake_irq>;
++		WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
++		status = "okay";
++	};
++
++	wireless_bluetooth: wireless-bluetooth {
++		compatible = "bluetooth-platdata";
++		clocks = <&rk809 1>;
++		clock-names = "ext_clock";
++		//wifi-bt-power-toggle;
++		uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default", "rts_gpio";
++		pinctrl-0 = <&uart8m0_rtsn>;
++		pinctrl-1 = <&uart8_gpios>;
++		BT,reset_gpio    = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
++		BT,wake_gpio     = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
++		BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
++		status = "okay";
++	};
++
++	flash_led: flash-led {
++		compatible = "led,rgb13h";
++		label = "pwm-flash-led";
++		led-max-microamp = <20000>;
++		flash-max-microamp = <20000>;
++		flash-max-timeout-us = <1000000>;
++		pwms = <&pwm11 0 25000 0>;
++		rockchip,camera-module-index = <1>;
++		rockchip,camera-module-facing = "front";
++		status = "disabled";
++	};
++
++	rk809-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "Analog RK809";
++		simple-audio-card,mclk-fs = <256>;
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&rk809>;
++		};
++	};
++
++	rk_headset: rk-headset {
++		compatible = "rockchip_headset";
++		headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&hp_det>;
++		io-channels = <&saradc 2>;    //HP_HOOK pin
++	};
+ };
+ 
+ &combphy1 {
+@@ -247,15 +338,59 @@
+ &i2c0 {
+ 	status = "okay";
+ 
++	fusb0: fusb30x@22 {
++		compatible = "fairchild,fusb302";
++		reg = <0x22>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fusb0_int>;
++		int-n-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
++		fusb340-switch-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
++		vbus-5v-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++		status = "okay";
++	};
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		vin-supply = <&vcc5v0_sys>;
++		regulator-compatible = "fan53555-reg";
++		regulator-name = "vdd_cpu";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1390000>;
++		regulator-ramp-delay = <2300>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-boot-on;
++		regulator-always-on;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
+ 	rk809: pmic@20 {
+ 		compatible = "rockchip,rk809";
+ 		reg = <0x20>;
+ 		interrupt-parent = <&gpio0>;
+ 		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
++		assigned-clock-rates = <12288000>;
++		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ 		#clock-cells = <1>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&pmic_int>;
++		clock-names = "mclk";
++		clocks = <&cru I2S1_MCLKOUT_TX>;
++		pinctrl-names = "default", "pmic-sleep",
++				"pmic-power-off", "pmic-reset";
++		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
++
+ 		rockchip,system-power-controller;
++		#sound-dai-cells = <0>;
++		clock-output-names = "rk808-clkout1", "rk808-clkout2";
++		//fb-inner-reg-idxs = <2>;
++		/* 1: rst regs (default in codes), 0: rst the pmic */
++		pmic-reset-func = <0>;
++		/* not save the PMIC_POWER_EN register in uboot */
++		not-save-power-en = <1>;
++
+ 		vcc1-supply = <&vcc3v3_sys>;
+ 		vcc2-supply = <&vcc3v3_sys>;
+ 		vcc3-supply = <&vcc3v3_sys>;
+@@ -284,6 +419,8 @@
+ 			};
+ 
+ 			vdd_gpu: DCDC_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-name = "vdd_gpu";
+ 				regulator-init-microvolt = <900000>;
+ 				regulator-initial-mode = <0x2>;
+@@ -320,19 +457,9 @@
+ 				};
+ 			};
+ 
+-			vcc_1v8: DCDC_REG5 {
+-				regulator-name = "vcc_1v8";
+-				regulator-always-on;
+-				regulator-boot-on;
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+ 			vdda0v9_image: LDO_REG1 {
++				regulator-boot-on;
++				regulator-always-on;
+ 				regulator-name = "vdda0v9_image";
+ 				regulator-min-microvolt = <900000>;
+ 				regulator-max-microvolt = <900000>;
+@@ -368,6 +495,8 @@
+ 			};
+ 
+ 			vccio_acodec: LDO_REG4 {
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-name = "vccio_acodec";
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+@@ -379,6 +508,8 @@
+ 
+ 			vccio_sd: LDO_REG5 {
+ 				regulator-name = "vccio_sd";
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <3300000>;
+ 
+@@ -426,6 +557,8 @@
+ 			};
+ 
+ 			vcca1v8_image: LDO_REG9 {
++				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-name = "vcca1v8_image";
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <1800000>;
+@@ -435,6 +568,17 @@
+ 				};
+ 			};
+ 
++			vcc_1v8: DCDC_REG5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc_1v8";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
+ 			vcc_3v3: SWITCH_REG1 {
+ 				regulator-name = "vcc_3v3";
+ 				regulator-always-on;
+@@ -455,6 +599,10 @@
+ 				};
+ 			};
+ 		};
++
++		codec {
++			mic-in-differential;
++		};
+ 	};
+ };
+ 
+@@ -477,7 +625,7 @@
+ };
+ 
+ &pcie30phy {
+-	status = "okay";
++	tatus = "okay";
+ };
+ 
+ &pcie3x2 {
+@@ -490,19 +638,27 @@
+ 
+ &pinctrl {
+ 	leds {
+-		user_led_enable_h: user-led-enable-h {
+-			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		led_power: led-power {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+ 
+ 	usb {
+ 		vcc5v0_host_en: vcc5v0-host-en {
+-			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 
+ 		vcc5v0_otg_en: vcc5v0-otg-en {
+ 			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++
++		vcc_hub_power_en: vcc-hub-power-en {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc_hub_reset_en: vcc-hub-reset-en {
++			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
+ 	};
+ 
+ 	pcie {
+@@ -512,21 +668,53 @@
+ 		vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
+ 			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++		pcie_pi6c_oe_en: pcie-pi6c-oe-en {
++			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
+ 	};
+ 
+ 	pmic {
+-		pmic_int: pmic-int {
++		pmic_int: pmic_int {
+ 			rockchip,pins =
+ 				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	wireless-wlan {
++		wifi_host_wake_irq: wifi-host-wake-irq {
++			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	wireless-bluetooth {
++		uart8_gpios: uart8-gpios {
++			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	fusb30x {
++		fusb0_int: fusb0-int {
++			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	headphone {
++		hp_det: hp-det {
++			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
+ };
+ 
+ &pmu_io_domains {
+ 	pmuio1-supply = <&vcc3v3_pmu>;
+ 	pmuio2-supply = <&vcc3v3_pmu>;
+ 	vccio1-supply = <&vccio_acodec>;
+-	vccio2-supply = <&vcc_1v8>;
+ 	vccio3-supply = <&vccio_sd>;
+ 	vccio4-supply = <&vcc_1v8>;
+ 	vccio5-supply = <&vcc_3v3>;
+@@ -548,25 +736,44 @@
+ 	bus-width = <8>;
+ 	max-frequency = <200000000>;
+ 	non-removable;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
++	supports-emmc;
+ 	status = "okay";
+ };
+ 
+ &sdmmc0 {
+ 	bus-width = <4>;
+ 	cap-sd-highspeed;
+-	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ 	disable-wp;
+-	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ 	sd-uhs-sdr104;
+ 	vmmc-supply = <&vcc3v3_sd>;
+ 	vqmmc-supply = <&vccio_sd>;
++	max-frequency = <150000000>;
++	supports-sd;
++	cap-mmc-highspeed;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&sdmmc2 {
++	max-frequency = <150000000>;
++	supports-sdio;
++	bus-width = <4>;
++	disable-wp;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
++	sd-uhs-sdr104;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
+ 	status = "okay";
+ };
+ 
+ &tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
+ 	status = "okay";
+ };
+ 
+@@ -588,6 +795,7 @@
+ };
+ 
+ &usb2phy0_otg {
++	vbus-supply = <&vcc5v0_otg>;
+ 	status = "okay";
+ };
+ 
+@@ -609,6 +817,10 @@
+ 	status = "okay";
+ };
+ 
++&usb_host0_xhci {
++	status = "okay";
++};
++
+ &usb_host1_ehci {
+ 	status = "okay";
+ };
+@@ -617,11 +829,13 @@
+ 	status = "okay";
+ };
+ 
+-&usb_host0_xhci {
++&usb_host1_xhci {
+ 	status = "okay";
+ };
+ 
+-&usb_host1_xhci {
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ 	status = "okay";
+ };
+ 
+@@ -632,12 +846,68 @@
+ 	};
+ };
+ 
+-&vop {
+-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++&vop_mmu {
+ 	status = "okay";
+ };
+ 
+-&vop_mmu {
++&i2s1_8ch {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2s1m0_sclktx
++		     &i2s1m0_lrcktx
++		     &i2s1m0_sdi0
++		     &i2s1m0_sdo0>;
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
++&i2c1 {
++    status = "okay";
++};
++
++&i2c4 {
++	status = "okay";
++};
++
++&i2c5 {
++    status = "okay";
++};
++
++&gic {
++    status = "okay";
++};
++
++&uart3 {
++//	status = "disabled";
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&uart4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart4m1_xfer>;
++        status = "okay";
++};
++
++&uart8 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
++};
++
++&rk809 {
++    rtc {
++        status = "disabled";
++    };
++};
++
++&pwm4 {
++	status = "okay";
++};
++
++&pwm5 {
++	status = "okay";
++};
++
++&pwm7 {
+ 	status = "okay";
+ };
diff --git a/patch/kernel/archive/rockchip64-6.6/drivers-regulator-fan53555-bug-fixed.patch b/patch/kernel/archive/rockchip64-6.6/drivers-regulator-fan53555-bug-fixed.patch
new file mode 100644
index 000000000000..1f8803d04760
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.6/drivers-regulator-fan53555-bug-fixed.patch
@@ -0,0 +1,44 @@
+From b95c594a0969e469ef627c3e1724566dc5aa3016 Mon Sep 17 00:00:00 2001
+From: ARC-MX <wmx129674@126.com>
+Date: Thu, 25 Jul 2024 17:44:54 +0800
+Subject: [PATCH] drivers:regulator:fan53555:add new device chip id
+
+drivers:regulator:fan53555
+
+When I use fan53555, I see an error:
+
+ FAN53555-regulator 0-0060: Chip ID 0 with rev 12 not supported!
+
+So I fixed this bug
+
+Signed-off-by: ARC-MX <wmx129674@126.com>
+---
+ drivers/regulator/fan53555.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c
+index 17c9bf204..c8a2e9405 100644
+--- a/drivers/regulator/fan53555.c
++++ b/drivers/regulator/fan53555.c
+@@ -113,6 +113,7 @@ enum {
+ enum {
+ 	FAN53555_CHIP_REV_00 = 0x3,
+ 	FAN53555_CHIP_REV_13 = 0xf,
++	FAN53555_CHIP_REV_23 = 0xc,
+ };
+ 
+ enum {
+@@ -301,6 +302,10 @@ static int fan53555_voltages_setup_fairchild(struct fan53555_device_info *di)
+ 			di->vsel_min = 800000;
+ 			di->vsel_step = 10000;
+ 			break;
++		case FAN53555_CHIP_REV_23:
++			di->vsel_min = 600000;
++			di->vsel_step = 12500;
++			break;
+ 		default:
+ 			dev_err(di->dev,
+ 				"Chip ID %d with rev %d not supported!\n",
+-- 
+2.25.1
+
diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3328-heltec.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-heltec.dts
new file mode 100755
index 000000000000..1cb919d9adba
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-heltec.dts
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+	model = "Rockchip RK3328 Heltec";
+	compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdio;
+		mmc2 = &emmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0m1_pin>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+	status = "okay";
+};
+
+&gmac2phy {
+	phy-supply = <&vcc_phy>;
+	clock_in_out = "output";
+	assigned-clock-rate = <50000000>;
+	assigned-clocks = <&cru SCLK_MAC2PHY>;
+	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	rk805: pmic@18 {
+		compatible = "rockchip,rk805";
+		reg = <0x18>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk805-clkout2";
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc5-supply = <&vcc_io>;
+		vcc6-supply = <&vcc_io>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vdd_arm: DCDC_REG2 {
+				regulator-name = "vdd_arm";
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io: DCDC_REG4 {
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_18: LDO_REG1 {
+				regulator-name = "vcc_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc18_emmc: LDO_REG2 {
+				regulator-name = "vcc18_emmc";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_10: LDO_REG3 {
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+		rockchip,pins =
+			<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdio {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	max-frequency = <150000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+	vmmc-supply = <&vcc_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&u2phy {
+	status = "okay";
+};
+
+&u2phy_host {
+	status = "okay";
+};
+
+&u2phy_otg {
+	status = "okay";
+};
+
+&usb20_otg {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip64-6.6/pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch b/patch/kernel/archive/rockchip64-6.6/pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch
new file mode 100644
index 000000000000..bc751233a684
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.6/pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch
@@ -0,0 +1,13 @@
+diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
+index 3f56991f5b89..f6da91941fbd 100644
+--- a/drivers/pinctrl/pinctrl-rockchip.c
++++ b/drivers/pinctrl/pinctrl-rockchip.c
+@@ -3813,7 +3813,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
+ 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
+ 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
+ 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
+-			     0,
++			     IOMUX_WIDTH_2BIT,
+ 			     IOMUX_WIDTH_3BIT,
+ 			     0),
+ 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
diff --git a/patch/kernel/archive/rockchip64-6.9/drivers-regulator-fan53555-bug-fixed.patch b/patch/kernel/archive/rockchip64-6.9/drivers-regulator-fan53555-bug-fixed.patch
new file mode 100644
index 000000000000..1f8803d04760
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.9/drivers-regulator-fan53555-bug-fixed.patch
@@ -0,0 +1,44 @@
+From b95c594a0969e469ef627c3e1724566dc5aa3016 Mon Sep 17 00:00:00 2001
+From: ARC-MX <wmx129674@126.com>
+Date: Thu, 25 Jul 2024 17:44:54 +0800
+Subject: [PATCH] drivers:regulator:fan53555:add new device chip id
+
+drivers:regulator:fan53555
+
+When I use fan53555, I see an error:
+
+ FAN53555-regulator 0-0060: Chip ID 0 with rev 12 not supported!
+
+So I fixed this bug
+
+Signed-off-by: ARC-MX <wmx129674@126.com>
+---
+ drivers/regulator/fan53555.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c
+index 17c9bf204..c8a2e9405 100644
+--- a/drivers/regulator/fan53555.c
++++ b/drivers/regulator/fan53555.c
+@@ -113,6 +113,7 @@ enum {
+ enum {
+ 	FAN53555_CHIP_REV_00 = 0x3,
+ 	FAN53555_CHIP_REV_13 = 0xf,
++	FAN53555_CHIP_REV_23 = 0xc,
+ };
+ 
+ enum {
+@@ -301,6 +302,10 @@ static int fan53555_voltages_setup_fairchild(struct fan53555_device_info *di)
+ 			di->vsel_min = 800000;
+ 			di->vsel_step = 10000;
+ 			break;
++		case FAN53555_CHIP_REV_23:
++			di->vsel_min = 600000;
++			di->vsel_step = 12500;
++			break;
+ 		default:
+ 			dev_err(di->dev,
+ 				"Chip ID %d with rev %d not supported!\n",
+-- 
+2.25.1
+
diff --git a/patch/kernel/archive/rockchip64-6.9/dt/rk3328-heltec.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3328-heltec.dts
new file mode 100755
index 000000000000..1cb919d9adba
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.9/dt/rk3328-heltec.dts
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+	model = "Rockchip RK3328 Heltec";
+	compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdio;
+		mmc2 = &emmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0m1_pin>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+	status = "okay";
+};
+
+&gmac2phy {
+	phy-supply = <&vcc_phy>;
+	clock_in_out = "output";
+	assigned-clock-rate = <50000000>;
+	assigned-clocks = <&cru SCLK_MAC2PHY>;
+	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	rk805: pmic@18 {
+		compatible = "rockchip,rk805";
+		reg = <0x18>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk805-clkout2";
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc5-supply = <&vcc_io>;
+		vcc6-supply = <&vcc_io>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vdd_arm: DCDC_REG2 {
+				regulator-name = "vdd_arm";
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io: DCDC_REG4 {
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_18: LDO_REG1 {
+				regulator-name = "vcc_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc18_emmc: LDO_REG2 {
+				regulator-name = "vcc18_emmc";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_10: LDO_REG3 {
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+		rockchip,pins =
+			<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdio {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	max-frequency = <150000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+	vmmc-supply = <&vcc_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&u2phy {
+	status = "okay";
+};
+
+&u2phy_host {
+	status = "okay";
+};
+
+&u2phy_otg {
+	status = "okay";
+};
+
+&usb20_otg {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
diff --git a/patch/kernel/archive/rockchip64-6.9/pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch b/patch/kernel/archive/rockchip64-6.9/pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch
new file mode 100644
index 000000000000..bc751233a684
--- /dev/null
+++ b/patch/kernel/archive/rockchip64-6.9/pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch
@@ -0,0 +1,13 @@
+diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
+index 3f56991f5b89..f6da91941fbd 100644
+--- a/drivers/pinctrl/pinctrl-rockchip.c
++++ b/drivers/pinctrl/pinctrl-rockchip.c
+@@ -3813,7 +3813,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
+ 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
+ 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
+ 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
+-			     0,
++			     IOMUX_WIDTH_2BIT,
+ 			     IOMUX_WIDTH_3BIT,
+ 			     0),
+ 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
diff --git a/patch/kernel/archive/sunxi-6.10/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch b/patch/kernel/archive/sunxi-6.10/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch
new file mode 100644
index 000000000000..fd0ed1d2c251
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch
@@ -0,0 +1,63 @@
+From d0f6b8b0000847160766e3b9df8a8c2b61d543d0 Mon Sep 17 00:00:00 2001
+From: Mikhail Iakhiaev <mikhailai@gmail.com>
+Date: Mon, 29 Jul 2024 09:50:36 -0700
+Subject: arm/patch: call flush_icache ASAP after writing new instruction.
+
+The patch moves flush_icache before the patch_unmap call.
+The change avoids the possibility of the CPU seeing
+partially-patched instructions if a function from patch_unmap
+call tree has just been patched. That HAS been observed
+in practice, leading to kernel panic or freezing in early boot:
+https://bugzilla.kernel.org/show_bug.cgi?id=219089
+Specifically, the patch_unmap invokes _raw_spin_unlock_irqrestore
+(could be non-inlined) and that function is being patched
+during the ftrace_init, so the original code would run the
+patched code BEFORE flushing the icache.
+
+Note, some arches are more careful about flushing icache early. E.g.
+arch/riscv/kernel/patch.c:
+  __patch_insn_set and __patch_insn_write call the
+  local_flush_icache_range before the patch_unmap and have an
+  explicit comment about this.
+arch/x86/kernel/alternative.c:
+  text_poke_early calls sync_core (flushes icache) before
+  local_irq_restore.
+
+Closes: https://bugzilla.kernel.org/show_bug.cgi?id=219089
+Signed-off-by: Mikhail Iakhiaev <mikhailai@gmail.com>
+
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ arch/arm/kernel/patch.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/kernel/patch.c b/arch/arm/kernel/patch.c
+index e9e828b6bb30..f003867f085a 100644
+--- a/arch/arm/kernel/patch.c
++++ b/arch/arm/kernel/patch.c
+@@ -99,13 +99,19 @@ void __kprobes __patch_text_real(void *addr, unsigned int insn, bool remap)
+ 		size = sizeof(u32);
+ 	}
+ 
+-	if (waddr != addr) {
++	if (waddr != addr)
+ 		flush_kernel_vmap_range(waddr, twopage ? size / 2 : size);
+-		patch_unmap(FIX_TEXT_POKE0, &flags);
+-	}
+ 
+ 	flush_icache_range((uintptr_t)(addr),
+ 			   (uintptr_t)(addr) + size);
++
++	/* Can only call 'patch_unmap' after flushing dcache and icache,
++	 * because it calls 'raw_spin_unlock_irqrestore', but that may
++	 * happen to be the very function we're currently patching
++	 * (as it happens during the ftrace init).
++	 */
++	if (waddr != addr)
++		patch_unmap(FIX_TEXT_POKE0, &flags);
+ }
+ 
+ static int __kprobes patch_text_stop_machine(void *data)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-axp813-Add-charger-LED.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-axp813-Add-charger-LED.patch
new file mode 100644
index 000000000000..ed6a9fce3c1e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-axp813-Add-charger-LED.patch
@@ -0,0 +1,30 @@
+From 022825af6d7cd605691a71d320c3176153adeb08 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 14 Nov 2017 02:47:51 +0100
+Subject: ARM: dts: axp813: Add charger LED
+
+PMIC supports charging status indication via a LED. Add support
+for it.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/axp81x.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/axp81x.dtsi b/arch/arm/boot/dts/allwinner/axp81x.dtsi
+index ebaf1c3ce8db..a4b1be159b02 100644
+--- a/arch/arm/boot/dts/allwinner/axp81x.dtsi
++++ b/arch/arm/boot/dts/allwinner/axp81x.dtsi
+@@ -161,4 +161,9 @@ reg_drivevbus: drivevbus {
+ 	usb_power_supply: usb-power {
+ 		compatible = "x-powers,axp813-usb-power-supply";
+ 	};
++
++	charger_led: charger-led {
++		compatible = "x-powers,axp813-charger-led";
++		status = "disabled";
++	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch
new file mode 100644
index 000000000000..2053a8865982
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch
@@ -0,0 +1,185 @@
+From 8bc6a1bfb39350a2ea451c6108e92a79b1eec29b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 01:23:10 +0100
+Subject: ARM: dts: sun5i: Add PocketBook Touch Lux 3 display/ctp support
+
+Add support for display and touchscreen via out-of-tree drivers.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../sun5i-a13-pocketbook-touch-lux-3.dts      | 105 +++++++++++++++++-
+ 1 file changed, 103 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
+index d60407772e5d..db28ab621804 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
++++ b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
+@@ -62,6 +62,11 @@ key-left {
+ 		};
+ 	};
+ 
++	regulator-eink {
++		compatible = "custom,reg-userspace-consumer";
++		controlled-supply = <&tp65185x>;
++	};
++
+ 	reg_1v8: regulator-1v8 {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vdd-1v8-nor-ctp";
+@@ -79,7 +84,6 @@ reg_1v8_nor: regulator-nor {
+ 		gpio = <&pio 2 14 GPIO_ACTIVE_HIGH>;
+ 		enable-active-high;
+ 		vin-supply = <&reg_1v8>;
+-		regulator-always-on;
+ 	};
+ 
+ 	reg_1v8_ctp: regulator-ctp {
+@@ -112,6 +116,7 @@ &ehci0 {
+ 
+ &i2c0 {
+ 	status = "okay";
++	//XXX: bsp has pullup on PB0/PB1 pins enabled, but it works without it
+ 
+ 	axp209: pmic@34 {
+ 		reg = <0x34>;
+@@ -128,12 +133,42 @@ pcf8563: rtc@51 {
+ 		compatible = "nxp,pcf8563";
+ 		reg = <0x51>;
+ 	};
++
++	// hacky PMIC driver for eInk display
++	tp65185x: regulator@68 {
++		compatible = "tp,tp65185x";
++		reg = <0x68>;
++
++		regulator-min-microvolt = <3120000>;
++		regulator-max-microvolt = <3120000>;
++		regulator-name = "eink-vcom";
++
++		//XXX: we don't use interrupts in the driver right now
++		//interrupt-parent = <&pio>;
++		//interrupts = <1 10 IRQ_TYPE_LEVEL_LOW>; /* PB10 */
++
++		wakeup-gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
++		powerup-gpios = <&pio 4 7 GPIO_ACTIVE_HIGH>; /* PE7 */
++		vcom-gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
++		//XXX: not a pullup on BSP (might have an external resistor)
++		powergood-gpios = <&pio 4 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PE6 */
++	};
+ };
+ 
+ &i2c2 {
+ 	status = "okay";
+ 
+-	/* Touchpanel is connected here. */
++	touchpanel@24 {
++		compatible = "cypress,cyttsp4_i2c_adapter";
++		reg = <0x24>;
++
++		interrupt-parent = <&pio>;
++		interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* PG11 */
++
++		vdd-supply = <&reg_1v8_ctp>;
++		power-gpios = <&pio 4 5 GPIO_ACTIVE_LOW>; /* PE5 */
++		reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */
++	};
+ };
+ 
+ &lradc {
+@@ -179,6 +214,20 @@ &otg_sram {
+ 	status = "okay";
+ };
+ 
++&pio {
++	eink_pins_active: eink-pins-lcd {
++		pins = "PD3", "PD4", "PD5", "PD6", "PD7", "PD10", "PD11", "PD12",
++			"PD13", "PD15", "PD20", "PD21", "PD22", "PD23", "PD24";
++		function = "lcd0";
++	};
++
++	eink_pins_idle: eink-pins-gpio {
++		pins = "PD3", "PD4", "PD5", "PD6", "PD7", "PD10", "PD11", "PD12",
++			"PD13", "PD15", "PD20", "PD21", "PD22", "PD23", "PD24";
++		function = "gpio_out";
++	};
++};
++
+ &pwm {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pwm0_pin>;
+@@ -219,6 +268,55 @@ &reg_ldo3 {
+ 	regulator-ramp-delay = <1600>;
+ };
+ 
++&soc {
++	display-controller@1c0c000 {
++		pinctrl-names = "idle", "active";
++		pinctrl-0 = <&eink_pins_idle>;
++		pinctrl-1 = <&eink_pins_active>;
++
++		all-gpios = <&pio 3 3 GPIO_ACTIVE_HIGH>,
++			<&pio 3 4 GPIO_ACTIVE_HIGH>,
++			<&pio 3 5 GPIO_ACTIVE_HIGH>,
++			<&pio 3 6 GPIO_ACTIVE_HIGH>,
++			<&pio 3 7 GPIO_ACTIVE_HIGH>,
++			<&pio 3 10 GPIO_ACTIVE_HIGH>,
++			<&pio 3 11 GPIO_ACTIVE_HIGH>,
++			<&pio 3 12 GPIO_ACTIVE_HIGH>,
++			<&pio 3 13 GPIO_ACTIVE_HIGH>,
++			<&pio 3 15 GPIO_ACTIVE_HIGH>,
++			<&pio 3 20 GPIO_ACTIVE_HIGH>,
++			<&pio 3 21 GPIO_ACTIVE_HIGH>,
++			<&pio 3 22 GPIO_ACTIVE_HIGH>,
++			<&pio 3 23 GPIO_ACTIVE_HIGH>,
++			<&pio 3 24 GPIO_ACTIVE_HIGH>;
++
++		compatible = "custom,pocketbook-touch-lux-3-tcon0-ed060xd4-display";
++		reg = <0x01c0c000 0x1000>, // TCON0 regs
++			<0x01e60000 0x10000>; // DEBE regs
++
++		interrupts = <44>; // TCON interrupt
++
++		resets = <&ccu RST_LCD>, <&ccu RST_DE_BE>;
++		reset-names = "tcon", "be";
++
++		clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_TCON_CH0>,
++			 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
++			 <&ccu CLK_DRAM_DE_BE>;
++		clock-names = "tcon_bus", "tcon_mod",
++			      "be_bus", "be_mod",
++			      "be_ram";
++
++		assigned-clocks = <&ccu CLK_DE_BE>;
++		assigned-clock-rates = <300000000>;
++
++		interconnects = <&mbus 18>;
++		interconnect-names = "dma-mem";
++
++		panel-supply = <&tp65185x>;
++		control-device-name = "eink-panel";
++	};
++};
++
+ &spi2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>;
+@@ -230,6 +328,7 @@ epd_flash: flash@0 {
+ 		compatible = "macronix,mx25u4033", "jedec,spi-nor";
+ 		reg = <0>;
+ 		spi-max-frequency = <4000000>;
++		vdd-supply = <&reg_1v8_nor>;
+ 	};
+ };
+ 
+@@ -253,6 +352,8 @@ &usb_power_supply {
+ };
+ 
+ &usbphy {
++	//XXX: might not work, need to test
++	usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ 	usb1_vbus-supply = <&reg_ldo3>;
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch
new file mode 100644
index 000000000000..3d4dedbb3da2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch
@@ -0,0 +1,26 @@
+From 54fcdf77e056758e20cff5f7e23f45bf1eff80cf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 5 Oct 2019 15:04:43 +0200
+Subject: ARM: dts: sun5i: Add soc handle
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun5i.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i.dtsi b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+index e6836fd4b8dc..126b80f3ca70 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+@@ -123,7 +123,7 @@ default-pool {
+ 		};
+ 	};
+ 
+-	soc {
++	soc: soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch
new file mode 100644
index 000000000000..744b3d36a2a7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch
@@ -0,0 +1,27 @@
+From ebf6714ed4c060fc42d78b0945d4b13b785e80f7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 25 Jun 2020 01:57:27 +0200
+Subject: ARM: dts: sun5i-a13-pocketbook-touch-lux-3: Add RTC clock-cells
+
+This stop the driver from complaining in dmesg.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
+index db28ab621804..ee81db68e546 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
++++ b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
+@@ -132,6 +132,7 @@ &i2c1 {
+ 	pcf8563: rtc@51 {
+ 		compatible = "nxp,pcf8563";
+ 		reg = <0x51>;
++		#clock-cells = <0>;
+ 	};
+ 
+ 	// hacky PMIC driver for eInk display
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
new file mode 100644
index 000000000000..7baca8e7c5b1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
@@ -0,0 +1,39 @@
+From 2a7ede988f5cd049f6d5bda08c53e600b1c5acbf Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 3 Apr 2021 20:53:26 -0500
+Subject: ARM: dts: sun8i: a83t: Add MBUS node
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index ef62ced26684..04b33b42b414 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -1056,6 +1056,21 @@ mdio: mdio {
+ 			};
+ 		};
+ 
++		mbus: dram-controller@1c62000 {
++			compatible = "allwinner,sun8i-a83t-mbus";
++			reg = <0x01c62000 0x1000>,
++			      <0x01c63000 0x1000>;
++			reg-names = "mbus", "dram";
++			clocks = <&ccu CLK_BUS_DRAM>,
++				 <&ccu CLK_DRAM>,
++				 <&ccu CLK_MBUS>;
++			clock-names = "apb", "dram", "mbus";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
++			#interconnect-cells = <1>;
++		};
++
+ 		gic: interrupt-controller@1c81000 {
+ 			compatible = "arm,gic-400";
+ 			reg = <0x01c81000 0x1000>,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
new file mode 100644
index 000000000000..041ac6934e7a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
@@ -0,0 +1,37 @@
+From 77eed4b2f47883d2330f10bb19c6a5c11987497c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 9 Sep 2019 06:02:10 +0200
+Subject: ARM: dts: sun8i-a83t: Add cedrus video codec support to A83T
+ [untested]
+
+Not tested at all.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index addf0cb0f465..ed3d8e692d84 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -441,6 +441,16 @@ syscon: syscon@1c00000 {
+ 			reg = <0x01c00000 0x1000>;
+ 		};
+ 
++		video-codec@01c0e000 {
++			compatible = "allwinner,sun8i-a83t-video-engine";
++			reg = <0x01c0e000 0x1000>;
++			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
++				 <&ccu CLK_DRAM_VE>;
++			clock-names = "ahb", "mod", "ram";
++			resets = <&ccu RST_BUS_VE>;
++			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
+ 		dma: dma-controller@1c02000 {
+ 			compatible = "allwinner,sun8i-a83t-dma";
+ 			reg = <0x01c02000 0x1000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..de12fad6e359
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From 45c38d0b6350c244ba1d3ddfc589fcf87200d0e6 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:32:57 +0200
+Subject: ARM: dts: sun8i: a83t: Add hdmi sound card
+
+A83t support HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 026c9b1b2217..cc86d3755036 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -150,6 +150,20 @@ cpu103: cpu@103 {
+ 		};
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun8i-a83t-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv7-timer";
+ 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+@@ -1059,6 +1073,7 @@ csi: camera@1cb0000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+ 			reg-io-width = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
new file mode 100644
index 000000000000..a86015263b18
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
@@ -0,0 +1,35 @@
+From 7439414f92df1ca313b6d96fc1b5aab946977433 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 13 Mar 2023 06:02:27 +0100
+Subject: ARM: dts: sun8i-a83t: Add missing GPU trip point
+
+Without this, thermal sensor driver fails to probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 660a2e29bc68..7a5dc8a18906 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -1309,6 +1309,15 @@ gpu_thermal: gpu-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 2>;
++
++			trips {
++				gpu_crit: gpu-crit {
++					/* milliCelsius */
++					temperature = <100000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
+ 		};
+ 	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
new file mode 100644
index 000000000000..300962b97731
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
@@ -0,0 +1,69 @@
+From 4afe0b795a351420113f1f0dd2ab13aa15d5c8d9 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:34:43 +0200
+Subject: ARM: dts: sun8i: a83t: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all A83t boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts    | 8 ++++++++
+ .../arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts | 8 ++++++++
+ 2 files changed, 16 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts
+index 32e811fa23e2..9a7117bca70d 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts
+@@ -162,6 +162,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -380,6 +384,10 @@ &reg_sw {
+ 	regulator-name = "vcc-ephy";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts
+index d5e6ddaffbce..d4d834084b12 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts
+@@ -197,6 +197,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -417,6 +421,10 @@ &reg_sw {
+ 	regulator-name = "vcc-wifi-io";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spdif {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
new file mode 100644
index 000000000000..efb71b039609
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
@@ -0,0 +1,134 @@
+From 0806fda6ae3778bca7b3e09e21f31940bcd9ca98 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 1 Sep 2019 23:56:49 +0200
+Subject: ARM: dts: sun8i-a83t: Improve CPU OPP tables (go up to 1.8GHz)
+
+This table is for the worst SoC bin, so it should work on all A83T
+bins.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 80 ++++++---------------
+ 1 file changed, 22 insertions(+), 58 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 04b33b42b414..026c9b1b2217 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -210,45 +210,27 @@ opp-480000000 {
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-600000000 {
+-			opp-hz = /bits/ 64 <600000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-720000000 {
+-			opp-hz = /bits/ 64 <720000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-864000000 {
+-			opp-hz = /bits/ 64 <864000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-912000000 {
+-			opp-hz = /bits/ 64 <912000000>;
++		opp-1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1008000000 {
+-			opp-hz = /bits/ 64 <1008000000>;
+-			opp-microvolt = <840000>;
++		opp-1412000000 {
++			opp-hz = /bits/ 64 <1412000000>;
++			opp-microvolt = <920000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1128000000 {
+-			opp-hz = /bits/ 64 <1128000000>;
+-			opp-microvolt = <840000>;
++		opp-1608000000 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <1000000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1200000000 {
+-			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <840000>;
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1080000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 	};
+@@ -263,45 +245,27 @@ opp-480000000 {
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-600000000 {
+-			opp-hz = /bits/ 64 <600000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-720000000 {
+-			opp-hz = /bits/ 64 <720000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-864000000 {
+-			opp-hz = /bits/ 64 <864000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-912000000 {
+-			opp-hz = /bits/ 64 <912000000>;
++		opp-1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1008000000 {
+-			opp-hz = /bits/ 64 <1008000000>;
+-			opp-microvolt = <840000>;
++		opp-1412000000 {
++			opp-hz = /bits/ 64 <1412000000>;
++			opp-microvolt = <920000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1128000000 {
+-			opp-hz = /bits/ 64 <1128000000>;
+-			opp-microvolt = <840000>;
++		opp-1608000000 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <1000000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1200000000 {
+-			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <840000>;
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1080000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
new file mode 100644
index 000000000000..e687e7139e49
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
@@ -0,0 +1,59 @@
+From 87a1df65d1aa8d9f01ac8b18f62525aee4049a3f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 1 Feb 2020 23:41:47 +0100
+Subject: ARM: dts: sun8i-a83t: Set fifo-size for uarts
+
+Boot time optimization.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index cc86d3755036..0bbf43850c95 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -926,6 +926,7 @@ uart0: serial@1c28000 {
+ 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART0>;
+ 			resets = <&ccu RST_BUS_UART0>;
+ 			status = "disabled";
+@@ -937,6 +938,7 @@ uart1: serial@1c28400 {
+ 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART1>;
+ 			resets = <&ccu RST_BUS_UART1>;
+ 			status = "disabled";
+@@ -948,6 +950,7 @@ uart2: serial@1c28800 {
+ 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART2>;
+ 			resets = <&ccu RST_BUS_UART2>;
+ 			status = "disabled";
+@@ -959,6 +962,7 @@ uart3: serial@1c28c00 {
+ 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART3>;
+ 			resets = <&ccu RST_BUS_UART3>;
+ 			status = "disabled";
+@@ -970,6 +974,7 @@ uart4: serial@1c29000 {
+ 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART4>;
+ 			resets = <&ccu RST_BUS_UART4>;
+ 			status = "disabled";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
new file mode 100644
index 000000000000..627587cf372b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
@@ -0,0 +1,66 @@
+From 1acac9e981b42164fe68442fe206a1d7ced96be5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 10 Nov 2017 14:33:28 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add PN544 NFC support
+
+Regulators on the schematic are named incorrectly. Both cameras are
+is in fact connected to the dvdd-csi-f regulator and dvdd-csi-r is
+in reality used for digital pad supply for NFC chip.
+
+At the same time vcc-mipi regulator is not used for MIPI, but for NFC
+VBAT power.
+
+Interpreting schematics is an art form! :D
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 43982b106a4d..5cedbe2455db 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -190,6 +190,16 @@ accelerometer@18 {
+ 		interrupt-parent = <&pio>;
+ 		interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
+ 	};
++
++	/* NFC (NPC 100) */
++	npc100: nfc@28 {
++		compatible = "nxp,nxp-nci-i2c";
++		reg = <0x28>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; /* PL6 */
++		enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
++		firmware-gpios = <&pio 3 3 GPIO_ACTIVE_HIGH>; /* PD3 */
++	};
+ };
+ 
+ &mmc0 {
+@@ -368,9 +378,10 @@ &reg_dldo1 {
+ };
+ 
+ &reg_dldo2 {
+-	regulator-min-microvolt = <2800000>;
++	regulator-min-microvolt = <3300000>;
+ 	regulator-max-microvolt = <4200000>;
+-	regulator-name = "vcc-mipi";
++	regulator-name = "vbat-nfc";
++	regulator-always-on;
+ };
+ 
+ &reg_dldo3 {
+@@ -393,7 +404,8 @@ &reg_drivevbus {
+ &reg_eldo1 {
+ 	regulator-min-microvolt = <1200000>;
+ 	regulator-max-microvolt = <1800000>;
+-	regulator-name = "dvdd-csi-r";
++	regulator-name = "pvdd-nfc";
++	regulator-always-on;
+ };
+ 
+ &reg_eldo2 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
new file mode 100644
index 000000000000..8a7c07f8b82d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
@@ -0,0 +1,180 @@
+From 275f7a22d3eed955503f03b2e56967a30f9b22af Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:43:24 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add camera sensors (HM5065, GC2145)
+
+The tablet has two cameras, that can be switched between. Add
+support for the both of them.
+
+Sensor is connected via parallel bus to CSI and via I2C bus to
+PE14/PE15 pins. Enable CSI module and add the node for HM5065
+camera sensor.
+
+Camera sensors are connected via I2C to PE14/PE15 pins on A83T.
+Unfortunately while the A83T datasheet suggests TWI2 I2C controller
+can be configured to have SDA/SCL on these pins, this configuration
+doesn't work in reality. We need to either use CCI I2C controller
+that is part of the CSI module, or as is done in this patch, use GPIO
+based bitbanging I2C driver.
+
+Reduce camera IOVDD voltage.
+
+Force dvdd-csi-r/f regulators to 1.8V.
+
+This is required by camera sensors that are connected to them.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun8i-a83t-tbs-a711.dts     | 101 +++++++++++++++++-
+ 1 file changed, 99 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index ce1a8d98b548..ba3ea3199c69 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -70,6 +70,16 @@ backlight: backlight {
+ 		default-brightness-level = <9>;
+ 	};
+ 
++	i2c_gpio: i2c-gpio {
++		compatible = "i2c-gpio";
++		/* PE15 = sda, PE14 = scl */
++		sda-gpios = <&pio 4 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&pio 4 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <1>; /* ~100 kHz */
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
+ 	panel {
+ 		compatible = "tbs,a711-panel", "panel-lvds";
+ 		backlight = <&backlight>;
+@@ -215,6 +225,13 @@ link2_codec: codec {
+ 	};
+ };
+ 
++&ccu {
++	/* Use a stable clock source with known fixed rate for MCLK */
++	assigned-clocks = <&ccu CLK_CSI_MCLK>;
++	assigned-clock-parents = <&osc24M>;
++	assigned-clock-rates = <24000000>;
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdc2>;
+ };
+@@ -223,6 +240,37 @@ &cpu100 {
+ 	cpu-supply = <&reg_dcdc3>;
+ };
+ 
++&csi {
++	pinctrl-names = "default";
++	pinctrl-0 = <&csi_8bit_parallel_pins>, <&csi_mclk_pin>;
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi_hm5065_ep: endpoint@0 {
++			reg = <0>;
++			remote-endpoint = <&hm5065_ep>;
++			bus-width = <8>;
++			data-active = <1>;
++			pclk-sample = <0>;
++			hsync-active = <0>;
++			vsync-active = <1>;
++		};
++
++		csi_gc2145_ep: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&gc2145_ep>;
++			bus-width = <8>;
++			hsync-active = <1>;
++			vsync-active = <1>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		};
++	};
++};
++
+ &de {
+ 	status = "okay";
+ };
+@@ -283,6 +331,55 @@ npc100: nfc@28 {
+ 	};
+ };
+ 
++&i2c_gpio {
++	hm5065: rear-camera@1f {
++		compatible = "himax,hm5065";
++		reg = <0x1f>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		AFVDD-supply = <&reg_dldo3>;
++		reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
++		enable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
++
++		port {
++			hm5065_ep: endpoint {
++				remote-endpoint = <&csi_hm5065_ep>;
++				bus-width = <8>;
++				data-active = <1>;
++				pclk-sample = <0>;
++				hsync-active = <0>;
++				vsync-active = <1>;
++			};
++		};
++	};
++
++	gc2145: front-camera@3c {
++		compatible = "galaxycore,gc2145";
++		reg = <0x3c>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
++		enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
++
++		port {
++			gc2145_ep: endpoint {
++				remote-endpoint = <&csi_gc2145_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++};
++
+ &i2s0 {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+@@ -500,7 +597,7 @@ &reg_drivevbus {
+ };
+ 
+ &reg_eldo1 {
+-	regulator-min-microvolt = <1200000>;
++	regulator-min-microvolt = <1800000>;
+ 	regulator-max-microvolt = <1800000>;
+ 	regulator-name = "pvdd-nfc";
+ 	regulator-always-on;
+@@ -513,7 +610,7 @@ &reg_eldo2 {
+ };
+ 
+ &reg_eldo3 {
+-	regulator-min-microvolt = <1200000>;
++	regulator-min-microvolt = <1800000>;
+ 	regulator-max-microvolt = <1800000>;
+ 	regulator-name = "dvdd-csi-f";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
new file mode 100644
index 000000000000..72ac9be237de
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
@@ -0,0 +1,32 @@
+From 340e96224abb9dca4a98ce0d39f2ec7bd9f42b82 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Nov 2017 21:57:45 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add flash led support
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index ba3ea3199c69..23eb11e99b98 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -61,6 +61,15 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	leds {
++		compatible = "gpio-leds";
++
++		flash_led {
++			label = "flash";
++			gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
+ 	backlight: backlight {
+ 		compatible = "pwm-backlight";
+ 		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
new file mode 100644
index 000000000000..d6726ecb8ce2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
@@ -0,0 +1,61 @@
+From ab94581cd06d39c23734852b86d8a7536ebcfcfe Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?=
+ <mylene.josserand@free-electrons.com>
+Date: Thu, 6 Jul 2017 10:57:55 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add powerup/down support for the 3G
+ modem
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The modem needs tree gpios to be powered-up:
+	- PL10 = reset
+	- PL8 = On/Off
+	- PL9 = vbat
+Because of that, the PL9 corresponds to the regulator's gpio whereas
+the PL8 (on/off) will be a power-gpio of the power sequence.
+
+Thanks to that, the modem is powered up:
+       # lsusb
+	Bus 001 Device 004: ID 19d2:ffeb
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 5cedbe2455db..f7d8e5425233 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -118,7 +118,7 @@ reg_vmain: reg-vmain {
+ 		regulator-name = "vmain";
+ 		regulator-min-microvolt = <5000000>;
+ 		regulator-max-microvolt = <5000000>;
+-		gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;
++		gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ 		enable-active-high;
+ 		vin-supply = <&reg_vbat>;
+ 	};
+@@ -134,6 +134,17 @@ wifi_pwrseq: pwrseq {
+ 		clocks = <&ac100_rtc 1>;
+ 		clock-names = "ext_clock";
+ 	};
++
++	modem {
++		compatible = "zte,mg3732";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vmain>;
++
++		enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++		reset-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
++		wakeup-gpios = <&r_pio 0 11 GPIO_ACTIVE_HIGH>; /* PL11 */
++	};
+ };
+ 
+ &cpu0 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
new file mode 100644
index 000000000000..470c4ab491e5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
@@ -0,0 +1,30 @@
+From 63111b65ae2f191f0f69578da5ec3cf4c460f569 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:15:37 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add regulators to the accelerometer
+
+The bosch,bma250 driver will fail to probe if the regulators are
+not specified in DT, because it tries to set voltage on dummy
+regulators, which fails with EINVAL.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 925891a1d6d9..ce1a8d98b548 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -268,6 +268,8 @@ accelerometer@18 {
+ 		reg = <0x18>;
+ 		interrupt-parent = <&pio>;
+ 		interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
++		vdd-supply = <&reg_dcdc1>;
++		vddio-supply = <&reg_dcdc1>;
+ 	};
+ 
+ 	/* NFC (NPC 100) */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
new file mode 100644
index 000000000000..3c0c1cb8f61f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
@@ -0,0 +1,131 @@
+From 8318600d3dd6b179ef3d157b8d6d525affcf40ce Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 22 Feb 2020 23:40:29 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add sound support via AC100 codec
+
+...
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun8i-a83t-tbs-a711.dts     | 85 +++++++++++++++++++
+ 1 file changed, 85 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index f7d8e5425233..925891a1d6d9 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -145,6 +145,74 @@ modem {
+ 		reset-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ 		wakeup-gpios = <&r_pio 0 11 GPIO_ACTIVE_HIGH>; /* PL11 */
+ 	};
++
++	bt_sco_codec: bt-sco-codec {
++		#sound-dai-cells = <1>;
++		compatible = "linux,bt-sco";
++		sound-name-prefix = "Bluetooth";
++	};
++
++	speaker_amp: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++		sound-name-prefix = "Speaker Amp";
++	};
++
++	sound: sound {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "ac100-audio";
++		simple-audio-card,aux-devs = <&ac100_codec_analog>, <&speaker_amp>;
++		simple-audio-card,widgets = "Microphone", "Headset Microphone",
++					    "Microphone", "Internal Microphone",
++					    "Headphone", "Headphone Jack",
++					    "Speaker", "Internal Speaker";
++		simple-audio-card,routing =
++				"Headphone Jack", "HP",
++				"Internal Speaker", "Speaker Amp OUTL",
++				"Speaker Amp INL", "SPKOUTL",
++				"Left DAC", "DACL",
++				"Right DAC", "DACR",
++				"ADCL", "Left ADC",
++				"ADCR", "Right ADC",
++				"Internal Microphone", "MBIAS",
++				"MIC1", "Internal Microphone",
++				"Headset Microphone", "HBIAS",
++				"MIC2", "Headset Microphone";
++
++		simple-audio-card,dai-link@0 {
++			format = "i2s";
++			frame-master = <&link0_cpu>;
++			bitclock-master = <&link0_cpu>;
++			mclk-fs = <512>;
++
++			link0_cpu: cpu {
++				sound-dai = <&i2s0>;
++			};
++
++			link0_codec: codec {
++				sound-dai = <&ac100_codec 0>;
++			};
++		};
++
++		simple-audio-card,dai-link@2 {
++			format = "dsp_a";
++			frame-master = <&link2_codec>;
++			bitclock-master = <&link2_codec>;
++			bitclock-inversion;
++
++			link2_cpu: cpu {
++				sound-dai = <&bt_sco_codec 0>;
++			};
++
++			link2_codec: codec {
++				sound-dai = <&ac100_codec 2>;
++				dai-tdm-slot-num = <2>;
++				dai-tdm-slot-width = <16>;
++			};
++		};
++	};
+ };
+ 
+ &cpu0 {
+@@ -213,6 +281,12 @@ npc100: nfc@28 {
+ 	};
+ };
+ 
++&i2s0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2s0_pins>;
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdc1>;
+ 	pinctrl-names = "default";
+@@ -293,12 +367,23 @@ ac100: codec@e89 {
+ 		compatible = "x-powers,ac100";
+ 		reg = <0xe89>;
+ 
++		ac100_codec_analog: codec-analog {
++			compatible = "x-powers,ac100-codec-analog";
++			cpvdd-supply = <&reg_aldo2>;
++		};
++
+ 		ac100_codec: codec {
++			#sound-dai-cells = <1>;
+ 			compatible = "x-powers,ac100-codec";
+ 			interrupt-parent = <&r_pio>;
+ 			interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */
+ 			#clock-cells = <0>;
+ 			clock-output-names = "4M_adda";
++
++			LDOIN-supply = <&reg_aldo2>;
++			AVCC-supply = <&reg_aldo3>;
++			VDDIO1-supply = <&reg_dcdc1>;
++			VDDIO2-supply = <&reg_dldo1>;
+ 		};
+ 
+ 		ac100_rtc: rtc {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
new file mode 100644
index 000000000000..d8e72b3910cd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
@@ -0,0 +1,39 @@
+From 58d2e468a9b4042575fd208fe7e9392fc53b7b14 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 9 Nov 2019 23:55:48 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add support for the vibrator motor
+
+The board has a vibrator mottor. Hook it to the input subsystem.
+
+According to the PMIC specification, LDO needs to be enabled (value 0b11)
+to achieve the specified max driving current of 150mA. We can't drive
+the motor with just GPIO mode.
+
+In GPIO mode the chip is probably just using the regular CMOS logic
+output circuitry (typically limited to around 20-35mA, but not specified
+in this datasheet).
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 23eb11e99b98..81e1271482ed 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -118,6 +118,11 @@ panel_input: endpoint {
+ 		};
+ 	};
+ 
++	vibrator {
++		compatible = "gpio-vibrator";
++		vcc-supply = <&reg_ldo_io1>;
++	};
++
+ 	reg_gps: reg-gps {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "gps";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
new file mode 100644
index 000000000000..4085bb7f555d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
@@ -0,0 +1,31 @@
+From cd7f3c1c64eb26582e22d48a8894d035b5bae590 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 13:21:58 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Enable charging LED
+
+The tablet has a LED connected to the PMIC. The LED is visible in the
+top right corner of the tablet. Enable it.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 6a90763d8736..6edeaf8ed431 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -519,6 +519,10 @@ &battery_power_supply {
+ 	status = "okay";
+ };
+ 
++&charger_led {
++	status = "okay";
++};
++
+ &reg_aldo1 {
+ 	regulator-min-microvolt = <1800000>;
+ 	regulator-max-microvolt = <1800000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
new file mode 100644
index 000000000000..a823e835f5dd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
@@ -0,0 +1,47 @@
+From 0fa9d7ec82f52d1864a326736cb0131ccebc4b09 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:19:46 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Give Linux more privileges over SCPI
+
+This is needed since on A83T there's no PSCI/ATF implementation.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index b95da4c64dee..660a2e29bc68 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -286,7 +286,7 @@ opp-1800000000 {
+ 
+ 	scpi_protocol: scpi {
+ 		compatible = "arm,scpi";
+-		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mboxes = <&msgbox 0>, <&msgbox 1>;
+ 		mbox-names = "tx", "rx";
+ 		shmem = <&scpi_sram>;
+ 	};
+@@ -424,6 +424,9 @@ syscon: syscon@1c00000 {
+ 			compatible = "allwinner,sun8i-a83t-system-controller",
+ 				"syscon";
+ 			reg = <0x01c00000 0x1000>;
++                        #address-cells = <1>;
++                        #size-cells = <1>;
++                        ranges;
+ 
+ 			sram_a2: sram@40000 {
+ 				compatible = "mmio-sram";
+@@ -434,7 +437,7 @@ sram_a2: sram@40000 {
+ 
+ 				scpi_sram: scp-shmem@13c00 {
+ 					compatible = "arm,scp-shmem";
+-					reg = <0x13c00 0x200>;
++					reg = <0x13e00 0x200>;
+ 				};
+ 			};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
new file mode 100644
index 000000000000..afba321cd4da
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
@@ -0,0 +1,30 @@
+From 06e61366eff03663a4a268c69da72b0fa621a1a4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 8 Dec 2017 12:44:22 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Increase voltage on the vibrator
+
+Vibrator motor is weak at the current voltage. Increase the voltage.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 81e1271482ed..6a90763d8736 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -650,8 +650,8 @@ &reg_ldo_io0 {
+ };
+ 
+ &reg_ldo_io1 {
+-	regulator-min-microvolt = <3100000>;
+-	regulator-max-microvolt = <3100000>;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
+ 	regulator-name = "vcc-vb";
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
new file mode 100644
index 000000000000..cfa73fd561c5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
@@ -0,0 +1,42 @@
+From e0e6e33b3d6ab8201236e1e59d3674fead016c4f Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:14:51 +0200
+Subject: ARM: dts: sun8i: h2-plus: bananapi-m2-zero: Enable HDMI audio
+
+BananaPi M2 Zero has HDMI output and thus supports HDMI audio. Enable
+it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts
+index d3a7c9fa23e4..f40c2d0483b5 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts
+@@ -133,6 +133,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -256,6 +260,10 @@ &r_pio {
+ 		"", "", "", "", "", "", "", "";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &usb_otg {
+ 	dr_mode = "otg";
+ 	status = "okay";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
new file mode 100644
index 000000000000..cb92104e0f50
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
@@ -0,0 +1,272 @@
+From 58d59b976e2e34c1ff2eb74629f4c6e324b05425 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:06:37 +0200
+Subject: ARM: dts: sun8i: h3: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all H3 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts       | 8 ++++++++
+ .../dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts   | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts        | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts       | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts    | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts     | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts      | 8 ++++++++
+ .../boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts   | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts    | 8 ++++++++
+ 10 files changed, 80 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts
+index 5b77300307de..2fa04f508216 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts
+@@ -159,6 +159,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	linux,rc-map-name = "rc-tanix-tx3mini";
+ 	pinctrl-names = "default";
+@@ -213,6 +217,10 @@ &reg_usb0_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spdif {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spdif_tx_pin>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts
+index 02fbe00cde97..61d6529dcc70 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts
+@@ -70,3 +70,11 @@ hdmi_out_con: endpoint {
+ &i2c1 {
+ 	status = "okay";
+ };
++
++&i2s2 {
++	status = "okay";
++};
++
++&sound_hdmi {
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts
+index 59bd0746acf8..10ae138b14f0 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts
+@@ -118,6 +118,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -159,6 +163,10 @@ &ohci2 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart3 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts
+index 69243dcb30a6..9393779f33b6 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts
+@@ -91,6 +91,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -104,3 +108,7 @@ &ohci1 {
+ &ohci2 {
+ 	status = "okay";
+ };
++
++&sound_hdmi {
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
+index d2ae47b074bf..7fac0c8906e8 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
+@@ -145,6 +145,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -179,6 +183,10 @@ &reg_usb1_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts
+index 6a4316a52469..28ec2a5b1a5c 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts
+@@ -120,6 +120,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -156,6 +160,10 @@ &ohci2 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index 59f6f6d5e7ca..927fd1bab07d 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -146,6 +146,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -166,6 +170,10 @@ &reg_usb0_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+index 92a58e362004..624e248e3ffc 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+@@ -147,6 +147,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -206,6 +210,10 @@ &reg_usb0_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts
+index 7a6444a10e25..4073d34af23c 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts
+@@ -117,6 +117,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -155,6 +159,10 @@ &ohci0 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts
+index 4738f3a9efe4..ee645912ee39 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts
+@@ -69,6 +69,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	bus-width = <4>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+@@ -98,6 +102,10 @@ &ohci3 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
new file mode 100644
index 000000000000..534a2e42883b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
@@ -0,0 +1,72 @@
+From 670a952ab127b973df0d741262c276f3b28e710e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 17 Aug 2020 23:43:53 +0200
+Subject: ARM: dts: sun8i-h3: Use my own more aggressive OPPs on H3
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 36 +++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index eac2349a2380..da1991c991cb 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -48,6 +48,12 @@ cpu0_opp_table: opp-table-cpu {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
++		opp-480000000 {
++			opp-hz = /bits/ 64 <480000000>;
++			opp-microvolt = <1040000 1040000 1300000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
+ 		opp-648000000 {
+ 			opp-hz = /bits/ 64 <648000000>;
+ 			opp-microvolt = <1040000 1040000 1300000>;
+@@ -60,11 +66,41 @@ opp-816000000 {
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
++		opp-960000000 {
++			opp-hz = /bits/ 64 <960000000>;
++			opp-microvolt = <1200000 1200000 1300000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
+ 		opp-1008000000 {
+ 			opp-hz = /bits/ 64 <1008000000>;
+ 			opp-microvolt = <1200000 1200000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
++
++		opp-1104000000 {
++			opp-hz = /bits/ 64 <1104000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1296000000 {
++			opp-hz = /bits/ 64 <1296000000>;
++			opp-microvolt = <1340000 1340000 1340000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1368000000 {
++			opp-hz = /bits/ 64 <1368000000>;
++			opp-microvolt = <1400000 1400000 1400000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
+ 	};
+ 
+ 	cpus {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
new file mode 100644
index 000000000000..5eb79a43e911
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
@@ -0,0 +1,49 @@
+From 8ac8f0eaefdc74b96a2f4a43dc25816e871ca82f Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Apr 2022 02:24:26 +0200
+Subject: ARM: dts: sun8i-h3-orange-pi-one: Enable all gpio header UARTs
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index f5476cdab8a4..64c489e356ce 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -54,6 +54,9 @@ / {
+ 	aliases {
+ 		ethernet0 = &emac;
+ 		serial0 = &uart0;
++		serial1 = &uart1;
++		serial2 = &uart2;
++		serial3 = &uart3;
+ 	};
+ 
+ 	chosen {
+@@ -183,19 +186,19 @@ &uart0 {
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart1_pins>;
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &uart2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart2_pins>;
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &uart3 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart3_pins>;
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &usb_otg {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
new file mode 100644
index 000000000000..9ba07466cee3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
@@ -0,0 +1,31 @@
+From 818de2527ada6977560b5c0e7497ea9da1135756 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 13 May 2018 21:00:43 +0200
+Subject: ARM: dts: sun8i-h3-orange-pi-pc: Increase max CPUX voltage to 1.4V
+
+When using thermal regulation we can afford to go higher. Also add
+regulator-ramp-delay, because regulator takes some time to change
+voltage.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+index b96e015f54ee..92a58e362004 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+@@ -194,7 +194,8 @@ reg_vdd_cpux: regulator@65 {
+ 		 * Use 1.0V as the minimum voltage instead.
+ 		 */
+ 		regulator-min-microvolt = <1000000>;
+-		regulator-max-microvolt = <1300000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
+ 		regulator-boot-on;
+ 		regulator-always-on;
+ 	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..14bda5801b5b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From 6f32d1c4391dd39f39d6995ca205e8a7ad54e011 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:50:56 +0200
+Subject: ARM: dts: sun8i: r40: Add hdmi sound card
+
+R40 support HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-r40.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+index a5b1f1e3900d..d73828d6b3c0 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+@@ -124,6 +124,20 @@ de: display-engine {
+ 		status = "disabled";
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun8i-r40-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	thermal-zones {
+ 		cpu_thermal: cpu0-thermal {
+ 			/* milliseconds */
+@@ -1265,6 +1279,7 @@ gic: interrupt-controller@1c81000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun8i-r40-dw-hdmi",
+ 				     "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
new file mode 100644
index 000000000000..98ee548089df
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
@@ -0,0 +1,42 @@
+From 13d18354688c9a84502549c5de7335892d8a6556 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:52:43 +0200
+Subject: ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable HDMI audio
+
+BananaPi M2 Ultra has HDMI output and thus supports HDMI audio. Enable
+it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts    | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
+index cd2351acc32f..a91213e8d2c1 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
+@@ -169,6 +169,10 @@ axp22x: pmic@34 {
+ 
+ #include "axp22x.dtsi"
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir0 {
+ 	status = "okay";
+ };
+@@ -304,6 +308,10 @@ &reg_eldo3 {
+ 	regulator-name = "vdd1v2-sata";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &tcon_tv0 {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
new file mode 100644
index 000000000000..08f08e67651b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
@@ -0,0 +1,42 @@
+From 1528d96b29ff39d7b2ff1fc63ec9c41a540a96fc Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 12:00:46 +0200
+Subject: ARM: dts: sun8i: v40: bananapi-m2-berry: Enable HDMI audio
+
+BananaPi M2 Berry has HDMI output and thus supports HDMI audio. Enable
+it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts    | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts
+index 6575ef274453..0e1395a3d052 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts
+@@ -160,6 +160,10 @@ axp22x: pmic@34 {
+ 
+ #include "axp22x.dtsi"
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdc1>;
+ 	bus-width = <4>;
+@@ -275,6 +279,10 @@ &reg_eldo3 {
+ 	regulator-name = "vdd1v2-sata";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &tcon_tv0 {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
new file mode 100644
index 000000000000..7a44371ec5ed
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
@@ -0,0 +1,29 @@
+From 6d3a73aad86d48873d9d763b0b6f92b462e28aaa Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 12 Nov 2017 19:03:39 +0100
+Subject: ARM: dts: suni-a83t: Add i2s0 pins
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index ed3d8e692d84..ef62ced26684 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -829,6 +829,11 @@ spdif_tx_pin: spdif-tx-pin {
+ 				function = "spdif";
+ 			};
+ 
++			i2s0_pins: i2s0-pins {
++				pins = "PB4", "PB5", "PB6", "PB7", "PB8";
++				function = "i2s0";
++			};
++
+ 			uart0_pb_pins: uart0-pb-pins {
+ 				pins = "PB9", "PB10";
+ 				function = "uart0";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
new file mode 100644
index 000000000000..af2fe2779f1b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
@@ -0,0 +1,66 @@
+From d89b78cb80282c569dbef3e929617af77205f4c4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 25 Jan 2021 01:15:58 +0100
+Subject: ARM: dts: sunxi: Add aliases for MMC
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun5i.dtsi      | 6 ++++++
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 6 ++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi   | 6 ++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i.dtsi b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+index 126b80f3ca70..a15effbbbc51 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+@@ -51,6 +51,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 7a5dc8a18906..01ee8520ab3a 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -57,6 +57,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index e601317d5de2..30d72d3b670e 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -44,6 +44,12 @@
+ #include <dt-bindings/thermal/thermal.h>
+ 
+ / {
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpu0_opp_table: opp-table-cpu {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..9197447a29e0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
@@ -0,0 +1,52 @@
+From fd838616840a4eaa41b75038d07fb5b02538c3f2 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:14:29 -0600
+Subject: ARM: dts: sunxi: a83t: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 2228294a9164..b95da4c64dee 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -284,6 +284,13 @@ opp-1800000000 {
+ 		};
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -417,6 +424,20 @@ syscon: syscon@1c00000 {
+ 			compatible = "allwinner,sun8i-a83t-system-controller",
+ 				"syscon";
+ 			reg = <0x01c00000 0x1000>;
++
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0x14000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0x14000>;
++
++				scpi_sram: scp-shmem@13c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x13c00 0x200>;
++				};
++			};
++
+ 		};
+ 
+ 		video-codec@01c0e000 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch
new file mode 100644
index 000000000000..bf7e917b61f8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch
@@ -0,0 +1,33 @@
+From 49db0a7c658f5e5ef8311c9b03766e8aa4bbff5e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:03:34 -0600
+Subject: ARM: dts: sunxi: a83t: Protect SCP clocks
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 0bbf43850c95..2228294a9164 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -690,6 +690,7 @@ ccu: clock@1c20000 {
+ 			reg = <0x01c20000 0x400>;
+ 			clocks = <&osc24M>, <&osc16Md512>;
+ 			clock-names = "hosc", "losc";
++			protected-clocks = <CLK_BUS_MSGBOX>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+@@ -1137,6 +1138,7 @@ r_ccu: clock@1f01400 {
+ 			clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
+ 				 <&ccu CLK_PLL_PERIPH>;
+ 			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			protected-clocks = <CLK_APB0_TWD>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..cf3792bfaef9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
@@ -0,0 +1,81 @@
+From cdfd92cf594115c52b5f987050881df6cef998b5 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:12:36 -0600
+Subject: ARM: dts: sunxi: h3/h5: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi    | 13 +++++++++++++
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi |  7 +++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 13 +++++++++++++
+ 3 files changed, 33 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index da1991c991cb..e601317d5de2 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -206,6 +206,19 @@ syscon: system-control@1c00000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0xc000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0xc000>;
++
++				scpi_sram: scp-shmem@bc00 {
++					compatible = "arm,scp-shmem";
++					reg = <0xbc00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@1d00000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x01d00000 0x80000>;
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 6d15eaeb06f4..d7b0ac4cc299 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -120,6 +120,13 @@ cpu {
+ 		};
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index d3caf27b6a55..e02a3848003e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -86,6 +86,19 @@ syscon: system-control@1c00000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0x14000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0x14000>;
++
++				scpi_sram: scp-shmem@13c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x13c00 0x200>;
++				};
++			};
++
+ 			sram_c1: sram@18000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00018000 0x1c000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..18ea343edf1d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From e754d1e717e242da2c80be847606105aebeb5dff Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:04:58 +0200
+Subject: ARM: dts: sunxi: h3/h5: Add hdmi sound card
+
+H3 and H5 support HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 7df60515a903..0f19e7c00c50 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -106,6 +106,20 @@ de: display-engine {
+ 		status = "disabled";
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun8i-h3-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -818,6 +832,7 @@ csi: camera@1cb0000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun8i-h3-dw-hdmi",
+ 				     "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch
new file mode 100644
index 000000000000..e751ffd4a84e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch
@@ -0,0 +1,33 @@
+From a0a7c35298684d62725a6f401a4b669b5ff897f8 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:03:46 -0600
+Subject: ARM: dts: sunxi: h3/h5: Protect SCP clocks
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index a872fc586ab6..beadc26243f5 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -407,6 +407,7 @@ ccu: clock@1c20000 {
+ 			reg = <0x01c20000 0x400>;
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
+ 			clock-names = "hosc", "losc";
++			protected-clocks = <CLK_BUS_MSGBOX>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+@@ -902,6 +903,7 @@ r_ccu: clock@1f01400 {
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
+ 				 <&ccu CLK_PLL_PERIPH0>;
+ 			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			protected-clocks = <CLK_APB0_TWD>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
new file mode 100644
index 000000000000..4097c50a344b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
@@ -0,0 +1,88 @@
+From 41d4964786ec86353ba2041543bff180b8f964a6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Oct 2019 05:06:29 +0200
+Subject: ARM: sunxi: Add experimental suspend to memory implementation for
+ A83T
+
+This just ends with WFI, but all secondary CPUs will be shut down.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/mach-sunxi/sunxi.c | 46 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
+index e1b7945aac99..2d6b7b4528e9 100644
+--- a/arch/arm/mach-sunxi/sunxi.c
++++ b/arch/arm/mach-sunxi/sunxi.c
+@@ -12,10 +12,13 @@
+ #include <linux/init.h>
+ #include <linux/of_clk.h>
+ #include <linux/platform_device.h>
++#include <linux/of_platform.h>
+ #include <linux/reset/sunxi.h>
++#include <linux/suspend.h>
+ 
+ #include <asm/mach/arch.h>
+ #include <asm/secure_cntvoff.h>
++#include <asm/suspend.h>
+ 
+ static const char * const sunxi_board_dt_compat[] = {
+ 	"allwinner,sun4i-a10",
+@@ -86,10 +89,53 @@ static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
+ 	NULL,
+ };
+ 
++#ifdef CONFIG_PM_SLEEP
++static int sun8i_a83t_pm_valid(suspend_state_t state)
++{
++	return state == PM_SUSPEND_MEM;
++}
++
++static int sun8i_a83t_suspend_finish(unsigned long val)
++{
++	// don't do much
++	cpu_do_idle();
++	return 0;
++}
++
++static int sun8i_a83t_pm_enter(suspend_state_t state)
++{
++	switch (state) {
++	case PM_SUSPEND_MEM:
++		cpu_suspend(0, sun8i_a83t_suspend_finish);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const struct platform_suspend_ops sun8i_a83t_pm_ops = {
++	.enter = sun8i_a83t_pm_enter,
++	.valid = sun8i_a83t_pm_valid,
++};
++#define SUN8I_A83T_PM_OPS &sun8i_a83t_pm_ops
++#else
++#define SUN8I_A83T_PM_OPS NULL
++#endif
++
++static void __init sun8i_a83t_init_machine(void)
++{
++	suspend_set_ops(SUN8I_A83T_PM_OPS);
++
++	of_platform_default_populate(NULL, NULL, NULL);
++}
++
+ DT_MACHINE_START(SUN8I_A83T_CNTVOFF_DT, "Allwinner A83t board")
+ 	.init_early	= sun8i_a83t_cntvoff_init,
+ 	.init_time	= sun6i_timer_init,
+ 	.dt_compat	= sun8i_a83t_cntvoff_board_dt_compat,
++	.init_machine	= sun8i_a83t_init_machine,
+ MACHINE_END
+ 
+ static const char * const sun9i_board_dt_compat[] = {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
new file mode 100644
index 000000000000..05a5f2bc7431
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
@@ -0,0 +1,54 @@
+From 4ac97bf86932089f2e95639626513301ea84c04e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 2 Nov 2019 15:21:04 +0100
+Subject: ARM: sunxi: Use SCPI to send suspend message to SCP on A83T
+
+We use undefined value of 3, to mean SUSPEND_SYSTEM. SCP should:
+
+- kill CPU0
+- kill cluster 0
+- shutdown power to both clusters (Linux MCPM doesn't do that)
+...
+- reverse all of the above on interrupt
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/mach-sunxi/sunxi.c | 15 +++++++++++++--
+ 1 file changed, 13 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
+index 2d6b7b4528e9..d4c25c33455d 100644
+--- a/arch/arm/mach-sunxi/sunxi.c
++++ b/arch/arm/mach-sunxi/sunxi.c
+@@ -14,6 +14,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/of_platform.h>
+ #include <linux/reset/sunxi.h>
++#include <linux/scpi_protocol.h>
+ #include <linux/suspend.h>
+ 
+ #include <asm/mach/arch.h>
+@@ -97,8 +98,18 @@ static int sun8i_a83t_pm_valid(suspend_state_t state)
+ 
+ static int sun8i_a83t_suspend_finish(unsigned long val)
+ {
+-	// don't do much
+-	cpu_do_idle();
++	struct scpi_ops *scpi;
++
++	scpi = get_scpi_ops();
++	if (scpi && scpi->sys_set_power_state) {
++		//HACK: use invalid state to mean: suspend last CPU and the system
++		scpi->sys_set_power_state(3);
++		cpu_do_idle();
++	} else {
++		// don't do much if scpi is not available
++		cpu_do_idle();
++	}
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
new file mode 100644
index 000000000000..3f63ae556e8b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
@@ -0,0 +1,27 @@
+From de8eecb45a46ccf098b4e798fbbdb68edf8eeb4d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Oct 2019 05:08:04 +0200
+Subject: ARM: sunxi: sunxi_cpu0_hotplug_support_set is not supported on A83T
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/mach-sunxi/mc_smp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
+index 277f6aa8e6c2..ca237d50db4b 100644
+--- a/arch/arm/mach-sunxi/mc_smp.c
++++ b/arch/arm/mach-sunxi/mc_smp.c
+@@ -146,6 +146,9 @@ static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
+ 
+ static void sunxi_cpu0_hotplug_support_set(bool enable)
+ {
++	if (is_a83t)
++		return;
++
+ 	if (enable) {
+ 		writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base);
+ 		writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
new file mode 100644
index 000000000000..629165193cb9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
@@ -0,0 +1,235 @@
+From 8d1fad9954e7582b6ec81405a9594aeec9a08877 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Tue, 10 Nov 2020 20:42:44 +0100
+Subject: ASOC: sun9i-hdmi-audio: Initial implementation
+
+This implements HDMI audio sound card which is used to enable HDMI audio
+on all Allwinner SoCs with DW-HDMI core. First such SoC is A80, but it's
+been used on plenty of others, like A64, A83t, H2+, H3, H5, H6, R40 and
+V40.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ sound/soc/sunxi/Kconfig            |   8 ++
+ sound/soc/sunxi/Makefile           |   1 +
+ sound/soc/sunxi/sun9i-hdmi-audio.c | 180 +++++++++++++++++++++++++++++
+ 3 files changed, 189 insertions(+)
+ create mode 100644 sound/soc/sunxi/sun9i-hdmi-audio.c
+
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index f87b061f59b2..753c38c5d554 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -76,6 +76,14 @@ config SND_SUN50I_DMIC
+ 	  Say Y or M to add support for the DMIC audio block in the Allwinner
+ 	  H6 and affiliated SoCs.
+ 
++config SND_SUN9I_HDMI_AUDIO
++	tristate "Allwinner sun9i HDMI Audio Sound Card"
++	depends on OF
++	depends on SND_SUN4I_I2S
++	help
++	  Say Y or M to add support for the HDMI Audio sound card for Allwinner
++	  SoCs with DW-HDMI core.
++
+ config SND_SUN8I_ADDA_PR_REGMAP
+ 	tristate
+ 	select REGMAP
+diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
+index 6131aea97efa..19800277105c 100644
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -8,3 +8,4 @@ obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
+ obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+ obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
+ obj-$(CONFIG_SND_SUN50I_DMIC) += sun50i-dmic.o
++obj-$(CONFIG_SND_SUN9I_HDMI_AUDIO) += sun9i-hdmi-audio.o
+diff --git a/sound/soc/sunxi/sun9i-hdmi-audio.c b/sound/soc/sunxi/sun9i-hdmi-audio.c
+new file mode 100644
+index 000000000000..4320c7fa23d4
+--- /dev/null
++++ b/sound/soc/sunxi/sun9i-hdmi-audio.c
+@@ -0,0 +1,180 @@
++// SPDX-License-Identifier: GPL-2.0
++//
++// sun9i hdmi audio sound card
++//
++// Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@gmail.com>
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++
++static int sun9i_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
++				      struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++	unsigned int mclk;
++
++	mclk = params_rate(params) * 128;
++
++	return snd_soc_dai_set_sysclk(snd_soc_rtd_to_cpu(rtd, 0), 0, mclk,
++				      SND_SOC_CLOCK_OUT);
++}
++
++static const struct snd_soc_ops sun9i_hdmi_audio_ops = {
++	.hw_params = sun9i_hdmi_audio_hw_params,
++};
++
++static int sun9i_hdmi_audio_dai_init(struct snd_soc_pcm_runtime *rtd)
++{
++	int ret;
++
++	/* TODO: switch to custom api once it's implemented in sun4i-i2s */
++	ret = snd_soc_dai_set_tdm_slot(snd_soc_rtd_to_cpu(rtd, 0), 0, 0, 2, 32);
++	if (ret) {
++		dev_err(snd_soc_rtd_to_cpu(rtd, 0)->dev,
++			"setting tdm link slots failed\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int sun9i_hdmi_audio_parse_dai(struct device_node *node,
++				      struct snd_soc_dai_link_component *dlc)
++{
++	struct of_phandle_args args;
++	int ret;
++
++	if (!node)
++		return 0;
++
++	ret = of_parse_phandle_with_args(node, "sound-dai",
++					 "#sound-dai-cells", 0, &args);
++	if (ret)
++		return ret;
++
++	ret = snd_soc_get_dai_name(&args, &dlc->dai_name);
++	if (ret < 0) {
++		of_node_put(args.np);
++
++		return ret;
++	}
++
++	dlc->of_node = args.np;
++
++	return 0;
++}
++
++static int sun9i_hdmi_audio_probe(struct platform_device *pdev)
++{
++	struct snd_soc_dai_link_component *dlc;
++	struct device *dev = &pdev->dev;
++	struct snd_soc_dai_link *link;
++	struct snd_soc_card *card;
++	struct device_node *child;
++	int ret;
++
++	card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
++	if (!card)
++		return -ENOMEM;
++
++	link = devm_kzalloc(dev, sizeof(*link), GFP_KERNEL);
++	if (!link)
++		return -ENOMEM;
++
++	dlc = devm_kzalloc(dev, sizeof(*dlc) * 3, GFP_KERNEL);
++	if (!dlc)
++		return -ENOMEM;
++
++	child = of_get_child_by_name(dev->of_node, "codec");
++	if (!child)
++		return -ENODEV;
++
++	ret = sun9i_hdmi_audio_parse_dai(child, &dlc[1]);
++	of_node_put(child);
++	if (ret)
++		return ret;
++
++	child = of_get_child_by_name(dev->of_node, "cpu");
++	if (!child) {
++		ret = -ENODEV;
++		goto out_err;
++	}
++
++	ret = sun9i_hdmi_audio_parse_dai(child, &dlc[0]);
++	of_node_put(child);
++	if (ret)
++		goto out_err;
++
++	dlc[2].of_node = dlc[0].of_node;
++
++	platform_set_drvdata(pdev, card);
++
++	link->cpus = &dlc[0];
++	link->codecs = &dlc[1];
++	link->platforms = &dlc[2];
++
++	link->num_cpus = 1;
++	link->num_codecs = 1;
++	link->num_platforms = 1;
++
++	link->playback_only = 1;
++
++	link->name = "SUN9I-HDMI";
++	link->stream_name = "SUN9I-HDMI PCM";
++
++	link->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_CBS_CFS;
++
++	link->ops = &sun9i_hdmi_audio_ops;
++	link->init = sun9i_hdmi_audio_dai_init;
++
++	card->dai_link = link;
++	card->num_links = 1;
++	card->owner = THIS_MODULE;
++	card->dev = dev;
++	card->name = "sun9i-hdmi";
++
++	ret = devm_snd_soc_register_card(dev, card);
++	if (ret)
++		goto out_err;
++
++	return 0;
++
++out_err:
++	of_node_put(dlc[0].of_node);
++	of_node_put(dlc[1].of_node);
++
++	return ret;
++}
++
++static int sun9i_hdmi_audio_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++	of_node_put(card->dai_link->cpus->of_node);
++	of_node_put(card->dai_link->codecs->of_node);
++
++	return 0;
++}
++
++static const struct of_device_id sun9i_hdmi_audio_match[] = {
++	{ .compatible = "allwinner,sun9i-a80-hdmi-audio" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, sun9i_hdmi_audio_match);
++
++static struct platform_driver sun9i_hdmi_audio_driver = {
++	.probe = sun9i_hdmi_audio_probe,
++	.remove = sun9i_hdmi_audio_remove,
++	.driver = {
++		.name = "sun9i-hdmi-audio",
++		.of_match_table = sun9i_hdmi_audio_match,
++	},
++};
++module_platform_driver(sun9i_hdmi_audio_driver);
++
++MODULE_DESCRIPTION("sun9i HDMI Audio Sound Card");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@gmail.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch
new file mode 100644
index 000000000000..fc49f87cd651
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch
@@ -0,0 +1,29 @@
+From b283268213ca6530727ef0d0a09fd578e6552ef4 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 29 Jul 2022 01:08:29 +0200
+Subject: ASoC: codec: es8316: "DAC Soft Ramp Rate" is just a 2 bit control
+
+Max value should be 3, otherwise "DAC Soft Ramp Switch" will be
+overwritten by this control.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/codecs/es8316.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c
+index 61729e5b50a8..71aad3e4c83f 100644
+--- a/sound/soc/codecs/es8316.c
++++ b/sound/soc/codecs/es8316.c
+@@ -99,7 +99,7 @@ static const struct snd_kcontrol_new es8316_snd_controls[] = {
+ 	SOC_DOUBLE_R_TLV("DAC Playback Volume", ES8316_DAC_VOLL,
+ 			 ES8316_DAC_VOLR, 0, 0xc0, 1, dac_vol_tlv),
+ 	SOC_SINGLE("DAC Soft Ramp Switch", ES8316_DAC_SET1, 4, 1, 1),
+-	SOC_SINGLE("DAC Soft Ramp Rate", ES8316_DAC_SET1, 2, 4, 0),
++	SOC_SINGLE("DAC Soft Ramp Rate", ES8316_DAC_SET1, 2, 3, 0),
+ 	SOC_SINGLE("DAC Notch Filter Switch", ES8316_DAC_SET2, 6, 1, 0),
+ 	SOC_SINGLE("DAC Double Fs Switch", ES8316_DAC_SET2, 7, 1, 0),
+ 	SOC_SINGLE("DAC Stereo Enhancement", ES8316_DAC_SET3, 0, 7, 0),
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
new file mode 100644
index 000000000000..c74610dc9762
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
@@ -0,0 +1,154 @@
+From 535b6e35fdf2e43f27939d0e9ffee91c475483c3 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 25 Sep 2020 21:42:52 -0500
+Subject: ASoC: ec25: New codec driver for the EC25 modem
+
+The EC25 LTE modem has a PCM interface, and supports 16-bit PCM audio at
+an 8 kHz or 16 kHz sameple rate.
+
+Suggested-by: Luca Weiss <luca@z3ntu.xyz>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/codecs/Kconfig  |  3 ++
+ sound/soc/codecs/Makefile |  2 +
+ sound/soc/codecs/ec25.c   | 94 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 99 insertions(+)
+ create mode 100644 sound/soc/codecs/ec25.c
+
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index 4afc43d3f71f..beae7bf571b4 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -1091,6 +1091,9 @@ config SND_SOC_HDMI_CODEC
+ 	select SND_PCM_IEC958
+ 	select HDMI
+ 
++config SND_SOC_EC25
++	tristate "EC25 LTE module CODEC"
++
+ config SND_SOC_ES7134
+ 	tristate "Everest Semi ES7134 CODEC"
+ 
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index b4df22186e25..5795dcafa5e7 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -116,6 +116,7 @@ snd-soc-da7219-y := da7219.o da7219-aad.o
+ snd-soc-da732x-y := da732x.o
+ snd-soc-da9055-y := da9055.o
+ snd-soc-dmic-y := dmic.o
++snd-soc-ec25-y := ec25.o
+ snd-soc-es7134-y := es7134.o
+ snd-soc-es7241-y := es7241.o
+ snd-soc-es83xx-dsm-common-y := es83xx-dsm-common.o
+@@ -513,6 +514,7 @@ obj-$(CONFIG_SND_SOC_DA7219)	+= snd-soc-da7219.o
+ obj-$(CONFIG_SND_SOC_DA732X)	+= snd-soc-da732x.o
+ obj-$(CONFIG_SND_SOC_DA9055)	+= snd-soc-da9055.o
+ obj-$(CONFIG_SND_SOC_DMIC)	+= snd-soc-dmic.o
++obj-$(CONFIG_SND_SOC_EC25)	+= snd-soc-ec25.o
+ obj-$(CONFIG_SND_SOC_ES7134)	+= snd-soc-es7134.o
+ obj-$(CONFIG_SND_SOC_ES7241)	+= snd-soc-es7241.o
+ obj-$(CONFIG_SND_SOC_ES83XX_DSM_COMMON)    += snd-soc-es83xx-dsm-common.o
+diff --git a/sound/soc/codecs/ec25.c b/sound/soc/codecs/ec25.c
+new file mode 100644
+index 000000000000..4f9b6b06cce7
+--- /dev/null
++++ b/sound/soc/codecs/ec25.c
+@@ -0,0 +1,94 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include <linux/module.h>
++#include <sound/soc.h>
++
++static const struct snd_soc_dapm_widget ec25_dapm_widgets[] = {
++	SND_SOC_DAPM_OUTPUT("AOUT"),
++	SND_SOC_DAPM_INPUT("AIN"),
++};
++
++static const struct snd_soc_dapm_route ec25_dapm_routes[] = {
++	{ "AOUT", NULL, "Playback" },
++	{ "AOUT", NULL, "Wideband Playback" },
++	{ "Capture", NULL, "AIN" },
++	{ "Wideband Capture", NULL, "AIN" },
++};
++
++static const struct snd_soc_component_driver ec25_component_driver = {
++	.dapm_widgets		= ec25_dapm_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(ec25_dapm_widgets),
++	.dapm_routes		= ec25_dapm_routes,
++	.num_dapm_routes	= ARRAY_SIZE(ec25_dapm_routes),
++	.endianness		= 1,
++};
++
++static struct snd_soc_dai_driver ec25_dais[] = {
++	{
++		.name = "ec25",
++		.capture = {
++			.stream_name	= "Capture",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_8000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.playback = {
++			.stream_name	= "Playback",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_8000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.symmetric_rate = 1,
++		.symmetric_channels = 1,
++		.symmetric_sample_bits = 1,
++	},
++	{
++		.name = "ec25-wb",
++		.capture = {
++			.stream_name	= "Wideband Capture",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_16000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.playback = {
++			.stream_name	= "Wideband Playback",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_16000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.symmetric_rate = 1,
++		.symmetric_channels = 1,
++		.symmetric_sample_bits = 1,
++	},
++};
++
++static int ec25_codec_probe(struct platform_device *pdev)
++{
++	return devm_snd_soc_register_component(&pdev->dev, &ec25_component_driver,
++					       ec25_dais, ARRAY_SIZE(ec25_dais));
++}
++
++static const struct of_device_id ec25_codec_of_match[] = {
++	{ .compatible = "quectel,ec25", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ec25_codec_of_match);
++
++static struct platform_driver ec25_codec_driver = {
++	.driver	= {
++		.name		= "ec25",
++		.of_match_table	= of_match_ptr(ec25_codec_of_match),
++	},
++	.probe	= ec25_codec_probe,
++};
++
++module_platform_driver(ec25_codec_driver);
++
++MODULE_DESCRIPTION("ASoC ec25 driver");
++MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ec25");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
new file mode 100644
index 000000000000..2609a82c5f0f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
@@ -0,0 +1,45 @@
+From 9ffec7c6d93d7b0c83d95332c3a198e8bdbb1297 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 15 Aug 2022 02:23:37 +0200
+Subject: ASoC: rockchip: Fix doubling of playback speed after system sleep
+
+There is some issue with CRU on RK3399 that can be reproduced by:
+
+- playing some audio and stopping the playback (so that runtime PM suspends I2S)
+- putting system to deep sleep and resuming it (using mainline TF-A)
+- playing some audio (audio plays at 2x the normal speed)
+
+If the audio is kept playing during system sleep cycle, the issue
+does not manifest. Relevant registers in CRU are identical in bug/
+no-bug scenarios, so this patch is just touching the CRU registers
+without actually changing anything in the end. Touching the registers
+fixes the playback speed, though.
+
+Inspired by: https://github.com/djselbeck/linux/commit/cb4be5dec3fa18c4b344c11fed3fc57aa3bea424
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/rockchip/rockchip_i2s.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
+index b0c3ef030e06..cd2666a5359d 100644
+--- a/sound/soc/rockchip/rockchip_i2s.c
++++ b/sound/soc/rockchip/rockchip_i2s.c
+@@ -115,6 +115,13 @@ static int i2s_runtime_resume(struct device *dev)
+ 	if (ret)
+ 		clk_disable_unprepare(i2s->mclk);
+ 
++	if (ret == 0) {
++		unsigned long rate = clk_get_rate(i2s->mclk);
++
++		clk_set_rate(i2s->mclk, rate - 1);
++		clk_set_rate(i2s->mclk, rate);
++	}
++
+ 	return ret;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch
new file mode 100644
index 000000000000..6c7fb5951a10
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch
@@ -0,0 +1,67 @@
+From 5c6142020e7aa3ea44176271ac422a6f8ffe3a27 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 14 May 2024 10:46:10 +0200
+Subject: ASoC: simple-card: Allow to define pins for aux jack devices
+
+This restores original behavior of jack pins on Pinephone, as it was
+before upstreaming jack detection to codec driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/generic/simple-card-utils.c | 40 +++++++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+diff --git a/sound/soc/generic/simple-card-utils.c b/sound/soc/generic/simple-card-utils.c
+index b4876b4f259d..07e6a5f43b04 100644
+--- a/sound/soc/generic/simple-card-utils.c
++++ b/sound/soc/generic/simple-card-utils.c
+@@ -836,6 +836,46 @@ int simple_util_init_aux_jacks(struct simple_util_priv *priv, char *prefix)
+ 			continue;
+ 
+ 		(void)snd_soc_component_set_jack(component, jack, NULL);
++
++		/* add pins to the jack */
++		int count = of_property_count_strings(card->dev->of_node, "simple-audio-card,jack-pins");
++		if (count < 0) {
++			if (count != -EINVAL)
++				dev_warn(card->dev, "Invalid jack-pins property\n");
++			continue;
++		}
++		if (count % 2) {
++			dev_warn(card->dev, "jack-pins property must have even number of strings\n");
++			continue;
++		}
++
++		for (int idx = 0; idx < count; idx += 2) {
++			const char *aux_dev_name, *pin_name;
++			u32 mask;
++
++			ret = of_property_read_string_index(card->dev->of_node, "simple-audio-card,jack-pins", idx, &aux_dev_name);
++			if (ret < 0)
++				continue;
++			ret = of_property_read_string_index(card->dev->of_node, "simple-audio-card,jack-pins", idx + 1, &pin_name);
++			if (ret < 0)
++				continue;
++			ret = of_property_read_u32_index(card->dev->of_node, "simple-audio-card,jack-pins-mask", idx / 2, &mask);
++			if (ret < 0) {
++				dev_warn(card->dev, "jack-pins-mask for jack pin %s/%s can't be read\n", aux_dev_name, pin_name);
++				continue;
++			}
++
++			if (!strcmp(aux_dev_name, component->name)) {
++				struct snd_soc_jack_pin *pin = devm_kzalloc(card->dev, sizeof(*pin), GFP_KERNEL);
++
++				pin->pin = pin_name;
++				pin->mask = mask;
++
++				dev_info(card->dev, "Adding jack %s pin %s (mask %d)\n",
++					 aux_dev_name, pin_name, pin->mask);
++				snd_soc_jack_add_pins(jack, 1, pin);
++			}
++		}
+ 	}
+ 	return 0;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
new file mode 100644
index 000000000000..1d14610de7b0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
@@ -0,0 +1,129 @@
+From 64dca4af853146e4f3a2b35416f09ffe1cda22fa Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 17 Feb 2024 01:13:39 +0100
+Subject: ASoC: sun8i-codec: Add debug output for jack detection
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 32 +++++++++++++++++++++++++++++++-
+ 1 file changed, 31 insertions(+), 1 deletion(-)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 67e304cb4238..a89c0f6aa99f 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -9,6 +9,8 @@
+  * Mylène Josserand <mylene.josserand@free-electrons.com>
+  */
+ 
++#define DEBUG
++
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
+@@ -234,6 +236,7 @@ struct sun8i_codec {
+ 	int				jack_status;
+ 	int				jack_type;
+ 	int				jack_last_sample;
++	unsigned			jack_last_btn;
+ 	ktime_t				jack_hbias_ready;
+ 	struct mutex			jack_mutex;
+ 	int				last_hmic_irq;
+@@ -1344,6 +1347,8 @@ static void sun8i_codec_set_hmic_bias(struct sun8i_codec *scodec, bool enable)
+ 
+ 	snd_soc_dapm_sync(dapm);
+ 
++	dev_dbg(scodec->component->dev, "HMIC bias %s\n", enable ? "on" : "off");
++
+ 	regmap_update_bits(scodec->regmap, SUN8I_HMIC_CTRL1,
+ 			   irq_mask, enable ? irq_mask : 0);
+ }
+@@ -1352,6 +1357,7 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ {
+ 	struct sun8i_codec *scodec = container_of(work, struct sun8i_codec,
+ 						  jack_work.work);
++	struct device *dev = scodec->component->dev;
+ 	unsigned int mdata;
+ 	int type;
+ 
+@@ -1362,6 +1368,7 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 			return;
+ 
+ 		scodec->jack_last_sample = -1;
++		scodec->jack_last_btn = 0;
+ 
+ 		if (scodec->jack_type & SND_JACK_MICROPHONE) {
+ 			/*
+@@ -1419,6 +1426,8 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 
+ 		snd_soc_jack_report(scodec->jack, type, scodec->jack_type);
+ 		scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED;
++
++		dev_dbg(dev, "jack: plug-in reported\n");
+ 	} else if (scodec->jack_status == SUN8I_JACK_STATUS_CONNECTED) {
+ 		if (scodec->last_hmic_irq != SUN8I_HMIC_STS_JACK_OUT_IRQ_ST)
+ 			return;
+@@ -1428,14 +1437,18 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 			sun8i_codec_set_hmic_bias(scodec, false);
+ 
+ 		snd_soc_jack_report(scodec->jack, 0, scodec->jack_type);
++
++		dev_dbg(dev, "jack: plug-out reported\n");
+ 	}
+ }
+ 
+ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ {
+ 	struct sun8i_codec *scodec = dev_id;
++	struct device *dev = scodec->component->dev;
+ 	int type = SND_JACK_HEADSET;
+ 	unsigned int status, value;
++	unsigned btn_chg = 0;
+ 
+ 	guard(mutex)(&scodec->jack_mutex);
+ 
+@@ -1447,6 +1460,8 @@ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ 	 * 100ms after each interrupt..
+ 	 */
+ 	if (status & BIT(SUN8I_HMIC_STS_JACK_OUT_IRQ_ST)) {
++		dev_dbg(dev, "jack: irq plug-out\n");
++
+ 		/*
+ 		 * Out interrupt has priority over in interrupt so that if
+ 		 * we get both, we assume the disconnected state, which is
+@@ -1456,6 +1471,8 @@ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ 		mod_delayed_work(system_power_efficient_wq, &scodec->jack_work,
+ 				 msecs_to_jiffies(100));
+ 	} else if (status & BIT(SUN8I_HMIC_STS_JACK_IN_IRQ_ST)) {
++		dev_dbg(dev, "jack: irq plug-in\n");
++
+ 		scodec->last_hmic_irq = SUN8I_HMIC_STS_JACK_IN_IRQ_ST;
+ 		mod_delayed_work(system_power_efficient_wq, &scodec->jack_work,
+ 				 msecs_to_jiffies(100));
+@@ -1489,9 +1506,22 @@ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ 		 * samples are identical.
+ 		 */
+ 		if (scodec->jack_last_sample >= 0 &&
+-		    scodec->jack_last_sample == value)
++		    scodec->jack_last_sample == value) {
+ 			snd_soc_jack_report(scodec->jack, type,
+ 					    scodec->jack_type);
++			btn_chg = (scodec->jack_last_btn ^ type) & SUN8I_CODEC_BUTTONS;
++			scodec->jack_last_btn = type;
++		}
++
++		if (btn_chg & SND_JACK_BTN_0)
++			dev_dbg(dev, "jack: key_%spress BTN_0 (%#x)\n",
++				type & SND_JACK_BTN_0 ? "" : "de", value);
++		if (btn_chg & SND_JACK_BTN_1)
++			dev_dbg(dev, "jack: key_%spress BTN_1 (%#x)\n",
++				type & SND_JACK_BTN_1 ? "" : "de", value);
++		if (btn_chg & SND_JACK_BTN_2)
++			dev_dbg(dev, "jack: key_%spress BTN_2 (%#x)\n",
++				type & SND_JACK_BTN_2 ? "" : "de", value);
+ 
+ 		scodec->jack_last_sample = value;
+ 	}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
new file mode 100644
index 000000000000..5235b040c807
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
@@ -0,0 +1,47 @@
+From 9fa9442e36400a2d0a62917883bd594954952158 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Mar 2024 14:55:31 +0100
+Subject: ASoC: sun8i-codec: Allow the jack type to be set via device tree
+
+This makes the codec's jack detection functionality usable from within
+simple-sound-card.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index b5dafb749c3f..09fc25f67a15 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -1563,6 +1563,18 @@ static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component)
+ 	scodec->jack = NULL;
+ }
+ 
++static int sun8i_codec_component_get_jack_type(struct snd_soc_component *component)
++{
++	struct device_node *node = component->dev->of_node;
++
++	if (of_property_match_string(node, "jack-type", "headset") >= 0)
++		return SND_JACK_HEADSET | SUN8I_CODEC_BUTTONS;
++	else if (of_property_match_string(node, "jack-type", "headphone") >= 0)
++		return SND_JACK_HEADPHONE;
++
++	return 0;
++}
++
+ static int sun8i_codec_component_set_jack(struct snd_soc_component *component,
+ 					  struct snd_soc_jack *jack, void *data)
+ {
+@@ -1584,6 +1596,7 @@ static const struct snd_soc_component_driver sun8i_soc_component = {
+ 	.dapm_routes		= sun8i_codec_dapm_routes,
+ 	.num_dapm_routes	= ARRAY_SIZE(sun8i_codec_dapm_routes),
+ 	.set_jack		= sun8i_codec_component_set_jack,
++	.get_jack_type		= sun8i_codec_component_get_jack_type,
+ 	.probe			= sun8i_codec_component_probe,
+ 	.idle_bias_on		= 1,
+ 	.suspend_bias_off	= 1,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
new file mode 100644
index 000000000000..4cbda4e85363
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
@@ -0,0 +1,48 @@
+From 1340d883693900622c1966e915ae506583c9dcbe Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 26 Mar 2024 17:38:38 +0100
+Subject: ASoC: sun8i-codec: Set jack_type from DT in probe
+
+Jack type needs to be set in probe so that it can be used later on.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index a89c0f6aa99f..c6550f0b3204 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -1602,14 +1602,9 @@ static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component)
+ 
+ static int sun8i_codec_component_get_jack_type(struct snd_soc_component *component)
+ {
+-	struct device_node *node = component->dev->of_node;
+-
+-	if (of_property_match_string(node, "jack-type", "headset") >= 0)
+-		return SND_JACK_HEADSET | SUN8I_CODEC_BUTTONS;
+-	else if (of_property_match_string(node, "jack-type", "headphone") >= 0)
+-		return SND_JACK_HEADPHONE;
++	struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
+ 
+-	return 0;
++	return scodec->jack_type;
+ }
+ 
+ static int sun8i_codec_component_set_jack(struct snd_soc_component *component,
+@@ -1671,6 +1666,11 @@ static int sun8i_codec_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, scodec);
+ 
++	if (of_property_match_string(pdev->dev.of_node, "jack-type", "headset") >= 0)
++		scodec->jack_type = SND_JACK_HEADSET | SUN8I_CODEC_BUTTONS;
++	else if (of_property_match_string(pdev->dev.of_node, "jack-type", "headphone") >= 0)
++		scodec->jack_type = SND_JACK_HEADPHONE;
++
+ 	if (scodec->quirks->bus_clock) {
+ 		scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
+ 		if (IS_ERR(scodec->clk_bus)) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
new file mode 100644
index 000000000000..55943b49174b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
@@ -0,0 +1,31 @@
+From affb98b0c138a41fdd9aea5cf8d090c84ee9a188 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 23 Feb 2024 01:58:40 +0100
+Subject: ASoC: sun8i-codec: define button keycodes
+
+This is likely not upstreamable, but simple. :)
+---
+ sound/soc/sunxi/sun8i-codec.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 09fc25f67a15..67e304cb4238 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -1541,6 +1541,13 @@ static int sun8i_codec_enable_jack_detect(struct snd_soc_component *component,
+ 	if (ret)
+ 		return ret;
+ 
++	if (jack->jack->type & SND_JACK_MICROPHONE) {
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
++	}
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
new file mode 100644
index 000000000000..9e2993015c10
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
@@ -0,0 +1,215 @@
+From ccb07b9acbe14fef134649ba492ccaacdae8f223 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 22 Nov 2016 01:01:49 +0100
+Subject: Add README.md with information and u-boot patches
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ ...Fix-PLL1-setup-to-never-use-dividers.patch |  33 ++++
+ README.md                                     | 154 ++++++++++++++++++
+ 2 files changed, 187 insertions(+)
+ create mode 100644 0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
+ create mode 100644 README.md
+
+diff --git a/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch b/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
+new file mode 100644
+index 000000000000..2b892e805a2b
+--- /dev/null
++++ b/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
+@@ -0,0 +1,33 @@
++From 7f5071f906f79bdc99d6b4b0ccf0cb280abe740b Mon Sep 17 00:00:00 2001
++From: Ondrej Jirman <megi@xff.cz>
++Date: Tue, 20 Dec 2016 11:25:12 +0100
++Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers
++
++Kernel would lower the divider on first CLK change and cause the
++lock up.
++---
++ arch/arm/mach-sunxi/clock_sun6i.c | 7 +++----
++ 1 file changed, 3 insertions(+), 4 deletions(-)
++
++diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
++index 50fb302a19..91aa2a0478 100644
++--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++++ b/arch/arm/mach-sunxi/clock_sun6i.c
++@@ -94,11 +94,10 @@ void clock_set_pll1(unsigned int clk)
++ 	int k = 1;
++ 	int m = 1;
++ 
++-	if (clk > 1152000000) {
++-		k = 2;
++-	} else if (clk > 768000000) {
+++	if (clk >= 1368000000) {
++ 		k = 3;
++-		m = 2;
+++	} else if (clk >= 768000000) {
+++		k = 2;
++ 	}
++ 
++ 	/* Switch to 24MHz clock while changing PLL1 */
++-- 
++2.11.0
++
+diff --git a/README.md b/README.md
+new file mode 100644
+index 000000000000..74c4c16416d3
+--- /dev/null
++++ b/README.md
+@@ -0,0 +1,154 @@
++Mainline linux kernel for Orange Pi PC/PC2/PC3/One, TBS A711, PinePhone (Pro), PocketBook Touch Lux 3
++------------------------------------------------------------------------------------------------------
++
++This kernel tree is meant for:
++
++- Orange Pi One
++- Orange Pi PC
++- Orange Pi PC 2
++- Orange Pi 3
++- PinePhone 1.0, 1.1 and 1.2(a/b)
++- TBS A711 Tablet
++- PocketBook Touch Lux 3
++- Pinebook Pro
++- Pinephone Pro
++
++Features in addition to mainline:
++
++- [Orange Pi One/PC/PC2] More aggressive OPPs for CPU
++- [All] Mark one of DRM planes as a cursor plane, speeding up Xorg based desktop with modesetting driver
++- [Orange Pi One/PC/PC2] Configure on-board micro-switches to perform system power off function
++- [Orange Pi One/PC/PC2/3] HDMI audio
++- [Orange Pi 3] Ethernet
++- [TBS A711] HM5065 (back camera) / GC2145 (front camera)
++- [PinePhone] WiFi, Bluetooth, Audio, Modem power, HDMI out over USB-C, USB-C support, cameras, PMIC improvements, power management, fixes here and there
++- [PocketBook Touch Lux 3] Display and Touchscreen support
++- [Pinephone Pro] Everything
++
++Pre-built u-boot and kernels are available at https://xff.cz/kernels/
++
++You may need some firmware files for some part of the functionality. Those are
++available at: https://megous.com/git/linux-firmware
++
++If you want to reproduce my pre-built kernels exactly, you'll need to uncomment
++CONFIG_EXTRA_FIRMWARE_DIR and CONFIG_EXTRA_FIRMWARE in the defconfigs, and
++point CONFIG_EXTRA_FIRMWARE_DIR to a directory on your computer where the
++clone of https://megous.com/git/linux-firmware resides.
++
++You can also leave those two config options commented out, and copy the contents
++of https://megous.com/git/linux-firmware to /lib/firmware/ on the target device.
++
++You can use this kernel to run a desktop environment on Orange Pi SBCs,
++Arch Linux on your Pinephone, or to have a completely opensource OS on
++a Pocketbook e-ink book reader.
++
++Have fun!
++
++
++Build instructions
++------------------
++
++These are rudimentary instructions and you need to understand what you're doing.
++These are just core steps required to build the ATF/u-boot/kernel. Downloading,
++verifying, renaming to correct directories is not described or mentioned. You
++should be able to infer missing necessary steps yourself for your particular needs.
++
++Get necessary toolchains from:
++
++- https://releases.linaro.org/components/toolchain/binaries/latest/aarch64-linux-gnu/ for 64bit Orange Pi PC2 and Orange Pi 3, PinePhone
++- https://releases.linaro.org/components/toolchain/binaries/latest/arm-linux-gnueabihf/ for 32bit Orange Pis, Pocketbook, TBS tablet
++
++Extract toolchains and prepare the environment:
++
++    CWD=`pwd`
++    OUT=$CWD/builds
++    SRC=$CWD/u-boot
++    export PATH="$PATH:$CWD/Toolchains/arm/bin:$CWD/Toolchains/aarch64/bin"
++
++For Orange Pi PC2, Orange Pi 3 or PinePhone:
++
++    export CROSS_COMPILE=aarch64-linux-gnu-
++    export KBUILD_OUTPUT=$OUT/.tmp/uboot-pc2
++    rm -rf "$KBUILD_OUTPUT"
++    mkdir -p $KBUILD_OUTPUT $OUT/pc2
++
++Get and build ATF from https://github.com/ARM-software/arm-trusted-firmware:
++
++    make -C "$CWD/arm-trusted-firmware" PLAT=sun50i_a64 DEBUG=1 bl31
++    cp "$CWD/arm-trusted-firmware/build/sun50i_a64/debug/bl31.bin" "$KBUILD_OUTPUT"
++
++Use sun50i_a64 for Orange Pi PC2 or PinePhone and sun50i_h6 for Orange Pi 3.
++
++Build u-boot from https://megous.com/git/u-boot/ (opi-v2020.04 branch) with appropriate
++defconfig (orangepi_one_defconfig, orangepi_pc2_defconfig, orangepi_pc_defconfig, orangepi_3_defconfig, tbs_a711_defconfig, pinephone_defconfig).
++
++My u-boot branch already has all the necessary patches integrated and is configured for quick u-boot/kernel startup.
++
++    make -C u-boot orangepi_pc2_defconfig
++    make -C u-boot -j5
++    
++    cp $KBUILD_OUTPUT/.config $OUT/pc2/uboot.config
++    cat $KBUILD_OUTPUT/{spl/sunxi-spl.bin,u-boot.itb} > $OUT/pc2/uboot.bin
++
++Get kernel from this repository and checkout the latest orange-pi-5.18 branch.
++
++Build the kernel for 64-bit boards:
++
++    export ARCH=arm64
++    export CROSS_COMPILE=aarch64-linux-gnu-
++    export KBUILD_OUTPUT=$OUT/.tmp/linux-arm64
++    mkdir -p $KBUILD_OUTPUT $OUT/pc2
++
++    make -C linux orangepi_defconfig
++    # or make -C linux pocketbook_touch_lux_3_defconfig
++    # or make -C linux tbs_a711_defconfig
++    make -C linux -j5 clean
++    make -C linux -j5 Image dtbs
++
++    cp -f $KBUILD_OUTPUT/arch/arm64/boot/Image $OUT/pc2/
++    cp -f $KBUILD_OUTPUT/.config $OUT/pc2/linux.config
++    cp -f $KBUILD_OUTPUT/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dtb $OUT/pc2/board.dtb
++
++Build the kernel for 32-bit boards:
++
++    export ARCH=arm
++    export CROSS_COMPILE=arm-linux-gnueabihf-
++    export KBUILD_OUTPUT=$OUT/.tmp/linux-arm
++    mkdir -p $KBUILD_OUTPUT $OUT/pc
++
++    make orangepi_defconfig
++    # or make pinephone_defconfig
++    make -C linux orangepi_defconfig
++    make -C linux -j5 clean
++    make -C linux -j5 zImage dtbs
++    
++    cp -f $KBUILD_OUTPUT/arch/arm/boot/zImage $OUT/pc/
++    cp -f $KBUILD_OUTPUT/.config $OUT/pc/linux.config
++    cp -f $KBUILD_OUTPUT/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb $OUT/pc/board.dtb
++    # Or use sun8i-h3-orangepi-one.dtb for Orange Pi One
++
++
++PinePhone
++---------
++
++I don't run u-boot on PinePhone, so my pre-built kernel packages don't come
++with u-boot built for PinePhone.
++
++
++Kernel lockup issues
++--------------------
++
++*If you're getting lockups on boot or later during thermal regulation,
++you're missing an u-boot patch.*
++
++This patch is necessary to run this kernel!
++
++These lockups are caused by improper NKMP clock factors selection
++in u-boot for PLL_CPUX. (M divider should not be used. P divider
++should be used only for frequencies below 240MHz.)
++
++This patch for u-boot fixes it:
++
++  0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
++
++Kernel side is already fixed in this kernel tree.
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Add-support-for-my-private-Sapomat-device.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Add-support-for-my-private-Sapomat-device.patch
new file mode 100644
index 000000000000..6a9ea750e9ae
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Add-support-for-my-private-Sapomat-device.patch
@@ -0,0 +1,66 @@
+From a923b3a1fb29b86a95cd08b37b85d608ffec4a85 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 18 Aug 2017 13:56:06 +0200
+Subject: Add support for my private Sapomat device
+
+---
+ arch/arm/boot/dts/allwinner/Makefile          |  1 +
+ .../sun8i-h3-orangepi-pc-sapomat.dts          | 34 +++++++++++++++++++
+ 2 files changed, 35 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts
+
+diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
+index cd0d044882cf..54b156fca9bf 100644
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -238,6 +238,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-h3-orangepi-lite.dtb \
+ 	sun8i-h3-orangepi-one.dtb \
+ 	sun8i-h3-orangepi-pc.dtb \
++	sun8i-h3-orangepi-pc-sapomat.dtb \
+ 	sun8i-h3-orangepi-pc-plus.dtb \
+ 	sun8i-h3-orangepi-plus.dtb \
+ 	sun8i-h3-orangepi-plus2e.dtb \
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts
+new file mode 100644
+index 000000000000..55c82d5fb63f
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts
+@@ -0,0 +1,34 @@
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include "sun8i-h3-orangepi-pc.dts"
++
++/ {
++	model = "Xunlong Orange Pi PC Sapomat";
++
++	sapomat_gpio_keys {
++		compatible = "gpio-keys-polled";
++		poll-interval = <50>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&sapomat_btn_pins>;
++
++		red_btn {
++			label = "Red Button";
++			linux,code = <BTN_4>;
++			gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; /* PC4 */
++		};
++
++		green_btn {
++			label = "Green Button";
++			linux,code = <BTN_5>;
++			gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
++		};
++	};
++};
++
++&pio {
++	sapomat_btn_pins: btn_pins@0 {
++		pins = "PC4", "PC7";
++		function = "gpio_in";
++		bias-pull-up;
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Defconfigs-for-all-my-devices.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Defconfigs-for-all-my-devices.patch
new file mode 100644
index 000000000000..59e78eb5bd91
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Defconfigs-for-all-my-devices.patch
@@ -0,0 +1,3989 @@
+From 4fb1ad82377e12fee3e5eef688598a1d61231b00 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 16 Sep 2019 00:35:50 +0200
+Subject: Defconfigs for all my devices
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/configs/orangepi_defconfig           |  694 +++++++++++
+ .../configs/pocketbook_touch_lux_3_defconfig  |  416 +++++++
+ arch/arm/configs/tbs_a711_defconfig           |  528 +++++++++
+ arch/arm64/configs/orangepi_defconfig         | 1038 +++++++++++++++++
+ arch/arm64/configs/pinephone_defconfig        |  651 +++++++++++
+ .../configs/pinephone_multidist_defconfig     |  602 ++++++++++
+ 6 files changed, 3929 insertions(+)
+ create mode 100644 arch/arm/configs/orangepi_defconfig
+ create mode 100644 arch/arm/configs/pocketbook_touch_lux_3_defconfig
+ create mode 100644 arch/arm/configs/tbs_a711_defconfig
+ create mode 100644 arch/arm64/configs/orangepi_defconfig
+ create mode 100644 arch/arm64/configs/pinephone_defconfig
+ create mode 100644 arch/arm64/configs/pinephone_multidist_defconfig
+
+diff --git a/arch/arm/configs/orangepi_defconfig b/arch/arm/configs/orangepi_defconfig
+new file mode 100644
+index 000000000000..2ebd59970d3b
+--- /dev/null
++++ b/arch/arm/configs/orangepi_defconfig
+@@ -0,0 +1,694 @@
++CONFIG_KERNEL_LZ4=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_BOOT_CONFIG=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_BCM=y
++CONFIG_ARCH_BCM2835=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_MACH_SUN9I is not set
++CONFIG_ARM_LPAE=y
++CONFIG_ARM_ERRATA_814220=y
++CONFIG_SMP=y
++CONFIG_SCHED_MC=y
++CONFIG_MCPM=y
++CONFIG_NR_CPUS=8
++CONFIG_HOTPLUG_CPU=y
++CONFIG_HZ_300=y
++CONFIG_HIGHMEM=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_ARCH_FORCE_MAX_ORDER=11
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
++CONFIG_ARM_RASPBERRYPI_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++# CONFIG_SUSPEND is not set
++CONFIG_PM=y
++CONFIG_APM_EMULATION=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_NET_KEY=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_NET_IPIP=y
++CONFIG_IP_MROUTE=y
++CONFIG_SYN_COOKIES=y
++CONFIG_INET_UDP_DIAG=y
++CONFIG_INET_RAW_DIAG=y
++CONFIG_INET_DIAG_DESTROY=y
++CONFIG_IPV6_MIP6=y
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_ACCT=y
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_FTP=y
++CONFIG_NF_CONNTRACK_H323=y
++CONFIG_NF_CONNTRACK_IRC=y
++CONFIG_NF_CONNTRACK_NETBIOS_NS=y
++CONFIG_NF_CONNTRACK_SNMP=y
++CONFIG_NF_CONNTRACK_PPTP=y
++CONFIG_NF_CONNTRACK_SIP=y
++CONFIG_NF_CONNTRACK_TFTP=y
++CONFIG_NF_CT_NETLINK=y
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=y
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=y
++CONFIG_NFT_CT=y
++CONFIG_NFT_CONNLIMIT=y
++CONFIG_NFT_LOG=y
++CONFIG_NFT_LIMIT=y
++CONFIG_NFT_MASQ=y
++CONFIG_NFT_REDIR=y
++CONFIG_NFT_NAT=y
++CONFIG_NFT_TUNNEL=y
++CONFIG_NFT_QUEUE=y
++CONFIG_NFT_QUOTA=y
++CONFIG_NFT_REJECT=y
++CONFIG_NFT_HASH=y
++CONFIG_NFT_FIB_INET=y
++CONFIG_NFT_SOCKET=y
++CONFIG_NFT_OSF=y
++CONFIG_NFT_TPROXY=y
++CONFIG_NFT_DUP_NETDEV=y
++CONFIG_NFT_FWD_NETDEV=y
++CONFIG_NFT_FIB_NETDEV=y
++CONFIG_NFT_REJECT_NETDEV=y
++CONFIG_NF_FLOW_TABLE_INET=y
++CONFIG_NF_FLOW_TABLE=y
++CONFIG_IP_SET=y
++CONFIG_IP_SET_BITMAP_IP=y
++CONFIG_IP_SET_BITMAP_IPMAC=y
++CONFIG_IP_SET_BITMAP_PORT=y
++CONFIG_IP_SET_HASH_IP=y
++CONFIG_IP_SET_HASH_IPMARK=y
++CONFIG_IP_SET_HASH_IPPORT=y
++CONFIG_IP_SET_HASH_IPPORTIP=y
++CONFIG_IP_SET_HASH_IPPORTNET=y
++CONFIG_IP_SET_HASH_IPMAC=y
++CONFIG_IP_SET_HASH_MAC=y
++CONFIG_IP_SET_HASH_NETPORTNET=y
++CONFIG_IP_SET_HASH_NET=y
++CONFIG_IP_SET_HASH_NETNET=y
++CONFIG_IP_SET_HASH_NETPORT=y
++CONFIG_IP_SET_HASH_NETIFACE=y
++CONFIG_IP_SET_LIST_SET=y
++CONFIG_NFT_DUP_IPV4=y
++CONFIG_NFT_FIB_IPV4=y
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_NFT_DUP_IPV6=y
++CONFIG_NFT_FIB_IPV6=y
++CONFIG_NF_LOG_IPV6=y
++CONFIG_NF_TABLES_BRIDGE=y
++CONFIG_NFT_BRIDGE_REJECT=y
++CONFIG_IP_SCTP=y
++CONFIG_SCTP_COOKIE_HMAC_SHA1=y
++CONFIG_TIPC=y
++CONFIG_L2TP=y
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=y
++CONFIG_BRIDGE=y
++CONFIG_BRIDGE_VLAN_FILTERING=y
++CONFIG_VLAN_8021Q=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_BPF=y
++CONFIG_NET_CLS_MATCHALL=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_NET_TC_SKB_EXT=y
++CONFIG_BT=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_HS=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIBTSDIO=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_NFC=y
++CONFIG_NFC_DIGITAL=y
++CONFIG_NFC_NCI=y
++CONFIG_NFC_NXP_NCI=y
++CONFIG_NFC_NXP_NCI_I2C=y
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s edid/asus.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_RASPBERRYPI_FIRMWARE=y
++CONFIG_GNSS=y
++CONFIG_GNSS_SIRF_SERIAL=y
++CONFIG_GNSS_UBX_SERIAL=y
++CONFIG_OF_OVERLAY=y
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_INTEGRITY=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=y
++CONFIG_TUN=y
++CONFIG_VETH=y
++# CONFIG_NET_VENDOR_ALACRITECH is not set
++# CONFIG_NET_VENDOR_ALLWINNER is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AQUANTIA is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CADENCE is not set
++# CONFIG_NET_VENDOR_CAVIUM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_NET_VENDOR_CORTINA is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FARADAY is not set
++# CONFIG_NET_VENDOR_GOOGLE is not set
++# CONFIG_NET_VENDOR_HISILICON is not set
++# CONFIG_NET_VENDOR_HUAWEI is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MELLANOX is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_MICROSEMI is not set
++# CONFIG_NET_VENDOR_NI is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_NET_VENDOR_PENSANDO is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SOLARFLARE is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_SOCIONEXT is not set
++CONFIG_STMMAC_ETH=y
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_NET_VENDOR_XILINX is not set
++CONFIG_LED_TRIGGER_PHY=y
++CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
++CONFIG_PPP=y
++CONFIG_PPP_BSDCOMP=y
++CONFIG_PPP_DEFLATE=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=y
++CONFIG_PPPOL2TP=y
++CONFIG_PPP_ASYNC=y
++CONFIG_PPP_SYNC_TTY=y
++CONFIG_USB_RTL8152=y
++CONFIG_USB_USBNET=y
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=y
++# CONFIG_USB_NET_CDC_NCM is not set
++CONFIG_USB_NET_SMSC95XX=y
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_BRCMFMAC=y
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++CONFIG_RT2X00=y
++CONFIG_RT2800USB=y
++# CONFIG_RT2800USB_RT35XX is not set
++CONFIG_RT2800USB_RT53XX=y
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_ADC=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EDT_FT5X06=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_BCM2835AUX=y
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_HW_RANDOM=y
++# CONFIG_HW_RANDOM_IPROC_RNG200 is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_BCM2835=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_I2C_SUN6I_P2WI=y
++CONFIG_SPI=y
++CONFIG_SPI_BCM2835=y
++CONFIG_SPI_BCM2835AUX=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SUN6I=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_POWER_RESET=y
++CONFIG_POWER_RESET_GPIO=y
++CONFIG_POWER_RESET_GPIO_RESTART=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++CONFIG_SENSORS_RASPBERRYPI_HWMON=y
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_BCM2835_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_BCM2835_WDT=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_SY8106A=y
++CONFIG_RC_CORE=y
++CONFIG_BPF_LIRC_MODE2=y
++CONFIG_LIRC=y
++CONFIG_RC_DECODERS=y
++CONFIG_IR_JVC_DECODER=y
++CONFIG_IR_MCE_KBD_DECODER=y
++CONFIG_IR_NEC_DECODER=y
++CONFIG_IR_RC5_DECODER=y
++CONFIG_IR_RC6_DECODER=y
++CONFIG_IR_SANYO_DECODER=y
++CONFIG_IR_SHARP_DECODER=y
++CONFIG_IR_SONY_DECODER=y
++CONFIG_IR_XMP_DECODER=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=y
++CONFIG_IR_SUNXI=y
++CONFIG_MEDIA_CEC_RC=y
++CONFIG_MEDIA_CEC_SUPPORT=y
++CONFIG_MEDIA_SUPPORT=y
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
++CONFIG_VIDEO_SUN6I_CSI=y
++CONFIG_VIDEO_SUN8I_DEINTERLACE=y
++CONFIG_VIDEO_SUN8I_ROTATE=y
++# CONFIG_VIDEO_IR_I2C is not set
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_SUN4I_HDMI_CEC=y
++# CONFIG_DRM_SUN6I_DSI is not set
++CONFIG_DRM_PANEL_LVDS=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_VC4=y
++CONFIG_DRM_VC4_HDMI_CEC=y
++CONFIG_DRM_LIMA=y
++CONFIG_FB=y
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_HRTIMER=y
++CONFIG_SND_SEQUENCER=y
++CONFIG_SND_SEQUENCER_OSS=y
++CONFIG_SND_DUMMY=y
++CONFIG_SND_ALOOP=y
++# CONFIG_SND_SPI is not set
++CONFIG_SND_USB_AUDIO=y
++CONFIG_SND_SOC=y
++CONFIG_SND_BCM2835_SOC_I2S=y
++CONFIG_SND_SUN4I_CODEC=y
++CONFIG_SND_SUN8I_CODEC=y
++CONFIG_SND_SUN8I_CODEC_ANALOG=y
++CONFIG_SND_SUN4I_I2S=y
++CONFIG_SND_SUN4I_SPDIF=y
++CONFIG_SND_SOC_SPDIF=y
++CONFIG_SND_SIMPLE_CARD=y
++CONFIG_SND_AUDIO_GRAPH_CARD=y
++CONFIG_HIDRAW=y
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=y
++CONFIG_USB_PRINTER=y
++CONFIG_USB_WDM=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_UAS=y
++CONFIG_USBIP_CORE=y
++CONFIG_USBIP_VHCI_HCD=y
++CONFIG_USBIP_HOST=y
++CONFIG_USBIP_VUDC=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SUNXI=y
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_CH341=y
++CONFIG_USB_SERIAL_CP210X=y
++CONFIG_USB_SERIAL_FTDI_SIO=y
++CONFIG_USB_SERIAL_PL2303=y
++CONFIG_USB_SERIAL_OPTION=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_GADGET=y
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=y
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_CDC_COMPOSITE=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_MMC_BCM2835=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_SYSFS is not set
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_AC100=y
++CONFIG_RTC_DRV_SUNXI=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_BCM2835=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=y
++# CONFIG_BCM_VIDEOCORE is not set
++CONFIG_CLK_RASPBERRYPI=y
++# CONFIG_CLK_SUNXI_CLOCKS is not set
++# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
++# CONFIG_SUN4I_A10_CCU is not set
++# CONFIG_SUN5I_CCU is not set
++# CONFIG_SUN6I_A31_CCU is not set
++# CONFIG_SUN8I_A23_CCU is not set
++# CONFIG_SUN8I_A33_CCU is not set
++# CONFIG_SUN8I_V3S_CCU is not set
++# CONFIG_SUN8I_R40_CCU is not set
++CONFIG_MAILBOX=y
++CONFIG_BCM2835_MBOX=y
++# CONFIG_SUN6I_MSGBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_RASPBERRYPI_POWER=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_CONFIGFS=y
++CONFIG_BMA180=y
++CONFIG_AXP20X_ADC=y
++CONFIG_LTR501=y
++CONFIG_AK8975=y
++CONFIG_PWM=y
++CONFIG_PWM_BCM2835=y
++CONFIG_PWM_SUN4I=y
++CONFIG_RESET_RASPBERRYPI=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_XFS_FS=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_OVERLAY_FS=y
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_VFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_ECRYPT_FS=y
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V2 is not set
++# CONFIG_NFS_V3 is not set
++CONFIG_NFS_V4=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_2=y
++CONFIG_NFS_FSCACHE=y
++# CONFIG_NFS_V4_2_READ_PLUS is not set
++CONFIG_NFSD=y
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++CONFIG_CIFS=y
++# CONFIG_CIFS_STATS2 is not set
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++# CONFIG_CIFS_DEBUG is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_AES_TI=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_BLAKE2B=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_GHASH_ARM_CE=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=y
++CONFIG_CRYPTO_SHA1_ARM_CE=y
++CONFIG_CRYPTO_SHA2_ARM_CE=y
++CONFIG_CRYPTO_SHA512_ARM=y
++CONFIG_CRYPTO_AES_ARM=y
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRYPTO_AES_ARM_CE=y
++CONFIG_CRYPTO_CRC32_ARM_CE=y
++CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=y
++CONFIG_CRYPTO_DEV_SUN8I_SS=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=128
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DEBUG_KERNEL=y
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
++CONFIG_WQ_WATCHDOG=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_FTRACE is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm/configs/pocketbook_touch_lux_3_defconfig b/arch/arm/configs/pocketbook_touch_lux_3_defconfig
+new file mode 100644
+index 000000000000..2d5db37e86cb
+--- /dev/null
++++ b/arch/arm/configs/pocketbook_touch_lux_3_defconfig
+@@ -0,0 +1,416 @@
++CONFIG_KERNEL_LZ4=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_HZ_PERIODIC=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_BOOT_CONFIG=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_MACH_SUN4I is not set
++# CONFIG_MACH_SUN6I is not set
++# CONFIG_MACH_SUN7I is not set
++# CONFIG_MACH_SUN8I is not set
++# CONFIG_MACH_SUN9I is not set
++CONFIG_ARM_ERRATA_430973=y
++CONFIG_ARM_ERRATA_814220=y
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_ARM_PSCI=y
++CONFIG_HZ_1000=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_ARCH_FORCE_MAX_ORDER=11
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_BLK_DEV_INTEGRITY=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=m
++CONFIG_XFRM_SUB_POLICY=y
++CONFIG_INET=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_DIAG is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_CONNLIMIT=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_MASQ=m
++CONFIG_NFT_REDIR=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_TUNNEL=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_QUOTA=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_SOCKET=m
++CONFIG_NFT_OSF=m
++CONFIG_NFT_DUP_NETDEV=m
++CONFIG_NFT_FWD_NETDEV=m
++CONFIG_NF_FLOW_TABLE_INET=m
++CONFIG_NF_FLOW_TABLE=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPMARK=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_IPMAC=m
++CONFIG_IP_SET_HASH_MAC=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_NF_SOCKET_IPV4=y
++CONFIG_NF_TABLES_IPV4=y
++CONFIG_NFT_DUP_IPV4=m
++CONFIG_NFT_FIB_IPV4=m
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++CONFIG_NF_REJECT_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_MAC80211_DEBUGFS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s rtlwifi/rtl8188eufw.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++# CONFIG_FW_CACHE is not set
++CONFIG_SUNXI_RSB=y
++CONFIG_MTD=y
++# CONFIG_MTD_OF_PARTS is not set
++CONFIG_MTD_BLOCK_RO=y
++CONFIG_MTD_SPI_NOR=m
++CONFIG_OF_OVERLAY=y
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=m
++CONFIG_TUN=y
++# CONFIG_ETHERNET is not set
++# CONFIG_USB_NET_DRIVERS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_RTL_CARDS is not set
++CONFIG_RTL8XXXU=m
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_SILABS is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
++CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_AXP20X_PEK=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_SPI=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++CONFIG_SENSORS_NTC_THERMISTOR=y
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_MFD_SYSCON=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER_OF=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_TP65185X=y
++CONFIG_DRM=y
++CONFIG_FB=y
++CONFIG_FB_SUN5I_EINK=m
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++# CONFIG_HID is not set
++# CONFIG_USB_HID is not set
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=m
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=m
++CONFIG_USB_LEDS_TRIGGER_USBPORT=m
++CONFIG_USB_EHCI_HCD=m
++CONFIG_USB_EHCI_HCD_PLATFORM=m
++CONFIG_USB_OHCI_HCD=m
++CONFIG_USB_OHCI_HCD_PLATFORM=m
++CONFIG_USB_WDM=m
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_SUNXI=m
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_NOP_USB_XCEIV=m
++CONFIG_USB_GADGET=m
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_CDC_COMPOSITE=m
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_SYSFS is not set
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_PCF8563=y
++CONFIG_DMADEVICES=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set
++# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set
++# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PM_DEVFREQ=y
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_CONFIGFS=y
++CONFIG_BMA180=y
++CONFIG_AXP20X_ADC=y
++CONFIG_SUN4I_GPADC=m
++CONFIG_LTR501=y
++CONFIG_AK8975=y
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_VFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++# CONFIG_MISC_FILESYSTEMS is not set
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_BIG_KEYS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_ECDH=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_AES_TI=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_ESSIV=y
++CONFIG_CRYPTO_BLAKE2B=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_CURVE25519_NEON=y
++CONFIG_CRYPTO_GHASH_ARM_CE=y
++CONFIG_CRYPTO_POLY1305_ARM=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=y
++CONFIG_CRYPTO_SHA1_ARM_CE=y
++CONFIG_CRYPTO_SHA2_ARM_CE=y
++CONFIG_CRYPTO_SHA512_ARM=y
++CONFIG_CRYPTO_AES_ARM=y
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRYPTO_AES_ARM_CE=y
++CONFIG_CRYPTO_CHACHA20_NEON=y
++CONFIG_CRYPTO_CRC32_ARM_CE=y
++CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++CONFIG_CRYPTO_LIB_CURVE25519=y
++CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC_ITU_T=y
++CONFIG_LIBCRC32C=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=128
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DEBUG_FS=y
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm/configs/tbs_a711_defconfig b/arch/arm/configs/tbs_a711_defconfig
+new file mode 100644
+index 000000000000..f28899833bbf
+--- /dev/null
++++ b/arch/arm/configs/tbs_a711_defconfig
+@@ -0,0 +1,528 @@
++CONFIG_KERNEL_LZ4=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_MACH_SUN9I is not set
++CONFIG_ARM_ERRATA_814220=y
++CONFIG_SMP=y
++CONFIG_SCHED_MC=y
++CONFIG_MCPM=y
++CONFIG_NR_CPUS=8
++CONFIG_HZ_1000=y
++CONFIG_HIGHMEM=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_ARCH_FORCE_MAX_ORDER=11
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_PM_ADVANCED_DEBUG=y
++CONFIG_APM_EMULATION=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_BLK_DEV_INTEGRITY=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++# CONFIG_BFQ_GROUP_IOSCHED is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_INET=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_SYN_COOKIES=y
++CONFIG_INET_DIAG=m
++CONFIG_INET_UDP_DIAG=m
++CONFIG_INET_RAW_DIAG=m
++# CONFIG_IPV6_SIT is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=m
++CONFIG_NETFILTER_NETLINK_ACCT=m
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_INET=y
++CONFIG_NFT_NUMGEN=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_CONNLIMIT=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_MASQ=m
++CONFIG_NFT_REDIR=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_TUNNEL=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_QUOTA=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_FIB_INET=m
++CONFIG_NFT_SOCKET=m
++CONFIG_NFT_OSF=m
++CONFIG_NF_FLOW_TABLE_INET=m
++CONFIG_NF_FLOW_TABLE=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPMARK=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_IPMAC=m
++CONFIG_IP_SET_HASH_MAC=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_NFT_DUP_IPV4=m
++CONFIG_NFT_FIB_IPV4=m
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=m
++CONFIG_NF_LOG_IPV4=m
++CONFIG_NFT_DUP_IPV6=m
++CONFIG_NFT_FIB_IPV6=m
++CONFIG_NF_LOG_IPV6=m
++CONFIG_NF_TABLES_BRIDGE=m
++CONFIG_NFT_BRIDGE_REJECT=m
++CONFIG_BRIDGE=m
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_MATCHALL=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_BT=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++CONFIG_BT_HS=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIBTSDIO=m
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_CFG80211=y
++# CONFIG_CFG80211_DEFAULT_PS is not set
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_NFC=m
++CONFIG_NFC_DIGITAL=m
++CONFIG_NFC_NCI=m
++CONFIG_NFC_NXP_NCI=m
++CONFIG_NFC_NXP_NCI_I2C=m
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s brcm/brcmfmac43362-sdio.bin brcm/brcmfmac43362-sdio.txt brcm/BCM20702A1.hcd hm5065-af.bin hm5065-init.bin brcm/brcmfmac43362-sdio.tbs-biometrics,a711.txt"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++# CONFIG_FW_CACHE is not set
++CONFIG_ARM_SCPI_PROTOCOL=m
++CONFIG_GNSS=y
++CONFIG_GNSS_SIRF_SERIAL=y
++CONFIG_GNSS_UBX_SERIAL=y
++CONFIG_OF_OVERLAY=y
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_MODEM_POWER=m
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++# CONFIG_ETHERNET is not set
++CONFIG_PPP=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=m
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++# CONFIG_USB_NET_DRIVERS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_BRCMFMAC=m
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EDT_FT5X06=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_SPI=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SUN6I=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AC100=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_SYSCON=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_MEDIA_SUPPORT=m
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_VIDEO_ADV_DEBUG=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
++CONFIG_VIDEO_SUN6I_CSI=m
++CONFIG_VIDEO_SUN8I_DEINTERLACE=m
++CONFIG_VIDEO_SUN8I_ROTATE=m
++CONFIG_VIDEO_HM5065=m
++CONFIG_VIDEO_GC2145=m
++CONFIG_DRM=y
++CONFIG_DRM_SUN4I=y
++# CONFIG_DRM_SUN4I_HDMI is not set
++# CONFIG_DRM_SUN4I_BACKEND is not set
++# CONFIG_DRM_SUN6I_DSI is not set
++# CONFIG_DRM_SUN8I_DW_HDMI is not set
++CONFIG_DRM_PANEL_LVDS=y
++CONFIG_FB=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_SOUND=m
++CONFIG_SND=m
++CONFIG_SND_HRTIMER=m
++# CONFIG_SND_SUPPORT_OLD_API is not set
++CONFIG_SND_DEBUG=y
++CONFIG_SND_DEBUG_VERBOSE=y
++# CONFIG_SND_DRIVERS is not set
++# CONFIG_SND_ARM is not set
++# CONFIG_SND_SPI is not set
++# CONFIG_SND_USB is not set
++CONFIG_SND_SOC=m
++CONFIG_SND_SUN8I_CODEC=m
++CONFIG_SND_AC100_CODEC=m
++CONFIG_SND_SUN4I_I2S=m
++CONFIG_SND_SOC_BT_SCO=m
++CONFIG_SND_SOC_EC25=m
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_HIDRAW=y
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=m
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=m
++CONFIG_USB_LEDS_TRIGGER_USBPORT=m
++CONFIG_USB_EHCI_HCD=m
++CONFIG_USB_EHCI_HCD_PLATFORM=m
++CONFIG_USB_OHCI_HCD=m
++CONFIG_USB_OHCI_HCD_PLATFORM=m
++CONFIG_USB_ACM=m
++CONFIG_USB_WDM=m
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_SUNXI=m
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_NOP_USB_XCEIV=m
++CONFIG_USB_GADGET=m
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_ETH=m
++CONFIG_USB_ETH_EEM=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_AXP20X=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_BACKLIGHT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_SYSFS is not set
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_AC100=y
++# CONFIG_RTC_DRV_SUN6I is not set
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=m
++# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
++# CONFIG_SUN4I_A10_CCU is not set
++# CONFIG_SUN5I_CCU is not set
++# CONFIG_SUN6I_A31_CCU is not set
++# CONFIG_SUN8I_A23_CCU is not set
++# CONFIG_SUN8I_A33_CCU is not set
++# CONFIG_SUN8I_V3S_CCU is not set
++# CONFIG_SUN8I_R40_CCU is not set
++CONFIG_MAILBOX=y
++# CONFIG_IOMMU_SUPPORT is not set
++# CONFIG_ARM_SCPI_POWER_DOMAIN is not set
++CONFIG_IIO=y
++CONFIG_IIO_KFIFO_BUF=y
++CONFIG_IIO_CONFIGFS=y
++CONFIG_BMA180=m
++CONFIG_AXP20X_ADC=y
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++# CONFIG_MISC_FILESYSTEMS is not set
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_ECDH=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_AES_TI=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_BLAKE2B=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_DEFLATE=m
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_LZ4HC=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=m
++CONFIG_CRYPTO_USER_API_SKCIPHER=m
++CONFIG_CRYPTO_USER_API_RNG=m
++CONFIG_CRYPTO_USER_API_AEAD=m
++CONFIG_CRYPTO_CURVE25519_NEON=y
++CONFIG_CRYPTO_POLY1305_ARM=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=y
++CONFIG_CRYPTO_SHA1_ARM_CE=y
++CONFIG_CRYPTO_SHA2_ARM_CE=y
++CONFIG_CRYPTO_SHA512_ARM=y
++CONFIG_CRYPTO_AES_ARM=y
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRYPTO_AES_ARM_CE=y
++CONFIG_CRYPTO_CRC32_ARM_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=m
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=m
++CONFIG_CRYPTO_DEV_SUN8I_SS=m
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC_ITU_T=y
++CONFIG_LIBCRC32C=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DEBUG_KERNEL=y
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
++CONFIG_WQ_WATCHDOG=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_RCU_TRACE is not set
++CONFIG_BOOTTIME_TRACING=y
++CONFIG_FUNCTION_TRACER=y
++# CONFIG_UPROBE_EVENTS is not set
++CONFIG_UNWINDER_FRAME_POINTER=y
++CONFIG_DEBUG_LL=y
++CONFIG_EARLY_PRINTK=y
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm64/configs/orangepi_defconfig b/arch/arm64/configs/orangepi_defconfig
+new file mode 100644
+index 000000000000..82f1448bbf14
+--- /dev/null
++++ b/arch/arm64/configs/orangepi_defconfig
+@@ -0,0 +1,1038 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_WATCH_QUEUE=y
++CONFIG_GENERIC_IRQ_DEBUGFS=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_BPF_JIT_ALWAYS_ON=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_PREEMPT_VOLUNTARY=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_PSI=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=20
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=14
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_BPF=y
++CONFIG_CGROUP_MISC=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++CONFIG_RELAY=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_BOOT_CONFIG=y
++CONFIG_KALLSYMS_ALL=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_ARCH_ROCKCHIP=y
++# CONFIG_ARM64_ERRATUM_832075 is not set
++# CONFIG_ARM64_ERRATUM_834220 is not set
++# CONFIG_ARM64_ERRATUM_1542419 is not set
++# CONFIG_ARM64_ERRATUM_1508412 is not set
++# CONFIG_ARM64_ERRATUM_2051678 is not set
++# CONFIG_ARM64_ERRATUM_2077057 is not set
++# CONFIG_ARM64_ERRATUM_2658417 is not set
++# CONFIG_ARM64_ERRATUM_2054223 is not set
++# CONFIG_ARM64_ERRATUM_2067961 is not set
++# CONFIG_ARM64_ERRATUM_2441009 is not set
++# CONFIG_ARM64_ERRATUM_2645198 is not set
++# CONFIG_ARM64_ERRATUM_2966298 is not set
++# CONFIG_CAVIUM_ERRATUM_22375 is not set
++# CONFIG_CAVIUM_ERRATUM_23144 is not set
++# CONFIG_CAVIUM_ERRATUM_23154 is not set
++# CONFIG_CAVIUM_ERRATUM_27456 is not set
++# CONFIG_CAVIUM_ERRATUM_30115 is not set
++# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
++# CONFIG_FUJITSU_ERRATUM_010001 is not set
++# CONFIG_HISILICON_ERRATUM_161600802 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
++# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
++# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set
++CONFIG_ARM64_VA_BITS_48=y
++CONFIG_SCHED_MC=y
++CONFIG_SCHED_CLUSTER=y
++CONFIG_NR_CPUS=8
++CONFIG_NUMA=y
++CONFIG_NODES_SHIFT=3
++CONFIG_PARAVIRT=y
++CONFIG_COMPAT=y
++CONFIG_ARM64_PMEM=y
++# CONFIG_ARM64_PTR_AUTH is not set
++# CONFIG_ARM64_AMU_EXTN is not set
++# CONFIG_ARM64_TLB_RANGE is not set
++# CONFIG_ARM64_BTI is not set
++# CONFIG_ARM64_E0PD is not set
++# CONFIG_ARM64_MTE is not set
++# CONFIG_ARM64_EPAN is not set
++# CONFIG_ARM64_SVE is not set
++# CONFIG_EFI is not set
++CONFIG_HIBERNATION=y
++CONFIG_PM_AUTOSLEEP=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
++CONFIG_ARM_SCPI_CPUFREQ=y
++CONFIG_ARM_ROCKCHIP_CPUFREQ=y
++CONFIG_ARM_SCMI_CPUFREQ=y
++CONFIG_VIRTUALIZATION=y
++CONFIG_KVM=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++CONFIG_BLK_CGROUP_IOPRIO=y
++CONFIG_BLK_INLINE_ENCRYPTION=y
++CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_BINFMT_MISC=y
++CONFIG_ZSWAP=y
++CONFIG_ZSWAP_DEFAULT_ON=y
++CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4=y
++CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
++CONFIG_Z3FOLD=y
++CONFIG_ZSMALLOC_STAT=y
++CONFIG_TRANSPARENT_HUGEPAGE=y
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_SYSFS=y
++CONFIG_CMA_AREAS=7
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=y
++CONFIG_XDP_SOCKETS=y
++CONFIG_XDP_SOCKETS_DIAG=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_NET_IPIP=y
++CONFIG_IP_MROUTE=y
++CONFIG_INET_UDP_DIAG=y
++CONFIG_INET_RAW_DIAG=y
++CONFIG_INET_DIAG_DESTROY=y
++CONFIG_IPV6_ROUTER_PREF=y
++CONFIG_IPV6_ROUTE_INFO=y
++CONFIG_IPV6_OPTIMISTIC_DAD=y
++CONFIG_IPV6_MIP6=y
++CONFIG_IPV6_TUNNEL=y
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_HOOK=y
++CONFIG_NETFILTER_NETLINK_ACCT=y
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NF_CONNTRACK_TIMEOUT=y
++CONFIG_NF_CONNTRACK_TIMESTAMP=y
++CONFIG_NF_CONNTRACK_LABELS=y
++CONFIG_NF_CONNTRACK_FTP=y
++CONFIG_NF_CONNTRACK_H323=y
++CONFIG_NF_CONNTRACK_IRC=y
++CONFIG_NF_CONNTRACK_NETBIOS_NS=y
++CONFIG_NF_CONNTRACK_SNMP=y
++CONFIG_NF_CONNTRACK_PPTP=y
++CONFIG_NF_CONNTRACK_SANE=y
++CONFIG_NF_CONNTRACK_SIP=y
++CONFIG_NF_CONNTRACK_TFTP=y
++CONFIG_NF_CT_NETLINK=y
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=y
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=y
++CONFIG_NFT_CT=y
++CONFIG_NFT_FLOW_OFFLOAD=y
++CONFIG_NFT_CONNLIMIT=y
++CONFIG_NFT_LOG=y
++CONFIG_NFT_LIMIT=y
++CONFIG_NFT_MASQ=y
++CONFIG_NFT_REDIR=y
++CONFIG_NFT_NAT=y
++CONFIG_NFT_TUNNEL=y
++CONFIG_NFT_QUEUE=y
++CONFIG_NFT_QUOTA=y
++CONFIG_NFT_REJECT=y
++CONFIG_NFT_HASH=y
++CONFIG_NFT_FIB_INET=y
++CONFIG_NFT_SOCKET=y
++CONFIG_NFT_OSF=y
++CONFIG_NFT_TPROXY=y
++CONFIG_NFT_SYNPROXY=y
++CONFIG_NFT_DUP_NETDEV=y
++CONFIG_NFT_FWD_NETDEV=y
++CONFIG_NFT_FIB_NETDEV=y
++CONFIG_NFT_REJECT_NETDEV=y
++CONFIG_NF_FLOW_TABLE_INET=y
++CONFIG_NF_FLOW_TABLE=y
++CONFIG_IP_SET=y
++CONFIG_IP_SET_BITMAP_IP=y
++CONFIG_IP_SET_BITMAP_IPMAC=y
++CONFIG_IP_SET_BITMAP_PORT=y
++CONFIG_IP_SET_HASH_IP=y
++CONFIG_IP_SET_HASH_IPMARK=y
++CONFIG_IP_SET_HASH_IPPORT=y
++CONFIG_IP_SET_HASH_IPPORTIP=y
++CONFIG_IP_SET_HASH_IPPORTNET=y
++CONFIG_IP_SET_HASH_IPMAC=y
++CONFIG_IP_SET_HASH_MAC=y
++CONFIG_IP_SET_HASH_NETPORTNET=y
++CONFIG_IP_SET_HASH_NET=y
++CONFIG_IP_SET_HASH_NETNET=y
++CONFIG_IP_SET_HASH_NETPORT=y
++CONFIG_IP_SET_HASH_NETIFACE=y
++CONFIG_IP_SET_LIST_SET=y
++CONFIG_NFT_DUP_IPV4=y
++CONFIG_NFT_FIB_IPV4=y
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_IP_NF_ARPTABLES=y
++CONFIG_IP_NF_ARPFILTER=y
++CONFIG_IP_NF_ARP_MANGLE=y
++CONFIG_NFT_DUP_IPV6=y
++CONFIG_NFT_FIB_IPV6=y
++CONFIG_NF_LOG_IPV6=y
++CONFIG_NF_TABLES_BRIDGE=y
++CONFIG_NFT_BRIDGE_META=y
++CONFIG_NFT_BRIDGE_REJECT=y
++CONFIG_NF_CONNTRACK_BRIDGE=y
++CONFIG_IP_SCTP=y
++CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
++CONFIG_SCTP_COOKIE_HMAC_MD5=y
++CONFIG_TIPC=y
++CONFIG_L2TP=y
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=y
++CONFIG_BRIDGE=y
++CONFIG_BRIDGE_VLAN_FILTERING=y
++CONFIG_BRIDGE_MRP=y
++CONFIG_BRIDGE_CFM=y
++CONFIG_VLAN_8021Q=y
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_VLAN_8021Q_MVRP=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_SCH_HFSC=y
++CONFIG_NET_SCH_PRIO=y
++CONFIG_NET_SCH_MULTIQ=y
++CONFIG_NET_SCH_RED=y
++CONFIG_NET_SCH_SFB=y
++CONFIG_NET_SCH_SFQ=y
++CONFIG_NET_SCH_TEQL=y
++CONFIG_NET_SCH_TBF=y
++CONFIG_NET_SCH_CBS=y
++CONFIG_NET_SCH_ETF=y
++CONFIG_NET_SCH_TAPRIO=y
++CONFIG_NET_SCH_GRED=y
++CONFIG_NET_SCH_NETEM=y
++CONFIG_NET_SCH_DRR=y
++CONFIG_NET_SCH_MQPRIO=y
++CONFIG_NET_SCH_CHOKE=y
++CONFIG_NET_SCH_QFQ=y
++CONFIG_NET_SCH_CODEL=y
++CONFIG_NET_SCH_FQ_CODEL=y
++CONFIG_NET_SCH_CAKE=y
++CONFIG_NET_SCH_FQ=y
++CONFIG_NET_SCH_HHF=y
++CONFIG_NET_SCH_PIE=y
++CONFIG_NET_SCH_FQ_PIE=y
++CONFIG_NET_SCH_INGRESS=y
++CONFIG_NET_SCH_ETS=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_U32=y
++CONFIG_CLS_U32_PERF=y
++CONFIG_CLS_U32_MARK=y
++CONFIG_NET_CLS_FLOW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_BPF=y
++CONFIG_NET_CLS_FLOWER=y
++CONFIG_NET_CLS_MATCHALL=y
++CONFIG_NET_EMATCH=y
++CONFIG_NET_EMATCH_CMP=y
++CONFIG_NET_EMATCH_NBYTE=y
++CONFIG_NET_EMATCH_U32=y
++CONFIG_NET_EMATCH_META=y
++CONFIG_NET_EMATCH_TEXT=y
++CONFIG_NET_EMATCH_IPSET=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_GACT_PROB=y
++CONFIG_NETLINK_DIAG=y
++CONFIG_CGROUP_NET_PRIO=y
++CONFIG_BT=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_HS=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIBTUSB=y
++CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_BT_HCIUART_RTL=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_MESH=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_MAC80211_DEBUGFS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_PCI=y
++CONFIG_PCIEPORTBUS=y
++CONFIG_HOTPLUG_PCI_PCIE=y
++CONFIG_PCIEAER=y
++CONFIG_PCIE_DPC=y
++CONFIG_PCIE_PTM=y
++CONFIG_PCI_DEBUG=y
++CONFIG_PCI_REALLOC_ENABLE_AUTO=y
++CONFIG_PCI_STUB=y
++CONFIG_PCI_PF_STUB=y
++CONFIG_PCI_IOV=y
++CONFIG_PCI_PRI=y
++CONFIG_PCI_PASID=y
++CONFIG_HOTPLUG_PCI=y
++CONFIG_PCIE_ROCKCHIP_HOST=y
++CONFIG_PCIE_ROCKCHIP_DW_HOST=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s edid/asus.bin brcm/brcmfmac43456-sdio.bin brcm/brcmfmac43456-sdio.clm_blob brcm/brcmfmac43456-sdio.txt brcm/brcmfmac43456-sdio.pine64,pinebook-pro.txt brcm/BCM4345C5.hcd brcm/brcmfmac43456-sdio.xunlong,orangepi-3.txt anx7688-fw.bin rtl_bt/rtl8723cs_xx_config.bin rtl_bt/rtl8723cs_xx_fw.bin ov5640_af.bin brcm/brcmfmac43455-sdio.bin brcm/brcmfmac43455-sdio.pine64,pinephone-pro.txt brcm/brcmfmac43455-sdio.pine64,pinebook-pro.txt brcm/brcmfmac43455-sdio.clm_blob brcm/BCM4345C0.hcd rockchip/dptx.bin rt2870.bin rtw88/rtw8822c_fw.bin rtw88/rtw8822c_wow_fw.bin rtw89/rtw8852a_fw.bin rtl_nic/rtl8125a-3.fw rtl_nic/rtl8125b-2.fw rtl_nic/rtl8153a-4.fw rtl_nic/rtl8168h-2.fw brcm/brcmfmac43752-pcie.clm_blob brcm/brcmfmac43752-pcie.bin brcm/brcmfmac43752-pcie.txt bes2600/bes2600_factory.txt bes2600/best2002_fw_boot_sdio.bin bes2600/best2002_fw_sdio.bin bes2600/best2002_fw_sdio_btrf.bin bes2600/best2002_fw_sdio_nosignal.bin bes2600/sdd.bin bes2600/factory.bin rtl_bt/rtl8821c_fw.bin rtl_bt/rtl8821c_config.bin rtl_bt/rtl8822b_fw.bin rtl_bt/rtl8822b_config.bin rtw88/rtw8821c_fw.bin rtw88/rtw8822b_fw.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_ARM_SCMI_PROTOCOL=y
++CONFIG_ARM_SCPI_PROTOCOL=y
++CONFIG_GNSS=y
++CONFIG_MTD=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_PARTITIONED_MASTER=y
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_BLK_DEV_NVME=y
++CONFIG_NVME_HWMON=y
++CONFIG_SRAM=y
++CONFIG_PPKB_POWER_MANAGER=y
++CONFIG_MODEM_POWER=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_DWC=y
++# CONFIG_ATA_SFF is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_UEVENT=y
++CONFIG_DM_INTEGRITY=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=y
++CONFIG_TUN=y
++CONFIG_VETH=y
++# CONFIG_NET_VENDOR_ALACRITECH is not set
++# CONFIG_NET_VENDOR_ALLWINNER is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_VENDOR_AQUANTIA is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CADENCE is not set
++# CONFIG_NET_VENDOR_CAVIUM is not set
++# CONFIG_NET_VENDOR_CORTINA is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_GOOGLE is not set
++# CONFIG_NET_VENDOR_HISILICON is not set
++# CONFIG_NET_VENDOR_HUAWEI is not set
++CONFIG_IGB=y
++CONFIG_IGBVF=y
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MELLANOX is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_MICROSEMI is not set
++# CONFIG_NET_VENDOR_NI is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_NET_VENDOR_PENSANDO is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_R8169=y
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SOLARFLARE is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_SOCIONEXT is not set
++CONFIG_STMMAC_ETH=y
++CONFIG_DWMAC_DWC_QOS_ETH=y
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_NET_VENDOR_XILINX is not set
++CONFIG_LED_TRIGGER_PHY=y
++CONFIG_MOTORCOMM_PHY=y
++CONFIG_ROCKCHIP_PHY=y
++CONFIG_MDIO_SUN4I=y
++CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
++CONFIG_PPP=y
++CONFIG_PPP_BSDCOMP=y
++CONFIG_PPP_DEFLATE=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=y
++CONFIG_PPPOE=y
++CONFIG_PPPOL2TP=y
++CONFIG_PPP_ASYNC=y
++CONFIG_PPP_SYNC_TTY=y
++CONFIG_USB_RTL8152=y
++CONFIG_USB_USBNET=y
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=y
++CONFIG_USB_NET_CDC_MBIM=y
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++CONFIG_USB_NET_QMI_WWAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_BRCMFMAC=y
++CONFIG_BRCMFMAC_PCIE=y
++CONFIG_BRCM_TRACING=y
++CONFIG_BRCMDBG=y
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++CONFIG_RT2X00=y
++CONFIG_RT2800USB=y
++# CONFIG_RT2800USB_RT35XX is not set
++CONFIG_RT2800USB_RT53XX=y
++# CONFIG_RTL_CARDS is not set
++CONFIG_RTW88=y
++CONFIG_RTW88_8822BU=y
++CONFIG_RTW88_8822CE=y
++CONFIG_RTW88_8821CU=y
++CONFIG_RTW88_DEBUG=y
++CONFIG_RTW88_DEBUGFS=y
++CONFIG_RTW89=y
++CONFIG_RTW89_8852AE=y
++CONFIG_RTW89_8852CE=y
++# CONFIG_WLAN_VENDOR_RSI is not set
++CONFIG_CW1200=m
++CONFIG_CW1200_WLAN_SDIO=m
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_ADC=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_PINEPHONE=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_GOODIX=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++CONFIG_INPUT_UINPUT=y
++CONFIG_INPUT_RK805_PWRKEY=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_PCI1XXXX=y
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_I2C_RK3X=y
++CONFIG_SPI=y
++CONFIG_SPI_ROCKCHIP=y
++CONFIG_SPI_ROCKCHIP_SFC=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SUN6I=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_PINCTRL_RK805=y
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_SUN50I_H616 is not set
++# CONFIG_PINCTRL_SUN50I_H616_R is not set
++CONFIG_POWER_RESET_GPIO=y
++CONFIG_POWER_RESET_GPIO_RESTART=y
++CONFIG_SYSCON_REBOOT_MODE=y
++CONFIG_NVMEM_REBOOT_MODE=y
++CONFIG_IP5XXX_POWER=y
++CONFIG_BATTERY_CW2015=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++CONFIG_CHARGER_GPIO=y
++CONFIG_CHARGER_RK817=y
++CONFIG_CHARGER_RK818=y
++CONFIG_SENSORS_ARM_SCMI=y
++CONFIG_SENSORS_ARM_SCPI=y
++CONFIG_SENSORS_GPIO_FAN=y
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_DEVFREQ_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_ROCKCHIP_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_DW_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_SSB=y
++CONFIG_SSB_SDIOHOST=y
++CONFIG_SSB_DRIVER_PCICORE=y
++CONFIG_BCMA=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_RK8XX_I2C=y
++CONFIG_MFD_RK8XX_SPI=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_FAN53555=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_RK808=y
++CONFIG_REGULATOR_SY8106A=y
++CONFIG_RC_CORE=y
++CONFIG_BPF_LIRC_MODE2=y
++CONFIG_LIRC=y
++CONFIG_RC_DECODERS=y
++CONFIG_IR_JVC_DECODER=y
++CONFIG_IR_MCE_KBD_DECODER=y
++CONFIG_IR_NEC_DECODER=y
++CONFIG_IR_RC5_DECODER=y
++CONFIG_IR_RC6_DECODER=y
++CONFIG_IR_SANYO_DECODER=y
++CONFIG_IR_SHARP_DECODER=y
++CONFIG_IR_SONY_DECODER=y
++CONFIG_IR_XMP_DECODER=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=y
++CONFIG_IR_SUNXI=y
++CONFIG_MEDIA_CEC_RC=y
++CONFIG_MEDIA_CEC_SUPPORT=y
++CONFIG_MEDIA_SUPPORT=y
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_VIDEO_ADV_DEBUG=y
++CONFIG_V4L2_FLASH_LED_CLASS=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
++CONFIG_VIDEO_ROCKCHIP_RGA=y
++CONFIG_VIDEO_ROCKCHIP_ISP1=y
++CONFIG_VIDEO_SUN6I_CSI=y
++CONFIG_VIDEO_SUN8I_DEINTERLACE=y
++CONFIG_VIDEO_SUN8I_ROTATE=y
++CONFIG_VIDEO_HANTRO=y
++CONFIG_VIDEO_IMX258=y
++CONFIG_VIDEO_OV5640=y
++CONFIG_VIDEO_OV5648=y
++CONFIG_VIDEO_OV8858=y
++CONFIG_VIDEO_GC2145=y
++CONFIG_VIDEO_DW9714=y
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_ROCKCHIP=y
++CONFIG_ROCKCHIP_VOP2=y
++CONFIG_ROCKCHIP_ANALOGIX_DP=y
++CONFIG_ROCKCHIP_CDN_DP=y
++CONFIG_ROCKCHIP_DW_HDMI=y
++CONFIG_ROCKCHIP_DW_MIPI_DSI=y
++CONFIG_ROCKCHIP_INNO_HDMI=y
++CONFIG_ROCKCHIP_LVDS=y
++CONFIG_ROCKCHIP_RGB=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A=y
++CONFIG_DRM_PANEL_SIMPLE=y
++CONFIG_DRM_PANEL_EDP=y
++CONFIG_DRM_PANEL_HIMAX_HX8394=y
++CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
++CONFIG_DRM_PANEL_SITRONIX_ST7703=y
++CONFIG_DRM_DISPLAY_CONNECTOR=y
++CONFIG_DRM_SIMPLE_BRIDGE=y
++CONFIG_DRM_CDNS_DSI=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
++CONFIG_DRM_DW_HDMI_GP_AUDIO=y
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_LIMA=y
++CONFIG_DRM_PANFROST=y
++CONFIG_FB=y
++CONFIG_FB_SIMPLE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
++CONFIG_LOGO=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_HRTIMER=y
++# CONFIG_SND_SPI is not set
++CONFIG_SND_USB_AUDIO=y
++CONFIG_SND_SOC=y
++CONFIG_SND_SOC_ROCKCHIP=y
++CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
++CONFIG_SND_SOC_ROCKCHIP_PDM=y
++CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
++CONFIG_SND_SOC_RK3399_GRU_SOUND=y
++CONFIG_SND_SUN4I_CODEC=y
++CONFIG_SND_SUN8I_CODEC=y
++CONFIG_SND_SUN8I_CODEC_ANALOG=y
++CONFIG_SND_SUN50I_CODEC_ANALOG=y
++CONFIG_SND_SUN4I_I2S=y
++CONFIG_SND_SUN4I_SPDIF=y
++CONFIG_SND_SUN9I_HDMI_AUDIO=y
++CONFIG_SND_SOC_BT_SCO=y
++CONFIG_SND_SOC_EC25=y
++CONFIG_SND_SOC_ES8316=y
++CONFIG_SND_SOC_ES8328_I2C=y
++CONFIG_SND_SOC_RK817=y
++CONFIG_SND_SOC_RT5640=y
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
++CONFIG_SND_SOC_SPDIF=y
++CONFIG_SND_SIMPLE_CARD=y
++CONFIG_SND_AUDIO_GRAPH_CARD=y
++CONFIG_HIDRAW=y
++CONFIG_UHID=y
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_HID_MULTITOUCH=y
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB_ULPI_BUS=y
++CONFIG_USB_CONN_GPIO=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=y
++CONFIG_USB_MON=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=y
++CONFIG_USB_PRINTER=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_UAS=y
++CONFIG_USBIP_CORE=y
++CONFIG_USBIP_VHCI_HCD=y
++CONFIG_USBIP_HOST=y
++CONFIG_USBIP_VUDC=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SUNXI=y
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_DWC3=y
++CONFIG_USB_DWC3_ULPI=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_CONSOLE=y
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_SIMPLE=y
++CONFIG_USB_SERIAL_CH341=y
++CONFIG_USB_SERIAL_CP210X=y
++CONFIG_USB_SERIAL_FTDI_SIO=y
++CONFIG_USB_SERIAL_PL2303=y
++CONFIG_USB_SERIAL_QCAUX=y
++CONFIG_USB_SERIAL_QUALCOMM=y
++CONFIG_USB_SERIAL_OPTION=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_VBUS_DRAW=500
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=y
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_TYPEC_TCPM=y
++CONFIG_TYPEC_TCPCI=y
++CONFIG_TYPEC_HUSB311=y
++CONFIG_TYPEC_FUSB302=y
++CONFIG_TYPEC_UCSI=y
++CONFIG_TYPEC_ANX7688=y
++CONFIG_TYPEC_EXTCON=y
++CONFIG_TYPEC_DP_ALTMODE=y
++CONFIG_MMC=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_OF_ARASAN=y
++CONFIG_MMC_SDHCI_OF_DWCMSHC=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_PWM=y
++CONFIG_LEDS_REGULATOR=y
++CONFIG_LEDS_SGM3140=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=y
++CONFIG_LEDS_TRIGGER_CAMERA=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_HYM8563=y
++CONFIG_RTC_DRV_RK808=y
++CONFIG_RTC_DRV_SUN6I=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_PL330_DMA=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_ROCKCHIP_VDEC=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=y
++CONFIG_RTL8723CS=y
++CONFIG_COMMON_CLK_RK808=y
++CONFIG_COMMON_CLK_SCMI=y
++CONFIG_COMMON_CLK_SCPI=y
++CONFIG_COMMON_CLK_PWM=y
++# CONFIG_CLK_RK3308 is not set
++# CONFIG_CLK_RK3328 is not set
++# CONFIG_CLK_RK3368 is not set
++# CONFIG_SUN50I_A100_CCU is not set
++# CONFIG_SUN50I_A100_R_CCU is not set
++# CONFIG_SUN50I_H616_CCU is not set
++# CONFIG_SUN6I_RTC_CCU is not set
++# CONFIG_FSL_ERRATUM_A008585 is not set
++# CONFIG_HISILICON_ERRATUM_161010101 is not set
++CONFIG_MAILBOX=y
++CONFIG_ROCKCHIP_MBOX=y
++CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
++CONFIG_ROCKCHIP_IOMMU=y
++CONFIG_ARM_SMMU=y
++CONFIG_ARM_SMMU_V3=y
++CONFIG_ROCKCHIP_IODOMAIN=y
++CONFIG_ROCKCHIP_PM_DOMAINS=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_ARM_RK3399_DMC_DEVFREQ=y
++CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
++CONFIG_EXTCON_ADC_JACK=y
++CONFIG_EXTCON_GPIO=y
++CONFIG_EXTCON_USB_GPIO=y
++CONFIG_IIO=y
++CONFIG_IIO_BUFFER_CB=y
++CONFIG_IIO_BUFFER_HW_CONSUMER=y
++CONFIG_IIO_SW_DEVICE=y
++CONFIG_IIO_SW_TRIGGER=y
++CONFIG_IIO_ST_ACCEL_3AXIS=y
++# CONFIG_IIO_ST_ACCEL_SPI_3AXIS is not set
++CONFIG_AXP20X_ADC=y
++CONFIG_ROCKCHIP_SARADC=y
++CONFIG_INV_MPU6050_I2C=y
++CONFIG_STK3310=y
++CONFIG_AF8133J=y
++CONFIG_IIO_ST_MAGN_3AXIS=y
++CONFIG_IIO_HRTIMER_TRIGGER=y
++CONFIG_IIO_INTERRUPT_TRIGGER=y
++CONFIG_IIO_SYSFS_TRIGGER=y
++CONFIG_PWM=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_PHY_SUN50I_USB3=y
++CONFIG_PHY_ROCKCHIP_DP=y
++CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
++CONFIG_PHY_ROCKCHIP_EMMC=y
++CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
++CONFIG_PHY_ROCKCHIP_INNO_USB2=y
++CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
++CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
++CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
++CONFIG_PHY_ROCKCHIP_PCIE=y
++CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
++CONFIG_PHY_ROCKCHIP_TYPEC=y
++CONFIG_PHY_ROCKCHIP_USB=y
++CONFIG_PHY_ROCKCHIP_USBDP=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_ANDROID_BINDER_IPC=y
++CONFIG_ANDROID_BINDERFS=y
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_XFS_FS=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_BTRFS_FS=y
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_OVERLAY_FS=y
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_XINO_AUTO=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_ISO9660_FS=y
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_UTF8=y
++CONFIG_EXFAT_FS=y
++CONFIG_NTFS3_FS=y
++CONFIG_NTFS3_64BIT_CLUSTER=y
++CONFIG_NTFS3_FS_POSIX_ACL=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_INODE64=y
++CONFIG_HUGETLBFS=y
++CONFIG_ECRYPT_FS=y
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V2 is not set
++# CONFIG_NFS_V3 is not set
++CONFIG_NFS_V4=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_2=y
++CONFIG_NFS_FSCACHE=y
++CONFIG_NFSD=y
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y
++CONFIG_CIFS=y
++# CONFIG_CIFS_STATS2 is not set
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++# CONFIG_CIFS_DEBUG is not set
++CONFIG_CIFS_DFS_UPCALL=y
++CONFIG_CIFS_SWN_UPCALL=y
++CONFIG_CIFS_FSCACHE=y
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_BIG_KEYS=y
++CONFIG_TRUSTED_KEYS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_SECURITY=y
++# CONFIG_INTEGRITY is not set
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_ECDSA=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_NHPOLY1305_NEON=y
++CONFIG_CRYPTO_GHASH_ARM64_CE=y
++CONFIG_CRYPTO_SHA1_ARM64_CE=y
++CONFIG_CRYPTO_SHA2_ARM64_CE=y
++CONFIG_CRYPTO_SHA512_ARM64_CE=y
++CONFIG_CRYPTO_SHA3_ARM64=y
++CONFIG_CRYPTO_SM3_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64=y
++CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
++CONFIG_CRYPTO_AES_ARM64_BS=y
++CONFIG_CRYPTO_SM4_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_SS=y
++CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y
++CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
++CONFIG_CRYPTO_DEV_ROCKCHIP=y
++CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++# CONFIG_RAID6_PQ_BENCHMARK is not set
++CONFIG_CORDIC=y
++CONFIG_DMA_CMA=y
++CONFIG_DMA_NUMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_FONT_SUN12x22=y
++CONFIG_FONT_TER16x32=y
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_DEBUG_KERNEL=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_PER_VMA_LOCK_STATS=y
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_SOFTLOCKUP_DETECTOR=y
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
++CONFIG_WQ_WATCHDOG=y
++CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
++# CONFIG_RCU_TRACE is not set
++# CONFIG_FTRACE is not set
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm64/configs/pinephone_defconfig b/arch/arm64/configs/pinephone_defconfig
+new file mode 100644
+index 000000000000..7ac485b54aea
+--- /dev/null
++++ b/arch/arm64/configs/pinephone_defconfig
+@@ -0,0 +1,651 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_BPF_JIT_ALWAYS_ON=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_PREEMPT=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_PSI=y
++CONFIG_LOG_BUF_SHIFT=19
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_GZIP is not set
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++# CONFIG_RD_ZSTD is not set
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_ARM64_ERRATUM_832075 is not set
++# CONFIG_ARM64_ERRATUM_1024718 is not set
++# CONFIG_ARM64_ERRATUM_1418040 is not set
++# CONFIG_ARM64_ERRATUM_1165522 is not set
++# CONFIG_ARM64_ERRATUM_1319367 is not set
++# CONFIG_ARM64_ERRATUM_1530923 is not set
++# CONFIG_ARM64_ERRATUM_1286807 is not set
++# CONFIG_ARM64_ERRATUM_1463225 is not set
++# CONFIG_ARM64_ERRATUM_1542419 is not set
++# CONFIG_ARM64_ERRATUM_2051678 is not set
++# CONFIG_ARM64_ERRATUM_2077057 is not set
++# CONFIG_CAVIUM_ERRATUM_22375 is not set
++# CONFIG_CAVIUM_ERRATUM_23154 is not set
++# CONFIG_CAVIUM_ERRATUM_27456 is not set
++# CONFIG_CAVIUM_ERRATUM_30115 is not set
++# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
++# CONFIG_FUJITSU_ERRATUM_010001 is not set
++# CONFIG_HISILICON_ERRATUM_161600802 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
++# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
++# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
++CONFIG_SCHED_MC=y
++CONFIG_NR_CPUS=4
++CONFIG_HZ_100=y
++CONFIG_COMPAT=y
++# CONFIG_ARM64_HW_AFDBM is not set
++# CONFIG_ARM64_PAN is not set
++# CONFIG_ARM64_USE_LSE_ATOMICS is not set
++# CONFIG_ARM64_RAS_EXTN is not set
++# CONFIG_ARM64_CNP is not set
++# CONFIG_ARM64_PTR_AUTH is not set
++# CONFIG_ARM64_AMU_EXTN is not set
++# CONFIG_ARM64_TLB_RANGE is not set
++# CONFIG_ARM64_BTI is not set
++# CONFIG_ARM64_E0PD is not set
++# CONFIG_ARM64_SVE is not set
++# CONFIG_EFI is not set
++CONFIG_PM_AUTOSLEEP=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_CPU_IDLE_GOV_MENU=y
++CONFIG_CPU_IDLE_GOV_TEO=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=m
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_DIAG is not set
++# CONFIG_IPV6_SIT is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_CONNLIMIT=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_MASQ=m
++CONFIG_NFT_REDIR=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_TUNNEL=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_QUOTA=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_FIB_INET=m
++CONFIG_NFT_SOCKET=m
++CONFIG_NFT_OSF=m
++CONFIG_NFT_DUP_NETDEV=m
++CONFIG_NFT_FWD_NETDEV=m
++CONFIG_NF_FLOW_TABLE_INET=m
++CONFIG_NF_FLOW_TABLE=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPMARK=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_IPMAC=m
++CONFIG_IP_SET_HASH_MAC=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_NFT_FIB_IPV4=m
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=m
++CONFIG_NF_LOG_IPV4=m
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_NFT_DUP_IPV6=m
++CONFIG_NFT_FIB_IPV6=m
++CONFIG_NF_LOG_IPV6=m
++CONFIG_BRIDGE=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_ROUTE4=m
++CONFIG_NET_CLS_FW=m
++CONFIG_NET_CLS_CGROUP=m
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=m
++CONFIG_NET_ACT_GACT=m
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NETLINK_DIAG=m
++CONFIG_BT=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++CONFIG_BT_HS=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_RTL=y
++CONFIG_CFG80211=m
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=m
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=m
++CONFIG_RFKILL_GPIO=m
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s anx7688-fw.bin rtl_bt/rtl8723cs_xx_config.bin rtl_bt/rtl8723cs_xx_fw.bin ov5640_af.bin rtw88/rtw8703b_wow_fw.bin rtw88/rtw8703b_fw.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_ARM_SCPI_PROTOCOL=y
++# CONFIG_ARM_SMCCC_SOC_ID is not set
++CONFIG_ZRAM=m
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_PPKB_POWER_MANAGER=y
++CONFIG_MODEM_POWER=m
++CONFIG_SCSI=m
++CONFIG_BLK_DEV_SD=m
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_UEVENT=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++# CONFIG_ETHERNET is not set
++CONFIG_PPP=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=m
++CONFIG_USB_RTL8152=m
++CONFIG_USB_USBNET=m
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=m
++CONFIG_USB_NET_CDC_MBIM=m
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++CONFIG_USB_NET_QMI_WWAN=m
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_SILABS is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=m
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_PINEPHONE=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_GOODIX=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++CONFIG_INPUT_UINPUT=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_SUN8I_H3_R is not set
++# CONFIG_PINCTRL_SUN50I_H5 is not set
++# CONFIG_PINCTRL_SUN50I_H6 is not set
++# CONFIG_PINCTRL_SUN50I_H6_R is not set
++# CONFIG_PINCTRL_SUN50I_H616 is not set
++# CONFIG_PINCTRL_SUN50I_H616_R is not set
++CONFIG_NVMEM_REBOOT_MODE=y
++CONFIG_IP5XXX_POWER=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_MFD_SYSCON=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_MEDIA_SUPPORT=m
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_V4L2_FLASH_LED_CLASS=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
++CONFIG_VIDEO_SUN6I_CSI=m
++CONFIG_VIDEO_SUN8I_DEINTERLACE=m
++CONFIG_VIDEO_SUN8I_ROTATE=m
++CONFIG_VIDEO_OV5640=m
++CONFIG_VIDEO_GC2145=m
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
++CONFIG_DRM_PANEL_SITRONIX_ST7703=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_LIMA=m
++CONFIG_FB=y
++CONFIG_FB_SIMPLE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_SOUND=m
++CONFIG_SND=m
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=m
++CONFIG_SND_PCM_OSS=m
++CONFIG_SND_HRTIMER=m
++# CONFIG_SND_SUPPORT_OLD_API is not set
++CONFIG_SND_SEQUENCER=m
++CONFIG_SND_SEQ_DUMMY=m
++CONFIG_SND_SEQUENCER_OSS=m
++CONFIG_SND_ALOOP=m
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=m
++CONFIG_SND_SUN4I_CODEC=m
++CONFIG_SND_SUN8I_CODEC=m
++CONFIG_SND_SUN8I_CODEC_ANALOG=m
++CONFIG_SND_SUN50I_CODEC_ANALOG=m
++CONFIG_SND_SUN4I_I2S=m
++CONFIG_SND_SUN4I_SPDIF=m
++CONFIG_SND_SOC_BT_SCO=m
++CONFIG_SND_SOC_EC25=m
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_SND_AUDIO_GRAPH_CARD=m
++CONFIG_HID=m
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=m
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=m
++CONFIG_USB_LEDS_TRIGGER_USBPORT=m
++CONFIG_USB_MON=m
++CONFIG_USB_EHCI_HCD=m
++CONFIG_USB_EHCI_HCD_PLATFORM=m
++CONFIG_USB_OHCI_HCD=m
++CONFIG_USB_OHCI_HCD_PLATFORM=m
++CONFIG_USB_ACM=m
++CONFIG_USB_STORAGE=m
++CONFIG_USB_UAS=m
++CONFIG_USBIP_CORE=m
++CONFIG_USBIP_VHCI_HCD=m
++CONFIG_USBIP_HOST=m
++CONFIG_USBIP_VUDC=m
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_SUNXI=m
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_SIMPLE=m
++CONFIG_USB_SERIAL_CH341=m
++CONFIG_USB_SERIAL_CP210X=m
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_QCAUX=m
++CONFIG_USB_SERIAL_QUALCOMM=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_NOP_USB_XCEIV=m
++CONFIG_USB_GADGET=m
++CONFIG_USB_GADGET_VBUS_DRAW=500
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_AUDIO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_ETH_EEM=y
++CONFIG_USB_G_NCM=m
++CONFIG_USB_GADGETFS=m
++CONFIG_USB_FUNCTIONFS=m
++CONFIG_USB_FUNCTIONFS_ETH=y
++CONFIG_USB_FUNCTIONFS_RNDIS=y
++CONFIG_USB_FUNCTIONFS_GENERIC=y
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_USB_MIDI_GADGET=m
++CONFIG_USB_G_PRINTER=m
++CONFIG_USB_CDC_COMPOSITE=m
++CONFIG_USB_G_ACM_MS=m
++CONFIG_USB_G_MULTI=m
++CONFIG_USB_G_MULTI_CDC=y
++CONFIG_USB_G_HID=m
++CONFIG_USB_G_WEBCAM=m
++CONFIG_USB_RAW_GADGET=m
++CONFIG_TYPEC=y
++CONFIG_TYPEC_ANX7688=y
++CONFIG_TYPEC_DP_ALTMODE=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=y
++CONFIG_LEDS_CLASS_MULTICOLOR=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_SGM3140=m
++CONFIG_LEDS_GROUP_MULTICOLOR=m
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=m
++CONFIG_LEDS_TRIGGER_CAMERA=m
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_SUN6I=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=m
++CONFIG_RTL8723CS=m
++# CONFIG_SUN50I_H6_CCU is not set
++# CONFIG_SUN50I_H616_CCU is not set
++# CONFIG_SUN50I_H6_R_CCU is not set
++# CONFIG_SUN8I_H3_CCU is not set
++# CONFIG_HISILICON_ERRATUM_161010101 is not set
++# CONFIG_ARM64_ERRATUM_858921 is not set
++CONFIG_MAILBOX=y
++CONFIG_IOMMU_IO_PGTABLE_LPAE=y
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=m
++CONFIG_DEVFREQ_GOV_POWERSAVE=m
++CONFIG_DEVFREQ_GOV_USERSPACE=m
++CONFIG_DEVFREQ_GOV_PASSIVE=m
++CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_BUFFER_CB=m
++CONFIG_IIO_BUFFER_HW_CONSUMER=m
++CONFIG_IIO_SW_DEVICE=m
++CONFIG_IIO_SW_TRIGGER=m
++CONFIG_AXP20X_ADC=y
++CONFIG_INV_MPU6050_I2C=m
++CONFIG_STK3310=m
++CONFIG_AF8133J=m
++CONFIG_IIO_ST_MAGN_3AXIS=m
++CONFIG_IIO_HRTIMER_TRIGGER=m
++CONFIG_IIO_INTERRUPT_TRIGGER=m
++CONFIG_IIO_SYSFS_TRIGGER=m
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_ANDROID_BINDER_IPC=y
++CONFIG_ANDROID_BINDERFS=y
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_BTRFS_FS=y
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_NILFS2_FS=m
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=m
++CONFIG_FUSE_FS=m
++CONFIG_CUSE=m
++CONFIG_OVERLAY_FS=m
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_VFAT_FS=y
++CONFIG_EXFAT_FS=m
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_ECRYPT_FS=m
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=m
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_USER=m
++CONFIG_CRYPTO_PCRYPT=m
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_CURVE25519=m
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_ARC4=m
++CONFIG_CRYPTO_CHACHA20POLY1305=m
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++CONFIG_CRYPTO_MD4=m
++CONFIG_CRYPTO_SHA1=y
++CONFIG_CRYPTO_SHA3=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=m
++CONFIG_CRYPTO_USER_API_HASH=m
++CONFIG_CRYPTO_USER_API_SKCIPHER=m
++CONFIG_CRYPTO_USER_API_RNG=m
++CONFIG_CRYPTO_USER_API_AEAD=m
++CONFIG_CRYPTO_GHASH_ARM64_CE=m
++CONFIG_CRYPTO_SHA1_ARM64_CE=m
++CONFIG_CRYPTO_SHA2_ARM64_CE=m
++CONFIG_CRYPTO_SHA512_ARM64_CE=m
++CONFIG_CRYPTO_SHA3_ARM64=m
++CONFIG_CRYPTO_SM3_ARM64_CE=m
++CONFIG_CRYPTO_AES_ARM64=m
++CONFIG_CRYPTO_AES_ARM64_CE_BLK=m
++CONFIG_CRYPTO_AES_ARM64_BS=m
++CONFIG_CRYPTO_SM4_ARM64_CE=m
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=m
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
++CONFIG_CRYPTO_DEV_SUN8I_CE=m
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
++# CONFIG_RAID6_PQ_BENCHMARK is not set
++CONFIG_CRC_T10DIF=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++CONFIG_PER_VMA_LOCK_STATS=y
++CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
++CONFIG_FTRACE=y
++CONFIG_BOOTTIME_TRACING=y
++CONFIG_FUNCTION_TRACER=y
++CONFIG_FTRACE_SYSCALLS=y
++CONFIG_TRACER_SNAPSHOT=y
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm64/configs/pinephone_multidist_defconfig b/arch/arm64/configs/pinephone_multidist_defconfig
+new file mode 100644
+index 000000000000..92b9119238c0
+--- /dev/null
++++ b/arch/arm64/configs/pinephone_multidist_defconfig
+@@ -0,0 +1,602 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_BPF_JIT_ALWAYS_ON=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_PSI=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_BPF=y
++CONFIG_NAMESPACES=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_GZIP is not set
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++# CONFIG_RD_ZSTD is not set
++CONFIG_EXPERT=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_ARM64_ERRATUM_832075 is not set
++# CONFIG_ARM64_ERRATUM_1024718 is not set
++# CONFIG_ARM64_ERRATUM_1418040 is not set
++# CONFIG_ARM64_ERRATUM_1165522 is not set
++# CONFIG_ARM64_ERRATUM_1319367 is not set
++# CONFIG_ARM64_ERRATUM_1530923 is not set
++# CONFIG_ARM64_ERRATUM_1286807 is not set
++# CONFIG_ARM64_ERRATUM_1463225 is not set
++# CONFIG_ARM64_ERRATUM_1542419 is not set
++# CONFIG_ARM64_ERRATUM_2051678 is not set
++# CONFIG_ARM64_ERRATUM_2077057 is not set
++# CONFIG_CAVIUM_ERRATUM_22375 is not set
++# CONFIG_CAVIUM_ERRATUM_23154 is not set
++# CONFIG_CAVIUM_ERRATUM_27456 is not set
++# CONFIG_CAVIUM_ERRATUM_30115 is not set
++# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
++# CONFIG_FUJITSU_ERRATUM_010001 is not set
++# CONFIG_HISILICON_ERRATUM_161600802 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
++# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
++# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
++CONFIG_SCHED_MC=y
++CONFIG_NR_CPUS=4
++CONFIG_COMPAT=y
++# CONFIG_ARM64_HW_AFDBM is not set
++# CONFIG_ARM64_PAN is not set
++# CONFIG_ARM64_USE_LSE_ATOMICS is not set
++# CONFIG_ARM64_RAS_EXTN is not set
++# CONFIG_ARM64_CNP is not set
++# CONFIG_ARM64_PTR_AUTH is not set
++# CONFIG_ARM64_AMU_EXTN is not set
++# CONFIG_ARM64_TLB_RANGE is not set
++# CONFIG_ARM64_BTI is not set
++# CONFIG_ARM64_E0PD is not set
++# CONFIG_ARM64_SVE is not set
++# CONFIG_EFI is not set
++CONFIG_PM_AUTOSLEEP=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_DIAG is not set
++# CONFIG_IPV6_SIT is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=y
++CONFIG_NF_CONNTRACK_H323=y
++CONFIG_NF_CONNTRACK_IRC=y
++CONFIG_NF_CONNTRACK_NETBIOS_NS=y
++CONFIG_NF_CONNTRACK_SNMP=y
++CONFIG_NF_CONNTRACK_PPTP=y
++CONFIG_NF_CONNTRACK_SIP=y
++CONFIG_NF_CONNTRACK_TFTP=y
++CONFIG_NF_CT_NETLINK=y
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=y
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=y
++CONFIG_NFT_CT=y
++CONFIG_NFT_CONNLIMIT=y
++CONFIG_NFT_LOG=y
++CONFIG_NFT_LIMIT=y
++CONFIG_NFT_MASQ=y
++CONFIG_NFT_REDIR=y
++CONFIG_NFT_NAT=y
++CONFIG_NFT_TUNNEL=y
++CONFIG_NFT_QUEUE=y
++CONFIG_NFT_QUOTA=y
++CONFIG_NFT_REJECT=y
++CONFIG_NFT_HASH=y
++CONFIG_NFT_FIB_INET=y
++CONFIG_NFT_SOCKET=y
++CONFIG_NFT_OSF=y
++CONFIG_NFT_DUP_NETDEV=y
++CONFIG_NFT_FWD_NETDEV=y
++CONFIG_NF_FLOW_TABLE_INET=y
++CONFIG_NF_FLOW_TABLE=y
++CONFIG_IP_SET=y
++CONFIG_IP_SET_BITMAP_IP=y
++CONFIG_IP_SET_BITMAP_IPMAC=y
++CONFIG_IP_SET_BITMAP_PORT=y
++CONFIG_IP_SET_HASH_IP=y
++CONFIG_IP_SET_HASH_IPMARK=y
++CONFIG_IP_SET_HASH_IPPORT=y
++CONFIG_IP_SET_HASH_IPPORTIP=y
++CONFIG_IP_SET_HASH_IPPORTNET=y
++CONFIG_IP_SET_HASH_IPMAC=y
++CONFIG_IP_SET_HASH_MAC=y
++CONFIG_IP_SET_HASH_NETPORTNET=y
++CONFIG_IP_SET_HASH_NET=y
++CONFIG_IP_SET_HASH_NETNET=y
++CONFIG_IP_SET_HASH_NETPORT=y
++CONFIG_IP_SET_HASH_NETIFACE=y
++CONFIG_IP_SET_LIST_SET=y
++CONFIG_NFT_FIB_IPV4=y
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_NFT_DUP_IPV6=y
++CONFIG_NFT_FIB_IPV6=y
++CONFIG_NF_LOG_IPV6=y
++CONFIG_BRIDGE=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_NET_ACT_MIRRED=y
++CONFIG_NETLINK_DIAG=y
++CONFIG_BT=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_HS=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_RTL=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s anx7688-fw.bin rtl_bt/rtl8723cs_xx_config.bin rtl_bt/rtl8723cs_xx_fw.bin ov5640_af.bin rtw88/rtw8703b_wow_fw.bin rtw88/rtw8703b_fw.bin"
++CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_ARM_SCPI_PROTOCOL=y
++# CONFIG_ARM_SMCCC_SOC_ID is not set
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_PPKB_POWER_MANAGER=y
++CONFIG_MODEM_POWER=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_UEVENT=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=y
++CONFIG_TUN=y
++CONFIG_VETH=y
++# CONFIG_ETHERNET is not set
++CONFIG_PPP=y
++CONFIG_PPP_BSDCOMP=y
++CONFIG_PPP_DEFLATE=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=y
++CONFIG_USB_RTL8152=y
++CONFIG_USB_USBNET=y
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=y
++CONFIG_USB_NET_CDC_MBIM=y
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++CONFIG_USB_NET_QMI_WWAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_RTL_CARDS is not set
++CONFIG_RTW88=m
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_SILABS is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_PINEPHONE=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_GOODIX=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++CONFIG_INPUT_UINPUT=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_SUN8I_H3_R is not set
++# CONFIG_PINCTRL_SUN50I_H5 is not set
++# CONFIG_PINCTRL_SUN50I_H6 is not set
++# CONFIG_PINCTRL_SUN50I_H6_R is not set
++# CONFIG_PINCTRL_SUN50I_H616 is not set
++# CONFIG_PINCTRL_SUN50I_H616_R is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_NVMEM_REBOOT_MODE=y
++CONFIG_IP5XXX_POWER=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_MFD_SYSCON=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_SUPPORT_FILTER=y
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_V4L2_FLASH_LED_CLASS=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
++CONFIG_VIDEO_SUN6I_CSI=y
++CONFIG_VIDEO_SUN8I_DEINTERLACE=y
++CONFIG_VIDEO_SUN8I_ROTATE=y
++CONFIG_VIDEO_OV5640=y
++CONFIG_VIDEO_GC2145=y
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
++CONFIG_DRM_PANEL_SITRONIX_ST7703=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_LIMA=y
++CONFIG_FB=y
++CONFIG_FB_SIMPLE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_HRTIMER=y
++# CONFIG_SND_SUPPORT_OLD_API is not set
++# CONFIG_SND_DRIVERS is not set
++CONFIG_SND_USB_AUDIO=y
++CONFIG_SND_SOC=y
++CONFIG_SND_SUN4I_CODEC=y
++CONFIG_SND_SUN8I_CODEC=y
++CONFIG_SND_SUN8I_CODEC_ANALOG=y
++CONFIG_SND_SUN50I_CODEC_ANALOG=y
++CONFIG_SND_SUN4I_I2S=y
++CONFIG_SND_SUN4I_SPDIF=y
++CONFIG_SND_SUN9I_HDMI_AUDIO=y
++CONFIG_SND_SOC_BT_SCO=y
++CONFIG_SND_SOC_EC25=y
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
++CONFIG_SND_SIMPLE_CARD=y
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=y
++CONFIG_USB_MON=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_UAS=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SUNXI=y
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_CONSOLE=y
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_SIMPLE=y
++CONFIG_USB_SERIAL_CH341=y
++CONFIG_USB_SERIAL_CP210X=y
++CONFIG_USB_SERIAL_FTDI_SIO=y
++CONFIG_USB_SERIAL_QCAUX=y
++CONFIG_USB_SERIAL_OPTION=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_VBUS_DRAW=500
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=y
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_TYPEC=y
++CONFIG_TYPEC_TCPM=y
++CONFIG_TYPEC_TCPCI=y
++CONFIG_TYPEC_UCSI=y
++CONFIG_TYPEC_ANX7688=y
++CONFIG_TYPEC_DP_ALTMODE=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_SGM3140=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=y
++CONFIG_LEDS_TRIGGER_CAMERA=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_SUN6I=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=y
++CONFIG_RTL8723CS=m
++# CONFIG_SUN50I_H6_CCU is not set
++# CONFIG_SUN50I_H616_CCU is not set
++# CONFIG_SUN50I_H6_R_CCU is not set
++# CONFIG_SUN8I_H3_CCU is not set
++# CONFIG_HISILICON_ERRATUM_161010101 is not set
++# CONFIG_ARM64_ERRATUM_858921 is not set
++CONFIG_MAILBOX=y
++CONFIG_IOMMU_IO_PGTABLE_LPAE=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_BUFFER_CB=y
++CONFIG_IIO_BUFFER_HW_CONSUMER=y
++CONFIG_IIO_SW_DEVICE=y
++CONFIG_IIO_SW_TRIGGER=y
++CONFIG_AXP20X_ADC=y
++CONFIG_INV_MPU6050_I2C=y
++CONFIG_STK3310=y
++CONFIG_AF8133J=y
++CONFIG_IIO_ST_MAGN_3AXIS=y
++CONFIG_IIO_HRTIMER_TRIGGER=y
++CONFIG_IIO_INTERRUPT_TRIGGER=y
++CONFIG_IIO_SYSFS_TRIGGER=y
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_ANDROID_BINDER_IPC=y
++CONFIG_ANDROID_BINDERFS=y
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_BTRFS_FS=y
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_OVERLAY_FS=y
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_VFAT_FS=y
++CONFIG_EXFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_ECRYPT_FS=y
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_BIG_KEYS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_GHASH_ARM64_CE=y
++CONFIG_CRYPTO_SHA1_ARM64_CE=y
++CONFIG_CRYPTO_SHA2_ARM64_CE=y
++CONFIG_CRYPTO_SHA512_ARM64_CE=y
++CONFIG_CRYPTO_SHA3_ARM64=y
++CONFIG_CRYPTO_SM3_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64=y
++CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
++CONFIG_CRYPTO_AES_ARM64_BS=y
++CONFIG_CRYPTO_SM4_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++# CONFIG_RAID6_PQ_BENCHMARK is not set
++CONFIG_CRC_T10DIF=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++# CONFIG_SLUB_DEBUG is not set
++CONFIG_PER_VMA_LOCK_STATS=y
++CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
++CONFIG_BOOTTIME_TRACING=y
++CONFIG_FUNCTION_TRACER=y
++CONFIG_FTRACE_SYSCALLS=y
++CONFIG_TRACER_SNAPSHOT=y
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Fix-for-usb-gadget-on-PP.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Fix-for-usb-gadget-on-PP.patch
new file mode 100644
index 000000000000..d46f16ed27eb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Fix-for-usb-gadget-on-PP.patch
@@ -0,0 +1,192 @@
+From 90fff935b3971b4aefe785106acef348a14bf380 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 21 Jul 2024 23:06:34 +0200
+Subject: Fix for usb gadget on PP
+
+- this will get squashed into
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/gadget/function/f_ecm.c    |  6 ++----
+ drivers/usb/gadget/function/f_eem.c    | 22 +++++++---------------
+ drivers/usb/gadget/function/f_ncm.c    |  5 ++---
+ drivers/usb/gadget/function/f_rndis.c  | 21 ++++++---------------
+ drivers/usb/gadget/function/f_subset.c | 12 +++++-------
+ drivers/usb/gadget/function/u_ether.c  |  6 ++++--
+ 6 files changed, 26 insertions(+), 46 deletions(-)
+
+diff --git a/drivers/usb/gadget/function/f_ecm.c b/drivers/usb/gadget/function/f_ecm.c
+index e331cc64390b..d19f545876ce 100644
+--- a/drivers/usb/gadget/function/f_ecm.c
++++ b/drivers/usb/gadget/function/f_ecm.c
+@@ -685,14 +685,12 @@ ecm_bind(struct usb_configuration *c, struct usb_function *f)
+ 	ecm_opts = container_of(f->fi, struct f_ecm_opts, func_inst);
+ 
+ 	mutex_lock(&ecm_opts->lock);
+-
+ 	gether_set_gadget(ecm_opts->net, cdev->gadget);
+-
+ 	if (!ecm_opts->bound) {
+ 		status = gether_register_netdev(ecm_opts->net);
+-		ecm_opts->bound = true;
++		if (!status)
++			ecm_opts->bound = true;
+ 	}
+-
+ 	mutex_unlock(&ecm_opts->lock);
+ 	if (status)
+ 		return status;
+diff --git a/drivers/usb/gadget/function/f_eem.c b/drivers/usb/gadget/function/f_eem.c
+index 6382cd138d20..3a4fef6b4ec9 100644
+--- a/drivers/usb/gadget/function/f_eem.c
++++ b/drivers/usb/gadget/function/f_eem.c
+@@ -247,31 +247,23 @@ static int eem_bind(struct usb_configuration *c, struct usb_function *f)
+ 	struct usb_composite_dev *cdev = c->cdev;
+ 	struct f_eem		*eem = func_to_eem(f);
+ 	struct usb_string	*us;
+-	int			status;
++	int			status = 0;
+ 	struct usb_ep		*ep;
+ 
+ 	struct f_eem_opts	*eem_opts;
+ 
+ 	eem_opts = container_of(f->fi, struct f_eem_opts, func_inst);
+-	/*
+-	 * in drivers/usb/gadget/configfs.c:configfs_composite_bind()
+-	 * configurations are bound in sequence with list_for_each_entry,
+-	 * in each configuration its functions are bound in sequence
+-	 * with list_for_each_entry, so we assume no race condition
+-	 * with regard to eem_opts->bound access
+-	 */
++
+ 	mutex_lock(&eem_opts->lock);
+ 	gether_set_gadget(eem_opts->net, cdev->gadget);
+-	mutex_unlock(&eem_opts->lock);
+-
+ 	if (!eem_opts->bound) {
+-		mutex_lock(&eem_opts->lock);
+ 		status = gether_register_netdev(eem_opts->net);
+-		mutex_unlock(&eem_opts->lock);
+-		if (status)
+-			return status;
+-		eem_opts->bound = true;
++		if (!status)
++			eem_opts->bound = true;
+ 	}
++	mutex_unlock(&eem_opts->lock);
++	if (status)
++		return status;
+ 
+ 	us = usb_gstrings_attach(cdev, eem_strings,
+ 				 ARRAY_SIZE(eem_string_defs));
+diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c
+index 5e8659050d36..96499743e72f 100644
+--- a/drivers/usb/gadget/function/f_ncm.c
++++ b/drivers/usb/gadget/function/f_ncm.c
+@@ -1454,14 +1454,13 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f)
+ 	if (!ncm_opts->bound) {
+ 		ncm_opts->net->mtu = (ncm_opts->max_segment_size - ETH_HLEN);
+ 		status = gether_register_netdev(ncm_opts->net);
++		if (!status)
++			ncm_opts->bound = true;
+ 	}
+ 	mutex_unlock(&ncm_opts->lock);
+-
+ 	if (status)
+ 		goto fail;
+ 
+-	ncm_opts->bound = true;
+-
+ 	us = usb_gstrings_attach(cdev, ncm_strings,
+ 				 ARRAY_SIZE(ncm_string_defs));
+ 	if (IS_ERR(us)) {
+diff --git a/drivers/usb/gadget/function/f_rndis.c b/drivers/usb/gadget/function/f_rndis.c
+index a15dfb8e6f01..3df56bbfe828 100644
+--- a/drivers/usb/gadget/function/f_rndis.c
++++ b/drivers/usb/gadget/function/f_rndis.c
+@@ -658,7 +658,7 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f)
+ 	struct usb_composite_dev *cdev = c->cdev;
+ 	struct f_rndis		*rndis = func_to_rndis(f);
+ 	struct usb_string	*us;
+-	int			status;
++	int			status = 0;
+ 	struct usb_ep		*ep;
+ 
+ 	struct f_rndis_opts *rndis_opts;
+@@ -681,25 +681,16 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f)
+ 	rndis_iad_descriptor.bFunctionSubClass = rndis_opts->subclass;
+ 	rndis_iad_descriptor.bFunctionProtocol = rndis_opts->protocol;
+ 
+-	/*
+-	 * in drivers/usb/gadget/configfs.c:configfs_composite_bind()
+-	 * configurations are bound in sequence with list_for_each_entry,
+-	 * in each configuration its functions are bound in sequence
+-	 * with list_for_each_entry, so we assume no race condition
+-	 * with regard to rndis_opts->bound access
+-	 */
+ 	mutex_lock(&rndis_opts->lock);
+ 	gether_set_gadget(rndis_opts->net, cdev->gadget);
+-	mutex_unlock(&rndis_opts->lock);
+-
+ 	if (!rndis_opts->bound) {
+-		mutex_lock(&rndis_opts->lock);
+ 		status = gether_register_netdev(rndis_opts->net);
+-		mutex_unlock(&rndis_opts->lock);
+-		if (status)
+-			goto fail;
+-		rndis_opts->bound = true;
++		if (!status)
++			rndis_opts->bound = true;
+ 	}
++	mutex_unlock(&rndis_opts->lock);
++	if (status)
++		goto fail;
+ 
+ 	us = usb_gstrings_attach(cdev, rndis_strings,
+ 				 ARRAY_SIZE(rndis_string_defs));
+diff --git a/drivers/usb/gadget/function/f_subset.c b/drivers/usb/gadget/function/f_subset.c
+index 70448dd67812..3e92ce958a64 100644
+--- a/drivers/usb/gadget/function/f_subset.c
++++ b/drivers/usb/gadget/function/f_subset.c
+@@ -310,16 +310,14 @@ geth_bind(struct usb_configuration *c, struct usb_function *f)
+ 	 */
+ 	mutex_lock(&gether_opts->lock);
+ 	gether_set_gadget(gether_opts->net, cdev->gadget);
+-	mutex_unlock(&gether_opts->lock);
+-
+ 	if (!gether_opts->bound) {
+-		mutex_lock(&gether_opts->lock);
+ 		status = gether_register_netdev(gether_opts->net);
+-		mutex_unlock(&gether_opts->lock);
+-		if (status)
+-			return status;
+-		gether_opts->bound = true;
++		if (!status)
++			gether_opts->bound = true;
+ 	}
++	mutex_unlock(&gether_opts->lock);
++	if (status)
++		return status;
+ 
+ 	us = usb_gstrings_attach(cdev, geth_strings,
+ 				 ARRAY_SIZE(geth_string_defs));
+diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c
+index 1565d2239a34..ba3c989890ff 100644
+--- a/drivers/usb/gadget/function/u_ether.c
++++ b/drivers/usb/gadget/function/u_ether.c
+@@ -112,8 +112,10 @@ static void eth_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *p)
+ 
+ 	strscpy(p->driver, "g_ether", sizeof(p->driver));
+ 	strscpy(p->version, UETH__VERSION, sizeof(p->version));
+-	strscpy(p->fw_version, dev->gadget->name, sizeof(p->fw_version));
+-	strscpy(p->bus_info, dev_name(&dev->gadget->dev), sizeof(p->bus_info));
++	if (dev->gadget) {
++		strscpy(p->fw_version, dev->gadget->name, sizeof(p->fw_version));
++		strscpy(p->bus_info, dev_name(&dev->gadget->dev), sizeof(p->bus_info));
++	}
+ }
+ 
+ /* REVISIT can also support:
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Fix-intptr_t-typedef.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Fix-intptr_t-typedef.patch
new file mode 100644
index 000000000000..cf55d991c638
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Fix-intptr_t-typedef.patch
@@ -0,0 +1,32 @@
+From 64055f3eaffe871f48ff67b8d1ca1633db3c0b1b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 26 Aug 2023 10:55:24 +0200
+Subject: Fix intptr_t typedef
+
+GCC includes the same typedef, but on some 32bit platforms it's defined
+as int, leading to conflicts.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ include/linux/types.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/include/linux/types.h b/include/linux/types.h
+index 2bc8766ba20c..246d8b89d76a 100644
+--- a/include/linux/types.h
++++ b/include/linux/types.h
+@@ -40,7 +40,11 @@ typedef __kernel_uid16_t        uid16_t;
+ typedef __kernel_gid16_t        gid16_t;
+ 
+ typedef unsigned long		uintptr_t;
++#if __SIZEOF_POINTER__ == __SIZEOF_INT__
++typedef int			intptr_t;
++#else
+ typedef long			intptr_t;
++#endif
+ 
+ #ifdef CONFIG_HAVE_UID16
+ /* This is defined by include/asm-{arch}/posix_types.h */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
new file mode 100644
index 000000000000..e0340e0edbb2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
@@ -0,0 +1,30 @@
+From 6fd5e1f859eaab65281913fa082a1fb35ce707b9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 30 Sep 2017 21:31:35 +0200
+Subject: MAINTAINERS: Add entry for Himax HM5065
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ MAINTAINERS | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 958e935449e5..708d773834de 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -9839,6 +9839,12 @@ L:	linux-kernel@vger.kernel.org
+ S:	Maintained
+ F:	drivers/misc/hisi_hikey_usb.c
+ 
++HIMAX HM5065 SENSOR DRIVER
++M:	Ondrej Jirman <kernel@xff.cz>
++L:	linux-media@vger.kernel.org
++S:	Supported
++F:	drivers/media/i2c/hm5065.c
++
+ HIMAX HX83112B TOUCHSCREEN SUPPORT
+ M:	Job Noorman <job@noorman.info>
+ L:	linux-input@vger.kernel.org
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
new file mode 100644
index 000000000000..55e75dc58a9e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
@@ -0,0 +1,39 @@
+From c1d98f14fb92c6692b4987f32a8c1f0b8c91544c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 18 Aug 2017 13:55:48 +0200
+Subject: Make microbuttons on Orange Pi PC and PC 2 work as power off buttons
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts    | 2 +-
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index 927fd1bab07d..f5476cdab8a4 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -91,7 +91,7 @@ gpio-keys {
+ 
+ 		switch-4 {
+ 			label = "sw4";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ 		};
+ 	};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+index 460c0e3d2f97..0d6881c73b4c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -60,7 +60,7 @@ gpio-keys {
+ 
+ 		key-sw4 {
+ 			label = "sw4";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ 			wakeup-source;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
new file mode 100644
index 000000000000..304c4756c3e3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
@@ -0,0 +1,40 @@
+From 2b92534e689cd222fd5a7122f614d5c6e7bab81d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 10 Feb 2020 01:00:12 +0100
+Subject: Mark some slow drivers for async probe with PROBE_PREFER_ASYNCHRONOUS
+
+This makes it faster to boot TBS A711 tablet.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/iio/accel/bma180.c | 1 +
+ drivers/nfc/nxp-nci/i2c.c  | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c
+index 6581772cb0c4..88e796a67324 100644
+--- a/drivers/iio/accel/bma180.c
++++ b/drivers/iio/accel/bma180.c
+@@ -1127,6 +1127,7 @@ static struct i2c_driver bma180_driver = {
+ 		.name	= "bma180",
+ 		.pm	= pm_sleep_ptr(&bma180_pm_ops),
+ 		.of_match_table = bma180_of_match,
++		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ 	},
+ 	.probe		= bma180_probe,
+ 	.remove		= bma180_remove,
+diff --git a/drivers/nfc/nxp-nci/i2c.c b/drivers/nfc/nxp-nci/i2c.c
+index 3ae4b41c59ac..34c4e38cdf8a 100644
+--- a/drivers/nfc/nxp-nci/i2c.c
++++ b/drivers/nfc/nxp-nci/i2c.c
+@@ -348,6 +348,7 @@ static struct i2c_driver nxp_nci_i2c_driver = {
+ 		   .name = NXP_NCI_I2C_DRIVER_NAME,
+ 		   .acpi_match_table = ACPI_PTR(acpi_id),
+ 		   .of_match_table = of_nxp_nci_i2c_match,
++		   .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ 		  },
+ 	.probe = nxp_nci_i2c_probe,
+ 	.id_table = nxp_nci_i2c_id_table,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Revert-clk-qcom-Support-protected-clocks-property.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Revert-clk-qcom-Support-protected-clocks-property.patch
new file mode 100644
index 000000000000..a9200951cf87
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Revert-clk-qcom-Support-protected-clocks-property.patch
@@ -0,0 +1,54 @@
+From f6f2c5e530b20ee133042b5fa499218ef45257a5 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 30 Dec 2019 12:39:31 -0600
+Subject: Revert "clk: qcom: Support 'protected-clocks' property"
+
+Now that protected-clocks is handled in the clk core, this
+driver-specific implementation is redundant.
+
+This reverts commit b181b3b801da8893c8eb706e448dd5111b02de60.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/qcom/common.c | 18 ------------------
+ 1 file changed, 18 deletions(-)
+
+diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
+index 48f81e3a5e80..117e46ec6fee 100644
+--- a/drivers/clk/qcom/common.c
++++ b/drivers/clk/qcom/common.c
+@@ -222,22 +222,6 @@ int qcom_cc_register_sleep_clk(struct device *dev)
+ }
+ EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
+ 
+-/* Drop 'protected-clocks' from the list of clocks to register */
+-static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
+-{
+-	struct device_node *np = dev->of_node;
+-	struct property *prop;
+-	const __be32 *p;
+-	u32 i;
+-
+-	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
+-		if (i >= cc->num_rclks)
+-			continue;
+-
+-		cc->rclks[i] = NULL;
+-	}
+-}
+-
+ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
+ 					 void *data)
+ {
+@@ -300,8 +284,6 @@ int qcom_cc_really_probe(struct platform_device *pdev,
+ 	cc->rclks = rclks;
+ 	cc->num_rclks = num_clks;
+ 
+-	qcom_cc_drop_protected(dev, cc);
+-
+ 	for (i = 0; i < num_clk_hws; i++) {
+ 		ret = devm_clk_hw_register(dev, clk_hws[i]);
+ 		if (ret)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
new file mode 100644
index 000000000000..29ed3ed229f8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
@@ -0,0 +1,28 @@
+From 113ddcb84c8e1258beb92f4878a98ce3bc484a63 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 1 Nov 2020 02:57:38 +0100
+Subject: Revert "drm/sun4i: lvds: Invert the LVDS polarity"
+
+This reverts commit 3bc46a083fa9f475dd2e0ab8717d9839b070b8d9.
+---
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index a1a2c845ade0..b78799dedf62 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -476,7 +476,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
+ 		     SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
+ 		     SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
+ 
+-	reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0;
++	reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
++		SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
++		SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
+ 	if (sun4i_tcon_get_pixel_depth(encoder) == 24)
+ 		reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
+ 	else
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
new file mode 100644
index 000000000000..1dc17fddc8b4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
@@ -0,0 +1,39 @@
+From 173db19bad21fc665ef531d6cf230d8d15104782 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 7 May 2024 18:39:12 +0200
+Subject: Revert "usb: typec: tcpm: unregister existing source caps before
+ re-registration"
+
+This reverts commit 230ecdf71a644c9c73e0e6735b33173074ae3f94.
+---
+ drivers/usb/typec/tcpm/tcpm.c | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index 5d4da962acc8..338426258539 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -3004,7 +3004,7 @@ static int tcpm_register_source_caps(struct tcpm_port *port)
+ {
+ 	struct usb_power_delivery_desc desc = { port->negotiated_rev };
+ 	struct usb_power_delivery_capabilities_desc caps = { };
+-	struct usb_power_delivery_capabilities *cap = port->partner_source_caps;
++	struct usb_power_delivery_capabilities *cap;
+ 
+ 	if (!port->partner_pd)
+ 		port->partner_pd = usb_power_delivery_register(NULL, &desc);
+@@ -3014,11 +3014,6 @@ static int tcpm_register_source_caps(struct tcpm_port *port)
+ 	memcpy(caps.pdo, port->source_caps, sizeof(u32) * port->nr_source_caps);
+ 	caps.role = TYPEC_SOURCE;
+ 
+-	if (cap) {
+-		usb_power_delivery_unregister_capabilities(cap);
+-		port->partner_source_caps = NULL;
+-	}
+-
+ 	cap = usb_power_delivery_register_capabilities(port->partner_pd, &caps);
+ 	if (IS_ERR(cap))
+ 		return PTR_ERR(cap);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/Update-defconfigs.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/Update-defconfigs.patch
new file mode 100644
index 000000000000..f68a9fafd29e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/Update-defconfigs.patch
@@ -0,0 +1,301 @@
+From 91bd14a0e809c6a42ea8e6f1a3ec138ef7a9c9a3 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 12 May 2024 23:36:08 +0200
+Subject: Update defconfigs
+
+---
+ arch/arm/configs/orangepi_defconfig              |  3 +--
+ .../arm/configs/pocketbook_touch_lux_3_defconfig |  2 +-
+ arch/arm/configs/tbs_a711_defconfig              |  3 +--
+ arch/arm64/configs/orangepi_defconfig            | 16 ++++++----------
+ arch/arm64/configs/pinephone_defconfig           |  9 ++++-----
+ arch/arm64/configs/pinephone_multidist_defconfig |  9 ++++-----
+ 6 files changed, 17 insertions(+), 25 deletions(-)
+
+diff --git a/arch/arm/configs/orangepi_defconfig b/arch/arm/configs/orangepi_defconfig
+index 2ebd59970d3b..8dd9219c89d7 100644
+--- a/arch/arm/configs/orangepi_defconfig
++++ b/arch/arm/configs/orangepi_defconfig
+@@ -76,6 +76,7 @@ CONFIG_BLK_CGROUP_IOCOST=y
+ # CONFIG_MQ_IOSCHED_KYBER is not set
+ CONFIG_CMA=y
+ CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_AREAS=7
+ CONFIG_NET=y
+ CONFIG_PACKET=y
+ CONFIG_PACKET_DIAG=y
+@@ -191,7 +192,6 @@ CONFIG_BT_BNEP=y
+ CONFIG_BT_BNEP_MC_FILTER=y
+ CONFIG_BT_BNEP_PROTO_FILTER=y
+ CONFIG_BT_HIDP=y
+-CONFIG_BT_HS=y
+ CONFIG_BT_LEDS=y
+ CONFIG_BT_HCIBTSDIO=y
+ CONFIG_BT_HCIUART=y
+@@ -366,7 +366,6 @@ CONFIG_AXP20X_POWER=y
+ CONFIG_SENSORS_RASPBERRYPI_HWMON=y
+ CONFIG_THERMAL=y
+ CONFIG_THERMAL_STATISTICS=y
+-CONFIG_THERMAL_WRITABLE_TRIPS=y
+ CONFIG_THERMAL_GOV_FAIR_SHARE=y
+ CONFIG_THERMAL_GOV_BANG_BANG=y
+ CONFIG_CPU_THERMAL=y
+diff --git a/arch/arm/configs/pocketbook_touch_lux_3_defconfig b/arch/arm/configs/pocketbook_touch_lux_3_defconfig
+index 2d5db37e86cb..caef90469c39 100644
+--- a/arch/arm/configs/pocketbook_touch_lux_3_defconfig
++++ b/arch/arm/configs/pocketbook_touch_lux_3_defconfig
+@@ -71,6 +71,7 @@ CONFIG_BLK_CGROUP_IOLATENCY=y
+ # CONFIG_MQ_IOSCHED_KYBER is not set
+ CONFIG_CMA=y
+ CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_AREAS=7
+ CONFIG_NET=y
+ CONFIG_PACKET=y
+ CONFIG_PACKET_DIAG=y
+@@ -235,7 +236,6 @@ CONFIG_AXP20X_POWER=y
+ CONFIG_SENSORS_NTC_THERMISTOR=y
+ CONFIG_THERMAL=y
+ CONFIG_THERMAL_STATISTICS=y
+-CONFIG_THERMAL_WRITABLE_TRIPS=y
+ CONFIG_THERMAL_GOV_FAIR_SHARE=y
+ CONFIG_THERMAL_GOV_BANG_BANG=y
+ CONFIG_CPU_THERMAL=y
+diff --git a/arch/arm/configs/tbs_a711_defconfig b/arch/arm/configs/tbs_a711_defconfig
+index f28899833bbf..58ba99e82522 100644
+--- a/arch/arm/configs/tbs_a711_defconfig
++++ b/arch/arm/configs/tbs_a711_defconfig
+@@ -74,6 +74,7 @@ CONFIG_BLK_CGROUP_IOLATENCY=y
+ # CONFIG_BFQ_GROUP_IOSCHED is not set
+ CONFIG_CMA=y
+ CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_AREAS=7
+ CONFIG_NET=y
+ CONFIG_PACKET=y
+ CONFIG_PACKET_DIAG=y
+@@ -168,7 +169,6 @@ CONFIG_BT_BNEP=m
+ CONFIG_BT_BNEP_MC_FILTER=y
+ CONFIG_BT_BNEP_PROTO_FILTER=y
+ CONFIG_BT_HIDP=m
+-CONFIG_BT_HS=y
+ CONFIG_BT_LEDS=y
+ CONFIG_BT_HCIBTSDIO=m
+ CONFIG_BT_HCIUART=m
+@@ -272,7 +272,6 @@ CONFIG_AXP20X_POWER=y
+ # CONFIG_HWMON is not set
+ CONFIG_THERMAL=y
+ CONFIG_THERMAL_STATISTICS=y
+-CONFIG_THERMAL_WRITABLE_TRIPS=y
+ CONFIG_THERMAL_GOV_FAIR_SHARE=y
+ CONFIG_THERMAL_GOV_BANG_BANG=y
+ CONFIG_CPU_THERMAL=y
+diff --git a/arch/arm64/configs/orangepi_defconfig b/arch/arm64/configs/orangepi_defconfig
+index 82f1448bbf14..4ee0756cef5f 100644
+--- a/arch/arm64/configs/orangepi_defconfig
++++ b/arch/arm64/configs/orangepi_defconfig
+@@ -45,15 +45,14 @@ CONFIG_PERF_EVENTS=y
+ CONFIG_ARCH_SUNXI=y
+ CONFIG_ARCH_ROCKCHIP=y
+ # CONFIG_ARM64_ERRATUM_832075 is not set
+-# CONFIG_ARM64_ERRATUM_834220 is not set
+-# CONFIG_ARM64_ERRATUM_1542419 is not set
++CONFIG_ARM64_ERRATUM_2441007=y
++CONFIG_ARM64_ERRATUM_1286807=y
+ # CONFIG_ARM64_ERRATUM_1508412 is not set
+ # CONFIG_ARM64_ERRATUM_2051678 is not set
+ # CONFIG_ARM64_ERRATUM_2077057 is not set
+ # CONFIG_ARM64_ERRATUM_2658417 is not set
+ # CONFIG_ARM64_ERRATUM_2054223 is not set
+ # CONFIG_ARM64_ERRATUM_2067961 is not set
+-# CONFIG_ARM64_ERRATUM_2441009 is not set
+ # CONFIG_ARM64_ERRATUM_2645198 is not set
+ # CONFIG_ARM64_ERRATUM_2966298 is not set
+ # CONFIG_CAVIUM_ERRATUM_22375 is not set
+@@ -212,6 +211,7 @@ CONFIG_NFT_FIB_NETDEV=y
+ CONFIG_NFT_REJECT_NETDEV=y
+ CONFIG_NF_FLOW_TABLE_INET=y
+ CONFIG_NF_FLOW_TABLE=y
++CONFIG_NETFILTER_XTABLES=y
+ CONFIG_IP_SET=y
+ CONFIG_IP_SET_BITMAP_IP=y
+ CONFIG_IP_SET_BITMAP_IPMAC=y
+@@ -235,7 +235,6 @@ CONFIG_NF_TABLES_ARP=y
+ CONFIG_NF_LOG_ARP=y
+ CONFIG_NF_LOG_IPV4=y
+ # CONFIG_NF_NAT_SNMP_BASIC is not set
+-CONFIG_IP_NF_ARPTABLES=y
+ CONFIG_IP_NF_ARPFILTER=y
+ CONFIG_IP_NF_ARP_MANGLE=y
+ CONFIG_NFT_DUP_IPV6=y
+@@ -318,7 +317,6 @@ CONFIG_BT_BNEP=y
+ CONFIG_BT_BNEP_MC_FILTER=y
+ CONFIG_BT_BNEP_PROTO_FILTER=y
+ CONFIG_BT_HIDP=y
+-CONFIG_BT_HS=y
+ CONFIG_BT_LEDS=y
+ CONFIG_BT_HCIBTUSB=y
+ CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
+@@ -548,7 +546,6 @@ CONFIG_SENSORS_ARM_SCPI=y
+ CONFIG_SENSORS_GPIO_FAN=y
+ CONFIG_THERMAL=y
+ CONFIG_THERMAL_STATISTICS=y
+-CONFIG_THERMAL_WRITABLE_TRIPS=y
+ CONFIG_THERMAL_GOV_FAIR_SHARE=y
+ CONFIG_THERMAL_GOV_BANG_BANG=y
+ CONFIG_CPU_THERMAL=y
+@@ -631,11 +628,11 @@ CONFIG_ROCKCHIP_LVDS=y
+ CONFIG_ROCKCHIP_RGB=y
+ CONFIG_DRM_SUN4I=y
+ CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A=y
+-CONFIG_DRM_PANEL_SIMPLE=y
+-CONFIG_DRM_PANEL_EDP=y
+ CONFIG_DRM_PANEL_HIMAX_HX8394=y
+ CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
+ CONFIG_DRM_PANEL_SITRONIX_ST7703=y
++CONFIG_DRM_PANEL_EDP=y
++CONFIG_DRM_PANEL_SIMPLE=y
+ CONFIG_DRM_DISPLAY_CONNECTOR=y
+ CONFIG_DRM_SIMPLE_BRIDGE=y
+ CONFIG_DRM_CDNS_DSI=y
+@@ -829,6 +826,7 @@ CONFIG_MAILBOX=y
+ CONFIG_ROCKCHIP_MBOX=y
+ CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
+ CONFIG_ROCKCHIP_IOMMU=y
++CONFIG_SUN50I_IOMMU=y
+ CONFIG_ARM_SMMU=y
+ CONFIG_ARM_SMMU_V3=y
+ CONFIG_ROCKCHIP_IODOMAIN=y
+@@ -974,7 +972,6 @@ CONFIG_CRYPTO_SEQIV=y
+ CONFIG_CRYPTO_ECHAINIV=y
+ CONFIG_CRYPTO_MD4=y
+ CONFIG_CRYPTO_DEFLATE=y
+-CONFIG_CRYPTO_LZO=y
+ CONFIG_CRYPTO_ZSTD=y
+ CONFIG_CRYPTO_ANSI_CPRNG=y
+ CONFIG_CRYPTO_USER_API_HASH=y
+@@ -989,7 +986,6 @@ CONFIG_CRYPTO_SHA512_ARM64_CE=y
+ CONFIG_CRYPTO_SHA3_ARM64=y
+ CONFIG_CRYPTO_SM3_ARM64_CE=y
+ CONFIG_CRYPTO_AES_ARM64=y
+-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+ CONFIG_CRYPTO_AES_ARM64_BS=y
+ CONFIG_CRYPTO_SM4_ARM64_CE=y
+ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+diff --git a/arch/arm64/configs/pinephone_defconfig b/arch/arm64/configs/pinephone_defconfig
+index 7ac485b54aea..74e9abbf09a3 100644
+--- a/arch/arm64/configs/pinephone_defconfig
++++ b/arch/arm64/configs/pinephone_defconfig
+@@ -42,11 +42,11 @@ CONFIG_ARCH_SUNXI=y
+ # CONFIG_ARM64_ERRATUM_1165522 is not set
+ # CONFIG_ARM64_ERRATUM_1319367 is not set
+ # CONFIG_ARM64_ERRATUM_1530923 is not set
+-# CONFIG_ARM64_ERRATUM_1286807 is not set
++CONFIG_ARM64_ERRATUM_2441007=y
+ # CONFIG_ARM64_ERRATUM_1463225 is not set
+-# CONFIG_ARM64_ERRATUM_1542419 is not set
+ # CONFIG_ARM64_ERRATUM_2051678 is not set
+ # CONFIG_ARM64_ERRATUM_2077057 is not set
++CONFIG_ARM64_ERRATUM_2441009=y
+ # CONFIG_CAVIUM_ERRATUM_22375 is not set
+ # CONFIG_CAVIUM_ERRATUM_23154 is not set
+ # CONFIG_CAVIUM_ERRATUM_27456 is not set
+@@ -59,6 +59,7 @@ CONFIG_ARCH_SUNXI=y
+ # CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
+ # CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
+ # CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
++CONFIG_ARM64_VA_BITS_39=y
+ CONFIG_SCHED_MC=y
+ CONFIG_NR_CPUS=4
+ CONFIG_HZ_100=y
+@@ -107,6 +108,7 @@ CONFIG_PARTITION_ADVANCED=y
+ # CONFIG_MQ_IOSCHED_KYBER is not set
+ CONFIG_CMA=y
+ CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_AREAS=7
+ CONFIG_NET=y
+ CONFIG_PACKET=y
+ CONFIG_PACKET_DIAG=y
+@@ -206,7 +208,6 @@ CONFIG_BT_BNEP=m
+ CONFIG_BT_BNEP_MC_FILTER=y
+ CONFIG_BT_BNEP_PROTO_FILTER=y
+ CONFIG_BT_HIDP=m
+-CONFIG_BT_HS=y
+ CONFIG_BT_LEDS=y
+ CONFIG_BT_HCIUART=m
+ CONFIG_BT_HCIUART_RTL=y
+@@ -325,7 +326,6 @@ CONFIG_AXP20X_POWER=y
+ # CONFIG_HWMON is not set
+ CONFIG_THERMAL=y
+ CONFIG_THERMAL_STATISTICS=y
+-CONFIG_THERMAL_WRITABLE_TRIPS=y
+ CONFIG_THERMAL_GOV_FAIR_SHARE=y
+ CONFIG_THERMAL_GOV_BANG_BANG=y
+ CONFIG_CPU_THERMAL=y
+@@ -624,7 +624,6 @@ CONFIG_CRYPTO_SHA512_ARM64_CE=m
+ CONFIG_CRYPTO_SHA3_ARM64=m
+ CONFIG_CRYPTO_SM3_ARM64_CE=m
+ CONFIG_CRYPTO_AES_ARM64=m
+-CONFIG_CRYPTO_AES_ARM64_CE_BLK=m
+ CONFIG_CRYPTO_AES_ARM64_BS=m
+ CONFIG_CRYPTO_SM4_ARM64_CE=m
+ CONFIG_CRYPTO_AES_ARM64_CE_CCM=m
+diff --git a/arch/arm64/configs/pinephone_multidist_defconfig b/arch/arm64/configs/pinephone_multidist_defconfig
+index 92b9119238c0..9f65f896e251 100644
+--- a/arch/arm64/configs/pinephone_multidist_defconfig
++++ b/arch/arm64/configs/pinephone_multidist_defconfig
+@@ -42,11 +42,11 @@ CONFIG_ARCH_SUNXI=y
+ # CONFIG_ARM64_ERRATUM_1165522 is not set
+ # CONFIG_ARM64_ERRATUM_1319367 is not set
+ # CONFIG_ARM64_ERRATUM_1530923 is not set
+-# CONFIG_ARM64_ERRATUM_1286807 is not set
++CONFIG_ARM64_ERRATUM_2441007=y
+ # CONFIG_ARM64_ERRATUM_1463225 is not set
+-# CONFIG_ARM64_ERRATUM_1542419 is not set
+ # CONFIG_ARM64_ERRATUM_2051678 is not set
+ # CONFIG_ARM64_ERRATUM_2077057 is not set
++CONFIG_ARM64_ERRATUM_2441009=y
+ # CONFIG_CAVIUM_ERRATUM_22375 is not set
+ # CONFIG_CAVIUM_ERRATUM_23154 is not set
+ # CONFIG_CAVIUM_ERRATUM_27456 is not set
+@@ -59,6 +59,7 @@ CONFIG_ARCH_SUNXI=y
+ # CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
+ # CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
+ # CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
++CONFIG_ARM64_VA_BITS_39=y
+ CONFIG_SCHED_MC=y
+ CONFIG_NR_CPUS=4
+ CONFIG_COMPAT=y
+@@ -101,6 +102,7 @@ CONFIG_PARTITION_ADVANCED=y
+ # CONFIG_MQ_IOSCHED_KYBER is not set
+ CONFIG_CMA=y
+ CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_AREAS=7
+ CONFIG_NET=y
+ CONFIG_PACKET=y
+ CONFIG_PACKET_DIAG=y
+@@ -200,7 +202,6 @@ CONFIG_BT_BNEP=y
+ CONFIG_BT_BNEP_MC_FILTER=y
+ CONFIG_BT_BNEP_PROTO_FILTER=y
+ CONFIG_BT_HIDP=y
+-CONFIG_BT_HS=y
+ CONFIG_BT_LEDS=y
+ CONFIG_BT_HCIUART=y
+ CONFIG_BT_HCIUART_RTL=y
+@@ -320,7 +321,6 @@ CONFIG_AXP20X_POWER=y
+ # CONFIG_HWMON is not set
+ CONFIG_THERMAL=y
+ CONFIG_THERMAL_STATISTICS=y
+-CONFIG_THERMAL_WRITABLE_TRIPS=y
+ CONFIG_THERMAL_GOV_FAIR_SHARE=y
+ CONFIG_THERMAL_GOV_BANG_BANG=y
+ CONFIG_CPU_THERMAL=y
+@@ -575,7 +575,6 @@ CONFIG_CRYPTO_SHA512_ARM64_CE=y
+ CONFIG_CRYPTO_SHA3_ARM64=y
+ CONFIG_CRYPTO_SM3_ARM64_CE=y
+ CONFIG_CRYPTO_AES_ARM64=y
+-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+ CONFIG_CRYPTO_AES_ARM64_BS=y
+ CONFIG_CRYPTO_SM4_ARM64_CE=y
+ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
new file mode 100644
index 000000000000..dcf544b16d96
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
@@ -0,0 +1,35 @@
+From 3bdaf7b5a25eeb534db1d4e172d98d16f626d6fd Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Mon, 20 Jul 2020 01:11:34 +0800
+Subject: arm64: allwinner: dts: a64: enable K101-IM2BYL02 panel for PineTab
+
+Newer PineTab may switch to K101-IM2BYL02.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 840cd2631289..9bc1f71bdf5c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -200,12 +200,10 @@ &dsi {
+ 	status = "okay";
+ 
+ 	panel@0 {
+-		compatible = "feixin,k101-im2ba02";
++		compatible = "feixin,k101-im2byl02";
+ 		reg = <0>;
+-		avdd-supply = <&reg_dc1sw>;
+-		dvdd-supply = <&reg_dc1sw>;
+-		cvdd-supply = <&reg_ldo_io1>;
+-		reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
++		power-supply = <&reg_dc1sw>;
++		reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+ 		backlight = <&backlight>;
+ 	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
new file mode 100644
index 000000000000..7ddc43b1ad95
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
@@ -0,0 +1,66 @@
+From 9ff6d692b11a162aaef0312a32c306d57220da03 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 6 Dec 2020 11:15:34 -0600
+Subject: arm64: dts: allwinner: Enforce consistent MMC numbering
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 ++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  | 6 ++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 6 ++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 6cc777395553..aa00b7e709c3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -18,6 +18,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	chosen {
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index a6a2e2a19e75..080c3d10fdfa 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -6,6 +6,12 @@
+ #include <dt-bindings/thermal/thermal.h>
+ 
+ / {
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 14c2134bc6dc..ce355bd3e2e2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -17,6 +17,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Add-SCPI-protocol.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..c97cf3f6882c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Add-SCPI-protocol.patch
@@ -0,0 +1,51 @@
+From 7a7d865d32daab9ef8cba9bb99046684226310f9 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 14 Dec 2019 20:52:53 -0600
+Subject: arm64: dts: allwinner: a64: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index c36243023206..1a7506292b62 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -140,6 +140,13 @@ psci {
+ 		method = "smc";
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	sound: sound {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -368,6 +375,19 @@ syscon: syscon@1c00000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0x14000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0x14000>;
++
++				scpi_sram: scp-shmem@13c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x13c00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@18000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00018000 0x28000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..3e7140988653
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From 98817d01b8d0bbb9d8106e899633647581939fee Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 10:39:56 +0200
+Subject: arm64: dts: allwinner: a64: Add hdmi sound card
+
+A64 supports HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index ce4aa44c3353..9f91ad2cf569 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -169,6 +169,20 @@ link0_codec: codec {
+ 		};
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun50i-a64-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		allwinner,erratum-unknown1;
+@@ -1216,6 +1230,7 @@ deinterlace: deinterlace@1e00000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-a64-dw-hdmi",
+ 				     "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
new file mode 100644
index 000000000000..b1c7694708e6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
@@ -0,0 +1,204 @@
+From 10c077fedc1ad63aed08c27e63c26875aedd9b52 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 10:42:16 +0200
+Subject: arm64: dts: allwinner: a64: Enable hdmi sound card on boards with
+ hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all A64 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts   | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts    | 7 +++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts       | 8 ++++++++
+ .../boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts    | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts      | 8 ++++++++
+ 7 files changed, 55 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+index d1f415acd7b5..0b68888c9eef 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+@@ -130,6 +130,10 @@ &i2c1_pins {
+ 	bias-pull-up;
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -341,6 +345,10 @@ &sound {
+ 			"MIC1", "Onboard Microphone";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+index dec9960a7440..b6142224c329 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+@@ -102,6 +102,10 @@ &i2c1_pins {
+ 	bias-pull-up;
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -252,6 +256,10 @@ &simplefb_hdmi {
+ 	vcc-hdmi-supply = <&reg_dldo1>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+index fd3794678c33..0cc2e11dcb92 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+@@ -120,6 +120,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -355,6 +359,9 @@ &sound {
+ 		    "MIC1", "Microphone Jack Left",
+ 		    "Microphone Jack Right", "MBIAS",
+ 		    "MIC2", "Microphone Jack Right";
++};
++
++&sound_hdmi {
+ 	status = "okay";
+ };
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+index c8303a66438d..9194ca4b1e19 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+@@ -137,6 +137,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -340,6 +344,10 @@ &sound {
+ 			"MIC1", "Onboard Microphone";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spi0 {
+ 	status = "okay";
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index 2accb5ddf783..17886709b6b4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -107,6 +107,10 @@ &i2c1_pins {
+ 	bias-pull-up;
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rmii_phy1: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -270,6 +274,10 @@ &sound {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ /* On Euler connector */
+ &spdif {
+ 	status = "disabled";
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+index 5e66ce1a334f..970d528378db 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -96,6 +96,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -169,6 +173,10 @@ &sound {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
+index b407e1dd08a7..d323b52a186d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
+@@ -150,6 +150,10 @@ anx6345_in: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mixer0 {
+ 	status = "okay";
+ };
+@@ -366,6 +370,10 @@ &sound {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &tcon0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&lcd_rgb666_pins>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
new file mode 100644
index 000000000000..630d5257b518
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
@@ -0,0 +1,32 @@
+From 23b07bc39d9cc51bd0838adfb31fbdf6fd8fa45d Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Sun, 30 Jun 2019 22:45:34 +0800
+Subject: arm64: dts: allwinner: a64: Fix LRADC compatible
+
+The LRADC reference voltage of A64 is 2.0V, and AVCC is 3.0V. So the
+internal voltage divider is 2/3 (the A10 value), not 3/4 (the A83T
+value).
+
+Fix the compatible string of the A64 LRADC.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 0e27a4e0a092..6cc777395553 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -915,7 +915,7 @@ spdif: spdif@1c21000 {
+ 
+ 		lradc: lradc@1c21800 {
+ 			compatible = "allwinner,sun50i-a64-lradc",
+-				     "allwinner,sun8i-a83t-r-lradc";
++				     "allwinner,sun4i-a10-lradc-keys";
+ 			reg = <0x01c21800 0x400>;
+ 			interrupt-parent = <&r_intc>;
+ 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Protect-SCP-clocks.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Protect-SCP-clocks.patch
new file mode 100644
index 000000000000..d8d9ea02d8c3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-Protect-SCP-clocks.patch
@@ -0,0 +1,33 @@
+From b896fc88a23c020410d4ce8b38dbc90ec6b70004 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 30 Dec 2019 15:10:32 -0600
+Subject: arm64: dts: allwinner: a64: Protect SCP clocks
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index e807b13240b8..c36243023206 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -670,6 +670,7 @@ ccu: clock@1c20000 {
+ 			reg = <0x01c20000 0x400>;
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
+ 			clock-names = "hosc", "losc";
++			protected-clocks = <CLK_BUS_MSGBOX>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+@@ -1306,6 +1307,7 @@ r_ccu: clock@1f01400 {
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
+ 				 <&ccu CLK_PLL_PERIPH0>;
+ 			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			protected-clocks = <CLK_APB0_TWD>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
new file mode 100644
index 000000000000..97d289023f8c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
@@ -0,0 +1,99 @@
+From 262480096384af154bb668d017f1cd3fecf60d31 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 17 Nov 2020 01:06:30 +0100
+Subject: arm64: dts: allwinner: a64: pinetab: add front camera
+
+---
+ .../boot/dts/allwinner/sun50i-a64-pinetab.dts | 50 ++++++++++++++++---
+ 1 file changed, 44 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index c6007df99938..840cd2631289 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -55,12 +55,35 @@ i2c-csi {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
++		/* Front camera */
++		gc2145: front-camera@3c {
++			compatible = "galaxycore,gc2145";
++			reg = <0x3c>;
++			clocks = <&ccu CLK_CSI_MCLK>;
++			clock-names = "xclk";
++
++			AVDD-supply = <&reg_dldo3>;
++			DVDD-supply = <&reg_aldo1>;
++			IOVDD-supply = <&reg_eldo3>;
++			reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
++			enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
++
++			port {
++				gc2145_ep: endpoint {
++					remote-endpoint = <&csi_gc2145_ep>;
++					bus-width = <8>;
++					hsync-active = <1>;
++					vsync-active = <1>;
++					data-active = <1>;
++					pclk-sample = <1>;
++				};
++			};
++		};
++
+ 		/* Rear camera */
+-		ov5640: camera@3c {
++		ov5640: rear-camera@4c {
+ 			compatible = "ovti,ov5640";
+-			reg = <0x3c>;
+-			pinctrl-names = "default";
+-			pinctrl-0 = <&csi_mclk_pin>;
++			reg = <0x4c>;
+ 			clocks = <&ccu CLK_CSI_MCLK>;
+ 			clock-names = "xclk";
+ 
+@@ -72,7 +95,7 @@ ov5640: camera@3c {
+ 
+ 			port {
+ 				ov5640_ep: endpoint {
+-					remote-endpoint = <&csi_ep>;
++					remote-endpoint = <&csi_ov5640_ep>;
+ 					bus-width = <8>;
+ 					hsync-active = <1>; /* Active high */
+ 					vsync-active = <0>; /* Active low */
+@@ -131,10 +154,15 @@ &cpu3 {
+ };
+ 
+ &csi {
++	pinctrl-0 = <&csi_pins>, <&csi_mclk_pin>;
+ 	status = "okay";
+ 
+ 	port {
+-		csi_ep: endpoint {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi_ov5640_ep: endpoint@0 {
++			reg = <0>;
+ 			remote-endpoint = <&ov5640_ep>;
+ 			bus-width = <8>;
+ 			hsync-active = <1>; /* Active high */
+@@ -142,6 +170,16 @@ csi_ep: endpoint {
+ 			data-active = <1>;  /* Active high */
+ 			pclk-sample = <1>;  /* Rising */
+ 		};
++
++		csi_gc2145_ep: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&gc2145_ep>;
++			bus-width=<8>;
++			hsync-active = <1>; /* Active high */
++			vsync-active = <1>; /* Active high */
++			data-active = <1>;  /* Active high */
++			pclk-sample = <1>;  /* Rising */
++		};
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
new file mode 100644
index 000000000000..6f82e848ff09
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
@@ -0,0 +1,113 @@
+From 94c4e757eb47d55297271dcd8389391fe0be615f Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 12:40:31 +0200
+Subject: arm64: dts: allwinner: h5: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all H5 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts  | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 8 ++++++++
+ .../arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 8 ++++++++
+ .../boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts  | 8 ++++++++
+ 4 files changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
+index 076a0b983101..5882b62097a9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
+@@ -69,3 +69,11 @@ hdmi_out_con: endpoint {
+ &i2c1 {
+ 	status = "okay";
+ };
++
++&i2s2 {
++	status = "okay";
++};
++
++&sound_hdmi {
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+index ce3ae19e72db..460c0e3d2f97 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -145,6 +145,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -190,6 +194,10 @@ reg_vdd_cpux: regulator@65 {
+ 	};
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spi0  {
+ 	status = "okay";
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index b699bb900e13..b21bfc3f8624 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -145,6 +145,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -182,6 +186,10 @@ &ohci3 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+index 734481e998b8..c4b79e88163d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+@@ -77,6 +77,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -115,6 +119,10 @@ &ohci0 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..412223b12ee1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
@@ -0,0 +1,51 @@
+From b68858a9a3d0be74161c059f893d81828ea6b1d9 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 14 Dec 2019 20:54:40 -0600
+Subject: arm64: dts: allwinner: h6: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 0a1c673180cb..bf18ca27dea2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -103,6 +103,13 @@ cpu {
+ 		};
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -223,6 +230,19 @@ syscon: syscon@3000000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@100000 {
++				compatible = "mmio-sram";
++				reg = <0x00100000 0x18000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00100000 0x18000>;
++
++				scpi_sram: scp-shmem@17c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x17c00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@28000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00028000 0x1e000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..6ed7eb4e3a9b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
@@ -0,0 +1,56 @@
+From d0105885c81d43f4ba5b84eb3d4e03aa8312db6e Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Tue, 10 Nov 2020 20:43:28 +0100
+Subject: arm64: dts: allwinner: h6: Add hdmi sound card
+
+H6 supports HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 8a8591c4e7dd..511eb446b525 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -89,6 +89,20 @@ psci {
+ 		method = "smc";
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun50i-h6-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s1>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -102,6 +116,7 @@ timer {
+ 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ 	};
+ 
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -780,6 +795,7 @@ ohci3: usb@5311400 {
+ 		};
+ 
+ 		hdmi: hdmi@6000000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-h6-dw-hdmi";
+ 			reg = <0x06000000 0x10000>;
+ 			reg-io-width = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
new file mode 100644
index 000000000000..deb294bdb3ec
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
@@ -0,0 +1,123 @@
+From 38212aab1b3e84a9d687078bf1347de2a40d79f0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 11 Jan 2022 13:08:47 +0100
+Subject: arm64: dts: allwinner: h6: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all H6 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts  | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi   | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts    | 8 ++++++++
+ 4 files changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+index 3be1e8c2fdb9..10d0bd39c94f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+@@ -119,6 +119,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -290,6 +294,10 @@ sw {
+ 	};
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spdif {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spdif_tx_pin>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index f32f95c8ed5e..a8eaa98fef1b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -167,6 +167,10 @@ ext_rgmii_phy: ethernet-phy@1 {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+@@ -339,6 +343,10 @@ &rtc {
+ 	clocks = <&ext_osc32k>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_ph_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+index 13b07141c334..e5b7c7f2f7f7 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+@@ -91,6 +91,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+@@ -244,6 +248,10 @@ &rtc {
+ 	clocks = <&ext_osc32k>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_ph_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+index 3910393be1f9..c06b61e23103 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+@@ -123,6 +123,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -298,6 +302,10 @@ &rtc {
+ 	clocks = <&ext_osc32k>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ /*
+  * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI
+  * flash and eMMC at the same time, as one of them would fail probing.
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
new file mode 100644
index 000000000000..e837b2880c83
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
@@ -0,0 +1,33 @@
+From a5652f6f08c3c957751f8d432b45a071e513d7c3 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:04:01 -0600
+Subject: arm64: dts: allwinner: h6: Protect SCP clocks
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 511eb446b525..0a1c673180cb 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -257,6 +257,7 @@ ccu: clock@3001000 {
+ 			reg = <0x03001000 0x1000>;
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
+ 			clock-names = "hosc", "losc", "iosc";
++			protected-clocks = <CLK_BUS_MSGBOX>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+@@ -952,6 +953,7 @@ r_ccu: clock@7010000 {
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
+ 				 <&ccu CLK_PLL_PERIPH0>;
+ 			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			protected-clocks = <CLK_R_APB1_TWD>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
new file mode 100644
index 000000000000..3a6ddfcb65cc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
@@ -0,0 +1,105 @@
+From 749aa6345f8b2154e9b7cb03719951bf5b1d53a8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 20 Aug 2019 14:54:48 +0200
+Subject: arm64: dts: allwinner: orange-pi-3: Enable ethernet
+
+Orange Pi 3 has two regulators that power the Realtek RTL8211E
+PHY. According to the datasheet, both regulators need to be enabled
+at the same time, or that "phy-io" should be enabled slightly earlier
+than "phy" regulator.
+
+RTL8211E/RTL8211EG datasheet says:
+
+  Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously
+  or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power
+  later than 3.3V power may lead to errors.
+
+The driver ensures the regulator enable ordering. The timing is set
+in DT via startup-delay-us.
+
+We also need to wait at least 30ms after power-up/reset, before
+accessing the PHY registers.
+
+All values of RX/TX delay were tested exhaustively and a middle one
+of the range of working values was chosen.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-h6-orangepi-3.dts    | 40 +++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index 6c3bfe3d09d9..f32f95c8ed5e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -15,6 +15,7 @@ / {
+ 	aliases {
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
++		ethernet0 = &emac;
+ 	};
+ 
+ 	chosen {
+@@ -64,6 +65,15 @@ reg_vcc5v: vcc5v {
+ 		regulator-always-on;
+ 	};
+ 
++	reg_gmac_2v5: gmac-2v5 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-2v5";
++		regulator-min-microvolt = <2500000>;
++		regulator-max-microvolt = <2500000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++	};
++
+ 	reg_vcc33_wifi: vcc33-wifi {
+ 		/* Always on 3.3V regulator for WiFi and BT */
+ 		compatible = "regulator-fixed";
+@@ -128,6 +138,35 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii-id";
++	phy-handle = <&ext_rgmii_phy>;
++	/*
++	 * The board uses 2.5V RGMII signalling. Power sequence to enable
++	 * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails
++	 * at the same time and to wait 100ms. The driver enables phy-io
++	 * first. Delay is achieved with enable-ramp-delay on reg_aldo2.
++	 */
++	phy-supply = <&reg_aldo2>;
++	phy-io-supply = <&reg_gmac_2v5>;
++	allwinner,rx-delay-ps = <200>;
++	allwinner,tx-delay-ps = <200>;
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++
++		reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
++		reset-assert-us = <15000>;
++		reset-deassert-us = <40000>;
++	};
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+@@ -211,6 +250,7 @@ reg_aldo2: aldo2 {
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+ 				regulator-name = "vcc33-audio-tv-ephy-mac";
++				regulator-enable-ramp-delay = <100000>;
+ 			};
+ 
+ 			/* ALDO3 is shorted to CLDO1 */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
new file mode 100644
index 000000000000..b66d0aea7e81
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
@@ -0,0 +1,47 @@
+From 497f21855c947ea28c4e5b21288132501ea5bd45 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 24 Sep 2022 21:59:07 +0200
+Subject: arm64: dts: rockchip: rk356x: Fix PCIe register map and ranges
+
+I have two Realtek PCIe wifi cards connected over the 4 port PCIe bridge
+to Quartz64-A. The cards fail to work, when nvme SSD is connected at the
+same time to the bridge. Without nvme connected, cards work fine. The
+issue seems to be related to mixed use of devices which make use of I/O
+ranges and memory ranges.
+
+This patch changes I/O, MEM and config mappings so that config and I/O
+mappings use the 0xf4000000 outbound address space, and MEM range uses
+the whole 0x300000000 outbound space.
+
+These values were suggested by pgwipeout:
+
+  https://lore.kernel.org/lkml/875ygbsrf3.fsf@bloch.sibelius.xs4all.nl/T/#m84b5f6992cc26dffe0d3783c0d8c9c86e5e10c10
+
+This is identical to how BSP does the mappings.
+
+This change to the regs/ranges makes the issue go away and both nvme and
+wifi cards work when connected at the same time to the bridge. I tested
+the nvme with large amount of reads/writes, both behind the PCIe bridge
+and when directly connected to Quartz64-A board.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+index 3e2a8bfcafea..a9c6d7695f95 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1036,7 +1036,7 @@ pcie2x1: pcie@fe260000 {
+ 				<0 0 0 4 &pcie_intc 3>;
+ 		linux,pci-domain = <0>;
+ 		num-ib-windows = <6>;
+-		num-ob-windows = <2>;
++		num-ob-windows = <8>;
+ 		max-link-speed = <2>;
+ 		msi-map = <0x0 &gic 0x0 0x1000>;
+ 		num-lanes = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch
new file mode 100644
index 000000000000..958b248460e4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch
@@ -0,0 +1,30 @@
+From afc255dfb0adce483c6c7d6090ea34abc3dd4db1 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 14 May 2024 10:47:05 +0200
+Subject: arm64: dts: sun50-a64-pinephone: Define jack pins in DT
+
+To restore pre v6.8 behavior of the sound card.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 9cdef78a4abd..f82116abfecd 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -978,6 +978,10 @@ &sound {
+ 			"MIC1", "Internal Microphone",
+ 			"Headset Microphone", "HBIAS",
+ 			"MIC2", "Headset Microphone";
++	simple-audio-card,jack-pins =
++			"1c22e00.codec", "Headphone Jack",
++			"1c22e00.codec", "Headset Microphone";
++	simple-audio-card,jack-pins-mask = <1>, <2>;
+ 
+ 	simple-audio-card,dai-link@1 {
+ 		format = "dsp_a";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-Add-missing-trip-points-for-GPU.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-Add-missing-trip-points-for-GPU.patch
new file mode 100644
index 000000000000..2ea69523998e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-Add-missing-trip-points-for-GPU.patch
@@ -0,0 +1,51 @@
+From afeeddba723266c5795f4ea0647918d0d2e1dec3 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 16 Oct 2022 23:20:59 +0200
+Subject: arm64: dts: sun50i-a64: Add missing trip points for GPU
+
+Linux 6.1 requires them.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 1a7506292b62..0e27a4e0a092 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -257,6 +257,15 @@ gpu0_thermal: gpu0-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 1>;
++
++			trips {
++				gpu0_crit: gpu-crit {
++					/* milliCelsius */
++					temperature = <110000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
+ 		};
+ 
+ 		gpu1_thermal: gpu1-thermal {
+@@ -264,6 +273,15 @@ gpu1_thermal: gpu1-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 2>;
++
++			trips {
++				gpu1_crit: gpu-crit {
++					/* milliCelsius */
++					temperature = <110000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
+ 		};
+ 	};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
new file mode 100644
index 000000000000..e3e8968fdc48
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
@@ -0,0 +1,59 @@
+From 9ca799eec3485a9eb041428ca7038bab9c52434f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 1 Feb 2020 23:41:18 +0100
+Subject: arm64: dts: sun50i-a64: Set fifo-size for uarts
+
+Boot time optimization.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 9f91ad2cf569..e807b13240b8 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -967,6 +967,7 @@ uart0: serial@1c28000 {
+ 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART0>;
+ 			resets = <&ccu RST_BUS_UART0>;
+ 			status = "disabled";
+@@ -978,6 +979,7 @@ uart1: serial@1c28400 {
+ 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART1>;
+ 			resets = <&ccu RST_BUS_UART1>;
+ 			status = "disabled";
+@@ -989,6 +991,7 @@ uart2: serial@1c28800 {
+ 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART2>;
+ 			resets = <&ccu RST_BUS_UART2>;
+ 			status = "disabled";
+@@ -1000,6 +1003,7 @@ uart3: serial@1c28c00 {
+ 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART3>;
+ 			resets = <&ccu RST_BUS_UART3>;
+ 			status = "disabled";
+@@ -1011,6 +1015,7 @@ uart4: serial@1c29000 {
+ 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART4>;
+ 			resets = <&ccu RST_BUS_UART4>;
+ 			status = "disabled";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-AF8133J-to-PinePhone.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-AF8133J-to-PinePhone.patch
new file mode 100644
index 000000000000..5dc4fbd72ffb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-AF8133J-to-PinePhone.patch
@@ -0,0 +1,40 @@
+From 7010a1a9b005c3c2a428977b3d70aa75c80a5d4e Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Thu, 18 Mar 2021 20:22:05 +0800
+Subject: arm64: dts: sun50i-a64-pinephone: Add AF8133J to PinePhone
+
+New batches of PinePhones switched the magnetometer to AF8133J from
+LIS3MDL because lack of ST components.
+
+Add this magnetometer to the device tree. These two sensors do not
+conflict with each other, and the non-existent sensor's driver won't
+just get probed properly.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 0a8352147280..694d715ff875 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -499,6 +499,15 @@ &i2c1 {
+ 	status = "okay";
+ 	clock-frequency = <400000>;
+ 
++	/* Alternative magnetometer */
++	af8133j: magnetometer@1c {
++		compatible = "voltafield,af8133j";
++		reg = <0x1c>;
++		reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>;
++		avdd-supply = <&reg_dldo1>;
++		dvdd-supply = <&reg_dldo1>;
++	};
++
+ 	/* Magnetometer */
+ 	lis3mdl: magnetometer@1e {
+ 		compatible = "st,lis3mdl-magn";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
new file mode 100644
index 000000000000..f3372aa27773
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
@@ -0,0 +1,416 @@
+From 99d12ffe0c61c3bd89c55d9bc646783e41a031bd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Jul 2020 00:58:16 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add Type-C support for all PP
+ variants 1.0-1.2
+
+There are differences in GPIO and how VBUS is handled. Describe them
+in DTS. Thankfully we can support both unmodded and modded variants
+of 1.0 and 1.1 boards with one DTS. No need for more subvariants.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../allwinner/sun50i-a64-pinephone-1.0.dts    | 86 +++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.1.dts    | 86 +++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.2.dts    | 60 +++++++++++++
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 68 ++++++++++++++-
+ 4 files changed, 299 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index 219f720b8b7d..498ae493d176 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -8,6 +8,92 @@
+ / {
+ 	model = "Pine64 PinePhone Developer Batch (1.0)";
+ 	compatible = "pine64,pinephone-1.0", "pine64,pinephone", "allwinner,sun50i-a64";
++
++	reg_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++		enable-active-high;
++		vin-supply = <&reg_drivevbus>;
++	};
++};
++
++&axp803 {
++	x-powers,drive-vbus-en;
++};
++
++&i2c0 {
++	hdmi-bridge@28 {
++		compatible = "analogix,anx7688";
++		reg = <0x28>;
++
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_FALLING>; /* PL11 */
++
++		enable-gpios = <&pio 3 10 GPIO_ACTIVE_LOW>; /* PD10 */
++		reset-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++
++		cabledet-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++
++		avdd10-supply = <&reg_anx1v0>;
++		dvdd10-supply = <&reg_anx1v0>;
++		/* This is for the HW hack variant, but will also work for non-modified version. */
++		avdd18-supply = <&reg_ldo_io1>;
++		dvdd18-supply = <&reg_ldo_io1>;
++		avdd33-supply = <&reg_dldo1>;
++		vconn-supply = <&reg_vconn5v0>;
++		hdmi_vt-supply = <&reg_dldo1>;
++
++		source-caps = <
++			PDO_FIXED(5000, 500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		sink-caps = <
++			PDO_FIXED(5000, 3000, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		/*
++		 * ANX7688 can't enable/disable USB-5V <-> DCIN switch by
++		 * itself, and PMIC's N_VBUSEN is not connected anywhere either,
++		 * so we need to configure everything in software:
++		 *
++		 * - get the VBUS status from ANX7688 via I2C
++		 * - configure PMIC to let it know vbus drive status (via
++		 *   reg_drivevbus)
++		 * - enable VBUS switch and USB-5V regulator (via reg_vbus
++		 *   and reg_usb_5v)
++		 */
++		vbus-supply = <&reg_vbus>;
++		vbus_in-supply = <&usb_power_supply>;
++
++		port {
++			typec0_dr_sw: endpoint {
++				remote-endpoint = <&usb0_drd_sw>;
++			};
++		};
++	};
++};
++
++/*
++ * The N_VBUSEN pin is disconnected, but we need to inform the PMIC about
++ * the VBUS status anyway. To avoid the pin from floating and to inform
++ * the PMIC, about VBUS status, we couple reg_drivevbus with reg_vbus.
++ */
++&reg_drivevbus {
++	vin-supply = <&reg_usb_5v>;
++	status = "okay";
++};
++
++&usbphy {
++	usb-role-switch;
++
++	port {
++		usb0_drd_sw: endpoint {
++			remote-endpoint = <&typec0_dr_sw>;
++		};
++	};
+ };
+ 
+ &codec_analog {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 723af64a9cee..73275308f484 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -8,6 +8,20 @@
+ / {
+ 	model = "Pine64 PinePhone Braveheart (1.1)";
+ 	compatible = "pine64,pinephone-1.1", "pine64,pinephone", "allwinner,sun50i-a64";
++
++	reg_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++		enable-active-high;
++		vin-supply = <&reg_drivevbus>;
++	};
++};
++
++&axp803 {
++	x-powers,drive-vbus-en;
+ };
+ 
+ &backlight {
+@@ -33,7 +47,79 @@ &codec_analog {
+ 	allwinner,internal-bias-resistor;
+ };
+ 
++&i2c0 {
++	hdmi-bridge@28 {
++		compatible = "analogix,anx7688";
++		reg = <0x28>;
++
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_FALLING>; /* PL11 */
++
++		enable-gpios = <&pio 3 10 GPIO_ACTIVE_LOW>; /* PD10 */
++		reset-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++
++		cabledet-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++
++		avdd10-supply = <&reg_anx1v0>;
++		dvdd10-supply = <&reg_anx1v0>;
++		/* This is for the HW hack variant, but will also work for non-modified version. */
++		avdd18-supply = <&reg_ldo_io1>;
++		dvdd18-supply = <&reg_ldo_io1>;
++		avdd33-supply = <&reg_dldo1>;
++		vconn-supply = <&reg_vconn5v0>;
++		hdmi_vt-supply = <&reg_dldo1>;
++
++		source-caps = <
++			PDO_FIXED(5000, 500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		sink-caps = <
++			PDO_FIXED(5000, 3000, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		/*
++		 * ANX7688 can't enable/disable USB-5V <-> DCIN switch by
++		 * itself, and PMIC's N_VBUSEN is not connected anywhere either,
++		 * so we need to configure everything in software:
++		 *
++		 * - get the VBUS status from ANX7688 via I2C
++		 * - configure PMIC to let it know vbus drive status (via
++		 *   reg_drivevbus)
++		 * - enable VBUS switch and USB-5V regulator (via reg_vbus
++		 *   and reg_usb_5v)
++		 */
++		vbus-supply = <&reg_vbus>;
++		vbus_in-supply = <&usb_power_supply>;
++
++		port {
++			typec0_dr_sw: endpoint {
++				remote-endpoint = <&usb0_drd_sw>;
++			};
++		};
++	};
++};
++
++/*
++ * The N_VBUSEN pin is disconnected, but we need to inform the PMIC about
++ * the VBUS status anyway. To avoid the pin from floating and to inform
++ * the PMIC, about VBUS status, we couple reg_drivevbus with reg_vbus.
++ */
++&reg_drivevbus {
++	vin-supply = <&reg_usb_5v>;
++	status = "okay";
++};
++
+ &sgm3140 {
+ 	enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
++
++&usbphy {
++	usb-role-switch;
++
++	port {
++		usb0_drd_sw: endpoint {
++			remote-endpoint = <&typec0_dr_sw>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index 4e7e237cb46a..40127186606f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -48,7 +48,67 @@ &mmc1 {
+ 	mmc-pwrseq = <&wifi_pwrseq>;
+ };
+ 
++&i2c0 {
++	hdmi-bridge@28 {
++		compatible = "analogix,anx7688";
++		reg = <0x28>;
++
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_FALLING>; /* PL11 */
++
++		enable-gpios = <&pio 3 10 GPIO_ACTIVE_LOW>; /* PD10 */
++		reset-gpios = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++
++		cabledet-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++
++		avdd10-supply = <&reg_anx1v0>;
++		dvdd10-supply = <&reg_anx1v0>;
++		avdd18-supply = <&reg_ldo_io1>;
++		dvdd18-supply = <&reg_ldo_io1>;
++		avdd33-supply = <&reg_dcdc1>;
++		vconn-supply = <&reg_vconn5v0>;
++		hdmi_vt-supply = <&reg_dldo1>;
++
++		source-caps = <
++			PDO_FIXED(5000, 500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		sink-caps = <
++			PDO_FIXED(5000, 3000, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		/*
++		 * ANX7688 will enable/disable USB-5V <-> DCIN switch by itself
++		 * via VBUS_CTRL pin. The driver just has to enable the USB-5V
++		 * so that the switch has power.
++		 */
++		vbus-supply = <&reg_usb_5v>;
++		vbus_in-supply = <&usb_power_supply>;
++
++		port {
++			typec0_dr_sw: endpoint {
++				remote-endpoint = <&usb0_drd_sw>;
++			};
++		};
++	};
++};
++
++&reg_anx1v0 {
++	gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */
++	enable-active-high;
++};
++
+ &sgm3140 {
+ 	enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
++
++&usbphy {
++	usb-role-switch;
++
++	port {
++		usb0_drd_sw: endpoint {
++			remote-endpoint = <&typec0_dr_sw>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 44b18d5a9d93..d126c9e9a605 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -10,6 +10,7 @@
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/usb/pd.h>
+ 
+ / {
+ 	chassis-type = "handset";
+@@ -70,6 +71,24 @@ led2: led-2 {
+ 		};
+ 	};
+ 
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	reg_anx1v0: anx1v0 {
++		compatible = "regulator-fixed";
++		regulator-name = "anx1v0";
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1000000>;
++	};
++
+ 	multi-led {
+ 		compatible = "leds-group-multicolor";
+ 		color = <LED_COLOR_ID_RGB>;
+@@ -85,6 +104,24 @@ reg_ps: ps-regulator {
+ 		regulator-boot-on;
+ 	};
+ 
++	reg_usb_5v: usb-5v {
++		compatible = "regulator-fixed";
++		regulator-name = "usb-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 8 GPIO_ACTIVE_HIGH>; /* PD8 */
++		enable-active-high;
++	};
++
++	reg_vbat_bb: vbat-bb {
++		compatible = "regulator-fixed";
++		regulator-name = "vbat-bb";
++		regulator-min-microvolt = <3500000>;
++		regulator-max-microvolt = <3500000>;
++		gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++		enable-active-high;
++	};
++
+ 	reg_vbat_wifi: vbat-wifi {
+ 		compatible = "regulator-fixed";
+ 		regulator-min-microvolt = <3300000>;
+@@ -92,6 +129,16 @@ reg_vbat_wifi: vbat-wifi {
+ 		regulator-name = "vbat-wifi";
+ 	};
+ 
++	/* This is a charge pump for CC1 and CC2 pins on USB-C connector. */
++	reg_vconn5v0: vconn5v0 {
++		compatible = "regulator-fixed";
++		regulator-name = "vconn5v0";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 9 GPIO_ACTIVE_HIGH>; /* PD9 */
++		enable-active-high;
++	};
++
+ 	sgm3140: led-controller {
+ 		compatible = "sgmicro,sgm3140";
+ 		vin-supply = <&reg_dcdc1>;
+@@ -207,6 +254,21 @@ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	hvcc-supply = <&reg_dldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&sound_hdmi {
++	status = "okay";
++};
++
+ &i2c_csi {
+ 	gc2145: front-camera@3c {
+ 		compatible = "galaxycore,gc2145";
+@@ -309,6 +371,10 @@ &i2c2 {
+ 	status = "okay";
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &lradc {
+ 	vref-supply = <&reg_aldo3>;
+ 	wakeup-source;
+@@ -602,7 +668,7 @@ &uart3 {
+ };
+ 
+ &usb_otg {
+-	dr_mode = "peripheral";
++	dr_mode = "otg";
+ 	status = "okay";
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
new file mode 100644
index 000000000000..ce2207191185
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
@@ -0,0 +1,187 @@
+From 97f428b1c0c70f452d17411a65811aadf7b8deb6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 28 Sep 2020 04:35:13 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add detailed OCV to capactiy
+ conversion table
+
+This ensures that discharging stops at 3V, and that charging current
+limits are enforced. It also allows for more precise capacity reporting
+(on my device at the very least, at room temperature).
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 151 ++++++++++++++++++
+ 1 file changed, 151 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index d126c9e9a605..5437fc514e7b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -28,6 +28,156 @@ backlight: backlight {
+ 		/* Backlight configuration differs per PinePhone revision. */
+ 	};
+ 
++        bat: battery {
++                compatible = "simple-battery";
++                voltage-min-design-microvolt = <3000000>;
++                voltage-max-design-microvolt = <4350000>;
++                energy-full-design-microwatt-hours = <12000000>;
++                charge-full-design-microamp-hours = <2750000>;
++                precharge-current-microamp = <130000>;
++                charge-term-current-microamp = <50000>;
++                constant-charge-current-max-microamp = <1300000>;
++                constant-charge-voltage-max-microvolt = <4350000>;
++                factory-internal-resistance-micro-ohms = <150000>;
++                resistance-temp-table = <20 150>;
++                ocv-capacity-celsius = <20>;
++                ocv-capacity-table-0 =
++                	<4334000 100>,
++			<4319700 99>,
++			<4304300 98>,
++			<4292200 97>,
++			<4280100 96>,
++			<4269100 95>,
++			<4253700 94>,
++			<4242700 93>,
++			<4232800 92>,
++			<4222900 91>,
++			<4211900 90>,
++			<4203100 89>,
++			<4192100 88>,
++			<4177800 87>,
++			<4167900 86>,
++			<4155800 85>,
++			<4147000 84>,
++			<4136000 83>,
++			<4126100 82>,
++			<4111800 81>,
++			<4102999 80>,
++			<4093100 79>,
++			<4084300 78>,
++			<4075500 77>,
++			<4064500 76>,
++			<4054600 75>,
++			<4042500 74>,
++			<4035900 73>,
++			<4029300 72>,
++			<4018300 71>,
++			<4006200 70>,
++			<3993000 69>,
++			<3974300 68>,
++			<3964400 67>,
++			<3956700 66>,
++			<3949000 65>,
++			<3943500 64>,
++			<3938000 63>,
++			<3931400 62>,
++			<3923700 61>,
++			<3917100 60>,
++			<3903900 59>,
++			<3895100 58>,
++			<3887400 57>,
++			<3878600 56>,
++			<3870900 55>,
++			<3863200 54>,
++			<3855500 53>,
++			<3848900 52>,
++			<3837900 51>,
++			<3830200 50>,
++			<3825800 49>,
++			<3821400 48>,
++			<3815900 47>,
++			<3810400 46>,
++			<3806000 45>,
++			<3801600 44>,
++			<3797200 43>,
++			<3792800 42>,
++			<3789500 41>,
++			<3786200 40>,
++			<3781800 39>,
++			<3778500 38>,
++			<3775200 37>,
++			<3770800 36>,
++			<3764200 35>,
++			<3760900 34>,
++			<3758700 33>,
++			<3755400 32>,
++			<3754300 31>,
++			<3752100 30>,
++			<3748800 29>,
++			<3749900 28>,
++			<3745500 27>,
++			<3742200 26>,
++			<3741100 25>,
++			<3737800 24>,
++			<3734500 23>,
++			<3731200 22>,
++			<3730100 21>,
++			<3724600 20>,
++			<3722400 19>,
++			<3718000 18>,
++			<3713600 17>,
++			<3708100 16>,
++			<3701500 15>,
++			<3689400 14>,
++			<3682800 13>,
++			<3674000 12>,
++			<3666300 11>,
++			<3659700 10>,
++			<3653100 9>,
++			<3647600 8>,
++			<3641000 7>,
++			<3625600 6>,
++			<3613500 5>,
++			<3591500 4>,
++			<3554100 3>,
++			<3489200 2>,
++			<3393500 1>,
++			<3256000 0>;
++                x-powers,ocv-capacity-table =
++                	<0xc0 0>,
++			<0xc1 1>,
++			<0xc2 1>,
++			<0xc3 2>,
++			<0xc4 2>,
++			<0xc5 4>,
++			<0xc6 4>,
++			<0xc7 5>,
++			<0xc8 6>,
++			<0xc9 8>,
++			<0xca 11>,
++			<0xcb 15>,
++			<0xcc 22>,
++			<0xcd 36>,
++			<0xce 44>,
++			<0xcf 48>,
++			<0xd0 51>,
++			<0xd1 53>,
++			<0xd2 56>,
++			<0xd3 60>,
++			<0xd4 64>,
++			<0xd5 69>,
++			<0xd6 71>,
++			<0xd7 75>,
++			<0xd8 78>,
++			<0xd9 82>,
++			<0xda 84>,
++			<0xdb 85>,
++			<0xdc 88>,
++			<0xdd 92>,
++			<0xde 95>,
++			<0xdf 98>;
++        };
++
+ 	bt_sco_codec: bt-sco-codec {
+ 		#sound-dai-cells = <1>;
+ 		compatible = "linux,bt-sco";
+@@ -478,6 +628,7 @@ axp803: pmic@3a3 {
+ 
+ &battery_power_supply {
+ 	status = "okay";
++	monitored-battery = <&bat>;
+ };
+ 
+ &reg_aldo1 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
new file mode 100644
index 000000000000..bfd812d0d74c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
@@ -0,0 +1,130 @@
+From 9b184c1cb175091c3ca98eab0c0bbcd6b0197000 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Apr 2020 14:13:08 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add front/back cameras
+
+Pinephone has OV5640 back camera and GC2145 front camera. Add support
+for both.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 89 +++++++++++++++++++
+ 1 file changed, 89 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 6eab61a12cd8..44b18d5a9d93 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -36,6 +36,15 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	i2c_csi: i2c-csi {
++		compatible = "i2c-gpio";
++		sda-gpios = <&pio 4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PE13 */
++		scl-gpios = <&pio 4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PE12 */
++		i2c-gpio,delay-us = <3>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -134,6 +143,36 @@ &cpu3 {
+ 	cpu-supply = <&reg_dcdc2>;
+ };
+ 
++&csi {
++	pinctrl-0 = <&csi_pins>, <&csi_mclk_pin>;
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi_ov5640_ep: endpoint@0 {
++			reg = <0>;
++			remote-endpoint = <&ov5640_ep>;
++			bus-width = <8>;
++			hsync-active = <1>; /* Active high */
++			vsync-active = <0>; /* Active low */
++			data-active = <1>;  /* Active high */
++			pclk-sample = <1>;  /* Rising */
++		};
++
++		csi_gc2145_ep: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&gc2145_ep>;
++			bus-width = <8>;
++			hsync-active = <1>;
++			vsync-active = <1>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		};
++	};
++};
++
+ &dai {
+ 	status = "okay";
+ };
+@@ -168,6 +207,56 @@ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&i2c_csi {
++	gc2145: front-camera@3c {
++		compatible = "galaxycore,gc2145";
++		reg = <0x3c>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++
++		AVDD-supply = <&reg_dldo3>;
++		DVDD-supply = <&reg_aldo1>;
++		IOVDD-supply = <&reg_eldo3>;
++		reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
++		enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
++
++		port {
++			gc2145_ep: endpoint {
++				remote-endpoint = <&csi_gc2145_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++
++	ov5640: rear-camera@4c {
++		compatible = "ovti,ov5640";
++		reg = <0x4c>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++
++		AVDD-supply = <&reg_dldo3>;
++		DOVDD-supply = <&reg_aldo1>; /* shared with AFVCC */
++		DVDD-supply = <&reg_eldo3>;
++		reset-gpios = <&pio 3 3 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PD3 */
++		powerdown-gpios = <&pio 2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PC0 */
++
++		port {
++			ov5640_ep: endpoint {
++				remote-endpoint = <&csi_ov5640_ep>;
++				bus-width = <8>;
++				hsync-active = <1>; /* Active high */
++				vsync-active = <0>; /* Active low */
++				data-active = <1>;  /* Active high */
++				pclk-sample = <1>;  /* Rising */
++			};
++		};
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
new file mode 100644
index 000000000000..a5c30fe0c40c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
@@ -0,0 +1,26 @@
+From 0f21b453ed4f5ba99fd1a6f12a59c22b5cf421bd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 17 Jan 2021 23:06:03 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add interrupt pin for WiFi
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 10efafb282cd..1b2de298990f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -581,6 +581,8 @@ &mmc1 {
+ 
+ 	rtl8723cs: wifi@1 {
+ 		reg = <1>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 3 IRQ_TYPE_EDGE_FALLING>; /* PL3 */
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
new file mode 100644
index 000000000000..cbaa0a339939
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
@@ -0,0 +1,119 @@
+From bf464bb1a8483da75b42cecb1ed224280d00ebd4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Jul 2020 01:00:48 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add modem power manager
+
+Pinephone has a EG25-G modem that needs a special powerup/powerdown
+sequence. Add a power manager to manage the modem power.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../allwinner/sun50i-a64-pinephone-1.0.dts    | 22 ++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.1.dts    | 23 +++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.2.dts    | 23 +++++++++++++++++++
+ 3 files changed, 68 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index 498ae493d176..ff01e2be26e7 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -86,6 +86,28 @@ &reg_drivevbus {
+ 	status = "okay";
+ };
+ 
++&uart3 {
++	modem {
++		compatible = "quectel,eg25";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vbat_bb>; /* PL7 */
++
++		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
++		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
++		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++
++		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
++
++		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
++		dtr-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-DTR */
++		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
++
++		quectel,qdai = "1,1,0,1,0,0,1,1";
++	};
++};
++
+ &usbphy {
+ 	usb-role-switch;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 73275308f484..93dc8512fe45 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -114,6 +114,29 @@ &sgm3140 {
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
+ 
++&uart3 {
++	modem {
++		compatible = "quectel,eg25";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vbat_bb>; /* PL7 */
++
++		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
++		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
++		status-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++		status-pwrkey-multiplexed; /* status acts as pwrkey */
++
++		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
++
++		dtr-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-DTR */
++		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
++		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
++
++		quectel,qdai = "1,1,0,1,0,0,1,1";
++	};
++};
++
+ &usbphy {
+ 	usb-role-switch;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index 40127186606f..5e988230e6e4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -103,6 +103,29 @@ &sgm3140 {
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
+ 
++&uart3 {
++	modem {
++		compatible = "quectel,eg25";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vbat_bb>; /* PL7 */
++
++		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
++		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
++		status-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
++		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++
++		host-ready-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-RI */
++
++		dtr-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-DTR */
++		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
++		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
++
++		quectel,qdai = "1,1,0,1,0,0,1,1";
++	};
++};
++
+ &usbphy {
+ 	usb-role-switch;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-PinePhone-m.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-PinePhone-m.patch
new file mode 100644
index 000000000000..7c8234e4c903
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-PinePhone-m.patch
@@ -0,0 +1,41 @@
+From ec96537bbf218e3cc0bd8a54c000b08f614df633 Mon Sep 17 00:00:00 2001
+From: Shoji Keita <awaittrot@shjk.jp>
+Date: Wed, 14 Jul 2021 07:17:18 +0900
+Subject: arm64: dts: sun50i-a64-pinephone: Add mount-matrix for PinePhone
+ magnetometers.
+
+For lis3mdl, values are based on datasheet and PCB drawing.
+For af8133j, values are from testing on a real device.
+
+Signed-off-by: Shoji Keita <awaittrot@shjk.jp>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 694d715ff875..80a08fa0a52a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -506,6 +506,9 @@ af8133j: magnetometer@1c {
+ 		reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>;
+ 		avdd-supply = <&reg_dldo1>;
+ 		dvdd-supply = <&reg_dldo1>;
++		mount-matrix = "0", "-1", "0",
++				"-1", "0", "0",
++				"0", "0", "-1";
+ 	};
+ 
+ 	/* Magnetometer */
+@@ -514,6 +517,9 @@ lis3mdl: magnetometer@1e {
+ 		reg = <0x1e>;
+ 		vdd-supply = <&reg_dldo1>;
+ 		vddio-supply = <&reg_dldo1>;
++		mount-matrix = "0", "1", "0",
++				"-1", "0", "0",
++				"0", "0", "1";
+ 	};
+ 
+ 	/* Light/proximity sensor */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-acceleromet.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-acceleromet.patch
new file mode 100644
index 000000000000..34bf2baa64d7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-acceleromet.patch
@@ -0,0 +1,29 @@
+From 9aebb9e5c35bb7c689ecd8d81be73294092bab03 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 8 Sep 2020 15:31:26 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add mount matrix for accelerometer
+
+Port from pine64 kernel.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index e1e64065ef7a..807e77643bc9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -513,6 +513,9 @@ accelerometer@68 {
+ 		interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */
+ 		vdd-supply = <&reg_dldo1>;
+ 		vddio-supply = <&reg_dldo1>;
++		mount-matrix = "0", "1", "0",
++				"-1", "0", "0",
++				"0", "0", "-1";
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
new file mode 100644
index 000000000000..5a1fc2a9eca2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
@@ -0,0 +1,27 @@
+From 241938c1e0510d3c3401c1eec2e6c23805bc2b57 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 20 May 2023 16:58:11 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add power supply to stk3311
+
+This makes the driver disable the supply during sleep.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 657373db86bb..136de65e48b9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -641,6 +641,7 @@ light-sensor@48 {
+ 		reg = <0x48>;
+ 		interrupt-parent = <&pio>;
+ 		interrupts = <1 0 IRQ_TYPE_EDGE_FALLING>; /* PB0 */
++		vdd-supply = <&reg_ldo_io0>;
+ 	};
+ 
+ 	/* Accelerometer/gyroscope */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
new file mode 100644
index 000000000000..4603cae8dd58
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
@@ -0,0 +1,80 @@
+From 9ddf2d5ed4f775346afd951f8d71bf50d8e35d11 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 15 Feb 2021 17:45:13 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add reboot mode driver
+
+With the latest p-boot (released 2021-02-15), you can reboot to
+a particular boot option or to the menu, to FEL, to eMMC bootloader,
+regardless of the user defined p-boot defaults.
+
+Call reboot with cmd of LINUX_REBOOT_CMD_RESTART2 and arg:
+
+- fel          Reboot to FEL
+- emmc-egon    Reboot with chainload of bootloader from eMMC
+- sd1-8        Reboot to SD bootfs option
+- emmc1-8      Reboot to eMMC bootfs option
+- menu         Reboot to p-boot menu
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 37 +++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 136de65e48b9..f0aab1fd6080 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -423,6 +423,34 @@ sgm3140_flash: led {
+ 		};
+ 	};
+ 
++	/* PinePhone specific reboot modes for p-boot. */
++	reboot-mode {
++		compatible = "nvmem-reboot-mode";
++		nvmem-cells = <&reboot_mode>;
++		nvmem-cell-names = "reboot-mode";
++
++		mode-normal     = <0x0>;
++		mode-fel        = <0xb0010fe1>;
++		mode-emmc-egon  = <0xb001e33c>;
++		mode-sd1        = <0xb0010020>;
++		mode-sd2        = <0xb0010021>;
++		mode-sd3        = <0xb0010022>;
++		mode-sd4        = <0xb0010023>;
++		mode-sd5        = <0xb0010024>;
++		mode-sd6        = <0xb0010025>;
++		mode-sd7        = <0xb0010026>;
++		mode-sd8        = <0xb0010027>;
++		mode-emmc1      = <0xb0010000>;
++		mode-emmc2      = <0xb0010001>;
++		mode-emmc3      = <0xb0010002>;
++		mode-emmc4      = <0xb0010003>;
++		mode-emmc5      = <0xb0010004>;
++		mode-emmc6      = <0xb0010005>;
++		mode-emmc7      = <0xb0010006>;
++		mode-emmc8      = <0xb0010007>;
++		mode-menu       = <0xb00100ff>;
++	};
++
+ 	speaker_amp: audio-amplifier {
+ 		compatible = "simple-audio-amplifier";
+ 		enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
+@@ -916,6 +944,15 @@ &reg_rtc_ldo {
+ 	regulator-name = "vcc-rtc";
+ };
+ 
++&rtc {
++	#address-cells = <1>;
++	#size-cells = <1>;
++
++	reboot_mode: reboot-mode@4 {
++		reg = <0x4 0x4>;
++	};
++};
++
+ &sound {
+ 	status = "okay";
+ 	simple-audio-card,name = "PinePhone";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
new file mode 100644
index 000000000000..435e7c2a6733
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
@@ -0,0 +1,54 @@
+From e4083a77a507bc0af30ab685e965c0ac04750fb2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 18 Oct 2021 17:41:25 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add supply for i2c bus to anx7688
+
+The bus power needs to be enabled for anx7688 to be able to communicate
+with the master.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 1 +
+ 3 files changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index 8f6ea6b06aa9..cfb9518e057f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -43,6 +43,7 @@ hdmi-bridge@28 {
+ 		avdd18-supply = <&reg_ldo_io1>;
+ 		dvdd18-supply = <&reg_ldo_io1>;
+ 		avdd33-supply = <&reg_dldo1>;
++		i2c-supply = <&reg_ldo_io0>;
+ 		vconn-supply = <&reg_vconn5v0>;
+ 		hdmi_vt-supply = <&reg_dldo1>;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 63ceae07a0e0..35cb92e3b5f1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -52,6 +52,7 @@ hdmi-bridge@28 {
+ 		avdd18-supply = <&reg_ldo_io1>;
+ 		dvdd18-supply = <&reg_ldo_io1>;
+ 		avdd33-supply = <&reg_dldo1>;
++		i2c-supply = <&reg_ldo_io0>;
+ 		vconn-supply = <&reg_vconn5v0>;
+ 		hdmi_vt-supply = <&reg_dldo1>;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index d28a23e98232..aeb5c69fe51d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -51,6 +51,7 @@ hdmi-bridge@28 {
+ 		avdd18-supply = <&reg_ldo_io1>;
+ 		dvdd18-supply = <&reg_ldo_io1>;
+ 		avdd33-supply = <&reg_dcdc1>;
++		i2c-supply = <&reg_ldo_io0>;
+ 		vconn-supply = <&reg_vconn5v0>;
+ 		hdmi_vt-supply = <&reg_dldo1>;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
new file mode 100644
index 000000000000..81f1307d7ff9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
@@ -0,0 +1,33 @@
+From 838e5c27ee459200b19853507ac12b44e555c9be Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 6 Feb 2020 23:49:27 -0600
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for Bluetooth audio
+
+The PinePhone has a Bluetooth chip with its PCM interface connected to
+AIF3. Add the DAI link so headeset audio can be routed in hardware.
+
+Even though the link is mono, configuring the link for 2 slots is
+required for compatibility with AIF2, which uses a single 32-bit slot,
+and which shares its clock dividers with AIF3. Using equal clock
+frequencies allows the modem and headset to be used at the same time.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 807e77643bc9..85fe10220017 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -181,6 +181,7 @@ bat: battery {
+ 	bt_sco_codec: bt-sco-codec {
+ 		#sound-dai-cells = <1>;
+ 		compatible = "linux,bt-sco";
++		sound-name-prefix = "Bluetooth";
+ 	};
+ 
+ 	chosen {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
new file mode 100644
index 000000000000..5963e86fa92a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
@@ -0,0 +1,88 @@
+From 4e5d2c26452e68de3ff49d87e141250dbd7571b7 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 10 Nov 2022 20:11:10 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for Pinephone 1.2 beta
+
+Beta versions uses a different magnetometer chip.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |  1 +
+ .../allwinner/sun50i-a64-pinephone-1.2b.dts   | 29 +++++++++++++++++++
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 12 --------
+ 3 files changed, 30 insertions(+), 12 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 0db7b60b49a1..0a0ec8a39259 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2b.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-early-adopter.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts
+new file mode 100644
+index 000000000000..bb6e075972d1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
++
++/dts-v1/;
++
++#include "sun50i-a64-pinephone-1.2.dts"
++
++/ {
++	model = "Pine64 PinePhone (1.2b)";
++	compatible = "pine64,pinephone-1.2b", "pine64,pinephone", "allwinner,sun50i-a64";
++};
++
++&lis3mdl {
++	status = "disabled";
++};
++
++&i2c1 {
++	/* Alternative magnetometer */
++	af8133j: magnetometer@1c {
++		compatible = "voltafield,af8133j";
++		reg = <0x1c>;
++		reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>;
++		avdd-supply = <&reg_dldo1>;
++		dvdd-supply = <&reg_dldo1>;
++		mount-matrix = "0", "-1", "0",
++				"-1", "0", "0",
++				"0", "0", "-1";
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 9585d2ad91f4..657373db86bb 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -624,18 +624,6 @@ &i2c1 {
+ 	status = "okay";
+ 	clock-frequency = <400000>;
+ 
+-	/* Alternative magnetometer */
+-	af8133j: magnetometer@1c {
+-		compatible = "voltafield,af8133j";
+-		reg = <0x1c>;
+-		reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>;
+-		avdd-supply = <&reg_dldo1>;
+-		dvdd-supply = <&reg_dldo1>;
+-		mount-matrix = "0", "-1", "0",
+-				"-1", "0", "0",
+-				"0", "0", "-1";
+-	};
+-
+ 	/* Magnetometer */
+ 	lis3mdl: magnetometer@1e {
+ 		compatible = "st,lis3mdl-magn";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
new file mode 100644
index 000000000000..5aadf2768f5c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
@@ -0,0 +1,170 @@
+From fabf5bcc1d8aa545b6197f1c4c4dd336e815542a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 21 Jan 2022 23:28:48 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for Pinephone keyboard
+
+Pinephone keyboard can be used with Pinephone. Describe it in
+the device tree.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 136 ++++++++++++++++++
+ 1 file changed, 136 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 80a08fa0a52a..6ba56e41d6aa 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -178,6 +178,122 @@ bat: battery {
+ 			<0xdf 98>;
+         };
+ 
++        ppkb_battery: keyboard-battery {
++                compatible = "simple-battery";
++                voltage-min-design-microvolt = <3000000>;
++                voltage-max-design-microvolt = <4200000>;
++                energy-full-design-microwatt-hours = <21000000>;
++                charge-full-design-microamp-hours = <6000000>;
++                precharge-current-microamp = <100000>;
++                charge-term-current-microamp = <50000>;
++                constant-charge-current-max-microamp = <2000000>;
++                constant-charge-voltage-max-microvolt = <4200000>;
++                factory-internal-resistance-micro-ohms = <120000>;
++                ocv-capacity-celsius = <20>;
++                ocv-capacity-table-0 =
++                	<4147328 100>,
++			<4132636 99>,
++			<4121720 98>,
++			<4110905 97>,
++			<4102063 96>,
++			<4092428 95>,
++			<4082371 94>,
++			<4074137 93>,
++			<4064172 92>,
++			<4056387 91>,
++			<4047198 90>,
++			<4038599 89>,
++			<4030933 88>,
++			<4021831 87>,
++			<4012613 86>,
++			<4003863 85>,
++			<3995132 84>,
++			<3986108 83>,
++			<3977434 82>,
++			<3967977 81>,
++			<3960286 80>,
++			<3951737 79>,
++			<3943518 78>,
++			<3935723 77>,
++			<3928692 76>,
++			<3920093 75>,
++			<3912676 74>,
++			<3905481 73>,
++			<3899881 72>,
++			<3892341 71>,
++			<3887140 70>,
++			<3880005 69>,
++			<3876060 68>,
++			<3869195 67>,
++			<3863234 66>,
++			<3857808 65>,
++			<3851464 64>,
++			<3846976 63>,
++			<3840724 62>,
++			<3835254 61>,
++			<3830946 60>,
++			<3826564 59>,
++			<3821275 58>,
++			<3817413 57>,
++			<3811941 56>,
++			<3808947 55>,
++			<3804959 54>,
++			<3800958 53>,
++			<3797447 52>,
++			<3794303 51>,
++			<3790341 50>,
++			<3787022 49>,
++			<3783436 48>,
++			<3779936 47>,
++			<3776176 46>,
++			<3772160 45>,
++			<3769348 44>,
++			<3766705 43>,
++			<3762481 42>,
++			<3760894 41>,
++			<3758396 40>,
++			<3755803 39>,
++			<3753543 38>,
++			<3749691 37>,
++			<3747026 36>,
++			<3743937 35>,
++			<3741872 34>,
++			<3738529 33>,
++			<3737528 32>,
++			<3734059 31>,
++			<3731586 30>,
++			<3728576 29>,
++			<3725939 28>,
++			<3721208 27>,
++			<3718239 26>,
++			<3713032 25>,
++			<3709785 24>,
++			<3704045 23>,
++			<3701203 22>,
++			<3695965 21>,
++			<3691074 20>,
++			<3684562 19>,
++			<3679140 18>,
++			<3670993 17>,
++			<3664243 16>,
++			<3655383 15>,
++			<3647666 14>,
++			<3642747 13>,
++			<3637775 12>,
++			<3632593 11>,
++			<3627120 10>,
++			<3620923 9>,
++			<3611465 8>,
++			<3597536 7>,
++			<3577366 6>,
++			<3545253 5>,
++			<3497377 4>,
++			<3430377 3>,
++			<3337780 2>,
++			<3183953 1>,
++			<3064061 0>;
++        };
++
+ 	bt_sco_codec: bt-sco-codec {
+ 		#sound-dai-cells = <1>;
+ 		compatible = "linux,bt-sco";
+@@ -547,6 +663,26 @@ accelerometer@68 {
+ /* Connected to pogo pins (external spring based pinheader for user addons) */
+ &i2c2 {
+ 	status = "okay";
++
++	ppkb: keyboard@15 {
++		compatible = "pine64,pinephone-keyboard";
++		reg = <0x15>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 12 IRQ_TYPE_EDGE_FALLING>; /* PL12 */
++		vbat-supply = <&reg_usb_5v>;
++		wakeup-source;
++
++		i2c {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			charger@75 {
++				compatible = "injoinic,ip5209";
++				reg = <0x75>;
++				monitored-battery = <&ppkb_battery>;
++			};
++		};
++	};
+ };
+ 
+ &i2s2 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
new file mode 100644
index 000000000000..dc79713f1c14
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
@@ -0,0 +1,71 @@
+From 1a1550a14f8737d38506a1f1de23cdb0c1966057 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 5 Feb 2020 23:14:27 -0600
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for modem audio
+
+The PinePhone has a Quectel EG25-G modem (a variant of the EC25) with
+its PCM interface connected to AIF2. Add the DAI link so call audio can
+be routed in hardware.
+
+The modem supports two fixed sample rates, and one fixed word size, with
+a variable BCLK frequency. Use the minimum supported BCLK frequency,
+which corresponds to a slot width of 32 bits.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 25 ++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 85fe10220017..0bd1dfd59441 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -188,6 +188,12 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	ec25_codec: ec25-codec {
++		#sound-dai-cells = <1>;
++		compatible = "quectel,ec25";
++		sound-name-prefix = "Modem";
++	};
++
+ 	i2c_csi: i2c-csi {
+ 		compatible = "i2c-gpio";
+ 		sda-gpios = <&pio 4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PE13 */
+@@ -316,7 +322,7 @@ vibrator {
+ 
+ &codec {
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&aif3_pins>;
++	pinctrl-0 = <&aif2_pins>, <&aif3_pins>;
+ 	status = "okay";
+ };
+ 
+@@ -781,6 +787,23 @@ &sound {
+ 			"Headset Microphone", "HBIAS",
+ 			"MIC2", "Headset Microphone";
+ 
++	simple-audio-card,dai-link@1 {
++		format = "dsp_a";
++		frame-master = <&link1_codec>;
++		bitclock-master = <&link1_codec>;
++		bitclock-inversion;
++
++		link1_cpu: cpu {
++			sound-dai = <&ec25_codec 0>;
++		};
++
++		link1_codec: codec {
++			sound-dai = <&codec 1>;
++			dai-tdm-slot-num = <1>;
++			dai-tdm-slot-width = <32>;
++		};
++	};
++
+ 	simple-audio-card,dai-link@2 {
+ 		format = "dsp_a";
+ 		frame-master = <&link2_codec>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
new file mode 100644
index 000000000000..c809e7618d24
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
@@ -0,0 +1,35 @@
+From 555ad50d00d81d4087a7dcbafb70256d9db31ee7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 30 Nov 2020 06:14:07 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Bump I2C frequency to 400kHz
+
+High speed. :)
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 0bd1dfd59441..10efafb282cd 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -478,6 +478,7 @@ ov5640_ep: endpoint {
+ 
+ &i2c0 {
+ 	status = "okay";
++	clock-frequency = <400000>;
+ 
+ 	touchscreen@5d {
+ 		compatible = "goodix,gt917s";
+@@ -495,6 +496,7 @@ touchscreen@5d {
+ 
+ &i2c1 {
+ 	status = "okay";
++	clock-frequency = <400000>;
+ 
+ 	/* Magnetometer */
+ 	lis3mdl: magnetometer@1e {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
new file mode 100644
index 000000000000..d0eb7c88f9d7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
@@ -0,0 +1,29 @@
+From 5252a2ad8332d095d4301883779f049ebc530ebf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 26 Apr 2021 01:31:27 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Don't make lradc keys a wakeup
+ source
+
+This allow the crust to reach lower suspend state.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index b64b3b65997a..0a8352147280 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -540,7 +540,7 @@ &i2s2 {
+ 
+ &lradc {
+ 	vref-supply = <&reg_aldo3>;
+-	wakeup-source;
++//	wakeup-source;
+ 	status = "okay";
+ 
+ 	button-200 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
new file mode 100644
index 000000000000..e12c9fd4bdfc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
@@ -0,0 +1,34 @@
+From 68bfd8bf3cd75eff0314084ca537ce776557ab90 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 16 Apr 2022 02:12:06 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Enable Pinephone Keyboard power
+ manager
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 6ba56e41d6aa..9585d2ad91f4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -434,6 +434,15 @@ vibrator {
+ 		enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
+ 		vcc-supply = <&reg_dcdc1>;
+ 	};
++
++	keyboard-power {
++		compatible = "megi,pinephone-keyboard-power-manager";
++		phone-battery = "axp20x-battery";
++		phone-usb = "axp20x-usb";
++		kb-battery = "ip5xxx-battery";
++		kb-boost = "ip5xxx-boost";
++		kb-usb = "ip5xxx-usb";
++	};
+ };
+ 
+ &codec {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
new file mode 100644
index 000000000000..c4f3c2afed68
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
@@ -0,0 +1,29 @@
+From aeba874f4e798b7633c95c2929efd1b6e17d85a6 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 23 Sep 2020 00:13:54 -0500
+Subject: arm64: dts: sun50i-a64-pinephone: Enable internal HMIC bias
+
+Revisions 1.0 and 1.1 of the PinePhone mainboard do not have an external
+resistor connecting HBIAS to MIC2. Enable the internal resistor to
+provide the appropriate mic bias.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index ff01e2be26e7..8f6ea6b06aa9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -126,3 +126,7 @@ &sgm3140 {
+ 	enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ 	flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ };
++
++&codec_analog {
++	allwinner,internal-bias-resistor;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
new file mode 100644
index 000000000000..2c0cf1eb5c2b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
@@ -0,0 +1,29 @@
+From e316e38cce272c7a1558cc11044a899b79b14a6c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 5 Aug 2020 11:19:01 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Fix BH modem manager behavior
+
+PP 1.1 has STATUS line multiplexed with POWER KEY, but reading it doesn't
+work reliably. Just treat 1.1 as if it was 1.0, and ignore the STATUS.
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 93dc8512fe45..d67f31ef529e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -123,8 +123,8 @@ modem {
+ 
+ 		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
+ 		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+-		status-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+-		status-pwrkey-multiplexed; /* status acts as pwrkey */
++		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++		//status-pwrkey-multiplexed; /* status acts as pwrkey */
+ 
+ 		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ 		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
new file mode 100644
index 000000000000..5b6a4c5c5da1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
@@ -0,0 +1,28 @@
+From 997f1396bd58977987f378c22c7824cc4e8e9ae4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 25 Apr 2021 03:17:39 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Power off the touch controller in
+ sleep
+
+Otherwise it stays on and consumes quite a bit of power.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 1b2de298990f..b64b3b65997a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -491,6 +491,7 @@ touchscreen@5d {
+ 		VDDIO-supply = <&reg_ldo_io0>;
+ 		touchscreen-size-x = <720>;
+ 		touchscreen-size-y = <1440>;
++		poweroff-in-suspend;
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
new file mode 100644
index 000000000000..c08edf299488
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
@@ -0,0 +1,73 @@
+From 4c960e6f87a03d4177caadf1dc2a4fb0c1f31ef8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 7 Jun 2021 20:23:52 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Set minimum backlight duty cycle to
+ 10%
+
+Instead of creating our own table, use existing lth_brightness
+functionality in the pwm_bl driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone-1.1.dts  | 16 +---------------
+ .../dts/allwinner/sun50i-a64-pinephone-1.2.dts  | 17 +----------------
+ 2 files changed, 2 insertions(+), 31 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index d67f31ef529e..63ceae07a0e0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -26,21 +26,7 @@ &axp803 {
+ 
+ &backlight {
+ 	power-supply = <&reg_ldo_io0>;
+-	/*
+-	 * PWM backlight circuit on this PinePhone revision was changed since
+-	 * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight
+-	 * being off is around 20%. Duty cycle for the lowest brightness level
+-	 * also varries quite a bit between individual boards, so the lowest
+-	 * value here was chosen as a safe default.
+-	 */
+-	brightness-levels = <
+-		774  793  814  842
+-		882  935  1003 1088
+-		1192 1316 1462 1633
+-		1830 2054 2309 2596
+-		2916 3271 3664 4096>;
+-	num-interpolated-steps = <50>;
+-	default-brightness-level = <400>;
++	lth-brightness = <10>;
+ };
+ 
+ &codec_analog {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index 5e988230e6e4..d28a23e98232 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -17,22 +17,7 @@ wifi_pwrseq: wifi-pwrseq {
+ 
+ &backlight {
+ 	power-supply = <&reg_ldo_io0>;
+-	/*
+-	 * PWM backlight circuit on this PinePhone revision was changed since 1.0,
+-	 * and the lowest PWM duty cycle that doesn't lead to backlight being off
+-	 * is around 10%. Duty cycle for the lowest brightness level also varries
+-	 * quite a bit between individual boards, so the lowest value here was
+-	 * chosen as a safe default.
+-	 */
+-	brightness-levels = <
+-		5000 5248 5506 5858 6345
+-		6987 7805 8823 10062 11543
+-		13287 15317 17654 20319 23336
+-		26724 30505 34702 39335 44427
+-		50000
+-	>;
+-	num-interpolated-steps = <50>;
+-	default-brightness-level = <500>;
++	lth-brightness = <10>;
+ };
+ 
+ &lis3mdl {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
new file mode 100644
index 000000000000..ef9411451809
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
@@ -0,0 +1,43 @@
+From 373d2d6b62d0e4e6b1542580a33dda30311eca37 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 6 Feb 2020 04:58:32 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Shorten post-power-on-delay on mmcs
+
+These are not needed.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 5437fc514e7b..e1e64065ef7a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -553,6 +553,7 @@ &mmc0 {
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ 	disable-wp;
+ 	bus-width = <4>;
++	post-power-on-delay-ms = <1>; /* power is already turned on by the bootloader */
+ 	status = "okay";
+ };
+ 
+@@ -563,6 +564,7 @@ &mmc1 {
+ 	vqmmc-supply = <&reg_dldo4>;
+ 	bus-width = <4>;
+ 	non-removable;
++	post-power-on-delay-ms = <1>; /* wifi power is always on */
+ 	status = "okay";
+ 
+ 	rtl8723cs: wifi@1 {
+@@ -578,6 +580,7 @@ &mmc2 {
+ 	bus-width = <8>;
+ 	non-removable;
+ 	cap-mmc-hw-reset;
++	post-power-on-delay-ms = <1>; /* power is already turned on by the bootloader */
+ 	status = "okay";
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
new file mode 100644
index 000000000000..9be72c59d72b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
@@ -0,0 +1,35 @@
+From 11fbc69bcfe0c494a741eed9e4863b210752885c Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 23 Feb 2024 01:53:14 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Use newer jack detection
+ implementaion
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index f0aab1fd6080..9cdef78a4abd 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -476,6 +476,7 @@ keyboard-power {
+ &codec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&aif2_pins>, <&aif3_pins>;
++	jack-type = "headset";
+ 	status = "okay";
+ };
+ 
+@@ -956,7 +957,7 @@ reboot_mode: reboot-mode@4 {
+ &sound {
+ 	status = "okay";
+ 	simple-audio-card,name = "PinePhone";
+-	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
++	simple-audio-card,aux-devs = <&codec_analog>, <&codec>, <&speaker_amp>;
+ 	simple-audio-card,widgets = "Microphone", "Headset Microphone",
+ 				    "Microphone", "Internal Microphone",
+ 				    "Headphone", "Headphone Jack",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
new file mode 100644
index 000000000000..25e03ca6b29b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
@@ -0,0 +1,84 @@
+From b61173a496bd1b9fba570ca8d76605e52733ecc7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 26 Oct 2021 01:25:46 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Workaround broken HDMI HPD signal
+
+HDMI HPD signal from ANX7688 to SoC's HDMI PHY is wrongly level
+shifted and does not register most of the time at the SoC's input.
+
+We need to do the signalling in software. Link anx7688 to hdmi
+driver via extcon interface.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 6 +++++-
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 6 +++++-
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 6 +++++-
+ 3 files changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index cfb9518e057f..0530881d8401 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -25,7 +25,7 @@ &axp803 {
+ };
+ 
+ &i2c0 {
+-	hdmi-bridge@28 {
++	anx7688: hdmi-bridge@28 {
+ 		compatible = "analogix,anx7688";
+ 		reg = <0x28>;
+ 
+@@ -131,3 +131,7 @@ &sgm3140 {
+ &codec_analog {
+ 	allwinner,internal-bias-resistor;
+ };
++
++&hdmi {
++	extcon = <&anx7688 0>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 35cb92e3b5f1..053e4add9973 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -34,7 +34,7 @@ &codec_analog {
+ };
+ 
+ &i2c0 {
+-	hdmi-bridge@28 {
++	anx7688: hdmi-bridge@28 {
+ 		compatible = "analogix,anx7688";
+ 		reg = <0x28>;
+ 
+@@ -133,3 +133,7 @@ usb0_drd_sw: endpoint {
+ 		};
+ 	};
+ };
++
++&hdmi {
++	extcon = <&anx7688 0>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index aeb5c69fe51d..c4e3547e02e9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -34,7 +34,7 @@ &mmc1 {
+ };
+ 
+ &i2c0 {
+-	hdmi-bridge@28 {
++	anx7688: hdmi-bridge@28 {
+ 		compatible = "analogix,anx7688";
+ 		reg = <0x28>;
+ 
+@@ -121,3 +121,7 @@ usb0_drd_sw: endpoint {
+ 		};
+ 	};
+ };
++
++&hdmi {
++	extcon = <&anx7688 0>;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
new file mode 100644
index 000000000000..9863c81211c1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
@@ -0,0 +1,38 @@
+From 7a891e8c220e74c040bf2862173bab65ec8fd47e Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 18 Feb 2024 17:39:58 +0100
+Subject: arm64: dts: sun50i-a64-pinetab: Add accelerometer
+
+Add accelerometer. Patch picked up from here:
+
+https://github.com/dreemurrs-embedded/Pine64-Arch/blob/master/PKGBUILDS/pine64/linux-megi/pinetab-accelerometer.patch
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 910ed4730615..d4b41ffe0bde 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -237,7 +237,15 @@ &i2c0_pins {
+ &i2c1 {
+ 	status = "okay";
+ 
+-	/* TODO: add Bochs BMA223 accelerometer here */
++	bma223@18 {
++		compatible = "bosch,bma223", "bosch,bma222e";
++		reg = <0x18>;
++		interrupt-parent = <&pio>;
++		interrupts = <7 5 IRQ_TYPE_LEVEL_HIGH>; /* PH5 */
++		mount-matrix = "0", "-1", "0",
++			       "-1", "0", "0",
++			       "0", "0", "-1";
++	};
+ };
+ 
+ &lradc {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
new file mode 100644
index 000000000000..5a4b99346209
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
@@ -0,0 +1,28 @@
+From ad3afcc24d1510604b2a2a55831eedf52581ff46 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 18 Feb 2024 17:38:00 +0100
+Subject: arm64: dts: sun50i-a64-pinetab: Name sound card PineTab
+
+There's no upstream UCM for PineTab, yet. So I guess we can safely
+rename it. Pine64-Arch is using this name.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 9bc1f71bdf5c..910ed4730615 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -475,6 +475,7 @@ hdmi_out_con: endpoint {
+ 
+ &sound {
+ 	status = "okay";
++	simple-audio-card,name = "PineTab";
+ 	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
+ 	simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
+ 				    "Microphone", "Internal Microphone Right",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
new file mode 100644
index 000000000000..250e0dbfbc35
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
@@ -0,0 +1,44 @@
+From 248803c4f6a03fc846c685beb6efe6bc69cb21d6 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Sun, 14 Apr 2019 23:46:47 +0800
+Subject: arm64: dts: sun50i-a64-pinetab: enable RTL8723CS bluetooth
+
+PineTab has a RTL8723CS Wi-Fi/BT combo chip on board, the bluetooth part
+of it communicates with A64 via UART, and the power of it is controlled
+with some GPIO at PL bank.
+
+Enable the bluetooth in the device tree.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ .../boot/dts/allwinner/sun50i-a64-pinetab.dts      | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index d4b41ffe0bde..6a5cac22b465 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -511,6 +511,20 @@ &uart0 {
+ 	status = "okay";
+ };
+ 
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723cs-bt";
++		reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
++		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		firmware-postfix = "pinebook";
++	};
++};
++
+ &usb_otg {
+ 	dr_mode = "otg";
+ 	status = "okay";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
new file mode 100644
index 000000000000..2b1bd421766a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
@@ -0,0 +1,35 @@
+From 5e9ba4ea91bbbdfce8fe2e99a31655f5e8b41690 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 13 Mar 2023 06:02:46 +0100
+Subject: arm64: dts: sun50i-h5: Add missing GPU trip point
+
+Without this, thermal sensor driver fails to probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index e02a3848003e..a6a2e2a19e75 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -234,6 +234,15 @@ gpu-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 1>;
++
++			trips {
++				gpu_crit: gpu-crit {
++					/* milliCelsius */
++					temperature = <110000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
+ 		};
+ 	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
new file mode 100644
index 000000000000..e6b05cb81c87
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
@@ -0,0 +1,97 @@
+From 63bb17e36dd7613071ce221d95a597d1c95a326a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 17 Aug 2020 23:43:53 +0200
+Subject: arm64: dts: sun50i-h5: Use my own more aggressive OPPs on H5
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 44 +++++++++----------
+ 1 file changed, 22 insertions(+), 22 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
+index 1afad8b437d7..a74463c8cc52 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
+@@ -6,57 +6,57 @@ cpu_opp_table: opp-table-cpu {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
+-		opp-408000000 {
+-			opp-hz = /bits/ 64 <408000000>;
+-			opp-microvolt = <1000000 1000000 1310000>;
++		opp-480000000 {
++			opp-hz = /bits/ 64 <480000000>;
++			opp-microvolt = <1040000 1040000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-648000000 {
+ 			opp-hz = /bits/ 64 <648000000>;
+-			opp-microvolt = <1040000 1040000 1310000>;
++			opp-microvolt = <1040000 1040000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-816000000 {
+ 			opp-hz = /bits/ 64 <816000000>;
+-			opp-microvolt = <1080000 1080000 1310000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-912000000 {
+-			opp-hz = /bits/ 64 <912000000>;
+-			opp-microvolt = <1120000 1120000 1310000>;
++			opp-microvolt = <1100000 1100000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-960000000 {
+ 			opp-hz = /bits/ 64 <960000000>;
+-			opp-microvolt = <1160000 1160000 1310000>;
++			opp-microvolt = <1200000 1200000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-1008000000 {
+ 			opp-hz = /bits/ 64 <1008000000>;
+-			opp-microvolt = <1200000 1200000 1310000>;
++			opp-microvolt = <1200000 1200000 1300000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1104000000 {
++			opp-hz = /bits/ 64 <1104000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1056000000 {
+-			opp-hz = /bits/ 64 <1056000000>;
+-			opp-microvolt = <1240000 1240000 1310000>;
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1104000000 {
+-			opp-hz = /bits/ 64 <1104000000>;
+-			opp-microvolt = <1260000 1260000 1310000>;
++		opp-1296000000 {
++			opp-hz = /bits/ 64 <1296000000>;
++			opp-microvolt = <1340000 1340000 1340000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1152000000 {
+-			opp-hz = /bits/ 64 <1152000000>;
+-			opp-microvolt = <1300000 1300000 1310000>;
++		opp-1368000000 {
++			opp-hz = /bits/ 64 <1368000000>;
++			opp-microvolt = <1400000 1400000 1400000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
new file mode 100644
index 000000000000..73bd621d228f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
@@ -0,0 +1,45 @@
+From fe98b7e3099e9542b6b6955f7fff3edd0c72d232 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 10 Sep 2020 21:38:28 +0200
+Subject: arm64: xor: Select 32regs without benchmark to speed up boot
+
+32regs is fastest on Cortex-A53.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/include/asm/xor.h | 14 ++++----------
+ 1 file changed, 4 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/include/asm/xor.h b/arch/arm64/include/asm/xor.h
+index befcd8a7abc9..e4487ddc76e1 100644
+--- a/arch/arm64/include/asm/xor.h
++++ b/arch/arm64/include/asm/xor.h
+@@ -57,21 +57,15 @@ xor_neon_5(unsigned long bytes, unsigned long * __restrict p1,
+ 	kernel_neon_end();
+ }
+ 
+-static struct xor_block_template xor_block_arm64 = {
++static struct xor_block_template xor_block_arm64 __maybe_unused = {
+ 	.name   = "arm64_neon",
+ 	.do_2   = xor_neon_2,
+ 	.do_3   = xor_neon_3,
+ 	.do_4   = xor_neon_4,
+ 	.do_5	= xor_neon_5
+ };
+-#undef XOR_TRY_TEMPLATES
+-#define XOR_TRY_TEMPLATES           \
+-	do {        \
+-		xor_speed(&xor_block_8regs);    \
+-		xor_speed(&xor_block_32regs);    \
+-		if (cpu_has_neon()) { \
+-			xor_speed(&xor_block_arm64);\
+-		} \
+-	} while (0)
++
++#define XOR_SELECT_TEMPLATE(x)	\
++	(&xor_block_32regs)
+ 
+ #endif /* ! CONFIG_KERNEL_MODE_NEON */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
new file mode 100644
index 000000000000..1b6c55847baa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
@@ -0,0 +1,35 @@
+From fbb1db1b96dadfa7c4dffc96ae344d1300565f30 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 7 Aug 2022 14:28:16 +0200
+Subject: bluetooth: bcm: Restore drive_rts_on_open = true behavior on
+ bcm20702a1
+
+This is what it was on v5.5. It doesn't fix the UART issues though.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/bluetooth/hci_bcm.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c
+index 89d4c2224546..78c139ac0331 100644
+--- a/drivers/bluetooth/hci_bcm.c
++++ b/drivers/bluetooth/hci_bcm.c
+@@ -1593,8 +1593,13 @@ static struct bcm_device_data cyw55572_device_data = {
+ 	.max_autobaud_speed = 921600,
+ };
+ 
++static struct bcm_device_data bcm20702a1_device_data = {
++	.drive_rts_on_open = true,
++	.no_early_set_baudrate = true,
++};
++
+ static const struct of_device_id bcm_bluetooth_of_match[] = {
+-	{ .compatible = "brcm,bcm20702a1" },
++	{ .compatible = "brcm,bcm20702a1", .data = &bcm20702a1_device_data },
+ 	{ .compatible = "brcm,bcm4329-bt" },
+ 	{ .compatible = "brcm,bcm4330-bt" },
+ 	{ .compatible = "brcm,bcm4334-bt" },
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
new file mode 100644
index 000000000000..6e27f0b6f2d5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
@@ -0,0 +1,28 @@
+From 6237c7dc27af84d234d2b4f11e64e13e8d9d058d Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 30 Apr 2023 18:12:17 +0200
+Subject: bluetooth: h5: Don't re-initialize rtl8723cs on resume
+
+The power is kept across during sleep, and this is not necessary.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/bluetooth/hci_h5.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c
+index c0436881a533..3f6955ce9b7c 100644
+--- a/drivers/bluetooth/hci_h5.c
++++ b/drivers/bluetooth/hci_h5.c
+@@ -1108,7 +1108,7 @@ static const struct of_device_id rtl_bluetooth_of_match[] = {
+ 	{ .compatible = "realtek,rtl8723bs-bt",
+ 	  .data = (const void *)&h5_data_rtl8723bs },
+ 	{ .compatible = "realtek,rtl8723cs-bt",
+-	  .data = (const void *)&h5_data_rtl8723bs },
++	  .data = (const void *)&h5_data_rtl8822cs },
+ 	{ .compatible = "realtek,rtl8723ds-bt",
+ 	  .data = (const void *)&h5_data_rtl8723bs },
+ #endif
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/bus-sunxi-rsb-Always-check-register-address-validity.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/bus-sunxi-rsb-Always-check-register-address-validity.patch
new file mode 100644
index 000000000000..f6be13ca164a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/bus-sunxi-rsb-Always-check-register-address-validity.patch
@@ -0,0 +1,32 @@
+From f1b46e62b0c22379ce761038387a350d21f5cbd4 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 30 Dec 2019 21:56:59 -0600
+Subject: bus: sunxi-rsb: Always check register address validity
+
+The register address was already validated for read operations before
+being truncated to a u8. Write operations have the same set of possible
+addresses, and the address is being truncated from u32 to u8 here as
+well, so the same check is needed.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/bus/sunxi-rsb.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c
+index 1e29ba76615d..7dcb990cdaf2 100644
+--- a/drivers/bus/sunxi-rsb.c
++++ b/drivers/bus/sunxi-rsb.c
+@@ -447,6 +447,9 @@ static int regmap_sunxi_rsb_reg_write(void *context, unsigned int reg,
+ 	struct sunxi_rsb_ctx *ctx = context;
+ 	struct sunxi_rsb_device *rdev = ctx->rdev;
+ 
++	if (reg > 0xff)
++		return -EINVAL;
++
+ 	return sunxi_rsb_write(rdev->rsb, rdev->rtaddr, reg, &val, ctx->size);
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/clk-Implement-protected-clocks-for-all-OF-clock-providers.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-Implement-protected-clocks-for-all-OF-clock-providers.patch
new file mode 100644
index 000000000000..ad097952a88a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-Implement-protected-clocks-for-all-OF-clock-providers.patch
@@ -0,0 +1,206 @@
+From 12c35c75b3dbc9f11a7caab4c157c8b0c7b376b8 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 29 Dec 2019 20:23:28 -0600
+Subject: clk: Implement protected-clocks for all OF clock providers
+
+This is a generic implementation of the "protected-clocks" property from
+the common clock binding. It allows firmware to inform the OS about
+clocks that must not be disabled while the OS is running.
+
+This implementation comes with some caveats:
+
+1) Clocks that have CLK_IS_CRITICAL in their init data are prepared/
+enabled before they are attached to the clock tree. protected-clocks are
+only protected once the clock provider is added, which is generally
+after all of the clocks it provides have been registered. This leaves a
+window of opportunity where something could disable or modify the clock,
+such as a driver running on another CPU, or the clock core itself. There
+is a comment to this effect in __clk_core_init():
+
+  /*
+   * Enable CLK_IS_CRITICAL clocks so newly added critical clocks
+   * don't get accidentally disabled when walking the orphan tree and
+   * reparenting clocks
+   */
+
+Similarly, these clocks will be enabled after they are first reparented,
+unlike other CLK_IS_CRITICAL clocks. See the comment in
+clk_core_reparent_orphans_nolock():
+
+  /*
+   * We need to use __clk_set_parent_before() and _after() to
+   * to properly migrate any prepare/enable count of the orphan
+   * clock. This is important for CLK_IS_CRITICAL clocks, which
+   * are enabled during init but might not have a parent yet.
+   */
+
+Ideally we could detect protected clocks before they are reparented, but
+there are two problems with that:
+
+  a) From the clock core's perspective, hw->init is const.
+
+  b) The clock core doesn't see the device_node until __clk_register is
+     called on the first clock.
+
+So the only "race-free" way to detect protected-clocks is to do it in
+the middle of __clk_register, between when core->flags is initialized
+and calling __clk_core_init(). That requires scanning the device tree
+again for each clock, which is part of why I didn't do it that way.
+
+2) __clk_protect needs to be idempotent, for two reasons:
+
+  a) Clocks with CLK_IS_CRITICAL in their init data are already
+     prepared/enabled, and we don't want to prepare/enable them again.
+
+  b) of_clk_set_defaults() is called twice for (at least some) clock
+     controllers registered with CLK_OF_DECLARE. It is called first in
+     of_clk_add_provider()/of_clk_add_hw_provider() inside clk_init_cb,
+     and again afterward in of_clk_init(). The second call in
+     of_clk_init() may be unnecessary, but verifying that would require
+     auditing all users of CLK_OF_DECLARE to ensure they called one of
+     the of_clk_add{,_hw}_provider functions.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/clk-conf.c | 54 ++++++++++++++++++++++++++++++++++++++++++
+ drivers/clk/clk.c      | 31 ++++++++++++++++++++++++
+ drivers/clk/clk.h      |  2 ++
+ 3 files changed, 87 insertions(+)
+
+diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
+index 1a4e6340f95c..3b8e22d453cc 100644
+--- a/drivers/clk/clk-conf.c
++++ b/drivers/clk/clk-conf.c
+@@ -11,6 +11,54 @@
+ #include <linux/of.h>
+ #include <linux/printk.h>
+ 
++#include "clk.h"
++
++static int __set_clk_flags(struct device_node *node)
++{
++	struct of_phandle_args clkspec;
++	struct property *prop;
++	int i, index = 0, rc;
++	const __be32 *cur;
++	struct clk *clk;
++	u32 nr_cells;
++
++	rc = of_property_read_u32(node, "#clock-cells", &nr_cells);
++	if (rc < 0) {
++		pr_err("clk: missing #clock-cells property on %pOF\n", node);
++		return rc;
++	}
++
++	clkspec.np         = node;
++	clkspec.args_count = nr_cells;
++
++	of_property_for_each_u32(node, "protected-clocks", prop, cur, clkspec.args[0]) {
++		/* read the remainder of the clock specifier */
++		for (i = 1; i < nr_cells; ++i) {
++			cur = of_prop_next_u32(prop, cur, &clkspec.args[i]);
++			if (!cur) {
++				pr_err("clk: invalid value of protected-clocks"
++				       " property at %pOF\n", node);
++				return -EINVAL;
++			}
++		}
++		clk = of_clk_get_from_provider(&clkspec);
++		if (IS_ERR(clk)) {
++			if (PTR_ERR(clk) != -EPROBE_DEFER)
++				pr_err("clk: couldn't get protected clock"
++				       " %u for %pOF\n", index, node);
++			return PTR_ERR(clk);
++		}
++
++		rc = __clk_protect(clk);
++		if (rc < 0)
++			pr_warn("clk: failed to protect %s: %d\n",
++				__clk_get_name(clk), rc);
++		clk_put(clk);
++		index++;
++	}
++	return 0;
++}
++
+ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
+ {
+ 	struct of_phandle_args clkspec;
+@@ -143,6 +191,12 @@ int of_clk_set_defaults(struct device_node *node, bool clk_supplier)
+ 	if (!node)
+ 		return 0;
+ 
++	if (clk_supplier) {
++		rc = __set_clk_flags(node);
++		if (rc < 0)
++			return rc;
++	}
++
+ 	rc = __set_clk_parents(node, clk_supplier);
+ 	if (rc < 0)
+ 		return rc;
+diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
+index 8cca52be993f..d6590be526be 100644
+--- a/drivers/clk/clk.c
++++ b/drivers/clk/clk.c
+@@ -4737,6 +4737,37 @@ struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
+ }
+ EXPORT_SYMBOL_GPL(devm_clk_hw_get_clk);
+ 
++/*
++ * clk-conf helpers
++ */
++
++int __clk_protect(struct clk *clk)
++{
++	struct clk_core *core = clk->core;
++	int ret = 0;
++
++	clk_prepare_lock();
++
++	/*
++	 * If CLK_IS_CRITICAL was set in the clock's init data, then
++	 * the clock was already prepared/enabled when it was added.
++	 */
++	if (core->flags & CLK_IS_CRITICAL)
++		goto out;
++
++	core->flags |= CLK_IS_CRITICAL;
++	ret = clk_core_prepare(core);
++	if (ret)
++		goto out;
++
++	ret = clk_core_enable_lock(core);
++
++out:
++	clk_prepare_unlock();
++
++	return ret;
++}
++
+ /*
+  * clkdev helpers
+  */
+diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h
+index 2d801900cad5..367a0f036b13 100644
+--- a/drivers/clk/clk.h
++++ b/drivers/clk/clk.h
+@@ -24,6 +24,7 @@ struct clk_hw *clk_find_hw(const char *dev_id, const char *con_id);
+ #ifdef CONFIG_COMMON_CLK
+ struct clk *clk_hw_create_clk(struct device *dev, struct clk_hw *hw,
+ 			      const char *dev_id, const char *con_id);
++int __clk_protect(struct clk *clk);
+ void __clk_put(struct clk *clk);
+ #else
+ /* All these casts to avoid ifdefs in clkdev... */
+@@ -33,6 +34,7 @@ clk_hw_create_clk(struct device *dev, struct clk_hw *hw, const char *dev_id,
+ {
+ 	return (struct clk *)hw;
+ }
++static inline int __clk_protect(struct clk *clk) { return 0; }
+ static inline void __clk_put(struct clk *clk) { }
+ 
+ #endif
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
new file mode 100644
index 000000000000..6d15d532817d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
@@ -0,0 +1,55 @@
+From d6a7d69f210282afda61913e5af9abd6d6c2e8ae Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 10 Mar 2020 06:04:32 +0100
+Subject: clk: sunxi-ng: Don't use CPU PLL gating and CPUX reparenting to HOSC
+
+It's not necessary when not using dividers on CPU PLL, and it's
+causing cntvct jump backs on H3.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 21 ---------------------
+ 1 file changed, 21 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 4f77bbb9e82e..8b419f8edaa6 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -1029,20 +1029,6 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
+ 	.num_resets	= ARRAY_SIZE(sun50i_h5_ccu_resets),
+ };
+ 
+-static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
+-	.common	= &pll_cpux_clk.common,
+-	/* copy from pll_cpux_clk */
+-	.enable	= BIT(31),
+-	.lock	= BIT(28),
+-};
+-
+-static struct ccu_mux_nb sun8i_h3_cpu_nb = {
+-	.common		= &cpux_clk.common,
+-	.cm		= &cpux_clk.mux,
+-	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
+-	.bypass_index	= 1, /* index of 24 MHz oscillator */
+-};
+-
+ static int sun8i_h3_ccu_probe(struct platform_device *pdev)
+ {
+ 	const struct sunxi_ccu_desc *desc;
+@@ -1067,13 +1053,6 @@ static int sun8i_h3_ccu_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
+-	/* Gate then ungate PLL CPU after any rate changes */
+-	ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
+-
+-	/* Reparent CPU during PLL CPU rate changes */
+-	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
+-				  &sun8i_h3_cpu_nb);
+-
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
new file mode 100644
index 000000000000..b8263efc4407
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
@@ -0,0 +1,59 @@
+From be8f956cc8f9474d0bf108b68813b2c614a9e0ba Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 3 Apr 2021 17:14:49 -0500
+Subject: clk: sunxi-ng: Export CLK_DRAM for devfreq
+
+MBUS needs to reference the CLK_DRAM clock, as it is responsible for
+DRAM frequency scaling.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-a83t.h      | 4 ----
+ include/dt-bindings/clock/sun8i-a83t-ccu.h | 5 ++---
+ 2 files changed, 2 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
+index 40e575ba51d2..6c927bc75224 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
+@@ -42,12 +42,8 @@
+ 
+ /* module and usb clocks exported */
+ 
+-#define CLK_DRAM		82
+-
+ /* dram gates and more module clocks exported */
+ 
+-#define CLK_MBUS		95
+-
+ /* more module clocks exported */
+ 
+ #define CLK_NUMBER		(CLK_GPU_HYD + 1)
+diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h
+index 78af5085f630..affe1857eb54 100644
+--- a/include/dt-bindings/clock/sun8i-a83t-ccu.h
++++ b/include/dt-bindings/clock/sun8i-a83t-ccu.h
+@@ -116,10 +116,9 @@
+ #define CLK_USB_HSIC		79
+ #define CLK_USB_HSIC_12M	80
+ #define CLK_USB_OHCI0		81
+-
++#define CLK_DRAM		82
+ #define CLK_DRAM_VE		83
+ #define CLK_DRAM_CSI		84
+-
+ #define CLK_TCON0		85
+ #define CLK_TCON1		86
+ #define CLK_CSI_MISC		87
+@@ -130,7 +129,7 @@
+ #define CLK_AVS			92
+ #define CLK_HDMI		93
+ #define CLK_HDMI_SLOW		94
+-
++#define CLK_MBUS		95
+ #define CLK_MIPI_DSI0		96
+ #define CLK_MIPI_DSI1		97
+ #define CLK_GPU_CORE		98
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
new file mode 100644
index 000000000000..b2c54eb361ab
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
@@ -0,0 +1,59 @@
+From e682f408f47e4f8c815d36941d17cf37251e4bf5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 12 Jan 2017 16:34:57 +0100
+Subject: clk: sunxi-ng: Set maximum P and M factors to 1 for H3 pll-cpux clock
+
+When using M factor greater than 1 system is experiencing
+occasional lockups. P factor should only be used for clock
+speeds below 288MHz. We don't use such speeds in the mainline
+kernel.
+
+This change was verified to fix lockups with PLL stress
+tester available at https://xff.cz/git/arisc-firmware/.
+
+Note that M factor must not be used outside the kernel either,
+so for example u-boot needs a similar patch.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index ca5739fa04f7..4f77bbb9e82e 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -25,15 +25,21 @@
+ 
+ #include "ccu-sun8i-h3.h"
+ 
+-static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
+-				     "osc24M", 0x000,
+-				     8, 5,	/* N */
+-				     4, 2,	/* K */
+-				     0, 2,	/* M */
+-				     16, 2,	/* P */
+-				     BIT(31),	/* gate */
+-				     BIT(28),	/* lock */
+-				     CLK_SET_RATE_UNGATE);
++static struct ccu_nkmp pll_cpux_clk = {
++	.enable		= BIT(31),
++	.lock		= BIT(28),
++	.n		= _SUNXI_CCU_MULT(8, 5),
++	.k		= _SUNXI_CCU_MULT(4, 2),
++	.m		= _SUNXI_CCU_DIV_MAX(0, 2, 1),
++	.p		= _SUNXI_CCU_DIV_MAX(16, 2, 1),
++	.common		= {
++		.reg		= 0x000,
++		.hw.init	= CLK_HW_INIT("pll-cpux",
++					      "osc24M",
++					      &ccu_nkmp_ops,
++					      CLK_SET_RATE_UNGATE),
++	},
++};
+ 
+ /*
+  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
new file mode 100644
index 000000000000..3fe913bc6eb5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
@@ -0,0 +1,87 @@
+From b7bc9f26f407f704a9b43610e216a1072913b026 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jul 2020 17:10:15 -0500
+Subject: clk: sunxi-ng: a64: Increase PLL_AUDIO base frequency
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 41 +++++++++++++++++++++------
+ 1 file changed, 32 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index 491b16cfe368..399d68586274 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -47,15 +47,35 @@ static struct ccu_nkmp pll_cpux_clk = {
+  * With sigma-delta modulation for fractional-N on the audio PLL,
+  * we have to use specific dividers. This means the variable divider
+  * can no longer be used, as the audio codec requests the exact clock
+- * rates we support through this mechanism. So we now hard code the
+- * variable divider to 1. This means the clock rates will no longer
+- * match the clock names.
++ * rates we support through this mechanism.
++ *
++ * For the audio codec to work correctly, pll-audio must be exactly
++ * 22579200 Hz or 24576000 Hz, and pll-audio-4x (1x the base) must be
++ * between 3x and 8x that frequency. For the SRC to work at 96 kHz,
++ * pll-audio-4x must be at least 6x pll-audio.
++ *
++ * For now, hard code the variable divider to 3.
+  */
+ #define SUN50I_A64_PLL_AUDIO_REG	0x008
++#define SUN50I_A64_PLL_AUDIO_BIAS_REG	0x224
+ 
+ static struct ccu_sdm_setting pll_audio_sdm_table[] = {
+-	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
+-	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
++	/* 24000000 * (  7 + 0x10d84 / 131072 ) /  8 / 1 - 22579200 == -6.9Hz */
++	{ .rate =  22579200, .pattern = 0xc0010d84, .m =  8, .n =  7 },
++	/* 24000000 * ( 14 + 0x0ac02 / 131072 ) / 14 / 1 - 24576000 == -2.5Hz */
++	{ .rate =  24576000, .pattern = 0xc000ac08, .m = 14, .n = 14 },
++	/* 24000000 * (  8 + 0x0ef35 / 131072 ) /  3 / 3 - 22579200 ==  3.3Hz */
++	{ .rate =  67737600, .pattern = 0xc000ef35, .m =  3, .n =  8 },
++	/* 24000000 * ( 15 + 0x0b852 / 131072 ) /  5 / 3 - 24576000 ==  1.0Hz */
++	{ .rate =  73728000, .pattern = 0xc000b852, .m =  5, .n = 15 },
++	/* 24000000 * (  7 + 0x10d84 / 131072 ) /  2 / 4 - 22579200 == -6.9Hz */
++	{ .rate =  90316800, .pattern = 0xc0010d84, .m =  2, .n =  7 },
++	/* 24000000 * ( 16 + 0x0c49c / 131072 ) /  4 / 4 - 24576000 ==  4.0Hz */
++	{ .rate =  98304000, .pattern = 0xc000c49c, .m =  4, .n = 16 },
++	/* 24000000 * (  5 + 0x14a23 / 131072 ) /  1 / 6 - 22579200 == -6.9Hz */
++	{ .rate = 135475200, .pattern = 0xc0014a23, .m =  1, .n =  5 },
++	/* 24000000 * ( 12 + 0x09375 / 131072 ) /  2 / 6 - 24576000 ==  4.0Hz */
++	{ .rate = 147456000, .pattern = 0xc0009375, .m =  2, .n = 12 },
+ };
+ 
+ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+@@ -610,10 +630,10 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
+ 	&pll_audio_base_clk.common.hw
+ };
+ 
+-/* We hardcode the divider to 1 for now */
++/* We hardcode the divider to 3 for now */
+ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ 			    clk_parent_pll_audio,
+-			    1, 1, CLK_SET_RATE_PARENT);
++			    3, 1, CLK_SET_RATE_PARENT);
+ static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ 			    clk_parent_pll_audio,
+ 			    2, 1, CLK_SET_RATE_PARENT);
+@@ -952,10 +972,13 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	if (IS_ERR(reg))
+ 		return PTR_ERR(reg);
+ 
+-	/* Force the PLL-Audio-1x divider to 1 */
++	/* Force the pll-audio variable divider to 3 */
+ 	val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
+ 	val &= ~GENMASK(19, 16);
+-	writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
++	writel(val | (2 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
++
++	/* Decrease the PLL AUDIO bias current to reduce noise. */
++	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
+ 
+ 	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
new file mode 100644
index 000000000000..865b1cc45a53
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
@@ -0,0 +1,47 @@
+From 87c4069368ef80a39d43cd4ef42b0ea5f360c58c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 14 Aug 2023 07:28:11 +0200
+Subject: clk: sunxi-ng: sun50i-a64: Switch parent of MIPI-DSI to periph0(1x)
+
+This makes video0(1x) clock less constrained, and improves compatibility
+with external monitors on Pinephone when using both internal display
+and HDMI output at once.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index 95aea78a0fd6..ee49e1db9d8b 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -962,6 +962,8 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
+ 	.bypass_index	= 1, /* index of 24 MHz oscillator */
+ };
+ 
++#define CCU_MIPI_DSI_CLK 0x168
++
+ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ {
+ 	void __iomem *reg;
+@@ -981,9 +983,15 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
+ 
+ 	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
+-	if (ret)
++	if (ret) {
+ 		writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ 
++		/* Set MIPI-DSI clock parent to periph0(1x), so that video0(1x) is free to change. */
++		val = readl(reg + CCU_MIPI_DSI_CLK);
++		val &= 0x30f;
++		val |= (2 << 8) | ((4 - 1) << 0); /* M-1 */
++		writel(val, reg + CCU_MIPI_DSI_CLK);
++	}
+ 	/* Set PLL MIPI as parent for TCON0 */
+ 	val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
+ 	val &= ~GENMASK(26, 24);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
new file mode 100644
index 000000000000..4fa95c66720b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
@@ -0,0 +1,29 @@
+From 41ed79af60250bb45346efdb083cf636150e37d4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 31 Oct 2019 18:31:32 +0100
+Subject: cpufreq: sun50i: Show detected CPU bin, for easier debugging
+
+Useful for people running into crashes during boot, due to issues
+with OPP voltages.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/cpufreq/sun50i-cpufreq-nvmem.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+index ef83e4bf2639..60d913400d76 100644
+--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+@@ -236,6 +236,8 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
+ 	snprintf(name, sizeof(name), "speed%d", speed);
+ 	config.prop_name = name;
+ 
++	pr_info("Using CPU speed bin %s\n", name);
++
+ 	for_each_possible_cpu(cpu) {
+ 		struct device *cpu_dev = get_cpu_device(cpu);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
new file mode 100644
index 000000000000..7a0b18f4065a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
@@ -0,0 +1,152 @@
+From 77aaef12cb85ddbae2a6417bcedae26f322d6ebf Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 1 Sep 2023 00:57:04 +0200
+Subject: drm: bridge: dw-hdmi: Allow to accept HPD status from other drivers
+
+This change allows other drivers to provide HPD status.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 63 +++++++++++++++++++++--
+ 1 file changed, 59 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 9f2bc932c371..4fd58d829c82 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -9,6 +9,7 @@
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/err.h>
++#include <linux/extcon.h>
+ #include <linux/hdmi.h>
+ #include <linux/i2c.h>
+ #include <linux/irq.h>
+@@ -198,6 +199,8 @@ struct dw_hdmi {
+ 	hdmi_codec_plugged_cb plugged_cb;
+ 	struct device *codec_dev;
+ 	enum drm_connector_status last_connector_result;
++	struct extcon_dev *extcon;
++	struct notifier_block extcon_nb;
+ };
+ 
+ #define HDMI_IH_PHY_STAT0_RX_SENSE \
+@@ -1689,6 +1692,12 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
+ enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
+ 					       void *data)
+ {
++	if (hdmi->extcon) {
++		return extcon_get_state(hdmi->extcon, EXTCON_DISP_HDMI) > 0
++			? connector_status_connected
++			: connector_status_disconnected;
++	}
++
+ 	return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
+ 		connector_status_connected : connector_status_disconnected;
+ }
+@@ -1699,7 +1708,7 @@ void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
+ {
+ 	u8 old_mask = hdmi->phy_mask;
+ 
+-	if (force || disabled || !rxsense)
++	if (force || disabled || !rxsense || hdmi->extcon)
+ 		hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
+ 	else
+ 		hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
+@@ -3131,7 +3140,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ 			status = connector_status_disconnected;
+ 	}
+ 
+-	if (status != connector_status_unknown) {
++	if (status != connector_status_unknown && !hdmi->extcon) {
+ 		dev_dbg(hdmi->dev, "EVENT=%s\n",
+ 			status == connector_status_connected ?
+ 			"plugin" : "plugout");
+@@ -3317,6 +3326,25 @@ bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi)
+ }
+ EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420);
+ 
++static int dw_hdmi_extcon_notifier(struct notifier_block *nb,
++				   unsigned long event, void *ptr)
++{
++	struct dw_hdmi *hdmi = container_of(nb, struct dw_hdmi, extcon_nb);
++
++	enum drm_connector_status status = dw_hdmi_phy_read_hpd(hdmi, NULL);
++
++	dev_info(hdmi->dev, "EVENT=%s\n",
++		 status == connector_status_connected ? "plugin" : "plugout");
++
++	if (hdmi->bridge.dev) {
++		//XXX: ???
++		drm_helper_hpd_irq_event(hdmi->bridge.dev);
++		drm_bridge_hpd_notify(&hdmi->bridge, status);
++	}
++
++	return NOTIFY_DONE;
++}
++
+ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
+ 			      const struct dw_hdmi_plat_data *plat_data)
+ {
+@@ -3358,15 +3386,38 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
+ 	if (ret < 0)
+ 		return ERR_PTR(ret);
+ 
++	hdmi->extcon = extcon_get_edev_by_phandle(dev, 0);
++	if (IS_ERR(hdmi->extcon)) {
++		if (PTR_ERR(hdmi->extcon) == -ENODEV) {
++			hdmi->extcon = NULL;
++		} else {
++			if (PTR_ERR(hdmi->extcon) != -EPROBE_DEFER)
++				dev_err(dev, "Invalid or missing extcon\n");
++			return ERR_CAST(hdmi->extcon);
++		}
++	}
++
++	if (hdmi->extcon) {
++		/* don't register IRQ for native HPD */
++		hdmi->phy_mask = (u8)~(HDMI_PHY_RX_SENSE);
++
++		hdmi->extcon_nb.notifier_call = dw_hdmi_extcon_notifier;
++		ret = extcon_register_notifier_all(hdmi->extcon, &hdmi->extcon_nb);
++		if (ret < 0) {
++			dev_err(dev, "failed to register extcon notifier\n");
++			return ERR_PTR(ret);
++		}
++	}
++
+ 	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
+ 	if (ddc_node) {
+ 		hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
+ 		of_node_put(ddc_node);
+ 		if (!hdmi->ddc) {
+ 			dev_dbg(hdmi->dev, "failed to read ddc node\n");
+-			return ERR_PTR(-EPROBE_DEFER);
++			ret = -EPROBE_DEFER;
++			goto err_extcon;
+ 		}
+-
+ 	} else {
+ 		dev_dbg(hdmi->dev, "no ddc property found\n");
+ 	}
+@@ -3610,6 +3661,8 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
+ 	clk_disable_unprepare(hdmi->isfr_clk);
+ err_res:
+ 	i2c_put_adapter(hdmi->ddc);
++err_extcon:
++	extcon_unregister_notifier_all(hdmi->extcon, &hdmi->extcon_nb);
+ 
+ 	return ERR_PTR(ret);
+ }
+@@ -3617,6 +3670,8 @@ EXPORT_SYMBOL_GPL(dw_hdmi_probe);
+ 
+ void dw_hdmi_remove(struct dw_hdmi *hdmi)
+ {
++	extcon_unregister_notifier_all(hdmi->extcon, &hdmi->extcon_nb);
++
+ 	drm_bridge_remove(&hdmi->bridge);
+ 
+ 	if (hdmi->audio && !IS_ERR(hdmi->audio))
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
new file mode 100644
index 000000000000..32f3045305f6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
@@ -0,0 +1,41 @@
+From 4917f7e1ffe1512b66e2b2738b50533d8056c381 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 1 Sep 2023 00:59:08 +0200
+Subject: drm: bridge: dw-hdmi: Report HDMI hotplug events
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 4fd58d829c82..5ee318de2ef1 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -2458,7 +2458,13 @@ static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
+ 	enum drm_connector_status result;
+ 
+ 	result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
+-	hdmi->last_connector_result = result;
++
++	if (result != hdmi->last_connector_result) {
++		dev_info(hdmi->dev, "read_hpd result: %d", result);
++		handle_plugged_change(hdmi,
++				      result == connector_status_connected);
++		hdmi->last_connector_result = result;
++	}
+ 
+ 	return result;
+ }
+@@ -3141,7 +3147,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ 	}
+ 
+ 	if (status != connector_status_unknown && !hdmi->extcon) {
+-		dev_dbg(hdmi->dev, "EVENT=%s\n",
++		dev_info(hdmi->dev, "EVENT=%s\n",
+ 			status == connector_status_connected ?
+ 			"plugin" : "plugout");
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
new file mode 100644
index 000000000000..aa5bf272591c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
@@ -0,0 +1,37 @@
+From 7895ba31d1056ef84bffd06aec8cb19ff1826bf4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 29 Oct 2020 04:55:40 +0100
+Subject: drm/panel: st7703: Fix xbd599 timings to make refresh rate exactly
+ 60.006Hz
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/panel/panel-sitronix-st7703.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+index 7d8302cca091..56d3a98e384b 100644
+--- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+@@ -321,14 +321,14 @@ static int xbd599_init_sequence(struct st7703 *ctx)
+ 
+ static const struct drm_display_mode xbd599_mode = {
+ 	.hdisplay    = 720,
+-	.hsync_start = 720 + 40,
+-	.hsync_end   = 720 + 40 + 40,
+-	.htotal	     = 720 + 40 + 40 + 40,
++	.hsync_start = 720 + 30,
++	.hsync_end   = 720 + 30 + 28,
++	.htotal	     = 720 + 30 + 28 + 30,
+ 	.vdisplay    = 1440,
+ 	.vsync_start = 1440 + 18,
+ 	.vsync_end   = 1440 + 18 + 10,
+ 	.vtotal	     = 1440 + 18 + 10 + 17,
+-	.clock	     = 69000,
++	.clock	     = 72000,
+ 	.flags	     = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ 	.width_mm    = 68,
+ 	.height_mm   = 136,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
new file mode 100644
index 000000000000..3e86d415413a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
@@ -0,0 +1,36 @@
+From 71619238f704dbbdd5c4056866f82312f7c46e11 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 24 Sep 2022 21:54:23 +0200
+Subject: drm: rockchip: Fix panic on reboot when DRM device fails to bind
+
+When DRM device is freed, we need to clear the drvdata pointer, because
+it now points to invalid memory.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+index ab55d7132550..5e2a4c967f83 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+@@ -202,6 +202,7 @@ static int rockchip_drm_bind(struct device *dev)
+ 	component_unbind_all(dev, drm_dev);
+ err_free:
+ 	drm_dev_put(drm_dev);
++	dev_set_drvdata(dev, NULL);
+ 	return ret;
+ }
+ 
+@@ -218,6 +219,7 @@ static void rockchip_drm_unbind(struct device *dev)
+ 	rockchip_iommu_cleanup(drm_dev);
+ 
+ 	drm_dev_put(drm_dev);
++	dev_set_drvdata(dev, NULL);
+ }
+ 
+ DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch
new file mode 100644
index 000000000000..8562c551282e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch
@@ -0,0 +1,35 @@
+From e01d25402dbd30bb07415d8195db135f51af2b4e Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 9 Jun 2024 14:30:12 +0200
+Subject: drm: rockchip: dw-mipi-dsi-rockchip: Fix ISP1 PHY initialization
+
+After suspend/resume cycle, ISP1 would stop receiving data.
+Re-initializing DPHY during PHY power on fixes the issue.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+index 4cc8ed8f4fbd..9ad48c6dfac3 100644
+--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+@@ -1240,6 +1240,14 @@ static int dw_mipi_dsi_dphy_power_on(struct phy *phy)
+ 		goto err_phy_cfg_clk;
+ 	}
+ 
++	if (dsi->cdata->dphy_rx_init) {
++		ret = dsi->cdata->dphy_rx_init(phy);
++		if (ret < 0) {
++			DRM_DEV_ERROR(dsi->dev, "hardware-specific phy init failed: %d\n", ret);
++			goto err_pwr_on;
++		}
++	}
++
+ 	/* do soc-variant specific init */
+ 	if (dsi->cdata->dphy_rx_power_on) {
+ 		ret = dsi->cdata->dphy_rx_power_on(phy);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Restore-DPHY-config-on-resume.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Restore-DPHY-config-on-resume.patch
new file mode 100644
index 000000000000..f3973a699948
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Restore-DPHY-config-on-resume.patch
@@ -0,0 +1,94 @@
+From 043e41ba3eeb25029116375921951ad5b2f031c5 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 17 Jul 2024 09:30:39 +0200
+Subject: drm: rockchip: dw-mipi-dsi-rockchip: Restore DPHY config on resume
+
+After a suspend and resume cycle, ISP1 stops receiving data, as observed on the
+Pine64 PinePhone Pro, which is based on the Rockchip RK3399 SoC. Re-initializing
+DPHY during resume, if the SoC variant supports initialization, fixes this
+issue.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 51 ++++++++++++-------
+ 1 file changed, 34 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+index 9ad48c6dfac3..000462c6392a 100644
+--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+@@ -1122,6 +1122,31 @@ static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = {
+ 	.unbind	= dw_mipi_dsi_rockchip_dphy_unbind,
+ };
+ 
++static int dw_mipi_dsi_dphy_rx_init(struct dw_mipi_dsi_rockchip *dsi)
++{
++	int ret;
++
++	if (dsi->cdata->dphy_rx_init) {
++		ret = clk_prepare_enable(dsi->pclk);
++		if (ret < 0)
++			return ret;
++
++		ret = clk_prepare_enable(dsi->grf_clk);
++		if (ret) {
++			clk_disable_unprepare(dsi->pclk);
++			return ret;
++		}
++
++		ret = dsi->cdata->dphy_rx_init(dsi->dphy);
++		clk_disable_unprepare(dsi->grf_clk);
++		clk_disable_unprepare(dsi->pclk);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++
+ static int dw_mipi_dsi_dphy_init(struct phy *phy)
+ {
+ 	struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
+@@ -1142,23 +1167,9 @@ static int dw_mipi_dsi_dphy_init(struct phy *phy)
+ 	if (ret < 0)
+ 		goto err_graph;
+ 
+-	if (dsi->cdata->dphy_rx_init) {
+-		ret = clk_prepare_enable(dsi->pclk);
+-		if (ret < 0)
+-			goto err_init;
+-
+-		ret = clk_prepare_enable(dsi->grf_clk);
+-		if (ret) {
+-			clk_disable_unprepare(dsi->pclk);
+-			goto err_init;
+-		}
+-
+-		ret = dsi->cdata->dphy_rx_init(phy);
+-		clk_disable_unprepare(dsi->grf_clk);
+-		clk_disable_unprepare(dsi->pclk);
+-		if (ret < 0)
+-			goto err_init;
+-	}
++	ret = dw_mipi_dsi_dphy_rx_init(dsi);
++	if (ret < 0)
++		goto err_init;
+ 
+ 	return 0;
+ 
+@@ -1341,6 +1352,12 @@ static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev)
+ 			dw_mipi_dsi_rockchip_config(dsi->slave);
+ 
+ 		clk_disable_unprepare(dsi->grf_clk);
++	} else if (dsi->usage_mode == DW_DSI_USAGE_PHY) {
++		ret = dw_mipi_dsi_dphy_rx_init(dsi);
++		if (ret < 0) {
++			DRM_DEV_ERROR(dsi->dev, "hardware-specific phy init failed: %d\n", ret);
++			return ret;
++		}
+ 	}
+ 
+ 	return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Add-more-parameters-to-sunxi_engine-commit-callback.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Add-more-parameters-to-sunxi_engine-commit-callback.patch
new file mode 100644
index 000000000000..afb76c5c70c7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Add-more-parameters-to-sunxi_engine-commit-callback.patch
@@ -0,0 +1,112 @@
+From 1e72feb88817f6b8aa830d41d74d86c6ac911b9b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 31 Oct 2022 03:01:28 +0100
+Subject: drm/sun4i: Add more parameters to sunxi_engine commit callback
+
+These will be needed later on when we move layer configuration to
+crtc update.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun4i_backend.c |  4 +++-
+ drivers/gpu/drm/sun4i/sun4i_crtc.c    |  2 +-
+ drivers/gpu/drm/sun4i/sun8i_mixer.c   |  5 ++++-
+ drivers/gpu/drm/sun4i/sunxi_engine.h  | 13 ++++++++++---
+ 4 files changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
+index 335fd0edb904..e89eb96d3131 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
++++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
+@@ -69,7 +69,9 @@ static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
+ 			   SUN4I_BACKEND_OCCTL_ENABLE, 0);
+ }
+ 
+-static void sun4i_backend_commit(struct sunxi_engine *engine)
++static void sun4i_backend_commit(struct sunxi_engine *engine,
++				 struct drm_crtc *crtc,
++				 struct drm_atomic_state *state)
+ {
+ 	DRM_DEBUG_DRIVER("Committing changes\n");
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c
+index c06d7cd45388..18e74047b0f5 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
++++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
+@@ -91,7 +91,7 @@ static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc,
+ 
+ 	DRM_DEBUG_DRIVER("Committing plane changes\n");
+ 
+-	sunxi_engine_commit(scrtc->engine);
++	sunxi_engine_commit(scrtc->engine, crtc, state);
+ 
+ 	if (event) {
+ 		crtc->state->event = NULL;
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 1e681314e379..bdeb9b80e038 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -16,6 +16,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/reset.h>
+ 
++#include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_framebuffer.h>
+@@ -249,7 +250,9 @@ int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format)
+ 	return -EINVAL;
+ }
+ 
+-static void sun8i_mixer_commit(struct sunxi_engine *engine)
++static void sun8i_mixer_commit(struct sunxi_engine *engine,
++			       struct drm_crtc *crtc,
++			       struct drm_atomic_state *state)
+ {
+ 	DRM_DEBUG_DRIVER("Committing changes\n");
+ 
+diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h b/drivers/gpu/drm/sun4i/sunxi_engine.h
+index ec8cf9b2bda4..ec0c4932f15c 100644
+--- a/drivers/gpu/drm/sun4i/sunxi_engine.h
++++ b/drivers/gpu/drm/sun4i/sunxi_engine.h
+@@ -7,6 +7,7 @@
+ #define _SUNXI_ENGINE_H_
+ 
+ struct drm_plane;
++struct drm_crtc;
+ struct drm_device;
+ struct drm_crtc_state;
+ struct drm_display_mode;
+@@ -59,7 +60,9 @@ struct sunxi_engine_ops {
+ 	 *
+ 	 * This function is optional.
+ 	 */
+-	void (*commit)(struct sunxi_engine *engine);
++	void (*commit)(struct sunxi_engine *engine,
++		       struct drm_crtc *crtc,
++		       struct drm_atomic_state *state);
+ 
+ 	/**
+ 	 * @layers_init:
+@@ -144,12 +147,16 @@ struct sunxi_engine {
+ /**
+  * sunxi_engine_commit() - commit all changes of the engine
+  * @engine:	pointer to the engine
++ * @crtc:	pointer to crtc the engine is associated with
++ * @state:	atomic state
+  */
+ static inline void
+-sunxi_engine_commit(struct sunxi_engine *engine)
++sunxi_engine_commit(struct sunxi_engine *engine,
++		    struct drm_crtc *crtc,
++		    struct drm_atomic_state *state)
+ {
+ 	if (engine->ops && engine->ops->commit)
+-		engine->ops->commit(engine);
++		engine->ops->commit(engine, crtc, state);
+ }
+ 
+ /**
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Fix-layer-zpos-change-atomic-modesetting.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Fix-layer-zpos-change-atomic-modesetting.patch
new file mode 100644
index 000000000000..4575a21c648e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Fix-layer-zpos-change-atomic-modesetting.patch
@@ -0,0 +1,386 @@
+From 62feed6a5626e653dba190fab0ee41530b358b94 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 1 Nov 2022 11:49:18 +0100
+Subject: drm/sun4i: Fix layer zpos change/atomic modesetting
+
+Identical configurations of planes can lead to different (and wrong)
+layer -> pipe routing at HW level, depending on the order of atomic
+plane changes.
+
+For example:
+
+- Layer 1 is configured to zpos 0 and thus uses pipe 0. No other layer
+  is enabled. This is a typical situation at boot.
+
+- When a compositor takes over and layer 3 is enabled,
+  sun8i_ui_layer_enable() will get called with old_zpos=0 zpos=1, which
+  will lead to incorrect disabling of pipe 0 and enabling of pipe 1.
+
+What happens is that sun8i_ui_layer_enable() function may disable
+blender pipes even if it is no longer assigned to its layer.
+
+To correct this, move the routing setup out of individual plane's
+atomic_update into crtc's atomic_update, where it can be calculated
+and updated all at once.
+
+Remove the atomic_disable callback because it is no longer needed.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c    | 71 ++++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun8i_mixer.h    |  6 +++
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 73 +------------------------
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 74 +-------------------------
+ 4 files changed, 81 insertions(+), 143 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index bdeb9b80e038..86a38a2f00a7 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -250,12 +250,83 @@ int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format)
+ 	return -EINVAL;
+ }
+ 
++static void sun8i_layer_enable(struct sun8i_layer *layer, bool enable)
++{
++	u32 ch_base = sun8i_channel_base(layer->mixer, layer->channel);
++	u32 val, reg, mask;
++
++	if (layer->type == SUN8I_LAYER_TYPE_UI) {
++		val = enable ? SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN : 0;
++		mask = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
++		reg = SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay);
++	} else {
++		val = enable ? SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN : 0;
++		mask = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
++		reg = SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay);
++	}
++
++	regmap_update_bits(layer->mixer->engine.regs, reg, mask, val);
++}
++
+ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 			       struct drm_crtc *crtc,
+ 			       struct drm_atomic_state *state)
+ {
++	struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
++	u32 bld_base = sun8i_blender_base(mixer);
++	struct drm_plane_state *plane_state;
++	struct drm_plane *plane;
++	u32 route = 0, pipe_en = 0;
++
+ 	DRM_DEBUG_DRIVER("Committing changes\n");
+ 
++	drm_for_each_plane(plane, state->dev) {
++		struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
++		bool enable;
++		int zpos;
++
++		if (!(plane->possible_crtcs & drm_crtc_mask(crtc)) || layer->mixer != mixer)
++			continue;
++
++		plane_state = drm_atomic_get_new_plane_state(state, plane);
++		if (!plane_state)
++			plane_state = plane->state;
++
++		enable = plane_state->crtc && plane_state->visible;
++		zpos = plane_state->normalized_zpos;
++
++		DRM_DEBUG_DRIVER("  plane %d: chan=%d ovl=%d en=%d zpos=%d\n",
++				 plane->base.id, layer->channel, layer->overlay,
++				 enable, zpos);
++
++		/* We always update the layer enable bit, because it can clear
++		 * spontaneously for unknown reasons. */
++		sun8i_layer_enable(layer, enable);
++
++		if (!enable)
++			continue;
++
++		/* Route layer to pipe based on zpos */	
++		route |= layer->channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
++		pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
++	}
++
++	regmap_update_bits(mixer->engine.regs,
++			   SUN8I_MIXER_BLEND_ROUTE(bld_base),
++			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(0) |
++			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(1) |
++			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(2) |
++			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(3),
++			   route);
++
++	regmap_update_bits(mixer->engine.regs,
++			   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(0) |
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(1) |
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(2) |
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(3),
++			   pipe_en);
++
+ 	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
+ 		     SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
+ }
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 5a610ee30301..d7898c9c9cc0 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -186,9 +186,15 @@ struct sun8i_mixer {
+ 	struct clk			*mod_clk;
+ };
+ 
++enum {
++	SUN8I_LAYER_TYPE_UI,
++	SUN8I_LAYER_TYPE_VI,
++};
++
+ struct sun8i_layer {
+ 	struct drm_plane	plane;
+ 	struct sun8i_mixer	*mixer;
++	int			type;
+ 	int			channel;
+ 	int			overlay;
+ };
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index 248fbb606ede..b90e5edef4e8 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -24,55 +24,6 @@
+ #include "sun8i_ui_layer.h"
+ #include "sun8i_ui_scaler.h"
+ 
+-static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
+-				  int overlay, bool enable, unsigned int zpos,
+-				  unsigned int old_zpos)
+-{
+-	u32 val, bld_base, ch_base;
+-
+-	bld_base = sun8i_blender_base(mixer);
+-	ch_base = sun8i_channel_base(mixer, channel);
+-
+-	DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n",
+-			 enable ? "En" : "Dis", channel, overlay);
+-
+-	if (enable)
+-		val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
+-	else
+-		val = 0;
+-
+-	regmap_update_bits(mixer->engine.regs,
+-			   SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
+-			   SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
+-
+-	if (!enable || zpos != old_zpos) {
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+-				   SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
+-				   0);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+-				   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
+-				   0);
+-	}
+-
+-	if (enable) {
+-		val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+-				   val, val);
+-
+-		val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+-				   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
+-				   val);
+-	}
+-}
+-
+ static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
+ 					int overlay, struct drm_plane *plane)
+ {
+@@ -259,36 +210,18 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
+ 						   true, true);
+ }
+ 
+-static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane,
+-					  struct drm_atomic_state *state)
+-{
+-	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+-									   plane);
+-	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+-	unsigned int old_zpos = old_state->normalized_zpos;
+-	struct sun8i_mixer *mixer = layer->mixer;
+-
+-	sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
+-			      old_zpos);
+-}
+ 
+ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
+ 					 struct drm_atomic_state *state)
+ {
+-	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+-									   plane);
+ 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ 									   plane);
+ 	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int zpos = new_state->normalized_zpos;
+-	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+ 
+-	if (!new_state->visible) {
+-		sun8i_ui_layer_enable(mixer, layer->channel,
+-				      layer->overlay, false, 0, old_zpos);
++	if (!new_state->crtc || !new_state->visible)
+ 		return;
+-	}
+ 
+ 	sun8i_ui_layer_update_coord(mixer, layer->channel,
+ 				    layer->overlay, plane, zpos);
+@@ -298,13 +231,10 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
+ 				      layer->overlay, plane);
+ 	sun8i_ui_layer_update_buffer(mixer, layer->channel,
+ 				     layer->overlay, plane);
+-	sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay,
+-			      true, zpos, old_zpos);
+ }
+ 
+ static const struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = {
+ 	.atomic_check	= sun8i_ui_layer_atomic_check,
+-	.atomic_disable	= sun8i_ui_layer_atomic_disable,
+ 	.atomic_update	= sun8i_ui_layer_atomic_update,
+ };
+ 
+@@ -390,6 +320,7 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 
+ 	drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs);
+ 	layer->mixer = mixer;
++	layer->type = SUN8I_LAYER_TYPE_UI;
+ 	layer->channel = channel;
+ 	layer->overlay = 0;
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index 0c0f1ac80517..9c09d9c08496 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -18,55 +18,6 @@
+ #include "sun8i_vi_layer.h"
+ #include "sun8i_vi_scaler.h"
+ 
+-static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
+-				  int overlay, bool enable, unsigned int zpos,
+-				  unsigned int old_zpos)
+-{
+-	u32 val, bld_base, ch_base;
+-
+-	bld_base = sun8i_blender_base(mixer);
+-	ch_base = sun8i_channel_base(mixer, channel);
+-
+-	DRM_DEBUG_DRIVER("%sabling VI channel %d overlay %d\n",
+-			 enable ? "En" : "Dis", channel, overlay);
+-
+-	if (enable)
+-		val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
+-	else
+-		val = 0;
+-
+-	regmap_update_bits(mixer->engine.regs,
+-			   SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
+-			   SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
+-
+-	if (!enable || zpos != old_zpos) {
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+-				   SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
+-				   0);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+-				   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
+-				   0);
+-	}
+-
+-	if (enable) {
+-		val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+-				   val, val);
+-
+-		val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+-				   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
+-				   val);
+-	}
+-}
+-
+ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
+ 					int overlay, struct drm_plane *plane)
+ {
+@@ -393,36 +344,17 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
+ 						   true, true);
+ }
+ 
+-static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane,
+-					  struct drm_atomic_state *state)
+-{
+-	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+-									   plane);
+-	struct sun8i_layer *layer = plane_to_sun8i_vi_layer(plane);
+-	unsigned int old_zpos = old_state->normalized_zpos;
+-	struct sun8i_mixer *mixer = layer->mixer;
+-
+-	sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
+-			      old_zpos);
+-}
+-
+ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
+ 					 struct drm_atomic_state *state)
+ {
+-	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+-									   plane);
+ 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ 									   plane);
+ 	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int zpos = new_state->normalized_zpos;
+-	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+ 
+-	if (!new_state->visible) {
+-		sun8i_vi_layer_enable(mixer, layer->channel,
+-				      layer->overlay, false, 0, old_zpos);
++	if (!new_state->crtc || !new_state->visible)
+ 		return;
+-	}
+ 
+ 	sun8i_vi_layer_update_coord(mixer, layer->channel,
+ 				    layer->overlay, plane, zpos);
+@@ -432,13 +364,10 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
+ 				      layer->overlay, plane);
+ 	sun8i_vi_layer_update_buffer(mixer, layer->channel,
+ 				     layer->overlay, plane);
+-	sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay,
+-			      true, zpos, old_zpos);
+ }
+ 
+ static const struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
+ 	.atomic_check	= sun8i_vi_layer_atomic_check,
+-	.atomic_disable	= sun8i_vi_layer_atomic_disable,
+ 	.atomic_update	= sun8i_vi_layer_atomic_update,
+ };
+ 
+@@ -613,6 +542,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 
+ 	drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
+ 	layer->mixer = mixer;
++	layer->type = SUN8I_LAYER_TYPE_VI;
+ 	layer->channel = index;
+ 	layer->overlay = 0;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Implement-gamma-correction.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Implement-gamma-correction.patch
new file mode 100644
index 000000000000..5b9b8f7bddd2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Implement-gamma-correction.patch
@@ -0,0 +1,131 @@
+From 10ae03375dff024f625fb9e29882d9787804e3ad Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Wed, 13 Mar 2019 19:50:17 -0700
+Subject: drm/sun4i: Implement gamma correction
+
+Add support for gamma corretion to sun4i TCON driver. Its LUT has 256
+entries and can be updated only when gamma correction is disabled.
+
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+---
+ drivers/gpu/drm/sun4i/sun4i_crtc.c | 14 +++++++++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 33 ++++++++++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.h | 12 ++++++++++-
+ 3 files changed, 58 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c
+index 18e74047b0f5..a09944a49e89 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
++++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
+@@ -103,6 +103,20 @@ static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc,
+ 			drm_crtc_send_vblank_event(crtc, event);
+ 		spin_unlock_irq(&crtc->dev->event_lock);
+ 	}
++
++	if (crtc->state->color_mgmt_changed) {
++		if (crtc->state->gamma_lut) {
++			/* LUT can be only updated when gamma correction is
++			 * disabled
++			 */
++			sun4i_tcon_enable_gamma(scrtc->tcon, false);
++			sun4i_tcon_load_gamma_lut(scrtc->tcon,
++						  crtc->state->gamma_lut->data);
++			sun4i_tcon_enable_gamma(scrtc->tcon, true);
++		} else
++			sun4i_tcon_enable_gamma(scrtc->tcon, false);
++	}
++
+ }
+ 
+ static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc,
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index b78799dedf62..84f1914afec5 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -240,6 +240,34 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
+ }
+ EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
+ 
++void sun4i_tcon_load_gamma_lut(struct sun4i_tcon *tcon,
++			       struct drm_color_lut *lut)
++{
++	int i;
++
++	for (i = 0; i < SUN4I_TCON_GAMMA_LUT_SIZE; i++) {
++		u32 r, g, b;
++
++		r = drm_color_lut_extract(lut[i].red, 8);
++		g = drm_color_lut_extract(lut[i].green, 8);
++		b = drm_color_lut_extract(lut[i].blue, 8);
++
++		regmap_write(tcon->regs, SUN4I_TCON_GAMMA_TABLE_REG + 4 * i,
++			     SUN4I_TCON_GAMMA_TABLE_R(r) |
++			     SUN4I_TCON_GAMMA_TABLE_G(g) |
++			     SUN4I_TCON_GAMMA_TABLE_B(b));
++	}
++}
++EXPORT_SYMBOL(sun4i_tcon_load_gamma_lut);
++
++void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable)
++{
++	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
++			   SUN4I_TCON_GCTL_GAMMA_ENABLE,
++			   enable ? SUN4I_TCON_GCTL_GAMMA_ENABLE : 0);
++}
++EXPORT_SYMBOL(sun4i_tcon_enable_gamma);
++
+ /*
+  * This function is a helper for TCON output muxing. The TCON output
+  * muxing control register in earlier SoCs (without the TCON TOP block)
+@@ -1288,6 +1316,11 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 
+ 	list_add_tail(&tcon->list, &drv->tcon_list);
+ 
++	drm_mode_crtc_set_gamma_size(&tcon->crtc->crtc,
++				     SUN4I_TCON_GAMMA_LUT_SIZE);
++	drm_crtc_enable_color_mgmt(&tcon->crtc->crtc, 0, false,
++				   tcon->crtc->crtc.gamma_size);
++
+ 	return 0;
+ 
+ err_free_dclk:
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index fa23aa23fe4a..97df39db2a31 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -19,6 +19,7 @@
+ 
+ #define SUN4I_TCON_GCTL_REG			0x0
+ #define SUN4I_TCON_GCTL_TCON_ENABLE			BIT(31)
++#define SUN4I_TCON_GCTL_GAMMA_ENABLE			BIT(30)
+ #define SUN4I_TCON_GCTL_IOMAP_MASK			BIT(0)
+ #define SUN4I_TCON_GCTL_IOMAP_TCON1			(1 << 0)
+ #define SUN4I_TCON_GCTL_IOMAP_TCON0			(0 << 0)
+@@ -229,7 +230,13 @@
+ #define SUN4I_TCON1_FILL_BEG2_REG		0x31c
+ #define SUN4I_TCON1_FILL_END2_REG		0x320
+ #define SUN4I_TCON1_FILL_DATA2_REG		0x324
+-#define SUN4I_TCON1_GAMMA_TABLE_REG		0x400
++
++#define SUN4I_TCON_GAMMA_TABLE_REG		0x400
++#define SUN4I_TCON_GAMMA_TABLE_B(x)		((x) & 0xff)
++#define SUN4I_TCON_GAMMA_TABLE_G(x)		(((x) & 0xff) << 8)
++#define SUN4I_TCON_GAMMA_TABLE_R(x)		(((x) & 0xff) << 16)
++
++#define SUN4I_TCON_GAMMA_LUT_SIZE		256
+ 
+ #define SUN4I_TCON_MAX_CHANNELS		2
+ 
+@@ -297,6 +304,9 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
+ 			 const struct drm_display_mode *mode);
+ void sun4i_tcon_set_status(struct sun4i_tcon *crtc,
+ 			   const struct drm_encoder *encoder, bool enable);
++void sun4i_tcon_load_gamma_lut(struct sun4i_tcon *tcon,
++			       struct drm_color_lut *lut);
++void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable);
+ 
+ extern const struct of_device_id sun4i_tcon_of_table[];
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
new file mode 100644
index 000000000000..64db580f8975
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
@@ -0,0 +1,73 @@
+From b0621d0df8f1c66974431cadcd42fbacc6365429 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 31 Oct 2022 03:23:11 +0100
+Subject: drm/sun4i: Mark one of the UI planes as a cursor one
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c    | 7 ++++++-
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 7 ++-----
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 4 +++-
+ 3 files changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 542c86f66b3a..15fe48794983 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -347,8 +347,13 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
+ 
+ 	for (i = 0; i < mixer->cfg->ui_num; i++) {
+ 		struct sun8i_layer *layer;
++		enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
++		if (i == 0)
++			type = DRM_PLANE_TYPE_PRIMARY;
++		else if (i == (mixer->cfg->ui_num - 1))
++			type = DRM_PLANE_TYPE_CURSOR;
+ 
+-		layer = sun8i_ui_layer_init_one(drm, mixer, i);
++		layer = sun8i_ui_layer_init_one(drm, mixer, i, type);
+ 		if (IS_ERR(layer)) {
+ 			dev_err(drm->dev, "Couldn't initialize %s plane\n",
+ 				i ? "overlay" : "primary");
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index b90e5edef4e8..0349e8bdffd6 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -277,9 +277,9 @@ static const uint64_t sun8i_layer_modifiers[] = {
+ 
+ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 					    struct sun8i_mixer *mixer,
+-					    int index)
++					    int index,
++					    enum drm_plane_type type)
+ {
+-	enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
+ 	int channel = mixer->cfg->vi_num + index;
+ 	struct sun8i_layer *layer;
+ 	unsigned int plane_cnt;
+@@ -289,9 +289,6 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 	if (!layer)
+ 		return ERR_PTR(-ENOMEM);
+ 
+-	if (index == 0)
+-		type = DRM_PLANE_TYPE_PRIMARY;
+-
+ 	/* possible crtcs are set later */
+ 	ret = drm_universal_plane_init(drm, &layer->plane, 0,
+ 				       &sun8i_ui_layer_funcs,
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+index 83892f6ff211..d4530e9f64e0 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+@@ -51,5 +51,7 @@ struct sun8i_layer;
+ 
+ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 					    struct sun8i_mixer *mixer,
+-					    int index);
++					    int index,
++					    enum drm_plane_type type);
++
+ #endif /* _SUN8I_UI_LAYER_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
new file mode 100644
index 000000000000..b505dec6dddb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
@@ -0,0 +1,547 @@
+From febd4d8b65ec8d7b1950693d6906ee536d924571 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 30 Apr 2023 18:19:16 +0200
+Subject: drm/sun4i: Support taking over display pipeline state from p-boot
+
+For perfect, flickerless and fast boot.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c         |  4 +-
+ drivers/gpu/drm/drm_fbdev_generic.c           | 14 +++++
+ drivers/gpu/drm/panel/panel-sitronix-st7703.c | 17 ++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.c            | 23 ++++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.h            |  2 +
+ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c        | 13 +++++
+ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h        |  2 +
+ drivers/gpu/drm/sun4i/sun8i_mixer.c           | 52 +++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun8i_mixer.h           |  3 ++
+ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c   | 14 +++++
+ drivers/video/backlight/pwm_bl.c              | 25 ++++++++-
+ 11 files changed, 167 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index 399d68586274..95aea78a0fd6 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -980,7 +980,9 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	/* Decrease the PLL AUDIO bias current to reduce noise. */
+ 	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
+ 
+-	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
++	if (ret)
++		writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ 
+ 	/* Set PLL MIPI as parent for TCON0 */
+ 	val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
+diff --git a/drivers/gpu/drm/drm_fbdev_generic.c b/drivers/gpu/drm/drm_fbdev_generic.c
+index 1e200d815e1a..0debdf3dec8c 100644
+--- a/drivers/gpu/drm/drm_fbdev_generic.c
++++ b/drivers/gpu/drm/drm_fbdev_generic.c
+@@ -78,6 +78,7 @@ static int drm_fbdev_generic_helper_fb_probe(struct drm_fb_helper *fb_helper,
+ 	size_t screen_size;
+ 	void *screen_buffer;
+ 	u32 format;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	drm_dbg_kms(dev, "surface width(%d), height(%d) and bpp(%d)\n",
+@@ -125,6 +126,19 @@ static int drm_fbdev_generic_helper_fb_probe(struct drm_fb_helper *fb_helper,
+ 	if (ret)
+ 		goto err_drm_fb_helper_release_info;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		// copy framebuffer contents from p-boot if reasonable
++		if (screen_size != 720 * 1440 * 4) {
++			drm_err(dev, "surface width(%d), height(%d) and bpp(%d) does not match p-boot requirements\n",
++				    sizes->surface_width, sizes->surface_height,
++				    sizes->surface_bpp);
++			return 0;
++		}
++
++		memcpy(screen_buffer, __va(fb_start), screen_size);
++	}
++
+ 	return 0;
+ 
+ err_drm_fb_helper_release_info:
+diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+index 56d3a98e384b..22329bfdcacc 100644
+--- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+@@ -63,6 +63,7 @@ struct st7703 {
+ 	struct dentry *debugfs;
+ 	const struct st7703_panel_desc *desc;
+ 	enum drm_panel_orientation orientation;
++	bool hw_preenabled;
+ };
+ 
+ struct st7703_panel_desc {
+@@ -704,6 +705,11 @@ static int st7703_enable(struct drm_panel *panel)
+ 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ 	int ret;
+ 
++	if (ctx->hw_preenabled) {
++		ctx->hw_preenabled = false;
++		return 0;
++	}
++
+ 	ret = ctx->desc->init_sequence(ctx);
+ 	if (ret < 0) {
+ 		dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
+@@ -771,8 +777,10 @@ static int st7703_prepare(struct drm_panel *panel)
+ 	if (ctx->prepared)
+ 		return 0;
+ 
++	if (!ctx->hw_preenabled) {
+ 	dev_dbg(ctx->dev, "Resetting the panel\n");
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
++	}
+ 
+ 	ret = regulator_enable(ctx->iovcc);
+ 	if (ret < 0) {
+@@ -788,10 +796,12 @@ static int st7703_prepare(struct drm_panel *panel)
+ 	}
+ 
+ 	/* Give power supplies time to stabilize before deasserting reset. */
++	if (!ctx->hw_preenabled) {
+ 	usleep_range(10000, 20000);
+ 
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ 	usleep_range(15000, 20000);
++	}
+ 
+ 	ctx->prepared = true;
+ 
+@@ -884,12 +894,19 @@ static int st7703_probe(struct mipi_dsi_device *dsi)
+ {
+ 	struct device *dev = &dsi->dev;
+ 	struct st7703 *ctx;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+ 	if (!ctx)
+ 		return -ENOMEM;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		ctx->hw_preenabled = true;
++	}
++
+ 	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ 	if (IS_ERR(ctx->reset_gpio))
+ 		return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "Failed to get reset gpio\n");
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index 84f1914afec5..4a3ba9082b4c 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -40,6 +40,8 @@
+ #include "sun8i_tcon_top.h"
+ #include "sunxi_engine.h"
+ 
++static bool hw_preconfigured;
++
+ static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
+ {
+ 	struct drm_connector *connector;
+@@ -743,6 +745,13 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
+ 			 const struct drm_encoder *encoder,
+ 			 const struct drm_display_mode *mode)
+ {
++	if (tcon->hw_preconfigured) {
++		// avoid the first modeset
++		tcon->hw_preconfigured = false;
++		hw_preconfigured = false;
++		return;
++	}
++
+ 	switch (encoder->encoder_type) {
+ 	case DRM_MODE_ENCODER_DSI:
+ 		/* DSI is tied to special case of CPU interface */
+@@ -883,6 +892,7 @@ static int sun4i_tcon_init_regmap(struct device *dev,
+ 		return PTR_ERR(tcon->regs);
+ 	}
+ 
++	if (!tcon->hw_preconfigured) {
+ 	/* Make sure the TCON is disabled and all IRQs are off */
+ 	regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
+ 	regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
+@@ -891,6 +901,7 @@ static int sun4i_tcon_init_regmap(struct device *dev,
+ 	/* Disable IO lines and set them to tristate */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
+ 	regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
++	}
+ 
+ 	return 0;
+ }
+@@ -1162,6 +1173,9 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 	tcon->dev = dev;
+ 	tcon->id = engine->id;
+ 	tcon->quirks = of_device_get_match_data(dev);
++	
++	if (tcon->id == 0)
++		tcon->hw_preconfigured = hw_preconfigured;
+ 
+ 	tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
+ 	if (IS_ERR(tcon->lcd_rst)) {
+@@ -1183,12 +1197,14 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 		}
+ 	}
+ 
++	if (!tcon->hw_preconfigured) {
+ 	/* Make sure our TCON is reset */
+ 	ret = reset_control_reset(tcon->lcd_rst);
+ 	if (ret) {
+ 		dev_err(dev, "Couldn't deassert our reset line\n");
+ 		return ret;
+ 	}
++	}
+ 
+ 	if (tcon->quirks->supports_lvds) {
+ 		/*
+@@ -1352,8 +1368,15 @@ static int sun4i_tcon_probe(struct platform_device *pdev)
+ 	const struct sun4i_tcon_quirks *quirks;
+ 	struct drm_bridge *bridge;
+ 	struct drm_panel *panel;
++	u32 fb_start;
+ 	int ret;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		hw_preconfigured = true;
++	}
++
+ 	quirks = of_device_get_match_data(&pdev->dev);
+ 
+ 	/* panels and bridges are present only on TCONs with channel 0 */
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index 97df39db2a31..864d70b9d242 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -293,6 +293,8 @@ struct sun4i_tcon {
+ 
+ 	/* TCON list management */
+ 	struct list_head		list;
++
++	bool hw_preconfigured;
+ };
+ 
+ struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
+diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+index 4abf4f102007..62926a19388c 100644
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+@@ -732,6 +732,7 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	reset_control_deassert(dsi->reset);
+ 	clk_prepare_enable(dsi->mod_clk);
+ 
++	if (!dsi->hw_preconfigured) {
+ 	/*
+ 	 * Enable the DSI block.
+ 	 */
+@@ -758,6 +759,7 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	sun6i_dsi_setup_inst_loop(dsi, mode);
+ 	sun6i_dsi_setup_format(dsi, mode);
+ 	sun6i_dsi_setup_timings(dsi, mode);
++	}
+ 
+ 	phy_init(dsi->dphy);
+ 
+@@ -787,11 +789,15 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	if (dsi->panel)
+ 		drm_panel_enable(dsi->panel);
+ 
++	if (!dsi->hw_preconfigured) {
+ 	sun6i_dsi_start(dsi, DSI_START_HSC);
+ 
+ 	udelay(1000);
+ 
+ 	sun6i_dsi_start(dsi, DSI_START_HSD);
++	}
++
++	dsi->hw_preconfigured = false;
+ }
+ 
+ static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
+@@ -1105,6 +1111,7 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct sun6i_dsi *dsi;
+ 	void __iomem *base;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	variant = device_get_match_data(dev);
+@@ -1120,6 +1127,12 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
+ 	dsi->host.dev = dev;
+ 	dsi->variant = variant;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		dsi->hw_preconfigured = true;
++	}
++
+ 	base = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(base)) {
+ 		dev_err(dev, "Couldn't map the DSI encoder registers\n");
+diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+index f1ddefe0f554..958c2997ab43 100644
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+@@ -38,6 +38,8 @@ struct sun6i_dsi {
+ 	struct drm_panel	*panel;
+ 
+ 	const struct sun6i_dsi_variant *variant;
++	
++	bool hw_preconfigured;
+ };
+ 
+ static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 15fe48794983..eb55798c200d 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -24,6 +24,7 @@
+ #include <drm/drm_probe_helper.h>
+ 
+ #include "sun4i_drv.h"
++#include "sun4i_tcon.h"
+ #include "sun8i_mixer.h"
+ #include "sun8i_ui_layer.h"
+ #include "sun8i_vi_layer.h"
+@@ -34,6 +35,8 @@ struct de2_fmt_info {
+ 	u32	de2_fmt;
+ };
+ 
++static bool hw_preconfigured;
++
+ static const struct de2_fmt_info de2_formats[] = {
+ 	{
+ 		.drm_fmt = DRM_FORMAT_ARGB8888,
+@@ -278,6 +281,33 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 	struct drm_plane *plane;
+ 	u32 route = 0, pipe_en = 0;
+ 
++	if (mixer->hw_preconfigured && engine->id == 0) {
++		struct sun4i_tcon* tcon;
++		u32 val, saved, ret;
++
++		/*
++		 * This is the first commit, wait for vblank on tcon0 before continuing.
++		 */
++		list_for_each_entry(tcon, &mixer->drv->tcon_list, list) {
++			if (tcon->id == 0) {
++				regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &saved);
++				saved &= 0xffff0000;
++
++				regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
++
++				ret = regmap_read_poll_timeout(tcon->regs, SUN4I_TCON_GINT0_REG, val,
++							 val & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
++								SUN4I_TCON_GINT0_VBLANK_INT(1) |
++								SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT),
++							 100, 40000);
++
++				regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, saved);
++			}
++		}
++
++		mixer->hw_preconfigured = false;
++	}
++
+ 	DRM_DEBUG_DRIVER("Committing changes\n");
+ 
+ 	drm_for_each_plane(plane, state->dev) {
+@@ -459,6 +489,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	dev_set_drvdata(dev, mixer);
+ 	mixer->engine.ops = &sun8i_engine_ops;
+ 	mixer->engine.node = dev->of_node;
++	mixer->drv = drv;
+ 
+ 	if (of_property_present(dev->of_node, "iommus")) {
+ 		/*
+@@ -483,6 +514,11 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	 */
+ 	mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node);
+ 
++	if (mixer->engine.id == 0) {
++		mixer->hw_preconfigured = hw_preconfigured;
++		hw_preconfigured = false;
++	}
++
+ 	mixer->cfg = of_device_get_match_data(dev);
+ 	if (!mixer->cfg)
+ 		return -EINVAL;
+@@ -530,8 +566,11 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	 * reason for the mixer to be functional. Make sure it's the
+ 	 * case.
+ 	 */
++
++	if (!mixer->hw_preconfigured) {
+ 	if (mixer->cfg->mod_rate)
+ 		clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate);
++	}
+ 
+ 	clk_prepare_enable(mixer->mod_clk);
+ 
+@@ -539,6 +578,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 
+ 	base = sun8i_blender_base(mixer);
+ 
++	if (!mixer->hw_preconfigured) {
+ 	/* Reset registers and disable unused sub-engines */
+ 	if (mixer->cfg->is_de3) {
+ 		for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
+@@ -570,6 +610,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	/* Enable the mixer */
+ 	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
+ 		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
++	} /* hw_preconfigured */
+ 
+ 	/* Set background color to black */
+ 	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
+@@ -590,8 +631,10 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 			     SUN8I_MIXER_BLEND_MODE(base, i),
+ 			     SUN8I_MIXER_BLEND_MODE_DEF);
+ 
++	if (!mixer->hw_preconfigured) {
+ 	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+ 			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
++	}
+ 
+ 	return 0;
+ 
+@@ -621,6 +664,15 @@ static const struct component_ops sun8i_mixer_ops = {
+ 
+ static int sun8i_mixer_probe(struct platform_device *pdev)
+ {
++	int ret;
++	u32 fb_start;
++
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		hw_preconfigured = true;
++	}
++
+ 	return component_add(&pdev->dev, &sun8i_mixer_ops);
+ }
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index d7898c9c9cc0..68e2741b0962 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -184,6 +184,9 @@ struct sun8i_mixer {
+ 
+ 	struct clk			*bus_clk;
+ 	struct clk			*mod_clk;
++
++	struct sun4i_drv		*drv;
++	bool				hw_preconfigured;
+ };
+ 
+ enum {
+diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+index 36eab95271b2..a19a27cea860 100644
+--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
++++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+@@ -195,6 +195,8 @@ struct sun6i_dphy {
+ 
+ 	const struct sun6i_dphy_variant		*variant;
+ 	enum sun6i_dphy_direction		direction;
++
++	bool hw_preconfigured;
+ };
+ 
+ static int sun6i_dphy_init(struct phy *phy)
+@@ -226,6 +228,11 @@ static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
+ {
+ 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
+ 
++	if (dphy->hw_preconfigured) {
++		dphy->hw_preconfigured = false;
++		return;
++	}
++
+ 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
+ 		     SUN6I_DPHY_ANA0_REG_PWS |
+ 		     SUN6I_DPHY_ANA0_REG_DMPC |
+@@ -551,6 +558,7 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
+ 	struct sun6i_dphy *dphy;
+ 	const char *direction;
+ 	void __iomem *regs;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
+@@ -561,6 +569,12 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
+ 	if (!dphy->variant)
+ 		return -EINVAL;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		dphy->hw_preconfigured = true;
++	}
++
+ 	regs = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(regs)) {
+ 		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
+diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
+index 61d30bc98eea..c1195299a214 100644
+--- a/drivers/video/backlight/pwm_bl.c
++++ b/drivers/video/backlight/pwm_bl.c
+@@ -444,7 +444,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	struct backlight_properties props;
+ 	struct backlight_device *bl;
+ 	struct pwm_bl_data *pb;
+-	struct pwm_state state;
++	struct pwm_state state, state_real;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -509,6 +509,11 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	/* Sync up PWM state. */
+ 	pwm_init_state(pb->pwm, &state);
+ 
++	/* Read real state, but only if the PWM is enabled. */
++	pwm_get_state(pb->pwm, &state_real);
++	if (state_real.enabled)
++		state = state_real;
++
+ 	/*
+ 	 * The DT case will set the pwm_period_ns field to 0 and store the
+ 	 * period, parsed from the DT, in the PWM device. For the non-DT case,
+@@ -601,6 +606,24 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 
+ 	bl->props.brightness = data->dft_brightness;
+ 	bl->props.power = pwm_backlight_initial_power_state(pb);
++	if (bl->props.power == FB_BLANK_UNBLANK && pb->levels) {
++		u64 level;
++
++		/* If the backlight is already on, determine the default
++		 * brightness from PWM duty cycle instead of forcing
++		 * the brightness determined by the driver 
++		 */
++		pwm_get_state(pb->pwm, &state);
++		level = (u64)state.duty_cycle * pb->scale;
++		do_div(level, (u64)state.period);
++
++		for (i = 0; i <= data->max_brightness; i++) {
++			if (data->levels[i] > level) {
++				bl->props.brightness = i;
++				break;
++			}
++		}
++	}
+ 	backlight_update_status(bl);
+ 
+ 	platform_set_drvdata(pdev, bl);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Unify-sun8i_-_layer-structs.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Unify-sun8i_-_layer-structs.patch
new file mode 100644
index 000000000000..4d1b1c1b6f2e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-Unify-sun8i_-_layer-structs.patch
@@ -0,0 +1,236 @@
+From e078be62829c8bc09c6e31086f28d8f058e65d54 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 31 Oct 2022 03:19:07 +0100
+Subject: drm/sun4i: Unify sun8i_*_layer structs
+
+These structs are identical, use a single struct to represent private
+data for the DRM plane. This is a preparation for configuring layer
+routing from the CRTC (mixer) instead of current approach of setting
+up routing from individual layer's atomic_update callback.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c    |  4 ++--
+ drivers/gpu/drm/sun4i/sun8i_mixer.h    | 14 ++++++++++++++
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 14 +++++++-------
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 20 ++++----------------
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 14 +++++++-------
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 20 ++++----------------
+ 6 files changed, 38 insertions(+), 48 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 01382860aaee..1e681314e379 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -271,7 +271,7 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	for (i = 0; i < mixer->cfg->vi_num; i++) {
+-		struct sun8i_vi_layer *layer;
++		struct sun8i_layer *layer;
+ 
+ 		layer = sun8i_vi_layer_init_one(drm, mixer, i);
+ 		if (IS_ERR(layer)) {
+@@ -284,7 +284,7 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
+ 	}
+ 
+ 	for (i = 0; i < mixer->cfg->ui_num; i++) {
+-		struct sun8i_ui_layer *layer;
++		struct sun8i_layer *layer;
+ 
+ 		layer = sun8i_ui_layer_init_one(drm, mixer, i);
+ 		if (IS_ERR(layer)) {
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 85c94884fb9a..5a610ee30301 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -9,6 +9,7 @@
+ #include <linux/clk.h>
+ #include <linux/regmap.h>
+ #include <linux/reset.h>
++#include <drm/drm_plane.h>
+ 
+ #include "sunxi_engine.h"
+ 
+@@ -185,6 +186,19 @@ struct sun8i_mixer {
+ 	struct clk			*mod_clk;
+ };
+ 
++struct sun8i_layer {
++	struct drm_plane	plane;
++	struct sun8i_mixer	*mixer;
++	int			channel;
++	int			overlay;
++};
++
++static inline struct sun8i_layer *
++plane_to_sun8i_layer(struct drm_plane *plane)
++{
++	return container_of(plane, struct sun8i_layer, plane);
++}
++
+ static inline struct sun8i_mixer *
+ engine_to_sun8i_mixer(struct sunxi_engine *engine)
+ {
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index ca75ca0835a6..248fbb606ede 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -232,7 +232,7 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
+ {
+ 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
+ 										 plane);
+-	struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	struct drm_crtc *crtc = new_plane_state->crtc;
+ 	struct drm_crtc_state *crtc_state;
+ 	int min_scale, max_scale;
+@@ -264,7 +264,7 @@ static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane,
+ {
+ 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+ 									   plane);
+-	struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+ 
+@@ -279,7 +279,7 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
+ 									   plane);
+ 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ 									   plane);
+-	struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int zpos = new_state->normalized_zpos;
+ 	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+@@ -345,13 +345,13 @@ static const uint64_t sun8i_layer_modifiers[] = {
+ 	DRM_FORMAT_MOD_INVALID
+ };
+ 
+-struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+-					       struct sun8i_mixer *mixer,
+-					       int index)
++struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
++					    struct sun8i_mixer *mixer,
++					    int index)
+ {
+ 	enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
+ 	int channel = mixer->cfg->vi_num + index;
+-	struct sun8i_ui_layer *layer;
++	struct sun8i_layer *layer;
+ 	unsigned int plane_cnt;
+ 	int ret;
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+index e3e32ee1178d..83892f6ff211 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+@@ -47,21 +47,9 @@
+ #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_COMBINED	((2) << 1)
+ 
+ struct sun8i_mixer;
++struct sun8i_layer;
+ 
+-struct sun8i_ui_layer {
+-	struct drm_plane	plane;
+-	struct sun8i_mixer	*mixer;
+-	int			channel;
+-	int			overlay;
+-};
+-
+-static inline struct sun8i_ui_layer *
+-plane_to_sun8i_ui_layer(struct drm_plane *plane)
+-{
+-	return container_of(plane, struct sun8i_ui_layer, plane);
+-}
+-
+-struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+-					       struct sun8i_mixer *mixer,
+-					       int index);
++struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
++					    struct sun8i_mixer *mixer,
++					    int index);
+ #endif /* _SUN8I_UI_LAYER_H_ */
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index f9c0a56d3a14..0c0f1ac80517 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -366,7 +366,7 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
+ {
+ 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
+ 										 plane);
+-	struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	struct drm_crtc *crtc = new_plane_state->crtc;
+ 	struct drm_crtc_state *crtc_state;
+ 	int min_scale, max_scale;
+@@ -398,7 +398,7 @@ static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane,
+ {
+ 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+ 									   plane);
+-	struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_vi_layer(plane);
+ 	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+ 
+@@ -413,7 +413,7 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
+ 									   plane);
+ 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ 									   plane);
+-	struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int zpos = new_state->normalized_zpos;
+ 	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+@@ -539,14 +539,14 @@ static const uint64_t sun8i_layer_modifiers[] = {
+ 	DRM_FORMAT_MOD_INVALID
+ };
+ 
+-struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+-					       struct sun8i_mixer *mixer,
+-					       int index)
++struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
++					    struct sun8i_mixer *mixer,
++					    int index)
+ {
+ 	enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
+ 	u32 supported_encodings, supported_ranges;
+ 	unsigned int plane_cnt, format_count;
+-	struct sun8i_vi_layer *layer;
++	struct sun8i_layer *layer;
+ 	const u32 *formats;
+ 	int ret;
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
+index 48c399e1c86d..655440cdc78f 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
+@@ -52,21 +52,9 @@
+ #define SUN8I_MIXER_CHAN_VI_DS_M(x)			((x) << 0)
+ 
+ struct sun8i_mixer;
++struct sun8i_layer;
+ 
+-struct sun8i_vi_layer {
+-	struct drm_plane	plane;
+-	struct sun8i_mixer	*mixer;
+-	int			channel;
+-	int			overlay;
+-};
+-
+-static inline struct sun8i_vi_layer *
+-plane_to_sun8i_vi_layer(struct drm_plane *plane)
+-{
+-	return container_of(plane, struct sun8i_vi_layer, plane);
+-}
+-
+-struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+-					       struct sun8i_mixer *mixer,
+-					       int index);
++struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
++					    struct sun8i_mixer *mixer,
++					    int index);
+ #endif /* _SUN8I_VI_LAYER_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-drm-Change-update_bits-to-write.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-drm-Change-update_bits-to-write.patch
new file mode 100644
index 000000000000..0e0f7b6fc9d4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-drm-Change-update_bits-to-write.patch
@@ -0,0 +1,42 @@
+From ad60fcfd615a12f24ae12e34bf4598a4d8307fac Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 24 Feb 2024 14:36:36 +0100
+Subject: drm: sun4i-drm: Change update_bits to write
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 +++---------------
+ 1 file changed, 3 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 86a38a2f00a7..542c86f66b3a 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -311,21 +311,9 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 		pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
+ 	}
+ 
+-	regmap_update_bits(mixer->engine.regs,
+-			   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+-			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(0) |
+-			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(1) |
+-			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(2) |
+-			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(3),
+-			   route);
+-
+-	regmap_update_bits(mixer->engine.regs,
+-			   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(0) |
+-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(1) |
+-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(2) |
+-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(3),
+-			   pipe_en);
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route);
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
++		     pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
+ 
+ 	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
+ 		     SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
new file mode 100644
index 000000000000..186fbad7d044
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
@@ -0,0 +1,179 @@
+From 2d14664c492e6c5537f62d6db1add8b7f47614cc Mon Sep 17 00:00:00 2001
+From: Frank Oltmanns <frank@oltmanns.dev>
+Date: Sun, 10 Mar 2024 14:32:29 +0100
+Subject: drm/sun4i: tcon: Support keeping dclk rate upon ancestor clock
+ changes
+
+Allow the dclk to reset its rate when a rate change is initiated from an
+ancestor clock. This makes it possible to no longer to get an exclusive
+lock. As a consequence, it is now possible to set new rates if
+necessary, e.g. when an external display is connected.
+
+The first user of this functionality is the A64 because PLL-VIDEO0 is an
+ancestor for both HDMI and TCON0. This allows to select an optimal rate
+for TCON0 as long as there is no external HDMI connection. Once a change
+in PLL-VIDEO0 is performed when an HDMI connection is established, TCON0
+can react gracefully and select an optimal rate based on this the new
+constraint.
+
+Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
+---
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 70 +++++++++++++++++++++++++++---
+ drivers/gpu/drm/sun4i/sun4i_tcon.h | 12 +++++
+ 2 files changed, 76 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index 4a3ba9082b4c..654df088f2de 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -110,9 +110,11 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
+ 
+ 	if (enabled) {
+ 		clk_prepare_enable(clk);
+-		clk_rate_exclusive_get(clk);
++		if (!tcon->quirks->restores_rate)
++			clk_rate_exclusive_get(clk);
+ 	} else {
+-		clk_rate_exclusive_put(clk);
++		if (!tcon->quirks->restores_rate)
++			clk_rate_exclusive_put(clk);
+ 		clk_disable_unprepare(clk);
+ 	}
+ }
+@@ -373,6 +375,53 @@ static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
+ 	regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
+ }
+ 
++static void sun4i_rate_reset_notifier_delayed_update(struct work_struct *work)
++{
++	struct sun4i_rate_reset_nb *rate_reset = container_of(work, struct sun4i_rate_reset_nb,
++							    reset_rate_work.work);
++
++	clk_set_rate(rate_reset->target_clk, rate_reset->saved_rate);
++}
++
++static int sun4i_rate_reset_notifier_cb(struct notifier_block *nb,
++				      unsigned long event, void *data)
++{
++	struct sun4i_rate_reset_nb *rate_reset = to_sun4i_rate_reset_nb(nb);
++
++	if (event == POST_RATE_CHANGE)
++		mod_delayed_work(system_wq, &rate_reset->reset_rate_work, msecs_to_jiffies(100));
++
++	return NOTIFY_DONE;
++}
++
++static void sun4i_rate_reset_notifier_register(struct sun4i_rate_reset_nb *rate_reset_nb)
++{
++	if (rate_reset_nb->is_registered)
++		return;
++
++	rate_reset_nb->clk_nb.notifier_call = sun4i_rate_reset_notifier_cb;
++
++	INIT_DELAYED_WORK(&rate_reset_nb->reset_rate_work,
++			  sun4i_rate_reset_notifier_delayed_update);
++
++	if (!clk_notifier_register(rate_reset_nb->target_clk,
++				   &rate_reset_nb->clk_nb))
++		rate_reset_nb->is_registered = true;
++}
++
++static struct sun4i_rate_reset_nb tcon_rate_reset_tcon0_nb;
++
++static void sun4i_tcon0_set_dclk_rate(struct sun4i_tcon *tcon, unsigned long rate)
++{
++	clk_set_rate(tcon->dclk, rate);
++
++	if (tcon->quirks->restores_rate) {
++		tcon_rate_reset_tcon0_nb.target_clk = tcon->dclk;
++		tcon_rate_reset_tcon0_nb.saved_rate = rate;
++		sun4i_rate_reset_notifier_register(&tcon_rate_reset_tcon0_nb);
++	}
++}
++
+ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
+ 				     const struct drm_encoder *encoder,
+ 				     const struct drm_display_mode *mode)
+@@ -390,8 +439,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
+ 	 */
+ 	tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
+ 	tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
+-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes)
+-						  / SUN6I_DSI_TCON_DIV);
++	sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000 * (bpp / lanes)
++				  / SUN6I_DSI_TCON_DIV);
+ 
+ 	/* Set the resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+@@ -464,7 +513,7 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
+ 
+ 	tcon->dclk_min_div = 7;
+ 	tcon->dclk_max_div = 7;
+-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
++	sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000);
+ 
+ 	/* Set the resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+@@ -548,7 +597,7 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
+ 
+ 	tcon->dclk_min_div = tcon->quirks->dclk_min_div;
+ 	tcon->dclk_max_div = 127;
+-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
++	sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000);
+ 
+ 	/* Set the resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+@@ -1561,6 +1610,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
+ 	.supports_lvds		= true,
+ };
+ 
++static const struct sun4i_tcon_quirks sun50i_a64_lcd_quirks = {
++	.supports_lvds		= true,
++	.has_channel_0		= true,
++	.restores_rate		= true,
++	.dclk_min_div		= 1,
++	.setup_lvds_phy		= sun6i_tcon_setup_lvds_phy,
++};
++
+ static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
+ 	.supports_lvds		= true,
+ 	.has_channel_0		= true,
+@@ -1619,6 +1676,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
+ 	{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
+ 	{ .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
+ 	{ .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
++	{ .compatible = "allwinner,sun50i-a64-tcon-lcd", .data = &sun50i_a64_lcd_quirks },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index 864d70b9d242..729d64b78846 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -250,6 +250,7 @@ struct sun4i_tcon_quirks {
+ 	bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
+ 	bool	supports_lvds;   /* Does the TCON support an LVDS output? */
+ 	bool	polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
++	bool	restores_rate;   /* restores the initial rate when rate changes */
+ 	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */
+ 
+ 	/* callback to handle tcon muxing options */
+@@ -312,4 +313,15 @@ void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable);
+ 
+ extern const struct of_device_id sun4i_tcon_of_table[];
+ 
++struct sun4i_rate_reset_nb {
++	struct notifier_block	clk_nb;
++	struct delayed_work	reset_rate_work;
++
++	struct clk		*target_clk;
++	unsigned long		saved_rate;
++	bool			is_registered;
++};
++
++#define to_sun4i_rate_reset_nb(_nb) container_of(_nb, struct sun4i_rate_reset_nb, clk_nb)
++
+ #endif /* __SUN4I_TCON_H__ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
new file mode 100644
index 000000000000..40999cc91de1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
@@ -0,0 +1,34 @@
+From 60a1c8380c6b5cf61b849f8fa1f1b6e676473f4b Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Tue, 10 Sep 2019 12:02:23 +0800
+Subject: dt-bindings: axp20x-adc: allow to use TS pin as GPADC
+
+The AXP series PMICs allow to use the TS pin as GPADC rather than the
+battery temperature sensor.
+
+Add the property to enable this mode.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ .../devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml     | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
+index d40689f233f2..74f051a86927 100644
+--- a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
++++ b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
+@@ -61,6 +61,11 @@ properties:
+   "#io-channel-cells":
+     const: 1
+ 
++  x-powers,ts-as-gpadc:
++    description: |
++      Boolean. Defines whether the TS pin should be used
++      as GPADC rather than battery temperature sensor pin.
++
+ additionalProperties: false
+ 
+ examples:
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
new file mode 100644
index 000000000000..3cbae6fdb9c1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
@@ -0,0 +1,35 @@
+From 86c627db56ca6148b491c55d3a8d3b52da9be921 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 00:00:00 +0100
+Subject: dt-bindings: input: gpio-vibrator: Don't require enable-gpios
+
+It is possible to turn the motor on/off just by enabling/disabling
+the vcc-supply. Change the binding to require either enable-gpios
+or vcc-supply or both.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ Documentation/devicetree/bindings/input/gpio-vibrator.yaml | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
+index 2384465eaa19..082ac06471db 100644
+--- a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
++++ b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
+@@ -24,7 +24,12 @@ properties:
+ 
+ required:
+   - compatible
+-  - enable-gpios
++
++anyOf:
++  - required:
++    - enable-gpios
++  - required:
++    - vcc-supply
+ 
+ additionalProperties: false
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
new file mode 100644
index 000000000000..3d7420411ce0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
@@ -0,0 +1,46 @@
+From e261276012a3c3a902a0e7d8bf7b2aa1b7f2ded3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 13:40:15 +0100
+Subject: dt-bindings: leds: Add a binding for AXP813 charger led
+
+The AXP813 PMIC can control one LED. Add binding to represent the LED.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../devicetree/bindings/leds/leds-axp20x.yaml | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/leds/leds-axp20x.yaml
+
+diff --git a/Documentation/devicetree/bindings/leds/leds-axp20x.yaml b/Documentation/devicetree/bindings/leds/leds-axp20x.yaml
+new file mode 100644
+index 000000000000..110edae82204
+--- /dev/null
++++ b/Documentation/devicetree/bindings/leds/leds-axp20x.yaml
+@@ -0,0 +1,24 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/leds/leds-axp20x.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: LED driver for AXP813 PMIC from X-Powers.
++
++maintainers:
++  - Ondrej Jirman <megi@xff.cz>
++
++description: |
++  This module is part of the AXP20x MFD device. For more details
++  see Documentation/devicetree/bindings/mfd/axp20x.txt.
++
++  The LED controller is represented as a sub-node of the PMIC node on
++  the device tree.
++
++properties:
++  compatible:
++    const: x-powers,axp813-charger-led
++
++required:
++  - compatible
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
new file mode 100644
index 000000000000..1cae55fdb25d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
@@ -0,0 +1,71 @@
+From d43b99afd70b06b3f0e6f41711b4ec221adaed05 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 30 Sep 2017 02:30:39 +0200
+Subject: dt-bindings: media: Add bindings for Himax HM5065 camera sensor
+
+HM5065 is 5MP CMOS sensor...
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../devicetree/bindings/media/i2c/hm5065.txt  | 49 +++++++++++++++++++
+ 1 file changed, 49 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/media/i2c/hm5065.txt
+
+diff --git a/Documentation/devicetree/bindings/media/i2c/hm5065.txt b/Documentation/devicetree/bindings/media/i2c/hm5065.txt
+new file mode 100644
+index 000000000000..92ba6cac0d2f
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/i2c/hm5065.txt
+@@ -0,0 +1,49 @@
++* Himax HM5065 CSI camera sensor
++
++Required Properties:
++- compatible: should be "himax,hm5065"
++- reg: I2C device address (0x1f)
++- clocks: reference to the external input clock for the sensor.
++- clock-names: should be "xclk".
++- IOVDD-supply: Digital I/O voltage supply, 2.8 volts
++- AVDD-supply: Analog voltage supply, 2.8 volts
++- DVDD-supply: Digital core voltage supply, 1.8 volts
++- AFVDD-supply: Auto focus voltage supply, 2.8 volts
++
++Optional Properties (one or both must be configured):
++- reset-gpios: reference to the GPIO connected to the reset pin, if any.
++	       This is an active low signal to the HM5065.
++- enable-gpios: reference to the GPIO connected to the CE pin,
++		if any. This is an active high signal to the HM5065.
++
++The device node must contain one 'port' child node for its digital output
++video port, in accordance with the video interface bindings defined in
++Documentation/devicetree/bindings/media/video-interfaces.txt.
++
++Example:
++
++&i2c1 {
++	hm5065: camera@1f {
++		compatible = "himax,hm5065";
++		reg = <0x1f>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		AFVDD-supply = <&reg_dldo3>;
++		reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
++		enable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
++
++		port {
++			hm5065_ep: endpoint {
++				remote-endpoint = <&csi0_hm5065_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
new file mode 100644
index 000000000000..27b819053231
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
@@ -0,0 +1,84 @@
+From ef0e890e77af1c86c744661d8d193f36f04925e9 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 17 Feb 2024 02:01:49 +0100
+Subject: dt: bindings: mfd: Add codec related properties to AC100 PMIC
+
+This PMIC includes a co-packaged audio codec with analog and digital
+parts. Add additional properties that describe power supplies to
+the codec, and the node for analog part of the codec.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../bindings/mfd/x-powers,ac100.yaml          | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml b/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
+index f3d8394b27e7..59ad898fbf85 100644
+--- a/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
++++ b/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
+@@ -34,11 +34,39 @@ properties:
+         description: >
+           Name of the 4M_adda clock exposed by the codec
+ 
++      "#sound-dai-cells":
++        const: 1
++
++      LDOIN-supply: true
++      AVCC-supply: true
++      VDDIO1-supply: true
++      VDDIO2-supply: true
++
+     required:
+       - "#clock-cells"
+       - compatible
+       - interrupts
+       - clock-output-names
++      - "#sound-dai-cells"
++      - LDOIN-supply
++      - AVCC-supply
++      - VDDIO1-supply
++      - VDDIO2-supply
++
++    additionalProperties: false
++
++  codec-analog:
++    type: object
++
++    properties:
++      compatible:
++        const: x-powers,ac100-codec-analog
++
++      CPVDD-supply: true
++
++    required:
++      - compatible
++      - CPVDD-supply
+ 
+     additionalProperties: false
+ 
+@@ -94,12 +122,22 @@ examples:
+             compatible = "x-powers,ac100";
+             reg = <0xe89>;
+ 
++            ac100_codec_analog: codec-analog {
++                compatible = "x-powers,ac100-codec-analog";
++                CPVDD-supply = <&reg_aldo2>;
++            };
++
+             ac100_codec: codec {
++                #sound-dai-cells = <1>;
+                 compatible = "x-powers,ac100-codec";
+                 interrupt-parent = <&r_pio>;
+                 interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */
+                 #clock-cells = <0>;
+                 clock-output-names = "4M_adda";
++                LDOIN-supply = <&reg_aldo2>;
++                AVCC-supply = <&reg_aldo3>;
++                VDDIO1-supply = <&reg_dcdc1>;
++                VDDIO2-supply = <&reg_dldo1>;
+             };
+ 
+             ac100_rtc: rtc {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
new file mode 100644
index 000000000000..76874f942418
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
@@ -0,0 +1,36 @@
+From c62247a0608ea66f181414ec0c826dc564c60eb8 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 23 Feb 2024 00:47:12 +0100
+Subject: dt-bindings: sound: Add jack-type property to sun8i-a33-codec
+
+The codec driver needs to know what jack connector is connected to
+on the board. Add proprty to describe the type of connector.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../bindings/sound/allwinner,sun8i-a33-codec.yaml        | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml
+index 63eadc4200ac..399fc00ad3f4 100644
+--- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml
++++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml
+@@ -44,6 +44,15 @@ properties:
+       - const: bus
+       - const: mod
+ 
++  jack-type:
++    enum:
++      - headset
++      - headphone
++    description:
++      Type of jack connector connected to the codec. This can be either
++      a 3-pin headphone connector or 4-pin headset connector. If not
++      specified, jack detection is disabled.
++
+ required:
+   - "#sound-dai-cells"
+   - compatible
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
new file mode 100644
index 000000000000..8b5ac42f9c10
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
@@ -0,0 +1,127 @@
+From bec2740ef7f1a5c942d825ecb2e6a80d66e1468a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 5 Mar 2019 22:02:41 -0600
+Subject: firmware: arm_scpi: Support unidirectional mailbox channels
+
+Some mailbox controllers have only unidirectional channels, so we need a
+pair of them for each SCPI channel. If a mbox-names property is present,
+look for "rx" and "tx" mbox channels; otherwise, the existing behavior
+is preserved, and a single mbox channel is used for each SCPI channel.
+
+Note that since the mailbox framework only supports a single phandle
+with each name (mbox_request_channel_byname always returns the first
+one), this new mode only supports a single SCPI channel.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/firmware/arm_scpi.c | 58 +++++++++++++++++++++++++++++--------
+ 1 file changed, 46 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
+index 5f3a6422b02c..907b2d09da6a 100644
+--- a/drivers/firmware/arm_scpi.c
++++ b/drivers/firmware/arm_scpi.c
+@@ -237,7 +237,8 @@ struct scpi_xfer {
+ 
+ struct scpi_chan {
+ 	struct mbox_client cl;
+-	struct mbox_chan *chan;
++	struct mbox_chan *rx_chan;
++	struct mbox_chan *tx_chan;
+ 	void __iomem *tx_payload;
+ 	void __iomem *rx_payload;
+ 	struct list_head rx_pending;
+@@ -511,7 +512,7 @@ static int scpi_send_message(u8 idx, void *tx_buf, unsigned int tx_len,
+ 	msg->rx_len = rx_len;
+ 	reinit_completion(&msg->done);
+ 
+-	ret = mbox_send_message(scpi_chan->chan, msg);
++	ret = mbox_send_message(scpi_chan->tx_chan, msg);
+ 	if (ret < 0 || !rx_buf)
+ 		goto out;
+ 
+@@ -869,8 +870,13 @@ static void scpi_free_channels(void *data)
+ 	struct scpi_drvinfo *info = data;
+ 	int i;
+ 
+-	for (i = 0; i < info->num_chans; i++)
+-		mbox_free_channel(info->channels[i].chan);
++	for (i = 0; i < info->num_chans; i++) {
++		struct scpi_chan *pchan = &info->channels[i];
++
++		if (pchan->tx_chan != pchan->rx_chan)
++			mbox_free_channel(pchan->tx_chan);
++		mbox_free_channel(pchan->rx_chan);
++	}
+ }
+ 
+ static void scpi_remove(struct platform_device *pdev)
+@@ -920,6 +926,7 @@ static int scpi_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct device_node *np = dev->of_node;
+ 	struct scpi_drvinfo *scpi_drvinfo;
++	bool use_mbox_names = false;
+ 
+ 	scpi_drvinfo = devm_kzalloc(dev, sizeof(*scpi_drvinfo), GFP_KERNEL);
+ 	if (!scpi_drvinfo)
+@@ -932,6 +939,14 @@ static int scpi_probe(struct platform_device *pdev)
+ 		dev_err(dev, "no mboxes property in '%pOF'\n", np);
+ 		return -ENODEV;
+ 	}
++	if (of_get_property(dev->of_node, "mbox-names", NULL)) {
++		use_mbox_names = true;
++		if (count != 2) {
++			dev_err(dev, "need exactly 2 mboxes with mbox-names\n");
++			return -ENODEV;
++		}
++		count /= 2;
++	}
+ 
+ 	scpi_drvinfo->channels =
+ 		devm_kcalloc(dev, count, sizeof(struct scpi_chan), GFP_KERNEL);
+@@ -980,15 +995,34 @@ static int scpi_probe(struct platform_device *pdev)
+ 		mutex_init(&pchan->xfers_lock);
+ 
+ 		ret = scpi_alloc_xfer_list(dev, pchan);
+-		if (!ret) {
+-			pchan->chan = mbox_request_channel(cl, idx);
+-			if (!IS_ERR(pchan->chan))
+-				continue;
+-			ret = PTR_ERR(pchan->chan);
+-			if (ret != -EPROBE_DEFER)
+-				dev_err(dev, "failed to get channel%d err %d\n",
+-					idx, ret);
++		if (ret)
++			return ret;
++
++		if (use_mbox_names) {
++			pchan->rx_chan = mbox_request_channel_byname(cl, "rx");
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->rx_chan);
++				goto fail;
++			}
++			pchan->tx_chan = mbox_request_channel_byname(cl, "tx");
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->tx_chan);
++				goto fail;
++			}
++		} else {
++			pchan->rx_chan = mbox_request_channel(cl, idx);
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->rx_chan);
++				goto fail;
++			}
++			pchan->tx_chan = pchan->rx_chan;
+ 		}
++		continue;
++
++fail:
++		if (ret != -EPROBE_DEFER)
++			dev_err(dev, "failed to get channel%d err %d\n",
++				idx, ret);
+ 		return ret;
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
new file mode 100644
index 000000000000..dd90a19ff0a4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
@@ -0,0 +1,87 @@
+From 2c443f5d27ee63e21f599724fbd7901cfce54556 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 2 Nov 2019 15:14:10 +0100
+Subject: firmware: scpi: Add support for sending a SCPI_CMD_SET_SYS_PWR_STATE
+ msg
+
+This is NOT the right message to signal SCP we want to suspend the
+system, but we use it anyway, because we simply want to do a fixed
+function suspend sequence, instead of more complicated and granular
+cluster/cpu/system power management.
+
+Normally we'd signal system suspend by sending a CSS power state
+message. I guess that can be done later, if wanted.
+
+For now, Linux will kill all secondary CPU cores via MCPM, and SCP
+will kill the last CPU, and suspend the system.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/firmware/arm_scpi.c   | 10 ++++++++++
+ include/linux/scpi_protocol.h |  1 +
+ 2 files changed, 11 insertions(+)
+
+diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
+index 94a6b4e667de..5f3a6422b02c 100644
+--- a/drivers/firmware/arm_scpi.c
++++ b/drivers/firmware/arm_scpi.c
+@@ -187,6 +187,7 @@ enum scpi_drv_cmds {
+ 	CMD_SENSOR_VALUE,
+ 	CMD_SET_DEVICE_PWR_STATE,
+ 	CMD_GET_DEVICE_PWR_STATE,
++	CMD_SET_SYS_PWR_STATE,
+ 	CMD_MAX_COUNT,
+ };
+ 
+@@ -203,6 +204,7 @@ static int scpi_std_commands[CMD_MAX_COUNT] = {
+ 	SCPI_CMD_SENSOR_VALUE,
+ 	SCPI_CMD_SET_DEVICE_PWR_STATE,
+ 	SCPI_CMD_GET_DEVICE_PWR_STATE,
++	SCPI_CMD_SET_SYS_PWR_STATE,
+ };
+ 
+ static int scpi_legacy_commands[CMD_MAX_COUNT] = {
+@@ -218,6 +220,7 @@ static int scpi_legacy_commands[CMD_MAX_COUNT] = {
+ 	LEGACY_SCPI_CMD_SENSOR_VALUE,
+ 	-1, /* SET_DEVICE_PWR_STATE */
+ 	-1, /* GET_DEVICE_PWR_STATE */
++	LEGACY_SCPI_CMD_SYS_PWR_STATE,
+ };
+ 
+ struct scpi_xfer {
+@@ -782,6 +785,12 @@ static int scpi_device_set_power_state(u16 dev_id, u8 pstate)
+ 				 sizeof(dev_set), &stat, sizeof(stat));
+ }
+ 
++static int scpi_sys_set_power_state(u8 pstate)
++{
++	return scpi_send_message(CMD_SET_SYS_PWR_STATE, &pstate,
++				 sizeof(pstate), NULL, 0);
++}
++
+ static struct scpi_ops scpi_ops = {
+ 	.get_version = scpi_get_version,
+ 	.clk_get_range = scpi_clk_get_range,
+@@ -798,6 +807,7 @@ static struct scpi_ops scpi_ops = {
+ 	.sensor_get_value = scpi_sensor_get_value,
+ 	.device_get_power_state = scpi_device_get_power_state,
+ 	.device_set_power_state = scpi_device_set_power_state,
++	.sys_set_power_state = scpi_sys_set_power_state,
+ };
+ 
+ struct scpi_ops *get_scpi_ops(void)
+diff --git a/include/linux/scpi_protocol.h b/include/linux/scpi_protocol.h
+index d2176a56828a..6169348c3b72 100644
+--- a/include/linux/scpi_protocol.h
++++ b/include/linux/scpi_protocol.h
+@@ -76,6 +76,7 @@ struct scpi_ops {
+ 	int (*sensor_get_value)(u16, u64 *);
+ 	int (*device_get_power_state)(u16);
+ 	int (*device_set_power_state)(u16, u8);
++	int (*sys_set_power_state)(u8);
+ };
+ 
+ #if IS_REACHABLE(CONFIG_ARM_SCPI_PROTOCOL)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
new file mode 100644
index 000000000000..2876cfa061a0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
@@ -0,0 +1,64 @@
+From c52fb69b8e18beacf0d79c82309140b1da66b109 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Oct 2019 05:08:35 +0200
+Subject: gnss: ubx: Send soft powerdown message on suspend
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gnss/ubx.c | 35 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+diff --git a/drivers/gnss/ubx.c b/drivers/gnss/ubx.c
+index 92402f6082c4..fd0ccb054477 100644
+--- a/drivers/gnss/ubx.c
++++ b/drivers/gnss/ubx.c
+@@ -33,11 +33,46 @@ static int ubx_set_active(struct gnss_serial *gserial)
+ 	return 0;
+ }
+ 
++// RXM-PMREQ
++static const u8 ubx_suspend_packet[] = {
++	0xb5, 0x62, // 'ub'
++	0x02, 0x41, // message class and id
++	0x08, 0x00, // message length
++	0x00, 0x00, 0x00, 0x00, // duration (0 == infinite)
++	0x02, 0x00, 0x00, 0x00, // flags (backup)
++	0x4d, 0x3b, // checksum
++};
++
+ static int ubx_set_standby(struct gnss_serial *gserial)
+ {
+ 	struct ubx_data *data = gnss_serial_get_drvdata(gserial);
+ 	int ret;
+ 
++#if 0
++	struct serdev_device *serdev = gserial->serdev;
++
++	// we can't know what state the device is in, so first make sure
++	// it's woken up by writing a zero byte to it and then suspend it
++	// for sure
++
++	ret = serdev_device_write(serdev, "", 1, MAX_SCHEDULE_TIMEOUT);
++	if (ret < 0)
++		return ret;
++
++	serdev_device_wait_until_sent(serdev, 0);
++
++	// wait for wakeup
++	mdelay(100);
++
++	ret = serdev_device_write(serdev, ubx_suspend_packet,
++				  sizeof(ubx_suspend_packet),
++				  MAX_SCHEDULE_TIMEOUT);
++	if (ret < 0 || ret < sizeof(ubx_suspend_packet))
++		return ret;
++
++	serdev_device_wait_until_sent(serdev, 0);
++#endif
++
+ 	ret = regulator_disable(data->vcc);
+ 	if (ret)
+ 		return ret;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/hm5065-yaml-bindings-wip.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/hm5065-yaml-bindings-wip.patch
new file mode 100644
index 000000000000..0a3c80a8669c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/hm5065-yaml-bindings-wip.patch
@@ -0,0 +1,109 @@
+From 33f34fe20cd8d887ea602af1842008c5eb1a6e83 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 20 May 2019 17:58:05 +0200
+Subject: hm5065: yaml bindings (wip)
+
+---
+ .../devicetree/bindings/media/i2c/hm5065.yaml | 90 +++++++++++++++++++
+ 1 file changed, 90 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/media/i2c/hm5065.yaml
+
+diff --git a/Documentation/devicetree/bindings/media/i2c/hm5065.yaml b/Documentation/devicetree/bindings/media/i2c/hm5065.yaml
+new file mode 100644
+index 000000000000..df7a4f514b3f
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/i2c/hm5065.yaml
+@@ -0,0 +1,90 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/media/i2c/hm5065.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Himax HM5065 CSI camera sensor
++
++description: |+
++  At least one of reset-gpios and enable-gpios must be configured.
++
++  The device node must contain one 'port' child node for its digital output
++  video port, in accordance with the video interface bindings defined in
++  
++  Documentation/devicetree/bindings/media/video-interfaces.txt.
++
++maintainers:
++  - Ondrej Jirman <megi@xff.cz>
++
++properties:
++  compatible:
++    const: himax,hm5065
++
++  reg:
++    maxItems: 1
++
++  reset-gpios:
++    maxItems: 1
++    description: reference to the GPIO connected to the reset pin, if any. This is an active low signal to the HM5065.
++
++  enable-gpios:
++    maxItems: 1
++    description: reference to the GPIO connected to the CE pin, if any. This is an active high signal to the HM5065.
++
++  IOVDD-supply:
++    description: Digital I/O voltage supply, 2.8 volts
++
++  AVDD-supply:
++    description: Analog voltage supply, 2.8 volts
++
++  DVDD-supply:
++    description: Digital core voltage supply, 1.8 volts
++
++  AFVDD-supply:
++    description: Auto focus voltage supply, 2.8 volts
++
++  clocks:
++    minItems: 1
++    maxItems: 1
++    description: reference to the external input clock for the sensor.
++
++- clock-names: should be "xclk".
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - IOVDD-supply
++  - AVDD-supply
++  - DVDD-supply
++  - AFVDD-supply
++
++Example:
++
++&i2c1 {
++	hm5065: camera@1f {
++		compatible = "himax,hm5065";
++		reg = <0x1f>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		AFVDD-supply = <&reg_dldo3>;
++		reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
++		enable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
++
++		port {
++			hm5065_ep: endpoint {
++				remote-endpoint = <&csi0_hm5065_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
new file mode 100644
index 000000000000..fc1d97d7f54a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
@@ -0,0 +1,35 @@
+From 64ea64d6c621e81ea22e54238f2a1370d4a50724 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 17 Jan 2021 23:19:52 +0100
+Subject: i2c: mv64xxx: Don't make a fuss when pinctrl recovery state is not
+ present
+
+Otherwise dmesg log presents a useless error.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/i2c/busses/i2c-mv64xxx.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
+index dc160cbc3155..df82deb65ecc 100644
+--- a/drivers/i2c/busses/i2c-mv64xxx.c
++++ b/drivers/i2c/busses/i2c-mv64xxx.c
+@@ -950,6 +950,14 @@ static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
+ 		return -ENODEV;
+ 	}
+ 
++	if (IS_ERR(pinctrl_lookup_state(rinfo->pinctrl, "gpio")) &&
++		IS_ERR(pinctrl_lookup_state(rinfo->pinctrl, "recovery"))) {
++		/* No recovery state is vailable in pinctrl. */
++		devm_pinctrl_put(rinfo->pinctrl);
++		rinfo->pinctrl = NULL;
++		return 0;
++	}
++
+ 	drv_data->adapter.bus_recovery_info = rinfo;
+ 	return 0;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
new file mode 100644
index 000000000000..0d3f58554772
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
@@ -0,0 +1,42 @@
+From c634a65277831993c6d03c70589620a48c97824a Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Tue, 10 Sep 2019 12:03:32 +0800
+Subject: iio: adc: axp20x_adc: allow to set TS pin to GPADC mode
+
+The TS pin of AXP PMICs can be set to GPADC mode. In this situation, it
+doesn't affect battery charging.
+
+Add the code to do the mode setting.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ drivers/iio/adc/axp20x_adc.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
+index d6c51b0f48e3..855cc7c809eb 100644
+--- a/drivers/iio/adc/axp20x_adc.c
++++ b/drivers/iio/adc/axp20x_adc.c
+@@ -40,6 +40,7 @@
+ #define AXP813_TS_GPIO0_ADC_RATE_HZ(x)		AXP20X_ADC_RATE_HZ(x)
+ #define AXP813_V_I_ADC_RATE_HZ(x)		((ilog2((x) / 100) << 4) & AXP813_V_I_ADC_RATE_MASK)
+ #define AXP813_ADC_RATE_HZ(x)			(AXP20X_ADC_RATE_HZ(x) | AXP813_V_I_ADC_RATE_HZ(x))
++#define AXP20X_TS_FUNCTION_GPADC		BIT(2)
+ 
+ #define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg)	\
+ 	{							\
+@@ -716,6 +717,11 @@ static int axp20x_probe(struct platform_device *pdev)
+ 				   info->data->adc_en2_mask,
+ 				   info->data->adc_en2_mask);
+ 
++	if (of_property_read_bool(pdev->dev.of_node, "x-powers,ts-as-gpadc"))
++		regmap_update_bits(info->regmap, AXP20X_ADC_RATE,
++				   AXP20X_TS_FUNCTION_GPADC,
++				   AXP20X_TS_FUNCTION_GPADC);
++
+ 	/* Configure ADCs rate */
+ 	info->data->adc_rate(info, 100);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch
new file mode 100644
index 000000000000..1005ad0e54a6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch
@@ -0,0 +1,61 @@
+From f95292ffc531452cbe48f34f4b0edaaf636324ca Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 7 Oct 2019 02:12:34 +0200
+Subject: iio: adc: sun4i-gpadc-iio: Allow to use sun5i-a13-gpadc-iio from DT
+
+We can now use allwinner,sun5i-a13-gpadc-iio to create a sub-node of
+allwinner,sun5i-a13-ts, that can be referenced by other drivers
+via IIO framework.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun5i.dtsi | 5 +++++
+ drivers/iio/adc/sun4i-gpadc-iio.c      | 3 ++-
+ drivers/mfd/sun4i-gpadc.c              | 1 +
+ 3 files changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i.dtsi b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+index d7c7b454a11a..e6836fd4b8dc 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+@@ -657,6 +657,11 @@ rtp: rtp@1c25000 {
+ 			reg = <0x01c25000 0x100>;
+ 			interrupts = <29>;
+ 			#thermal-sensor-cells = <0>;
++
++			rtp_adc: adc {
++				compatible = "allwinner,sun5i-a13-gpadc-iio";
++				#io-channel-cells = <1>;
++			};
+ 		};
+ 
+ 		uart0: serial@1c28000 {
+diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
+index 100ecced5fc1..10439952ae9d 100644
+--- a/drivers/iio/adc/sun4i-gpadc-iio.c
++++ b/drivers/iio/adc/sun4i-gpadc-iio.c
+@@ -621,7 +621,8 @@ static int sun4i_gpadc_probe(struct platform_device *pdev)
+ 	indio_dev->info = &sun4i_gpadc_iio_info;
+ 	indio_dev->modes = INDIO_DIRECT_MODE;
+ 
+-	if (pdev->dev.of_node)
++	if (pdev->dev.of_node && of_match_node(sun4i_gpadc_of_id,
++					       pdev->dev.of_node))
+ 		ret = sun4i_gpadc_probe_dt(pdev, indio_dev);
+ 	else
+ 		ret = sun4i_gpadc_probe_mfd(pdev, indio_dev);
+diff --git a/drivers/mfd/sun4i-gpadc.c b/drivers/mfd/sun4i-gpadc.c
+index 3029d48e982c..51da961cffd5 100644
+--- a/drivers/mfd/sun4i-gpadc.c
++++ b/drivers/mfd/sun4i-gpadc.c
+@@ -53,6 +53,7 @@ static struct mfd_cell sun4i_gpadc_cells[] = {
+ static struct mfd_cell sun5i_gpadc_cells[] = {
+ 	{
+ 		.name	= "sun5i-a13-gpadc-iio",
++		.of_compatible	= "allwinner,sun5i-a13-gpadc-iio",
+ 		.resources = adc_resources,
+ 		.num_resources = ARRAY_SIZE(adc_resources),
+ 	},
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
new file mode 100644
index 000000000000..e2cc0426d764
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
@@ -0,0 +1,39 @@
+From 5c7e18a1a1dc76ec86c5bdca46457fb950832e10 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 29 Oct 2022 23:12:49 +0200
+Subject: iio: st_sensors: Don't report error when the device is not present on
+ I2C bus
+
+On Pinephone, this is not an error, because there are two alternate
+magentometer configurations.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/iio/common/st_sensors/st_sensors_core.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/iio/common/st_sensors/st_sensors_core.c b/drivers/iio/common/st_sensors/st_sensors_core.c
+index c77d7bdcc121..f0612b5ea8e0 100644
+--- a/drivers/iio/common/st_sensors/st_sensors_core.c
++++ b/drivers/iio/common/st_sensors/st_sensors_core.c
+@@ -600,8 +600,16 @@ int st_sensors_verify_id(struct iio_dev *indio_dev)
+ 		err = regmap_read(sdata->regmap,
+ 				  sdata->sensor_settings->wai_addr, &wai);
+ 		if (err < 0) {
++			if (err == -ENXIO) {
++				dev_info(&indio_dev->dev,
++					 "%s is not present on the bus\n",
++					 indio_dev->name);
++				return err;
++			}
++
+ 			dev_err(&indio_dev->dev,
+-				"failed to read Who-Am-I register.\n");
++				"%s: failed to read Who-Am-I register (%d).\n",
++				indio_dev->name, err);
+ 			return err;
+ 		}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch
new file mode 100644
index 000000000000..8e07a13b94d8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch
@@ -0,0 +1,32 @@
+From 2eea1d5a5a96a2442055d0a3149525f4d124291d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 18:00:33 +0200
+Subject: input: cyttsp4: Clear the ids buffer in a saner way
+
+Fixes memory corruption / NPE failures during touch data
+acquisition.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 31fd75477322..c115cb449146 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -854,10 +854,9 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 	struct cyttsp4_sysinfo *si = cd->si;
+ 	struct cyttsp4_touch tch;
+ 	int i, j, t = 0;
+-	int ids[max(CY_TMA1036_MAX_TCH, CY_TMA4XX_MAX_TCH)];
++	int ids[CY_TMA4XX_MAX_TCH + 1] = {0};
+ 	struct cyttsp4_signal_def* sig;
+ 
+-	memset(ids, 0, si->si_ofs.tch_abs[CY_TCH_T].max * sizeof(int));
+ 	for (i = 0; i < num_cur_tch; i++) {
+ 		cyttsp4_get_touch(cd, &tch, si->xy_data +
+ 				  (i * si->si_ofs.tch_rec_size));
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch
new file mode 100644
index 000000000000..7aac37487f85
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch
@@ -0,0 +1,263 @@
+From 2b38134e7ca05938ac2d533bdf7a4590b23564a2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 16:01:06 +0200
+Subject: input: cyttsp4: De-obfuscate MT signals setup/platform data
+
+Original code does a lot of array math, and is needlessly complicated.
+Make it easier to use and clean it up.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 102 ++++++++++-------------
+ drivers/input/touchscreen/cyttsp4_core.h |  26 ------
+ include/linux/platform_data/cyttsp4.h    |  27 ++++--
+ 3 files changed, 66 insertions(+), 89 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 867c18abc89b..31fd75477322 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -853,31 +853,26 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 	struct device *dev = &cd->input->dev;
+ 	struct cyttsp4_sysinfo *si = cd->si;
+ 	struct cyttsp4_touch tch;
+-	int sig;
+ 	int i, j, t = 0;
+ 	int ids[max(CY_TMA1036_MAX_TCH, CY_TMA4XX_MAX_TCH)];
++	struct cyttsp4_signal_def* sig;
+ 
+ 	memset(ids, 0, si->si_ofs.tch_abs[CY_TCH_T].max * sizeof(int));
+ 	for (i = 0; i < num_cur_tch; i++) {
+ 		cyttsp4_get_touch(cd, &tch, si->xy_data +
+-			(i * si->si_ofs.tch_rec_size));
+-		if ((tch.abs[CY_TCH_T] < cd->pdata->frmwrk->abs
+-			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MIN_OST]) ||
+-			(tch.abs[CY_TCH_T] > cd->pdata->frmwrk->abs
+-			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MAX_OST])) {
++				  (i * si->si_ofs.tch_rec_size));
++
++		sig = &cd->pdata->signals[CY_ABS_ID_OST];
++		if (tch.abs[CY_TCH_T] < sig->min ||
++			tch.abs[CY_TCH_T] > sig->max) {
+ 			dev_err(dev, "%s: tch=%d -> bad trk_id=%d max_id=%d\n",
+-				__func__, i, tch.abs[CY_TCH_T],
+-				cd->pdata->frmwrk->abs[(CY_ABS_ID_OST *
+-				CY_NUM_ABS_SET) + CY_MAX_OST]);
++				__func__, i, tch.abs[CY_TCH_T], sig->max);
+ 			continue;
+ 		}
+ 
+ 		/* use 0 based track id's */
+-		sig = cd->pdata->frmwrk->abs
+-			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + 0];
+-		if (sig != CY_IGNORE_VALUE) {
+-			t = tch.abs[CY_TCH_T] - cd->pdata->frmwrk->abs
+-				[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MIN_OST];
++		if (sig->signal >= 0) {
++			t = tch.abs[CY_TCH_T] - sig->min;
+ 			if (tch.abs[CY_TCH_E] == CY_EV_LIFTOFF) {
+ 				dev_dbg(dev, "%s: t=%d e=%d lift-off\n",
+ 					__func__, t, tch.abs[CY_TCH_E]);
+@@ -885,18 +880,18 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 			}
+ 			input_mt_slot(cd->input, t);
+ 			input_mt_report_slot_state(cd->input, MT_TOOL_FINGER,
+-					true);
++						   true);
+ 			ids[t] = true;
+ 		}
+ 
+ 		/* all devices: position and pressure fields */
+ 		for (j = 0; j <= CY_ABS_W_OST; j++) {
+-			sig = cd->pdata->frmwrk->abs[((CY_ABS_X_OST + j) *
+-				CY_NUM_ABS_SET) + 0];
+-			if (sig != CY_IGNORE_VALUE)
+-				input_report_abs(cd->input, sig,
+-					tch.abs[CY_TCH_X + j]);
++			sig = &cd->pdata->signals[j];
++			if (sig->signal >= 0)
++				input_report_abs(cd->input, sig->signal,
++						 tch.abs[CY_TCH_X + j]);
+ 		}
++
+ 		if (si->si_ofs.tch_rec_size > CY_TMA1036_TCH_REC_SIZE) {
+ 			/*
+ 			 * TMA400 size and orientation fields:
+@@ -909,12 +904,10 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 
+ 			/* Get the extended touch fields */
+ 			for (j = 0; j < CY_NUM_EXT_TCH_FIELDS; j++) {
+-				sig = cd->pdata->frmwrk->abs
+-					[((CY_ABS_MAJ_OST + j) *
+-					CY_NUM_ABS_SET) + 0];
+-				if (sig != CY_IGNORE_VALUE)
+-					input_report_abs(cd->input, sig,
+-						tch.abs[CY_TCH_MAJ + j]);
++				sig = &cd->pdata->signals[CY_ABS_MAJ_OST + j];
++				if (sig->signal >= 0)
++					input_report_abs(cd->input, sig->signal,
++							 tch.abs[CY_TCH_MAJ + j]);
+ 			}
+ 		}
+ 
+@@ -1878,7 +1871,7 @@ static void cyttsp4_mt_close(struct input_dev *input)
+ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ {
+ 	struct device *dev = cd->dev;
+-	int signal = CY_IGNORE_VALUE;
++	struct cyttsp4_signal_def *signal;
+ 	int max_x, max_y, max_p, min, max;
+ 	int max_x_tmp, max_y_tmp;
+ 	int i;
+@@ -1903,37 +1896,30 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 	max_p = cd->si->si_ofs.max_p;
+ 
+ 	/* set event signal capabilities */
+-	for (i = 0; i < (cd->pdata->frmwrk->size / CY_NUM_ABS_SET); i++) {
+-		signal = cd->pdata->frmwrk->abs
+-			[(i * CY_NUM_ABS_SET) + CY_SIGNAL_OST];
+-		if (signal != CY_IGNORE_VALUE) {
+-			__set_bit(signal, cd->input->absbit);
+-			min = cd->pdata->frmwrk->abs
+-				[(i * CY_NUM_ABS_SET) + CY_MIN_OST];
+-			max = cd->pdata->frmwrk->abs
+-				[(i * CY_NUM_ABS_SET) + CY_MAX_OST];
+-			if (i == CY_ABS_ID_OST) {
+-				/* shift track ids down to start at 0 */
+-				max = max - min;
+-				min = min - min;
+-			} else if (i == CY_ABS_X_OST)
+-				max = max_x;
+-			else if (i == CY_ABS_Y_OST)
+-				max = max_y;
+-			else if (i == CY_ABS_P_OST)
+-				max = max_p;
+-			input_set_abs_params(cd->input, signal, min, max,
+-				cd->pdata->frmwrk->abs
+-				[(i * CY_NUM_ABS_SET) + CY_FUZZ_OST],
+-				cd->pdata->frmwrk->abs
+-				[(i * CY_NUM_ABS_SET) + CY_FLAT_OST]);
+-			dev_dbg(dev, "%s: register signal=%02X min=%d max=%d\n",
+-				__func__, signal, min, max);
+-			if ((i == CY_ABS_ID_OST) &&
+-				(cd->si->si_ofs.tch_rec_size <
+-				CY_TMA4XX_TCH_REC_SIZE))
+-				break;
+-		}
++	for (i = 0; i < cd->pdata->n_signals; i++) {
++		signal = &cd->pdata->signals[i];
++
++		__set_bit(signal->signal, cd->input->absbit);
++
++		max = signal->max;
++		min = signal->min;
++
++		if (signal->signal == ABS_MT_POSITION_X)
++			max = max_x;
++		else if (signal->signal == ABS_MT_POSITION_Y)
++			max = max_y;
++		else if (signal->signal == ABS_MT_PRESSURE)
++			max = max_p;
++
++		input_set_abs_params(cd->input, signal->signal, min, max,
++				     signal->fuzz, signal->flat);
++		dev_dbg(dev, "%s: register signal=%02X min=%d max=%d\n",
++			__func__, signal->signal, min, max);
++
++		if ((i == CY_ABS_ID_OST) &&
++			(cd->si->si_ofs.tch_rec_size <
++			CY_TMA4XX_TCH_REC_SIZE))
++			break;
+ 	}
+ 
+ 	input_mt_init_slots(cd->input, cd->si->si_ofs.tch_abs[CY_TCH_T].max,
+diff --git a/drivers/input/touchscreen/cyttsp4_core.h b/drivers/input/touchscreen/cyttsp4_core.h
+index 05fb30058d87..995bfd0a54d0 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.h
++++ b/drivers/input/touchscreen/cyttsp4_core.h
+@@ -357,32 +357,6 @@ enum cyttsp4_hst_mode_bits {
+ 	CY_HST_RESET       = (1 << 0),
+ };
+ 
+-/* abs settings */
+-#define CY_IGNORE_VALUE			0xFFFF
+-
+-/* abs signal capabilities offsets in the frameworks array */
+-enum cyttsp4_sig_caps {
+-	CY_SIGNAL_OST,
+-	CY_MIN_OST,
+-	CY_MAX_OST,
+-	CY_FUZZ_OST,
+-	CY_FLAT_OST,
+-	CY_NUM_ABS_SET	/* number of signal capability fields */
+-};
+-
+-/* abs axis signal offsets in the framworks array  */
+-enum cyttsp4_sig_ost {
+-	CY_ABS_X_OST,
+-	CY_ABS_Y_OST,
+-	CY_ABS_P_OST,
+-	CY_ABS_W_OST,
+-	CY_ABS_ID_OST,
+-	CY_ABS_MAJ_OST,
+-	CY_ABS_MIN_OST,
+-	CY_ABS_OR_OST,
+-	CY_NUM_ABS_OST	/* number of abs signals */
+-};
+-
+ enum cyttsp4_flags {
+ 	CY_FLAG_NONE = 0x00,
+ 	CY_FLAG_HOVER = 0x04,
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index 362fa181ac04..1b5b30796e43 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -21,15 +21,31 @@
+ 
+ #define CY_TOUCH_SETTINGS_MAX 32
+ 
+-struct touch_framework {
+-	const uint16_t  *abs;
+-	uint8_t         size;
+-} __packed;
++/* abs axis signal offsets in the signals array  */
++enum cyttsp4_sig_ost {
++	CY_ABS_X_OST,
++	CY_ABS_Y_OST,
++	CY_ABS_P_OST,
++	CY_ABS_W_OST,
++	CY_ABS_ID_OST,
++	CY_ABS_MAJ_OST,
++	CY_ABS_MIN_OST,
++	CY_ABS_OR_OST,
++	CY_NUM_ABS_OST	/* number of abs signals */
++};
+ 
+ struct cyttsp4_virtual_key {
+ 	int code;
+ };
+ 
++struct cyttsp4_signal_def {
++	int signal;
++	int min;
++	int max;
++	int fuzz;
++	int flat;
++};
++
+ struct cyttsp4_platform_data {
+ 	char const *inp_dev_name;
+ 	unsigned short flags;
+@@ -46,7 +62,8 @@ struct cyttsp4_platform_data {
+ 	int (*irq_stat)(struct cyttsp4_platform_data *pdata,
+ 		struct device *dev);
+ 
+-	struct touch_framework *frmwrk;
++	int n_signals;
++	struct cyttsp4_signal_def *signals;
+ 
+ 	int n_keys;
+ 	struct cyttsp4_virtual_key* keys;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch
new file mode 100644
index 000000000000..3d9fe6a8d0fd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch
@@ -0,0 +1,85 @@
+From 9459c84d75ab02c4d2a9a7e0606f9b5bedd77baf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 14:46:11 +0200
+Subject: input: cyttsp4: De-obfuscate platform data for keys
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 22 +++-------------------
+ include/linux/platform_data/cyttsp4.h    | 12 ++++++------
+ 2 files changed, 9 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 7cb26929dc73..f2dd87cdeb8f 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -541,8 +541,6 @@ static int cyttsp4_si_get_btn_data(struct cyttsp4 *cd)
+ {
+ 	struct cyttsp4_sysinfo *si = &cd->sysinfo;
+ 	int btn;
+-	int num_defined_keys;
+-	u16 *key_table;
+ 	void *p;
+ 	int rc = 0;
+ 
+@@ -559,24 +557,10 @@ static int cyttsp4_si_get_btn_data(struct cyttsp4 *cd)
+ 		}
+ 		si->btn = p;
+ 
+-		if (cd->cpdata->sett[CY_IC_GRPNUM_BTN_KEYS] == NULL)
+-			num_defined_keys = 0;
+-		else if (cd->cpdata->sett[CY_IC_GRPNUM_BTN_KEYS]->data == NULL)
+-			num_defined_keys = 0;
+-		else
+-			num_defined_keys = cd->cpdata->sett
+-				[CY_IC_GRPNUM_BTN_KEYS]->size;
+-
+-		for (btn = 0; btn < si->si_ofs.num_btns &&
+-			btn < num_defined_keys; btn++) {
+-			key_table = (u16 *)cd->cpdata->sett
+-				[CY_IC_GRPNUM_BTN_KEYS]->data;
+-			si->btn[btn].key_code = key_table[btn];
+-			si->btn[btn].state = CY_BTN_RELEASED;
+-			si->btn[btn].enabled = true;
+-		}
+-		for (; btn < si->si_ofs.num_btns; btn++) {
++		for (btn = 0; btn < si->si_ofs.num_btns; btn++) {
+ 			si->btn[btn].key_code = KEY_RESERVED;
++			if (btn < cd->cpdata->n_keys)
++				si->btn[btn].key_code = cd->cpdata->keys[btn].code;
+ 			si->btn[btn].state = CY_BTN_RELEASED;
+ 			si->btn[btn].enabled = true;
+ 		}
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index 5dc9d2be384b..c54160c17b0b 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -33,11 +33,9 @@ struct cyttsp4_mt_platform_data {
+ 	char const *inp_dev_name;
+ };
+ 
+-struct touch_settings {
+-	const uint8_t *data;
+-	uint32_t size;
+-	uint8_t tag;
+-} __packed;
++struct cyttsp4_virtual_key {
++	int code;
++};
+ 
+ struct cyttsp4_core_platform_data {
+ 	int irq_gpio;
+@@ -51,7 +49,9 @@ struct cyttsp4_core_platform_data {
+ 		int on, struct device *dev, atomic_t *ignore_irq);
+ 	int (*irq_stat)(struct cyttsp4_core_platform_data *pdata,
+ 		struct device *dev);
+-	struct touch_settings *sett[CY_TOUCH_SETTINGS_MAX];
++
++	int n_keys;
++	struct cyttsp4_virtual_key* keys;
+ };
+ 
+ struct cyttsp4_platform_data {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch
new file mode 100644
index 000000000000..860ec062f8aa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch
@@ -0,0 +1,29 @@
+From 1c49ca9a46e73b0c2e2a4224a1eecadab25aa657 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 18:01:49 +0200
+Subject: input: cyttsp4: ENOSYS error is ok when powering up
+
+This error is handled gracefully, don't report it.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index c115cb449146..a9e86e444aeb 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -1764,7 +1764,8 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 		rc = -ENOSYS;
+ 	}
+ 	if (rc < 0) {
+-		dev_err(dev, "%s: HW Power up fails r=%d\n",
++		if (rc != -ENOSYS)
++			dev_err(dev, "%s: HW Power up fails r=%d\n",
+ 				__func__, rc);
+ 
+ 		/* Initiate a read transaction to wake up */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch
new file mode 100644
index 000000000000..09724fd6ad26
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch
@@ -0,0 +1,31 @@
+From e50015b49213fbc00d325c6aba260805b9e6a40a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 18:03:41 +0200
+Subject: input: cyttsp4: Faster recovery from failed wakeup (HACK)
+
+For some reason on Pocket Book Touch Lux 3, sending and I2C
+data, doesn't wake up the device, and it always times out.
+
+Lower the timeout, so that reset is done ASAP after wakeup.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index a9e86e444aeb..8170c25ecdb9 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -26,7 +26,7 @@
+ #define CY_CORE_SLEEP_REQUEST_EXCLUSIVE_TIMEOUT	5000
+ #define CY_CORE_MODE_CHANGE_TIMEOUT		1000
+ #define CY_CORE_RESET_AND_WAIT_TIMEOUT		500
+-#define CY_CORE_WAKEUP_TIMEOUT			500
++#define CY_CORE_WAKEUP_TIMEOUT			50
+ 
+ #define CY_CORE_STARTUP_RETRY_COUNT		3
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Fix-probe-oops.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Fix-probe-oops.patch
new file mode 100644
index 000000000000..c052dfef446c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Fix-probe-oops.patch
@@ -0,0 +1,29 @@
+From 94d7912bd911b7faa48a02e8eb19c6073cb43f0b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 11 Mar 2022 22:01:10 +0100
+Subject: input: cyttsp4: Fix probe oops
+
+__set_bit is called with bit offset -1 which causes oops.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 8036093d99af..f03c8842e447 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -1903,6 +1903,9 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 	for (i = 0; i < cd->n_signals; i++) {
+ 		signal = &cd->signals[i];
+ 
++		if (signal->signal < 0)
++			continue;
++
+ 		__set_bit(signal->signal, cd->input->absbit);
+ 
+ 		max = signal->max;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Fix-warnings.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Fix-warnings.patch
new file mode 100644
index 000000000000..e22e954cf9c1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Fix-warnings.patch
@@ -0,0 +1,47 @@
+From 7fff3f45b05b1bd96202cc2b68042024669e32b6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 7 Oct 2019 06:22:56 +0200
+Subject: input: cyttsp4: Fix warnings
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 882639b8124d..7438fc45c10e 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -1461,6 +1461,7 @@ static void cyttsp4_watchdog_work(struct work_struct *work)
+ 	return;
+ }
+ 
++#if 0
+ static int cyttsp4_set_power(struct cyttsp4* cd, int on)
+ {
+ 	dev_dbg(cd->dev, "Power %s\n", on ? "up" : "down");
+@@ -1476,6 +1477,7 @@ static int cyttsp4_set_power(struct cyttsp4* cd, int on)
+ 
+ 	return -ENOSYS;
+ }
++#endif
+ 
+ static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
+ {
+@@ -1743,12 +1745,12 @@ static int cyttsp4_core_sleep(struct cyttsp4 *cd)
+ 
+ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ {
++#if 0
+ 	struct device *dev = cd->dev;
+ 	int rc;
+ 	u8 mode;
+ 	int t;
+ 
+-#if 0
+ 	/* Already woken? */
+ 	mutex_lock(&cd->system_lock);
+ 	if (cd->sleep_state == SS_SLEEP_OFF) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch
new file mode 100644
index 000000000000..29f2c0f52452
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch
@@ -0,0 +1,105 @@
+From a28a496da915d4fe21792314db5daf2d899bd046 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 14 Oct 2019 18:00:32 +0200
+Subject: input: cyttsp4: Make the driver not hog the system's workqueue
+
+The driver's work items can take 100's of ms, use a separate
+thread for this.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 20 ++++++++++++++------
+ drivers/input/touchscreen/cyttsp4_core.h |  3 ++-
+ 2 files changed, 16 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 7438fc45c10e..8036093d99af 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -721,7 +721,7 @@ static void cyttsp4_queue_startup_(struct cyttsp4 *cd)
+ {
+ 	if (cd->startup_state == STARTUP_NONE) {
+ 		cd->startup_state = STARTUP_QUEUED;
+-		schedule_work(&cd->startup_work);
++		queue_work(cd->wq, &cd->startup_work);
+ 		dev_dbg(cd->dev, "%s: cyttsp4_startup queued\n", __func__);
+ 	} else {
+ 		dev_dbg(cd->dev, "%s: startup_state = %d\n", __func__,
+@@ -1237,9 +1237,7 @@ static void cyttsp4_watchdog_timer(struct timer_list *t)
+ 
+ 	dev_vdbg(cd->dev, "%s: Watchdog timer triggered\n", __func__);
+ 
+-	schedule_work(&cd->watchdog_work);
+-
+-	return;
++	queue_work(cd->wq, &cd->watchdog_work);
+ }
+ 
+ static int cyttsp4_request_exclusive(struct cyttsp4 *cd, void *ownptr,
+@@ -2048,6 +2046,13 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 		goto error_disable_vdd;
+ 	}
+ 
++	cd->wq = alloc_workqueue("cyttsp4", WQ_SYSFS, 0);
++	if (!cd->wq) {
++		rc = -ENOMEM;
++		dev_err(dev, "failed to allocate workqueue\n");
++		goto error_disable_vdd;
++	}
++
+ 	/* Initialize device info */
+ 	cd->dev = dev;
+ 	cd->bus_ops = ops;
+@@ -2071,7 +2076,7 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	if (rc) {
+ 		dev_err(cd->dev, "failed to request IRQ %d, err: %d\n",
+ 			cd->irq, rc);
+-		goto error_disable_vdd;
++		goto error_free_wq;
+ 	}
+ 
+ 	/* Setup watchdog timer */
+@@ -2105,6 +2110,8 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	cyttsp4_stop_wd_timer(cd);
+ 	pm_runtime_disable(dev);
+ 	cyttsp4_free_si_ptrs(cd);
++error_free_wq:
++	destroy_workqueue(cd->wq);
+ error_disable_vdd:
+ 	gpiod_set_value_cansleep(cd->reset_gpio, 1);
+ 	gpiod_set_value_cansleep(cd->power_gpio, 0);
+@@ -2132,8 +2139,9 @@ int cyttsp4_remove(struct cyttsp4 *cd)
+ 	pm_runtime_suspend(dev);
+ 	pm_runtime_disable(dev);
+ 
+-	cancel_work_sync(&cd->startup_work);
+ 	cyttsp4_stop_wd_timer(cd);
++	cancel_work_sync(&cd->startup_work);
++	destroy_workqueue(cd->wq);
+ 	cyttsp4_free_si_ptrs(cd);
+ 	return 0;
+ }
+diff --git a/drivers/input/touchscreen/cyttsp4_core.h b/drivers/input/touchscreen/cyttsp4_core.h
+index cff547979b28..ac2d7b303f39 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.h
++++ b/drivers/input/touchscreen/cyttsp4_core.h
+@@ -62,7 +62,7 @@ enum cyttsp_cmd_bits {
+ };
+ 
+ /* Timeout in ms. */
+-#define CY_WATCHDOG_TIMEOUT		1000
++#define CY_WATCHDOG_TIMEOUT		10000
+ 
+ #define CY_MAX_PRINT_SIZE		512
+ #ifdef VERBOSE_DEBUG
+@@ -316,6 +316,7 @@ struct cyttsp4 {
+ 	enum cyttsp4_startup_state startup_state;
+ 	int int_status;
+ 	wait_queue_head_t wait_q;
++	struct workqueue_struct *wq;
+ 	int irq;
+ 	struct work_struct startup_work;
+ 	struct work_struct watchdog_work;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch
new file mode 100644
index 000000000000..696c3aa2b5ee
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch
@@ -0,0 +1,590 @@
+From 74643e4ce47d119319d0d818045d1e598ef1e8b6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 1 Oct 2019 00:31:06 +0200
+Subject: input: cyttsp4: Port the driver to use device properties
+
+The driver has several unimplemented features, that are nevertheless
+expressed in its platform data. Drop this.
+
+If needed, interested parties can implement them properly in the
+future.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 234 +++++++++++------------
+ drivers/input/touchscreen/cyttsp4_core.h |  36 +++-
+ include/linux/platform_data/cyttsp4.h    |  70 -------
+ 3 files changed, 151 insertions(+), 189 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 8170c25ecdb9..c2781ca405a6 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -17,7 +17,9 @@
+ #include <linux/gpio.h>
+ #include <linux/input/mt.h>
+ #include <linux/interrupt.h>
++#include <linux/of_device.h>
+ #include <linux/pm_runtime.h>
++#include <linux/property.h>
+ #include <linux/sched.h>
+ #include <linux/slab.h>
+ 
+@@ -131,23 +133,20 @@ static int cyttsp4_hw_soft_reset(struct cyttsp4 *cd)
+ 	return 0;
+ }
+ 
+-static int cyttsp4_hw_hard_reset(struct cyttsp4 *cd)
+-{
+-	if (cd->pdata->xres) {
+-		cd->pdata->xres(cd->pdata, cd->dev);
+-		dev_dbg(cd->dev, "%s: execute HARD reset\n", __func__);
+-		return 0;
+-	}
+-	dev_err(cd->dev, "%s: FAILED to execute HARD reset\n", __func__);
+-	return -ENOSYS;
+-}
+-
+ static int cyttsp4_hw_reset(struct cyttsp4 *cd)
+ {
+-	int rc = cyttsp4_hw_hard_reset(cd);
+-	if (rc == -ENOSYS)
+-		rc = cyttsp4_hw_soft_reset(cd);
+-	return rc;
++	if (!cd->reset_gpio)
++		return cyttsp4_hw_soft_reset(cd);
++
++	gpiod_set_value_cansleep(cd->reset_gpio, 1);
++	msleep(20);
++
++	gpiod_set_value_cansleep(cd->reset_gpio, 0);
++	msleep(40);
++
++	gpiod_set_value_cansleep(cd->reset_gpio, 1);
++	msleep(20);
++	return 0;
+ }
+ 
+ /*
+@@ -559,8 +558,8 @@ static int cyttsp4_si_get_btn_data(struct cyttsp4 *cd)
+ 
+ 		for (btn = 0; btn < si->si_ofs.num_btns; btn++) {
+ 			si->btn[btn].key_code = KEY_RESERVED;
+-			if (btn < cd->pdata->n_keys)
+-				si->btn[btn].key_code = cd->pdata->keys[btn].code;
++			if (btn < cd->n_keys)
++				si->btn[btn].key_code = cd->keys[btn].code;
+ 			si->btn[btn].state = CY_BTN_RELEASED;
+ 			si->btn[btn].enabled = true;
+ 		}
+@@ -803,13 +802,13 @@ static void cyttsp4_get_touch(struct cyttsp4 *cd,
+ 			touch->abs[abs], touch->abs[abs]);
+ 	}
+ 
+-	if (cd->pdata->flags & CY_FLAG_FLIP) {
++	if (cd->flags & CY_FLAG_FLIP) {
+ 		swap(touch->abs[CY_TCH_X], touch->abs[CY_TCH_Y]);
+ 		flipped = true;
+ 	} else
+ 		flipped = false;
+ 
+-	if (cd->pdata->flags & CY_FLAG_INV_X) {
++	if (cd->flags & CY_FLAG_INV_X) {
+ 		if (flipped)
+ 			touch->abs[CY_TCH_X] = cd->si->si_ofs.max_y -
+ 				touch->abs[CY_TCH_X];
+@@ -817,7 +816,7 @@ static void cyttsp4_get_touch(struct cyttsp4 *cd,
+ 			touch->abs[CY_TCH_X] = cd->si->si_ofs.max_x -
+ 				touch->abs[CY_TCH_X];
+ 	}
+-	if (cd->pdata->flags & CY_FLAG_INV_Y) {
++	if (cd->flags & CY_FLAG_INV_Y) {
+ 		if (flipped)
+ 			touch->abs[CY_TCH_Y] = cd->si->si_ofs.max_x -
+ 				touch->abs[CY_TCH_Y];
+@@ -828,8 +827,8 @@ static void cyttsp4_get_touch(struct cyttsp4 *cd,
+ 
+ 	dev_vdbg(dev, "%s: flip=%s inv-x=%s inv-y=%s x=%04X(%d) y=%04X(%d)\n",
+ 		__func__, flipped ? "true" : "false",
+-		cd->pdata->flags & CY_FLAG_INV_X ? "true" : "false",
+-		cd->pdata->flags & CY_FLAG_INV_Y ? "true" : "false",
++		cd->flags & CY_FLAG_INV_X ? "true" : "false",
++		cd->flags & CY_FLAG_INV_Y ? "true" : "false",
+ 		touch->abs[CY_TCH_X], touch->abs[CY_TCH_X],
+ 		touch->abs[CY_TCH_Y], touch->abs[CY_TCH_Y]);
+ }
+@@ -861,7 +860,7 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 		cyttsp4_get_touch(cd, &tch, si->xy_data +
+ 				  (i * si->si_ofs.tch_rec_size));
+ 
+-		sig = &cd->pdata->signals[CY_ABS_ID_OST];
++		sig = &cd->signals[CY_ABS_ID_OST];
+ 		if (tch.abs[CY_TCH_T] < sig->min ||
+ 			tch.abs[CY_TCH_T] > sig->max) {
+ 			dev_err(dev, "%s: tch=%d -> bad trk_id=%d max_id=%d\n",
+@@ -885,7 +884,7 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 
+ 		/* all devices: position and pressure fields */
+ 		for (j = 0; j <= CY_ABS_W_OST; j++) {
+-			sig = &cd->pdata->signals[j];
++			sig = &cd->signals[j];
+ 			if (sig->signal >= 0)
+ 				input_report_abs(cd->input, sig->signal,
+ 						 tch.abs[CY_TCH_X + j]);
+@@ -903,7 +902,7 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 
+ 			/* Get the extended touch fields */
+ 			for (j = 0; j < CY_NUM_EXT_TCH_FIELDS; j++) {
+-				sig = &cd->pdata->signals[CY_ABS_MAJ_OST + j];
++				sig = &cd->signals[CY_ABS_MAJ_OST + j];
+ 				if (sig->signal >= 0)
+ 					input_report_abs(cd->input, sig->signal,
+ 							 tch.abs[CY_TCH_MAJ + j]);
+@@ -1207,13 +1206,6 @@ static irqreturn_t cyttsp4_irq(int irq, void *handle)
+ 		dev_err(dev, "%s: Fail handshake mode=0x%02X r=%d\n",
+ 				__func__, mode[0], rc);
+ 
+-	/*
+-	 * a non-zero udelay period is required for using
+-	 * IRQF_TRIGGER_LOW in order to delay until the
+-	 * device completes isr deassert
+-	 */
+-	udelay(cd->pdata->level_irq_udelay);
+-
+ cyttsp4_irq_exit:
+ 	mutex_unlock(&cd->system_lock);
+ 	return IRQ_HANDLED;
+@@ -1471,6 +1463,22 @@ static void cyttsp4_watchdog_work(struct work_struct *work)
+ 	return;
+ }
+ 
++static int cyttsp4_set_power(struct cyttsp4* cd, int on)
++{
++	dev_dbg(cd->dev, "Power %s\n", on ? "up" : "down");
++
++	if (!cd->power_gpio)
++		return -ENOSYS;
++
++	//atomic_set(&cd->ignore_irq, 1);
++
++	//gpiod_set_value_cansleep(cd->power_gpio, on);
++
++	//atomic_set(&cd->ignore_irq, 0);
++
++	return -ENOSYS;
++}
++
+ static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
+ {
+ 	enum cyttsp4_sleep_state ss = SS_SLEEP_ON;
+@@ -1517,13 +1525,7 @@ static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
+ 	}
+ 	dev_vdbg(cd->dev, "%s: write DEEP SLEEP succeeded\n", __func__);
+ 
+-	if (cd->pdata->power) {
+-		dev_dbg(cd->dev, "%s: Power down HW\n", __func__);
+-		rc = cd->pdata->power(cd->pdata, 0, cd->dev, &cd->ignore_irq);
+-	} else {
+-		dev_dbg(cd->dev, "%s: No power function\n", __func__);
+-		rc = 0;
+-	}
++	rc = cyttsp4_set_power(cd, 0);
+ 	if (rc < 0) {
+ 		dev_err(cd->dev, "%s: HW Power down fails r=%d\n",
+ 				__func__, rc);
+@@ -1756,13 +1758,7 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 	cd->int_status |= CY_INT_AWAKE;
+ 	cd->sleep_state = SS_WAKING;
+ 
+-	if (cd->pdata->power) {
+-		dev_dbg(dev, "%s: Power up HW\n", __func__);
+-		rc = cd->pdata->power(cd->pdata, 1, dev, &cd->ignore_irq);
+-	} else {
+-		dev_dbg(dev, "%s: No power function\n", __func__);
+-		rc = -ENOSYS;
+-	}
++	rc = cyttsp4_set_power(cd, 1);
+ 	if (rc < 0) {
+ 		if (rc != -ENOSYS)
+ 			dev_err(dev, "%s: HW Power up fails r=%d\n",
+@@ -1886,7 +1882,7 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 	max_y_tmp = cd->si->si_ofs.max_y;
+ 
+ 	/* get maximum values from the sysinfo data */
+-	if (cd->pdata->flags & CY_FLAG_FLIP) {
++	if (cd->flags & CY_FLAG_FLIP) {
+ 		max_x = max_y_tmp - 1;
+ 		max_y = max_x_tmp - 1;
+ 	} else {
+@@ -1896,8 +1892,8 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 	max_p = cd->si->si_ofs.max_p;
+ 
+ 	/* set event signal capabilities */
+-	for (i = 0; i < cd->pdata->n_signals; i++) {
+-		signal = &cd->pdata->signals[i];
++	for (i = 0; i < cd->n_signals; i++) {
++		signal = &cd->signals[i];
+ 
+ 		__set_bit(signal->signal, cd->input->absbit);
+ 
+@@ -1948,7 +1944,7 @@ static int cyttsp4_mt_probe(struct cyttsp4 *cd)
+ 		goto error_alloc_failed;
+ 	}
+ 
+-	cd->input->name = cd->pdata->inp_dev_name;
++	cd->input->name = "mt_ctp";
+ 	scnprintf(cd->phys, sizeof(cd->phys)-1, "%s", dev_name(dev));
+ 	cd->input->phys = cd->phys;
+ 	cd->input->id.bustype = cd->bus_ops->bustype;
+@@ -1973,38 +1969,77 @@ static int cyttsp4_mt_probe(struct cyttsp4 *cd)
+ 	return rc;
+ }
+ 
++static struct cyttsp4_signal_def cyttsp4_default_signals[CY_NUM_ABS_OST] = {
++	[CY_ABS_X_OST]   = { ABS_MT_POSITION_X, 0, 758, },
++	[CY_ABS_Y_OST]   = { ABS_MT_POSITION_Y, 0, 1024, },
++	[CY_ABS_P_OST]   = { ABS_MT_PRESSURE, 0, 255, },
++	[CY_ABS_W_OST]   = { -1 },
++	[CY_ABS_ID_OST]  = { ABS_MT_TRACKING_ID, 0, 15, },
++	[CY_ABS_MAJ_OST] = { ABS_MT_TOUCH_MAJOR, 0, 255, },
++	[CY_ABS_MIN_OST] = { ABS_MT_TOUCH_MINOR, 0, 255, },
++	[CY_ABS_OR_OST]  = { ABS_MT_ORIENTATION, -127, 127, },
++};
++
+ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 		struct device *dev, u16 irq, size_t xfer_buf_size)
+ {
+ 	struct cyttsp4 *cd;
+-	struct cyttsp4_platform_data *pdata = dev_get_platdata(dev);
+-	unsigned long irq_flags;
+ 	int rc = 0;
+ 
+-	if (!pdata) {
+-		dev_err(dev, "%s: Missing platform data\n", __func__);
+-		rc = -ENODEV;
+-		goto error_no_pdata;
+-	}
+-
+-	cd = kzalloc(sizeof(*cd), GFP_KERNEL);
++	cd = devm_kzalloc(dev, sizeof(*cd), GFP_KERNEL);
+ 	if (!cd) {
+ 		dev_err(dev, "%s: Error, kzalloc\n", __func__);
+-		rc = -ENOMEM;
+-		goto error_alloc_data;
++		return ERR_PTR(-ENOMEM);
+ 	}
+ 
+-	cd->xfer_buf = kzalloc(xfer_buf_size, GFP_KERNEL);
++	cd->signals = cyttsp4_default_signals;
++	cd->n_signals = ARRAY_SIZE(cyttsp4_default_signals);
++
++	if (device_property_read_bool(dev, "flip"))
++		cd->flags |= CY_FLAG_FLIP;
++	if (device_property_read_bool(dev, "invert-x"))
++		cd->flags |= CY_FLAG_INV_X;
++	if (device_property_read_bool(dev, "invert-y"))
++		cd->flags |= CY_FLAG_INV_Y;
++
++	cd->vdd_supply = devm_regulator_get(dev, "vdd");
++	if (IS_ERR(cd->vdd_supply)) {
++		rc = PTR_ERR(cd->vdd_supply);
++		dev_err(dev, "can't get vdd power (%d)\n", rc);
++		return ERR_PTR(rc);
++	}
++
++	rc = regulator_enable(cd->vdd_supply);
++	if (rc) {
++		dev_err(dev, "can't enable vdd power (%d)\n", rc);
++		return ERR_PTR(rc);
++	}
++
++	cd->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_HIGH);
++	if (IS_ERR(cd->reset_gpio)) {
++		rc = PTR_ERR(cd->reset_gpio);
++		dev_err(dev, "can't get reset gpio (%d)\n", rc);
++		return ERR_PTR(rc);
++	}
++
++	cd->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
++	if (IS_ERR(cd->reset_gpio)) {
++		rc = PTR_ERR(cd->reset_gpio);
++		dev_err(dev, "can't get reset gpio (%d)\n", rc);
++		return ERR_PTR(rc);
++	}
++
++	cd->xfer_buf = devm_kzalloc(dev, xfer_buf_size, GFP_KERNEL);
+ 	if (!cd->xfer_buf) {
+ 		dev_err(dev, "%s: Error, kzalloc\n", __func__);
+ 		rc = -ENOMEM;
+-		goto error_free_cd;
++		goto error_disable_vdd;
+ 	}
+ 
+ 	/* Initialize device info */
+ 	cd->dev = dev;
+-	cd->pdata = pdata;
+ 	cd->bus_ops = ops;
++	dev_set_drvdata(dev, cd);
+ 
+ 	/* Initialize mutexes and spinlocks */
+ 	mutex_init(&cd->system_lock);
+@@ -2018,43 +2053,20 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	INIT_WORK(&cd->watchdog_work, cyttsp4_watchdog_work);
+ 
+ 	/* Initialize IRQ */
+-	cd->irq = gpio_to_irq(cd->pdata->irq_gpio);
+-	if (cd->irq < 0) {
+-		rc = -EINVAL;
+-		goto error_free_xfer;
+-	}
+-
+-	dev_set_drvdata(dev, cd);
+-
+-	/* Call platform init function */
+-	if (cd->pdata->init) {
+-		dev_dbg(cd->dev, "%s: Init HW\n", __func__);
+-		rc = cd->pdata->init(cd->pdata, 1, cd->dev);
+-	} else {
+-		dev_dbg(cd->dev, "%s: No HW INIT function\n", __func__);
+-		rc = 0;
+-	}
+-	if (rc < 0)
+-		dev_err(cd->dev, "%s: HW Init fail r=%d\n", __func__, rc);
+-
+-	dev_dbg(dev, "%s: initialize threaded irq=%d\n", __func__, cd->irq);
+-	if (cd->pdata->level_irq_udelay > 0)
+-		/* use level triggered interrupts */
+-		irq_flags = IRQF_TRIGGER_LOW | IRQF_ONESHOT;
+-	else
+-		/* use edge triggered interrupts */
+-		irq_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
+-
+-	rc = request_threaded_irq(cd->irq, NULL, cyttsp4_irq, irq_flags,
+-		dev_name(dev), cd);
+-	if (rc < 0) {
+-		dev_err(dev, "%s: Error, could not request irq\n", __func__);
+-		goto error_request_irq;
++	rc = devm_request_threaded_irq(dev, cd->irq, NULL, cyttsp4_irq,
++				       IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
++				       dev_name(dev), cd);
++	if (rc) {
++		dev_err(cd->dev, "failed to request IRQ %d, err: %d\n",
++			cd->irq, rc);
++		goto error_disable_vdd;
+ 	}
+ 
+ 	/* Setup watchdog timer */
+ 	timer_setup(&cd->watchdog_timer, cyttsp4_watchdog_timer, 0);
+ 
++	//XXX: msleep(300);
++
+ 	/*
+ 	 * call startup directly to ensure that the device
+ 	 * is tested before leaving the probe
+@@ -2062,17 +2074,15 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	rc = cyttsp4_startup(cd);
+ 
+ 	/* Do not fail probe if startup fails but the device is detected */
+-	if (rc < 0 && cd->mode == CY_MODE_UNKNOWN) {
+-		dev_err(cd->dev, "%s: Fail initial startup r=%d\n",
++	if (rc && cd->mode == CY_MODE_UNKNOWN) {
++		dev_err(cd->dev, "%s: Fail initial startup rc=%d\n",
+ 			__func__, rc);
+ 		goto error_startup;
+ 	}
+ 
+ 	rc = cyttsp4_mt_probe(cd);
+-	if (rc < 0) {
+-		dev_err(dev, "%s: Error, fail mt probe\n", __func__);
++	if (rc)
+ 		goto error_startup;
+-	}
+ 
+ 	pm_runtime_enable(dev);
+ 
+@@ -2083,17 +2093,10 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	cyttsp4_stop_wd_timer(cd);
+ 	pm_runtime_disable(dev);
+ 	cyttsp4_free_si_ptrs(cd);
+-	free_irq(cd->irq, cd);
+-error_request_irq:
+-	if (cd->pdata->init)
+-		cd->pdata->init(cd->pdata, 0, dev);
+-error_free_xfer:
+-	kfree(cd->xfer_buf);
+-error_free_cd:
+-	kfree(cd);
+-error_alloc_data:
+-error_no_pdata:
+-	dev_err(dev, "%s failed.\n", __func__);
++error_disable_vdd:
++	gpiod_set_value_cansleep(cd->reset_gpio, 1);
++	gpiod_set_value_cansleep(cd->power_gpio, 0);
++	regulator_disable(cd->vdd_supply);
+ 	return ERR_PTR(rc);
+ }
+ EXPORT_SYMBOL_GPL(cyttsp4_probe);
+@@ -2118,14 +2121,8 @@ int cyttsp4_remove(struct cyttsp4 *cd)
+ 	pm_runtime_disable(dev);
+ 
+ 	cancel_work_sync(&cd->startup_work);
+-
+ 	cyttsp4_stop_wd_timer(cd);
+-
+-	free_irq(cd->irq, cd);
+-	if (cd->pdata->init)
+-		cd->pdata->init(cd->pdata, 0, dev);
+ 	cyttsp4_free_si_ptrs(cd);
+-	kfree(cd);
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(cyttsp4_remove);
+@@ -2133,3 +2130,4 @@ EXPORT_SYMBOL_GPL(cyttsp4_remove);
+ MODULE_LICENSE("GPL");
+ MODULE_DESCRIPTION("Cypress TrueTouch(R) Standard touchscreen core driver");
+ MODULE_AUTHOR("Cypress");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
+diff --git a/drivers/input/touchscreen/cyttsp4_core.h b/drivers/input/touchscreen/cyttsp4_core.h
+index 995bfd0a54d0..cff547979b28 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.h
++++ b/drivers/input/touchscreen/cyttsp4_core.h
+@@ -24,6 +24,8 @@
+ #include <linux/stringify.h>
+ #include <linux/types.h>
+ #include <linux/platform_data/cyttsp4.h>
++#include <linux/regulator/consumer.h>
++#include <linux/gpio.h>
+ 
+ #define CY_REG_BASE			0x00
+ 
+@@ -329,12 +331,19 @@ struct cyttsp4 {
+ 	bool is_suspended;
+ 	char phys[NAME_MAX];
+ 	int num_prv_tch;
+-	struct cyttsp4_platform_data *pdata;
+ 	const struct cyttsp4_bus_ops *bus_ops;
+ 	u8 *xfer_buf;
+ #ifdef VERBOSE_DEBUG
+ 	u8 pr_buf[CY_MAX_PRBUF_SIZE];
+ #endif
++	int flags;
++	int n_signals;
++	struct cyttsp4_signal_def *signals;
++	int n_keys;
++	struct cyttsp4_virtual_key* keys;
++	struct gpio_desc *reset_gpio;
++	struct gpio_desc *power_gpio;
++	struct regulator *vdd_supply;
+ };
+ 
+ struct cyttsp4_bus_ops {
+@@ -392,6 +401,31 @@ enum cyttsp4_event_id {
+ /* y-axis, 0:origin is on top side of panel, 1: bottom */
+ #define CY_PCFG_ORIGIN_Y_MASK		0x80
+ 
++/* abs axis signal offsets in the signals array  */
++enum cyttsp4_sig_ost {
++	CY_ABS_X_OST,
++	CY_ABS_Y_OST,
++	CY_ABS_P_OST,
++	CY_ABS_W_OST,
++	CY_ABS_ID_OST,
++	CY_ABS_MAJ_OST,
++	CY_ABS_MIN_OST,
++	CY_ABS_OR_OST,
++	CY_NUM_ABS_OST	/* number of abs signals */
++};
++
++struct cyttsp4_virtual_key {
++	int code;
++};
++
++struct cyttsp4_signal_def {
++	int signal;
++	int min;
++	int max;
++	int fuzz;
++	int flat;
++};
++
+ static inline int cyttsp4_adap_read(struct cyttsp4 *ts, u16 addr, int size,
+ 		void *buf)
+ {
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index e718d2204ce7..e69de29bb2d1 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -1,70 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * Header file for:
+- * Cypress TrueTouch(TM) Standard Product (TTSP) touchscreen drivers.
+- * For use with Cypress Txx3xx parts.
+- * Supported parts include:
+- * CY8CTST341
+- * CY8CTMA340
+- *
+- * Copyright (C) 2009, 2010, 2011 Cypress Semiconductor, Inc.
+- * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
+- *
+- * Contact Cypress Semiconductor at www.cypress.com (kev@cypress.com)
+- */
+-#ifndef _CYTTSP4_H_
+-#define _CYTTSP4_H_
+-
+-#define CYTTSP4_MT_NAME "cyttsp4_mt"
+-
+-#define CY_TOUCH_SETTINGS_MAX 32
+-
+-/* abs axis signal offsets in the signals array  */
+-enum cyttsp4_sig_ost {
+-	CY_ABS_X_OST,
+-	CY_ABS_Y_OST,
+-	CY_ABS_P_OST,
+-	CY_ABS_W_OST,
+-	CY_ABS_ID_OST,
+-	CY_ABS_MAJ_OST,
+-	CY_ABS_MIN_OST,
+-	CY_ABS_OR_OST,
+-	CY_NUM_ABS_OST	/* number of abs signals */
+-};
+-
+-struct cyttsp4_virtual_key {
+-	int code;
+-};
+-
+-struct cyttsp4_signal_def {
+-	int signal;
+-	int min;
+-	int max;
+-	int fuzz;
+-	int flat;
+-};
+-
+-struct cyttsp4_platform_data {
+-	char const *inp_dev_name;
+-	unsigned short flags;
+-
+-	int irq_gpio;
+-	int rst_gpio;
+-	int level_irq_udelay;
+-	int (*xres)(struct cyttsp4_platform_data *pdata,
+-		struct device *dev);
+-	int (*init)(struct cyttsp4_platform_data *pdata,
+-		int on, struct device *dev);
+-	int (*power)(struct cyttsp4_platform_data *pdata,
+-		int on, struct device *dev, atomic_t *ignore_irq);
+-	int (*irq_stat)(struct cyttsp4_platform_data *pdata,
+-		struct device *dev);
+-
+-	int n_signals;
+-	struct cyttsp4_signal_def *signals;
+-
+-	int n_keys;
+-	struct cyttsp4_virtual_key* keys;
+-};
+-
+-#endif /* _CYTTSP4_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch
new file mode 100644
index 000000000000..dba31301792e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch
@@ -0,0 +1,27 @@
+From 884f2752927453a9a916d9a08b64ab0745635a34 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 15:06:16 +0200
+Subject: input: cyttsp4: Remove unused enable_vkeys
+
+It doesn't seem to be used anywhere.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ include/linux/platform_data/cyttsp4.h | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index 1f945aa2466e..362fa181ac04 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -24,7 +24,6 @@
+ struct touch_framework {
+ 	const uint16_t  *abs;
+ 	uint8_t         size;
+-	uint8_t         enable_vkeys;
+ } __packed;
+ 
+ struct cyttsp4_virtual_key {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch
new file mode 100644
index 000000000000..08221dc26ed6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch
@@ -0,0 +1,718 @@
+From 362d32b72092cc79b46ab9121e4046993f1462de Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 15:05:39 +0200
+Subject: input: cyttsp4: Remove useless indirection with driver/platform data
+
+It is not necessary to have struct cyttsp4_mt_data fields separate
+from struct cyttsp4, as cyttsp4_mt_data was embedded as 'md' field
+anyway.
+
+The same goes for struct cyttsp4_mt_platform_data.
+
+Remove all this indirection.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 233 +++++++++++------------
+ drivers/input/touchscreen/cyttsp4_core.h |  18 +-
+ include/linux/platform_data/cyttsp4.h    |  26 +--
+ 3 files changed, 128 insertions(+), 149 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index f2dd87cdeb8f..867c18abc89b 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -133,8 +133,8 @@ static int cyttsp4_hw_soft_reset(struct cyttsp4 *cd)
+ 
+ static int cyttsp4_hw_hard_reset(struct cyttsp4 *cd)
+ {
+-	if (cd->cpdata->xres) {
+-		cd->cpdata->xres(cd->cpdata, cd->dev);
++	if (cd->pdata->xres) {
++		cd->pdata->xres(cd->pdata, cd->dev);
+ 		dev_dbg(cd->dev, "%s: execute HARD reset\n", __func__);
+ 		return 0;
+ 	}
+@@ -559,8 +559,8 @@ static int cyttsp4_si_get_btn_data(struct cyttsp4 *cd)
+ 
+ 		for (btn = 0; btn < si->si_ofs.num_btns; btn++) {
+ 			si->btn[btn].key_code = KEY_RESERVED;
+-			if (btn < cd->cpdata->n_keys)
+-				si->btn[btn].key_code = cd->cpdata->keys[btn].code;
++			if (btn < cd->pdata->n_keys)
++				si->btn[btn].key_code = cd->pdata->keys[btn].code;
+ 			si->btn[btn].state = CY_BTN_RELEASED;
+ 			si->btn[btn].enabled = true;
+ 		}
+@@ -732,41 +732,41 @@ static void cyttsp4_queue_startup_(struct cyttsp4 *cd)
+ 	}
+ }
+ 
+-static void cyttsp4_report_slot_liftoff(struct cyttsp4_mt_data *md,
++static void cyttsp4_report_slot_liftoff(struct cyttsp4 *cd,
+ 		int max_slots)
+ {
+ 	int t;
+ 
+-	if (md->num_prv_tch == 0)
++	if (cd->num_prv_tch == 0)
+ 		return;
+ 
+ 	for (t = 0; t < max_slots; t++) {
+-		input_mt_slot(md->input, t);
+-		input_mt_report_slot_inactive(md->input);
++		input_mt_slot(cd->input, t);
++		input_mt_report_slot_inactive(cd->input);
+ 	}
+ }
+ 
+-static void cyttsp4_lift_all(struct cyttsp4_mt_data *md)
++static void cyttsp4_lift_all(struct cyttsp4 *cd)
+ {
+-	if (!md->si)
++	if (!cd->si)
+ 		return;
+ 
+-	if (md->num_prv_tch != 0) {
+-		cyttsp4_report_slot_liftoff(md,
+-				md->si->si_ofs.tch_abs[CY_TCH_T].max);
+-		input_sync(md->input);
+-		md->num_prv_tch = 0;
++	if (cd->num_prv_tch != 0) {
++		cyttsp4_report_slot_liftoff(cd,
++				cd->si->si_ofs.tch_abs[CY_TCH_T].max);
++		input_sync(cd->input);
++		cd->num_prv_tch = 0;
+ 	}
+ }
+ 
+-static void cyttsp4_get_touch_axis(struct cyttsp4_mt_data *md,
++static void cyttsp4_get_touch_axis(struct cyttsp4 *cd,
+ 	int *axis, int size, int max, u8 *xy_data, int bofs)
+ {
+ 	int nbyte;
+ 	int next;
+ 
+ 	for (nbyte = 0, *axis = 0, next = 0; nbyte < size; nbyte++) {
+-		dev_vdbg(&md->input->dev,
++		dev_vdbg(&cd->input->dev,
+ 			"%s: *axis=%02X(%d) size=%d max=%08X xy_data=%p"
+ 			" xy_data[%d]=%02X(%d) bofs=%d\n",
+ 			__func__, *axis, *axis, size, max, xy_data, next,
+@@ -777,23 +777,23 @@ static void cyttsp4_get_touch_axis(struct cyttsp4_mt_data *md,
+ 
+ 	*axis &= max - 1;
+ 
+-	dev_vdbg(&md->input->dev,
++	dev_vdbg(&cd->input->dev,
+ 		"%s: *axis=%02X(%d) size=%d max=%08X xy_data=%p"
+ 		" xy_data[%d]=%02X(%d)\n",
+ 		__func__, *axis, *axis, size, max, xy_data, next,
+ 		xy_data[next], xy_data[next]);
+ }
+ 
+-static void cyttsp4_get_touch(struct cyttsp4_mt_data *md,
++static void cyttsp4_get_touch(struct cyttsp4 *cd,
+ 	struct cyttsp4_touch *touch, u8 *xy_data)
+ {
+-	struct device *dev = &md->input->dev;
+-	struct cyttsp4_sysinfo *si = md->si;
++	struct device *dev = &cd->input->dev;
++	struct cyttsp4_sysinfo *si = cd->si;
+ 	enum cyttsp4_tch_abs abs;
+ 	bool flipped;
+ 
+ 	for (abs = CY_TCH_X; abs < CY_TCH_NUM_ABS; abs++) {
+-		cyttsp4_get_touch_axis(md, &touch->abs[abs],
++		cyttsp4_get_touch_axis(cd, &touch->abs[abs],
+ 			si->si_ofs.tch_abs[abs].size,
+ 			si->si_ofs.tch_abs[abs].max,
+ 			xy_data + si->si_ofs.tch_abs[abs].ofs,
+@@ -803,33 +803,33 @@ static void cyttsp4_get_touch(struct cyttsp4_mt_data *md,
+ 			touch->abs[abs], touch->abs[abs]);
+ 	}
+ 
+-	if (md->pdata->flags & CY_FLAG_FLIP) {
++	if (cd->pdata->flags & CY_FLAG_FLIP) {
+ 		swap(touch->abs[CY_TCH_X], touch->abs[CY_TCH_Y]);
+ 		flipped = true;
+ 	} else
+ 		flipped = false;
+ 
+-	if (md->pdata->flags & CY_FLAG_INV_X) {
++	if (cd->pdata->flags & CY_FLAG_INV_X) {
+ 		if (flipped)
+-			touch->abs[CY_TCH_X] = md->si->si_ofs.max_y -
++			touch->abs[CY_TCH_X] = cd->si->si_ofs.max_y -
+ 				touch->abs[CY_TCH_X];
+ 		else
+-			touch->abs[CY_TCH_X] = md->si->si_ofs.max_x -
++			touch->abs[CY_TCH_X] = cd->si->si_ofs.max_x -
+ 				touch->abs[CY_TCH_X];
+ 	}
+-	if (md->pdata->flags & CY_FLAG_INV_Y) {
++	if (cd->pdata->flags & CY_FLAG_INV_Y) {
+ 		if (flipped)
+-			touch->abs[CY_TCH_Y] = md->si->si_ofs.max_x -
++			touch->abs[CY_TCH_Y] = cd->si->si_ofs.max_x -
+ 				touch->abs[CY_TCH_Y];
+ 		else
+-			touch->abs[CY_TCH_Y] = md->si->si_ofs.max_y -
++			touch->abs[CY_TCH_Y] = cd->si->si_ofs.max_y -
+ 				touch->abs[CY_TCH_Y];
+ 	}
+ 
+ 	dev_vdbg(dev, "%s: flip=%s inv-x=%s inv-y=%s x=%04X(%d) y=%04X(%d)\n",
+ 		__func__, flipped ? "true" : "false",
+-		md->pdata->flags & CY_FLAG_INV_X ? "true" : "false",
+-		md->pdata->flags & CY_FLAG_INV_Y ? "true" : "false",
++		cd->pdata->flags & CY_FLAG_INV_X ? "true" : "false",
++		cd->pdata->flags & CY_FLAG_INV_Y ? "true" : "false",
+ 		touch->abs[CY_TCH_X], touch->abs[CY_TCH_X],
+ 		touch->abs[CY_TCH_Y], touch->abs[CY_TCH_Y]);
+ }
+@@ -848,10 +848,10 @@ static void cyttsp4_final_sync(struct input_dev *input, int max_slots, int *ids)
+ 	input_sync(input);
+ }
+ 
+-static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
++static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ {
+-	struct device *dev = &md->input->dev;
+-	struct cyttsp4_sysinfo *si = md->si;
++	struct device *dev = &cd->input->dev;
++	struct cyttsp4_sysinfo *si = cd->si;
+ 	struct cyttsp4_touch tch;
+ 	int sig;
+ 	int i, j, t = 0;
+@@ -859,42 +859,42 @@ static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
+ 
+ 	memset(ids, 0, si->si_ofs.tch_abs[CY_TCH_T].max * sizeof(int));
+ 	for (i = 0; i < num_cur_tch; i++) {
+-		cyttsp4_get_touch(md, &tch, si->xy_data +
++		cyttsp4_get_touch(cd, &tch, si->xy_data +
+ 			(i * si->si_ofs.tch_rec_size));
+-		if ((tch.abs[CY_TCH_T] < md->pdata->frmwrk->abs
++		if ((tch.abs[CY_TCH_T] < cd->pdata->frmwrk->abs
+ 			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MIN_OST]) ||
+-			(tch.abs[CY_TCH_T] > md->pdata->frmwrk->abs
++			(tch.abs[CY_TCH_T] > cd->pdata->frmwrk->abs
+ 			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MAX_OST])) {
+ 			dev_err(dev, "%s: tch=%d -> bad trk_id=%d max_id=%d\n",
+ 				__func__, i, tch.abs[CY_TCH_T],
+-				md->pdata->frmwrk->abs[(CY_ABS_ID_OST *
++				cd->pdata->frmwrk->abs[(CY_ABS_ID_OST *
+ 				CY_NUM_ABS_SET) + CY_MAX_OST]);
+ 			continue;
+ 		}
+ 
+ 		/* use 0 based track id's */
+-		sig = md->pdata->frmwrk->abs
++		sig = cd->pdata->frmwrk->abs
+ 			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + 0];
+ 		if (sig != CY_IGNORE_VALUE) {
+-			t = tch.abs[CY_TCH_T] - md->pdata->frmwrk->abs
++			t = tch.abs[CY_TCH_T] - cd->pdata->frmwrk->abs
+ 				[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MIN_OST];
+ 			if (tch.abs[CY_TCH_E] == CY_EV_LIFTOFF) {
+ 				dev_dbg(dev, "%s: t=%d e=%d lift-off\n",
+ 					__func__, t, tch.abs[CY_TCH_E]);
+ 				goto cyttsp4_get_mt_touches_pr_tch;
+ 			}
+-			input_mt_slot(md->input, t);
+-			input_mt_report_slot_state(md->input, MT_TOOL_FINGER,
++			input_mt_slot(cd->input, t);
++			input_mt_report_slot_state(cd->input, MT_TOOL_FINGER,
+ 					true);
+ 			ids[t] = true;
+ 		}
+ 
+ 		/* all devices: position and pressure fields */
+ 		for (j = 0; j <= CY_ABS_W_OST; j++) {
+-			sig = md->pdata->frmwrk->abs[((CY_ABS_X_OST + j) *
++			sig = cd->pdata->frmwrk->abs[((CY_ABS_X_OST + j) *
+ 				CY_NUM_ABS_SET) + 0];
+ 			if (sig != CY_IGNORE_VALUE)
+-				input_report_abs(md->input, sig,
++				input_report_abs(cd->input, sig,
+ 					tch.abs[CY_TCH_X + j]);
+ 		}
+ 		if (si->si_ofs.tch_rec_size > CY_TMA1036_TCH_REC_SIZE) {
+@@ -909,11 +909,11 @@ static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
+ 
+ 			/* Get the extended touch fields */
+ 			for (j = 0; j < CY_NUM_EXT_TCH_FIELDS; j++) {
+-				sig = md->pdata->frmwrk->abs
++				sig = cd->pdata->frmwrk->abs
+ 					[((CY_ABS_MAJ_OST + j) *
+ 					CY_NUM_ABS_SET) + 0];
+ 				if (sig != CY_IGNORE_VALUE)
+-					input_report_abs(md->input, sig,
++					input_report_abs(cd->input, sig,
+ 						tch.abs[CY_TCH_MAJ + j]);
+ 			}
+ 		}
+@@ -940,9 +940,9 @@ static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
+ 				tch.abs[CY_TCH_E]);
+ 	}
+ 
+-	cyttsp4_final_sync(md->input, si->si_ofs.tch_abs[CY_TCH_T].max, ids);
++	cyttsp4_final_sync(cd->input, si->si_ofs.tch_abs[CY_TCH_T].max, ids);
+ 
+-	md->num_prv_tch = num_cur_tch;
++	cd->num_prv_tch = num_cur_tch;
+ 
+ 	return;
+ }
+@@ -950,9 +950,8 @@ static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
+ /* read xy_data for all current touches */
+ static int cyttsp4_xy_worker(struct cyttsp4 *cd)
+ {
+-	struct cyttsp4_mt_data *md = &cd->md;
+-	struct device *dev = &md->input->dev;
+-	struct cyttsp4_sysinfo *si = md->si;
++	struct device *dev = &cd->input->dev;
++	struct cyttsp4_sysinfo *si = cd->si;
+ 	u8 num_cur_tch;
+ 	u8 hst_mode;
+ 	u8 rep_len;
+@@ -1024,9 +1023,9 @@ static int cyttsp4_xy_worker(struct cyttsp4 *cd)
+ 	dev_vdbg(dev, "%s: extract data num_cur_tch=%d\n", __func__,
+ 		num_cur_tch);
+ 	if (num_cur_tch)
+-		cyttsp4_get_mt_touches(md, num_cur_tch);
++		cyttsp4_get_mt_touches(cd, num_cur_tch);
+ 	else
+-		cyttsp4_lift_all(md);
++		cyttsp4_lift_all(cd);
+ 
+ 	rc = 0;
+ 
+@@ -1037,21 +1036,20 @@ static int cyttsp4_xy_worker(struct cyttsp4 *cd)
+ static int cyttsp4_mt_attention(struct cyttsp4 *cd)
+ {
+ 	struct device *dev = cd->dev;
+-	struct cyttsp4_mt_data *md = &cd->md;
+ 	int rc = 0;
+ 
+-	if (!md->si)
++	if (!cd->si)
+ 		return 0;
+ 
+-	mutex_lock(&md->report_lock);
+-	if (!md->is_suspended) {
++	mutex_lock(&cd->report_lock);
++	if (!cd->is_suspended) {
+ 		/* core handles handshake */
+ 		rc = cyttsp4_xy_worker(cd);
+ 	} else {
+ 		dev_vdbg(dev, "%s: Ignoring report while suspended\n",
+ 			__func__);
+ 	}
+-	mutex_unlock(&md->report_lock);
++	mutex_unlock(&cd->report_lock);
+ 	if (rc < 0)
+ 		dev_err(dev, "%s: xy_worker error r=%d\n", __func__, rc);
+ 
+@@ -1222,7 +1220,7 @@ static irqreturn_t cyttsp4_irq(int irq, void *handle)
+ 	 * IRQF_TRIGGER_LOW in order to delay until the
+ 	 * device completes isr deassert
+ 	 */
+-	udelay(cd->cpdata->level_irq_udelay);
++	udelay(cd->pdata->level_irq_udelay);
+ 
+ cyttsp4_irq_exit:
+ 	mutex_unlock(&cd->system_lock);
+@@ -1527,9 +1525,9 @@ static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
+ 	}
+ 	dev_vdbg(cd->dev, "%s: write DEEP SLEEP succeeded\n", __func__);
+ 
+-	if (cd->cpdata->power) {
++	if (cd->pdata->power) {
+ 		dev_dbg(cd->dev, "%s: Power down HW\n", __func__);
+-		rc = cd->cpdata->power(cd->cpdata, 0, cd->dev, &cd->ignore_irq);
++		rc = cd->pdata->power(cd->pdata, 0, cd->dev, &cd->ignore_irq);
+ 	} else {
+ 		dev_dbg(cd->dev, "%s: No power function\n", __func__);
+ 		rc = 0;
+@@ -1644,7 +1642,7 @@ static int cyttsp4_startup_(struct cyttsp4 *cd)
+ 		goto exit;
+ 	}
+ 
+-	cyttsp4_lift_all(&cd->md);
++	cyttsp4_lift_all(cd);
+ 
+ 	/* restore to sleep if was suspended */
+ 	mutex_lock(&cd->system_lock);
+@@ -1766,9 +1764,9 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 	cd->int_status |= CY_INT_AWAKE;
+ 	cd->sleep_state = SS_WAKING;
+ 
+-	if (cd->cpdata->power) {
++	if (cd->pdata->power) {
+ 		dev_dbg(dev, "%s: Power up HW\n", __func__);
+-		rc = cd->cpdata->power(cd->cpdata, 1, dev, &cd->ignore_irq);
++		rc = cd->pdata->power(cd->pdata, 1, dev, &cd->ignore_irq);
+ 	} else {
+ 		dev_dbg(dev, "%s: No power function\n", __func__);
+ 		rc = -ENOSYS;
+@@ -1830,10 +1828,9 @@ static int cyttsp4_core_wake(struct cyttsp4 *cd)
+ static int cyttsp4_core_suspend(struct device *dev)
+ {
+ 	struct cyttsp4 *cd = dev_get_drvdata(dev);
+-	struct cyttsp4_mt_data *md = &cd->md;
+ 	int rc;
+ 
+-	md->is_suspended = true;
++	cd->is_suspended = true;
+ 
+ 	rc = cyttsp4_core_sleep(cd);
+ 	if (rc < 0) {
+@@ -1846,10 +1843,9 @@ static int cyttsp4_core_suspend(struct device *dev)
+ static int cyttsp4_core_resume(struct device *dev)
+ {
+ 	struct cyttsp4 *cd = dev_get_drvdata(dev);
+-	struct cyttsp4_mt_data *md = &cd->md;
+ 	int rc;
+ 
+-	md->is_suspended = false;
++	cd->is_suspended = false;
+ 
+ 	rc = cyttsp4_core_wake(cd);
+ 	if (rc < 0) {
+@@ -1871,18 +1867,17 @@ static int cyttsp4_mt_open(struct input_dev *input)
+ 
+ static void cyttsp4_mt_close(struct input_dev *input)
+ {
+-	struct cyttsp4_mt_data *md = input_get_drvdata(input);
+-	mutex_lock(&md->report_lock);
+-	if (!md->is_suspended)
++	struct cyttsp4 *cd = input_get_drvdata(input);
++	mutex_lock(&cd->report_lock);
++	if (!cd->is_suspended)
+ 		pm_runtime_put(input->dev.parent);
+-	mutex_unlock(&md->report_lock);
++	mutex_unlock(&cd->report_lock);
+ }
+ 
+ 
+ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ {
+ 	struct device *dev = cd->dev;
+-	struct cyttsp4_mt_data *md = &cd->md;
+ 	int signal = CY_IGNORE_VALUE;
+ 	int max_x, max_y, max_p, min, max;
+ 	int max_x_tmp, max_y_tmp;
+@@ -1890,32 +1885,32 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 	int rc;
+ 
+ 	dev_vdbg(dev, "%s: Initialize event signals\n", __func__);
+-	__set_bit(EV_ABS, md->input->evbit);
+-	__set_bit(EV_REL, md->input->evbit);
+-	__set_bit(EV_KEY, md->input->evbit);
++	__set_bit(EV_ABS, cd->input->evbit);
++	__set_bit(EV_REL, cd->input->evbit);
++	__set_bit(EV_KEY, cd->input->evbit);
+ 
+-	max_x_tmp = md->si->si_ofs.max_x;
+-	max_y_tmp = md->si->si_ofs.max_y;
++	max_x_tmp = cd->si->si_ofs.max_x;
++	max_y_tmp = cd->si->si_ofs.max_y;
+ 
+ 	/* get maximum values from the sysinfo data */
+-	if (md->pdata->flags & CY_FLAG_FLIP) {
++	if (cd->pdata->flags & CY_FLAG_FLIP) {
+ 		max_x = max_y_tmp - 1;
+ 		max_y = max_x_tmp - 1;
+ 	} else {
+ 		max_x = max_x_tmp - 1;
+ 		max_y = max_y_tmp - 1;
+ 	}
+-	max_p = md->si->si_ofs.max_p;
++	max_p = cd->si->si_ofs.max_p;
+ 
+ 	/* set event signal capabilities */
+-	for (i = 0; i < (md->pdata->frmwrk->size / CY_NUM_ABS_SET); i++) {
+-		signal = md->pdata->frmwrk->abs
++	for (i = 0; i < (cd->pdata->frmwrk->size / CY_NUM_ABS_SET); i++) {
++		signal = cd->pdata->frmwrk->abs
+ 			[(i * CY_NUM_ABS_SET) + CY_SIGNAL_OST];
+ 		if (signal != CY_IGNORE_VALUE) {
+-			__set_bit(signal, md->input->absbit);
+-			min = md->pdata->frmwrk->abs
++			__set_bit(signal, cd->input->absbit);
++			min = cd->pdata->frmwrk->abs
+ 				[(i * CY_NUM_ABS_SET) + CY_MIN_OST];
+-			max = md->pdata->frmwrk->abs
++			max = cd->pdata->frmwrk->abs
+ 				[(i * CY_NUM_ABS_SET) + CY_MAX_OST];
+ 			if (i == CY_ABS_ID_OST) {
+ 				/* shift track ids down to start at 0 */
+@@ -1927,23 +1922,23 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 				max = max_y;
+ 			else if (i == CY_ABS_P_OST)
+ 				max = max_p;
+-			input_set_abs_params(md->input, signal, min, max,
+-				md->pdata->frmwrk->abs
++			input_set_abs_params(cd->input, signal, min, max,
++				cd->pdata->frmwrk->abs
+ 				[(i * CY_NUM_ABS_SET) + CY_FUZZ_OST],
+-				md->pdata->frmwrk->abs
++				cd->pdata->frmwrk->abs
+ 				[(i * CY_NUM_ABS_SET) + CY_FLAT_OST]);
+ 			dev_dbg(dev, "%s: register signal=%02X min=%d max=%d\n",
+ 				__func__, signal, min, max);
+ 			if ((i == CY_ABS_ID_OST) &&
+-				(md->si->si_ofs.tch_rec_size <
++				(cd->si->si_ofs.tch_rec_size <
+ 				CY_TMA4XX_TCH_REC_SIZE))
+ 				break;
+ 		}
+ 	}
+ 
+-	input_mt_init_slots(md->input, md->si->si_ofs.tch_abs[CY_TCH_T].max,
++	input_mt_init_slots(cd->input, cd->si->si_ofs.tch_abs[CY_TCH_T].max,
+ 			INPUT_MT_DIRECT);
+-	rc = input_register_device(md->input);
++	rc = input_register_device(cd->input);
+ 	if (rc < 0)
+ 		dev_err(dev, "%s: Error, failed register input device r=%d\n",
+ 			__func__, rc);
+@@ -1953,34 +1948,31 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ static int cyttsp4_mt_probe(struct cyttsp4 *cd)
+ {
+ 	struct device *dev = cd->dev;
+-	struct cyttsp4_mt_data *md = &cd->md;
+-	struct cyttsp4_mt_platform_data *pdata = cd->pdata->mt_pdata;
+ 	int rc = 0;
+ 
+-	mutex_init(&md->report_lock);
+-	md->pdata = pdata;
++	mutex_init(&cd->report_lock);
+ 	/* Create the input device and register it. */
+ 	dev_vdbg(dev, "%s: Create the input device and register it\n",
+ 		__func__);
+-	md->input = input_allocate_device();
+-	if (md->input == NULL) {
++	cd->input = input_allocate_device();
++	if (cd->input == NULL) {
+ 		dev_err(dev, "%s: Error, failed to allocate input device\n",
+ 			__func__);
+ 		rc = -ENOSYS;
+ 		goto error_alloc_failed;
+ 	}
+ 
+-	md->input->name = pdata->inp_dev_name;
+-	scnprintf(md->phys, sizeof(md->phys)-1, "%s", dev_name(dev));
+-	md->input->phys = md->phys;
+-	md->input->id.bustype = cd->bus_ops->bustype;
+-	md->input->dev.parent = dev;
+-	md->input->open = cyttsp4_mt_open;
+-	md->input->close = cyttsp4_mt_close;
+-	input_set_drvdata(md->input, md);
++	cd->input->name = cd->pdata->inp_dev_name;
++	scnprintf(cd->phys, sizeof(cd->phys)-1, "%s", dev_name(dev));
++	cd->input->phys = cd->phys;
++	cd->input->id.bustype = cd->bus_ops->bustype;
++	cd->input->dev.parent = dev;
++	cd->input->open = cyttsp4_mt_open;
++	cd->input->close = cyttsp4_mt_close;
++	input_set_drvdata(cd->input, cd);
+ 
+ 	/* get sysinfo */
+-	md->si = &cd->sysinfo;
++	cd->si = &cd->sysinfo;
+ 
+ 	rc = cyttsp4_setup_input_device(cd);
+ 	if (rc)
+@@ -1989,7 +1981,7 @@ static int cyttsp4_mt_probe(struct cyttsp4 *cd)
+ 	return 0;
+ 
+ error_init_input:
+-	input_free_device(md->input);
++	input_free_device(cd->input);
+ error_alloc_failed:
+ 	dev_err(dev, "%s failed.\n", __func__);
+ 	return rc;
+@@ -2003,7 +1995,7 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	unsigned long irq_flags;
+ 	int rc = 0;
+ 
+-	if (!pdata || !pdata->core_pdata || !pdata->mt_pdata) {
++	if (!pdata) {
+ 		dev_err(dev, "%s: Missing platform data\n", __func__);
+ 		rc = -ENODEV;
+ 		goto error_no_pdata;
+@@ -2026,7 +2018,6 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	/* Initialize device info */
+ 	cd->dev = dev;
+ 	cd->pdata = pdata;
+-	cd->cpdata = pdata->core_pdata;
+ 	cd->bus_ops = ops;
+ 
+ 	/* Initialize mutexes and spinlocks */
+@@ -2041,7 +2032,7 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	INIT_WORK(&cd->watchdog_work, cyttsp4_watchdog_work);
+ 
+ 	/* Initialize IRQ */
+-	cd->irq = gpio_to_irq(cd->cpdata->irq_gpio);
++	cd->irq = gpio_to_irq(cd->pdata->irq_gpio);
+ 	if (cd->irq < 0) {
+ 		rc = -EINVAL;
+ 		goto error_free_xfer;
+@@ -2050,9 +2041,9 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	dev_set_drvdata(dev, cd);
+ 
+ 	/* Call platform init function */
+-	if (cd->cpdata->init) {
++	if (cd->pdata->init) {
+ 		dev_dbg(cd->dev, "%s: Init HW\n", __func__);
+-		rc = cd->cpdata->init(cd->cpdata, 1, cd->dev);
++		rc = cd->pdata->init(cd->pdata, 1, cd->dev);
+ 	} else {
+ 		dev_dbg(cd->dev, "%s: No HW INIT function\n", __func__);
+ 		rc = 0;
+@@ -2061,7 +2052,7 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 		dev_err(cd->dev, "%s: HW Init fail r=%d\n", __func__, rc);
+ 
+ 	dev_dbg(dev, "%s: initialize threaded irq=%d\n", __func__, cd->irq);
+-	if (cd->cpdata->level_irq_udelay > 0)
++	if (cd->pdata->level_irq_udelay > 0)
+ 		/* use level triggered interrupts */
+ 		irq_flags = IRQF_TRIGGER_LOW | IRQF_ONESHOT;
+ 	else
+@@ -2108,8 +2099,8 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	cyttsp4_free_si_ptrs(cd);
+ 	free_irq(cd->irq, cd);
+ error_request_irq:
+-	if (cd->cpdata->init)
+-		cd->cpdata->init(cd->cpdata, 0, dev);
++	if (cd->pdata->init)
++		cd->pdata->init(cd->pdata, 0, dev);
+ error_free_xfer:
+ 	kfree(cd->xfer_buf);
+ error_free_cd:
+@@ -2121,17 +2112,17 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ }
+ EXPORT_SYMBOL_GPL(cyttsp4_probe);
+ 
+-static void cyttsp4_mt_release(struct cyttsp4_mt_data *md)
++static void cyttsp4_mt_release(struct cyttsp4 *cd)
+ {
+-	input_unregister_device(md->input);
+-	input_set_drvdata(md->input, NULL);
++	input_unregister_device(cd->input);
++	input_set_drvdata(cd->input, NULL);
+ }
+ 
+ int cyttsp4_remove(struct cyttsp4 *cd)
+ {
+ 	struct device *dev = cd->dev;
+ 
+-	cyttsp4_mt_release(&cd->md);
++	cyttsp4_mt_release(cd);
+ 
+ 	/*
+ 	 * Suspend the device before freeing the startup_work and stopping
+@@ -2145,8 +2136,8 @@ int cyttsp4_remove(struct cyttsp4 *cd)
+ 	cyttsp4_stop_wd_timer(cd);
+ 
+ 	free_irq(cd->irq, cd);
+-	if (cd->cpdata->init)
+-		cd->cpdata->init(cd->cpdata, 0, dev);
++	if (cd->pdata->init)
++		cd->pdata->init(cd->pdata, 0, dev);
+ 	cyttsp4_free_si_ptrs(cd);
+ 	kfree(cd);
+ 	return 0;
+diff --git a/drivers/input/touchscreen/cyttsp4_core.h b/drivers/input/touchscreen/cyttsp4_core.h
+index 6262f6e45075..05fb30058d87 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.h
++++ b/drivers/input/touchscreen/cyttsp4_core.h
+@@ -305,16 +305,6 @@ struct cyttsp4_sysinfo {
+ 	u8 *xy_data;			/* operational touch regs */
+ };
+ 
+-struct cyttsp4_mt_data {
+-	struct cyttsp4_mt_platform_data *pdata;
+-	struct cyttsp4_sysinfo *si;
+-	struct input_dev *input;
+-	struct mutex report_lock;
+-	bool is_suspended;
+-	char phys[NAME_MAX];
+-	int num_prv_tch;
+-};
+-
+ struct cyttsp4 {
+ 	struct device *dev;
+ 	struct mutex system_lock;
+@@ -333,9 +323,13 @@ struct cyttsp4 {
+ 	int exclusive_waits;
+ 	atomic_t ignore_irq;
+ 	bool invalid_touch_app;
+-	struct cyttsp4_mt_data md;
++	struct cyttsp4_sysinfo *si;
++	struct input_dev *input;
++	struct mutex report_lock;
++	bool is_suspended;
++	char phys[NAME_MAX];
++	int num_prv_tch;
+ 	struct cyttsp4_platform_data *pdata;
+-	struct cyttsp4_core_platform_data *cpdata;
+ 	const struct cyttsp4_bus_ops *bus_ops;
+ 	u8 *xfer_buf;
+ #ifdef VERBOSE_DEBUG
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index c54160c17b0b..1f945aa2466e 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -27,36 +27,30 @@ struct touch_framework {
+ 	uint8_t         enable_vkeys;
+ } __packed;
+ 
+-struct cyttsp4_mt_platform_data {
+-	struct touch_framework *frmwrk;
+-	unsigned short flags;
+-	char const *inp_dev_name;
+-};
+-
+ struct cyttsp4_virtual_key {
+ 	int code;
+ };
+ 
+-struct cyttsp4_core_platform_data {
++struct cyttsp4_platform_data {
++	char const *inp_dev_name;
++	unsigned short flags;
++
+ 	int irq_gpio;
+ 	int rst_gpio;
+ 	int level_irq_udelay;
+-	int (*xres)(struct cyttsp4_core_platform_data *pdata,
++	int (*xres)(struct cyttsp4_platform_data *pdata,
+ 		struct device *dev);
+-	int (*init)(struct cyttsp4_core_platform_data *pdata,
++	int (*init)(struct cyttsp4_platform_data *pdata,
+ 		int on, struct device *dev);
+-	int (*power)(struct cyttsp4_core_platform_data *pdata,
++	int (*power)(struct cyttsp4_platform_data *pdata,
+ 		int on, struct device *dev, atomic_t *ignore_irq);
+-	int (*irq_stat)(struct cyttsp4_core_platform_data *pdata,
++	int (*irq_stat)(struct cyttsp4_platform_data *pdata,
+ 		struct device *dev);
+ 
++	struct touch_framework *frmwrk;
++
+ 	int n_keys;
+ 	struct cyttsp4_virtual_key* keys;
+ };
+ 
+-struct cyttsp4_platform_data {
+-	struct cyttsp4_core_platform_data *core_pdata;
+-	struct cyttsp4_mt_platform_data *mt_pdata;
+-};
+-
+ #endif /* _CYTTSP4_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch
new file mode 100644
index 000000000000..db0c0f8a82df
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch
@@ -0,0 +1,125 @@
+From 3744df7593d6e48c591f82c62d43c5c4f0bb417b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 1 Oct 2019 02:21:43 +0200
+Subject: input: cyttsp4: Restart on wakeup (wakeup by I2C read doesn't work)
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 30 ++++++++++++++++--------
+ 1 file changed, 20 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index c2781ca405a6..882639b8124d 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -28,7 +28,7 @@
+ #define CY_CORE_SLEEP_REQUEST_EXCLUSIVE_TIMEOUT	5000
+ #define CY_CORE_MODE_CHANGE_TIMEOUT		1000
+ #define CY_CORE_RESET_AND_WAIT_TIMEOUT		500
+-#define CY_CORE_WAKEUP_TIMEOUT			50
++#define CY_CORE_WAKEUP_TIMEOUT			250
+ 
+ #define CY_CORE_STARTUP_RETRY_COUNT		3
+ 
+@@ -139,13 +139,11 @@ static int cyttsp4_hw_reset(struct cyttsp4 *cd)
+ 		return cyttsp4_hw_soft_reset(cd);
+ 
+ 	gpiod_set_value_cansleep(cd->reset_gpio, 1);
+-	msleep(20);
+-
+-	gpiod_set_value_cansleep(cd->reset_gpio, 0);
+ 	msleep(40);
+ 
+-	gpiod_set_value_cansleep(cd->reset_gpio, 1);
++	gpiod_set_value_cansleep(cd->reset_gpio, 0);
+ 	msleep(20);
++
+ 	return 0;
+ }
+ 
+@@ -1525,12 +1523,14 @@ static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
+ 	}
+ 	dev_vdbg(cd->dev, "%s: write DEEP SLEEP succeeded\n", __func__);
+ 
++	/*
+ 	rc = cyttsp4_set_power(cd, 0);
+ 	if (rc < 0) {
+ 		dev_err(cd->dev, "%s: HW Power down fails r=%d\n",
+ 				__func__, rc);
+ 		goto error;
+ 	}
++          */
+ 
+ 	/* Give time to FW to sleep */
+ 	msleep(50);
+@@ -1748,6 +1748,7 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 	u8 mode;
+ 	int t;
+ 
++#if 0
+ 	/* Already woken? */
+ 	mutex_lock(&cd->system_lock);
+ 	if (cd->sleep_state == SS_SLEEP_OFF) {
+@@ -1765,7 +1766,8 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 				__func__, rc);
+ 
+ 		/* Initiate a read transaction to wake up */
+-		cyttsp4_adap_read(cd, CY_REG_BASE, sizeof(mode), &mode);
++		rc = cyttsp4_adap_read(cd, CY_REG_BASE, sizeof(mode), &mode);
++		dev_err(dev, "Waking up by read rc=%d\n", rc);
+ 	} else
+ 		dev_vdbg(cd->dev, "%s: HW power up succeeds\n",
+ 			__func__);
+@@ -1782,7 +1784,13 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 		cyttsp4_queue_startup_(cd);
+ 		mutex_unlock(&cd->system_lock);
+ 	}
+-
++#else
++	mutex_lock(&cd->system_lock);
++	cd->int_status &= ~CY_INT_AWAKE;
++	/* Try starting up */
++	cyttsp4_queue_startup_(cd);
++	mutex_unlock(&cd->system_lock);
++#endif
+ 	mutex_lock(&cd->system_lock);
+ 	cd->sleep_state = SS_SLEEP_OFF;
+ 	mutex_unlock(&cd->system_lock);
+@@ -1992,6 +2000,7 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 		return ERR_PTR(-ENOMEM);
+ 	}
+ 
++	cd->irq = irq;
+ 	cd->signals = cyttsp4_default_signals;
+ 	cd->n_signals = ARRAY_SIZE(cyttsp4_default_signals);
+ 
+@@ -2005,7 +2014,8 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	cd->vdd_supply = devm_regulator_get(dev, "vdd");
+ 	if (IS_ERR(cd->vdd_supply)) {
+ 		rc = PTR_ERR(cd->vdd_supply);
+-		dev_err(dev, "can't get vdd power (%d)\n", rc);
++		if (rc != -EPROBE_DEFER)
++			dev_err(dev, "can't get vdd power (%d)\n", rc);
+ 		return ERR_PTR(rc);
+ 	}
+ 
+@@ -2019,14 +2029,14 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	if (IS_ERR(cd->reset_gpio)) {
+ 		rc = PTR_ERR(cd->reset_gpio);
+ 		dev_err(dev, "can't get reset gpio (%d)\n", rc);
+-		return ERR_PTR(rc);
++		goto error_disable_vdd;
+ 	}
+ 
+ 	cd->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ 	if (IS_ERR(cd->reset_gpio)) {
+ 		rc = PTR_ERR(cd->reset_gpio);
+ 		dev_err(dev, "can't get reset gpio (%d)\n", rc);
+-		return ERR_PTR(rc);
++		goto error_disable_vdd;
+ 	}
+ 
+ 	cd->xfer_buf = devm_kzalloc(dev, xfer_buf_size, GFP_KERNEL);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch
new file mode 100644
index 000000000000..b511522c63c8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch
@@ -0,0 +1,64 @@
+From 61b51598a9af28c73a2673bffb53c6bcdb6961d9 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 6 Mar 2023 01:17:09 +0100
+Subject: input: cyttsp4: Use i2c/spi names directly in the driver
+
+Platform data is going to be removed.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_i2c.c | 4 ++--
+ drivers/input/touchscreen/cyttsp4_spi.c | 2 +-
+ include/linux/platform_data/cyttsp4.h   | 2 --
+ 3 files changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_i2c.c b/drivers/input/touchscreen/cyttsp4_i2c.c
+index da32c151def5..5b38a4f34209 100644
+--- a/drivers/input/touchscreen/cyttsp4_i2c.c
++++ b/drivers/input/touchscreen/cyttsp4_i2c.c
+@@ -50,14 +50,14 @@ static void cyttsp4_i2c_remove(struct i2c_client *client)
+ }
+ 
+ static const struct i2c_device_id cyttsp4_i2c_id[] = {
+-	{ CYTTSP4_I2C_NAME },
++	{ "cyttsp4_i2c_adapter" },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(i2c, cyttsp4_i2c_id);
+ 
+ static struct i2c_driver cyttsp4_i2c_driver = {
+ 	.driver = {
+-		.name	= CYTTSP4_I2C_NAME,
++		.name	= "cyttsp4_i2c_adapter",
+ 		.pm	= pm_ptr(&cyttsp4_pm_ops),
+ 	},
+ 	.probe		= cyttsp4_i2c_probe,
+diff --git a/drivers/input/touchscreen/cyttsp4_spi.c b/drivers/input/touchscreen/cyttsp4_spi.c
+index 944fbbe9113e..f3cca8c9c119 100644
+--- a/drivers/input/touchscreen/cyttsp4_spi.c
++++ b/drivers/input/touchscreen/cyttsp4_spi.c
+@@ -172,7 +172,7 @@ static void cyttsp4_spi_remove(struct spi_device *spi)
+ 
+ static struct spi_driver cyttsp4_spi_driver = {
+ 	.driver = {
+-		.name	= CYTTSP4_SPI_NAME,
++		.name	= "cyttsp4_spi_adapter",
+ 		.pm	= pm_ptr(&cyttsp4_pm_ops),
+ 	},
+ 	.probe  = cyttsp4_spi_probe,
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index 1b5b30796e43..e718d2204ce7 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -16,8 +16,6 @@
+ #define _CYTTSP4_H_
+ 
+ #define CYTTSP4_MT_NAME "cyttsp4_mt"
+-#define CYTTSP4_I2C_NAME "cyttsp4_i2c_adapter"
+-#define CYTTSP4_SPI_NAME "cyttsp4_spi_adapter"
+ 
+ #define CY_TOUCH_SETTINGS_MAX 32
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
new file mode 100644
index 000000000000..2a139100c250
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
@@ -0,0 +1,76 @@
+From 6ba74016b76a9c170d32608d5b7322e49a671ca1 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 8 Sep 2023 01:07:30 +0200
+Subject: input: gpio-vibra: Allow to use vcc-supply alone to control the
+ vibrator
+
+Make enable-gpio optional to allow using this driver with boards that
+have vibrator connected to a power supply without intermediate gpio
+based enable circuitry.
+
+Also avoid a case where neither regulator nor enable gpio is specified,
+and bail out in probe in such a case.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/misc/gpio-vibra.c | 25 ++++++++++++++++++-------
+ 1 file changed, 18 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/input/misc/gpio-vibra.c b/drivers/input/misc/gpio-vibra.c
+index ad44b4d18a2a..de24e28458b0 100644
+--- a/drivers/input/misc/gpio-vibra.c
++++ b/drivers/input/misc/gpio-vibra.c
+@@ -39,7 +39,7 @@ static int gpio_vibrator_start(struct gpio_vibrator *vibrator)
+ 	struct device *pdev = vibrator->input->dev.parent;
+ 	int err;
+ 
+-	if (!vibrator->vcc_on) {
++	if (vibrator->vcc && !vibrator->vcc_on) {
+ 		err = regulator_enable(vibrator->vcc);
+ 		if (err) {
+ 			dev_err(pdev, "failed to enable regulator: %d\n", err);
+@@ -57,7 +57,7 @@ static void gpio_vibrator_stop(struct gpio_vibrator *vibrator)
+ {
+ 	gpiod_set_value_cansleep(vibrator->gpio, 0);
+ 
+-	if (vibrator->vcc_on) {
++	if (vibrator->vcc && vibrator->vcc_on) {
+ 		regulator_disable(vibrator->vcc);
+ 		vibrator->vcc_on = false;
+ 	}
+@@ -112,16 +112,27 @@ static int gpio_vibrator_probe(struct platform_device *pdev)
+ 	if (!vibrator->input)
+ 		return -ENOMEM;
+ 
+-	vibrator->vcc = devm_regulator_get(&pdev->dev, "vcc");
+-	if (IS_ERR(vibrator->vcc))
+-		return dev_err_probe(&pdev->dev, PTR_ERR(vibrator->vcc),
++	vibrator->vcc = devm_regulator_get_optional(&pdev->dev, "vcc");
++	err = PTR_ERR_OR_ZERO(vibrator->vcc);
++	if (err == -ENODEV) {
++		vibrator->vcc = NULL;
++	} else if (err) {
++		return dev_err_probe(&pdev->dev, err,
+ 				     "Failed to request regulator\n");
++	}
+ 
+-	vibrator->gpio = devm_gpiod_get(&pdev->dev, "enable", GPIOD_OUT_LOW);
+-	if (IS_ERR(vibrator->gpio))
++	vibrator->gpio = devm_gpiod_get_optional(&pdev->dev, "enable",
++						 GPIOD_OUT_LOW);
++	err = PTR_ERR_OR_ZERO(vibrator->gpio);
++	if (err)
+ 		return dev_err_probe(&pdev->dev, PTR_ERR(vibrator->gpio),
+ 				     "Failed to request main gpio\n");
+ 
++	if (!vibrator->vcc && !vibrator->gpio) {
++		dev_err(&pdev->dev, "Neither gpio nor regulator provided\n");
++		return -EINVAL;
++	}
++
+ 	INIT_WORK(&vibrator->play_work, gpio_vibrator_play_work);
+ 
+ 	vibrator->input->name = "gpio-vibrator";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
new file mode 100644
index 000000000000..0a584803a022
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
@@ -0,0 +1,347 @@
+From 90051ab5fd4222a4c7a562aae3eeff285bab4108 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 4 Feb 2021 00:55:20 +0100
+Subject: leds: axp20x: Support charger LED on AXP20x like PMICs
+
+There is single LED that can be turned on and off by the user, or set to
+be controlled by the charger in 2 different modes.
+
+The driver initializes the LED to be controlled by the charger, but
+allows to switch it to user control, and change the mode of charging
+indication via a sysfs.
+
+The driver was developed on AXP813, but should work on other PMICs like
+that without changes.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/leds/Kconfig       |  15 +++
+ drivers/leds/Makefile      |   1 +
+ drivers/leds/leds-axp20x.c | 255 +++++++++++++++++++++++++++++++++++++
+ drivers/mfd/axp20x.c       |   3 +
+ 4 files changed, 274 insertions(+)
+ create mode 100644 drivers/leds/leds-axp20x.c
+
+diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
+index 05e6af88b88c..5c6993777c68 100644
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -920,6 +920,14 @@ config LEDS_IP30
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called leds-ip30.
+ 
++config LEDS_SGM3140
++	tristate "LED support for the SGM3140"
++	depends on LEDS_CLASS_FLASH
++	depends on V4L2_FLASH_LED_CLASS || !V4L2_FLASH_LED_CLASS
++	help
++	  This option enables support for the SGM3140 500mA Buck/Boost Charge
++	  Pump LED Driver.
++
+ config LEDS_ACER_A500
+ 	tristate "Power button LED support for Acer Iconia Tab A500"
+ 	depends on LEDS_CLASS && MFD_ACER_A500_EC
+@@ -927,6 +935,13 @@ config LEDS_ACER_A500
+ 	  This option enables support for the Power Button LED of
+ 	  Acer Iconia Tab A500.
+ 
++config LEDS_AXP20X
++	tristate "Charger LED support for AXP20X-like PMICs (AXP813, ...)"
++	depends on LEDS_CLASS && MFD_AXP20X
++	help
++	  This option enables support for on-chip LED driver on
++	  AXP20X-like PMICs.
++
+ source "drivers/leds/blink/Kconfig"
+ 
+ comment "Flash and Torch LED drivers"
+diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
+index effdfc6f1e95..9e1b57baf066 100644
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -90,6 +90,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA)		+= leds-turris-omnia.o
+ obj-$(CONFIG_LEDS_WM831X_STATUS)	+= leds-wm831x-status.o
+ obj-$(CONFIG_LEDS_WM8350)		+= leds-wm8350.o
+ obj-$(CONFIG_LEDS_WRAP)			+= leds-wrap.o
++obj-$(CONFIG_LEDS_AXP20X)		+= leds-axp20x.o
+ 
+ # Kinetic ExpressWire Protocol
+ obj-$(CONFIG_LEDS_EXPRESSWIRE)		+= leds-expresswire.o
+diff --git a/drivers/leds/leds-axp20x.c b/drivers/leds/leds-axp20x.c
+new file mode 100644
+index 000000000000..fd94930f6433
+--- /dev/null
++++ b/drivers/leds/leds-axp20x.c
+@@ -0,0 +1,255 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * LED Driver for X-Powers AXP813 PMIC and similar.
++ *
++ * Copyright(c) 2020 Ondrej Jirman <megi@xff.cz>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/leds.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/mfd/axp20x.h>
++
++#define AXP20X_CHGLED_CTRL_MASK		BIT(3)
++#define AXP20X_CHGLED_CTRL_CHARGER	BIT(3)
++#define AXP20X_CHGLED_CTRL_USER		0
++
++#define AXP20X_CHRG_CTRL2_MODE		BIT(4)
++
++#define AXP20X_CHGLED_USER_STATE_MASK		GENMASK(5, 4)
++#define AXP20X_CHGLED_USER_STATE_OFF		(0 << 4)
++#define AXP20X_CHGLED_USER_STATE_BLINK_SLOW	(1 << 4)
++#define AXP20X_CHGLED_USER_STATE_BLINK_FAST	(2 << 4)
++#define AXP20X_CHGLED_USER_STATE_ON		(3 << 4)
++
++static struct led_hw_trigger_type axp20x_charger_led_trigger_type;
++
++struct axp20x_led {
++	struct led_classdev cdev;
++	struct regmap *regmap;
++};
++
++static int axp20x_led_set(struct led_classdev *led_cdev,
++			   enum led_brightness value)
++{
++	struct axp20x_led *led =
++			container_of(led_cdev, struct axp20x_led, cdev);
++	unsigned int val;
++
++	val = value == LED_OFF ? AXP20X_CHGLED_USER_STATE_OFF :
++		AXP20X_CHGLED_USER_STATE_ON;
++
++	return regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
++				  AXP20X_CHGLED_USER_STATE_MASK, val);
++
++}
++
++static int axp20x_set_charger_control(struct led_classdev *led_cdev, bool on)
++{
++	struct axp20x_led *led = container_of(led_cdev, struct axp20x_led, cdev);
++
++	return regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
++				  AXP20X_CHGLED_CTRL_MASK,
++				  on ? AXP20X_CHGLED_CTRL_CHARGER :
++				  AXP20X_CHGLED_CTRL_USER);
++}
++
++static int axp20x_trig_charger_activate(struct led_classdev *led_cdev)
++{
++	return axp20x_set_charger_control(led_cdev, true);
++}
++
++static void axp20x_trig_charger_deactivate(struct led_classdev *led_cdev)
++{
++	axp20x_set_charger_control(led_cdev, false);
++}
++
++static ssize_t charger_mode_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	struct led_classdev *led_cdev = led_trigger_get_led(dev);
++	struct axp20x_led *led = container_of(led_cdev, struct axp20x_led, cdev);
++	unsigned int val;
++	int ret;
++
++	ret = regmap_read(led->regmap, AXP20X_CHRG_CTRL2, &val);
++	if (ret)
++		return ret;
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 val & AXP20X_CHRG_CTRL2_MODE ? 1 : 0);
++}
++
++static ssize_t charger_mode_store(struct device *dev,
++				  struct device_attribute *attr,
++				  const char *buf, size_t len)
++{
++	struct led_classdev *led_cdev = led_trigger_get_led(dev);
++	struct axp20x_led *led = container_of(led_cdev, struct axp20x_led, cdev);
++	unsigned int mode;
++	int ret;
++
++	ret = kstrtouint(buf, 0, &mode);
++	if (ret)
++		return ret;
++
++	if (mode > 1)
++		return -ERANGE;
++
++	ret = regmap_update_bits(led->regmap, AXP20X_CHRG_CTRL2,
++				 AXP20X_CHRG_CTRL2_MODE,
++				 mode ? AXP20X_CHRG_CTRL2_MODE : 0);
++	if (ret)
++		return ret;
++
++	return len;
++}
++static DEVICE_ATTR_RW(charger_mode);
++
++static struct attribute *axp20x_led_attrs[] = {
++	&dev_attr_charger_mode.attr,
++	NULL,
++};
++
++ATTRIBUTE_GROUPS(axp20x_led);
++
++static struct led_trigger axp20x_charger_led_trigger = {
++	.name		= "charger",
++	.trigger_type	= &axp20x_charger_led_trigger_type,
++	.activate	= axp20x_trig_charger_activate,
++	.deactivate	= axp20x_trig_charger_deactivate,
++	.groups		= axp20x_led_groups,
++};
++
++static int axp20x_led_probe(struct platform_device *pdev)
++{
++	struct axp20x_dev *axp20x;
++	struct axp20x_led *led;
++	unsigned int val;
++	int ret;
++
++	if (!of_device_is_available(pdev->dev.of_node))
++		return -ENODEV;
++
++	axp20x = dev_get_drvdata(pdev->dev.parent);
++	if (!axp20x)
++		return -EINVAL;
++
++	led = devm_kzalloc(&pdev->dev,
++			   sizeof(struct axp20x_led),
++			   GFP_KERNEL);
++	if (!led)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, led);
++
++	led->regmap = axp20x->regmap;
++
++	led->cdev.name = "axp20x-chgarger-led";
++	led->cdev.brightness_set_blocking = axp20x_led_set;
++	led->cdev.brightness = LED_OFF;
++	led->cdev.max_brightness = 1;
++	led->cdev.trigger_type = &axp20x_charger_led_trigger_type;
++
++	ret = regmap_read(led->regmap, AXP20X_OFF_CTRL, &val);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to read charger control status\n");
++		return ret;
++	}
++
++	if ((val & AXP20X_CHGLED_CTRL_MASK) == AXP20X_CHGLED_CTRL_CHARGER)
++		led->cdev.default_trigger = axp20x_charger_led_trigger.name;
++
++	ret = devm_led_classdev_register(pdev->dev.parent, &led->cdev);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to register led %s\n",
++			led->cdev.name);
++		return ret;
++	}
++
++	ret = regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
++				 AXP20X_CHGLED_CTRL_MASK,
++				 AXP20X_CHGLED_CTRL_CHARGER);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to enable charger control\n");
++		return ret;
++	}
++
++	ret = axp20x_led_set(&led->cdev, led->cdev.brightness);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to init led brightness\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static void axp20x_led_shutdown(struct platform_device *pdev)
++{
++	struct axp20x_led *led = platform_get_drvdata(pdev);
++
++	/* On shutdown, we want to give LED control back to the PMIC,
++	 * so that it doesn't stay on, while the system is off.
++	 */
++
++	axp20x_led_set(&led->cdev, LED_OFF);
++	axp20x_set_charger_control(&led->cdev, true);
++}
++
++static int axp20x_led_remove(struct platform_device *pdev)
++{
++	axp20x_led_shutdown(pdev);
++
++	return 0;
++}
++
++static const struct of_device_id axp20x_leds_of_match[] = {
++	{ .compatible = "x-powers,axp813-charger-led", },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, axp20x_leds_of_match);
++
++static struct platform_driver axp20x_led_driver = {
++	.driver		= {
++		.name	= "leds-axp20x",
++		.of_match_table = axp20x_leds_of_match,
++	},
++	.probe		= axp20x_led_probe,
++	.remove		= axp20x_led_remove,
++	.shutdown	= axp20x_led_shutdown,
++};
++
++static int __init axp20x_led_driver_init(void)
++{
++	int ret;
++
++	ret = led_trigger_register(&axp20x_charger_led_trigger);
++	if (ret)
++		return ret;
++
++	ret = platform_driver_register(&axp20x_led_driver);
++	if (ret) {
++		led_trigger_unregister(&axp20x_charger_led_trigger);
++		return ret;
++	}
++
++	return 0;
++}
++
++static void __exit axp20x_led_driver_exit(void)
++{
++	platform_driver_unregister(&axp20x_led_driver);
++	led_trigger_unregister(&axp20x_charger_led_trigger);
++}
++
++module_init(axp20x_led_driver_init);
++module_exit(axp20x_led_driver_exit);
++
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("LED driver for AXP813 PMIC");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:leds-axp20x");
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index dacd3c96c9f5..d35b5cc6b8fe 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -1172,6 +1172,9 @@ static const struct mfd_cell axp813_cells[] = {
+ 		.num_resources	= ARRAY_SIZE(axp803_usb_power_supply_resources),
+ 		.resources	= axp803_usb_power_supply_resources,
+ 		.of_compatible	= "x-powers,axp813-usb-power-supply",
++	}, {
++		.name		= "axp20x-charger-led",
++		.of_compatible	= "x-powers,axp813-charger-led",
+ 	},
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
new file mode 100644
index 000000000000..7f295eacd4ab
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
@@ -0,0 +1,64 @@
+From a3d4756b919d39ec6393537ead45f340d28b824e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 2 Nov 2019 15:09:01 +0100
+Subject: mailbox: Allow to run mailbox while timekeeping is suspended
+
+This makes it possible to send messages from CPU suspend finisher.
+
+We simply implement cl->tx_block using a busywait loop when
+timekeeping is suspended, instead of using hrtimer.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mailbox/mailbox.c | 28 ++++++++++++++++++++++++----
+ 1 file changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c
+index ebff3baf3045..9d6656a0dc38 100644
+--- a/drivers/mailbox/mailbox.c
++++ b/drivers/mailbox/mailbox.c
+@@ -84,10 +84,12 @@ static void msg_submit(struct mbox_chan *chan)
+ 	spin_unlock_irqrestore(&chan->lock, flags);
+ 
+ 	if (!err && (chan->txdone_method & TXDONE_BY_POLL)) {
+-		/* kick start the timer immediately to avoid delays */
+-		spin_lock_irqsave(&chan->mbox->poll_hrt_lock, flags);
+-		hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);
+-		spin_unlock_irqrestore(&chan->mbox->poll_hrt_lock, flags);
++		if (!timekeeping_suspended) {
++			/* kick start the timer immediately to avoid delays */
++			spin_lock_irqsave(&chan->mbox->poll_hrt_lock, flags);
++			hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);
++			spin_unlock_irqrestore(&chan->mbox->poll_hrt_lock, flags);
++		}
+ 	}
+ }
+ 
+@@ -269,6 +271,24 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg)
+ 
+ 	msg_submit(chan);
+ 
++	if (chan->cl->tx_block && timekeeping_suspended) {
++		int i = chan->cl->tx_tout * 10;
++		bool txdone;
++
++		while (i--) {
++			txdone = chan->mbox->ops->last_tx_done(chan);
++			if (txdone) {
++				tx_tick(chan, 0);
++				return 0;
++			}
++
++			udelay(100);
++		}
++
++		tx_tick(chan, -ETIME);
++		return -ETIME;
++	}
++
+ 	if (chan->cl->tx_block) {
+ 		unsigned long wait;
+ 		int ret;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
new file mode 100644
index 000000000000..4079ec94e328
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
@@ -0,0 +1,35 @@
+From 89bb8d013b5e0155c78fcd33dfcc8271cfc81da5 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 26 Apr 2020 14:38:15 -0500
+Subject: media: cedrus: Fix failure to clean up hardware on probe failure
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
+index f52df6836045..992b30e5ccac 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
+@@ -478,7 +478,7 @@ static int cedrus_probe(struct platform_device *pdev)
+ 	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "Failed to register V4L2 device\n");
+-		return ret;
++		goto err_hw;
+ 	}
+ 
+ 	vfd = &dev->vfd;
+@@ -539,6 +539,8 @@ static int cedrus_probe(struct platform_device *pdev)
+ 	v4l2_m2m_release(dev->m2m_dev);
+ err_v4l2:
+ 	v4l2_device_unregister(&dev->v4l2_dev);
++err_hw:
++	cedrus_hw_remove(dev);
+ 
+ 	return ret;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
new file mode 100644
index 000000000000..5ff3a5afb3e0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
@@ -0,0 +1,549 @@
+From ba0d0f69928a6473159cc50c2213ad7272d47d0c Mon Sep 17 00:00:00 2001
+From: Benjamin Schaaf <ben.schaaf@gmail.com>
+Date: Mon, 22 Nov 2021 23:38:26 +1100
+Subject: media: gc2145: Add PIXEL_RATE, HBLANK and VBLANK controls
+
+---
+ drivers/media/i2c/gc2145.c | 469 ++++++++++++++++++++-----------------
+ 1 file changed, 258 insertions(+), 211 deletions(-)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index df15b72651e2..749dce832aa0 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -216,6 +216,9 @@ static const char * const gc2145_supply_name[] = {
+ 
+ struct gc2145_ctrls {
+ 	struct v4l2_ctrl_handler handler;
++	struct v4l2_ctrl *pixel_rate;
++	struct v4l2_ctrl *hblank;
++	struct v4l2_ctrl *vblank;
+ 	struct {
+ 		struct v4l2_ctrl *auto_exposure;
+ 		struct v4l2_ctrl *exposure;
+@@ -866,6 +869,224 @@ static int gc2145_set_exposure(struct gc2145_dev *sensor)
+ 	return gc2145_tx_commit(sensor);;
+ }
+ 
++struct gc2145_sensor_params {
++	unsigned int enable_scaler;
++	unsigned int col_scaler_only;
++	unsigned int row_skip;
++	unsigned int col_skip;
++	unsigned long sh_delay;
++	unsigned long hb;
++	unsigned long vb;
++	unsigned long st;
++	unsigned long et;
++	unsigned long win_width;
++	unsigned long win_height;
++	unsigned long width;
++	unsigned long height;
++};
++
++static void gc2145_sensor_params_init(struct gc2145_sensor_params* p, int width, int height)
++{
++	p->win_height = height + 32;
++	p->win_width = (width + 16);
++	p->width = width;
++	p->height = height;
++	p->st = 2;
++	p->et = 2;
++	p->vb = 8;
++	p->hb = 0x1f0;
++	p->sh_delay = 30;
++}
++
++// unit is PCLK periods
++static unsigned long
++gc2145_sensor_params_get_row_period(struct gc2145_sensor_params* p)
++{
++	return 2 * (p->win_width / 2 / (p->col_skip + 1) + p->sh_delay + p->hb + 4);
++}
++
++static unsigned long
++gc2145_sensor_params_get_frame_period(struct gc2145_sensor_params* p)
++{
++	unsigned long rt = gc2145_sensor_params_get_row_period(p);
++
++	return rt * (p->vb + p->win_height) / (p->row_skip + 1);
++}
++
++static void
++gc2145_sensor_params_fit_hb_to_power_line_period(struct gc2145_sensor_params* p,
++					  unsigned long power_line_freq,
++					  unsigned long pclk)
++{
++	unsigned long rt, power_line_ratio;
++
++        for (p->hb = 0x1f0; p->hb < 2047; p->hb++) {
++		rt = gc2145_sensor_params_get_row_period(p);
++
++		// power_line_ratio is row_freq / power_line_freq * 1000
++                power_line_ratio = pclk / power_line_freq * 1000 / rt;
++
++		// if we're close enough, stop the search
++                if (power_line_ratio % 1000 < 50)
++                        break;
++        }
++
++	// finding the optimal Hb is not critical
++	if (p->hb == 2047)
++		p->hb = 0x1f0;
++}
++
++static void
++gc2145_sensor_params_fit_vb_to_frame_period(struct gc2145_sensor_params* p,
++				     unsigned long frame_period)
++{
++	unsigned long rt, fp;
++
++	p->vb = 8;
++	rt = gc2145_sensor_params_get_row_period(p);
++	fp = gc2145_sensor_params_get_frame_period(p);
++
++	if (frame_period > fp)
++		p->vb = frame_period * (p->row_skip + 1) / rt - p->win_height;
++
++	if (p->vb > 4095)
++		p->vb = 4095;
++}
++
++static struct gc2145_sensor_params gc2145_get_sensor_params(
++	unsigned long framerate,
++	unsigned long width,
++	unsigned long height,
++	unsigned long *pclk2)
++{
++	struct gc2145_sensor_params params = {0};
++	bool scaling_desired;
++	unsigned long frame_period;
++	unsigned long power_line_freq = 50;
++
++	/*
++	 * Equations for calculating framerate are:
++	 *
++	 *    ww = width + 16
++	 *    wh = height + 32
++	 *    Rt = (ww / 2 / (col_skip + 1) + sh_delay + Hb + 4)
++	 *    Ft = Rt * (Vb + wh) / (row_skip + 1)
++	 *    framerate = 2pclk / 4 / Ft
++	 *
++	 * Based on these equations:
++	 *
++	 * 1) First we need to determine what 2PCLK frequency to use. The 2PCLK
++	 *    frequency is not arbitrarily precise, so we need to calculate the
++	 *    actual frequency used, after setting our target frequency.
++	 *
++	 *    We use a simple heuristic:
++	 *
++	 *      If pixel_count * 2 * framerate * 1.15 is > 40MHz, we use 60MHz,
++	 *      otherwise we use 40MHz.
++	 *
++	 * 2) We want to determine lowest Hb that we can use to extend row
++	 *    period so that row time takes an integer fraction of the power
++	 *    line frequency period. Minimum Hb is 0x1f0.
++	 *
++	 * 3) If the requested resolution is less than half the sensor's size,
++	 *    we'll use scaling, or row skipping + column scaling, or row and
++	 *    column skiping, depending on what allows us to achieve the
++	 *    requested framerate.
++	 *
++	 * 4) We use the selected Hb to calculate Vb value that will give
++	 *    us the desired framerate, given the scaling/skipping option
++	 *    selected in 3).
++	 */
++
++	scaling_desired = width <= GC2145_SENSOR_WIDTH_MAX / 2
++			&& height <= GC2145_SENSOR_HEIGHT_MAX / 2;
++
++	*pclk2 = 60000000;
++
++	gc2145_sensor_params_init(&params, width, height);
++
++	// if the resolution is < half the sensor size, enable the scaler
++	// to cover more area of the chip
++	if (scaling_desired) {
++		params.enable_scaler = 1;
++		*pclk2 *= 2;
++		gc2145_sensor_params_init(&params, width * 2, height * 2);
++	}
++
++	// we need to call this each time pclk or power_line_freq is changed
++	gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++							 power_line_freq,
++							 *pclk2 / 2);
++
++	frame_period = gc2145_sensor_params_get_frame_period(&params);
++	if (framerate <= *pclk2 / 2 / frame_period)
++		goto apply;
++
++	if (scaling_desired) {
++		// try using just the column scaler + row skip
++		params.col_scaler_only = 1;
++		params.row_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++								 power_line_freq,
++								 *pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++		if (framerate <= *pclk2 / 2 / frame_period)
++			goto apply;
++
++
++		/*
++		// try disabling the scaler and just use skipping
++		params.enable_scaler = 0;
++		*pclk2 /= 2;
++		params.col_scaler_only = 0;
++		params.col_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params, power_line_freq, *pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++
++		if (framerate <= *pclk2 / 2 / frame_period)
++			goto apply;
++		*/
++	}
++
++apply:
++	// adjust vb to fit the target framerate
++	gc2145_sensor_params_fit_vb_to_frame_period(&params,
++						    *pclk2 / 2 / framerate);
++
++	return params;
++}
++
++static int gc2145_sensor_params_apply(struct gc2145_dev *sensor,
++				      struct gc2145_sensor_params* p)
++{
++	u32 off_x = (GC2145_SENSOR_WIDTH_MAX - p->width) / 2;
++	u32 off_y = (GC2145_SENSOR_HEIGHT_MAX - p->height) / 2;
++
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, 0xfd, (p->enable_scaler ? BIT(0) : 0)
++			| (p->col_scaler_only ? BIT(1) : 0));
++
++	gc2145_tx_write8(sensor, 0x18, 0x0a
++		       | (p->col_skip ? BIT(7) : 0)
++		       | (p->row_skip ? BIT(6) : 0));
++
++	gc2145_tx_write16(sensor, 0x09, off_y);
++	gc2145_tx_write16(sensor, 0x0b, off_x);
++	gc2145_tx_write16(sensor, 0x0d, p->win_height);
++	gc2145_tx_write16(sensor, 0x0f, p->win_width);
++	gc2145_tx_write16(sensor, 0x05, p->hb);
++	gc2145_tx_write16(sensor, 0x07, p->vb);
++	gc2145_tx_write16(sensor, 0x11, p->sh_delay);
++
++	gc2145_tx_write8(sensor, 0x13, p->st);
++	gc2145_tx_write8(sensor, 0x14, p->et);
++
++	return gc2145_tx_commit(sensor);
++}
++
+ /* Test patterns */
+ 
+ enum {
+@@ -1054,12 +1275,31 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	//u64 wb_mask = 0;
+ 	//unsigned int i;
+ 	int ret;
++	struct gc2145_sensor_params params;
++	unsigned long pixel_rate;
+ 
+ 	v4l2_ctrl_handler_init(hdl, 32);
+ 
+ 	/* we can use our own mutex for the ctrl lock */
+ 	hdl->lock = &sensor->lock;
+ 
++	/* Clock related controls */
++	params = gc2145_get_sensor_params(sensor->frame_interval.denominator,
++					  sensor->fmt.width,
++					  sensor->fmt.height,
++					  &pixel_rate);
++	ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
++					      0, INT_MAX, 1,
++					      pixel_rate);
++
++	ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
++					  0, INT_MAX, 1,
++					  params.win_height);
++
++	ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
++					  0, INT_MAX, 1,
++					  params.win_width);
++
+ 	/* Exposure controls */
+ 	ctrls->auto_exposure = v4l2_ctrl_new_std_menu(hdl, ops,
+ 						      V4L2_CID_EXPOSURE_AUTO,
+@@ -1153,6 +1393,10 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	v4l2_ctrl_auto_cluster(3, &ctrls->wb, V4L2_WHITE_BALANCE_MANUAL, false);
+ #endif
+ 
++	ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++	ctrls->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++	ctrls->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++
+ 	v4l2_ctrl_auto_cluster(4, &ctrls->auto_exposure, V4L2_EXPOSURE_MANUAL,
+ 			       true);
+ 
+@@ -1386,125 +1630,11 @@ static int gc2145_setup_aec(struct gc2145_dev *sensor,
+ 	return gc2145_tx_commit(sensor);
+ }
+ 
+-struct gc2145_sensor_params {
+-	unsigned int enable_scaler;
+-	unsigned int col_scaler_only;
+-	unsigned int row_skip;
+-	unsigned int col_skip;
+-	unsigned long sh_delay;
+-	unsigned long hb;
+-	unsigned long vb;
+-	unsigned long st;
+-	unsigned long et;
+-	unsigned long win_width;
+-	unsigned long win_height;
+-	unsigned long width;
+-	unsigned long height;
+-};
+-
+-static void gc2145_sensor_params_init(struct gc2145_sensor_params* p, int width, int height)
+-{
+-	p->win_height = height + 32;
+-	p->win_width = (width + 16);
+-	p->width = width;
+-	p->height = height;
+-	p->st = 2;
+-	p->et = 2;
+-	p->vb = 8;
+-	p->hb = 0x1f0;
+-	p->sh_delay = 30;
+-}
+-
+-// unit is PCLK periods
+-static unsigned long
+-gc2145_sensor_params_get_row_period(struct gc2145_sensor_params* p)
+-{
+-	return 2 * (p->win_width / 2 / (p->col_skip + 1) + p->sh_delay + p->hb + 4);
+-}
+-
+-static unsigned long
+-gc2145_sensor_params_get_frame_period(struct gc2145_sensor_params* p)
+-{
+-	unsigned long rt = gc2145_sensor_params_get_row_period(p);
+-
+-	return rt * (p->vb + p->win_height) / (p->row_skip + 1);
+-}
+-
+-static void
+-gc2145_sensor_params_fit_hb_to_power_line_period(struct gc2145_sensor_params* p,
+-					  unsigned long power_line_freq,
+-					  unsigned long pclk)
+-{
+-	unsigned long rt, power_line_ratio;
+-
+-        for (p->hb = 0x1f0; p->hb < 2047; p->hb++) {
+-		rt = gc2145_sensor_params_get_row_period(p);
+-
+-		// power_line_ratio is row_freq / power_line_freq * 1000
+-                power_line_ratio = pclk / power_line_freq * 1000 / rt;
+-
+-		// if we're close enough, stop the search
+-                if (power_line_ratio % 1000 < 50)
+-                        break;
+-        }
+-
+-	// finding the optimal Hb is not critical
+-	if (p->hb == 2047)
+-		p->hb = 0x1f0;
+-}
+-
+-static void
+-gc2145_sensor_params_fit_vb_to_frame_period(struct gc2145_sensor_params* p,
+-				     unsigned long frame_period)
+-{
+-	unsigned long rt, fp;
+-
+-	p->vb = 8;
+-	rt = gc2145_sensor_params_get_row_period(p);
+-	fp = gc2145_sensor_params_get_frame_period(p);
+-
+-	if (frame_period > fp)
+-		p->vb = frame_period * (p->row_skip + 1) / rt - p->win_height;
+-
+-	if (p->vb > 4095)
+-		p->vb = 4095;
+-}
+-
+-static int gc2145_sensor_params_apply(struct gc2145_dev *sensor,
+-				      struct gc2145_sensor_params* p)
+-{
+-	u32 off_x = (GC2145_SENSOR_WIDTH_MAX - p->width) / 2;
+-	u32 off_y = (GC2145_SENSOR_HEIGHT_MAX - p->height) / 2;
+-
+-	gc2145_tx_start(sensor);
+-
+-	gc2145_tx_write8(sensor, 0xfd, (p->enable_scaler ? BIT(0) : 0)
+-			| (p->col_scaler_only ? BIT(1) : 0));
+-
+-	gc2145_tx_write8(sensor, 0x18, 0x0a
+-		       | (p->col_skip ? BIT(7) : 0)
+-		       | (p->row_skip ? BIT(6) : 0));
+-
+-	gc2145_tx_write16(sensor, 0x09, off_y);
+-	gc2145_tx_write16(sensor, 0x0b, off_x);
+-	gc2145_tx_write16(sensor, 0x0d, p->win_height);
+-	gc2145_tx_write16(sensor, 0x0f, p->win_width);
+-	gc2145_tx_write16(sensor, 0x05, p->hb);
+-	gc2145_tx_write16(sensor, 0x07, p->vb);
+-	gc2145_tx_write16(sensor, 0x11, p->sh_delay);
+-
+-	gc2145_tx_write8(sensor, 0x13, p->st);
+-	gc2145_tx_write8(sensor, 0x14, p->et);
+-
+-	return gc2145_tx_commit(sensor);
+-}
+-
+ static int gc2145_setup_mode(struct gc2145_dev *sensor)
+ {
+-	int scaling_desired, ret, pad, i;
+-	struct gc2145_sensor_params params = {0};
+-	unsigned long pclk2, frame_period;
+-	unsigned long power_line_freq = 50;
++	int ret, pad, i;
++	struct gc2145_sensor_params params;
++	unsigned long pclk2;
+ 	unsigned long width = sensor->fmt.width;
+ 	unsigned long height = sensor->fmt.height;
+ 	unsigned long framerate = sensor->frame_interval.denominator;
+@@ -1518,100 +1648,7 @@ static int gc2145_setup_mode(struct gc2145_dev *sensor)
+ 		return -EINVAL;
+ 	}
+ 
+-        /*
+-	 * Equations for calculating framerate are:
+-	 *
+-	 *    ww = width + 16
+-	 *    wh = height + 32
+-	 *    Rt = (ww / 2 / (col_skip + 1) + sh_delay + Hb + 4)
+-	 *    Ft = Rt * (Vb + wh) / (row_skip + 1)
+-	 *    framerate = 2pclk / 4 / Ft
+-	 *
+-	 * Based on these equations:
+-	 *
+-	 * 1) First we need to determine what 2PCLK frequency to use. The 2PCLK
+-	 *    frequency is not arbitrarily precise, so we need to calculate the
+-	 *    actual frequency used, after setting our target frequency.
+-	 *
+-	 *    We use a simple heuristic:
+-	 *
+-	 *      If pixel_count * 2 * framerate * 1.15 is > 40MHz, we use 60MHz,
+-	 *      otherwise we use 40MHz.
+-	 *
+-	 * 2) We want to determine lowest Hb that we can use to extend row
+-	 *    period so that row time takes an integer fraction of the power
+-	 *    line frequency period. Minimum Hb is 0x1f0.
+-	 *
+-	 * 3) If the requested resolution is less than half the sensor's size,
+-	 *    we'll use scaling, or row skipping + column scaling, or row and
+-	 *    column skiping, depending on what allows us to achieve the
+-	 *    requested framerate.
+-         *
+-	 * 4) We use the selected Hb to calculate Vb value that will give
+-	 *    us the desired framerate, given the scaling/skipping option
+-	 *    selected in 3).
+-	 */
+-
+-	scaling_desired = width <= GC2145_SENSOR_WIDTH_MAX / 2
+-			&& height <= GC2145_SENSOR_HEIGHT_MAX / 2;
+-
+-	pclk2 = 60000000;
+-
+-	ret = gc2145_set_2pclk(sensor, &pclk2, false);
+-	if (ret < 0)
+-		return ret;
+-
+-	gc2145_sensor_params_init(&params, width, height);
+-
+-	// if the resolution is < half the sensor size, enable the scaler
+-	// to cover more area of the chip
+-	if (scaling_desired) {
+-		params.enable_scaler = 1;
+-		pclk2 *= 2;
+-		gc2145_sensor_params_init(&params, width * 2, height * 2);
+-	}
+-
+-	// we need to call this each time pclk or power_line_freq is changed
+-	gc2145_sensor_params_fit_hb_to_power_line_period(&params,
+-							 power_line_freq,
+-							 pclk2 / 2);
+-
+-	frame_period = gc2145_sensor_params_get_frame_period(&params);
+-	if (framerate <= pclk2 / 2 / frame_period)
+-		goto apply;
+-
+-	if (scaling_desired) {
+-		// try using just the column scaler + row skip
+-		params.col_scaler_only = 1;
+-		params.row_skip = 1;
+-		gc2145_sensor_params_fit_hb_to_power_line_period(&params,
+-								 power_line_freq,
+-								 pclk2 / 2);
+-
+-		frame_period = gc2145_sensor_params_get_frame_period(&params);
+-		if (framerate <= pclk2 / 2 / frame_period)
+-			goto apply;
+-
+-
+-		/*
+-		// try disabling the scaler and just use skipping
+-		params.enable_scaler = 0;
+-		pclk2 /= 2;
+-		params.col_scaler_only = 0;
+-		params.col_skip = 1;
+-		gc2145_sensor_params_fit_hb_to_power_line_period(&params, power_line_freq, pclk2 / 2);
+-
+-		frame_period = gc2145_sensor_params_get_frame_period(&params);
+-
+-		if (framerate <= pclk2 / 2 / frame_period)
+-			goto apply;
+-                  */
+-	}
+-
+-apply:
+-        // adjust vb to fit the target framerate
+-	gc2145_sensor_params_fit_vb_to_frame_period(&params,
+-						    pclk2 / 2 / framerate);
++	params = gc2145_get_sensor_params(framerate, width, height, &pclk2);
+ 
+ 	gc2145_sensor_params_apply(sensor, &params);
+ 
+@@ -1845,6 +1882,8 @@ static int gc2145_set_fmt(struct v4l2_subdev *sd,
+ 	struct gc2145_dev *sensor = to_gc2145_dev(sd);
+ 	struct v4l2_mbus_framefmt *mf = &format->format;
+ 	const struct gc2145_pixfmt *pixfmt;
++	struct gc2145_sensor_params params;
++	unsigned long pixel_rate;
+ 	int ret = 0;
+ 
+ 	if (format->pad != 0)
+@@ -1884,6 +1923,14 @@ static int gc2145_set_fmt(struct v4l2_subdev *sd,
+ 
+ 	sensor->fmt = *mf;
+ 	sensor->pending_mode_change = true;
++
++	params = gc2145_get_sensor_params(sensor->frame_interval.denominator, mf->width, mf->height, &pixel_rate);
++	__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
++				 pixel_rate);
++	__v4l2_ctrl_s_ctrl(sensor->ctrls.hblank,
++			   params.win_height);
++	__v4l2_ctrl_s_ctrl(sensor->ctrls.vblank,
++			   params.win_width);
+ out:
+ 	mutex_unlock(&sensor->lock);
+ 	return ret;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
new file mode 100644
index 000000000000..69f601cf0441
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
@@ -0,0 +1,30 @@
+From 9bd8195aa3bb4cbef4693c6f0fe5674ee1180535 Mon Sep 17 00:00:00 2001
+From: Martijn Braam <martijn@brixit.nl>
+Date: Fri, 4 Sep 2020 17:35:39 +0200
+Subject: media: gc2145: Added BGGR bayer mode
+
+Not all raw bayer modes from the sensor match up with the ones defined
+in v4l, mostly because they're mirrored.
+---
+ drivers/media/i2c/gc2145.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index cc85ac772d5a..7539b122eeef 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -187,6 +187,11 @@ static const struct gc2145_pixfmt gc2145_formats[] = {
+ 		.colorspace        = V4L2_COLORSPACE_SRGB,
+ 		.fmt_setup         = 0x06,
+ 	},
++	{
++		.code              = MEDIA_BUS_FMT_SBGGR8_1X8,
++		.colorspace        = V4L2_COLORSPACE_RAW,
++		.fmt_setup         = 0x17,
++	},
+ };
+ 
+ static const struct gc2145_pixfmt *gc2145_find_format(u32 code)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Disable-debug-output.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Disable-debug-output.patch
new file mode 100644
index 000000000000..215dfc735f76
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Disable-debug-output.patch
@@ -0,0 +1,37 @@
+From 8d3a42891bd0c835b575ce6121bf6c65acf77e67 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 27 Oct 2021 17:22:51 +0200
+Subject: media: gc2145: Disable debug output
+
+People don't like it. Hmm...
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/gc2145.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index 7539b122eeef..df15b72651e2 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -8,7 +8,7 @@
+  * (at your option) any later version.
+  */
+ 
+-#define DEBUG
++//#define DEBUG
+ 
+ #include <asm/div64.h>
+ #include <linux/clk.h>
+@@ -374,7 +374,7 @@ static int gc2145_switch_bank(struct gc2145_dev *sensor, u16 reg)
+ 			return ret;
+ 
+ 		sensor->current_bank = bank;
+-		dev_info(&sensor->i2c_client->dev, "bank switch: 0x%02x\n",
++		dev_dbg(&sensor->i2c_client->dev, "bank switch: 0x%02x\n",
+ 				(unsigned int)sensor->current_bank);
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
new file mode 100644
index 000000000000..0e6227cf9b7e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
@@ -0,0 +1,2306 @@
+From 5cf627fa3a0d8585031f440d0649114acadcfc84 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:51:18 +0200
+Subject: media: gc2145: Galaxycore camera module driver
+
+WIP!
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/Kconfig  |   10 +
+ drivers/media/i2c/Makefile |    1 +
+ drivers/media/i2c/gc2145.c | 2252 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 2263 insertions(+)
+ create mode 100644 drivers/media/i2c/gc2145.c
+
+diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
+index 0b16e091fb4f..c47097ce91e1 100644
+--- a/drivers/media/i2c/Kconfig
++++ b/drivers/media/i2c/Kconfig
+@@ -680,6 +680,16 @@ config VIDEO_HM5065
+ 	  This is a V4L2 sensor-level driver for Himax HM5065
+ 	  5 Mpixel camera.
+ 
++config VIDEO_GC2145
++	tristate "GalaxyCore GC2145 sensor support"
++	depends on I2C
++	select V4L2_FWNODE
++	select VIDEO_V4L2_SUBDEV_API
++	select MEDIA_CONTROLLER
++	help
++	  This is a V4L2 sensor-level driver for GalaxyCore GC2145
++	  2 Mpixel camera.
++
+ endif
+ 
+ menu "Camera ISPs"
+diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
+index e84186ed81cb..0576c8962839 100644
+--- a/drivers/media/i2c/Makefile
++++ b/drivers/media/i2c/Makefile
+@@ -153,3 +153,4 @@ obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o
+ obj-$(CONFIG_VIDEO_WM8739) += wm8739.o
+ obj-$(CONFIG_VIDEO_WM8775) += wm8775.o
+ obj-$(CONFIG_VIDEO_HM5065)	+= hm5065.o
++obj-$(CONFIG_VIDEO_GC2145)	+= gc2145.o
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+new file mode 100644
+index 000000000000..cc85ac772d5a
+--- /dev/null
++++ b/drivers/media/i2c/gc2145.c
+@@ -0,0 +1,2252 @@
++/*
++ * Galaxycore GC2145 driver.
++ * Copyright (C) 2018 Ondřej Jirman <megi@xff.cz>.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#define DEBUG
++
++#include <asm/div64.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/clkdev.h>
++#include <linux/ctype.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/firmware.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++#include <media/v4l2-subdev.h>
++
++/*
++ * GC2145
++ * - 2M pixel
++ * - 1600 x 1200, max frame rate: 720P, 30fps@96MHz
++ * - Bayer RGB, RGB565, YCbCr 4:2:2
++ * - AE, AWB
++ * - PLL
++ * - AVDD 2.7-3V, DVDD 1.7-1.9V, IOVDD 1.7-3V
++ * - Power 180mW / 200uA standby
++ * - Interpolation, denoise, gamma, edge enhance
++ * I2C:
++ * - write reg8
++ * - read reg8
++ * - write reg8 multi
++ *
++ * Power on:
++ * MCLK on
++ * PWDN, RESET low
++ * IOVDD, AVDD, DVDD on in sequence
++ * RESET high
++ *
++ * Power off:
++ * PWDN, RESET low
++ * RESET high
++ * delay
++ * PWDN high
++ * RESET low
++ * IOVDD, AVDD, DVDD off
++ * PWDN low?
++ * MCLK off
++ *
++ * Init:
++ * - check chip id
++ * - setup pll
++ * - setup CSI interface / PAD drive strength
++ * - setup resolution/fps
++ * - enable postprocessing
++ *   (ISP related chapter)
++ *
++ * Stream on:
++ * - ???
++ */
++
++#define GC2145_FIRMWARE_PARAMETERS	"gc2145-init.bin"
++
++#define GC2145_SENSOR_WIDTH_MIN		88u
++#define GC2145_SENSOR_HEIGHT_MIN	72u
++
++//XXX: 1616x1232 8H/16V dummy pixels on each side
++#define GC2145_SENSOR_WIDTH_MAX		1600u
++#define GC2145_SENSOR_HEIGHT_MAX	1200u
++
++/* {{{ Register definitions */
++
++/* system registers */
++#define GC2145_REG_CHIP_ID			0xf0
++#define GC2145_REG_CHIP_ID_VALUE		0x2145
++
++#define GC2145_REG_PAD_IO		0xf2
++#define GC2145_REG_PLL_MODE1		0xf7
++#define GC2145_REG_PLL_MODE2		0xf8
++#define GC2145_REG_CM_MODE		0xf9
++#define GC2145_REG_CLK_DIV_MODE		0xfa
++#define GC2145_REG_ANALOG_PWC		0xfc
++#define GC2145_REG_SCALER_MODE		0xfd
++#define GC2145_REG_RESET		0xfe
++
++#define GC2145_P0_EXPOSURE_HI		0x03
++#define GC2145_P0_EXPOSURE_LO		0x04
++#define GC2145_P0_HBLANK_DELAY_HI	0x05
++#define GC2145_P0_HBLANK_DELAY_LO	0x06
++#define GC2145_P0_VBLANK_DELAY_HI	0x07
++#define GC2145_P0_VBLANK_DELAY_LO	0x08
++#define GC2145_P0_ROW_START_HI		0x09
++#define GC2145_P0_ROW_START_LO		0x0a
++#define GC2145_P0_COL_START_HI		0x0b
++#define GC2145_P0_COL_START_LO		0x0c
++#define GC2145_P0_WIN_HEIGHT_HI		0x0d
++#define GC2145_P0_WIN_HEIGHT_LO		0x0e
++#define GC2145_P0_WIN_WIDTH_HI		0x0f
++#define GC2145_P0_WIN_WIDTH_LO		0x10
++#define GC2145_P0_SH_DELAY_HI		0x11
++#define GC2145_P0_SH_DELAY_LO		0x12
++#define GC2145_P0_START_TIME		0x13
++#define GC2145_P0_END_TIME		0x14
++
++#define GC2145_P0_ISP_BLK_ENABLE1	0x80
++#define GC2145_P0_ISP_BLK_ENABLE2	0x81
++#define GC2145_P0_ISP_BLK_ENABLE3	0x82
++#define GC2145_P0_ISP_SPECIAL_EFFECT	0x83
++#define GC2145_P0_ISP_OUT_FORMAT	0x84
++#define GC2145_P0_FRAME_START		0x85
++#define GC2145_P0_SYNC_MODE		0x86
++#define GC2145_P0_ISP_BLK_ENABLE4	0x87
++#define GC2145_P0_ISP_MODULE_GATING	0x88
++#define GC2145_P0_ISP_BYPASS_MODE	0x89
++#define GC2145_P0_DEBUG_MODE2		0x8c
++#define GC2145_P0_DEBUG_MODE3		0x8d
++
++#define GC2145_P0_CROP_ENABLE		0x90
++#define GC2145_P0_CROP_Y1_HI		0x91
++#define GC2145_P0_CROP_Y1_LO		0x92
++#define GC2145_P0_CROP_X1_HI		0x93
++#define GC2145_P0_CROP_X1_LO		0x94
++#define GC2145_P0_CROP_WIN_HEIGHT_HI	0x95
++#define GC2145_P0_CROP_WIN_HEIGHT_LO	0x96
++#define GC2145_P0_CROP_WIN_WIDTH_HI	0x97
++#define GC2145_P0_CROP_WIN_WIDTH_LO	0x98
++
++#define GC2145_P0_SUBSAMPLE_RATIO	0x99
++#define GC2145_P0_SUBSAMPLE_MODE	0x9a
++#define GC2145_P0_SUB_ROW_N1		0x9b
++#define GC2145_P0_SUB_ROW_N2		0x9c
++#define GC2145_P0_SUB_ROW_N3		0x9d
++#define GC2145_P0_SUB_ROW_N4		0x9e
++#define GC2145_P0_SUB_COL_N1		0x9f
++#define GC2145_P0_SUB_COL_N2		0xa0
++#define GC2145_P0_SUB_COL_N3		0xa1
++#define GC2145_P0_SUB_COL_N4		0xa2
++#define GC2145_P0_OUT_BUF_ENABLE	0xc2
++
++/* }}} */
++
++struct gc2145_pixfmt {
++	u32 code;
++	u32 colorspace;
++	u8 fmt_setup;
++};
++
++static const struct gc2145_pixfmt gc2145_formats[] = {
++	{
++		.code              = MEDIA_BUS_FMT_UYVY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x00,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_VYUY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x01,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x02,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x03,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_RGB565_2X8_LE,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x06,
++	},
++};
++
++static const struct gc2145_pixfmt *gc2145_find_format(u32 code)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(gc2145_formats); i++)
++		if (gc2145_formats[i].code == code)
++			return &gc2145_formats[i];
++
++	return NULL;
++}
++
++/* regulator supplies */
++static const char * const gc2145_supply_name[] = {
++	"IOVDD", /* Digital I/O (1.7-3V) suppply */
++	"AVDD",  /* Analog (2.7-3V) supply */
++	"DVDD",  /* Digital Core (1.7-1.9V) supply */
++};
++
++#define GC2145_NUM_SUPPLIES ARRAY_SIZE(gc2145_supply_name)
++
++struct gc2145_ctrls {
++	struct v4l2_ctrl_handler handler;
++	struct {
++		struct v4l2_ctrl *auto_exposure;
++		struct v4l2_ctrl *exposure;
++		struct v4l2_ctrl *d_gain;
++		struct v4l2_ctrl *a_gain;
++	};
++	struct v4l2_ctrl *metering;
++	struct v4l2_ctrl *exposure_bias;
++	struct {
++		struct v4l2_ctrl *wb;
++		struct v4l2_ctrl *blue_balance;
++		struct v4l2_ctrl *red_balance;
++	};
++	struct v4l2_ctrl *aaa_lock;
++	struct v4l2_ctrl *hflip;
++	struct v4l2_ctrl *vflip;
++	struct v4l2_ctrl *pl_freq;
++	struct v4l2_ctrl *colorfx;
++	struct v4l2_ctrl *brightness;
++	struct v4l2_ctrl *saturation;
++	struct v4l2_ctrl *contrast;
++	struct v4l2_ctrl *gamma;
++	struct v4l2_ctrl *test_pattern;
++	struct v4l2_ctrl *test_data[4];
++};
++
++enum {
++	TX_WRITE = 1,
++	TX_WRITE16,
++	TX_UPDATE_BITS,
++};
++
++#define GC2145_MAX_OPS 64
++
++struct gc2145_tx_op {
++	int op;
++	u16 reg;
++	u16 val;
++	u16 mask;
++};
++
++struct gc2145_dev {
++	struct i2c_client *i2c_client;
++	struct v4l2_subdev sd;
++	struct media_pad pad;
++	struct v4l2_fwnode_endpoint ep; /* the parsed DT endpoint info */
++	struct clk *xclk; /* external clock for GC2145 */
++
++	struct regulator_bulk_data supplies[GC2145_NUM_SUPPLIES];
++	struct gpio_desc *reset_gpio; // nrst pin
++	struct gpio_desc *enable_gpio; // ce pin
++
++	/* lock to protect all members below */
++	struct mutex lock;
++
++	struct v4l2_mbus_framefmt fmt;
++	struct v4l2_fract frame_interval;
++	struct gc2145_ctrls ctrls;
++
++	bool pending_mode_change;
++	bool powered;
++	bool streaming;
++
++	u8 current_bank;
++
++	struct gc2145_tx_op ops[GC2145_MAX_OPS];
++	int n_ops;
++	int tx_started;
++};
++
++static inline struct gc2145_dev *to_gc2145_dev(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct gc2145_dev, sd);
++}
++
++/* {{{ Register access helpers */
++
++static int gc2145_write_regs(struct gc2145_dev *sensor, u8 addr,
++			     u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg;
++	u8 buf[128 + 1];
++	int ret;
++
++	if (data_size > sizeof(buf) - 1) {
++		v4l2_err(&sensor->sd, "%s: oversized transfer (size=%d)\n",
++			 __func__, data_size);
++		return -EINVAL;
++	}
++
++	buf[0] = addr;
++	memcpy(buf + 1, data, data_size);
++
++	msg.addr = client->addr;
++	msg.flags = client->flags;
++	msg.buf = buf;
++	msg.len = data_size + 1;
++
++	dev_dbg(&sensor->i2c_client->dev, "[wr %02x] <= %*ph\n",
++		(u32)addr, data_size, data);
++
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: addr=%x, data=%*ph\n",
++			 __func__, ret, (u32)addr, data_size, data);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int gc2145_read_regs(struct gc2145_dev *sensor, u8 addr,
++			    u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg[2];
++	int ret;
++
++	msg[0].addr = client->addr;
++	msg[0].flags = client->flags;
++	msg[0].buf = &addr;
++	msg[0].len = 1;
++
++	msg[1].addr = client->addr;
++	msg[1].flags = client->flags | I2C_M_RD;
++	msg[1].buf = data;
++	msg[1].len = data_size;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: start_index=%x, data_size=%d\n",
++			 __func__, ret, (u32)addr, data_size);
++		return ret;
++	}
++
++	dev_dbg(&sensor->i2c_client->dev, "[rd %02x] => %*ph\n",
++		(u32)addr, data_size, data);
++
++	return 0;
++}
++
++static int gc2145_switch_bank(struct gc2145_dev *sensor, u16 reg)
++{
++	int ret;
++	u8 bank = reg >> 8;
++
++	if (bank & ~3u)
++		return -ERANGE;
++
++	if (sensor->current_bank != bank) {
++		ret = gc2145_write_regs(sensor, GC2145_REG_RESET, &bank, 1);
++		if (ret)
++			return ret;
++
++		sensor->current_bank = bank;
++		dev_info(&sensor->i2c_client->dev, "bank switch: 0x%02x\n",
++				(unsigned int)sensor->current_bank);
++	}
++
++	return 0;
++}
++
++static int gc2145_read(struct gc2145_dev *sensor, u16 reg, u8 *val)
++{
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	return gc2145_read_regs(sensor, reg, val, 1);
++}
++
++static int gc2145_write(struct gc2145_dev *sensor, u16 reg, u8 val)
++{
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	if ((reg & 0xffu) == GC2145_REG_RESET)
++		sensor->current_bank = val & 3;
++
++	return gc2145_write_regs(sensor, reg, &val, 1);
++}
++
++static int gc2145_update_bits(struct gc2145_dev *sensor, u16 reg, u8 mask, u8 val)
++{
++	int ret;
++	u8 tmp;
++
++	ret = gc2145_read(sensor, reg, &tmp);
++	if (ret)
++		return ret;
++
++	tmp &= ~mask;
++	tmp |= val & mask;
++
++	return gc2145_write(sensor, reg, tmp);
++}
++
++static int gc2145_read16(struct gc2145_dev *sensor, u16 reg, u16 *val)
++{
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read_regs(sensor, reg, (u8 *)val, sizeof(*val));
++	if (ret)
++		return ret;
++
++	*val = be16_to_cpu(*val);
++	return 0;
++}
++
++static int gc2145_write16(struct gc2145_dev *sensor, u16 reg, u16 val)
++{
++	u16 tmp = cpu_to_be16(val);
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	return gc2145_write_regs(sensor, reg, (u8 *)&tmp, sizeof(tmp));
++}
++
++static void gc2145_tx_start(struct gc2145_dev *sensor)
++{
++	if (sensor->tx_started++)
++		dev_err(&sensor->i2c_client->dev,
++				"tx_start called multiple times\n");
++
++	sensor->n_ops = 0;
++}
++
++static void gc2145_tx_add(struct gc2145_dev *sensor, int kind,
++			  u16 reg, u16 val, u16 mask)
++{
++	struct gc2145_tx_op *op;
++
++	if (!sensor->tx_started) {
++		dev_err(&sensor->i2c_client->dev,
++				"op added without calling tx_start\n");
++		return;
++	}
++
++	if (sensor->n_ops >= ARRAY_SIZE(sensor->ops)) {
++		dev_err(&sensor->i2c_client->dev,
++				"ops overflow, increase GC2145_MAX_OPS\n");
++		return;
++	}
++
++	op = &sensor->ops[sensor->n_ops++];
++	op->op = kind;
++	op->reg = reg;
++	op->val = val;
++	op->mask = mask;
++}
++
++static void gc2145_tx_write8(struct gc2145_dev *sensor, u16 reg, u8 val)
++{
++	return gc2145_tx_add(sensor, TX_WRITE, reg, val, 0);
++}
++
++static void gc2145_tx_write16(struct gc2145_dev *sensor, u16 reg, u16 val)
++{
++	return gc2145_tx_add(sensor, TX_WRITE16, reg, val, 0);
++}
++
++static void gc2145_tx_update_bits(struct gc2145_dev *sensor, u16 reg,
++				  u8 mask, u8 val)
++{
++	return gc2145_tx_add(sensor, TX_UPDATE_BITS, reg, val, mask);
++}
++
++static int gc2145_tx_commit(struct gc2145_dev *sensor)
++{
++	struct gc2145_tx_op* op;
++	int i, ret, n_ops;
++
++	if (!sensor->tx_started) {
++		dev_err(&sensor->i2c_client->dev,
++				"tx_commit called without tx_start\n");
++		return 0;
++	}
++
++	n_ops = sensor->n_ops;
++	sensor->tx_started = 0;
++	sensor->n_ops = 0;
++
++	for (i = 0; i < n_ops; i++) {
++		op = &sensor->ops[i];
++
++		switch (op->op) {
++		case TX_WRITE:
++			ret = gc2145_write(sensor, op->reg, op->val);
++			break;
++		case TX_WRITE16:
++			ret = gc2145_write16(sensor, op->reg, op->val);
++			break;
++		case TX_UPDATE_BITS:
++			ret = gc2145_update_bits(sensor, op->reg, op->mask, op->val);
++			break;
++		default:
++			dev_err(&sensor->i2c_client->dev, "invalid op at %d\n", i);
++			ret = -EINVAL;
++		}
++
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++/*
++ * Efficiently write to a set of registers, using auto-increment
++ * when possible. User must not use address 0xff. To switch banks,
++ * use sequence: 0xfe, bank_no.
++ */
++static int gc2145_set_registers(struct gc2145_dev *sensor,
++				const uint8_t* data, size_t data_len)
++{
++	int ret = 0, i = 0;
++	u16 start, len;
++	u8 buf[128];
++
++	if (data_len % 2 != 0) {
++		v4l2_err(&sensor->sd, "Register map has invalid size\n");
++		return -EINVAL;
++	}
++
++	/* we speed up communication by using auto-increment functionality */
++	while (i < data_len) {
++		start = data[i];
++		len = 0;
++
++		while (i < data_len && data[i] == (start + len) &&
++		       len < sizeof(buf)) {
++			buf[len++] = data[i + 1];
++			i += 2;
++		}
++
++		ret = gc2145_write_regs(sensor, start, buf, len);
++		if (ret)
++			return ret;
++	}
++
++	sensor->current_bank = 0xff;
++	return 0;
++}
++
++/*
++ * The firmware format:
++ * <record 0>, ..., <record N - 1>
++ * "record" is a 1-byte register address followed by 1-byte data
++ */
++static int gc2145_load_firmware(struct gc2145_dev *sensor, const char *name)
++{
++	const struct firmware *fw;
++	int ret;
++
++	ret = request_firmware(&fw, name, sensor->sd.v4l2_dev->dev);
++	if (ret) {
++		v4l2_warn(&sensor->sd,
++			  "Failed to read firmware %s, continuing anyway...\n",
++			  name);
++		return 1;
++	}
++
++	if (fw->size == 0)
++		return 1;
++
++	ret = gc2145_set_registers(sensor, fw->data, fw->size);
++
++	release_firmware(fw);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Controls */
++
++static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct gc2145_dev,
++			     ctrls.handler)->sd;
++}
++
++#if 0
++static const u8 gc2145_wb_opts[][2] = {
++	{ V4L2_WHITE_BALANCE_MANUAL, GC2145_REG_WB_MODE_OFF },
++	{ V4L2_WHITE_BALANCE_INCANDESCENT, GC2145_REG_WB_MODE_TUNGSTEN_PRESET },
++	{ V4L2_WHITE_BALANCE_FLUORESCENT,
++		GC2145_REG_WB_MODE_FLUORESCENT_PRESET },
++	{ V4L2_WHITE_BALANCE_HORIZON, GC2145_REG_WB_MODE_HORIZON_PRESET },
++	{ V4L2_WHITE_BALANCE_CLOUDY, GC2145_REG_WB_MODE_CLOUDY_PRESET },
++	{ V4L2_WHITE_BALANCE_DAYLIGHT, GC2145_REG_WB_MODE_SUNNY_PRESET },
++	{ V4L2_WHITE_BALANCE_AUTO, GC2145_REG_WB_MODE_AUTOMATIC },
++};
++
++static int gc2145_set_power_line_frequency(struct gc2145_dev *sensor, s32 val)
++{
++	u16 freq;
++	int ret;
++
++	switch (val) {
++	case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
++		ret = gc2145_write(sensor, GC2145_REG_ANTI_FLICKER_MODE, 0);
++		if (ret)
++			return ret;
++
++		return gc2145_write(sensor, GC2145_REG_FD_ENABLE_DETECT, 0);
++	case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
++	case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
++		ret = gc2145_write(sensor, GC2145_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write(sensor, GC2145_REG_FD_ENABLE_DETECT, 0);
++		if (ret)
++			return ret;
++
++		freq = (val == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) ?
++			0x4b20 : 0x4bc0;
++
++		return gc2145_write16(sensor, GC2145_REG_FD_FLICKER_FREQUENCY,
++				      freq);
++	case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
++		ret = gc2145_write(sensor, GC2145_REG_FD_ENABLE_DETECT, 1);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write(sensor, GC2145_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write16(sensor, GC2145_REG_FD_MAX_NUMBER_ATTEMP,
++				     100);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write16(sensor, GC2145_REG_FD_FLICKER_FREQUENCY,
++				     0);
++		if (ret)
++			return ret;
++
++		return gc2145_write(sensor, GC2145_REG_FD_DETECTION_START, 1);
++	default:
++		return -EINVAL;
++	}
++}
++
++static int gc2145_set_colorfx(struct gc2145_dev *sensor, s32 val)
++{
++	int ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++			   GC2145_REG_EFFECTS_COLOR_NORMAL);
++	if (ret)
++		return ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_NEGATIVE, 0);
++	if (ret)
++		return ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_SOLARISING, 0);
++	if (ret)
++		return ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_SKECTH, 0);
++	if (ret)
++		return ret;
++
++	switch (val) {
++	case V4L2_COLORFX_NONE:
++		return 0;
++	case V4L2_COLORFX_NEGATIVE:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_NEGATIVE, 1);
++	case V4L2_COLORFX_SOLARIZATION:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_SOLARISING, 1);
++	case V4L2_COLORFX_SKETCH:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_SKECTH, 1);
++	case V4L2_COLORFX_ANTIQUE:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_ANTIQUE);
++	case V4L2_COLORFX_SEPIA:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_SEPIA);
++	case V4L2_COLORFX_AQUA:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_AQUA);
++	case V4L2_COLORFX_BW:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_BLACK_WHITE);
++	default:
++		return -EINVAL;
++	}
++}
++
++static int gc2145_3a_lock(struct gc2145_dev *sensor, struct v4l2_ctrl *ctrl)
++{
++	bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
++	bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
++	int ret = 0;
++
++	if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE
++	    && sensor->ctrls.auto_exposure->val == V4L2_EXPOSURE_AUTO) {
++		ret = gc2145_write(sensor, GC2145_REG_FREEZE_AUTO_EXPOSURE,
++				   ae_lock);
++		if (ret)
++			return ret;
++	}
++
++	if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE)
++	    && sensor->ctrls.wb->val == V4L2_WHITE_BALANCE_AUTO) {
++		ret = gc2145_write(sensor, GC2145_REG_WB_MISC_SETTINGS,
++				   awb_lock ?
++				   GC2145_REG_WB_MISC_SETTINGS_FREEZE_ALGO : 0);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int gc2145_set_white_balance(struct gc2145_dev *sensor)
++{
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	bool manual_wb = ctrls->wb->val == V4L2_WHITE_BALANCE_MANUAL;
++	int ret = 0, i;
++	s32 val;
++
++	if (ctrls->wb->is_new) {
++		for (i = 0; i < ARRAY_SIZE(gc2145_wb_opts); i++) {
++			if (gc2145_wb_opts[i][0] != ctrls->wb->val)
++				continue;
++
++			ret = gc2145_write(sensor, GC2145_REG_WB_MODE,
++					    gc2145_wb_opts[i][1]);
++			if (ret)
++				return ret;
++			goto next;
++		}
++
++		return -EINVAL;
++	}
++
++next:
++	if (ctrls->wb->is_new || ctrls->blue_balance->is_new) {
++		val = manual_wb ? ctrls->blue_balance->val : 1000;
++		ret = gc2145_write16(sensor, GC2145_REG_WB_HUE_B_BIAS,
++				     gc2145_mili_to_fp16(val));
++		if (ret)
++			return ret;
++	}
++
++	if (ctrls->wb->is_new || ctrls->red_balance->is_new) {
++		val = manual_wb ? ctrls->red_balance->val : 1000;
++		ret = gc2145_write16(sensor, GC2145_REG_WB_HUE_R_BIAS,
++				     gc2145_mili_to_fp16(val));
++	}
++
++	return ret;
++}
++
++#endif
++
++/* Exposure */
++
++static int gc2145_get_exposure(struct gc2145_dev *sensor)
++{
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	u8 again, dgain;
++	u16 exp;
++	int ret;
++
++	ret = gc2145_read(sensor, 0xb1, &again);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read(sensor, 0xb2, &dgain);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read16(sensor, 0x03, &exp);
++	if (ret)
++		return ret;
++
++	ctrls->exposure->val = exp;
++	ctrls->d_gain->val = dgain;
++	ctrls->a_gain->val = again;
++
++	return 0;
++}
++
++#define AE_BIAS_MENU_DEFAULT_VALUE_INDEX 4
++static const s64 ae_bias_menu_values[] = {
++	-4000, -3000, -2000, -1000, 0, 1000, 2000, 3000, 4000
++};
++
++static const s8 ae_bias_menu_reg_values[] = {
++	0x55, 0x60, 0x65, 0x70, 0x7b, 0x85, 0x90, 0x95, 0xa0
++};
++
++static int gc2145_set_exposure(struct gc2145_dev *sensor)
++{
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	bool is_auto = (ctrls->auto_exposure->val != V4L2_EXPOSURE_MANUAL);
++
++	gc2145_tx_start(sensor);
++
++	if (ctrls->auto_exposure->is_new) {
++		gc2145_tx_write8(sensor, 0xb6, is_auto ? 1 : 0);
++
++		//XXX: remove?
++		//if (ctrls->auto_exposure->cur.val != ctrls->auto_exposure->val &&
++		    //!is_auto) {
++			/*
++			 * Hack: At this point, there are current volatile
++			 * values in val, but control framework will not
++			 * update the cur values for our autocluster, as it
++			 * should. I couldn't find the reason. This fixes
++			 * it for our driver. Remove this after the kernel
++			 * is fixed.
++			 */
++			//ctrls->exposure->cur.val = ctrls->exposure->val;
++			//ctrls->d_gain->cur.val = ctrls->d_gain->val;
++			//ctrls->a_gain->cur.val = ctrls->a_gain->val;
++		//}
++	}
++
++	if (!is_auto && ctrls->exposure->is_new)
++		gc2145_tx_write16(sensor, 0x03, ctrls->exposure->val);
++
++	if (!is_auto && ctrls->d_gain->is_new)
++		gc2145_tx_write8(sensor, 0xb2, ctrls->d_gain->val);
++
++	if (!is_auto && ctrls->a_gain->is_new)
++		gc2145_tx_write8(sensor, 0xb1, ctrls->a_gain->val);
++
++	return gc2145_tx_commit(sensor);;
++}
++
++/* Test patterns */
++
++enum {
++	GC2145_TEST_PATTERN_DISABLED,
++	GC2145_TEST_PATTERN_VGA_COLOR_BARS,
++	GC2145_TEST_PATTERN_UXGA_COLOR_BARS,
++	GC2145_TEST_PATTERN_SKIN_MAP,
++	GC2145_TEST_PATTERN_SOLID_COLOR,
++};
++
++static const char * const test_pattern_menu[] = {
++	"Disabled",
++	"VGA color bars",
++	"UXGA color bars",
++	"Skin map",
++	"Solid black color",
++	"Solid light gray color",
++	"Solid gray color",
++	"Solid dark gray color",
++	"Solid white color",
++	"Solid red color",
++	"Solid green color",
++	"Solid blue color",
++	"Solid yellow color",
++	"Solid cyan color",
++	"Solid magenta color",
++};
++
++static int gc2145_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	if (!sensor->powered)
++		return -EIO;
++
++	switch (ctrl->id) {
++	case V4L2_CID_EXPOSURE_AUTO:
++		ret = gc2145_get_exposure(sensor);
++		if (ret)
++			return ret;
++		break;
++	default:
++		dev_err(&sensor->i2c_client->dev, "getting unknown control %d\n", ctrl->id);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int gc2145_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	s32 val = ctrl->val;
++	unsigned int i;
++	int ret;
++	u8 test1, test2;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	/*
++	 * If the device is not powered up by the host driver do
++	 * not apply any controls to H/W at this time. Instead
++	 * the controls will be restored right after power-up.
++	 */
++	if (!sensor->powered)
++		return 0;
++
++	switch (ctrl->id) {
++	case V4L2_CID_EXPOSURE_AUTO:
++		return gc2145_set_exposure(sensor);
++
++	case V4L2_CID_AUTO_EXPOSURE_BIAS:
++		if (val < 0 || val >= ARRAY_SIZE(ae_bias_menu_reg_values)) {
++			dev_err(&sensor->i2c_client->dev, "ae bias out of range\n");
++			return -EINVAL;
++		}
++
++		return gc2145_write(sensor, 0x113,
++				    (u8)ae_bias_menu_reg_values[val]);
++
++	case V4L2_CID_VFLIP:
++		return gc2145_update_bits(sensor, 0x17, BIT(1), val ? BIT(1) : 0);
++
++	case V4L2_CID_HFLIP:
++		return gc2145_update_bits(sensor, 0x17, BIT(0), val ? BIT(0) : 0);
++
++	case V4L2_CID_TEST_PATTERN:
++		for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++			v4l2_ctrl_activate(ctrls->test_data[i],
++					   val == 6); /* solid color */
++
++		test1 = 0;
++		test2 = 0x01;
++
++		if (val == GC2145_TEST_PATTERN_VGA_COLOR_BARS)
++			test1 = 0x04;
++		else if (val == GC2145_TEST_PATTERN_UXGA_COLOR_BARS)
++			test1 = 0x44;
++		else if (val == GC2145_TEST_PATTERN_SKIN_MAP)
++			test1 = 0x10;
++		else if (val >= GC2145_TEST_PATTERN_SOLID_COLOR) {
++			test1 = 0x04;
++			test2 = ((val - GC2145_TEST_PATTERN_SOLID_COLOR) << 4) | 0x8;
++		} else if (val != GC2145_TEST_PATTERN_DISABLED) {
++			dev_err(&sensor->i2c_client->dev, "test pattern out of range\n");
++			return -EINVAL;
++		}
++
++		ret = gc2145_write(sensor, 0x8c, test1);
++		if (ret)
++			return ret;
++
++		return gc2145_write(sensor, 0x8d, test2);
++
++#if 0
++	case V4L2_CID_EXPOSURE_METERING:
++		if (val == V4L2_EXPOSURE_METERING_AVERAGE)
++			reg = GC2145_REG_EXPOSURE_METERING_FLAT;
++		else if (val == V4L2_EXPOSURE_METERING_CENTER_WEIGHTED)
++			reg = GC2145_REG_EXPOSURE_METERING_CENTERED;
++		else
++			return -EINVAL;
++
++		return gc2145_write(sensor, GC2145_REG_EXPOSURE_METERING, reg);
++
++	case V4L2_CID_CONTRAST:
++		return gc2145_write(sensor, GC2145_REG_CONTRAST, val);
++
++	case V4L2_CID_SATURATION:
++		return gc2145_write(sensor, GC2145_REG_COLOR_SATURATION, val);
++
++	case V4L2_CID_BRIGHTNESS:
++		return gc2145_write(sensor, GC2145_REG_BRIGHTNESS, val);
++
++	case V4L2_CID_POWER_LINE_FREQUENCY:
++		return gc2145_set_power_line_frequency(sensor, val);
++
++	case V4L2_CID_GAMMA:
++		return gc2145_write(sensor, GC2145_REG_P0_GAMMA_GAIN, val);
++
++	case V4L2_CID_COLORFX:
++		return gc2145_set_colorfx(sensor, val);
++
++	case V4L2_CID_3A_LOCK:
++		return gc2145_3a_lock(sensor, ctrl);
++
++	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
++		return gc2145_set_white_balance(sensor);
++
++	case V4L2_CID_TEST_PATTERN_RED:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_RED, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENR:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_GREEN_R, val);
++
++	case V4L2_CID_TEST_PATTERN_BLUE:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_BLUE, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENB:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_GREEN_B, val);
++
++#endif
++	default:
++		dev_err(&sensor->i2c_client->dev, "setting unknown control %d\n", ctrl->id);
++		return -EINVAL;
++	}
++}
++
++static const struct v4l2_ctrl_ops gc2145_ctrl_ops = {
++	.g_volatile_ctrl = gc2145_g_volatile_ctrl,
++	.s_ctrl = gc2145_s_ctrl,
++};
++
++static int gc2145_init_controls(struct gc2145_dev *sensor)
++{
++	const struct v4l2_ctrl_ops *ops = &gc2145_ctrl_ops;
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++	//u8 wb_max = 0;
++	//u64 wb_mask = 0;
++	//unsigned int i;
++	int ret;
++
++	v4l2_ctrl_handler_init(hdl, 32);
++
++	/* we can use our own mutex for the ctrl lock */
++	hdl->lock = &sensor->lock;
++
++	/* Exposure controls */
++	ctrls->auto_exposure = v4l2_ctrl_new_std_menu(hdl, ops,
++						      V4L2_CID_EXPOSURE_AUTO,
++						      V4L2_EXPOSURE_MANUAL, 0,
++						      V4L2_EXPOSURE_AUTO);
++	ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
++					    1, 0x1fff, 1, 0x80);
++	ctrls->a_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
++					  0, 255, 1, 0x20);
++	ctrls->d_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_DIGITAL_GAIN,
++					  0, 255, 1, 0x40);
++	ctrls->exposure_bias =
++		v4l2_ctrl_new_int_menu(hdl, ops, V4L2_CID_AUTO_EXPOSURE_BIAS,
++				       ARRAY_SIZE(ae_bias_menu_values) - 1,
++				       AE_BIAS_MENU_DEFAULT_VALUE_INDEX,
++				       ae_bias_menu_values);
++
++	/* V/H flips */
++	ctrls->hflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_HFLIP, 0, 1, 1, 0);
++	ctrls->vflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_VFLIP, 0, 1, 1, 0);
++
++
++	/* Test patterns */
++	ctrls->test_pattern =
++		v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
++					     ARRAY_SIZE(test_pattern_menu) - 1,
++					     0, 0, test_pattern_menu);
++#if 0
++
++	ctrls->metering =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_EXPOSURE_METERING,
++				       V4L2_EXPOSURE_METERING_CENTER_WEIGHTED,
++				       0, V4L2_EXPOSURE_METERING_AVERAGE);
++
++	for (i = 0; i < ARRAY_SIZE(gc2145_wb_opts); i++) {
++		if (wb_max < gc2145_wb_opts[i][0])
++			wb_max = gc2145_wb_opts[i][0];
++		wb_mask |= BIT(gc2145_wb_opts[i][0]);
++	}
++
++	ctrls->wb = v4l2_ctrl_new_std_menu(hdl, ops,
++			V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
++			wb_max, ~wb_mask, V4L2_WHITE_BALANCE_AUTO);
++
++	ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
++						0, 4000, 1, 1000);
++	ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
++					       0, 4000, 1, 1000);
++
++	ctrls->gamma = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA,
++					 0, 31, 1, 20);
++
++	ctrls->colorfx =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX, 15,
++				       ~(BIT(V4L2_COLORFX_NONE) |
++					 BIT(V4L2_COLORFX_NEGATIVE) |
++					 BIT(V4L2_COLORFX_SOLARIZATION) |
++					 BIT(V4L2_COLORFX_SKETCH) |
++					 BIT(V4L2_COLORFX_SEPIA) |
++					 BIT(V4L2_COLORFX_ANTIQUE) |
++					 BIT(V4L2_COLORFX_AQUA) |
++					 BIT(V4L2_COLORFX_BW)),
++				       V4L2_COLORFX_NONE);
++
++	ctrls->pl_freq =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
++				V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
++				V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
++
++	ctrls->brightness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS,
++					      0, 200, 1, 90);
++	ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
++					      0, 200, 1, 110);
++	ctrls->contrast = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST,
++					    0, 200, 1, 108);
++
++	ctrls->aaa_lock = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_3A_LOCK,
++					    0, 0x7, 0, 0);
++
++	for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++		ctrls->test_data[i] =
++			v4l2_ctrl_new_std(hdl, ops,
++					  V4L2_CID_TEST_PATTERN_RED + i,
++					  0, 1023, 1, 0);
++
++	ctrls->af_status->flags |= V4L2_CTRL_FLAG_VOLATILE |
++		V4L2_CTRL_FLAG_READ_ONLY;
++
++	v4l2_ctrl_auto_cluster(3, &ctrls->wb, V4L2_WHITE_BALANCE_MANUAL, false);
++#endif
++
++	v4l2_ctrl_auto_cluster(4, &ctrls->auto_exposure, V4L2_EXPOSURE_MANUAL,
++			       true);
++
++	if (hdl->error) {
++		ret = hdl->error;
++		goto free_ctrls;
++	}
++
++	sensor->sd.ctrl_handler = hdl;
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(hdl);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Video ops */
++
++/*
++ * Clock tree
++ * ----------
++ *
++ *     MCLK pin
++ *         |
++ *  DIV2 (optional)        - Divide input MCLK by 2 when 0xf7[1] == 1
++ *         |
++ *   /- PLL mux -\         - PLL selected by 0xf8[7], otherwise fixed 32x mult
++ *   |           |
++ * PLL           |         - PLL multiplies by 0xf8[5:0]+1 * 4
++ *   |      Fixed 32/48x   - Multiplies 32x when 0xf7[2] == 1 otherwise 48x
++ *    \_________/
++ *         |
++ *       DOUBLE  (div by 4 or 8) based on 0xf7[3]
++ *         |
++ *     /-------\
++ *     |       |
++ * pclk_div  sclk_div
++ *     |       |
++ *   2pclk    sclk
++ */
++__maybe_unused
++static int gc2145_get_2pclk(struct gc2145_dev *sensor, unsigned long* pclk)
++{
++	u8 pll_mode1, pll_mode2, clk_div_mode;
++	bool mclk_div2_en; // 0xf7[1]
++	bool pll_en; // 0xf8[7]
++	bool double_clk; // 0xf7[3]
++	bool fixed_32x; // 0xf7[2]
++	unsigned long pll_mult; // 0xf8[5:0] + 1
++	unsigned long sclk_div; // 1 << (0xf7[5:4] + 1)
++	unsigned long pclk_div; // 0xfa[7:4] + 1
++	unsigned long int_clk;
++	unsigned long mclk;
++        int ret;
++
++	ret = gc2145_read(sensor, 0xf7, &pll_mode1);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read(sensor, 0xf8, &pll_mode2);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read(sensor, 0xfa, &clk_div_mode);
++	if (ret)
++		return ret;
++
++	mclk = clk_get_rate(sensor->xclk);
++	if (mclk == 0)
++		return -EINVAL;
++
++	mclk_div2_en = pll_mode1 & BIT(1);
++	pll_en = pll_mode2 & BIT(7);
++	double_clk = pll_mode1 & BIT(3);
++	fixed_32x = pll_mode1 & BIT(2);
++	pll_mult = (pll_mode2 & 0x3f) + 1;
++	pclk_div = (clk_div_mode >> 4) + 1;
++	sclk_div = 1 << (((pll_mode1 >> 4) & 0x3) + 1);
++
++	int_clk = mclk / (mclk_div2_en ? 2 : 1);
++
++	if (pll_en)
++		int_clk *= pll_mult * 4;
++	else
++		int_clk *= fixed_32x ? 32 : 48;
++
++	int_clk /= double_clk ? 4 : 8;
++
++	if (pclk)
++		*pclk = int_clk / pclk_div;
++
++	return 0;
++}
++
++static int gc2145_set_2pclk(struct gc2145_dev *sensor,
++			    unsigned long *freq, bool apply)
++{
++	unsigned long pll_mult, pll_mult_max, /*sclk_div,*/ pclk_div, pclk2,/* sclk,*/
++		      mclk;
++	unsigned long pll_mult_best = 0, pclk_div_best = 0, diff_best = ULONG_MAX, diff,
++		      pclk2_best = 0;
++	int mclk_div2_en; //, double_clk;
++	int mclk_div2_en_best = 0; //, double_clk_best;
++
++	mclk = clk_get_rate(sensor->xclk);
++	if (mclk == 0)
++		return -EINVAL;
++
++        for (mclk_div2_en = 0; mclk_div2_en <= 1; mclk_div2_en++) {
++		pll_mult_max = 768000000 / 4 / (mclk / (mclk_div2_en ? 2 : 1));
++		if (pll_mult_max > 32)
++			pll_mult_max = 32;
++
++		for (pll_mult = 2; pll_mult <= pll_mult_max; pll_mult++) {
++			for (pclk_div = 1; pclk_div <= 8; pclk_div++) {
++				pclk2 = mclk / (mclk_div2_en ? 2 : 1) * pll_mult / pclk_div;
++
++				if (pclk2 > *freq)
++					continue;
++
++				diff = *freq - pclk2;
++
++				if (diff < diff_best) {
++					diff_best = diff;
++					pclk2_best = pclk2;
++
++					pll_mult_best = pll_mult;
++					pclk_div_best = pclk_div;
++					mclk_div2_en_best = mclk_div2_en;
++				}
++
++				if (diff == 0)
++					goto found;
++			}
++		}
++	}
++
++	if (diff_best == ULONG_MAX)
++		return -1;
++
++found:
++	*freq = pclk2_best;
++	if (!apply)
++		return 0;
++
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, 0xf7,
++			 ((pclk_div_best - 1)) << 4 |
++			 (mclk_div2_en_best << 1) | BIT(0) /* pll_en */);
++	gc2145_tx_write8(sensor, 0xf8, BIT(7) | (pll_mult_best - 1));
++	gc2145_tx_write8(sensor, 0xfa,
++			 (pclk_div_best - 1) << 4 |
++			 (((pclk_div_best - 1) / 2) & 0xf));
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_setup_awb(struct gc2145_dev *sensor,
++			     u16 x1, u16 y1, u16 x2, u16 y2)
++{
++	int ratio = 8; //XXX: manual for gc2035 FAE says 4
++
++	gc2145_tx_start(sensor);
++
++	// disable awb
++	gc2145_tx_update_bits(sensor, 0x82, BIT(1), 0);
++
++	// reset white balance RGB gains
++	gc2145_tx_write8(sensor, 0xb3, 0x40);
++	gc2145_tx_write8(sensor, 0xb4, 0x40);
++	gc2145_tx_write8(sensor, 0xb5, 0x40);
++
++	// awb window
++	gc2145_tx_write8(sensor, 0x1ec, x1 / ratio);
++	gc2145_tx_write8(sensor, 0x1ed, y1 / ratio);
++	gc2145_tx_write8(sensor, 0x1ee, x2 / ratio);
++	gc2145_tx_write8(sensor, 0x1ef, y2 / ratio);
++
++	// eanble awb
++	gc2145_tx_update_bits(sensor, 0x82, BIT(1), BIT(1));
++
++	//1051  { 0xfe, 0x01 },
++	//1052  { 0x74, 0x01 },
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_setup_aec(struct gc2145_dev *sensor,
++			     u16 x1, u16 y1, u16 x2, u16 y2,
++			     u16 cx1, u16 cy1, u16 cx2, u16 cy2)
++{
++        u16 x_ratio = 8;
++
++	//XXX: gc2035 has x ratio 16
++	//XXX: gc2035 doesn't have low light mode
++	gc2145_tx_start(sensor);
++
++	// disable AEC
++	gc2145_tx_write8(sensor, 0xb6, 0);
++
++	// set reasonable initial exposure and gains
++	gc2145_tx_write16(sensor, 0x03, 1200);
++	gc2145_tx_write8(sensor, 0xb1, 0x20);
++	gc2145_tx_write8(sensor, 0xb2, 0xe0);
++
++	// setup measure window
++	gc2145_tx_write8(sensor, 0x101, x1 / x_ratio);
++	gc2145_tx_write8(sensor, 0x102, x2 / x_ratio);
++	gc2145_tx_write8(sensor, 0x103, y1 / 8);
++	gc2145_tx_write8(sensor, 0x104, y2 / 8);
++
++	// setup center
++	gc2145_tx_write8(sensor, 0x105, cx1 / x_ratio);
++	gc2145_tx_write8(sensor, 0x106, cx2 / x_ratio);
++	gc2145_tx_write8(sensor, 0x107, cy1 / 8);
++	gc2145_tx_write8(sensor, 0x108, cy2 / 8);
++
++	// increase maximum exposure level to 4
++	//gc2145_tx_write8(sensor, 0x13c, 0x60);
++	// setup AEC mode: measure point, adjust_max_gain, skip_mode = 2
++	//gc2145_tx_write8(sensor, 0x10a, 0xc2);
++
++	// AEC_ASDE_select_luma_value AEC_low_light_exp_THD_max:
++	//gc2145_tx_write8(sensor, 0x121, 0x15);
++
++	// enable AEC again
++	gc2145_tx_write8(sensor, 0xb6, 1);
++
++	return gc2145_tx_commit(sensor);
++}
++
++struct gc2145_sensor_params {
++	unsigned int enable_scaler;
++	unsigned int col_scaler_only;
++	unsigned int row_skip;
++	unsigned int col_skip;
++	unsigned long sh_delay;
++	unsigned long hb;
++	unsigned long vb;
++	unsigned long st;
++	unsigned long et;
++	unsigned long win_width;
++	unsigned long win_height;
++	unsigned long width;
++	unsigned long height;
++};
++
++static void gc2145_sensor_params_init(struct gc2145_sensor_params* p, int width, int height)
++{
++	p->win_height = height + 32;
++	p->win_width = (width + 16);
++	p->width = width;
++	p->height = height;
++	p->st = 2;
++	p->et = 2;
++	p->vb = 8;
++	p->hb = 0x1f0;
++	p->sh_delay = 30;
++}
++
++// unit is PCLK periods
++static unsigned long
++gc2145_sensor_params_get_row_period(struct gc2145_sensor_params* p)
++{
++	return 2 * (p->win_width / 2 / (p->col_skip + 1) + p->sh_delay + p->hb + 4);
++}
++
++static unsigned long
++gc2145_sensor_params_get_frame_period(struct gc2145_sensor_params* p)
++{
++	unsigned long rt = gc2145_sensor_params_get_row_period(p);
++
++	return rt * (p->vb + p->win_height) / (p->row_skip + 1);
++}
++
++static void
++gc2145_sensor_params_fit_hb_to_power_line_period(struct gc2145_sensor_params* p,
++					  unsigned long power_line_freq,
++					  unsigned long pclk)
++{
++	unsigned long rt, power_line_ratio;
++
++        for (p->hb = 0x1f0; p->hb < 2047; p->hb++) {
++		rt = gc2145_sensor_params_get_row_period(p);
++
++		// power_line_ratio is row_freq / power_line_freq * 1000
++                power_line_ratio = pclk / power_line_freq * 1000 / rt;
++
++		// if we're close enough, stop the search
++                if (power_line_ratio % 1000 < 50)
++                        break;
++        }
++
++	// finding the optimal Hb is not critical
++	if (p->hb == 2047)
++		p->hb = 0x1f0;
++}
++
++static void
++gc2145_sensor_params_fit_vb_to_frame_period(struct gc2145_sensor_params* p,
++				     unsigned long frame_period)
++{
++	unsigned long rt, fp;
++
++	p->vb = 8;
++	rt = gc2145_sensor_params_get_row_period(p);
++	fp = gc2145_sensor_params_get_frame_period(p);
++
++	if (frame_period > fp)
++		p->vb = frame_period * (p->row_skip + 1) / rt - p->win_height;
++
++	if (p->vb > 4095)
++		p->vb = 4095;
++}
++
++static int gc2145_sensor_params_apply(struct gc2145_dev *sensor,
++				      struct gc2145_sensor_params* p)
++{
++	u32 off_x = (GC2145_SENSOR_WIDTH_MAX - p->width) / 2;
++	u32 off_y = (GC2145_SENSOR_HEIGHT_MAX - p->height) / 2;
++
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, 0xfd, (p->enable_scaler ? BIT(0) : 0)
++			| (p->col_scaler_only ? BIT(1) : 0));
++
++	gc2145_tx_write8(sensor, 0x18, 0x0a
++		       | (p->col_skip ? BIT(7) : 0)
++		       | (p->row_skip ? BIT(6) : 0));
++
++	gc2145_tx_write16(sensor, 0x09, off_y);
++	gc2145_tx_write16(sensor, 0x0b, off_x);
++	gc2145_tx_write16(sensor, 0x0d, p->win_height);
++	gc2145_tx_write16(sensor, 0x0f, p->win_width);
++	gc2145_tx_write16(sensor, 0x05, p->hb);
++	gc2145_tx_write16(sensor, 0x07, p->vb);
++	gc2145_tx_write16(sensor, 0x11, p->sh_delay);
++
++	gc2145_tx_write8(sensor, 0x13, p->st);
++	gc2145_tx_write8(sensor, 0x14, p->et);
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_setup_mode(struct gc2145_dev *sensor)
++{
++	int scaling_desired, ret, pad, i;
++	struct gc2145_sensor_params params = {0};
++	unsigned long pclk2, frame_period;
++	unsigned long power_line_freq = 50;
++	unsigned long width = sensor->fmt.width;
++	unsigned long height = sensor->fmt.height;
++	unsigned long framerate = sensor->frame_interval.denominator;
++	const struct gc2145_pixfmt *pix_fmt;
++	unsigned long rt, ft, ft_rt;
++
++	pix_fmt = gc2145_find_format(sensor->fmt.code);
++	if (!pix_fmt) {
++		dev_err(&sensor->i2c_client->dev,
++			"pixel format not supported %u\n", sensor->fmt.code);
++		return -EINVAL;
++	}
++
++        /*
++	 * Equations for calculating framerate are:
++	 *
++	 *    ww = width + 16
++	 *    wh = height + 32
++	 *    Rt = (ww / 2 / (col_skip + 1) + sh_delay + Hb + 4)
++	 *    Ft = Rt * (Vb + wh) / (row_skip + 1)
++	 *    framerate = 2pclk / 4 / Ft
++	 *
++	 * Based on these equations:
++	 *
++	 * 1) First we need to determine what 2PCLK frequency to use. The 2PCLK
++	 *    frequency is not arbitrarily precise, so we need to calculate the
++	 *    actual frequency used, after setting our target frequency.
++	 *
++	 *    We use a simple heuristic:
++	 *
++	 *      If pixel_count * 2 * framerate * 1.15 is > 40MHz, we use 60MHz,
++	 *      otherwise we use 40MHz.
++	 *
++	 * 2) We want to determine lowest Hb that we can use to extend row
++	 *    period so that row time takes an integer fraction of the power
++	 *    line frequency period. Minimum Hb is 0x1f0.
++	 *
++	 * 3) If the requested resolution is less than half the sensor's size,
++	 *    we'll use scaling, or row skipping + column scaling, or row and
++	 *    column skiping, depending on what allows us to achieve the
++	 *    requested framerate.
++         *
++	 * 4) We use the selected Hb to calculate Vb value that will give
++	 *    us the desired framerate, given the scaling/skipping option
++	 *    selected in 3).
++	 */
++
++	scaling_desired = width <= GC2145_SENSOR_WIDTH_MAX / 2
++			&& height <= GC2145_SENSOR_HEIGHT_MAX / 2;
++
++	pclk2 = 60000000;
++
++	ret = gc2145_set_2pclk(sensor, &pclk2, false);
++	if (ret < 0)
++		return ret;
++
++	gc2145_sensor_params_init(&params, width, height);
++
++	// if the resolution is < half the sensor size, enable the scaler
++	// to cover more area of the chip
++	if (scaling_desired) {
++		params.enable_scaler = 1;
++		pclk2 *= 2;
++		gc2145_sensor_params_init(&params, width * 2, height * 2);
++	}
++
++	// we need to call this each time pclk or power_line_freq is changed
++	gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++							 power_line_freq,
++							 pclk2 / 2);
++
++	frame_period = gc2145_sensor_params_get_frame_period(&params);
++	if (framerate <= pclk2 / 2 / frame_period)
++		goto apply;
++
++	if (scaling_desired) {
++		// try using just the column scaler + row skip
++		params.col_scaler_only = 1;
++		params.row_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++								 power_line_freq,
++								 pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++		if (framerate <= pclk2 / 2 / frame_period)
++			goto apply;
++
++
++		/*
++		// try disabling the scaler and just use skipping
++		params.enable_scaler = 0;
++		pclk2 /= 2;
++		params.col_scaler_only = 0;
++		params.col_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params, power_line_freq, pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++
++		if (framerate <= pclk2 / 2 / frame_period)
++			goto apply;
++                  */
++	}
++
++apply:
++        // adjust vb to fit the target framerate
++	gc2145_sensor_params_fit_vb_to_frame_period(&params,
++						    pclk2 / 2 / framerate);
++
++	gc2145_sensor_params_apply(sensor, &params);
++
++	ret = gc2145_set_2pclk(sensor, &pclk2, true);
++	if (ret < 0)
++		return ret;
++
++	pad = (width > 256 && height > 256) ? 32 : 16;
++
++	ret = gc2145_setup_awb(sensor, pad, pad, width - pad * 2, height - pad * 2);
++	if (ret)
++		return ret;
++
++	ret = gc2145_setup_aec(sensor,
++				pad, pad, width - pad * 2, height - pad * 2,
++				2 * pad, 2 * pad, width - pad * 4, height - pad * 4);
++	if (ret)
++		return ret;
++
++	gc2145_tx_start(sensor);
++
++	// anti-flicker step
++	//gc2145_tx_write16(sensor, 0x125, 360); //XXX: get this from the calculator (hb related)
++
++	//XXX: calculate auto exposure settings, there are 4 slots that the HW
++	//uses and exposure settings are set in row_time units
++
++	rt = gc2145_sensor_params_get_row_period(&params);
++	ft = gc2145_sensor_params_get_frame_period(&params);
++	ft_rt = ft / rt / 4;
++
++	for (i = 0; i < 7; i++) {
++		// exposure settings for exposure levels
++		gc2145_tx_write16(sensor, 0x127 + 2 * i, ft_rt * (i + 1));
++		// max dg gains
++		gc2145_tx_write8(sensor, 0x135 + i, 0x50);
++	}
++
++	// max analog gain
++	gc2145_tx_write8(sensor, 0x11f, 0x50);
++	// max digital gain
++	gc2145_tx_write8(sensor, 0x120, 0xe0);
++
++	gc2145_tx_write8(sensor, GC2145_P0_ISP_OUT_FORMAT, pix_fmt->fmt_setup);
++
++	// set gamma curve
++	gc2145_tx_update_bits(sensor, 0x80, BIT(6), BIT(6));
++
++	// disable denoising
++	gc2145_tx_update_bits(sensor, 0x80, BIT(2), 0);
++
++	// drive strength
++	gc2145_tx_write8(sensor, 0x24,
++			 (pclk2 / (params.enable_scaler + 1)) > 40000000 ?
++				0xff : 0x55);
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_set_stream(struct gc2145_dev *sensor, int enable)
++{
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, GC2145_REG_PAD_IO, enable ? 0x0f : 0);
++
++	//XXX: maybe disable cam module function blocks that are not used
++	//and downclock the PLL/disable it when not streaming?
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	if (sensor->streaming == !enable) {
++		if (enable && sensor->pending_mode_change) {
++			ret = gc2145_setup_mode(sensor);
++			if (ret)
++				goto out;
++		}
++
++		ret = gc2145_set_stream(sensor, enable);
++		if (ret)
++			goto out;
++
++		sensor->streaming = !!enable;
++	}
++
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Pad ops */
++
++static int gc2145_get_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	fi->interval = sensor->frame_interval;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int gc2145_set_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret = 0, fps;
++	struct gc2145_sensor_params params;
++	unsigned long pixel_rate;
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++
++	/* user requested infinite frame rate */
++	if (fi->interval.numerator == 0)
++		fps = 60;
++	else
++		fps = DIV_ROUND_CLOSEST(fi->interval.denominator,
++					fi->interval.numerator);
++
++	fps = clamp(fps, 1, 60);
++
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = fps;
++	fi->interval = sensor->frame_interval;
++
++	params = gc2145_get_sensor_params(fps, sensor->fmt.width, sensor->fmt.height, &pixel_rate);
++	__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
++				 pixel_rate);
++
++#if 0
++	if (sensor->streaming) {
++		ret = gc2145_write16(sensor, GC2145_REG_DESIRED_FRAME_RATE_NUM,
++				     fps);
++		if (ret)
++			goto err_unlock;
++	}
++err_unlock:
++#endif
++
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++static int gc2145_enum_mbus_code(struct v4l2_subdev *sd,
++				 struct v4l2_subdev_state *sd_state,
++				 struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad != 0 || code->index >= ARRAY_SIZE(gc2145_formats))
++		return -EINVAL;
++
++	code->code = gc2145_formats[code->index].code;
++
++	return 0;
++}
++
++static int gc2145_enum_frame_size(struct v4l2_subdev *sd,
++				  struct v4l2_subdev_state *sd_state,
++				  struct v4l2_subdev_frame_size_enum *fse)
++{
++	if (fse->pad != 0 || fse->index > 0)
++		return -EINVAL;
++
++	fse->min_width = GC2145_SENSOR_WIDTH_MIN;
++	fse->max_width = GC2145_SENSOR_WIDTH_MAX;
++
++	fse->min_height = GC2145_SENSOR_HEIGHT_MIN;
++	fse->max_height = GC2145_SENSOR_HEIGHT_MAX;
++
++	return 0;
++}
++
++static int gc2145_enum_frame_interval(
++	struct v4l2_subdev *sd,
++	struct v4l2_subdev_state *sd_state,
++	struct v4l2_subdev_frame_interval_enum *fie)
++{
++	if (fie->pad != 0 || fie->index > 0)
++		return -EINVAL;
++
++	fie->interval.numerator = 1;
++	fie->interval.denominator = 30;
++
++	return 0;
++}
++
++static int gc2145_get_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	struct v4l2_mbus_framefmt *mf;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		format->format = *mf;
++		return 0;
++	}
++
++	mutex_lock(&sensor->lock);
++	format->format = sensor->fmt;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int gc2145_set_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	const struct gc2145_pixfmt *pixfmt;
++	int ret = 0;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	/* check if we support requested mbus fmt */
++	pixfmt = gc2145_find_format(mf->code);
++	if (!pixfmt)
++		pixfmt = &gc2145_formats[0];
++
++	mf->code = pixfmt->code;
++	mf->colorspace = pixfmt->colorspace;
++	mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
++	mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++	mf->quantization = V4L2_QUANTIZATION_DEFAULT;
++	mf->field = V4L2_FIELD_NONE;
++
++	mutex_lock(&sensor->lock);
++
++	mf->width = clamp(mf->width, GC2145_SENSOR_WIDTH_MIN,
++		      GC2145_SENSOR_WIDTH_MAX);
++	mf->height = clamp(mf->height, GC2145_SENSOR_HEIGHT_MIN,
++		       GC2145_SENSOR_HEIGHT_MAX);
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		struct v4l2_mbus_framefmt *try_mf;
++
++		try_mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		*try_mf = *mf;
++		goto out;
++	}
++
++	if (sensor->streaming) {
++		ret = -EBUSY;
++		goto out;
++	}
++
++	sensor->fmt = *mf;
++	sensor->pending_mode_change = true;
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Core Ops */
++
++static int gc2145_configure(struct gc2145_dev *sensor)
++{
++	struct v4l2_mbus_config_parallel *bus = &sensor->ep.bus.parallel;
++	u8 sync_mode = 0;
++	u16 chip_id;
++	int ret;
++
++	ret = gc2145_read16(sensor, GC2145_REG_CHIP_ID, &chip_id);
++	if (ret)
++		return ret;
++
++	dev_info(&sensor->i2c_client->dev, "device id: 0x%04x\n",
++		 (unsigned int)chip_id);
++
++	if (chip_id != GC2145_REG_CHIP_ID_VALUE) {
++		dev_err(&sensor->i2c_client->dev,
++			"unsupported device id: 0x%04x\n",
++			(unsigned int)chip_id);
++		return -EINVAL;
++	}
++
++        // setup parallel bus
++
++	if (bus->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
++		sync_mode |= 0x01;
++
++	if (bus->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
++		sync_mode |= 0x02;
++
++	if (bus->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
++		sync_mode |= 0x04;
++
++	gc2145_tx_start(sensor);
++
++	// soft reset
++	gc2145_tx_write8(sensor, GC2145_REG_RESET, 0xf0);
++
++	// enable analog/digital parts
++	gc2145_tx_write8(sensor, GC2145_REG_ANALOG_PWC, 0x06);
++
++	// safe initial PLL setting
++	gc2145_tx_write8(sensor, GC2145_REG_PLL_MODE1, 0x1d);
++	gc2145_tx_write8(sensor, GC2145_REG_PLL_MODE2, 0x84);
++	gc2145_tx_write8(sensor, GC2145_REG_CLK_DIV_MODE, 0x00);
++
++	gc2145_tx_write8(sensor, GC2145_REG_CM_MODE, 0xfe);
++
++	// disable pads
++	gc2145_tx_write8(sensor, GC2145_REG_PAD_IO, 0);
++
++	gc2145_tx_write8(sensor, 0x19, 0x0c); // set AD pipe number
++	gc2145_tx_write8(sensor, 0x20, 0x01); // AD clk mode
++
++	// enable defect correction, etc.
++	gc2145_tx_write8(sensor, 0x80, 0x0b);
++
++	gc2145_tx_write8(sensor, GC2145_P0_SYNC_MODE, sync_mode);
++
++	ret = gc2145_tx_commit(sensor);
++	if (ret)
++		return ret;
++
++	// load default register values from the firmware file
++	ret = gc2145_load_firmware(sensor, GC2145_FIRMWARE_PARAMETERS);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int gc2145_set_power(struct gc2145_dev *sensor, bool on)
++{
++	int ret = 0;
++
++	if (on) {
++		ret = regulator_bulk_enable(GC2145_NUM_SUPPLIES,
++					    sensor->supplies);
++		if (ret)
++			return ret;
++
++		ret = clk_set_rate(sensor->xclk, 24000000);
++		if (ret)
++			goto xclk_off;
++
++		ret = clk_prepare_enable(sensor->xclk);
++		if (ret)
++			goto power_off;
++
++		usleep_range(10000, 12000);
++		gpiod_direction_output(sensor->reset_gpio, 1);
++		usleep_range(10000, 12000);
++		gpiod_direction_output(sensor->enable_gpio, 1);
++		usleep_range(10000, 12000);
++		gpiod_direction_output(sensor->reset_gpio, 0);
++		usleep_range(40000, 50000);
++
++		ret = gc2145_configure(sensor);
++		if (ret)
++			goto xclk_off;
++
++		ret = gc2145_setup_mode(sensor);
++		if (ret)
++			goto xclk_off;
++
++		return 0;
++	}
++
++xclk_off:
++	clk_disable_unprepare(sensor->xclk);
++power_off:
++	gpiod_direction_input(sensor->reset_gpio);
++	gpiod_direction_input(sensor->enable_gpio);
++	regulator_bulk_disable(GC2145_NUM_SUPPLIES, sensor->supplies);
++	msleep(100);
++	return ret;
++}
++
++static int gc2145_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	bool power_up, power_down;
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	power_up = on && !sensor->powered;
++	power_down = !on && sensor->powered;
++
++	if (power_up || power_down) {
++		ret = gc2145_set_power(sensor, power_up);
++		if (!ret)
++			sensor->powered = on;
++	}
++
++	mutex_unlock(&sensor->lock);
++
++	if (!ret && power_up) {
++		/* restore controls */
++		ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
++		if (ret)
++			gc2145_s_power(sd, 0);
++	}
++
++	return ret;
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int gc2145_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret;
++	u8 val = 0;
++
++	if (reg->reg > 0xffff)
++		return -EINVAL;
++
++	reg->size = 1;
++
++	mutex_lock(&sensor->lock);
++	ret = gc2145_read(sensor, reg->reg, &val);
++	mutex_unlock(&sensor->lock);
++	if (ret)
++		return -EIO;
++
++	reg->val = val;
++	return 0;
++}
++
++static int gc2145_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret;
++
++	if (reg->reg > 0xffff || reg->val > 0xff)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	ret = gc2145_write(sensor, reg->reg, reg->val);
++	mutex_unlock(&sensor->lock);
++
++	return ret;
++}
++#endif
++
++/* }}} */
++
++static const struct v4l2_subdev_core_ops gc2145_core_ops = {
++	.s_power = gc2145_s_power,
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = gc2145_g_register,
++	.s_register = gc2145_s_register,
++#endif
++};
++
++static const struct v4l2_subdev_pad_ops gc2145_pad_ops = {
++	.enum_mbus_code = gc2145_enum_mbus_code,
++	.enum_frame_size = gc2145_enum_frame_size,
++	.enum_frame_interval = gc2145_enum_frame_interval,
++	.get_fmt = gc2145_get_fmt,
++	.set_fmt = gc2145_set_fmt,
++	.get_frame_interval = gc2145_get_frame_interval,
++	.set_frame_interval = gc2145_set_frame_interval,
++};
++
++static const struct v4l2_subdev_video_ops gc2145_video_ops = {
++	.s_stream = gc2145_s_stream,
++};
++
++static const struct v4l2_subdev_ops gc2145_subdev_ops = {
++	.core = &gc2145_core_ops,
++	.pad = &gc2145_pad_ops,
++	.video = &gc2145_video_ops,
++};
++
++static int gc2145_get_regulators(struct gc2145_dev *sensor)
++{
++	int i;
++
++	for (i = 0; i < GC2145_NUM_SUPPLIES; i++)
++		sensor->supplies[i].supply = gc2145_supply_name[i];
++
++	return devm_regulator_bulk_get(&sensor->i2c_client->dev,
++				       GC2145_NUM_SUPPLIES,
++				       sensor->supplies);
++}
++
++static int gc2145_probe(struct i2c_client *client)
++{
++	struct device *dev = &client->dev;
++	struct fwnode_handle *endpoint;
++	struct gc2145_dev *sensor;
++	int ret;
++
++	sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
++	if (!sensor)
++		return -ENOMEM;
++
++	sensor->i2c_client = client;
++
++	sensor->fmt.code = gc2145_formats[0].code;
++	sensor->fmt.width = 1600;
++	sensor->fmt.height = 1200;
++	sensor->fmt.field = V4L2_FIELD_NONE;
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = 10;
++	sensor->pending_mode_change = true;
++	sensor->current_bank = 0xff;
++
++	endpoint = fwnode_graph_get_next_endpoint(
++		of_fwnode_handle(client->dev.of_node), NULL);
++	if (!endpoint) {
++		dev_err(dev, "endpoint node not found\n");
++		return -EINVAL;
++	}
++
++	ret = v4l2_fwnode_endpoint_parse(endpoint, &sensor->ep);
++	fwnode_handle_put(endpoint);
++	if (ret) {
++		dev_err(dev, "could not parse endpoint\n");
++		return ret;
++	}
++
++	if (sensor->ep.bus_type != V4L2_MBUS_PARALLEL) {
++		dev_err(dev, "unsupported bus type %d\n", sensor->ep.bus_type);
++		return -EINVAL;
++	}
++
++	sensor->xclk = devm_clk_get(dev, "xclk");
++	if (IS_ERR(sensor->xclk)) {
++		dev_err(dev, "failed to get xclk\n");
++		return PTR_ERR(sensor->xclk);
++	}
++
++	sensor->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_IN);
++	if (IS_ERR(sensor->enable_gpio)) {
++		dev_err(dev, "failed to get enable gpio\n");
++		return PTR_ERR(sensor->enable_gpio);
++	}
++
++	sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_IN);
++	if (IS_ERR(sensor->reset_gpio)) {
++		dev_err(dev, "failed to get reset gpio\n");
++		return PTR_ERR(sensor->reset_gpio);
++	}
++
++	if (!sensor->enable_gpio || !sensor->reset_gpio) {
++		dev_err(dev, "enable and reset pins must be configured\n");
++		return ret;
++	}
++
++	v4l2_i2c_subdev_init(&sensor->sd, client, &gc2145_subdev_ops);
++
++	sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
++	sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
++	if (ret)
++		return ret;
++
++	mutex_init(&sensor->lock);
++
++	ret = gc2145_get_regulators(sensor);
++	if (ret)
++		goto entity_cleanup;
++
++	ret = gc2145_init_controls(sensor);
++	if (ret)
++		goto entity_cleanup;
++
++	ret = v4l2_async_register_subdev(&sensor->sd);
++	if (ret)
++		goto free_ctrls;
++
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++entity_cleanup:
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	return ret;
++}
++
++static void gc2145_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++
++	v4l2_async_unregister_subdev(&sensor->sd);
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++}
++
++static const struct i2c_device_id gc2145_id[] = {
++	{"gc2145", 0},
++	{},
++};
++MODULE_DEVICE_TABLE(i2c, gc2145_id);
++
++static const struct of_device_id gc2145_dt_ids[] = {
++	{ .compatible = "galaxycore,gc2145" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, gc2145_dt_ids);
++
++static struct i2c_driver gc2145_i2c_driver = {
++	.driver = {
++		.name  = "gc2145",
++		.of_match_table	= gc2145_dt_ids,
++	},
++	.id_table = gc2145_id,
++	.probe    = gc2145_probe,
++	.remove   = gc2145_remove,
++};
++
++module_i2c_driver(gc2145_i2c_driver);
++
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("GC2145 Camera Subdev Driver");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-fix-white-balance-colors.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-fix-white-balance-colors.patch
new file mode 100644
index 000000000000..fd1e60efc76d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-fix-white-balance-colors.patch
@@ -0,0 +1,183 @@
+From 12bf46f4ab0af76d1ad034d264798e2afac1a8ca Mon Sep 17 00:00:00 2001
+From: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+Date: Sat, 26 Aug 2023 12:10:49 +0300
+Subject: media: gc2145: fix white-balance colors
+
+awb initialization settings were taken from gc2145.c driver developed
+by STMicroelectronics with a help of Galaxycore. Most of these
+registers are not documented in a publicly available gc2145
+documentation.
+
+Don't reset white balance gains, exposure and gains on every stream
+start. That keeps old values set by AWB/AEC previously and makes
+AWB/AEC algorithms achieve correct settings on stream restart faster.
+
+For Megapixels DCP calibration file for front camera has to be removed
+to get good quality pictures.
+```
+rm /usr/share/megapixels/config/pine64,pinephone,front.dcp
+```
+
+Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+---
+ drivers/media/i2c/gc2145.c | 118 ++++++++++++++++++++++++++++++-------
+ 1 file changed, 97 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index 429d86bf5f01..b505b3f07387 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -1,6 +1,7 @@
+ /*
+  * Galaxycore GC2145 driver.
+  * Copyright (C) 2018 Ondřej Jirman <megi@xff.cz>.
++ * Copyright (C) 2022, STMicroelectronics SA
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -1556,34 +1557,114 @@ static int gc2145_set_2pclk(struct gc2145_dev *sensor,
+ 	return gc2145_tx_commit(sensor);
+ }
+ 
++struct gc2145_reg {
++	unsigned char address;
++	unsigned char val;
++};
++
++static const struct gc2145_reg gc2145_awb_regs[] = {
++	{0xfe, 0x01},
++	{0x4f, 0x00}, {0x4f, 0x00}, {0x4b, 0x01}, {0x4f, 0x00},
++	{0x4c, 0x01}, {0x4d, 0x71}, {0x4e, 0x01},
++	{0x4c, 0x01}, {0x4d, 0x91}, {0x4e, 0x01},
++	{0x4c, 0x01}, {0x4d, 0x70}, {0x4e, 0x01},
++	{0x4c, 0x01}, {0x4d, 0x90}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xb0}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0x8f}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0x6f}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xaf}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xd0}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xf0}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xcf}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xef}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0x6e}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8e}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xae}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xce}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x4d}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x6d}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8d}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xad}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xcd}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x4c}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x6c}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8c}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xac}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xcc}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xcb}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x4b}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x6b}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8b}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xab}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8a}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xaa}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xca}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xca}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xc9}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0x8a}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0x89}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xa9}, {0x4e, 0x04},
++	{0x4c, 0x02}, {0x4d, 0x0b}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x0a}, {0x4e, 0x05},
++	{0x4c, 0x01}, {0x4d, 0xeb}, {0x4e, 0x05},
++	{0x4c, 0x01}, {0x4d, 0xea}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x09}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x29}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x2a}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x4a}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x8a}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x49}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x69}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x89}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0xa9}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x48}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x68}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x69}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0xca}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xc9}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xe9}, {0x4e, 0x07},
++	{0x4c, 0x03}, {0x4d, 0x09}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xc8}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xe8}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xa7}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xc7}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xe7}, {0x4e, 0x07},
++	{0x4c, 0x03}, {0x4d, 0x07}, {0x4e, 0x07},
++	{0x4f, 0x01},
++	{0x50, 0x80}, {0x51, 0xa8}, {0x52, 0x47}, {0x53, 0x38},
++	{0x54, 0xc7}, {0x56, 0x0e}, {0x58, 0x08}, {0x5b, 0x00},
++	{0x5c, 0x74}, {0x5d, 0x8b}, {0x61, 0xdb}, {0x62, 0xb8},
++	{0x63, 0x86}, {0x64, 0xc0}, {0x65, 0x04}, {0x67, 0xa8},
++	{0x68, 0xb0}, {0x69, 0x00}, {0x6a, 0xa8}, {0x6b, 0xb0},
++	{0x6c, 0xaf}, {0x6d, 0x8b}, {0x6e, 0x50}, {0x6f, 0x18},
++	{0x73, 0xf0}, {0x70, 0x0d}, {0x71, 0x60}, {0x72, 0x80},
++	{0x74, 0x01}, {0x75, 0x01}, {0x7f, 0x0c}, {0x76, 0x70},
++	{0x77, 0x58}, {0x78, 0xa0}, {0x79, 0x5e}, {0x7a, 0x54},
++	{0x7b, 0x58},
++	{0xfe, 0x00},
++};
++
+ static int gc2145_setup_awb(struct gc2145_dev *sensor,
+ 			     u16 x1, u16 y1, u16 x2, u16 y2)
+ {
+ 	int ratio = 8; //XXX: manual for gc2035 FAE says 4
+ 
+-	gc2145_tx_start(sensor);
+-
+ 	// disable awb
+-	gc2145_tx_update_bits(sensor, 0x82, BIT(1), 0);
++	gc2145_update_bits(sensor, 0x82, BIT(1), 0);
+ 
+-	// reset white balance RGB gains
+-	gc2145_tx_write8(sensor, 0xb3, 0x40);
+-	gc2145_tx_write8(sensor, 0xb4, 0x40);
+-	gc2145_tx_write8(sensor, 0xb5, 0x40);
++	// load awb settings
++	gc2145_set_registers(sensor, (void*)gc2145_awb_regs, sizeof(gc2145_awb_regs));
+ 
+ 	// awb window
+-	gc2145_tx_write8(sensor, 0x1ec, x1 / ratio);
+-	gc2145_tx_write8(sensor, 0x1ed, y1 / ratio);
+-	gc2145_tx_write8(sensor, 0x1ee, x2 / ratio);
+-	gc2145_tx_write8(sensor, 0x1ef, y2 / ratio);
++	gc2145_write(sensor, 0x1ec, x1 / ratio);
++	gc2145_write(sensor, 0x1ed, y1 / ratio);
++	gc2145_write(sensor, 0x1ee, x2 / ratio);
++	gc2145_write(sensor, 0x1ef, y2 / ratio);
+ 
+ 	// eanble awb
+-	gc2145_tx_update_bits(sensor, 0x82, BIT(1), BIT(1));
+-
+-	//1051  { 0xfe, 0x01 },
+-	//1052  { 0x74, 0x01 },
++	gc2145_update_bits(sensor, 0x82, BIT(1), BIT(1));
+ 
+-	return gc2145_tx_commit(sensor);
++	return 0;
+ }
+ 
+ static int gc2145_setup_aec(struct gc2145_dev *sensor,
+@@ -1599,11 +1680,6 @@ static int gc2145_setup_aec(struct gc2145_dev *sensor,
+ 	// disable AEC
+ 	gc2145_tx_write8(sensor, 0xb6, 0);
+ 
+-	// set reasonable initial exposure and gains
+-	gc2145_tx_write16(sensor, 0x03, 1200);
+-	gc2145_tx_write8(sensor, 0xb1, 0x20);
+-	gc2145_tx_write8(sensor, 0xb2, 0xe0);
+-
+ 	// setup measure window
+ 	gc2145_tx_write8(sensor, 0x101, x1 / x_ratio);
+ 	gc2145_tx_write8(sensor, 0x102, x2 / x_ratio);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-implement-system-suspend.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-implement-system-suspend.patch
new file mode 100644
index 000000000000..aabe67114711
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-gc2145-implement-system-suspend.patch
@@ -0,0 +1,72 @@
+From 437dd1d9cf44769126a0fb7766528e0842f5ebc8 Mon Sep 17 00:00:00 2001
+From: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+Date: Mon, 14 Aug 2023 13:27:08 +0300
+Subject: media: gc2145: implement system suspend
+
+If system was suspended while camera sensor was used, data and
+interrupts were still coming from sensor and that caused unstable
+system. Sometimes system hanged during a resume.
+
+Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+---
+ drivers/media/i2c/gc2145.c | 37 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index 749dce832aa0..429d86bf5f01 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -2275,6 +2275,42 @@ static void gc2145_remove(struct i2c_client *client)
+ 	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
+ }
+ 
++static int gc2145_sensor_suspend(struct device *dev)
++{
++	struct v4l2_subdev *sd = dev_get_drvdata(dev);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++
++	mutex_lock(&sensor->lock);
++	if (sensor->streaming)
++		gc2145_set_stream(sensor, false);
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int gc2145_sensor_resume(struct device *dev)
++{
++	struct v4l2_subdev *sd = dev_get_drvdata(dev);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++	if (sensor->streaming) {
++		ret = gc2145_set_stream(sensor, true);
++		if (ret) {
++			gc2145_set_stream(sensor, false);
++			sensor->streaming = false;
++		}
++	}
++	mutex_unlock(&sensor->lock);
++
++	return ret;
++}
++
++static const struct dev_pm_ops gc2145_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(gc2145_sensor_suspend, gc2145_sensor_resume)
++};
++
+ static const struct i2c_device_id gc2145_id[] = {
+ 	{"gc2145", 0},
+ 	{},
+@@ -2291,6 +2327,7 @@ static struct i2c_driver gc2145_i2c_driver = {
+ 	.driver = {
+ 		.name  = "gc2145",
+ 		.of_match_table	= gc2145_dt_ids,
++		.pm = &gc2145_pm_ops,
+ 	},
+ 	.id_table = gc2145_id,
+ 	.probe    = gc2145_probe,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
new file mode 100644
index 000000000000..ce2456c005b0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
@@ -0,0 +1,2268 @@
+From 96b8cce951b821b389ea17ce0ebf5962ae308ee5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 30 Sep 2017 02:39:48 +0200
+Subject: media: hm5065: Add subdev driver for Himax HM5065 camera sensor
+
+HM5065 is 5MP CMOS sensor. This driver implements support for
+V4L2_MBUS_PARALLEL bus type only. The driver  Other features:
+
+- External clock rates support from 6-27MHz (discrete values)
+- Resolution support from 2592x1944 to 88x72
+- Frame rates are available depending on the PCLK frequency
+  (from VGA@120 to 2592x1944@8)
+- Support for several YUV and RGB media bus formats
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/Kconfig  |   10 +
+ drivers/media/i2c/Makefile |    1 +
+ drivers/media/i2c/hm5065.c | 2207 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 2218 insertions(+)
+ create mode 100644 drivers/media/i2c/hm5065.c
+
+diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
+index 742bc665602e..00da6022ddd2 100644
+--- a/drivers/media/i2c/Kconfig
++++ b/drivers/media/i2c/Kconfig
+@@ -670,6 +670,16 @@ config VIDEO_ST_VGXY61
+ source "drivers/media/i2c/ccs/Kconfig"
+ source "drivers/media/i2c/et8ek8/Kconfig"
+ 
++config VIDEO_HM5065
++	tristate "Himax HM5065 sensor support"
++	depends on I2C
++	select V4L2_FWNODE
++	select VIDEO_V4L2_SUBDEV_API
++	select MEDIA_CONTROLLER
++	help
++	  This is a V4L2 sensor-level driver for Himax HM5065
++	  5 Mpixel camera.
++
+ endif
+ 
+ menu "Camera ISPs"
+diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
+index dfbe6448b549..aed36d8be369 100644
+--- a/drivers/media/i2c/Makefile
++++ b/drivers/media/i2c/Makefile
+@@ -152,3 +152,4 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o
+ obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o
+ obj-$(CONFIG_VIDEO_WM8739) += wm8739.o
+ obj-$(CONFIG_VIDEO_WM8775) += wm8775.o
++obj-$(CONFIG_VIDEO_HM5065)	+= hm5065.o
+diff --git a/drivers/media/i2c/hm5065.c b/drivers/media/i2c/hm5065.c
+new file mode 100644
+index 000000000000..a3500a4c1441
+--- /dev/null
++++ b/drivers/media/i2c/hm5065.c
+@@ -0,0 +1,2207 @@
++/*
++ * Himax HM5065 driver.
++ * Copyright (C) 2017-2019 Ondřej Jirman <megi@xff.cz>.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <asm/div64.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/clkdev.h>
++#include <linux/ctype.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/firmware.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++#include <media/v4l2-subdev.h>
++
++#define HM5065_AF_FIRMWARE		"hm5065-af.bin"
++#define HM5065_FIRMWARE_PARAMETERS	"hm5065-init.bin"
++
++#define HM5065_SENSOR_WIDTH	2592u
++#define HM5065_SENSOR_HEIGHT	1944u
++#define HM5065_CAPTURE_WIDTH_MIN	88u
++#define HM5065_CAPTURE_HEIGHT_MIN	72u
++
++/* {{{ Register definitions */
++
++/* registers are assumed to be u8 unless otherwise specified */
++
++/* device parameters */
++#define HM5065_REG_DEVICE_ID			0x0000 /* u16 */
++#define HM5065_REG_DEVICE_ID_VALUE		0x039e
++#define HM5065_REG_FIRMWARE_VSN			0x0002
++#define HM5065_REG_PATCH_VSN			0x0003
++#define HM5065_REG_EXCLOCKLUT			0x0009 /* standby */
++
++#define HM5065_REG_INT_EVENT_FLAG		0x000a
++#define HM5065_REG_INT_EVENT_FLAG_OP_MODE	BIT(0)
++#define HM5065_REG_INT_EVENT_FLAG_CAM_MODE	BIT(1)
++#define HM5065_REG_INT_EVENT_FLAG_JPEG_STATUS	BIT(2)
++#define HM5065_REG_INT_EVENT_FLAG_NUM_FRAMES	BIT(3)
++#define HM5065_REG_INT_EVENT_FLAG_AF_LOCKED	BIT(4)
++
++/* mode manager */
++#define HM5065_REG_USER_COMMAND			0x0010
++#define HM5065_REG_USER_COMMAND_STOP		0x00
++#define HM5065_REG_USER_COMMAND_RUN		0x01
++#define HM5065_REG_USER_COMMAND_POWEROFF	0x02
++
++#define HM5065_REG_STATE			0x0011
++#define HM5065_REG_STATE_RAW			0x10
++#define HM5065_REG_STATE_IDLE			0x20
++#define HM5065_REG_STATE_RUNNING		0x30
++
++#define HM5065_REG_ACTIVE_PIPE_SETUP_BANK	0x0012
++#define HM5065_REG_ACTIVE_PIPE_SETUP_BANK_0	0x00
++#define HM5065_REG_ACTIVE_PIPE_SETUP_BANK_1	0x01
++
++#define HM5065_REG_NUMBER_OF_FRAMES_STREAMED	0x0014 /* ro */
++#define HM5065_REG_REQUIRED_STREAM_LENGTH	0x0015
++
++#define HM5065_REG_CSI_ENABLE			0x0016 /* standby */
++#define HM5065_REG_CSI_ENABLE_DISABLE		0x00
++#define HM5065_REG_CSI_ENABLE_CSI2_1LANE	0x01
++#define HM5065_REG_CSI_ENABLE_CSI2_2LANE	0x02
++
++/* pipe setup bank 0 */
++#define HM5065_REG_P0_SENSOR_MODE		0x0040
++#define HM5065_REG_SENSOR_MODE_FULLSIZE		0x00
++#define HM5065_REG_SENSOR_MODE_BINNING_2X2	0x01
++#define HM5065_REG_SENSOR_MODE_BINNING_4X4	0x02
++#define HM5065_REG_SENSOR_MODE_SUBSAMPLING_2X2	0x03
++#define HM5065_REG_SENSOR_MODE_SUBSAMPLING_4X4	0x04
++
++#define HM5065_REG_P0_IMAGE_SIZE		0x0041
++#define HM5065_REG_IMAGE_SIZE_5MP		0x00
++#define HM5065_REG_IMAGE_SIZE_UXGA		0x01
++#define HM5065_REG_IMAGE_SIZE_SXGA		0x02
++#define HM5065_REG_IMAGE_SIZE_SVGA		0x03
++#define HM5065_REG_IMAGE_SIZE_VGA		0x04
++#define HM5065_REG_IMAGE_SIZE_CIF		0x05
++#define HM5065_REG_IMAGE_SIZE_QVGA		0x06
++#define HM5065_REG_IMAGE_SIZE_QCIF		0x07
++#define HM5065_REG_IMAGE_SIZE_QQVGA		0x08
++#define HM5065_REG_IMAGE_SIZE_QQCIF		0x09
++#define HM5065_REG_IMAGE_SIZE_MANUAL		0x0a
++
++#define HM5065_REG_P0_MANUAL_HSIZE		0x0042 /* u16 */
++#define HM5065_REG_P0_MANUAL_VSIZE		0x0044 /* u16 */
++
++#define HM5065_REG_P0_DATA_FORMAT		0x0046
++#define HM5065_REG_DATA_FORMAT_YCBCR_JFIF       0x00
++#define HM5065_REG_DATA_FORMAT_YCBCR_REC601     0x01
++#define HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM     0x02
++#define HM5065_REG_DATA_FORMAT_RGB_565          0x03
++#define HM5065_REG_DATA_FORMAT_RGB_565_CUSTOM   0x04
++#define HM5065_REG_DATA_FORMAT_RGB_444          0x05
++#define HM5065_REG_DATA_FORMAT_RGB_555          0x06
++#define HM5065_REG_DATA_FORMAT_RAW10ITU10       0x07
++#define HM5065_REG_DATA_FORMAT_RAW10ITU8        0x08
++#define HM5065_REG_DATA_FORMAT_JPEG             0x09
++
++#define HM5065_REG_P0_GAMMA_GAIN		0x0049 /* 0-31 */
++#define HM5065_REG_P0_GAMMA_INTERPOLATION	0x004a /* 0-16 */
++#define HM5065_REG_P0_PEAKING_GAIN		0x004c /* 0-63 */
++
++#define HM5065_REG_P0_JPEG_SQUEEZE_MODE		0x004d
++#define HM5065_REG_JPEG_SQUEEZE_MODE_USER	0x00
++#define HM5065_REG_JPEG_SQUEEZE_MODE_AUTO	0x01
++
++#define HM5065_REG_P0_JPEG_TARGET_FILE_SIZE	0x004e /* u16, kB */
++#define HM5065_REG_P0_JPEG_IMAGE_QUALITY	0x0050
++#define HM5065_REG_JPEG_IMAGE_QUALITY_HIGH	0x00
++#define HM5065_REG_JPEG_IMAGE_QUALITY_MEDIUM	0x01
++#define HM5065_REG_JPEG_IMAGE_QUALITY_LOW	0x02
++
++/* pipe setup bank 1 (only register indexes) */
++#define HM5065_REG_P1_SENSOR_MODE		0x0060
++#define HM5065_REG_P1_IMAGE_SIZE		0x0061
++#define HM5065_REG_P1_MANUAL_HSIZE		0x0062 /* u16 */
++#define HM5065_REG_P1_MANUAL_VSIZE		0x0064 /* u16 */
++#define HM5065_REG_P1_DATA_FORMAT		0x0066
++#define HM5065_REG_P1_GAMMA_GAIN		0x0069 /* 0-31 */
++#define HM5065_REG_P1_GAMMA_INTERPOLATION	0x006a /* 0-16 */
++#define HM5065_REG_P1_PEAKING_GAIN		0x006c /* 0-63 */
++#define HM5065_REG_P1_JPEG_SQUEEZE_MODE		0x006d
++#define HM5065_REG_P1_JPEG_TARGET_FILE_SIZE	0x006e /* u16, kB */
++#define HM5065_REG_P1_JPEG_IMAGE_QUALITY	0x0070
++
++/* pipe setup - common registers */
++#define HM5065_REG_CONTRAST			0x0080 /* 0-200 */
++#define HM5065_REG_COLOR_SATURATION		0x0081 /* 0-200 */
++#define HM5065_REG_BRIGHTNESS			0x0082 /* 0-200 */
++#define HM5065_REG_HORIZONTAL_MIRROR		0x0083 /* 0,1 */
++#define HM5065_REG_VERTICAL_FLIP		0x0084 /* 0,1 */
++
++#define HM5065_REG_YCRCB_ORDER			0x0085
++#define HM5065_REG_YCRCB_ORDER_CB_Y_CR_Y	0x00
++#define HM5065_REG_YCRCB_ORDER_CR_Y_CB_Y	0x01
++#define HM5065_REG_YCRCB_ORDER_Y_CB_Y_CR	0x02
++#define HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB	0x03
++
++/* clock chain parameter inputs (floating point) */
++#define HM5065_REG_EXTERNAL_CLOCK_FREQ_MHZ	0x00b0 /* fp16, 6-27, standby */
++#define HM5065_REG_TARGET_PLL_OUTPUT	0x00b2 /* fp16, 450-1000, standby */
++
++/* static frame rate control */
++#define HM5065_REG_DESIRED_FRAME_RATE_NUM	0x00c8 /* u16 */
++#define HM5065_REG_DESIRED_FRAME_RATE_DEN	0x00ca
++
++/* static frame rate status */
++#define HM5065_REG_REQUESTED_FRAME_RATE_HZ	0x00d8 /* fp16 */
++#define HM5065_REG_MAX_FRAME_RATE_HZ		0x00da /* fp16 */
++#define HM5065_REG_MIN_FRAME_RATE_HZ		0x00dc /* fp16 */
++
++/* exposure controls */
++#define HM5065_REG_EXPOSURE_MODE			0x0128
++#define HM5065_REG_EXPOSURE_MODE_AUTO			0x00
++#define HM5065_REG_EXPOSURE_MODE_COMPILED_MANUAL	0x01
++#define HM5065_REG_EXPOSURE_MODE_DIRECT_MANUAL		0x02
++
++#define HM5065_REG_EXPOSURE_METERING		0x0129
++#define HM5065_REG_EXPOSURE_METERING_FLAT	0x00
++#define HM5065_REG_EXPOSURE_METERING_BACKLIT	0x01
++#define HM5065_REG_EXPOSURE_METERING_CENTERED	0x02
++
++#define HM5065_REG_MANUAL_EXPOSURE_TIME_NUM	0x012a
++#define HM5065_REG_MANUAL_EXPOSURE_TIME_DEN	0x012b
++#define HM5065_REG_MANUAL_EXPOSURE_TIME_US	0x012c /* fp16 */
++#define HM5065_REG_COLD_START_DESIRED_TIME_US	0x012e /* fp16, standby */
++#define HM5065_REG_EXPOSURE_COMPENSATION	0x0130 /* s8, -7 - +7 */
++
++#define HM5065_REG_DIRECT_MODE_COARSE_INTEGRATION_LINES	0x0132 /* u16 */
++#define HM5065_REG_DIRECT_MODE_FINE_INTEGRATION_PIXELS	0x0134 /* u16 */
++#define HM5065_REG_DIRECT_MODE_CODED_ANALOG_GAIN	0x0136 /* u16 */
++#define HM5065_REG_DIRECT_MODE_DIGITAL_GAIN		0x0138 /* fp16 */
++#define HM5065_REG_FREEZE_AUTO_EXPOSURE			0x0142 /* 0,1 */
++#define HM5065_REG_USER_MAXIMUM_INTEGRATION_TIME_US	0x0143 /* fp16 */
++#define HM5065_REG_ANTI_FLICKER_MODE			0x0148 /* 0,1 */
++
++/* exposure algorithm controls */
++#define HM5065_REG_DIGITAL_GAIN_FLOOR			0x015c /* fp16 */
++#define HM5065_REG_DIGITAL_GAIN_CEILING			0x015e /* fp16 */
++#define HM5065_REG_ANALOG_GAIN_FLOOR			0x02c0 /* u16 */
++#define HM5065_REG_ANALOG_GAIN_CEILING			0x02c2 /* u16 */
++
++/* exposure status */
++#define HM5065_REG_COARSE_INTEGRATION			0x017c /* u16 */
++#define HM5065_REG_FINE_INTEGRATION_PENDING_PIXELS	0x017e /* u16 */
++#define HM5065_REG_ANALOG_GAIN_PENDING			0x0180 /* fp16 */
++#define HM5065_REG_DIGITAL_GAIN_PENDING			0x0182 /* fp16 */
++#define HM5065_REG_DESIRED_EXPOSURE_TIME_US		0x0184 /* fp16 */
++#define HM5065_REG_COMPILED_EXPOSURE_TIME_US		0x0186 /* fp16 */
++#define HM5065_REG_USER_MAXIMUM_INTEGRATION_LINES	0x0189 /* u16 */
++#define HM5065_REG_TOTAL_INTEGRATION_TIME_PENDING_US	0x018b /* fp16 */
++#define HM5065_REG_CODED_ANALOG_GAIN_PENDING		0x018d /* u16 */
++
++/* flicker detect */
++#define HM5065_REG_FD_ENABLE_DETECT			0x0190 /* 0,1 */
++#define HM5065_REG_FD_DETECTION_START			0x0191 /* 0,1 */
++#define HM5065_REG_FD_MAX_NUMBER_ATTEMP	0x0192 /* 0-255, 0 = continuous */
++#define HM5065_REG_FD_FLICKER_IDENTIFICATION_THRESHOLD	0x0193 /* u16 */
++#define HM5065_REG_FD_WIN_TIMES				0x0195
++#define HM5065_REG_FD_FRAME_RATE_SHIFT_NUMBER		0x0196
++#define HM5065_REG_FD_MANUAL_FREF_ENABLE		0x0197 /* 0,1 */
++#define HM5065_REG_FD_MANU_FREF_100			0x0198 /* u16 */
++#define HM5065_REG_FD_MANU_FREF_120			0x019a /* u16 */
++#define HM5065_REG_FD_FLICKER_FREQUENCY			0x019c /* fp16 */
++
++/* white balance control */
++#define HM5065_REG_WB_MODE			0x01a0
++#define HM5065_REG_WB_MODE_OFF			0x00
++#define HM5065_REG_WB_MODE_AUTOMATIC		0x01
++#define HM5065_REG_WB_MODE_AUTO_INSTANT		0x02
++#define HM5065_REG_WB_MODE_MANUAL_RGB		0x03
++#define HM5065_REG_WB_MODE_CLOUDY_PRESET	0x04
++#define HM5065_REG_WB_MODE_SUNNY_PRESET		0x05
++#define HM5065_REG_WB_MODE_LED_PRESET		0x06
++#define HM5065_REG_WB_MODE_FLUORESCENT_PRESET	0x07
++#define HM5065_REG_WB_MODE_TUNGSTEN_PRESET	0x08
++#define HM5065_REG_WB_MODE_HORIZON_PRESET	0x09
++
++#define HM5065_REG_WB_MANUAL_RED_GAIN		0x01a1
++#define HM5065_REG_WB_MANUAL_GREEN_GAIN		0x01a2
++#define HM5065_REG_WB_MANUAL_BLUE_GAIN		0x01a3
++
++#define HM5065_REG_WB_MISC_SETTINGS		0x01a4
++#define HM5065_REG_WB_MISC_SETTINGS_FREEZE_ALGO	BIT(2)
++
++#define HM5065_REG_WB_HUE_R_BIAS		0x01a5 /* fp16 */
++#define HM5065_REG_WB_HUE_B_BIAS		0x01a7 /* fp16 */
++
++#define HM5065_REG_WB_STATUS			0x01c0
++#define HM5065_REG_WB_STATUS_STABLE		BIT(0)
++
++#define HM5065_REG_WB_NORM_RED_GAIN		0x01c8 /* fp16 */
++#define HM5065_REG_WB_PART_RED_GAIN		0x01e0 /* fp16 */
++#define HM5065_REG_WB_PART_GREEN_GAIN		0x01e2 /* fp16 */
++#define HM5065_REG_WB_PART_BLUE_GAIN		0x01e4 /* fp16 */
++
++/* image stability status */
++#define HM5065_REG_WHITE_BALANCE_STABLE		0x0291 /* 0,1 */
++#define HM5065_REG_EXPOSURE_STABLE		0x0292 /* 0,1 */
++#define HM5065_REG_STABLE			0x0294 /* 0,1 */
++
++/* special effects */
++#define HM5065_REG_EFFECTS_NEGATIVE		0x0380 /* 0,1 */
++#define HM5065_REG_EFFECTS_SOLARISING		0x0381 /* 0,1 */
++#define HM5065_REG_EFFECTS_SKECTH		0x0382 /* 0,1 */
++
++#define HM5065_REG_EFFECTS_COLOR		0x0384
++#define HM5065_REG_EFFECTS_COLOR_NORMAL         0x00
++#define HM5065_REG_EFFECTS_COLOR_RED_ONLY       0x01
++#define HM5065_REG_EFFECTS_COLOR_YELLOW_ONLY    0x02
++#define HM5065_REG_EFFECTS_COLOR_GREEN_ONLY     0x03
++#define HM5065_REG_EFFECTS_COLOR_BLUE_ONLY      0x04
++#define HM5065_REG_EFFECTS_COLOR_BLACK_WHITE    0x05
++#define HM5065_REG_EFFECTS_COLOR_SEPIA          0x06
++#define HM5065_REG_EFFECTS_COLOR_ANTIQUE        0x07
++#define HM5065_REG_EFFECTS_COLOR_AQUA           0x08
++#define HM5065_REG_EFFECTS_COLOR_MANUAL_MATRIX  0x09
++
++/* anti-vignete, otp flash (skipped), page 79-89 */
++
++/* flash control */
++#define HM5065_REG_FLASH_MODE		0x02d0 /* 0,1 */
++#define HM5065_REG_FLASH_RECOMMENDED	0x02d1 /* 0,1 */
++
++/* test pattern */
++#define HM5065_REG_ENABLE_TEST_PATTERN	0x05d8 /* 0,1 */
++
++#define HM5065_REG_TEST_PATTERN				0x05d9
++#define HM5065_REG_TEST_PATTERN_NONE			0x00
++#define HM5065_REG_TEST_PATTERN_HORIZONTAL_GREY_SCALE	0x01
++#define HM5065_REG_TEST_PATTERN_VERTICAL_GREY_SCALE	0x02
++#define HM5065_REG_TEST_PATTERN_DIAGONAL_GREY_SCALE	0x03
++#define HM5065_REG_TEST_PATTERN_PN28			0x04
++#define HM5065_REG_TEST_PATTERN_PN9			0x05
++#define HM5065_REG_TEST_PATTERN_SOLID_COLOR		0x06
++#define HM5065_REG_TEST_PATTERN_COLOR_BARS		0x07
++#define HM5065_REG_TEST_PATTERN_GRADUATED_COLOR_BARS	0x08
++
++#define HM5065_REG_TESTDATA_RED		0x4304 /* u16, 0-1023 */
++#define HM5065_REG_TESTDATA_GREEN_R	0x4308 /* u16, 0-1023 */
++#define HM5065_REG_TESTDATA_BLUE	0x430c /* u16, 0-1023 */
++#define HM5065_REG_TESTDATA_GREEN_B	0x4310 /* u16, 0-1023 */
++
++/* contrast stretch */
++#define HM5065_REG_CS_ENABLE			0x05e8 /* 0,1 */
++#define HM5065_REG_CS_GAIN_CEILING		0x05e9 /* fp16 */
++#define HM5065_REG_CS_BLACK_OFFSET_CEILING	0x05eb
++#define HM5065_REG_CS_WHITE_PIX_TARGET		0x05ec /* fp16 */
++#define HM5065_REG_CS_BLACK_PIX_TARGET		0x05ee /* fp16 */
++#define HM5065_REG_CS_ENABLED			0x05f8 /* 0,1 */
++#define HM5065_REG_CS_TOTAL_PIXEL		0x05f9 /* fp16 */
++#define HM5065_REG_CS_W_TARGET			0x05fb /* u32 */
++#define HM5065_REG_CS_B_TARGET			0x05ff /* u32 */
++#define HM5065_REG_CS_GAIN			0x0603 /* fp16 */
++#define HM5065_REG_CS_BLACK_OFFSET		0x0605
++#define HM5065_REG_CS_WHITE_LIMIT		0x0606
++
++/* preset controls */
++#define HM5065_REG_PRESET_LOADER_ENABLE		0x0638 /* 0,1, standby */
++
++#define HM5065_REG_INDIVIDUAL_PRESET		0x0639 /* standby */
++#define HM5065_REG_INDIVIDUAL_PRESET_ANTIVIGNETTE	BIT(0)
++#define HM5065_REG_INDIVIDUAL_PRESET_WHITE_BALANCE	BIT(1)
++#define HM5065_REG_INDIVIDUAL_PRESET_VCM		BIT(4)
++
++/* jpeg control parameters*/
++#define HM5065_REG_JPEG_STATUS			0x0649
++#define HM5065_REG_JPEG_RESTART			0x064a
++#define HM5065_REG_JPEG_HI_SQUEEZE_VALUE	0x064b /* 5-255 (5 = max q.) */
++#define HM5065_REG_JPEG_MED_SQUEEZE_VALUE	0x064c /* 5-255 */
++#define HM5065_REG_JPEG_LOW_SQUEEZE_VALUE	0x064d /* 5-255 */
++#define HM5065_REG_JPEG_LINE_LENGTH		0x064e /* u16, standby */
++#define HM5065_REG_JPEG_CLOCK_RATIO		0x0650 /* 1-8, standby */
++#define HM5065_REG_JPEG_THRES			0x0651 /* u16, standby */
++#define HM5065_REG_JPEG_BYTE_SENT		0x0653 /* u32 */
++
++/* autofocus */
++
++#define HM5065_REG_AF_WINDOWS_SYSTEM		0x065a
++#define HM5065_REG_AF_WINDOWS_SYSTEM_7_ZONES	0x00
++#define HM5065_REG_AF_WINDOWS_SYSTEM_1_ZONE	0x01
++
++#define HM5065_REG_AF_H_RATIO_NUM		0x065b
++#define HM5065_REG_AF_H_RATIO_DEN		0x065c
++#define HM5065_REG_AF_V_RATIO_NUM		0x065d
++#define HM5065_REG_AF_V_RATIO_DEN		0x065e
++
++#define HM5065_REG_AF_RANGE			0x0709
++#define HM5065_REG_AF_RANGE_FULL		0x00
++#define HM5065_REG_AF_RANGE_LANDSCAPE		0x01
++#define HM5065_REG_AF_RANGE_MACRO		0x02
++
++#define HM5065_REG_AF_MODE			0x070a
++#define HM5065_REG_AF_MODE_MANUAL		0x00
++#define HM5065_REG_AF_MODE_CONTINUOUS		0x01
++#define HM5065_REG_AF_MODE_SINGLE		0x03
++
++#define HM5065_REG_AF_MODE_STATUS		0x0720
++
++#define HM5065_REG_AF_COMMAND			0x070b
++#define HM5065_REG_AF_COMMAND_NULL		0x00
++#define HM5065_REG_AF_COMMAND_RELEASED_BUTTON	0x01
++#define HM5065_REG_AF_COMMAND_HALF_BUTTON	0x02
++#define HM5065_REG_AF_COMMAND_TAKE_SNAPSHOT	0x03
++#define HM5065_REG_AF_COMMAND_REFOCUS		0x04
++
++#define HM5065_REG_AF_LENS_COMMAND		0x070c
++#define HM5065_REG_AF_LENS_COMMAND_NULL				0x00
++#define HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_INFINITY	0x01
++#define HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_MACRO		0x02
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_INFINITY		0x03
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_MACRO			0x04
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_RECOVERY		0x05
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_TARGET_POSITION		0x07
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_HYPERFOCAL		0x0C
++
++#define HM5065_REG_AF_MANUAL_STEP_SIZE		0x070d
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE	0x0714
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE_AF	BIT(0)
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE_AE	BIT(1)
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE_AWB	BIT(2)
++#define HM5065_REG_AF_FACE_LOCATION_X_START	0x0715 /* u16 */
++#define HM5065_REG_AF_FACE_LOCATION_X_SIZE	0x0717 /* u16 */
++#define HM5065_REG_AF_FACE_LOCATION_Y_START	0x0719 /* u16 */
++#define HM5065_REG_AF_FACE_LOCATION_Y_SIZE	0x071b /* u16 */
++
++#define HM5065_REG_AF_IN_FOCUS			0x07ae /* ro 0,1 */
++#define HM5065_REG_AF_IS_STABLE			0x0725 /* ro 0,1 */
++
++/* reverse engineered registers */
++#define HM5065_REG_BUS_DATA_FORMAT		0x7000
++#define HM5065_REG_COLORSPACE			0x5200
++#define HM5065_REG_BUS_CONFIG			0x7101
++#define HM5065_REG_BUS_CONFIG_BT656		0x24
++#define HM5065_REG_BUS_CONFIG_PARALLEL_HH_VL	0x44
++
++/* }}} */
++
++struct reg_value {
++	u16 addr;
++	u8 value;
++} __packed;
++
++/*
++ * Sensor has various pre-defined PLL configurations for a set of
++ * external clock frequencies.
++ */
++struct hm5065_clk_lut {
++	unsigned long clk_freq;
++	u8 lut_id;
++};
++
++static const struct hm5065_clk_lut hm5065_clk_luts[] = {
++	{ .clk_freq = 12000000, .lut_id = 0x10 },
++	{ .clk_freq = 13000000, .lut_id = 0x11 },
++	{ .clk_freq = 13500000, .lut_id = 0x12 },
++	{ .clk_freq = 14400000, .lut_id = 0x13 },
++	{ .clk_freq = 18000000, .lut_id = 0x14 },
++	{ .clk_freq = 19200000, .lut_id = 0x15 },
++	{ .clk_freq = 24000000, .lut_id = 0x16 },
++	{ .clk_freq = 26000000, .lut_id = 0x17 },
++	{ .clk_freq = 27000000, .lut_id = 0x18 },
++};
++
++static const struct hm5065_clk_lut *hm5065_find_clk_lut(unsigned long freq)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(hm5065_clk_luts); i++)
++		if (hm5065_clk_luts[i].clk_freq == freq)
++			return &hm5065_clk_luts[i];
++
++	return NULL;
++}
++
++struct hm5065_pixfmt {
++	u32 code;
++	u32 colorspace;
++	u8 data_fmt;
++	u8 ycbcr_order;
++	u8 fmt_setup;
++};
++
++//XXX: identify colrorspace correctly, see datasheet page 40
++static const struct hm5065_pixfmt hm5065_formats[] = {
++	{
++		.code              = MEDIA_BUS_FMT_UYVY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_CB_Y_CR_Y,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_VYUY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_CR_Y_CB_Y,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CB_Y_CR,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_RGB565_2X8_LE,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_RGB_565,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB,
++		.fmt_setup         = 0x02
++	},
++	{
++		.code              = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_RGB_555,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB,
++		.fmt_setup         = 0x02
++	},
++};
++
++#define HM5065_NUM_FORMATS ARRAY_SIZE(hm5065_formats)
++
++static const struct hm5065_pixfmt *hm5065_find_format(u32 code)
++{
++	int i;
++
++	for (i = 0; i < HM5065_NUM_FORMATS; i++)
++		if (hm5065_formats[i].code == code)
++			return &hm5065_formats[i];
++
++	return NULL;
++}
++
++/* regulator supplies */
++static const char * const hm5065_supply_name[] = {
++	"IOVDD", /* Digital I/O (2.8V) suppply */
++	"AFVDD",  /* Autofocus (2.8V) supply */
++	"DVDD",  /* Digital Core (1.8V) supply */
++	"AVDD",  /* Analog (2.8V) supply */
++};
++
++#define HM5065_NUM_SUPPLIES ARRAY_SIZE(hm5065_supply_name)
++
++struct hm5065_ctrls {
++	struct v4l2_ctrl_handler handler;
++	struct {
++		struct v4l2_ctrl *auto_exposure;
++		struct v4l2_ctrl *exposure;
++		struct v4l2_ctrl *d_gain;
++		struct v4l2_ctrl *a_gain;
++	};
++	struct v4l2_ctrl *metering;
++	struct v4l2_ctrl *exposure_bias;
++	struct {
++		struct v4l2_ctrl *wb;
++		struct v4l2_ctrl *blue_balance;
++		struct v4l2_ctrl *red_balance;
++	};
++	struct {
++		struct v4l2_ctrl *focus_auto;
++		struct v4l2_ctrl *af_start;
++		struct v4l2_ctrl *af_stop;
++		struct v4l2_ctrl *af_status;
++		struct v4l2_ctrl *af_distance;
++		struct v4l2_ctrl *focus_relative;
++	};
++	struct v4l2_ctrl *aaa_lock;
++	struct v4l2_ctrl *hflip;
++	struct v4l2_ctrl *vflip;
++	struct v4l2_ctrl *pl_freq;
++	struct v4l2_ctrl *colorfx;
++	struct v4l2_ctrl *brightness;
++	struct v4l2_ctrl *saturation;
++	struct v4l2_ctrl *contrast;
++	struct v4l2_ctrl *gamma;
++	struct v4l2_ctrl *test_pattern;
++	struct v4l2_ctrl *test_data[4];
++};
++
++struct hm5065_dev {
++	struct i2c_client *i2c_client;
++	struct v4l2_subdev sd;
++	struct media_pad pad;
++	struct v4l2_fwnode_endpoint ep; /* the parsed DT endpoint info */
++	struct clk *xclk; /* external clock for HM5065 */
++
++	struct regulator_bulk_data supplies[HM5065_NUM_SUPPLIES];
++	struct gpio_desc *reset_gpio; // nrst pin
++	struct gpio_desc *enable_gpio; // ce pin
++
++	/* lock to protect all members below */
++	struct mutex lock;
++
++	struct v4l2_mbus_framefmt fmt;
++	struct v4l2_fract frame_interval;
++	struct hm5065_ctrls ctrls;
++
++	bool pending_mode_change;
++	bool powered;
++	bool streaming;
++};
++
++static inline struct hm5065_dev *to_hm5065_dev(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct hm5065_dev, sd);
++}
++
++static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct hm5065_dev,
++			     ctrls.handler)->sd;
++}
++
++/* {{{ Register access helpers */
++
++static int hm5065_write_regs(struct hm5065_dev *sensor, u16 start_index,
++			     u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg;
++	u8 buf[130];
++	int ret;
++
++	if (data_size > sizeof(buf) - 2) {
++		v4l2_err(&sensor->sd, "%s: oversized transfer (size=%d)\n",
++			 __func__, data_size);
++		return -EINVAL;
++	}
++
++	buf[0] = start_index >> 8;
++	buf[1] = start_index & 0xff;
++	memcpy(buf + 2, data, data_size);
++
++	msg.addr = client->addr;
++	msg.flags = client->flags;
++	msg.buf = buf;
++	msg.len = data_size + 2;
++
++	dev_dbg(&sensor->i2c_client->dev, "wr: %04x <= %*ph\n",
++		(u32)start_index, data_size, data);
++
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: start_index=%x, data=%*ph\n",
++			 __func__, ret, (u32)start_index, data_size, data);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int hm5065_read_regs(struct hm5065_dev *sensor, u16 start_index,
++			    u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg[2];
++	u8 buf[2];
++	int ret;
++
++	buf[0] = start_index >> 8;
++	buf[1] = start_index & 0xff;
++
++	msg[0].addr = client->addr;
++	msg[0].flags = client->flags;
++	msg[0].buf = buf;
++	msg[0].len = sizeof(buf);
++
++	msg[1].addr = client->addr;
++	msg[1].flags = client->flags | I2C_M_RD;
++	msg[1].buf = data;
++	msg[1].len = data_size;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: start_index=%x, data_size=%d\n",
++			 __func__, ret, (u32)start_index, data_size);
++		return ret;
++	}
++
++	dev_dbg(&sensor->i2c_client->dev, "rd: %04x => %*ph\n",
++		(u32)start_index, data_size, data);
++
++	return 0;
++}
++
++static int hm5065_read(struct hm5065_dev *sensor, u16 reg, u8 *val)
++{
++	return hm5065_read_regs(sensor, reg, val, 1);
++}
++
++static int hm5065_write(struct hm5065_dev *sensor, u16 reg, u8 val)
++{
++	return hm5065_write_regs(sensor, reg, &val, 1);
++}
++
++static int hm5065_read16(struct hm5065_dev *sensor, u16 reg, u16 *val)
++{
++	int ret;
++
++	ret = hm5065_read_regs(sensor, reg, (u8 *)val, sizeof(*val));
++	if (ret)
++		return ret;
++
++	*val = be16_to_cpu(*val);
++	return 0;
++}
++
++static int hm5065_write16(struct hm5065_dev *sensor, u16 reg, u16 val)
++{
++	u16 tmp = cpu_to_be16(val);
++
++	return hm5065_write_regs(sensor, reg, (u8 *)&tmp, sizeof(tmp));
++}
++
++/*
++ * The firmware format:
++ * <record 0>, ..., <record N - 1>
++ * "record" is a 2-byte register address (big endian) followed by 1-byte data
++ */
++static int hm5065_load_firmware(struct hm5065_dev *sensor, const char *name)
++{
++	int ret = 0, i = 0, list_size;
++	const struct firmware *fw;
++	struct reg_value *list;
++	u16 start, len;
++	u8 buf[128];
++
++	ret = request_firmware(&fw, name, sensor->sd.v4l2_dev->dev);
++	if (ret) {
++		v4l2_warn(&sensor->sd,
++			  "Failed to read firmware %s, continuing anyway...\n",
++			  name);
++		return 1;
++	}
++
++	if (fw->size == 0) {
++		ret = 1;
++		goto err_release;
++	}
++
++	if (fw->size % 3 != 0) {
++		v4l2_err(&sensor->sd, "Firmware image %s has invalid size\n",
++			 name);
++		ret = -EINVAL;
++		goto err_release;
++	}
++
++	list_size = fw->size / 3;
++	list = (struct reg_value *)fw->data;
++
++	/* we speed up I2C communication via auto-increment functionality */
++	while (i < list_size) {
++		start = be16_to_cpu(list[i].addr);
++		len = 0;
++
++		while (i < list_size &&
++		       be16_to_cpu(list[i].addr) == (start + len) &&
++		       len < sizeof(buf))
++			buf[len++] = list[i++].value;
++
++		ret = hm5065_write_regs(sensor, start, buf, len);
++		if (ret)
++			goto err_release;
++	}
++
++err_release:
++	release_firmware(fw);
++	return ret;
++}
++
++/*
++ * Sensor uses ST Float900 format to represent floating point numbers.
++ * Binary floating point number: * (s ? -1 : 0) * 1.mmmmmmmmm * 2^eeeeee
++ *
++ * Following functions convert long value to and from the floating point format.
++ *
++ * Example:
++ * mili variant: val = 123456 => fp_val = 123.456
++ * micro variant: val = -12345678 => fp_val = -12.345678
++ */
++static s64 hm5065_mili_from_fp16(u16 fp_val)
++{
++	s64 val;
++	s64 mantisa = fp_val & 0x1ff;
++	int exp = (int)((fp_val >> 9) & 0x3f) - 31;
++
++	val = (1000 * (mantisa | 0x200));
++	if (exp > 0)
++		val <<= exp;
++	else if (exp < 0)
++		val >>= -exp;
++	val >>= 9;
++
++	if (fp_val & 0x8000)
++		val = -val;
++
++	return val;
++}
++
++static u16 hm5065_mili_to_fp16(s32 val)
++{
++	int fls;
++	u16 e, m, s = 0;
++	u64 v, rem;
++
++	if (val == 0)
++		return 0;
++
++	if (val < 0) {
++		val = -val;
++		s = 0x8000;
++	}
++
++	v = (u64)val * 1024;
++	rem = do_div(v, 1000);
++	if (rem >= 500)
++		v++;
++
++	fls = fls64(v) - 1;
++	e = 31 + fls - 10;
++	m = fls > 9 ? v >> (fls - 9) : v << (9 - fls);
++
++	return s | (m & 0x1ff) | (e << 9);
++}
++
++/* }}} */
++/* {{{ Controls */
++
++static int hm5065_get_af_status(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	u8 is_stable, mode;
++	int ret;
++
++	ret = hm5065_read(sensor, HM5065_REG_AF_MODE_STATUS, &mode);
++	if (ret)
++		return ret;
++
++	if (mode == HM5065_REG_AF_MODE_MANUAL) {
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_IDLE;
++		return 0;
++	}
++
++	ret = hm5065_read(sensor, HM5065_REG_AF_IS_STABLE, &is_stable);
++	if (ret)
++		return ret;
++
++	if (is_stable)
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_REACHED;
++	else if (!is_stable && mode == HM5065_REG_AF_MODE_CONTINUOUS)
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_BUSY;
++	else
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_IDLE;
++
++	return 0;
++}
++
++static int hm5065_get_exposure(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	u16 again, dgain, exp;
++	int ret;
++
++	ret = hm5065_read16(sensor, HM5065_REG_CODED_ANALOG_GAIN_PENDING,
++			    &again);
++	if (ret)
++		return ret;
++
++	ret = hm5065_read16(sensor, HM5065_REG_DIGITAL_GAIN_PENDING, &dgain);
++	if (ret)
++		return ret;
++
++	ret = hm5065_read16(sensor, HM5065_REG_COARSE_INTEGRATION, &exp);
++	if (ret)
++		return ret;
++
++	ctrls->exposure->val = exp;
++	ctrls->d_gain->val = clamp(hm5065_mili_from_fp16(dgain), 1000ll,
++				   4000ll);
++	ctrls->a_gain->val = again;
++
++	return 0;
++}
++
++static int hm5065_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	if (!sensor->powered)
++		return -EIO;
++
++	switch (ctrl->id) {
++	case V4L2_CID_FOCUS_AUTO:
++		ret = hm5065_get_af_status(sensor);
++		if (ret)
++			return ret;
++		break;
++	case V4L2_CID_EXPOSURE_AUTO:
++		ret = hm5065_get_exposure(sensor);
++		if (ret)
++			return ret;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const u8 hm5065_wb_opts[][2] = {
++	{ V4L2_WHITE_BALANCE_MANUAL, HM5065_REG_WB_MODE_OFF },
++	{ V4L2_WHITE_BALANCE_INCANDESCENT, HM5065_REG_WB_MODE_TUNGSTEN_PRESET },
++	{ V4L2_WHITE_BALANCE_FLUORESCENT,
++		HM5065_REG_WB_MODE_FLUORESCENT_PRESET },
++	{ V4L2_WHITE_BALANCE_HORIZON, HM5065_REG_WB_MODE_HORIZON_PRESET },
++	{ V4L2_WHITE_BALANCE_CLOUDY, HM5065_REG_WB_MODE_CLOUDY_PRESET },
++	{ V4L2_WHITE_BALANCE_DAYLIGHT, HM5065_REG_WB_MODE_SUNNY_PRESET },
++	{ V4L2_WHITE_BALANCE_AUTO, HM5065_REG_WB_MODE_AUTOMATIC },
++};
++
++static int hm5065_set_power_line_frequency(struct hm5065_dev *sensor, s32 val)
++{
++	u16 freq;
++	int ret;
++
++	switch (val) {
++	case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
++		ret = hm5065_write(sensor, HM5065_REG_ANTI_FLICKER_MODE, 0);
++		if (ret)
++			return ret;
++
++		return hm5065_write(sensor, HM5065_REG_FD_ENABLE_DETECT, 0);
++	case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
++	case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
++		ret = hm5065_write(sensor, HM5065_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_FD_ENABLE_DETECT, 0);
++		if (ret)
++			return ret;
++
++		freq = (val == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) ?
++			0x4b20 : 0x4bc0;
++
++		return hm5065_write16(sensor, HM5065_REG_FD_FLICKER_FREQUENCY,
++				      freq);
++	case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
++		ret = hm5065_write(sensor, HM5065_REG_FD_ENABLE_DETECT, 1);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write16(sensor, HM5065_REG_FD_MAX_NUMBER_ATTEMP,
++				     100);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write16(sensor, HM5065_REG_FD_FLICKER_FREQUENCY,
++				     0);
++		if (ret)
++			return ret;
++
++		return hm5065_write(sensor, HM5065_REG_FD_DETECTION_START, 1);
++	default:
++		return -EINVAL;
++	}
++}
++
++static int hm5065_set_colorfx(struct hm5065_dev *sensor, s32 val)
++{
++	int ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++			   HM5065_REG_EFFECTS_COLOR_NORMAL);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_NEGATIVE, 0);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_SOLARISING, 0);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_SKECTH, 0);
++	if (ret)
++		return ret;
++
++	switch (val) {
++	case V4L2_COLORFX_NONE:
++		return 0;
++	case V4L2_COLORFX_NEGATIVE:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_NEGATIVE, 1);
++	case V4L2_COLORFX_SOLARIZATION:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_SOLARISING, 1);
++	case V4L2_COLORFX_SKETCH:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_SKECTH, 1);
++	case V4L2_COLORFX_ANTIQUE:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_ANTIQUE);
++	case V4L2_COLORFX_SEPIA:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_SEPIA);
++	case V4L2_COLORFX_AQUA:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_AQUA);
++	case V4L2_COLORFX_BW:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_BLACK_WHITE);
++	default:
++		return -EINVAL;
++	}
++}
++
++#define AE_BIAS_MENU_DEFAULT_VALUE_INDEX 7
++static const s64 ae_bias_menu_values[] = {
++	-2100, -1800, -1500, -1200, -900, -600, -300,
++	0, 300, 600, 900, 1200, 1500, 1800, 2100
++};
++
++static const s8 ae_bias_menu_reg_values[] = {
++	-7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7
++};
++
++static int hm5065_set_exposure(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	bool is_auto = (ctrls->auto_exposure->val != V4L2_EXPOSURE_MANUAL);
++	int ret = 0;
++
++	if (ctrls->auto_exposure->is_new) {
++		ret = hm5065_write(sensor, HM5065_REG_EXPOSURE_MODE,
++				   is_auto ?
++				   HM5065_REG_EXPOSURE_MODE_AUTO :
++				   HM5065_REG_EXPOSURE_MODE_DIRECT_MANUAL);
++		if (ret)
++			return ret;
++
++		if (ctrls->auto_exposure->cur.val != ctrls->auto_exposure->val &&
++		    !is_auto) {
++			/*
++			 * Hack: At this point, there are current volatile
++			 * values in val, but control framework will not
++			 * update the cur values for our autocluster, as it
++			 * should. I couldn't find the reason. This fixes
++			 * it for our driver. Remove this after the kernel
++			 * is fixed.
++			 */
++			ctrls->exposure->cur.val = ctrls->exposure->val;
++			ctrls->d_gain->cur.val = ctrls->d_gain->val;
++			ctrls->a_gain->cur.val = ctrls->a_gain->val;
++		}
++	}
++
++	if (!is_auto && ctrls->exposure->is_new) {
++		ret = hm5065_write16(sensor,
++			   HM5065_REG_DIRECT_MODE_COARSE_INTEGRATION_LINES,
++			   ctrls->exposure->val);
++		if (ret)
++			return ret;
++	}
++
++	if (!is_auto && ctrls->d_gain->is_new) {
++		ret = hm5065_write16(sensor,
++				     HM5065_REG_DIRECT_MODE_DIGITAL_GAIN,
++				     hm5065_mili_to_fp16(ctrls->d_gain->val));
++		if (ret)
++			return ret;
++	}
++
++	if (!is_auto && ctrls->a_gain->is_new)
++		ret = hm5065_write16(sensor,
++				     HM5065_REG_DIRECT_MODE_CODED_ANALOG_GAIN,
++				     ctrls->a_gain->val);
++
++	return ret;
++}
++
++static int hm5065_3a_lock(struct hm5065_dev *sensor, struct v4l2_ctrl *ctrl)
++{
++	bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
++	bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
++	int ret = 0;
++
++	if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE
++	    && sensor->ctrls.auto_exposure->val == V4L2_EXPOSURE_AUTO) {
++		ret = hm5065_write(sensor, HM5065_REG_FREEZE_AUTO_EXPOSURE,
++				   ae_lock);
++		if (ret)
++			return ret;
++	}
++
++	if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE)
++	    && sensor->ctrls.wb->val == V4L2_WHITE_BALANCE_AUTO) {
++		ret = hm5065_write(sensor, HM5065_REG_WB_MISC_SETTINGS,
++				   awb_lock ?
++				   HM5065_REG_WB_MISC_SETTINGS_FREEZE_ALGO : 0);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int hm5065_set_auto_focus(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	bool auto_focus = ctrls->focus_auto->val;
++	int ret = 0;
++	u8 range;
++
++	if (auto_focus && ctrls->af_distance->is_new) {
++		switch (ctrls->af_distance->val) {
++		case V4L2_AUTO_FOCUS_RANGE_MACRO:
++			range = HM5065_REG_AF_RANGE_MACRO;
++			break;
++		case V4L2_AUTO_FOCUS_RANGE_AUTO:
++			range = HM5065_REG_AF_RANGE_FULL;
++			break;
++		case V4L2_AUTO_FOCUS_RANGE_INFINITY:
++			range = HM5065_REG_AF_RANGE_LANDSCAPE;
++			break;
++		default:
++			return -EINVAL;
++		}
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_RANGE, range);
++		if (ret)
++			return ret;
++	}
++
++	if (ctrls->focus_auto->is_new) {
++		v4l2_ctrl_activate(ctrls->af_start, !auto_focus);
++		v4l2_ctrl_activate(ctrls->af_stop, !auto_focus);
++		v4l2_ctrl_activate(ctrls->focus_relative, !auto_focus);
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   auto_focus ?
++				   HM5065_REG_AF_MODE_CONTINUOUS :
++				   HM5065_REG_AF_MODE_SINGLE);
++		if (ret)
++			return ret;
++
++		if (!auto_focus) {
++			ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++					 HM5065_REG_AF_COMMAND_RELEASED_BUTTON);
++			if (ret)
++				return ret;
++		}
++	}
++
++	if (!auto_focus && ctrls->af_start->is_new) {
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   HM5065_REG_AF_MODE_SINGLE);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++				   HM5065_REG_AF_COMMAND_RELEASED_BUTTON);
++		if (ret)
++			return ret;
++
++		usleep_range(190000, 200000);
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++				   HM5065_REG_AF_COMMAND_HALF_BUTTON);
++		if (ret)
++			return ret;
++	}
++
++	if (!auto_focus && ctrls->af_stop->is_new) {
++		ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++				   HM5065_REG_AF_COMMAND_RELEASED_BUTTON);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   HM5065_REG_AF_MODE_MANUAL);
++		if (ret)
++			return ret;
++	}
++
++	if (!auto_focus && ctrls->focus_relative->is_new &&
++	    ctrls->focus_relative->val) {
++		u8 cmd = 0xff;
++		s32 step = ctrls->focus_relative->val;
++
++		ctrls->focus_relative->val = 0;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   HM5065_REG_AF_MODE_MANUAL);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MANUAL_STEP_SIZE,
++				   abs(step));
++		if (ret)
++			return ret;
++
++		if (step < 0)
++			cmd = HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_INFINITY;
++		else if (step > 0)
++			cmd = HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_MACRO;
++
++		if (cmd != 0xff)
++			ret = hm5065_write(sensor, HM5065_REG_AF_LENS_COMMAND,
++					   cmd);
++
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int hm5065_set_white_balance(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	bool manual_wb = ctrls->wb->val == V4L2_WHITE_BALANCE_MANUAL;
++	int ret = 0, i;
++	s32 val;
++
++	if (ctrls->wb->is_new) {
++		for (i = 0; i < ARRAY_SIZE(hm5065_wb_opts); i++) {
++			if (hm5065_wb_opts[i][0] != ctrls->wb->val)
++				continue;
++
++			ret = hm5065_write(sensor, HM5065_REG_WB_MODE,
++					    hm5065_wb_opts[i][1]);
++			if (ret)
++				return ret;
++			goto next;
++		}
++
++		return -EINVAL;
++	}
++
++next:
++	if (ctrls->wb->is_new || ctrls->blue_balance->is_new) {
++		val = manual_wb ? ctrls->blue_balance->val : 1000;
++		ret = hm5065_write16(sensor, HM5065_REG_WB_HUE_B_BIAS,
++				     hm5065_mili_to_fp16(val));
++		if (ret)
++			return ret;
++	}
++
++	if (ctrls->wb->is_new || ctrls->red_balance->is_new) {
++		val = manual_wb ? ctrls->red_balance->val : 1000;
++		ret = hm5065_write16(sensor, HM5065_REG_WB_HUE_R_BIAS,
++				     hm5065_mili_to_fp16(val));
++	}
++
++	return ret;
++}
++
++static int hm5065_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	s32 val = ctrl->val;
++	unsigned int i;
++	int ret;
++	u8 reg;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	/*
++	 * If the device is not powered up by the host driver do
++	 * not apply any controls to H/W at this time. Instead
++	 * the controls will be restored right after power-up.
++	 */
++	if (!sensor->powered)
++		return 0;
++
++	switch (ctrl->id) {
++	case V4L2_CID_EXPOSURE_AUTO:
++		return hm5065_set_exposure(sensor);
++
++	case V4L2_CID_EXPOSURE_METERING:
++		if (val == V4L2_EXPOSURE_METERING_AVERAGE)
++			reg = HM5065_REG_EXPOSURE_METERING_FLAT;
++		else if (val == V4L2_EXPOSURE_METERING_CENTER_WEIGHTED)
++			reg = HM5065_REG_EXPOSURE_METERING_CENTERED;
++		else
++			return -EINVAL;
++
++		return hm5065_write(sensor, HM5065_REG_EXPOSURE_METERING, reg);
++
++	case V4L2_CID_AUTO_EXPOSURE_BIAS:
++		if (val < 0 || val >= ARRAY_SIZE(ae_bias_menu_reg_values))
++			return -EINVAL;
++
++		return hm5065_write(sensor, HM5065_REG_EXPOSURE_COMPENSATION,
++				    (u8)ae_bias_menu_reg_values[val]);
++
++	case V4L2_CID_FOCUS_AUTO:
++		return hm5065_set_auto_focus(sensor);
++
++	case V4L2_CID_CONTRAST:
++		return hm5065_write(sensor, HM5065_REG_CONTRAST, val);
++
++	case V4L2_CID_SATURATION:
++		return hm5065_write(sensor, HM5065_REG_COLOR_SATURATION, val);
++
++	case V4L2_CID_BRIGHTNESS:
++		return hm5065_write(sensor, HM5065_REG_BRIGHTNESS, val);
++
++	case V4L2_CID_POWER_LINE_FREQUENCY:
++		return hm5065_set_power_line_frequency(sensor, val);
++
++	case V4L2_CID_GAMMA:
++		return hm5065_write(sensor, HM5065_REG_P0_GAMMA_GAIN, val);
++
++	case V4L2_CID_VFLIP:
++		return hm5065_write(sensor, HM5065_REG_VERTICAL_FLIP,
++				    val ? 1 : 0);
++
++	case V4L2_CID_HFLIP:
++		return hm5065_write(sensor, HM5065_REG_HORIZONTAL_MIRROR,
++				    val ? 1 : 0);
++
++	case V4L2_CID_COLORFX:
++		return hm5065_set_colorfx(sensor, val);
++
++	case V4L2_CID_3A_LOCK:
++		return hm5065_3a_lock(sensor, ctrl);
++
++	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
++		return hm5065_set_white_balance(sensor);
++
++	case V4L2_CID_TEST_PATTERN_RED:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_RED, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENR:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_GREEN_R, val);
++
++	case V4L2_CID_TEST_PATTERN_BLUE:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_BLUE, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENB:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_GREEN_B, val);
++
++	case V4L2_CID_TEST_PATTERN:
++		for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++			v4l2_ctrl_activate(ctrls->test_data[i],
++					   val == 6); /* solid color */
++
++		ret = hm5065_write(sensor, HM5065_REG_ENABLE_TEST_PATTERN,
++				   val == 0 ? 0 : 1);
++		if (ret)
++			return ret;
++
++		return hm5065_write(sensor, HM5065_REG_TEST_PATTERN, val);
++
++	default:
++		return -EINVAL;
++	}
++}
++
++static const struct v4l2_ctrl_ops hm5065_ctrl_ops = {
++	.g_volatile_ctrl = hm5065_g_volatile_ctrl,
++	.s_ctrl = hm5065_s_ctrl,
++};
++
++static const char * const test_pattern_menu[] = {
++	"Disabled",
++	"Horizontal gray scale",
++	"Vertical gray scale",
++	"Diagonal gray scale",
++	"PN28",
++	"PN9 (bus test)",
++	"Solid color",
++	"Color bars",
++	"Graduated color bars",
++};
++
++static int hm5065_init_controls(struct hm5065_dev *sensor)
++{
++	const struct v4l2_ctrl_ops *ops = &hm5065_ctrl_ops;
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++	u8 wb_max = 0;
++	u64 wb_mask = 0;
++	unsigned int i;
++	int ret;
++
++	v4l2_ctrl_handler_init(hdl, 32);
++
++	/* we can use our own mutex for the ctrl lock */
++	hdl->lock = &sensor->lock;
++
++	ctrls->auto_exposure = v4l2_ctrl_new_std_menu(hdl, ops,
++						      V4L2_CID_EXPOSURE_AUTO,
++						      V4L2_EXPOSURE_MANUAL, 0,
++						      V4L2_EXPOSURE_AUTO);
++	ctrls->exposure = v4l2_ctrl_new_std(hdl, ops,
++					    V4L2_CID_EXPOSURE,
++					    1, HM5065_SENSOR_HEIGHT, 1, 30);
++	ctrls->d_gain = v4l2_ctrl_new_std(hdl, ops,
++					  V4L2_CID_DIGITAL_GAIN,
++					  1000, 4000, 1, 1000);
++
++	ctrls->a_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
++					  0, 0xf4, 1, 0);
++
++	ctrls->metering =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_EXPOSURE_METERING,
++				       V4L2_EXPOSURE_METERING_CENTER_WEIGHTED,
++				       0, V4L2_EXPOSURE_METERING_AVERAGE);
++	ctrls->exposure_bias =
++		v4l2_ctrl_new_int_menu(hdl, ops,
++				       V4L2_CID_AUTO_EXPOSURE_BIAS,
++				       ARRAY_SIZE(ae_bias_menu_values) - 1,
++				       AE_BIAS_MENU_DEFAULT_VALUE_INDEX,
++				       ae_bias_menu_values);
++
++	for (i = 0; i < ARRAY_SIZE(hm5065_wb_opts); i++) {
++		if (wb_max < hm5065_wb_opts[i][0])
++			wb_max = hm5065_wb_opts[i][0];
++		wb_mask |= BIT(hm5065_wb_opts[i][0]);
++	}
++
++	ctrls->wb = v4l2_ctrl_new_std_menu(hdl, ops,
++			V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
++			wb_max, ~wb_mask, V4L2_WHITE_BALANCE_AUTO);
++
++	ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
++						0, 4000, 1, 1000);
++	ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
++					       0, 4000, 1, 1000);
++
++	ctrls->gamma = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA,
++					 0, 31, 1, 20);
++
++	ctrls->colorfx =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX, 15,
++				       ~(BIT(V4L2_COLORFX_NONE) |
++					 BIT(V4L2_COLORFX_NEGATIVE) |
++					 BIT(V4L2_COLORFX_SOLARIZATION) |
++					 BIT(V4L2_COLORFX_SKETCH) |
++					 BIT(V4L2_COLORFX_SEPIA) |
++					 BIT(V4L2_COLORFX_ANTIQUE) |
++					 BIT(V4L2_COLORFX_AQUA) |
++					 BIT(V4L2_COLORFX_BW)),
++				       V4L2_COLORFX_NONE);
++
++	ctrls->pl_freq =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
++				V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
++				V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
++
++	ctrls->hflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_HFLIP, 0, 1, 1, 0);
++	ctrls->vflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_VFLIP, 0, 1, 1, 0);
++
++	ctrls->focus_auto = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_AUTO,
++					      0, 1, 1, 1);
++
++	ctrls->af_start = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_START,
++					    0, 1, 1, 0);
++
++	ctrls->af_stop = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_STOP,
++					   0, 1, 1, 0);
++
++	ctrls->af_status = v4l2_ctrl_new_std(hdl, ops,
++					     V4L2_CID_AUTO_FOCUS_STATUS, 0,
++					     (V4L2_AUTO_FOCUS_STATUS_BUSY |
++					      V4L2_AUTO_FOCUS_STATUS_REACHED |
++					      V4L2_AUTO_FOCUS_STATUS_FAILED),
++					     0, V4L2_AUTO_FOCUS_STATUS_IDLE);
++
++	ctrls->af_distance =
++		v4l2_ctrl_new_std_menu(hdl, ops,
++				       V4L2_CID_AUTO_FOCUS_RANGE,
++				       V4L2_AUTO_FOCUS_RANGE_MACRO,
++				       ~(BIT(V4L2_AUTO_FOCUS_RANGE_AUTO) |
++					 BIT(V4L2_AUTO_FOCUS_RANGE_INFINITY) |
++					 BIT(V4L2_AUTO_FOCUS_RANGE_MACRO)),
++				       V4L2_AUTO_FOCUS_RANGE_AUTO);
++
++	ctrls->focus_relative = v4l2_ctrl_new_std(hdl, ops,
++						  V4L2_CID_FOCUS_RELATIVE,
++						  -100, 100, 1, 0);
++
++	ctrls->brightness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS,
++					      0, 200, 1, 90);
++	ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
++					      0, 200, 1, 110);
++	ctrls->contrast = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST,
++					    0, 200, 1, 108);
++
++	ctrls->aaa_lock = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_3A_LOCK,
++					    0, 0x7, 0, 0);
++
++	ctrls->test_pattern =
++		v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
++					     ARRAY_SIZE(test_pattern_menu) - 1,
++					     0, 0, test_pattern_menu);
++	for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++		ctrls->test_data[i] =
++			v4l2_ctrl_new_std(hdl, ops,
++					  V4L2_CID_TEST_PATTERN_RED + i,
++					  0, 1023, 1, 0);
++
++	if (hdl->error) {
++		ret = hdl->error;
++		goto free_ctrls;
++	}
++
++	ctrls->af_status->flags |= V4L2_CTRL_FLAG_VOLATILE |
++		V4L2_CTRL_FLAG_READ_ONLY;
++
++	v4l2_ctrl_auto_cluster(3, &ctrls->wb, V4L2_WHITE_BALANCE_MANUAL, false);
++	v4l2_ctrl_auto_cluster(4, &ctrls->auto_exposure, V4L2_EXPOSURE_MANUAL,
++			       true);
++	v4l2_ctrl_cluster(6, &ctrls->focus_auto);
++
++	sensor->sd.ctrl_handler = hdl;
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(hdl);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Video ops */
++
++static int hm5065_get_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *sd_state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	fi->interval = sensor->frame_interval;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int hm5065_get_max_binning(int width, int height)
++{
++	if (width < HM5065_SENSOR_WIDTH / 4 &&
++	    height < HM5065_SENSOR_HEIGHT / 4)
++		return 4;
++	else if (width < HM5065_SENSOR_WIDTH / 2 &&
++		 height < HM5065_SENSOR_HEIGHT / 2)
++		return 2;
++
++	return 1;
++}
++
++static int hm5065_get_max_fps(int width, int height)
++{
++	int max_fps, bin_factor;
++
++	// more bining allows for faster readouts
++	bin_factor = hm5065_get_max_binning(width, height);
++	max_fps = 25000000 / (width * height * 2) * bin_factor;
++
++	return clamp(max_fps, 1, 60);
++}
++
++static int hm5065_set_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *sd_state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret = 0, fps, max_fps;
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++
++	max_fps = hm5065_get_max_fps(sensor->fmt.width, sensor->fmt.height);
++
++	/* user requested infinite frame rate */
++	if (fi->interval.numerator == 0)
++		fps = max_fps;
++	else
++		fps = DIV_ROUND_CLOSEST(fi->interval.denominator,
++					fi->interval.numerator);
++
++	fps = clamp(fps, 1, max_fps);
++
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = fps;
++	fi->interval = sensor->frame_interval;
++
++	if (sensor->streaming) {
++		ret = hm5065_write16(sensor, HM5065_REG_DESIRED_FRAME_RATE_NUM,
++				     fps);
++		if (ret)
++			goto err_unlock;
++
++		ret = hm5065_write(sensor, HM5065_REG_DESIRED_FRAME_RATE_DEN,
++				   1);
++	}
++
++err_unlock:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++static int hm5065_setup_mode(struct hm5065_dev *sensor)
++{
++	const struct hm5065_pixfmt *pix_fmt;
++	u8 sensor_mode;
++	int ret, fps;
++
++	pix_fmt = hm5065_find_format(sensor->fmt.code);
++	if (!pix_fmt) {
++		dev_err(&sensor->i2c_client->dev,
++			"pixel format not supported %u\n", sensor->fmt.code);
++		return -EINVAL;
++	}
++
++	ret = hm5065_write(sensor, HM5065_REG_USER_COMMAND,
++			   HM5065_REG_USER_COMMAND_POWEROFF);
++	if (ret)
++		return ret;
++
++	switch (hm5065_get_max_binning(sensor->fmt.width, sensor->fmt.height)) {
++	case 4:
++		sensor_mode = HM5065_REG_SENSOR_MODE_BINNING_4X4;
++		break;
++	case 2:
++		sensor_mode = HM5065_REG_SENSOR_MODE_BINNING_2X2;
++		break;
++	default:
++		sensor_mode = HM5065_REG_SENSOR_MODE_FULLSIZE;
++	}
++
++	ret = hm5065_write(sensor, HM5065_REG_P0_SENSOR_MODE, sensor_mode);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write16(sensor, HM5065_REG_P0_MANUAL_HSIZE,
++			     sensor->fmt.width);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write16(sensor, HM5065_REG_P0_MANUAL_VSIZE,
++			     sensor->fmt.height);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_P0_IMAGE_SIZE,
++			   HM5065_REG_IMAGE_SIZE_MANUAL);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_P0_DATA_FORMAT,
++			   pix_fmt->data_fmt);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_YCRCB_ORDER,
++			   pix_fmt->ycbcr_order);
++	if (ret)
++		return ret;
++
++	/* without this, brightness, contrast and saturation will not work */
++	ret = hm5065_write(sensor, HM5065_REG_COLORSPACE, 9);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_BUS_DATA_FORMAT,
++			   pix_fmt->fmt_setup);
++	if (ret)
++		return ret;
++
++	fps = hm5065_get_max_fps(sensor->fmt.width, sensor->fmt.height);
++	fps = clamp(fps, 1, (int)sensor->frame_interval.denominator);
++
++	ret = hm5065_write16(sensor, HM5065_REG_DESIRED_FRAME_RATE_NUM, fps);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_DESIRED_FRAME_RATE_DEN, 1);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int hm5065_set_stream(struct hm5065_dev *sensor, int enable)
++{
++	return hm5065_write(sensor, HM5065_REG_USER_COMMAND, enable ?
++			    HM5065_REG_USER_COMMAND_RUN :
++			    HM5065_REG_USER_COMMAND_STOP);
++}
++
++static int hm5065_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	if (sensor->streaming == !enable) {
++		if (enable && sensor->pending_mode_change) {
++			ret = hm5065_setup_mode(sensor);
++			if (ret)
++				goto out;
++		}
++
++		ret = hm5065_set_stream(sensor, enable);
++		if (ret)
++			goto out;
++
++		if (enable && sensor->ctrls.focus_auto->cur.val) {
++			msleep(100);
++
++			/* checking error here is not super important */
++			hm5065_write(sensor, HM5065_REG_AF_MODE,
++				     HM5065_REG_AF_MODE_CONTINUOUS);
++		}
++
++		sensor->streaming = !!enable;
++	}
++
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Pad ops */
++
++static int hm5065_enum_mbus_code(struct v4l2_subdev *sd,
++				 struct v4l2_subdev_state *sd_state,
++				 struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad != 0)
++		return -EINVAL;
++	if (code->index >= HM5065_NUM_FORMATS)
++		return -EINVAL;
++
++	code->code = hm5065_formats[code->index].code;
++
++	return 0;
++}
++
++static int hm5065_enum_frame_size(struct v4l2_subdev *sd,
++				  struct v4l2_subdev_state *sd_state,
++				  struct v4l2_subdev_frame_size_enum *fse)
++{
++	if (fse->pad != 0)
++		return -EINVAL;
++	if (fse->index != 0)
++		return -EINVAL;
++
++	fse->min_width = HM5065_CAPTURE_WIDTH_MIN;
++	fse->min_height = HM5065_CAPTURE_HEIGHT_MIN;
++
++	fse->max_width = HM5065_SENSOR_WIDTH;
++	fse->max_height = HM5065_SENSOR_HEIGHT;
++
++	return 0;
++}
++
++static int hm5065_enum_frame_interval(struct v4l2_subdev *sd,
++				      struct v4l2_subdev_state *sd_state,
++				      struct v4l2_subdev_frame_interval_enum
++				      *fie)
++{
++	struct v4l2_fract tpf;
++	u32 max_fps, width, height;
++
++	if (fie->pad != 0)
++		return -EINVAL;
++
++	width = clamp(fie->width, HM5065_CAPTURE_WIDTH_MIN,
++		      HM5065_SENSOR_WIDTH);
++	height = clamp(fie->height, HM5065_CAPTURE_HEIGHT_MIN,
++		       HM5065_SENSOR_HEIGHT);
++
++	max_fps = hm5065_get_max_fps(width, height);
++
++	if (fie->index + 1 > max_fps)
++		return -EINVAL;
++
++	tpf.numerator = 1;
++	tpf.denominator = fie->index + 1;
++	fie->interval = tpf;
++
++	return 0;
++}
++
++static int hm5065_get_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	struct v4l2_mbus_framefmt *mf;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		format->format = *mf;
++		return 0;
++	}
++
++	mutex_lock(&sensor->lock);
++	format->format = sensor->fmt;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int hm5065_set_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	const struct hm5065_pixfmt *pixfmt;
++	int ret = 0;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	/* check if we support requested mbus fmt */
++	pixfmt = hm5065_find_format(mf->code);
++	if (!pixfmt)
++		pixfmt = &hm5065_formats[0];
++
++	mf->code = pixfmt->code;
++	mf->colorspace = pixfmt->colorspace;
++	mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
++	mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++	mf->quantization = V4L2_QUANTIZATION_DEFAULT;
++	mf->field = V4L2_FIELD_NONE;
++
++	mutex_lock(&sensor->lock);
++
++	mf->width = clamp(mf->width, HM5065_CAPTURE_WIDTH_MIN,
++			  HM5065_SENSOR_WIDTH);
++	mf->height = clamp(mf->height, HM5065_CAPTURE_HEIGHT_MIN,
++			  HM5065_SENSOR_HEIGHT);
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		struct v4l2_mbus_framefmt *try_mf;
++
++		try_mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		*try_mf = *mf;
++		goto out;
++	}
++
++	if (sensor->streaming) {
++		ret = -EBUSY;
++		goto out;
++	}
++
++	sensor->fmt = *mf;
++	sensor->pending_mode_change = true;
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Core Ops */
++
++static void hm5065_chip_enable(struct hm5065_dev *sensor, bool enable)
++{
++	gpiod_set_value(sensor->enable_gpio, enable ? 1 : 0);
++	gpiod_set_value(sensor->reset_gpio, enable ? 0 : 1);
++}
++
++static int hm5065_configure(struct hm5065_dev *sensor)
++{
++	int ret;
++	u16 device_id;
++	const struct hm5065_clk_lut *lut;
++	unsigned long xclk_freq;
++
++	ret = hm5065_read16(sensor, HM5065_REG_DEVICE_ID, &device_id);
++	if (ret)
++		return ret;
++
++	if (device_id != HM5065_REG_DEVICE_ID_VALUE) {
++		dev_err(&sensor->i2c_client->dev,
++			"unsupported device id: 0x%04x\n",
++			(unsigned int)device_id);
++		return -EINVAL;
++	}
++
++	xclk_freq = clk_get_rate(sensor->xclk);
++	lut = hm5065_find_clk_lut(xclk_freq);
++	if (!lut) {
++		dev_err(&sensor->i2c_client->dev,
++			"xclk frequency out of range: %lu Hz\n", xclk_freq);
++		return -EINVAL;
++	}
++
++	ret = hm5065_write(sensor, HM5065_REG_EXCLOCKLUT, lut->lut_id);
++	if (ret)
++		return ret;
++
++	ret = hm5065_load_firmware(sensor, HM5065_AF_FIRMWARE);
++	if (ret < 0)
++		return ret;
++
++	if (ret == 0) /* ret == 1 means firmware file missing */
++		mdelay(200);
++
++	ret = hm5065_load_firmware(sensor, HM5065_FIRMWARE_PARAMETERS);
++	if (ret < 0)
++		return ret;
++
++	if (sensor->ep.bus_type == V4L2_MBUS_BT656) {
++		ret = hm5065_write(sensor, HM5065_REG_BUS_CONFIG,
++				   HM5065_REG_BUS_CONFIG_BT656);
++	} else {
++		ret = hm5065_write(sensor, HM5065_REG_BUS_CONFIG,
++				   HM5065_REG_BUS_CONFIG_PARALLEL_HH_VL);
++	}
++
++	return ret;
++}
++
++static int hm5065_set_power(struct hm5065_dev *sensor, bool on)
++{
++	int ret = 0;
++
++	if (on) {
++		ret = regulator_bulk_enable(HM5065_NUM_SUPPLIES,
++					    sensor->supplies);
++		if (ret)
++			return ret;
++
++		ret = clk_prepare_enable(sensor->xclk);
++		if (ret)
++			goto power_off;
++
++		ret = clk_set_rate(sensor->xclk, 24000000);
++		if (ret)
++			goto xclk_off;
++
++		usleep_range(1000, 2000);
++		hm5065_chip_enable(sensor, false);
++		usleep_range(1000, 2000);
++		hm5065_chip_enable(sensor, true);
++		usleep_range(50000, 70000);
++
++		ret = hm5065_configure(sensor);
++		if (ret)
++			goto xclk_off;
++
++		ret = hm5065_setup_mode(sensor);
++		if (ret)
++			goto xclk_off;
++
++		return 0;
++	}
++
++xclk_off:
++	clk_disable_unprepare(sensor->xclk);
++power_off:
++	hm5065_chip_enable(sensor, false);
++	regulator_bulk_disable(HM5065_NUM_SUPPLIES, sensor->supplies);
++	msleep(100);
++	return ret;
++}
++
++static int hm5065_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	bool power_up, power_down;
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	power_up = on && !sensor->powered;
++	power_down = !on && sensor->powered;
++
++	if (power_up || power_down) {
++		ret = hm5065_set_power(sensor, power_up);
++		if (!ret)
++			sensor->powered = on;
++	}
++
++	mutex_unlock(&sensor->lock);
++
++	if (!ret && power_up) {
++		/* restore controls */
++		ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
++		if (ret)
++			hm5065_s_power(sd, 0);
++	}
++
++	return ret;
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int hm5065_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret;
++	u8 val = 0;
++
++	if (reg->reg > 0xffff)
++		return -EINVAL;
++
++	reg->size = 1;
++
++	mutex_lock(&sensor->lock);
++	ret = hm5065_read(sensor, reg->reg, &val);
++	mutex_unlock(&sensor->lock);
++	if (ret)
++		return -EIO;
++
++	reg->val = val;
++	return 0;
++}
++
++static int hm5065_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret;
++
++	if (reg->reg > 0xffff || reg->val > 0xff)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	ret = hm5065_write(sensor, reg->reg, reg->val);
++	mutex_unlock(&sensor->lock);
++
++	return ret;
++}
++#endif
++
++/* }}} */
++
++static const struct v4l2_subdev_core_ops hm5065_core_ops = {
++	.s_power = hm5065_s_power,
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = hm5065_g_register,
++	.s_register = hm5065_s_register,
++#endif
++};
++
++static const struct v4l2_subdev_pad_ops hm5065_pad_ops = {
++	.enum_mbus_code = hm5065_enum_mbus_code,
++	.enum_frame_size = hm5065_enum_frame_size,
++	.enum_frame_interval = hm5065_enum_frame_interval,
++	.get_fmt = hm5065_get_fmt,
++	.set_fmt = hm5065_set_fmt,
++	.get_frame_interval = hm5065_get_frame_interval,
++	.set_frame_interval = hm5065_set_frame_interval,
++};
++
++static const struct v4l2_subdev_video_ops hm5065_video_ops = {
++	.s_stream = hm5065_s_stream,
++};
++
++static const struct v4l2_subdev_ops hm5065_subdev_ops = {
++	.core = &hm5065_core_ops,
++	.pad = &hm5065_pad_ops,
++	.video = &hm5065_video_ops,
++};
++
++static int hm5065_get_regulators(struct hm5065_dev *sensor)
++{
++	int i;
++
++	for (i = 0; i < HM5065_NUM_SUPPLIES; i++)
++		sensor->supplies[i].supply = hm5065_supply_name[i];
++
++	return devm_regulator_bulk_get(&sensor->i2c_client->dev,
++				       HM5065_NUM_SUPPLIES,
++				       sensor->supplies);
++}
++
++#define HM5065_PARALLEL_SUPPORT_FLAGS \
++	(V4L2_MBUS_HSYNC_ACTIVE_LOW | V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
++	 V4L2_MBUS_PCLK_SAMPLE_FALLING | V4L2_MBUS_DATA_ACTIVE_HIGH)
++
++static int hm5065_probe(struct i2c_client *client)
++{
++	struct device *dev = &client->dev;
++	struct fwnode_handle *endpoint;
++	struct hm5065_dev *sensor;
++	int ret;
++
++	sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
++	if (!sensor)
++		return -ENOMEM;
++
++	sensor->i2c_client = client;
++
++	sensor->fmt.code = hm5065_formats[0].code;
++	sensor->fmt.width = 1280;
++	sensor->fmt.height = 720;
++	sensor->fmt.field = V4L2_FIELD_NONE;
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = 15;
++	sensor->pending_mode_change = true;
++
++	endpoint = fwnode_graph_get_next_endpoint(
++		of_fwnode_handle(client->dev.of_node), NULL);
++	if (!endpoint) {
++		dev_err(dev, "endpoint node not found\n");
++		return -EINVAL;
++	}
++
++	ret = v4l2_fwnode_endpoint_parse(endpoint, &sensor->ep);
++	fwnode_handle_put(endpoint);
++	if (ret) {
++		dev_err(dev, "could not parse endpoint\n");
++		return ret;
++	}
++
++	/*
++	 * We don't know how to configure the camera for any other parallel
++	 * mode, yet.
++	 */
++	if (sensor->ep.bus_type != V4L2_MBUS_BT656 &&
++	    !(sensor->ep.bus_type == V4L2_MBUS_PARALLEL &&
++	      (sensor->ep.bus.parallel.flags & HM5065_PARALLEL_SUPPORT_FLAGS) ==
++	      HM5065_PARALLEL_SUPPORT_FLAGS)) {
++		dev_err(dev, "unsupported bus configuration %d/%08x\n",
++			sensor->ep.bus_type, sensor->ep.bus.parallel.flags);
++		return -EINVAL;
++	}
++
++	/* get system clock (xclk) */
++	sensor->xclk = devm_clk_get(dev, "xclk");
++	if (IS_ERR(sensor->xclk)) {
++		dev_err(dev, "failed to get xclk\n");
++		return PTR_ERR(sensor->xclk);
++	}
++
++	sensor->enable_gpio = devm_gpiod_get_optional(dev, "enable",
++							  GPIOD_OUT_LOW);
++	sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
++						     GPIOD_OUT_HIGH);
++
++	if (!sensor->enable_gpio && !sensor->reset_gpio) {
++		dev_err(dev,
++			"either chip enable or reset pin must be configured\n");
++		return ret;
++	}
++
++	v4l2_i2c_subdev_init(&sensor->sd, client, &hm5065_subdev_ops);
++
++	sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
++	sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
++	if (ret)
++		return ret;
++
++	ret = hm5065_get_regulators(sensor);
++	if (ret)
++		return ret;
++
++	mutex_init(&sensor->lock);
++
++	ret = hm5065_init_controls(sensor);
++	if (ret)
++		goto entity_cleanup;
++
++	ret = v4l2_async_register_subdev(&sensor->sd);
++	if (ret)
++		goto free_ctrls;
++
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++entity_cleanup:
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	return ret;
++}
++
++static void hm5065_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++
++	v4l2_async_unregister_subdev(&sensor->sd);
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++}
++
++static const struct i2c_device_id hm5065_id[] = {
++	{"hm5065", 0},
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(i2c, hm5065_id);
++
++static const struct of_device_id hm5065_dt_ids[] = {
++	{ .compatible = "himax,hm5065" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, hm5065_dt_ids);
++
++static struct i2c_driver hm5065_i2c_driver = {
++	.driver = {
++		.name  = "hm5065",
++		.of_match_table	= hm5065_dt_ids,
++	},
++	.id_table = hm5065_id,
++	.probe    = hm5065_probe,
++	.remove   = hm5065_remove,
++};
++
++module_i2c_driver(hm5065_i2c_driver);
++
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("HM5065 Camera Subdev Driver");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
new file mode 100644
index 000000000000..ba24eef148f9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
@@ -0,0 +1,52 @@
+From 3c1f4957b8f02c9bcf79fd83da646e489d051bb8 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 13 Jan 2024 21:00:27 +0100
+Subject: media: i2c: gc2145: Move upstream driver out of the way
+
+Upstream only implements MIPI CSI, but we already have a driver
+with parallel bus support.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/Kconfig                     | 4 ++--
+ drivers/media/i2c/Makefile                    | 2 +-
+ drivers/media/i2c/{gc2145.c => gc2145-mipi.c} | 0
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+ rename drivers/media/i2c/{gc2145.c => gc2145-mipi.c} (100%)
+
+diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
+index 00da6022ddd2..0b16e091fb4f 100644
+--- a/drivers/media/i2c/Kconfig
++++ b/drivers/media/i2c/Kconfig
+@@ -70,9 +70,9 @@ config VIDEO_GC0308
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called gc0308.
+ 
+-config VIDEO_GC2145
++config VIDEO_GC2145_MIPI
+ 	select V4L2_CCI_I2C
+-	tristate "GalaxyCore GC2145 sensor support"
++	tristate "GalaxyCore GC2145 sensor support - MIPI variant"
+ 	help
+ 	  This is a V4L2 sensor-level driver for GalaxyCore GC2145
+ 	  2 Mpixel camera.
+diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
+index aed36d8be369..e84186ed81cb 100644
+--- a/drivers/media/i2c/Makefile
++++ b/drivers/media/i2c/Makefile
+@@ -38,7 +38,7 @@ obj-$(CONFIG_VIDEO_DW9768) += dw9768.o
+ obj-$(CONFIG_VIDEO_DW9807_VCM) += dw9807-vcm.o
+ obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/
+ obj-$(CONFIG_VIDEO_GC0308) += gc0308.o
+-obj-$(CONFIG_VIDEO_GC2145) += gc2145.o
++obj-$(CONFIG_VIDEO_GC2145_MIPI) += gc2145-mipi.o
+ obj-$(CONFIG_VIDEO_HI556) += hi556.o
+ obj-$(CONFIG_VIDEO_HI846) += hi846.o
+ obj-$(CONFIG_VIDEO_HI847) += hi847.o
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145-mipi.c
+similarity index 100%
+rename from drivers/media/i2c/gc2145.c
+rename to drivers/media/i2c/gc2145-mipi.c
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
new file mode 100644
index 000000000000..9459dcacbc3f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
@@ -0,0 +1,43 @@
+From 6ed1c6d98845be657c136dc2ced5578415cc570f Mon Sep 17 00:00:00 2001
+From: Robert Mader <robert.mader@collabora.com>
+Date: Mon, 6 May 2024 16:36:05 -0700
+Subject: media: i2c: gc2145: Parse and register properties
+
+In order to propagate V4L2_CID_CAMERA_SENSOR_ROTATION and
+V4L2_CID_CAMERA_ORIENTATION values from the DT to userspace.
+
+Signed-off-by: Robert Mader <robert.mader@collabora.com>
+---
+ drivers/media/i2c/gc2145.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index b505b3f07387..d80e457f275b 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -1272,6 +1272,7 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	const struct v4l2_ctrl_ops *ops = &gc2145_ctrl_ops;
+ 	struct gc2145_ctrls *ctrls = &sensor->ctrls;
+ 	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++	struct v4l2_fwnode_device_properties props;
+ 	//u8 wb_max = 0;
+ 	//u64 wb_mask = 0;
+ 	//unsigned int i;
+@@ -1324,6 +1325,14 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	ctrls->vflip = v4l2_ctrl_new_std(hdl, ops,
+ 					 V4L2_CID_VFLIP, 0, 1, 1, 0);
+ 
++	ret = v4l2_fwnode_device_parse(&sensor->i2c_client->dev, &props);
++	if (ret)
++		goto free_ctrls;
++
++	ret = v4l2_ctrl_new_fwnode_properties(hdl, &gc2145_ctrl_ops,
++					      &props);
++	if (ret)
++		goto free_ctrls;
+ 
+ 	/* Test patterns */
+ 	ctrls->test_pattern =
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
new file mode 100644
index 000000000000..3d64653e4504
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
@@ -0,0 +1,24 @@
+From b8802ff1b6a98d36ddb7fb90a8db3321c9dac3a6 Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Thu, 29 Dec 2022 11:10:41 +0000
+Subject: media: ov5640: Add read-only property for vblank
+
+---
+ drivers/media/i2c/ov5640.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 59a644dc36e2..1b132ee43c81 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -3845,6 +3845,7 @@ static int ov5640_init_controls(struct ov5640_dev *sensor)
+ 	ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+ 	ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+ 	ctrls->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++	ctrls->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+ 	ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
+ 	ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
new file mode 100644
index 000000000000..154802d2f966
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
@@ -0,0 +1,119 @@
+From 9773e51d658ac589c80c9e54a2db7e2c51623d57 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 8 Nov 2023 19:13:37 +0100
+Subject: media: ov5640: Don't powerup the sensor during driver probe
+
+It causes autofocus clicking during boot on some devices, and
+it's enough to do it when turning on the sensor power by media
+pipeline via s_power callback, later on.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 55 +++++++++-----------------------------
+ 1 file changed, 12 insertions(+), 43 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 87129127ced3..1b8344b226b0 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2496,6 +2496,7 @@ static void ov5640_powerup_sequence(struct ov5640_dev *sensor)
+ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
++	u16 chip_id;
+ 	int ret;
+ 
+ 	ret = clk_prepare_enable(sensor->xclk);
+@@ -2519,6 +2520,13 @@ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ 	if (ret)
+ 		goto power_off;
+ 
++	ret = ov5640_read_reg16(sensor, OV5640_REG_CHIP_ID, &chip_id);
++	if (ret) {
++		dev_err(&client->dev, "%s: failed to read chip identifier\n",
++			__func__);
++		goto power_off;
++	}
++
+ 	return 0;
+ 
+ power_off:
+@@ -3840,28 +3848,6 @@ static int ov5640_get_regulators(struct ov5640_dev *sensor)
+ 				       sensor->supplies);
+ }
+ 
+-static int ov5640_check_chip_id(struct ov5640_dev *sensor)
+-{
+-	struct i2c_client *client = sensor->i2c_client;
+-	int ret = 0;
+-	u16 chip_id;
+-
+-	ret = ov5640_read_reg16(sensor, OV5640_REG_CHIP_ID, &chip_id);
+-	if (ret) {
+-		dev_err(&client->dev, "%s: failed to read chip identifier\n",
+-			__func__);
+-		return ret;
+-	}
+-
+-	if (chip_id != 0x5640) {
+-		dev_err(&client->dev, "%s: wrong chip identifier, expected 0x5640, got 0x%x\n",
+-			__func__, chip_id);
+-		return -ENXIO;
+-	}
+-
+-	return 0;
+-}
+-
+ static int ov5640_probe(struct i2c_client *client)
+ {
+ 	struct device *dev = &client->dev;
+@@ -3962,35 +3948,16 @@ static int ov5640_probe(struct i2c_client *client)
+ 	if (ret)
+ 		goto entity_cleanup;
+ 
+-	ret = ov5640_sensor_resume(dev);
+-	if (ret) {
+-		dev_err(dev, "failed to power on\n");
+-		goto free_ctrls;
+-	}
+-
+-	pm_runtime_set_active(dev);
+-	pm_runtime_get_noresume(dev);
+-	pm_runtime_enable(dev);
+-
+-	ret = ov5640_check_chip_id(sensor);
+-	if (ret)
+-		goto err_pm_runtime;
+-
+ 	ret = v4l2_async_register_subdev_sensor(&sensor->sd);
+ 	if (ret)
+-		goto err_pm_runtime;
++		goto free_ctrls;
+ 
++	pm_runtime_enable(dev);
+ 	pm_runtime_set_autosuspend_delay(dev, 1000);
+ 	pm_runtime_use_autosuspend(dev);
+-	pm_runtime_mark_last_busy(dev);
+-	pm_runtime_put_autosuspend(dev);
+ 
+ 	return 0;
+ 
+-err_pm_runtime:
+-	pm_runtime_put_noidle(dev);
+-	pm_runtime_disable(dev);
+-	ov5640_sensor_suspend(dev);
+ free_ctrls:
+ 	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
+ entity_cleanup:
+@@ -4005,6 +3972,8 @@ static void ov5640_remove(struct i2c_client *client)
+ 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
+ 	struct device *dev = &client->dev;
+ 
++	pm_runtime_dont_use_autosuspend(dev);
++
+ 	pm_runtime_disable(dev);
+ 	if (!pm_runtime_status_suspended(dev))
+ 		ov5640_sensor_suspend(dev);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
new file mode 100644
index 000000000000..e9a12cc01e32
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
@@ -0,0 +1,50 @@
+From 8420dcfeda7482b01f2ac8b0f2788eca34d752a9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 24 Jan 2020 18:25:59 +0100
+Subject: media: ov5640: [Experiment] Try to disable denoising/sharpening
+
+Not sure how this works exactly. More tests are needed.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 5162d45fe73b..d19f6edae9fd 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2326,6 +2326,7 @@ static int ov5640_set_mode(struct ov5640_dev *sensor)
+ 	bool auto_gain = sensor->ctrls.auto_gain->val == 1;
+ 	bool auto_exp =  sensor->ctrls.auto_exp->val == V4L2_EXPOSURE_AUTO;
+ 	int ret;
++	u8 tmp;
+ 
+ 	dn_mode = mode->dn_mode;
+ 	orig_dn_mode = orig_mode->dn_mode;
+@@ -2389,6 +2390,22 @@ static int ov5640_set_mode(struct ov5640_dev *sensor)
+ 	if (ret < 0)
+ 		return ret;
+ 
++	ret = ov5640_read_reg(sensor, 0x5308, &tmp);
++	if (ret)
++		return ret;
++
++	ret = ov5640_write_reg(sensor, 0x5308, tmp | 0x10 | 0x40);
++	if (ret)
++		return ret;
++
++	ret = ov5640_write_reg(sensor, 0x5306, 0);
++	if (ret)
++		return ret;
++
++	ret = ov5640_write_reg(sensor, 0x5302, 0);
++	if (ret)
++		return ret;
++
+ 	sensor->pending_mode_change = false;
+ 	sensor->last_mode = mode;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
new file mode 100644
index 000000000000..56c211a749d1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
@@ -0,0 +1,113 @@
+From 2020bc3fb16e60a966aa29aa2549860c27bf721b Mon Sep 17 00:00:00 2001
+From: Benjamin Schaaf <ben.schaaf@gmail.com>
+Date: Mon, 22 Nov 2021 23:38:26 +1100
+Subject: media: ov5640: Fix focus commands blocking until complete
+
+Previously setting the focus controls would block until the sensor
+completed the focus routine.
+---
+ drivers/media/i2c/ov5640.c | 67 ++++++++++----------------------------
+ 1 file changed, 18 insertions(+), 49 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 74004ede5fc8..59a644dc36e2 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2642,6 +2642,19 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 	return -ETIMEDOUT;
+ }
+ 
++static int ov5640_fw_command(struct ov5640_dev *sensor, int command)
++{
++	int ret;
++
++	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, command);
++	if(ret)
++		return ret;
++
++	msleep(5);
++
++	return 0;
++}
++
+ static int ov5640_af_init(struct ov5640_dev *sensor)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
+@@ -2679,6 +2692,11 @@ static int ov5640_af_init(struct ov5640_dev *sensor)
+ 
+ 	// Set lens focus driver on
+ 	ret = ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
++	if (ret)
++		return ret;
++
++	// Set the default focus zone
++	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_ZONE_CONFIG);
+ 	if (ret)
+ 		return ret;
+ 	return ret;
+@@ -3303,35 +3321,6 @@ static int ov5640_set_framefmt(struct ov5640_dev *sensor,
+ 			      is_jpeg ? (BIT(5) | BIT(3)) : 0);
+ }
+ 
+-static int ov5640_fw_command(struct ov5640_dev *sensor, int command)
+-{
+-	u8 fw_ack;
+-	int i;
+-	int ret;
+-
+-	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_ACK, 0x01);
+-	if(ret)
+-		return ret;
+-	
+-	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, command);
+-	if(ret)
+-		return ret;
+-
+-	for (i = 0; i < 100; i++) {
+-		ret = ov5640_read_reg(sensor, OV5640_REG_FW_CMD_ACK, &fw_ack);
+-		if (ret)
+-			return ret;
+-
+-		if (fw_ack == 0){
+-			return ret;
+-		}
+-
+-		msleep(50);
+-	}
+-	return -ETIMEDOUT;
+-}
+-
+-
+ /*
+  * Sensor Controls.
+  */
+@@ -3467,26 +3456,6 @@ static int ov5640_set_ctrl_focus(struct ov5640_dev *sensor, int command)
+ 		return 0;
+ 	}
+ 
+-	if (command == OV5640_FW_CMD_RELEASE_FOCUS) {
+-		dev_dbg(&client->dev, "%s: Releasing autofocus\n",
+-			__func__);
+-		return ov5640_fw_command(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
+-	}
+-	
+-	// Restart zone config
+-	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_ZONE_CONFIG);
+-	if (ret)
+-		return ret;
+-
+-	// Set default focus zones
+-	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_DEFAULT_ZONES);
+-	if (ret)
+-		return ret;
+-
+-	dev_dbg(&client->dev, "%s: Triggering autofocus\n",
+-		__func__);
+-
+-	// Start focussing
+ 	return ov5640_fw_command(sensor, command);
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Implement-autofocus.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Implement-autofocus.patch
new file mode 100644
index 000000000000..80877abcc3a7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Implement-autofocus.patch
@@ -0,0 +1,395 @@
+From 6c25d1b8df191b8f6c39a97c70ba5aaea0fba1aa Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 7 Aug 2022 15:17:09 +0200
+Subject: media: ov5640: Implement autofocus
+
+The autofocus functionality needs a firmware blob loaded into the
+internal microcontroller.
+
+V4L2 doesn't have an api to control all autofocus functionality, but
+this at least makes it possible to focus on the center of the sensor.
+
+Signed-off-by: Martijn Braam <martijn@brixit.nl>
+---
+ drivers/media/i2c/ov5640.c | 279 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 279 insertions(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index ebacb17e7a7b..3e04fe83ab30 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -9,6 +9,7 @@
+ #include <linux/clkdev.h>
+ #include <linux/ctype.h>
+ #include <linux/delay.h>
++#include <linux/firmware.h>
+ #include <linux/device.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/i2c.h>
+@@ -119,6 +120,38 @@
+ #define OV5640_REG_SDE_CTRL5		0x5585
+ #define OV5640_REG_AVG_READOUT		0x56a1
+ 
++/* autofocus registers */
++
++#define OV5640_REG_SYS_RESET00		0x3000
++#define OV5640_REG_SYS_RESET01		0x3001
++#define OV5640_REG_SYS_CLOCK_ENABLE00	0x3004
++#define OV5640_REG_SYS_CLOCK_ENABLE01	0x3005
++
++#define OV5640_REG_FW_CMD_MAIN		0x3022
++#define OV5640_REG_FW_CMD_ACK		0x3023
++#define OV5640_REG_FW_CMD_PARA0		0x3024
++#define OV5640_REG_FW_CMD_PARA1		0x3025
++#define OV5640_REG_FW_CMD_PARA2		0x3026
++#define OV5640_REG_FW_CMD_PARA3		0x3027
++#define OV5640_REG_FW_CMD_PARA4		0x3028
++#define OV5640_REG_FW_STATUS		0x3029
++
++#define OV5640_REG_VCM_CONTROL4		0x3606
++#define OV5640_REG_FIRMWARE_BASE	0x8000
++
++#define OV5640_FW_STATUS_S_FIRMWARE	0x7f
++#define OV5640_FW_STATUS_S_STARTUP	0x7e
++#define OV5640_FW_STATUS_S_IDLE		0x70
++#define OV5640_FW_STATUS_S_FOCUSING	0x00
++#define OV5640_FW_STATUS_S_FOCUSED	0x10
++
++#define OV5640_FW_CMD_TRIGGER_FOCUS	0x03
++#define OV5640_FW_CMD_CONTINUOUS_FOCUS	0x04
++#define OV5640_FW_CMD_GET_FOCUS_RESULT	0x07
++#define OV5640_FW_CMD_RELEASE_FOCUS	0x08
++#define OV5640_FW_CMD_ZONE_CONFIG	0x12
++#define OV5640_FW_CMD_DEFAULT_ZONES	0x80
++
+ enum ov5640_mode_id {
+ 	OV5640_MODE_QQVGA_160_120 = 0,
+ 	OV5640_MODE_QCIF_176_144,
+@@ -423,6 +456,12 @@ struct ov5640_ctrls {
+ 		struct v4l2_ctrl *auto_gain;
+ 		struct v4l2_ctrl *gain;
+ 	};
++	struct {
++		struct v4l2_ctrl *focus_auto;
++		struct v4l2_ctrl *af_start;
++		struct v4l2_ctrl *af_stop;
++		struct v4l2_ctrl *af_status;
++	};
+ 	struct v4l2_ctrl *brightness;
+ 	struct v4l2_ctrl *light_freq;
+ 	struct v4l2_ctrl *saturation;
+@@ -465,6 +504,8 @@ struct ov5640_dev {
+ 
+ 	bool pending_mode_change;
+ 	bool streaming;
++
++	bool af_initialized;
+ };
+ 
+ static inline struct ov5640_dev *to_ov5640_dev(struct v4l2_subdev *sd)
+@@ -2493,6 +2534,118 @@ static void ov5640_powerup_sequence(struct ov5640_dev *sensor)
+ 			 OV5640_REG_SYS_CTRL0_SW_PWDN);
+ }
+ 
++static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
++					const struct firmware *fw)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	const u8 *data = (const u8 *)fw->data;
++	u8 fw_status;
++	int i;
++	int ret;
++
++	// Putting MCU in reset state
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
++	if (ret)
++		return ret;
++
++	// Write firmware
++	for (i = 0; i < fw->size / sizeof(u8); i++)
++		ov5640_write_reg(sensor,
++				OV5640_REG_FIRMWARE_BASE + i, 
++				data[i]);
++
++	// Reset MCU state
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_ACK, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA0, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA1, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA2, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA3, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA4, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_STATUS, 0x7f);
++
++	// Start AF MCU
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x00);
++	if (ret)
++		return ret;
++
++	dev_info(&client->dev, "firmware upload success\n");
++
++	// Wait for firmware to be ready
++	for (i = 0; i < 5; i++) {
++		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
++		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
++			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
++			return ret;
++		}
++		msleep(50);
++	}
++	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x, retrying...\n", fw_status);
++
++	// Putting MCU in reset state
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
++	if (ret)
++		return ret;
++	// Start AF MCU
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x00);
++	if (ret)
++		return ret;
++	// Wait for firmware to be ready
++	for (i = 0; i < 5; i++) {
++		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
++		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
++			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
++			return ret;
++		}
++		msleep(50);
++	}
++	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x\n", fw_status);
++	return -ETIMEDOUT;
++}
++
++static int ov5640_af_init(struct ov5640_dev *sensor)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	const char* fwname = "ov5640_af.bin";
++	const struct firmware *fw;
++	int ret;
++
++	if (sensor->af_initialized) {
++		return 0;
++	}
++
++	if (firmware_request_nowarn(&fw, fwname, &client->dev) == 0) {
++		ret = ov5640_copy_fw_to_device(sensor, fw);
++		if (ret == 0)
++			sensor->af_initialized = 1;
++	} else {
++		dev_warn(&client->dev, "%s: no autofocus firmware available (%s)\n",
++			__func__, fwname);
++		ret = -1;
++	}
++	release_firmware(fw);
++
++	if (ret)
++		return ret;
++
++	// Enable AF systems
++	ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_CLOCK_ENABLE00,
++			     (BIT(6) | BIT(5)), (BIT(6) | BIT(5)));
++	if (ret)
++		return ret;
++	ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_CLOCK_ENABLE01,
++			     BIT(6), BIT(6));
++	if (ret)
++		return ret;
++
++	// Set lens focus driver on
++	ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
++	if (ret)
++		return ret;
++
++	return ret;
++}
++
+ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
+@@ -2514,8 +2667,11 @@ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ 		goto xclk_off;
+ 	}
+ 
++	sensor->af_initialized = 0;
++
+ 	ov5640_powerup_sequence(sensor);
+ 
++
+ 	ret = ov5640_init_slave_id(sensor);
+ 	if (ret)
+ 		goto power_off;
+@@ -3109,6 +3265,35 @@ static int ov5640_set_framefmt(struct ov5640_dev *sensor,
+ 			      is_jpeg ? (BIT(5) | BIT(3)) : 0);
+ }
+ 
++static int ov5640_fw_command(struct ov5640_dev *sensor, int command)
++{
++	u8 fw_ack;
++	int i;
++	int ret;
++
++	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_ACK, 0x01);
++	if(ret)
++		return ret;
++	
++	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, command);
++	if(ret)
++		return ret;
++
++	for (i = 0; i < 100; i++) {
++		ret = ov5640_read_reg(sensor, OV5640_REG_FW_CMD_ACK, &fw_ack);
++		if (ret)
++			return ret;
++
++		if (fw_ack == 0){
++			return ret;
++		}
++
++		msleep(50);
++	}
++	return -ETIMEDOUT;
++}
++
++
+ /*
+  * Sensor Controls.
+  */
+@@ -3225,6 +3410,41 @@ static int ov5640_set_ctrl_exposure(struct ov5640_dev *sensor,
+ 	return ret;
+ }
+ 
++static int ov5640_set_ctrl_focus(struct ov5640_dev *sensor, int command)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	int ret;
++
++	ret = ov5640_af_init(sensor);
++	if (ret) {
++		dev_err(&client->dev, "%s: no autofocus firmware loaded\n",
++			__func__);
++		return 0;
++	}
++
++	if (command == OV5640_FW_CMD_RELEASE_FOCUS) {
++		dev_dbg(&client->dev, "%s: Releasing autofocus\n",
++			__func__);
++		return ov5640_fw_command(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
++	}
++	
++	// Restart zone config
++	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_ZONE_CONFIG);
++	if (ret)
++		return ret;
++
++	// Set default focus zones
++	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_DEFAULT_ZONES);
++	if (ret)
++		return ret;
++
++	dev_dbg(&client->dev, "%s: Triggering autofocus\n",
++		__func__);
++
++	// Start focussing
++	return ov5640_fw_command(sensor, command);
++}
++
+ static int ov5640_set_ctrl_gain(struct ov5640_dev *sensor, bool auto_gain)
+ {
+ 	struct ov5640_ctrls *ctrls = &sensor->ctrls;
+@@ -3340,6 +3560,32 @@ static int ov5640_set_ctrl_vblank(struct ov5640_dev *sensor, int value)
+ 				  mode->height + value);
+ }
+ 
++static int ov5640_get_af_status(struct ov5640_dev *sensor)
++{
++	u8 fw_status;
++	int ret;
++
++	ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
++	if (ret)
++		return ret;
++
++	switch (fw_status) {
++		case OV5640_FW_STATUS_S_FIRMWARE:
++		case OV5640_FW_STATUS_S_STARTUP:
++			return V4L2_AUTO_FOCUS_STATUS_FAILED;
++			break;
++		case OV5640_FW_STATUS_S_IDLE:
++			return V4L2_AUTO_FOCUS_STATUS_IDLE;
++			break;
++		case OV5640_FW_STATUS_S_FOCUSED:
++			return V4L2_AUTO_FOCUS_STATUS_REACHED;
++			break;
++		default:
++			return V4L2_AUTO_FOCUS_STATUS_BUSY;
++			break;
++	}
++}
++
+ static int ov5640_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
+ {
+ 	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
+@@ -3364,6 +3610,12 @@ static int ov5640_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
+ 			return val;
+ 		sensor->ctrls.exposure->val = val;
+ 		break;
++	case V4L2_CID_FOCUS_AUTO:
++		val = ov5640_get_af_status(sensor);
++		if (val < 0)
++			return val;
++		sensor->ctrls.af_status->val = val;
++		break;
+ 	}
+ 
+ 	pm_runtime_mark_last_busy(&sensor->i2c_client->dev);
+@@ -3413,6 +3665,18 @@ static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl)
+ 	case V4L2_CID_AUTO_WHITE_BALANCE:
+ 		ret = ov5640_set_ctrl_white_balance(sensor, ctrl->val);
+ 		break;
++	case V4L2_CID_FOCUS_AUTO:
++		if (ctrl->val)
++			ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_CONTINUOUS_FOCUS);
++		else
++			ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
++		break;
++	case V4L2_CID_AUTO_FOCUS_START:
++		ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_TRIGGER_FOCUS);
++		break;
++	case V4L2_CID_AUTO_FOCUS_STOP:
++		ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
++		break;
+ 	case V4L2_CID_HUE:
+ 		ret = ov5640_set_ctrl_hue(sensor, ctrl->val);
+ 		break;
+@@ -3513,6 +3777,20 @@ static int ov5640_init_controls(struct ov5640_dev *sensor)
+ 	ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
+ 					0, 1023, 1, 0);
+ 
++	/* Autofocus */
++	ctrls->focus_auto = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_AUTO,
++					    0, 1, 1, 0);
++	ctrls->af_start = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_START,
++					    0, 1, 1, 0);
++	ctrls->af_stop = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_STOP,
++					   0, 1, 1, 0);
++	ctrls->af_status = v4l2_ctrl_new_std(hdl, ops,
++					     V4L2_CID_AUTO_FOCUS_STATUS, 0,
++					     (V4L2_AUTO_FOCUS_STATUS_BUSY |
++					      V4L2_AUTO_FOCUS_STATUS_REACHED |
++					      V4L2_AUTO_FOCUS_STATUS_FAILED),
++					     0, V4L2_AUTO_FOCUS_STATUS_IDLE);
++
+ 	ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
+ 					      0, 255, 1, 64);
+ 	ctrls->hue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HUE,
+@@ -3559,6 +3837,7 @@ static int ov5640_init_controls(struct ov5640_dev *sensor)
+ 	v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false);
+ 	v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true);
+ 	v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true);
++	v4l2_ctrl_cluster(4, &ctrls->focus_auto);
+ 
+ 	sensor->sd.ctrl_handler = hdl;
+ 	return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Improve-error-reporting.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Improve-error-reporting.patch
new file mode 100644
index 000000000000..5ac34f365d3b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Improve-error-reporting.patch
@@ -0,0 +1,43 @@
+From d7854ae95951c0f70ec3d50e7e32ebac1f02f10e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 22 Oct 2021 19:52:49 +0200
+Subject: media: ov5640: Improve error reporting
+
+Some probe errors are currently not reported. Report them properly.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index da6a23e3d585..ebacb17e7a7b 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -3939,8 +3939,10 @@ static int ov5640_probe(struct i2c_client *client)
+ 		return ret;
+ 
+ 	ret = ov5640_get_regulators(sensor);
+-	if (ret)
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to get regulators\n");
+ 		goto entity_cleanup;
++	}
+ 
+ 	mutex_init(&sensor->lock);
+ 
+@@ -3949,8 +3951,10 @@ static int ov5640_probe(struct i2c_client *client)
+ 		goto entity_cleanup;
+ 
+ 	ret = v4l2_async_register_subdev_sensor(&sensor->sd);
+-	if (ret)
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to register sensor\n");
+ 		goto free_ctrls;
++	}
+ 
+ 	pm_runtime_enable(dev);
+ 	pm_runtime_set_autosuspend_delay(dev, 1000);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Improve-firmware-load-time.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Improve-firmware-load-time.patch
new file mode 100644
index 000000000000..a562449b77db
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Improve-firmware-load-time.patch
@@ -0,0 +1,177 @@
+From c78f09b1c7e46112209711905b18cb6a9f93758e Mon Sep 17 00:00:00 2001
+From: Benjamin Schaaf <ben.schaaf@gmail.com>
+Date: Mon, 22 Nov 2021 23:38:26 +1100
+Subject: media: ov5640: Improve firmware load time
+
+Downloading the firmware can be done in groups to minimize i2c packets.
+The firmware status is set practically immediately upon successfully
+loading it, so there's no need for a long timeout or retry. The
+firmware can also not be loaded when the sensor isn't powered on, so
+don't bother trying.
+---
+ drivers/media/i2c/ov5640.c | 97 ++++++++++++++++++++++++++++----------
+ 1 file changed, 71 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 3e04fe83ab30..74004ede5fc8 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -1232,6 +1232,8 @@ static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val)
+ 	msg.buf = buf;
+ 	msg.len = sizeof(buf);
+ 
++	dev_dbg(&client->dev, "[wr %04x] <= %d\n", reg, val);
++
+ 	ret = i2c_transfer(client->adapter, &msg, 1);
+ 	if (ret < 0) {
+ 		dev_err(&client->dev, "%s: error: reg=%x, val=%x\n",
+@@ -1242,6 +1244,42 @@ static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val)
+ 	return 0;
+ }
+ 
++static int ov5640_write_regs(struct ov5640_dev *sensor, u16 reg,
++			     const u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg;
++	u8 buf[254 + 2];
++	int ret;
++
++	if (data_size > sizeof(buf) - 2) {
++		v4l2_err(&sensor->sd, "%s: oversized transfer (size=%d)\n",
++			 __func__, data_size);
++		return -EINVAL;
++	}
++
++	buf[0] = reg >> 8;
++	buf[1] = reg & 0xff;
++	memcpy(buf + 2, data, data_size);
++
++	msg.addr = client->addr;
++	msg.flags = client->flags;
++	msg.buf = buf;
++	msg.len = data_size + 2;
++
++	dev_dbg(&client->dev, "[wr %04x] <= %*ph\n", (u32)reg, data_size, data);
++
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: reg=%x, data=%*ph\n",
++			 __func__, ret, (u32)reg, data_size, data);
++		return ret;
++	}
++
++	return 0;
++}
++
+ static int ov5640_read_reg(struct ov5640_dev *sensor, u16 reg, u8 *val)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
+@@ -2542,6 +2580,7 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 	u8 fw_status;
+ 	int i;
+ 	int ret;
++	int num_groups, group_size = 254;
+ 
+ 	// Putting MCU in reset state
+ 	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
+@@ -2549,10 +2588,24 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 		return ret;
+ 
+ 	// Write firmware
+-	for (i = 0; i < fw->size / sizeof(u8); i++)
+-		ov5640_write_reg(sensor,
+-				OV5640_REG_FIRMWARE_BASE + i, 
+-				data[i]);
++	num_groups = fw->size / group_size;
++	for (i = 0; i < num_groups; i++) {
++		ret = ov5640_write_regs(sensor,
++					OV5640_REG_FIRMWARE_BASE + i * group_size,
++					data + i * group_size,
++					group_size);
++		if (ret)
++			return ret;
++	}
++
++	if (i * group_size < fw->size) {
++		ret = ov5640_write_regs(sensor,
++					OV5640_REG_FIRMWARE_BASE + i * group_size,
++					data + i * group_size,
++					fw->size - i * group_size);
++		if (ret)
++			return ret;
++	}
+ 
+ 	// Reset MCU state
+ 	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, 0x00);
+@@ -2574,31 +2627,17 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 	// Wait for firmware to be ready
+ 	for (i = 0; i < 5; i++) {
+ 		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
+-		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
+-			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
++		if (ret) {
+ 			return ret;
+ 		}
+-		msleep(50);
+-	}
+-	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x, retrying...\n", fw_status);
+ 
+-	// Putting MCU in reset state
+-	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
+-	if (ret)
+-		return ret;
+-	// Start AF MCU
+-	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x00);
+-	if (ret)
+-		return ret;
+-	// Wait for firmware to be ready
+-	for (i = 0; i < 5; i++) {
+-		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
+ 		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
+-			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
+-			return ret;
++			dev_info(&client->dev, "fw started after %d ms\n", i * 5);
++			return 0;
+ 		}
+-		msleep(50);
++		msleep(5);
+ 	}
++
+ 	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x\n", fw_status);
+ 	return -ETIMEDOUT;
+ }
+@@ -2639,10 +2678,9 @@ static int ov5640_af_init(struct ov5640_dev *sensor)
+ 		return ret;
+ 
+ 	// Set lens focus driver on
+-	ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
++	ret = ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
+ 	if (ret)
+ 		return ret;
+-
+ 	return ret;
+ }
+ 
+@@ -3415,9 +3453,16 @@ static int ov5640_set_ctrl_focus(struct ov5640_dev *sensor, int command)
+ 	struct i2c_client *client = sensor->i2c_client;
+ 	int ret;
+ 
++	// Don't attempt to do focus if the embedded controller is powered down
++	if (!sensor->streaming) {
++		dev_err(&client->dev, "%s: can't set focus when not powered\n",
++			__func__);
++		return 0;
++	}
++
+ 	ret = ov5640_af_init(sensor);
+ 	if (ret) {
+-		dev_err(&client->dev, "%s: no autofocus firmware loaded\n",
++		dev_err(&client->dev, "%s: autofocus firmware load failed\n",
+ 			__func__);
+ 		return 0;
+ 	}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
new file mode 100644
index 000000000000..e236bc23ea34
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
@@ -0,0 +1,29 @@
+From eca322845efe464f9a638f7bd504bd1fef87b2e8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 26 Jan 2020 00:19:40 +0100
+Subject: media: ov5640: Sleep after poweroff to ensure next poweron is not too
+ early
+
+It's easy to use v4l2 userspace api in such a way that user can trigger
+a brownout on the sensor instead of a proper powerdown and powerup.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index d19f6edae9fd..87129127ced3 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2534,6 +2534,7 @@ static void ov5640_set_power_off(struct ov5640_dev *sensor)
+ 	ov5640_power(sensor, false);
+ 	regulator_bulk_disable(OV5640_NUM_SUPPLIES, sensor->supplies);
+ 	clk_disable_unprepare(sensor->xclk);
++	msleep(100);
+ }
+ 
+ static int ov5640_set_power_mipi(struct ov5640_dev *sensor, bool on)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-set-default-ae-target-lower.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-set-default-ae-target-lower.patch
new file mode 100644
index 000000000000..3a97687897cb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-set-default-ae-target-lower.patch
@@ -0,0 +1,27 @@
+From f0565c0ed6806e53b3878a6fc29f42663ab2b63c Mon Sep 17 00:00:00 2001
+From: Martijn Braam <martijn@brixit.nl>
+Date: Wed, 7 Oct 2020 17:33:43 +0200
+Subject: media: ov5640: set default ae target lower
+
+The OV5640 tries to overexpose all photos by about 1 stop. This makes
+the exposure target one stop lower.
+---
+ drivers/media/i2c/ov5640.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 1b8344b226b0..da6a23e3d585 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -3874,7 +3874,7 @@ static int ov5640_probe(struct i2c_client *client)
+ 	sensor->current_link_freq =
+ 		ov5640_csi2_link_freqs[OV5640_DEFAULT_LINK_FREQ];
+ 
+-	sensor->ae_target = 52;
++	sensor->ae_target = 28;
+ 
+ 	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev),
+ 						  NULL);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
new file mode 100644
index 000000000000..9ef69cbd1799
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
@@ -0,0 +1,31 @@
+From f2ae45d175480d10e092a132c91003631eb87ca8 Mon Sep 17 00:00:00 2001
+From: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+Date: Mon, 14 Aug 2023 13:25:07 +0300
+Subject: media: ov5640: use pm_runtime_force_suspend/resume for system suspend
+
+If system was suspended while camera sensor was used, data and
+interrupts were still coming from sensor and that caused unstable
+system. Sometimes system hanged during a resume. Use
+pm_runtime_force_* helpers in order to support system suspend.
+
+Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+---
+ drivers/media/i2c/ov5640.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 1b132ee43c81..83e8a06506e9 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -4284,6 +4284,8 @@ static void ov5640_remove(struct i2c_client *client)
+ }
+ 
+ static const struct dev_pm_ops ov5640_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
+ 	SET_RUNTIME_PM_OPS(ov5640_sensor_suspend, ov5640_sensor_resume, NULL)
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
new file mode 100644
index 000000000000..1ea05e55e275
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
@@ -0,0 +1,29 @@
+From 6434ca55ff1e8cdb1a86f445b250a521340d2fa5 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 24 Apr 2024 00:00:31 +0200
+Subject: media: ov5648: Fix call to pm_runtime_set_suspended
+
+It should be done when RPM is disabled.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5648.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/i2c/ov5648.c b/drivers/media/i2c/ov5648.c
+index 4b86d2631bd1..c691e235388a 100644
+--- a/drivers/media/i2c/ov5648.c
++++ b/drivers/media/i2c/ov5648.c
+@@ -2566,8 +2566,8 @@ static int ov5648_probe(struct i2c_client *client)
+ 
+ 	/* Runtime PM */
+ 
+-	pm_runtime_enable(sensor->dev);
+ 	pm_runtime_set_suspended(sensor->dev);
++	pm_runtime_enable(sensor->dev);
+ 
+ 	/* V4L2 subdev register */
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-rkisp1-Adapt-to-different-SoCs-having-different-size-limi.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-rkisp1-Adapt-to-different-SoCs-having-different-size-limi.patch
new file mode 100644
index 000000000000..401359f512fc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-rkisp1-Adapt-to-different-SoCs-having-different-size-limi.patch
@@ -0,0 +1,167 @@
+From aa7ff283cf92d115dbf66e2c622c92a611b9c6cb Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 15 Mar 2024 23:37:01 +0100
+Subject: media: rkisp1: Adapt to different SoCs having different size limits
+
+- RK3399 has input/output limit of main path 4416 x 3312
+- PX30 has input/output limit of main path 3264 x 2448
+- i.MX8MP has input/output limit of main path 4096 x 3072
+
+Use rkisp1_info struct to encode the limits.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+
+# Conflicts:
+#	drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+---
+ drivers/media/platform/rockchip/rkisp1/rkisp1-common.h  | 6 ++++--
+ drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c     | 5 +++--
+ drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c     | 6 ++++++
+ drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c     | 9 +++++----
+ drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c | 4 ++--
+ 5 files changed, 20 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+index 26573f6ae575..b4c958b93629 100644
+--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
++++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+@@ -34,8 +34,6 @@ struct regmap;
+ #define RKISP1_ISP_SD_SINK			BIT(1)
+ 
+ /* min and max values for the widths and heights of the entities */
+-#define RKISP1_ISP_MAX_WIDTH			4032
+-#define RKISP1_ISP_MAX_HEIGHT			3024
+ #define RKISP1_ISP_MIN_WIDTH			32
+ #define RKISP1_ISP_MIN_HEIGHT			32
+ 
+@@ -140,6 +138,8 @@ enum rkisp1_feature {
+  * @isr_size: number of entries in the @isrs array
+  * @isp_ver: ISP version
+  * @features: bitmask of rkisp1_feature features implemented by the ISP
++ * @max_width: maximum input frame width
++ * @max_height: maximum input frame height
+  *
+  * This structure contains information about the ISP specific to a particular
+  * ISP model, version, or integration in a particular SoC.
+@@ -151,6 +151,8 @@ struct rkisp1_info {
+ 	unsigned int isr_size;
+ 	enum rkisp1_cif_isp_version isp_ver;
+ 	unsigned int features;
++	unsigned int max_width;
++	unsigned int max_height;
+ };
+ 
+ /*
+diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c
+index 4202642e0523..841e58c20f7f 100644
+--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c
++++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c
+@@ -307,6 +307,7 @@ static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd,
+ 			      struct v4l2_subdev_state *sd_state,
+ 			      struct v4l2_subdev_format *fmt)
+ {
++	struct rkisp1_csi *csi = to_rkisp1_csi(sd);
+ 	const struct rkisp1_mbus_info *mbus_info;
+ 	struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
+ 
+@@ -326,10 +327,10 @@ static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd,
+ 
+ 	sink_fmt->width = clamp_t(u32, fmt->format.width,
+ 				  RKISP1_ISP_MIN_WIDTH,
+-				  RKISP1_ISP_MAX_WIDTH);
++				  csi->rkisp1->info->max_width);
+ 	sink_fmt->height = clamp_t(u32, fmt->format.height,
+ 				   RKISP1_ISP_MIN_HEIGHT,
+-				   RKISP1_ISP_MAX_HEIGHT);
++				   csi->rkisp1->info->max_height);
+ 
+ 	fmt->format = *sink_fmt;
+ 
+diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+index bb0202386c70..0535ce57e862 100644
+--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
++++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+@@ -510,6 +510,8 @@ static const struct rkisp1_info px30_isp_info = {
+ 	.features = RKISP1_FEATURE_MIPI_CSI2
+ 		  | RKISP1_FEATURE_SELF_PATH
+ 		  | RKISP1_FEATURE_DUAL_CROP,
++	.max_width = 3264,
++	.max_height = 2448,
+ };
+ 
+ static const char * const rk3399_isp_clks[] = {
+@@ -531,6 +533,8 @@ static const struct rkisp1_info rk3399_isp_info = {
+ 	.features = RKISP1_FEATURE_MIPI_CSI2
+ 		  | RKISP1_FEATURE_SELF_PATH
+ 		  | RKISP1_FEATURE_DUAL_CROP,
++	.max_width = 4416,
++	.max_height = 3312,
+ };
+ 
+ static const char * const imx8mp_isp_clks[] = {
+@@ -551,6 +555,8 @@ static const struct rkisp1_info imx8mp_isp_info = {
+ 	.isp_ver = RKISP1_V_IMX8MP,
+ 	.features = RKISP1_FEATURE_MAIN_STRIDE
+ 		  | RKISP1_FEATURE_DMA_34BIT,
++	.max_width = 4096,
++	.max_height = 3072,
+ };
+ 
+ static const struct of_device_id rkisp1_of_match[] = {
+diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
+index e45a213baf49..f787a7e91e3e 100644
+--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
++++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
+@@ -517,6 +517,7 @@ static int rkisp1_isp_enum_frame_size(struct v4l2_subdev *sd,
+ 				      struct v4l2_subdev_state *sd_state,
+ 				      struct v4l2_subdev_frame_size_enum *fse)
+ {
++	struct rkisp1_isp *isp = to_rkisp1_isp(sd);
+ 	const struct rkisp1_mbus_info *mbus_info;
+ 
+ 	if (fse->pad == RKISP1_ISP_PAD_SINK_PARAMS ||
+@@ -539,9 +540,9 @@ static int rkisp1_isp_enum_frame_size(struct v4l2_subdev *sd,
+ 		return -EINVAL;
+ 
+ 	fse->min_width = RKISP1_ISP_MIN_WIDTH;
+-	fse->max_width = RKISP1_ISP_MAX_WIDTH;
++	fse->max_width = isp->rkisp1->info->max_width;
+ 	fse->min_height = RKISP1_ISP_MIN_HEIGHT;
+-	fse->max_height = RKISP1_ISP_MAX_HEIGHT;
++	fse->max_height = isp->rkisp1->info->max_height;
+ 
+ 	return 0;
+ }
+@@ -772,10 +773,10 @@ static void rkisp1_isp_set_sink_fmt(struct rkisp1_isp *isp,
+ 
+ 	sink_fmt->width = clamp_t(u32, format->width,
+ 				  RKISP1_ISP_MIN_WIDTH,
+-				  RKISP1_ISP_MAX_WIDTH);
++				  isp->rkisp1->info->max_width);
+ 	sink_fmt->height = clamp_t(u32, format->height,
+ 				   RKISP1_ISP_MIN_HEIGHT,
+-				   RKISP1_ISP_MAX_HEIGHT);
++				   isp->rkisp1->info->max_height);
+ 
+ 	/*
+ 	 * Adjust the color space fields. Accept any color primaries and
+diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
+index 6f3931ca5b51..e22cc2db24cf 100644
+--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
++++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
+@@ -494,10 +494,10 @@ static void rkisp1_rsz_set_sink_fmt(struct rkisp1_resizer *rsz,
+ 
+ 	sink_fmt->width = clamp_t(u32, format->width,
+ 				  RKISP1_ISP_MIN_WIDTH,
+-				  RKISP1_ISP_MAX_WIDTH);
++				  rsz->rkisp1->info->max_width);
+ 	sink_fmt->height = clamp_t(u32, format->height,
+ 				   RKISP1_ISP_MIN_HEIGHT,
+-				   RKISP1_ISP_MAX_HEIGHT);
++				   rsz->rkisp1->info->max_height);
+ 
+ 	/*
+ 	 * Adjust the color space fields. Accept any color primaries and
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
new file mode 100644
index 000000000000..3f213291f4e4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
@@ -0,0 +1,166 @@
+From 4bebd466efce4fbe53aa458b17ab30b1ebd98bb4 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 6 Jan 2023 11:25:09 +0100
+Subject: media: sun6i-csi: Add multicamera support for parallel bus
+
+Multiple cameras may be connected to parallel bus eg. in a tablet.
+Allow to register multiple parallel bus subdevices and switch between
+them by enabling/disabling media graph links.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.c        | 51 +++++++++++--------
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.h        |  4 +-
+ 2 files changed, 33 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+index 92290876a8b3..0ea1fae7352e 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+@@ -207,12 +207,12 @@ static void sun6i_csi_bridge_disable(struct sun6i_csi_device *csi_dev)
+ 
+ static void
+ sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev,
+-				    struct v4l2_subdev_state *state)
++				    struct v4l2_subdev_state *state,
++				    struct sun6i_csi_bridge_source *source)
+ {
+ 	struct device *dev = csi_dev->dev;
+ 	struct regmap *regmap = csi_dev->regmap;
+-	struct v4l2_fwnode_endpoint *endpoint =
+-		&csi_dev->bridge.source_parallel.endpoint;
++	struct v4l2_fwnode_endpoint *endpoint = &source->endpoint;
+ 	unsigned char bus_width = endpoint->bus.parallel.bus_width;
+ 	unsigned int flags = endpoint->bus.parallel.flags;
+ 	const struct v4l2_mbus_framefmt *sink_format;
+@@ -377,10 +377,8 @@ static void sun6i_csi_bridge_configure(struct sun6i_csi_device *csi_dev,
+ 				       struct sun6i_csi_bridge_source *source,
+ 				       struct v4l2_subdev_state *state)
+ {
+-	struct sun6i_csi_bridge *bridge = &csi_dev->bridge;
+-
+-	if (source == &bridge->source_parallel)
+-		sun6i_csi_bridge_configure_parallel(csi_dev, state);
++	if (source->endpoint.bus_type == V4L2_MBUS_PARALLEL)
++		sun6i_csi_bridge_configure_parallel(csi_dev, state, source);
+ 	else
+ 		sun6i_csi_bridge_configure_mipi_csi2(csi_dev, state);
+ 
+@@ -396,11 +394,11 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 	struct media_pad *local_pad = &bridge->pads[SUN6I_CSI_BRIDGE_PAD_SINK];
+ 	bool capture_streaming = csi_dev->capture.state.streaming;
+ 	struct device *dev = csi_dev->dev;
+-	struct sun6i_csi_bridge_source *source;
++	struct sun6i_csi_bridge_source *source = NULL;
+ 	struct v4l2_subdev *source_subdev;
+ 	struct media_pad *remote_pad;
+ 	struct v4l2_subdev_state *state;
+-	int ret;
++	int ret, i;
+ 
+ 	/* Source */
+ 
+@@ -413,10 +411,20 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 
+ 	source_subdev = media_entity_to_v4l2_subdev(remote_pad->entity);
+ 
+-	if (source_subdev == bridge->source_parallel.subdev)
+-		source = &bridge->source_parallel;
+-	else
++	if (source_subdev == bridge->source_mipi_csi2.subdev) {
+ 		source = &bridge->source_mipi_csi2;
++	} else {
++		for (i = 0; i < SUN6I_CSI_SOURCE_PARALLEL_MAX; i++) {
++			if (source_subdev == bridge->source_parallel[i].subdev) {
++				source = &bridge->source_parallel[i];
++				break;
++			}
++		}
++	}
++	if (!source) {
++		dev_err(dev, "bridge source not found\n");
++		return -ENODEV;
++	}
+ 
+ 	if (!on) {
+ 		v4l2_subdev_call(source_subdev, video, s_stream, 0);
+@@ -647,10 +655,10 @@ sun6i_csi_bridge_notifier_bound(struct v4l2_async_notifier *notifier,
+ 
+ 	switch (source->endpoint.base.port) {
+ 	case SUN6I_CSI_PORT_PARALLEL:
+-		enabled = true;
++		enabled = source->endpoint.base.id == 0;
+ 		break;
+ 	case SUN6I_CSI_PORT_MIPI_CSI2:
+-		enabled = !bridge->source_parallel.expected;
++		enabled = !bridge->source_parallel[0].expected;
+ 		break;
+ 	default:
+ 		return -EINVAL;
+@@ -696,7 +704,7 @@ sun6i_csi_bridge_notifier_ops = {
+ 
+ static int sun6i_csi_bridge_source_setup(struct sun6i_csi_device *csi_dev,
+ 					 struct sun6i_csi_bridge_source *source,
+-					 u32 port,
++					 u32 port, u32 ep,
+ 					 enum v4l2_mbus_type *bus_types)
+ {
+ 	struct device *dev = csi_dev->dev;
+@@ -706,7 +714,7 @@ static int sun6i_csi_bridge_source_setup(struct sun6i_csi_device *csi_dev,
+ 	struct fwnode_handle *handle;
+ 	int ret;
+ 
+-	handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), port, 0, 0);
++	handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), port, ep, 0);
+ 	if (!handle)
+ 		return -ENODEV;
+ 
+@@ -765,7 +773,7 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 		V4L2_MBUS_BT656,
+ 		V4L2_MBUS_INVALID
+ 	};
+-	int ret;
++	int ret, i;
+ 
+ 	/* V4L2 Subdev */
+ 
+@@ -817,11 +825,12 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 		v4l2_async_nf_init(notifier, v4l2_dev);
+ 	notifier->ops = &sun6i_csi_bridge_notifier_ops;
+ 
+-	sun6i_csi_bridge_source_setup(csi_dev, &bridge->source_parallel,
+-				      SUN6I_CSI_PORT_PARALLEL,
+-				      parallel_mbus_types);
++	for (i = 0; i < SUN6I_CSI_SOURCE_PARALLEL_MAX; i++)
++		sun6i_csi_bridge_source_setup(csi_dev, &bridge->source_parallel[i],
++					      SUN6I_CSI_PORT_PARALLEL, i,
++					      parallel_mbus_types);
+ 	sun6i_csi_bridge_source_setup(csi_dev, &bridge->source_mipi_csi2,
+-				      SUN6I_CSI_PORT_MIPI_CSI2, NULL);
++				      SUN6I_CSI_PORT_MIPI_CSI2, 0, NULL);
+ 
+ 	ret = v4l2_async_nf_register(notifier);
+ 	if (ret) {
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+index a5b0a6f064dd..e755b67a2db3 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+@@ -38,12 +38,14 @@ struct sun6i_csi_bridge_async_subdev {
+ 	struct sun6i_csi_bridge_source	*source;
+ };
+ 
++#define SUN6I_CSI_SOURCE_PARALLEL_MAX 2
++
+ struct sun6i_csi_bridge {
+ 	struct v4l2_subdev		subdev;
+ 	struct v4l2_async_notifier	notifier;
+ 	struct media_pad		pads[2];
+ 
+-	struct sun6i_csi_bridge_source	source_parallel;
++	struct sun6i_csi_bridge_source	source_parallel[SUN6I_CSI_SOURCE_PARALLEL_MAX];
+ 	struct sun6i_csi_bridge_source	source_mipi_csi2;
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
new file mode 100644
index 000000000000..45d337b5f065
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
@@ -0,0 +1,82 @@
+From 6823b7c12ee15c653c97689ea0e9bc53619d5439 Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Tue, 3 Jan 2023 18:52:04 +0000
+Subject: media: sun6i-csi: add V4L2_CAP_IO_MC capability
+
+Advertise the V4L2_CAP_IO_MC flag and update
+sun6i_csi_capture_enum_fmt to work with this capability.
+
+With the capability adverstised, the VIDIOC_ENUM_FMT ioctl
+implementation is updated to enumerate pixel formats depending
+on the supplied mbus_code.  If the code is 0, all formats are
+enumerated, if not, only pixel formats that match with the supplied
+mbus_code are enumeratd.
+
+Signed-off-by: Adam Pigg <adam@piggz.co.uk>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 37 +++++++++++++++++--
+ 1 file changed, 34 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index 510f4597a18e..371fe49753a4 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -722,13 +722,43 @@ static int sun6i_csi_capture_enum_fmt(struct file *file, void *private,
+ 				      struct v4l2_fmtdesc *fmtdesc)
+ {
+ 	u32 index = fmtdesc->index;
++	unsigned int i;
+ 
+ 	if (index >= ARRAY_SIZE(sun6i_csi_capture_formats))
+ 		return -EINVAL;
+ 
+-	fmtdesc->pixelformat = sun6i_csi_capture_formats[index].pixelformat;
++	for (i = 0; i < ARRAY_SIZE(sun6i_csi_capture_formats); i++) {
++		const struct sun6i_csi_capture_format *format =
++			&sun6i_csi_capture_formats[i];
+ 
+-	return 0;
++		/*
++		 * If a media bus code is specified, only consider formats that
++		 * match it.
++		 */
++		if (fmtdesc->mbus_code) {
++			unsigned int j;
++
++			if (!format->mbus_codes)
++				continue;
++
++			for (j = 0; format->mbus_codes[j]; j++) {
++				if (fmtdesc->mbus_code == format->mbus_codes[j])
++					break;
++			}
++
++			if (!format->mbus_codes[j])
++				continue;
++		}
++
++		if (index == 0) {
++			fmtdesc->pixelformat = format->pixelformat;
++			return 0;
++		}
++
++		index--;
++	}
++
++	return -EINVAL;
+ }
+ 
+ static int sun6i_csi_capture_g_fmt(struct file *file, void *private,
+@@ -1034,7 +1064,8 @@ int sun6i_csi_capture_setup(struct sun6i_csi_device *csi_dev)
+ 
+ 	strscpy(video_dev->name, SUN6I_CSI_CAPTURE_NAME,
+ 		sizeof(video_dev->name));
+-	video_dev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++	video_dev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING
++				| V4L2_CAP_IO_MC;
+ 	video_dev->vfl_dir = VFL_DIR_RX;
+ 	video_dev->release = video_device_release_empty;
+ 	video_dev->fops = &sun6i_csi_capture_fops;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
new file mode 100644
index 000000000000..b0df91804b8d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
@@ -0,0 +1,128 @@
+From dd852ceae37a6f8c7f700aaa3786994f312a6896 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Date: Wed, 4 Jan 2023 12:29:56 +0200
+Subject: media: sun6i-csi: capture: Use subdev operation to access bridge
+ format
+
+Replace the sun6i_csi_bridge helper functions sun6i_csi_bridge_format()
+and sun6i_csi_bridge_dimensions() that access the bridge fields from the
+capture side with usage of the subdev .get_fmt() operation. This
+decouples the bridge and capture side better by using abstractions
+provided by the V4L2 subdev API, and prepares for usage of the subdev
+active state in the bridge.
+
+The sun6i_csi_bridge_dimensions() helper is now unused and is removed.
+The sun6i_csi_bridge_format() helper will be removed in a subsequent
+change.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit e728c6bbead7a10d9ffd1139e416e1199b5837a6)
+---
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.c        | 13 ++---------
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.h        |  7 ------
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 23 ++++++++++++-------
+ 3 files changed, 17 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+index d006d9dd0170..2303e5d2baee 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+@@ -15,17 +15,8 @@
+ 
+ /* Helpers */
+ 
+-void sun6i_csi_bridge_dimensions(struct sun6i_csi_device *csi_dev,
+-				 unsigned int *width, unsigned int *height)
+-{
+-	if (width)
+-		*width = csi_dev->bridge.mbus_format.width;
+-	if (height)
+-		*height = csi_dev->bridge.mbus_format.height;
+-}
+-
+-void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
+-			     u32 *mbus_code, u32 *field)
++static void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
++				    u32 *mbus_code, u32 *field)
+ {
+ 	if (mbus_code)
+ 		*mbus_code = csi_dev->bridge.mbus_format.code;
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+index 44653b38f722..722b633b7893 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+@@ -49,13 +49,6 @@ struct sun6i_csi_bridge {
+ 	struct sun6i_csi_bridge_source	source_mipi_csi2;
+ };
+ 
+-/* Helpers */
+-
+-void sun6i_csi_bridge_dimensions(struct sun6i_csi_device *csi_dev,
+-				 unsigned int *width, unsigned int *height);
+-void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
+-			     u32 *mbus_code, u32 *field);
+-
+ /* Format */
+ 
+ const struct sun6i_csi_bridge_format *
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index 14c0dc827c52..b26dc8bf55b0 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -893,11 +893,14 @@ static int sun6i_csi_capture_link_validate(struct media_link *link)
+ 	const struct sun6i_csi_capture_format *capture_format;
+ 	const struct sun6i_csi_bridge_format *bridge_format;
+ 	unsigned int capture_width, capture_height;
+-	unsigned int bridge_width, bridge_height;
+ 	const struct v4l2_format_info *format_info;
+ 	u32 pixelformat, capture_field;
+-	u32 mbus_code, bridge_field;
++	struct v4l2_subdev_format fmt = {
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++		.pad = SUN6I_CSI_BRIDGE_PAD_SOURCE,
++	};
+ 	bool match;
++	int ret;
+ 
+ 	sun6i_csi_capture_dimensions(csi_dev, &capture_width, &capture_height);
+ 
+@@ -906,18 +909,21 @@ static int sun6i_csi_capture_link_validate(struct media_link *link)
+ 	if (WARN_ON(!capture_format))
+ 		return -EINVAL;
+ 
+-	sun6i_csi_bridge_dimensions(csi_dev, &bridge_width, &bridge_height);
++	ret = v4l2_subdev_call_state_active(&csi_dev->bridge.subdev, pad,
++					    get_fmt, &fmt);
++	if (ret)
++		return ret;
+ 
+-	sun6i_csi_bridge_format(csi_dev, &mbus_code, &bridge_field);
+-	bridge_format = sun6i_csi_bridge_format_find(mbus_code);
++	bridge_format = sun6i_csi_bridge_format_find(fmt.format.code);
+ 	if (WARN_ON(!bridge_format))
+ 		return -EINVAL;
+ 
+ 	/* No cropping/scaling is supported. */
+-	if (capture_width != bridge_width || capture_height != bridge_height) {
++	if (capture_width != fmt.format.width ||
++	    capture_height != fmt.format.height) {
+ 		v4l2_err(v4l2_dev,
+ 			 "invalid input/output dimensions: %ux%u/%ux%u\n",
+-			 bridge_width, bridge_height, capture_width,
++			 fmt.format.width, fmt.format.height, capture_width,
+ 			 capture_height);
+ 		return -EINVAL;
+ 	}
+@@ -949,7 +955,8 @@ static int sun6i_csi_capture_link_validate(struct media_link *link)
+ 	/* With raw input mode, we need a 1:1 match between input and output. */
+ 	if (bridge_format->input_format == SUN6I_CSI_INPUT_FMT_RAW ||
+ 	    capture_format->input_format_raw) {
+-		match = sun6i_csi_capture_format_match(pixelformat, mbus_code);
++		match = sun6i_csi_capture_format_match(pixelformat,
++						       fmt.format.code);
+ 		if (!match)
+ 			goto invalid;
+ 	}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
new file mode 100644
index 000000000000..555365c6a257
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
@@ -0,0 +1,65 @@
+From 36669e80724c3b087bbc5ebaa75c3d3d31c7fc8b Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Wed, 4 Jan 2023 21:18:51 +0000
+Subject: media: sun6i-csi: implement vidioc_enum_framesizes
+
+Create sun6i_csi_capture_enum_framesizes which defines the min
+and max frame sizes.
+
+As per the specification of vidioc_enum_framesizes, if the supplied
+index is >0 or no valid formats are found for the supplied format,
+return -EINVAL.
+
+Set the type to V4L2_FRMSIZE_TYPE_CONTINUOUS and set the min and max
+width and height from the approriate macros, 32x32 - 4800x4800.
+
+Signed-off-by: Adam Pigg <adam@piggz.co.uk>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index 371fe49753a4..d65151216efa 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -795,6 +795,29 @@ static int sun6i_csi_capture_try_fmt(struct file *file, void *private,
+ 	return 0;
+ }
+ 
++static int sun6i_csi_capture_enum_framesizes(struct file *file, void *fh,
++					  struct v4l2_frmsizeenum *fsize)
++{
++	const struct sun6i_csi_capture_format *format;
++
++	if (fsize->index > 0)
++		return -EINVAL;
++
++	format = sun6i_csi_capture_format_find(fsize->pixel_format);
++	if (!format)
++		return -EINVAL;
++
++	fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
++	fsize->stepwise.min_width = SUN6I_CSI_CAPTURE_WIDTH_MIN;
++	fsize->stepwise.max_width = SUN6I_CSI_CAPTURE_WIDTH_MAX;
++	fsize->stepwise.min_height = SUN6I_CSI_CAPTURE_HEIGHT_MIN;
++	fsize->stepwise.max_height = SUN6I_CSI_CAPTURE_HEIGHT_MAX;
++	fsize->stepwise.step_width = 1;
++	fsize->stepwise.step_height = 1;
++
++	return 0;
++}
++
+ static int sun6i_csi_capture_enum_input(struct file *file, void *private,
+ 					struct v4l2_input *input)
+ {
+@@ -831,6 +854,7 @@ static const struct v4l2_ioctl_ops sun6i_csi_capture_ioctl_ops = {
+ 	.vidioc_g_fmt_vid_cap		= sun6i_csi_capture_g_fmt,
+ 	.vidioc_s_fmt_vid_cap		= sun6i_csi_capture_s_fmt,
+ 	.vidioc_try_fmt_vid_cap		= sun6i_csi_capture_try_fmt,
++	.vidioc_enum_framesizes		= sun6i_csi_capture_enum_framesizes,
+ 
+ 	.vidioc_enum_input		= sun6i_csi_capture_enum_input,
+ 	.vidioc_g_input			= sun6i_csi_capture_g_input,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
new file mode 100644
index 000000000000..a01d11251f65
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
@@ -0,0 +1,431 @@
+From fe96cf63f91da9c7e2b1828c9c012d5a92e2c62b Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Tue, 3 Jan 2023 18:20:21 +0000
+Subject: media: sun6i-csi: merge sun6i_csi_formats and sun6i_csi_formats_match
+
+Information about media bus formats and pixel formats supported by the
+driver is split between the sun6i_csi_capture_formats and
+sun6i_csi_capture_format_matches arrays. This makes it difficult to map
+media bus formats to pixel formats when enumerating the supported pixel
+formats by walking the sun6i_csi_capture_formats array. To prepare for
+support of media bus format support in sun6i_csi_capture_enum_fmt(),
+merge the two arrays toegether.
+
+To do this, sun6i_csi_capture_formats gains a const u32* to store the
+mbus_codes previously from sun6i_csi_capture_format_matches and
+sun6i_csi_capture_format_match is updated to iterate through this to
+find the mbus code while iterating sun6i_csi_capture_formats.
+
+In addition to merging the arrys, to produce semi-planar or multi-planar
+YUV formats, related mbus codes have been added to the *NV* and related
+pixel formats.
+
+Signed-off-by: Adam Pigg <adam@piggz.co.uk>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 211 +++++++++---------
+ .../sunxi/sun6i-csi/sun6i_csi_capture.h       |   6 +-
+ 2 files changed, 102 insertions(+), 115 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index b26dc8bf55b0..510f4597a18e 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -22,6 +22,8 @@
+ 
+ /* Helpers */
+ 
++#define SUN6I_BUS_FMTS(fmt...) (const u32[]) {fmt, 0}
++
+ void sun6i_csi_capture_dimensions(struct sun6i_csi_device *csi_dev,
+ 				  unsigned int *width, unsigned int *height)
+ {
+@@ -49,72 +51,86 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.pixelformat		= V4L2_PIX_FMT_SBGGR8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SBGGR8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGBRG8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGBRG8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGRBG8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGRBG8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SRGGB8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SRGGB8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SBGGR10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SBGGR10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGBRG10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGBRG10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGRBG10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGRBG10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SRGGB10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SRGGB10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SBGGR12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SBGGR12_1X12),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGBRG12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGBRG12_1X12),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGRBG12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGRBG12_1X12),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SRGGB12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SRGGB12_1X12),
+ 	},
+ 	/* RGB */
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_RGB565,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RGB565,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RGB565,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_RGB565_2X8_LE),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_RGB565X,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RGB565,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RGB565,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_RGB565_2X8_BE),
+ 	},
+ 	/* YUV422 */
+ 	{
+@@ -123,6 +139,8 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_YUYV8_2X8,
++							 MEDIA_BUS_FMT_YUYV8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YVYU,
+@@ -130,6 +148,8 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_YVYU8_2X8,
++							 MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_UYVY,
+@@ -137,6 +157,8 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++							 MEDIA_BUS_FMT_UYVY8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_VYUY,
+@@ -144,57 +166,124 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_VYUY8_2X8,
++							 MEDIA_BUS_FMT_VYUY8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV16,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422SP,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV61,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422SP,
+ 		.input_yuv_seq_invert	= true,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YUV422P,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422P,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422P,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	/* YUV420 */
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV12_16L16,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420MB,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420MB,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420SP,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV21,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420SP,
+ 		.input_yuv_seq_invert	= true,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YUV420,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420P,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420P,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YVU420,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420P,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420P,
+ 		.input_yuv_seq_invert	= true,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	/* Compressed */
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_JPEG,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_JPEG_1X8),
+ 	},
+ };
+ 
+@@ -210,118 +299,20 @@ struct sun6i_csi_capture_format *sun6i_csi_capture_format_find(u32 pixelformat)
+ 	return NULL;
+ }
+ 
+-/* RAW formats need an exact match between pixel and mbus formats. */
+-static const
+-struct sun6i_csi_capture_format_match sun6i_csi_capture_format_matches[] = {
+-	/* YUV420 */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YUYV,
+-		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YUYV,
+-		.mbus_code	= MEDIA_BUS_FMT_YUYV8_1X16,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YVYU,
+-		.mbus_code	= MEDIA_BUS_FMT_YVYU8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YVYU,
+-		.mbus_code	= MEDIA_BUS_FMT_YVYU8_1X16,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_UYVY,
+-		.mbus_code	= MEDIA_BUS_FMT_UYVY8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_UYVY,
+-		.mbus_code	= MEDIA_BUS_FMT_UYVY8_1X16,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_VYUY,
+-		.mbus_code	= MEDIA_BUS_FMT_VYUY8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_VYUY,
+-		.mbus_code	= MEDIA_BUS_FMT_VYUY8_1X16,
+-	},
+-	/* RGB */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_RGB565,
+-		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_LE,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_RGB565X,
+-		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_BE,
+-	},
+-	/* Bayer */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SBGGR8,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGBRG8,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGRBG8,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SRGGB8,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SBGGR10,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGBRG10,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGRBG10,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SRGGB10,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SBGGR12,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGBRG12,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGRBG12,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SRGGB12,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
+-	},
+-	/* Compressed */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_JPEG,
+-		.mbus_code	= MEDIA_BUS_FMT_JPEG_1X8,
+-	},
+-};
+-
+ static bool sun6i_csi_capture_format_match(u32 pixelformat, u32 mbus_code)
+ {
+-	unsigned int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(sun6i_csi_capture_format_matches); i++) {
+-		const struct sun6i_csi_capture_format_match *match =
+-			&sun6i_csi_capture_format_matches[i];
+-
+-		if (match->pixelformat == pixelformat &&
+-		    match->mbus_code == mbus_code)
+-			return true;
++	unsigned int i, j;
++
++	for (i = 0; i < ARRAY_SIZE(sun6i_csi_capture_formats); i++) {
++		const struct sun6i_csi_capture_format *format =
++			&sun6i_csi_capture_formats[i];
++
++		if (format->pixelformat == pixelformat) {
++			for (j = 0; format->mbus_codes[j]; j++) {
++				if (mbus_code == format->mbus_codes[j])
++					return true;
++			}
++		}
+ 	}
+ 
+ 	return false;
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h
+index 3ee5ccefbd10..0484942834e3 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h
+@@ -27,11 +27,7 @@ struct sun6i_csi_capture_format {
+ 	bool	input_yuv_seq_invert;
+ 	bool	input_format_raw;
+ 	u32	hsize_len_factor;
+-};
+-
+-struct sun6i_csi_capture_format_match {
+-	u32	pixelformat;
+-	u32	mbus_code;
++	const u32 *mbus_codes;
+ };
+ 
+ #undef current
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
new file mode 100644
index 000000000000..1c78a98182a1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
@@ -0,0 +1,346 @@
+From 1db2face1c2b0d9988a391f3574f2a111bb565bd Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 13 Jan 2024 21:24:24 +0100
+Subject: media: sun6i-csi: subdev: Use subdev active state to store active
+ format
+
+The sun6i_csi_bridge structure stores the active format as a struct
+v4l2_mbus_framefmt instance. Now that the V4L2 subdev core supports
+managing the active state, use it to replace the manually-managed
+format. This simplifies the implementation of the subdev operations by
+removing the need for a custom .get_fmt() handler.
+
+The subdev state now needs to be passed manually from the .s_stream()
+operation to internal functions that need to access the format. As a
+result, the sun6i_csi_bridge_format() helper function is now unused and
+can be dropped.
+
+The .init_state() and .set_fmt() operations also need to be updated
+accordingly. As a result, .set_fmt() now correctly propagates the format
+from the sink pad to the source pad.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit b14038f024ad84473ed79f3baecc2da9ca16d9a5)
+---
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.c        | 149 +++++++++---------
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.h        |   2 -
+ 2 files changed, 73 insertions(+), 78 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+index 2303e5d2baee..92290876a8b3 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+@@ -13,17 +13,6 @@
+ #include "sun6i_csi_bridge.h"
+ #include "sun6i_csi_reg.h"
+ 
+-/* Helpers */
+-
+-static void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
+-				    u32 *mbus_code, u32 *field)
+-{
+-	if (mbus_code)
+-		*mbus_code = csi_dev->bridge.mbus_format.code;
+-	if (field)
+-		*field = csi_dev->bridge.mbus_format.field;
+-}
+-
+ /* Format */
+ 
+ static const struct sun6i_csi_bridge_format sun6i_csi_bridge_formats[] = {
+@@ -217,7 +206,8 @@ static void sun6i_csi_bridge_disable(struct sun6i_csi_device *csi_dev)
+ }
+ 
+ static void
+-sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev)
++sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev,
++				    struct v4l2_subdev_state *state)
+ {
+ 	struct device *dev = csi_dev->dev;
+ 	struct regmap *regmap = csi_dev->regmap;
+@@ -225,14 +215,14 @@ sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev)
+ 		&csi_dev->bridge.source_parallel.endpoint;
+ 	unsigned char bus_width = endpoint->bus.parallel.bus_width;
+ 	unsigned int flags = endpoint->bus.parallel.flags;
+-	u32 field;
++	const struct v4l2_mbus_framefmt *sink_format;
+ 	u32 value = SUN6I_CSI_IF_CFG_IF_CSI;
+ 
+-	sun6i_csi_bridge_format(csi_dev, NULL, &field);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
+ 
+-	if (field == V4L2_FIELD_INTERLACED ||
+-	    field == V4L2_FIELD_INTERLACED_TB ||
+-	    field == V4L2_FIELD_INTERLACED_BT)
++	if (sink_format->field == V4L2_FIELD_INTERLACED ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_TB ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_BT)
+ 		value |= SUN6I_CSI_IF_CFG_SRC_TYPE_INTERLACED |
+ 			 SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(1) |
+ 			 SUN6I_CSI_IF_CFG_FIELD_DT_FIELD_VSYNC;
+@@ -308,17 +298,18 @@ sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev)
+ }
+ 
+ static void
+-sun6i_csi_bridge_configure_mipi_csi2(struct sun6i_csi_device *csi_dev)
++sun6i_csi_bridge_configure_mipi_csi2(struct sun6i_csi_device *csi_dev,
++				     struct v4l2_subdev_state *state)
+ {
++	const struct v4l2_mbus_framefmt *sink_format;
+ 	struct regmap *regmap = csi_dev->regmap;
+ 	u32 value = SUN6I_CSI_IF_CFG_IF_MIPI;
+-	u32 field;
+ 
+-	sun6i_csi_bridge_format(csi_dev, NULL, &field);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
+ 
+-	if (field == V4L2_FIELD_INTERLACED ||
+-	    field == V4L2_FIELD_INTERLACED_TB ||
+-	    field == V4L2_FIELD_INTERLACED_BT)
++	if (sink_format->field == V4L2_FIELD_INTERLACED ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_TB ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_BT)
+ 		value |= SUN6I_CSI_IF_CFG_SRC_TYPE_INTERLACED;
+ 	else
+ 		value |= SUN6I_CSI_IF_CFG_SRC_TYPE_PROGRESSIVE;
+@@ -326,19 +317,20 @@ sun6i_csi_bridge_configure_mipi_csi2(struct sun6i_csi_device *csi_dev)
+ 	regmap_write(regmap, SUN6I_CSI_IF_CFG_REG, value);
+ }
+ 
+-static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
++static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev,
++					      struct v4l2_subdev_state *state)
+ {
+ 	struct regmap *regmap = csi_dev->regmap;
+ 	bool capture_streaming = csi_dev->capture.state.streaming;
+ 	const struct sun6i_csi_bridge_format *bridge_format;
+ 	const struct sun6i_csi_capture_format *capture_format;
+-	u32 mbus_code, field, pixelformat;
++	const struct v4l2_mbus_framefmt *sink_format;
++	u32 pixelformat;
+ 	u8 input_format, input_yuv_seq, output_format;
+ 	u32 value = 0;
+ 
+-	sun6i_csi_bridge_format(csi_dev, &mbus_code, &field);
+-
+-	bridge_format = sun6i_csi_bridge_format_find(mbus_code);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
++	bridge_format = sun6i_csi_bridge_format_find(sink_format->code);
+ 	if (WARN_ON(!bridge_format))
+ 		return;
+ 
+@@ -358,9 +350,9 @@ static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
+ 		if (capture_format->input_yuv_seq_invert)
+ 			input_yuv_seq = bridge_format->input_yuv_seq_invert;
+ 
+-		if (field == V4L2_FIELD_INTERLACED ||
+-		    field == V4L2_FIELD_INTERLACED_TB ||
+-		    field == V4L2_FIELD_INTERLACED_BT)
++		if (sink_format->field == V4L2_FIELD_INTERLACED ||
++		    sink_format->field == V4L2_FIELD_INTERLACED_TB ||
++		    sink_format->field == V4L2_FIELD_INTERLACED_BT)
+ 			output_format = capture_format->output_format_field;
+ 		else
+ 			output_format = capture_format->output_format_frame;
+@@ -371,9 +363,9 @@ static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
+ 	value |= SUN6I_CSI_CH_CFG_INPUT_FMT(input_format);
+ 	value |= SUN6I_CSI_CH_CFG_INPUT_YUV_SEQ(input_yuv_seq);
+ 
+-	if (field == V4L2_FIELD_TOP)
++	if (sink_format->field == V4L2_FIELD_TOP)
+ 		value |= SUN6I_CSI_CH_CFG_FIELD_SEL_FIELD0;
+-	else if (field == V4L2_FIELD_BOTTOM)
++	else if (sink_format->field == V4L2_FIELD_BOTTOM)
+ 		value |= SUN6I_CSI_CH_CFG_FIELD_SEL_FIELD1;
+ 	else
+ 		value |= SUN6I_CSI_CH_CFG_FIELD_SEL_EITHER;
+@@ -382,16 +374,17 @@ static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
+ }
+ 
+ static void sun6i_csi_bridge_configure(struct sun6i_csi_device *csi_dev,
+-				       struct sun6i_csi_bridge_source *source)
++				       struct sun6i_csi_bridge_source *source,
++				       struct v4l2_subdev_state *state)
+ {
+ 	struct sun6i_csi_bridge *bridge = &csi_dev->bridge;
+ 
+ 	if (source == &bridge->source_parallel)
+-		sun6i_csi_bridge_configure_parallel(csi_dev);
++		sun6i_csi_bridge_configure_parallel(csi_dev, state);
+ 	else
+-		sun6i_csi_bridge_configure_mipi_csi2(csi_dev);
++		sun6i_csi_bridge_configure_mipi_csi2(csi_dev, state);
+ 
+-	sun6i_csi_bridge_configure_format(csi_dev);
++	sun6i_csi_bridge_configure_format(csi_dev, state);
+ }
+ 
+ /* V4L2 Subdev */
+@@ -406,6 +399,7 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 	struct sun6i_csi_bridge_source *source;
+ 	struct v4l2_subdev *source_subdev;
+ 	struct media_pad *remote_pad;
++	struct v4l2_subdev_state *state;
+ 	int ret;
+ 
+ 	/* Source */
+@@ -441,8 +435,9 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 	sun6i_csi_bridge_irq_clear(csi_dev);
+ 
+ 	/* Configure */
+-
+-	sun6i_csi_bridge_configure(csi_dev, source);
++	state = v4l2_subdev_lock_and_get_active_state(subdev);
++	sun6i_csi_bridge_configure(csi_dev, source, state);
++	v4l2_subdev_unlock_state(state);
+ 
+ 	if (capture_streaming)
+ 		sun6i_csi_capture_configure(csi_dev);
+@@ -495,13 +490,9 @@ sun6i_csi_bridge_mbus_format_prepare(struct v4l2_mbus_framefmt *mbus_format)
+ static int sun6i_csi_bridge_init_state(struct v4l2_subdev *subdev,
+ 				       struct v4l2_subdev_state *state)
+ {
+-	struct sun6i_csi_device *csi_dev = v4l2_get_subdevdata(subdev);
+ 	unsigned int pad = SUN6I_CSI_BRIDGE_PAD_SINK;
+ 	struct v4l2_mbus_framefmt *mbus_format =
+ 		v4l2_subdev_state_get_format(state, pad);
+-	struct mutex *lock = &csi_dev->bridge.lock;
+-
+-	mutex_lock(lock);
+ 
+ 	mbus_format->code = sun6i_csi_bridge_formats[0].mbus_code;
+ 	mbus_format->width = 1280;
+@@ -509,8 +500,6 @@ static int sun6i_csi_bridge_init_state(struct v4l2_subdev *subdev,
+ 
+ 	sun6i_csi_bridge_mbus_format_prepare(mbus_format);
+ 
+-	mutex_unlock(lock);
+-
+ 	return 0;
+ }
+ 
+@@ -527,53 +516,60 @@ sun6i_csi_bridge_enum_mbus_code(struct v4l2_subdev *subdev,
+ 	return 0;
+ }
+ 
+-static int sun6i_csi_bridge_get_fmt(struct v4l2_subdev *subdev,
+-				    struct v4l2_subdev_state *state,
+-				    struct v4l2_subdev_format *format)
+-{
+-	struct sun6i_csi_device *csi_dev = v4l2_get_subdevdata(subdev);
+-	struct v4l2_mbus_framefmt *mbus_format = &format->format;
+-	struct mutex *lock = &csi_dev->bridge.lock;
+-
+-	mutex_lock(lock);
+-
+-	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
+-		*mbus_format = *v4l2_subdev_state_get_format(state,
+-							     format->pad);
+-	else
+-		*mbus_format = csi_dev->bridge.mbus_format;
+-
+-	mutex_unlock(lock);
+-
+-	return 0;
+-}
+-
+ static int sun6i_csi_bridge_set_fmt(struct v4l2_subdev *subdev,
+ 				    struct v4l2_subdev_state *state,
+ 				    struct v4l2_subdev_format *format)
+ {
+-	struct sun6i_csi_device *csi_dev = v4l2_get_subdevdata(subdev);
+-	struct v4l2_mbus_framefmt *mbus_format = &format->format;
+-	struct mutex *lock = &csi_dev->bridge.lock;
++	struct v4l2_mbus_framefmt *sink_format;
++	struct v4l2_mbus_framefmt *src_format;
+ 
+-	mutex_lock(lock);
++	/*
++	 * As the source format can't change independently of the sink format,
++	 * a set operation on the source is a get.
++	 */
++	if (format->pad == SUN6I_CSI_BRIDGE_PAD_SOURCE)
++		return v4l2_subdev_get_fmt(subdev, state, format);
+ 
+-	sun6i_csi_bridge_mbus_format_prepare(mbus_format);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
+ 
++	/*
+ 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
+ 		*v4l2_subdev_state_get_format(state, format->pad) =
+ 			*mbus_format;
++	*/
++
++	if (!sun6i_csi_bridge_format_find(format->format.code))
++		sink_format->code = sun6i_csi_bridge_formats[0].mbus_code;
+ 	else
+-		csi_dev->bridge.mbus_format = *mbus_format;
++		sink_format->code = format->format.code;
++
++	sink_format->width = format->format.width;
++	sink_format->height = format->format.height;
++
++	/* Accept any colorspace as the CSI bridge isn't colorspace-aware. */
++	sink_format->colorspace = format->format.colorspace;
++	sink_format->xfer_func = format->format.xfer_func;
++	sink_format->ycbcr_enc = format->format.ycbcr_enc;
++	sink_format->quantization = format->format.quantization;
++
++	sink_format->field = V4L2_FIELD_NONE;
+ 
+-	mutex_unlock(lock);
++	format->format = *sink_format;
++
++	/*
++	 * Propagate the format to the source pad. The CSI bridge can't
++	 * transcode, the format on the source pad always matches the sink pad
++	 * exactly.
++	 */
++	src_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SOURCE);
++	*src_format = *sink_format;
+ 
+ 	return 0;
+ }
+ 
+ static const struct v4l2_subdev_pad_ops sun6i_csi_bridge_pad_ops = {
+ 	.enum_mbus_code	= sun6i_csi_bridge_enum_mbus_code,
+-	.get_fmt	= sun6i_csi_bridge_get_fmt,
++	.get_fmt	= v4l2_subdev_get_fmt,
+ 	.set_fmt	= sun6i_csi_bridge_set_fmt,
+ };
+ 
+@@ -771,8 +767,6 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 	};
+ 	int ret;
+ 
+-	mutex_init(&bridge->lock);
+-
+ 	/* V4L2 Subdev */
+ 
+ 	v4l2_subdev_init(subdev, &sun6i_csi_bridge_subdev_ops);
+@@ -801,6 +795,9 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 		return ret;
+ 
+ 	/* V4L2 Subdev */
++	ret = v4l2_subdev_init_finalize(subdev);
++	if (ret)
++		goto error_media_entity;
+ 
+ 	if (csi_dev->isp_available)
+ 		ret = v4l2_async_register_subdev(subdev);
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+index 722b633b7893..a5b0a6f064dd 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+@@ -42,8 +42,6 @@ struct sun6i_csi_bridge {
+ 	struct v4l2_subdev		subdev;
+ 	struct v4l2_async_notifier	notifier;
+ 	struct media_pad		pads[2];
+-	struct v4l2_mbus_framefmt	mbus_format;
+-	struct mutex			lock; /* Mbus format lock. */
+ 
+ 	struct sun6i_csi_bridge_source	source_parallel;
+ 	struct sun6i_csi_bridge_source	source_mipi_csi2;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
new file mode 100644
index 000000000000..d61d506f7110
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
@@ -0,0 +1,102 @@
+From 5848aa0221770f980d4e7ea5db0eaf9213d7abe7 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 01:01:58 -0600
+Subject: mfd: axp20x: Add battery IRQ resources
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/mfd/axp20x.c | 36 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index d35b5cc6b8fe..99d1723bc9c9 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -291,6 +291,15 @@ static const struct resource axp20x_ac_power_supply_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
+ };
+ 
++static const struct resource axp20x_battery_resources[] = {
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_PLUGIN, "BATT_PLUGIN"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_REMOVAL, "BATT_REMOVAL"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_ENT_ACT_MODE, "BATT_HEALTH_DEAD"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_EXIT_ACT_MODE, "BATT_HEALTH_GOOD"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_CHARG, "BATT_CHARGING"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_CHARG_DONE, "BATT_CHARGING_DONE"),
++};
++
+ static const struct resource axp20x_pek_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
+ 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
+@@ -343,6 +352,23 @@ static const struct resource axp717_pek_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP717_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
+ };
+ 
++static const struct resource axp803_battery_resources[] = {
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_PLUGIN, "BATT_PLUGIN"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_REMOVAL, "BATT_REMOVAL"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ENT_ACT_MODE, "BATT_HEALTH_DEAD"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_EXIT_ACT_MODE, "BATT_HEALTH_GOOD"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_CHARG, "BATT_CHARGING"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_CHARG_DONE, "BATT_CHARGING_DONE"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_HIGH, "BATT_CHG_TEMP_HIGH"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_HIGH_END, "BATT_CHG_TEMP_HIGH_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_LOW, "BATT_CHG_TEMP_LOW"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_LOW_END, "BATT_CHG_TEMP_LOW_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_HIGH, "BATT_ACT_TEMP_HIGH"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_HIGH_END, "BATT_ACT_TEMP_HIGH_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW, "BATT_ACT_TEMP_LOW"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW_END, "BATT_ACT_TEMP_LOW_END"),
++};
++
+ static const struct resource axp803_pek_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
+@@ -937,6 +963,8 @@ static const struct mfd_cell axp20x_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp209-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp20x_battery_resources),
++		.resources	= axp20x_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-ac-power-supply",
+ 		.of_compatible	= "x-powers,axp202-ac-power-supply",
+@@ -971,6 +999,8 @@ static const struct mfd_cell axp221_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp221-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp20x_battery_resources),
++		.resources	= axp20x_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-usb-power-supply",
+ 		.of_compatible	= "x-powers,axp221-usb-power-supply",
+@@ -993,6 +1023,8 @@ static const struct mfd_cell axp223_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp221-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp20x_battery_resources),
++		.resources	= axp20x_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-regulator",
+ 	}, {
+@@ -1102,6 +1134,8 @@ static const struct mfd_cell axp803_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp813-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp803_battery_resources),
++		.resources	= axp803_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-ac-power-supply",
+ 		.of_compatible	= "x-powers,axp813-ac-power-supply",
+@@ -1162,6 +1196,8 @@ static const struct mfd_cell axp813_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp813-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp803_battery_resources),
++		.resources	= axp803_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-ac-power-supply",
+ 		.of_compatible	= "x-powers,axp813-ac-power-supply",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/misc-modem-power-Power-manager-for-modems.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/misc-modem-power-Power-manager-for-modems.patch
new file mode 100644
index 000000000000..8ca62ed7300c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/misc-modem-power-Power-manager-for-modems.patch
@@ -0,0 +1,2050 @@
+From 56956585d67fa8494fb9fee3a1164ee767fbe667 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 12 Nov 2017 02:10:15 +0100
+Subject: misc: modem-power: Power manager for modems
+
+This driver allows for powering/resetting devices that are otherwise
+handled by other subsytems (USB). It also has mechanismsm for polling
+from userspace on device->SoC wakeup events via GPIO.
+
+This is mostly useful for controling modems. The supported modems are:
+
+- Quectel EG25
+- ZTE MG3732
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/misc/Kconfig       |    7 +
+ drivers/misc/Makefile      |    1 +
+ drivers/misc/modem-power.c | 1992 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 2000 insertions(+)
+ create mode 100644 drivers/misc/modem-power.c
+
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index faf983680040..c702600975ef 100644
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -585,6 +585,13 @@ config NSM
+ 	  To compile this driver as a module, choose M here.
+ 	  The module will be called nsm.
+ 
++config MODEM_POWER
++	tristate "Modem power/wakeup support for EG25, MG3732, etc."
++	depends on OF && SERIAL_DEV_BUS && RFKILL
++	help
++	  This driver provides support for powering up and handling
++	  wakeup signals for various modems.
++
+ source "drivers/misc/c2port/Kconfig"
+ source "drivers/misc/eeprom/Kconfig"
+ source "drivers/misc/cb710/Kconfig"
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index 153a3f4837e8..7983f42813d9 100644
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -69,3 +69,4 @@ obj-$(CONFIG_TMR_INJECT)	+= xilinx_tmr_inject.o
+ obj-$(CONFIG_TPS6594_ESM)	+= tps6594-esm.o
+ obj-$(CONFIG_TPS6594_PFSM)	+= tps6594-pfsm.o
+ obj-$(CONFIG_NSM)		+= nsm.o
++obj-$(CONFIG_MODEM_POWER)	+= modem-power.o
+diff --git a/drivers/misc/modem-power.c b/drivers/misc/modem-power.c
+new file mode 100644
+index 000000000000..36729ce00752
+--- /dev/null
++++ b/drivers/misc/modem-power.c
+@@ -0,0 +1,1992 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Modem power control driver.
++ *
++ * Ondrej Jirman <megi@xff.cz>
++ *
++ * How this works
++ * --------------
++ *
++ * The driver:
++ * - can be registered as a platform or serial device
++ * - will use gpios, regulator and (optionally) serial port to control the modem
++ * - exposes a character device to control the modem power and receive various
++ *   events
++ * - exposes sysfs interface to control modem power and wakeup
++ * - supports multiple modem types and instances
++ *
++ * Power up/power down:
++ * - may take a lot of time (eg. ~13-22s powerup, >22s powerdown)
++ * - happens on a private workqueue under a lock
++ * - may happen from shutdown hook
++ * - prevents suspend when powerup/powerdown is in progress
++ * - is serialized and there's no abort of in-progress operations
++ * - for specific power sequence see comments in the section for each
++ *   supported modem variant
++ * - the driver monitors the power status of the modem (optionally)
++ *   and tries to complete the powerdown initiated via AT command
++ * - the driver tries to detect when the modem is killswitched off
++ *   and updates the driver status to reflect that
++ *
++ * Suspend/resume:
++ * - suspend is blocked if powerup/down is in progress
++ * - modem can wakeup the host over gpio based IRQ (RI signal)
++ * - the driver will assert ap_ready after resume finishes
++ *
++ * Rfkill:
++ * - the driver implements a rfkill interface if rfkill gpio is available
++ */
++
++//#define DEBUG
++
++#include <linux/wait.h>
++#include <linux/interrupt.h>
++#include <linux/device.h>
++#include <linux/cdev.h>
++#include <linux/kfifo.h>
++#include <linux/module.h>
++#include <linux/poll.h>
++#include <linux/spinlock.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/serdev.h>
++#include <linux/rfkill.h>
++
++#define DRIVER_NAME "modem-power"
++
++enum {
++	MPWR_REQ_NONE = 0,
++	MPWR_REQ_RESET,
++	MPWR_REQ_PWDN,
++	MPWR_REQ_PWUP,
++};
++
++enum {
++	MPWR_MODE_NORMAL = 1,
++	MPWR_MODE_DUMB,
++	MPWR_MODE_FASTBOOT,
++	MPWR_MODE_ALT1,
++	MPWR_MODE_ALT2,
++};
++
++struct mpwr_dev;
++
++struct mpwr_gpio {
++	const char* name;
++	unsigned desc_off;
++	int flags;
++	bool required;
++	int irq_flags;
++	unsigned irq_off;
++};
++
++#define MPWR_GPIO_DEF(_name, _flags, _req) \
++	{ .name = #_name, \
++	  .desc_off = offsetof(struct mpwr_dev, _name##_gpio), \
++	  .flags = _flags, \
++	  .required = _req, \
++	}
++
++#define MPWR_GPIO_DEF_IRQ(_name, _flags, _req, _irq_flags) \
++	{ .name = #_name, \
++	  .desc_off = offsetof(struct mpwr_dev, _name##_gpio), \
++	  .flags = _flags, \
++	  .required = _req, \
++	  .irq_flags = _irq_flags, \
++	  .irq_off = offsetof(struct mpwr_dev, _name##_irq), \
++	}
++
++struct mpwr_variant {
++	int (*power_init)(struct mpwr_dev* mpwr);
++	int (*power_up)(struct mpwr_dev* mpwr);
++	int (*power_down)(struct mpwr_dev* mpwr);
++	int (*reset)(struct mpwr_dev* mpwr);
++	void (*recv_msg)(struct mpwr_dev *mpwr, const char *msg);
++	int (*suspend)(struct mpwr_dev *mpwr);
++	int (*resume)(struct mpwr_dev *mpwr);
++	const struct mpwr_gpio* gpios;
++	bool regulator_required;
++	bool monitor_wakeup;
++};
++
++struct mpwr_dev {
++	struct device *dev;
++	const struct mpwr_variant* variant;
++
++	wait_queue_head_t wait;
++
++	/* serdev */
++	struct serdev_device *serdev;
++	char rcvbuf[4096];
++	size_t rcvbuf_fill;
++	char msg[4096];
++        int msg_len;
++        int msg_ok;
++	//struct kfifo kfifo;
++	DECLARE_KFIFO(kfifo, unsigned char, 4096);
++
++	/* power */
++	struct regulator *regulator;
++	struct regulator *regulator_vbus;
++
++	/* outputs */
++	struct gpio_desc *enable_gpio;
++	struct gpio_desc *reset_gpio;
++	struct gpio_desc *pwrkey_gpio;
++	struct gpio_desc *sleep_gpio;
++	struct gpio_desc *dtr_gpio;
++	struct gpio_desc *host_ready_gpio;
++	struct gpio_desc *cts_gpio;
++	struct gpio_desc *rts_gpio;
++
++	/* inputs */
++	struct gpio_desc *status_gpio;
++	struct gpio_desc *wakeup_gpio;
++	int wakeup_irq;
++	bool status_pwrkey_multiplexed;
++
++	/* config */
++	struct cdev cdev;
++	dev_t major;
++
++	/* rfkill */
++	struct rfkill *rfkill;
++
++	/* powerup/dn work queue */
++	struct workqueue_struct *wq;
++	struct work_struct power_work;
++	struct work_struct finish_pdn_work;
++        struct mutex modem_lock;
++
++	// change
++	spinlock_t lock; /* protects last_request */
++	int last_request;
++	int powerup_mode;
++	ktime_t last_wakeup;
++
++	struct timer_list wd_timer;
++        struct delayed_work host_ready_work;
++
++	unsigned long flags[1];
++};
++
++enum {
++	/* modem is powered */
++	MPWR_F_POWERED,
++	MPWR_F_POWER_CHANGE_INPROGRESS,
++	MPWR_F_KILLSWITCHED,
++	/* we got a wakeup from the modem */
++	MPWR_F_GOT_WAKEUP,
++        /* serdev */
++        MPWR_F_RECEIVING_MSG,
++        /* eg25 */
++        MPWR_F_GOT_PDN,
++	/* config options */
++        MPWR_F_BLOCKED,
++	/* file */
++	MPWR_F_OPEN,
++	MPWR_F_OVERFLOW,
++};
++
++static struct class* mpwr_class;
++
++static int mpwr_serdev_at_cmd(struct mpwr_dev *mpwr, const char *msg, int timeout_ms);
++static int mpwr_serdev_at_cmd_with_retry(struct mpwr_dev *mpwr, const char *msg,
++					 int timeout_ms, int tries);
++static int mpwr_serdev_at_cmd_with_retry_ignore_timeout(struct mpwr_dev *mpwr, const char *msg,
++							int timeout_ms, int tries);
++
++// {{{ mg2723 variant
++
++static int mpwr_mg2723_power_init(struct mpwr_dev* mpwr)
++{
++	// if the device has power applied or doesn't have regulator
++	// configured (we assume it's always powered) initialize GPIO
++	// to shut it down initially
++	if (!mpwr->regulator || regulator_is_enabled(mpwr->regulator)) {
++		gpiod_set_value(mpwr->enable_gpio, 0);
++		gpiod_set_value(mpwr->reset_gpio, 1);
++	} else {
++		// device is not powered, don't drive the gpios
++		gpiod_direction_input(mpwr->enable_gpio);
++		gpiod_direction_input(mpwr->reset_gpio);
++	}
++
++	return 0;
++}
++
++static int mpwr_mg2723_power_up(struct mpwr_dev* mpwr)
++{
++	int ret;
++
++	// power up
++	if (mpwr->regulator) {
++		ret = regulator_enable(mpwr->regulator);
++		if (ret < 0) {
++			dev_err(mpwr->dev,
++				"can't enable power supply err=%d", ret);
++			return ret;
++		}
++	}
++
++	gpiod_direction_output(mpwr->enable_gpio, 1);
++	gpiod_direction_output(mpwr->reset_gpio, 1);
++	msleep(300);
++	gpiod_set_value(mpwr->reset_gpio, 0);
++
++	return 0;
++}
++
++static int mpwr_mg2723_power_down(struct mpwr_dev* mpwr)
++{
++	gpiod_set_value(mpwr->enable_gpio, 0);
++	msleep(50);
++
++	if (mpwr->regulator) {
++		regulator_disable(mpwr->regulator);
++
++		gpiod_direction_input(mpwr->enable_gpio);
++		gpiod_direction_input(mpwr->reset_gpio);
++	} else {
++		gpiod_set_value(mpwr->reset_gpio, 1);
++	}
++
++	return 0;
++}
++
++static int mpwr_mg2723_reset(struct mpwr_dev* mpwr)
++{
++	gpiod_set_value(mpwr->reset_gpio, 1);
++	msleep(300);
++	gpiod_set_value(mpwr->reset_gpio, 0);
++
++	return 0;
++}
++
++static const struct mpwr_gpio mpwr_mg2723_gpios[] = {
++	MPWR_GPIO_DEF(enable, GPIOD_IN, true),
++	MPWR_GPIO_DEF(reset, GPIOD_IN, true),
++	MPWR_GPIO_DEF_IRQ(wakeup, GPIOD_IN, true, IRQF_TRIGGER_FALLING),
++	{ },
++};
++
++static const struct mpwr_variant mpwr_mg2723_variant = {
++	.power_init = mpwr_mg2723_power_init,
++	.power_up = mpwr_mg2723_power_up,
++	.power_down = mpwr_mg2723_power_down,
++	.reset = mpwr_mg2723_reset,
++	.gpios = mpwr_mg2723_gpios,
++};
++
++// }}}
++// {{{ eg25 variant
++
++static bool mpwr_eg25_qcfg_airplanecontrol_is_ok(const char* v)
++{
++	return strstarts(v, "1,");
++}
++
++struct mpwr_eg25_qcfg {
++	const char* name;
++	const char* val;
++	bool (*is_ok)(const char* val);
++};
++
++#define EG25G_LATEST_KNOWN_FIRMWARE "EG25GGBR07A08M2G_01.002.07"
++
++static const struct mpwr_eg25_qcfg mpwr_eg25_qcfgs[] = {
++	//{ "risignaltype",       "\"respective\"", },
++	{ "risignaltype",       "\"physical\"", },
++	{ "urc/ri/ring",        "\"pulse\",1,1000,5000,\"off\",1", },
++	{ "urc/ri/smsincoming", "\"pulse\",1,1", },
++	{ "urc/ri/other",       "\"off\",1,1", },
++	{ "urc/ri/pin",         "uart_ri", },
++	{ "urc/delay",          "0", },
++
++	//{ "sleep/datactrl",     "0,300,1", },
++
++	{ "sleepind/level",     "0", },
++	{ "wakeupin/level",     "0", },
++
++	{ "ApRstLevel",		"0", },
++	{ "ModemRstLevel",	"0", },
++
++	// in EG25-G this tries to modify file in /etc (read-only)
++	// and fails
++	//{ "dbgctl",		"0", },
++
++	// we don't need AP_READY
++	{ "apready",            "0,0,500", },
++
++	{ "airplanecontrol",    "1",   mpwr_eg25_qcfg_airplanecontrol_is_ok },
++
++	// available since firmware R07A08_01.002.01.002
++	{ "fast/poweroff",	"1" },
++};
++
++static char* mpwr_serdev_get_response_value(struct mpwr_dev *mpwr,
++					    const char* prefix)
++{
++	int off;
++
++	for (off = 0; off < mpwr->msg_len; off += strlen(mpwr->msg + off) + 1)
++		if (strstarts(mpwr->msg + off, prefix))
++			return mpwr->msg + off + strlen(prefix);
++
++	return NULL;
++}
++
++static struct gpio_desc *mpwr_eg25_get_pwrkey_gpio(struct mpwr_dev *mpwr)
++{
++	if (mpwr->status_pwrkey_multiplexed)
++		return mpwr->status_gpio;
++
++	return mpwr->pwrkey_gpio;
++}
++
++/*
++ * Gpio meanings
++ * -------------
++ *
++ * enable_gpio - 1 = enables RF, 0 = disables RF
++ * sleep_gpio  - 1 = puts modem to sleep, 0 = wakes up the modem (must be 0
++ *               during poweron)
++ * reset_gpio  - accepts 150-460ms reset pulse (high __|^|__)
++ * pwrkey_gpio - accepts 100ms-650ms pulse for powerup (high __|^|__)
++ *                       650ms+ pulse for powerdown
++ *                       (initiated after pulse ends, pulse may have indefinite
++ *                        duration)
++ * status_gpio - modem power status 0 = powered  1 = unpowered
++ * wakeup_gpio - "ring indicator" output from the modem
++ * host_ready_gpio - AP_READY pin - host is ready to receive URCs
++ *
++ * (pwrkey may be multiplexed with status_gpio)
++ *
++ * Modem behavior
++ * --------------
++ *
++ * wakeup_gpio (RI):
++ * - goes high shortly after power is applied (~15ms)
++ * - goes low when RDY is sent
++ *
++ * dtr_gpio
++ * - when high, modem can sleep if requested
++ * - H->L will wake up a sleeping modem
++ * - internal pull-up
++ *
++ * ri
++ * - pulled low when there's URC
++ * - modem wakes up on URC automatically
++ *
++ * - AT+QURCCFG
++ * - AT+QINDCFG="csq",1
++ * - AT+QINDCFG="ring",1
++ * - AT+QINDCFG="smsincoming",1
++ * - AT+CGREG=0
++ * - AT+CREG=0
++ *
++ * - AT+QURCCFG="urcport","uart1"
++ */
++static int mpwr_eg25_power_up(struct mpwr_dev* mpwr)
++{
++	struct gpio_desc *pwrkey_gpio = mpwr_eg25_get_pwrkey_gpio(mpwr);
++	bool wakeup_ok, status_ok;
++	bool needs_restart = false;
++	u32 speed = 115200;
++	int ret, i, off;
++	ktime_t start;
++	int mode = mpwr->powerup_mode;
++
++	if (regulator_is_enabled(mpwr->regulator))
++		dev_warn(mpwr->dev,
++			 "regulator was already enabled during powerup");
++
++	/* Enable the modem power. */
++	ret = regulator_enable(mpwr->regulator);
++	if (ret < 0) {
++		dev_err(mpwr->dev,
++			"can't enable power supply err=%d", ret);
++		return ret;
++	}
++
++	ret = regulator_enable(mpwr->regulator_vbus);
++	if (ret < 0) {
++		dev_err(mpwr->dev,
++			"can't enable vbus power supply err=%d", ret);
++		regulator_disable(mpwr->regulator);
++		return ret;
++	}
++
++	/* Drive default gpio signals during powerup */
++	/* host_ready_gpio should be 1 during normal powerup */
++	gpiod_direction_output(mpwr->host_ready_gpio, mode != MPWR_MODE_ALT2);
++	/* #W_DISABLE must be left pulled up during modem power up
++	 * early on, because opensource bootloader uses this signal to enter
++	 * fastboot mode when it's pulled down.
++	 *
++	 * This should be 1 for normal powerup and 0 for fastboot mode with
++	 * special Biktor's firmware.
++	 */
++	gpiod_direction_output(mpwr->enable_gpio, mode != MPWR_MODE_FASTBOOT);
++	gpiod_direction_output(mpwr->sleep_gpio, 0);
++	gpiod_direction_output(mpwr->reset_gpio, 0);
++	gpiod_direction_output(pwrkey_gpio, 0);
++	/* dtr_gpio should be 0 during normal powerup */
++	gpiod_direction_output(mpwr->dtr_gpio, mode == MPWR_MODE_ALT1);
++
++	/* Wait for powerup. (30ms min. according to datasheet) */
++	msleep(50);
++
++	/* Send 200ms pwrkey pulse to initiate poweron */
++	gpiod_set_value(pwrkey_gpio, 1);
++	msleep(200);
++	gpiod_set_value(pwrkey_gpio, 0);
++
++	/* skip modem killswitch status checks in fastboot bootloader entry mode */
++	if (mode != MPWR_MODE_NORMAL)
++		goto open_serdev;
++
++	/* Switch status key to input, in case it's multiplexed with pwrkey. */
++	gpiod_direction_input(mpwr->status_gpio);
++
++	/*
++	 * Wait for status/wakeup change, assume good values, if CTS/status
++	 * signals, are not configured.
++	 */
++	status_ok = mpwr->status_gpio ? false : true;
++	wakeup_ok = mpwr->wakeup_gpio ? false : true;
++
++	/* wait up to 10s for status */
++	start = ktime_get();
++	while (ktime_ms_delta(ktime_get(), start) < 10000) {
++		if (!wakeup_ok && mpwr->wakeup_gpio && gpiod_get_value(mpwr->wakeup_gpio)) {
++			dev_info(mpwr->dev, "wakeup ok\n");
++			wakeup_ok = true;
++		}
++
++		if (!status_ok && mpwr->status_gpio && !gpiod_get_value(mpwr->status_gpio)) {
++			dev_info(mpwr->dev, "status ok\n");
++			status_ok = true;
++		}
++
++		/* modem is ready */
++		if (wakeup_ok && status_ok)
++			break;
++
++		msleep(50);
++	}
++
++	if (!wakeup_ok) {
++		dev_err(mpwr->dev, "The modem looks kill-switched\n");
++		if (!test_and_set_bit(MPWR_F_KILLSWITCHED, mpwr->flags))
++			sysfs_notify(&mpwr->dev->kobj, NULL, "killswitched");
++		goto err_shutdown_noclose;
++	}
++
++	if (!status_ok) {
++		dev_err(mpwr->dev, "The modem didn't report powerup success in time\n");
++		goto err_shutdown_noclose;
++	}
++
++	if (test_and_clear_bit(MPWR_F_KILLSWITCHED, mpwr->flags))
++		sysfs_notify(&mpwr->dev->kobj, NULL, "killswitched");
++
++open_serdev:
++	/* open serial console */
++	ret = serdev_device_open(mpwr->serdev);
++	if (ret) {
++		dev_err(mpwr->dev, "error opening serdev (%d)\n", ret);
++		goto err_shutdown_noclose;
++	}
++
++	of_property_read_u32(mpwr->dev->of_node, "current-speed", &speed);
++	serdev_device_set_baudrate(mpwr->serdev, speed);
++	serdev_device_set_flow_control(mpwr->serdev, false);
++	ret = serdev_device_set_parity(mpwr->serdev, SERDEV_PARITY_NONE);
++	if (ret) {
++		dev_err(mpwr->dev, "error setting serdev parity (%d)\n", ret);
++		goto err_shutdown;
++	}
++
++	if (mode != MPWR_MODE_NORMAL)
++		goto powered_up;
++
++	ret = mpwr_serdev_at_cmd_with_retry_ignore_timeout(mpwr, "AT&FE0", 1000, 30);
++	if (ret)
++		goto err_shutdown;
++
++	/* print firmware version */
++        ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QVERSION;+QSUBSYSVER", 1000, 15);
++        if (ret == 0 && mpwr->msg_len > 0) {
++		bool outdated = false;
++
++		dev_info(mpwr->dev, "===================================================\n");
++		for (off = 0; off < mpwr->msg_len; off += strlen(mpwr->msg + off) + 1) {
++			if (strstr(mpwr->msg + off, "Project Rev") && !strstr(mpwr->msg + off, EG25G_LATEST_KNOWN_FIRMWARE))
++				outdated = true;
++
++			dev_info(mpwr->dev, "%s\n", mpwr->msg + off);
++		}
++		dev_info(mpwr->dev, "===================================================\n");
++
++		if (outdated)
++			dev_warn(mpwr->dev, "Your modem has an outdated firmware. Latest know version is %s. Consider updating.\n", EG25G_LATEST_KNOWN_FIRMWARE);
++	}
++
++	/* print ADB key to dmesg */
++        ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QADBKEY?", 1000, 15);
++        if (ret == 0) {
++		const char *val = mpwr_serdev_get_response_value(mpwr, "+QADBKEY: ");
++		if (val)
++			dev_info(mpwr->dev, "ADB KEY is '%s' (you can use it to unlock ADB access to the modem, see https://xnux.eu/devices/feature/modem-pp.html)\n", val);
++	}
++
++        // check DAI config
++        ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QDAI?", 1000, 15);
++        if (ret == 0) {
++		const char *val = mpwr_serdev_get_response_value(mpwr, "+QDAI: ");
++		const char *needed_val = NULL;
++		char buf[128];
++
++		if (val) {
++			of_property_read_string(mpwr->dev->of_node, "quectel,qdai", &needed_val);
++
++			if (needed_val && strcmp(needed_val, val)) {
++				dev_warn(mpwr->dev, "QDAI is '%s' (changing to '%s')\n", val, needed_val);
++
++				/* update qdai */
++				snprintf(buf, sizeof buf, "AT+QDAI=%s", needed_val);
++				ret = mpwr_serdev_at_cmd(mpwr, buf, 5000);
++				if (ret == 0)
++					needs_restart = true;
++			} else {
++				dev_info(mpwr->dev, "QDAI is '%s'\n", val);
++			}
++		}
++	}
++
++	/* reset the modem, to apply QDAI config if necessary */
++	if (needs_restart) {
++		dev_info(mpwr->dev, "Restarting modem\n");
++
++		/* reboot is broken with fastboot enabled */
++		mpwr_serdev_at_cmd(mpwr, "AT+QCFG=\"fast/poweroff\",0", 5000);
++
++		ret = mpwr_serdev_at_cmd(mpwr, "AT+CFUN=1,1", 5000);
++		if (ret)
++			goto err_shutdown;
++
++		/* wait a bit before starting to probe the modem again */
++		msleep(6000);
++
++		ret = mpwr_serdev_at_cmd_with_retry_ignore_timeout(mpwr, "AT&FE0", 1000, 30);
++		if (ret)
++			goto err_shutdown;
++
++		// wait until QDAI starts succeeding (then the modem is ready
++		// to accept the following QCFGs)
++		ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QDAI?", 1000, 15);
++		if (ret)
++			goto err_shutdown;
++	}
++
++        /* check and update important QCFGs */
++        for (i = 0; i < ARRAY_SIZE(mpwr_eg25_qcfgs); i++) {
++                const char* name = mpwr_eg25_qcfgs[i].name;
++                const char* needed_val = mpwr_eg25_qcfgs[i].val;
++		bool (*is_ok)(const char* val) = mpwr_eg25_qcfgs[i].is_ok;
++		const char *val;
++                char buf[128];
++
++                snprintf(buf, sizeof buf, "AT+QCFG=\"%s\"", name);
++                ret = mpwr_serdev_at_cmd(mpwr, buf, 1000);
++                if (ret)
++			continue;
++
++                snprintf(buf, sizeof buf, "+QCFG: \"%s\",", name);
++		val = mpwr_serdev_get_response_value(mpwr, buf);
++		if (val) {
++			if (needed_val && (is_ok ? !is_ok(val) : strcmp(needed_val, val))) {
++				dev_info(mpwr->dev, "QCFG '%s' is '%s' (changing to '%s')\n", name, val, needed_val);
++
++				/* update qcfg */
++				snprintf(buf, sizeof buf, "AT+QCFG=\"%s\",%s", name, needed_val);
++				ret = mpwr_serdev_at_cmd(mpwr, buf, 1000);
++				if (ret)
++					break; /* go to next QCFG */
++			} else {
++				dev_info(mpwr->dev, "QCFG '%s' is '%s'\n", name, val);
++			}
++		}
++        }
++
++	/* setup URC port */
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QURCCFG=\"urcport\",\"all\"", 2000);
++        if (ret) {
++		dev_info(mpwr->dev, "Your modem doesn't support AT+QURCCFG=\"urcport\",\"all\", consider upgrading the firmware.\n");
++
++		ret = mpwr_serdev_at_cmd(mpwr, "AT+QURCCFG=\"urcport\",\"usbat\"", 2000);
++		if (ret)
++			dev_err(mpwr->dev, "Modem may not report URCs to the right port!\n");
++	}
++
++	/* enable the modem to go to sleep when DTR is low */
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QSCLK=1", 2000);
++        if (ret)
++		dev_err(mpwr->dev, "Modem will probably not sleep!\n");
++
++powered_up:
++	// if we're signaling some alternate boot mode via GPIO, we need to
++	// sleep here so that modem's boot script notices the gpio
++	if (mode == MPWR_MODE_ALT1 || mode == MPWR_MODE_FASTBOOT || mode == MPWR_MODE_ALT2)
++		msleep(12000);
++
++	gpiod_direction_output(mpwr->dtr_gpio, 1);
++
++	return 0;
++
++err_shutdown:
++	serdev_device_close(mpwr->serdev);
++err_shutdown_noclose:
++	dev_warn(mpwr->dev,
++		 "Forcibly cutting off power, data loss may occur.\n");
++	gpiod_direction_input(mpwr->enable_gpio);
++	gpiod_direction_input(mpwr->reset_gpio);
++	gpiod_direction_input(mpwr->sleep_gpio);
++	gpiod_direction_input(pwrkey_gpio);
++	gpiod_direction_input(mpwr->host_ready_gpio);
++	gpiod_direction_input(mpwr->dtr_gpio);
++
++	regulator_disable(mpwr->regulator_vbus);
++	regulator_disable(mpwr->regulator);
++	return -ENODEV;
++}
++
++static int mpwr_eg25_power_down_finish(struct mpwr_dev* mpwr)
++{
++	struct gpio_desc *pwrkey_gpio = mpwr_eg25_get_pwrkey_gpio(mpwr);
++	ktime_t start = ktime_get();
++	int ret;
++
++	serdev_device_close(mpwr->serdev);
++
++	/*
++	 * This function is called right after POWERED DOWN message is received.
++	 *
++	 * In case of fast/poweroff == 1, no POWERED DOWN message is sent.
++	 * Fast power off times are around 1s since the end of 800ms
++	 * POK pulse.
++	 *
++	 * When the modem powers down RI (wakeup) goes low and STATUS goes
++	 * high at the same time. Status is not connected on some boards.
++	 * RI should be inactive during poweroff, but we don't know for sure.
++	 *
++	 * Therfore:
++	 * - wait for STATUS going low
++	 * - in case that's not available wait for RI going low
++	 * - in case timings seem off, warn the user
++	 *
++	 * In addition, some boards have PWRKEY multiplexed with STATUS signal.
++	 * In that case we need to switch STATUS to output high level, as soon
++	 * as it goes low in order to prevent a power-up signal being registered
++	 * by the modem.
++	 */
++
++	if (mpwr->status_gpio) {
++		/* wait up to 30s for status going high */
++		while (ktime_ms_delta(ktime_get(), start) < 30000) {
++			if (gpiod_get_value(mpwr->status_gpio)) {
++				if (ktime_ms_delta(ktime_get(), start) < 500)
++					dev_warn(mpwr->dev,
++						 "STATUS signal is high too soon during powerdown. Modem is already off?\n");
++				goto powerdown;
++			}
++
++			msleep(20);
++		}
++
++		dev_warn(mpwr->dev,
++			 "STATUS signal didn't go high during shutdown. Modem is still on?\n");
++		goto force_powerdown;
++	} else {
++		clear_bit(MPWR_F_GOT_WAKEUP, mpwr->flags);
++
++		if (!gpiod_get_value(mpwr->wakeup_gpio)) {
++			dev_warn(mpwr->dev,
++				 "RI signal is low too soon during powerdown. Modem is already off, or spurious wakeup?\n");
++			msleep(2000);
++			goto powerdown;
++		}
++
++		ret = wait_event_timeout(mpwr->wait,
++					 test_bit(MPWR_F_GOT_WAKEUP, mpwr->flags),
++					 msecs_to_jiffies(30000));
++		if (ret <= 0) {
++			dev_warn(mpwr->dev,
++				 "RI signal didn't go low during shutdown, is modem really powering down?\n");
++			goto force_powerdown;
++		}
++
++		if (ktime_ms_delta(ktime_get(), start) < 500) {
++			dev_warn(mpwr->dev,
++				 "RI signal is low too soon during powerdown. Modem is already off, or spurious wakeup?\n");
++			msleep(2000);
++			goto powerdown;
++		}
++	}
++
++powerdown:
++	gpiod_direction_input(mpwr->enable_gpio);
++	gpiod_direction_input(mpwr->reset_gpio);
++	gpiod_direction_input(mpwr->sleep_gpio);
++	gpiod_direction_input(pwrkey_gpio);
++	gpiod_direction_input(mpwr->host_ready_gpio);
++	gpiod_direction_input(mpwr->dtr_gpio);
++
++	regulator_disable(mpwr->regulator_vbus);
++	regulator_disable(mpwr->regulator);
++
++	return 0;
++
++force_powerdown:
++	dev_warn(mpwr->dev,
++		 "Forcibly cutting off power, data loss may occur.\n");
++	goto powerdown;
++}
++
++static int mpwr_eg25_power_down(struct mpwr_dev* mpwr)
++{
++	struct gpio_desc *pwrkey_gpio = mpwr_eg25_get_pwrkey_gpio(mpwr);
++	//int ret;
++
++	/* Send 800ms pwrkey pulse to initiate powerdown. */
++	gpiod_direction_output(pwrkey_gpio, 1);
++	msleep(800);
++	gpiod_set_value(pwrkey_gpio, 0);
++
++	/* Switch status key to input, in case it's multiplexed with pwrkey. */
++	gpiod_direction_input(mpwr->status_gpio);
++
++	msleep(20);
++
++#if 0
++	// wait for POWERED DOWN message
++	clear_bit(MPWR_F_GOT_PDN, mpwr->flags);
++	ret = wait_event_timeout(mpwr->wait,
++				 test_bit(MPWR_F_GOT_PDN, mpwr->flags),
++				 msecs_to_jiffies(7000));
++	if (ret <= 0)
++		dev_warn(mpwr->dev,
++			 "POWERED DOWN message not received, is modem really powering down?\n");
++#endif
++
++	return mpwr_eg25_power_down_finish(mpwr);
++}
++
++static void mpwr_finish_pdn_work(struct work_struct *work)
++{
++	/*
++	struct mpwr_dev *mpwr = container_of(work, struct mpwr_dev, power_work);
++	unsigned long flags;
++
++	spin_lock_irqsave(&mpwr->lock, flags);
++	spin_unlock_irqrestore(&mpwr->lock, flags);
++
++	pm_stay_awake(mpwr->dev);
++
++	mutex_lock(&mpwr->modem_lock);
++
++	mutex_unlock(&mpwr->modem_lock);
++
++	pm_relax(mpwr->dev);
++	*/
++}
++
++static void mpwr_eg25_receive_msg(struct mpwr_dev *mpwr, const char *msg)
++{
++	unsigned int msg_len;
++
++	if (!strcmp(msg, "POWERED DOWN")) {
++		// system is powering down
++                set_bit(MPWR_F_GOT_PDN, mpwr->flags);
++		wake_up(&mpwr->wait);
++
++		/*
++		if (mutex_trylock(&mpwr->modem_lock)) {
++			// if no power op is in progress, this means userspace
++			// tried to shut the modem down via AT command, finish up
++			// the job
++
++			pm_stay_awake(mpwr->dev);
++
++			queue_work(mpwr->wq, &mpwr->power_work);
++			dev_warn(mpwr->dev, "userspace shut down the modem via AT command, finishing the job\n");
++			mpwr_eg25_power_down_finish(mpwr);
++			mutex_unlock(&mpwr->modem_lock);
++
++			pm_relax(mpwr->dev);
++		}
++                  */
++                return;
++	}
++
++	if (!strcmp(msg, "RDY")) {
++		// system is ready after powerup
++                return;
++	}
++
++	if (!test_bit(MPWR_F_OPEN, mpwr->flags))
++		return;
++
++	msg_len = strlen(msg);
++
++	if (msg_len + 1 > kfifo_avail(&mpwr->kfifo)) {
++		if (!test_and_set_bit(MPWR_F_OVERFLOW, mpwr->flags))
++			wake_up(&mpwr->wait);
++		return;
++	}
++
++	kfifo_in(&mpwr->kfifo, msg, msg_len);
++	kfifo_in(&mpwr->kfifo, "\n", 1);
++	wake_up(&mpwr->wait);
++}
++
++static void mpwr_host_ready_work(struct work_struct *work)
++{
++        struct mpwr_dev *mpwr = container_of(work, struct mpwr_dev, host_ready_work.work);
++	int ret;
++
++	mutex_lock(&mpwr->modem_lock);
++	gpiod_direction_output(mpwr->dtr_gpio, 0);
++
++	/*
++	 * We need to give the modem some time to wake up.
++	 */
++	msleep(5);
++
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QCFG=\"urc/cache\",0", 500);
++	if (ret)
++		dev_warn(mpwr->dev,
++			 "Failed to disable urc/cache, you may not be able to see URCs\n");
++
++	gpiod_direction_output(mpwr->dtr_gpio, 1);
++	mutex_unlock(&mpwr->modem_lock);
++
++	gpiod_direction_output(mpwr->host_ready_gpio, 1);
++}
++
++static int mpwr_eg25_suspend(struct mpwr_dev *mpwr)
++{
++	int ret;
++
++	cancel_delayed_work_sync(&mpwr->host_ready_work);
++
++	gpiod_direction_output(mpwr->host_ready_gpio, 0);
++
++	mutex_lock(&mpwr->modem_lock);
++	gpiod_direction_output(mpwr->dtr_gpio, 0);
++
++	msleep(5);
++
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QCFG=\"urc/cache\",1", 500);
++	if (ret)
++		dev_warn(mpwr->dev,
++			 "Failed to enable urc/cache, you may lose URCs during suspend\n");
++
++	gpiod_direction_output(mpwr->dtr_gpio, 1);
++	mutex_unlock(&mpwr->modem_lock);
++
++	return 0;
++}
++
++static int mpwr_eg25_resume(struct mpwr_dev *mpwr)
++{
++	//gpiod_direction_output(mpwr->dtr_gpio, 0);
++
++	// delay disabling URC cache until the whole system is hopefully resumed...
++	schedule_delayed_work(&mpwr->host_ready_work, msecs_to_jiffies(1000));
++
++	return 0;
++}
++
++static const struct mpwr_gpio mpwr_eg25_gpios[] = {
++	MPWR_GPIO_DEF(enable, GPIOD_OUT_HIGH, true),
++	MPWR_GPIO_DEF(reset, GPIOD_OUT_LOW, true),
++	MPWR_GPIO_DEF(pwrkey, GPIOD_OUT_LOW, false),
++	MPWR_GPIO_DEF(dtr, GPIOD_OUT_LOW, true),
++	MPWR_GPIO_DEF(status, GPIOD_IN, false),
++	MPWR_GPIO_DEF_IRQ(wakeup, GPIOD_IN, true,
++			  IRQF_TRIGGER_FALLING),
++
++	// XXX: not really needed...
++	MPWR_GPIO_DEF(sleep, GPIOD_OUT_LOW, false),
++	MPWR_GPIO_DEF(host_ready, GPIOD_OUT_HIGH, false),
++	MPWR_GPIO_DEF(cts, GPIOD_IN, false),
++	MPWR_GPIO_DEF(rts, GPIOD_OUT_LOW, false),
++	{ },
++};
++
++static const struct mpwr_variant mpwr_eg25_variant = {
++	.power_up = mpwr_eg25_power_up,
++	.power_down = mpwr_eg25_power_down,
++	.recv_msg = mpwr_eg25_receive_msg,
++	.suspend = mpwr_eg25_suspend,
++	.resume = mpwr_eg25_resume,
++	.gpios = mpwr_eg25_gpios,
++	.regulator_required = true,
++	.monitor_wakeup = true,
++};
++
++// }}}
++// {{{ generic helpers
++
++static void mpwr_reset(struct mpwr_dev* mpwr)
++{
++	struct device *dev = mpwr->dev;
++	int ret;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags)) {
++		dev_err(dev, "reset requested but device is not enabled");
++		return;
++	}
++
++	if (!mpwr->reset_gpio) {
++		dev_err(dev, "reset is not configured for this device");
++		return;
++	}
++
++	if (!mpwr->variant->reset) {
++		dev_err(dev, "reset requested but not implemented");
++		return;
++	}
++
++	dev_info(dev, "resetting");
++	ret = mpwr->variant->reset(mpwr);
++	if (ret) {
++		dev_err(dev, "reset failed");
++	}
++}
++
++static void mpwr_power_down(struct mpwr_dev* mpwr)
++{
++	struct device *dev = mpwr->dev;
++	ktime_t start = ktime_get();
++	int ret;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return;
++
++	if (!mpwr->variant->power_down) {
++		dev_err(dev, "power down requested but not implemented");
++		return;
++	}
++
++	dev_info(dev, "powering down");
++
++	ret = mpwr->variant->power_down(mpwr);
++	if (ret) {
++		dev_err(dev, "power down failed");
++	} else {
++		clear_bit(MPWR_F_POWERED, mpwr->flags);
++		sysfs_notify(&mpwr->dev->kobj, NULL, "powered");
++		dev_info(mpwr->dev, "powered down in %lld ms\n",
++			 ktime_ms_delta(ktime_get(), start));
++	}
++}
++
++static void mpwr_power_up(struct mpwr_dev* mpwr)
++{
++	struct device *dev = mpwr->dev;
++	ktime_t start = ktime_get();
++	int ret;
++
++	if (test_bit(MPWR_F_POWERED, mpwr->flags))
++		return;
++
++	if (!mpwr->variant->power_up) {
++		dev_err(dev, "power up requested but not implemented");
++		return;
++	}
++
++	dev_info(dev, "powering up");
++
++	ret = mpwr->variant->power_up(mpwr);
++	if (ret) {
++		dev_err(dev, "power up failed");
++	} else {
++		set_bit(MPWR_F_POWERED, mpwr->flags);
++		sysfs_notify(&mpwr->dev->kobj, NULL, "powered");
++		dev_info(mpwr->dev, "powered up in %lld ms\n",
++			 ktime_ms_delta(ktime_get(), start));
++	}
++}
++
++// }}}
++// {{{ chardev
++
++static int mpwr_release(struct inode *ip, struct file *fp)
++{
++	struct mpwr_dev* mpwr = fp->private_data;
++
++	clear_bit(MPWR_F_OPEN, mpwr->flags);
++
++	return 0;
++}
++
++static int mpwr_open(struct inode *ip, struct file *fp)
++{
++	struct mpwr_dev* mpwr = container_of(ip->i_cdev, struct mpwr_dev, cdev);
++
++	fp->private_data = mpwr;
++
++	if (test_and_set_bit(MPWR_F_OPEN, mpwr->flags))
++		return -EBUSY;
++
++	nonseekable_open(ip, fp);
++	return 0;
++}
++
++static ssize_t mpwr_read(struct file *fp, char __user *buf, size_t len,
++			 loff_t *off)
++{
++	struct mpwr_dev* mpwr = fp->private_data;
++	int non_blocking = fp->f_flags & O_NONBLOCK;
++	unsigned int copied;
++	int ret;
++
++	if (non_blocking && kfifo_is_empty(&mpwr->kfifo))
++		return -EWOULDBLOCK;
++
++	ret = wait_event_interruptible(mpwr->wait,
++				       !kfifo_is_empty(&mpwr->kfifo)
++				       || test_bit(MPWR_F_OVERFLOW, mpwr->flags));
++	if (ret)
++		return ret;
++
++	if (test_and_clear_bit(MPWR_F_OVERFLOW, mpwr->flags)) {
++		if (len < 9)
++			return -E2BIG;
++		if (copy_to_user(buf, "OVERFLOW\n", 9))
++			return -EFAULT;
++		return 9;
++	}
++
++	ret = kfifo_to_user(&mpwr->kfifo, buf, len, &copied);
++
++	return ret ? ret : copied;
++}
++
++static unsigned int mpwr_poll(struct file *fp, poll_table *wait)
++{
++	struct mpwr_dev* mpwr = fp->private_data;
++
++	poll_wait(fp, &mpwr->wait, wait);
++
++	if (!kfifo_is_empty(&mpwr->kfifo))
++		return EPOLLIN | EPOLLRDNORM;
++
++	return 0;
++}
++
++static const struct file_operations mpwr_fops = {
++	.owner		= THIS_MODULE,
++	.open		= mpwr_open,
++	.release	= mpwr_release,
++	.llseek		= noop_llseek,
++	.read		= mpwr_read,
++	.poll		= mpwr_poll,
++};
++
++// }}}
++
++static void mpwr_work_handler(struct work_struct *work)
++{
++	struct mpwr_dev *mpwr = container_of(work, struct mpwr_dev, power_work);
++	unsigned long flags;
++	int last_request;
++
++	spin_lock_irqsave(&mpwr->lock, flags);
++	last_request = mpwr->last_request;
++	mpwr->last_request = 0;
++	spin_unlock_irqrestore(&mpwr->lock, flags);
++
++	pm_stay_awake(mpwr->dev);
++
++	mutex_lock(&mpwr->modem_lock);
++
++	if (last_request == MPWR_REQ_RESET) {
++		mpwr_reset(mpwr);
++	} else if (last_request == MPWR_REQ_PWDN) {
++		mpwr_power_down(mpwr);
++	} else if (last_request == MPWR_REQ_PWUP) {
++		mpwr_power_up(mpwr);
++	}
++
++	mutex_unlock(&mpwr->modem_lock);
++
++	clear_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags);
++	sysfs_notify(&mpwr->dev->kobj, NULL, "is_busy");
++	wake_up(&mpwr->wait);
++
++	pm_relax(mpwr->dev);
++}
++
++static void mpwr_request_power_change(struct mpwr_dev* mpwr, int request, int mode)
++{
++	unsigned long flags;
++
++	set_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags);
++	sysfs_notify(&mpwr->dev->kobj, NULL, "is_busy");
++
++	spin_lock_irqsave(&mpwr->lock, flags);
++	mpwr->last_request = request;
++	if (mode >= 0)
++		mpwr->powerup_mode = mode;
++	spin_unlock_irqrestore(&mpwr->lock, flags);
++
++	queue_work(mpwr->wq, &mpwr->power_work);
++}
++
++static irqreturn_t mpwr_gpio_isr(int irq, void *dev_id)
++{
++	struct mpwr_dev *mpwr = dev_id;
++
++	if (irq == mpwr->wakeup_irq) {
++		dev_dbg(mpwr->dev, "wakeup irq\n");
++
++		if (device_can_wakeup(mpwr->dev))
++			pm_wakeup_event(mpwr->dev, 2000);
++
++		set_bit(MPWR_F_GOT_WAKEUP, mpwr->flags);
++		spin_lock(&mpwr->lock);
++		mpwr->last_wakeup = ktime_get();
++		spin_unlock(&mpwr->lock);
++		wake_up(&mpwr->wait);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static void mpwr_wd_timer_fn(struct timer_list *t)
++{
++	struct mpwr_dev *mpwr = from_timer(mpwr, t, wd_timer);
++
++	if (!mpwr->variant->monitor_wakeup || !test_bit(MPWR_F_POWERED, mpwr->flags))
++		return;
++
++	/*
++	 * Monitor wakeup status:
++	 *
++	 * If RI signal is low for too long we assume the user killswitched
++	 * the modem at runtime.
++	 */
++	spin_lock(&mpwr->lock);
++	if (!gpiod_get_value(mpwr->wakeup_gpio)) {
++		if (ktime_ms_delta(ktime_get(), mpwr->last_wakeup) > 5000) {
++			if (!test_and_set_bit(MPWR_F_KILLSWITCHED, mpwr->flags))
++				sysfs_notify(&mpwr->dev->kobj, NULL, "killswitched");
++			wake_up(&mpwr->wait);
++			dev_warn(mpwr->dev, "modem looks killswitched at runtime!\n");
++		}
++	}
++	spin_unlock(&mpwr->lock);
++
++	mod_timer(t, jiffies + msecs_to_jiffies(1000));
++}
++
++// {{{ sysfs
++
++static ssize_t powered_show(struct device *dev,
++			    struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 !!test_bit(MPWR_F_POWERED, mpwr->flags));
++}
++
++static ssize_t powered_store(struct device *dev,
++			     struct device_attribute *attr,
++			     const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	unsigned status;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtouint(buf, 10, &status);
++	if (ret)
++		return ret;
++
++	mpwr_request_power_change(mpwr, status ? MPWR_REQ_PWUP : MPWR_REQ_PWDN, status);
++
++	return len;
++}
++
++static ssize_t powered_blocking_store(struct device *dev,
++				      struct device_attribute *attr,
++				      const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	unsigned status;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtouint(buf, 10, &status);
++	if (ret)
++		return ret;
++
++	mpwr_request_power_change(mpwr, status ? MPWR_REQ_PWUP : MPWR_REQ_PWDN, status);
++
++	ret = wait_event_interruptible_timeout(mpwr->wait,
++					       !test_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags),
++					       msecs_to_jiffies(60000));
++	if (ret <= 0) {
++		dev_err(mpwr->dev, "Power state change timeout\n");
++		return -EIO;
++	}
++
++	if (!!status != !!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return -EIO;
++
++	return len;
++}
++
++static ssize_t help_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	return scnprintf(buf, PAGE_SIZE,
++			"echo N > powered, where N can be:\n"
++			"0: power off\n"
++			"1: normal powerup\n"
++			"2: dumb powerup (no AT commands and little error checking during powerup)\n"
++			"3: fastboot powerup (with biktor's patched aboot - #W_DISABLE held low during powerup)\n"
++			"4: alternate powerup (megi's userspace - DTR held high during powerup)\n\n"
++			"echo N > powered_blocking can be used for the write to block until power status transition completes\n");
++}
++
++static ssize_t killswitched_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 !!test_bit(MPWR_F_KILLSWITCHED, mpwr->flags));
++}
++
++static ssize_t is_busy_show(struct device *dev,
++			    struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 !!test_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags));
++}
++
++static ssize_t hard_reset_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	bool val;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtobool(buf, &val);
++	if (ret)
++		return ret;
++	if (val)
++		mpwr_request_power_change(mpwr, MPWR_REQ_RESET, -1);
++
++	return len;
++}
++
++static ssize_t debug_pins_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	unsigned val;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtouint(buf, 16, &val);
++	if (ret)
++		return ret;
++
++	gpiod_direction_output(mpwr->host_ready_gpio, val & BIT(0));
++	gpiod_direction_output(mpwr->enable_gpio, val & BIT(1));
++	gpiod_direction_output(mpwr->dtr_gpio, val & BIT(2));
++	gpiod_direction_output(mpwr->rts_gpio, val & BIT(3));
++
++	return len;
++}
++
++static ssize_t debug_pins_show(struct device *dev,
++			       struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "CTS=%u RI=%u\n",
++			 gpiod_get_value(mpwr->cts_gpio), gpiod_get_value(mpwr->wakeup_gpio));
++}
++
++static DEVICE_ATTR_RW(powered);
++static DEVICE_ATTR_WO(powered_blocking);
++static DEVICE_ATTR_RO(killswitched);
++static DEVICE_ATTR_RO(is_busy);
++static DEVICE_ATTR_RO(help);
++static DEVICE_ATTR_WO(hard_reset);
++static DEVICE_ATTR_RW(debug_pins);
++
++static struct attribute *mpwr_attrs[] = {
++	&dev_attr_powered.attr,
++	&dev_attr_powered_blocking.attr,
++	&dev_attr_killswitched.attr,
++	&dev_attr_is_busy.attr,
++	&dev_attr_help.attr,
++	&dev_attr_hard_reset.attr,
++	&dev_attr_debug_pins.attr,
++	NULL,
++};
++
++static const struct attribute_group mpwr_group = {
++	.attrs = mpwr_attrs,
++};
++
++// }}}
++// {{{ rfkill
++
++static int mpwr_rfkill_set(void *data, bool blocked)
++{
++	struct mpwr_dev *mpwr = data;
++
++	gpiod_set_value(mpwr->enable_gpio, !blocked);
++	return 0;
++}
++
++static void mpwr_rfkill_query(struct rfkill *rfkill, void *data)
++{
++	struct mpwr_dev *mpwr = data;
++
++	rfkill_set_sw_state(rfkill, !gpiod_get_value(mpwr->enable_gpio));
++}
++
++static const struct rfkill_ops mpwr_rfkill_ops = {
++	.set_block = mpwr_rfkill_set,
++	.query = mpwr_rfkill_query,
++};
++
++// }}}
++// {{{ probe
++
++static int mpwr_probe_generic(struct device *dev, struct mpwr_dev **mpwr_out)
++{
++	struct mpwr_dev *mpwr;
++	struct device_node *np = dev->of_node;
++	struct device *sdev;
++	const char* cdev_name = NULL;
++	int ret, i;
++
++	mpwr = devm_kzalloc(dev, sizeof(*mpwr), GFP_KERNEL);
++	if (!mpwr)
++		return -ENOMEM;
++
++	mpwr->variant = of_device_get_match_data(dev);
++	if (!mpwr->variant)
++		return -EINVAL;
++
++	mpwr->dev = dev;
++	init_waitqueue_head(&mpwr->wait);
++        mutex_init(&mpwr->modem_lock);
++        spin_lock_init(&mpwr->lock);
++	INIT_WORK(&mpwr->power_work, &mpwr_work_handler);
++	INIT_WORK(&mpwr->finish_pdn_work, &mpwr_finish_pdn_work);
++        INIT_DELAYED_WORK(&mpwr->host_ready_work, mpwr_host_ready_work);
++	INIT_KFIFO(mpwr->kfifo);
++
++	ret = of_property_read_string(np, "char-device-name", &cdev_name);
++	if (ret) {
++		dev_err(dev, "char-device-name is not configured");
++		return -EINVAL;
++	}
++
++	if (of_property_read_bool(np, "blocked"))
++		set_bit(MPWR_F_BLOCKED, mpwr->flags);
++
++	mpwr->status_pwrkey_multiplexed =
++		of_property_read_bool(np, "status-pwrkey-multiplexed");
++
++	mpwr->regulator = devm_regulator_get_optional(dev, "power");
++	if (IS_ERR(mpwr->regulator)) {
++		ret = PTR_ERR(mpwr->regulator);
++                if (ret != -ENODEV) {
++			dev_err(dev, "can't get power supply err=%d", ret);
++			return ret;
++		}
++
++		mpwr->regulator = NULL;
++	}
++
++	if (!mpwr->regulator && mpwr->variant->regulator_required) {
++		dev_err(dev, "can't get power supply err=%d", -ENODEV);
++		return -ENODEV;
++	}
++
++	mpwr->regulator_vbus = devm_regulator_get(dev, "vbus");
++	if (IS_ERR(mpwr->regulator_vbus))
++		return dev_err_probe(dev, PTR_ERR(mpwr->regulator_vbus),
++				     "can't get vbus power supply\n");
++
++	for (i = 0; mpwr->variant->gpios[i].name; i++) {
++		const struct mpwr_gpio *io = &mpwr->variant->gpios[i];
++		struct gpio_desc **desc = (struct gpio_desc **)((u8*)mpwr +
++								io->desc_off);
++		int *irq = (int*)((u8*)mpwr + io->irq_off);
++		char buf[64];
++
++		if (io->required)
++			*desc = devm_gpiod_get(dev, io->name, io->flags);
++		else
++			*desc = devm_gpiod_get_optional(dev, io->name, io->flags);
++
++		if (IS_ERR(*desc)) {
++			dev_err(dev, "can't get %s gpio err=%ld", io->name,
++				PTR_ERR(*desc));
++			return PTR_ERR(*desc);
++		}
++
++		if (!*desc)
++			continue;
++
++		if (io->irq_flags == 0 || io->irq_off == 0)
++			continue;
++
++		*irq = gpiod_to_irq(*desc);
++		if (*irq <= 0) {
++			dev_err(dev, "error converting %s gpio to irq: %d",
++				io->name, ret);
++			return *irq;
++		}
++
++		snprintf(buf, sizeof buf, "modem-%s-gpio", io->name);
++		ret = devm_request_irq(dev, *irq, mpwr_gpio_isr, io->irq_flags,
++				       devm_kstrdup(dev, buf, GFP_KERNEL), mpwr);
++		if (ret) {
++			dev_err(dev, "error requesting %s irq: %d",
++				io->name, ret);
++			return ret;
++		}
++	}
++
++	if (mpwr->status_pwrkey_multiplexed && mpwr->pwrkey_gpio) {
++		dev_err(dev, "status and pwrkey are multiplexed, but pwrkey defined\n");
++		return -EINVAL;
++	}
++
++	if (mpwr->status_pwrkey_multiplexed && !mpwr->status_gpio) {
++		dev_err(dev, "status and pwrkey are multiplexed, but status is not defined\n");
++		return -EINVAL;
++	}
++
++	ret = devm_device_add_group(dev, &mpwr_group);
++	if (ret)
++		return ret;
++
++	// create char device
++	ret = alloc_chrdev_region(&mpwr->major, 0, 1, "modem-power");
++	if (ret) {
++		dev_err(dev, "can't allocate chrdev region");
++		goto err_disable_regulator;
++	}
++
++	cdev_init(&mpwr->cdev, &mpwr_fops);
++	mpwr->cdev.owner = THIS_MODULE;
++	ret = cdev_add(&mpwr->cdev, mpwr->major, 1);
++	if (ret) {
++		dev_err(dev, "can't add cdev");
++		goto err_unreg_chrev_region;
++	}
++
++	sdev = device_create(mpwr_class, dev, mpwr->major, mpwr, cdev_name);
++	if (IS_ERR(sdev)) {
++		ret = PTR_ERR(sdev);
++		goto err_del_cdev;
++	}
++
++	if (mpwr->wakeup_irq > 0) {
++		ret = device_init_wakeup(dev, true);
++		if (ret) {
++			dev_err(dev, "failed to init wakeup (%d)\n", ret);
++			goto err_free_dev;
++		}
++	}
++
++	if (mpwr->enable_gpio) {
++		mpwr->rfkill = rfkill_alloc("modem", dev, RFKILL_TYPE_WWAN,
++					    &mpwr_rfkill_ops, mpwr);
++		if (!mpwr->rfkill) {
++			dev_err(dev, "failed to alloc rfkill\n");
++			ret = -ENOMEM;
++			goto err_deinit_wakeup;
++		}
++
++                rfkill_init_sw_state(mpwr->rfkill, false);
++
++		ret = rfkill_register(mpwr->rfkill);
++		if (ret) {
++			dev_err(dev, "failed to register rfkill (%d)\n", ret);
++			goto err_free_rfkill;
++		}
++	}
++
++	mpwr->wq = alloc_ordered_workqueue("modem-power", 0);
++	if (!mpwr->wq) {
++		ret = -ENOMEM;
++		dev_err(dev, "failed to allocate workqueue\n");
++		goto err_unreg_rfkill;
++	}
++
++	if (mpwr->variant->power_init)
++		mpwr->variant->power_init(mpwr);
++
++	timer_setup(&mpwr->wd_timer, mpwr_wd_timer_fn, 0);
++	mod_timer(&mpwr->wd_timer, jiffies + msecs_to_jiffies(50));
++
++	dev_info(dev, "modem power manager ready");
++	*mpwr_out = mpwr;
++
++	return 0;
++
++err_unreg_rfkill:
++	if (mpwr->rfkill)
++		rfkill_unregister(mpwr->rfkill);
++err_free_rfkill:
++	if (mpwr->rfkill)
++		rfkill_destroy(mpwr->rfkill);
++err_deinit_wakeup:
++	if (mpwr->wakeup_irq > 0)
++		device_init_wakeup(dev, false);
++err_free_dev:
++	device_destroy(mpwr_class, mpwr->major);
++err_del_cdev:
++	cdev_del(&mpwr->cdev);
++err_unreg_chrev_region:
++	unregister_chrdev_region(mpwr->major, 1);
++err_disable_regulator:
++	cancel_work_sync(&mpwr->power_work);
++	return ret;
++}
++
++static int mpwr_remove_generic(struct mpwr_dev *mpwr)
++{
++	if (mpwr->rfkill) {
++		rfkill_unregister(mpwr->rfkill);
++		rfkill_destroy(mpwr->rfkill);
++	}
++
++	if (mpwr->wakeup_irq > 0)
++		device_init_wakeup(mpwr->dev, false);
++
++	del_timer_sync(&mpwr->wd_timer);
++        cancel_delayed_work_sync(&mpwr->host_ready_work);
++
++	cancel_work_sync(&mpwr->power_work);
++	destroy_workqueue(mpwr->wq);
++
++	mutex_lock(&mpwr->modem_lock);
++	mpwr_power_down(mpwr);
++	mutex_unlock(&mpwr->modem_lock);
++
++	device_destroy(mpwr_class, mpwr->major);
++	cdev_del(&mpwr->cdev);
++	unregister_chrdev_region(mpwr->major, 1);
++
++	return 0;
++}
++
++static void mpwr_shutdown_generic(struct mpwr_dev *mpwr)
++{
++	cancel_work_sync(&mpwr->power_work);
++        cancel_delayed_work_sync(&mpwr->host_ready_work);
++
++	mutex_lock(&mpwr->modem_lock);
++	mpwr_power_down(mpwr);
++	mutex_unlock(&mpwr->modem_lock);
++}
++
++// }}}
++// {{{ suspend/resume
++
++static int __maybe_unused mpwr_suspend(struct device *dev)
++{
++	struct mpwr_dev *mpwr = dev_get_drvdata(dev);
++	int ret = 0;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return 0;
++
++	//if (mpwr->sleep_gpio)
++		//gpiod_direction_output(mpwr->sleep_gpio, 1);
++
++	if (mpwr->variant->suspend)
++		mpwr->variant->suspend(mpwr);
++
++	if (mpwr->wakeup_irq && device_may_wakeup(mpwr->dev))
++		enable_irq_wake(mpwr->wakeup_irq);
++
++	return ret;
++}
++
++static int __maybe_unused mpwr_resume(struct device *dev)
++{
++	struct mpwr_dev *mpwr = dev_get_drvdata(dev);
++	int ret = 0;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return 0;
++
++	//if (mpwr->sleep_gpio)
++		//gpiod_direction_output(mpwr->sleep_gpio, 0);
++
++	if (mpwr->variant->resume)
++		mpwr->variant->resume(mpwr);
++
++	if (mpwr->wakeup_irq && device_may_wakeup(mpwr->dev))
++		disable_irq_wake(mpwr->wakeup_irq);
++
++	return ret;
++}
++
++static const struct dev_pm_ops mpwr_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(mpwr_suspend, mpwr_resume)
++};
++
++// }}}
++// {{{ serdev
++
++static int mpwr_serdev_send_msg(struct mpwr_dev *mpwr, const char *msg)
++{
++	int ret, len;
++	char buf[128];
++
++	if (!mpwr->serdev)
++		return -ENODEV;
++
++	len = snprintf(buf, sizeof buf, "%s\r\n", msg);
++	if (len >= sizeof buf)
++		return -E2BIG;
++
++	ret = serdev_device_write(mpwr->serdev, buf, len, msecs_to_jiffies(3000));
++	if (ret < len)
++		return -EIO;
++
++	serdev_device_wait_until_sent(mpwr->serdev, msecs_to_jiffies(3000));
++
++	return 0;
++}
++
++static int __mpwr_serdev_at_cmd(struct mpwr_dev *mpwr, const char *msg,
++				int timeout_ms, bool report_error, bool report_timeout)
++{
++        int ret;
++
++        if (test_and_set_bit(MPWR_F_RECEIVING_MSG, mpwr->flags))
++		return -EBUSY;
++
++	mpwr->msg_len = 0;
++
++	dev_dbg(mpwr->dev, "SEND: %s\n", msg);
++
++	ret = mpwr_serdev_send_msg(mpwr, msg);
++        if (ret) {
++		clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++		dev_err(mpwr->dev, "AT command '%s' can't be sent (%d)\n", msg, ret);
++                return ret;
++        }
++
++	ret = wait_event_interruptible_timeout(mpwr->wait,
++					       !test_bit(MPWR_F_RECEIVING_MSG, mpwr->flags),
++					       msecs_to_jiffies(timeout_ms));
++	if (ret <= 0) {
++		clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++		if (report_timeout)
++			dev_err(mpwr->dev, "AT command '%s' timed out\n", msg);
++                return ret ? ret : -ETIMEDOUT;
++	}
++
++        if (!mpwr->msg_ok) {
++		if (report_error)
++			dev_err(mpwr->dev, "AT command '%s' returned ERROR\n", msg);
++                return -EINVAL;
++	}
++
++        return 0;
++}
++
++static int mpwr_serdev_at_cmd(struct mpwr_dev *mpwr, const char *msg, int timeout_ms)
++{
++	return __mpwr_serdev_at_cmd(mpwr, msg, timeout_ms, true, true);
++}
++
++static int __mpwr_serdev_at_cmd_with_retry(struct mpwr_dev *mpwr, const char *msg,
++					   int timeout_ms, int tries, bool ignore_timeout)
++{
++	int ret = 0;
++
++	if (tries < 1)
++		tries = 1;
++
++	while (tries-- > 0) {
++		ret = __mpwr_serdev_at_cmd(mpwr, msg, timeout_ms, false, !ignore_timeout);
++		if (ret != -EINVAL && (!ignore_timeout || ret != -ETIMEDOUT))
++			return ret;
++
++		if (ret != -ETIMEDOUT)
++			msleep(1000);
++	}
++
++	dev_err(mpwr->dev, "AT command '%s' returned ERROR\n", msg);
++	return ret;
++}
++
++static int mpwr_serdev_at_cmd_with_retry(struct mpwr_dev *mpwr, const char *msg,
++					 int timeout_ms, int tries)
++{
++	return __mpwr_serdev_at_cmd_with_retry(mpwr, msg, timeout_ms, tries, false);
++}
++
++static int mpwr_serdev_at_cmd_with_retry_ignore_timeout(struct mpwr_dev *mpwr, const char *msg,
++							int timeout_ms, int tries)
++{
++	return __mpwr_serdev_at_cmd_with_retry(mpwr, msg, timeout_ms, tries, true);
++}
++
++static void mpwr_serdev_receive_msg(struct mpwr_dev *mpwr, const char *msg)
++{
++	dev_dbg(mpwr->dev, "RECV: %s\n", msg);
++
++	if (mpwr->variant->recv_msg)
++		mpwr->variant->recv_msg(mpwr, msg);
++
++        if (!test_bit(MPWR_F_RECEIVING_MSG, mpwr->flags))
++                return;
++
++	if (!strcmp(msg, "OK")) {
++                clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++                mpwr->msg_ok = true;
++		wake_up(&mpwr->wait);
++                return;
++	} else if (!strcmp(msg, "ERROR")) {
++                clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++                mpwr->msg_ok = false;
++		wake_up(&mpwr->wait);
++                return;
++	} else {
++                int len = strlen(msg);
++
++                if (mpwr->msg_len + len + 1 > sizeof(mpwr->msg)) {
++                        dev_warn(mpwr->dev, "message buffer overflow, ignoring message\n");
++                        return;
++                }
++
++                memcpy(mpwr->msg + mpwr->msg_len, msg, len + 1);
++                mpwr->msg_len += len + 1;
++        }
++}
++
++static size_t mpwr_serdev_receive_buf(struct serdev_device *serdev,
++				      const u8 *buf, size_t count)
++{
++	struct mpwr_dev *mpwr = serdev_device_get_drvdata(serdev);
++	size_t avail = sizeof(mpwr->rcvbuf) - mpwr->rcvbuf_fill;
++	char* p;
++
++	if (avail < count)
++		count = avail;
++
++	if (avail > 0) {
++		memcpy(mpwr->rcvbuf + mpwr->rcvbuf_fill, buf, count);
++		mpwr->rcvbuf_fill += count;
++	}
++
++	while (true) {
++		p = strnstr(mpwr->rcvbuf, "\r\n", mpwr->rcvbuf_fill);
++		if (p) {
++			if (p > mpwr->rcvbuf) {
++				*p = 0;
++				mpwr_serdev_receive_msg(mpwr, mpwr->rcvbuf);
++			}
++
++			mpwr->rcvbuf_fill -= (p - mpwr->rcvbuf) + 2;
++			memmove(mpwr->rcvbuf, p + 2, mpwr->rcvbuf_fill);
++		} else {
++			if (sizeof(mpwr->rcvbuf) - mpwr->rcvbuf_fill == 0) {
++				mpwr->rcvbuf_fill = 0;
++				dev_warn(mpwr->dev, "rcvbuf overflow\n");
++			}
++
++			break;
++		}
++	}
++
++        return count;
++}
++
++static const struct serdev_device_ops mpwr_serdev_ops = {
++	.receive_buf = mpwr_serdev_receive_buf,
++	.write_wakeup = serdev_device_write_wakeup,
++};
++
++static int mpwr_serdev_probe(struct serdev_device *serdev)
++{
++	struct device *dev = &serdev->dev;
++        struct mpwr_dev* mpwr;
++        int ret;
++
++	ret = mpwr_probe_generic(dev, &mpwr);
++	if (ret)
++		return ret;
++
++	serdev_device_set_drvdata(serdev, mpwr);
++	serdev_device_set_client_ops(serdev, &mpwr_serdev_ops);
++	mpwr->serdev = serdev;
++
++        return 0;
++}
++
++static void mpwr_serdev_remove(struct serdev_device *serdev)
++{
++	struct mpwr_dev *mpwr = serdev_device_get_drvdata(serdev);
++
++	mpwr_remove_generic(mpwr);
++}
++
++static const struct of_device_id mpwr_of_match_serdev[] = {
++	{ .compatible = "quectel,eg25",
++	  .data = &mpwr_eg25_variant },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mpwr_of_match_serdev);
++
++static void mpwr_serdev_shutdown(struct device *dev)
++{
++	struct mpwr_dev *mpwr = dev_get_drvdata(dev);
++
++	mpwr_shutdown_generic(mpwr);
++}
++
++static struct serdev_device_driver mpwr_serdev_driver = {
++        .probe  = mpwr_serdev_probe,
++        .remove = mpwr_serdev_remove,
++        .driver = {
++                .name = DRIVER_NAME,
++                .of_match_table = mpwr_of_match_serdev,
++		.pm = &mpwr_pm_ops,
++		.shutdown = mpwr_serdev_shutdown,
++        },
++};
++
++// }}}
++// {{{ platdev
++
++static int mpwr_pdev_probe(struct platform_device *pdev)
++{
++        struct mpwr_dev* mpwr;
++        int ret;
++
++	ret = mpwr_probe_generic(&pdev->dev, &mpwr);
++	if (ret)
++		return ret;
++
++	platform_set_drvdata(pdev, mpwr);
++        return 0;
++}
++
++static int mpwr_pdev_remove(struct platform_device *pdev)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(pdev);
++
++	return mpwr_remove_generic(mpwr);
++}
++
++static void mpwr_pdev_shutdown(struct platform_device *pdev)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(pdev);
++
++	mpwr_shutdown_generic(mpwr);
++}
++
++static const struct of_device_id mpwr_of_match_plat[] = {
++	{ .compatible = "zte,mg3732",
++	  .data = &mpwr_mg2723_variant },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mpwr_of_match_plat);
++
++static struct platform_driver mpwr_platform_driver = {
++	.probe = mpwr_pdev_probe,
++	.remove = mpwr_pdev_remove,
++	.shutdown = mpwr_pdev_shutdown,
++	.driver = {
++		.name = DRIVER_NAME,
++		.of_match_table = mpwr_of_match_plat,
++		.pm = &mpwr_pm_ops,
++	},
++};
++
++// }}}
++// {{{ driver init
++
++static int __init mpwr_driver_init(void)
++{
++	int ret;
++
++	mpwr_class = class_create("modem-power");
++	if (IS_ERR(mpwr_class))
++		return PTR_ERR(mpwr_class);
++
++	ret = serdev_device_driver_register(&mpwr_serdev_driver);
++	if (ret)
++		goto err_class;
++
++	ret = platform_driver_register(&mpwr_platform_driver);
++	if (ret)
++		goto err_serdev;
++
++	return ret;
++
++err_serdev:
++	serdev_device_driver_unregister(&mpwr_serdev_driver);
++err_class:
++	class_destroy(mpwr_class);
++	return ret;
++}
++
++static void __exit mpwr_driver_exit(void)
++{
++	serdev_device_driver_unregister(&mpwr_serdev_driver);
++	platform_driver_unregister(&mpwr_platform_driver);
++	class_destroy(mpwr_class);
++}
++
++module_init(mpwr_driver_init);
++module_exit(mpwr_driver_exit);
++
++MODULE_DESCRIPTION("Modem power manager");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_LICENSE("GPL v2");
++
++// }}}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/mmc-add-delay-after-power-class-selection.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/mmc-add-delay-after-power-class-selection.patch
new file mode 100644
index 000000000000..ffa50d13b096
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/mmc-add-delay-after-power-class-selection.patch
@@ -0,0 +1,38 @@
+From 6f848bbf8c86c3af515ede4d6ba2d3b210e5449b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 16 Mar 2018 20:31:55 +0100
+Subject: mmc: add delay after power class selection
+
+This seems to fix issue with sporadic ETIMEOUT in eMMC cache
+initialization on second generation TBS A711 tablet.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mmc/core/mmc.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
+index 5b2f7c285461..08efb293b70f 100644
+--- a/drivers/mmc/core/mmc.c
++++ b/drivers/mmc/core/mmc.c
+@@ -1854,6 +1854,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
+ 	 */
+ 	mmc_select_powerclass(card);
+ 
++	msleep(20);
++
+ 	/*
+ 	 * Enable HPI feature (if supported)
+ 	 */
+@@ -1872,6 +1874,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
+ 		}
+ 	}
+ 
++	msleep(20);
++
+ 	/*
+ 	 * If cache size is higher than 0, this indicates the existence of cache
+ 	 * and it can be turned on. Note that some eMMCs from Micron has been
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
new file mode 100644
index 000000000000..5efc5e251cbc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
@@ -0,0 +1,52 @@
+From 2c310c74617ae2afb551b15ccd8cc17eeb5feab3 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sat, 22 Jan 2022 20:35:39 +0000
+Subject: mmc: dw-mmc-rockchip: fix sdmmc after soft reboot
+
+During shutdown the dw-mmc driver shuts down the vqmmc regulator.
+This leads to situations where the sdmmc is unavailable after a soft
+reboot.
+Fix this by ensuring the vqmmc regulator is powered up on kernel
+shutdown.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ drivers/mmc/host/dw_mmc-rockchip.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
+index b07190ba4b7a..db2e8dd67993 100644
+--- a/drivers/mmc/host/dw_mmc-rockchip.c
++++ b/drivers/mmc/host/dw_mmc-rockchip.c
+@@ -10,6 +10,7 @@
+ #include <linux/of_address.h>
+ #include <linux/mmc/slot-gpio.h>
+ #include <linux/pm_runtime.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/slab.h>
+ 
+ #include "dw_mmc.h"
+@@ -388,9 +389,20 @@ static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
+ 			   NULL)
+ };
+ 
++static void dw_mci_rockchip_shutdown(struct platform_device *pdev)
++{
++	struct dw_mci *host = dev_get_drvdata(&pdev->dev);
++	struct mmc_host *mmc = host->slot->mmc;
++
++	if (!IS_ERR(mmc->supply.vqmmc) && !(host->vqmmc_enabled))
++		if(!regulator_enable(mmc->supply.vqmmc))
++			host->vqmmc_enabled = true;
++}
++
+ static struct platform_driver dw_mci_rockchip_pltfm_driver = {
+ 	.probe		= dw_mci_rockchip_probe,
+ 	.remove_new	= dw_mci_rockchip_remove,
++	.shutdown	= dw_mci_rockchip_shutdown,
+ 	.driver		= {
+ 		.name		= "dwmmc_rockchip",
+ 		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
new file mode 100644
index 000000000000..2a454f76c65a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
@@ -0,0 +1,143 @@
+From d6bb6fc166d25d0c70f3ee55423119096ea87306 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 15 Feb 2021 09:11:16 +0100
+Subject: mmc: sunxi-mmc: Remove runtime-PM
+
+With runtime PM I get a lot of errors like (on H5/H6 f2fs formatted
+rootfs):
+
+[81360.499781] mmc_erase: group start error -110, status 0x0
+[81360.550703] mmc_erase: group start error -110, status 0x0
+[81360.599594] sunxi-mmc 4020000.mmc: data error, sending stop command
+[81360.599611] sunxi-mmc 4020000.mmc: send stop command failed
+[83474.053131] mmc_erase: group start error -110, status 0x0
+[83474.104043] mmc_erase: group start error -110, status 0x0
+[83850.888258] mmc_erase: group start error -110, status 0x0
+[83850.938810] mmc_erase: group start error -110, status 0x0
+[83850.989808] mmc_erase: group start error -110, status 0x0
+[83851.040888] mmc_erase: group start error -110, status 0x0
+[83851.091908] mmc_erase: group start error -110, status 0x0
+[83851.142938] mmc_erase: group start error -110, status 0x0
+[83851.193806] sunxi-mmc 4020000.mmc: data error, sending stop command
+[83851.193825] sunxi-mmc 4020000.mmc: send stop command failed
+[83851.201040] sunxi-mmc 4020000.mmc: data error, sending stop command
+[83851.201062] sunxi-mmc 4020000.mmc: send stop command failed
+[83851.720183] mmc_erase: group start error -110, status 0x0
+[83851.770866] mmc_erase: group start error -110, status 0x0
+[83851.821418] mmc_erase: group start error -110, status 0x0
+[83851.872081] mmc_erase: group start error -110, status 0x0
+[83851.922757] mmc_erase: group start error -110, status 0x0
+[83851.999497] mmc_erase: group start error -110, status 0x0
+[83852.050151] mmc_erase: group start error -110, status 0x0
+[83852.101319] mmc_erase: group start error -110, status 0x0
+[83852.152189] mmc_erase: group start error -110, status 0x0
+[83852.202866] mmc_erase: group start error -110, status 0x0
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mmc/host/sunxi-mmc.c | 35 +++++++++++++++++++----------------
+ 1 file changed, 19 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index d3bd0ac99ec4..e9370c736497 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -949,9 +949,15 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ {
+ 	struct sunxi_mmc_host *host = mmc_priv(mmc);
+ 
++	if (ios->power_mode == MMC_POWER_OFF)
++		sunxi_mmc_reset_host(host);
++
+ 	sunxi_mmc_card_power(host, ios);
+ 	sunxi_mmc_set_bus_width(host, ios->bus_width);
+ 	sunxi_mmc_set_clk(host, ios);
++
++	if (ios->power_mode == MMC_POWER_UP)
++		sunxi_mmc_init_host(host);
+ }
+ 
+ static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
+@@ -977,8 +983,8 @@ static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+ 	unsigned long flags;
+ 	u32 imask;
+ 
+-	if (enable)
+-		pm_runtime_get_noresume(host->dev);
++	//if (enable)
++		//pm_runtime_get_noresume(host->dev);
+ 
+ 	spin_lock_irqsave(&host->lock, flags);
+ 
+@@ -993,8 +999,8 @@ static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+ 	mmc_writel(host, REG_IMASK, imask);
+ 	spin_unlock_irqrestore(&host->lock, flags);
+ 
+-	if (!enable)
+-		pm_runtime_put_noidle(host->mmc->parent);
++	//if (!enable)
++		//pm_runtime_put_noidle(host->mmc->parent);
+ }
+ 
+ static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
+@@ -1464,10 +1470,10 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		goto error_free_dma;
+ 
+-	pm_runtime_set_active(&pdev->dev);
+-	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
+-	pm_runtime_use_autosuspend(&pdev->dev);
+-	pm_runtime_enable(&pdev->dev);
++	//pm_runtime_set_active(&pdev->dev);
++	//pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
++	//pm_runtime_use_autosuspend(&pdev->dev);
++	//pm_runtime_enable(&pdev->dev);
+ 
+ 	ret = mmc_add_host(mmc);
+ 	if (ret)
+@@ -1492,11 +1498,11 @@ static void sunxi_mmc_remove(struct platform_device *pdev)
+ 	struct sunxi_mmc_host *host = mmc_priv(mmc);
+ 
+ 	mmc_remove_host(mmc);
+-	pm_runtime_disable(&pdev->dev);
+-	if (!pm_runtime_status_suspended(&pdev->dev)) {
++	//pm_runtime_disable(&pdev->dev);
++	//if (!pm_runtime_status_suspended(&pdev->dev)) {
+ 		disable_irq(host->irq);
+ 		sunxi_mmc_disable(host);
+-	}
++	//}
+ 	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+ 	mmc_free_host(mmc);
+ }
+@@ -1531,7 +1537,6 @@ static int sunxi_mmc_runtime_suspend(struct device *dev)
+ 	 * Disabling the irq  will prevent this.
+ 	 */
+ 	disable_irq(host->irq);
+-	sunxi_mmc_reset_host(host);
+ 	sunxi_mmc_disable(host);
+ 
+ 	return 0;
+@@ -1539,8 +1544,6 @@ static int sunxi_mmc_runtime_suspend(struct device *dev)
+ #endif
+ 
+ static const struct dev_pm_ops sunxi_mmc_pm_ops = {
+-	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+-				pm_runtime_force_resume)
+ 	SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
+ 			   sunxi_mmc_runtime_resume,
+ 			   NULL)
+@@ -1550,8 +1553,8 @@ static struct platform_driver sunxi_mmc_driver = {
+ 	.driver = {
+ 		.name	= "sunxi-mmc",
+ 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+-		.of_match_table = sunxi_mmc_of_match,
+-		.pm = &sunxi_mmc_pm_ops,
++		.of_match_table = of_match_ptr(sunxi_mmc_of_match),
++		//.pm = &sunxi_mmc_pm_ops,
+ 	},
+ 	.probe		= sunxi_mmc_probe,
+ 	.remove_new	= sunxi_mmc_remove,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
new file mode 100644
index 000000000000..f44b04404953
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
@@ -0,0 +1,85 @@
+From 8336de04155e6e67d262bdb36fb5e4a9d78a52f6 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 1 Aug 2023 14:56:33 +0200
+Subject: mtd: spi-nor: Add Alliance memory support
+
+- 128MBit flash: as25f1128mq
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mtd/spi-nor/Makefile   |  1 +
+ drivers/mtd/spi-nor/alliance.c | 24 ++++++++++++++++++++++++
+ drivers/mtd/spi-nor/core.c     |  1 +
+ drivers/mtd/spi-nor/core.h     |  1 +
+ 4 files changed, 27 insertions(+)
+ create mode 100644 drivers/mtd/spi-nor/alliance.c
+
+diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
+index 5e68468b72fc..37a3ac018a39 100644
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ 
+ spi-nor-objs			:= core.o sfdp.o swp.o otp.o sysfs.o
++spi-nor-objs			+= alliance.o
+ spi-nor-objs			+= atmel.o
+ spi-nor-objs			+= eon.o
+ spi-nor-objs			+= esmt.o
+diff --git a/drivers/mtd/spi-nor/alliance.c b/drivers/mtd/spi-nor/alliance.c
+new file mode 100644
+index 000000000000..f3f03d458a5c
+--- /dev/null
++++ b/drivers/mtd/spi-nor/alliance.c
+@@ -0,0 +1,24 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2023, Ondrej Jirman <megi@xff.cz>
++ */
++
++#include <linux/mtd/spi-nor.h>
++
++#include "core.h"
++
++static const struct flash_info alliance_nor_parts[] = {
++	{
++		.id = SNOR_ID(0x52, 0x42, 0x18),
++		.name = "as25f1128mq",
++		.size = SZ_16M,
++		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
++		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
++	},
++};
++
++const struct spi_nor_manufacturer spi_nor_alliance = {
++	.name = "alliance",
++	.parts = alliance_nor_parts,
++	.nparts = ARRAY_SIZE(alliance_nor_parts),
++};
+diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
+index a5109f1d5e30..c7020ebb915e 100644
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -1974,6 +1974,7 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
+ }
+ 
+ static const struct spi_nor_manufacturer *manufacturers[] = {
++	&spi_nor_alliance,
+ 	&spi_nor_atmel,
+ 	&spi_nor_eon,
+ 	&spi_nor_esmt,
+diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
+index 442786685515..69a7dc6540d3 100644
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -590,6 +590,7 @@ struct sfdp {
+ };
+ 
+ /* Manufacturer drivers. */
++extern const struct spi_nor_manufacturer spi_nor_alliance;
+ extern const struct spi_nor_manufacturer spi_nor_atmel;
+ extern const struct spi_nor_manufacturer spi_nor_eon;
+ extern const struct spi_nor_manufacturer spi_nor_esmt;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch
new file mode 100644
index 000000000000..f08382da61ec
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch
@@ -0,0 +1,41 @@
+From 7876e3aeac9a52885d8475bcdc0269cea3c52c56 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 30 Sep 2019 11:49:54 +0200
+Subject: mtd: spi-nor: Add vdd regulator support
+
+On some boards, SPI NOR needs a regulator be enabled.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mtd/spi-nor/core.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
+index 028514c6996f..a5109f1d5e30 100644
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -17,6 +17,7 @@
+ #include <linux/mtd/spi-nor.h>
+ #include <linux/mutex.h>
+ #include <linux/of_platform.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/sched/task_stack.h>
+ #include <linux/sizes.h>
+ #include <linux/slab.h>
+@@ -3630,6 +3631,13 @@ static int spi_nor_probe(struct spi_mem *spimem)
+ 	if (!nor)
+ 		return -ENOMEM;
+ 
++	ret = devm_regulator_get_enable(&spi->dev, "vdd");
++	if (ret)
++		return dev_err_probe(&spi->dev, ret,
++				     "unable to get vdd regulator\n");
++
++	msleep(5);
++
+ 	nor->spimem = spimem;
+ 	nor->dev = &spi->dev;
+ 	spi_nor_set_flash_node(nor, spi->dev.of_node);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
new file mode 100644
index 000000000000..94780678792a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
@@ -0,0 +1,89 @@
+From 9d59552e19d9b0567242ca5642ed5facdcebafd6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 20 Aug 2019 14:31:38 +0200
+Subject: net: stmmac: sun8i: Add support for enabling a regulator for PHY I/O
+ pins
+
+Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
+to the phy datasheet, both regulators need to be enabled at the same time.
+
+Add support for the second optional regulator, "phy-io", to the glue
+driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 20 ++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 49704e017a48..08eeaf8d14bf 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -61,6 +61,8 @@ struct emac_variant {
+ /* struct sunxi_priv_data - hold all sunxi private data
+  * @ephy_clk:	reference to the optional EPHY clock for the internal PHY
+  * @regulator_phy: reference to the optional regulator
++ * @regulator_phy_io: reference to the optional regulator for
++ *		PHY I/O pins
+  * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
+  * @variant:	reference to the current board variant
+  * @regmap:	regmap for using the syscon
+@@ -71,6 +73,7 @@ struct emac_variant {
+ struct sunxi_priv_data {
+ 	struct clk *ephy_clk;
+ 	struct regulator *regulator_phy;
++	struct regulator *regulator_phy_io;
+ 	struct reset_control *rst_ephy;
+ 	const struct emac_variant *variant;
+ 	struct regmap_field *regmap_field;
+@@ -588,10 +591,16 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	struct sunxi_priv_data *gmac = priv;
+ 	int ret;
+ 
++	ret = regulator_enable(gmac->regulator_phy_io);
++	if (ret) {
++		dev_err(&pdev->dev, "Fail to enable PHY I/O regulator\n");
++		return ret;
++	}
++
+ 	ret = regulator_enable(gmac->regulator_phy);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "Fail to enable PHY regulator\n");
+-		return ret;
++		goto err_disable_regulator_phy_io;
+ 	}
+ 
+ 	if (gmac->use_internal_phy) {
+@@ -604,6 +613,8 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 
+ err_disable_regulator:
+ 	regulator_disable(gmac->regulator_phy);
++err_disable_regulator_phy_io:
++	regulator_disable(gmac->regulator_phy_io);
+ 
+ 	return ret;
+ }
+@@ -1051,6 +1062,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+ 		sun8i_dwmac_unpower_internal_phy(gmac);
+ 
+ 	regulator_disable(gmac->regulator_phy);
++	regulator_disable(gmac->regulator_phy_io);
+ }
+ 
+ static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
+@@ -1179,6 +1191,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy),
+ 				     "Failed to get PHY regulator\n");
+ 
++	/* Optional regulator for PHY I/O pins */
++	gmac->regulator_phy_io = devm_regulator_get(dev, "phy-io");
++	if (IS_ERR(gmac->regulator_phy_io))
++		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy_io),
++				     "Failed to get PHY I/O regulator\n");
++
+ 	/* The "GMAC clock control" register might be located in the
+ 	 * CCU address range (on the R40), or the system control address
+ 	 * range (on most other sun8i and later SoCs).
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
new file mode 100644
index 000000000000..eabb1acb4cd7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
@@ -0,0 +1,81 @@
+From eaa9f4b8d0a87b60e2f1d041644eac3d0c19d375 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 20 Aug 2019 14:29:29 +0200
+Subject: net: stmmac: sun8i: Rename PHY regulator variable to regulator_phy
+
+We'll be adding further optional regulators, and this makes it clearer
+what the regulator is for.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c  | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 31aa3d52fb4c..49704e017a48 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -60,7 +60,7 @@ struct emac_variant {
+ 
+ /* struct sunxi_priv_data - hold all sunxi private data
+  * @ephy_clk:	reference to the optional EPHY clock for the internal PHY
+- * @regulator:	reference to the optional regulator
++ * @regulator_phy: reference to the optional regulator
+  * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
+  * @variant:	reference to the current board variant
+  * @regmap:	regmap for using the syscon
+@@ -70,7 +70,7 @@ struct emac_variant {
+  */
+ struct sunxi_priv_data {
+ 	struct clk *ephy_clk;
+-	struct regulator *regulator;
++	struct regulator *regulator_phy;
+ 	struct reset_control *rst_ephy;
+ 	const struct emac_variant *variant;
+ 	struct regmap_field *regmap_field;
+@@ -588,9 +588,9 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	struct sunxi_priv_data *gmac = priv;
+ 	int ret;
+ 
+-	ret = regulator_enable(gmac->regulator);
++	ret = regulator_enable(gmac->regulator_phy);
+ 	if (ret) {
+-		dev_err(&pdev->dev, "Fail to enable regulator\n");
++		dev_err(&pdev->dev, "Fail to enable PHY regulator\n");
+ 		return ret;
+ 	}
+ 
+@@ -603,7 +603,7 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	return 0;
+ 
+ err_disable_regulator:
+-	regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator_phy);
+ 
+ 	return ret;
+ }
+@@ -1050,7 +1050,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+ 	if (gmac->variant->soc_has_internal_phy)
+ 		sun8i_dwmac_unpower_internal_phy(gmac);
+ 
+-	regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator_phy);
+ }
+ 
+ static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
+@@ -1174,9 +1174,9 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	/* Optional regulator for PHY */
+-	gmac->regulator = devm_regulator_get(dev, "phy");
+-	if (IS_ERR(gmac->regulator))
+-		return dev_err_probe(dev, PTR_ERR(gmac->regulator),
++	gmac->regulator_phy = devm_regulator_get(dev, "phy");
++	if (IS_ERR(gmac->regulator_phy))
++		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy),
+ 				     "Failed to get PHY regulator\n");
+ 
+ 	/* The "GMAC clock control" register might be located in the
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
new file mode 100644
index 000000000000..7129fc6a19a4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
@@ -0,0 +1,84 @@
+From 243314dc1a656e67889b95c18c60ac012af8d1f0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 27 Mar 2019 13:21:06 +0100
+Subject: net: stmmac: sun8i: Use devm_regulator_get for PHY regulator
+
+Use devm_regulator_get instead of devm_regulator_get_optional and rely
+on dummy supply. This avoids NULL checks before regulator_enable/disable
+calls.
+
+This path also improves error reporting, because we now report both
+use of dummy supply and error during registration with more detail,
+instead of generic info level message "No regulator found" that
+was reported previously on errors and lack of regulator property in DT.
+
+Finally, we'll be adding further optional regulators, and the overall
+code will be simpler.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 27 +++++++------------
+ 1 file changed, 10 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index e1b761dcfa1d..31aa3d52fb4c 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -588,12 +588,10 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	struct sunxi_priv_data *gmac = priv;
+ 	int ret;
+ 
+-	if (gmac->regulator) {
+-		ret = regulator_enable(gmac->regulator);
+-		if (ret) {
+-			dev_err(&pdev->dev, "Fail to enable regulator\n");
+-			return ret;
+-		}
++	ret = regulator_enable(gmac->regulator);
++	if (ret) {
++		dev_err(&pdev->dev, "Fail to enable regulator\n");
++		return ret;
+ 	}
+ 
+ 	if (gmac->use_internal_phy) {
+@@ -605,8 +603,7 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	return 0;
+ 
+ err_disable_regulator:
+-	if (gmac->regulator)
+-		regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator);
+ 
+ 	return ret;
+ }
+@@ -1053,8 +1050,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+ 	if (gmac->variant->soc_has_internal_phy)
+ 		sun8i_dwmac_unpower_internal_phy(gmac);
+ 
+-	if (gmac->regulator)
+-		regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator);
+ }
+ 
+ static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
+@@ -1178,13 +1174,10 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	/* Optional regulator for PHY */
+-	gmac->regulator = devm_regulator_get_optional(dev, "phy");
+-	if (IS_ERR(gmac->regulator)) {
+-		if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
+-			return -EPROBE_DEFER;
+-		dev_info(dev, "No regulator found\n");
+-		gmac->regulator = NULL;
+-	}
++	gmac->regulator = devm_regulator_get(dev, "phy");
++	if (IS_ERR(gmac->regulator))
++		return dev_err_probe(dev, PTR_ERR(gmac->regulator),
++				     "Failed to get PHY regulator\n");
+ 
+ 	/* The "GMAC clock control" register might be located in the
+ 	 * CCU address range (on the R40), or the system control address
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
new file mode 100644
index 000000000000..558d4215eace
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
@@ -0,0 +1,106 @@
+From a0d1b9cae4b6ea4fa41dc135bd59ae138f891cce Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 10 Nov 2017 14:29:26 +0100
+Subject: nfc: pn544: Add support for VBAT/PVDD regulators
+
+Regulators are required, so this can't go into mainline as is.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/nfc/pn544/i2c.c | 31 +++++++++++++++++++++++++++++--
+ 1 file changed, 29 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/nfc/pn544/i2c.c b/drivers/nfc/pn544/i2c.c
+index 3f6d74832bac..ed6ade728f55 100644
+--- a/drivers/nfc/pn544/i2c.c
++++ b/drivers/nfc/pn544/i2c.c
+@@ -16,6 +16,7 @@
+ #include <linux/nfc.h>
+ #include <linux/firmware.h>
+ #include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
+ 
+ #include <asm/unaligned.h>
+ 
+@@ -59,6 +60,14 @@ MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match);
+ 
+ #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
+ 
++/* regulator supplies */
++static const char * const pn544_supply_names[] = {
++	"PVDD",  /* Digital Core (1.8V) supply */
++	"VBAT",  /* Analog (2.9V-5.5V) supply */
++};
++
++#define PN544_NUM_SUPPLIES ARRAY_SIZE(pn544_supply_names)
++
+ /*
+  * Exposed through the 4 most significant bytes
+  * from the HCI SW_VERSION first byte, a.k.a.
+@@ -150,6 +159,7 @@ struct pn544_i2c_phy {
+ 	struct i2c_client *i2c_dev;
+ 	struct nfc_hci_dev *hdev;
+ 
++	struct regulator_bulk_data supplies[PN544_NUM_SUPPLIES];
+ 	struct gpio_desc *gpiod_en;
+ 	struct gpio_desc *gpiod_fw;
+ 
+@@ -240,6 +250,13 @@ static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode)
+ static int pn544_hci_i2c_enable(void *phy_id)
+ {
+ 	struct pn544_i2c_phy *phy = phy_id;
++	int ret;
++
++	pr_info("%s\n", __func__);
++
++	ret = regulator_bulk_enable(PN544_NUM_SUPPLIES, phy->supplies);
++	if (ret)
++		return ret;
+ 
+ 	pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE);
+ 
+@@ -262,6 +279,8 @@ static void pn544_hci_i2c_disable(void *phy_id)
+ 	gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
+ 	usleep_range(10000, 15000);
+ 
++	regulator_bulk_disable(PN544_NUM_SUPPLIES, phy->supplies);
++
+ 	phy->powered = 0;
+ }
+ 
+@@ -368,7 +387,7 @@ static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb)
+ 
+ 	if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) ||
+ 	    (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) {
+-		nfc_err(&client->dev, "invalid len byte\n");
++		nfc_err(&client->dev, "invalid len byte %hhx\n", len);
+ 		r = -EBADMSG;
+ 		goto flush;
+ 	}
+@@ -870,7 +889,7 @@ static int pn544_hci_i2c_probe(struct i2c_client *client)
+ {
+ 	struct device *dev = &client->dev;
+ 	struct pn544_i2c_phy *phy;
+-	int r = 0;
++	int r = 0, i;
+ 
+ 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+ 		nfc_err(&client->dev, "Need I2C_FUNC_I2C\n");
+@@ -892,6 +911,14 @@ static int pn544_hci_i2c_probe(struct i2c_client *client)
+ 	if (r)
+ 		dev_dbg(dev, "Unable to add GPIO mapping table\n");
+ 
++	for (i = 0; i < PN544_NUM_SUPPLIES; i++)
++		phy->supplies[i].supply = pn544_supply_names[i];
++
++	r = devm_regulator_bulk_get(&client->dev, PN544_NUM_SUPPLIES,
++				    phy->supplies);
++	if (r)
++		return r;
++
+ 	/* Get EN GPIO */
+ 	phy->gpiod_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
+ 	if (IS_ERR(phy->gpiod_en)) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
new file mode 100644
index 000000000000..5b1993533791
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
@@ -0,0 +1,58 @@
+From 8465bbc3c387360cd9c64e0b5f105f6698e17ad4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 15 May 2021 21:43:44 +0200
+Subject: of: property: fw_devlink: Support allwinner,sram links
+
+allwinner,sram property points to a node representing section of SRAM,
+which is implemented by its ancestor (syscon), so we link to the
+parent of parent of the actual SRAM section node that the link points
+to.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/of/property.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/of/property.c b/drivers/of/property.c
+index 164d77cb9445..6fcfcda9d9ad 100644
+--- a/drivers/of/property.c
++++ b/drivers/of/property.c
+@@ -1355,6 +1355,27 @@ static struct device_node *parse_remote_endpoint(struct device_node *np,
+ 	return of_graph_get_remote_port_parent(np);
+ }
+ 
++static struct device_node *parse_allwinner_sram(struct device_node *np,
++						const char *prop_name, int index)
++{
++	struct device_node *sram_node;
++
++	if (!IS_ENABLED(CONFIG_SUNXI_SRAM))
++		return NULL;
++
++	if (strcmp(prop_name, "allwinner,sram"))
++		return NULL;
++
++	if (index > 0)
++		return NULL;
++
++	sram_node = of_parse_phandle(np, prop_name, 0);
++	sram_node = of_get_parent(sram_node);
++	sram_node = of_get_parent(sram_node);
++
++	return sram_node;
++}
++
+ static const struct supplier_bindings of_supplier_bindings[] = {
+ 	{ .parse_prop = parse_clocks, },
+ 	{ .parse_prop = parse_interconnects, },
+@@ -1403,6 +1424,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {
+ 		.parse_prop = parse_post_init_providers,
+ 		.fwlink_flags = FWLINK_FLAG_IGNORE,
+ 	},
++	{ .parse_prop = parse_allwinner_sram, },
+ 	{}
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
new file mode 100644
index 000000000000..e53901ff9257
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
@@ -0,0 +1,31 @@
+From 671322f39e971ea480a39283236fdee3916ec2f4 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 29 Oct 2022 23:16:51 +0200
+Subject: opp: core: Avoid confusing error when no regulator is defined in DT
+
+A64 GPU doesn't have a separate regulator. Avoid useless error.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/opp/core.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/opp/core.c b/drivers/opp/core.c
+index 4e4d293bf5b1..a9a472510f9f 100644
+--- a/drivers/opp/core.c
++++ b/drivers/opp/core.c
+@@ -2186,6 +2186,11 @@ static int _opp_set_regulators(struct opp_table *opp_table, struct device *dev,
+ 	for (i = 0; i < count; i++) {
+ 		reg = regulator_get_optional(dev, names[i]);
+ 		if (IS_ERR(reg)) {
++			if (PTR_ERR(reg) == -ENODEV) {
++				ret = -ENODEV;
++				goto free_regulators;
++			}
++
+ 			ret = dev_err_probe(dev, PTR_ERR(reg),
+ 					    "%s: no regulator (%s) found\n",
+ 					    __func__, names[i]);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
new file mode 100644
index 000000000000..135842b28a97
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
@@ -0,0 +1,32 @@
+From 4140996e99b8da5a2a6bba7501a0e0ddf5dc5041 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 14 Jun 2023 00:48:21 +0200
+Subject: pci: Workaround ITS timeouts on poweroff/reboot on Orange Pi 5 Plus
+
+Call to pci_free_irq_vectors on PCIE2x ports causes ITS timeout messages
+and delayed shutdown/reboot (by up to a minute).
+
+The root cause will be elsewhere. This is not for upstream. Anyway,
+there should be no harm from this, since we're shutting down anyway.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/pci/pcie/portdrv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c
+index bb65dfe43409..967b4d956a84 100644
+--- a/drivers/pci/pcie/portdrv.c
++++ b/drivers/pci/pcie/portdrv.c
+@@ -739,7 +739,7 @@ static void pcie_portdrv_shutdown(struct pci_dev *dev)
+ 		pm_runtime_dont_use_autosuspend(&dev->dev);
+ 	}
+ 
+-	pcie_port_device_remove(dev);
++	device_for_each_child(&dev->dev, NULL, remove_iter);
+ }
+ 
+ static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
new file mode 100644
index 000000000000..6f7bd0ec8a7d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
@@ -0,0 +1,146 @@
+From c7744b5bc2a8470078f453b1e12c12c942ff72d2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 8 Jun 2020 00:11:06 +0200
+Subject: phy: allwinner: sun4i-usb: Add support for usb_role_switch
+
+This allow controlling the usb0 data role from a typec port driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/phy/allwinner/Kconfig         |  1 +
+ drivers/phy/allwinner/phy-sun4i-usb.c | 51 ++++++++++++++++++++++++++-
+ 2 files changed, 51 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
+index fb584518b2d0..e93a53139460 100644
+--- a/drivers/phy/allwinner/Kconfig
++++ b/drivers/phy/allwinner/Kconfig
+@@ -12,6 +12,7 @@ config PHY_SUN4I_USB
+ 	depends on USB_SUPPORT
+ 	select GENERIC_PHY
+ 	select USB_COMMON
++	select USB_ROLE_SWITCH
+ 	help
+ 	  Enable this to support the transceiver that is part of Allwinner
+ 	  sunxi SoCs.
+diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
+index b0f19e950601..9b6b68eb00f8 100644
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -32,6 +32,7 @@
+ #include <linux/reset.h>
+ #include <linux/spinlock.h>
+ #include <linux/usb/of.h>
++#include <linux/usb/role.h>
+ #include <linux/workqueue.h>
+ 
+ #define REG_ISCR			0x00
+@@ -140,6 +141,9 @@ struct sun4i_usb_phy_data {
+ 	int id_det;
+ 	int vbus_det;
+ 	struct delayed_work detect;
++	struct usb_role_switch_desc switch_desc;
++	struct usb_role_switch *role_switch;
++	int usb_role;
+ };
+ 
+ #define to_sun4i_usb_phy_data(phy) \
+@@ -402,6 +406,9 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
+ 
+ static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
+ {
++	if (data->usb_role >= 0)
++		return data->usb_role == USB_ROLE_HOST ? 0 : 1;
++
+ 	switch (data->dr_mode) {
+ 	case USB_DR_MODE_OTG:
+ 		if (data->id_det_gpio)
+@@ -418,6 +425,9 @@ static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
+ 
+ static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
+ {
++	if (data->usb_role >= 0)
++		return data->usb_role == USB_ROLE_NONE ? 0 : 1;
++
+ 	if (data->vbus_det_gpio)
+ 		return gpiod_get_value_cansleep(data->vbus_det_gpio);
+ 
+@@ -437,7 +447,7 @@ static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
+ 
+ static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data)
+ {
+-	return data->vbus_det_gpio || data->vbus_power_supply;
++	return data->usb_role >= 0 || data->vbus_det_gpio || data->vbus_power_supply;
+ }
+ 
+ static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
+@@ -696,6 +706,24 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
+ 	return data->phys[args->args[0]].phy;
+ }
+ 
++static int sun4i_usb_role_set(struct usb_role_switch *sw, enum usb_role role)
++{
++	struct sun4i_usb_phy_data *data = usb_role_switch_get_drvdata(sw);
++
++	data->usb_role = role;
++	queue_delayed_work(system_wq, &data->detect, 0);
++
++	return 0;
++}
++
++static enum usb_role sun4i_usb_role_get(struct usb_role_switch *sw)
++{
++	struct sun4i_usb_phy_data *data = usb_role_switch_get_drvdata(sw);
++	int role = sun4i_usb_phy0_get_id_det(data) ? USB_ROLE_DEVICE : USB_ROLE_HOST;
++
++	return data->usb_role >= 0 ? data->usb_role : role;
++}
++
+ static void sun4i_usb_phy_remove(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -709,6 +737,8 @@ static void sun4i_usb_phy_remove(struct platform_device *pdev)
+ 		devm_free_irq(dev, data->vbus_det_irq, data);
+ 
+ 	cancel_delayed_work_sync(&data->detect);
++
++	usb_role_switch_unregister(data->role_switch);
+ }
+ 
+ static const unsigned int sun4i_usb_phy0_cable[] = {
+@@ -736,6 +766,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 	if (!data->cfg)
+ 		return -EINVAL;
+ 
++	data->usb_role = -1;
++
+ 	data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
+ 	if (IS_ERR(data->base))
+ 		return PTR_ERR(data->base);
+@@ -896,6 +928,23 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		return PTR_ERR(phy_provider);
+ 	}
+ 
++	/* setup role switcher */
++	data->switch_desc.name = "usb0";
++	data->switch_desc.fwnode = dev_fwnode(dev);
++	data->switch_desc.set = sun4i_usb_role_set;
++	data->switch_desc.get = sun4i_usb_role_get;
++	data->switch_desc.driver_data = data;
++
++	/*
++	 * Don't interfere with the default behavior of this driver until
++	 * the consumer of the role switch uses the switch for the first time.
++	 */
++	data->role_switch = usb_role_switch_register(dev, &data->switch_desc);
++	if (IS_ERR(data->role_switch)) {
++		dev_warn(dev, "Unable to register Role Switch\n");
++		data->role_switch = NULL;
++	}
++
+ 	dev_dbg(dev, "successfully loaded\n");
+ 
+ 	return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
new file mode 100644
index 000000000000..30283346956c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
@@ -0,0 +1,31 @@
+From 878dfb3cc23912c4fb84a2304a78cfa2061b4b4d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 27 Feb 2020 00:53:17 +0100
+Subject: power: axp20x_battery: Allow to set target voltage to 4.35V
+
+Some devices have batteries that allow that.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 6ac5c80cfda2..f24520719a74 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -374,6 +374,11 @@ static int axp20x_battery_set_max_voltage(struct axp20x_batt_ps *axp20x_batt,
+ 		val = AXP20X_CHRG_CTRL1_TGT_4_2V;
+ 		break;
+ 
++	case 4350000:
++	case 4360000:
++		val = AXP20X_CHRG_CTRL1_TGT_4_36V;
++		break;
++
+ 	default:
+ 		/*
+ 		 * AXP20x max voltage can be set to 4.36V and AXP22X max voltage
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
new file mode 100644
index 000000000000..4d5a704a581a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
@@ -0,0 +1,43 @@
+From 040deb92ecfc48bf401aa9a5843d62b78c671052 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 14 Mar 2021 15:49:34 +0100
+Subject: power: axp803: Add interrupts for low battery power condition
+
+These are necessary so that the device is woken up by interrupt
+when low on battery, to handle the condition.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mfd/axp20x.c                  | 2 ++
+ drivers/power/supply/axp20x_battery.c | 2 ++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index 99d1723bc9c9..2a78fd64ffad 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -367,6 +367,8 @@ static const struct resource axp803_battery_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_HIGH_END, "BATT_ACT_TEMP_HIGH_END"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW, "BATT_ACT_TEMP_LOW"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW_END, "BATT_ACT_TEMP_LOW_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_LOW_PWR_LVL1, "BATT_LOW_PWR_LVL1"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_LOW_PWR_LVL2, "BATT_LOW_PWR_LVL2"),
+ };
+ 
+ static const struct resource axp803_pek_resources[] = {
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 97b11f05803e..b7b3e6b945dd 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -615,6 +615,8 @@ static const struct axp_irq_data axp813_irqs[] = {
+ 	{ "BATT_HEALTH_GOOD",		axp20x_battery_changed_irq },
+ 	{ "BATT_CHARGING",		axp20x_battery_changed_irq },
+ 	{ "BATT_CHARGING_DONE",		axp20x_battery_changed_irq },
++	{ "BATT_LOW_PWR_LVL1",		axp20x_battery_changed_irq },
++	{ "BATT_LOW_PWR_LVL2",		axp20x_battery_changed_irq },
+ 	{ "BATT_CHG_TEMP_HIGH",		axp20x_battery_temp_hot_irq },
+ 	{ "BATT_CHG_TEMP_HIGH_END",	axp20x_battery_temp_normal_irq },
+ 	{ "BATT_CHG_TEMP_LOW",		axp20x_battery_temp_cold_irq },
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
new file mode 100644
index 000000000000..d46aab514def
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
@@ -0,0 +1,45 @@
+From 1b287510a07d4a4bf773f3b7239f1b1143e47026 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 22 Jun 2020 02:28:01 +0200
+Subject: power: supply: Add support for USB_BC_ENABLED and
+ USB_DCP_INPUT_CURRENT_LIMIT
+
+- USB_BC_ENABLED - enabling/disabling BC 1.2 USB type detection
+- USB_DCP_INPUT_CURRENT_LIMIT - setting a default current limit for DCP/CDP
+                                ports
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/power_supply_sysfs.c | 2 ++
+ include/linux/power_supply.h              | 2 ++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c
+index b86e11bdc07e..5697a9873941 100644
+--- a/drivers/power/supply/power_supply_sysfs.c
++++ b/drivers/power/supply/power_supply_sysfs.c
+@@ -209,6 +209,8 @@ static struct power_supply_attr power_supply_attrs[] = {
+ 	POWER_SUPPLY_ATTR(TIME_TO_FULL_NOW),
+ 	POWER_SUPPLY_ATTR(TIME_TO_FULL_AVG),
+ 	POWER_SUPPLY_ENUM_ATTR(TYPE),
++	POWER_SUPPLY_ATTR(USB_BC_ENABLED),
++	POWER_SUPPLY_ATTR(USB_DCP_INPUT_CURRENT_LIMIT),
+ 	POWER_SUPPLY_ATTR(USB_TYPE),
+ 	POWER_SUPPLY_ENUM_ATTR(SCOPE),
+ 	POWER_SUPPLY_ATTR(PRECHARGE_CURRENT),
+diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
+index 8e5705a56b85..ae8dcc688cfa 100644
+--- a/include/linux/power_supply.h
++++ b/include/linux/power_supply.h
+@@ -162,6 +162,8 @@ enum power_supply_property {
+ 	POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
+ 	POWER_SUPPLY_PROP_TIME_TO_FULL_AVG,
+ 	POWER_SUPPLY_PROP_TYPE, /* use power_supply.type instead */
++	POWER_SUPPLY_PROP_USB_BC_ENABLED,
++	POWER_SUPPLY_PROP_USB_DCP_INPUT_CURRENT_LIMIT,
+ 	POWER_SUPPLY_PROP_USB_TYPE,
+ 	POWER_SUPPLY_PROP_SCOPE,
+ 	POWER_SUPPLY_PROP_PRECHARGE_CURRENT,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
new file mode 100644
index 000000000000..4650f4f12294
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
@@ -0,0 +1,75 @@
+From be7dbf28868b2d0990e75bd8a4cf361157a8ca0a Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 10 Nov 2022 20:05:58 +0100
+Subject: power: supply: axp20x-battery: Add support for
+ POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN
+
+Report total battery capacity.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 210be590691c..19b5f332fa75 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -85,6 +85,7 @@ struct axp20x_batt_ps {
+ 	/* Maximum constant charge current */
+ 	unsigned int max_ccc;
+ 	const struct axp_data	*data;
++	struct power_supply_battery_info *info;
+ };
+ 
+ static int axp20x_battery_get_max_voltage(struct axp20x_batt_ps *axp20x_batt,
+@@ -370,6 +371,16 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 		val->intval *= 1000;
+ 		break;
+ 
++	case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:
++		val->intval = 0;
++		if (axp20x_batt->info)
++			val->intval = axp20x_batt->info->energy_full_design_uwh;
++		return 0;
++
++	case POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN:
++		val->intval = 0;
++		return 0;
++
+ 	default:
+ 		return -EINVAL;
+ 	}
+@@ -563,6 +574,8 @@ static enum power_supply_property axp20x_battery_props[] = {
+ 	POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+ 	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+ 	POWER_SUPPLY_PROP_CAPACITY,
++	POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN,
++	POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN,
+ };
+ 
+ static int axp20x_battery_prop_writeable(struct power_supply *psy,
+@@ -704,7 +717,6 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
+ 	struct axp20x_batt_ps *axp20x_batt;
+ 	struct power_supply_config psy_cfg = {};
+-	struct power_supply_battery_info *info;
+ 	struct device *dev = &pdev->dev;
+ 	const struct axp_irq_data *irq_data;
+ 	int irq, ret;
+@@ -761,9 +773,9 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 
+ 	axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD;
+ 
+-	if (!power_supply_get_battery_info(axp20x_batt->batt, &info)) {
+-		int vmin = info->voltage_min_design_uv;
+-		int ccc = info->constant_charge_current_max_ua;
++	if (!power_supply_get_battery_info(axp20x_batt->batt, &axp20x_batt->info)) {
++		int vmin = axp20x_batt->info->voltage_min_design_uv;
++		int ccc = axp20x_batt->info->constant_charge_current_max_ua;
+ 
+ 		if (vmin > 0 && axp20x_set_voltage_min_design(axp20x_batt,
+ 							      vmin))
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
new file mode 100644
index 000000000000..377f3d4235e7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
@@ -0,0 +1,35 @@
+From fc52eda9a03de86b5b64a1fea2d1ff8fac060f44 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 27 Aug 2022 20:50:43 +0200
+Subject: power: supply: axp20x-battery: Enable poweron by RTC alarm
+
+For the Pinephone to be able to poweron on RTC alarm, some bits in
+PMIC need to be enabled. This will cause PMIC to be wakeable by
+SoC pulling the interrupt line low.
+
+This may need some coordination from a bootloader.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 4e084b83e7cf..210be590691c 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -856,6 +856,11 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 		ret = regmap_update_bits(axp20x_batt->regmap, 0x84, 0x37, 0x31);
+ 		if (ret)
+ 			goto warn_bat;
++
++		// enable poweron by RTC
++		ret = regmap_update_bits(axp20x_batt->regmap, 0x8f, BIT(7), BIT(7));
++		if (ret)
++			goto warn_bat;
+ 	}
+ 
+ 	return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
new file mode 100644
index 000000000000..d45d07614898
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
@@ -0,0 +1,86 @@
+From fe92da3ae7f46769732c2faa8dddb40e06ab83a8 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Apr 2022 02:50:14 +0200
+Subject: power: supply: axp20x-battery: Support
+ POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR
+
+Support force disabling the charger in a more standardized way.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 31 +++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index b7b3e6b945dd..4e084b83e7cf 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -227,6 +227,19 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 		val->intval = !!(reg & AXP20X_PWR_OP_BATT_PRESENT);
+ 		break;
+ 
++	case POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR:
++		ret = regmap_read(axp20x_batt->regmap, AXP20X_CHRG_CTRL1,
++				  &reg);
++		if (ret)
++			return ret;
++
++		if (reg & AXP20X_CHRG_CTRL1_ENABLE)
++			val->intval = POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO;
++		else
++			val->intval = POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE;
++
++		return 0;
++
+ 	case POWER_SUPPLY_PROP_STATUS:
+ 		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE,
+ 				  &reg);
+@@ -504,6 +517,21 @@ static int axp20x_battery_set_prop(struct power_supply *psy,
+ 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
+ 		return axp20x_set_max_constant_charge_current(axp20x_batt,
+ 							      val->intval);
++	case POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR:
++		switch (val->intval) {
++		case POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO:
++			return regmap_update_bits(axp20x_batt->regmap,
++						  AXP20X_CHRG_CTRL1,
++						  AXP20X_CHRG_CTRL1_ENABLE,
++						  AXP20X_CHRG_CTRL1_ENABLE);
++		case POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE:
++			return regmap_update_bits(axp20x_batt->regmap,
++						  AXP20X_CHRG_CTRL1,
++						  AXP20X_CHRG_CTRL1_ENABLE, 0);
++		default:
++			return -EINVAL;
++		}
++
+ 	case POWER_SUPPLY_PROP_STATUS:
+ 		switch (val->intval) {
+ 		case POWER_SUPPLY_STATUS_CHARGING:
+@@ -525,6 +553,7 @@ static enum power_supply_property axp20x_battery_props[] = {
+ 	POWER_SUPPLY_PROP_PRESENT,
+ 	POWER_SUPPLY_PROP_ONLINE,
+ 	POWER_SUPPLY_PROP_STATUS,
++	POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR,
+ 	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+ 	POWER_SUPPLY_PROP_CURRENT_NOW,
+ 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT,
+@@ -540,6 +569,7 @@ static int axp20x_battery_prop_writeable(struct power_supply *psy,
+ 					 enum power_supply_property psp)
+ {
+ 	return psp == POWER_SUPPLY_PROP_STATUS ||
++	       psp == POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR ||
+ 	       psp == POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN ||
+ 	       psp == POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN ||
+ 	       psp == POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT ||
+@@ -554,6 +584,7 @@ static const struct power_supply_desc axp20x_batt_ps_desc = {
+ 	.property_is_writeable = axp20x_battery_prop_writeable,
+ 	.get_property = axp20x_battery_get_prop,
+ 	.set_property = axp20x_battery_set_prop,
++	.charge_behaviours = BIT(POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO) | BIT(POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE),
+ };
+ 
+ static irqreturn_t axp20x_battery_changed_irq(int irq, void *devid)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
new file mode 100644
index 000000000000..e48563d8001e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
@@ -0,0 +1,59 @@
+From db11055646234e7d7d169ecf898398a12276cda5 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 15 Mar 2024 21:48:34 +0100
+Subject: power: supply: axp20x-usb-power: Add missing interrupts
+
+Notify power_supply_change on BC detection interrupts for the consumers
+to get BC results ASAP.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mfd/axp20x.c                    |  2 ++
+ drivers/power/supply/axp20x_usb_power.c | 11 +++++++++--
+ 2 files changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index 2a78fd64ffad..f5a47d63b1b7 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -321,6 +321,8 @@ static const struct resource axp22x_usb_power_supply_resources[] = {
+ static const struct resource axp803_usb_power_supply_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BC_USB_CHNG, "BC_USB_CHNG"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_MV_CHNG, "MV_CHNG"),
+ };
+ 
+ static const struct resource axp22x_pek_resources[] = {
+diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
+index e31f08cef861..b10ccf280451 100644
+--- a/drivers/power/supply/axp20x_usb_power.c
++++ b/drivers/power/supply/axp20x_usb_power.c
+@@ -463,6 +463,13 @@ static const char * const axp22x_irq_names[] = {
+ 	"VBUS_REMOVAL",
+ };
+ 
++static const char * const axp813_irq_names[] = {
++	"VBUS_PLUGIN",
++	"VBUS_REMOVAL",
++	"BC_USB_CHNG",
++	"MV_CHNG",
++};
++
+ static int axp192_usb_curr_lim_table[] = {
+ 	-1,
+ 	-1,
+@@ -540,8 +547,8 @@ static const struct axp_data axp223_data = {
+ 
+ static const struct axp_data axp813_data = {
+ 	.power_desc	= &axp813_usb_power_desc,
+-	.irq_names	= axp22x_irq_names,
+-	.num_irq_names	= ARRAY_SIZE(axp22x_irq_names),
++	.irq_names	= axp813_irq_names,
++	.num_irq_names	= ARRAY_SIZE(axp813_irq_names),
+ 	.curr_lim_table = axp813_usb_curr_lim_table,
+ 	.curr_lim_table_size = ARRAY_SIZE(axp813_usb_curr_lim_table),
+ 	.curr_lim_fld	= REG_FIELD(AXP22X_CHRG_CTRL3, 4, 7),
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
new file mode 100644
index 000000000000..4e70da78b3de
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
@@ -0,0 +1,38 @@
+From 8e6f521c31ea0372c4fe3c956d27d9b27fe84883 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 14 Dec 2020 07:42:08 +0100
+Subject: power: supply: axp20x-usb-power: Change Vbus hold voltage to 4.5V
+
+This fixes USB-PD charger resets.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_usb_power.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
+index dae7e5cfc54e..e31f08cef861 100644
+--- a/drivers/power/supply/axp20x_usb_power.c
++++ b/drivers/power/supply/axp20x_usb_power.c
+@@ -733,6 +733,18 @@ static int axp20x_usb_power_probe(struct platform_device *pdev)
+ 			return ret;
+ 	}
+ 
++	/*TODO: Re-work this into a supply property with OF based default value */
++	if (of_machine_is_compatible("pine64,pinephone-1.2") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.1") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.0") > 0) {
++
++		dev_info(&pdev->dev, "Increasing Vbus hold voltage to 4.5V\n");
++
++		ret = regmap_update_bits(axp20x->regmap, 0x30, 0x7 << 3, 0x5 << 3);
++		if (ret)
++			return ret;
++	}
++
+ 	psy_cfg.of_node = pdev->dev.of_node;
+ 	psy_cfg.drv_data = power;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
new file mode 100644
index 000000000000..d2406d2a0eca
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
@@ -0,0 +1,63 @@
+From b3afbce62eca4e4a025884cae9543321f8066d15 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 28 Feb 2020 19:16:46 +0100
+Subject: power: supply: axp20x_battery: Add support for reporting OCV
+
+Export OCV reported by PMIC via sysfs.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index f24520719a74..bad981c349ff 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -180,6 +180,25 @@ static int axp20x_get_constant_charge_current(struct axp20x_batt_ps *axp,
+ 	return 0;
+ }
+ 
++static int axp20x_get_ocv_voltage(struct axp20x_batt_ps *axp, int *val)
++{
++	int ret;
++	unsigned int ocvh, ocvl, ocv;
++
++	ret = regmap_read(axp->regmap, AXP288_FG_OCVH_REG, &ocvh);
++	if (ret)
++		return ret;
++
++	ret = regmap_read(axp->regmap, AXP288_FG_OCVL_REG, &ocvl);
++	if (ret)
++		return ret;
++
++	ocv = ocvh << 4 | (ocvl & 0xf);
++
++	*val = ocv * 1100;
++	return 0;
++}
++
+ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 				   enum power_supply_property psp,
+ 				   union power_supply_propval *val)
+@@ -277,6 +296,9 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 		val->intval *= 1000;
+ 		break;
+ 
++	case POWER_SUPPLY_PROP_VOLTAGE_OCV:
++		return axp20x_get_ocv_voltage(axp20x_batt, &val->intval);
++
+ 	case POWER_SUPPLY_PROP_CAPACITY:
+ 		/* When no battery is present, return capacity is 100% */
+ 		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE,
+@@ -498,6 +520,7 @@ static enum power_supply_property axp20x_battery_props[] = {
+ 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT,
+ 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX,
+ 	POWER_SUPPLY_PROP_HEALTH,
++	POWER_SUPPLY_PROP_VOLTAGE_OCV,
+ 	POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+ 	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+ 	POWER_SUPPLY_PROP_CAPACITY,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
new file mode 100644
index 000000000000..afe6ea7f4144
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
@@ -0,0 +1,40 @@
+From a12ea6318d380c682943cd162e5bdd545c35e5c5 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 00:55:09 -0600
+Subject: power: supply: axp20x_battery: Fix charging done detection
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/supply/axp20x_battery.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 5aed07bbc716..75c835e20347 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -33,6 +33,7 @@
+ 
+ #define AXP20X_PWR_STATUS_BAT_CHARGING	BIT(2)
+ 
++#define AXP20X_PWR_OP_BATT_CHARGING	BIT(6)
+ #define AXP20X_PWR_OP_BATT_PRESENT	BIT(5)
+ #define AXP20X_PWR_OP_BATT_ACTIVATED	BIT(3)
+ 
+@@ -218,12 +219,12 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 		break;
+ 
+ 	case POWER_SUPPLY_PROP_STATUS:
+-		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_INPUT_STATUS,
++		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE,
+ 				  &reg);
+ 		if (ret)
+ 			return ret;
+ 
+-		if (reg & AXP20X_PWR_STATUS_BAT_CHARGING) {
++		if (reg & AXP20X_PWR_OP_BATT_CHARGING) {
+ 			val->intval = POWER_SUPPLY_STATUS_CHARGING;
+ 			return 0;
+ 		}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
new file mode 100644
index 000000000000..a90f9e6cccca
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
@@ -0,0 +1,117 @@
+From e6f8ca76530223ebe07f0c936dcc56079f36f80c Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 01:04:33 -0600
+Subject: power: supply: axp20x_battery: Monitor battery health
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/supply/axp20x_battery.c | 58 ++++++++++++++++++++++++++-
+ 1 file changed, 56 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index a9e577768c90..97b11f05803e 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -81,6 +81,7 @@ struct axp20x_batt_ps {
+ 	struct iio_channel *batt_chrg_i;
+ 	struct iio_channel *batt_dischrg_i;
+ 	struct iio_channel *batt_v;
++	int health;
+ 	/* Maximum constant charge current */
+ 	unsigned int max_ccc;
+ 	const struct axp_data	*data;
+@@ -272,7 +273,7 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 			return 0;
+ 		}
+ 
+-		val->intval = POWER_SUPPLY_HEALTH_GOOD;
++		val->intval = axp20x_batt->health;
+ 		break;
+ 
+ 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
+@@ -564,6 +565,39 @@ static irqreturn_t axp20x_battery_changed_irq(int irq, void *devid)
+ 	return IRQ_HANDLED;
+ }
+ 
++static irqreturn_t axp20x_battery_temp_cold_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_COLD;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t axp20x_battery_temp_hot_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_OVERHEAT;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t axp20x_battery_temp_normal_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
+ static const struct axp_irq_data axp20x_irqs[] = {
+ 	{ "BATT_PLUGIN",		axp20x_battery_changed_irq },
+ 	{ "BATT_REMOVAL",		axp20x_battery_changed_irq },
+@@ -574,6 +608,24 @@ static const struct axp_irq_data axp20x_irqs[] = {
+ 	{}
+ };
+ 
++static const struct axp_irq_data axp813_irqs[] = {
++	{ "BATT_PLUGIN",		axp20x_battery_changed_irq },
++	{ "BATT_REMOVAL",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_DEAD",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_GOOD",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING_DONE",		axp20x_battery_changed_irq },
++	{ "BATT_CHG_TEMP_HIGH",		axp20x_battery_temp_hot_irq },
++	{ "BATT_CHG_TEMP_HIGH_END",	axp20x_battery_temp_normal_irq },
++	{ "BATT_CHG_TEMP_LOW",		axp20x_battery_temp_cold_irq },
++	{ "BATT_CHG_TEMP_LOW_END",	axp20x_battery_temp_normal_irq },
++	{ "BATT_ACT_TEMP_HIGH",		axp20x_battery_temp_hot_irq },
++	{ "BATT_ACT_TEMP_HIGH_END",	axp20x_battery_temp_normal_irq },
++	{ "BATT_ACT_TEMP_LOW",		axp20x_battery_temp_cold_irq },
++	{ "BATT_ACT_TEMP_LOW_END",	axp20x_battery_temp_normal_irq },
++	{}
++};
++
+ static const struct axp_data axp209_data = {
+ 	.ccc_scale = 100000,
+ 	.ccc_offset = 300000,
+@@ -597,7 +649,7 @@ static const struct axp_data axp813_data = {
+ 	.has_fg_valid = true,
+ 	.get_max_voltage = axp813_battery_get_max_voltage,
+ 	.set_max_voltage = axp20x_battery_set_max_voltage,
+-	.irqs = axp20x_irqs,
++	.irqs = axp813_irqs,
+ };
+ 
+ static const struct of_device_id axp20x_battery_ps_id[] = {
+@@ -674,6 +726,8 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 		return PTR_ERR(axp20x_batt->batt);
+ 	}
+ 
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD;
++
+ 	if (!power_supply_get_battery_info(axp20x_batt->batt, &info)) {
+ 		int vmin = info->voltage_min_design_uv;
+ 		int ccc = info->constant_charge_current_max_ua;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
new file mode 100644
index 000000000000..2d78cb0dba8a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
@@ -0,0 +1,138 @@
+From 897ad03a2fb3cb7e2e8f14540c796e5348654c8a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 01:04:17 -0600
+Subject: power: supply: axp20x_battery: Send uevents for status changes
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/supply/axp20x_battery.c | 55 ++++++++++++++++++++++++++-
+ 1 file changed, 53 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 75c835e20347..a9e577768c90 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -56,14 +56,22 @@
+ 
+ #define AXP20X_V_OFF_MASK		GENMASK(2, 0)
+ 
++#define DRVNAME "axp20x-battery-power-supply"
++
+ struct axp20x_batt_ps;
+ 
++struct axp_irq_data {
++	const char *name;
++	irq_handler_t handler;
++};
++
+ struct axp_data {
+ 	int	ccc_scale;
+ 	int	ccc_offset;
+ 	bool	has_fg_valid;
+ 	int	(*get_max_voltage)(struct axp20x_batt_ps *batt, int *val);
+ 	int	(*set_max_voltage)(struct axp20x_batt_ps *batt, int val);
++	const struct axp_irq_data *irqs;
+ };
+ 
+ struct axp20x_batt_ps {
+@@ -547,11 +555,31 @@ static const struct power_supply_desc axp20x_batt_ps_desc = {
+ 	.set_property = axp20x_battery_set_prop,
+ };
+ 
++static irqreturn_t axp20x_battery_changed_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
++static const struct axp_irq_data axp20x_irqs[] = {
++	{ "BATT_PLUGIN",		axp20x_battery_changed_irq },
++	{ "BATT_REMOVAL",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_DEAD",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_GOOD",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING_DONE",		axp20x_battery_changed_irq },
++	{}
++};
++
+ static const struct axp_data axp209_data = {
+ 	.ccc_scale = 100000,
+ 	.ccc_offset = 300000,
+ 	.get_max_voltage = axp20x_battery_get_max_voltage,
+ 	.set_max_voltage = axp20x_battery_set_max_voltage,
++	.irqs = axp20x_irqs,
+ };
+ 
+ static const struct axp_data axp221_data = {
+@@ -560,6 +588,7 @@ static const struct axp_data axp221_data = {
+ 	.has_fg_valid = true,
+ 	.get_max_voltage = axp22x_battery_get_max_voltage,
+ 	.set_max_voltage = axp22x_battery_set_max_voltage,
++	.irqs = axp20x_irqs,
+ };
+ 
+ static const struct axp_data axp813_data = {
+@@ -568,6 +597,7 @@ static const struct axp_data axp813_data = {
+ 	.has_fg_valid = true,
+ 	.get_max_voltage = axp813_battery_get_max_voltage,
+ 	.set_max_voltage = axp20x_battery_set_max_voltage,
++	.irqs = axp20x_irqs,
+ };
+ 
+ static const struct of_device_id axp20x_battery_ps_id[] = {
+@@ -586,11 +616,13 @@ MODULE_DEVICE_TABLE(of, axp20x_battery_ps_id);
+ 
+ static int axp20x_power_probe(struct platform_device *pdev)
+ {
++	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
+ 	struct axp20x_batt_ps *axp20x_batt;
+ 	struct power_supply_config psy_cfg = {};
+ 	struct power_supply_battery_info *info;
+ 	struct device *dev = &pdev->dev;
+-	int ret;
++	const struct axp_irq_data *irq_data;
++	int irq, ret;
+ 
+ 	if (!of_device_is_available(pdev->dev.of_node))
+ 		return -ENODEV;
+@@ -664,6 +696,25 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 		}
+ 	}
+ 
++	/* Request irqs after registering, as irqs may trigger immediately */
++	for (irq_data = axp20x_batt->data->irqs; irq_data->name; irq_data++) {
++		irq = platform_get_irq_byname(pdev, irq_data->name);
++		if (irq < 0) {
++			dev_err(&pdev->dev, "No IRQ for %s: %d\n",
++				irq_data->name, irq);
++			return irq;
++		}
++		irq = regmap_irq_get_virq(axp20x->regmap_irqc, irq);
++		ret = devm_request_any_context_irq(&pdev->dev, irq,
++						   irq_data->handler, 0,
++						   DRVNAME, axp20x_batt);
++		if (ret < 0) {
++			dev_err(&pdev->dev, "Error requesting %s IRQ: %d\n",
++				irq_data->name, ret);
++			return ret;
++		}
++	}
++
+ 	/*
+ 	 * Update max CCC to a valid value if battery info is present or set it
+ 	 * to current register value by default.
+@@ -730,7 +781,7 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ static struct platform_driver axp20x_batt_driver = {
+ 	.probe    = axp20x_power_probe,
+ 	.driver   = {
+-		.name  = "axp20x-battery-power-supply",
++		.name		= DRVNAME,
+ 		.of_match_table = axp20x_battery_ps_id,
+ 	},
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
new file mode 100644
index 000000000000..cd9cb9ef17f3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
@@ -0,0 +1,90 @@
+From 3a858c118a51eefb96fde6becbaffd0675f208a7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Sep 2020 14:59:41 +0200
+Subject: power: supply: axp20x_battery: Setup thermal regulation
+ (experimental)
+
+Values for NTC resistances were pulled out of thin air!
+
+None of this is tested to actually work.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 54 +++++++++++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index bad981c349ff..5aed07bbc716 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -589,6 +589,7 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 	struct power_supply_config psy_cfg = {};
+ 	struct power_supply_battery_info *info;
+ 	struct device *dev = &pdev->dev;
++	int ret;
+ 
+ 	if (!of_device_is_available(pdev->dev.of_node))
+ 		return -ENODEV;
+@@ -669,6 +670,59 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 	axp20x_get_constant_charge_current(axp20x_batt,
+ 					   &axp20x_batt->max_ccc);
+ 
++	if (of_machine_is_compatible("pine64,pinephone-1.2") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.1") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.0") > 0) {
++		// 3kOhm NTC inside PinePhone batery
++		// ---------------------------------
++		//
++		// Charging:
++		//  0 - 15 °C: Max 0.2C CC to 4.35V : 9750 Ohm - 4710 Ohm
++		// 15 - 50 °C: Max 0.5C CC to 4.35V : 4710 Ohm - 1080 Ohm
++		//
++		// Discharging:
++		// -10 °C : 16500 Ohm
++		//  55 °C : 896 Ohm
++		// enable TS pin input to ADC
++
++		dev_info(dev, "Configuring battery thermal regulation for Pinephone\n");
++
++		ret = regmap_update_bits(axp20x_batt->regmap, 0x82, BIT(0), BIT(0));
++		if (ret)
++			goto warn_bat;
++
++		// safety thresholds:
++
++		// voltage = reg_val * 12800 uV (range is 0 - 3.264V)
++		ret = regmap_write(axp20x_batt->regmap, 0x38,  9750 * 80 / 12800); // V_LTF-charge
++		if (ret)
++			goto warn_bat;
++
++		ret = regmap_write(axp20x_batt->regmap, 0x39,  1080 * 80 / 12800); // V_HTF-charge
++		if (ret)
++			goto warn_bat;
++
++		ret = regmap_write(axp20x_batt->regmap, 0x3c, 16500 * 80 / 12800); // V_LTF-work
++		if (ret)
++			goto warn_bat;
++
++		ret = regmap_write(axp20x_batt->regmap, 0x3d,   896 * 80 / 12800); // V_HTF-work
++		if (ret)
++			goto warn_bat;
++
++		// There is a hysteresis of 460.8 mV(refer to TS pin voltage) for UTP
++		// threshold, and there is a hysteresis of 57.6 mV for OTP threshold.
++
++		// use TS pin only when charging, make it affect the charger, I = 80uA
++		ret = regmap_update_bits(axp20x_batt->regmap, 0x84, 0x37, 0x31);
++		if (ret)
++			goto warn_bat;
++	}
++
++	return 0;
++
++warn_bat:
++	dev_err(dev, "Failed to configure battery thermal regulation\n");
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch
new file mode 100644
index 000000000000..da8abf340e9d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch
@@ -0,0 +1,194 @@
+From c38d412239283fcda328704ca6b0b852a8c639b1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 5 Oct 2019 15:10:11 +0200
+Subject: regulator: Add simple driver for enabling a regulator from userspace
+
+This is just like userspace-consumer, but can be used from device
+tree.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/Kconfig                 |   9 ++
+ drivers/regulator/Makefile                |   1 +
+ drivers/regulator/userspace-consumer-of.c | 137 ++++++++++++++++++++++
+ 3 files changed, 147 insertions(+)
+ create mode 100644 drivers/regulator/userspace-consumer-of.c
+
+diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
+index d333be2bea3b..0ec7f70d74d0 100644
+--- a/drivers/regulator/Kconfig
++++ b/drivers/regulator/Kconfig
+@@ -66,6 +66,15 @@ config REGULATOR_NETLINK_EVENTS
+ 
+ 	  If unsure, say no.
+ 
++config REGULATOR_USERSPACE_CONSUMER_OF
++	tristate "Userspace regulator consumer support (OF)"
++	help
++	  There are some classes of devices that are controlled entirely
++	  from user space. Userspace consumer driver provides ability to
++	  control power supplies for such devices.
++
++	  If unsure, say no.
++
+ config REGULATOR_88PG86X
+ 	tristate "Marvell 88PG86X voltage regulators"
+ 	depends on I2C
+diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
+index ba15fa5f30ad..0f5df4aff8e5 100644
+--- a/drivers/regulator/Makefile
++++ b/drivers/regulator/Makefile
+@@ -10,6 +10,7 @@ obj-$(CONFIG_OF) += of_regulator.o
+ obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o
+ obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o
+ obj-$(CONFIG_REGULATOR_USERSPACE_CONSUMER) += userspace-consumer.o
++obj-$(CONFIG_REGULATOR_USERSPACE_CONSUMER_OF) += userspace-consumer-of.o
+ 
+ obj-$(CONFIG_REGULATOR_88PG86X) += 88pg86x.o
+ obj-$(CONFIG_REGULATOR_88PM800) += 88pm800-regulator.o
+diff --git a/drivers/regulator/userspace-consumer-of.c b/drivers/regulator/userspace-consumer-of.c
+new file mode 100644
+index 000000000000..5b835af17bea
+--- /dev/null
++++ b/drivers/regulator/userspace-consumer-of.c
+@@ -0,0 +1,137 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++
++#include <linux/err.h>
++#include <linux/mutex.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++
++struct userspace_consumer_data {
++	struct mutex lock;
++	bool enabled;
++	struct regulator *supply;
++};
++
++static ssize_t reg_show_state(struct device *dev,
++			  struct device_attribute *attr, char *buf)
++{
++	struct userspace_consumer_data *data = dev_get_drvdata(dev);
++
++	if (data->enabled)
++		return sprintf(buf, "enabled\n");
++
++	return sprintf(buf, "disabled\n");
++}
++
++static ssize_t reg_set_state(struct device *dev, struct device_attribute *attr,
++			 const char *buf, size_t count)
++{
++	struct userspace_consumer_data *data = dev_get_drvdata(dev);
++	bool enabled;
++	int ret;
++
++	/*
++	 * sysfs_streq() doesn't need the \n's, but we add them so the strings
++	 * will be shared with show_state(), above.
++	 */
++	if (sysfs_streq(buf, "enabled\n") || sysfs_streq(buf, "1"))
++		enabled = true;
++	else if (sysfs_streq(buf, "disabled\n") || sysfs_streq(buf, "0"))
++		enabled = false;
++	else {
++		dev_err(dev, "Configuring invalid mode\n");
++		return count;
++	}
++
++	mutex_lock(&data->lock);
++	if (enabled != data->enabled) {
++		if (enabled)
++			ret = regulator_enable(data->supply);
++		else
++			ret = regulator_disable(data->supply);
++
++		if (ret == 0)
++			data->enabled = enabled;
++		else
++			dev_err(dev, "Failed to configure state: %d\n", ret);
++	}
++	mutex_unlock(&data->lock);
++
++	return count;
++}
++
++static DEVICE_ATTR(state, 0644, reg_show_state, reg_set_state);
++
++static struct attribute *attributes[] = {
++	&dev_attr_state.attr,
++	NULL,
++};
++
++static const struct attribute_group attr_group = {
++	.attrs	= attributes,
++};
++
++static int regulator_userspace_consumer_probe(struct platform_device *pdev)
++{
++	struct userspace_consumer_data *drvdata;
++	int ret;
++
++	drvdata = devm_kzalloc(&pdev->dev,
++			       sizeof(struct userspace_consumer_data),
++			       GFP_KERNEL);
++	if (drvdata == NULL)
++		return -ENOMEM;
++
++	mutex_init(&drvdata->lock);
++
++	drvdata->supply = devm_regulator_get(&pdev->dev, "controlled");
++	if (IS_ERR(drvdata->supply)) {
++		ret = PTR_ERR(drvdata->supply);
++		if (ret != -EPROBE_DEFER)
++			dev_err(&pdev->dev, "Failed to get supply: %d\n", ret);
++		return ret;
++	}
++
++	ret = sysfs_create_group(&pdev->dev.kobj, &attr_group);
++	if (ret != 0)
++		return ret;
++
++	platform_set_drvdata(pdev, drvdata);
++
++	return 0;
++}
++
++static int regulator_userspace_consumer_remove(struct platform_device *pdev)
++{
++	struct userspace_consumer_data *data = platform_get_drvdata(pdev);
++
++	sysfs_remove_group(&pdev->dev.kobj, &attr_group);
++
++	if (data->enabled)
++		regulator_disable(data->supply);
++
++	return 0;
++}
++
++static const struct of_device_id ids_of_match[] = {
++	{ .compatible = "custom,reg-userspace-consumer", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ids_of_match);
++
++static struct platform_driver regulator_userspace_consumer_driver = {
++	.probe		= regulator_userspace_consumer_probe,
++	.remove		= regulator_userspace_consumer_remove,
++	.driver		= {
++		.name		= "reg-userspace-consumer-of",
++		.of_match_table = of_match_ptr(ids_of_match),
++	},
++};
++
++module_platform_driver(regulator_userspace_consumer_driver);
++
++MODULE_AUTHOR("Mike Rapoport <mike@compulab.co.il>");
++MODULE_DESCRIPTION("Userspace consumer for voltage and current regulators");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
new file mode 100644
index 000000000000..6616ca707c81
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
@@ -0,0 +1,61 @@
+From 25ff2a2acd883d0a6ef561bba6f8ead12603b045 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 8 Jun 2020 00:15:04 +0200
+Subject: regulator: axp20x: Add support for vin-supply for drivevbus
+
+When drivevbus is used to control some regulator via the N_VBUSEN
+pin of the PMIC, this regulator may have a source supply. Allow to
+specify the supply using the vin-supply property.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/axp20x-regulator.c | 30 +++++++++++++++++++++++++---
+ 1 file changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index f3c447ecdc3b..7af0f1bf83cd 100644
+--- a/drivers/regulator/axp20x-regulator.c
++++ b/drivers/regulator/axp20x-regulator.c
+@@ -1707,12 +1707,36 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	if (drivevbus) {
++		struct regulator_desc *new_desc;
++		bool drivevbus_vin = false;
++		struct device_node *nr, *nd;
++
++		nr = of_get_child_by_name(pdev->dev.parent->of_node, "regulators");
++		if (nr) {
++			nd = of_get_child_by_name(nr, "drivevbus");
++			if (nd) {
++				drivevbus_vin = !!of_find_property(nd, "vin-supply", NULL);
++				of_node_put(nd);
++			}
++
++			of_node_put(nr);
++		}
++
++		new_desc = devm_kzalloc(&pdev->dev, sizeof(*new_desc), GFP_KERNEL);
++		if (!new_desc)
++			return -ENOMEM;
++
++		*new_desc = axp22x_drivevbus_regulator;
++
++		if (drivevbus_vin) {
++			new_desc->supply_name = "vin";
++			dev_info(&pdev->dev, "drivevbus has vin\n");
++		}
++
+ 		/* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
+ 		regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
+ 				   AXP22X_MISC_N_VBUSEN_FUNC, 0);
+-		rdev = devm_regulator_register(&pdev->dev,
+-					       &axp22x_drivevbus_regulator,
+-					       &config);
++		rdev = devm_regulator_register(&pdev->dev, new_desc, &config);
+ 		if (IS_ERR(rdev)) {
+ 			dev_err(&pdev->dev, "Failed to register drivevbus\n");
+ 			return PTR_ERR(rdev);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
new file mode 100644
index 000000000000..158629e16a99
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
@@ -0,0 +1,41 @@
+From 7d4fc86c4656152b0f7ad2a648ea57f2c3b0f179 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 18 Feb 2020 23:57:20 +0100
+Subject: regulator: axp20x: Enable over-temperature protection and 16s reset
+ function
+
+Why not? Also why here, but whatever.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/axp20x-regulator.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index 59474b74ccff..bb6cb4125714 100644
+--- a/drivers/regulator/axp20x-regulator.c
++++ b/drivers/regulator/axp20x-regulator.c
+@@ -92,6 +92,8 @@
+ #define AXP22X_WORKMODE_DCDCX_MASK(x)	BIT_MASK(x)
+ 
+ #define AXP22X_MISC_N_VBUSEN_FUNC	BIT(4)
++#define AXP22X_MISC_16S_RESET_FUNC	BIT(3)
++#define AXP22X_MISC_OTP			BIT(2)
+ 
+ #define AXP22X_DCDC1_V_OUT_MASK		GENMASK(4, 0)
+ #define AXP22X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
+@@ -1751,6 +1753,11 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
+ 		}
+ 	}
+ 
++	// enable 16s power-on reset and over-temperature protection
++	regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
++			   AXP22X_MISC_16S_RESET_FUNC | AXP22X_MISC_OTP,
++			   AXP22X_MISC_16S_RESET_FUNC | AXP22X_MISC_OTP);
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
new file mode 100644
index 000000000000..20380dd659d3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
@@ -0,0 +1,53 @@
+From 17a5123cd76af3ab9b8a2ae81790a3a7c36a0cc1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 9 Jun 2020 22:00:36 +0200
+Subject: regulator: axp20x: Turn N_VBUSEN to input on x-powers,sense-vbus-en
+
+When x-powers,sense-vbus-en is present on the PMIC DT node, force
+the N_VBUSEN to be an input. This is necessary on boards that
+have N_VBUSEN connected to VBUS enabling switch to make PMIC
+not charge when the board is generating VBUS voltage itself.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 4 ++++
+ drivers/regulator/axp20x-regulator.c                      | 8 ++++++++
+ 2 files changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index c4e3547e02e9..ec4927dfe9dc 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -15,6 +15,10 @@ wifi_pwrseq: wifi-pwrseq {
+ 	};
+ };
+ 
++&axp803 {
++	x-powers,sense-vbus-en;
++};
++
+ &backlight {
+ 	power-supply = <&reg_ldo_io0>;
+ 	lth-brightness = <10>;
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index 7af0f1bf83cd..59474b74ccff 100644
+--- a/drivers/regulator/axp20x-regulator.c
++++ b/drivers/regulator/axp20x-regulator.c
+@@ -1706,6 +1706,14 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
+ 						&aldo1_name);
+ 	}
+ 
++	if (!drivevbus &&
++	    of_property_read_bool(pdev->dev.parent->of_node, "x-powers,sense-vbus-en")) {
++		/* make N_VBUSEN an input */
++		regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
++				   AXP22X_MISC_N_VBUSEN_FUNC,
++				   AXP22X_MISC_N_VBUSEN_FUNC);
++	}
++
+ 	if (drivevbus) {
+ 		struct regulator_desc *new_desc;
+ 		bool drivevbus_vin = false;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch
new file mode 100644
index 000000000000..bd469917d7de
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch
@@ -0,0 +1,235 @@
+From 7527e12095b521492e4c710a43c5b5b152a4c6ce Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 17 Oct 2019 23:23:17 +0200
+Subject: regulator: tp65185: Add hwmon device for reading temperature
+
+Temperature for the display waveforms compensation is read
+via a special NTC measurement hardware inside the tp65185x.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/tp65185x.c | 134 +++++++++++++++++++++++++++++++++--
+ 1 file changed, 127 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/regulator/tp65185x.c b/drivers/regulator/tp65185x.c
+index 8b57a11ff2f9..08245b50e334 100644
+--- a/drivers/regulator/tp65185x.c
++++ b/drivers/regulator/tp65185x.c
+@@ -7,10 +7,12 @@
+ #include <linux/err.h>
+ #include <linux/i2c.h>
+ #include <linux/module.h>
++#include <linux/mutex.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/driver.h>
+ #include <linux/regulator/of_regulator.h>
+ #include <linux/gpio/consumer.h>
++#include <linux/hwmon.h>
+ #include <linux/delay.h>
+ 
+ #define REG_TMST_VALUE    0x00
+@@ -31,6 +33,9 @@
+ #define REG_PG            0x0F
+ #define REG_REVID         0x10
+ 
++#define REG_TMST1_READ_THERM	0x80
++#define REG_TMST1_CONV_END	0x20
++
+ struct tp65185x {
+ 	struct device* dev;
+ 	struct gpio_desc* wakeup_gpio;
+@@ -39,6 +44,8 @@ struct tp65185x {
+ 	struct gpio_desc* powergood_gpio;
+ 	struct regmap *regmap;
+ 	bool is_enabled;
++	struct mutex wakeup_mutex;
++	int wake_refs;
+ 	int vcom;
+ };
+ 
+@@ -192,6 +199,30 @@ static int wait_for_power_good(struct tp65185x *tp)
+ 	return -ETIMEDOUT;
+ }
+ 
++static void wakeup_regulator(struct tp65185x *tp, int wake)
++{
++	mutex_lock(&tp->wakeup_mutex);
++
++	if (wake) {
++		tp->wake_refs++;
++		if (tp->wake_refs > 1)
++			goto out_unlock;
++
++		gpiod_set_value(tp->wakeup_gpio, 1);
++		usleep_range(3000, 4000);
++	} else {
++		tp->wake_refs--;
++		if (tp->wake_refs > 0)
++			goto out_unlock;
++
++		gpiod_set_value(tp->wakeup_gpio, 0);
++		usleep_range(100, 200);
++	}
++
++out_unlock:
++	mutex_unlock(&tp->wakeup_mutex);
++}
++
+ static int enable_supply(struct regulator_dev *rdev)
+ {
+ 	struct tp65185x* tp = rdev_get_drvdata(rdev);
+@@ -200,9 +231,7 @@ static int enable_supply(struct regulator_dev *rdev)
+ 	if (tp->is_enabled)
+ 		return 0;
+ 
+-	// wake up the regulator
+-	gpiod_set_value(tp->wakeup_gpio, 1);
+-	usleep_range(3000, 4000);
++	wakeup_regulator(tp, 1);
+ 
+ 	ret = apply_voltage(tp, tp->vcom);
+ 	if (ret) {
+@@ -247,7 +276,7 @@ static int enable_supply(struct regulator_dev *rdev)
+ 	usleep_range(2000, 3000);
+ 	gpiod_set_value(tp->powerup_gpio, 0);
+ 	msleep(100);
+-	gpiod_set_value(tp->wakeup_gpio, 0);
++	wakeup_regulator(tp, 0);
+ 	return ret;
+ }
+ 
+@@ -273,7 +302,7 @@ static int disable_supply(struct regulator_dev *rdev)
+ 	show_power_status(tp, "power down");
+ 
+ 	// this will power down the V3P3 switch too
+-	gpiod_set_value(tp->wakeup_gpio, 0);
++	wakeup_regulator(tp, 0);
+ 
+ 	tp->is_enabled = false;
+ 
+@@ -309,8 +338,85 @@ static const struct regulator_desc tp65185x_reg = {
+ 	.owner = THIS_MODULE,
+ };
+ 
+-static int tp65185x_i2c_probe(struct i2c_client *i2c,
+-			      const struct i2c_device_id *id)
++static int tp65185x_ntc_read_temperature(struct tp65185x* tp, long *val)
++{
++	int ret;
++	unsigned int reg;
++
++	wakeup_regulator(tp, 1);
++
++	ret = regmap_update_bits(tp->regmap, REG_TMST1,
++				 REG_TMST1_READ_THERM,
++				 REG_TMST1_READ_THERM);
++	if (ret)
++		goto err_sleep;
++
++	ret = regmap_read_poll_timeout(tp->regmap, REG_TMST1, reg,
++				       reg & REG_TMST1_CONV_END,
++				       2000, 100000);
++	if (ret)
++		goto err_sleep;
++
++	ret = regmap_read(tp->regmap, REG_TMST_VALUE, &reg);
++	if (ret)
++		goto err_sleep;
++
++	*val = (s8)(u8)reg;
++
++err_sleep:
++	wakeup_regulator(tp, 0);
++	return ret;
++}
++
++static int tp65185x_ntc_read(struct device *dev, enum hwmon_sensor_types type,
++			     u32 attr, int channel, long *val)
++{
++	struct tp65185x *tp = dev_get_drvdata(dev);
++
++	if (type == hwmon_temp && attr == hwmon_temp_input) {
++		return tp65185x_ntc_read_temperature(tp, val);
++	} else if (type == hwmon_temp && attr == hwmon_temp_type) {
++		*val = 4;
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
++static umode_t tp65185x_ntc_is_visible(const void *data,
++				       enum hwmon_sensor_types type,
++				       u32 attr, int channel)
++{
++	if (type == hwmon_temp) {
++		switch (attr) {
++		case hwmon_temp_input:
++		case hwmon_temp_type:
++			return 0444;
++		default:
++			break;
++		}
++	}
++
++	return 0;
++}
++
++static const struct hwmon_channel_info *tp65185x_ntc_info[] = {
++	HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
++	HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_TYPE),
++	NULL
++};
++
++static const struct hwmon_ops tp65185x_ntc_hwmon_ops = {
++	.is_visible = tp65185x_ntc_is_visible,
++	.read = tp65185x_ntc_read,
++};
++
++static const struct hwmon_chip_info tp65185x_ntc_chip_info = {
++	.ops = &tp65185x_ntc_hwmon_ops,
++	.info = tp65185x_ntc_info,
++};
++
++static int tp65185x_i2c_probe(struct i2c_client *i2c)
+ {
+ 	struct device *dev = &i2c->dev;
+ 	struct regulator_dev *rdev;
+@@ -318,6 +424,7 @@ static int tp65185x_i2c_probe(struct i2c_client *i2c,
+ 	unsigned int reg;
+ 	struct tp65185x* tp;
+ 	const char* rev = NULL;
++	struct device *hwmon_dev;
+ 	int ret;
+ 
+ 	tp = devm_kzalloc(dev, sizeof(*tp), GFP_KERNEL);
+@@ -325,6 +432,7 @@ static int tp65185x_i2c_probe(struct i2c_client *i2c,
+ 		return -ENOMEM;
+ 
+ 	tp->dev = dev;
++	mutex_init(&tp->wakeup_mutex);
+ 
+ 	tp->powergood_gpio = devm_gpiod_get(dev, "powergood", GPIOD_IN);
+ 	if (IS_ERR(tp->powergood_gpio)) {
+@@ -404,6 +512,18 @@ static int tp65185x_i2c_probe(struct i2c_client *i2c,
+ 		return ret;
+ 	}
+ 
++	hwmon_dev = devm_hwmon_device_register_with_info(&i2c->dev,
++							 "tps65185",
++							 tp,
++							 &tp65185x_ntc_chip_info,
++							 NULL);
++        if (IS_ERR(hwmon_dev)) {
++		ret = PTR_ERR(hwmon_dev);
++                dev_err(dev, "unable to register tmst as hwmon device (%d)\n",
++			ret);
++                return ret;
++        }
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch
new file mode 100644
index 000000000000..dcc1b7af5001
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch
@@ -0,0 +1,487 @@
+From 724c700b61ab7c5cbaea998a8e3394527cd0c281 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 5 Oct 2019 15:12:51 +0200
+Subject: regulator: tp65185x: Add tp65185x eInk panel regulator driver
+
+This is a very simple driver that doesn't try to expose individual
+regulators, and implements the specific power sequencing necessary
+for the eInk panel power up directly.
+
+All the 6 regulators are thus represented as one logical supply.
+VCOM output is the only voltage that needs setting, and it can
+be changed by setting the voltage of the regulator exported by
+the driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/Kconfig    |   8 +
+ drivers/regulator/Makefile   |   1 +
+ drivers/regulator/tp65185x.c | 428 +++++++++++++++++++++++++++++++++++
+ 3 files changed, 437 insertions(+)
+ create mode 100644 drivers/regulator/tp65185x.c
+
+diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
+index 0ec7f70d74d0..eafa1d8f8381 100644
+--- a/drivers/regulator/Kconfig
++++ b/drivers/regulator/Kconfig
+@@ -1702,4 +1702,12 @@ config REGULATOR_QCOM_LABIBB
+ 	  boost regulator and IBB can be used as a negative boost regulator
+ 	  for LCD display panel.
+ 
++config REGULATOR_TP65185X
++	tristate "eInk display regulator tp65185x"
++	depends on I2C
++	select REGMAP_I2C
++	help
++	  This driver provides support for the voltage regulators for
++	  eInk displays on various e-book readers.
++
+ endif
+diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
+index 0f5df4aff8e5..7b3fb2642232 100644
+--- a/drivers/regulator/Makefile
++++ b/drivers/regulator/Makefile
+@@ -199,5 +199,6 @@ obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o
+ obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
+ obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
+ obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
++obj-$(CONFIG_REGULATOR_TP65185X) += tp65185x.o
+ 
+ ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
+diff --git a/drivers/regulator/tp65185x.c b/drivers/regulator/tp65185x.c
+new file mode 100644
+index 000000000000..8b57a11ff2f9
+--- /dev/null
++++ b/drivers/regulator/tp65185x.c
+@@ -0,0 +1,428 @@
++// SPDX-License-Identifier: GPL-2.0+
++//
++// Regulator device driver for tp65185x (eInk panel regulator)
++//
++// Copyright (C) 2019 Ondřej Jirman <megi@xff.cz>
++
++#include <linux/err.h>
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/regmap.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/of_regulator.h>
++#include <linux/gpio/consumer.h>
++#include <linux/delay.h>
++
++#define REG_TMST_VALUE    0x00
++#define REG_ENABLE        0x01
++#define REG_VADJ          0x02
++#define REG_VCOM1         0x03
++#define REG_VCOM2         0x04
++#define REG_INT_EN1       0x05
++#define REG_INT_EN2       0x06
++#define REG_INT1          0x07
++#define REG_INT2          0x08
++#define REG_UPSEQ0        0x09
++#define REG_UPSEQ1        0x0A
++#define REG_DWNSEQ0       0x0B
++#define REG_DWNSEQ1       0x0C
++#define REG_TMST1         0x0D
++#define REG_TMST2         0x0E
++#define REG_PG            0x0F
++#define REG_REVID         0x10
++
++struct tp65185x {
++	struct device* dev;
++	struct gpio_desc* wakeup_gpio;
++	struct gpio_desc* vcom_gpio;
++	struct gpio_desc* powerup_gpio;
++	struct gpio_desc* powergood_gpio;
++	struct regmap *regmap;
++	bool is_enabled;
++	int vcom;
++};
++
++static const struct regmap_config tp65185x_regmap_config = {
++	.reg_bits = 8,
++	.val_bits = 8,
++	.max_register = 0x10,
++	.cache_type = REGCACHE_NONE,
++};
++
++struct voltage_rail {
++	const char* name;
++	int bit;
++	int bit_en;
++};
++
++static const struct voltage_rail rails[] = {
++	{ "VB",    7, -1 },
++	{ "VDDH",  6, 3 },
++	{ "VN",    5, -1 },
++	{ "VPOS",  4, 2 },
++	{ "VEE",   3, 1 },
++	{ "VNEG",  1, 0 },
++	{ "VCOM",  -1, 4 },
++	{ "V3P3",  -1, 5 },
++};
++
++static int apply_voltage(struct tp65185x *tp, int vcom)
++{
++	int ret;
++
++	ret = regmap_write(tp->regmap, REG_VCOM1, vcom & 0xff);
++	if (ret)
++		return ret;
++
++	return regmap_write(tp->regmap, REG_VCOM2, (vcom >> 8) & 1);
++}
++
++static int set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV,
++		       unsigned *selector)
++{
++	struct tp65185x* tp = rdev_get_drvdata(rdev);
++	unsigned int vcom = min_uV / 10000;
++
++	if (vcom > 511 || min_uV < 0)
++		return -EINVAL;
++
++	tp->vcom = vcom;
++
++	// setup VCOM
++
++	if (!tp->is_enabled)
++		return 0;
++
++	return apply_voltage(tp, vcom);
++}
++
++static int get_voltage(struct regulator_dev *rdev)
++{
++	struct tp65185x* tp = rdev_get_drvdata(rdev);
++	unsigned int lsb, msb;
++	int ret;
++
++	if (tp->is_enabled) {
++		ret = regmap_read(rdev->regmap, REG_VCOM1, &lsb);
++		if (ret)
++			return ret;
++
++		ret = regmap_read(rdev->regmap, REG_VCOM2, &msb);
++		if (ret)
++			return ret;
++
++		return (lsb | ((msb & 1) << 8)) * 10000;
++	}
++
++	return tp->vcom * 10000;
++}
++
++#ifdef DEBUG
++static int show_power_status(struct tp65185x* tp, const char* state)
++{
++	unsigned int reg;
++	int i, ret;
++
++	ret = regmap_read(tp->regmap, REG_PG, &reg);
++	if (ret)
++		return ret;
++
++	dev_warn(tp->dev, "%s:\n", state);
++
++	dev_warn(tp->dev, "  voltage rail power good:\n");
++	for (i = 0; i < ARRAY_SIZE(rails); i++)
++		if (rails[i].bit >= 0)
++			dev_warn(tp->dev, "    %s %s\n", rails[i].name,
++				 reg & BIT(rails[i].bit) ? "good" : "fail");
++
++	ret = regmap_read(tp->regmap, REG_ENABLE, &reg);
++	if (ret)
++		return ret;
++
++	dev_warn(tp->dev, "  voltage rail enable status:\n");
++	for (i = 0; i < ARRAY_SIZE(rails); i++)
++		if (rails[i].bit_en >= 0)
++			dev_warn(tp->dev, "    %s %s\n", rails[i].name,
++				 reg & BIT(rails[i].bit_en)
++					? "enabled" : "disabled");
++
++	return 0;
++}
++#else
++static int show_power_status(struct tp65185x* tp, const char* state)
++{
++	return 0;
++}
++#endif
++
++static int show_power_bad(struct tp65185x* tp)
++{
++	unsigned int reg;
++	int i, ret;
++
++	ret = regmap_read(tp->regmap, REG_PG, &reg);
++	if (ret)
++		return ret;
++
++	dev_warn(tp->dev, "Voltage rail failures:\n");
++	for (i = 0; i < ARRAY_SIZE(rails); i++)
++		if (rails[i].bit >= 0 && !(reg & BIT(rails[i].bit)))
++			dev_warn(tp->dev, "  %s failed\n", rails[i].name);
++
++	return 0;
++}
++
++static int wait_for_power_good(struct tp65185x *tp)
++{
++	int ret, loops = 10;
++
++	// wait for power good
++	while (loops-- > 0) {
++		ret = gpiod_get_value(tp->powergood_gpio);
++		if (ret < 0)
++			return ret;
++
++		if (ret)
++			return 0;
++
++		msleep(5);
++	}
++
++	show_power_bad(tp);
++	return -ETIMEDOUT;
++}
++
++static int enable_supply(struct regulator_dev *rdev)
++{
++	struct tp65185x* tp = rdev_get_drvdata(rdev);
++	int ret;
++
++	if (tp->is_enabled)
++		return 0;
++
++	// wake up the regulator
++	gpiod_set_value(tp->wakeup_gpio, 1);
++	usleep_range(3000, 4000);
++
++	ret = apply_voltage(tp, tp->vcom);
++	if (ret) {
++		dev_err(tp->dev, "vcom restore failed (%d)\n", ret);
++		goto err;
++	}
++
++	show_power_status(tp, "pre-powerup");
++
++	// enable the VDD on the panel (V3P3) first
++	ret = regmap_write(tp->regmap, REG_ENABLE, 0x20);
++	if (ret) {
++		dev_err(tp->dev, "vdd enable failed (%d)\n", ret);
++		goto err;
++	}
++
++	usleep_range(2000, 2200);
++
++	show_power_status(tp, "V3P3 en");
++
++	// powerup by default takes about 20ms
++	gpiod_set_value(tp->powerup_gpio, 1);
++	usleep_range(22000, 24000);
++
++	ret = wait_for_power_good(tp);
++	if (ret)
++		goto err;
++
++	show_power_status(tp, "powerup done");
++
++	// enable VCOM last
++	gpiod_set_value(tp->vcom_gpio, 1);
++	usleep_range(4000, 5000);
++
++	show_power_status(tp, "powerup vcom");
++
++        tp->is_enabled = true;
++	return 0;
++
++err:
++	gpiod_set_value(tp->vcom_gpio, 0);
++	usleep_range(2000, 3000);
++	gpiod_set_value(tp->powerup_gpio, 0);
++	msleep(100);
++	gpiod_set_value(tp->wakeup_gpio, 0);
++	return ret;
++}
++
++static int disable_supply(struct regulator_dev *rdev)
++{
++	struct tp65185x* tp = rdev_get_drvdata(rdev);
++
++	if (!tp->is_enabled)
++		return 0;
++
++	show_power_status(tp, "pre-poweroff");
++
++	gpiod_set_value(tp->vcom_gpio, 0);
++	usleep_range(5000, 6000);
++
++	show_power_status(tp, "vcom down");
++
++	gpiod_set_value(tp->powerup_gpio, 0);
++
++	// it may take up to 100ms to power off all high voltage rails
++	msleep(100);
++
++	show_power_status(tp, "power down");
++
++	// this will power down the V3P3 switch too
++	gpiod_set_value(tp->wakeup_gpio, 0);
++
++	tp->is_enabled = false;
++
++	return 0;
++}
++
++static int is_supply_enabled(struct regulator_dev *rdev)
++{
++	struct tp65185x* tp = rdev_get_drvdata(rdev);
++	//int ret;
++
++	//ret = gpiod_get_value(tp->powergood_gpio);
++	//if (ret < 0)
++		//return ret;
++
++	return tp->is_enabled;
++}
++
++static const struct regulator_ops tp65185x_ops = {
++	.is_enabled		= is_supply_enabled,
++	.enable			= enable_supply,
++	.disable		= disable_supply,
++	.set_voltage		= set_voltage,
++	.get_voltage		= get_voltage,
++};
++
++static const struct regulator_desc tp65185x_reg = {
++	.name = "tp65185x",
++	.id = 0,
++	.continuous_voltage_range = 1,
++	.ops = &tp65185x_ops,
++	.type = REGULATOR_VOLTAGE,
++	.owner = THIS_MODULE,
++};
++
++static int tp65185x_i2c_probe(struct i2c_client *i2c,
++			      const struct i2c_device_id *id)
++{
++	struct device *dev = &i2c->dev;
++	struct regulator_dev *rdev;
++	struct regulator_config config = { };
++	unsigned int reg;
++	struct tp65185x* tp;
++	const char* rev = NULL;
++	int ret;
++
++	tp = devm_kzalloc(dev, sizeof(*tp), GFP_KERNEL);
++	if (!tp)
++		return -ENOMEM;
++
++	tp->dev = dev;
++
++	tp->powergood_gpio = devm_gpiod_get(dev, "powergood", GPIOD_IN);
++	if (IS_ERR(tp->powergood_gpio)) {
++		ret = PTR_ERR(tp->powergood_gpio);
++		dev_err(dev, "Can't get wakeup gpio (%d)\n", ret);
++		return ret;
++	}
++
++	tp->powerup_gpio = devm_gpiod_get(dev, "powerup", GPIOD_OUT_LOW);
++	if (IS_ERR(tp->powerup_gpio)) {
++		ret = PTR_ERR(tp->powerup_gpio);
++		dev_err(dev, "Can't get wakeup gpio (%d)\n", ret);
++		return ret;
++	}
++
++	tp->vcom_gpio = devm_gpiod_get(dev, "vcom", GPIOD_OUT_LOW);
++	if (IS_ERR(tp->vcom_gpio)) {
++		ret = PTR_ERR(tp->vcom_gpio);
++		dev_err(dev, "Can't get wakeup gpio (%d)\n", ret);
++		return ret;
++	}
++
++	tp->wakeup_gpio = devm_gpiod_get(dev, "wakeup", GPIOD_OUT_HIGH);
++	if (IS_ERR(tp->wakeup_gpio)) {
++		ret = PTR_ERR(tp->wakeup_gpio);
++		dev_err(dev, "Can't get wakeup gpio (%d)\n", ret);
++		return ret;
++	}
++
++	// wait for wakeup
++	usleep_range(10000, 12000);
++
++	i2c_set_clientdata(i2c, tp);
++
++	tp->regmap = devm_regmap_init_i2c(i2c, &tp65185x_regmap_config);
++	if (IS_ERR(tp->regmap)) {
++		ret = PTR_ERR(tp->regmap);
++		dev_err(dev, "Failed to allocate register map: %d\n", ret);
++		return ret;
++	}
++
++	ret = regmap_read(tp->regmap, REG_REVID, &reg);
++	if (ret) {
++		dev_err(dev, "chip id read failed (%d)\n", ret);
++		return ret;
++	}
++
++	switch (reg) {
++		case 0x45: rev = "TPS65185 1p0"; break;
++		case 0x55: rev = "TPS65185 1p1"; break;
++		case 0x65: rev = "TPS65185 1p2"; break;
++		case 0x66: rev = "TPS651851 1p0"; break;
++		default:
++			dev_err(dev, "reading chip id\n");
++			break;
++
++	}
++
++	dev_info(dev, "detected chip id 0x%02x (%s)\n", (int)reg, rev);
++
++	// disable regulators, move to sleep
++	gpiod_set_value(tp->wakeup_gpio, 0);
++
++	config.driver_data = tp;
++	config.dev = &i2c->dev;
++	config.regmap = tp->regmap;
++	config.of_node = dev->of_node;
++	config.init_data = of_get_regulator_init_data(dev, dev->of_node,
++						      &tp65185x_reg);
++	if (!config.init_data)
++		return -ENOMEM;
++
++	rdev = devm_regulator_register(&i2c->dev, &tp65185x_reg, &config);
++	if (IS_ERR(rdev)) {
++		ret = PTR_ERR(rdev);
++		dev_err(&i2c->dev, "Failed to register egulator (%d)\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static const struct i2c_device_id tp65185x_i2c_id[] = {
++	{ "tp65185x", 0 },
++	{ },
++};
++MODULE_DEVICE_TABLE(i2c, tp65185x_i2c_id);
++
++static struct i2c_driver tp65185x_regulator_driver = {
++	.driver = {
++		.name = "tp65185x",
++	},
++	.probe = tp65185x_i2c_probe,
++	.id_table = tp65185x_i2c_id,
++};
++
++module_i2c_driver(tp65185x_regulator_driver);
++
++MODULE_AUTHOR("Ondřej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("Regulator device driver for tp65185x");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
new file mode 100644
index 000000000000..0dd57f821980
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
@@ -0,0 +1,31 @@
+From 217d5f7c7da48215731910760767c792572f2d38 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Mar 2024 15:08:57 +0100
+Subject: rtc: Print which error caused RTC read failure
+
+Currently we can't know from kernel log, whether the read failed due
+to I2C bus error, or invalid time value, etc. Print the error in error
+message.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/rtc/class.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c
+index e31fa0ad127e..2f14aecf0e24 100644
+--- a/drivers/rtc/class.c
++++ b/drivers/rtc/class.c
+@@ -66,7 +66,8 @@ static void rtc_hctosys(struct rtc_device *rtc)
+ 	err = rtc_read_time(rtc, &tm);
+ 	if (err) {
+ 		dev_err(rtc->dev.parent,
+-			"hctosys: unable to read the hardware clock\n");
++			"hctosys: unable to read the hardware clock %pe\n",
++			ERR_PTR(err));
+ 		goto err_read;
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
new file mode 100644
index 000000000000..b6cbddd189df
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
@@ -0,0 +1,69 @@
+From c5db8d3a918fef9246898d0b844c1e1b52034c8a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 2 Jan 2021 15:52:27 -0600
+Subject: rtc: sun6i: Allow RTC wakeup after shutdown
+
+Only IRQs that have enable_irq_wake() called on them can wake the system
+from sleep or after it has been shut down. Currently, the RTC alarm can
+only wake the system from sleep. Run the suspend callback to arm the IRQ
+during the shutdown process, so the RTC alarm also works after shutdown.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/rtc/rtc-sun6i.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
+index 8e0c66906103..02129ea346c1 100644
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -709,6 +709,7 @@ static struct nvmem_config sun6i_rtc_nvmem_cfg = {
+ };
+ 
+ #ifdef CONFIG_PM_SLEEP
++
+ /* Enable IRQ wake on suspend, to wake up from RTC. */
+ static int sun6i_rtc_suspend(struct device *dev)
+ {
+@@ -721,7 +722,7 @@ static int sun6i_rtc_suspend(struct device *dev)
+ }
+ 
+ /* Disable IRQ wake on resume. */
+-static int sun6i_rtc_resume(struct device *dev)
++static int __maybe_unused sun6i_rtc_resume(struct device *dev)
+ {
+ 	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
+ 
+@@ -730,6 +731,7 @@ static int sun6i_rtc_resume(struct device *dev)
+ 
+ 	return 0;
+ }
++
+ #endif
+ 
+ static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
+@@ -849,6 +851,13 @@ static int sun6i_rtc_probe(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static void sun6i_rtc_shutdown(struct platform_device *pdev)
++{
++#ifdef CONFIG_PM_SLEEP
++	sun6i_rtc_suspend(&pdev->dev);
++#endif
++}
++
+ /*
+  * As far as RTC functionality goes, all models are the same. The
+  * datasheets claim that different models have different number of
+@@ -873,6 +882,7 @@ MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
+ 
+ static struct platform_driver sun6i_rtc_driver = {
+ 	.probe		= sun6i_rtc_probe,
++	.shutdown	= sun6i_rtc_shutdown,
+ 	.driver		= {
+ 		.name		= "sun6i-rtc",
+ 		.of_match_table = sun6i_rtc_dt_ids,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
new file mode 100644
index 000000000000..5e2e794aeae9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
@@ -0,0 +1,1075 @@
+From 0314996f8f06ca22c62f6c8434a8e506945ebedf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 12 Nov 2017 23:09:14 +0100
+Subject: sound: soc: ac100-codec: Support analog part of X-Powers AC100 codec
+
+Most of the controls are implemented.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mfd/ac100.c           |   3 +
+ include/linux/mfd/ac100.h     |   1 +
+ sound/soc/sunxi/Kconfig       |  11 +
+ sound/soc/sunxi/Makefile      |   1 +
+ sound/soc/sunxi/ac100-codec.c | 991 ++++++++++++++++++++++++++++++++++
+ 5 files changed, 1007 insertions(+)
+ create mode 100644 sound/soc/sunxi/ac100-codec.c
+
+diff --git a/drivers/mfd/ac100.c b/drivers/mfd/ac100.c
+index 8f47c392cbd1..6cc9b1035642 100644
+--- a/drivers/mfd/ac100.c
++++ b/drivers/mfd/ac100.c
+@@ -79,6 +79,9 @@ static struct mfd_cell ac100_cells[] = {
+ 	{
+ 		.name		= "ac100-codec",
+ 		.of_compatible	= "x-powers,ac100-codec",
++	}, {
++		.name		= "ac100-codec-analog",
++		.of_compatible	= "x-powers,ac100-codec-analog",
+ 	}, {
+ 		.name		= "ac100-rtc",
+ 		.of_compatible	= "x-powers,ac100-rtc",
+diff --git a/include/linux/mfd/ac100.h b/include/linux/mfd/ac100.h
+index 88005c3a1b2d..621bd10b79b2 100644
+--- a/include/linux/mfd/ac100.h
++++ b/include/linux/mfd/ac100.h
+@@ -80,6 +80,7 @@ struct ac100_dev {
+ #define AC100_ERPOUT_CTRL		0x57
+ #define AC100_SPKOUT_CTRL		0x58
+ #define AC100_LINEOUT_CTRL		0x59
++#define AC100_ADDA_TUNE1 		0x5a
+ 
+ /* ADC digital audio processing (high pass filter & auto gain control */
+ #define AC100_ADC_DAP_L_STA		0x80
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index 1f18f016acbb..7b2b3bcb062e 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -22,6 +22,17 @@ config SND_SUN8I_CODEC
+ 
+ 	  Say Y or M if you want to add sun8i digital audio codec support.
+ 
++config SND_AC100_CODEC
++	tristate "Allwinner (X-Powers) AC100 audio codec (analog part)"
++	depends on OF
++	depends on MACH_SUN8I || COMPILE_TEST
++	select MFD_AC100
++	help
++	  This option enables the audio codec support for Allwinner (X-Powers)
++	  AC100 chip.
++
++	  Say Y or M if you want to add AC100 audio codec support.
++
+ config SND_SUN8I_CODEC_ANALOG
+ 	tristate "Allwinner sun8i Codec Analog Controls Support"
+ 	depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
+index 4483fe9c94ef..6131aea97efa 100644
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_SND_AC100_CODEC) += ac100-codec.o
+ obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-codec.o
+ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
+ obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+diff --git a/sound/soc/sunxi/ac100-codec.c b/sound/soc/sunxi/ac100-codec.c
+new file mode 100644
+index 000000000000..c3fec8d8da52
+--- /dev/null
++++ b/sound/soc/sunxi/ac100-codec.c
+@@ -0,0 +1,991 @@
++/*
++ * This driver supports the controls for X-Powers (Allwinner)
++ * AC100 audio codec. This codec is co-packaged with AXP81x PMICs.
++ *
++ * (C) Copyright 2020 Ondrej Jirman <megi@xff.cz>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/pm_runtime.h>
++#include <linux/regmap.h>
++#include <linux/mfd/ac100.h>
++
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/tlv.h>
++#include <sound/soc-dapm.h>
++
++#define AC100_ADC_APC_CTRL_ADCR_EN_OFF                          15
++#define AC100_ADC_APC_CTRL_ADCR_EN_MASK                         BIT(15)
++#define AC100_ADC_APC_CTRL_ADCR_EN_DISABLED                     0
++#define AC100_ADC_APC_CTRL_ADCR_EN_ENABLED                      BIT(15)
++#define AC100_ADC_APC_CTRL_ADCR_GAIN_OFF                        12
++#define AC100_ADC_APC_CTRL_ADCR_GAIN(v)                         (((v) & 0x7) << 12)
++#define AC100_ADC_APC_CTRL_ADCL_EN_OFF                          11
++#define AC100_ADC_APC_CTRL_ADCL_EN_MASK                         BIT(11)
++#define AC100_ADC_APC_CTRL_ADCL_EN_DISABLED                     0
++#define AC100_ADC_APC_CTRL_ADCL_EN_ENABLED                      BIT(11)
++#define AC100_ADC_APC_CTRL_ADCL_GAIN_OFF                        8
++#define AC100_ADC_APC_CTRL_ADCL_GAIN(v)                         (((v) & 0x7) << 8)
++#define AC100_ADC_APC_CTRL_MBIAS_EN_OFF                         7
++#define AC100_ADC_APC_CTRL_MBIAS_EN_MASK                        BIT(7)
++#define AC100_ADC_APC_CTRL_MBIAS_EN_DISABLED                    0
++#define AC100_ADC_APC_CTRL_MBIAS_EN_ENABLED                     BIT(7)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_OFF             6
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_MASK            BIT(6)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_DISABLED        0
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_ENABLED         BIT(6)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_OFF            4
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_MASK           GENMASK(5, 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_250K           (0x0 << 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_500K           (0x1 << 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_1M             (0x2 << 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_2M             (0x3 << 4)
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_OFF                       2
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_MASK                      BIT(2)
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_LOAD                      0
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_HBIAS_EN                  BIT(2)
++#define AC100_ADC_APC_CTRL_HBIAS_EN_OFF                         1
++#define AC100_ADC_APC_CTRL_HBIAS_EN_MASK                        BIT(1)
++#define AC100_ADC_APC_CTRL_HBIAS_EN_DISABLED                    0
++#define AC100_ADC_APC_CTRL_HBIAS_EN_ENABLED                     BIT(1)
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_OFF                     0
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_MASK                    BIT(0)
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_DISABLED                0
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_ENABLED                 BIT(0)
++
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_OFF                       13
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_MASK                      BIT(13)
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_ENABLED                   BIT(13)
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_OFF                       12
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_MASK                      BIT(12)
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_ENABLED                   BIT(12)
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_OFF                  11
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_MASK                 BIT(11)
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_DISABLED             0
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_ENABLED              BIT(11)
++#define AC100_ADC_SRC_ADCR_LINEINR_OFF                          10
++#define AC100_ADC_SRC_ADCR_LINEINR_MASK                         BIT(10)
++#define AC100_ADC_SRC_ADCR_LINEINR_DISABLED                     0
++#define AC100_ADC_SRC_ADCR_LINEINR_ENABLED                      BIT(10)
++#define AC100_ADC_SRC_ADCR_AUXINR_OFF                           9
++#define AC100_ADC_SRC_ADCR_AUXINR_MASK                          BIT(9)
++#define AC100_ADC_SRC_ADCR_AUXINR_DISABLED                      0
++#define AC100_ADC_SRC_ADCR_AUXINR_ENABLED                       BIT(9)
++#define AC100_ADC_SRC_ADCR_ROUTMIX_OFF                          8
++#define AC100_ADC_SRC_ADCR_ROUTMIX_MASK                         BIT(8)
++#define AC100_ADC_SRC_ADCR_ROUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCR_ROUTMIX_ENABLED                      BIT(8)
++#define AC100_ADC_SRC_ADCR_LOUTMIX_OFF                          7
++#define AC100_ADC_SRC_ADCR_LOUTMIX_MASK                         BIT(7)
++#define AC100_ADC_SRC_ADCR_LOUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCR_LOUTMIX_ENABLED                      BIT(7)
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_OFF                       6
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_MASK                      BIT(6)
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_ENABLED                   BIT(6)
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_OFF                       5
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_MASK                      BIT(5)
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_ENABLED                   BIT(5)
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_OFF                  4
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_MASK                 BIT(4)
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_DISABLED             0
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_ENABLED              BIT(4)
++#define AC100_ADC_SRC_ADCL_LINEINL_OFF                          3
++#define AC100_ADC_SRC_ADCL_LINEINL_MASK                         BIT(3)
++#define AC100_ADC_SRC_ADCL_LINEINL_DISABLED                     0
++#define AC100_ADC_SRC_ADCL_LINEINL_ENABLED                      BIT(3)
++#define AC100_ADC_SRC_ADCL_AUXINL_OFF                           2
++#define AC100_ADC_SRC_ADCL_AUXINL_MASK                          BIT(2)
++#define AC100_ADC_SRC_ADCL_AUXINL_DISABLED                      0
++#define AC100_ADC_SRC_ADCL_AUXINL_ENABLED                       BIT(2)
++#define AC100_ADC_SRC_ADCL_LOUTMIX_OFF                          1
++#define AC100_ADC_SRC_ADCL_LOUTMIX_MASK                         BIT(1)
++#define AC100_ADC_SRC_ADCL_LOUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCL_LOUTMIX_ENABLED                      BIT(1)
++#define AC100_ADC_SRC_ADCL_ROUTMIX_OFF                          0
++#define AC100_ADC_SRC_ADCL_ROUTMIX_MASK                         BIT(0)
++#define AC100_ADC_SRC_ADCL_ROUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCL_ROUTMIX_ENABLED                      BIT(0)
++
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_OFF                    15
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_MASK                   BIT(15)
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_DISABLED               0
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_ENABLED                BIT(15)
++#define AC100_ADC_SRC_BST_CTRL_MIC1BOOST_OFF                    12
++#define AC100_ADC_SRC_BST_CTRL_MIC1BOOST(v)                     (((v) & 0x7) << 12)
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_OFF                    11
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_MASK                   BIT(11)
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_DISABLED               0
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_ENABLED                BIT(11)
++#define AC100_ADC_SRC_BST_CTRL_MIC2BOOST_OFF                    8
++#define AC100_ADC_SRC_BST_CTRL_MIC2BOOST(v)                     (((v) & 0x7) << 8)
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_OFF                      7
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_MASK                     BIT(7)
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_MIC2                     0
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_MIC3                     BIT(7)
++#define AC100_ADC_SRC_BST_CTRL_LINEIN_DIFF_PREG_OFF             4
++#define AC100_ADC_SRC_BST_CTRL_LINEIN_DIFF_PREG(v)              (((v) & 0x7) << 4)
++#define AC100_ADC_SRC_BST_CTRL_AXI_PREG_OFF                     0
++#define AC100_ADC_SRC_BST_CTRL_AXI_PREG(v)                      ((v) & 0x7)
++
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_OFF                  15
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_MASK                 BIT(15)
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_ENABLED              BIT(15)
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_OFF                  14
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_MASK                 BIT(14)
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_ENABLED              BIT(14)
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_OFF                  13
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_MASK                 BIT(13)
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_ENABLED              BIT(13)
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_OFF                  12
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_MASK                 BIT(12)
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_ENABLED              BIT(12)
++#define AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN_OFF                 8
++#define AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN(v)                  (((v) & 0xf) << 8)
++
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_OFF                   13
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_MASK                  BIT(13)
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_ENABLED               BIT(13)
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_OFF                   12
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_MASK                  BIT(12)
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_ENABLED               BIT(12)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_OFF              11
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_MASK             BIT(11)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_DISABLED         0
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_ENABLED          BIT(11)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_OFF                      10
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_MASK                     BIT(10)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_DISABLED                 0
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_ENABLED                  BIT(10)
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_OFF                       9
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_MASK                      BIT(9)
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_DISABLED                  0
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_ENABLED                   BIT(9)
++#define AC100_OUT_MXR_SRC_RMIX_DACR_OFF                         8
++#define AC100_OUT_MXR_SRC_RMIX_DACR_MASK                        BIT(8)
++#define AC100_OUT_MXR_SRC_RMIX_DACR_DISABLED                    0
++#define AC100_OUT_MXR_SRC_RMIX_DACR_ENABLED                     BIT(8)
++#define AC100_OUT_MXR_SRC_RMIX_DACL_OFF                         7
++#define AC100_OUT_MXR_SRC_RMIX_DACL_MASK                        BIT(7)
++#define AC100_OUT_MXR_SRC_RMIX_DACL_DISABLED                    0
++#define AC100_OUT_MXR_SRC_RMIX_DACL_ENABLED                     BIT(7)
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_OFF                   6
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_MASK                  BIT(6)
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_ENABLED               BIT(6)
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_OFF                   5
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_MASK                  BIT(5)
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_ENABLED               BIT(5)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_OFF              4
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_MASK             BIT(4)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_DISABLED         0
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_ENABLED          BIT(4)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_OFF                      3
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_MASK                     BIT(3)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_DISABLED                 0
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_ENABLED                  BIT(3)
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_OFF                       2
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_MASK                      BIT(2)
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_DISABLED                  0
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_ENABLED                   BIT(2)
++#define AC100_OUT_MXR_SRC_LMIX_DACL_OFF                         1
++#define AC100_OUT_MXR_SRC_LMIX_DACL_MASK                        BIT(1)
++#define AC100_OUT_MXR_SRC_LMIX_DACL_DISABLED                    0
++#define AC100_OUT_MXR_SRC_LMIX_DACL_ENABLED                     BIT(1)
++#define AC100_OUT_MXR_SRC_LMIX_DACR_OFF                         0
++#define AC100_OUT_MXR_SRC_LMIX_DACR_MASK                        BIT(0)
++#define AC100_OUT_MXR_SRC_LMIX_DACR_DISABLED                    0
++#define AC100_OUT_MXR_SRC_LMIX_DACR_ENABLED                     BIT(0)
++
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_OFF              14
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_MASK             GENMASK(15, 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_1_88V            (0x0 << 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_2_09V            (0x1 << 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_2_33V            (0x2 << 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_2_50V            (0x3 << 14)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_OFF              12
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_MASK             GENMASK(13, 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_1_88V            (0x0 << 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_2_09V            (0x1 << 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_2_33V            (0x2 << 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_2_50V            (0x3 << 12)
++#define AC100_OUT_MXR_SRC_BST_AX_GAIN_OFF                       9
++#define AC100_OUT_MXR_SRC_BST_AX_GAIN(v)                        (((v) & 0x7) << 9)
++#define AC100_OUT_MXR_SRC_BST_MIC1_GAIN_OFF                     6
++#define AC100_OUT_MXR_SRC_BST_MIC1_GAIN(v)                      (((v) & 0x7) << 6)
++#define AC100_OUT_MXR_SRC_BST_MIC2_GAIN_OFF                     3
++#define AC100_OUT_MXR_SRC_BST_MIC2_GAIN(v)                      (((v) & 0x7) << 3)
++#define AC100_OUT_MXR_SRC_BST_LINEIN_GAIN_OFF                   0
++#define AC100_OUT_MXR_SRC_BST_LINEIN_GAIN(v)                    ((v) & 0x7)
++
++#define AC100_HPOUT_CTRL_RIGHT_SRC_OFF                          15
++#define AC100_HPOUT_CTRL_RIGHT_SRC_MASK                         BIT(15)
++#define AC100_HPOUT_CTRL_RIGHT_SRC_DACR                         0
++#define AC100_HPOUT_CTRL_RIGHT_SRC_RAMIX                        BIT(15)
++#define AC100_HPOUT_CTRL_LEFT_SRC_OFF                           14
++#define AC100_HPOUT_CTRL_LEFT_SRC_MASK                          BIT(14)
++#define AC100_HPOUT_CTRL_LEFT_SRC_DACL                          0
++#define AC100_HPOUT_CTRL_LEFT_SRC_LAMIX                         BIT(14)
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_OFF                      13
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_MASK                     BIT(13)
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_MUTE                     0
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_NOT_MUTE                 BIT(13)
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_OFF                       12
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_MASK                      BIT(12)
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_MUTE                      0
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_NOT_MUTE                  BIT(12)
++#define AC100_HPOUT_CTRL_PA_EN_OFF                              11
++#define AC100_HPOUT_CTRL_PA_EN_MASK                             BIT(11)
++#define AC100_HPOUT_CTRL_PA_EN_DISABLED                         0
++#define AC100_HPOUT_CTRL_PA_EN_ENABLED                          BIT(11)
++#define AC100_HPOUT_CTRL_VOLUME_OFF                             4
++#define AC100_HPOUT_CTRL_VOLUME(v)                              (((v) & 0x3f) << 4)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_OFF                      2
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_MASK                     GENMASK(3, 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_4ms                      (0x0 << 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_8ms                      (0x1 << 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_16ms                     (0x2 << 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_32ms                     (0x3 << 2)
++#define AC100_HPOUT_CTRL_OUTPUT_CURRENT_OFF                     0
++#define AC100_HPOUT_CTRL_OUTPUT_CURRENT(v)                      ((v) & 0x3)
++
++#define AC100_ERPOUT_CTRL_RAMP_TIME_OFF                         11
++#define AC100_ERPOUT_CTRL_RAMP_TIME_MASK                        GENMASK(12, 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_256ms                       (0x0 << 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_512ms                       (0x1 << 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_640ms                       (0x2 << 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_768ms                       (0x3 << 11)
++#define AC100_ERPOUT_CTRL_OUT_CURRENT_OFF                       9
++#define AC100_ERPOUT_CTRL_OUT_CURRENT(v)                        (((v) & 0x3) << 9)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_OFF                      7
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_MASK                     GENMASK(8, 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_DACR                     (0x0 << 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_DACL                     (0x1 << 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_RAMIX                    (0x2 << 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_LAMIX                    (0x3 << 7)
++#define AC100_ERPOUT_CTRL_MUTE_OFF                              6
++#define AC100_ERPOUT_CTRL_MUTE_MASK                             BIT(6)
++#define AC100_ERPOUT_CTRL_MUTE_MUTE                             0
++#define AC100_ERPOUT_CTRL_MUTE_NOT_MUTE                         BIT(6)
++#define AC100_ERPOUT_CTRL_PA_EN_OFF                             5
++#define AC100_ERPOUT_CTRL_PA_EN_MASK                            BIT(5)
++#define AC100_ERPOUT_CTRL_PA_EN_DISABLED                        0
++#define AC100_ERPOUT_CTRL_PA_EN_ENABLED                         BIT(5)
++#define AC100_ERPOUT_CTRL_VOLUME_OFF                            0
++#define AC100_ERPOUT_CTRL_VOLUME(v)                             ((v) & 0x1f)
++
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_OFF                         12
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_MASK                        BIT(12)
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_MIXR                        0
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_MIXL_MIXR                   BIT(12)
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_OFF                      11
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_MASK                     BIT(11)
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_DISABLED                 0
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_ENABLED                  BIT(11)
++#define AC100_SPKOUT_CTRL_RIGHT_EN_OFF                          9
++#define AC100_SPKOUT_CTRL_RIGHT_EN_MASK                         BIT(9)
++#define AC100_SPKOUT_CTRL_RIGHT_EN_DISABLED                     0
++#define AC100_SPKOUT_CTRL_RIGHT_EN_ENABLED                      BIT(9)
++#define AC100_SPKOUT_CTRL_LEFT_SRC_OFF                          8
++#define AC100_SPKOUT_CTRL_LEFT_SRC_MASK                         BIT(8)
++#define AC100_SPKOUT_CTRL_LEFT_SRC_MIXL                         0
++#define AC100_SPKOUT_CTRL_LEFT_SRC_MIXL_MIXR                    BIT(8)
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_OFF                       7
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_MASK                      BIT(7)
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_DISABLED                  0
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_ENABLED                   BIT(7)
++#define AC100_SPKOUT_CTRL_LEFT_EN_OFF                           5
++#define AC100_SPKOUT_CTRL_LEFT_EN_MASK                          BIT(5)
++#define AC100_SPKOUT_CTRL_LEFT_EN_DISABLED                      0
++#define AC100_SPKOUT_CTRL_LEFT_EN_ENABLED                       BIT(5)
++#define AC100_SPKOUT_CTRL_VOLUME_OFF                            0
++#define AC100_SPKOUT_CTRL_VOLUME(v)                             ((v) & 0x1f)
++
++#define AC100_LINEOUT_CTRL_LINEOUT_GAIN_OFF                     5
++#define AC100_LINEOUT_CTRL_LINEOUT_GAIN(v)                      (((v) & 0x7) << 5)
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_OFF                       4
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_MASK                      BIT(4)
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_DISABLED                  0
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_ENABLED                   BIT(4)
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_OFF                       3
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_MASK                      BIT(3)
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_ON                        BIT(3)
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_OFF                       2
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_MASK                      BIT(2)
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_ON                        BIT(2)
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_OFF                       1
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_MASK                      BIT(1)
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_ON                        BIT(1)
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_OFF                       0
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_MASK                      BIT(0)
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_ON                        BIT(0)
++
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_OFF                  8
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_MASK                 BIT(8)
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_DIS                  0
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_EN                   BIT(8)
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_TIME_OFF                7
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_TIME                    BIT(7)
++
++struct ac100_codec {
++	struct device *dev;
++	struct snd_soc_component component;
++};
++
++/* ADC mixer controls */
++static const struct snd_kcontrol_new ac100_codec_adc_mixer_controls[] = {
++	SOC_DAPM_DOUBLE("Mic1 Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_MIC1_BOOST_OFF,
++			AC100_ADC_SRC_ADCR_MIC1_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mic2 Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_MIC2_BOOST_OFF,
++			AC100_ADC_SRC_ADCR_MIC2_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Differential Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_LINEINL_LINEINR_OFF,
++			AC100_ADC_SRC_ADCR_LINEINL_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_LINEINL_OFF,
++			AC100_ADC_SRC_ADCR_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Aux In Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_AUXINL_OFF,
++			AC100_ADC_SRC_ADCR_AUXINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mixer Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_LOUTMIX_OFF,
++			AC100_ADC_SRC_ADCR_ROUTMIX_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_ROUTMIX_OFF,
++			AC100_ADC_SRC_ADCR_LOUTMIX_OFF, 1, 0),
++};
++
++/* Output mixer controls */
++static const struct snd_kcontrol_new ac100_codec_mixer_controls[] = {
++	SOC_DAPM_DOUBLE("Mic1 Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_OFF,
++			AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mic2 Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_OFF,
++			AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Differential Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_OFF,
++			AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_LINEINL_OFF,
++			AC100_OUT_MXR_SRC_RMIX_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Aux In Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_AUXINL_OFF,
++			AC100_OUT_MXR_SRC_RMIX_AUXINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("DAC Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_DACL_OFF,
++			AC100_OUT_MXR_SRC_RMIX_DACR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("DAC Reversed Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_DACR_OFF,
++			AC100_OUT_MXR_SRC_RMIX_DACL_OFF, 1, 0),
++};
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_out_mixer_pregain_scale,
++				  -450, 150, 0);
++
++static const DECLARE_TLV_DB_RANGE(ac100_codec_mic_gain_scale,
++	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
++	1, 7, TLV_DB_SCALE_ITEM(3000, 300, 0),
++);
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_pre_gain_scale,
++				  -1200, 300, 0);
++
++static const DECLARE_TLV_DB_RANGE(ac100_codec_earpiece_vol_scale,
++	0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
++	2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
++);
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_lineout_vol_scale, -450, 150, 0);
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_hp_vol_scale, -6300, 100, 1);
++
++static const char *ac100_codec_hp_pa_delay_texts[] = {
++	"4ms", "8ms", "16ms", "32ms"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_hp_pa_delay_enum,
++			    AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_STARTUP_DELAY_OFF,
++			    ac100_codec_hp_pa_delay_texts);
++
++static const char *ac100_codec_hp_pa_cur_texts[] = {
++	"low", "mid", "higher", "highest"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_hp_pa_cur_enum,
++			    AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_OUTPUT_CURRENT_OFF,
++			    ac100_codec_hp_pa_cur_texts);
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_ep_pa_cur_enum,
++			    AC100_ERPOUT_CTRL,
++			    AC100_ERPOUT_CTRL_OUT_CURRENT_OFF,
++			    ac100_codec_hp_pa_cur_texts);
++
++static const char *ac100_codec_ep_pa_ramp_time_texts[] = {
++	"256ms", "512ms", "640ms", "768ms"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_ep_pa_ramp_time_enum,
++			    AC100_ERPOUT_CTRL,
++			    AC100_ERPOUT_CTRL_RAMP_TIME_OFF,
++			    ac100_codec_ep_pa_ramp_time_texts);
++
++static const char *ac100_codec_mic_bv_texts[] = {
++	"1.88V", "2.09V", "2.33V", "2.5V"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_mic1_bv_enum,
++			    AC100_OUT_MXR_SRC_BST,
++			    AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_OFF,
++			    ac100_codec_mic_bv_texts);
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_mic2_bv_enum,
++			    AC100_OUT_MXR_SRC_BST,
++			    AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_OFF,
++			    ac100_codec_mic_bv_texts);
++
++/* volume / mute controls */
++static const struct snd_kcontrol_new ac100_codec_controls[] = {
++	/* Microphone Amp boost gain */
++	SOC_SINGLE_TLV("Mic1 Boost Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_MIC1BOOST_OFF, 0x7, 0,
++		       ac100_codec_mic_gain_scale),
++
++	SOC_SINGLE_TLV("Mic2 Boost Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_MIC2BOOST_OFF, 0x7, 0,
++		       ac100_codec_mic_gain_scale),
++
++	SOC_SINGLE_TLV("Line In Pre-Gain Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_LINEIN_DIFF_PREG_OFF, 0x7, 0,
++		       ac100_codec_pre_gain_scale),
++
++	SOC_SINGLE_TLV("Aux In Pre-Gain Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_AXI_PREG_OFF, 0x7, 0,
++		       ac100_codec_pre_gain_scale),
++
++	/* ADC */
++	SOC_DOUBLE_TLV("ADC Gain Capture Volume", AC100_ADC_APC_CTRL,
++		       AC100_ADC_APC_CTRL_ADCL_GAIN_OFF,
++		       AC100_ADC_APC_CTRL_ADCR_GAIN_OFF, 0x7, 0,
++		       ac100_codec_out_mixer_pregain_scale),
++
++	/* Mixer pre-gain */
++	SOC_SINGLE_TLV("Mic1 Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_MIC1_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Mic2 Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_MIC2_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Line In Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_LINEIN_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Aux In Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_AX_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Headphone Playback Volume",
++		       AC100_HPOUT_CTRL,
++		       AC100_HPOUT_CTRL_VOLUME_OFF, 0x3f, 0,
++		       ac100_codec_hp_vol_scale),
++
++	SOC_SINGLE_TLV("Earpiece Playback Volume",
++		       AC100_ERPOUT_CTRL,
++		       AC100_ERPOUT_CTRL_VOLUME_OFF, 0x1f, 0,
++		       ac100_codec_earpiece_vol_scale),
++
++	SOC_SINGLE_TLV("Speaker Playback Volume",
++		       AC100_SPKOUT_CTRL,
++		       AC100_SPKOUT_CTRL_VOLUME_OFF, 0x1f, 0,
++		       ac100_codec_earpiece_vol_scale),
++
++	SOC_SINGLE_TLV("Line Out Playback Volume",
++		       AC100_LINEOUT_CTRL,
++		       AC100_LINEOUT_CTRL_LINEOUT_GAIN_OFF, 0x7, 0,
++		       ac100_codec_lineout_vol_scale),
++
++	SOC_ENUM("Headphone Amplifier Startup Delay",
++		 ac100_codec_hp_pa_delay_enum),
++	SOC_ENUM("Headphone Amplifier Current", ac100_codec_hp_pa_cur_enum),
++
++	SOC_ENUM("Earpiece Amplifier Ramp Time",
++		 ac100_codec_ep_pa_ramp_time_enum),
++	SOC_ENUM("Earpiece Amplifier Current", ac100_codec_ep_pa_cur_enum),
++
++	SOC_ENUM("Mic1 Bias Voltage", ac100_codec_mic1_bv_enum),
++	SOC_ENUM("Mic2 Bias Voltage", ac100_codec_mic2_bv_enum),
++};
++
++/* Headphone */
++
++static const char * const ac100_codec_hp_src_enum_text[] = {
++	"DAC", "Mixer",
++};
++
++static SOC_ENUM_DOUBLE_DECL(ac100_codec_hp_src_enum,
++			    AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_LEFT_SRC_OFF,
++			    AC100_HPOUT_CTRL_RIGHT_SRC_OFF,
++			    ac100_codec_hp_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_hp_src[] = {
++	SOC_DAPM_ENUM("Headphone Source Playback Route",
++		      ac100_codec_hp_src_enum),
++};
++
++static const struct snd_kcontrol_new ac100_codec_hp_switch =
++	SOC_DAPM_DOUBLE("Headphone Playback Switch",
++			AC100_HPOUT_CTRL,
++			AC100_HPOUT_CTRL_LEFT_PA_MUTE_OFF,
++			AC100_HPOUT_CTRL_RIGHT_PA_MUTE_OFF, 1, 0);
++
++/* Earpiece */
++
++static const struct snd_kcontrol_new ac100_codec_earpiece_switch =
++	SOC_DAPM_SINGLE("Playback Switch",
++			AC100_ERPOUT_CTRL,
++			AC100_ERPOUT_CTRL_MUTE_OFF, 1, 0);
++
++static const char * const ac100_codec_earpiece_src_enum_text[] = {
++	"DACR", "DACL", "Right Mixer", "Left Mixer",
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_earpiece_src_enum,
++			    AC100_ERPOUT_CTRL,
++			    AC100_ERPOUT_CTRL_INPUT_SOURCE_OFF,
++			    ac100_codec_earpiece_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_earpiece_src[] = {
++	SOC_DAPM_ENUM("Earpiece Source Playback Route",
++		      ac100_codec_earpiece_src_enum),
++};
++
++/* Speaker */
++
++static const char * const ac100_codec_spk_src_enum_text[] = {
++	"Stereo", "Mono",
++};
++
++static SOC_ENUM_DOUBLE_DECL(ac100_codec_spk_src_enum,
++			    AC100_SPKOUT_CTRL,
++			    AC100_SPKOUT_CTRL_LEFT_SRC_OFF,
++			    AC100_SPKOUT_CTRL_RIGHT_SRC_OFF,
++			    ac100_codec_spk_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_spk_src[] = {
++	SOC_DAPM_ENUM("Speaker Source Playback Route",
++		      ac100_codec_spk_src_enum),
++};
++
++static const struct snd_kcontrol_new ac100_codec_spk_switch =
++	SOC_DAPM_DOUBLE("Speaker Playback Switch",
++			AC100_SPKOUT_CTRL,
++			AC100_SPKOUT_CTRL_LEFT_EN_OFF,
++			AC100_SPKOUT_CTRL_RIGHT_EN_OFF, 1, 0);
++
++static const struct snd_kcontrol_new ac100_codec_spk_inv_switch =
++	SOC_DAPM_DOUBLE("Speaker Invert Switch",
++			AC100_SPKOUT_CTRL,
++			AC100_SPKOUT_CTRL_LEFT_INV_EN_OFF,
++			AC100_SPKOUT_CTRL_RIGHT_INV_EN_OFF, 1, 0);
++
++/* Line Out */
++
++static const struct snd_kcontrol_new ac100_codec_lineout_mixer_controls[] = {
++	SOC_DAPM_SINGLE("Mic1 Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S0_OFF, 1, 0),
++	SOC_DAPM_SINGLE("Mic2 Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S1_OFF, 1, 0),
++	SOC_DAPM_SINGLE("Right Mixer Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S2_OFF, 1, 0),
++	SOC_DAPM_SINGLE("Left Mixer Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S3_OFF, 1, 0),
++};
++
++static const struct snd_kcontrol_new ac100_codec_lineout_switch =
++	SOC_DAPM_SINGLE("Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_EN_OFF, 1, 0);
++
++/* Mic2 Boost Source */
++
++static const char * const ac100_codec_mic2boost_src_enum_text[] = {
++	"Mic2", "Mic3",
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_mic2boost_src_enum,
++			    AC100_ADC_SRC_BST_CTRL,
++			    AC100_ADC_SRC_BST_CTRL_MIC2SLT_OFF,
++			    ac100_codec_mic2boost_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_mic2boost_src[] = {
++	SOC_DAPM_ENUM("Mic2 Source Capture Route",
++		      ac100_codec_mic2boost_src_enum),
++};
++
++/* This is done to remove the headphone buffer DC offset. */
++static int ac100_codec_hp_power(struct snd_soc_dapm_widget *w,
++				struct snd_kcontrol *k, int event)
++{
++	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
++	unsigned int val = SND_SOC_DAPM_EVENT_ON(event) ? 0xf : 0;
++
++	// zero cross detection
++	if (SND_SOC_DAPM_EVENT_OFF(event)) {
++		snd_soc_component_update_bits(component,
++					      AC100_ADDA_TUNE1,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_MASK,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_EN);
++	} else {
++		snd_soc_component_update_bits(component,
++					      AC100_ADDA_TUNE1,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_MASK,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_DIS);
++	}
++
++	snd_soc_component_update_bits(component, AC100_OUT_MXR_DAC_A_CTRL,
++				      AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN(0xf),
++				      AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN(val));
++	return 0;
++}
++
++static const struct snd_soc_dapm_widget ac100_codec_widgets[] = {
++	/* DAC */
++	SND_SOC_DAPM_DAC("Left DAC", NULL, AC100_OUT_MXR_DAC_A_CTRL,
++			 AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_OFF, 0),
++	SND_SOC_DAPM_DAC("Right DAC", NULL, AC100_OUT_MXR_DAC_A_CTRL,
++			 AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_OFF, 0),
++
++	/* ADC */
++	SND_SOC_DAPM_ADC("Left ADC", NULL, AC100_ADC_APC_CTRL,
++			 AC100_ADC_APC_CTRL_ADCL_EN_OFF, 0),
++	SND_SOC_DAPM_ADC("Right ADC", NULL, AC100_ADC_APC_CTRL,
++			 AC100_ADC_APC_CTRL_ADCR_EN_OFF, 0),
++
++	/*
++	 * Due to this component and the codec belonging to separate DAPM
++	 * contexts, we need to manually link the above widgets to their
++	 * stream widgets at the card level.
++	 */
++
++        /* Headphones */
++
++	SND_SOC_DAPM_REGULATOR_SUPPLY("cpvdd", 0, 0),
++	SND_SOC_DAPM_MUX("Left Headphone Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_hp_src),
++	SND_SOC_DAPM_MUX("Right Headphone Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_hp_src),
++	SND_SOC_DAPM_SWITCH("Left Headphone Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_hp_switch),
++	SND_SOC_DAPM_SWITCH("Right Headphone Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_hp_switch),
++	SND_SOC_DAPM_OUT_DRV("Left Headphone Amp",
++			     SND_SOC_NOPM, 0, 0, NULL, 0),
++	SND_SOC_DAPM_OUT_DRV("Right Headphone Amp",
++			     SND_SOC_NOPM, 0, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("Headphone Amp", AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_PA_EN_OFF, 0,
++			    ac100_codec_hp_power,
++			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
++	SND_SOC_DAPM_OUTPUT("HP"),
++
++        /* Earpiece */
++
++	SND_SOC_DAPM_MUX("Earpiece Source Playback Route",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_earpiece_src),
++	SND_SOC_DAPM_SWITCH("Earpiece",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_earpiece_switch),
++	SND_SOC_DAPM_OUT_DRV("Earpiece Amp", AC100_ERPOUT_CTRL,
++			     AC100_ERPOUT_CTRL_PA_EN_OFF, 0, NULL, 0),
++	SND_SOC_DAPM_OUTPUT("EARPIECE"),
++
++	/* Speaker */
++
++	SND_SOC_DAPM_MUX("Left Speaker Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_spk_src),
++	SND_SOC_DAPM_MUX("Right Speaker Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_spk_src),
++	SND_SOC_DAPM_SWITCH("Left Speaker Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_switch),
++	SND_SOC_DAPM_SWITCH("Right Speaker Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_switch),
++	SND_SOC_DAPM_SWITCH("Left Speaker Invert Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_inv_switch),
++	SND_SOC_DAPM_SWITCH("Right Speaker Invert Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_inv_switch),
++	SND_SOC_DAPM_OUTPUT("SPKOUTL"),
++	SND_SOC_DAPM_OUTPUT("SPKOUTR"),
++
++	/* Line Out */
++
++	SND_SOC_DAPM_MIXER("Line Out Mixer", SND_SOC_NOPM, 0, 0,
++			   ac100_codec_lineout_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_lineout_mixer_controls)),
++	SND_SOC_DAPM_SWITCH("Line Out",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_lineout_switch),
++	SND_SOC_DAPM_OUTPUT("LINEOUT"),
++
++	/* Microphone 1 */
++
++	SND_SOC_DAPM_INPUT("MIC1"),
++	SND_SOC_DAPM_SUPPLY("MBIAS", AC100_ADC_APC_CTRL,
++			    AC100_ADC_APC_CTRL_MBIAS_EN_OFF,
++			    0, NULL, 0),
++	SND_SOC_DAPM_PGA("Mic1 Amplifier", AC100_ADC_SRC_BST_CTRL,
++			 AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_OFF, 0, NULL, 0),
++
++        /* Microphone 2 and 3 */
++
++	SND_SOC_DAPM_INPUT("MIC2"),
++	SND_SOC_DAPM_INPUT("MIC3"),
++	SND_SOC_DAPM_MUX("Mic2 Amplifier Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_mic2boost_src),
++	SND_SOC_DAPM_SUPPLY("HBIAS", AC100_ADC_APC_CTRL,
++			    AC100_ADC_APC_CTRL_HBIAS_EN_OFF,
++			    0, NULL, 0),
++	SND_SOC_DAPM_PGA("Mic2 Amplifier", AC100_ADC_SRC_BST_CTRL,
++			 AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_OFF, 0, NULL, 0),
++
++	/* Line input */
++
++	SND_SOC_DAPM_INPUT("LINEIN"),
++
++	/* Aux input */
++
++	SND_SOC_DAPM_INPUT("AUXIN"),
++
++	/* Output mixers */
++	SND_SOC_DAPM_MIXER("Left Mixer", AC100_OUT_MXR_DAC_A_CTRL,
++			   AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_OFF, 0,
++			   ac100_codec_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_mixer_controls)),
++	SND_SOC_DAPM_MIXER("Right Mixer", AC100_OUT_MXR_DAC_A_CTRL,
++			   AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_OFF, 0,
++			   ac100_codec_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_mixer_controls)),
++
++	/* Input mixers */
++	SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
++			   ac100_codec_adc_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_adc_mixer_controls)),
++	SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
++			   ac100_codec_adc_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_adc_mixer_controls)),
++};
++
++static const struct snd_soc_dapm_route ac100_codec_routes[] = {
++	/* Microphone Routes */
++	{ "Mic1 Amplifier", NULL, "MIC1"},
++	{ "Mic2 Amplifier", NULL, "Mic2 Amplifier Source"},
++	{ "Mic2 Amplifier Source", "Mic2", "MIC2" },
++	{ "Mic2 Amplifier Source", "Mic3", "MIC3" },
++
++	/* Mixer Routes */
++	{ "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
++	{ "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
++	{ "Left Mixer", "Line In Differential Playback Switch", "LINEIN" },
++	{ "Left Mixer", "Line In Playback Switch", "LINEIN" },
++	{ "Left Mixer", "Aux In Playback Switch", "AUXIN" },
++	{ "Left Mixer", "DAC Playback Switch", "Left DAC" },
++	{ "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
++
++	{ "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
++	{ "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
++	{ "Right Mixer", "Line In Differential Playback Switch", "LINEIN" },
++	{ "Right Mixer", "Line In Playback Switch", "LINEIN" },
++	{ "Right Mixer", "Aux In Playback Switch", "AUXIN" },
++	{ "Right Mixer", "DAC Playback Switch", "Right DAC" },
++	{ "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
++
++	/* ADC Mixer Routes */
++	{ "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
++	{ "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
++	{ "Left ADC Mixer", "Line In Differential Capture Switch", "LINEIN" },
++	{ "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
++	{ "Left ADC Mixer", "Aux In Capture Switch", "AUXIN" },
++	{ "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
++	{ "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
++
++	{ "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
++	{ "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
++	{ "Right ADC Mixer", "Line In Differential Capture Switch", "LINEIN" },
++	{ "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
++	{ "Right ADC Mixer", "Aux In Capture Switch", "AUXIN" },
++	{ "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
++	{ "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
++
++	/* ADC Routes */
++	{ "Left ADC", NULL, "Left ADC Mixer" },
++	{ "Right ADC", NULL, "Right ADC Mixer" },
++
++	/* Headphone Routes */
++	{ "Left Headphone Source", "DAC", "Left DAC" },
++	{ "Left Headphone Source", "Mixer", "Left Mixer" },
++	{ "Left Headphone Switch", "Headphone Playback Switch", "Left Headphone Source" },
++	{ "Left Headphone Amp", NULL, "Left Headphone Switch" },
++	{ "Left Headphone Amp", NULL, "Headphone Amp" },
++	{ "HP", NULL, "Left Headphone Amp" },
++
++	{ "Right Headphone Source", "DAC", "Right DAC" },
++	{ "Right Headphone Source", "Mixer", "Right Mixer" },
++	{ "Right Headphone Switch", "Headphone Playback Switch", "Right Headphone Source" },
++	{ "Right Headphone Amp", NULL, "Right Headphone Switch" },
++	{ "Right Headphone Amp", NULL, "Headphone Amp" },
++	{ "HP", NULL, "Right Headphone Amp" },
++
++	{ "Headphone Amp", NULL, "cpvdd" },
++
++	/* Speaker Routes */
++	{ "Left Speaker Source", "Stereo", "Left Mixer" },
++	{ "Left Speaker Source", "Mono", "Right Mixer" },
++	{ "Left Speaker Source", "Mono", "Left Mixer" },
++	{ "Left Speaker Switch", "Speaker Playback Switch", "Left Speaker Source" },
++	{ "SPKOUTL", NULL, "Left Speaker Switch" },
++
++	{ "Right Speaker Source", "Stereo", "Right Mixer" },
++	{ "Right Speaker Source", "Mono", "Right Mixer" },
++	{ "Right Speaker Source", "Mono", "Left Mixer" },
++	{ "Right Speaker Switch", "Speaker Playback Switch", "Right Speaker Source" },
++	{ "SPKOUTR", NULL, "Right Speaker Switch" },
++
++	/* Earpiece Routes */
++	{ "Earpiece Source Playback Route", "DACR", "Right DAC" },
++	{ "Earpiece Source Playback Route", "DACL", "Left DAC" },
++	{ "Earpiece Source Playback Route", "Right Mixer", "Right Mixer" },
++	{ "Earpiece Source Playback Route", "Left Mixer", "Left Mixer" },
++	{ "Earpiece", "Playback Switch", "Earpiece Source Playback Route" },
++	{ "Earpiece Amp", NULL, "Earpiece" },
++	{ "EARPIECE", NULL, "Earpiece Amp" },
++
++	/* Line-out Routes */
++	{ "Line Out", "Playback Switch", "Line Out Mixer" },
++	{ "Line Out Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
++	{ "Line Out Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
++	{ "Line Out Mixer", "Right Mixer Playback Switch", "Right Mixer" },
++	{ "Line Out Mixer", "Left Mixer Playback Switch", "Left Mixer" },
++	{ "LINEOUT", NULL, "Line Out" },
++};
++
++static const struct snd_soc_component_driver ac100_codec_analog_cmpnt_drv = {
++	.controls		= ac100_codec_controls,
++	.num_controls		= ARRAY_SIZE(ac100_codec_controls),
++	.dapm_widgets		= ac100_codec_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(ac100_codec_widgets),
++	.dapm_routes		= ac100_codec_routes,
++	.num_dapm_routes	= ARRAY_SIZE(ac100_codec_routes),
++};
++
++static int ac100_codec_probe(struct platform_device *pdev)
++{
++	struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
++	struct ac100_codec *codec;
++	int ret = 0;
++
++	codec = devm_kzalloc(&pdev->dev, sizeof(*codec), GFP_KERNEL);
++	if (!codec)
++		return -ENOMEM;
++
++	codec->dev = &pdev->dev;
++	platform_set_drvdata(pdev, codec);
++
++	snd_soc_component_init_regmap(&codec->component, ac100->regmap);
++
++	ret = snd_soc_component_initialize(&codec->component,
++					   &ac100_codec_analog_cmpnt_drv,
++					   &pdev->dev);
++	if (ret < 0)
++		return ret;
++
++	ret = snd_soc_add_component(&codec->component, NULL, 0);
++	if (ret) {
++		dev_err(&pdev->dev,
++			"Failed to register codec component (%d)\n", ret);
++		return ret;
++	}
++
++	return ret;
++}
++
++static int ac100_codec_remove(struct platform_device *pdev)
++{
++	snd_soc_unregister_component(&pdev->dev);
++
++	/*
++	 * We do not call snd_soc_component_exit_regmap, because regmap
++	 * is still owned by the mfd device.
++	 */
++	return 0;
++}
++
++static const struct of_device_id ac100_codec_of_match[] = {
++	{ .compatible = "x-powers,ac100-codec-analog" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, ac100_codec_of_match);
++
++static struct platform_driver ac100_codec_driver = {
++	.driver = {
++		.name = "ac100-codec-analog",
++		.of_match_table = ac100_codec_of_match,
++	},
++	.probe = ac100_codec_probe,
++	.remove = ac100_codec_remove,
++};
++module_platform_driver(ac100_codec_driver);
++
++MODULE_DESCRIPTION("X-Powers AC100 codec driver");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ac100-codec");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
new file mode 100644
index 000000000000..d2c5011d09cd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
@@ -0,0 +1,371 @@
+From 5819633ccb8645d4733d0b2f37d4c59de967296d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 9 Feb 2020 17:58:59 +0100
+Subject: sound: soc: sun8i-codec: Add support for digital part of the AC100
+ codec
+
+X-Power AC100 codec has almost the same digital part as the A64 codec.
+The major difference is that registers are spaced differently. A64
+has codec register address stride of 4 bytes, while AC100 has addresses
+packed together.
+
+We use a custom regmap/regmap_bus to translate register addresses from
+the A64 regmap to the correct registers in the AC100's MFD regmap.
+
+We also need to power the codec, so AC100's regulators are also enabled
+by the codec driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/Kconfig       |   4 +-
+ sound/soc/sunxi/sun8i-codec.c | 216 ++++++++++++++++++++++++++++++++--
+ 2 files changed, 212 insertions(+), 8 deletions(-)
+
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index 7b2b3bcb062e..f87b061f59b2 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -16,9 +16,11 @@ config SND_SUN8I_CODEC
+ 	depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+ 	depends on COMMON_CLK
+ 	select REGMAP_MMIO
++	select MFD_AC100
+ 	help
+ 	  This option enables the digital part of the internal audio codec for
+-	  Allwinner sun8i SoC (and particularly A33).
++	  Allwinner sun8i SoC (and particularly A33). It also supports digital
++	  part of X-Powers AC100.
+ 
+ 	  Say Y or M if you want to add sun8i digital audio codec support.
+ 
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index c6550f0b3204..2e4581f371a7 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -21,7 +21,9 @@
+ #include <linux/of.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/log2.h>
++#include <linux/mfd/ac100.h>
+ 
+ #include <sound/jack.h>
+ #include <sound/pcm_params.h>
+@@ -194,6 +196,50 @@
+ 				 SNDRV_PCM_RATE_192000    |\
+ 				 SNDRV_PCM_RATE_KNOT)
+ 
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_OFF	15
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_MASK	BIT(15)
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_ENABLED	BIT(15)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_OFF	12
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_MASK	GENMASK(13, 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_MCLK1	(0x0 << 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_MCLK2	(0x1 << 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_BCLK1	(0x2 << 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_BCLK2	(0x3 << 12)
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_OFF	11
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_MASK	BIT(11)
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_ENABLED	BIT(11)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_OFF	8
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_MASK	GENMASK(9, 8)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_MCLK1	(0x0 << 8)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_MCLK2	(0x1 << 8)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_PLL	(0x2 << 8)
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_OFF	7
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_MASK	BIT(7)
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_ENABLED	BIT(7)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_OFF	4
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_MASK	GENMASK(5, 4)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_MCLK1	(0x0 << 4)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_MCLK2	(0x1 << 4)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_PLL	(0x2 << 4)
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_OFF	3
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_MASK	BIT(3)
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_ENABLED	BIT(3)
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_OFF	0
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_MASK	BIT(0)
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_I2S1CLK	0
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_I2S2CLK	BIT(0)
++
++static const char *const ac100_supply_names[] = {
++	"LDOIN",
++	"AVCC",
++	"VDDIO1",
++	"VDDIO2",
++};
++
+ enum {
+ 	SUN8I_CODEC_AIF1,
+ 	SUN8I_CODEC_AIF2,
+@@ -242,6 +288,9 @@ struct sun8i_codec {
+ 	int				last_hmic_irq;
+ 	unsigned int			sysclk_rate;
+ 	int				sysclk_refcnt;
++
++	struct regmap			*ac100_regmap;
++	struct regulator_bulk_data	supplies[ARRAY_SIZE(ac100_supply_names)];
+ };
+ 
+ static struct snd_soc_dai_driver sun8i_codec_dais[];
+@@ -645,6 +694,10 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
+ 			   SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK,
+ 			   bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV);
+ 
++	/* TODO: Implement clk driver for AC100 codec system clock */
++	if (scodec->ac100_regmap)
++		goto update_sample_rate;
++
+ 	/*
+ 	 * SYSCLK rate
+ 	 *
+@@ -667,6 +720,7 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
+ 		scodec->sysclk_refcnt++;
+ 	scodec->sysclk_rate = sysclk_rate;
+ 
++update_sample_rate:
+ 	aif->lrck_div_order = lrck_div_order;
+ 	aif->sample_rate = sample_rate;
+ 	aif->open_streams |= BIT(substream->stream);
+@@ -684,8 +738,11 @@ static int sun8i_codec_hw_free(struct snd_pcm_substream *substream,
+ 	if (aif->open_streams != BIT(substream->stream))
+ 		goto done;
+ 
+-	clk_rate_exclusive_put(scodec->clk_module);
+-	scodec->sysclk_refcnt--;
++	if (!scodec->ac100_regmap) {
++		clk_rate_exclusive_put(scodec->clk_module);
++		scodec->sysclk_refcnt--;
++	}
++
+ 	aif->lrck_div_order = 0;
+ 	aif->sample_rate = 0;
+ 
+@@ -958,8 +1015,6 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
+ 
+ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
+ 	/* System Clocks */
+-	SND_SOC_DAPM_CLOCK_SUPPLY("mod"),
+-
+ 	SND_SOC_DAPM_SUPPLY("AIF1CLK",
+ 			    SUN8I_SYSCLK_CTL,
+ 			    SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
+@@ -1120,8 +1175,6 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
+ 
+ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
+ 	/* Clock Routes */
+-	{ "AIF1CLK", NULL, "mod" },
+-
+ 	{ "SYSCLK", NULL, "AIF1CLK" },
+ 
+ 	{ "CLK AIF1", NULL, "AIF1CLK" },
+@@ -1291,6 +1344,16 @@ static const struct snd_soc_dapm_route sun8i_codec_legacy_routes[] = {
+ 	{ "AIF1 Slot 0 Right", NULL, "DACR" },
+ };
+ 
++static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets_sun8i[] = {
++	SND_SOC_DAPM_CLOCK_SUPPLY("mod"),
++};
++
++static const struct snd_soc_dapm_route sun8i_codec_dapm_routes_sun8i[] = {
++	{ "AIF1CLK", NULL, "mod" },
++};
++
++static int ac100_codec_component_probe(struct snd_soc_component *component);
++
+ static int sun8i_codec_component_probe(struct snd_soc_component *component)
+ {
+ 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
+@@ -1299,6 +1362,21 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component)
+ 
+ 	scodec->component = component;
+ 
++	if (scodec->ac100_regmap)
++                return ac100_codec_component_probe(component);
++
++	ret = snd_soc_dapm_new_controls(dapm,
++					sun8i_codec_dapm_widgets_sun8i,
++					ARRAY_SIZE(sun8i_codec_dapm_widgets_sun8i));
++	if (ret)
++		return ret;
++
++	ret = snd_soc_dapm_add_routes(dapm,
++				      sun8i_codec_dapm_routes_sun8i,
++				      ARRAY_SIZE(sun8i_codec_dapm_routes_sun8i));
++	if (ret)
++		return ret;
++
+ 	/* Add widgets for backward compatibility with old device trees. */
+ 	if (scodec->quirks->legacy_widgets) {
+ 		ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_legacy_widgets,
+@@ -1640,7 +1718,7 @@ static bool sun8i_codec_volatile_reg(struct device *dev, unsigned int reg)
+ 	return reg == SUN8I_HMIC_STS;
+ }
+ 
+-static const struct regmap_config sun8i_codec_regmap_config = {
++static struct regmap_config sun8i_codec_regmap_config = {
+ 	.reg_bits	= 32,
+ 	.reg_stride	= 4,
+ 	.val_bits	= 32,
+@@ -1650,12 +1728,124 @@ static const struct regmap_config sun8i_codec_regmap_config = {
+ 	.cache_type	= REGCACHE_FLAT,
+ };
+ 
++/* AC100 Codec Support (digital parts) */
++
++static int sun8i_codec_ac100_regmap_read(void *context,
++					 unsigned int reg, unsigned int *val)
++{
++	struct sun8i_codec *scodec = context;
++
++	return regmap_read(scodec->ac100_regmap, reg / 4, val);
++}
++
++static int sun8i_codec_ac100_regmap_write(void *context,
++					  unsigned int reg, unsigned int val)
++{
++	struct sun8i_codec *scodec = context;
++
++	return regmap_write(scodec->ac100_regmap, reg / 4, val);
++}
++
++static struct regmap_bus sun8i_codec_ac100_regmap_bus = {
++	.reg_write = sun8i_codec_ac100_regmap_write,
++	.reg_read = sun8i_codec_ac100_regmap_read,
++};
++
++static int ac100_codec_component_probe(struct snd_soc_component *component)
++{
++	struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
++
++        /*
++	 * The system clock(SYSCLK) of AC100 must be 512*fs(fs=48KHz or 44.1KHz)
++	 * Source clocks from the SoC.
++	 */
++
++        regmap_update_bits(scodec->ac100_regmap, AC100_SYSCLK_CTRL,
++                            AC100_SYSCLK_CTRL_I2S1CLK_SRC_MASK,
++                            AC100_SYSCLK_CTRL_I2S1CLK_SRC_MCLK1);
++        regmap_update_bits(scodec->ac100_regmap, AC100_SYSCLK_CTRL,
++                            AC100_SYSCLK_CTRL_I2S2CLK_SRC_MASK,
++                            AC100_SYSCLK_CTRL_I2S2CLK_SRC_MCLK1);
++        regmap_update_bits(scodec->ac100_regmap, AC100_SYSCLK_CTRL,
++                            AC100_SYSCLK_CTRL_SYSCLK_SRC_MASK,
++                            AC100_SYSCLK_CTRL_SYSCLK_SRC_I2S1CLK);
++
++	/* Program the default sample rate. */
++	return sun8i_codec_update_sample_rate(scodec);
++}
++
++static int sun8i_codec_probe_ac100(struct platform_device *pdev)
++{
++	struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
++	struct device* dev = &pdev->dev;
++	struct sun8i_codec *scodec;
++	int ret, i;
++
++	scodec = devm_kzalloc(dev, sizeof(*scodec), GFP_KERNEL);
++	if (!scodec)
++		return -ENOMEM;
++
++	scodec->quirks = of_device_get_match_data(&pdev->dev);
++	scodec->ac100_regmap = ac100->regmap;
++
++	platform_set_drvdata(pdev, scodec);
++
++	/*
++	 * Caching is done by the MFD regmap, so disable the mapped regmap
++	 * cache.
++	 */
++	sun8i_codec_regmap_config.cache_type = REGCACHE_NONE;
++
++	/*
++	 * We need to create a custom regmap_bus that will map reads/writes to
++	 * the MFD regmap
++	 */
++	scodec->regmap = __regmap_lockdep_wrapper(__devm_regmap_init,
++		 "ac100-regmap-codec", dev,
++		  &sun8i_codec_ac100_regmap_bus, scodec,
++		  &sun8i_codec_regmap_config);
++	if (IS_ERR(scodec->regmap))
++		return dev_err_probe(dev, PTR_ERR(scodec->regmap),
++				     "Failed to create our regmap\n");
++
++	for (i = 0; i < ARRAY_SIZE(scodec->supplies); i++)
++		scodec->supplies[i].supply = ac100_supply_names[i];
++
++        ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(scodec->supplies),
++                                      scodec->supplies);
++        if (ret)
++		return dev_err_probe(dev, ret, "Failed to request supplies\n");
++
++	ret = regulator_bulk_enable(ARRAY_SIZE(scodec->supplies),
++				    scodec->supplies);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to enable supplies\n");
++
++	ret = devm_snd_soc_register_component(dev, &sun8i_soc_component,
++					      sun8i_codec_dais,
++					      ARRAY_SIZE(sun8i_codec_dais));
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to register codec\n");
++		goto err_disable_reg;
++	}
++
++	return 0;
++
++err_disable_reg:
++	regulator_bulk_disable(ARRAY_SIZE(scodec->supplies),
++			       scodec->supplies);
++	return ret;
++}
++
+ static int sun8i_codec_probe(struct platform_device *pdev)
+ {
+ 	struct sun8i_codec *scodec;
+ 	void __iomem *base;
+ 	int ret;
+ 
++	if (of_device_is_compatible(pdev->dev.of_node, "x-powers,ac100-codec"))
++		return sun8i_codec_probe_ac100(pdev);
++
+ 	scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
+ 	if (!scodec)
+ 		return -ENOMEM;
+@@ -1728,6 +1918,14 @@ static int sun8i_codec_probe(struct platform_device *pdev)
+ 
+ static void sun8i_codec_remove(struct platform_device *pdev)
+ {
++	struct sun8i_codec *scodec = dev_get_drvdata(&pdev->dev);
++
++	if (scodec->ac100_regmap) {
++		regulator_bulk_disable(ARRAY_SIZE(scodec->supplies),
++				       scodec->supplies);
++		return;
++	}
++
+ 	pm_runtime_disable(&pdev->dev);
+ 	if (!pm_runtime_status_suspended(&pdev->dev))
+ 		sun8i_codec_runtime_suspend(&pdev->dev);
+@@ -1744,9 +1942,13 @@ static const struct sun8i_codec_quirks sun50i_a64_quirks = {
+ 	.jack_detection	= true,
+ };
+ 
++static const struct sun8i_codec_quirks ac100_quirks = {
++};
++
+ static const struct of_device_id sun8i_codec_of_match[] = {
+ 	{ .compatible = "allwinner,sun8i-a33-codec", .data = &sun8i_a33_quirks },
+ 	{ .compatible = "allwinner,sun50i-a64-codec", .data = &sun50i_a64_quirks },
++	{ .compatible = "x-powers,ac100-codec", .data = &ac100_quirks },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/spi-fixes.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/spi-fixes.patch
new file mode 100644
index 000000000000..c3a53821b749
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/spi-fixes.patch
@@ -0,0 +1,66 @@
+From ee2f55399f1186f6c24287a4ee51782d5b63107e Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 25 Feb 2024 04:22:51 +0100
+Subject: spi fixes
+
+---
+ drivers/spi/spi-rockchip.c | 15 +++++----------
+ 1 file changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
+index 052dda891a40..ce5169943f69 100644
+--- a/drivers/spi/spi-rockchip.c
++++ b/drivers/spi/spi-rockchip.c
+@@ -767,7 +767,7 @@ static int rockchip_spi_enable_clocks(struct rockchip_spi *rs, bool en)
+ 		clk_disable_unprepare(rs->apb_pclk);
+ 	}
+ 
+-	rs->clk_enabled = en;
++	rs->clk_enabled = !!en;
+ 	return 0;
+ }
+ 
+@@ -814,6 +814,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 		return PTR_ERR(rs->spiclk);
+ 	}
+ 
++	rs->clk_enabled = true;
+ 	spi_enable_chip(rs, false);
+ 
+ 	ret = platform_get_irq(pdev, 0);
+@@ -922,7 +923,9 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 	pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
+ 	pm_runtime_use_autosuspend(&pdev->dev);
+ 	pm_runtime_set_active(&pdev->dev);
+-	pm_runtime_enable(&pdev->dev);
++	ret = devm_pm_runtime_enable(&pdev->dev);
++	if (ret < 0)
++		goto err_pm_disable;
+ 
+ 	ret = devm_spi_register_controller(&pdev->dev, ctlr);
+ 	if (ret < 0) {
+@@ -933,8 +936,6 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 	return 0;
+ 
+ err_pm_disable:
+-	pm_runtime_dont_use_autosuspend(&pdev->dev);
+-	pm_runtime_disable(&pdev->dev);
+ 	if (ctlr->dma_rx)
+ 		dma_release_channel(ctlr->dma_rx);
+ err_free_dma_tx:
+@@ -949,12 +950,6 @@ static void rockchip_spi_remove(struct platform_device *pdev)
+ 	struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
+ 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
+ 
+-	pm_runtime_get_sync(&pdev->dev);
+-	//pm_runtime_dont_use_autosuspend(&pdev->dev);
+-	pm_runtime_put_noidle(&pdev->dev);
+-	pm_runtime_disable(&pdev->dev);
+-	pm_runtime_set_suspended(&pdev->dev);
+-
+ 	if (ctlr->dma_tx)
+ 		dma_release_channel(ctlr->dma_tx);
+ 	if (ctlr->dma_rx)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch
new file mode 100644
index 000000000000..5210b9afd8f8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch
@@ -0,0 +1,274 @@
+From 3ef381e0974f0989a65f55c5dcaed30ebaf47c07 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 4 Nov 2023 18:22:31 +0100
+Subject: spi: rockchip: Fix runtime PM and other issues
+
+The driver didn't bother with proper error handling, or clock resource
+management, leading to warnings during suspend/resume.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/spi/spi-rockchip.c | 121 ++++++++++++++++++++-----------------
+ 1 file changed, 66 insertions(+), 55 deletions(-)
+
+diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
+index e1ecd96c7858..052dda891a40 100644
+--- a/drivers/spi/spi-rockchip.c
++++ b/drivers/spi/spi-rockchip.c
+@@ -196,6 +196,8 @@ struct rockchip_spi {
+ 	bool cs_high_supported; /* native CS supports active-high polarity */
+ 
+ 	struct spi_transfer *xfer; /* Store xfer temporarily */
++
++	bool clk_enabled;
+ };
+ 
+ static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
+@@ -740,6 +742,35 @@ static int rockchip_spi_setup(struct spi_device *spi)
+ 	return 0;
+ }
+ 
++static int rockchip_spi_enable_clocks(struct rockchip_spi *rs, bool en)
++{
++	int ret;
++
++        if (!!en == rs->clk_enabled)
++		return 0;
++
++	if (en) {
++		ret = clk_prepare_enable(rs->apb_pclk);
++		if (ret < 0) {
++			dev_err(rs->dev, "Failed to enable apb_pclk\n");
++			return ret;
++		}
++
++		ret = clk_prepare_enable(rs->spiclk);
++		if (ret < 0) {
++			dev_err(rs->dev, "Failed to enable spiclk\n");
++			clk_disable_unprepare(rs->apb_pclk);
++			return ret;
++		}
++	} else {
++		clk_disable_unprepare(rs->spiclk);
++		clk_disable_unprepare(rs->apb_pclk);
++	}
++
++	rs->clk_enabled = en;
++	return 0;
++}
++
+ static int rockchip_spi_probe(struct platform_device *pdev)
+ {
+ 	int ret;
+@@ -753,10 +784,10 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 	target_mode = of_property_read_bool(np, "spi-slave");
+ 
+ 	if (target_mode)
+-		ctlr = spi_alloc_target(&pdev->dev,
++		ctlr = devm_spi_alloc_target(&pdev->dev,
+ 				sizeof(struct rockchip_spi));
+ 	else
+-		ctlr = spi_alloc_host(&pdev->dev,
++		ctlr = devm_spi_alloc_host(&pdev->dev,
+ 				sizeof(struct rockchip_spi));
+ 
+ 	if (!ctlr)
+@@ -768,35 +799,31 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 
+ 	/* Get basic io resource and map it */
+ 	rs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
+-	if (IS_ERR(rs->regs)) {
+-		ret =  PTR_ERR(rs->regs);
+-		goto err_put_ctlr;
+-	}
++	if (IS_ERR(rs->regs))
++		return PTR_ERR(rs->regs);
+ 
+ 	rs->apb_pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
+ 	if (IS_ERR(rs->apb_pclk)) {
+ 		dev_err(&pdev->dev, "Failed to get apb_pclk\n");
+-		ret = PTR_ERR(rs->apb_pclk);
+-		goto err_put_ctlr;
++		return PTR_ERR(rs->apb_pclk);
+ 	}
+ 
+ 	rs->spiclk = devm_clk_get_enabled(&pdev->dev, "spiclk");
+ 	if (IS_ERR(rs->spiclk)) {
+ 		dev_err(&pdev->dev, "Failed to get spi_pclk\n");
+-		ret = PTR_ERR(rs->spiclk);
+-		goto err_put_ctlr;
++		return PTR_ERR(rs->spiclk);
+ 	}
+ 
+ 	spi_enable_chip(rs, false);
+ 
+ 	ret = platform_get_irq(pdev, 0);
+ 	if (ret < 0)
+-		goto err_put_ctlr;
++		return ret;
+ 
+ 	ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
+ 			IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
+ 	if (ret)
+-		goto err_put_ctlr;
++		return ret;
+ 
+ 	rs->dev = &pdev->dev;
+ 	rs->freq = clk_get_rate(rs->spiclk);
+@@ -821,15 +848,9 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 	rs->fifo_len = get_fifo_len(rs);
+ 	if (!rs->fifo_len) {
+ 		dev_err(&pdev->dev, "Failed to get fifo length\n");
+-		ret = -EINVAL;
+-		goto err_put_ctlr;
++		return -EINVAL;
+ 	}
+ 
+-	pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
+-	pm_runtime_use_autosuspend(&pdev->dev);
+-	pm_runtime_set_active(&pdev->dev);
+-	pm_runtime_enable(&pdev->dev);
+-
+ 	ctlr->auto_runtime_pm = true;
+ 	ctlr->bus_num = pdev->id;
+ 	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
+@@ -862,10 +883,8 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 	ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
+ 	if (IS_ERR(ctlr->dma_tx)) {
+ 		/* Check tx to see if we need defer probing driver */
+-		if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
+-			ret = -EPROBE_DEFER;
+-			goto err_disable_pm_runtime;
+-		}
++		if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
+ 		dev_warn(rs->dev, "Failed to request TX DMA channel\n");
+ 		ctlr->dma_tx = NULL;
+ 	}
+@@ -900,24 +919,27 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 		break;
+ 	}
+ 
++	pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
++	pm_runtime_use_autosuspend(&pdev->dev);
++	pm_runtime_set_active(&pdev->dev);
++	pm_runtime_enable(&pdev->dev);
++
+ 	ret = devm_spi_register_controller(&pdev->dev, ctlr);
+ 	if (ret < 0) {
+ 		dev_err(&pdev->dev, "Failed to register controller\n");
+-		goto err_free_dma_rx;
++		goto err_pm_disable;
+ 	}
+ 
+ 	return 0;
+ 
+-err_free_dma_rx:
++err_pm_disable:
++	pm_runtime_dont_use_autosuspend(&pdev->dev);
++	pm_runtime_disable(&pdev->dev);
+ 	if (ctlr->dma_rx)
+ 		dma_release_channel(ctlr->dma_rx);
+ err_free_dma_tx:
+ 	if (ctlr->dma_tx)
+ 		dma_release_channel(ctlr->dma_tx);
+-err_disable_pm_runtime:
+-	pm_runtime_disable(&pdev->dev);
+-err_put_ctlr:
+-	spi_controller_put(ctlr);
+ 
+ 	return ret;
+ }
+@@ -925,9 +947,10 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ static void rockchip_spi_remove(struct platform_device *pdev)
+ {
+ 	struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
++	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
+ 
+ 	pm_runtime_get_sync(&pdev->dev);
+-
++	//pm_runtime_dont_use_autosuspend(&pdev->dev);
+ 	pm_runtime_put_noidle(&pdev->dev);
+ 	pm_runtime_disable(&pdev->dev);
+ 	pm_runtime_set_suspended(&pdev->dev);
+@@ -937,7 +960,7 @@ static void rockchip_spi_remove(struct platform_device *pdev)
+ 	if (ctlr->dma_rx)
+ 		dma_release_channel(ctlr->dma_rx);
+ 
+-	spi_controller_put(ctlr);
++	rockchip_spi_enable_clocks(rs, true);
+ }
+ 
+ #ifdef CONFIG_PM_SLEEP
+@@ -951,8 +974,8 @@ static int rockchip_spi_suspend(struct device *dev)
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	clk_disable_unprepare(rs->spiclk);
+-	clk_disable_unprepare(rs->apb_pclk);
++	pm_runtime_disable(dev);
++	rockchip_spi_enable_clocks(rs, false);
+ 
+ 	pinctrl_pm_select_sleep_state(dev);
+ 
+@@ -967,19 +990,17 @@ static int rockchip_spi_resume(struct device *dev)
+ 
+ 	pinctrl_pm_select_default_state(dev);
+ 
+-	ret = clk_prepare_enable(rs->apb_pclk);
+-	if (ret < 0)
+-		return ret;
++	if (!pm_runtime_status_suspended(dev)) {
++		ret = rockchip_spi_enable_clocks(rs, true);
++		if (ret < 0)
++			return ret;
++	}
+ 
+-	ret = clk_prepare_enable(rs->spiclk);
+-	if (ret < 0)
+-		clk_disable_unprepare(rs->apb_pclk);
++	pm_runtime_enable(dev);
+ 
+ 	ret = spi_controller_resume(ctlr);
+-	if (ret < 0) {
+-		clk_disable_unprepare(rs->spiclk);
+-		clk_disable_unprepare(rs->apb_pclk);
+-	}
++	if (ret < 0)
++		return ret;
+ 
+ 	return 0;
+ }
+@@ -991,27 +1012,17 @@ static int rockchip_spi_runtime_suspend(struct device *dev)
+ 	struct spi_controller *ctlr = dev_get_drvdata(dev);
+ 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
+ 
+-	clk_disable_unprepare(rs->spiclk);
+-	clk_disable_unprepare(rs->apb_pclk);
++	rockchip_spi_enable_clocks(rs, false);
+ 
+ 	return 0;
+ }
+ 
+ static int rockchip_spi_runtime_resume(struct device *dev)
+ {
+-	int ret;
+ 	struct spi_controller *ctlr = dev_get_drvdata(dev);
+ 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
+ 
+-	ret = clk_prepare_enable(rs->apb_pclk);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = clk_prepare_enable(rs->spiclk);
+-	if (ret < 0)
+-		clk_disable_unprepare(rs->apb_pclk);
+-
+-	return 0;
++	return rockchip_spi_enable_clocks(rs, true);
+ }
+ #endif /* CONFIG_PM */
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
new file mode 100644
index 000000000000..c164d372de85
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
@@ -0,0 +1,150 @@
+From 97a7d0c8a6fda9710f7b62563c31184592c501a7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 2 Sep 2019 14:51:17 +0200
+Subject: sunxi: Use dev_err_probe to handle EPROBE_DEFER errors
+
+This makes it easier to debug EPROBE_DEFER issues via debugfs.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/kernel/topology.c                    |  2 +-
+ drivers/gpu/drm/panel/panel-sitronix-st7703.c |  2 +-
+ drivers/i2c/busses/i2c-gpio.c                 | 11 +++++++++--
+ drivers/phy/allwinner/phy-sun4i-usb.c         | 16 ++++++++++------
+ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c   |  6 ++++--
+ 5 files changed, 25 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
+index 2336ee2aa44a..20efde3cb1c2 100644
+--- a/arch/arm/kernel/topology.c
++++ b/arch/arm/kernel/topology.c
+@@ -121,7 +121,7 @@ static void __init parse_dt_topology(void)
+ 
+ 		rate = of_get_property(cn, "clock-frequency", &len);
+ 		if (!rate || len != 4) {
+-			pr_err("%pOF missing clock-frequency property\n", cn);
++			//pr_err("%pOF missing clock-frequency property\n", cn);
+ 			continue;
+ 		}
+ 
+diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+index 22329bfdcacc..0efe925760d8 100644
+--- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+@@ -944,7 +944,7 @@ static int st7703_probe(struct mipi_dsi_device *dsi)
+ 
+ 	ret = mipi_dsi_attach(dsi);
+ 	if (ret < 0) {
+-		dev_err(dev, "mipi_dsi_attach failed (%d). Is host ready?\n", ret);
++		dev_err_probe(dev, ret, "mipi_dsi_attach failed\n");
+ 		drm_panel_remove(&ctx->panel);
+ 		return ret;
+ 	}
+diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
+index 4f1411b1a775..ad9399376a09 100644
+--- a/drivers/i2c/busses/i2c-gpio.c
++++ b/drivers/i2c/busses/i2c-gpio.c
+@@ -314,6 +314,13 @@ static struct gpio_desc *i2c_gpio_get_desc(struct device *dev,
+ 		return retdesc;
+ 	}
+ 
++	/* return early so that EPROBE_DEFER is not ignored on named gpios */
++	if (PTR_ERR(retdesc) == -EPROBE_DEFER) {
++		dev_err_probe(dev, PTR_ERR(retdesc),
++			      "error trying to get descriptor\n");
++		return retdesc;
++	}
++
+ 	retdesc = devm_gpiod_get_index(dev, NULL, index, gflags);
+ 	if (!IS_ERR(retdesc)) {
+ 		dev_dbg(dev, "got GPIO from index %u\n", index);
+@@ -330,8 +337,8 @@ static struct gpio_desc *i2c_gpio_get_desc(struct device *dev,
+ 	if (ret == -ENOENT)
+ 		retdesc = ERR_PTR(-EPROBE_DEFER);
+ 
+-	if (PTR_ERR(retdesc) != -EPROBE_DEFER)
+-		dev_err(dev, "error trying to get descriptor: %d\n", ret);
++	dev_err_probe(dev, PTR_ERR(retdesc),
++		      "error trying to get descriptor\n");
+ 
+ 	return retdesc;
+ }
+diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
+index 9b6b68eb00f8..be63d60ce738 100644
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -775,14 +775,16 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 	data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det",
+ 						    GPIOD_IN);
+ 	if (IS_ERR(data->id_det_gpio)) {
+-		dev_err(dev, "Couldn't request ID GPIO\n");
++		dev_err_probe(dev, PTR_ERR(data->id_det_gpio),
++			      "Couldn't request ID GPIO\n");
+ 		return PTR_ERR(data->id_det_gpio);
+ 	}
+ 
+ 	data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det",
+ 						      GPIOD_IN);
+ 	if (IS_ERR(data->vbus_det_gpio)) {
+-		dev_err(dev, "Couldn't request VBUS detect GPIO\n");
++		dev_err_probe(dev, PTR_ERR(data->vbus_det_gpio),
++			      "Couldn't request VBUS detect GPIO\n");
+ 		return PTR_ERR(data->vbus_det_gpio);
+ 	}
+ 
+@@ -790,7 +792,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
+ 						     "usb0_vbus_power-supply");
+ 		if (IS_ERR(data->vbus_power_supply)) {
+-			dev_err(dev, "Couldn't get the VBUS power supply\n");
++			dev_err_probe(dev, PTR_ERR(data->vbus_power_supply),
++				      "Couldn't get the VBUS power supply\n");
+ 			return PTR_ERR(data->vbus_power_supply);
+ 		}
+ 
+@@ -823,8 +826,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		phy->vbus = devm_regulator_get_optional(dev, name);
+ 		if (IS_ERR(phy->vbus)) {
+ 			if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
+-				dev_err(dev,
+-					"Couldn't get regulator %s... Deferring probe\n",
++				dev_err_probe(dev, PTR_ERR(phy->vbus),
++					"Couldn't get regulator %s\n",
+ 					name);
+ 				return -EPROBE_DEFER;
+ 			}
+@@ -839,7 +842,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 
+ 		phy->clk = devm_clk_get(dev, name);
+ 		if (IS_ERR(phy->clk)) {
+-			dev_err(dev, "failed to get clock %s\n", name);
++			dev_err_probe(dev, PTR_ERR(phy->clk),
++				      "failed to get clock %s\n", name);
+ 			return PTR_ERR(phy->clk);
+ 		}
+ 
+diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+index a19a27cea860..0107514e7d2b 100644
+--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
++++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+@@ -584,13 +584,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
+ 	dphy->regs = devm_regmap_init_mmio_clk(&pdev->dev, "bus",
+ 					       regs, &sun6i_dphy_regmap_config);
+ 	if (IS_ERR(dphy->regs)) {
+-		dev_err(&pdev->dev, "Couldn't create the DPHY encoder regmap\n");
++		dev_err_probe(&pdev->dev, PTR_ERR(dphy->regs),
++			      "Couldn't create the DPHY encoder regmap\n");
+ 		return PTR_ERR(dphy->regs);
+ 	}
+ 
+ 	dphy->reset = devm_reset_control_get_shared(&pdev->dev, NULL);
+ 	if (IS_ERR(dphy->reset)) {
+-		dev_err(&pdev->dev, "Couldn't get our reset line\n");
++		dev_err_probe(&pdev->dev, PTR_ERR(dphy->reset),
++			      "Couldn't get our reset line\n");
+ 		return PTR_ERR(dphy->reset);
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
new file mode 100644
index 000000000000..d804d65649af
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
@@ -0,0 +1,88 @@
+From 74a42cd040f7f000fb75a078aed46f752379ac56 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Jul 2020 12:21:14 +0200
+Subject: thermal: sun8i: Be loud when probe fails
+
+I noticed several mobile Linux distributions failing to enable the
+thermal regulation correctly, because the kernel is silent
+when thermal driver fails to probe. Add enough error reporting
+to debug issues and warn users in case thermal sensor is failing
+to probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/thermal/sun8i_thermal.c | 22 +++++++++++++++++++---
+ 1 file changed, 19 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
+index 3203d8bd13a8..c6a82ef84aca 100644
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -308,8 +308,13 @@ static int sun8i_ths_calibrate(struct ths_device *tmdev)
+ 
+ 	calcell = nvmem_cell_get(dev, "calibration");
+ 	if (IS_ERR(calcell)) {
++		dev_err_probe(dev, PTR_ERR(calcell),
++			      "Failed to get calibration nvmem cell (%pe)\n",
++			      calcell);
++
+ 		if (PTR_ERR(calcell) == -EPROBE_DEFER)
+ 			return -EPROBE_DEFER;
++
+ 		/*
+ 		 * Even if the external calibration data stored in sid is
+ 		 * not accessible, the THS hardware can still work, although
+@@ -329,6 +334,8 @@ static int sun8i_ths_calibrate(struct ths_device *tmdev)
+ 	caldata = nvmem_cell_read(calcell, &callen);
+ 	if (IS_ERR(caldata)) {
+ 		ret = PTR_ERR(caldata);
++		dev_err(dev, "Failed to read calibration data (%pe)\n",
++			caldata);
+ 		goto out;
+ 	}
+ 
+@@ -386,13 +393,17 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
+ 		return PTR_ERR(base);
+ 
+ 	tmdev->regmap = devm_regmap_init_mmio(dev, base, &config);
+-	if (IS_ERR(tmdev->regmap))
++	if (IS_ERR(tmdev->regmap)) {
++		dev_err(dev, "Failed to init regmap (%pe)\n", tmdev->regmap);
+ 		return PTR_ERR(tmdev->regmap);
++	}
+ 
+ 	if (tmdev->chip->has_bus_clk_reset) {
+ 		tmdev->reset = devm_reset_control_get(dev, NULL);
+-		if (IS_ERR(tmdev->reset))
++		if (IS_ERR(tmdev->reset)) {
++			dev_err(dev, "Failed to get reset (%pe)\n", tmdev->reset);
+ 			return PTR_ERR(tmdev->reset);
++		}
+ 
+ 		ret = reset_control_deassert(tmdev->reset);
+ 		if (ret)
+@@ -543,6 +554,9 @@ static int sun8i_ths_register(struct ths_device *tmdev)
+ 		if (IS_ERR(tmdev->sensor[i].tzd)) {
+ 			if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
+ 				return PTR_ERR(tmdev->sensor[i].tzd);
++			dev_err(tmdev->dev,
++				"Failed to register sensor %d (%pe)\n",
++				i, tmdev->sensor[i].tzd);
+ 			continue;
+ 		}
+ 
+@@ -591,8 +605,10 @@ static int sun8i_ths_probe(struct platform_device *pdev)
+ 	ret = devm_request_threaded_irq(dev, irq, NULL,
+ 					sun8i_irq_thread,
+ 					IRQF_ONESHOT, "ths", tmdev);
+-	if (ret)
++	if (ret) {
++		dev_err(dev, "Failed to request irq (%d)\n", ret);
+ 		return ret;
++	}
+ 
+ 	return 0;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
new file mode 100644
index 000000000000..414d6d5444dd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
@@ -0,0 +1,206 @@
+From 10447507ecb1da6e4314ea178b47308963c2ba1c Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 7 Sep 2023 14:07:26 +0200
+Subject: usb: gadget: Fix dangling pointer in netdev private data
+
+Some USB drivers destroy and re-create the gadget regularly. This
+leads to stale gadget pointer in gether_* using USB gadget functions
+(ecm, eem, ncm, rndis, etc.).
+
+Don't parent the netdev to the gadget device, and set gadget to
+NULL in function unbind callback, to avoid potential user-after-free
+issues.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/gadget/function/f_ecm.c    |  6 +++++-
+ drivers/usb/gadget/function/f_eem.c    | 10 +++++++++-
+ drivers/usb/gadget/function/f_ncm.c    |  4 ++++
+ drivers/usb/gadget/function/f_rndis.c  | 13 +++++++++++--
+ drivers/usb/gadget/function/f_subset.c | 10 +++++++++-
+ drivers/usb/gadget/function/u_ether.c  |  4 ----
+ 6 files changed, 38 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/gadget/function/f_ecm.c b/drivers/usb/gadget/function/f_ecm.c
+index f55f60639e42..e331cc64390b 100644
+--- a/drivers/usb/gadget/function/f_ecm.c
++++ b/drivers/usb/gadget/function/f_ecm.c
+@@ -907,7 +907,9 @@ static void ecm_free(struct usb_function *f)
+ 
+ static void ecm_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
+-	struct f_ecm		*ecm = func_to_ecm(f);
++	struct f_ecm *ecm = func_to_ecm(f);
++	struct f_ecm_opts *opts = container_of(f->fi, struct f_ecm_opts,
++					       func_inst);
+ 
+ 	DBG(c->cdev, "ecm unbind\n");
+ 
+@@ -920,6 +922,8 @@ static void ecm_unbind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	kfree(ecm->notify_req->buf);
+ 	usb_ep_free_request(ecm->notify, ecm->notify_req);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *ecm_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_eem.c b/drivers/usb/gadget/function/f_eem.c
+index 3b445bd88498..6382cd138d20 100644
+--- a/drivers/usb/gadget/function/f_eem.c
++++ b/drivers/usb/gadget/function/f_eem.c
+@@ -260,9 +260,12 @@ static int eem_bind(struct usb_configuration *c, struct usb_function *f)
+ 	 * with list_for_each_entry, so we assume no race condition
+ 	 * with regard to eem_opts->bound access
+ 	 */
++	mutex_lock(&eem_opts->lock);
++	gether_set_gadget(eem_opts->net, cdev->gadget);
++	mutex_unlock(&eem_opts->lock);
++
+ 	if (!eem_opts->bound) {
+ 		mutex_lock(&eem_opts->lock);
+-		gether_set_gadget(eem_opts->net, cdev->gadget);
+ 		status = gether_register_netdev(eem_opts->net);
+ 		mutex_unlock(&eem_opts->lock);
+ 		if (status)
+@@ -635,9 +638,14 @@ static void eem_free(struct usb_function *f)
+ 
+ static void eem_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
++	struct f_eem_opts *opts = container_of(f->fi, struct f_eem_opts,
++					       func_inst);
++
+ 	DBG(c->cdev, "eem unbind\n");
+ 
+ 	usb_free_all_descriptors(f);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *eem_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c
+index 0acc32ed9960..5e8659050d36 100644
+--- a/drivers/usb/gadget/function/f_ncm.c
++++ b/drivers/usb/gadget/function/f_ncm.c
+@@ -1728,6 +1728,8 @@ static void ncm_free(struct usb_function *f)
+ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
+ 	struct f_ncm *ncm = func_to_ncm(f);
++	struct f_ncm_opts *opts = container_of(f->fi, struct f_ncm_opts,
++					       func_inst);
+ 
+ 	DBG(c->cdev, "ncm unbind\n");
+ 
+@@ -1746,6 +1748,8 @@ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	kfree(ncm->notify_req->buf);
+ 	usb_ep_free_request(ncm->notify, ncm->notify_req);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *ncm_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_rndis.c b/drivers/usb/gadget/function/f_rndis.c
+index b47f99d17ee9..a15dfb8e6f01 100644
+--- a/drivers/usb/gadget/function/f_rndis.c
++++ b/drivers/usb/gadget/function/f_rndis.c
+@@ -688,9 +688,14 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f)
+ 	 * with list_for_each_entry, so we assume no race condition
+ 	 * with regard to rndis_opts->bound access
+ 	 */
++	mutex_lock(&rndis_opts->lock);
++	gether_set_gadget(rndis_opts->net, cdev->gadget);
++	mutex_unlock(&rndis_opts->lock);
++
+ 	if (!rndis_opts->bound) {
+-		gether_set_gadget(rndis_opts->net, cdev->gadget);
++		mutex_lock(&rndis_opts->lock);
+ 		status = gether_register_netdev(rndis_opts->net);
++		mutex_unlock(&rndis_opts->lock);
+ 		if (status)
+ 			goto fail;
+ 		rndis_opts->bound = true;
+@@ -954,7 +959,9 @@ static void rndis_free(struct usb_function *f)
+ 
+ static void rndis_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
+-	struct f_rndis		*rndis = func_to_rndis(f);
++	struct f_rndis *rndis = func_to_rndis(f);
++	struct f_rndis_opts *opts = container_of(f->fi, struct f_rndis_opts,
++						 func_inst);
+ 
+ 	kfree(f->os_desc_table);
+ 	f->os_desc_n = 0;
+@@ -962,6 +969,8 @@ static void rndis_unbind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	kfree(rndis->notify_req->buf);
+ 	usb_ep_free_request(rndis->notify, rndis->notify_req);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *rndis_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_subset.c b/drivers/usb/gadget/function/f_subset.c
+index 8ae9689ef2a0..70448dd67812 100644
+--- a/drivers/usb/gadget/function/f_subset.c
++++ b/drivers/usb/gadget/function/f_subset.c
+@@ -308,9 +308,12 @@ geth_bind(struct usb_configuration *c, struct usb_function *f)
+ 	 * with list_for_each_entry, so we assume no race condition
+ 	 * with regard to gether_opts->bound access
+ 	 */
++	mutex_lock(&gether_opts->lock);
++	gether_set_gadget(gether_opts->net, cdev->gadget);
++	mutex_unlock(&gether_opts->lock);
++
+ 	if (!gether_opts->bound) {
+ 		mutex_lock(&gether_opts->lock);
+-		gether_set_gadget(gether_opts->net, cdev->gadget);
+ 		status = gether_register_netdev(gether_opts->net);
+ 		mutex_unlock(&gether_opts->lock);
+ 		if (status)
+@@ -456,8 +459,13 @@ static void geth_free(struct usb_function *f)
+ 
+ static void geth_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
++	struct f_gether_opts *opts = container_of(f->fi, struct f_gether_opts,
++						  func_inst);
++
+ 	geth_string_defs[0].id = 0;
+ 	usb_free_all_descriptors(f);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *geth_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c
+index 95191083b455..1565d2239a34 100644
+--- a/drivers/usb/gadget/function/u_ether.c
++++ b/drivers/usb/gadget/function/u_ether.c
+@@ -787,7 +787,6 @@ struct eth_dev *gether_setup_name(struct usb_gadget *g,
+ 	net->max_mtu = GETHER_MAX_MTU_SIZE;
+ 
+ 	dev->gadget = g;
+-	SET_NETDEV_DEV(net, &g->dev);
+ 	SET_NETDEV_DEVTYPE(net, &gadget_type);
+ 
+ 	status = register_netdev(net);
+@@ -860,8 +859,6 @@ int gether_register_netdev(struct net_device *net)
+ 	struct usb_gadget *g;
+ 	int status;
+ 
+-	if (!net->dev.parent)
+-		return -EINVAL;
+ 	dev = netdev_priv(net);
+ 	g = dev->gadget;
+ 
+@@ -892,7 +889,6 @@ void gether_set_gadget(struct net_device *net, struct usb_gadget *g)
+ 
+ 	dev = netdev_priv(net);
+ 	dev->gadget = g;
+-	SET_NETDEV_DEV(net, &g->dev);
+ }
+ EXPORT_SYMBOL_GPL(gether_set_gadget);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
new file mode 100644
index 000000000000..754613053f88
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
@@ -0,0 +1,107 @@
+From 374caa8b180fb8f8e6d9607c9f5faf1ea76b57e5 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 6 Mar 2023 01:19:52 +0100
+Subject: usb: musb: sunxi: Avoid enabling host side code on SoCs where it's
+ not used
+
+For some sunxi SoCs host side code is active but unused, because
+phy re-routes USB handling to a regular EHCI/OHCI driver.
+
+When host side code of musb is left initialized it sometimes
+interferes with suspend to RAM. Disabling the host side code
+on SoCs that re-route host mode to a regular *HCI hardware
+block fixes the issue.
+
+Issue: https://gitlab.com/postmarketOS/pmaports/-/issues/1478
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/musb/musb_core.c | 10 ++++++++++
+ drivers/usb/musb/sunxi.c     | 30 +++++++++++++++++++++++-------
+ 2 files changed, 33 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index b24adb5b399f..8b3ad9101180 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -975,6 +975,16 @@ static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
+ 	case OTG_STATE_B_IDLE:
+ 		musb_g_disconnect(musb);
+ 		break;
++	case OTG_STATE_A_WAIT_VRISE:
++		/*
++		 * For sunxi use case, where host side of the musb driver
++		 * is not used for host mode, we want to ignore
++		 * OTG_STATE_A_WAIT_VRISE state set in sunxi glue code
++		 * when transitioning to host mode on disconnect, in
++		 * order to not confuse the dmesg reader about possible
++		 * issues.
++		 */
++		break;
+ 	default:
+ 		WARNING("unhandled DISCONNECT transition (%s)\n",
+ 			musb_otg_state_string(musb));
+diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
+index d54283fd026b..7e7703de28a3 100644
+--- a/drivers/usb/musb/sunxi.c
++++ b/drivers/usb/musb/sunxi.c
+@@ -352,12 +352,6 @@ static int sunxi_musb_set_mode(struct musb *musb, u8 mode)
+ 	if (glue->phy_mode == new_mode)
+ 		return 0;
+ 
+-	if (musb->port_mode != MUSB_OTG) {
+-		dev_err(musb->controller->parent,
+-			"Error changing modes is only supported in dual role mode\n");
+-		return -EINVAL;
+-	}
+-
+ 	if (musb->port1_status & USB_PORT_STAT_ENABLE)
+ 		musb_root_disconnect(musb);
+ 
+@@ -676,13 +670,22 @@ static const struct musb_hdrc_config sunxi_musb_hdrc_config_4eps = {
+ 	.ram_bits	= SUNXI_MUSB_RAM_BITS,
+ };
+ 
++static const char * const sunxi_musb_host_rerouted_phys[] = {
++	"allwinner,sun8i-h3-usb-phy",
++	"allwinner,sun8i-r40-usb-phy",
++	"allwinner,sun8i-v3s-usb-phy",
++	"allwinner,sun50i-a64-usb-phy",
++	"allwinner,sun50i-h6-usb-phy",
++	NULL,
++};
++
+ static int sunxi_musb_probe(struct platform_device *pdev)
+ {
+ 	struct musb_hdrc_platform_data	pdata;
+ 	struct platform_device_info	pinfo;
+ 	struct sunxi_glue		*glue;
+-	struct device_node		*np = pdev->dev.of_node;
+ 	const struct sunxi_musb_cfg	*cfg;
++	struct device_node		*np = pdev->dev.of_node, *phy_np;
+ 	int ret;
+ 
+ 	if (!np) {
+@@ -763,6 +766,19 @@ static int sunxi_musb_probe(struct platform_device *pdev)
+ 		return dev_err_probe(&pdev->dev, PTR_ERR(glue->phy),
+ 				     "Error getting phy\n");
+ 
++	/*
++	 * Host mode is handled outside of the musb driver on some allwinner
++	 * SoCs. We don't need musb host side code to be enabled at all.
++	 * In fact it causes occasional issues with suspend to ram, when
++	 * the host side code is enabled and unused (due to phy being re-routed
++	 * to a different *HCI controller).
++	 */
++	phy_np = glue->phy->dev.of_node;
++	if (of_device_compatible_match(phy_np, sunxi_musb_host_rerouted_phys)) {
++		dev_info(&pdev->dev, "Disabling musb host side code due to re-routed phy\n");
++		pdata.mode = MUSB_PERIPHERAL;
++	}
++
+ 	glue->usb_phy = usb_phy_generic_register();
+ 	if (IS_ERR(glue->usb_phy)) {
+ 		dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
new file mode 100644
index 000000000000..383af8d2be47
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
@@ -0,0 +1,33 @@
+From d8e8b0c058e907df2290d4ee9464cbf09c8daf81 Mon Sep 17 00:00:00 2001
+From: Thomas Thorne <Thomas.Thorne@Net2Edge.com>
+Date: Tue, 20 Sep 2022 20:34:57 -0400
+Subject: usb: serial: option: add 'reset_resume' callback for WWAN devices
+
+This avoids the issue where the PPP modem does not reset correctly on resume,
+causing issues with incoming calls on suspend.
+
+Noted here: https://github.com/the-modem-distro/pinephone_modem_sdk/issues/97
+
+This is part of a larger patch:
+https://github.com/Quectel-Community/meta-quectel-community/commit/24adef2128f79b4d31490634438a917b3df462e2#diff-45dc5960ca2f1ef57139fe751587b3b043de9cca5864e2801210c00e75bd0780
+
+However the rest of the patch is not needed/already upstreamed.
+---
+ drivers/usb/serial/option.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
+index 311040f9b935..75528309851f 100644
+--- a/drivers/usb/serial/option.c
++++ b/drivers/usb/serial/option.c
+@@ -2399,6 +2399,7 @@ static struct usb_serial_driver option_1port_device = {
+ #ifdef CONFIG_PM
+ 	.suspend           = usb_wwan_suspend,
+ 	.resume            = usb_wwan_resume,
++	.reset_resume	   = usb_wwan_resume,
+ #endif
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
new file mode 100644
index 000000000000..17859c9b1ab0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
@@ -0,0 +1,98 @@
+From 21d7014125e8214ac91cda87bb1e2c05f6403ca4 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 5 Sep 2022 00:56:07 +0200
+Subject: usb: typec: altmodes: displayport: Respect DP_CAP_RECEPTACLE bit
+
+DP_CAP_RECEPTACLE swaps the meaning of pin assignments. So eg.
+pin assignments for DFP_D plug are stored in DP_CAP_UFP_D_PIN_ASSIGN
+bits. Yes, it's slightly confusing. :)
+
+Make the kernel report lack of match in supported pin configurations
+between connected ports, so that the user is not confused why their
+USB-C dock doesn't have working Alt-DP mode, in case the dock returns
+wrong VDO.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/altmodes/displayport.c | 48 ++++++++++++++++++++++--
+ 1 file changed, 44 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c
+index 596cd4806018..6cdf87d8f927 100644
+--- a/drivers/usb/typec/altmodes/displayport.c
++++ b/drivers/usb/typec/altmodes/displayport.c
+@@ -116,11 +116,29 @@ static int dp_altmode_configure(struct dp_altmode *dp, u8 con)
+ 		/* Account for active cable capabilities */
+ 		if (dp->plug_prime)
+ 			pin_assign &= DP_CAP_UFP_D_PIN_ASSIGN(dp->plug_prime->vdo);
++
++		/*
++		 * The Display Port Alt mode standard is not publicly available,
++		 * so this is based on guesswork and real VDOs received from
++		 * receptacle based and plug based Type-C alt mode supporting
++		 * docks to make configuration work in practice:
++		 *
++		 * Plug (captive cable) based dock: port=c46 alt=c05
++		 * Recpetacle based dock: port=c46 alt=c0045
++		 *
++		pin_assign = DP_CAP_DFP_D_PIN_ASSIGN(dp->port->vdo);
++		pin_assign &= dp->alt->vdo & DP_CAP_RECEPTACLE ?
++			DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo) :
++			DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
++		 */
+ 		break;
+ 	default:
+ 		break;
+ 	}
+ 
++	dev_info(&dp->alt->dev, "con=%d pin_assign=%x (port=%x alt=%x)\n",
++		 (int)con, (unsigned)pin_assign, dp->port->vdo, dp->alt->vdo);
++
+ 	/* Determining the initial pin assignment. */
+ 	if (!DP_CONF_GET_PIN_ASSIGN(dp->data.conf)) {
+ 		/* Is USB together with DP preferred */
+@@ -726,15 +744,37 @@ int dp_altmode_probe(struct typec_altmode *alt)
+ 	struct typec_altmode *plug = typec_altmode_get_plug(alt, TYPEC_PLUG_SOP_P);
+ 	struct fwnode_handle *fwnode;
+ 	struct dp_altmode *dp;
++	u32 port_pins, alt_pins;
+ 
+ 	/* FIXME: Port can only be DFP_U. */
+ 
++	/*
++	 * When port is a receptacle DP_CAP_xFP_D_PIN_ASSIGN macros have the
++	 * regular meaning. When the port is a plug, the meaning is swapped.
++	 *
++	 * Check if we have any matching DFP_D<->UFP_D or UFP_D<->DFP_D pin assignment.
++	 */
++        port_pins = port->vdo & DP_CAP_RECEPTACLE ?
++		DP_CAP_DFP_D_PIN_ASSIGN(port->vdo) | DP_CAP_UFP_D_PIN_ASSIGN(port->vdo) << 8 :
++		DP_CAP_UFP_D_PIN_ASSIGN(port->vdo) | DP_CAP_DFP_D_PIN_ASSIGN(port->vdo) << 8;
++
++        alt_pins = alt->vdo & DP_CAP_RECEPTACLE ?
++		DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo) | DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo) << 8 :
++		DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo) | DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo) << 8;
++
++	/* Can't plug plug into a plug */
++	if (!(port->vdo & DP_CAP_RECEPTACLE) && !(alt->vdo & DP_CAP_RECEPTACLE)) {
++		dev_warn(&alt->dev, "Our Alt-DP VDO 0x%06x and peer port VDO 0x%06x are not compatible (both are reported as plugs!)\n",
++			 port->vdo, alt->vdo);
++		return -ENODEV;
++	}
++
+ 	/* Make sure we have compatiple pin configurations */
+-	if (!(DP_CAP_PIN_ASSIGN_DFP_D(port->vdo) &
+-	      DP_CAP_PIN_ASSIGN_UFP_D(alt->vdo)) &&
+-	    !(DP_CAP_PIN_ASSIGN_UFP_D(port->vdo) &
+-	      DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo)))
++	if (!(port_pins & alt_pins)) {
++		dev_warn(&alt->dev, "Our Alt-DP VDO 0x%06x and peer port VDO 0x%06x are not compatible (no shared pinconf %04x<->%04x (UUDD))\n",
++			 port->vdo, alt->vdo, port_pins, alt_pins);
+ 		return -ENODEV;
++	}
+ 
+ 	dp = devm_kzalloc(&alt->dev, sizeof(*dp), GFP_KERNEL);
+ 	if (!dp)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
new file mode 100644
index 000000000000..e904b7d93719
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
@@ -0,0 +1,2333 @@
+From 7b02ebbd231e891436e990d32a4871c2f9eec039 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 13 Feb 2020 15:37:25 +0100
+Subject: usb: typec: anx7688: Add driver for ANX7688 USB-C HDMI bridge
+
+The driver is now ready for some testing with more USB-C devices.
+It supports data and power role switching properly on all PinePhone
+variants, that have the HW mod: https://xnux.eu/devices/pp-usbc-fix.jpg.
+
+- fix possibly unbalanced connect/disconnect
+- better cabledet interrupt handling
+  - handle connect/disconnect in a workqueue
+  - debounce cabledet changes
+- send PDO to the right i2c address
+- proper error handling where it matters the most
+- proper locking
+- handle power supplies
+- handle inital connection/cable status after driver probe
+  not just on cabledet change
+- handle software interrupts from OCM
+- allow to update OCM firmware via sysfs
+- allow to dump OCM firmware via debugfs
+- allow to dump registers via debugfs
+- hook into allwinner usb phy driver to handle change in
+  data role (via usb_role_switch)
+- handle vbus/vconn enable/disable based on firmware
+  requests
+- proper cleanup of resources on driver unload
+
+Todo:
+- tell PMIC what USB input current limit to set based on
+  PD messages from firmware
+- add support for manual data/power role setting for devices
+  without the HW mod
+
+Signed-off-by: Martijn Braam <martijn@brixit.nl>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/Kconfig   |   12 +
+ drivers/usb/typec/Makefile  |    1 +
+ drivers/usb/typec/anx7688.c | 2237 +++++++++++++++++++++++++++++++++++
+ 3 files changed, 2250 insertions(+)
+ create mode 100644 drivers/usb/typec/anx7688.c
+
+diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig
+index 2f80c2792dbd..982b7c444a1f 100644
+--- a/drivers/usb/typec/Kconfig
++++ b/drivers/usb/typec/Kconfig
+@@ -52,6 +52,7 @@ source "drivers/usb/typec/ucsi/Kconfig"
+ 
+ source "drivers/usb/typec/tipd/Kconfig"
+ 
++
+ config TYPEC_ANX7411
+ 	tristate "Analogix ANX7411 Type-C DRP Port controller driver"
+ 	depends on I2C
+@@ -64,6 +65,17 @@ config TYPEC_ANX7411
+ 	  If you choose to build this driver as a dynamically linked module, the
+ 	  module will be called anx7411.ko.
+ 
++config TYPEC_ANX7688
++	tristate "Analogix ANX7688 Type-C DRP Port controller and mux driver"
++	depends on I2C
++	depends on USB_ROLE_SWITCH
++	help
++	  Say Y or M here if your system has Analogix ANX7688 Type-C Bridge
++	  controller driver.
++
++	  If you choose to build this driver as a dynamically linked module, the
++	  module will be called anx7688.ko.
++
+ config TYPEC_RT1719
+ 	tristate "Richtek RT1719 Sink Only Type-C controller driver"
+ 	depends on USB_ROLE_SWITCH || !USB_ROLE_SWITCH
+diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile
+index 7a368fea61bc..3f8ff94ad294 100644
+--- a/drivers/usb/typec/Makefile
++++ b/drivers/usb/typec/Makefile
+@@ -7,6 +7,7 @@ obj-$(CONFIG_TYPEC_TCPM)	+= tcpm/
+ obj-$(CONFIG_TYPEC_UCSI)	+= ucsi/
+ obj-$(CONFIG_TYPEC_TPS6598X)	+= tipd/
+ obj-$(CONFIG_TYPEC_ANX7411)	+= anx7411.o
++obj-$(CONFIG_TYPEC_ANX7688)	+= anx7688.o
+ obj-$(CONFIG_TYPEC_HD3SS3220)	+= hd3ss3220.o
+ obj-$(CONFIG_TYPEC_STUSB160X) 	+= stusb160x.o
+ obj-$(CONFIG_TYPEC_RT1719)	+= rt1719.o
+diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c
+new file mode 100644
+index 000000000000..fa1d3496af73
+--- /dev/null
++++ b/drivers/usb/typec/anx7688.c
+@@ -0,0 +1,2237 @@
++/*
++ * ANX7688 USB-C HDMI bridge/PD driver
++ *
++ * Warning, this driver is somewhat PinePhone specific.
++ *
++ * How this works:
++ * - this driver allows to program firmware into ANX7688 EEPROM, and
++ *   initialize it
++ * - it then communicates with the firmware running on the OCM (on-chip
++ *   microcontroller)
++ * - it detects whether there is cable plugged in or not and powers
++ *   up or down the ANX7688 based on that
++ * - when the cable is connected the firmware on the OCM will handle
++ *   the detection of the nature of the device on the other end
++ *   of the USB-C cable
++ * - this driver then communicates with the USB phy to let it swap
++ *   data roles accordingly
++ * - it also enables VBUS and VCONN regulators as appropriate
++ * - USB phy driver (Allwinner) needs to know whether to switch to
++ *   device or host mode, or whether to turn off
++ * - when the firmware detects SRC.1.5A or SRC.3.0A via CC pins
++ *   or something else via PD, it notifies this driver via software
++ *   interrupt and this driver will determine how to update the TypeC
++ *   port status and what input current limit is appropriate
++ * - input current limit determination happens 500ms after cable
++ *   insertion or hard reset (delay is necessary to determine whether
++ *   the remote end is PD capable or not)
++ * - this driver tells to the PMIC driver that the input current limit
++ *   needs to be changed
++ * - this driver also monitors PMIC status and re-sets the input current
++ *   limit if it changes for some reason (due to PMIC internal decision
++ *   making) (this is disabled for now)
++ *
++ * ANX7688 FW behavior as observed:
++ *
++ * - DO NOT SET MORE THAN 1 SINK CAPABILITY! Firmware will ignore what
++ *   you set and send hardcoded PDO_BATT 5-21V 30W message!
++ */
++
++#define DEBUG
++
++#include <linux/debugfs.h>
++#include <linux/delay.h>
++#include <linux/extcon-provider.h>
++#include <linux/firmware.h>
++#include <linux/gpio/consumer.h>
++#include <linux/i2c.h>
++#include <linux/interrupt.h>
++#include <linux/irqreturn.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_irq.h>
++#include <linux/power_supply.h>
++#include <linux/regulator/consumer.h>
++#include <linux/usb/pd.h>
++#include <linux/usb/role.h>
++#include <linux/usb/typec.h>
++
++#define DISABLE_OCM 0
++
++/* firmware regs */
++
++#define ANX7688_REG_VBUS_OFF_DELAY_TIME 0x22
++#define ANX7688_REG_FEATURE_CTRL        0x27
++#define ANX7688_REG_EEPROM_LOAD_STATUS1 0x11
++#define ANX7688_REG_EEPROM_LOAD_STATUS0 0x12
++#define ANX7688_REG_FW_VERSION1         0x15
++#define ANX7688_REG_FW_VERSION0         0x16
++
++#define ANX7688_EEPROM_FW_LOADED	0x01
++
++#define ANX7688_REG_STATUS_INT_MASK     0x17
++#define ANX7688_REG_STATUS_INT          0x28
++#define ANX7688_IRQS_RECEIVED_MSG       BIT(0)
++#define ANX7688_IRQS_RECEIVED_ACK       BIT(1)
++#define ANX7688_IRQS_VCONN_CHANGE       BIT(2)
++#define ANX7688_IRQS_VBUS_CHANGE        BIT(3)
++#define ANX7688_IRQS_CC_STATUS_CHANGE   BIT(4)
++#define ANX7688_IRQS_DATA_ROLE_CHANGE   BIT(5)
++
++#define ANX7688_REG_STATUS              0x29
++#define ANX7688_VCONN_STATUS            BIT(2) /* 0 = off  1 = on */
++#define ANX7688_VBUS_STATUS             BIT(3) /* 0 = off  1 = on */
++#define ANX7688_DATA_ROLE_STATUS        BIT(5) /* 0 = device 1 = host */
++
++#define ANX7688_REG_CC_STATUS           0x2a
++#define ANX7688_REG_TRY_UFP_TIMER       0x23
++#define ANX7688_REG_TIME_CTRL           0x24
++
++#define ANX7688_REG_MAX_VOLTAGE         0x1b
++#define ANX7688_REG_MAX_POWER           0x1c
++#define ANX7688_REG_MIN_POWER           0x1d
++#define ANX7688_REG_MAX_VOLTAGE_STATUS  0x1e
++#define ANX7688_REG_MAX_POWER_STATUS    0x1f
++
++#define ANX7688_SOFT_INT_MASK           0x7f
++
++/* tcpc regs */
++
++#define ANX7688_TCPC_REG_VENDOR_ID0     0x00
++#define ANX7688_TCPC_REG_VENDOR_ID1     0x01
++#define ANX7688_TCPC_REG_ALERT0         0x10
++#define ANX7688_TCPC_REG_ALERT1         0x11
++#define ANX7688_TCPC_REG_ALERT_MASK0    0x12
++#define ANX7688_TCPC_REG_ALERT_MASK1    0x13
++#define ANX7688_TCPC_REG_INTERFACE_SEND 0x30
++#define ANX7688_TCPC_REG_INTERFACE_RECV 0x51
++
++/* hw regs */
++
++#define ANX7688_REG_IRQ_EXT_SOURCE0     0x3e
++#define ANX7688_REG_IRQ_EXT_SOURCE1     0x4e
++#define ANX7688_REG_IRQ_EXT_SOURCE2     0x4f
++#define ANX7688_REG_IRQ_EXT_MASK0       0x3b
++#define ANX7688_REG_IRQ_EXT_MASK1       0x3c
++#define ANX7688_REG_IRQ_EXT_MASK2       0x3d
++#define ANX7688_REG_IRQ_SOURCE0         0x54
++#define ANX7688_REG_IRQ_SOURCE1         0x55
++#define ANX7688_REG_IRQ_SOURCE2         0x56
++#define ANX7688_REG_IRQ_MASK0           0x57
++#define ANX7688_REG_IRQ_MASK1           0x58
++#define ANX7688_REG_IRQ_MASK2           0x59
++
++#define ANX7688_IRQ2_SOFT_INT           BIT(2)
++
++#define ANX7688_REG_USBC_RESET_CTRL		0x05
++#define ANX7688_USBC_RESET_CTRL_OCM_RESET	BIT(4)
++
++//#define ANX7688_IRQ2_USB_PLUGIN         BIT(4)
++//#define ANX7688_REG_IRQ_STATUS          0x53
++
++/* ocm messages */
++
++#define ANX7688_OCM_MSG_PWR_SRC_CAP     0x00
++#define ANX7688_OCM_MSG_PWR_SNK_CAP     0x01
++#define ANX7688_OCM_MSG_DP_SNK_IDENTITY 0x02
++#define ANX7688_OCM_MSG_SVID            0x03
++#define ANX7688_OCM_MSG_GET_DP_SNK_CAP  0x04
++#define ANX7688_OCM_MSG_ACCEPT          0x05
++#define ANX7688_OCM_MSG_REJECT          0x06
++#define ANX7688_OCM_MSG_PSWAP_REQ       0x10
++#define ANX7688_OCM_MSG_DSWAP_REQ       0x11
++#define ANX7688_OCM_MSG_GOTO_MIN_REQ    0x12
++#define ANX7688_OCM_MSG_VCONN_SWAP_REQ  0x13
++#define ANX7688_OCM_MSG_VDM             0x14
++#define ANX7688_OCM_MSG_DP_SNK_CFG      0x15
++#define ANX7688_OCM_MSG_PWR_OBJ_REQ     0x16
++#define ANX7688_OCM_MSG_PD_STATUS_REQ   0x17
++#define ANX7688_OCM_MSG_DP_ALT_ENTER    0x19
++#define ANX7688_OCM_MSG_DP_ALT_EXIT     0x1a
++#define ANX7688_OCM_MSG_GET_SNK_CAP     0x1b
++#define ANX7688_OCM_MSG_RESPONSE_TO_REQ 0xf0
++#define ANX7688_OCM_MSG_SOFT_RST        0xf1
++#define ANX7688_OCM_MSG_HARD_RST        0xf2
++#define ANX7688_OCM_MSG_RESTART         0xf3
++
++static const char * const anx7688_supply_names[] = {
++	"avdd33",
++	"avdd18",
++	"dvdd18",
++	"avdd10",
++	"dvdd10",
++	"i2c",
++	"hdmi_vt",
++
++	"vconn", // power for VCONN1/VCONN2 switches
++	"vbus", // vbus power
++};
++
++#define ANX7688_NUM_SUPPLIES ARRAY_SIZE(anx7688_supply_names)
++#define ANX7688_NUM_ALWAYS_ON_SUPPLIES (ANX7688_NUM_SUPPLIES - 1)
++
++#define ANX7688_I2C_INDEX (ANX7688_NUM_SUPPLIES - 4)
++#define ANX7688_VCONN_INDEX (ANX7688_NUM_SUPPLIES - 2)
++#define ANX7688_VBUS_INDEX (ANX7688_NUM_SUPPLIES - 1)
++
++enum {
++	ANX7688_F_POWERED,
++	ANX7688_F_CONNECTED,
++	ANX7688_F_FW_FAILED,
++	ANX7688_F_PWRSUPPLY_CHANGE,
++	ANX7688_F_CURRENT_UPDATE,
++};
++
++struct anx7688 {
++	struct device *dev;
++	struct i2c_client *client;
++	struct i2c_client *client_tcpc;
++	struct regulator_bulk_data supplies[ANX7688_NUM_SUPPLIES];
++	struct power_supply *vbus_in_supply;
++	struct notifier_block vbus_in_nb;
++	int input_current_limit; // mA
++	struct gpio_desc *gpio_enable;
++	struct gpio_desc *gpio_reset;
++	struct gpio_desc *gpio_cabledet;
++
++	uint32_t src_caps[8];
++	unsigned n_src_caps;
++
++	uint32_t snk_caps[8];
++	unsigned n_snk_caps;
++
++	unsigned long flags[1];
++
++	struct delayed_work work;
++	struct timer_list work_timer;
++
++	struct mutex lock;
++	bool vbus_on, vconn_on;
++	bool pd_capable;
++	int pd_current_limit; // mA
++	ktime_t current_update_deadline;
++
++	struct typec_port *port;
++	struct typec_partner *partner;
++	struct usb_pd_identity partner_identity;
++	struct usb_role_switch *role_sw;
++	int pwr_role, data_role;
++
++	struct dentry *debug_root;
++
++	/* for debug */
++	int last_status;
++	int last_cc_status;
++	int last_dp_state;
++	int last_bc_result;
++
++	/* for HDMI HPD */
++	struct extcon_dev *extcon;
++	int last_extcon_state;
++};
++
++static const unsigned int anx7688_extcon_cable[] = {
++	EXTCON_DISP_HDMI,
++	EXTCON_NONE,
++};
++
++static int anx7688_reg_read(struct anx7688 *anx7688, u8 reg_addr)
++{
++	int ret;
++
++	ret = i2c_smbus_read_byte_data(anx7688->client, reg_addr);
++	if (ret < 0)
++		dev_err(anx7688->dev, "i2c read failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static int anx7688_reg_write(struct anx7688 *anx7688, u8 reg_addr, u8 value)
++{
++	int ret;
++
++	ret = i2c_smbus_write_byte_data(anx7688->client, reg_addr, value);
++	if (ret < 0)
++		dev_err(anx7688->dev, "i2c write failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static int anx7688_reg_update_bits(struct anx7688 *anx7688, u8 reg_addr,
++				   u8 mask, u8 value)
++{
++	int ret;
++
++	ret = anx7688_reg_read(anx7688, reg_addr);
++	if (ret < 0)
++		return ret;
++
++	ret &= ~mask;
++	ret |= value;
++
++	return anx7688_reg_write(anx7688, reg_addr, ret);
++}
++
++static int anx7688_tcpc_reg_read(struct anx7688 *anx7688, u8 reg_addr)
++{
++	int ret;
++
++	ret = i2c_smbus_read_byte_data(anx7688->client_tcpc, reg_addr);
++	if (ret < 0)
++		dev_err(anx7688->dev, "tcpc i2c read failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static int anx7688_tcpc_reg_write(struct anx7688 *anx7688, u8 reg_addr, u8 value)
++{
++	int ret;
++
++	ret = i2c_smbus_write_byte_data(anx7688->client_tcpc, reg_addr, value);
++	if (ret < 0)
++		dev_err(anx7688->dev, "tcpc i2c write failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static void anx7688_power_enable(struct anx7688 *anx7688)
++{
++	gpiod_set_value(anx7688->gpio_reset, 1);
++	gpiod_set_value(anx7688->gpio_enable, 1);
++
++	/* wait for power to stabilize and release reset */
++	msleep(10);
++	gpiod_set_value(anx7688->gpio_reset, 0);
++	udelay(2);
++
++	dev_dbg(anx7688->dev, "power enabled\n");
++
++	set_bit(ANX7688_F_POWERED, anx7688->flags);
++}
++
++static void anx7688_power_disable(struct anx7688 *anx7688)
++{
++	gpiod_set_value(anx7688->gpio_reset, 1);
++	msleep(5);
++	gpiod_set_value(anx7688->gpio_enable, 0);
++
++	dev_dbg(anx7688->dev, "power disabled\n");
++
++	clear_bit(ANX7688_F_POWERED, anx7688->flags);
++}
++
++static int anx7688_send_ocm_message(struct anx7688 *anx7688, int cmd,
++				    const u8 *data, int data_len)
++{
++	int ret = 0, i;
++	u8 pkt[32];
++
++	if (data_len > sizeof(pkt) - 3) {
++		dev_dbg(anx7688->dev,
++			"invalid ocm message length cmd=0x%02x len=%d\n",
++			cmd, data_len);
++		return -EINVAL;
++	}
++
++	// prepare pd packet
++	pkt[0] = data_len + 1;
++	pkt[1] = cmd;
++	if (data_len > 0)
++		memcpy(pkt + 2, data, data_len);
++	pkt[2 + data_len] = 0;
++	for (i = 0; i < data_len + 2; i++)
++		pkt[data_len + 2] -= pkt[i];
++
++	dev_dbg(anx7688->dev, "send pd packet cmd=0x%02x %*ph\n",
++		cmd, data_len + 3, pkt);
++
++	ret = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_INTERFACE_SEND);
++	if (ret) {
++		dev_err(anx7688->dev,
++			"failed to send pd packet (tx buffer full)\n");
++		return -EBUSY;
++	}
++
++	ret = i2c_smbus_write_i2c_block_data(anx7688->client_tcpc,
++					     ANX7688_TCPC_REG_INTERFACE_SEND,
++					     data_len + 3, pkt);
++	if (ret < 0)
++		dev_err(anx7688->dev,
++			"failed to send pd packet (err=%d)\n", ret);
++
++	// wait until the message is processed (30ms max)
++	for (i = 0; i < 300; i++) {
++		ret = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_INTERFACE_SEND);
++		if (ret <= 0)
++			return ret;
++
++		udelay(100);
++	}
++
++	dev_err(anx7688->dev, "timeout waiting for the message queue flush\n");
++	return -ETIMEDOUT;
++}
++
++static int anx7688_connect(struct anx7688 *anx7688)
++{
++#if DISABLE_OCM
++	int ret;
++
++	dev_dbg(anx7688->dev, "cable inserted\n");
++
++	msleep(10);
++	anx7688_power_enable(anx7688);
++
++	/* reset the OCM right away */
++	ret = anx7688_reg_update_bits(anx7688, ANX7688_REG_USBC_RESET_CTRL,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET);
++	if (ret)
++		goto err_poweroff;
++
++	/* enable interrupts for VBUS, etc. */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, 0xff);
++	if (ret)
++		goto err_poweroff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_MASK2, ~(BIT(6) | BIT(5) | BIT(4)));
++	if (ret)
++		goto err_poweroff;
++
++	set_bit(ANX7688_F_CONNECTED, anx7688->flags);
++	return 0;
++
++err_poweroff:
++	anx7688_power_disable(anx7688);
++	return ret;
++#else
++	struct typec_partner_desc desc = {};
++	int ret, i;
++	u8 fw[2];
++	const u8 dp_snk_identity[16] = {
++		0x00, 0x00, 0x00, 0xec,	/* id header */
++		0x00, 0x00, 0x00, 0x00,	/* cert stat */
++		0x00, 0x00, 0x00, 0x00,	/* product type */
++		0x39, 0x00, 0x00, 0x51	/* alt mode adapter */
++	};
++	const u8 svid[4] = {
++		0x00, 0x00, 0x01, 0xff,
++	};
++	u32 caps[8];
++
++	dev_dbg(anx7688->dev, "cable inserted\n");
++
++	anx7688->last_status = -1;
++	anx7688->last_cc_status = -1;
++	anx7688->last_dp_state = -1;
++
++	msleep(10);
++	anx7688_power_enable(anx7688);
++
++	ret = regulator_enable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++	if (ret) {
++		dev_err(anx7688->dev, "failed to enable vconn\n");
++		goto err_poweroff;
++	}
++	anx7688->vconn_on = true;
++
++	/* wait till the firmware is loaded (typically ~30ms) */
++	for (i = 0; i < 100; i++) {
++		ret = anx7688_reg_read(anx7688, ANX7688_REG_EEPROM_LOAD_STATUS0);
++
++		if (ret >= 0 && (ret & ANX7688_EEPROM_FW_LOADED) == ANX7688_EEPROM_FW_LOADED) {
++			dev_dbg(anx7688->dev, "eeprom0 = 0x%02x\n", ret);
++			dev_info(anx7688->dev, "fw loaded after %d ms\n", i * 10);
++			goto fw_loaded;
++		}
++
++		msleep(5);
++	}
++
++	set_bit(ANX7688_F_FW_FAILED, anx7688->flags);
++	dev_err(anx7688->dev, "boot firmware load failed (you may need to flash FW to anx7688 first)\n");
++	ret = -ETIMEDOUT;
++	goto err_vconoff;
++
++fw_loaded:
++	ret = i2c_smbus_read_i2c_block_data(anx7688->client,
++					    ANX7688_REG_FW_VERSION1, 2, fw);
++	if (ret < 0) {
++		dev_err(anx7688->dev, "failed to read firmware version\n");
++		goto err_vconoff;
++	}
++
++	dev_info(anx7688->dev, "OCM firmware loaded (version 0x%04x)\n",
++		 fw[1] | fw[0] << 8);
++
++	/* Unmask interrupts */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_STATUS_INT, 0);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_STATUS_INT_MASK, ~ANX7688_SOFT_INT_MASK);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, 0xff);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_MASK2, (u8)~ANX7688_IRQ2_SOFT_INT);
++	if (ret)
++		goto err_vconoff;
++
++	/* time to turn off vbus after cc disconnect (unit is 4 ms) */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_VBUS_OFF_DELAY_TIME, 100 / 4);
++	if (ret)
++		goto err_vconoff;
++
++	//anx7688_reg_write(anx7688, ANX7688_REG_TIME_CTRL, 0x00);
++
++	/* 300ms (unit is 2 ms) */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_TRY_UFP_TIMER, 300 / 2);
++	if (ret)
++		goto err_vconoff;
++
++	/* maximum voltage in 100 mV units */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_MAX_VOLTAGE, 50); /* 5 V */
++	if (ret)
++		goto err_vconoff;
++
++	/* min/max power in 500 mW units */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_MAX_POWER, 15 * 2); /* 15 W */
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_MIN_POWER, 1);  /* 0.5 W */
++	if (ret)
++		goto err_vconoff;
++
++	/* auto_pd, try.src, try.sink, goto safe 5V */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_FEATURE_CTRL, 0x1e & ~BIT(2)); // disable try_src
++	if (ret)
++		goto err_vconoff;
++
++	for (i = 0; i < anx7688->n_src_caps; i++)
++		caps[i] = cpu_to_le32(anx7688->src_caps[i]);
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PWR_SRC_CAP,
++				       (u8*)&caps, 4 * anx7688->n_src_caps);
++	if (ret)
++		goto err_vconoff;
++
++	for (i = 0; i < anx7688->n_snk_caps; i++)
++		caps[i] = cpu_to_le32(anx7688->snk_caps[i]);
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PWR_SNK_CAP,
++				       (u8*)&caps, 4 * anx7688->n_snk_caps);
++	if (ret)
++		goto err_vconoff;
++
++	/* Send DP SNK identity */
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_DP_SNK_IDENTITY,
++				       dp_snk_identity, sizeof dp_snk_identity);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_SVID,
++				       svid, sizeof svid);
++	if (ret)
++		goto err_vconoff;
++
++	dev_dbg(anx7688->dev, "OCM configuration completed\n");
++
++	desc.accessory = TYPEC_ACCESSORY_NONE;
++
++	typec_unregister_partner(anx7688->partner);
++
++	anx7688->partner = typec_register_partner(anx7688->port, &desc);
++	if (IS_ERR(anx7688->partner)) {
++		ret = PTR_ERR(anx7688->partner);
++		goto err_vconoff;
++	}
++
++	// after this deadline passes we'll check if device is pd_capable and
++	// set up the current limit accordingly
++	anx7688->current_update_deadline = ktime_add_ms(ktime_get(), 3000);
++
++	set_bit(ANX7688_F_CONNECTED, anx7688->flags);
++	return 0;
++
++err_vconoff:
++	regulator_disable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++	anx7688->vconn_on = false;
++err_poweroff:
++	anx7688_power_disable(anx7688);
++	dev_err(anx7688->dev, "OCM configuration failed\n");
++	return ret;
++#endif
++}
++
++static void anx7688_set_hdmi_hpd(struct anx7688 *anx7688, int state)
++{
++	if (!anx7688->extcon)
++		return;
++
++	if (anx7688->last_extcon_state != state) {
++		extcon_set_state_sync(anx7688->extcon, EXTCON_DISP_HDMI, state);
++		anx7688->last_extcon_state = state;
++	}
++}
++
++static void anx7688_disconnect(struct anx7688 *anx7688)
++{
++	union power_supply_propval val = {0,};
++	struct device *dev = anx7688->dev;
++	int ret;
++
++	dev_dbg(dev, "cable removed\n");
++
++	anx7688->current_update_deadline = 0;
++
++	anx7688_set_hdmi_hpd(anx7688, 0);
++
++	if (anx7688->vconn_on) {
++		regulator_disable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++		anx7688->vconn_on = false;
++	}
++
++	if (anx7688->vbus_on) {
++		regulator_disable(anx7688->supplies[ANX7688_VBUS_INDEX].consumer);
++		anx7688->vbus_on = false;
++	}
++
++	anx7688_power_disable(anx7688);
++
++	anx7688->pd_capable = false;
++
++	typec_unregister_partner(anx7688->partner);
++	anx7688->partner = NULL;
++
++	anx7688->pwr_role = TYPEC_SINK;
++	anx7688->data_role = TYPEC_DEVICE;
++	typec_set_pwr_role(anx7688->port, anx7688->pwr_role);
++	typec_set_data_role(anx7688->port, anx7688->data_role);
++	typec_set_pwr_opmode(anx7688->port, TYPEC_PWR_MODE_USB);
++	typec_set_vconn_role(anx7688->port, TYPEC_SINK);
++
++	usb_role_switch_set_role(anx7688->role_sw, USB_ROLE_NONE);
++
++	val.intval = 500 * 1000;
++	dev_dbg(dev, "setting vbus_in current limit to %d mA\n", val.intval);
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++					&val);
++	if (ret)
++		dev_err(dev, "failed to set vbus_in current to %d mA\n",
++			val.intval / 1000);
++
++	val.intval = 0;
++	dev_dbg(dev, "disabling vbus_in power path\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_ONLINE,
++					&val);
++	if (ret)
++		dev_err(dev, "failed to offline vbus_in\n");
++
++	val.intval = 1;
++	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_USB_BC_ENABLED,
++					&val);
++	if (ret)
++		dev_err(dev, "failed to enabled USB BC1.2 detection\n");
++
++	clear_bit(ANX7688_F_CONNECTED, anx7688->flags);
++}
++
++static void anx7688_handle_cable_change(struct anx7688* anx7688)
++{
++	int cabledet;
++	bool connected;
++
++	connected = test_bit(ANX7688_F_CONNECTED, anx7688->flags);
++	cabledet = gpiod_get_value(anx7688->gpio_cabledet);
++
++	if (cabledet && !connected)
++		anx7688_connect(anx7688);
++	else if (!cabledet && connected)
++		anx7688_disconnect(anx7688);
++}
++
++static irqreturn_t anx7688_irq_plug_handler(int irq, void *data)
++{
++	struct anx7688 *anx7688 = data;
++
++	dev_dbg(anx7688->dev, "plug irq (cd=%d)\n",
++		gpiod_get_value(anx7688->gpio_cabledet));
++
++	/*
++	 * After each cabledet change the scheduled work timer is reset
++	 * to fire in ~10ms. So the work is done only after the cabledet
++	 * is stable for ~10ms.
++	 */
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(10));
++
++	return IRQ_HANDLED;
++}
++
++enum {
++	CMD_SUCCESS,
++	CMD_REJECT,
++	CMD_FAIL,
++	CMD_BUSY,
++};
++
++static const char* anx7688_cmd_statuses[] = {
++	"SUCCESS",
++	"REJECT",
++	"FAIL",
++	"BUSY",
++};
++
++static int anx7688_handle_pd_message_response(struct anx7688* anx7688,
++					      u8 to_cmd, u8 resp)
++{
++	const char* status = resp <= CMD_BUSY ? anx7688_cmd_statuses[resp] : "UNKNOWN";
++
++	switch (to_cmd) {
++	case ANX7688_OCM_MSG_PSWAP_REQ:
++		dev_info(anx7688->dev, "received response to PSWAP_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_DSWAP_REQ:
++		dev_info(anx7688->dev, "received response to DSWAP_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_VCONN_SWAP_REQ:
++		dev_info(anx7688->dev, "received response to VCONN_SWAP_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_PWR_OBJ_REQ:
++		dev_info(anx7688->dev, "received response to PWR_OBJ_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_VDM:
++		dev_info(anx7688->dev, "received response to VDM (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_GOTO_MIN_REQ:
++		dev_info(anx7688->dev, "received response to GOTO_MIN_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_GET_SNK_CAP:
++		dev_info(anx7688->dev, "received response to GET_SNK_CAP (%s)\n", status);
++		break;
++
++	default:
++		dev_info(anx7688->dev, "received response to unknown request (%s)\n", status);
++		break;
++	}
++
++	return 0;
++}
++
++static int anx7688_handle_pd_message(struct anx7688* anx7688,
++				     u8 cmd, u8* msg, unsigned len)
++{
++	struct device *dev = anx7688->dev;
++	union power_supply_propval psy_val = {0,};
++	uint32_t* pdos = (uint32_t*)msg;
++	int ret, i, rdo_max_v, rdo_max_p;
++	uint32_t pdo, rdo;
++
++	switch (cmd) {
++	case ANX7688_OCM_MSG_PWR_SRC_CAP:
++		dev_info(anx7688->dev, "received SRC_CAP\n");
++
++		if (len % 4 != 0) {
++			dev_warn(anx7688->dev, "received invalid sized PDO array\n");
++			break;
++		}
++
++		/* the partner is PD capable */
++		anx7688->pd_capable = true;
++
++		for (i = 0; i < len / 4; i++) {
++			pdo = le32_to_cpu(pdos[i]);
++
++			if (pdo_type(pdo) == PDO_TYPE_FIXED) {
++				unsigned voltage = pdo_fixed_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SRC_CAP PDO_FIXED (%umV %umA)\n", voltage, max_curr);
++			} else if (pdo_type(pdo) == PDO_TYPE_BATT) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_pow = pdo_max_power(pdo);
++
++				dev_info(anx7688->dev, "SRC_CAP PDO_BATT (%umV-%umV %umW)\n", min_volt, max_volt, max_pow);
++			} else if (pdo_type(pdo) == PDO_TYPE_VAR) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SRC_CAP PDO_VAR (%umV-%umV %umA)\n", min_volt, max_volt, max_curr);
++			} else {
++				dev_info(anx7688->dev, "SRC_CAP PDO_APDO (0x%08X)\n", pdo);
++			}
++		}
++
++		/* when auto_pd mode is enabled, the FW has already set
++		 * RDO_MAX_VOLTAGE and RDO_MAX_POWER for the RDO it sent to the
++		 * partner based on the received SOURCE_CAPs. This does not
++		 * mean, the request was acked, but we can't do better here than
++		 * calculate the current_limit to set later and hope for the best.
++		 */
++		rdo_max_v = anx7688_reg_read(anx7688, ANX7688_REG_MAX_VOLTAGE_STATUS);
++		if (rdo_max_v < 0)
++			return rdo_max_v;
++		if (rdo_max_v == 0)
++			return -EINVAL;
++
++		rdo_max_p = anx7688_reg_read(anx7688, ANX7688_REG_MAX_POWER_STATUS);
++		if (rdo_max_p < 0)
++			return rdo_max_p;
++
++		anx7688->pd_current_limit = rdo_max_p * 5000 / rdo_max_v;
++
++		dev_dbg(anx7688->dev, "RDO max voltage = %dmV, max power = %dmW, PD current limit = %dmA\n",
++			rdo_max_v * 100, rdo_max_p * 500, anx7688->pd_current_limit);
++
++		// update current limit sooner, now that we have PD negotiation result
++		anx7688->current_update_deadline = ktime_add_ms(ktime_get(), 500);
++
++		//TODO: we should go through PDOs and decide which one
++		//to request, build a RDO with a proper index of the
++		//selected PDO and send it via PWR_OBJ_REQ message to FW
++		//but we're using auto_pd, so FW does this for us
++		//
++		//rdo = cpu_to_le32(RDO_FIXED(0, 1500, 1500, RDO_USB_COMM));
++		//ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PWR_OBJ_REQ, &rdo, 4);
++
++		break;
++
++	case ANX7688_OCM_MSG_PWR_SNK_CAP:
++		dev_info(anx7688->dev, "received SNK_CAP\n");
++
++		if (len % 4 != 0) {
++			dev_warn(anx7688->dev, "received invalid sized PDO array\n");
++			break;
++		}
++
++		for (i = 0; i < len / 4; i++) {
++			pdo = le32_to_cpu(pdos[i]);
++
++			if (pdo_type(pdo) == PDO_TYPE_FIXED) {
++				unsigned voltage = pdo_fixed_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SNK_CAP PDO_FIXED (%umV %umA)\n", voltage, max_curr);
++			} else if (pdo_type(pdo) == PDO_TYPE_BATT) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_pow = pdo_max_power(pdo);
++
++				dev_info(anx7688->dev, "SNK_CAP PDO_BATT (%umV-%umV %umW)\n", min_volt, max_volt, max_pow);
++			} else if (pdo_type(pdo) == PDO_TYPE_VAR) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SNK_CAP PDO_VAR (%umV-%umV %umA)\n", min_volt, max_volt, max_curr);
++			} else {
++				dev_info(anx7688->dev, "SNK_CAP PDO_APDO (0x%08X)\n", pdo);
++			}
++		}
++
++		break;
++
++	case ANX7688_OCM_MSG_PWR_OBJ_REQ:
++		dev_info(anx7688->dev, "received PWR_OBJ_REQ\n");
++
++		anx7688->pd_capable = true;
++
++		if (len != 4) {
++			dev_warn(anx7688->dev, "received invalid sized RDO\n");
++			break;
++		}
++
++		rdo = le32_to_cpu(pdos[0]);
++
++		if (rdo_index(rdo) >= 1 && rdo_index(rdo) <= anx7688->n_src_caps) {
++			unsigned rdo_op_curr = rdo_op_current(rdo);
++			unsigned rdo_max_curr = rdo_max_current(rdo);
++			unsigned rdo_idx = rdo_index(rdo) - 1;
++			unsigned pdo_volt, pdo_max_curr;
++
++			pdo = anx7688->src_caps[rdo_idx];
++			pdo_volt = pdo_fixed_voltage(pdo);
++			pdo_max_curr = pdo_max_current(pdo);
++
++			dev_info(anx7688->dev, "RDO (idx=%d op=%umA max=%umA)\n",
++				 rdo_idx, rdo_op_curr, rdo_max_curr);
++
++			dev_info(anx7688->dev, "PDO_FIXED (%umV %umA)\n",
++				 pdo_volt, pdo_max_curr);
++
++			//TODO: we should check the req and respond with accept/reject
++			// but we're using auto_pd feature, so the FW will do
++			// this for us
++			if (rdo_op_curr > pdo_max_curr || rdo_max_curr > pdo_max_curr) {
++				//ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_REJECT, 0, 0);
++			} else {
++				//ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_ACCEPT, 0, 0);
++			}
++		} else {
++			dev_info(anx7688->dev, "PWR_OBJ RDO index out of range (RDO = 0x%08X)\n", rdo);
++		}
++
++		break;
++
++	case ANX7688_OCM_MSG_ACCEPT:
++		dev_info(anx7688->dev, "received ACCEPT\n");
++		break;
++
++	case ANX7688_OCM_MSG_REJECT:
++		dev_info(anx7688->dev, "received REJECT\n");
++		break;
++
++	case ANX7688_OCM_MSG_RESPONSE_TO_REQ:
++		if (len < 2) {
++			dev_warn(anx7688->dev, "received short RESPONSE_TO_REQ\n");
++			break;
++		}
++
++		anx7688_handle_pd_message_response(anx7688, msg[0], msg[1]);
++		break;
++
++	case ANX7688_OCM_MSG_SOFT_RST:
++		dev_info(anx7688->dev, "received SOFT_RST\n");
++		break;
++
++	case ANX7688_OCM_MSG_HARD_RST:
++		if (anx7688->pd_capable) {
++			dev_info(anx7688->dev, "received HARD_RST\n");
++
++			// stop drawing power from VBUS
++			psy_val.intval = 0;
++			dev_dbg(dev, "disabling vbus_in power path\n");
++			ret = power_supply_set_property(anx7688->vbus_in_supply,
++							POWER_SUPPLY_PROP_ONLINE,
++							&psy_val);
++			if (ret)
++				dev_err(anx7688->dev, "failed to offline vbus_in\n");
++
++			// wait till the dust settles
++			anx7688->current_update_deadline = ktime_add_ms(ktime_get(), 3000);
++		} else {
++			dev_dbg(anx7688->dev, "received HARD_RST, idiot firmware is bored\n");
++		}
++
++		break;
++
++	case ANX7688_OCM_MSG_RESTART:
++		dev_info(anx7688->dev, "received RESTART\n");
++		break;
++
++	case ANX7688_OCM_MSG_PSWAP_REQ:
++		dev_info(anx7688->dev, "received PSWAP_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_DSWAP_REQ:
++		dev_info(anx7688->dev, "received DSWAP_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_VCONN_SWAP_REQ:
++		dev_info(anx7688->dev, "received VCONN_SWAP_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_ALT_ENTER:
++		dev_info(anx7688->dev, "received DP_ALT_ENTER\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_ALT_EXIT:
++		dev_info(anx7688->dev, "received DP_ALT_EXIT\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_SNK_IDENTITY:
++		dev_info(anx7688->dev, "received DP_SNK_IDENTITY\n");
++		break;
++
++	case ANX7688_OCM_MSG_SVID:
++		dev_info(anx7688->dev, "received SVID\n");
++		break;
++
++	case ANX7688_OCM_MSG_VDM:
++		dev_info(anx7688->dev, "received VDM\n");
++		break;
++
++	case ANX7688_OCM_MSG_GOTO_MIN_REQ:
++		dev_info(anx7688->dev, "received GOTO_MIN_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_PD_STATUS_REQ:
++		dev_info(anx7688->dev, "received PD_STATUS_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_GET_DP_SNK_CAP:
++		dev_info(anx7688->dev, "received GET_DP_SNK_CAP\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_SNK_CFG:
++		dev_info(anx7688->dev, "received DP_SNK_CFG\n");
++		break;
++
++	default:
++		dev_info(anx7688->dev, "received unknown message 0x%02x\n", cmd);
++		break;
++	}
++
++	return 0;
++}
++
++static int anx7688_receive_msg(struct anx7688* anx7688)
++{
++	u8 pkt[32], checksum = 0;
++	int i, ret;
++
++	ret = i2c_smbus_read_i2c_block_data(anx7688->client_tcpc,
++					    ANX7688_TCPC_REG_INTERFACE_RECV,
++					    32, pkt);
++	if (ret < 0) {
++		dev_err(anx7688->dev, "failed to read pd msg\n");
++		return ret;
++	}
++
++	ret = anx7688_tcpc_reg_write(anx7688, ANX7688_TCPC_REG_INTERFACE_RECV, 0);
++	if (ret) {
++		dev_warn(anx7688->dev, "failed to clear recv fifo\n");
++	}
++
++	if (pkt[0] == 0 || pkt[0] > sizeof(pkt) - 2) {
++		dev_err(anx7688->dev, "received invalid pd message: %*ph\n",
++			(int)sizeof(pkt), pkt);
++		return -EINVAL;
++	}
++
++	dev_dbg(anx7688->dev, "recv ocm message cmd=0x%02x %*ph\n",
++		pkt[1], pkt[0] + 2, pkt);
++
++	for (i = 0; i < pkt[0] + 2; i++)
++		checksum += pkt[i];
++
++	if (checksum != 0) {
++		dev_err(anx7688->dev, "bad checksum on received message\n");
++		return -EINVAL;
++	}
++
++	anx7688_handle_pd_message(anx7688, pkt[1], pkt + 2, pkt[0] - 1);
++	return 0;
++}
++
++static const char* anx7688_cc_status_string(unsigned v)
++{
++	switch (v) {
++	case 0: return "SRC.Open";
++	case 1: return "SRC.Rd";
++	case 2: return "SRC.Ra";
++	case 4: return "SNK.Default";
++	case 8: return "SNK.Power1.5";
++	case 12: return "SNK.Power3.0";
++	default: return "UNK";
++	}
++}
++
++static int anx7688_update_status(struct anx7688 *anx7688)
++{
++	struct device *dev = anx7688->dev;
++	bool vbus_on, vconn_on, dr_dfp;
++	int status, cc_status, dp_state, dp_substate, ret;
++
++	status = anx7688_reg_read(anx7688, ANX7688_REG_STATUS);
++	if (status < 0)
++		return status;
++
++	cc_status = anx7688_reg_read(anx7688, ANX7688_REG_CC_STATUS);
++	if (cc_status < 0)
++		return cc_status;
++
++	dp_state = anx7688_tcpc_reg_read(anx7688, 0x87);
++	if (dp_state < 0)
++		return dp_state;
++
++	dp_substate = anx7688_tcpc_reg_read(anx7688, 0x88);
++	if (dp_substate < 0)
++		return dp_substate;
++
++	anx7688_set_hdmi_hpd(anx7688, dp_state >= 3);
++
++	dp_state = (dp_state << 8) | dp_substate;
++
++	if (anx7688->last_status == -1 || anx7688->last_status != status) {
++		anx7688->last_status = status;
++		dev_dbg(dev, "status changed to 0x%02x\n", status);
++	}
++
++	if (anx7688->last_cc_status == -1 || anx7688->last_cc_status != cc_status) {
++		anx7688->last_cc_status = cc_status;
++		dev_dbg(dev, "cc_status changed to CC1 = %s CC2 = %s\n",
++			anx7688_cc_status_string(cc_status & 0xf),
++			anx7688_cc_status_string((cc_status >> 4) & 0xf));
++	}
++
++	if (anx7688->last_dp_state == -1 || anx7688->last_dp_state != dp_state) {
++		anx7688->last_dp_state = dp_state;
++		dev_dbg(dev, "DP state changed to 0x%04x\n", dp_state);
++	}
++
++	vbus_on = !!(status & ANX7688_VBUS_STATUS);
++	vconn_on = !!(status & ANX7688_VCONN_STATUS);
++	dr_dfp = !!(status & ANX7688_DATA_ROLE_STATUS);
++
++	if (anx7688->vbus_on != vbus_on) {
++		dev_dbg(anx7688->dev, "POWER role change to %s\n",
++			vbus_on ? "SOURCE" : "SINK");
++
++		if (vbus_on) {
++			ret = regulator_enable(anx7688->supplies[ANX7688_VBUS_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to enable vbus\n");
++				return ret;
++			}
++		} else {
++			ret = regulator_disable(anx7688->supplies[ANX7688_VBUS_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to disable vbus\n");
++				return ret;
++			}
++		}
++
++		anx7688->pwr_role = vbus_on ? TYPEC_SOURCE : TYPEC_SINK;
++		typec_set_pwr_role(anx7688->port, anx7688->pwr_role);
++		anx7688->vbus_on = vbus_on;
++	}
++
++	if (anx7688->vconn_on != vconn_on) {
++		dev_dbg(anx7688->dev, "VCONN role change to %s\n",
++			vconn_on ? "SOURCE" : "SINK");
++
++		if (vconn_on) {
++			ret = regulator_enable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to enable vconn\n");
++				return ret;
++			}
++		} else {
++			ret = regulator_disable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to disable vconn\n");
++				return ret;
++			}
++		}
++
++		typec_set_vconn_role(anx7688->port, vconn_on ? TYPEC_SOURCE : TYPEC_SINK);
++		anx7688->vconn_on = vconn_on;
++	}
++
++	anx7688->data_role = dr_dfp ? TYPEC_HOST : TYPEC_DEVICE;
++	typec_set_data_role(anx7688->port, anx7688->data_role);
++
++	if (usb_role_switch_get_role(anx7688->role_sw) !=
++	    (dr_dfp ? USB_ROLE_HOST : USB_ROLE_DEVICE)) {
++		dev_dbg(anx7688->dev, "DATA role change requested to %s\n",
++			dr_dfp ? "DFP" : "UFP");
++
++		ret = usb_role_switch_set_role(anx7688->role_sw,
++					       dr_dfp ? USB_ROLE_HOST : USB_ROLE_DEVICE);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++static irqreturn_t anx7688_irq_status_handler(int irq, void *data)
++{
++#if DISABLE_OCM
++	struct anx7688 *anx7688 = data;
++	struct device *dev = anx7688->dev;
++	int ext2_status;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_CONNECTED, anx7688->flags)) {
++		/*
++		 * The chip should be disabled and powered off, nothing
++		 * more to do.
++		 */
++		dev_dbg(dev, "spurious status irq\n");
++		goto out_unlock;
++	}
++
++	//dev_dbg(dev, "status irq\n");
++
++	ext2_status = anx7688_reg_read(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2);
++	dev_dbg(dev, "  ext2 = 0x%02x\n", ext2_status);
++	anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, ext2_status);
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return IRQ_HANDLED;
++#else
++	struct anx7688 *anx7688 = data;
++	struct device *dev = anx7688->dev;
++	int tcpc_status, ext2_status, soft_status;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_CONNECTED, anx7688->flags)) {
++		dev_dbg(dev, "spurious status irq\n");
++		/* anx chip should be disabled and power off, nothing
++		 * more to do */
++		goto out_unlock;
++	}
++
++	//dev_dbg(dev, "status irq\n");
++
++	// clear tcpc interrupt
++	tcpc_status = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_ALERT0);
++	if (tcpc_status > 0) {
++		//dev_dbg(dev, "  tcpc = 0x%02x\n", tcpc_status);
++		anx7688_tcpc_reg_write(anx7688, ANX7688_TCPC_REG_ALERT0, tcpc_status);
++	}
++
++	ext2_status = anx7688_reg_read(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2);
++	if (ext2_status & ANX7688_IRQ2_SOFT_INT) {
++		soft_status = anx7688_reg_read(anx7688, ANX7688_REG_STATUS_INT);
++		anx7688_reg_write(anx7688, ANX7688_REG_STATUS_INT, 0);
++
++		//dev_dbg(dev, "  soft = 0x%02x\n", soft_status);
++
++		if (soft_status > 0) {
++			soft_status &= ANX7688_SOFT_INT_MASK;
++
++			if (soft_status & ANX7688_IRQS_RECEIVED_MSG)
++				anx7688_receive_msg(anx7688);
++
++			if (soft_status & (ANX7688_IRQS_CC_STATUS_CHANGE |
++					   ANX7688_IRQS_VBUS_CHANGE |
++					   ANX7688_IRQS_VCONN_CHANGE |
++					   ANX7688_IRQS_DATA_ROLE_CHANGE)) {
++				anx7688_update_status(anx7688);
++			}
++		}
++
++		anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, ANX7688_IRQ2_SOFT_INT);
++	}
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return IRQ_HANDLED;
++#endif
++}
++
++static int anx7688_dr_set(struct typec_port *port, enum typec_data_role role)
++{
++	struct anx7688 *anx7688 = typec_get_drvdata(port);
++	int ret = 0;
++
++	dev_info(anx7688->dev, "data role set %d\n", role);
++
++	if (anx7688->data_role != role) {
++		mutex_lock(&anx7688->lock);
++		ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_DSWAP_REQ, 0, 0);
++		mutex_unlock(&anx7688->lock);
++	}
++
++	return ret;
++}
++
++static int anx7688_pr_set(struct typec_port *port, enum typec_role role)
++{
++	struct anx7688 *anx7688 = typec_get_drvdata(port);
++	int ret = 0;
++
++	dev_info(anx7688->dev, "power role set %d\n", role);
++
++	if (anx7688->pwr_role != role) {
++		mutex_lock(&anx7688->lock);
++		ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PSWAP_REQ, 0, 0);
++		mutex_unlock(&anx7688->lock);
++	}
++
++	return ret;
++}
++
++/*
++ * Calls to the eerpom functions need to be taken under the anx7688 lock.
++ */
++
++static int anx7688_eeprom_set_address(struct anx7688 *anx7688, u16 addr)
++{
++	int ret;
++
++	ret = anx7688_reg_write(anx7688, 0xe0, (addr >> 8) & 0xff);
++	if (ret < 0)
++		return ret;
++
++	return anx7688_reg_write(anx7688, 0xe1, addr & 0xff);
++}
++
++static int anx7688_eeprom_wait_done(struct anx7688 *anx7688)
++{
++	ktime_t timeout;
++	int ret;
++
++	// wait for read to be done
++	timeout = ktime_add_us(ktime_get(), 50000);
++	while (true) {
++		ret = anx7688_reg_read(anx7688, 0xe2);
++		if (ret < 0)
++			return ret;
++
++		if (ret & BIT(3))
++			return 0;
++
++		if (ktime_after(ktime_get(), timeout)) {
++			dev_err(anx7688->dev, "timeout waiting for eeprom\n");
++			return -ETIMEDOUT;
++		}
++	}
++}
++
++/* wait for internal FSM of EEPROM to be in a state ready for
++ * programming/reading
++ */
++static int anx7688_eeprom_wait_ready(struct anx7688 *anx7688)
++{
++	ktime_t timeout;
++	int ret;
++
++	// wait until eeprom is ready
++	timeout = ktime_add_us(ktime_get(), 1000000);
++	while (true) {
++		ret = anx7688_reg_read(anx7688, 0x7f);
++		if (ret < 0)
++			return ret;
++
++		if ((ret & 0x0f) == 7)
++			return 0;
++
++		if (ktime_after(ktime_get(), timeout)) {
++			dev_err(anx7688->dev, "timeout waiting for eeprom to initialize\n");
++			return -ETIMEDOUT;
++		}
++
++		msleep(5);
++	}
++}
++
++static int anx7688_eeprom_read(struct anx7688 *anx7688, unsigned addr, u8 buf[16])
++{
++	int ret;
++
++	ret = anx7688_eeprom_set_address(anx7688, addr);
++	if (ret)
++		return ret;
++
++	// initiate read
++	ret = anx7688_reg_write(anx7688, 0xe2, 0x06);
++	if (ret < 0)
++		return ret;
++
++	ret = anx7688_eeprom_wait_done(anx7688);
++	if (ret)
++		return ret;
++
++	ret = i2c_smbus_read_i2c_block_data(anx7688->client, 0xd0, 16, buf);
++	if (ret < 0) {
++		dev_err(anx7688->dev,
++			"failed to read eeprom data (err=%d)\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int anx7688_eeprom_write(struct anx7688 *anx7688, unsigned addr,
++				const u8 buf[16])
++{
++	int ret;
++
++	ret = anx7688_eeprom_set_address(anx7688, addr);
++	if (ret)
++		return ret;
++
++	ret = i2c_smbus_write_i2c_block_data(anx7688->client, 0xd0, 16, buf);
++	if (ret < 0) {
++		dev_err(anx7688->dev,
++			"failed to write eeprom data (err=%d)\n", ret);
++		return ret;
++	}
++
++	dev_info(anx7688->dev, "eeprom wr %x %*ph\n", addr, 16, buf);
++
++	// initiate write
++	ret = anx7688_reg_write(anx7688, 0xe2, 0x01);
++	if (ret < 0)
++		return ret;
++
++	ret = anx7688_eeprom_wait_done(anx7688);
++	if (ret)
++		return ret;
++
++	udelay(1500);
++	udelay(1000);
++
++	return 0;
++}
++
++/*
++ * The firmware is flashed as is from address 0x10 up to 0xffff.
++ */
++static int anx7688_flash_firmware(struct anx7688 *anx7688)
++{
++	const char* fw_name = "anx7688-fw.bin";
++	const struct firmware *fw;
++	unsigned addr;
++	u8 buf[16];
++	int ret;
++
++	ret = request_firmware(&fw, fw_name, anx7688->dev);
++	if (ret < 0)
++		return ret;
++
++	if (fw->size > 0x10000 - 16) {
++		dev_err(anx7688->dev, "Firmware is too big %s\n", fw_name);
++		ret = -E2BIG;
++		goto err_release;
++	}
++
++	mutex_lock(&anx7688->lock);
++
++	/*
++	 * Cabledet changes will not be processed, since we're holding the
++	 * lock, so the firmware flashing is safe from interruptions.
++	 */
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	msleep(20);
++
++	anx7688_power_enable(anx7688);
++
++	// reset OCM
++	ret = anx7688_reg_update_bits(anx7688, ANX7688_REG_USBC_RESET_CTRL,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET);
++	if (ret < 0)
++		goto err_unlock;
++
++	ret = anx7688_eeprom_wait_ready(anx7688);
++	if (ret)
++		goto err_unlock;
++
++	msleep(10);
++
++	/*
++	 * Write to some magic registers to unlock flashing the EEPROM.
++	 */
++	ret = anx7688_reg_update_bits(anx7688, 0x3f, BIT(5), BIT(5));
++	if (ret < 0)
++		goto err_unlock;
++
++	ret = anx7688_reg_update_bits(anx7688, 0x44,
++				      BIT(0) | BIT(7),
++				      BIT(0) | BIT(7));
++	if (ret < 0)
++		goto err_unlock;
++
++	ret = anx7688_reg_update_bits(anx7688, 0x66, BIT(3), BIT(3));
++	if (ret < 0)
++		goto err_unlock;
++
++	msleep(50);
++
++	ret = anx7688_eeprom_wait_done(anx7688);
++	if (ret)
++		goto err_unlock;
++
++	for (addr = 0; addr < fw->size; addr += sizeof buf) {
++		memset(buf, 0, sizeof buf);
++		memcpy(buf, fw->data + addr, min_t(unsigned, fw->size - addr, sizeof buf));
++
++		ret = anx7688_eeprom_write(anx7688, addr + 0x10, buf);
++		if (ret < 0)
++			goto err_unlock;
++	}
++
++	clear_bit(ANX7688_F_FW_FAILED, anx7688->flags);
++
++err_unlock:
++	anx7688_power_disable(anx7688);
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(20));
++	mutex_unlock(&anx7688->lock);
++
++err_release:
++	release_firmware(fw);
++	return ret;
++}
++
++static const struct typec_operations anx7688_typec_ops = {
++	.dr_set = anx7688_dr_set,
++	.pr_set = anx7688_pr_set,
++};
++
++static ssize_t flash_eeprom_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	return scnprintf(buf, PAGE_SIZE, "Write 1 to this file to initiate firmware flashing. Consult dmesg for results.\n");
++}
++
++static ssize_t flash_eeprom_store(struct device *dev,
++				  struct device_attribute *attr,
++				  const char *buf, size_t len)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++	unsigned val;
++	int ret;
++
++	ret = kstrtouint(buf, 0, &val);
++	if (ret)
++		return ret;
++
++	if (val == 1) {
++		ret = anx7688_flash_firmware(anx7688);
++		if (ret)
++			return ret;
++	}
++
++	return len;
++}
++static DEVICE_ATTR_RW(flash_eeprom);
++
++static ssize_t reg_update_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t len)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++	unsigned val, addr, devaddr, data;
++	int ret;
++
++	ret = kstrtouint(buf, 16, &val);
++	if (ret)
++		return ret;
++
++	data = val & 0xff;
++	addr = (val >> 8) & 0xff;
++	devaddr = (val >> 16) & 0xff;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_POWERED, anx7688->flags)) {
++		ret = -ENODEV;
++		goto out_unlock;
++	}
++
++	if (devaddr == 0x50)
++		ret = anx7688_reg_write(anx7688, addr, val);
++	else if (devaddr == 0x58)
++		ret = anx7688_tcpc_reg_write(anx7688, addr, val);
++	else
++		ret = -EINVAL;
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return ret ? ret : len;
++}
++static DEVICE_ATTR_WO(reg_update);
++
++static ssize_t hwreset_store(struct device *dev,
++			     struct device_attribute *attr,
++			     const char *buf, size_t len)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++
++	mutex_lock(&anx7688->lock);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(20));
++	mutex_unlock(&anx7688->lock);
++
++	return len;
++}
++static DEVICE_ATTR_WO(hwreset);
++
++static struct attribute *anx7688_attrs[] = {
++	&dev_attr_flash_eeprom.attr,
++	&dev_attr_reg_update.attr,
++	&dev_attr_hwreset.attr,
++	NULL,
++};
++
++ATTRIBUTE_GROUPS(anx7688);
++
++/*
++ * This function has to work when the ANX7688 is active, and when
++ * it is powered down. It power cycles the chip and asserts the OCM
++ * reset, to prevent OCM FW interfering with EEPROM reading.
++ *
++ * After reading EEPROM, the reconnection is scheduled.
++ */
++static int anx7688_firmware_show(struct seq_file *s, void *data)
++{
++	struct anx7688 *anx7688 = s->private;
++	unsigned addr;
++	u8 buf[16];
++	int ret;
++
++	mutex_lock(&anx7688->lock);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	msleep(20);
++
++	anx7688_power_enable(anx7688);
++
++	ret = anx7688_reg_update_bits(anx7688, ANX7688_REG_USBC_RESET_CTRL,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET);
++	if (ret < 0)
++		goto out_powerdown;
++
++	ret = anx7688_eeprom_wait_ready(anx7688);
++	if (ret)
++		goto out_powerdown;
++
++	msleep(10);
++
++	for (addr = 0x10; addr < 0x10000; addr += 16) {
++		// set address
++		ret = anx7688_eeprom_read(anx7688, addr, buf);
++		if (ret < 0)
++			goto out_powerdown;
++
++		seq_write(s, buf, sizeof buf);
++	}
++
++out_powerdown:
++	anx7688_power_disable(anx7688);
++	schedule_delayed_work(&anx7688->work, 0);
++	mutex_unlock(&anx7688->lock);
++
++	return ret;
++}
++DEFINE_SHOW_ATTRIBUTE(anx7688_firmware);
++
++static int anx7688_regs_show(struct seq_file *s, void *data)
++{
++	struct anx7688 *anx7688 = s->private;
++	u8 buf[16];
++	unsigned i, addr;
++	int ret = -ENODEV;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_POWERED, anx7688->flags))
++		goto out_unlock;
++
++	for (addr = 0; addr < 256; addr += 16) {
++		ret = i2c_smbus_read_i2c_block_data(anx7688->client, addr,
++						    sizeof buf, buf);
++		if (ret < 0) {
++			dev_err(anx7688->dev,
++				"failed to read registers (err=%d)\n", ret);
++			goto out_unlock;
++		}
++
++		for (i = 0; i < 16; i++)
++			seq_printf(s, "50%02x: %02x\n", addr + i, buf[i]);
++	}
++
++	for (addr = 0; addr < 256; addr += 16) {
++		ret = i2c_smbus_read_i2c_block_data(anx7688->client_tcpc, addr,
++						    sizeof buf, buf);
++		if (ret < 0) {
++			dev_err(anx7688->dev,
++				"failed to read registers (err=%d)\n", ret);
++			goto out_unlock;
++		}
++
++		for (i = 0; i < 16; i++)
++			seq_printf(s, "58%02x: %02x\n", addr + i, buf[i]);
++	}
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return ret;
++}
++DEFINE_SHOW_ATTRIBUTE(anx7688_regs);
++
++static int anx7688_status_show(struct seq_file *s, void *data)
++{
++	struct anx7688 *anx7688 = s->private;
++
++	mutex_lock(&anx7688->lock);
++
++	seq_printf(s, "not much\n");
++
++	mutex_unlock(&anx7688->lock);
++
++	return 0;
++}
++DEFINE_SHOW_ATTRIBUTE(anx7688_status);
++
++/*
++ * This is just a 1s watchdog checking the state if cabledet pin.
++ */
++static void anx7688_cabledet_timer_fn(struct timer_list *t)
++{
++	struct anx7688 *anx7688 = from_timer(anx7688, t, work_timer);
++
++	schedule_delayed_work(&anx7688->work, 0);
++	mod_timer(t, jiffies + msecs_to_jiffies(1000));
++}
++
++static void anx7688_handle_vbus_in_notify(struct anx7688* anx7688)
++{
++	union power_supply_propval psy_val = {0,};
++	struct device *dev = anx7688->dev;
++	int ret;
++
++	/* PD charger doesn't like this for some reason, so it's disabled for now */
++	if (anx7688->input_current_limit && false) {
++		ret = power_supply_get_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++						&psy_val);
++		if (ret) {
++			dev_err(dev, "failed to get vbus_in current\n");
++			return;
++		}
++
++		if (psy_val.intval == anx7688->input_current_limit)
++			goto check_type;
++
++		psy_val.intval = anx7688->input_current_limit * 1000;
++		dev_dbg(dev, "setting vbus_in current limit to %d mA\n",
++			psy_val.intval / 1000);
++		ret = power_supply_set_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++						&psy_val);
++		if (ret)
++			dev_err(dev, "failed to set vbus_in current to %d mA\n",
++				psy_val.intval / 1000);
++	}
++
++check_type:
++	ret = power_supply_get_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_USB_TYPE,
++					&psy_val);
++	if (ret) {
++		dev_err(dev, "failed to get USB BC1.2 result\n");
++		return;
++	}
++
++	if (anx7688->last_bc_result == psy_val.intval)
++		return;
++
++	anx7688->last_bc_result = psy_val.intval;
++
++	switch (psy_val.intval) {
++	case POWER_SUPPLY_USB_TYPE_DCP:
++	case POWER_SUPPLY_USB_TYPE_CDP:
++		dev_dbg(dev, "BC 1.2 result: DCP or CDP\n");
++		break;
++	case POWER_SUPPLY_USB_TYPE_SDP:
++	default:
++		dev_dbg(dev, "BC 1.2 result: SDP\n");
++		break;
++	}
++}
++
++static int anx7688_cc_status(unsigned v)
++{
++	switch (v) {
++	case 0: return -1;
++	case 1: return -1;
++	case 2: return -1;
++	case 4: return TYPEC_PWR_MODE_USB;
++	case 8: return TYPEC_PWR_MODE_1_5A;
++	case 12: return TYPEC_PWR_MODE_3_0A;
++	default: return -1;
++	}
++}
++
++static const char* anx7688_get_power_mode_name(enum typec_pwr_opmode mode)
++{
++	switch (mode) {
++	case TYPEC_PWR_MODE_USB: return "USB";
++	case TYPEC_PWR_MODE_1_5A: return "1.5A";
++	case TYPEC_PWR_MODE_3_0A: return "3.0A";
++	case TYPEC_PWR_MODE_PD: return "PD";
++	default: return "Unknown";
++	}
++}
++
++/*
++ * This is called after 500ms after connection when the PD contract should have
++ * been negotiated. We should inspect CC pins or PD status here and decide what
++ * input current limit to set.
++ */
++static void anx7688_handle_current_update(struct anx7688* anx7688)
++{
++	unsigned cc_status = anx7688->last_cc_status;
++	union power_supply_propval val = {0,};
++	struct device *dev = anx7688->dev;
++	int pwr_mode, ret, current_limit = 0;
++
++	if (anx7688->pd_capable) {
++		pwr_mode = TYPEC_PWR_MODE_PD;
++	} else if (cc_status < 0) {
++		pwr_mode = TYPEC_PWR_MODE_USB;
++	} else {
++		pwr_mode = anx7688_cc_status(cc_status & 0xf);
++		if (pwr_mode < 0)
++			pwr_mode = anx7688_cc_status((cc_status >> 4) & 0xf);
++		if (pwr_mode < 0)
++			pwr_mode = TYPEC_PWR_MODE_USB;
++	}
++
++	if (pwr_mode == TYPEC_PWR_MODE_1_5A)
++		current_limit = 1500;
++	else if (pwr_mode == TYPEC_PWR_MODE_3_0A)
++		current_limit = 3000;
++	else if (pwr_mode == TYPEC_PWR_MODE_PD)
++		current_limit = anx7688->pd_current_limit;
++
++	anx7688->input_current_limit = current_limit;
++
++	dev_info(anx7688->dev, "updating power mode to %s, current limit %dmA (0 => BC1.2)\n",
++		 anx7688_get_power_mode_name(pwr_mode), current_limit);
++
++	if (current_limit) {
++		/*
++		 * Disable BC1.2 detection, because we'll be setting
++		 * a current limit determined by USB-PD
++		 */
++		val.intval = 0;
++		dev_dbg(dev, "disabling USB BC 1.2 detection\n");
++		ret = power_supply_set_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_USB_BC_ENABLED,
++						&val);
++		if (ret)
++			dev_err(dev, "failed to disable USB BC1.2 detection\n");
++
++		val.intval = current_limit * 1000;
++		dev_dbg(dev, "setting vbus_in current limit to %d mA\n", current_limit);
++		ret = power_supply_set_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++						&val);
++		if (ret)
++			dev_err(dev, "failed to set vbus_in current to %d mA\n",
++				current_limit);
++	} else {
++		/*
++		 * Use the result of BC1.2 detection performed by PMIC.
++		 */
++		ret = power_supply_get_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_USB_BC_ENABLED,
++						&val);
++		if (ret)
++			dev_err(dev, "failed to get USB BC1.2 detection status\n");
++
++		if (ret != 0 || val.intval == 0) {
++			/*
++			 * If BC is disabled or we can't get its status,
++			 * set conservative 500mA limit. Otherwise leave
++			 * the limit to BC1.2.
++			 */
++			val.intval = 500 * 1000;
++			dev_dbg(dev, "setting vbus_in current limit to %d mA\n",
++				val.intval / 1000);
++			ret = power_supply_set_property(anx7688->vbus_in_supply,
++							POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++							&val);
++			if (ret)
++				dev_err(dev, "failed to set vbus_in current to %d mA\n",
++					val.intval / 1000);
++		}
++	}
++
++	/* Turn on VBUS power path inside PMIC. */
++	val.intval = 1;
++	dev_dbg(dev, "enabling vbus_in power path\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_ONLINE,
++					&val);
++	if (ret)
++		dev_err(anx7688->dev, "failed to enable vbus_in\n");
++
++	typec_set_pwr_opmode(anx7688->port, pwr_mode);
++}
++
++static int anx7688_vbus_in_notify(struct notifier_block *nb,
++				  unsigned long val, void *v)
++{
++	struct anx7688 *anx7688 = container_of(nb, struct anx7688, vbus_in_nb);
++	struct power_supply *psy = v;
++
++	/* atomic context */
++	if (val == PSY_EVENT_PROP_CHANGED && psy == anx7688->vbus_in_supply) {
++		set_bit(ANX7688_F_PWRSUPPLY_CHANGE, anx7688->flags);
++		schedule_delayed_work(&anx7688->work, 0);
++	}
++
++	return NOTIFY_OK;
++}
++
++static void anx7688_work(struct work_struct *work)
++{
++	struct anx7688 *anx7688 = container_of(work, struct anx7688, work.work);
++
++	if (test_bit(ANX7688_F_FW_FAILED, anx7688->flags))
++		return;
++
++	mutex_lock(&anx7688->lock);
++
++	if (test_and_clear_bit(ANX7688_F_PWRSUPPLY_CHANGE, anx7688->flags))
++		anx7688_handle_vbus_in_notify(anx7688);
++
++	anx7688_handle_cable_change(anx7688);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags)) {
++		/*
++		 * We check status periodically outside of interrupt, just to
++		 * be sure we didn't miss any status interrupts
++		 */
++		anx7688_update_status(anx7688);
++
++		if (anx7688->current_update_deadline &&
++		    ktime_after(ktime_get(), anx7688->current_update_deadline)) {
++			anx7688->current_update_deadline = 0;
++			anx7688_handle_current_update(anx7688);
++		}
++	}
++
++	mutex_unlock(&anx7688->lock);
++}
++
++static int anx7688_i2c_probe(struct i2c_client *client)
++{
++	struct anx7688 *anx7688;
++	struct device *dev = &client->dev;
++	struct typec_capability typec_cap = { };
++	union power_supply_propval psy_val;
++	int i, vid_h, vid_l;
++	int irq_cabledet;
++	int ret = 0;
++
++	anx7688 = devm_kzalloc(dev, sizeof(*anx7688), GFP_KERNEL);
++	if (!anx7688)
++		return -ENOMEM;
++
++	i2c_set_clientdata(client, anx7688);
++	anx7688->client = client;
++	anx7688->dev = &client->dev;
++	mutex_init(&anx7688->lock);
++	INIT_DELAYED_WORK(&anx7688->work, anx7688_work);
++	anx7688->last_extcon_state = -1;
++
++	ret = of_property_read_variable_u32_array(dev->of_node, "source-caps",
++						  anx7688->src_caps,
++						  1, ARRAY_SIZE(anx7688->src_caps));
++	if (ret < 0) {
++		dev_err(dev, "failed to get source-caps from DT\n");
++		return ret;
++	}
++	anx7688->n_src_caps = ret;
++
++	ret = of_property_read_variable_u32_array(dev->of_node, "sink-caps",
++						  anx7688->snk_caps,
++						  1, ARRAY_SIZE(anx7688->snk_caps));
++	if (ret < 0) {
++		dev_err(dev, "failed to get sink-caps from DT\n");
++		return ret;
++	}
++	anx7688->n_snk_caps = ret;
++
++	for (i = 0; i < ANX7688_NUM_SUPPLIES; i++)
++		anx7688->supplies[i].supply = anx7688_supply_names[i];
++	ret = devm_regulator_bulk_get(dev, ANX7688_NUM_SUPPLIES,
++				      anx7688->supplies);
++	if (ret)
++		return ret;
++
++	anx7688->vbus_in_supply =
++		devm_power_supply_get_by_phandle(dev, "vbus_in-supply");
++	if (IS_ERR(anx7688->vbus_in_supply)) {
++		dev_err(dev, "Couldn't get the VBUS power supply\n");
++		return PTR_ERR(anx7688->vbus_in_supply);
++	}
++
++	if (!anx7688->vbus_in_supply)
++		return -EPROBE_DEFER;
++
++	anx7688->gpio_enable = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
++	if (IS_ERR(anx7688->gpio_enable)) {
++		dev_err(dev, "Could not get enable gpio\n");
++		return PTR_ERR(anx7688->gpio_enable);
++	}
++
++	anx7688->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
++	if (IS_ERR(anx7688->gpio_reset)) {
++		dev_err(dev, "Could not get reset gpio\n");
++		return PTR_ERR(anx7688->gpio_reset);
++	}
++
++	anx7688->gpio_cabledet = devm_gpiod_get(dev, "cabledet", GPIOD_IN);
++	if (IS_ERR(anx7688->gpio_cabledet)) {
++		dev_err(dev, "Could not get cabledet gpio\n");
++		return PTR_ERR(anx7688->gpio_cabledet);
++	}
++
++	irq_cabledet = gpiod_to_irq(anx7688->gpio_cabledet);
++	if (irq_cabledet < 0) {
++		dev_err(dev, "Could not get cabledet irq\n");
++		return irq_cabledet;
++	}
++
++	ret = devm_device_add_groups(&client->dev, anx7688_groups);
++	if (ret)
++		return ret;
++
++	// Initialize extcon device
++	anx7688->extcon = devm_extcon_dev_allocate(dev, anx7688_extcon_cable);
++	if (IS_ERR(anx7688->extcon))
++		return -ENOMEM;
++
++	ret = devm_extcon_dev_register(dev, anx7688->extcon);
++	if (ret) {
++		dev_err(dev, "failed to register extcon device\n");
++		return ret;
++	}
++
++	// Register the TCPC i2c interface as second interface (0x58)
++	anx7688->client_tcpc = i2c_new_dummy_device(client->adapter, 0x2c);
++	if (IS_ERR(anx7688->client_tcpc)) {
++		dev_err(dev, "Could not register tcpc i2c client\n");
++		return PTR_ERR(anx7688->client_tcpc);
++	}
++	i2c_set_clientdata(anx7688->client_tcpc, anx7688);
++
++	// powerup and probe the ANX chip
++
++	ret = regulator_bulk_enable(ANX7688_NUM_ALWAYS_ON_SUPPLIES,
++				    anx7688->supplies);
++	if (ret) {
++		dev_err(dev, "Could not enable regulators\n");
++		goto err_dummy_dev;
++	}
++
++	msleep(10);
++
++	anx7688_power_enable(anx7688);
++
++	vid_l = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_VENDOR_ID0);
++	vid_h = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_VENDOR_ID1);
++	if (vid_l < 0 || vid_h < 0) {
++		ret = vid_l < 0 ? vid_l : vid_h;
++		anx7688_power_disable(anx7688);
++		goto err_disable_reg;
++	}
++
++	dev_info(dev, "Vendor id 0x%04x\n", vid_l | vid_h << 8);
++
++	anx7688_power_disable(anx7688);
++
++	anx7688->role_sw = usb_role_switch_get(dev);
++	if (IS_ERR(anx7688->role_sw)) {
++		dev_err(dev, "Could not get role switch\n");
++		ret = PTR_ERR(anx7688->role_sw);
++		goto err_disable_reg;
++	}
++
++	// setup a typec port device
++	typec_cap.revision = USB_TYPEC_REV_1_2;
++	typec_cap.pd_revision = 0x200;
++	typec_cap.prefer_role = TYPEC_NO_PREFERRED_ROLE;
++	typec_cap.type = TYPEC_PORT_DRP;
++	typec_cap.data = TYPEC_PORT_DRD;
++	typec_cap.driver_data = anx7688;
++	typec_cap.ops = &anx7688_typec_ops;
++
++	anx7688->port = typec_register_port(dev, &typec_cap);
++	if (IS_ERR(anx7688->port)) {
++		dev_err(dev, "Could not register type-c port\n");
++		ret = PTR_ERR(anx7688->port);
++		goto err_role_sw;
++	}
++
++	anx7688->pwr_role = TYPEC_SINK;
++	anx7688->data_role = TYPEC_DEVICE;
++	typec_set_pwr_role(anx7688->port, anx7688->pwr_role);
++	typec_set_data_role(anx7688->port, anx7688->data_role);
++	typec_set_pwr_opmode(anx7688->port, TYPEC_PWR_MODE_USB);
++	typec_set_vconn_role(anx7688->port, TYPEC_SINK);
++
++	// make sure BC1.2 detection in PMIC is enabled
++	anx7688->last_bc_result = -1;
++	psy_val.intval = 1;
++	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_USB_BC_ENABLED,
++					&psy_val);
++	if (ret) {
++		dev_err(anx7688->dev, "failed to enable BC1.2 detection\n");
++		goto err_cport;
++	}
++
++	ret = devm_request_irq(dev, irq_cabledet, anx7688_irq_plug_handler,
++			       IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
++			       "anx7688-cabledet", anx7688);
++	if (ret < 0) {
++		dev_err(dev, "Could not request cabledet irq (%d)\n", ret);
++		goto err_cport;
++	}
++
++	ret = devm_request_threaded_irq(dev, client->irq,
++					NULL, anx7688_irq_status_handler,
++					IRQF_ONESHOT, NULL, anx7688);
++	if (ret < 0) {
++		dev_err(dev, "Could not request irq (%d)\n", ret);
++		goto err_cport;
++	}
++
++	anx7688->vbus_in_nb.notifier_call = anx7688_vbus_in_notify;
++	anx7688->vbus_in_nb.priority = 0;
++	ret = power_supply_reg_notifier(&anx7688->vbus_in_nb);
++	if (ret)
++		goto err_cport;
++
++	anx7688->debug_root = debugfs_create_dir("anx7688", NULL);
++	debugfs_create_file("firmware", 0444, anx7688->debug_root, anx7688,
++			    &anx7688_firmware_fops);
++	debugfs_create_file("regs", 0444, anx7688->debug_root, anx7688,
++			    &anx7688_regs_fops);
++	debugfs_create_file("status", 0444, anx7688->debug_root, anx7688,
++			    &anx7688_status_fops);
++
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(10));
++
++	timer_setup(&anx7688->work_timer, anx7688_cabledet_timer_fn, 0);
++	mod_timer(&anx7688->work_timer, jiffies + msecs_to_jiffies(1000));
++
++	return 0;
++
++err_cport:
++	typec_unregister_port(anx7688->port);
++err_role_sw:
++	usb_role_switch_put(anx7688->role_sw);
++err_disable_reg:
++	regulator_bulk_disable(ANX7688_NUM_ALWAYS_ON_SUPPLIES, anx7688->supplies);
++err_dummy_dev:
++	i2c_unregister_device(anx7688->client_tcpc);
++	return ret;
++}
++
++static void anx7688_i2c_remove(struct i2c_client *client)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(client);
++
++	mutex_lock(&anx7688->lock);
++
++	power_supply_unreg_notifier(&anx7688->vbus_in_nb);
++
++	del_timer_sync(&anx7688->work_timer);
++
++	cancel_delayed_work_sync(&anx7688->work);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	typec_unregister_partner(anx7688->partner);
++	typec_unregister_port(anx7688->port);
++	usb_role_switch_put(anx7688->role_sw);
++
++	regulator_bulk_disable(ANX7688_NUM_ALWAYS_ON_SUPPLIES, anx7688->supplies);
++	i2c_unregister_device(anx7688->client_tcpc);
++
++	debugfs_remove(anx7688->debug_root);
++
++	mutex_unlock(&anx7688->lock);
++}
++
++static int __maybe_unused anx7688_suspend(struct device *dev)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++
++	del_timer_sync(&anx7688->work_timer);
++	cancel_delayed_work_sync(&anx7688->work);
++
++	regulator_disable(anx7688->supplies[ANX7688_I2C_INDEX].consumer);
++
++	return 0;
++}
++
++static int __maybe_unused anx7688_resume(struct device *dev)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++	int ret;
++
++	ret = regulator_enable(anx7688->supplies[ANX7688_I2C_INDEX].consumer);
++	if (ret)
++		dev_warn(anx7688->dev,
++			 "failed to enable I2C regulator (%d)\n", ret);
++
++	// check status right after resume, since it could have changed during
++	// sleep
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(50));
++	mod_timer(&anx7688->work_timer, jiffies + msecs_to_jiffies(1000));
++
++	return 0;
++}
++
++static const struct dev_pm_ops anx7688_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(anx7688_suspend, anx7688_resume)
++};
++
++static const struct i2c_device_id anx7688_ids[] = {
++	{ "anx7688", 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, anx7688_ids);
++
++static struct of_device_id anx7688_of_match_table[] = {
++	{ .compatible = "analogix,anx7688" },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, anx7688_of_match_table);
++
++static struct i2c_driver anx7688_driver = {
++	.driver = {
++		.name = "anx7688",
++		.of_match_table = anx7688_of_match_table,
++		.pm = &anx7688_pm_ops,
++	},
++	.probe = anx7688_i2c_probe,
++	.remove = anx7688_i2c_remove,
++	.id_table = anx7688_ids,
++};
++
++module_i2c_driver(anx7688_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Martijn Braam <martijn@brixit.nl>");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("Analogix ANX7688 USB-C DisplayPort bridge");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch
new file mode 100644
index 000000000000..bf223289b24d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch
@@ -0,0 +1,28 @@
+From 99ed79dfa9411e18b5b0b947c7b7f281d25964ce Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 5 Jul 2024 23:25:25 +0200
+Subject: usb: typec: anx7688: Port to Linux 6.10
+
+devm_* variant of device_add_groups was dropped.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/anx7688.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c
+index 77c154565340..448a6f48ab36 100644
+--- a/drivers/usb/typec/anx7688.c
++++ b/drivers/usb/typec/anx7688.c
+@@ -1975,7 +1975,7 @@ static int anx7688_i2c_probe(struct i2c_client *client)
+ 		return irq_cabledet;
+ 	}
+ 
+-	ret = devm_device_add_groups(&client->dev, anx7688_groups);
++	ret = device_add_groups(&client->dev, anx7688_groups);
+ 	if (ret)
+ 		return ret;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
new file mode 100644
index 000000000000..7b291171a2e3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
@@ -0,0 +1,110 @@
+From 875b04226e8cc03cbfad1bbeb867b01c27eda082 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 15 Mar 2024 23:05:10 +0100
+Subject: usb: typec: anx7688: Port to Linux 6.9
+
+POWER_SUPPLY_PROP_USB_BC_ENABLED is no longer needed, nor supported
+by axp20x driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/anx7688.c | 51 ++++---------------------------------
+ 1 file changed, 5 insertions(+), 46 deletions(-)
+
+diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c
+index fa1d3496af73..77c154565340 100644
+--- a/drivers/usb/typec/anx7688.c
++++ b/drivers/usb/typec/anx7688.c
+@@ -636,14 +636,6 @@ static void anx7688_disconnect(struct anx7688 *anx7688)
+ 	if (ret)
+ 		dev_err(dev, "failed to offline vbus_in\n");
+ 
+-	val.intval = 1;
+-	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
+-	ret = power_supply_set_property(anx7688->vbus_in_supply,
+-					POWER_SUPPLY_PROP_USB_BC_ENABLED,
+-					&val);
+-	if (ret)
+-		dev_err(dev, "failed to enabled USB BC1.2 detection\n");
+-
+ 	clear_bit(ANX7688_F_CONNECTED, anx7688->flags);
+ }
+ 
+@@ -1822,17 +1814,8 @@ static void anx7688_handle_current_update(struct anx7688* anx7688)
+ 
+ 	if (current_limit) {
+ 		/*
+-		 * Disable BC1.2 detection, because we'll be setting
+-		 * a current limit determined by USB-PD
++		 * Set a current limit determined by USB-PD
+ 		 */
+-		val.intval = 0;
+-		dev_dbg(dev, "disabling USB BC 1.2 detection\n");
+-		ret = power_supply_set_property(anx7688->vbus_in_supply,
+-						POWER_SUPPLY_PROP_USB_BC_ENABLED,
+-						&val);
+-		if (ret)
+-			dev_err(dev, "failed to disable USB BC1.2 detection\n");
+-
+ 		val.intval = current_limit * 1000;
+ 		dev_dbg(dev, "setting vbus_in current limit to %d mA\n", current_limit);
+ 		ret = power_supply_set_property(anx7688->vbus_in_supply,
+@@ -1846,27 +1829,13 @@ static void anx7688_handle_current_update(struct anx7688* anx7688)
+ 		 * Use the result of BC1.2 detection performed by PMIC.
+ 		 */
+ 		ret = power_supply_get_property(anx7688->vbus_in_supply,
+-						POWER_SUPPLY_PROP_USB_BC_ENABLED,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
+ 						&val);
+ 		if (ret)
+-			dev_err(dev, "failed to get USB BC1.2 detection status\n");
+-
+-		if (ret != 0 || val.intval == 0) {
+-			/*
+-			 * If BC is disabled or we can't get its status,
+-			 * set conservative 500mA limit. Otherwise leave
+-			 * the limit to BC1.2.
+-			 */
+-			val.intval = 500 * 1000;
+-			dev_dbg(dev, "setting vbus_in current limit to %d mA\n",
++			dev_err(dev, "failed to get vbus_in current limit\n");
++		if (ret == 0)
++			dev_dbg(dev, "vbus_in current limit is %d mA\n",
+ 				val.intval / 1000);
+-			ret = power_supply_set_property(anx7688->vbus_in_supply,
+-							POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
+-							&val);
+-			if (ret)
+-				dev_err(dev, "failed to set vbus_in current to %d mA\n",
+-					val.intval / 1000);
+-		}
+ 	}
+ 
+ 	/* Turn on VBUS power path inside PMIC. */
+@@ -1932,7 +1901,6 @@ static int anx7688_i2c_probe(struct i2c_client *client)
+ 	struct anx7688 *anx7688;
+ 	struct device *dev = &client->dev;
+ 	struct typec_capability typec_cap = { };
+-	union power_supply_propval psy_val;
+ 	int i, vid_h, vid_l;
+ 	int irq_cabledet;
+ 	int ret = 0;
+@@ -2087,15 +2055,6 @@ static int anx7688_i2c_probe(struct i2c_client *client)
+ 
+ 	// make sure BC1.2 detection in PMIC is enabled
+ 	anx7688->last_bc_result = -1;
+-	psy_val.intval = 1;
+-	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
+-	ret = power_supply_set_property(anx7688->vbus_in_supply,
+-					POWER_SUPPLY_PROP_USB_BC_ENABLED,
+-					&psy_val);
+-	if (ret) {
+-		dev_err(anx7688->dev, "failed to enable BC1.2 detection\n");
+-		goto err_cport;
+-	}
+ 
+ 	ret = devm_request_irq(dev, irq_cabledet, anx7688_irq_plug_handler,
+ 			       IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
new file mode 100644
index 000000000000..ade9c5382d6c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
@@ -0,0 +1,38 @@
+From 39fbc1e5511325f748f8f282af8776c0debd3a53 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 14 Nov 2021 01:14:25 +0100
+Subject: usb: typec: fusb302: Add OF extcon support
+
+It's possible to create a dependency cycle between fusb302 and
+other drivers via extcon device, so we retrieve the device on
+demand after probe and not during probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 35ddbaf50f64..954803316d5e 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -518,6 +518,16 @@ static int tcpm_get_current_limit(struct tcpc_dev *dev)
+ 	int current_limit = 0;
+ 	unsigned long timeout;
+ 
++	/*
++	 * To avoid cycles in OF dependencies, we get extcon when necessary
++	 * outside of probe function.
++	 */
++	if (of_property_read_bool(chip->dev->of_node, "extcon") && !chip->extcon) {
++		chip->extcon = extcon_get_edev_by_phandle(chip->dev, 0);
++		if (IS_ERR(chip->extcon))
++			chip->extcon = NULL;
++	}
++
+ 	if (!chip->extcon)
+ 		return 0;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
new file mode 100644
index 000000000000..d260cb49fcf5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
@@ -0,0 +1,40 @@
+From 57f64310bac90bc305dd7fa582a8f148f7f69b98 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 20 Nov 2021 14:35:10 +0100
+Subject: usb: typec: fusb302: Clear interrupts before we start toggling
+
+This is recommended by the datasheet.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 954803316d5e..ab9b01a490cc 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -586,6 +586,7 @@ static int fusb302_set_toggling(struct fusb302_chip *chip,
+ 				enum toggling_mode mode)
+ {
+ 	int ret = 0;
++	u8 reg;
+ 
+ 	/* first disable toggling */
+ 	ret = fusb302_i2c_clear_bits(chip, FUSB_REG_CONTROL2,
+@@ -644,6 +645,12 @@ static int fusb302_set_toggling(struct fusb302_chip *chip,
+ 	} else {
+ 		/* Datasheet says vconn MUST be off when toggling */
+ 		WARN(chip->vconn_on, "Vconn is on during toggle start");
++
++		/* clear interrupts */
++                ret = fusb302_i2c_read(chip, FUSB_REG_INTERRUPT, &reg);
++		if (ret < 0)
++			return ret;
++
+ 		/* unmask TOGDONE interrupt */
+ 		ret = fusb302_i2c_clear_bits(chip, FUSB_REG_MASKA,
+ 					     FUSB_REG_MASKA_TOGDONE);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
new file mode 100644
index 000000000000..0193d29a7c32
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
@@ -0,0 +1,112 @@
+From d318a3ff035e20d5d1f95db35744cc2f754b98fc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 7 Nov 2021 19:29:06 +0100
+Subject: usb: typec: fusb302: Extend debugging interface with driver state
+ dumps
+
+This is useful for debugging.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 78 ++++++++++++++++++++++++++++++++
+ 1 file changed, 78 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 24962413fe2c..3061eb699f1a 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -207,6 +207,81 @@ static int fusb302_debug_show(struct seq_file *s, void *v)
+ }
+ DEFINE_SHOW_ATTRIBUTE(fusb302_debug);
+ 
++static const char * const typec_cc_status_name[];
++static const char * const cc_polarity_name[];
++static const char * const toggling_mode_name[] = {
++	[TOGGLING_MODE_OFF] = "Off",
++	[TOGGLING_MODE_DRP] = "DRP",
++	[TOGGLING_MODE_SNK] = "SNK",
++	[TOGGLING_MODE_SRC] = "SRC",
++};
++static const char * const src_current_status_name[] = {
++	[SRC_CURRENT_DEFAULT] = "Default",
++	[SRC_CURRENT_MEDIUM] = "Medium",
++	[SRC_CURRENT_HIGH] = "High",
++};
++
++#define FUSB_REG(n) { n, #n },
++struct fusb_reg {
++	u8 addr;
++	const char* name;
++} fusb_regs[] = {
++	FUSB_REG(FUSB_REG_DEVICE_ID)
++	FUSB_REG(FUSB_REG_SWITCHES0)
++	FUSB_REG(FUSB_REG_SWITCHES1)
++	FUSB_REG(FUSB_REG_MEASURE)
++	FUSB_REG(FUSB_REG_CONTROL0)
++	FUSB_REG(FUSB_REG_CONTROL1)
++	FUSB_REG(FUSB_REG_CONTROL2)
++	FUSB_REG(FUSB_REG_CONTROL3)
++	FUSB_REG(FUSB_REG_MASK)
++	FUSB_REG(FUSB_REG_POWER)
++	FUSB_REG(FUSB_REG_RESET)
++	FUSB_REG(FUSB_REG_MASKA)
++	FUSB_REG(FUSB_REG_MASKB)
++	FUSB_REG(FUSB_REG_STATUS0A)
++	FUSB_REG(FUSB_REG_STATUS1A)
++	FUSB_REG(FUSB_REG_INTERRUPTA)
++	FUSB_REG(FUSB_REG_INTERRUPTB)
++	FUSB_REG(FUSB_REG_STATUS0)
++	FUSB_REG(FUSB_REG_STATUS1)
++	FUSB_REG(FUSB_REG_INTERRUPT)
++};
++
++static int fusb302_i2c_read(struct fusb302_chip *chip,
++			    u8 address, u8 *data);
++
++static int fusb302_debug_regs_show(struct seq_file *s, void *v)
++{
++	struct fusb302_chip *chip = (struct fusb302_chip *)s->private;
++	int i, ret;
++
++	seq_printf(s, "chip->intr_togdone = %d\n", chip->intr_togdone);
++	seq_printf(s, "chip->intr_bc_lvl = %d\n", chip->intr_bc_lvl);
++	seq_printf(s, "chip->intr_comp_chng = %d\n", chip->intr_comp_chng);
++	seq_printf(s, "chip->vconn_on = %d\n", chip->vconn_on);
++	seq_printf(s, "chip->vbus_on = %d\n", chip->vbus_on);
++	seq_printf(s, "chip->charge_on = %d\n", chip->charge_on);
++	seq_printf(s, "chip->vbus_present = %d\n", chip->vbus_present);
++	seq_printf(s, "chip->cc_polarity = %s\n", cc_polarity_name[chip->cc_polarity]);
++	seq_printf(s, "chip->cc1 = %s\n", typec_cc_status_name[chip->cc1]);
++	seq_printf(s, "chip->cc2 = %s\n", typec_cc_status_name[chip->cc2]);
++	seq_printf(s, "chip->toggling_mode = %s\n", toggling_mode_name[chip->toggling_mode]);
++	seq_printf(s, "chip->src_current_status = %s\n", src_current_status_name[chip->src_current_status]);
++
++	seq_printf(s, "\nRegisters:\n");
++        for (i = 0; i < ARRAY_SIZE(fusb_regs); i++) {
++		u8 val = 0;
++
++		ret = fusb302_i2c_read(chip, fusb_regs[i].addr, &val);
++		if (ret >= 0)
++			seq_printf(s, "%s = %02hhx\n", fusb_regs[i].name, val);
++	}
++
++	return 0;
++}
++DEFINE_SHOW_ATTRIBUTE(fusb302_debug_regs);
++
+ static void fusb302_debugfs_init(struct fusb302_chip *chip)
+ {
+ 	char name[NAME_MAX];
+@@ -216,6 +291,9 @@ static void fusb302_debugfs_init(struct fusb302_chip *chip)
+ 	chip->dentry = debugfs_create_dir(name, usb_debug_root);
+ 	debugfs_create_file("log", S_IFREG | 0444, chip->dentry, chip,
+ 			    &fusb302_debug_fops);
++
++	debugfs_create_file("regs", S_IFREG | 0444, chip->dentry, chip,
++			    &fusb302_debug_regs_fops);
+ }
+ 
+ static void fusb302_debugfs_exit(struct fusb302_chip *chip)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
new file mode 100644
index 000000000000..be878ca2e39e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
@@ -0,0 +1,49 @@
+From b484c21111e1fe6955a513c18cdcd4f3c6b03bd9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 20 Nov 2021 14:33:58 +0100
+Subject: usb: typec: fusb302: Fix register definitions
+
+MEASURE_VBUS bit is at position 6. MDAC bits are also wrong.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302_reg.h | 16 +++++++---------
+ 1 file changed, 7 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302_reg.h b/drivers/usb/typec/tcpm/fusb302_reg.h
+index edc0e4b0f1e6..f37d226c5027 100644
+--- a/drivers/usb/typec/tcpm/fusb302_reg.h
++++ b/drivers/usb/typec/tcpm/fusb302_reg.h
+@@ -27,14 +27,13 @@
+ #define FUSB_REG_SWITCHES1_TXCC2_EN		BIT(1)
+ #define FUSB_REG_SWITCHES1_TXCC1_EN		BIT(0)
+ #define FUSB_REG_MEASURE			0x04
+-#define FUSB_REG_MEASURE_MDAC5			BIT(7)
+-#define FUSB_REG_MEASURE_MDAC4			BIT(6)
+-#define FUSB_REG_MEASURE_MDAC3			BIT(5)
+-#define FUSB_REG_MEASURE_MDAC2			BIT(4)
+-#define FUSB_REG_MEASURE_MDAC1			BIT(3)
+-#define FUSB_REG_MEASURE_MDAC0			BIT(2)
+-#define FUSB_REG_MEASURE_VBUS			BIT(1)
+-#define FUSB_REG_MEASURE_XXXX5			BIT(0)
++#define FUSB_REG_MEASURE_VBUS			BIT(6)
++#define FUSB_REG_MEASURE_MDAC5			BIT(5)
++#define FUSB_REG_MEASURE_MDAC4			BIT(4)
++#define FUSB_REG_MEASURE_MDAC3			BIT(3)
++#define FUSB_REG_MEASURE_MDAC2			BIT(2)
++#define FUSB_REG_MEASURE_MDAC1			BIT(1)
++#define FUSB_REG_MEASURE_MDAC0			BIT(0)
+ #define FUSB_REG_CONTROL0			0x06
+ #define FUSB_REG_CONTROL0_TX_FLUSH		BIT(6)
+ #define FUSB_REG_CONTROL0_INT_MASK		BIT(5)
+@@ -105,7 +104,6 @@
+ #define FUSB_REG_STATUS0A_RX_SOFT_RESET		BIT(1)
+ #define FUSB_REG_STATUS0A_RX_HARD_RESET		BIT(0)
+ #define FUSB_REG_STATUS1A			0x3D
+-#define FUSB_REG_STATUS1A_TOGSS			BIT(3)
+ #define FUSB_REG_STATUS1A_TOGSS_RUNNING		0x0
+ #define FUSB_REG_STATUS1A_TOGSS_SRC1		0x1
+ #define FUSB_REG_STATUS1A_TOGSS_SRC2		0x2
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
new file mode 100644
index 000000000000..efcdfcf4f5a6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
@@ -0,0 +1,189 @@
+From 8354ed999d8a0676083ee9e164e94c6d2125071b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:55:34 +0100
+Subject: usb: typec: fusb302: More useful of logging status on interrupt
+
+This is just for debugging. It prints more info that's useful to
+see how hardware state changes in time.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 121 ++++++++++++++++++++++++++-----
+ 1 file changed, 104 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 0779e9eabf60..32d894e1b247 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -68,7 +68,7 @@ static const u8 rd_mda_value[] = {
+ };
+ 
+ #define LOG_BUFFER_ENTRIES	1024
+-#define LOG_BUFFER_ENTRY_SIZE	128
++#define LOG_BUFFER_ENTRY_SIZE	256
+ 
+ struct fusb302_chip {
+ 	struct device *dev;
+@@ -1598,6 +1598,84 @@ static irqreturn_t fusb302_irq_intn(int irq, void *dev_id)
+ 	return IRQ_HANDLED;
+ }
+ 
++static void fusb302_print_state(struct fusb302_chip *chip)
++{
++	u8 ctl0, ctl2, measure, status0, status1a, sw0, mask;
++	int ret;
++
++	ret = fusb302_i2c_read(chip, FUSB_REG_CONTROL0, &ctl0);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_CONTROL2, &ctl2);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_MEASURE, &measure);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS1A, &status1a);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_SWITCHES0, &sw0);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_MASK, &mask);
++	if (ret < 0)
++		return;
++
++	//FUSB_REG(FUSB_REG_POWER) // power control
++
++	const char* host_cur = "?";
++	switch ((ctl0 >> 2) & 3) {
++	case 0: host_cur = "none"; break;
++	case 1: host_cur = "80uA"; break;
++	case 2: host_cur = "160uA"; break;
++	case 3: host_cur = "330uA"; break;
++	}
++
++	const char* bc_lvl = "?";
++	switch (status0 & 3) {
++	case 0: bc_lvl = "0-200mV"; break;
++	case 1: bc_lvl = "200-660mV"; break;
++	case 2: bc_lvl = "660-1230mV"; break;
++	case 3: bc_lvl = ">1230mV"; break;
++	}
++
++	// status0
++	unsigned vbusok = !!(status0 & BIT(7));
++	unsigned activity = !!(status0 & BIT(6));
++	unsigned comp = !!(status0 & BIT(5));
++	unsigned wake = !!(status0 & BIT(2));
++
++	// measure
++	unsigned mdac = ((measure & 0x3f) + 1) * 42 * (measure & BIT(6) ? 10 : 1);
++
++	// status1a
++	unsigned togss = (status1a >> 3) & 7;
++	const char* togss_s = "?";
++	switch (togss) {
++	case 0: togss_s = "running"; break;
++	case 1: togss_s = "src1"; break;
++	case 2: togss_s = "src2"; break;
++	case 5: togss_s = "snk1"; break;
++	case 6: togss_s = "snk2"; break;
++	case 7: togss_s = "audio"; break;
++	}
++
++	// ctl2 print as is
++
++#define SW(n) (!!(sw0 & BIT(n)))
++
++	fusb302_log(chip, "state: cc(puen=%u%u vconn=%u%u meas=%u%u pdwn=%u%u) "
++		    "host_cur=%s mdac=%umV comp=%u bc_lvl=%s vbusok=%u act=%u "
++		    "wake=%u togss=%s ctl2=0x%02x mask=0x%02x",
++		    SW(6), SW(7), SW(4), SW(5), SW(2), SW(3), SW(0), SW(1),
++		    host_cur, mdac, comp, bc_lvl, vbusok, activity,
++		    wake, togss_s, ctl2, mask);
++}
++
+ static void fusb302_irq_work(struct work_struct *work)
+ {
+ 	struct fusb302_chip *chip = container_of(work, struct fusb302_chip,
+@@ -1607,6 +1685,7 @@ static void fusb302_irq_work(struct work_struct *work)
+ 	u8 interrupta;
+ 	u8 interruptb;
+ 	u8 status0;
++	u8 mda;
+ 	bool vbus_present;
+ 	bool comp_result;
+ 	bool intr_togdone;
+@@ -1632,9 +1711,10 @@ static void fusb302_irq_work(struct work_struct *work)
+ 	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
+ 	if (ret < 0)
+ 		goto done;
+-	fusb302_log(chip,
+-		    "IRQ: 0x%02x, a: 0x%02x, b: 0x%02x, status0: 0x%02x",
+-		    interrupt, interrupta, interruptb, status0);
++	fusb302_log(chip, "IRQ: 0x%02x, a: 0x%02x, b: 0x%02x",
++		    interrupt, interrupta, interruptb);
++
++	fusb302_print_state(chip);
+ 
+ 	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK) {
+ 		vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
+@@ -1646,32 +1726,39 @@ static void fusb302_irq_work(struct work_struct *work)
+ 		}
+ 	}
+ 
+-	if ((interrupta & FUSB_REG_INTERRUPTA_TOGDONE) && intr_togdone) {
++	if (interrupta & FUSB_REG_INTERRUPTA_TOGDONE) {
+ 		fusb302_log(chip, "IRQ: TOGDONE");
+-		ret = fusb302_handle_togdone(chip);
+-		if (ret < 0) {
+-			fusb302_log(chip,
+-				    "handle togdone error, ret=%d", ret);
+-			goto done;
++		if (intr_togdone) {
++			ret = fusb302_handle_togdone(chip);
++			if (ret < 0) {
++				fusb302_log(chip,
++					    "handle togdone error, ret=%d", ret);
++				goto done;
++			}
+ 		}
+ 	}
+ 
+-	if ((interrupt & FUSB_REG_INTERRUPT_BC_LVL) && intr_bc_lvl) {
++	if (interrupt & FUSB_REG_INTERRUPT_BC_LVL) {
+ 		fusb302_log(chip, "IRQ: BC_LVL, handler pending");
+ 		/*
+ 		 * as BC_LVL interrupt can be affected by PD activity,
+ 		 * apply delay to for the handler to wait for the PD
+ 		 * signaling to finish.
+ 		 */
+-		mod_delayed_work(chip->wq, &chip->bc_lvl_handler,
+-				 msecs_to_jiffies(T_BC_LVL_DEBOUNCE_DELAY_MS));
++		if (intr_bc_lvl)
++			mod_delayed_work(chip->wq, &chip->bc_lvl_handler,
++					 msecs_to_jiffies(T_BC_LVL_DEBOUNCE_DELAY_MS));
+ 	}
+ 
+-	if ((interrupt & FUSB_REG_INTERRUPT_COMP_CHNG) && intr_comp_chng) {
++	if (interrupt & FUSB_REG_INTERRUPT_COMP_CHNG) {
++		ret = fusb302_i2c_read(chip, FUSB_REG_MEASURE, &mda);
++		if (ret < 0)
++			goto done;
++
+ 		comp_result = !!(status0 & FUSB_REG_STATUS0_COMP);
+-		fusb302_log(chip, "IRQ: COMP_CHNG, comp=%s",
+-			    comp_result ? "true" : "false");
+-		if (comp_result) {
++		fusb302_log(chip, "IRQ: COMP_CHNG, cc* %s mdac (%u mV)",
++			    comp_result ? ">" : "<", ((mda & 0x3f) + 1) * 42 * (mda & BIT(6) ? 10 : 1));
++		if (comp_result && intr_comp_chng) {
+ 			/* cc level > Rd_threshold, detach */
+ 			chip->cc1 = TYPEC_CC_OPEN;
+ 			chip->cc2 = TYPEC_CC_OPEN;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
new file mode 100644
index 000000000000..6968177a982e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
@@ -0,0 +1,76 @@
+From 6263d67c2800ecbed49e826d0f00c4e2c7279260 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:53:27 +0100
+Subject: usb: typec: fusb302: Retry reading of CC pins status if activity is
+ detected
+
+This is just for testing, to see if this ever happens. It should
+also help when this happens.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 34 ++++++++++++++++++++++++++++++--
+ 1 file changed, 32 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 3061eb699f1a..0779e9eabf60 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -1317,6 +1317,36 @@ static int fusb302_handle_togdone_snk(struct fusb302_chip *chip,
+ 	return ret;
+ }
+ 
++static int fusb302_get_status0_stable(struct fusb302_chip *chip, u8 *status0)
++{
++	int ret, tries = 0;
++	u8 reg;
++
++try_again:
++	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &reg);
++	if (ret < 0)
++		return ret;
++
++	if (reg & FUSB_REG_STATUS0_ACTIVITY) {
++		fusb302_log(chip, "activity reading CC status");
++		if (++tries == 5) {
++			fusb302_log(chip, "failed to read stable status0 value");
++
++			/*
++			 * The best we can do is to return at least something.
++			 */
++			*status0 = reg;
++			return 0;
++		}
++
++		usleep_range(50, 100);
++		goto try_again;
++	}
++
++	*status0 = reg;
++	return 0;
++}
++
+ /* On error returns < 0, otherwise a typec_cc_status value */
+ static int fusb302_get_src_cc_status(struct fusb302_chip *chip,
+ 				     enum typec_cc_polarity cc_polarity,
+@@ -1344,7 +1374,7 @@ static int fusb302_get_src_cc_status(struct fusb302_chip *chip,
+ 		return ret;
+ 
+ 	usleep_range(50, 100);
+-	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
++	ret = fusb302_get_status0_stable(chip, &status0);
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -1360,7 +1390,7 @@ static int fusb302_get_src_cc_status(struct fusb302_chip *chip,
+ 		return ret;
+ 
+ 	usleep_range(50, 100);
+-	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
++	ret = fusb302_get_status0_stable(chip, &status0);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
new file mode 100644
index 000000000000..d6db0545b5bd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
@@ -0,0 +1,50 @@
+From bbef20f087a4b7d17a659b82d42ef620b828ae96 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 7 Nov 2021 19:28:27 +0100
+Subject: usb: typec: fusb302: Set the current before enabling pullups
+
+This seems more reasonable and should avoid short period of incorrect
+current setting being applied to CC pin.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 00247497bf29..24962413fe2c 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -635,6 +635,14 @@ static int tcpm_set_cc(struct tcpc_dev *dev, enum typec_cc_status cc)
+ 		goto done;
+ 	}
+ 
++	/* adjust current for SRC */
++	ret = fusb302_set_src_current(chip, cc_src_current[cc]);
++	if (ret < 0) {
++		fusb302_log(chip, "cannot set src current %s, ret=%d",
++			    typec_cc_status_name[cc], ret);
++		goto done;
++	}
++
+ 	ret = fusb302_i2c_mask_write(chip, FUSB_REG_SWITCHES0,
+ 				     switches0_mask, switches0_data);
+ 	if (ret < 0) {
+@@ -645,14 +653,6 @@ static int tcpm_set_cc(struct tcpc_dev *dev, enum typec_cc_status cc)
+ 	chip->cc1 = TYPEC_CC_OPEN;
+ 	chip->cc2 = TYPEC_CC_OPEN;
+ 
+-	/* adjust current for SRC */
+-	ret = fusb302_set_src_current(chip, cc_src_current[cc]);
+-	if (ret < 0) {
+-		fusb302_log(chip, "cannot set src current %s, ret=%d",
+-			    typec_cc_status_name[cc], ret);
+-		goto done;
+-	}
+-
+ 	/* enable/disable interrupts, BC_LVL for SNK and COMP_CHNG for SRC */
+ 	switch (cc) {
+ 	case TYPEC_CC_RP_DEF:
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
new file mode 100644
index 000000000000..cddcb9ab5602
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
@@ -0,0 +1,33 @@
+From 97c096164fc5bfb44d99555b3877235dc5eebd33 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 30 Jan 2022 23:46:37 +0100
+Subject: usb: typec: fusb302: Slightly increase wait time for BC1.2 result
+
+This is not strictly necessary, but it should not hurt. Looking at
+kernel log timing, the BC1.2 detection completion time and this
+timeout are quite tight. This adds some headspace just in case.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index ef18a448b740..00247497bf29 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -445,9 +445,9 @@ static int tcpm_get_current_limit(struct tcpc_dev *dev)
+ 
+ 	/*
+ 	 * USB2 Charger detection may still be in progress when we get here,
+-	 * this can take upto 600ms, wait 800ms max.
++	 * this can take upto 600ms, wait 1000ms max.
+ 	 */
+-	timeout = jiffies + msecs_to_jiffies(800);
++	timeout = jiffies + msecs_to_jiffies(1000);
+ 	do {
+ 		if (extcon_get_state(chip->extcon, EXTCON_CHG_USB_SDP) == 1)
+ 			current_limit = 500;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
new file mode 100644
index 000000000000..53be3e9c0266
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
@@ -0,0 +1,43 @@
+From 41ece03f6ed1f62c0759ca4168ed60d0ae7a71ea Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:57:06 +0100
+Subject: usb: typec: fusb302: Update VBUS state even if VBUS interrupt is not
+ triggered
+
+This seems to improve robustness.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 32d894e1b247..35ddbaf50f64 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -1716,14 +1716,16 @@ static void fusb302_irq_work(struct work_struct *work)
+ 
+ 	fusb302_print_state(chip);
+ 
+-	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK) {
+-		vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
++	vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
++	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK)
+ 		fusb302_log(chip, "IRQ: VBUS_OK, vbus=%s",
+ 			    vbus_present ? "On" : "Off");
+-		if (vbus_present != chip->vbus_present) {
+-			chip->vbus_present = vbus_present;
+-			tcpm_vbus_change(chip->tcpm_port);
+-		}
++	if (vbus_present != chip->vbus_present) {
++		chip->vbus_present = vbus_present;
++		if (!(interrupt & FUSB_REG_INTERRUPT_VBUSOK))
++		fusb302_log(chip, "IRQ: VBUS changed without interrupt, vbus=%s",
++			    vbus_present ? "On" : "Off");
++		tcpm_vbus_change(chip->tcpm_port);
+ 	}
+ 
+ 	if (interrupta & FUSB_REG_INTERRUPTA_TOGDONE) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
new file mode 100644
index 000000000000..a9091285fcaf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
@@ -0,0 +1,95 @@
+From a3872930164ccfbfb7efeaec41b60de9552f2042 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 18 Feb 2023 00:38:44 +0100
+Subject: usb: typec: tcpm: Fix PD devices/capabilities registration
+
+Unregister caps before registering them. Store NULL to the struct
+if registration fails, so that next attempt can succeed.
+
+Fixes "sysfs: cannot create duplicate filename
+'/devices/virtual/usb_power_delivery/pd1/source-capabilities'" error.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 37 +++++++++++++++++++++++++++--------
+ 1 file changed, 29 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index b60bc1be25dc..138d8c857827 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -3008,15 +3008,22 @@ static int tcpm_register_source_caps(struct tcpm_port *port)
+ 	struct usb_power_delivery_desc desc = { port->negotiated_rev };
+ 	struct usb_power_delivery_capabilities_desc caps = { };
+ 	struct usb_power_delivery_capabilities *cap;
++	struct usb_power_delivery *partner_pd;
++
++	if (!port->partner_pd) {
++		partner_pd = usb_power_delivery_register(NULL, &desc);
++		if (IS_ERR(partner_pd))
++			return PTR_ERR(partner_pd);
+ 
+-	if (!port->partner_pd)
+-		port->partner_pd = usb_power_delivery_register(NULL, &desc);
+-	if (IS_ERR(port->partner_pd))
+-		return PTR_ERR(port->partner_pd);
++		port->partner_pd = partner_pd;
++	}
+ 
+ 	memcpy(caps.pdo, port->source_caps, sizeof(u32) * port->nr_source_caps);
+ 	caps.role = TYPEC_SOURCE;
+ 
++	usb_power_delivery_unregister_capabilities(port->partner_source_caps);
++	port->partner_source_caps = NULL;
++
+ 	cap = usb_power_delivery_register_capabilities(port->partner_pd, &caps);
+ 	if (IS_ERR(cap))
+ 		return PTR_ERR(cap);
+@@ -3031,15 +3038,22 @@ static int tcpm_register_sink_caps(struct tcpm_port *port)
+ 	struct usb_power_delivery_desc desc = { port->negotiated_rev };
+ 	struct usb_power_delivery_capabilities_desc caps = { };
+ 	struct usb_power_delivery_capabilities *cap;
++	struct usb_power_delivery *partner_pd;
++
++	if (!port->partner_pd) {
++		partner_pd = usb_power_delivery_register(NULL, &desc);
++		if (IS_ERR(partner_pd))
++			return PTR_ERR(partner_pd);
+ 
+-	if (!port->partner_pd)
+-		port->partner_pd = usb_power_delivery_register(NULL, &desc);
+-	if (IS_ERR(port->partner_pd))
+-		return PTR_ERR(port->partner_pd);
++		port->partner_pd = partner_pd;
++	}
+ 
+ 	memcpy(caps.pdo, port->sink_caps, sizeof(u32) * port->nr_sink_caps);
+ 	caps.role = TYPEC_SINK;
+ 
++	usb_power_delivery_unregister_capabilities(port->partner_sink_caps);
++	port->partner_sink_caps = NULL;
++
+ 	cap = usb_power_delivery_register_capabilities(port->partner_pd, &caps);
+ 	if (IS_ERR(cap))
+ 		return PTR_ERR(cap);
+@@ -6991,10 +7005,17 @@ static int tcpm_port_register_pd(struct tcpm_port *port)
+ 		port->pds[i] = usb_power_delivery_register(port->dev, &desc);
+ 		if (IS_ERR(port->pds[i])) {
+ 			ret = PTR_ERR(port->pds[i]);
++			port->pds[i] = NULL;
+ 			goto err_unregister;
+ 		}
+ 		port->pd_list[i]->pd = port->pds[i];
+ 
++		usb_power_delivery_unregister_capabilities(port->pd_list[i]->source_cap);
++		port->pd_list[i]->source_cap = NULL;
++
++		usb_power_delivery_unregister_capabilities(port->pd_list[i]->sink_cap);
++		port->pd_list[i]->sink_cap = NULL;
++
+ 		if (port->pd_list[i]->source_desc.pdo[0]) {
+ 			cap = usb_power_delivery_register_capabilities(port->pds[i],
+ 								&port->pd_list[i]->source_desc);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-tcpm-Improve-logs.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-tcpm-Improve-logs.patch
new file mode 100644
index 000000000000..6330da8bfbf7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-tcpm-Improve-logs.patch
@@ -0,0 +1,64 @@
+From f0b6f55e2d37dd6bcd14eb25ff1ef2c845cb2424 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:58:05 +0100
+Subject: usb: typec: tcpm: Improve logs
+
+This adds clarity to debugging.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 15 +++++++++++----
+ 1 file changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index 138d8c857827..dac00c42f07f 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -957,10 +957,13 @@ static int tcpm_pd_transmit(struct tcpm_port *port,
+ 		break;
+ 	}
+ 
+-	if (msg)
++	if (msg) {
+ 		tcpm_log(port, "PD TX, header: %#x", le16_to_cpu(msg->header));
+-	else
++		for (ret = 0; ret < pd_header_cnt_le(msg->header); ret++)
++			tcpm_log(port, "  tx payload[%d]: %#x", ret, le32_to_cpu(msg->payload[ret]));
++	} else {
+ 		tcpm_log(port, "PD TX, type: %#x", tx_sop_type);
++	}
+ 
+ 	reinit_completion(&port->tx_complete);
+ 	ret = port->tcpc->pd_transmit(port->tcpc, tx_sop_type, msg, negotiated_rev);
+@@ -3679,6 +3682,10 @@ void tcpm_pd_receive(struct tcpm_port *port, const struct pd_message *msg,
+ 		     enum tcpm_transmit_type rx_sop_type)
+ {
+ 	struct pd_rx_event *event;
++	int ret;
++
++	for (ret = 0; ret < pd_header_cnt_le(msg->header); ret++)
++		tcpm_log(port, "  rx payload[%d]: %#x", ret, le32_to_cpu(msg->payload[ret]));
+ 
+ 	event = kzalloc(sizeof(*event), GFP_ATOMIC);
+ 	if (!event)
+@@ -5938,7 +5945,7 @@ static void _tcpm_cc_change(struct tcpm_port *port, enum typec_cc_status cc1,
+ 
+ static void _tcpm_pd_vbus_on(struct tcpm_port *port)
+ {
+-	tcpm_log_force(port, "VBUS on");
++	tcpm_log_force(port, "VBUS event received: on");
+ 	port->vbus_present = true;
+ 	/*
+ 	 * When vbus_present is true i.e. Voltage at VBUS is greater than VSAFE5V implicitly
+@@ -6028,7 +6035,7 @@ static void _tcpm_pd_vbus_on(struct tcpm_port *port)
+ 
+ static void _tcpm_pd_vbus_off(struct tcpm_port *port)
+ {
+-	tcpm_log_force(port, "VBUS off");
++	tcpm_log_force(port, "VBUS event received: off");
+ 	port->vbus_present = false;
+ 	port->vbus_never_low = false;
+ 	switch (port->state) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
new file mode 100644
index 000000000000..583c0f944c96
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
@@ -0,0 +1,52 @@
+From 4d4b3a03c2780d71614459f9306d4dee6504b3e2 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 14 Aug 2022 16:23:28 +0200
+Subject: usb: typec: tcpm: Unregister altmodes before registering new ones
+
+Just in case there are already altmodes registered. Otherwise the
+kernel will fail with:
+
+[50554.467172] sysfs: cannot create duplicate filename '/bus/typec/devices/port0-partner.0'
+[50554.467198] CPU: 2 PID: 897 Comm: 4-0022 Tainted: G         C        5.18.15-1-MANJARO-ARM #1
+[50554.467208] Hardware name: Pine64 PinePhonePro (DT)
+[50554.467214] Call trace:
+[50554.467218]  dump_backtrace.part.0+0xcc/0xe0
+[50554.467241]  show_stack+0x18/0x6c
+[50554.467249]  dump_stack_lvl+0x64/0x80
+[50554.467262]  dump_stack+0x18/0x34
+[50554.467270]  sysfs_warn_dup+0x60/0x7c
+[50554.467279]  sysfs_do_create_link_sd+0xf0/0x100
+[50554.467286]  sysfs_create_link+0x24/0x44
+[50554.467292]  bus_add_device+0x64/0x120
+[50554.467304]  device_add+0x320/0x890
+[50554.467312]  device_register+0x20/0x30
+[50554.467318]  typec_register_altmode+0x1e4/0x35c
+[50554.467330]  typec_partner_register_altmode+0x10/0x20
+[50554.467339]  tcpm_pd_rx_handler+0x1804/0x18e0
+[50554.467346]  kthread_worker_fn+0xa0/0x180
+[50554.467357]  kthread+0x108/0x10c
+[50554.467364]  ret_from_fork+0x10/0x20
+[50554.467528] typec port0-partner: failed to register alternate mode (-17)
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index 338426258539..b60bc1be25dc 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -1751,6 +1751,9 @@ static void tcpm_register_partner_altmodes(struct tcpm_port *port)
+ 		return;
+ 
+ 	for (i = 0; i < modep->altmodes; i++) {
++		typec_unregister_altmode(port->partner_altmode[i]);
++		port->partner_altmode[i] = NULL;
++
+ 		altmode = typec_partner_register_altmode(port->partner,
+ 						&modep->altmode_desc[i]);
+ 		if (IS_ERR(altmode)) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
new file mode 100644
index 000000000000..7cc40454a8d0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
@@ -0,0 +1,386 @@
+From 3bf7c75f7edfb6d0980860d7412276b755a63622 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 7 Nov 2021 19:24:40 +0100
+Subject: usb: typec: typec-extcon: Add typec -> extcon bridge driver
+
+This bridge connects standard Type C port interfaces for controling
+muxes, switches and usb roles to muxes, switches and usb role
+drivers controlled via extcon interface.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/Kconfig        |   7 +
+ drivers/usb/typec/Makefile       |   1 +
+ drivers/usb/typec/typec-extcon.c | 332 +++++++++++++++++++++++++++++++
+ 3 files changed, 340 insertions(+)
+ create mode 100644 drivers/usb/typec/typec-extcon.c
+
+diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig
+index 982b7c444a1f..9913435a0fd9 100644
+--- a/drivers/usb/typec/Kconfig
++++ b/drivers/usb/typec/Kconfig
+@@ -122,6 +122,13 @@ config TYPEC_WUSB3801
+ 	  If you choose to build this driver as a dynamically linked module, the
+ 	  module will be called wusb3801.ko.
+ 
++config TYPEC_EXTCON
++	tristate "Type-C switch/mux -> extcon interface bridge driver"
++	depends on USB_ROLE_SWITCH
++	help
++	  Say Y or M here if your system needs bridging between typec class
++	  and extcon interfaces.
++
+ source "drivers/usb/typec/mux/Kconfig"
+ 
+ source "drivers/usb/typec/altmodes/Kconfig"
+diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile
+index 3f8ff94ad294..0b2d1d251c53 100644
+--- a/drivers/usb/typec/Makefile
++++ b/drivers/usb/typec/Makefile
+@@ -12,4 +12,5 @@ obj-$(CONFIG_TYPEC_HD3SS3220)	+= hd3ss3220.o
+ obj-$(CONFIG_TYPEC_STUSB160X) 	+= stusb160x.o
+ obj-$(CONFIG_TYPEC_RT1719)	+= rt1719.o
+ obj-$(CONFIG_TYPEC_WUSB3801)	+= wusb3801.o
++obj-$(CONFIG_TYPEC_EXTCON)	+= typec-extcon.o
+ obj-$(CONFIG_TYPEC)		+= mux/
+diff --git a/drivers/usb/typec/typec-extcon.c b/drivers/usb/typec/typec-extcon.c
+new file mode 100644
+index 000000000000..e460f35c8390
+--- /dev/null
++++ b/drivers/usb/typec/typec-extcon.c
+@@ -0,0 +1,332 @@
++/*
++ * typec -> extcon bridge
++ * Copyright (c) 2021 Ondřej Jirman <megi@xff.cz>
++ *
++ * This driver bridges standard type-c interfaces to drivers that
++ * expect extcon interface.
++ */
++
++#include <linux/delay.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/power_supply.h>
++#include <linux/platform_device.h>
++#include <linux/usb/pd.h>
++#include <linux/usb/role.h>
++#include <linux/usb/typec.h>
++#include <linux/usb/typec_dp.h>
++#include <linux/usb/typec_mux.h>
++#include <linux/extcon-provider.h>
++
++struct typec_extcon {
++        struct device *dev;
++
++	/* consumers */
++	struct usb_role_switch *role_sw;
++        struct typec_switch_dev *sw;
++        struct typec_mux_dev *mux;
++
++	/* providers */
++	struct extcon_dev *extcon;
++	struct notifier_block extcon_nb;
++
++	/* cached state from typec controller */
++	enum usb_role role;
++	enum typec_orientation orientation;
++	struct typec_altmode alt;
++	unsigned long mode;
++	bool has_alt;
++	struct mutex lock;
++};
++
++static const unsigned int typec_extcon_cable[] = {
++	EXTCON_DISP_DP,
++
++	EXTCON_USB,
++	EXTCON_USB_HOST,
++
++	EXTCON_CHG_USB_SDP,
++	EXTCON_CHG_USB_CDP,
++	EXTCON_CHG_USB_DCP,
++	EXTCON_CHG_USB_ACA,
++
++	EXTCON_NONE,
++};
++
++static void typec_extcon_set_cable(struct typec_extcon *tce, int id, bool on,
++				   union extcon_property_value prop_ss,
++				   union extcon_property_value prop_or)
++{
++	union extcon_property_value cur_ss, cur_or;
++	bool prop_diff = false;
++	int ret;
++
++	ret = extcon_get_property(tce->extcon, id,
++				  EXTCON_PROP_USB_SS, &cur_ss);
++	if (ret || cur_ss.intval != prop_ss.intval)
++		prop_diff = true;
++
++	ret = extcon_get_property(tce->extcon, id,
++				  EXTCON_PROP_USB_TYPEC_POLARITY, &cur_or);
++	if (ret || cur_or.intval != prop_or.intval)
++		prop_diff = true;
++
++	if (!on && extcon_get_state(tce->extcon, id)) {
++		extcon_set_state_sync(tce->extcon, id, false);
++	} else if (on && (!extcon_get_state(tce->extcon, id) || prop_diff)) {
++		extcon_set_state(tce->extcon, id, true);
++		extcon_set_property(tce->extcon, id,
++				    EXTCON_PROP_USB_SS, prop_ss);
++		extcon_set_property(tce->extcon, id,
++				    EXTCON_PROP_USB_TYPEC_POLARITY, prop_or);
++		extcon_sync(tce->extcon, id);
++	}
++}
++
++static int typec_extcon_sync_extcon(struct typec_extcon *tce)
++{
++	union extcon_property_value prop_ss, prop_or;
++	bool has_dp = false;
++
++        mutex_lock(&tce->lock);
++
++	/* connector is disconnected */
++	if (tce->orientation == TYPEC_ORIENTATION_NONE) {
++		typec_extcon_set_cable(tce, EXTCON_USB, false, prop_ss, prop_or);
++		typec_extcon_set_cable(tce, EXTCON_USB_HOST, false, prop_ss, prop_or);
++		typec_extcon_set_cable(tce, EXTCON_DISP_DP, false, prop_ss, prop_or);
++
++                goto out_unlock;
++	}
++
++	prop_or.intval = tce->orientation == TYPEC_ORIENTATION_NORMAL ? 0 : 1;
++	prop_ss.intval = 0;
++
++	if (tce->has_alt && tce->alt.svid == USB_TYPEC_DP_SID) {
++		switch (tce->mode) {
++		case TYPEC_STATE_SAFE:
++			break;
++		case TYPEC_DP_STATE_C:
++		case TYPEC_DP_STATE_E:
++			has_dp = true;
++			break;
++		case TYPEC_DP_STATE_D:
++			has_dp = true;
++			fallthrough;
++		case TYPEC_STATE_USB:
++			prop_ss.intval = 1;
++			break;
++		default:
++			dev_err(tce->dev, "unhandled mux mode=%lu\n", tce->mode);
++			break;
++		}
++	}
++
++	typec_extcon_set_cable(tce, EXTCON_USB,
++			tce->role == USB_ROLE_DEVICE, prop_ss, prop_or);
++	typec_extcon_set_cable(tce, EXTCON_USB_HOST,
++			tce->role == USB_ROLE_HOST, prop_ss, prop_or);
++
++	typec_extcon_set_cable(tce, EXTCON_DISP_DP, has_dp, prop_ss, prop_or);
++
++out_unlock:
++	mutex_unlock(&tce->lock);
++	return 0;
++}
++
++static int typec_extcon_sw_set(struct typec_switch_dev *sw,
++			       enum typec_orientation orientation)
++{
++        struct typec_extcon *tce = typec_switch_get_drvdata(sw);
++
++	dev_dbg(tce->dev, "SW SET: orientation=%d\n", orientation);
++
++        mutex_lock(&tce->lock);
++	tce->orientation = orientation;
++        mutex_unlock(&tce->lock);
++
++	typec_extcon_sync_extcon(tce);
++
++        return 0;
++}
++
++static int typec_extcon_mux_set(struct typec_mux_dev *mux,
++				struct typec_mux_state *state)
++{
++        struct typec_extcon *tce = typec_mux_get_drvdata(mux);
++	struct typec_altmode *alt = state->alt;
++
++	dev_dbg(tce->dev, "MUX SET: state->mode=%lu\n", state->mode);
++	if (alt)
++		dev_dbg(tce->dev, "      ...alt: svid=%04hx mode=%d vdo=%08x active=%u\n",
++			alt->svid, alt->mode, alt->vdo, alt->active);
++
++        mutex_lock(&tce->lock);
++	tce->mode = state->mode;
++	tce->has_alt = alt != NULL;
++        if (alt)
++		tce->alt = *alt;
++	mutex_unlock(&tce->lock);
++
++	typec_extcon_sync_extcon(tce);
++
++        return 0;
++}
++
++static int typec_extcon_usb_set_role(struct usb_role_switch *sw,
++				     enum usb_role role)
++{
++        struct typec_extcon *tce = usb_role_switch_get_drvdata(sw);
++
++	dev_dbg(tce->dev, "ROLE SET: role=%d\n", role);
++
++        mutex_lock(&tce->lock);
++	tce->role = role;
++	mutex_unlock(&tce->lock);
++
++	typec_extcon_sync_extcon(tce);
++
++        return 0;
++}
++
++static int typec_extcon_notifier(struct notifier_block *nb,
++					 unsigned long action, void *data)
++{
++	struct typec_extcon *tce = container_of(nb, struct typec_extcon, extcon_nb);
++
++	bool sdp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_SDP);
++	bool cdp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_CDP);
++	bool dcp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_DCP);
++	bool usb = extcon_get_state(tce->extcon, EXTCON_USB);
++	bool usb_host = extcon_get_state(tce->extcon, EXTCON_USB_HOST);
++	bool dp = extcon_get_state(tce->extcon, EXTCON_DISP_DP);
++
++	dev_info(tce->dev, "extcon changed sdp=%d cdp=%d dcp=%d usb=%d usb_host=%d dp=%d\n",
++		 sdp, cdp, dcp, usb, usb_host, dp);
++
++	return NOTIFY_OK;
++}
++
++static int typec_extcon_probe(struct platform_device *pdev)
++{
++        struct typec_switch_desc sw_desc = { };
++        struct typec_mux_desc mux_desc = { };
++        struct usb_role_switch_desc role_desc = { };
++        struct device *dev = &pdev->dev;
++        struct typec_extcon *tce;
++        int ret = 0;
++
++        tce = devm_kzalloc(dev, sizeof(*tce), GFP_KERNEL);
++        if (!tce)
++                return -ENOMEM;
++
++        tce->dev = &pdev->dev;
++	mutex_init(&tce->lock);
++	tce->mode = TYPEC_STATE_SAFE;
++
++	sw_desc.drvdata = tce;
++	sw_desc.fwnode = dev->fwnode;
++	sw_desc.set = typec_extcon_sw_set;
++
++	tce->sw = typec_switch_register(dev, &sw_desc);
++	if (IS_ERR(tce->sw))
++		return dev_err_probe(dev, PTR_ERR(tce->sw),
++				     "Error registering typec switch\n");
++
++	mux_desc.drvdata = tce;
++	mux_desc.fwnode = dev->fwnode;
++	mux_desc.set = typec_extcon_mux_set;
++
++	tce->mux = typec_mux_register(dev, &mux_desc);
++	if (IS_ERR(tce->mux)) {
++		ret = dev_err_probe(dev, PTR_ERR(tce->mux),
++				    "Error registering typec mux\n");
++		goto err_sw;
++	}
++
++	role_desc.driver_data = tce;
++	role_desc.fwnode = dev->fwnode;
++	role_desc.name = fwnode_get_name(dev->fwnode);
++	role_desc.set = typec_extcon_usb_set_role;
++
++	tce->role_sw = usb_role_switch_register(dev, &role_desc);
++	if (IS_ERR(tce->role_sw)) {
++		ret = dev_err_probe(dev, PTR_ERR(tce->role_sw),
++				    "Error registering USB role switch\n");
++		goto err_mux;
++	}
++
++	tce->extcon = devm_extcon_dev_allocate(dev, typec_extcon_cable);
++	if (IS_ERR(tce->extcon)) {
++		ret = PTR_ERR(tce->extcon);
++		goto err_role;
++	}
++
++	ret = devm_extcon_dev_register(dev, tce->extcon);
++	if (ret) {
++		ret = dev_err_probe(dev, ret, "failed to register extcon device\n");
++		goto err_role;
++	}
++
++	extcon_set_property_capability(tce->extcon, EXTCON_USB,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(tce->extcon, EXTCON_USB,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++	extcon_set_property_capability(tce->extcon, EXTCON_USB_HOST,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(tce->extcon, EXTCON_USB_HOST,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++	extcon_set_property_capability(tce->extcon, EXTCON_DISP_DP,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(tce->extcon, EXTCON_DISP_DP,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++
++	tce->extcon_nb.notifier_call = typec_extcon_notifier;
++	ret = devm_extcon_register_notifier_all(dev, tce->extcon, &tce->extcon_nb);
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to register extcon notifier\n");
++		goto err_role;
++	}
++
++	return 0;
++
++err_role:
++	usb_role_switch_unregister(tce->role_sw);
++err_mux:
++	typec_mux_unregister(tce->mux);
++err_sw:
++	typec_switch_unregister(tce->sw);
++	return ret;
++}
++
++static int typec_extcon_remove(struct platform_device *pdev)
++{
++        struct typec_extcon *tce = platform_get_drvdata(pdev);
++
++	usb_role_switch_unregister(tce->role_sw);
++	typec_mux_unregister(tce->mux);
++	typec_switch_unregister(tce->sw);
++
++        return 0;
++}
++
++static struct of_device_id typec_extcon_of_match_table[] = {
++        { .compatible = "linux,typec-extcon-bridge" },
++        { },
++};
++MODULE_DEVICE_TABLE(of, typec_extcon_of_match_table);
++
++static struct platform_driver typec_extcon_driver = {
++        .driver = {
++                .name = "typec-extcon",
++                .of_match_table = typec_extcon_of_match_table,
++        },
++        .probe = typec_extcon_probe,
++        .remove = typec_extcon_remove,
++};
++
++module_platform_driver(typec_extcon_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("typec -> extcon bridge driver");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
new file mode 100644
index 000000000000..40b6320e03e0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
@@ -0,0 +1,48 @@
+From 3a48a58fb6460a29600ad9cbf67072b620360bb7 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 9 Feb 2023 20:33:50 +0100
+Subject: usb: typec: typec-extcon: Allow to force reset on each mux change
+
+This may help with some Alt-DP USB adapters.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/typec-extcon.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/usb/typec/typec-extcon.c b/drivers/usb/typec/typec-extcon.c
+index 12be8f203f76..d5a7f40f0921 100644
+--- a/drivers/usb/typec/typec-extcon.c
++++ b/drivers/usb/typec/typec-extcon.c
+@@ -19,6 +19,10 @@
+ #include <linux/usb/typec_mux.h>
+ #include <linux/extcon-provider.h>
+ 
++static bool reset_on_mux;
++module_param(reset_on_mux, bool, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(reset_on_mux, "Set DP=0 on each type-c mux change");
++
+ struct typec_extcon {
+         struct device *dev;
+ 
+@@ -162,6 +166,17 @@ static int typec_extcon_mux_set(struct typec_mux_dev *mux,
+ 		dev_dbg(tce->dev, "      ...alt: svid=%04hx mode=%d vdo=%08x active=%u\n",
+ 			alt->svid, alt->mode, alt->vdo, alt->active);
+ 
++        mutex_lock(&tce->lock);
++	if (reset_on_mux && alt != NULL && tce->has_alt) {
++		tce->mode = state->mode;
++		tce->has_alt = false;
++		mutex_unlock(&tce->lock);
++
++		typec_extcon_sync_extcon(tce);
++	} else {
++		mutex_unlock(&tce->lock);
++	}
++
+         mutex_lock(&tce->lock);
+ 	tce->mode = state->mode;
+ 	tce->has_alt = alt != NULL;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
new file mode 100644
index 000000000000..b50ecc7048c9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
@@ -0,0 +1,25 @@
+From aabe1b3a69cebd52863b079934e67c0e36c65f21 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 23 Mar 2022 14:21:34 +0100
+Subject: usb: typec: typec-extcon: Enable debugging for now
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/typec-extcon.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/typec/typec-extcon.c b/drivers/usb/typec/typec-extcon.c
+index e460f35c8390..12be8f203f76 100644
+--- a/drivers/usb/typec/typec-extcon.c
++++ b/drivers/usb/typec/typec-extcon.c
+@@ -5,6 +5,7 @@
+  * This driver bridges standard type-c interfaces to drivers that
+  * expect extcon interface.
+  */
++#define DEBUG
+ 
+ #include <linux/delay.h>
+ #include <linux/kernel.h>
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch
new file mode 100644
index 000000000000..f8c0336b8e3d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch
@@ -0,0 +1,1276 @@
+From 0640083106edc0e9ff79802ae5c0f1f58a6a4960 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 24 Sep 2019 17:53:02 +0200
+Subject: video: fbdev: eInk display driver for A13 based PocketBooks
+
+This driver uses DEBE and TCON0 to bitbang the ED060XD4 eInk panel
+protocol on LCD data pins. There's no other sane way to do it,
+as PocketBook e-book reader was designed this way.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/video/fbdev/Kconfig           |   12 +
+ drivers/video/fbdev/Makefile          |    4 +
+ drivers/video/fbdev/sun5i-eink-neon.c |   49 ++
+ drivers/video/fbdev/sun5i-eink.c      | 1158 +++++++++++++++++++++++++
+ 4 files changed, 1223 insertions(+)
+ create mode 100644 drivers/video/fbdev/sun5i-eink-neon.c
+ create mode 100644 drivers/video/fbdev/sun5i-eink.c
+
+diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
+index ea36c6956bf3..9032669e8dff 100644
+--- a/drivers/video/fbdev/Kconfig
++++ b/drivers/video/fbdev/Kconfig
+@@ -657,6 +657,18 @@ config FB_ATMEL
+ 	help
+ 	  This enables support for the AT91 LCD Controller.
+ 
++config FB_SUN5I_EINK
++	tristate "eInk display Framebuffer Support (A13 based eBook readers)"
++	depends on FB
++	select FB_MODE_HELPERS
++	select FB_CFB_FILLRECT
++	select FB_CFB_COPYAREA
++	select FB_CFB_IMAGEBLIT
++	select BITREVERSE
++	help
++	  This driver supports PocketBook Touch Lux 3 e-paper display.
++
++
+ config FB_NVIDIA
+ 	tristate "nVidia Framebuffer Support"
+ 	depends on FB && PCI
+diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile
+index 3eecd51267fa..e4760c66d14a 100644
+--- a/drivers/video/fbdev/Makefile
++++ b/drivers/video/fbdev/Makefile
+@@ -127,3 +127,7 @@ obj-$(CONFIG_FB_SIMPLE)           += simplefb.o
+ 
+ # the test framebuffer is last
+ obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
++
++obj-$(CONFIG_FB_SUN5I_EINK)       += sun5ieink.o
++sun5ieink-objs = sun5i-eink.o sun5i-eink-neon.o
++CFLAGS_sun5i-eink-neon.o	  += -march=armv7-a -mfloat-abi=softfp -mfpu=neon -ffreestanding -isystem $(shell $(CC) -print-file-name=include)
+diff --git a/drivers/video/fbdev/sun5i-eink-neon.c b/drivers/video/fbdev/sun5i-eink-neon.c
+new file mode 100644
+index 000000000000..9e2386fd91ea
+--- /dev/null
++++ b/drivers/video/fbdev/sun5i-eink-neon.c
+@@ -0,0 +1,49 @@
++#include <linux/export.h>
++#include <linux/compiler.h>
++#include <linux/types.h>
++#include <arm_neon.h>
++
++void eink_ctlstream_fill_data_neon(u32* cmd, u8* fb, int stride,
++				   int sources, int gates, u32 masks[4])
++{
++	uint32x4_t mask;
++	int g, s;
++	int cutoff = sources / 4 / 8 / 3 * 2;
++
++	mask = vdupq_n_u32(0);
++
++	for (g = 0; g < gates; g++) {
++		if (unlikely(g == 0))
++			mask = vdupq_n_u32(masks[0]);
++		else
++			mask = vdupq_n_u32(masks[2]);
++
++		for (s = 0; s < sources / 4 / 8; s++) {
++			uint8x8_t src;
++			uint16x8_t dst;
++			uint32x4_t out;
++
++			if (unlikely(s == cutoff))
++				mask = vdupq_n_u32(g == 0 ? masks[1] : masks[3]);
++
++			src = vld1_u8(fb);
++			fb += 8;
++
++			dst = vshll_n_u8(src, 3);
++			dst = vsliq_n_u16(dst, vmovl_u8(vshr_n_u8(src, 3)), 8);
++
++			out = vmovl_u16(vget_low_u16(dst));
++			out = vorrq_u32(out, mask);
++			vst1q_u32(cmd, out);
++			cmd += 4;
++
++			out = vmovl_u16(vget_high_u16(dst));
++			out = vorrq_u32(out, mask);
++			vst1q_u32(cmd, out);
++			cmd += 4;
++		}
++
++		cmd += stride - sources / 4;
++	}
++}
++EXPORT_SYMBOL_GPL(eink_ctlstream_fill_data_neon);
+diff --git a/drivers/video/fbdev/sun5i-eink.c b/drivers/video/fbdev/sun5i-eink.c
+new file mode 100644
+index 000000000000..daceb0613922
+--- /dev/null
++++ b/drivers/video/fbdev/sun5i-eink.c
+@@ -0,0 +1,1158 @@
++/*
++ * Copyright Ondrej Jirman <megi@xff.cz>
++ */
++#include <linux/cdev.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/gpio/consumer.h>
++#include <linux/interrupt.h>
++#include <linux/iopoll.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++#include <linux/iio/consumer.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/wait.h>
++#include <linux/workqueue.h>
++#include <asm/neon.h>
++
++// {{{ Registry defines
++
++#define SUN4I_TCON_GCTL_REG			0x0
++#define SUN4I_TCON_GCTL_TCON_ENABLE			BIT(31)
++#define SUN4I_TCON_GCTL_IOMAP_MASK			BIT(0)
++#define SUN4I_TCON_GCTL_IOMAP_TCON1			(1 << 0)
++#define SUN4I_TCON_GCTL_IOMAP_TCON0			(0 << 0)
++
++#define SUN4I_TCON_GINT0_REG			0x4
++#define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe)		BIT(31 - (pipe))
++#define SUN4I_TCON_GINT0_VBLANK_INT(pipe)		BIT(15 - (pipe))
++#define SUN4I_TCON_GINT0_LINE_ENABLE(pipe)		BIT(29 - (pipe))
++#define SUN4I_TCON_GINT0_LINE_INT(pipe)			BIT(13 - (pipe))
++
++#define SUN4I_TCON_GINT1_REG			0x8
++
++#define SUN4I_TCON0_CTL_REG			0x40
++#define SUN4I_TCON0_CTL_TCON_ENABLE			BIT(31)
++#define SUN4I_TCON0_CTL_IF_MASK				GENMASK(25, 24)
++#define SUN4I_TCON0_CTL_IF_8080				(1 << 24)
++#define SUN4I_TCON0_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
++#define SUN4I_TCON0_CTL_CLK_DELAY(delay)		((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
++#define SUN4I_TCON0_CTL_SRC_SEL_MASK			GENMASK(2, 0)
++
++#define SUN4I_TCON0_DCLK_REG			0x44
++#define SUN4I_TCON0_DCLK_GATE_BIT			(31)
++#define SUN4I_TCON0_DCLK_DIV_SHIFT			(0)
++#define SUN4I_TCON0_DCLK_DIV_WIDTH			(7)
++
++#define SUN4I_TCON0_BASIC0_REG			0x48
++#define SUN4I_TCON0_BASIC0_X(width)			((((width) - 1) & 0xfff) << 16)
++#define SUN4I_TCON0_BASIC0_Y(height)			(((height) - 1) & 0xfff)
++
++#define SUN4I_TCON0_BASIC1_REG			0x4c
++#define SUN4I_TCON0_BASIC1_H_TOTAL(total)		((((total) - 1) & 0x1fff) << 16)
++#define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
++
++#define SUN4I_TCON0_BASIC2_REG			0x50
++#define SUN4I_TCON0_BASIC2_V_TOTAL(total)		(((total) & 0x1fff) << 16)
++#define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
++
++#define SUN4I_TCON0_BASIC3_REG			0x54
++#define SUN4I_TCON0_BASIC3_H_SYNC(width)		((((width) - 1) & 0x7ff) << 16)
++#define SUN4I_TCON0_BASIC3_V_SYNC(height)		(((height) - 1) & 0x7ff)
++
++#define SUN4I_TCON0_HV_IF_REG			0x58
++
++#define SUN4I_TCON0_IO_POL_REG			0x88
++#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase)		((phase & 3) << 28)
++#define SUN4I_TCON0_IO_POL_DE_NEGATIVE			BIT(27)
++#define SUN4I_TCON0_IO_POL_DCLK_NEGATIVE		BIT(26)
++#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE		BIT(25)
++#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE		BIT(24)
++
++#define SUN4I_TCON0_IO_TRI_REG			0x8c
++#define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE		BIT(25)
++#define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE		BIT(24)
++#define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins)	GENMASK(pins, 0)
++
++#define SUN4I_BACKEND_MODCTL_REG		0x800
++#define SUN4I_BACKEND_MODCTL_LINE_SEL			BIT(29)
++#define SUN4I_BACKEND_MODCTL_ITLMOD_EN			BIT(28)
++#define SUN4I_BACKEND_MODCTL_OUT_SEL			GENMASK(22, 20)
++#define SUN4I_BACKEND_MODCTL_OUT_LCD0				(0 << 20)
++#define SUN4I_BACKEND_MODCTL_OUT_LCD1				(1 << 20)
++#define SUN4I_BACKEND_MODCTL_OUT_FE0				(6 << 20)
++#define SUN4I_BACKEND_MODCTL_OUT_FE1				(7 << 20)
++#define SUN4I_BACKEND_MODCTL_HWC_EN			BIT(16)
++#define SUN4I_BACKEND_MODCTL_LAY_EN(l)			BIT(8 + l)
++#define SUN4I_BACKEND_MODCTL_OCSC_EN			BIT(5)
++#define SUN4I_BACKEND_MODCTL_DFLK_EN			BIT(4)
++#define SUN4I_BACKEND_MODCTL_DLP_START_CTL		BIT(2)
++#define SUN4I_BACKEND_MODCTL_START_CTL			BIT(1)
++#define SUN4I_BACKEND_MODCTL_DEBE_EN			BIT(0)
++
++#define SUN4I_BACKEND_BACKCOLOR_REG		0x804
++#define SUN4I_BACKEND_BACKCOLOR(r, g, b)		(((r) << 16) | ((g) << 8) | (b))
++
++#define SUN4I_BACKEND_DISSIZE_REG		0x808
++#define SUN4I_BACKEND_DISSIZE(w, h)			(((((h) - 1) & 0xffff) << 16) | \
++							 (((w) - 1) & 0xffff))
++
++#define SUN4I_BACKEND_LAYSIZE_REG(l)		(0x810 + (0x4 * (l)))
++#define SUN4I_BACKEND_LAYSIZE(w, h)			(((((h) - 1) & 0x1fff) << 16) | \
++							 (((w) - 1) & 0x1fff))
++
++#define SUN4I_BACKEND_LAYCOOR_REG(l)		(0x820 + (0x4 * (l)))
++#define SUN4I_BACKEND_LAYCOOR(x, y)			((((u32)(y) & 0xffff) << 16) | \
++							 ((u32)(x) & 0xffff))
++
++#define SUN4I_BACKEND_LAYLINEWIDTH_REG(l)	(0x840 + (0x4 * (l)))
++
++#define SUN4I_BACKEND_LAYFB_L32ADD_REG(l)	(0x850 + (0x4 * (l)))
++
++#define SUN4I_BACKEND_LAYFB_H4ADD_REG		0x860
++#define SUN4I_BACKEND_LAYFB_H4ADD_MSK(l)		GENMASK(3 + ((l) * 8), (l) * 8)
++#define SUN4I_BACKEND_LAYFB_H4ADD(l, val)		((val) << ((l) * 8))
++
++#define SUN4I_BACKEND_REGBUFFCTL_REG		0x870
++#define SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS		BIT(1)
++#define SUN4I_BACKEND_REGBUFFCTL_LOADCTL		BIT(0)
++
++#define SUN4I_BACKEND_CKMAX_REG			0x880
++#define SUN4I_BACKEND_CKMIN_REG			0x884
++#define SUN4I_BACKEND_CKCFG_REG			0x888
++#define SUN4I_BACKEND_ATTCTL_REG0(l)		(0x890 + (0x4 * (l)))
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK	GENMASK(31, 24)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(x)		((x) << 24)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK	BIT(15)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(x)		((x) << 15)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK	GENMASK(11, 10)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(x)			((x) << 10)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_WORKMOD_MASK	GENMASK(23, 22)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_WORKMOD(x)		((x) << 22)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN		BIT(2)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN		BIT(1)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN	BIT(0)
++
++#define SUN4I_BACKEND_ATTCTL_REG1(l)		(0x8a0 + (0x4 * (l)))
++#define SUN4I_BACKEND_ATTCTL_REG1_LAY_HSCAFCT		GENMASK(15, 14)
++#define SUN4I_BACKEND_ATTCTL_REG1_LAY_WSCAFCT		GENMASK(13, 12)
++#define SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT		GENMASK(11, 8)
++#define SUN4I_BACKEND_LAY_FBFMT_1BPP				(0 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_2BPP				(1 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_4BPP				(2 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_8BPP				(3 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGB655				(4 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGB565				(5 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGB556				(6 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_ARGB1555			(7 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGBA5551			(8 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_XRGB8888			(9 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_ARGB8888			(10 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGB888				(11 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_ARGB4444			(12 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGBA4444			(13 << 8)
++
++// }}}
++
++#define EINK_IOCTL_UPDATE _IO('A', 0)
++//#define EINK_IOCTL_STATUS _IOR('A', 2, int)
++
++enum {
++	EINK_REQ_NONE = 0,
++	EINK_REQ_UPDATE,
++	EINK_REQ_POWERDOWN,
++};
++
++enum {
++	EINK_WORKING,
++	EINK_OPEN,
++	EINK_WAITING_INT,
++	EINK_BE_SETUP,
++};
++
++struct eink_dev {
++	struct device *dev;
++
++	// io
++	struct pinctrl* pinctrl;
++	struct pinctrl_state *pinctrl_active;
++	struct pinctrl_state *pinctrl_idle;
++	struct gpio_descs* gpios;
++
++	// power
++	struct regulator *panel_supply;
++	struct timer_list powerdown_timer;
++	bool powered;
++
++	// tcon0
++	struct clk_bulk_data *clks;
++	int num_clks;
++
++        struct reset_control *rstc;
++	struct regmap *tcon_regs;
++	struct regmap *be_regs;
++	int irq;
++
++	// framebuffers
++	u8* framebuffers[2];
++	u32* ctlstream;
++	dma_addr_t ctlstream_paddr;
++	size_t ctlstream_size; // byte size
++
++	// control device
++	struct cdev cdev;
++	dev_t major;
++	bool is_open; // device can be used by only one user
++
++	// rendering work
++	spinlock_t lock;
++	wait_queue_head_t waitqueue;
++	struct workqueue_struct *wq;
++	struct work_struct work;
++	unsigned long flags[1];
++	int last_request;
++
++	const struct eink_panel_config* panel;
++};
++
++struct eink_panel_config {
++	int sources;
++	int gates;
++	int h_lead;
++	int h_trail;
++	int v_extra;
++};
++
++static const struct eink_panel_config eink_ed060xd4_panel = {
++	.sources = 1024,
++	.gates = 758,
++	.h_lead = 40, // 1000ns (should be multiple of 8 for 256-bit alignment)
++	.h_trail = 8, // should be multiple of 8 for 256-bit alignment
++	.v_extra = 9,
++};
++
++// buf format is 1 byte per pixel, len needs to be multiple of 4 bytes
++
++/* PocketBook 626(2) (Touch Lux 3) port D <-> Panel pin map */
++
++#define	D0        BIT(3)
++#define	D1        BIT(4)
++#define	D2        BIT(5)
++#define	D3        BIT(6)
++#define	D4        BIT(7)
++
++#define	D5       BIT(10)
++#define	D6       BIT(11)
++#define	D7       BIT(12)
++#define	S_LE     BIT(13)
++#define	G_MODE1  BIT(15)
++
++#define	S_OE     BIT(20)
++#define	S_SP     BIT(21)
++#define	G_CLK    BIT(22)
++#define	G_SP     BIT(23)
++
++/*
++ * we need to encode stream of control signals for various operations
++ * into separate rows:
++ *
++ * - sequence for starting a frame
++ * - three leading G_CLK pulses
++ * - sequence for all data rows
++ *   - wait time with OE for previous row
++ * - wait time for the last row without shifting in more data
++ * - trailing row with a sequence for ending a frame
++ *
++ * So we have to have:
++ * - 6 special rows with no data + all the data rows
++ * - all of these have to have the same width
++ * - we want to use TCON to manage timing of the OE via HT/HBP settings
++ *
++ * Timings:
++ * - we use 20MHz clock (50ns period)
++ * - we have to spend 256 clocks per row, pushing data
++ * - we want to have 85Hz frame refresh rate
++ *   - 11765us budget per frame
++ *   - minimum G_CLK low time is 500ns, minimum G_CLK cycle time is 5us
++ *     - G_SP 100ns setup (to G_CLK H->L)/hold time(after G_CLK H->L)
++ *   - LE pulse width >150ns
++ *     - LE delay before more data 200ns
++ *   - 12us time the output reacts to LE (this should be hsync time/hbp)
++ *   - at 20MHz, time to load data is 13us (about 100 FPS)
++ */
++static void eink_ctlstream_prepare(struct eink_dev* eink)
++{
++	const struct eink_panel_config* pc = eink->panel;
++	u32* p = eink->ctlstream;
++	int row_width = pc->sources / 4 + pc->h_lead + pc->h_trail; // ~262
++	int i, j, t, r;
++	u32 base;
++
++#define SET_PINS(t, v) { \
++		for (i = 0; i < t; i++) \
++			*p++ = v; \
++		r -= t; \
++	}
++
++	// prepare a startup row
++	t = row_width / 3;
++
++	r = row_width;
++	SET_PINS(20, G_MODE1 | G_SP | S_SP            );
++	SET_PINS(2*t,G_MODE1 | G_SP | S_SP | G_CLK    );
++	SET_PINS(r,  G_MODE1 | G_SP | S_SP            );
++
++	r = row_width;
++	SET_PINS(t,  G_MODE1 | G_SP | S_SP | G_CLK    );
++	SET_PINS(t,  G_MODE1 |        S_SP | G_CLK    );
++	SET_PINS(r,  G_MODE1 |        S_SP            );
++
++	r = row_width;
++	SET_PINS(t,  G_MODE1 |        S_SP | G_CLK    );
++	SET_PINS(t,  G_MODE1 | G_SP | S_SP | G_CLK    );
++	SET_PINS(r,  G_MODE1 | G_SP | S_SP            );
++
++	// three empty rows
++	for (j = 0; j < 3; j++) {
++		r = row_width;
++
++		SET_PINS(2*t,  G_MODE1 | G_SP | S_SP | G_CLK    );
++		SET_PINS(r,    G_MODE1 | G_SP | S_SP            );
++	}
++
++	// extra row is there to keep S_OE high for the previous last data
++	// row that was shifted in
++	for (j = 0; j < pc->gates + 1; j++) {
++		base = G_MODE1 | G_SP;
++
++                // We have 40 periods here to work with here (h_lead).
++		r = pc->h_lead;
++
++		// S_SP goes high after the last data and there's 2us
++		// delay (it may even go high during the last data period?)
++		SET_PINS(20, base | S_SP); // 1000ns for tLEdly
++		base &= ~S_OE;
++		SET_PINS(2,  base | S_SP);
++		SET_PINS(6,  base | S_SP | (j > 0 ? S_LE : 0)); // 300ns for tLEw
++		if (j > 0)
++			base |= S_OE;
++		SET_PINS(2,  base | S_SP | (j > 0 ? S_LE : 0));  // S_OE goes high
++		SET_PINS(r-2,base | S_SP); // 400ns for tLEoff
++		SET_PINS(r,  base | S_SP | G_CLK); // 400ns for tLEoff
++
++		if (j >= pc->gates)
++			base |= S_SP;
++
++		// start loading data immediately at S_SP going low
++		r = pc->sources / 4;
++		t = r / 3;
++		SET_PINS(t,  base | G_CLK);
++		SET_PINS(r,  base);
++
++		r = pc->h_trail;
++		SET_PINS(r,  base | S_SP);
++	}
++
++	r = row_width;
++	SET_PINS(r,               G_SP | S_SP                   );
++
++	// this last row will be stopped by an interrupt before finishing
++	// completely, so it's a dummy one
++	r = row_width;
++	SET_PINS(r,               G_SP | S_SP                   );
++}
++
++void eink_ctlstream_fill_data_neon(u32* cmd, u8* fb, int stride,
++				   int sources, int gates, u32 masks[4]);
++
++static void eink_ctlstream_fill_data(struct eink_dev* eink, u8* fb)
++{
++	const struct eink_panel_config* pc = eink->panel;
++	int row_width = pc->sources / 4 + pc->h_lead + pc->h_trail;
++	u32 masks[4] = {
++		G_MODE1 | G_SP | G_CLK,
++		G_MODE1 | G_SP,
++		G_MODE1 | G_SP | S_OE | G_CLK,
++		G_MODE1 | G_SP | S_OE,
++	};
++
++	kernel_neon_begin();
++	eink_ctlstream_fill_data_neon(eink->ctlstream + 6 * row_width + pc->h_lead,
++				      fb, row_width, pc->sources,
++				      pc->gates, masks);
++	kernel_neon_end();
++}
++
++static int eink_set_power(struct eink_dev* eink, bool en)
++{
++	int ret;
++
++	if (!en != !eink->powered) {
++		dev_warn(eink->dev, "%sable power supply", en ? "en" : "dis");
++
++		if (en)
++			ret = regulator_enable(eink->panel_supply);
++		else
++			ret = regulator_disable(eink->panel_supply);
++		if (ret) {
++			dev_err(eink->dev, "can't %sable power supply (%d)",
++				en ? "en" : "dis", ret);
++			return ret;
++		}
++	}
++
++	if (en)
++		mod_timer(&eink->powerdown_timer,
++			  jiffies + msecs_to_jiffies(5000));
++	else
++		del_timer_sync(&eink->powerdown_timer);
++
++	eink->powered = en;
++	return 0;
++}
++
++__maybe_unused
++static void print_time(struct device* dev, u64 ts, char *buf)
++{
++	do_div(ts, 1000);
++	dev_info(dev, "[%s] %6lu us", buf, (unsigned long)ts);
++}
++
++// DCLK = 20MHz
++static int eink_update(struct eink_dev* eink)
++{
++	struct regmap *tcon = eink->tcon_regs;
++	struct regmap *be = eink->be_regs;
++	unsigned long sclk_rate;
++	u32 ddiv = 6, w, h;
++	u32 lo_paddr, hi_paddr;
++	u32 vbp = 1, hbp = 40;
++	int ret;
++
++	ret = eink_set_power(eink, 1);
++	if (ret)
++		return ret;
++
++	sclk_rate = clk_get_rate(eink->clks[1].clk);
++	if (sclk_rate == 0)
++		return -EINVAL;
++
++	spin_lock(&eink->lock);
++	eink_ctlstream_fill_data(eink, eink->framebuffers[0]);
++	spin_unlock(&eink->lock);
++
++	w = eink->panel->sources / 4 + eink->panel->h_lead + eink->panel->h_trail;
++	h = eink->panel->gates + eink->panel->v_extra;
++
++	// Setup DEBE
++
++	if (!test_bit(EINK_BE_SETUP, eink->flags)) {
++	regmap_write(be, SUN4I_BACKEND_DISSIZE_REG,
++		     SUN4I_BACKEND_DISSIZE(w, h));
++	regmap_write(be, SUN4I_BACKEND_LAYSIZE_REG(0),
++		     SUN4I_BACKEND_LAYSIZE(w, h));
++	regmap_write(be, SUN4I_BACKEND_LAYCOOR_REG(0),
++		     SUN4I_BACKEND_LAYCOOR(0, 0));
++	regmap_write(be, SUN4I_BACKEND_LAYLINEWIDTH_REG(0),
++		     w * 4 * 8); /* input format has 4 bytes per pixel */
++
++	lo_paddr = eink->ctlstream_paddr << 3;
++	hi_paddr = eink->ctlstream_paddr >> 29;
++	regmap_write(be, SUN4I_BACKEND_LAYFB_L32ADD_REG(0), lo_paddr);
++	regmap_update_bits(be, SUN4I_BACKEND_LAYFB_H4ADD_REG,
++			   SUN4I_BACKEND_LAYFB_H4ADD_MSK(0),
++			   SUN4I_BACKEND_LAYFB_H4ADD(0, hi_paddr));
++
++	regmap_write(be, SUN4I_BACKEND_ATTCTL_REG0(0),
++		     SUN4I_BACKEND_ATTCTL_REG0_LAY_WORKMOD(0) |
++		     SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(0) |
++		     SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(3));
++
++	regmap_write(be, SUN4I_BACKEND_ATTCTL_REG1(0),
++		     SUN4I_BACKEND_LAY_FBFMT_XRGB8888);
++
++	/* load BE buffers */
++	regmap_write(be, SUN4I_BACKEND_REGBUFFCTL_REG,
++		     SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
++		     SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
++	set_bit(EINK_BE_SETUP, eink->flags);
++	}
++
++	// Setup TCON/TCON0
++	//
++	// TCON0 timings, allwinner style:
++	//
++	// ht - horizontal total time
++	//   - total number of clock cycles in a row
++	// hbp - horizontal back porch
++	//   - number of dclk cycles between start of hsync and data
++	// vt - vertical total time
++	//   - number of rows in two frames
++	// vbp - vertical back porch
++	//   - number of rows between vsync start and a valid data line
++	// hspw
++	//   - width of hsync signal (in # of dclk cycles)
++	// vspw
++	//   - width of vsync signal (in # of rows)
++	//
++	// Notes:
++	// hbp(aw)=hbp(panel)+hspw(panel) (same for vbp)
++
++	/* Enable tcon module */
++	regmap_write(tcon, SUN4I_TCON_GCTL_REG,
++		     SUN4I_TCON_GCTL_TCON_ENABLE |
++		     SUN4I_TCON_GCTL_IOMAP_TCON0);
++
++	/* Set the resolution */
++	regmap_write(tcon, SUN4I_TCON0_BASIC0_REG,
++		     SUN4I_TCON0_BASIC0_X(w) |
++		     SUN4I_TCON0_BASIC0_Y(h));
++
++	/* Set horizontal display timings */
++	regmap_write(tcon, SUN4I_TCON0_BASIC1_REG,
++		     SUN4I_TCON0_BASIC1_H_TOTAL(w + hbp + 2) |
++		     SUN4I_TCON0_BASIC1_H_BACKPORCH(hbp));
++
++	/* Set vertical display timings */
++	regmap_write(tcon, SUN4I_TCON0_BASIC2_REG,
++		     SUN4I_TCON0_BASIC2_V_TOTAL((h + vbp + 2) * 2) |
++		     SUN4I_TCON0_BASIC2_V_BACKPORCH(vbp));
++
++	/* Set Hsync and Vsync length */
++	regmap_write(tcon, SUN4I_TCON0_BASIC3_REG,
++		     SUN4I_TCON0_BASIC3_V_SYNC(1) |
++		     SUN4I_TCON0_BASIC3_H_SYNC(1));
++
++        /* Setup output mode/pins */
++	regmap_write(tcon, SUN4I_TCON0_HV_IF_REG, 0); // 24bit parallel mode
++        regmap_write(tcon, SUN4I_TCON0_IO_POL_REG, SUN4I_TCON0_IO_POL_DCLK_NEGATIVE);
++        regmap_write(tcon, SUN4I_TCON0_IO_TRI_REG, 0);
++
++	ret = pinctrl_select_state(eink->pinctrl, eink->pinctrl_active);
++	if (ret) {
++		dev_err(eink->dev, "can't switch to active pinctrl state (%d)",
++			ret);
++	}
++
++	set_bit(EINK_WAITING_INT, eink->flags);
++
++	/* Interrupt after h lines */
++	regmap_write(tcon, SUN4I_TCON_GINT0_REG, 0);
++        regmap_write(tcon, SUN4I_TCON_GINT1_REG, (h + vbp + 2) << 16);
++	//regmap_write(tcon, SUN4I_TCON_GINT0_REG,
++		     //SUN4I_TCON_GINT0_VBLANK_ENABLE(0));
++	regmap_write(tcon, SUN4I_TCON_GINT0_REG,
++		     SUN4I_TCON_GINT0_LINE_ENABLE(0));
++
++	/* Configure and enable the dot clock */
++	regmap_write(tcon, SUN4I_TCON0_DCLK_REG,
++		     BIT(SUN4I_TCON0_DCLK_GATE_BIT) |
++		     (ddiv << SUN4I_TCON0_DCLK_DIV_SHIFT));
++
++	/* Enable tcon 0, set clk delay */
++	regmap_write(tcon, SUN4I_TCON0_CTL_REG,
++		     SUN4I_TCON0_CTL_CLK_DELAY(3)); // up to 30
++
++	regmap_update_bits(tcon, SUN4I_TCON0_CTL_REG,
++			   SUN4I_TCON0_CTL_TCON_ENABLE,
++			   SUN4I_TCON0_CTL_TCON_ENABLE);
++
++	ret = wait_event_timeout(eink->waitqueue,
++				 !test_bit(EINK_WAITING_INT, eink->flags),
++				 msecs_to_jiffies(100));
++	if (ret == 0)
++		dev_warn(eink->dev, "Timeout waiting for TCON transfer\n");
++
++	// stop everything, cleanup
++        //regmap_write(tcon, SUN4I_TCON0_DCLK_REG, 0);
++	regmap_update_bits(tcon, SUN4I_TCON0_CTL_REG,
++			   SUN4I_TCON0_CTL_TCON_ENABLE,
++			   0);
++        //regmap_write(tcon, SUN4I_TCON_GCTL_REG, 0);
++        regmap_write(tcon, SUN4I_TCON_GINT0_REG, 0);
++        regmap_write(tcon, SUN4I_TCON_GINT1_REG, 0);
++
++	ret = pinctrl_select_state(eink->pinctrl, eink->pinctrl_idle);
++	if (ret) {
++		dev_err(eink->dev, "can't switch to idle pinctrl state (%d)",
++			ret);
++	}
++
++        regmap_write(tcon, SUN4I_TCON0_IO_TRI_REG, ~0);
++
++	return ret;
++}
++
++static void eink_supply_powerdown_timer(struct timer_list *t)
++{
++	struct eink_dev *eink = from_timer(eink, t, powerdown_timer);
++
++	//dev_info(eink->dev, "powering down");
++
++	spin_lock(&eink->lock);
++	eink->last_request = EINK_REQ_POWERDOWN;
++	spin_unlock(&eink->lock);
++
++	queue_work(eink->wq, &eink->work);
++}
++
++static void eink_work_handler(struct work_struct *work)
++{
++	struct eink_dev *eink = container_of(work, struct eink_dev, work);
++	int last_request;
++
++	spin_lock(&eink->lock);
++	last_request = eink->last_request;
++	eink->last_request = 0;
++	spin_unlock(&eink->lock);
++
++	if (last_request == EINK_REQ_UPDATE) {
++		eink_update(eink);
++	} else if (last_request == EINK_REQ_POWERDOWN) {
++		eink_set_power(eink, 0);
++	}
++
++	clear_bit(EINK_WORKING, eink->flags);
++	wake_up(&eink->waitqueue);
++}
++
++static ssize_t eink_read(struct file *fp, char __user *buf, size_t len,
++			 loff_t *off)
++{
++	struct eink_dev* eink = fp->private_data;
++	int ret, fb_size;
++
++	fb_size = eink->panel->sources / 4 * eink->panel->gates;
++	if (len != fb_size)
++		return -EINVAL;
++
++	spin_lock(&eink->lock);
++	if (copy_to_user(buf, eink->framebuffers[0], fb_size))
++		ret = -EFAULT;
++	else
++		ret = fb_size;
++	spin_unlock(&eink->lock);
++
++	return ret;
++}
++
++static ssize_t eink_write(struct file *fp, const char __user *buf,
++			  size_t len, loff_t *off)
++{
++	struct eink_dev* eink = fp->private_data;
++	int non_blocking = fp->f_flags & O_NONBLOCK;
++	int ret, fb_size;
++
++	fb_size = eink->panel->sources / 4 * eink->panel->gates;
++	if (len != fb_size)
++		return -EINVAL;
++
++	if (test_and_set_bit(EINK_WORKING, eink->flags))
++		return -EBUSY;
++
++	spin_lock(&eink->lock);
++	ret = copy_from_user(eink->framebuffers[0], buf, len);
++	if (ret) {
++		clear_bit(EINK_WORKING, eink->flags);
++		spin_unlock(&eink->lock);
++		return -EFAULT;
++	}
++
++	eink->last_request = EINK_REQ_UPDATE;
++	spin_unlock(&eink->lock);
++
++	queue_work(eink->wq, &eink->work);
++
++	// first handle non-blocking path
++	if (non_blocking && test_bit(EINK_WORKING, eink->flags))
++		return -EWOULDBLOCK;
++
++	// wait for availability of wakeup
++	wait_event(eink->waitqueue,
++		   !test_bit(EINK_WORKING, eink->flags));
++
++	//u64 ts = ktime_get_boottime_ns();
++	//print_time(eink->dev, ktime_get_boottime() - ts, "one frame");
++
++	return len;
++}
++
++static unsigned int eink_poll(struct file *fp, poll_table *wait)
++{
++	struct eink_dev* eink = fp->private_data;
++	int ret = 0;
++
++	poll_wait(fp, &eink->waitqueue, wait);
++
++	if (!test_bit(EINK_WORKING, eink->flags))
++		ret |= POLLIN | POLLRDNORM;
++
++	return ret;
++}
++
++static long eink_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
++{
++	struct eink_dev* eink = fp->private_data;
++	unsigned long flags;
++	int ret = -ENOSYS;
++	//void __user *parg = (void __user *)arg;
++
++	if (!capable(CAP_SYS_ADMIN))
++		return -EACCES;
++
++	if (test_and_set_bit(EINK_WORKING, eink->flags))
++		return -EBUSY;
++
++	spin_lock_irqsave(&eink->lock, flags);
++
++	switch (cmd) {
++	case EINK_IOCTL_UPDATE:
++		eink->last_request = EINK_REQ_UPDATE;
++		ret = 0;
++		break;
++		/*
++	case EINK_IOCTL_BLANK:
++		eink->last_request = EINK_REQ_BLANK;
++		ret = 0;
++		break;
++	case EINK_IOCTL_STATUS:
++		if (copy_to_user(parg, &powered, sizeof powered))
++			return -EFAULT;
++
++		return 0;
++		*/
++	}
++
++	spin_unlock_irqrestore(&eink->lock, flags);
++
++	if (ret == 0)
++		queue_work(eink->wq, &eink->work);
++	else
++		clear_bit(EINK_WORKING, eink->flags);
++
++	return ret;
++}
++
++static int eink_release(struct inode *ip, struct file *fp)
++{
++	struct eink_dev* eink = fp->private_data;
++
++	clear_bit(EINK_OPEN, eink->flags);
++	return 0;
++}
++
++static int eink_open(struct inode *ip, struct file *fp)
++{
++	struct eink_dev* eink = container_of(ip->i_cdev, struct eink_dev, cdev);
++
++	if (test_and_set_bit(EINK_OPEN, eink->flags))
++		return -EBUSY;
++
++	fp->private_data = eink;
++
++	nonseekable_open(ip, fp);
++	return 0;
++}
++
++static const struct file_operations eink_fops = {
++	.owner		= THIS_MODULE,
++	.read		= eink_read,
++	.write		= eink_write,
++	.poll		= eink_poll,
++	.unlocked_ioctl	= eink_ioctl,
++	.open		= eink_open,
++	.release	= eink_release,
++	.llseek		= noop_llseek,
++};
++
++static struct regmap_config eink_tcon_regmap_config = {
++	.name		= "tcon",
++        .reg_bits       = 32,
++        .val_bits       = 32,
++        .reg_stride     = 4,
++        .max_register   = 0x7ff,
++	.cache_type     = REGCACHE_NONE,
++};
++
++static struct regmap_config eink_be_regmap_config = {
++	.name		= "be",
++        .reg_bits       = 32,
++        .val_bits       = 32,
++        .reg_stride     = 4,
++        .max_register   = 0x57ff,
++	.cache_type     = REGCACHE_NONE,
++};
++
++static struct class* eink_class;
++
++static irqreturn_t eink_tcon0_irq_handler(int irq, void *private)
++{
++        struct eink_dev *eink = private;
++	struct regmap *tcon = eink->tcon_regs;
++        unsigned int status;
++
++        regmap_read(eink->tcon_regs, SUN4I_TCON_GINT0_REG, &status);
++
++        if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
++			SUN4I_TCON_GINT0_LINE_INT(0))))
++                return IRQ_NONE;
++
++	// stop everything
++        //regmap_write(tcon, SUN4I_TCON_GCTL_REG, 0);
++
++	regmap_update_bits(tcon, SUN4I_TCON0_CTL_REG,
++			   SUN4I_TCON0_CTL_TCON_ENABLE,
++			   0);
++
++        regmap_write(tcon, SUN4I_TCON_GINT0_REG, 0);
++        regmap_write(tcon, SUN4I_TCON_GINT1_REG, 0);
++        //regmap_write(tcon, SUN4I_TCON0_DCLK_REG, 0);
++        //regmap_write(tcon, SUN4I_TCON0_IO_TRI_REG, ~0);
++
++	clear_bit(EINK_WAITING_INT, eink->flags);
++	wake_up(&eink->waitqueue);
++
++	/*
++        regmap_update_bits(eink->tcon_regs, SUN4I_TCON_GINT0_REG,
++                           SUN4I_TCON_GINT0_VBLANK_INT(0) |
++                           SUN4I_TCON_GINT0_LINE_INT(0),
++                           0);
++          */
++
++        return IRQ_HANDLED;
++}
++
++static const struct clk_bulk_data eink_clocks[] = {
++	{ .id = "tcon_bus" },
++	{ .id = "tcon_mod" },
++	{ .id = "be_bus" },
++	{ .id = "be_mod" },
++	{ .id = "be_ram" },
++};
++
++static int eink_probe(struct platform_device *pdev)
++{
++	struct eink_dev *eink;
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct device *sdev;
++	const char* cdev_name = NULL;
++        void __iomem *tcon_regs, *be_regs;
++	int ret, i, fb_size, cs_size;
++
++	eink = devm_kzalloc(dev, sizeof(*eink), GFP_KERNEL);
++	if (!eink)
++		return -ENOMEM;
++
++	eink->panel = &eink_ed060xd4_panel;
++	fb_size = eink->panel->sources / 4 * eink->panel->gates;
++
++	// we shift four 2-bit source values per clock cycle
++	cs_size = ((eink->panel->sources / 4 + eink->panel->h_lead + eink->panel->h_trail) *
++		   (eink->panel->gates + eink->panel->v_extra)) * 4;
++
++	eink->framebuffers[0] = devm_kzalloc(dev, fb_size, GFP_KERNEL);
++	if (!eink->framebuffers[0])
++		return -ENOMEM;
++
++	eink->framebuffers[1] = devm_kzalloc(dev, fb_size, GFP_KERNEL);
++	if (!eink->framebuffers[1])
++		return -ENOMEM;
++
++	eink->dev = dev;
++	platform_set_drvdata(pdev, eink);
++	init_waitqueue_head(&eink->waitqueue);
++	spin_lock_init(&eink->lock);
++	INIT_WORK(&eink->work, &eink_work_handler);
++	timer_setup(&eink->powerdown_timer, eink_supply_powerdown_timer, 0);
++
++	ret = of_dma_configure(dev, dev->of_node, true);
++	if (ret) {
++		dev_err(dev, "failed to configure dma (%d)\n", ret);
++		return ret;
++	}
++
++	tcon_regs = devm_platform_ioremap_resource(pdev, 0);
++        if (IS_ERR(tcon_regs))
++                return PTR_ERR(tcon_regs);
++
++	be_regs = devm_platform_ioremap_resource(pdev, 1);
++        if (IS_ERR(be_regs))
++                return PTR_ERR(be_regs);
++
++	eink->pinctrl = devm_pinctrl_get(dev);
++	if (IS_ERR(eink->pinctrl)) {
++		ret = PTR_ERR(eink->pinctrl);
++		dev_err(dev, "can't get pinctrl (%d)\n", ret);
++		return ret;
++	}
++
++	eink->pinctrl_active = pinctrl_lookup_state(eink->pinctrl, "active");
++	if (!eink->pinctrl_active) {
++		dev_err(dev, "missing active pinctrl state");
++		return -EINVAL;
++	}
++
++	eink->pinctrl_idle = pinctrl_lookup_state(eink->pinctrl, "idle");
++	if (!eink->pinctrl_idle) {
++		dev_err(dev, "missing idle pinctrl state");
++		return -EINVAL;
++	}
++
++	ret = pinctrl_select_state(eink->pinctrl, eink->pinctrl_idle);
++	if (ret) {
++		dev_err(eink->dev, "can't switch to idle pinctrl state (%d)",
++			ret);
++		return ret;
++	}
++
++	eink->gpios = devm_gpiod_get_array(dev, "all", GPIOD_OUT_LOW);
++	if (IS_ERR(eink->gpios)) {
++		ret = PTR_ERR(eink->gpios);
++		dev_err(dev, "can't get all gpios (%d)\n", ret);
++		return ret;
++	}
++
++	eink->irq = platform_get_irq(pdev, 0);
++	if (eink->irq < 0) {
++                dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
++		return eink->irq;
++	}
++
++	ret = of_property_read_string(np, "control-device-name", &cdev_name);
++	if (ret) {
++		dev_err(dev, "char-device-name is not configured (%d)\n", ret);
++		return ret;
++	}
++
++	eink->panel_supply = devm_regulator_get(dev, "panel");
++	if (IS_ERR(eink->panel_supply)) {
++		ret = PTR_ERR(eink->panel_supply);
++		dev_err(dev, "can't get panel supply (%d)\n", ret);
++		return ret;
++	}
++
++	eink->clks = devm_kmemdup(dev, eink_clocks, sizeof(eink_clocks),
++				  GFP_KERNEL);
++	if (!eink->clks)
++		return -ENOMEM;
++
++	eink->num_clks = ARRAY_SIZE(eink_clocks);
++	ret = devm_clk_bulk_get(dev, eink->num_clks, eink->clks);
++	if (ret)
++		return ret;
++
++        eink->rstc = devm_reset_control_array_get(dev, false, false);
++        if (IS_ERR(eink->rstc)) {
++		ret = PTR_ERR(eink->rstc);
++                dev_err(dev, "Couldn't get our reset line (%d)\n", ret);
++                return ret;
++        }
++
++        eink->tcon_regs = devm_regmap_init_mmio(dev, tcon_regs, &eink_tcon_regmap_config);
++        if (IS_ERR(eink->tcon_regs)) {
++		ret = PTR_ERR(eink->tcon_regs);
++                dev_err(dev, "Couldn't create the TCON regmap (%d)\n", ret);
++                return ret;
++        }
++
++        eink->be_regs = devm_regmap_init_mmio(dev, be_regs, &eink_be_regmap_config);
++        if (IS_ERR(eink->be_regs)) {
++		ret = PTR_ERR(eink->be_regs);
++                dev_err(dev, "Couldn't create the BE regmap (%d)\n", ret);
++                return ret;
++        }
++
++	// init the actual hardware
++        ret = reset_control_deassert(eink->rstc);
++        if (ret) {
++                dev_err(dev, "Couldn't deassert our reset line (%d)\n", ret);
++                return ret;
++        }
++
++	// possible to set 27-381MHz in 3MHz steps
++	ret = clk_set_rate(eink->clks[1].clk, 120000000);
++	if (ret) {
++                dev_err(dev, "Couldn't set tcon0 rate to  (%d)\n", ret);
++                goto err_reset;
++	}
++
++	ret = clk_bulk_prepare_enable(eink->num_clks, eink->clks);
++	if (ret) {
++                dev_err(dev, "Couldn't enable clocks (%d)\n", ret);
++                goto err_reset;
++	}
++
++	/* Clear DEBE registers */
++	for (i = 0x800; i < 0x1000; i += 4)
++		regmap_write(eink->be_regs, i, 0);
++
++	/* Disable registers autoloading */
++	regmap_write(eink->be_regs,
++		     SUN4I_BACKEND_REGBUFFCTL_REG,
++		     SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
++
++	regmap_write(eink->be_regs,
++		     SUN4I_BACKEND_MODCTL_REG,
++		     SUN4I_BACKEND_MODCTL_START_CTL);
++
++	/* Enable the backend */
++	regmap_write(eink->be_regs,
++		     SUN4I_BACKEND_MODCTL_REG,
++		     SUN4I_BACKEND_MODCTL_DEBE_EN |
++		     SUN4I_BACKEND_MODCTL_START_CTL |
++		     SUN4I_BACKEND_MODCTL_OUT_LCD0 |
++		     SUN4I_BACKEND_MODCTL_LAY_EN(0));
++
++        /* Make sure the TCON is disabled and all IRQs are off */
++        regmap_write(eink->tcon_regs, SUN4I_TCON_GCTL_REG, 0);
++        regmap_write(eink->tcon_regs, SUN4I_TCON_GINT0_REG, 0);
++        regmap_write(eink->tcon_regs, SUN4I_TCON_GINT1_REG, 0);
++
++        /* Disable IO lines and set them to tristate */
++        regmap_write(eink->tcon_regs, SUN4I_TCON0_IO_TRI_REG, ~0);
++
++        ret = devm_request_irq(dev, eink->irq, eink_tcon0_irq_handler, 0,
++                               dev_name(dev), eink);
++        if (ret) {
++                dev_err(dev, "Couldn't request the IRQ\n");
++                goto err_disable_hw;
++        }
++
++	// create char device
++	ret = alloc_chrdev_region(&eink->major, 0, 1, "eink");
++	if (ret) {
++		dev_err(dev, "can't allocate chrdev region");
++		goto err_disable_hw;
++	}
++
++	cdev_init(&eink->cdev, &eink_fops);
++	eink->cdev.owner = THIS_MODULE;
++	ret = cdev_add(&eink->cdev, eink->major, 1);
++	if (ret) {
++		dev_err(dev, "can't add cdev");
++		goto err_unreg_chrev_region;
++	}
++
++	sdev = device_create(eink_class, dev, eink->major, eink, cdev_name);
++	if (IS_ERR(sdev)) {
++		ret = PTR_ERR(sdev);
++		goto err_del_cdev;
++	}
++
++	eink->ctlstream_size = round_up(cs_size, PAGE_SIZE);
++	eink->ctlstream = dma_alloc_wc(dev, eink->ctlstream_size,
++				       &eink->ctlstream_paddr,
++				       GFP_KERNEL | __GFP_NOWARN);
++	if (!eink->ctlstream) {
++		ret = -ENOMEM;
++		dev_err(dev, "failed to allocate buffer with size %zu\n",
++			eink->ctlstream_size);
++		goto err_destroy_device;
++	}
++
++	eink_ctlstream_prepare(eink);
++
++	eink->wq = alloc_workqueue("eink", WQ_SYSFS | WQ_HIGHPRI, 0);
++	if (!eink->wq) {
++		ret = -ENOMEM;
++		dev_err(dev, "failed to allocate workqueue\n");
++		goto err_free_dma;
++	}
++
++	dev_info(dev, "eink-panel driver ready!\n");
++	return 0;
++
++err_free_dma:
++	dma_free_wc(eink->dev, eink->ctlstream_size, eink->ctlstream,
++		    eink->ctlstream_paddr);
++err_destroy_device:
++	device_destroy(eink_class, eink->major);
++err_del_cdev:
++	cdev_del(&eink->cdev);
++err_unreg_chrev_region:
++	unregister_chrdev(eink->major, "eink");
++err_disable_hw:
++	clk_bulk_disable_unprepare(eink->num_clks, eink->clks);
++err_reset:
++        reset_control_assert(eink->rstc);
++	cancel_work_sync(&eink->work);
++
++	return ret;
++}
++
++static int eink_remove(struct platform_device *pdev)
++{
++	struct eink_dev *eink = platform_get_drvdata(pdev);
++
++	eink_set_power(eink, 0);
++
++	del_timer_sync(&eink->powerdown_timer);
++	cancel_work_sync(&eink->work);
++	destroy_workqueue(eink->wq);
++
++	dma_free_wc(eink->dev, eink->ctlstream_size, eink->ctlstream,
++		    eink->ctlstream_paddr);
++
++	clk_bulk_disable_unprepare(eink->num_clks, eink->clks);
++        reset_control_assert(eink->rstc);
++
++	device_destroy(eink_class, eink->major);
++	cdev_del(&eink->cdev);
++	unregister_chrdev(eink->major, "eink");
++
++	return 0;
++}
++
++static const struct of_device_id eink_of_match[] = {
++	{ .compatible = "custom,pocketbook-touch-lux-3-tcon0-ed060xd4-display" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, eink_of_match);
++
++static struct platform_driver eink_platform_driver = {
++	.probe = eink_probe,
++	.remove = eink_remove,
++	.driver = {
++		.name = "eink_tcon0",
++		.of_match_table = eink_of_match,
++	},
++};
++
++static int __init eink_driver_init(void)
++{
++	int ret;
++
++	eink_class = class_create("eink-panel");
++
++	ret = platform_driver_register(&eink_platform_driver);
++	if (ret)
++		class_destroy(eink_class);
++
++	return ret;
++}
++
++static void __exit eink_driver_exit(void)
++{
++	platform_driver_unregister(&eink_platform_driver);
++	class_destroy(eink_class);
++}
++
++module_init(eink_driver_init);
++module_exit(eink_driver_exit);
++
++MODULE_VERSION("1.0.0");
++MODULE_DESCRIPTION("eInk display Allwinner TCON0 based bit-banging driver");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch b/patch/kernel/archive/sunxi-6.10/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
new file mode 100644
index 000000000000..1ff14007802f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
@@ -0,0 +1,126 @@
+From 9422b61aa651037602ed5938bc1bb7d0c83796c4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 7 Jun 2021 20:27:07 +0200
+Subject: video: pwm_bl: Allow to change lth_brightness via sysfs
+
+Read minimum duty cycle in % from DT, and allow to change it via
+sysfs.
+
+Minimum brightness calibration instructions:
+
+  echo 1 > /sys/class/backlight/backlight/brightness
+
+  echo 1 > /sys/class/backlight/backlight/device/lth_brightness
+  echo 2 > /sys/class/backlight/backlight/device/lth_brightness
+  echo 3 > /sys/class/backlight/backlight/device/lth_brightness
+
+  .... increase values until you like the minimum brightness
+
+Then make sure to restore this value after each boot by writing it to
+/sys/class/backlight/backlight/device/lth_brightness
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/video/backlight/pwm_bl.c | 72 +++++++++++++++++++++++++++++++-
+ 1 file changed, 70 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
+index c1195299a214..16a583ce8841 100644
+--- a/drivers/video/backlight/pwm_bl.c
++++ b/drivers/video/backlight/pwm_bl.c
+@@ -437,6 +437,61 @@ static int pwm_backlight_initial_power_state(const struct pwm_bl_data *pb)
+ 	return active ? FB_BLANK_UNBLANK: FB_BLANK_POWERDOWN;
+ }
+ 
++static ssize_t lth_brightness_show(struct device *dev,
++				   struct device_attribute *attr, char *buf)
++{
++	struct backlight_device *bl = platform_get_drvdata(to_platform_device(dev));
++	struct pwm_bl_data *pb = bl ? bl_get_data(bl) : NULL;
++	struct pwm_state state;
++	unsigned val;
++
++	if (!pb)
++		return -EBUSY;
++
++	pwm_get_state(pb->pwm, &state);
++	val = div_u64(100 * pb->lth_brightness, state.period);
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n", val);
++}
++
++static ssize_t lth_brightness_store(struct device *dev,
++				    struct device_attribute *attr,
++				    const char *buf, size_t len)
++{
++	struct backlight_device *bl = platform_get_drvdata(to_platform_device(dev));
++	struct pwm_bl_data *pb = bl ? bl_get_data(bl) : NULL;
++	struct pwm_state state;
++	unsigned val;
++	int ret;
++
++	if (!pb)
++		return -EBUSY;
++
++	ret = kstrtouint(buf, 10, &val);
++	if (ret)
++		return ret;
++
++        if (val > 100)
++		val = 100;
++
++	pwm_get_state(pb->pwm, &state);
++	pb->lth_brightness = div_u64(val * state.period, 100);
++	pwm_backlight_update_status(bl);
++
++	return len;
++}
++
++static DEVICE_ATTR_RW(lth_brightness);
++
++static struct attribute *pwm_bl_attrs[] = {
++	&dev_attr_lth_brightness.attr,
++	NULL,
++};
++
++static const struct attribute_group pwm_bl_group = {
++	.attrs = pwm_bl_attrs,
++};
++
+ static int pwm_backlight_probe(struct platform_device *pdev)
+ {
+ 	struct platform_pwm_backlight_data *data = dev_get_platdata(&pdev->dev);
+@@ -445,6 +500,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	struct backlight_device *bl;
+ 	struct pwm_bl_data *pb;
+ 	struct pwm_state state, state_real;
++	u32 lth_brightness;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -584,8 +640,20 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 		pb->scale = data->max_brightness;
+ 	}
+ 
+-	pb->lth_brightness = data->lth_brightness * (div_u64(state.period,
+-				pb->scale));
++	pb->lth_brightness = div_u64(data->lth_brightness * state.period, pb->scale);
++
++	ret = of_property_read_u32(pdev->dev.of_node, "lth-brightness",
++				   &lth_brightness);
++	if (ret == 0) {
++		if (lth_brightness > 100)
++			lth_brightness = 100;
++
++		pb->lth_brightness = div_u64(lth_brightness * state.period, 100);
++	}
++
++	ret = devm_device_add_group(&pdev->dev, &pwm_bl_group);
++	if (ret)
++		goto err_alloc;
+ 
+ 	props.type = BACKLIGHT_RAW;
+ 	props.max_brightness = data->max_brightness;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.10/series.conf b/patch/kernel/archive/sunxi-6.10/series.conf
new file mode 100644
index 000000000000..46a550d3cfe0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/series.conf
@@ -0,0 +1,263 @@
+#
+#	This file is made manually by simply copying text
+#	from the target series.* files.
+#	Add (-) at the beginning of the line if the patch should not be applied.
+#	At the same time, the patch does not need to be deleted.
+#
+	patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
+	patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
+	patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
+	patches.megous/media-ov5640-set-default-ae-target-lower.patch
+	patches.megous/media-ov5640-Improve-error-reporting.patch
+	patches.megous/media-ov5640-Implement-autofocus.patch
+	patches.megous/media-ov5640-Improve-firmware-load-time.patch
+	patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
+	patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
+	patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
+	patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
+	patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
+	patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
+	patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
+	patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
+	patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
+	patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
+	patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
+	patches.megous/mmc-add-delay-after-power-class-selection.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
+	patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
+	patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
+	patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
+	patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
+	patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
+	patches.megous/ARM-dts-axp813-Add-charger-LED.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
+	patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
+	patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/hm5065-yaml-bindings-wip.patch
+	patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
+	patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
+	patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
+	patches.megous/media-gc2145-Disable-debug-output.patch
+	patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
+	patches.megous/media-gc2145-implement-system-suspend.patch
+	patches.megous/media-gc2145-fix-white-balance-colors.patch
+	patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
+	patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
+	patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
+	patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
+	patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
+	patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
+	patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
+	patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
+	patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
+	patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
+	patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
+	patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
+	patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
+	patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
+	patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
+	patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
+	patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
+	patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
+	patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch
+	patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch
+	patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch
+	patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch
+	patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch
+	patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch
+	patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch
+	patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch
+	patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch
+	patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch
+	patches.megous/input-cyttsp4-Fix-warnings.patch
+	patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch
+	patches.megous/input-cyttsp4-Fix-probe-oops.patch
+	patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch
+	patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch
+	patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch
+	patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch
+	patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch
+	patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch
+	patches.megous/ARM-dts-sun5i-Add-soc-handle.patch
+	patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch
+	patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-acceleromet.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-AF8133J-to-PinePhone.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-PinePhone-m.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
+	patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch
+	patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
+	patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
+	patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
+	patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
+	patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
+	patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch
+	patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
+	patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
+	patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
+	patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
+	patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
+	patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
+	patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
+	patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
+	patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
+	patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
+	patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
+	patches.megous/clk-Implement-protected-clocks-for-all-OF-clock-providers.patch
+	patches.megous/Revert-clk-qcom-Support-protected-clocks-property.patch
+	patches.megous/ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch
+	patches.megous/arm64-dts-allwinner-a64-Protect-SCP-clocks.patch
+	patches.megous/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
+	patches.megous/bus-sunxi-rsb-Always-check-register-address-validity.patch
+	patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
+	patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
+	patches.megous/arm64-dts-allwinner-a64-Add-SCPI-protocol.patch
+	patches.megous/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
+	patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
+	patches.megous/misc-modem-power-Power-manager-for-modems.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-sun50i-a64-Add-missing-trip-points-for-GPU.patch
+	patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
+	patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch
+	patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch
+	patches.megous/spi-fixes.patch
+	patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
+	patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
+	patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
+	patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
+	patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
+	patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
+	patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
+	patches.megous/Fix-for-usb-gadget-on-PP.patch
+	patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
+	patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
+	patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
+	patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
+	patches.megous/Fix-intptr_t-typedef.patch
+	patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
+	patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
+	patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
+	patches.megous/media-rkisp1-Adapt-to-different-SoCs-having-different-size-limi.patch
+	patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
+	patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch
+	patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Restore-DPHY-config-on-resume.patch
+	patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
+	patches.megous/drm-sun4i-Unify-sun8i_-_layer-structs.patch
+	patches.megous/drm-sun4i-Add-more-parameters-to-sunxi_engine-commit-callback.patch
+	patches.megous/drm-sun4i-Fix-layer-zpos-change-atomic-modesetting.patch
+	patches.megous/drm-sun4i-drm-Change-update_bits-to-write.patch
+	patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
+	patches.megous/drm-sun4i-Implement-gamma-correction.patch
+	patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
+	patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
+	patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
+	patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
+	patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
+	patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
+	patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
+	patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
+	patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
+	patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
+	patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
+	patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
+	patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch
+	patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
+	patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
+	patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
+	patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
+	patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
+	patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
+	patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
+	patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
+	patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
+	patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
+	patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
+	patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
+	patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
+	patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
+	patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
+	patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
+	patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
+	patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
+	patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
+	patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
+	patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
+	patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
+	patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
+	patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
+	patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
+	patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
+	patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
+	patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
+	patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
+	patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
+	patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
+	patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
+	patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
+	patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
+	patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
+	patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
+	patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
+	patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
+	patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
+	patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
+	patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
+	patches.megous/usb-typec-tcpm-Improve-logs.patch
+	patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
+	patches.megous/Add-support-for-my-private-Sapomat-device.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
+	patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
+-	patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
+	patches.megous/Defconfigs-for-all-my-devices.patch
+	patches.megous/Update-defconfigs.patch
diff --git a/patch/kernel/archive/sunxi-6.10/series.megous b/patch/kernel/archive/sunxi-6.10/series.megous
new file mode 100644
index 000000000000..867f2197c9d6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.10/series.megous
@@ -0,0 +1,262 @@
+#
+#	Automatically generated by the script mk_format_patch
+#
+#	git@github.com:The-going/linux-sf.git
+#
+	patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
+	patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
+	patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
+	patches.megous/media-ov5640-set-default-ae-target-lower.patch
+	patches.megous/media-ov5640-Improve-error-reporting.patch
+	patches.megous/media-ov5640-Implement-autofocus.patch
+	patches.megous/media-ov5640-Improve-firmware-load-time.patch
+	patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
+	patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
+	patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
+	patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
+	patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
+	patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
+	patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
+	patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
+	patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
+	patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
+	patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
+	patches.megous/mmc-add-delay-after-power-class-selection.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
+	patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
+	patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
+	patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
+	patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
+	patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
+	patches.megous/ARM-dts-axp813-Add-charger-LED.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
+	patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
+	patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/hm5065-yaml-bindings-wip.patch
+	patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
+	patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
+	patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
+	patches.megous/media-gc2145-Disable-debug-output.patch
+	patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
+	patches.megous/media-gc2145-implement-system-suspend.patch
+	patches.megous/media-gc2145-fix-white-balance-colors.patch
+	patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
+	patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
+	patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
+	patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
+	patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
+	patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
+	patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
+	patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
+	patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
+	patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
+	patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
+	patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
+	patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
+	patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
+	patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
+	patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
+	patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
+	patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
+	patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch
+	patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch
+	patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch
+	patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch
+	patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch
+	patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch
+	patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch
+	patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch
+	patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch
+	patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch
+	patches.megous/input-cyttsp4-Fix-warnings.patch
+	patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch
+	patches.megous/input-cyttsp4-Fix-probe-oops.patch
+	patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch
+	patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch
+	patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch
+	patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch
+	patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch
+	patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch
+	patches.megous/ARM-dts-sun5i-Add-soc-handle.patch
+	patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch
+	patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-acceleromet.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-AF8133J-to-PinePhone.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-PinePhone-m.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
+	patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch
+	patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
+	patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
+	patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
+	patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
+	patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
+	patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch
+	patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
+	patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
+	patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
+	patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
+	patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
+	patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
+	patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
+	patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
+	patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
+	patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
+	patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
+	patches.megous/clk-Implement-protected-clocks-for-all-OF-clock-providers.patch
+	patches.megous/Revert-clk-qcom-Support-protected-clocks-property.patch
+	patches.megous/ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch
+	patches.megous/arm64-dts-allwinner-a64-Protect-SCP-clocks.patch
+	patches.megous/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
+	patches.megous/bus-sunxi-rsb-Always-check-register-address-validity.patch
+	patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
+	patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
+	patches.megous/arm64-dts-allwinner-a64-Add-SCPI-protocol.patch
+	patches.megous/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
+	patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
+	patches.megous/misc-modem-power-Power-manager-for-modems.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-sun50i-a64-Add-missing-trip-points-for-GPU.patch
+	patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
+	patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch
+	patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch
+	patches.megous/spi-fixes.patch
+	patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
+	patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
+	patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
+	patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
+	patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
+	patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
+	patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
+	patches.megous/Fix-for-usb-gadget-on-PP.patch
+	patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
+	patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
+	patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
+	patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
+	patches.megous/Fix-intptr_t-typedef.patch
+	patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
+	patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
+	patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
+	patches.megous/media-rkisp1-Adapt-to-different-SoCs-having-different-size-limi.patch
+	patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
+	patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch
+	patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Restore-DPHY-config-on-resume.patch
+	patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
+	patches.megous/drm-sun4i-Unify-sun8i_-_layer-structs.patch
+	patches.megous/drm-sun4i-Add-more-parameters-to-sunxi_engine-commit-callback.patch
+	patches.megous/drm-sun4i-Fix-layer-zpos-change-atomic-modesetting.patch
+	patches.megous/drm-sun4i-drm-Change-update_bits-to-write.patch
+	patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
+	patches.megous/drm-sun4i-Implement-gamma-correction.patch
+	patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
+	patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
+	patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
+	patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
+	patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
+	patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
+	patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
+	patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
+	patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
+	patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
+	patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
+	patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
+	patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch
+	patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
+	patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
+	patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
+	patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
+	patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
+	patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
+	patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
+	patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
+	patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
+	patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
+	patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
+	patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
+	patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
+	patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
+	patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
+	patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
+	patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
+	patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
+	patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
+	patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
+	patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
+	patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
+	patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
+	patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
+	patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
+	patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
+	patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
+	patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
+	patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
+	patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
+	patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
+	patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
+	patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
+	patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
+	patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
+	patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
+	patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
+	patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
+	patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
+	patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
+	patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
+	patches.megous/usb-typec-tcpm-Improve-logs.patch
+	patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
+	patches.megous/Add-support-for-my-private-Sapomat-device.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
+	patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
+-	patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
+	patches.megous/Defconfigs-for-all-my-devices.patch
+	patches.megous/Update-defconfigs.patch
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch
new file mode 100644
index 000000000000..055398963704
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch
@@ -0,0 +1,31 @@
+From 7a6264fac2099b181564b09baa283157f19cc069 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Mon, 26 Jun 2023 13:29:46 +0000
+Subject: ARM: dts: sun8i: nanopiduo2: Use key-0 as power button
+
+The onboard button key-0 was not marked as power button. This meant
+that once the board was suspended, there was no way to bring it back
+to life. Mark key-0 as power button so that it can be used to bring
+the board back to life
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+index 343b02b97155..4878d27bab3e 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+@@ -42,8 +42,9 @@ gpio-keys {
+ 
+ 		key-0 {
+ 			label = "k1";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */
++			wakeup-source;
+ 		};
+ 	};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch
new file mode 100644
index 000000000000..8b6b02ca1082
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch
@@ -0,0 +1,31 @@
+From c6de1fe93692bf97c0057346eeadbab3b71d05d3 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Mon, 26 Jun 2023 13:53:14 +0000
+Subject: ARM: dts: sun8i: nanopiduo2: enable ethernet
+
+NanoPi Duo2 has pinout for ethernet. Lets enable the same in dts
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+index 4878d27bab3e..8669fd0879e7 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+@@ -105,6 +105,13 @@ &ehci0 {
+ 	status = "okay";
+ };
+ 
++&emac {
++	phy-handle = <&int_mii_phy>;
++	phy-mode = "mii";
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
+ &mmc0 {
+ 	bus-width = <4>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-FB_TFT-ST7796S-driver.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-FB_TFT-ST7796S-driver.patch
new file mode 100644
index 000000000000..0d69f51cf3c4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-FB_TFT-ST7796S-driver.patch
@@ -0,0 +1,154 @@
+From c8afe85b198d4dc383fe541cb2fb166b7d1132fb Mon Sep 17 00:00:00 2001
+From: Alan <Alan>
+Date: Sat, 20 May 2023 14:33:52 +0800
+Subject: Add: FB_TFT ST7796S driver
+
+---
+ drivers/staging/fbtft/Kconfig      |  10 +++
+ drivers/staging/fbtft/Makefile     |   1 +
+ drivers/staging/fbtft/fb_st7796s.c | 100 +++++++++++++++++++++++++++++
+ 3 files changed, 111 insertions(+)
+ create mode 100644 drivers/staging/fbtft/fb_st7796s.c
+
+diff --git a/drivers/staging/fbtft/Kconfig b/drivers/staging/fbtft/Kconfig
+index 5dda3c65a38e..8e491c9f6c0e 100644
+--- a/drivers/staging/fbtft/Kconfig
++++ b/drivers/staging/fbtft/Kconfig
+@@ -172,6 +172,16 @@ config FB_TFT_ST7789V
+ 
+ 	  Say Y if you have such a display that utilizes this controller.
+ 
++config FB_TFT_ST7796S
++	tristate "FB driver for the ST7796S LCD Controller"
++	depends on FB_TFT
++	help
++	  This enables generic framebuffer support for the Sitronix ST7796S
++	  display controller. The controller is intended for small color
++	  displays with a resolution of up to 480x320 pixels.
++
++	  Say Y if you have such a display that utilizes this controller.
++
+ config FB_TFT_TINYLCD
+ 	tristate "FB driver for tinylcd.com display"
+ 	depends on FB_TFT
+diff --git a/drivers/staging/fbtft/Makefile b/drivers/staging/fbtft/Makefile
+index e9cdf0f0a7da..7b2098b8a1bd 100644
+--- a/drivers/staging/fbtft/Makefile
++++ b/drivers/staging/fbtft/Makefile
+@@ -31,6 +31,7 @@ obj-$(CONFIG_FB_TFT_SSD1331)     += fb_ssd1331.o
+ obj-$(CONFIG_FB_TFT_SSD1351)     += fb_ssd1351.o
+ obj-$(CONFIG_FB_TFT_ST7735R)     += fb_st7735r.o
+ obj-$(CONFIG_FB_TFT_ST7789V)     += fb_st7789v.o
++obj-$(CONFIG_FB_TFT_ST7796S)     += fb_st7796s.o
+ obj-$(CONFIG_FB_TFT_TINYLCD)     += fb_tinylcd.o
+ obj-$(CONFIG_FB_TFT_TLS8204)     += fb_tls8204.o
+ obj-$(CONFIG_FB_TFT_UC1611)      += fb_uc1611.o
+diff --git a/drivers/staging/fbtft/fb_st7796s.c b/drivers/staging/fbtft/fb_st7796s.c
+new file mode 100644
+index 000000000000..cad489cef595
+--- /dev/null
++++ b/drivers/staging/fbtft/fb_st7796s.c
+@@ -0,0 +1,100 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * FB driver for the ST7796S LCD Controller
++ *
++ * Copyright (c) 2023 Alan Ma
++ * Copyright (c) 2014 Petr Olivka
++ * Copyright (c) 2013 Noralf Tronnes
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <video/mipi_display.h>
++
++#include "fbtft.h"
++
++#define DRVNAME	"fb_st7796s"
++#define WIDTH		480
++#define HEIGHT		320
++
++static const s16 default_init_sequence[] = {
++	-1, 0xC0, 0x0C, 0x02,
++	-1, 0xC1, 0x44,
++	-1, 0xC5, 0x00, 0x16, 0x80,
++	-1, 0x36, 0x28,
++	/* Interface Mode Control */
++	-1, 0x3A, 0x55,
++	-1, 0XB0, 0x00,
++	/* Frame rate 70HZ */
++	-1, 0xB1, 0xB0,
++	-1, 0xB4, 0x02,
++	/* RGB/MCU Interface Control */
++	-1, 0xB6, 0x02, 0x02,
++	-1, 0xE9, 0x00,
++	-1, 0XF7, 0xA9, 0x51, 0x2C, 0x82,
++	/* SLP_OUT - Sleep out */
++	-1, MIPI_DCS_EXIT_SLEEP_MODE,
++	-2, 50,
++	/* DISP_ON */
++	-1, MIPI_DCS_SET_DISPLAY_ON,
++	-3
++};
++
++static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
++{
++	write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
++		  xs >> 8, xs & 0xff, xe >> 8, xe & 0xff);
++
++	write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
++		  ys >> 8, ys & 0xff, ye >> 8, ye & 0xff);
++
++	write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
++}
++
++static int set_var(struct fbtft_par *par)
++{
++	switch (par->info->var.rotate) {
++	case 270:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0x80 | (par->bgr << 3));
++		break;
++	case 180:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0xE0 | (par->bgr << 3));
++		break;
++	case 90:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0x40 | (par->bgr << 3));
++		break;
++	default:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0x20 | (par->bgr << 3));
++		break;
++	}
++
++	return 0;
++}
++
++static struct fbtft_display display = {
++	.regwidth = 8,
++	.width = WIDTH,
++	.height = HEIGHT,
++	.init_sequence = default_init_sequence,
++	.fbtftops = {
++		.set_addr_win = set_addr_win,
++		.set_var = set_var,
++	},
++};
++
++FBTFT_REGISTER_DRIVER(DRVNAME, "sitronix,st7796s", &display);
++
++MODULE_ALIAS("spi:" DRVNAME);
++MODULE_ALIAS("platform:" DRVNAME);
++MODULE_ALIAS("spi:st7796s");
++MODULE_ALIAS("platform:st7796s");
++
++MODULE_DESCRIPTION("FB driver for the ST7796S LCD Controller");
++MODULE_AUTHOR("Alan Ma");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch
new file mode 100644
index 000000000000..8f6674e7ab6f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch
@@ -0,0 +1,88 @@
+From 68e3c93f16478ac7a1fe2d64b79c76b96e5782f6 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Tue, 19 Sep 2023 11:06:01 +0000
+Subject: Add wifi nodes for Inovato Quadra
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |  1 +
+ .../allwinner/sun50i-h6-inovato-quadra.dts    | 56 +++++++++++++++++++
+ 2 files changed, 57 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index ad82da8e2aad..8b504ee408e7 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-inovato-quadra.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts
+new file mode 100644
+index 000000000000..551ad69f18a6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts
+@@ -0,0 +1,56 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (c) 2023 Gunjan Gupta <gunjan@armbian.com>
++
++/dts-v1/;
++
++#include "sun50i-h6-tanix.dtsi"
++
++/ {
++	model = "Inovato Quadra";
++	compatible = "oranth,inovato-quadra", "allwinner,sun50i-h6";
++
++	aliases {
++		ethernet1 = &xr819;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			label = "red";
++			gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
++		};
++
++		led-1 {
++			label = "blue";
++			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++			default-state = "on";
++		};
++	};
++};
++
++&i2s1 {
++	status = "okay";
++};
++
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++
++	xr819: sdio_wifi@1 {
++		compatible = "xradio,xr819";
++		interrupt-names = "host-wake";
++		interrupt-parent = <&r_pio>;
++		interrupts = <1 0 IRQ_TYPE_EDGE_RISING>;
++		local-mac-address = [dc 44 6d c0 ff ee];
++		reg = <1>;
++	};
++};
++
++&sound_hdmi {
++	status = "okay";
++};
++
++&wifi_pwrseq {
++	post-power-on-delay-ms = <0xc8>;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch
new file mode 100644
index 000000000000..0500677ac77d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch
@@ -0,0 +1,275 @@
+From 190990bcecd1c3e1fddb09f77c31cfc653c9421f Mon Sep 17 00:00:00 2001
+From: Alan <Alan>
+Date: Sat, 20 May 2023 17:26:21 +0800
+Subject: Add: ws2812 RGB driver for allwinner H616
+
+---
+ drivers/leds/rgb/Kconfig       |   7 +
+ drivers/leds/rgb/Makefile      |   1 +
+ drivers/leds/rgb/leds-ws2812.c | 229 +++++++++++++++++++++++++++++++++
+ 3 files changed, 237 insertions(+)
+ create mode 100644 drivers/leds/rgb/leds-ws2812.c
+
+diff --git a/drivers/leds/rgb/Kconfig b/drivers/leds/rgb/Kconfig
+index 183bccc06cf3..855cf847ff93 100644
+--- a/drivers/leds/rgb/Kconfig
++++ b/drivers/leds/rgb/Kconfig
+@@ -52,3 +52,10 @@ config LEDS_MT6370_RGB
+ 	  will be called "leds-mt6370-rgb".
+ 
+ endif # LEDS_CLASS_MULTICOLOR
++
++config LEDS_WS2812
++	tristate "WS2812 RGB support for allwinner H616"
++	depends on PINCTRL_SUN50I_H616
++
++	help
++	  Say Y here if you want to use the WS2812.
+\ No newline at end of file
+diff --git a/drivers/leds/rgb/Makefile b/drivers/leds/rgb/Makefile
+index c11cc56384e7..4a01f721c11a 100644
+--- a/drivers/leds/rgb/Makefile
++++ b/drivers/leds/rgb/Makefile
+@@ -4,3 +4,4 @@ obj-$(CONFIG_LEDS_GROUP_MULTICOLOR)	+= leds-group-multicolor.o
+ obj-$(CONFIG_LEDS_PWM_MULTICOLOR)	+= leds-pwm-multicolor.o
+ obj-$(CONFIG_LEDS_QCOM_LPG)		+= leds-qcom-lpg.o
+ obj-$(CONFIG_LEDS_MT6370_RGB)		+= leds-mt6370-rgb.o
++obj-$(CONFIG_LEDS_WS2812)		+= leds-ws2812.o
+diff --git a/drivers/leds/rgb/leds-ws2812.c b/drivers/leds/rgb/leds-ws2812.c
+new file mode 100644
+index 000000000000..1af735ce8e4d
+--- /dev/null
++++ b/drivers/leds/rgb/leds-ws2812.c
+@@ -0,0 +1,229 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
++ */
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/cdev.h>
++#include <linux/fs.h>
++#include <linux/device.h>
++#include <asm/uaccess.h>
++#include <linux/moduleparam.h>
++#include <linux/ioctl.h>
++#include <linux/version.h>
++#include <linux/errno.h>
++#include <linux/rbtree.h>
++#include <linux/ktime.h>
++#include <linux/string.h>
++#include <linux/mutex.h>
++#include <linux/time.h>
++#include <linux/hrtimer.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/input.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++#include <linux/uaccess.h>
++
++#define GPIO_BASE 0x0300B000
++#define GPIO_DAT_OFFSET(n) ((n)*0x0024 + 0x10)
++
++static uint32_t ws2812_pin = 0;
++static volatile uint32_t *ws2812_gpio_port;
++static volatile uint32_t ws2812_gpio_bit;
++static volatile uint32_t ws2812_set_val = 0;
++static volatile uint32_t ws2812_reset_val = 0;
++
++DEFINE_SPINLOCK(lock);
++
++// ws2812 reset
++static void ws2812_rst(void)
++{
++	*ws2812_gpio_port &= ~ws2812_gpio_bit;
++	udelay(200);// RES low voltage time, Above 50µs
++}
++
++static void ws2812_Write_24Bits(uint32_t grb)
++{
++	uint8_t i;
++	for (i = 0; i < 24; i++)
++	{
++		if (grb & 0x800000)
++		{
++			// loop for delay about 700ns
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			// loop for delay about 600ns
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++		}
++		else
++		{
++			// loop for delay about 200ns
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			// loop for delay about 800ns
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++		}
++		grb <<= 1;
++	}
++}
++
++static void ws2812_write_array(uint32_t *rgb, uint32_t cnt)
++{
++	uint32_t i = 0;
++	unsigned long flags;
++
++	for (i = 0; i < cnt; i++)
++	{
++		// rgb -> grb
++		rgb[i] = (((rgb[i] >> 16) & 0xff) << 8) | (((rgb[i] >> 8) & 0xff) << 16) | ((rgb[i]) & 0xff);
++	}
++
++	spin_lock_irqsave(&lock, flags);
++	ws2812_set_val = *ws2812_gpio_port | ws2812_gpio_bit;
++	ws2812_reset_val = *ws2812_gpio_port & (~ws2812_gpio_bit);
++	ws2812_rst();
++	for (i = 0; i < cnt; i++)
++	{
++		ws2812_Write_24Bits(rgb[i]);
++	}
++	spin_unlock_irqrestore(&lock, flags);
++}
++
++ssize_t ws2812_read(struct file *file, char __user *user, size_t bytesize, loff_t *this_loff_t)
++{
++	return 0;
++}
++
++ssize_t ws2812_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos)
++{
++	uint32_t rgb[255];
++	unsigned long ret = 0;
++
++	if (count > 255 * 4) count = 255 * 4;
++	ret = copy_from_user(&rgb[0], user_buf, count);
++	if (ret < 0)
++	{
++		printk("copy_from_user fail!!!\n");
++		return -1;
++	}
++
++	ws2812_write_array((uint32_t *)rgb, count / 4);
++
++	return 0;
++}
++
++int ws2812_open(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++int ws2812_close(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static struct file_operations ws2812_ops = {
++	.owner = THIS_MODULE,
++	.open = ws2812_open,
++	.release = ws2812_close,
++	.write = ws2812_write,
++};
++
++static struct miscdevice ws2812_misc_dev = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name = "ws2812-led",
++	.fops = &ws2812_ops,
++};
++
++static int ws2812_probe(struct platform_device *pdev)
++{
++	int ret;
++	struct device_node *ws2812_gpio_node = pdev->dev.of_node;
++	uint32_t rgb_cnt = 0;
++	uint32_t rgb[255];
++
++	of_property_read_u32(ws2812_gpio_node, "rgb_cnt", &rgb_cnt);
++	if (rgb_cnt > 255)
++		rgb_cnt = 255;
++
++	of_property_read_u32_array(ws2812_gpio_node, "rgb_value", rgb, rgb_cnt);
++	ws2812_pin = of_get_named_gpio(ws2812_gpio_node, "gpios", 0);
++	if (!gpio_is_valid(ws2812_pin))
++	{
++		printk(KERN_ERR "ws2812: gpio: %d is invalid\n", ws2812_pin);
++		return -ENODEV;
++	}
++
++	ws2812_gpio_port = ioremap(GPIO_BASE + GPIO_DAT_OFFSET((ws2812_pin >> 5)), 4);
++	ws2812_gpio_bit = 1 << (ws2812_pin & 0x001F);
++
++	if (gpio_request(ws2812_pin, "ws2812-gpio"))
++	{
++		printk(KERN_ERR "ws2812: gpio %d request failed!\n", ws2812_pin);
++		gpio_free(ws2812_pin);
++		return -ENODEV;
++	}
++	gpio_direction_output(ws2812_pin, 0);
++
++	ret = misc_register(&ws2812_misc_dev);
++	msleep(50);
++
++	ws2812_write_array(rgb, rgb_cnt);
++
++	return 0;
++}
++
++static int ws2812_remove(struct platform_device *pdev)
++{
++	misc_deregister(&ws2812_misc_dev);
++	gpio_free(ws2812_pin);
++
++	return 0;
++}
++
++static const struct of_device_id ws2812_of_match[] = {
++	{.compatible = "rgb-ws2812"},
++	{/* sentinel */}};
++
++MODULE_DEVICE_TABLE(of, ws2812_of_match);
++
++static struct platform_driver ws2812_driver = {
++	.probe		= ws2812_probe,
++	.remove		= ws2812_remove,
++	.driver		= {
++		.name	= "ws2812_ctl",
++		.of_match_table = ws2812_of_match,
++	},
++};
++
++module_platform_driver(ws2812_driver);
++
++MODULE_AUTHOR("MacLodge, Alan Ma <tech@biqu3d.com>");
++MODULE_DESCRIPTION("WS2812 RGB driver for Allwinner");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ws2812_ctl");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch
new file mode 100644
index 000000000000..9a6c1668cc5d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch
@@ -0,0 +1,48 @@
+From b6b946580b8e87d715f6449c8023bb70ac649783 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 2 Jan 2021 15:52:27 -0600
+Subject: Input: axp20x-pek - allow wakeup after shutdown
+
+While the AXP20x PMIC handles the power button itself after shutting
+down, it is not always possible to use the PMIC's built-in shutdown
+feature, such as when other wakeup sources are needed (for example, an
+IR remote or wake-on-LAN) that require firmware support. In that case,
+the PMIC remains on, but suspended, until the board is powered back on.
+
+During this "fake" off state, IRQ configuration is similar to system
+sleep, where enable_irq_wake() must be call on an IRQ for it to be
+wakeup capable. Run the suspend callback to arm the power button IRQs
+during the shutdown process, so the power button works in this state.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/input/misc/axp20x-pek.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/input/misc/axp20x-pek.c b/drivers/input/misc/axp20x-pek.c
+index 4581606a28d6..7217dc6ed26a 100644
+--- a/drivers/input/misc/axp20x-pek.c
++++ b/drivers/input/misc/axp20x-pek.c
+@@ -393,6 +393,11 @@ static const struct dev_pm_ops axp20x_pek_pm_ops = {
+ 	.resume_noirq = pm_sleep_ptr(axp20x_pek_resume_noirq),
+ };
+ 
++static void axp20x_pek_shutdown(struct platform_device *pdev)
++{
++	axp20x_pek_suspend(&pdev->dev);
++}
++
+ static const struct platform_device_id axp_pek_id_match[] = {
+ 	{
+ 		.name = "axp20x-pek",
+@@ -408,6 +413,7 @@ MODULE_DEVICE_TABLE(platform, axp_pek_id_match);
+ 
+ static struct platform_driver axp20x_pek_driver = {
+ 	.probe		= axp20x_pek_probe,
++	.shutdown	= axp20x_pek_shutdown,
+ 	.id_table	= axp_pek_id_match,
+ 	.driver		= {
+ 		.name		= "axp20x-pek",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch
new file mode 100644
index 000000000000..9e33b65fb139
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch
@@ -0,0 +1,39 @@
+From 633be858e3fa418f2e1ecab9cbfb6dd78232efd3 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Wed, 31 May 2023 08:12:00 +0000
+Subject: LED-green_power_on-red_status_heartbeat
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+---
+ .../boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi      | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 54dfaf24e75d..3d996494d37c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -27,16 +27,17 @@ leds {
+ 		compatible = "gpio-leds";
+ 
+ 		led-0 {
+-			function = LED_FUNCTION_POWER;
++			function = LED_FUNCTION_STATUS;
+ 			color = <LED_COLOR_ID_RED>;
+ 			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+-			default-state = "on";
++			linux,default-trigger = "heartbeat";
+ 		};
+ 
+ 		led-1 {
+-			function = LED_FUNCTION_STATUS;
++			function = LED_FUNCTION_POWER;
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++			default-state = "on";
+ 		};
+ 	};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch
new file mode 100644
index 000000000000..591e1ac5f13a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch
@@ -0,0 +1,195 @@
+From b8f2e5aba953293fc13a6ea819924cf415baa30a Mon Sep 17 00:00:00 2001
+From: Alan <Alan>
+Date: Sat, 20 May 2023 14:44:07 +0800
+Subject: Optimize: TSC2007 touchscreen add polling method
+
+---
+ drivers/input/touchscreen/tsc2007.h      |   6 ++
+ drivers/input/touchscreen/tsc2007_core.c | 110 +++++++++++++++++++++--
+ 2 files changed, 108 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/input/touchscreen/tsc2007.h b/drivers/input/touchscreen/tsc2007.h
+index 69b08dd6c8df..5252b6c6daeb 100644
+--- a/drivers/input/touchscreen/tsc2007.h
++++ b/drivers/input/touchscreen/tsc2007.h
+@@ -66,10 +66,13 @@ struct tsc2007 {
+ 	u16			model;
+ 	u16			x_plate_ohms;
+ 	u16			max_rt;
++	u16			rt_thr;
++	u8			touched;
+ 	unsigned long		poll_period; /* in jiffies */
+ 	int			fuzzx;
+ 	int			fuzzy;
+ 	int			fuzzz;
++	bool			ignore_nak;
+ 
+ 	struct gpio_desc	*gpiod;
+ 	int			irq;
+@@ -81,6 +84,9 @@ struct tsc2007 {
+ 	void			(*clear_penirq)(void);
+ 
+ 	struct mutex		mlock;
++
++	struct timer_list timer;
++	struct work_struct work_i2c_poll;
+ };
+ 
+ int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd);
+diff --git a/drivers/input/touchscreen/tsc2007_core.c b/drivers/input/touchscreen/tsc2007_core.c
+index b3655250d4a7..5267b0d0ad8c 100644
+--- a/drivers/input/touchscreen/tsc2007_core.c
++++ b/drivers/input/touchscreen/tsc2007_core.c
+@@ -28,6 +28,8 @@
+ #include <linux/platform_data/tsc2007.h>
+ #include "tsc2007.h"
+ 
++#define POLL_INTERVAL_MS 17 /* 17ms = 60fps */
++
+ int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd)
+ {
+ 	s32 data;
+@@ -172,6 +174,65 @@ static irqreturn_t tsc2007_soft_irq(int irq, void *handle)
+ 	return IRQ_HANDLED;
+ }
+ 
++static irqreturn_t tsc2007_soft_poll(int irq, void *handle)
++{
++	struct tsc2007 *ts = handle;
++	struct input_dev *input = ts->input;
++	struct ts_event tc;
++	u32 rt;
++
++	if(!ts->stopped) {
++
++		mutex_lock(&ts->mlock);
++		tsc2007_read_values(ts, &tc);
++		mutex_unlock(&ts->mlock);
++
++		rt = tsc2007_calculate_resistance(ts, &tc);
++
++		if (rt == 0 || rt == 256) {
++
++			/*
++				* Sample found inconsistent by debouncing or pressure is
++				* beyond the maximum. Don't report it to user space,
++				* repeat at least once more the measurement.
++				*/
++			dev_dbg(&ts->client->dev, "ignored pressure %d\n", rt);
++
++		} else {
++
++			if (rt < ts->rt_thr) {
++
++				dev_dbg(&ts->client->dev,
++					"DOWN point(%4d,%4d), resistance (%4u)\n",
++					tc.x, tc.y, rt);
++
++				rt = ts->max_rt - rt;
++
++				input_report_key(input, BTN_TOUCH, 1);
++				input_report_abs(input, ABS_X, tc.y);
++				input_report_abs(input, ABS_Y, 4096 - tc.x);
++				input_report_abs(input, ABS_PRESSURE, rt);
++
++				input_sync(input);
++				ts->touched = 1;
++
++			} else if (ts->touched == 1) {
++
++				dev_dbg(&ts->client->dev, "UP\n");
++
++				input_report_key(input, BTN_TOUCH, 0);
++				input_report_abs(input, ABS_PRESSURE, 0);
++				input_sync(input);
++				ts->touched = 0;
++			}
++		}
++
++
++	}
++
++	return IRQ_HANDLED;
++}
++
+ static void tsc2007_stop(struct tsc2007 *ts)
+ {
+ 	ts->stopped = true;
+@@ -216,11 +277,32 @@ static int tsc2007_get_pendown_state_gpio(struct device *dev)
+ 	return gpiod_get_value_cansleep(ts->gpiod);
+ }
+ 
++static void tsc2007_ts_irq_poll_timer(struct timer_list *t)
++{
++	struct tsc2007 *ts = from_timer(ts, t, timer);
++
++	schedule_work(&ts->work_i2c_poll);
++	mod_timer(&ts->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS));
++}
++
++static void tsc2007_ts_work_i2c_poll(struct work_struct *work)
++{
++	struct tsc2007 *ts = container_of(work,
++			struct tsc2007, work_i2c_poll);
++
++	tsc2007_soft_poll(0, ts);
++}
++
+ static int tsc2007_probe_properties(struct device *dev, struct tsc2007 *ts)
+ {
+ 	u32 val32;
+ 	u64 val64;
+ 
++	ts->ignore_nak = device_property_read_bool(dev, "i2c,ignore-nak");
++
++	if (!device_property_read_u32(dev, "ti,rt-thr", &val32))
++		ts->rt_thr = val32;
++
+ 	if (!device_property_read_u32(dev, "ti,max-rt", &val32))
+ 		ts->max_rt = val32;
+ 	else
+@@ -317,6 +399,9 @@ static int tsc2007_probe(struct i2c_client *client)
+ 	if (!input_dev)
+ 		return -ENOMEM;
+ 
++	if (ts->ignore_nak)
++		client->flags |= I2C_M_IGNORE_NAK;
++
+ 	i2c_set_clientdata(client, ts);
+ 
+ 	ts->client = client;
+@@ -362,14 +447,23 @@ static int tsc2007_probe(struct i2c_client *client)
+ 			pdata->init_platform_hw();
+ 	}
+ 
+-	err = devm_request_threaded_irq(&client->dev, ts->irq,
+-					NULL, tsc2007_soft_irq,
+-					IRQF_ONESHOT,
+-					client->dev.driver->name, ts);
+-	if (err) {
+-		dev_err(&client->dev, "Failed to request irq %d: %d\n",
+-			ts->irq, err);
+-		return err;
++	if (ts->gpiod) {
++		err = devm_request_threaded_irq(&client->dev, ts->irq,
++						NULL, tsc2007_soft_irq,
++						IRQF_ONESHOT,
++						client->dev.driver->name, ts);
++		if (err) {
++			dev_err(&client->dev, "Failed to request irq %d: %d\n",
++				ts->irq, err);
++			return err;
++		}
++	} else {
++		INIT_WORK(&ts->work_i2c_poll,
++			  tsc2007_ts_work_i2c_poll);
++		timer_setup(&ts->timer, tsc2007_ts_irq_poll_timer, 0);
++		ts->timer.expires = jiffies +
++					msecs_to_jiffies(POLL_INTERVAL_MS);
++		add_timer(&ts->timer);
+ 	}
+ 
+ 	tsc2007_stop(ts);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs-arch-arm64-boot-dts-allwinne.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs-arch-arm64-boot-dts-allwinne.patch
new file mode 100644
index 000000000000..ce86532651d6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs-arch-arm64-boot-dts-allwinne.patch
@@ -0,0 +1,5452 @@
+From 1a8ee4f49169293e1144c2297db537a1e7de63ed Mon Sep 17 00:00:00 2001
+From: Stephen Graf <stephen.graf@gmail.com>
+Date: Thu, 9 May 2024 20:59:34 -0700
+Subject: Sound for H616, H618 Allwinner SOCs
+
+Signed-off-by: Stephen Graf <stephen.graf@gmail.com>
+---
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  |   18 +
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi |   83 +
+ drivers/clk/sunxi-ng/ccu-sun50i-h616.c        |   33 +-
+ include/sound/soc-dai.h                       |   13 +
+ sound/soc/Kconfig                             |    1 +
+ sound/soc/Makefile                            |    1 +
+ sound/soc/soc-core.c                          |   25 +
+ sound/soc/sunxi/Kconfig                       |    8 +
+ sound/soc/sunxi/Makefile                      |    1 +
+ sound/soc/sunxi/sun50iw9-codec.c              | 1093 ++++++++++++
+ sound/soc/sunxi_v2/Kconfig                    |   48 +
+ sound/soc/sunxi_v2/Makefile                   |   11 +
+ sound/soc/sunxi_v2/drv_hdmi.h                 |   63 +
+ sound/soc/sunxi_v2/snd_sunxi_ahub.c           | 1477 +++++++++++++++++
+ sound/soc/sunxi_v2/snd_sunxi_ahub.h           |   67 +
+ sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c       |  534 ++++++
+ sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h       |  291 ++++
+ sound/soc/sunxi_v2/snd_sunxi_common.c         |  267 +++
+ sound/soc/sunxi_v2/snd_sunxi_common.h         |   67 +
+ sound/soc/sunxi_v2/snd_sunxi_log.h            |   29 +
+ sound/soc/sunxi_v2/snd_sunxi_mach.c           |  479 ++++++
+ sound/soc/sunxi_v2/snd_sunxi_mach.h           |   17 +
+ sound/soc/sunxi_v2/snd_sunxi_mach_utils.c     |  422 +++++
+ sound/soc/sunxi_v2/snd_sunxi_mach_utils.h     |  116 ++
+ 24 files changed, 5147 insertions(+), 17 deletions(-)
+ create mode 100644 sound/soc/sunxi/sun50iw9-codec.c
+ create mode 100644 sound/soc/sunxi_v2/Kconfig
+ create mode 100644 sound/soc/sunxi_v2/Makefile
+ create mode 100644 sound/soc/sunxi_v2/drv_hdmi.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_common.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_common.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_log.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach_utils.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach_utils.h
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index ce3dc6d9cd66..23553f2249c2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -105,6 +105,24 @@ &de {
+ 	status = "okay";
+ };
+ 
++&codec {
++        allwinner,audio-routing =
++                "Line Out", "LINEOUT";
++        status = "okay";
++};
++
++&ahub_dam_plat {
++        status = "okay";
++};
++
++&ahub1_plat {
++        status = "okay";
++};
++
++&ahub1_mach {
++        status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 90e55a6aef1d..3df5b74bf306 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -182,6 +182,78 @@ dma: dma-controller@3002000 {
+ 			#dma-cells = <1>;
+ 		};
+ 
++                codec: codec@05096000 {
++                        #sound-dai-cells = <0>;
++                        compatible = "allwinner,sun50i-h616-codec";
++                        reg = <0x05096000 0x31c>;
++                        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++                        clocks = <&ccu CLK_BUS_AUDIO_CODEC>,
++                                 <&ccu CLK_AUDIO_CODEC_1X>,
++                                 <&ccu CLK_AUDIO_CODEC_4X>;
++                        clock-names = "apb", "audio-codec-1x", "audio-codec-4x";
++                        resets = <&ccu RST_BUS_AUDIO_CODEC>;
++                        dmas = <&dma 6>;
++                        dma-names = "tx";
++                        status = "disabled";
++                };
++
++                ahub_dam_plat:ahub_dam_plat@5097000 {
++                        #sound-dai-cells = <0>;
++                        /* sound card without pcm for hardware mix setting */
++                        compatible      = "allwinner,sunxi-snd-plat-ahub_dam";
++                        reg             = <0x05097000 0x1000>;
++                        resets          = <&ccu RST_BUS_AUDIO_HUB>;
++                        clocks          = <&ccu CLK_AUDIO_CODEC_1X>,
++                                          <&ccu CLK_AUDIO_CODEC_4X>,
++                                          <&ccu CLK_AUDIO_HUB>,
++                                          <&ccu CLK_BUS_AUDIO_HUB>;
++                        clock-names     = "clk_pll_audio",
++                                          "clk_pll_audio_4x",
++                                          "clk_audio_hub",
++                                          "clk_bus_audio_hub";
++                        status          = "disabled";
++                };
++
++                ahub1_plat:ahub1_plat {
++                        #sound-dai-cells = <0>;
++                        compatible      = "allwinner,sunxi-snd-plat-ahub";
++                        apb_num         = <1>;  /* for dma port 4 */
++                        dmas            = <&dma 4>, <&dma 4>;
++                        dma-names       = "tx", "rx";
++                        playback_cma    = <128>;
++                        capture_cma     = <128>;
++                        tx_fifo_size    = <128>;
++                        rx_fifo_size    = <128>;
++
++                        tdm_num         = <1>;
++                        tx_pin          = <0>;
++                        rx_pin          = <0>;
++                        status          = "disabled";
++                };
++
++                ahub1_mach:ahub1_mach {
++                        compatible = "allwinner,sunxi-snd-mach";
++                        soundcard-mach,name = "HDMI";
++
++                        soundcard-mach,format           = "i2s";
++                        soundcard-mach,frame-master     = <&ahub1_cpu>;
++                        soundcard-mach,bitclock-master  = <&ahub1_cpu>;
++                        /* soundcard-mach,frame-inversion; */
++                        /* soundcard-mach,bitclock-inversion; */
++                        soundcard-mach,slot-num         = <2>;
++                        soundcard-mach,slot-width       = <32>;
++                        status          = "disabled";
++                        ahub1_cpu: soundcard-mach,cpu {
++                                sound-dai = <&ahub1_plat>;
++                                soundcard-mach,pll-fs   = <4>;
++                                soundcard-mach,mclk-fs  = <0>;
++                        };
++
++                        ahub1_codec: soundcard-mach,codec {
++                                sound-dai = <&hdmi>;
++                        };
++                };
++
+ 		gpu: gpu@1800000 {
+ 			compatible = "allwinner,sun50i-h616-mali",
+ 				     "arm,mali-bifrost";
+@@ -457,6 +529,17 @@ gic: interrupt-controller@3021000 {
+ 			#interrupt-cells = <3>;
+ 		};
+ 
++                iommu: iommu@30f0000 {
++                        compatible = "allwinner,sun50i-h616-iommu",
++                                     "allwinner,sun50i-h6-iommu";
++                        reg = <0x030f0000 0x10000>;
++                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
++                        clocks = <&ccu CLK_BUS_IOMMU>;
++                        resets = <&ccu RST_BUS_IOMMU>;
++                        #iommu-cells = <1>;
++                        status = "okay";
++                };
++
+ 		mmc0: mmc@4020000 {
+ 			compatible = "allwinner,sun50i-h616-mmc",
+ 				     "allwinner,sun50i-a100-mmc";
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+index 21e918582aa5..ab2628596b36 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+@@ -215,20 +215,22 @@ static struct ccu_nkmp pll_de_clk = {
+ 	},
+ };
+ 
+-/*
+- * TODO: Determine SDM settings for the audio PLL. The manual suggests
+- * PLL_FACTOR_N=16, PLL_POST_DIV_P=2, OUTPUT_DIV=2, pattern=0xe000c49b
+- * for 24.576 MHz, and PLL_FACTOR_N=22, PLL_POST_DIV_P=3, OUTPUT_DIV=2,
+- * pattern=0xe001288c for 22.5792 MHz.
+- * This clashes with our fixed PLL_POST_DIV_P.
+- */
+ #define SUN50I_H616_PLL_AUDIO_REG	0x078
++
++static struct ccu_sdm_setting pll_audio_sdm_table[] = {
++        { .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 },
++        { .rate = 98304000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
++};
++
+ static struct ccu_nm pll_audio_hs_clk = {
+ 	.enable		= BIT(31),
+ 	.lock		= BIT(28),
+ 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
+-	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
++        .m              = _SUNXI_CCU_DIV(16, 6),
++        .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table,
++                                         BIT(24), 0x178, BIT(31)),
+ 	.common		= {
++                .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
+ 		.reg		= 0x078,
+ 		.hw.init	= CLK_HW_INIT("pll-audio-hs", "osc24M",
+ 					      &ccu_nm_ops,
+@@ -688,13 +690,13 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
+  */
+ static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x",
+ 			    clk_parent_pll_audio,
+-			    96, 1, CLK_SET_RATE_PARENT);
++                            4, 1, CLK_SET_RATE_PARENT);
+ static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ 			    clk_parent_pll_audio,
+-			    48, 1, CLK_SET_RATE_PARENT);
++                            2, 1, CLK_SET_RATE_PARENT);
+ static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ 			    clk_parent_pll_audio,
+-			    24, 1, CLK_SET_RATE_PARENT);
++                            1, 1, CLK_SET_RATE_PARENT);
+ 
+ static const struct clk_hw *pll_periph0_parents[] = {
+ 	&pll_periph0_clk.common.hw
+@@ -1130,13 +1132,10 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev)
+ 		writel(val, reg + usb2_clk_regs[i]);
+ 	}
+ 
+-	/*
+-	 * Force the post-divider of pll-audio to 12 and the output divider
+-	 * of it to 2, so 24576000 and 22579200 rates can be set exactly.
+-	 */
+ 	val = readl(reg + SUN50I_H616_PLL_AUDIO_REG);
+-	val &= ~(GENMASK(21, 16) | BIT(0));
+-	writel(val | (11 << 16) | BIT(0), reg + SUN50I_H616_PLL_AUDIO_REG);
++        val &= ~BIT(1);
++        val |= BIT(0);
++        writel(val, reg + SUN50I_H616_PLL_AUDIO_REG);
+ 
+ 	/*
+ 	 * First clock parent (osc32K) is unusable for CEC. But since there
+diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h
+index adcd8719d343..778751096c23 100644
+--- a/include/sound/soc-dai.h
++++ b/include/sound/soc-dai.h
+@@ -415,6 +415,15 @@ struct snd_soc_dai_driver {
+ 	struct snd_soc_dobj dobj;
+ 	struct of_phandle_args *dai_args;
+ 
++        /* DAI driver callbacks */
++        int (*probe)(struct snd_soc_dai *dai);
++        int (*remove)(struct snd_soc_dai *dai);
++        /* compress dai */
++        int (*compress_new)(struct snd_soc_pcm_runtime *rtd, int num);
++        /* Optional Callback used at pcm creation*/
++        int (*pcm_new)(struct snd_soc_pcm_runtime *rtd,
++                      struct snd_soc_dai *dai);
++
+ 	/* ops */
+ 	const struct snd_soc_dai_ops *ops;
+ 	const struct snd_soc_cdai_ops *cops;
+@@ -425,6 +434,10 @@ struct snd_soc_dai_driver {
+ 	unsigned int symmetric_rate:1;
+ 	unsigned int symmetric_channels:1;
+ 	unsigned int symmetric_sample_bits:1;
++
++        /* probe ordering - for components with runtime dependencies */
++        int probe_order;
++        int remove_order;
+ };
+ 
+ /* for Playback/Capture */
+diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
+index 439fa631c342..7dc3967ccb27 100644
+--- a/sound/soc/Kconfig
++++ b/sound/soc/Kconfig
+@@ -108,6 +108,7 @@ source "sound/soc/starfive/Kconfig"
+ source "sound/soc/sti/Kconfig"
+ source "sound/soc/stm/Kconfig"
+ source "sound/soc/sunxi/Kconfig"
++source "sound/soc/sunxi_v2/Kconfig"
+ source "sound/soc/tegra/Kconfig"
+ source "sound/soc/ti/Kconfig"
+ source "sound/soc/uniphier/Kconfig"
+diff --git a/sound/soc/Makefile b/sound/soc/Makefile
+index 8376fdb217ed..79b48e8b3657 100644
+--- a/sound/soc/Makefile
++++ b/sound/soc/Makefile
+@@ -65,6 +65,7 @@ obj-$(CONFIG_SND_SOC)	+= starfive/
+ obj-$(CONFIG_SND_SOC)	+= sti/
+ obj-$(CONFIG_SND_SOC)	+= stm/
+ obj-$(CONFIG_SND_SOC)	+= sunxi/
++obj-$(CONFIG_SND_SOC)   += sunxi_v2/
+ obj-$(CONFIG_SND_SOC)	+= tegra/
+ obj-$(CONFIG_SND_SOC)	+= ti/
+ obj-$(CONFIG_SND_SOC)	+= uniphier/
+diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
+index e65fe3a7c3e4..f43402e66020 100644
+--- a/sound/soc/soc-core.c
++++ b/sound/soc/soc-core.c
+@@ -2523,6 +2523,7 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component,
+ {
+ 	struct device *dev = component->dev;
+ 	struct snd_soc_dai *dai;
++        struct snd_soc_dai_ops *ops; /* REMOVE ME */
+ 
+ 	lockdep_assert_held(&client_mutex);
+ 
+@@ -2551,6 +2552,30 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component,
+ 	if (!dai->name)
+ 		return NULL;
+ 
++        /* REMOVE ME */
++        if (dai_drv->probe              ||
++            dai_drv->remove             ||
++            dai_drv->compress_new       ||
++            dai_drv->pcm_new            ||
++            dai_drv->probe_order        ||
++            dai_drv->remove_order) {
++
++                ops = devm_kzalloc(dev, sizeof(struct snd_soc_dai_ops), GFP_KERNEL);
++                if (!ops)
++                        return NULL;
++                if (dai_drv->ops)
++                        memcpy(ops, dai_drv->ops, sizeof(struct snd_soc_dai_ops));
++
++                ops->probe              = dai_drv->probe;
++                ops->remove             = dai_drv->remove;
++                ops->compress_new       = dai_drv->compress_new;
++                ops->pcm_new            = dai_drv->pcm_new;
++                ops->probe_order        = dai_drv->probe_order;
++                ops->remove_order       = dai_drv->remove_order;
++
++                dai_drv->ops = ops;
++        }
++
+ 	dai->component = component;
+ 	dai->dev = dev;
+ 	dai->driver = dai_drv;
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index 753c38c5d554..0f6579ea7143 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -10,6 +10,14 @@ config SND_SUN4I_CODEC
+ 	  Select Y or M to add support for the Codec embedded in the Allwinner
+ 	  A10 and affiliated SoCs.
+ 
++config SND_SUN50IW9_CODEC
++        tristate "Allwinner H616 Codec Support"
++        select SND_SOC_GENERIC_DMAENGINE_PCM
++        select REGMAP_MMIO
++        help
++          Select Y or M to add support for the Codec embedded in the Allwinner
++          H616 and affiliated SoCs.
++
+ config SND_SUN8I_CODEC
+ 	tristate "Allwinner SUN8I audio codec"
+ 	depends on OF
+diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
+index b0b976a3d069..f72d94f3004c 100644
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
+ obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-codec.o
++obj-$(CONFIG_SND_SUN50IW9_CODEC) += sun50iw9-codec.o
+ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
+ obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+ obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
+diff --git a/sound/soc/sunxi/sun50iw9-codec.c b/sound/soc/sunxi/sun50iw9-codec.c
+new file mode 100644
+index 000000000000..38b1d3824c20
+--- /dev/null
++++ b/sound/soc/sunxi/sun50iw9-codec.c
+@@ -0,0 +1,1093 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright 2014 Emilio López <emilio@elopez.com.ar>
++ * Copyright 2014 Jon Smirl <jonsmirl@gmail.com>
++ * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
++ * Copyright 2015 Adam Sampson <ats@offog.org>
++ * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
++ * Copyright 2021 gryzun <gryzun_an@rambler.ru>
++ *
++ * Based on the Allwinner SDK driver, released under the GPL.
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/of_platform.h>
++#include <linux/clk.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/gpio/consumer.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/tlv.h>
++#include <sound/initval.h>
++#include <sound/dmaengine_pcm.h>
++
++#define SUNXI_DAC_DPC (0x00)
++#define SUNXI_DAC_DPC_EN_DA (31)
++#define SUNXI_DAC_DPC_DVOL (12)
++#define SUNXI_DAC_DPC_HPF_EN (18)
++
++#define SUNXI_DAC_FIFOC (0x10)
++#define SUNXI_DAC_FIFOC_DAC_FS (29)
++#define SUNXI_DAC_FIFOC_TX_FIFO_MODE (24)
++#define SUNXI_DAC_FIFOC_DRQ_CLR_CNT (21)
++#define SUNXI_DAC_FIFOC_MONO_EN (6)
++#define SUNXI_DAC_FIFOC_TX_SAMPLE_BITS (5)
++#define SUNXI_DAC_FIFOC_DAC_DRQ_EN (4)
++#define SUNXI_DAC_FIFOC_FIFO_FLUSH (0)
++
++#define SUNXI_DAC_FIFO_STA (0x14)
++#define SUNXI_DAC_TXE_INT (3)
++#define SUNXI_DAC_TXU_INT (2)
++#define SUNXI_DAC_TXO_INT (1)
++#define SUNXI_DAC_TXDATA (0x20)
++#define SUNXI_DAC_CNT (0x24)
++#define SUNXI_DAC_DG_REG (0x28)
++#define SUNXI_DAC_DAP_CTL (0xf0)
++
++#define SUNXI_DAC_AC_DAC_REG (0x310)
++#define SUNXI_DAC_LEN (15)
++#define SUNXI_DAC_REN (14)
++#define SUNXI_LINEOUTL_EN (13)
++#define SUNXI_LMUTE (12)
++#define SUNXI_LINEOUTR_EN (11)
++#define SUNXI_RMUTE (10)
++#define SUNXI_RSWITCH (9)
++#define SUNXI_RAMPEN (8)
++#define SUNXI_LINEOUTL_SEL (6)
++#define SUNXI_LINEOUTR_SEL (5)
++#define SUNXI_LINEOUT_VOL (0)
++
++#define SUNXI_DAC_AC_MIXER_REG (0x314)
++#define SUNXI_LMIX_LDAC (21)
++#define SUNXI_LMIX_RDAC (20)
++#define SUNXI_RMIX_RDAC (17)
++#define SUNXI_RMIX_LDAC (16)
++#define SUNXI_LMIXEN (11)
++#define SUNXI_RMIXEN (10)
++
++#define SUNXI_DAC_AC_RAMP_REG (0x31c)
++#define SUNXI_RAMP_STEP (4)
++#define SUNXI_RDEN (0)
++
++#define LABEL(constant)        \
++    {                          \
++#constant, constant, 0 \
++    }
++#define LABEL_END   \
++    {               \
++        NULL, 0, -1 \
++    }
++
++struct audiocodec_reg_label
++{
++    const char *name;
++    const unsigned int address;
++    int value;
++};
++
++static struct audiocodec_reg_label reg_labels[] = {
++    LABEL(SUNXI_DAC_DPC),
++    LABEL(SUNXI_DAC_FIFOC),
++    LABEL(SUNXI_DAC_FIFO_STA),
++    LABEL(SUNXI_DAC_CNT),
++    LABEL(SUNXI_DAC_DG_REG),
++    LABEL(SUNXI_DAC_DAP_CTL),
++    LABEL(SUNXI_DAC_AC_DAC_REG),
++    LABEL(SUNXI_DAC_AC_MIXER_REG),
++    LABEL(SUNXI_DAC_AC_RAMP_REG),
++    LABEL_END,
++};
++
++struct regmap *codec_regmap_debug = NULL;
++
++struct sun50i_h616_codec
++{
++    unsigned char *name;
++    struct device *dev;
++    struct regmap *regmap;
++    struct clk *clk_apb;
++    struct clk *clk_module;
++    struct reset_control *rst;
++    struct gpio_desc *gpio_pa;
++
++    /* ADC_FIFOC register is at different offset on different SoCs */
++    struct regmap_field *reg_adc_fifoc;
++
++    struct snd_dmaengine_dai_dma_data playback_dma_data;
++};
++
++static void sun50i_h616_codec_start_playback(struct sun50i_h616_codec *scodec)
++{
++    /* Flush TX FIFO */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       BIT(SUNXI_DAC_FIFOC_FIFO_FLUSH),
++                       BIT(SUNXI_DAC_FIFOC_FIFO_FLUSH));
++
++    /* Enable DAC DRQ */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN),
++                       BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN));
++}
++
++static void sun50i_h616_codec_stop_playback(struct sun50i_h616_codec *scodec)
++{
++    /* Disable DAC DRQ */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN),
++                       0);
++}
++
++static int sun50i_h616_codec_trigger(struct snd_pcm_substream *substream, int cmd,
++                                     struct snd_soc_dai *dai)
++{
++    struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
++
++    switch (cmd)
++    {
++    case SNDRV_PCM_TRIGGER_START:
++    case SNDRV_PCM_TRIGGER_RESUME:
++    case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN),
++                               (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN));
++        break;
++    case SNDRV_PCM_TRIGGER_STOP:
++    case SNDRV_PCM_TRIGGER_SUSPEND:
++    case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN),
++                               (0x0 << SUNXI_DAC_FIFOC_DAC_DRQ_EN));
++        break;
++    default:
++        return -EINVAL;
++    }
++    return 0;
++}
++
++static int sun50i_h616_codec_prepare(struct snd_pcm_substream *substream,
++                                     struct snd_soc_dai *dai)
++{
++    struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
++
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       (0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH),
++                       (0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH));
++    regmap_write(scodec->regmap, SUNXI_DAC_FIFO_STA,
++                 (0x1 << SUNXI_DAC_TXE_INT | 1 << SUNXI_DAC_TXU_INT | 0x1 << SUNXI_DAC_TXO_INT));
++    regmap_write(scodec->regmap, SUNXI_DAC_CNT, 0);
++
++    return 0;
++}
++
++static unsigned long sun50i_h616_codec_get_mod_freq(struct snd_pcm_hw_params *params)
++{
++    unsigned int rate = params_rate(params);
++
++    switch (rate)
++    {
++    case 176400:
++    case 88200:
++    case 44100:
++    case 33075:
++    case 22050:
++    case 14700:
++    case 11025:
++    case 7350:
++        return 22579200;
++
++    case 192000:
++    case 96000:
++    case 48000:
++    case 32000:
++    case 24000:
++    case 16000:
++    case 12000:
++    case 8000:
++        return 24576000;
++
++    default:
++        return 0;
++    }
++}
++
++static int sun50i_h616_codec_get_hw_rate(struct snd_pcm_hw_params *params)
++{
++    unsigned int rate = params_rate(params);
++
++    switch (rate)
++    {
++    case 192000:
++    case 176400:
++        return 6;
++
++    case 96000:
++    case 88200:
++        return 7;
++
++    case 48000:
++    case 44100:
++        return 0;
++
++    case 32000:
++    case 33075:
++        return 1;
++
++    case 24000:
++    case 22050:
++        return 2;
++
++    case 16000:
++    case 14700:
++        return 3;
++
++    case 12000:
++    case 11025:
++        return 4;
++
++    case 8000:
++    case 7350:
++        return 5;
++
++    default:
++        return -EINVAL;
++    }
++}
++
++static int sun50i_h616_codec_hw_params_playback(struct sun50i_h616_codec *scodec,
++                                                struct snd_pcm_hw_params *params,
++                                                unsigned int hwrate)
++{
++    u32 val;
++
++    /* Set DAC sample rate */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       7 << SUNXI_DAC_FIFOC_DAC_FS,
++                       hwrate << SUNXI_DAC_FIFOC_DAC_FS);
++
++    /* Set the number of channels we want to use */
++    if (params_channels(params) == 1)
++        val = BIT(SUNXI_DAC_FIFOC_MONO_EN);
++    else
++        val = 0;
++
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       BIT(SUNXI_DAC_FIFOC_MONO_EN),
++                       val);
++
++    /* Set the number of sample bits to either 16 or 24 bits */
++    if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32)
++    {
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                           BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS),
++                           BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS));
++
++        /* Set TX FIFO mode to padding the LSBs with 0 */
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                           BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE),
++                           0);
++
++        scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++    }
++    else
++    {
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                           BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS),
++                           0);
++
++        /* Set TX FIFO mode to repeat the MSB */
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                           BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE),
++                           BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE));
++
++        scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++    }
++
++    return 0;
++}
++
++struct sample_rate
++{
++    unsigned int samplerate;
++    unsigned int rate_bit;
++};
++
++static const struct sample_rate sample_rate_conv[] = {
++    {44100, 0},
++    {48000, 0},
++    {8000, 5},
++    {32000, 1},
++    {22050, 2},
++    {24000, 2},
++    {16000, 3},
++    {11025, 4},
++    {12000, 4},
++    {192000, 6},
++    {96000, 7},
++};
++
++static int sun50i_h616_codec_hw_params(struct snd_pcm_substream *substream,
++                                       struct snd_pcm_hw_params *params,
++                                       struct snd_soc_dai *dai)
++{
++    struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
++    unsigned long clk_freq;
++    int ret, hwrate;
++    int i;
++
++    clk_freq = sun50i_h616_codec_get_mod_freq(params);
++    if (!clk_freq)
++        return -EINVAL;
++
++    ret = clk_set_rate(scodec->clk_module, clk_freq * 2);
++    if (ret)
++        return ret;
++
++    hwrate = sun50i_h616_codec_get_hw_rate(params);
++    if (hwrate < 0)
++        return hwrate;
++
++    switch (params_format(params))
++    {
++    case SNDRV_PCM_FORMAT_S16_LE:
++        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++        {
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE),
++                               (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE));
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS),
++                               (0x0 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS));
++        }
++        break;
++    case SNDRV_PCM_FORMAT_S24_LE:
++        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++        {
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE),
++                               (0x0 << SUNXI_DAC_FIFOC_TX_FIFO_MODE));
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS),
++                               (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS));
++        }
++        break;
++    default:
++        break;
++    }
++
++    for (i = 0; i < ARRAY_SIZE(sample_rate_conv); i++)
++    {
++        if (sample_rate_conv[i].samplerate == params_rate(params))
++        {
++            if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++            {
++                regmap_update_bits(scodec->regmap,
++                                   SUNXI_DAC_FIFOC,
++                                   (0x7 << SUNXI_DAC_FIFOC_DAC_FS),
++                                   (sample_rate_conv[i].rate_bit << SUNXI_DAC_FIFOC_DAC_FS));
++            }
++        }
++    }
++
++    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++    {
++        switch (params_channels(params))
++        {
++        case 1:
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_MONO_EN),
++                               (0x1 << SUNXI_DAC_FIFOC_MONO_EN));
++            break;
++        case 2:
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_MONO_EN),
++                               (0x0 << SUNXI_DAC_FIFOC_MONO_EN));
++            break;
++        default:
++            pr_err("[%s] Playback cannot support %d channels.\n",
++                   __func__, params_channels(params));
++            return -EINVAL;
++        }
++    }
++
++    return 0;
++}
++
++static unsigned int sun50i_h616_codec_src_rates[] = {
++    8000, 11025, 12000, 16000, 22050, 24000, 32000,
++    44100, 48000, 96000, 192000};
++
++static struct snd_pcm_hw_constraint_list sun50i_h616_codec_constraints = {
++    .count = ARRAY_SIZE(sun50i_h616_codec_src_rates),
++    .list = sun50i_h616_codec_src_rates,
++};
++
++static int sun50i_h616_codec_startup(struct snd_pcm_substream *substream,
++                                     struct snd_soc_dai *dai)
++{
++    struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
++
++    snd_pcm_hw_constraint_list(substream->runtime, 0,
++                               SNDRV_PCM_HW_PARAM_RATE, &sun50i_h616_codec_constraints);
++
++    /*
++     * Stop issuing DRQ when we have room for less than 16 samples
++     * in our TX FIFO
++     */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT,
++                       3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT);
++
++    return clk_prepare_enable(scodec->clk_module);
++}
++
++static void sun50i_h616_codec_shutdown(struct snd_pcm_substream *substream,
++                                       struct snd_soc_dai *dai)
++{
++    struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
++
++    clk_disable_unprepare(scodec->clk_module);
++}
++
++static const struct snd_soc_dai_ops sun50i_h616_codec_dai_ops = {
++    .startup = sun50i_h616_codec_startup,
++    .shutdown = sun50i_h616_codec_shutdown,
++    .trigger = sun50i_h616_codec_trigger,
++    .hw_params = sun50i_h616_codec_hw_params,
++    .prepare = sun50i_h616_codec_prepare,
++};
++
++static struct snd_soc_dai_driver sun50i_h616_codec_dai = {
++    .name = "Codec",
++    .ops = &sun50i_h616_codec_dai_ops,
++    .playback = {
++        .stream_name = "Codec Playback",
++        .channels_min = 1,
++        .channels_max = 2,
++        .rate_min = 8000,
++        .rate_max = 192000,
++        .rates = SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT,
++        .formats = SNDRV_PCM_FMTBIT_S16_LE |
++                   SNDRV_PCM_FMTBIT_S24_LE,
++        .sig_bits = 24,
++    },
++};
++
++static int sunxi_lineout_event(struct snd_soc_dapm_widget *w,
++                               struct snd_kcontrol *k, int event)
++{
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card);
++
++    switch (event)
++    {
++    case SND_SOC_DAPM_POST_PMU:
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG,
++                           (0x1 << SUNXI_RDEN), (0x1 << SUNXI_RDEN));
++        msleep(25);
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN),
++                           (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN));
++        break;
++    case SND_SOC_DAPM_PRE_PMD:
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG,
++                           (0x1 << SUNXI_RDEN), (0x0 << SUNXI_RDEN));
++        msleep(25);
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN),
++                           (0x0 << SUNXI_LINEOUTL_EN) | (0x0 << SUNXI_LINEOUTR_EN));
++
++        break;
++    default:
++        break;
++    }
++
++    return 0;
++}
++
++static const DECLARE_TLV_DB_SCALE(digital_tlv, 0, -116, -7424);
++static const DECLARE_TLV_DB_SCALE(linein_to_l_r_mix_vol_tlv, -450, 150, 0);
++static const DECLARE_TLV_DB_SCALE(fmin_to_l_r_mix_vol_tlv, -450, 150, 0);
++
++static const unsigned int lineout_tlv[] = {
++    TLV_DB_RANGE_HEAD(2),
++    0,
++    0,
++    TLV_DB_SCALE_ITEM(0, 0, 1),
++    1,
++    31,
++    TLV_DB_SCALE_ITEM(-4350, 150, 1),
++};
++
++/*lineoutL mux select */
++const char *const left_lineoutl_text[] = {
++    "LOMixer",
++    "LROMixer",
++};
++
++static const struct soc_enum left_lineout_enum =
++    SOC_ENUM_SINGLE(SUNXI_DAC_AC_DAC_REG, SUNXI_LINEOUTL_SEL,
++                    ARRAY_SIZE(left_lineoutl_text), left_lineoutl_text);
++
++static const struct snd_kcontrol_new left_lineout_mux =
++    SOC_DAPM_ENUM("Left LINEOUT Mux", left_lineout_enum);
++
++/*lineoutR mux select */
++const char *const right_lineoutr_text[] = {
++    "ROMixer",
++    "LROMixer",
++};
++
++static const struct soc_enum right_lineout_enum =
++    SOC_ENUM_SINGLE(SUNXI_DAC_AC_DAC_REG, SUNXI_LINEOUTR_SEL,
++                    ARRAY_SIZE(right_lineoutr_text), right_lineoutr_text);
++
++static const struct snd_kcontrol_new right_lineout_mux =
++    SOC_DAPM_ENUM("Right LINEOUT Mux", right_lineout_enum);
++
++static const struct snd_kcontrol_new sun50i_h616_codec_codec_controls[] = {
++
++    SOC_SINGLE_TLV("digital volume", SUNXI_DAC_DPC,
++                   SUNXI_DAC_DPC_DVOL, 0x3F, 0, digital_tlv),
++
++    SOC_SINGLE_TLV("LINEOUT volume", SUNXI_DAC_AC_DAC_REG,
++                   SUNXI_LINEOUT_VOL, 0x1F, 0, lineout_tlv),
++};
++
++static const struct snd_kcontrol_new left_output_mixer[] = {
++    SOC_DAPM_SINGLE("DACL Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIX_LDAC, 1, 0),
++    SOC_DAPM_SINGLE("DACR Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIX_RDAC, 1, 0),
++};
++
++static const struct snd_kcontrol_new right_output_mixer[] = {
++    SOC_DAPM_SINGLE("DACL Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIX_LDAC, 1, 0),
++    SOC_DAPM_SINGLE("DACR Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIX_RDAC, 1, 0),
++};
++
++static const struct snd_soc_dapm_widget sun50i_h616_codec_codec_widgets[] = {
++
++    /* Digital parts of the DACs */
++    SND_SOC_DAPM_SUPPLY("DAC Enable", SUNXI_DAC_DPC,
++                        SUNXI_DAC_DPC_EN_DA, 0, NULL, 0),
++
++    SND_SOC_DAPM_AIF_IN_E("DACL", "Codec Playback", 0, SUNXI_DAC_AC_DAC_REG, SUNXI_DAC_LEN, 0,
++                          NULL, 0),
++    SND_SOC_DAPM_AIF_IN_E("DACR", "Codec Playback", 0, SUNXI_DAC_AC_DAC_REG, SUNXI_DAC_REN, 0,
++                          NULL, 0),
++
++    SND_SOC_DAPM_MIXER("Left Output Mixer", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIXEN, 0,
++                       left_output_mixer, ARRAY_SIZE(left_output_mixer)),
++    SND_SOC_DAPM_MIXER("Right Output Mixer", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIXEN, 0,
++                       right_output_mixer, ARRAY_SIZE(right_output_mixer)),
++
++    SND_SOC_DAPM_MUX("Left LINEOUT Mux", SND_SOC_NOPM,
++                     0, 0, &left_lineout_mux),
++    SND_SOC_DAPM_MUX("Right LINEOUT Mux", SND_SOC_NOPM,
++                     0, 0, &right_lineout_mux),
++
++    SND_SOC_DAPM_OUTPUT("LINEOUTL"),
++    SND_SOC_DAPM_OUTPUT("LINEOUTR"),
++
++    SND_SOC_DAPM_LINE("LINEOUT", sunxi_lineout_event),
++};
++
++static const struct snd_soc_component_driver sun50i_h616_codec_codec = {
++    .controls = sun50i_h616_codec_codec_controls,
++    .num_controls = ARRAY_SIZE(sun50i_h616_codec_codec_controls),
++    .dapm_widgets = sun50i_h616_codec_codec_widgets,
++    .num_dapm_widgets = ARRAY_SIZE(sun50i_h616_codec_codec_widgets),
++    .idle_bias_on = 1,
++    .use_pmdown_time = 1,
++    .endianness = 1,
++};
++
++static const struct snd_soc_component_driver sun50i_h616_codec_component = {
++    .name = "sun50i_h616-codec",
++    .legacy_dai_naming = 1,
++#ifdef CONFIG_DEBUG_FS
++	.debugfs_prefix		= "cpu",
++#endif
++};
++
++#define SUN50IW9_CODEC_RATES (SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT)
++#define SUN50IW9_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
++
++static int sun50i_h616_codec_dai_probe(struct snd_soc_dai *dai)
++{
++    struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(card);
++
++    snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data,
++                              NULL);
++
++    return 0;
++}
++
++static struct snd_soc_dai_driver dummy_cpu_dai = {
++    .name = "sun50i_h616-codec-cpu-dai",
++    .probe = sun50i_h616_codec_dai_probe,
++    .playback = {
++        .stream_name = "Playback",
++        .channels_min = 1,
++        .channels_max = 2,
++        .rates = SUN50IW9_CODEC_RATES,
++        .formats = SUN50IW9_CODEC_FORMATS,
++        .sig_bits = 24,
++    },
++};
++
++static struct snd_soc_dai_link *sun50i_h616_codec_create_link(struct device *dev,
++                                                              int *num_links)
++{
++    struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link),
++                                                 GFP_KERNEL);
++    struct snd_soc_dai_link_component *dlc = devm_kzalloc(dev,
++                                                          3 * sizeof(*dlc), GFP_KERNEL);
++    if (!link || !dlc)
++        return NULL;
++
++    link->cpus = &dlc[0];
++    link->codecs = &dlc[1];
++    link->platforms = &dlc[2];
++
++    link->num_cpus = 1;
++    link->num_codecs = 1;
++    link->num_platforms = 1;
++
++    link->name = "cdc";
++    link->stream_name = "CDC PCM";
++    link->codecs->dai_name = "Codec";
++    link->cpus->dai_name = dev_name(dev);
++    link->codecs->name = dev_name(dev);
++    link->platforms->name = dev_name(dev);
++    link->dai_fmt = SND_SOC_DAIFMT_I2S;
++    link->playback_only = true;
++    link->capture_only = false;
++
++    *num_links = 1;
++
++    return link;
++};
++
++static int sun50i_h616_codec_spk_event(struct snd_soc_dapm_widget *w,
++                                       struct snd_kcontrol *k, int event)
++{
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card);
++
++    gpiod_set_value_cansleep(scodec->gpio_pa,
++                             !!SND_SOC_DAPM_EVENT_ON(event));
++
++    if (SND_SOC_DAPM_EVENT_ON(event))
++    {
++        /*
++         * Need a delay to wait for DAC to push the data. 700ms seems
++         * to be the best compromise not to feel this delay while
++         * playing a sound.
++         */
++        msleep(700);
++    }
++
++    return 0;
++}
++
++static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = {
++    SND_SOC_DAPM_LINE("Line Out", NULL),
++    SND_SOC_DAPM_SPK("Speaker", sun50i_h616_codec_spk_event),
++};
++
++/* Connect digital side enables to analog side widgets */
++static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = {
++    /* DAC Routes */
++    {"DACR", NULL, "DAC Enable"},
++    {"DACL", NULL, "DAC Enable"},
++
++    {"Left Output Mixer", "DACR Switch", "DACR"},
++    {"Left Output Mixer", "DACL Switch", "DACL"},
++
++    {"Right Output Mixer", "DACL Switch", "DACL"},
++    {"Right Output Mixer", "DACR Switch", "DACR"},
++
++    {"Left LINEOUT Mux", "LOMixer", "Left Output Mixer"},
++    {"Left LINEOUT Mux", "LROMixer", "Right Output Mixer"},
++    {"Right LINEOUT Mux", "ROMixer", "Right Output Mixer"},
++    {"Right LINEOUT Mux", "LROMixer", "Left Output Mixer"},
++
++    {"LINEOUTL", NULL, "Left LINEOUT Mux"},
++    {"LINEOUTR", NULL, "Right LINEOUT Mux"},
++
++    {"LINEOUT", NULL, "LINEOUTL"},
++    {"LINEOUT", NULL, "LINEOUTR"},
++
++    {"Speaker", NULL, "LINEOUTL"},
++    {"Speaker", NULL, "LINEOUTR"},
++};
++
++static const struct snd_kcontrol_new sunxi_card_controls[] = {
++    SOC_DAPM_PIN_SWITCH("LINEOUT"),
++};
++
++static struct snd_soc_card *sun50i_h616_codec_create_card(struct device *dev)
++{
++    struct snd_soc_card *card;
++    int ret;
++
++    card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
++    if (!card)
++        return ERR_PTR(-ENOMEM);
++
++    card->dai_link = sun50i_h616_codec_create_link(dev, &card->num_links);
++    if (!card->dai_link)
++        return ERR_PTR(-ENOMEM);
++
++    card->dev = dev;
++    card->owner = THIS_MODULE;
++    card->name = "audiocodec";
++    card->controls = sunxi_card_controls;
++    card->num_controls = ARRAY_SIZE(sunxi_card_controls),
++    card->dapm_widgets = sun6i_codec_card_dapm_widgets;
++    card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
++    card->dapm_routes = sun8i_codec_card_routes;
++    card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
++    card->fully_routed = true;
++
++    ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
++    if (ret)
++        dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
++
++    return card;
++};
++
++static const struct regmap_config sun50i_h616_codec_regmap_config = {
++    .reg_bits = 32,
++    .reg_stride = 4,
++    .val_bits = 32,
++    .max_register = SUNXI_DAC_AC_RAMP_REG,
++    .cache_type = REGCACHE_NONE,
++};
++
++struct sun50i_h616_codec_quirks
++{
++    const struct regmap_config *regmap_config;
++    const struct snd_soc_component_driver *codec;
++    struct snd_soc_card *(*create_card)(struct device *dev);
++    struct reg_field reg_adc_fifoc; /* used for regmap_field */
++    unsigned int reg_dac_txdata;    /* TX FIFO offset for DMA config */
++    unsigned int reg_adc_rxdata;    /* RX FIFO offset for DMA config */
++    bool has_reset;
++};
++
++static const struct sun50i_h616_codec_quirks sun50i_h616_codec_quirks = {
++    .regmap_config = &sun50i_h616_codec_regmap_config,
++    .codec = &sun50i_h616_codec_codec,
++    .create_card = sun50i_h616_codec_create_card,
++    .reg_dac_txdata = SUNXI_DAC_TXDATA,
++    .has_reset = true,
++};
++
++static const struct of_device_id sun50i_h616_codec_of_match[] = {
++    {
++        .compatible = "allwinner,sun50i-h616-codec",
++        .data = &sun50i_h616_codec_quirks,
++    },
++    {}};
++MODULE_DEVICE_TABLE(of, sun50i_h616_codec_of_match);
++
++static ssize_t show_audio_reg(struct device *dev,
++                              struct device_attribute *attr, char *buf)
++{
++    int count = 0, i = 0;
++    unsigned int reg_val;
++    unsigned int size = ARRAY_SIZE(reg_labels);
++
++    count += sprintf(buf, "dump audiocodec reg:\n");
++
++    while ((i < size) && (reg_labels[i].name != NULL))
++    {
++        regmap_read(codec_regmap_debug,
++                    reg_labels[i].address, &reg_val);
++        count += sprintf(buf + count, "%-20s [0x%03x]: 0x%-10x save_val:0x%x\n",
++                         reg_labels[i].name, (reg_labels[i].address),
++                         reg_val, reg_labels[i].value);
++        i++;
++    }
++
++    return count;
++}
++
++static DEVICE_ATTR(audio_reg, 0644, show_audio_reg, NULL);
++
++static struct attribute *audio_debug_attrs[] = {
++    &dev_attr_audio_reg.attr,
++    NULL,
++};
++
++static struct attribute_group audio_debug_attr_group = {
++    .name = "audio_reg_debug",
++    .attrs = audio_debug_attrs,
++};
++
++static void sunxi_codec_init(struct sun50i_h616_codec *scodec)
++{
++    /* Disable DRC function for playback */
++    regmap_write(scodec->regmap, SUNXI_DAC_DAP_CTL, 0);
++
++    /* Enable HPF(high passed filter) */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_DPC,
++                       (0x1 << SUNXI_DAC_DPC_HPF_EN), (0x1 << SUNXI_DAC_DPC_HPF_EN));
++
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                       (0x1f << SUNXI_LINEOUT_VOL),
++                       (0x1a << SUNXI_LINEOUT_VOL));
++
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_DPC,
++                       (0x3f << SUNXI_DAC_DPC_DVOL), (0 << SUNXI_DAC_DPC_DVOL));
++
++    /* Mixer to channel LINEOUT MUTE control init */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                       (0x1 << SUNXI_LMUTE), (0x1 << SUNXI_LMUTE));
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                       (0x1 << SUNXI_RMUTE), (0x1 << SUNXI_RMUTE));
++
++    /* ramp func about */
++    if (0)
++    {
++        /* Not used the ramp func cause there is the MUTE to avoid pop noise */
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_RSWITCH), (0x1 << SUNXI_RSWITCH));
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_RAMPEN), (0x0 << SUNXI_RAMPEN));
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG,
++                           (0x7 << SUNXI_RAMP_STEP), (0x0 << SUNXI_RAMP_STEP));
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG,
++                           (0x1 << SUNXI_RDEN), (0x0 << SUNXI_RDEN));
++    }
++    else
++    {
++        /* If no MUTE to avoid pop, just use the ramp func to avoid it */
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_RSWITCH), (0x0 << SUNXI_RSWITCH));
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_RAMPEN), (0x1 << SUNXI_RAMPEN));
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG,
++                           (0x7 << SUNXI_RAMP_STEP), (0x1 << SUNXI_RAMP_STEP));
++    }
++}
++
++static int sun50i_h616_codec_probe(struct platform_device *pdev)
++{
++    struct snd_soc_card *card;
++    struct sun50i_h616_codec *scodec;
++    const struct sun50i_h616_codec_quirks *quirks;
++    struct resource *res;
++    void __iomem *base;
++    int ret;
++
++    scodec = devm_kzalloc(&pdev->dev, sizeof(struct sun50i_h616_codec), GFP_KERNEL);
++    if (!scodec)
++        return -ENOMEM;
++
++    scodec->dev = &pdev->dev;
++
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++    base = devm_ioremap_resource(&pdev->dev, res);
++    if (IS_ERR(base))
++        return PTR_ERR(base);
++
++    quirks = of_device_get_match_data(&pdev->dev);
++    if (quirks == NULL)
++    {
++        dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
++        return -ENODEV;
++    }
++
++    scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
++                                           quirks->regmap_config);
++    if (IS_ERR(scodec->regmap))
++    {
++        dev_err(&pdev->dev, "Failed to create our regmap\n");
++        return PTR_ERR(scodec->regmap);
++    }
++
++    /* Get the clocks from the DT */
++    scodec->clk_apb = devm_clk_get(&pdev->dev, "apb");
++    if (IS_ERR(scodec->clk_apb))
++    {
++        dev_err(&pdev->dev, "Failed to get the APB clock\n");
++        return PTR_ERR(scodec->clk_apb);
++    }
++
++    scodec->clk_module = devm_clk_get(&pdev->dev, "audio-codec-1x");
++    if (IS_ERR(scodec->clk_module))
++    {
++        dev_err(&pdev->dev, "Failed to get the codec module clock\n");
++        return PTR_ERR(scodec->clk_module);
++    }
++
++    if (quirks->has_reset)
++    {
++        scodec->rst = devm_reset_control_get_exclusive(&pdev->dev,
++                                                       NULL);
++        if (IS_ERR(scodec->rst))
++        {
++            dev_err(&pdev->dev, "Failed to get reset control\n");
++            return PTR_ERR(scodec->rst);
++        }
++    }
++
++    scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa",
++                                              GPIOD_OUT_LOW);
++    if (IS_ERR(scodec->gpio_pa))
++    {
++        ret = PTR_ERR(scodec->gpio_pa);
++        if (ret != -EPROBE_DEFER)
++            dev_err(&pdev->dev, "Failed to get pa gpio: %d\n", ret);
++        return ret;
++    }
++
++    /* Enable the bus clock */
++    if (clk_prepare_enable(scodec->clk_apb))
++    {
++        dev_err(&pdev->dev, "Failed to enable the APB clock\n");
++        return -EINVAL;
++    }
++
++    /* Deassert the reset control */
++    if (scodec->rst)
++    {
++        ret = reset_control_deassert(scodec->rst);
++        if (ret)
++        {
++            dev_err(&pdev->dev,
++                    "Failed to deassert the reset control\n");
++            goto err_clk_disable;
++        }
++    }
++
++    /* DMA configuration for TX FIFO */
++    scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata;
++    scodec->playback_dma_data.maxburst = 8;
++    scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++
++    ret = devm_snd_soc_register_component(&pdev->dev, quirks->codec,
++                                          &sun50i_h616_codec_dai, 1);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "Failed to register our codec\n");
++        goto err_assert_reset;
++    }
++
++    ret = devm_snd_soc_register_component(&pdev->dev,
++                                          &sun50i_h616_codec_component,
++                                          &dummy_cpu_dai, 1);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "Failed to register our DAI\n");
++        goto err_assert_reset;
++    }
++
++    ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "Failed to register against DMAEngine\n");
++        goto err_assert_reset;
++    }
++
++    card = quirks->create_card(&pdev->dev);
++    if (IS_ERR(card))
++    {
++        ret = PTR_ERR(card);
++        dev_err(&pdev->dev, "Failed to create our card\n");
++        goto err_assert_reset;
++    }
++
++    snd_soc_card_set_drvdata(card, scodec);
++
++    codec_regmap_debug = scodec->regmap;
++
++    ret = snd_soc_register_card(card);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "Failed to register our card\n");
++        goto err_assert_reset;
++    }
++
++    ret = sysfs_create_group(&pdev->dev.kobj, &audio_debug_attr_group);
++    if (ret)
++        dev_warn(&pdev->dev, "failed to create attr group\n");
++
++    sunxi_codec_init(scodec);
++
++    return 0;
++
++err_assert_reset:
++    if (scodec->rst)
++        reset_control_assert(scodec->rst);
++err_clk_disable:
++    clk_disable_unprepare(scodec->clk_apb);
++    return ret;
++}
++
++static int sun50i_h616_codec_remove(struct platform_device *pdev)
++{
++    struct snd_soc_card *card = platform_get_drvdata(pdev);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(card);
++
++    snd_soc_unregister_card(card);
++    if (scodec->rst)
++        reset_control_assert(scodec->rst);
++    clk_disable_unprepare(scodec->clk_apb);
++
++    return 0;
++}
++
++static struct platform_driver sun50i_h616_codec_driver = {
++    .driver = {
++        .name = "sun50i-h616-codec",
++        .of_match_table = sun50i_h616_codec_of_match,
++    },
++    .probe = sun50i_h616_codec_probe,
++    .remove = sun50i_h616_codec_remove,
++};
++module_platform_driver(sun50i_h616_codec_driver);
++
++MODULE_DESCRIPTION("Allwinner H616 codec driver");
++MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>");
++MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
++MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
++MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
++MODULE_AUTHOR("Leeboby <leeboby@aliyun.com>");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/sunxi_v2/Kconfig b/sound/soc/sunxi_v2/Kconfig
+new file mode 100644
+index 000000000000..37fc579ba9db
+--- /dev/null
++++ b/sound/soc/sunxi_v2/Kconfig
+@@ -0,0 +1,48 @@
++# common
++config SND_SOC_SUNXI_MACH
++	tristate
++
++# ahub dam
++config SND_SOC_SUNXI_AHUB_DAM
++	tristate
++
++config SND_SOC_SUNXI_INTERNALCODEC
++	tristate
++
++config SND_SOC_SUNXI_SUN50IW9_CODEC
++	tristate
++
++# menu select
++menu "Allwinner SoC Audio support V2"
++	depends on ARCH_SUNXI
++
++# aaudio
++config SND_SOC_SUNXI_AAUDIO
++	tristate "Allwinner AAUDIO support"
++	select REGMAP_MMIO
++	select SND_SOC_GENERIC_DMAENGINE_PCM
++	select SND_SOC_SUNXI_MACH
++	select SND_SOC_SUNXI_INTERNALCODEC
++	select SND_SOC_SUNXI_SUN50IW9_CODEC
++	depends on ARCH_SUNXI
++	help
++	    Select Y or M to support analog-audio Module in the Allwinner SoCs.
++
++# ahub
++config SND_SOC_SUNXI_AHUB
++	tristate "Allwinner AHUB Support"
++	select REGMAP_MMIO
++	select SND_SOC_GENERIC_DMAENGINE_PCM
++	select SND_SOC_SUNXI_MACH
++	select SND_SOC_SUNXI_AHUB_DAM
++	depends on ARCH_SUNXI
++	help
++	    Select Y or M to support audio-hub Module in Allwinner SoCs.
++
++config SND_SOC_SUNXI_DEBUG
++	tristate "Components Debug"
++	depends on SND_SOC_SUNXI_COMPONENTS
++	help
++	    Select Y or M to support debug components.
++
++endmenu
+diff --git a/sound/soc/sunxi_v2/Makefile b/sound/soc/sunxi_v2/Makefile
+new file mode 100644
+index 000000000000..c7c2ef8f9fe9
+--- /dev/null
++++ b/sound/soc/sunxi_v2/Makefile
+@@ -0,0 +1,11 @@
++# platform -> ahub
++snd_soc_sunxi_ahub_dam-objs			+= snd_sunxi_ahub_dam.o
++obj-$(CONFIG_SND_SOC_SUNXI_AHUB_DAM)		+= snd_soc_sunxi_ahub_dam.o
++
++snd_soc_sunxi_ahub-objs				+= snd_sunxi_ahub.o
++obj-$(CONFIG_SND_SOC_SUNXI_AHUB)		+= snd_soc_sunxi_ahub.o
++
++# common -> machine (note: Finally compile, save system startup time)
++snd_soc_sunxi_machine-objs			+= snd_sunxi_mach.o
++snd_soc_sunxi_machine-objs			+= snd_sunxi_mach_utils.o
++obj-$(CONFIG_SND_SOC_SUNXI_MACH)		+= snd_soc_sunxi_machine.o
+diff --git a/sound/soc/sunxi_v2/drv_hdmi.h b/sound/soc/sunxi_v2/drv_hdmi.h
+new file mode 100644
+index 000000000000..2e05489b01e1
+--- /dev/null
++++ b/sound/soc/sunxi_v2/drv_hdmi.h
+@@ -0,0 +1,63 @@
++/*
++ * Allwinner SoCs hdmi driver.
++ *
++ * Copyright (C) 2016 Allwinner.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#ifndef __DRV_HDMI_H__
++#define __DRV_HDMI_H__
++
++typedef struct {
++	__u8    hw_intf;        /* 0:iis  1:spdif 2:pcm */
++	__u16	fs_between;     /* fs */
++	__u32   sample_rate;    /*sample rate*/
++	__u8    clk_edge;       /* 0:*/
++	__u8    ch0_en;         /* 1 */
++	__u8    ch1_en;         /* 0 */
++	__u8	ch2_en;         /* 0 */
++	__u8	ch3_en;         /* 0 */
++	__u8	word_length;    /* 32 */
++	__u8    shift_ctl;      /* 0 */
++	__u8    dir_ctl;        /* 0 */
++	__u8    ws_pol;
++	__u8    just_pol;
++	__u8    channel_num;
++	__u8	data_raw;
++	__u8    sample_bit;
++	__u8    ca;     /* channel allocation */
++} hdmi_audio_t;
++
++typedef struct {
++	__s32 (*hdmi_audio_enable)(__u8 mode, __u8 channel);
++	__s32 (*hdmi_set_audio_para)(hdmi_audio_t *audio_para);
++	__s32 (*hdmi_is_playback)(void);
++} __audio_hdmi_func;
++
++enum hdmi_hpd_status {
++	STATUE_CLOSE = 0,
++	STATUE_OPEN = 1,
++};
++
++void audio_set_hdmi_func(__audio_hdmi_func *hdmi_func);
++#if defined(CONFIG_SND_SUNXI_SOC_AUDIOHUB_INTERFACE)
++void audio_set_muti_hdmi_func(__audio_hdmi_func *hdmi_func);
++#endif
++
++/******************** SND_HDMI for sunxi_v2 begain ***************************/
++#if IS_ENABLED(CONFIG_HDMI2_DISP2_SUNXI)
++extern int snd_hdmi_get_func(__audio_hdmi_func *hdmi_func);
++#else
++static inline int snd_hdmi_get_func(__audio_hdmi_func *hdmi_func)
++{
++		pr_err("HDMI Audio API is disable\n");
++
++			return -1;
++}
++#endif
++/******************** SND_HDMI for sunxi_v2 end ******************************/
++
++#endif
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub.c b/sound/soc/sunxi_v2/snd_sunxi_ahub.c
+new file mode 100644
+index 000000000000..8a1065e9183e
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub.c
+@@ -0,0 +1,1477 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_ahub.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/ioport.h>
++#include <linux/regmap.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++#include <sound/soc.h>
++#include <sound/pcm_params.h>
++#include <sound/dmaengine_pcm.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_ahub.h"
++
++#define HLOG           "AHUB"
++#define DRV_NAME       "sunxi-snd-plat-ahub"
++
++static int sunxi_ahub_dai_startup(struct snd_pcm_substream *substream,
++                                 struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               snd_soc_dai_set_dma_data(dai, substream,
++                                        &ahub_info->playback_dma_param);
++       } else {
++               snd_soc_dai_set_dma_data(dai, substream,
++                                        &ahub_info->capture_dma_param);
++       }
++
++       /* APBIF & I2S of RST and GAT */
++       if (tdm_num > 3 || apb_num > 2) {
++               SND_LOG_ERR(HLOG, "unspport tdm num or apbif num\n");
++               return -EINVAL;
++       }
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_TXDIF0_RST - apb_num),
++                                  0x1 << (APBIF_TXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_TXDIF0_GAT - apb_num),
++                                  0x1 << (APBIF_TXDIF0_GAT - apb_num));
++       } else {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_RXDIF0_RST - apb_num),
++                                  0x1 << (APBIF_RXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_RXDIF0_GAT - apb_num),
++                                  0x1 << (APBIF_RXDIF0_GAT - apb_num));
++       }
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_pll(struct snd_soc_dai *dai,
++                                 int pll_id, int source,
++                                 unsigned int freq_in, unsigned int freq_out)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct sunxi_ahub_clk_info *clk_info = NULL;
++
++       SND_LOG_DEBUG(HLOG, "stream -> %s, freq_in ->%u, freq_out ->%u\n",
++                     pll_id ? "IN" : "OUT", freq_in, freq_out);
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       clk_info = &ahub_info->clk_info;
++
++       if (freq_in > 24576000) {
++               //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pllx4)) {
++               //      SND_LOG_ERR(HLOG, "set parent of clk_module to pllx4 failed\n");
++               //      return -EINVAL;
++               //}
++
++               if (clk_set_rate(clk_info->clk_pll, freq_in)) {
++                       SND_LOG_ERR(HLOG, "freq : %u pllx4 clk unsupport\n", freq_in);
++                       return -EINVAL;
++               }
++       } else {
++               //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pll)) {
++               //      SND_LOG_ERR(HLOG, "set parent of clk_module to pll failed\n");
++               //      return -EINVAL;
++               //}
++               if (clk_set_rate(clk_info->clk_pll, freq_in)) {
++                       SND_LOG_ERR(HLOG, "freq : %u pll clk unsupport\n", freq_in);
++                       return -EINVAL;
++               }
++       }
++       if (clk_set_rate(clk_info->clk_module, freq_out / 2)) {
++               SND_LOG_ERR(HLOG, "freq : %u module clk unsupport\n", freq_out);
++               return -EINVAL;
++       }
++
++       ahub_info->pllclk_freq = freq_in;
++       ahub_info->mclk_freq = freq_out;
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
++                                    unsigned int freq, int dir)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num;
++       unsigned int mclk_ratio, mclk_ratio_map;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       if (freq == 0) {
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                                  0x1 << I2S_CLKD_MCLK, 0x0 << I2S_CLKD_MCLK);
++               SND_LOG_DEBUG(HLOG, "mclk freq: 0\n");
++               return 0;
++       }
++       if (ahub_info->pllclk_freq == 0) {
++               SND_LOG_ERR(HLOG, "pllclk freq is invalid\n");
++               return -ENOMEM;
++       }
++       mclk_ratio = ahub_info->pllclk_freq / freq;
++
++       switch (mclk_ratio) {
++       case 1:
++               mclk_ratio_map = 1;
++               break;
++       case 2:
++               mclk_ratio_map = 2;
++               break;
++       case 4:
++               mclk_ratio_map = 3;
++               break;
++       case 6:
++               mclk_ratio_map = 4;
++               break;
++       case 8:
++               mclk_ratio_map = 5;
++               break;
++       case 12:
++               mclk_ratio_map = 6;
++               break;
++       case 16:
++               mclk_ratio_map = 7;
++               break;
++       case 24:
++               mclk_ratio_map = 8;
++               break;
++       case 32:
++               mclk_ratio_map = 9;
++               break;
++       case 48:
++               mclk_ratio_map = 10;
++               break;
++       case 64:
++               mclk_ratio_map = 11;
++               break;
++       case 96:
++               mclk_ratio_map = 12;
++               break;
++       case 128:
++               mclk_ratio_map = 13;
++               break;
++       case 176:
++               mclk_ratio_map = 14;
++               break;
++       case 192:
++               mclk_ratio_map = 15;
++               break;
++       default:
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                                  0x1 << I2S_CLKD_MCLK, 0x0 << I2S_CLKD_MCLK);
++               SND_LOG_ERR(HLOG, "mclk freq div unsupport\n");
++               return -EINVAL;
++       }
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                          0xf << I2S_CLKD_MCLKDIV,
++                          mclk_ratio_map << I2S_CLKD_MCLKDIV);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                          0x1 << I2S_CLKD_MCLK, 0x1 << I2S_CLKD_MCLK);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num;
++       unsigned int bclk_ratio;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       /* ratio -> cpudai pllclk / pcm rate */
++       switch (ratio) {
++       case 1:
++               bclk_ratio = 1;
++               break;
++       case 2:
++               bclk_ratio = 2;
++               break;
++       case 4:
++               bclk_ratio = 3;
++               break;
++       case 6:
++               bclk_ratio = 4;
++               break;
++       case 8:
++               bclk_ratio = 5;
++               break;
++       case 12:
++               bclk_ratio = 6;
++               break;
++       case 16:
++               bclk_ratio = 7;
++               break;
++       case 24:
++               bclk_ratio = 8;
++               break;
++       case 32:
++               bclk_ratio = 9;
++               break;
++       case 48:
++               bclk_ratio = 10;
++               break;
++       case 64:
++               bclk_ratio = 11;
++               break;
++       case 96:
++               bclk_ratio = 12;
++               break;
++       case 128:
++               bclk_ratio = 13;
++               break;
++       case 176:
++               bclk_ratio = 14;
++               break;
++       case 192:
++               bclk_ratio = 15;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "bclk freq div unsupport\n");
++               return -EINVAL;
++       }
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                          0xf << I2S_CLKD_BCLKDIV,
++                          (bclk_ratio - 2) << I2S_CLKD_BCLKDIV);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, tx_pin, rx_pin;
++       unsigned int mode, offset;
++       unsigned int lrck_polarity, brck_polarity;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       ahub_info->fmt = fmt;
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       /* set TDM format */
++       switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++       case    SND_SOC_DAIFMT_I2S:
++               mode = 1;
++               offset = 1;
++               break;
++       case    SND_SOC_DAIFMT_RIGHT_J:
++               mode = 2;
++               offset = 0;
++               break;
++       case    SND_SOC_DAIFMT_LEFT_J:
++               mode = 1;
++               offset = 0;
++               break;
++       case    SND_SOC_DAIFMT_DSP_A:
++               mode = 0;
++               offset = 1;
++               /* L data MSB after FRM LRC (short frame) */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_WIDTH,
++                                  0x0 << I2S_FMT0_LRCK_WIDTH);
++               break;
++       case    SND_SOC_DAIFMT_DSP_B:
++               mode = 0;
++               offset = 0;
++               /* L data MSB during FRM LRC (long frame) */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_WIDTH,
++                                  0x1 << I2S_FMT0_LRCK_WIDTH);
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "format setting failed\n");
++               return -EINVAL;
++       }
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x3 << I2S_CTL_MODE, mode << I2S_CTL_MODE);
++       /* regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin),
++        *                 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++        */
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 0),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 1),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 2),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 3),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_IN_SLOT(tdm_num),
++                          0x3 << I2S_IN_OFFSET, offset << I2S_IN_OFFSET);
++
++       /* set lrck & bclk polarity */
++       switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++       case    SND_SOC_DAIFMT_NB_NF:
++               lrck_polarity = 0;
++               brck_polarity = 0;
++               break;
++       case    SND_SOC_DAIFMT_NB_IF:
++               lrck_polarity = 1;
++               brck_polarity = 0;
++               break;
++       case    SND_SOC_DAIFMT_IB_NF:
++               lrck_polarity = 0;
++               brck_polarity = 1;
++               break;
++       case    SND_SOC_DAIFMT_IB_IF:
++               lrck_polarity = 1;
++               brck_polarity = 1;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "invert clk setting failed\n");
++               return -EINVAL;
++       }
++       if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) ||
++           ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_B))
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_POLARITY,
++                                  (lrck_polarity^1) << I2S_FMT0_LRCK_POLARITY);
++       else
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_POLARITY,
++                                  lrck_polarity << I2S_FMT0_LRCK_POLARITY);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                          0x1 << I2S_FMT0_BCLK_POLARITY,
++                          brck_polarity << I2S_FMT0_BCLK_POLARITY);
++
++       /* set master/slave */
++       switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++       case    SND_SOC_DAIFMT_CBM_CFM:
++               /* lrck & bclk dir output */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                                  0x1 << I2S_CTL_CLK_OUT, 0x0 << I2S_CTL_CLK_OUT);
++               break;
++       case    SND_SOC_DAIFMT_CBS_CFS:
++               /* lrck & bclk dir input */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                                  0x1 << I2S_CTL_CLK_OUT, 0x1 << I2S_CTL_CLK_OUT);
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unknown master/slave format\n");
++               return -EINVAL;
++       }
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_tdm_slot(struct snd_soc_dai *dai,
++                                      unsigned int tx_mask, unsigned int rx_mask,
++                                      int slots, int slot_width)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, tx_pin, rx_pin;
++       unsigned int slot_width_map, lrck_width_map;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       switch (slot_width) {
++       case 8:
++               slot_width_map = 1;
++               break;
++       case 12:
++               slot_width_map = 2;
++               break;
++       case 16:
++               slot_width_map = 3;
++               break;
++       case 20:
++               slot_width_map = 4;
++               break;
++       case 24:
++               slot_width_map = 5;
++               break;
++       case 28:
++               slot_width_map = 6;
++               break;
++       case 32:
++               slot_width_map = 7;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unknown slot width\n");
++               return -EINVAL;
++       }
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                          0x7 << I2S_FMT0_SW, slot_width_map << I2S_FMT0_SW);
++
++       /* bclk num of per channel
++        * I2S/RIGHT_J/LEFT_J   -> lrck long total is lrck_width_map * 2
++        * DSP_A/DAP_B          -> lrck long total is lrck_width_map * 1
++        */
++       switch (ahub_info->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++       case    SND_SOC_DAIFMT_I2S:
++       case    SND_SOC_DAIFMT_RIGHT_J:
++       case    SND_SOC_DAIFMT_LEFT_J:
++               slots /= 2;
++               break;
++       case    SND_SOC_DAIFMT_DSP_A:
++       case    SND_SOC_DAIFMT_DSP_B:
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unsupoort format\n");
++               return -EINVAL;
++       }
++       lrck_width_map = slots * slot_width - 1;
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                          0x3ff << I2S_FMT0_LRCK_PERIOD,
++                          lrck_width_map << I2S_FMT0_LRCK_PERIOD);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_hw_params(struct snd_pcm_substream *substream,
++                                   struct snd_pcm_hw_params *params,
++                                   struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num, tx_pin, rx_pin;
++       unsigned int channels;
++       unsigned int channels_en[16] = {
++               0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff,
++               0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff
++       };
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       /* configure DMA */
++       switch (params_physical_width(params)) {
++       case 16:
++               ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++               ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++               break;
++       case 24:
++       case 32:
++               ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++               ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++               break;
++       default:
++               dev_err(dai->dev, "Unsupported physical sample width: %d\n",
++                       params_physical_width(params));
++               return -EINVAL;
++       }
++
++       /* set bits */
++       switch (params_format(params)) {
++       case SNDRV_PCM_FORMAT_S16_LE:
++               /* apbifn bits */
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                          0x7 << APBIF_TX_WS,
++                                          0x3 << APBIF_TX_WS);
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                          0x1 << APBIF_TX_TXIM,
++                                          0x1 << APBIF_TX_TXIM);
++               } else {
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                          0x7 << APBIF_RX_WS,
++                                          0x3 << APBIF_RX_WS);
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                          0x3 << APBIF_RX_RXOM,
++                                          0x1 << APBIF_RX_RXOM);
++               }
++
++               regmap_update_bits(regmap,
++                                  SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x7 << I2S_FMT0_SR,
++                                  0x3 << I2S_FMT0_SR);
++               break;
++       case SNDRV_PCM_FORMAT_S20_3LE:
++       case SNDRV_PCM_FORMAT_S24_LE:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                          0x7 << APBIF_TX_WS, 0x5 << APBIF_TX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                          0x1 << APBIF_TX_TXIM, 0x1 << APBIF_TX_TXIM);
++               } else {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                          0x7 << APBIF_RX_WS, 0x5 << APBIF_RX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                          0x3 << APBIF_RX_RXOM, 0x1 << APBIF_RX_RXOM);
++               }
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x7 << I2S_FMT0_SR, 0x5 << I2S_FMT0_SR);
++               break;
++       case SNDRV_PCM_FORMAT_S32_LE:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                          0x7 << APBIF_TX_WS, 0x7 << APBIF_TX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                          0x1 << APBIF_TX_TXIM, 0x1 << APBIF_TX_TXIM);
++               } else {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                          0x7 << APBIF_RX_WS, 0x7 << APBIF_RX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                          0x3 << APBIF_RX_RXOM, 0x1 << APBIF_RX_RXOM);
++               }
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x7 << I2S_FMT0_SR, 0x7 << I2S_FMT0_SR);
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unrecognized format bits\n");
++               return -EINVAL;
++       }
++
++       /* set channels */
++       channels = params_channels(params);
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               /* apbifn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                  0xf << APBIF_TX_CHAN_NUM,
++                                  (channels - 1) << APBIF_TX_CHAN_NUM);
++               /* tdmn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CHCFG(tdm_num),
++                                  0xf << I2S_CHCFG_TX_CHANNUM,
++                                  (channels - 1) << I2S_CHCFG_TX_CHANNUM);
++
++               regmap_update_bits(regmap,
++                                  SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin),
++                                  0xf << I2S_OUT_SLOT_NUM,
++                                  (channels - 1) << I2S_OUT_SLOT_NUM);
++               regmap_update_bits(regmap,
++                                  SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin),
++                                  0xffff << I2S_OUT_SLOT_EN,
++                                  channels_en[channels - 1] << I2S_OUT_SLOT_EN);
++       } else {
++               /* apbifn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                  0xf << APBIF_RX_CHAN_NUM,
++                                  (channels - 1) << APBIF_RX_CHAN_NUM);
++               /* tdmn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CHCFG(tdm_num),
++                                  0xf << I2S_CHCFG_RX_CHANNUM,
++                                  (channels - 1) << I2S_CHCFG_RX_CHANNUM);
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_IN_SLOT(tdm_num),
++                                  0xf << I2S_IN_SLOT_NUM,
++                                  (channels - 1) << I2S_IN_SLOT_NUM);
++       }
++
++       return 0;
++}
++
++static void sunxi_ahub_dai_tx_route(struct sunxi_ahub_info *ahub_info,
++                                   bool enable)
++{
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, tx_pin;
++       unsigned int apb_num;
++
++       SND_LOG_DEBUG(HLOG, "%s\n", enable ? "on" : "off");
++
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       apb_num = ahub_info->dts_info.apb_num;
++
++       if (enable)
++               goto tx_route_enable;
++       else
++               goto tx_route_disable;
++
++tx_route_enable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDO0_EN + tx_pin),
++                          0x1 << (I2S_CTL_SDO0_EN + tx_pin));
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_TXEN, 0x1 << I2S_CTL_TXEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_OUT_MUTE, 0x0 << I2S_CTL_OUT_MUTE);
++       /* start apbif tx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                          0x1 << APBIF_TX_START, 0x1 << APBIF_TX_START);
++       /* enable tx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_TX_DRQ, 0x1 << APBIF_TX_DRQ);
++       return;
++
++tx_route_disable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_OUT_MUTE, 0x1 << I2S_CTL_OUT_MUTE);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_TXEN, 0x0 << I2S_CTL_TXEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDO0_EN + tx_pin),
++                          0x0 << (I2S_CTL_SDO0_EN + tx_pin));
++       /* stop apbif tx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                          0x1 << APBIF_TX_START, 0x0 << APBIF_TX_START);
++       /* disable tx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_TX_DRQ, 0x0 << APBIF_TX_DRQ);
++       return;
++}
++
++static void sunxi_ahub_dai_rx_route(struct sunxi_ahub_info *ahub_info,
++                                   bool enable)
++{
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, rx_pin;
++       unsigned int apb_num;
++
++       SND_LOG_DEBUG(HLOG, "%s\n", enable ? "on" : "off");
++
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       rx_pin = ahub_info->dts_info.rx_pin;
++       apb_num = ahub_info->dts_info.apb_num;
++
++       if (enable)
++               goto rx_route_enable;
++       else
++               goto rx_route_disable;
++
++rx_route_enable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDI0_EN + rx_pin),
++                          0x1 << (I2S_CTL_SDI0_EN + rx_pin));
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_RXEN, 0x1 << I2S_CTL_RXEN);
++       /* start apbif rx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                          0x1 << APBIF_RX_START, 0x1 << APBIF_RX_START);
++       /* enable rx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_RX_DRQ, 0x1 << APBIF_RX_DRQ);
++       return;
++
++rx_route_disable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_RXEN, 0x0 << I2S_CTL_RXEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDI0_EN + rx_pin),
++                          0x0 << (I2S_CTL_SDI0_EN + rx_pin));
++       /* stop apbif rx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                          0x1 << APBIF_RX_START, 0x0 << APBIF_RX_START);
++       /* disable rx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_RX_DRQ, 0x0 << APBIF_RX_DRQ);
++       return;
++}
++
++static int sunxi_ahub_dai_trigger(struct snd_pcm_substream *substream,
++                                 int cmd,
++                                 struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++
++       switch (cmd) {
++       case    SNDRV_PCM_TRIGGER_START:
++       case    SNDRV_PCM_TRIGGER_RESUME:
++       case    SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       sunxi_ahub_dai_tx_route(ahub_info, true);
++               } else {
++                       sunxi_ahub_dai_rx_route(ahub_info, true);
++               }
++               break;
++       case    SNDRV_PCM_TRIGGER_STOP:
++       case    SNDRV_PCM_TRIGGER_SUSPEND:
++       case    SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       sunxi_ahub_dai_tx_route(ahub_info, false);
++               } else {
++                       sunxi_ahub_dai_rx_route(ahub_info, false);
++               }
++               break;
++       default:
++               return -EINVAL;
++       }
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_prepare(struct snd_pcm_substream *substream,
++                                 struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               /* clear txfifo */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                  0x1 << APBIF_TX_FTX, 0x1 << APBIF_TX_FTX);
++               /* clear tx o/u irq */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_TX_IRQ_STA(apb_num),
++                            (0x1 << APBIF_TX_OV_PEND) | (0x1 << APBIF_TX_EM_PEND));
++               /* clear tx fifo cnt */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_TXFIFO_CNT(apb_num), 0);
++       } else {
++               /* clear rxfifo */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                  0x1 << APBIF_RX_FRX, 0x1 << APBIF_RX_FRX);
++               /* clear rx o/u irq */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_RX_IRQ_STA(apb_num),
++                            (0x1 << APBIF_RX_UV_PEND) | (0x1 << APBIF_RX_AV_PEND));
++               /* clear rx fifo cnt */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_RXFIFO_CNT(apb_num), 0);
++       }
++
++       return 0;
++}
++
++static void sunxi_ahub_dai_shutdown(struct snd_pcm_substream *substream,
++                                   struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       /* APBIF & I2S of RST and GAT */
++       if (tdm_num > 3 || apb_num > 2) {
++               SND_LOG_ERR(HLOG, "unspport tdm num or apbif num\n");
++               return;
++       }
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_TXDIF0_RST - apb_num),
++                                  0x0 << (APBIF_TXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_TXDIF0_GAT - apb_num),
++                                  0x0 << (APBIF_TXDIF0_GAT - apb_num));
++       } else {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_RXDIF0_RST - apb_num),
++                                  0x0 << (APBIF_RXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_RXDIF0_GAT - apb_num),
++                                  0x0 << (APBIF_RXDIF0_GAT - apb_num));
++       }
++}
++
++static const struct snd_soc_dai_ops sunxi_ahub_dai_ops = {
++        /* call by machine */
++        .set_pll        = sunxi_ahub_dai_set_pll,       // set pllclk
++        .set_sysclk     = sunxi_ahub_dai_set_sysclk,    // set mclk
++        .set_bclk_ratio = sunxi_ahub_dai_set_bclk_ratio,// set bclk freq
++        .set_tdm_slot   = sunxi_ahub_dai_set_tdm_slot,  // set slot num and width
++        .set_fmt        = sunxi_ahub_dai_set_fmt,       // set tdm fmt
++        /* call by asoc */
++        .startup        = sunxi_ahub_dai_startup,
++        .hw_params      = sunxi_ahub_dai_hw_params,     // set hardware params
++        .prepare        = sunxi_ahub_dai_prepare,       // clean irq and fifo
++        .trigger        = sunxi_ahub_dai_trigger,       // set drq
++        .shutdown       = sunxi_ahub_dai_shutdown,
++};
++
++static void snd_soc_sunxi_ahub_init(struct sunxi_ahub_info *ahub_info)
++{
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num, tx_pin, rx_pin;
++       unsigned int reg_val = 0;
++       unsigned int rx_pin_map = 0;
++       unsigned int tdm_to_apb = 0;
++       unsigned int apb_to_tdm = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_GEN, 0x1 << I2S_CTL_GEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                          0x1 << (I2S0_RST - tdm_num),
++                          0x1 << (I2S0_RST - tdm_num));
++       regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                          0x1 << (I2S0_GAT - tdm_num),
++                          0x1 << (I2S0_GAT - tdm_num));
++
++       /* tdm tx channels map */
++       regmap_write(regmap, SUNXI_AHUB_I2S_OUT_CHMAP0(tdm_num, tx_pin), 0x76543210);
++       regmap_write(regmap, SUNXI_AHUB_I2S_OUT_CHMAP1(tdm_num, tx_pin), 0xFEDCBA98);
++
++       /* tdm rx channels map */
++       rx_pin_map = (rx_pin << 4) | (rx_pin << 12) | (rx_pin << 20) | (rx_pin << 28);
++       reg_val = 0x03020100 | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP0(tdm_num), reg_val);
++       reg_val = 0x07060504 | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP1(tdm_num), reg_val);
++       reg_val = 0x0B0A0908 | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP2(tdm_num), reg_val);
++       reg_val = 0x0F0E0D0C | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP3(tdm_num), reg_val);
++
++       /* tdm tx & rx data fmt
++        * 1. MSB first
++        * 2. transfer 0 after each sample in each slot
++        * 3. linear PCM
++        */
++       regmap_write(regmap, SUNXI_AHUB_I2S_FMT1(tdm_num), 0x30);
++
++       /* apbif tx & rx data fmt
++        * 1. MSB first
++        * 2. trigger level tx -> 0x20, rx -> 0x40
++        */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                          0x1 << APBIF_TX_TXIM, 0x0 << APBIF_TX_TXIM);
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                          0x3f << APBIF_TX_LEVEL, 0x20 << APBIF_TX_LEVEL);
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                          0x3 << APBIF_RX_RXOM, 0x0 << APBIF_RX_RXOM);
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                          0x7f << APBIF_RX_LEVEL, 0x40 << APBIF_RX_LEVEL);
++
++       /* apbif <-> tdm */
++       switch (tdm_num)
++       {
++       case 0:
++               tdm_to_apb = APBIF_RX_I2S0_TXDIF;
++               break;
++       case 1:
++               tdm_to_apb = APBIF_RX_I2S1_TXDIF;
++               break;
++       case 2:
++               tdm_to_apb = APBIF_RX_I2S2_TXDIF;
++               break;
++       case 3:
++               tdm_to_apb = APBIF_RX_I2S3_TXDIF;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unspport tdm num\n");
++               return;
++       }
++       regmap_write(regmap, SUNXI_AHUB_APBIF_RXFIFO_CONT(apb_num), 0x1 << tdm_to_apb);
++
++       switch (apb_num)
++       {
++       case 0:
++               apb_to_tdm = I2S_RX_APBIF_TXDIF0;
++               break;
++       case 1:
++               apb_to_tdm = I2S_RX_APBIF_TXDIF1;
++               break;
++       case 2:
++               apb_to_tdm = I2S_RX_APBIF_TXDIF2;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unspport apb num\n");
++               return;
++       }
++       regmap_write(regmap, SUNXI_AHUB_I2S_RXCONT(tdm_num), 0x1 << apb_to_tdm);
++
++       return;
++}
++
++static int sunxi_ahub_dai_probe(struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       /* pcm_new will using the dma_param about the cma and fifo params. */
++       snd_soc_dai_init_dma_data(dai,
++                                 &ahub_info->playback_dma_param,
++                                 &ahub_info->capture_dma_param);
++
++       snd_soc_sunxi_ahub_init(ahub_info);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_remove(struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_GEN, 0x0 << I2S_CTL_GEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                          0x1 << (I2S0_RST - tdm_num),
++                          0x0 << (I2S0_RST - tdm_num));
++       regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                          0x1 << (I2S0_GAT - tdm_num),
++                          0x0 << (I2S0_GAT - tdm_num));
++
++       return 0;
++}
++
++static struct snd_soc_dai_driver sunxi_ahub_dai = {
++       .name           = "ahub_plat",
++       .probe          = sunxi_ahub_dai_probe,
++       .remove         = sunxi_ahub_dai_remove,
++       .playback = {
++               .stream_name    = "Playback",
++               .channels_min   = 1,
++               .channels_max   = 2,
++               .rates          = SNDRV_PCM_RATE_8000_192000
++                               | SNDRV_PCM_RATE_KNOT,
++               .formats        = SNDRV_PCM_FMTBIT_S16_LE
++                               | SNDRV_PCM_FMTBIT_S24_LE
++                               | SNDRV_PCM_FMTBIT_S32_LE,
++       },
++       .capture = {
++               .stream_name    = "Capture",
++               .channels_min   = 1,
++               .channels_max   = 2,
++               .rates          = SNDRV_PCM_RATE_8000_192000
++                               | SNDRV_PCM_RATE_KNOT,
++               .formats        = SNDRV_PCM_FMTBIT_S16_LE
++                               | SNDRV_PCM_FMTBIT_S24_LE
++                               | SNDRV_PCM_FMTBIT_S32_LE,
++       },
++       .ops = &sunxi_ahub_dai_ops,
++};
++
++static int sunxi_ahub_probe(struct snd_soc_component *component)
++{
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       return 0;
++}
++
++static int sunxi_ahub_suspend(struct snd_soc_component *component)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       return 0;
++}
++
++static int sunxi_ahub_resume(struct snd_soc_component *component)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       snd_soc_sunxi_ahub_init(ahub_info);
++
++       return 0;
++}
++
++int sunxi_loopback_debug_get(struct snd_kcontrol *kcontrol,
++                            struct snd_ctl_elem_value *ucontrol)
++{
++       unsigned int reg_val;
++       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++       struct sunxi_ahub_mem_info *mem_info = &ahub_info->mem_info;
++       struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info;
++
++       regmap_read(mem_info->regmap, SUNXI_AHUB_I2S_CTL(dts_info->tdm_num), &reg_val);
++       ucontrol->value.integer.value[0] = ((reg_val & (1 << I2S_CTL_LOOP0)) ? 1 : 0);
++
++       return 0;
++}
++
++int sunxi_loopback_debug_set(struct snd_kcontrol *kcontrol,
++                            struct snd_ctl_elem_value *ucontrol)
++{
++       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++       struct sunxi_ahub_mem_info *mem_info = &ahub_info->mem_info;
++       struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info;
++
++       switch (ucontrol->value.integer.value[0]) {
++       case    0:
++               regmap_update_bits(mem_info->regmap,
++                                  SUNXI_AHUB_I2S_CTL(dts_info->tdm_num),
++                                  1 << I2S_CTL_LOOP0, 0 << I2S_CTL_LOOP0);
++               break;
++       case    1:
++               regmap_update_bits(mem_info->regmap,
++                                  SUNXI_AHUB_I2S_CTL(dts_info->tdm_num),
++                                  1 << I2S_CTL_LOOP0, 1 << I2S_CTL_LOOP0);
++               break;
++       default:
++               return -EINVAL;
++       }
++
++       return 0;
++}
++
++static const struct snd_kcontrol_new sunxi_ahub_controls[] = {
++       SOC_SINGLE_EXT("loopback debug", SND_SOC_NOPM, 0, 1, 0,
++                      sunxi_loopback_debug_get, sunxi_loopback_debug_set),
++};
++
++static struct snd_soc_component_driver sunxi_ahub_component = {
++       .name           = DRV_NAME,
++       .probe          = sunxi_ahub_probe,
++       .suspend        = sunxi_ahub_suspend,
++       .resume         = sunxi_ahub_resume,
++       .controls       = sunxi_ahub_controls,
++       .num_controls   = ARRAY_SIZE(sunxi_ahub_controls),
++};
++
++/*******************************************************************************
++ * for kernel source
++ ******************************************************************************/
++static int snd_soc_sunxi_ahub_pin_init(struct platform_device *pdev,
++                                      struct device_node *np,
++                                      struct sunxi_ahub_pinctl_info *pin_info)
++{
++       int ret = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (of_property_read_bool(np, "pinctrl_used")) {
++               pin_info->pinctrl_used = 1;
++       } else {
++               pin_info->pinctrl_used = 0;
++               SND_LOG_DEBUG(HLOG, "unused pinctrl\n");
++               return 0;
++       }
++
++       pin_info->pinctrl = devm_pinctrl_get(&pdev->dev);
++       if (IS_ERR_OR_NULL(pin_info->pinctrl)) {
++               SND_LOG_ERR(HLOG, "pinctrl get failed\n");
++               ret = -EINVAL;
++               return ret;
++       }
++       pin_info->pinstate = pinctrl_lookup_state(pin_info->pinctrl,
++                                                 PINCTRL_STATE_DEFAULT);
++       if (IS_ERR_OR_NULL(pin_info->pinstate)) {
++               SND_LOG_ERR(HLOG, "pinctrl default state get fail\n");
++               ret = -EINVAL;
++               goto err_loopup_pinstate;
++       }
++       pin_info->pinstate_sleep = pinctrl_lookup_state(pin_info->pinctrl,
++                                                       PINCTRL_STATE_SLEEP);
++       if (IS_ERR_OR_NULL(pin_info->pinstate_sleep)) {
++               SND_LOG_ERR(HLOG, "pinctrl sleep state get failed\n");
++               ret = -EINVAL;
++               goto err_loopup_pin_sleep;
++       }
++       ret = pinctrl_select_state(pin_info->pinctrl, pin_info->pinstate);
++       if (ret < 0) {
++               SND_LOG_ERR(HLOG, "daudio set pinctrl default state fail\n");
++               ret = -EBUSY;
++               goto err_pinctrl_select_default;
++       }
++
++       return 0;
++
++err_pinctrl_select_default:
++err_loopup_pin_sleep:
++err_loopup_pinstate:
++       devm_pinctrl_put(pin_info->pinctrl);
++       return ret;
++}
++
++static int snd_soc_sunxi_ahub_dts_params_init(struct platform_device *pdev,
++                                             struct device_node *np,
++                                             struct sunxi_ahub_dts_info *dts_info)
++{
++       int ret = 0;
++       unsigned int temp_val = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       /* get tdm fmt of apb_num & tdm_num & tx/rx_pin */
++       ret = of_property_read_u32(np, "apb_num", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "apb_num config missing\n");
++               dts_info->apb_num = 0;
++       } else {
++               if (temp_val > 2) {     /* APBIFn (n = 0~2) */
++                       dts_info->apb_num = 0;
++                       SND_LOG_WARN(HLOG, "apb_num config invalid\n");
++               } else {
++                       dts_info->apb_num = temp_val;
++               }
++       }
++       ret = of_property_read_u32(np, "tdm_num", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "tdm_num config missing\n");
++               dts_info->tdm_num = 0;
++       } else {
++               if (temp_val > 3) {     /* I2Sn (n = 0~3) */
++                       dts_info->tdm_num = 0;
++                       SND_LOG_WARN(HLOG, "tdm_num config invalid\n");
++               } else {
++                       dts_info->tdm_num = temp_val;
++               }
++       }
++       ret = of_property_read_u32(np, "tx_pin", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "tx_pin config missing\n");
++               dts_info->tx_pin = 0;
++       } else {
++               if (temp_val > 3) {     /* I2S_DOUTn (n = 0~3) */
++                       dts_info->tx_pin = 0;
++                       SND_LOG_WARN(HLOG, "tx_pin config invalid\n");
++               } else {
++                       dts_info->tx_pin = temp_val;
++               }
++       }
++       ret = of_property_read_u32(np, "rx_pin", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "rx_pin config missing\n");
++               dts_info->rx_pin = 0;
++       } else {
++               if (temp_val > 3) {     /* I2S_DINTn (n = 0~3) */
++                       dts_info->rx_pin = 0;
++                       SND_LOG_WARN(HLOG, "rx_pin config invalid\n");
++               } else {
++                       dts_info->rx_pin = temp_val;
++               }
++       }
++
++       SND_LOG_DEBUG(HLOG, "playback_cma : %lu\n", dts_info->playback_cma);
++       SND_LOG_DEBUG(HLOG, "capture_cma  : %lu\n", dts_info->capture_cma);
++       SND_LOG_DEBUG(HLOG, "tx_fifo_size : %lu\n", dts_info->playback_fifo_size);
++       SND_LOG_DEBUG(HLOG, "rx_fifo_size : %lu\n", dts_info->capture_fifo_size);
++       SND_LOG_DEBUG(HLOG, "apb_num      : %u\n", dts_info->apb_num);
++       SND_LOG_DEBUG(HLOG, "tdm_num      : %u\n", dts_info->tdm_num);
++       SND_LOG_DEBUG(HLOG, "tx_pin       : %u\n", dts_info->tx_pin);
++       SND_LOG_DEBUG(HLOG, "rx_pin       : %u\n", dts_info->rx_pin);
++
++       return 0;
++};
++
++static int snd_soc_sunxi_ahub_regulator_init(struct platform_device *pdev,
++                                            struct device_node *np,
++                                            struct sunxi_ahub_regulator_info *regulator_info)
++{
++       int ret = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regulator_info->regulator_name = NULL;
++       if (of_property_read_string(np, "ahub_regulator", &regulator_info->regulator_name)) {
++               SND_LOG_DEBUG(HLOG, "regulator missing\n");
++               regulator_info->regulator = NULL;
++               return 0;
++       }
++
++       regulator_info->regulator = regulator_get(NULL, regulator_info->regulator_name);
++       if (IS_ERR_OR_NULL(regulator_info->regulator)) {
++               SND_LOG_ERR(HLOG, "get duaido vcc-pin failed\n");
++               ret = -EFAULT;
++               goto err_regulator_get;
++       }
++       ret = regulator_set_voltage(regulator_info->regulator, 3300000, 3300000);
++       if (ret < 0) {
++               SND_LOG_ERR(HLOG, "set duaido voltage failed\n");
++               ret = -EFAULT;
++               goto err_regulator_set_vol;
++       }
++       ret = regulator_enable(regulator_info->regulator);
++       if (ret < 0) {
++               SND_LOG_ERR(HLOG, "enable duaido vcc-pin failed\n");
++               ret = -EFAULT;
++               goto err_regulator_enable;
++       }
++
++       return 0;
++
++err_regulator_enable:
++err_regulator_set_vol:
++       if (regulator_info->regulator)
++               regulator_put(regulator_info->regulator);
++err_regulator_get:
++       return ret;
++};
++
++static void snd_soc_sunxi_dma_params_init(struct sunxi_ahub_info *ahub_info)
++{
++       struct resource *res = ahub_info->mem_info.res;
++       struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       ahub_info->playback_dma_param.addr =
++               res->start + SUNXI_AHUB_APBIF_TXFIFO(dts_info->apb_num);
++       ahub_info->playback_dma_param.maxburst = 8;
++       //ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++
++       ahub_info->capture_dma_param.addr =
++               res->start + SUNXI_AHUB_APBIF_RXFIFO(dts_info->apb_num);
++       ahub_info->capture_dma_param.maxburst = 8;
++       //ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++};
++
++static int sunxi_ahub_dev_probe(struct platform_device *pdev)
++{
++       int ret;
++       struct device_node *np = pdev->dev.of_node;
++       struct sunxi_ahub_info *ahub_info = NULL;
++       struct sunxi_ahub_mem_info *mem_info = NULL;
++       struct sunxi_ahub_clk_info *clk_info = NULL;
++       struct sunxi_ahub_pinctl_info *pin_info = NULL;
++       struct sunxi_ahub_dts_info *dts_info = NULL;
++       struct sunxi_ahub_regulator_info *regulator_info = NULL;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       ahub_info = devm_kzalloc(&pdev->dev,
++                                 sizeof(struct sunxi_ahub_info),
++                                 GFP_KERNEL);
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "alloc sunxi_ahub_info failed\n");
++               ret = -ENOMEM;
++               goto err_devm_malloc_sunxi_daudio;
++       }
++       dev_set_drvdata(&pdev->dev, ahub_info);
++       ahub_info->dev = &pdev->dev;
++       mem_info = &ahub_info->mem_info;
++       clk_info = &ahub_info->clk_info;
++       pin_info = &ahub_info->pin_info;
++       dts_info = &ahub_info->dts_info;
++       regulator_info = &ahub_info->regulator_info;
++
++       ret = snd_soc_sunxi_ahub_mem_get(mem_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "remap get failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_mem_get;
++       }
++
++       ret = snd_soc_sunxi_ahub_clk_get(clk_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "clk get failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_clk_get;
++       }
++
++       ret = snd_soc_sunxi_ahub_dts_params_init(pdev, np, dts_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "dts init failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_dts_params_init;
++       }
++
++       ret = snd_soc_sunxi_ahub_pin_init(pdev, np, pin_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "pinctrl init failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_pin_init;
++       }
++
++       ret = snd_soc_sunxi_ahub_regulator_init(pdev, np, regulator_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "regulator_info init failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_regulator_init;
++       }
++
++       snd_soc_sunxi_dma_params_init(ahub_info);
++
++       ret = snd_soc_register_component(&pdev->dev,
++                                        &sunxi_ahub_component,
++                                        &sunxi_ahub_dai, 1);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "component register failed\n");
++               ret = -ENOMEM;
++               goto err_snd_soc_register_component;
++       }
++
++        ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
++        if (ret) {
++               SND_LOG_ERR(HLOG, "register ASoC platform failed\n");
++               ret = -ENOMEM;
++               goto err_snd_soc_sunxi_dma_platform_register;
++        }
++
++       SND_LOG_DEBUG(HLOG, "register ahub platform success\n");
++
++       return 0;
++
++err_snd_soc_sunxi_dma_platform_register:
++       snd_soc_unregister_component(&pdev->dev);
++err_snd_soc_register_component:
++err_snd_soc_sunxi_ahub_regulator_init:
++err_snd_soc_sunxi_ahub_dts_params_init:
++err_snd_soc_sunxi_ahub_pin_init:
++err_snd_soc_sunxi_ahub_clk_get:
++err_snd_soc_sunxi_ahub_mem_get:
++       devm_kfree(&pdev->dev, ahub_info);
++err_devm_malloc_sunxi_daudio:
++       of_node_put(np);
++       return ret;
++}
++
++static int sunxi_ahub_dev_remove(struct platform_device *pdev)
++{
++       struct sunxi_ahub_info *ahub_info = dev_get_drvdata(&pdev->dev);
++       struct sunxi_ahub_pinctl_info *pin_info = &ahub_info->pin_info;
++       struct sunxi_ahub_regulator_info *regulator_info = &ahub_info->regulator_info;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       snd_soc_unregister_component(&pdev->dev);
++
++       if (regulator_info->regulator) {
++               if (!IS_ERR_OR_NULL(regulator_info->regulator)) {
++                       regulator_disable(regulator_info->regulator);
++                       regulator_put(regulator_info->regulator);
++               }
++       }
++       if (pin_info->pinctrl_used) {
++               devm_pinctrl_put(pin_info->pinctrl);
++       }
++
++       devm_kfree(&pdev->dev, ahub_info);
++
++       SND_LOG_DEBUG(HLOG, "unregister ahub platform success\n");
++
++       return 0;
++}
++
++static const struct of_device_id sunxi_ahub_of_match[] = {
++       { .compatible = "allwinner," DRV_NAME, },
++       {},
++};
++MODULE_DEVICE_TABLE(of, sunxi_ahub_of_match);
++
++static struct platform_driver sunxi_ahub_driver = {
++       .driver = {
++               .name           = DRV_NAME,
++               .owner          = THIS_MODULE,
++               .of_match_table = sunxi_ahub_of_match,
++       },
++       .probe  = sunxi_ahub_dev_probe,
++       .remove = sunxi_ahub_dev_remove,
++};
++
++int __init sunxi_ahub_dev_init(void)
++{
++       int ret;
++
++       ret = platform_driver_register(&sunxi_ahub_driver);
++       if (ret != 0) {
++               SND_LOG_ERR(HLOG, "platform driver register failed\n");
++               return -EINVAL;
++       }
++
++       return ret;
++}
++
++void __exit sunxi_ahub_dev_exit(void)
++{
++       platform_driver_unregister(&sunxi_ahub_driver);
++}
++
++late_initcall(sunxi_ahub_dev_init);
++module_exit(sunxi_ahub_dev_exit);
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard platform of ahub");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub.h b/sound/soc/sunxi_v2/snd_sunxi_ahub.h
+new file mode 100644
+index 000000000000..b3c1cc592844
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub.h
+@@ -0,0 +1,67 @@
++/* sound\soc\sunxi\snd_sunxi_ahub.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_AHUB_H
++#define __SND_SUNXI_AHUB_H
++
++#include "snd_sunxi_ahub_dam.h"
++
++struct sunxi_ahub_pinctl_info {
++       struct pinctrl *pinctrl;
++       struct pinctrl_state *pinstate;
++       struct pinctrl_state *pinstate_sleep;
++
++       bool pinctrl_used;
++};
++
++struct sunxi_ahub_dts_info {
++       unsigned int dai_type;
++       unsigned int apb_num;
++       unsigned int tdm_num;
++       unsigned int tx_pin;
++       unsigned int rx_pin;
++
++       /* value must be (2^n)Kbyte */
++       size_t playback_cma;
++       size_t playback_fifo_size;
++       size_t capture_cma;
++       size_t capture_fifo_size;
++};
++
++struct sunxi_ahub_regulator_info {
++       struct regulator *regulator;
++       const char *regulator_name;
++};
++
++struct sunxi_ahub_info {
++       struct device *dev;
++
++       struct sunxi_ahub_mem_info mem_info;
++       struct sunxi_ahub_clk_info clk_info;
++       struct sunxi_ahub_pinctl_info pin_info;
++       struct sunxi_ahub_dts_info dts_info;
++       struct sunxi_ahub_regulator_info regulator_info;
++
++       //struct sunxi_dma_params playback_dma_param;
++       //struct sunxi_dma_params capture_dma_param;
++        struct snd_dmaengine_dai_dma_data playback_dma_param;
++        struct snd_dmaengine_dai_dma_data capture_dma_param;
++
++       /* for Hardware param setting */
++       unsigned int fmt;
++       unsigned int pllclk_freq;
++       unsigned int moduleclk_freq;
++       unsigned int mclk_freq;
++       unsigned int lrck_freq;
++       unsigned int bclk_freq;
++};
++
++#endif /* __SND_SUNXI_AHUB_H */
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c
+new file mode 100644
+index 000000000000..1fcc8aefd50c
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c
+@@ -0,0 +1,534 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_ahub_dam.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <sound/soc.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/device.h>
++#include <linux/ioport.h>
++#include <linux/regmap.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++#include <sound/soc.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_ahub_dam.h"
++
++#define HLOG		"AHUB_DAM"
++#define DRV_NAME	"sunxi-snd-plat-ahub_dam"
++
++static struct resource g_res;
++struct sunxi_ahub_mem_info g_mem_info = {
++	.res = &g_res,
++};
++static struct sunxi_ahub_clk_info g_clk_info;
++static struct regmap_config g_regmap_config = {
++	.reg_bits = 32,
++	.reg_stride = 4,
++	.val_bits = 32,
++	.max_register = SUNXI_AHUB_MAX_REG,
++	.cache_type = REGCACHE_NONE,
++};
++
++static struct snd_soc_dai_driver sunxi_ahub_dam_dai = {
++	.name           = "ahub_dam",
++};
++
++static int sunxi_ahub_dam_probe(struct snd_soc_component *component)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	return 0;
++}
++
++static int sunxi_ahub_dam_suspend(struct snd_soc_component *component)
++{
++	struct sunxi_ahub_clk_info *clk_info = &g_clk_info;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	clk_disable_unprepare(clk_info->clk_module);
++	clk_disable_unprepare(clk_info->clk_pll);
++	//clk_disable_unprepare(clk_info->clk_pllx4);
++	clk_disable_unprepare(clk_info->clk_bus);
++	reset_control_assert(clk_info->clk_rst);
++
++	return 0;
++}
++
++static int sunxi_ahub_dam_resume(struct snd_soc_component *component)
++{
++	struct sunxi_ahub_clk_info *clk_info = &g_clk_info;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (reset_control_deassert(clk_info->clk_rst)) {
++		SND_LOG_ERR(HLOG, "clk rst deassert failed\n");
++		return -EINVAL;
++	}
++	if (clk_prepare_enable(clk_info->clk_bus)) {
++		SND_LOG_ERR(HLOG, "clk bus enable failed\n");
++		return -EBUSY;
++	}
++	if (clk_prepare_enable(clk_info->clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk_pll enable failed\n");
++		return -EBUSY;
++	}
++	//if (clk_prepare_enable(clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk_pllx4 enable failed\n");
++	//	return -EBUSY;
++	//}
++	if (clk_prepare_enable(clk_info->clk_module)) {
++		SND_LOG_ERR(HLOG, "clk_module enable failed\n");
++		return -EBUSY;
++	}
++
++	return 0;
++}
++
++struct str_conv {
++	char *str;
++	unsigned int reg;
++};
++static struct str_conv ahub_mux_name[] = {
++	{"APBIF0 Src Select",	SUNXI_AHUB_APBIF_RXFIFO_CONT(0)},
++	{"APBIF1 Src Select",	SUNXI_AHUB_APBIF_RXFIFO_CONT(1)},
++	{"APBIF2 Src Select",	SUNXI_AHUB_APBIF_RXFIFO_CONT(2)},
++	{"I2S0 Src Select",	SUNXI_AHUB_I2S_RXCONT(0)},
++	{"I2S1 Src Select",	SUNXI_AHUB_I2S_RXCONT(1)},
++	{"I2S2 Src Select",	SUNXI_AHUB_I2S_RXCONT(2)},
++	{"I2S3 Src Select",	SUNXI_AHUB_I2S_RXCONT(3)},
++	{"DAM0C0 Src Select",	SUNXI_AHUB_DAM_RX0_SRC(0)},
++	{"DAM0C1 Src Select",	SUNXI_AHUB_DAM_RX1_SRC(0)},
++	{"DAM0C2 Src Select",	SUNXI_AHUB_DAM_RX2_SRC(0)},
++	{"DAM1C0 Src Select",	SUNXI_AHUB_DAM_RX0_SRC(1)},
++	{"DAM1C1 Src Select",	SUNXI_AHUB_DAM_RX1_SRC(1)},
++	{"DAM1C2 Src Select",	SUNXI_AHUB_DAM_RX2_SRC(1)},
++};
++static const char *ahub_mux_text[] = {
++	"NONE",
++	"APBIF_TXDIF0",
++	"APBIF_TXDIF1",
++	"APBIF_TXDIF2",
++	"I2S0_TXDIF",
++	"I2S1_TXDIF",
++	"I2S2_TXDIF",
++	"I2S3_TXDIF",
++	"DAM0_TXDIF",
++	"DAM1_TXDIF",
++};
++static const unsigned int ahub_mux_values[] = {
++	0,
++	1 << I2S_RX_APBIF_TXDIF0,
++	1 << I2S_RX_APBIF_TXDIF1,
++	1 << I2S_RX_APBIF_TXDIF2,
++	1 << I2S_RX_I2S0_TXDIF,
++	1 << I2S_RX_I2S1_TXDIF,
++	1 << I2S_RX_I2S2_TXDIF,
++	1 << I2S_RX_I2S3_TXDIF,
++	1 << I2S_RX_DAM0_TXDIF,
++	1 << I2S_RX_DAM1_TXDIF,
++};
++static SOC_ENUM_SINGLE_EXT_DECL(ahub_mux, ahub_mux_text);
++
++static int sunxi_ahub_mux_get(struct snd_kcontrol *kcontrol,
++			      struct snd_ctl_elem_value *ucontrol)
++{
++	int i;
++	unsigned int reg_val;
++	unsigned int src_reg;
++	struct regmap *regmap = g_mem_info.regmap;
++
++	for (i = 0; i < ARRAY_SIZE(ahub_mux_name); i++) {
++		if (!strncmp(ahub_mux_name[i].str, kcontrol->id.name,
++			     strlen(ahub_mux_name[i].str))) {
++			src_reg = ahub_mux_name[i].reg;
++			regmap_read(regmap, src_reg, &reg_val);
++			reg_val &= 0xffffc000;
++			break;
++		}
++	}
++
++	for (i = 1; i < ARRAY_SIZE(ahub_mux_values); i++) {
++		if (reg_val & ahub_mux_values[i]) {
++			ucontrol->value.integer.value[0] = i;
++			return 0;
++		}
++	}
++	ucontrol->value.integer.value[0] = 0;
++
++	return 0;
++}
++
++static int sunxi_ahub_mux_set(struct snd_kcontrol *kcontrol,
++			      struct snd_ctl_elem_value *ucontrol)
++{
++	int i;
++	unsigned int src_reg, src_regbit;
++	struct regmap *regmap = g_mem_info.regmap;
++
++	if (ucontrol->value.integer.value[0] > ARRAY_SIZE(ahub_mux_name))
++		return -EINVAL;
++
++	src_regbit = ahub_mux_values[ucontrol->value.integer.value[0]];
++	for (i = 0; i < ARRAY_SIZE(ahub_mux_name); i++) {
++		if (!strncmp(ahub_mux_name[i].str, kcontrol->id.name,
++			     strlen(ahub_mux_name[i].str))) {
++			src_reg = ahub_mux_name[i].reg;
++			regmap_update_bits(regmap, src_reg, 0xffffc000, src_regbit);
++			break;
++		}
++	}
++
++	return 0;
++}
++
++static const struct snd_kcontrol_new sunxi_ahub_dam_controls[] = {
++	SOC_ENUM_EXT("APBIF0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("APBIF1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("APBIF2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S3 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM0C0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM0C1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM0C2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM1C0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM1C1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM1C2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++};
++
++static struct snd_soc_component_driver sunxi_ahub_dam_dev = {
++	.name		= DRV_NAME,
++	.probe		= sunxi_ahub_dam_probe,
++	.suspend	= sunxi_ahub_dam_suspend,
++	.resume		= sunxi_ahub_dam_resume,
++	.controls	= sunxi_ahub_dam_controls,
++	.num_controls	= ARRAY_SIZE(sunxi_ahub_dam_controls),
++};
++
++/*******************************************************************************
++ * for kernel source
++ ******************************************************************************/
++int snd_soc_sunxi_ahub_mem_get(struct sunxi_ahub_mem_info *mem_info)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (IS_ERR_OR_NULL(g_mem_info.regmap)) {
++		SND_LOG_ERR(HLOG, "regmap is invalid\n");
++		return -EINVAL;
++	}
++	if (IS_ERR_OR_NULL(g_mem_info.res)) {
++		SND_LOG_ERR(HLOG, "res is invalid\n");
++		return -EINVAL;
++	}
++
++	mem_info->regmap = g_mem_info.regmap;
++	mem_info->res = g_mem_info.res;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(snd_soc_sunxi_ahub_mem_get);
++
++int snd_soc_sunxi_ahub_clk_get(struct sunxi_ahub_clk_info *clk_info)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (IS_ERR_OR_NULL(g_clk_info.clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk_pll is invalid\n");
++		return -EINVAL;
++	}
++	//if (IS_ERR_OR_NULL(g_clk_info.clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk_pllx4 is invalid\n");
++	//	return -EINVAL;
++	//}
++	if (IS_ERR_OR_NULL(g_clk_info.clk_module)) {
++		SND_LOG_ERR(HLOG, "clk_module is invalid\n");
++		return -EINVAL;
++	}
++
++	clk_info->clk_pll = g_clk_info.clk_pll;
++	//clk_info->clk_pllx4 = g_clk_info.clk_pllx4;
++	clk_info->clk_module = g_clk_info.clk_module;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(snd_soc_sunxi_ahub_clk_get);
++
++static int snd_soc_sunxi_ahub_mem_init(struct platform_device *pdev,
++				       struct device_node *np,
++				       struct sunxi_ahub_mem_info *mem_info)
++{
++	int ret = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	ret = of_address_to_resource(np, 0, mem_info->res);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "parse device node resource failed\n");
++		ret = -EINVAL;
++		goto err_of_addr_to_resource;
++	}
++
++	mem_info->memregion = devm_request_mem_region(&pdev->dev,
++					mem_info->res->start,
++					resource_size(mem_info->res),
++					DRV_NAME);
++	if (IS_ERR_OR_NULL(mem_info->memregion)) {
++		SND_LOG_ERR(HLOG, "memory region already claimed\n");
++		ret = -EBUSY;
++		goto err_devm_request_region;
++	}
++
++	mem_info->membase = devm_ioremap(&pdev->dev,
++					 mem_info->memregion->start,
++					 resource_size(mem_info->memregion));
++	if (IS_ERR_OR_NULL(mem_info->membase)) {
++		SND_LOG_ERR(HLOG, "ioremap failed\n");
++		ret = -EBUSY;
++		goto err_devm_ioremap;
++	}
++
++	mem_info->regmap = devm_regmap_init_mmio(&pdev->dev,
++						 mem_info->membase,
++						 &g_regmap_config);
++	if (IS_ERR_OR_NULL(mem_info->regmap)) {
++		SND_LOG_ERR(HLOG, "regmap init failed\n");
++		ret = -EINVAL;
++		goto err_devm_regmap_init;
++	}
++
++	return 0;
++
++err_devm_regmap_init:
++	devm_iounmap(&pdev->dev, mem_info->membase);
++err_devm_ioremap:
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++err_devm_request_region:
++err_of_addr_to_resource:
++	return ret;
++};
++
++static int snd_soc_sunxi_ahub_clk_init(struct platform_device *pdev,
++				       struct device_node *np,
++				       struct sunxi_ahub_clk_info *clk_info)
++{
++	int ret = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	/* deassert rst clk */
++	clk_info->clk_rst = devm_reset_control_get(&pdev->dev, NULL);
++	if (IS_ERR_OR_NULL(clk_info->clk_rst)) {
++		SND_LOG_ERR(HLOG, "clk rst get failed\n");
++		ret = -EBUSY;
++		goto err_rst_clk;
++	}
++	if (reset_control_deassert(clk_info->clk_rst)) {
++		SND_LOG_ERR(HLOG, "deassert reset clk failed\n");
++		ret = -EBUSY;
++		goto err_rst_clk;
++	}
++
++	/* enable ahub bus clk */
++	clk_info->clk_bus = of_clk_get_by_name(np, "clk_bus_audio_hub");
++	if (IS_ERR_OR_NULL(clk_info->clk_bus)) {
++		SND_LOG_ERR(HLOG, "clk bus get failed\n");
++		ret = -EBUSY;
++		goto err_bus_clk;
++	}
++	if (clk_prepare_enable(clk_info->clk_bus)) {
++		SND_LOG_ERR(HLOG, "ahub clk bus enable failed\n");
++		ret = -EBUSY;
++		goto err_bus_clk;
++	}
++
++	/* get clk of ahub */
++	clk_info->clk_module = of_clk_get_by_name(np, "clk_audio_hub");
++	if (IS_ERR_OR_NULL(clk_info->clk_module)) {
++		SND_LOG_ERR(HLOG, "clk module get failed\n");
++		ret = -EBUSY;
++		goto err_module_clk;
++	}
++	clk_info->clk_pll = of_clk_get_by_name(np, "clk_pll_audio");
++	if (IS_ERR_OR_NULL(clk_info->clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk pll get failed\n");
++		ret = -EBUSY;
++		goto err_pll_clk;
++	}
++	//clk_info->clk_pllx4 = of_clk_get_by_name(np, "clk_pll_audio_4x");
++	//if (IS_ERR_OR_NULL(clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk pllx4 get failed\n");
++	//	ret = -EBUSY;
++	//	goto err_pllx4_clk;
++	//}
++
++	/* set ahub clk parent */
++	//if (clk_set_parent(clk_info->clk_module, clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "set parent of clk_module to pllx4 failed\n");
++	//	ret = -EINVAL;
++	//	goto err_set_parent_clk;
++	//}
++
++	/* enable clk of ahub */
++	if (clk_prepare_enable(clk_info->clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk_pll enable failed\n");
++		ret = -EBUSY;
++		goto err_pll_clk_enable;
++	}
++	//if (clk_prepare_enable(clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk_pllx4 enable failed\n");
++	//	ret = -EBUSY;
++	//	goto err_pllx4_clk_enable;
++	//}
++	if (clk_prepare_enable(clk_info->clk_module)) {
++		SND_LOG_ERR(HLOG, "clk_module enable failed\n");
++		ret = -EBUSY;
++		goto err_module_clk_enable;
++	}
++
++	return 0;
++
++err_module_clk_enable:
++//	clk_disable_unprepare(clk_info->clk_pllx4);
++//err_pllx4_clk_enable:
++	clk_disable_unprepare(clk_info->clk_pll);
++err_pll_clk_enable:
++//err_set_parent_clk:
++//	clk_put(clk_info->clk_pllx4);
++//err_pllx4_clk:
++//	clk_put(clk_info->clk_pll);
++err_pll_clk:
++	clk_put(clk_info->clk_module);
++err_module_clk:
++	clk_disable_unprepare(clk_info->clk_bus);
++	clk_put(clk_info->clk_bus);
++err_bus_clk:
++	reset_control_assert(clk_info->clk_rst);
++err_rst_clk:
++	return ret;
++}
++
++static int sunxi_ahub_dam_dev_probe(struct platform_device *pdev)
++{
++	int ret;
++	struct device_node *np = pdev->dev.of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	ret = snd_soc_sunxi_ahub_mem_init(pdev, np, &g_mem_info);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "remap init failed\n");
++		ret = -EINVAL;
++		goto err_snd_soc_sunxi_ahub_mem_init;
++	}
++
++	ret = snd_soc_sunxi_ahub_clk_init(pdev, np, &g_clk_info);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "clk init failed\n");
++		ret = -EINVAL;
++		goto err_snd_soc_sunxi_ahub_clk_init;
++	}
++
++	ret = snd_soc_register_component(&pdev->dev,
++					 &sunxi_ahub_dam_dev,
++					 &sunxi_ahub_dam_dai, 1);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "component register failed\n");
++		ret = -ENOMEM;
++		goto err_snd_soc_register_component;
++	}
++
++	SND_LOG_DEBUG(HLOG, "register ahub_dam platform success\n");
++
++	return 0;
++
++err_snd_soc_register_component:
++err_snd_soc_sunxi_ahub_clk_init:
++err_snd_soc_sunxi_ahub_mem_init:
++	of_node_put(np);
++	return ret;
++}
++
++static int sunxi_ahub_dam_dev_remove(struct platform_device *pdev)
++{
++	struct sunxi_ahub_mem_info *mem_info = &g_mem_info;
++	struct sunxi_ahub_clk_info *clk_info = &g_clk_info;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	snd_soc_unregister_component(&pdev->dev);
++
++	devm_iounmap(&pdev->dev, mem_info->membase);
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++
++	clk_disable_unprepare(clk_info->clk_module);
++	clk_put(clk_info->clk_module);
++	clk_disable_unprepare(clk_info->clk_pll);
++	clk_put(clk_info->clk_pll);
++	//clk_disable_unprepare(clk_info->clk_pllx4);
++	//clk_put(clk_info->clk_pllx4);
++	clk_disable_unprepare(clk_info->clk_bus);
++	clk_put(clk_info->clk_bus);
++	reset_control_assert(clk_info->clk_rst);
++
++	SND_LOG_DEBUG(HLOG, "unregister ahub_dam platform success\n");
++
++	return 0;
++}
++
++static const struct of_device_id sunxi_ahub_dam_of_match[] = {
++	{ .compatible = "allwinner," DRV_NAME, },
++	{},
++};
++MODULE_DEVICE_TABLE(of, sunxi_ahub_dam_of_match);
++
++static struct platform_driver sunxi_ahub_dam_driver = {
++	.driver	= {
++		.name		= DRV_NAME,
++		.owner		= THIS_MODULE,
++		.of_match_table	= sunxi_ahub_dam_of_match,
++	},
++	.probe	= sunxi_ahub_dam_dev_probe,
++	.remove	= sunxi_ahub_dam_dev_remove,
++};
++
++int __init sunxi_ahub_dam_dev_init(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&sunxi_ahub_dam_driver);
++	if (ret != 0) {
++		SND_LOG_ERR(HLOG, "platform driver register failed\n");
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
++void __exit sunxi_ahub_dam_dev_exit(void)
++{
++	platform_driver_unregister(&sunxi_ahub_dam_driver);
++}
++
++late_initcall(sunxi_ahub_dam_dev_init);
++module_exit(sunxi_ahub_dam_dev_exit);
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard platform of ahub_dam");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h
+new file mode 100644
+index 000000000000..b7679bf545e9
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h
+@@ -0,0 +1,291 @@
++/* sound\soc\sunxi\snd_sunxi_ahub_dam.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * some simple description for this code
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ */
++#ifndef __SND_SUNXI_AHUB_DAM_H
++#define __SND_SUNXI_AHUB_DAM_H
++
++/* SUNXI Audio Hub registers list */
++#define SUNXI_AHUB_CTL				0x00
++#define SUNXI_AHUB_VER				0x04
++#define SUNXI_AHUB_RST				0x08
++#define SUNXI_AHUB_GAT				0x0c
++
++#define SUNXI_AHUB_APBIF_TX_CTL(n)		(0x10 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TX_IRQ_CTL(n)		(0x14 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TX_IRQ_STA(n)		(0x18 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_TXFIFO_CTL(n)		(0x20 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TXFIFO_STA(n)		(0x24 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_TXFIFO(n)		(0x30 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TXFIFO_CNT(n)		(0x34 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_RX_CTL(n)		(0x100 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RX_IRQ_CTL(n)		(0x104 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RX_IRQ_STA(n)		(0x108 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_RXFIFO_CTL(n)		(0x110 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RXFIFO_STA(n)		(0x114 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RXFIFO_CONT(n)		(0x118 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_RXFIFO(n)		(0x120 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RXFIFO_CNT(n)		(0x124 + ((n) * 0x30))
++
++#define SUNXI_AHUB_I2S_CTL(n)			(0x200 + ((n) << 8))
++#define SUNXI_AHUB_I2S_FMT0(n)			(0x204 + ((n) << 8))
++#define SUNXI_AHUB_I2S_FMT1(n)			(0x208 + ((n) << 8))
++#define SUNXI_AHUB_I2S_CLKD(n)			(0x20c + ((n) << 8))
++
++#define SUNXI_AHUB_I2S_RXCONT(n)		(0x220 + ((n) << 8))
++#define SUNXI_AHUB_I2S_CHCFG(n)			(0x224 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IRQ_CTL(n)		(0x228 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IRQ_STA(n)		(0x22C + ((n) << 8))
++#define SUNXI_AHUB_I2S_OUT_SLOT(n, m)		(0x230 + ((n) << 8) + ((m) << 4))
++#define SUNXI_AHUB_I2S_OUT_CHMAP0(n, m)		(0x234 + ((n) << 8) + ((m) << 4))
++#define SUNXI_AHUB_I2S_OUT_CHMAP1(n, m)		(0x238 + ((n) << 8) + ((m) << 4))
++
++#define SUNXI_AHUB_I2S_IN_SLOT(n)		(0x270 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP0(n)		(0x274 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP1(n)		(0x278 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP2(n)		(0x27C + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP3(n)		(0x280 + ((n) << 8))
++
++#define SUNXI_AHUB_DAM_CTL(n)			(0xA00 + ((n) << 7))
++
++#define SUNXI_AHUB_DAM_RX0_SRC(n)		(0xA10 + ((n) << 7))
++#define SUNXI_AHUB_DAM_RX1_SRC(n)		(0xA14 + ((n) << 7))
++#define SUNXI_AHUB_DAM_RX2_SRC(n)		(0xA18 + ((n) << 7))
++
++#define SUNXI_AHUB_DAM_MIX_CTL0(n)		(0xA30 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL1(n)		(0xA34 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL2(n)		(0xA38 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL3(n)		(0xA3C + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL4(n)		(0xA40 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL5(n)		(0xA44 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL6(n)		(0xA48 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL7(n)		(0xA4C + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL0(n)		(0xA50 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL1(n)		(0xA54 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL2(n)		(0xA58 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL3(n)		(0xA5C + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL4(n)		(0xA60 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL5(n)		(0xA64 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL6(n)		(0xA68 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL7(n)		(0xA6C + ((n) << 7))
++
++#define SUNXI_AHUB_MAX_REG			SUNXI_AHUB_DAM_GAIN_CTL7(1)
++
++/* SUNXI_AHUB_CTL */
++#define HDMI_SRC_SEL			0x04
++
++/* SUNXI_AHUB_RST */
++#define APBIF_TXDIF0_RST		31
++#define APBIF_TXDIF1_RST		30
++#define APBIF_TXDIF2_RST		29
++#define APBIF_RXDIF0_RST		27
++#define APBIF_RXDIF1_RST		26
++#define APBIF_RXDIF2_RST		25
++#define I2S0_RST			23
++#define I2S1_RST			22
++#define I2S2_RST			21
++#define I2S3_RST			20
++#define DAM0_RST			15
++#define DAM1_RST			14
++
++/* SUNXI_AHUB_GAT */
++#define APBIF_TXDIF0_GAT		31
++#define APBIF_TXDIF1_GAT		30
++#define APBIF_TXDIF2_GAT		29
++#define APBIF_RXDIF0_GAT		27
++#define APBIF_RXDIF1_GAT		26
++#define APBIF_RXDIF2_GAT		25
++#define I2S0_GAT			23
++#define I2S1_GAT			22
++#define I2S2_GAT			21
++#define I2S3_GAT			20
++#define DAM0_GAT			15
++#define DAM1_GAT			14
++
++/* SUNXI_AHUB_APBIF_TX_CTL */
++#define APBIF_TX_WS			16
++#define APBIF_TX_CHAN_NUM		8
++#define	APBIF_TX_START			4
++
++/* SUNXI_AHUB_APBIF_TX_IRQ_CTL */
++#define APBIF_TX_DRQ			3
++#define APBIF_TX_OVEN			1
++#define APBIF_TX_EMEN			0
++
++/* SUNXI_AHUB_APBIF_TX_IRQ_STA */
++#define APBIF_TX_OV_PEND		2
++#define APBIF_TX_EM_PEND		0
++
++/* SUNXI_AHUB_APBIF_TXFIFO_CTL */
++#define APBIF_TX_FTX			12
++#define APBIF_TX_LEVEL			4
++#define APBIF_TX_TXIM			0
++
++/* SUNXI_AHUB_APBIF_TXFIFO_STA */
++#define APBIF_TX_EMPTY			8
++#define APBIF_TX_EMCNT			0
++
++/* SUNXI_AHUB_APBIF_RX_CTL */
++#define APBIF_RX_WS			16
++#define APBIF_RX_CHAN_NUM		8
++#define	APBIF_RX_START			4
++
++/* SUNXI_AHUB_APBIF_RX_IRQ_CTL */
++#define APBIF_RX_DRQ			3
++#define APBIF_RX_UVEN			2
++#define APBIF_RX_AVEN			0
++
++/* SUNXI_AHUB_APBIF_RX_IRQ_STA */
++#define APBIF_RX_UV_PEND		2
++#define APBIF_RX_AV_PEND		0
++
++/* SUNXI_AHUB_APBIF_RXFIFO_CTL */
++#define APBIF_RX_FRX			12
++#define APBIF_RX_LEVEL			4
++#define APBIF_RX_RXOM			0
++
++/* SUNXI_AHUB_APBIF_RXFIFO_STA */
++#define APBIF_RX_AVAIL			8
++#define APBIF_RX_AVCNT			0
++
++/* SUNXI_AHUB_APBIF_RXFIFO_CONT */
++#define APBIF_RX_APBIF_TXDIF0		31
++#define APBIF_RX_APBIF_TXDIF1		30
++#define APBIF_RX_APBIF_TXDIF2		29
++#define APBIF_RX_I2S0_TXDIF		27
++#define APBIF_RX_I2S1_TXDIF		26
++#define APBIF_RX_I2S2_TXDIF		25
++#define APBIF_RX_I2S3_TXDIF		23
++#define APBIF_RX_DAM0_TXDIF		19
++#define APBIF_RX_DAM1_TXDIF		15
++
++/* SUNXI_AHUB_I2S_CTL */
++#define I2S_CTL_LOOP3			23
++#define I2S_CTL_LOOP2			22
++#define I2S_CTL_LOOP1			21
++#define I2S_CTL_LOOP0			20
++#define I2S_CTL_SDI3_EN			15
++#define I2S_CTL_SDI2_EN			14
++#define I2S_CTL_SDI1_EN			13
++#define I2S_CTL_SDI0_EN			12
++#define I2S_CTL_CLK_OUT			18
++#define I2S_CTL_SDO3_EN			11
++#define I2S_CTL_SDO2_EN			10
++#define I2S_CTL_SDO1_EN			9
++#define I2S_CTL_SDO0_EN			8
++#define I2S_CTL_OUT_MUTE		6
++#define I2S_CTL_MODE			4
++#define I2S_CTL_TXEN			2
++#define I2S_CTL_RXEN			1
++#define I2S_CTL_GEN			0
++
++/* SUNXI_AHUB_I2S_FMT0 */
++#define I2S_FMT0_LRCK_WIDTH		30
++#define I2S_FMT0_LRCK_POLARITY		19
++#define I2S_FMT0_LRCK_PERIOD		8
++#define I2S_FMT0_BCLK_POLARITY		7
++#define I2S_FMT0_SR			4
++#define I2S_FMT0_EDGE			3
++#define I2S_FMT0_SW			0
++
++/* SUNXI_AHUB_I2S_FMT1 */
++#define I2S_FMT1_RX_LSB			7
++#define I2S_FMT1_TX_LSB			6
++#define I2S_FMT1_EXT			4
++#define I2S_FMT1_RX_PDM			2
++#define I2S_FMT1_TX_PDM			0
++
++/* SUNXI_AHUB_I2S_CLKD */
++#define I2S_CLKD_MCLK			8
++#define	I2S_CLKD_BCLKDIV		4
++#define I2S_CLKD_MCLKDIV		0
++
++/* SUNXI_AHUB_I2S_RXCONT */
++#define I2S_RX_APBIF_TXDIF0		31
++#define I2S_RX_APBIF_TXDIF1		30
++#define I2S_RX_APBIF_TXDIF2		29
++#define I2S_RX_I2S0_TXDIF		27
++#define I2S_RX_I2S1_TXDIF		26
++#define I2S_RX_I2S2_TXDIF		25
++#define I2S_RX_I2S3_TXDIF		23
++#define I2S_RX_DAM0_TXDIF		19
++#define I2S_RX_DAM1_TXDIF		15
++
++/* SUNXI_AHUB_I2S_CHCFG */
++#define I2S_CHCFG_HIZ			9
++#define	I2S_CHCFG_TX_STATE		8
++#define I2S_CHCFG_RX_CHANNUM		4
++#define I2S_CHCFG_TX_CHANNUM		0
++
++/* SUNXI_AHUB_I2S_IRQ_CTL */
++#define I2S_IRQ_RXOV_EN			1
++#define I2S_IRQ_TXUV_EN			0
++
++/* SUNXI_AHUB_I2S_IRQ_STA */
++#define I2S_IRQ_RXOV_PEND		1
++#define I2S_IRQ_TXUV_PEND		0
++
++/* SUNXI_AHUB_I2S_OUT_SLOT */
++#define I2S_OUT_OFFSET			20
++#define I2S_OUT_SLOT_NUM		16
++#define I2S_OUT_SLOT_EN			0
++
++/* SUNXI_AHUB_I2S_IN_SLOT */
++#define I2S_IN_OFFSET			20
++#define I2S_IN_SLOT_NUM			16
++
++/* SUNXI_AHUB_DAM_CTL */
++#define DAM_CTL_RX2_NUM			24
++#define DAM_CTL_RX1_NUM			20
++#define DAM_CTL_RX0_NUM			16
++#define DAM_CTL_TX_NUM			8
++#define DAM_CTL_RX2EN			6
++#define DAM_CTL_RX1EN			5
++#define DAM_CTL_RX0EN			4
++#define DAM_CTL_TXEN			0
++
++/* SUNXI_AHUB_DAM_RX##chan##_SRC */
++#define DAM_RX_APBIF_TXDIF0		31
++#define DAM_RX_APBIF_TXDIF1		30
++#define DAM_RX_APBIF_TXDIF2		29
++#define DAM_RX_I2S0_TXDIF		27
++#define DAM_RX_I2S1_TXDIF		26
++#define DAM_RX_I2S2_TXDIF		25
++#define DAM_RX_I2S3_TXDIF		23
++#define DAM_RX_DAM0_TXDIF		19
++#define DAM_RX_DAM1_TXDIF		15
++
++struct sunxi_ahub_mem_info {
++	char *dev_name;
++	struct resource *res;
++	void __iomem *membase;
++	struct resource *memregion;
++	struct regmap *regmap;
++};
++
++struct sunxi_ahub_clk_info {
++	struct clk *clk_pll;
++	struct clk *clk_pllx4;
++	struct clk *clk_module;
++	struct clk *clk_bus;
++	struct reset_control *clk_rst;
++};
++
++extern int snd_soc_sunxi_ahub_mem_get(struct sunxi_ahub_mem_info *mem_info);
++extern int snd_soc_sunxi_ahub_clk_get(struct sunxi_ahub_clk_info *clk_info);
++
++#endif /* __SND_SUNXI_AHUB_DAM_H */
+\ No newline at end of file
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_common.c b/sound/soc/sunxi_v2/snd_sunxi_common.c
+new file mode 100644
+index 000000000000..410ab75aea5a
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_common.c
+@@ -0,0 +1,267 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_common.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/device.h>
++#include <linux/ioport.h>
++#include <linux/regmap.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_common.h"
++
++#define HLOG		"COMMON"
++
++/* for regmap */
++int snd_sunxi_mem_init(struct platform_device *pdev,
++		       struct sunxi_mem_info *mem_info)
++{
++	int ret = 0;
++	struct device_node *np = pdev->dev.of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	ret = of_address_to_resource(np, 0, mem_info->res);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "parse device node resource failed\n");
++		ret = -EINVAL;
++		goto err_of_addr_to_resource;
++	}
++
++	mem_info->memregion = devm_request_mem_region(&pdev->dev,
++					mem_info->res->start,
++					resource_size(mem_info->res),
++					mem_info->dev_name);
++	if (IS_ERR_OR_NULL(mem_info->memregion)) {
++		SND_LOG_ERR(HLOG, "memory region already claimed\n");
++		ret = -EBUSY;
++		goto err_devm_request_region;
++	}
++
++	mem_info->membase = devm_ioremap(&pdev->dev,
++					 mem_info->memregion->start,
++					 resource_size(mem_info->memregion));
++	if (IS_ERR_OR_NULL(mem_info->membase)) {
++		SND_LOG_ERR(HLOG, "ioremap failed\n");
++		ret = -EBUSY;
++		goto err_devm_ioremap;
++	}
++
++	mem_info->regmap = devm_regmap_init_mmio(&pdev->dev,
++						 mem_info->membase,
++						 mem_info->regmap_config);
++	if (IS_ERR_OR_NULL(mem_info->regmap)) {
++		SND_LOG_ERR(HLOG, "regmap init failed\n");
++		ret = -EINVAL;
++		goto err_devm_regmap_init;
++	}
++
++	return 0;
++
++err_devm_regmap_init:
++	devm_iounmap(&pdev->dev, mem_info->membase);
++err_devm_ioremap:
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++err_devm_request_region:
++err_of_addr_to_resource:
++	return ret;
++}
++
++void snd_sunxi_mem_exit(struct platform_device *pdev,
++			struct sunxi_mem_info *mem_info)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	devm_iounmap(&pdev->dev, mem_info->membase);
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++}
++
++/* for reg labels */
++int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels)
++{
++	int i = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	while (reg_labels[i].name != NULL) {
++		regmap_read(regmap,
++			    reg_labels[i].address, &(reg_labels[i].value));
++		i++;
++	}
++
++	return i;
++}
++
++int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels)
++{
++	int i = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	while (reg_labels[i].name != NULL) {
++		regmap_write(regmap,
++			     reg_labels[i].address, reg_labels[i].value);
++		i++;
++	}
++
++	return i;
++}
++
++/* for pa config */
++struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev,
++					u32 *pa_pin_max)
++{
++	int ret, i;
++	u32 pin_max;
++	u32 gpio_tmp;
++	u32 temp_val;
++	char str[20] = {0};
++	struct pa_config *pa_cfg;
++	struct device_node *np = pdev->dev.of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	*pa_pin_max = 0;
++	ret = of_property_read_u32(np, "pa_pin_max", &temp_val);
++	if (ret < 0) {
++		SND_LOG_WARN(HLOG, "pa_pin_max get failed, default 0\n");
++		return NULL;
++	} else {
++		pin_max = temp_val;
++	}
++
++	pa_cfg = kzalloc(sizeof(struct pa_config) * pin_max, GFP_KERNEL);
++	if (!pa_cfg) {
++		SND_LOG_ERR(HLOG, "can't pa_config memory\n");
++		return NULL;
++	}
++
++	for (i = 0; i < pin_max; i++) {
++		sprintf(str, "pa_pin_%d", i);
++		ret = of_get_named_gpio(np, str, 0);
++		if (ret < 0) {
++			SND_LOG_ERR(HLOG, "pa_pin_%u get failed\n", i);
++			pa_cfg[i].used = 0;
++			continue;
++		}
++		gpio_tmp = ret;
++		if (!gpio_is_valid(gpio_tmp)) {
++			SND_LOG_ERR(HLOG, "pa_pin_%u (%u) is invalid\n",
++				    i, gpio_tmp);
++			pa_cfg[i].used = 0;
++			continue;
++		}
++		ret = devm_gpio_request(&pdev->dev, gpio_tmp, str);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "pa_pin_%u (%u) request failed\n",
++				    i, gpio_tmp);
++			pa_cfg[i].used = 0;
++			continue;
++		}
++		pa_cfg[i].used = 1;
++		pa_cfg[i].pin = gpio_tmp;
++
++		sprintf(str, "pa_pin_level_%d", i);
++		ret = of_property_read_u32(np, str, &temp_val);
++		if (ret < 0) {
++			SND_LOG_WARN(HLOG, "%s get failed, default low\n", str);
++			pa_cfg[i].level = 0;
++		} else {
++			if (temp_val > 0)
++				pa_cfg[i].level = 1;
++		}
++		sprintf(str, "pa_pin_msleep_%d", i);
++		ret = of_property_read_u32(np, str, &temp_val);
++		if (ret < 0) {
++			SND_LOG_WARN(HLOG, "%s get failed, default 0\n", str);
++			pa_cfg[i].msleep = 0;
++		} else {
++			pa_cfg[i].msleep = temp_val;
++		}
++	}
++
++	*pa_pin_max = pin_max;
++	snd_sunxi_pa_pin_disable(pa_cfg, pin_max);
++
++	return pa_cfg;
++}
++
++void snd_sunxi_pa_pin_exit(struct platform_device *pdev,
++			   struct pa_config *pa_cfg, u32 pa_pin_max)
++{
++	int i;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	snd_sunxi_pa_pin_disable(pa_cfg, pa_pin_max);
++
++	for (i = 0; i < pa_pin_max; i++) {
++		if (!pa_cfg[i].used)
++			continue;
++
++		gpio_free(pa_cfg[i].pin);
++	}
++
++	if (pa_cfg)
++		kfree(pa_cfg);
++}
++
++int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max)
++{
++	int i;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (pa_pin_max < 1) {
++		SND_LOG_DEBUG(HLOG, "no pa pin config\n");
++		return 0;
++	}
++
++	for (i = 0; i < pa_pin_max; i++) {
++		if (!pa_cfg[i].used)
++			continue;
++
++		gpio_direction_output(pa_cfg[i].pin, 1);
++		gpio_set_value(pa_cfg[i].pin, pa_cfg[i].level);
++	}
++
++	return 0;
++}
++
++void snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max)
++{
++	int i;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (pa_pin_max < 1) {
++		SND_LOG_DEBUG(HLOG, "no pa pin config\n");
++		return;
++	}
++
++	for (i = 0; i < pa_pin_max; i++) {
++		if (!pa_cfg[i].used)
++			continue;
++
++		gpio_direction_output(pa_cfg[i].pin, 1);
++		gpio_set_value(pa_cfg[i].pin, !pa_cfg[i].level);
++	}
++}
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_common.h b/sound/soc/sunxi_v2/snd_sunxi_common.h
+new file mode 100644
+index 000000000000..7b88d20c25e0
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_common.h
+@@ -0,0 +1,67 @@
++/* sound\soc\sunxi\snd_sunxi_common.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_COMMON_H
++#define __SND_SUNXI_COMMON_H
++
++/* for regmap */
++struct sunxi_mem_info {
++	char *dev_name;
++	struct resource *res;
++	struct regmap_config *regmap_config;
++
++	void __iomem *membase;
++	struct resource *memregion;
++	struct regmap *regmap;
++};
++
++int snd_sunxi_mem_init(struct platform_device *pdev,
++		       struct sunxi_mem_info *mem_info);
++void snd_sunxi_mem_exit(struct platform_device *pdev,
++			struct sunxi_mem_info *mem_info);
++
++/* for reg debug */
++#define REG_LABEL(constant)	{#constant, constant, 0}
++#define REG_LABEL_END		{NULL, 0, 0}
++
++struct reg_label {
++	const char *name;
++	const unsigned int address;
++	unsigned int value;
++};
++
++/* EX:
++ * static struct reg_label reg_labels[] = {
++ * 	REG_LABEL(SUNXI_REG_0),
++ * 	REG_LABEL(SUNXI_REG_1),
++ * 	REG_LABEL(SUNXI_REG_n),
++ * 	REG_LABEL_END,
++ * };
++ */
++int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels);
++int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels);
++
++/* for pa config */
++struct pa_config {
++	u32 pin;
++	u32 msleep;
++	bool used;
++	bool level;
++};
++
++struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev,
++					u32 *pa_pin_max);
++void snd_sunxi_pa_pin_exit(struct platform_device *pdev,
++			   struct pa_config *pa_cfg, u32 pa_pin_max);
++int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max);
++void snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max);
++
++#endif /* __SND_SUNXI_COMMON_H */
+\ No newline at end of file
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_log.h b/sound/soc/sunxi_v2/snd_sunxi_log.h
+new file mode 100644
+index 000000000000..89ad9fe71936
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_log.h
+@@ -0,0 +1,29 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_log.h
++ * (C) Copyright 2021-2025
++ * allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_LOG_H
++#define __SND_SUNXI_LOG_H
++#include <linux/kernel.h>
++
++#define SND_LOG_ERR(head, fmt, arg...) \
++	pr_err("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#define SND_LOG_WARN(head, fmt, arg...) \
++	pr_warn("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#define SND_LOG_INFO(head, fmt, arg...) \
++	pr_info("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#define SND_LOG_DEBUG(head, fmt, arg...) \
++	pr_debug("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#endif /* __SND_SUNXI_LOG_H */
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach.c b/sound/soc/sunxi_v2/snd_sunxi_mach.c
+new file mode 100644
+index 000000000000..27449ad6b843
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach.c
+@@ -0,0 +1,479 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_mach.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * based on ${LINUX}/sound/soc/generic/simple-card.c
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <sound/soc.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_mach.h"
++
++#define HLOG		"MACH"
++#define DAI		"sound-dai"
++#define CELL		"#sound-dai-cells"
++#define PREFIX		"soundcard-mach,"
++
++#define DRV_NAME	"sunxi-snd-mach"
++
++static void asoc_simple_shutdown(struct snd_pcm_substream *substream)
++{
++}
++
++static int asoc_simple_startup(struct snd_pcm_substream *substream)
++{
++	return 0;
++}
++
++static int asoc_simple_hw_params(struct snd_pcm_substream *substream,
++				 struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++
++	struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
++	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
++
++	struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card);
++	struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, rtd->num);
++	struct simple_dai_props *dai_props = simple_priv_to_props(priv, rtd->num);
++	struct asoc_simple_dai *dais = priv->dais;
++	unsigned int mclk;
++	unsigned int cpu_pll_clk, codec_pll_clk;
++	unsigned int cpu_bclk_ratio, codec_bclk_ratio;
++	unsigned int freq_point;
++	int cpu_clk_div, codec_clk_div;
++	int ret = 0;
++
++	switch (params_rate(params)) {
++	case 8000:
++	case 12000:
++	case 16000:
++	case 24000:
++	case 32000:
++	case 48000:
++	case 64000:
++	case 96000:
++	case 192000:
++		freq_point = 24576000;
++		break;
++	case 11025:
++	case 22050:
++	case 44100:
++	case 88200:
++	case 176400:
++		freq_point = 22579200;
++		break;
++	default:
++		SND_LOG_ERR(HLOG, "Invalid rate %d\n", params_rate(params));
++		return -EINVAL;
++	}
++
++	/* for cpudai pll clk */
++	cpu_pll_clk	= freq_point * dai_props->cpu_pll_fs;
++	codec_pll_clk	= freq_point * dai_props->codec_pll_fs;
++	cpu_clk_div	= cpu_pll_clk / params_rate(params);
++	codec_clk_div	= codec_pll_clk / params_rate(params);
++	SND_LOG_DEBUG(HLOG, "freq point   : %u\n", freq_point);
++	SND_LOG_DEBUG(HLOG, "cpu pllclk   : %u\n", cpu_pll_clk);
++	SND_LOG_DEBUG(HLOG, "codec pllclk : %u\n", codec_pll_clk);
++	SND_LOG_DEBUG(HLOG, "cpu clk_div  : %u\n", cpu_clk_div);
++	SND_LOG_DEBUG(HLOG, "codec clk_div: %u\n", codec_clk_div);
++
++	if (cpu_dai->driver->ops->set_pll) {
++		ret = snd_soc_dai_set_pll(cpu_dai, substream->stream, 0,
++					  cpu_pll_clk, cpu_pll_clk);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set pllclk failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_pll) {
++		ret = snd_soc_dai_set_pll(codec_dai, substream->stream, 0,
++					  codec_pll_clk, codec_pll_clk);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec_dai set pllclk failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_clkdiv) {
++		ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, cpu_clk_div);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set clk_div failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_clkdiv) {
++		ret = snd_soc_dai_set_clkdiv(codec_dai, 0, codec_clk_div);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cadec_dai set clk_div failed.\n");
++			return ret;
++		}
++	}
++
++	/* use for tdm only */
++	if (!(dais->slots && dais->slot_width))
++		return 0;
++
++	/* for cpudai & codecdai mclk */
++	if (dai_props->mclk_fp)
++		mclk = (freq_point >> 1) * dai_props->mclk_fs;
++	else
++		mclk = params_rate(params) * dai_props->mclk_fs;
++	cpu_bclk_ratio = cpu_pll_clk / (params_rate(params) * dais->slot_width * dais->slots);
++	codec_bclk_ratio = codec_pll_clk / (params_rate(params) * dais->slot_width * dais->slots);
++	SND_LOG_DEBUG(HLOG, "mclk            : %u\n", mclk);
++	SND_LOG_DEBUG(HLOG, "cpu_bclk_ratio  : %u\n", cpu_bclk_ratio);
++	SND_LOG_DEBUG(HLOG, "codec_bclk_ratio: %u\n", codec_bclk_ratio);
++
++	if (cpu_dai->driver->ops->set_sysclk) {
++		ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk, SND_SOC_CLOCK_OUT);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set sysclk(mclk) failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_sysclk) {
++		ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk, SND_SOC_CLOCK_IN);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cadec_dai set sysclk(mclk) failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_bclk_ratio) {
++		ret = snd_soc_dai_set_bclk_ratio(cpu_dai, cpu_bclk_ratio);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set bclk failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_bclk_ratio) {
++		ret = snd_soc_dai_set_bclk_ratio(codec_dai, codec_bclk_ratio);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec_dai set bclk failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_fmt) {
++		ret = snd_soc_dai_set_fmt(cpu_dai, dai_link->dai_fmt);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu dai set fmt failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_fmt) {
++		ret = snd_soc_dai_set_fmt(codec_dai, dai_link->dai_fmt);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec dai set fmt failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_tdm_slot) {
++		ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 0, dais->slots, dais->slot_width);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu dai set tdm slot failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_tdm_slot) {
++		ret = snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, dais->slots, dais->slot_width);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec dai set tdm slot failed\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static struct snd_soc_ops simple_ops = {
++	.startup = asoc_simple_startup,
++	.shutdown = asoc_simple_shutdown,
++	.hw_params = asoc_simple_hw_params,
++};
++
++static int asoc_simple_dai_init(struct snd_soc_pcm_runtime *rtd)
++{
++	int i;
++	struct snd_soc_card *card = rtd->card;
++	struct snd_soc_dapm_context *dapm = &card->dapm;
++
++	const struct snd_kcontrol_new *controls = card->controls;
++
++	for (i = 0; i < card->num_controls; i++)
++		if (controls[i].info == snd_soc_dapm_info_pin_switch)
++			snd_soc_dapm_disable_pin(dapm,
++				(const char *)controls[i].private_value);
++
++	if (card->num_controls)
++		snd_soc_dapm_sync(dapm);
++
++	/* snd_soc_dai_set_sysclk(); */
++	/* snd_soc_dai_set_tdm_slot(); */
++
++	return 0;
++}
++
++static int simple_dai_link_of(struct device_node *node,
++			      struct asoc_simple_priv *priv)
++{
++	struct device *dev = simple_priv_to_dev(priv);
++	struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, 0);
++	struct simple_dai_props *dai_props = simple_priv_to_props(priv, 0);
++	struct device_node *top_np = NULL;
++	struct device_node *cpu = NULL;
++	struct device_node *plat = NULL;
++	struct device_node *codec = NULL;
++	char prop[128];
++	char *prefix = "";
++	int ret, single_cpu;
++
++	prefix = PREFIX;
++	top_np = node;
++
++	snprintf(prop, sizeof(prop), "%scpu", prefix);
++	cpu = of_get_child_by_name(top_np, prop);
++	if (!cpu) {
++		ret = -EINVAL;
++		SND_LOG_ERR(HLOG, "Can't find %s DT node\n", prop);
++		goto dai_link_of_err;
++	}
++	snprintf(prop, sizeof(prop), "%splat", prefix);
++	plat = of_get_child_by_name(top_np, prop);
++
++	snprintf(prop, sizeof(prop), "%scodec", prefix);
++	codec = of_get_child_by_name(top_np, prop);
++	if (!codec) {
++		ret = -EINVAL;
++		SND_LOG_ERR(HLOG, "Can't find %s DT node\n", prop);
++		goto dai_link_of_err;
++	}
++
++	ret = asoc_simple_parse_daifmt(top_np, codec, prefix, &dai_link->dai_fmt);
++	if (ret < 0)
++		goto dai_link_of_err;
++	/* sunxi: parse stream direction
++	 * ex1)
++	 * top_node {
++	 *	PREFIXplayback-only;
++	 * }
++	 * ex2)
++	 * top_node {
++	 *	PREFIXcapture-only;
++	 * }
++	 */
++	ret = asoc_simple_parse_daistream(top_np, prefix, dai_link);
++	if (ret < 0)
++		goto dai_link_of_err;
++	/* sunxi: parse slot-num & slot-width
++	 * ex)
++	 * top_node {
++	 *	PREFIXplayslot-num	= <x>;
++	 *	PREFIXplayslot-width	= <x>;
++	 * }
++	 */
++	ret = asoc_simple_parse_tdm_slot(top_np, prefix, priv->dais);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	ret = asoc_simple_parse_cpu(cpu, dai_link, DAI, CELL, &single_cpu);
++	if (ret < 0)
++		goto dai_link_of_err;
++	ret = asoc_simple_parse_codec(codec, dai_link, DAI, CELL);
++	if (ret < 0) {
++		if (ret == -EPROBE_DEFER)
++			goto dai_link_of_err;
++		dai_link->codecs->name = "snd-soc-dummy";
++		dai_link->codecs->dai_name = "snd-soc-dummy-dai";
++		/* dai_link->codecs->name = "sunxi-dummy-codec"; */
++		/* dai_link->codecs->dai_name = "sunxi-dummy-codec-dai"; */
++		SND_LOG_DEBUG(HLOG, "use dummy codec for simple card.\n");
++	}
++	ret = asoc_simple_parse_platform(plat, dai_link, DAI, CELL);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	/* sunxi: parse pll-fs & mclk-fs
++	 * ex)
++	 * top_node {
++	 *	PREFIXcpu {
++	 *		PREFIXpll-fs	= <x>;
++	 *		PREFIXmclk-fs	= <x>;
++	 *	}
++	 * }
++	 */
++	ret = asoc_simple_parse_tdm_clk(cpu, codec, prefix, dai_props);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	ret = asoc_simple_set_dailink_name(dev, dai_link,
++					   "%s-%s",
++					   dai_link->cpus->dai_name,
++					   dai_link->codecs->dai_name);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	dai_link->ops = &simple_ops;
++	dai_link->init = asoc_simple_dai_init;
++
++	SND_LOG_DEBUG(HLOG, "name   : %s\n", dai_link->stream_name);
++	SND_LOG_DEBUG(HLOG, "format : %x\n", dai_link->dai_fmt);
++	SND_LOG_DEBUG(HLOG, "cpu    : %s\n", dai_link->cpus->name);
++	SND_LOG_DEBUG(HLOG, "codec  : %s\n", dai_link->codecs->name);
++
++	asoc_simple_canonicalize_cpu(dai_link, single_cpu);
++	asoc_simple_canonicalize_platform(dai_link);
++
++dai_link_of_err:
++	of_node_put(cpu);
++	of_node_put(plat);
++	of_node_put(codec);
++
++	return ret;
++}
++
++static int simple_parse_of(struct asoc_simple_priv *priv)
++{
++	int ret;
++	struct device *dev = simple_priv_to_dev(priv);
++	struct snd_soc_card *card = simple_priv_to_card(priv);
++	struct device_node *top_np = dev->of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (!top_np)
++		return -EINVAL;
++
++	/* DAPM widgets */
++	ret = asoc_simple_parse_widgets(card, PREFIX);
++	if (ret < 0)
++		return ret;
++
++	/* DAPM routes */
++	ret = asoc_simple_parse_routing(card, PREFIX);
++	if (ret < 0)
++		return ret;
++
++	/* DAPM pin_switches */
++	ret = asoc_simple_parse_pin_switches(card, PREFIX);
++	if (ret < 0)
++		return ret;
++
++	/* For single DAI link & old style of DT node */
++	ret = simple_dai_link_of(top_np, priv);
++	if (ret < 0)
++		return ret;
++
++	ret = asoc_simple_parse_card_name(card, PREFIX);
++	return ret;
++}
++
++static int simple_soc_probe(struct snd_soc_card *card)
++{
++	return 0;
++}
++
++static int asoc_simple_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *top_np = dev->of_node;
++	struct asoc_simple_priv *priv;
++	struct snd_soc_card *card;
++	int ret;
++
++	/* Allocate the private data and the DAI link array */
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	card = simple_priv_to_card(priv);
++	card->owner		= THIS_MODULE;
++	card->dev		= dev;
++	card->probe		= simple_soc_probe;
++
++	ret = asoc_simple_init_priv(priv);
++	if (ret < 0)
++		return ret;
++
++	if (top_np && of_device_is_available(top_np)) {
++		ret = simple_parse_of(priv);
++		if (ret < 0) {
++			if (ret != -EPROBE_DEFER)
++				SND_LOG_ERR(HLOG, "parse error %d\n", ret);
++			goto err;
++		}
++	} else {
++		SND_LOG_ERR(HLOG, "simple card dts available\n");
++	}
++
++	snd_soc_card_set_drvdata(card, priv);
++
++	/* asoc_simple_debug_info(priv); */
++	ret = devm_snd_soc_register_card(dev, card);
++	if (ret >= 0)
++		return ret;
++err:
++	asoc_simple_clean_reference(card);
++
++	return ret;
++}
++
++static int asoc_simple_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++	return asoc_simple_clean_reference(card);
++}
++
++static const struct of_device_id snd_soc_sunxi_of_match[] = {
++	{ .compatible = "allwinner," DRV_NAME, },
++	{},
++};
++MODULE_DEVICE_TABLE(of, snd_soc_sunxi_of_match);
++
++static struct platform_driver sunxi_soundcard_machine_driver = {
++	.driver	= {
++		.name		= DRV_NAME,
++		.pm		= &snd_soc_pm_ops,
++		.of_match_table	= snd_soc_sunxi_of_match,
++	},
++	.probe	= asoc_simple_probe,
++	.remove	= asoc_simple_remove,
++};
++
++int __init sunxi_soundcard_machine_dev_init(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&sunxi_soundcard_machine_driver);
++	if (ret != 0) {
++		SND_LOG_ERR(HLOG, "platform driver register failed\n");
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
++void __exit sunxi_soundcard_machine_dev_exit(void)
++{
++	platform_driver_unregister(&sunxi_soundcard_machine_driver);
++}
++
++late_initcall(sunxi_soundcard_machine_dev_init);
++module_exit(sunxi_soundcard_machine_dev_exit);
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard machine");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach.h b/sound/soc/sunxi_v2/snd_sunxi_mach.h
+new file mode 100644
+index 000000000000..ab429c8841ab
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach.h
+@@ -0,0 +1,17 @@
++/* sound\soc\sunxi\snd_sunxi_mach.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_MACH_H
++#define __SND_SUNXI_MACH_H
++
++#include "snd_sunxi_mach_utils.h"
++
++#endif /* __SND_SUNXI_MACH_H */
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c
+new file mode 100644
+index 000000000000..15f474e5cbeb
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c
+@@ -0,0 +1,422 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_mach_utils.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * based on ${LINUX}/sound/soc/generic/simple-card.c
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <sound/soc.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_mach_utils.h"
++
++#define HLOG           "mach_utils"
++
++int asoc_simple_clean_reference(struct snd_soc_card *card)
++{
++       struct snd_soc_dai_link *dai_link;
++       int i;
++
++       for_each_card_prelinks(card, i, dai_link) {
++               of_node_put(dai_link->cpus->of_node);
++               of_node_put(dai_link->codecs->of_node);
++       }
++       return 0;
++}
++
++int asoc_simple_init_priv(struct asoc_simple_priv *priv)
++{
++       struct snd_soc_card *card = simple_priv_to_card(priv);
++       struct device *dev = simple_priv_to_dev(priv);
++       struct snd_soc_dai_link *dai_link;
++       struct simple_dai_props *dai_props;
++       struct asoc_simple_dai *dais;
++       struct snd_soc_codec_conf *cconf = NULL;
++
++       dai_props = devm_kcalloc(dev, 1, sizeof(*dai_props), GFP_KERNEL);
++       dai_link  = devm_kcalloc(dev, 1, sizeof(*dai_link),  GFP_KERNEL);
++       dais      = devm_kcalloc(dev, 1, sizeof(*dais),      GFP_KERNEL);
++       if (!dai_props || !dai_link || !dais)
++               return -ENOMEM;
++
++       /*
++       if (li->conf) {
++               cconf = devm_kcalloc(dev, li->conf, sizeof(*cconf), GFP_KERNEL);
++               if (!cconf)
++                       return -ENOMEM;
++       }
++       */
++
++       /*
++        * Use snd_soc_dai_link_component instead of legacy style
++        * It is codec only. but cpu/platform will be supported in the future.
++        * see
++        *      soc-core.c :: snd_soc_init_multicodec()
++        *
++        * "platform" might be removed
++        * see
++        *      simple-card-utils.c :: asoc_simple_canonicalize_platform()
++        */
++       dai_link->cpus          = &dai_props->cpus;
++       dai_link->num_cpus      = 1;
++       dai_link->codecs        = &dai_props->codecs;
++       dai_link->num_codecs    = 1;
++       dai_link->platforms     = &dai_props->platforms;
++       dai_link->num_platforms = 1;
++
++       priv->dai_props         = dai_props;
++       priv->dai_link          = dai_link;
++       priv->dais              = dais;
++       priv->codec_conf        = cconf;
++
++       card->dai_link          = priv->dai_link;
++       card->num_links         = 1;
++       card->codec_conf        = cconf;
++       card->num_configs       = 0;
++
++       return 0;
++}
++
++int asoc_simple_parse_widgets(struct snd_soc_card *card, char *prefix)
++{
++       struct device_node *node = card->dev->of_node;
++       char prop[128];
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%s%s", prefix, "widgets");
++
++       if (of_property_read_bool(node, prop))
++               return snd_soc_of_parse_audio_simple_widgets(card, prop);
++
++       /* no widgets is not error */
++       return 0;
++}
++
++int asoc_simple_parse_routing(struct snd_soc_card *card, char *prefix)
++{
++       struct device_node *node = card->dev->of_node;
++       char prop[128];
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%s%s", prefix, "routing");
++
++       if (!of_property_read_bool(node, prop))
++               return 0;
++
++       return snd_soc_of_parse_audio_routing(card, prop);
++}
++
++int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix)
++{
++       const unsigned int nb_controls_max = 16;
++       const char **strings, *control_name;
++       struct snd_kcontrol_new *controls;
++       struct device *dev = card->dev;
++       unsigned int i, nb_controls;
++       char prop[128];
++       int ret;
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%s%s", prefix, "pin-switches");
++
++       if (!of_property_read_bool(dev->of_node, prop))
++               return 0;
++
++       strings = devm_kcalloc(dev, nb_controls_max,
++                              sizeof(*strings), GFP_KERNEL);
++       if (!strings)
++               return -ENOMEM;
++
++       ret = of_property_read_string_array(dev->of_node, prop,
++                                           strings, nb_controls_max);
++       if (ret < 0)
++               return ret;
++
++       nb_controls = (unsigned int)ret;
++
++       controls = devm_kcalloc(dev, nb_controls,
++                               sizeof(*controls), GFP_KERNEL);
++       if (!controls)
++               return -ENOMEM;
++
++       for (i = 0; i < nb_controls; i++) {
++               control_name = devm_kasprintf(dev, GFP_KERNEL,
++                                             "%s Switch", strings[i]);
++               if (!control_name)
++                       return -ENOMEM;
++
++               controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
++               controls[i].name = control_name;
++               controls[i].info = snd_soc_dapm_info_pin_switch;
++               controls[i].get = snd_soc_dapm_get_pin_switch;
++               controls[i].put = snd_soc_dapm_put_pin_switch;
++               controls[i].private_value = (unsigned long)strings[i];
++       }
++
++       card->controls = controls;
++       card->num_controls = nb_controls;
++
++       return 0;
++}
++
++int asoc_simple_parse_daifmt(struct device_node *node,
++                            struct device_node *codec,
++                            char *prefix,
++                            unsigned int *retfmt)
++{
++       struct device_node *bitclkmaster = NULL;
++       struct device_node *framemaster = NULL;
++       unsigned int daifmt;
++
++       daifmt = snd_soc_daifmt_parse_format(node, prefix);
++
++       snd_soc_daifmt_parse_clock_provider_as_phandle(node, prefix, &bitclkmaster, &framemaster);
++       if (!bitclkmaster && !framemaster) {
++               /*
++                * No dai-link level and master setting was not found from
++                * sound node level, revert back to legacy DT parsing and
++                * take the settings from codec node.
++                */
++               SND_LOG_DEBUG(HLOG, "Revert to legacy daifmt parsing\n");
++
++               daifmt |= snd_soc_daifmt_parse_clock_provider_as_flag(codec, NULL);
++       } else {
++               daifmt |= snd_soc_daifmt_clock_provider_from_bitmap(
++                       ((codec == bitclkmaster) << 4) | (codec == framemaster));
++       }
++
++       of_node_put(bitclkmaster);
++       of_node_put(framemaster);
++
++       *retfmt = daifmt;
++
++       return 0;
++}
++
++int asoc_simple_parse_daistream(struct device_node *node, char *prefix,
++                               struct snd_soc_dai_link *dai_link)
++{
++       char prop[128];
++
++       if (!prefix)
++               prefix = "";
++
++       /* check "[prefix]playback-only" */
++       snprintf(prop, sizeof(prop), "%splayback-only", prefix);
++       if (of_property_read_bool(node, prop))
++               dai_link->playback_only = 1;
++
++       /* check "[prefix]capture-only" */
++       snprintf(prop, sizeof(prop), "%scapture-only", prefix);
++       if (of_property_read_bool(node, prop))
++               dai_link->capture_only = 1;
++
++       return 0;
++}
++
++int asoc_simple_parse_tdm_slot(struct device_node *node, char *prefix,
++                              struct asoc_simple_dai *dais)
++{
++       int ret;
++       char prop[128];
++       unsigned int val;
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%sslot-num", prefix);
++       ret = of_property_read_u32(node, prop, &val);
++       if (!ret)
++               dais->slots = val;
++
++       snprintf(prop, sizeof(prop), "%sslot-width", prefix);
++       ret = of_property_read_u32(node, prop, &val);
++       if (!ret)
++               dais->slot_width = val;
++
++       return 0;
++}
++
++int asoc_simple_parse_tdm_clk(struct device_node *cpu,
++                             struct device_node *codec,
++                             char *prefix,
++                             struct simple_dai_props *dai_props)
++{
++       int ret;
++       char prop[128];
++       unsigned int val;
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%spll-fs", prefix);
++       ret = of_property_read_u32(cpu, prop, &val);
++       if (ret)
++               dai_props->cpu_pll_fs = 1;      /* default sysclk 24.576 or 22.5792MHz * 1 */
++       else
++               dai_props->cpu_pll_fs = val;
++
++       ret = of_property_read_u32(codec, prop, &val);
++       if (ret)
++               dai_props->codec_pll_fs = 1;    /* default sysclk 24.576 or 22.5792MHz * 1 */
++       else
++               dai_props->codec_pll_fs = val;
++
++       snprintf(prop, sizeof(prop), "%smclk-fp", prefix);
++       dai_props->mclk_fp = of_property_read_bool(cpu, prop);
++
++       snprintf(prop, sizeof(prop), "%smclk-fs", prefix);
++       ret = of_property_read_u32(cpu, prop, &val);
++       if (ret)
++               dai_props->mclk_fs = 0;         /* default mclk 0Hz(un output) */
++       else
++               dai_props->mclk_fs = val;
++
++       return 0;
++}
++
++int asoc_simple_parse_card_name(struct snd_soc_card *card,
++                               char *prefix)
++{
++       int ret;
++
++       if (!prefix)
++               prefix = "";
++
++       /* Parse the card name from DT */
++       ret = snd_soc_of_parse_card_name(card, "label");
++       if (ret < 0 || !card->name) {
++               char prop[128];
++
++               snprintf(prop, sizeof(prop), "%sname", prefix);
++               ret = snd_soc_of_parse_card_name(card, prop);
++               if (ret < 0)
++                       return ret;
++       }
++
++       if (!card->name && card->dai_link)
++               card->name = card->dai_link->name;
++
++       return 0;
++}
++
++int asoc_simple_parse_dai(struct device_node *node,
++                         struct snd_soc_dai_link_component *dlc,
++                         const char *list_name, const char *cells_name,
++                         int *is_single_link)
++{
++       struct of_phandle_args args;
++       int ret;
++
++       if (!node)
++               return 0;
++
++       /*
++        * Get node via "sound-dai = <&phandle port>"
++        * it will be used as xxx_of_node on soc_bind_dai_link()
++        */
++       ret = of_parse_phandle_with_args(node, list_name, cells_name, 0, &args);
++       if (ret)
++               return ret;
++
++       /*
++        * FIXME
++        *
++        * Here, dlc->dai_name is pointer to CPU/Codec DAI name.
++        * If user unbinded CPU or Codec driver, but not for Sound Card,
++        * dlc->dai_name is keeping unbinded CPU or Codec
++        * driver's pointer.
++        *
++        * If user re-bind CPU or Codec driver again, ALSA SoC will try
++        * to rebind Card via snd_soc_try_rebind_card(), but because of
++        * above reason, it might can't bind Sound Card.
++        * Because Sound Card is pointing to released dai_name pointer.
++        *
++        * To avoid this rebind Card issue,
++        * 1) It needs to alloc memory to keep dai_name eventhough
++        *    CPU or Codec driver was unbinded, or
++        * 2) user need to rebind Sound Card everytime
++        *    if he unbinded CPU or Codec.
++        */
++       ret = snd_soc_of_get_dai_name(node, &dlc->dai_name, 0);
++       if (ret < 0)
++               return ret;
++
++       dlc->of_node = args.np;
++
++       if (is_single_link)
++               *is_single_link = !args.args_count;
++
++       return 0;
++}
++
++int asoc_simple_set_dailink_name(struct device *dev,
++                                struct snd_soc_dai_link *dai_link,
++                                const char *fmt, ...)
++{
++       va_list ap;
++       char *name = NULL;
++       int ret = -ENOMEM;
++
++       va_start(ap, fmt);
++       name = devm_kvasprintf(dev, GFP_KERNEL, fmt, ap);
++       va_end(ap);
++
++       if (name) {
++               ret = 0;
++
++               dai_link->name          = name;
++               dai_link->stream_name   = name;
++       }
++
++       return ret;
++}
++
++void asoc_simple_canonicalize_platform(struct snd_soc_dai_link *dai_link)
++{
++       /* Assumes platform == cpu */
++       if (!dai_link->platforms->of_node)
++               dai_link->platforms->of_node = dai_link->cpus->of_node;
++
++       /*
++        * DPCM BE can be no platform.
++        * Alloced memory will be waste, but not leak.
++        */
++       if (!dai_link->platforms->of_node)
++               dai_link->num_platforms = 0;
++}
++
++void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link *dai_link,
++                                 int is_single_links)
++{
++       /*
++        * In soc_bind_dai_link() will check cpu name after
++        * of_node matching if dai_link has cpu_dai_name.
++        * but, it will never match if name was created by
++        * fmt_single_name() remove cpu_dai_name if cpu_args
++        * was 0. See:
++        *      fmt_single_name()
++        *      fmt_multiple_name()
++        */
++       if (is_single_links)
++               dai_link->cpus->dai_name = NULL;
++}
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard machine utils");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h
+new file mode 100644
+index 000000000000..a9cffa0d859b
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h
+@@ -0,0 +1,116 @@
++/* sound\soc\sunxi\snd_sunxi_mach_utils.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_MACH_UTILS_H
++#define __SND_SUNXI_MACH_UTILS_H
++
++#define simple_priv_to_card(priv)      (&(priv)->snd_card)
++#define simple_priv_to_props(priv, i)  ((priv)->dai_props + (i))
++#define simple_priv_to_dev(priv)       (simple_priv_to_card(priv)->dev)
++#define simple_priv_to_link(priv, i)   (simple_priv_to_card(priv)->dai_link + (i))
++
++#define asoc_simple_parse_cpu(node, dai_link,                          \
++                             list_name, cells_name, is_single_link)    \
++       asoc_simple_parse_dai(node, dai_link->cpus,                     \
++                             list_name, cells_name, is_single_link)
++
++#define asoc_simple_parse_codec(node, dai_link,                                \
++                               list_name, cells_name)                  \
++       asoc_simple_parse_dai(node, dai_link->codecs,                   \
++                             list_name, cells_name, NULL)
++
++#define asoc_simple_parse_platform(node, dai_link,                     \
++                                  list_name, cells_name)               \
++       asoc_simple_parse_dai(node, dai_link->platforms,                \
++                             list_name, cells_name, NULL)
++
++struct asoc_simple_dai {
++       const char *name;
++       unsigned int sysclk;
++       int clk_direction;
++       int slots;
++       int slot_width;
++       unsigned int tx_slot_mask;
++       unsigned int rx_slot_mask;
++       struct clk *clk;
++};
++
++struct asoc_simple_data {
++       u32 convert_rate;
++       u32 convert_channels;
++};
++
++struct asoc_simple_jack {
++       struct snd_soc_jack jack;
++       struct snd_soc_jack_pin pin;
++       struct snd_soc_jack_gpio gpio;
++};
++
++struct asoc_simple_priv {
++       struct snd_soc_card snd_card;
++       struct simple_dai_props {
++               struct asoc_simple_dai *cpu_dai;
++               struct asoc_simple_dai *codec_dai;
++               struct snd_soc_dai_link_component cpus;   /* single cpu */
++               struct snd_soc_dai_link_component codecs; /* single codec */
++               struct snd_soc_dai_link_component platforms;
++               struct asoc_simple_data adata;
++               struct snd_soc_codec_conf *codec_conf;
++               bool mclk_fp;
++               unsigned int mclk_fs;
++               unsigned int cpu_pll_fs;
++               unsigned int codec_pll_fs;
++       } *dai_props;
++       struct asoc_simple_jack hp_jack;
++       struct asoc_simple_jack mic_jack;
++       struct snd_soc_dai_link *dai_link;
++       struct asoc_simple_dai *dais;
++       struct snd_soc_codec_conf *codec_conf;
++       struct gpio_desc *pa_gpio;
++};
++
++int asoc_simple_clean_reference(struct snd_soc_card *card);
++int asoc_simple_init_priv(struct asoc_simple_priv *priv);
++
++int asoc_simple_parse_widgets(struct snd_soc_card *card, char *prefix);
++int asoc_simple_parse_routing(struct snd_soc_card *card, char *prefix);
++int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix);
++
++int asoc_simple_parse_daistream(struct device_node *node,
++                               char *prefix,
++                               struct snd_soc_dai_link *dai_link);
++int asoc_simple_parse_daifmt(struct device_node *node,
++                            struct device_node *codec,
++                            char *prefix,
++                            unsigned int *retfmt);
++int asoc_simple_parse_tdm_slot(struct device_node *node,
++                              char *prefix,
++                              struct asoc_simple_dai *dais);
++int asoc_simple_parse_tdm_clk(struct device_node *cpu,
++                             struct device_node *codec,
++                             char *prefix,
++                             struct simple_dai_props *dai_props);
++
++int asoc_simple_parse_card_name(struct snd_soc_card *card, char *prefix);
++int asoc_simple_parse_dai(struct device_node *node,
++                         struct snd_soc_dai_link_component *dlc,
++                         const char *list_name,
++                         const char *cells_name,
++                         int *is_single_link);
++
++int asoc_simple_set_dailink_name(struct device *dev,
++                                struct snd_soc_dai_link *dai_link,
++                                const char *fmt, ...);
++void asoc_simple_canonicalize_platform(struct snd_soc_dai_link *dai_link);
++void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link *dai_link,
++                                 int is_single_links);
++
++#endif /* __SND_SUNXI_MACH_UTILS_H */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch
new file mode 100644
index 000000000000..6a325ccca38f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch
@@ -0,0 +1,53 @@
+From 760f10718c0d69ebfccd155e5353ac5bf730d1e6 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Mon, 26 Jun 2023 14:29:56 +0000
+Subject: Temp_fix mailbox
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 67c4ecff7150..33d83ec887b1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -42,7 +42,7 @@ bat: battery {
+                 resistance-temp-table = <20 150>;
+                 ocv-capacity-celsius = <20>;
+                 ocv-capacity-table-0 =
+-                	<4334000 100>,
++			<4334000 100>,
+ 			<4319700 99>,
+ 			<4304300 98>,
+ 			<4292200 97>,
+@@ -144,7 +144,7 @@ bat: battery {
+ 			<3393500 1>,
+ 			<3256000 0>;
+                 x-powers,ocv-capacity-table =
+-                	<0xc0 0>,
++			<0xc0 0>,
+ 			<0xc1 1>,
+ 			<0xc2 1>,
+ 			<0xc3 2>,
+@@ -191,7 +191,7 @@ ppkb_battery: keyboard-battery {
+                 factory-internal-resistance-micro-ohms = <120000>;
+                 ocv-capacity-celsius = <20>;
+                 ocv-capacity-table-0 =
+-                	<4147328 100>,
++			<4147328 100>,
+ 			<4132636 99>,
+ 			<4121720 98>,
+ 			<4110905 97>,
+@@ -749,6 +749,7 @@ &mmc1 {
+ 	non-removable;
+ 	post-power-on-delay-ms = <1>; /* wifi power is always on */
+ 	status = "okay";
++	keep-power-in-suspend;
+ 
+ 	rtl8723cs: wifi@1 {
+ 		reg = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/add-bigtreetech-cb1-dts.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/add-bigtreetech-cb1-dts.patch
new file mode 100644
index 000000000000..a9a7840807fa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/add-bigtreetech-cb1-dts.patch
@@ -0,0 +1,455 @@
+From bbd85618d5e4ba7921e3ac2b648a137d48004022 Mon Sep 17 00:00:00 2001
+From: Your Name <you@example.com>
+Date: Tue, 30 May 2023 10:18:55 +0800
+Subject: add bigtreetech-cb1 dts
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   2 +
+ .../sun50i-h616-bigtreetech-cb1-emmc.dts      |  44 +++
+ .../sun50i-h616-bigtreetech-cb1-sd.dts        |  35 ++
+ .../sun50i-h616-bigtreetech-cb1.dtsi          | 327 ++++++++++++++++++
+ 4 files changed, 408 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 4d4d2e5c01f2..74a6e5e0d7b3 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -50,6 +50,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
+ 
+ subdir-y	:= $(dts-dirs) overlay
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+new file mode 100644
+index 000000000000..f878c23f1d90
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+@@ -0,0 +1,44 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Copyright (C) 2023 Alan.Ma <tech@biqu3d.com>.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616-bigtreetech-cb1.dtsi"
++
++&mmc2 {
++	vmmc-supply = <&reg_dldo1>;
++
++	no-1-8-v;
++	bus-width = <8>;
++	non-removable;
++	status = "okay";
++};
++
++&ws2812 {
++	gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
++};
++
++&i2c_gpio {
++	gpios = <&pio 8 6 GPIO_ACTIVE_HIGH>, /* SDA PI6 */
++			<&pio 8 4 GPIO_ACTIVE_HIGH>; /* SCL PI4 */
++};
++
++&can0_pin_irq {
++	pins = "PI3";
++};
++
++&can {
++	interrupts = <8 3 0x08>; /* PI3 IRQ_TYPE_LEVEL_LOW */
++};
++
++&tft_35 {
++	dc-gpios  = <&pio 8 15 GPIO_ACTIVE_HIGH>; /* PI15 */
++};
++
++&spi1 {
++	cs-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>, /* PI5 */
++			   <&pio 8 14 GPIO_ACTIVE_HIGH>, /* PI14 */
++			   <&pio 8 7 GPIO_ACTIVE_HIGH>; /* PI7 */
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+new file mode 100644
+index 000000000000..e18dd854d74b
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+@@ -0,0 +1,35 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Copyright (C) 2023 Alan.Ma <tech@biqu3d.com>.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616-bigtreetech-cb1.dtsi"
++
++&ws2812 {
++	gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */
++};
++
++&i2c_gpio {
++	gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>, /* SDA PC12 */
++			<&pio 2 10 GPIO_ACTIVE_HIGH>; /* SCL PC10 */
++};
++
++&can0_pin_irq {
++	pins = "PC9";
++};
++
++&can {
++	interrupts = <2 9 0x08>; /* PC9 IRQ_TYPE_LEVEL_LOW */
++};
++
++&tft_35 {
++	dc-gpios  = <&pio 2 14 GPIO_ACTIVE_HIGH>; /* PC14 */
++};
++
++&spi1 {
++	cs-gpios = <&pio 2 11 GPIO_ACTIVE_HIGH>, /* PC11 */
++			   <&pio 2 7 GPIO_ACTIVE_HIGH>, /* PC7 */
++			   <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+new file mode 100644
+index 000000000000..e82da4b6e340
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+@@ -0,0 +1,327 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Copyright (C) 2023 Alan.Ma <tech@biqu3d.com>.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "BigTreeTech CB1";
++	compatible = "bigtreetech,cb1", "allwinner,sun50i-h616";
++
++	aliases {
++		ethernet0 = &emac1;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		act_led: led-0 {
++			gpios = <&pio 7 5 GPIO_ACTIVE_LOW>; /* PH5 */
++			linux,default-trigger = "heartbeat";
++		};
++
++		gpio_1 {
++			function = "wifi_power";
++			gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++			default-state = "on";
++		};
++
++		gpio_2 {
++			function = "wifi_wake";
++			gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
++			default-state = "on";
++		};
++	};
++
++	reg_vcc5v: regulator-vcc5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_usb1_vbus: regulator-usb1-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb1-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&reg_vcc5v>;
++		enable-active-high;
++	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc5v>;
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>;  /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
++
++	ws2812: ws2812 {
++		compatible = "rgb-ws2812";
++		pinctrl-names = "default";
++		rgb_cnt = <2>;
++		rgb_value = <0x010000 0x010000>;
++		status = "disabled";
++	};
++
++	i2c_gpio: i2c-gpio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++
++		i2c-gpio,delay-us = <3>; /* 100 kHz */
++
++		tft_tp: ns2009@48 {
++			compatible = "ti,tsc2007";
++			reg = <0x48>;
++			status = "disabled";
++			ti,x-plate-ohms = <660>;
++			ti,rt-thr = <3000>;
++			ti,fuzzx = <32>;
++			ti,fuzzy = <16>;
++			i2c,ignore-nak = <1>;
++		};
++
++		light: bh1750@5c {
++			compatible = "rohm,bh1750";
++			reg = <0x5c>;
++			status = "disabled";
++		};
++	};
++
++	mcp2515_clock: mcp2515_clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency  = <12000000>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_dldo1>;
++	broken-cd;
++	bus-width = <4>;
++	max-frequency = <50000000>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	max-frequency = <25000000>;
++	non-removable;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
++&pio {
++	can0_pin_irq: can0_pin_irq {
++		function = "irq";
++		bias-pull-up;
++	};
++};
++
++&spi1 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	status = "disabled";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins>;
++
++	can: mcp2515@0 {
++		status = "disabled";
++		compatible = "microchip,mcp2515";
++		reg = <0x0>;
++		clocks = <&mcp2515_clock>;
++		spi-max-frequency = <12500000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&can0_pin_irq>;
++		interrupt-parent = <&pio>;
++		vdd-supply = <&reg_vcc33_wifi>;
++		xceiver-supply = <&reg_vcc33_wifi>;
++	};
++
++	tft_35: st7789v@1 {
++		status = "disabled";
++		compatible = "sitronix,st7796s";
++		reg = <1>;
++		spi-max-frequency =<12500000>;
++		fps =<60>;
++		buswidth = <8>;
++		rotate =<0>;
++		width = <480>;
++		height = <320>;
++		bpp = <24>;
++		bgr;
++		regwidth = <8>;
++		debug = <0x00>;	 //0x20 show fps
++		txbuflen = <307200>;
++		spi-cpol;
++		spi-cpha;
++	};
++};
++
++&r_i2c {
++	status = "okay";
++
++	axp313a: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		wakeup-source;
++
++		regulators{
++			reg_dcdc1: dcdc1 {
++				regulator-name = "axp313a-dcdc1";
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <3400000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-name = "axp313a-dcdc2";
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1540000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-ramp-delay = <200>;
++				regulator-always-on;
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-name = "axp313a-dcdc3";
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1840000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_aldo1: aldo1 {
++				regulator-name = "axp313a-aldo1";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_dldo1: dldo1 {
++				regulator-name = "axp313a-dldo1";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++		};
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc3>;
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_usb1_vbus>;
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&usbotg {
++	/*
++	 * PHY0 pins are connected to a USB-C socket, but a role switch
++	 * is not implemented: both CC pins are pulled to GND.
++	 * The VBUS pins power the device, so a fixed peripheral mode
++	 * is the best choice.
++	 * The board can be powered via GPIOs, in this case port0 *can*
++	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
++	 * then provided by the GPIOs. Any user of this setup would
++	 * need to adjust the DT accordingly: dr_mode set to "host",
++	 * enabling OHCI0 and EHCI0.
++	 */
++	dr_mode = "peripheral";
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/add-dtb-overlay-for-zero2w.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/add-dtb-overlay-for-zero2w.patch
new file mode 100644
index 000000000000..29a9d3c35d43
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/add-dtb-overlay-for-zero2w.patch
@@ -0,0 +1,215 @@
+From ee00f965c88e0a4a5f158b6eafb5fe2e5ce12c71 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Fri, 5 Apr 2024 10:57:18 +0800
+Subject: add dtb overlay for zero2w
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile | 16 ++++++++-----
+ .../allwinner/overlay/sun50i-h616-gpu.dtso    | 14 +++++++++++
+ .../overlay/sun50i-h616-i2c0-pi.dtso          | 23 +++++++++++++++++++
+ .../overlay/sun50i-h616-i2c1-pi.dtso          | 16 +++++++++++++
+ ...616-i2c2.dtso => sun50i-h616-i2c2-ph.dtso} |  0
+ .../overlay/sun50i-h616-i2c2-pi.dtso          | 23 +++++++++++++++++++
+ ...616-i2c3.dtso => sun50i-h616-i2c3-ph.dtso} |  0
+ ...616-i2c4.dtso => sun50i-h616-i2c4-ph.dtso} |  0
+ ...6-uart2.dtso => sun50i-h616-uart2-ph.dtso} |  0
+ ...6-uart5.dtso => sun50i-h616-uart5-ph.dtso} |  0
+ .../allwinner/sun50i-h618-orangepi-zero2w.dts | 12 ----------
+ 11 files changed, 86 insertions(+), 18 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso
+ rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-i2c2.dtso => sun50i-h616-i2c2-ph.dtso} (100%)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso
+ rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-i2c3.dtso => sun50i-h616-i2c3-ph.dtso} (100%)
+ rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-i2c4.dtso => sun50i-h616-i2c4-ph.dtso} (100%)
+ rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-uart2.dtso => sun50i-h616-uart2-ph.dtso} (100%)
+ rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-uart5.dtso => sun50i-h616-uart5-ph.dtso} (100%)
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 369b2976b1bb..24383cb63770 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -49,11 +49,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-uart2.dtbo \
+ 	sun50i-h6-uart3.dtbo \
+ 	sun50i-h6-w1-gpio.dtbo \
+-	sun50i-h616-i2c2.dtbo \
+-	sun50i-h616-i2c3.dtbo \
+-	sun50i-h616-i2c4.dtbo \
+-	sun50i-h616-uart2.dtbo \
+-	sun50i-h616-uart5.dtbo \
++	sun50i-h616-i2c2-ph.dtbo \
++	sun50i-h616-i2c3-ph.dtbo \
++	sun50i-h616-i2c4-ph.dtbo \
++	sun50i-h616-uart2-ph.dtbo \
++	sun50i-h616-uart5-ph.dtbo \
+ 	sun50i-h616-spi-spidev.dtbo \
+ 	sun50i-h616-spidev0_0.dtbo \
+ 	sun50i-h616-spidev1_0.dtbo \
+@@ -63,7 +63,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h616-tft35_spi.dtbo \
+ 	sun50i-h616-mcp2515.dtbo \
+ 	sun50i-h616-ws2812.dtbo \
+-	sun50i-h616-light.dtbo
++	sun50i-h616-light.dtbo \
++	sun50i-h616-i2c0-pi.dtbo \
++	sun50i-h616-i2c1-pi.dtbo \
++	sun50i-h616-i2c2-pi.dtbo \
++	sun50i-h616-gpu.dtbo
+ 
+ scr-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-a64-fixup.scr \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso
+new file mode 100644
+index 000000000000..ac8846ac7d27
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso
+@@ -0,0 +1,14 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&gpu>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso
+new file mode 100644
+index 000000000000..b5003934c895
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c0_pi_pins>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart2>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso
+new file mode 100644
+index 000000000000..05f3100967ff
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso
+@@ -0,0 +1,16 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pi_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso
+similarity index 100%
+rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso
+rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso
+new file mode 100644
+index 000000000000..0f7d7e9968d6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_pi_pins>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart3>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso
+similarity index 100%
+rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso
+rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso
+similarity index 100%
+rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso
+rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso
+similarity index 100%
+rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso
+rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5-ph.dtso
+similarity index 100%
+rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5-ph.dtso
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+index b224902f5684..2a4c152b9294 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+@@ -312,12 +312,6 @@ &uart4 {
+ 	status = "disabled";
+ };
+ 
+-&uart5 {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&uart5_ph_pins>;
+-	status = "disabled";
+-};
+-
+ &i2c3 {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+@@ -447,12 +441,6 @@ uart4_pi_pins: uart4-pi-pins {
+ 		function = "uart4";
+ 	};
+ 
+-	/omit-if-no-ref/
+-	uart5_ph_pins: uart5-ph-pins {
+-		pins = "PH2", "PH3";
+-		function = "uart5";
+-	};
+-
+ 	/omit-if-no-ref/
+ 	spi1_cs1_pin: spi1-cs1-pin {
+ 		pins = "PH9";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch
new file mode 100644
index 000000000000..8beb4a58c909
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch
@@ -0,0 +1,73 @@
+From be6241b48636a739722e573d1dbb6f5c7856afc7 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 16 Apr 2022 11:51:35 +0300
+Subject: add nodes for sunxi-info, sunxi-addr and sunxi-dump-reg
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 19 +++++++++++++++++++
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 19 +++++++++++++++++++
+ 2 files changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 926b3f568c0d..d01c5c72ff86 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -1242,6 +1242,25 @@ ths: thermal-sensor@5070400 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <1>;
+ 		};
++
++		sunxi-info {
++			compatible = "allwinner,sun50i-h6-sys-info";
++			status = "okay";
++		};
++
++		addr_mgt: addr-mgt {
++			compatible = "allwinner,sunxi-addr_mgt";
++			type_addr_wifi = <0x2>;
++			type_addr_bt = <0x2>;
++			type_addr_eth = <0x2>;
++			status = "okay";
++		};
++
++		dump_reg: dump_reg@20000 {
++			compatible = "allwinner,sunxi-dump-reg";
++			reg = <0x0 0x03001000 0x0 0x0f20>;
++			status = "okay";
++		};
+ 	};
+ 
+ 	thermal-zones {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 6ba83df33652..de2a736f0e33 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -854,6 +854,25 @@ ths: thermal-sensor@5070400 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <1>;
+ 		};
++
++		dump_reg: dump_reg@20000 {
++			compatible = "allwinner,sunxi-dump-reg";
++			reg = <0x0 0x03001000 0x0 0x0f20>;
++			status = "okay";
++		};
++
++		sunxi-info {
++			compatible = "allwinner,sun50i-h616-sys-info";
++			status = "okay";
++		};
++
++		addr_mgt: addr-mgt {
++			compatible = "allwinner,sunxi-addr_mgt";
++			type_addr_wifi = <0x2>;
++			type_addr_bt = <0x2>;
++			type_addr_eth = <0x2>;
++			status = "okay";
++		};
+ 	};
+ 
+ 	thermal-zones {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/adding-dummy-regulators-in-pinctr-arch-arm-boot-dts-allwinner-s.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/adding-dummy-regulators-in-pinctr-arch-arm-boot-dts-allwinner-s.patch
new file mode 100644
index 000000000000..64c7a871193d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/adding-dummy-regulators-in-pinctr-arch-arm-boot-dts-allwinner-s.patch
@@ -0,0 +1,29 @@
+From 63dbe7a62208a8721dcf82efad59f7996a156890 Mon Sep 17 00:00:00 2001
+From: Stephen Graf <stephen.graf@gmail.com>
+Date: Thu, 30 May 2024 18:19:07 -0700
+Subject: adding dummy regulators in pinctr
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+
+Signed-off-by: Stephen Graf <stephen.graf@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index 927fd1bab07d..1aee01494ada 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -209,3 +209,10 @@ &usbphy {
+ 	usb0_vbus-supply = <&reg_usb0_vbus>;
+ 	status = "okay";
+ };
++
++&pio {
++        vcc-pa-supply = <&reg_vcc3v3>;
++        vcc-pc-supply = <&reg_vcc3v3>;
++        vcc-pd-supply = <&reg_vcc3v3>;
++        vcc-pg-supply = <&reg_vcc3v3>;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch
new file mode 100644
index 000000000000..46c976c3742d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch
@@ -0,0 +1,39 @@
+From b05628be187259b61b73f3f20a117e1fdd0c6221 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Thu, 22 Feb 2024 19:31:11 -0500
+Subject: arch: arm64: dts: allwinner: sun50i-h616: PG 12c pins
+
+pins = "PG17", "PG18";
+pins = "PG15", "PG16";
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index ccaca20eb10b..345d941f3e76 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -334,6 +334,18 @@ i2c4_ph_pins: i2c4-ph-pins {
+ 				function = "i2c4";
+ 			};
+ 
++			/omit-if-no-ref/
++			i2c3_pg_pins: i2c3-pg-pins {
++				pins = "PG17", "PG18";
++				function = "i2c3";
++			};
++
++			/omit-if-no-ref/
++			i2c4_pg_pins: i2c4-pg-pins {
++				pins = "PG15", "PG16";
++				function = "i2c4";
++			};
++
+ 			ir_rx_pin: ir-rx-pin {
+ 				pins = "PH10";
+ 				function = "ir_rx";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch
new file mode 100644
index 000000000000..5d4af3adc429
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch
@@ -0,0 +1,30 @@
+From 6b4b39bd1f85161ff9a8e932871e33555eca6e3d Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Wed, 6 Mar 2024 06:51:01 -0500
+Subject: arch: arm64: dts: allwinner: sun50i-h616: spi1 cs1 pin
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 345d941f3e76..90e55a6aef1d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -407,6 +407,12 @@ spi1_cs0_pin: spi1-cs0-pin {
+ 				function = "spi1";
+ 			};
+ 
++			/omit-if-no-ref/
++			spi1_cs1_pin: spi1-cs1-pin {
++				pins = "PH9";
++				function = "spi1";
++			};
++
+ 			uart0_ph_pins: uart0-ph-pins {
+ 				pins = "PH0", "PH1";
+ 				function = "uart0";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arch-arm64-dts-allwinner-sun50i-h618-bananapi-m4-zero.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arch-arm64-dts-allwinner-sun50i-h618-bananapi-m4-zero.patch
new file mode 100644
index 000000000000..3871da1ab416
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arch-arm64-dts-allwinner-sun50i-h618-bananapi-m4-zero.patch
@@ -0,0 +1,309 @@
+From e13a5648e7b0cadac49af05ac7452771253b0f73 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Sun, 17 Mar 2024 18:54:24 -0400
+Subject: arch: arm64: dts: allwinner: sun50i-h618-bananapi-m4-zero
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../sun50i-h618-bananapi-m4-zero.dts          | 276 ++++++++++++++++++
+ 2 files changed, 277 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 74a6e5e0d7b3..fd2f4f11e1fb 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
+ 
+ subdir-y	:= $(dts-dirs) overlay
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts
+new file mode 100644
+index 000000000000..fba5b39cc319
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts
+@@ -0,0 +1,276 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2024 Patrick Yavitz <pyavitz@xxxxx.com>
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "BananaPi M4 Zero";
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h618";
++
++	aliases {
++		ethernet0 = &emac1;
++		serial0 = &uart0;
++		serial5 = &uart5;
++		i2c3 = &i2c3;
++		i2c4 = &i2c4;
++		spi1 = &spi1;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		key-sw3 {
++			label = "sw3";
++			linux,code = <BTN_0>;
++			gpios = <&pio 2 7 GPIO_ACTIVE_LOW>;	/* PC7 */
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			color = <LED_COLOR_ID_RED>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>;	/* PC12 */
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	reg_vcc5v: regulator-5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_usb_vbus: regulator-usb-vbus {
++		/* separate discrete regulator for the USB ports */
++		compatible = "regulator-fixed";
++		regulator-name = "usb-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&reg_vcc5v>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&de {
++	status = "okay";
++};
++
++/* Connected to an on-board RTL8821CU USB WiFi chip. */
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "disabled";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "disabled";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ir_rx_pin>;
++	status = "okay";
++};
++
++&mdio1 {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_dldo1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;	/* PF6 */
++	bus-width = <4>;
++	max-frequency = <50000000>;
++	status = "okay";
++};
++
++&mmc2 {
++	vmmc-supply = <&reg_dldo1>;
++	vqmmc-supply = <&reg_aldo1>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	mmc-hs200-1_8v;
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pc-supply = <&reg_aldo1>;
++	vcc-pf-supply = <&reg_dldo1>;
++	vcc-pg-supply = <&reg_dldo1>;
++	vcc-ph-supply = <&reg_dldo1>;
++	vcc-pi-supply = <&reg_dldo1>;
++};
++
++&r_i2c {
++	status = "okay";
++
++	axp313: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		interrupt-parent = <&pio>;
++
++		vin1-supply = <&reg_vcc5v>;
++		vin2-supply = <&reg_vcc5v>;
++		vin3-supply = <&reg_vcc5v>;
++
++		regulators {
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-1v8-pll";
++			};
++
++			reg_dldo1: dldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc-3v3-io";
++			};
++
++			reg_dcdc1: dcdc1 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <990000>;
++				regulator-name = "vdd-gpu-sys";
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-always-on;
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-name = "vdd-dram";
++			};
++		};
++	};
++};
++
++&spi1 {
++	status = "disabled";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
++
++	spidev@1 {
++		compatible = "rohm,dh2228fv";
++		status = "disabled";
++		reg = <1>;
++		spi-max-frequency = <1000000>;
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	status = "okay";
++};
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart5_pins>;
++	status = "okay";
++};
++
++&usbotg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_usb_vbus>;
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch
new file mode 100644
index 000000000000..53e938cccdf9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch
@@ -0,0 +1,48 @@
+From 944b81371656107101029f67759713abf4f30a51 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Mon, 10 Jul 2023 19:24:21 +0000
+Subject: arm: dts: sun8i: h3: reduce opp-microvolt to prevent not supported by
+ regulator error
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index 1b02a4c3f05d..8c2f597772fe 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -86,19 +86,19 @@ opp-1008000000 {
+ 
+ 		opp-1104000000 {
+ 			opp-hz = /bits/ 64 <1104000000>;
+-			opp-microvolt = <1320000 1320000 1320000>;
++			opp-microvolt = <1300000 1300000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-1200000000 {
+ 			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <1320000 1320000 1320000>;
++			opp-microvolt = <1300000 1300000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-1296000000 {
+ 			opp-hz = /bits/ 64 <1296000000>;
+-			opp-microvolt = <1340000 1340000 1340000>;
++			opp-microvolt = <1300000 1300000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+@@ -106,6 +106,7 @@ opp-1368000000 {
+ 			opp-hz = /bits/ 64 <1368000000>;
+ 			opp-microvolt = <1400000 1400000 1400000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
++			status = "disabled";
+ 		};
+ 	};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch
new file mode 100644
index 000000000000..5edd35b87c64
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch
@@ -0,0 +1,166 @@
+From 3a4da37c64b078259531ef7476d80c1b9afab444 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@mgmail.com>
+Date: Thu, 1 Feb 2024 22:38:21 +0000
+Subject: arm64: dts: H616: Add overlays that are also compatible with orange
+ pi zero2 and zero3
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  5 ++++
+ .../allwinner/overlay/sun50i-h616-i2c2.dtso   |  8 ++++++
+ .../allwinner/overlay/sun50i-h616-i2c3.dtso   |  8 ++++++
+ .../allwinner/overlay/sun50i-h616-i2c4.dtso   |  8 ++++++
+ .../allwinner/overlay/sun50i-h616-uart2.dtso  |  8 ++++++
+ .../allwinner/overlay/sun50i-h616-uart5.dtso  |  8 ++++++
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 26 ++++++++++++++++++-
+ 7 files changed, 70 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 84711585fc86..369b2976b1bb 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -49,6 +49,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-uart2.dtbo \
+ 	sun50i-h6-uart3.dtbo \
+ 	sun50i-h6-w1-gpio.dtbo \
++	sun50i-h616-i2c2.dtbo \
++	sun50i-h616-i2c3.dtbo \
++	sun50i-h616-i2c4.dtbo \
++	sun50i-h616-uart2.dtbo \
++	sun50i-h616-uart5.dtbo \
+ 	sun50i-h616-spi-spidev.dtbo \
+ 	sun50i-h616-spidev0_0.dtbo \
+ 	sun50i-h616-spidev1_0.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso
+new file mode 100644
+index 000000000000..feebc9ad85fb
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso
+@@ -0,0 +1,8 @@
++/dts-v1/;
++/plugin/;
++
++&i2c2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c2_ph_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso
+new file mode 100644
+index 000000000000..bb212d3c66da
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso
+@@ -0,0 +1,8 @@
++/dts-v1/;
++/plugin/;
++
++&i2c3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_ph_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso
+new file mode 100644
+index 000000000000..8fbcc658b22c
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso
+@@ -0,0 +1,8 @@
++/dts-v1/;
++/plugin/;
++
++&i2c4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c4_ph_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso
+new file mode 100644
+index 000000000000..6a6806906972
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso
+@@ -0,0 +1,8 @@
++/dts-v1/;
++/plugin/;
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+new file mode 100644
+index 000000000000..4f172489276b
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+@@ -0,0 +1,8 @@
++/dts-v1/;
++/plugin/;
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart5_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index e71b79ebced8..362c43d5eb9f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -319,11 +319,21 @@ i2c0_pins: i2c0-pins {
+ 				function = "i2c0";
+ 			};
+ 
++			i2c2_ph_pins: i2c2-ph-pins {
++				pins = "PH2", "PH3";
++				function = "i2c2";
++			};
++
+ 			i2c3_ph_pins: i2c3-ph-pins {
+ 				pins = "PH4", "PH5";
+ 				function = "i2c3";
+ 			};
+ 
++			i2c4_ph_pins: i2c4-ph-pins {
++				pins = "PH6", "PH7";
++				function = "i2c4";
++			};
++
+ 			ir_rx_pin: ir-rx-pin {
+ 				pins = "PH10";
+ 				function = "ir_rx";
+@@ -374,7 +384,6 @@ spi0_cs0_pin: spi0-cs0-pin {
+ 				function = "spi0";
+ 			};
+ 
+-			/omit-if-no-ref/
+ 			spi1_pins: spi1-pins {
+ 				pins = "PH6", "PH7", "PH8";
+ 				function = "spi1";
+@@ -402,6 +411,21 @@ uart1_rts_cts_pins: uart1-rts-cts-pins {
+ 				pins = "PG8", "PG9";
+ 				function = "uart1";
+ 			};
++
++			uart2_pins: uart2-pins {
++				pins = "PH5", "PH6";
++				function = "uart2";
++			};
++
++			uart2_rts_cts_pins: uart2-rts-cts-pins {
++				pins = "PH7", "PH8";
++				function = "uart2";
++			};
++
++			uart5_pins: uart5-pins {
++				pins = "PH2", "PH3";
++				function = "uart5";
++			};
+ 		};
+ 
+ 		gic: interrupt-controller@3021000 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch
new file mode 100644
index 000000000000..fc6739fe21d9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch
@@ -0,0 +1,64 @@
+From e01bc0a8b41090dabdab780763d35479e653c401 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 13 Nov 2022 23:15:38 +0300
+Subject: arm64: dts: allwiner: sun50i-h616.dtsi: add usb,ehci,ohci
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 74aed0d232a9..44f8ae11ca16 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -58,12 +58,12 @@ reserved-memory {
+ 		ranges;
+ 
+ 		/*
+-		 * 256 KiB reserved for Trusted Firmware-A (BL31).
++		 * 512 KiB reserved for Trusted Firmware-A (BL31).
+ 		 * This is added by BL31 itself, but some bootloaders fail
+ 		 * to propagate this into the DTB handed to kernels.
+ 		 */
+ 		secmon@40000000 {
+-			reg = <0x0 0x40000000 0x0 0x40000>;
++			reg = <0x0 0x40000000 0x0 0x80000>;
+ 			no-map;
+ 		};
+ 	};
+@@ -466,6 +466,8 @@ spi0: spi@5010000 {
+ 			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ 			clock-names = "ahb", "mod";
+ 			resets = <&ccu RST_BUS_SPI0>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi0_pins>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -479,6 +481,8 @@ spi1: spi@5011000 {
+ 			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ 			clock-names = "ahb", "mod";
+ 			resets = <&ccu RST_BUS_SPI1>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -688,11 +692,14 @@ r_ccu: clock@7010000 {
+ 		r_pio: pinctrl@7022000 {
+ 			compatible = "allwinner,sun50i-h616-r-pinctrl";
+ 			reg = <0x07022000 0x400>;
++			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
+ 				 <&rtc CLK_OSC32K>;
+ 			clock-names = "apb", "hosc", "losc";
+ 			gpio-controller;
+ 			#gpio-cells = <3>;
++			interrupt-controller;
++			#interrupt-cells = <3>;
+ 
+ 			/omit-if-no-ref/
+ 			r_i2c_pins: r-i2c-pins {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-.patch
new file mode 100644
index 000000000000..8d1bc86d5f2d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-.patch
@@ -0,0 +1,474 @@
+From c15cdd5568126541113d6970018f449ed44f2288 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Tue, 23 May 2023 16:43:00 +0000
+Subject: arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2
+ arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+ arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+ drivers/cpufreq/cpufreq-dt-platdev.c drivers/cpufreq/sun50i-cpufreq-nvmem.c
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+---
+ .../dts/allwinner/sun50i-h616-cpu-opp.dtsi    | 75 +++++++++++++++
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  |  1 +
+ .../allwinner/sun50i-h616-orangepi-zero2.dts  |  5 +
+ .../dts/allwinner/sun50i-h618-cpu-dvfs.dtsi   | 64 +++++++++++++
+ .../allwinner/sun50i-h618-orangepi-zero3.dts  | 62 ++-----------
+ drivers/cpufreq/cpufreq-dt-platdev.c          |  2 +
+ drivers/cpufreq/sun50i-cpufreq-nvmem.c        | 92 ++++++++++++++-----
+ 7 files changed, 221 insertions(+), 80 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+new file mode 100644
+index 000000000000..36f2950367c6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+@@ -0,0 +1,75 @@
++//SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++//Testing Version 1  from: AGM1968 <AGM1968@users.noreply.github.com>
++//Noted: PLL_CPUX = 24 MHz*N/P (WIP)
++
++/ {
++	cpu_opp_table: opp-table-cpu {
++		compatible = "allwinner,sun50i-h616-operating-points";
++		nvmem-cells = <&cpu_speed_grade>;
++		opp-shared;
++ 
++		opp-480000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <480000000>;
++			opp-microvolt-speed0 = <820000 820000 1100000>; 
++			opp-microvolt-speed1 = <880000 880000 1100000>;
++			opp-microvolt-speed2 = <880000 880000 1100000>;
++		};
++	
++		opp-600000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <600000000>;
++			opp-microvolt-speed0 = <820000 820000 1100000>;
++			opp-microvolt-speed1 = <880000 880000 1100000>;
++			opp-microvolt-speed2 = <880000 880000 1100000>;
++		};
++
++		opp-792000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <792000000>;
++		        opp-microvolt-speed0 = <860000 860000 1100000>;
++			opp-microvolt-speed1 = <940000 940000 1100000>;
++			opp-microvolt-speed2 = <940000 940000 1100000>;
++		};
++
++		opp-1008000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1008000000>;
++			opp-microvolt-speed0 = <900000 900000 1100000>;
++			opp-microvolt-speed1 = <1020000 1020000 1100000>;
++			opp-microvolt-speed2 = <1020000 1020000 1100000>;
++		};
++
++		opp-1200000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt-speed0 = <960000 960000 1100000>;
++			opp-microvolt-speed1 = <1100000 1100000 1100000>;
++			opp-microvolt-speed2 = <1100000 1100000 1100000>;
++		};
++
++		opp-1512000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1512000000>;
++			opp-microvolt-speed0 = <1100000 1100000 1100000>;
++			opp-microvolt-speed1 = <1100000 1100000 1100000>;
++			opp-microvolt-speed2 = <1100000 1100000 1100000>;
++		};
++	};
++};
++
++&cpu0 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu1 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu2 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu3 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index a795087c681f..54dfaf24e75d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -7,6 +7,7 @@
+  */
+ 
+ #include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+index 649274d77827..47ab2acedae6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+@@ -12,6 +12,11 @@ / {
+ 	compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+ };
+ 
++&cpu0  {
++	cpu-supply = <&reg_dcdca>;
++	status = "okay";
++};
++
+ &emac0 {
+ 	allwinner,rx-delay-ps = <3100>;
+ 	allwinner,tx-delay-ps = <700>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+new file mode 100644
+index 000000000000..0509e3fb22e2
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+@@ -0,0 +1,64 @@
++
++
++&r_i2c {
++	status = "okay";
++
++	axp313: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		interrupt-parent = <&pio>;
++		interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9 */
++
++		vin1-supply = <&reg_vcc5v>;
++		vin2-supply = <&reg_vcc5v>;
++		vin3-supply = <&reg_vcc5v>;
++
++		regulators {
++			/* Supplies VCC-PLL and DRAM */
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc1v8";
++			};
++
++			/* Supplies VCC-IO, so needs to be always on. */
++			reg_dldo1: dldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc3v3";
++			};
++
++			reg_dcdc1: dcdc1 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <990000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-name = "vdd-gpu-sys";
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-always-on;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-ramp-delay = <200>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-always-on;
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-name = "vdd-dram";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+index b3b1b8692125..eba89a87785b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+@@ -6,12 +6,18 @@
+ /dts-v1/;
+ 
+ #include "sun50i-h616-orangepi-zero.dtsi"
++#include "sun50i-h618-cpu-dvfs.dtsi"
+ 
+ / {
+ 	model = "OrangePi Zero3";
+ 	compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
+ };
+ 
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
+ &emac0 {
+ 	allwinner,tx-delay-ps = <700>;
+ 	phy-mode = "rgmii-rxid";
+@@ -31,62 +37,6 @@ &mmc0 {
+ 	vmmc-supply = <&reg_dldo1>;
+ };
+ 
+-&r_i2c {
+-	status = "okay";
+-
+-	axp313: pmic@36 {
+-		compatible = "x-powers,axp313a";
+-		reg = <0x36>;
+-		#interrupt-cells = <1>;
+-		interrupt-controller;
+-		interrupt-parent = <&pio>;
+-		interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9 */
+-
+-		vin1-supply = <&reg_vcc5v>;
+-		vin2-supply = <&reg_vcc5v>;
+-		vin3-supply = <&reg_vcc5v>;
+-
+-		regulators {
+-			/* Supplies VCC-PLL, so needs to be always on. */
+-			reg_aldo1: aldo1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-				regulator-name = "vcc1v8";
+-			};
+-
+-			/* Supplies VCC-IO, so needs to be always on. */
+-			reg_dldo1: dldo1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <3300000>;
+-				regulator-max-microvolt = <3300000>;
+-				regulator-name = "vcc3v3";
+-			};
+-
+-			reg_dcdc1: dcdc1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <990000>;
+-				regulator-name = "vdd-gpu-sys";
+-			};
+-
+-			reg_dcdc2: dcdc2 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <1100000>;
+-				regulator-name = "vdd-cpu";
+-			};
+-
+-			reg_dcdc3: dcdc3 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <1100000>;
+-				regulator-max-microvolt = <1100000>;
+-				regulator-name = "vdd-dram";
+-			};
+-		};
+-	};
+-};
+-
+ &pio {
+ 	vcc-pc-supply = <&reg_dldo1>;
+ 	vcc-pf-supply = <&reg_dldo1>;
+diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
+index fb2875ce1fdd..0b5cbe13ccb1 100644
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -104,6 +104,8 @@ static const struct of_device_id allowlist[] __initconst = {
+  */
+ static const struct of_device_id blocklist[] __initconst = {
+ 	{ .compatible = "allwinner,sun50i-h6", },
++	{ .compatible = "allwinner,sun50i-h616", },
++	{ .compatible = "allwinner,sun50i-h618", },
+ 
+ 	{ .compatible = "apple,arm-platform", },
+ 
+diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+index 6845ab5034ec..51d7010c49a7 100644
+--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+@@ -6,6 +6,9 @@
+  * provide the OPP framework with required information.
+  *
+  * Copyright (C) 2019 Yangtao Li <tiny.windzz@gmail.com>
++ *
++ * ADD efuse_xlate to extract SoC version so that h6 and h616 can coexist.
++ * Version 1 AGM1968 <AGM1968@users.noreply.github.com>
+  */
+ 
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+@@ -20,25 +23,62 @@
+ 
+ #define MAX_NAME_LEN	7
+ 
+-#define NVMEM_MASK	0x7
+-#define NVMEM_SHIFT	5
++#define SUN50I_H616_NVMEM_MASK 0x22
++#define SUN50I_H616_NVMEM_SHIFT 5
++#define SUN50I_H6_NVMEM_MASK 0x7
++#define SUN50I_H6_NVMEM_SHIFT 5
++
++struct sunxi_cpufreq_soc_data {
++	u32 (*efuse_xlate) (void *efuse);
++};
+ 
+ static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
+ 
++static u32 sun50i_h616_efuse_xlate(void *efuse)
++{
++   u32 efuse_value = (*(u32 *)efuse >> SUN50I_H616_NVMEM_SHIFT) &
++             SUN50I_H616_NVMEM_MASK;
++
++   /* Tested as V1 h616 soc. Expected efuse values are 1 - 3,
++      slowest to fastest */
++   if (efuse_value >=1 && efuse_value <= 3)
++       return efuse_value - 1;
++   else
++       return 0;
++};
++
++static u32 sun50i_h6_efuse_xlate(void *efuse)
++{
++   u32 efuse_value = (*(u32 *)efuse >> SUN50I_H6_NVMEM_SHIFT) &
++             SUN50I_H6_NVMEM_MASK;
++
++   /*
++    * We treat unexpected efuse values as if the SoC was from
++    * the slowest bin. Expected efuse values are 1 - 3, slowest
++    * to fastest.
++   */
++   if (efuse_value >= 1 && efuse_value <= 3)
++       return efuse_value - 1;
++   else
++       return 0;
++};
++
++
+ /**
+  * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
++ * @soc_data: pointer to sunxi_cpufreq_soc_data context
+  * @versions: Set to the value parsed from efuse
+  *
+  * Returns 0 if success.
+  */
+-static int sun50i_cpufreq_get_efuse(u32 *versions)
++static int sun50i_cpufreq_get_efuse(const struct sunxi_cpufreq_soc_data *soc_data,
++		u32 *versions)
+ {
+ 	struct nvmem_cell *speedbin_nvmem;
+ 	struct device_node *np;
+ 	struct device *cpu_dev;
+-	u32 *speedbin, efuse_value;
++	u32 *speedbin;
+ 	size_t len;
+-	int ret;
+ 
+ 	cpu_dev = get_cpu_device(0);
+ 	if (!cpu_dev)
+@@ -47,10 +87,9 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
+ 	np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
+ 	if (!np)
+ 		return -ENOENT;
+-
+-	ret = of_device_is_compatible(np,
+-				      "allwinner,sun50i-h6-operating-points");
+-	if (!ret) {
++	if (of_device_is_compatible(np, "allwinner,sun50i-h6-operating-points")) {}
++	else if (of_device_is_compatible(np, "allwinner,sun50i-h616-operating-points")) {}
++	else {
+ 		of_node_put(np);
+ 		return -ENOENT;
+ 	}
+@@ -66,17 +105,7 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
+ 	if (IS_ERR(speedbin))
+ 		return PTR_ERR(speedbin);
+ 
+-	efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
+-
+-	/*
+-	 * We treat unexpected efuse values as if the SoC was from
+-	 * the slowest bin. Expected efuse values are 1-3, slowest
+-	 * to fastest.
+-	 */
+-	if (efuse_value >= 1 && efuse_value <= 3)
+-		*versions = efuse_value - 1;
+-	else
+-		*versions = 0;
++	*versions = soc_data->efuse_xlate(speedbin);
+ 
+ 	kfree(speedbin);
+ 	return 0;
+@@ -84,18 +113,23 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
+ 
+ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
+ {
++	const struct of_device_id *match;
+ 	int *opp_tokens;
+ 	char name[MAX_NAME_LEN];
+ 	unsigned int cpu;
+ 	u32 speed = 0;
+ 	int ret;
+ 
++	match = dev_get_platdata(&pdev->dev);
++	if (!match)
++		return -EINVAL;
++
+ 	opp_tokens = kcalloc(num_possible_cpus(), sizeof(*opp_tokens),
+ 			     GFP_KERNEL);
+ 	if (!opp_tokens)
+ 		return -ENOMEM;
+ 
+-	ret = sun50i_cpufreq_get_efuse(&speed);
++	ret = sun50i_cpufreq_get_efuse(match-> data, &speed);
+ 	if (ret) {
+ 		kfree(opp_tokens);
+ 		return ret;
+@@ -159,8 +193,18 @@ static struct platform_driver sun50i_cpufreq_driver = {
+ 	},
+ };
+ 
++static const struct sunxi_cpufreq_soc_data sun50i_h616_data = {
++    .efuse_xlate = sun50i_h616_efuse_xlate,
++};
++
++static const struct sunxi_cpufreq_soc_data sun50i_h6_data = {
++    .efuse_xlate = sun50i_h6_efuse_xlate,
++};
++
+ static const struct of_device_id sun50i_cpufreq_match_list[] = {
+-	{ .compatible = "allwinner,sun50i-h6" },
++	{ .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data },
++        { .compatible = "allwinner,sun50i-h616", .data = &sun50i_h616_data },
++        { .compatible = "allwinner,sun50i-h618", .data = &sun50i_h616_data },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
+@@ -196,8 +240,8 @@ static int __init sun50i_cpufreq_init(void)
+ 		return ret;
+ 
+ 	sun50i_cpufreq_pdev =
+-		platform_device_register_simple("sun50i-cpufreq-nvmem",
+-						-1, NULL, 0);
++		platform_device_register_data(NULL,
++		"sun50i-cpufreq-nvmem", -1, match, sizeof(*match));
+ 	ret = PTR_ERR_OR_ZERO(sun50i_cpufreq_pdev);
+ 	if (ret == 0)
+ 		return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwinner-h616-Fix-thermal-zones-add-missing-trips.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwinner-h616-Fix-thermal-zones-add-missing-trips.patch
new file mode 100644
index 000000000000..5a3567f63724
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwinner-h616-Fix-thermal-zones-add-missing-trips.patch
@@ -0,0 +1,73 @@
+From b7ff2326aa729907a527503fe7da50317c3fbd86 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Micha=C5=82=20Dzieko=C5=84ski?=
+ <michal.dziekonski+github@gmail.com>
+Date: Wed, 3 May 2023 12:17:28 +0000
+Subject: arm64: dts: allwinner: h616: Fix thermal zones (add missing trips)
+
+Signed-off-by: Michal Dziekonski <michal.dziekonski+github@gmail.com>
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 29 +++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index e3848b22359b..6ba83df33652 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -877,6 +877,11 @@ cpu_target: trip-point@1 {
+ 					type = "passive";
+ 					hysteresis = <0>;
+ 				};
++				cpu_temp_critical: trip-point@2 {
++					temperature = <110000>;
++					type = "critical";
++					hysteresis = <0>;
++				};
+ 			};
+ 
+ 			cooling-maps {
+@@ -895,18 +900,42 @@ gpu-thermal {
+ 			polling-delay = <1000>;
+ 			thermal-sensors = <&ths 0>;
+ 			sustainable-power = <1100>;
++
++			trips {
++				gpu_temp_critical: trip-point@0 {
++					temperature = <110000>;
++					type = "critical";
++					hysteresis = <0>;
++				};
++			};
+ 		};
+ 
+ 		ve-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 1>;
++
++			trips {
++				ve_temp_critical: trip-point@0 {
++					temperature = <110000>;
++					type = "critical";
++					hysteresis = <0>;
++				};
++			};
+ 		};
+ 
+ 		ddr-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 3>;
++
++			trips {
++				ddr_temp_critical: trip-point@0 {
++					temperature = <110000>;
++					type = "critical";
++					hysteresis = <0>;
++				};
++			};
+ 		};
+ 	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch
new file mode 100644
index 000000000000..c43bdd7667ba
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch
@@ -0,0 +1,48 @@
+From 0bc7e696227939df69c5bccdb4d19693a3db43f5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Micha=C5=82=20Dzieko=C5=84ski?=
+ <michal.dziekonski+github@gmail.com>
+Date: Sun, 28 May 2023 00:26:43 +0000
+Subject: arm64: dts: allwinner: h616 orangepi zero2: Enable expansion board
+ USB ports
+
+Signed-off-by: Michal Dziekonski <michal.dziekonski+github@gmail.com>
+---
+ .../dts/allwinner/sun50i-h616-orangepi-zero.dtsi  | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 3d996494d37c..558852702e55 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -67,6 +67,13 @@ &ehci1 {
+ };
+ 
+ /* USB 2 & 3 are on headers only. */
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
+ 
+ &emac0 {
+ 	pinctrl-names = "default";
+@@ -92,6 +99,14 @@ &ohci1 {
+ 	status = "okay";
+ };
+ 
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
+ &spi0  {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch
new file mode 100644
index 000000000000..2b40cf4986b0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch
@@ -0,0 +1,68 @@
+From 4113bf1a9d66fe7c958bdf6ff1ad198310b3659f Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Wed, 13 Dec 2023 19:15:45 +0000
+Subject: arm64: dts: h616: add wifi support for orange pi zero 2 and zero3
+
+---
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 558852702e55..6aca609464c0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -60,6 +60,34 @@ reg_usb1_vbus: regulator-usb1-vbus {
+ 		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ 		status = "okay";
+ 	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc5v>;
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
+ };
+ 
+ &ehci1 {
+@@ -95,6 +123,16 @@ &mmc0 {
+ 	status = "okay";
+ };
+ 
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
+ &ohci1 {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch
new file mode 100644
index 000000000000..2964914428b2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch
@@ -0,0 +1,511 @@
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index a957365..812685d 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-early-adopter.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-x96q-lpddr3.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
+new file mode 100644
+index 0000000..ba48e0d
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
+@@ -0,0 +1,491 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2023 Arm Ltd.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
++#include "sun50i-h618-cpu-dvfs.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "X96Q TV-Box";
++	compatible = "x96q,tv-box", "allwinner,sun50i-h616";
++
++	aliases {
++		serial0 = &uart0;
++		serial2 = &uart2;
++		serial3 = &uart3;
++		serial4 = &uart4;
++		serial5 = &uart5;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			function = LED_FUNCTION_STATUS;
++			color = <LED_COLOR_ID_GREEN>;
++			label = "green_led";
++			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++			linux,default-trigger = "heartbeat";
++		};
++
++		100m_link {
++			label = "100m_link";
++			gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
++			default-state = "off";
++		};
++
++		100m_act {
++			label = "100m_act";
++			gpios = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
++			default-state = "off";
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		/* SY8089 DC/DC converter */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&reg_vcc5v>;
++		regulator-always-on;
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc3v3>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
++
++	ac200_pwm_clk: ac200_clk {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		// pwm5 period_ns = 500 > 334 for select 24M clock.
++		pwms = <&pwm 5 500 0>;
++		clock-frequency = <2000000>;
++		status = "okay";
++	};
++
++	soc {
++		pwm: pwm@300a000 {
++			compatible = "allwinner,sun50i-h616-pwm";
++			reg = <0x0300a000 0x400>;
++			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
++			clock-names = "mod", "bus";
++			resets = <&ccu RST_BUS_PWM>;
++			pwm-number = <6>;
++			pwm-base = <0x0>;
++			sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>;
++			#pwm-cells = <3>;
++			status = "okay";
++		};
++
++		pwm0: pwm0@0300a000 {
++			compatible = "allwinner,sunxi-pwm0";
++		};
++
++		pwm1: pwm1@0300a000 {
++			compatible = "allwinner,sunxi-pwm1";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm1_ph_pin>;
++		};
++
++		pwm2: pwm2@0300a000 {
++			compatible = "allwinner,sunxi-pwm2";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm2_ph_pin>;
++		};
++
++		pwm3: pwm3@0300a000 {
++			compatible = "allwinner,sunxi-pwm3";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm3_ph_pin>;
++		};
++
++		pwm4: pwm4@0300a000 {
++			compatible = "allwinner,sunxi-pwm4";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm4_ph_pin>;
++		};
++
++		pwm5: pwm5@0300a000 {
++			compatible = "allwinner,sunxi-pwm5";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm5_pin>;
++			clk_bypass_output = <0x1>;
++			status = "okay";
++		};
++	};
++};
++
++&de {
++	status = "okay";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "disabled";
++};
++
++&mmc0 {
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
++	bus-width = <4>;
++	vmmc-supply = <&reg_dldo1>;
++	max-frequency = <50000000>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
++&emac0 {
++	status = "disabled";
++};
++
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&rmii_phy>;
++	phy-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&mdio1 {
++	rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&ehci0 {
++	status = "disabled";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "disabled";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ir_rx_pin>;
++	status = "okay";
++};
++
++&spi0  {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
++
++	flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <40000000>;
++	};
++};
++
++&spi1 {
++	status = "disabled";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
++
++	spidev@1 {
++		compatible = "rohm,dh2228fv";
++		status = "disabled";
++		reg = <1>;
++		spi-max-frequency = <1000000>;
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pi_pins>;
++	status = "disabled";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pi_pins>;
++	status = "disabled";
++};
++
++&uart4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart4_pi_pins>;
++	status = "disabled";
++};
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart5_ph_pins>;
++	status = "disabled";
++};
++
++&i2c3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa_pins>;
++
++	ac200_x: mfd@10 {
++		compatible = "x-powers,ac200-sunxi";
++		reg = <0x10>;
++		clocks = <&ac200_pwm_clk>;
++		// ephy id
++		nvmem-cells = <&ephy_calibration>;
++		nvmem-cell-names = "calibration";
++
++		ac200_ephy: phy {
++			compatible = "x-powers,ac200-ephy-sunxi";
++			status = "okay";
++		};
++	};
++};
++
++&i2c4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c4_ph_pins>;
++	status = "disabled";
++};
++
++&usbotg {
++	/*
++	 * PHY0 pins are connected to a USB-C socket, but a role switch
++	 * is not implemented: both CC pins are pulled to GND.
++	 * The VBUS pins power the device, so a fixed peripheral mode
++	 * is the best choice.
++	 * The board can be powered via GPIOs, in this case port0 *can*
++	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
++	 * then provided by the GPIOs. Any user of this setup would
++	 * need to adjust the DT accordingly: dr_mode set to "host",
++	 * enabling OHCI0 and EHCI0.
++	 */
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_vcc5v>;
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
++&sid {
++	ephy_calibration: ephy-calibration@2c {
++		reg = <0x2c 0x2>;
++	};
++};
++
++&cpu_temp_critical {
++	temperature = <100000>;
++};
++
++&gpu_temp_critical {
++	temperature = <100000>;
++};
++
++&ve_temp_critical {
++	temperature = <100000>;
++};
++
++&ddr_temp_critical {
++	temperature = <100000>;
++};
++
++&pio {
++	vcc-pc-supply = <&reg_dldo1>;
++	vcc-pf-supply = <&reg_dldo1>;
++	vcc-pg-supply = <&reg_aldo1>;
++	vcc-ph-supply = <&reg_dldo1>;
++	vcc-pi-supply = <&reg_dldo1>;
++
++	/omit-if-no-ref/
++	i2c0_pi_pins: i2c0-pi-pins {
++		pins = "PI5", "PI6";
++		function = "i2c0";
++	};
++
++	/omit-if-no-ref/
++	i2c1_pi_pins: i2c1-pi-pins {
++		pins = "PI7", "PI8";
++		function = "i2c1";
++	};
++
++	/omit-if-no-ref/
++	i2c2_pi_pins: i2c2-pi-pins {
++		pins = "PI9", "PI10";
++		function = "i2c2";
++	};
++
++    i2c3_pa_pins: i2c3-pa-pins {
++        pins = "PA10", "PA11";
++        function = "i2c3";
++        bias-pull-up;
++    };
++
++	/omit-if-no-ref/
++	i2c4_ph_pins: i2c4-ph-pins {
++		pins = "PH6", "PH7";
++		function = "i2c4";
++	};
++
++	/omit-if-no-ref/
++	uart2_pi_pins: uart2-pi-pins {
++		pins = "PI5", "PI6";
++		function = "uart2";
++	};
++
++	/omit-if-no-ref/
++	uart3_pi_pins: uart3-pi-pins {
++		pins = "PI9", "PI10";
++		function = "uart3";
++	};
++
++	/omit-if-no-ref/
++	uart4_pi_pins: uart4-pi-pins {
++		pins = "PI13", "PI14";
++		function = "uart4";
++	};
++
++	/omit-if-no-ref/
++	uart5_ph_pins: uart5-ph-pins {
++		pins = "PH2", "PH3";
++		function = "uart5";
++	};
++
++	/omit-if-no-ref/
++	spi1_cs1_pin: spi1-cs1-pin {
++		pins = "PH9";
++		function = "spi1";
++	};
++
++	/omit-if-no-ref/
++	pwm1_ph_pin: pwm1-ph-pin {
++		pins = "PH3";
++		function = "pwm1";
++	};
++
++	/omit-if-no-ref/
++	pwm2_ph_pin: pwm2-ph-pin {
++		pins = "PH2";
++		function = "pwm2";
++	};
++
++	/omit-if-no-ref/
++	pwm3_ph_pin: pwm3-ph-pin {
++		pins = "PH0";
++		function = "pwm3";
++	};
++
++	/omit-if-no-ref/
++	pwm4_ph_pin: pwm4-ph-pin {
++		pins = "PH1";
++		function = "pwm4";
++	};
++
++	/omit-if-no-ref/
++	pwm5_pin: pwm5-pin {
++		pins = "PA12";
++		function = "pwm5";
++	};
++};
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch
new file mode 100644
index 000000000000..3b67bb0c2998
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch
@@ -0,0 +1,40 @@
+From 82bc11e604e91080964a0a83a2590268e6d3dae1 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 27 Sep 2022 15:28:08 +0300
+Subject: arm64: dts: sun50i-h5-nanopi-r1s-h5: add rtl8153 support
+
+---
+ .../boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts     | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+index a3e040da38a0..78c568cabcb2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+@@ -21,7 +21,8 @@ / {
+ 
+ 	aliases {
+ 		ethernet0 = &emac;
+-		ethernet1 = &rtl8189etv;
++		ethernet1 = &rtl8153;
++		ethernet2 = &rtl8189etv;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -116,6 +117,13 @@ &cpu0 {
+ 
+ &ehci1 {
+ 	status = "okay";
++
++	rtl8153: device@1 {
++		compatible = "usbbda,8153";
++		reg = <1>;
++		realtek,led-data = <0x87>;
++		local-mac-address = [00 00 00 00 00 00];
++	};
+ };
+ 
+ &ehci2 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-emac1.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-emac1.patch
new file mode 100644
index 000000000000..6509e0f87fbb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-emac1.patch
@@ -0,0 +1,46 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: JohnTheCoolingFan <ivan8215145640@gmail.com>
+Date: Thu, 13 Jun 2024 11:50:55 +0000
+Subject: ARM64: dts: sun50i-h616: BigTreeTech CB1: Enable EMAC1
+
+Signed-off-by: JohnTheCoolingFan <ivan8215145640@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 18 ++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+index bbff30ccf..b98e85a51 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+@@ -142,10 +142,28 @@ mcp2515_clock: mcp2515_clock {
+ 		#clock-cells = <0>;
+ 		clock-frequency  = <12000000>;
+ 	};
+ };
+ 
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&rmii_phy>;
++	phy-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&mdio1 {
++	rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dldo1>;
+ 	broken-cd;
+ 	bus-width = <4>;
+ 	max-frequency = <50000000>;
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-hdmi.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-hdmi.patch
new file mode 100644
index 000000000000..2d9e9768e897
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-hdmi.patch
@@ -0,0 +1,65 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: JohnTheCoolingFan <ivan8215145640@gmail.com>
+Date: Thu, 13 Jun 2024 11:07:35 +0000
+Subject: ARM64: dts: sun50i-h616: BigTreeTech CB1: Enable HDMI
+
+Signed-off-by: JohnTheCoolingFan <ivan8215145640@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 26 ++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+index e82da4b6e..bbff30ccf 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+@@ -23,10 +23,21 @@ aliases {
+ 
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+ 		act_led: led-0 {
+ 			gpios = <&pio 7 5 GPIO_ACTIVE_LOW>; /* PH5 */
+@@ -255,10 +266,25 @@ reg_dldo1: dldo1 {
+ 			};
+ 		};
+ 	};
+ };
+ 
++&de {
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_aldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdc2>;
+ 	status = "okay";
+ };
+ 
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-ir-receiver.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-ir-receiver.patch
new file mode 100644
index 000000000000..c8874144a2cf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-ir-receiver.patch
@@ -0,0 +1,32 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: JohnTheCoolingFan <ivan8215145640@gmail.com>
+Date: Mon, 12 Aug 2024 14:50:16 +0000
+Subject: ARM64: dts: sun50i-h616: BigTreeTech CB1: Enable IR receiver
+
+Signed-off-by: JohnTheCoolingFan <ivan8215145640@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+index b98e85a51..c2e20408c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+@@ -352,10 +352,14 @@ &ehci3 {
+ 
+ &ohci3 {
+ 	status = "okay";
+ };
+ 
++&ir {
++	status = "okay";
++};
++
+ &usbotg {
+ 	/*
+ 	 * PHY0 pins are connected to a USB-C socket, but a role switch
+ 	 * is not implemented: both CC pins are pulled to GND.
+ 	 * The VBUS pins power the device, so a fixed peripheral mode
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/cb1-overlay.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/cb1-overlay.patch
new file mode 100644
index 000000000000..bca094646565
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/cb1-overlay.patch
@@ -0,0 +1,498 @@
+From c8966edf0256fbb7635f338441f51ef3471bcd59 Mon Sep 17 00:00:00 2001
+From: Your Name <you@example.com>
+Date: Tue, 30 May 2023 12:04:55 +0800
+Subject: cb1-overlay
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  15 ++-
+ .../overlay/sun50i-h616-fixup.scr-cmd         | 110 ++++++++++++++++++
+ .../dts/allwinner/overlay/sun50i-h616-ir.dtso |  13 +++
+ .../allwinner/overlay/sun50i-h616-light.dtso  |  27 +++++
+ .../overlay/sun50i-h616-mcp2515.dtso          |  18 +++
+ .../overlay/sun50i-h616-spi-spidev.dtso       |  42 +++++++
+ .../overlay/sun50i-h616-spidev0_0.dtso        |  28 +++++
+ .../overlay/sun50i-h616-spidev1_0.dtso        |  28 +++++
+ .../overlay/sun50i-h616-spidev1_1.dtso        |  28 +++++
+ .../overlay/sun50i-h616-spidev1_2.dtso        |  28 +++++
+ .../overlay/sun50i-h616-tft35_spi.dtso        |  33 ++++++
+ .../allwinner/overlay/sun50i-h616-ws2812.dtso |  13 +++
+ 12 files changed, 381 insertions(+), 2 deletions(-)
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 40d67ebb5932..fb6b30d5753e 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -47,12 +47,23 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-uart1.dtbo \
+ 	sun50i-h6-uart2.dtbo \
+ 	sun50i-h6-uart3.dtbo \
+-	sun50i-h6-w1-gpio.dtbo
++	sun50i-h6-w1-gpio.dtbo \
++	sun50i-h616-spi-spidev.dtbo \
++	sun50i-h616-spidev0_0.dtbo \
++	sun50i-h616-spidev1_0.dtbo \
++	sun50i-h616-spidev1_1.dtbo \
++	sun50i-h616-spidev1_2.dtbo \
++	sun50i-h616-ir.dtbo \
++	sun50i-h616-tft35_spi.dtbo \
++	sun50i-h616-mcp2515.dtbo \
++	sun50i-h616-ws2812.dtbo \
++	sun50i-h616-light.dtbo
+ 
+ scr-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-a64-fixup.scr \
+ 	sun50i-h5-fixup.scr \
+-	sun50i-h6-fixup.scr
++	sun50i-h6-fixup.scr \
++	sun50i-h616-fixup.scr
+ 
+ dtbotxt-$(CONFIG_ARCH_SUNXI) += \
+ 	README.sun50i-a64-overlays \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd
+new file mode 100755
+index 000000000000..2bde77cb082d
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd
+@@ -0,0 +1,110 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(C|G|H|I)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6'
++test "${tmp_bank}" = "H" && setenv tmp_bank 7;
++test "${tmp_bank}" = "I" && setenv tmp_bank 8;
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@300b000/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@300b000 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++for f in ${overlays}; do
++	if test "${f}" = "pwm34"; then
++		setenv bootargs_new ""
++		for arg in ${bootargs}; do
++			if test "${arg}" = "console=ttyS0,115200"; then
++				echo "Warning: Disabling ttyS0 console due to enabled PWM3 and PWM4 overlay"
++			else
++				setenv bootargs_new "${bootargs_new} ${arg}"
++			fi
++		done
++		setenv bootargs "${bootargs_new}"
++	fi
++done
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@300b000/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@300b000 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@300b000/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@5000400 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@5000800 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart3-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart3-rts-cts-pins phandle
++	fdt set /soc/serial@5000c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000c00 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000c00 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso
+new file mode 100755
+index 000000000000..825433add1c3
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&ir>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso
+new file mode 100755
+index 000000000000..5010ea6a57b5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c_gpio>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@1 {
++		target = <&uart0>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++
++    fragment@2 {
++		target = <&pwm>;
++		__overlay__ {
++            status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso
+new file mode 100755
+index 000000000000..64841956e568
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso
+@@ -0,0 +1,18 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++    fragment@0 {
++		target = <&spi1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@1 {
++		target = <&can>;
++		__overlay__ {
++            status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso
+new file mode 100755
+index 000000000000..e0ceed71965f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@5010000";
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso
+new file mode 100755
+index 000000000000..a5a89707c3dd
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@5010000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev0_0: spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso
+new file mode 100755
+index 000000000000..20a0486442cc
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev1_0: spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso
+new file mode 100755
+index 000000000000..a9ae45e84063
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev1_1: spidev@1 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <1>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso
+new file mode 100755
+index 000000000000..efe5a8949b3a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev1_2: spidev@2 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <2>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso
+new file mode 100755
+index 000000000000..e96582bcbed5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso
+@@ -0,0 +1,33 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&i2c_gpio>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@1 {
++		target = <&spi1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@2 {
++		target = <&tft_35>;
++		__overlay__ {
++            status = "okay";
++            spi-max-frequency = <12500000>;
++		};
++	};
++
++    fragment@3 {
++		target = <&tft_tp>;
++		__overlay__ {
++            status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso
+new file mode 100755
+index 000000000000..4e43907cb0ce
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&ws2812>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/driver-allwinner-h618-emac.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/driver-allwinner-h618-emac.patch
new file mode 100644
index 000000000000..89d9e16df695
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/driver-allwinner-h618-emac.patch
@@ -0,0 +1,4519 @@
+From 9eb9f2e36907405e3644fb1434652a7a13116ad8 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Wed, 1 May 2024 14:32:00 +0800
+Subject: driver: allwinner h618 emac
+
+commit:
+97b476246bc79756423cf6c1d4907606c9633d4b
+---
+ drivers/gpio/gpiolib-of.c                     |   29 +-
+ drivers/mfd/Kconfig                           |   10 +
+ drivers/mfd/Makefile                          |    1 +
+ drivers/mfd/sunxi-ac200.c                     |  288 +++
+ drivers/net/ethernet/allwinner/Kconfig        |    8 +
+ drivers/net/ethernet/allwinner/Makefile       |    2 +
+ drivers/net/ethernet/allwinner/sunxi-gmac.c   | 2219 +++++++++++++++++
+ drivers/net/ethernet/allwinner/sunxi-gmac.h   |  270 ++
+ .../net/ethernet/allwinner/sunxi_gmac_ops.c   |  768 ++++++
+ drivers/net/phy/Kconfig                       |    8 +
+ drivers/net/phy/Makefile                      |    1 +
+ drivers/net/phy/sunxi-ephy.c                  |  518 ++++
+ include/linux/mfd/ac200.h                     |  213 ++
+ include/linux/of_gpio.h                       |   18 +
+ 14 files changed, 4338 insertions(+), 15 deletions(-)
+ create mode 100644 drivers/mfd/sunxi-ac200.c
+ create mode 100644 drivers/net/ethernet/allwinner/sunxi-gmac.c
+ create mode 100644 drivers/net/ethernet/allwinner/sunxi-gmac.h
+ create mode 100644 drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
+ create mode 100644 drivers/net/phy/sunxi-ephy.c
+ create mode 100644 include/linux/mfd/ac200.h
+
+diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
+index d9525d95e818..6842f90f9efe 100644
+--- a/drivers/gpio/gpiolib-of.c
++++ b/drivers/gpio/gpiolib-of.c
+@@ -25,21 +25,6 @@
+ #include "gpiolib.h"
+ #include "gpiolib-of.h"
+ 
+-/*
+- * This is Linux-specific flags. By default controllers' and Linux' mapping
+- * match, but GPIO controllers are free to translate their own flags to
+- * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
+- */
+-enum of_gpio_flags {
+-	OF_GPIO_ACTIVE_LOW = 0x1,
+-	OF_GPIO_SINGLE_ENDED = 0x2,
+-	OF_GPIO_OPEN_DRAIN = 0x4,
+-	OF_GPIO_TRANSITORY = 0x8,
+-	OF_GPIO_PULL_UP = 0x10,
+-	OF_GPIO_PULL_DOWN = 0x20,
+-	OF_GPIO_PULL_DISABLE = 0x40,
+-};
+-
+ /**
+  * of_gpio_named_count() - Count GPIOs for a device
+  * @np:		device node to count GPIOs for
+@@ -398,6 +383,20 @@ static struct gpio_desc *of_get_named_gpiod_flags(const struct device_node *np,
+ 	return desc;
+ }
+ 
++int of_get_named_gpio_flags(const struct device_node *np, const char *list_name,
++			    int index, enum of_gpio_flags *flags)
++{
++	struct gpio_desc *desc;
++
++	desc = of_get_named_gpiod_flags(np, list_name, index, flags);
++
++	if (IS_ERR(desc))
++		return PTR_ERR(desc);
++	else
++		return desc_to_gpio(desc);
++}
++EXPORT_SYMBOL_GPL(of_get_named_gpio_flags);
++
+ /**
+  * of_get_named_gpio() - Get a GPIO number to use with GPIO API
+  * @np:		device node to get GPIO from
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index caed5e75d11f..e532334e024f 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -203,6 +203,16 @@ config MFD_AC200
+ 	  This driver include only the core APIs. You have to select individual
+ 	  components like Ethernet PHY or codec under the corresponding menus.
+ 
++config MFD_AC200_SUNXI
++	tristate "X-Powers AC200 (Sunxi)"
++	select MFD_CORE
++	depends on I2C
++	depends on PWM_SUNXI_ENHANCE
++	help
++	  If you say Y here you get support for the X-Powers AC200 IC.
++	  This driver include only the core APIs. You have to select individual
++	  components like Ethernet PHY or RTC under the corresponding menus.
++
+ config MFD_AXP20X
+ 	tristate
+ 	select MFD_CORE
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+index 0c3b4aaf4eb7..bc180cf44009 100644
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -141,6 +141,7 @@ obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
+ 
+ obj-$(CONFIG_MFD_AC100)		+= ac100.o
+ obj-$(CONFIG_MFD_AC200)		+= ac200.o
++obj-$(CONFIG_MFD_AC200_SUNXI)		+= sunxi-ac200.o
+ obj-$(CONFIG_MFD_AXP20X)	+= axp20x.o
+ obj-$(CONFIG_MFD_AXP20X_I2C)	+= axp20x-i2c.o
+ obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
+diff --git a/drivers/mfd/sunxi-ac200.c b/drivers/mfd/sunxi-ac200.c
+new file mode 100644
+index 000000000000..7c5b0e0523cf
+--- /dev/null
++++ b/drivers/mfd/sunxi-ac200.c
+@@ -0,0 +1,288 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * MFD core driver for X-Powers' AC200 IC
++ *
++ * The AC200 is a chip which is co-packaged with Allwinner H6 SoC and
++ * includes analog audio codec, analog TV encoder, ethernet PHY, eFuse
++ * and RTC.
++ *
++ * Copyright (c) 2020 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#include <linux/i2c.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/ac200.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/nvmem-consumer.h>
++
++#define SUNXI_AC300_KEY	(0x1 << 8)
++
++/* Interrupts */
++#define AC200_IRQ_RTC  0
++#define AC200_IRQ_EPHY 1
++#define AC200_IRQ_TVE  2
++
++/* IRQ enable register */
++#define AC200_SYS_IRQ_ENABLE_OUT_EN BIT(15)
++#define AC200_SYS_IRQ_ENABLE_RTC    BIT(12)
++#define AC200_SYS_IRQ_ENABLE_EPHY   BIT(8)
++#define AC200_SYS_IRQ_ENABLE_TVE    BIT(4)
++
++static const struct regmap_range_cfg ac200_range_cfg[] = {
++	{
++		.range_min = AC200_SYS_VERSION,
++		.range_max = AC200_IC_CHARA1,
++		.selector_reg = AC200_TWI_REG_ADDR_H,
++		.selector_mask = 0xff,
++		.selector_shift = 0,
++		.window_start = 0,
++		.window_len = 256,
++	}
++};
++
++static const struct regmap_config ac200_regmap_config = {
++	.name = "ac200",
++	.reg_bits	= 8,
++	.val_bits	= 16,
++	.ranges		= ac200_range_cfg,
++	.num_ranges	= ARRAY_SIZE(ac200_range_cfg),
++	.max_register	= AC200_IC_CHARA1,
++};
++
++static const struct regmap_irq ac200_regmap_irqs[] = {
++	REGMAP_IRQ_REG(AC200_IRQ_RTC,  0, AC200_SYS_IRQ_ENABLE_RTC),
++	REGMAP_IRQ_REG(AC200_IRQ_EPHY, 0, AC200_SYS_IRQ_ENABLE_EPHY),
++	REGMAP_IRQ_REG(AC200_IRQ_TVE,  0, AC200_SYS_IRQ_ENABLE_TVE),
++};
++
++static const struct regmap_irq_chip ac200_regmap_irq_chip = {
++	.name			= "ac200_irq_chip",
++	.status_base		= AC200_SYS_IRQ_STATUS,
++	.mask_base		= AC200_SYS_IRQ_ENABLE,
++	.irqs			= ac200_regmap_irqs,
++	.num_irqs		= ARRAY_SIZE(ac200_regmap_irqs),
++	.num_regs		= 1,
++};
++
++static const struct resource ephy_resource[] = {
++	DEFINE_RES_IRQ(AC200_IRQ_EPHY),
++};
++
++static const struct mfd_cell ac200_cells[] = {
++	{
++		.name		= "ac200-ephy-sunxi",
++		.num_resources	= ARRAY_SIZE(ephy_resource),
++		.resources	= ephy_resource,
++		.of_compatible	= "x-powers,ac200-ephy-sunxi",
++	},
++	{
++		.name = "acx00-codec",
++		.of_compatible	= "x-powers,ac200-codec-sunxi",
++	},
++};
++
++atomic_t ac200_en;
++
++int ac200_enable(void)
++{
++    return atomic_read(&ac200_en);
++}
++
++EXPORT_SYMBOL(ac200_enable);
++
++static uint16_t ephy_caldata = 0;
++
++static int sun50i_ephy_get_calibrate(struct device *dev)
++{
++	struct nvmem_cell *calcell;
++	uint16_t *caldata;
++	size_t callen;
++	int ret = 0;
++
++	calcell = devm_nvmem_cell_get(dev, "calibration");
++	if (IS_ERR(calcell)) {
++		dev_err_probe(dev, PTR_ERR(calcell),
++			      "Failed to get calibration nvmem cell (%pe)\n",
++			      calcell);
++
++		if (PTR_ERR(calcell) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++		goto out;
++	}
++
++	caldata = nvmem_cell_read(calcell, &callen);
++	if (IS_ERR(caldata)) {
++		ret = PTR_ERR(caldata);
++		dev_err(dev, "Failed to read calibration data (%pe)\n",
++			caldata);
++		goto out;
++	}
++
++    ephy_caldata = *caldata;
++	kfree(caldata);
++out:
++	return ret;
++}
++
++uint16_t sun50i_ephy_calibrate_value(void)
++{
++    return ephy_caldata;
++}
++
++EXPORT_SYMBOL(sun50i_ephy_calibrate_value);
++
++static int ac200_i2c_probe(struct i2c_client *i2c)
++{
++    struct device *dev = &i2c->dev;
++    struct ac200_dev *ac200;
++    uint32_t ephy_cal;
++    int ret;
++
++    // 24Mhz clock for both ac200 and ac300 devices
++    ac200 = devm_kzalloc(dev, sizeof(*ac200), GFP_KERNEL);
++    if (!ac200)
++        return -ENOMEM;
++
++    ac200->clk = devm_clk_get(dev, NULL);
++    if (IS_ERR(ac200->clk)) {
++        dev_err(dev, "Can't obtain the clock!\n");
++        return PTR_ERR(ac200->clk);
++    }
++
++    ret = clk_prepare_enable(ac200->clk);
++    if (ret) {
++        dev_err(dev, "rclk_prepare_enable failed! \n");
++        return ret;
++    }
++
++    ret = sun50i_ephy_get_calibrate(dev);
++	if (ret) {
++        dev_err(dev, "sun50i get ephy id failed\n");
++        return ret;
++    }
++    ephy_cal = sun50i_ephy_calibrate_value();
++
++    if (ephy_cal & SUNXI_AC300_KEY) {
++        pr_warn("it's ac300, skip the ac200 init!\n");
++        return -EINVAL;
++    } else {
++        pr_warn("it's ac200, ac200 init start!\n");
++    }
++
++    i2c_set_clientdata(i2c, ac200);
++
++    ac200->regmap = devm_regmap_init_i2c(i2c, &ac200_regmap_config);
++    if (IS_ERR(ac200->regmap))
++    {
++        ret = PTR_ERR(ac200->regmap);
++        dev_err(dev, "regmap init failed: %d\n", ret);
++        return ret;
++    }
++
++    /* do a reset to put chip in a known state */
++    ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++    if (ret)
++    {
++        dev_err(dev, "AC200_SYS_CONTROL 0 failed! \n");
++        return ret;
++    }
++	atomic_set(&ac200_en, 0);
++
++    ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++    if (ret)
++    {
++        dev_err(dev, "AC200_SYS_CONTROL 1 failed! \n");
++        return ret;
++    }
++	atomic_set(&ac200_en, 1);
++
++    ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ac200_cells,
++                               ARRAY_SIZE(ac200_cells), NULL, 0, NULL);
++    if (ret)
++    {
++        dev_err(dev, "failed to add MFD devices: %d\n", ret);
++        return ret;
++    }
++    else
++    {
++        dev_err(dev, "add MFD devices success! \n");
++    }
++
++    return 0;
++}
++
++static void ac200_i2c_remove(struct i2c_client *i2c)
++{
++	struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++	regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++
++	mfd_remove_devices(&i2c->dev);
++}static void ac200_i2c_shutdown(struct i2c_client *i2c)
++{
++    struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++    regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++}
++
++static int ac200_i2c_suspend(struct device *dev)
++{
++	struct ac200_dev *ac200 = dev_get_drvdata(dev);
++
++	if (!IS_ERR_OR_NULL(ac200->clk))
++		clk_disable_unprepare(ac200->clk);
++
++	atomic_set(&ac200_en, 0);
++	return 0;
++}
++
++static int ac200_i2c_resume(struct device *dev)
++{
++	struct ac200_dev *ac200 = dev_get_drvdata(dev);
++
++	if (!IS_ERR_OR_NULL(ac200->clk))
++		clk_prepare_enable(ac200->clk);
++
++	atomic_set(&ac200_en, 0);
++	msleep(40);
++    regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++	atomic_set(&ac200_en, 1);
++	return 0;
++}
++
++static const struct dev_pm_ops ac200_core_pm_ops = {
++	.suspend_late = ac200_i2c_suspend,
++	.resume_early = ac200_i2c_resume,
++};
++
++static const struct i2c_device_id ac200_ids[] = {
++	{ "ac200", },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(i2c, ac200_ids);
++
++static const struct of_device_id ac200_of_match[] = {
++	{ .compatible = "x-powers,ac200-sunxi" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_of_match);
++
++static struct i2c_driver ac200_i2c_driver = {
++	.driver = {
++		.name	= "ac200-sunxi",
++		.of_match_table	= of_match_ptr(ac200_of_match),
++        .pm = &ac200_core_pm_ops,
++	},
++	.probe	= ac200_i2c_probe,
++	.remove = ac200_i2c_remove,
++    .shutdown = ac200_i2c_shutdown,
++	.id_table = ac200_ids,
++};
++module_i2c_driver(ac200_i2c_driver);
++
++MODULE_DESCRIPTION("MFD core driver for AC200");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/net/ethernet/allwinner/Kconfig b/drivers/net/ethernet/allwinner/Kconfig
+index 3e81059f8693..36d808810ca4 100644
+--- a/drivers/net/ethernet/allwinner/Kconfig
++++ b/drivers/net/ethernet/allwinner/Kconfig
+@@ -34,4 +34,12 @@ config SUN4I_EMAC
+ 	  To compile this driver as a module, choose M here.  The module
+ 	  will be called sun4i-emac.
+ 
++config SUNXI_GMAC
++    tristate "Allwinner GMAC support"
++	depends on ARCH_SUNXI
++	depends on OF
++	depends on AC200_PHY_SUNXI
++	select CRC32
++	select MII
++
+ endif # NET_VENDOR_ALLWINNER
+diff --git a/drivers/net/ethernet/allwinner/Makefile b/drivers/net/ethernet/allwinner/Makefile
+index ddd5a5079e8a..56b9c434a5b8 100644
+--- a/drivers/net/ethernet/allwinner/Makefile
++++ b/drivers/net/ethernet/allwinner/Makefile
+@@ -4,3 +4,5 @@
+ #
+ 
+ obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o
++sunxi_gmac-objs := sunxi_gmac_ops.o sunxi-gmac.o
++obj-$(CONFIG_SUNXI_GMAC) += sunxi_gmac.o
+diff --git a/drivers/net/ethernet/allwinner/sunxi-gmac.c b/drivers/net/ethernet/allwinner/sunxi-gmac.c
+new file mode 100644
+index 000000000000..d31b86fc1e8c
+--- /dev/null
++++ b/drivers/net/ethernet/allwinner/sunxi-gmac.c
+@@ -0,0 +1,2219 @@
++/*
++ * linux/drivers/net/ethernet/allwinner/sunxi_gmac.c
++ *
++ * Copyright © 2016-2018, fuzhaoke
++ *		Author: fuzhaoke <fuzhaoke@allwinnertech.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ */
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/mii.h>
++#include <linux/gpio.h>
++#include <linux/crc32.h>
++#include <linux/skbuff.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/crypto.h>
++#include <crypto/algapi.h>
++#include <crypto/hash.h>
++#include <linux/err.h>
++#include <linux/scatterlist.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of_net.h>
++#include <linux/of_gpio.h>
++#include <linux/io.h>
++#include "sunxi-gmac.h"
++#include <linux/timer.h>
++#include <linux/phylink.h>
++#include <linux/reset.h>
++
++
++int sunxi_get_soc_chipid(unsigned char *chipid);
++
++#define DMA_DESC_RX 256
++#define DMA_DESC_TX 256
++#define BUDGET      (dma_desc_rx / 4)
++#define TX_THRESH   (dma_desc_tx / 4)
++
++#define HASH_TABLE_SIZE 64
++#define MAX_BUF_SZ      (SZ_2K - 1)
++
++#define POWER_CHAN_NUM  3
++
++#undef PKT_DEBUG
++#undef DESC_PRINT
++
++#define circ_cnt(head, tail, size) (((head) > (tail)) ? ((head) - (tail)) : ((head) - (tail)) & ((size) - 1))
++
++#define circ_space(head, tail, size) circ_cnt((tail), ((head) + 1), (size))
++
++#define circ_inc(n, s) (((n) + 1) % (s))
++
++#define GETH_MAC_ADDRESS "01:02:03:04:05:06"
++static char *mac_str = GETH_MAC_ADDRESS;
++module_param(mac_str, charp, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(mac_str, "MAC Address String.(xx:xx:xx:xx:xx:xx)");
++
++static int rxmode = 1;
++module_param(rxmode, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(rxmode, "DMA threshold control value");
++
++static int txmode = 1;
++module_param(txmode, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(txmode, "DMA threshold control value");
++
++static int pause = 0x400;
++module_param(pause, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(pause, "Flow Control Pause Time");
++
++#define TX_TIMEO 5000
++static int watchdog = TX_TIMEO;
++module_param(watchdog, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
++
++static int dma_desc_rx = DMA_DESC_RX;
++module_param(dma_desc_rx, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(watchdog, "The number of receive's descriptors");
++
++static int dma_desc_tx = DMA_DESC_TX;
++module_param(dma_desc_tx, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(watchdog, "The number of transmit's descriptors");
++
++/* - 0: Flow Off
++ * - 1: Rx Flow
++ * - 2: Tx Flow
++ * - 3: Rx & Tx Flow
++ */
++static int flow_ctrl;
++module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(flow_ctrl, "Flow control [0: off, 1: rx, 2: tx, 3: both]");
++
++static unsigned long tx_delay;
++module_param(tx_delay, ulong, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(tx_delay, "Adjust transmit clock delay, value: 0~7");
++
++static unsigned long rx_delay;
++module_param(rx_delay, ulong, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(rx_delay, "Adjust receive clock delay, value: 0~31");
++
++/* whether using ephy_clk */
++static int g_use_ephy_clk;
++static int g_phy_addr;
++
++struct geth_priv {
++    struct dma_desc *dma_tx;
++    struct sk_buff **tx_sk;
++    unsigned int tx_clean;
++    unsigned int tx_dirty;
++    dma_addr_t dma_tx_phy;
++
++    struct reset_control *ephy_rst;
++
++    unsigned long buf_sz;
++
++    struct dma_desc *dma_rx;
++    struct sk_buff **rx_sk;
++    unsigned int rx_clean;
++    unsigned int rx_dirty;
++    dma_addr_t dma_rx_phy;
++
++    struct net_device *ndev;
++    struct device *dev;
++    struct napi_struct napi;
++
++    struct geth_extra_stats xstats;
++
++    struct mii_bus *mii;
++    int link;
++    int speed;
++    int duplex;
++#define INT_PHY 0
++#define EXT_PHY 1
++    int phy_ext;
++    int phy_interface;
++
++    void __iomem *base;
++    void __iomem *base_phy;
++    struct clk *geth_clk;
++    struct clk *ephy_clk;
++    struct pinctrl *pinctrl;
++
++    struct regulator *gmac_power[POWER_CHAN_NUM];
++    bool is_suspend;
++    int phyrst;
++    u8 rst_active_low;
++    /* definition spinlock */
++    spinlock_t lock;
++    spinlock_t tx_lock;
++
++    /* resume work */
++    struct work_struct eth_work;
++};
++
++static u64 geth_dma_mask = DMA_BIT_MASK(32);
++
++void sunxi_udelay(int n)
++{
++    udelay(n);
++}
++
++static int geth_stop(struct net_device *ndev);
++static int geth_open(struct net_device *ndev);
++static void geth_tx_complete(struct geth_priv *priv);
++static void geth_rx_refill(struct net_device *ndev);
++
++#ifdef CONFIG_GETH_ATTRS
++static ssize_t adjust_bgs_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int value = 0;
++    u32 efuse_value;
++    struct net_device *ndev = to_net_dev(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    if (priv->phy_ext == INT_PHY) {
++        value = readl(priv->base_phy) >> 28;
++        if (sunxi_efuse_read(EFUSE_OEM_NAME, &efuse_value) != 0)
++            pr_err("get PHY efuse fail!\n");
++        else
++#if defined(CONFIG_ARCH_SUN50IW2)
++            value = value - ((efuse_value >> 24) & 0x0F);
++#else
++            pr_warn("miss config come from efuse!\n");
++#endif
++    }
++
++    return sprintf(buf, "bgs: %d\n", value);
++}
++
++static ssize_t adjust_bgs_write(struct device *dev, struct device_attribute *attr,
++                                const char *buf, size_t count)
++{
++    unsigned int out = 0;
++    struct net_device *ndev = to_net_dev(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    u32 clk_value = readl(priv->base_phy);
++    u32 efuse_value;
++
++    out = simple_strtoul(buf, NULL, 10);
++
++    if (priv->phy_ext == INT_PHY) {
++        clk_value &= ~(0xF << 28);
++        if (sunxi_efuse_read(EFUSE_OEM_NAME, &efuse_value) != 0)
++            pr_err("get PHY efuse fail!\n");
++        else
++#if defined(CONFIG_ARCH_SUN50IW2)
++            clk_value |= (((efuse_value >> 24) & 0x0F) + out) << 28;
++#else
++            pr_warn("miss config come from efuse!\n");
++#endif
++    }
++
++    writel(clk_value, priv->base_phy);
++
++    return count;
++}
++
++static struct device_attribute adjust_reg[] = {
++    __ATTR(adjust_bgs, 0664, adjust_bgs_show, adjust_bgs_write),
++};
++
++static int geth_create_attrs(struct net_device *ndev)
++{
++    int j, ret;
++
++    for (j = 0; j < ARRAY_SIZE(adjust_reg); j++) {
++        ret = device_create_file(&ndev->dev, &adjust_reg[j]);
++        if (ret)
++            goto sysfs_failed;
++    }
++    goto succeed;
++
++sysfs_failed:
++    while (j--)
++        device_remove_file(&ndev->dev, &adjust_reg[j]);
++succeed:
++    return ret;
++}
++#endif
++
++#ifdef DEBUG
++static void desc_print(struct dma_desc *desc, int size)
++{
++#ifdef DESC_PRINT
++    int i;
++
++    for (i = 0; i < size; i++) {
++        u32 *x = (u32 *)(desc + i);
++
++        pr_info("\t%d [0x%08lx]: %08x %08x %08x %08x\n",
++                i, (unsigned long)(&desc[i]),
++                x[0], x[1], x[2], x[3]);
++    }
++    pr_info("\n");
++#endif
++}
++#endif
++
++static ssize_t gphy_test_show(struct device *dev,
++                              struct device_attribute *attr, char *buf)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return 0;
++    }
++
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return 0;
++    }
++
++    return sprintf(buf, "Usage:\necho [0/1/2/3/4] > gphy_test\n"
++                        "0 - Normal Mode\n"
++                        "1 - Transmit Jitter Test\n"
++                        "2 - Transmit Jitter Test(MASTER mode)\n"
++                        "3 - Transmit Jitter Test(SLAVE mode)\n"
++                        "4 - Transmit Distortion Test\n\n");
++}
++
++static ssize_t gphy_test_store(struct device *dev,
++                               struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    u16 value = 0;
++    int ret = 0;
++    u16 data = 0;
++
++    if (!dev) {
++        pr_err("Argument is invalid\n");
++        return count;
++    }
++
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return count;
++    }
++
++    data = sunxi_mdio_read(priv->base, g_phy_addr, MII_CTRL1000);
++
++    ret = kstrtou16(buf, 0, &value);
++    if (ret)
++        return ret;
++
++    if (value >= 0 && value <= 4) {
++        data &= ~(0x7 << 13);
++        data |= value << 13;
++        sunxi_mdio_write(priv->base, g_phy_addr, MII_CTRL1000, data);
++        pr_info("Set MII_CTRL1000(0x09) Reg: 0x%x\n", data);
++    } else {
++        pr_info("unknown value (%d)\n", value);
++    }
++
++    return count;
++}
++
++static DEVICE_ATTR(gphy_test, 0664, gphy_test_show, gphy_test_store);
++
++static struct mii_reg_dump mii_reg;
++
++static ssize_t mii_read_show(struct device *dev,
++                             struct device_attribute *attr, char *buf)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return 0;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return 0;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return 0;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return 0;
++    }
++
++    mii_reg.value = sunxi_mdio_read(priv->base, mii_reg.addr, mii_reg.reg);
++    return sprintf(buf, "ADDR[0x%02x]:REG[0x%02x] = 0x%04x\n",
++               mii_reg.addr, mii_reg.reg, mii_reg.value);
++}
++
++static ssize_t mii_read_store(struct device *dev,
++                              struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++    int ret = 0;
++    u16 reg, addr;
++    char *ptr;
++
++    ptr = (char *)buf;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return count;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return count;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return count;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return count;
++    }
++
++    ret = sunxi_parse_read_str(ptr, &addr, &reg);
++    if (ret)
++        return ret;
++
++    mii_reg.addr = addr;
++    mii_reg.reg = reg;
++
++    return count;
++}
++
++static DEVICE_ATTR(mii_read, 0664, mii_read_show, mii_read_store);
++
++static ssize_t mii_write_show(struct device *dev,
++                              struct device_attribute *attr, char *buf)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++    u16 bef_val, aft_val;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return 0;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return 0;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return 0;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return 0;
++    }
++
++    bef_val = sunxi_mdio_read(priv->base, mii_reg.addr, mii_reg.reg);
++    sunxi_mdio_write(priv->base, mii_reg.addr, mii_reg.reg, mii_reg.value);
++    aft_val = sunxi_mdio_read(priv->base, mii_reg.addr, mii_reg.reg);
++    return sprintf(buf, "before ADDR[0x%02x]:REG[0x%02x] = 0x%04x\n"
++                "after  ADDR[0x%02x]:REG[0x%02x] = 0x%04x\n",
++                mii_reg.addr, mii_reg.reg, bef_val,
++                mii_reg.addr, mii_reg.reg, aft_val);
++}
++
++static ssize_t mii_write_store(struct device *dev,
++                               struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++    int ret = 0;
++    u16 reg, addr, val;
++    char *ptr;
++
++    ptr = (char *)buf;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return count;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return count;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return count;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return count;
++    }
++
++    ret = sunxi_parse_write_str(ptr, &addr, &reg, &val);
++    if (ret)
++        return ret;
++
++    mii_reg.reg = reg;
++    mii_reg.addr = addr;
++    mii_reg.value = val;
++
++    return count;
++}
++
++static DEVICE_ATTR(mii_write, 0664, mii_write_show, mii_write_store);
++
++static int geth_power_on(struct geth_priv *priv)
++{
++    int value;
++    int i;
++
++    value = readl(priv->base_phy);
++    if (priv->phy_ext == INT_PHY) {
++        value |= (1 << 15);
++        value &= ~(1 << 16);
++        value |= (3 << 17);
++    } else {
++        value &= ~(1 << 15);
++
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            if (regulator_enable(priv->gmac_power[i]) != 0) {
++                pr_err("gmac-power%d enable error\n", i);
++                return -EINVAL;
++            }
++        }
++    }
++
++    writel(value, priv->base_phy);
++
++    return 0;
++}
++
++static void geth_power_off(struct geth_priv *priv)
++{
++    int value;
++    int i;
++
++    if (priv->phy_ext == INT_PHY) {
++        value = readl(priv->base_phy);
++        value |= (1 << 16);
++        writel(value, priv->base_phy);
++    } else {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            regulator_disable(priv->gmac_power[i]);
++        }
++    }
++}
++
++/* PHY interface operations */
++static int geth_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
++{
++    struct net_device *ndev = bus->priv;
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    return (int)sunxi_mdio_read(priv->base, phyaddr, phyreg);
++}
++
++static int geth_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, u16 data)
++{
++    struct net_device *ndev = bus->priv;
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    sunxi_mdio_write(priv->base, phyaddr, phyreg, data);
++
++    return 0;
++}
++
++static int geth_mdio_reset(struct mii_bus *bus)
++{
++    struct net_device *ndev = bus->priv;
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    return sunxi_mdio_reset(priv->base);
++}
++
++static void geth_adjust_link(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phydev = ndev->phydev;
++    unsigned long flags;
++    int new_state = 0;
++
++    if (!phydev)
++        return;
++
++    spin_lock_irqsave(&priv->lock, flags);
++    if (phydev->link) {
++        /* Now we make sure that we can be in full duplex mode.
++         * If not, we operate in half-duplex mode.
++         */
++        if (phydev->duplex != priv->duplex) {
++            new_state = 1;
++            priv->duplex = phydev->duplex;
++        }
++        /* Flow Control operation */
++        if (phydev->pause)
++            sunxi_flow_ctrl(priv->base, phydev->duplex, flow_ctrl, pause);
++
++        if (phydev->speed != priv->speed) {
++            new_state = 1;
++            priv->speed = phydev->speed;
++        }
++
++        if (priv->link == 0) {
++            new_state = 1;
++            priv->link = phydev->link;
++        }
++
++        if (new_state)
++            sunxi_set_link_mode(priv->base, priv->duplex, priv->speed);
++
++#ifdef LOOPBACK_DEBUG
++        phydev->state = PHY_FORCING;
++#endif
++
++    } else if (priv->link != phydev->link) {
++        new_state = 1;
++        priv->link = 0;
++        priv->speed = 0;
++        priv->duplex = -1;
++    }
++
++    if (new_state)
++        phy_print_status(phydev);
++
++    spin_unlock_irqrestore(&priv->lock, flags);
++}
++
++static int geth_phy_init(struct net_device *ndev)
++{
++    int value;
++    struct mii_bus *new_bus;
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phydev = ndev->phydev;
++    u32 supported = 0, advertising = 0;
++
++    /* Fixup the phy interface type */
++    if (priv->phy_ext == INT_PHY) {
++        priv->phy_interface = PHY_INTERFACE_MODE_MII;
++    } else {
++        /* If config gpio to reset the phy device, we should reset it */
++        if (gpio_is_valid(priv->phyrst)) {
++            gpio_direction_output(priv->phyrst, priv->rst_active_low);
++            msleep(50);
++            gpio_direction_output(priv->phyrst, !priv->rst_active_low);
++            msleep(50);
++        }
++    }
++
++    new_bus = mdiobus_alloc();
++    if (!new_bus) {
++        netdev_err(ndev, "Failed to alloc new mdio bus\n");
++        return -ENOMEM;
++    }
++
++    new_bus->name = dev_name(priv->dev);
++    new_bus->read = &geth_mdio_read;
++    new_bus->write = &geth_mdio_write;
++    new_bus->reset = &geth_mdio_reset;
++    snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x", new_bus->name, 0);
++
++    new_bus->parent = priv->dev;
++    new_bus->priv = ndev;
++
++    if (mdiobus_register(new_bus)) {
++        pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
++        goto reg_fail;
++    }
++
++    priv->mii = new_bus;
++
++    {
++        int addr;
++        for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
++            struct phy_device *phydev_tmp = mdiobus_get_phy(new_bus, addr);
++
++            if (IS_ERR_OR_NULL(phydev_tmp) || phydev_tmp->phy_id == 0xffff) {
++                if (!IS_ERR_OR_NULL(phydev_tmp))
++                    phy_device_remove(phydev_tmp);
++                phydev_tmp = mdiobus_scan_c22(new_bus, addr);
++            }
++
++            if (IS_ERR_OR_NULL(phydev_tmp) || phydev_tmp->phy_id == 0xffff ||
++                phydev_tmp->phy_id == 0x00 || phydev_tmp->phy_id == AC300_ID)
++                continue;
++
++            if (phydev_tmp->phy_id == EPHY_ID || phydev_tmp->phy_id == IP101G_ID) {
++                phydev = phydev_tmp;
++                g_phy_addr = addr;
++                break;
++            }
++        }
++    }
++
++    if (!phydev) {
++        netdev_err(ndev, "No PHY found!\n");
++        goto err;
++    }
++
++    phy_write(phydev, MII_BMCR, BMCR_RESET);
++    while (BMCR_RESET & phy_read(phydev, MII_BMCR))
++        msleep(30);
++
++    value = phy_read(phydev, MII_BMCR);
++    phy_write(phydev, MII_BMCR, (value & ~BMCR_PDOWN));
++
++    phydev->irq = PHY_POLL;
++
++    value = phy_connect_direct(ndev, phydev, &geth_adjust_link, priv->phy_interface);
++    if (value) {
++        netdev_err(ndev, "Could not attach to PHY\n");
++        goto err;
++    } else {
++        netdev_info(ndev, "%s: Type(%d) PHY ID %08x at %d IRQ %s (%s)\n",
++                ndev->name, phydev->interface, phydev->phy_id,
++                phydev->mdio.addr, "poll", dev_name(&phydev->mdio.dev));
++    }
++
++#if 0
++    phydev->supported &= PHY_GBIT_FEATURES; //kandy 000002cf
++    phydev->advertising = phydev->supported;
++#else
++
++    ethtool_convert_link_mode_to_legacy_u32(&supported, phydev->supported);
++
++    advertising = supported &= *PHY_BASIC_FEATURES; // kandy 000002cf
++
++    ethtool_convert_legacy_u32_to_link_mode(phydev->supported, supported);
++    ethtool_convert_legacy_u32_to_link_mode(phydev->advertising, advertising);
++#endif
++
++    if (priv->phy_ext == INT_PHY) {
++        /* EPHY Initial */
++        phy_write(phydev, 0x1f, 0x0100); /* switch to page 1 */
++        phy_write(phydev, 0x12, 0x4824); /* Disable APS */
++        phy_write(phydev, 0x1f, 0x0200); /* switchto page 2 */
++        phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */
++        phy_write(phydev, 0x1f, 0x0600); /* switchto page 6 */
++        phy_write(phydev, 0x14, 0x708F); /* PHYAFE TX optimization */
++        phy_write(phydev, 0x19, 0x0000);
++        phy_write(phydev, 0x13, 0xf000); /* PHYAFE RX optimization */
++        phy_write(phydev, 0x15, 0x1530);
++        phy_write(phydev, 0x1f, 0x0800); /* switch to page 8 */
++        phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */
++        phy_write(phydev, 0x1f, 0x0100); /* switchto page 1 */
++        /* reg 0x17 bit3,set 0 to disable iEEE */
++        phy_write(phydev, 0x17, phy_read(phydev, 0x17) & (~(1<<3)));
++        phy_write(phydev, 0x1f, 0x0000); /* switch to page 0 */
++    }
++
++    return 0;
++
++err:
++    mdiobus_unregister(new_bus);
++reg_fail:
++    mdiobus_free(new_bus);
++
++    return -EINVAL;
++}
++
++static int geth_phy_release(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phydev = ndev->phydev;
++    int value = 0;
++
++    /* Stop and disconnect the PHY */
++    if (phydev)
++        phy_stop(phydev);
++
++    priv->link = PHY_DOWN;
++    priv->speed = 0;
++    priv->duplex = -1;
++
++    if (phydev) {
++        value = phy_read(phydev, MII_BMCR);
++        phy_write(phydev, MII_BMCR, (value | BMCR_PDOWN));
++        phy_disconnect(phydev);
++        ndev->phydev = NULL;
++    }
++
++#if 1 // defined(CONFIG_SUNXI_EPHY)
++    gmac_ephy_shutdown(); /* Turn off the clock of PHY for low power consumption  */
++#endif
++
++    if (priv->mii) {
++        mdiobus_unregister(priv->mii);
++        priv->mii->priv = NULL;
++        mdiobus_free(priv->mii);
++        priv->mii = NULL;
++    }
++
++    return 0;
++}
++
++static void geth_rx_refill(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct dma_desc *desc;
++    struct sk_buff *sk = NULL;
++    dma_addr_t paddr;
++
++    while (circ_space(priv->rx_clean, priv->rx_dirty, dma_desc_rx) > 0) {
++        int entry = priv->rx_clean;
++
++        /* Find the dirty's desc and clean it */
++        desc = priv->dma_rx + entry;
++
++        if (priv->rx_sk[entry] == NULL) {
++            sk = netdev_alloc_skb_ip_align(ndev, priv->buf_sz);
++
++            if (unlikely(sk == NULL))
++                break;
++
++            priv->rx_sk[entry] = sk;
++            paddr = dma_map_single(priv->dev, sk->data,
++                           priv->buf_sz, DMA_FROM_DEVICE);
++            desc_buf_set(desc, paddr, priv->buf_sz);
++        }
++
++        /* sync memery */
++        wmb();
++        desc_set_own(desc);
++        priv->rx_clean = circ_inc(priv->rx_clean, dma_desc_rx);
++    }
++}
++
++/* geth_dma_desc_init - initialize the RX/TX descriptor list
++ * @ndev: net device structure
++ * Description: initialize the list for dma.
++ */
++static int geth_dma_desc_init(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    unsigned int buf_sz;
++
++    priv->rx_sk = kzalloc(sizeof(struct sk_buff *) * dma_desc_rx, GFP_KERNEL);
++    if (!priv->rx_sk)
++        return -ENOMEM;
++
++    priv->tx_sk = kzalloc(sizeof(struct sk_buff *) * dma_desc_tx, GFP_KERNEL);
++    if (!priv->tx_sk)
++        goto tx_sk_err;
++
++    /* Set the size of buffer depend on the MTU & max buf size */
++    buf_sz = MAX_BUF_SZ;
++
++    priv->dma_tx = dma_alloc_coherent(priv->dev,
++                                      dma_desc_tx * sizeof(struct dma_desc),
++                                      &priv->dma_tx_phy,
++                                      GFP_KERNEL);
++    if (!priv->dma_tx)
++        goto dma_tx_err;
++
++    priv->dma_rx = dma_alloc_coherent(priv->dev,
++                                      dma_desc_rx * sizeof(struct dma_desc),
++                                      &priv->dma_rx_phy,
++                                      GFP_KERNEL);
++    if (!priv->dma_rx)
++        goto dma_rx_err;
++
++    priv->buf_sz = buf_sz;
++
++    return 0;
++
++dma_rx_err:
++    dma_free_coherent(priv->dev, dma_desc_rx * sizeof(struct dma_desc), priv->dma_tx, priv->dma_tx_phy);
++dma_tx_err:
++    kfree(priv->tx_sk);
++tx_sk_err:
++    kfree(priv->rx_sk);
++
++    return -ENOMEM;
++}
++
++static void geth_free_rx_sk(struct geth_priv *priv)
++{
++    int i;
++
++    for (i = 0; i < dma_desc_rx; i++) {
++        if (priv->rx_sk[i] != NULL) {
++            struct dma_desc *desc = priv->dma_rx + i;
++
++            dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_FROM_DEVICE);
++            dev_kfree_skb_any(priv->rx_sk[i]);
++            priv->rx_sk[i] = NULL;
++        }
++    }
++}
++
++static void geth_free_tx_sk(struct geth_priv *priv)
++{
++    int i;
++
++    for (i = 0; i < dma_desc_tx; i++) {
++        if (priv->tx_sk[i] != NULL) {
++            struct dma_desc *desc = priv->dma_tx + i;
++
++            if (desc_buf_get_addr(desc))
++                dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_TO_DEVICE);
++            dev_kfree_skb_any(priv->tx_sk[i]);
++            priv->tx_sk[i] = NULL;
++        }
++    }
++}
++
++static void geth_free_dma_desc(struct geth_priv *priv)
++{
++    /* Free the region of consistent memory previously allocated for the DMA */
++    dma_free_coherent(priv->dev, dma_desc_tx * sizeof(struct dma_desc), priv->dma_tx, priv->dma_tx_phy);
++    dma_free_coherent(priv->dev, dma_desc_rx * sizeof(struct dma_desc), priv->dma_rx, priv->dma_rx_phy);
++
++    kfree(priv->rx_sk);
++    kfree(priv->tx_sk);
++}
++
++#ifdef CONFIG_PM
++static int geth_select_gpio_state(struct pinctrl *pctrl, char *name)
++{
++    int ret = 0;
++    struct pinctrl_state *pctrl_state = NULL;
++
++    pctrl_state = pinctrl_lookup_state(pctrl, name);
++    if (IS_ERR(pctrl_state)) {
++        pr_err("gmac pinctrl_lookup_state(%s) failed! return %p\n", name, pctrl_state);
++        return -EINVAL;
++    }
++
++    ret = pinctrl_select_state(pctrl, pctrl_state);
++    if (ret < 0)
++        pr_err("gmac pinctrl_select_state(%s) failed! return %d\n", name, ret);
++
++    return ret;
++}
++
++static int geth_suspend(struct device *dev)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    cancel_work_sync(&priv->eth_work);
++
++    if (!ndev || !netif_running(ndev))
++        return 0;
++
++    spin_lock(&priv->lock);
++    netif_device_detach(ndev);
++    spin_unlock(&priv->lock);
++
++    geth_stop(ndev);
++
++    if (priv->phy_ext == EXT_PHY)
++        geth_select_gpio_state(priv->pinctrl, PINCTRL_STATE_SLEEP);
++
++    return 0;
++}
++
++static void geth_resume_work(struct work_struct *work)
++{
++    struct geth_priv *priv = container_of(work, struct geth_priv, eth_work);
++    struct net_device *ndev = priv->ndev;
++
++    if (!netif_running(ndev))
++        return;
++
++    if (priv->phy_ext == EXT_PHY)
++        geth_select_gpio_state(priv->pinctrl, PINCTRL_STATE_DEFAULT);
++
++    geth_open(ndev);
++
++#if 1 //defined(CONFIG_SUNXI_EPHY)
++    if (!ephy_is_enable()) {
++        pr_info("[geth_resume] ephy is not enable, waiting...\n");
++        msleep(2000);
++        if (!ephy_is_enable()) {
++            netdev_err(ndev, "Wait for ephy resume timeout.\n");
++            return;
++        }
++    }
++#endif
++
++    spin_lock(&priv->lock);
++    netif_device_attach(ndev);
++    spin_unlock(&priv->lock);
++
++}
++
++static void geth_resume(struct device *dev)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    schedule_work(&priv->eth_work);
++}
++
++
++
++static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
++{
++	struct net_device *ndev = platform_get_drvdata(ofdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    cancel_work_sync(&priv->eth_work);
++
++    if (!ndev || !netif_running(ndev))
++        return 0;
++
++    spin_lock(&priv->lock);
++    netif_device_detach(ndev);
++    spin_unlock(&priv->lock);
++
++    geth_stop(ndev);
++
++    if (priv->phy_ext == EXT_PHY)
++        geth_select_gpio_state(priv->pinctrl, PINCTRL_STATE_SLEEP);
++
++
++	return 0;
++}
++
++static int ucc_geth_resume(struct platform_device *ofdev)
++{
++	struct net_device *ndev = platform_get_drvdata(ofdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    schedule_work(&priv->eth_work);
++
++
++	return 0;
++}
++
++static int geth_freeze(struct device *dev)
++{
++    return 0;
++}
++
++static int geth_restore(struct device *dev)
++{
++    return 0;
++}
++
++static const struct dev_pm_ops geth_pm_ops = {
++    .complete = geth_resume,
++    .prepare = geth_suspend,
++    .suspend = NULL,
++    .resume = NULL,
++    .freeze = geth_freeze,
++    .restore = geth_restore,
++};
++#else
++static const struct dev_pm_ops geth_pm_ops;
++#endif /* CONFIG_PM */
++
++/*#define sunxi_get_soc_chipid(x) {}*/
++static void geth_chip_hwaddr(u8 *addr)
++{
++#define MD5_SIZE 16
++#define CHIP_SIZE 16
++
++    struct crypto_ahash *tfm;
++    struct ahash_request *req;
++    struct scatterlist sg;
++    u8 result[MD5_SIZE];
++    u8 chipid[CHIP_SIZE];
++    int i = 0;
++    int ret = -1;
++
++    memset(chipid, 0, sizeof(chipid));
++    memset(result, 0, sizeof(result));
++
++    sunxi_get_soc_chipid((u8 *)chipid);
++
++    tfm = crypto_alloc_ahash("md5", 0, CRYPTO_ALG_ASYNC);
++    if (IS_ERR(tfm)) {
++        pr_err("Failed to alloc md5\n");
++        return;
++    }
++
++    req = ahash_request_alloc(tfm, GFP_KERNEL);
++    if (!req)
++        goto out;
++
++    ahash_request_set_callback(req, 0, NULL, NULL);
++
++    ret = crypto_ahash_init(req);
++    if (ret) {
++        pr_err("crypto_ahash_init() failed\n");
++        goto out;
++    }
++
++    sg_init_one(&sg, chipid, sizeof(chipid));
++    ahash_request_set_crypt(req, &sg, result, sizeof(chipid));
++    ret = crypto_ahash_update(req);
++    if (ret) {
++        pr_err("crypto_ahash_update() failed for id\n");
++        goto out;
++    }
++
++    ret = crypto_ahash_final(req);
++    if (ret) {
++        pr_err("crypto_ahash_final() failed for result\n");
++        goto out;
++    }
++
++    ahash_request_free(req);
++
++    /* Choose md5 result's [0][2][4][6][8][10] byte as mac address */
++    for (i = 0; i < ETH_ALEN; i++)
++        addr[i] = result[2 * i];
++    addr[0] &= 0xfe; /* clear multicast bit */
++    addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
++
++out:
++    crypto_free_ahash(tfm);
++}
++
++static void geth_check_addr(struct net_device *ndev, unsigned char *mac)
++{
++    int i;
++    char *p = mac;
++    u8 addr[ETH_ALEN];
++
++    if (!is_valid_ether_addr(ndev->dev_addr)) {
++        for (i = 0; i < ETH_ALEN; i++, p++)
++            addr[i] = simple_strtoul(p, &p, 16);
++
++        if (!is_valid_ether_addr(addr))
++            geth_chip_hwaddr(addr);
++
++        if (!is_valid_ether_addr(addr)) {
++            eth_random_addr(addr);
++            pr_warn("%s: Use random mac address\n", ndev->name);
++        }
++    }
++
++    eth_hw_addr_set(ndev, addr);
++}
++
++static void geth_clk_enable(struct geth_priv *priv)
++{
++    int phy_interface = 0;
++    u32 clk_value;
++    u32 efuse_value;
++
++    if (clk_prepare_enable(priv->geth_clk))
++        pr_err("try to enable geth_clk failed!\n");
++
++    if (((priv->phy_ext == INT_PHY) || g_use_ephy_clk) && !IS_ERR_OR_NULL(priv->ephy_clk)) {
++        if (clk_prepare_enable(priv->ephy_clk))
++            pr_err("try to enable ephy_clk failed!\n");
++    }
++
++    phy_interface = priv->phy_interface;
++
++    clk_value = readl(priv->base_phy);
++    if (phy_interface == PHY_INTERFACE_MODE_RGMII)
++        clk_value |= 0x00000004;
++    else
++        clk_value &= (~0x00000004);
++
++    clk_value &= (~0x00002003);
++    if (phy_interface == PHY_INTERFACE_MODE_RGMII || phy_interface == PHY_INTERFACE_MODE_GMII)
++        clk_value |= 0x00000002;
++    else if (phy_interface == PHY_INTERFACE_MODE_RMII)
++        clk_value |= 0x00002001;
++
++    if (priv->phy_ext == INT_PHY) {
++//         if (0 != sunxi_efuse_read(EFUSE_OEM_NAME, &efuse_value))
++//             pr_err("get PHY efuse fail!\n");
++//         else
++// #if defined(CONFIG_ARCH_SUN50IW2)
++//             clk_value |= (((efuse_value >> 24) & 0x0F) + 3) << 28;
++// #else
++//             pr_warn("miss config come from efuse!\n");
++// #endif
++    }
++
++    /* Adjust Tx/Rx clock delay */
++    clk_value &= ~(0x07 << 10);
++    clk_value |= ((tx_delay & 0x07) << 10);
++    clk_value &= ~(0x1F << 5);
++    clk_value |= ((rx_delay & 0x1F) << 5);
++
++    writel(clk_value, priv->base_phy);
++}
++
++static void geth_clk_disable(struct geth_priv *priv)
++{
++    if (((priv->phy_ext == INT_PHY) || g_use_ephy_clk) && !IS_ERR_OR_NULL(priv->ephy_clk))
++        clk_disable_unprepare(priv->ephy_clk);
++
++    clk_disable_unprepare(priv->geth_clk);
++}
++
++static void geth_tx_err(struct geth_priv *priv)
++{
++    netif_stop_queue(priv->ndev);
++
++    sunxi_stop_tx(priv->base);
++
++    geth_free_tx_sk(priv);
++    memset(priv->dma_tx, 0, dma_desc_tx * sizeof(struct dma_desc));
++    desc_init_chain(priv->dma_tx, (unsigned long)priv->dma_tx_phy, dma_desc_tx);
++    priv->tx_dirty = 0;
++    priv->tx_clean = 0;
++    sunxi_start_tx(priv->base, priv->dma_tx_phy);
++
++    priv->ndev->stats.tx_errors++;
++    netif_wake_queue(priv->ndev);
++}
++
++static inline void geth_schedule(struct geth_priv *priv)
++{
++    if (likely(napi_schedule_prep(&priv->napi))) {
++        sunxi_int_disable(priv->base);
++        __napi_schedule(&priv->napi);
++    }
++}
++
++static irqreturn_t geth_interrupt(int irq, void *dev_id)
++{
++    struct net_device *ndev = (struct net_device *)dev_id;
++    struct geth_priv *priv = netdev_priv(ndev);
++    int status;
++
++    if (unlikely(!ndev)) {
++        pr_err("%s: invalid ndev pointer\n", __func__);
++        return IRQ_NONE;
++    }
++
++    status = sunxi_int_status(priv->base, (void *)(&priv->xstats));
++
++    if (likely(status == handle_tx_rx))
++        geth_schedule(priv);
++    else if (unlikely(status == tx_hard_error_bump_tc))
++        netdev_info(ndev, "Do nothing for bump tc\n");
++    else if (unlikely(status == tx_hard_error))
++        geth_tx_err(priv);
++    else
++        netdev_info(ndev, "Do nothing.....\n");
++
++    return IRQ_HANDLED;
++}
++
++static int geth_open(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    int ret = 0;
++
++    ret = geth_dma_desc_init(ndev);
++    if (ret) {
++        ret = -EINVAL;
++        return ret;
++    }
++
++    ret = geth_power_on(priv);
++    if (ret) {
++        netdev_err(ndev, "Power on is failed\n");
++        ret = -EINVAL;
++        goto power_err;
++    }
++
++    geth_clk_enable(priv);
++
++    ret = geth_phy_init(ndev);
++    if (ret) {
++        netdev_err(ndev, "phy init again...\n");
++        ret = geth_phy_init(ndev);
++        if (ret) {
++            netdev_err(ndev, "phy init failed\n");
++            ret = -EINVAL;
++            goto phy_err;
++        }
++    }
++
++    ret = sunxi_mac_reset((void *)priv->base, &sunxi_udelay, 10000);
++    if (ret) {
++        netdev_err(ndev, "Initialize hardware error\n");
++        goto mac_err;
++    }
++
++    sunxi_mac_init(priv->base, txmode, rxmode);
++    sunxi_set_umac(priv->base, ndev->dev_addr, 0);
++
++    memset(priv->dma_tx, 0, dma_desc_tx * sizeof(struct dma_desc));
++    memset(priv->dma_rx, 0, dma_desc_rx * sizeof(struct dma_desc));
++
++    desc_init_chain(priv->dma_rx, (unsigned long)priv->dma_rx_phy, dma_desc_rx);
++    desc_init_chain(priv->dma_tx, (unsigned long)priv->dma_tx_phy, dma_desc_tx);
++
++    priv->rx_clean = 0;
++    priv->rx_dirty = 0;
++    priv->tx_clean = 0;
++    priv->tx_dirty = 0;
++    geth_rx_refill(ndev);
++
++    /* Extra statistics */
++    memset(&priv->xstats, 0, sizeof(struct geth_extra_stats));
++
++    if (ndev->phydev)
++        phy_start(ndev->phydev);
++
++    sunxi_start_rx(priv->base, (unsigned long)((struct dma_desc *)priv->dma_rx_phy + priv->rx_dirty));
++    sunxi_start_tx(priv->base, (unsigned long)((struct dma_desc *)priv->dma_tx_phy + priv->tx_clean));
++
++    /* Enable the Rx/Tx */
++    sunxi_mac_enable(priv->base);
++
++    netif_carrier_on(ndev);
++
++    napi_enable(&priv->napi);
++    netif_start_queue(ndev);
++
++    return 0;
++
++mac_err:
++    geth_phy_release(ndev);
++phy_err:
++    geth_clk_disable(priv);
++
++    geth_power_off(priv);
++
++power_err:
++    geth_free_dma_desc(priv);
++
++    return ret;
++}
++
++static int geth_stop(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    netif_stop_queue(ndev);
++    napi_disable(&priv->napi);
++
++    netif_carrier_off(ndev);
++
++    /* Release PHY resources */
++    geth_phy_release(ndev);
++
++    /* Disable Rx/Tx */
++    sunxi_mac_disable(priv->base);
++
++    geth_clk_disable(priv);
++    geth_power_off(priv);
++
++    netif_tx_lock_bh(ndev);
++    /* Release the DMA TX/RX socket buffers */
++    geth_free_rx_sk(priv);
++    geth_free_tx_sk(priv);
++    netif_tx_unlock_bh(ndev);
++
++    /* Ensure that hareware have been stopped */
++    geth_free_dma_desc(priv);
++
++    return 0;
++}
++
++static void geth_tx_complete(struct geth_priv *priv)
++{
++    unsigned int entry = 0;
++    struct sk_buff *skb = NULL;
++    struct dma_desc *desc = NULL;
++    int tx_stat;
++
++    spin_lock(&priv->tx_lock);
++    while (circ_cnt(priv->tx_dirty, priv->tx_clean, dma_desc_tx) > 0) {
++        entry = priv->tx_clean;
++        desc = priv->dma_tx + entry;
++
++        /* Check if the descriptor is owned by the DMA. */
++        if (desc_get_own(desc))
++            break;
++
++        /* Verify tx error by looking at the last segment */
++        if (desc_get_tx_ls(desc)) {
++            tx_stat = desc_get_tx_status(desc, (void *)(&priv->xstats));
++
++            if (likely(!tx_stat))
++                priv->ndev->stats.tx_packets++;
++            else
++                priv->ndev->stats.tx_errors++;
++        }
++
++        dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_TO_DEVICE);
++
++        skb = priv->tx_sk[entry];
++        priv->tx_sk[entry] = NULL;
++        desc_init(desc);
++
++        /* Find next dirty desc */
++        priv->tx_clean = circ_inc(entry, dma_desc_tx);
++
++        if (unlikely(skb == NULL))
++            continue;
++
++        dev_kfree_skb(skb);
++    }
++
++    if (unlikely(netif_queue_stopped(priv->ndev)) && circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) > TX_THRESH) {
++        netif_wake_queue(priv->ndev);
++    }
++    spin_unlock(&priv->tx_lock);
++}
++
++static netdev_tx_t geth_xmit(struct sk_buff *skb, struct net_device *ndev)
++{
++    struct geth_priv  *priv = netdev_priv(ndev);
++    unsigned int entry;
++    struct dma_desc *desc, *first;
++    unsigned int len, tmp_len = 0;
++    int i, csum_insert;
++    int nfrags = skb_shinfo(skb)->nr_frags;
++    dma_addr_t paddr;
++
++    spin_lock(&priv->tx_lock);
++    if (unlikely(circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) < (nfrags + 1))) {
++        if (!netif_queue_stopped(ndev)) {
++            netdev_err(ndev, "%s: BUG! Tx Ring full when queue awake\n", __func__);
++            netif_stop_queue(ndev);
++        }
++        spin_unlock(&priv->tx_lock);
++
++        return NETDEV_TX_BUSY;
++    }
++
++    csum_insert = (skb->ip_summed == CHECKSUM_PARTIAL);
++    entry = priv->tx_dirty;
++    first = priv->dma_tx + entry;
++    desc = priv->dma_tx + entry;
++
++    len = skb_headlen(skb);
++    priv->tx_sk[entry] = skb;
++
++#ifdef PKT_DEBUG
++    printk("======TX PKT DATA: ============\n");
++    /* dump the packet */
++    print_hex_dump(KERN_DEBUG, "skb->data: ", DUMP_PREFIX_NONE,
++                   16, 1, skb->data, 64, true);
++#endif
++
++    /* Every desc max size is 2K */
++    while (len != 0) {
++        desc = priv->dma_tx + entry;
++        tmp_len = ((len > MAX_BUF_SZ) ? MAX_BUF_SZ : len);
++
++        paddr = dma_map_single(priv->dev, skb->data, tmp_len, DMA_TO_DEVICE);
++        if (dma_mapping_error(priv->dev, paddr)) {
++            dev_kfree_skb(skb);
++            return -EIO;
++        }
++        desc_buf_set(desc, paddr, tmp_len);
++        /* Don't set the first's own bit, here */
++        if (first != desc) {
++            priv->tx_sk[entry] = NULL;
++            desc_set_own(desc);
++        }
++
++        entry = circ_inc(entry, dma_desc_tx);
++        len -= tmp_len;
++    }
++
++    for (i = 0; i < nfrags; i++) {
++        const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
++
++        len = skb_frag_size(frag);
++        desc = priv->dma_tx + entry;
++        paddr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE);
++        if (dma_mapping_error(priv->dev, paddr)) {
++            dev_kfree_skb(skb);
++            return -EIO;
++        }
++
++        desc_buf_set(desc, paddr, len);
++        desc_set_own(desc);
++        priv->tx_sk[entry] = NULL;
++        entry = circ_inc(entry, dma_desc_tx);
++    }
++
++    ndev->stats.tx_bytes += skb->len;
++    priv->tx_dirty = entry;
++    desc_tx_close(first, desc, csum_insert);
++
++    desc_set_own(first);
++    spin_unlock(&priv->tx_lock);
++
++    if (circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) <= (MAX_SKB_FRAGS + 1)) {
++        netif_stop_queue(ndev);
++        if (circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) > TX_THRESH)
++            netif_wake_queue(ndev);
++    }
++
++#ifdef DEBUG
++    printk("=======TX Descriptor DMA: 0x%08llx\n", priv->dma_tx_phy);
++    printk("Tx pointor: dirty: %d, clean: %d\n", priv->tx_dirty, priv->tx_clean);
++    desc_print(priv->dma_tx, dma_desc_tx);
++#endif
++    sunxi_tx_poll(priv->base);
++    geth_tx_complete(priv);
++
++    return NETDEV_TX_OK;
++}
++
++static int geth_rx(struct geth_priv *priv, int limit)
++{
++    unsigned int rxcount = 0;
++    unsigned int entry;
++    struct dma_desc *desc;
++    struct sk_buff *skb;
++    int status;
++    int frame_len;
++
++    while (rxcount < limit) {
++        entry = priv->rx_dirty;
++        desc = priv->dma_rx + entry;
++
++        if (desc_get_own(desc))
++            break;
++
++        rxcount++;
++        priv->rx_dirty = circ_inc(priv->rx_dirty, dma_desc_rx);
++
++        /* Get length & status from hardware */
++        frame_len = desc_rx_frame_len(desc);
++        status = desc_get_rx_status(desc, (void *)(&priv->xstats));
++
++        netdev_dbg(priv->ndev, "Rx frame size %d, status: %d\n", frame_len, status);
++
++        skb = priv->rx_sk[entry];
++        if (unlikely(!skb)) {
++            netdev_err(priv->ndev, "Skb is null\n");
++            priv->ndev->stats.rx_dropped++;
++            break;
++        }
++
++#ifdef PKT_DEBUG
++        printk("======RX PKT DATA: ============\n");
++        /* dump the packet */
++        print_hex_dump(KERN_DEBUG, "skb->data: ", DUMP_PREFIX_NONE,
++                       16, 1, skb->data, 64, true);
++#endif
++
++        if (status == discard_frame) {
++            netdev_dbg(priv->ndev, "Get error pkt\n");
++            priv->ndev->stats.rx_errors++;
++            continue;
++        }
++
++        if (unlikely(status != llc_snap))
++            frame_len -= ETH_FCS_LEN;
++
++        priv->rx_sk[entry] = NULL;
++
++        skb_put(skb, frame_len);
++        dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_FROM_DEVICE);
++
++        skb->protocol = eth_type_trans(skb, priv->ndev);
++
++        skb->ip_summed = CHECKSUM_UNNECESSARY;
++        napi_gro_receive(&priv->napi, skb);
++
++        priv->ndev->stats.rx_packets++;
++        priv->ndev->stats.rx_bytes += frame_len;
++    }
++
++#ifdef DEBUG
++    if (rxcount > 0) {
++        printk("======RX Descriptor DMA: 0x%08llx=\n", priv->dma_rx_phy);
++        printk("RX pointor: dirty: %d, clean: %d\n", priv->rx_dirty, priv->rx_clean);
++        desc_print(priv->dma_rx, dma_desc_rx);
++    }
++#endif
++    geth_rx_refill(priv->ndev);
++
++    return rxcount;
++}
++
++static int geth_poll(struct napi_struct *napi, int budget)
++{
++    struct geth_priv *priv = container_of(napi, struct geth_priv, napi);
++    int work_done = 0;
++
++    geth_tx_complete(priv);
++    work_done = geth_rx(priv, budget);
++
++    if (work_done < budget) {
++        napi_complete(napi);
++        sunxi_int_enable(priv->base);
++    }
++
++    return work_done;
++}
++
++static int geth_change_mtu(struct net_device *ndev, int new_mtu)
++{
++    int max_mtu;
++
++    if (netif_running(ndev)) {
++        pr_err("%s: must be stopped to change its MTU\n", ndev->name);
++        return -EBUSY;
++    }
++
++    max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
++
++    if ((new_mtu < 46) || (new_mtu > max_mtu)) {
++        pr_err("%s: invalid MTU, max MTU is: %d\n", ndev->name, max_mtu);
++        return -EINVAL;
++    }
++
++    ndev->mtu = new_mtu;
++    netdev_update_features(ndev);
++
++    return 0;
++}
++
++static netdev_features_t geth_fix_features(struct net_device *ndev, netdev_features_t features)
++{
++    return features;
++}
++
++static void geth_set_rx_mode(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    unsigned int value = 0;
++
++    pr_debug("%s: # mcasts %d, # unicast %d\n",
++             __func__, netdev_mc_count(ndev), netdev_uc_count(ndev));
++
++    spin_lock(&priv->lock);
++    if (ndev->flags & IFF_PROMISC) {
++        value = GETH_FRAME_FILTER_PR;
++    } else if ((netdev_mc_count(ndev) > HASH_TABLE_SIZE) ||
++               (ndev->flags & IFF_ALLMULTI)) {
++        value = GETH_FRAME_FILTER_PM; /* pass all multi */
++        sunxi_hash_filter(priv->base, ~0UL, ~0UL);
++    } else if (!netdev_mc_empty(ndev)) {
++        u32 mc_filter[2];
++        struct netdev_hw_addr *ha;
++
++        /* Hash filter for multicast */
++        value = GETH_FRAME_FILTER_HMC;
++
++        memset(mc_filter, 0, sizeof(mc_filter));
++        netdev_for_each_mc_addr(ha, ndev) {
++            /* The upper 6 bits of the calculated CRC are used to
++             *  index the contens of the hash table
++             */
++            int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
++            /* The most significant bit determines the register to
++             * use (H/L) while the other 5 bits determine the bit
++             * within the register.
++             */
++            mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
++        }
++        sunxi_hash_filter(priv->base, mc_filter[0], mc_filter[1]);
++    }
++
++    /* Handle multiple unicast addresses (perfect filtering)*/
++    if (netdev_uc_count(ndev) > 16) {
++        /* Switch to promiscuous mode is more than 8 addrs are required */
++        value |= GETH_FRAME_FILTER_PR;
++    } else {
++        int reg = 1;
++        struct netdev_hw_addr *ha;
++
++        netdev_for_each_uc_addr(ha, ndev) {
++            sunxi_set_umac(priv->base, ha->addr, reg);
++            reg++;
++        }
++    }
++
++#ifdef FRAME_FILTER_DEBUG
++    /* Enable Receive all mode (to debug filtering_fail errors) */
++    value |= GETH_FRAME_FILTER_RA;
++#endif
++    sunxi_set_filter(priv->base, value);
++    spin_unlock(&priv->lock);
++}
++
++static void geth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    geth_tx_err(priv);
++}
++
++static int geth_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
++{
++    if (!netif_running(ndev))
++        return -EINVAL;
++
++    if (!ndev->phydev)
++        return -EINVAL;
++
++    return phy_mii_ioctl(ndev->phydev, rq, cmd);
++}
++
++/* Configuration changes (passed on by ifconfig) */
++static int geth_config(struct net_device *ndev, struct ifmap *map)
++{
++    if (ndev->flags & IFF_UP) /* can't act on a running interface */
++        return -EBUSY;
++
++    /* Don't allow changing the I/O address */
++    if (map->base_addr != ndev->base_addr) {
++        pr_warn("%s: can't change I/O address\n", ndev->name);
++        return -EOPNOTSUPP;
++    }
++
++    /* Don't allow changing the IRQ */
++    if (map->irq != ndev->irq) {
++        pr_warn("%s: can't change IRQ number %d\n", ndev->name, ndev->irq);
++        return -EOPNOTSUPP;
++    }
++
++    return 0;
++}
++
++static int geth_set_mac_address(struct net_device *ndev, void *p)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct sockaddr *addr = p;
++
++    if (!is_valid_ether_addr(addr->sa_data))
++        return -EADDRNOTAVAIL;
++
++	eth_hw_addr_set(ndev, addr->sa_data);
++
++    sunxi_set_umac(priv->base, ndev->dev_addr, 0);
++
++    return 0;
++}
++
++int geth_set_features(struct net_device *ndev, netdev_features_t features)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    if (features & NETIF_F_LOOPBACK && netif_running(ndev))
++        sunxi_mac_loopback(priv->base, 1);
++    else
++        sunxi_mac_loopback(priv->base, 0);
++
++    return 0;
++}
++
++#ifdef CONFIG_NET_POLL_CONTROLLER
++/* Polling receive - used by NETCONSOLE and other diagnostic tools
++ * to allow network I/O with interrupts disabled.
++ */
++static void geth_poll_controller(struct net_device *dev)
++{
++    disable_irq(dev->irq);
++    geth_interrupt(dev->irq, dev);
++    enable_irq(dev->irq);
++}
++#endif
++
++static const struct net_device_ops geth_netdev_ops = {
++    .ndo_init = NULL,
++    .ndo_open = geth_open,
++    .ndo_start_xmit = geth_xmit,
++    .ndo_stop = geth_stop,
++    .ndo_change_mtu = geth_change_mtu,
++    .ndo_fix_features = geth_fix_features,
++    .ndo_set_rx_mode = geth_set_rx_mode,
++    .ndo_tx_timeout = geth_tx_timeout,
++    .ndo_do_ioctl = geth_ioctl,
++    .ndo_set_config = geth_config,
++#ifdef CONFIG_NET_POLL_CONTROLLER
++    .ndo_poll_controller = geth_poll_controller,
++#endif
++    .ndo_set_mac_address = geth_set_mac_address,
++    .ndo_set_features = geth_set_features,
++};
++
++static int geth_check_if_running(struct net_device *ndev)
++{
++    if (!netif_running(ndev))
++        return -EBUSY;
++    return 0;
++}
++
++static int geth_get_sset_count(struct net_device *netdev, int sset)
++{
++    int len;
++
++    switch (sset) {
++    case ETH_SS_STATS:
++        len = 0;
++        return len;
++    default:
++        return -EOPNOTSUPP;
++    }
++}
++
++#if 0
++static int geth_ethtool_getsettings(struct net_device *ndev,
++                    struct ethtool_cmd *cmd)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phy = ndev->phydev;
++    int rc;
++
++    if (phy == NULL) {
++        netdev_err(ndev, "%s: %s: PHY is not registered\n",
++               __func__, ndev->name);
++        return -ENODEV;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_err("%s: interface is disabled: we cannot track "
++               "link speed / duplex setting\n", ndev->name);
++        return -EBUSY;
++    }
++
++    cmd->transceiver = XCVR_INTERNAL;
++    spin_lock_irq(&priv->lock);
++    rc = phy_ethtool_gset(phy, cmd);
++    spin_unlock_irq(&priv->lock);
++
++    return rc;
++}
++
++static int geth_ethtool_setsettings(struct net_device *ndev,
++                    struct ethtool_cmd *cmd)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phy = ndev->phydev;
++    int rc;
++
++    spin_lock(&priv->lock);
++    rc = phy_ethtool_sset(phy, cmd);
++    spin_unlock(&priv->lock);
++
++    return rc;
++}
++#endif
++
++static void geth_ethtool_getdrvinfo(struct net_device *ndev,
++                                    struct ethtool_drvinfo *info)
++{
++    strlcpy(info->driver, "sunxi_geth", sizeof(info->driver));
++
++#define DRV_MODULE_VERSION "SUNXI Gbgit driver V1.1"
++
++    strcpy(info->version, DRV_MODULE_VERSION);
++    info->fw_version[0] = '\0';
++}
++
++static const struct ethtool_ops geth_ethtool_ops = {
++    .begin = geth_check_if_running,
++    // .get_settings = geth_ethtool_getsettings,
++    // .set_settings = geth_ethtool_setsettings,
++    .get_link_ksettings = phy_ethtool_get_link_ksettings,
++    .set_link_ksettings = phy_ethtool_set_link_ksettings,
++    .get_link = ethtool_op_get_link,
++    .get_pauseparam = NULL,
++    .set_pauseparam = NULL,
++    .get_ethtool_stats = NULL,
++    .get_strings = NULL,
++    .get_wol = NULL,
++    .set_wol = NULL,
++    .get_sset_count = geth_get_sset_count,
++    .get_drvinfo = geth_ethtool_getdrvinfo,
++};
++
++struct gpio_config {
++	u32	gpio;
++	u32	mul_sel;
++	u32	pull;
++	u32	drv_level;
++	u32	data;
++};
++
++/* config hardware resource */
++static int geth_hw_init(struct platform_device *pdev)
++{
++    struct net_device *ndev = platform_get_drvdata(pdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct device_node *np = pdev->dev.of_node;
++    int ret = 0;
++    struct resource *res;
++    u32 value;
++    struct gpio_config cfg;
++    const char *gmac_power;
++    char power[20];
++    int i;
++
++// #ifdef CONFIG_SUNXI_EXT_PHY
++    priv->phy_ext = EXT_PHY;
++// #else
++//     priv->phy_ext = INT_PHY;
++// #endif
++
++    /* config memery resource */
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++    if (unlikely(!res)) {
++        pr_err("%s: ERROR: get gmac memory failed", __func__);
++        return -ENODEV;
++    }
++
++    priv->base = devm_ioremap_resource(&pdev->dev, res);
++    if (!priv->base) {
++        pr_err("%s: ERROR: gmac memory mapping failed", __func__);
++        return -ENOMEM;
++    }
++
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++    if (unlikely(!res)) {
++        pr_err("%s: ERROR: get phy memory failed", __func__);
++        ret = -ENODEV;
++        goto mem_err;
++    }
++
++    priv->base_phy = devm_ioremap_resource(&pdev->dev, res);
++    if (unlikely(!priv->base_phy)) {
++        pr_err("%s: ERROR: phy memory mapping failed", __func__);
++        ret = -ENOMEM;
++        goto mem_err;
++    }
++
++    /* config IRQ */
++    ndev->irq = platform_get_irq_byname(pdev, "gmacirq");
++    if (ndev->irq == -ENXIO) {
++        pr_err("%s: ERROR: MAC IRQ not found\n", __func__);
++        ret = -ENXIO;
++        goto irq_err;
++    }
++
++    ret = request_irq(ndev->irq, geth_interrupt, IRQF_SHARED, dev_name(&pdev->dev), ndev);
++    if (unlikely(ret < 0)) {
++        pr_err("Could not request irq %d, error: %d\n", ndev->irq, ret);
++        goto irq_err;
++    }
++
++    /* config clock */
++    priv->geth_clk = of_clk_get_by_name(np, "bus-emac1");
++    if (unlikely(!priv->geth_clk || IS_ERR(priv->geth_clk))) {
++        pr_err("Get gmac clock failed!\n");
++        ret = -EINVAL;
++        goto clk_err;
++    }
++
++    if (INT_PHY == priv->phy_ext) {
++        priv->ephy_clk = of_clk_get_by_name(np, "emac-25m");
++        if (unlikely(IS_ERR_OR_NULL(priv->ephy_clk))) {
++            pr_err("Get ephy clock failed!\n");
++            ret = -EINVAL;
++            goto clk_err;
++        }
++    }
++#if 1 // defined(CONFIG_ARCH_SUN8IW12) || defined(CONFIG_ARCH_SUN50IW9)
++    else {
++        if (!of_property_read_u32(np, "use_ephy25m", &g_use_ephy_clk)
++                && g_use_ephy_clk) {
++            priv->ephy_clk = of_clk_get_by_name(np, "ephy");
++            if (unlikely(IS_ERR_OR_NULL(priv->ephy_clk))) {
++                pr_err("Get ephy clk failed!\n");
++                ret = -EINVAL;
++                goto clk_err;
++            }
++        }
++    }
++#endif
++
++    /* config power regulator */
++    if (EXT_PHY == priv->phy_ext) {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            snprintf(power, 15, "gmac-power%d", i);
++            ret = of_property_read_string(np, power, &gmac_power);
++            if (ret) {
++                priv->gmac_power[i] = NULL;
++                pr_info("gmac-power%d: NULL\n", i);
++                continue;
++            }
++            priv->gmac_power[i] = regulator_get(NULL, gmac_power);
++            if (IS_ERR(priv->gmac_power[i])) {
++                pr_err("gmac-power%d get error!\n", i);
++                ret = -EINVAL;
++                goto clk_err;
++            }
++        }
++    }
++
++    // /* config other parameters */
++    // priv->phy_interface = of_get_phy_mode(np);
++    // if (priv->phy_interface != PHY_INTERFACE_MODE_MII &&
++    //     priv->phy_interface != PHY_INTERFACE_MODE_RGMII &&
++    //     priv->phy_interface != PHY_INTERFACE_MODE_RMII) {
++    //     pr_err("Not support phy type!\n");
++    //     priv->phy_interface = PHY_INTERFACE_MODE_MII;
++    // }
++
++    priv->phy_interface = PHY_INTERFACE_MODE_RMII;
++
++    if (!of_property_read_u32(np, "tx-delay", &value))
++        tx_delay = value;
++
++    if (!of_property_read_u32(np, "rx-delay", &value))
++        rx_delay = value;
++
++    /* config pinctrl */
++    if (EXT_PHY == priv->phy_ext) {
++        priv->phyrst = of_get_named_gpio_flags(np, "phy-rst", 0, (enum of_gpio_flags *)&cfg);
++        priv->rst_active_low = (cfg.data == OF_GPIO_ACTIVE_LOW) ? 1 : 0;
++
++        if (gpio_is_valid(priv->phyrst)) {
++            if (gpio_request(priv->phyrst, "phy-rst") < 0) {
++                pr_err("gmac gpio request fail!\n");
++                ret = -EINVAL;
++                goto pin_err;
++            }
++        }
++
++        priv->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++        if (IS_ERR_OR_NULL(priv->pinctrl)) {
++            pr_err("gmac pinctrl error!\n");
++            priv->pinctrl = NULL;
++            ret = -EINVAL;
++            goto pin_err;
++        }
++    }
++
++    priv->ephy_rst = devm_reset_control_get_optional(&pdev->dev, "stmmaceth");
++    reset_control_assert(priv->ephy_rst);
++    reset_control_deassert(priv->ephy_rst);
++
++    msleep(800);
++
++    return 0;
++
++pin_err:
++    if (EXT_PHY == priv->phy_ext) {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            regulator_put(priv->gmac_power[i]);
++        }
++    }
++clk_err:
++    free_irq(ndev->irq, ndev);
++irq_err:
++    devm_iounmap(&pdev->dev, priv->base_phy);
++mem_err:
++    devm_iounmap(&pdev->dev, priv->base);
++
++    return ret;
++}
++
++static void geth_hw_release(struct platform_device *pdev)
++{
++    struct net_device *ndev = platform_get_drvdata(pdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    int i;
++
++    devm_iounmap(&pdev->dev, (priv->base_phy));
++    devm_iounmap(&pdev->dev, priv->base);
++    free_irq(ndev->irq, ndev);
++    if (priv->geth_clk)
++        clk_put(priv->geth_clk);
++
++    if (EXT_PHY == priv->phy_ext) {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            regulator_put(priv->gmac_power[i]);
++        }
++
++        if (!IS_ERR_OR_NULL(priv->pinctrl))
++            devm_pinctrl_put(priv->pinctrl);
++
++        if (gpio_is_valid(priv->phyrst))
++            gpio_free(priv->phyrst);
++    }
++
++    if (!IS_ERR_OR_NULL(priv->ephy_clk))
++        clk_put(priv->ephy_clk);
++}
++
++/**
++ * geth_probe
++ * @pdev: platform device pointer
++ * Description: the driver is initialized through platform_device.
++ */
++static int geth_probe(struct platform_device *pdev)
++{
++    int ret = 0;
++    struct net_device *ndev = NULL;
++    struct geth_priv *priv;
++
++#ifdef CONFIG_OF
++    pdev->dev.dma_mask = &geth_dma_mask;
++    pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++#endif
++
++    ndev = alloc_etherdev(sizeof(struct geth_priv));
++    if (!ndev) {
++        dev_err(&pdev->dev, "could not allocate device.\n");
++        return -ENOMEM;
++    }
++    SET_NETDEV_DEV(ndev, &pdev->dev);
++
++    priv = netdev_priv(ndev);
++    platform_set_drvdata(pdev, ndev);
++
++    /* Must set private data to pdev, before call it */
++    ret = geth_hw_init(pdev);
++    if (0 != ret) {
++        pr_err("geth_hw_init fail!\n");
++        goto hw_err;
++    }
++
++    /* setup the netdevice, fill the field of netdevice */
++    ether_setup(ndev);
++    ndev->netdev_ops = &geth_netdev_ops;
++    netdev_set_default_ethtool_ops(ndev, &geth_ethtool_ops);
++    ndev->base_addr = (unsigned long)priv->base;
++
++    priv->ndev = ndev;
++    priv->dev = &pdev->dev;
++
++    /* TODO: support the VLAN frames */
++    ndev->hw_features = NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_IP_CSUM |
++                        NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
++
++    ndev->features |= ndev->hw_features;
++    ndev->hw_features |= NETIF_F_LOOPBACK;
++    ndev->priv_flags |= IFF_UNICAST_FLT;
++
++    ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
++
++    netif_napi_add(ndev, &priv->napi, geth_poll);
++
++    spin_lock_init(&priv->lock);
++    spin_lock_init(&priv->tx_lock);
++
++    /* The last val is mdc clock ratio */
++    sunxi_geth_register((void *)ndev->base_addr, HW_VERSION, 0x03);
++
++    ret = register_netdev(ndev);
++    if (ret) {
++        netif_napi_del(&priv->napi);
++        pr_err("Error: Register %s failed\n", ndev->name);
++        goto reg_err;
++    }
++
++    /* Before open the device, the mac address should be set */
++    geth_check_addr(ndev, mac_str);
++
++#ifdef CONFIG_GETH_ATTRS
++    geth_create_attrs(ndev);
++#endif
++    device_create_file(&pdev->dev, &dev_attr_gphy_test);
++    device_create_file(&pdev->dev, &dev_attr_mii_read);
++    device_create_file(&pdev->dev, &dev_attr_mii_write);
++
++    device_enable_async_suspend(&pdev->dev);
++
++#ifdef CONFIG_PM
++    INIT_WORK(&priv->eth_work, geth_resume_work);
++#endif
++
++    return 0;
++
++reg_err:
++    geth_hw_release(pdev);
++hw_err:
++    platform_set_drvdata(pdev, NULL);
++    free_netdev(ndev);
++
++    return ret;
++}
++
++static int geth_remove(struct platform_device *pdev)
++{
++    struct net_device *ndev = platform_get_drvdata(pdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    device_remove_file(&pdev->dev, &dev_attr_gphy_test);
++    device_remove_file(&pdev->dev, &dev_attr_mii_read);
++    device_remove_file(&pdev->dev, &dev_attr_mii_write);
++
++    netif_napi_del(&priv->napi);
++    unregister_netdev(ndev);
++    geth_hw_release(pdev);
++    platform_set_drvdata(pdev, NULL);
++    free_netdev(ndev);
++
++    return 0;
++}
++
++static const struct of_device_id geth_of_match[] = {
++    {.compatible = "allwinner,sunxi-gmac",},
++    {},
++};
++MODULE_DEVICE_TABLE(of, geth_of_match);
++
++static struct platform_driver geth_driver = {
++    .probe = geth_probe,
++    .remove = geth_remove,
++	.suspend	= ucc_geth_suspend,
++	.resume		= ucc_geth_resume,
++    .driver = {
++        .name = "sunxi-gmac",
++        .owner = THIS_MODULE,
++        .pm = &geth_pm_ops,
++        .of_match_table = geth_of_match,
++    },
++};
++module_platform_driver(geth_driver);
++
++#ifndef MODULE
++static int __init set_mac_addr(char *str)
++{
++    char *p = str;
++
++    if (str && strlen(str))
++        memcpy(mac_str, p, 18);
++
++    return 0;
++}
++__setup("mac_addr=", set_mac_addr);
++#endif
++
++MODULE_DESCRIPTION("Allwinner Gigabit Ethernet driver");
++MODULE_AUTHOR("fuzhaoke <fuzhaoke@allwinnertech.com>");
++MODULE_LICENSE("Dual BSD/GPL");
+diff --git a/drivers/net/ethernet/allwinner/sunxi-gmac.h b/drivers/net/ethernet/allwinner/sunxi-gmac.h
+new file mode 100644
+index 000000000000..0ba8977d28f4
+--- /dev/null
++++ b/drivers/net/ethernet/allwinner/sunxi-gmac.h
+@@ -0,0 +1,270 @@
++/*
++ * linux/drivers/net/ethernet/allwinner/sunxi_gmac.h
++ *
++ * Copyright © 2016-2018, fuzhaoke
++ *		Author: fuzhaoke <fuzhaoke@allwinnertech.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ */
++#ifndef __SUNXI_GETH_H__
++#define __SUNXI_GETH_H__
++
++#include <linux/etherdevice.h>
++#include <linux/netdevice.h>
++#include <linux/phy.h>
++#include <linux/module.h>
++#include <linux/init.h>
++
++/* GETH_FRAME_FILTER  register value */
++#define GETH_FRAME_FILTER_PR	0x00000001	/* Promiscuous Mode */
++#define GETH_FRAME_FILTER_HUC	0x00000002	/* Hash Unicast */
++#define GETH_FRAME_FILTER_HMC	0x00000004	/* Hash Multicast */
++#define GETH_FRAME_FILTER_DAIF	0x00000008	/* DA Inverse Filtering */
++#define GETH_FRAME_FILTER_PM	0x00000010	/* Pass all multicast */
++#define GETH_FRAME_FILTER_DBF	0x00000020	/* Disable Broadcast frames */
++#define GETH_FRAME_FILTER_SAIF	0x00000100	/* Inverse Filtering */
++#define GETH_FRAME_FILTER_SAF	0x00000200	/* Source Address Filter */
++#define GETH_FRAME_FILTER_HPF	0x00000400	/* Hash or perfect Filter */
++#define GETH_FRAME_FILTER_RA	0x80000000	/* Receive all mode */
++
++/* Default tx descriptor */
++#define TX_SINGLE_DESC0		0x80000000
++#define TX_SINGLE_DESC1		0x63000000
++
++/* Default rx descriptor */
++#define RX_SINGLE_DESC0		0x80000000
++#define RX_SINGLE_DESC1		0x83000000
++
++#define EPHY_ID			0x00441400
++#define AC300_ID		0xc0000000
++#define EPHY_ID_RTL8211F	0x001CC916
++#define IP101G_ID		0x02430c54
++
++typedef union {
++	struct {
++		/* TDES0 */
++		unsigned int deferred:1;	/* Deferred bit (only half-duplex) */
++		unsigned int under_err:1;	/* Underflow error */
++		unsigned int ex_deferral:1;	/* Excessive deferral */
++		unsigned int coll_cnt:4;	/* Collision count */
++		unsigned int vlan_tag:1;	/* VLAN Frame */
++		unsigned int ex_coll:1;		/* Excessive collision */
++		unsigned int late_coll:1;	/* Late collision */
++		unsigned int no_carr:1;		/* No carrier */
++		unsigned int loss_carr:1;	/* Loss of collision */
++		unsigned int ipdat_err:1;	/* IP payload error */
++		unsigned int frm_flu:1;		/* Frame flushed */
++		unsigned int jab_timeout:1;	/* Jabber timeout */
++		unsigned int err_sum:1;		/* Error summary */
++		unsigned int iphead_err:1;	/* IP header error */
++		unsigned int ttss:1;		/* Transmit time stamp status */
++		unsigned int reserved0:13;
++		unsigned int own:1;		/* Own bit. CPU:0, DMA:1 */
++	} tx;
++
++	/* bits 5 7 0 | Frame status
++	 * ----------------------------------------------------------
++	 *      0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
++	 *      1 0 0 | IPv4/6 No CSUM errorS.
++	 *      1 0 1 | IPv4/6 CSUM PAYLOAD error
++	 *      1 1 0 | IPv4/6 CSUM IP HR error
++	 *      1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS
++	 *      0 0 1 | IPv4/6 unsupported IP PAYLOAD
++	 *      0 1 1 | COE bypassed.. no IPv4/6 frame
++	 *      0 1 0 | Reserved.
++	 */
++	struct {
++		/* RDES0 */
++		unsigned int chsum_err:1;	/* Payload checksum error */
++		unsigned int crc_err:1;		/* CRC error */
++		unsigned int dribbling:1;	/* Dribble bit error */
++		unsigned int mii_err:1;		/* Received error (bit3) */
++		unsigned int recv_wt:1;		/* Received watchdog timeout */
++		unsigned int frm_type:1;	/* Frame type */
++		unsigned int late_coll:1;	/* Late Collision */
++		unsigned int ipch_err:1;	/* IPv header checksum error (bit7) */
++		unsigned int last_desc:1;	/* Laset descriptor */
++		unsigned int first_desc:1;	/* First descriptor */
++		unsigned int vlan_tag:1;	/* VLAN Tag */
++		unsigned int over_err:1;	/* Overflow error (bit11) */
++		unsigned int len_err:1;		/* Length error */
++		unsigned int sou_filter:1;	/* Source address filter fail */
++		unsigned int desc_err:1;	/* Descriptor error */
++		unsigned int err_sum:1;		/* Error summary (bit15) */
++		unsigned int frm_len:14;	/* Frame length */
++		unsigned int des_filter:1;	/* Destination address filter fail */
++		unsigned int own:1;		/* Own bit. CPU:0, DMA:1 */
++	#define RX_PKT_OK		0x7FFFB77C
++	#define RX_LEN			0x3FFF0000
++	} rx;
++
++	unsigned int all;
++} desc0_u;
++
++typedef union {
++	struct {
++		/* TDES1 */
++		unsigned int buf1_size:11;	/* Transmit buffer1 size */
++		unsigned int buf2_size:11;	/* Transmit buffer2 size */
++		unsigned int ttse:1;		/* Transmit time stamp enable */
++		unsigned int dis_pad:1;		/* Disable pad (bit23) */
++		unsigned int adr_chain:1;	/* Second address chained */
++		unsigned int end_ring:1;	/* Transmit end of ring */
++		unsigned int crc_dis:1;		/* Disable CRC */
++		unsigned int cic:2;		/* Checksum insertion control (bit27:28) */
++		unsigned int first_sg:1;	/* First Segment */
++		unsigned int last_seg:1;	/* Last Segment */
++		unsigned int interrupt:1;	/* Interrupt on completion */
++	} tx;
++
++	struct {
++		/* RDES1 */
++		unsigned int buf1_size:11;	/* Received buffer1 size */
++		unsigned int buf2_size:11;	/* Received buffer2 size */
++		unsigned int reserved1:2;
++		unsigned int adr_chain:1;	/* Second address chained */
++		unsigned int end_ring:1;		/* Received end of ring */
++		unsigned int reserved2:5;
++		unsigned int dis_ic:1;		/* Disable interrupt on completion */
++	} rx;
++
++	unsigned int all;
++} desc1_u;
++
++typedef struct dma_desc {
++	desc0_u desc0;
++	desc1_u desc1;
++	/* The address of buffers */
++	unsigned int	desc2;
++	/* Next desc's address */
++	unsigned int	desc3;
++} __attribute__((packed)) dma_desc_t;
++
++enum rx_frame_status { /* IPC status */
++	good_frame = 0,
++	discard_frame = 1,
++	csum_none = 2,
++	llc_snap = 4,
++};
++
++enum tx_dma_irq_status {
++	tx_hard_error = 1,
++	tx_hard_error_bump_tc = 2,
++	handle_tx_rx = 3,
++};
++
++struct geth_extra_stats {
++	/* Transmit errors */
++	unsigned long tx_underflow;
++	unsigned long tx_carrier;
++	unsigned long tx_losscarrier;
++	unsigned long vlan_tag;
++	unsigned long tx_deferred;
++	unsigned long tx_vlan;
++	unsigned long tx_jabber;
++	unsigned long tx_frame_flushed;
++	unsigned long tx_payload_error;
++	unsigned long tx_ip_header_error;
++
++	/* Receive errors */
++	unsigned long rx_desc;
++	unsigned long sa_filter_fail;
++	unsigned long overflow_error;
++	unsigned long ipc_csum_error;
++	unsigned long rx_collision;
++	unsigned long rx_crc;
++	unsigned long dribbling_bit;
++	unsigned long rx_length;
++	unsigned long rx_mii;
++	unsigned long rx_multicast;
++	unsigned long rx_gmac_overflow;
++	unsigned long rx_watchdog;
++	unsigned long da_rx_filter_fail;
++	unsigned long sa_rx_filter_fail;
++	unsigned long rx_missed_cntr;
++	unsigned long rx_overflow_cntr;
++	unsigned long rx_vlan;
++
++	/* Tx/Rx IRQ errors */
++	unsigned long tx_undeflow_irq;
++	unsigned long tx_process_stopped_irq;
++	unsigned long tx_jabber_irq;
++	unsigned long rx_overflow_irq;
++	unsigned long rx_buf_unav_irq;
++	unsigned long rx_process_stopped_irq;
++	unsigned long rx_watchdog_irq;
++	unsigned long tx_early_irq;
++	unsigned long fatal_bus_error_irq;
++
++	/* Extra info */
++	unsigned long threshold;
++	unsigned long tx_pkt_n;
++	unsigned long rx_pkt_n;
++	unsigned long poll_n;
++	unsigned long sched_timer_n;
++	unsigned long normal_irq_n;
++};
++
++struct mii_reg_dump {
++	u32 addr;
++	u16 reg;
++	u16 value;
++};
++
++int sunxi_mdio_read(void *,  int, int);
++int sunxi_mdio_write(void *, int, int, unsigned short);
++int sunxi_mdio_reset(void *);
++void sunxi_set_link_mode(void *iobase, int duplex, int speed);
++void sunxi_int_disable(void *);
++int sunxi_int_status(void *, struct geth_extra_stats *x);
++int sunxi_mac_init(void *, int txmode, int rxmode);
++void sunxi_set_umac(void *, unsigned char *, int);
++void sunxi_mac_enable(void *);
++void sunxi_mac_disable(void *);
++void sunxi_tx_poll(void *);
++void sunxi_int_enable(void *);
++void sunxi_start_rx(void *, unsigned long);
++void sunxi_start_tx(void *, unsigned long);
++void sunxi_stop_tx(void *);
++void sunxi_stop_rx(void *);
++void sunxi_hash_filter(void *iobase, unsigned long low, unsigned long high);
++void sunxi_set_filter(void *iobase, unsigned long flags);
++void sunxi_flow_ctrl(void *iobase, int duplex, int fc, int pause);
++void sunxi_mac_loopback(void *iobase, int enable);
++
++void desc_buf_set(struct dma_desc *p, unsigned long paddr, int size);
++void desc_set_own(struct dma_desc *p);
++void desc_init_chain(struct dma_desc *p, unsigned long paddr,  unsigned int size);
++void desc_tx_close(struct dma_desc *first, struct dma_desc *end, int csum_insert);
++void desc_init(struct dma_desc *p);
++int desc_get_tx_status(struct dma_desc *desc, struct geth_extra_stats *x);
++int desc_buf_get_len(struct dma_desc *desc);
++int desc_buf_get_addr(struct dma_desc *desc);
++int desc_get_rx_status(struct dma_desc *desc, struct geth_extra_stats *x);
++int desc_get_own(struct dma_desc *desc);
++int desc_get_tx_ls(struct dma_desc *desc);
++int desc_rx_frame_len(struct dma_desc *desc);
++
++int sunxi_mac_reset(void *iobase, void (*mdelay)(int), int n);
++int sunxi_geth_register(void *iobase, int version, unsigned int div);
++
++int sunxi_parse_read_str(char *str, u16 *addr, u16 *reg);
++int sunxi_parse_write_str(char *str, u16 *addr, u16 *reg, u16 *val);
++extern int ephy_is_enable(void);
++extern int gmac_ephy_shutdown(void);
++
++#if defined(CONFIG_ARCH_SUN8IW3) \
++	|| defined(CONFIG_ARCH_SUN9IW1) \
++	|| defined(CONFIG_ARCH_SUN7I)
++#define HW_VERSION	0
++#else
++#define HW_VERSION	1
++#endif
++
++#endif
+diff --git a/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c b/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
+new file mode 100644
+index 000000000000..926516835023
+--- /dev/null
++++ b/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
+@@ -0,0 +1,768 @@
++/*
++ * linux/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
++ *
++ * Copyright © 2016-2018, fuzhaoke
++ *		Author: fuzhaoke <fuzhaoke@allwinnertech.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ */
++#include <linux/kernel.h>
++#include <linux/ctype.h>
++#include <linux/printk.h>
++#include <linux/io.h>
++#include "sunxi-gmac.h"
++
++/******************************************************************************
++ *	sun8iw6 operations
++ *****************************************************************************/
++#define GETH_BASIC_CTL0		0x00
++#define GETH_BASIC_CTL1		0x04
++#define GETH_INT_STA		0x08
++#define GETH_INT_EN		0x0C
++#define GETH_TX_CTL0		0x10
++#define GETH_TX_CTL1		0x14
++#define GETH_TX_FLOW_CTL	0x1C
++#define GETH_TX_DESC_LIST	0x20
++#define GETH_RX_CTL0		0x24
++#define GETH_RX_CTL1		0x28
++#define GETH_RX_DESC_LIST	0x34
++#define GETH_RX_FRM_FLT		0x38
++#define GETH_RX_HASH0		0x40
++#define GETH_RX_HASH1		0x44
++#define GETH_MDIO_ADDR		0x48
++#define GETH_MDIO_DATA		0x4C
++#define GETH_ADDR_HI(reg)	(0x50 + ((reg) << 3))
++#define GETH_ADDR_LO(reg)	(0x54 + ((reg) << 3))
++#define GETH_TX_DMA_STA		0xB0
++#define GETH_TX_CUR_DESC	0xB4
++#define GETH_TX_CUR_BUF		0xB8
++#define GETH_RX_DMA_STA		0xC0
++#define GETH_RX_CUR_DESC	0xC4
++#define GETH_RX_CUR_BUF		0xC8
++#define GETH_RGMII_STA		0xD0
++
++#define RGMII_IRQ		0x00000001
++
++#define	CTL0_LM			0x02
++#define CTL0_DM			0x01
++#define CTL0_SPEED		0x04
++
++#define BURST_LEN		0x3F000000
++#define RX_TX_PRI		0x02
++#define SOFT_RST		0x01
++
++#define TX_FLUSH		0x01
++#define TX_MD			0x02
++#define TX_NEXT_FRM		0x04
++#define TX_TH			0x0700
++
++#define RX_FLUSH		0x01
++#define RX_MD			0x02
++#define RX_RUNT_FRM		0x04
++#define RX_TH			0x0030
++
++#define TX_INT			0x00001
++#define TX_STOP_INT		0x00002
++#define TX_UA_INT		0x00004
++#define TX_TOUT_INT		0x00008
++#define TX_UNF_INT		0x00010
++#define TX_EARLY_INT		0x00020
++#define RX_INT			0x00100
++#define RX_UA_INT		0x00200
++#define RX_STOP_INT		0x00400
++#define RX_TOUT_INT		0x00800
++#define RX_OVF_INT		0x01000
++#define RX_EARLY_INT		0x02000
++#define LINK_STA_INT		0x10000
++
++#define DISCARD_FRAME	-1
++#define GOOD_FRAME	0
++#define CSUM_NONE	2
++#define LLC_SNAP	4
++
++#define SF_DMA_MODE		1
++
++/* Flow Control defines */
++#define FLOW_OFF	0
++#define FLOW_RX		1
++#define FLOW_TX		2
++#define FLOW_AUTO	(FLOW_TX | FLOW_RX)
++
++#define HASH_TABLE_SIZE 64
++#define PAUSE_TIME 0x200
++#define GMAC_MAX_UNICAST_ADDRESSES	8
++
++/* PHY address */
++#define PHY_ADDR		0x01
++#define PHY_DM			0x0010
++#define PHY_AUTO_NEG		0x0020
++#define PHY_POWERDOWN		0x0080
++#define PHY_NEG_EN		0x1000
++
++#define MII_BUSY		0x00000001
++#define MII_WRITE		0x00000002
++#define MII_PHY_MASK		0x0000FFC0
++#define MII_CR_MASK		0x0000001C
++#define MII_CLK			0x00000008
++/* bits 4 3 2 | AHB1 Clock	| MDC Clock
++ * -------------------------------------------------------
++ *      0 0 0 | 60 ~ 100 MHz	| div-42
++ *      0 0 1 | 100 ~ 150 MHz	| div-62
++ *      0 1 0 | 20 ~ 35 MHz	| div-16
++ *      0 1 1 | 35 ~ 60 MHz	| div-26
++ *      1 0 0 | 150 ~ 250 MHz	| div-102
++ *      1 0 1 | 250 ~ 300 MHz	| div-124
++ *      1 1 x | Reserved	|
++ */
++
++enum csum_insertion {
++	cic_dis		= 0, /* Checksum Insertion Control */
++	cic_ip		= 1, /* Only IP header */
++	cic_no_pse	= 2, /* IP header but not pseudoheader */
++	cic_full	= 3, /* IP header and pseudoheader */
++};
++
++struct gethdev {
++	void *iobase;
++	unsigned int ver;
++	unsigned int mdc_div;
++};
++
++static struct gethdev hwdev;
++
++/***************************************************************************
++ * External interface
++ **************************************************************************/
++/* Set a ring desc buffer */
++void desc_init_chain(struct dma_desc *desc, unsigned long addr, unsigned int size)
++{
++	/* In chained mode the desc3 points to the next element in the ring.
++	 * The latest element has to point to the head.
++	 */
++	int i;
++	struct dma_desc *p = desc;
++	unsigned long dma_phy = addr;
++
++	for (i = 0; i < (size - 1); i++) {
++		dma_phy += sizeof(struct dma_desc);
++		p->desc3 = (unsigned int)dma_phy;
++		/* Chain mode */
++		p->desc1.all |= (1 << 24);
++		p++;
++	}
++	p->desc1.all |= (1 << 24);
++	p->desc3 = (unsigned int)addr;
++}
++
++int sunxi_mdio_read(void *iobase, int phyaddr, int phyreg)
++{
++	unsigned int value = 0;
++
++	/* Mask the MDC_DIV_RATIO */
++	value |= ((hwdev.mdc_div & 0x07) << 20);
++	value |= (((phyaddr << 12) & (0x0001F000)) |
++			((phyreg << 4) & (0x000007F0)) |
++			MII_BUSY);
++
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	writel(value, iobase + GETH_MDIO_ADDR);
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	return (int)readl(iobase + GETH_MDIO_DATA);
++}
++
++int sunxi_mdio_write(void *iobase, int phyaddr, int phyreg, unsigned short data)
++{
++	unsigned int value;
++
++	value = ((0x07 << 20) & readl(iobase + GETH_MDIO_ADDR)) |
++		 (hwdev.mdc_div << 20);
++	value |= (((phyaddr << 12) & (0x0001F000)) |
++		  ((phyreg << 4) & (0x000007F0))) |
++		  MII_WRITE | MII_BUSY;
++
++	/* Wait until any existing MII operation is complete */
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	/* Set the MII address register to write */
++	writel(data, iobase + GETH_MDIO_DATA);
++	writel(value, iobase + GETH_MDIO_ADDR);
++
++	/* Wait until any existing MII operation is complete */
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	return 0;
++}
++
++int sunxi_mdio_reset(void *iobase)
++{
++	writel((4 << 2), iobase + GETH_MDIO_ADDR);
++	return 0;
++}
++
++void sunxi_set_link_mode(void *iobase, int duplex, int speed)
++{
++	unsigned int ctrl = readl(iobase + GETH_BASIC_CTL0);
++
++	if (!duplex)
++		ctrl &= ~CTL0_DM;
++	else
++		ctrl |= CTL0_DM;
++
++	switch (speed) {
++	case 1000:
++		ctrl &= ~0x0C;
++		break;
++	case 100:
++	case 10:
++	default:
++		ctrl |= 0x08;
++		if (speed == 100)
++			ctrl |= 0x04;
++		else
++			ctrl &= ~0x04;
++		break;
++	}
++
++	writel(ctrl, iobase + GETH_BASIC_CTL0);
++}
++
++void sunxi_mac_loopback(void *iobase, int enable)
++{
++	int reg;
++
++	reg = readl(iobase + GETH_BASIC_CTL0);
++	if (enable)
++		reg |= 0x02;
++	else
++		reg &= ~0x02;
++	writel(reg, iobase + GETH_BASIC_CTL0);
++}
++
++void sunxi_flow_ctrl(void *iobase, int duplex, int fc, int pause)
++{
++	unsigned int flow = 0;
++
++	if (fc & FLOW_RX) {
++		flow = readl(iobase + GETH_RX_CTL0);
++		flow |= 0x10000;
++		writel(flow, iobase + GETH_RX_CTL0);
++	}
++
++	if (fc & FLOW_TX) {
++		flow = readl(iobase + GETH_TX_FLOW_CTL);
++		flow |= 0x00001;
++		writel(flow, iobase + GETH_TX_FLOW_CTL);
++	}
++
++	if (duplex) {
++		flow = readl(iobase + GETH_TX_FLOW_CTL);
++		flow |= (pause << 4);
++		writel(flow, iobase + GETH_TX_FLOW_CTL);
++	}
++}
++
++int sunxi_int_status(void *iobase, struct geth_extra_stats *x)
++{
++	int ret = 0;
++	/* read the status register (CSR5) */
++	unsigned int intr_status;
++
++	intr_status = readl(iobase + GETH_RGMII_STA);
++	if (intr_status & RGMII_IRQ)
++		readl(iobase + GETH_RGMII_STA);
++
++	intr_status = readl(iobase + GETH_INT_STA);
++
++	/* ABNORMAL interrupts */
++	if (intr_status & TX_UNF_INT) {
++		ret = tx_hard_error_bump_tc;
++		x->tx_undeflow_irq++;
++	}
++	if (intr_status & TX_TOUT_INT) {
++		x->tx_jabber_irq++;
++	}
++	if (intr_status & RX_OVF_INT) {
++		x->rx_overflow_irq++;
++	}
++	if (intr_status & RX_UA_INT) {
++		x->rx_buf_unav_irq++;
++	}
++	if (intr_status & RX_STOP_INT) {
++		x->rx_process_stopped_irq++;
++	}
++	if (intr_status & RX_TOUT_INT) {
++		x->rx_watchdog_irq++;
++	}
++	if (intr_status & TX_EARLY_INT) {
++		x->tx_early_irq++;
++	}
++	if (intr_status & TX_STOP_INT) {
++		x->tx_process_stopped_irq++;
++		ret = tx_hard_error;
++	}
++
++	/* TX/RX NORMAL interrupts */
++	if (intr_status & (TX_INT | RX_INT | RX_EARLY_INT | TX_UA_INT)) {
++		x->normal_irq_n++;
++		if (intr_status & (TX_INT | RX_INT))
++			ret = handle_tx_rx;
++	}
++	/* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
++	writel(intr_status & 0x3FFF, iobase + GETH_INT_STA);
++
++	return ret;
++}
++
++void sunxi_start_rx(void *iobase, unsigned long rxbase)
++{
++	unsigned int value;
++
++	/* Write the base address of Rx descriptor lists into registers */
++	writel(rxbase, iobase + GETH_RX_DESC_LIST);
++
++	value = readl(iobase + GETH_RX_CTL1);
++	value |= 0x40000000;
++	writel(value, iobase + GETH_RX_CTL1);
++}
++
++void sunxi_stop_rx(void *iobase)
++{
++	unsigned int value;
++
++	value = readl(iobase + GETH_RX_CTL1);
++	value &= ~0x40000000;
++	writel(value, iobase + GETH_RX_CTL1);
++}
++
++void sunxi_start_tx(void *iobase, unsigned long txbase)
++{
++	unsigned int value;
++
++	/* Write the base address of Tx descriptor lists into registers */
++	writel(txbase, iobase + GETH_TX_DESC_LIST);
++
++	value = readl(iobase + GETH_TX_CTL1);
++	value |= 0x40000000;
++	writel(value, iobase + GETH_TX_CTL1);
++}
++
++void sunxi_stop_tx(void *iobase)
++{
++	unsigned int value = readl(iobase + GETH_TX_CTL1);
++
++	value &= ~0x40000000;
++	writel(value, iobase + GETH_TX_CTL1);
++}
++
++static int sunxi_dma_init(void *iobase)
++{
++	unsigned int value;
++
++	/* Burst should be 8 */
++	value = (8 << 24);
++
++#ifdef CONFIG_GMAC_DA
++	value |= RX_TX_PRI;	/* Rx has priority over tx */
++#endif
++	writel(value, iobase + GETH_BASIC_CTL1);
++
++	/* Mask interrupts by writing to CSR7 */
++	writel(RX_INT | TX_INT | TX_UNF_INT, iobase + GETH_INT_EN);
++
++	return 0;
++}
++
++int sunxi_mac_init(void *iobase, int txmode, int rxmode)
++{
++	unsigned int value;
++
++	sunxi_dma_init(iobase);
++
++	/* Initialize the core component */
++	value = readl(iobase + GETH_TX_CTL0);
++	value |= (1 << 30);	/* Jabber Disable */
++	writel(value, iobase + GETH_TX_CTL0);
++
++	value = readl(iobase + GETH_RX_CTL0);
++	value |= (1 << 27);	/* Enable CRC & IPv4 Header Checksum */
++	value |= (1 << 28);	/* Automatic Pad/CRC Stripping */
++	value |= (1 << 29);	/* Jumbo Frame Enable */
++	writel(value, iobase + GETH_RX_CTL0);
++
++	writel((hwdev.mdc_div << 20), iobase + GETH_MDIO_ADDR); /* MDC_DIV_RATIO */
++
++	/* Set the Rx&Tx mode */
++	value = readl(iobase + GETH_TX_CTL1);
++	if (txmode == SF_DMA_MODE) {
++		/* Transmit COE type 2 cannot be done in cut-through mode. */
++		value |= TX_MD;
++		/* Operating on second frame increase the performance
++		 * especially when transmit store-and-forward is used.
++		 */
++		value |= TX_NEXT_FRM;
++	} else {
++		value &= ~TX_MD;
++		value &= ~TX_TH;
++		/* Set the transmit threshold */
++		if (txmode <= 64)
++			value |= 0x00000000;
++		else if (txmode <= 128)
++			value |= 0x00000100;
++		else if (txmode <= 192)
++			value |= 0x00000200;
++		else
++			value |= 0x00000300;
++	}
++	writel(value, iobase + GETH_TX_CTL1);
++
++	value = readl(iobase + GETH_RX_CTL1);
++	if (rxmode == SF_DMA_MODE) {
++		value |= RX_MD;
++	} else {
++		value &= ~RX_MD;
++		value &= ~RX_TH;
++		if (rxmode <= 32)
++			value |= 0x10;
++		else if (rxmode <= 64)
++			value |= 0x00;
++		else if (rxmode <= 96)
++			value |= 0x20;
++		else
++			value |= 0x30;
++	}
++	writel(value, iobase + GETH_RX_CTL1);
++
++	return 0;
++}
++
++void sunxi_hash_filter(void *iobase, unsigned long low, unsigned long high)
++{
++	writel(high, iobase + GETH_RX_HASH0);
++	writel(low, iobase + GETH_RX_HASH1);
++}
++
++void sunxi_set_filter(void *iobase, unsigned long flags)
++{
++	int tmp_flags;
++
++	tmp_flags = readl(iobase + GETH_RX_FRM_FLT);
++
++	tmp_flags |= ((flags >> 31) |
++			((flags >> 9) & 0x00000002) |
++			((flags << 1) & 0x00000010) |
++			((flags >> 3) & 0x00000060) |
++			((flags << 7) & 0x00000300) |
++			((flags << 6) & 0x00003000) |
++			((flags << 12) & 0x00030000) |
++			(flags << 31));
++
++	writel(tmp_flags, iobase + GETH_RX_FRM_FLT);
++}
++
++void sunxi_set_umac(void *iobase, unsigned char *addr, int index)
++{
++	unsigned long data;
++
++	data = (addr[5] << 8) | addr[4];
++	writel(data, iobase + GETH_ADDR_HI(index));
++	data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
++	writel(data, iobase + GETH_ADDR_LO(index));
++}
++
++void sunxi_mac_enable(void *iobase)
++{
++	unsigned long value;
++
++	value = readl(iobase + GETH_TX_CTL0);
++	value |= (1 << 31);
++	writel(value, iobase + GETH_TX_CTL0);
++
++	value = readl(iobase + GETH_RX_CTL0);
++	value |= (1 << 31);
++	writel(value, iobase + GETH_RX_CTL0);
++}
++
++void sunxi_mac_disable(void *iobase)
++{
++	unsigned long value;
++
++	value = readl(iobase + GETH_TX_CTL0);
++	value &= ~(1 << 31);
++	writel(value, iobase + GETH_TX_CTL0);
++
++	value = readl(iobase + GETH_RX_CTL0);
++	value &= ~(1 << 31);
++	writel(value, iobase + GETH_RX_CTL0);
++}
++
++void sunxi_tx_poll(void *iobase)
++{
++	unsigned int value;
++
++	value = readl(iobase + GETH_TX_CTL1);
++	writel(value | 0x80000000, iobase + GETH_TX_CTL1);
++}
++
++void sunxi_rx_poll(void *iobase)
++{
++	unsigned int value;
++
++	value = readl(iobase + GETH_RX_CTL1);
++	writel(value | 0x80000000, iobase + GETH_RX_CTL1);
++}
++
++void sunxi_int_enable(void *iobase)
++{
++	writel(RX_INT | TX_INT | TX_UNF_INT, iobase + GETH_INT_EN);
++}
++
++void sunxi_int_disable(void *iobase)
++{
++	writel(0, iobase + GETH_INT_EN);
++}
++
++void desc_buf_set(struct dma_desc *desc, unsigned long paddr, int size)
++{
++	desc->desc1.all &= (~((1 << 11) - 1));
++	desc->desc1.all |= (size & ((1 << 11) - 1));
++	desc->desc2 = paddr;
++}
++
++void desc_set_own(struct dma_desc *desc)
++{
++	desc->desc0.all |= 0x80000000;
++}
++
++void desc_tx_close(struct dma_desc *first, struct dma_desc *end, int csum_insert)
++{
++	struct dma_desc *desc = first;
++
++	first->desc1.tx.first_sg = 1;
++	end->desc1.tx.last_seg = 1;
++	end->desc1.tx.interrupt = 1;
++
++	if (csum_insert)
++		do {
++			desc->desc1.tx.cic = 3;
++			desc++;
++		} while (desc <= end);
++}
++
++void desc_init(struct dma_desc *desc)
++{
++	desc->desc1.all = 0;
++	desc->desc2  = 0;
++
++	desc->desc1.all |= (1 << 24);
++}
++
++int desc_get_tx_status(struct dma_desc *desc, struct geth_extra_stats *x)
++{
++	int ret = 0;
++
++	if (desc->desc0.tx.under_err) {
++		x->tx_underflow++;
++		ret = -1;
++	}
++	if (desc->desc0.tx.no_carr) {
++		x->tx_carrier++;
++		ret = -1;
++	}
++	if (desc->desc0.tx.loss_carr) {
++		x->tx_losscarrier++;
++		ret = -1;
++	}
++
++#if 0
++	if ((desc->desc0.tx.ex_deferral) ||
++			(desc->desc0.tx.ex_coll) ||
++			(desc->desc0.tx.late_coll))
++		stats->collisions += desc->desc0.tx.coll_cnt;
++#endif
++
++	if (desc->desc0.tx.deferred)
++		x->tx_deferred++;
++
++	return ret;
++}
++
++int desc_buf_get_len(struct dma_desc *desc)
++{
++	return (desc->desc1.all & ((1 << 11) - 1));
++}
++
++int desc_buf_get_addr(struct dma_desc *desc)
++{
++	return desc->desc2;
++}
++
++int desc_rx_frame_len(struct dma_desc *desc)
++{
++	return desc->desc0.rx.frm_len;
++}
++
++int desc_get_rx_status(struct dma_desc *desc, struct geth_extra_stats *x)
++{
++	int ret = good_frame;
++
++	if (desc->desc0.rx.last_desc == 0) {
++		return discard_frame;
++	}
++
++	if (desc->desc0.rx.err_sum) {
++		if (desc->desc0.rx.desc_err)
++			x->rx_desc++;
++
++		if (desc->desc0.rx.sou_filter)
++			x->sa_filter_fail++;
++
++		if (desc->desc0.rx.over_err)
++			x->overflow_error++;
++
++		if (desc->desc0.rx.ipch_err)
++			x->ipc_csum_error++;
++
++		if (desc->desc0.rx.late_coll)
++			x->rx_collision++;
++
++		if (desc->desc0.rx.crc_err)
++			x->rx_crc++;
++
++		ret = discard_frame;
++	}
++
++	if (desc->desc0.rx.len_err) {
++		ret = discard_frame;
++	}
++	if (desc->desc0.rx.mii_err) {
++		ret = discard_frame;
++	}
++
++	return ret;
++}
++
++int desc_get_own(struct dma_desc *desc)
++{
++	return desc->desc0.all & 0x80000000;
++}
++
++int desc_get_tx_ls(struct dma_desc *desc)
++{
++	return desc->desc1.tx.last_seg;
++}
++
++int sunxi_geth_register(void *iobase, int version, unsigned int div)
++{
++	hwdev.ver = version;
++	hwdev.iobase = iobase;
++	hwdev.mdc_div = div;
++
++	return 0;
++}
++
++int sunxi_mac_reset(void *iobase, void (*delay)(int), int n)
++{
++	unsigned int value;
++
++	/* DMA SW reset */
++	value = readl(iobase + GETH_BASIC_CTL1);
++	value |= SOFT_RST;
++	writel(value, iobase + GETH_BASIC_CTL1);
++
++	delay(n);
++
++	return !!(readl(iobase + GETH_BASIC_CTL1) & SOFT_RST);
++}
++
++/**
++ * sunxi_parse_read_str - parse the input string for write attri.
++ * @str: string to be parsed, eg: "0x00 0x01".
++ * @addr: store the reg address. eg: 0x00.
++ * @reg: store the expect value. eg: 0x01.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int sunxi_parse_read_str(char *str, u16 *addr, u16 *reg)
++{
++	char *ptr = str;
++	char *tstr = NULL;
++	int ret;
++
++	/*
++	 * Skip the leading whitespace, find the true split symbol.
++	 * And it must be 'address value'.
++	 */
++	tstr = strim(str);
++	ptr = strchr(tstr, ' ');
++	if (!ptr)
++		return -EINVAL;
++
++	/*
++	 * Replaced split symbol with a %NUL-terminator temporary.
++	 * Will be fixed at end.
++	 */
++	*ptr = '\0';
++	ret = kstrtos16(tstr, 16, addr);
++	if (ret)
++		goto out;
++
++	ret = kstrtos16(skip_spaces(ptr + 1), 16, reg);
++
++out:
++	return ret;
++}
++
++/**
++ * sunxi_parse_write_str - parse the input string for compare attri.
++ * @str: string to be parsed, eg: "0x00 0x11 0x11".
++ * @addr: store the address. eg: 0x00.
++ * @reg: store the reg. eg: 0x11.
++ * @val: store the value. eg: 0x11.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int sunxi_parse_write_str(char *str, u16 *addr,
++			  u16 *reg, u16 *val)
++{
++	u16 result_addr[3] = { 0 };
++	char *ptr = str;
++	char *ptr2 = NULL;
++	int i, ret = 0;
++
++	for (i = 0; i < ARRAY_SIZE(result_addr); i++) {
++		ptr = skip_spaces(ptr);
++		ptr2 = strchr(ptr, ' ');
++		if (ptr2)
++			*ptr2 = '\0';
++
++		ret = kstrtou16(ptr, 16, &result_addr[i]);
++		if (!ptr2)
++			break;
++
++		*ptr2 = ' ';
++
++		if (ret)
++			break;
++
++		ptr = ptr2 + 1;
++	}
++
++	*addr = result_addr[0];
++	*reg = result_addr[1];
++	*val = result_addr[2];
++
++	return ret;
++}
++MODULE_LICENSE("Dual BSD/GPL");
+diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
+index 43edfd9d61dc..0283b463cad9 100644
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -75,6 +75,14 @@ config AC200_PHY
+ 	help
+ 	  Fast ethernet PHY as found in X-Powers AC200 multi-function device.
+ 
++config AC200_PHY_SUNXI
++	tristate "AC200 EPHY(Sunxi)"
++	depends on NVMEM
++	depends on OF
++	depends on MFD_AC200_SUNXI
++	help
++	  Fast ethernet PHY as found in X-Powers AC200(Sunxi) multi-function device.
++
+ config AMD_PHY
+ 	tristate "AMD PHYs"
+ 	help
+diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
+index e5a46da678ff..340df0674fcd 100644
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -33,6 +33,7 @@ sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
+ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
+ obj-$(CONFIG_AC200_PHY)		+= ac200-phy.o
++obj-$(CONFIG_AC200_PHY_SUNXI)		+= sunxi-ephy.o
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+diff --git a/drivers/net/phy/sunxi-ephy.c b/drivers/net/phy/sunxi-ephy.c
+new file mode 100644
+index 000000000000..92f5ba101ced
+--- /dev/null
++++ b/drivers/net/phy/sunxi-ephy.c
+@@ -0,0 +1,518 @@
++/*
++ * Copyright © 2015-2016, Shuge
++ *		Author: Sugar <shugeLinux@gmail.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/errno.h>
++#include <linux/unistd.h>
++#include <linux/interrupt.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/spinlock.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/mii.h>
++#include <linux/ethtool.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <linux/mfd/ac200.h>
++
++#define EPHY_AC200 1
++#define EPHY_AC300 2
++
++#define WAIT_MAX_COUNT 200
++
++struct ephy_res {
++	struct phy_device *ac300;
++	struct ac200_dev *ac200;
++	atomic_t ephy_en;
++};
++
++static struct ephy_res ac200_ephy;
++static struct ephy_res ac300_ephy;
++u8 ephy_type;
++
++static int ac200_reg_read(struct ac200_dev *ac200, unsigned short reg)
++{
++	unsigned int val;
++	int ret;
++
++	ret = regmap_read(ac200->regmap, reg, &val);
++
++	if (ret < 0)
++		return ret;
++	else
++		return val;
++}
++
++static int ac200_reg_write(struct ac200_dev *ac200, unsigned short reg, unsigned short val)
++{
++	return regmap_write(ac200->regmap, reg, val);
++}
++
++int ephy_is_enable(void)
++{
++	if (ephy_type == EPHY_AC200)
++		return atomic_read(&ac200_ephy.ephy_en);
++	else if (ephy_type == EPHY_AC300)
++		return atomic_read(&ac300_ephy.ephy_en);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ephy_is_enable);
++
++static void disable_intelligent_ieee(struct phy_device *phydev)
++{
++	unsigned int value;
++
++	phy_write(phydev, 0x1f, 0x0100); /* switch to page 1 */
++	value = phy_read(phydev, 0x17);  /* read address 0 0x17 register */
++	value &= ~(1 << 3);			  /* reg 0x17 bit 3, set 0 to disable IEEE */
++	phy_write(phydev, 0x17, value);
++	phy_write(phydev, 0x1f, 0x0000); /* switch to page 0 */
++}
++
++static void disable_802_3az_ieee(struct phy_device *phydev)
++{
++	unsigned int value;
++
++	phy_write(phydev, 0xd, 0x7);
++	phy_write(phydev, 0xe, 0x3c);
++	phy_write(phydev, 0xd, 0x1 << 14 | 0x7);
++	value = phy_read(phydev, 0xe);
++	value &= ~(0x1 << 1);
++	phy_write(phydev, 0xd, 0x7);
++	phy_write(phydev, 0xe, 0x3c);
++	phy_write(phydev, 0xd, 0x1 << 14 | 0x7);
++	phy_write(phydev, 0xe, value);
++
++	phy_write(phydev, 0x1f, 0x0200); /* switch to page 2 */
++	phy_write(phydev, 0x18, 0x0000);
++}
++
++static void ephy_config_default(struct phy_device *phydev)
++{
++	phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824); /* Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200); /* Switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600); /* Switch to Page 6 */
++	phy_write(phydev, 0x14, 0x708b); /* PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xF000); /* PHYAFE RX optimization */
++	phy_write(phydev, 0x15, 0x1530);
++
++	phy_write(phydev, 0x1f, 0x0800); /* Switch to Page 8 */
++	phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */
++}
++
++static void __maybe_unused ephy_config_fixed(struct phy_device *phydev)
++{
++	phy_write(phydev, 0x1f, 0x0100); /*switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824); /*Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200); /*switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000); /*PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600); /*switch to Page 6 */
++	phy_write(phydev, 0x14, 0x7809); /*PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xf000); /*PHYAFE RX optimization */
++	phy_write(phydev, 0x10, 0x5523);
++	phy_write(phydev, 0x15, 0x3533);
++
++	phy_write(phydev, 0x1f, 0x0800); /*switch to Page 8 */
++	phy_write(phydev, 0x1d, 0x0844); /*disable auto offset */
++	phy_write(phydev, 0x18, 0x00bc); /*PHYAFE TRX optimization */
++}
++
++static void __maybe_unused ephy_config_cali(struct phy_device *phydev, u16 ephy_cali)
++{
++	int value;
++	value = phy_read(phydev, 0x06);
++	value &= ~(0x0F << 12);
++	value |= (0x0F & (0x03 + ephy_cali)) << 12;
++	phy_write(phydev, 0x06, value);
++
++	return;
++}
++
++int ephy_config_init(struct phy_device *phydev)
++{
++	int value;
++#if 1 //defined(CONFIG_ARCH_SUN50IW9)
++	if (ephy_type == EPHY_AC300) {
++		int ret;
++		u16 ephy_cali = 0;
++		ephy_cali = sun50i_ephy_calibrate_value();
++		if (ret) {
++			pr_err("ephy cali efuse read fail!\n");
++			return -1;
++		}
++		ephy_config_cali(ac300_ephy.ac300, ephy_cali);
++		/*
++		* BIT9: the flag of calibration value
++		* 0: Normal
++		* 1: Low level of calibration value
++		*/
++		if (ephy_cali & BIT(9)) {
++			pr_debug("ac300:ephy cali efuse read: fixed!\n");
++			ephy_config_fixed(phydev);
++		} else {
++			pr_debug("ac300:ephy cali efuse read: default!\n");
++			ephy_config_default(phydev);
++		}
++	} else {
++		pr_debug("ac200:ephy cali efuse read: default!\n");
++		ephy_config_default(phydev);
++	}
++#else
++	ephy_config_default(phydev);
++#endif
++
++#if 0
++	/* Disable Auto Power Saving mode */
++	phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
++	value = phy_read(phydev, 0x17);
++	value &= ~BIT(13);
++	phy_write(phydev, 0x17, value);
++#endif
++	disable_intelligent_ieee(phydev); /* Disable Intelligent IEEE */
++	disable_802_3az_ieee(phydev);  /* Disable 802.3az IEEE */
++	phy_write(phydev, 0x1f, 0x0000); /* Switch to Page 0 */
++
++#if 1 // def CONFIG_MFD_ACX00
++	if (ephy_type == EPHY_AC200) {
++		value = ac200_reg_read(ac200_ephy.ac200, AC200_EPHY_CTL);
++		if (phydev->interface == PHY_INTERFACE_MODE_RMII)
++			value |= (1 << 11);
++		else
++			value &= (~(1 << 11));
++		ac200_reg_write(ac200_ephy.ac200, AC200_EPHY_CTL, value | (1 << 11));
++	} else
++#endif
++	if (ephy_type == EPHY_AC300) {
++		value = phy_read(ac300_ephy.ac300, 0x06);
++		if (phydev->interface == PHY_INTERFACE_MODE_RMII)
++			value |= (1 << 11);
++		else
++			value &= (~(1 << 11));
++		phy_write(ac300_ephy.ac300, 0x06, value | (1 << 1)); /*LED_POL 1:Low active*/
++	}
++
++#if defined(CONFIG_ARCH_SUN50IW6)
++	value = phy_read(phydev, 0x13);
++	value |= 1 << 12;
++	phy_write(phydev, 0x13, value);
++#endif
++
++	return 0;
++}
++EXPORT_SYMBOL(ephy_config_init);
++
++static int ephy_probe(struct phy_device *phydev)
++{
++	return 0;
++}
++
++#if 0
++static int ephy_ack_interrupt(struct phy_device *phydev)
++{
++	int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
++
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++#endif
++
++
++static struct phy_driver sunxi_phy_driver = {
++	.phy_id = 0x00441400,
++	.name = "ephy",
++	.phy_id_mask = 0x0ffffff0,
++	.features = PHY_BASIC_FEATURES, //| SUPPORTED_Pause |SUPPORTED_Asym_Pause,
++#if 0
++	.flags = PHY_HAS_INTERRUPT,
++	.ack_interrupt = ephy_ack_interrupt,
++#endif
++	.config_init = &ephy_config_init,
++	.config_aneg = &genphy_config_aneg,
++	.read_status = &genphy_read_status,
++	.suspend = genphy_suspend,
++	.resume = genphy_resume,
++	.probe = ephy_probe,
++};
++
++static void ac300_ephy_enable(struct ephy_res *priv)
++{
++	phy_write(priv->ac300, 0x00, 0x1f83); /* release reset */
++
++	phy_write(priv->ac300, 0x00, 0x1fb7); /* clk gating (24MHz clock)*/
++
++	//phy_write(priv->ac300, 0x05, 0xa81f);
++	phy_write(priv->ac300, 0x05, 0xa819);
++
++	phy_write(priv->ac300, 0x06, 0x00);
++
++	msleep(1000); /* FIXME: fix some board compatible issues. */
++
++	atomic_set(&ac300_ephy.ephy_en, 1);
++}
++
++static void ac300_ephy_disable(struct ephy_res *priv)
++{
++	phy_write(priv->ac300, 0x00, 0x1f40);
++	phy_write(priv->ac300, 0x05, 0xa800);
++
++	phy_write(priv->ac300, 0x06, 0x01);
++
++	atomic_set(&ac300_ephy.ephy_en, 0);
++}
++
++static int ac300_ephy_probe(struct phy_device *phydev)
++{
++	ac300_ephy.ac300 = phydev;
++
++	atomic_set(&ac300_ephy.ephy_en, 0);
++	ac300_ephy_enable(&ac300_ephy);
++
++	ephy_type = EPHY_AC300;
++
++	return 0;
++}
++
++static void ac300_ephy_shutdown(struct phy_device *phydev)
++{
++	ac300_ephy.ac300 = phydev;
++
++	phy_write(ac300_ephy.ac300, 0x00, 0x1f40);
++	phy_write(ac300_ephy.ac300, 0x05, 0xa800);
++	phy_write(ac300_ephy.ac300, 0x06, 0x01);
++}
++
++int gmac_ephy_shutdown(void)
++{
++	if (ephy_type == EPHY_AC300)
++		ac300_ephy_disable(&ac300_ephy);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(gmac_ephy_shutdown);
++
++static int ac300_ephy_suspend(struct phy_device *phydev)
++{
++	ac300_ephy_disable(&ac300_ephy);
++
++	return 0;
++}
++
++static int ac300_ephy_resume(struct phy_device *phydev)
++{
++	ac300_ephy_enable(&ac300_ephy);
++
++	return 0;
++}
++
++static struct phy_driver ac300_ephy_driver = {
++	.phy_id = 0xc0000000,
++	.name = "ac300",
++	.phy_id_mask = 0xffffffff,
++	.suspend = ac300_ephy_suspend,
++	.resume = ac300_ephy_resume,
++	.probe = ac300_ephy_probe,
++	// .shutdown = ac300_ephy_shutdown,
++};
++
++
++static void ac200_ephy_enable(struct ephy_res *priv)
++{
++#if 1 //ifdef CONFIG_MFD_ACX00
++	int value;
++	unsigned char i = 0;
++#if 1 // defined(CONFIG_ARCH_SUN50IW6) || defined(CONFIG_ARCH_SUN50IW9)
++	u16 ephy_cali = 0;
++#endif
++
++	if (!ac200_enable()) {
++		for (i = 0; i < WAIT_MAX_COUNT; i++) {
++			msleep(10);
++			if (ac200_enable())
++			break;
++		}
++		if (i == WAIT_MAX_COUNT) {
++			pr_err("acx00 is no enable, and ac200_ephy_enable is fail\n");
++			return;
++		}
++	}
++
++	value = ac200_reg_read(priv->ac200, AC200_SYS_EPHY_CTL0);
++	value |= 0x03;
++	ac200_reg_write(priv->ac200, AC200_SYS_EPHY_CTL0, value);
++	value = ac200_reg_read(priv->ac200, AC200_SYS_EPHY_CTL1);
++
++	value |= 0x0f;
++
++	ac200_reg_write(priv->ac200, AC200_SYS_EPHY_CTL1, value);
++	ac200_reg_write(priv->ac200, AC200_EPHY_CTL, 0x06);
++
++	/*for ephy */
++	value = ac200_reg_read(priv->ac200, AC200_EPHY_CTL);
++	value &= ~(0xf << 12);
++
++#if 1 // defined(CONFIG_ARCH_SUN50IW6) || defined(CONFIG_ARCH_SUN50IW9)
++
++	ephy_cali = sun50i_ephy_calibrate_value();
++	value |= (0x0F & (0x03 + ephy_cali)) << 12;
++#else
++	value |= (0x0F & (0x03 + ac200_reg_read(priv->ac200, AC200_SID))) << 12;
++#endif
++
++	ac200_reg_write(priv->ac200, AC200_EPHY_CTL, value);
++
++	atomic_set(&ac200_ephy.ephy_en, 1);
++#endif
++}
++
++static void ac200_ephy_disable(struct ephy_res *priv)
++{
++	int value;
++
++	/* reset ephy */
++	value = ac200_reg_read(priv->ac200, AC200_SYS_EPHY_CTL0);
++	value &= ~0x01;
++	ac200_reg_write(priv->ac200, AC200_SYS_EPHY_CTL0, value);
++
++	/* shutdown ephy */
++	value = ac200_reg_read(priv->ac200, AC200_EPHY_CTL);
++	value |= 0x01;
++	ac200_reg_write(priv->ac200, AC200_EPHY_CTL, value);
++
++	atomic_set(&priv->ephy_en, 0);
++}
++
++static const struct platform_device_id ac200_ephy_id[] = {
++	{ "ac200-ephy", 0},
++	{ },
++};
++MODULE_DEVICE_TABLE(platform, ac200_ephy_id);
++
++static int ac200_ephy_probe(struct platform_device *pdev)
++{
++	struct ac200_dev *ax = dev_get_drvdata(pdev->dev.parent);
++
++	if (!ax)
++		return -ENODEV;
++
++	ac200_ephy.ac200 = ax;
++	ephy_type = EPHY_AC200;
++	platform_set_drvdata(pdev, &ac200_ephy);
++
++	atomic_set(&ac200_ephy.ephy_en, 0);
++	ac200_ephy_enable(&ac200_ephy);
++
++	return 0;
++}
++
++static int ac200_ephy_remove(struct platform_device *pdev)
++{
++	ac200_ephy_disable(&ac200_ephy);
++
++	return 0;
++}
++
++static int ac200_ephy_suspend(struct device *dev)
++{
++	ac200_ephy_disable(&ac200_ephy);
++
++	return 0;
++}
++
++static int ac200_ephy_resume(struct device *dev)
++{
++	ac200_ephy_enable(&ac200_ephy);
++
++	return 0;
++}
++
++/* Suspend hook structures */
++static const struct dev_pm_ops ac200_ephy_pm_ops = {
++	.suspend = ac200_ephy_suspend,
++	.resume = ac200_ephy_resume,
++};
++
++static struct platform_driver ac200_ephy_driver = {
++	.driver = {
++		.name = "ac200-ephy-sunxi",
++		.owner = THIS_MODULE,
++		.pm = &ac200_ephy_pm_ops,
++	},
++	.probe = ac200_ephy_probe,
++	.remove = ac200_ephy_remove,
++	.id_table = ac200_ephy_id,
++};
++
++static int ephy_init(void)
++{
++	int ret = 0;
++
++	ret = platform_driver_register(&ac200_ephy_driver);
++	if (ret)
++		return ret;
++
++	ret = phy_driver_register(&ac300_ephy_driver, THIS_MODULE);
++	if (ret)
++		goto ac300_ephy_error;
++
++	ret = phy_driver_register(&sunxi_phy_driver, THIS_MODULE);
++	if (ret)
++		goto ephy_driver_error;
++
++	return ret;
++
++ephy_driver_error:
++	phy_driver_unregister(&ac300_ephy_driver);
++
++ac300_ephy_error:
++	platform_driver_unregister(&ac200_ephy_driver);
++
++	return ret;
++}
++
++static void ephy_exit(void)
++{
++	phy_driver_unregister(&sunxi_phy_driver);
++	phy_driver_unregister(&ac300_ephy_driver);
++	platform_driver_unregister(&ac200_ephy_driver);
++}
++
++module_init(ephy_init);
++module_exit(ephy_exit);
++
++static struct mdio_device_id __maybe_unused ephy_tbl[] = {
++	{ 0x00441400, 0x0ffffff0 },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, ephy_tbl);
++
++MODULE_DESCRIPTION("Allwinner EPHY drivers");
++MODULE_AUTHOR("Sugar <shugeLinux@gmail.com>");
++MODULE_LICENSE("GPL");
+diff --git a/include/linux/mfd/ac200.h b/include/linux/mfd/ac200.h
+new file mode 100644
+index 000000000000..84d89cbfbd3d
+--- /dev/null
++++ b/include/linux/mfd/ac200.h
+@@ -0,0 +1,213 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * AC200 register list
++ *
++ * Copyright (C) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#ifndef __LINUX_MFD_AC200_H
++#define __LINUX_MFD_AC200_H
++
++#include <linux/regmap.h>
++#include <linux/clk.h>
++
++/* interface registers (can be accessed from any page) */
++#define AC200_TWI_CHANGE_TO_RSB		0x3E
++#define AC200_TWI_PAD_DELAY		0xC4
++#define AC200_TWI_REG_ADDR_H		0xFE
++
++/* General registers */
++#define AC200_SYS_VERSION		0x0000
++#define AC200_SYS_CONTROL		0x0002
++#define AC200_SYS_IRQ_ENABLE		0x0004
++#define AC200_SYS_IRQ_STATUS		0x0006
++#define AC200_SYS_CLK_CTL		0x0008
++#define AC200_SYS_DLDO_OSC_CTL		0x000A
++#define AC200_SYS_PLL_CTL0		0x000C
++#define AC200_SYS_PLL_CTL1		0x000E
++#define AC200_SYS_AUDIO_CTL0		0x0010
++#define AC200_SYS_AUDIO_CTL1		0x0012
++#define AC200_SYS_EPHY_CTL0		0x0014
++#define AC200_SYS_EPHY_CTL1		0x0016
++#define AC200_SYS_TVE_CTL0		0x0018
++#define AC200_SYS_TVE_CTL1		0x001A
++
++/* Audio Codec registers */
++#define AC200_AC_SYS_CLK_CTL		0x2000
++#define AC200_SYS_MOD_RST		0x2002
++#define AC200_SYS_SAMP_CTL		0x2004
++#define AC200_I2S_CTL			0x2100
++#define AC200_I2S_CLK			0x2102
++#define AC200_I2S_FMT0			0x2104
++#define AC200_I2S_FMT1			0x2108
++#define AC200_I2S_MIX_SRC		0x2114
++#define AC200_I2S_MIX_GAIN		0x2116
++#define AC200_I2S_DACDAT_DVC		0x2118
++#define AC200_I2S_ADCDAT_DVC		0x211A
++#define AC200_AC_DAC_DPC		0x2200
++#define AC200_AC_DAC_MIX_SRC		0x2202
++#define AC200_AC_DAC_MIX_GAIN		0x2204
++#define AC200_DACA_OMIXER_CTRL		0x2220
++#define AC200_OMIXER_SR			0x2222
++#define AC200_LINEOUT_CTRL		0x2224
++#define AC200_AC_ADC_DPC		0x2300
++#define AC200_MBIAS_CTRL		0x2310
++#define AC200_ADC_MIC_CTRL		0x2320
++#define AC200_ADCMIXER_SR		0x2322
++#define AC200_ANALOG_TUNING0		0x232A
++#define AC200_ANALOG_TUNING1		0x232C
++#define AC200_AC_AGC_SEL		0x2480
++#define AC200_ADC_DAPLCTRL		0x2500
++#define AC200_ADC_DAPRCTRL		0x2502
++#define AC200_ADC_DAPLSTA		0x2504
++#define AC200_ADC_DAPRSTA		0x2506
++#define AC200_ADC_DAPLTL		0x2508
++#define AC200_ADC_DAPRTL		0x250A
++#define AC200_ADC_DAPLHAC		0x250C
++#define AC200_ADC_DAPLLAC		0x250E
++#define AC200_ADC_DAPRHAC		0x2510
++#define AC200_ADC_DAPRLAC		0x2512
++#define AC200_ADC_DAPLDT		0x2514
++#define AC200_ADC_DAPLAT		0x2516
++#define AC200_ADC_DAPRDT		0x2518
++#define AC200_ADC_DAPRAT		0x251A
++#define AC200_ADC_DAPNTH		0x251C
++#define AC200_ADC_DAPLHNAC		0x251E
++#define AC200_ADC_DAPLLNAC		0x2520
++#define AC200_ADC_DAPRHNAC		0x2522
++#define AC200_ADC_DAPRLNAC		0x2524
++#define AC200_AC_DAPHHPFC		0x2526
++#define AC200_AC_DAPLHPFC		0x2528
++#define AC200_AC_DAPOPT			0x252A
++#define AC200_AC_DAC_DAPCTRL		0x3000
++#define AC200_AC_DRC_HHPFC		0x3002
++#define AC200_AC_DRC_LHPFC		0x3004
++#define AC200_AC_DRC_CTRL		0x3006
++#define AC200_AC_DRC_LPFHAT		0x3008
++#define AC200_AC_DRC_LPFLAT		0x300A
++#define AC200_AC_DRC_RPFHAT		0x300C
++#define AC200_AC_DRC_RPFLAT		0x300E
++#define AC200_AC_DRC_LPFHRT		0x3010
++#define AC200_AC_DRC_LPFLRT		0x3012
++#define AC200_AC_DRC_RPFHRT		0x3014
++#define AC200_AC_DRC_RPFLRT		0x3016
++#define AC200_AC_DRC_LRMSHAT		0x3018
++#define AC200_AC_DRC_LRMSLAT		0x301A
++#define AC200_AC_DRC_RRMSHAT		0x301C
++#define AC200_AC_DRC_RRMSLAT		0x301E
++#define AC200_AC_DRC_HCT		0x3020
++#define AC200_AC_DRC_LCT		0x3022
++#define AC200_AC_DRC_HKC		0x3024
++#define AC200_AC_DRC_LKC		0x3026
++#define AC200_AC_DRC_HOPC		0x3028
++#define AC200_AC_DRC_LOPC		0x302A
++#define AC200_AC_DRC_HLT		0x302C
++#define AC200_AC_DRC_LLT		0x302E
++#define AC200_AC_DRC_HKI		0x3030
++#define AC200_AC_DRC_LKI		0x3032
++#define AC200_AC_DRC_HOPL		0x3034
++#define AC200_AC_DRC_LOPL		0x3036
++#define AC200_AC_DRC_HET		0x3038
++#define AC200_AC_DRC_LET		0x303A
++#define AC200_AC_DRC_HKE		0x303C
++#define AC200_AC_DRC_LKE		0x303E
++#define AC200_AC_DRC_HOPE		0x3040
++#define AC200_AC_DRC_LOPE		0x3042
++#define AC200_AC_DRC_HKN		0x3044
++#define AC200_AC_DRC_LKN		0x3046
++#define AC200_AC_DRC_SFHAT		0x3048
++#define AC200_AC_DRC_SFLAT		0x304A
++#define AC200_AC_DRC_SFHRT		0x304C
++#define AC200_AC_DRC_SFLRT		0x304E
++#define AC200_AC_DRC_MXGHS		0x3050
++#define AC200_AC_DRC_MXGLS		0x3052
++#define AC200_AC_DRC_MNGHS		0x3054
++#define AC200_AC_DRC_MNGLS		0x3056
++#define AC200_AC_DRC_EPSHC		0x3058
++#define AC200_AC_DRC_EPSLC		0x305A
++#define AC200_AC_DRC_HPFHGAIN		0x305E
++#define AC200_AC_DRC_HPFLGAIN		0x3060
++#define AC200_AC_DRC_BISTCR		0x3100
++#define AC200_AC_DRC_BISTST		0x3102
++
++/* TVE registers */
++#define AC200_TVE_CTL0			0x4000
++#define AC200_TVE_CTL1			0x4002
++#define AC200_TVE_MOD0			0x4004
++#define AC200_TVE_MOD1			0x4006
++#define AC200_TVE_DAC_CFG0		0x4008
++#define AC200_TVE_DAC_CFG1		0x400A
++#define AC200_TVE_YC_DELAY		0x400C
++#define AC200_TVE_YC_FILTER		0x400E
++#define AC200_TVE_BURST_FRQ0		0x4010
++#define AC200_TVE_BURST_FRQ1		0x4012
++#define AC200_TVE_FRONT_PORCH		0x4014
++#define AC200_TVE_BACK_PORCH		0x4016
++#define AC200_TVE_TOTAL_LINE		0x401C
++#define AC200_TVE_FIRST_ACTIVE		0x401E
++#define AC200_TVE_BLACK_LEVEL		0x4020
++#define AC200_TVE_BLANK_LEVEL		0x4022
++#define AC200_TVE_PLUG_EN		0x4030
++#define AC200_TVE_PLUG_IRQ_EN		0x4032
++#define AC200_TVE_PLUG_IRQ_STA		0x4034
++#define AC200_TVE_PLUG_STA		0x4038
++#define AC200_TVE_PLUG_DEBOUNCE		0x4040
++#define AC200_TVE_DAC_TEST		0x4042
++#define AC200_TVE_PLUG_PULSE_LEVEL	0x40F4
++#define AC200_TVE_PLUG_PULSE_START	0x40F8
++#define AC200_TVE_PLUG_PULSE_PERIOD	0x40FA
++#define AC200_TVE_IF_CTL		0x5000
++#define AC200_TVE_IF_TIM0		0x5008
++#define AC200_TVE_IF_TIM1		0x500A
++#define AC200_TVE_IF_TIM2		0x500C
++#define AC200_TVE_IF_TIM3		0x500E
++#define AC200_TVE_IF_SYNC0		0x5010
++#define AC200_TVE_IF_SYNC1		0x5012
++#define AC200_TVE_IF_SYNC2		0x5014
++#define AC200_TVE_IF_TIM4		0x5016
++#define AC200_TVE_IF_STATUS		0x5018
++
++/* EPHY registers */
++#define AC200_EPHY_CTL			0x6000
++#define AC200_EPHY_BIST			0x6002
++
++/* eFuse registers (0x8000 - 0x9FFF, layout unknown) */
++
++/* RTC registers */
++#define AC200_LOSC_CTRL0		0xA000
++#define AC200_LOSC_CTRL1		0xA002
++#define AC200_LOSC_AUTO_SWT_STA		0xA004
++#define AC200_INTOSC_CLK_PRESCAL	0xA008
++#define AC200_RTC_YY_MM_DD0		0xA010
++#define AC200_RTC_YY_MM_DD1		0xA012
++#define AC200_RTC_HH_MM_SS0		0xA014
++#define AC200_RTC_HH_MM_SS1		0xA016
++#define AC200_ALARM0_CUR_VLU0		0xA024
++#define AC200_ALARM0_CUR_VLU1		0xA026
++#define AC200_ALARM0_ENABLE		0xA028
++#define AC200_ALARM0_IRQ_EN		0xA02C
++#define AC200_ALARM0_IRQ_STA		0xA030
++#define AC200_ALARM1_WK_HH_MM_SS0	0xA040
++#define AC200_ALARM1_WK_HH_MM_SS1	0xA042
++#define AC200_ALARM1_ENABLE		0xA044
++#define AC200_ALARM1_IRQ_EN		0xA048
++#define AC200_ALARM1_IRQ_STA		0xA04C
++#define AC200_ALARM_CONFIG		0xA050
++#define AC200_LOSC_OUT_GATING		0xA060
++#define AC200_GP_DATA(x)		(0xA100 + (x) * 2)
++#define AC200_RTC_DEB			0xA170
++#define AC200_GPL_HOLD_OUTPUT		0xA180
++#define AC200_VDD_RTC			0xA190
++#define AC200_IC_CHARA0			0xA1F0
++#define AC200_IC_CHARA1			0xA1F2
++
++struct ac200_dev {
++	struct clk			*clk;
++	struct regmap			*regmap;
++	struct regmap_irq_chip_data	*regmap_irqc;
++};
++
++extern int ac200_enable(void);
++extern uint16_t sun50i_ephy_calibrate_value(void);
++
++#endif /* __LINUX_MFD_AC200_H */
+diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
+index d0f66a5e1b2a..71349cac1a67 100644
+--- a/include/linux/of_gpio.h
++++ b/include/linux/of_gpio.h
+@@ -15,6 +15,21 @@
+ #include <linux/gpio.h>		/* FIXME: Shouldn't be here */
+ #include <linux/of.h>
+ 
++/*
++ * This is Linux-specific flags. By default controllers' and Linux' mapping
++ * match, but GPIO controllers are free to translate their own flags to
++ * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
++ */
++enum of_gpio_flags {
++	OF_GPIO_ACTIVE_LOW = 0x1,
++	OF_GPIO_SINGLE_ENDED = 0x2,
++	OF_GPIO_OPEN_DRAIN = 0x4,
++	OF_GPIO_TRANSITORY = 0x8,
++	OF_GPIO_PULL_UP = 0x10,
++	OF_GPIO_PULL_DOWN = 0x20,
++	OF_GPIO_PULL_DISABLE = 0x40,
++};
++
+ struct device_node;
+ 
+ #ifdef CONFIG_OF_GPIO
+@@ -22,6 +37,9 @@ struct device_node;
+ extern int of_get_named_gpio(const struct device_node *np,
+ 			     const char *list_name, int index);
+ 
++extern int of_get_named_gpio_flags(const struct device_node *np,
++		const char *list_name, int index, enum of_gpio_flags *flags);
++
+ #else /* CONFIG_OF_GPIO */
+ 
+ #include <linux/errno.h>
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
new file mode 100644
index 000000000000..f892f9a16be8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
@@ -0,0 +1,1317 @@
+From d33be8d15727f4b9f9741744c11df3b22a6e9273 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Wed, 1 May 2024 14:24:51 +0800
+Subject: drivers: pwm: Add pwm-sunxi-enhance driver for h616
+
+linux-orangepi commit:
+c68ef342eba3673c7f1f5aa1ab819b06da1f60c6
+---
+ drivers/pwm/Kconfig             |    9 +
+ drivers/pwm/Makefile            |    1 +
+ drivers/pwm/pwm-sunxi-enhance.c | 1194 +++++++++++++++++++++++++++++++
+ drivers/pwm/pwm-sunxi-enhance.h |   60 ++
+ 4 files changed, 1264 insertions(+)
+ create mode 100644 drivers/pwm/pwm-sunxi-enhance.c
+ create mode 100644 drivers/pwm/pwm-sunxi-enhance.h
+
+diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
+index 8ebcddf91f7b..44adc2b7df0e 100644
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -615,6 +615,15 @@ config PWM_SUN4I
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called pwm-sun4i.
+ 
++config PWM_SUNXI_ENHANCE
++	tristate "Sunxi Enhance PWM support"
++	depends on PWM && ARCH_SUNXI
++	help
++	Enhance PWM framework driver for sunxi.
++
++	To compile this driver as a module, choose M here: the module
++	will be called pwm-sunxi.
++
+ config PWM_SUNPLUS
+ 	tristate "Sunplus PWM support"
+ 	depends on ARCH_SUNPLUS || COMPILE_TEST
+diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
+index c822389c2a24..9339710d4177 100644
+--- a/drivers/pwm/Makefile
++++ b/drivers/pwm/Makefile
+@@ -57,6 +57,7 @@ obj-$(CONFIG_PWM_STM32)		+= pwm-stm32.o
+ obj-$(CONFIG_PWM_STM32_LP)	+= pwm-stm32-lp.o
+ obj-$(CONFIG_PWM_STMPE)		+= pwm-stmpe.o
+ obj-$(CONFIG_PWM_SUN4I)		+= pwm-sun4i.o
++obj-$(CONFIG_PWM_SUNXI_ENHANCE)		+= pwm-sunxi-enhance.o
+ obj-$(CONFIG_PWM_SUNPLUS)	+= pwm-sunplus.o
+ obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
+ obj-$(CONFIG_PWM_TIECAP)	+= pwm-tiecap.o
+diff --git a/drivers/pwm/pwm-sunxi-enhance.c b/drivers/pwm/pwm-sunxi-enhance.c
+new file mode 100644
+index 000000000000..68e22077ce34
+--- /dev/null
++++ b/drivers/pwm/pwm-sunxi-enhance.c
+@@ -0,0 +1,1194 @@
++/*
++ * Allwinnertech pulse-width-modulation controller driver
++ *
++ * Copyright (C) 2015 AllWinner
++ *
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#include <linux/types.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/cdev.h>
++#include <linux/pwm.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <linux/fs.h>
++#include <linux/device.h>
++#include <linux/gpio.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++#include <linux/of_iommu.h>
++#include <linux/of_device.h>
++#include <linux/of_platform.h>
++#include <linux/printk.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include "pwm-sunxi-enhance.h"
++
++#define PWM_NUM_MAX 4
++#define PWM_BIND_NUM 2
++#define PWM_PIN_STATE_ACTIVE "default"
++//#define PWM_PIN_STATE_SLEEP "sleep"
++
++#define SETMASK(width, shift) ((width ? ((-1U) >> (32 - width)) : 0) << (shift))
++#define CLRMASK(width, shift) (~(SETMASK(width, shift)))
++#define GET_BITS(shift, width, reg) \
++    (((reg)&SETMASK(width, shift)) >> (shift))
++#define SET_BITS(shift, width, reg, val) \
++    (((reg)&CLRMASK(width, shift)) | (val << (shift)))
++
++static int pwm_debug = 0;
++module_param(pwm_debug, int, 0644);
++MODULE_PARM_DESC(pwm_debug, "enable pwm debug");
++
++#define pwm_debug(fmt, ...) \
++    if (pwm_debug)          \
++    printk(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__)
++
++struct sunxi_pwm_config
++{
++    unsigned int dead_time;
++    unsigned int bind_pwm;
++
++    unsigned int clk_bypass_output;
++};
++
++struct sunxi_pwm_chip
++{
++    struct pwm_chip chip;
++    void __iomem *base;
++    struct sunxi_pwm_config *config;
++    struct clk *bus_clk;
++    struct clk *clk;
++    struct reset_control *pwm_rst_clk;
++};
++
++static inline struct sunxi_pwm_chip *to_sunxi_pwm_chip(struct pwm_chip *chip)
++{
++    return container_of(chip, struct sunxi_pwm_chip, chip);
++}
++
++static inline u32 sunxi_pwm_readl(struct pwm_chip *chip, u32 offset)
++{
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++    u32 value = 0;
++
++    value = readl(pc->base + offset);
++
++    return value;
++}
++
++static inline u32 sunxi_pwm_writel(struct pwm_chip *chip, u32 offset, u32 value)
++{
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    writel(value, pc->base + offset);
++
++    return 0;
++}
++
++static int sunxi_pwm_pin_set_state(struct device *dev, char *name)
++{
++    struct pinctrl *pctl;
++    struct pinctrl_state *state;
++    int ret = -1;
++
++    pctl = devm_pinctrl_get(dev);
++    if (IS_ERR(pctl))
++    {
++        dev_err(dev, "pinctrl_get failed!\n");
++        ret = PTR_ERR(pctl);
++        goto exit;
++    }
++
++    state = pinctrl_lookup_state(pctl, name);
++    if (IS_ERR(state))
++    {
++        dev_err(dev, "pinctrl_lookup_state(%s) failed!\n", name);
++        ret = PTR_ERR(state);
++        goto exit;
++    }
++
++    ret = pinctrl_select_state(pctl, state);
++    if (ret < 0)
++    {
++        dev_err(dev, "pinctrl_select_state(%s) failed!\n", name);
++        goto exit;
++    }
++    ret = 0;
++
++exit:
++    return ret;
++}
++
++static int sunxi_pwm_get_config(struct platform_device *pdev, struct sunxi_pwm_config *config)
++{
++    struct device_node *np = pdev->dev.of_node;
++    int ret = 0;
++
++    /* read register config */
++    ret = of_property_read_u32(np, "bind_pwm", &config->bind_pwm);
++    if (ret < 0)
++    {
++        /*if there is no bind pwm,set 255, dual pwm invalid!*/
++        config->bind_pwm = 255;
++        ret = 0;
++    }
++
++    ret = of_property_read_u32(np, "dead_time", &config->dead_time);
++    if (ret < 0)
++    {
++        /*if there is  bind pwm, but not set dead time,set bind pwm 255,dual pwm invalid!*/
++        config->bind_pwm = 255;
++        ret = 0;
++    }
++
++    ret = of_property_read_u32(np, "clk_bypass_output", &config->clk_bypass_output);
++    if (ret < 0)
++    {
++        /*if use pwm as the internal clock source!*/
++        config->clk_bypass_output = 0;
++        ret = 0;
++    }
++
++    of_node_put(np);
++
++    return ret;
++}
++
++static int sunxi_pwm_set_polarity_single(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity)
++{
++    u32 temp;
++    unsigned int reg_offset, reg_shift, reg_width;
++    u32 sel = 0;
++
++    sel = pwm->pwm - chip->base;
++    reg_offset = PWM_PCR_BASE + sel * 0x20;
++    reg_shift = PWM_ACT_STA_SHIFT;
++    reg_width = PWM_ACT_STA_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    if (polarity == PWM_POLARITY_NORMAL)
++        temp = SET_BITS(reg_shift, 1, temp, 1);
++    else
++        temp = SET_BITS(reg_shift, 1, temp, 0);
++
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    return 0;
++}
++
++static int sunxi_pwm_set_polarity_dual(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity, int bind_num)
++{
++    u32 temp[2];
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    u32 sel[2] = {0};
++
++    sel[0] = pwm->pwm - chip->base;
++    sel[1] = bind_num - chip->base;
++    /* config current pwm*/
++    reg_offset[0] = PWM_PCR_BASE + sel[0] * 0x20;
++    reg_shift[0] = PWM_ACT_STA_SHIFT;
++    reg_width[0] = PWM_ACT_STA_WIDTH;
++    temp[0] = sunxi_pwm_readl(chip, reg_offset[0]);
++    if (polarity == PWM_POLARITY_NORMAL)
++        temp[0] = SET_BITS(reg_shift[0], 1, temp[0], 1);
++    else
++        temp[0] = SET_BITS(reg_shift[0], 1, temp[0], 0);
++
++    /* config bind pwm*/
++    reg_offset[1] = PWM_PCR_BASE + sel[1] * 0x20;
++    reg_shift[1] = PWM_ACT_STA_SHIFT;
++    reg_width[1] = PWM_ACT_STA_WIDTH;
++    temp[1] = sunxi_pwm_readl(chip, reg_offset[1]);
++
++    /*bind pwm's polarity is reverse compare with the  current pwm*/
++    if (polarity == PWM_POLARITY_NORMAL)
++        temp[1] = SET_BITS(reg_shift[0], 1, temp[1], 0);
++    else
++        temp[1] = SET_BITS(reg_shift[0], 1, temp[1], 1);
++
++    /*config register at the same time*/
++    sunxi_pwm_writel(chip, reg_offset[0], temp[0]);
++    sunxi_pwm_writel(chip, reg_offset[1], temp[1]);
++
++    return 0;
++}
++
++static int sunxi_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity)
++{
++    int bind_num;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
++    if (bind_num == 255)
++        sunxi_pwm_set_polarity_single(chip, pwm, polarity);
++    else
++        sunxi_pwm_set_polarity_dual(chip, pwm, polarity, bind_num);
++
++    return 0;
++}
++
++static u32 get_pccr_reg_offset(u32 sel, u32 *reg_offset)
++{
++    switch (sel)
++    {
++    case 0:
++    case 1:
++        *reg_offset = PWM_PCCR01;
++        break;
++    case 2:
++    case 3:
++        *reg_offset = PWM_PCCR23;
++        break;
++    case 4:
++    case 5:
++        *reg_offset = PWM_PCCR45;
++        break;
++    case 6:
++    case 7:
++        *reg_offset = PWM_PCCR67;
++        break;
++    case 8:
++        *reg_offset = PWM_PCCR8;
++        break;
++    default:
++        pr_err("%s:Not supported!\n", __func__);
++        break;
++    }
++    return 0;
++}
++
++static u32 get_pdzcr_reg_offset(u32 sel, u32 *reg_offset)
++{
++    switch (sel)
++    {
++    case 0:
++    case 1:
++        *reg_offset = PWM_PDZCR01;
++        break;
++    case 2:
++    case 3:
++        *reg_offset = PWM_PDZCR23;
++        break;
++    case 4:
++    case 5:
++        *reg_offset = PWM_PDZCR45;
++        break;
++    case 6:
++    case 7:
++        *reg_offset = PWM_PDZCR67;
++        break;
++    default:
++        pr_err("%s:Not supported!\n", __func__);
++        break;
++    }
++    return 0;
++}
++
++#define PRESCALE_MAX 256
++
++static int sunxi_pwm_config_single(struct pwm_chip *chip, struct pwm_device *pwm,
++                                   int duty_ns, int period_ns)
++{
++    unsigned int temp;
++    unsigned long long c = 0;
++    unsigned long entire_cycles = 256, active_cycles = 192;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++    unsigned int reg_offset, reg_shift, reg_width;
++    unsigned int reg_bypass_shift;
++    unsigned int reg_clk_src_shift, reg_clk_src_width;
++    unsigned int reg_div_m_shift, reg_div_m_width;
++    unsigned int pre_scal_id = 0, div_m = 0, prescale = 0;
++    u32 sel = 0;
++    u32 pre_scal[][2] = {
++
++        /* reg_value  clk_pre_div */
++        {0, 1},
++        {1, 2},
++        {2, 4},
++        {3, 8},
++        {4, 16},
++        {5, 32},
++        {6, 64},
++        {7, 128},
++        {8, 256},
++    };
++
++    sel = pwm->pwm - chip->base;
++
++    get_pccr_reg_offset(sel, &reg_offset);
++    if ((sel % 2) == 0)
++        reg_bypass_shift = 0x5;
++    else
++        reg_bypass_shift = 0x6;
++    /*src clk reg*/
++    reg_clk_src_shift = PWM_CLK_SRC_SHIFT;
++    reg_clk_src_width = PWM_CLK_SRC_WIDTH;
++
++    if (period_ns > 0 && period_ns <= 10)
++    {
++        /* if freq lt 100M, then direct output 100M clock,set by pass. */
++        c = 100000000;
++        /*bypass reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++
++        /*clk_src_reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 1);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++
++        return 0;
++    }
++    else if (period_ns > 10 && period_ns <= 334)
++    {
++        /* if freq between 3M~100M, then select 100M as clock */
++        c = 100000000;
++        /*set clk bypass_output reg to 1 when pwm is used as the internal clock source.*/
++        if (pc->config[pwm->pwm - chip->base].clk_bypass_output == 1) {
++            temp = sunxi_pwm_readl(chip, reg_offset);
++            temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
++            sunxi_pwm_writel(chip, reg_offset, temp);
++        }
++        /*clk_src_reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 1);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++    }
++    else if (period_ns > 334)
++    {
++        /* if freq < 3M, then select 24M clock */
++        c = 24000000;
++        /*set clk bypass_output reg to 1 when pwm is used as the internal clock source.*/
++        if (pc->config[pwm->pwm - chip->base].clk_bypass_output == 1) {
++            temp = sunxi_pwm_readl(chip, reg_offset);
++            temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
++            sunxi_pwm_writel(chip, reg_offset, temp);
++        }
++        /*clk_src_reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 0);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++    }
++    pwm_debug("duty_ns=%d period_ns=%d c =%llu.\n", duty_ns, period_ns, c);
++
++    c = c * period_ns;
++    do_div(c, 1000000000);
++    entire_cycles = (unsigned long)c;
++
++    for (pre_scal_id = 0; pre_scal_id < 9; pre_scal_id++)
++    {
++        if (entire_cycles <= 65536)
++            break;
++        for (prescale = 0; prescale < PRESCALE_MAX + 1; prescale++)
++        {
++            entire_cycles = ((unsigned long)c / pre_scal[pre_scal_id][1]) / (prescale + 1);
++            if (entire_cycles <= 65536)
++            {
++                div_m = pre_scal[pre_scal_id][0];
++                break;
++            }
++        }
++    }
++
++    c = (unsigned long long)entire_cycles * duty_ns;
++    do_div(c, period_ns);
++    active_cycles = c;
++    if (entire_cycles == 0)
++        entire_cycles++;
++
++    /* config  clk div_m*/
++    reg_div_m_shift = PWM_DIV_M_SHIFT;
++    reg_div_m_width = PWM_DIV_M_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_div_m_shift, reg_div_m_width, temp, div_m);
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    /* config prescal */
++    reg_offset = PWM_PCR_BASE + 0x20 * sel;
++    reg_shift = PWM_PRESCAL_SHIFT;
++    reg_width = PWM_PRESCAL_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_shift, reg_width, temp, prescale);
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    /* config active cycles */
++    reg_offset = PWM_PPR_BASE + 0x20 * sel;
++    reg_shift = PWM_ACT_CYCLES_SHIFT;
++    reg_width = PWM_ACT_CYCLES_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_shift, reg_width, temp, active_cycles);
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    /* config period cycles */
++    reg_offset = PWM_PPR_BASE + 0x20 * sel;
++    reg_shift = PWM_PERIOD_CYCLES_SHIFT;
++    reg_width = PWM_PERIOD_CYCLES_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_shift, reg_width, temp, (entire_cycles - 1));
++
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    pwm_debug("active_cycles=%lu entire_cycles=%lu prescale=%u div_m=%u\n",
++              active_cycles, entire_cycles, prescale, div_m);
++    return 0;
++}
++
++static int sunxi_pwm_config_dual(struct pwm_chip *chip, struct pwm_device *pwm,
++                                 int duty_ns, int period_ns, int bind_num)
++{
++    u32 value[2] = {0};
++    unsigned int temp;
++    unsigned long long c = 0, clk = 0, clk_temp = 0;
++    unsigned long entire_cycles = 256, active_cycles = 192;
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    unsigned int reg_bypass_shift;
++    unsigned int reg_dz_en_offset[2], reg_dz_en_shift[2], reg_dz_en_width[2];
++    unsigned int pre_scal_id = 0, div_m = 0, prescale = 0;
++    int src_clk_sel = 0;
++    int i = 0;
++    unsigned int dead_time = 0, duty = 0;
++    u32 pre_scal[][2] = {
++
++        /* reg_value  clk_pre_div */
++        {0, 1},
++        {1, 2},
++        {2, 4},
++        {3, 8},
++        {4, 16},
++        {5, 32},
++        {6, 64},
++        {7, 128},
++        {8, 256},
++    };
++    unsigned int pwm_index[2] = {0};
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    pwm_index[0] = pwm->pwm - chip->base;
++    pwm_index[1] = bind_num - chip->base;
++
++    /* if duty time < dead time,it is wrong. */
++    dead_time = pc->config[pwm_index[0]].dead_time;
++    duty = (unsigned int)duty_ns;
++    /* judge if the pwm eanble dead zone */
++    get_pdzcr_reg_offset(pwm_index[0], &reg_dz_en_offset[0]);
++    reg_dz_en_shift[0] = PWM_DZ_EN_SHIFT;
++    reg_dz_en_width[0] = PWM_DZ_EN_WIDTH;
++
++    value[0] = sunxi_pwm_readl(chip, reg_dz_en_offset[0]);
++    value[0] = SET_BITS(reg_dz_en_shift[0], reg_dz_en_width[0], value[0], 1);
++    sunxi_pwm_writel(chip, reg_dz_en_offset[0], value[0]);
++    temp = sunxi_pwm_readl(chip, reg_dz_en_offset[0]);
++    temp &= (1u << reg_dz_en_shift[0]);
++    if (duty < dead_time || temp == 0)
++    {
++        pr_err("[PWM]duty time or dead zone error.\n");
++        return -EINVAL;
++    }
++
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        if ((i % 2) == 0)
++            reg_bypass_shift = 0x5;
++        else
++            reg_bypass_shift = 0x6;
++        get_pccr_reg_offset(pwm_index[i], &reg_offset[i]);
++        reg_shift[i] = reg_bypass_shift;
++        reg_width[i] = PWM_BYPASS_WIDTH;
++    }
++
++    if (period_ns > 0 && period_ns <= 10)
++    {
++        /* if freq lt 100M, then direct output 100M clock,set by pass */
++        clk = 100000000;
++        src_clk_sel = 1;
++
++        /* config the two pwm bypass */
++        for (i = 0; i < PWM_BIND_NUM; i++)
++        {
++            temp = sunxi_pwm_readl(chip, reg_offset[i]);
++            temp = SET_BITS(reg_shift[i], reg_width[i], temp, 1);
++            sunxi_pwm_writel(chip, reg_offset[i], temp);
++
++            reg_shift[i] = PWM_CLK_SRC_SHIFT;
++            reg_width[i] = PWM_CLK_SRC_WIDTH;
++            temp = sunxi_pwm_readl(chip, reg_offset[i]);
++            temp = SET_BITS(reg_shift[i], reg_width[i], temp, 1);
++            sunxi_pwm_writel(chip, reg_offset[i], temp);
++        }
++
++        return 0;
++    }
++    else if (period_ns > 10 && period_ns <= 334)
++    {
++        clk = 100000000;
++        src_clk_sel = 1;
++    }
++    else if (period_ns > 334)
++    {
++        /* if freq < 3M, then select 24M clock */
++        clk = 24000000;
++        src_clk_sel = 0;
++    }
++
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_shift[i] = PWM_CLK_SRC_SHIFT;
++        reg_width[i] = PWM_CLK_SRC_WIDTH;
++
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, src_clk_sel);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    c = clk;
++    c *= period_ns;
++    do_div(c, 1000000000);
++    entire_cycles = (unsigned long)c;
++
++    /* get div_m and prescale,which satisfy: deat_val <= 256, entire <= 65536 */
++    for (pre_scal_id = 0; pre_scal_id < 9; pre_scal_id++)
++    {
++        for (prescale = 0; prescale < PRESCALE_MAX + 1; prescale++)
++        {
++            entire_cycles = ((unsigned long)c / pre_scal[pre_scal_id][1]) / (prescale + 1);
++            clk_temp = clk;
++            do_div(clk_temp, pre_scal[pre_scal_id][1] * (prescale + 1));
++            clk_temp *= dead_time;
++            do_div(clk_temp, 1000000000);
++            if (entire_cycles <= 65536 && clk_temp <= 256)
++            {
++                div_m = pre_scal[pre_scal_id][0];
++                break;
++            }
++        }
++        if (entire_cycles <= 65536 && clk_temp <= 256)
++            break;
++        else
++        {
++            pr_err("%s:config dual err.entire_cycles=%lu, dead_zone_val=%llu",
++                   __func__, entire_cycles, clk_temp);
++            return -EINVAL;
++        }
++    }
++
++    c = (unsigned long long)entire_cycles * duty_ns;
++    do_div(c, period_ns);
++    active_cycles = c;
++    if (entire_cycles == 0)
++        entire_cycles++;
++
++    /* config  clk div_m*/
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_shift[i] = PWM_DIV_M_SHIFT;
++        reg_width[i] = PWM_DIV_M_SHIFT;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, div_m);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    /* config prescal */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PCR_BASE + 0x20 * pwm_index[i];
++        reg_shift[i] = PWM_PRESCAL_SHIFT;
++        reg_width[i] = PWM_PRESCAL_WIDTH;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, prescale);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    /* config active cycles */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PPR_BASE + 0x20 * pwm_index[i];
++        reg_shift[i] = PWM_ACT_CYCLES_SHIFT;
++        reg_width[i] = PWM_ACT_CYCLES_WIDTH;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, active_cycles);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    /* config period cycles */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PPR_BASE + 0x20 * pwm_index[i];
++        reg_shift[i] = PWM_PERIOD_CYCLES_SHIFT;
++        reg_width[i] = PWM_PERIOD_CYCLES_WIDTH;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, (entire_cycles - 1));
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    pwm_debug("active_cycles=%lu entire_cycles=%lu prescale=%u div_m=%u\n",
++              active_cycles, entire_cycles, prescale, div_m);
++
++    /* config dead zone, one config for two pwm */
++    reg_offset[0] = reg_dz_en_offset[0];
++    reg_shift[0] = PWM_PDZINTV_SHIFT;
++    reg_width[0] = PWM_PDZINTV_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset[0]);
++    temp = SET_BITS(reg_shift[0], reg_width[0], temp, (unsigned int)clk_temp);
++    sunxi_pwm_writel(chip, reg_offset[0], temp);
++
++    return 0;
++}
++
++static int sunxi_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
++                            int duty_ns, int period_ns)
++{
++    int bind_num;
++
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
++    if (bind_num == 255) {
++        sunxi_pwm_config_single(chip, pwm, duty_ns, period_ns);
++    }
++    else {
++        sunxi_pwm_config_dual(chip, pwm, duty_ns, period_ns, bind_num);
++    }
++
++    return 0;
++}
++
++static int sunxi_pwm_enable_single(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    unsigned int value = 0, index = 0;
++    unsigned int reg_offset, reg_shift;
++    struct device_node *sub_np;
++    struct platform_device *pwm_pdevice;
++    int ret;
++
++    index = pwm->pwm - chip->base;
++    sub_np = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", index);
++    if (IS_ERR_OR_NULL(sub_np))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return -ENODEV;
++    }
++    pwm_pdevice = of_find_device_by_node(sub_np);
++    if (IS_ERR_OR_NULL(pwm_pdevice))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return -ENODEV;
++    }
++    ret = sunxi_pwm_pin_set_state(&pwm_pdevice->dev, PWM_PIN_STATE_ACTIVE);
++    if (ret != 0)
++        return ret;
++
++    /* enable clk for pwm controller */
++    get_pccr_reg_offset(index, &reg_offset);
++    reg_shift = PWM_CLK_GATING_SHIFT;
++    value = sunxi_pwm_readl(chip, reg_offset);
++    value = SET_BITS(reg_shift, 1, value, 1);
++    sunxi_pwm_writel(chip, reg_offset, value);
++
++    /* enable pwm controller */
++    reg_offset = PWM_PER;
++    reg_shift = index;
++    value = sunxi_pwm_readl(chip, reg_offset);
++    value = SET_BITS(reg_shift, 1, value, 1);
++    sunxi_pwm_writel(chip, reg_offset, value);
++
++    return 0;
++}
++
++static int sunxi_pwm_enable_dual(struct pwm_chip *chip, struct pwm_device *pwm, int bind_num)
++{
++    u32 value[2] = {0};
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    struct device_node *sub_np[2];
++    struct platform_device *pwm_pdevice[2];
++    int i = 0, ret = 0;
++    unsigned int pwm_index[2] = {0};
++
++    pwm_index[0] = pwm->pwm - chip->base;
++    pwm_index[1] = bind_num - chip->base;
++
++    /*set current pwm pin state*/
++    sub_np[0] = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", pwm_index[0]);
++    if (IS_ERR_OR_NULL(sub_np[0]))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return -ENODEV;
++    }
++    pwm_pdevice[0] = of_find_device_by_node(sub_np[0]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[0]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return -ENODEV;
++    }
++
++    /*set bind pwm pin state*/
++    sub_np[1] = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", pwm_index[1]);
++    if (IS_ERR_OR_NULL(sub_np[1]))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return -ENODEV;
++    }
++    pwm_pdevice[1] = of_find_device_by_node(sub_np[1]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[1]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return -ENODEV;
++    }
++
++    ret = sunxi_pwm_pin_set_state(&pwm_pdevice[0]->dev, PWM_PIN_STATE_ACTIVE);
++    if (ret != 0)
++        return ret;
++    ret = sunxi_pwm_pin_set_state(&pwm_pdevice[1]->dev, PWM_PIN_STATE_ACTIVE);
++    if (ret != 0)
++        return ret;
++
++    /* enable clk for pwm controller */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        get_pccr_reg_offset(pwm_index[i], &reg_offset[i]);
++        reg_shift[i] = PWM_CLK_GATING_SHIFT;
++        reg_width[i] = PWM_CLK_GATING_WIDTH;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 1);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    /* enable pwm controller */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PER;
++        reg_shift[i] = pwm_index[i];
++        reg_width[i] = 0x1;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 1);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    return 0;
++}
++
++static int sunxi_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    int bind_num;
++    int ret = 0;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
++    if (bind_num == 255)
++        ret = sunxi_pwm_enable_single(chip, pwm);
++    else
++        ret = sunxi_pwm_enable_dual(chip, pwm, bind_num);
++
++    sunxi_pwm_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
++
++    return ret;
++}
++
++static void sunxi_pwm_disable_single(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    u32 value = 0, index = 0;
++    unsigned int reg_offset, reg_shift, reg_width;
++    struct device_node *sub_np;
++    struct platform_device *pwm_pdevice;
++
++    index = pwm->pwm - chip->base;
++    sub_np = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", index);
++    if (IS_ERR_OR_NULL(sub_np))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return;
++    }
++    pwm_pdevice = of_find_device_by_node(sub_np);
++    if (IS_ERR_OR_NULL(pwm_pdevice))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return;
++    }
++
++    /* disable pwm controller */
++    reg_offset = PWM_PER;
++    reg_shift = index;
++    reg_width = 0x1;
++    value = sunxi_pwm_readl(chip, reg_offset);
++    value = SET_BITS(reg_shift, reg_width, value, 0);
++    sunxi_pwm_writel(chip, reg_offset, value);
++
++    /*
++     * 0 , 1 --> 0
++     * 2 , 3 --> 2
++     * 4 , 5 --> 4
++     * 6 , 7 --> 6
++     */
++    reg_shift &= ~(1);
++
++    if (GET_BITS(reg_shift, 2, value) == 0)
++    {
++        /* disable clk for pwm controller. */
++        get_pccr_reg_offset(index, &reg_offset);
++        reg_shift = PWM_CLK_GATING_SHIFT;
++        reg_width = 0x1;
++        value = sunxi_pwm_readl(chip, reg_offset);
++        value = SET_BITS(reg_shift, reg_width, value, 0);
++        sunxi_pwm_writel(chip, reg_offset, value);
++    }
++
++    // sunxi_pwm_pin_set_state(&pwm_pdevice->dev, PWM_PIN_STATE_SLEEP);
++}
++
++static void sunxi_pwm_disable_dual(struct pwm_chip *chip, struct pwm_device *pwm, int bind_num)
++{
++    u32 value[2] = {0};
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    struct device_node *sub_np[2];
++    struct platform_device *pwm_pdevice[2];
++    int i = 0;
++    unsigned int pwm_index[2] = {0};
++
++    pwm_index[0] = pwm->pwm - chip->base;
++    pwm_index[1] = bind_num - chip->base;
++
++    /* get current index pwm device */
++    sub_np[0] = of_parse_phandle(chip->dev->of_node, "pwms", pwm_index[0]);
++    if (IS_ERR_OR_NULL(sub_np[0]))
++    {
++        pr_err("%s: can't parse \"pwms\" property\n", __func__);
++        return;
++    }
++    pwm_pdevice[0] = of_find_device_by_node(sub_np[0]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[0]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return;
++    }
++    /* get bind pwm device */
++    sub_np[1] = of_parse_phandle(chip->dev->of_node, "pwms", pwm_index[1]);
++    if (IS_ERR_OR_NULL(sub_np[1]))
++    {
++        pr_err("%s: can't parse \"pwms\" property\n", __func__);
++        return;
++    }
++    pwm_pdevice[1] = of_find_device_by_node(sub_np[1]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[1]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return;
++    }
++
++    /* disable pwm controller */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PER;
++        reg_shift[i] = pwm_index[i];
++        reg_width[i] = 0x1;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 0);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    /* disable pwm clk gating */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        get_pccr_reg_offset(pwm_index[i], &reg_offset[i]);
++        reg_shift[i] = PWM_CLK_GATING_SHIFT;
++        reg_width[i] = 0x1;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 0);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    /* disable pwm dead zone,one for the two pwm */
++    get_pdzcr_reg_offset(pwm_index[0], &reg_offset[0]);
++    reg_shift[0] = PWM_DZ_EN_SHIFT;
++    reg_width[0] = PWM_DZ_EN_WIDTH;
++    value[0] = sunxi_pwm_readl(chip, reg_offset[0]);
++    value[0] = SET_BITS(reg_shift[0], reg_width[0], value[0], 0);
++    sunxi_pwm_writel(chip, reg_offset[0], value[0]);
++
++    /* config pin sleep */
++    // sunxi_pwm_pin_set_state(&pwm_pdevice[0]->dev, PWM_PIN_STATE_SLEEP);
++    // sunxi_pwm_pin_set_state(&pwm_pdevice[1]->dev, PWM_PIN_STATE_SLEEP);
++}
++
++static void sunxi_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    int bind_num;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
++    if (bind_num == 255)
++        sunxi_pwm_disable_single(chip, pwm);
++    else
++        sunxi_pwm_disable_dual(chip, pwm, bind_num);
++}
++
++static int sunxi_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
++			    const struct pwm_state *state)
++{
++	int err;
++	bool enabled = pwm->state.enabled;
++
++	if (state->polarity != pwm->state.polarity) {
++		/*
++		 * Changing the polarity of a running PWM is only allowed when
++		 * the PWM driver implements ->apply().
++		 */
++		if (enabled) {
++			sunxi_pwm_disable(chip, pwm);
++
++			enabled = false;
++		}
++
++		err = sunxi_pwm_set_polarity(chip, pwm, state->polarity);
++		if (err)
++			return err;
++	}
++
++
++	if (!state->enabled) {
++		if (enabled) {
++			sunxi_pwm_disable(chip, pwm);
++        }
++
++		return 0;
++	}
++
++	/*
++	 * We cannot skip calling ->config even if state->period ==
++	 * pwm->state.period && state->duty_cycle == pwm->state.duty_cycle
++	 * because we might have exited early in the last call to
++	 * pwm_apply_state because of !state->enabled and so the two values in
++	 * pwm->state might not be configured in hardware.
++	 */
++	err = sunxi_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
++	if (err) {
++		return err;
++    }
++
++	if (!enabled)
++		err = sunxi_pwm_enable(chip, pwm);
++
++	return err;
++}
++
++static const struct pwm_ops sunxi_pwm_ops = {
++	.apply = sunxi_pwm_apply,
++	.owner = THIS_MODULE,
++};
++
++static int sunxi_pwm_probe(struct platform_device *pdev)
++{
++    int ret;
++    struct sunxi_pwm_chip *pwm;
++    struct device_node *np = pdev->dev.of_node;
++    int i;
++    struct platform_device *pwm_pdevice;
++    struct device_node *sub_np;
++
++    pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
++    if (!pwm)
++    {
++        dev_err(&pdev->dev, "failed to allocate memory!\n");
++        return -ENOMEM;
++    }
++
++    /* io map pwm base */
++    pwm->base = (void __iomem *)of_iomap(pdev->dev.of_node, 0);
++    if (!pwm->base)
++    {
++        dev_err(&pdev->dev, "unable to map pwm registers\n");
++        ret = -EINVAL;
++        goto err_iomap;
++    }
++
++    /* read property pwm-number */
++    ret = of_property_read_u32(np, "pwm-number", &pwm->chip.npwm);
++    if (ret < 0)
++    {
++        dev_err(&pdev->dev, "failed to get pwm number: %d, force to one!\n", ret);
++        /* force to one pwm if read property fail */
++        pwm->chip.npwm = 1;
++    }
++
++    /* read property pwm-base */
++    ret = of_property_read_u32(np, "pwm-base", &pwm->chip.base);
++    if (ret < 0)
++    {
++        dev_err(&pdev->dev, "failed to get pwm-base: %d, force to -1 !\n", ret);
++        /* force to one pwm if read property fail */
++        pwm->chip.base = -1;
++    }
++    pwm->chip.dev = &pdev->dev;
++    pwm->chip.ops = &sunxi_pwm_ops;
++
++    /* add pwm chip to pwm-core */
++    ret = pwmchip_add(&pwm->chip);
++    if (ret < 0)
++    {
++        dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
++        goto err_add;
++    }
++    platform_set_drvdata(pdev, pwm);
++
++    pwm->config = devm_kzalloc(&pdev->dev, sizeof(*pwm->config) * pwm->chip.npwm, GFP_KERNEL);
++    if (!pwm->config)
++    {
++        dev_err(&pdev->dev, "failed to allocate memory!\n");
++        goto err_alloc;
++    }
++
++    for (i = 0; i < pwm->chip.npwm; i++)
++    {
++        sub_np = of_parse_phandle(np, "sunxi-pwms", i);
++        if (IS_ERR_OR_NULL(sub_np))
++        {
++            pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++            return -EINVAL;
++        }
++
++        pwm_pdevice = of_find_device_by_node(sub_np);
++        ret = sunxi_pwm_get_config(pwm_pdevice, &pwm->config[i]);
++        if (ret)
++        {
++            pr_err("Get config failed,exit!\n");
++            goto err_get_config;
++        }
++    }
++
++    pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
++    if (IS_ERR(pwm->clk))
++        return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk),
++                             "get mod clock failed\n");
++
++    pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
++    if (IS_ERR(pwm->bus_clk))
++        return dev_err_probe(&pdev->dev, PTR_ERR(pwm->bus_clk),
++                             "get bus clock failed\n");
++
++    pwm->pwm_rst_clk = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
++    if (IS_ERR(pwm->pwm_rst_clk))
++        return dev_err_probe(&pdev->dev, PTR_ERR(pwm->pwm_rst_clk),
++                             "get reset failed\n");
++
++    /* Deassert reset */
++    ret = reset_control_deassert(pwm->pwm_rst_clk);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
++                ERR_PTR(ret));
++        return ret;
++    }
++
++    ret = clk_prepare_enable(pwm->clk);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "cannot prepare and enable clk %pe\n",
++                ERR_PTR(ret));
++        goto err_alloc;
++    }
++
++    ret = clk_prepare_enable(pwm->bus_clk);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
++                ERR_PTR(ret));
++        goto err_alloc;
++    }
++
++    return 0;
++
++err_get_config:
++err_alloc:
++    pwmchip_remove(&pwm->chip);
++err_add:
++    iounmap(pwm->base);
++err_iomap:
++    return ret;
++}
++
++static int sunxi_pwm_remove(struct platform_device *pdev)
++{
++    struct sunxi_pwm_chip *pwm = platform_get_drvdata(pdev);
++    clk_disable(pwm->clk);
++    clk_disable(pwm->bus_clk);
++    reset_control_assert(pwm->pwm_rst_clk);
++    pwmchip_remove(&pwm->chip);
++
++    return 0;
++}
++
++static int sunxi_pwm_suspend(struct platform_device *pdev, pm_message_t state)
++{
++    return 0;
++}
++
++static int sunxi_pwm_resume(struct platform_device *pdev)
++{
++    return 0;
++}
++
++#if !IS_ENABLED(CONFIG_OF)
++struct platform_device sunxi_pwm_device = {
++    .name = "sunxi_pwm",
++    .id = -1,
++};
++#else
++static const struct of_device_id sunxi_pwm_match[] = {
++    {
++        .compatible = "allwinner,sun50i-h616-pwm",
++    },
++    {},
++};
++MODULE_DEVICE_TABLE(of, sunxi_pwm_match);
++#endif
++
++static struct platform_driver sunxi_pwm_driver = {
++    .probe = sunxi_pwm_probe,
++    .remove = sunxi_pwm_remove,
++    .suspend = sunxi_pwm_suspend,
++    .resume = sunxi_pwm_resume,
++    .driver = {
++        .name = "sunxi_pwm",
++        .owner = THIS_MODULE,
++        .of_match_table = sunxi_pwm_match,
++    },
++};
++
++static int __init pwm_module_init(void)
++{
++    int ret = 0;
++
++#if !IS_ENABLED(CONFIG_OF)
++    ret = platform_device_register(&sunxi_pwm_device);
++#endif
++    if (ret == 0)
++    {
++        ret = platform_driver_register(&sunxi_pwm_driver);
++    }
++
++    return ret;
++}
++
++static void __exit pwm_module_exit(void)
++{
++    platform_driver_unregister(&sunxi_pwm_driver);
++#if !IS_ENABLED(CONFIG_OF)
++    platform_device_unregister(&sunxi_pwm_device);
++#endif
++}
++
++subsys_initcall(pwm_module_init);
++module_exit(pwm_module_exit);
++
++MODULE_AUTHOR("zengqi");
++MODULE_AUTHOR("liuli");
++MODULE_DESCRIPTION("pwm driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:sunxi-pwm");
+diff --git a/drivers/pwm/pwm-sunxi-enhance.h b/drivers/pwm/pwm-sunxi-enhance.h
+new file mode 100644
+index 000000000000..e25e10bf5a3d
+--- /dev/null
++++ b/drivers/pwm/pwm-sunxi-enhance.h
+@@ -0,0 +1,60 @@
++/*
++ * drivers/pwm/pwm-sunxi-new.h
++ *
++ * Allwinnertech pulse-width-modulation controller driver
++ *
++ * Copyright (C) 2018 AllWinner
++ *
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#ifndef __PWM_SUNXI_NEW__H__
++#define __PWM_SUNXI_NEW__H__
++
++#define PWM_PIER	(0x0000)
++#define PWM_PISR	(0x0004)
++#define	PWM_CIER	(0x0010)
++#define	PWM_CISR	(0x0014)
++#define PWM_PCCR01	(0x0020)
++#define PWM_PCCR23	(0x0024)
++#define PWM_PCCR45	(0x0028)
++#define PWM_PCCR67	(0x002c)
++#define PWM_PDZCR01	(0x0030)
++#define PWM_PDZCR23	(0x0034)
++#define	PWM_PDZCR45	(0x0038)
++#define	PWM_PDZCR67	(0x003c)
++#define PWM_PER		(0x0040)
++#define PWM_CER		(0x0044)
++
++#define PWM_PCR_BASE	(0x0060 + 0x0000)
++#define PWM_PPR_BASE	(0x0060 + 0x0004)
++#define PWM_PCNTR_BASE	(0x0060 + 0x0008)
++#define PWM_CCR_BASE	(0x0060 + 0x000c)
++#define	PWM_CRLR_BASE	(0x0060 + 0x0010)
++#define PWM_CFLR_BASE	(0x0060 + 0x0014)
++#define PWM_PCCR8	(0x0300)
++
++#define PWM_ACT_STA_SHIFT	0x8
++#define PWM_ACT_STA_WIDTH	0x1
++#define PWM_CLK_SRC_SHIFT	0x7
++#define PWM_CLK_SRC_WIDTH	0x2
++#define PWM_DIV_M_SHIFT		0x0
++#define PWM_DIV_M_WIDTH		0x4
++#define PWM_PRESCAL_SHIFT	0x0
++#define PWM_PRESCAL_WIDTH	0x8
++#define PWM_ACT_CYCLES_SHIFT	0x0
++#define PWM_ACT_CYCLES_WIDTH	0x10
++#define PWM_PERIOD_CYCLES_SHIFT	0x10
++#define PWM_PERIOD_CYCLES_WIDTH	0x10
++#define PWM_DZ_EN_SHIFT		0x0
++#define PWM_DZ_EN_WIDTH		0x1
++#define PWM_PDZINTV_SHIFT	0x8
++#define PWM_PDZINTV_WIDTH	0x8
++#define PWM_BYPASS_WIDTH	0x1
++#define PWM_CLK_GATING_SHIFT	0x4
++#define PWM_CLK_GATING_WIDTH	0x1
++
++#endif
++
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
new file mode 100644
index 000000000000..7f23b5dc7fbf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
@@ -0,0 +1,659 @@
+From 5d014e2618382e8e9e319d800c7641a22dc58130 Mon Sep 17 00:00:00 2001
+From: Radoslav <radoslavv@centrum.sk>
+Date: Sat, 15 Apr 2023 22:47:26 +0200
+Subject: enable TV Output on OrangePi Zero LTE
+
+Credits to sorce https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/README2.md
+Merged:
+1. sunxi-6.1/0036-wip-h3-h5-cvbs-armbian.patch : makes additions to the "dts", which tells the kernel where are the new devices. Adds kernel code to interact with the tv encoder. With my modifications, now it is applicable to Armbian (this patch came from the LibreElec github).
+    https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/sunxi-6.1/0036-wip-h3-h5-cvbs-armbian.patch
+2. sunxi-6.1/zzzz2-tv.patch : by Armbian user "gleam2003", adds directives to make sure that the dtbo (device tree binary overlay) is compiled
+    https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/sunxi-6.1/zzzz2-tv.patch
+3. sunxi-6.1/zzzz3-tv.patch : more additions to the "dts" and "dtsi" (like C include files), which I noticed were included in "yam" patch, but missing from the LibreElec patch
+    https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/sunxi-6.1/zzzz3-tv.patch
+
+> X-Git-Archeology: - Revision 41260ac309b487d241fec97ffbdeced730bc2d04: https://github.com/armbian/build/commit/41260ac309b487d241fec97ffbdeced730bc2d04
+> X-Git-Archeology:   Date: Sat, 15 Apr 2023 22:47:26 +0200
+> X-Git-Archeology:   From: Radoslav <radoslavv@centrum.sk>
+> X-Git-Archeology:   Subject: h3-tve (arm-dts-sun8i-h3-orangepizero-add_tve.patch)
+---
+ arch/arm/boot/dts/allwinner/overlay/Makefile  |  1 +
+ .../overlay/README.sun8i-h3-overlays          | 10 ++
+ .../dts/allwinner/overlay/sun8i-h3-tve.dtso   | 34 +++++++
+ .../allwinner/sun8i-h2-plus-orangepi-zero.dts |  4 +
+ .../dts/allwinner/sun8i-h3-orangepi-pc.dts    |  4 +
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi     | 22 +++++
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi  | 95 ++++++++++++++++++-
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  1 +
+ .../overlay/README.sun50i-h5-overlays         |  5 +
+ .../dts/allwinner/overlay/sun50i-h5-tve.dtso  | 34 +++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  | 22 +++++
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c           | 14 ++-
+ drivers/gpu/drm/sun4i/Makefile                |  2 +-
+ drivers/gpu/drm/sun4i/sun4i_tv.c              | 35 ++++++-
+ drivers/gpu/drm/sun4i/sun8i_mixer.c           | 36 ++++++-
+ drivers/gpu/drm/sun4i/sun8i_mixer.h           |  5 +-
+ 16 files changed, 310 insertions(+), 14 deletions(-)
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso
+
+diff --git a/arch/arm/boot/dts/allwinner/overlay/Makefile b/arch/arm/boot/dts/allwinner/overlay/Makefile
+index 560f926b7018..23ecb62e2478 100644
+--- a/arch/arm/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm/boot/dts/allwinner/overlay/Makefile
+@@ -80,6 +80,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-h3-usbhost2.dtbo \
+ 	sun8i-h3-usbhost3.dtbo \
+ 	sun8i-h3-w1-gpio.dtbo \
++        sun8i-h3-tve.dtbo \
+ 	sun8i-r40-i2c2.dtbo \
+ 	sun8i-r40-i2c3.dtbo \
+ 	sun8i-r40-spi-spidev0.dtbo \
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+index 302973491051..a347fe7b0e81 100644
+--- a/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+@@ -34,6 +34,7 @@ adding fixed software (GPIO) chip selects is possible with a separate overlay
+ - usbhost2
+ - usbhost3
+ - w1-gpio
++- tve
+ 
+ ### Overlay details:
+ 
+@@ -248,3 +249,12 @@ param_w1_pin_int_pullup (bool)
+ 	Set to 1 to enable the pull-up
+ 	This option should not be used with multiple devices, parasite power setup
+ 		or long wires -	please use external pull-up resistor instead
++
++### tve
++
++Activates Composite TV Encoder
++
++Parameters:
++	Unknown at this stage. 
++	Maybe none. 
++	Not sure how to change the mode between PAL/NTSC.
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso
+new file mode 100644
+index 000000000000..07ba7ba713dd
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso
+@@ -0,0 +1,34 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++	
++	fragment@0 {
++		target = <&de>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&mixer1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&tcon1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@3 {
++		target = <&tve>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+index 7b42ab8b5180..330a79390238 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+@@ -180,6 +180,10 @@ flash@0 {
+ 	};
+ };
+ 
++&tve {
++        status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+index 624e248e3ffc..01c3a7f7620a 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+@@ -214,6 +214,10 @@ &sound_hdmi {
+ 	status = "okay";
+ };
+ 
++&tve {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index 8c2f597772fe..35c864fe4823 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -295,6 +295,20 @@ ths: thermal-sensor@1c25000 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <0>;
+ 		};
++
++		tve: tv-encoder@1e00000 {
++			compatible = "allwinner,sun8i-h3-tv-encoder";
++			reg = <0x01e00000 0x1000>;
++			clocks = <&ccu CLK_BUS_TVE>;
++			resets = <&ccu RST_BUS_TVE>;
++			status = "disabled";
++
++			port {
++				tve_in_tcon1: endpoint {
++					remote-endpoint = <&tcon1_out_tve>;
++				};
++			};
++		};
+ 	};
+ 
+ 	thermal-zones {
+@@ -384,6 +398,10 @@ &mbus {
+ 	compatible = "allwinner,sun8i-h3-mbus";
+ };
+ 
++&mixer1 {
++	resets = <&display_clocks RST_WB>;
++};
++
+ &mmc0 {
+ 	compatible = "allwinner,sun7i-a20-mmc";
+ 	clocks = <&ccu CLK_BUS_MMC0>,
+@@ -431,3 +449,7 @@ &rtc {
+ &sid {
+ 	compatible = "allwinner,sun8i-h3-sid";
+ };
++
++&tcon1_out_tve {
++	remote-endpoint = <&tve_in_tcon1>;
++};
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 5a3fb7644dd1..2e211b39b6cf 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -102,7 +102,7 @@ osc32k: osc32k_clk {
+ 
+ 	de: display-engine {
+ 		compatible = "allwinner,sun8i-h3-display-engine";
+-		allwinner,pipelines = <&mixer0>;
++		allwinner,pipelines = <&mixer0>, <&mixer1>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -160,11 +160,50 @@ ports {
+ 				#size-cells = <0>;
+ 
+ 				mixer0_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
+ 					reg = <1>;
+ 
+-					mixer0_out_tcon0: endpoint {
++					mixer0_out_tcon0: endpoint@0 {
++						reg = <0>;
+ 						remote-endpoint = <&tcon0_in_mixer0>;
+ 					};
++
++					mixer0_out_tcon1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon1_in_mixer0>;
++					};
++				};
++			};
++		};
++
++		mixer1: mixer@1200000 {
++			compatible = "allwinner,sun8i-h3-de2-mixer-1";
++			reg = <0x01200000 0x100000>;
++			clocks = <&display_clocks CLK_BUS_MIXER1>,
++				 <&display_clocks CLK_MIXER1>;
++			clock-names = "bus",
++				      "mod";
++			/* reset is added by SoC dtsi */
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				mixer1_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <1>;
++
++					mixer1_out_tcon0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon0_in_mixer1>;
++					};
++
++					mixer1_out_tcon1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon1_in_mixer1>;
++					};
+ 				};
+ 			};
+ 		};
+@@ -193,11 +232,19 @@ ports {
+ 				#size-cells = <0>;
+ 
+ 				tcon0_in: port@0 {
++					#address-cells = <1>;
++					#size-cells = <0>;
+ 					reg = <0>;
+ 
+-					tcon0_in_mixer0: endpoint {
++					tcon0_in_mixer0: endpoint@0 {
++						reg = <0>;
+ 						remote-endpoint = <&mixer0_out_tcon0>;
+ 					};
++
++					tcon0_in_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&mixer1_out_tcon0>;
++					};
+ 				};
+ 
+ 				tcon0_out: port@1 {
+@@ -213,6 +260,48 @@ tcon0_out_hdmi: endpoint@1 {
+ 			};
+ 		};
+ 
++		tcon1: lcd-controller@1c0d000 {
++			compatible = "allwinner,sun8i-h3-tcon-tv",
++				     "allwinner,sun8i-a83t-tcon-tv";
++			reg = <0x01c0d000 0x1000>;
++			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TVE>;
++			clock-names = "ahb", "tcon-ch1";
++			resets = <&ccu RST_BUS_TCON1>;
++			reset-names = "lcd";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon1_in: port@0 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <0>;
++
++					tcon1_in_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&mixer0_out_tcon1>;
++					};
++
++					tcon1_in_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&mixer1_out_tcon1>;
++					};
++				};
++
++				tcon1_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <1>;
++
++					tcon1_out_tve: endpoint@1 {
++						reg = <1>;
++					};
++				};
++			};
++		};
++
+ 		mmc0: mmc@1c0f000 {
+ 			/* compatible and clocks are in per SoC .dtsi file */
+ 			reg = <0x01c0f000 0x1000>;
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index fb6b30d5753e..84711585fc86 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h5-spi-add-cs1.dtbo \
+ 	sun50i-h5-spi-jedec-nor.dtbo \
+ 	sun50i-h5-spi-spidev.dtbo \
++	sun50i-h5-tve.dtbo \
+ 	sun50i-h5-uart1.dtbo \
+ 	sun50i-h5-uart2.dtbo \
+ 	sun50i-h5-uart3.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+index 1ac7fbcf62d1..a2ef4427c65b 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+@@ -26,6 +26,7 @@ adding fixed software (GPIO) chip selects is possible with a separate overlay
+ - spi-add-cs1
+ - spi-jedec-nor
+ - spi-spidev
++- tve
+ - uart1
+ - uart2
+ - uart3
+@@ -170,6 +171,10 @@ param_spidev_max_freq (int)
+ 	Default: 1000000
+ 	Range: 3000 - 100000000
+ 
++### tve
++
++Activates Composite TV Encoder
++
+ ### uart1
+ 
+ Activates serial port 1 (/dev/ttyS1)
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso
+new file mode 100644
+index 000000000000..73e6e1215a5a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso
+@@ -0,0 +1,34 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h5";
++
++	fragment@0 {
++		target = <&de>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&mixer1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&tcon1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@3 {
++		target = <&tve>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index c63e0871658e..fee2d680d2ca 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -203,6 +203,20 @@ ths: thermal-sensor@1c25000 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <1>;
+ 		};
++
++		tve: tv-encoder@1e40000 {
++			compatible = "allwinner,sun50i-h5-tv-encoder";
++			reg = <0x01e40000 0x1000>;
++			clocks = <&ccu CLK_BUS_TVE>;
++			resets = <&ccu RST_BUS_TVE>;
++			status = "disabled";
++
++			port {
++				tve_in_tcon1: endpoint {
++					remote-endpoint = <&tcon1_out_tve>;
++				};
++			};
++		};
+ 	};
+ 
+ 	thermal-zones {
+@@ -307,6 +321,10 @@ &mbus {
+ 	compatible = "allwinner,sun50i-h5-mbus";
+ };
+ 
++&mixer1 {
++	resets = <&display_clocks RST_MIXER1>;
++};
++
+ &mmc0 {
+ 	compatible = "allwinner,sun50i-h5-mmc",
+ 		     "allwinner,sun50i-a64-mmc";
+@@ -342,3 +360,7 @@ &rtc {
+ &sid {
+ 	compatible = "allwinner,sun50i-h5-sid";
+ };
++
++&tcon1_out_tve {
++	remote-endpoint = <&tve_in_tcon1>;
++};
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 5d75d07dec0e..80731b155f6c 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -469,8 +469,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
+ 				 CLK_SET_RATE_PARENT);
+ 
+ static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
+-static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
+-				 0x120, 0, 4, 24, 3, BIT(31), 0);
++struct ccu_div tve_clk = {
++	.enable	= BIT(31),
++	.div	= _SUNXI_CCU_DIV(0, 4),
++	.mux	= _SUNXI_CCU_MUX(24, 3),
++	.fixed_post_div = 16,
++	.common	= {
++		.reg		= 0x120,
++		.features	= CCU_FEATURE_FIXED_POSTDIV,
++		.hw.init	= CLK_HW_INIT_PARENTS("tve", tve_parents,
++						      &ccu_div_ops, 0),
++	},
++};
+ 
+ static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
+ static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
+diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
+index 5e9dc9370584..3a7130623351 100644
+--- a/drivers/gpu/drm/sun4i/Makefile
++++ b/drivers/gpu/drm/sun4i/Makefile
+@@ -19,7 +19,7 @@ sun8i-drm-hdmi-y		+= sun8i_hdmi_phy_clk.o
+ 
+ sun8i-mixer-y			+= sun8i_mixer.o sun8i_ui_layer.o \
+ 				   sun8i_vi_layer.o sun8i_ui_scaler.o \
+-				   sun8i_vi_scaler.o sun8i_csc.o
++				   sun8i_vi_scaler.o sun8i_csc.o sun4i_tv.o
+ 
+ sun4i-tcon-y			+= sun4i_crtc.o
+ sun4i-tcon-y			+= sun4i_tcon_dclk.o
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
+index ec65d9d59de7..d2235d5a7416 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
+@@ -10,6 +10,7 @@
+ #include <linux/component.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/reset.h>
+@@ -159,6 +160,11 @@ struct tv_mode {
+ 	const struct resync_parameters	*resync_params;
+ };
+ 
++struct sun4i_tv_quirks {
++	unsigned int calibration;
++	unsigned int unknown : 1;
++};
++
+ struct sun4i_tv {
+ 	struct drm_connector	connector;
+ 	struct drm_encoder	encoder;
+@@ -419,7 +425,7 @@ static const struct regmap_config sun4i_tv_regmap_config = {
+ 	.reg_bits	= 32,
+ 	.val_bits	= 32,
+ 	.reg_stride	= 4,
+-	.max_register	= SUN4I_TVE_WSS_DATA2_REG,
++	.max_register	= 0x400,
+ 	.name		= "tv-encoder",
+ };
+ 
+@@ -429,13 +435,19 @@ static int sun4i_tv_bind(struct device *dev, struct device *master,
+ 	struct platform_device *pdev = to_platform_device(dev);
+ 	struct drm_device *drm = data;
+ 	struct sun4i_drv *drv = drm->dev_private;
++	const struct sun4i_tv_quirks *quirks;
+ 	struct sun4i_tv *tv;
+ 	void __iomem *regs;
+ 	int ret;
+ 
++	quirks = of_device_get_match_data(dev);
++	if (!quirks)
++		return -EINVAL;
++
+ 	tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
+ 	if (!tv)
+ 		return -ENOMEM;
++
+ 	tv->drv = drv;
+ 	dev_set_drvdata(dev, tv);
+ 
+@@ -472,6 +484,11 @@ static int sun4i_tv_bind(struct device *dev, struct device *master,
+ 	}
+ 	clk_prepare_enable(tv->clk);
+ 
++	if (quirks->calibration)
++		regmap_write(tv->regs, 0x304, quirks->calibration);
++	if (quirks->unknown)
++		regmap_write(tv->regs, 0x30c, 0x00101110);
++
+ 	drm_encoder_helper_add(&tv->encoder,
+ 			       &sun4i_tv_helper_funcs);
+ 	ret = drm_simple_encoder_init(drm, &tv->encoder,
+@@ -551,8 +568,22 @@ static void sun4i_tv_remove(struct platform_device *pdev)
+ 	component_del(&pdev->dev, &sun4i_tv_ops);
+ }
+ 
++static const struct sun4i_tv_quirks a10_quirks = {
++};
++
++static const struct sun4i_tv_quirks h3_quirks = {
++	.calibration = 0x02000c00,
++};
++
++static const struct sun4i_tv_quirks h5_quirks = {
++	.calibration = 0x02850000,
++	.unknown = 1,
++};
++
+ static const struct of_device_id sun4i_tv_of_table[] = {
+-	{ .compatible = "allwinner,sun4i-a10-tv-encoder" },
++	{ .compatible = "allwinner,sun4i-a10-tv-encoder", .data = &a10_quirks },
++	{ .compatible = "allwinner,sun8i-h3-tv-encoder", .data = &h3_quirks },
++	{ .compatible = "allwinner,sun50i-h5-tv-encoder", .data = &h5_quirks },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index a0b9d9e25e63..790c7e0d6761 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -37,6 +37,12 @@ struct de2_fmt_info {
+ 
+ static bool hw_preconfigured;
+ 
++static const u32 sun8i_rgb2yuv_coef[12] = {
++	0x00000107, 0x00000204, 0x00000064, 0x00004200,
++	0x00001f68, 0x00001ed6, 0x000001c2, 0x00020200,
++	0x000001c2, 0x00001e87, 0x00001fb7, 0x00020200,
++};
++
+ static const struct de2_fmt_info de2_formats[] = {
+ 	{
+ 		.drm_fmt = DRM_FORMAT_ARGB8888,
+@@ -432,10 +438,29 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine,
+ 			 interlaced ? "on" : "off");
+ }
+ 
++static void sun8i_mixer_apply_color_correction(struct sunxi_engine *engine)
++{
++	DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
++
++	regmap_bulk_write(engine->regs, SUN8I_MIXER_DCSC_COEF_REG(0),
++			  sun8i_rgb2yuv_coef, 12);
++	regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 1);
++}
++
++static void sun8i_mixer_disable_color_correction(struct sunxi_engine *engine)
++{
++	DRM_DEBUG_DRIVER("Disabling color correction\n");
++
++	/* Disable color correction */
++	regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 0);
++}
++
+ static const struct sunxi_engine_ops sun8i_engine_ops = {
+-	.commit		= sun8i_mixer_commit,
+-	.layers_init	= sun8i_layers_init,
+-	.mode_set	= sun8i_mixer_mode_set,
++	.commit				= sun8i_mixer_commit,
++	.layers_init			= sun8i_layers_init,
++	.mode_set			= sun8i_mixer_mode_set,
++	.apply_color_correction		= sun8i_mixer_apply_color_correction,
++	.disable_color_correction	= sun8i_mixer_disable_color_correction,
+ };
+ 
+ static const struct regmap_config sun8i_mixer_regmap_config = {
+@@ -716,8 +741,9 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+ static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
+ 	.ccsc		= CCSC_MIXER1_LAYOUT,
+ 	.mod_rate	= 432000000,
+-	.scaler_mask	= 0xf,
+-	.ui_num		= 3,
++	.scaler_mask	= 0x3,
++	.scanline_yuv	= 2048,
++	.ui_num		= 1,
+ 	.vi_num		= 1,
+ };
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 68e2741b0962..7bc8efca6980 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -119,6 +119,10 @@
+ /* format 20 is packed YVU444 10-bit */
+ /* format 21 is packed YUV444 10-bit */
+ 
++/* The DCSC sub-engine is used to do color space conversation */
++#define SUN8I_MIXER_DCSC_EN			0xb0000
++#define SUN8I_MIXER_DCSC_COEF_REG(x)		(0xb0010 + 0x4 * (x))
++
+ /*
+  * Sub-engines listed bellow are unused for now. The EN registers are here only
+  * to be used to disable these sub-engines.
+@@ -129,7 +133,6 @@
+ #define SUN8I_MIXER_PEAK_EN			0xa6000
+ #define SUN8I_MIXER_ASE_EN			0xa8000
+ #define SUN8I_MIXER_FCC_EN			0xaa000
+-#define SUN8I_MIXER_DCSC_EN			0xb0000
+ 
+ #define SUN50I_MIXER_FCE_EN			0x70000
+ #define SUN50I_MIXER_PEAK_EN			0x70800
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/orangepi-zero2w-add-dtb.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/orangepi-zero2w-add-dtb.patch
new file mode 100644
index 000000000000..f2e9477ed86c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/orangepi-zero2w-add-dtb.patch
@@ -0,0 +1,572 @@
+From aeccb62b0f4c6891a09790f5f4546dff8cc60815 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Fri, 15 Mar 2024 12:30:26 +0800
+Subject: orangepi-zero2w add dtb
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi |  25 +-
+ .../allwinner/sun50i-h618-orangepi-zero2w.dts | 491 ++++++++++++++++++
+ 3 files changed, 509 insertions(+), 8 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 8b504ee408e7..a957365edc1a 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -56,5 +56,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb
+ 
+ subdir-y	:= $(dts-dirs) overlay
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 362c43d5eb9f..ccaca20eb10b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -209,7 +209,7 @@ video-codec@1c0e000 {
+ 
+ 		syscon: syscon@3000000 {
+ 			compatible = "allwinner,sun50i-h616-system-control";
+-			reg = <0x03000000 0x1000>;
++			reg = <0x03000000 0x30>,<0x03000038 0x0fc8>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			ranges;
+@@ -690,19 +690,28 @@ mdio0: mdio {
+ 		};
+ 
+ 		emac1: ethernet@5030000 {
+-			compatible = "allwinner,sun50i-h616-emac";
+-			syscon = <&syscon 1>;
+-			reg = <0x05030000 0x10000>;
++			compatible = "allwinner,sunxi-gmac";
++			reg = <0x05030000 0x10000>,
++			      <0x03000034 0x4>;
++			reg-names = "gmac1_reg","ephy_reg";
+ 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "macirq";
++			interrupt-names = "gmacirq";
+ 			resets = <&ccu RST_BUS_EMAC1>;
+ 			reset-names = "stmmaceth";
+-			clocks = <&ccu CLK_BUS_EMAC1>;
+-			clock-names = "stmmaceth";
++			clocks = <&ccu CLK_BUS_EMAC1>,<&ccu CLK_EMAC_25M>;
++			clock-names = "bus-emac1","emac-25m";
++			pinctrl-0 = <&rmii_pins>;
++			pinctrl-names = "default";
++			tx-delay = <7>;
++			rx-delay = <31>;
++			phy-rst;
++			gmac-power0;
++			gmac-power1;
++			gmac-power2;
+ 			status = "disabled";
+ 
+ 			mdio1: mdio {
+-				compatible = "snps,dwmac-mdio";
++				compatible = "ethernet-phy-ieee802.3-c22";
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+ 			};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+new file mode 100644
+index 000000000000..b224902f5684
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+@@ -0,0 +1,491 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2023 Arm Ltd.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
++#include "sun50i-h618-cpu-dvfs.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "OrangePi Zero 2W";
++	compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618";
++
++	aliases {
++		serial0 = &uart0;
++		serial2 = &uart2;
++		serial3 = &uart3;
++		serial4 = &uart4;
++		serial5 = &uart5;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			function = LED_FUNCTION_STATUS;
++			color = <LED_COLOR_ID_GREEN>;
++			label = "green_led";
++			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++			linux,default-trigger = "heartbeat";
++		};
++
++		100m_link {
++			label = "100m_link";
++			gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
++			default-state = "off";
++		};
++
++		100m_act {
++			label = "100m_act";
++			gpios = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
++			default-state = "off";
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		/* SY8089 DC/DC converter */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&reg_vcc5v>;
++		regulator-always-on;
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc3v3>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
++
++	ac200_pwm_clk: ac200_clk {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		// pwm5 period_ns = 500 > 334 for select 24M clock.
++		pwms = <&pwm 5 500 0>;
++		clock-frequency = <2000000>;
++		status = "okay";
++	};
++
++	soc {
++		pwm: pwm@300a000 {
++			compatible = "allwinner,sun50i-h616-pwm";
++			reg = <0x0300a000 0x400>;
++			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
++			clock-names = "mod", "bus";
++			resets = <&ccu RST_BUS_PWM>;
++			pwm-number = <6>;
++			pwm-base = <0x0>;
++			sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>;
++			#pwm-cells = <3>;
++			status = "okay";
++		};
++
++		pwm0: pwm0@0300a000 {
++			compatible = "allwinner,sunxi-pwm0";
++		};
++
++		pwm1: pwm1@0300a000 {
++			compatible = "allwinner,sunxi-pwm1";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm1_ph_pin>;
++		};
++
++		pwm2: pwm2@0300a000 {
++			compatible = "allwinner,sunxi-pwm2";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm2_ph_pin>;
++		};
++
++		pwm3: pwm3@0300a000 {
++			compatible = "allwinner,sunxi-pwm3";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm3_ph_pin>;
++		};
++
++		pwm4: pwm4@0300a000 {
++			compatible = "allwinner,sunxi-pwm4";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm4_ph_pin>;
++		};
++
++		pwm5: pwm5@0300a000 {
++			compatible = "allwinner,sunxi-pwm5";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm5_pin>;
++			clk_bypass_output = <0x1>;
++			status = "okay";
++		};
++	};
++};
++
++&de {
++	status = "okay";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "disabled";
++};
++
++&mmc0 {
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
++	bus-width = <4>;
++	vmmc-supply = <&reg_dldo1>;
++	max-frequency = <50000000>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
++&emac0 {
++	status = "disabled";
++};
++
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&rmii_phy>;
++	phy-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&mdio1 {
++	rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&ehci0 {
++	status = "disabled";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "disabled";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ir_rx_pin>;
++	status = "okay";
++};
++
++&spi0  {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
++
++	flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <40000000>;
++	};
++};
++
++&spi1 {
++	status = "disabled";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
++
++	spidev@1 {
++		compatible = "rohm,dh2228fv";
++		status = "disabled";
++		reg = <1>;
++		spi-max-frequency = <1000000>;
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pi_pins>;
++	status = "disabled";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pi_pins>;
++	status = "disabled";
++};
++
++&uart4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart4_pi_pins>;
++	status = "disabled";
++};
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart5_ph_pins>;
++	status = "disabled";
++};
++
++&i2c3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa_pins>;
++
++	ac200_x: mfd@10 {
++		compatible = "x-powers,ac200-sunxi";
++		reg = <0x10>;
++		clocks = <&ac200_pwm_clk>;
++		// ephy id
++		nvmem-cells = <&ephy_calibration>;
++		nvmem-cell-names = "calibration";
++
++		ac200_ephy: phy {
++			compatible = "x-powers,ac200-ephy-sunxi";
++			status = "okay";
++		};
++	};
++};
++
++&i2c4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c4_ph_pins>;
++	status = "disabled";
++};
++
++&usbotg {
++	/*
++	 * PHY0 pins are connected to a USB-C socket, but a role switch
++	 * is not implemented: both CC pins are pulled to GND.
++	 * The VBUS pins power the device, so a fixed peripheral mode
++	 * is the best choice.
++	 * The board can be powered via GPIOs, in this case port0 *can*
++	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
++	 * then provided by the GPIOs. Any user of this setup would
++	 * need to adjust the DT accordingly: dr_mode set to "host",
++	 * enabling OHCI0 and EHCI0.
++	 */
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_vcc5v>;
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
++&sid {
++	ephy_calibration: ephy-calibration@2c {
++		reg = <0x2c 0x2>;
++	};
++};
++
++&cpu_temp_critical {
++	temperature = <100000>;
++};
++
++&gpu_temp_critical {
++	temperature = <100000>;
++};
++
++&ve_temp_critical {
++	temperature = <100000>;
++};
++
++&ddr_temp_critical {
++	temperature = <100000>;
++};
++
++&pio {
++	vcc-pc-supply = <&reg_dldo1>;
++	vcc-pf-supply = <&reg_dldo1>;
++	vcc-pg-supply = <&reg_aldo1>;
++	vcc-ph-supply = <&reg_dldo1>;
++	vcc-pi-supply = <&reg_dldo1>;
++
++	/omit-if-no-ref/
++	i2c0_pi_pins: i2c0-pi-pins {
++		pins = "PI5", "PI6";
++		function = "i2c0";
++	};
++
++	/omit-if-no-ref/
++	i2c1_pi_pins: i2c1-pi-pins {
++		pins = "PI7", "PI8";
++		function = "i2c1";
++	};
++
++	/omit-if-no-ref/
++	i2c2_pi_pins: i2c2-pi-pins {
++		pins = "PI9", "PI10";
++		function = "i2c2";
++	};
++
++    i2c3_pa_pins: i2c3-pa-pins {
++        pins = "PA10", "PA11";
++        function = "i2c3";
++        bias-pull-up;
++    };
++
++	/omit-if-no-ref/
++	i2c4_ph_pins: i2c4-ph-pins {
++		pins = "PH6", "PH7";
++		function = "i2c4";
++	};
++
++	/omit-if-no-ref/
++	uart2_pi_pins: uart2-pi-pins {
++		pins = "PI5", "PI6";
++		function = "uart2";
++	};
++
++	/omit-if-no-ref/
++	uart3_pi_pins: uart3-pi-pins {
++		pins = "PI9", "PI10";
++		function = "uart3";
++	};
++
++	/omit-if-no-ref/
++	uart4_pi_pins: uart4-pi-pins {
++		pins = "PI13", "PI14";
++		function = "uart4";
++	};
++
++	/omit-if-no-ref/
++	uart5_ph_pins: uart5-ph-pins {
++		pins = "PH2", "PH3";
++		function = "uart5";
++	};
++
++	/omit-if-no-ref/
++	spi1_cs1_pin: spi1-cs1-pin {
++		pins = "PH9";
++		function = "spi1";
++	};
++
++	/omit-if-no-ref/
++	pwm1_ph_pin: pwm1-ph-pin {
++		pins = "PH3";
++		function = "pwm1";
++	};
++
++	/omit-if-no-ref/
++	pwm2_ph_pin: pwm2-ph-pin {
++		pins = "PH2";
++		function = "pwm2";
++	};
++
++	/omit-if-no-ref/
++	pwm3_ph_pin: pwm3-ph-pin {
++		pins = "PH0";
++		function = "pwm3";
++	};
++
++	/omit-if-no-ref/
++	pwm4_ph_pin: pwm4-ph-pin {
++		pins = "PH1";
++		function = "pwm4";
++	};
++
++	/omit-if-no-ref/
++	pwm5_pin: pwm5-pin {
++		pins = "PA12";
++		function = "pwm5";
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.7/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch b/patch/kernel/archive/sunxi-6.7/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch
new file mode 100644
index 000000000000..2964914428b2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.7/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch
@@ -0,0 +1,511 @@
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index a957365..812685d 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-early-adopter.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-x96q-lpddr3.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
+new file mode 100644
+index 0000000..ba48e0d
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
+@@ -0,0 +1,491 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2023 Arm Ltd.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
++#include "sun50i-h618-cpu-dvfs.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "X96Q TV-Box";
++	compatible = "x96q,tv-box", "allwinner,sun50i-h616";
++
++	aliases {
++		serial0 = &uart0;
++		serial2 = &uart2;
++		serial3 = &uart3;
++		serial4 = &uart4;
++		serial5 = &uart5;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			function = LED_FUNCTION_STATUS;
++			color = <LED_COLOR_ID_GREEN>;
++			label = "green_led";
++			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++			linux,default-trigger = "heartbeat";
++		};
++
++		100m_link {
++			label = "100m_link";
++			gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
++			default-state = "off";
++		};
++
++		100m_act {
++			label = "100m_act";
++			gpios = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
++			default-state = "off";
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		/* SY8089 DC/DC converter */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&reg_vcc5v>;
++		regulator-always-on;
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc3v3>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
++
++	ac200_pwm_clk: ac200_clk {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		// pwm5 period_ns = 500 > 334 for select 24M clock.
++		pwms = <&pwm 5 500 0>;
++		clock-frequency = <2000000>;
++		status = "okay";
++	};
++
++	soc {
++		pwm: pwm@300a000 {
++			compatible = "allwinner,sun50i-h616-pwm";
++			reg = <0x0300a000 0x400>;
++			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
++			clock-names = "mod", "bus";
++			resets = <&ccu RST_BUS_PWM>;
++			pwm-number = <6>;
++			pwm-base = <0x0>;
++			sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>;
++			#pwm-cells = <3>;
++			status = "okay";
++		};
++
++		pwm0: pwm0@0300a000 {
++			compatible = "allwinner,sunxi-pwm0";
++		};
++
++		pwm1: pwm1@0300a000 {
++			compatible = "allwinner,sunxi-pwm1";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm1_ph_pin>;
++		};
++
++		pwm2: pwm2@0300a000 {
++			compatible = "allwinner,sunxi-pwm2";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm2_ph_pin>;
++		};
++
++		pwm3: pwm3@0300a000 {
++			compatible = "allwinner,sunxi-pwm3";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm3_ph_pin>;
++		};
++
++		pwm4: pwm4@0300a000 {
++			compatible = "allwinner,sunxi-pwm4";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm4_ph_pin>;
++		};
++
++		pwm5: pwm5@0300a000 {
++			compatible = "allwinner,sunxi-pwm5";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm5_pin>;
++			clk_bypass_output = <0x1>;
++			status = "okay";
++		};
++	};
++};
++
++&de {
++	status = "okay";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "disabled";
++};
++
++&mmc0 {
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
++	bus-width = <4>;
++	vmmc-supply = <&reg_dldo1>;
++	max-frequency = <50000000>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
++&emac0 {
++	status = "disabled";
++};
++
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&rmii_phy>;
++	phy-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&mdio1 {
++	rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&ehci0 {
++	status = "disabled";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "disabled";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ir_rx_pin>;
++	status = "okay";
++};
++
++&spi0  {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
++
++	flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <40000000>;
++	};
++};
++
++&spi1 {
++	status = "disabled";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
++
++	spidev@1 {
++		compatible = "rohm,dh2228fv";
++		status = "disabled";
++		reg = <1>;
++		spi-max-frequency = <1000000>;
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pi_pins>;
++	status = "disabled";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pi_pins>;
++	status = "disabled";
++};
++
++&uart4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart4_pi_pins>;
++	status = "disabled";
++};
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart5_ph_pins>;
++	status = "disabled";
++};
++
++&i2c3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa_pins>;
++
++	ac200_x: mfd@10 {
++		compatible = "x-powers,ac200-sunxi";
++		reg = <0x10>;
++		clocks = <&ac200_pwm_clk>;
++		// ephy id
++		nvmem-cells = <&ephy_calibration>;
++		nvmem-cell-names = "calibration";
++
++		ac200_ephy: phy {
++			compatible = "x-powers,ac200-ephy-sunxi";
++			status = "okay";
++		};
++	};
++};
++
++&i2c4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c4_ph_pins>;
++	status = "disabled";
++};
++
++&usbotg {
++	/*
++	 * PHY0 pins are connected to a USB-C socket, but a role switch
++	 * is not implemented: both CC pins are pulled to GND.
++	 * The VBUS pins power the device, so a fixed peripheral mode
++	 * is the best choice.
++	 * The board can be powered via GPIOs, in this case port0 *can*
++	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
++	 * then provided by the GPIOs. Any user of this setup would
++	 * need to adjust the DT accordingly: dr_mode set to "host",
++	 * enabling OHCI0 and EHCI0.
++	 */
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_vcc5v>;
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
++&sid {
++	ephy_calibration: ephy-calibration@2c {
++		reg = <0x2c 0x2>;
++	};
++};
++
++&cpu_temp_critical {
++	temperature = <100000>;
++};
++
++&gpu_temp_critical {
++	temperature = <100000>;
++};
++
++&ve_temp_critical {
++	temperature = <100000>;
++};
++
++&ddr_temp_critical {
++	temperature = <100000>;
++};
++
++&pio {
++	vcc-pc-supply = <&reg_dldo1>;
++	vcc-pf-supply = <&reg_dldo1>;
++	vcc-pg-supply = <&reg_aldo1>;
++	vcc-ph-supply = <&reg_dldo1>;
++	vcc-pi-supply = <&reg_dldo1>;
++
++	/omit-if-no-ref/
++	i2c0_pi_pins: i2c0-pi-pins {
++		pins = "PI5", "PI6";
++		function = "i2c0";
++	};
++
++	/omit-if-no-ref/
++	i2c1_pi_pins: i2c1-pi-pins {
++		pins = "PI7", "PI8";
++		function = "i2c1";
++	};
++
++	/omit-if-no-ref/
++	i2c2_pi_pins: i2c2-pi-pins {
++		pins = "PI9", "PI10";
++		function = "i2c2";
++	};
++
++    i2c3_pa_pins: i2c3-pa-pins {
++        pins = "PA10", "PA11";
++        function = "i2c3";
++        bias-pull-up;
++    };
++
++	/omit-if-no-ref/
++	i2c4_ph_pins: i2c4-ph-pins {
++		pins = "PH6", "PH7";
++		function = "i2c4";
++	};
++
++	/omit-if-no-ref/
++	uart2_pi_pins: uart2-pi-pins {
++		pins = "PI5", "PI6";
++		function = "uart2";
++	};
++
++	/omit-if-no-ref/
++	uart3_pi_pins: uart3-pi-pins {
++		pins = "PI9", "PI10";
++		function = "uart3";
++	};
++
++	/omit-if-no-ref/
++	uart4_pi_pins: uart4-pi-pins {
++		pins = "PI13", "PI14";
++		function = "uart4";
++	};
++
++	/omit-if-no-ref/
++	uart5_ph_pins: uart5-ph-pins {
++		pins = "PH2", "PH3";
++		function = "uart5";
++	};
++
++	/omit-if-no-ref/
++	spi1_cs1_pin: spi1-cs1-pin {
++		pins = "PH9";
++		function = "spi1";
++	};
++
++	/omit-if-no-ref/
++	pwm1_ph_pin: pwm1-ph-pin {
++		pins = "PH3";
++		function = "pwm1";
++	};
++
++	/omit-if-no-ref/
++	pwm2_ph_pin: pwm2-ph-pin {
++		pins = "PH2";
++		function = "pwm2";
++	};
++
++	/omit-if-no-ref/
++	pwm3_ph_pin: pwm3-ph-pin {
++		pins = "PH0";
++		function = "pwm3";
++	};
++
++	/omit-if-no-ref/
++	pwm4_ph_pin: pwm4-ph-pin {
++		pins = "PH1";
++		function = "pwm4";
++	};
++
++	/omit-if-no-ref/
++	pwm5_pin: pwm5-pin {
++		pins = "PA12";
++		function = "pwm5";
++	};
++};
+
diff --git a/patch/kernel/archive/sunxi-6.7/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-emac1.patch b/patch/kernel/archive/sunxi-6.7/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-emac1.patch
new file mode 120000
index 000000000000..93a6f46415e3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.7/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-emac1.patch
@@ -0,0 +1 @@
+../../sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-emac1.patch
\ No newline at end of file
diff --git a/patch/kernel/archive/sunxi-6.7/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-hdmi.patch b/patch/kernel/archive/sunxi-6.7/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-hdmi.patch
new file mode 120000
index 000000000000..0de064853345
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.7/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-hdmi.patch
@@ -0,0 +1 @@
+../../sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-enable-hdmi.patch
\ No newline at end of file
diff --git a/patch/kernel/archive/sunxi-6.9/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch b/patch/kernel/archive/sunxi-6.9/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch
new file mode 100644
index 000000000000..fd0ed1d2c251
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch
@@ -0,0 +1,63 @@
+From d0f6b8b0000847160766e3b9df8a8c2b61d543d0 Mon Sep 17 00:00:00 2001
+From: Mikhail Iakhiaev <mikhailai@gmail.com>
+Date: Mon, 29 Jul 2024 09:50:36 -0700
+Subject: arm/patch: call flush_icache ASAP after writing new instruction.
+
+The patch moves flush_icache before the patch_unmap call.
+The change avoids the possibility of the CPU seeing
+partially-patched instructions if a function from patch_unmap
+call tree has just been patched. That HAS been observed
+in practice, leading to kernel panic or freezing in early boot:
+https://bugzilla.kernel.org/show_bug.cgi?id=219089
+Specifically, the patch_unmap invokes _raw_spin_unlock_irqrestore
+(could be non-inlined) and that function is being patched
+during the ftrace_init, so the original code would run the
+patched code BEFORE flushing the icache.
+
+Note, some arches are more careful about flushing icache early. E.g.
+arch/riscv/kernel/patch.c:
+  __patch_insn_set and __patch_insn_write call the
+  local_flush_icache_range before the patch_unmap and have an
+  explicit comment about this.
+arch/x86/kernel/alternative.c:
+  text_poke_early calls sync_core (flushes icache) before
+  local_irq_restore.
+
+Closes: https://bugzilla.kernel.org/show_bug.cgi?id=219089
+Signed-off-by: Mikhail Iakhiaev <mikhailai@gmail.com>
+
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ arch/arm/kernel/patch.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/kernel/patch.c b/arch/arm/kernel/patch.c
+index e9e828b6bb30..f003867f085a 100644
+--- a/arch/arm/kernel/patch.c
++++ b/arch/arm/kernel/patch.c
+@@ -99,13 +99,19 @@ void __kprobes __patch_text_real(void *addr, unsigned int insn, bool remap)
+ 		size = sizeof(u32);
+ 	}
+ 
+-	if (waddr != addr) {
++	if (waddr != addr)
+ 		flush_kernel_vmap_range(waddr, twopage ? size / 2 : size);
+-		patch_unmap(FIX_TEXT_POKE0, &flags);
+-	}
+ 
+ 	flush_icache_range((uintptr_t)(addr),
+ 			   (uintptr_t)(addr) + size);
++
++	/* Can only call 'patch_unmap' after flushing dcache and icache,
++	 * because it calls 'raw_spin_unlock_irqrestore', but that may
++	 * happen to be the very function we're currently patching
++	 * (as it happens during the ftrace init).
++	 */
++	if (waddr != addr)
++		patch_unmap(FIX_TEXT_POKE0, &flags);
+ }
+ 
+ static int __kprobes patch_text_stop_machine(void *data)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch
new file mode 100644
index 000000000000..055398963704
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch
@@ -0,0 +1,31 @@
+From 7a6264fac2099b181564b09baa283157f19cc069 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Mon, 26 Jun 2023 13:29:46 +0000
+Subject: ARM: dts: sun8i: nanopiduo2: Use key-0 as power button
+
+The onboard button key-0 was not marked as power button. This meant
+that once the board was suspended, there was no way to bring it back
+to life. Mark key-0 as power button so that it can be used to bring
+the board back to life
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+index 343b02b97155..4878d27bab3e 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+@@ -42,8 +42,9 @@ gpio-keys {
+ 
+ 		key-0 {
+ 			label = "k1";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */
++			wakeup-source;
+ 		};
+ 	};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch
new file mode 100644
index 000000000000..8b6b02ca1082
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch
@@ -0,0 +1,31 @@
+From c6de1fe93692bf97c0057346eeadbab3b71d05d3 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Mon, 26 Jun 2023 13:53:14 +0000
+Subject: ARM: dts: sun8i: nanopiduo2: enable ethernet
+
+NanoPi Duo2 has pinout for ethernet. Lets enable the same in dts
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+index 4878d27bab3e..8669fd0879e7 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+@@ -105,6 +105,13 @@ &ehci0 {
+ 	status = "okay";
+ };
+ 
++&emac {
++	phy-handle = <&int_mii_phy>;
++	phy-mode = "mii";
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
+ &mmc0 {
+ 	bus-width = <4>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/ASoC-AC200-Initial-driver.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/ASoC-AC200-Initial-driver.patch
new file mode 100644
index 000000000000..203f5558ce4f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/ASoC-AC200-Initial-driver.patch
@@ -0,0 +1,844 @@
+From 71ab505efa74deadc7878a1b390089a6485c0f83 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Thu, 1 Sep 2022 17:36:53 +0200
+Subject: ASoC: AC200: Initial driver
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ sound/soc/codecs/Kconfig  |  10 +
+ sound/soc/codecs/Makefile |   2 +
+ sound/soc/codecs/ac200.c  | 774 ++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 786 insertions(+)
+ create mode 100644 sound/soc/codecs/ac200.c
+
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index d0f114a11714..8d0fd8879f38 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -16,6 +16,7 @@ config SND_SOC_ALL_CODECS
+ 	depends on COMPILE_TEST
+ 	imply SND_SOC_88PM860X
+ 	imply SND_SOC_AB8500_CODEC
++	imply SND_SOC_AC200_CODEC
+ 	imply SND_SOC_AC97_CODEC
+ 	imply SND_SOC_AD1836
+ 	imply SND_SOC_AD193X_SPI
+@@ -402,6 +403,15 @@ config SND_SOC_AB8500_CODEC
+ 	tristate
+ 	depends on ABX500_CORE
+ 
++config SND_SOC_AC200_CODEC
++	tristate "AC200 Codec"
++	depends on MFD_AC200
++	help
++	  Enable support for X-Powers AC200 analog audio codec.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called snd-soc-ac200.
++
+ config SND_SOC_AC97_CODEC
+ 	tristate "Build generic ASoC AC97 CODEC driver"
+ 	select SND_AC97_CODEC
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index 371a30250ef7..0a8c0f7df3d0 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ snd-soc-88pm860x-objs := 88pm860x-codec.o
+ snd-soc-ab8500-codec-objs := ab8500-codec.o
++snd-soc-ac200-objs := ac200.o
+ snd-soc-ac97-objs := ac97.o
+ snd-soc-ad1836-objs := ad1836.o
+ snd-soc-ad193x-objs := ad193x.o
+@@ -396,6 +397,7 @@ snd-soc-simple-mux-objs := simple-mux.o
+ 
+ obj-$(CONFIG_SND_SOC_88PM860X)	+= snd-soc-88pm860x.o
+ obj-$(CONFIG_SND_SOC_AB8500_CODEC)	+= snd-soc-ab8500-codec.o
++obj-$(CONFIG_SND_SOC_AC200_CODEC)	+= snd-soc-ac200.o
+ obj-$(CONFIG_SND_SOC_AC97_CODEC)	+= snd-soc-ac97.o
+ obj-$(CONFIG_SND_SOC_AD1836)	+= snd-soc-ad1836.o
+ obj-$(CONFIG_SND_SOC_AD193X)	+= snd-soc-ad193x.o
+diff --git a/sound/soc/codecs/ac200.c b/sound/soc/codecs/ac200.c
+new file mode 100644
+index 000000000000..113a45408116
+--- /dev/null
++++ b/sound/soc/codecs/ac200.c
+@@ -0,0 +1,774 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * X-Powers AC200 Codec Driver
++ *
++ * Copyright (C) 2022 Jernej Skrabec <jernej.skrabec@gmail.com>
++ */
++
++#include <linux/module.h>
++#include <linux/regmap.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/tlv.h>
++
++#define AC200_CODEC_RATES (SNDRV_PCM_RATE_8000 | \
++			   SNDRV_PCM_RATE_11025 | \
++			   SNDRV_PCM_RATE_16000 | \
++			   SNDRV_PCM_RATE_22050 | \
++			   SNDRV_PCM_RATE_32000 | \
++			   SNDRV_PCM_RATE_44100 | \
++			   SNDRV_PCM_RATE_48000 | \
++			   SNDRV_PCM_RATE_96000 | \
++			   SNDRV_PCM_RATE_192000 | \
++			   SNDRV_PCM_RATE_KNOT)
++
++#define AC200_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
++			     SNDRV_PCM_FMTBIT_S16_LE | \
++			     SNDRV_PCM_FMTBIT_S20_LE | \
++			     SNDRV_PCM_FMTBIT_S24_LE | \
++			     SNDRV_PCM_FMTBIT_S32_LE)
++
++#define AC200_SYS_AUDIO_CTL0			0x0010
++#define AC200_SYS_AUDIO_CTL0_MCLK_GATING	BIT(1)
++#define AC200_SYS_AUDIO_CTL0_RST_INVALID	BIT(0)
++#define AC200_SYS_AUDIO_CTL1			0x0012
++#define AC200_SYS_AUDIO_CTL1_I2S_IO_EN		BIT(0)
++
++#define AC200_SYS_CLK_CTL			0x2000
++#define AC200_SYS_CLK_CTL_I2S			15
++#define AC200_SYS_CLK_CTL_ADC			3
++#define AC200_SYS_CLK_CTL_DAC			2
++#define AC200_SYS_MOD_RST			0x2002
++#define AC200_SYS_MOD_RST_I2S			15
++#define AC200_SYS_MOD_RST_ADC			3
++#define AC200_SYS_MOD_RST_DAC			2
++#define AC200_SYS_SR_CTL			0x2004
++#define AC200_SYS_SR_CTL_SR_MASK		GENMASK(3, 0)
++#define AC200_SYS_SR_CTL_SR(x)			(x)
++#define AC200_I2S_CTL				0x2100
++#define AC200_I2S_CTL_SDO_EN			3
++#define AC200_I2S_CTL_TX_EN			2
++#define AC200_I2S_CTL_RX_EN			1
++#define AC200_I2S_CTL_GEN			0
++#define AC200_I2S_CLK				0x2102
++#define AC200_I2S_CLK_BCLK_OUT			BIT(15)
++#define AC200_I2S_CLK_LRCK_OUT			BIT(14)
++#define AC200_I2S_CLK_BCLKDIV_MASK		GENMASK(13, 10)
++#define AC200_I2S_CLK_BCLKDIV(x)		((x) << 10)
++#define AC200_I2S_CLK_LRCK_MASK			GENMASK(9, 0)
++#define AC200_I2S_CLK_LRCK(x)			((x) - 1)
++#define AC200_I2S_FMT0				0x2104
++#define AC200_I2S_FMT0_MODE_MASK		GENMASK(15, 14)
++#define AC200_I2S_FMT0_MODE(x)			((x) << 14)
++#define AC200_I2S_FMT0_MODE_PCM			0
++#define AC200_I2S_FMT0_MODE_LEFT		1
++#define AC200_I2S_FMT0_MODE_RIGHT		2
++#define AC200_I2S_FMT0_TX_OFFSET_MASK		GENMASK(11, 10)
++#define AC200_I2S_FMT0_TX_OFFSET(x)		((x) << 10)
++#define AC200_I2S_FMT0_RX_OFFSET_MASK		GENMASK(9, 8)
++#define AC200_I2S_FMT0_RX_OFFSET(x)		((x) << 8)
++#define AC200_I2S_FMT0_SR_MASK			GENMASK(6, 4)
++#define AC200_I2S_FMT0_SR(x)			((x) << 4)
++#define AC200_I2S_FMT0_SW_MASK			GENMASK(3, 1)
++#define AC200_I2S_FMT0_SW(x)			((x) << 1)
++#define AC200_I2S_FMT1				0x2108
++#define AC200_I2S_FMT1_BCLK_POL_INVERT		BIT(15)
++#define AC200_I2S_FMT1_LRCK_POL_INVERT		BIT(14)
++#define AC200_I2S_MIX_SRC			0x2114
++#define AC200_I2S_MIX_SRC_LMIX_DAC		13
++#define AC200_I2S_MIX_SRC_LMIX_ADC		12
++#define AC200_I2S_MIX_SRC_RMIX_DAC		9
++#define AC200_I2S_MIX_SRC_RMIX_ADC		8
++#define AC200_I2S_MIX_GAIN			0x2116
++#define AC200_I2S_MIX_GAIN_LMIX_DAC		13
++#define AC200_I2S_MIX_GAIN_LMIX_ADC		12
++#define AC200_I2S_MIX_GAIN_RMIX_DAC		9
++#define AC200_I2S_MIX_GAIN_RMIX_ADC		8
++#define AC200_I2S_DAC_VOL			0x2118
++#define AC200_I2S_DAC_VOL_LEFT			8
++#define AC200_I2S_DAC_VOL_RIGHT			0
++#define AC200_I2S_ADC_VOL			0x211A
++#define AC200_I2S_ADC_VOL_LEFT			8
++#define AC200_I2S_ADC_VOL_RIGHT			0
++#define AC200_DAC_CTL				0x2200
++#define AC200_DAC_CTL_DAC_EN			15
++#define AC200_DAC_MIX_SRC			0x2202
++#define AC200_DAC_MIX_SRC_LMIX_DAC		13
++#define AC200_DAC_MIX_SRC_LMIX_ADC		12
++#define AC200_DAC_MIX_SRC_RMIX_DAC		9
++#define AC200_DAC_MIX_SRC_RMIX_ADC		8
++#define AC200_DAC_MIX_GAIN			0x2204
++#define AC200_DAC_MIX_GAIN_LMIX_DAC		13
++#define AC200_DAC_MIX_GAIN_LMIX_ADC		12
++#define AC200_DAC_MIX_GAIN_RMIX_DAC		9
++#define AC200_DAC_MIX_GAIN_RMIX_ADC		8
++#define AC200_OUT_MIX_CTL			0x2220
++#define AC200_OUT_MIX_CTL_RDAC_EN		15
++#define AC200_OUT_MIX_CTL_LDAC_EN		14
++#define AC200_OUT_MIX_CTL_RMIX_EN		13
++#define AC200_OUT_MIX_CTL_LMIX_EN		12
++#define AC200_OUT_MIX_CTL_MIC1_VOL		4
++#define AC200_OUT_MIX_CTL_MIC2_VOL		0
++#define AC200_OUT_MIX_SRC			0x2222
++#define AC200_OUT_MIX_SRC_RMIX_MIC1		14
++#define AC200_OUT_MIX_SRC_RMIX_MIC2		13
++#define AC200_OUT_MIX_SRC_RMIX_RDAC		9
++#define AC200_OUT_MIX_SRC_RMIX_LDAC		8
++#define AC200_OUT_MIX_SRC_LMIX_MIC1		6
++#define AC200_OUT_MIX_SRC_LMIX_MIC2		5
++#define AC200_OUT_MIX_SRC_LMIX_RDAC		1
++#define AC200_OUT_MIX_SRC_LMIX_LDAC		0
++#define AC200_LINEOUT_CTL			0x2224
++#define AC200_LINEOUT_CTL_EN			15
++#define AC200_LINEOUT_CTL_LEN			14
++#define AC200_LINEOUT_CTL_REN			13
++#define AC200_LINEOUT_CTL_LMONO			12
++#define AC200_LINEOUT_CTL_RMONO			11
++#define AC200_LINEOUT_CTL_VOL			0
++#define AC200_ADC_CTL				0x2300
++#define AC200_ADC_CTL_ADC_EN			15
++#define AC200_MBIAS_CTL				0x2310
++#define AC200_MBIAS_CTL_MBIAS_EN		15
++#define AC200_MBIAS_CTL_ADDA_BIAS_EN		3
++#define AC200_ADC_MIC_CTL			0x2320
++#define AC200_ADC_MIC_CTL_RADC_EN		15
++#define AC200_ADC_MIC_CTL_LADC_EN		14
++#define AC200_ADC_MIC_CTL_ADC_VOL		8
++#define AC200_ADC_MIC_CTL_MIC1_GAIN_EN		7
++#define AC200_ADC_MIC_CTL_MIC1_BOOST		4
++#define AC200_ADC_MIC_CTL_MIC2_GAIN_EN		3
++#define AC200_ADC_MIC_CTL_MIC2_BOOST		0
++#define AC200_ADC_MIX_SRC			0x2322
++#define AC200_ADC_MIX_SRC_RMIX_MIC1		14
++#define AC200_ADC_MIX_SRC_RMIX_MIC2		13
++#define AC200_ADC_MIX_SRC_RMIX_RMIX		9
++#define AC200_ADC_MIX_SRC_RMIX_LMIX		8
++#define AC200_ADC_MIX_SRC_LMIX_MIC1		6
++#define AC200_ADC_MIX_SRC_LMIX_MIC2		5
++#define AC200_ADC_MIX_SRC_LMIX_LMIX		1
++#define AC200_ADC_MIX_SRC_LMIX_RMIX		0
++
++struct ac200_codec {
++	struct regmap *regmap;
++	unsigned int format;
++};
++
++struct ac200_map {
++	int match;
++	int value;
++};
++
++static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(mixer_scale, -600, 600, 0);
++static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(gain_scale, -450, 150, 0);
++static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(lineout_scale, -4650, 150, 1);
++static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(codec_scale, -12000, 75, 1);
++static const unsigned int mic_scale[] = {
++	TLV_DB_RANGE_HEAD(2),
++	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
++	1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
++};
++
++static const struct snd_kcontrol_new ac200_codec_controls[] = {
++	SOC_DOUBLE_TLV("Master Playback Volume", AC200_I2S_DAC_VOL,
++		       AC200_I2S_DAC_VOL_LEFT, AC200_I2S_DAC_VOL_RIGHT,
++		       0xff, 0, codec_scale),
++	SOC_DOUBLE_TLV("Master Capture Volume", AC200_I2S_ADC_VOL,
++		       AC200_I2S_ADC_VOL_LEFT, AC200_I2S_ADC_VOL_RIGHT,
++		       0xff, 0, codec_scale),
++	SOC_DOUBLE_TLV("I2S ADC Capture Volume", AC200_I2S_MIX_GAIN,
++		       AC200_I2S_MIX_GAIN_LMIX_ADC, AC200_I2S_MIX_GAIN_RMIX_ADC,
++		       0x1, 1, mixer_scale),
++	SOC_DOUBLE_TLV("I2S DAC Capture Volume", AC200_I2S_MIX_GAIN,
++		       AC200_I2S_MIX_GAIN_LMIX_DAC, AC200_I2S_MIX_GAIN_RMIX_DAC,
++		       0x1, 1, mixer_scale),
++	SOC_DOUBLE_TLV("DAC I2S Playback Volume", AC200_DAC_MIX_GAIN,
++		       AC200_DAC_MIX_GAIN_LMIX_DAC, AC200_DAC_MIX_GAIN_RMIX_DAC,
++		       0x1, 1, mixer_scale),
++	SOC_DOUBLE_TLV("ADC Playback Volume", AC200_DAC_MIX_GAIN,
++		       AC200_DAC_MIX_GAIN_LMIX_ADC, AC200_DAC_MIX_GAIN_RMIX_ADC,
++		       0x1, 1, mixer_scale),
++	SOC_SINGLE_TLV("MIC1 Playback Volume", AC200_OUT_MIX_CTL,
++		       AC200_OUT_MIX_CTL_MIC1_VOL, 0x7, 0, gain_scale),
++	SOC_SINGLE_TLV("MIC2 Playback Volume", AC200_OUT_MIX_CTL,
++		       AC200_OUT_MIX_CTL_MIC2_VOL, 0x7, 0, gain_scale),
++	SOC_SINGLE_TLV("ADC Volume", AC200_ADC_MIC_CTL,
++		       AC200_ADC_MIC_CTL_ADC_VOL, 0x07, 0, gain_scale),
++	SOC_SINGLE_TLV("Line Out Playback Volume", AC200_LINEOUT_CTL,
++		       AC200_LINEOUT_CTL_VOL, 0x1f, 0, lineout_scale),
++	SOC_SINGLE_TLV("MIC1 Boost Volume", AC200_ADC_MIC_CTL,
++		       AC200_ADC_MIC_CTL_MIC1_BOOST, 0x07, 0, mic_scale),
++	SOC_SINGLE_TLV("MIC2 Boost Volume", AC200_ADC_MIC_CTL,
++		       AC200_ADC_MIC_CTL_MIC2_BOOST, 0x07, 0, mic_scale),
++	SOC_DOUBLE("Line Out Playback Switch", AC200_LINEOUT_CTL,
++		   AC200_LINEOUT_CTL_LEN, AC200_LINEOUT_CTL_REN, 1, 0),
++};
++
++static const struct snd_kcontrol_new i2s_mixer[] = {
++	SOC_DAPM_DOUBLE("I2S DAC Capture Switch", AC200_I2S_MIX_SRC,
++			AC200_I2S_MIX_SRC_LMIX_DAC,
++			AC200_I2S_MIX_SRC_RMIX_DAC, 1, 0),
++	SOC_DAPM_DOUBLE("I2S ADC Capture Switch", AC200_I2S_MIX_SRC,
++			AC200_I2S_MIX_SRC_LMIX_ADC,
++			AC200_I2S_MIX_SRC_RMIX_ADC, 1, 0),
++};
++
++static const struct snd_kcontrol_new dac_mixer[] = {
++	SOC_DAPM_DOUBLE("DAC I2S Playback Switch", AC200_DAC_MIX_SRC,
++			AC200_DAC_MIX_SRC_LMIX_DAC,
++			AC200_DAC_MIX_SRC_RMIX_DAC, 1, 0),
++	SOC_DAPM_DOUBLE("ADC Playback Switch", AC200_DAC_MIX_SRC,
++			AC200_DAC_MIX_SRC_LMIX_ADC,
++			AC200_DAC_MIX_SRC_RMIX_ADC, 1, 0),
++};
++
++static const struct snd_kcontrol_new output_mixer[] = {
++	SOC_DAPM_DOUBLE("MIC1 Playback Switch", AC200_OUT_MIX_SRC,
++			AC200_OUT_MIX_SRC_LMIX_MIC1,
++			AC200_OUT_MIX_SRC_RMIX_MIC1, 1, 0),
++	SOC_DAPM_DOUBLE("MIC2 Playback Switch", AC200_OUT_MIX_SRC,
++			AC200_OUT_MIX_SRC_LMIX_MIC2,
++			AC200_OUT_MIX_SRC_RMIX_MIC2, 1, 0),
++	SOC_DAPM_DOUBLE("DAC Playback Switch", AC200_OUT_MIX_SRC,
++			AC200_OUT_MIX_SRC_LMIX_LDAC,
++			AC200_OUT_MIX_SRC_RMIX_RDAC, 1, 0),
++	SOC_DAPM_DOUBLE("DAC Reversed Playback Switch", AC200_OUT_MIX_SRC,
++			AC200_OUT_MIX_SRC_LMIX_RDAC,
++			AC200_OUT_MIX_SRC_RMIX_LDAC, 1, 0),
++};
++
++static const struct snd_kcontrol_new input_mixer[] = {
++	SOC_DAPM_DOUBLE("MIC1 Capture Switch", AC200_ADC_MIX_SRC,
++			AC200_ADC_MIX_SRC_LMIX_MIC1,
++			AC200_ADC_MIX_SRC_RMIX_MIC1, 1, 0),
++	SOC_DAPM_DOUBLE("MIC2 Capture Switch", AC200_ADC_MIX_SRC,
++			AC200_ADC_MIX_SRC_LMIX_MIC2,
++			AC200_ADC_MIX_SRC_RMIX_MIC2, 1, 0),
++	SOC_DAPM_DOUBLE("Output Mixer Capture Switch", AC200_ADC_MIX_SRC,
++			AC200_ADC_MIX_SRC_LMIX_LMIX,
++			AC200_ADC_MIX_SRC_RMIX_RMIX, 1, 0),
++	SOC_DAPM_DOUBLE("Output Mixer Reverse Capture Switch",
++			AC200_ADC_MIX_SRC,
++			AC200_ADC_MIX_SRC_LMIX_RMIX,
++			AC200_ADC_MIX_SRC_RMIX_LMIX, 1, 0),
++};
++
++const char * const lineout_mux_enum_text[] = {
++	"Stereo", "Mono",
++};
++
++static SOC_ENUM_DOUBLE_DECL(lineout_mux_enum, AC200_LINEOUT_CTL,
++			    AC200_LINEOUT_CTL_LMONO, AC200_LINEOUT_CTL_RMONO,
++			    lineout_mux_enum_text);
++
++static const struct snd_kcontrol_new lineout_mux =
++	SOC_DAPM_ENUM("Line Out Source Playback Route", lineout_mux_enum);
++
++static const struct snd_soc_dapm_widget ac200_codec_dapm_widgets[] = {
++	/* Regulator */
++	SND_SOC_DAPM_REGULATOR_SUPPLY("avcc", 0, 0),
++
++	/* System clocks */
++	SND_SOC_DAPM_SUPPLY("CLK SYS I2S", AC200_SYS_CLK_CTL,
++			    AC200_SYS_CLK_CTL_I2S, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("CLK SYS DAC", AC200_SYS_CLK_CTL,
++			    AC200_SYS_CLK_CTL_DAC, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("CLK SYS ADC", AC200_SYS_CLK_CTL,
++			    AC200_SYS_CLK_CTL_ADC, 0, NULL, 0),
++
++	/* Module resets */
++	SND_SOC_DAPM_SUPPLY("RST SYS I2S", AC200_SYS_MOD_RST,
++			    AC200_SYS_MOD_RST_I2S, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("RST SYS DAC", AC200_SYS_MOD_RST,
++			    AC200_SYS_MOD_RST_DAC, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("RST SYS ADC", AC200_SYS_MOD_RST,
++			    AC200_SYS_MOD_RST_DAC, 0, NULL, 0),
++
++	/* I2S gates */
++	SND_SOC_DAPM_SUPPLY("CLK I2S GEN", AC200_I2S_CTL,
++			    AC200_I2S_CTL_GEN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("CLK I2S SDO", AC200_I2S_CTL,
++			    AC200_I2S_CTL_SDO_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("CLK I2S TX", AC200_I2S_CTL,
++			    AC200_I2S_CTL_TX_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("CLK I2S RX", AC200_I2S_CTL,
++			    AC200_I2S_CTL_RX_EN, 0, NULL, 0),
++
++	/* Module supplies */
++	SND_SOC_DAPM_SUPPLY("ADC Enable", AC200_ADC_CTL,
++			    AC200_ADC_CTL_ADC_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("DAC Enable", AC200_DAC_CTL,
++			    AC200_DAC_CTL_DAC_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("Line Out Enable", AC200_LINEOUT_CTL,
++			    AC200_LINEOUT_CTL_EN, 0, NULL, 0),
++
++	/* Bias */
++	SND_SOC_DAPM_SUPPLY("MIC Bias", AC200_MBIAS_CTL,
++			    AC200_MBIAS_CTL_MBIAS_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("ADDA Bias", AC200_MBIAS_CTL,
++			    AC200_MBIAS_CTL_ADDA_BIAS_EN, 0, NULL, 0),
++
++	/* DAC */
++	SND_SOC_DAPM_DAC("Left DAC", "Playback", AC200_OUT_MIX_CTL,
++			 AC200_OUT_MIX_CTL_LDAC_EN, 0),
++	SND_SOC_DAPM_DAC("Right DAC", "Playback", AC200_OUT_MIX_CTL,
++			 AC200_OUT_MIX_CTL_RDAC_EN, 0),
++
++	/* ADC */
++	SND_SOC_DAPM_ADC("Left ADC", "Capture", AC200_ADC_MIC_CTL,
++			 AC200_ADC_MIC_CTL_LADC_EN, 0),
++	SND_SOC_DAPM_ADC("Right ADC", "Capture", AC200_ADC_MIC_CTL,
++			 AC200_ADC_MIC_CTL_RADC_EN, 0),
++
++	/* Mixers */
++	SND_SOC_DAPM_MIXER("Left Output Mixer", AC200_OUT_MIX_CTL,
++			   AC200_OUT_MIX_CTL_LMIX_EN, 0,
++			   output_mixer, ARRAY_SIZE(output_mixer)),
++	SND_SOC_DAPM_MIXER("Right Output Mixer", AC200_OUT_MIX_CTL,
++			   AC200_OUT_MIX_CTL_RMIX_EN, 0,
++			   output_mixer, ARRAY_SIZE(output_mixer)),
++
++	SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
++			   input_mixer, ARRAY_SIZE(input_mixer)),
++	SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
++			   input_mixer, ARRAY_SIZE(input_mixer)),
++
++	SND_SOC_DAPM_MIXER("Left DAC Mixer", SND_SOC_NOPM, 0, 0,
++			   dac_mixer, ARRAY_SIZE(dac_mixer)),
++	SND_SOC_DAPM_MIXER("Right DAC Mixer", SND_SOC_NOPM, 0, 0,
++			   dac_mixer, ARRAY_SIZE(dac_mixer)),
++
++	SND_SOC_DAPM_MIXER("Left I2S Mixer", SND_SOC_NOPM, 0, 0,
++			   i2s_mixer, ARRAY_SIZE(i2s_mixer)),
++	SND_SOC_DAPM_MIXER("Right I2S Mixer", SND_SOC_NOPM, 0, 0,
++			   i2s_mixer, ARRAY_SIZE(i2s_mixer)),
++
++	/* Muxes */
++	SND_SOC_DAPM_MUX("Line Out Source Playback Route",
++			 SND_SOC_NOPM, 0, 0, &lineout_mux),
++
++	/* Gain/attenuation */
++	SND_SOC_DAPM_PGA("MIC1 Amplifier", AC200_ADC_MIC_CTL,
++			 AC200_ADC_MIC_CTL_MIC1_GAIN_EN, 0, NULL, 0),
++	SND_SOC_DAPM_PGA("MIC2 Amplifier", AC200_ADC_MIC_CTL,
++			 AC200_ADC_MIC_CTL_MIC2_GAIN_EN, 0, NULL, 0),
++
++	/* Inputs */
++	SND_SOC_DAPM_INPUT("MIC1"),
++	SND_SOC_DAPM_INPUT("MIC2"),
++
++	/* Outputs */
++	SND_SOC_DAPM_OUTPUT("LINEOUT"),
++};
++
++static const struct snd_soc_dapm_route ac200_codec_dapm_routes[] = {
++	{ "RST SYS I2S", NULL, "CLK SYS I2S" },
++	{ "RST SYS ADC", NULL, "CLK SYS ADC" },
++	{ "RST SYS DAC", NULL, "CLK SYS DAC" },
++
++	{ "CLK I2S GEN", NULL, "RST SYS I2S" },
++	{ "CLK I2S SDO", NULL, "CLK I2S GEN" },
++	{ "CLK I2S TX", NULL, "CLK I2S SDO" },
++	{ "CLK I2S RX", NULL, "CLK I2S SDO" },
++
++	{ "ADC Enable", NULL, "RST SYS ADC" },
++	{ "ADC Enable", NULL, "ADDA Bias" },
++	{ "ADC Enable", NULL, "avcc" },
++	{ "DAC Enable", NULL, "RST SYS DAC" },
++	{ "DAC Enable", NULL, "ADDA Bias" },
++	{ "DAC Enable", NULL, "avcc" },
++
++	{ "Left DAC", NULL,  "DAC Enable" },
++	{ "Left DAC", NULL,  "CLK I2S RX" },
++	{ "Right DAC", NULL,  "DAC Enable" },
++	{ "Right DAC", NULL,  "CLK I2S RX" },
++
++	{ "Left ADC", NULL,  "ADC Enable" },
++	{ "Left ADC", NULL,  "CLK I2S TX" },
++	{ "Right ADC", NULL,  "ADC Enable" },
++	{ "Right ADC", NULL,  "CLK I2S TX" },
++
++	{ "Left Output Mixer", "MIC1 Playback Switch", "MIC1 Amplifier" },
++	{ "Left Output Mixer", "MIC2 Playback Switch", "MIC2 Amplifier" },
++	{ "Left Output Mixer", "DAC Playback Switch", "Left DAC Mixer" },
++	{ "Left Output Mixer", "DAC Reversed Playback Switch", "Right DAC Mixer" },
++
++	{ "Right Output Mixer", "MIC1 Playback Switch", "MIC1 Amplifier" },
++	{ "Right Output Mixer", "MIC2 Playback Switch", "MIC2 Amplifier" },
++	{ "Right Output Mixer", "DAC Playback Switch", "Right DAC Mixer" },
++	{ "Right Output Mixer", "DAC Reversed Playback Switch", "Left DAC Mixer" },
++
++	{ "Left Input Mixer", "MIC1 Capture Switch", "MIC1 Amplifier" },
++	{ "Left Input Mixer", "MIC2 Capture Switch", "MIC2 Amplifier" },
++	{ "Left Input Mixer", "Output Mixer Capture Switch", "Left Output Mixer" },
++	{ "Left Input Mixer", "Output Mixer Reverse Capture Switch", "Right Output Mixer" },
++
++	{ "Right Input Mixer", "MIC1 Capture Switch", "MIC1 Amplifier" },
++	{ "Right Input Mixer", "MIC2 Capture Switch", "MIC2 Amplifier" },
++	{ "Right Input Mixer", "Output Mixer Capture Switch", "Right Output Mixer" },
++	{ "Right Input Mixer", "Output Mixer Reverse Capture Switch", "Left Output Mixer" },
++
++	{ "Left I2S Mixer", "I2S DAC Capture Switch", "Left DAC" },
++	{ "Left I2S Mixer", "I2S ADC Capture Switch", "Left Input Mixer" },
++	{ "Right I2S Mixer", "I2S DAC Capture Switch", "Right DAC" },
++	{ "Right I2S Mixer", "I2S ADC Capture Switch", "Right Input Mixer" },
++
++	{ "Left DAC Mixer", "DAC I2S Playback Switch", "Left DAC" },
++	{ "Left DAC Mixer", "ADC Playback Switch", "Left Input Mixer" },
++	{ "Right DAC Mixer", "DAC I2S Playback Switch", "Right DAC" },
++	{ "Right DAC Mixer", "ADC Playback Switch", "Right Input Mixer" },
++
++	{ "Line Out Source Playback Route", "Stereo", "Left Output Mixer" },
++	{ "Line Out Source Playback Route", "Stereo", "Right Output Mixer" },
++	{ "Line Out Source Playback Route", "Mono", "Right Output Mixer" },
++	{ "Line Out Source Playback Route", "Mono", "Left Output Mixer" },
++
++	{ "Left ADC", NULL, "Left I2S Mixer" },
++	{ "Right ADC", NULL, "Right I2S Mixer" },
++
++	{ "LINEOUT", NULL, "Line Out Enable", },
++	{ "LINEOUT", NULL, "Line Out Source Playback Route" },
++
++	{ "MIC1", NULL, "MIC Bias" },
++	{ "MIC2", NULL, "MIC Bias" },
++	{ "MIC1 Amplifier", NULL, "MIC1" },
++	{ "MIC2 Amplifier", NULL, "MIC2" },
++};
++
++static int ac200_get_sr_sw(unsigned int width)
++{
++	switch (width) {
++	case 8:
++		return 1;
++	case 12:
++		return 2;
++	case 16:
++		return 3;
++	case 20:
++		return 4;
++	case 24:
++		return 5;
++	case 28:
++		return 6;
++	case 32:
++		return 7;
++	}
++
++	return -EINVAL;
++}
++
++static const struct ac200_map ac200_bclk_div_map[] = {
++	{ .match = 1,	.value = 1 },
++	{ .match = 2,	.value = 2 },
++	{ .match = 4,	.value = 3 },
++	{ .match = 6,	.value = 4 },
++	{ .match = 8,	.value = 5 },
++	{ .match = 12,	.value = 6 },
++	{ .match = 16,	.value = 7 },
++	{ .match = 24,	.value = 8 },
++	{ .match = 32,	.value = 9 },
++	{ .match = 48,	.value = 10 },
++	{ .match = 64,	.value = 11 },
++	{ .match = 96,	.value = 12 },
++	{ .match = 128,	.value = 13 },
++	{ .match = 176,	.value = 14 },
++	{ .match = 192,	.value = 15 },
++};
++
++static int ac200_get_bclk_div(unsigned int sample_rate, unsigned int period)
++{
++	unsigned int sysclk_rate = (sample_rate % 4000) ? 22579200 : 24576000;
++	unsigned int div = sysclk_rate / sample_rate / period;
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(ac200_bclk_div_map); i++) {
++		const struct ac200_map *bdiv = &ac200_bclk_div_map[i];
++
++		if (bdiv->match == div)
++			return bdiv->value;
++	}
++
++	return -EINVAL;
++}
++
++static const struct ac200_map ac200_ssr_map[] = {
++	{ .match = 8000,	.value = 0 },
++	{ .match = 11025,	.value = 1 },
++	{ .match = 12000,	.value = 2 },
++	{ .match = 16000,	.value = 3 },
++	{ .match = 22050,	.value = 4 },
++	{ .match = 24000,	.value = 5 },
++	{ .match = 32000,	.value = 6 },
++	{ .match = 44100,	.value = 7 },
++	{ .match = 48000,	.value = 8 },
++	{ .match = 96000,	.value = 9 },
++	{ .match = 192000,	.value = 10 },
++};
++
++static int ac200_get_ssr(unsigned int sample_rate)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(ac200_ssr_map); i++) {
++		const struct ac200_map *ssr = &ac200_ssr_map[i];
++
++		if (ssr->match == sample_rate)
++			return ssr->value;
++	}
++
++	return -EINVAL;
++}
++
++static int ac200_codec_hw_params(struct snd_pcm_substream *substream,
++				 struct snd_pcm_hw_params *params,
++				 struct snd_soc_dai *dai)
++{
++	struct ac200_codec *priv = snd_soc_dai_get_drvdata(dai);
++	unsigned int slot_width = params_physical_width(params);
++	unsigned int sample_rate = params_rate(params);
++	int sr, period, sw, bclkdiv, ssr;
++
++	sr = ac200_get_sr_sw(params_width(params));
++	if (sr < 0)
++		return sr;
++
++	sw = ac200_get_sr_sw(slot_width);
++	if (sw < 0)
++		return sw;
++
++	regmap_update_bits(priv->regmap, AC200_I2S_FMT0,
++			   AC200_I2S_FMT0_SR_MASK |
++			   AC200_I2S_FMT0_SW_MASK,
++			   AC200_I2S_FMT0_SR(sr) |
++			   AC200_I2S_FMT0_SW(sw));
++
++	switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++	case SND_SOC_DAIFMT_RIGHT_J:
++	case SND_SOC_DAIFMT_LEFT_J:
++		period = slot_width;
++		break;
++	case SND_SOC_DAIFMT_DSP_A:
++	case SND_SOC_DAIFMT_DSP_B:
++		period = slot_width * 2;
++		break;
++	}
++
++	bclkdiv = ac200_get_bclk_div(sample_rate, period);
++	if (bclkdiv < 0)
++		return bclkdiv;
++
++	regmap_update_bits(priv->regmap, AC200_I2S_CLK,
++			   AC200_I2S_CLK_LRCK_MASK |
++			   AC200_I2S_CLK_BCLKDIV_MASK,
++			   AC200_I2S_CLK_LRCK(period) |
++			   AC200_I2S_CLK_BCLKDIV(bclkdiv));
++
++	ssr = ac200_get_ssr(sample_rate);
++	if (ssr < 0)
++		return ssr;
++
++	regmap_update_bits(priv->regmap, AC200_SYS_SR_CTL,
++			   AC200_SYS_SR_CTL_SR_MASK,
++			   AC200_SYS_SR_CTL_SR(ssr));
++
++	return 0;
++}
++
++static int ac200_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++	struct ac200_codec *priv = snd_soc_dai_get_drvdata(dai);
++	unsigned long offset, mode, value;
++
++	priv->format = fmt;
++
++	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
++	case SND_SOC_DAIFMT_CBP_CFP:
++		value = AC200_I2S_CLK_BCLK_OUT | AC200_I2S_CLK_LRCK_OUT;
++		break;
++	case SND_SOC_DAIFMT_CBC_CFP:
++		value = AC200_I2S_CLK_LRCK_OUT;
++		break;
++	case SND_SOC_DAIFMT_CBP_CFC:
++		value = AC200_I2S_CLK_BCLK_OUT;
++		break;
++	case SND_SOC_DAIFMT_CBC_CFC:
++		value = 0;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(priv->regmap, AC200_I2S_CLK,
++			   AC200_I2S_CLK_BCLK_OUT |
++			   AC200_I2S_CLK_LRCK_OUT, value);
++
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++		mode = AC200_I2S_FMT0_MODE_LEFT;
++		offset = 1;
++		break;
++	case SND_SOC_DAIFMT_RIGHT_J:
++		mode = AC200_I2S_FMT0_MODE_RIGHT;
++		offset = 0;
++		break;
++	case SND_SOC_DAIFMT_LEFT_J:
++		mode = AC200_I2S_FMT0_MODE_LEFT;
++		offset = 0;
++		break;
++	case SND_SOC_DAIFMT_DSP_A:
++		mode = AC200_I2S_FMT0_MODE_PCM;
++		offset = 1;
++		break;
++	case SND_SOC_DAIFMT_DSP_B:
++		mode = AC200_I2S_FMT0_MODE_PCM;
++		offset = 0;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(priv->regmap, AC200_I2S_FMT0,
++			   AC200_I2S_FMT0_MODE_MASK |
++			   AC200_I2S_FMT0_TX_OFFSET_MASK |
++			   AC200_I2S_FMT0_RX_OFFSET_MASK,
++			   AC200_I2S_FMT0_MODE(mode) |
++			   AC200_I2S_FMT0_TX_OFFSET(offset) |
++			   AC200_I2S_FMT0_RX_OFFSET(offset));
++
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_NB_NF:
++		value = 0;
++		break;
++	case SND_SOC_DAIFMT_NB_IF:
++		value = AC200_I2S_FMT1_LRCK_POL_INVERT;
++		break;
++	case SND_SOC_DAIFMT_IB_NF:
++		value = AC200_I2S_FMT1_BCLK_POL_INVERT;
++		break;
++	case SND_SOC_DAIFMT_IB_IF:
++		value = AC200_I2S_FMT1_BCLK_POL_INVERT |
++			AC200_I2S_FMT1_LRCK_POL_INVERT;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(priv->regmap, AC200_I2S_FMT1,
++			   AC200_I2S_FMT1_BCLK_POL_INVERT |
++			   AC200_I2S_FMT1_LRCK_POL_INVERT, value);
++
++
++	return 0;
++}
++
++static const struct snd_soc_dai_ops ac200_codec_dai_ops = {
++	.hw_params	= ac200_codec_hw_params,
++	.set_fmt	= ac200_codec_set_fmt,
++};
++
++static struct snd_soc_dai_driver ac200_codec_dai = {
++	.name = "ac200-dai",
++	.playback = {
++		.stream_name = "Playback",
++		.channels_min = 2,
++		.channels_max = 2,
++		.rates = AC200_CODEC_RATES,
++		.formats = AC200_CODEC_FORMATS,
++	},
++	.capture = {
++		.stream_name = "Capture",
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = AC200_CODEC_RATES,
++		.formats = AC200_CODEC_FORMATS,
++	},
++	.ops = &ac200_codec_dai_ops,
++	.symmetric_rate = 1,
++	.symmetric_sample_bits = 1,
++};
++
++static int ac200_codec_component_probe(struct snd_soc_component *component)
++{
++	struct ac200_codec *priv = snd_soc_component_get_drvdata(component);
++
++	snd_soc_component_init_regmap(component, priv->regmap);
++
++	return 0;
++}
++
++static struct snd_soc_component_driver ac200_soc_component = {
++	.controls		= ac200_codec_controls,
++	.num_controls		= ARRAY_SIZE(ac200_codec_controls),
++	.dapm_widgets		= ac200_codec_dapm_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(ac200_codec_dapm_widgets),
++	.dapm_routes		= ac200_codec_dapm_routes,
++	.num_dapm_routes	= ARRAY_SIZE(ac200_codec_dapm_routes),
++	.probe			= ac200_codec_component_probe,
++};
++
++static int ac200_codec_probe(struct platform_device *pdev)
++{
++	struct ac200_codec *priv;
++	int ret;
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(struct ac200_codec), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
++	if (!priv->regmap)
++		return -EPROBE_DEFER;
++
++	platform_set_drvdata(pdev, priv);
++
++	ret = regmap_write(priv->regmap, AC200_SYS_AUDIO_CTL0,
++			   AC200_SYS_AUDIO_CTL0_RST_INVALID |
++			   AC200_SYS_AUDIO_CTL0_MCLK_GATING);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(priv->regmap, AC200_SYS_AUDIO_CTL1,
++			   AC200_SYS_AUDIO_CTL1_I2S_IO_EN);
++	if (ret)
++		return ret;
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &ac200_soc_component,
++					      &ac200_codec_dai, 1);
++
++	if (ret)
++		dev_err(&pdev->dev, "Failed to register codec: %d\n", ret);
++
++	return ret;
++}
++
++static int ac200_codec_remove(struct platform_device *pdev)
++{
++	struct ac200_codec *priv =  dev_get_drvdata(&pdev->dev);
++
++	regmap_write(priv->regmap, AC200_SYS_AUDIO_CTL0, 0);
++	regmap_write(priv->regmap, AC200_SYS_AUDIO_CTL1, 0);
++
++	return 0;
++}
++
++static const struct of_device_id ac200_codec_match[] = {
++	{ .compatible = "x-powers,ac200-codec" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ac200_codec_match);
++
++static struct platform_driver ac200_codec_driver = {
++	.driver = {
++		.name = "ac200-codec",
++		.of_match_table = ac200_codec_match,
++	},
++	.probe = ac200_codec_probe,
++	.remove = ac200_codec_remove,
++};
++module_platform_driver(ac200_codec_driver);
++
++MODULE_DESCRIPTION("X-Powers AC200 Codec Driver");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@gmail.com>");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-FB_TFT-ST7796S-driver.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-FB_TFT-ST7796S-driver.patch
new file mode 100644
index 000000000000..0297d816e110
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-FB_TFT-ST7796S-driver.patch
@@ -0,0 +1,154 @@
+From 8e9dc6b15f203a0dc6066b32326342984a6a5cb7 Mon Sep 17 00:00:00 2001
+From: Alan <Alan>
+Date: Sat, 20 May 2023 14:33:52 +0800
+Subject: Add: FB_TFT ST7796S driver
+
+---
+ drivers/staging/fbtft/Kconfig      |  10 +++
+ drivers/staging/fbtft/Makefile     |   1 +
+ drivers/staging/fbtft/fb_st7796s.c | 100 +++++++++++++++++++++++++++++
+ 3 files changed, 111 insertions(+)
+ create mode 100644 drivers/staging/fbtft/fb_st7796s.c
+
+diff --git a/drivers/staging/fbtft/Kconfig b/drivers/staging/fbtft/Kconfig
+index 77ab44362f16..107065985eb4 100644
+--- a/drivers/staging/fbtft/Kconfig
++++ b/drivers/staging/fbtft/Kconfig
+@@ -168,6 +168,16 @@ config FB_TFT_ST7789V
+ 
+ 	  Say Y if you have such a display that utilizes this controller.
+ 
++config FB_TFT_ST7796S
++	tristate "FB driver for the ST7796S LCD Controller"
++	depends on FB_TFT
++	help
++	  This enables generic framebuffer support for the Sitronix ST7796S
++	  display controller. The controller is intended for small color
++	  displays with a resolution of up to 480x320 pixels.
++
++	  Say Y if you have such a display that utilizes this controller.
++
+ config FB_TFT_TINYLCD
+ 	tristate "FB driver for tinylcd.com display"
+ 	depends on FB_TFT
+diff --git a/drivers/staging/fbtft/Makefile b/drivers/staging/fbtft/Makefile
+index e9cdf0f0a7da..7b2098b8a1bd 100644
+--- a/drivers/staging/fbtft/Makefile
++++ b/drivers/staging/fbtft/Makefile
+@@ -31,6 +31,7 @@ obj-$(CONFIG_FB_TFT_SSD1331)     += fb_ssd1331.o
+ obj-$(CONFIG_FB_TFT_SSD1351)     += fb_ssd1351.o
+ obj-$(CONFIG_FB_TFT_ST7735R)     += fb_st7735r.o
+ obj-$(CONFIG_FB_TFT_ST7789V)     += fb_st7789v.o
++obj-$(CONFIG_FB_TFT_ST7796S)     += fb_st7796s.o
+ obj-$(CONFIG_FB_TFT_TINYLCD)     += fb_tinylcd.o
+ obj-$(CONFIG_FB_TFT_TLS8204)     += fb_tls8204.o
+ obj-$(CONFIG_FB_TFT_UC1611)      += fb_uc1611.o
+diff --git a/drivers/staging/fbtft/fb_st7796s.c b/drivers/staging/fbtft/fb_st7796s.c
+new file mode 100644
+index 000000000000..cad489cef595
+--- /dev/null
++++ b/drivers/staging/fbtft/fb_st7796s.c
+@@ -0,0 +1,100 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * FB driver for the ST7796S LCD Controller
++ *
++ * Copyright (c) 2023 Alan Ma
++ * Copyright (c) 2014 Petr Olivka
++ * Copyright (c) 2013 Noralf Tronnes
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <video/mipi_display.h>
++
++#include "fbtft.h"
++
++#define DRVNAME	"fb_st7796s"
++#define WIDTH		480
++#define HEIGHT		320
++
++static const s16 default_init_sequence[] = {
++	-1, 0xC0, 0x0C, 0x02,
++	-1, 0xC1, 0x44,
++	-1, 0xC5, 0x00, 0x16, 0x80,
++	-1, 0x36, 0x28,
++	/* Interface Mode Control */
++	-1, 0x3A, 0x55,
++	-1, 0XB0, 0x00,
++	/* Frame rate 70HZ */
++	-1, 0xB1, 0xB0,
++	-1, 0xB4, 0x02,
++	/* RGB/MCU Interface Control */
++	-1, 0xB6, 0x02, 0x02,
++	-1, 0xE9, 0x00,
++	-1, 0XF7, 0xA9, 0x51, 0x2C, 0x82,
++	/* SLP_OUT - Sleep out */
++	-1, MIPI_DCS_EXIT_SLEEP_MODE,
++	-2, 50,
++	/* DISP_ON */
++	-1, MIPI_DCS_SET_DISPLAY_ON,
++	-3
++};
++
++static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
++{
++	write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
++		  xs >> 8, xs & 0xff, xe >> 8, xe & 0xff);
++
++	write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
++		  ys >> 8, ys & 0xff, ye >> 8, ye & 0xff);
++
++	write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
++}
++
++static int set_var(struct fbtft_par *par)
++{
++	switch (par->info->var.rotate) {
++	case 270:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0x80 | (par->bgr << 3));
++		break;
++	case 180:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0xE0 | (par->bgr << 3));
++		break;
++	case 90:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0x40 | (par->bgr << 3));
++		break;
++	default:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0x20 | (par->bgr << 3));
++		break;
++	}
++
++	return 0;
++}
++
++static struct fbtft_display display = {
++	.regwidth = 8,
++	.width = WIDTH,
++	.height = HEIGHT,
++	.init_sequence = default_init_sequence,
++	.fbtftops = {
++		.set_addr_win = set_addr_win,
++		.set_var = set_var,
++	},
++};
++
++FBTFT_REGISTER_DRIVER(DRVNAME, "sitronix,st7796s", &display);
++
++MODULE_ALIAS("spi:" DRVNAME);
++MODULE_ALIAS("platform:" DRVNAME);
++MODULE_ALIAS("spi:st7796s");
++MODULE_ALIAS("platform:st7796s");
++
++MODULE_DESCRIPTION("FB driver for the ST7796S LCD Controller");
++MODULE_AUTHOR("Alan Ma");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch
new file mode 100644
index 000000000000..0984db690c84
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch
@@ -0,0 +1,1551 @@
+From 9d110a13e2fe9c4a020985b3534f2a5be67dacbd Mon Sep 17 00:00:00 2001
+From: afaulkner420 <afaulkner420@gmail.com>
+Date: Fri, 25 Mar 2022 19:28:00 +0000
+Subject: Add dump_reg and sunxi-sysinfo drivers
+
+---
+ drivers/char/Kconfig                       |   2 +
+ drivers/char/Makefile                      |   2 +
+ drivers/char/dump_reg/Kconfig              |  21 +
+ drivers/char/dump_reg/Makefile             |   2 +
+ drivers/char/dump_reg/dump_reg.c           | 888 +++++++++++++++++++++
+ drivers/char/dump_reg/dump_reg.h           | 132 +++
+ drivers/char/dump_reg/dump_reg_misc.c      | 209 +++++
+ drivers/char/sunxi-sysinfo/Kconfig         |  10 +
+ drivers/char/sunxi-sysinfo/Makefile        |   5 +
+ drivers/char/sunxi-sysinfo/sunxi-sysinfo.c | 177 ++++
+ 10 files changed, 1448 insertions(+)
+ create mode 100644 drivers/char/dump_reg/Kconfig
+ create mode 100644 drivers/char/dump_reg/Makefile
+ create mode 100644 drivers/char/dump_reg/dump_reg.c
+ create mode 100644 drivers/char/dump_reg/dump_reg.h
+ create mode 100644 drivers/char/dump_reg/dump_reg_misc.c
+ create mode 100644 drivers/char/sunxi-sysinfo/Kconfig
+ create mode 100644 drivers/char/sunxi-sysinfo/Makefile
+ create mode 100644 drivers/char/sunxi-sysinfo/sunxi-sysinfo.c
+
+diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
+index 625af75833fc..b26c72ad100c 100644
+--- a/drivers/char/Kconfig
++++ b/drivers/char/Kconfig
+@@ -133,6 +133,8 @@ config POWERNV_OP_PANEL
+ 	  If unsure, say M here to build it as a module called powernv-op-panel.
+ 
+ source "drivers/char/ipmi/Kconfig"
++source "drivers/char/sunxi-sysinfo/Kconfig"
++source "drivers/char/dump_reg/Kconfig"
+ 
+ config DS1620
+ 	tristate "NetWinder thermometer support"
+diff --git a/drivers/char/Makefile b/drivers/char/Makefile
+index c5f532e412f1..8155bdcb3703 100644
+--- a/drivers/char/Makefile
++++ b/drivers/char/Makefile
+@@ -10,6 +10,7 @@ obj-$(CONFIG_ATARI_DSP56K)	+= dsp56k.o
+ obj-$(CONFIG_VIRTIO_CONSOLE)	+= virtio_console.o
+ obj-$(CONFIG_UV_MMTIMER)	+= uv_mmtimer.o
+ obj-$(CONFIG_IBM_BSR)		+= bsr.o
++obj-$(CONFIG_ARCH_SUNXI)        += sunxi-sysinfo/
+ 
+ obj-$(CONFIG_PRINTER)		+= lp.o
+ 
+@@ -43,3 +44,4 @@ obj-$(CONFIG_PS3_FLASH)		+= ps3flash.o
+ obj-$(CONFIG_XILLYBUS_CLASS)	+= xillybus/
+ obj-$(CONFIG_POWERNV_OP_PANEL)	+= powernv-op-panel.o
+ obj-$(CONFIG_ADI)		+= adi.o
++obj-$(CONFIG_DUMP_REG)          += dump_reg/
+diff --git a/drivers/char/dump_reg/Kconfig b/drivers/char/dump_reg/Kconfig
+new file mode 100644
+index 000000000000..dbf24c59fd40
+--- /dev/null
++++ b/drivers/char/dump_reg/Kconfig
+@@ -0,0 +1,21 @@
++#
++# dump reg config.
++#
++
++config DUMP_REG
++	tristate "dump reg driver for sunxi platform"
++	default y
++	help
++	  Say y here if you want to support dump regs module.
++	  The dump regs module is used to dump regs of any devices
++	  if you want it, When in doubt, say "Y".
++
++config DUMP_REG_MISC
++	tristate "dump reg misc driver"
++	depends on DUMP_REG
++	default y
++	help
++	  Add misc driver support, you can use dump regs function
++	  via ("/sys/class/...") sysfs interface.
++	  When in doubt, say "Y".
++
+diff --git a/drivers/char/dump_reg/Makefile b/drivers/char/dump_reg/Makefile
+new file mode 100644
+index 000000000000..e953f413b128
+--- /dev/null
++++ b/drivers/char/dump_reg/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_DUMP_REG) += dump_reg.o
++obj-$(CONFIG_DUMP_REG_MISC) += dump_reg_misc.o
+diff --git a/drivers/char/dump_reg/dump_reg.c b/drivers/char/dump_reg/dump_reg.c
+new file mode 100644
+index 000000000000..a839666c50a5
+--- /dev/null
++++ b/drivers/char/dump_reg/dump_reg.c
+@@ -0,0 +1,888 @@
++/*
++ * dump registers sysfs driver
++ *
++ * Copyright(c) 2015-2018 Allwinnertech Co., Ltd.
++ *      http://www.allwinnertech.com
++ *
++ * Author: Liugang <liugang@allwinnertech.com>
++ *         Xiafeng <xiafeng@allwinnertech.com>
++ *         Martin <wuyan@allwinnertech.com>
++ *         Lewis  <liuyu@allwinnertech.com>
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/kdev_t.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/miscdevice.h>
++#include <linux/seq_file.h>
++#include <linux/platform_device.h>
++#include <linux/sysfs.h>
++#include <linux/mod_devicetable.h>
++#include "dump_reg.h"
++
++/* the register and vaule to be test by dump_reg */
++static u32 test_addr;
++static u32 test_size;
++static struct class *dump_class;
++
++/* Access in byte mode ? 1: byte-mode, 0: word-mode */
++static unsigned int rw_byte_mode;
++
++/* for dump_reg class */
++static struct dump_addr dump_para;
++static struct write_group *wt_group;
++static struct compare_group *cmp_group;
++
++static u32 _read(void __iomem *vaddr)
++{
++	if (rw_byte_mode)
++		return (u32)readb(vaddr);
++	else
++		return readl(vaddr);
++}
++
++static void _write(u32 val, void __iomem *vaddr)
++{
++	if (rw_byte_mode)
++		writeb((u8)val, vaddr);
++	else
++		writel(val, vaddr);
++}
++
++static void __iomem *_io_remap(unsigned long paddr, size_t size)
++{
++	return ioremap(paddr, size);
++}
++
++static void _io_unmap(void __iomem *vaddr)
++{
++	iounmap(vaddr);
++}
++
++static void __iomem *_mem_remap(unsigned long paddr, size_t size)
++{
++	return (void __iomem *)phys_to_virt(paddr);
++}
++
++/*
++ * Convert a physical address (which is already mapped) to virtual address
++ */
++static void __iomem *_get_vaddr(struct dump_addr *dump_addr, unsigned long uaddr)
++{
++	unsigned long offset = uaddr - dump_addr->uaddr_start;
++	return (void __iomem *)(dump_addr->vaddr_start + offset);
++}
++
++const struct dump_struct dump_table[] = {
++	{
++		.addr_start = SUNXI_IO_PHYS_START,
++		.addr_end   = SUNXI_IO_PHYS_END,
++		.remap = _io_remap,
++		.unmap = _io_unmap,
++		.get_vaddr = _get_vaddr,
++		.read  = _read,
++		.write = _write,
++	},
++	{
++		.addr_start = SUNXI_PLAT_PHYS_START,
++		.addr_end   = SUNXI_PLAT_PHYS_END,
++		.remap = _mem_remap,
++		.unmap = NULL,
++		.get_vaddr = _get_vaddr,
++		.read  = _read,
++		.write = _write,
++	},
++#if defined(SUNXI_IOMEM_START)
++	{
++		.addr_start = SUNXI_IOMEM_START,
++		.addr_end   = SUNXI_IOMEM_END,
++		.remap = NULL,  /* .remap = NULL: uaddr is a virtual address */
++		.unmap = NULL,
++		.get_vaddr = _get_vaddr,
++		.read  = _read,
++		.write = _write,
++	},
++#endif
++	{
++		.addr_start = SUNXI_MEM_PHYS_START,
++		.addr_end   = SUNXI_MEM_PHYS_END,
++		.remap = NULL,  /* .remap = NULL: uaddr is a virtual address */
++		.unmap = NULL,
++		.get_vaddr = _get_vaddr,
++		.read  = _read,
++		.write = _write,
++	},
++};
++EXPORT_SYMBOL(dump_table);
++
++/**
++ * __addr_valid - check if @uaddr is valid.
++ * @uaddr: addr to judge.
++ *
++ * return index if @addr is valid, -ENXIO if not.
++ */
++int __addr_valid(unsigned long uaddr)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dump_table); i++)
++		if (uaddr >= dump_table[i].addr_start &&
++		    uaddr <= dump_table[i].addr_end)
++			return i;
++	return -ENXIO;
++}
++EXPORT_SYMBOL(__addr_valid);
++
++/**
++ * __dump_regs_ex - dump a range of registers' value, copy to buf.
++ * @dump_addr: start and end address of registers.
++ * @buf: store the dump info.
++ * @buf_size: buf size
++ *
++ * return bytes written to buf, <=0 indicate err
++ */
++ssize_t __dump_regs_ex(struct dump_addr *dump_addr, char *buf, ssize_t buf_size)
++{
++	int index;
++	ssize_t cnt = 0;
++	unsigned long uaddr;
++	unsigned long remap_size;
++	const struct dump_struct *dump;
++
++	/* Make the address 4-bytes aligned */
++	dump_addr->uaddr_start &= (~0x3UL);
++	dump_addr->uaddr_end &= (~0x3UL);
++	remap_size = dump_addr->uaddr_end - dump_addr->uaddr_start + 4;
++
++	index = __addr_valid(dump_addr->uaddr_start);
++	if ((index < 0) || (index != __addr_valid(dump_addr->uaddr_end)) ||
++	    (buf == NULL)) {
++		pr_err("%s(): Invalid para: index=%d, start=0x%lx, end=0x%lx, buf=0x%p\n",
++		       __func__, index, dump_addr->uaddr_start, dump_addr->uaddr_end, buf);
++		return -EIO;
++	}
++
++	dump = &dump_table[index];
++	if (dump->remap) {
++		dump_addr->vaddr_start = dump->remap(dump_addr->uaddr_start, remap_size);
++		if (!dump_addr->vaddr_start) {
++			pr_err("%s(): remap failed\n", __func__);
++			return -EIO;
++		}
++	} else  /* if (dump->remap = NULL), then treat uaddr as a virtual address */
++		dump_addr->vaddr_start = (void __iomem *)dump_addr->uaddr_start;
++
++	if (dump_addr->uaddr_start == dump_addr->uaddr_end) {
++		cnt = sprintf(buf, "0x%08x\n", dump->read(dump_addr->vaddr_start));
++		goto out;
++	}
++
++	for (uaddr = (dump_addr->uaddr_start & ~0x0F); uaddr <= dump_addr->uaddr_end;
++	     uaddr += 4) {
++		if (!(uaddr & 0x0F))
++			cnt += snprintf(buf + cnt, buf_size - cnt,
++				     "\n" PRINT_ADDR_FMT ":", uaddr);
++
++		if (cnt >= buf_size) {
++			pr_warn("Range too large, strings buffer overflow\n");
++			cnt = buf_size;
++			goto out;
++		}
++
++		if (uaddr < dump_addr->uaddr_start)  /* Don't show unused uaddr */
++			/* "0x12345678 ", 11 space */
++			cnt += snprintf(buf + cnt, buf_size - cnt, "           ");
++		else
++			cnt += snprintf(buf + cnt, buf_size - cnt, " 0x%08x",
++				dump->read(dump->get_vaddr(dump_addr, uaddr)));
++	}
++	cnt += snprintf(buf + cnt, buf_size - cnt, "\n");
++
++	pr_debug("%s(): start=0x%lx, end=0x%lx, return=%zd\n", __func__,
++		 dump_addr->uaddr_start, dump_addr->uaddr_end, cnt);
++
++out:
++	if (dump->unmap)
++		dump->unmap(dump_addr->vaddr_start);
++
++	return cnt;
++}
++EXPORT_SYMBOL(__dump_regs_ex);
++
++/**
++ * __parse_dump_str - parse the input string for dump attri.
++ * @buf: the input string, eg: "0x01c20000,0x01c20300".
++ * @size: buf size.
++ * @start: store the start reg's addr parsed from buf, eg 0x01c20000.
++ * @end: store the end reg's addr parsed from buf, eg 0x01c20300.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int __parse_dump_str(const char *buf, size_t size,
++			    unsigned long *start, unsigned long *end)
++{
++	char *ptr = NULL;
++	char *ptr2 = (char *)buf;
++	int ret = 0, times = 0;
++
++	/* Support single address mode, some time it haven't ',' */
++next:
++	/*
++	 * Default dump only one register(*start =*end).
++	 * If ptr is not NULL, we will cover the default value of end.
++	 */
++	if (times == 1)
++		*start = *end;
++
++	if (!ptr2 || (ptr2 - buf) >= size)
++		goto out;
++
++	ptr = ptr2;
++	ptr2 = strnchr(ptr, size - (ptr - buf), ',');
++	if (ptr2) {
++		*ptr2 = '\0';
++		ptr2++;
++	}
++
++	ptr = strim(ptr);
++	if (!strlen(ptr))
++		goto next;
++
++	ret = kstrtoul(ptr, 16, end);
++	if (!ret) {
++		times++;
++		goto next;
++	} else
++		pr_warn("String syntax errors: \"%s\"\n", ptr);
++
++out:
++	return ret;
++}
++EXPORT_SYMBOL(__parse_dump_str);
++
++/**
++ * __write_show - dump a register's value, copy to buf.
++ * @pgroup: the addresses to read.
++ * @buf: store the dump info.
++ *
++ * return bytes written to buf, <=0 indicate err.
++ */
++ssize_t __write_show(struct write_group *pgroup, char *buf, ssize_t len)
++{
++#define WR_DATA_FMT PRINT_ADDR_FMT"  0x%08x  %s"
++
++	int i = 0;
++	ssize_t cnt = 0;
++	unsigned long reg = 0;
++	u32 val;
++	u8 rval_buf[16];
++	struct dump_addr dump_addr;
++
++	if (!pgroup) {
++		pr_err("%s,%d err, pgroup is NULL!\n", __func__, __LINE__);
++		goto end;
++	}
++
++	cnt += snprintf(buf, len - cnt, WR_PRINT_FMT);
++	if (cnt > len) {
++		cnt = -EINVAL;
++		goto end;
++	}
++
++	for (i = 0; i < pgroup->num; i++) {
++		reg = pgroup->pitem[i].reg_addr;
++		val = pgroup->pitem[i].val;
++		dump_addr.uaddr_start = reg;
++		dump_addr.uaddr_end = reg;
++		if (__dump_regs_ex(&dump_addr, rval_buf, sizeof(rval_buf)) < 0)
++			return -EINVAL;
++
++		cnt +=
++		    snprintf(buf + cnt, len - cnt, WR_DATA_FMT, reg, val,
++			     rval_buf);
++		if (cnt > len) {
++			cnt = len;
++			goto end;
++		}
++	}
++
++end:
++	return cnt;
++}
++EXPORT_SYMBOL(__write_show);
++
++/**
++ * __parse_write_str - parse the input string for write attri.
++ * @str: string to be parsed, eg: "0x01c20818 0x55555555".
++ * @reg_addr: store the reg address. eg: 0x01c20818.
++ * @val: store the expect value. eg: 0x55555555.
++ *
++ * return 0 if success, otherwise failed.
++ */
++static int __parse_write_str(char *str, unsigned long *reg_addr, u32 *val)
++{
++	char *ptr = str;
++	char *tstr = NULL;
++	int ret = 0;
++
++	/*
++	 * Skip the leading whitespace, find the true split symbol.
++	 * And it must be 'address value'.
++	 */
++	tstr = strim(str);
++	ptr = strchr(tstr, ' ');
++	if (!ptr)
++		return -EINVAL;
++
++	/*
++	 * Replaced split symbol with a %NUL-terminator temporary.
++	 * Will be fixed at end.
++	 */
++	*ptr = '\0';
++	ret = kstrtoul(tstr, 16, reg_addr);
++	if (ret)
++		goto out;
++
++	ret = kstrtou32(skip_spaces(ptr + 1), 16, val);
++
++out:
++	return ret;
++}
++
++/**
++ * __write_item_init - init for write attri. parse input string,
++ *                     and construct write struct.
++ * @ppgroup: store the struct allocated, the struct contains items parsed from
++ *           input buf.
++ * @buf: input string, eg: "0x01c20800 0x00000031,0x01c20818 0x55555555,...".
++ * @size: buf size.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int __write_item_init(struct write_group **ppgroup, const char *buf,
++			     size_t size)
++{
++	char *ptr, *ptr2;
++	unsigned long addr = 0;
++	u32 val;
++	struct write_group *pgroup;
++
++	/* alloc item buffer */
++	pgroup = kmalloc(sizeof(struct write_group), GFP_KERNEL);
++	if (!pgroup)
++		return -ENOMEM;
++
++	pgroup->pitem = kmalloc(sizeof(struct write_item) * MAX_WRITE_ITEM,
++				GFP_KERNEL);
++	if (!pgroup->pitem) {
++		kfree(pgroup);
++		return -ENOMEM;
++	}
++
++	pgroup->num = 0;
++	ptr = (char *)buf;
++	do {
++		ptr2 = strchr(ptr, ',');
++		if (ptr2)
++			*ptr2 = '\0';
++
++		if (!__parse_write_str(ptr, &addr, &val)) {
++			pgroup->pitem[pgroup->num].reg_addr = addr;
++			pgroup->pitem[pgroup->num].val = val;
++			pgroup->num++;
++		} else
++			pr_err("%s: Failed to parse string: %s\n", __func__,
++			       ptr);
++
++		if (!ptr2)
++			break;
++
++		ptr = ptr2 + 1;
++		*ptr2 = ',';
++
++	} while (pgroup->num <= MAX_WRITE_ITEM);
++
++	/* free buffer if no valid item */
++	if (pgroup->num == 0) {
++		kfree(pgroup->pitem);
++		kfree(pgroup);
++		return -EINVAL;
++	}
++
++	*ppgroup = pgroup;
++	return 0;
++}
++EXPORT_SYMBOL(__write_item_init);
++
++/**
++ * __write_item_deinit - reled_addrse memory that cred_addrted by
++ *                       __write_item_init.
++ * @pgroup: the write struct allocated in __write_item_init.
++ */
++void __write_item_deinit(struct write_group *pgroup)
++{
++	if (pgroup != NULL) {
++		if (pgroup->pitem != NULL)
++			kfree(pgroup->pitem);
++		kfree(pgroup);
++	}
++}
++EXPORT_SYMBOL(__write_item_deinit);
++
++/**
++ * __compare_regs_ex - dump a range of registers' value, copy to buf.
++ * @pgroup: addresses of registers.
++ * @buf: store the dump info.
++ *
++ * return bytes written to buf, <= 0 indicate err.
++ */
++ssize_t __compare_regs_ex(struct compare_group *pgroup, char *buf,
++				 ssize_t len)
++{
++#define CMP_DATAO_FMT PRINT_ADDR_FMT"  0x%08x  0x%08x  0x%08x  OK\n"
++#define CMP_DATAE_FMT PRINT_ADDR_FMT"  0x%08x  0x%08x  0x%08x  ERR\n"
++
++	int i;
++	ssize_t cnt = 0;
++	unsigned long reg;
++	u32 expect, actual, mask;
++	u8 actualb[16];
++	struct dump_addr dump_addr;
++
++	if (!pgroup) {
++		pr_err("%s,%d err, pgroup is NULL!\n", __func__, __LINE__);
++		goto end;
++	}
++
++	cnt += snprintf(buf, len - cnt, CMP_PRINT_FMT);
++	if (cnt > len) {
++		cnt = -EINVAL;
++		goto end;
++	}
++
++	for (i = 0; i < pgroup->num; i++) {
++		reg = pgroup->pitem[i].reg_addr;
++		expect = pgroup->pitem[i].val_expect;
++		dump_addr.uaddr_start = reg;
++		dump_addr.uaddr_end = reg;
++		if (__dump_regs_ex(&dump_addr, actualb, sizeof(actualb)) < 0)
++			return -EINVAL;
++
++		if (kstrtou32(actualb, 16, &actual))
++			return -EINVAL;
++
++		mask = pgroup->pitem[i].val_mask;
++		if ((actual & mask) == (expect & mask))
++			cnt +=
++			    snprintf(buf + cnt, len - cnt, CMP_DATAO_FMT, reg,
++				     expect, actual, mask);
++		else
++			cnt +=
++			    snprintf(buf + cnt, len - cnt, CMP_DATAE_FMT, reg,
++				     expect, actual, mask);
++		if (cnt > len) {
++			cnt = -EINVAL;
++			goto end;
++		}
++	}
++
++end:
++	return cnt;
++}
++EXPORT_SYMBOL(__compare_regs_ex);
++
++/**
++ * __parse_compare_str - parse the input string for compare attri.
++ * @str: string to be parsed, eg: "0x01c20000 0x80000011 0x00000011".
++ * @reg_addr: store the reg address. eg: 0x01c20000.
++ * @val_expect: store the expect value. eg: 0x80000011.
++ * @val_mask: store the mask value. eg: 0x00000011.
++ *
++ * return 0 if success, otherwise failed.
++ */
++static int __parse_compare_str(char *str, unsigned long *reg_addr,
++			       u32 *val_expect, u32 *val_mask)
++{
++	unsigned long result_addr[3] = { 0 };
++	char *ptr = str;
++	char *ptr2 = NULL;
++	int i, ret = 0;
++
++	for (i = 0; i < ARRAY_SIZE(result_addr); i++) {
++		ptr = skip_spaces(ptr);
++		ptr2 = strchr(ptr, ' ');
++		if (ptr2)
++			*ptr2 = '\0';
++
++		ret = kstrtoul(ptr, 16, &result_addr[i]);
++		if (!ptr2)
++			break;
++
++		*ptr2 = ' ';
++
++		if (ret)
++			break;
++
++		ptr = ptr2 + 1;
++	}
++
++	*reg_addr = result_addr[0];
++	*val_expect = (u32) result_addr[1];
++	*val_mask = (u32) result_addr[2];
++
++	return ret;
++}
++
++/**
++ * __compare_item_init - init for compare attri. parse input string,
++ *                       and construct compare struct.
++ * @ppgroup: store the struct allocated, the struct contains items parsed from
++ *           input buf.
++ * @buf: input string,
++ *  eg: "0x01c20000 0x80000011 0x00000011,0x01c20004 0x0000c0a4 0x0000c0a0,...".
++ * @size: buf size.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int __compare_item_init(struct compare_group **ppgroup,
++			       const char *buf, size_t size)
++{
++	char *ptr, *ptr2;
++	unsigned long addr = 0;
++	u32 val_expect = 0, val_mask = 0;
++	struct compare_group *pgroup = NULL;
++
++	/* alloc item buffer */
++	pgroup = kmalloc(sizeof(struct compare_group), GFP_KERNEL);
++	if (pgroup == NULL)
++		return -EINVAL;
++
++	pgroup->pitem = kmalloc(sizeof(struct compare_item) * MAX_COMPARE_ITEM,
++				GFP_KERNEL);
++	if (pgroup->pitem == NULL) {
++		kfree(pgroup);
++		return -EINVAL;
++	}
++
++	pgroup->num = 0;
++
++	/* get item from buf */
++	ptr = (char *)buf;
++	do {
++		ptr2 = strchr(ptr, ',');
++		if (ptr2)
++			*ptr2 = '\0';
++
++		if (!__parse_compare_str(ptr, &addr, &val_expect, &val_mask)) {
++			pgroup->pitem[pgroup->num].reg_addr = addr;
++			pgroup->pitem[pgroup->num].val_expect = val_expect;
++			pgroup->pitem[pgroup->num].val_mask = val_mask;
++			pgroup->num++;
++		} else
++			pr_err("%s: Failed to parse string: %s\n", __func__,
++			       ptr);
++
++		if (!ptr2)
++			break;
++
++		*ptr2 = ',';
++		ptr = ptr2 + 1;
++
++	} while (pgroup->num <= MAX_COMPARE_ITEM);
++
++	/* free buffer if no valid item */
++	if (pgroup->num == 0) {
++		kfree(pgroup->pitem);
++		kfree(pgroup);
++		return -EINVAL;
++	}
++	*ppgroup = pgroup;
++
++	return 0;
++}
++EXPORT_SYMBOL(__compare_item_init);
++
++/**
++ * __compare_item_deinit - reled_addrse memory that cred_addrted by
++ *                         __compare_item_init.
++ * @pgroup: the compare struct allocated in __compare_item_init.
++ */
++void __compare_item_deinit(struct compare_group *pgroup)
++{
++	if (pgroup) {
++		kfree(pgroup->pitem);
++		kfree(pgroup);
++	}
++}
++EXPORT_SYMBOL(__compare_item_deinit);
++
++/**
++ * dump_show - show func of dump attribute.
++ * @dev: class ptr.
++ * @attr: attribute ptr.
++ * @buf: the input buf which contain the start and end reg.
++ *       eg: "0x01c20000,0x01c20100\n".
++ *
++ * return size written to the buf, otherwise failed.
++ */
++static ssize_t
++dump_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	return __dump_regs_ex(&dump_para, buf, PAGE_SIZE);
++}
++
++static ssize_t
++dump_store(const struct class *class, const struct class_attribute *attr,
++	   const char *buf, size_t count)
++{
++	int index;
++	unsigned long start_reg = 0;
++	unsigned long end_reg = 0;
++
++	if (__parse_dump_str(buf, count, &start_reg, &end_reg)) {
++		pr_err("%s,%d err, invalid para!\n", __func__, __LINE__);
++		goto err;
++	}
++
++	index = __addr_valid(start_reg);
++	if ((index < 0) || (index != __addr_valid(end_reg))) {
++		pr_err("%s,%d err, invalid para!\n", __func__, __LINE__);
++		goto err;
++	}
++
++	dump_para.uaddr_start = start_reg;
++	dump_para.uaddr_end = end_reg;
++	pr_debug("%s,%d, start_reg:" PRINT_ADDR_FMT ", end_reg:" PRINT_ADDR_FMT
++		 "\n", __func__, __LINE__, start_reg, end_reg);
++
++	return count;
++
++err:
++	dump_para.uaddr_start = 0;
++	dump_para.uaddr_end = 0;
++
++	return -EINVAL;
++}
++
++static ssize_t
++write_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	/* display write result */
++	return __write_show(wt_group, buf, PAGE_SIZE);
++}
++
++static ssize_t
++write_store(const struct class *class, const struct class_attribute *attr,
++	    const char *buf, size_t count)
++{
++	int i;
++	int index;
++	unsigned long reg;
++	u32 val;
++	const struct dump_struct *dump;
++	struct dump_addr dump_addr;
++
++	/* free if not NULL */
++	if (wt_group) {
++		__write_item_deinit(wt_group);
++		wt_group = NULL;
++	}
++
++	/* parse input buf for items that will be dumped */
++	if (__write_item_init(&wt_group, buf, count) < 0)
++		return -EINVAL;
++
++	/**
++	 * write reg
++	 * it is better if the regs been remaped and unmaped only once,
++	 * but we map everytime for the range between min and max address
++	 * maybe too large.
++	 */
++	for (i = 0; i < wt_group->num; i++) {
++		reg = wt_group->pitem[i].reg_addr;
++		dump_addr.uaddr_start = reg;
++		val = wt_group->pitem[i].val;
++		index = __addr_valid(reg);
++		dump = &dump_table[index];
++		if (dump->remap)
++			dump_addr.vaddr_start = dump->remap(reg, 4);
++		else
++			dump_addr.vaddr_start = (void __iomem *)reg;
++		dump->write(val, dump->get_vaddr(&dump_addr, reg));
++		if (dump->unmap)
++			dump->unmap(dump_addr.vaddr_start);
++	}
++
++	return count;
++}
++
++static ssize_t
++compare_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	/* dump the items */
++	return __compare_regs_ex(cmp_group, buf, PAGE_SIZE);
++}
++
++static ssize_t
++compare_store(const struct class *class, const struct class_attribute *attr,
++	      const char *buf, size_t count)
++{
++	/* free if struct not null */
++	if (cmp_group) {
++		__compare_item_deinit(cmp_group);
++		cmp_group = NULL;
++	}
++
++	/* parse input buf for items that will be dumped */
++	if (__compare_item_init(&cmp_group, buf, count) < 0)
++		return -EINVAL;
++
++	return count;
++}
++
++static ssize_t
++rw_byte_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	return sprintf(buf, "read/write mode: %u(%s)\n", rw_byte_mode,
++		       rw_byte_mode ? "byte" : "word");
++}
++
++static ssize_t
++rw_byte_store(const struct class *class, const struct class_attribute *attr,
++	      const char *buf, size_t count)
++{
++	unsigned long value;
++	int ret;
++
++	ret = kstrtoul(buf, 10, &value);
++	if (!ret && (value > 1)) {
++		pr_err("%s,%d err, invalid para!\n", __func__, __LINE__);
++		goto out;
++	}
++	rw_byte_mode = value;
++out:
++	return count;
++}
++
++static ssize_t
++test_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	return sprintf(buf, "addr:0x%08x\nsize:0x%08x\n", test_addr, test_size);
++}
++
++static ssize_t
++help_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	const char *info =
++		"dump single register:          echo {addr} > dump; cat dump\n"
++		"dump multi  registers:         echo {start-addr},{end-addr} > dump; cat dump\n"
++		"write single register:         echo {addr} {val} > write; cat write\n"
++		"write multi  registers:        echo {addr1} {val1},{addr2} {val2},... > write; cat write\n"
++		"compare single register:       echo {addr} {expect-val} {mask} > compare; cat compare\n"
++		"compare multi  registers:      echo {addr1} {expect-val1} {mask1},{addr2} {expect-val2} {mask2},... > compare; cat compare\n"
++		"byte-access mode:              echo 1 > rw_byte\n"
++		"word-access mode (default):    echo 0 > rw_byte\n"
++		"show test address info:        cat test\n";
++	return sprintf(buf, info);
++}
++
++static struct class_attribute dump_class_attrs[] = {
++	__ATTR(dump,     S_IWUSR | S_IRUGO, dump_show,     dump_store),
++	__ATTR(write,    S_IWUSR | S_IRUGO, write_show,    write_store),
++	__ATTR(compare,  S_IWUSR | S_IRUGO, compare_show,  compare_store),
++	__ATTR(rw_byte,  S_IWUSR | S_IRUGO, rw_byte_show,  rw_byte_store),
++	__ATTR(test,     S_IRUGO,           test_show, NULL),
++	__ATTR(help,     S_IRUGO,           help_show, NULL),
++};
++
++static const struct of_device_id sunxi_dump_reg_match[] = {
++	{.compatible = "allwinner,sunxi-dump-reg", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, sunxi_dump_reg_match);
++
++static int sunxi_dump_reg_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	struct device *dev = &pdev->dev;
++
++	int err;
++	int i;
++
++	/* sys/class/sunxi_dump */
++	dump_class = class_create("sunxi_dump");
++	if (IS_ERR(dump_class)) {
++		pr_err("%s:%u class_create() failed\n", __func__, __LINE__);
++		return PTR_ERR(dump_class);
++	}
++
++	/* sys/class/sunxi_dump/xxx */
++	for (i = 0; i < ARRAY_SIZE(dump_class_attrs); i++) {
++		err = class_create_file(dump_class, &dump_class_attrs[i]);
++		if (err) {
++			pr_err("%s:%u class_create_file() failed. err=%d\n", __func__, __LINE__, err);
++			while (i--) {
++				class_remove_file(dump_class, &dump_class_attrs[i]);
++			}
++			class_destroy(dump_class);
++			dump_class = NULL;
++			return err;
++		}
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(dev, "Fail to get IORESOURCE_MEM \n");
++		goto error;
++	}
++
++	test_addr = res->start;
++	test_size = resource_size(res);
++
++	return 0;
++error:
++	dev_err(dev, "sunxi_dump_reg probe error\n");
++	return -1;
++}
++
++static int sunxi_dump_reg_remove(struct platform_device *pdev)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dump_class_attrs); i++) {
++		class_remove_file(dump_class, &dump_class_attrs[i]);
++	}
++
++	class_destroy(dump_class);
++	return 0;
++}
++
++static struct platform_driver sunxi_dump_reg_driver = {
++	.probe  = sunxi_dump_reg_probe,
++	.remove = sunxi_dump_reg_remove,
++	.driver = {
++		.name   = "dump_reg",
++		.owner  = THIS_MODULE,
++		.of_match_table = sunxi_dump_reg_match,
++	},
++};
++
++module_platform_driver(sunxi_dump_reg_driver);
++
++MODULE_ALIAS("dump reg driver");
++MODULE_ALIAS("platform:dump reg");
++MODULE_LICENSE("GPL v2");
++MODULE_VERSION("1.0.3");
++MODULE_AUTHOR("xiafeng <xiafeng@allwinnertech.com>");
++MODULE_AUTHOR("Martin <wuyan@allwinnertech.com>");
++MODULE_AUTHOR("liuyu <SWCliuyus@allwinnertech.com>");
++MODULE_DESCRIPTION("dump registers driver");
+diff --git a/drivers/char/dump_reg/dump_reg.h b/drivers/char/dump_reg/dump_reg.h
+new file mode 100644
+index 000000000000..85af5c96ed50
+--- /dev/null
++++ b/drivers/char/dump_reg/dump_reg.h
+@@ -0,0 +1,132 @@
++/*
++ * dump registers head file
++ *
++ * (C) Copyright 2015-2018
++ * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
++ * Liugang <liugang@reuuimllatech.com>
++ * Xiafeng <xiafeng@allwinnertech.com>
++ * Martin  <wuyan@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ */
++#ifndef _DUMP_REG_H_
++#define _DUMP_REG_H_
++
++/* BROM/SRAM/peripheral-registers space */
++#define SUNXI_IO_PHYS_START		(0x01000000UL)
++#define SUNXI_IO_PHYS_END		(SUNXI_IO_PHYS_START + SZ_128M + SZ_16M -1)
++
++/* DRAM space (Only map the first 1GB) */
++#define SUNXI_PLAT_PHYS_START		(0x40000000UL)
++#define SUNXI_PLAT_PHYS_END		(SUNXI_PLAT_PHYS_START + SZ_1G - 1)
++
++#if IS_ENABLED(CONFIG_ARM64)
++/* Virtual address space 1 */
++#define SUNXI_IOMEM_START		(0xffffff8000000000UL)
++#define SUNXI_IOMEM_END			(SUNXI_IOMEM_START + SZ_2G)
++/* Virtual address space 2 */
++#define SUNXI_MEM_PHYS_START		(0xffffffc000000000UL)
++#define SUNXI_MEM_PHYS_END		(SUNXI_MEM_PHYS_START + SZ_2G)
++/* Print format */
++#define PRINT_ADDR_FMT			"0x%016lx"
++#define CMP_PRINT_FMT                   "reg                 expect      actual      mask        result\n"
++#define WR_PRINT_FMT                    "reg                 to_write    after_write\n"
++#else
++/* Virtual address space 2 */
++#define SUNXI_MEM_PHYS_START		PAGE_OFFSET
++#define SUNXI_MEM_PHYS_END		(SUNXI_MEM_PHYS_START + SZ_1G - 1)
++/* Print format */
++#define PRINT_ADDR_FMT			"0x%08lx"
++#define CMP_PRINT_FMT                   "reg         expect      actual      mask        result\n"
++#define WR_PRINT_FMT                    "reg         to_write    after_write\n"
++#endif
++
++/* Item count */
++#define MAX_COMPARE_ITEM		64
++#define MAX_WRITE_ITEM			64
++
++struct dump_addr {
++	/* User specified address. Maybe physical or virtual address */
++	unsigned long uaddr_start;
++	unsigned long uaddr_end;
++	/* Virtual address */
++	void __iomem *vaddr_start;
++};
++
++struct dump_struct {
++	unsigned long addr_start;
++	unsigned long addr_end;
++	/* some registers' operate method maybe different */
++	void __iomem *(*remap)(unsigned long paddr, size_t size);
++	void (*unmap)(void __iomem *vaddr);
++	void __iomem *(*get_vaddr)(struct dump_addr *dump_addr, unsigned long uaddr);
++	 u32 (*read)(void __iomem *vaddr);
++	void (*write)(u32 val, void __iomem *vaddr);
++};
++
++/**
++ * compare_item - reg compare item struct
++ * @reg_addr:	reg address.
++ * @val_expect: expected value, provided by caller.
++ * @val_mask:   mask value, provided by caller. only mask bits will be compared.
++ */
++struct compare_item {
++	unsigned long reg_addr;
++	u32	val_expect;
++	u32	val_mask;
++};
++
++/**
++ * compare_group - reg compare group struct
++ * @num:	pitem element count. cannot exceed MAX_COMPARE_ITEM.
++ * @pitem:	items that will be compared, provided by caller.
++ */
++struct compare_group {
++	u32	num;
++	u32	reserve;
++	struct compare_item *pitem;
++};
++
++/**
++ * write_item - reg write item struct
++ * @reg_addr:	reg address.
++ * @val:	value to write
++ */
++struct write_item {
++	unsigned long reg_addr;
++	u32	val;
++	u32	reserve;
++};
++
++/**
++ * write_group - reg write group struct
++ * @num:	pitem element count. cannot exceed MAX_WRITE_ITEM.
++ * @pitem:	items that will be write, provided by caller.
++ */
++struct write_group {
++	u32	num;
++	u32	reserve;
++	struct write_item *pitem;
++};
++
++extern const struct dump_struct dump_table[4];
++
++int __addr_valid(unsigned long addr);
++ssize_t __dump_regs_ex(struct dump_addr *reg, char *buf, ssize_t len);
++int __parse_dump_str(const char *buf, size_t size,
++						unsigned long *start, unsigned long *end);
++ssize_t __write_show(struct write_group *pgroup, char *buf, ssize_t len);
++int  __write_item_init(struct write_group **ppgroup, const char *buf,
++						size_t size);
++void __write_item_deinit(struct write_group *pgroup);
++ssize_t __compare_regs_ex(struct compare_group *pgroup, char *buf,
++							ssize_t len);
++int  __compare_item_init(struct compare_group **ppgroup,
++						const char *buf, size_t size);
++void __compare_item_deinit(struct compare_group *pgroup);
++
++#endif /* _DUMP_REG_H_ */
+diff --git a/drivers/char/dump_reg/dump_reg_misc.c b/drivers/char/dump_reg/dump_reg_misc.c
+new file mode 100644
+index 000000000000..238ddd147533
+--- /dev/null
++++ b/drivers/char/dump_reg/dump_reg_misc.c
+@@ -0,0 +1,209 @@
++/*
++ * misc dump registers driver -
++ * User space application could use dump-reg functions through file operations
++ * (open/read/write/close) to the sysfs node created by this driver.
++ *
++ * Copyright(c) 2015-2018 Allwinnertech Co., Ltd.
++ *      http://www.allwinnertech.com
++ *
++ * Author: Liugang <liugang@allwinnertech.com>
++ *         Xiafeng <xiafeng@allwinnertech.com>
++ *         Martin  <wuyan@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/kdev_t.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/miscdevice.h>
++#include <linux/seq_file.h>
++#include "dump_reg.h"
++
++/* for dump_reg misc driver */
++static struct dump_addr misc_dump_para;
++static struct write_group *misc_wt_group;
++static struct compare_group *misc_cmp_group;
++
++static ssize_t
++misc_dump_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	return __dump_regs_ex(&misc_dump_para, buf, PAGE_SIZE);
++}
++
++static ssize_t
++misc_dump_store(struct device *dev, struct device_attribute *attr,
++		const char *buf, size_t size)
++{
++	int index;
++	unsigned long start_reg = 0;
++	unsigned long end_reg = 0;
++
++	if (__parse_dump_str(buf, size, &start_reg, &end_reg)) {
++		pr_err("%s,%d err, invalid para!\n", __func__, __LINE__);
++		goto err;
++	}
++
++	index = __addr_valid(start_reg);
++	if ((index < 0) || (index != __addr_valid(end_reg))) {
++		pr_err("%s,%d err, invalid para!\n", __func__, __LINE__);
++		goto err;
++	}
++
++	misc_dump_para.uaddr_start = start_reg;
++	misc_dump_para.uaddr_end = end_reg;
++	pr_debug("%s,%d, start_reg:" PRINT_ADDR_FMT ", end_reg:" PRINT_ADDR_FMT
++		 "\n", __func__, __LINE__, start_reg, end_reg);
++
++	return size;
++
++err:
++	misc_dump_para.uaddr_start = 0;
++	misc_dump_para.uaddr_end = 0;
++
++	return -EINVAL;
++}
++
++static ssize_t
++misc_write_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	/* display write result */
++	return __write_show(misc_wt_group, buf, PAGE_SIZE);
++}
++
++static ssize_t
++misc_write_store(struct device *dev, struct device_attribute *attr,
++		 const char *buf, size_t size)
++{
++	int i;
++	int index;
++	unsigned long reg;
++	u32 val;
++	const struct dump_struct *dump;
++	struct dump_addr dump_addr;
++
++	/* free if not NULL */
++	if (misc_wt_group) {
++		__write_item_deinit(misc_wt_group);
++		misc_wt_group = NULL;
++	}
++
++	/* parse input buf for items that will be dumped */
++	if (__write_item_init(&misc_wt_group, buf, size) < 0)
++		return -EINVAL;
++
++	/**
++	 * write reg
++	 * it is better if the regs been remaped and unmaped only once,
++	 * but we map everytime for the range between min and max address
++	 * maybe too large.
++	 */
++	for (i = 0; i < misc_wt_group->num; i++) {
++		reg = misc_wt_group->pitem[i].reg_addr;
++		dump_addr.uaddr_start = reg;
++		val = misc_wt_group->pitem[i].val;
++		index = __addr_valid(reg);
++		dump = &dump_table[index];
++		if (dump->remap)
++			dump_addr.vaddr_start = dump->remap(reg, 4);
++		else
++			dump_addr.vaddr_start = (void __iomem *)reg;
++		dump->write(val, dump->get_vaddr(&dump_addr, reg));
++		if (dump->unmap)
++			dump->unmap(dump_addr.vaddr_start);
++	}
++
++	return size;
++}
++
++static ssize_t
++misc_compare_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	/* dump the items */
++	return __compare_regs_ex(misc_cmp_group, buf, PAGE_SIZE);
++}
++
++static ssize_t
++misc_compare_store(struct device *dev, struct device_attribute *attr,
++		   const char *buf, size_t size)
++{
++	/* free if struct not null */
++	if (misc_cmp_group) {
++		__compare_item_deinit(misc_cmp_group);
++		misc_cmp_group = NULL;
++	}
++
++	/* parse input buf for items that will be dumped */
++	if (__compare_item_init(&misc_cmp_group, buf, size) < 0)
++		return -EINVAL;
++
++	return size;
++}
++
++static DEVICE_ATTR(dump, S_IWUSR | S_IRUGO, misc_dump_show, misc_dump_store);
++static DEVICE_ATTR(write, S_IWUSR | S_IRUGO, misc_write_show, misc_write_store);
++static DEVICE_ATTR(compare, S_IWUSR | S_IRUGO, misc_compare_show,
++		   misc_compare_store);
++
++static struct attribute *misc_attributes[] = {  /* files under '/sys/devices/virtual/misc/sunxi-reg/rw/' */
++	&dev_attr_dump.attr,
++	&dev_attr_write.attr,
++	&dev_attr_compare.attr,
++	NULL,
++};
++
++static struct attribute_group misc_attribute_group = {
++	.name = "rw",  /* directory: '/sys/devices/virtual/misc/sunxi-reg/rw/' */
++	.attrs = misc_attributes,
++};
++
++static struct miscdevice dump_reg_dev = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name = "sunxi-reg",  /* device node: '/dev/sunxi-reg' */
++};
++
++static int __init misc_dump_reg_init(void)
++{
++	int err;
++
++	pr_info("misc dump reg init\n");
++	err = misc_register(&dump_reg_dev);
++	if (err) {
++		pr_err("dump register driver as misc device error!\n");
++		goto exit;
++	}
++
++	err = sysfs_create_group(&dump_reg_dev.this_device->kobj,
++				 &misc_attribute_group);
++	if (err)
++		pr_err("dump register sysfs create group failed!\n");
++
++exit:
++	return err;
++}
++
++static void __exit misc_dump_reg_exit(void)
++{
++	pr_info("misc dump reg exit\n");
++
++	sysfs_remove_group(&(dump_reg_dev.this_device->kobj),
++			   &misc_attribute_group);
++	misc_deregister(&dump_reg_dev);
++}
++
++module_init(misc_dump_reg_init);
++module_exit(misc_dump_reg_exit);
++
++MODULE_ALIAS("misc dump reg driver");
++MODULE_LICENSE("GPL v2");
++MODULE_VERSION("1.0.1");
++MODULE_AUTHOR("xiafeng <xiafeng@allwinnertech.com>");
++MODULE_DESCRIPTION("misc dump registers driver");
+diff --git a/drivers/char/sunxi-sysinfo/Kconfig b/drivers/char/sunxi-sysinfo/Kconfig
+new file mode 100644
+index 000000000000..9b6e2f06d708
+--- /dev/null
++++ b/drivers/char/sunxi-sysinfo/Kconfig
+@@ -0,0 +1,10 @@
++#
++# sunxi system information driver.
++#
++
++config SUNXI_SYS_INFO
++	tristate "sunxi system info driver"
++	default y
++	help
++	  This driver is used for query system information.
++	  If you don't know whether need it, please select y.
+diff --git a/drivers/char/sunxi-sysinfo/Makefile b/drivers/char/sunxi-sysinfo/Makefile
+new file mode 100644
+index 000000000000..188696592114
+--- /dev/null
++++ b/drivers/char/sunxi-sysinfo/Makefile
+@@ -0,0 +1,5 @@
++#
++# Makefile for sunxi system information driver
++#
++
++obj-$(CONFIG_SUNXI_SYS_INFO) += sunxi-sysinfo.o
+diff --git a/drivers/char/sunxi-sysinfo/sunxi-sysinfo.c b/drivers/char/sunxi-sysinfo/sunxi-sysinfo.c
+new file mode 100644
+index 000000000000..a5b4e6c0b578
+--- /dev/null
++++ b/drivers/char/sunxi-sysinfo/sunxi-sysinfo.c
+@@ -0,0 +1,177 @@
++/*
++ * Based on drivers/char/sunxi-sysinfo/sunxi-sysinfo.c
++ *
++ * Copyright (C) 2015 Allwinnertech Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/printk.h>
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/vmalloc.h>
++#include <linux/uaccess.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <linux/compat.h>
++#include <linux/platform_device.h>
++#include <linux/of_platform.h>
++#include <linux/of.h>
++
++extern int sunxi_get_soc_chipid(unsigned char *chipid);
++extern int sunxi_get_serial(unsigned  char *serial);
++
++struct sunxi_info_quirks {
++	char * platform_name;
++};
++
++static const struct sunxi_info_quirks sun5i_h6_info_quirks = {
++	.platform_name  = "sun50i-h6",
++};
++
++static const struct sunxi_info_quirks sun5i_h616_info_quirks = {
++	.platform_name  = "sun50i-h616",
++};
++
++struct sunxi_info_quirks *quirks;
++
++static int soc_info_open(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static int soc_info_release(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static const struct file_operations soc_info_ops = {
++	.owner   = THIS_MODULE,
++	.open    = soc_info_open,
++	.release = soc_info_release,
++};
++
++struct miscdevice soc_info_device = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name  = "sunxi_soc_info",
++	.fops  = &soc_info_ops,
++};
++
++static ssize_t sys_info_show(const struct class *class,
++			     const struct class_attribute *attr, char *buf)
++{
++	int i;
++	int databuf[4] = {0};
++	char tmpbuf[129] = {0};
++	size_t size = 0;
++
++	/* platform */
++	size += sprintf(buf + size, "sunxi_platform    : %s\n", quirks->platform_name);
++
++	/* chipid */
++	sunxi_get_soc_chipid((u8 *)databuf);
++
++	for (i = 0; i < 4; i++)
++		sprintf(tmpbuf + i*8, "%08x", databuf[i]);
++	tmpbuf[128] = 0;
++	size += sprintf(buf + size, "sunxi_chipid      : %s\n", tmpbuf);
++
++	/* serial */
++	sunxi_get_serial((u8 *)databuf);
++	for (i = 0; i < 4; i++)
++		sprintf(tmpbuf + i*8, "%08x", databuf[i]);
++	tmpbuf[128] = 0;
++	size += sprintf(buf + size, "sunxi_serial      : %s\n", tmpbuf);
++
++	return size;
++}
++
++static struct class_attribute info_class_attrs[] = {
++	__ATTR(sys_info, 0644, sys_info_show, NULL),
++};
++
++static struct class info_class = {
++	.name           = "sunxi_info",
++};
++
++static const struct of_device_id sunxi_info_match[] = {
++        {
++		.compatible = "allwinner,sun50i-h6-sys-info",
++		.data = &sun5i_h6_info_quirks,
++        },
++        {
++		.compatible = "allwinner,sun50i-h616-sys-info",
++		.data = &sun5i_h616_info_quirks,
++        },
++        {}
++};
++
++static int sunxi_info_probe(struct platform_device *pdev)
++{
++	int i, ret = 0;
++
++	quirks = of_device_get_match_data(&pdev->dev);
++	if (quirks == NULL) {
++		dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
++		return -ENODEV;
++	}
++
++	ret = class_register(&info_class);
++	if (ret != 0)
++		return ret;
++
++	/* need some class specific sysfs attributes */
++	for (i = 0; i < ARRAY_SIZE(info_class_attrs); i++) {
++		ret = class_create_file(&info_class, &info_class_attrs[i]);
++		if (ret)
++			goto out_class_create_file_failed;
++	}
++
++	ret = misc_register(&soc_info_device);
++	if (ret != 0) {
++		pr_err("%s: misc_register() failed!(%d)\n", __func__, ret);
++		class_unregister(&info_class);
++		return ret;
++	}
++
++	return ret;
++
++out_class_create_file_failed:
++	class_unregister(&info_class);
++
++	return ret;
++}
++
++static int sunxi_info_remove(struct platform_device *pdev)
++{
++	misc_deregister(&soc_info_device);
++	class_unregister(&info_class);
++
++	return 0;
++}
++
++static struct platform_driver sunxi_info_driver = {
++        .probe  = sunxi_info_probe,
++        .remove = sunxi_info_remove,
++        .driver = {
++                .name   = "sunxi_info",
++                .owner  = THIS_MODULE,
++                .of_match_table = sunxi_info_match,
++        },
++};
++module_platform_driver(sunxi_info_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("xiafeng<xiafeng@allwinnertech.com>");
++MODULE_DESCRIPTION("sunxi sys info.");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch
new file mode 100644
index 000000000000..f9e25dbce368
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch
@@ -0,0 +1,610 @@
+From 6f085079d8a204f54785bbac5225ef5c43572670 Mon Sep 17 00:00:00 2001
+From: afaulkner420 <afaulkner420@gmail.com>
+Date: Fri, 25 Mar 2022 20:18:18 +0000
+Subject: Add sunxi-addr driver - Used to fix uwe5622 bluetooth MAC addresses
+
+---
+ drivers/misc/Kconfig                 |   1 +
+ drivers/misc/Makefile                |   1 +
+ drivers/misc/sunxi-addr/Kconfig      |   6 +
+ drivers/misc/sunxi-addr/Makefile     |   5 +
+ drivers/misc/sunxi-addr/sha256.c     | 178 +++++++++++++
+ drivers/misc/sunxi-addr/sunxi-addr.c | 357 +++++++++++++++++++++++++++
+ 6 files changed, 548 insertions(+)
+ create mode 100644 drivers/misc/sunxi-addr/Kconfig
+ create mode 100644 drivers/misc/sunxi-addr/Makefile
+ create mode 100644 drivers/misc/sunxi-addr/sha256.c
+ create mode 100644 drivers/misc/sunxi-addr/sunxi-addr.c
+
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index 57201f491f8d..26f2df508f70 100644
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -598,4 +598,5 @@ source "drivers/misc/cardreader/Kconfig"
+ source "drivers/misc/uacce/Kconfig"
+ source "drivers/misc/pvpanic/Kconfig"
+ source "drivers/misc/mchp_pci1xxxx/Kconfig"
++source "drivers/misc/sunxi-addr/Kconfig"
+ endmenu
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index c5556e3008c1..9ba27862b564 100644
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -69,3 +69,4 @@ obj-$(CONFIG_TPS6594_ESM)	+= tps6594-esm.o
+ obj-$(CONFIG_TPS6594_PFSM)	+= tps6594-pfsm.o
+ obj-$(CONFIG_NSM)		+= nsm.o
+ obj-$(CONFIG_MODEM_POWER)	+= modem-power.o
++obj-$(CONFIG_SUNXI_ADDR_MGT)    += sunxi-addr/
+diff --git a/drivers/misc/sunxi-addr/Kconfig b/drivers/misc/sunxi-addr/Kconfig
+new file mode 100644
+index 000000000000..801dd2c02a56
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/Kconfig
+@@ -0,0 +1,6 @@
++config SUNXI_ADDR_MGT
++  tristate "Allwinner Network MAC Addess Manager"
++  depends on BT || ETHERNET || WLAN
++  depends on NVMEM_SUNXI_SID
++  help
++    allwinner network mac address management
+diff --git a/drivers/misc/sunxi-addr/Makefile b/drivers/misc/sunxi-addr/Makefile
+new file mode 100644
+index 000000000000..f01fd4783566
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/Makefile
+@@ -0,0 +1,5 @@
++#
++# Makefile for wifi mac addr manager drivers
++#
++sunxi_addr-objs := sunxi-addr.o sha256.o
++obj-$(CONFIG_SUNXI_ADDR_MGT)   += sunxi_addr.o
+diff --git a/drivers/misc/sunxi-addr/sha256.c b/drivers/misc/sunxi-addr/sha256.c
+new file mode 100644
+index 000000000000..78825810c53f
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/sha256.c
+@@ -0,0 +1,178 @@
++/*
++ * Local implement of sha256.
++ *
++ * Copyright (C) 2013 Allwinner.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#include <linux/kernel.h>
++#include <linux/string.h>
++
++/****************************** MACROS ******************************/
++#define ROTRIGHT(a, b) (((a) >> (b)) | ((a) << (32 - (b))))
++#define CH(x, y, z)    (((x) & (y)) ^ (~(x) & (z)))
++#define MAJ(x, y, z)   (((x) & (y)) ^  ((x) & (z)) ^ ((y) & (z)))
++#define EP0(x)         (ROTRIGHT(x,  2) ^ ROTRIGHT(x, 13) ^ ROTRIGHT(x, 22))
++#define EP1(x)         (ROTRIGHT(x,  6) ^ ROTRIGHT(x, 11) ^ ROTRIGHT(x, 25))
++#define SIG0(x)        (ROTRIGHT(x,  7) ^ ROTRIGHT(x, 18) ^ ((x) >> 3))
++#define SIG1(x)        (ROTRIGHT(x, 17) ^ ROTRIGHT(x, 19) ^ ((x) >> 10))
++
++/**************************** VARIABLES *****************************/
++static const uint32_t k[64] = {
++	0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
++	0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
++	0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
++	0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
++	0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
++	0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
++	0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,
++	0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,
++	0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
++	0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,
++	0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,
++	0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
++	0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
++	0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,
++	0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
++	0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
++};
++
++struct sha256_ctx {
++	uint8_t data[64];   /* current 512-bit chunk of message data, just like a buffer */
++	uint32_t datalen;   /* sign the data length of current chunk */
++	uint64_t bitlen;    /* the bit length of the total message */
++	uint32_t state[8];  /* store the middle state of hash abstract */
++};
++
++/*********************** FUNCTION DEFINITIONS ***********************/
++static void sha256_transform(struct sha256_ctx *ctx, const uint8_t *data)
++{
++	uint32_t a, b, c, d, e, f, g, h, i, j, t1, t2, m[64];
++
++	/* initialization */
++	for (i = 0, j = 0; i < 16; ++i, j += 4)
++		m[i] = (data[j] << 24) | (data[j + 1] << 16) |
++			(data[j + 2] << 8) | (data[j + 3]);
++	for ( ; i < 64; ++i)
++		m[i] = SIG1(m[i - 2]) + m[i - 7] + SIG0(m[i - 15]) + m[i - 16];
++
++	a = ctx->state[0];
++	b = ctx->state[1];
++	c = ctx->state[2];
++	d = ctx->state[3];
++	e = ctx->state[4];
++	f = ctx->state[5];
++	g = ctx->state[6];
++	h = ctx->state[7];
++
++	for (i = 0; i < 64; ++i) {
++		t1 = h + EP1(e) + CH(e, f, g) + k[i] + m[i];
++		t2 = EP0(a) + MAJ(a, b, c);
++		h = g;
++		g = f;
++		f = e;
++		e = d + t1;
++		d = c;
++		c = b;
++		b = a;
++		a = t1 + t2;
++	}
++
++	ctx->state[0] += a;
++	ctx->state[1] += b;
++	ctx->state[2] += c;
++	ctx->state[3] += d;
++	ctx->state[4] += e;
++	ctx->state[5] += f;
++	ctx->state[6] += g;
++	ctx->state[7] += h;
++}
++
++static void sha256_init(struct sha256_ctx *ctx)
++{
++	ctx->datalen = 0;
++	ctx->bitlen = 0;
++	ctx->state[0] = 0x6a09e667;
++	ctx->state[1] = 0xbb67ae85;
++	ctx->state[2] = 0x3c6ef372;
++	ctx->state[3] = 0xa54ff53a;
++	ctx->state[4] = 0x510e527f;
++	ctx->state[5] = 0x9b05688c;
++	ctx->state[6] = 0x1f83d9ab;
++	ctx->state[7] = 0x5be0cd19;
++}
++
++static void sha256_update(struct sha256_ctx *ctx, const uint8_t *data, size_t len)
++{
++	uint32_t i;
++
++	for (i = 0; i < len; ++i) {
++		ctx->data[ctx->datalen] = data[i];
++		ctx->datalen++;
++		if (ctx->datalen == 64) {
++			/* 64 byte = 512 bit  means the buffer ctx->data has
++			 * fully stored one chunk of message,
++			 * so do the sha256 hash map for the current chunk.
++			 */
++			sha256_transform(ctx, ctx->data);
++			ctx->bitlen += 512;
++			ctx->datalen = 0;
++		}
++	}
++}
++
++static void sha256_final(struct sha256_ctx *ctx, uint8_t *hash)
++{
++	uint32_t i;
++
++	i = ctx->datalen;
++
++	/* Pad whatever data is left in the buffer. */
++	if (ctx->datalen < 56) {
++		ctx->data[i++] = 0x80;  /* pad 10000000 = 0x80 */
++		while (i < 56)
++			ctx->data[i++] = 0x00;
++	} else {
++		ctx->data[i++] = 0x80;
++		while (i < 64)
++			ctx->data[i++] = 0x00;
++		sha256_transform(ctx, ctx->data);
++		memset(ctx->data, 0, 56);
++	}
++
++	/* Append to the padding the total message's length in bits and transform. */
++	ctx->bitlen += ctx->datalen * 8;
++	ctx->data[63] = ctx->bitlen;
++	ctx->data[62] = ctx->bitlen >> 8;
++	ctx->data[61] = ctx->bitlen >> 16;
++	ctx->data[60] = ctx->bitlen >> 24;
++	ctx->data[59] = ctx->bitlen >> 32;
++	ctx->data[58] = ctx->bitlen >> 40;
++	ctx->data[57] = ctx->bitlen >> 48;
++	ctx->data[56] = ctx->bitlen >> 56;
++	sha256_transform(ctx, ctx->data);
++
++	/* copying the final state to the output hash(use big endian). */
++	for (i = 0; i < 4; ++i) {
++		hash[i]      = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 4]  = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 8]  = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 20] = (ctx->state[5] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 24] = (ctx->state[6] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 28] = (ctx->state[7] >> (24 - i * 8)) & 0x000000ff;
++	}
++}
++
++int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output)
++{
++	struct sha256_ctx ctx;
++
++	sha256_init(&ctx);
++	sha256_update(&ctx, plaintext, psize);
++	sha256_final(&ctx, output);
++	return 0;
++}
+diff --git a/drivers/misc/sunxi-addr/sunxi-addr.c b/drivers/misc/sunxi-addr/sunxi-addr.c
+new file mode 100644
+index 000000000000..f4f2dcecbb48
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/sunxi-addr.c
+@@ -0,0 +1,357 @@
++/*
++ * The driver of SUNXI NET MAC ADDR Manager.
++ *
++ * Copyright (C) 2013 Allwinner.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#define DEBUG
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/miscdevice.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++
++#define ADDR_MGT_DBG(fmt, arg...) printk(KERN_DEBUG "[ADDR_MGT] %s: " fmt "\n",\
++				__func__, ## arg)
++#define ADDR_MGT_ERR(fmt, arg...) printk(KERN_ERR "[ADDR_MGT] %s: " fmt "\n",\
++				__func__, ## arg)
++
++#define MODULE_CUR_VERSION  "v1.0.9"
++
++#define MATCH_STR_LEN       20
++#define ADDR_VAL_LEN        6
++#define ADDR_STR_LEN        18
++#define ID_LEN              16
++#define HASH_LEN            32
++
++#define TYPE_ANY            0
++#define TYPE_BURN           1
++#define TYPE_IDGEN          2
++#define TYPE_USER           3
++#define TYPE_RAND           4
++
++#define ADDR_FMT_STR        0
++#define ADDR_FMT_VAL        1
++
++#define IS_TYPE_INVALID(x)  ((x < TYPE_ANY) || (x > TYPE_RAND))
++
++#define ADDR_CLASS_ATTR_ADD(name) \
++static ssize_t addr_##name##_show(const struct class *class, \
++		const struct class_attribute *attr, char *buffer) \
++{ \
++	char addr[ADDR_STR_LEN]; \
++	if (IS_TYPE_INVALID(get_addr_by_name(ADDR_FMT_STR, addr, #name))) \
++		return 0; \
++	return sprintf(buffer, "%.17s\n", addr); \
++} \
++static ssize_t addr_##name##_store(const struct class *class, \
++		const struct class_attribute *attr, \
++		const char *buffer, size_t count) \
++{ \
++	if (count != ADDR_STR_LEN) { \
++		ADDR_MGT_ERR("Length wrong."); \
++		return -EINVAL; \
++	} \
++	set_addr_by_name(TYPE_USER, ADDR_FMT_STR, buffer, #name); \
++	return count; \
++} \
++static CLASS_ATTR_RW(addr_##name);
++
++struct addr_mgt_info {
++	unsigned int type_def;
++	unsigned int type_cur;
++	unsigned int flag;
++	char *addr;
++	char *name;
++};
++
++static struct addr_mgt_info info[] = {
++	{TYPE_ANY, TYPE_ANY, 1, NULL, "wifi"},
++	{TYPE_ANY, TYPE_ANY, 0, NULL, "bt"  },
++	{TYPE_ANY, TYPE_ANY, 1, NULL, "eth" },
++};
++
++extern int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output);
++extern int sunxi_get_soc_chipid(unsigned char *chipid);
++
++static int addr_parse(int fmt, const char *addr, int check)
++{
++	char val_buf[ADDR_VAL_LEN];
++	char cmp_buf[ADDR_VAL_LEN];
++	int  ret = ADDR_VAL_LEN;
++
++	if (fmt == ADDR_FMT_STR)
++		ret = sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
++					&val_buf[0], &val_buf[1], &val_buf[2],
++					&val_buf[3], &val_buf[4], &val_buf[5]);
++	else
++		memcpy(val_buf, addr, ADDR_VAL_LEN);
++
++	if (ret != ADDR_VAL_LEN)
++		return -1;
++
++	if (check && (val_buf[0] & 0x3))
++		return -1;
++
++	memset(cmp_buf, 0x00, ADDR_VAL_LEN);
++	if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
++		return -1;
++
++	memset(cmp_buf, 0xFF, ADDR_VAL_LEN);
++	if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
++		return -1;
++
++	return 0;
++}
++
++static struct addr_mgt_info *addr_find_by_name(char *name)
++{
++	int i = 0;
++	for (i = 0; i < ARRAY_SIZE(info); i++) {
++		if (strcmp(info[i].name, name) == 0)
++			return &info[i];
++	}
++	return NULL;
++}
++
++static int get_addr_by_name(int fmt, char *addr, char *name)
++{
++	struct addr_mgt_info *t;
++
++	t = addr_find_by_name(name);
++	if (t == NULL) {
++		ADDR_MGT_ERR("can't find addr named: %s", name);
++		return -1;
++	}
++
++	if (IS_TYPE_INVALID(t->type_cur)) {
++		ADDR_MGT_ERR("addr type invalid");
++		return -1;
++	}
++
++	if (addr_parse(ADDR_FMT_VAL, t->addr, t->flag)) {
++		ADDR_MGT_ERR("addr parse fail(%s)", t->addr);
++		return -1;
++	}
++
++	if (fmt == ADDR_FMT_STR)
++		sprintf(addr, "%02X:%02X:%02X:%02X:%02X:%02X",
++				t->addr[0], t->addr[1], t->addr[2],
++				t->addr[3], t->addr[4], t->addr[5]);
++	else
++		memcpy(addr, t->addr, ADDR_VAL_LEN);
++
++	return t->type_cur;
++}
++
++static int set_addr_by_name(int type, int fmt, const char *addr, char *name)
++{
++	struct addr_mgt_info *t;
++
++	t = addr_find_by_name(name);
++	if (t == NULL) {
++		ADDR_MGT_ERR("can't find addr named: %s", name);
++		return -1;
++	}
++
++	if (addr_parse(fmt, addr, t->flag)) {
++		ADDR_MGT_ERR("addr parse fail(%s)", addr);
++		return -1;
++	}
++
++	t->type_cur = type;
++	if (fmt == ADDR_FMT_STR)
++		sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
++				&t->addr[0], &t->addr[1], &t->addr[2],
++				&t->addr[3], &t->addr[4], &t->addr[5]);
++	else
++		memcpy(t->addr, addr, ADDR_VAL_LEN);
++
++	return 0;
++}
++
++int get_custom_mac_address(int fmt, char *name, char *addr)
++{
++	return get_addr_by_name(fmt, addr, name);
++}
++EXPORT_SYMBOL_GPL(get_custom_mac_address);
++
++static int addr_factory(struct device_node *np,
++			int idx, int type, char *mac, char *name)
++{
++	int  ret, i;
++	char match[MATCH_STR_LEN];
++	const char *p;
++	char id[ID_LEN], hash[HASH_LEN], cmp_buf[ID_LEN];
++	struct timespec64 curtime;
++
++	switch (type) {
++	case TYPE_BURN:
++		sprintf(match, "addr_%s", name);
++		ret = of_property_read_string_index(np, match, 0, &p);
++		if (ret)
++			return -1;
++
++		ret = sscanf(p, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
++			&mac[0], &mac[1], &mac[2],
++			&mac[3], &mac[4], &mac[5]);
++
++		if (ret != ADDR_VAL_LEN)
++			return -1;
++		break;
++	case TYPE_IDGEN:
++		if (idx > HASH_LEN / ADDR_VAL_LEN - 1)
++			return -1;
++		if (sunxi_get_soc_chipid(id))
++			return -1;
++		memset(cmp_buf, 0x00, ID_LEN);
++		if (memcmp(id, cmp_buf, ID_LEN) == 0)
++			return -1;
++		if (hmac_sha256(id, ID_LEN, hash))
++			return -1;
++		memcpy(mac, &hash[idx * ADDR_VAL_LEN], ADDR_VAL_LEN);
++		break;
++	case TYPE_RAND:
++		for (i = 0; i < ADDR_VAL_LEN; i++) {
++			ktime_get_real_ts64(&curtime);
++			mac[i] = (char)curtime.tv_nsec;
++		}
++		break;
++	default:
++		ADDR_MGT_ERR("unsupport type: %d", type);
++		return -1;
++	}
++	return 0;
++}
++
++static int addr_init(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	int  type, i, j;
++	char match[MATCH_STR_LEN];
++	char addr[ADDR_VAL_LEN];
++	int  type_tab[] = {TYPE_BURN, TYPE_IDGEN, TYPE_RAND};
++
++	/* init addr type and value */
++	for (i = 0; i < ARRAY_SIZE(info); i++) {
++		sprintf(match, "type_addr_%s", info[i].name);
++		if (of_property_read_u32(np, match, &type)) {
++			ADDR_MGT_DBG("Failed to get type_def_%s, use default: %d",
++						info[i].name, info[i].type_def);
++		} else {
++			info[i].type_def = type;
++			info[i].type_cur = type;
++		}
++
++		if (IS_TYPE_INVALID(info[i].type_def))
++			return -1;
++		if (info[i].type_def != TYPE_ANY) {
++			if (addr_factory(np, i, info[i].type_def, addr, info[i].name))
++				return -1;
++		} else {
++			for (j = 0; j < ARRAY_SIZE(type_tab); j++) {
++				if (!addr_factory(np, i, type_tab[j], addr, info[i].name)) {
++					info[i].type_cur = type_tab[j];
++					break;
++				}
++			}
++		}
++
++		if (info[i].flag)
++			addr[0] &= 0xFC;
++
++		if (addr_parse(ADDR_FMT_VAL, addr, info[i].flag))
++			return -1;
++		else {
++			info[i].addr = devm_kzalloc(&pdev->dev, ADDR_VAL_LEN, GFP_KERNEL);
++			memcpy(info[i].addr, addr, ADDR_VAL_LEN);
++		}
++	}
++	return 0;
++}
++
++static ssize_t summary_show(const struct class *class,
++				const struct class_attribute *attr, char *buffer)
++{
++	int i = 0, ret = 0;
++
++	ret += sprintf(&buffer[ret], "name cfg cur address\n");
++	for (i = 0; i < ARRAY_SIZE(info); i++) {
++		ret += sprintf(&buffer[ret],
++			"%4s  %d   %d  %02X:%02X:%02X:%02X:%02X:%02X\n",
++			info[i].name,   info[i].type_def, info[i].type_cur,
++			info[i].addr[0], info[i].addr[1], info[i].addr[2],
++			info[i].addr[3], info[i].addr[4], info[i].addr[5]);
++	}
++	return ret;
++}
++static CLASS_ATTR_RO(summary);
++
++ADDR_CLASS_ATTR_ADD(wifi);
++ADDR_CLASS_ATTR_ADD(bt);
++ADDR_CLASS_ATTR_ADD(eth);
++
++static struct attribute *addr_class_attrs[] = {
++	&class_attr_summary.attr,
++	&class_attr_addr_wifi.attr,
++	&class_attr_addr_bt.attr,
++	&class_attr_addr_eth.attr,
++	NULL
++};
++ATTRIBUTE_GROUPS(addr_class);
++
++static struct class addr_class = {
++	.name = "addr_mgt",
++	.class_groups = addr_class_groups,
++};
++
++static const struct of_device_id addr_mgt_ids[] = {
++	{ .compatible = "allwinner,sunxi-addr_mgt" },
++	{ /* Sentinel */ }
++};
++
++static int addr_mgt_probe(struct platform_device *pdev)
++{
++	int status;
++
++	ADDR_MGT_DBG("module version: %s", MODULE_CUR_VERSION);
++	status = class_register(&addr_class);
++	if (status < 0) {
++		ADDR_MGT_ERR("class register error, status: %d.", status);
++		return -1;
++	}
++
++	if (addr_init(pdev)) {
++		ADDR_MGT_ERR("failed to init addr.");
++		class_unregister(&addr_class);
++		return -1;
++	}
++	ADDR_MGT_DBG("success.");
++	return 0;
++}
++
++static int addr_mgt_remove(struct platform_device *pdev)
++{
++	class_unregister(&addr_class);
++	return 0;
++}
++
++static struct platform_driver addr_mgt_driver = {
++	.probe  = addr_mgt_probe,
++	.remove = addr_mgt_remove,
++	.driver = {
++		.owner = THIS_MODULE,
++		.name  = "sunxi-addr-mgt",
++		.of_match_table = addr_mgt_ids,
++	},
++};
++
++module_platform_driver_probe(addr_mgt_driver, addr_mgt_probe);
++
++MODULE_AUTHOR("Allwinnertech");
++MODULE_DESCRIPTION("Network MAC Addess Manager");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch
new file mode 100644
index 000000000000..2dd6b9ac79c2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch
@@ -0,0 +1,88 @@
+From 68e3c93f16478ac7a1fe2d64b79c76b96e5782f6 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Tue, 19 Sep 2023 11:06:01 +0000
+Subject: Add wifi nodes for Inovato Quadra
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |  1 +
+ .../allwinner/sun50i-h6-inovato-quadra.dts    | 56 +++++++++++++++++++
+ 2 files changed, 57 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index ad82da8e2aad..8b504ee408e7 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-inovato-quadra.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts
+new file mode 100644
+index 000000000000..551ad69f18a6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts
+@@ -0,0 +1,56 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (c) 2023 Gunjan Gupta <gunjan@armbian.com>
++
++/dts-v1/;
++
++#include "sun50i-h6-tanix.dtsi"
++
++/ {
++	model = "Inovato Quadra";
++	compatible = "oranth,inovato-quadra", "allwinner,sun50i-h6";
++
++	aliases {
++		ethernet1 = &xr819;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			label = "red";
++			gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
++		};
++
++		led-1 {
++			label = "blue";
++			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++			default-state = "on";
++		};
++	};
++};
++
++&i2s1 {
++	status = "okay";
++};
++
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++
++	xr819: sdio_wifi@1 {
++		compatible = "xradio,xr819";
++		interrupt-names = "host-wake";
++		interrupt-parent = <&r_pio>;
++		interrupts = <1 0 IRQ_TYPE_EDGE_RISING>;
++		local-mac-address = [dc 44 6d c0 ff ee];
++		reg = <1>;
++	};
++};
++
++&sound_hdmi {
++	status = "okay";
++};
++
++&wifi_pwrseq {
++	post-power-on-delay-ms = <0xc8>;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch
new file mode 100644
index 000000000000..44cae6b77e40
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch
@@ -0,0 +1,275 @@
+From b00947dcec1f065d87e0d560a4e32e3f4309ffdf Mon Sep 17 00:00:00 2001
+From: Alan <Alan>
+Date: Sat, 20 May 2023 17:26:21 +0800
+Subject: Add: ws2812 RGB driver for allwinner H616
+
+---
+ drivers/leds/rgb/Kconfig       |   7 +
+ drivers/leds/rgb/Makefile      |   1 +
+ drivers/leds/rgb/leds-ws2812.c | 229 +++++++++++++++++++++++++++++++++
+ 3 files changed, 237 insertions(+)
+ create mode 100644 drivers/leds/rgb/leds-ws2812.c
+
+diff --git a/drivers/leds/rgb/Kconfig b/drivers/leds/rgb/Kconfig
+index 8fc12d6a2958..67e65f72b0be 100644
+--- a/drivers/leds/rgb/Kconfig
++++ b/drivers/leds/rgb/Kconfig
+@@ -77,3 +77,10 @@ config LEDS_MT6370_RGB
+ 	  will be called "leds-mt6370-rgb".
+ 
+ endif # LEDS_CLASS_MULTICOLOR
++
++config LEDS_WS2812
++	tristate "WS2812 RGB support for allwinner H616"
++	depends on PINCTRL_SUN50I_H616
++
++	help
++	  Say Y here if you want to use the WS2812.
+\ No newline at end of file
+diff --git a/drivers/leds/rgb/Makefile b/drivers/leds/rgb/Makefile
+index a501fd27f179..8f7646ead3c1 100644
+--- a/drivers/leds/rgb/Makefile
++++ b/drivers/leds/rgb/Makefile
+@@ -6,3 +6,4 @@ obj-$(CONFIG_LEDS_NCP5623)		+= leds-ncp5623.o
+ obj-$(CONFIG_LEDS_PWM_MULTICOLOR)	+= leds-pwm-multicolor.o
+ obj-$(CONFIG_LEDS_QCOM_LPG)		+= leds-qcom-lpg.o
+ obj-$(CONFIG_LEDS_MT6370_RGB)		+= leds-mt6370-rgb.o
++obj-$(CONFIG_LEDS_WS2812)		+= leds-ws2812.o
+diff --git a/drivers/leds/rgb/leds-ws2812.c b/drivers/leds/rgb/leds-ws2812.c
+new file mode 100644
+index 000000000000..1af735ce8e4d
+--- /dev/null
++++ b/drivers/leds/rgb/leds-ws2812.c
+@@ -0,0 +1,229 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
++ */
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/cdev.h>
++#include <linux/fs.h>
++#include <linux/device.h>
++#include <asm/uaccess.h>
++#include <linux/moduleparam.h>
++#include <linux/ioctl.h>
++#include <linux/version.h>
++#include <linux/errno.h>
++#include <linux/rbtree.h>
++#include <linux/ktime.h>
++#include <linux/string.h>
++#include <linux/mutex.h>
++#include <linux/time.h>
++#include <linux/hrtimer.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/input.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++#include <linux/uaccess.h>
++
++#define GPIO_BASE 0x0300B000
++#define GPIO_DAT_OFFSET(n) ((n)*0x0024 + 0x10)
++
++static uint32_t ws2812_pin = 0;
++static volatile uint32_t *ws2812_gpio_port;
++static volatile uint32_t ws2812_gpio_bit;
++static volatile uint32_t ws2812_set_val = 0;
++static volatile uint32_t ws2812_reset_val = 0;
++
++DEFINE_SPINLOCK(lock);
++
++// ws2812 reset
++static void ws2812_rst(void)
++{
++	*ws2812_gpio_port &= ~ws2812_gpio_bit;
++	udelay(200);// RES low voltage time, Above 50µs
++}
++
++static void ws2812_Write_24Bits(uint32_t grb)
++{
++	uint8_t i;
++	for (i = 0; i < 24; i++)
++	{
++		if (grb & 0x800000)
++		{
++			// loop for delay about 700ns
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			// loop for delay about 600ns
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++		}
++		else
++		{
++			// loop for delay about 200ns
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			// loop for delay about 800ns
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++		}
++		grb <<= 1;
++	}
++}
++
++static void ws2812_write_array(uint32_t *rgb, uint32_t cnt)
++{
++	uint32_t i = 0;
++	unsigned long flags;
++
++	for (i = 0; i < cnt; i++)
++	{
++		// rgb -> grb
++		rgb[i] = (((rgb[i] >> 16) & 0xff) << 8) | (((rgb[i] >> 8) & 0xff) << 16) | ((rgb[i]) & 0xff);
++	}
++
++	spin_lock_irqsave(&lock, flags);
++	ws2812_set_val = *ws2812_gpio_port | ws2812_gpio_bit;
++	ws2812_reset_val = *ws2812_gpio_port & (~ws2812_gpio_bit);
++	ws2812_rst();
++	for (i = 0; i < cnt; i++)
++	{
++		ws2812_Write_24Bits(rgb[i]);
++	}
++	spin_unlock_irqrestore(&lock, flags);
++}
++
++ssize_t ws2812_read(struct file *file, char __user *user, size_t bytesize, loff_t *this_loff_t)
++{
++	return 0;
++}
++
++ssize_t ws2812_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos)
++{
++	uint32_t rgb[255];
++	unsigned long ret = 0;
++
++	if (count > 255 * 4) count = 255 * 4;
++	ret = copy_from_user(&rgb[0], user_buf, count);
++	if (ret < 0)
++	{
++		printk("copy_from_user fail!!!\n");
++		return -1;
++	}
++
++	ws2812_write_array((uint32_t *)rgb, count / 4);
++
++	return 0;
++}
++
++int ws2812_open(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++int ws2812_close(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static struct file_operations ws2812_ops = {
++	.owner = THIS_MODULE,
++	.open = ws2812_open,
++	.release = ws2812_close,
++	.write = ws2812_write,
++};
++
++static struct miscdevice ws2812_misc_dev = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name = "ws2812-led",
++	.fops = &ws2812_ops,
++};
++
++static int ws2812_probe(struct platform_device *pdev)
++{
++	int ret;
++	struct device_node *ws2812_gpio_node = pdev->dev.of_node;
++	uint32_t rgb_cnt = 0;
++	uint32_t rgb[255];
++
++	of_property_read_u32(ws2812_gpio_node, "rgb_cnt", &rgb_cnt);
++	if (rgb_cnt > 255)
++		rgb_cnt = 255;
++
++	of_property_read_u32_array(ws2812_gpio_node, "rgb_value", rgb, rgb_cnt);
++	ws2812_pin = of_get_named_gpio(ws2812_gpio_node, "gpios", 0);
++	if (!gpio_is_valid(ws2812_pin))
++	{
++		printk(KERN_ERR "ws2812: gpio: %d is invalid\n", ws2812_pin);
++		return -ENODEV;
++	}
++
++	ws2812_gpio_port = ioremap(GPIO_BASE + GPIO_DAT_OFFSET((ws2812_pin >> 5)), 4);
++	ws2812_gpio_bit = 1 << (ws2812_pin & 0x001F);
++
++	if (gpio_request(ws2812_pin, "ws2812-gpio"))
++	{
++		printk(KERN_ERR "ws2812: gpio %d request failed!\n", ws2812_pin);
++		gpio_free(ws2812_pin);
++		return -ENODEV;
++	}
++	gpio_direction_output(ws2812_pin, 0);
++
++	ret = misc_register(&ws2812_misc_dev);
++	msleep(50);
++
++	ws2812_write_array(rgb, rgb_cnt);
++
++	return 0;
++}
++
++static int ws2812_remove(struct platform_device *pdev)
++{
++	misc_deregister(&ws2812_misc_dev);
++	gpio_free(ws2812_pin);
++
++	return 0;
++}
++
++static const struct of_device_id ws2812_of_match[] = {
++	{.compatible = "rgb-ws2812"},
++	{/* sentinel */}};
++
++MODULE_DEVICE_TABLE(of, ws2812_of_match);
++
++static struct platform_driver ws2812_driver = {
++	.probe		= ws2812_probe,
++	.remove		= ws2812_remove,
++	.driver		= {
++		.name	= "ws2812_ctl",
++		.of_match_table = ws2812_of_match,
++	},
++};
++
++module_platform_driver(ws2812_driver);
++
++MODULE_AUTHOR("MacLodge, Alan Ma <tech@biqu3d.com>");
++MODULE_DESCRIPTION("WS2812 RGB driver for Allwinner");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ws2812_ctl");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Bananapro-add-AXP209-regulators.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Bananapro-add-AXP209-regulators.patch
new file mode 100644
index 000000000000..5fe432e63cfc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Bananapro-add-AXP209-regulators.patch
@@ -0,0 +1,72 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 12 Apr 2022 21:14:36 +0300
+Subject: Bananapro add AXP209 regulators
+
+Author: Heiko Jehmlich <hje@jecons.de>
+Signed-off-by: Heiko Jehmlich <hje@jecons.de>
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts | 50 ++++++++++
+ 1 file changed, 50 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+index 3a34fb39a840..d5bc590604a9 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+@@ -257,3 +257,53 @@ &usbphy {
+ &reg_ahci_5v {
+ 	status = "okay";
+ };
++
++#include "axp209.dtsi"
++
++&ac_power_supply {
++	status = "okay";
++};
++
++&battery_power_supply {
++	status = "okay";
++};
++
++&reg_dcdc2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1000000>;
++	regulator-max-microvolt = <1450000>;
++	regulator-name = "vdd-cpu";
++};
++
++&reg_dcdc3 {
++	regulator-always-on;
++	regulator-min-microvolt = <1000000>;
++	regulator-max-microvolt = <1400000>;
++	regulator-name = "vdd-int-dll";
++};
++
++&reg_ldo1 {
++	regulator-name = "vdd-rtc";
++};
++
++&reg_ldo2 {
++	regulator-always-on;
++	regulator-min-microvolt = <3000000>;
++	regulator-max-microvolt = <3000000>;
++	regulator-name = "avcc";
++};
++
++&reg_ldo3 {
++	regulator-always-on;
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "vddio-csi0";
++	regulator-ramp-delay = <1600>;
++};
++
++&reg_ldo4 {
++	regulator-always-on; /* required for SATA */
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "vddio-csi1";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch
new file mode 100644
index 000000000000..f93db4608e8f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch
@@ -0,0 +1,63 @@
+From 073fe82934a9ca83fa80f9415d48f6d69dd6c69f Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Mon, 25 Dec 2017 12:08:01 +0800
+Subject: Doc:dt-bindings:usb: add binding for DWC3 controller on Allwinner SoC
+
+The Allwinner H6 SoC uses DWC3 controller for USB3.
+
+Add its device tree binding document.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ .../bindings/usb/allwinner,dwc3.txt           | 39 +++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
+
+diff --git a/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
+new file mode 100644
+index 000000000000..3f7714636785
+--- /dev/null
++++ b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
+@@ -0,0 +1,39 @@
++Allwinner SuperSpeed DWC3 USB SoC controller
++
++Required properties:
++- compatible:	should contain "allwinner,sun50i-h6-dwc3" for H6 SoC
++- clocks:	A list of phandle + clock-specifier pairs for the
++		clocks listed in clock-names
++- clock-names:	Should contain the following:
++  "bus"		The bus clock of the DWC3 part
++- resets:	A list of phandle + reset-specifier pairs for the
++		resets listed in reset-names
++- reset-names:	Should contain the following:
++  "bus"		The bus reset of the DWC3 part
++
++Required child node:
++A child node must exist to represent the core DWC3 IP block. The name of
++the node is not important. The content of the node is defined in dwc3.txt.
++
++Phy documentation is provided in the following places:
++Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
++
++Example device nodes:
++	usb3: usb@5200000 {
++		compatible = "allwinner,sun50i-h6-dwc3";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges;
++		clocks = <&ccu CLK_BUS_XHCI>;
++		clock-names = "bus";
++		resets = <&ccu RST_BUS_XHCI>;
++		reset-names = "bus";
++
++		dwc3: dwc3 {
++			compatible = "snps,dwc3";
++			reg = <0x5200000 0x10000>;
++			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
++			phys = <&usb3phy>;
++			phy-names = "usb3-phy";
++		};
++	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Fix-include-uapi-spi-spidev-module.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Fix-include-uapi-spi-spidev-module.patch
new file mode 100644
index 000000000000..f9b44e9dc915
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Fix-include-uapi-spi-spidev-module.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Thu, 28 Apr 2022 15:45:14 +0300
+Subject: Fix include uapi spi spidev module
+
+---
+ drivers/spi/spidev.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index 456eca57ee4f..6a306e8efc6f 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -21,8 +21,7 @@
+ #include <linux/slab.h>
+ #include <linux/compat.h>
+ 
+-#include <linux/spi/spi.h>
+-#include <linux/spi/spidev.h>
++#include <uapi/linux/spi/spidev.h>
+ 
+ #include <linux/uaccess.h>
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch
new file mode 100644
index 000000000000..98ce9837e6d2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch
@@ -0,0 +1,48 @@
+From 40adc1cad2067a294c5bf893b1909520ddc19713 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 2 Jan 2021 15:52:27 -0600
+Subject: Input: axp20x-pek - allow wakeup after shutdown
+
+While the AXP20x PMIC handles the power button itself after shutting
+down, it is not always possible to use the PMIC's built-in shutdown
+feature, such as when other wakeup sources are needed (for example, an
+IR remote or wake-on-LAN) that require firmware support. In that case,
+the PMIC remains on, but suspended, until the board is powered back on.
+
+During this "fake" off state, IRQ configuration is similar to system
+sleep, where enable_irq_wake() must be call on an IRQ for it to be
+wakeup capable. Run the suspend callback to arm the power button IRQs
+during the shutdown process, so the power button works in this state.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/input/misc/axp20x-pek.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/input/misc/axp20x-pek.c b/drivers/input/misc/axp20x-pek.c
+index 24f9e9d893de..521fcd626f74 100644
+--- a/drivers/input/misc/axp20x-pek.c
++++ b/drivers/input/misc/axp20x-pek.c
+@@ -384,6 +384,11 @@ static const struct dev_pm_ops axp20x_pek_pm_ops = {
+ 	.resume_noirq = pm_sleep_ptr(axp20x_pek_resume_noirq),
+ };
+ 
++static void axp20x_pek_shutdown(struct platform_device *pdev)
++{
++	axp20x_pek_suspend(&pdev->dev);
++}
++
+ static const struct platform_device_id axp_pek_id_match[] = {
+ 	{
+ 		.name = "axp20x-pek",
+@@ -399,6 +404,7 @@ MODULE_DEVICE_TABLE(platform, axp_pek_id_match);
+ 
+ static struct platform_driver axp20x_pek_driver = {
+ 	.probe		= axp20x_pek_probe,
++	.shutdown	= axp20x_pek_shutdown,
+ 	.id_table	= axp_pek_id_match,
+ 	.driver		= {
+ 		.name		= "axp20x-pek",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch
new file mode 100644
index 000000000000..9e33b65fb139
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch
@@ -0,0 +1,39 @@
+From 633be858e3fa418f2e1ecab9cbfb6dd78232efd3 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Wed, 31 May 2023 08:12:00 +0000
+Subject: LED-green_power_on-red_status_heartbeat
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+---
+ .../boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi      | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 54dfaf24e75d..3d996494d37c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -27,16 +27,17 @@ leds {
+ 		compatible = "gpio-leds";
+ 
+ 		led-0 {
+-			function = LED_FUNCTION_POWER;
++			function = LED_FUNCTION_STATUS;
+ 			color = <LED_COLOR_ID_RED>;
+ 			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+-			default-state = "on";
++			linux,default-trigger = "heartbeat";
+ 		};
+ 
+ 		led-1 {
+-			function = LED_FUNCTION_STATUS;
++			function = LED_FUNCTION_POWER;
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++			default-state = "on";
+ 		};
+ 	};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch
new file mode 100644
index 000000000000..65d83eaec833
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch
@@ -0,0 +1,27 @@
+From 5fc8a58d0c25d4ed325bd23c3ac9cdd5d6112785 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 11:28:14 +0300
+Subject: Makefile: CONFIG_SHELL fix for builddeb packaging
+
+---
+ Makefile | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Makefile b/Makefile
+index d9243ad053f9..e65dccf2cc47 100644
+--- a/Makefile
++++ b/Makefile
+@@ -423,7 +423,9 @@ KCONFIG_CONFIG	?= .config
+ export KCONFIG_CONFIG
+ 
+ # SHELL used by kbuild
+-CONFIG_SHELL := sh
++CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
++	  else if [ -x /bin/bash ]; then echo /bin/bash; \
++	  else echo sh; fi ; fi)
+ 
+ HOST_LFS_CFLAGS := $(shell getconf LFS_CFLAGS 2>/dev/null)
+ HOST_LFS_LDFLAGS := $(shell getconf LFS_LDFLAGS 2>/dev/null)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch
new file mode 100644
index 000000000000..591e1ac5f13a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch
@@ -0,0 +1,195 @@
+From b8f2e5aba953293fc13a6ea819924cf415baa30a Mon Sep 17 00:00:00 2001
+From: Alan <Alan>
+Date: Sat, 20 May 2023 14:44:07 +0800
+Subject: Optimize: TSC2007 touchscreen add polling method
+
+---
+ drivers/input/touchscreen/tsc2007.h      |   6 ++
+ drivers/input/touchscreen/tsc2007_core.c | 110 +++++++++++++++++++++--
+ 2 files changed, 108 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/input/touchscreen/tsc2007.h b/drivers/input/touchscreen/tsc2007.h
+index 69b08dd6c8df..5252b6c6daeb 100644
+--- a/drivers/input/touchscreen/tsc2007.h
++++ b/drivers/input/touchscreen/tsc2007.h
+@@ -66,10 +66,13 @@ struct tsc2007 {
+ 	u16			model;
+ 	u16			x_plate_ohms;
+ 	u16			max_rt;
++	u16			rt_thr;
++	u8			touched;
+ 	unsigned long		poll_period; /* in jiffies */
+ 	int			fuzzx;
+ 	int			fuzzy;
+ 	int			fuzzz;
++	bool			ignore_nak;
+ 
+ 	struct gpio_desc	*gpiod;
+ 	int			irq;
+@@ -81,6 +84,9 @@ struct tsc2007 {
+ 	void			(*clear_penirq)(void);
+ 
+ 	struct mutex		mlock;
++
++	struct timer_list timer;
++	struct work_struct work_i2c_poll;
+ };
+ 
+ int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd);
+diff --git a/drivers/input/touchscreen/tsc2007_core.c b/drivers/input/touchscreen/tsc2007_core.c
+index b3655250d4a7..5267b0d0ad8c 100644
+--- a/drivers/input/touchscreen/tsc2007_core.c
++++ b/drivers/input/touchscreen/tsc2007_core.c
+@@ -28,6 +28,8 @@
+ #include <linux/platform_data/tsc2007.h>
+ #include "tsc2007.h"
+ 
++#define POLL_INTERVAL_MS 17 /* 17ms = 60fps */
++
+ int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd)
+ {
+ 	s32 data;
+@@ -172,6 +174,65 @@ static irqreturn_t tsc2007_soft_irq(int irq, void *handle)
+ 	return IRQ_HANDLED;
+ }
+ 
++static irqreturn_t tsc2007_soft_poll(int irq, void *handle)
++{
++	struct tsc2007 *ts = handle;
++	struct input_dev *input = ts->input;
++	struct ts_event tc;
++	u32 rt;
++
++	if(!ts->stopped) {
++
++		mutex_lock(&ts->mlock);
++		tsc2007_read_values(ts, &tc);
++		mutex_unlock(&ts->mlock);
++
++		rt = tsc2007_calculate_resistance(ts, &tc);
++
++		if (rt == 0 || rt == 256) {
++
++			/*
++				* Sample found inconsistent by debouncing or pressure is
++				* beyond the maximum. Don't report it to user space,
++				* repeat at least once more the measurement.
++				*/
++			dev_dbg(&ts->client->dev, "ignored pressure %d\n", rt);
++
++		} else {
++
++			if (rt < ts->rt_thr) {
++
++				dev_dbg(&ts->client->dev,
++					"DOWN point(%4d,%4d), resistance (%4u)\n",
++					tc.x, tc.y, rt);
++
++				rt = ts->max_rt - rt;
++
++				input_report_key(input, BTN_TOUCH, 1);
++				input_report_abs(input, ABS_X, tc.y);
++				input_report_abs(input, ABS_Y, 4096 - tc.x);
++				input_report_abs(input, ABS_PRESSURE, rt);
++
++				input_sync(input);
++				ts->touched = 1;
++
++			} else if (ts->touched == 1) {
++
++				dev_dbg(&ts->client->dev, "UP\n");
++
++				input_report_key(input, BTN_TOUCH, 0);
++				input_report_abs(input, ABS_PRESSURE, 0);
++				input_sync(input);
++				ts->touched = 0;
++			}
++		}
++
++
++	}
++
++	return IRQ_HANDLED;
++}
++
+ static void tsc2007_stop(struct tsc2007 *ts)
+ {
+ 	ts->stopped = true;
+@@ -216,11 +277,32 @@ static int tsc2007_get_pendown_state_gpio(struct device *dev)
+ 	return gpiod_get_value_cansleep(ts->gpiod);
+ }
+ 
++static void tsc2007_ts_irq_poll_timer(struct timer_list *t)
++{
++	struct tsc2007 *ts = from_timer(ts, t, timer);
++
++	schedule_work(&ts->work_i2c_poll);
++	mod_timer(&ts->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS));
++}
++
++static void tsc2007_ts_work_i2c_poll(struct work_struct *work)
++{
++	struct tsc2007 *ts = container_of(work,
++			struct tsc2007, work_i2c_poll);
++
++	tsc2007_soft_poll(0, ts);
++}
++
+ static int tsc2007_probe_properties(struct device *dev, struct tsc2007 *ts)
+ {
+ 	u32 val32;
+ 	u64 val64;
+ 
++	ts->ignore_nak = device_property_read_bool(dev, "i2c,ignore-nak");
++
++	if (!device_property_read_u32(dev, "ti,rt-thr", &val32))
++		ts->rt_thr = val32;
++
+ 	if (!device_property_read_u32(dev, "ti,max-rt", &val32))
+ 		ts->max_rt = val32;
+ 	else
+@@ -317,6 +399,9 @@ static int tsc2007_probe(struct i2c_client *client)
+ 	if (!input_dev)
+ 		return -ENOMEM;
+ 
++	if (ts->ignore_nak)
++		client->flags |= I2C_M_IGNORE_NAK;
++
+ 	i2c_set_clientdata(client, ts);
+ 
+ 	ts->client = client;
+@@ -362,14 +447,23 @@ static int tsc2007_probe(struct i2c_client *client)
+ 			pdata->init_platform_hw();
+ 	}
+ 
+-	err = devm_request_threaded_irq(&client->dev, ts->irq,
+-					NULL, tsc2007_soft_irq,
+-					IRQF_ONESHOT,
+-					client->dev.driver->name, ts);
+-	if (err) {
+-		dev_err(&client->dev, "Failed to request irq %d: %d\n",
+-			ts->irq, err);
+-		return err;
++	if (ts->gpiod) {
++		err = devm_request_threaded_irq(&client->dev, ts->irq,
++						NULL, tsc2007_soft_irq,
++						IRQF_ONESHOT,
++						client->dev.driver->name, ts);
++		if (err) {
++			dev_err(&client->dev, "Failed to request irq %d: %d\n",
++				ts->irq, err);
++			return err;
++		}
++	} else {
++		INIT_WORK(&ts->work_i2c_poll,
++			  tsc2007_ts_work_i2c_poll);
++		timer_setup(&ts->timer, tsc2007_ts_irq_poll_timer, 0);
++		ts->timer.expires = jiffies +
++					msecs_to_jiffies(POLL_INTERVAL_MS);
++		add_timer(&ts->timer);
+ 	}
+ 
+ 	tsc2007_stop(ts);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch
new file mode 100644
index 000000000000..3db6c1e3792a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch
@@ -0,0 +1,53 @@
+From 42bfd57db1e8a2daf66799d001d7e23e5ab35a06 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Mon, 26 Jun 2023 14:29:56 +0000
+Subject: Temp_fix mailbox
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 4d3931f83b6b..d57db12f9986 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -42,7 +42,7 @@ bat: battery {
+                 resistance-temp-table = <20 150>;
+                 ocv-capacity-celsius = <20>;
+                 ocv-capacity-table-0 =
+-                	<4334000 100>,
++			<4334000 100>,
+ 			<4319700 99>,
+ 			<4304300 98>,
+ 			<4292200 97>,
+@@ -144,7 +144,7 @@ bat: battery {
+ 			<3393500 1>,
+ 			<3256000 0>;
+                 x-powers,ocv-capacity-table =
+-                	<0xc0 0>,
++			<0xc0 0>,
+ 			<0xc1 1>,
+ 			<0xc2 1>,
+ 			<0xc3 2>,
+@@ -191,7 +191,7 @@ ppkb_battery: keyboard-battery {
+                 factory-internal-resistance-micro-ohms = <120000>;
+                 ocv-capacity-celsius = <20>;
+                 ocv-capacity-table-0 =
+-                	<4147328 100>,
++			<4147328 100>,
+ 			<4132636 99>,
+ 			<4121720 98>,
+ 			<4110905 97>,
+@@ -756,6 +756,7 @@ &mmc1 {
+ 	non-removable;
+ 	post-power-on-delay-ms = <1>; /* wifi power is always on */
+ 	status = "okay";
++	keep-power-in-suspend;
+ 
+ 	rtl8723cs: wifi@1 {
+ 		reg = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/add-initial-support-for-orangepi3-lts.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/add-initial-support-for-orangepi3-lts.patch
new file mode 100644
index 000000000000..6b52f73b41a4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/add-initial-support-for-orangepi3-lts.patch
@@ -0,0 +1,431 @@
+From 9772a09716ae0a9134e1d584ee2c151d08b787c5 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 16 Apr 2022 11:51:35 +0300
+Subject: add initial support for orangepi3-lts
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h6-orangepi-3-lts.dts    | 399 ++++++++++++++++++
+ 2 files changed, 400 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 32798335eec0..02f32ad891cd 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3-lts.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+new file mode 100644
+index 000000000000..dd6b4e15263e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+@@ -0,0 +1,399 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2023 Jernej Skrabec <jernej.skrabec@gmail.com>
++// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
++
++/dts-v1/;
++
++#include "sun50i-h6.dtsi"
++#include "sun50i-h6-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "OrangePi 3 LTS";
++	compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	ext_osc32k: ext_osc32k_clk {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		clock-frequency = <32768>;
++		clock-output-names = "ext_osc32k";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		status {
++			label = "green-led";
++			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++			default-state = "on";
++		};
++
++		power {
++			label = "red-led";
++			gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the DC jack */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <150000>;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		enable-active-high;
++		gpio = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "ext_clock";
++		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&ac200_codec {
++	avcc-supply = <&reg_aldo2>;
++	status = "okay";
++};
++
++&ac200_pwm_clk {
++	status = "okay";
++};
++
++&analog {
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdca>;
++};
++
++&de {
++	status = "okay";
++};
++
++&dwc3 {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii-id";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_gmac_3v3>;
++	allwinner,rx-delay-ps = <200>;
++	allwinner,tx-delay-ps = <300>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdcc>;
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_bldo2>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&i2c3 {
++	status = "okay";
++};
++
++&i2s1 {
++	status = "okay";
++};
++
++&i2s3 {
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++		motorcomm,clk-out-frequency-hz = <125000000>;
++		reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
++		reset-assert-us = <15000>;
++		reset-deassert-us = <40000>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_cldo1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	bus-width = <4>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++};
++
++&mmc2 {
++	vmmc-supply = <&reg_cldo1>;
++	vqmmc-supply = <&reg_bldo2>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	mmc-hs200-1_8v;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pc-supply = <&reg_bldo2>;
++	vcc-pd-supply = <&reg_cldo1>;
++	vcc-pg-supply = <&reg_vcc_wifi_io>;
++};
++
++&pwm {
++	status = "okay";
++};
++
++&r_ir {
++	status = "okay";
++};
++
++&r_i2c {
++	status = "okay";
++
++	axp805: pmic@36 {
++		compatible = "x-powers,axp805", "x-powers,axp806";
++		reg = <0x36>;
++		interrupt-parent = <&r_intc>;
++		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-controller;
++		#interrupt-cells = <1>;
++		x-powers,self-working-mode;
++		vina-supply = <&reg_vcc5v>;
++		vinb-supply = <&reg_vcc5v>;
++		vinc-supply = <&reg_vcc5v>;
++		vind-supply = <&reg_vcc5v>;
++		vine-supply = <&reg_vcc5v>;
++		aldoin-supply = <&reg_vcc5v>;
++		bldoin-supply = <&reg_vcc5v>;
++		cldoin-supply = <&reg_vcc5v>;
++
++		regulators {
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc-pl-led-ir";
++			};
++
++			reg_aldo2: aldo2 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-audio-tv-ephy-mac";
++				regulator-enable-ramp-delay = <100000>;
++			};
++
++			/* ALDO3 is shorted to CLDO1 */
++			reg_aldo3: aldo3 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
++			};
++
++			reg_bldo1: bldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc18-dram-bias-pll";
++			};
++
++			reg_bldo2: bldo2 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-efuse-pcie-hdmi-pc";
++			};
++
++			reg_bldo3: bldo3 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-pm-pg-dcxoio-wifi";
++			};
++
++			bldo4 {
++				/* unused */
++			};
++
++			reg_cldo1: cldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
++			};
++
++			cldo2 {
++				/* unused */
++			};
++
++			cldo3 {
++				/* unused */
++			};
++
++			reg_dcdca: dcdca {
++				regulator-always-on;
++				regulator-min-microvolt = <800000>;
++				regulator-max-microvolt = <1160000>;
++				regulator-ramp-delay = <2500>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdcc: dcdcc {
++				regulator-enable-ramp-delay = <32000>;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <1080000>;
++				regulator-ramp-delay = <2500>;
++				regulator-name = "vdd-gpu";
++			};
++
++			reg_dcdcd: dcdcd {
++				regulator-always-on;
++				regulator-min-microvolt = <960000>;
++				regulator-max-microvolt = <960000>;
++				regulator-name = "vdd-sys";
++			};
++
++			reg_dcdce: dcdce {
++				regulator-always-on;
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-name = "vcc-dram";
++			};
++
++			sw {
++				/* unused */
++			};
++		};
++	};
++};
++
++&rtc {
++	clocks = <&ext_osc32k>;
++};
++
++&sound_hdmi {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	uart-has-rtscts;
++	status = "disabled";
++};
++
++&usb2otg {
++	/*
++	 * This board doesn't have a controllable VBUS even though it
++	 * does have an ID pin. Using it as anything but a USB host is
++	 * unsafe.
++	 */
++	dr_mode = "host";
++	status = "okay";
++};
++
++&usb2phy {
++	usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
++	usb0_vbus-supply = <&reg_vcc5v>;
++	usb3_vbus-supply = <&reg_vcc5v>;
++	status = "okay";
++};
++
++&usb3phy {
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch
new file mode 100644
index 000000000000..3f250c9eb718
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch
@@ -0,0 +1,73 @@
+From be6241b48636a739722e573d1dbb6f5c7856afc7 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 16 Apr 2022 11:51:35 +0300
+Subject: add nodes for sunxi-info, sunxi-addr and sunxi-dump-reg
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 19 +++++++++++++++++++
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 19 +++++++++++++++++++
+ 2 files changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 926b3f568c0d..d01c5c72ff86 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -1241,6 +1241,25 @@ ths: thermal-sensor@5070400 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <1>;
+ 		};
++
++		sunxi-info {
++			compatible = "allwinner,sun50i-h6-sys-info";
++			status = "okay";
++		};
++
++		addr_mgt: addr-mgt {
++			compatible = "allwinner,sunxi-addr_mgt";
++			type_addr_wifi = <0x2>;
++			type_addr_bt = <0x2>;
++			type_addr_eth = <0x2>;
++			status = "okay";
++		};
++
++		dump_reg: dump_reg@20000 {
++			compatible = "allwinner,sunxi-dump-reg";
++			reg = <0x0 0x03001000 0x0 0x0f20>;
++			status = "okay";
++		};
+ 	};
+ 
+ 	thermal-zones {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 6ba83df33652..de2a736f0e33 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -922,6 +922,25 @@ r_rsb: rsb@7083000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 		};
++
++		dump_reg: dump_reg@20000 {
++			compatible = "allwinner,sunxi-dump-reg";
++			reg = <0x0 0x03001000 0x0 0x0f20>;
++			status = "okay";
++		};
++
++		sunxi-info {
++			compatible = "allwinner,sun50i-h616-sys-info";
++			status = "okay";
++		};
++
++		addr_mgt: addr-mgt {
++			compatible = "allwinner,sunxi-addr_mgt";
++			type_addr_wifi = <0x2>;
++			type_addr_bt = <0x2>;
++			type_addr_eth = <0x2>;
++			status = "okay";
++		};
+ 	};
+ 
+ 	thermal-zones {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/adding-dummy-regulators-in-pinctr-arch-arm-boot-dts-allwinner-s.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/adding-dummy-regulators-in-pinctr-arch-arm-boot-dts-allwinner-s.patch
new file mode 100644
index 000000000000..f28575c27f3e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/adding-dummy-regulators-in-pinctr-arch-arm-boot-dts-allwinner-s.patch
@@ -0,0 +1,29 @@
+From 2c535e9609f8259613f9974cdfc93539cd6e5a3b Mon Sep 17 00:00:00 2001
+From: Stephen Graf <stephen.graf@gmail.com>
+Date: Thu, 30 May 2024 18:19:07 -0700
+Subject: adding dummy regulators in pinctr
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+
+Signed-off-by: Stephen Graf <stephen.graf@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index 64c489e356ce..43ddd952f69e 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -212,3 +212,10 @@ &usbphy {
+ 	usb0_vbus-supply = <&reg_usb0_vbus>;
+ 	status = "okay";
+ };
++
++&pio {
++        vcc-pa-supply = <&reg_vcc3v3>;
++        vcc-pc-supply = <&reg_vcc3v3>;
++        vcc-pd-supply = <&reg_vcc3v3>;
++        vcc-pg-supply = <&reg_vcc3v3>;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch
new file mode 100644
index 000000000000..1eaa6f6c2a6f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch
@@ -0,0 +1,39 @@
+From 1fe553681a9b71473a77cb34bdf0c5c380fb04e1 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Thu, 22 Feb 2024 19:31:11 -0500
+Subject: arch: arm64: dts: allwinner: sun50i-h616: PG 12c pins
+
+pins = "PG17", "PG18";
+pins = "PG15", "PG16";
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 58cf9bca7e3c..fda9ff395b1d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -335,6 +335,18 @@ i2c4_ph_pins: i2c4-ph-pins {
+ 				function = "i2c4";
+ 			};
+ 
++			/omit-if-no-ref/
++			i2c3_pg_pins: i2c3-pg-pins {
++				pins = "PG17", "PG18";
++				function = "i2c3";
++			};
++
++			/omit-if-no-ref/
++			i2c4_pg_pins: i2c4-pg-pins {
++				pins = "PG15", "PG16";
++				function = "i2c4";
++			};
++
+ 			ir_rx_pin: ir-rx-pin {
+ 				pins = "PH10";
+ 				function = "ir_rx";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch
new file mode 100644
index 000000000000..23c4ad5a0386
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch
@@ -0,0 +1,30 @@
+From 6b4b39bd1f85161ff9a8e932871e33555eca6e3d Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Wed, 6 Mar 2024 06:51:01 -0500
+Subject: arch: arm64: dts: allwinner: sun50i-h616: spi1 cs1 pin
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 345d941f3e76..90e55a6aef1d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -408,6 +408,12 @@ spi1_cs0_pin: spi1-cs0-pin {
+ 				function = "spi1";
+ 			};
+ 
++			/omit-if-no-ref/
++			spi1_cs1_pin: spi1-cs1-pin {
++				pins = "PH9";
++				function = "spi1";
++			};
++
+ 			spdif_tx_pin: spdif-tx-pin {
+ 				pins = "PH4";
+ 				function = "spdif";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arch-arm64-dts-allwinner-sun50i-h618-bananapi-m4-zero.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arch-arm64-dts-allwinner-sun50i-h618-bananapi-m4-zero.patch
new file mode 100644
index 000000000000..55e8458c4dca
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arch-arm64-dts-allwinner-sun50i-h618-bananapi-m4-zero.patch
@@ -0,0 +1,309 @@
+From e13a5648e7b0cadac49af05ac7452771253b0f73 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@xxxxx.com>
+Date: Sun, 17 Mar 2024 18:54:24 -0400
+Subject: arch: arm64: dts: allwinner: sun50i-h618-bananapi-m4-zero
+
+Signed-off-by: Patrick Yavitz <pyavitz@xxxxx.com>
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../sun50i-h618-bananapi-m4-zero.dts          | 276 ++++++++++++++++++
+ 2 files changed, 277 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 74a6e5e0d7b3..fd2f4f11e1fb 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -53,6 +53,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts
+new file mode 100644
+index 000000000000..fba5b39cc319
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts
+@@ -0,0 +1,276 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2024 Patrick Yavitz <pyavitz@xxxxx.com>
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "BananaPi M4 Zero";
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h618";
++
++	aliases {
++		ethernet0 = &emac1;
++		serial0 = &uart0;
++		serial5 = &uart5;
++		i2c3 = &i2c3;
++		i2c4 = &i2c4;
++		spi1 = &spi1;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		key-sw3 {
++			label = "sw3";
++			linux,code = <BTN_0>;
++			gpios = <&pio 2 7 GPIO_ACTIVE_LOW>;	/* PC7 */
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			color = <LED_COLOR_ID_RED>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>;	/* PC12 */
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	reg_vcc5v: regulator-5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_usb_vbus: regulator-usb-vbus {
++		/* separate discrete regulator for the USB ports */
++		compatible = "regulator-fixed";
++		regulator-name = "usb-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&reg_vcc5v>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&de {
++	status = "okay";
++};
++
++/* Connected to an on-board RTL8821CU USB WiFi chip. */
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "disabled";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "disabled";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ir_rx_pin>;
++	status = "okay";
++};
++
++&mdio1 {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_dldo1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;	/* PF6 */
++	bus-width = <4>;
++	max-frequency = <50000000>;
++	status = "okay";
++};
++
++&mmc2 {
++	vmmc-supply = <&reg_dldo1>;
++	vqmmc-supply = <&reg_aldo1>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	mmc-hs200-1_8v;
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pc-supply = <&reg_aldo1>;
++	vcc-pf-supply = <&reg_dldo1>;
++	vcc-pg-supply = <&reg_dldo1>;
++	vcc-ph-supply = <&reg_dldo1>;
++	vcc-pi-supply = <&reg_dldo1>;
++};
++
++&r_i2c {
++	status = "okay";
++
++	axp313: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		interrupt-parent = <&pio>;
++
++		vin1-supply = <&reg_vcc5v>;
++		vin2-supply = <&reg_vcc5v>;
++		vin3-supply = <&reg_vcc5v>;
++
++		regulators {
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-1v8-pll";
++			};
++
++			reg_dldo1: dldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc-3v3-io";
++			};
++
++			reg_dcdc1: dcdc1 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <990000>;
++				regulator-name = "vdd-gpu-sys";
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-always-on;
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-name = "vdd-dram";
++			};
++		};
++	};
++};
++
++&spi1 {
++	status = "disabled";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
++
++	spidev@1 {
++		compatible = "rohm,dh2228fv";
++		status = "disabled";
++		reg = <1>;
++		spi-max-frequency = <1000000>;
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	status = "okay";
++};
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart5_pins>;
++	status = "okay";
++};
++
++&usbotg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_usb_vbus>;
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch
new file mode 100644
index 000000000000..e71e405a98ba
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch
@@ -0,0 +1,79 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 23 Jan 2022 16:43:53 +0300
+Subject: arm:arm64:dts: Add leds axp20x charger
+
+---
+ arch/arm/boot/dts/allwinner/axp209.dtsi   | 5 +++++
+ arch/arm/boot/dts/allwinner/axp22x.dtsi   | 5 +++++
+ arch/arm/boot/dts/allwinner/axp81x.dtsi   | 5 +++++
+ arch/arm64/boot/dts/allwinner/axp803.dtsi | 5 +++++
+ 4 files changed, 20 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/axp209.dtsi b/arch/arm/boot/dts/allwinner/axp209.dtsi
+index 469d0f7d5185..bad2b8fcf6b5 100644
+--- a/arch/arm/boot/dts/allwinner/axp209.dtsi
++++ b/arch/arm/boot/dts/allwinner/axp209.dtsi
+@@ -76,6 +76,11 @@ axp_gpio: gpio {
+ 		#gpio-cells = <2>;
+ 	};
+ 
++	axp_led: led {
++		compatible = "x-powers,axp20x-led";
++		status = "disabled";
++	};
++
+ 	battery_power_supply: battery-power {
+ 		compatible = "x-powers,axp209-battery-power-supply";
+ 		status = "disabled";
+diff --git a/arch/arm/boot/dts/allwinner/axp22x.dtsi b/arch/arm/boot/dts/allwinner/axp22x.dtsi
+index f79650afd0a7..91c66b2456e9 100644
+--- a/arch/arm/boot/dts/allwinner/axp22x.dtsi
++++ b/arch/arm/boot/dts/allwinner/axp22x.dtsi
+@@ -62,6 +62,11 @@ axp_adc: adc {
+ 		#io-channel-cells = <1>;
+ 	};
+ 
++	axp_led: led {
++		compatible = "x-powers,axp20x-led";
++		status = "disabled";
++	};
++
+ 	battery_power_supply: battery-power {
+ 		compatible = "x-powers,axp221-battery-power-supply";
+ 		status = "disabled";
+diff --git a/arch/arm/boot/dts/allwinner/axp81x.dtsi b/arch/arm/boot/dts/allwinner/axp81x.dtsi
+index a4b1be159b02..9a432a0dcdab 100644
+--- a/arch/arm/boot/dts/allwinner/axp81x.dtsi
++++ b/arch/arm/boot/dts/allwinner/axp81x.dtsi
+@@ -64,6 +64,11 @@ axp_gpio: gpio {
+ 		#gpio-cells = <2>;
+ 	};
+ 
++	axp_led: led {
++		compatible = "x-powers,axp20x-led";
++		status = "disabled";
++	};
++
+ 	battery_power_supply: battery-power {
+ 		compatible = "x-powers,axp813-battery-power-supply";
+ 		status = "disabled";
+diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi
+index 422be59f5d88..3ad8967a11dd 100644
+--- a/arch/arm64/boot/dts/allwinner/axp803.dtsi
++++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
+@@ -28,6 +28,11 @@ axp_gpio: gpio {
+ 		#gpio-cells = <2>;
+ 	};
+ 
++	axp_led: led {
++		compatible = "x-powers,axp20x-led";
++		status = "disabled";
++	};
++
+ 	battery_power_supply: battery-power {
+ 		compatible = "x-powers,axp803-battery-power-supply",
+ 			     "x-powers,axp813-battery-power-supply";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch
new file mode 100644
index 000000000000..064bc94e87a0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch
@@ -0,0 +1,196 @@
+From 520fc44528976ca1ad51c4c97c4afcc7a4622fd4 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 15:00:36 +0300
+Subject: arm:dts: Add sun8i-h2-plus-nanopi-duo device
+
+---
+ arch/arm/boot/dts/allwinner/Makefile          |   1 +
+ .../allwinner/sun8i-h2-plus-nanopi-duo.dts    | 164 ++++++++++++++++++
+ 2 files changed, 165 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/sun8i-h2-plus-nanopi-duo.dts
+
+diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
+index 7c7fb94d2153..f8ada252119e 100644
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -283,6 +283,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-a83t-tbs-a711.dtb \
+ 	sun8i-h2-plus-bananapi-m2-zero.dtb \
+ 	sun8i-h2-plus-libretech-all-h3-cc.dtb \
++	sun8i-h2-plus-nanopi-duo.dtb \
+ 	sun8i-h2-plus-orangepi-r1.dtb \
+ 	sun8i-h2-plus-orangepi-zero.dtb \
+ 	sun8i-h3-bananapi-m2-plus.dtb \
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-nanopi-duo.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-nanopi-duo.dts
+new file mode 100644
+index 000000000000..2b31b8fddbf3
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-nanopi-duo.dts
+@@ -0,0 +1,164 @@
++/*
++ * adapted by karabek, 2018 , based on
++ *   Copyright (C) 2016 James Pettigrew <james@innovum.com.au>
++ *   Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
++ *
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun8i-h3-nanopi.dtsi"
++#include <dt-bindings/pinctrl/sun4i-a10.h>
++
++/ {
++	model = "FriendlyARM NanoPi DUO";
++	compatible = "friendlyarm,nanopi-duo", "allwinner,sun8i-h3";
++
++	aliases {
++		ethernet0 = &emac;
++		ethernet1 = &xr819;
++	};
++
++	reg_sy8113b: gpio-regulator {
++		compatible = "regulator-gpio";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; 		// 50=4ms check
++
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; 	// PL6 check
++		enable-active-high;
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++
++	reg_vcc_wifi: reg_vcc_wifi {
++		compatible = "regulator-fixed";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-name = "vcc-wifi";
++		gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>;	// PL7 WIFI_POWER_EN
++	        startup-delay-us = <70000>;
++        	enable-active-high;
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_en_npi>;
++		reset-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>;  // PG13 WL_RESTN
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_sy8113b>;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&emac {
++	phy-handle = <&int_mii_phy>;
++	phy-mode = "mii";
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vqmmc-supply = <&reg_vcc_wifi>;
++	vmmc-supply = <&reg_vcc3v3>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	xr819: sdio_wifi@1 {
++		reg = <1>;
++		compatible = "xradio,xr819";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_wake>;
++		interrupt-parent = <&pio>;
++		interrupts = <6 10 IRQ_TYPE_EDGE_RISING>;
++		interrupt-names = "host-wake";
++	};
++};
++
++&mmc1_pins {
++	bias-pull-up;
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&pio {
++	wifi_en_npi: wifi_en_pin {
++		pins = "PG13";
++		function = "gpio_out";
++	};
++	wifi_wake: wifi_wake@0 {
++		pins = "PG10";
++		function = "irq";
++		pull = <SUN4I_PINCTRL_NO_PULL>;
++	};
++};
++
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	/*
++	 * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only
++	 * power up the board; when it's used as OTG port, this VBUS is
++	 * always off even if the board is powered via GPIO pins.
++	 */
++	status = "okay";
++	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch
new file mode 100644
index 000000000000..4c2165991d06
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch
@@ -0,0 +1,257 @@
+From e9e3e7f150cda3927ce140759d5623335c2c3313 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 15:23:33 +0300
+Subject: arm:dts: Add sun8i-h2-plus-sunvell-r69 device
+
+---
+ arch/arm/boot/dts/allwinner/Makefile          |   1 +
+ .../allwinner/sun8i-h2-plus-sunvell-r69.dts   | 225 ++++++++++++++++++
+ 2 files changed, 226 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/sun8i-h2-plus-sunvell-r69.dts
+
+diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
+index f8ada252119e..5f437f5971fd 100644
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -286,6 +286,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-h2-plus-nanopi-duo.dtb \
+ 	sun8i-h2-plus-orangepi-r1.dtb \
+ 	sun8i-h2-plus-orangepi-zero.dtb \
++	sun8i-h2-plus-sunvell-r69.dtb \
+ 	sun8i-h3-bananapi-m2-plus.dtb \
+ 	sun8i-h3-bananapi-m2-plus-v1.2.dtb \
+ 	sun8i-h3-beelink-x2.dtb \
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-sunvell-r69.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-sunvell-r69.dts
+new file mode 100644
+index 000000000000..bb0c2f72b723
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-sunvell-r69.dts
+@@ -0,0 +1,225 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Based original Sunvell R69 FEX file (2019 karabek)
++ */
++
++/dts-v1/;
++#include "sun8i-h3.dtsi"
++#include "sunxi-common-regulators.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
++
++/ {
++	model = "Sunvell R69";
++	compatible = "sunvell,sunvell-r69", "allwinner,sun8i-h2-plus";
++
++	aliases {
++		ethernet0 = &emac;
++		ethernet1 = &xr819;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
++
++		pwr_led {
++			label = "sunvell-r69:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
++		};
++
++		status_led {
++			label = "sunvell-r69:blue:status";
++			gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	reg_vdd_cpux: vdd-cpux-regulator {
++		compatible = "regulator-gpio";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>;		/* 4ms */
++
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;	/* PL6 */
++		enable-active-high;
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++
++	reg_vcc_wifi: reg_vcc_wifi {
++		compatible = "regulator-fixed";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-name = "vcc-wifi";
++		gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>;
++	        startup-delay-us = <70000>;
++		enable-active-high;
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 0 GPIO_ACTIVE_LOW>;
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
++&de {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&emac {
++	phy-handle = <&int_mii_phy>;
++	phy-mode = "mii";
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&r_ir_rx_pin>;		/* <&r_ir_rx_pin> */
++	status = "okay";
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc_wifi>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	xr819: sdio_wifi@1 {
++		reg = <1>;
++		compatible = "xradio,xr819";
++		interrupt-parent = <&pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_RISING>;
++		interrupt-names = "host-wake";
++	};
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_8bit_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&mmc2_8bit_pins {
++	/* Increase current from 30mA to 40mA for DDR eMMC */
++	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&pio {
++	leds_opc: led_pins {
++		pins = "PA15";
++		function = "gpio_out";
++	};
++};
++
++&r_pio {
++	leds_r_opc: led_pins {
++		pins = "PL10";
++		function = "gpio_out";
++	};
++};
++
++&reg_usb0_vbus {
++	gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>;	/* PL2 */
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>;
++	status = "disabled";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pins>;
++	status = "disabled";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pins>;
++	status = "disabled";
++};
++
++&usb_otg {
++	dr_mode = "host";
++	status = "okay";
++};
++
++&usbphy {
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch
new file mode 100644
index 000000000000..22c9ffac4f77
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch
@@ -0,0 +1,38 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 14:46:11 +0300
+Subject: arm:dts: a10-cubiebord a20-cubietruck green LED mmc0 default-trigger
+
+---
+ arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts | 2 +-
+ arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts
+index 0645d6064235..f97b53c4438c 100644
+--- a/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts
++++ b/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts
+@@ -83,7 +83,7 @@ led-0 {
+ 		led-1 {
+ 			label = "cubieboard:green:usr";
+ 			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */
+-			linux,default-trigger = "heartbeat";
++			linux,default-trigger = "mmc0";
+ 		};
+ 	};
+ };
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+index 525cb7fcca79..df428f29b82f 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+@@ -93,6 +93,7 @@ led-2 {
+ 		led-3 {
+ 			label = "cubietruck:green:usr";
+ 			gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "mmc0";
+ 		};
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch
new file mode 100644
index 000000000000..0554c988fe11
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch
@@ -0,0 +1,86 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 13:18:28 +0300
+Subject: arm:dts: a20-orangepi and mini fix phy-mode, hdmi
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts |  2 +-
+ arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts      | 31 +++++++++-
+ 2 files changed, 31 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts
+index 84efa01e7cba..fc87309aec4a 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts
+@@ -121,7 +121,7 @@ &gmac {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&gmac_rgmii_pins>;
+ 	phy-handle = <&phy1>;
+-	phy-mode = "rgmii";
++	phy-mode = "rgmii-id";
+ 	phy-supply = <&reg_gmac_3v3>;
+ 	status = "okay";
+ };
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts
+index 5d77f1d9818f..0c760b0a51c0 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts
+@@ -61,6 +61,17 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -85,6 +96,14 @@ &ahci {
+ 	status = "okay";
+ };
+ 
++&codec {
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+@@ -97,11 +116,21 @@ &gmac {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&gmac_rgmii_pins>;
+ 	phy-handle = <&phy1>;
+-	phy-mode = "rgmii";
++	phy-mode = "rgmii-id";
+ 	phy-supply = <&reg_gmac_3v3>;
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch
new file mode 100644
index 000000000000..ad81ccf01ee7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch
@@ -0,0 +1,80 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 15:34:01 +0300
+Subject: arm:dts: h3-nanopi-neo Add regulator, leds, mmc2
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts | 57 ++++++++++
+ 1 file changed, 57 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts
+index df71fab3cf4e..032849663443 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts
+@@ -49,6 +49,63 @@ / {
+ 	aliases {
+ 		ethernet0 = &emac;
+ 	};
++
++	/* Warning: sunxi-5.18:
++	 * The leds node is present in the sun8i-h3-nanopi.dtsi file
++	 * You will have to fix this situation yourself
++	 */
++	leds {
++		compatible = "gpio-leds";
++
++		pwr {
++			label = "nanopi:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
++			linux,default-trigger = "default-on";
++		};
++
++		status {
++			label = "nanopi:green:status";
++			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	vdd_cpux: gpio-regulator {
++		compatible = "regulator-gpio";
++		pinctrl-names = "default";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpux>;
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_8bit_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&mmc2_8bit_pins {
++	/* Increase drive strength for DDR modes */
++	drive-strength = <40>;
++	/* eMMC is missing pull-ups */
++	bias-pull-up;
+ };
+ 
+ &ehci0 {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch
new file mode 100644
index 000000000000..21f4aadb406f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch
@@ -0,0 +1,196 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 15:45:43 +0300
+Subject: arm:dts: h3-nanopi-neo-air Add regulator camera wifi bluetooth otg
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts | 153 ++++++++++
+ 1 file changed, 153 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts
+index 9e1a33f94cad..bff96ae65469 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts
+@@ -70,12 +70,92 @@ led-0 {
+ 		led-1 {
+ 			label = "nanopi:blue:status";
+ 			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
++			linux,default-trigger = "heartbeat";
+ 		};
+ 	};
+ 
++	vdd_cpux: gpio-regulator {
++		compatible = "regulator-gpio";
++		pinctrl-names = "default";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++
+ 	wifi_pwrseq: wifi_pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_en_npi>;
+ 		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++		post-power-on-delay-ms = <200>;
++	};
++
++	rfkill_bt {
++		compatible = "rfkill-gpio";
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_pwr_pin>;
++		reset-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++		clocks = <&osc32k>;
++		clock-frequency = <32768>;
++		rfkill-name = "sunxi-bt";
++		rfkill-type = "bluetooth";
++	};
++
++	cam_xclk: cam-xclk {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		clock-frequency = <24000000>;
++		clock-output-names = "cam-xclk";
++	};
++
++	reg_cam_avdd: cam-avdd {
++		compatible = "regulator-fixed";
++		regulator-name = "cam500b-avdd";
++		regulator-min-microvolt = <2800000>;
++		regulator-max-microvolt = <2800000>;
++		vin-supply = <&reg_vcc3v3>;
++	};
++
++	reg_cam_dovdd: cam-dovdd {
++		compatible = "regulator-fixed";
++		regulator-name = "cam500b-dovdd";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&reg_vcc3v3>;
++	};
++
++	reg_cam_dvdd: cam-dvdd {
++		compatible = "regulator-fixed";
++		regulator-name = "cam500b-dvdd";
++		regulator-min-microvolt = <1500000>;
++		regulator-max-microvolt = <1500000>;
++		vin-supply = <&reg_vcc3v3>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpux>;
++};
++
++&pio {
++	bt_pwr_pin: bt_pwr_pin@0 {
++		pins = "PG13";
++		function = "gpio_out";
++	};
++};
++
++&r_pio {
++	wifi_en_npi: wifi_en_pin {
++		pins = "PL7";
++		function = "gpio_out";
+ 	};
+ };
+ 
+@@ -110,6 +190,74 @@ &mmc2 {
+ 	vqmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <8>;
+ 	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&mmc2_8bit_pins {
++	/* Increase drive strength for DDR modes */
++	drive-strength = <40>;
++	/* eMMC is missing pull-ups */
++	bias-pull-up;
++};
++
++&csi {
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		/* Parallel bus endpoint */
++		csi_from_ov5640: endpoint {
++			remote-endpoint = <&ov5640_to_csi>;
++			bus-width = <8>;
++			data-shift = <2>;
++			hsync-active = <1>; /* Active high */
++			vsync-active = <0>; /* Active low */
++			data-active = <1>;  /* Active high */
++			pclk-sample = <1>;  /* Rising */
++		};
++	};
++};
++
++&i2c2 {
++	status = "okay";
++	ov5640: camera@3c {
++		compatible = "ovti,ov5640";
++		reg = <0x3c>;
++		clocks = <&cam_xclk>;
++		clock-names = "xclk";
++
++		reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>;
++		powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>;
++		AVDD-supply = <&reg_cam_avdd>;
++		DOVDD-supply = <&reg_cam_dovdd>;
++		DVDD-supply = <&reg_cam_dvdd>;
++
++		port {
++			ov5640_to_csi: endpoint {
++				remote-endpoint = <&csi_from_ov5640>;
++				bus-width = <8>;
++				data-shift = <2>;
++				hsync-active = <1>; /* Active high */
++				vsync-active = <0>; /* Active low */
++				data-active = <1>;  /* Active high */
++				pclk-sample = <1>;  /* Rising */
++			};
++		};
++	};
++};
++
++&i2c2_pins {
++	bias-pull-up;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ohci0 {
+ 	status = "okay";
+ };
+ 
+@@ -137,6 +285,11 @@ bluetooth {
+ 	};
+ };
+ 
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
+ &usbphy {
+ 	/* USB VBUS is always on */
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch
new file mode 100644
index 000000000000..479d423b635d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch
@@ -0,0 +1,59 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 18:23:18 +0300
+Subject: arm:dts: h3-orangepi-2 Add regulator vdd cpu
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts | 29 ++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
+index 2b5890327a47..bc20c44d1c22 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
+@@ -124,6 +124,10 @@ &de {
+ 	status = "okay";
+ };
+ 
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+@@ -178,6 +182,31 @@ rtl8189: sdio_wifi@1 {
+ 	};
+ };
+ 
++&r_i2c {
++	status = "okay";
++
++	reg_vdd_cpux: regulator@65 {
++		compatible = "silergy,sy8106a";
++		reg = <0x65>;
++		regulator-name = "vdd-cpux";
++		silergy,fixed-microvolt = <1200000>;
++		/*
++		 * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
++		 * however both the Armbian DVFS table and the official one
++		 * have operating points with voltage under 1.1V, and both
++		 * DVFS table are known to work properly at the lowest
++		 * operating point.
++		 *
++		 * Use 1.0V as the minimum voltage instead.
++		 */
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
+ &reg_usb1_vbus {
+ 	gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch
new file mode 100644
index 000000000000..522f833f5c90
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch
@@ -0,0 +1,4964 @@
+From 88e42e5bc65e62fe8175fad57223b6f1d94e6d2e Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 12:54:05 +0300
+Subject: arm:dts:overlay Add Overlays for sunxi
+
+---
+ arch/arm/boot/dts/allwinner/Makefile          |   2 +
+ arch/arm/boot/dts/allwinner/overlay/Makefile  |  97 +++++
+ .../overlay/README.sun4i-a10-overlays         | 278 ++++++++++++++
+ .../overlay/README.sun5i-a13-overlays         | 172 +++++++++
+ .../overlay/README.sun7i-a20-overlays         | 348 ++++++++++++++++++
+ .../overlay/README.sun8i-h3-overlays          | 250 +++++++++++++
+ .../overlay/sun4i-a10-analog-codec.dtso       |  13 +
+ .../dts/allwinner/overlay/sun4i-a10-can.dtso  |  15 +
+ .../allwinner/overlay/sun4i-a10-fixup.scr-cmd | 124 +++++++
+ .../dts/allwinner/overlay/sun4i-a10-i2c1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun4i-a10-i2c2.dtso |  22 ++
+ .../dts/allwinner/overlay/sun4i-a10-nand.dtso | 103 ++++++
+ .../allwinner/overlay/sun4i-a10-pps-gpio.dtso |  29 ++
+ .../dts/allwinner/overlay/sun4i-a10-pwm.dtso  |  15 +
+ .../overlay/sun4i-a10-spdif-out.dtso          |  38 ++
+ .../overlay/sun4i-a10-spi-jedec-nor.dtso      |  57 +++
+ .../overlay/sun4i-a10-spi-spidev.dtso         |  57 +++
+ .../dts/allwinner/overlay/sun4i-a10-spi0.dtso |  23 ++
+ .../dts/allwinner/overlay/sun4i-a10-spi1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun4i-a10-spi2.dtso |  23 ++
+ .../allwinner/overlay/sun4i-a10-uart2.dtso    |  37 ++
+ .../allwinner/overlay/sun4i-a10-uart3.dtso    |  47 +++
+ .../allwinner/overlay/sun4i-a10-uart4.dtso    |  37 ++
+ .../allwinner/overlay/sun4i-a10-uart5.dtso    |  32 ++
+ .../allwinner/overlay/sun4i-a10-uart6.dtso    |  32 ++
+ .../allwinner/overlay/sun4i-a10-uart7.dtso    |  32 ++
+ .../allwinner/overlay/sun4i-a10-w1-gpio.dtso  |  29 ++
+ .../overlay/sun5i-a13-analog-codec.dtso       |  13 +
+ .../allwinner/overlay/sun5i-a13-fixup.scr-cmd |  48 +++
+ .../dts/allwinner/overlay/sun5i-a13-i2c1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun5i-a13-i2c2.dtso |  22 ++
+ .../dts/allwinner/overlay/sun5i-a13-nand.dtso |  60 +++
+ .../dts/allwinner/overlay/sun5i-a13-pwm.dtso  |  15 +
+ .../overlay/sun5i-a13-spi-jedec-nor.dtso      |  57 +++
+ .../overlay/sun5i-a13-spi-spidev.dtso         |  57 +++
+ .../dts/allwinner/overlay/sun5i-a13-spi0.dtso |  38 ++
+ .../dts/allwinner/overlay/sun5i-a13-spi1.dtso |  39 ++
+ .../dts/allwinner/overlay/sun5i-a13-spi2.dtso |  22 ++
+ .../allwinner/overlay/sun5i-a13-uart0.dtso    |  32 ++
+ .../allwinner/overlay/sun5i-a13-uart1.dtso    |  22 ++
+ .../allwinner/overlay/sun5i-a13-uart2.dtso    |  22 ++
+ .../allwinner/overlay/sun5i-a13-uart3.dtso    |  22 ++
+ .../overlay/sun7i-a20-analog-codec.dtso       |  13 +
+ .../dts/allwinner/overlay/sun7i-a20-can.dtso  |  15 +
+ .../allwinner/overlay/sun7i-a20-fixup.scr-cmd | 143 +++++++
+ .../dts/allwinner/overlay/sun7i-a20-i2c1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun7i-a20-i2c2.dtso |  22 ++
+ .../dts/allwinner/overlay/sun7i-a20-i2c3.dtso |  22 ++
+ .../dts/allwinner/overlay/sun7i-a20-i2c4.dtso |  32 ++
+ .../dts/allwinner/overlay/sun7i-a20-i2s0.dtso |  25 ++
+ .../dts/allwinner/overlay/sun7i-a20-i2s1.dtso |  25 ++
+ .../dts/allwinner/overlay/sun7i-a20-mmc2.dtso |  18 +
+ .../dts/allwinner/overlay/sun7i-a20-nand.dtso | 103 ++++++
+ .../allwinner/overlay/sun7i-a20-pps-gpio.dtso |  29 ++
+ .../dts/allwinner/overlay/sun7i-a20-pwm.dtso  |  15 +
+ .../overlay/sun7i-a20-spdif-out.dtso          |  38 ++
+ .../overlay/sun7i-a20-spi-add-cs1.dtso        |  16 +
+ .../overlay/sun7i-a20-spi-jedec-nor.dtso      |  57 +++
+ .../overlay/sun7i-a20-spi-spidev.dtso         |  57 +++
+ .../dts/allwinner/overlay/sun7i-a20-spi0.dtso |  23 ++
+ .../dts/allwinner/overlay/sun7i-a20-spi1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun7i-a20-spi2.dtso |  23 ++
+ .../allwinner/overlay/sun7i-a20-uart2.dtso    |  32 ++
+ .../allwinner/overlay/sun7i-a20-uart3.dtso    |  42 +++
+ .../allwinner/overlay/sun7i-a20-uart4.dtso    |  22 ++
+ .../allwinner/overlay/sun7i-a20-uart5.dtso    |  22 ++
+ .../allwinner/overlay/sun7i-a20-uart6.dtso    |  22 ++
+ .../allwinner/overlay/sun7i-a20-uart7.dtso    |  22 ++
+ .../allwinner/overlay/sun7i-a20-w1-gpio.dtso  |  29 ++
+ .../overlay/sun8i-h3-analog-codec.dtso        |  17 +
+ .../dts/allwinner/overlay/sun8i-h3-cir.dtso   |  15 +
+ .../allwinner/overlay/sun8i-h3-fixup.scr-cmd  | 110 ++++++
+ .../dts/allwinner/overlay/sun8i-h3-i2c0.dtso  |  20 +
+ .../dts/allwinner/overlay/sun8i-h3-i2c1.dtso  |  20 +
+ .../dts/allwinner/overlay/sun8i-h3-i2c2.dtso  |  20 +
+ .../allwinner/overlay/sun8i-h3-pps-gpio.dtso  |  29 ++
+ .../dts/allwinner/overlay/sun8i-h3-pwm.dtso   |  39 ++
+ .../allwinner/overlay/sun8i-h3-spdif-out.dtso |  38 ++
+ .../overlay/sun8i-h3-spi-add-cs1.dtso         |  41 +++
+ .../overlay/sun8i-h3-spi-jedec-nor.dtso       |  42 +++
+ .../overlay/sun8i-h3-spi-spidev.dtso          |  42 +++
+ .../dts/allwinner/overlay/sun8i-h3-uart1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun8i-h3-uart2.dtso |  22 ++
+ .../dts/allwinner/overlay/sun8i-h3-uart3.dtso |  22 ++
+ .../allwinner/overlay/sun8i-h3-usbhost0.dtso  |  27 ++
+ .../allwinner/overlay/sun8i-h3-usbhost1.dtso  |  27 ++
+ .../allwinner/overlay/sun8i-h3-usbhost2.dtso  |  27 ++
+ .../allwinner/overlay/sun8i-h3-usbhost3.dtso  |  27 ++
+ .../allwinner/overlay/sun8i-h3-w1-gpio.dtso   |  29 ++
+ .../dts/allwinner/overlay/sun8i-r40-i2c2.dtso |  20 +
+ .../dts/allwinner/overlay/sun8i-r40-i2c3.dtso |  20 +
+ .../overlay/sun8i-r40-spi-spidev0.dtso        |  27 ++
+ .../overlay/sun8i-r40-spi-spidev1.dtso        |  27 ++
+ .../allwinner/overlay/sun8i-r40-uart2.dtso    |  22 ++
+ .../allwinner/overlay/sun8i-r40-uart4.dtso    |  22 ++
+ .../allwinner/overlay/sun8i-r40-uart5.dtso    |  22 ++
+ .../allwinner/overlay/sun8i-r40-uart7.dtso    |  22 ++
+ 97 files changed, 4176 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/Makefile
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/README.sun4i-a10-overlays
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/README.sun5i-a13-overlays
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/README.sun7i-a20-overlays
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-analog-codec.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-can.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-fixup.scr-cmd
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-nand.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pps-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pwm.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spdif-out.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-jedec-nor.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-spidev.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart4.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart5.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart6.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart7.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-w1-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-analog-codec.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-fixup.scr-cmd
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-nand.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-pwm.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-jedec-nor.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-spidev.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-analog-codec.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-can.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-fixup.scr-cmd
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c4.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-mmc2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-nand.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pps-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pwm.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spdif-out.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-add-cs1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-jedec-nor.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-spidev.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart4.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart5.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart6.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart7.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-w1-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-analog-codec.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cir.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-fixup.scr-cmd
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pps-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pwm.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spdif-out.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-add-cs1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-jedec-nor.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-spidev.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-w1-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart4.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart5.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart7.dtso
+
+diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
+index 5f437f5971fd..016e23c1dc1c 100644
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -336,3 +336,5 @@ dtb-$(CONFIG_MACH_SUNIV) += \
+ 	suniv-f1c100s-licheepi-nano.dtb \
+ 	suniv-f1c200s-lctech-pi.dtb \
+ 	suniv-f1c200s-popstick-v1.1.dtb
++
++subdir-y	:= overlay
+diff --git a/arch/arm/boot/dts/allwinner/overlay/Makefile b/arch/arm/boot/dts/allwinner/overlay/Makefile
+new file mode 100644
+index 000000000000..0c47e8fda8fc
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/Makefile
+@@ -0,0 +1,97 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_MACH_SUN4I) += \
++	sun4i-a10-analog-codec.dtbo \
++	sun4i-a10-can.dtbo \
++	sun4i-a10-i2c1.dtbo \
++	sun4i-a10-i2c2.dtbo \
++	sun4i-a10-nand.dtbo \
++	sun4i-a10-pps-gpio.dtbo \
++	sun4i-a10-pwm.dtbo \
++	sun4i-a10-spdif-out.dtbo \
++	sun4i-a10-spi-jedec-nor.dtbo \
++	sun4i-a10-spi-spidev.dtbo \
++	sun4i-a10-uart2.dtbo \
++	sun4i-a10-uart3.dtbo \
++	sun4i-a10-uart4.dtbo \
++	sun4i-a10-uart5.dtbo \
++	sun4i-a10-uart6.dtbo \
++	sun4i-a10-uart7.dtbo \
++	sun4i-a10-w1-gpio.dtbo
++
++dtb-$(CONFIG_MACH_SUN5I) += \
++	sun5i-a13-analog-codec.dtbo \
++	sun5i-a13-i2c1.dtbo \
++	sun5i-a13-i2c2.dtbo \
++	sun5i-a13-nand.dtbo \
++	sun5i-a13-pwm.dtbo \
++	sun5i-a13-spi0.dtbo \
++	sun5i-a13-spi1.dtbo \
++	sun5i-a13-spi2.dtbo \
++	sun5i-a13-spi-jedec-nor.dtbo \
++	sun5i-a13-spi-spidev.dtbo \
++	sun5i-a13-uart0.dtbo \
++	sun5i-a13-uart1.dtbo \
++	sun5i-a13-uart2.dtbo \
++	sun5i-a13-uart3.dtbo
++
++dtb-$(CONFIG_MACH_SUN7I) += \
++	sun7i-a20-analog-codec.dtbo \
++	sun7i-a20-can.dtbo \
++	sun7i-a20-i2c1.dtbo \
++	sun7i-a20-i2c2.dtbo \
++	sun7i-a20-i2c3.dtbo \
++	sun7i-a20-i2c4.dtbo \
++	sun7i-a20-mmc2.dtbo \
++	sun7i-a20-nand.dtbo \
++	sun7i-a20-pps-gpio.dtbo \
++	sun7i-a20-pwm.dtbo \
++	sun7i-a20-spdif-out.dtbo \
++	sun7i-a20-spi-add-cs1.dtbo \
++	sun7i-a20-spi-jedec-nor.dtbo \
++	sun7i-a20-spi-spidev.dtbo \
++	sun7i-a20-uart2.dtbo \
++	sun7i-a20-uart3.dtbo \
++	sun7i-a20-uart4.dtbo \
++	sun7i-a20-uart5.dtbo \
++	sun7i-a20-uart6.dtbo \
++	sun7i-a20-uart7.dtbo \
++	sun7i-a20-w1-gpio.dtbo
++
++dtb-$(CONFIG_MACH_SUN8I) += \
++	sun8i-h3-analog-codec.dtbo \
++	sun8i-h3-cir.dtbo \
++	sun8i-h3-i2c0.dtbo \
++	sun8i-h3-i2c1.dtbo \
++	sun8i-h3-i2c2.dtbo \
++	sun8i-h3-pps-gpio.dtbo \
++	sun8i-h3-pwm.dtbo \
++	sun8i-h3-spdif-out.dtbo \
++	sun8i-h3-spi-add-cs1.dtbo \
++	sun8i-h3-spi-jedec-nor.dtbo \
++	sun8i-h3-spi-spidev.dtbo \
++	sun8i-h3-uart1.dtbo \
++	sun8i-h3-uart2.dtbo \
++	sun8i-h3-uart3.dtbo \
++	sun8i-h3-usbhost0.dtbo \
++	sun8i-h3-usbhost1.dtbo \
++	sun8i-h3-usbhost2.dtbo \
++	sun8i-h3-usbhost3.dtbo \
++	sun8i-h3-w1-gpio.dtbo \
++	sun8i-r40-i2c2.dtbo \
++	sun8i-r40-i2c3.dtbo \
++	sun8i-r40-spi-spidev0.dtbo \
++	sun8i-r40-spi-spidev1.dtbo \
++	sun8i-r40-uart2.dtbo \
++	sun8i-r40-uart4.dtbo \
++	sun8i-r40-uart5.dtbo \
++	sun8i-r40-uart7.dtbo
++
++scr-$(CONFIG_MACH_SUN4I) += sun4i-a10-fixup.scr
++scr-$(CONFIG_MACH_SUN5I) += sun5i-a13-fixup.scr
++scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr
++scr-$(CONFIG_MACH_SUN8I) += sun8i-h3-fixup.scr
++
++dtbotxt-$(CONFIG_MACH_SUN4I) += README.sun4i-a10-overlays
++dtbotxt-$(CONFIG_MACH_SUN5I) += README.sun5i-a13-overlays
++dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays
++dtbotxt-$(CONFIG_MACH_SUN8I) += README.sun8i-h3-overlays
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun4i-a10-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun4i-a10-overlays
+new file mode 100644
+index 000000000000..e0795f13ddf1
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun4i-a10-overlays
+@@ -0,0 +1,278 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++sun4i-a10 (Allwinner A10)
++
++### Platform details:
++
++Supported pin banks: PB, PC, PD, PE, PG, PH, PI
++
++SPI controller 0 have 2 exposed hardware CS,
++other SPI controllers have only one hardware CS
++Reference: A10 User manual section 17.4.13, A10 datasheet section 5.2
++
++I2C bus 0 is used for the AXP209 PMIC
++
++### Provided overlays:
++
++- analog-codec
++- can
++- i2c1
++- i2c2
++- nand
++- pps-gpio
++- pwm
++- spdif-out
++- spi0
++- spi1
++- spi2
++- spi-jedec-nor
++- spi-spidev
++- uart1
++- uart2
++- uart3
++- uart4
++- uart5
++- uart6
++- uart7
++- w1-gpio
++
++### Overlay details:
++
++### analog-codec
++
++Activates SoC analog codec driver that provides Line Out and Mic In
++functionality
++
++## can
++
++Activates SoC CAN controller
++
++CAN pins (TX, RX): PH20, PH21
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PB18, PB19
++
++### i2c2
++
++Activates TWI/I2C bus 2
++
++I2C2 pins (SCL, SDA): PB20, PB21
++
++### nand
++
++Activates NAND controller
++
++This overlay should not be used until mainline MLC NAND support
++allows using NAND storage reliably
++
++### pps-gpio
++
++Activates pulse-per-second GPIO client
++
++Parameters:
++
++param_pps_pin (pin)
++	Pin PPS source is connected to
++	Optional
++	Default: PI15
++
++param_pps_falling_edge (bool)
++	Assert by falling edge
++	Optional
++	Default: 0
++	When set (to 1), assert is indicated by a falling edge
++		(instead of by a rising edge)
++
++### pwm
++
++Activates hardware PWM controller
++
++PWM pins (PWM0, PWM1): PB2, PI3
++
++Parameters:
++
++param_pwm_pins (string)
++	PWM pins activated with this overlay
++	Optional
++	Default: both
++	Supported values: 0, 1, both
++	If set to 0 only PWM0 can be used,
++		if set to 1 then only PWM1 can be used,
++		if set to both (default), both PWM0 and PWM1 can be used
++
++### spdif-out
++
++Activates SPDIF/Toslink audio output
++
++SPDIF pin: PB13
++
++### spi0
++
++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++
++### spi1
++
++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++
++### spi2
++
++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spi2_bus_pins (char)
++	SPI bus 2 pinmux variant
++	Optional
++	Default: a
++	Supported values: a, b
++	Determines what pins SPI bus 2 is exposed on if SPI 2 is used
++
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate mcp2515 support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
++UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3
++
++Parameters:
++
++param_uart3_pins (char)
++	Determines what pins UART 3 is exposed on
++	Optional
++	Default: a
++	Supported values: a, b
++
++param_uart3_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart4
++
++Activates serial port 4 (/dev/ttyS4)
++
++UART 4 pins a (TX, RX): PG10, PG11
++UART 4 pins b (TX, RX): PH4, PH5
++
++Parameters:
++
++param_uart4_pins (char)
++	Determines what pins UART 4 is exposed on
++	Optional
++	Default: a
++	Supported values: a, b
++
++### uart 5
++
++Activates serial port 5 (/dev/ttyS5)
++
++UART 5 pins (TX, RX): PH6, PH7
++
++### uart 6
++
++Activates serial port 6 (/dev/ttyS6)
++
++UART 6 pins (TX, RX): PI12, PI13
++
++### uart 7
++
++Activates serial port 7 (/dev/ttyS7)
++
++UART 7 pins (TX, RX): PI20, PI21
++
++### w1-gpio
++
++Activates 1-Wire GPIO master
++Requires an external pull-up resistor on the data pin
++or enabling the internal pull-up
++
++Parameters:
++
++param_w1_pin (pin)
++	Data pin for 1-Wire master
++	Optional
++	Default: PI15
++
++param_w1_pin_int_pullup (bool)
++	Enable internal pull-up for the data pin
++	Optional
++	Default: 0
++	Set to 1 to enable the pull-up
++	This option should not be used with multiple sensors or long wires -
++		please use external pull-up resistor instead
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun5i-a13-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun5i-a13-overlays
+new file mode 100644
+index 000000000000..9f9653f09573
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun5i-a13-overlays
+@@ -0,0 +1,172 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++sun5i-a13 (Allwinner A13)
++
++### Platform details:
++
++I2C bus 0 is used for the AXP209 PMIC
++
++### Provided overlays:
++
++- analog-codec
++- i2c1
++- i2c2
++- nand
++- pwm
++- spi0
++- spi1
++- spi2
++- spi-jedec-nor
++- spi-spidev
++- uart0
++- uart1
++- uart2
++- uart3
++
++### Overlay details:
++
++### analog-codec
++
++Activates SoC analog codec driver that provides HP Out and Mic In
++functionality
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PB15, PB16
++
++### i2c2
++
++Activates TWI/I2C bus 2
++
++I2C2 pins (SCL, SDA): PB17, PB18
++
++### nand
++
++Activates NAND controller
++
++This overlay should not be used until mainline MLC NAND support
++allows using NAND storage reliably
++
++### pwm
++
++Activates hardware PWM controller
++
++PWM pins (PWM0): PB2
++
++### spi0
++
++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
++
++### spi1
++
++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
++
++### spi2
++
++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate mcp2515 support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart 0
++
++Activates serial port 0 (/dev/ttyS0)
++
++UART 0 pins (TX, RX): PF2, PF4
++
++### uart 1
++
++Activates serial port 1 (/dev/ttyS1)
++
++UART 1 pins a (TX, RX): PE10, PE11
++UART 1 pins b (TX, RX): PG3, PG4
++
++Parameters:
++
++param_uart1_pins (char)
++	UART 1 pinmux variant
++	Optional
++	Default: a
++	Supported values: a, b
++	Determines what pins UART 1 is exposed on if UART 1 is used
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins (TX, RX, RTS, CTS): PG9, PG10, PG12, PG11
++
++Parameters:
++
++param_uart3_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun7i-a20-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun7i-a20-overlays
+new file mode 100644
+index 000000000000..362f87961135
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun7i-a20-overlays
+@@ -0,0 +1,348 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++sun7i-a20 (Allwinner A20)
++
++### Platform details:
++
++Supported pin banks: PB, PC, PD, PE, PG, PH, PI
++
++SPI controller 0 have 2 exposed hardware CS,
++other SPI controllers have only one hardware CS
++Reference: A20 Datasheet sections 6.3.5.1, 1.19.2
++
++I2C bus 0 is used for the AXP209 PMIC
++
++### Provided overlays:
++
++- analog-codec
++- can
++- i2c1
++- i2c2
++- i2c3
++- i2c4
++- i2s0
++- i2s1
++- mmc2
++- nand
++- pps-gpio
++- pwm
++- spdif-out
++- spi0
++- spi1
++- spi2
++- spi-add-cs1
++- spi-jedec-nor
++- spi-spidev
++- uart1
++- uart2
++- uart3
++- uart4
++- uart5
++- uart6
++- uart7
++- w1-gpio
++
++### Overlay details:
++
++### analog-codec
++
++Activates SoC analog codec driver that provides Line Out and Mic In
++functionality
++
++## can
++
++Activates SoC CAN controller
++
++CAN pins (TX, RX): PH20, PH21
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PB18, PB19
++
++### i2c2
++
++Activates TWI/I2C bus 2
++
++I2C2 pins (SCL, SDA): PB20, PB21
++
++### i2c3
++
++Activates TWI/I2C bus 3
++
++I2C3 pins (SCL, SDA): PI0, PI1
++
++### i2c4
++
++Activates TWI/I2C bus 4
++
++I2C4 pins (SCL, SDA): PI2, PI3
++
++### i2s0
++
++Activates SoC I2S controller 0
++
++I2S0 pins (MCLK, BCLK, LRCK, DO0, DO1, DO2, DO3, DI): PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12
++
++### i2s1
++
++Activates SoC I2S controller 1
++
++I2S1 pins (MCLK, BCLK, LRCK, DO, DI): PA9, PA14, PA15, PA16, PA17
++
++### mmc2
++
++Activates SD/MMC controller 2. To be used on boards with second SD slot, eMMC
++or tSD instead of NAND storage.
++
++MMC2 pins: PC6, PC7, PC8, PC9, PC10, PC11
++
++Parameters:
++
++param_mmc2_cd_pin (pin)
++	SD/MMC 2 card detect pin
++	Optional
++	Default: PH0
++
++param_mmc2_non_removable (bool)
++	Option for non-removable storage options on MMC 2 controller (eMMC or tSD)
++	Optional
++	Default: 0
++	Set to 1 to use this option
++
++### nand
++
++Activates NAND controller
++
++This overlay should not be used until mainline MLC NAND support
++allows using NAND storage reliably
++
++### pps-gpio
++
++Activates pulse-per-second GPIO client
++
++Parameters:
++
++param_pps_pin (pin)
++	Pin PPS source is connected to
++	Optional
++	Default: PI15
++
++param_pps_falling_edge (bool)
++	Assert by falling edge
++	Optional
++	Default: 0
++	When set (to 1), assert is indicated by a falling edge
++		(instead of by a rising edge)
++
++### pwm
++
++Activates hardware PWM controller
++
++PWM pins (PWM0, PWM1): PB2, PI3
++
++Parameters:
++
++param_pwm_pins (string)
++	PWM pins activated with this overlay
++	Optional
++	Default: both
++	Supported values: 0, 1, both
++	If set to 0 only PWM0 can be used,
++		if set to 1 then only PWM1 can be used,
++		if set to both (default), both PWM0 and PWM1 can be used
++
++### spdif-out
++
++Activates SPDIF/Toslink audio output
++
++SPDIF pin: PB13
++
++### spi0
++
++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++
++### spi1
++
++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++
++### spi2
++
++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spi2_bus_pins (char)
++	SPI bus 2 pinmux variant
++	Optional
++	Default: a
++	Supported values: a, b
++	Determines what pins SPI bus 2 is exposed on if SPI 2 is used
++
++### spi-add-cs1
++
++Activates SPI chip select 1 on SPI controller 0
++This overlay is required for using chip select 1 with other SPI overlays
++
++SPI 0 CS1 pin: PI14
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spinor_spi_cs (int)
++	SPI chip select number for SPI NOR connected to SPI bus 0
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate mcp2515 support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spidev_spi_cs (int)
++	SPI chip select number for SPIdev on SPI bus 0
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
++UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3
++
++Parameters:
++
++param_uart3_pins (char)
++	Determines what pins UART 3 is exposed on
++	Optional
++	Default: a
++	Supported values: a, b
++
++param_uart3_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart4
++
++Activates serial port 4 (/dev/ttyS4)
++
++UART 4 pins a (TX, RX): PG10, PG11
++UART 4 pins b (TX, RX): PH4, PH5
++
++Parameters:
++
++param_uart4_pins (char)
++	Determines what pins UART 4 is exposed on
++	Optional
++	Default: a
++	Supported values: a, b
++
++### uart 5
++
++Activates serial port 5 (/dev/ttyS5)
++
++UART 5 pins (TX, RX): PH6, PH7
++
++### uart 6
++
++Activates serial port 6 (/dev/ttyS6)
++
++UART 6 pins (TX, RX): PI12, PI13
++
++### uart 7
++
++Activates serial port 7 (/dev/ttyS7)
++
++UART 7 pins (TX, RX): PI20, PI21
++
++### w1-gpio
++
++Activates 1-Wire GPIO master
++Requires an external pull-up resistor on the data pin
++or enabling the internal pull-up
++
++Parameters:
++
++param_w1_pin (pin)
++	Data pin for 1-Wire master
++	Optional
++	Default: PI15
++
++param_w1_pin_int_pullup (bool)
++	Enable internal pull-up for the data pin
++	Optional
++	Default: 0
++	Set to 1 to enable the pull-up
++	This option should not be used with multiple sensors or long wires -
++		please use external pull-up resistor instead
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+new file mode 100644
+index 000000000000..302973491051
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+@@ -0,0 +1,250 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++sun8i-h3 (Allwinner H3)
++
++### Platform details:
++
++Supported pin banks: PA, PC, PD, PG
++
++Both SPI controllers have only one hardware CS pin exposed,
++adding fixed software (GPIO) chip selects is possible with a separate overlay
++
++### Provided overlays:
++
++- analog-codec
++- cir
++- i2c0
++- i2c1
++- i2c2
++- pps-gpio
++- pwm
++- spdif-out
++- spi-add-cs1
++- spi-jedec-nor
++- spi-spidev
++- uart1
++- uart2
++- uart3
++- usbhost0
++- usbhost1
++- usbhost2
++- usbhost3
++- w1-gpio
++
++### Overlay details:
++
++### analog-codec
++
++Activates SoC analog codec driver that provides Line Out and Mic In
++functionality
++
++### cir
++
++Activates CIR (Infrared remote) receiver
++
++CIR pin: PL11
++
++### i2c0
++
++Activates TWI/I2C bus 0
++
++I2C0 pins (SCL, SDA): PA11, PA12
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PA18, PA19
++
++### i2c2
++
++Activates TWI/I2C bus 2
++
++I2C2 pins (SCL, SDA): PE12, PE13
++
++On most board this bus is wired to Camera (CSI) socket
++
++### pps-gpio
++
++Activates pulse-per-second GPIO client
++
++Parameters:
++
++param_pps_pin (pin)
++	Pin PPS source is connected to
++	Optional
++	Default: PD14
++
++param_pps_falling_edge (bool)
++	Assert by falling edge
++	Optional
++	Default: 0
++	When set (to 1), assert is indicated by a falling edge
++		(instead of by a rising edge)
++
++### pwm
++
++Activates hardware PWM controller
++
++PWM pin: PA5
++
++Pin PA5 is used as UART0 RX by default, so if this overlay is activated,
++UART0 and kernel console on ttyS0 will be disabled
++
++### spdif-out
++
++Activates SPDIF/Toslink audio output
++
++SPDIF pin: PA17
++
++### spi-add-cs1
++
++Adds support for using SPI chip select 1 with GPIO for both SPI controllers
++Respective GPIO will be claimed only if controller is enabled by another
++overlay
++This overlay is required for using chip select 1 with other SPI overlays
++Due to the u-boot limitations CS1 pin can't be customized by a parameter, but
++it can be changed by using an edited copy of this overlay
++A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO)
++
++SPI 0 pins (CS1): PA21
++SPI 1 pins (CS1): PA10
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1
++
++param_spinor_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate SPIdev support on
++	Required
++	Supported values: 0, 1
++
++param_spidev_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart1
++
++Activates serial port 1 (/dev/ttyS1)
++
++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
++
++Parameters:
++
++param_uart1_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16
++
++Parameters:
++
++param_uart3_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### usbhost0
++
++Activates USB host controller 0
++
++### usbhost1
++
++Activates USB host controller 1
++
++### usbhost2
++
++Activates USB host controller 2
++
++### usbhost3
++
++Activates USB host controller 3
++
++### w1-gpio
++
++Activates 1-Wire GPIO master
++Requires an external pull-up resistor on the data pin
++or enabling the internal pull-up
++
++Parameters:
++
++param_w1_pin (pin)
++	Data pin for 1-Wire master
++	Optional
++	Default: PD14
++
++param_w1_pin_int_pullup (bool)
++	Enable internal pull-up for the data pin
++	Optional
++	Default: 0
++	Set to 1 to enable the pull-up
++	This option should not be used with multiple devices, parasite power setup
++		or long wires -	please use external pull-up resistor instead
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-analog-codec.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-analog-codec.dtso
+new file mode 100644
+index 000000000000..9254e22e0eea
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-analog-codec.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&codec>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-can.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-can.dtso
+new file mode 100644
+index 000000000000..1a9511d1956b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-can.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&can0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&can0_ph_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-fixup.scr-cmd b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-fixup.scr-cmd
+new file mode 100644
+index 000000000000..c5614cb95124
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-fixup.scr-cmd
+@@ -0,0 +1,124 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "B" && setenv tmp_bank 1;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "E" && setenv tmp_bank 4;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6;
++test "${tmp_bank}" = "H" && setenv tmp_bank 7;
++test "${tmp_bank}" = "I" && setenv tmp_bank 8'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test "${param_spi2_bus_pins}" = "b"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/spi2@1 phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/spi2_cs0@1 phandle
++	fdt set /soc/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++if test "${param_pwm_pins}" = "0"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm0@0
++	fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test "${param_pwm_pins}" = "1"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm1@0
++	fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/uart2@0 phandle
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test "${param_uart3_pins}" = "b"; then
++	if test "${param_uart3_rtscts}" = "1"; then
++		fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3_pins_b phandle
++		fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_pins_b_rts_cts phandle
++		fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++		fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++		env delete tmp_phandle1 tmp_phandle2
++	else
++		fdt get value tmp_phandle /soc/pinctrl@1c20800/uart3_pins_b phandle
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>"
++		env delete tmp_phandle
++	fi
++else
++	if test "${param_uart3_rtscts}" = "1"; then
++		fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3_pins_a phandle
++		fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_pins_a_rts_cts phandle
++		fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++		fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++		env delete tmp_phandle1 tmp_phandle2
++	fi
++fi
++
++if test "${param_uart4_pins}" = "b"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/uart4@1 phandle
++	fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c1.dtso
+new file mode 100644
+index 000000000000..4c104bf4a5f0
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc@1c00000/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c2.dtso
+new file mode 100644
+index 000000000000..1c2c3e9aca81
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc@1c00000/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-nand.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-nand.dtso
+new file mode 100644
+index 000000000000..f0d4c2f34859
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-nand.dtso
+@@ -0,0 +1,103 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			nand_pins_a: nand_pins@0 {
++				pins = "PC0", "PC1", "PC2",
++						"PC5", "PC8", "PC9", "PC10",
++						"PC11", "PC12", "PC13", "PC14",
++						"PC15", "PC16";
++				function = "nand0";
++			};
++
++			nand_cs0_pins_a: nand_cs@0 {
++				pins = "PC4";
++				function = "nand0";
++			};
++
++			nand_cs1_pins_a: nand_cs@1 {
++				pins = "PC3";
++				function = "nand0";
++			};
++
++			nand_cs2_pins_a: nand_cs@2 {
++				pins = "PC17";
++				function = "nand0";
++			};
++
++			nand_cs3_pins_a: nand_cs@3 {
++				pins = "PC18";
++				function = "nand0";
++			};
++
++			nand_rb0_pins_a: nand_rb@0 {
++				pins = "PC6";
++				function = "nand0";
++			};
++
++			nand_rb1_pins_a: nand_rb@1 {
++				pins = "PC7";
++				function = "nand0";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&nfc>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
++			status = "okay";
++
++			nand@0 {
++				reg = <0>;
++				allwinner,rb = <0>;
++				nand-ecc-mode = "hw";
++				nand-on-flash-bbt;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <2>;
++					#size-cells = <2>;
++
++					partition@0 {
++						label = "SPL";
++						reg = <0x0 0x0 0x0 0x400000>;
++					};
++
++					partition@400000 {
++						label = "SPL.backup";
++						reg = <0x0 0x400000 0x0 0x400000>;
++					};
++
++					partition@800000 {
++						label = "U-Boot";
++						reg = <0x0 0x800000 0x0 0x400000>;
++					};
++
++					partition@c00000 {
++						label = "U-Boot.backup";
++						reg = <0x0 0xc00000 0x0 0x400000>;
++					};
++
++					partition@1000000 {
++						label = "env";
++						reg = <0x0 0x1000000 0x0 0x400000>;
++					};
++
++					partition@1400000 {
++						label = "rootfs";
++						reg = <0x0 0xa00000 0x01 0xff000000>;
++					};
++				};
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pps-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pps-gpio.dtso
+new file mode 100644
+index 000000000000..6031fc53e548
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pps-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pps_pins: pps_pins {
++				pins = "PI15";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			pps@0 {
++				compatible = "pps-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&pps_pins>;
++				gpios = <&pio 8 15 0>;  /* PI15 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pwm.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pwm.dtso
+new file mode 100644
+index 000000000000..ba885004fe4f
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pwm.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spdif-out.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spdif-out.dtso
+new file mode 100644
+index 000000000000..234dfc880f1f
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spdif-out.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&spdif>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&spdif_tx_pin>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			sound {
++				compatible = "simple-audio-card";
++				simple-audio-card,name = "On-board SPDIF";
++
++				simple-audio-card,cpu {
++					sound-dai = <&spdif>;
++				};
++
++				simple-audio-card,codec {
++					sound-dai = <&spdif_out>;
++				};
++			};
++
++			spdif_out: spdif-out {
++				#sound-dai-cells = <0>;
++				compatible = "linux,spdif-dit";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-jedec-nor.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..ee4ff6f453d1
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-jedec-nor.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++			spi1 = "/soc@1c00000/spi@1c06000";
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-spidev.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-spidev.dtso
+new file mode 100644
+index 000000000000..eac4f1e2d244
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-spidev.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++			spi1 = "/soc@1c00000/spi@1c06000";
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi0.dtso
+new file mode 100644
+index 000000000000..cad50d8a29a7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi0.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default", "default";
++			pinctrl-0 = <&spi0_pi_pins>;
++			pinctrl-1 = <&spi0_cs0_pi_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi1.dtso
+new file mode 100644
+index 000000000000..8c606d6b06a1
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc@1c00000/spi@1c06000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi2.dtso
+new file mode 100644
+index 000000000000..145f285588f8
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi2.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi2>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default", "default";
++			pinctrl-0 = <&spi2_pins_a>;
++			pinctrl-1 = <&spi2_cs0_pins_a>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart2.dtso
+new file mode 100644
+index 000000000000..89bb44d5aee0
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart2.dtso
+@@ -0,0 +1,37 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc@1c00000/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart2_pins_a: uart2@0 {
++				pins = "PI16", "PI17", "PI18", "PI19";
++				function = "uart2";
++			};
++
++			uart2_pins_a_2: uart2@1 {
++				pins = "PI18", "PI19";
++				function = "uart2";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins_a_2>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart3.dtso
+new file mode 100644
+index 000000000000..f599d92082e4
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart3.dtso
+@@ -0,0 +1,47 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc@1c00000/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart3_pins_a: uart3@0 {
++				pins = "PG6", "PG7";
++				function = "uart3";
++			};
++
++			uart3_pins_a_rts_cts: uart3@1 {
++				pins = "PG8", "PG9";
++				function = "uart3";
++			};
++
++			uart3_pins_b: uart3@2 {
++				pins = "PH0", "PH1";
++				function = "uart3";
++			};
++
++			uart3_pins_b_rts_cts: uart3@3 {
++				pins = "PH2", "PH3";
++				function = "uart3";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart4.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart4.dtso
+new file mode 100644
+index 000000000000..b5e562a6477b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart4.dtso
+@@ -0,0 +1,37 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial4 = "/soc@1c00000/serial@1c29000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart4_pins_a: uart4@0 {
++				pins = "PG10", "PG11";
++				function = "uart4";
++			};
++
++			uart4_pins_b: uart4@1 {
++				pins = "PH4", "PH5";
++				function = "uart4";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart4>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart4_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart5.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart5.dtso
+new file mode 100644
+index 000000000000..12c3f9699b23
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart5.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial5 = "/soc@1c00000/serial@1c29400";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart5_pins_a: uart5@0 {
++				pins = "PH6", "PH7";
++				function = "uart5";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart5>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart5_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart6.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart6.dtso
+new file mode 100644
+index 000000000000..6be41d505509
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart6.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial6 = "/soc@1c00000/serial@1c29800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart6_pins_a: uart6@0 {
++				pins = "PI12", "PI13";
++				function = "uart6";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart6>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart6_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart7.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart7.dtso
+new file mode 100644
+index 000000000000..967f6afbe7d3
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart7.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial7 = "/soc@1c00000/serial@1c29c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart7_pins_a: uart7@0 {
++				pins = "PI20", "PI21";
++				function = "uart7";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart7>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart7_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-w1-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-w1-gpio.dtso
+new file mode 100644
+index 000000000000..41da08c60aa7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PI15";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 8 15 0>; /* PI15 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-analog-codec.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-analog-codec.dtso
+new file mode 100644
+index 000000000000..60e2717fc582
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-analog-codec.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a13";
++
++	fragment@0 {
++		target = <&codec>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-fixup.scr-cmd b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-fixup.scr-cmd
+new file mode 100644
+index 000000000000..c82590c1ac18
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-fixup.scr-cmd
+@@ -0,0 +1,48 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test "${param_uart1_pins}" = "b"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c28400/uart1@1 phandle
++	fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2@0 phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-cts-rts@0 phandle
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3@0 phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts@0 phandle
++	fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c1.dtso
+new file mode 100644
+index 000000000000..444c32ca01d5
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc@1c00000/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c2.dtso
+new file mode 100644
+index 000000000000..7a30681ca287
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc@1c00000/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-nand.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-nand.dtso
+new file mode 100644
+index 000000000000..0c5fc89a1058
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-nand.dtso
+@@ -0,0 +1,60 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target = <&nfc>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&nand_pins>, <&nand_cs0_pin>, <&nand_rb0_pin>;
++			status = "okay";
++
++			nand@0 {
++				reg = <0>;
++				allwinner,rb = <0>;
++				nand-ecc-mode = "hw";
++				nand-on-flash-bbt;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <2>;
++					#size-cells = <2>;
++
++					partition@0 {
++						label = "SPL";
++						reg = <0x0 0x0 0x0 0x400000>;
++					};
++
++					partition@400000 {
++						label = "SPL.backup";
++						reg = <0x0 0x400000 0x0 0x400000>;
++					};
++
++					partition@800000 {
++						label = "U-Boot";
++						reg = <0x0 0x800000 0x0 0x400000>;
++					};
++
++					partition@c00000 {
++						label = "U-Boot.backup";
++						reg = <0x0 0xc00000 0x0 0x400000>;
++					};
++
++					partition@1000000 {
++						label = "env";
++						reg = <0x0 0x1000000 0x0 0x400000>;
++					};
++
++					partition@1400000 {
++						label = "rootfs";
++						reg = <0x0 0xa00000 0x01 0xff000000>;
++					};
++				};
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-pwm.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-pwm.dtso
+new file mode 100644
+index 000000000000..54f5d5123eb1
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-pwm.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm0_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-jedec-nor.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..8cebb0b988de
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-jedec-nor.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c05000";
++			spi1 = "/soc/spi@1c06000";
++			spi2 = "/soc/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-spidev.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-spidev.dtso
+new file mode 100644
+index 000000000000..ad0685f8af18
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-spidev.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c05000";
++			spi1 = "/soc/spi@1c06000";
++			spi2 = "/soc/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi0.dtso
+new file mode 100644
+index 000000000000..b23a754c0006
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi0.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c05000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			spi0_pins_a: spi0@0 {
++				pins = "PC0", "PC1", "PC2";
++				function = "spi0";
++			};
++
++			spi0_cs0_pins_a: spi0-cs0@0 {
++				pins = "PC3";
++				function = "spi0";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi0>;
++		__overlay__ {
++				status = "okay";
++				pinctrl-names = "default", "default";
++				pinctrl-0 = <&spi0_pins_a>;
++				pinctrl-1 = <&spi0_cs0_pins_a>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi1.dtso
+new file mode 100644
+index 000000000000..cc0af5db3fd0
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi1.dtso
+@@ -0,0 +1,39 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@1c06000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			spi1_pins_a: spi1@0 {
++				pins = "PG10", "PG11", "PG12";
++				function = "spi1";
++			};
++
++			spi1_cs0_pins_a: spi1-cs0@0 {
++				pins = "PG9";
++				function = "spi1";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>;
++		};
++	};
++
++
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi2.dtso
+new file mode 100644
+index 000000000000..6cf5c41a9eca
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi2 = "/soc/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi2>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart0.dtso
+new file mode 100644
+index 000000000000..6edad42bfcd7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart0.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			uart0 = "/soc@1c00000/serial@1c28000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart0_pa_pins: uart0@0 {
++				pins = "PF2", "PF4";
++				function = "uart0";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart0>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart0_pa_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart1.dtso
+new file mode 100644
+index 000000000000..675b701ed535
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			uart1 = "/soc@1c00000/serial@1c28400";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart1>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pe_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart2.dtso
+new file mode 100644
+index 000000000000..b3c4e3d7a0e2
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			uart2 = "/soc@1c00000/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pd_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart3.dtso
+new file mode 100644
+index 000000000000..15c25d0c5992
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart3.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			uart3 = "/soc@1c00000/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pg_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-analog-codec.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-analog-codec.dtso
+new file mode 100644
+index 000000000000..e1a70c5102bc
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-analog-codec.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&codec>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-can.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-can.dtso
+new file mode 100644
+index 000000000000..65aebcd4144c
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-can.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&can0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&can0_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-fixup.scr-cmd b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-fixup.scr-cmd
+new file mode 100644
+index 000000000000..b97042a720a7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-fixup.scr-cmd
+@@ -0,0 +1,143 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "B" && setenv tmp_bank 1;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "E" && setenv tmp_bank 4;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6;
++test "${tmp_bank}" = "H" && setenv tmp_bank 7;
++test "${tmp_bank}" = "I" && setenv tmp_bank 8'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_bus}" = "0" && test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_bus}" = "0" && test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test "${param_spi2_bus_pins}" = "b"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/spi2@1 phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/spi2_cs0@1 phandle
++	fdt set /soc/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++if test "${param_pwm_pins}" = "0"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm0@0
++	fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test "${param_pwm_pins}" = "1"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm1@0
++	fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test -n "${param_mmc2_cd_pin}"; then
++	setenv tmp_bank "${param_mmc2_cd_pin}"
++	setenv tmp_pin "${param_mmc2_cd_pin}"
++	run decompose_pin
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /soc/mmc@1c11000 cd-gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 1>"
++fi
++
++if test "${param_mmc2_non_removable}" = "1"; then
++	fdt rm /soc/mmc@1c11000 cd-gpios
++	fdt set /soc/mmc@1c11000 non-removable
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/uart2-pi-pins phandle
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test "${param_uart3_pins}" = "b"; then
++	if test "${param_uart3_rtscts}" = "1"; then
++		fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-ph-pins phandle
++		fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts-ph-pins phandle
++		fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++		fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++		env delete tmp_phandle1 tmp_phandle2
++	else
++		fdt get value tmp_phandle /soc/pinctrl@1c20800/uart3-ph-pins phandle
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>"
++		env delete tmp_phandle
++	fi
++else
++	if test "${param_uart3_rtscts}" = "1"; then
++		fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pg-pins phandle
++		fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts-pg-pins phandle
++		fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++		fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++		env delete tmp_phandle1 tmp_phandle2
++	fi
++fi
++
++if test "${param_uart4_pins}" = "b"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/uart4-pg-pins phandle
++	fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c1.dtso
+new file mode 100644
+index 000000000000..c5f6e9732d3a
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc@1c00000/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c2.dtso
+new file mode 100644
+index 000000000000..fa93d1ed9b72
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc@1c00000/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c3.dtso
+new file mode 100644
+index 000000000000..945795c338e8
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c3.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c3 = "/soc@1c00000/i2c@1c2b800";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c3>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c3_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c4.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c4.dtso
+new file mode 100644
+index 000000000000..4fcf08c2469b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c4.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c4 = "/soc@1c00000/i2c@1c2c000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			i2c4_pins_a: i2c4@0 {
++				pins = "PI2", "PI3";
++				function = "i2c4";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&i2c4>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c4_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s0.dtso
+new file mode 100644
+index 000000000000..1a19a2417d3b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s0.dtso
+@@ -0,0 +1,25 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			i2s0_pins: i2s0 {
++				pins = "PB5", "PB6", "PB7", "PB8", "PB9", "PB10", "PB11", "PB12";
++				function = "i2s0";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&i2s0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2s0_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s1.dtso
+new file mode 100644
+index 000000000000..e6f0a22b7991
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s1.dtso
+@@ -0,0 +1,25 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			i2s1_pins: i2s1 {
++				pins = "PA9", "PA14", "PA15", "PA16", "PA17";
++				function = "i2s1";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&i2s1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2s1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-mmc2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-mmc2.dtso
+new file mode 100644
+index 000000000000..ede92f243a1d
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-mmc2.dtso
+@@ -0,0 +1,18 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&mmc2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&mmc2_pins>;
++			vmmc-supply = <&reg_vcc3v3>;
++			bus-width = <4>;
++			cd-gpios = <&pio 7 0 1>; /* PH0, active low */
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-nand.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-nand.dtso
+new file mode 100644
+index 000000000000..ffa49cc69473
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-nand.dtso
+@@ -0,0 +1,103 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			nand_pins_a: nand_pins@0 {
++				pins = "PC0", "PC1", "PC2",
++						"PC5", "PC8", "PC9", "PC10",
++						"PC11", "PC12", "PC13", "PC14",
++						"PC15", "PC16";
++				function = "nand0";
++			};
++
++			nand_cs0_pins_a: nand_cs@0 {
++				pins = "PC4";
++				function = "nand0";
++			};
++
++			nand_cs1_pins_a: nand_cs@1 {
++				pins = "PC3";
++				function = "nand0";
++			};
++
++			nand_cs2_pins_a: nand_cs@2 {
++				pins = "PC17";
++				function = "nand0";
++			};
++
++			nand_cs3_pins_a: nand_cs@3 {
++				pins = "PC18";
++				function = "nand0";
++			};
++
++			nand_rb0_pins_a: nand_rb@0 {
++				pins = "PC6";
++				function = "nand0";
++			};
++
++			nand_rb1_pins_a: nand_rb@1 {
++				pins = "PC7";
++				function = "nand0";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&nfc>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
++			status = "okay";
++
++			nand@0 {
++				reg = <0>;
++				allwinner,rb = <0>;
++				nand-ecc-mode = "hw";
++				nand-on-flash-bbt;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <2>;
++					#size-cells = <2>;
++
++					partition@0 {
++						label = "SPL";
++						reg = <0x0 0x0 0x0 0x400000>;
++					};
++
++					partition@400000 {
++						label = "SPL.backup";
++						reg = <0x0 0x400000 0x0 0x400000>;
++					};
++
++					partition@800000 {
++						label = "U-Boot";
++						reg = <0x0 0x800000 0x0 0x400000>;
++					};
++
++					partition@c00000 {
++						label = "U-Boot.backup";
++						reg = <0x0 0xc00000 0x0 0x400000>;
++					};
++
++					partition@1000000 {
++						label = "env";
++						reg = <0x0 0x1000000 0x0 0x400000>;
++					};
++
++					partition@1400000 {
++						label = "rootfs";
++						reg = <0x0 0xa00000 0x01 0xff000000>;
++					};
++				};
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pps-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pps-gpio.dtso
+new file mode 100644
+index 000000000000..fe3e2bd96467
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pps-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pps_pins: pps_pins {
++				pins = "PI15";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			pps@0 {
++				compatible = "pps-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&pps_pins>;
++				gpios = <&pio 8 15 0>;  /* PI15 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pwm.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pwm.dtso
+new file mode 100644
+index 000000000000..b0cfe4deae76
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pwm.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spdif-out.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spdif-out.dtso
+new file mode 100644
+index 000000000000..11a09396bd35
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spdif-out.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&spdif>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&spdif_tx_pin>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			sound {
++				compatible = "simple-audio-card";
++				simple-audio-card,name = "On-board SPDIF";
++
++				simple-audio-card,cpu {
++					sound-dai = <&spdif>;
++				};
++
++				simple-audio-card,codec {
++					sound-dai = <&spdif_out>;
++				};
++			};
++
++			spdif_out: spdif-out {
++				#sound-dai-cells = <0>;
++				compatible = "linux,spdif-dit";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-add-cs1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-add-cs1.dtso
+new file mode 100644
+index 000000000000..c0a4ba2b3d4e
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-add-cs1.dtso
+@@ -0,0 +1,16 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&spi0>;
++		__overlay__ {
++			pinctrl-names = "default", "default", "default";
++			pinctrl-0 = <&spi0_pi_pins>;
++			pinctrl-1 = <&spi0_cs0_pi_pin>;
++			pinctrl-2 = <&spi0_cs1_pi_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-jedec-nor.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..b91097eca5b6
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-jedec-nor.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++			spi1 = "/soc@1c00000/spi@1c06000";
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-spidev.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-spidev.dtso
+new file mode 100644
+index 000000000000..341fe3229ffc
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-spidev.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++			spi1 = "/soc@1c00000/spi@1c06000";
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi0.dtso
+new file mode 100644
+index 000000000000..cad50d8a29a7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi0.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default", "default";
++			pinctrl-0 = <&spi0_pi_pins>;
++			pinctrl-1 = <&spi0_cs0_pi_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi1.dtso
+new file mode 100644
+index 000000000000..f0218eb9f76b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc@1c00000/spi@1c06000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pi_pins>, <&spi1_cs0_pi_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi2.dtso
+new file mode 100644
+index 000000000000..effba42b48bd
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi2.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi2>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default", "default";
++			pinctrl-0 = <&spi2_pb_pins>;
++			pinctrl-1 = <&spi2_pb_cs0_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart2.dtso
+new file mode 100644
+index 000000000000..79d1dca7a311
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart2.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc@1c00000/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart2_pins_a_2: uart2@1 {
++				pins = "PI18", "PI19";
++				function = "uart2";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins_a_2>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart3.dtso
+new file mode 100644
+index 000000000000..703acbcf377b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart3.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc@1c00000/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart3_pins_a_2: uart3@2 {
++				pins = "PG6", "PG7";
++				function = "uart3";
++			};
++
++			uart3_pins_a_rts_cts: uart3@1 {
++				pins = "PG8", "PG9";
++				function = "uart3";
++			};
++
++			uart3_pins_b_rts_cts: uart3@3 {
++				pins = "PH2", "PH3";
++				function = "uart3";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins_a_2>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart4.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart4.dtso
+new file mode 100644
+index 000000000000..19180341a67f
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart4.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial4 = "/soc@1c00000/serial@1c29000";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart4>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart4_pg_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart5.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart5.dtso
+new file mode 100644
+index 000000000000..a1369eee2917
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart5.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial5 = "/soc@1c00000/serial@1c29400";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart5>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart5_pi_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart6.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart6.dtso
+new file mode 100644
+index 000000000000..fb9efe2a9475
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart6.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial6 = "/soc@1c00000/serial@1c29800";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart6>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart6_pi_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart7.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart7.dtso
+new file mode 100644
+index 000000000000..bbdca3ec67ed
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart7.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial7 = "/soc@1c00000/serial@1c29c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart7>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart7_pi_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-w1-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-w1-gpio.dtso
+new file mode 100644
+index 000000000000..7d77606a1604
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PI15";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 8 15 0>; /* PI15 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-analog-codec.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-analog-codec.dtso
+new file mode 100644
+index 000000000000..36dbc31ae2a2
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-analog-codec.dtso
+@@ -0,0 +1,17 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&codec>;
++		__overlay__ {
++			allwinner,audio-routing =
++				"Line Out", "LINEOUT",
++				"MIC1", "Mic",
++				"Mic",  "MBIAS";
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cir.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cir.dtso
+new file mode 100644
+index 000000000000..bf4a0eafa133
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cir.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&ir>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&r_ir_rx_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-fixup.scr-cmd b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-fixup.scr-cmd
+new file mode 100644
+index 000000000000..604fe8bb78c1
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-fixup.scr-cmd
+@@ -0,0 +1,110 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "A" && setenv tmp_bank 0;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++for f in ${overlays}; do
++	if test "${f}" = "pwm"; then
++		setenv bootargs_new ""
++		for arg in ${bootargs}; do
++			if test "${arg}" = "console=ttyS0,115200"; then
++				echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
++			else
++				setenv bootargs_new "${bootargs_new} ${arg}"
++			fi
++		done
++		setenv bootargs "${bootargs_new}"
++	fi
++done
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@1c28400 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@1c28800 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-rts-cts-pins phandle
++	fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c0.dtso
+new file mode 100644
+index 000000000000..a36ac8667674
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c0.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c0 = "/soc/i2c@1c2ac00";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c1.dtso
+new file mode 100644
+index 000000000000..258c86de07cc
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c1.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c2.dtso
+new file mode 100644
+index 000000000000..a1e3284984df
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c2.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pps-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pps-gpio.dtso
+new file mode 100644
+index 000000000000..16a737b02935
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pps-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pps_pins: pps_pins {
++				pins = "PD14";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			pps@0 {
++				compatible = "pps-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&pps_pins>;
++				gpios = <&pio 3 14 0>; /* PD14 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pwm.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pwm.dtso
+new file mode 100644
+index 000000000000..ed3b8e606249
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pwm.dtso
+@@ -0,0 +1,39 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/chosen";
++		__overlay__ {
++			/delete-property/ stdout-path;
++		};
++	};
++
++	fragment@1 {
++		target = <&uart0>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++
++	fragment@2 {
++		target = <&pio>;
++		__overlay__ {
++			pwm0_pin: pwm0 {
++				pins = "PA5";
++				function = "pwm0";
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm0_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spdif-out.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spdif-out.dtso
+new file mode 100644
+index 000000000000..35b2d567704c
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spdif-out.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&spdif>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&spdif_tx_pin>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			sound {
++				compatible = "simple-audio-card";
++				simple-audio-card,name = "On-board SPDIF";
++
++				simple-audio-card,cpu {
++					sound-dai = <&spdif>;
++				};
++
++				simple-audio-card,codec {
++					sound-dai = <&spdif_out>;
++				};
++			};
++
++			spdif_out: spdif-out {
++				#sound-dai-cells = <0>;
++				compatible = "linux,spdif-dit";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-add-cs1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-add-cs1.dtso
+new file mode 100644
+index 000000000000..bd8e2561729d
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-add-cs1.dtso
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			spi0_cs1: spi0_cs1 {
++				pins = "PA21";
++				function = "gpio_out";
++				output-high;
++			};
++
++			spi1_cs1: spi1_cs1 {
++				pins = "PA10";
++				function = "gpio_out";
++				output-high;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi0_cs1>;
++			cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi1_cs1>;
++			cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-jedec-nor.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..95fa5f2ca1ef
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-jedec-nor.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c68000";
++			spi1 = "/soc/spi@1c69000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-spidev.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-spidev.dtso
+new file mode 100644
+index 000000000000..c79beb95ecfa
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c68000";
++			spi1 = "/soc/spi@1c69000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart1.dtso
+new file mode 100644
+index 000000000000..3c10d4db420b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial1 = "/soc/serial@1c28400";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart1>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart2.dtso
+new file mode 100644
+index 000000000000..f16e61862913
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart3.dtso
+new file mode 100644
+index 000000000000..b1aef575e0f0
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart3.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost0.dtso
+new file mode 100644
+index 000000000000..6bd8aedbee20
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost0.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&ehci0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci0>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost1.dtso
+new file mode 100644
+index 000000000000..4c7222b10beb
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost1.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&ehci1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost2.dtso
+new file mode 100644
+index 000000000000..2b83ec933a9d
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost2.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&ehci2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci2>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost3.dtso
+new file mode 100644
+index 000000000000..e2f28ab1ae64
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost3.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&ehci3>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci3>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-w1-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-w1-gpio.dtso
+new file mode 100644
+index 000000000000..f4ccb7fba9ad
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PD14";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 3 14 0>; /* PD14 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c2.dtso
+new file mode 100644
+index 000000000000..a1e3284984df
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c2.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c3.dtso
+new file mode 100644
+index 000000000000..949a98234551
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c3.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c3 = "/soc/i2c@1c2b800";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c3>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev0.dtso
+new file mode 100644
+index 000000000000..fae9c3f75bb7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev0.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            spi0 = "/soc/spi@1c05000";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            #address-cells = <0x00000001>;
++            #size-cells = <0x00000000>;
++            status = "okay";
++            spidev@0 {
++                compatible = "armbian,spi-dev";
++                status = "okay";
++                reg = <0x00000000>;
++                spi-max-frequency = <0x000f4240>;
++            };
++        };
++    };
++    __fixups__ {
++        spi0 = "/fragment@1:target:0";
++    };
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev1.dtso
+new file mode 100644
+index 000000000000..cb98ddf6bbd8
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev1.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            spi1 = "/soc/spi@1c06000";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            #address-cells = <0x00000001>;
++            #size-cells = <0x00000000>;
++            status = "okay";
++            spidev@0 {
++                compatible = "armbian,spi-dev";
++                status = "okay";
++                reg = <0x00000000>;
++                spi-max-frequency = <0x000f4240>;
++            };
++        };
++    };
++    __fixups__ {
++        spi1 = "/fragment@1:target:0";
++    };
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart2.dtso
+new file mode 100644
+index 000000000000..2030d6777fa9
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            serial2 = "/soc/serial@1c28800";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            pinctrl-names = "default";
++            pinctrl-0 = <0xffffffff>;
++            status = "okay";
++        };
++    };
++    __fixups__ {
++        uart2 = "/fragment@1:target:0";
++        uart2_pi_pins = "/fragment@1/__overlay__:pinctrl-0:0";
++    };
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart4.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart4.dtso
+new file mode 100644
+index 000000000000..0d7f934f6828
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart4.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            serial4 = "/soc/serial@1c29000";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            pinctrl-names = "default";
++            pinctrl-0 = <0xffffffff>;
++            status = "okay";
++        };
++    };
++    __fixups__ {
++        uart4 = "/fragment@1:target:0";
++        uart4_ph_pins = "/fragment@1/__overlay__:pinctrl-0:0";
++    };
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart5.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart5.dtso
+new file mode 100644
+index 000000000000..e695535afc7e
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart5.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            serial5 = "/soc/serial@1c29400";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            pinctrl-names = "default";
++            pinctrl-0 = <0xffffffff>;
++            status = "okay";
++        };
++    };
++    __fixups__ {
++        uart5 = "/fragment@1:target:0";
++        uart5_ph_pins = "/fragment@1/__overlay__:pinctrl-0:0";
++    };
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart7.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart7.dtso
+new file mode 100644
+index 000000000000..e572598339a6
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart7.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            serial7 = "/soc/serial@1c29c00";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            pinctrl-names = "default";
++            pinctrl-0 = <0xffffffff>;
++            status = "okay";
++        };
++    };
++    __fixups__ {
++        uart7 = "/fragment@1:target:0";
++        uart7_pi_pins = "/fragment@1/__overlay__:pinctrl-0:0";
++    };
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch
new file mode 100644
index 000000000000..04330899f433
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch
@@ -0,0 +1,209 @@
+From 10c3d372d0fcb4e4f403dc8863022120b6c710bd Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:29:16 +0300
+Subject: arm:dts:overlay: sun8i-h3-cpu-clock add overclock
+
+---
+ arch/arm/boot/dts/allwinner/overlay/Makefile  |  3 +
+ .../sun8i-h3-cpu-clock-1.2GHz-1.3v.dtso       | 31 +++++++++
+ .../sun8i-h3-cpu-clock-1.368GHz-1.3v.dtso     | 67 +++++++++++++++++++
+ .../sun8i-h3-cpu-clock-1.3GHz-1.3v.dtso       | 61 +++++++++++++++++
+ 4 files changed, 162 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dtso
+
+diff --git a/arch/arm/boot/dts/allwinner/overlay/Makefile b/arch/arm/boot/dts/allwinner/overlay/Makefile
+index 0c47e8fda8fc..560f926b7018 100644
+--- a/arch/arm/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm/boot/dts/allwinner/overlay/Makefile
+@@ -60,6 +60,9 @@ dtb-$(CONFIG_MACH_SUN7I) += \
+ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-h3-analog-codec.dtbo \
+ 	sun8i-h3-cir.dtbo \
++	sun8i-h3-cpu-clock-1.2GHz-1.3v.dtbo \
++	sun8i-h3-cpu-clock-1.368GHz-1.3v.dtbo \
++	sun8i-h3-cpu-clock-1.3GHz-1.3v.dtbo \
+ 	sun8i-h3-i2c0.dtbo \
+ 	sun8i-h3-i2c1.dtbo \
+ 	sun8i-h3-i2c2.dtbo \
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dtso
+new file mode 100644
+index 000000000000..b07e694c781a
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dtso
+@@ -0,0 +1,31 @@
++// DT overlay for CPU frequency operating points to up to 1.2GHz at a maximum CPU voltage of 1.3v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu0_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the existing DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-1104000000 {
++				opp-hz = /bits/ 64 <1104000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1200000000 {
++				opp-hz = /bits/ 64 <1200000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dtso
+new file mode 100644
+index 000000000000..e3fd7e5c85a6
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dtso
+@@ -0,0 +1,67 @@
++// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu0_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-1056000000 {
++				opp-hz = /bits/ 64 <1056000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1104000000 {
++				opp-hz = /bits/ 64 <1104000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1152000000 {
++				opp-hz = /bits/ 64 <1152000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1200000000 {
++				opp-hz = /bits/ 64 <1200000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1224000000 {
++				opp-hz = /bits/ 64 <1224000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1248000000 {
++				opp-hz = /bits/ 64 <1248000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1296000000 {
++				opp-hz = /bits/ 64 <1296000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1368000000 {
++				opp-hz = /bits/ 64 <1368000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dtso
+new file mode 100644
+index 000000000000..413222831eab
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dtso
+@@ -0,0 +1,61 @@
++// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu0_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-1056000000 {
++				opp-hz = /bits/ 64 <1056000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1104000000 {
++				opp-hz = /bits/ 64 <1104000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1152000000 {
++				opp-hz = /bits/ 64 <1152000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1200000000 {
++				opp-hz = /bits/ 64 <1200000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1224000000 {
++				opp-hz = /bits/ 64 <1224000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1248000000 {
++				opp-hz = /bits/ 64 <1248000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1296000000 {
++				opp-hz = /bits/ 64 <1296000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch
new file mode 100644
index 000000000000..c8764aef4226
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch
@@ -0,0 +1,133 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hehopmajieh <hehopmajieh@debian.bg>
+Date: Thu, 19 Mar 2020 10:40:44 +0200
+Subject: arm:dts:sun5i-a13-olinuxino Add panel lcd-olinuxino-4.3 needed to fix
+ overlay tests
+
+---
+ arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts | 79 ++++++----
+ 1 file changed, 44 insertions(+), 35 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts
+index fadeae3cd8bb..d015a24c67a2 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts
++++ b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts
+@@ -48,6 +48,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/pwm/pwm.h>
+ 
+ / {
+ 	model = "Olimex A13-Olinuxino";
+@@ -72,40 +73,28 @@ led {
+ 		};
+ 	};
+ 
+-	bridge {
+-		compatible = "dumb-vga-dac";
++	lcd_backlight: backlight {
++                compatible = "pwm-backlight";
++                pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
++                brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
++                default-brightness-level = <8>;
++        };
++
++        panel: panel {
++                compatible = "olimex,lcd-olinuxino-4.3";
++                backlight = <&lcd_backlight>;
++                enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */
++                pinctrl-names = "default";
++                #address-cells = <1>;
++                #size-cells = <0>;
++                port {
++                        panel_input: endpoint {
++                        	remote-endpoint = <&tcon0_out_lcd>;
++                        };
++                };
++
++        };
+ 
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-
+-				vga_bridge_in: endpoint {
+-					remote-endpoint = <&tcon0_out_vga>;
+-				};
+-			};
+-
+-			port@1 {
+-				reg = <1>;
+-
+-				vga_bridge_out: endpoint {
+-					remote-endpoint = <&vga_con_in>;
+-				};
+-			};
+-		};
+-	};
+-
+-	vga {
+-		compatible = "vga-connector";
+-
+-		port {
+-			vga_con_in: endpoint {
+-				remote-endpoint = <&vga_bridge_out>;
+-			};
+-		};
+-	};
+ };
+ 
+ &be0 {
+@@ -130,6 +119,11 @@ axp209: pmic@34 {
+ 
+ 		interrupt-controller;
+ 		#interrupt-cells = <1>;
++		axp_gpio:gpio{ 
++                        compatible = "x-powers,axp209-gpio";
++                        gpio-controller;
++                        #gpio-cells = <2>; 
++                };
+ 	};
+ };
+ 
+@@ -221,12 +215,18 @@ &tcon0 {
+ };
+ 
+ &tcon0_out {
+-	tcon0_out_vga: endpoint@0 {
++	tcon0_out_lcd: endpoint@0 {
+ 		reg = <0>;
+-		remote-endpoint = <&vga_bridge_in>;
++		remote-endpoint = <&panel_input>;
+ 	};
+ };
+ 
++&pwm {
++        pinctrl-names = "default";
++        pinctrl-0 = <&pwm0_pin>;
++        status = "okay";
++};
++
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart1_pg_pins>;
+@@ -245,3 +245,12 @@ &usbphy {
+ 	usb1_vbus-supply = <&reg_usb1_vbus>;
+ 	status = "okay";
+ };
++
++&rtp {
++	allwinner,ts-attached;
++	#thermal-sensor-cells = <0>;
++	/* sensitive/noisy touch panel */
++	touchscreen-inverted-x;
++	allwinner,tp-sensitive-adjust = <0>;
++	allwinner,filter-type = <3>;
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch
new file mode 100644
index 000000000000..0da0d63579bd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch
@@ -0,0 +1,106 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Mitko Gamishev <hehopmajieh@debian.bg>
+Date: Wed, 5 Feb 2020 15:00:25 +0200
+Subject: arm:dts:sun5i-a13-olinuxino-micro add panel lcd-olinuxino-4.3
+
+---
+ arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts | 62 +++++++++-
+ 1 file changed, 60 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts
+index bfe1075e62cc..32874f6a5917 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts
++++ b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts
+@@ -44,7 +44,7 @@
+ /dts-v1/;
+ #include "sun5i-a13.dtsi"
+ #include "sunxi-common-regulators.dtsi"
+-
++#include <dt-bindings/pwm/pwm.h>
+ #include <dt-bindings/gpio/gpio.h>
+ 
+ / {
+@@ -70,6 +70,40 @@ led {
+ 			default-state = "on";
+ 		};
+ 	};
++
++	 backlight: backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
++                brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
++                default-brightness-level = <8>;
++
++        };
++
++	 panel: panel {
++                compatible = "olimex,lcd-olinuxino-4.3";
++                backlight = <&backlight>;
++		enable-gpios = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
++		pinctrl-names = "default";
++                #address-cells = <1>;
++                #size-cells = <0>;
++		port {
++			panel_input: endpoint {
++				remote-endpoint = <&tcon0_out_lcd>;
++			};
++		};
++
++                };
++
++	};
++
++
++
++&be0 {
++	status = "okay";
++};
++
++&codec {
++	status = "okay";
+ };
+ 
+ &ehci0 {
+@@ -117,10 +151,28 @@ &reg_usb0_vbus {
+ };
+ 
+ &reg_usb1_vbus {
+-	gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
++	gpio = <&pio 2 19 GPIO_ACTIVE_HIGH>;
+ 	status = "okay";
+ };
+ 
++&tcon0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&lcd_rgb666_pins>;
++	status = "okay";
++};
++&tcon0_out {
++	tcon0_out_lcd: endpoint@0 {
++		reg = <0>;
++		remote-endpoint = <&panel_input>;
++	};
++};
++
++&pwm {
++        pinctrl-names = "default";
++        pinctrl-0 = <&pwm0_pin>;
++        status = "okay";
++};
++
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart1_pg_pins>;
+@@ -139,3 +191,9 @@ &usbphy {
+ 	usb1_vbus-supply = <&reg_usb1_vbus>;
+ 	status = "okay";
+ };
++
++&rtp {
++	allwinner,ts-attached;
++	touchscreen-inverted-x;
++};
++
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch
new file mode 100644
index 000000000000..b219c1b9c863
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch
@@ -0,0 +1,99 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 23 Jan 2022 22:32:07 +0300
+Subject: arm:dts:sun7i-a20 Disable OOB IRQ for brcm-wifi on Cubietruck and
+ Banana-Pro
+
+While doing some brcmfmac driver work I needed to test this also on some
+devicetree based boards. So I fired up the good old Cubietruck and when
+that would not work a Banana Pro.
+
+With an unmodified 4.17 kernel both boards intermittently would come up
+with non working wifi with the following errors:
+
+ brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout
+ brcmfmac: brcmf_bus_started: failed: -110
+ brcmfmac: brcmf_attach: dongle is not responding: err=-110
+ brcmfmac: brcmf_sdio_firmware_callback: brcmf_attach failed
+
+They would come up this way more often then with actual working wifi,
+once this problem happens it seems to require a power-cycle to fix.
+Once things work one can safely reboot without hitting the issue.
+
+I've found that disabling OOB interrupts fixes this. This really is more
+of a workaround then a proper fix, but it makes the wifi reliable again
+and it does not have much of a downside.
+
+Using an OOB IRQ instead of the sdio-IRQ mechanism is mostly important to
+allow the MMC controller to go into runtime-suspend which is not really an
+issue on these boards since they are (usually) not battery powered.
+
+I've looked at recent brcmfmac and mmc-core changes which may explain this
+and I've not found anything. So the most likely culprit is the A20 external
+interrupt handling e.g. perhaps it is set to edge instead of level? Either
+way I do not have time to further investigate this.
+
+BugLink: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=908438
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts  | 16 ++++++++--
+ arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts | 16 ++++++++--
+ 2 files changed, 26 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+index e22f0e8bb17a..e687480765e6 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+@@ -162,9 +162,19 @@ &mmc3 {
+ 	brcmf: wifi@1 {
+ 		reg = <1>;
+ 		compatible = "brcm,bcm4329-fmac";
+-		interrupt-parent = <&pio>;
+-		interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>;
+-		interrupt-names = "host-wake";
++		/*
++		 * OOB interrupt support is broken ATM, often the first irq
++		 * does not get seen resulting in the drv probe failing with:
++		 *
++		 * brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout
++		 * brcmfmac: brcmf_bus_started: failed: -110
++		 * brcmfmac: brcmf_attach: dongle is not responding: err=-110
++		 * brcmfmac: brcmf_sdio_firmware_callback: brcmf_attach failed
++		 *
++		 * interrupt-parent = <&pio>;
++		 * interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>;
++		 * interrupt-names = "host-wake";
++		 */
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+index 52160e368304..525cb7fcca79 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+@@ -213,9 +213,19 @@ &mmc3 {
+ 	brcmf: wifi@1 {
+ 		reg = <1>;
+ 		compatible = "brcm,bcm4329-fmac";
+-		interrupt-parent = <&pio>;
+-		interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */
+-		interrupt-names = "host-wake";
++		/*
++		 * OOB interrupt support is broken ATM, often the first irq
++		 * does not get seen resulting in the drv probe failing with:
++		 *
++		 * brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout
++		 * brcmfmac: brcmf_bus_started: failed: -110
++		 * brcmfmac: brcmf_attach: dongle is not responding: err=-110
++		 * brcmfmac: brcmf_sdio_firmware_callback: brcmf_attach failed
++		 *
++		 * interrupt-parent = <&pio>;
++		 * interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>;
++		 * interrupt-names = "host-wake";
++		 */
+ 	};
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch
new file mode 100644
index 000000000000..65a6160d2358
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch
@@ -0,0 +1,78 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:15:19 +0300
+Subject: arm:dts: sun7i-a20-bananapro add hdmi-connector, de
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts | 30 ++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+index e687480765e6..3a34fb39a840 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+@@ -60,6 +60,17 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -91,6 +102,7 @@ reg_gmac_3v3: gmac-3v3 {
+ };
+ 
+ &ahci {
++	target-supply = <&reg_ahci_5v>;
+ 	status = "okay";
+ };
+ 
+@@ -98,6 +110,10 @@ &codec {
+ 	status = "okay";
+ };
+ 
++&de {
++	status = "okay";
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+@@ -115,6 +131,16 @@ &gmac {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+@@ -227,3 +253,7 @@ &usbphy {
+ 	usb2_vbus-supply = <&reg_usb2_vbus>;
+ 	status = "okay";
+ };
++
++&reg_ahci_5v {
++	status = "okay";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch
new file mode 100644
index 000000000000..6dd60f8e76b0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 11:38:08 +0300
+Subject: arm:dts: sun7i-a20-cubietruck add alias uart2
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+index df428f29b82f..a3d169c4395e 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+@@ -55,6 +55,7 @@ / {
+ 
+ 	aliases {
+ 		serial0 = &uart0;
++		serial2 = &uart2;
+ 	};
+ 
+ 	chosen {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch
new file mode 100644
index 000000000000..a658db2f7251
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch
@@ -0,0 +1,55 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Wed, 24 Jun 2020 20:53:36 +0300
+Subject: arm:dts:sun7i-a20: olimex-som(204)-evb,olinuxino-micro decrease dcdc2
+ min voltage
+
+fixes some kernel crashes
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts    | 2 +-
+ arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts | 2 +-
+ arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts   | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts
+index f05ee32bc9cb..e1867190c70c 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts
+@@ -247,7 +247,7 @@ &reg_ahci_5v {
+ 
+ &reg_dcdc2 {
+ 	regulator-always-on;
+-	regulator-min-microvolt = <1000000>;
++	regulator-min-microvolt = <1300000>;
+ 	regulator-max-microvolt = <1400000>;
+ 	regulator-name = "vdd-cpu";
+ };
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts
+index 54af6c18075b..ae3aa1055559 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts
+@@ -218,7 +218,7 @@ &reg_ahci_5v {
+ 
+ &reg_dcdc2 {
+ 	regulator-always-on;
+-	regulator-min-microvolt = <1000000>;
++	regulator-min-microvolt = <1300000>;
+ 	regulator-max-microvolt = <1400000>;
+ 	regulator-name = "vdd-cpu";
+ };
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts
+index a1b89b2a2999..7077ceea73e2 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts
+@@ -268,7 +268,7 @@ &battery_power_supply {
+ 
+ &reg_dcdc2 {
+ 	regulator-always-on;
+-	regulator-min-microvolt = <1000000>;
++	regulator-min-microvolt = <1300000>;
+ 	regulator-max-microvolt = <1400000>;
+ 	regulator-name = "vdd-cpu";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch
new file mode 100644
index 000000000000..0161a25115a8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Wed, 3 Jun 2020 13:49:44 +0300
+Subject: arm:dts:sun7i-a20-olinuxino-lime2 enable audio codec
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
+index ecb91fb899ff..e0174ca486cd 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
+@@ -96,6 +96,10 @@ &ahci {
+ 	status = "okay";
+ };
+ 
++&codec {
++        status = "okay";
++};
++
+ &de {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch
new file mode 100644
index 000000000000..1e0dcbd19f4d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hehopmajieh <hehopmajieh@debian.bg>
+Date: Tue, 16 Jun 2020 15:40:59 +0300
+Subject: arm:dts:sun7i-a20-olinuxino-lime2 enable ldo3 always-on
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
+index e0174ca486cd..ae710f785915 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
+@@ -237,10 +237,10 @@ &reg_ldo2 {
+ };
+ 
+ &reg_ldo3 {
++	regulator-always-on;
+ 	regulator-min-microvolt = <2800000>;
+ 	regulator-max-microvolt = <2800000>;
+ 	regulator-name = "vddio-csi0";
+-	regulator-soft-start;
+ 	regulator-ramp-delay = <1600>;
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch
new file mode 100644
index 000000000000..92a04c18462f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hehopmajieh <hehopmajieh@debian.bg>
+Date: Tue, 14 Apr 2020 10:28:16 +0300
+Subject: arm:dts:sun7i-a20-olinuxino-micro-emmc Add vqmmc node
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts
+index 2337b44a88aa..c79e9ad02812 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts
+@@ -55,6 +55,7 @@ mmc2_pwrseq: pwrseq {
+ 
+ &mmc2 {
+ 	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+ 	non-removable;
+ 	mmc-pwrseq = <&mmc2_pwrseq>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch
new file mode 100644
index 000000000000..1935688c31cb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 7 Feb 2022 19:15:17 +0300
+Subject: arm:dts: sun8i-h2-plus-orangepi-zero fix xradio interrupt
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+index 3706216ffb40..7b42ab8b5180 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+@@ -49,6 +49,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
+ 
+ / {
+ 	model = "Xunlong Orange Pi Zero";
+@@ -151,6 +152,10 @@ &mmc1 {
+ 	 */
+ 	xr819: sdio_wifi@1 {
+ 		reg = <1>;
++		compatible = "xradio,xr819";
++		interrupt-parent = <&pio>;
++		interrupts = <6 10 IRQ_TYPE_EDGE_RISING>;
++		interrupt-names = "host-wake";
+ 	};
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch
new file mode 100644
index 000000000000..8935eb4e5b18
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch
@@ -0,0 +1,104 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:34:48 +0300
+Subject: arm:dts:sun8i-h3 add thermal zones
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 68 ++++++++--
+ 1 file changed, 55 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index 30d72d3b670e..1b02a4c3f05d 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -297,32 +297,74 @@ ths: thermal-sensor@1c25000 {
+ 	};
+ 
+ 	thermal-zones {
+-		cpu_thermal: cpu-thermal {
+-			polling-delay-passive = <0>;
+-			polling-delay = <0>;
++		cpu_thermal {
++			/* milliseconds */
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
+ 			thermal-sensors = <&ths>;
+ 
+ 			trips {
+-				cpu_hot_trip: cpu-hot {
++				cpu_warm: cpu_warm {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_hot_pre: cpu_hot_pre {
+ 					temperature = <80000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 
+-				cpu_very_hot_trip: cpu-very-hot {
+-					temperature = <100000>;
+-					hysteresis = <0>;
++				cpu_hot: cpu_hot {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot_pre: cpu_very_hot_pre {
++					temperature = <90000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot: cpu_very_hot {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_crit: cpu_crit {
++					temperature = <105000>;
++					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
+ 
+ 			cooling-maps {
+-				cpu-hot-limit {
+-					trip = <&cpu_hot_trip>;
+-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				cpu_warm_limit_cpu {
++					trip = <&cpu_warm>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>;
++				};
++
++				cpu_hot_pre_limit_cpu {
++					trip = <&cpu_hot_pre>;
++					cooling-device = <&cpu0 2 3>;
++				};
++
++				cpu_hot_limit_cpu {
++					trip = <&cpu_hot>;
++					cooling-device = <&cpu0 3 4>;
++				};
++
++				cpu_very_hot_pre_limit_cpu {
++					trip = <&cpu_very_hot_pre>;
++					cooling-device = <&cpu0 5 6>;
++				};
++
++				cpu_very_hot_limit_cpu {
++					trip = <&cpu_very_hot>;
++					cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>;
+ 				};
+ 			};
+ 		};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch
new file mode 100644
index 000000000000..18f702481816
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch
@@ -0,0 +1,25 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:06:34 +0300
+Subject: arm:dts:sun8i-h3-bananapi-m2-plus add wifi_pwrseq
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts
+index 195a75da13f1..f3f324e669a0 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts
+@@ -48,3 +48,8 @@ / {
+ 	model = "Banana Pi BPI-M2-Plus H3";
+ 	compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
+ };
++
++&wifi_pwrseq {
++		clocks = <&rtc 1>;
++		clock-names = "ext_clock";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch
new file mode 100644
index 000000000000..fdea4d0f9686
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch
@@ -0,0 +1,60 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 14:14:41 +0300
+Subject: arm:dts: sun8i-h3-nanopi add leds pio pins
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi | 23 ++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi
+index cf8413fba6c1..57d5f75133fd 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi
+@@ -59,6 +59,8 @@ chosen {
+ 
+ 	leds {
+ 		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&leds_npi>, <&leds_r_npi>;
+ 
+ 		led-0 {
+ 			label = "nanopi:blue:status";
+@@ -75,6 +77,8 @@ led-1 {
+ 
+ 	gpio-keys {
+ 		compatible = "gpio-keys";
++		pinctrl-names = "default";
++		pinctrl-0 = <&sw_r_npi>;
+ 
+ 		key-0 {
+ 			label = "k1";
+@@ -100,6 +104,25 @@ &ohci3 {
+ 	status = "okay";
+ };
+ 
++&pio {
++	leds_npi: led_pins {
++		pins = "PA10";
++		function = "gpio_out";
++	};
++};
++
++&r_pio {
++	leds_r_npi: led_pins {
++		pins = "PL10";
++		function = "gpio_out";
++	};
++
++	sw_r_npi: key_pins {
++		pins = "PL3";
++		function = "gpio_in";
++	};
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch
new file mode 100644
index 000000000000..1887bf48f45a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch
@@ -0,0 +1,33 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 7 Feb 2022 19:01:59 +0300
+Subject: arm:dts: sun8i-h3-orangepi-pc-plus add wifi_pwrseq
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts
+index babf4cf1b2f6..e1efbf1b1baf 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts
+@@ -51,10 +51,16 @@ aliases {
+ 		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ 		ethernet1 = &rtl8189ftv;
+ 	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */
++	};
+ };
+ 
+ &mmc1 {
+ 	vmmc-supply = <&reg_vcc3v3>;
++	mmc-pwrseq = <&wifi_pwrseq>;
+ 	bus-width = <4>;
+ 	non-removable;
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch
new file mode 100644
index 000000000000..53e938cccdf9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch
@@ -0,0 +1,48 @@
+From 944b81371656107101029f67759713abf4f30a51 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Mon, 10 Jul 2023 19:24:21 +0000
+Subject: arm: dts: sun8i: h3: reduce opp-microvolt to prevent not supported by
+ regulator error
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index 1b02a4c3f05d..8c2f597772fe 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -86,19 +86,19 @@ opp-1008000000 {
+ 
+ 		opp-1104000000 {
+ 			opp-hz = /bits/ 64 <1104000000>;
+-			opp-microvolt = <1320000 1320000 1320000>;
++			opp-microvolt = <1300000 1300000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-1200000000 {
+ 			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <1320000 1320000 1320000>;
++			opp-microvolt = <1300000 1300000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-1296000000 {
+ 			opp-hz = /bits/ 64 <1296000000>;
+-			opp-microvolt = <1340000 1340000 1340000>;
++			opp-microvolt = <1300000 1300000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+@@ -106,6 +106,7 @@ opp-1368000000 {
+ 			opp-hz = /bits/ 64 <1368000000>;
+ 			opp-microvolt = <1400000 1400000 1400000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
++			status = "disabled";
+ 		};
+ 	};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch
new file mode 100644
index 000000000000..ab0a1b8a33c4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch
@@ -0,0 +1,40 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:01:30 +0300
+Subject: arm:dts: sun8i-r40 add clk_out_a fix bananam2ultra
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-r40.dtsi | 17 ++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+index 83562328b8c0..74c20d84046f 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+@@ -75,6 +75,23 @@ osc32k: osc32k {
+ 			clock-accuracy = <20000>;
+ 			clock-output-names = "ext-osc32k";
+ 		};
++
++		osc24M_32k: clk@1 {
++			#clock-cells = <0>;
++			compatible = "fixed-factor-clock";
++			clock-div = <732>;
++			clock-mult = <1>;
++			clocks = <&osc24M>;
++			clock-output-names = "osc24M_32k";
++		};
++
++		clk_out_a: clk@01c201f0 {
++			#clock-cells = <0>;
++			compatible = "allwinner,sun7i-a20-out-clk";
++			reg = <0x01c201f0 0x4>;
++			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
++			clock-output-names = "clk_out_a";
++		};
+ 	};
+ 
+ 	cpus {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch
new file mode 100644
index 000000000000..f71404e66c9f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch
@@ -0,0 +1,63 @@
+From 606b4f4da15c9ec3a14c3b2bca30211a81afd249 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 21:18:21 +0300
+Subject: arm:dts: sun8i-r40 bananapi-m2-ultra add codec analog
+
+---
+ .../allwinner/sun8i-r40-bananapi-m2-ultra.dts  | 10 ++++++++++
+ arch/arm/boot/dts/allwinner/sun8i-r40.dtsi     | 18 ++++++++++++++++++
+ 2 files changed, 28 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
+index 3508633a8e55..ebb2bd322112 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
+@@ -118,6 +118,16 @@ &cpu0 {
+ 	cpu-supply = <&reg_dcdc2>;
+ };
+ 
++&codec {
++	allwinner,audio-routing =
++		"Headphone", "HP",
++		"Headphone", "HPCOM",
++		"MIC1", "Mic",
++		"Mic", "MBIAS";
++	allwinner,codec-analog-controls = <&codec_analog>;
++	status = "okay";
++};
++
+ &de {
+ 	status = "okay";
+ };
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+index d73828d6b3c0..548bdee2f3b4 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+@@ -839,6 +839,24 @@ i2s2: i2s@1c22800 {
+ 			dma-names = "rx", "tx";
+ 		};
+ 
++		codec: codec@1c22c00 {
++			#sound-dai-cells = <1>;
++			compatible = "allwinner,sun8i-h3-codec";
++			reg = <0x01c22c00 0x300>;
++			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_CODEC>;
++			clock-names = "apb", "codec";
++			resets = <&ccu RST_BUS_CODEC>;
++			dmas = <&dma 19>, <&dma 19>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		codec_analog: codec-analog@1c22f00 {
++			compatible = "allwinner,sun8i-a23-codec-analog";
++			reg = <0x01c22f00 0x4>;
++		};
++
+ 		ths: thermal-sensor@1c24c00 {
+ 			compatible = "allwinner,sun8i-r40-ths";
+ 			reg = <0x01c24c00 0x100>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch
new file mode 100644
index 000000000000..7c0d2059b4e8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch
@@ -0,0 +1,63 @@
+From 382dfff02a8cb4eb087265db7b5143a01f568226 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 12:58:57 +0300
+Subject: arm:dts: sun8i-v3s/s3-pinecube enable sound codec
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts | 14 ++++++++++++++
+ arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi        | 14 ++++++++++++++
+ 2 files changed, 28 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts
+index 20966e954eda..773ad05033a2 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts
+@@ -58,6 +58,20 @@ wifi_pwrseq: wifi_pwrseq {
+ 	};
+ };
+ 
++
++&i2s0 {
++       status = "okay";
++};
++
++&codec {
++	allwinner,audio-routing =
++		"Speaker", "LINEOUT",
++		"MIC1", "Mic",
++		"Mic",  "MBIAS";
++	allwinner,pa-gpios = <&pio 6 6 GPIO_ACTIVE_HIGH>; /* PG6 */
++	status = "okay";
++};
++
+ &csi1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&csi1_8bit_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+index e8a04476b776..029754f492f0 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+@@ -506,6 +506,20 @@ codec_analog: codec-analog@1c23000 {
+ 			reg = <0x01c23000 0x4>;
+ 		};
+ 
++
++               i2s0: i2s@1c22000 {
++                       #sound-dai-cells = <0>;
++                       compatible = "allwinner,sun8i-h3-i2s";
++                       reg = <0x01c22000 0x400>;
++                       interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
++                       clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
++                       clock-names = "apb", "mod";
++                       dmas = <&dma 3>, <&dma 3>;
++                       resets = <&ccu RST_BUS_I2S0>; /* TODO: Areset/sun8i-v3s-ccu says this isn't available on V3s */
++                       dma-names = "rx", "tx";
++                       status = "disabled";
++               };
++
+ 		uart0: serial@1c28000 {
+ 			compatible = "snps,dw-apb-uart";
+ 			reg = <0x01c28000 0x400>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch
new file mode 100644
index 000000000000..cd8ed46256c2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Philipp Rossak <embed3d@gmail.com>
+Date: Sat, 27 Jan 2018 21:30:16 +0100
+Subject: arm:dts: sun9i-a80 add thermal sensor
+
+As we have gained the support for the thermal sensor in A80,
+we can now add its device nodes to the device tree.
+
+The clocks and the resets are shared between the GPADC and the THS
+sensor.
+
+Signed-off-by: Philipp Rossak <embed3d@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun9i-a80.dtsi | 11 ++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
+index 7d3f3300f431..14c68bdd1292 100644
+--- a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
+@@ -941,6 +941,17 @@ ccu: clock@6000000 {
+ 			#reset-cells = <1>;
+ 		};
+ 
++		ths: thermal-sensor@6004C00 {
++			compatible = "allwinner,sun9i-a80-ths";
++			reg = <0x06004C00 0x100>;
++			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_GPADC>, <&ccu CLK_GPADC>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_GPADC>;
++			#thermal-sensor-cells = <1>;
++			#io-channel-cells = <0>;
++		};
++
+ 		timer@6000c00 {
+ 			compatible = "allwinner,sun4i-a10-timer";
+ 			reg = <0x06000c00 0xa0>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch
new file mode 100644
index 000000000000..17613ecf15f5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch
@@ -0,0 +1,54 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Philipp Rossak <embed3d@gmail.com>
+Date: Sat, 27 Jan 2018 21:39:09 +0100
+Subject: arm:dts: sun9i-a80 add thermal zone
+
+This patch adds the thermal zones to the A80.
+
+Sensor 0 is located besides the big CPU, sensor 1 is located besides the
+DRAM, sensor 2 is located besides the GPU and sensor 3 is located besides
+the small CPU.
+
+Signed-off-by: Philipp Rossak <embed3d@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun9i-a80.dtsi | 26 ++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
+index 14c68bdd1292..7b7260f0cfa9 100644
+--- a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
+@@ -1261,4 +1261,30 @@ r_rsb: rsb@8003400 {
+ 			#size-cells = <0>;
+ 		};
+ 	};
++
++	thermal-zones {
++		cpu0_thermal: cpu0-thermal {
++			polling-delay-passive = <1000>;
++			polling-delay = <5000>;
++			thermal-sensors = <&ths 0>;
++		};
++
++		dram_thermal: dram-thermal {
++			polling-delay-passive = <1000>;
++			polling-delay = <5000>;
++			thermal-sensors = <&ths 1>;
++		};
++
++		gpu_thermal: gpu-thermal {
++			polling-delay-passive = <1000>;
++			polling-delay = <5000>;
++			thermal-sensors = <&ths 2>;
++		};
++
++		cpu2_thermal: cpu2-thermal {
++			polling-delay-passive = <1000>;
++			polling-delay = <5000>;
++			thermal-sensors = <&ths 3>;
++		};
++	};
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch
new file mode 100644
index 000000000000..3aeab230e6b2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch
@@ -0,0 +1,33 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:43:08 +0300
+Subject: arm:dts:sunxi-h3-h5.dtsi add i2s0 i2s1 pins
+
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 68dd7a6331b4..5a3fb7644dd1 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -464,6 +464,16 @@ i2c2_pins: i2c2-pins {
+ 				function = "i2c2";
+ 			};
+ 
++			i2s0_pins: i2s0-pins {
++				pins = "PA18", "PA19", "PA20", "PA21";
++				function = "i2s0";
++			};
++
++			i2s1_pins: i2s1-pins {
++				pins = "PG10", "PG11", "PG12", "PG13";
++				function = "i2s1";
++			};
++
+ 			mmc0_pins: mmc0-pins {
+ 				pins = "PF0", "PF1", "PF2", "PF3",
+ 				       "PF4", "PF5";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch
new file mode 100644
index 000000000000..a8d6f45416f7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 16:12:37 +0300
+Subject: arm:dts: sunxi-h3-h5.dtsi force mmc0 bus-width
+
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index ad2179fae156..68dd7a6331b4 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -221,6 +221,7 @@ mmc0: mmc@1c0f000 {
+ 			resets = <&ccu RST_BUS_MMC0>;
+ 			reset-names = "ahb";
+ 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
++			bus-width = <0x4>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch
new file mode 100644
index 000000000000..d7131d9d5e94
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch
@@ -0,0 +1,429 @@
+From 903e373669df260be08499379f8083b1dfad6a0b Mon Sep 17 00:00:00 2001
+From: wuweidong <625769020@qq.com>
+Date: Mon, 27 Nov 2017 10:23:51 +0800
+Subject: arm64:dts: Add sun50i-h5-nanopi-k1-plus device
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h5-nanopi-k1-plus.dts    | 396 ++++++++++++++++++
+ 2 files changed, 397 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 38867649c063..63f1b3fbe4ac 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-k1-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
+new file mode 100644
+index 000000000000..b7045a9efab5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
+@@ -0,0 +1,396 @@
++/*
++ * Copyright (C) 2016 ARM Ltd.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun50i-h5.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
++
++/ {
++	model = "FriendlyElec NanoPi K1 Plus";
++	compatible = "friendlyelec,nanopi-k1-plus", "allwinner,sun50i-h5";
++
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		status {
++			label = "nanopi:green:status";
++			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
++			};
++		pwr {
++			label = "nanopi:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++	};
++
++	r-gpio-keys {
++		compatible = "gpio-keys";
++
++		sw4 {
++			label = "sw4";
++			linux,code = <BTN_0>;
++			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		pinctrl-names = "default";
++		pinctrl-0 = <&gmac_power_pin_nanopi>;
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++	};
++
++	reg_usb0_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
++		status = "okay";
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++        compatible = "mmc-pwrseq-simple";
++        pinctrl-names = "default";
++        pinctrl-0 = <&wifi_en_npi>;
++        reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++        post-power-on-delay-ms = <200>;
++    };
++
++	rfkill_bt {
++		compatible = "rfkill-gpio";
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_pwr_pin>;
++		reset-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++		clocks = <&osc32k>;
++		clock-frequency = <32768>;
++		rfkill-name = "sunxi-bt";
++		rfkill-type = "bluetooth";
++	};
++
++	pcm5102a: pcm5102a-codec {
++        #sound-dai-cells = <0>;
++        compatible = "ti,pcm5102a";
++        status = "disabled";
++    };
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
++&codec {
++	allwinner,audio-routing =
++		"Line Out", "LINEOUT",
++		"MIC1", "Mic",
++		"Mic",  "MBIAS";
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0>;
++	};
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii-id";
++	local-mac-address = [ 00 00 00 00 00 00 ];
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&r_ir_rx_pin>;
++	status = "okay";
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	status = "okay";
++};
++
++&mmc1 {
++    vmmc-supply = <&reg_vcc3v3>;
++    vqmmc-supply = <&reg_vcc3v3>;
++    mmc-pwrseq = <&wifi_pwrseq>;
++    bus-width = <4>;
++    non-removable;
++    status = "okay";
++    brcmf: bcrmf@1 {
++        reg = <1>;
++        compatible = "brcm,bcm4329-fmac";
++    };
++};
++
++&mmc2 {
++    vmmc-supply = <&reg_vcc3v3>;
++    bus-width = <8>;
++    non-removable;
++    cap-mmc-hw-reset;
++    boot_device = <0>;
++    status = "okay";
++};
++
++&mmc2_8bit_pins {
++    /* Increase drive strength for DDR modes */
++    drive-strength = <40>;
++    /* eMMC is missing pull-ups */
++    bias-pull-up;
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++
++&pio {
++	leds_npi: led_pins@0 {
++		pins = "PA10";
++		function = "gpio_out";
++	};
++	gmac_power_pin_nanopi: gmac_power_pin@0 {
++		pins = "PD6";
++		function = "gpio_out";
++	};
++	bt_pwr_pin: bt_pwr_pin@0 {
++		pins = "PG13";
++		function = "gpio_out";
++	};
++	spi0_cs_pins: spi0_cs_pins {
++        pins = "PC3", "PA6";
++        function = "gpio_out";
++    };
++};
++&r_pio {
++	leds_r_npi: led_pins@0 {
++		pins = "PL10";
++		function = "gpio_out";
++	};
++	vdd_cpux_r_npi: regulator_pins@0 {
++		allwinner,pins = "PL6";
++		allwinner,function = "gpio_out";
++		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++	};
++	wifi_en_npi: wifi_en_pin {
++        pins = "PL7";
++        function = "gpio_out";
++    };
++};
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++
++&r_i2c {
++	status = "okay";
++	reg_vdd_cpux: regulator@65 {
++		compatible = "silergy,sy8106a";
++		reg = <0x65>;
++		regulator-name = "vdd-cpux";
++		silergy,fixed-microvolt = <1200000>;
++		/*
++		 * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
++		 * however both the Armbian DVFS table and the official one
++		 * have operating points with voltage under 1.1V, and both
++		 * DVFS table are known to work properly at the lowest
++		 * operating point.
++		 *
++		 * Use 1.0V as the minimum voltage instead.
++		 */
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
++&spi0 {
++	status = "okay";
++        spi-flash@0 {
++                #address-cells = <1>;
++                #size-cells = <0>;
++                compatible = "jedec,spi-nor";
++                reg = <0>; /* Chip select 0 */
++                spi-max-frequency = <10000000>;
++                status = "okay";
++                partitions {
++                        compatible = "fixed-partitions";
++                        #address-cells = <1>;
++                        #size-cells = <1>;
++                        partition@0 {
++                                label = "uboot";
++                                reg = <0x0 0x100000>;
++                        };
++                        partition@100000 {
++                                label = "env";
++                                reg = <0x100000 0x100000>;
++                        };
++                };
++        };
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>;
++	status = "disabled";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pins>;
++	status = "disabled";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
++	status = "okay";
++};
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	/* USB Type-A ports' VBUS is always on */
++	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++	usb0_vbus-supply = <&reg_usb0_vbus>;
++	status = "okay";
++};
++
++&i2s0 {
++	sound-dai = <&pcm5102a>;
++	status = "disabled";
++};
+\ No newline at end of file
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch
new file mode 100644
index 000000000000..f6b05f7022d9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch
@@ -0,0 +1,272 @@
+From 378442fb448c1b8ef354506ab44adcd19f7bd193 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 18:54:36 +0300
+Subject: arm64:dts: Add sun50i-h5-nanopi-m1-plus2 device
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h5-nanopi-m1-plus2.dts   | 240 ++++++++++++++++++
+ 2 files changed, 241 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 6c4914bb5426..c20b2419fa56 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-core2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-k1-plus.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-m1-plus2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
+new file mode 100644
+index 000000000000..d051382cc800
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
+@@ -0,0 +1,240 @@
++/*
++ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++ * Copyright (C) 2017 Armbian
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun50i-h5.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "FriendlyARM Nanopi M1 Plus 2";
++	compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		pwr {
++			label = "nanopi:green:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		status {
++			label = "nanopi:blue:status";
++			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	reg_usb0_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
++		status = "okay";
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++		post-power-on-delay-ms = <50>;
++	};
++
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii";
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@7 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <7>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	status = "okay";
++};
++
++&mmc1 {
++        vmmc-supply = <&reg_vcc3v3>;
++        vqmmc-supply = <&reg_vcc3v3>;
++        mmc-pwrseq = <&wifi_pwrseq>;
++        bus-width = <4>;
++        non-removable;
++        status = "okay";
++
++        brcmf: brcmf@1 {
++                reg = <1>;
++                compatible = "brcm,bcm4329-fmac";
++                interrupt-parent = <&pio>;
++                interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
++                interrupt-names = "host-wake";
++                pinctrl-names = "default";
++                pinctrl-0 = <&wifi_wake>;
++        };
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_8bit_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&mixer0 {
++	status = "okay";
++};
++
++&r_pio {
++	wifi_wake: wifi_wake@0 {
++		pins = "PL7";
++		function = "irq";
++		bias-pull-up;
++	};
++};
++
++&tcon0 {
++	status = "okay";
++};
++
++&r_i2c {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	/* USB Type-A port's VBUS is always on */
++	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++	usb0_vbus-supply = <&reg_usb0_vbus>;
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch
new file mode 100644
index 000000000000..712569784e0c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch
@@ -0,0 +1,242 @@
+From 615fa14df68b6ac3b141f57fae9c2899467626ab Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 18:43:42 +0300
+Subject: arm64:dts: Add sun50i-h5-nanopi-neo-core2 device
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h5-nanopi-neo-core2.dts  | 210 ++++++++++++++++++
+ 2 files changed, 211 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 63f1b3fbe4ac..bf96b7c00e6b 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-core2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-k1-plus.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
+new file mode 100644
+index 000000000000..57283cc16ad9
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
+@@ -0,0 +1,210 @@
++/*
++ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
++ * Copyright (C) 2016 ARM Ltd.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun50i-h5.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
++
++/ {
++	model = "FriendlyARM NanoPi NEO Core2";
++	compatible = "friendlyarm,nanopi-neo-core2", "allwinner,sun50i-h5";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		pwr {
++			label = "nanopi:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
++			linux,default-trigger = "default-on";
++		};
++
++		status {
++			label = "nanopi:green:status";
++			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		pinctrl-names = "default";
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		pinctrl-names = "default";
++		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpux>;
++};
++
++&codec {
++	allwinner,audio-routing =
++		"Line Out", "LINEOUT",
++		"MIC1", "Mic",
++		"Mic",  "MBIAS";
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii-id";
++	status = "okay";
++};
++
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@7 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <7>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc3v3>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	brcmf: wifi@1 {
++		reg = <1>;
++		compatible = "brcm,bcm4329-fmac";
++	};
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_8bit_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&r_i2c {
++	status = "okay";
++
++	vdd_cpux: regulator@65 {
++		compatible = "silergy,sy8106a";
++		reg = <0x65>;
++		silergy,fixed-microvolt = <1000000>;
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	/* USB Type-A ports' VBUS is always on */
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch
new file mode 100644
index 000000000000..eadf6b8e95f5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch
@@ -0,0 +1,212 @@
+From c80a123a2fd841cddfeced499c43e1d5dae14d03 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 18:49:55 +0300
+Subject: arm64:dts: Add sun50i-h5-nanopi-neo2-v1.1 device
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h5-nanopi-neo2-v1.1.dts  | 180 ++++++++++++++++++
+ 2 files changed, 181 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index bf96b7c00e6b..6c4914bb5426 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2-v1.1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-core2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
+new file mode 100644
+index 000000000000..06ffbbd29a93
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
+@@ -0,0 +1,180 @@
++/*
++ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun50i-h5.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "FriendlyARM NanoPi NEO 2";
++	compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		pwr {
++			label = "nanopi:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
++			linux,default-trigger = "default-on";
++		};
++
++		status {
++			label = "nanopi:green:status";
++			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	vdd_cpux: gpio-regulator {
++		compatible = "regulator-gpio";
++		pinctrl-names = "default";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++
++	reg_usb0_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
++		status = "okay";
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpux>;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii-id";
++	status = "okay";
++};
++
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@7 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <7>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	/* USB Type-A port's VBUS is always on */
++	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++	usb0_vbus-supply = <&reg_usb0_vbus>;
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch
new file mode 100644
index 000000000000..a25d584eead4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch
@@ -0,0 +1,99 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 14:24:40 +0300
+Subject: arm64:dts: FIXME: a64-olinuxino add regulator audio mmc
+
+Duplicate nodes appeared as a result of patching and this needs
+to be fixed and tested on the board
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 46 ++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+index 21d0bdc28766..636b64a1d8db 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+@@ -52,6 +52,13 @@ reg_usb1_vbus: usb1-vbus {
+ 		status = "okay";
+ 	};
+ 
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
+ 	wifi_pwrseq: wifi_pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+@@ -99,6 +106,10 @@ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&mixer0 {
++	status = "okay";
++};
++
+ &emac {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&rgmii_pins>;
+@@ -159,6 +170,16 @@ rtl8723bs: wifi@1 {
+ 	};
+ };
+ 
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
+ &ohci0 {
+ 	status = "okay";
+ };
+@@ -184,6 +205,7 @@ &r_pio {
+ 	 */
+ };
+ 
++/* FIXME: Duplicate node */
+ &pio {
+ 	vcc-pa-supply = <&reg_dcdc1>;
+ 	vcc-pb-supply = <&reg_dcdc1>;
+@@ -365,6 +387,30 @@ &sound_hdmi {
+ 	status = "okay";
+ };
+ 
++/* FIXME: Duplicate node
++ * &sound {
++ * 	status = "okay";
++ * 	simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
++ * 				    "Microphone", "Internal Microphone Right",
++ * 				    "Headphone", "Headphone Jack";
++ * 	simple-audio-card,aux-devs = <&codec_analog>;
++ * 	simple-audio-card,routing =
++ * 			"Left DAC", "AIF1 Slot 0 Left",
++ * 			"Right DAC", "AIF1 Slot 0 Right",
++ * 			"INL", "LINEOUT",
++ * 			"INR", "LINEOUT",
++ * 			"Headphone Jack", "HP",
++ * 			"AIF1 Slot 0 Left ADC", "Left ADC",
++ * 			"AIF1 Slot 0 Right ADC", "Right ADC",
++ * 			"Left ADC", "ADC",
++ * 			"Right ADC", "ADC",
++ * 			"Internal Microphone Left", "MBIAS",
++ * 			"MIC1", "Internal Microphone Left",
++ * 			"Internal Microphone Right", "HBIAS",
++ * 			"MIC2", "Internal Microphone Right";
++ * };
++ */
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch
new file mode 100644
index 000000000000..fb234ab0dcac
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch
@@ -0,0 +1,166 @@
+From 3a4da37c64b078259531ef7476d80c1b9afab444 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@mgmail.com>
+Date: Thu, 1 Feb 2024 22:38:21 +0000
+Subject: arm64: dts: H616: Add overlays that are also compatible with orange
+ pi zero2 and zero3
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  5 ++++
+ .../allwinner/overlay/sun50i-h616-i2c2.dtso   |  8 ++++++
+ .../allwinner/overlay/sun50i-h616-i2c3.dtso   |  8 ++++++
+ .../allwinner/overlay/sun50i-h616-i2c4.dtso   |  8 ++++++
+ .../allwinner/overlay/sun50i-h616-uart2.dtso  |  8 ++++++
+ .../allwinner/overlay/sun50i-h616-uart5.dtso  |  8 ++++++
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 26 ++++++++++++++++++-
+ 7 files changed, 70 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 84711585fc86..369b2976b1bb 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -49,6 +49,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-uart2.dtbo \
+ 	sun50i-h6-uart3.dtbo \
+ 	sun50i-h6-w1-gpio.dtbo \
++	sun50i-h616-i2c2.dtbo \
++	sun50i-h616-i2c3.dtbo \
++	sun50i-h616-i2c4.dtbo \
++	sun50i-h616-uart2.dtbo \
++	sun50i-h616-uart5.dtbo \
+ 	sun50i-h616-spi-spidev.dtbo \
+ 	sun50i-h616-spidev0_0.dtbo \
+ 	sun50i-h616-spidev1_0.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso
+new file mode 100644
+index 000000000000..feebc9ad85fb
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso
+@@ -0,0 +1,8 @@
++/dts-v1/;
++/plugin/;
++
++&i2c2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c2_ph_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso
+new file mode 100644
+index 000000000000..bb212d3c66da
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso
+@@ -0,0 +1,8 @@
++/dts-v1/;
++/plugin/;
++
++&i2c3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_ph_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso
+new file mode 100644
+index 000000000000..8fbcc658b22c
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso
+@@ -0,0 +1,8 @@
++/dts-v1/;
++/plugin/;
++
++&i2c4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c4_ph_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso
+new file mode 100644
+index 000000000000..6a6806906972
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso
+@@ -0,0 +1,8 @@
++/dts-v1/;
++/plugin/;
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+new file mode 100644
+index 000000000000..4f172489276b
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+@@ -0,0 +1,8 @@
++/dts-v1/;
++/plugin/;
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart5_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index e71b79ebced8..362c43d5eb9f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -320,11 +320,21 @@ i2c0_pins: i2c0-pins {
+ 				function = "i2c0";
+ 			};
+ 
++			i2c2_ph_pins: i2c2-ph-pins {
++				pins = "PH2", "PH3";
++				function = "i2c2";
++			};
++
+ 			i2c3_ph_pins: i2c3-ph-pins {
+ 				pins = "PH4", "PH5";
+ 				function = "i2c3";
+ 			};
+ 
++			i2c4_ph_pins: i2c4-ph-pins {
++				pins = "PH6", "PH7";
++				function = "i2c4";
++			};
++
+ 			ir_rx_pin: ir-rx-pin {
+ 				pins = "PH10";
+ 				function = "ir_rx";
+@@ -375,7 +385,6 @@ spi0_cs0_pin: spi0-cs0-pin {
+ 				function = "spi0";
+ 			};
+ 
+-			/omit-if-no-ref/
+ 			spi1_pins: spi1-pins {
+ 				pins = "PH6", "PH7", "PH8";
+ 				function = "spi1";
+@@ -414,6 +423,21 @@ x32clk_fanout_pin: x32clk-fanout-pin {
+ 				pins = "PG10";
+ 				function = "clock";
+ 			};
++
++			uart2_pins: uart2-pins {
++				pins = "PH5", "PH6";
++				function = "uart2";
++			};
++
++			uart2_rts_cts_pins: uart2-rts-cts-pins {
++				pins = "PH7", "PH8";
++				function = "uart2";
++			};
++
++			uart5_pins: uart5-pins {
++				pins = "PH2", "PH3";
++				function = "uart5";
++			};
+ 		};
+ 
+ 		gic: interrupt-controller@3021000 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch
new file mode 100644
index 000000000000..1bdb62ce7cc3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch
@@ -0,0 +1,64 @@
+From e01bc0a8b41090dabdab780763d35479e653c401 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 13 Nov 2022 23:15:38 +0300
+Subject: arm64: dts: allwiner: sun50i-h616.dtsi: add usb,ehci,ohci
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 74aed0d232a9..44f8ae11ca16 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -59,12 +59,12 @@ reserved-memory {
+ 		ranges;
+ 
+ 		/*
+-		 * 256 KiB reserved for Trusted Firmware-A (BL31).
++		 * 512 KiB reserved for Trusted Firmware-A (BL31).
+ 		 * This is added by BL31 itself, but some bootloaders fail
+ 		 * to propagate this into the DTB handed to kernels.
+ 		 */
+ 		secmon@40000000 {
+-			reg = <0x0 0x40000000 0x0 0x40000>;
++			reg = <0x0 0x40000000 0x0 0x80000>;
+ 			no-map;
+ 		};
+ 	};
+@@ -526,6 +526,8 @@ spi0: spi@5010000 {
+ 			dmas = <&dma 22>, <&dma 22>;
+ 			dma-names = "rx", "tx";
+ 			resets = <&ccu RST_BUS_SPI0>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi0_pins>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -541,6 +543,8 @@ spi1: spi@5011000 {
+ 			dmas = <&dma 23>, <&dma 23>;
+ 			dma-names = "rx", "tx";
+ 			resets = <&ccu RST_BUS_SPI1>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -778,11 +782,14 @@ r_ccu: clock@7010000 {
+ 		r_pio: pinctrl@7022000 {
+ 			compatible = "allwinner,sun50i-h616-r-pinctrl";
+ 			reg = <0x07022000 0x400>;
++			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
+ 				 <&rtc CLK_OSC32K>;
+ 			clock-names = "apb", "hosc", "losc";
+ 			gpio-controller;
+ 			#gpio-cells = <3>;
++			interrupt-controller;
++			#interrupt-cells = <3>;
+ 
+ 			/omit-if-no-ref/
+ 			r_i2c_pins: r-i2c-pins {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-Add-Overlays-for-sunxi64.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-Add-Overlays-for-sunxi64.patch
new file mode 100644
index 000000000000..151b79032b1d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-Add-Overlays-for-sunxi64.patch
@@ -0,0 +1,2491 @@
+From 57e14cc021c86e56fe492bb28899b4dc5ebb61a4 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 6 Aug 2024 20:41:29 +0300
+Subject: [PATCH] arm64:dts:allwinner: Add Overlays for sunxi64
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   2 +
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  59 +++++
+ .../overlay/README.sun50i-a64-overlays        | 196 ++++++++++++++
+ .../overlay/README.sun50i-h5-overlays         | 250 ++++++++++++++++++
+ .../overlay/sun50i-a64-fixup.scr-cmd          |  95 +++++++
+ .../allwinner/overlay/sun50i-a64-i2c0.dtso    |  32 +++
+ .../allwinner/overlay/sun50i-a64-i2c1.dtso    |  22 ++
+ .../overlay/sun50i-a64-pps-gpio.dtso          |  29 ++
+ .../overlay/sun50i-a64-spi-add-cs1.dtso       |  41 +++
+ .../overlay/sun50i-a64-spi-jedec-nor.dtso     |  34 +++
+ .../overlay/sun50i-a64-spi-spidev.dtso        |  42 +++
+ .../allwinner/overlay/sun50i-a64-uart1.dtso   |  22 ++
+ .../allwinner/overlay/sun50i-a64-uart2.dtso   |  37 +++
+ .../allwinner/overlay/sun50i-a64-uart3.dtso   |  32 +++
+ .../allwinner/overlay/sun50i-a64-uart4.dtso   |  37 +++
+ .../allwinner/overlay/sun50i-a64-w1-gpio.dtso |  29 ++
+ .../overlay/sun50i-h5-analog-codec.dtso       |  17 ++
+ .../dts/allwinner/overlay/sun50i-h5-cir.dtso  |  15 ++
+ .../allwinner/overlay/sun50i-h5-fixup.scr-cmd | 110 ++++++++
+ .../dts/allwinner/overlay/sun50i-h5-i2c0.dtso |  20 ++
+ .../dts/allwinner/overlay/sun50i-h5-i2c1.dtso |  20 ++
+ .../dts/allwinner/overlay/sun50i-h5-i2c2.dtso |  20 ++
+ .../allwinner/overlay/sun50i-h5-pps-gpio.dtso |  29 ++
+ .../dts/allwinner/overlay/sun50i-h5-pwm.dtso  |  39 +++
+ .../overlay/sun50i-h5-spdif-out.dtso          |  38 +++
+ .../overlay/sun50i-h5-spi-add-cs1.dtso        |  41 +++
+ .../overlay/sun50i-h5-spi-jedec-nor.dtso      |  42 +++
+ .../overlay/sun50i-h5-spi-spidev.dtso         |  42 +++
+ .../allwinner/overlay/sun50i-h5-uart1.dtso    |  22 ++
+ .../allwinner/overlay/sun50i-h5-uart2.dtso    |  32 +++
+ .../allwinner/overlay/sun50i-h5-uart3.dtso    |  32 +++
+ .../allwinner/overlay/sun50i-h5-usbhost0.dtso |  27 ++
+ .../allwinner/overlay/sun50i-h5-usbhost1.dtso |  27 ++
+ .../allwinner/overlay/sun50i-h5-usbhost2.dtso |  27 ++
+ .../allwinner/overlay/sun50i-h5-usbhost3.dtso |  27 ++
+ .../allwinner/overlay/sun50i-h5-w1-gpio.dtso  |  29 ++
+ .../allwinner/overlay/sun50i-h6-fixup.scr-cmd |  96 +++++++
+ .../dts/allwinner/overlay/sun50i-h6-i2c0.dtso |  20 ++
+ .../dts/allwinner/overlay/sun50i-h6-i2c1.dtso |  20 ++
+ .../dts/allwinner/overlay/sun50i-h6-i2c2.dtso |  20 ++
+ .../dts/allwinner/overlay/sun50i-h6-pwm.dtso  |  25 ++
+ .../allwinner/overlay/sun50i-h6-ruart.dtso    |  13 +
+ .../overlay/sun50i-h6-spi-add-cs1.dtso        |  41 +++
+ .../overlay/sun50i-h6-spi-jedec-nor.dtso      |  42 +++
+ .../overlay/sun50i-h6-spi-spidev.dtso         |  42 +++
+ .../overlay/sun50i-h6-spi-spidev1.dtso        |  30 +++
+ .../allwinner/overlay/sun50i-h6-uart1.dtso    |  22 ++
+ .../allwinner/overlay/sun50i-h6-uart2.dtso    |  32 +++
+ .../allwinner/overlay/sun50i-h6-uart3.dtso    |  32 +++
+ .../allwinner/overlay/sun50i-h6-w1-gpio.dtso  |  29 ++
+ 50 files changed, 2079 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/Makefile
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index c20b2419fa56..6ba94dea8027 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -52,3 +52,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-transpeed-8k618-t.dtb
++
++subdir-y	:= $(dts-dirs) overlay
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+new file mode 100644
+index 000000000000..d0a15e720a7e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -0,0 +1,59 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_SUNXI) += \
++	sun50i-a64-i2c0.dtbo \
++	sun50i-a64-i2c1.dtbo \
++	sun50i-a64-pps-gpio.dtbo \
++	sun50i-a64-spi-add-cs1.dtbo \
++	sun50i-a64-spi-jedec-nor.dtbo \
++	sun50i-a64-spi-spidev.dtbo \
++	sun50i-a64-uart1.dtbo \
++	sun50i-a64-uart2.dtbo \
++	sun50i-a64-uart3.dtbo \
++	sun50i-a64-uart4.dtbo \
++	sun50i-a64-w1-gpio.dtbo \
++	sun50i-h5-analog-codec.dtbo \
++	sun50i-h5-cir.dtbo \
++	sun50i-h5-i2c0.dtbo \
++	sun50i-h5-i2c1.dtbo \
++	sun50i-h5-i2c2.dtbo \
++	sun50i-h5-pps-gpio.dtbo \
++	sun50i-h5-pwm.dtbo \
++	sun50i-h5-spdif-out.dtbo \
++	sun50i-h5-spi-add-cs1.dtbo \
++	sun50i-h5-spi-jedec-nor.dtbo \
++	sun50i-h5-spi-spidev.dtbo \
++	sun50i-h5-uart1.dtbo \
++	sun50i-h5-uart2.dtbo \
++	sun50i-h5-uart3.dtbo \
++	sun50i-h5-usbhost0.dtbo \
++	sun50i-h5-usbhost1.dtbo \
++	sun50i-h5-usbhost2.dtbo \
++	sun50i-h5-usbhost3.dtbo \
++	sun50i-h5-w1-gpio.dtbo \
++	sun50i-h6-i2c0.dtbo \
++	sun50i-h6-i2c1.dtbo \
++	sun50i-h6-i2c2.dtbo \
++	sun50i-h6-pwm.dtbo \
++	sun50i-h6-ruart.dtbo \
++	sun50i-h6-spi-add-cs1.dtbo \
++	sun50i-h6-spi-jedec-nor.dtbo \
++	sun50i-h6-spi-spidev.dtbo \
++	sun50i-h6-spi-spidev1.dtbo \
++	sun50i-h6-uart1.dtbo \
++	sun50i-h6-uart2.dtbo \
++	sun50i-h6-uart3.dtbo \
++	sun50i-h6-w1-gpio.dtbo
++
++scr-$(CONFIG_ARCH_SUNXI) += \
++	sun50i-a64-fixup.scr \
++	sun50i-h5-fixup.scr \
++	sun50i-h6-fixup.scr
++
++dtbotxt-$(CONFIG_ARCH_SUNXI) += \
++	README.sun50i-a64-overlays \
++	README.sun50i-h5-overlays
++
++targets += $(dtb-y) $(scr-y) $(dtbotxt-y)
++
++always		:= $(dtb-y) $(scr-y) $(dtbotxt-y)
++clean-files	:= *.dtbo *.scr
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
+new file mode 100644
+index 000000000000..cd9dbc686412
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
+@@ -0,0 +1,196 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/Hardware_Allwinner_overlays/
++
++### Platform:
++
++sun50i-a64 (Allwinner A64)
++
++### Platform details:
++
++Supported pin banks: PB, PC, PD, PH
++
++Both SPI controllers have only one hardware CS pin exposed,
++adding fixed software (GPIO) chip selects is possible with a separate overlay
++
++I2C controller 2 (PE14, PE15) pins are used for non-I2C CSI functions or are not available
++on supported boards, so this controller is not supported in provided overlays
++
++### Provided overlays:
++
++- i2c0
++- i2c1
++- pps-gpio
++- spi-add-cs1
++- spi-jedec-nor
++- spi-spidev
++- uart1
++- uart2
++- uart3
++- uart4
++- w1-gpio
++
++### Overlay details:
++
++### i2c0
++
++Activates TWI/I2C bus 0
++
++I2C0 pins (SCL, SDA): PH0, PH1
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PH2, PH3
++
++### pps-gpio
++
++Activates pulse-per-second GPIO client
++
++Parameters:
++
++param_pps_pin (pin)
++	Pin PPS source is connected to
++	Optional
++	Default: PD4
++
++param_pps_falling_edge (bool)
++	Assert by falling edge
++	Optional
++	Default: 0
++	When set (to 1), assert is indicated by a falling edge
++		(instead of by a rising edge)
++
++### spi-add-cs1
++
++Adds support for using SPI chip select 1 with GPIO for both SPI controllers
++Respective GPIO will be claimed only if controller is enabled by another overlay
++This overlay is required for using chip select 1 with other SPI overlays
++
++SPI 0 pins (CS1): PB6
++SPI 1 pins (CS1): PD6
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1
++
++param_spinor_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate SPIdev support on
++	Required
++	Supported values: 0, 1
++
++param_spidev_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart1
++
++Activates serial port 1 (/dev/ttyS1)
++
++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
++
++Parameters:
++
++param_uart1_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PB0, PB1, PB2, PB3
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins (TX, RX): PD0, PD1
++
++### uart4
++
++Activates serial port 4 (/dev/ttyS4)
++
++UART 4 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### w1-gpio
++
++Activates 1-Wire GPIO master
++Requires external pull-up resistor on data pin
++
++Parameters:
++
++param_w1_pin (pin)
++	Data pin for 1-Wire master
++	Optional
++	Default: PD4
++
++param_w1_pin_int_pullup (bool)
++	Enable internal pull-up for the data pin
++	Optional
++	Default: 0
++	Set to 1 to enable the pull-up
++	This option should not be used with multiple devices, parasite power setup
++		or long wires -	please use external pull-up resistor instead
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+new file mode 100644
+index 000000000000..1ac7fbcf62d1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+@@ -0,0 +1,250 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++sun50i-h5 (Allwinner H5)
++
++### Platform details:
++
++Supported pin banks: PA, PC, PD, PG
++
++Both SPI controllers have only one hardware CS pin exposed,
++adding fixed software (GPIO) chip selects is possible with a separate overlay
++
++### Provided overlays:
++
++- analog-codec
++- cir
++- i2c0
++- i2c1
++- i2c2
++- pps-gpio
++- pwm
++- spdif-out
++- spi-add-cs1
++- spi-jedec-nor
++- spi-spidev
++- uart1
++- uart2
++- uart3
++- usbhost0
++- usbhost1
++- usbhost2
++- usbhost3
++- w1-gpio
++
++### Overlay details:
++
++### analog-codec
++
++Activates SoC analog codec driver that provides Line Out and Mic In
++functionality
++
++### cir
++
++Activates CIR (Infrared remote) receiver
++
++CIR pin: PL11
++
++### i2c0
++
++Activates TWI/I2C bus 0
++
++I2C0 pins (SCL, SDA): PA11, PA12
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PA18, PA19
++
++### i2c2
++
++Activates TWI/I2C bus 2
++
++I2C2 pins (SCL, SDA): PE12, PE13
++
++On most board this bus is wired to Camera (CSI) socket
++
++### pps-gpio
++
++Activates pulse-per-second GPIO client
++
++Parameters:
++
++param_pps_pin (pin)
++	Pin PPS source is connected to
++	Optional
++	Default: PD14
++
++param_pps_falling_edge (bool)
++	Assert by falling edge
++	Optional
++	Default: 0
++	When set (to 1), assert is indicated by a falling edge
++		(instead of by a rising edge)
++
++### pwm
++
++Activates hardware PWM controller
++
++PWM pin: PA5
++
++Pin PA5 is used as UART0 RX by default, so if this overlay is activated,
++UART0 and kernel console on ttyS0 will be disabled
++
++### spdif-out
++
++Activates SPDIF/Toslink audio output
++
++SPDIF pin: PA17
++
++### spi-add-cs1
++
++Adds support for using SPI chip select 1 with GPIO for both SPI controllers
++Respective GPIO will be claimed only if controller is enabled by another
++overlay
++This overlay is required for using chip select 1 with other SPI overlays
++Due to the u-boot limitations CS1 pin can't be customized by a parameter, but
++it can be changed by using an edited copy of this overlay
++A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO)
++
++SPI 0 pins (CS1): PA21
++SPI 1 pins (CS1): PA10
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1
++
++param_spinor_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate SPIdev support on
++	Required
++	Supported values: 0, 1
++
++param_spidev_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart1
++
++Activates serial port 1 (/dev/ttyS1)
++
++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
++
++Parameters:
++
++param_uart1_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16
++
++Parameters:
++
++param_uart3_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### usbhost0
++
++Activates USB host controller 0
++
++### usbhost1
++
++Activates USB host controller 1
++
++### usbhost2
++
++Activates USB host controller 2
++
++### usbhost3
++
++Activates USB host controller 3
++
++### w1-gpio
++
++Activates 1-Wire GPIO master
++Requires an external pull-up resistor on the data pin
++or enabling the internal pull-up
++
++Parameters:
++
++param_w1_pin (pin)
++	Data pin for 1-Wire master
++	Optional
++	Default: PD14
++
++param_w1_pin_int_pullup (bool)
++	Enable internal pull-up for the data pin
++	Optional
++	Default: 0
++	Set to 1 to enable the pull-up
++	This option should not be used with multiple devices, parasite power setup
++		or long wires -	please use external pull-up resistor instead
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd
+new file mode 100644
+index 000000000000..9b34c05ecf18
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd
+@@ -0,0 +1,95 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|H)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "B" && setenv tmp_bank 1;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "H" && setenv tmp_bank 7'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>";
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>";
++	fi
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@1c28400 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@1c28800 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart4_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart4-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart4-rts-cts-pins phandle
++	fdt set /soc/serial@1c29000 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c29000 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dtso
+new file mode 100644
+index 000000000000..37bdb2c2fae3
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c0 = "/soc/i2c@1c2ac00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			i2c0_pins: i2c0_pins {
++				pins = "PH0", "PH1";
++				function = "i2c0";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&i2c0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c0_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dtso
+new file mode 100644
+index 000000000000..b2483c9cd7b2
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dtso
+new file mode 100644
+index 000000000000..5fa161c4718e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pps_pins: pps_pins {
++				pins = "PD4";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			pps@0 {
++				compatible = "pps-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&pps_pins>;
++				gpios = <&pio 3 4 0>; /* PD4 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dtso
+new file mode 100644
+index 000000000000..4432aac51f2e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dtso
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			spi0_cs1: spi0_cs1 {
++				pins = "PB6";
++				function = "gpio_out";
++				output-high;
++			};
++
++			spi1_cs1: spi1_cs1 {
++				pins = "PD6";
++				function = "gpio_out";
++				output-high;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi0_cs1>;
++			cs-gpios = <0>, <&pio 1 6 0>; /* PB6 */
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi1_cs1>;
++			cs-gpios = <0>, <&pio 3 6 0>; /* PD6 */
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..31d73e572281
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dtso
+@@ -0,0 +1,34 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dtso
+new file mode 100644
+index 000000000000..84a435b79bee
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c68000";
++			spi1 = "/soc/spi@1c69000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dtso
+new file mode 100644
+index 000000000000..4d8dac1a59cb
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial1 = "/soc/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart1>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dtso
+new file mode 100644
+index 000000000000..7286d7360df1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dtso
+@@ -0,0 +1,37 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart2_pins: uart2-pins {
++				pins = "PB0", "PB1";
++				function = "uart2";
++			};
++
++			uart2_rts_cts_pins: uart2-rts-cts-pins {
++				pins = "PB2", "PB3";
++				function = "uart2";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dtso
+new file mode 100644
+index 000000000000..c5729b9d2568
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart3_pins: uart3-pins {
++				pins = "PD0", "PD1";
++				function = "uart3";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dtso
+new file mode 100644
+index 000000000000..21c9b738aa93
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dtso
+@@ -0,0 +1,37 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial4 = "/soc/serial@1c29000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart4_pins: uart4-pins {
++				pins = "PD2", "PD3";
++				function = "uart4";
++			};
++
++			uart4_rts_cts_pins: uart4-rts-cts-pins {
++				pins = "PD4", "PD5";
++				function = "uart4";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart4>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart4_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dtso
+new file mode 100644
+index 000000000000..d230469135de
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PD4";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 3 4 0>; /* PD4 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dtso
+new file mode 100644
+index 000000000000..aaa66d5e7ca1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dtso
+@@ -0,0 +1,17 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&codec>;
++		__overlay__ {
++			allwinner,audio-routing =
++				"Line Out", "LINEOUT",
++				"MIC1", "Mic",
++				"Mic",  "MBIAS";
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dtso
+new file mode 100644
+index 000000000000..90c264a0ab78
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&ir>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&r_ir_rx_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd
+new file mode 100644
+index 000000000000..7abb64d84a8a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd
+@@ -0,0 +1,110 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "A" && setenv tmp_bank 0;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++for f in ${overlays}; do
++	if test "${f}" = "pwm"; then
++		setenv bootargs_new ""
++		for arg in ${bootargs}; do
++			if test "${arg}" = "console=ttyS0,115200"; then
++				echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
++			else
++				setenv bootargs_new "${bootargs_new} ${arg}"
++			fi
++		done
++		setenv bootargs "${bootargs_new}"
++	fi
++done
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@1c28400 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@1c28800 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-rts-cts-pins phandle
++	fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dtso
+new file mode 100644
+index 000000000000..87fbd7e51a11
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c0 = "/soc/i2c@1c2ac00";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dtso
+new file mode 100644
+index 000000000000..6008b9a0853e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dtso
+new file mode 100644
+index 000000000000..2980dbf34300
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dtso
+new file mode 100644
+index 000000000000..46e067562e3d
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pps_pins: pps_pins {
++				pins = "PD14";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			pps@0 {
++				compatible = "pps-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&pps_pins>;
++				gpios = <&pio 3 14 0>; /* PD14 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dtso
+new file mode 100644
+index 000000000000..6d12e8420de9
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dtso
+@@ -0,0 +1,39 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/chosen";
++		__overlay__ {
++			/delete-property/ stdout-path;
++		};
++	};
++
++	fragment@1 {
++		target = <&uart0>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++
++	fragment@2 {
++		target = <&pio>;
++		__overlay__ {
++			pwm0_pin: pwm0 {
++				pins = "PA5";
++				function = "pwm0";
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm0_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dtso
+new file mode 100644
+index 000000000000..65bc51b0218e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&spdif>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&spdif_tx_pin>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			sound {
++				compatible = "simple-audio-card";
++				simple-audio-card,name = "On-board SPDIF";
++
++				simple-audio-card,cpu {
++					sound-dai = <&spdif>;
++				};
++
++				simple-audio-card,codec {
++					sound-dai = <&spdif_out>;
++				};
++			};
++
++			spdif_out: spdif-out {
++				#sound-dai-cells = <0>;
++				compatible = "linux,spdif-dit";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dtso
+new file mode 100644
+index 000000000000..8e3eab295f49
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dtso
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			spi0_cs1: spi0_cs1 {
++				pins = "PA21";
++				function = "gpio_out";
++				output-high;
++			};
++
++			spi1_cs1: spi1_cs1 {
++				pins = "PA10";
++				function = "gpio_out";
++				output-high;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi0_cs1>;
++			cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi1_cs1>;
++			cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..5a45808c11a5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c68000";
++			spi1 = "/soc/spi@1c69000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dtso
+new file mode 100644
+index 000000000000..69a14b2c60e4
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c68000";
++			spi1 = "/soc/spi@1c69000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dtso
+new file mode 100644
+index 000000000000..92e3eb4d9b66
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial1 = "/soc/serial@1c28400";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart1>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dtso
+new file mode 100644
+index 000000000000..92bee1a9600a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart2_rts_cts: uart2-rts-cts-pins {
++				pins = "PA2", "PA3";
++				function = "uart2";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dtso
+new file mode 100644
+index 000000000000..a2197f1668fb
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart3_rts_cts: uart3-rts-cts-pins {
++				pins = "PA15", "PA16";
++				function = "uart3";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dtso
+new file mode 100644
+index 000000000000..c1d79c232fa4
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&ehci0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci0>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dtso
+new file mode 100644
+index 000000000000..2b4f245bf297
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&ehci1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dtso
+new file mode 100644
+index 000000000000..54800e729538
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&ehci2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci2>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dtso
+new file mode 100644
+index 000000000000..a99524ea38f3
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&ehci3>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci3>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dtso
+new file mode 100644
+index 000000000000..6e99626ac660
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PD14";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 3 14 0>; /* PD14 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
+new file mode 100644
+index 000000000000..f757db7aa4ad
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
+@@ -0,0 +1,96 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "A" && setenv tmp_bank 0;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@300b000/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@300b000 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@300b000/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@300b000 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@300b000/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@5000400 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@5000800 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart3-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart3-rts-cts-pins phandle
++	fdt set /soc/serial@5000c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000c00 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000c00 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dtso
+new file mode 100644
+index 000000000000..7e7ee8c46e9c
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c0 = "/soc/i2c@5002000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dtso
+new file mode 100644
+index 000000000000..111769821262
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc/i2c@5002400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dtso
+new file mode 100644
+index 000000000000..b627529c2144
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc/i2c@5002800";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dtso
+new file mode 100644
+index 000000000000..a8aa74ed1988
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dtso
+@@ -0,0 +1,25 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6-pwm";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pwm_pin: pwm-pin {
++				pins = "PD22";
++				function = "pwm";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dtso
+new file mode 100644
+index 000000000000..6430cb083370
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target = <&r_uart>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dtso
+new file mode 100644
+index 000000000000..0fa060fa1eff
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dtso
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			spi0_cs1: spi0_cs1 {
++				pins = "PA10";
++				function = "gpio_out";
++				output-high;
++			};
++
++			spi1_cs1: spi1_cs1 {
++				pins = "PA21";
++				function = "gpio_out";
++				output-high;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi0_cs1>;
++			cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi1_cs1>;
++			cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..4f81dbb9924c
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@5010000";
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dtso
+new file mode 100644
+index 000000000000..1f077ea80ae5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3-spi";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@5010000";
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dtso
+new file mode 100644
+index 000000000000..5e6b70530fae
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dtso
+@@ -0,0 +1,30 @@
++// Enable the spidev interface
++/dts-v1/;
++/plugin/;
++
++/ {
++    compatible = "allwinner,sun8i-h3-spi";
++
++    fragment@0 {
++	target-path = "/aliases";
++	__overlay__ {
++            /* Path to the SPI controller nodes */
++            spi1 = "/soc/spi@5011000";
++        };
++    };
++    fragment@1 {
++        target = <&spi1>;
++        __overlay__ {
++            pinctrl-names = "default";
++            pinctrl-0 = <&spi1_pins>;
++            status = "okay";
++            #address-cells = <1>;
++            #size-cells = <0>;
++            spidev@0 {
++                compatible = "armbian,spi-dev";
++                reg = <0x0>;
++                spi-max-frequency = <1000000>;
++            };
++        };
++    };
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dtso
+new file mode 100644
+index 000000000000..44aa94efdad1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial1 = "/soc/serial@5000400";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart1>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dtso
+new file mode 100644
+index 000000000000..bf9174bcd2e6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc/serial@5000800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart2_rts_cts: uart2-rts-cts-pins {
++				pins = "PD21", "PD22";
++				function = "uart2";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dtso
+new file mode 100644
+index 000000000000..418edc14a0e4
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc/serial@5000c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart3_rts_cts: uart3-rts-cts-pins {
++				pins = "PD25", "PD26";
++				function = "uart3";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dtso
+new file mode 100644
+index 000000000000..3043c87780e4
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PC9";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 2 9 0>; /* PC9 */
++				status = "okay";
++			};
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch
new file mode 100644
index 000000000000..05c17e33497e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch
@@ -0,0 +1,144 @@
+From 9b78c14249134a95616781690f51f7c7a2801548 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:40:20 +0200
+Subject: arm64: dts: allwinner: h6: Add AC200 EPHY nodes
+
+All Allwinner H6 SoCs feature a co-packaged AC200 die, which replaces
+the integrated PHY and audio circuitry of its H3/H5 predecessors. It is
+using an internal I2C connection, but otherwise pretty much behaves as
+it would be externally connected.
+
+Since every H6 SoC contains this chip, add the required DT nodes to the
+SoC .dtsi, but keep them disabled. This is for now just covering the
+AC200 MFD parent and its EPHY child.
+Any board making use of one of the integrated PHY needs to enable it and
+connect the MAC and PHY accordingly.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 73 ++++++++++++++++++++
+ 1 file changed, 73 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 279206b364ea..107ec6b979ff 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -24,6 +24,16 @@ aliases {
+ 		mmc2 = &mmc2;
+ 	};
+ 
++	ac200_pwm_clk: ac200_clk {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		clock-frequency = <24000000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pwm1_pin>;
++		pwms = <&pwm 1 42 0>;
++		status = "disabled";
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -334,6 +344,14 @@ ths_calibration: thermal-sensor-calibration@14 {
+ 			cpu_speed_grade: cpu-speed-grade@1c {
+ 				reg = <0x1c 0x4>;
+ 			};
++
++			ephy_calib: ephy_calib@2c {
++				reg = <0x2c 0x2>;
++			};
++
++			ac200_bg: ac200_bg@30 {
++				reg = <0x30 0x2>;
++			};
+ 		};
+ 
+ 		timer@3009000 {
+@@ -389,6 +407,13 @@ ext_rgmii_pins: rgmii-pins {
+ 				drive-strength = <40>;
+ 			};
+ 
++			ext_rmii_pins: rmii_pins {
++				pins = "PA0", "PA1", "PA2", "PA3", "PA4",
++				       "PA5", "PA6", "PA7", "PA8", "PA9";
++				function = "emac";
++				drive-strength = <40>;
++			};
++
+ 			hdmi_pins: hdmi-pins {
+ 				pins = "PH8", "PH9", "PH10";
+ 				function = "hdmi";
+@@ -409,6 +434,12 @@ i2c2_pins: i2c2-pins {
+ 				function = "i2c2";
+ 			};
+ 
++			i2c3_pins: i2c3-pins {
++				pins = "PB17", "PB18";
++				function = "i2c3";
++				bias-pull-up;
++			};
++
+ 			mmc0_pins: mmc0-pins {
+ 				pins = "PF0", "PF1", "PF2", "PF3",
+ 				       "PF4", "PF5";
+@@ -436,6 +467,11 @@ mmc2_pins: mmc2-pins {
+ 				bias-pull-up;
+ 			};
+ 
++			pwm1_pin: pwm1-pin {
++				pins = "PB19";
++				function = "pwm1";
++			};
++
+ 			/omit-if-no-ref/
+ 			spi0_pins: spi0-pins {
+ 				pins = "PC0", "PC2", "PC3";
+@@ -648,6 +684,43 @@ i2c2: i2c@5002800 {
+ 			#size-cells = <0>;
+ 		};
+ 
++		i2c3: i2c@5002c00 {
++			compatible = "allwinner,sun50i-h6-i2c",
++				     "allwinner,sun6i-a31-i2c";
++			reg = <0x05002c00 0x400>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C3>;
++			resets = <&ccu RST_BUS_I2C3>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c3_pins>;
++			clock-frequency = <100000>;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			ac200: mfd@10 {
++				compatible = "x-powers,ac200";
++				reg = <0x10>;
++				clocks = <&ac200_pwm_clk>;
++				interrupt-parent = <&pio>;
++				interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>;
++				interrupt-controller;
++				#interrupt-cells = <1>;
++				nvmem-cells = <&ac200_bg>;
++				nvmem-cell-names = "bandgap";
++
++				ac200_ephy_ctl: syscon {
++					compatible = "x-powers,ac200-ephy-ctl";
++					nvmem-cells = <&ephy_calib>;
++					nvmem-cell-names = "calibration";
++					#clock-cells = <0>;
++					#reset-cells = <0>;
++					phy-mode = "rmii";
++					status = "disabled";
++				};
++			};
++		};
++
+ 		spi0: spi@5010000 {
+ 			compatible = "allwinner,sun50i-h6-spi",
+ 				     "allwinner,sun8i-h3-spi";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch
new file mode 100644
index 000000000000..52d07f07ba5b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch
@@ -0,0 +1,87 @@
+From eb9de352b9187f9a271e390d2d8458772abf8989 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Thu, 1 Sep 2022 17:45:03 +0200
+Subject: arm64: dts: allwinner: h6: add AC200 codec nodes
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 42 ++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 107ec6b979ff..d0e181e17627 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -24,6 +24,22 @@ aliases {
+ 		mmc2 = &mmc2;
+ 	};
+ 
++	analog: analog-codec {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "ac200-audio";
++		simple-audio-card,mclk-fs = <512>;
++		status = "disabled";
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s3>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&ac200_codec>;
++		};
++	};
++
+ 	ac200_pwm_clk: ac200_clk {
+ 		compatible = "pwm-clock";
+ 		#clock-cells = <0>;
+@@ -440,6 +456,11 @@ i2c3_pins: i2c3-pins {
+ 				bias-pull-up;
+ 			};
+ 
++			i2s3_pins: i2s3-pins {
++				pins = "PB12", "PB13", "PB14", "PB15", "PB16";
++				function = "i2s3";
++			};
++
+ 			mmc0_pins: mmc0-pins {
+ 				pins = "PF0", "PF1", "PF2", "PF3",
+ 				       "PF4", "PF5";
+@@ -718,6 +739,12 @@ ac200_ephy_ctl: syscon {
+ 					phy-mode = "rmii";
+ 					status = "disabled";
+ 				};
++
++				ac200_codec: codec {
++					#sound-dai-cells = <0>;
++					compatible = "x-powers,ac200-codec";
++					status = "disabled";
++				};
+ 			};
+ 		};
+ 
+@@ -775,6 +802,21 @@ mdio: mdio {
+ 			};
+ 		};
+ 
++		i2s3: i2s@508f000 {
++			#sound-dai-cells = <0>;
++			compatible = "allwinner,sun50i-h6-i2s";
++			reg = <0x0508f000 0x1000>;
++			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2S3>, <&ccu CLK_I2S3>;
++			clock-names = "apb", "mod";
++			dmas = <&dma 6>, <&dma 6>;
++			resets = <&ccu RST_BUS_I2S3>;
++			dma-names = "rx", "tx";
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2s3_pins>;
++			status = "disabled";
++		};
++
+ 		i2s1: i2s@5091000 {
+ 			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-h6-i2s";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch
new file mode 100644
index 000000000000..3671238c733b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch
@@ -0,0 +1,142 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Thu, 1 Sep 2022 17:49:28 +0200
+Subject: arm64: dts: allwinner: h6: enable AC200 codec
+
+Enable AC200 analog codec on H6 based boards where present.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts     | 25 ++++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts       | 25 ++++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts | 14 ++++++
+ 3 files changed, 64 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index 5e3405408244..871020167557 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -104,6 +104,19 @@ wifi_pwrseq: wifi-pwrseq {
+ 	};
+ };
+ 
++&ac200_codec {
++	avcc-supply = <&reg_aldo2>;
++	status = "okay";
++};
++
++&ac200_pwm_clk {
++	status = "okay";
++};
++
++&analog {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdca>;
+ };
+@@ -172,6 +185,14 @@ ext_rgmii_phy: ethernet-phy@1 {
+ 	};
+ };
+ 
++&i2c3 {
++	status = "okay";
++};
++
++&i2s3 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+@@ -219,6 +240,10 @@ &pio {
+ 	vcc-pg-supply = <&reg_vcc_wifi_io>;
+ };
+ 
++&pwm {
++	status = "okay";
++};
++
+ &r_ir {
+ 	status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+index 454d2a2974c9..5bb973ea3fb4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+@@ -93,6 +93,19 @@ &dwc3 {
+ 	status = "okay";
+ };
+ 
++&ac200_codec {
++	avcc-supply = <&reg_aldo2>;
++	status = "okay";
++};
++
++&ac200_pwm_clk {
++	status = "okay";
++};
++
++&analog {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdca>;
+ };
+@@ -139,6 +152,14 @@ &i2s1 {
+ 	status = "okay";
+ };
+ 
++&i2c3 {
++	status = "okay";
++};
++
++&i2s3 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -195,6 +216,10 @@ &pio {
+ 	vcc-pg-supply = <&reg_aldo1>;
+ };
+ 
++&pwm {
++	status = "okay";
++};
++
+ &r_i2c {
+ 	status = "okay";
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts
+index 08d84160d88f..931e8b99fd93 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts
+@@ -10,6 +10,20 @@ / {
+ 	compatible = "oranth,tanix-tx6-mini", "allwinner,sun50i-h6";
+ };
+ 
++
++&ac200_codec {
++	avcc-supply = <&reg_vcc3v3>;
++	status = "okay";
++};
++
++&analog {
++	status = "okay";
++};
++
++&i2s3 {
++	status = "okay";
++};
++
+ &r_ir {
+ 	linux,rc-map-name = "rc-tanix-tx3mini";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch
new file mode 100644
index 000000000000..df155ba22eab
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch
@@ -0,0 +1,97 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sat, 24 Aug 2019 01:03:05 +0200
+Subject: arm64: dts: allwinner: h6: tanix: enable Ethernet
+
+Tanix-TX6 and TX6 mini boards provide an 100MBit/s Ethernet port, which
+uses the EPHY integrated into the Allwinner H6 SoC.
+
+Enable the MAC node, plus the required AC200 nodes to allow configuring
+and enabling the integrated PHY.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi | 38 ++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
+index 4903d6358112..51a75debab44 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
+@@ -10,6 +10,7 @@
+ 
+ / {
+ 	aliases {
++		ethernet0 = &emac;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -84,6 +85,16 @@ wifi_pwrseq: wifi-pwrseq {
+ 	};
+ };
+ 
++&ac200_ephy_ctl {
++	x-powers,led-polarity = <GPIO_ACTIVE_HIGH>;
++	phy-address = <1>;
++	status = "okay";
++};
++
++&ac200_pwm_clk {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_vdd_cpu_gpu>;
+ };
+@@ -104,6 +115,14 @@ &ehci3 {
+ 	status = "okay";
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&ext_rmii_phy>;
++	status = "okay";
++};
++
+ &gpu {
+ 	mali-supply = <&reg_vdd_cpu_gpu>;
+ 	status = "okay";
+@@ -119,6 +138,21 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2c3 {
++	status = "okay";
++};
++
++&mdio {
++	ext_rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-id0044.1400",
++			     "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++		resets = <&ac200_ephy_ctl>;
++		reset-names = "phy";
++		clocks = <&ac200_ephy_ctl>;
++	};
++};
++
+ &mmc0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&mmc0_pins>;
+@@ -161,6 +195,10 @@ &pio {
+ 	vcc-pg-supply = <&reg_vcc1v8>;
+ };
+ 
++&pwm {
++	status = "okay";
++};
++
+ &r_ir {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-Add-device-node-for-SID.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-Add-device-node-for-SID.patch
new file mode 100644
index 000000000000..5ad4218cc24b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-Add-device-node-for-SID.patch
@@ -0,0 +1,30 @@
+From 1f1974f4bd665193ef98b8cfe8158badaedbe760 Mon Sep 17 00:00:00 2001
+From: Kali Prasad <kprasadvnsi@protonmail.com>
+Date: Sun, 19 Sep 2021 08:02:27 +0000
+Subject: arm64: dts: allwinner: h616: Add device node for SID
+
+The device tree binding for H616's SID controller.
+
+Signed-off-by: Kali Prasad <kprasadvnsi@protonmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index a1eead46e68c..7ec3d5dbad35 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -191,6 +191,10 @@ sid: efuse@3006000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 
++			cpu_speed_grade: cpu-speed-grade@0 {
++				reg = <0x00 0x02>;
++			};
++
+ 			ths_calibration: thermal-sensor-calibration@14 {
+ 				reg = <0x14 0x8>;
+ 			};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-.patch
new file mode 100644
index 000000000000..8d1bc86d5f2d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-.patch
@@ -0,0 +1,474 @@
+From c15cdd5568126541113d6970018f449ed44f2288 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Tue, 23 May 2023 16:43:00 +0000
+Subject: arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2
+ arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+ arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+ drivers/cpufreq/cpufreq-dt-platdev.c drivers/cpufreq/sun50i-cpufreq-nvmem.c
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+---
+ .../dts/allwinner/sun50i-h616-cpu-opp.dtsi    | 75 +++++++++++++++
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  |  1 +
+ .../allwinner/sun50i-h616-orangepi-zero2.dts  |  5 +
+ .../dts/allwinner/sun50i-h618-cpu-dvfs.dtsi   | 64 +++++++++++++
+ .../allwinner/sun50i-h618-orangepi-zero3.dts  | 62 ++-----------
+ drivers/cpufreq/cpufreq-dt-platdev.c          |  2 +
+ drivers/cpufreq/sun50i-cpufreq-nvmem.c        | 92 ++++++++++++++-----
+ 7 files changed, 221 insertions(+), 80 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+new file mode 100644
+index 000000000000..36f2950367c6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
+@@ -0,0 +1,75 @@
++//SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++//Testing Version 1  from: AGM1968 <AGM1968@users.noreply.github.com>
++//Noted: PLL_CPUX = 24 MHz*N/P (WIP)
++
++/ {
++	cpu_opp_table: opp-table-cpu {
++		compatible = "allwinner,sun50i-h616-operating-points";
++		nvmem-cells = <&cpu_speed_grade>;
++		opp-shared;
++ 
++		opp-480000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <480000000>;
++			opp-microvolt-speed0 = <820000 820000 1100000>; 
++			opp-microvolt-speed1 = <880000 880000 1100000>;
++			opp-microvolt-speed2 = <880000 880000 1100000>;
++		};
++	
++		opp-600000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <600000000>;
++			opp-microvolt-speed0 = <820000 820000 1100000>;
++			opp-microvolt-speed1 = <880000 880000 1100000>;
++			opp-microvolt-speed2 = <880000 880000 1100000>;
++		};
++
++		opp-792000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <792000000>;
++		        opp-microvolt-speed0 = <860000 860000 1100000>;
++			opp-microvolt-speed1 = <940000 940000 1100000>;
++			opp-microvolt-speed2 = <940000 940000 1100000>;
++		};
++
++		opp-1008000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1008000000>;
++			opp-microvolt-speed0 = <900000 900000 1100000>;
++			opp-microvolt-speed1 = <1020000 1020000 1100000>;
++			opp-microvolt-speed2 = <1020000 1020000 1100000>;
++		};
++
++		opp-1200000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt-speed0 = <960000 960000 1100000>;
++			opp-microvolt-speed1 = <1100000 1100000 1100000>;
++			opp-microvolt-speed2 = <1100000 1100000 1100000>;
++		};
++
++		opp-1512000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1512000000>;
++			opp-microvolt-speed0 = <1100000 1100000 1100000>;
++			opp-microvolt-speed1 = <1100000 1100000 1100000>;
++			opp-microvolt-speed2 = <1100000 1100000 1100000>;
++		};
++	};
++};
++
++&cpu0 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu1 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu2 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu3 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index a795087c681f..54dfaf24e75d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -7,6 +7,7 @@
+  */
+ 
+ #include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+index 649274d77827..47ab2acedae6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+@@ -12,6 +12,11 @@ / {
+ 	compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+ };
+ 
++&cpu0  {
++	cpu-supply = <&reg_dcdca>;
++	status = "okay";
++};
++
+ &emac0 {
+ 	allwinner,rx-delay-ps = <3100>;
+ 	allwinner,tx-delay-ps = <700>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+new file mode 100644
+index 000000000000..0509e3fb22e2
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+@@ -0,0 +1,64 @@
++
++
++&r_i2c {
++	status = "okay";
++
++	axp313: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		interrupt-parent = <&pio>;
++		interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9 */
++
++		vin1-supply = <&reg_vcc5v>;
++		vin2-supply = <&reg_vcc5v>;
++		vin3-supply = <&reg_vcc5v>;
++
++		regulators {
++			/* Supplies VCC-PLL and DRAM */
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc1v8";
++			};
++
++			/* Supplies VCC-IO, so needs to be always on. */
++			reg_dldo1: dldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc3v3";
++			};
++
++			reg_dcdc1: dcdc1 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <990000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-name = "vdd-gpu-sys";
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-always-on;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-ramp-delay = <200>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-always-on;
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-name = "vdd-dram";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+index b3b1b8692125..eba89a87785b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+@@ -6,12 +6,18 @@
+ /dts-v1/;
+ 
+ #include "sun50i-h616-orangepi-zero.dtsi"
++#include "sun50i-h618-cpu-dvfs.dtsi"
+ 
+ / {
+ 	model = "OrangePi Zero3";
+ 	compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
+ };
+ 
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
+ &emac0 {
+ 	allwinner,tx-delay-ps = <700>;
+ 	phy-mode = "rgmii-rxid";
+@@ -31,62 +37,6 @@ &mmc0 {
+ 	vmmc-supply = <&reg_dldo1>;
+ };
+ 
+-&r_i2c {
+-	status = "okay";
+-
+-	axp313: pmic@36 {
+-		compatible = "x-powers,axp313a";
+-		reg = <0x36>;
+-		#interrupt-cells = <1>;
+-		interrupt-controller;
+-		interrupt-parent = <&pio>;
+-		interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9 */
+-
+-		vin1-supply = <&reg_vcc5v>;
+-		vin2-supply = <&reg_vcc5v>;
+-		vin3-supply = <&reg_vcc5v>;
+-
+-		regulators {
+-			/* Supplies VCC-PLL, so needs to be always on. */
+-			reg_aldo1: aldo1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-				regulator-name = "vcc1v8";
+-			};
+-
+-			/* Supplies VCC-IO, so needs to be always on. */
+-			reg_dldo1: dldo1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <3300000>;
+-				regulator-max-microvolt = <3300000>;
+-				regulator-name = "vcc3v3";
+-			};
+-
+-			reg_dcdc1: dcdc1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <990000>;
+-				regulator-name = "vdd-gpu-sys";
+-			};
+-
+-			reg_dcdc2: dcdc2 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <1100000>;
+-				regulator-name = "vdd-cpu";
+-			};
+-
+-			reg_dcdc3: dcdc3 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <1100000>;
+-				regulator-max-microvolt = <1100000>;
+-				regulator-name = "vdd-dram";
+-			};
+-		};
+-	};
+-};
+-
+ &pio {
+ 	vcc-pc-supply = <&reg_dldo1>;
+ 	vcc-pf-supply = <&reg_dldo1>;
+diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
+index fb2875ce1fdd..0b5cbe13ccb1 100644
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -104,6 +104,8 @@ static const struct of_device_id allowlist[] __initconst = {
+  */
+ static const struct of_device_id blocklist[] __initconst = {
+ 	{ .compatible = "allwinner,sun50i-h6", },
++	{ .compatible = "allwinner,sun50i-h616", },
++	{ .compatible = "allwinner,sun50i-h618", },
+ 
+ 	{ .compatible = "apple,arm-platform", },
+ 
+diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+index 6845ab5034ec..51d7010c49a7 100644
+--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+@@ -6,6 +6,9 @@
+  * provide the OPP framework with required information.
+  *
+  * Copyright (C) 2019 Yangtao Li <tiny.windzz@gmail.com>
++ *
++ * ADD efuse_xlate to extract SoC version so that h6 and h616 can coexist.
++ * Version 1 AGM1968 <AGM1968@users.noreply.github.com>
+  */
+ 
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+@@ -20,25 +23,62 @@
+ 
+ #define MAX_NAME_LEN	7
+ 
+-#define NVMEM_MASK	0x7
+-#define NVMEM_SHIFT	5
++#define SUN50I_H616_NVMEM_MASK 0x22
++#define SUN50I_H616_NVMEM_SHIFT 5
++#define SUN50I_H6_NVMEM_MASK 0x7
++#define SUN50I_H6_NVMEM_SHIFT 5
++
++struct sunxi_cpufreq_soc_data {
++	u32 (*efuse_xlate) (void *efuse);
++};
+ 
+ static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
+ 
++static u32 sun50i_h616_efuse_xlate(void *efuse)
++{
++   u32 efuse_value = (*(u32 *)efuse >> SUN50I_H616_NVMEM_SHIFT) &
++             SUN50I_H616_NVMEM_MASK;
++
++   /* Tested as V1 h616 soc. Expected efuse values are 1 - 3,
++      slowest to fastest */
++   if (efuse_value >=1 && efuse_value <= 3)
++       return efuse_value - 1;
++   else
++       return 0;
++};
++
++static u32 sun50i_h6_efuse_xlate(void *efuse)
++{
++   u32 efuse_value = (*(u32 *)efuse >> SUN50I_H6_NVMEM_SHIFT) &
++             SUN50I_H6_NVMEM_MASK;
++
++   /*
++    * We treat unexpected efuse values as if the SoC was from
++    * the slowest bin. Expected efuse values are 1 - 3, slowest
++    * to fastest.
++   */
++   if (efuse_value >= 1 && efuse_value <= 3)
++       return efuse_value - 1;
++   else
++       return 0;
++};
++
++
+ /**
+  * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
++ * @soc_data: pointer to sunxi_cpufreq_soc_data context
+  * @versions: Set to the value parsed from efuse
+  *
+  * Returns 0 if success.
+  */
+-static int sun50i_cpufreq_get_efuse(u32 *versions)
++static int sun50i_cpufreq_get_efuse(const struct sunxi_cpufreq_soc_data *soc_data,
++		u32 *versions)
+ {
+ 	struct nvmem_cell *speedbin_nvmem;
+ 	struct device_node *np;
+ 	struct device *cpu_dev;
+-	u32 *speedbin, efuse_value;
++	u32 *speedbin;
+ 	size_t len;
+-	int ret;
+ 
+ 	cpu_dev = get_cpu_device(0);
+ 	if (!cpu_dev)
+@@ -47,10 +87,9 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
+ 	np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
+ 	if (!np)
+ 		return -ENOENT;
+-
+-	ret = of_device_is_compatible(np,
+-				      "allwinner,sun50i-h6-operating-points");
+-	if (!ret) {
++	if (of_device_is_compatible(np, "allwinner,sun50i-h6-operating-points")) {}
++	else if (of_device_is_compatible(np, "allwinner,sun50i-h616-operating-points")) {}
++	else {
+ 		of_node_put(np);
+ 		return -ENOENT;
+ 	}
+@@ -66,17 +105,7 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
+ 	if (IS_ERR(speedbin))
+ 		return PTR_ERR(speedbin);
+ 
+-	efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
+-
+-	/*
+-	 * We treat unexpected efuse values as if the SoC was from
+-	 * the slowest bin. Expected efuse values are 1-3, slowest
+-	 * to fastest.
+-	 */
+-	if (efuse_value >= 1 && efuse_value <= 3)
+-		*versions = efuse_value - 1;
+-	else
+-		*versions = 0;
++	*versions = soc_data->efuse_xlate(speedbin);
+ 
+ 	kfree(speedbin);
+ 	return 0;
+@@ -84,18 +113,23 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
+ 
+ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
+ {
++	const struct of_device_id *match;
+ 	int *opp_tokens;
+ 	char name[MAX_NAME_LEN];
+ 	unsigned int cpu;
+ 	u32 speed = 0;
+ 	int ret;
+ 
++	match = dev_get_platdata(&pdev->dev);
++	if (!match)
++		return -EINVAL;
++
+ 	opp_tokens = kcalloc(num_possible_cpus(), sizeof(*opp_tokens),
+ 			     GFP_KERNEL);
+ 	if (!opp_tokens)
+ 		return -ENOMEM;
+ 
+-	ret = sun50i_cpufreq_get_efuse(&speed);
++	ret = sun50i_cpufreq_get_efuse(match-> data, &speed);
+ 	if (ret) {
+ 		kfree(opp_tokens);
+ 		return ret;
+@@ -159,8 +193,18 @@ static struct platform_driver sun50i_cpufreq_driver = {
+ 	},
+ };
+ 
++static const struct sunxi_cpufreq_soc_data sun50i_h616_data = {
++    .efuse_xlate = sun50i_h616_efuse_xlate,
++};
++
++static const struct sunxi_cpufreq_soc_data sun50i_h6_data = {
++    .efuse_xlate = sun50i_h6_efuse_xlate,
++};
++
+ static const struct of_device_id sun50i_cpufreq_match_list[] = {
+-	{ .compatible = "allwinner,sun50i-h6" },
++	{ .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data },
++        { .compatible = "allwinner,sun50i-h616", .data = &sun50i_h616_data },
++        { .compatible = "allwinner,sun50i-h618", .data = &sun50i_h616_data },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
+@@ -196,8 +240,8 @@ static int __init sun50i_cpufreq_init(void)
+ 		return ret;
+ 
+ 	sun50i_cpufreq_pdev =
+-		platform_device_register_simple("sun50i-cpufreq-nvmem",
+-						-1, NULL, 0);
++		platform_device_register_data(NULL,
++		"sun50i-cpufreq-nvmem", -1, match, sizeof(*match));
+ 	ret = PTR_ERR_OR_ZERO(sun50i_cpufreq_pdev);
+ 	if (ret == 0)
+ 		return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-Add-thermal-sensor-and-thermal-zones.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-Add-thermal-sensor-and-thermal-zones.patch
new file mode 100644
index 000000000000..99e4ef9235ac
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-Add-thermal-sensor-and-thermal-zones.patch
@@ -0,0 +1,82 @@
+From 14386e14a87e08bff223be039ac856d00009934d Mon Sep 17 00:00:00 2001
+From: Kali Prasad <kprasadvnsi@protonmail.com>
+Date: Sun, 19 Sep 2021 08:02:27 +0000
+Subject: arm64: dts: allwinner: h616: Add thermal sensor and thermal zones
+
+There are four sensors, CPU, GPU, VE, and DDR.
+
+Signed-off-by: Kali Prasad <kprasadvnsi@protonmail.com>
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 21 +++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 7ec3d5dbad35..5d459ec2f95d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -26,6 +26,8 @@ cpu0: cpu@0 {
+ 			reg = <0>;
+ 			enable-method = "psci";
+ 			clocks = <&ccu CLK_CPUX>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		cpu1: cpu@1 {
+@@ -34,6 +36,8 @@ cpu1: cpu@1 {
+ 			reg = <1>;
+ 			enable-method = "psci";
+ 			clocks = <&ccu CLK_CPUX>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		cpu2: cpu@2 {
+@@ -42,6 +46,8 @@ cpu2: cpu@2 {
+ 			reg = <2>;
+ 			enable-method = "psci";
+ 			clocks = <&ccu CLK_CPUX>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		cpu3: cpu@3 {
+@@ -50,6 +56,8 @@ cpu3: cpu@3 {
+ 			reg = <3>;
+ 			enable-method = "psci";
+ 			clocks = <&ccu CLK_CPUX>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			#cooling-cells = <2>;
+ 		};
+ 	};
+ 
+@@ -922,6 +930,9 @@ cpu-thermal {
+ 			polling-delay = <1000>;
+ 			thermal-sensors = <&ths 2>;
+ 			sustainable-power = <1000>;
++			k_po = <20>;
++			k_pu = <40>;
++			k_i = <0>;
+ 
+ 			trips {
+ 				cpu_threshold: cpu-trip-0 {
+@@ -940,6 +951,16 @@ cpu_critical: cpu-trip-2 {
+ 					hysteresis = <0>;
+ 				};
+ 			};
++
++			cooling-maps {
++				map0 {
++					trip = <&cpu_target>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
++			};
+ 		};
+ 
+ 		gpu-thermal {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch
new file mode 100644
index 000000000000..c43bdd7667ba
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch
@@ -0,0 +1,48 @@
+From 0bc7e696227939df69c5bccdb4d19693a3db43f5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Micha=C5=82=20Dzieko=C5=84ski?=
+ <michal.dziekonski+github@gmail.com>
+Date: Sun, 28 May 2023 00:26:43 +0000
+Subject: arm64: dts: allwinner: h616 orangepi zero2: Enable expansion board
+ USB ports
+
+Signed-off-by: Michal Dziekonski <michal.dziekonski+github@gmail.com>
+---
+ .../dts/allwinner/sun50i-h616-orangepi-zero.dtsi  | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 3d996494d37c..558852702e55 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -67,6 +67,13 @@ &ehci1 {
+ };
+ 
+ /* USB 2 & 3 are on headers only. */
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
+ 
+ &emac0 {
+ 	pinctrl-names = "default";
+@@ -92,6 +99,14 @@ &ohci1 {
+ 	status = "okay";
+ };
+ 
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
+ &spi0  {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch
new file mode 100644
index 000000000000..df3e141a6f59
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch
@@ -0,0 +1,26 @@
+From ad255f4402670d30adafcb0c6bfa7705025c68c3 Mon Sep 17 00:00:00 2001
+From: Ukhellfire <afaulkner420@gmail.com>
+Date: Fri, 25 Mar 2022 07:10:57 +0000
+Subject: arm64: dts/allwinner/sun50i-h6: Fix H6 emmc
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 68f2fb6be1b3..279206b364ea 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -547,8 +547,7 @@ mmc1: mmc@4021000 {
+ 		};
+ 
+ 		mmc2: mmc@4022000 {
+-			compatible = "allwinner,sun50i-h6-emmc",
+-				     "allwinner,sun50i-a64-emmc";
++			compatible = "allwinner,sun50i-h6-emmc";
+ 			reg = <0x04022000 0x1000>;
+ 			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ 			clock-names = "ahb", "mmc";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch
new file mode 100644
index 000000000000..8128ee2261d9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch
@@ -0,0 +1,38 @@
+From 2a126ac27a8de31a434072da86c6d3e3d58e141b Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:07:46 +0200
+Subject: arm64:dts: allwinner: sun50i-h616 Add GPU node
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 35c097c666c1..d40216d00449 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -109,6 +109,20 @@ soc {
+ 		#size-cells = <1>;
+ 		ranges = <0x0 0x0 0x0 0x40000000>;
+ 
++		gpu: gpu@1800000 {
++			compatible = "allwinner,sun50i-h616-mali",
++				     "arm,mali-bifrost";
++			reg = <0x1800000 0x40000>;
++			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "job", "mmu", "gpu";
++			clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>;
++			clock-names = "core", "bus";
++			resets = <&ccu RST_BUS_GPU>;
++			status = "disabled";
++		};
++
+ 		syscon: syscon@3000000 {
+ 			compatible = "allwinner,sun50i-h616-system-control";
+ 			reg = <0x03000000 0x1000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch
new file mode 100644
index 000000000000..56a6fe52766f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch
@@ -0,0 +1,55 @@
+From d7cc13b02f1b89a8a59907af61410fd37f0c578e Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:14:55 +0200
+Subject: arm64:dts:allwinner: sun50i-h616 Add VPU node
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index d40216d00449..8b1fd5ed8583 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -123,6 +123,17 @@ gpu: gpu@1800000 {
+ 			status = "disabled";
+ 		};
+ 
++		video-codec@1c0e000 {
++			compatible = "allwinner,sun50i-h616-video-engine";
++			reg = <0x01c0e000 0x2000>;
++			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
++				 <&ccu CLK_MBUS_VE>;
++			clock-names = "ahb", "mod", "ram";
++			resets = <&ccu RST_BUS_VE>;
++			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
++			allwinner,sram = <&ve_sram 1>;
++		};
++
+ 		syscon: syscon@3000000 {
+ 			compatible = "allwinner,sun50i-h616-system-control";
+ 			reg = <0x03000000 0x1000>;
+@@ -137,6 +148,19 @@ sram_c: sram@28000 {
+ 				#size-cells = <1>;
+ 				ranges = <0 0x00028000 0x30000>;
+ 			};
++
++			sram_c1: sram@1a00000 {
++				compatible = "mmio-sram";
++				reg = <0x01a00000 0x200000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x01a00000 0x200000>;
++
++				ve_sram: sram-section@0 {
++					compatible = "allwinner,sun50i-h616-sram-c1";
++					reg = <0x000000 0x200000>;
++				};
++			};
+ 		};
+ 
+ 		ccu: clock@3001000 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch
new file mode 100644
index 000000000000..6f53e028cf4a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch
@@ -0,0 +1,339 @@
+From b6a6720230348aaea07042e6689c2e8d11677a61 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Fri, 29 Dec 2023 11:18:33 +0000
+Subject: arm64: dts: h616: add hdmi support for zero2 and zero3
+
+---
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  |  25 ++
+ .../allwinner/sun50i-h616-orangepi-zero2.dts  |   4 +
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 213 ++++++++++++++++++
+ 3 files changed, 242 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 6aca609464c0..ce3dc6d9cd66 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -23,6 +23,17 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -90,6 +101,10 @@ wifi_pwrseq: wifi-pwrseq {
+ 	};
+ };
+ 
++&de {
++	status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+@@ -110,6 +125,16 @@ &emac0 {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &mdio0 {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+index 47ab2acedae6..d8a019fd4f7c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+@@ -29,6 +29,10 @@ &gpu {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	hvcc-supply = <&reg_bldo1>;
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdce>;
+ };
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 3df1c02dbcd2..f0403f3523d9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -7,8 +7,11 @@
+ #include <dt-bindings/clock/sun50i-h616-ccu.h>
+ #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+ #include <dt-bindings/clock/sun6i-rtc.h>
++#include <dt-bindings/clock/sun8i-de2.h>
++#include <dt-bindings/clock/sun8i-tcon-top.h>
+ #include <dt-bindings/reset/sun50i-h616-ccu.h>
+ #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
++#include <dt-bindings/reset/sun8i-de2.h>
+ #include <dt-bindings/thermal/thermal.h>
+ 
+ / {
+@@ -61,6 +64,12 @@ cpu3: cpu@3 {
+ 		};
+ 	};
+ 
++	de: display-engine {
++		compatible = "allwinner,sun50i-h6-display-engine";
++		allwinner,pipelines = <&mixer0>;
++		status = "disabled";
++	};
++
+ 	reserved-memory {
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+@@ -117,6 +126,50 @@ soc {
+ 		#size-cells = <1>;
+ 		ranges = <0x0 0x0 0x0 0x40000000>;
+ 
++		bus@1000000 {
++			compatible = "allwinner,sun50i-h616-de33",
++				     "allwinner,sun50i-a64-de2";
++			reg = <0x1000000 0x400000>;
++			allwinner,sram = <&de3_sram 1>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0x1000000 0x400000>;
++
++			display_clocks: clock@8000 {
++				compatible = "allwinner,sun50i-h616-de33-clk";
++				reg = <0x8000 0x100>;
++				clocks = <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
++				clock-names = "mod", "bus";
++				resets = <&ccu RST_BUS_DE>;
++				#clock-cells = <1>;
++				#reset-cells = <1>;
++			};
++
++			mixer0: mixer@100000 {
++				compatible = "allwinner,sun50i-h616-de33-mixer-0";
++				reg = <0x100000 0x100000>,
++				      <0x8100 0x40>,
++				      <0x280000 0x20000>;
++				clocks = <&display_clocks CLK_BUS_MIXER0>,
++					 <&display_clocks CLK_MIXER0>;
++				clock-names = "bus", "mod";
++				resets = <&display_clocks RST_MIXER0>;
++
++				ports {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					mixer0_out: port@1 {
++						reg = <1>;
++
++						mixer0_out_tcon_top_mixer0: endpoint {
++							remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
++						};
++					};
++				};
++			};
++		};
++
+ 		gpu: gpu@1800000 {
+ 			compatible = "allwinner,sun50i-h616-mali",
+ 				     "arm,mali-bifrost";
+@@ -149,12 +202,31 @@ syscon: syscon@3000000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@100000 {
++				compatible = "mmio-sram";
++				reg = <0x00100000 0x18000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00100000 0x18000>;
++
++				scpi_sram: scpi-sram@17c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x17c00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@28000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00028000 0x30000>;
+ 				#address-cells = <1>;
+ 				#size-cells = <1>;
+ 				ranges = <0 0x00028000 0x30000>;
++
++				de3_sram: sram-section@0 {
++					compatible = "allwinner,sun50i-h616-sram-c",
++						     "allwinner,sun50i-a64-sram-c";
++					reg = <0x0000 0x1e000>;
++				};
+ 			};
+ 
+ 			sram_c1: sram@1a00000 {
+@@ -834,6 +906,147 @@ ohci3: usb@5311400 {
+ 			status = "disabled";
+ 		};
+ 
++		hdmi: hdmi@6000000 {
++			#sound-dai-cells = <0>;
++			compatible = "allwinner,sun50i-h616-dw-hdmi",
++				     "allwinner,sun50i-h6-dw-hdmi";
++			reg = <0x06000000 0x10000>;
++			reg-io-width = <1>;
++			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
++				 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
++				 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
++			clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
++				      "hdcp-bus";
++			resets = <&ccu RST_BUS_HDMI>, <&ccu RST_BUS_HDCP>;
++			reset-names = "ctrl", "hdcp";
++			phys = <&hdmi_phy>;
++			phy-names = "phy";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				hdmi_in: port@0 {
++					reg = <0>;
++
++					hdmi_in_tcon_top: endpoint {
++						remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
++					};
++				};
++
++				hdmi_out: port@1 {
++					reg = <1>;
++				};
++			};
++		};
++
++		hdmi_phy: hdmi-phy@6010000 {
++			compatible = "allwinner,sun50i-h616-hdmi-phy";
++			reg = <0x06010000 0x10000>;
++			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_HDMI_SUB>;
++			reset-names = "phy";
++			#phy-cells = <0>;
++		};
++
++		tcon_top: tcon-top@6510000 {
++			compatible = "allwinner,sun50i-h6-tcon-top";
++			reg = <0x06510000 0x1000>;
++			clocks = <&ccu CLK_BUS_TCON_TOP>,
++				 <&ccu CLK_TCON_TV0>;
++			clock-names = "bus",
++				      "tcon-tv0";
++			clock-output-names = "tcon-top-tv0";
++			resets = <&ccu RST_BUS_TCON_TOP>;
++			#clock-cells = <1>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon_top_mixer0_in: port@0 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <0>;
++
++					tcon_top_mixer0_in_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
++					};
++				};
++
++				tcon_top_mixer0_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <1>;
++
++					tcon_top_mixer0_out_tcon_tv: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
++					};
++				};
++
++				tcon_top_hdmi_in: port@4 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <4>;
++
++					tcon_top_hdmi_in_tcon_tv: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon_tv_out_tcon_top>;
++					};
++				};
++
++				tcon_top_hdmi_out: port@5 {
++					reg = <5>;
++
++					tcon_top_hdmi_out_hdmi: endpoint {
++						remote-endpoint = <&hdmi_in_tcon_top>;
++					};
++				};
++			};
++		};
++
++		tcon_tv: lcd-controller@6515000 {
++			compatible = "allwinner,sun50i-h6-tcon-tv",
++				     "allwinner,sun8i-r40-tcon-tv";
++			reg = <0x06515000 0x1000>;
++			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_TCON_TV0>,
++				 <&tcon_top CLK_TCON_TOP_TV0>;
++			clock-names = "ahb",
++				      "tcon-ch1";
++			resets = <&ccu RST_BUS_TCON_TV0>;
++			reset-names = "lcd";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon_tv_in: port@0 {
++					reg = <0>;
++
++					tcon_tv_in_tcon_top_mixer0: endpoint {
++						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
++					};
++				};
++
++				tcon_tv_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <1>;
++
++					tcon_tv_out_tcon_top: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
++					};
++				};
++			};
++		};
++
+ 		rtc: rtc@7000000 {
+ 			compatible = "allwinner,sun50i-h616-rtc";
+ 			reg = <0x07000000 0x400>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch
new file mode 100644
index 000000000000..2b40cf4986b0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch
@@ -0,0 +1,68 @@
+From 4113bf1a9d66fe7c958bdf6ff1ad198310b3659f Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Wed, 13 Dec 2023 19:15:45 +0000
+Subject: arm64: dts: h616: add wifi support for orange pi zero 2 and zero3
+
+---
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 558852702e55..6aca609464c0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -60,6 +60,34 @@ reg_usb1_vbus: regulator-usb1-vbus {
+ 		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ 		status = "okay";
+ 	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc5v>;
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
+ };
+ 
+ &ehci1 {
+@@ -95,6 +123,16 @@ &mmc0 {
+ 	status = "okay";
+ };
+ 
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
+ &ohci1 {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch
new file mode 100644
index 000000000000..6cdffdd60c00
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: root <guido.lehwalder@gmail.com>
+Date: Tue, 26 Jan 2021 18:17:33 +0300
+Subject: arm64:dts: nanopi-a64 set right phy-mode to rgmii-id
+
+set right phy-mode for NPI A64 to rgmii-id for working
+onboard-ethernet
+
+Signed-off-by: root <guido.lehwalder@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+index 6239d2c435c8..2d65dad79e5b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+@@ -80,7 +80,7 @@ &ehci1 {
+ &emac {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&rgmii_pins>;
+-	phy-mode = "rgmii";
++	phy-mode = "rgmii-id";
+ 	phy-handle = <&ext_rgmii_phy>;
+ 	phy-supply = <&reg_dcdc1>;
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch
new file mode 100644
index 000000000000..c1bb826cbd99
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch
@@ -0,0 +1,144 @@
+From 42b62c9d7c5958bcf12363ae866bc2ca6035a187 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 20:27:02 +0300
+Subject: arm64:dts:overlay: sun50i-a64-pine64-7inch-lcd
+
+Added to orange-pi-5.9 2020-11-30
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  1 +
+ .../overlay/README.sun50i-a64-overlays        |  5 ++
+ .../overlay/sun50i-a64-pine64-7inch-lcd.dtso  | 87 +++++++++++++++++++
+ 3 files changed, 93 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index ae404a5258a9..8d5ae3e3beb8 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -2,6 +2,7 @@
+ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-a64-i2c0.dtbo \
+ 	sun50i-a64-i2c1.dtbo \
++	sun50i-a64-pine64-7inch-lcd.dtbo \
+ 	sun50i-a64-pps-gpio.dtbo \
+ 	sun50i-a64-spi-add-cs1.dtbo \
+ 	sun50i-a64-spi-jedec-nor.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
+index cd9dbc686412..b684c2e3abb1 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
+@@ -20,6 +20,7 @@ on supported boards, so this controller is not supported in provided overlays
+ 
+ - i2c0
+ - i2c1
++- pine64-7inch-lcd
+ - pps-gpio
+ - spi-add-cs1
+ - spi-jedec-nor
+@@ -44,6 +45,10 @@ Activates TWI/I2C bus 1
+ 
+ I2C1 pins (SCL, SDA): PH2, PH3
+ 
++### pine64-7inch-lcd
++
++Activates the Pine64 7" LCD on pine64/pine64so boards
++
+ ### pps-gpio
+ 
+ Activates pulse-per-second GPIO client
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dtso
+new file mode 100644
+index 000000000000..34708103fe15
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dtso
+@@ -0,0 +1,87 @@
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pwm/pwm.h>
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target = <&reg_ldo_io0>;
++
++		__overlay__ {
++			regulator-min-microvolt = <3300000>;
++			regulator-max-microvolt = <3300000>;
++			regulator-name = "vcc-ctp";
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c0>;
++
++		__overlay__ {
++			status = "okay";
++
++			gt911: touchscreen@5d {
++				compatible = "goodix,gt911";
++				reg = <0x5d>;
++		
++				interrupt-parent = <&pio>;
++				interrupts = <7 4 IRQ_TYPE_EDGE_RISING>; /* PH4 */
++				reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
++				AVDD28-supply = <&reg_ldo_io0>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&r_pwm>;
++
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@3 {
++		target-path = "/";
++
++		__overlay__ {
++			backlight: backlight {
++				compatible = "pwm-backlight";
++				pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>;
++				brightness-levels = <1 2 4 8 16 32 64 128 512>;
++				default-brightness-level = <8>;
++				enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
++			};
++		};
++	};
++
++	fragment@4 {
++		target = <&dsi>;
++
++		__overlay__ {
++			vcc-dsi-supply = <&reg_dldo1>;
++			status = "okay";
++		
++			panel@0 {
++				compatible = "feiyang,fy07024di26a30d";
++				reg = <0>;
++				avdd-supply = <&reg_dc1sw>;
++				dvdd-supply = <&reg_dldo2>;
++				reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
++				backlight = <&backlight>;
++			};
++		};
++	};
++
++	fragment@5 {
++		target = <&dphy>;
++
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch
new file mode 100644
index 000000000000..e0b90b6293bc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch
@@ -0,0 +1,220 @@
+From d2fedf157df2dcd57fa46c1c08a680e236f82dc8 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:01:10 +0300
+Subject: arm64:dts:overlay sun50i-h5 add gpio regulator overclock
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  4 ++
+ .../sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso      | 31 ++++++++++
+ .../sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso      | 31 ++++++++++
+ .../sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso      | 61 +++++++++++++++++++
+ .../sun50i-h5-gpio-regulator-1.3v.dtso        | 38 ++++++++++++
+ 5 files changed, 165 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 8d5ae3e3beb8..9e3def41669e 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -14,6 +14,10 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-a64-w1-gpio.dtbo \
+ 	sun50i-h5-analog-codec.dtbo \
+ 	sun50i-h5-cir.dtbo \
++	sun50i-h5-cpu-clock-1.0GHz-1.1v.dtbo \
++	sun50i-h5-cpu-clock-1.2GHz-1.3v.dtbo \
++	sun50i-h5-cpu-clock-1.3GHz-1.3v.dtbo \
++	sun50i-h5-gpio-regulator-1.3v.dtbo \
+ 	sun50i-h5-i2c0.dtbo \
+ 	sun50i-h5-i2c1.dtbo \
+ 	sun50i-h5-i2c2.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso
+new file mode 100644
+index 000000000000..674ec1dcbfe4
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso
+@@ -0,0 +1,31 @@
++// DT overlay for CPU frequency operating points to up to 1.0GHz at a maximum CPU voltage of 1.1v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the H5 DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-960000000 {
++				opp-hz = /bits/ 64 <960000000>;
++				opp-microvolt = <1100000 1100000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1008000000 {
++				opp-hz = /bits/ 64 <1008000000>;
++				opp-microvolt = <1100000 1100000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso
+new file mode 100644
+index 000000000000..4fb5c81d31d5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso
+@@ -0,0 +1,31 @@
++// DT overlay for CPU frequency operating points to up to 1.2GHz at a maximum CPU voltage of 1.3v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the H5 DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-1104000000 {
++				opp-hz = /bits/ 64 <1104000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1200000000 {
++				opp-hz = /bits/ 64 <1200000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso
+new file mode 100644
+index 000000000000..9c633973df8b
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso
+@@ -0,0 +1,61 @@
++// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the H5 DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-1056000000 {
++				opp-hz = /bits/ 64 <1056000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1104000000 {
++				opp-hz = /bits/ 64 <1104000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1152000000 {
++				opp-hz = /bits/ 64 <1152000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1200000000 {
++				opp-hz = /bits/ 64 <1200000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1224000000 {
++				opp-hz = /bits/ 64 <1224000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1248000000 {
++				opp-hz = /bits/ 64 <1248000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1296000000 {
++				opp-hz = /bits/ 64 <1296000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso
+new file mode 100644
+index 000000000000..8d2755c3d76f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/";
++
++		__overlay__ {
++			reg_vdd_cpux: gpio-regulator {
++				compatible = "regulator-gpio";
++				regulator-name = "vdd-cpux";
++				regulator-type = "voltage";
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1300000>;
++				regulator-ramp-delay = <50>; /* 4ms */
++
++				gpios = <&r_pio 0 6 0>; /* PL6 */
++				enable-active-high;
++				gpios-states = <0x1>;
++				states = <1100000 0x0
++					  1300000 0x1>;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&cpu0>;
++
++		__overlay__ {
++			cpu-supply = <&reg_vdd_cpux>;
++		};
++	};
++};
++
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch
new file mode 100644
index 000000000000..5a0ff798727d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:52:48 +0300
+Subject: arm64:dts: sun50i-a64 force mmc0 bus-width
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 2bf345c04514..8d724dae11a3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -569,6 +569,7 @@ mmc0: mmc@1c0f000 {
+ 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ 			max-frequency = <150000000>;
+ 			status = "disabled";
++			bus-width = <0x4>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 		};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch
new file mode 100644
index 000000000000..e1362f531059
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hehopmajieh <hehopmajieh@debian.bg>
+Date: Wed, 20 May 2020 09:25:56 +0300
+Subject: arm64:dts:sun50i-a64-olinuxino-1Ge16GW Disable clock phase and hs
+ just for test
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+index 100a7ce499a6..41c7a4ed4287 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+@@ -15,8 +15,8 @@ / {
+ 
+ &mmc2 {
+ 	vqmmc-supply = <&reg_eldo1>;
+-	mmc-hs200-1_8v;
+-	allwinner,drive-data-phase = <180>;
++/*	mmc-hs200-1_8v;
++	allwinner,drive-data-phase = <180>;*/
+ };
+ 
+ &pio {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch
new file mode 100644
index 000000000000..5e5a46567ff2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Fri, 20 Mar 2020 17:31:49 +0200
+Subject: arm64:dts: sun50i-a64-olinuxino-1Ge16GW: enable bluetooth
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts | 21 ++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+index a508d77d2c09..100a7ce499a6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+@@ -18,3 +18,24 @@ &mmc2 {
+ 	mmc-hs200-1_8v;
+ 	allwinner,drive-data-phase = <180>;
+ };
++
++&pio {
++	vcc-pc-supply = <&reg_eldo1>;
++	uart1_cts_pins: uart1_cts_pins {
++		pins = "PG8";
++		function = "uart1";
++	};
++};
++
++&uart1 {
++        pinctrl-names = "default";
++        pinctrl-0 = <&uart1_pins>, <&uart1_cts_pins>;
++        status = "okay";
++        bluetooth {
++                compatible = "realtek,rtl8723bs-bt";
++                reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++                device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++                host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++                firmware-postfix = "olinuxino";
++        };
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch
new file mode 100644
index 000000000000..c0549d8252cf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch
@@ -0,0 +1,603 @@
+From c983159a71a33f173d369fdeea0cfe08afd831d1 Mon Sep 17 00:00:00 2001
+From: Mitko Gamishev <hehopmajieh@debian.bg>
+Date: Wed, 5 Feb 2020 15:03:08 +0200
+Subject: arm64:dts:sun50i-a64-olinuxino add boards
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   5 +
+ .../dts/allwinner/sun50i-a64-olinuxino-1G.dts | 362 ++++++++++++++++++
+ .../sun50i-a64-olinuxino-1Ge16GW.dts          |  20 +
+ .../allwinner/sun50i-a64-olinuxino-1Ge4GW.dts |  97 +++++
+ .../allwinner/sun50i-a64-olinuxino-1Gs16M.dts |  31 ++
+ .../allwinner/sun50i-a64-olinuxino-2Ge8G.dts  |  25 ++
+ 6 files changed, 540 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 54424ab784a5..4d4d2e5c01f2 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -5,6 +5,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-oceanic-5205-5inmfd.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-emmc.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1G.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1Ge4GW.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1Ge16GW.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1Gs16M.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-2Ge8G.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts
+new file mode 100644
+index 000000000000..54af704d2c68
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts
+@@ -0,0 +1,362 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 OLIMEX Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "Olimex A64-Olinuxino-1G";
++	compatible = "olimex,a64-olinuxino-1g", "allwinner,sun50i-a64";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	hdmi-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "allwinner,hdmi";
++		simple-audio-card,mclk-fs = <256>;
++		status = "okay";
++
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
++	reg_vcc_sys: vcc-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-sys";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++		status = "okay";
++	};
++
++	reg_usb1_vbus: usb1-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb1-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++		enable-active-high;
++		gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */
++		status = "okay";
++	};
++};
++
++&codec {
++	status = "okay";
++};
++
++&codec_analog {
++	hpvcc-supply = <&reg_eldo1>;
++	status = "okay";
++};
++
++&dai {
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_dcdc1>;
++	allwinner,tx-delay-ps = <600>;
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_dldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++/* Exposed to UEXT connector */
++&i2c1 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c1_pins>;
++	status = "disabled";
++};
++
++&i2s2 {
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&mmc0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc0_pins>;
++	vmmc-supply = <&reg_dcdc1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
++	disable-wp;
++	bus-width = <4>;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&r_rsb {
++	status = "okay";
++
++	axp803: pmic@3a3 {
++		compatible = "x-powers,axp803";
++		reg = <0x3a3>;
++		interrupt-parent = <&r_intc>;
++		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
++		x-powers,drive-vbus-en;	/* set N_VBUSEN as output pin */
++	};
++};
++
++#include "axp803.dtsi"
++
++&ac_power_supply {
++	status = "okay";
++};
++
++&axp_led {
++	label = "axp20x:yellow:chgled";
++	status = "okay";
++	x-powers,charger-mode = <0>;
++};
++
++&battery_power_supply {
++	status = "okay";
++};
++
++&reg_aldo1 {
++	regulator-always-on;
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "vcc-pe";
++};
++
++&reg_aldo2 {
++	regulator-always-on;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-pl";
++};
++
++&reg_aldo3 {
++	regulator-always-on;
++	regulator-min-microvolt = <3000000>;
++	regulator-max-microvolt = <3000000>;
++	regulator-name = "vcc-pll-avcc";
++};
++
++&reg_dcdc1 {
++	regulator-always-on;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-3v3";
++};
++
++&reg_dcdc2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1040000>;
++	regulator-max-microvolt = <1300000>;
++	regulator-name = "vdd-cpux";
++};
++
++/* DCDC3 is polyphased with DCDC2 */
++
++/*
++ * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal
++ * 1.35V that the PMIC can drive.
++ */
++&reg_dcdc5 {
++	regulator-always-on;
++	regulator-min-microvolt = <1360000>;
++	regulator-max-microvolt = <1360000>;
++	regulator-name = "vcc-ddr3";
++};
++
++&reg_dcdc6 {
++	regulator-always-on;
++	regulator-min-microvolt = <1100000>;
++	regulator-max-microvolt = <1100000>;
++	regulator-name = "vdd-sys";
++};
++
++&reg_dldo1 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-hdmi";
++};
++
++&reg_dldo2 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-mipi";
++};
++
++&reg_dldo3 {
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "vcc-avdd-csi";
++};
++
++&reg_dldo4 {
++	regulator-always-on;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-wifi-io";
++};
++
++&reg_drivevbus {
++	regulator-name = "usb0-vbus";
++	status = "okay";
++};
++
++&reg_eldo1 {
++	regulator-always-on;
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "vcc-emmc";
++};
++
++&reg_eldo2 {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "vcc-dvdd-csi";
++};
++
++&reg_fldo1 {
++	regulator-min-microvolt = <1200000>;
++	regulator-max-microvolt = <1200000>;
++	regulator-name = "vcc-1v2-hsic";
++};
++
++/*
++ * The A64 chip cannot work without this regulator off, although
++ * it seems to be only driving the AR100 core.
++ * Maybe we don't still know well about CPUs domain.
++ */
++&reg_fldo2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1100000>;
++	regulator-max-microvolt = <1100000>;
++	regulator-name = "vdd-cpus";
++};
++
++&reg_rtc_ldo {
++	regulator-name = "vcc-rtc";
++};
++
++&simplefb_hdmi {
++	vcc-hdmi-supply = <&reg_dldo1>;
++};
++
++&sound {
++	simple-audio-card,aux-devs = <&codec_analog>;
++	simple-audio-card,widgets = "Microphone", "Microphone Jack Left",
++				    "Microphone", "Microphone Jack Right",
++				    "Headphone", "Headphone Jack";
++	simple-audio-card,routing = "Left DAC", "AIF1 Slot 0 Left",
++				    "Right DAC", "AIF1 Slot 0 Right",
++				    "Headphone Jack", "HP",
++				    "AIF1 Slot 0 Left ADC", "Left ADC",
++				    "AIF1 Slot 0 Right ADC", "Right ADC",
++				    "Microphone Jack Left", "MBIAS",
++				    "MIC1", "Microphone Jack Left",
++				    "Microphone Jack Left", "HBIAS",
++				    "MIC2", "Microphone Jack Right";
++	status = "okay";
++};
++
++&spdif {
++	status = "disabled";
++};
++
++/* Exposed on UEXT */
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins>;
++	status = "disabled";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pb_pins>;
++	status = "okay";
++};
++
++/* Exposed on UEXT */
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pins>;
++	status = "disabled";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	status = "okay";
++	usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
++	usb0_vbus_det-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
++	usb0_vbus-supply = <&reg_drivevbus>;
++	usb1_vbus-supply = <&reg_usb1_vbus>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+new file mode 100644
+index 000000000000..a508d77d2c09
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+@@ -0,0 +1,20 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 OLIMEX Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64-olinuxino-1Ge4GW.dts"
++
++/ {
++	model = "Olimex A64-Olinuxino-1Ge16GW";
++	compatible = "olimex,a64-olinuxino-1ge16gw", "allwinner,sun50i-a64";
++};
++
++&mmc2 {
++	vqmmc-supply = <&reg_eldo1>;
++	mmc-hs200-1_8v;
++	allwinner,drive-data-phase = <180>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts
+new file mode 100644
+index 000000000000..c87ecc6e1d8f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts
+@@ -0,0 +1,97 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 OLIMEX Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64-olinuxino-1G.dts"
++
++/ {
++	model = "Olimex A64-Olinuxino-1Ge4GW";
++	compatible = "olimex,a64-olinuxino-1ge4gw", "allwinner,sun50i-a64";
++
++	aliases {
++		ethernet1 = &rtl8723bs;
++		mmc1 = &mmc2;
++	};
++
++	bt-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,bitclock-inversion = <1>;
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,name = "RTL8723BS";
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&bt_sco>;
++		};
++	};
++
++	bt_sco: bt-sco {
++		compatible = "linux,bt-sco";
++		#sound-dai-cells = <0>;
++		status = "okay";
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
++	};
++};
++
++&i2s1 {
++	status = "okay";
++};
++
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vmmc-supply = <&reg_aldo2>;
++	vqmmc-supply = <&reg_dldo4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	rtl8723bs: wifi@1 {
++		reg = <1>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
++		interrupt-names = "host-wake";
++	};
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_pins>;
++	vmmc-supply = <&reg_dcdc1>;
++	vqmmc-supply = <&reg_dcdc1>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&pio {
++	uart1_cts_pins: uart1_cts_pins {
++		pins = "PG8";
++		function = "uart1";
++	};
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_cts_pins>;
++	status = "okay";
++	bluetooth {
++		compatible = "realtek,rtl8723bs-bt";
++		reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		firmware-postfix = "olinuxino";
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts
+new file mode 100644
+index 000000000000..5b85f4d2b05f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts
+@@ -0,0 +1,31 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 OLIMEX Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64-olinuxino-1G.dts"
++
++/ {
++	model = "Olimex A64-Olinuxino-1Gs16M";
++	compatible = "olimex,a64-olinuxino-1gs16m", "allwinner,sun50i-a64";
++
++	aliases {
++		spi0 = &spi0;
++	};
++};
++
++&spi0 {
++	status = "okay";
++
++	spi-nor@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "winbond,w25q128", "jedec,spi-nor", "spi-flash";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++		status = "okay";
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts
+new file mode 100644
+index 000000000000..3583c37d3930
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts
+@@ -0,0 +1,25 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 OLIMEX Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64-olinuxino-1G.dts"
++
++/ {
++	model = "Olimex A64-Olinuxino-2Ge8G-IND";
++	compatible = "olimex,a64-olinuxino-2ge8g", "allwinner,sun50i-a64";
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_pins>;
++	vmmc-supply = <&reg_dcdc1>;
++	vqmmc-supply = <&reg_dcdc1>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch
new file mode 100644
index 000000000000..3772d24368fd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch
@@ -0,0 +1,38 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Fri, 20 Mar 2020 13:53:44 +0200
+Subject: arm64:dts: sun50i-a64-olinuxino-emmc: enable bluetooth
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts | 17 ++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts
+index efb20846de49..963b8b2075e8 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts
+@@ -22,4 +22,21 @@ &mmc2 {
+ 
+ &pio {
+ 	vcc-pc-supply = <&reg_eldo1>;
++	uart1_cts_pins: uart1_cts_pins {
++		pins = "PG8";
++		function = "uart1";
++	};
++};
++
++&uart1 {
++        pinctrl-names = "default";
++        pinctrl-0 = <&uart1_pins>, <&uart1_cts_pins>;
++        status = "okay";
++        bluetooth {
++                compatible = "realtek,rtl8723bs-bt";
++                reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++                device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++                host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++                firmware-postfix = "olinuxino";
++        };
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch
new file mode 100644
index 000000000000..e1a58a9b8577
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:48:25 +0300
+Subject: arm64:dts: sun50i-a64-orangepi-win add aliase ethernet1
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+index 306ce4acf967..fff7fe6dd4ad 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+@@ -15,6 +15,7 @@ / {
+ 
+ 	aliases {
+ 		ethernet0 = &emac;
++		ethernet1 = &brcmf;
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
+ 		serial2 = &uart2;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch
new file mode 100644
index 000000000000..f10710f8794e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch
@@ -0,0 +1,49 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 19:10:06 +0300
+Subject: arm64:dts: sun50i-a64-pine64 add spi0
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 29 ++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index cba8ae87529f..fc0f7975c731 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -350,3 +350,32 @@ &usb_otg {
+ &usbphy {
+ 	status = "okay";
+ };
++
++&spi0 {
++        status = "okay";
++        spi-flash@0 {
++                #address-cells = <1>;
++                #size-cells = <0>;
++                compatible = "jedec,spi-nor";
++                reg = <0>; /* Chip select 0 */
++                spi-max-frequency = <10000000>;
++                status = "disabled";
++                partitions {
++                        compatible = "fixed-partitions";
++                        #address-cells = <1>;
++                        #size-cells = <1>;
++                        partition@0 {
++                                label = "uboot";
++                                reg = <0x0 0x100000>;
++                        };
++                        partition@100000 {
++                                label = "env";
++                                reg = <0x100000 0x100000>;
++                        };
++                        partition@200000 {
++                                label = "data";
++                                reg = <0x200000 0x200000>;
++                        };
++                };
++        };
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch
new file mode 100644
index 000000000000..12aeb8a8468c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch
@@ -0,0 +1,40 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Wed, 31 Oct 2018 20:45:16 -0700
+Subject: arm64:dts: sun50i-a64-pine64 enable Bluetooth
+
+Pine64 has optional RTL8723BS WiFi + BT module, BT is connected to UART1
+and uses PL4 as BT reset, PL5 as device wake GPIO, PL6 as host wake GPIO
+the I2C controlling signals are connected to R_I2C bus.
+
+Enable it in the device tree.
+
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index a08c97f231ac..cba8ae87529f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -310,7 +310,15 @@ &uart0 {
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+-	status = "disabled";
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723bs-bt";
++		reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		firmware-postfix = "pine64";
++	};
+ };
+ 
+ /* On Pi-2 connector */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch
new file mode 100644
index 000000000000..04b3d4e6fc57
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch
@@ -0,0 +1,52 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Thu, 9 Feb 2017 00:18:56 +0800
+Subject: arm64:dts: sun50i-a64-pine64 enable wifi mmc1
+
+The Wi-Fi modules of Pine64 is powered via DLDO4 and ELDO1 (the latter
+one provides I/O voltage).
+
+Add device node for it.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16 ++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index 17886709b6b4..a08c97f231ac 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -35,6 +35,11 @@ hdmi_con_in: endpoint {
+ 			};
+ 		};
+ 	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
++	};
+ };
+ 
+ &codec {
+@@ -128,6 +133,17 @@ &mmc0 {
+ 	status = "okay";
+ };
+ 
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vmmc-supply = <&reg_dldo4>;
++	vqmmc-supply = <&reg_eldo1>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	bus-width = <4>;
++	status = "okay";
++};
++
+ &ohci0 {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch
new file mode 100644
index 000000000000..7da5ad714e5a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch
@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Sun, 3 Dec 2017 11:43:08 -0800
+Subject: arm64:dts: sun50i-a64-sopine-baseboard Add i2s2 mmc1
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 14 ++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+index 970d528378db..ee4fd195e6a4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -100,6 +100,10 @@ &i2s2 {
+ 	status = "okay";
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -107,6 +111,16 @@ ext_rgmii_phy: ethernet-phy@1 {
+ 	};
+ };
+ 
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vmmc-supply = <&reg_dldo4>;
++	vqmmc-supply = <&reg_eldo1>;
++	non-removable;
++	bus-width = <4>;
++	status = "okay";
++};
++
+ &mmc2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&mmc2_pins>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch
new file mode 100644
index 000000000000..9bd99a710ef9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch
@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Wed, 31 Oct 2018 20:50:09 -0700
+Subject: arm64:dts: sun50i-a64-sopine-baseboard enable Bluetooth
+
+SoPine has optional RTL8723BS WiFi + BT module, BT is connected to UART1
+and uses PL4 as BT reset, PL5 as device wake GPIO, PL6 as host wake GPIO
+the I2C controlling signals are connected to R_I2C bus.
+
+Enable it in the device tree.
+
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 14 ++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+index ee4fd195e6a4..56714cc3f507 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -197,6 +197,20 @@ &uart0 {
+ 	status = "okay";
+ };
+ 
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723bs-bt";
++		reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		firmware-postfix = "pine64";
++	};
++};
++
+ /* On Pi-2 connector */
+ &uart2 {
+ 	pinctrl-names = "default";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch
new file mode 100644
index 000000000000..d415575cfb55
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch
@@ -0,0 +1,42 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Mon, 6 Apr 2020 15:26:10 +0300
+Subject: arm64:dts:sun50i-a64.dtsi adjust thermal trip points
+
+default values for alert1/crit are way too high.
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 8d724dae11a3..c566075f9b31 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -245,21 +245,21 @@ map1 {
+ 			trips {
+ 				cpu_alert0: cpu_alert0 {
+ 					/* milliCelsius */
+-					temperature = <75000>;
++					temperature = <70000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 
+ 				cpu_alert1: cpu_alert1 {
+ 					/* milliCelsius */
+-					temperature = <90000>;
++					temperature = <80000>;
+ 					hysteresis = <2000>;
+ 					type = "hot";
+ 				};
+ 
+ 				cpu_crit: cpu_crit {
+ 					/* milliCelsius */
+-					temperature = <110000>;
++					temperature = <90000>;
+ 					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch
new file mode 100644
index 000000000000..206cad8f52ec
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch
@@ -0,0 +1,122 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 20:40:02 +0300
+Subject: arm64:dts:sun50i-h5 add cpu opp refs
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts   | 3 ++-
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts  | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts      | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts   | 1 +
+ 8 files changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
+index cfb943e9ae85..a54bacaddbe0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
+@@ -3,6 +3,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ #include <arm/allwinner/sunxi-bananapi-m2-plus.dtsi>
+ 
+ / {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
+index b7045a9efab5..4980076da872 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
+@@ -42,6 +42,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+@@ -393,4 +394,4 @@ &usbphy {
+ &i2s0 {
+ 	sound-dai = <&pcm5102a>;
+ 	status = "disabled";
+-};
+\ No newline at end of file
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
+index d051382cc800..2c742e0e8af3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
+@@ -43,6 +43,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
+index 57283cc16ad9..8d1958cd5dfa 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
+@@ -43,6 +43,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
+index 4c3921ac236c..49e28ed6d2bb 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
+@@ -4,6 +4,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
+index 06ffbbd29a93..be48938ee030 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
+@@ -42,6 +42,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+index 39331229c315..ba597c9d3bef 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+@@ -3,6 +3,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index 375572d2f9b5..8b92d5e77220 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -5,6 +5,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch
new file mode 100644
index 000000000000..e62291003878
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch
@@ -0,0 +1,102 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:12:46 +0300
+Subject: arm64:dts:sun50i-h5 add termal zones
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 66 ++++++++--
+ 1 file changed, 54 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index 080c3d10fdfa..c63e0871658e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -207,31 +207,73 @@ ths: thermal-sensor@1c25000 {
+ 
+ 	thermal-zones {
+ 		cpu_thermal: cpu-thermal {
+-			polling-delay-passive = <0>;
+-			polling-delay = <0>;
++			/* milliseconds */
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
+ 			thermal-sensors = <&ths 0>;
+ 
+ 			trips {
+-				cpu_hot_trip: cpu-hot {
++				cpu_warm: cpu_warm {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_hot_pre: cpu_hot_pre {
+ 					temperature = <80000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 
+-				cpu_very_hot_trip: cpu-very-hot {
+-					temperature = <100000>;
+-					hysteresis = <0>;
++				cpu_hot: cpu_hot {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot_pre: cpu_very_hot_pre {
++					temperature = <90000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot: cpu_very_hot {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_crit: cpu_crit {
++					temperature = <105000>;
++					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
+ 
+ 			cooling-maps {
+-				cpu-hot-limit {
+-					trip = <&cpu_hot_trip>;
+-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				cpu_warm_limit_cpu {
++					trip = <&cpu_warm>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>;
++				};
++
++				cpu_hot_pre_limit_cpu {
++					trip = <&cpu_hot_pre>;
++					cooling-device = <&cpu0 2 3>;
++				};
++
++				cpu_hot_limit_cpu {
++					trip = <&cpu_hot>;
++					cooling-device = <&cpu0 3 4>;
++				};
++
++				cpu_very_hot_pre_limit_cpu {
++					trip = <&cpu_very_hot_pre>;
++					cooling-device = <&cpu0 5 6>;
++				};
++
++				cpu_very_hot_limit_cpu {
++					trip = <&cpu_very_hot>;
++					cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>;
+ 				};
+ 			};
+ 		};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch
new file mode 100644
index 000000000000..2f7b1c3d9855
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Sat, 15 Jul 2023 17:06:17 +0000
+Subject: arm64: dts: sun50i: h5: enable power button for orangepi prime
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index f430acd8558f..35e09098570f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -63,8 +63,9 @@ gpio-keys {
+ 
+ 		key-sw4 {
+ 			label = "sw4";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
++			wakeup-source;
+ 		};
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch
new file mode 100644
index 000000000000..082058be6db9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch
@@ -0,0 +1,65 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 19:24:24 +0300
+Subject: arm64:dts: sun50i-h5-nanopi-neo2 add regulator, led triger
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 23 +++++++++-
+ 1 file changed, 22 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+index 05486cccee1c..39331229c315 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+@@ -25,12 +25,13 @@ leds {
+ 		led-0 {
+ 			label = "nanopi:green:pwr";
+ 			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+-			default-state = "on";
++			linux,default-trigger = "default-on";
+ 		};
+ 
+ 		led-1 {
+ 			label = "nanopi:blue:status";
+ 			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
+ 		};
+ 	};
+ 
+@@ -51,6 +52,22 @@ reg_vcc3v3: vcc3v3 {
+ 		regulator-max-microvolt = <3300000>;
+ 	};
+ 
++	vdd_cpux: gpio-regulator {
++		compatible = "regulator-gpio";
++		pinctrl-names = "default";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1100000 0x1>;
++	};
++
+ 	reg_usb0_vbus: usb0-vbus {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "usb0-vbus";
+@@ -62,6 +79,10 @@ reg_usb0_vbus: usb0-vbus {
+ 	};
+ };
+ 
++&cpu0 {
++	cpu-supply = <&vdd_cpux>;
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch
new file mode 100644
index 000000000000..3b67bb0c2998
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch
@@ -0,0 +1,40 @@
+From 82bc11e604e91080964a0a83a2590268e6d3dae1 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 27 Sep 2022 15:28:08 +0300
+Subject: arm64: dts: sun50i-h5-nanopi-r1s-h5: add rtl8153 support
+
+---
+ .../boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts     | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+index a3e040da38a0..78c568cabcb2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+@@ -21,7 +21,8 @@ / {
+ 
+ 	aliases {
+ 		ethernet0 = &emac;
+-		ethernet1 = &rtl8189etv;
++		ethernet1 = &rtl8153;
++		ethernet2 = &rtl8189etv;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -116,6 +117,13 @@ &cpu0 {
+ 
+ &ehci1 {
+ 	status = "okay";
++
++	rtl8153: device@1 {
++		compatible = "usbbda,8153";
++		reg = <1>;
++		realtek,led-data = <0x87>;
++		local-mac-address = [00 00 00 00 00 00];
++	};
+ };
+ 
+ &ehci2 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch
new file mode 100644
index 000000000000..00a857637712
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch
@@ -0,0 +1,51 @@
+From 70183d84d9cccae5f50461ebde1a9776639319b1 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 19:27:52 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-pc2 add spi flash
+
+---
+ .../dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 25 ++++++++++++++-----
+ 1 file changed, 19 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+index 460c0e3d2f97..c756b1a58c90 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -198,15 +198,28 @@ &sound_hdmi {
+ 	status = "okay";
+ };
+ 
+-&spi0  {
++&spi0 {
+ 	status = "okay";
+-
+-	flash@0 {
++	spi-flash@0 {
+ 		#address-cells = <1>;
+-		#size-cells = <1>;
++		#size-cells = <0>;
+ 		compatible = "jedec,spi-nor";
+-		reg = <0>;
+-		spi-max-frequency = <40000000>;
++		reg = <0>; /* Chip select 0 */
++		spi-max-frequency = <10000000>;
++		status = "okay";
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			partition@0 {
++				label = "uboot";
++				reg = <0x0 0x100000>;
++			};
++			partition@100000 {
++				label = "env";
++				reg = <0x100000 0x100000>;
++			};
++		};
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch
new file mode 100644
index 000000000000..880a7912ba78
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch
@@ -0,0 +1,92 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 19:34:31 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-prime add regulator
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 43 ++++++++--
+ 1 file changed, 36 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index 6e44f86a8f63..375572d2f9b5 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -8,11 +8,19 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
+ 
+ / {
+ 	model = "Xunlong Orange Pi Prime";
+ 	compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
+ 
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
+ 	aliases {
+ 		ethernet0 = &emac;
+ 		serial0 = &uart0;
+@@ -68,13 +76,6 @@ reg_gmac_3v3: gmac-3v3 {
+ 		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ 	};
+ 
+-	reg_vcc3v3: vcc3v3 {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc3v3";
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
+-	};
+-
+ 	reg_usb0_vbus: usb0-vbus {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "usb0-vbus";
+@@ -91,6 +92,10 @@ wifi_pwrseq: wifi_pwrseq {
+ 	};
+ };
+ 
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
+ &codec {
+ 	allwinner,audio-routing =
+ 		"Line Out", "LINEOUT",
+@@ -189,6 +194,30 @@ &ohci3 {
+ &sound_hdmi {
+ 	status = "okay";
+ };
++&r_i2c {
++	status = "okay";
++
++	reg_vdd_cpux: regulator@65 {
++		compatible = "silergy,sy8106a";
++		reg = <0x65>;
++		regulator-name = "vdd-cpux";
++		silergy,fixed-microvolt = <1200000>;
++		/*
++		 * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
++		 * however both the Armbian DVFS table and the official one
++		 * have operating points with voltage under 1.1V, and both
++		 * DVFS table are known to work properly at the lowest
++		 * operating point.
++		 *
++		 * Use 1.0V as the minimum voltage instead.
++		 */
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
+ 
+ &uart0 {
+ 	pinctrl-names = "default";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch
new file mode 100644
index 000000000000..badd015a1eff
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 7 Feb 2022 19:11:07 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-prime add rtl8723cs
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index 8b92d5e77220..f430acd8558f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -25,6 +25,7 @@ reg_vcc3v3: vcc3v3 {
+ 	aliases {
+ 		ethernet0 = &emac;
+ 		serial0 = &uart0;
++		ethernet1 = &rtl8723cs;
+ 	};
+ 
+ 	chosen {
+@@ -174,6 +175,10 @@ &mmc1 {
+ 	bus-width = <4>;
+ 	non-removable;
+ 	status = "okay";
++
++	rtl8723cs: sdio_wifi@1 {
++		reg = <1>;
++	};
+ };
+ 
+ &ohci0 {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch
new file mode 100644
index 000000000000..9103c9ac0477
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch
@@ -0,0 +1,67 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 19:49:11 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-zero-plus add regulator
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 25 +++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
+index 7ec5ac850a0d..dfa5fd2a766c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
+@@ -4,6 +4,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+@@ -36,12 +37,13 @@ leds {
+ 		led-0 {
+ 			label = "orangepi:green:pwr";
+ 			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+-			default-state = "on";
++			linux,default-trigger = "default-on";
+ 		};
+ 
+ 		led-1 {
+ 			label = "orangepi:red:status";
+ 			gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
++			linux,default-trigger = "heartbeat";
+ 		};
+ 	};
+ 
+@@ -54,6 +56,27 @@ reg_gmac_3v3: gmac-3v3 {
+ 		enable-active-high;
+ 		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ 	};
++
++	reg_sy8113b: gpio-regulator {
++		compatible = "regulator-gpio";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		enable-active-high;
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_sy8113b>;
+ };
+ 
+ &ehci0 {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus2-regulator-gpio-fix.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus2-regulator-gpio-fix.patch
new file mode 100644
index 000000000000..cba9a962bd83
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus2-regulator-gpio-fix.patch
@@ -0,0 +1,106 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 19:54:04 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-zero-plus2 regulator-gpio fix
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts | 58 +++++++---
+ 1 file changed, 45 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+index 3e69ebde50d3..999fdcd96143 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+@@ -4,6 +4,7 @@
+ /dts-v1/;
+ 
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ 
+@@ -30,33 +31,55 @@ hdmi_con_in: endpoint {
+ 		};
+ 	};
+ 
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
++		post-power-on-delay-ms = <200>;
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+ 		led-0 {
+ 			label = "orangepi:green:pwr";
+-			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+-			default-state = "on";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
++			linux,default-trigger = "default-on";
+ 		};
+ 
+ 		led-1 {
+ 			label = "orangepi:red:status";
+-			gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
++			gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
++			linux,default-trigger = "heartbeat";
+ 		};
+ 	};
+ 
+-	reg_vcc3v3: vcc3v3 {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc3v3";
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
++	reg_vdd_cpux: gpio-regulator {
++		compatible = "regulator-gpio";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1108475>;
++		regulator-max-microvolt = <1307810>;
++		regulator-ramp-delay = <50>; /* 4ms */
++//		enable-gpios =  <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++		gpios = <&r_pio 0 6 0>; /* PL6 */
++		enable-active-high;
++		gpios-states = <0x1>;
++		states = <1108475 0x0
++			  1307810 0x1>;
+ 	};
++};
+ 
+-	wifi_pwrseq: wifi_pwrseq {
+-		compatible = "mmc-pwrseq-simple";
+-		reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
+-		post-power-on-delay-ms = <200>;
+-	};
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
+ };
+ 
+ &de {
+@@ -149,3 +172,12 @@ &usb_otg {
+ &usbphy {
+ 	status = "okay";
+ };
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	status = "okay";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch
new file mode 100644
index 000000000000..baa21d8486ce
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch
@@ -0,0 +1,119 @@
+From 9225fcd789138c71c754a9844e8b9c9c930076a4 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 23 Jan 2022 20:49:27 +0300
+Subject: arm64:dts: sun50i-h6 Add r_uart uart2-3 pins
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 60 ++++++++++++++++----
+ 1 file changed, 50 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index b831ff159e78..8bd7952cff13 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -309,6 +309,17 @@ msgbox: mailbox@3003000 {
+ 			#mbox-cells = <1>;
+ 		};
+ 
++		gic: interrupt-controller@3021000 {
++			compatible = "arm,gic-400";
++			reg = <0x03021000 0x1000>,
++			      <0x03022000 0x2000>,
++			      <0x03024000 0x2000>,
++			      <0x03026000 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++			interrupt-controller;
++			#interrupt-cells = <3>;
++		};
++
+ 		sid: efuse@3006000 {
+ 			compatible = "allwinner,sun50i-h6-sid";
+ 			reg = <0x03006000 0x400>;
+@@ -368,6 +379,7 @@ pio: pinctrl@300b000 {
+ 			interrupt-controller;
+ 			#interrupt-cells = <3>;
+ 
++			/omit-if-no-ref/
+ 			ext_rgmii_pins: rgmii-pins {
+ 				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ 				       "PD5", "PD7", "PD8", "PD9", "PD10",
+@@ -413,6 +425,7 @@ mmc1_pins: mmc1-pins {
+ 				bias-pull-up;
+ 			};
+ 
++			/omit-if-no-ref/
+ 			mmc2_pins: mmc2-pins {
+ 				pins = "PC1", "PC4", "PC5", "PC6",
+ 				       "PC7", "PC8", "PC9", "PC10",
+@@ -467,17 +480,26 @@ uart1_rts_cts_pins: uart1-rts-cts-pins {
+ 				pins = "PG8", "PG9";
+ 				function = "uart1";
+ 			};
+-		};
+ 
+-		gic: interrupt-controller@3021000 {
+-			compatible = "arm,gic-400";
+-			reg = <0x03021000 0x1000>,
+-			      <0x03022000 0x2000>,
+-			      <0x03024000 0x2000>,
+-			      <0x03026000 0x2000>;
+-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+-			interrupt-controller;
+-			#interrupt-cells = <3>;
++			uart2_pins: uart2-pins {
++				pins = "PD19", "PD20";
++				function = "uart2";
++			};
++
++			uart2_rts_cts_pins: uart2-rts-cts-pins {
++				pins = "PD21", "PD22";
++				function = "uart2";
++			};
++
++			uart3_pins: uart3-pins {
++				pins = "PD23", "PD24";
++				function = "uart3";
++			};
++
++			uart3_rts_cts_pins: uart3-rts-cts-pins {
++				pins = "PD25", "PD26";
++				function = "uart3";
++			};
+ 		};
+ 
+ 		iommu: iommu@30f0000 {
+@@ -962,6 +984,19 @@ tcon_tv_out_tcon_top: endpoint@1 {
+ 			};
+ 		};
+ 
++		r_uart: serial@7080000 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x07080000 0x400>;
++			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
++			reg-shift = <2>;
++			reg-io-width = <4>;
++			clocks = <&r_ccu CLK_R_APB2_UART>;
++			resets = <&r_ccu RST_R_APB2_UART>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&r_uart_pins>;
++			status = "disabled";
++		};
++
+ 		rtc: rtc@7000000 {
+ 			compatible = "allwinner,sun50i-h6-rtc";
+ 			reg = <0x07000000 0x400>;
+@@ -1027,6 +1062,11 @@ r_rsb_pins: r-rsb-pins {
+ 				pins = "PL0", "PL1";
+ 				function = "s_rsb";
+ 			};
++
++			r_uart_pins: r-uart-pins {
++				pins = "PL2", "PL3";
++				function = "s_uart";
++			};
+ 		};
+ 
+ 		r_ir: ir@7040000 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch
new file mode 100644
index 000000000000..6af2919fe3a8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 20:12:37 +0300
+Subject: arm64:dts: sun50i-h6-orangepi-3 add r_uart aliase
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index 500744cc1442..5e3405408244 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -15,6 +15,7 @@ / {
+ 	aliases {
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
++		serial9 = &r_uart;
+ 		ethernet0 = &emac;
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch
new file mode 100644
index 000000000000..b88da76d8018
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch
@@ -0,0 +1,25 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 17:06:21 +0300
+Subject: arm64:dts: sun50i-h6-orangepi-3 delete-node &spi0
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index c84c78bb9f88..500744cc1442 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -347,6 +347,8 @@ &sound_hdmi {
+ 	status = "okay";
+ };
+ 
++/delete-node/ &spi0;
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_ph_pins>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch
new file mode 100644
index 000000000000..ba8d29102bf9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:18:05 +0300
+Subject: arm64:dts: sun50i-h6-orangepi add cpu opp refs
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+index b019bbaae21d..a494b3bbf925 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+@@ -5,6 +5,7 @@
+ /dts-v1/;
+ 
+ #include "sun50i-h6.dtsi"
++#include "sun50i-h6-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ 
+@@ -64,6 +65,10 @@ reg_vcc5v: vcc5v {
+ 	};
+ };
+ 
++&cpu0 {
++        cpu-supply = <&reg_dcdca>;
++};
++
+ &de {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch
new file mode 100644
index 000000000000..1751d465f761
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:22:57 +0300
+Subject: arm64:dts: sun50i-h6-orangepi enable higher clock
+ regulator-max-microvolt
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+index a494b3bbf925..ee1919b800ce 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+@@ -217,7 +217,7 @@ reg_cldo3: cldo3 {
+ 			reg_dcdca: dcdca {
+ 				regulator-always-on;
+ 				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <1080000>;
++				regulator-max-microvolt = <1160000>;
+ 				regulator-name = "vdd-cpu";
+ 			};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch
new file mode 100644
index 000000000000..9b6efb5280db
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch
@@ -0,0 +1,60 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igor.pecovnik@gmail.com>
+Date: Thu, 22 Jul 2021 08:56:39 +0200
+Subject: arm64:dts: sun50i-h6-orangepi-lite2 spi0, usb3phy, dwc3 enable
+
+Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts | 26 ++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
+index fb31dcb1cb6d..d16ef4cc0dd1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
+@@ -1,5 +1,6 @@
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ // Copyright (C) 2018 Jagan Teki <jagan@openedev.com>
++// Copyright (C) 2021 Igor Pecovnik <igor@armbian.com>
+ 
+ #include "sun50i-h6-orangepi.dtsi"
+ 
+@@ -11,6 +12,16 @@ aliases {
+ 		serial1 = &uart1; /* BT-UART */
+ 	};
+ 
++	reg_usb_vbus: vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		startup-delay-us = <100000>;
++		gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 USB0-DRVVBUS */
++		enable-active-high;
++	};
++
+ 	wifi_pwrseq: wifi_pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		clocks = <&rtc CLK_OSC32K_FANOUT>;
+@@ -72,3 +83,18 @@ bluetooth {
+ 		max-speed = <1500000>;
+ 	};
+ };
++
++&spi0 {
++       pinctrl-names = "default";
++       pinctrl-0 = <&spi0_pins>;
++       status = "disabled";
++};
++
++&usb3phy {
++       phy-supply = <&reg_usb_vbus>;
++       status = "okay";
++};
++
++&dwc3 {
++       status = "okay";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch
new file mode 100644
index 000000000000..ead63dccc9e0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch
@@ -0,0 +1,40 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 24 Jul 2022 13:56:50 +0300
+Subject: arm64: dts: sun50i-h6-orangepi.dtsi: Rollback r_rsb to r_i2c
+
+This fix affects two boards:
+sun50i-h6-orangepi-lite2.dts
+sun50i-h6-orangepi-one-plus.dts
+
+It also depends on the revision of the board.
+If your board fails when working with this fix, just disable
+it by adding (-) minus to the first position of the line
+in which the patch is written in the series.conf file.
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+index ee1919b800ce..15f4d7de951e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+@@ -129,12 +129,12 @@ &r_pio {
+ 	vcc-pm-supply = <&reg_bldo3>;
+ };
+ 
+-&r_rsb {
++&r_i2c {
+ 	status = "okay";
+ 
+-	axp805: pmic@745 {
++	axp805: pmic@36 {
+ 		compatible = "x-powers,axp805", "x-powers,axp806";
+-		reg = <0x745>;
++		reg = <0x36>;
+ 		interrupt-parent = <&r_intc>;
+ 		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ 		interrupt-controller;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch
new file mode 100644
index 000000000000..4e8fd0fae2e0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch
@@ -0,0 +1,36 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 19:05:25 +0300
+Subject: arm64:dts: sun50i-h6-pine-h64 add dwc3 usb3phy
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+index 41d3b5d21c40..454d2a2974c9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+@@ -89,6 +89,10 @@ reg_usb_vbus: vbus {
+ 	};
+ };
+ 
++&dwc3 {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdca>;
+ };
+@@ -378,3 +382,8 @@ &usb2phy {
+ 	usb3_vbus-supply = <&reg_usb_vbus>;
+ 	status = "okay";
+ };
++
++&usb3phy {
++	phy-supply = <&reg_usb_vbus>;
++	status = "okay";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch
new file mode 100644
index 000000000000..fb3955473c90
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch
@@ -0,0 +1,81 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 18:41:47 +0300
+Subject: arm64:dts: sun50i-h6-pine-h64 add wifi rtl8723cs
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 38 ++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+index 341f42ae0f30..41d3b5d21c40 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+@@ -41,6 +41,14 @@ hdmi_con_in: endpoint {
+ 		};
+ 	};
+ 
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "ext_clock";
++		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
++		post-power-on-delay-ms = <200>;
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -141,6 +149,24 @@ &mmc0 {
+ 	status = "okay";
+ };
+ 
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vmmc-supply = <&reg_cldo2>;
++	vqmmc-supply = <&reg_bldo2>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	rtl8723cs: sdio_wifi@1 {
++		reg = <1>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
++		interrupt-names = "host-wake";
++	};
++};
++
+ &mmc2 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	vqmmc-supply = <&reg_bldo2>;
+@@ -234,12 +260,24 @@ reg_cldo1: cldo1 {
+ 			};
+ 
+ 			reg_cldo2: cldo2 {
++				/*
++				 * This regulator is connected with CLDO3.
++				 * Before the kernel can support synchronized
++				 * enable of coupled regulators, keep them
++				 * both always on as a ugly hack.
++				 */
++				regulator-always-on;
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+ 				regulator-name = "vcc-wifi-1";
+ 			};
+ 
+ 			reg_cldo3: cldo3 {
++				/*
++				 * This regulator is connected with CLDO2.
++				 * See the comments for CLDO2.
++				 */
++				regulator-always-on;
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+ 				regulator-name = "vcc-wifi-2";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch
new file mode 100644
index 000000000000..45144e143e02
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch
@@ -0,0 +1,34 @@
+From 15e2ed3401b70a75780941f51750182d709625d8 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:19:32 +0300
+Subject: arm64:dts: sun50i-h6.dtsi add pinctrl pins for spi
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index d40c031143fd..68f2fb6be1b3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -658,6 +658,8 @@ spi0: spi@5010000 {
+ 			clock-names = "ahb", "mod";
+ 			dmas = <&dma 22>, <&dma 22>;
+ 			dma-names = "rx", "tx";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>;
+ 			resets = <&ccu RST_BUS_SPI0>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+@@ -673,6 +675,8 @@ spi1: spi@5011000 {
+ 			clock-names = "ahb", "mod";
+ 			dmas = <&dma 23>, <&dma 23>;
+ 			dma-names = "rx", "tx";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins>, <&spi1_cs_pin>;
+ 			resets = <&ccu RST_BUS_SPI1>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
new file mode 100644
index 000000000000..9ffc429c346a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
@@ -0,0 +1,111 @@
+From a4edf9dd782a58eeae32df147d48774060218c84 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 17:02:30 +0300
+Subject: arm64:dts: sun50i-h6.dtsi improve thermals
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 68 ++++++++++++++++----
+ 1 file changed, 55 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 8bd7952cff13..d40c031143fd 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -1,5 +1,6 @@
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++// Copyright (C) 2020 Igor Pecovnik <igor@armbian.com>
+ 
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/sun50i-h6-ccu.h>
+@@ -1126,33 +1127,74 @@ ths: thermal-sensor@5070400 {
+ 
+ 	thermal-zones {
+ 		cpu-thermal {
+-			polling-delay-passive = <0>;
+-			polling-delay = <0>;
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
+ 			thermal-sensors = <&ths 0>;
+ 
+ 			trips {
+-				cpu_alert: cpu-alert {
++				cpu_warm: cpu_warm {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_hot_pre: cpu_hot_pre {
++					temperature = <80000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_hot: cpu_hot {
+ 					temperature = <85000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 
+-				cpu-crit {
+-					temperature = <100000>;
+-					hysteresis = <0>;
++				cpu_very_hot_pre: cpu_very_hot_pre {
++					temperature = <90000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot: cpu_very_hot {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_crit: cpu_crit {
++					temperature = <105000>;
++					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
+ 
+ 			cooling-maps {
+-				map0 {
+-					trip = <&cpu_alert>;
+-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				cpu_warm_limit_cpu {
++					trip = <&cpu_warm>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>;
+ 				};
+-			};
++
++				cpu_hot_pre_limit_cpu {
++					trip = <&cpu_hot_pre>;
++					cooling-device = <&cpu0 2 3>;
++				};
++
++				cpu_hot_limit_cpu {
++					trip = <&cpu_hot>;
++					cooling-device = <&cpu0 3 4>;
++				};
++
++				cpu_very_hot_pre_limit_cpu {
++					trip = <&cpu_very_hot_pre>;
++					cooling-device = <&cpu0 5 6>;
++				};
++
++				cpu_very_hot_limit_cpu {
++					trip = <&cpu_very_hot>;
++					cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>;
++				};
++		       };
+ 		};
+ 
+ 		gpu-thermal {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch
new file mode 100644
index 000000000000..e20f0a3c56e2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch
@@ -0,0 +1,29 @@
+From 5f4c8eb028518f90f37f13630dedac2c8d9f7b9a Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:09:42 +0200
+Subject: arm64:dts: sun50i-h616-orangepi-zero2 Enable GPU mali
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+index b5d713926a34..649274d77827 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+@@ -19,6 +19,11 @@ &emac0 {
+ 	phy-supply = <&reg_dcdce>;
+ };
+ 
++&gpu {
++	mali-supply = <&reg_dcdcc>;
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdce>;
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch
new file mode 100644
index 000000000000..8ad681408e45
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 14 Dec 2022 20:15:41 +0300
+Subject: arm64: dts: sun50i-h616-orangepi-zero2: reg_usb1_vbus status ok
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 15290e6892fc..0666d16ba7d0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -56,6 +56,7 @@ reg_usb1_vbus: regulator-usb1-vbus {
+ 		vin-supply = <&reg_vcc5v>;
+ 		enable-active-high;
+ 		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
++		status = "okay";
+ 	};
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch
new file mode 100644
index 000000000000..5e4ea7ff7dc0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch
@@ -0,0 +1,103 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Mon, 14 Jun 2021 20:48:15 +0200
+Subject: arm64:dts: sun50i-h616-x96-mate T95 eth & sd card hack
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts | 21 +++++++-
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi         | 26 ++++++++++
+ 2 files changed, 46 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+index 959b6fd18483..d1c9bd0236f4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+@@ -15,6 +15,7 @@ / {
+ 	compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
+ 
+ 	aliases {
++		ethernet0 = &emac1;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -40,13 +41,31 @@ &ehci2 {
+ 	status = "okay";
+ };
+ 
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&rmii_phy>;
++	phy-supply = <&reg_aldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
+ &ir {
+ 	status = "okay";
+ };
+ 
++&mdio1 {
++	rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdce>;
+-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
++	broken-cd;
+ 	bus-width = <4>;
+ 	status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 944ff2747d27..45359b0d317a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -272,6 +272,13 @@ mmc2_pins: mmc2-pins {
+ 				bias-pull-up;
+ 			};
+ 
++			rmii_pins: rmii-pins {
++				pins = "PA0", "PA1", "PA2", "PA3", "PA4",
++				       "PA5", "PA6", "PA7", "PA8", "PA9";
++				function = "emac1";
++				drive-strength = <40>;
++			};
++
+ 			/omit-if-no-ref/
+ 			spi0_pins: spi0-pins {
+ 				pins = "PC0", "PC2", "PC4";
+@@ -608,6 +615,25 @@ mdio0: mdio {
+ 			};
+ 		};
+ 
++		emac1: ethernet@5030000 {
++			compatible = "allwinner,sun50i-h616-emac";
++			syscon = <&syscon 1>;
++			reg = <0x05030000 0x10000>;
++			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "macirq";
++			resets = <&ccu RST_BUS_EMAC1>;
++			reset-names = "stmmaceth";
++			clocks = <&ccu CLK_BUS_EMAC1>;
++			clock-names = "stmmaceth";
++			status = "disabled";
++
++			mdio1: mdio {
++				compatible = "snps,dwmac-mdio";
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++		};
++
+ 		spdif: spdif@5093000 {
+ 			compatible = "allwinner,sun50i-h616-spdif";
+ 			reg = <0x05093000 0x400>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch
new file mode 100644
index 000000000000..3ea8692132c4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch
@@ -0,0 +1,64 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Mon, 14 Jun 2021 22:39:58 +0200
+Subject: arm64:dts: sun50i-h616-x96-mate add hdmi
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts | 26 ++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+index d1c9bd0236f4..f380d492ae67 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+@@ -23,6 +23,17 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	reg_vcc5v: vcc5v {
+ 		/* board wide 5V supply directly from the DC input */
+ 		compatible = "regulator-fixed";
+@@ -33,6 +44,10 @@ reg_vcc5v: vcc5v {
+ 	};
+ };
+ 
++&de {
++	status = "okay";
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+@@ -52,6 +67,17 @@ &emac1 {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	hvcc-supply = <&reg_bldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &ir {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch
new file mode 100644
index 000000000000..f6848d996bcd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch
@@ -0,0 +1,28 @@
+From 293226da1c08fad4617ad5292f9724cf5868b2ef Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Thu, 28 Dec 2023 15:01:03 +0000
+Subject: arm64:dts: sun50i-h618-orangepi-zero3 Enable GPU mali
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+index eba89a87785b..cb038a23fbc2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+@@ -28,6 +28,11 @@ &ext_rgmii_phy {
+ 	motorcomm,clk-out-frequency-hz = <125000000>;
+ };
+ 
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "okay";
++};
++
+ &mmc0 {
+ 	/*
+ 	 * The schematic shows the card detect pin wired up to PF6, via an
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/cb1-overlay.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/cb1-overlay.patch
new file mode 100644
index 000000000000..3b96e3b4e56f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/cb1-overlay.patch
@@ -0,0 +1,498 @@
+From 95306c476e345675aafe86ec3cd5e3344be2f344 Mon Sep 17 00:00:00 2001
+From: Your Name <you@example.com>
+Date: Tue, 30 May 2023 12:04:55 +0800
+Subject: cb1-overlay
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  15 ++-
+ .../overlay/sun50i-h616-fixup.scr-cmd         | 110 ++++++++++++++++++
+ .../dts/allwinner/overlay/sun50i-h616-ir.dtso |  13 +++
+ .../allwinner/overlay/sun50i-h616-light.dtso  |  27 +++++
+ .../overlay/sun50i-h616-mcp2515.dtso          |  18 +++
+ .../overlay/sun50i-h616-spi-spidev.dtso       |  42 +++++++
+ .../overlay/sun50i-h616-spidev0_0.dtso        |  28 +++++
+ .../overlay/sun50i-h616-spidev1_0.dtso        |  28 +++++
+ .../overlay/sun50i-h616-spidev1_1.dtso        |  28 +++++
+ .../overlay/sun50i-h616-spidev1_2.dtso        |  28 +++++
+ .../overlay/sun50i-h616-tft35_spi.dtso        |  33 ++++++
+ .../allwinner/overlay/sun50i-h616-ws2812.dtso |  13 +++
+ 12 files changed, 381 insertions(+), 2 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 40d67ebb5932..fb6b30d5753e 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -47,12 +47,23 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-uart1.dtbo \
+ 	sun50i-h6-uart2.dtbo \
+ 	sun50i-h6-uart3.dtbo \
+-	sun50i-h6-w1-gpio.dtbo
++	sun50i-h6-w1-gpio.dtbo \
++	sun50i-h616-spi-spidev.dtbo \
++	sun50i-h616-spidev0_0.dtbo \
++	sun50i-h616-spidev1_0.dtbo \
++	sun50i-h616-spidev1_1.dtbo \
++	sun50i-h616-spidev1_2.dtbo \
++	sun50i-h616-ir.dtbo \
++	sun50i-h616-tft35_spi.dtbo \
++	sun50i-h616-mcp2515.dtbo \
++	sun50i-h616-ws2812.dtbo \
++	sun50i-h616-light.dtbo
+ 
+ scr-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-a64-fixup.scr \
+ 	sun50i-h5-fixup.scr \
+-	sun50i-h6-fixup.scr
++	sun50i-h6-fixup.scr \
++	sun50i-h616-fixup.scr
+ 
+ dtbotxt-$(CONFIG_ARCH_SUNXI) += \
+ 	README.sun50i-a64-overlays \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd
+new file mode 100644
+index 000000000000..2bde77cb082d
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd
+@@ -0,0 +1,110 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(C|G|H|I)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6'
++test "${tmp_bank}" = "H" && setenv tmp_bank 7;
++test "${tmp_bank}" = "I" && setenv tmp_bank 8;
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@300b000/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@300b000 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++for f in ${overlays}; do
++	if test "${f}" = "pwm34"; then
++		setenv bootargs_new ""
++		for arg in ${bootargs}; do
++			if test "${arg}" = "console=ttyS0,115200"; then
++				echo "Warning: Disabling ttyS0 console due to enabled PWM3 and PWM4 overlay"
++			else
++				setenv bootargs_new "${bootargs_new} ${arg}"
++			fi
++		done
++		setenv bootargs "${bootargs_new}"
++	fi
++done
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@300b000/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@300b000 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@300b000/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@5000400 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@5000800 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart3-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart3-rts-cts-pins phandle
++	fdt set /soc/serial@5000c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000c00 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000c00 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso
+new file mode 100644
+index 000000000000..825433add1c3
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&ir>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso
+new file mode 100644
+index 000000000000..5010ea6a57b5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c_gpio>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@1 {
++		target = <&uart0>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++
++    fragment@2 {
++		target = <&pwm>;
++		__overlay__ {
++            status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso
+new file mode 100644
+index 000000000000..64841956e568
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso
+@@ -0,0 +1,18 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++    fragment@0 {
++		target = <&spi1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@1 {
++		target = <&can>;
++		__overlay__ {
++            status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso
+new file mode 100644
+index 000000000000..e0ceed71965f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@5010000";
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso
+new file mode 100644
+index 000000000000..a5a89707c3dd
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@5010000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev0_0: spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso
+new file mode 100644
+index 000000000000..20a0486442cc
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev1_0: spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso
+new file mode 100644
+index 000000000000..a9ae45e84063
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev1_1: spidev@1 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <1>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso
+new file mode 100644
+index 000000000000..efe5a8949b3a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev1_2: spidev@2 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <2>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso
+new file mode 100644
+index 000000000000..e96582bcbed5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso
+@@ -0,0 +1,33 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&i2c_gpio>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@1 {
++		target = <&spi1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@2 {
++		target = <&tft_35>;
++		__overlay__ {
++            status = "okay";
++            spi-max-frequency = <12500000>;
++		};
++	};
++
++    fragment@3 {
++		target = <&tft_tp>;
++		__overlay__ {
++            status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso
+new file mode 100644
+index 000000000000..4e43907cb0ce
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&ws2812>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch
new file mode 100644
index 000000000000..034b0566d117
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch
@@ -0,0 +1,251 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 10 Jun 2022 18:20:29 +0100
+Subject: clk: gate: add support for regmap based gates
+
+While we have nice wrappers for simple bit-flip MMIO based clock gates,
+a single bit to toggle in a regmap still requires to write a lot of clock
+framework boilerplate.
+
+Support generic wrappers for regmap based clock gates, by adding them to
+the existing clock-gates.c file. Since a read-modify-write operation in a
+regmap can be much more complex than a readl/writel pair, we cannot use
+the .enable/.disable ops members, but do the actual flipping already in
+.prepare/.unprepare, where we can sleep. Also we cannot provide an
+.is_enabled function, since this must not sleep as well.
+On the upside all the locking for the r/m/w operation is provided by
+regmap already, so we can skip that.
+The rest of the CCF boilerplate code can be shared.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/clk/clk-gate.c       | 60 +++++++++-
+ include/linux/clk-provider.h | 36 +++++-
+ 2 files changed, 89 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
+index 64283807600b..f83aef5e6e79 100644
+--- a/drivers/clk/clk-gate.c
++++ b/drivers/clk/clk-gate.c
+@@ -9,6 +9,7 @@
+ #include <linux/clk-provider.h>
+ #include <linux/device.h>
+ #include <linux/module.h>
++#include <linux/regmap.h>
+ #include <linux/slab.h>
+ #include <linux/io.h>
+ #include <linux/err.h>
+@@ -124,11 +125,42 @@ const struct clk_ops clk_gate_ops = {
+ };
+ EXPORT_SYMBOL_GPL(clk_gate_ops);
+ 
++static int clk_gate_regmap_setclrbit(struct clk_hw *hw, bool enable)
++{
++	struct clk_gate *gate = to_clk_gate(hw);
++	bool set = gate->flags & CLK_GATE_SET_TO_DISABLE;
++
++	set ^= enable;
++
++	if (set)
++		return regmap_set_bits(gate->regmap, gate->regmap_offs,
++				       BIT(gate->bit_idx));
++	else
++		return regmap_clear_bits(gate->regmap, gate->regmap_offs,
++					 BIT(gate->bit_idx));
++}
++
++static int clk_gate_regmap_prepare(struct clk_hw *hw)
++{
++	return clk_gate_regmap_setclrbit(hw, true);
++}
++
++static void clk_gate_regmap_unprepare(struct clk_hw *hw)
++{
++	clk_gate_regmap_setclrbit(hw, false);
++}
++
++const struct clk_ops clk_gate_regmap_ops = {
++	.prepare = clk_gate_regmap_prepare,
++	.unprepare = clk_gate_regmap_unprepare,
++};
++
+ struct clk_hw *__clk_hw_register_gate(struct device *dev,
+ 		struct device_node *np, const char *name,
+ 		const char *parent_name, const struct clk_hw *parent_hw,
+ 		const struct clk_parent_data *parent_data,
+ 		unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
+ 		void __iomem *reg, u8 bit_idx,
+ 		u8 clk_gate_flags, spinlock_t *lock)
+ {
+@@ -150,7 +182,10 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev,
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	init.name = name;
+-	init.ops = &clk_gate_ops;
++	if (regmap)
++		init.ops = &clk_gate_regmap_ops;
++	else
++		init.ops = &clk_gate_ops;
+ 	init.flags = flags;
+ 	init.parent_names = parent_name ? &parent_name : NULL;
+ 	init.parent_hws = parent_hw ? &parent_hw : NULL;
+@@ -162,6 +197,8 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev,
+ 
+ 	/* struct clk_gate assignments */
+ 	gate->reg = reg;
++	gate->regmap = regmap;
++	gate->regmap_offs = regmap_offs;
+ 	gate->bit_idx = bit_idx;
+ 	gate->flags = clk_gate_flags;
+ 	gate->lock = lock;
+@@ -197,6 +234,22 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
+ }
+ EXPORT_SYMBOL_GPL(clk_register_gate);
+ 
++struct clk *clk_register_regmap_gate(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
++		u8 bit_idx, u8 clk_gate_flags)
++{
++	struct clk_hw *hw;
++
++	hw = clk_hw_register_regmap_gate(dev, name, parent_name, flags, regmap,
++					 regmap_offs, bit_idx, clk_gate_flags);
++
++	if (IS_ERR(hw))
++		return ERR_CAST(hw);
++	return hw->clk;
++}
++EXPORT_SYMBOL_GPL(clk_register_regmap_gate);
++
+ void clk_unregister_gate(struct clk *clk)
+ {
+ 	struct clk_gate *gate;
+@@ -234,6 +287,7 @@ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
+ 		const char *parent_name, const struct clk_hw *parent_hw,
+ 		const struct clk_parent_data *parent_data,
+ 		unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
+ 		void __iomem *reg, u8 bit_idx,
+ 		u8 clk_gate_flags, spinlock_t *lock)
+ {
+@@ -244,8 +298,8 @@ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	hw = __clk_hw_register_gate(dev, np, name, parent_name, parent_hw,
+-				    parent_data, flags, reg, bit_idx,
+-				    clk_gate_flags, lock);
++				    parent_data, flags, regmap, regmap_offs,
++				    reg, bit_idx, clk_gate_flags, lock);
+ 
+ 	if (!IS_ERR(hw)) {
+ 		*ptr = hw;
+diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
+index ec32ec58c59f..790d30e57d56 100644
+--- a/include/linux/clk-provider.h
++++ b/include/linux/clk-provider.h
+@@ -8,6 +8,7 @@
+ 
+ #include <linux/of.h>
+ #include <linux/of_clk.h>
++#include <linux/regmap.h>
+ 
+ /*
+  * flags used across common struct clk.  these flags should only affect the
+@@ -512,6 +513,8 @@ void of_fixed_clk_setup(struct device_node *np);
+ struct clk_gate {
+ 	struct clk_hw hw;
+ 	void __iomem	*reg;
++	struct regmap	*regmap;
++	unsigned int	regmap_offs;
+ 	u8		bit_idx;
+ 	u8		flags;
+ 	spinlock_t	*lock;
+@@ -529,6 +532,7 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev,
+ 		const char *parent_name, const struct clk_hw *parent_hw,
+ 		const struct clk_parent_data *parent_data,
+ 		unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
+ 		void __iomem *reg, u8 bit_idx,
+ 		u8 clk_gate_flags, spinlock_t *lock);
+ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
+@@ -536,12 +540,17 @@ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
+ 		const char *parent_name, const struct clk_hw *parent_hw,
+ 		const struct clk_parent_data *parent_data,
+ 		unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
+ 		void __iomem *reg, u8 bit_idx,
+ 		u8 clk_gate_flags, spinlock_t *lock);
+ struct clk *clk_register_gate(struct device *dev, const char *name,
+ 		const char *parent_name, unsigned long flags,
+ 		void __iomem *reg, u8 bit_idx,
+ 		u8 clk_gate_flags, spinlock_t *lock);
++struct clk *clk_register_regmap_gate(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
++		u8 bit_idx, u8 clk_gate_flags);
+ /**
+  * clk_hw_register_gate - register a gate clock with the clock framework
+  * @dev: device that is registering this clock
+@@ -556,8 +565,14 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
+ #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,     \
+ 			     clk_gate_flags, lock)			      \
+ 	__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL,      \
+-			       NULL, (flags), (reg), (bit_idx),		      \
++			       NULL, (flags), NULL, 0, (reg), (bit_idx),      \
+ 			       (clk_gate_flags), (lock))
++
++#define clk_hw_register_regmap_gate(dev, name, parent_name, flags, regmap,    \
++				    regmap_offs, bit_idx, clk_gate_flags)     \
++	__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL,      \
++			       NULL, (flags), regmap, regmap_offs, NULL,      \
++			       (bit_idx), (clk_gate_flags), NULL)
+ /**
+  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
+  * framework
+@@ -573,8 +588,15 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
+ #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg,      \
+ 				       bit_idx, clk_gate_flags, lock)	      \
+ 	__clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw),        \
+-			       NULL, (flags), (reg), (bit_idx),		      \
++			       NULL, (flags), NULL, 0, (reg), (bit_idx),      \
+ 			       (clk_gate_flags), (lock))
++
++#define clk_hw_register_regmap_gate_parent_hw(dev, name, parent_hw, flags,    \
++					      regmap, regmap_offs, bit_idx,   \
++					      clk_gate_flags)		      \
++	__clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw),        \
++			       NULL, (flags), regmap, regmap_offs, NULL,      \
++			       (bit_idx), (clk_gate_flags), NULL)
+ /**
+  * clk_hw_register_gate_parent_data - register a gate clock with the clock
+  * framework
+@@ -590,7 +612,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
+ #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg,  \
+ 				       bit_idx, clk_gate_flags, lock)	      \
+ 	__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
+-			       (flags), (reg), (bit_idx),		      \
++			       (flags), NULL, 0, (reg), (bit_idx),	      \
+ 			       (clk_gate_flags), (lock))
+ /**
+  * devm_clk_hw_register_gate - register a gate clock with the clock framework
+@@ -606,8 +628,14 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
+ #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
+ 				  clk_gate_flags, lock)			      \
+ 	__devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
+-			       NULL, (flags), (reg), (bit_idx),		      \
++			       NULL, (flags), NULL, 0, (reg), (bit_idx),      \
+ 			       (clk_gate_flags), (lock))
++#define devm_clk_hw_register_regmap_gate(dev, name, parent_name, flags,	      \
++					 regmap, regmap_offs, bit_idx,	      \
++					 clk_gate_flags)		      \
++	__devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
++			       NULL, (flags), (regmap), (regmap_offs), NULL,  \
++			       (bit_idx), (clk_gate_flags), NULL)
+ /**
+  * devm_clk_hw_register_gate_parent_data - register a gate clock with the
+  * clock framework
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/driver-allwinner-h618-emac.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/driver-allwinner-h618-emac.patch
new file mode 100644
index 000000000000..fd1d74741667
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/driver-allwinner-h618-emac.patch
@@ -0,0 +1,4519 @@
+From 9f025558c506b86670bad8fc2e798fecbdd88825 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Wed, 1 May 2024 14:32:00 +0800
+Subject: driver: allwinner h618 emac
+
+commit:
+97b476246bc79756423cf6c1d4907606c9633d4b
+---
+ drivers/gpio/gpiolib-of.c                     |   29 +-
+ drivers/mfd/Kconfig                           |   10 +
+ drivers/mfd/Makefile                          |    1 +
+ drivers/mfd/sunxi-ac200.c                     |  288 +++
+ drivers/net/ethernet/allwinner/Kconfig        |    8 +
+ drivers/net/ethernet/allwinner/Makefile       |    2 +
+ drivers/net/ethernet/allwinner/sunxi-gmac.c   | 2219 +++++++++++++++++
+ drivers/net/ethernet/allwinner/sunxi-gmac.h   |  270 ++
+ .../net/ethernet/allwinner/sunxi_gmac_ops.c   |  768 ++++++
+ drivers/net/phy/Kconfig                       |    8 +
+ drivers/net/phy/Makefile                      |    1 +
+ drivers/net/phy/sunxi-ephy.c                  |  518 ++++
+ include/linux/mfd/ac200.h                     |  213 ++
+ include/linux/of_gpio.h                       |   18 +
+ 14 files changed, 4338 insertions(+), 15 deletions(-)
+ create mode 100644 drivers/mfd/sunxi-ac200.c
+ create mode 100644 drivers/net/ethernet/allwinner/sunxi-gmac.c
+ create mode 100644 drivers/net/ethernet/allwinner/sunxi-gmac.h
+ create mode 100644 drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
+ create mode 100644 drivers/net/phy/sunxi-ephy.c
+ create mode 100644 include/linux/mfd/ac200.h
+
+diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
+index 5c4442200118..af4a5ae2fd5f 100644
+--- a/drivers/gpio/gpiolib-of.c
++++ b/drivers/gpio/gpiolib-of.c
+@@ -25,21 +25,6 @@
+ #include "gpiolib.h"
+ #include "gpiolib-of.h"
+ 
+-/*
+- * This is Linux-specific flags. By default controllers' and Linux' mapping
+- * match, but GPIO controllers are free to translate their own flags to
+- * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
+- */
+-enum of_gpio_flags {
+-	OF_GPIO_ACTIVE_LOW = 0x1,
+-	OF_GPIO_SINGLE_ENDED = 0x2,
+-	OF_GPIO_OPEN_DRAIN = 0x4,
+-	OF_GPIO_TRANSITORY = 0x8,
+-	OF_GPIO_PULL_UP = 0x10,
+-	OF_GPIO_PULL_DOWN = 0x20,
+-	OF_GPIO_PULL_DISABLE = 0x40,
+-};
+-
+ /**
+  * of_gpio_named_count() - Count GPIOs for a device
+  * @np:		device node to count GPIOs for
+@@ -427,6 +412,20 @@ static struct gpio_desc *of_get_named_gpiod_flags(const struct device_node *np,
+ 	return desc;
+ }
+ 
++int of_get_named_gpio_flags(const struct device_node *np, const char *list_name,
++			    int index, enum of_gpio_flags *flags)
++{
++	struct gpio_desc *desc;
++
++	desc = of_get_named_gpiod_flags(np, list_name, index, flags);
++
++	if (IS_ERR(desc))
++		return PTR_ERR(desc);
++	else
++		return desc_to_gpio(desc);
++}
++EXPORT_SYMBOL_GPL(of_get_named_gpio_flags);
++
+ /**
+  * of_get_named_gpio() - Get a GPIO number to use with GPIO API
+  * @np:		device node to get GPIO from
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index d791ce40f63f..ded9baa9dd55 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -203,6 +203,16 @@ config MFD_AC200
+ 	  This driver include only the core APIs. You have to select individual
+ 	  components like Ethernet PHY or codec under the corresponding menus.
+ 
++config MFD_AC200_SUNXI
++	tristate "X-Powers AC200 (Sunxi)"
++	select MFD_CORE
++	depends on I2C
++	depends on PWM_SUNXI_ENHANCE
++	help
++	  If you say Y here you get support for the X-Powers AC200 IC.
++	  This driver include only the core APIs. You have to select individual
++	  components like Ethernet PHY or RTC under the corresponding menus.
++
+ config MFD_AXP20X
+ 	tristate
+ 	select MFD_CORE
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+index 0c3b4aaf4eb7..bc180cf44009 100644
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -141,6 +141,7 @@ obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
+ 
+ obj-$(CONFIG_MFD_AC100)		+= ac100.o
+ obj-$(CONFIG_MFD_AC200)		+= ac200.o
++obj-$(CONFIG_MFD_AC200_SUNXI)		+= sunxi-ac200.o
+ obj-$(CONFIG_MFD_AXP20X)	+= axp20x.o
+ obj-$(CONFIG_MFD_AXP20X_I2C)	+= axp20x-i2c.o
+ obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
+diff --git a/drivers/mfd/sunxi-ac200.c b/drivers/mfd/sunxi-ac200.c
+new file mode 100644
+index 000000000000..7c5b0e0523cf
+--- /dev/null
++++ b/drivers/mfd/sunxi-ac200.c
+@@ -0,0 +1,288 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * MFD core driver for X-Powers' AC200 IC
++ *
++ * The AC200 is a chip which is co-packaged with Allwinner H6 SoC and
++ * includes analog audio codec, analog TV encoder, ethernet PHY, eFuse
++ * and RTC.
++ *
++ * Copyright (c) 2020 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#include <linux/i2c.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/ac200.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/nvmem-consumer.h>
++
++#define SUNXI_AC300_KEY	(0x1 << 8)
++
++/* Interrupts */
++#define AC200_IRQ_RTC  0
++#define AC200_IRQ_EPHY 1
++#define AC200_IRQ_TVE  2
++
++/* IRQ enable register */
++#define AC200_SYS_IRQ_ENABLE_OUT_EN BIT(15)
++#define AC200_SYS_IRQ_ENABLE_RTC    BIT(12)
++#define AC200_SYS_IRQ_ENABLE_EPHY   BIT(8)
++#define AC200_SYS_IRQ_ENABLE_TVE    BIT(4)
++
++static const struct regmap_range_cfg ac200_range_cfg[] = {
++	{
++		.range_min = AC200_SYS_VERSION,
++		.range_max = AC200_IC_CHARA1,
++		.selector_reg = AC200_TWI_REG_ADDR_H,
++		.selector_mask = 0xff,
++		.selector_shift = 0,
++		.window_start = 0,
++		.window_len = 256,
++	}
++};
++
++static const struct regmap_config ac200_regmap_config = {
++	.name = "ac200",
++	.reg_bits	= 8,
++	.val_bits	= 16,
++	.ranges		= ac200_range_cfg,
++	.num_ranges	= ARRAY_SIZE(ac200_range_cfg),
++	.max_register	= AC200_IC_CHARA1,
++};
++
++static const struct regmap_irq ac200_regmap_irqs[] = {
++	REGMAP_IRQ_REG(AC200_IRQ_RTC,  0, AC200_SYS_IRQ_ENABLE_RTC),
++	REGMAP_IRQ_REG(AC200_IRQ_EPHY, 0, AC200_SYS_IRQ_ENABLE_EPHY),
++	REGMAP_IRQ_REG(AC200_IRQ_TVE,  0, AC200_SYS_IRQ_ENABLE_TVE),
++};
++
++static const struct regmap_irq_chip ac200_regmap_irq_chip = {
++	.name			= "ac200_irq_chip",
++	.status_base		= AC200_SYS_IRQ_STATUS,
++	.mask_base		= AC200_SYS_IRQ_ENABLE,
++	.irqs			= ac200_regmap_irqs,
++	.num_irqs		= ARRAY_SIZE(ac200_regmap_irqs),
++	.num_regs		= 1,
++};
++
++static const struct resource ephy_resource[] = {
++	DEFINE_RES_IRQ(AC200_IRQ_EPHY),
++};
++
++static const struct mfd_cell ac200_cells[] = {
++	{
++		.name		= "ac200-ephy-sunxi",
++		.num_resources	= ARRAY_SIZE(ephy_resource),
++		.resources	= ephy_resource,
++		.of_compatible	= "x-powers,ac200-ephy-sunxi",
++	},
++	{
++		.name = "acx00-codec",
++		.of_compatible	= "x-powers,ac200-codec-sunxi",
++	},
++};
++
++atomic_t ac200_en;
++
++int ac200_enable(void)
++{
++    return atomic_read(&ac200_en);
++}
++
++EXPORT_SYMBOL(ac200_enable);
++
++static uint16_t ephy_caldata = 0;
++
++static int sun50i_ephy_get_calibrate(struct device *dev)
++{
++	struct nvmem_cell *calcell;
++	uint16_t *caldata;
++	size_t callen;
++	int ret = 0;
++
++	calcell = devm_nvmem_cell_get(dev, "calibration");
++	if (IS_ERR(calcell)) {
++		dev_err_probe(dev, PTR_ERR(calcell),
++			      "Failed to get calibration nvmem cell (%pe)\n",
++			      calcell);
++
++		if (PTR_ERR(calcell) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++		goto out;
++	}
++
++	caldata = nvmem_cell_read(calcell, &callen);
++	if (IS_ERR(caldata)) {
++		ret = PTR_ERR(caldata);
++		dev_err(dev, "Failed to read calibration data (%pe)\n",
++			caldata);
++		goto out;
++	}
++
++    ephy_caldata = *caldata;
++	kfree(caldata);
++out:
++	return ret;
++}
++
++uint16_t sun50i_ephy_calibrate_value(void)
++{
++    return ephy_caldata;
++}
++
++EXPORT_SYMBOL(sun50i_ephy_calibrate_value);
++
++static int ac200_i2c_probe(struct i2c_client *i2c)
++{
++    struct device *dev = &i2c->dev;
++    struct ac200_dev *ac200;
++    uint32_t ephy_cal;
++    int ret;
++
++    // 24Mhz clock for both ac200 and ac300 devices
++    ac200 = devm_kzalloc(dev, sizeof(*ac200), GFP_KERNEL);
++    if (!ac200)
++        return -ENOMEM;
++
++    ac200->clk = devm_clk_get(dev, NULL);
++    if (IS_ERR(ac200->clk)) {
++        dev_err(dev, "Can't obtain the clock!\n");
++        return PTR_ERR(ac200->clk);
++    }
++
++    ret = clk_prepare_enable(ac200->clk);
++    if (ret) {
++        dev_err(dev, "rclk_prepare_enable failed! \n");
++        return ret;
++    }
++
++    ret = sun50i_ephy_get_calibrate(dev);
++	if (ret) {
++        dev_err(dev, "sun50i get ephy id failed\n");
++        return ret;
++    }
++    ephy_cal = sun50i_ephy_calibrate_value();
++
++    if (ephy_cal & SUNXI_AC300_KEY) {
++        pr_warn("it's ac300, skip the ac200 init!\n");
++        return -EINVAL;
++    } else {
++        pr_warn("it's ac200, ac200 init start!\n");
++    }
++
++    i2c_set_clientdata(i2c, ac200);
++
++    ac200->regmap = devm_regmap_init_i2c(i2c, &ac200_regmap_config);
++    if (IS_ERR(ac200->regmap))
++    {
++        ret = PTR_ERR(ac200->regmap);
++        dev_err(dev, "regmap init failed: %d\n", ret);
++        return ret;
++    }
++
++    /* do a reset to put chip in a known state */
++    ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++    if (ret)
++    {
++        dev_err(dev, "AC200_SYS_CONTROL 0 failed! \n");
++        return ret;
++    }
++	atomic_set(&ac200_en, 0);
++
++    ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++    if (ret)
++    {
++        dev_err(dev, "AC200_SYS_CONTROL 1 failed! \n");
++        return ret;
++    }
++	atomic_set(&ac200_en, 1);
++
++    ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ac200_cells,
++                               ARRAY_SIZE(ac200_cells), NULL, 0, NULL);
++    if (ret)
++    {
++        dev_err(dev, "failed to add MFD devices: %d\n", ret);
++        return ret;
++    }
++    else
++    {
++        dev_err(dev, "add MFD devices success! \n");
++    }
++
++    return 0;
++}
++
++static void ac200_i2c_remove(struct i2c_client *i2c)
++{
++	struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++	regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++
++	mfd_remove_devices(&i2c->dev);
++}static void ac200_i2c_shutdown(struct i2c_client *i2c)
++{
++    struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++    regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++}
++
++static int ac200_i2c_suspend(struct device *dev)
++{
++	struct ac200_dev *ac200 = dev_get_drvdata(dev);
++
++	if (!IS_ERR_OR_NULL(ac200->clk))
++		clk_disable_unprepare(ac200->clk);
++
++	atomic_set(&ac200_en, 0);
++	return 0;
++}
++
++static int ac200_i2c_resume(struct device *dev)
++{
++	struct ac200_dev *ac200 = dev_get_drvdata(dev);
++
++	if (!IS_ERR_OR_NULL(ac200->clk))
++		clk_prepare_enable(ac200->clk);
++
++	atomic_set(&ac200_en, 0);
++	msleep(40);
++    regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++	atomic_set(&ac200_en, 1);
++	return 0;
++}
++
++static const struct dev_pm_ops ac200_core_pm_ops = {
++	.suspend_late = ac200_i2c_suspend,
++	.resume_early = ac200_i2c_resume,
++};
++
++static const struct i2c_device_id ac200_ids[] = {
++	{ "ac200", },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(i2c, ac200_ids);
++
++static const struct of_device_id ac200_of_match[] = {
++	{ .compatible = "x-powers,ac200-sunxi" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_of_match);
++
++static struct i2c_driver ac200_i2c_driver = {
++	.driver = {
++		.name	= "ac200-sunxi",
++		.of_match_table	= of_match_ptr(ac200_of_match),
++        .pm = &ac200_core_pm_ops,
++	},
++	.probe	= ac200_i2c_probe,
++	.remove = ac200_i2c_remove,
++    .shutdown = ac200_i2c_shutdown,
++	.id_table = ac200_ids,
++};
++module_i2c_driver(ac200_i2c_driver);
++
++MODULE_DESCRIPTION("MFD core driver for AC200");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/net/ethernet/allwinner/Kconfig b/drivers/net/ethernet/allwinner/Kconfig
+index 3e81059f8693..36d808810ca4 100644
+--- a/drivers/net/ethernet/allwinner/Kconfig
++++ b/drivers/net/ethernet/allwinner/Kconfig
+@@ -34,4 +34,12 @@ config SUN4I_EMAC
+ 	  To compile this driver as a module, choose M here.  The module
+ 	  will be called sun4i-emac.
+ 
++config SUNXI_GMAC
++    tristate "Allwinner GMAC support"
++	depends on ARCH_SUNXI
++	depends on OF
++	depends on AC200_PHY_SUNXI
++	select CRC32
++	select MII
++
+ endif # NET_VENDOR_ALLWINNER
+diff --git a/drivers/net/ethernet/allwinner/Makefile b/drivers/net/ethernet/allwinner/Makefile
+index ddd5a5079e8a..56b9c434a5b8 100644
+--- a/drivers/net/ethernet/allwinner/Makefile
++++ b/drivers/net/ethernet/allwinner/Makefile
+@@ -4,3 +4,5 @@
+ #
+ 
+ obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o
++sunxi_gmac-objs := sunxi_gmac_ops.o sunxi-gmac.o
++obj-$(CONFIG_SUNXI_GMAC) += sunxi_gmac.o
+diff --git a/drivers/net/ethernet/allwinner/sunxi-gmac.c b/drivers/net/ethernet/allwinner/sunxi-gmac.c
+new file mode 100644
+index 000000000000..d31b86fc1e8c
+--- /dev/null
++++ b/drivers/net/ethernet/allwinner/sunxi-gmac.c
+@@ -0,0 +1,2219 @@
++/*
++ * linux/drivers/net/ethernet/allwinner/sunxi_gmac.c
++ *
++ * Copyright © 2016-2018, fuzhaoke
++ *		Author: fuzhaoke <fuzhaoke@allwinnertech.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ */
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/mii.h>
++#include <linux/gpio.h>
++#include <linux/crc32.h>
++#include <linux/skbuff.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/crypto.h>
++#include <crypto/algapi.h>
++#include <crypto/hash.h>
++#include <linux/err.h>
++#include <linux/scatterlist.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of_net.h>
++#include <linux/of_gpio.h>
++#include <linux/io.h>
++#include "sunxi-gmac.h"
++#include <linux/timer.h>
++#include <linux/phylink.h>
++#include <linux/reset.h>
++
++
++int sunxi_get_soc_chipid(unsigned char *chipid);
++
++#define DMA_DESC_RX 256
++#define DMA_DESC_TX 256
++#define BUDGET      (dma_desc_rx / 4)
++#define TX_THRESH   (dma_desc_tx / 4)
++
++#define HASH_TABLE_SIZE 64
++#define MAX_BUF_SZ      (SZ_2K - 1)
++
++#define POWER_CHAN_NUM  3
++
++#undef PKT_DEBUG
++#undef DESC_PRINT
++
++#define circ_cnt(head, tail, size) (((head) > (tail)) ? ((head) - (tail)) : ((head) - (tail)) & ((size) - 1))
++
++#define circ_space(head, tail, size) circ_cnt((tail), ((head) + 1), (size))
++
++#define circ_inc(n, s) (((n) + 1) % (s))
++
++#define GETH_MAC_ADDRESS "01:02:03:04:05:06"
++static char *mac_str = GETH_MAC_ADDRESS;
++module_param(mac_str, charp, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(mac_str, "MAC Address String.(xx:xx:xx:xx:xx:xx)");
++
++static int rxmode = 1;
++module_param(rxmode, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(rxmode, "DMA threshold control value");
++
++static int txmode = 1;
++module_param(txmode, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(txmode, "DMA threshold control value");
++
++static int pause = 0x400;
++module_param(pause, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(pause, "Flow Control Pause Time");
++
++#define TX_TIMEO 5000
++static int watchdog = TX_TIMEO;
++module_param(watchdog, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
++
++static int dma_desc_rx = DMA_DESC_RX;
++module_param(dma_desc_rx, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(watchdog, "The number of receive's descriptors");
++
++static int dma_desc_tx = DMA_DESC_TX;
++module_param(dma_desc_tx, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(watchdog, "The number of transmit's descriptors");
++
++/* - 0: Flow Off
++ * - 1: Rx Flow
++ * - 2: Tx Flow
++ * - 3: Rx & Tx Flow
++ */
++static int flow_ctrl;
++module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(flow_ctrl, "Flow control [0: off, 1: rx, 2: tx, 3: both]");
++
++static unsigned long tx_delay;
++module_param(tx_delay, ulong, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(tx_delay, "Adjust transmit clock delay, value: 0~7");
++
++static unsigned long rx_delay;
++module_param(rx_delay, ulong, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(rx_delay, "Adjust receive clock delay, value: 0~31");
++
++/* whether using ephy_clk */
++static int g_use_ephy_clk;
++static int g_phy_addr;
++
++struct geth_priv {
++    struct dma_desc *dma_tx;
++    struct sk_buff **tx_sk;
++    unsigned int tx_clean;
++    unsigned int tx_dirty;
++    dma_addr_t dma_tx_phy;
++
++    struct reset_control *ephy_rst;
++
++    unsigned long buf_sz;
++
++    struct dma_desc *dma_rx;
++    struct sk_buff **rx_sk;
++    unsigned int rx_clean;
++    unsigned int rx_dirty;
++    dma_addr_t dma_rx_phy;
++
++    struct net_device *ndev;
++    struct device *dev;
++    struct napi_struct napi;
++
++    struct geth_extra_stats xstats;
++
++    struct mii_bus *mii;
++    int link;
++    int speed;
++    int duplex;
++#define INT_PHY 0
++#define EXT_PHY 1
++    int phy_ext;
++    int phy_interface;
++
++    void __iomem *base;
++    void __iomem *base_phy;
++    struct clk *geth_clk;
++    struct clk *ephy_clk;
++    struct pinctrl *pinctrl;
++
++    struct regulator *gmac_power[POWER_CHAN_NUM];
++    bool is_suspend;
++    int phyrst;
++    u8 rst_active_low;
++    /* definition spinlock */
++    spinlock_t lock;
++    spinlock_t tx_lock;
++
++    /* resume work */
++    struct work_struct eth_work;
++};
++
++static u64 geth_dma_mask = DMA_BIT_MASK(32);
++
++void sunxi_udelay(int n)
++{
++    udelay(n);
++}
++
++static int geth_stop(struct net_device *ndev);
++static int geth_open(struct net_device *ndev);
++static void geth_tx_complete(struct geth_priv *priv);
++static void geth_rx_refill(struct net_device *ndev);
++
++#ifdef CONFIG_GETH_ATTRS
++static ssize_t adjust_bgs_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int value = 0;
++    u32 efuse_value;
++    struct net_device *ndev = to_net_dev(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    if (priv->phy_ext == INT_PHY) {
++        value = readl(priv->base_phy) >> 28;
++        if (sunxi_efuse_read(EFUSE_OEM_NAME, &efuse_value) != 0)
++            pr_err("get PHY efuse fail!\n");
++        else
++#if defined(CONFIG_ARCH_SUN50IW2)
++            value = value - ((efuse_value >> 24) & 0x0F);
++#else
++            pr_warn("miss config come from efuse!\n");
++#endif
++    }
++
++    return sprintf(buf, "bgs: %d\n", value);
++}
++
++static ssize_t adjust_bgs_write(struct device *dev, struct device_attribute *attr,
++                                const char *buf, size_t count)
++{
++    unsigned int out = 0;
++    struct net_device *ndev = to_net_dev(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    u32 clk_value = readl(priv->base_phy);
++    u32 efuse_value;
++
++    out = simple_strtoul(buf, NULL, 10);
++
++    if (priv->phy_ext == INT_PHY) {
++        clk_value &= ~(0xF << 28);
++        if (sunxi_efuse_read(EFUSE_OEM_NAME, &efuse_value) != 0)
++            pr_err("get PHY efuse fail!\n");
++        else
++#if defined(CONFIG_ARCH_SUN50IW2)
++            clk_value |= (((efuse_value >> 24) & 0x0F) + out) << 28;
++#else
++            pr_warn("miss config come from efuse!\n");
++#endif
++    }
++
++    writel(clk_value, priv->base_phy);
++
++    return count;
++}
++
++static struct device_attribute adjust_reg[] = {
++    __ATTR(adjust_bgs, 0664, adjust_bgs_show, adjust_bgs_write),
++};
++
++static int geth_create_attrs(struct net_device *ndev)
++{
++    int j, ret;
++
++    for (j = 0; j < ARRAY_SIZE(adjust_reg); j++) {
++        ret = device_create_file(&ndev->dev, &adjust_reg[j]);
++        if (ret)
++            goto sysfs_failed;
++    }
++    goto succeed;
++
++sysfs_failed:
++    while (j--)
++        device_remove_file(&ndev->dev, &adjust_reg[j]);
++succeed:
++    return ret;
++}
++#endif
++
++#ifdef DEBUG
++static void desc_print(struct dma_desc *desc, int size)
++{
++#ifdef DESC_PRINT
++    int i;
++
++    for (i = 0; i < size; i++) {
++        u32 *x = (u32 *)(desc + i);
++
++        pr_info("\t%d [0x%08lx]: %08x %08x %08x %08x\n",
++                i, (unsigned long)(&desc[i]),
++                x[0], x[1], x[2], x[3]);
++    }
++    pr_info("\n");
++#endif
++}
++#endif
++
++static ssize_t gphy_test_show(struct device *dev,
++                              struct device_attribute *attr, char *buf)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return 0;
++    }
++
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return 0;
++    }
++
++    return sprintf(buf, "Usage:\necho [0/1/2/3/4] > gphy_test\n"
++                        "0 - Normal Mode\n"
++                        "1 - Transmit Jitter Test\n"
++                        "2 - Transmit Jitter Test(MASTER mode)\n"
++                        "3 - Transmit Jitter Test(SLAVE mode)\n"
++                        "4 - Transmit Distortion Test\n\n");
++}
++
++static ssize_t gphy_test_store(struct device *dev,
++                               struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    u16 value = 0;
++    int ret = 0;
++    u16 data = 0;
++
++    if (!dev) {
++        pr_err("Argument is invalid\n");
++        return count;
++    }
++
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return count;
++    }
++
++    data = sunxi_mdio_read(priv->base, g_phy_addr, MII_CTRL1000);
++
++    ret = kstrtou16(buf, 0, &value);
++    if (ret)
++        return ret;
++
++    if (value >= 0 && value <= 4) {
++        data &= ~(0x7 << 13);
++        data |= value << 13;
++        sunxi_mdio_write(priv->base, g_phy_addr, MII_CTRL1000, data);
++        pr_info("Set MII_CTRL1000(0x09) Reg: 0x%x\n", data);
++    } else {
++        pr_info("unknown value (%d)\n", value);
++    }
++
++    return count;
++}
++
++static DEVICE_ATTR(gphy_test, 0664, gphy_test_show, gphy_test_store);
++
++static struct mii_reg_dump mii_reg;
++
++static ssize_t mii_read_show(struct device *dev,
++                             struct device_attribute *attr, char *buf)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return 0;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return 0;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return 0;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return 0;
++    }
++
++    mii_reg.value = sunxi_mdio_read(priv->base, mii_reg.addr, mii_reg.reg);
++    return sprintf(buf, "ADDR[0x%02x]:REG[0x%02x] = 0x%04x\n",
++               mii_reg.addr, mii_reg.reg, mii_reg.value);
++}
++
++static ssize_t mii_read_store(struct device *dev,
++                              struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++    int ret = 0;
++    u16 reg, addr;
++    char *ptr;
++
++    ptr = (char *)buf;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return count;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return count;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return count;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return count;
++    }
++
++    ret = sunxi_parse_read_str(ptr, &addr, &reg);
++    if (ret)
++        return ret;
++
++    mii_reg.addr = addr;
++    mii_reg.reg = reg;
++
++    return count;
++}
++
++static DEVICE_ATTR(mii_read, 0664, mii_read_show, mii_read_store);
++
++static ssize_t mii_write_show(struct device *dev,
++                              struct device_attribute *attr, char *buf)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++    u16 bef_val, aft_val;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return 0;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return 0;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return 0;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return 0;
++    }
++
++    bef_val = sunxi_mdio_read(priv->base, mii_reg.addr, mii_reg.reg);
++    sunxi_mdio_write(priv->base, mii_reg.addr, mii_reg.reg, mii_reg.value);
++    aft_val = sunxi_mdio_read(priv->base, mii_reg.addr, mii_reg.reg);
++    return sprintf(buf, "before ADDR[0x%02x]:REG[0x%02x] = 0x%04x\n"
++                "after  ADDR[0x%02x]:REG[0x%02x] = 0x%04x\n",
++                mii_reg.addr, mii_reg.reg, bef_val,
++                mii_reg.addr, mii_reg.reg, aft_val);
++}
++
++static ssize_t mii_write_store(struct device *dev,
++                               struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++    int ret = 0;
++    u16 reg, addr, val;
++    char *ptr;
++
++    ptr = (char *)buf;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return count;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return count;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return count;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return count;
++    }
++
++    ret = sunxi_parse_write_str(ptr, &addr, &reg, &val);
++    if (ret)
++        return ret;
++
++    mii_reg.reg = reg;
++    mii_reg.addr = addr;
++    mii_reg.value = val;
++
++    return count;
++}
++
++static DEVICE_ATTR(mii_write, 0664, mii_write_show, mii_write_store);
++
++static int geth_power_on(struct geth_priv *priv)
++{
++    int value;
++    int i;
++
++    value = readl(priv->base_phy);
++    if (priv->phy_ext == INT_PHY) {
++        value |= (1 << 15);
++        value &= ~(1 << 16);
++        value |= (3 << 17);
++    } else {
++        value &= ~(1 << 15);
++
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            if (regulator_enable(priv->gmac_power[i]) != 0) {
++                pr_err("gmac-power%d enable error\n", i);
++                return -EINVAL;
++            }
++        }
++    }
++
++    writel(value, priv->base_phy);
++
++    return 0;
++}
++
++static void geth_power_off(struct geth_priv *priv)
++{
++    int value;
++    int i;
++
++    if (priv->phy_ext == INT_PHY) {
++        value = readl(priv->base_phy);
++        value |= (1 << 16);
++        writel(value, priv->base_phy);
++    } else {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            regulator_disable(priv->gmac_power[i]);
++        }
++    }
++}
++
++/* PHY interface operations */
++static int geth_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
++{
++    struct net_device *ndev = bus->priv;
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    return (int)sunxi_mdio_read(priv->base, phyaddr, phyreg);
++}
++
++static int geth_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, u16 data)
++{
++    struct net_device *ndev = bus->priv;
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    sunxi_mdio_write(priv->base, phyaddr, phyreg, data);
++
++    return 0;
++}
++
++static int geth_mdio_reset(struct mii_bus *bus)
++{
++    struct net_device *ndev = bus->priv;
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    return sunxi_mdio_reset(priv->base);
++}
++
++static void geth_adjust_link(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phydev = ndev->phydev;
++    unsigned long flags;
++    int new_state = 0;
++
++    if (!phydev)
++        return;
++
++    spin_lock_irqsave(&priv->lock, flags);
++    if (phydev->link) {
++        /* Now we make sure that we can be in full duplex mode.
++         * If not, we operate in half-duplex mode.
++         */
++        if (phydev->duplex != priv->duplex) {
++            new_state = 1;
++            priv->duplex = phydev->duplex;
++        }
++        /* Flow Control operation */
++        if (phydev->pause)
++            sunxi_flow_ctrl(priv->base, phydev->duplex, flow_ctrl, pause);
++
++        if (phydev->speed != priv->speed) {
++            new_state = 1;
++            priv->speed = phydev->speed;
++        }
++
++        if (priv->link == 0) {
++            new_state = 1;
++            priv->link = phydev->link;
++        }
++
++        if (new_state)
++            sunxi_set_link_mode(priv->base, priv->duplex, priv->speed);
++
++#ifdef LOOPBACK_DEBUG
++        phydev->state = PHY_FORCING;
++#endif
++
++    } else if (priv->link != phydev->link) {
++        new_state = 1;
++        priv->link = 0;
++        priv->speed = 0;
++        priv->duplex = -1;
++    }
++
++    if (new_state)
++        phy_print_status(phydev);
++
++    spin_unlock_irqrestore(&priv->lock, flags);
++}
++
++static int geth_phy_init(struct net_device *ndev)
++{
++    int value;
++    struct mii_bus *new_bus;
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phydev = ndev->phydev;
++    u32 supported = 0, advertising = 0;
++
++    /* Fixup the phy interface type */
++    if (priv->phy_ext == INT_PHY) {
++        priv->phy_interface = PHY_INTERFACE_MODE_MII;
++    } else {
++        /* If config gpio to reset the phy device, we should reset it */
++        if (gpio_is_valid(priv->phyrst)) {
++            gpio_direction_output(priv->phyrst, priv->rst_active_low);
++            msleep(50);
++            gpio_direction_output(priv->phyrst, !priv->rst_active_low);
++            msleep(50);
++        }
++    }
++
++    new_bus = mdiobus_alloc();
++    if (!new_bus) {
++        netdev_err(ndev, "Failed to alloc new mdio bus\n");
++        return -ENOMEM;
++    }
++
++    new_bus->name = dev_name(priv->dev);
++    new_bus->read = &geth_mdio_read;
++    new_bus->write = &geth_mdio_write;
++    new_bus->reset = &geth_mdio_reset;
++    snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x", new_bus->name, 0);
++
++    new_bus->parent = priv->dev;
++    new_bus->priv = ndev;
++
++    if (mdiobus_register(new_bus)) {
++        pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
++        goto reg_fail;
++    }
++
++    priv->mii = new_bus;
++
++    {
++        int addr;
++        for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
++            struct phy_device *phydev_tmp = mdiobus_get_phy(new_bus, addr);
++
++            if (IS_ERR_OR_NULL(phydev_tmp) || phydev_tmp->phy_id == 0xffff) {
++                if (!IS_ERR_OR_NULL(phydev_tmp))
++                    phy_device_remove(phydev_tmp);
++                phydev_tmp = mdiobus_scan_c22(new_bus, addr);
++            }
++
++            if (IS_ERR_OR_NULL(phydev_tmp) || phydev_tmp->phy_id == 0xffff ||
++                phydev_tmp->phy_id == 0x00 || phydev_tmp->phy_id == AC300_ID)
++                continue;
++
++            if (phydev_tmp->phy_id == EPHY_ID || phydev_tmp->phy_id == IP101G_ID) {
++                phydev = phydev_tmp;
++                g_phy_addr = addr;
++                break;
++            }
++        }
++    }
++
++    if (!phydev) {
++        netdev_err(ndev, "No PHY found!\n");
++        goto err;
++    }
++
++    phy_write(phydev, MII_BMCR, BMCR_RESET);
++    while (BMCR_RESET & phy_read(phydev, MII_BMCR))
++        msleep(30);
++
++    value = phy_read(phydev, MII_BMCR);
++    phy_write(phydev, MII_BMCR, (value & ~BMCR_PDOWN));
++
++    phydev->irq = PHY_POLL;
++
++    value = phy_connect_direct(ndev, phydev, &geth_adjust_link, priv->phy_interface);
++    if (value) {
++        netdev_err(ndev, "Could not attach to PHY\n");
++        goto err;
++    } else {
++        netdev_info(ndev, "%s: Type(%d) PHY ID %08x at %d IRQ %s (%s)\n",
++                ndev->name, phydev->interface, phydev->phy_id,
++                phydev->mdio.addr, "poll", dev_name(&phydev->mdio.dev));
++    }
++
++#if 0
++    phydev->supported &= PHY_GBIT_FEATURES; //kandy 000002cf
++    phydev->advertising = phydev->supported;
++#else
++
++    ethtool_convert_link_mode_to_legacy_u32(&supported, phydev->supported);
++
++    advertising = supported &= *PHY_BASIC_FEATURES; // kandy 000002cf
++
++    ethtool_convert_legacy_u32_to_link_mode(phydev->supported, supported);
++    ethtool_convert_legacy_u32_to_link_mode(phydev->advertising, advertising);
++#endif
++
++    if (priv->phy_ext == INT_PHY) {
++        /* EPHY Initial */
++        phy_write(phydev, 0x1f, 0x0100); /* switch to page 1 */
++        phy_write(phydev, 0x12, 0x4824); /* Disable APS */
++        phy_write(phydev, 0x1f, 0x0200); /* switchto page 2 */
++        phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */
++        phy_write(phydev, 0x1f, 0x0600); /* switchto page 6 */
++        phy_write(phydev, 0x14, 0x708F); /* PHYAFE TX optimization */
++        phy_write(phydev, 0x19, 0x0000);
++        phy_write(phydev, 0x13, 0xf000); /* PHYAFE RX optimization */
++        phy_write(phydev, 0x15, 0x1530);
++        phy_write(phydev, 0x1f, 0x0800); /* switch to page 8 */
++        phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */
++        phy_write(phydev, 0x1f, 0x0100); /* switchto page 1 */
++        /* reg 0x17 bit3,set 0 to disable iEEE */
++        phy_write(phydev, 0x17, phy_read(phydev, 0x17) & (~(1<<3)));
++        phy_write(phydev, 0x1f, 0x0000); /* switch to page 0 */
++    }
++
++    return 0;
++
++err:
++    mdiobus_unregister(new_bus);
++reg_fail:
++    mdiobus_free(new_bus);
++
++    return -EINVAL;
++}
++
++static int geth_phy_release(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phydev = ndev->phydev;
++    int value = 0;
++
++    /* Stop and disconnect the PHY */
++    if (phydev)
++        phy_stop(phydev);
++
++    priv->link = PHY_DOWN;
++    priv->speed = 0;
++    priv->duplex = -1;
++
++    if (phydev) {
++        value = phy_read(phydev, MII_BMCR);
++        phy_write(phydev, MII_BMCR, (value | BMCR_PDOWN));
++        phy_disconnect(phydev);
++        ndev->phydev = NULL;
++    }
++
++#if 1 // defined(CONFIG_SUNXI_EPHY)
++    gmac_ephy_shutdown(); /* Turn off the clock of PHY for low power consumption  */
++#endif
++
++    if (priv->mii) {
++        mdiobus_unregister(priv->mii);
++        priv->mii->priv = NULL;
++        mdiobus_free(priv->mii);
++        priv->mii = NULL;
++    }
++
++    return 0;
++}
++
++static void geth_rx_refill(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct dma_desc *desc;
++    struct sk_buff *sk = NULL;
++    dma_addr_t paddr;
++
++    while (circ_space(priv->rx_clean, priv->rx_dirty, dma_desc_rx) > 0) {
++        int entry = priv->rx_clean;
++
++        /* Find the dirty's desc and clean it */
++        desc = priv->dma_rx + entry;
++
++        if (priv->rx_sk[entry] == NULL) {
++            sk = netdev_alloc_skb_ip_align(ndev, priv->buf_sz);
++
++            if (unlikely(sk == NULL))
++                break;
++
++            priv->rx_sk[entry] = sk;
++            paddr = dma_map_single(priv->dev, sk->data,
++                           priv->buf_sz, DMA_FROM_DEVICE);
++            desc_buf_set(desc, paddr, priv->buf_sz);
++        }
++
++        /* sync memery */
++        wmb();
++        desc_set_own(desc);
++        priv->rx_clean = circ_inc(priv->rx_clean, dma_desc_rx);
++    }
++}
++
++/* geth_dma_desc_init - initialize the RX/TX descriptor list
++ * @ndev: net device structure
++ * Description: initialize the list for dma.
++ */
++static int geth_dma_desc_init(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    unsigned int buf_sz;
++
++    priv->rx_sk = kzalloc(sizeof(struct sk_buff *) * dma_desc_rx, GFP_KERNEL);
++    if (!priv->rx_sk)
++        return -ENOMEM;
++
++    priv->tx_sk = kzalloc(sizeof(struct sk_buff *) * dma_desc_tx, GFP_KERNEL);
++    if (!priv->tx_sk)
++        goto tx_sk_err;
++
++    /* Set the size of buffer depend on the MTU & max buf size */
++    buf_sz = MAX_BUF_SZ;
++
++    priv->dma_tx = dma_alloc_coherent(priv->dev,
++                                      dma_desc_tx * sizeof(struct dma_desc),
++                                      &priv->dma_tx_phy,
++                                      GFP_KERNEL);
++    if (!priv->dma_tx)
++        goto dma_tx_err;
++
++    priv->dma_rx = dma_alloc_coherent(priv->dev,
++                                      dma_desc_rx * sizeof(struct dma_desc),
++                                      &priv->dma_rx_phy,
++                                      GFP_KERNEL);
++    if (!priv->dma_rx)
++        goto dma_rx_err;
++
++    priv->buf_sz = buf_sz;
++
++    return 0;
++
++dma_rx_err:
++    dma_free_coherent(priv->dev, dma_desc_rx * sizeof(struct dma_desc), priv->dma_tx, priv->dma_tx_phy);
++dma_tx_err:
++    kfree(priv->tx_sk);
++tx_sk_err:
++    kfree(priv->rx_sk);
++
++    return -ENOMEM;
++}
++
++static void geth_free_rx_sk(struct geth_priv *priv)
++{
++    int i;
++
++    for (i = 0; i < dma_desc_rx; i++) {
++        if (priv->rx_sk[i] != NULL) {
++            struct dma_desc *desc = priv->dma_rx + i;
++
++            dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_FROM_DEVICE);
++            dev_kfree_skb_any(priv->rx_sk[i]);
++            priv->rx_sk[i] = NULL;
++        }
++    }
++}
++
++static void geth_free_tx_sk(struct geth_priv *priv)
++{
++    int i;
++
++    for (i = 0; i < dma_desc_tx; i++) {
++        if (priv->tx_sk[i] != NULL) {
++            struct dma_desc *desc = priv->dma_tx + i;
++
++            if (desc_buf_get_addr(desc))
++                dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_TO_DEVICE);
++            dev_kfree_skb_any(priv->tx_sk[i]);
++            priv->tx_sk[i] = NULL;
++        }
++    }
++}
++
++static void geth_free_dma_desc(struct geth_priv *priv)
++{
++    /* Free the region of consistent memory previously allocated for the DMA */
++    dma_free_coherent(priv->dev, dma_desc_tx * sizeof(struct dma_desc), priv->dma_tx, priv->dma_tx_phy);
++    dma_free_coherent(priv->dev, dma_desc_rx * sizeof(struct dma_desc), priv->dma_rx, priv->dma_rx_phy);
++
++    kfree(priv->rx_sk);
++    kfree(priv->tx_sk);
++}
++
++#ifdef CONFIG_PM
++static int geth_select_gpio_state(struct pinctrl *pctrl, char *name)
++{
++    int ret = 0;
++    struct pinctrl_state *pctrl_state = NULL;
++
++    pctrl_state = pinctrl_lookup_state(pctrl, name);
++    if (IS_ERR(pctrl_state)) {
++        pr_err("gmac pinctrl_lookup_state(%s) failed! return %p\n", name, pctrl_state);
++        return -EINVAL;
++    }
++
++    ret = pinctrl_select_state(pctrl, pctrl_state);
++    if (ret < 0)
++        pr_err("gmac pinctrl_select_state(%s) failed! return %d\n", name, ret);
++
++    return ret;
++}
++
++static int geth_suspend(struct device *dev)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    cancel_work_sync(&priv->eth_work);
++
++    if (!ndev || !netif_running(ndev))
++        return 0;
++
++    spin_lock(&priv->lock);
++    netif_device_detach(ndev);
++    spin_unlock(&priv->lock);
++
++    geth_stop(ndev);
++
++    if (priv->phy_ext == EXT_PHY)
++        geth_select_gpio_state(priv->pinctrl, PINCTRL_STATE_SLEEP);
++
++    return 0;
++}
++
++static void geth_resume_work(struct work_struct *work)
++{
++    struct geth_priv *priv = container_of(work, struct geth_priv, eth_work);
++    struct net_device *ndev = priv->ndev;
++
++    if (!netif_running(ndev))
++        return;
++
++    if (priv->phy_ext == EXT_PHY)
++        geth_select_gpio_state(priv->pinctrl, PINCTRL_STATE_DEFAULT);
++
++    geth_open(ndev);
++
++#if 1 //defined(CONFIG_SUNXI_EPHY)
++    if (!ephy_is_enable()) {
++        pr_info("[geth_resume] ephy is not enable, waiting...\n");
++        msleep(2000);
++        if (!ephy_is_enable()) {
++            netdev_err(ndev, "Wait for ephy resume timeout.\n");
++            return;
++        }
++    }
++#endif
++
++    spin_lock(&priv->lock);
++    netif_device_attach(ndev);
++    spin_unlock(&priv->lock);
++
++}
++
++static void geth_resume(struct device *dev)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    schedule_work(&priv->eth_work);
++}
++
++
++
++static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
++{
++	struct net_device *ndev = platform_get_drvdata(ofdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    cancel_work_sync(&priv->eth_work);
++
++    if (!ndev || !netif_running(ndev))
++        return 0;
++
++    spin_lock(&priv->lock);
++    netif_device_detach(ndev);
++    spin_unlock(&priv->lock);
++
++    geth_stop(ndev);
++
++    if (priv->phy_ext == EXT_PHY)
++        geth_select_gpio_state(priv->pinctrl, PINCTRL_STATE_SLEEP);
++
++
++	return 0;
++}
++
++static int ucc_geth_resume(struct platform_device *ofdev)
++{
++	struct net_device *ndev = platform_get_drvdata(ofdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    schedule_work(&priv->eth_work);
++
++
++	return 0;
++}
++
++static int geth_freeze(struct device *dev)
++{
++    return 0;
++}
++
++static int geth_restore(struct device *dev)
++{
++    return 0;
++}
++
++static const struct dev_pm_ops geth_pm_ops = {
++    .complete = geth_resume,
++    .prepare = geth_suspend,
++    .suspend = NULL,
++    .resume = NULL,
++    .freeze = geth_freeze,
++    .restore = geth_restore,
++};
++#else
++static const struct dev_pm_ops geth_pm_ops;
++#endif /* CONFIG_PM */
++
++/*#define sunxi_get_soc_chipid(x) {}*/
++static void geth_chip_hwaddr(u8 *addr)
++{
++#define MD5_SIZE 16
++#define CHIP_SIZE 16
++
++    struct crypto_ahash *tfm;
++    struct ahash_request *req;
++    struct scatterlist sg;
++    u8 result[MD5_SIZE];
++    u8 chipid[CHIP_SIZE];
++    int i = 0;
++    int ret = -1;
++
++    memset(chipid, 0, sizeof(chipid));
++    memset(result, 0, sizeof(result));
++
++    sunxi_get_soc_chipid((u8 *)chipid);
++
++    tfm = crypto_alloc_ahash("md5", 0, CRYPTO_ALG_ASYNC);
++    if (IS_ERR(tfm)) {
++        pr_err("Failed to alloc md5\n");
++        return;
++    }
++
++    req = ahash_request_alloc(tfm, GFP_KERNEL);
++    if (!req)
++        goto out;
++
++    ahash_request_set_callback(req, 0, NULL, NULL);
++
++    ret = crypto_ahash_init(req);
++    if (ret) {
++        pr_err("crypto_ahash_init() failed\n");
++        goto out;
++    }
++
++    sg_init_one(&sg, chipid, sizeof(chipid));
++    ahash_request_set_crypt(req, &sg, result, sizeof(chipid));
++    ret = crypto_ahash_update(req);
++    if (ret) {
++        pr_err("crypto_ahash_update() failed for id\n");
++        goto out;
++    }
++
++    ret = crypto_ahash_final(req);
++    if (ret) {
++        pr_err("crypto_ahash_final() failed for result\n");
++        goto out;
++    }
++
++    ahash_request_free(req);
++
++    /* Choose md5 result's [0][2][4][6][8][10] byte as mac address */
++    for (i = 0; i < ETH_ALEN; i++)
++        addr[i] = result[2 * i];
++    addr[0] &= 0xfe; /* clear multicast bit */
++    addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
++
++out:
++    crypto_free_ahash(tfm);
++}
++
++static void geth_check_addr(struct net_device *ndev, unsigned char *mac)
++{
++    int i;
++    char *p = mac;
++    u8 addr[ETH_ALEN];
++
++    if (!is_valid_ether_addr(ndev->dev_addr)) {
++        for (i = 0; i < ETH_ALEN; i++, p++)
++            addr[i] = simple_strtoul(p, &p, 16);
++
++        if (!is_valid_ether_addr(addr))
++            geth_chip_hwaddr(addr);
++
++        if (!is_valid_ether_addr(addr)) {
++            eth_random_addr(addr);
++            pr_warn("%s: Use random mac address\n", ndev->name);
++        }
++    }
++
++    eth_hw_addr_set(ndev, addr);
++}
++
++static void geth_clk_enable(struct geth_priv *priv)
++{
++    int phy_interface = 0;
++    u32 clk_value;
++    u32 efuse_value;
++
++    if (clk_prepare_enable(priv->geth_clk))
++        pr_err("try to enable geth_clk failed!\n");
++
++    if (((priv->phy_ext == INT_PHY) || g_use_ephy_clk) && !IS_ERR_OR_NULL(priv->ephy_clk)) {
++        if (clk_prepare_enable(priv->ephy_clk))
++            pr_err("try to enable ephy_clk failed!\n");
++    }
++
++    phy_interface = priv->phy_interface;
++
++    clk_value = readl(priv->base_phy);
++    if (phy_interface == PHY_INTERFACE_MODE_RGMII)
++        clk_value |= 0x00000004;
++    else
++        clk_value &= (~0x00000004);
++
++    clk_value &= (~0x00002003);
++    if (phy_interface == PHY_INTERFACE_MODE_RGMII || phy_interface == PHY_INTERFACE_MODE_GMII)
++        clk_value |= 0x00000002;
++    else if (phy_interface == PHY_INTERFACE_MODE_RMII)
++        clk_value |= 0x00002001;
++
++    if (priv->phy_ext == INT_PHY) {
++//         if (0 != sunxi_efuse_read(EFUSE_OEM_NAME, &efuse_value))
++//             pr_err("get PHY efuse fail!\n");
++//         else
++// #if defined(CONFIG_ARCH_SUN50IW2)
++//             clk_value |= (((efuse_value >> 24) & 0x0F) + 3) << 28;
++// #else
++//             pr_warn("miss config come from efuse!\n");
++// #endif
++    }
++
++    /* Adjust Tx/Rx clock delay */
++    clk_value &= ~(0x07 << 10);
++    clk_value |= ((tx_delay & 0x07) << 10);
++    clk_value &= ~(0x1F << 5);
++    clk_value |= ((rx_delay & 0x1F) << 5);
++
++    writel(clk_value, priv->base_phy);
++}
++
++static void geth_clk_disable(struct geth_priv *priv)
++{
++    if (((priv->phy_ext == INT_PHY) || g_use_ephy_clk) && !IS_ERR_OR_NULL(priv->ephy_clk))
++        clk_disable_unprepare(priv->ephy_clk);
++
++    clk_disable_unprepare(priv->geth_clk);
++}
++
++static void geth_tx_err(struct geth_priv *priv)
++{
++    netif_stop_queue(priv->ndev);
++
++    sunxi_stop_tx(priv->base);
++
++    geth_free_tx_sk(priv);
++    memset(priv->dma_tx, 0, dma_desc_tx * sizeof(struct dma_desc));
++    desc_init_chain(priv->dma_tx, (unsigned long)priv->dma_tx_phy, dma_desc_tx);
++    priv->tx_dirty = 0;
++    priv->tx_clean = 0;
++    sunxi_start_tx(priv->base, priv->dma_tx_phy);
++
++    priv->ndev->stats.tx_errors++;
++    netif_wake_queue(priv->ndev);
++}
++
++static inline void geth_schedule(struct geth_priv *priv)
++{
++    if (likely(napi_schedule_prep(&priv->napi))) {
++        sunxi_int_disable(priv->base);
++        __napi_schedule(&priv->napi);
++    }
++}
++
++static irqreturn_t geth_interrupt(int irq, void *dev_id)
++{
++    struct net_device *ndev = (struct net_device *)dev_id;
++    struct geth_priv *priv = netdev_priv(ndev);
++    int status;
++
++    if (unlikely(!ndev)) {
++        pr_err("%s: invalid ndev pointer\n", __func__);
++        return IRQ_NONE;
++    }
++
++    status = sunxi_int_status(priv->base, (void *)(&priv->xstats));
++
++    if (likely(status == handle_tx_rx))
++        geth_schedule(priv);
++    else if (unlikely(status == tx_hard_error_bump_tc))
++        netdev_info(ndev, "Do nothing for bump tc\n");
++    else if (unlikely(status == tx_hard_error))
++        geth_tx_err(priv);
++    else
++        netdev_info(ndev, "Do nothing.....\n");
++
++    return IRQ_HANDLED;
++}
++
++static int geth_open(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    int ret = 0;
++
++    ret = geth_dma_desc_init(ndev);
++    if (ret) {
++        ret = -EINVAL;
++        return ret;
++    }
++
++    ret = geth_power_on(priv);
++    if (ret) {
++        netdev_err(ndev, "Power on is failed\n");
++        ret = -EINVAL;
++        goto power_err;
++    }
++
++    geth_clk_enable(priv);
++
++    ret = geth_phy_init(ndev);
++    if (ret) {
++        netdev_err(ndev, "phy init again...\n");
++        ret = geth_phy_init(ndev);
++        if (ret) {
++            netdev_err(ndev, "phy init failed\n");
++            ret = -EINVAL;
++            goto phy_err;
++        }
++    }
++
++    ret = sunxi_mac_reset((void *)priv->base, &sunxi_udelay, 10000);
++    if (ret) {
++        netdev_err(ndev, "Initialize hardware error\n");
++        goto mac_err;
++    }
++
++    sunxi_mac_init(priv->base, txmode, rxmode);
++    sunxi_set_umac(priv->base, ndev->dev_addr, 0);
++
++    memset(priv->dma_tx, 0, dma_desc_tx * sizeof(struct dma_desc));
++    memset(priv->dma_rx, 0, dma_desc_rx * sizeof(struct dma_desc));
++
++    desc_init_chain(priv->dma_rx, (unsigned long)priv->dma_rx_phy, dma_desc_rx);
++    desc_init_chain(priv->dma_tx, (unsigned long)priv->dma_tx_phy, dma_desc_tx);
++
++    priv->rx_clean = 0;
++    priv->rx_dirty = 0;
++    priv->tx_clean = 0;
++    priv->tx_dirty = 0;
++    geth_rx_refill(ndev);
++
++    /* Extra statistics */
++    memset(&priv->xstats, 0, sizeof(struct geth_extra_stats));
++
++    if (ndev->phydev)
++        phy_start(ndev->phydev);
++
++    sunxi_start_rx(priv->base, (unsigned long)((struct dma_desc *)priv->dma_rx_phy + priv->rx_dirty));
++    sunxi_start_tx(priv->base, (unsigned long)((struct dma_desc *)priv->dma_tx_phy + priv->tx_clean));
++
++    /* Enable the Rx/Tx */
++    sunxi_mac_enable(priv->base);
++
++    netif_carrier_on(ndev);
++
++    napi_enable(&priv->napi);
++    netif_start_queue(ndev);
++
++    return 0;
++
++mac_err:
++    geth_phy_release(ndev);
++phy_err:
++    geth_clk_disable(priv);
++
++    geth_power_off(priv);
++
++power_err:
++    geth_free_dma_desc(priv);
++
++    return ret;
++}
++
++static int geth_stop(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    netif_stop_queue(ndev);
++    napi_disable(&priv->napi);
++
++    netif_carrier_off(ndev);
++
++    /* Release PHY resources */
++    geth_phy_release(ndev);
++
++    /* Disable Rx/Tx */
++    sunxi_mac_disable(priv->base);
++
++    geth_clk_disable(priv);
++    geth_power_off(priv);
++
++    netif_tx_lock_bh(ndev);
++    /* Release the DMA TX/RX socket buffers */
++    geth_free_rx_sk(priv);
++    geth_free_tx_sk(priv);
++    netif_tx_unlock_bh(ndev);
++
++    /* Ensure that hareware have been stopped */
++    geth_free_dma_desc(priv);
++
++    return 0;
++}
++
++static void geth_tx_complete(struct geth_priv *priv)
++{
++    unsigned int entry = 0;
++    struct sk_buff *skb = NULL;
++    struct dma_desc *desc = NULL;
++    int tx_stat;
++
++    spin_lock(&priv->tx_lock);
++    while (circ_cnt(priv->tx_dirty, priv->tx_clean, dma_desc_tx) > 0) {
++        entry = priv->tx_clean;
++        desc = priv->dma_tx + entry;
++
++        /* Check if the descriptor is owned by the DMA. */
++        if (desc_get_own(desc))
++            break;
++
++        /* Verify tx error by looking at the last segment */
++        if (desc_get_tx_ls(desc)) {
++            tx_stat = desc_get_tx_status(desc, (void *)(&priv->xstats));
++
++            if (likely(!tx_stat))
++                priv->ndev->stats.tx_packets++;
++            else
++                priv->ndev->stats.tx_errors++;
++        }
++
++        dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_TO_DEVICE);
++
++        skb = priv->tx_sk[entry];
++        priv->tx_sk[entry] = NULL;
++        desc_init(desc);
++
++        /* Find next dirty desc */
++        priv->tx_clean = circ_inc(entry, dma_desc_tx);
++
++        if (unlikely(skb == NULL))
++            continue;
++
++        dev_kfree_skb(skb);
++    }
++
++    if (unlikely(netif_queue_stopped(priv->ndev)) && circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) > TX_THRESH) {
++        netif_wake_queue(priv->ndev);
++    }
++    spin_unlock(&priv->tx_lock);
++}
++
++static netdev_tx_t geth_xmit(struct sk_buff *skb, struct net_device *ndev)
++{
++    struct geth_priv  *priv = netdev_priv(ndev);
++    unsigned int entry;
++    struct dma_desc *desc, *first;
++    unsigned int len, tmp_len = 0;
++    int i, csum_insert;
++    int nfrags = skb_shinfo(skb)->nr_frags;
++    dma_addr_t paddr;
++
++    spin_lock(&priv->tx_lock);
++    if (unlikely(circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) < (nfrags + 1))) {
++        if (!netif_queue_stopped(ndev)) {
++            netdev_err(ndev, "%s: BUG! Tx Ring full when queue awake\n", __func__);
++            netif_stop_queue(ndev);
++        }
++        spin_unlock(&priv->tx_lock);
++
++        return NETDEV_TX_BUSY;
++    }
++
++    csum_insert = (skb->ip_summed == CHECKSUM_PARTIAL);
++    entry = priv->tx_dirty;
++    first = priv->dma_tx + entry;
++    desc = priv->dma_tx + entry;
++
++    len = skb_headlen(skb);
++    priv->tx_sk[entry] = skb;
++
++#ifdef PKT_DEBUG
++    printk("======TX PKT DATA: ============\n");
++    /* dump the packet */
++    print_hex_dump(KERN_DEBUG, "skb->data: ", DUMP_PREFIX_NONE,
++                   16, 1, skb->data, 64, true);
++#endif
++
++    /* Every desc max size is 2K */
++    while (len != 0) {
++        desc = priv->dma_tx + entry;
++        tmp_len = ((len > MAX_BUF_SZ) ? MAX_BUF_SZ : len);
++
++        paddr = dma_map_single(priv->dev, skb->data, tmp_len, DMA_TO_DEVICE);
++        if (dma_mapping_error(priv->dev, paddr)) {
++            dev_kfree_skb(skb);
++            return -EIO;
++        }
++        desc_buf_set(desc, paddr, tmp_len);
++        /* Don't set the first's own bit, here */
++        if (first != desc) {
++            priv->tx_sk[entry] = NULL;
++            desc_set_own(desc);
++        }
++
++        entry = circ_inc(entry, dma_desc_tx);
++        len -= tmp_len;
++    }
++
++    for (i = 0; i < nfrags; i++) {
++        const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
++
++        len = skb_frag_size(frag);
++        desc = priv->dma_tx + entry;
++        paddr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE);
++        if (dma_mapping_error(priv->dev, paddr)) {
++            dev_kfree_skb(skb);
++            return -EIO;
++        }
++
++        desc_buf_set(desc, paddr, len);
++        desc_set_own(desc);
++        priv->tx_sk[entry] = NULL;
++        entry = circ_inc(entry, dma_desc_tx);
++    }
++
++    ndev->stats.tx_bytes += skb->len;
++    priv->tx_dirty = entry;
++    desc_tx_close(first, desc, csum_insert);
++
++    desc_set_own(first);
++    spin_unlock(&priv->tx_lock);
++
++    if (circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) <= (MAX_SKB_FRAGS + 1)) {
++        netif_stop_queue(ndev);
++        if (circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) > TX_THRESH)
++            netif_wake_queue(ndev);
++    }
++
++#ifdef DEBUG
++    printk("=======TX Descriptor DMA: 0x%08llx\n", priv->dma_tx_phy);
++    printk("Tx pointor: dirty: %d, clean: %d\n", priv->tx_dirty, priv->tx_clean);
++    desc_print(priv->dma_tx, dma_desc_tx);
++#endif
++    sunxi_tx_poll(priv->base);
++    geth_tx_complete(priv);
++
++    return NETDEV_TX_OK;
++}
++
++static int geth_rx(struct geth_priv *priv, int limit)
++{
++    unsigned int rxcount = 0;
++    unsigned int entry;
++    struct dma_desc *desc;
++    struct sk_buff *skb;
++    int status;
++    int frame_len;
++
++    while (rxcount < limit) {
++        entry = priv->rx_dirty;
++        desc = priv->dma_rx + entry;
++
++        if (desc_get_own(desc))
++            break;
++
++        rxcount++;
++        priv->rx_dirty = circ_inc(priv->rx_dirty, dma_desc_rx);
++
++        /* Get length & status from hardware */
++        frame_len = desc_rx_frame_len(desc);
++        status = desc_get_rx_status(desc, (void *)(&priv->xstats));
++
++        netdev_dbg(priv->ndev, "Rx frame size %d, status: %d\n", frame_len, status);
++
++        skb = priv->rx_sk[entry];
++        if (unlikely(!skb)) {
++            netdev_err(priv->ndev, "Skb is null\n");
++            priv->ndev->stats.rx_dropped++;
++            break;
++        }
++
++#ifdef PKT_DEBUG
++        printk("======RX PKT DATA: ============\n");
++        /* dump the packet */
++        print_hex_dump(KERN_DEBUG, "skb->data: ", DUMP_PREFIX_NONE,
++                       16, 1, skb->data, 64, true);
++#endif
++
++        if (status == discard_frame) {
++            netdev_dbg(priv->ndev, "Get error pkt\n");
++            priv->ndev->stats.rx_errors++;
++            continue;
++        }
++
++        if (unlikely(status != llc_snap))
++            frame_len -= ETH_FCS_LEN;
++
++        priv->rx_sk[entry] = NULL;
++
++        skb_put(skb, frame_len);
++        dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_FROM_DEVICE);
++
++        skb->protocol = eth_type_trans(skb, priv->ndev);
++
++        skb->ip_summed = CHECKSUM_UNNECESSARY;
++        napi_gro_receive(&priv->napi, skb);
++
++        priv->ndev->stats.rx_packets++;
++        priv->ndev->stats.rx_bytes += frame_len;
++    }
++
++#ifdef DEBUG
++    if (rxcount > 0) {
++        printk("======RX Descriptor DMA: 0x%08llx=\n", priv->dma_rx_phy);
++        printk("RX pointor: dirty: %d, clean: %d\n", priv->rx_dirty, priv->rx_clean);
++        desc_print(priv->dma_rx, dma_desc_rx);
++    }
++#endif
++    geth_rx_refill(priv->ndev);
++
++    return rxcount;
++}
++
++static int geth_poll(struct napi_struct *napi, int budget)
++{
++    struct geth_priv *priv = container_of(napi, struct geth_priv, napi);
++    int work_done = 0;
++
++    geth_tx_complete(priv);
++    work_done = geth_rx(priv, budget);
++
++    if (work_done < budget) {
++        napi_complete(napi);
++        sunxi_int_enable(priv->base);
++    }
++
++    return work_done;
++}
++
++static int geth_change_mtu(struct net_device *ndev, int new_mtu)
++{
++    int max_mtu;
++
++    if (netif_running(ndev)) {
++        pr_err("%s: must be stopped to change its MTU\n", ndev->name);
++        return -EBUSY;
++    }
++
++    max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
++
++    if ((new_mtu < 46) || (new_mtu > max_mtu)) {
++        pr_err("%s: invalid MTU, max MTU is: %d\n", ndev->name, max_mtu);
++        return -EINVAL;
++    }
++
++    ndev->mtu = new_mtu;
++    netdev_update_features(ndev);
++
++    return 0;
++}
++
++static netdev_features_t geth_fix_features(struct net_device *ndev, netdev_features_t features)
++{
++    return features;
++}
++
++static void geth_set_rx_mode(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    unsigned int value = 0;
++
++    pr_debug("%s: # mcasts %d, # unicast %d\n",
++             __func__, netdev_mc_count(ndev), netdev_uc_count(ndev));
++
++    spin_lock(&priv->lock);
++    if (ndev->flags & IFF_PROMISC) {
++        value = GETH_FRAME_FILTER_PR;
++    } else if ((netdev_mc_count(ndev) > HASH_TABLE_SIZE) ||
++               (ndev->flags & IFF_ALLMULTI)) {
++        value = GETH_FRAME_FILTER_PM; /* pass all multi */
++        sunxi_hash_filter(priv->base, ~0UL, ~0UL);
++    } else if (!netdev_mc_empty(ndev)) {
++        u32 mc_filter[2];
++        struct netdev_hw_addr *ha;
++
++        /* Hash filter for multicast */
++        value = GETH_FRAME_FILTER_HMC;
++
++        memset(mc_filter, 0, sizeof(mc_filter));
++        netdev_for_each_mc_addr(ha, ndev) {
++            /* The upper 6 bits of the calculated CRC are used to
++             *  index the contens of the hash table
++             */
++            int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
++            /* The most significant bit determines the register to
++             * use (H/L) while the other 5 bits determine the bit
++             * within the register.
++             */
++            mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
++        }
++        sunxi_hash_filter(priv->base, mc_filter[0], mc_filter[1]);
++    }
++
++    /* Handle multiple unicast addresses (perfect filtering)*/
++    if (netdev_uc_count(ndev) > 16) {
++        /* Switch to promiscuous mode is more than 8 addrs are required */
++        value |= GETH_FRAME_FILTER_PR;
++    } else {
++        int reg = 1;
++        struct netdev_hw_addr *ha;
++
++        netdev_for_each_uc_addr(ha, ndev) {
++            sunxi_set_umac(priv->base, ha->addr, reg);
++            reg++;
++        }
++    }
++
++#ifdef FRAME_FILTER_DEBUG
++    /* Enable Receive all mode (to debug filtering_fail errors) */
++    value |= GETH_FRAME_FILTER_RA;
++#endif
++    sunxi_set_filter(priv->base, value);
++    spin_unlock(&priv->lock);
++}
++
++static void geth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    geth_tx_err(priv);
++}
++
++static int geth_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
++{
++    if (!netif_running(ndev))
++        return -EINVAL;
++
++    if (!ndev->phydev)
++        return -EINVAL;
++
++    return phy_mii_ioctl(ndev->phydev, rq, cmd);
++}
++
++/* Configuration changes (passed on by ifconfig) */
++static int geth_config(struct net_device *ndev, struct ifmap *map)
++{
++    if (ndev->flags & IFF_UP) /* can't act on a running interface */
++        return -EBUSY;
++
++    /* Don't allow changing the I/O address */
++    if (map->base_addr != ndev->base_addr) {
++        pr_warn("%s: can't change I/O address\n", ndev->name);
++        return -EOPNOTSUPP;
++    }
++
++    /* Don't allow changing the IRQ */
++    if (map->irq != ndev->irq) {
++        pr_warn("%s: can't change IRQ number %d\n", ndev->name, ndev->irq);
++        return -EOPNOTSUPP;
++    }
++
++    return 0;
++}
++
++static int geth_set_mac_address(struct net_device *ndev, void *p)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct sockaddr *addr = p;
++
++    if (!is_valid_ether_addr(addr->sa_data))
++        return -EADDRNOTAVAIL;
++
++	eth_hw_addr_set(ndev, addr->sa_data);
++
++    sunxi_set_umac(priv->base, ndev->dev_addr, 0);
++
++    return 0;
++}
++
++int geth_set_features(struct net_device *ndev, netdev_features_t features)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    if (features & NETIF_F_LOOPBACK && netif_running(ndev))
++        sunxi_mac_loopback(priv->base, 1);
++    else
++        sunxi_mac_loopback(priv->base, 0);
++
++    return 0;
++}
++
++#ifdef CONFIG_NET_POLL_CONTROLLER
++/* Polling receive - used by NETCONSOLE and other diagnostic tools
++ * to allow network I/O with interrupts disabled.
++ */
++static void geth_poll_controller(struct net_device *dev)
++{
++    disable_irq(dev->irq);
++    geth_interrupt(dev->irq, dev);
++    enable_irq(dev->irq);
++}
++#endif
++
++static const struct net_device_ops geth_netdev_ops = {
++    .ndo_init = NULL,
++    .ndo_open = geth_open,
++    .ndo_start_xmit = geth_xmit,
++    .ndo_stop = geth_stop,
++    .ndo_change_mtu = geth_change_mtu,
++    .ndo_fix_features = geth_fix_features,
++    .ndo_set_rx_mode = geth_set_rx_mode,
++    .ndo_tx_timeout = geth_tx_timeout,
++    .ndo_do_ioctl = geth_ioctl,
++    .ndo_set_config = geth_config,
++#ifdef CONFIG_NET_POLL_CONTROLLER
++    .ndo_poll_controller = geth_poll_controller,
++#endif
++    .ndo_set_mac_address = geth_set_mac_address,
++    .ndo_set_features = geth_set_features,
++};
++
++static int geth_check_if_running(struct net_device *ndev)
++{
++    if (!netif_running(ndev))
++        return -EBUSY;
++    return 0;
++}
++
++static int geth_get_sset_count(struct net_device *netdev, int sset)
++{
++    int len;
++
++    switch (sset) {
++    case ETH_SS_STATS:
++        len = 0;
++        return len;
++    default:
++        return -EOPNOTSUPP;
++    }
++}
++
++#if 0
++static int geth_ethtool_getsettings(struct net_device *ndev,
++                    struct ethtool_cmd *cmd)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phy = ndev->phydev;
++    int rc;
++
++    if (phy == NULL) {
++        netdev_err(ndev, "%s: %s: PHY is not registered\n",
++               __func__, ndev->name);
++        return -ENODEV;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_err("%s: interface is disabled: we cannot track "
++               "link speed / duplex setting\n", ndev->name);
++        return -EBUSY;
++    }
++
++    cmd->transceiver = XCVR_INTERNAL;
++    spin_lock_irq(&priv->lock);
++    rc = phy_ethtool_gset(phy, cmd);
++    spin_unlock_irq(&priv->lock);
++
++    return rc;
++}
++
++static int geth_ethtool_setsettings(struct net_device *ndev,
++                    struct ethtool_cmd *cmd)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phy = ndev->phydev;
++    int rc;
++
++    spin_lock(&priv->lock);
++    rc = phy_ethtool_sset(phy, cmd);
++    spin_unlock(&priv->lock);
++
++    return rc;
++}
++#endif
++
++static void geth_ethtool_getdrvinfo(struct net_device *ndev,
++                                    struct ethtool_drvinfo *info)
++{
++    strlcpy(info->driver, "sunxi_geth", sizeof(info->driver));
++
++#define DRV_MODULE_VERSION "SUNXI Gbgit driver V1.1"
++
++    strcpy(info->version, DRV_MODULE_VERSION);
++    info->fw_version[0] = '\0';
++}
++
++static const struct ethtool_ops geth_ethtool_ops = {
++    .begin = geth_check_if_running,
++    // .get_settings = geth_ethtool_getsettings,
++    // .set_settings = geth_ethtool_setsettings,
++    .get_link_ksettings = phy_ethtool_get_link_ksettings,
++    .set_link_ksettings = phy_ethtool_set_link_ksettings,
++    .get_link = ethtool_op_get_link,
++    .get_pauseparam = NULL,
++    .set_pauseparam = NULL,
++    .get_ethtool_stats = NULL,
++    .get_strings = NULL,
++    .get_wol = NULL,
++    .set_wol = NULL,
++    .get_sset_count = geth_get_sset_count,
++    .get_drvinfo = geth_ethtool_getdrvinfo,
++};
++
++struct gpio_config {
++	u32	gpio;
++	u32	mul_sel;
++	u32	pull;
++	u32	drv_level;
++	u32	data;
++};
++
++/* config hardware resource */
++static int geth_hw_init(struct platform_device *pdev)
++{
++    struct net_device *ndev = platform_get_drvdata(pdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct device_node *np = pdev->dev.of_node;
++    int ret = 0;
++    struct resource *res;
++    u32 value;
++    struct gpio_config cfg;
++    const char *gmac_power;
++    char power[20];
++    int i;
++
++// #ifdef CONFIG_SUNXI_EXT_PHY
++    priv->phy_ext = EXT_PHY;
++// #else
++//     priv->phy_ext = INT_PHY;
++// #endif
++
++    /* config memery resource */
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++    if (unlikely(!res)) {
++        pr_err("%s: ERROR: get gmac memory failed", __func__);
++        return -ENODEV;
++    }
++
++    priv->base = devm_ioremap_resource(&pdev->dev, res);
++    if (!priv->base) {
++        pr_err("%s: ERROR: gmac memory mapping failed", __func__);
++        return -ENOMEM;
++    }
++
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++    if (unlikely(!res)) {
++        pr_err("%s: ERROR: get phy memory failed", __func__);
++        ret = -ENODEV;
++        goto mem_err;
++    }
++
++    priv->base_phy = devm_ioremap_resource(&pdev->dev, res);
++    if (unlikely(!priv->base_phy)) {
++        pr_err("%s: ERROR: phy memory mapping failed", __func__);
++        ret = -ENOMEM;
++        goto mem_err;
++    }
++
++    /* config IRQ */
++    ndev->irq = platform_get_irq_byname(pdev, "gmacirq");
++    if (ndev->irq == -ENXIO) {
++        pr_err("%s: ERROR: MAC IRQ not found\n", __func__);
++        ret = -ENXIO;
++        goto irq_err;
++    }
++
++    ret = request_irq(ndev->irq, geth_interrupt, IRQF_SHARED, dev_name(&pdev->dev), ndev);
++    if (unlikely(ret < 0)) {
++        pr_err("Could not request irq %d, error: %d\n", ndev->irq, ret);
++        goto irq_err;
++    }
++
++    /* config clock */
++    priv->geth_clk = of_clk_get_by_name(np, "bus-emac1");
++    if (unlikely(!priv->geth_clk || IS_ERR(priv->geth_clk))) {
++        pr_err("Get gmac clock failed!\n");
++        ret = -EINVAL;
++        goto clk_err;
++    }
++
++    if (INT_PHY == priv->phy_ext) {
++        priv->ephy_clk = of_clk_get_by_name(np, "emac-25m");
++        if (unlikely(IS_ERR_OR_NULL(priv->ephy_clk))) {
++            pr_err("Get ephy clock failed!\n");
++            ret = -EINVAL;
++            goto clk_err;
++        }
++    }
++#if 1 // defined(CONFIG_ARCH_SUN8IW12) || defined(CONFIG_ARCH_SUN50IW9)
++    else {
++        if (!of_property_read_u32(np, "use_ephy25m", &g_use_ephy_clk)
++                && g_use_ephy_clk) {
++            priv->ephy_clk = of_clk_get_by_name(np, "ephy");
++            if (unlikely(IS_ERR_OR_NULL(priv->ephy_clk))) {
++                pr_err("Get ephy clk failed!\n");
++                ret = -EINVAL;
++                goto clk_err;
++            }
++        }
++    }
++#endif
++
++    /* config power regulator */
++    if (EXT_PHY == priv->phy_ext) {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            snprintf(power, 15, "gmac-power%d", i);
++            ret = of_property_read_string(np, power, &gmac_power);
++            if (ret) {
++                priv->gmac_power[i] = NULL;
++                pr_info("gmac-power%d: NULL\n", i);
++                continue;
++            }
++            priv->gmac_power[i] = regulator_get(NULL, gmac_power);
++            if (IS_ERR(priv->gmac_power[i])) {
++                pr_err("gmac-power%d get error!\n", i);
++                ret = -EINVAL;
++                goto clk_err;
++            }
++        }
++    }
++
++    // /* config other parameters */
++    // priv->phy_interface = of_get_phy_mode(np);
++    // if (priv->phy_interface != PHY_INTERFACE_MODE_MII &&
++    //     priv->phy_interface != PHY_INTERFACE_MODE_RGMII &&
++    //     priv->phy_interface != PHY_INTERFACE_MODE_RMII) {
++    //     pr_err("Not support phy type!\n");
++    //     priv->phy_interface = PHY_INTERFACE_MODE_MII;
++    // }
++
++    priv->phy_interface = PHY_INTERFACE_MODE_RMII;
++
++    if (!of_property_read_u32(np, "tx-delay", &value))
++        tx_delay = value;
++
++    if (!of_property_read_u32(np, "rx-delay", &value))
++        rx_delay = value;
++
++    /* config pinctrl */
++    if (EXT_PHY == priv->phy_ext) {
++        priv->phyrst = of_get_named_gpio_flags(np, "phy-rst", 0, (enum of_gpio_flags *)&cfg);
++        priv->rst_active_low = (cfg.data == OF_GPIO_ACTIVE_LOW) ? 1 : 0;
++
++        if (gpio_is_valid(priv->phyrst)) {
++            if (gpio_request(priv->phyrst, "phy-rst") < 0) {
++                pr_err("gmac gpio request fail!\n");
++                ret = -EINVAL;
++                goto pin_err;
++            }
++        }
++
++        priv->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++        if (IS_ERR_OR_NULL(priv->pinctrl)) {
++            pr_err("gmac pinctrl error!\n");
++            priv->pinctrl = NULL;
++            ret = -EINVAL;
++            goto pin_err;
++        }
++    }
++
++    priv->ephy_rst = devm_reset_control_get_optional(&pdev->dev, "stmmaceth");
++    reset_control_assert(priv->ephy_rst);
++    reset_control_deassert(priv->ephy_rst);
++
++    msleep(800);
++
++    return 0;
++
++pin_err:
++    if (EXT_PHY == priv->phy_ext) {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            regulator_put(priv->gmac_power[i]);
++        }
++    }
++clk_err:
++    free_irq(ndev->irq, ndev);
++irq_err:
++    devm_iounmap(&pdev->dev, priv->base_phy);
++mem_err:
++    devm_iounmap(&pdev->dev, priv->base);
++
++    return ret;
++}
++
++static void geth_hw_release(struct platform_device *pdev)
++{
++    struct net_device *ndev = platform_get_drvdata(pdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    int i;
++
++    devm_iounmap(&pdev->dev, (priv->base_phy));
++    devm_iounmap(&pdev->dev, priv->base);
++    free_irq(ndev->irq, ndev);
++    if (priv->geth_clk)
++        clk_put(priv->geth_clk);
++
++    if (EXT_PHY == priv->phy_ext) {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            regulator_put(priv->gmac_power[i]);
++        }
++
++        if (!IS_ERR_OR_NULL(priv->pinctrl))
++            devm_pinctrl_put(priv->pinctrl);
++
++        if (gpio_is_valid(priv->phyrst))
++            gpio_free(priv->phyrst);
++    }
++
++    if (!IS_ERR_OR_NULL(priv->ephy_clk))
++        clk_put(priv->ephy_clk);
++}
++
++/**
++ * geth_probe
++ * @pdev: platform device pointer
++ * Description: the driver is initialized through platform_device.
++ */
++static int geth_probe(struct platform_device *pdev)
++{
++    int ret = 0;
++    struct net_device *ndev = NULL;
++    struct geth_priv *priv;
++
++#ifdef CONFIG_OF
++    pdev->dev.dma_mask = &geth_dma_mask;
++    pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++#endif
++
++    ndev = alloc_etherdev(sizeof(struct geth_priv));
++    if (!ndev) {
++        dev_err(&pdev->dev, "could not allocate device.\n");
++        return -ENOMEM;
++    }
++    SET_NETDEV_DEV(ndev, &pdev->dev);
++
++    priv = netdev_priv(ndev);
++    platform_set_drvdata(pdev, ndev);
++
++    /* Must set private data to pdev, before call it */
++    ret = geth_hw_init(pdev);
++    if (0 != ret) {
++        pr_err("geth_hw_init fail!\n");
++        goto hw_err;
++    }
++
++    /* setup the netdevice, fill the field of netdevice */
++    ether_setup(ndev);
++    ndev->netdev_ops = &geth_netdev_ops;
++    netdev_set_default_ethtool_ops(ndev, &geth_ethtool_ops);
++    ndev->base_addr = (unsigned long)priv->base;
++
++    priv->ndev = ndev;
++    priv->dev = &pdev->dev;
++
++    /* TODO: support the VLAN frames */
++    ndev->hw_features = NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_IP_CSUM |
++                        NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
++
++    ndev->features |= ndev->hw_features;
++    ndev->hw_features |= NETIF_F_LOOPBACK;
++    ndev->priv_flags |= IFF_UNICAST_FLT;
++
++    ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
++
++    netif_napi_add(ndev, &priv->napi, geth_poll);
++
++    spin_lock_init(&priv->lock);
++    spin_lock_init(&priv->tx_lock);
++
++    /* The last val is mdc clock ratio */
++    sunxi_geth_register((void *)ndev->base_addr, HW_VERSION, 0x03);
++
++    ret = register_netdev(ndev);
++    if (ret) {
++        netif_napi_del(&priv->napi);
++        pr_err("Error: Register %s failed\n", ndev->name);
++        goto reg_err;
++    }
++
++    /* Before open the device, the mac address should be set */
++    geth_check_addr(ndev, mac_str);
++
++#ifdef CONFIG_GETH_ATTRS
++    geth_create_attrs(ndev);
++#endif
++    device_create_file(&pdev->dev, &dev_attr_gphy_test);
++    device_create_file(&pdev->dev, &dev_attr_mii_read);
++    device_create_file(&pdev->dev, &dev_attr_mii_write);
++
++    device_enable_async_suspend(&pdev->dev);
++
++#ifdef CONFIG_PM
++    INIT_WORK(&priv->eth_work, geth_resume_work);
++#endif
++
++    return 0;
++
++reg_err:
++    geth_hw_release(pdev);
++hw_err:
++    platform_set_drvdata(pdev, NULL);
++    free_netdev(ndev);
++
++    return ret;
++}
++
++static int geth_remove(struct platform_device *pdev)
++{
++    struct net_device *ndev = platform_get_drvdata(pdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    device_remove_file(&pdev->dev, &dev_attr_gphy_test);
++    device_remove_file(&pdev->dev, &dev_attr_mii_read);
++    device_remove_file(&pdev->dev, &dev_attr_mii_write);
++
++    netif_napi_del(&priv->napi);
++    unregister_netdev(ndev);
++    geth_hw_release(pdev);
++    platform_set_drvdata(pdev, NULL);
++    free_netdev(ndev);
++
++    return 0;
++}
++
++static const struct of_device_id geth_of_match[] = {
++    {.compatible = "allwinner,sunxi-gmac",},
++    {},
++};
++MODULE_DEVICE_TABLE(of, geth_of_match);
++
++static struct platform_driver geth_driver = {
++    .probe = geth_probe,
++    .remove = geth_remove,
++	.suspend	= ucc_geth_suspend,
++	.resume		= ucc_geth_resume,
++    .driver = {
++        .name = "sunxi-gmac",
++        .owner = THIS_MODULE,
++        .pm = &geth_pm_ops,
++        .of_match_table = geth_of_match,
++    },
++};
++module_platform_driver(geth_driver);
++
++#ifndef MODULE
++static int __init set_mac_addr(char *str)
++{
++    char *p = str;
++
++    if (str && strlen(str))
++        memcpy(mac_str, p, 18);
++
++    return 0;
++}
++__setup("mac_addr=", set_mac_addr);
++#endif
++
++MODULE_DESCRIPTION("Allwinner Gigabit Ethernet driver");
++MODULE_AUTHOR("fuzhaoke <fuzhaoke@allwinnertech.com>");
++MODULE_LICENSE("Dual BSD/GPL");
+diff --git a/drivers/net/ethernet/allwinner/sunxi-gmac.h b/drivers/net/ethernet/allwinner/sunxi-gmac.h
+new file mode 100644
+index 000000000000..0ba8977d28f4
+--- /dev/null
++++ b/drivers/net/ethernet/allwinner/sunxi-gmac.h
+@@ -0,0 +1,270 @@
++/*
++ * linux/drivers/net/ethernet/allwinner/sunxi_gmac.h
++ *
++ * Copyright © 2016-2018, fuzhaoke
++ *		Author: fuzhaoke <fuzhaoke@allwinnertech.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ */
++#ifndef __SUNXI_GETH_H__
++#define __SUNXI_GETH_H__
++
++#include <linux/etherdevice.h>
++#include <linux/netdevice.h>
++#include <linux/phy.h>
++#include <linux/module.h>
++#include <linux/init.h>
++
++/* GETH_FRAME_FILTER  register value */
++#define GETH_FRAME_FILTER_PR	0x00000001	/* Promiscuous Mode */
++#define GETH_FRAME_FILTER_HUC	0x00000002	/* Hash Unicast */
++#define GETH_FRAME_FILTER_HMC	0x00000004	/* Hash Multicast */
++#define GETH_FRAME_FILTER_DAIF	0x00000008	/* DA Inverse Filtering */
++#define GETH_FRAME_FILTER_PM	0x00000010	/* Pass all multicast */
++#define GETH_FRAME_FILTER_DBF	0x00000020	/* Disable Broadcast frames */
++#define GETH_FRAME_FILTER_SAIF	0x00000100	/* Inverse Filtering */
++#define GETH_FRAME_FILTER_SAF	0x00000200	/* Source Address Filter */
++#define GETH_FRAME_FILTER_HPF	0x00000400	/* Hash or perfect Filter */
++#define GETH_FRAME_FILTER_RA	0x80000000	/* Receive all mode */
++
++/* Default tx descriptor */
++#define TX_SINGLE_DESC0		0x80000000
++#define TX_SINGLE_DESC1		0x63000000
++
++/* Default rx descriptor */
++#define RX_SINGLE_DESC0		0x80000000
++#define RX_SINGLE_DESC1		0x83000000
++
++#define EPHY_ID			0x00441400
++#define AC300_ID		0xc0000000
++#define EPHY_ID_RTL8211F	0x001CC916
++#define IP101G_ID		0x02430c54
++
++typedef union {
++	struct {
++		/* TDES0 */
++		unsigned int deferred:1;	/* Deferred bit (only half-duplex) */
++		unsigned int under_err:1;	/* Underflow error */
++		unsigned int ex_deferral:1;	/* Excessive deferral */
++		unsigned int coll_cnt:4;	/* Collision count */
++		unsigned int vlan_tag:1;	/* VLAN Frame */
++		unsigned int ex_coll:1;		/* Excessive collision */
++		unsigned int late_coll:1;	/* Late collision */
++		unsigned int no_carr:1;		/* No carrier */
++		unsigned int loss_carr:1;	/* Loss of collision */
++		unsigned int ipdat_err:1;	/* IP payload error */
++		unsigned int frm_flu:1;		/* Frame flushed */
++		unsigned int jab_timeout:1;	/* Jabber timeout */
++		unsigned int err_sum:1;		/* Error summary */
++		unsigned int iphead_err:1;	/* IP header error */
++		unsigned int ttss:1;		/* Transmit time stamp status */
++		unsigned int reserved0:13;
++		unsigned int own:1;		/* Own bit. CPU:0, DMA:1 */
++	} tx;
++
++	/* bits 5 7 0 | Frame status
++	 * ----------------------------------------------------------
++	 *      0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
++	 *      1 0 0 | IPv4/6 No CSUM errorS.
++	 *      1 0 1 | IPv4/6 CSUM PAYLOAD error
++	 *      1 1 0 | IPv4/6 CSUM IP HR error
++	 *      1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS
++	 *      0 0 1 | IPv4/6 unsupported IP PAYLOAD
++	 *      0 1 1 | COE bypassed.. no IPv4/6 frame
++	 *      0 1 0 | Reserved.
++	 */
++	struct {
++		/* RDES0 */
++		unsigned int chsum_err:1;	/* Payload checksum error */
++		unsigned int crc_err:1;		/* CRC error */
++		unsigned int dribbling:1;	/* Dribble bit error */
++		unsigned int mii_err:1;		/* Received error (bit3) */
++		unsigned int recv_wt:1;		/* Received watchdog timeout */
++		unsigned int frm_type:1;	/* Frame type */
++		unsigned int late_coll:1;	/* Late Collision */
++		unsigned int ipch_err:1;	/* IPv header checksum error (bit7) */
++		unsigned int last_desc:1;	/* Laset descriptor */
++		unsigned int first_desc:1;	/* First descriptor */
++		unsigned int vlan_tag:1;	/* VLAN Tag */
++		unsigned int over_err:1;	/* Overflow error (bit11) */
++		unsigned int len_err:1;		/* Length error */
++		unsigned int sou_filter:1;	/* Source address filter fail */
++		unsigned int desc_err:1;	/* Descriptor error */
++		unsigned int err_sum:1;		/* Error summary (bit15) */
++		unsigned int frm_len:14;	/* Frame length */
++		unsigned int des_filter:1;	/* Destination address filter fail */
++		unsigned int own:1;		/* Own bit. CPU:0, DMA:1 */
++	#define RX_PKT_OK		0x7FFFB77C
++	#define RX_LEN			0x3FFF0000
++	} rx;
++
++	unsigned int all;
++} desc0_u;
++
++typedef union {
++	struct {
++		/* TDES1 */
++		unsigned int buf1_size:11;	/* Transmit buffer1 size */
++		unsigned int buf2_size:11;	/* Transmit buffer2 size */
++		unsigned int ttse:1;		/* Transmit time stamp enable */
++		unsigned int dis_pad:1;		/* Disable pad (bit23) */
++		unsigned int adr_chain:1;	/* Second address chained */
++		unsigned int end_ring:1;	/* Transmit end of ring */
++		unsigned int crc_dis:1;		/* Disable CRC */
++		unsigned int cic:2;		/* Checksum insertion control (bit27:28) */
++		unsigned int first_sg:1;	/* First Segment */
++		unsigned int last_seg:1;	/* Last Segment */
++		unsigned int interrupt:1;	/* Interrupt on completion */
++	} tx;
++
++	struct {
++		/* RDES1 */
++		unsigned int buf1_size:11;	/* Received buffer1 size */
++		unsigned int buf2_size:11;	/* Received buffer2 size */
++		unsigned int reserved1:2;
++		unsigned int adr_chain:1;	/* Second address chained */
++		unsigned int end_ring:1;		/* Received end of ring */
++		unsigned int reserved2:5;
++		unsigned int dis_ic:1;		/* Disable interrupt on completion */
++	} rx;
++
++	unsigned int all;
++} desc1_u;
++
++typedef struct dma_desc {
++	desc0_u desc0;
++	desc1_u desc1;
++	/* The address of buffers */
++	unsigned int	desc2;
++	/* Next desc's address */
++	unsigned int	desc3;
++} __attribute__((packed)) dma_desc_t;
++
++enum rx_frame_status { /* IPC status */
++	good_frame = 0,
++	discard_frame = 1,
++	csum_none = 2,
++	llc_snap = 4,
++};
++
++enum tx_dma_irq_status {
++	tx_hard_error = 1,
++	tx_hard_error_bump_tc = 2,
++	handle_tx_rx = 3,
++};
++
++struct geth_extra_stats {
++	/* Transmit errors */
++	unsigned long tx_underflow;
++	unsigned long tx_carrier;
++	unsigned long tx_losscarrier;
++	unsigned long vlan_tag;
++	unsigned long tx_deferred;
++	unsigned long tx_vlan;
++	unsigned long tx_jabber;
++	unsigned long tx_frame_flushed;
++	unsigned long tx_payload_error;
++	unsigned long tx_ip_header_error;
++
++	/* Receive errors */
++	unsigned long rx_desc;
++	unsigned long sa_filter_fail;
++	unsigned long overflow_error;
++	unsigned long ipc_csum_error;
++	unsigned long rx_collision;
++	unsigned long rx_crc;
++	unsigned long dribbling_bit;
++	unsigned long rx_length;
++	unsigned long rx_mii;
++	unsigned long rx_multicast;
++	unsigned long rx_gmac_overflow;
++	unsigned long rx_watchdog;
++	unsigned long da_rx_filter_fail;
++	unsigned long sa_rx_filter_fail;
++	unsigned long rx_missed_cntr;
++	unsigned long rx_overflow_cntr;
++	unsigned long rx_vlan;
++
++	/* Tx/Rx IRQ errors */
++	unsigned long tx_undeflow_irq;
++	unsigned long tx_process_stopped_irq;
++	unsigned long tx_jabber_irq;
++	unsigned long rx_overflow_irq;
++	unsigned long rx_buf_unav_irq;
++	unsigned long rx_process_stopped_irq;
++	unsigned long rx_watchdog_irq;
++	unsigned long tx_early_irq;
++	unsigned long fatal_bus_error_irq;
++
++	/* Extra info */
++	unsigned long threshold;
++	unsigned long tx_pkt_n;
++	unsigned long rx_pkt_n;
++	unsigned long poll_n;
++	unsigned long sched_timer_n;
++	unsigned long normal_irq_n;
++};
++
++struct mii_reg_dump {
++	u32 addr;
++	u16 reg;
++	u16 value;
++};
++
++int sunxi_mdio_read(void *,  int, int);
++int sunxi_mdio_write(void *, int, int, unsigned short);
++int sunxi_mdio_reset(void *);
++void sunxi_set_link_mode(void *iobase, int duplex, int speed);
++void sunxi_int_disable(void *);
++int sunxi_int_status(void *, struct geth_extra_stats *x);
++int sunxi_mac_init(void *, int txmode, int rxmode);
++void sunxi_set_umac(void *, unsigned char *, int);
++void sunxi_mac_enable(void *);
++void sunxi_mac_disable(void *);
++void sunxi_tx_poll(void *);
++void sunxi_int_enable(void *);
++void sunxi_start_rx(void *, unsigned long);
++void sunxi_start_tx(void *, unsigned long);
++void sunxi_stop_tx(void *);
++void sunxi_stop_rx(void *);
++void sunxi_hash_filter(void *iobase, unsigned long low, unsigned long high);
++void sunxi_set_filter(void *iobase, unsigned long flags);
++void sunxi_flow_ctrl(void *iobase, int duplex, int fc, int pause);
++void sunxi_mac_loopback(void *iobase, int enable);
++
++void desc_buf_set(struct dma_desc *p, unsigned long paddr, int size);
++void desc_set_own(struct dma_desc *p);
++void desc_init_chain(struct dma_desc *p, unsigned long paddr,  unsigned int size);
++void desc_tx_close(struct dma_desc *first, struct dma_desc *end, int csum_insert);
++void desc_init(struct dma_desc *p);
++int desc_get_tx_status(struct dma_desc *desc, struct geth_extra_stats *x);
++int desc_buf_get_len(struct dma_desc *desc);
++int desc_buf_get_addr(struct dma_desc *desc);
++int desc_get_rx_status(struct dma_desc *desc, struct geth_extra_stats *x);
++int desc_get_own(struct dma_desc *desc);
++int desc_get_tx_ls(struct dma_desc *desc);
++int desc_rx_frame_len(struct dma_desc *desc);
++
++int sunxi_mac_reset(void *iobase, void (*mdelay)(int), int n);
++int sunxi_geth_register(void *iobase, int version, unsigned int div);
++
++int sunxi_parse_read_str(char *str, u16 *addr, u16 *reg);
++int sunxi_parse_write_str(char *str, u16 *addr, u16 *reg, u16 *val);
++extern int ephy_is_enable(void);
++extern int gmac_ephy_shutdown(void);
++
++#if defined(CONFIG_ARCH_SUN8IW3) \
++	|| defined(CONFIG_ARCH_SUN9IW1) \
++	|| defined(CONFIG_ARCH_SUN7I)
++#define HW_VERSION	0
++#else
++#define HW_VERSION	1
++#endif
++
++#endif
+diff --git a/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c b/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
+new file mode 100644
+index 000000000000..926516835023
+--- /dev/null
++++ b/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
+@@ -0,0 +1,768 @@
++/*
++ * linux/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
++ *
++ * Copyright © 2016-2018, fuzhaoke
++ *		Author: fuzhaoke <fuzhaoke@allwinnertech.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ */
++#include <linux/kernel.h>
++#include <linux/ctype.h>
++#include <linux/printk.h>
++#include <linux/io.h>
++#include "sunxi-gmac.h"
++
++/******************************************************************************
++ *	sun8iw6 operations
++ *****************************************************************************/
++#define GETH_BASIC_CTL0		0x00
++#define GETH_BASIC_CTL1		0x04
++#define GETH_INT_STA		0x08
++#define GETH_INT_EN		0x0C
++#define GETH_TX_CTL0		0x10
++#define GETH_TX_CTL1		0x14
++#define GETH_TX_FLOW_CTL	0x1C
++#define GETH_TX_DESC_LIST	0x20
++#define GETH_RX_CTL0		0x24
++#define GETH_RX_CTL1		0x28
++#define GETH_RX_DESC_LIST	0x34
++#define GETH_RX_FRM_FLT		0x38
++#define GETH_RX_HASH0		0x40
++#define GETH_RX_HASH1		0x44
++#define GETH_MDIO_ADDR		0x48
++#define GETH_MDIO_DATA		0x4C
++#define GETH_ADDR_HI(reg)	(0x50 + ((reg) << 3))
++#define GETH_ADDR_LO(reg)	(0x54 + ((reg) << 3))
++#define GETH_TX_DMA_STA		0xB0
++#define GETH_TX_CUR_DESC	0xB4
++#define GETH_TX_CUR_BUF		0xB8
++#define GETH_RX_DMA_STA		0xC0
++#define GETH_RX_CUR_DESC	0xC4
++#define GETH_RX_CUR_BUF		0xC8
++#define GETH_RGMII_STA		0xD0
++
++#define RGMII_IRQ		0x00000001
++
++#define	CTL0_LM			0x02
++#define CTL0_DM			0x01
++#define CTL0_SPEED		0x04
++
++#define BURST_LEN		0x3F000000
++#define RX_TX_PRI		0x02
++#define SOFT_RST		0x01
++
++#define TX_FLUSH		0x01
++#define TX_MD			0x02
++#define TX_NEXT_FRM		0x04
++#define TX_TH			0x0700
++
++#define RX_FLUSH		0x01
++#define RX_MD			0x02
++#define RX_RUNT_FRM		0x04
++#define RX_TH			0x0030
++
++#define TX_INT			0x00001
++#define TX_STOP_INT		0x00002
++#define TX_UA_INT		0x00004
++#define TX_TOUT_INT		0x00008
++#define TX_UNF_INT		0x00010
++#define TX_EARLY_INT		0x00020
++#define RX_INT			0x00100
++#define RX_UA_INT		0x00200
++#define RX_STOP_INT		0x00400
++#define RX_TOUT_INT		0x00800
++#define RX_OVF_INT		0x01000
++#define RX_EARLY_INT		0x02000
++#define LINK_STA_INT		0x10000
++
++#define DISCARD_FRAME	-1
++#define GOOD_FRAME	0
++#define CSUM_NONE	2
++#define LLC_SNAP	4
++
++#define SF_DMA_MODE		1
++
++/* Flow Control defines */
++#define FLOW_OFF	0
++#define FLOW_RX		1
++#define FLOW_TX		2
++#define FLOW_AUTO	(FLOW_TX | FLOW_RX)
++
++#define HASH_TABLE_SIZE 64
++#define PAUSE_TIME 0x200
++#define GMAC_MAX_UNICAST_ADDRESSES	8
++
++/* PHY address */
++#define PHY_ADDR		0x01
++#define PHY_DM			0x0010
++#define PHY_AUTO_NEG		0x0020
++#define PHY_POWERDOWN		0x0080
++#define PHY_NEG_EN		0x1000
++
++#define MII_BUSY		0x00000001
++#define MII_WRITE		0x00000002
++#define MII_PHY_MASK		0x0000FFC0
++#define MII_CR_MASK		0x0000001C
++#define MII_CLK			0x00000008
++/* bits 4 3 2 | AHB1 Clock	| MDC Clock
++ * -------------------------------------------------------
++ *      0 0 0 | 60 ~ 100 MHz	| div-42
++ *      0 0 1 | 100 ~ 150 MHz	| div-62
++ *      0 1 0 | 20 ~ 35 MHz	| div-16
++ *      0 1 1 | 35 ~ 60 MHz	| div-26
++ *      1 0 0 | 150 ~ 250 MHz	| div-102
++ *      1 0 1 | 250 ~ 300 MHz	| div-124
++ *      1 1 x | Reserved	|
++ */
++
++enum csum_insertion {
++	cic_dis		= 0, /* Checksum Insertion Control */
++	cic_ip		= 1, /* Only IP header */
++	cic_no_pse	= 2, /* IP header but not pseudoheader */
++	cic_full	= 3, /* IP header and pseudoheader */
++};
++
++struct gethdev {
++	void *iobase;
++	unsigned int ver;
++	unsigned int mdc_div;
++};
++
++static struct gethdev hwdev;
++
++/***************************************************************************
++ * External interface
++ **************************************************************************/
++/* Set a ring desc buffer */
++void desc_init_chain(struct dma_desc *desc, unsigned long addr, unsigned int size)
++{
++	/* In chained mode the desc3 points to the next element in the ring.
++	 * The latest element has to point to the head.
++	 */
++	int i;
++	struct dma_desc *p = desc;
++	unsigned long dma_phy = addr;
++
++	for (i = 0; i < (size - 1); i++) {
++		dma_phy += sizeof(struct dma_desc);
++		p->desc3 = (unsigned int)dma_phy;
++		/* Chain mode */
++		p->desc1.all |= (1 << 24);
++		p++;
++	}
++	p->desc1.all |= (1 << 24);
++	p->desc3 = (unsigned int)addr;
++}
++
++int sunxi_mdio_read(void *iobase, int phyaddr, int phyreg)
++{
++	unsigned int value = 0;
++
++	/* Mask the MDC_DIV_RATIO */
++	value |= ((hwdev.mdc_div & 0x07) << 20);
++	value |= (((phyaddr << 12) & (0x0001F000)) |
++			((phyreg << 4) & (0x000007F0)) |
++			MII_BUSY);
++
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	writel(value, iobase + GETH_MDIO_ADDR);
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	return (int)readl(iobase + GETH_MDIO_DATA);
++}
++
++int sunxi_mdio_write(void *iobase, int phyaddr, int phyreg, unsigned short data)
++{
++	unsigned int value;
++
++	value = ((0x07 << 20) & readl(iobase + GETH_MDIO_ADDR)) |
++		 (hwdev.mdc_div << 20);
++	value |= (((phyaddr << 12) & (0x0001F000)) |
++		  ((phyreg << 4) & (0x000007F0))) |
++		  MII_WRITE | MII_BUSY;
++
++	/* Wait until any existing MII operation is complete */
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	/* Set the MII address register to write */
++	writel(data, iobase + GETH_MDIO_DATA);
++	writel(value, iobase + GETH_MDIO_ADDR);
++
++	/* Wait until any existing MII operation is complete */
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	return 0;
++}
++
++int sunxi_mdio_reset(void *iobase)
++{
++	writel((4 << 2), iobase + GETH_MDIO_ADDR);
++	return 0;
++}
++
++void sunxi_set_link_mode(void *iobase, int duplex, int speed)
++{
++	unsigned int ctrl = readl(iobase + GETH_BASIC_CTL0);
++
++	if (!duplex)
++		ctrl &= ~CTL0_DM;
++	else
++		ctrl |= CTL0_DM;
++
++	switch (speed) {
++	case 1000:
++		ctrl &= ~0x0C;
++		break;
++	case 100:
++	case 10:
++	default:
++		ctrl |= 0x08;
++		if (speed == 100)
++			ctrl |= 0x04;
++		else
++			ctrl &= ~0x04;
++		break;
++	}
++
++	writel(ctrl, iobase + GETH_BASIC_CTL0);
++}
++
++void sunxi_mac_loopback(void *iobase, int enable)
++{
++	int reg;
++
++	reg = readl(iobase + GETH_BASIC_CTL0);
++	if (enable)
++		reg |= 0x02;
++	else
++		reg &= ~0x02;
++	writel(reg, iobase + GETH_BASIC_CTL0);
++}
++
++void sunxi_flow_ctrl(void *iobase, int duplex, int fc, int pause)
++{
++	unsigned int flow = 0;
++
++	if (fc & FLOW_RX) {
++		flow = readl(iobase + GETH_RX_CTL0);
++		flow |= 0x10000;
++		writel(flow, iobase + GETH_RX_CTL0);
++	}
++
++	if (fc & FLOW_TX) {
++		flow = readl(iobase + GETH_TX_FLOW_CTL);
++		flow |= 0x00001;
++		writel(flow, iobase + GETH_TX_FLOW_CTL);
++	}
++
++	if (duplex) {
++		flow = readl(iobase + GETH_TX_FLOW_CTL);
++		flow |= (pause << 4);
++		writel(flow, iobase + GETH_TX_FLOW_CTL);
++	}
++}
++
++int sunxi_int_status(void *iobase, struct geth_extra_stats *x)
++{
++	int ret = 0;
++	/* read the status register (CSR5) */
++	unsigned int intr_status;
++
++	intr_status = readl(iobase + GETH_RGMII_STA);
++	if (intr_status & RGMII_IRQ)
++		readl(iobase + GETH_RGMII_STA);
++
++	intr_status = readl(iobase + GETH_INT_STA);
++
++	/* ABNORMAL interrupts */
++	if (intr_status & TX_UNF_INT) {
++		ret = tx_hard_error_bump_tc;
++		x->tx_undeflow_irq++;
++	}
++	if (intr_status & TX_TOUT_INT) {
++		x->tx_jabber_irq++;
++	}
++	if (intr_status & RX_OVF_INT) {
++		x->rx_overflow_irq++;
++	}
++	if (intr_status & RX_UA_INT) {
++		x->rx_buf_unav_irq++;
++	}
++	if (intr_status & RX_STOP_INT) {
++		x->rx_process_stopped_irq++;
++	}
++	if (intr_status & RX_TOUT_INT) {
++		x->rx_watchdog_irq++;
++	}
++	if (intr_status & TX_EARLY_INT) {
++		x->tx_early_irq++;
++	}
++	if (intr_status & TX_STOP_INT) {
++		x->tx_process_stopped_irq++;
++		ret = tx_hard_error;
++	}
++
++	/* TX/RX NORMAL interrupts */
++	if (intr_status & (TX_INT | RX_INT | RX_EARLY_INT | TX_UA_INT)) {
++		x->normal_irq_n++;
++		if (intr_status & (TX_INT | RX_INT))
++			ret = handle_tx_rx;
++	}
++	/* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
++	writel(intr_status & 0x3FFF, iobase + GETH_INT_STA);
++
++	return ret;
++}
++
++void sunxi_start_rx(void *iobase, unsigned long rxbase)
++{
++	unsigned int value;
++
++	/* Write the base address of Rx descriptor lists into registers */
++	writel(rxbase, iobase + GETH_RX_DESC_LIST);
++
++	value = readl(iobase + GETH_RX_CTL1);
++	value |= 0x40000000;
++	writel(value, iobase + GETH_RX_CTL1);
++}
++
++void sunxi_stop_rx(void *iobase)
++{
++	unsigned int value;
++
++	value = readl(iobase + GETH_RX_CTL1);
++	value &= ~0x40000000;
++	writel(value, iobase + GETH_RX_CTL1);
++}
++
++void sunxi_start_tx(void *iobase, unsigned long txbase)
++{
++	unsigned int value;
++
++	/* Write the base address of Tx descriptor lists into registers */
++	writel(txbase, iobase + GETH_TX_DESC_LIST);
++
++	value = readl(iobase + GETH_TX_CTL1);
++	value |= 0x40000000;
++	writel(value, iobase + GETH_TX_CTL1);
++}
++
++void sunxi_stop_tx(void *iobase)
++{
++	unsigned int value = readl(iobase + GETH_TX_CTL1);
++
++	value &= ~0x40000000;
++	writel(value, iobase + GETH_TX_CTL1);
++}
++
++static int sunxi_dma_init(void *iobase)
++{
++	unsigned int value;
++
++	/* Burst should be 8 */
++	value = (8 << 24);
++
++#ifdef CONFIG_GMAC_DA
++	value |= RX_TX_PRI;	/* Rx has priority over tx */
++#endif
++	writel(value, iobase + GETH_BASIC_CTL1);
++
++	/* Mask interrupts by writing to CSR7 */
++	writel(RX_INT | TX_INT | TX_UNF_INT, iobase + GETH_INT_EN);
++
++	return 0;
++}
++
++int sunxi_mac_init(void *iobase, int txmode, int rxmode)
++{
++	unsigned int value;
++
++	sunxi_dma_init(iobase);
++
++	/* Initialize the core component */
++	value = readl(iobase + GETH_TX_CTL0);
++	value |= (1 << 30);	/* Jabber Disable */
++	writel(value, iobase + GETH_TX_CTL0);
++
++	value = readl(iobase + GETH_RX_CTL0);
++	value |= (1 << 27);	/* Enable CRC & IPv4 Header Checksum */
++	value |= (1 << 28);	/* Automatic Pad/CRC Stripping */
++	value |= (1 << 29);	/* Jumbo Frame Enable */
++	writel(value, iobase + GETH_RX_CTL0);
++
++	writel((hwdev.mdc_div << 20), iobase + GETH_MDIO_ADDR); /* MDC_DIV_RATIO */
++
++	/* Set the Rx&Tx mode */
++	value = readl(iobase + GETH_TX_CTL1);
++	if (txmode == SF_DMA_MODE) {
++		/* Transmit COE type 2 cannot be done in cut-through mode. */
++		value |= TX_MD;
++		/* Operating on second frame increase the performance
++		 * especially when transmit store-and-forward is used.
++		 */
++		value |= TX_NEXT_FRM;
++	} else {
++		value &= ~TX_MD;
++		value &= ~TX_TH;
++		/* Set the transmit threshold */
++		if (txmode <= 64)
++			value |= 0x00000000;
++		else if (txmode <= 128)
++			value |= 0x00000100;
++		else if (txmode <= 192)
++			value |= 0x00000200;
++		else
++			value |= 0x00000300;
++	}
++	writel(value, iobase + GETH_TX_CTL1);
++
++	value = readl(iobase + GETH_RX_CTL1);
++	if (rxmode == SF_DMA_MODE) {
++		value |= RX_MD;
++	} else {
++		value &= ~RX_MD;
++		value &= ~RX_TH;
++		if (rxmode <= 32)
++			value |= 0x10;
++		else if (rxmode <= 64)
++			value |= 0x00;
++		else if (rxmode <= 96)
++			value |= 0x20;
++		else
++			value |= 0x30;
++	}
++	writel(value, iobase + GETH_RX_CTL1);
++
++	return 0;
++}
++
++void sunxi_hash_filter(void *iobase, unsigned long low, unsigned long high)
++{
++	writel(high, iobase + GETH_RX_HASH0);
++	writel(low, iobase + GETH_RX_HASH1);
++}
++
++void sunxi_set_filter(void *iobase, unsigned long flags)
++{
++	int tmp_flags;
++
++	tmp_flags = readl(iobase + GETH_RX_FRM_FLT);
++
++	tmp_flags |= ((flags >> 31) |
++			((flags >> 9) & 0x00000002) |
++			((flags << 1) & 0x00000010) |
++			((flags >> 3) & 0x00000060) |
++			((flags << 7) & 0x00000300) |
++			((flags << 6) & 0x00003000) |
++			((flags << 12) & 0x00030000) |
++			(flags << 31));
++
++	writel(tmp_flags, iobase + GETH_RX_FRM_FLT);
++}
++
++void sunxi_set_umac(void *iobase, unsigned char *addr, int index)
++{
++	unsigned long data;
++
++	data = (addr[5] << 8) | addr[4];
++	writel(data, iobase + GETH_ADDR_HI(index));
++	data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
++	writel(data, iobase + GETH_ADDR_LO(index));
++}
++
++void sunxi_mac_enable(void *iobase)
++{
++	unsigned long value;
++
++	value = readl(iobase + GETH_TX_CTL0);
++	value |= (1 << 31);
++	writel(value, iobase + GETH_TX_CTL0);
++
++	value = readl(iobase + GETH_RX_CTL0);
++	value |= (1 << 31);
++	writel(value, iobase + GETH_RX_CTL0);
++}
++
++void sunxi_mac_disable(void *iobase)
++{
++	unsigned long value;
++
++	value = readl(iobase + GETH_TX_CTL0);
++	value &= ~(1 << 31);
++	writel(value, iobase + GETH_TX_CTL0);
++
++	value = readl(iobase + GETH_RX_CTL0);
++	value &= ~(1 << 31);
++	writel(value, iobase + GETH_RX_CTL0);
++}
++
++void sunxi_tx_poll(void *iobase)
++{
++	unsigned int value;
++
++	value = readl(iobase + GETH_TX_CTL1);
++	writel(value | 0x80000000, iobase + GETH_TX_CTL1);
++}
++
++void sunxi_rx_poll(void *iobase)
++{
++	unsigned int value;
++
++	value = readl(iobase + GETH_RX_CTL1);
++	writel(value | 0x80000000, iobase + GETH_RX_CTL1);
++}
++
++void sunxi_int_enable(void *iobase)
++{
++	writel(RX_INT | TX_INT | TX_UNF_INT, iobase + GETH_INT_EN);
++}
++
++void sunxi_int_disable(void *iobase)
++{
++	writel(0, iobase + GETH_INT_EN);
++}
++
++void desc_buf_set(struct dma_desc *desc, unsigned long paddr, int size)
++{
++	desc->desc1.all &= (~((1 << 11) - 1));
++	desc->desc1.all |= (size & ((1 << 11) - 1));
++	desc->desc2 = paddr;
++}
++
++void desc_set_own(struct dma_desc *desc)
++{
++	desc->desc0.all |= 0x80000000;
++}
++
++void desc_tx_close(struct dma_desc *first, struct dma_desc *end, int csum_insert)
++{
++	struct dma_desc *desc = first;
++
++	first->desc1.tx.first_sg = 1;
++	end->desc1.tx.last_seg = 1;
++	end->desc1.tx.interrupt = 1;
++
++	if (csum_insert)
++		do {
++			desc->desc1.tx.cic = 3;
++			desc++;
++		} while (desc <= end);
++}
++
++void desc_init(struct dma_desc *desc)
++{
++	desc->desc1.all = 0;
++	desc->desc2  = 0;
++
++	desc->desc1.all |= (1 << 24);
++}
++
++int desc_get_tx_status(struct dma_desc *desc, struct geth_extra_stats *x)
++{
++	int ret = 0;
++
++	if (desc->desc0.tx.under_err) {
++		x->tx_underflow++;
++		ret = -1;
++	}
++	if (desc->desc0.tx.no_carr) {
++		x->tx_carrier++;
++		ret = -1;
++	}
++	if (desc->desc0.tx.loss_carr) {
++		x->tx_losscarrier++;
++		ret = -1;
++	}
++
++#if 0
++	if ((desc->desc0.tx.ex_deferral) ||
++			(desc->desc0.tx.ex_coll) ||
++			(desc->desc0.tx.late_coll))
++		stats->collisions += desc->desc0.tx.coll_cnt;
++#endif
++
++	if (desc->desc0.tx.deferred)
++		x->tx_deferred++;
++
++	return ret;
++}
++
++int desc_buf_get_len(struct dma_desc *desc)
++{
++	return (desc->desc1.all & ((1 << 11) - 1));
++}
++
++int desc_buf_get_addr(struct dma_desc *desc)
++{
++	return desc->desc2;
++}
++
++int desc_rx_frame_len(struct dma_desc *desc)
++{
++	return desc->desc0.rx.frm_len;
++}
++
++int desc_get_rx_status(struct dma_desc *desc, struct geth_extra_stats *x)
++{
++	int ret = good_frame;
++
++	if (desc->desc0.rx.last_desc == 0) {
++		return discard_frame;
++	}
++
++	if (desc->desc0.rx.err_sum) {
++		if (desc->desc0.rx.desc_err)
++			x->rx_desc++;
++
++		if (desc->desc0.rx.sou_filter)
++			x->sa_filter_fail++;
++
++		if (desc->desc0.rx.over_err)
++			x->overflow_error++;
++
++		if (desc->desc0.rx.ipch_err)
++			x->ipc_csum_error++;
++
++		if (desc->desc0.rx.late_coll)
++			x->rx_collision++;
++
++		if (desc->desc0.rx.crc_err)
++			x->rx_crc++;
++
++		ret = discard_frame;
++	}
++
++	if (desc->desc0.rx.len_err) {
++		ret = discard_frame;
++	}
++	if (desc->desc0.rx.mii_err) {
++		ret = discard_frame;
++	}
++
++	return ret;
++}
++
++int desc_get_own(struct dma_desc *desc)
++{
++	return desc->desc0.all & 0x80000000;
++}
++
++int desc_get_tx_ls(struct dma_desc *desc)
++{
++	return desc->desc1.tx.last_seg;
++}
++
++int sunxi_geth_register(void *iobase, int version, unsigned int div)
++{
++	hwdev.ver = version;
++	hwdev.iobase = iobase;
++	hwdev.mdc_div = div;
++
++	return 0;
++}
++
++int sunxi_mac_reset(void *iobase, void (*delay)(int), int n)
++{
++	unsigned int value;
++
++	/* DMA SW reset */
++	value = readl(iobase + GETH_BASIC_CTL1);
++	value |= SOFT_RST;
++	writel(value, iobase + GETH_BASIC_CTL1);
++
++	delay(n);
++
++	return !!(readl(iobase + GETH_BASIC_CTL1) & SOFT_RST);
++}
++
++/**
++ * sunxi_parse_read_str - parse the input string for write attri.
++ * @str: string to be parsed, eg: "0x00 0x01".
++ * @addr: store the reg address. eg: 0x00.
++ * @reg: store the expect value. eg: 0x01.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int sunxi_parse_read_str(char *str, u16 *addr, u16 *reg)
++{
++	char *ptr = str;
++	char *tstr = NULL;
++	int ret;
++
++	/*
++	 * Skip the leading whitespace, find the true split symbol.
++	 * And it must be 'address value'.
++	 */
++	tstr = strim(str);
++	ptr = strchr(tstr, ' ');
++	if (!ptr)
++		return -EINVAL;
++
++	/*
++	 * Replaced split symbol with a %NUL-terminator temporary.
++	 * Will be fixed at end.
++	 */
++	*ptr = '\0';
++	ret = kstrtos16(tstr, 16, addr);
++	if (ret)
++		goto out;
++
++	ret = kstrtos16(skip_spaces(ptr + 1), 16, reg);
++
++out:
++	return ret;
++}
++
++/**
++ * sunxi_parse_write_str - parse the input string for compare attri.
++ * @str: string to be parsed, eg: "0x00 0x11 0x11".
++ * @addr: store the address. eg: 0x00.
++ * @reg: store the reg. eg: 0x11.
++ * @val: store the value. eg: 0x11.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int sunxi_parse_write_str(char *str, u16 *addr,
++			  u16 *reg, u16 *val)
++{
++	u16 result_addr[3] = { 0 };
++	char *ptr = str;
++	char *ptr2 = NULL;
++	int i, ret = 0;
++
++	for (i = 0; i < ARRAY_SIZE(result_addr); i++) {
++		ptr = skip_spaces(ptr);
++		ptr2 = strchr(ptr, ' ');
++		if (ptr2)
++			*ptr2 = '\0';
++
++		ret = kstrtou16(ptr, 16, &result_addr[i]);
++		if (!ptr2)
++			break;
++
++		*ptr2 = ' ';
++
++		if (ret)
++			break;
++
++		ptr = ptr2 + 1;
++	}
++
++	*addr = result_addr[0];
++	*reg = result_addr[1];
++	*val = result_addr[2];
++
++	return ret;
++}
++MODULE_LICENSE("Dual BSD/GPL");
+diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
+index ddee1d6b5a2d..8cefee900679 100644
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -83,6 +83,14 @@ config AC200_PHY
+ 	help
+ 	  Fast ethernet PHY as found in X-Powers AC200 multi-function device.
+ 
++config AC200_PHY_SUNXI
++	tristate "AC200 EPHY(Sunxi)"
++	depends on NVMEM
++	depends on OF
++	depends on MFD_AC200_SUNXI
++	help
++	  Fast ethernet PHY as found in X-Powers AC200(Sunxi) multi-function device.
++
+ config AMD_PHY
+ 	tristate "AMD and Altima PHYs"
+ 	help
+diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
+index 8624cedf2721..07093e0f0841 100644
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -33,6 +33,7 @@ sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
+ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
+ obj-$(CONFIG_AC200_PHY)		+= ac200-phy.o
++obj-$(CONFIG_AC200_PHY_SUNXI)		+= sunxi-ephy.o
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+diff --git a/drivers/net/phy/sunxi-ephy.c b/drivers/net/phy/sunxi-ephy.c
+new file mode 100644
+index 000000000000..92f5ba101ced
+--- /dev/null
++++ b/drivers/net/phy/sunxi-ephy.c
+@@ -0,0 +1,518 @@
++/*
++ * Copyright © 2015-2016, Shuge
++ *		Author: Sugar <shugeLinux@gmail.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/errno.h>
++#include <linux/unistd.h>
++#include <linux/interrupt.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/spinlock.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/mii.h>
++#include <linux/ethtool.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <linux/mfd/ac200.h>
++
++#define EPHY_AC200 1
++#define EPHY_AC300 2
++
++#define WAIT_MAX_COUNT 200
++
++struct ephy_res {
++	struct phy_device *ac300;
++	struct ac200_dev *ac200;
++	atomic_t ephy_en;
++};
++
++static struct ephy_res ac200_ephy;
++static struct ephy_res ac300_ephy;
++u8 ephy_type;
++
++static int ac200_reg_read(struct ac200_dev *ac200, unsigned short reg)
++{
++	unsigned int val;
++	int ret;
++
++	ret = regmap_read(ac200->regmap, reg, &val);
++
++	if (ret < 0)
++		return ret;
++	else
++		return val;
++}
++
++static int ac200_reg_write(struct ac200_dev *ac200, unsigned short reg, unsigned short val)
++{
++	return regmap_write(ac200->regmap, reg, val);
++}
++
++int ephy_is_enable(void)
++{
++	if (ephy_type == EPHY_AC200)
++		return atomic_read(&ac200_ephy.ephy_en);
++	else if (ephy_type == EPHY_AC300)
++		return atomic_read(&ac300_ephy.ephy_en);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ephy_is_enable);
++
++static void disable_intelligent_ieee(struct phy_device *phydev)
++{
++	unsigned int value;
++
++	phy_write(phydev, 0x1f, 0x0100); /* switch to page 1 */
++	value = phy_read(phydev, 0x17);  /* read address 0 0x17 register */
++	value &= ~(1 << 3);			  /* reg 0x17 bit 3, set 0 to disable IEEE */
++	phy_write(phydev, 0x17, value);
++	phy_write(phydev, 0x1f, 0x0000); /* switch to page 0 */
++}
++
++static void disable_802_3az_ieee(struct phy_device *phydev)
++{
++	unsigned int value;
++
++	phy_write(phydev, 0xd, 0x7);
++	phy_write(phydev, 0xe, 0x3c);
++	phy_write(phydev, 0xd, 0x1 << 14 | 0x7);
++	value = phy_read(phydev, 0xe);
++	value &= ~(0x1 << 1);
++	phy_write(phydev, 0xd, 0x7);
++	phy_write(phydev, 0xe, 0x3c);
++	phy_write(phydev, 0xd, 0x1 << 14 | 0x7);
++	phy_write(phydev, 0xe, value);
++
++	phy_write(phydev, 0x1f, 0x0200); /* switch to page 2 */
++	phy_write(phydev, 0x18, 0x0000);
++}
++
++static void ephy_config_default(struct phy_device *phydev)
++{
++	phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824); /* Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200); /* Switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600); /* Switch to Page 6 */
++	phy_write(phydev, 0x14, 0x708b); /* PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xF000); /* PHYAFE RX optimization */
++	phy_write(phydev, 0x15, 0x1530);
++
++	phy_write(phydev, 0x1f, 0x0800); /* Switch to Page 8 */
++	phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */
++}
++
++static void __maybe_unused ephy_config_fixed(struct phy_device *phydev)
++{
++	phy_write(phydev, 0x1f, 0x0100); /*switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824); /*Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200); /*switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000); /*PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600); /*switch to Page 6 */
++	phy_write(phydev, 0x14, 0x7809); /*PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xf000); /*PHYAFE RX optimization */
++	phy_write(phydev, 0x10, 0x5523);
++	phy_write(phydev, 0x15, 0x3533);
++
++	phy_write(phydev, 0x1f, 0x0800); /*switch to Page 8 */
++	phy_write(phydev, 0x1d, 0x0844); /*disable auto offset */
++	phy_write(phydev, 0x18, 0x00bc); /*PHYAFE TRX optimization */
++}
++
++static void __maybe_unused ephy_config_cali(struct phy_device *phydev, u16 ephy_cali)
++{
++	int value;
++	value = phy_read(phydev, 0x06);
++	value &= ~(0x0F << 12);
++	value |= (0x0F & (0x03 + ephy_cali)) << 12;
++	phy_write(phydev, 0x06, value);
++
++	return;
++}
++
++int ephy_config_init(struct phy_device *phydev)
++{
++	int value;
++#if 1 //defined(CONFIG_ARCH_SUN50IW9)
++	if (ephy_type == EPHY_AC300) {
++		int ret;
++		u16 ephy_cali = 0;
++		ephy_cali = sun50i_ephy_calibrate_value();
++		if (ret) {
++			pr_err("ephy cali efuse read fail!\n");
++			return -1;
++		}
++		ephy_config_cali(ac300_ephy.ac300, ephy_cali);
++		/*
++		* BIT9: the flag of calibration value
++		* 0: Normal
++		* 1: Low level of calibration value
++		*/
++		if (ephy_cali & BIT(9)) {
++			pr_debug("ac300:ephy cali efuse read: fixed!\n");
++			ephy_config_fixed(phydev);
++		} else {
++			pr_debug("ac300:ephy cali efuse read: default!\n");
++			ephy_config_default(phydev);
++		}
++	} else {
++		pr_debug("ac200:ephy cali efuse read: default!\n");
++		ephy_config_default(phydev);
++	}
++#else
++	ephy_config_default(phydev);
++#endif
++
++#if 0
++	/* Disable Auto Power Saving mode */
++	phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
++	value = phy_read(phydev, 0x17);
++	value &= ~BIT(13);
++	phy_write(phydev, 0x17, value);
++#endif
++	disable_intelligent_ieee(phydev); /* Disable Intelligent IEEE */
++	disable_802_3az_ieee(phydev);  /* Disable 802.3az IEEE */
++	phy_write(phydev, 0x1f, 0x0000); /* Switch to Page 0 */
++
++#if 1 // def CONFIG_MFD_ACX00
++	if (ephy_type == EPHY_AC200) {
++		value = ac200_reg_read(ac200_ephy.ac200, AC200_EPHY_CTL);
++		if (phydev->interface == PHY_INTERFACE_MODE_RMII)
++			value |= (1 << 11);
++		else
++			value &= (~(1 << 11));
++		ac200_reg_write(ac200_ephy.ac200, AC200_EPHY_CTL, value | (1 << 11));
++	} else
++#endif
++	if (ephy_type == EPHY_AC300) {
++		value = phy_read(ac300_ephy.ac300, 0x06);
++		if (phydev->interface == PHY_INTERFACE_MODE_RMII)
++			value |= (1 << 11);
++		else
++			value &= (~(1 << 11));
++		phy_write(ac300_ephy.ac300, 0x06, value | (1 << 1)); /*LED_POL 1:Low active*/
++	}
++
++#if defined(CONFIG_ARCH_SUN50IW6)
++	value = phy_read(phydev, 0x13);
++	value |= 1 << 12;
++	phy_write(phydev, 0x13, value);
++#endif
++
++	return 0;
++}
++EXPORT_SYMBOL(ephy_config_init);
++
++static int ephy_probe(struct phy_device *phydev)
++{
++	return 0;
++}
++
++#if 0
++static int ephy_ack_interrupt(struct phy_device *phydev)
++{
++	int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
++
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++#endif
++
++
++static struct phy_driver sunxi_phy_driver = {
++	.phy_id = 0x00441400,
++	.name = "ephy",
++	.phy_id_mask = 0x0ffffff0,
++	.features = PHY_BASIC_FEATURES, //| SUPPORTED_Pause |SUPPORTED_Asym_Pause,
++#if 0
++	.flags = PHY_HAS_INTERRUPT,
++	.ack_interrupt = ephy_ack_interrupt,
++#endif
++	.config_init = &ephy_config_init,
++	.config_aneg = &genphy_config_aneg,
++	.read_status = &genphy_read_status,
++	.suspend = genphy_suspend,
++	.resume = genphy_resume,
++	.probe = ephy_probe,
++};
++
++static void ac300_ephy_enable(struct ephy_res *priv)
++{
++	phy_write(priv->ac300, 0x00, 0x1f83); /* release reset */
++
++	phy_write(priv->ac300, 0x00, 0x1fb7); /* clk gating (24MHz clock)*/
++
++	//phy_write(priv->ac300, 0x05, 0xa81f);
++	phy_write(priv->ac300, 0x05, 0xa819);
++
++	phy_write(priv->ac300, 0x06, 0x00);
++
++	msleep(1000); /* FIXME: fix some board compatible issues. */
++
++	atomic_set(&ac300_ephy.ephy_en, 1);
++}
++
++static void ac300_ephy_disable(struct ephy_res *priv)
++{
++	phy_write(priv->ac300, 0x00, 0x1f40);
++	phy_write(priv->ac300, 0x05, 0xa800);
++
++	phy_write(priv->ac300, 0x06, 0x01);
++
++	atomic_set(&ac300_ephy.ephy_en, 0);
++}
++
++static int ac300_ephy_probe(struct phy_device *phydev)
++{
++	ac300_ephy.ac300 = phydev;
++
++	atomic_set(&ac300_ephy.ephy_en, 0);
++	ac300_ephy_enable(&ac300_ephy);
++
++	ephy_type = EPHY_AC300;
++
++	return 0;
++}
++
++static void ac300_ephy_shutdown(struct phy_device *phydev)
++{
++	ac300_ephy.ac300 = phydev;
++
++	phy_write(ac300_ephy.ac300, 0x00, 0x1f40);
++	phy_write(ac300_ephy.ac300, 0x05, 0xa800);
++	phy_write(ac300_ephy.ac300, 0x06, 0x01);
++}
++
++int gmac_ephy_shutdown(void)
++{
++	if (ephy_type == EPHY_AC300)
++		ac300_ephy_disable(&ac300_ephy);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(gmac_ephy_shutdown);
++
++static int ac300_ephy_suspend(struct phy_device *phydev)
++{
++	ac300_ephy_disable(&ac300_ephy);
++
++	return 0;
++}
++
++static int ac300_ephy_resume(struct phy_device *phydev)
++{
++	ac300_ephy_enable(&ac300_ephy);
++
++	return 0;
++}
++
++static struct phy_driver ac300_ephy_driver = {
++	.phy_id = 0xc0000000,
++	.name = "ac300",
++	.phy_id_mask = 0xffffffff,
++	.suspend = ac300_ephy_suspend,
++	.resume = ac300_ephy_resume,
++	.probe = ac300_ephy_probe,
++	// .shutdown = ac300_ephy_shutdown,
++};
++
++
++static void ac200_ephy_enable(struct ephy_res *priv)
++{
++#if 1 //ifdef CONFIG_MFD_ACX00
++	int value;
++	unsigned char i = 0;
++#if 1 // defined(CONFIG_ARCH_SUN50IW6) || defined(CONFIG_ARCH_SUN50IW9)
++	u16 ephy_cali = 0;
++#endif
++
++	if (!ac200_enable()) {
++		for (i = 0; i < WAIT_MAX_COUNT; i++) {
++			msleep(10);
++			if (ac200_enable())
++			break;
++		}
++		if (i == WAIT_MAX_COUNT) {
++			pr_err("acx00 is no enable, and ac200_ephy_enable is fail\n");
++			return;
++		}
++	}
++
++	value = ac200_reg_read(priv->ac200, AC200_SYS_EPHY_CTL0);
++	value |= 0x03;
++	ac200_reg_write(priv->ac200, AC200_SYS_EPHY_CTL0, value);
++	value = ac200_reg_read(priv->ac200, AC200_SYS_EPHY_CTL1);
++
++	value |= 0x0f;
++
++	ac200_reg_write(priv->ac200, AC200_SYS_EPHY_CTL1, value);
++	ac200_reg_write(priv->ac200, AC200_EPHY_CTL, 0x06);
++
++	/*for ephy */
++	value = ac200_reg_read(priv->ac200, AC200_EPHY_CTL);
++	value &= ~(0xf << 12);
++
++#if 1 // defined(CONFIG_ARCH_SUN50IW6) || defined(CONFIG_ARCH_SUN50IW9)
++
++	ephy_cali = sun50i_ephy_calibrate_value();
++	value |= (0x0F & (0x03 + ephy_cali)) << 12;
++#else
++	value |= (0x0F & (0x03 + ac200_reg_read(priv->ac200, AC200_SID))) << 12;
++#endif
++
++	ac200_reg_write(priv->ac200, AC200_EPHY_CTL, value);
++
++	atomic_set(&ac200_ephy.ephy_en, 1);
++#endif
++}
++
++static void ac200_ephy_disable(struct ephy_res *priv)
++{
++	int value;
++
++	/* reset ephy */
++	value = ac200_reg_read(priv->ac200, AC200_SYS_EPHY_CTL0);
++	value &= ~0x01;
++	ac200_reg_write(priv->ac200, AC200_SYS_EPHY_CTL0, value);
++
++	/* shutdown ephy */
++	value = ac200_reg_read(priv->ac200, AC200_EPHY_CTL);
++	value |= 0x01;
++	ac200_reg_write(priv->ac200, AC200_EPHY_CTL, value);
++
++	atomic_set(&priv->ephy_en, 0);
++}
++
++static const struct platform_device_id ac200_ephy_id[] = {
++	{ "ac200-ephy", 0},
++	{ },
++};
++MODULE_DEVICE_TABLE(platform, ac200_ephy_id);
++
++static int ac200_ephy_probe(struct platform_device *pdev)
++{
++	struct ac200_dev *ax = dev_get_drvdata(pdev->dev.parent);
++
++	if (!ax)
++		return -ENODEV;
++
++	ac200_ephy.ac200 = ax;
++	ephy_type = EPHY_AC200;
++	platform_set_drvdata(pdev, &ac200_ephy);
++
++	atomic_set(&ac200_ephy.ephy_en, 0);
++	ac200_ephy_enable(&ac200_ephy);
++
++	return 0;
++}
++
++static int ac200_ephy_remove(struct platform_device *pdev)
++{
++	ac200_ephy_disable(&ac200_ephy);
++
++	return 0;
++}
++
++static int ac200_ephy_suspend(struct device *dev)
++{
++	ac200_ephy_disable(&ac200_ephy);
++
++	return 0;
++}
++
++static int ac200_ephy_resume(struct device *dev)
++{
++	ac200_ephy_enable(&ac200_ephy);
++
++	return 0;
++}
++
++/* Suspend hook structures */
++static const struct dev_pm_ops ac200_ephy_pm_ops = {
++	.suspend = ac200_ephy_suspend,
++	.resume = ac200_ephy_resume,
++};
++
++static struct platform_driver ac200_ephy_driver = {
++	.driver = {
++		.name = "ac200-ephy-sunxi",
++		.owner = THIS_MODULE,
++		.pm = &ac200_ephy_pm_ops,
++	},
++	.probe = ac200_ephy_probe,
++	.remove = ac200_ephy_remove,
++	.id_table = ac200_ephy_id,
++};
++
++static int ephy_init(void)
++{
++	int ret = 0;
++
++	ret = platform_driver_register(&ac200_ephy_driver);
++	if (ret)
++		return ret;
++
++	ret = phy_driver_register(&ac300_ephy_driver, THIS_MODULE);
++	if (ret)
++		goto ac300_ephy_error;
++
++	ret = phy_driver_register(&sunxi_phy_driver, THIS_MODULE);
++	if (ret)
++		goto ephy_driver_error;
++
++	return ret;
++
++ephy_driver_error:
++	phy_driver_unregister(&ac300_ephy_driver);
++
++ac300_ephy_error:
++	platform_driver_unregister(&ac200_ephy_driver);
++
++	return ret;
++}
++
++static void ephy_exit(void)
++{
++	phy_driver_unregister(&sunxi_phy_driver);
++	phy_driver_unregister(&ac300_ephy_driver);
++	platform_driver_unregister(&ac200_ephy_driver);
++}
++
++module_init(ephy_init);
++module_exit(ephy_exit);
++
++static struct mdio_device_id __maybe_unused ephy_tbl[] = {
++	{ 0x00441400, 0x0ffffff0 },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, ephy_tbl);
++
++MODULE_DESCRIPTION("Allwinner EPHY drivers");
++MODULE_AUTHOR("Sugar <shugeLinux@gmail.com>");
++MODULE_LICENSE("GPL");
+diff --git a/include/linux/mfd/ac200.h b/include/linux/mfd/ac200.h
+new file mode 100644
+index 000000000000..84d89cbfbd3d
+--- /dev/null
++++ b/include/linux/mfd/ac200.h
+@@ -0,0 +1,213 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * AC200 register list
++ *
++ * Copyright (C) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#ifndef __LINUX_MFD_AC200_H
++#define __LINUX_MFD_AC200_H
++
++#include <linux/regmap.h>
++#include <linux/clk.h>
++
++/* interface registers (can be accessed from any page) */
++#define AC200_TWI_CHANGE_TO_RSB		0x3E
++#define AC200_TWI_PAD_DELAY		0xC4
++#define AC200_TWI_REG_ADDR_H		0xFE
++
++/* General registers */
++#define AC200_SYS_VERSION		0x0000
++#define AC200_SYS_CONTROL		0x0002
++#define AC200_SYS_IRQ_ENABLE		0x0004
++#define AC200_SYS_IRQ_STATUS		0x0006
++#define AC200_SYS_CLK_CTL		0x0008
++#define AC200_SYS_DLDO_OSC_CTL		0x000A
++#define AC200_SYS_PLL_CTL0		0x000C
++#define AC200_SYS_PLL_CTL1		0x000E
++#define AC200_SYS_AUDIO_CTL0		0x0010
++#define AC200_SYS_AUDIO_CTL1		0x0012
++#define AC200_SYS_EPHY_CTL0		0x0014
++#define AC200_SYS_EPHY_CTL1		0x0016
++#define AC200_SYS_TVE_CTL0		0x0018
++#define AC200_SYS_TVE_CTL1		0x001A
++
++/* Audio Codec registers */
++#define AC200_AC_SYS_CLK_CTL		0x2000
++#define AC200_SYS_MOD_RST		0x2002
++#define AC200_SYS_SAMP_CTL		0x2004
++#define AC200_I2S_CTL			0x2100
++#define AC200_I2S_CLK			0x2102
++#define AC200_I2S_FMT0			0x2104
++#define AC200_I2S_FMT1			0x2108
++#define AC200_I2S_MIX_SRC		0x2114
++#define AC200_I2S_MIX_GAIN		0x2116
++#define AC200_I2S_DACDAT_DVC		0x2118
++#define AC200_I2S_ADCDAT_DVC		0x211A
++#define AC200_AC_DAC_DPC		0x2200
++#define AC200_AC_DAC_MIX_SRC		0x2202
++#define AC200_AC_DAC_MIX_GAIN		0x2204
++#define AC200_DACA_OMIXER_CTRL		0x2220
++#define AC200_OMIXER_SR			0x2222
++#define AC200_LINEOUT_CTRL		0x2224
++#define AC200_AC_ADC_DPC		0x2300
++#define AC200_MBIAS_CTRL		0x2310
++#define AC200_ADC_MIC_CTRL		0x2320
++#define AC200_ADCMIXER_SR		0x2322
++#define AC200_ANALOG_TUNING0		0x232A
++#define AC200_ANALOG_TUNING1		0x232C
++#define AC200_AC_AGC_SEL		0x2480
++#define AC200_ADC_DAPLCTRL		0x2500
++#define AC200_ADC_DAPRCTRL		0x2502
++#define AC200_ADC_DAPLSTA		0x2504
++#define AC200_ADC_DAPRSTA		0x2506
++#define AC200_ADC_DAPLTL		0x2508
++#define AC200_ADC_DAPRTL		0x250A
++#define AC200_ADC_DAPLHAC		0x250C
++#define AC200_ADC_DAPLLAC		0x250E
++#define AC200_ADC_DAPRHAC		0x2510
++#define AC200_ADC_DAPRLAC		0x2512
++#define AC200_ADC_DAPLDT		0x2514
++#define AC200_ADC_DAPLAT		0x2516
++#define AC200_ADC_DAPRDT		0x2518
++#define AC200_ADC_DAPRAT		0x251A
++#define AC200_ADC_DAPNTH		0x251C
++#define AC200_ADC_DAPLHNAC		0x251E
++#define AC200_ADC_DAPLLNAC		0x2520
++#define AC200_ADC_DAPRHNAC		0x2522
++#define AC200_ADC_DAPRLNAC		0x2524
++#define AC200_AC_DAPHHPFC		0x2526
++#define AC200_AC_DAPLHPFC		0x2528
++#define AC200_AC_DAPOPT			0x252A
++#define AC200_AC_DAC_DAPCTRL		0x3000
++#define AC200_AC_DRC_HHPFC		0x3002
++#define AC200_AC_DRC_LHPFC		0x3004
++#define AC200_AC_DRC_CTRL		0x3006
++#define AC200_AC_DRC_LPFHAT		0x3008
++#define AC200_AC_DRC_LPFLAT		0x300A
++#define AC200_AC_DRC_RPFHAT		0x300C
++#define AC200_AC_DRC_RPFLAT		0x300E
++#define AC200_AC_DRC_LPFHRT		0x3010
++#define AC200_AC_DRC_LPFLRT		0x3012
++#define AC200_AC_DRC_RPFHRT		0x3014
++#define AC200_AC_DRC_RPFLRT		0x3016
++#define AC200_AC_DRC_LRMSHAT		0x3018
++#define AC200_AC_DRC_LRMSLAT		0x301A
++#define AC200_AC_DRC_RRMSHAT		0x301C
++#define AC200_AC_DRC_RRMSLAT		0x301E
++#define AC200_AC_DRC_HCT		0x3020
++#define AC200_AC_DRC_LCT		0x3022
++#define AC200_AC_DRC_HKC		0x3024
++#define AC200_AC_DRC_LKC		0x3026
++#define AC200_AC_DRC_HOPC		0x3028
++#define AC200_AC_DRC_LOPC		0x302A
++#define AC200_AC_DRC_HLT		0x302C
++#define AC200_AC_DRC_LLT		0x302E
++#define AC200_AC_DRC_HKI		0x3030
++#define AC200_AC_DRC_LKI		0x3032
++#define AC200_AC_DRC_HOPL		0x3034
++#define AC200_AC_DRC_LOPL		0x3036
++#define AC200_AC_DRC_HET		0x3038
++#define AC200_AC_DRC_LET		0x303A
++#define AC200_AC_DRC_HKE		0x303C
++#define AC200_AC_DRC_LKE		0x303E
++#define AC200_AC_DRC_HOPE		0x3040
++#define AC200_AC_DRC_LOPE		0x3042
++#define AC200_AC_DRC_HKN		0x3044
++#define AC200_AC_DRC_LKN		0x3046
++#define AC200_AC_DRC_SFHAT		0x3048
++#define AC200_AC_DRC_SFLAT		0x304A
++#define AC200_AC_DRC_SFHRT		0x304C
++#define AC200_AC_DRC_SFLRT		0x304E
++#define AC200_AC_DRC_MXGHS		0x3050
++#define AC200_AC_DRC_MXGLS		0x3052
++#define AC200_AC_DRC_MNGHS		0x3054
++#define AC200_AC_DRC_MNGLS		0x3056
++#define AC200_AC_DRC_EPSHC		0x3058
++#define AC200_AC_DRC_EPSLC		0x305A
++#define AC200_AC_DRC_HPFHGAIN		0x305E
++#define AC200_AC_DRC_HPFLGAIN		0x3060
++#define AC200_AC_DRC_BISTCR		0x3100
++#define AC200_AC_DRC_BISTST		0x3102
++
++/* TVE registers */
++#define AC200_TVE_CTL0			0x4000
++#define AC200_TVE_CTL1			0x4002
++#define AC200_TVE_MOD0			0x4004
++#define AC200_TVE_MOD1			0x4006
++#define AC200_TVE_DAC_CFG0		0x4008
++#define AC200_TVE_DAC_CFG1		0x400A
++#define AC200_TVE_YC_DELAY		0x400C
++#define AC200_TVE_YC_FILTER		0x400E
++#define AC200_TVE_BURST_FRQ0		0x4010
++#define AC200_TVE_BURST_FRQ1		0x4012
++#define AC200_TVE_FRONT_PORCH		0x4014
++#define AC200_TVE_BACK_PORCH		0x4016
++#define AC200_TVE_TOTAL_LINE		0x401C
++#define AC200_TVE_FIRST_ACTIVE		0x401E
++#define AC200_TVE_BLACK_LEVEL		0x4020
++#define AC200_TVE_BLANK_LEVEL		0x4022
++#define AC200_TVE_PLUG_EN		0x4030
++#define AC200_TVE_PLUG_IRQ_EN		0x4032
++#define AC200_TVE_PLUG_IRQ_STA		0x4034
++#define AC200_TVE_PLUG_STA		0x4038
++#define AC200_TVE_PLUG_DEBOUNCE		0x4040
++#define AC200_TVE_DAC_TEST		0x4042
++#define AC200_TVE_PLUG_PULSE_LEVEL	0x40F4
++#define AC200_TVE_PLUG_PULSE_START	0x40F8
++#define AC200_TVE_PLUG_PULSE_PERIOD	0x40FA
++#define AC200_TVE_IF_CTL		0x5000
++#define AC200_TVE_IF_TIM0		0x5008
++#define AC200_TVE_IF_TIM1		0x500A
++#define AC200_TVE_IF_TIM2		0x500C
++#define AC200_TVE_IF_TIM3		0x500E
++#define AC200_TVE_IF_SYNC0		0x5010
++#define AC200_TVE_IF_SYNC1		0x5012
++#define AC200_TVE_IF_SYNC2		0x5014
++#define AC200_TVE_IF_TIM4		0x5016
++#define AC200_TVE_IF_STATUS		0x5018
++
++/* EPHY registers */
++#define AC200_EPHY_CTL			0x6000
++#define AC200_EPHY_BIST			0x6002
++
++/* eFuse registers (0x8000 - 0x9FFF, layout unknown) */
++
++/* RTC registers */
++#define AC200_LOSC_CTRL0		0xA000
++#define AC200_LOSC_CTRL1		0xA002
++#define AC200_LOSC_AUTO_SWT_STA		0xA004
++#define AC200_INTOSC_CLK_PRESCAL	0xA008
++#define AC200_RTC_YY_MM_DD0		0xA010
++#define AC200_RTC_YY_MM_DD1		0xA012
++#define AC200_RTC_HH_MM_SS0		0xA014
++#define AC200_RTC_HH_MM_SS1		0xA016
++#define AC200_ALARM0_CUR_VLU0		0xA024
++#define AC200_ALARM0_CUR_VLU1		0xA026
++#define AC200_ALARM0_ENABLE		0xA028
++#define AC200_ALARM0_IRQ_EN		0xA02C
++#define AC200_ALARM0_IRQ_STA		0xA030
++#define AC200_ALARM1_WK_HH_MM_SS0	0xA040
++#define AC200_ALARM1_WK_HH_MM_SS1	0xA042
++#define AC200_ALARM1_ENABLE		0xA044
++#define AC200_ALARM1_IRQ_EN		0xA048
++#define AC200_ALARM1_IRQ_STA		0xA04C
++#define AC200_ALARM_CONFIG		0xA050
++#define AC200_LOSC_OUT_GATING		0xA060
++#define AC200_GP_DATA(x)		(0xA100 + (x) * 2)
++#define AC200_RTC_DEB			0xA170
++#define AC200_GPL_HOLD_OUTPUT		0xA180
++#define AC200_VDD_RTC			0xA190
++#define AC200_IC_CHARA0			0xA1F0
++#define AC200_IC_CHARA1			0xA1F2
++
++struct ac200_dev {
++	struct clk			*clk;
++	struct regmap			*regmap;
++	struct regmap_irq_chip_data	*regmap_irqc;
++};
++
++extern int ac200_enable(void);
++extern uint16_t sun50i_ephy_calibrate_value(void);
++
++#endif /* __LINUX_MFD_AC200_H */
+diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
+index d0f66a5e1b2a..71349cac1a67 100644
+--- a/include/linux/of_gpio.h
++++ b/include/linux/of_gpio.h
+@@ -15,6 +15,21 @@
+ #include <linux/gpio.h>		/* FIXME: Shouldn't be here */
+ #include <linux/of.h>
+ 
++/*
++ * This is Linux-specific flags. By default controllers' and Linux' mapping
++ * match, but GPIO controllers are free to translate their own flags to
++ * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
++ */
++enum of_gpio_flags {
++	OF_GPIO_ACTIVE_LOW = 0x1,
++	OF_GPIO_SINGLE_ENDED = 0x2,
++	OF_GPIO_OPEN_DRAIN = 0x4,
++	OF_GPIO_TRANSITORY = 0x8,
++	OF_GPIO_PULL_UP = 0x10,
++	OF_GPIO_PULL_DOWN = 0x20,
++	OF_GPIO_PULL_DISABLE = 0x40,
++};
++
+ struct device_node;
+ 
+ #ifdef CONFIG_OF_GPIO
+@@ -22,6 +37,9 @@ struct device_node;
+ extern int of_get_named_gpio(const struct device_node *np,
+ 			     const char *list_name, int index);
+ 
++extern int of_get_named_gpio_flags(const struct device_node *np,
++		const char *list_name, int index, enum of_gpio_flags *flags);
++
+ #else /* CONFIG_OF_GPIO */
+ 
+ #include <linux/errno.h>
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch
new file mode 100644
index 000000000000..5bac82dc370e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Tue, 5 Sep 2023 11:16:07 +0000
+Subject: drivers: devfreq: sun8i-a33-mbus: disable autorefresh
+
+---
+ drivers/devfreq/sun8i-a33-mbus.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/devfreq/sun8i-a33-mbus.c b/drivers/devfreq/sun8i-a33-mbus.c
+index 13d32213139f..81832c3ffafa 100644
+--- a/drivers/devfreq/sun8i-a33-mbus.c
++++ b/drivers/devfreq/sun8i-a33-mbus.c
+@@ -202,8 +202,8 @@ static int sun8i_a33_mbus_set_dram_freq(struct sun8i_a33_mbus *priv,
+ 	writel_relaxed(vtfcr, priv->reg_dram + DRAM_VTFCR);
+ 
+ 	/* Enable automatic self-refresh at the lowest frequency only. */
+-	if (freq == priv->freq_table[0])
+-		pwrctl |= DRAM_PWRCTL_SELFREF_EN;
++	// if (freq == priv->freq_table[0])
++	//	pwrctl |= DRAM_PWRCTL_SELFREF_EN;
+ 	writel_relaxed(pwrctl, priv->reg_dram + DRAM_PWRCTL);
+ 
+ 	sun8i_a33_mbus_restart_pmu_counters(priv);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
new file mode 100644
index 000000000000..1931ff3ac3ff
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
@@ -0,0 +1,1317 @@
+From 0af09c99fc0c8ba11d323c42045c796fa88afe0d Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Wed, 1 May 2024 14:24:51 +0800
+Subject: drivers: pwm: Add pwm-sunxi-enhance driver for h616
+
+linux-orangepi commit:
+c68ef342eba3673c7f1f5aa1ab819b06da1f60c6
+---
+ drivers/pwm/Kconfig             |    9 +
+ drivers/pwm/Makefile            |    1 +
+ drivers/pwm/pwm-sunxi-enhance.c | 1194 +++++++++++++++++++++++++++++++
+ drivers/pwm/pwm-sunxi-enhance.h |   60 ++
+ 4 files changed, 1264 insertions(+)
+ create mode 100644 drivers/pwm/pwm-sunxi-enhance.c
+ create mode 100644 drivers/pwm/pwm-sunxi-enhance.h
+
+diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
+index 4b956d661755..ebc35b44e9f2 100644
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -625,6 +625,15 @@ config PWM_SUN4I
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called pwm-sun4i.
+ 
++config PWM_SUNXI_ENHANCE
++	tristate "Sunxi Enhance PWM support"
++	depends on PWM && ARCH_SUNXI
++	help
++	Enhance PWM framework driver for sunxi.
++
++	To compile this driver as a module, choose M here: the module
++	will be called pwm-sunxi.
++
+ config PWM_SUNPLUS
+ 	tristate "Sunplus PWM support"
+ 	depends on ARCH_SUNPLUS || COMPILE_TEST
+diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
+index c5ec9e168ee7..b39ae3ec8be9 100644
+--- a/drivers/pwm/Makefile
++++ b/drivers/pwm/Makefile
+@@ -58,6 +58,7 @@ obj-$(CONFIG_PWM_STM32)		+= pwm-stm32.o
+ obj-$(CONFIG_PWM_STM32_LP)	+= pwm-stm32-lp.o
+ obj-$(CONFIG_PWM_STMPE)		+= pwm-stmpe.o
+ obj-$(CONFIG_PWM_SUN4I)		+= pwm-sun4i.o
++obj-$(CONFIG_PWM_SUNXI_ENHANCE)		+= pwm-sunxi-enhance.o
+ obj-$(CONFIG_PWM_SUNPLUS)	+= pwm-sunplus.o
+ obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
+ obj-$(CONFIG_PWM_TIECAP)	+= pwm-tiecap.o
+diff --git a/drivers/pwm/pwm-sunxi-enhance.c b/drivers/pwm/pwm-sunxi-enhance.c
+new file mode 100644
+index 000000000000..68e22077ce34
+--- /dev/null
++++ b/drivers/pwm/pwm-sunxi-enhance.c
+@@ -0,0 +1,1194 @@
++/*
++ * Allwinnertech pulse-width-modulation controller driver
++ *
++ * Copyright (C) 2015 AllWinner
++ *
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#include <linux/types.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/cdev.h>
++#include <linux/pwm.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <linux/fs.h>
++#include <linux/device.h>
++#include <linux/gpio.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++#include <linux/of_iommu.h>
++#include <linux/of_device.h>
++#include <linux/of_platform.h>
++#include <linux/printk.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include "pwm-sunxi-enhance.h"
++
++#define PWM_NUM_MAX 4
++#define PWM_BIND_NUM 2
++#define PWM_PIN_STATE_ACTIVE "default"
++//#define PWM_PIN_STATE_SLEEP "sleep"
++
++#define SETMASK(width, shift) ((width ? ((-1U) >> (32 - width)) : 0) << (shift))
++#define CLRMASK(width, shift) (~(SETMASK(width, shift)))
++#define GET_BITS(shift, width, reg) \
++    (((reg)&SETMASK(width, shift)) >> (shift))
++#define SET_BITS(shift, width, reg, val) \
++    (((reg)&CLRMASK(width, shift)) | (val << (shift)))
++
++static int pwm_debug = 0;
++module_param(pwm_debug, int, 0644);
++MODULE_PARM_DESC(pwm_debug, "enable pwm debug");
++
++#define pwm_debug(fmt, ...) \
++    if (pwm_debug)          \
++    printk(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__)
++
++struct sunxi_pwm_config
++{
++    unsigned int dead_time;
++    unsigned int bind_pwm;
++
++    unsigned int clk_bypass_output;
++};
++
++struct sunxi_pwm_chip
++{
++    struct pwm_chip chip;
++    void __iomem *base;
++    struct sunxi_pwm_config *config;
++    struct clk *bus_clk;
++    struct clk *clk;
++    struct reset_control *pwm_rst_clk;
++};
++
++static inline struct sunxi_pwm_chip *to_sunxi_pwm_chip(struct pwm_chip *chip)
++{
++    return container_of(chip, struct sunxi_pwm_chip, chip);
++}
++
++static inline u32 sunxi_pwm_readl(struct pwm_chip *chip, u32 offset)
++{
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++    u32 value = 0;
++
++    value = readl(pc->base + offset);
++
++    return value;
++}
++
++static inline u32 sunxi_pwm_writel(struct pwm_chip *chip, u32 offset, u32 value)
++{
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    writel(value, pc->base + offset);
++
++    return 0;
++}
++
++static int sunxi_pwm_pin_set_state(struct device *dev, char *name)
++{
++    struct pinctrl *pctl;
++    struct pinctrl_state *state;
++    int ret = -1;
++
++    pctl = devm_pinctrl_get(dev);
++    if (IS_ERR(pctl))
++    {
++        dev_err(dev, "pinctrl_get failed!\n");
++        ret = PTR_ERR(pctl);
++        goto exit;
++    }
++
++    state = pinctrl_lookup_state(pctl, name);
++    if (IS_ERR(state))
++    {
++        dev_err(dev, "pinctrl_lookup_state(%s) failed!\n", name);
++        ret = PTR_ERR(state);
++        goto exit;
++    }
++
++    ret = pinctrl_select_state(pctl, state);
++    if (ret < 0)
++    {
++        dev_err(dev, "pinctrl_select_state(%s) failed!\n", name);
++        goto exit;
++    }
++    ret = 0;
++
++exit:
++    return ret;
++}
++
++static int sunxi_pwm_get_config(struct platform_device *pdev, struct sunxi_pwm_config *config)
++{
++    struct device_node *np = pdev->dev.of_node;
++    int ret = 0;
++
++    /* read register config */
++    ret = of_property_read_u32(np, "bind_pwm", &config->bind_pwm);
++    if (ret < 0)
++    {
++        /*if there is no bind pwm,set 255, dual pwm invalid!*/
++        config->bind_pwm = 255;
++        ret = 0;
++    }
++
++    ret = of_property_read_u32(np, "dead_time", &config->dead_time);
++    if (ret < 0)
++    {
++        /*if there is  bind pwm, but not set dead time,set bind pwm 255,dual pwm invalid!*/
++        config->bind_pwm = 255;
++        ret = 0;
++    }
++
++    ret = of_property_read_u32(np, "clk_bypass_output", &config->clk_bypass_output);
++    if (ret < 0)
++    {
++        /*if use pwm as the internal clock source!*/
++        config->clk_bypass_output = 0;
++        ret = 0;
++    }
++
++    of_node_put(np);
++
++    return ret;
++}
++
++static int sunxi_pwm_set_polarity_single(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity)
++{
++    u32 temp;
++    unsigned int reg_offset, reg_shift, reg_width;
++    u32 sel = 0;
++
++    sel = pwm->pwm - chip->base;
++    reg_offset = PWM_PCR_BASE + sel * 0x20;
++    reg_shift = PWM_ACT_STA_SHIFT;
++    reg_width = PWM_ACT_STA_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    if (polarity == PWM_POLARITY_NORMAL)
++        temp = SET_BITS(reg_shift, 1, temp, 1);
++    else
++        temp = SET_BITS(reg_shift, 1, temp, 0);
++
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    return 0;
++}
++
++static int sunxi_pwm_set_polarity_dual(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity, int bind_num)
++{
++    u32 temp[2];
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    u32 sel[2] = {0};
++
++    sel[0] = pwm->pwm - chip->base;
++    sel[1] = bind_num - chip->base;
++    /* config current pwm*/
++    reg_offset[0] = PWM_PCR_BASE + sel[0] * 0x20;
++    reg_shift[0] = PWM_ACT_STA_SHIFT;
++    reg_width[0] = PWM_ACT_STA_WIDTH;
++    temp[0] = sunxi_pwm_readl(chip, reg_offset[0]);
++    if (polarity == PWM_POLARITY_NORMAL)
++        temp[0] = SET_BITS(reg_shift[0], 1, temp[0], 1);
++    else
++        temp[0] = SET_BITS(reg_shift[0], 1, temp[0], 0);
++
++    /* config bind pwm*/
++    reg_offset[1] = PWM_PCR_BASE + sel[1] * 0x20;
++    reg_shift[1] = PWM_ACT_STA_SHIFT;
++    reg_width[1] = PWM_ACT_STA_WIDTH;
++    temp[1] = sunxi_pwm_readl(chip, reg_offset[1]);
++
++    /*bind pwm's polarity is reverse compare with the  current pwm*/
++    if (polarity == PWM_POLARITY_NORMAL)
++        temp[1] = SET_BITS(reg_shift[0], 1, temp[1], 0);
++    else
++        temp[1] = SET_BITS(reg_shift[0], 1, temp[1], 1);
++
++    /*config register at the same time*/
++    sunxi_pwm_writel(chip, reg_offset[0], temp[0]);
++    sunxi_pwm_writel(chip, reg_offset[1], temp[1]);
++
++    return 0;
++}
++
++static int sunxi_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity)
++{
++    int bind_num;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
++    if (bind_num == 255)
++        sunxi_pwm_set_polarity_single(chip, pwm, polarity);
++    else
++        sunxi_pwm_set_polarity_dual(chip, pwm, polarity, bind_num);
++
++    return 0;
++}
++
++static u32 get_pccr_reg_offset(u32 sel, u32 *reg_offset)
++{
++    switch (sel)
++    {
++    case 0:
++    case 1:
++        *reg_offset = PWM_PCCR01;
++        break;
++    case 2:
++    case 3:
++        *reg_offset = PWM_PCCR23;
++        break;
++    case 4:
++    case 5:
++        *reg_offset = PWM_PCCR45;
++        break;
++    case 6:
++    case 7:
++        *reg_offset = PWM_PCCR67;
++        break;
++    case 8:
++        *reg_offset = PWM_PCCR8;
++        break;
++    default:
++        pr_err("%s:Not supported!\n", __func__);
++        break;
++    }
++    return 0;
++}
++
++static u32 get_pdzcr_reg_offset(u32 sel, u32 *reg_offset)
++{
++    switch (sel)
++    {
++    case 0:
++    case 1:
++        *reg_offset = PWM_PDZCR01;
++        break;
++    case 2:
++    case 3:
++        *reg_offset = PWM_PDZCR23;
++        break;
++    case 4:
++    case 5:
++        *reg_offset = PWM_PDZCR45;
++        break;
++    case 6:
++    case 7:
++        *reg_offset = PWM_PDZCR67;
++        break;
++    default:
++        pr_err("%s:Not supported!\n", __func__);
++        break;
++    }
++    return 0;
++}
++
++#define PRESCALE_MAX 256
++
++static int sunxi_pwm_config_single(struct pwm_chip *chip, struct pwm_device *pwm,
++                                   int duty_ns, int period_ns)
++{
++    unsigned int temp;
++    unsigned long long c = 0;
++    unsigned long entire_cycles = 256, active_cycles = 192;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++    unsigned int reg_offset, reg_shift, reg_width;
++    unsigned int reg_bypass_shift;
++    unsigned int reg_clk_src_shift, reg_clk_src_width;
++    unsigned int reg_div_m_shift, reg_div_m_width;
++    unsigned int pre_scal_id = 0, div_m = 0, prescale = 0;
++    u32 sel = 0;
++    u32 pre_scal[][2] = {
++
++        /* reg_value  clk_pre_div */
++        {0, 1},
++        {1, 2},
++        {2, 4},
++        {3, 8},
++        {4, 16},
++        {5, 32},
++        {6, 64},
++        {7, 128},
++        {8, 256},
++    };
++
++    sel = pwm->pwm - chip->base;
++
++    get_pccr_reg_offset(sel, &reg_offset);
++    if ((sel % 2) == 0)
++        reg_bypass_shift = 0x5;
++    else
++        reg_bypass_shift = 0x6;
++    /*src clk reg*/
++    reg_clk_src_shift = PWM_CLK_SRC_SHIFT;
++    reg_clk_src_width = PWM_CLK_SRC_WIDTH;
++
++    if (period_ns > 0 && period_ns <= 10)
++    {
++        /* if freq lt 100M, then direct output 100M clock,set by pass. */
++        c = 100000000;
++        /*bypass reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++
++        /*clk_src_reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 1);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++
++        return 0;
++    }
++    else if (period_ns > 10 && period_ns <= 334)
++    {
++        /* if freq between 3M~100M, then select 100M as clock */
++        c = 100000000;
++        /*set clk bypass_output reg to 1 when pwm is used as the internal clock source.*/
++        if (pc->config[pwm->pwm - chip->base].clk_bypass_output == 1) {
++            temp = sunxi_pwm_readl(chip, reg_offset);
++            temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
++            sunxi_pwm_writel(chip, reg_offset, temp);
++        }
++        /*clk_src_reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 1);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++    }
++    else if (period_ns > 334)
++    {
++        /* if freq < 3M, then select 24M clock */
++        c = 24000000;
++        /*set clk bypass_output reg to 1 when pwm is used as the internal clock source.*/
++        if (pc->config[pwm->pwm - chip->base].clk_bypass_output == 1) {
++            temp = sunxi_pwm_readl(chip, reg_offset);
++            temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
++            sunxi_pwm_writel(chip, reg_offset, temp);
++        }
++        /*clk_src_reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 0);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++    }
++    pwm_debug("duty_ns=%d period_ns=%d c =%llu.\n", duty_ns, period_ns, c);
++
++    c = c * period_ns;
++    do_div(c, 1000000000);
++    entire_cycles = (unsigned long)c;
++
++    for (pre_scal_id = 0; pre_scal_id < 9; pre_scal_id++)
++    {
++        if (entire_cycles <= 65536)
++            break;
++        for (prescale = 0; prescale < PRESCALE_MAX + 1; prescale++)
++        {
++            entire_cycles = ((unsigned long)c / pre_scal[pre_scal_id][1]) / (prescale + 1);
++            if (entire_cycles <= 65536)
++            {
++                div_m = pre_scal[pre_scal_id][0];
++                break;
++            }
++        }
++    }
++
++    c = (unsigned long long)entire_cycles * duty_ns;
++    do_div(c, period_ns);
++    active_cycles = c;
++    if (entire_cycles == 0)
++        entire_cycles++;
++
++    /* config  clk div_m*/
++    reg_div_m_shift = PWM_DIV_M_SHIFT;
++    reg_div_m_width = PWM_DIV_M_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_div_m_shift, reg_div_m_width, temp, div_m);
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    /* config prescal */
++    reg_offset = PWM_PCR_BASE + 0x20 * sel;
++    reg_shift = PWM_PRESCAL_SHIFT;
++    reg_width = PWM_PRESCAL_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_shift, reg_width, temp, prescale);
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    /* config active cycles */
++    reg_offset = PWM_PPR_BASE + 0x20 * sel;
++    reg_shift = PWM_ACT_CYCLES_SHIFT;
++    reg_width = PWM_ACT_CYCLES_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_shift, reg_width, temp, active_cycles);
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    /* config period cycles */
++    reg_offset = PWM_PPR_BASE + 0x20 * sel;
++    reg_shift = PWM_PERIOD_CYCLES_SHIFT;
++    reg_width = PWM_PERIOD_CYCLES_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_shift, reg_width, temp, (entire_cycles - 1));
++
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    pwm_debug("active_cycles=%lu entire_cycles=%lu prescale=%u div_m=%u\n",
++              active_cycles, entire_cycles, prescale, div_m);
++    return 0;
++}
++
++static int sunxi_pwm_config_dual(struct pwm_chip *chip, struct pwm_device *pwm,
++                                 int duty_ns, int period_ns, int bind_num)
++{
++    u32 value[2] = {0};
++    unsigned int temp;
++    unsigned long long c = 0, clk = 0, clk_temp = 0;
++    unsigned long entire_cycles = 256, active_cycles = 192;
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    unsigned int reg_bypass_shift;
++    unsigned int reg_dz_en_offset[2], reg_dz_en_shift[2], reg_dz_en_width[2];
++    unsigned int pre_scal_id = 0, div_m = 0, prescale = 0;
++    int src_clk_sel = 0;
++    int i = 0;
++    unsigned int dead_time = 0, duty = 0;
++    u32 pre_scal[][2] = {
++
++        /* reg_value  clk_pre_div */
++        {0, 1},
++        {1, 2},
++        {2, 4},
++        {3, 8},
++        {4, 16},
++        {5, 32},
++        {6, 64},
++        {7, 128},
++        {8, 256},
++    };
++    unsigned int pwm_index[2] = {0};
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    pwm_index[0] = pwm->pwm - chip->base;
++    pwm_index[1] = bind_num - chip->base;
++
++    /* if duty time < dead time,it is wrong. */
++    dead_time = pc->config[pwm_index[0]].dead_time;
++    duty = (unsigned int)duty_ns;
++    /* judge if the pwm eanble dead zone */
++    get_pdzcr_reg_offset(pwm_index[0], &reg_dz_en_offset[0]);
++    reg_dz_en_shift[0] = PWM_DZ_EN_SHIFT;
++    reg_dz_en_width[0] = PWM_DZ_EN_WIDTH;
++
++    value[0] = sunxi_pwm_readl(chip, reg_dz_en_offset[0]);
++    value[0] = SET_BITS(reg_dz_en_shift[0], reg_dz_en_width[0], value[0], 1);
++    sunxi_pwm_writel(chip, reg_dz_en_offset[0], value[0]);
++    temp = sunxi_pwm_readl(chip, reg_dz_en_offset[0]);
++    temp &= (1u << reg_dz_en_shift[0]);
++    if (duty < dead_time || temp == 0)
++    {
++        pr_err("[PWM]duty time or dead zone error.\n");
++        return -EINVAL;
++    }
++
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        if ((i % 2) == 0)
++            reg_bypass_shift = 0x5;
++        else
++            reg_bypass_shift = 0x6;
++        get_pccr_reg_offset(pwm_index[i], &reg_offset[i]);
++        reg_shift[i] = reg_bypass_shift;
++        reg_width[i] = PWM_BYPASS_WIDTH;
++    }
++
++    if (period_ns > 0 && period_ns <= 10)
++    {
++        /* if freq lt 100M, then direct output 100M clock,set by pass */
++        clk = 100000000;
++        src_clk_sel = 1;
++
++        /* config the two pwm bypass */
++        for (i = 0; i < PWM_BIND_NUM; i++)
++        {
++            temp = sunxi_pwm_readl(chip, reg_offset[i]);
++            temp = SET_BITS(reg_shift[i], reg_width[i], temp, 1);
++            sunxi_pwm_writel(chip, reg_offset[i], temp);
++
++            reg_shift[i] = PWM_CLK_SRC_SHIFT;
++            reg_width[i] = PWM_CLK_SRC_WIDTH;
++            temp = sunxi_pwm_readl(chip, reg_offset[i]);
++            temp = SET_BITS(reg_shift[i], reg_width[i], temp, 1);
++            sunxi_pwm_writel(chip, reg_offset[i], temp);
++        }
++
++        return 0;
++    }
++    else if (period_ns > 10 && period_ns <= 334)
++    {
++        clk = 100000000;
++        src_clk_sel = 1;
++    }
++    else if (period_ns > 334)
++    {
++        /* if freq < 3M, then select 24M clock */
++        clk = 24000000;
++        src_clk_sel = 0;
++    }
++
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_shift[i] = PWM_CLK_SRC_SHIFT;
++        reg_width[i] = PWM_CLK_SRC_WIDTH;
++
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, src_clk_sel);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    c = clk;
++    c *= period_ns;
++    do_div(c, 1000000000);
++    entire_cycles = (unsigned long)c;
++
++    /* get div_m and prescale,which satisfy: deat_val <= 256, entire <= 65536 */
++    for (pre_scal_id = 0; pre_scal_id < 9; pre_scal_id++)
++    {
++        for (prescale = 0; prescale < PRESCALE_MAX + 1; prescale++)
++        {
++            entire_cycles = ((unsigned long)c / pre_scal[pre_scal_id][1]) / (prescale + 1);
++            clk_temp = clk;
++            do_div(clk_temp, pre_scal[pre_scal_id][1] * (prescale + 1));
++            clk_temp *= dead_time;
++            do_div(clk_temp, 1000000000);
++            if (entire_cycles <= 65536 && clk_temp <= 256)
++            {
++                div_m = pre_scal[pre_scal_id][0];
++                break;
++            }
++        }
++        if (entire_cycles <= 65536 && clk_temp <= 256)
++            break;
++        else
++        {
++            pr_err("%s:config dual err.entire_cycles=%lu, dead_zone_val=%llu",
++                   __func__, entire_cycles, clk_temp);
++            return -EINVAL;
++        }
++    }
++
++    c = (unsigned long long)entire_cycles * duty_ns;
++    do_div(c, period_ns);
++    active_cycles = c;
++    if (entire_cycles == 0)
++        entire_cycles++;
++
++    /* config  clk div_m*/
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_shift[i] = PWM_DIV_M_SHIFT;
++        reg_width[i] = PWM_DIV_M_SHIFT;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, div_m);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    /* config prescal */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PCR_BASE + 0x20 * pwm_index[i];
++        reg_shift[i] = PWM_PRESCAL_SHIFT;
++        reg_width[i] = PWM_PRESCAL_WIDTH;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, prescale);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    /* config active cycles */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PPR_BASE + 0x20 * pwm_index[i];
++        reg_shift[i] = PWM_ACT_CYCLES_SHIFT;
++        reg_width[i] = PWM_ACT_CYCLES_WIDTH;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, active_cycles);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    /* config period cycles */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PPR_BASE + 0x20 * pwm_index[i];
++        reg_shift[i] = PWM_PERIOD_CYCLES_SHIFT;
++        reg_width[i] = PWM_PERIOD_CYCLES_WIDTH;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, (entire_cycles - 1));
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    pwm_debug("active_cycles=%lu entire_cycles=%lu prescale=%u div_m=%u\n",
++              active_cycles, entire_cycles, prescale, div_m);
++
++    /* config dead zone, one config for two pwm */
++    reg_offset[0] = reg_dz_en_offset[0];
++    reg_shift[0] = PWM_PDZINTV_SHIFT;
++    reg_width[0] = PWM_PDZINTV_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset[0]);
++    temp = SET_BITS(reg_shift[0], reg_width[0], temp, (unsigned int)clk_temp);
++    sunxi_pwm_writel(chip, reg_offset[0], temp);
++
++    return 0;
++}
++
++static int sunxi_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
++                            int duty_ns, int period_ns)
++{
++    int bind_num;
++
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
++    if (bind_num == 255) {
++        sunxi_pwm_config_single(chip, pwm, duty_ns, period_ns);
++    }
++    else {
++        sunxi_pwm_config_dual(chip, pwm, duty_ns, period_ns, bind_num);
++    }
++
++    return 0;
++}
++
++static int sunxi_pwm_enable_single(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    unsigned int value = 0, index = 0;
++    unsigned int reg_offset, reg_shift;
++    struct device_node *sub_np;
++    struct platform_device *pwm_pdevice;
++    int ret;
++
++    index = pwm->pwm - chip->base;
++    sub_np = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", index);
++    if (IS_ERR_OR_NULL(sub_np))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return -ENODEV;
++    }
++    pwm_pdevice = of_find_device_by_node(sub_np);
++    if (IS_ERR_OR_NULL(pwm_pdevice))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return -ENODEV;
++    }
++    ret = sunxi_pwm_pin_set_state(&pwm_pdevice->dev, PWM_PIN_STATE_ACTIVE);
++    if (ret != 0)
++        return ret;
++
++    /* enable clk for pwm controller */
++    get_pccr_reg_offset(index, &reg_offset);
++    reg_shift = PWM_CLK_GATING_SHIFT;
++    value = sunxi_pwm_readl(chip, reg_offset);
++    value = SET_BITS(reg_shift, 1, value, 1);
++    sunxi_pwm_writel(chip, reg_offset, value);
++
++    /* enable pwm controller */
++    reg_offset = PWM_PER;
++    reg_shift = index;
++    value = sunxi_pwm_readl(chip, reg_offset);
++    value = SET_BITS(reg_shift, 1, value, 1);
++    sunxi_pwm_writel(chip, reg_offset, value);
++
++    return 0;
++}
++
++static int sunxi_pwm_enable_dual(struct pwm_chip *chip, struct pwm_device *pwm, int bind_num)
++{
++    u32 value[2] = {0};
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    struct device_node *sub_np[2];
++    struct platform_device *pwm_pdevice[2];
++    int i = 0, ret = 0;
++    unsigned int pwm_index[2] = {0};
++
++    pwm_index[0] = pwm->pwm - chip->base;
++    pwm_index[1] = bind_num - chip->base;
++
++    /*set current pwm pin state*/
++    sub_np[0] = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", pwm_index[0]);
++    if (IS_ERR_OR_NULL(sub_np[0]))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return -ENODEV;
++    }
++    pwm_pdevice[0] = of_find_device_by_node(sub_np[0]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[0]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return -ENODEV;
++    }
++
++    /*set bind pwm pin state*/
++    sub_np[1] = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", pwm_index[1]);
++    if (IS_ERR_OR_NULL(sub_np[1]))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return -ENODEV;
++    }
++    pwm_pdevice[1] = of_find_device_by_node(sub_np[1]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[1]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return -ENODEV;
++    }
++
++    ret = sunxi_pwm_pin_set_state(&pwm_pdevice[0]->dev, PWM_PIN_STATE_ACTIVE);
++    if (ret != 0)
++        return ret;
++    ret = sunxi_pwm_pin_set_state(&pwm_pdevice[1]->dev, PWM_PIN_STATE_ACTIVE);
++    if (ret != 0)
++        return ret;
++
++    /* enable clk for pwm controller */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        get_pccr_reg_offset(pwm_index[i], &reg_offset[i]);
++        reg_shift[i] = PWM_CLK_GATING_SHIFT;
++        reg_width[i] = PWM_CLK_GATING_WIDTH;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 1);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    /* enable pwm controller */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PER;
++        reg_shift[i] = pwm_index[i];
++        reg_width[i] = 0x1;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 1);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    return 0;
++}
++
++static int sunxi_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    int bind_num;
++    int ret = 0;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
++    if (bind_num == 255)
++        ret = sunxi_pwm_enable_single(chip, pwm);
++    else
++        ret = sunxi_pwm_enable_dual(chip, pwm, bind_num);
++
++    sunxi_pwm_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
++
++    return ret;
++}
++
++static void sunxi_pwm_disable_single(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    u32 value = 0, index = 0;
++    unsigned int reg_offset, reg_shift, reg_width;
++    struct device_node *sub_np;
++    struct platform_device *pwm_pdevice;
++
++    index = pwm->pwm - chip->base;
++    sub_np = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", index);
++    if (IS_ERR_OR_NULL(sub_np))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return;
++    }
++    pwm_pdevice = of_find_device_by_node(sub_np);
++    if (IS_ERR_OR_NULL(pwm_pdevice))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return;
++    }
++
++    /* disable pwm controller */
++    reg_offset = PWM_PER;
++    reg_shift = index;
++    reg_width = 0x1;
++    value = sunxi_pwm_readl(chip, reg_offset);
++    value = SET_BITS(reg_shift, reg_width, value, 0);
++    sunxi_pwm_writel(chip, reg_offset, value);
++
++    /*
++     * 0 , 1 --> 0
++     * 2 , 3 --> 2
++     * 4 , 5 --> 4
++     * 6 , 7 --> 6
++     */
++    reg_shift &= ~(1);
++
++    if (GET_BITS(reg_shift, 2, value) == 0)
++    {
++        /* disable clk for pwm controller. */
++        get_pccr_reg_offset(index, &reg_offset);
++        reg_shift = PWM_CLK_GATING_SHIFT;
++        reg_width = 0x1;
++        value = sunxi_pwm_readl(chip, reg_offset);
++        value = SET_BITS(reg_shift, reg_width, value, 0);
++        sunxi_pwm_writel(chip, reg_offset, value);
++    }
++
++    // sunxi_pwm_pin_set_state(&pwm_pdevice->dev, PWM_PIN_STATE_SLEEP);
++}
++
++static void sunxi_pwm_disable_dual(struct pwm_chip *chip, struct pwm_device *pwm, int bind_num)
++{
++    u32 value[2] = {0};
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    struct device_node *sub_np[2];
++    struct platform_device *pwm_pdevice[2];
++    int i = 0;
++    unsigned int pwm_index[2] = {0};
++
++    pwm_index[0] = pwm->pwm - chip->base;
++    pwm_index[1] = bind_num - chip->base;
++
++    /* get current index pwm device */
++    sub_np[0] = of_parse_phandle(chip->dev->of_node, "pwms", pwm_index[0]);
++    if (IS_ERR_OR_NULL(sub_np[0]))
++    {
++        pr_err("%s: can't parse \"pwms\" property\n", __func__);
++        return;
++    }
++    pwm_pdevice[0] = of_find_device_by_node(sub_np[0]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[0]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return;
++    }
++    /* get bind pwm device */
++    sub_np[1] = of_parse_phandle(chip->dev->of_node, "pwms", pwm_index[1]);
++    if (IS_ERR_OR_NULL(sub_np[1]))
++    {
++        pr_err("%s: can't parse \"pwms\" property\n", __func__);
++        return;
++    }
++    pwm_pdevice[1] = of_find_device_by_node(sub_np[1]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[1]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return;
++    }
++
++    /* disable pwm controller */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PER;
++        reg_shift[i] = pwm_index[i];
++        reg_width[i] = 0x1;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 0);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    /* disable pwm clk gating */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        get_pccr_reg_offset(pwm_index[i], &reg_offset[i]);
++        reg_shift[i] = PWM_CLK_GATING_SHIFT;
++        reg_width[i] = 0x1;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 0);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    /* disable pwm dead zone,one for the two pwm */
++    get_pdzcr_reg_offset(pwm_index[0], &reg_offset[0]);
++    reg_shift[0] = PWM_DZ_EN_SHIFT;
++    reg_width[0] = PWM_DZ_EN_WIDTH;
++    value[0] = sunxi_pwm_readl(chip, reg_offset[0]);
++    value[0] = SET_BITS(reg_shift[0], reg_width[0], value[0], 0);
++    sunxi_pwm_writel(chip, reg_offset[0], value[0]);
++
++    /* config pin sleep */
++    // sunxi_pwm_pin_set_state(&pwm_pdevice[0]->dev, PWM_PIN_STATE_SLEEP);
++    // sunxi_pwm_pin_set_state(&pwm_pdevice[1]->dev, PWM_PIN_STATE_SLEEP);
++}
++
++static void sunxi_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    int bind_num;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
++    if (bind_num == 255)
++        sunxi_pwm_disable_single(chip, pwm);
++    else
++        sunxi_pwm_disable_dual(chip, pwm, bind_num);
++}
++
++static int sunxi_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
++			    const struct pwm_state *state)
++{
++	int err;
++	bool enabled = pwm->state.enabled;
++
++	if (state->polarity != pwm->state.polarity) {
++		/*
++		 * Changing the polarity of a running PWM is only allowed when
++		 * the PWM driver implements ->apply().
++		 */
++		if (enabled) {
++			sunxi_pwm_disable(chip, pwm);
++
++			enabled = false;
++		}
++
++		err = sunxi_pwm_set_polarity(chip, pwm, state->polarity);
++		if (err)
++			return err;
++	}
++
++
++	if (!state->enabled) {
++		if (enabled) {
++			sunxi_pwm_disable(chip, pwm);
++        }
++
++		return 0;
++	}
++
++	/*
++	 * We cannot skip calling ->config even if state->period ==
++	 * pwm->state.period && state->duty_cycle == pwm->state.duty_cycle
++	 * because we might have exited early in the last call to
++	 * pwm_apply_state because of !state->enabled and so the two values in
++	 * pwm->state might not be configured in hardware.
++	 */
++	err = sunxi_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
++	if (err) {
++		return err;
++    }
++
++	if (!enabled)
++		err = sunxi_pwm_enable(chip, pwm);
++
++	return err;
++}
++
++static const struct pwm_ops sunxi_pwm_ops = {
++	.apply = sunxi_pwm_apply,
++	.owner = THIS_MODULE,
++};
++
++static int sunxi_pwm_probe(struct platform_device *pdev)
++{
++    int ret;
++    struct sunxi_pwm_chip *pwm;
++    struct device_node *np = pdev->dev.of_node;
++    int i;
++    struct platform_device *pwm_pdevice;
++    struct device_node *sub_np;
++
++    pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
++    if (!pwm)
++    {
++        dev_err(&pdev->dev, "failed to allocate memory!\n");
++        return -ENOMEM;
++    }
++
++    /* io map pwm base */
++    pwm->base = (void __iomem *)of_iomap(pdev->dev.of_node, 0);
++    if (!pwm->base)
++    {
++        dev_err(&pdev->dev, "unable to map pwm registers\n");
++        ret = -EINVAL;
++        goto err_iomap;
++    }
++
++    /* read property pwm-number */
++    ret = of_property_read_u32(np, "pwm-number", &pwm->chip.npwm);
++    if (ret < 0)
++    {
++        dev_err(&pdev->dev, "failed to get pwm number: %d, force to one!\n", ret);
++        /* force to one pwm if read property fail */
++        pwm->chip.npwm = 1;
++    }
++
++    /* read property pwm-base */
++    ret = of_property_read_u32(np, "pwm-base", &pwm->chip.base);
++    if (ret < 0)
++    {
++        dev_err(&pdev->dev, "failed to get pwm-base: %d, force to -1 !\n", ret);
++        /* force to one pwm if read property fail */
++        pwm->chip.base = -1;
++    }
++    pwm->chip.dev = &pdev->dev;
++    pwm->chip.ops = &sunxi_pwm_ops;
++
++    /* add pwm chip to pwm-core */
++    ret = pwmchip_add(&pwm->chip);
++    if (ret < 0)
++    {
++        dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
++        goto err_add;
++    }
++    platform_set_drvdata(pdev, pwm);
++
++    pwm->config = devm_kzalloc(&pdev->dev, sizeof(*pwm->config) * pwm->chip.npwm, GFP_KERNEL);
++    if (!pwm->config)
++    {
++        dev_err(&pdev->dev, "failed to allocate memory!\n");
++        goto err_alloc;
++    }
++
++    for (i = 0; i < pwm->chip.npwm; i++)
++    {
++        sub_np = of_parse_phandle(np, "sunxi-pwms", i);
++        if (IS_ERR_OR_NULL(sub_np))
++        {
++            pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++            return -EINVAL;
++        }
++
++        pwm_pdevice = of_find_device_by_node(sub_np);
++        ret = sunxi_pwm_get_config(pwm_pdevice, &pwm->config[i]);
++        if (ret)
++        {
++            pr_err("Get config failed,exit!\n");
++            goto err_get_config;
++        }
++    }
++
++    pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
++    if (IS_ERR(pwm->clk))
++        return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk),
++                             "get mod clock failed\n");
++
++    pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
++    if (IS_ERR(pwm->bus_clk))
++        return dev_err_probe(&pdev->dev, PTR_ERR(pwm->bus_clk),
++                             "get bus clock failed\n");
++
++    pwm->pwm_rst_clk = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
++    if (IS_ERR(pwm->pwm_rst_clk))
++        return dev_err_probe(&pdev->dev, PTR_ERR(pwm->pwm_rst_clk),
++                             "get reset failed\n");
++
++    /* Deassert reset */
++    ret = reset_control_deassert(pwm->pwm_rst_clk);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
++                ERR_PTR(ret));
++        return ret;
++    }
++
++    ret = clk_prepare_enable(pwm->clk);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "cannot prepare and enable clk %pe\n",
++                ERR_PTR(ret));
++        goto err_alloc;
++    }
++
++    ret = clk_prepare_enable(pwm->bus_clk);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
++                ERR_PTR(ret));
++        goto err_alloc;
++    }
++
++    return 0;
++
++err_get_config:
++err_alloc:
++    pwmchip_remove(&pwm->chip);
++err_add:
++    iounmap(pwm->base);
++err_iomap:
++    return ret;
++}
++
++static int sunxi_pwm_remove(struct platform_device *pdev)
++{
++    struct sunxi_pwm_chip *pwm = platform_get_drvdata(pdev);
++    clk_disable(pwm->clk);
++    clk_disable(pwm->bus_clk);
++    reset_control_assert(pwm->pwm_rst_clk);
++    pwmchip_remove(&pwm->chip);
++
++    return 0;
++}
++
++static int sunxi_pwm_suspend(struct platform_device *pdev, pm_message_t state)
++{
++    return 0;
++}
++
++static int sunxi_pwm_resume(struct platform_device *pdev)
++{
++    return 0;
++}
++
++#if !IS_ENABLED(CONFIG_OF)
++struct platform_device sunxi_pwm_device = {
++    .name = "sunxi_pwm",
++    .id = -1,
++};
++#else
++static const struct of_device_id sunxi_pwm_match[] = {
++    {
++        .compatible = "allwinner,sun50i-h616-pwm",
++    },
++    {},
++};
++MODULE_DEVICE_TABLE(of, sunxi_pwm_match);
++#endif
++
++static struct platform_driver sunxi_pwm_driver = {
++    .probe = sunxi_pwm_probe,
++    .remove = sunxi_pwm_remove,
++    .suspend = sunxi_pwm_suspend,
++    .resume = sunxi_pwm_resume,
++    .driver = {
++        .name = "sunxi_pwm",
++        .owner = THIS_MODULE,
++        .of_match_table = sunxi_pwm_match,
++    },
++};
++
++static int __init pwm_module_init(void)
++{
++    int ret = 0;
++
++#if !IS_ENABLED(CONFIG_OF)
++    ret = platform_device_register(&sunxi_pwm_device);
++#endif
++    if (ret == 0)
++    {
++        ret = platform_driver_register(&sunxi_pwm_driver);
++    }
++
++    return ret;
++}
++
++static void __exit pwm_module_exit(void)
++{
++    platform_driver_unregister(&sunxi_pwm_driver);
++#if !IS_ENABLED(CONFIG_OF)
++    platform_device_unregister(&sunxi_pwm_device);
++#endif
++}
++
++subsys_initcall(pwm_module_init);
++module_exit(pwm_module_exit);
++
++MODULE_AUTHOR("zengqi");
++MODULE_AUTHOR("liuli");
++MODULE_DESCRIPTION("pwm driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:sunxi-pwm");
+diff --git a/drivers/pwm/pwm-sunxi-enhance.h b/drivers/pwm/pwm-sunxi-enhance.h
+new file mode 100644
+index 000000000000..e25e10bf5a3d
+--- /dev/null
++++ b/drivers/pwm/pwm-sunxi-enhance.h
+@@ -0,0 +1,60 @@
++/*
++ * drivers/pwm/pwm-sunxi-new.h
++ *
++ * Allwinnertech pulse-width-modulation controller driver
++ *
++ * Copyright (C) 2018 AllWinner
++ *
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#ifndef __PWM_SUNXI_NEW__H__
++#define __PWM_SUNXI_NEW__H__
++
++#define PWM_PIER	(0x0000)
++#define PWM_PISR	(0x0004)
++#define	PWM_CIER	(0x0010)
++#define	PWM_CISR	(0x0014)
++#define PWM_PCCR01	(0x0020)
++#define PWM_PCCR23	(0x0024)
++#define PWM_PCCR45	(0x0028)
++#define PWM_PCCR67	(0x002c)
++#define PWM_PDZCR01	(0x0030)
++#define PWM_PDZCR23	(0x0034)
++#define	PWM_PDZCR45	(0x0038)
++#define	PWM_PDZCR67	(0x003c)
++#define PWM_PER		(0x0040)
++#define PWM_CER		(0x0044)
++
++#define PWM_PCR_BASE	(0x0060 + 0x0000)
++#define PWM_PPR_BASE	(0x0060 + 0x0004)
++#define PWM_PCNTR_BASE	(0x0060 + 0x0008)
++#define PWM_CCR_BASE	(0x0060 + 0x000c)
++#define	PWM_CRLR_BASE	(0x0060 + 0x0010)
++#define PWM_CFLR_BASE	(0x0060 + 0x0014)
++#define PWM_PCCR8	(0x0300)
++
++#define PWM_ACT_STA_SHIFT	0x8
++#define PWM_ACT_STA_WIDTH	0x1
++#define PWM_CLK_SRC_SHIFT	0x7
++#define PWM_CLK_SRC_WIDTH	0x2
++#define PWM_DIV_M_SHIFT		0x0
++#define PWM_DIV_M_WIDTH		0x4
++#define PWM_PRESCAL_SHIFT	0x0
++#define PWM_PRESCAL_WIDTH	0x8
++#define PWM_ACT_CYCLES_SHIFT	0x0
++#define PWM_ACT_CYCLES_WIDTH	0x10
++#define PWM_PERIOD_CYCLES_SHIFT	0x10
++#define PWM_PERIOD_CYCLES_WIDTH	0x10
++#define PWM_DZ_EN_SHIFT		0x0
++#define PWM_DZ_EN_WIDTH		0x1
++#define PWM_PDZINTV_SHIFT	0x8
++#define PWM_PDZINTV_WIDTH	0x8
++#define PWM_BYPASS_WIDTH	0x1
++#define PWM_CLK_GATING_SHIFT	0x4
++#define PWM_CLK_GATING_WIDTH	0x1
++
++#endif
++
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-clk-sunxi-ng-ccu-add-min-max-rate-sun50i-a64.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-clk-sunxi-ng-ccu-add-min-max-rate-sun50i-a64.patch
new file mode 100644
index 000000000000..b8a09d6a8575
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-clk-sunxi-ng-ccu-add-min-max-rate-sun50i-a64.patch
@@ -0,0 +1,57 @@
+From b6894e8ddd9774b19b7e1dd87a7a4569a6ada801 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Tue, 24 Jul 2018 10:17:55 -0700
+Subject: drv:clk:sunxi-ng: ccu: add min/max rate sun50i-a64
+
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
+ drivers/clk/sunxi-ng/ccu_nkm.c        | 5 +++++
+ drivers/clk/sunxi-ng/ccu_nkm.h        | 3 +++
+ 3 files changed, 10 insertions(+)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index f72c428671d1..3fe32ec6ad4a 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -196,6 +196,8 @@ static struct ccu_nkm pll_mipi_clk = {
+ 	.n		= _SUNXI_CCU_MULT(8, 4),
+ 	.k		= _SUNXI_CCU_MULT_MIN(4, 2, 2),
+ 	.m		= _SUNXI_CCU_DIV(0, 4),
++	.min_rate	= 300000000,
++	.max_rate	= 1400000000,
+ 	.common		= {
+ 		.reg		= 0x040,
+ 		.hw.init	= CLK_HW_INIT("pll-mipi", "pll-video0",
+diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
+index 853f84398e2b..adb35bc1c31e 100644
+--- a/drivers/clk/sunxi-ng/ccu_nkm.c
++++ b/drivers/clk/sunxi-ng/ccu_nkm.c
+@@ -157,6 +157,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
+ 	_nkm.min_m = 1;
+ 	_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
+ 
++	if (rate < nkm->min_rate)
++		rate = nkm->min_rate;
++	if (nkm->max_rate && (rate > nkm->max_rate))
++		rate = nkm->max_rate;
++
+ 	if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ 		rate *= nkm->fixed_post_div;
+ 
+diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
+index 6601defb3f38..57aa8087c2a7 100644
+--- a/drivers/clk/sunxi-ng/ccu_nkm.h
++++ b/drivers/clk/sunxi-ng/ccu_nkm.h
+@@ -28,6 +28,9 @@ struct ccu_nkm {
+ 
+ 	unsigned int		fixed_post_div;
+ 
++	unsigned int		min_rate;
++	unsigned int		max_rate;
++
+ 	struct ccu_common	common;
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch
new file mode 100644
index 000000000000..b268d99eccf4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch
@@ -0,0 +1,48 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 14:18:17 +0300
+Subject: drv:clocksource:arm_arch_timer fix a64 timejump
+
+---
+ drivers/clocksource/arm_arch_timer.c | 25 ++++++----
+ 1 file changed, 14 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
+index 7dd2c615bce2..fae1985407ab 100644
+--- a/drivers/clocksource/arm_arch_timer.c
++++ b/drivers/clocksource/arm_arch_timer.c
+@@ -383,17 +383,20 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
+  * with all ones or all zeros in the low bits. Bound the loop by the maximum
+  * number of CPU cycles in 3 consecutive 24 MHz counter periods.
+  */
+-#define __sun50i_a64_read_reg(reg) ({					\
+-	u64 _val;							\
+-	int _retries = 150;						\
+-									\
+-	do {								\
+-		_val = read_sysreg(reg);				\
+-		_retries--;						\
+-	} while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries);	\
+-									\
+-	WARN_ON_ONCE(!_retries);					\
+-	_val;								\
++#define __sun50i_a64_read_reg(reg) ({                                                 \
++    register u64 _tries = 5, _old, _new;                                              \
++                                                                                      \
++    do {                                                                              \
++        if (unlikely(_tries < 3))                                                     \
++            isb();                                                                    \
++        _old = read_sysreg(reg);                                                      \
++        _new = read_sysreg(reg);                                                      \
++    } while (unlikely((_new - _old) >> 4) && --_tries);                               \
++                                                                                      \
++    if (unlikely(!_tries))                                                            \
++        pr_err("(cpu %d) returning possibly incorrect counter value %llx (%llx)\n",   \
++                smp_processor_id() + 1, _new, _old);                                  \
++   _new;                                                                              \
+ })
+ 
+ static u64 notrace sun50i_a64_read_cntpct_el0(void)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch
new file mode 100644
index 000000000000..ad3f198295f7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch
@@ -0,0 +1,51 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Mon, 7 Dec 2015 09:33:28 +0100
+Subject: drv:gpu:drm: gem: dma: Export with handle allocator
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ drivers/gpu/drm/drm_gem_dma_helper.c | 3 ++-
+ include/drm/drm_gem_dma_helper.h     | 4 ++++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/drm_gem_dma_helper.c b/drivers/gpu/drm/drm_gem_dma_helper.c
+index 870b90b78bc4..e93173639775 100644
+--- a/drivers/gpu/drm/drm_gem_dma_helper.c
++++ b/drivers/gpu/drm/drm_gem_dma_helper.c
+@@ -187,7 +187,7 @@ EXPORT_SYMBOL_GPL(drm_gem_dma_create);
+  * A struct drm_gem_dma_object * on success or an ERR_PTR()-encoded negative
+  * error code on failure.
+  */
+-static struct drm_gem_dma_object *
++struct drm_gem_dma_object *
+ drm_gem_dma_create_with_handle(struct drm_file *file_priv,
+ 			       struct drm_device *drm, size_t size,
+ 			       uint32_t *handle)
+@@ -214,6 +214,7 @@ drm_gem_dma_create_with_handle(struct drm_file *file_priv,
+ 
+ 	return dma_obj;
+ }
++EXPORT_SYMBOL_GPL(drm_gem_dma_create_with_handle);
+ 
+ /**
+  * drm_gem_dma_free - free resources associated with a DMA GEM object
+diff --git a/include/drm/drm_gem_dma_helper.h b/include/drm/drm_gem_dma_helper.h
+index a827bde494f6..e93c6843b1e0 100644
+--- a/include/drm/drm_gem_dma_helper.h
++++ b/include/drm/drm_gem_dma_helper.h
+@@ -34,6 +34,10 @@ struct drm_gem_dma_object {
+ 
+ struct drm_gem_dma_object *drm_gem_dma_create(struct drm_device *drm,
+ 					      size_t size);
++struct drm_gem_dma_object *
++drm_gem_dma_create_with_handle(struct drm_file *file_priv,
++			       struct drm_device *drm, size_t size,
++			       uint32_t *handle);
+ void drm_gem_dma_free(struct drm_gem_dma_object *dma_obj);
+ void drm_gem_dma_print_info(const struct drm_gem_dma_object *dma_obj,
+ 			    struct drm_printer *p, unsigned int indent);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch
new file mode 100644
index 000000000000..643a7fdbee71
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch
@@ -0,0 +1,170 @@
+From b5065b831d752c7fc91d574e9a1ef3e565cd0432 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 19:34:55 +0300
+Subject: drv:gpu:drm: panel-simple Add compability olinuxino lcd
+
+---
+ drivers/gpu/drm/panel/panel-simple.c | 126 ++++++++++++++++++++++++++-
+ 1 file changed, 122 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
+index 6aac6f2accb4..9f36f687dc75 100644
+--- a/drivers/gpu/drm/panel/panel-simple.c
++++ b/drivers/gpu/drm/panel/panel-simple.c
+@@ -3314,6 +3314,44 @@ static const struct panel_desc okaya_rs800480t_7x0gp = {
+ 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+ };
+ 
++static const struct drm_display_mode olimex_vga_olinuxino_800_mode = {
++	.clock = 40000,
++	.hdisplay = 800,
++	.hsync_start = 800 + 40,
++	.hsync_end = 800 + 40 + 128,
++	.htotal = 800 + 40 + 128 + 88,
++	.vdisplay = 600,
++	.vsync_start = 600 + 5,
++	.vsync_end = 600 + 5 + 4,
++	.vtotal = 600 + 5 + 4 + 19,
++};
++
++static const struct drm_display_mode olimex_vga_olinuxino_1024_mode = {
++	.clock = 45000,
++	.hdisplay = 1024,
++	.hsync_start = 1024 + 16,
++	.hsync_end = 1024 + 16 + 10,
++	.htotal = 1024 + 16 + 10 + 150,
++	.vdisplay = 600,
++	.vsync_start = 600 + 2,
++	.vsync_end = 600 + 2 + 21,
++	.vtotal = 600 + 2 + 21 + 2,
++};
++
++
++static const struct drm_display_mode olimex_lcd_olinuxino_43_mode = {
++	.clock = 12000,
++	.hdisplay = 480,
++	.hsync_start = 480 + 8,
++	.hsync_end = 480 + 8 + 20,
++	.htotal = 480 + 8 + 20 + 23,
++	.vdisplay = 272,
++	.vsync_start = 272 + 4,
++	.vsync_end = 272 + 4 + 10,
++	.vtotal = 272 + 4 + 10 + 13,
++};
++
++
+ static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
+ 	.clock = 9000,
+ 	.hdisplay = 480,
+@@ -3326,8 +3364,8 @@ static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
+ 	.vtotal = 272 + 8 + 5 + 3,
+ };
+ 
+-static const struct panel_desc olimex_lcd_olinuxino_43ts = {
+-	.modes = &olimex_lcd_olinuxino_43ts_mode,
++static const struct panel_desc olimex_lcd_olinuxino_43 = {
++	.modes = &olimex_lcd_olinuxino_43_mode,
+ 	.num_modes = 1,
+ 	.size = {
+ 		.width = 95,
+@@ -3336,6 +3374,71 @@ static const struct panel_desc olimex_lcd_olinuxino_43ts = {
+ 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ };
+ 
++static const struct drm_display_mode olimex_lcd_olinuxino_5_mode = {
++	.clock = 33300,
++	.hdisplay = 800,
++	.hsync_start = 800 + 210,
++	.hsync_end = 800 + 210 + 20,
++	.htotal = 800 + 210 + 20 + 26,
++	.vdisplay = 480,
++	.vsync_start = 480 + 22,
++	.vsync_end = 480 + 22 + 10,
++	.vtotal = 480 + 22 + 10 + 13,
++};
++
++static const struct panel_desc olimex_lcd_olinuxino_5 = {
++	.modes = &olimex_lcd_olinuxino_5_mode,
++	.num_modes = 1,
++	.size = {
++		.width = 154,
++		.height = 86,
++	},
++	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
++};
++static const struct drm_display_mode olimex_lcd_olinuxino_7_mode = {
++	.clock = 33300,
++	.hdisplay = 800,
++	.hsync_start = 800 + 210,
++	.hsync_end = 800 + 210 + 20,
++	.htotal = 800 + 210 + 20 + 26,
++	.vdisplay = 480,
++	.vsync_start = 480 + 22,
++	.vsync_end = 480 + 22 + 10,
++	.vtotal = 480 + 22 + 10 + 13,
++};
++
++static const struct panel_desc olimex_lcd_olinuxino_7 = {
++	.modes = &olimex_lcd_olinuxino_7_mode,
++	.num_modes = 1,
++	.size = {
++		.width = 154,
++		.height = 86,
++	},
++	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
++};
++
++static const struct drm_display_mode olimex_lcd_olinuxino_10_mode = {
++	.clock = 45000,
++	.hdisplay = 1024,
++	.hsync_start = 1024 + 16,
++	.hsync_end = 1024 + 16 + 1,
++	.htotal = 1024 + 10 + 6 + 160,
++	.vdisplay = 600,
++	.vsync_start = 600 + 1,
++	.vsync_end = 600 + 1 + 1,
++	.vtotal = 600 + 1 + 1 + 22,
++};
++
++static const struct panel_desc olimex_lcd_olinuxino_10 = {
++	.modes = &olimex_lcd_olinuxino_10_mode,
++	.num_modes = 1,
++	.size = {
++		.width = 222,
++		.height = 143,
++	},
++	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
++};
++
+ /*
+  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
+  * pixel clocks, but this is the timing that was being used in the Adafruit
+@@ -4623,8 +4726,23 @@ static const struct of_device_id platform_of_match[] = {
+ 		.compatible = "okaya,rs800480t-7x0gp",
+ 		.data = &okaya_rs800480t_7x0gp,
+ 	}, {
+-		.compatible = "olimex,lcd-olinuxino-43-ts",
+-		.data = &olimex_lcd_olinuxino_43ts,
++		.compatible = "olimex,olinuxino-vga-800x600",
++		.data = &olimex_vga_olinuxino_800_mode,
++	}, {
++		.compatible = "olimex,olinuxino-vga-1024x768",
++		.data = &olimex_vga_olinuxino_1024_mode,
++	}, {
++		.compatible = "olimex,lcd-olinuxino-4.3",
++		.data = &olimex_lcd_olinuxino_43,
++	}, {
++		.compatible = "olimex,lcd-olinuxino-5",
++		.data = &olimex_lcd_olinuxino_5,
++	}, {
++		.compatible = "olimex,lcd-olinuxino-7",
++		.data = &olimex_lcd_olinuxino_7,
++	}, {
++		.compatible = "olimex,lcd-olinuxino-10",
++		.data = &olimex_lcd_olinuxino_10,
+ 	}, {
+ 		.compatible = "ontat,yx700wv03",
+ 		.data = &ontat_yx700wv03,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch
new file mode 100644
index 000000000000..500114c3a564
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch
@@ -0,0 +1,103 @@
+From d67590fdea164deffb54df238928e2eb1e3e390a Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Mon, 7 Dec 2015 09:47:34 +0100
+Subject: drv:gpu:drm:sun4i: Add GEM allocator
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ drivers/gpu/drm/sun4i/sun4i_drv.c | 27 +++++++++++++++++++++++++++
+ include/uapi/drm/sun4i_drm.h      | 29 +++++++++++++++++++++++++++++
+ 2 files changed, 56 insertions(+)
+ create mode 100644 include/uapi/drm/sun4i_drm.h
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
+index 6a8dfc022d3c..4f7d8818d3f6 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
++++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
+@@ -24,6 +24,8 @@
+ #include <drm/drm_probe_helper.h>
+ #include <drm/drm_vblank.h>
+ 
++#include <uapi/drm/sun4i_drm.h>
++
+ #include "sun4i_drv.h"
+ #include "sun4i_frontend.h"
+ #include "sun4i_framebuffer.h"
+@@ -42,6 +44,27 @@ static int drm_sun4i_gem_dumb_create(struct drm_file *file_priv,
+ 
+ DEFINE_DRM_GEM_DMA_FOPS(sun4i_drv_fops);
+ 
++static int sun4i_gem_create_ioctl(struct drm_device *drm, void *data,
++				  struct drm_file *file_priv)
++{
++	struct drm_sun4i_gem_create *args = data;
++	struct drm_gem_dma_object *dma_obj;
++	size_t size;
++
++	/* The Mali requires a 64 bytes alignment */
++	size = ALIGN(args->size, 64);
++
++	dma_obj = drm_gem_dma_create_with_handle(file_priv, drm, size,
++						 &args->handle);
++
++	return PTR_ERR_OR_ZERO(dma_obj);
++}
++
++static const struct drm_ioctl_desc sun4i_drv_ioctls[] = {
++	DRM_IOCTL_DEF_DRV(SUN4I_GEM_CREATE, sun4i_gem_create_ioctl,
++			  DRM_AUTH),
++};
++
+ static const struct drm_driver sun4i_drv_driver = {
+ 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+ 
+@@ -53,6 +76,10 @@ static const struct drm_driver sun4i_drv_driver = {
+ 	.major			= 1,
+ 	.minor			= 0,
+ 
++	/* Custom ioctls */
++	.ioctls			= sun4i_drv_ioctls,
++	.num_ioctls		= ARRAY_SIZE(sun4i_drv_ioctls),
++
+ 	/* GEM Operations */
+ 	DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(drm_sun4i_gem_dumb_create),
+ };
+diff --git a/include/uapi/drm/sun4i_drm.h b/include/uapi/drm/sun4i_drm.h
+new file mode 100644
+index 000000000000..67b9dd4ee594
+--- /dev/null
++++ b/include/uapi/drm/sun4i_drm.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright (C) 2015 Free Electrons
++ * Copyright (C) 2015 NextThing Co
++ *
++ * Maxime Ripard <maxime.ripard@free-electrons.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef _UAPI_SUN4I_DRM_H_
++#define _UAPI_SUN4I_DRM_H_
++
++#include <drm/drm.h>
++
++struct drm_sun4i_gem_create {
++	__u64 size;
++	__u32 flags;
++	__u32 handle;
++};
++
++#define DRM_SUN4I_GEM_CREATE		0x00
++
++#define DRM_IOCTL_SUN4I_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_SUN4I_GEM_CREATE, \
++						 struct drm_sun4i_gem_create)
++
++#endif
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch
new file mode 100644
index 000000000000..c8f9a9df8cec
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch
@@ -0,0 +1,633 @@
+From 23eafa9ce094c20abcd97137378a581dd76517ce Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 13:07:16 +0300
+Subject: drv:gpu:drm:sun4i: Add HDMI audio sun4i-hdmi encoder
+
+Add HDMI audio support for the sun4i-hdmi encoder, used on
+the older Allwinner chips - A10, A20, A31.
+
+Most of the code is based on the BSP implementation. In it
+dditional formats are supported (S20_3LE and S24_LE), however
+there where some problems with them and only S16_LE is left.
+
+Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
+---
+ drivers/gpu/drm/sun4i/Kconfig            |  11 +
+ drivers/gpu/drm/sun4i/Makefile           |   3 +
+ drivers/gpu/drm/sun4i/sun4i_hdmi.h       |  36 ++
+ drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c | 450 +++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c   |  16 +
+ 5 files changed, 516 insertions(+)
+ create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c
+
+diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
+index 4741d9f6544c..733381869998 100644
+--- a/drivers/gpu/drm/sun4i/Kconfig
++++ b/drivers/gpu/drm/sun4i/Kconfig
+@@ -23,6 +23,17 @@ config DRM_SUN4I_HDMI
+ 	  Choose this option if you have an Allwinner A10/A10s/A20/A31
+ 	  SoC with an HDMI controller.
+ 
++config DRM_SUN4I_HDMI_AUDIO
++	bool "Allwinner A10 HDMI Audio Support"
++	default y
++	depends on DRM_SUN4I_HDMI
++	depends on SND_SOC=y || SND_SOC=DRM_SUN4I_HDMI
++	select SND_PCM_ELD
++	select SND_SOC_GENERIC_DMAENGINE_PCM
++	help
++	  Choose this option if you have an Allwinner SoC with an HDMI
++	  controller and want to use audio.
++
+ config DRM_SUN4I_HDMI_CEC
+ 	bool "Allwinner A10/A10s/A20/A31 HDMI CEC Support"
+ 	depends on DRM_SUN4I_HDMI
+diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
+index bad7497a0d11..5e9dc9370584 100644
+--- a/drivers/gpu/drm/sun4i/Makefile
++++ b/drivers/gpu/drm/sun4i/Makefile
+@@ -5,6 +5,9 @@ sun4i-frontend-y		+= sun4i_frontend.o
+ sun4i-drm-y			+= sun4i_drv.o
+ sun4i-drm-y			+= sun4i_framebuffer.o
+ 
++ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO
++sun4i-drm-hdmi-y		+= sun4i_hdmi_audio.o
++endif
+ sun4i-drm-hdmi-y		+= sun4i_hdmi_ddc_clk.o
+ sun4i-drm-hdmi-y		+= sun4i_hdmi_enc.o
+ sun4i-drm-hdmi-y		+= sun4i_hdmi_i2c.o
+diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+index 65c801cd6f35..2edced4eb5d5 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+@@ -42,7 +42,32 @@
+ #define SUN4I_HDMI_VID_TIMING_POL_VSYNC		BIT(1)
+ #define SUN4I_HDMI_VID_TIMING_POL_HSYNC		BIT(0)
+ 
++#define SUN4I_HDMI_AUDIO_CTRL_REG	0x040
++#define SUN4I_HDMI_AUDIO_CTRL_ENABLE		BIT(31)
++#define SUN4I_HDMI_AUDIO_CTRL_RESET		BIT(30)
++
++#define SUN4I_HDMI_AUDIO_FMT_REG	0x048
++#define SUN4I_HDMI_AUDIO_FMT_SRC		BIT(31)
++#define SUN4I_HDMI_AUDIO_FMT_LAYOUT		BIT(3)
++#define SUN4I_HDMI_AUDIO_FMT_CH_CFG(n)		((n) - 1)
++#define SUN4I_HDMI_AUDIO_FMT_CH_CFG_MASK	GENMASK(2, 0)
++
++#define SUN4I_HDMI_AUDIO_PCM_REG	0x4c
++#define SUN4I_HDMI_AUDIO_PCM_CH_MAP(n, m)	(((m) - 1) << ((n) * 4))
++#define SUN4I_HDMI_AUDIO_PCM_CH_MAP_MASK(n)	(GENMASK(2, 0) << ((n) * 4))
++
++#define SUN4I_HDMI_AUDIO_CTS_REG	0x050
++#define SUN4I_HDMI_AUDIO_CTS(n)			((n) & GENMASK(19, 0))
++
++#define SUN4I_HDMI_AUDIO_N_REG		0x054
++#define SUN4I_HDMI_AUDIO_N(n)			((n) & GENMASK(19, 0))
++
++#define SUN4I_HDMI_AUDIO_STAT0_REG	0x58
++#define SUN4I_HDMI_AUDIO_STAT0_FREQ(n)		((n) << 24)
++#define SUN4I_HDMI_AUDIO_STAT0_FREQ_MASK	GENMASK(27, 24)
++
+ #define SUN4I_HDMI_AVI_INFOFRAME_REG(n)	(0x080 + (n))
++#define SUN4I_HDMI_AUDIO_INFOFRAME_REG(n)	(0x0a0 + (n))
+ 
+ #define SUN4I_HDMI_PAD_CTRL0_REG	0x200
+ #define SUN4I_HDMI_PAD_CTRL0_BIASEN		BIT(31)
+@@ -242,6 +267,11 @@ struct sun4i_hdmi_variant {
+ 	bool			ddc_fifo_has_dir;
+ };
+ 
++struct sun4i_hdmi_audio {
++	struct snd_soc_card		*card;
++	u8				channels;
++};
++
+ struct sun4i_hdmi {
+ 	struct drm_connector	connector;
+ 	struct drm_encoder	encoder;
+@@ -285,6 +315,10 @@ struct sun4i_hdmi {
+ 
+ 	struct sun4i_drv	*drv;
+ 
++	bool			hdmi_audio;
++
++	struct sun4i_hdmi_audio audio;
++
+ 	struct cec_adapter	*cec_adap;
+ 
+ 	const struct sun4i_hdmi_variant	*variant;
+@@ -293,5 +327,7 @@ struct sun4i_hdmi {
+ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
+ int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
+ int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi);
++int sun4i_hdmi_audio_create(struct sun4i_hdmi *hdmi);
++void sun4i_hdmi_audio_destroy(struct sun4i_hdmi *hdmi);
+ 
+ #endif /* _SUN4I_HDMI_H_ */
+diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c
+new file mode 100644
+index 000000000000..a66b6c51947a
+--- /dev/null
++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c
+@@ -0,0 +1,450 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (C) 2020 Olimex Ltd.
++ *   Author: Stefan Mavrodiev <stefan@olimex.com>
++ */
++#include <linux/dma-mapping.h>
++#include <linux/dmaengine.h>
++#include <linux/module.h>
++#include <linux/of_dma.h>
++#include <linux/regmap.h>
++
++#include <drm/drm_print.h>
++
++#include <sound/dmaengine_pcm.h>
++#include <sound/pcm_drm_eld.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++
++#include "sun4i_hdmi.h"
++
++static int sun4i_hdmi_audio_ctl_eld_info(struct snd_kcontrol *kcontrol,
++					 struct snd_ctl_elem_info *uinfo)
++{
++	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
++	uinfo->count = MAX_ELD_BYTES;
++	return 0;
++}
++
++static int sun4i_hdmi_audio_ctl_eld_get(struct snd_kcontrol *kcontrol,
++					struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++	struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
++	struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card);
++
++	memcpy(ucontrol->value.bytes.data,
++	       hdmi->connector.eld,
++	       MAX_ELD_BYTES);
++
++	return 0;
++}
++
++static const struct snd_kcontrol_new sun4i_hdmi_audio_controls[] = {
++	{
++		.access = SNDRV_CTL_ELEM_ACCESS_READ |
++			  SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
++		.name = "ELD",
++		.info = sun4i_hdmi_audio_ctl_eld_info,
++		.get = sun4i_hdmi_audio_ctl_eld_get,
++	},
++};
++
++static const struct snd_soc_dapm_widget sun4i_hdmi_audio_widgets[] = {
++	SND_SOC_DAPM_OUTPUT("TX"),
++};
++
++static const struct snd_soc_dapm_route sun4i_hdmi_audio_routes[] = {
++	{ "TX", NULL, "Playback" },
++};
++
++static const struct snd_soc_component_driver sun4i_hdmi_audio_component = {
++	.controls               = sun4i_hdmi_audio_controls,
++	.num_controls           = ARRAY_SIZE(sun4i_hdmi_audio_controls),
++	.dapm_widgets		= sun4i_hdmi_audio_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(sun4i_hdmi_audio_widgets),
++	.dapm_routes		= sun4i_hdmi_audio_routes,
++	.num_dapm_routes	= ARRAY_SIZE(sun4i_hdmi_audio_routes),
++};
++
++static int sun4i_hdmi_audio_startup(struct snd_pcm_substream *substream,
++				    struct snd_soc_dai *dai)
++{
++	struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
++	struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card);
++	u32 reg;
++	int ret;
++
++	regmap_write(hdmi->regmap, SUN4I_HDMI_AUDIO_CTRL_REG, 0);
++	regmap_write(hdmi->regmap,
++		     SUN4I_HDMI_AUDIO_CTRL_REG,
++		     SUN4I_HDMI_AUDIO_CTRL_RESET);
++	ret = regmap_read_poll_timeout(hdmi->regmap,
++				       SUN4I_HDMI_AUDIO_CTRL_REG,
++				       reg, !reg, 100, 50000);
++	if (ret < 0) {
++		DRM_ERROR("Failed to reset HDMI Audio\n");
++		return ret;
++	}
++
++	regmap_write(hdmi->regmap,
++		     SUN4I_HDMI_AUDIO_CTRL_REG,
++		     SUN4I_HDMI_AUDIO_CTRL_ENABLE);
++
++	return snd_pcm_hw_constraint_eld(substream->runtime,
++					hdmi->connector.eld);
++}
++
++static void sun4i_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
++				      struct snd_soc_dai *dai)
++{
++	struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
++	struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card);
++
++	regmap_write(hdmi->regmap, SUN4I_HDMI_AUDIO_CTRL_REG, 0);
++}
++
++static int sun4i_hdmi_setup_audio_infoframes(struct sun4i_hdmi *hdmi)
++{
++	union hdmi_infoframe frame;
++	u8 buffer[14];
++	int i, ret;
++
++	ret = hdmi_audio_infoframe_init(&frame.audio);
++	if (ret < 0) {
++		DRM_ERROR("Failed to init HDMI audio infoframe\n");
++		return ret;
++	}
++
++	frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
++	frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
++	frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
++	frame.audio.channels = hdmi->audio.channels;
++
++	ret = hdmi_infoframe_pack(&frame, buffer, sizeof(buffer));
++	if (ret < 0) {
++		DRM_ERROR("Failed to pack HDMI audio infoframe\n");
++		return ret;
++	}
++
++	for (i = 0; i < sizeof(buffer); i++)
++		writeb(buffer[i],
++		       hdmi->base + SUN4I_HDMI_AUDIO_INFOFRAME_REG(i));
++
++	return 0;
++}
++
++static void sun4i_hdmi_audio_set_cts_n(struct sun4i_hdmi *hdmi,
++				       struct snd_pcm_hw_params *params)
++{
++	struct drm_encoder *encoder = &hdmi->encoder;
++	struct drm_crtc *crtc = encoder->crtc;
++	const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
++	u32 rate = params_rate(params);
++	u32 n, cts;
++	u64 tmp;
++
++	/**
++	 * Calculate Cycle Time Stamp (CTS) and Numerator (N):
++	 *
++	 * N = 128 * Samplerate / 1000
++	 * CTS = (Ftdms * N) / (128 * Samplerate)
++	 */
++
++	n = 128 * rate / 1000;
++	tmp = (u64)(mode->clock * 1000) * n;
++	do_div(tmp, 128 * rate);
++	cts = tmp;
++
++	regmap_write(hdmi->regmap,
++		     SUN4I_HDMI_AUDIO_CTS_REG,
++		     SUN4I_HDMI_AUDIO_CTS(cts));
++
++	regmap_write(hdmi->regmap,
++		     SUN4I_HDMI_AUDIO_N_REG,
++		     SUN4I_HDMI_AUDIO_N(n));
++}
++
++static int sun4i_hdmi_audio_set_hw_rate(struct sun4i_hdmi *hdmi,
++					struct snd_pcm_hw_params *params)
++{
++	u32 rate = params_rate(params);
++	u32 val;
++
++	switch (rate) {
++	case 44100:
++		val = 0x0;
++		break;
++	case 48000:
++		val = 0x2;
++		break;
++	case 32000:
++		val = 0x3;
++		break;
++	case 88200:
++		val = 0x8;
++		break;
++	case 96000:
++		val = 0x9;
++		break;
++	case 176400:
++		val = 0xc;
++		break;
++	case 192000:
++		val = 0xe;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(hdmi->regmap,
++			   SUN4I_HDMI_AUDIO_STAT0_REG,
++			   SUN4I_HDMI_AUDIO_STAT0_FREQ_MASK,
++			   SUN4I_HDMI_AUDIO_STAT0_FREQ(val));
++
++	return 0;
++}
++
++static int sun4i_hdmi_audio_set_hw_channels(struct sun4i_hdmi *hdmi,
++					    struct snd_pcm_hw_params *params)
++{
++	u32 channels = params_channels(params);
++
++	if (channels > 8)
++		return -EINVAL;
++
++	hdmi->audio.channels = channels;
++
++	regmap_update_bits(hdmi->regmap,
++			   SUN4I_HDMI_AUDIO_FMT_REG,
++			   SUN4I_HDMI_AUDIO_FMT_LAYOUT,
++			   (channels > 2) ? SUN4I_HDMI_AUDIO_FMT_LAYOUT : 0);
++
++	regmap_update_bits(hdmi->regmap,
++			   SUN4I_HDMI_AUDIO_FMT_REG,
++			   SUN4I_HDMI_AUDIO_FMT_CH_CFG_MASK,
++			   SUN4I_HDMI_AUDIO_FMT_CH_CFG(channels));
++
++	regmap_write(hdmi->regmap, SUN4I_HDMI_AUDIO_PCM_REG, 0x76543210);
++
++	/**
++	 * If only one channel is required, send the same sample
++	 * to the sink device as a left and right channel.
++	 */
++	if (channels == 1)
++		regmap_update_bits(hdmi->regmap,
++				   SUN4I_HDMI_AUDIO_PCM_REG,
++				   SUN4I_HDMI_AUDIO_PCM_CH_MAP_MASK(1),
++				   SUN4I_HDMI_AUDIO_PCM_CH_MAP(1, 1));
++
++	return 0;
++}
++
++static int sun4i_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
++				      struct snd_pcm_hw_params *params,
++				      struct snd_soc_dai *dai)
++{
++	struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
++	struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card);
++	int ret;
++
++	ret = sun4i_hdmi_audio_set_hw_rate(hdmi, params);
++	if (ret < 0)
++		return ret;
++
++	ret = sun4i_hdmi_audio_set_hw_channels(hdmi, params);
++	if (ret < 0)
++		return ret;
++
++	sun4i_hdmi_audio_set_cts_n(hdmi, params);
++
++	return 0;
++}
++
++static int sun4i_hdmi_audio_trigger(struct snd_pcm_substream *substream,
++				    int cmd,
++				    struct snd_soc_dai *dai)
++{
++	struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
++	struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card);
++	int ret = 0;
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++		ret = sun4i_hdmi_setup_audio_infoframes(hdmi);
++		break;
++	default:
++		break;
++	}
++
++	return ret;
++}
++
++static int sun4i_hdmi_audio_dai_probe(struct snd_soc_dai *dai)
++{
++	struct snd_dmaengine_dai_dma_data *dma_data;
++
++	dma_data = devm_kzalloc(dai->dev, sizeof(*dma_data), GFP_KERNEL);
++	if (!dma_data)
++		return -ENOMEM;
++
++	dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++	dma_data->maxburst = 8;
++
++	snd_soc_dai_init_dma_data(dai, dma_data, NULL);
++
++	return 0;
++}
++
++static const struct snd_soc_dai_ops sun4i_hdmi_audio_dai_ops = {
++	.probe = sun4i_hdmi_audio_dai_probe,
++	.startup = sun4i_hdmi_audio_startup,
++	.shutdown = sun4i_hdmi_audio_shutdown,
++	.hw_params = sun4i_hdmi_audio_hw_params,
++	.trigger = sun4i_hdmi_audio_trigger,
++};
++
++static struct snd_soc_dai_driver sun4i_hdmi_audio_dai = {
++	.name = "HDMI",
++	.ops = &sun4i_hdmi_audio_dai_ops,
++	.playback = {
++		.stream_name	= "Playback",
++		.channels_min	= 1,
++		.channels_max	= 8,
++		.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		.rates		= SNDRV_PCM_RATE_8000_192000,
++	},
++};
++
++static const struct snd_pcm_hardware sun4i_hdmi_audio_pcm_hardware = {
++	.info			= SNDRV_PCM_INFO_INTERLEAVED |
++				  SNDRV_PCM_INFO_BLOCK_TRANSFER |
++				  SNDRV_PCM_INFO_MMAP |
++				  SNDRV_PCM_INFO_MMAP_VALID |
++				  SNDRV_PCM_INFO_PAUSE |
++				  SNDRV_PCM_INFO_RESUME,
++	.formats		= SNDRV_PCM_FMTBIT_S16_LE,
++	.rates                  = SNDRV_PCM_RATE_8000_192000,
++	.rate_min               = 8000,
++	.rate_max               = 192000,
++	.channels_min           = 1,
++	.channels_max           = 8,
++	.buffer_bytes_max	= 128 * 1024,
++	.period_bytes_min	= 4 * 1024,
++	.period_bytes_max	= 32 * 1024,
++	.periods_min		= 2,
++	.periods_max		= 8,
++	.fifo_size		= 128,
++};
++
++static const struct snd_dmaengine_pcm_config sun4i_hdmi_audio_pcm_config = {
++	.chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-tx",
++	.pcm_hardware = &sun4i_hdmi_audio_pcm_hardware,
++	.prealloc_buffer_size = 128 * 1024,
++	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
++};
++
++struct snd_soc_card sun4i_hdmi_audio_card = {
++	.name = "sun4i-hdmi",
++};
++
++int sun4i_hdmi_audio_create(struct sun4i_hdmi *hdmi)
++{
++	struct snd_soc_card *card = &sun4i_hdmi_audio_card;
++	struct snd_soc_dai_link_component *comp;
++	struct snd_soc_dai_link *link;
++	int ret;
++
++	ret = snd_dmaengine_pcm_register(hdmi->dev,
++					 &sun4i_hdmi_audio_pcm_config, 0);
++	if (ret < 0) {
++		DRM_ERROR("Could not register PCM\n");
++		return ret;
++	}
++
++	ret = snd_soc_register_component(hdmi->dev,
++					 &sun4i_hdmi_audio_component,
++					 &sun4i_hdmi_audio_dai, 1);
++	if (ret < 0) {
++		DRM_ERROR("Could not register DAI\n");
++		goto unregister_pcm;
++	}
++
++	link = devm_kzalloc(hdmi->dev, sizeof(*link), GFP_KERNEL);
++	if (!link) {
++		ret = -ENOMEM;
++		goto unregister_component;
++	}
++
++	comp = devm_kzalloc(hdmi->dev, sizeof(*comp) * 3, GFP_KERNEL);
++	if (!comp) {
++		ret = -ENOMEM;
++		goto unregister_component;
++	}
++
++	link->cpus = &comp[0];
++	link->codecs = &comp[1];
++	link->platforms = &comp[2];
++
++	link->num_cpus = 1;
++	link->num_codecs = 1;
++	link->num_platforms = 1;
++
++	link->playback_only = 1;
++
++	link->name = "SUN4I-HDMI";
++	link->stream_name = "SUN4I-HDMI PCM";
++
++	link->codecs->name = dev_name(hdmi->dev);
++	link->codecs->dai_name	= sun4i_hdmi_audio_dai.name;
++
++	link->cpus->dai_name = dev_name(hdmi->dev);
++
++	link->platforms->name = dev_name(hdmi->dev);
++
++	link->dai_fmt = SND_SOC_DAIFMT_I2S;
++
++	card->dai_link = link;
++	card->num_links = 1;
++	card->dev = hdmi->dev;
++
++	hdmi->audio.card = card;
++
++	/**
++	 * snd_soc_register_card() will overwrite the driver_data pointer.
++	 * So before registering the card, store the original pointer in
++	 * card->drvdata.
++	 */
++	snd_soc_card_set_drvdata(card, hdmi);
++	ret = snd_soc_register_card(card);
++	if (ret)
++		goto unregister_component;
++
++	return 0;
++
++unregister_component:
++	snd_soc_unregister_component(hdmi->dev);
++unregister_pcm:
++	snd_dmaengine_pcm_unregister(hdmi->dev);
++	return ret;
++}
++
++void sun4i_hdmi_audio_destroy(struct sun4i_hdmi *hdmi)
++{
++	struct snd_soc_card *card = hdmi->audio.card;
++	void *data;
++
++	/**
++	 * Before removing the card, restore the previously stored driver_data.
++	 * This will ensure proper removal of the sun4i-hdmi module, since it
++	 * uses dev_get_drvdata() in the unbind function.
++	 */
++	data = snd_soc_card_get_drvdata(card);
++
++	snd_soc_unregister_card(card);
++	snd_soc_unregister_component(hdmi->dev);
++	snd_dmaengine_pcm_unregister(hdmi->dev);
++
++	dev_set_drvdata(hdmi->dev, data);
++}
+diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+index bae69d696765..45a13164b99d 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+@@ -26,6 +26,8 @@
+ #include <drm/drm_probe_helper.h>
+ #include <drm/drm_simple_kms_helper.h>
+ 
++#include <sound/soc.h>
++
+ #include "sun4i_backend.h"
+ #include "sun4i_crtc.h"
+ #include "sun4i_drv.h"
+@@ -71,6 +73,11 @@ static void sun4i_hdmi_disable(struct drm_encoder *encoder,
+ 
+ 	DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
+ 
++#ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO
++	if (hdmi->hdmi_audio)
++		sun4i_hdmi_audio_destroy(hdmi);
++#endif
++
+ 	val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
+ 	val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
+ 	writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
+@@ -153,6 +160,11 @@ static void sun4i_hdmi_enable(struct drm_encoder *encoder,
+ 		val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
+ 
+ 	writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
++
++#ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO
++	if (hdmi->hdmi_audio && sun4i_hdmi_audio_create(hdmi))
++		DRM_ERROR("Couldn't create the HDMI audio adapter\n");
++#endif
+ }
+ 
+ static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
+@@ -221,6 +233,10 @@ static int sun4i_hdmi_get_modes(struct drm_connector *connector)
+ 	if (!edid)
+ 		return 0;
+ 
++#ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO
++	hdmi->hdmi_audio = drm_detect_monitor_audio(edid);
++#endif
++
+ 	DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
+ 			 connector->display_info.is_hdmi ? "an HDMI" : "a DVI");
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch
new file mode 100644
index 000000000000..c40405a0ea95
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch
@@ -0,0 +1,42 @@
+From cace2d3b68ecf65eeda52ff4bc9c23ca11b0b06f Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:37:03 +0300
+Subject: drv:gpu:drm:sun4i:sun8i_mixer.c add h3 mixer1
+
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index eb55798c200d..8aabc78c0223 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -706,6 +706,14 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+ 	.vi_num		= 1,
+ };
+ 
++static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
++	.ccsc		= CCSC_MIXER1_LAYOUT,
++	.mod_rate	= 432000000,
++	.scaler_mask	= 0xf,
++	.ui_num		= 3,
++	.vi_num		= 1,
++};
++
+ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
+ 	.ccsc		= CCSC_MIXER0_LAYOUT,
+ 	.mod_rate	= 297000000,
+@@ -792,6 +800,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
+ 		.compatible = "allwinner,sun8i-h3-de2-mixer-0",
+ 		.data = &sun8i_h3_mixer0_cfg,
+ 	},
++	{
++		.compatible = "allwinner,sun8i-h3-de2-mixer-1",
++		.data = &sun8i_h3_mixer1_cfg,
++	},
+ 	{
+ 		.compatible = "allwinner,sun8i-r40-de2-mixer-0",
+ 		.data = &sun8i_r40_mixer0_cfg,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch
new file mode 100644
index 000000000000..548ea88845b9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch
@@ -0,0 +1,168 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Mitko Gamishev <hehopmajieh@debian.bg>
+Date: Wed, 5 Feb 2020 14:57:10 +0200
+Subject: drv:iio:adc:axp20x_adc arm64:dts:axp803 hwmon enable thermal
+
+---
+ arch/arm64/boot/dts/allwinner/axp803.dtsi |  1 +
+ drivers/iio/adc/axp20x_adc.c              | 88 ++++++++++
+ 2 files changed, 89 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi
+index a6b4b87f185d..422be59f5d88 100644
+--- a/arch/arm64/boot/dts/allwinner/axp803.dtsi
++++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
+@@ -19,6 +19,7 @@ ac_power_supply: ac-power {
+ 	axp_adc: adc {
+ 		compatible = "x-powers,axp803-adc", "x-powers,axp813-adc";
+ 		#io-channel-cells = <1>;
++		#thermal-sensor-cells = <0>;
+ 	};
+ 
+ 	axp_gpio: gpio {
+diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
+index 83e228980ad5..1c6978037513 100644
+--- a/drivers/iio/adc/axp20x_adc.c
++++ b/drivers/iio/adc/axp20x_adc.c
+@@ -7,6 +7,7 @@
+ 
+ #include <linux/bitfield.h>
+ #include <linux/completion.h>
++#include <linux/hwmon.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+@@ -619,6 +620,74 @@ static int axp813_adc_rate(struct axp20x_adc_iio *info, int rate)
+ 				 AXP813_ADC_RATE_HZ(rate));
+ }
+ 
++
++static umode_t axp813_adc_hwmon_is_visible(const void *data,
++					   enum hwmon_sensor_types type,
++					   u32 attr, int channel)
++{
++	return (type == hwmon_temp && attr == hwmon_temp_input) ? 0444 : 0;
++}
++
++static int axp813_adc_hwmon_read(struct device *dev,
++				 enum hwmon_sensor_types type,
++				 u32 attr, int channel, long *temp)
++{
++	struct axp20x_adc_iio *info = dev_get_drvdata(dev);
++	int ret;
++	int raw;
++
++	switch (attr) {
++		case hwmon_temp_input:
++		raw = axp20x_read_variable_width(info->regmap, AXP22X_PMIC_TEMP_H, 12);
++		*temp = (raw - 2667) * 100;
++		ret = 0;
++		break;
++	default:
++		ret = -EOPNOTSUPP;
++		break;
++	}
++
++	return ret;
++}
++
++static u32 axp813_adc_hwmon_chip_config[] = {
++	HWMON_C_REGISTER_TZ,
++	0
++};
++
++static const struct hwmon_channel_info axp813_adc_hwmon_chip = {
++	.type = hwmon_chip,
++	.config = axp813_adc_hwmon_chip_config,
++};
++
++static u32 axp813_adc_hwmon_temp_config[] = {
++	HWMON_T_INPUT,
++	0
++};
++
++
++static const struct hwmon_channel_info axp813_adc_hwmon_temp = {
++	.type = hwmon_temp,
++	.config = axp813_adc_hwmon_temp_config,
++};
++
++
++static const struct hwmon_channel_info *axp813_adc_hwmon_info[] = {
++	&axp813_adc_hwmon_chip,
++	&axp813_adc_hwmon_temp,
++	NULL
++};
++
++static const struct hwmon_ops axp813_adc_hwmon_hwmon_ops = {
++	.is_visible = axp813_adc_hwmon_is_visible,
++	.read = axp813_adc_hwmon_read,
++};
++
++static const struct hwmon_chip_info axp813_adc_hwmon_chip_info = {
++	.ops = &axp813_adc_hwmon_hwmon_ops,
++	.info = axp813_adc_hwmon_info,
++};
++
+ struct axp_data {
+ 	const struct iio_info		*iio_info;
+ 	int				num_channels;
+@@ -627,6 +696,7 @@ struct axp_data {
+ 	unsigned long			adc_en2_mask;
+ 	int				(*adc_rate)(struct axp20x_adc_iio *info,
+ 						    int rate);
++	bool				hwmon_en;
+ 	struct iio_map			*maps;
+ };
+ 
+@@ -637,6 +707,7 @@ static const struct axp_data axp20x_data = {
+ 	.adc_en1_mask = AXP20X_ADC_EN1_MASK,
+ 	.adc_en2_mask = AXP20X_ADC_EN2_MASK,
+ 	.adc_rate = axp20x_adc_rate,
++	.hwmon_en = false,
+ 	.maps = axp20x_maps,
+ };
+ 
+@@ -646,6 +717,7 @@ static const struct axp_data axp22x_data = {
+ 	.channels = axp22x_adc_channels,
+ 	.adc_en1_mask = AXP22X_ADC_EN1_MASK,
+ 	.adc_rate = axp22x_adc_rate,
++	.hwmon_en = false,
+ 	.maps = axp22x_maps,
+ };
+ 
+@@ -655,6 +727,7 @@ static const struct axp_data axp813_data = {
+ 	.channels = axp813_adc_channels,
+ 	.adc_en1_mask = AXP22X_ADC_EN1_MASK,
+ 	.adc_rate = axp813_adc_rate,
++	.hwmon_en = true,
+ 	.maps = axp22x_maps,
+ };
+ 
+@@ -737,8 +810,23 @@ static int axp20x_probe(struct platform_device *pdev)
+ 		goto fail_register;
+ 	}
+ 
++	if (info->data->hwmon_en) {
++		/* Register hwmon device */
++		struct device *hwmon_dev;
++
++		hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, "axp813_adc", info, &axp813_adc_hwmon_chip_info, NULL);
++		if (IS_ERR(hwmon_dev)) {
++			ret = PTR_ERR(hwmon_dev);
++			dev_err(&pdev->dev, "unable to register hwmon device %d\n", ret);
++			goto fail_hwmon;
++		}
++	}
++
+ 	return 0;
+ 
++fail_hwmon:
++	iio_device_unregister(indio_dev);
++
+ fail_register:
+ 	iio_map_array_unregister(indio_dev);
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch
new file mode 100644
index 000000000000..37f5425b017b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch
@@ -0,0 +1,63 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Mitko Gamishev <hehopmajieh@debian.bg>
+Date: Wed, 5 Feb 2020 15:18:04 +0200
+Subject: drv:input:touchscreen:sun4i-ts Enable parsing
+
+---
+ drivers/input/touchscreen/sun4i-ts.c | 19 ++++++++--
+ 1 file changed, 15 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/input/touchscreen/sun4i-ts.c b/drivers/input/touchscreen/sun4i-ts.c
+index bb3c6072fc82..9092286aa7dd 100644
+--- a/drivers/input/touchscreen/sun4i-ts.c
++++ b/drivers/input/touchscreen/sun4i-ts.c
+@@ -32,6 +32,7 @@
+ #include <linux/thermal.h>
+ #include <linux/init.h>
+ #include <linux/input.h>
++#include <linux/input/touchscreen.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+@@ -106,6 +107,7 @@
+ struct sun4i_ts_data {
+ 	struct device *dev;
+ 	struct input_dev *input;
++	struct touchscreen_properties prop;
+ 	void __iomem *base;
+ 	unsigned int irq;
+ 	bool ignore_fifo_data;
+@@ -123,8 +125,8 @@ static void sun4i_ts_irq_handle_input(struct sun4i_ts_data *ts, u32 reg_val)
+ 		y = readl(ts->base + TP_DATA);
+ 		/* The 1st location reported after an up event is unreliable */
+ 		if (!ts->ignore_fifo_data) {
+-			input_report_abs(ts->input, ABS_X, x);
+-			input_report_abs(ts->input, ABS_Y, y);
++			touchscreen_report_pos(ts->input, &ts->prop, x, y, false);
++
+ 			/*
+ 			 * The hardware has a separate down status bit, but
+ 			 * that gets set before we get the first location,
+@@ -296,8 +298,17 @@ static int sun4i_ts_probe(struct platform_device *pdev)
+ 		ts->input->id.version = 0x0100;
+ 		ts->input->evbit[0] =  BIT(EV_SYN) | BIT(EV_KEY) | BIT(EV_ABS);
+ 		__set_bit(BTN_TOUCH, ts->input->keybit);
+-		input_set_abs_params(ts->input, ABS_X, 0, 4095, 0, 0);
+-		input_set_abs_params(ts->input, ABS_Y, 0, 4095, 0, 0);
++
++		touchscreen_parse_properties(ts->input, false, &ts->prop);
++
++		if (!ts->prop.max_x || !ts->prop.max_y) {
++			dev_info(&pdev->dev, "Invalid configuration, using defaults\n");
++			ts->prop.max_x = 4095;
++			ts->prop.max_y = 4095;
++		}
++
++		input_set_abs_params(ts->input, ABS_X, 0, ts->prop.max_x, 0, 0);
++		input_set_abs_params(ts->input, ABS_Y, 0, ts->prop.max_y, 0, 0);
+ 		input_set_drvdata(ts->input, ts);
+ 	}
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch
new file mode 100644
index 000000000000..186dec2a4753
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Koumes <koumes@centrum.cz>
+Date: Sat, 1 Jun 2019 21:20:26 +0000
+Subject: drv:media:dvb-frontends:si2168: fix cmd timeout
+
+Some demuxer si2168 commands may take 130-140 ms.
+(DVB-T/T2 tuner MyGica T230C v2).
+Details: https://github.com/CoreELEC/CoreELEC/pull/208
+---
+ drivers/media/dvb-frontends/si2168.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/dvb-frontends/si2168.c b/drivers/media/dvb-frontends/si2168.c
+index dae1f2153e8b..cd44523f46a8 100644
+--- a/drivers/media/dvb-frontends/si2168.c
++++ b/drivers/media/dvb-frontends/si2168.c
+@@ -40,7 +40,7 @@ static int si2168_cmd_execute(struct i2c_client *client, struct si2168_cmd *cmd)
+ 
+ 	if (cmd->rlen) {
+ 		/* wait cmd execution terminate */
+-		#define TIMEOUT 70
++		#define TIMEOUT 200
+ 		timeout = jiffies + msecs_to_jiffies(TIMEOUT);
+ 		while (!time_after(jiffies, timeout)) {
+ 			ret = i2c_master_recv(client, cmd->args, cmd->rlen);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch
new file mode 100644
index 000000000000..edbd0cc2b2ac
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch
@@ -0,0 +1,658 @@
+From a9a14990250d540ab76315a94450bac322ed3e1f Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 21:38:26 +0300
+Subject: drv:mfd:axp20x add sysfs interface
+
+---
+ drivers/mfd/axp20x.c | 614 +++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 614 insertions(+)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index 352e11e48a28..b0b099023c39 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -83,6 +83,7 @@ static const struct regmap_range axp20x_volatile_ranges[] = {
+ 	regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
+ 	regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
+ 	regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
++	regmap_reg_range(AXP20X_CHRG_CC_31_24, AXP20X_DISCHRG_CC_7_0),
+ 	regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
+ };
+ 
+@@ -1172,6 +1173,611 @@ static int axp20x_power_off(struct sys_off_data *data)
+ 	return NOTIFY_DONE;
+ }
+ 
++#define kobj_to_device(x) container_of(x, struct device, kobj)
++
++int axp20x_get_adc_freq(struct axp20x_dev *axp)
++{
++	unsigned int res;
++	int ret, freq = 25;
++
++	ret = regmap_read(axp->regmap, AXP20X_ADC_RATE, &res);
++	if (ret < 0) {
++		dev_warn(axp->dev, "Unable to read ADC sampling frequency: %d\n", ret);
++		return freq;
++	}
++	switch ((res & 0xC0) >> 6) {
++	case 0:
++		freq = 25;
++		break;
++	case 1:
++		freq = 50;
++		break;
++	case 2:
++		freq = 100;
++		break;
++	case 3:
++		freq = 200;
++		break;
++	}
++	return freq;
++}
++
++static ssize_t axp20x_sysfs_read_bin_file(struct file *filp,
++				struct kobject *kobj,
++				struct bin_attribute *bin_attr,
++				char *buf, loff_t off, size_t count)
++{
++	int ret;
++
++	struct device *dev = kobj_to_device(kobj);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	ret = regmap_raw_read(axp->regmap, AXP20X_OCV(off), buf, count);
++	if (ret < 0)
++	{
++		dev_warn(axp->dev, "read_bin_file: error reading: %d\n", ret);
++		return ret;
++	}
++	return count;
++}
++
++static ssize_t axp20x_sysfs_write_bin_file(struct file *filp,
++				struct kobject *kobj,
++				struct bin_attribute *bin_attr,
++				char *buf, loff_t off, size_t count)
++{
++	int ret;
++
++	struct device *dev = kobj_to_device(kobj);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	ret = regmap_raw_write(axp->regmap, AXP20X_OCV(off), buf, count);
++	if (ret < 0)
++	{
++		dev_warn(axp->dev, "write_bin_file: error writing: %d\n", ret);
++		return ret;
++	}
++	return count;
++}
++
++static ssize_t axp20x_read_special(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	int i, freq, ret = 0;
++	unsigned int res;
++	u32 lval1, lval2;
++	s64 llval;
++	u64 ullval;
++
++	const char *subsystem = kobject_name(kobj);
++	struct device *dev = kobj_to_device(kobj->parent);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	dev_dbg(axp->dev, "read_special: reading attribute %s of object %s\n", attr->attr.name, subsystem);
++
++	if (strcmp(subsystem, "battery") == 0) {
++		if (strcmp(attr->attr.name, "power") == 0) {
++			lval1 = 0;
++			for (i = 0; i < 3; i++) {
++				ret |= regmap_read(axp->regmap, AXP20X_PWR_BATT_H + i, &res);
++				lval1 |= res << ((2 - i) * 8);
++			}
++			llval = lval1 * 1100 / 1000;
++		} else if (strcmp(attr->attr.name, "charge") == 0) {
++			ret = regmap_raw_read(axp->regmap, AXP20X_CHRG_CC_31_24, &lval1, sizeof(lval1));
++			ret |= regmap_raw_read(axp->regmap, AXP20X_DISCHRG_CC_31_24, &lval2, sizeof(lval2));
++			be32_to_cpus(&lval1);
++			be32_to_cpus(&lval2);
++			ullval = abs((s64)lval1 - (s64)lval2) * 65536 * 500;
++			freq = axp20x_get_adc_freq(axp);
++			do_div(ullval, 3600 * freq);
++			llval = (lval1 < lval2) ? -ullval : ullval;
++		} else if (strcmp(attr->attr.name, "capacity") == 0) {
++			ret = regmap_read(axp->regmap, AXP20X_FG_RES, &res);
++			llval = res & 0x7f;
++		} else
++			return -EINVAL;
++	} else
++		return -EINVAL;
++
++	if (ret < 0) {
++		dev_warn(axp->dev, "Unable to read parameter: %d\n", ret);
++		return ret;
++	}
++	return sprintf(buf, "%lld\n", llval);
++}
++
++static ssize_t axp20x_write_int(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	int reg, var, ret = 0, scale, width = 12, offset = 0;
++	unsigned int res;
++
++	const char *subsystem = kobject_name(kobj);
++	struct device *dev = kobj_to_device(kobj->parent);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	dev_dbg(axp->dev, "write_int: writing attribute %s of object %s\n", attr->attr.name, subsystem);
++
++	ret = kstrtoint(buf, 10, &var);
++	if (ret < 0)
++		return ret;
++
++	if (strcmp(subsystem, "control") == 0) {
++		if (strcmp(attr->attr.name, "battery_rdc") == 0) {
++			reg = AXP20X_RDC_H;
++			scale = 1074;
++			width = 13;
++			offset = 537;
++			/* TODO: Disable & enable fuel gauge */
++		} else
++			return -EINVAL;
++	} else
++		return -EINVAL;
++
++	res = (var + offset) / scale;
++
++	ret = regmap_write_bits(axp->regmap, reg, (1U << (width - 8)) - 1, (res >> 8) & 0xFF);
++	ret |= regmap_write_bits(axp->regmap, reg + 1, 0xFF, res & 0xFF);
++
++	if (ret < 0) {
++		dev_warn(axp->dev, "Unable to write parameter: %d\n", ret);
++		return ret;
++	}
++	return count;
++}
++
++static ssize_t axp20x_read_bool(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	int val, ret, reg, bit;
++	unsigned int res;
++
++	const char *subsystem = kobject_name(kobj);
++	struct device *dev = kobj_to_device(kobj->parent);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	dev_dbg(axp->dev, "read_bool: reading attribute %s of object %s\n", attr->attr.name, subsystem);
++
++	if (strcmp(subsystem, "ac") == 0) {
++		if (strcmp(attr->attr.name, "connected") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 7;
++		} else if (strcmp(attr->attr.name, "used") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 6;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "vbus") == 0) {
++		if (strcmp(attr->attr.name, "connected") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 5;
++		} else if (strcmp(attr->attr.name, "used") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 4;
++		} else if (strcmp(attr->attr.name, "strong") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 3;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "battery") == 0) {
++		if (strcmp(attr->attr.name, "connected") == 0) {
++			reg = AXP20X_PWR_OP_MODE;
++			bit = 5;
++		} else if (strcmp(attr->attr.name, "charging") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 2;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "pmu") == 0) {
++		if (strcmp(attr->attr.name, "overheat") == 0) {
++			reg = AXP20X_PWR_OP_MODE;
++			bit = 7;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "charger") == 0) {
++		if (strcmp(attr->attr.name, "charging") == 0) {
++			reg = AXP20X_PWR_OP_MODE;
++			bit = 6;
++		} else if (strcmp(attr->attr.name, "cell_activation") == 0) {
++			reg = AXP20X_PWR_OP_MODE;
++			bit = 3;
++		} else if (strcmp(attr->attr.name, "low_power") == 0) {
++			reg = AXP20X_PWR_OP_MODE;
++			bit = 2;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "control") == 0) {
++		if (strcmp(attr->attr.name, "set_vbus_direct_mode") == 0) {
++			reg = AXP20X_VBUS_IPSOUT_MGMT;
++			bit = 6;
++		} else if (strcmp(attr->attr.name, "reset_charge_counter") == 0) {
++			reg = AXP20X_CC_CTRL;
++			bit = 5;
++		} else if (strcmp(attr->attr.name, "charge_rtc_battery") == 0) {
++			reg = AXP20X_CHRG_BAK_CTRL;
++			bit = 7;
++		} else if (strcmp(attr->attr.name, "disable_fuel_gauge") == 0) {
++			reg = AXP20X_FG_RES;
++			bit = 7;
++		} else
++			return -EINVAL;
++	} else
++		return -EINVAL;
++
++	ret = regmap_read(axp->regmap, reg, &res);
++	if (ret < 0) {
++		dev_warn(axp->dev, "Unable to read parameter: %d\n", ret);
++		return ret;
++	}
++	val = (res & BIT(bit)) == BIT(bit) ? 1 : 0;
++	return sprintf(buf, "%d\n", val);
++}
++
++static ssize_t axp20x_write_bool(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	int var, ret, reg, bit;
++
++	const char *subsystem = kobject_name(kobj);
++	struct device *dev = kobj_to_device(kobj->parent);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	dev_dbg(axp->dev, "write_bool: writing attribute %s of object %s", attr->attr.name, subsystem);
++
++	ret = kstrtoint(buf, 10, &var);
++	if (ret < 0)
++		return ret;
++
++	if (strcmp(subsystem, "control") == 0) {
++		if (strcmp(attr->attr.name, "set_vbus_direct_mode") == 0) {
++			reg = AXP20X_VBUS_IPSOUT_MGMT;
++			bit = 6;
++		} else if (strcmp(attr->attr.name, "reset_charge_counter") == 0) {
++			reg = AXP20X_CC_CTRL;
++			bit = 5;
++		} else if (strcmp(attr->attr.name, "charge_rtc_battery") == 0) {
++			reg = AXP20X_CHRG_BAK_CTRL;
++			bit = 7;
++		} else if (strcmp(attr->attr.name, "disable_fuel_gauge") == 0) {
++			reg = AXP20X_FG_RES;
++			bit = 7;
++		} else
++			return -EINVAL;
++	} else
++		return -EINVAL;
++
++	ret = regmap_update_bits(axp->regmap, reg, BIT(bit), var ? BIT(bit) : 0);
++	if (ret)
++		dev_warn(axp->dev, "Unable to write value: %d", ret);
++	return count;
++}
++
++static int axp20x_averaging_helper(struct regmap *reg_map, int reg_h,
++	int width)
++{
++	long acc = 0;
++	int ret, i;
++
++	for (i = 0; i < 3; i++) {
++		ret = axp20x_read_variable_width(reg_map, reg_h, width);
++		if (ret < 0)
++			return ret;
++		acc += ret;
++		msleep(20); /* For 100Hz sampling frequency */
++	}
++	return (int)(acc / 3);
++}
++
++static ssize_t axp20x_read_int(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	int val, ret, scale, reg, width = 12, offset = 0;
++
++	const char *subsystem = kobject_name(kobj);
++	struct device *dev = kobj_to_device(kobj->parent);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	dev_dbg(axp->dev, "read_int: reading attribute %s of object %s\n", attr->attr.name, subsystem);
++
++	if (strcmp(subsystem, "ac") == 0) {
++		if (strcmp(attr->attr.name, "voltage") == 0) {
++			reg = AXP20X_ACIN_V_ADC_H;
++			scale = 1700;
++		} else if (strcmp(attr->attr.name, "amperage") == 0) {
++			reg = AXP20X_ACIN_I_ADC_H;
++			scale = 625;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "vbus") == 0) {
++		if (strcmp(attr->attr.name, "voltage") == 0) {
++			reg = AXP20X_VBUS_V_ADC_H;
++			scale = 1700;
++		} else if (strcmp(attr->attr.name, "amperage") == 0) {
++			reg = AXP20X_VBUS_I_ADC_H;
++			scale = 375;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "battery") == 0) {
++		if (strcmp(attr->attr.name, "voltage") == 0) {
++			reg = AXP20X_BATT_V_H;
++			scale = 1100;
++		} else if (strcmp(attr->attr.name, "amperage") == 0) {
++			reg = AXP20X_BATT_DISCHRG_I_H;
++			scale = 500;
++			width = 13;
++		} else if (strcmp(attr->attr.name, "ts_voltage") == 0) {
++			reg = AXP20X_TS_IN_H;
++			scale = 800;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "pmu") == 0) {
++		if (strcmp(attr->attr.name, "temp") == 0) {
++			reg = AXP20X_TEMP_ADC_H;
++			scale = 100;
++			offset = 144700;
++		} else if (strcmp(attr->attr.name, "voltage") == 0) {
++			reg = AXP20X_IPSOUT_V_HIGH_H;
++			scale = 1400;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "charger") == 0) {
++		if (strcmp(attr->attr.name, "amperage") == 0) {
++			reg = AXP20X_BATT_CHRG_I_H;
++			scale = 500;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "control") == 0) {
++		if (strcmp(attr->attr.name, "battery_rdc") == 0) {
++			reg = AXP20X_RDC_H;
++			width = 13;
++			scale = 1074;
++			offset = 537;
++		} else
++			return -EINVAL;
++	} else
++		return -EINVAL;
++
++	ret = axp20x_averaging_helper(axp->regmap, reg, width);
++
++	if (ret < 0) {
++		dev_warn(axp->dev, "Unable to read parameter: %d\n", ret);
++		return ret;
++	}
++	val = ret * scale - offset;
++	return sprintf(buf, "%d\n", val);
++}
++
++/* AC IN */
++static struct kobj_attribute ac_in_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute ac_in_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute ac_in_connected = __ATTR(connected, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute ac_in_used = __ATTR(used, S_IRUGO, axp20x_read_bool, NULL);
++
++static struct attribute *axp20x_attributes_ac[] = {
++	&ac_in_voltage.attr,
++	&ac_in_amperage.attr,
++	&ac_in_connected.attr,
++	&ac_in_used.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_ac = {
++	.attrs = axp20x_attributes_ac,
++};
++
++/* Vbus */
++static struct kobj_attribute vbus_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute vbus_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute vbus_connected = __ATTR(connected, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute vbus_used = __ATTR(used, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute vbus_strong = __ATTR(strong, S_IRUGO, axp20x_read_bool, NULL);
++
++static struct attribute *axp20x_attributes_vbus[] = {
++	&vbus_voltage.attr,
++	&vbus_amperage.attr,
++	&vbus_connected.attr,
++	&vbus_used.attr,
++	&vbus_strong.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_vbus = {
++	.attrs = axp20x_attributes_vbus,
++};
++
++/* Battery */
++static struct kobj_attribute batt_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute batt_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute batt_ts_voltage = __ATTR(ts_voltage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute batt_power = __ATTR(power, S_IRUGO, axp20x_read_special, NULL);
++static struct kobj_attribute batt_charge = __ATTR(charge, S_IRUGO, axp20x_read_special, NULL);
++static struct kobj_attribute batt_capacity = __ATTR(capacity, S_IRUGO, axp20x_read_special, NULL);
++static struct kobj_attribute batt_connected = __ATTR(connected, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute batt_charging = __ATTR(charging, S_IRUGO, axp20x_read_bool, NULL);
++
++static struct attribute *axp20x_attributes_battery[] = {
++	&batt_voltage.attr,
++	&batt_amperage.attr,
++	&batt_ts_voltage.attr,
++	&batt_power.attr,
++	&batt_charge.attr,
++	&batt_capacity.attr,
++	&batt_connected.attr,
++	&batt_charging.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_battery = {
++	.attrs = axp20x_attributes_battery,
++};
++
++/* PMU */
++static struct kobj_attribute pmu_temp = __ATTR(temp, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute pmu_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute pmu_overheat = __ATTR(overheat, S_IRUGO, axp20x_read_bool, NULL);
++
++static struct attribute *axp20x_attributes_pmu[] = {
++	&pmu_temp.attr,
++	&pmu_voltage.attr,
++	&pmu_overheat.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_pmu = {
++	.attrs = axp20x_attributes_pmu,
++};
++
++/* Charger */
++static struct kobj_attribute charger_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute charger_charging = __ATTR(charging, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute charger_cell_activation = __ATTR(cell_activation, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute charger_low_power = __ATTR(low_power, S_IRUGO, axp20x_read_bool, NULL);
++
++static struct attribute *axp20x_attributes_charger[] = {
++	&charger_amperage.attr,
++	&charger_charging.attr,
++	&charger_cell_activation.attr,
++	&charger_low_power.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_charger = {
++	.attrs = axp20x_attributes_charger,
++};
++
++/* Control (writeable) */
++static struct kobj_attribute control_vbus_direct_mode = __ATTR(set_vbus_direct_mode, (S_IRUGO | S_IWUSR),
++	axp20x_read_bool, axp20x_write_bool);
++static struct kobj_attribute control_reset_charge_counter = __ATTR(reset_charge_counter, (S_IRUGO | S_IWUSR),
++	axp20x_read_bool, axp20x_write_bool);
++static struct kobj_attribute control_charge_rtc_battery = __ATTR(charge_rtc_battery, (S_IRUGO | S_IWUSR),
++	axp20x_read_bool, axp20x_write_bool);
++static struct kobj_attribute control_disable_fuel_gauge = __ATTR(disable_fuel_gauge, (S_IRUGO | S_IWUSR),
++	axp20x_read_bool, axp20x_write_bool);
++static struct kobj_attribute control_battery_rdc = __ATTR(battery_rdc, (S_IRUGO | S_IWUSR),
++	axp20x_read_int, axp20x_write_int);
++
++static struct attribute *axp20x_attributes_control[] = {
++	&control_vbus_direct_mode.attr,
++	&control_reset_charge_counter.attr,
++	&control_charge_rtc_battery.attr,
++	&control_disable_fuel_gauge.attr,
++	&control_battery_rdc.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_control = {
++	.attrs = axp20x_attributes_control,
++};
++
++static struct {
++	struct kobject *ac;
++	struct kobject *vbus;
++	struct kobject *battery;
++	struct kobject *pmu;
++	struct kobject *charger;
++	struct kobject *control;
++} subsystems;
++
++static struct bin_attribute axp20x_ocv_curve = __BIN_ATTR(ocv_curve, S_IRUGO | S_IWUSR,
++	axp20x_sysfs_read_bin_file, axp20x_sysfs_write_bin_file, AXP20X_OCV_MAX + 1);
++
++static void axp20x_sysfs_create_subgroup(const char name[], struct axp20x_dev *axp,
++	struct kobject *subgroup, const struct attribute_group *attrs)
++{
++	int ret;
++	struct kobject *parent = &axp->dev->kobj;
++	subgroup = kobject_create_and_add(name, parent);
++	if (subgroup != NULL) {
++		ret = sysfs_create_group(subgroup, attrs);
++		if (ret) {
++			dev_warn(axp->dev, "Unable to register sysfs group: %s: %d", name, ret);
++			kobject_put(subgroup);
++		}
++	}
++}
++
++static void axp20x_sysfs_remove_subgroup(struct kobject *subgroup,
++	const struct attribute_group *attrs)
++{
++	sysfs_remove_group(subgroup, attrs);
++	kobject_put(subgroup);
++}
++
++static int axp20x_sysfs_init(struct axp20x_dev *axp)
++{
++	int ret;
++	unsigned int res;
++
++	/* Enable all ADC channels in the first register */
++	ret = regmap_write(axp->regmap, AXP20X_ADC_EN1, 0xFF);
++	if (ret)
++		dev_warn(axp->dev, "Unable to enable ADC: %d", ret);
++
++	/*
++	 * Set ADC sampling frequency to 100Hz (default is 25)
++	 * Always measure battery temperature (default: only when charging)
++	 */
++	ret = regmap_update_bits(axp->regmap, AXP20X_ADC_RATE, 0xC3, 0x82);
++	if (ret)
++		dev_warn(axp->dev, "Unable to set ADC frequency and TS current output: %d", ret);
++
++	/* Enable fuel gauge and charge counter */
++	ret = regmap_update_bits(axp->regmap, AXP20X_FG_RES, 0x80, 0x00);
++	if (ret)
++		dev_warn(axp->dev, "Unable to enable battery fuel gauge: %d", ret);
++	/* ret = regmap_update_bits(axp->regmap, AXP20X_CC_CTRL, 0xC0, 0x00); */
++	ret |= regmap_update_bits(axp->regmap, AXP20X_CC_CTRL, 0xC0, 0x80);
++	if (ret)
++		dev_warn(axp->dev, "Unable to enable battery charge counter: %d", ret);
++
++	/* Enable battery detection */
++	ret = regmap_read(axp->regmap, AXP20X_OFF_CTRL, &res);
++	if (ret == 0) {
++		if ((res & 0x40) != 0x40) {
++			dev_info(axp->dev, "Battery detection is disabled, enabling");
++			ret = regmap_update_bits(axp->regmap, AXP20X_OFF_CTRL, 0x40, 0x40);
++			if (ret)
++				dev_warn(axp->dev, "Unable to enable battery detection: %d", ret);
++		}
++	} else
++		dev_warn(axp->dev, "Unable to read register AXP20X_OFF_CTRL: %d", ret);
++
++	/* Get info about backup (RTC) battery */
++	ret = regmap_read(axp->regmap, AXP20X_CHRG_BAK_CTRL, &res);
++	if (ret == 0) {
++		dev_info(axp->dev, "Backup (RTC) battery charging is %s",
++			(res & 0x80) == 0x80 ? "enabled" : "disabled");
++		if ((res & 0x60) != 0x20)
++			dev_warn(axp->dev, "Backup (RTC) battery target voltage is not 3.0V");
++	} else
++		dev_warn(axp->dev, "Unable to read register AXP20X_CHRG_BAK_CTRL: %d", ret);
++
++	axp20x_sysfs_create_subgroup("ac", axp, subsystems.ac, &axp20x_group_ac);
++	axp20x_sysfs_create_subgroup("vbus", axp, subsystems.vbus, &axp20x_group_vbus);
++	axp20x_sysfs_create_subgroup("battery", axp, subsystems.battery, &axp20x_group_battery);
++	axp20x_sysfs_create_subgroup("pmu", axp, subsystems.pmu, &axp20x_group_pmu);
++	axp20x_sysfs_create_subgroup("charger", axp, subsystems.charger, &axp20x_group_charger);
++	axp20x_sysfs_create_subgroup("control", axp, subsystems.control, &axp20x_group_control);
++
++	ret = sysfs_create_bin_file(&axp->dev->kobj, &axp20x_ocv_curve);
++	if (ret)
++		dev_warn(axp->dev, "Unable to create sysfs ocv_curve file: %d", ret);
++
++	ret = sysfs_create_link_nowarn(power_kobj, &axp->dev->kobj, "axp_pmu");
++	if (ret)
++		dev_warn(axp->dev, "Unable to create sysfs symlink: %d", ret);
++	return ret;
++}
++
++static void axp20x_sysfs_exit(struct axp20x_dev *axp)
++{
++	sysfs_delete_link(power_kobj, &axp->dev->kobj, "axp_pmu");
++	sysfs_remove_bin_file(&axp->dev->kobj, &axp20x_ocv_curve);
++	axp20x_sysfs_remove_subgroup(subsystems.control, &axp20x_group_control);
++	axp20x_sysfs_remove_subgroup(subsystems.charger, &axp20x_group_charger);
++	axp20x_sysfs_remove_subgroup(subsystems.pmu, &axp20x_group_pmu);
++	axp20x_sysfs_remove_subgroup(subsystems.battery, &axp20x_group_battery);
++	axp20x_sysfs_remove_subgroup(subsystems.vbus, &axp20x_group_vbus);
++	axp20x_sysfs_remove_subgroup(subsystems.ac, &axp20x_group_ac);
++}
++
+ int axp20x_match_device(struct axp20x_dev *axp20x)
+ {
+ 	struct device *dev = axp20x->dev;
+@@ -1363,6 +1969,10 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
+ 					      SYS_OFF_PRIO_DEFAULT,
+ 					      axp20x_power_off, axp20x);
+ 
++	if (axp20x->variant == AXP209_ID || axp20x->variant == AXP202_ID) {
++		axp20x_sysfs_init(axp20x);
++	}
++
+ 	dev_info(axp20x->dev, "AXP20X driver loaded\n");
+ 
+ 	return 0;
+@@ -1371,6 +1981,10 @@ EXPORT_SYMBOL(axp20x_device_probe);
+ 
+ void axp20x_device_remove(struct axp20x_dev *axp20x)
+ {
++	if (axp20x->variant == AXP209_ID || axp20x->variant == AXP202_ID) {
++		axp20x_sysfs_exit(axp20x);
++	}
++
+ 	mfd_remove_devices(axp20x->dev);
+ 	regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch
new file mode 100644
index 000000000000..bf7cebc2be6f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Mitko Gamishev <hehopmajieh@debian.bg>
+Date: Wed, 5 Feb 2020 15:31:25 +0200
+Subject: drv:mmc:host:sunxi-mmc Disable DDR52 mode on all A20 based boards
+
+---
+ drivers/mmc/host/sunxi-mmc.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index 9c86bd19a95d..7f336908a21c 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1452,7 +1452,9 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 	 */
+ 	if ((host->cfg->clk_delays || host->use_new_timings) &&
+ 	    !of_device_is_compatible(pdev->dev.of_node,
+-				     "allwinner,sun50i-h5-emmc"))
++				     "allwinner,sun50i-h5-emmc") &&
++	    !of_machine_is_compatible("allwinner,sun7i-a20") &&
++	    !of_machine_is_compatible("olimex,a64-olinuxino-2ge8g"))
+ 		mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
+ 
+ 	ret = mmc_of_parse(mmc);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch
new file mode 100644
index 000000000000..4f0757a3e644
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch
@@ -0,0 +1,38 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 13:26:03 +0300
+Subject: drv:mmc:host:sunxi-mmc: add h5 emmc compatible
+
+---
+ drivers/mmc/host/sunxi-mmc.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index e9370c736497..9c86bd19a95d 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1214,6 +1214,13 @@ static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = {
+ 	.needs_new_timings = true,
+ };
+ 
++static const struct sunxi_mmc_cfg sun50i_h5_emmc_cfg = {
++	.idma_des_size_bits = 13,
++	.clk_delays = NULL,
++	.can_calibrate = true,
++	.needs_new_timings = false,
++};
++
+ static const struct of_device_id sunxi_mmc_of_match[] = {
+ 	{ .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
+ 	{ .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
+@@ -1225,6 +1232,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
+ 	{ .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
+ 	{ .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg },
+ 	{ .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
++	{ .compatible = "allwinner,sun50i-h5-emmc", .data = &sun50i_h5_emmc_cfg },
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch
new file mode 100644
index 000000000000..2a87981a550b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:47:29 +0300
+Subject: drv:mtd:nand:raw:nand_ids.c add H27UBG8T2BTR-BC nand
+
+---
+ drivers/mtd/nand/raw/nand_ids.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
+index 650351c62af6..4f2166076c8a 100644
+--- a/drivers/mtd/nand/raw/nand_ids.c
++++ b/drivers/mtd/nand/raw/nand_ids.c
+@@ -50,6 +50,10 @@ struct nand_flash_dev nand_flash_ids[] = {
+ 	{"SDTNRGAMA 64G 3.3V 8-bit",
+ 		{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
+ 		  SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
++	{"H27UBG8T2BTR-BC 32G 3.3V 8-bit",
++		{ .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} },
++		  SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
++		  NAND_ECC_INFO(40, SZ_1K) },
+ 	{"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
+ 		{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
+ 		  SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch
new file mode 100644
index 000000000000..ecf5ee260fe5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch
@@ -0,0 +1,64 @@
+From cee3a50fee29f88352a354d4032564f18ec1f650 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Thu, 10 Dec 2020 14:42:12 +0000
+Subject: drv:net:stmmac:dwmac-sun8i: second EMAC clock register
+
+The Allwinner H616 SoC has two EMAC controllers, with the second one
+being tied to the internal PHY, but also using a separate EMAC clock
+register.
+
+To tell the driver about which clock register to use, we add a parameter
+to our syscon phandle. The driver will use this value as an index into
+the regmap, so that we can address more than the first register, if
+needed.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 08eeaf8d14bf..e81a5ba28f00 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -1165,11 +1165,13 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 	struct stmmac_resources stmmac_res;
+ 	struct sunxi_priv_data *gmac;
+ 	struct device *dev = &pdev->dev;
++	struct reg_field syscon_field;
+ 	phy_interface_t interface;
+ 	int ret;
+ 	struct stmmac_priv *priv;
+ 	struct net_device *ndev;
+ 	struct regmap *regmap;
++	u32 syscon_idx = 0;
+ 
+ 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+ 	if (ret)
+@@ -1224,8 +1226,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
+-	gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
+-						     *gmac->variant->syscon_field);
++	syscon_field = *gmac->variant->syscon_field;
++	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1,
++					 &syscon_idx);
++	if (!ret)
++		syscon_field.reg += syscon_idx * sizeof(u32);
++	gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, syscon_field);
+ 	if (IS_ERR(gmac->regmap_field)) {
+ 		ret = PTR_ERR(gmac->regmap_field);
+ 		dev_err(dev, "Unable to map syscon register: %d\n", ret);
+@@ -1350,6 +1356,8 @@ static const struct of_device_id sun8i_dwmac_match[] = {
+ 		.data = &emac_variant_a64 },
+ 	{ .compatible = "allwinner,sun50i-h6-emac",
+ 		.data = &emac_variant_h6 },
++	{ .compatible = "allwinner,sun50i-h616-emac",
++		.data = &emac_variant_h6 },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch
new file mode 100644
index 000000000000..78f360723134
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch
@@ -0,0 +1,41 @@
+From 225fb86e947935ae0c30f26a4acc990b7698831b Mon Sep 17 00:00:00 2001
+From: Kali Prasad <kprasadvnsi@protonmail.com>
+Date: Sun, 19 Sep 2021 08:02:27 +0000
+Subject: drv:nvmem:sunxi_sid: Support SID on H616
+
+Add support for H616's SID controller. It supports 4K-bit
+EFUSE.
+
+Signed-off-by: Kali Prasad <kprasadvnsi@protonmail.com>
+---
+ drivers/nvmem/sunxi_sid.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
+index ba14a76208ab..c13112b9149b 100644
+--- a/drivers/nvmem/sunxi_sid.c
++++ b/drivers/nvmem/sunxi_sid.c
+@@ -205,6 +205,12 @@ static const struct sunxi_sid_cfg sun50i_h6_cfg = {
+ 	.size = 0x200,
+ };
+ 
++static const struct sunxi_sid_cfg sun50i_h616_cfg = {
++	.value_offset = 0x200,
++	.size = 0x100,
++	.need_register_readout = true,
++};
++
+ static const struct of_device_id sunxi_sid_of_match[] = {
+ 	{ .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg },
+ 	{ .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
+@@ -214,6 +220,7 @@ static const struct of_device_id sunxi_sid_of_match[] = {
+ 	{ .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
++	{ .compatible = "allwinner,sun50i-h616-sid", .data = &sun50i_h616_cfg },
+ 	{/* sentinel */},
+ };
+ MODULE_DEVICE_TABLE(of, sunxi_sid_of_match);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
new file mode 100644
index 000000000000..e0e344c67010
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
@@ -0,0 +1,343 @@
+From 877cb766f1df5f4844a87983b96805b8a5985deb Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:22:21 +0300
+Subject: drv:of: Device Tree Overlay ConfigFS interface
+
+---
+ drivers/of/Kconfig       |   7 +
+ drivers/of/Makefile      |   1 +
+ drivers/of/configfs.c    | 278 +++++++++++++++++++++++++++++++++++++++
+ drivers/of/fdt_address.c |   2 +-
+ 4 files changed, 287 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/of/configfs.c
+
+diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
+index dd726c7056bf..777f28836cf9 100644
+--- a/drivers/of/Kconfig
++++ b/drivers/of/Kconfig
+@@ -107,6 +107,13 @@ config OF_OVERLAY
+ 	  While this option is selected automatically when needed, you can
+ 	  enable it manually to improve device tree unit test coverage.
+ 
++config OF_CONFIGFS
++        bool "Device Tree Overlay ConfigFS interface"
++        select CONFIGFS_FS
++        depends on OF_OVERLAY
++        help
++          Enable a simple user-space driven DT overlay interface.
++
+ config OF_NUMA
+ 	bool
+ 
+diff --git a/drivers/of/Makefile b/drivers/of/Makefile
+index 251d33532148..4622ec81b249 100644
+--- a/drivers/of/Makefile
++++ b/drivers/of/Makefile
+@@ -11,6 +11,7 @@ obj-$(CONFIG_OF_UNITTEST) += unittest.o
+ obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o
+ obj-$(CONFIG_OF_RESOLVE)  += resolver.o
+ obj-$(CONFIG_OF_OVERLAY) += overlay.o
++obj-$(CONFIG_OF_CONFIGFS) += configfs.o
+ obj-$(CONFIG_OF_NUMA) += of_numa.o
+ 
+ ifdef CONFIG_KEXEC_FILE
+diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c
+new file mode 100644
+index 000000000000..87974779561f
+--- /dev/null
++++ b/drivers/of/configfs.c
+@@ -0,0 +1,278 @@
++/*
++ * Configfs entries for device-tree
++ *
++ * Copyright (C) 2013 - Pantelis Antoniou <panto@antoniou-consulting.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ */
++#include <linux/ctype.h>
++#include <linux/cpu.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_fdt.h>
++#include <linux/spinlock.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/configfs.h>
++#include <linux/types.h>
++#include <linux/stat.h>
++#include <linux/limits.h>
++#include <linux/file.h>
++#include <linux/vmalloc.h>
++#include <linux/firmware.h>
++#include <linux/sizes.h>
++
++#include "of_private.h"
++
++struct cfs_overlay_item {
++	struct config_item	item;
++
++	char			path[PATH_MAX];
++
++	const struct firmware	*fw;
++	struct device_node	*overlay;
++	int			ov_id;
++
++	void			*dtbo;
++	int			dtbo_size;
++};
++
++static inline struct cfs_overlay_item *to_cfs_overlay_item(
++		struct config_item *item)
++{
++	return item ? container_of(item, struct cfs_overlay_item, item) : NULL;
++}
++
++static ssize_t cfs_overlay_item_path_show(struct config_item *item,
++		char *page)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	return sprintf(page, "%s\n", overlay->path);
++}
++
++static ssize_t cfs_overlay_item_path_store(struct config_item *item,
++		const char *page, size_t count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	const char *p = page;
++	char *s;
++	int err;
++
++	/* if it's set do not allow changes */
++	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
++		return -EPERM;
++
++	/* copy to path buffer (and make sure it's always zero terminated */
++	count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p);
++	overlay->path[sizeof(overlay->path) - 1] = '\0';
++
++	/* strip trailing newlines */
++	s = overlay->path + strlen(overlay->path);
++	while (s > overlay->path && *--s == '\n')
++		*s = '\0';
++
++	pr_debug("%s: path is '%s'\n", __func__, overlay->path);
++
++	err = request_firmware(&overlay->fw, overlay->path, NULL);
++	if (err != 0)
++		goto out_err;
++
++	err = of_overlay_fdt_apply((void *)overlay->fw->data,
++				   (u32)overlay->fw->size,
++				   &overlay->ov_id, NULL);
++	if (err != 0)
++		goto out_err;
++
++	return count;
++
++out_err:
++
++	release_firmware(overlay->fw);
++	overlay->fw = NULL;
++
++	overlay->path[0] = '\0';
++	return err;
++}
++
++static ssize_t cfs_overlay_item_status_show(struct config_item *item,
++		char *page)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	return sprintf(page, "%s\n",
++			overlay->ov_id > 0 ? "applied" : "unapplied");
++}
++
++CONFIGFS_ATTR(cfs_overlay_item_, path);
++CONFIGFS_ATTR_RO(cfs_overlay_item_, status);
++
++static struct configfs_attribute *cfs_overlay_attrs[] = {
++	&cfs_overlay_item_attr_path,
++	&cfs_overlay_item_attr_status,
++	NULL,
++};
++
++ssize_t cfs_overlay_item_dtbo_read(struct config_item *item,
++		void *buf, size_t max_count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	pr_debug("%s: buf=%p max_count=%zu\n", __func__,
++			buf, max_count);
++
++	if (overlay->dtbo == NULL)
++		return 0;
++
++	/* copy if buffer provided */
++	if (buf != NULL) {
++		/* the buffer must be large enough */
++		if (overlay->dtbo_size > max_count)
++			return -ENOSPC;
++
++		memcpy(buf, overlay->dtbo, overlay->dtbo_size);
++	}
++
++	return overlay->dtbo_size;
++}
++
++ssize_t cfs_overlay_item_dtbo_write(struct config_item *item,
++		const void *buf, size_t count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	int err;
++
++	/* if it's set do not allow changes */
++	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
++		return -EPERM;
++
++	/* copy the contents */
++	overlay->dtbo = kmemdup(buf, count, GFP_KERNEL);
++	if (overlay->dtbo == NULL)
++		return -ENOMEM;
++
++	overlay->dtbo_size = count;
++
++	err = of_overlay_fdt_apply(overlay->dtbo, overlay->dtbo_size,
++				   &overlay->ov_id, NULL);
++	if (err != 0)
++		goto out_err;
++
++	return count;
++
++out_err:
++	kfree(overlay->dtbo);
++	overlay->dtbo = NULL;
++	overlay->dtbo_size = 0;
++	overlay->ov_id = 0;
++
++	return err;
++}
++
++CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M);
++
++static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = {
++	&cfs_overlay_item_attr_dtbo,
++	NULL,
++};
++
++static void cfs_overlay_release(struct config_item *item)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	if (overlay->ov_id > 0)
++		of_overlay_remove(&overlay->ov_id);
++	if (overlay->fw)
++		release_firmware(overlay->fw);
++	/* kfree with NULL is safe */
++	kfree(overlay->dtbo);
++	kfree(overlay);
++}
++
++static struct configfs_item_operations cfs_overlay_item_ops = {
++	.release	= cfs_overlay_release,
++};
++
++static struct config_item_type cfs_overlay_type = {
++	.ct_item_ops	= &cfs_overlay_item_ops,
++	.ct_attrs	= cfs_overlay_attrs,
++	.ct_bin_attrs	= cfs_overlay_bin_attrs,
++	.ct_owner	= THIS_MODULE,
++};
++
++static struct config_item *cfs_overlay_group_make_item(
++		struct config_group *group, const char *name)
++{
++	struct cfs_overlay_item *overlay;
++
++	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
++	if (!overlay)
++		return ERR_PTR(-ENOMEM);
++
++	config_item_init_type_name(&overlay->item, name, &cfs_overlay_type);
++	return &overlay->item;
++}
++
++static void cfs_overlay_group_drop_item(struct config_group *group,
++		struct config_item *item)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	config_item_put(&overlay->item);
++}
++
++static struct configfs_group_operations overlays_ops = {
++	.make_item	= cfs_overlay_group_make_item,
++	.drop_item	= cfs_overlay_group_drop_item,
++};
++
++static struct config_item_type overlays_type = {
++	.ct_group_ops   = &overlays_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++static struct configfs_group_operations of_cfs_ops = {
++	/* empty - we don't allow anything to be created */
++};
++
++static struct config_item_type of_cfs_type = {
++	.ct_group_ops   = &of_cfs_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++struct config_group of_cfs_overlay_group;
++
++static struct configfs_subsystem of_cfs_subsys = {
++	.su_group = {
++		.cg_item = {
++			.ci_namebuf = "device-tree",
++			.ci_type = &of_cfs_type,
++		},
++	},
++	.su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex),
++};
++
++static int __init of_cfs_init(void)
++{
++	int ret;
++
++	pr_info("%s\n", __func__);
++
++	config_group_init(&of_cfs_subsys.su_group);
++	config_group_init_type_name(&of_cfs_overlay_group, "overlays",
++			&overlays_type);
++	configfs_add_default_group(&of_cfs_overlay_group,
++			&of_cfs_subsys.su_group);
++
++	ret = configfs_register_subsystem(&of_cfs_subsys);
++	if (ret != 0) {
++		pr_err("%s: failed to register subsys\n", __func__);
++		goto out;
++	}
++	pr_info("%s: OK\n", __func__);
++out:
++	return ret;
++}
++late_initcall(of_cfs_init);
+diff --git a/drivers/of/fdt_address.c b/drivers/of/fdt_address.c
+index 1dc15ab78b10..f697f2a52df4 100644
+--- a/drivers/of/fdt_address.c
++++ b/drivers/of/fdt_address.c
+@@ -160,7 +160,7 @@ static int __init fdt_translate_one(const void *blob, int parent,
+  * that can be mapped to a cpu physical address). This is not really specified
+  * that way, but this is traditionally the way IBM at least do things
+  */
+-static u64 __init fdt_translate_address(const void *blob, int node_offset)
++u64 __init fdt_translate_address(const void *blob, int node_offset)
+ {
+ 	int parent, len;
+ 	const struct of_bus *bus, *pbus;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch
new file mode 100644
index 000000000000..2606a5c31097
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch
@@ -0,0 +1,36 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 10 May 2021 11:01:31 +0100
+Subject: drv:phy: sun4i-usb: Allow reset line to be shared
+
+The USB HCIs (and PHYs?) in Allwinner's newer generation SoCs (H616)
+rely on the reset line of USB PHY 2 to be de-asserted, even when only
+one of the other PHYs is actually in use.
+
+To make those ports work, we include this reset line in the HCIs' resets
+property, which requires this line to be shareable.
+
+Change the call to allocate the reset line to mark it as shared, to
+enable the other ports on those SoCs.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/phy/allwinner/phy-sun4i-usb.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
+index 318c630c7c50..3788de7cea35 100644
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -866,7 +866,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		}
+ 
+ 		snprintf(name, sizeof(name), "usb%d_reset", i);
+-		phy->reset = devm_reset_control_get(dev, name);
++		phy->reset = devm_reset_control_get_shared(dev, name);
+ 		if (IS_ERR(phy->reset)) {
+ 			dev_err(dev, "failed to get reset %s\n", name);
+ 			return PTR_ERR(phy->reset);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch
new file mode 100644
index 000000000000..18dcc3b2dd2a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch
@@ -0,0 +1,30 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: WaterByWind <WaterByWind@users.noreply.github.com>
+Date: Sun, 14 Apr 2019 16:16:09 -0400
+Subject: drv:pinctrl: pinctrl-sun50i-a64 disable_strict_mode
+
+With kernel 4.15.y (and later):
+*  Strict mode was enabled by default via commit 1396007286b1e2fd5dd10ae6a5ccaaaed51ab762 which can/will cause breakage with existing implementations.
+* The ability to configure strict mode was added via commit aae842a3ff3385f27f1df8a9ee1494a416ec032d to allow older drivers to maintain existing behavior and avoid breakage.
+* Commit cd70387f892205bcd7b8093b0837269b0739cbe0 had then explicitly disabled strict mode for most other existing SoCs but did not include A64.
+
+This change is to update the A64 pinctrl driver similar to the other pre-existing SoC pinctrl drivers.
+---
+ drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
+index 1c23ce9df52f..d66897d6103a 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
+@@ -577,6 +577,7 @@ static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
+ 	.pins = a64_pins,
+ 	.npins = ARRAY_SIZE(a64_pins),
+ 	.irq_banks = 3,
++	.disable_strict_mode = true,
+ };
+ 
+ static int a64_pinctrl_probe(struct platform_device *pdev)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
new file mode 100644
index 000000000000..c8387bceba90
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:11:11 +0300
+Subject: drv:pinctrl:sunxi:pinctrl-sun50i-h6.c GPIO disable_strict_mode
+
+---
+ drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
+index 517118341316..16ac3946c776 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
+@@ -587,6 +587,7 @@ static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 };
+ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
+ 	.pins = h6_pins,
+ 	.npins = ARRAY_SIZE(h6_pins),
++	.disable_strict_mode = true,
+ 	.irq_banks = 4,
+ 	.irq_bank_map = h6_irq_bank_map,
+ 	.irq_read_needs_mux = true,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch
new file mode 100644
index 000000000000..400b4b0f33b5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch
@@ -0,0 +1,45 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 21 Apr 2021 12:46:43 +0100
+Subject: drv:rtc: sun6i: Add Allwinner H616 support
+
+The H616 RTC changes its day storage to the newly introduced linear day
+scheme, so pair the new compatible string with this feature flag.
+The clock part is missing an external 32768 Hz oscillator input pin,
+for future expansion we must thus ignore any provided clock for now.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/rtc/rtc-sun6i.c | 16 ++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
+index 190ea007d82e..e0b85a0d5645 100644
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -389,6 +389,22 @@ static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
+ CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
+ 		      sun50i_h6_rtc_clk_init);
+ 
++static const struct sun6i_rtc_clk_data sun50i_h616_rtc_data = {
++	.rc_osc_rate = 16000000,
++	.fixed_prescaler = 32,
++	.has_prescaler = 1,
++	.has_out_clk = 1,
++	.no_ext_losc = 1,
++};
++
++static void __init sun50i_h616_rtc_clk_init(struct device_node *node)
++{
++	sun6i_rtc_clk_init(node, &sun50i_h616_rtc_data);
++}
++
++CLK_OF_DECLARE_DRIVER(sun50i_h616_rtc_clk, "allwinner,sun50i-h616-rtc",
++		      sun50i_h616_rtc_clk_init);
++
+ /*
+  * The R40 user manual is self-conflicting on whether the prescaler is
+  * fixed or configurable. The clock diagram shows it as fixed, but there
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch
new file mode 100644
index 000000000000..7902dc4945ac
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch
@@ -0,0 +1,68 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 14 Jun 2021 23:02:45 +0100
+Subject: drv:rtc:sun6i: support RTCs without external LOSCs
+
+Some newer Allwinner RTCs (for instance the one in the H616 SoC) lack
+a pin for an external 32768 Hz oscillator. As a consequence, this LOSC
+can't be selected as the RTC clock source, and we must rely on the
+internal RC oscillator.
+To allow additions of clocks to the RTC node, add a feature bit to ignore
+any provided clocks for now (the current code would think this is the
+external LOSC). Later DTs and code can then for instance add the PLL
+based clock input, and older kernel won't get confused.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/rtc/rtc-sun6i.c | 16 +++++++---
+ 1 file changed, 11 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
+index 02129ea346c1..190ea007d82e 100644
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -137,6 +137,7 @@ struct sun6i_rtc_clk_data {
+ 	unsigned int has_out_clk : 1;
+ 	unsigned int has_losc_en : 1;
+ 	unsigned int has_auto_swt : 1;
++	unsigned int no_ext_losc : 1;
+ };
+ 
+ #define RTC_LINEAR_DAY	BIT(0)
+@@ -260,7 +261,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node,
+ 	}
+ 
+ 	/* Switch to the external, more precise, oscillator, if present */
+-	if (of_property_present(node, "clocks")) {
++	if (!rtc->data->no_ext_losc && of_get_property(node, "clocks", NULL)) {
+ 		reg |= SUN6I_LOSC_CTRL_EXT_OSC;
+ 		if (rtc->data->has_losc_en)
+ 			reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
+@@ -284,14 +285,19 @@ static void __init sun6i_rtc_clk_init(struct device_node *node,
+ 	}
+ 
+ 	parents[0] = clk_hw_get_name(rtc->int_osc);
+-	/* If there is no external oscillator, this will be NULL and ... */
+-	parents[1] = of_clk_get_parent_name(node, 0);
++	if (rtc->data->no_ext_losc) {
++		parents[1] = NULL;
++		init.num_parents = 1;
++	} else {
++		/* If there is no external oscillator, this will be NULL and */
++		parents[1] = of_clk_get_parent_name(node, 0);
++		/* ... number of clock parents will be 1. */
++		init.num_parents = of_clk_get_parent_count(node) + 1;
++	}
+ 
+ 	rtc->hw.init = &init;
+ 
+ 	init.parent_names = parents;
+-	/* ... number of clock parents will be 1. */
+-	init.num_parents = of_clk_get_parent_count(node) + 1;
+ 	of_property_read_string_index(node, "clock-output-names", 0,
+ 				      &init.name);
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch
new file mode 100644
index 000000000000..6f986247cfd7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sat, 16 Oct 2021 21:26:41 +0200
+Subject: drv:soc: sunxi: sram: Add SRAM C1 H616 handling
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/soc/sunxi/sunxi_sram.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
+index 4458b2e0562b..9e65d8dfe355 100644
+--- a/drivers/soc/sunxi/sunxi_sram.c
++++ b/drivers/soc/sunxi/sunxi_sram.c
+@@ -70,6 +70,12 @@ static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
+ 				  SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
+ };
+ 
++static struct sunxi_sram_desc sun50i_h616_sram_c1 = {
++	.data	= SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
++				  SUNXI_SRAM_MAP(0x7fffffff, 0, "cpu"),
++				  SUNXI_SRAM_MAP(0, 1, "ve")),
++};
++
+ static struct sunxi_sram_desc sun4i_a10_sram_d = {
+ 	.data	= SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
+ 				  SUNXI_SRAM_MAP(0, 0, "cpu"),
+@@ -99,6 +105,10 @@ static const struct of_device_id sunxi_sram_dt_ids[] = {
+ 		.compatible	= "allwinner,sun50i-a64-sram-c",
+ 		.data		= &sun50i_a64_sram_c.data,
+ 	},
++	{
++		.compatible	= "allwinner,sun50i-h616-sram-c1",
++		.data		= &sun50i_h616_sram_c1.data,
++	},
+ 	{}
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch
new file mode 100644
index 000000000000..1dc2ff3bcef7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch
@@ -0,0 +1,36 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 14:16:31 +0300
+Subject: drv:spi:spi-sun4i.c spi bug low on sck
+
+---
+ drivers/spi/spi-sun4i.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
+index b8947265d329..62e20f229e2c 100644
+--- a/drivers/spi/spi-sun4i.c
++++ b/drivers/spi/spi-sun4i.c
+@@ -389,6 +389,7 @@ static int sun4i_spi_runtime_resume(struct device *dev)
+ 	struct spi_controller *host = dev_get_drvdata(dev);
+ 	struct sun4i_spi *sspi = spi_controller_get_devdata(host);
+ 	int ret;
++	u32 reg;
+ 
+ 	ret = clk_prepare_enable(sspi->hclk);
+ 	if (ret) {
+@@ -401,9 +402,10 @@ static int sun4i_spi_runtime_resume(struct device *dev)
+ 		dev_err(dev, "Couldn't enable module clock\n");
+ 		goto err;
+ 	}
++	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
+ 
+ 	sun4i_spi_write(sspi, SUN4I_CTL_REG,
+-			SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
++			reg | SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
+ 
+ 	return 0;
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch
new file mode 100644
index 000000000000..a8c2a7b8e46e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch
@@ -0,0 +1,37 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 11:56:51 +0300
+Subject: drv:spi:spidev Add armbian spi-dev compatible
+
+---
+ drivers/spi/spidev.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index d13dc15cc191..456eca57ee4f 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -700,6 +700,7 @@ static const struct class spidev_class = {
+ };
+ 
+ static const struct spi_device_id spidev_spi_ids[] = {
++	{ .name = "spi-dev" },
+ 	{ .name = "dh2228fv" },
+ 	{ .name = "ltc2488" },
+ 	{ .name = "sx1301" },
+@@ -724,10 +725,12 @@ static int spidev_of_check(struct device *dev)
+ 		return 0;
+ 
+ 	dev_err(dev, "spidev listed directly in DT is not supported\n");
++	dev_info(dev, "Use a compatible alias string like spi-dev in DT\n");
+ 	return -EINVAL;
+ }
+ 
+ static const struct of_device_id spidev_dt_ids[] = {
++	{ .compatible = "armbian,spi-dev", .data = &spidev_of_check },
+ 	{ .compatible = "cisco,spi-petra", .data = &spidev_of_check },
+ 	{ .compatible = "dh,dhcom-board", .data = &spidev_of_check },
+ 	{ .compatible = "lineartechnology,ltc2488", .data = &spidev_of_check },
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch
new file mode 100644
index 000000000000..089747e17c90
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch
@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:49:45 +0200
+Subject: drv:staging:media:sunxi:cedrus: add H616 variant
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.c | 13 ++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
+index a0f9f4a5b03a..160bd376eb58 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
+@@ -651,6 +651,15 @@ static const struct cedrus_variant sun50i_h6_cedrus_variant = {
+ 	.mod_rate	= 600000000,
+ };
+ 
++static const struct cedrus_variant sun50i_h616_cedrus_variant = {
++	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
++			  CEDRUS_CAPABILITY_MPEG2_DEC |
++			  CEDRUS_CAPABILITY_H264_DEC |
++			  CEDRUS_CAPABILITY_H265_DEC |
++			  CEDRUS_CAPABILITY_VP8_DEC,
++	.mod_rate	= 600000000,
++};
++
+ static const struct of_device_id cedrus_dt_match[] = {
+ 	{
+ 		.compatible = "allwinner,sun4i-a10-video-engine",
+@@ -696,6 +705,10 @@ static const struct of_device_id cedrus_dt_match[] = {
+ 		.compatible = "allwinner,sun50i-h6-video-engine",
+ 		.data = &sun50i_h6_cedrus_variant,
+ 	},
++	{
++		.compatible = "allwinner,sun50i-h616-video-engine",
++		.data = &sun50i_h6_cedrus_variant,
++	},
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, cedrus_dt_match);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch
new file mode 100644
index 000000000000..44e005aec770
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch
@@ -0,0 +1,25 @@
+From 4209ec96eef018a0ccbbca0bd659671822e963fc Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 7 Feb 2022 17:00:50 +0300
+Subject: drv:staging:rtl8723bs: AP bugfix
+
+---
+ drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c b/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
+index 65a450fcdce7..bf57c603c724 100644
+--- a/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
++++ b/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
+@@ -1932,7 +1932,7 @@ void rtw_cfg80211_indicate_sta_assoc(struct adapter *padapter, u8 *pmgmt_frame,
+ 		else /*  WIFI_REASSOCREQ */
+ 			ie_offset = _REASOCREQ_IE_OFFSET_;
+ 
+-		sinfo.filled = 0;
++		sinfo.pertid = 0;
+ 		sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset;
+ 		sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset;
+ 		cfg80211_new_sta(ndev, GetAddr2Ptr(pmgmt_frame), &sinfo, GFP_ATOMIC);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch
new file mode 100644
index 000000000000..6075f42f7c73
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 20:08:50 +0300
+Subject: drv:usb:gadget:composite rename gadget serial console manufacturer
+
+rename the manufacturer of gadgets for serial consoles
+to the Armbian brand.
+---
+ drivers/usb/gadget/composite.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
+index 0ace45b66a31..89b596897733 100644
+--- a/drivers/usb/gadget/composite.c
++++ b/drivers/usb/gadget/composite.c
+@@ -2758,7 +2758,7 @@ EXPORT_SYMBOL_GPL(usb_composite_setup_continue);
+ 
+ static char *composite_default_mfr(struct usb_gadget *gadget)
+ {
+-	return kasprintf(GFP_KERNEL, "%s %s with %s", init_utsname()->sysname,
++	return kasprintf(GFP_KERNEL, "%s %s with %s", "Armbian Linux",
+ 			 init_utsname()->release, gadget->name);
+ }
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
new file mode 100644
index 000000000000..d0a6c1fa29f0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
@@ -0,0 +1,659 @@
+From 123d69e22b497618e427611d0d98b78b176808d8 Mon Sep 17 00:00:00 2001
+From: Radoslav <radoslavv@centrum.sk>
+Date: Sat, 15 Apr 2023 22:47:26 +0200
+Subject: enable TV Output on OrangePi Zero LTE
+
+Credits to sorce https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/README2.md
+Merged:
+1. sunxi-6.1/0036-wip-h3-h5-cvbs-armbian.patch : makes additions to the "dts", which tells the kernel where are the new devices. Adds kernel code to interact with the tv encoder. With my modifications, now it is applicable to Armbian (this patch came from the LibreElec github).
+    https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/sunxi-6.1/0036-wip-h3-h5-cvbs-armbian.patch
+2. sunxi-6.1/zzzz2-tv.patch : by Armbian user "gleam2003", adds directives to make sure that the dtbo (device tree binary overlay) is compiled
+    https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/sunxi-6.1/zzzz2-tv.patch
+3. sunxi-6.1/zzzz3-tv.patch : more additions to the "dts" and "dtsi" (like C include files), which I noticed were included in "yam" patch, but missing from the LibreElec patch
+    https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/sunxi-6.1/zzzz3-tv.patch
+
+> X-Git-Archeology: - Revision 41260ac309b487d241fec97ffbdeced730bc2d04: https://github.com/armbian/build/commit/41260ac309b487d241fec97ffbdeced730bc2d04
+> X-Git-Archeology:   Date: Sat, 15 Apr 2023 22:47:26 +0200
+> X-Git-Archeology:   From: Radoslav <radoslavv@centrum.sk>
+> X-Git-Archeology:   Subject: h3-tve (arm-dts-sun8i-h3-orangepizero-add_tve.patch)
+---
+ arch/arm/boot/dts/allwinner/overlay/Makefile  |  1 +
+ .../overlay/README.sun8i-h3-overlays          | 10 ++
+ .../dts/allwinner/overlay/sun8i-h3-tve.dtso   | 34 +++++++
+ .../allwinner/sun8i-h2-plus-orangepi-zero.dts |  4 +
+ .../dts/allwinner/sun8i-h3-orangepi-pc.dts    |  4 +
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi     | 22 +++++
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi  | 95 ++++++++++++++++++-
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  1 +
+ .../overlay/README.sun50i-h5-overlays         |  5 +
+ .../dts/allwinner/overlay/sun50i-h5-tve.dtso  | 34 +++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  | 22 +++++
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c           | 14 ++-
+ drivers/gpu/drm/sun4i/Makefile                |  2 +-
+ drivers/gpu/drm/sun4i/sun4i_tv.c              | 35 ++++++-
+ drivers/gpu/drm/sun4i/sun8i_mixer.c           | 36 ++++++-
+ drivers/gpu/drm/sun4i/sun8i_mixer.h           |  5 +-
+ 16 files changed, 310 insertions(+), 14 deletions(-)
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso
+
+diff --git a/arch/arm/boot/dts/allwinner/overlay/Makefile b/arch/arm/boot/dts/allwinner/overlay/Makefile
+index 560f926b7018..23ecb62e2478 100644
+--- a/arch/arm/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm/boot/dts/allwinner/overlay/Makefile
+@@ -80,6 +80,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-h3-usbhost2.dtbo \
+ 	sun8i-h3-usbhost3.dtbo \
+ 	sun8i-h3-w1-gpio.dtbo \
++        sun8i-h3-tve.dtbo \
+ 	sun8i-r40-i2c2.dtbo \
+ 	sun8i-r40-i2c3.dtbo \
+ 	sun8i-r40-spi-spidev0.dtbo \
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+index 302973491051..a347fe7b0e81 100644
+--- a/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+@@ -34,6 +34,7 @@ adding fixed software (GPIO) chip selects is possible with a separate overlay
+ - usbhost2
+ - usbhost3
+ - w1-gpio
++- tve
+ 
+ ### Overlay details:
+ 
+@@ -248,3 +249,12 @@ param_w1_pin_int_pullup (bool)
+ 	Set to 1 to enable the pull-up
+ 	This option should not be used with multiple devices, parasite power setup
+ 		or long wires -	please use external pull-up resistor instead
++
++### tve
++
++Activates Composite TV Encoder
++
++Parameters:
++	Unknown at this stage. 
++	Maybe none. 
++	Not sure how to change the mode between PAL/NTSC.
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso
+new file mode 100644
+index 000000000000..07ba7ba713dd
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso
+@@ -0,0 +1,34 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++	
++	fragment@0 {
++		target = <&de>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&mixer1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&tcon1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@3 {
++		target = <&tve>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+index 7b42ab8b5180..330a79390238 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+@@ -180,6 +180,10 @@ flash@0 {
+ 	};
+ };
+ 
++&tve {
++        status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+index 624e248e3ffc..01c3a7f7620a 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+@@ -214,6 +214,10 @@ &sound_hdmi {
+ 	status = "okay";
+ };
+ 
++&tve {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index 8c2f597772fe..35c864fe4823 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -295,6 +295,20 @@ ths: thermal-sensor@1c25000 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <0>;
+ 		};
++
++		tve: tv-encoder@1e00000 {
++			compatible = "allwinner,sun8i-h3-tv-encoder";
++			reg = <0x01e00000 0x1000>;
++			clocks = <&ccu CLK_BUS_TVE>;
++			resets = <&ccu RST_BUS_TVE>;
++			status = "disabled";
++
++			port {
++				tve_in_tcon1: endpoint {
++					remote-endpoint = <&tcon1_out_tve>;
++				};
++			};
++		};
+ 	};
+ 
+ 	thermal-zones {
+@@ -384,6 +398,10 @@ &mbus {
+ 	compatible = "allwinner,sun8i-h3-mbus";
+ };
+ 
++&mixer1 {
++	resets = <&display_clocks RST_WB>;
++};
++
+ &mmc0 {
+ 	compatible = "allwinner,sun7i-a20-mmc";
+ 	clocks = <&ccu CLK_BUS_MMC0>,
+@@ -431,3 +449,7 @@ &rtc {
+ &sid {
+ 	compatible = "allwinner,sun8i-h3-sid";
+ };
++
++&tcon1_out_tve {
++	remote-endpoint = <&tve_in_tcon1>;
++};
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 9ccbbe7eb337..4ba15518661f 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -116,7 +116,7 @@ cpu {
+ 
+ 	de: display-engine {
+ 		compatible = "allwinner,sun8i-h3-display-engine";
+-		allwinner,pipelines = <&mixer0>;
++		allwinner,pipelines = <&mixer0>, <&mixer1>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -160,11 +160,50 @@ ports {
+ 				#size-cells = <0>;
+ 
+ 				mixer0_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
+ 					reg = <1>;
+ 
+-					mixer0_out_tcon0: endpoint {
++					mixer0_out_tcon0: endpoint@0 {
++						reg = <0>;
+ 						remote-endpoint = <&tcon0_in_mixer0>;
+ 					};
++
++					mixer0_out_tcon1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon1_in_mixer0>;
++					};
++				};
++			};
++		};
++
++		mixer1: mixer@1200000 {
++			compatible = "allwinner,sun8i-h3-de2-mixer-1";
++			reg = <0x01200000 0x100000>;
++			clocks = <&display_clocks CLK_BUS_MIXER1>,
++				 <&display_clocks CLK_MIXER1>;
++			clock-names = "bus",
++				      "mod";
++			/* reset is added by SoC dtsi */
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				mixer1_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <1>;
++
++					mixer1_out_tcon0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon0_in_mixer1>;
++					};
++
++					mixer1_out_tcon1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon1_in_mixer1>;
++					};
+ 				};
+ 			};
+ 		};
+@@ -193,11 +232,19 @@ ports {
+ 				#size-cells = <0>;
+ 
+ 				tcon0_in: port@0 {
++					#address-cells = <1>;
++					#size-cells = <0>;
+ 					reg = <0>;
+ 
+-					tcon0_in_mixer0: endpoint {
++					tcon0_in_mixer0: endpoint@0 {
++						reg = <0>;
+ 						remote-endpoint = <&mixer0_out_tcon0>;
+ 					};
++
++					tcon0_in_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&mixer1_out_tcon0>;
++					};
+ 				};
+ 
+ 				tcon0_out: port@1 {
+@@ -213,6 +260,48 @@ tcon0_out_hdmi: endpoint@1 {
+ 			};
+ 		};
+ 
++		tcon1: lcd-controller@1c0d000 {
++			compatible = "allwinner,sun8i-h3-tcon-tv",
++				     "allwinner,sun8i-a83t-tcon-tv";
++			reg = <0x01c0d000 0x1000>;
++			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TVE>;
++			clock-names = "ahb", "tcon-ch1";
++			resets = <&ccu RST_BUS_TCON1>;
++			reset-names = "lcd";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon1_in: port@0 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <0>;
++
++					tcon1_in_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&mixer0_out_tcon1>;
++					};
++
++					tcon1_in_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&mixer1_out_tcon1>;
++					};
++				};
++
++				tcon1_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <1>;
++
++					tcon1_out_tve: endpoint@1 {
++						reg = <1>;
++					};
++				};
++			};
++		};
++
+ 		mmc0: mmc@1c0f000 {
+ 			/* compatible and clocks are in per SoC .dtsi file */
+ 			reg = <0x01c0f000 0x1000>;
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index fb6b30d5753e..84711585fc86 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h5-spi-add-cs1.dtbo \
+ 	sun50i-h5-spi-jedec-nor.dtbo \
+ 	sun50i-h5-spi-spidev.dtbo \
++	sun50i-h5-tve.dtbo \
+ 	sun50i-h5-uart1.dtbo \
+ 	sun50i-h5-uart2.dtbo \
+ 	sun50i-h5-uart3.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+index 1ac7fbcf62d1..a2ef4427c65b 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+@@ -26,6 +26,7 @@ adding fixed software (GPIO) chip selects is possible with a separate overlay
+ - spi-add-cs1
+ - spi-jedec-nor
+ - spi-spidev
++- tve
+ - uart1
+ - uart2
+ - uart3
+@@ -170,6 +171,10 @@ param_spidev_max_freq (int)
+ 	Default: 1000000
+ 	Range: 3000 - 100000000
+ 
++### tve
++
++Activates Composite TV Encoder
++
+ ### uart1
+ 
+ Activates serial port 1 (/dev/ttyS1)
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso
+new file mode 100644
+index 000000000000..73e6e1215a5a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso
+@@ -0,0 +1,34 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h5";
++
++	fragment@0 {
++		target = <&de>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&mixer1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&tcon1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@3 {
++		target = <&tve>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index c63e0871658e..fee2d680d2ca 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -203,6 +203,20 @@ ths: thermal-sensor@1c25000 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <1>;
+ 		};
++
++		tve: tv-encoder@1e40000 {
++			compatible = "allwinner,sun50i-h5-tv-encoder";
++			reg = <0x01e40000 0x1000>;
++			clocks = <&ccu CLK_BUS_TVE>;
++			resets = <&ccu RST_BUS_TVE>;
++			status = "disabled";
++
++			port {
++				tve_in_tcon1: endpoint {
++					remote-endpoint = <&tcon1_out_tve>;
++				};
++			};
++		};
+ 	};
+ 
+ 	thermal-zones {
+@@ -307,6 +321,10 @@ &mbus {
+ 	compatible = "allwinner,sun50i-h5-mbus";
+ };
+ 
++&mixer1 {
++	resets = <&display_clocks RST_MIXER1>;
++};
++
+ &mmc0 {
+ 	compatible = "allwinner,sun50i-h5-mmc",
+ 		     "allwinner,sun50i-a64-mmc";
+@@ -342,3 +360,7 @@ &rtc {
+ &sid {
+ 	compatible = "allwinner,sun50i-h5-sid";
+ };
++
++&tcon1_out_tve {
++	remote-endpoint = <&tve_in_tcon1>;
++};
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 5d75d07dec0e..80731b155f6c 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -469,8 +469,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
+ 				 CLK_SET_RATE_PARENT);
+ 
+ static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
+-static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
+-				 0x120, 0, 4, 24, 3, BIT(31), 0);
++struct ccu_div tve_clk = {
++	.enable	= BIT(31),
++	.div	= _SUNXI_CCU_DIV(0, 4),
++	.mux	= _SUNXI_CCU_MUX(24, 3),
++	.fixed_post_div = 16,
++	.common	= {
++		.reg		= 0x120,
++		.features	= CCU_FEATURE_FIXED_POSTDIV,
++		.hw.init	= CLK_HW_INIT_PARENTS("tve", tve_parents,
++						      &ccu_div_ops, 0),
++	},
++};
+ 
+ static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
+ static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
+diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
+index 5e9dc9370584..3a7130623351 100644
+--- a/drivers/gpu/drm/sun4i/Makefile
++++ b/drivers/gpu/drm/sun4i/Makefile
+@@ -19,7 +19,7 @@ sun8i-drm-hdmi-y		+= sun8i_hdmi_phy_clk.o
+ 
+ sun8i-mixer-y			+= sun8i_mixer.o sun8i_ui_layer.o \
+ 				   sun8i_vi_layer.o sun8i_ui_scaler.o \
+-				   sun8i_vi_scaler.o sun8i_csc.o
++				   sun8i_vi_scaler.o sun8i_csc.o sun4i_tv.o
+ 
+ sun4i-tcon-y			+= sun4i_crtc.o
+ sun4i-tcon-y			+= sun4i_tcon_dclk.o
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
+index ec65d9d59de7..d2235d5a7416 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
+@@ -10,6 +10,7 @@
+ #include <linux/component.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/reset.h>
+@@ -159,6 +160,11 @@ struct tv_mode {
+ 	const struct resync_parameters	*resync_params;
+ };
+ 
++struct sun4i_tv_quirks {
++	unsigned int calibration;
++	unsigned int unknown : 1;
++};
++
+ struct sun4i_tv {
+ 	struct drm_connector	connector;
+ 	struct drm_encoder	encoder;
+@@ -419,7 +425,7 @@ static const struct regmap_config sun4i_tv_regmap_config = {
+ 	.reg_bits	= 32,
+ 	.val_bits	= 32,
+ 	.reg_stride	= 4,
+-	.max_register	= SUN4I_TVE_WSS_DATA2_REG,
++	.max_register	= 0x400,
+ 	.name		= "tv-encoder",
+ };
+ 
+@@ -429,13 +435,19 @@ static int sun4i_tv_bind(struct device *dev, struct device *master,
+ 	struct platform_device *pdev = to_platform_device(dev);
+ 	struct drm_device *drm = data;
+ 	struct sun4i_drv *drv = drm->dev_private;
++	const struct sun4i_tv_quirks *quirks;
+ 	struct sun4i_tv *tv;
+ 	void __iomem *regs;
+ 	int ret;
+ 
++	quirks = of_device_get_match_data(dev);
++	if (!quirks)
++		return -EINVAL;
++
+ 	tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
+ 	if (!tv)
+ 		return -ENOMEM;
++
+ 	tv->drv = drv;
+ 	dev_set_drvdata(dev, tv);
+ 
+@@ -472,6 +484,11 @@ static int sun4i_tv_bind(struct device *dev, struct device *master,
+ 	}
+ 	clk_prepare_enable(tv->clk);
+ 
++	if (quirks->calibration)
++		regmap_write(tv->regs, 0x304, quirks->calibration);
++	if (quirks->unknown)
++		regmap_write(tv->regs, 0x30c, 0x00101110);
++
+ 	drm_encoder_helper_add(&tv->encoder,
+ 			       &sun4i_tv_helper_funcs);
+ 	ret = drm_simple_encoder_init(drm, &tv->encoder,
+@@ -551,8 +568,22 @@ static void sun4i_tv_remove(struct platform_device *pdev)
+ 	component_del(&pdev->dev, &sun4i_tv_ops);
+ }
+ 
++static const struct sun4i_tv_quirks a10_quirks = {
++};
++
++static const struct sun4i_tv_quirks h3_quirks = {
++	.calibration = 0x02000c00,
++};
++
++static const struct sun4i_tv_quirks h5_quirks = {
++	.calibration = 0x02850000,
++	.unknown = 1,
++};
++
+ static const struct of_device_id sun4i_tv_of_table[] = {
+-	{ .compatible = "allwinner,sun4i-a10-tv-encoder" },
++	{ .compatible = "allwinner,sun4i-a10-tv-encoder", .data = &a10_quirks },
++	{ .compatible = "allwinner,sun8i-h3-tv-encoder", .data = &h3_quirks },
++	{ .compatible = "allwinner,sun50i-h5-tv-encoder", .data = &h5_quirks },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 8aabc78c0223..3c18c7515a0a 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -37,6 +37,12 @@ struct de2_fmt_info {
+ 
+ static bool hw_preconfigured;
+ 
++static const u32 sun8i_rgb2yuv_coef[12] = {
++	0x00000107, 0x00000204, 0x00000064, 0x00004200,
++	0x00001f68, 0x00001ed6, 0x000001c2, 0x00020200,
++	0x000001c2, 0x00001e87, 0x00001fb7, 0x00020200,
++};
++
+ static const struct de2_fmt_info de2_formats[] = {
+ 	{
+ 		.drm_fmt = DRM_FORMAT_ARGB8888,
+@@ -425,10 +431,29 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine,
+ 			 interlaced ? "on" : "off");
+ }
+ 
++static void sun8i_mixer_apply_color_correction(struct sunxi_engine *engine)
++{
++	DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
++
++	regmap_bulk_write(engine->regs, SUN8I_MIXER_DCSC_COEF_REG(0),
++			  sun8i_rgb2yuv_coef, 12);
++	regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 1);
++}
++
++static void sun8i_mixer_disable_color_correction(struct sunxi_engine *engine)
++{
++	DRM_DEBUG_DRIVER("Disabling color correction\n");
++
++	/* Disable color correction */
++	regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 0);
++}
++
+ static const struct sunxi_engine_ops sun8i_engine_ops = {
+-	.commit		= sun8i_mixer_commit,
+-	.layers_init	= sun8i_layers_init,
+-	.mode_set	= sun8i_mixer_mode_set,
++	.commit				= sun8i_mixer_commit,
++	.layers_init			= sun8i_layers_init,
++	.mode_set			= sun8i_mixer_mode_set,
++	.apply_color_correction		= sun8i_mixer_apply_color_correction,
++	.disable_color_correction	= sun8i_mixer_disable_color_correction,
+ };
+ 
+ static const struct regmap_config sun8i_mixer_regmap_config = {
+@@ -709,8 +734,9 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+ static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
+ 	.ccsc		= CCSC_MIXER1_LAYOUT,
+ 	.mod_rate	= 432000000,
+-	.scaler_mask	= 0xf,
+-	.ui_num		= 3,
++	.scaler_mask	= 0x3,
++	.scanline_yuv	= 2048,
++	.ui_num		= 1,
+ 	.vi_num		= 1,
+ };
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 68e2741b0962..7bc8efca6980 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -119,6 +119,10 @@
+ /* format 20 is packed YVU444 10-bit */
+ /* format 21 is packed YUV444 10-bit */
+ 
++/* The DCSC sub-engine is used to do color space conversation */
++#define SUN8I_MIXER_DCSC_EN			0xb0000
++#define SUN8I_MIXER_DCSC_COEF_REG(x)		(0xb0010 + 0x4 * (x))
++
+ /*
+  * Sub-engines listed bellow are unused for now. The EN registers are here only
+  * to be used to disable these sub-engines.
+@@ -129,7 +133,6 @@
+ #define SUN8I_MIXER_PEAK_EN			0xa6000
+ #define SUN8I_MIXER_ASE_EN			0xa8000
+ #define SUN8I_MIXER_FCC_EN			0xaa000
+-#define SUN8I_MIXER_DCSC_EN			0xb0000
+ 
+ #define SUN50I_MIXER_FCE_EN			0x70000
+ #define SUN50I_MIXER_PEAK_EN			0x70800
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch
new file mode 100644
index 000000000000..cdef7a51490f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch
@@ -0,0 +1,115 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 27 May 2022 14:45:59 +0300
+Subject: fix: cpu opp table sun8i-a83t
+
+cpu opp table can only be a multiple of the integer 24 * 8 * n
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 52 ++++++----
+ 1 file changed, 32 insertions(+), 20 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index df70bd569f9d..4f849c9e573e 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -224,32 +224,38 @@ cpu0_opp_table: opp-table-cluster0 {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
+-		opp-480000000 {
+-			opp-hz = /bits/ 64 <480000000>;
++		opp-576000000 {
++			opp-hz = /bits/ 64 <576000000>; /* 24x8x3 */
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1008000000 {
+-			opp-hz = /bits/ 64 <1008000000>;
++		opp-768000000 {
++			opp-hz = /bits/ 64 <768000000>; /* 24x8x4 */
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1412000000 {
+-			opp-hz = /bits/ 64 <1412000000>;
++		opp-1152000000 {
++			opp-hz = /bits/ 64 <1152000000>; /* 24x8x6 */
++			opp-microvolt = <900000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1344000000 {
++			opp-hz = /bits/ 64 <1344000000>; /* 24x8x7 */
+ 			opp-microvolt = <920000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1608000000 {
+-			opp-hz = /bits/ 64 <1608000000>;
++		opp-1536000000 {
++			opp-hz = /bits/ 64 <1536000000>; /* 24x8x8 */
+ 			opp-microvolt = <1000000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1800000000 {
+-			opp-hz = /bits/ 64 <1800000000>;
++		opp-1728000000 {
++			opp-hz = /bits/ 64 <1728000000>; /* 24x8x9 */
+ 			opp-microvolt = <1080000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+@@ -259,32 +265,38 @@ cpu1_opp_table: opp-table-cluster1 {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
+-		opp-480000000 {
+-			opp-hz = /bits/ 64 <480000000>;
++		opp-576000000 {
++			opp-hz = /bits/ 64 <576000000>; /* 24x8x3 */
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1008000000 {
+-			opp-hz = /bits/ 64 <1008000000>;
++		opp-768000000 {
++			opp-hz = /bits/ 64 <768000000>; /* 24x8x4 */
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1412000000 {
+-			opp-hz = /bits/ 64 <1412000000>;
++		opp-1152000000 {
++			opp-hz = /bits/ 64 <1152000000>; /* 24x8x6 */
++			opp-microvolt = <900000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1344000000 {
++			opp-hz = /bits/ 64 <1344000000>; /* 24x8x7 */
+ 			opp-microvolt = <920000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1608000000 {
+-			opp-hz = /bits/ 64 <1608000000>;
++		opp-1536000000 {
++			opp-hz = /bits/ 64 <1536000000>; /* 24x8x8 */
+ 			opp-microvolt = <1000000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1800000000 {
+-			opp-hz = /bits/ 64 <1800000000>;
++		opp-1728000000 {
++			opp-hz = /bits/ 64 <1728000000>; /* 24x8x9 */
+ 			opp-microvolt = <1080000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch
new file mode 100644
index 000000000000..9a29131061ab
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch
@@ -0,0 +1,35 @@
+From 11dfd4ac6f8ebba5c2f7f49678cd3981ebe9fec5 Mon Sep 17 00:00:00 2001
+From: Qiang Yu <yuq825@gmail.com>
+Date: Tue, 19 Jun 2018 13:51:17 +0800
+Subject: include:uapi:drm_fourcc: add ARM tiled format modifier
+
+Signed-off-by: Qiang Yu <yuq825@gmail.com>
+
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ include/uapi/drm/drm_fourcc.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
+index 84d502e42961..52d3e2e18582 100644
+--- a/include/uapi/drm/drm_fourcc.h
++++ b/include/uapi/drm/drm_fourcc.h
+@@ -1324,6 +1324,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
+  */
+ #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
+ 
++/*
++ * ARM tiled format
++ *
++ * This is used by ARM Mali Utgard/Midgard GPU. It divides buffer into
++ * 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
++ * in the block are reordered.
++ */
++#define DRM_FORMAT_MOD_ARM_TILED fourcc_mod_code(ARM, 1)
++
+ /*
+  * Arm 16x16 Block U-Interleaved modifier
+  *
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch
new file mode 100644
index 000000000000..296d3da7079b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch
@@ -0,0 +1,375 @@
+From b5a9bed8ee8da49bb63437a5a2bfb1fc588decca Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 13 Jun 2022 17:37:19 +0100
+Subject: mfd: Add support for X-Powers AC200 EPHY syscon
+
+The X-Powers AC200 mixed signal chip contains a 100Mbit/s Ethernet PHY.
+While the PHY is using the standard MDIO and MII/RMII interfaces to
+the MAC, there are some registers in the AC200 that need to be setup to
+make the PHY functional:
+- The MDIO PHY address needs to set.
+- The LED polarity needs to be configured.
+- The MII interface mode needs to be set (MII or RMII).
+- There is a reset line that controls the PHY operation.
+- There is a clock gate that blocks or forwards the AC200's internal clock
+  to the PHY.
+
+This driver here takes care of those setup needs, but does not cover the
+actual PHY operation. Once the PHY is set up and enabled, it behaves like
+a standard MDIO/MII controlled PHY, and can be driven by the IEEE802.3-C22
+driver.
+
+To some degree those parameters mimic the typical wired setup of a
+physical PHY chip: the LED polarity, MII interface mode and PHY address
+are typically configued via connecting certain pins. We use the
+devicetree to learn those parameters, which depend on the board setup.
+
+This driver is a child of the AC200 MFD parent device, and uses its
+regmap and input clock. It also provides a reset and clock controller,
+which the actual PHY device (node) needs to refer to. This ensures that
+this PHY control device is initialised before the PHY is expected to work.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/phy/allwinner/Kconfig          |   9 +
+ drivers/phy/allwinner/Makefile         |   1 +
+ drivers/phy/allwinner/ac200-ephy-ctl.c | 301 +++++++++++++++++++++++++
+ 3 files changed, 311 insertions(+)
+ create mode 100644 drivers/phy/allwinner/ac200-ephy-ctl.c
+
+diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
+index e93a53139460..d3614169de5c 100644
+--- a/drivers/phy/allwinner/Kconfig
++++ b/drivers/phy/allwinner/Kconfig
+@@ -58,3 +58,12 @@ config PHY_SUN50I_USB3
+ 	  part of Allwinner H6 SoC.
+ 
+ 	  This driver controls each individual USB 2+3 host PHY combo.
++
++config AC200_PHY_CTL
++	tristate "X-Power AC200 PHY control driver"
++	depends on MFD_AC200
++	depends on RESET_CONTROLLER
++	help
++	  Enable this to support the Ethernet PHY operation of the AC200
++	  mixed signal chip. This driver just enables and configures the
++	  PHY, the PHY itself is supported by a standard driver.
+diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
+index bd74901a1255..0eecec7a908a 100644
+--- a/drivers/phy/allwinner/Makefile
++++ b/drivers/phy/allwinner/Makefile
+@@ -3,3 +3,4 @@ obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
+ obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY)	+= phy-sun6i-mipi-dphy.o
+ obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
+ obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
++obj-$(CONFIG_AC200_PHY_CTL)		+= ac200-ephy-ctl.o
+diff --git a/drivers/phy/allwinner/ac200-ephy-ctl.c b/drivers/phy/allwinner/ac200-ephy-ctl.c
+new file mode 100644
+index 000000000000..8efeaf18e42c
+--- /dev/null
++++ b/drivers/phy/allwinner/ac200-ephy-ctl.c
+@@ -0,0 +1,301 @@
++// SPDX-License-Identifier: GPL-2.0+
++/**
++ * syscon driver to control and configure AC200 Ethernet PHY
++ * Copyright (c) 2022 Arm Ltd.
++ *
++ * TODO's and questions:
++ * =========================
++ * - This driver is something like a syscon driver, as it controls various
++ *   bits and registers that effect other devices (the actual PHY). It's
++ *   unclear where it should live, though:
++ *   - it could be integrated into the MFD driver, but this looks messy
++ *   - it could live at the current location (drivers/phy/allwinner), but that
++ *     sounds wrong
++ *   - it could be a separate file, but in drivers/mfd
++ *   - anything else
++ *
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/of_net.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++#include <linux/reset-controller.h>
++
++/* macros for system ephy control 0 register */
++#define AC200_SYS_EPHY_CTL0		0x0014
++#define AC200_EPHY_RESET_INVALID	BIT(0)
++#define AC200_EPHY_SYSCLK_GATING	1
++
++/* macros for system ephy control 1 register */
++#define AC200_SYS_EPHY_CTL1		0x0016
++#define AC200_EPHY_E_EPHY_MII_IO_EN	BIT(0)
++#define AC200_EPHY_E_LNK_LED_IO_EN	BIT(1)
++#define AC200_EPHY_E_SPD_LED_IO_EN	BIT(2)
++#define AC200_EPHY_E_DPX_LED_IO_EN	BIT(3)
++
++/* macros for ephy control register */
++#define AC200_EPHY_CTL			0x6000
++#define AC200_EPHY_SHUTDOWN		BIT(0)
++#define AC200_EPHY_LED_POL		BIT(1)
++#define AC200_EPHY_CLK_SEL		BIT(2)
++#define AC200_EPHY_ADDR(x)		(((x) & 0x1F) << 4)
++#define AC200_EPHY_XMII_SEL		BIT(11)
++#define AC200_EPHY_CALIB(x)		(((x) & 0xF) << 12)
++
++struct ac200_ephy_ctl_dev {
++	struct reset_controller_dev	rcdev;
++	struct clk_hw			*gate_clk;
++	struct regmap			*regmap;
++};
++
++static struct ac200_ephy_ctl_dev *to_phy_dev(struct reset_controller_dev *rcdev)
++{
++	return container_of(rcdev, struct ac200_ephy_ctl_dev, rcdev);
++}
++
++static int ephy_ctl_reset(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++	int ret;
++
++	ret = regmap_clear_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++				AC200_EPHY_RESET_INVALID);
++	if (ret)
++		return ret;
++
++	/* This is going via I2C, so there is plenty of built-in delay. */
++	return regmap_set_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++			       AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_assert(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++
++	return regmap_clear_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++				 AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_deassert(struct reset_controller_dev *rcdev,
++			     unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++
++	return regmap_set_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++			       AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_status(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++
++	return regmap_test_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++				AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_reset_of_xlate(struct reset_controller_dev *rcdev,
++				   const struct of_phandle_args *reset_spec)
++{
++	if (WARN_ON(reset_spec->args_count != 0))
++		return -EINVAL;
++
++	return 0;
++}
++
++const struct reset_control_ops ephy_ctl_reset_ops = {
++	.assert		= ephy_ctl_assert,
++	.deassert	= ephy_ctl_deassert,
++	.reset		= ephy_ctl_reset,
++	.status		= ephy_ctl_status,
++};
++
++static void ac200_ephy_ctl_disable(struct ac200_ephy_ctl_dev *priv)
++{
++	regmap_write(priv->regmap, AC200_EPHY_CTL, AC200_EPHY_SHUTDOWN);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1, 0);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
++}
++
++static int ac200_ephy_ctl_probe(struct platform_device *pdev)
++{
++	struct reset_controller_dev *rcdev;
++	struct device *dev = &pdev->dev;
++	struct ac200_ephy_ctl_dev *priv;
++	struct nvmem_cell *calcell;
++	const char *parent_name;
++	phy_interface_t phy_if;
++	u16 *caldata, ephy_ctl;
++	struct clk *clk;
++	size_t callen;
++	u32 value;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, priv);
++
++	priv->regmap = dev_get_regmap(dev->parent, NULL);
++	if (!priv->regmap)
++		return -EPROBE_DEFER;
++
++	calcell = devm_nvmem_cell_get(dev, "calibration");
++	if (IS_ERR(calcell))
++		return dev_err_probe(dev, PTR_ERR(calcell),
++				     "Unable to find calibration data!\n");
++
++	caldata = nvmem_cell_read(calcell, &callen);
++	if (IS_ERR(caldata)) {
++		dev_err(dev, "Unable to read calibration data!\n");
++		return PTR_ERR(caldata);
++	}
++
++	if (callen != 2) {
++		dev_err(dev, "Calibration data length must be 2 bytes!\n");
++		kfree(caldata);
++		return -EINVAL;
++	}
++
++	ephy_ctl = AC200_EPHY_CALIB(*caldata + 3);
++	kfree(caldata);
++
++	ret = of_get_phy_mode(dev->of_node, &phy_if);
++	if (ret) {
++		dev_err(dev, "Unable to read PHY connection mode\n");
++		return ret;
++	}
++
++	switch (phy_if) {
++	case PHY_INTERFACE_MODE_MII:
++		break;
++	case PHY_INTERFACE_MODE_RMII:
++		ephy_ctl |= AC200_EPHY_XMII_SEL;
++		break;
++	default:
++		dev_err(dev, "Illegal PHY connection mode (%d), only RMII or MII supported\n",
++			phy_if);
++		return -EINVAL;
++	}
++
++	ret = of_property_read_u32(dev->of_node, "x-powers,led-polarity",
++				   &value);
++	if (ret) {
++		dev_err(dev, "Unable to read LED polarity setting\n");
++		return ret;
++	}
++
++	if (value == GPIO_ACTIVE_LOW)
++		ephy_ctl |= AC200_EPHY_LED_POL;
++
++	ret = of_property_read_u32(dev->of_node, "phy-address", &value);
++	if (ret) {
++		dev_err(dev, "Unable to read PHY address value\n");
++		return ret;
++	}
++
++	ephy_ctl |= AC200_EPHY_ADDR(value);
++
++	clk = clk_get(dev->parent, NULL);
++	if (IS_ERR(clk))
++		return dev_err_probe(dev, PTR_ERR(clk),
++				     "Unable to obtain the clock\n");
++
++	if (clk_get_rate(clk) == 24000000)
++		ephy_ctl |= AC200_EPHY_CLK_SEL;
++
++	clk_put(clk);
++
++	/* Assert reset and gate clock, to disable PHY for now */
++	ret = regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1,
++			   AC200_EPHY_E_EPHY_MII_IO_EN |
++			   AC200_EPHY_E_LNK_LED_IO_EN |
++			   AC200_EPHY_E_SPD_LED_IO_EN |
++			   AC200_EPHY_E_DPX_LED_IO_EN);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(priv->regmap, AC200_EPHY_CTL, ephy_ctl);
++	if (ret)
++		return ret;
++
++	rcdev = &priv->rcdev;
++	rcdev->owner = dev->driver->owner;
++	rcdev->nr_resets = 1;
++	rcdev->ops = &ephy_ctl_reset_ops;
++	rcdev->of_node = dev->of_node;
++	rcdev->of_reset_n_cells = 0;
++	rcdev->of_xlate = ephy_ctl_reset_of_xlate;
++
++	ret = devm_reset_controller_register(dev, rcdev);
++	if (ret) {
++		dev_err(dev, "Unable to register reset controller: %d\n", ret);
++		goto err_disable_ephy;
++	}
++
++	parent_name = of_clk_get_parent_name(dev->parent->of_node, 0);
++	priv->gate_clk = devm_clk_hw_register_regmap_gate(dev,
++				"ac200-ephy-ctl-gate", parent_name, 0,
++				priv->regmap, AC200_SYS_EPHY_CTL0,
++				AC200_EPHY_SYSCLK_GATING, 0);
++	if (IS_ERR(priv->gate_clk)) {
++		ret = PTR_ERR(priv->gate_clk);
++		dev_err(dev, "Unable to register gate clock: %d\n", ret);
++		goto err_disable_ephy;
++	}
++
++	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
++					  priv->gate_clk);
++	if (ret) {
++		dev_err(dev, "Unable to register clock provider: %d\n", ret);
++		goto err_disable_ephy;
++	}
++
++	return 0;
++
++err_disable_ephy:
++	ac200_ephy_ctl_disable(priv);
++
++	return ret;
++}
++
++static int ac200_ephy_ctl_remove(struct platform_device *pdev)
++{
++	struct ac200_ephy_ctl_dev *priv = platform_get_drvdata(pdev);
++
++	ac200_ephy_ctl_disable(priv);
++
++	return 0;
++}
++
++static const struct of_device_id ac200_ephy_ctl_match[] = {
++	{ .compatible = "x-powers,ac200-ephy-ctl" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_ephy_ctl_match);
++
++static struct platform_driver ac200_ephy_ctl_driver = {
++	.probe		= ac200_ephy_ctl_probe,
++	.remove		= ac200_ephy_ctl_remove,
++	.driver		= {
++		.name		= "ac200-ephy-ctl",
++		.of_match_table	= ac200_ephy_ctl_match,
++	},
++};
++module_platform_driver(ac200_ephy_ctl_driver);
++
++MODULE_AUTHOR("Andre Przywara <andre.przywara@arm.com>");
++MODULE_DESCRIPTION("AC200 Ethernet PHY control driver");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch
new file mode 100644
index 000000000000..60aa0a7ebc28
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch
@@ -0,0 +1,266 @@
+From 8ed81a9342dbbc1f474b479ac2e71a3b93a75c1c Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:21 +0200
+Subject: mfd: Add support for X-Powers AC200
+
+The X-Powers AC200 is a mixed signal multi-purpose chip, which provides
+audio DAC/ADCs, a CVBS video encoder, a 100Mbit/s Ethernet PHY and a
+real-time clock. Its control registers can be accessed via I2C or
+Allwinner's RSB bus.
+Beside this chip being used on some older boards (for instance the Remix
+Mini PC), it is quite wide spread due to its die being co-packaged on the
+Allwinner H6 and H616 SoCs, which use its audio, video and PHY
+functionality.
+
+Aside from the RTC, the other functions do not need constant
+hand-holding via the I2C registers, but rather need to be configured and
+enabled only once.
+
+We model the control side of this chip using the MFD subsystem. This
+driver here just provides the parent device for the various subfunctions,
+and takes care of enabling clocks and reset, but also provides the regmap,
+which the respective child drivers will use.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mfd/Kconfig  |  12 +++
+ drivers/mfd/Makefile |   1 +
+ drivers/mfd/ac200.c  | 190 +++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 203 insertions(+)
+ create mode 100644 drivers/mfd/ac200.c
+
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index 68d71b4b55bd..caed5e75d11f 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -191,6 +191,18 @@ config MFD_AC100
+ 	  This driver include only the core APIs. You have to select individual
+ 	  components like codecs or RTC under the corresponding menus.
+ 
++config MFD_AC200
++	tristate "X-Powers AC200"
++	select MFD_CORE
++	select REGMAP_I2C
++	depends on COMMON_CLK
++	depends on I2C
++	depends on OF
++	help
++	  If you say Y here you get support for the X-Powers AC200 IC.
++	  This driver include only the core APIs. You have to select individual
++	  components like Ethernet PHY or codec under the corresponding menus.
++
+ config MFD_AXP20X
+ 	tristate
+ 	select MFD_CORE
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+index c66f07edcd0e..0c3b4aaf4eb7 100644
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -140,6 +140,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)	+= da9052-spi.o
+ obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
+ 
+ obj-$(CONFIG_MFD_AC100)		+= ac100.o
++obj-$(CONFIG_MFD_AC200)		+= ac200.o
+ obj-$(CONFIG_MFD_AXP20X)	+= axp20x.o
+ obj-$(CONFIG_MFD_AXP20X_I2C)	+= axp20x-i2c.o
+ obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
+diff --git a/drivers/mfd/ac200.c b/drivers/mfd/ac200.c
+new file mode 100644
+index 000000000000..ad28c380c880
+--- /dev/null
++++ b/drivers/mfd/ac200.c
+@@ -0,0 +1,190 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * MFD core driver for X-Powers' AC200 IC
++ *
++ * The AC200 is a chip which is co-packaged with Allwinner H6 SoC and
++ * includes analog audio codec, analog TV encoder, ethernet PHY, eFuse
++ * and RTC.
++ *
++ * Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@gmail.com>
++ *
++ * Based on AC100 driver with following copyrights:
++ * Copyright (2016) Chen-Yu Tsai
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/i2c.h>
++#include <linux/kernel.h>
++#include <linux/mfd/core.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/regmap.h>
++
++struct ac200_dev {
++	struct clk	*clk;
++	struct regmap	*regmap;
++};
++
++#define AC200_SYS_CONTROL	0x0002
++#define AC200_SYS_BG_CTL	0x0050
++
++/* interface register (can be accessed from any page) */
++#define AC200_TWI_REG_ADDR_H	0xFE
++
++#define AC200_MAX_REG		0xA1F2
++
++static const struct regmap_range_cfg ac200_range_cfg[] = {
++	{
++		.range_max = AC200_MAX_REG,
++		.selector_reg = AC200_TWI_REG_ADDR_H,
++		.selector_mask = 0xff,
++		.selector_shift = 0,
++		.window_start = 0,
++		.window_len = 256,
++	}
++};
++
++static const struct regmap_config ac200_regmap_config = {
++	.name		= "AC200",
++	.reg_bits	= 8,
++	.reg_stride	= 2,
++	.val_bits	= 16,
++	.ranges		= ac200_range_cfg,
++	.num_ranges	= ARRAY_SIZE(ac200_range_cfg),
++	.max_register	= AC200_MAX_REG,
++};
++
++static struct mfd_cell ac200_cells[] = {
++	{
++		.name		= "ac200-codec",
++		.of_compatible	= "x-powers,ac200-codec",
++	}, {
++		.name		= "ac200-ephy-ctl",
++		.of_compatible	= "x-powers,ac200-ephy-ctl",
++	},
++};
++
++static int ac200_i2c_probe(struct i2c_client *i2c)
++{
++	struct device *dev = &i2c->dev;
++	struct nvmem_cell *bgcell;
++	struct ac200_dev *ac200;
++	u16 *bgdata, bgval;
++	size_t bglen;
++	int ret;
++
++	ac200 = devm_kzalloc(dev, sizeof(*ac200), GFP_KERNEL);
++	if (!ac200)
++		return -ENOMEM;
++
++	i2c_set_clientdata(i2c, ac200);
++
++	ac200->clk = devm_clk_get(dev, NULL);
++	if (IS_ERR(ac200->clk))
++		return dev_err_probe(dev, PTR_ERR(ac200->clk),
++				     "Can't obtain the clock\n");
++
++	ac200->regmap = devm_regmap_init_i2c(i2c, &ac200_regmap_config);
++	if (IS_ERR(ac200->regmap)) {
++		ret = PTR_ERR(ac200->regmap);
++		dev_err(dev, "Regmap init failed: %d\n", ret);
++		return ret;
++	}
++
++	bgcell = devm_nvmem_cell_get(dev, "bandgap");
++	if (IS_ERR(bgcell))
++		return dev_err_probe(dev, PTR_ERR(bgcell),
++				     "Unable to find bandgap data!\n");
++
++	bgdata = nvmem_cell_read(bgcell, &bglen);
++	if (IS_ERR(bgdata)) {
++		dev_err(dev, "Unable to read bandgap data!\n");
++		return PTR_ERR(bgdata);
++	}
++
++	if (bglen != 2) {
++		dev_err(dev, "Invalid nvmem bandgap length!\n");
++		kfree(bgdata);
++		return -EINVAL;
++	}
++
++	bgval = *bgdata;
++	kfree(bgdata);
++
++	ret = clk_prepare_enable(ac200->clk);
++	if (ret)
++		return ret;
++
++	/*
++	 * There is no documentation on how long we have to wait before
++	 * executing first operation. Vendor driver sleeps for 40 ms.
++	 */
++	msleep(40);
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++	if (ret)
++		goto err;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++	if (ret)
++		goto err;
++
++	if (bgval) {
++		/* bandgap register is not documented */
++		ret = regmap_write(ac200->regmap, AC200_SYS_BG_CTL,
++				   0x8280 | bgval);
++		if (ret)
++			goto err;
++	}
++
++	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ac200_cells,
++				   ARRAY_SIZE(ac200_cells), NULL, 0, NULL);
++	if (ret) {
++		dev_err(dev, "Failed to add MFD devices: %d\n", ret);
++		goto err;
++	}
++
++	return 0;
++
++err:
++	clk_disable_unprepare(ac200->clk);
++	return ret;
++}
++
++static void ac200_i2c_remove(struct i2c_client *i2c)
++{
++	struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++	regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++
++	clk_disable_unprepare(ac200->clk);
++}
++
++static const struct i2c_device_id ac200_ids[] = {
++	{ "ac200", },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ac200_ids);
++
++static const struct of_device_id ac200_of_match[] = {
++	{ .compatible = "x-powers,ac200" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ac200_of_match);
++
++static struct i2c_driver ac200_i2c_driver = {
++	.driver = {
++		.name	= "ac200",
++		.of_match_table	= of_match_ptr(ac200_of_match),
++	},
++	.probe	= ac200_i2c_probe,
++	.remove = ac200_i2c_remove,
++	.id_table = ac200_ids,
++};
++module_i2c_driver(ac200_i2c_driver);
++
++MODULE_DESCRIPTION("MFD core driver for AC200");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@gmail.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch
new file mode 100644
index 000000000000..a901ce9ee391
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch
@@ -0,0 +1,43 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ukhellfire <afaulkner420@gmail.com>
+Date: Thu, 24 Mar 2022 22:21:00 +0000
+Subject: mmc/host/sunxi-mmc: Fix H6 emmc
+
+We have the wrong MMC CAP voltage for the emmc on this board
+---
+ drivers/mmc/host/sunxi-mmc.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index 7f336908a21c..a2747093de99 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1233,6 +1233,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
+ 	{ .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg },
+ 	{ .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
+ 	{ .compatible = "allwinner,sun50i-h5-emmc", .data = &sun50i_h5_emmc_cfg },
++	{ .compatible = "allwinner,sun50i-h6-emmc", .data = &sun50i_a64_emmc_cfg },
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
+@@ -1444,7 +1445,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 				  MMC_CAP_SDIO_IRQ;
+ 
+ 	/*
+-	 * Some H5 devices do not have signal traces precise enough to
++	 * Some H5 and H6 devices do not have signal traces precise enough to
+ 	 * use HS DDR mode for their eMMC chips.
+ 	 *
+ 	 * We still enable HS DDR modes for all the other controller
+@@ -1453,6 +1454,8 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 	if ((host->cfg->clk_delays || host->use_new_timings) &&
+ 	    !of_device_is_compatible(pdev->dev.of_node,
+ 				     "allwinner,sun50i-h5-emmc") &&
++	    !of_device_is_compatible(pdev->dev.of_node,
++				     "allwinner,sun50i-h6-emmc") &&
+ 	    !of_machine_is_compatible("allwinner,sun7i-a20") &&
+ 	    !of_machine_is_compatible("olimex,a64-olinuxino-2ge8g"))
+ 		mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch
new file mode 100644
index 000000000000..7d27ee1de581
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch
@@ -0,0 +1,143 @@
+From f6ae01c5de09c0051590465c37d62ab625a1db28 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:57 +0200
+Subject: net: phy: Add support for AC200 EPHY
+
+The X-Powers AC200 mixed signal chip contains a 100Mbit/s Ethernet PHY.
+While its sporting a usable default setup, and can be controlled by the
+generic IEEE802.3-C22 PHY driver, the BSP sets up some extra registers,
+which this driver here covers.
+
+Add a PHY driver matching the AC200 EPHY ID registers, and which
+programs some PHY registers according to the BSP code.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/net/phy/Kconfig     |  7 ++++
+ drivers/net/phy/Makefile    |  1 +
+ drivers/net/phy/ac200-phy.c | 82 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 90 insertions(+)
+ create mode 100644 drivers/net/phy/ac200-phy.c
+
+diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
+index 107880d13d21..43edfd9d61dc 100644
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -76,6 +76,13 @@ config SFP
+ 
+ comment "MII PHY device drivers"
+ 
++config AC200_PHY
++	tristate "AC200 EPHY"
++	depends on NVMEM
++	depends on OF
++	help
++	  Fast ethernet PHY as found in X-Powers AC200 multi-function device.
++
+ config AMD_PHY
+ 	tristate "AMD and Altima PHYs"
+ 	help
+diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
+index c945ed9bd14b..e5a46da678ff 100644
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -32,6 +32,7 @@ obj-$(CONFIG_SFP)		+= sfp.o
+ sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
+ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
++obj-$(CONFIG_AC200_PHY)		+= ac200-phy.o
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+diff --git a/drivers/net/phy/ac200-phy.c b/drivers/net/phy/ac200-phy.c
+new file mode 100644
+index 000000000000..8499914f49b8
+--- /dev/null
++++ b/drivers/net/phy/ac200-phy.c
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: GPL-2.0+
++/**
++ * Driver for AC200 Ethernet PHY
++ *
++ * Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@gmail.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/phy.h>
++
++#define AC200_EPHY_ID			0x00441400
++#define AC200_EPHY_ID_MASK		0x0ffffff0
++
++static int ac200_ephy_config_init(struct phy_device *phydev)
++{
++	phy_write(phydev, 0x1f, 0x0100);	/* Switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824);	/* Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200);	/* Switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000);	/* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600);	/* Switch to Page 6 */
++	phy_write(phydev, 0x14, 0x708f);	/* PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xF000);	/* PHYAFE RX optimization */
++	phy_write(phydev, 0x15, 0x1530);
++
++	phy_write(phydev, 0x1f, 0x0800);	/* Switch to Page 8 */
++	phy_write(phydev, 0x18, 0x00bc);	/* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0100);	/* switch to page 1 */
++	phy_clear_bits(phydev, 0x17, BIT(3));	/* disable intelligent EEE */
++
++	/* disable 802.3az EEE */
++	phy_write(phydev, 0x1f, 0x0200);	/* switch to page 2 */
++	phy_write(phydev, 0x18, 0x0000);
++	phy_write(phydev, 0x1f, 0x0000);	/* switch to page 0 */
++	phy_clear_bits_mmd(phydev, 0x7, 0x3c, BIT(1));
++
++	/* FIXME: This is probably H6 specific */
++	phy_set_bits(phydev, 0x13, BIT(12));
++
++	return 0;
++}
++
++static int ac200_ephy_probe(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct clk *clk;
++
++	clk = devm_clk_get_optional_enabled(dev, NULL);
++	if (IS_ERR(clk))
++		return dev_err_probe(dev, PTR_ERR(clk),
++				     "Failed to request clock\n");
++
++	return 0;
++}
++
++static struct phy_driver ac200_ephy_driver[] = {
++	{
++		.phy_id		= AC200_EPHY_ID,
++		.phy_id_mask	= AC200_EPHY_ID_MASK,
++		.name		= "Allwinner AC200 EPHY",
++		.soft_reset	= genphy_soft_reset,
++		.config_init	= ac200_ephy_config_init,
++		.probe		= ac200_ephy_probe,
++		.suspend	= genphy_suspend,
++		.resume		= genphy_resume,
++	}
++};
++module_phy_driver(ac200_ephy_driver);
++
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@gmail.com>");
++MODULE_DESCRIPTION("AC200 Ethernet PHY driver");
++MODULE_LICENSE("GPL");
++
++static const struct mdio_device_id __maybe_unused ac200_ephy_phy_tbl[] = {
++	{ AC200_EPHY_ID, AC200_EPHY_ID_MASK },
++	{ }
++};
++MODULE_DEVICE_TABLE(mdio, ac200_ephy_phy_tbl);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch
new file mode 100644
index 000000000000..d63ba081d7dd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch
@@ -0,0 +1,79 @@
+From 77997cebd91e706546a64e9a3a7856d9dce209d9 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 26 Jul 2020 02:38:31 +0200
+Subject: net: usb: r8152: add LED configuration from OF
+
+This adds the ability to configure the LED configuration register using
+OF. This way, the correct value for board specific LED configuration can
+be determined.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/net/usb/r8152.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
+index 127b34dcc5b3..8099556fef85 100644
+--- a/drivers/net/usb/r8152.c
++++ b/drivers/net/usb/r8152.c
+@@ -12,6 +12,7 @@
+ #include <linux/ethtool.h>
+ #include <linux/phy.h>
+ #include <linux/usb.h>
++#include <linux/of.h>
+ #include <linux/crc32.h>
+ #include <linux/if_vlan.h>
+ #include <linux/uaccess.h>
+@@ -7036,6 +7037,22 @@ static void rtl_tally_reset(struct r8152 *tp)
+ 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
+ }
+ 
++static int r8152_led_configuration(struct r8152 *tp)
++{
++	u32 led_data;
++	int ret;
++
++	ret = of_property_read_u32(tp->udev->dev.of_node, "realtek,led-data",
++								&led_data);
++
++	if (ret)
++		return ret;
++	
++	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data);
++
++	return 0;
++}
++
+ static void r8152b_init(struct r8152 *tp)
+ {
+ 	u32 ocp_data;
+@@ -7077,6 +7094,8 @@ static void r8152b_init(struct r8152 *tp)
+ 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
+ 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
+ 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153_init(struct r8152 *tp)
+@@ -7217,6 +7236,8 @@ static void r8153_init(struct r8152 *tp)
+ 		tp->coalesce = COALESCE_SLOW;
+ 		break;
+ 	}
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153b_init(struct r8152 *tp)
+@@ -7299,6 +7320,8 @@ static void r8153b_init(struct r8152 *tp)
+ 	rtl_tally_reset(tp);
+ 
+ 	tp->coalesce = 15000;	/* 15 us */
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153c_init(struct r8152 *tp)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch
new file mode 100644
index 000000000000..64d2f95be2a2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch
@@ -0,0 +1,58 @@
+From e1af11511f4985906856ae422e7a01b251cb3b86 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 16 Apr 2022 11:19:05 +0300
+Subject: nvmem: sunxi_sid: add sunxi_get_soc_chipid, sunxi_get_serial
+
+---
+ drivers/nvmem/sunxi_sid.c | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
+index c13112b9149b..f29fac7edef9 100644
+--- a/drivers/nvmem/sunxi_sid.c
++++ b/drivers/nvmem/sunxi_sid.c
+@@ -36,6 +36,25 @@ struct sunxi_sid {
+ 	u32			value_offset;
+ };
+ 
++static unsigned int sunxi_soc_chipid[4];
++static unsigned int sunxi_serial[4];
++
++int sunxi_get_soc_chipid(unsigned char *chipid)
++{
++	memcpy(chipid, sunxi_soc_chipid, 16);
++
++	return 0;
++}
++EXPORT_SYMBOL(sunxi_get_soc_chipid);
++
++int sunxi_get_serial(unsigned       char *serial)
++{
++	memcpy(serial, sunxi_serial, 16);
++
++	return 0;
++}
++EXPORT_SYMBOL(sunxi_get_serial);
++
+ static int sunxi_sid_read(void *context, unsigned int offset,
+ 			  void *val, size_t bytes)
+ {
+@@ -178,6 +197,15 @@ static int sunxi_sid_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, nvmem);
+ 
++	nvmem_cfg->reg_read(sid, 0, &sunxi_soc_chipid[0], sizeof(int));
++	nvmem_cfg->reg_read(sid, 4, &sunxi_soc_chipid[1], sizeof(int));
++	nvmem_cfg->reg_read(sid, 8, &sunxi_soc_chipid[2], sizeof(int));
++	nvmem_cfg->reg_read(sid, 12, &sunxi_soc_chipid[3], sizeof(int));
++
++	sunxi_serial[0] = sunxi_soc_chipid[3];
++	sunxi_serial[1] = sunxi_soc_chipid[2];
++	sunxi_serial[2] = (sunxi_soc_chipid[1] >> 16) & 0x0ffff;
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/scripts-add-overlay-compilation-support.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/scripts-add-overlay-compilation-support.patch
new file mode 100644
index 000000000000..c0230bbf44cf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/scripts-add-overlay-compilation-support.patch
@@ -0,0 +1,92 @@
+From 0c6d5024ccc3eb01faf94ce0b181a8b46718b5f6 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 21:04:08 +0300
+Subject: scripts: add overlay compilation support
+
+---
+ .gitignore               |  1 +
+ scripts/Makefile.dtbinst | 10 +++++++++-
+ scripts/Makefile.lib     | 12 +++++++++++-
+ 3 files changed, 21 insertions(+), 2 deletions(-)
+
+diff --git a/.gitignore b/.gitignore
+index c59dc60ba62e..e11167ab9d44 100644
+--- a/.gitignore
++++ b/.gitignore
+@@ -42,6 +42,7 @@
+ *.rpm
+ *.rsi
+ *.s
++*.scr
+ *.so
+ *.so.dbg
+ *.su
+diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
+index 9d920419a62c..0b674435f63a 100644
+--- a/scripts/Makefile.dtbinst
++++ b/scripts/Makefile.dtbinst
+@@ -22,7 +22,15 @@ quiet_cmd_dtb_install = INSTALL $@
+ $(dst)/%: $(obj)/%
+ 	$(call cmd,dtb_install)
+ 
++$(dst)/%.scr: $(obj)/%.scr
++	$(call cmd,dtb_install)
++
++$(dst)/README.%-overlays: $(obj)/README.%-overlays
++	$(call cmd,dtb_install)
++
+ dtbs := $(patsubst $(obj)/%,%,$(call read-file, $(obj)/dtbs-list))
++script-files	:= $(addprefix $(dst)/, $(scr-y))
++readme-files	:= $(addprefix $(dst)/, $(dtbotxt-y))
+ 
+ ifdef CONFIG_ARCH_WANT_FLAT_DTB_INSTALL
+ 
+@@ -37,7 +45,7 @@ dtbs := $(notdir $(dtbs))
+ 
+ endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL
+ 
+-__dtbs_install: $(addprefix $(dst)/, $(dtbs))
++__dtbs_install: $(addprefix $(dst)/, $(dtbs)) $(script-files) $(readme-files)
+ 	@:
+ 
+ .PHONY: $(PHONY)
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 3179747cbd2c..34e80ae7daeb 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -93,6 +93,9 @@ base-dtb-y := $(filter %.dtb, $(call real-search, $(multi-dtb-y), .dtb, -dtbs))
+ 
+ always-y			+= $(dtb-y)
+ 
++# Overlay Fixup script targets
++extra-y				+= $(scr-y) $(dtbotxt-y)
++
+ # Add subdir path
+ 
+ ifneq ($(obj),.)
+@@ -370,7 +373,8 @@ DTC_FLAGS += -Wnode_name_chars_strict \
+ 	-Wunique_unit_address
+ endif
+ 
+-DTC_FLAGS += $(DTC_FLAGS_$(target-stem))
++DTC_FLAGS += $(DTC_FLAGS_$(target-stem)) \
++	-@
+ 
+ # Set -@ if the target is a base DTB that overlay is applied onto
+ DTC_FLAGS += $(if $(filter $(patsubst $(obj)/%,%,$@), $(base-dtb-y)), -@)
+@@ -429,6 +433,12 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE
+ $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
+ 	$(call if_changed_dep,dtc)
+ 
++quiet_cmd_scr = MKIMAGE $@
++      cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
++
++$(obj)/%.scr: $(src)/%.scr-cmd FORCE
++	$(call if_changed,scr)
++
+ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+ 
+ # Bzip2
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch
new file mode 100644
index 000000000000..1e2703e0a273
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: wuweidong <625769020@qq.com>
+Date: Tue, 28 Nov 2017 17:25:19 +0800
+Subject: sound:soc:sunxi: Provoke the early load of sun8i-codec-analog
+
+---
+ sound/soc/sunxi/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
+index 0dccdaa35bec..b0b976a3d069 100644
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -1,9 +1,9 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
+ obj-$(CONFIG_SND_AC100_CODEC) += ac100-codec.o
+ obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-codec.o
+ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
+ obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+-obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
+ obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
+ obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+ obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch
new file mode 100644
index 000000000000..b5d774979c58
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch
@@ -0,0 +1,120 @@
+From ba6f9ed11e62e17513268319cc6d78f9d966b38b Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:42:37 +0300
+Subject: sound:soc:sunxi:sun4i-codec adcis select capture source
+
+---
+ sound/soc/sunxi/sun4i-codec.c | 51 ++++++++++++++++++++++++++++++++---
+ 1 file changed, 47 insertions(+), 4 deletions(-)
+
+diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
+index a2618ed650b0..ac2a855bee5d 100644
+--- a/sound/soc/sunxi/sun4i-codec.c
++++ b/sound/soc/sunxi/sun4i-codec.c
+@@ -5,6 +5,7 @@
+  * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
+  * Copyright 2015 Adam Sampson <ats@offog.org>
+  * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
++ * Copyright 2021 gryzun <gryzun_an@rambler.ru>
+  *
+  * Based on the Allwinner SDK driver, released under the GPL.
+  */
+@@ -654,6 +655,16 @@ static struct snd_soc_dai_driver sun4i_codec_dai = {
+ };
+ 
+ /*** sun4i Codec ***/
++
++static const char *adcis_text[] = {"Line In", "FM In", "Mic1 Mono", "Mic2 Mono",
++			"Mic1,Mic2", "Mic1+2 Mono", "MIX Out", "Line,Mic1"};
++
++static SOC_ENUM_SINGLE_DECL(adcis_mixer, SUN4I_CODEC_ADC_ACTL,
++					SUN4I_CODEC_ADC_ACTL_ADCIS, adcis_text);
++
++static const struct snd_kcontrol_new sun4i_codec_mux_controls =
++	SOC_DAPM_ENUM("Capture Source Capture Route", adcis_mixer);
++
+ static const struct snd_kcontrol_new sun4i_codec_pa_mute =
+ 	SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL,
+ 			SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0);
+@@ -667,6 +678,8 @@ static DECLARE_TLV_DB_SCALE(sun4i_codec_fmin_loopback_gain_scale, -450, 150,
+ 			    0);
+ static DECLARE_TLV_DB_SCALE(sun4i_codec_micin_loopback_gain_scale, -450, 150,
+ 			    0);
++static DECLARE_TLV_DB_SCALE(sun4i_codec_capture_gain_scale, -450, 150,
++			    0);
+ static DECLARE_TLV_DB_RANGE(sun4i_codec_micin_preamp_gain_scale,
+ 			    0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+ 			    1, 7, TLV_DB_SCALE_ITEM(3500, 300, 0));
+@@ -720,6 +733,9 @@ static const struct snd_kcontrol_new sun7i_codec_controls[] = {
+ 	SOC_SINGLE_TLV("Mic2 Boost Volume", SUN7I_CODEC_AC_MIC_PHONE_CAL,
+ 		       SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG2, 7, 0,
+ 		       sun7i_codec_micin_preamp_gain_scale),
++	SOC_SINGLE_TLV("Capture Boost Capture Volume", SUN4I_CODEC_ADC_ACTL,
++		       SUN4I_CODEC_ADC_ACTL_VADCG, 7, 0,
++		       sun4i_codec_capture_gain_scale),
+ };
+ 
+ static const struct snd_kcontrol_new sun4i_codec_mixer_controls[] = {
+@@ -798,6 +814,13 @@ static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = {
+ 	SND_SOC_DAPM_PGA("MIC2 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
+ 			 SUN4I_CODEC_ADC_ACTL_PREG2EN, 0, NULL, 0),
+ 
++	/* ADC Mux */
++	SND_SOC_DAPM_MUX("Right Capture Source Capture Route", SND_SOC_NOPM, 0, 0,
++		&sun4i_codec_mux_controls),
++
++	SND_SOC_DAPM_MUX("Left Capture Source Capture Route", SND_SOC_NOPM, 0, 0,
++		&sun4i_codec_mux_controls),
++
+ 	/* Power Amplifier */
+ 	SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL,
+ 			   SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
+@@ -826,6 +849,30 @@ static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = {
+ 	{ "Right ADC", NULL, "ADC" },
+ 	{ "Right DAC", NULL, "DAC" },
+ 
++	/* Left Mux Capture Routes */
++	{ "Left Capture Source Capture Route", "Mic1 Mono", "MIC1 Pre-Amplifier" },
++	{ "Left Capture Source Capture Route", "Mic2 Mono", "MIC2 Pre-Amplifier" },
++	{ "Left Capture Source Capture Route", "Line In", "Line Left" },
++	{ "Left Capture Source Capture Route", "FM In", "FM Left" },
++	{ "Left Capture Source Capture Route", "MIX Out", "Left Mixer" },
++	{ "Left Capture Source Capture Route", "Mic1,Mic2", "MIC1 Pre-Amplifier" },
++	{ "Left Capture Source Capture Route", "Mic1+2 Mono", "MIC1 Pre-Amplifier" },
++	{ "Left Capture Source Capture Route", "Mic1+2 Mono", "MIC2 Pre-Amplifier" },
++	{ "Left Capture Source Capture Route", "Line,Mic1", "Line Left" },
++	{ "Left ADC", NULL, "Left Capture Source Capture Route" },
++
++	/* Right Mux Capture Routes */
++	{ "Right Capture Source Capture Route", "Mic1 Mono", "MIC1 Pre-Amplifier" },
++	{ "Right Capture Source Capture Route", "Mic2 Mono", "MIC2 Pre-Amplifier" },
++	{ "Right Capture Source Capture Route", "Line In", "Line Right" },
++	{ "Right Capture Source Capture Route", "FM In", "FM Right" },
++	{ "Right Capture Source Capture Route", "MIX Out", "Right Mixer" },
++	{ "Right Capture Source Capture Route", "Mic1,Mic2", "MIC2 Pre-Amplifier" },
++	{ "Right Capture Source Capture Route", "Mic1+2 Mono", "MIC1 Pre-Amplifier" },
++	{ "Right Capture Source Capture Route", "Mic1+2 Mono", "MIC2 Pre-Amplifier" },
++	{ "Right Capture Source Capture Route", "Line,Mic1", "MIC1 Pre-Amplifier" },
++	{ "Right ADC", NULL, "Right Capture Source Capture Route" },
++
+ 	/* Right Mixer Routes */
+ 	{ "Right Mixer", NULL, "Mixer Enable" },
+ 	{ "Right Mixer", "Right Mixer Left DAC Playback Switch", "Left DAC" },
+@@ -855,14 +902,10 @@ static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = {
+ 	{ "HP Left", NULL, "Power Amplifier Mute" },
+ 
+ 	/* Mic1 Routes */
+-	{ "Left ADC", NULL, "MIC1 Pre-Amplifier" },
+-	{ "Right ADC", NULL, "MIC1 Pre-Amplifier" },
+ 	{ "MIC1 Pre-Amplifier", NULL, "Mic1"},
+ 	{ "Mic1", NULL, "VMIC" },
+ 
+ 	/* Mic2 Routes */
+-	{ "Left ADC", NULL, "MIC2 Pre-Amplifier" },
+-	{ "Right ADC", NULL, "MIC2 Pre-Amplifier" },
+ 	{ "MIC2 Pre-Amplifier", NULL, "Mic2"},
+ 	{ "Mic2", NULL, "VMIC" },
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-sun4i-spdif-add-mclk_multiplier.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-sun4i-spdif-add-mclk_multiplier.patch
new file mode 100644
index 000000000000..b5074e7691da
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-sun4i-spdif-add-mclk_multiplier.patch
@@ -0,0 +1,69 @@
+From 1351eabe9d80d112adb5cad75479c647511e2acb Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 23 Jan 2022 22:22:39 +0300
+Subject: sound:soc:sunxi:sun4i-spdif add mclk_multiplier
+
+---
+ sound/soc/sunxi/sun4i-spdif.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/sound/soc/sunxi/sun4i-spdif.c b/sound/soc/sunxi/sun4i-spdif.c
+index f41c30955857..93470617ffc2 100644
+--- a/sound/soc/sunxi/sun4i-spdif.c
++++ b/sound/soc/sunxi/sun4i-spdif.c
+@@ -176,6 +176,7 @@ struct sun4i_spdif_quirks {
+ 	unsigned int reg_dac_txdata;
+ 	bool has_reset;
+ 	unsigned int val_fctl_ftx;
++	unsigned int mclk_multiplier;
+ };
+ 
+ struct sun4i_spdif_dev {
+@@ -313,6 +314,7 @@ static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
+ 	default:
+ 		return -EINVAL;
+ 	}
++	mclk *= host->quirks->mclk_multiplier;
+ 
+ 	ret = clk_set_rate(host->spdif_clk, mclk);
+ 	if (ret < 0) {
+@@ -347,6 +349,7 @@ static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
+ 	default:
+ 		return -EINVAL;
+ 	}
++	mclk_div *= host->quirks->mclk_multiplier;
+ 
+ 	reg_val = 0;
+ 	reg_val |= SUN4I_SPDIF_TXCFG_ASS;
+@@ -540,24 +543,28 @@ static struct snd_soc_dai_driver sun4i_spdif_dai = {
+ static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
+ 	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
++	.mclk_multiplier = 1,
+ };
+ 
+ static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
+ 	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
+ 	.has_reset	= true,
++	.mclk_multiplier = 1,
+ };
+ 
+ static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
+ 	.reg_dac_txdata	= SUN8I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
+ 	.has_reset	= true,
++	.mclk_multiplier = 4,
+ };
+ 
+ static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
+ 	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
+ 	.has_reset      = true,
++	.mclk_multiplier = 1,
+ };
+ 
+ static const struct of_device_id sun4i_spdif_of_match[] = {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch b/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch
new file mode 100644
index 000000000000..cf22c7b3ecb0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch
@@ -0,0 +1,31 @@
+From fa53739fad82d70148e1c942da553f5236122902 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 13:04:18 +0300
+Subject: sound:soc:sunxi:sun8i-codec-analog enable sound
+
+---
+ sound/soc/sunxi/sun8i-codec-analog.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/sunxi/sun8i-codec-analog.c b/sound/soc/sunxi/sun8i-codec-analog.c
+index 445b34141896..0fd8de06e216 100644
+--- a/sound/soc/sunxi/sun8i-codec-analog.c
++++ b/sound/soc/sunxi/sun8i-codec-analog.c
+@@ -728,8 +728,12 @@ static int sun8i_codec_analog_add_mixer(struct snd_soc_component *cmpnt,
+ }
+ 
+ static const struct sun8i_codec_analog_quirks sun8i_v3s_quirks = {
+-	.has_headphone	= true,
+-	.has_hmic	= true,
++	.has_headphone  = true,
++	.has_hmic       = true,
++	.has_linein     = true,
++	.has_lineout    = true,
++	.has_mbias      = true,
++	.has_mic2       = true,
+ };
+ 
+ static int sun8i_codec_analog_cmpnt_probe(struct snd_soc_component *cmpnt)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
new file mode 100644
index 000000000000..6ceb8f557823
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
@@ -0,0 +1,31 @@
+From 133ac821f592bc7255cd3e031ea7416f1b3b2438 Mon Sep 17 00:00:00 2001
+From: Arnav Singh <me@arnavion.dev>
+Date: Mon, 6 May 2024 16:36:06 -0700
+Subject: arm64: dts: sun50i: Define orientation and rotation for PinePhone
+ front camera
+
+This enables libcamera to detect the correct orientation from
+the device tree and propagate it further to e.g. Pipewire.
+
+Signed-off-by: Arnav Singh <me@arnavion.dev>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index a2e9c65eae2d..4d3931f83b6b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -586,6 +586,9 @@ gc2145: front-camera@3c {
+ 		reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
+ 		enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
+ 
++		orientation = <0>;
++		rotation = <90>;
++
+ 		port {
+ 			gc2145_ep: endpoint {
+ 				remote-endpoint = <&csi_gc2145_ep>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-axp813-Add-charger-LED.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-axp813-Add-charger-LED.patch
new file mode 100644
index 000000000000..d90d8c894a35
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-axp813-Add-charger-LED.patch
@@ -0,0 +1,30 @@
+From ed5832ca06a102aa6a6240973f87bf072bb00198 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 14 Nov 2017 02:47:51 +0100
+Subject: ARM: dts: axp813: Add charger LED
+
+PMIC supports charging status indication via a LED. Add support
+for it.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/axp81x.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/axp81x.dtsi b/arch/arm/boot/dts/allwinner/axp81x.dtsi
+index ebaf1c3ce8db..a4b1be159b02 100644
+--- a/arch/arm/boot/dts/allwinner/axp81x.dtsi
++++ b/arch/arm/boot/dts/allwinner/axp81x.dtsi
+@@ -161,4 +161,9 @@ reg_drivevbus: drivevbus {
+ 	usb_power_supply: usb-power {
+ 		compatible = "x-powers,axp813-usb-power-supply";
+ 	};
++
++	charger_led: charger-led {
++		compatible = "x-powers,axp813-charger-led";
++		status = "disabled";
++	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
new file mode 100644
index 000000000000..f7190bf1a4e2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
@@ -0,0 +1,39 @@
+From 6643bad42776163c1d1522c02ec9692200a8b3f1 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 3 Apr 2021 20:53:26 -0500
+Subject: ARM: dts: sun8i: a83t: Add MBUS node
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 8ef86b688b87..17c007076d4d 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -1056,6 +1056,21 @@ mdio: mdio {
+ 			};
+ 		};
+ 
++		mbus: dram-controller@1c62000 {
++			compatible = "allwinner,sun8i-a83t-mbus";
++			reg = <0x01c62000 0x1000>,
++			      <0x01c63000 0x1000>;
++			reg-names = "mbus", "dram";
++			clocks = <&ccu CLK_BUS_DRAM>,
++				 <&ccu CLK_DRAM>,
++				 <&ccu CLK_MBUS>;
++			clock-names = "apb", "dram", "mbus";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
++			#interconnect-cells = <1>;
++		};
++
+ 		gic: interrupt-controller@1c81000 {
+ 			compatible = "arm,gic-400";
+ 			reg = <0x01c81000 0x1000>,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
new file mode 100644
index 000000000000..6ee7c2cae65e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
@@ -0,0 +1,37 @@
+From 8f5216b248b737f804e79d6a94a2d1fbc9c493ce Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 9 Sep 2019 06:02:10 +0200
+Subject: ARM: dts: sun8i-a83t: Add cedrus video codec support to A83T
+ [untested]
+
+Not tested at all.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 94eb3bfc989e..abf926163cc9 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -441,6 +441,16 @@ syscon: syscon@1c00000 {
+ 			reg = <0x01c00000 0x1000>;
+ 		};
+ 
++		video-codec@01c0e000 {
++			compatible = "allwinner,sun8i-a83t-video-engine";
++			reg = <0x01c0e000 0x1000>;
++			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
++				 <&ccu CLK_DRAM_VE>;
++			clock-names = "ahb", "mod", "ram";
++			resets = <&ccu RST_BUS_VE>;
++			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
+ 		dma: dma-controller@1c02000 {
+ 			compatible = "allwinner,sun8i-a83t-dma";
+ 			reg = <0x01c02000 0x1000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..3ad81f226ade
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From e21dd926bad02ab8b8a13f53eb5dbd67898a316a Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:32:57 +0200
+Subject: ARM: dts: sun8i: a83t: Add hdmi sound card
+
+A83t support HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index cb698c5a40c2..045f7b4f6253 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -150,6 +150,20 @@ cpu103: cpu@103 {
+ 		};
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun8i-a83t-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv7-timer";
+ 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+@@ -1059,6 +1073,7 @@ csi: camera@1cb0000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+ 			reg-io-width = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
new file mode 100644
index 000000000000..d772f871c6e5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
@@ -0,0 +1,35 @@
+From 46fe431cea08295e59482241bc30c8000f8595aa Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 13 Mar 2023 06:02:27 +0100
+Subject: ARM: dts: sun8i-a83t: Add missing GPU trip point
+
+Without this, thermal sensor driver fails to probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 0ea31e3e41af..83a9b129bb5d 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -1309,6 +1309,15 @@ gpu_thermal: gpu-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 2>;
++
++			trips {
++				gpu_crit: gpu-crit {
++					/* milliCelsius */
++					temperature = <100000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
+ 		};
+ 	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
new file mode 100644
index 000000000000..b9ba027f193e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
@@ -0,0 +1,69 @@
+From 9ac57706746cacda2cdbdcc218eebc87820e47f1 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:34:43 +0200
+Subject: ARM: dts: sun8i: a83t: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all A83t boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts    | 8 ++++++++
+ .../arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts | 8 ++++++++
+ 2 files changed, 16 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts
+index 8d56b103f063..19bd06860e6a 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts
+@@ -162,6 +162,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -380,6 +384,10 @@ &reg_sw {
+ 	regulator-name = "vcc-ephy";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts
+index 870993393fc2..1a5a8a638499 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts
+@@ -197,6 +197,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -417,6 +421,10 @@ &reg_sw {
+ 	regulator-name = "vcc-wifi-io";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spdif {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
new file mode 100644
index 000000000000..a83fd30382e9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
@@ -0,0 +1,134 @@
+From 3354efaf6cb5978d4834ca06fdb2e377c84ad892 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 1 Sep 2019 23:56:49 +0200
+Subject: ARM: dts: sun8i-a83t: Improve CPU OPP tables (go up to 1.8GHz)
+
+This table is for the worst SoC bin, so it should work on all A83T
+bins.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 80 ++++++---------------
+ 1 file changed, 22 insertions(+), 58 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 94eb3bfc989e..0a7aadf2b208 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -210,45 +210,27 @@ opp-480000000 {
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-600000000 {
+-			opp-hz = /bits/ 64 <600000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-720000000 {
+-			opp-hz = /bits/ 64 <720000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-864000000 {
+-			opp-hz = /bits/ 64 <864000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-912000000 {
+-			opp-hz = /bits/ 64 <912000000>;
++		opp-1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1008000000 {
+-			opp-hz = /bits/ 64 <1008000000>;
+-			opp-microvolt = <840000>;
++		opp-1412000000 {
++			opp-hz = /bits/ 64 <1412000000>;
++			opp-microvolt = <920000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1128000000 {
+-			opp-hz = /bits/ 64 <1128000000>;
+-			opp-microvolt = <840000>;
++		opp-1608000000 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <1000000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1200000000 {
+-			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <840000>;
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1080000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 	};
+@@ -263,45 +245,27 @@ opp-480000000 {
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-600000000 {
+-			opp-hz = /bits/ 64 <600000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-720000000 {
+-			opp-hz = /bits/ 64 <720000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-864000000 {
+-			opp-hz = /bits/ 64 <864000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-912000000 {
+-			opp-hz = /bits/ 64 <912000000>;
++		opp-1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1008000000 {
+-			opp-hz = /bits/ 64 <1008000000>;
+-			opp-microvolt = <840000>;
++		opp-1412000000 {
++			opp-hz = /bits/ 64 <1412000000>;
++			opp-microvolt = <920000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1128000000 {
+-			opp-hz = /bits/ 64 <1128000000>;
+-			opp-microvolt = <840000>;
++		opp-1608000000 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <1000000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1200000000 {
+-			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <840000>;
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1080000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
new file mode 100644
index 000000000000..46650bf79379
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
@@ -0,0 +1,59 @@
+From 4d7645d38d9d775977f3c4b08ffd77fb2c95c765 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 1 Feb 2020 23:41:47 +0100
+Subject: ARM: dts: sun8i-a83t: Set fifo-size for uarts
+
+Boot time optimization.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 045f7b4f6253..c9c190491e00 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -926,6 +926,7 @@ uart0: serial@1c28000 {
+ 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART0>;
+ 			resets = <&ccu RST_BUS_UART0>;
+ 			status = "disabled";
+@@ -937,6 +938,7 @@ uart1: serial@1c28400 {
+ 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART1>;
+ 			resets = <&ccu RST_BUS_UART1>;
+ 			status = "disabled";
+@@ -948,6 +950,7 @@ uart2: serial@1c28800 {
+ 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART2>;
+ 			resets = <&ccu RST_BUS_UART2>;
+ 			status = "disabled";
+@@ -959,6 +962,7 @@ uart3: serial@1c28c00 {
+ 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART3>;
+ 			resets = <&ccu RST_BUS_UART3>;
+ 			status = "disabled";
+@@ -970,6 +974,7 @@ uart4: serial@1c29000 {
+ 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART4>;
+ 			resets = <&ccu RST_BUS_UART4>;
+ 			status = "disabled";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
new file mode 100644
index 000000000000..228f7ce32428
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
@@ -0,0 +1,66 @@
+From 2f403f69a91591025fc43912435f980f3232fcb2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 10 Nov 2017 14:33:28 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add PN544 NFC support
+
+Regulators on the schematic are named incorrectly. Both cameras are
+is in fact connected to the dvdd-csi-f regulator and dvdd-csi-r is
+in reality used for digital pad supply for NFC chip.
+
+At the same time vcc-mipi regulator is not used for MIPI, but for NFC
+VBAT power.
+
+Interpreting schematics is an art form! :D
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index a7d4ca308990..262fb3bdfde3 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -190,6 +190,16 @@ accelerometer@18 {
+ 		interrupt-parent = <&pio>;
+ 		interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
+ 	};
++
++	/* NFC (NPC 100) */
++	npc100: nfc@28 {
++		compatible = "nxp,nxp-nci-i2c";
++		reg = <0x28>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; /* PL6 */
++		enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
++		firmware-gpios = <&pio 3 3 GPIO_ACTIVE_HIGH>; /* PD3 */
++	};
+ };
+ 
+ &mmc0 {
+@@ -368,9 +378,10 @@ &reg_dldo1 {
+ };
+ 
+ &reg_dldo2 {
+-	regulator-min-microvolt = <2800000>;
++	regulator-min-microvolt = <3300000>;
+ 	regulator-max-microvolt = <4200000>;
+-	regulator-name = "vcc-mipi";
++	regulator-name = "vbat-nfc";
++	regulator-always-on;
+ };
+ 
+ &reg_dldo3 {
+@@ -393,7 +404,8 @@ &reg_drivevbus {
+ &reg_eldo1 {
+ 	regulator-min-microvolt = <1200000>;
+ 	regulator-max-microvolt = <1800000>;
+-	regulator-name = "dvdd-csi-r";
++	regulator-name = "pvdd-nfc";
++	regulator-always-on;
+ };
+ 
+ &reg_eldo2 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
new file mode 100644
index 000000000000..ba3e84d4c72a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
@@ -0,0 +1,180 @@
+From 608cd14b4eb4dcd8f9921616f8b681f76d1c832d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:43:24 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add camera sensors (HM5065, GC2145)
+
+The tablet has two cameras, that can be switched between. Add
+support for the both of them.
+
+Sensor is connected via parallel bus to CSI and via I2C bus to
+PE14/PE15 pins. Enable CSI module and add the node for HM5065
+camera sensor.
+
+Camera sensors are connected via I2C to PE14/PE15 pins on A83T.
+Unfortunately while the A83T datasheet suggests TWI2 I2C controller
+can be configured to have SDA/SCL on these pins, this configuration
+doesn't work in reality. We need to either use CCI I2C controller
+that is part of the CSI module, or as is done in this patch, use GPIO
+based bitbanging I2C driver.
+
+Reduce camera IOVDD voltage.
+
+Force dvdd-csi-r/f regulators to 1.8V.
+
+This is required by camera sensors that are connected to them.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun8i-a83t-tbs-a711.dts     | 101 +++++++++++++++++-
+ 1 file changed, 99 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index f2212a620c81..1b597ac966c0 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -70,6 +70,16 @@ backlight: backlight {
+ 		default-brightness-level = <9>;
+ 	};
+ 
++	i2c_gpio: i2c-gpio {
++		compatible = "i2c-gpio";
++		/* PE15 = sda, PE14 = scl */
++		sda-gpios = <&pio 4 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&pio 4 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <1>; /* ~100 kHz */
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
+ 	panel {
+ 		compatible = "tbs,a711-panel", "panel-lvds";
+ 		backlight = <&backlight>;
+@@ -215,6 +225,13 @@ link2_codec: codec {
+ 	};
+ };
+ 
++&ccu {
++	/* Use a stable clock source with known fixed rate for MCLK */
++	assigned-clocks = <&ccu CLK_CSI_MCLK>;
++	assigned-clock-parents = <&osc24M>;
++	assigned-clock-rates = <24000000>;
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdc2>;
+ };
+@@ -223,6 +240,37 @@ &cpu100 {
+ 	cpu-supply = <&reg_dcdc3>;
+ };
+ 
++&csi {
++	pinctrl-names = "default";
++	pinctrl-0 = <&csi_8bit_parallel_pins>, <&csi_mclk_pin>;
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi_hm5065_ep: endpoint@0 {
++			reg = <0>;
++			remote-endpoint = <&hm5065_ep>;
++			bus-width = <8>;
++			data-active = <1>;
++			pclk-sample = <0>;
++			hsync-active = <0>;
++			vsync-active = <1>;
++		};
++
++		csi_gc2145_ep: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&gc2145_ep>;
++			bus-width = <8>;
++			hsync-active = <1>;
++			vsync-active = <1>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		};
++	};
++};
++
+ &de {
+ 	status = "okay";
+ };
+@@ -283,6 +331,55 @@ npc100: nfc@28 {
+ 	};
+ };
+ 
++&i2c_gpio {
++	hm5065: rear-camera@1f {
++		compatible = "himax,hm5065";
++		reg = <0x1f>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		AFVDD-supply = <&reg_dldo3>;
++		reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
++		enable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
++
++		port {
++			hm5065_ep: endpoint {
++				remote-endpoint = <&csi_hm5065_ep>;
++				bus-width = <8>;
++				data-active = <1>;
++				pclk-sample = <0>;
++				hsync-active = <0>;
++				vsync-active = <1>;
++			};
++		};
++	};
++
++	gc2145: front-camera@3c {
++		compatible = "galaxycore,gc2145";
++		reg = <0x3c>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
++		enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
++
++		port {
++			gc2145_ep: endpoint {
++				remote-endpoint = <&csi_gc2145_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++};
++
+ &i2s0 {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+@@ -500,7 +597,7 @@ &reg_drivevbus {
+ };
+ 
+ &reg_eldo1 {
+-	regulator-min-microvolt = <1200000>;
++	regulator-min-microvolt = <1800000>;
+ 	regulator-max-microvolt = <1800000>;
+ 	regulator-name = "pvdd-nfc";
+ 	regulator-always-on;
+@@ -513,7 +610,7 @@ &reg_eldo2 {
+ };
+ 
+ &reg_eldo3 {
+-	regulator-min-microvolt = <1200000>;
++	regulator-min-microvolt = <1800000>;
+ 	regulator-max-microvolt = <1800000>;
+ 	regulator-name = "dvdd-csi-f";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
new file mode 100644
index 000000000000..003449bae559
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
@@ -0,0 +1,32 @@
+From 6a90d5ef9a83e9b99d1ef17b4d47e12f9a0ce52c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Nov 2017 21:57:45 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add flash led support
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 1b597ac966c0..4f10efb00dde 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -61,6 +61,15 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	leds {
++		compatible = "gpio-leds";
++
++		flash_led {
++			label = "flash";
++			gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
+ 	backlight: backlight {
+ 		compatible = "pwm-backlight";
+ 		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
new file mode 100644
index 000000000000..760cd0eb716b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
@@ -0,0 +1,61 @@
+From 16ce87f7c325002ae666436fb4976a82a1e92414 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?=
+ <mylene.josserand@free-electrons.com>
+Date: Thu, 6 Jul 2017 10:57:55 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add powerup/down support for the 3G
+ modem
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The modem needs tree gpios to be powered-up:
+	- PL10 = reset
+	- PL8 = On/Off
+	- PL9 = vbat
+Because of that, the PL9 corresponds to the regulator's gpio whereas
+the PL8 (on/off) will be a power-gpio of the power sequence.
+
+Thanks to that, the modem is powered up:
+       # lsusb
+	Bus 001 Device 004: ID 19d2:ffeb
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 262fb3bdfde3..ee2c895174a5 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -118,7 +118,7 @@ reg_vmain: reg-vmain {
+ 		regulator-name = "vmain";
+ 		regulator-min-microvolt = <5000000>;
+ 		regulator-max-microvolt = <5000000>;
+-		gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;
++		gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ 		enable-active-high;
+ 		vin-supply = <&reg_vbat>;
+ 	};
+@@ -134,6 +134,17 @@ wifi_pwrseq: wifi_pwrseq {
+ 		clocks = <&ac100_rtc 1>;
+ 		clock-names = "ext_clock";
+ 	};
++
++	modem {
++		compatible = "zte,mg3732";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vmain>;
++
++		enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++		reset-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
++		wakeup-gpios = <&r_pio 0 11 GPIO_ACTIVE_HIGH>; /* PL11 */
++	};
+ };
+ 
+ &cpu0 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
new file mode 100644
index 000000000000..4b09b27b0518
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
@@ -0,0 +1,30 @@
+From 73c01b1ca6aac449b3f79d64f9d5171512a8c72b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:15:37 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add regulators to the accelerometer
+
+The bosch,bma250 driver will fail to probe if the regulators are
+not specified in DT, because it tries to set voltage on dummy
+regulators, which fails with EINVAL.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index b6378501dc20..f2212a620c81 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -268,6 +268,8 @@ accelerometer@18 {
+ 		reg = <0x18>;
+ 		interrupt-parent = <&pio>;
+ 		interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
++		vdd-supply = <&reg_dcdc1>;
++		vddio-supply = <&reg_dcdc1>;
+ 	};
+ 
+ 	/* NFC (NPC 100) */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
new file mode 100644
index 000000000000..f5fb2ac91083
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
@@ -0,0 +1,131 @@
+From 929191b65f38c80553fb4dba9042c369c30f4d64 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 22 Feb 2020 23:40:29 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add sound support via AC100 codec
+
+...
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun8i-a83t-tbs-a711.dts     | 85 +++++++++++++++++++
+ 1 file changed, 85 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index ee2c895174a5..b6378501dc20 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -145,6 +145,74 @@ modem {
+ 		reset-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ 		wakeup-gpios = <&r_pio 0 11 GPIO_ACTIVE_HIGH>; /* PL11 */
+ 	};
++
++	bt_sco_codec: bt-sco-codec {
++		#sound-dai-cells = <1>;
++		compatible = "linux,bt-sco";
++		sound-name-prefix = "Bluetooth";
++	};
++
++	speaker_amp: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++		sound-name-prefix = "Speaker Amp";
++	};
++
++	sound: sound {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "ac100-audio";
++		simple-audio-card,aux-devs = <&ac100_codec_analog>, <&speaker_amp>;
++		simple-audio-card,widgets = "Microphone", "Headset Microphone",
++					    "Microphone", "Internal Microphone",
++					    "Headphone", "Headphone Jack",
++					    "Speaker", "Internal Speaker";
++		simple-audio-card,routing =
++				"Headphone Jack", "HP",
++				"Internal Speaker", "Speaker Amp OUTL",
++				"Speaker Amp INL", "SPKOUTL",
++				"Left DAC", "DACL",
++				"Right DAC", "DACR",
++				"ADCL", "Left ADC",
++				"ADCR", "Right ADC",
++				"Internal Microphone", "MBIAS",
++				"MIC1", "Internal Microphone",
++				"Headset Microphone", "HBIAS",
++				"MIC2", "Headset Microphone";
++
++		simple-audio-card,dai-link@0 {
++			format = "i2s";
++			frame-master = <&link0_cpu>;
++			bitclock-master = <&link0_cpu>;
++			mclk-fs = <512>;
++
++			link0_cpu: cpu {
++				sound-dai = <&i2s0>;
++			};
++
++			link0_codec: codec {
++				sound-dai = <&ac100_codec 0>;
++			};
++		};
++
++		simple-audio-card,dai-link@2 {
++			format = "dsp_a";
++			frame-master = <&link2_codec>;
++			bitclock-master = <&link2_codec>;
++			bitclock-inversion;
++
++			link2_cpu: cpu {
++				sound-dai = <&bt_sco_codec 0>;
++			};
++
++			link2_codec: codec {
++				sound-dai = <&ac100_codec 2>;
++				dai-tdm-slot-num = <2>;
++				dai-tdm-slot-width = <16>;
++			};
++		};
++	};
+ };
+ 
+ &cpu0 {
+@@ -213,6 +281,12 @@ npc100: nfc@28 {
+ 	};
+ };
+ 
++&i2s0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2s0_pins>;
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdc1>;
+ 	pinctrl-names = "default";
+@@ -293,12 +367,23 @@ ac100: codec@e89 {
+ 		compatible = "x-powers,ac100";
+ 		reg = <0xe89>;
+ 
++		ac100_codec_analog: codec-analog {
++			compatible = "x-powers,ac100-codec-analog";
++			cpvdd-supply = <&reg_aldo2>;
++		};
++
+ 		ac100_codec: codec {
++			#sound-dai-cells = <1>;
+ 			compatible = "x-powers,ac100-codec";
+ 			interrupt-parent = <&r_pio>;
+ 			interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */
+ 			#clock-cells = <0>;
+ 			clock-output-names = "4M_adda";
++
++			LDOIN-supply = <&reg_aldo2>;
++			AVCC-supply = <&reg_aldo3>;
++			VDDIO1-supply = <&reg_dcdc1>;
++			VDDIO2-supply = <&reg_dldo1>;
+ 		};
+ 
+ 		ac100_rtc: rtc {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
new file mode 100644
index 000000000000..3f33f9ce10da
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
@@ -0,0 +1,39 @@
+From dec2d739e21a0b88d9c6017562aeffd2fcce1f4c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 9 Nov 2019 23:55:48 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add support for the vibrator motor
+
+The board has a vibrator mottor. Hook it to the input subsystem.
+
+According to the PMIC specification, LDO needs to be enabled (value 0b11)
+to achieve the specified max driving current of 150mA. We can't drive
+the motor with just GPIO mode.
+
+In GPIO mode the chip is probably just using the regular CMOS logic
+output circuitry (typically limited to around 20-35mA, but not specified
+in this datasheet).
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 4f10efb00dde..a8c2b1dccca4 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -118,6 +118,11 @@ panel_input: endpoint {
+ 		};
+ 	};
+ 
++	vibrator {
++		compatible = "gpio-vibrator";
++		vcc-supply = <&reg_ldo_io1>;
++	};
++
+ 	reg_gps: reg-gps {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "gps";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
new file mode 100644
index 000000000000..c81edb694963
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
@@ -0,0 +1,31 @@
+From 63d4551e65ae08a2d62299bbabfc7954adec1467 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 13:21:58 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Enable charging LED
+
+The tablet has a LED connected to the PMIC. The LED is visible in the
+top right corner of the tablet. Enable it.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 9c579e29e7ce..b6b46e57d0ed 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -519,6 +519,10 @@ &battery_power_supply {
+ 	status = "okay";
+ };
+ 
++&charger_led {
++	status = "okay";
++};
++
+ &reg_aldo1 {
+ 	regulator-min-microvolt = <1800000>;
+ 	regulator-max-microvolt = <1800000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
new file mode 100644
index 000000000000..5aec34d1a777
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
@@ -0,0 +1,47 @@
+From a12f8e383cb2f12e39ec92940ca490df0c7e5af9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:19:46 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Give Linux more privileges over SCPI
+
+This is needed since on A83T there's no PSCI/ATF implementation.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index c34dacef14ea..0ea31e3e41af 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -286,7 +286,7 @@ opp-1800000000 {
+ 
+ 	scpi_protocol: scpi {
+ 		compatible = "arm,scpi";
+-		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mboxes = <&msgbox 0>, <&msgbox 1>;
+ 		mbox-names = "tx", "rx";
+ 		shmem = <&scpi_sram>;
+ 	};
+@@ -424,6 +424,9 @@ syscon: syscon@1c00000 {
+ 			compatible = "allwinner,sun8i-a83t-system-controller",
+ 				"syscon";
+ 			reg = <0x01c00000 0x1000>;
++                        #address-cells = <1>;
++                        #size-cells = <1>;
++                        ranges;
+ 
+ 			sram_a2: sram@40000 {
+ 				compatible = "mmio-sram";
+@@ -434,7 +437,7 @@ sram_a2: sram@40000 {
+ 
+ 				scpi_sram: scp-shmem@13c00 {
+ 					compatible = "arm,scp-shmem";
+-					reg = <0x13c00 0x200>;
++					reg = <0x13e00 0x200>;
+ 				};
+ 			};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
new file mode 100644
index 000000000000..d57f99c1fcb6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
@@ -0,0 +1,30 @@
+From cd1a1502072948cc1ad719669cde1d8f655603d1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 8 Dec 2017 12:44:22 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Increase voltage on the vibrator
+
+Vibrator motor is weak at the current voltage. Increase the voltage.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index a8c2b1dccca4..9c579e29e7ce 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -650,8 +650,8 @@ &reg_ldo_io0 {
+ };
+ 
+ &reg_ldo_io1 {
+-	regulator-min-microvolt = <3100000>;
+-	regulator-max-microvolt = <3100000>;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
+ 	regulator-name = "vcc-vb";
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
new file mode 100644
index 000000000000..c60f4773ea4b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
@@ -0,0 +1,42 @@
+From 1d4f2378dd27c2abb0048d6be94de7b5e73cbb9e Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:14:51 +0200
+Subject: ARM: dts: sun8i: h2-plus: bananapi-m2-zero: Enable HDMI audio
+
+BananaPi M2 Zero has HDMI output and thus supports HDMI audio. Enable
+it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts
+index d729b7c705db..ed5737284c09 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts
+@@ -133,6 +133,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -256,6 +260,10 @@ &r_pio {
+ 		"", "", "", "", "", "", "", "";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &usb_otg {
+ 	dr_mode = "otg";
+ 	status = "okay";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
new file mode 100644
index 000000000000..ff2cb694af93
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
@@ -0,0 +1,272 @@
+From 2d576057638f3d0afd8d95d8929874628cab4f28 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:06:37 +0200
+Subject: ARM: dts: sun8i: h3: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all H3 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts       | 8 ++++++++
+ .../dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts   | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts        | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts       | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts    | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts     | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts      | 8 ++++++++
+ .../boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts   | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts    | 8 ++++++++
+ 10 files changed, 80 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts
+index a6d38ecee141..5d2a0c0b8c7c 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts
+@@ -159,6 +159,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	linux,rc-map-name = "rc-tanix-tx3mini";
+ 	pinctrl-names = "default";
+@@ -213,6 +217,10 @@ &reg_usb0_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spdif {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spdif_tx_pin>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts
+index 02fbe00cde97..61d6529dcc70 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts
+@@ -70,3 +70,11 @@ hdmi_out_con: endpoint {
+ &i2c1 {
+ 	status = "okay";
+ };
++
++&i2s2 {
++	status = "okay";
++};
++
++&sound_hdmi {
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts
+index 4ba533b0340f..e94ffe3c1c69 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts
+@@ -118,6 +118,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -159,6 +163,10 @@ &ohci2 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart3 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts
+index 69243dcb30a6..9393779f33b6 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts
+@@ -91,6 +91,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -104,3 +108,7 @@ &ohci1 {
+ &ohci2 {
+ 	status = "okay";
+ };
++
++&sound_hdmi {
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
+index f1f9dbead32a..2b5890327a47 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
+@@ -145,6 +145,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -179,6 +183,10 @@ &reg_usb1_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts
+index 305b34a321f5..9037bc673800 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts
+@@ -120,6 +120,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -156,6 +160,10 @@ &ohci2 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index 59f6f6d5e7ca..927fd1bab07d 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -146,6 +146,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -166,6 +170,10 @@ &reg_usb0_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+index 92a58e362004..624e248e3ffc 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+@@ -147,6 +147,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -206,6 +210,10 @@ &reg_usb0_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts
+index 561ea1d2f861..70202baa54b9 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts
+@@ -117,6 +117,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -155,6 +159,10 @@ &ohci0 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts
+index 4738f3a9efe4..ee645912ee39 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts
+@@ -69,6 +69,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	bus-width = <4>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+@@ -98,6 +102,10 @@ &ohci3 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
new file mode 100644
index 000000000000..be97398552dd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
@@ -0,0 +1,72 @@
+From 8287f76b01b293aebb294aba2c0e72f03163f1b8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 17 Aug 2020 23:43:53 +0200
+Subject: ARM: dts: sun8i-h3: Use my own more aggressive OPPs on H3
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 36 +++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index eac2349a2380..da1991c991cb 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -48,6 +48,12 @@ cpu0_opp_table: opp-table-cpu {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
++		opp-480000000 {
++			opp-hz = /bits/ 64 <480000000>;
++			opp-microvolt = <1040000 1040000 1300000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
+ 		opp-648000000 {
+ 			opp-hz = /bits/ 64 <648000000>;
+ 			opp-microvolt = <1040000 1040000 1300000>;
+@@ -60,11 +66,41 @@ opp-816000000 {
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
++		opp-960000000 {
++			opp-hz = /bits/ 64 <960000000>;
++			opp-microvolt = <1200000 1200000 1300000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
+ 		opp-1008000000 {
+ 			opp-hz = /bits/ 64 <1008000000>;
+ 			opp-microvolt = <1200000 1200000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
++
++		opp-1104000000 {
++			opp-hz = /bits/ 64 <1104000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1296000000 {
++			opp-hz = /bits/ 64 <1296000000>;
++			opp-microvolt = <1340000 1340000 1340000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1368000000 {
++			opp-hz = /bits/ 64 <1368000000>;
++			opp-microvolt = <1400000 1400000 1400000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
+ 	};
+ 
+ 	cpus {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
new file mode 100644
index 000000000000..21d43e41d9b9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
@@ -0,0 +1,49 @@
+From a320e89c50343f0a205b39d2ea1f9db0d7e4bf65 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Apr 2022 02:24:26 +0200
+Subject: ARM: dts: sun8i-h3-orange-pi-one: Enable all gpio header UARTs
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index f5476cdab8a4..64c489e356ce 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -54,6 +54,9 @@ / {
+ 	aliases {
+ 		ethernet0 = &emac;
+ 		serial0 = &uart0;
++		serial1 = &uart1;
++		serial2 = &uart2;
++		serial3 = &uart3;
+ 	};
+ 
+ 	chosen {
+@@ -183,19 +186,19 @@ &uart0 {
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart1_pins>;
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &uart2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart2_pins>;
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &uart3 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart3_pins>;
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &usb_otg {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
new file mode 100644
index 000000000000..7b15f56ab4bb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
@@ -0,0 +1,31 @@
+From 919234c96391c73bd3e6b761e2924690848d565f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 13 May 2018 21:00:43 +0200
+Subject: ARM: dts: sun8i-h3-orange-pi-pc: Increase max CPUX voltage to 1.4V
+
+When using thermal regulation we can afford to go higher. Also add
+regulator-ramp-delay, because regulator takes some time to change
+voltage.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+index b96e015f54ee..92a58e362004 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+@@ -194,7 +194,8 @@ reg_vdd_cpux: regulator@65 {
+ 		 * Use 1.0V as the minimum voltage instead.
+ 		 */
+ 		regulator-min-microvolt = <1000000>;
+-		regulator-max-microvolt = <1300000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
+ 		regulator-boot-on;
+ 		regulator-always-on;
+ 	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..60ba024dac29
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From cb1a71e2a2488de7d42243e40861bff0fad6e428 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:50:56 +0200
+Subject: ARM: dts: sun8i: r40: Add hdmi sound card
+
+R40 support HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-r40.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+index a5b1f1e3900d..d73828d6b3c0 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+@@ -124,6 +124,20 @@ de: display-engine {
+ 		status = "disabled";
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun8i-r40-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	thermal-zones {
+ 		cpu_thermal: cpu0-thermal {
+ 			/* milliseconds */
+@@ -1265,6 +1279,7 @@ gic: interrupt-controller@1c81000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun8i-r40-dw-hdmi",
+ 				     "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
new file mode 100644
index 000000000000..81701d913f46
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
@@ -0,0 +1,42 @@
+From 8ebc93a114a49eca3274d7f6861f6310e0b1cfda Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:52:43 +0200
+Subject: ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable HDMI audio
+
+BananaPi M2 Ultra has HDMI output and thus supports HDMI audio. Enable
+it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts    | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
+index 28197bbcb1d5..3508633a8e55 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
+@@ -169,6 +169,10 @@ axp22x: pmic@34 {
+ 
+ #include "axp22x.dtsi"
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir0 {
+ 	status = "okay";
+ };
+@@ -304,6 +308,10 @@ &reg_eldo3 {
+ 	regulator-name = "vdd1v2-sata";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &tcon_tv0 {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
new file mode 100644
index 000000000000..10e96cd2c801
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
@@ -0,0 +1,42 @@
+From eb1f050547e65956edf6365edf515945efecec85 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 12:00:46 +0200
+Subject: ARM: dts: sun8i: v40: bananapi-m2-berry: Enable HDMI audio
+
+BananaPi M2 Berry has HDMI output and thus supports HDMI audio. Enable
+it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts    | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts
+index 434871040aca..a661b1a60146 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts
+@@ -160,6 +160,10 @@ axp22x: pmic@34 {
+ 
+ #include "axp22x.dtsi"
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdc1>;
+ 	bus-width = <4>;
+@@ -275,6 +279,10 @@ &reg_eldo3 {
+ 	regulator-name = "vdd1v2-sata";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &tcon_tv0 {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
new file mode 100644
index 000000000000..29644c1ba17c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
@@ -0,0 +1,29 @@
+From 8aac7b42eb76a49b8d271bb166b151d7e9080db4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 12 Nov 2017 19:03:39 +0100
+Subject: ARM: dts: suni-a83t: Add i2s0 pins
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index abf926163cc9..8ef86b688b87 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -829,6 +829,11 @@ spdif_tx_pin: spdif-tx-pin {
+ 				function = "spdif";
+ 			};
+ 
++			i2s0_pins: i2s0-pins {
++				pins = "PB4", "PB5", "PB6", "PB7", "PB8";
++				function = "i2s0";
++			};
++
+ 			uart0_pb_pins: uart0-pb-pins {
+ 				pins = "PB9", "PB10";
+ 				function = "uart0";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
new file mode 100644
index 000000000000..286fb330e7b2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
@@ -0,0 +1,66 @@
+From 60bc0b89bb6ffe3fdec4a76a0c5c801f6f39056c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 25 Jan 2021 01:15:58 +0100
+Subject: ARM: dts: sunxi: Add aliases for MMC
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun5i.dtsi      | 6 ++++++
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 6 ++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi   | 6 ++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i.dtsi b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+index d7c7b454a11a..cdd23ff16159 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+@@ -51,6 +51,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 89d56fd297fd..8caeaeb6a29f 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -57,6 +57,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index eac2349a2380..5b89d444f86e 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -44,6 +44,12 @@
+ #include <dt-bindings/thermal/thermal.h>
+ 
+ / {
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpu0_opp_table: opp-table-cpu {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..837c4da24ad4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
@@ -0,0 +1,52 @@
+From c598df99fac9a1e73b05495ff37950877d78177c Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:14:29 -0600
+Subject: ARM: dts: sunxi: a83t: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 07a849919e6a..c08b3a7c2524 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -284,6 +284,13 @@ opp-1800000000 {
+ 		};
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -417,6 +424,20 @@ syscon: syscon@1c00000 {
+ 			compatible = "allwinner,sun8i-a83t-system-controller",
+ 				"syscon";
+ 			reg = <0x01c00000 0x1000>;
++
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0x14000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0x14000>;
++
++				scpi_sram: scp-shmem@13c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x13c00 0x200>;
++				};
++			};
++
+ 		};
+ 
+ 		video-codec@01c0e000 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch
new file mode 100644
index 000000000000..0b2035c86ec0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch
@@ -0,0 +1,33 @@
+From 5dff8ca1acae733c8cd3d56eb785e9635eacd507 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:03:34 -0600
+Subject: ARM: dts: sunxi: a83t: Protect SCP clocks
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index c9c190491e00..219c50e61c14 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -690,6 +690,7 @@ ccu: clock@1c20000 {
+ 			reg = <0x01c20000 0x400>;
+ 			clocks = <&osc24M>, <&osc16Md512>;
+ 			clock-names = "hosc", "losc";
++			protected-clocks = <CLK_BUS_MSGBOX>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+@@ -1137,6 +1138,7 @@ r_ccu: clock@1f01400 {
+ 			clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
+ 				 <&ccu CLK_PLL_PERIPH>;
+ 			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			protected-clocks = <CLK_APB0_TWD>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..140ae09201d6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
@@ -0,0 +1,81 @@
+From 4d734e9a8c40ed1e9d4d6075cbc172ea09ee8b78 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:12:36 -0600
+Subject: ARM: dts: sunxi: h3/h5: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi    | 13 +++++++++++++
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi |  7 +++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 13 +++++++++++++
+ 3 files changed, 33 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index da1991c991cb..e601317d5de2 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -206,6 +206,19 @@ syscon: system-control@1c00000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0xc000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0xc000>;
++
++				scpi_sram: scp-shmem@bc00 {
++					compatible = "arm,scp-shmem";
++					reg = <0xbc00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@1d00000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x01d00000 0x80000>;
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index cbe8e77bbdc7..935a4303cf01 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -120,6 +120,13 @@ de: display-engine {
+ 		status = "disabled";
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index d3caf27b6a55..e02a3848003e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -86,6 +86,19 @@ syscon: system-control@1c00000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0x14000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0x14000>;
++
++				scpi_sram: scp-shmem@13c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x13c00 0x200>;
++				};
++			};
++
+ 			sram_c1: sram@18000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00018000 0x1c000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..5d6113d86a2b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From 242a0c55fdbd5cc08f8d51490509540e3bd1ddc2 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:04:58 +0200
+Subject: ARM: dts: sunxi: h3/h5: Add hdmi sound card
+
+H3 and H5 support HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index ade1cd50e445..3c0da94661c9 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -106,6 +106,20 @@ de: display-engine {
+ 		status = "disabled";
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun8i-h3-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -818,6 +832,7 @@ csi: camera@1cb0000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun8i-h3-dw-hdmi",
+ 				     "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch
new file mode 100644
index 000000000000..42dcf3198323
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch
@@ -0,0 +1,33 @@
+From de005a441ecc4abdf3bca6d08bba86ddbec8d3b6 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:03:46 -0600
+Subject: ARM: dts: sunxi: h3/h5: Protect SCP clocks
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 699ab2f7a1ac..cbe8e77bbdc7 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -407,6 +407,7 @@ ccu: clock@1c20000 {
+ 			reg = <0x01c20000 0x400>;
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
+ 			clock-names = "hosc", "losc";
++			protected-clocks = <CLK_BUS_MSGBOX>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+@@ -902,6 +903,7 @@ r_ccu: clock@1f01400 {
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
+ 				 <&ccu CLK_PLL_PERIPH0>;
+ 			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			protected-clocks = <CLK_APB0_TWD>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
new file mode 100644
index 000000000000..6c943c547424
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
@@ -0,0 +1,88 @@
+From 9e159be40c94c436771beff9fc9bac787ea1cde8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Oct 2019 05:06:29 +0200
+Subject: ARM: sunxi: Add experimental suspend to memory implementation for
+ A83T
+
+This just ends with WFI, but all secondary CPUs will be shut down.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/mach-sunxi/sunxi.c | 46 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
+index e1b7945aac99..2d6b7b4528e9 100644
+--- a/arch/arm/mach-sunxi/sunxi.c
++++ b/arch/arm/mach-sunxi/sunxi.c
+@@ -12,10 +12,13 @@
+ #include <linux/init.h>
+ #include <linux/of_clk.h>
+ #include <linux/platform_device.h>
++#include <linux/of_platform.h>
+ #include <linux/reset/sunxi.h>
++#include <linux/suspend.h>
+ 
+ #include <asm/mach/arch.h>
+ #include <asm/secure_cntvoff.h>
++#include <asm/suspend.h>
+ 
+ static const char * const sunxi_board_dt_compat[] = {
+ 	"allwinner,sun4i-a10",
+@@ -86,10 +89,53 @@ static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
+ 	NULL,
+ };
+ 
++#ifdef CONFIG_PM_SLEEP
++static int sun8i_a83t_pm_valid(suspend_state_t state)
++{
++	return state == PM_SUSPEND_MEM;
++}
++
++static int sun8i_a83t_suspend_finish(unsigned long val)
++{
++	// don't do much
++	cpu_do_idle();
++	return 0;
++}
++
++static int sun8i_a83t_pm_enter(suspend_state_t state)
++{
++	switch (state) {
++	case PM_SUSPEND_MEM:
++		cpu_suspend(0, sun8i_a83t_suspend_finish);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const struct platform_suspend_ops sun8i_a83t_pm_ops = {
++	.enter = sun8i_a83t_pm_enter,
++	.valid = sun8i_a83t_pm_valid,
++};
++#define SUN8I_A83T_PM_OPS &sun8i_a83t_pm_ops
++#else
++#define SUN8I_A83T_PM_OPS NULL
++#endif
++
++static void __init sun8i_a83t_init_machine(void)
++{
++	suspend_set_ops(SUN8I_A83T_PM_OPS);
++
++	of_platform_default_populate(NULL, NULL, NULL);
++}
++
+ DT_MACHINE_START(SUN8I_A83T_CNTVOFF_DT, "Allwinner A83t board")
+ 	.init_early	= sun8i_a83t_cntvoff_init,
+ 	.init_time	= sun6i_timer_init,
+ 	.dt_compat	= sun8i_a83t_cntvoff_board_dt_compat,
++	.init_machine	= sun8i_a83t_init_machine,
+ MACHINE_END
+ 
+ static const char * const sun9i_board_dt_compat[] = {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
new file mode 100644
index 000000000000..3b32e1cccf36
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
@@ -0,0 +1,54 @@
+From 9809ff4891da9c4df9321aaaaeb95061dd7d4926 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 2 Nov 2019 15:21:04 +0100
+Subject: ARM: sunxi: Use SCPI to send suspend message to SCP on A83T
+
+We use undefined value of 3, to mean SUSPEND_SYSTEM. SCP should:
+
+- kill CPU0
+- kill cluster 0
+- shutdown power to both clusters (Linux MCPM doesn't do that)
+...
+- reverse all of the above on interrupt
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/mach-sunxi/sunxi.c | 15 +++++++++++++--
+ 1 file changed, 13 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
+index 2d6b7b4528e9..d4c25c33455d 100644
+--- a/arch/arm/mach-sunxi/sunxi.c
++++ b/arch/arm/mach-sunxi/sunxi.c
+@@ -14,6 +14,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/of_platform.h>
+ #include <linux/reset/sunxi.h>
++#include <linux/scpi_protocol.h>
+ #include <linux/suspend.h>
+ 
+ #include <asm/mach/arch.h>
+@@ -97,8 +98,18 @@ static int sun8i_a83t_pm_valid(suspend_state_t state)
+ 
+ static int sun8i_a83t_suspend_finish(unsigned long val)
+ {
+-	// don't do much
+-	cpu_do_idle();
++	struct scpi_ops *scpi;
++
++	scpi = get_scpi_ops();
++	if (scpi && scpi->sys_set_power_state) {
++		//HACK: use invalid state to mean: suspend last CPU and the system
++		scpi->sys_set_power_state(3);
++		cpu_do_idle();
++	} else {
++		// don't do much if scpi is not available
++		cpu_do_idle();
++	}
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
new file mode 100644
index 000000000000..3263dae7f772
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
@@ -0,0 +1,27 @@
+From b7675990ec9b9fd5bbd909d69203e80c8d6789ea Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Oct 2019 05:08:04 +0200
+Subject: ARM: sunxi: sunxi_cpu0_hotplug_support_set is not supported on A83T
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/mach-sunxi/mc_smp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
+index 277f6aa8e6c2..ca237d50db4b 100644
+--- a/arch/arm/mach-sunxi/mc_smp.c
++++ b/arch/arm/mach-sunxi/mc_smp.c
+@@ -146,6 +146,9 @@ static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
+ 
+ static void sunxi_cpu0_hotplug_support_set(bool enable)
+ {
++	if (is_a83t)
++		return;
++
+ 	if (enable) {
+ 		writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base);
+ 		writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
new file mode 100644
index 000000000000..7e8713dc72db
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
@@ -0,0 +1,235 @@
+From 0c64362068d5c8de642fd5e0e7372c828a3feec0 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Tue, 10 Nov 2020 20:42:44 +0100
+Subject: ASOC: sun9i-hdmi-audio: Initial implementation
+
+This implements HDMI audio sound card which is used to enable HDMI audio
+on all Allwinner SoCs with DW-HDMI core. First such SoC is A80, but it's
+been used on plenty of others, like A64, A83t, H2+, H3, H5, H6, R40 and
+V40.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ sound/soc/sunxi/Kconfig            |   8 ++
+ sound/soc/sunxi/Makefile           |   1 +
+ sound/soc/sunxi/sun9i-hdmi-audio.c | 180 +++++++++++++++++++++++++++++
+ 3 files changed, 189 insertions(+)
+ create mode 100644 sound/soc/sunxi/sun9i-hdmi-audio.c
+
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index f87b061f59b2..753c38c5d554 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -76,6 +76,14 @@ config SND_SUN50I_DMIC
+ 	  Say Y or M to add support for the DMIC audio block in the Allwinner
+ 	  H6 and affiliated SoCs.
+ 
++config SND_SUN9I_HDMI_AUDIO
++	tristate "Allwinner sun9i HDMI Audio Sound Card"
++	depends on OF
++	depends on SND_SUN4I_I2S
++	help
++	  Say Y or M to add support for the HDMI Audio sound card for Allwinner
++	  SoCs with DW-HDMI core.
++
+ config SND_SUN8I_ADDA_PR_REGMAP
+ 	tristate
+ 	select REGMAP
+diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
+index 6131aea97efa..19800277105c 100644
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -8,3 +8,4 @@ obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
+ obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+ obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
+ obj-$(CONFIG_SND_SUN50I_DMIC) += sun50i-dmic.o
++obj-$(CONFIG_SND_SUN9I_HDMI_AUDIO) += sun9i-hdmi-audio.o
+diff --git a/sound/soc/sunxi/sun9i-hdmi-audio.c b/sound/soc/sunxi/sun9i-hdmi-audio.c
+new file mode 100644
+index 000000000000..4320c7fa23d4
+--- /dev/null
++++ b/sound/soc/sunxi/sun9i-hdmi-audio.c
+@@ -0,0 +1,180 @@
++// SPDX-License-Identifier: GPL-2.0
++//
++// sun9i hdmi audio sound card
++//
++// Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@gmail.com>
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++
++static int sun9i_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
++				      struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++	unsigned int mclk;
++
++	mclk = params_rate(params) * 128;
++
++	return snd_soc_dai_set_sysclk(snd_soc_rtd_to_cpu(rtd, 0), 0, mclk,
++				      SND_SOC_CLOCK_OUT);
++}
++
++static const struct snd_soc_ops sun9i_hdmi_audio_ops = {
++	.hw_params = sun9i_hdmi_audio_hw_params,
++};
++
++static int sun9i_hdmi_audio_dai_init(struct snd_soc_pcm_runtime *rtd)
++{
++	int ret;
++
++	/* TODO: switch to custom api once it's implemented in sun4i-i2s */
++	ret = snd_soc_dai_set_tdm_slot(snd_soc_rtd_to_cpu(rtd, 0), 0, 0, 2, 32);
++	if (ret) {
++		dev_err(snd_soc_rtd_to_cpu(rtd, 0)->dev,
++			"setting tdm link slots failed\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int sun9i_hdmi_audio_parse_dai(struct device_node *node,
++				      struct snd_soc_dai_link_component *dlc)
++{
++	struct of_phandle_args args;
++	int ret;
++
++	if (!node)
++		return 0;
++
++	ret = of_parse_phandle_with_args(node, "sound-dai",
++					 "#sound-dai-cells", 0, &args);
++	if (ret)
++		return ret;
++
++	ret = snd_soc_get_dai_name(&args, &dlc->dai_name);
++	if (ret < 0) {
++		of_node_put(args.np);
++
++		return ret;
++	}
++
++	dlc->of_node = args.np;
++
++	return 0;
++}
++
++static int sun9i_hdmi_audio_probe(struct platform_device *pdev)
++{
++	struct snd_soc_dai_link_component *dlc;
++	struct device *dev = &pdev->dev;
++	struct snd_soc_dai_link *link;
++	struct snd_soc_card *card;
++	struct device_node *child;
++	int ret;
++
++	card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
++	if (!card)
++		return -ENOMEM;
++
++	link = devm_kzalloc(dev, sizeof(*link), GFP_KERNEL);
++	if (!link)
++		return -ENOMEM;
++
++	dlc = devm_kzalloc(dev, sizeof(*dlc) * 3, GFP_KERNEL);
++	if (!dlc)
++		return -ENOMEM;
++
++	child = of_get_child_by_name(dev->of_node, "codec");
++	if (!child)
++		return -ENODEV;
++
++	ret = sun9i_hdmi_audio_parse_dai(child, &dlc[1]);
++	of_node_put(child);
++	if (ret)
++		return ret;
++
++	child = of_get_child_by_name(dev->of_node, "cpu");
++	if (!child) {
++		ret = -ENODEV;
++		goto out_err;
++	}
++
++	ret = sun9i_hdmi_audio_parse_dai(child, &dlc[0]);
++	of_node_put(child);
++	if (ret)
++		goto out_err;
++
++	dlc[2].of_node = dlc[0].of_node;
++
++	platform_set_drvdata(pdev, card);
++
++	link->cpus = &dlc[0];
++	link->codecs = &dlc[1];
++	link->platforms = &dlc[2];
++
++	link->num_cpus = 1;
++	link->num_codecs = 1;
++	link->num_platforms = 1;
++
++	link->playback_only = 1;
++
++	link->name = "SUN9I-HDMI";
++	link->stream_name = "SUN9I-HDMI PCM";
++
++	link->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_CBS_CFS;
++
++	link->ops = &sun9i_hdmi_audio_ops;
++	link->init = sun9i_hdmi_audio_dai_init;
++
++	card->dai_link = link;
++	card->num_links = 1;
++	card->owner = THIS_MODULE;
++	card->dev = dev;
++	card->name = "sun9i-hdmi";
++
++	ret = devm_snd_soc_register_card(dev, card);
++	if (ret)
++		goto out_err;
++
++	return 0;
++
++out_err:
++	of_node_put(dlc[0].of_node);
++	of_node_put(dlc[1].of_node);
++
++	return ret;
++}
++
++static int sun9i_hdmi_audio_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++	of_node_put(card->dai_link->cpus->of_node);
++	of_node_put(card->dai_link->codecs->of_node);
++
++	return 0;
++}
++
++static const struct of_device_id sun9i_hdmi_audio_match[] = {
++	{ .compatible = "allwinner,sun9i-a80-hdmi-audio" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, sun9i_hdmi_audio_match);
++
++static struct platform_driver sun9i_hdmi_audio_driver = {
++	.probe = sun9i_hdmi_audio_probe,
++	.remove = sun9i_hdmi_audio_remove,
++	.driver = {
++		.name = "sun9i-hdmi-audio",
++		.of_match_table = sun9i_hdmi_audio_match,
++	},
++};
++module_platform_driver(sun9i_hdmi_audio_driver);
++
++MODULE_DESCRIPTION("sun9i HDMI Audio Sound Card");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@gmail.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch
new file mode 100644
index 000000000000..1f1b6226f3b7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch
@@ -0,0 +1,29 @@
+From d9ab66ba8d1d7b9c168bfdccb7b4424b52329615 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 29 Jul 2022 01:08:29 +0200
+Subject: ASoC: codec: es8316: "DAC Soft Ramp Rate" is just a 2 bit control
+
+Max value should be 3, otherwise "DAC Soft Ramp Switch" will be
+overwritten by this control.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/codecs/es8316.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c
+index e53b2856d625..2a59bb6d2178 100644
+--- a/sound/soc/codecs/es8316.c
++++ b/sound/soc/codecs/es8316.c
+@@ -99,7 +99,7 @@ static const struct snd_kcontrol_new es8316_snd_controls[] = {
+ 	SOC_DOUBLE_R_TLV("DAC Playback Volume", ES8316_DAC_VOLL,
+ 			 ES8316_DAC_VOLR, 0, 0xc0, 1, dac_vol_tlv),
+ 	SOC_SINGLE("DAC Soft Ramp Switch", ES8316_DAC_SET1, 4, 1, 1),
+-	SOC_SINGLE("DAC Soft Ramp Rate", ES8316_DAC_SET1, 2, 4, 0),
++	SOC_SINGLE("DAC Soft Ramp Rate", ES8316_DAC_SET1, 2, 3, 0),
+ 	SOC_SINGLE("DAC Notch Filter Switch", ES8316_DAC_SET2, 6, 1, 0),
+ 	SOC_SINGLE("DAC Double Fs Switch", ES8316_DAC_SET2, 7, 1, 0),
+ 	SOC_SINGLE("DAC Stereo Enhancement", ES8316_DAC_SET3, 0, 7, 0),
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
new file mode 100644
index 000000000000..7c726c1530ef
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
@@ -0,0 +1,154 @@
+From ad8a2490ac09eecb6b84949208a794f6085ffbbb Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 25 Sep 2020 21:42:52 -0500
+Subject: ASoC: ec25: New codec driver for the EC25 modem
+
+The EC25 LTE modem has a PCM interface, and supports 16-bit PCM audio at
+an 8 kHz or 16 kHz sameple rate.
+
+Suggested-by: Luca Weiss <luca@z3ntu.xyz>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/codecs/Kconfig  |  3 ++
+ sound/soc/codecs/Makefile |  2 +
+ sound/soc/codecs/ec25.c   | 94 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 99 insertions(+)
+ create mode 100644 sound/soc/codecs/ec25.c
+
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index f78ea2f86fa6..d0f114a11714 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -1089,6 +1089,9 @@ config SND_SOC_HDMI_CODEC
+ 	select SND_PCM_IEC958
+ 	select HDMI
+ 
++config SND_SOC_EC25
++	tristate "EC25 LTE module CODEC"
++
+ config SND_SOC_ES7134
+ 	tristate "Everest Semi ES7134 CODEC"
+ 
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index 7c075539dc47..371a30250ef7 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -116,6 +116,7 @@ snd-soc-da7219-objs := da7219.o da7219-aad.o
+ snd-soc-da732x-objs := da732x.o
+ snd-soc-da9055-objs := da9055.o
+ snd-soc-dmic-objs := dmic.o
++snd-soc-ec25-objs := ec25.o
+ snd-soc-es7134-objs := es7134.o
+ snd-soc-es7241-objs := es7241.o
+ snd-soc-es83xx-dsm-common-objs := es83xx-dsm-common.o
+@@ -511,6 +512,7 @@ obj-$(CONFIG_SND_SOC_DA7219)	+= snd-soc-da7219.o
+ obj-$(CONFIG_SND_SOC_DA732X)	+= snd-soc-da732x.o
+ obj-$(CONFIG_SND_SOC_DA9055)	+= snd-soc-da9055.o
+ obj-$(CONFIG_SND_SOC_DMIC)	+= snd-soc-dmic.o
++obj-$(CONFIG_SND_SOC_EC25)	+= snd-soc-ec25.o
+ obj-$(CONFIG_SND_SOC_ES7134)	+= snd-soc-es7134.o
+ obj-$(CONFIG_SND_SOC_ES7241)	+= snd-soc-es7241.o
+ obj-$(CONFIG_SND_SOC_ES83XX_DSM_COMMON)    += snd-soc-es83xx-dsm-common.o
+diff --git a/sound/soc/codecs/ec25.c b/sound/soc/codecs/ec25.c
+new file mode 100644
+index 000000000000..4f9b6b06cce7
+--- /dev/null
++++ b/sound/soc/codecs/ec25.c
+@@ -0,0 +1,94 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include <linux/module.h>
++#include <sound/soc.h>
++
++static const struct snd_soc_dapm_widget ec25_dapm_widgets[] = {
++	SND_SOC_DAPM_OUTPUT("AOUT"),
++	SND_SOC_DAPM_INPUT("AIN"),
++};
++
++static const struct snd_soc_dapm_route ec25_dapm_routes[] = {
++	{ "AOUT", NULL, "Playback" },
++	{ "AOUT", NULL, "Wideband Playback" },
++	{ "Capture", NULL, "AIN" },
++	{ "Wideband Capture", NULL, "AIN" },
++};
++
++static const struct snd_soc_component_driver ec25_component_driver = {
++	.dapm_widgets		= ec25_dapm_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(ec25_dapm_widgets),
++	.dapm_routes		= ec25_dapm_routes,
++	.num_dapm_routes	= ARRAY_SIZE(ec25_dapm_routes),
++	.endianness		= 1,
++};
++
++static struct snd_soc_dai_driver ec25_dais[] = {
++	{
++		.name = "ec25",
++		.capture = {
++			.stream_name	= "Capture",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_8000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.playback = {
++			.stream_name	= "Playback",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_8000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.symmetric_rate = 1,
++		.symmetric_channels = 1,
++		.symmetric_sample_bits = 1,
++	},
++	{
++		.name = "ec25-wb",
++		.capture = {
++			.stream_name	= "Wideband Capture",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_16000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.playback = {
++			.stream_name	= "Wideband Playback",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_16000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.symmetric_rate = 1,
++		.symmetric_channels = 1,
++		.symmetric_sample_bits = 1,
++	},
++};
++
++static int ec25_codec_probe(struct platform_device *pdev)
++{
++	return devm_snd_soc_register_component(&pdev->dev, &ec25_component_driver,
++					       ec25_dais, ARRAY_SIZE(ec25_dais));
++}
++
++static const struct of_device_id ec25_codec_of_match[] = {
++	{ .compatible = "quectel,ec25", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ec25_codec_of_match);
++
++static struct platform_driver ec25_codec_driver = {
++	.driver	= {
++		.name		= "ec25",
++		.of_match_table	= of_match_ptr(ec25_codec_of_match),
++	},
++	.probe	= ec25_codec_probe,
++};
++
++module_platform_driver(ec25_codec_driver);
++
++MODULE_DESCRIPTION("ASoC ec25 driver");
++MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ec25");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
new file mode 100644
index 000000000000..b5fa1e65db46
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
@@ -0,0 +1,45 @@
+From f8eff538da1a042e61a8304c3413fd2502fc4425 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 15 Aug 2022 02:23:37 +0200
+Subject: ASoC: rockchip: Fix doubling of playback speed after system sleep
+
+There is some issue with CRU on RK3399 that can be reproduced by:
+
+- playing some audio and stopping the playback (so that runtime PM suspends I2S)
+- putting system to deep sleep and resuming it (using mainline TF-A)
+- playing some audio (audio plays at 2x the normal speed)
+
+If the audio is kept playing during system sleep cycle, the issue
+does not manifest. Relevant registers in CRU are identical in bug/
+no-bug scenarios, so this patch is just touching the CRU registers
+without actually changing anything in the end. Touching the registers
+fixes the playback speed, though.
+
+Inspired by: https://github.com/djselbeck/linux/commit/cb4be5dec3fa18c4b344c11fed3fc57aa3bea424
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/rockchip/rockchip_i2s.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
+index b0c3ef030e06..cd2666a5359d 100644
+--- a/sound/soc/rockchip/rockchip_i2s.c
++++ b/sound/soc/rockchip/rockchip_i2s.c
+@@ -115,6 +115,13 @@ static int i2s_runtime_resume(struct device *dev)
+ 	if (ret)
+ 		clk_disable_unprepare(i2s->mclk);
+ 
++	if (ret == 0) {
++		unsigned long rate = clk_get_rate(i2s->mclk);
++
++		clk_set_rate(i2s->mclk, rate - 1);
++		clk_set_rate(i2s->mclk, rate);
++	}
++
+ 	return ret;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun50i-codec-analog-Enable-jack-detection-on-startup.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun50i-codec-analog-Enable-jack-detection-on-startup.patch
new file mode 100644
index 000000000000..cc52e2b7f856
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun50i-codec-analog-Enable-jack-detection-on-startup.patch
@@ -0,0 +1,97 @@
+From e91b24a934f8bbceab109e0dfa3bfd946ff475ae Mon Sep 17 00:00:00 2001
+From: Arnaud Ferraris <arnaud.ferraris@collabora.com>
+Date: Thu, 24 Sep 2020 23:01:57 -0500
+Subject: ASoC: sun50i-codec-analog: Enable jack detection on startup
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This commit adds the necessary setup to enable jack detection on startup
+as well as the callback function enabling the microphone ADC when
+headset bias is enabled. The microphone ADC is also disabled in suspend.
+
+Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
+[Samuel: Moved MICADCEN setup to HBIAS event, added bias hooks]
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Ondřej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun50i-codec-analog.c | 32 ++++++++++++++++++++++++++-
+ 1 file changed, 31 insertions(+), 1 deletion(-)
+
+diff --git a/sound/soc/sunxi/sun50i-codec-analog.c b/sound/soc/sunxi/sun50i-codec-analog.c
+index cedd4de42d1a..2081721a8ff2 100644
+--- a/sound/soc/sunxi/sun50i-codec-analog.c
++++ b/sound/soc/sunxi/sun50i-codec-analog.c
+@@ -116,8 +116,10 @@
+ #define SUN50I_ADDA_HS_MBIAS_CTRL_MMICBIASEN	7
+ 
+ #define SUN50I_ADDA_JACK_MIC_CTRL	0x1d
++#define SUN50I_ADDA_JACK_MIC_CTRL_JACKDETEN	7
+ #define SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN	6
+ #define SUN50I_ADDA_JACK_MIC_CTRL_HMICBIASEN	5
++#define SUN50I_ADDA_JACK_MIC_CTRL_MICADCEN	4
+ 
+ /* mixer controls */
+ static const struct snd_kcontrol_new sun50i_a64_codec_mixer_controls[] = {
+@@ -296,6 +298,19 @@ static const struct snd_kcontrol_new sun50i_codec_earpiece_switch[] = {
+ 			SUN50I_ADDA_EARPIECE_CTRL1_ESPPA_MUTE, 1, 0),
+ };
+ 
++static int sun50i_codec_hbias_event(struct snd_soc_dapm_widget *w,
++				    struct snd_kcontrol *kcontrol, int event)
++{
++	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
++	u32 value = !!SND_SOC_DAPM_EVENT_ON(event);
++
++	regmap_update_bits(component->regmap, SUN50I_ADDA_JACK_MIC_CTRL,
++			   BIT(SUN50I_ADDA_JACK_MIC_CTRL_MICADCEN),
++			   value << SUN50I_ADDA_JACK_MIC_CTRL_MICADCEN);
++
++	return 0;
++}
++
+ static const struct snd_soc_dapm_widget sun50i_a64_codec_widgets[] = {
+ 	/* DAC */
+ 	SND_SOC_DAPM_DAC("Left DAC", NULL, SUN50I_ADDA_MIX_DAC_CTRL,
+@@ -367,7 +382,8 @@ static const struct snd_soc_dapm_widget sun50i_a64_codec_widgets[] = {
+ 	/* Microphone Bias */
+ 	SND_SOC_DAPM_SUPPLY("HBIAS", SUN50I_ADDA_JACK_MIC_CTRL,
+ 			    SUN50I_ADDA_JACK_MIC_CTRL_HMICBIASEN,
+-			    0, NULL, 0),
++			    0, sun50i_codec_hbias_event,
++			    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+ 
+ 	/* Mic input path */
+ 	SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN50I_ADDA_MIC2_CTRL,
+@@ -474,14 +490,28 @@ static const struct snd_soc_dapm_route sun50i_a64_codec_routes[] = {
+ static int sun50i_a64_codec_set_bias_level(struct snd_soc_component *component,
+ 					   enum snd_soc_bias_level level)
+ {
++	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
++	int hbias;
++
+ 	switch (level) {
+ 	case SND_SOC_BIAS_OFF:
++		regmap_clear_bits(component->regmap, SUN50I_ADDA_JACK_MIC_CTRL,
++				   BIT(SUN50I_ADDA_JACK_MIC_CTRL_JACKDETEN) |
++				   BIT(SUN50I_ADDA_JACK_MIC_CTRL_MICADCEN));
++
+ 		regmap_set_bits(component->regmap, SUN50I_ADDA_HP_CTRL,
+ 				BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE));
+ 		break;
+ 	case SND_SOC_BIAS_STANDBY:
+ 		regmap_clear_bits(component->regmap, SUN50I_ADDA_HP_CTRL,
+ 				   BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE));
++
++		hbias = snd_soc_dapm_get_pin_status(dapm, "HBIAS");
++		regmap_update_bits(component->regmap, SUN50I_ADDA_JACK_MIC_CTRL,
++				   BIT(SUN50I_ADDA_JACK_MIC_CTRL_JACKDETEN) |
++				   BIT(SUN50I_ADDA_JACK_MIC_CTRL_MICADCEN),
++				   BIT(SUN50I_ADDA_JACK_MIC_CTRL_JACKDETEN) |
++				   hbias << SUN50I_ADDA_JACK_MIC_CTRL_MICADCEN);
+ 		break;
+ 	default:
+ 		break;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun50i-codec-analog-Move-suspend-resume-to-set_bias_level.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun50i-codec-analog-Move-suspend-resume-to-set_bias_level.patch
new file mode 100644
index 000000000000..40a3a2440a91
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun50i-codec-analog-Move-suspend-resume-to-set_bias_level.patch
@@ -0,0 +1,74 @@
+From 681dbf1e5bb315f78db7f029835594e814313227 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 26 Sep 2020 21:39:27 -0500
+Subject: ASoC: sun50i-codec-analog: Move suspend/resume to set_bias_level
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+With idle_bias_on and suspend_bias_off, there are bias level transitions
+that match the suspend/resume callbacks. However, there are also
+transitions during probe (OFF => STANDBY) and removal (STANDBY => OFF).
+
+By using the set_bias_level hook, the driver can have one copy of code
+that would otherwise be duplicated between the probe/resume and
+suspend/remove hooks.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Ondřej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun50i-codec-analog.c | 29 +++++++++++++++++----------
+ 1 file changed, 18 insertions(+), 11 deletions(-)
+
+diff --git a/sound/soc/sunxi/sun50i-codec-analog.c b/sound/soc/sunxi/sun50i-codec-analog.c
+index 8a32d05e23e1..cedd4de42d1a 100644
+--- a/sound/soc/sunxi/sun50i-codec-analog.c
++++ b/sound/soc/sunxi/sun50i-codec-analog.c
+@@ -471,17 +471,23 @@ static const struct snd_soc_dapm_route sun50i_a64_codec_routes[] = {
+ 	{ "EARPIECE", NULL, "Earpiece Amp" },
+ };
+ 
+-static int sun50i_a64_codec_suspend(struct snd_soc_component *component)
++static int sun50i_a64_codec_set_bias_level(struct snd_soc_component *component,
++					   enum snd_soc_bias_level level)
+ {
+-	return regmap_update_bits(component->regmap, SUN50I_ADDA_HP_CTRL,
+-				  BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE),
+-				  BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE));
+-}
++	switch (level) {
++	case SND_SOC_BIAS_OFF:
++		regmap_set_bits(component->regmap, SUN50I_ADDA_HP_CTRL,
++				BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE));
++		break;
++	case SND_SOC_BIAS_STANDBY:
++		regmap_clear_bits(component->regmap, SUN50I_ADDA_HP_CTRL,
++				   BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE));
++		break;
++	default:
++		break;
++	}
+ 
+-static int sun50i_a64_codec_resume(struct snd_soc_component *component)
+-{
+-	return regmap_update_bits(component->regmap, SUN50I_ADDA_HP_CTRL,
+-				  BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE), 0);
++	return 0;
+ }
+ 
+ static const struct snd_soc_component_driver sun50i_codec_analog_cmpnt_drv = {
+@@ -491,8 +497,9 @@ static const struct snd_soc_component_driver sun50i_codec_analog_cmpnt_drv = {
+ 	.num_dapm_widgets	= ARRAY_SIZE(sun50i_a64_codec_widgets),
+ 	.dapm_routes		= sun50i_a64_codec_routes,
+ 	.num_dapm_routes	= ARRAY_SIZE(sun50i_a64_codec_routes),
+-	.suspend		= sun50i_a64_codec_suspend,
+-	.resume			= sun50i_a64_codec_resume,
++	.set_bias_level		= sun50i_a64_codec_set_bias_level,
++	.idle_bias_on		= true,
++	.suspend_bias_off	= true,
+ };
+ 
+ static const struct of_device_id sun50i_codec_analog_of_match[] = {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
new file mode 100644
index 000000000000..27a62ec33dbc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
@@ -0,0 +1,129 @@
+From 1618af1d37034c16ade604dda25850b5c503f610 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 17 Feb 2024 01:13:39 +0100
+Subject: ASoC: sun8i-codec: Add debug output for jack detection
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 32 +++++++++++++++++++++++++++++++-
+ 1 file changed, 31 insertions(+), 1 deletion(-)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 3414924dd5a3..f3a913d5091b 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -9,6 +9,8 @@
+  * Mylène Josserand <mylene.josserand@free-electrons.com>
+  */
+ 
++#define DEBUG
++
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
+@@ -233,6 +235,7 @@ struct sun8i_codec {
+ 	int				jack_irq;
+ 	int				jack_status;
+ 	int				jack_last_sample;
++	unsigned			jack_last_btn;
+ 	ktime_t				jack_hbias_ready;
+ 	struct mutex			jack_mutex;
+ 	int				last_hmic_irq;
+@@ -1343,6 +1346,8 @@ static void sun8i_codec_set_hmic_bias(struct sun8i_codec *scodec, bool enable)
+ 
+ 	snd_soc_dapm_sync(dapm);
+ 
++	dev_dbg(scodec->component->dev, "HMIC bias %s\n", enable ? "on" : "off");
++
+ 	regmap_update_bits(scodec->regmap, SUN8I_HMIC_CTRL1,
+ 			   irq_mask, enable ? irq_mask : 0);
+ }
+@@ -1351,6 +1356,7 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ {
+ 	struct sun8i_codec *scodec = container_of(work, struct sun8i_codec,
+ 						  jack_work.work);
++	struct device *dev = scodec->component->dev;
+ 	unsigned int mdata;
+ 	int type_mask = scodec->jack->jack->type;
+ 	int type;
+@@ -1362,6 +1368,7 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 			return;
+ 
+ 		scodec->jack_last_sample = -1;
++		scodec->jack_last_btn = 0;
+ 
+ 		if (type_mask & SND_JACK_MICROPHONE) {
+ 			/*
+@@ -1419,6 +1426,8 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 
+ 		snd_soc_jack_report(scodec->jack, type, type_mask);
+ 		scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED;
++
++		dev_dbg(dev, "jack: plug-in reported\n");
+ 	} else if (scodec->jack_status == SUN8I_JACK_STATUS_CONNECTED) {
+ 		if (scodec->last_hmic_irq != SUN8I_HMIC_STS_JACK_OUT_IRQ_ST)
+ 			return;
+@@ -1428,14 +1437,18 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 			sun8i_codec_set_hmic_bias(scodec, false);
+ 
+ 		snd_soc_jack_report(scodec->jack, 0, type_mask);
++
++		dev_dbg(dev, "jack: plug-out reported\n");
+ 	}
+ }
+ 
+ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ {
+ 	struct sun8i_codec *scodec = dev_id;
++	struct device *dev = scodec->component->dev;
+ 	int type = SND_JACK_HEADSET;
+ 	unsigned int status, value;
++	unsigned btn_chg = 0;
+ 
+ 	guard(mutex)(&scodec->jack_mutex);
+ 
+@@ -1447,6 +1460,8 @@ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ 	 * 100ms after each interrupt..
+ 	 */
+ 	if (status & BIT(SUN8I_HMIC_STS_JACK_OUT_IRQ_ST)) {
++		dev_dbg(dev, "jack: irq plug-out\n");
++
+ 		/*
+ 		 * Out interrupt has priority over in interrupt so that if
+ 		 * we get both, we assume the disconnected state, which is
+@@ -1456,6 +1471,8 @@ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ 		mod_delayed_work(system_power_efficient_wq, &scodec->jack_work,
+ 				 msecs_to_jiffies(100));
+ 	} else if (status & BIT(SUN8I_HMIC_STS_JACK_IN_IRQ_ST)) {
++		dev_dbg(dev, "jack: irq plug-in\n");
++
+ 		scodec->last_hmic_irq = SUN8I_HMIC_STS_JACK_IN_IRQ_ST;
+ 		mod_delayed_work(system_power_efficient_wq, &scodec->jack_work,
+ 				 msecs_to_jiffies(100));
+@@ -1489,9 +1506,22 @@ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ 		 * samples are identical.
+ 		 */
+ 		if (scodec->jack_last_sample >= 0 &&
+-		    scodec->jack_last_sample == value)
++		    scodec->jack_last_sample == value) {
+ 			snd_soc_jack_report(scodec->jack, type,
+ 					    scodec->jack->jack->type);
++			btn_chg = (scodec->jack_last_btn ^ type) & SUN8I_CODEC_BUTTONS;
++			scodec->jack_last_btn = type;
++		}
++
++		if (btn_chg & SND_JACK_BTN_0)
++			dev_dbg(dev, "jack: key_%spress BTN_0 (%#x)\n",
++				type & SND_JACK_BTN_0 ? "" : "de", value);
++		if (btn_chg & SND_JACK_BTN_1)
++			dev_dbg(dev, "jack: key_%spress BTN_1 (%#x)\n",
++				type & SND_JACK_BTN_1 ? "" : "de", value);
++		if (btn_chg & SND_JACK_BTN_2)
++			dev_dbg(dev, "jack: key_%spress BTN_2 (%#x)\n",
++				type & SND_JACK_BTN_2 ? "" : "de", value);
+ 
+ 		scodec->jack_last_sample = value;
+ 	}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
new file mode 100644
index 000000000000..47dd07943039
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
@@ -0,0 +1,47 @@
+From 966b205b26c216301d279c82500dada714ccfd62 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Mar 2024 14:55:31 +0100
+Subject: ASoC: sun8i-codec: Allow the jack type to be set via device tree
+
+This makes the codec's jack detection functionality usable from within
+simple-sound-card.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 43795362fed0..097418364985 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -1563,6 +1563,18 @@ static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component)
+ 	scodec->jack = NULL;
+ }
+ 
++static int sun8i_codec_component_get_jack_type(struct snd_soc_component *component)
++{
++	struct device_node *node = component->dev->of_node;
++
++	if (of_property_match_string(node, "jack-type", "headset") >= 0)
++		return SND_JACK_HEADSET | SUN8I_CODEC_BUTTONS;
++	else if (of_property_match_string(node, "jack-type", "headphone") >= 0)
++		return SND_JACK_HEADPHONE;
++
++	return 0;
++}
++
+ static int sun8i_codec_component_set_jack(struct snd_soc_component *component,
+ 					  struct snd_soc_jack *jack, void *data)
+ {
+@@ -1584,6 +1596,7 @@ static const struct snd_soc_component_driver sun8i_soc_component = {
+ 	.dapm_routes		= sun8i_codec_dapm_routes,
+ 	.num_dapm_routes	= ARRAY_SIZE(sun8i_codec_dapm_routes),
+ 	.set_jack		= sun8i_codec_component_set_jack,
++	.get_jack_type		= sun8i_codec_component_get_jack_type,
+ 	.probe			= sun8i_codec_component_probe,
+ 	.idle_bias_on		= 1,
+ 	.suspend_bias_off	= 1,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Enable-bus-clock-at-STANDBY-and-higher-bias.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Enable-bus-clock-at-STANDBY-and-higher-bias.patch
new file mode 100644
index 000000000000..9e296ec1ed87
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Enable-bus-clock-at-STANDBY-and-higher-bias.patch
@@ -0,0 +1,136 @@
+From c932de864ced957de03d686384413ff3f60d3b39 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 26 Sep 2020 20:56:18 -0500
+Subject: ASoC: sun8i-codec: Enable bus clock at STANDBY and higher bias
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For codec variants that have a bus clock, that clock must be running to
+receive interrupts. Since jack and mic accessory detection should work
+even when no audio is playing, that means the bus clock should be
+enabled any time the system is on.
+
+Accomplish that by tying the bus clock to the runtime PM state, which is
+then tied to the bias level not being OFF. Since the codec sets
+idle_bias_on, bias will generally never be OFF. However, we can set
+suspend_bias_off to maintain the power savings of gating the bus clock
+during suspend, when we don't expect jack/accessory detection to work.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Ondřej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 41 ++++++++++++++++++++++++++++-------
+ 1 file changed, 33 insertions(+), 8 deletions(-)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 7b45ddffe990..2a46b96b03cc 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -177,12 +177,14 @@ struct sun8i_codec_aif {
+ };
+ 
+ struct sun8i_codec_quirks {
+-	bool legacy_widgets	: 1;
+-	bool lrck_inversion	: 1;
++	bool	bus_clock	: 1;
++	bool	legacy_widgets	: 1;
++	bool	lrck_inversion	: 1;
+ };
+ 
+ struct sun8i_codec {
+ 	struct regmap			*regmap;
++	struct clk			*clk_bus;
+ 	struct clk			*clk_module;
+ 	const struct sun8i_codec_quirks	*quirks;
+ 	struct sun8i_codec_aif		aifs[SUN8I_CODEC_NAIFS];
+@@ -197,6 +199,14 @@ static int sun8i_codec_runtime_resume(struct device *dev)
+ 	struct sun8i_codec *scodec = dev_get_drvdata(dev);
+ 	int ret;
+ 
++	if (scodec->clk_bus) {
++		ret = clk_prepare_enable(scodec->clk_bus);
++		if (ret) {
++			dev_err(dev, "Failed to enable the bus clock\n");
++			return ret;
++		}
++	}
++
+ 	regcache_cache_only(scodec->regmap, false);
+ 
+ 	ret = regcache_sync(scodec->regmap);
+@@ -215,6 +225,9 @@ static int sun8i_codec_runtime_suspend(struct device *dev)
+ 	regcache_cache_only(scodec->regmap, true);
+ 	regcache_mark_dirty(scodec->regmap);
+ 
++	if (scodec->clk_bus)
++		clk_disable_unprepare(scodec->clk_bus);
++
+ 	return 0;
+ }
+ 
+@@ -1277,6 +1290,7 @@ static const struct snd_soc_component_driver sun8i_soc_component = {
+ 	.num_dapm_routes	= ARRAY_SIZE(sun8i_codec_dapm_routes),
+ 	.probe			= sun8i_codec_component_probe,
+ 	.idle_bias_on		= 1,
++	.suspend_bias_off	= 1,
+ 	.endianness		= 1,
+ };
+ 
+@@ -1299,6 +1313,18 @@ static int sun8i_codec_probe(struct platform_device *pdev)
+ 	if (!scodec)
+ 		return -ENOMEM;
+ 
++	scodec->quirks = of_device_get_match_data(&pdev->dev);
++
++	platform_set_drvdata(pdev, scodec);
++
++	if (scodec->quirks->bus_clock) {
++		scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
++		if (IS_ERR(scodec->clk_bus)) {
++			dev_err(&pdev->dev, "Failed to get the bus clock\n");
++			return PTR_ERR(scodec->clk_bus);
++		}
++	}
++
+ 	scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
+ 	if (IS_ERR(scodec->clk_module)) {
+ 		dev_err(&pdev->dev, "Failed to get the module clock\n");
+@@ -1311,17 +1337,14 @@ static int sun8i_codec_probe(struct platform_device *pdev)
+ 		return PTR_ERR(base);
+ 	}
+ 
+-	scodec->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "bus", base,
+-						   &sun8i_codec_regmap_config);
++	scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
++					       &sun8i_codec_regmap_config);
+ 	if (IS_ERR(scodec->regmap)) {
+ 		dev_err(&pdev->dev, "Failed to create our regmap\n");
+ 		return PTR_ERR(scodec->regmap);
+ 	}
+ 
+-	scodec->quirks = of_device_get_match_data(&pdev->dev);
+-
+-	platform_set_drvdata(pdev, scodec);
+-
++	regcache_cache_only(scodec->regmap, true);
+ 	pm_runtime_enable(&pdev->dev);
+ 	if (!pm_runtime_enabled(&pdev->dev)) {
+ 		ret = sun8i_codec_runtime_resume(&pdev->dev);
+@@ -1357,11 +1380,13 @@ static void sun8i_codec_remove(struct platform_device *pdev)
+ }
+ 
+ static const struct sun8i_codec_quirks sun8i_a33_quirks = {
++	.bus_clock	= true,
+ 	.legacy_widgets	= true,
+ 	.lrck_inversion	= true,
+ };
+ 
+ static const struct sun8i_codec_quirks sun50i_a64_quirks = {
++	.bus_clock	= true,
+ };
+ 
+ static const struct of_device_id sun8i_codec_of_match[] = {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Fix-compilation-without-CONFIG_SND_JACK_INPUT_.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Fix-compilation-without-CONFIG_SND_JACK_INPUT_.patch
new file mode 100644
index 000000000000..f540ff1011f5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Fix-compilation-without-CONFIG_SND_JACK_INPUT_.patch
@@ -0,0 +1,85 @@
+From ce85087f27cac45cf9a850a65dbea293c2705a34 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 26 Mar 2024 17:37:33 +0100
+Subject: ASoC: sun8i-codec: Fix compilation without CONFIG_SND_JACK_INPUT_DEV
+
+Without CONFIG_SND_JACK_INPUT_DEV type doesn't exist in struct snd_jack.
+Store jack type in the driver instead of relying on snd_jack struct.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index af28d9e85d39..5eacd5201227 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -280,6 +280,7 @@ struct sun8i_codec {
+ 	struct delayed_work		jack_work;
+ 	int				jack_irq;
+ 	int				jack_status;
++	int				jack_type;
+ 	int				jack_last_sample;
+ 	unsigned			jack_last_btn;
+ 	ktime_t				jack_hbias_ready;
+@@ -1436,7 +1437,6 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 						  jack_work.work);
+ 	struct device *dev = scodec->component->dev;
+ 	unsigned int mdata;
+-	int type_mask = scodec->jack->jack->type;
+ 	int type;
+ 
+ 	guard(mutex)(&scodec->jack_mutex);
+@@ -1448,7 +1448,7 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 		scodec->jack_last_sample = -1;
+ 		scodec->jack_last_btn = 0;
+ 
+-		if (type_mask & SND_JACK_MICROPHONE) {
++		if (scodec->jack_type & SND_JACK_MICROPHONE) {
+ 			/*
+ 			 * If we were in disconnected state, we enable HBIAS and
+ 			 * wait 600ms before reading initial HDATA value.
+@@ -1461,7 +1461,7 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 			scodec->jack_status = SUN8I_JACK_STATUS_WAITING_HBIAS;
+ 		} else {
+ 			snd_soc_jack_report(scodec->jack, SND_JACK_HEADPHONE,
+-					    type_mask);
++					    scodec->jack_type);
+ 			scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED;
+ 		}
+ 	} else if (scodec->jack_status == SUN8I_JACK_STATUS_WAITING_HBIAS) {
+@@ -1502,7 +1502,7 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 		if (type == SND_JACK_HEADPHONE)
+ 			sun8i_codec_set_hmic_bias(scodec, false);
+ 
+-		snd_soc_jack_report(scodec->jack, type, type_mask);
++		snd_soc_jack_report(scodec->jack, type, scodec->jack_type);
+ 		scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED;
+ 
+ 		dev_dbg(dev, "jack: plug-in reported\n");
+@@ -1511,10 +1511,10 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 			return;
+ 
+ 		scodec->jack_status = SUN8I_JACK_STATUS_DISCONNECTED;
+-		if (type_mask & SND_JACK_MICROPHONE)
++		if (scodec->jack_type & SND_JACK_MICROPHONE)
+ 			sun8i_codec_set_hmic_bias(scodec, false);
+ 
+-		snd_soc_jack_report(scodec->jack, 0, type_mask);
++		snd_soc_jack_report(scodec->jack, 0, scodec->jack_type);
+ 
+ 		dev_dbg(dev, "jack: plug-out reported\n");
+ 	}
+@@ -1586,7 +1586,7 @@ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ 		if (scodec->jack_last_sample >= 0 &&
+ 		    scodec->jack_last_sample == value) {
+ 			snd_soc_jack_report(scodec->jack, type,
+-					    scodec->jack->jack->type);
++					    scodec->jack_type);
+ 			btn_chg = (scodec->jack_last_btn ^ type) & SUN8I_CODEC_BUTTONS;
+ 			scodec->jack_last_btn = type;
+ 		}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Implement-jack-and-accessory-detection.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Implement-jack-and-accessory-detection.patch
new file mode 100644
index 000000000000..8a6c4cd14651
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Implement-jack-and-accessory-detection.patch
@@ -0,0 +1,470 @@
+From 1428a27e66eb0b72aeec6866acc4b319dbad7977 Mon Sep 17 00:00:00 2001
+From: Arnaud Ferraris <arnaud.ferraris@collabora.com>
+Date: Fri, 25 Sep 2020 20:28:14 -0500
+Subject: ASoC: sun8i-codec: Implement jack and accessory detection
+
+Add support for the jack detection functionality in the A64 variant,
+which uses a pair of IRQs; and microphone accessory (button) detection,
+which uses an ADC with an IRQ trigger.
+
+IRQs will only be triggered if the JACKDETEN, HMICBIASEN, and MICADCEN
+bits are set appropriately in the analog codec component
+(sun50i-codec-analog), but there is no direct software dependency
+between the two components.
+
+Setup ADC so that it samples with period of 16ms, disable smoothing
+and enable MDATA threshold (should be below idle voltage/HMIC_DATA
+value). Also enable HMIC_N, which makes sure we get HMIC_N samples
+after HMIC_DATA crosses the threshold.
+
+This allows us to perform steady state detection of HMIC_DATA, by
+comparing current and previous ADC samples, to detect end of the
+transient when the user de-presses the button. Otherwise ADC could
+sample anywhere within the transient, and the driver may mis-issue
+key-press events for other buttons attached to the resistor ladder.
+
+Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
+[Samuel: Decouple from analog codec, fixes]
+Co-developed-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+[Ondrej: Almost complete rewrite of the patch, change to use set_jack/
+get_jack_type. Better de-bounce, fix mic button handling, better
+interrupt processing.]
+Co-developed-by: Ondrej Jirman <megi@xff.cz>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun50i-codec-analog.c |  12 +
+ sound/soc/sunxi/sun8i-codec.c         | 305 ++++++++++++++++++++++++++
+ 2 files changed, 317 insertions(+)
+
+diff --git a/sound/soc/sunxi/sun50i-codec-analog.c b/sound/soc/sunxi/sun50i-codec-analog.c
+index 2081721a8ff2..2dcdf113b66e 100644
+--- a/sound/soc/sunxi/sun50i-codec-analog.c
++++ b/sound/soc/sunxi/sun50i-codec-analog.c
+@@ -115,6 +115,11 @@
+ #define SUN50I_ADDA_HS_MBIAS_CTRL	0x0e
+ #define SUN50I_ADDA_HS_MBIAS_CTRL_MMICBIASEN	7
+ 
++#define SUN50I_ADDA_MDET_CTRL		0x1c
++#define SUN50I_ADDA_MDET_CTRL_SELDETADC_FS	4
++#define SUN50I_ADDA_MDET_CTRL_SELDETADC_DB	2
++#define SUN50I_ADDA_MDET_CTRL_SELDETADC_BF	0
++
+ #define SUN50I_ADDA_JACK_MIC_CTRL	0x1d
+ #define SUN50I_ADDA_JACK_MIC_CTRL_JACKDETEN	7
+ #define SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN	6
+@@ -564,6 +569,13 @@ static int sun50i_codec_analog_probe(struct platform_device *pdev)
+ 			   BIT(SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN),
+ 			   enable << SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN);
+ 
++	/* Select sample interval of the ADC sample to 16ms */
++	regmap_update_bits(regmap, SUN50I_ADDA_MDET_CTRL,
++			   0x7 << SUN50I_ADDA_MDET_CTRL_SELDETADC_FS |
++			   0x3 << SUN50I_ADDA_MDET_CTRL_SELDETADC_BF,
++			   0x3 << SUN50I_ADDA_MDET_CTRL_SELDETADC_FS |
++			   0x3 << SUN50I_ADDA_MDET_CTRL_SELDETADC_BF);
++
+ 	return devm_snd_soc_register_component(&pdev->dev,
+ 					       &sun50i_codec_analog_cmpnt_drv,
+ 					       NULL, 0);
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 2a46b96b03cc..43795362fed0 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -12,12 +12,16 @@
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
++#include <linux/input.h>
+ #include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/mutex.h>
+ #include <linux/of.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/log2.h>
+ 
++#include <sound/jack.h>
+ #include <sound/pcm_params.h>
+ #include <sound/soc.h>
+ #include <sound/soc-dapm.h>
+@@ -118,6 +122,23 @@
+ #define SUN8I_ADC_VOL_CTRL				0x104
+ #define SUN8I_ADC_VOL_CTRL_ADCL_VOL			8
+ #define SUN8I_ADC_VOL_CTRL_ADCR_VOL			0
++#define SUN8I_HMIC_CTRL1				0x110
++#define SUN8I_HMIC_CTRL1_HMIC_M				12
++#define SUN8I_HMIC_CTRL1_HMIC_N				8
++#define SUN8I_HMIC_CTRL1_MDATA_THRESHOLD_DB		5
++#define SUN8I_HMIC_CTRL1_JACK_OUT_IRQ_EN		4
++#define SUN8I_HMIC_CTRL1_JACK_IN_IRQ_EN			3
++#define SUN8I_HMIC_CTRL1_HMIC_DATA_IRQ_EN		0
++#define SUN8I_HMIC_CTRL2				0x114
++#define SUN8I_HMIC_CTRL2_HMIC_SAMPLE			14
++#define SUN8I_HMIC_CTRL2_HMIC_MDATA_THRESHOLD		8
++#define SUN8I_HMIC_CTRL2_HMIC_SF			6
++#define SUN8I_HMIC_STS					0x118
++#define SUN8I_HMIC_STS_MDATA_DISCARD			13
++#define SUN8I_HMIC_STS_HMIC_DATA			8
++#define SUN8I_HMIC_STS_JACK_OUT_IRQ_ST			4
++#define SUN8I_HMIC_STS_JACK_IN_IRQ_ST			3
++#define SUN8I_HMIC_STS_HMIC_DATA_IRQ_ST			0
+ #define SUN8I_DAC_DIG_CTRL				0x120
+ #define SUN8I_DAC_DIG_CTRL_ENDA				15
+ #define SUN8I_DAC_VOL_CTRL				0x124
+@@ -143,6 +164,17 @@
+ #define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK	GENMASK(5, 4)
+ #define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK	GENMASK(3, 2)
+ #define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_MASK	GENMASK(1, 0)
++#define SUN8I_HMIC_CTRL1_HMIC_M_MASK		GENMASK(15, 12)
++#define SUN8I_HMIC_CTRL1_HMIC_N_MASK		GENMASK(11, 8)
++#define SUN8I_HMIC_CTRL1_MDATA_THRESHOLD_DB_MASK GENMASK(6, 5)
++#define SUN8I_HMIC_CTRL2_HMIC_SAMPLE_MASK	GENMASK(15, 14)
++#define SUN8I_HMIC_CTRL2_HMIC_SF_MASK		GENMASK(7, 6)
++#define SUN8I_HMIC_STS_HMIC_DATA_MASK		GENMASK(12, 8)
++
++#define SUN8I_CODEC_BUTTONS	(SND_JACK_BTN_0|\
++				 SND_JACK_BTN_1|\
++				 SND_JACK_BTN_2|\
++				 SND_JACK_BTN_3)
+ 
+ #define SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE 48000
+ 
+@@ -178,16 +210,32 @@ struct sun8i_codec_aif {
+ 
+ struct sun8i_codec_quirks {
+ 	bool	bus_clock	: 1;
++	bool	jack_detection	: 1;
+ 	bool	legacy_widgets	: 1;
+ 	bool	lrck_inversion	: 1;
+ };
+ 
++enum {
++	SUN8I_JACK_STATUS_DISCONNECTED,
++	SUN8I_JACK_STATUS_WAITING_HBIAS,
++	SUN8I_JACK_STATUS_CONNECTED,
++};
++
+ struct sun8i_codec {
++	struct snd_soc_component	*component;
+ 	struct regmap			*regmap;
+ 	struct clk			*clk_bus;
+ 	struct clk			*clk_module;
+ 	const struct sun8i_codec_quirks	*quirks;
+ 	struct sun8i_codec_aif		aifs[SUN8I_CODEC_NAIFS];
++	struct snd_soc_jack		*jack;
++	struct delayed_work		jack_work;
++	int				jack_irq;
++	int				jack_status;
++	int				jack_last_sample;
++	ktime_t				jack_hbias_ready;
++	struct mutex			jack_mutex;
++	int				last_hmic_irq;
+ 	unsigned int			sysclk_rate;
+ 	int				sysclk_refcnt;
+ };
+@@ -1245,6 +1293,8 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component)
+ 	struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
+ 	int ret;
+ 
++	scodec->component = component;
++
+ 	/* Add widgets for backward compatibility with old device trees. */
+ 	if (scodec->quirks->legacy_widgets) {
+ 		ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_legacy_widgets,
+@@ -1281,6 +1331,251 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component)
+ 	return 0;
+ }
+ 
++static void sun8i_codec_set_hmic_bias(struct sun8i_codec *scodec, bool enable)
++{
++	struct snd_soc_dapm_context *dapm = &scodec->component->card->dapm;
++	int irq_mask = BIT(SUN8I_HMIC_CTRL1_HMIC_DATA_IRQ_EN);
++
++	if (enable)
++		snd_soc_dapm_force_enable_pin(dapm, "HBIAS");
++	else
++		snd_soc_dapm_disable_pin(dapm, "HBIAS");
++
++	snd_soc_dapm_sync(dapm);
++
++	regmap_update_bits(scodec->regmap, SUN8I_HMIC_CTRL1,
++			   irq_mask, enable ? irq_mask : 0);
++}
++
++static void sun8i_codec_jack_work(struct work_struct *work)
++{
++	struct sun8i_codec *scodec = container_of(work, struct sun8i_codec,
++						  jack_work.work);
++	unsigned int mdata;
++	int type_mask = scodec->jack->jack->type;
++	int type;
++
++	guard(mutex)(&scodec->jack_mutex);
++
++	if (scodec->jack_status == SUN8I_JACK_STATUS_DISCONNECTED) {
++		if (scodec->last_hmic_irq != SUN8I_HMIC_STS_JACK_IN_IRQ_ST)
++			return;
++
++		scodec->jack_last_sample = -1;
++
++		if (type_mask & SND_JACK_MICROPHONE) {
++			/*
++			 * If we were in disconnected state, we enable HBIAS and
++			 * wait 600ms before reading initial HDATA value.
++			 */
++			scodec->jack_hbias_ready = ktime_add_ms(ktime_get(), 600);
++			sun8i_codec_set_hmic_bias(scodec, true);
++			queue_delayed_work(system_power_efficient_wq,
++					   &scodec->jack_work,
++					   msecs_to_jiffies(610));
++			scodec->jack_status = SUN8I_JACK_STATUS_WAITING_HBIAS;
++		} else {
++			snd_soc_jack_report(scodec->jack, SND_JACK_HEADPHONE,
++					    type_mask);
++			scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED;
++		}
++	} else if (scodec->jack_status == SUN8I_JACK_STATUS_WAITING_HBIAS) {
++		/*
++		 * If we're waiting for HBIAS to stabilize, and we get plug-out
++		 * interrupt and nothing more for > 100ms, just cancel the
++		 * initialization.
++		 */
++		if (scodec->last_hmic_irq == SUN8I_HMIC_STS_JACK_OUT_IRQ_ST) {
++			scodec->jack_status = SUN8I_JACK_STATUS_DISCONNECTED;
++			sun8i_codec_set_hmic_bias(scodec, false);
++			return;
++		}
++
++		/*
++		 * If we're not done waiting for HBIAS to stabilize, wait more.
++		 */
++		if (!ktime_after(ktime_get(), scodec->jack_hbias_ready)) {
++			s64 msecs = ktime_ms_delta(scodec->jack_hbias_ready,
++						   ktime_get());
++
++			queue_delayed_work(system_power_efficient_wq,
++					   &scodec->jack_work,
++					   msecs_to_jiffies(msecs + 10));
++			return;
++		}
++
++		/*
++		 * Everything is stabilized, determine jack type and report it.
++		 */
++		regmap_read(scodec->regmap, SUN8I_HMIC_STS, &mdata);
++		mdata &= SUN8I_HMIC_STS_HMIC_DATA_MASK;
++		mdata >>= SUN8I_HMIC_STS_HMIC_DATA;
++
++		regmap_write(scodec->regmap, SUN8I_HMIC_STS, 0);
++
++		type = mdata < 16 ? SND_JACK_HEADPHONE : SND_JACK_HEADSET;
++		if (type == SND_JACK_HEADPHONE)
++			sun8i_codec_set_hmic_bias(scodec, false);
++
++		snd_soc_jack_report(scodec->jack, type, type_mask);
++		scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED;
++	} else if (scodec->jack_status == SUN8I_JACK_STATUS_CONNECTED) {
++		if (scodec->last_hmic_irq != SUN8I_HMIC_STS_JACK_OUT_IRQ_ST)
++			return;
++
++		scodec->jack_status = SUN8I_JACK_STATUS_DISCONNECTED;
++		if (type_mask & SND_JACK_MICROPHONE)
++			sun8i_codec_set_hmic_bias(scodec, false);
++
++		snd_soc_jack_report(scodec->jack, 0, type_mask);
++	}
++}
++
++static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
++{
++	struct sun8i_codec *scodec = dev_id;
++	int type = SND_JACK_HEADSET;
++	unsigned int status, value;
++
++	guard(mutex)(&scodec->jack_mutex);
++
++	regmap_read(scodec->regmap, SUN8I_HMIC_STS, &status);
++	regmap_write(scodec->regmap, SUN8I_HMIC_STS, status);
++
++	/*
++	 * De-bounce in/out interrupts via a delayed work re-scheduling to
++	 * 100ms after each interrupt..
++	 */
++	if (status & BIT(SUN8I_HMIC_STS_JACK_OUT_IRQ_ST)) {
++		/*
++		 * Out interrupt has priority over in interrupt so that if
++		 * we get both, we assume the disconnected state, which is
++		 * safer.
++		 */
++		scodec->last_hmic_irq = SUN8I_HMIC_STS_JACK_OUT_IRQ_ST;
++		mod_delayed_work(system_power_efficient_wq, &scodec->jack_work,
++				 msecs_to_jiffies(100));
++	} else if (status & BIT(SUN8I_HMIC_STS_JACK_IN_IRQ_ST)) {
++		scodec->last_hmic_irq = SUN8I_HMIC_STS_JACK_IN_IRQ_ST;
++		mod_delayed_work(system_power_efficient_wq, &scodec->jack_work,
++				 msecs_to_jiffies(100));
++	} else if (status & BIT(SUN8I_HMIC_STS_HMIC_DATA_IRQ_ST)) {
++		/*
++		 * Ignore data interrupts until jack status turns to connected
++		 * state, which is after HMIC enable stabilization is completed.
++		 * Until then tha data are bogus.
++		 */
++		if (scodec->jack_status != SUN8I_JACK_STATUS_CONNECTED)
++			return IRQ_HANDLED;
++
++		value = (status & SUN8I_HMIC_STS_HMIC_DATA_MASK) >>
++			SUN8I_HMIC_STS_HMIC_DATA;
++
++		/*
++		 * Assumes 60 mV per ADC LSB increment, 2V bias voltage, 2.2kOhm
++		 * bias resistor.
++		 */
++		if (value == 0)
++			type |= SND_JACK_BTN_0;
++		else if (value == 1)
++			type |= SND_JACK_BTN_3;
++		else if (value <= 3)
++			type |= SND_JACK_BTN_1;
++		else if (value <= 8)
++			type |= SND_JACK_BTN_2;
++
++		/*
++		 * De-bounce. Only report button after two consecutive A/D
++		 * samples are identical.
++		 */
++		if (scodec->jack_last_sample >= 0 &&
++		    scodec->jack_last_sample == value)
++			snd_soc_jack_report(scodec->jack, type,
++					    scodec->jack->jack->type);
++
++		scodec->jack_last_sample = value;
++	}
++
++	return IRQ_HANDLED;
++}
++
++static int sun8i_codec_enable_jack_detect(struct snd_soc_component *component,
++					  struct snd_soc_jack *jack, void *data)
++{
++	struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
++	struct platform_device *pdev = to_platform_device(component->dev);
++	int ret;
++
++	if (!scodec->quirks->jack_detection)
++		return 0;
++
++	scodec->jack = jack;
++
++	scodec->jack_irq = platform_get_irq(pdev, 0);
++	if (scodec->jack_irq < 0)
++		return scodec->jack_irq;
++
++	/* Reserved value required for jack IRQs to trigger. */
++	regmap_write(scodec->regmap, SUN8I_HMIC_CTRL1,
++			   0xf << SUN8I_HMIC_CTRL1_HMIC_N |
++			   0x0 << SUN8I_HMIC_CTRL1_MDATA_THRESHOLD_DB |
++			   0x4 << SUN8I_HMIC_CTRL1_HMIC_M);
++
++	/* Sample the ADC at 128 Hz; bypass smooth filter. */
++	regmap_write(scodec->regmap, SUN8I_HMIC_CTRL2,
++			   0x0 << SUN8I_HMIC_CTRL2_HMIC_SAMPLE |
++			   0x17 << SUN8I_HMIC_CTRL2_HMIC_MDATA_THRESHOLD |
++			   0x0 << SUN8I_HMIC_CTRL2_HMIC_SF);
++
++	/* Do not discard any MDATA, enable user written MDATA threshold. */
++	regmap_write(scodec->regmap, SUN8I_HMIC_STS, 0);
++
++	regmap_set_bits(scodec->regmap, SUN8I_HMIC_CTRL1,
++			BIT(SUN8I_HMIC_CTRL1_JACK_OUT_IRQ_EN) |
++			BIT(SUN8I_HMIC_CTRL1_JACK_IN_IRQ_EN));
++
++	ret = devm_request_threaded_irq(&pdev->dev, scodec->jack_irq,
++					NULL, sun8i_codec_jack_irq,
++					IRQF_ONESHOT,
++					dev_name(&pdev->dev), scodec);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component)
++{
++	struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
++
++	if (!scodec->quirks->jack_detection)
++		return;
++
++	devm_free_irq(component->dev, scodec->jack_irq, scodec);
++
++	cancel_delayed_work_sync(&scodec->jack_work);
++
++	regmap_clear_bits(scodec->regmap, SUN8I_HMIC_CTRL1,
++			  BIT(SUN8I_HMIC_CTRL1_JACK_OUT_IRQ_EN) |
++			  BIT(SUN8I_HMIC_CTRL1_JACK_IN_IRQ_EN) |
++			  BIT(SUN8I_HMIC_CTRL1_HMIC_DATA_IRQ_EN));
++
++	scodec->jack = NULL;
++}
++
++static int sun8i_codec_component_set_jack(struct snd_soc_component *component,
++					  struct snd_soc_jack *jack, void *data)
++{
++	int ret = 0;
++
++	if (jack)
++		ret = sun8i_codec_enable_jack_detect(component, jack, data);
++	else
++		sun8i_codec_disable_jack_detect(component);
++
++	return ret;
++}
++
+ static const struct snd_soc_component_driver sun8i_soc_component = {
+ 	.controls		= sun8i_codec_controls,
+ 	.num_controls		= ARRAY_SIZE(sun8i_codec_controls),
+@@ -1288,16 +1583,23 @@ static const struct snd_soc_component_driver sun8i_soc_component = {
+ 	.num_dapm_widgets	= ARRAY_SIZE(sun8i_codec_dapm_widgets),
+ 	.dapm_routes		= sun8i_codec_dapm_routes,
+ 	.num_dapm_routes	= ARRAY_SIZE(sun8i_codec_dapm_routes),
++	.set_jack		= sun8i_codec_component_set_jack,
+ 	.probe			= sun8i_codec_component_probe,
+ 	.idle_bias_on		= 1,
+ 	.suspend_bias_off	= 1,
+ 	.endianness		= 1,
+ };
+ 
++static bool sun8i_codec_volatile_reg(struct device *dev, unsigned int reg)
++{
++	return reg == SUN8I_HMIC_STS;
++}
++
+ static const struct regmap_config sun8i_codec_regmap_config = {
+ 	.reg_bits	= 32,
+ 	.reg_stride	= 4,
+ 	.val_bits	= 32,
++	.volatile_reg	= sun8i_codec_volatile_reg,
+ 	.max_register	= SUN8I_DAC_MXR_SRC,
+ 
+ 	.cache_type	= REGCACHE_FLAT,
+@@ -1314,6 +1616,8 @@ static int sun8i_codec_probe(struct platform_device *pdev)
+ 		return -ENOMEM;
+ 
+ 	scodec->quirks = of_device_get_match_data(&pdev->dev);
++	INIT_DELAYED_WORK(&scodec->jack_work, sun8i_codec_jack_work);
++	mutex_init(&scodec->jack_mutex);
+ 
+ 	platform_set_drvdata(pdev, scodec);
+ 
+@@ -1387,6 +1691,7 @@ static const struct sun8i_codec_quirks sun8i_a33_quirks = {
+ 
+ static const struct sun8i_codec_quirks sun50i_a64_quirks = {
+ 	.bus_clock	= true,
++	.jack_detection	= true,
+ };
+ 
+ static const struct of_device_id sun8i_codec_of_match[] = {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
new file mode 100644
index 000000000000..15108df820a9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
@@ -0,0 +1,48 @@
+From 2b74262d12ff80f1ad1229bc74c5019257630697 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 26 Mar 2024 17:38:38 +0100
+Subject: ASoC: sun8i-codec: Set jack_type from DT in probe
+
+Jack type needs to be set in probe so that it can be used later on.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 5eacd5201227..2e4581f371a7 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -1680,14 +1680,9 @@ static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component)
+ 
+ static int sun8i_codec_component_get_jack_type(struct snd_soc_component *component)
+ {
+-	struct device_node *node = component->dev->of_node;
+-
+-	if (of_property_match_string(node, "jack-type", "headset") >= 0)
+-		return SND_JACK_HEADSET | SUN8I_CODEC_BUTTONS;
+-	else if (of_property_match_string(node, "jack-type", "headphone") >= 0)
+-		return SND_JACK_HEADPHONE;
++	struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
+ 
+-	return 0;
++	return scodec->jack_type;
+ }
+ 
+ static int sun8i_codec_component_set_jack(struct snd_soc_component *component,
+@@ -1861,6 +1856,11 @@ static int sun8i_codec_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, scodec);
+ 
++	if (of_property_match_string(pdev->dev.of_node, "jack-type", "headset") >= 0)
++		scodec->jack_type = SND_JACK_HEADSET | SUN8I_CODEC_BUTTONS;
++	else if (of_property_match_string(pdev->dev.of_node, "jack-type", "headphone") >= 0)
++		scodec->jack_type = SND_JACK_HEADPHONE;
++
+ 	if (scodec->quirks->bus_clock) {
+ 		scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
+ 		if (IS_ERR(scodec->clk_bus)) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
new file mode 100644
index 000000000000..4970dc7551eb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
@@ -0,0 +1,31 @@
+From 89bc1ac0f6f4dabdb1bbb50e4347795c67c1745e Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 23 Feb 2024 01:58:40 +0100
+Subject: ASoC: sun8i-codec: define button keycodes
+
+This is likely not upstreamable, but simple. :)
+---
+ sound/soc/sunxi/sun8i-codec.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 097418364985..3414924dd5a3 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -1541,6 +1541,13 @@ static int sun8i_codec_enable_jack_detect(struct snd_soc_component *component,
+ 	if (ret)
+ 		return ret;
+ 
++	if (jack->jack->type & SND_JACK_MICROPHONE) {
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
++	}
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
new file mode 100644
index 000000000000..fd39015358a1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
@@ -0,0 +1,215 @@
+From 0c18f57b5dd36076a2160c62ffcc9cb1475bfd8b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 22 Nov 2016 01:01:49 +0100
+Subject: Add README.md with information and u-boot patches
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ ...Fix-PLL1-setup-to-never-use-dividers.patch |  33 ++++
+ README.md                                     | 154 ++++++++++++++++++
+ 2 files changed, 187 insertions(+)
+ create mode 100644 0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
+ create mode 100644 README.md
+
+diff --git a/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch b/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
+new file mode 100644
+index 000000000000..2b892e805a2b
+--- /dev/null
++++ b/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
+@@ -0,0 +1,33 @@
++From 7f5071f906f79bdc99d6b4b0ccf0cb280abe740b Mon Sep 17 00:00:00 2001
++From: Ondrej Jirman <megi@xff.cz>
++Date: Tue, 20 Dec 2016 11:25:12 +0100
++Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers
++
++Kernel would lower the divider on first CLK change and cause the
++lock up.
++---
++ arch/arm/mach-sunxi/clock_sun6i.c | 7 +++----
++ 1 file changed, 3 insertions(+), 4 deletions(-)
++
++diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
++index 50fb302a19..91aa2a0478 100644
++--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++++ b/arch/arm/mach-sunxi/clock_sun6i.c
++@@ -94,11 +94,10 @@ void clock_set_pll1(unsigned int clk)
++ 	int k = 1;
++ 	int m = 1;
++ 
++-	if (clk > 1152000000) {
++-		k = 2;
++-	} else if (clk > 768000000) {
+++	if (clk >= 1368000000) {
++ 		k = 3;
++-		m = 2;
+++	} else if (clk >= 768000000) {
+++		k = 2;
++ 	}
++ 
++ 	/* Switch to 24MHz clock while changing PLL1 */
++-- 
++2.11.0
++
+diff --git a/README.md b/README.md
+new file mode 100644
+index 000000000000..74c4c16416d3
+--- /dev/null
++++ b/README.md
+@@ -0,0 +1,154 @@
++Mainline linux kernel for Orange Pi PC/PC2/PC3/One, TBS A711, PinePhone (Pro), PocketBook Touch Lux 3
++------------------------------------------------------------------------------------------------------
++
++This kernel tree is meant for:
++
++- Orange Pi One
++- Orange Pi PC
++- Orange Pi PC 2
++- Orange Pi 3
++- PinePhone 1.0, 1.1 and 1.2(a/b)
++- TBS A711 Tablet
++- PocketBook Touch Lux 3
++- Pinebook Pro
++- Pinephone Pro
++
++Features in addition to mainline:
++
++- [Orange Pi One/PC/PC2] More aggressive OPPs for CPU
++- [All] Mark one of DRM planes as a cursor plane, speeding up Xorg based desktop with modesetting driver
++- [Orange Pi One/PC/PC2] Configure on-board micro-switches to perform system power off function
++- [Orange Pi One/PC/PC2/3] HDMI audio
++- [Orange Pi 3] Ethernet
++- [TBS A711] HM5065 (back camera) / GC2145 (front camera)
++- [PinePhone] WiFi, Bluetooth, Audio, Modem power, HDMI out over USB-C, USB-C support, cameras, PMIC improvements, power management, fixes here and there
++- [PocketBook Touch Lux 3] Display and Touchscreen support
++- [Pinephone Pro] Everything
++
++Pre-built u-boot and kernels are available at https://xff.cz/kernels/
++
++You may need some firmware files for some part of the functionality. Those are
++available at: https://megous.com/git/linux-firmware
++
++If you want to reproduce my pre-built kernels exactly, you'll need to uncomment
++CONFIG_EXTRA_FIRMWARE_DIR and CONFIG_EXTRA_FIRMWARE in the defconfigs, and
++point CONFIG_EXTRA_FIRMWARE_DIR to a directory on your computer where the
++clone of https://megous.com/git/linux-firmware resides.
++
++You can also leave those two config options commented out, and copy the contents
++of https://megous.com/git/linux-firmware to /lib/firmware/ on the target device.
++
++You can use this kernel to run a desktop environment on Orange Pi SBCs,
++Arch Linux on your Pinephone, or to have a completely opensource OS on
++a Pocketbook e-ink book reader.
++
++Have fun!
++
++
++Build instructions
++------------------
++
++These are rudimentary instructions and you need to understand what you're doing.
++These are just core steps required to build the ATF/u-boot/kernel. Downloading,
++verifying, renaming to correct directories is not described or mentioned. You
++should be able to infer missing necessary steps yourself for your particular needs.
++
++Get necessary toolchains from:
++
++- https://releases.linaro.org/components/toolchain/binaries/latest/aarch64-linux-gnu/ for 64bit Orange Pi PC2 and Orange Pi 3, PinePhone
++- https://releases.linaro.org/components/toolchain/binaries/latest/arm-linux-gnueabihf/ for 32bit Orange Pis, Pocketbook, TBS tablet
++
++Extract toolchains and prepare the environment:
++
++    CWD=`pwd`
++    OUT=$CWD/builds
++    SRC=$CWD/u-boot
++    export PATH="$PATH:$CWD/Toolchains/arm/bin:$CWD/Toolchains/aarch64/bin"
++
++For Orange Pi PC2, Orange Pi 3 or PinePhone:
++
++    export CROSS_COMPILE=aarch64-linux-gnu-
++    export KBUILD_OUTPUT=$OUT/.tmp/uboot-pc2
++    rm -rf "$KBUILD_OUTPUT"
++    mkdir -p $KBUILD_OUTPUT $OUT/pc2
++
++Get and build ATF from https://github.com/ARM-software/arm-trusted-firmware:
++
++    make -C "$CWD/arm-trusted-firmware" PLAT=sun50i_a64 DEBUG=1 bl31
++    cp "$CWD/arm-trusted-firmware/build/sun50i_a64/debug/bl31.bin" "$KBUILD_OUTPUT"
++
++Use sun50i_a64 for Orange Pi PC2 or PinePhone and sun50i_h6 for Orange Pi 3.
++
++Build u-boot from https://megous.com/git/u-boot/ (opi-v2020.04 branch) with appropriate
++defconfig (orangepi_one_defconfig, orangepi_pc2_defconfig, orangepi_pc_defconfig, orangepi_3_defconfig, tbs_a711_defconfig, pinephone_defconfig).
++
++My u-boot branch already has all the necessary patches integrated and is configured for quick u-boot/kernel startup.
++
++    make -C u-boot orangepi_pc2_defconfig
++    make -C u-boot -j5
++    
++    cp $KBUILD_OUTPUT/.config $OUT/pc2/uboot.config
++    cat $KBUILD_OUTPUT/{spl/sunxi-spl.bin,u-boot.itb} > $OUT/pc2/uboot.bin
++
++Get kernel from this repository and checkout the latest orange-pi-5.18 branch.
++
++Build the kernel for 64-bit boards:
++
++    export ARCH=arm64
++    export CROSS_COMPILE=aarch64-linux-gnu-
++    export KBUILD_OUTPUT=$OUT/.tmp/linux-arm64
++    mkdir -p $KBUILD_OUTPUT $OUT/pc2
++
++    make -C linux orangepi_defconfig
++    # or make -C linux pocketbook_touch_lux_3_defconfig
++    # or make -C linux tbs_a711_defconfig
++    make -C linux -j5 clean
++    make -C linux -j5 Image dtbs
++
++    cp -f $KBUILD_OUTPUT/arch/arm64/boot/Image $OUT/pc2/
++    cp -f $KBUILD_OUTPUT/.config $OUT/pc2/linux.config
++    cp -f $KBUILD_OUTPUT/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dtb $OUT/pc2/board.dtb
++
++Build the kernel for 32-bit boards:
++
++    export ARCH=arm
++    export CROSS_COMPILE=arm-linux-gnueabihf-
++    export KBUILD_OUTPUT=$OUT/.tmp/linux-arm
++    mkdir -p $KBUILD_OUTPUT $OUT/pc
++
++    make orangepi_defconfig
++    # or make pinephone_defconfig
++    make -C linux orangepi_defconfig
++    make -C linux -j5 clean
++    make -C linux -j5 zImage dtbs
++    
++    cp -f $KBUILD_OUTPUT/arch/arm/boot/zImage $OUT/pc/
++    cp -f $KBUILD_OUTPUT/.config $OUT/pc/linux.config
++    cp -f $KBUILD_OUTPUT/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb $OUT/pc/board.dtb
++    # Or use sun8i-h3-orangepi-one.dtb for Orange Pi One
++
++
++PinePhone
++---------
++
++I don't run u-boot on PinePhone, so my pre-built kernel packages don't come
++with u-boot built for PinePhone.
++
++
++Kernel lockup issues
++--------------------
++
++*If you're getting lockups on boot or later during thermal regulation,
++you're missing an u-boot patch.*
++
++This patch is necessary to run this kernel!
++
++These lockups are caused by improper NKMP clock factors selection
++in u-boot for PLL_CPUX. (M divider should not be used. P divider
++should be used only for frequencies below 240MHz.)
++
++This patch for u-boot fixes it:
++
++  0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
++
++Kernel side is already fixed in this kernel tree.
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/Add-support-for-my-private-Sapomat-device.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/Add-support-for-my-private-Sapomat-device.patch
new file mode 100644
index 000000000000..4372ed662a6b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/Add-support-for-my-private-Sapomat-device.patch
@@ -0,0 +1,66 @@
+From 1fd2051a41b18663256744e80e3ed3863cc858ba Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 18 Aug 2017 13:56:06 +0200
+Subject: Add support for my private Sapomat device
+
+---
+ arch/arm/boot/dts/allwinner/Makefile          |  1 +
+ .../sun8i-h3-orangepi-pc-sapomat.dts          | 34 +++++++++++++++++++
+ 2 files changed, 35 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts
+
+diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
+index 2d26c3397f14..7c7fb94d2153 100644
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-h3-orangepi-lite.dtb \
+ 	sun8i-h3-orangepi-one.dtb \
+ 	sun8i-h3-orangepi-pc.dtb \
++	sun8i-h3-orangepi-pc-sapomat.dtb \
+ 	sun8i-h3-orangepi-pc-plus.dtb \
+ 	sun8i-h3-orangepi-plus.dtb \
+ 	sun8i-h3-orangepi-plus2e.dtb \
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts
+new file mode 100644
+index 000000000000..55c82d5fb63f
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts
+@@ -0,0 +1,34 @@
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include "sun8i-h3-orangepi-pc.dts"
++
++/ {
++	model = "Xunlong Orange Pi PC Sapomat";
++
++	sapomat_gpio_keys {
++		compatible = "gpio-keys-polled";
++		poll-interval = <50>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&sapomat_btn_pins>;
++
++		red_btn {
++			label = "Red Button";
++			linux,code = <BTN_4>;
++			gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; /* PC4 */
++		};
++
++		green_btn {
++			label = "Green Button";
++			linux,code = <BTN_5>;
++			gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
++		};
++	};
++};
++
++&pio {
++	sapomat_btn_pins: btn_pins@0 {
++		pins = "PC4", "PC7";
++		function = "gpio_in";
++		bias-pull-up;
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/Defconfigs-for-all-my-devices.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/Defconfigs-for-all-my-devices.patch
new file mode 100644
index 000000000000..d70dd8235e22
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/Defconfigs-for-all-my-devices.patch
@@ -0,0 +1,3989 @@
+From 70c1f4eff2824e1f4ed03e81ccae8048fe9f0cb1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 16 Sep 2019 00:35:50 +0200
+Subject: Defconfigs for all my devices
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/configs/orangepi_defconfig           |  694 +++++++++++
+ .../configs/pocketbook_touch_lux_3_defconfig  |  416 +++++++
+ arch/arm/configs/tbs_a711_defconfig           |  528 +++++++++
+ arch/arm64/configs/orangepi_defconfig         | 1038 +++++++++++++++++
+ arch/arm64/configs/pinephone_defconfig        |  651 +++++++++++
+ .../configs/pinephone_multidist_defconfig     |  602 ++++++++++
+ 6 files changed, 3929 insertions(+)
+ create mode 100644 arch/arm/configs/orangepi_defconfig
+ create mode 100644 arch/arm/configs/pocketbook_touch_lux_3_defconfig
+ create mode 100644 arch/arm/configs/tbs_a711_defconfig
+ create mode 100644 arch/arm64/configs/orangepi_defconfig
+ create mode 100644 arch/arm64/configs/pinephone_defconfig
+ create mode 100644 arch/arm64/configs/pinephone_multidist_defconfig
+
+diff --git a/arch/arm/configs/orangepi_defconfig b/arch/arm/configs/orangepi_defconfig
+new file mode 100644
+index 000000000000..2ebd59970d3b
+--- /dev/null
++++ b/arch/arm/configs/orangepi_defconfig
+@@ -0,0 +1,694 @@
++CONFIG_KERNEL_LZ4=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_BOOT_CONFIG=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_BCM=y
++CONFIG_ARCH_BCM2835=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_MACH_SUN9I is not set
++CONFIG_ARM_LPAE=y
++CONFIG_ARM_ERRATA_814220=y
++CONFIG_SMP=y
++CONFIG_SCHED_MC=y
++CONFIG_MCPM=y
++CONFIG_NR_CPUS=8
++CONFIG_HOTPLUG_CPU=y
++CONFIG_HZ_300=y
++CONFIG_HIGHMEM=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_ARCH_FORCE_MAX_ORDER=11
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
++CONFIG_ARM_RASPBERRYPI_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++# CONFIG_SUSPEND is not set
++CONFIG_PM=y
++CONFIG_APM_EMULATION=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_NET_KEY=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_NET_IPIP=y
++CONFIG_IP_MROUTE=y
++CONFIG_SYN_COOKIES=y
++CONFIG_INET_UDP_DIAG=y
++CONFIG_INET_RAW_DIAG=y
++CONFIG_INET_DIAG_DESTROY=y
++CONFIG_IPV6_MIP6=y
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_ACCT=y
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_FTP=y
++CONFIG_NF_CONNTRACK_H323=y
++CONFIG_NF_CONNTRACK_IRC=y
++CONFIG_NF_CONNTRACK_NETBIOS_NS=y
++CONFIG_NF_CONNTRACK_SNMP=y
++CONFIG_NF_CONNTRACK_PPTP=y
++CONFIG_NF_CONNTRACK_SIP=y
++CONFIG_NF_CONNTRACK_TFTP=y
++CONFIG_NF_CT_NETLINK=y
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=y
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=y
++CONFIG_NFT_CT=y
++CONFIG_NFT_CONNLIMIT=y
++CONFIG_NFT_LOG=y
++CONFIG_NFT_LIMIT=y
++CONFIG_NFT_MASQ=y
++CONFIG_NFT_REDIR=y
++CONFIG_NFT_NAT=y
++CONFIG_NFT_TUNNEL=y
++CONFIG_NFT_QUEUE=y
++CONFIG_NFT_QUOTA=y
++CONFIG_NFT_REJECT=y
++CONFIG_NFT_HASH=y
++CONFIG_NFT_FIB_INET=y
++CONFIG_NFT_SOCKET=y
++CONFIG_NFT_OSF=y
++CONFIG_NFT_TPROXY=y
++CONFIG_NFT_DUP_NETDEV=y
++CONFIG_NFT_FWD_NETDEV=y
++CONFIG_NFT_FIB_NETDEV=y
++CONFIG_NFT_REJECT_NETDEV=y
++CONFIG_NF_FLOW_TABLE_INET=y
++CONFIG_NF_FLOW_TABLE=y
++CONFIG_IP_SET=y
++CONFIG_IP_SET_BITMAP_IP=y
++CONFIG_IP_SET_BITMAP_IPMAC=y
++CONFIG_IP_SET_BITMAP_PORT=y
++CONFIG_IP_SET_HASH_IP=y
++CONFIG_IP_SET_HASH_IPMARK=y
++CONFIG_IP_SET_HASH_IPPORT=y
++CONFIG_IP_SET_HASH_IPPORTIP=y
++CONFIG_IP_SET_HASH_IPPORTNET=y
++CONFIG_IP_SET_HASH_IPMAC=y
++CONFIG_IP_SET_HASH_MAC=y
++CONFIG_IP_SET_HASH_NETPORTNET=y
++CONFIG_IP_SET_HASH_NET=y
++CONFIG_IP_SET_HASH_NETNET=y
++CONFIG_IP_SET_HASH_NETPORT=y
++CONFIG_IP_SET_HASH_NETIFACE=y
++CONFIG_IP_SET_LIST_SET=y
++CONFIG_NFT_DUP_IPV4=y
++CONFIG_NFT_FIB_IPV4=y
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_NFT_DUP_IPV6=y
++CONFIG_NFT_FIB_IPV6=y
++CONFIG_NF_LOG_IPV6=y
++CONFIG_NF_TABLES_BRIDGE=y
++CONFIG_NFT_BRIDGE_REJECT=y
++CONFIG_IP_SCTP=y
++CONFIG_SCTP_COOKIE_HMAC_SHA1=y
++CONFIG_TIPC=y
++CONFIG_L2TP=y
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=y
++CONFIG_BRIDGE=y
++CONFIG_BRIDGE_VLAN_FILTERING=y
++CONFIG_VLAN_8021Q=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_BPF=y
++CONFIG_NET_CLS_MATCHALL=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_NET_TC_SKB_EXT=y
++CONFIG_BT=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_HS=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIBTSDIO=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_NFC=y
++CONFIG_NFC_DIGITAL=y
++CONFIG_NFC_NCI=y
++CONFIG_NFC_NXP_NCI=y
++CONFIG_NFC_NXP_NCI_I2C=y
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s edid/asus.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_RASPBERRYPI_FIRMWARE=y
++CONFIG_GNSS=y
++CONFIG_GNSS_SIRF_SERIAL=y
++CONFIG_GNSS_UBX_SERIAL=y
++CONFIG_OF_OVERLAY=y
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_INTEGRITY=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=y
++CONFIG_TUN=y
++CONFIG_VETH=y
++# CONFIG_NET_VENDOR_ALACRITECH is not set
++# CONFIG_NET_VENDOR_ALLWINNER is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AQUANTIA is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CADENCE is not set
++# CONFIG_NET_VENDOR_CAVIUM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_NET_VENDOR_CORTINA is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FARADAY is not set
++# CONFIG_NET_VENDOR_GOOGLE is not set
++# CONFIG_NET_VENDOR_HISILICON is not set
++# CONFIG_NET_VENDOR_HUAWEI is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MELLANOX is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_MICROSEMI is not set
++# CONFIG_NET_VENDOR_NI is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_NET_VENDOR_PENSANDO is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SOLARFLARE is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_SOCIONEXT is not set
++CONFIG_STMMAC_ETH=y
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_NET_VENDOR_XILINX is not set
++CONFIG_LED_TRIGGER_PHY=y
++CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
++CONFIG_PPP=y
++CONFIG_PPP_BSDCOMP=y
++CONFIG_PPP_DEFLATE=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=y
++CONFIG_PPPOL2TP=y
++CONFIG_PPP_ASYNC=y
++CONFIG_PPP_SYNC_TTY=y
++CONFIG_USB_RTL8152=y
++CONFIG_USB_USBNET=y
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=y
++# CONFIG_USB_NET_CDC_NCM is not set
++CONFIG_USB_NET_SMSC95XX=y
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_BRCMFMAC=y
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++CONFIG_RT2X00=y
++CONFIG_RT2800USB=y
++# CONFIG_RT2800USB_RT35XX is not set
++CONFIG_RT2800USB_RT53XX=y
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_ADC=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EDT_FT5X06=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_BCM2835AUX=y
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_HW_RANDOM=y
++# CONFIG_HW_RANDOM_IPROC_RNG200 is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_BCM2835=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_I2C_SUN6I_P2WI=y
++CONFIG_SPI=y
++CONFIG_SPI_BCM2835=y
++CONFIG_SPI_BCM2835AUX=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SUN6I=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_POWER_RESET=y
++CONFIG_POWER_RESET_GPIO=y
++CONFIG_POWER_RESET_GPIO_RESTART=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++CONFIG_SENSORS_RASPBERRYPI_HWMON=y
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_BCM2835_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_BCM2835_WDT=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_SY8106A=y
++CONFIG_RC_CORE=y
++CONFIG_BPF_LIRC_MODE2=y
++CONFIG_LIRC=y
++CONFIG_RC_DECODERS=y
++CONFIG_IR_JVC_DECODER=y
++CONFIG_IR_MCE_KBD_DECODER=y
++CONFIG_IR_NEC_DECODER=y
++CONFIG_IR_RC5_DECODER=y
++CONFIG_IR_RC6_DECODER=y
++CONFIG_IR_SANYO_DECODER=y
++CONFIG_IR_SHARP_DECODER=y
++CONFIG_IR_SONY_DECODER=y
++CONFIG_IR_XMP_DECODER=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=y
++CONFIG_IR_SUNXI=y
++CONFIG_MEDIA_CEC_RC=y
++CONFIG_MEDIA_CEC_SUPPORT=y
++CONFIG_MEDIA_SUPPORT=y
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
++CONFIG_VIDEO_SUN6I_CSI=y
++CONFIG_VIDEO_SUN8I_DEINTERLACE=y
++CONFIG_VIDEO_SUN8I_ROTATE=y
++# CONFIG_VIDEO_IR_I2C is not set
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_SUN4I_HDMI_CEC=y
++# CONFIG_DRM_SUN6I_DSI is not set
++CONFIG_DRM_PANEL_LVDS=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_VC4=y
++CONFIG_DRM_VC4_HDMI_CEC=y
++CONFIG_DRM_LIMA=y
++CONFIG_FB=y
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_HRTIMER=y
++CONFIG_SND_SEQUENCER=y
++CONFIG_SND_SEQUENCER_OSS=y
++CONFIG_SND_DUMMY=y
++CONFIG_SND_ALOOP=y
++# CONFIG_SND_SPI is not set
++CONFIG_SND_USB_AUDIO=y
++CONFIG_SND_SOC=y
++CONFIG_SND_BCM2835_SOC_I2S=y
++CONFIG_SND_SUN4I_CODEC=y
++CONFIG_SND_SUN8I_CODEC=y
++CONFIG_SND_SUN8I_CODEC_ANALOG=y
++CONFIG_SND_SUN4I_I2S=y
++CONFIG_SND_SUN4I_SPDIF=y
++CONFIG_SND_SOC_SPDIF=y
++CONFIG_SND_SIMPLE_CARD=y
++CONFIG_SND_AUDIO_GRAPH_CARD=y
++CONFIG_HIDRAW=y
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=y
++CONFIG_USB_PRINTER=y
++CONFIG_USB_WDM=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_UAS=y
++CONFIG_USBIP_CORE=y
++CONFIG_USBIP_VHCI_HCD=y
++CONFIG_USBIP_HOST=y
++CONFIG_USBIP_VUDC=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SUNXI=y
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_CH341=y
++CONFIG_USB_SERIAL_CP210X=y
++CONFIG_USB_SERIAL_FTDI_SIO=y
++CONFIG_USB_SERIAL_PL2303=y
++CONFIG_USB_SERIAL_OPTION=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_GADGET=y
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=y
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_CDC_COMPOSITE=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_MMC_BCM2835=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_SYSFS is not set
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_AC100=y
++CONFIG_RTC_DRV_SUNXI=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_BCM2835=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=y
++# CONFIG_BCM_VIDEOCORE is not set
++CONFIG_CLK_RASPBERRYPI=y
++# CONFIG_CLK_SUNXI_CLOCKS is not set
++# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
++# CONFIG_SUN4I_A10_CCU is not set
++# CONFIG_SUN5I_CCU is not set
++# CONFIG_SUN6I_A31_CCU is not set
++# CONFIG_SUN8I_A23_CCU is not set
++# CONFIG_SUN8I_A33_CCU is not set
++# CONFIG_SUN8I_V3S_CCU is not set
++# CONFIG_SUN8I_R40_CCU is not set
++CONFIG_MAILBOX=y
++CONFIG_BCM2835_MBOX=y
++# CONFIG_SUN6I_MSGBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_RASPBERRYPI_POWER=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_CONFIGFS=y
++CONFIG_BMA180=y
++CONFIG_AXP20X_ADC=y
++CONFIG_LTR501=y
++CONFIG_AK8975=y
++CONFIG_PWM=y
++CONFIG_PWM_BCM2835=y
++CONFIG_PWM_SUN4I=y
++CONFIG_RESET_RASPBERRYPI=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_XFS_FS=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_OVERLAY_FS=y
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_VFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_ECRYPT_FS=y
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V2 is not set
++# CONFIG_NFS_V3 is not set
++CONFIG_NFS_V4=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_2=y
++CONFIG_NFS_FSCACHE=y
++# CONFIG_NFS_V4_2_READ_PLUS is not set
++CONFIG_NFSD=y
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++CONFIG_CIFS=y
++# CONFIG_CIFS_STATS2 is not set
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++# CONFIG_CIFS_DEBUG is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_AES_TI=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_BLAKE2B=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_GHASH_ARM_CE=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=y
++CONFIG_CRYPTO_SHA1_ARM_CE=y
++CONFIG_CRYPTO_SHA2_ARM_CE=y
++CONFIG_CRYPTO_SHA512_ARM=y
++CONFIG_CRYPTO_AES_ARM=y
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRYPTO_AES_ARM_CE=y
++CONFIG_CRYPTO_CRC32_ARM_CE=y
++CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=y
++CONFIG_CRYPTO_DEV_SUN8I_SS=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=128
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DEBUG_KERNEL=y
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
++CONFIG_WQ_WATCHDOG=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_FTRACE is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm/configs/pocketbook_touch_lux_3_defconfig b/arch/arm/configs/pocketbook_touch_lux_3_defconfig
+new file mode 100644
+index 000000000000..2d5db37e86cb
+--- /dev/null
++++ b/arch/arm/configs/pocketbook_touch_lux_3_defconfig
+@@ -0,0 +1,416 @@
++CONFIG_KERNEL_LZ4=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_HZ_PERIODIC=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_BOOT_CONFIG=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_MACH_SUN4I is not set
++# CONFIG_MACH_SUN6I is not set
++# CONFIG_MACH_SUN7I is not set
++# CONFIG_MACH_SUN8I is not set
++# CONFIG_MACH_SUN9I is not set
++CONFIG_ARM_ERRATA_430973=y
++CONFIG_ARM_ERRATA_814220=y
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_ARM_PSCI=y
++CONFIG_HZ_1000=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_ARCH_FORCE_MAX_ORDER=11
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_BLK_DEV_INTEGRITY=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=m
++CONFIG_XFRM_SUB_POLICY=y
++CONFIG_INET=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_DIAG is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_CONNLIMIT=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_MASQ=m
++CONFIG_NFT_REDIR=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_TUNNEL=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_QUOTA=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_SOCKET=m
++CONFIG_NFT_OSF=m
++CONFIG_NFT_DUP_NETDEV=m
++CONFIG_NFT_FWD_NETDEV=m
++CONFIG_NF_FLOW_TABLE_INET=m
++CONFIG_NF_FLOW_TABLE=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPMARK=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_IPMAC=m
++CONFIG_IP_SET_HASH_MAC=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_NF_SOCKET_IPV4=y
++CONFIG_NF_TABLES_IPV4=y
++CONFIG_NFT_DUP_IPV4=m
++CONFIG_NFT_FIB_IPV4=m
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++CONFIG_NF_REJECT_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_MAC80211_DEBUGFS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s rtlwifi/rtl8188eufw.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++# CONFIG_FW_CACHE is not set
++CONFIG_SUNXI_RSB=y
++CONFIG_MTD=y
++# CONFIG_MTD_OF_PARTS is not set
++CONFIG_MTD_BLOCK_RO=y
++CONFIG_MTD_SPI_NOR=m
++CONFIG_OF_OVERLAY=y
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=m
++CONFIG_TUN=y
++# CONFIG_ETHERNET is not set
++# CONFIG_USB_NET_DRIVERS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_RTL_CARDS is not set
++CONFIG_RTL8XXXU=m
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_SILABS is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
++CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_AXP20X_PEK=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_SPI=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++CONFIG_SENSORS_NTC_THERMISTOR=y
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_MFD_SYSCON=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER_OF=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_TP65185X=y
++CONFIG_DRM=y
++CONFIG_FB=y
++CONFIG_FB_SUN5I_EINK=m
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++# CONFIG_HID is not set
++# CONFIG_USB_HID is not set
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=m
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=m
++CONFIG_USB_LEDS_TRIGGER_USBPORT=m
++CONFIG_USB_EHCI_HCD=m
++CONFIG_USB_EHCI_HCD_PLATFORM=m
++CONFIG_USB_OHCI_HCD=m
++CONFIG_USB_OHCI_HCD_PLATFORM=m
++CONFIG_USB_WDM=m
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_SUNXI=m
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_NOP_USB_XCEIV=m
++CONFIG_USB_GADGET=m
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_CDC_COMPOSITE=m
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_SYSFS is not set
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_PCF8563=y
++CONFIG_DMADEVICES=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set
++# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set
++# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PM_DEVFREQ=y
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_CONFIGFS=y
++CONFIG_BMA180=y
++CONFIG_AXP20X_ADC=y
++CONFIG_SUN4I_GPADC=m
++CONFIG_LTR501=y
++CONFIG_AK8975=y
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_VFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++# CONFIG_MISC_FILESYSTEMS is not set
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_BIG_KEYS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_ECDH=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_AES_TI=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_ESSIV=y
++CONFIG_CRYPTO_BLAKE2B=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_CURVE25519_NEON=y
++CONFIG_CRYPTO_GHASH_ARM_CE=y
++CONFIG_CRYPTO_POLY1305_ARM=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=y
++CONFIG_CRYPTO_SHA1_ARM_CE=y
++CONFIG_CRYPTO_SHA2_ARM_CE=y
++CONFIG_CRYPTO_SHA512_ARM=y
++CONFIG_CRYPTO_AES_ARM=y
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRYPTO_AES_ARM_CE=y
++CONFIG_CRYPTO_CHACHA20_NEON=y
++CONFIG_CRYPTO_CRC32_ARM_CE=y
++CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++CONFIG_CRYPTO_LIB_CURVE25519=y
++CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC_ITU_T=y
++CONFIG_LIBCRC32C=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=128
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DEBUG_FS=y
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm/configs/tbs_a711_defconfig b/arch/arm/configs/tbs_a711_defconfig
+new file mode 100644
+index 000000000000..f28899833bbf
+--- /dev/null
++++ b/arch/arm/configs/tbs_a711_defconfig
+@@ -0,0 +1,528 @@
++CONFIG_KERNEL_LZ4=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_MACH_SUN9I is not set
++CONFIG_ARM_ERRATA_814220=y
++CONFIG_SMP=y
++CONFIG_SCHED_MC=y
++CONFIG_MCPM=y
++CONFIG_NR_CPUS=8
++CONFIG_HZ_1000=y
++CONFIG_HIGHMEM=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_ARCH_FORCE_MAX_ORDER=11
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_PM_ADVANCED_DEBUG=y
++CONFIG_APM_EMULATION=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_BLK_DEV_INTEGRITY=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++# CONFIG_BFQ_GROUP_IOSCHED is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_INET=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_SYN_COOKIES=y
++CONFIG_INET_DIAG=m
++CONFIG_INET_UDP_DIAG=m
++CONFIG_INET_RAW_DIAG=m
++# CONFIG_IPV6_SIT is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=m
++CONFIG_NETFILTER_NETLINK_ACCT=m
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_INET=y
++CONFIG_NFT_NUMGEN=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_CONNLIMIT=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_MASQ=m
++CONFIG_NFT_REDIR=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_TUNNEL=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_QUOTA=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_FIB_INET=m
++CONFIG_NFT_SOCKET=m
++CONFIG_NFT_OSF=m
++CONFIG_NF_FLOW_TABLE_INET=m
++CONFIG_NF_FLOW_TABLE=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPMARK=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_IPMAC=m
++CONFIG_IP_SET_HASH_MAC=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_NFT_DUP_IPV4=m
++CONFIG_NFT_FIB_IPV4=m
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=m
++CONFIG_NF_LOG_IPV4=m
++CONFIG_NFT_DUP_IPV6=m
++CONFIG_NFT_FIB_IPV6=m
++CONFIG_NF_LOG_IPV6=m
++CONFIG_NF_TABLES_BRIDGE=m
++CONFIG_NFT_BRIDGE_REJECT=m
++CONFIG_BRIDGE=m
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_MATCHALL=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_BT=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++CONFIG_BT_HS=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIBTSDIO=m
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_CFG80211=y
++# CONFIG_CFG80211_DEFAULT_PS is not set
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_NFC=m
++CONFIG_NFC_DIGITAL=m
++CONFIG_NFC_NCI=m
++CONFIG_NFC_NXP_NCI=m
++CONFIG_NFC_NXP_NCI_I2C=m
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s brcm/brcmfmac43362-sdio.bin brcm/brcmfmac43362-sdio.txt brcm/BCM20702A1.hcd hm5065-af.bin hm5065-init.bin brcm/brcmfmac43362-sdio.tbs-biometrics,a711.txt"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++# CONFIG_FW_CACHE is not set
++CONFIG_ARM_SCPI_PROTOCOL=m
++CONFIG_GNSS=y
++CONFIG_GNSS_SIRF_SERIAL=y
++CONFIG_GNSS_UBX_SERIAL=y
++CONFIG_OF_OVERLAY=y
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_MODEM_POWER=m
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++# CONFIG_ETHERNET is not set
++CONFIG_PPP=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=m
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++# CONFIG_USB_NET_DRIVERS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_BRCMFMAC=m
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EDT_FT5X06=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_SPI=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SUN6I=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AC100=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_SYSCON=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_MEDIA_SUPPORT=m
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_VIDEO_ADV_DEBUG=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
++CONFIG_VIDEO_SUN6I_CSI=m
++CONFIG_VIDEO_SUN8I_DEINTERLACE=m
++CONFIG_VIDEO_SUN8I_ROTATE=m
++CONFIG_VIDEO_HM5065=m
++CONFIG_VIDEO_GC2145=m
++CONFIG_DRM=y
++CONFIG_DRM_SUN4I=y
++# CONFIG_DRM_SUN4I_HDMI is not set
++# CONFIG_DRM_SUN4I_BACKEND is not set
++# CONFIG_DRM_SUN6I_DSI is not set
++# CONFIG_DRM_SUN8I_DW_HDMI is not set
++CONFIG_DRM_PANEL_LVDS=y
++CONFIG_FB=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_SOUND=m
++CONFIG_SND=m
++CONFIG_SND_HRTIMER=m
++# CONFIG_SND_SUPPORT_OLD_API is not set
++CONFIG_SND_DEBUG=y
++CONFIG_SND_DEBUG_VERBOSE=y
++# CONFIG_SND_DRIVERS is not set
++# CONFIG_SND_ARM is not set
++# CONFIG_SND_SPI is not set
++# CONFIG_SND_USB is not set
++CONFIG_SND_SOC=m
++CONFIG_SND_SUN8I_CODEC=m
++CONFIG_SND_AC100_CODEC=m
++CONFIG_SND_SUN4I_I2S=m
++CONFIG_SND_SOC_BT_SCO=m
++CONFIG_SND_SOC_EC25=m
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_HIDRAW=y
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=m
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=m
++CONFIG_USB_LEDS_TRIGGER_USBPORT=m
++CONFIG_USB_EHCI_HCD=m
++CONFIG_USB_EHCI_HCD_PLATFORM=m
++CONFIG_USB_OHCI_HCD=m
++CONFIG_USB_OHCI_HCD_PLATFORM=m
++CONFIG_USB_ACM=m
++CONFIG_USB_WDM=m
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_SUNXI=m
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_NOP_USB_XCEIV=m
++CONFIG_USB_GADGET=m
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_ETH=m
++CONFIG_USB_ETH_EEM=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_AXP20X=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_BACKLIGHT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_SYSFS is not set
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_AC100=y
++# CONFIG_RTC_DRV_SUN6I is not set
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=m
++# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
++# CONFIG_SUN4I_A10_CCU is not set
++# CONFIG_SUN5I_CCU is not set
++# CONFIG_SUN6I_A31_CCU is not set
++# CONFIG_SUN8I_A23_CCU is not set
++# CONFIG_SUN8I_A33_CCU is not set
++# CONFIG_SUN8I_V3S_CCU is not set
++# CONFIG_SUN8I_R40_CCU is not set
++CONFIG_MAILBOX=y
++# CONFIG_IOMMU_SUPPORT is not set
++# CONFIG_ARM_SCPI_POWER_DOMAIN is not set
++CONFIG_IIO=y
++CONFIG_IIO_KFIFO_BUF=y
++CONFIG_IIO_CONFIGFS=y
++CONFIG_BMA180=m
++CONFIG_AXP20X_ADC=y
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++# CONFIG_MISC_FILESYSTEMS is not set
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_ECDH=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_AES_TI=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_BLAKE2B=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_DEFLATE=m
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_LZ4HC=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=m
++CONFIG_CRYPTO_USER_API_SKCIPHER=m
++CONFIG_CRYPTO_USER_API_RNG=m
++CONFIG_CRYPTO_USER_API_AEAD=m
++CONFIG_CRYPTO_CURVE25519_NEON=y
++CONFIG_CRYPTO_POLY1305_ARM=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=y
++CONFIG_CRYPTO_SHA1_ARM_CE=y
++CONFIG_CRYPTO_SHA2_ARM_CE=y
++CONFIG_CRYPTO_SHA512_ARM=y
++CONFIG_CRYPTO_AES_ARM=y
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRYPTO_AES_ARM_CE=y
++CONFIG_CRYPTO_CRC32_ARM_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=m
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=m
++CONFIG_CRYPTO_DEV_SUN8I_SS=m
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC_ITU_T=y
++CONFIG_LIBCRC32C=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DEBUG_KERNEL=y
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
++CONFIG_WQ_WATCHDOG=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_RCU_TRACE is not set
++CONFIG_BOOTTIME_TRACING=y
++CONFIG_FUNCTION_TRACER=y
++# CONFIG_UPROBE_EVENTS is not set
++CONFIG_UNWINDER_FRAME_POINTER=y
++CONFIG_DEBUG_LL=y
++CONFIG_EARLY_PRINTK=y
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm64/configs/orangepi_defconfig b/arch/arm64/configs/orangepi_defconfig
+new file mode 100644
+index 000000000000..82f1448bbf14
+--- /dev/null
++++ b/arch/arm64/configs/orangepi_defconfig
+@@ -0,0 +1,1038 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_WATCH_QUEUE=y
++CONFIG_GENERIC_IRQ_DEBUGFS=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_BPF_JIT_ALWAYS_ON=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_PREEMPT_VOLUNTARY=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_PSI=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=20
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=14
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_BPF=y
++CONFIG_CGROUP_MISC=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++CONFIG_RELAY=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_BOOT_CONFIG=y
++CONFIG_KALLSYMS_ALL=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_ARCH_ROCKCHIP=y
++# CONFIG_ARM64_ERRATUM_832075 is not set
++# CONFIG_ARM64_ERRATUM_834220 is not set
++# CONFIG_ARM64_ERRATUM_1542419 is not set
++# CONFIG_ARM64_ERRATUM_1508412 is not set
++# CONFIG_ARM64_ERRATUM_2051678 is not set
++# CONFIG_ARM64_ERRATUM_2077057 is not set
++# CONFIG_ARM64_ERRATUM_2658417 is not set
++# CONFIG_ARM64_ERRATUM_2054223 is not set
++# CONFIG_ARM64_ERRATUM_2067961 is not set
++# CONFIG_ARM64_ERRATUM_2441009 is not set
++# CONFIG_ARM64_ERRATUM_2645198 is not set
++# CONFIG_ARM64_ERRATUM_2966298 is not set
++# CONFIG_CAVIUM_ERRATUM_22375 is not set
++# CONFIG_CAVIUM_ERRATUM_23144 is not set
++# CONFIG_CAVIUM_ERRATUM_23154 is not set
++# CONFIG_CAVIUM_ERRATUM_27456 is not set
++# CONFIG_CAVIUM_ERRATUM_30115 is not set
++# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
++# CONFIG_FUJITSU_ERRATUM_010001 is not set
++# CONFIG_HISILICON_ERRATUM_161600802 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
++# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
++# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set
++CONFIG_ARM64_VA_BITS_48=y
++CONFIG_SCHED_MC=y
++CONFIG_SCHED_CLUSTER=y
++CONFIG_NR_CPUS=8
++CONFIG_NUMA=y
++CONFIG_NODES_SHIFT=3
++CONFIG_PARAVIRT=y
++CONFIG_COMPAT=y
++CONFIG_ARM64_PMEM=y
++# CONFIG_ARM64_PTR_AUTH is not set
++# CONFIG_ARM64_AMU_EXTN is not set
++# CONFIG_ARM64_TLB_RANGE is not set
++# CONFIG_ARM64_BTI is not set
++# CONFIG_ARM64_E0PD is not set
++# CONFIG_ARM64_MTE is not set
++# CONFIG_ARM64_EPAN is not set
++# CONFIG_ARM64_SVE is not set
++# CONFIG_EFI is not set
++CONFIG_HIBERNATION=y
++CONFIG_PM_AUTOSLEEP=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
++CONFIG_ARM_SCPI_CPUFREQ=y
++CONFIG_ARM_ROCKCHIP_CPUFREQ=y
++CONFIG_ARM_SCMI_CPUFREQ=y
++CONFIG_VIRTUALIZATION=y
++CONFIG_KVM=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++CONFIG_BLK_CGROUP_IOPRIO=y
++CONFIG_BLK_INLINE_ENCRYPTION=y
++CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_BINFMT_MISC=y
++CONFIG_ZSWAP=y
++CONFIG_ZSWAP_DEFAULT_ON=y
++CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4=y
++CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
++CONFIG_Z3FOLD=y
++CONFIG_ZSMALLOC_STAT=y
++CONFIG_TRANSPARENT_HUGEPAGE=y
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_SYSFS=y
++CONFIG_CMA_AREAS=7
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=y
++CONFIG_XDP_SOCKETS=y
++CONFIG_XDP_SOCKETS_DIAG=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_NET_IPIP=y
++CONFIG_IP_MROUTE=y
++CONFIG_INET_UDP_DIAG=y
++CONFIG_INET_RAW_DIAG=y
++CONFIG_INET_DIAG_DESTROY=y
++CONFIG_IPV6_ROUTER_PREF=y
++CONFIG_IPV6_ROUTE_INFO=y
++CONFIG_IPV6_OPTIMISTIC_DAD=y
++CONFIG_IPV6_MIP6=y
++CONFIG_IPV6_TUNNEL=y
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_HOOK=y
++CONFIG_NETFILTER_NETLINK_ACCT=y
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NF_CONNTRACK_TIMEOUT=y
++CONFIG_NF_CONNTRACK_TIMESTAMP=y
++CONFIG_NF_CONNTRACK_LABELS=y
++CONFIG_NF_CONNTRACK_FTP=y
++CONFIG_NF_CONNTRACK_H323=y
++CONFIG_NF_CONNTRACK_IRC=y
++CONFIG_NF_CONNTRACK_NETBIOS_NS=y
++CONFIG_NF_CONNTRACK_SNMP=y
++CONFIG_NF_CONNTRACK_PPTP=y
++CONFIG_NF_CONNTRACK_SANE=y
++CONFIG_NF_CONNTRACK_SIP=y
++CONFIG_NF_CONNTRACK_TFTP=y
++CONFIG_NF_CT_NETLINK=y
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=y
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=y
++CONFIG_NFT_CT=y
++CONFIG_NFT_FLOW_OFFLOAD=y
++CONFIG_NFT_CONNLIMIT=y
++CONFIG_NFT_LOG=y
++CONFIG_NFT_LIMIT=y
++CONFIG_NFT_MASQ=y
++CONFIG_NFT_REDIR=y
++CONFIG_NFT_NAT=y
++CONFIG_NFT_TUNNEL=y
++CONFIG_NFT_QUEUE=y
++CONFIG_NFT_QUOTA=y
++CONFIG_NFT_REJECT=y
++CONFIG_NFT_HASH=y
++CONFIG_NFT_FIB_INET=y
++CONFIG_NFT_SOCKET=y
++CONFIG_NFT_OSF=y
++CONFIG_NFT_TPROXY=y
++CONFIG_NFT_SYNPROXY=y
++CONFIG_NFT_DUP_NETDEV=y
++CONFIG_NFT_FWD_NETDEV=y
++CONFIG_NFT_FIB_NETDEV=y
++CONFIG_NFT_REJECT_NETDEV=y
++CONFIG_NF_FLOW_TABLE_INET=y
++CONFIG_NF_FLOW_TABLE=y
++CONFIG_IP_SET=y
++CONFIG_IP_SET_BITMAP_IP=y
++CONFIG_IP_SET_BITMAP_IPMAC=y
++CONFIG_IP_SET_BITMAP_PORT=y
++CONFIG_IP_SET_HASH_IP=y
++CONFIG_IP_SET_HASH_IPMARK=y
++CONFIG_IP_SET_HASH_IPPORT=y
++CONFIG_IP_SET_HASH_IPPORTIP=y
++CONFIG_IP_SET_HASH_IPPORTNET=y
++CONFIG_IP_SET_HASH_IPMAC=y
++CONFIG_IP_SET_HASH_MAC=y
++CONFIG_IP_SET_HASH_NETPORTNET=y
++CONFIG_IP_SET_HASH_NET=y
++CONFIG_IP_SET_HASH_NETNET=y
++CONFIG_IP_SET_HASH_NETPORT=y
++CONFIG_IP_SET_HASH_NETIFACE=y
++CONFIG_IP_SET_LIST_SET=y
++CONFIG_NFT_DUP_IPV4=y
++CONFIG_NFT_FIB_IPV4=y
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_IP_NF_ARPTABLES=y
++CONFIG_IP_NF_ARPFILTER=y
++CONFIG_IP_NF_ARP_MANGLE=y
++CONFIG_NFT_DUP_IPV6=y
++CONFIG_NFT_FIB_IPV6=y
++CONFIG_NF_LOG_IPV6=y
++CONFIG_NF_TABLES_BRIDGE=y
++CONFIG_NFT_BRIDGE_META=y
++CONFIG_NFT_BRIDGE_REJECT=y
++CONFIG_NF_CONNTRACK_BRIDGE=y
++CONFIG_IP_SCTP=y
++CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
++CONFIG_SCTP_COOKIE_HMAC_MD5=y
++CONFIG_TIPC=y
++CONFIG_L2TP=y
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=y
++CONFIG_BRIDGE=y
++CONFIG_BRIDGE_VLAN_FILTERING=y
++CONFIG_BRIDGE_MRP=y
++CONFIG_BRIDGE_CFM=y
++CONFIG_VLAN_8021Q=y
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_VLAN_8021Q_MVRP=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_SCH_HFSC=y
++CONFIG_NET_SCH_PRIO=y
++CONFIG_NET_SCH_MULTIQ=y
++CONFIG_NET_SCH_RED=y
++CONFIG_NET_SCH_SFB=y
++CONFIG_NET_SCH_SFQ=y
++CONFIG_NET_SCH_TEQL=y
++CONFIG_NET_SCH_TBF=y
++CONFIG_NET_SCH_CBS=y
++CONFIG_NET_SCH_ETF=y
++CONFIG_NET_SCH_TAPRIO=y
++CONFIG_NET_SCH_GRED=y
++CONFIG_NET_SCH_NETEM=y
++CONFIG_NET_SCH_DRR=y
++CONFIG_NET_SCH_MQPRIO=y
++CONFIG_NET_SCH_CHOKE=y
++CONFIG_NET_SCH_QFQ=y
++CONFIG_NET_SCH_CODEL=y
++CONFIG_NET_SCH_FQ_CODEL=y
++CONFIG_NET_SCH_CAKE=y
++CONFIG_NET_SCH_FQ=y
++CONFIG_NET_SCH_HHF=y
++CONFIG_NET_SCH_PIE=y
++CONFIG_NET_SCH_FQ_PIE=y
++CONFIG_NET_SCH_INGRESS=y
++CONFIG_NET_SCH_ETS=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_U32=y
++CONFIG_CLS_U32_PERF=y
++CONFIG_CLS_U32_MARK=y
++CONFIG_NET_CLS_FLOW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_BPF=y
++CONFIG_NET_CLS_FLOWER=y
++CONFIG_NET_CLS_MATCHALL=y
++CONFIG_NET_EMATCH=y
++CONFIG_NET_EMATCH_CMP=y
++CONFIG_NET_EMATCH_NBYTE=y
++CONFIG_NET_EMATCH_U32=y
++CONFIG_NET_EMATCH_META=y
++CONFIG_NET_EMATCH_TEXT=y
++CONFIG_NET_EMATCH_IPSET=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_GACT_PROB=y
++CONFIG_NETLINK_DIAG=y
++CONFIG_CGROUP_NET_PRIO=y
++CONFIG_BT=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_HS=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIBTUSB=y
++CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_BT_HCIUART_RTL=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_MESH=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_MAC80211_DEBUGFS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_PCI=y
++CONFIG_PCIEPORTBUS=y
++CONFIG_HOTPLUG_PCI_PCIE=y
++CONFIG_PCIEAER=y
++CONFIG_PCIE_DPC=y
++CONFIG_PCIE_PTM=y
++CONFIG_PCI_DEBUG=y
++CONFIG_PCI_REALLOC_ENABLE_AUTO=y
++CONFIG_PCI_STUB=y
++CONFIG_PCI_PF_STUB=y
++CONFIG_PCI_IOV=y
++CONFIG_PCI_PRI=y
++CONFIG_PCI_PASID=y
++CONFIG_HOTPLUG_PCI=y
++CONFIG_PCIE_ROCKCHIP_HOST=y
++CONFIG_PCIE_ROCKCHIP_DW_HOST=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s edid/asus.bin brcm/brcmfmac43456-sdio.bin brcm/brcmfmac43456-sdio.clm_blob brcm/brcmfmac43456-sdio.txt brcm/brcmfmac43456-sdio.pine64,pinebook-pro.txt brcm/BCM4345C5.hcd brcm/brcmfmac43456-sdio.xunlong,orangepi-3.txt anx7688-fw.bin rtl_bt/rtl8723cs_xx_config.bin rtl_bt/rtl8723cs_xx_fw.bin ov5640_af.bin brcm/brcmfmac43455-sdio.bin brcm/brcmfmac43455-sdio.pine64,pinephone-pro.txt brcm/brcmfmac43455-sdio.pine64,pinebook-pro.txt brcm/brcmfmac43455-sdio.clm_blob brcm/BCM4345C0.hcd rockchip/dptx.bin rt2870.bin rtw88/rtw8822c_fw.bin rtw88/rtw8822c_wow_fw.bin rtw89/rtw8852a_fw.bin rtl_nic/rtl8125a-3.fw rtl_nic/rtl8125b-2.fw rtl_nic/rtl8153a-4.fw rtl_nic/rtl8168h-2.fw brcm/brcmfmac43752-pcie.clm_blob brcm/brcmfmac43752-pcie.bin brcm/brcmfmac43752-pcie.txt bes2600/bes2600_factory.txt bes2600/best2002_fw_boot_sdio.bin bes2600/best2002_fw_sdio.bin bes2600/best2002_fw_sdio_btrf.bin bes2600/best2002_fw_sdio_nosignal.bin bes2600/sdd.bin bes2600/factory.bin rtl_bt/rtl8821c_fw.bin rtl_bt/rtl8821c_config.bin rtl_bt/rtl8822b_fw.bin rtl_bt/rtl8822b_config.bin rtw88/rtw8821c_fw.bin rtw88/rtw8822b_fw.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_ARM_SCMI_PROTOCOL=y
++CONFIG_ARM_SCPI_PROTOCOL=y
++CONFIG_GNSS=y
++CONFIG_MTD=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_PARTITIONED_MASTER=y
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_BLK_DEV_NVME=y
++CONFIG_NVME_HWMON=y
++CONFIG_SRAM=y
++CONFIG_PPKB_POWER_MANAGER=y
++CONFIG_MODEM_POWER=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_DWC=y
++# CONFIG_ATA_SFF is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_UEVENT=y
++CONFIG_DM_INTEGRITY=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=y
++CONFIG_TUN=y
++CONFIG_VETH=y
++# CONFIG_NET_VENDOR_ALACRITECH is not set
++# CONFIG_NET_VENDOR_ALLWINNER is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_VENDOR_AQUANTIA is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CADENCE is not set
++# CONFIG_NET_VENDOR_CAVIUM is not set
++# CONFIG_NET_VENDOR_CORTINA is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_GOOGLE is not set
++# CONFIG_NET_VENDOR_HISILICON is not set
++# CONFIG_NET_VENDOR_HUAWEI is not set
++CONFIG_IGB=y
++CONFIG_IGBVF=y
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MELLANOX is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_MICROSEMI is not set
++# CONFIG_NET_VENDOR_NI is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_NET_VENDOR_PENSANDO is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_R8169=y
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SOLARFLARE is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_SOCIONEXT is not set
++CONFIG_STMMAC_ETH=y
++CONFIG_DWMAC_DWC_QOS_ETH=y
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_NET_VENDOR_XILINX is not set
++CONFIG_LED_TRIGGER_PHY=y
++CONFIG_MOTORCOMM_PHY=y
++CONFIG_ROCKCHIP_PHY=y
++CONFIG_MDIO_SUN4I=y
++CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
++CONFIG_PPP=y
++CONFIG_PPP_BSDCOMP=y
++CONFIG_PPP_DEFLATE=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=y
++CONFIG_PPPOE=y
++CONFIG_PPPOL2TP=y
++CONFIG_PPP_ASYNC=y
++CONFIG_PPP_SYNC_TTY=y
++CONFIG_USB_RTL8152=y
++CONFIG_USB_USBNET=y
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=y
++CONFIG_USB_NET_CDC_MBIM=y
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++CONFIG_USB_NET_QMI_WWAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_BRCMFMAC=y
++CONFIG_BRCMFMAC_PCIE=y
++CONFIG_BRCM_TRACING=y
++CONFIG_BRCMDBG=y
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++CONFIG_RT2X00=y
++CONFIG_RT2800USB=y
++# CONFIG_RT2800USB_RT35XX is not set
++CONFIG_RT2800USB_RT53XX=y
++# CONFIG_RTL_CARDS is not set
++CONFIG_RTW88=y
++CONFIG_RTW88_8822BU=y
++CONFIG_RTW88_8822CE=y
++CONFIG_RTW88_8821CU=y
++CONFIG_RTW88_DEBUG=y
++CONFIG_RTW88_DEBUGFS=y
++CONFIG_RTW89=y
++CONFIG_RTW89_8852AE=y
++CONFIG_RTW89_8852CE=y
++# CONFIG_WLAN_VENDOR_RSI is not set
++CONFIG_CW1200=m
++CONFIG_CW1200_WLAN_SDIO=m
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_ADC=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_PINEPHONE=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_GOODIX=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++CONFIG_INPUT_UINPUT=y
++CONFIG_INPUT_RK805_PWRKEY=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_PCI1XXXX=y
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_I2C_RK3X=y
++CONFIG_SPI=y
++CONFIG_SPI_ROCKCHIP=y
++CONFIG_SPI_ROCKCHIP_SFC=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SUN6I=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_PINCTRL_RK805=y
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_SUN50I_H616 is not set
++# CONFIG_PINCTRL_SUN50I_H616_R is not set
++CONFIG_POWER_RESET_GPIO=y
++CONFIG_POWER_RESET_GPIO_RESTART=y
++CONFIG_SYSCON_REBOOT_MODE=y
++CONFIG_NVMEM_REBOOT_MODE=y
++CONFIG_IP5XXX_POWER=y
++CONFIG_BATTERY_CW2015=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++CONFIG_CHARGER_GPIO=y
++CONFIG_CHARGER_RK817=y
++CONFIG_CHARGER_RK818=y
++CONFIG_SENSORS_ARM_SCMI=y
++CONFIG_SENSORS_ARM_SCPI=y
++CONFIG_SENSORS_GPIO_FAN=y
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_DEVFREQ_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_ROCKCHIP_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_DW_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_SSB=y
++CONFIG_SSB_SDIOHOST=y
++CONFIG_SSB_DRIVER_PCICORE=y
++CONFIG_BCMA=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_RK8XX_I2C=y
++CONFIG_MFD_RK8XX_SPI=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_FAN53555=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_RK808=y
++CONFIG_REGULATOR_SY8106A=y
++CONFIG_RC_CORE=y
++CONFIG_BPF_LIRC_MODE2=y
++CONFIG_LIRC=y
++CONFIG_RC_DECODERS=y
++CONFIG_IR_JVC_DECODER=y
++CONFIG_IR_MCE_KBD_DECODER=y
++CONFIG_IR_NEC_DECODER=y
++CONFIG_IR_RC5_DECODER=y
++CONFIG_IR_RC6_DECODER=y
++CONFIG_IR_SANYO_DECODER=y
++CONFIG_IR_SHARP_DECODER=y
++CONFIG_IR_SONY_DECODER=y
++CONFIG_IR_XMP_DECODER=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=y
++CONFIG_IR_SUNXI=y
++CONFIG_MEDIA_CEC_RC=y
++CONFIG_MEDIA_CEC_SUPPORT=y
++CONFIG_MEDIA_SUPPORT=y
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_VIDEO_ADV_DEBUG=y
++CONFIG_V4L2_FLASH_LED_CLASS=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
++CONFIG_VIDEO_ROCKCHIP_RGA=y
++CONFIG_VIDEO_ROCKCHIP_ISP1=y
++CONFIG_VIDEO_SUN6I_CSI=y
++CONFIG_VIDEO_SUN8I_DEINTERLACE=y
++CONFIG_VIDEO_SUN8I_ROTATE=y
++CONFIG_VIDEO_HANTRO=y
++CONFIG_VIDEO_IMX258=y
++CONFIG_VIDEO_OV5640=y
++CONFIG_VIDEO_OV5648=y
++CONFIG_VIDEO_OV8858=y
++CONFIG_VIDEO_GC2145=y
++CONFIG_VIDEO_DW9714=y
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_ROCKCHIP=y
++CONFIG_ROCKCHIP_VOP2=y
++CONFIG_ROCKCHIP_ANALOGIX_DP=y
++CONFIG_ROCKCHIP_CDN_DP=y
++CONFIG_ROCKCHIP_DW_HDMI=y
++CONFIG_ROCKCHIP_DW_MIPI_DSI=y
++CONFIG_ROCKCHIP_INNO_HDMI=y
++CONFIG_ROCKCHIP_LVDS=y
++CONFIG_ROCKCHIP_RGB=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A=y
++CONFIG_DRM_PANEL_SIMPLE=y
++CONFIG_DRM_PANEL_EDP=y
++CONFIG_DRM_PANEL_HIMAX_HX8394=y
++CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
++CONFIG_DRM_PANEL_SITRONIX_ST7703=y
++CONFIG_DRM_DISPLAY_CONNECTOR=y
++CONFIG_DRM_SIMPLE_BRIDGE=y
++CONFIG_DRM_CDNS_DSI=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
++CONFIG_DRM_DW_HDMI_GP_AUDIO=y
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_LIMA=y
++CONFIG_DRM_PANFROST=y
++CONFIG_FB=y
++CONFIG_FB_SIMPLE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
++CONFIG_LOGO=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_HRTIMER=y
++# CONFIG_SND_SPI is not set
++CONFIG_SND_USB_AUDIO=y
++CONFIG_SND_SOC=y
++CONFIG_SND_SOC_ROCKCHIP=y
++CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
++CONFIG_SND_SOC_ROCKCHIP_PDM=y
++CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
++CONFIG_SND_SOC_RK3399_GRU_SOUND=y
++CONFIG_SND_SUN4I_CODEC=y
++CONFIG_SND_SUN8I_CODEC=y
++CONFIG_SND_SUN8I_CODEC_ANALOG=y
++CONFIG_SND_SUN50I_CODEC_ANALOG=y
++CONFIG_SND_SUN4I_I2S=y
++CONFIG_SND_SUN4I_SPDIF=y
++CONFIG_SND_SUN9I_HDMI_AUDIO=y
++CONFIG_SND_SOC_BT_SCO=y
++CONFIG_SND_SOC_EC25=y
++CONFIG_SND_SOC_ES8316=y
++CONFIG_SND_SOC_ES8328_I2C=y
++CONFIG_SND_SOC_RK817=y
++CONFIG_SND_SOC_RT5640=y
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
++CONFIG_SND_SOC_SPDIF=y
++CONFIG_SND_SIMPLE_CARD=y
++CONFIG_SND_AUDIO_GRAPH_CARD=y
++CONFIG_HIDRAW=y
++CONFIG_UHID=y
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_HID_MULTITOUCH=y
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB_ULPI_BUS=y
++CONFIG_USB_CONN_GPIO=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=y
++CONFIG_USB_MON=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=y
++CONFIG_USB_PRINTER=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_UAS=y
++CONFIG_USBIP_CORE=y
++CONFIG_USBIP_VHCI_HCD=y
++CONFIG_USBIP_HOST=y
++CONFIG_USBIP_VUDC=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SUNXI=y
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_DWC3=y
++CONFIG_USB_DWC3_ULPI=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_CONSOLE=y
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_SIMPLE=y
++CONFIG_USB_SERIAL_CH341=y
++CONFIG_USB_SERIAL_CP210X=y
++CONFIG_USB_SERIAL_FTDI_SIO=y
++CONFIG_USB_SERIAL_PL2303=y
++CONFIG_USB_SERIAL_QCAUX=y
++CONFIG_USB_SERIAL_QUALCOMM=y
++CONFIG_USB_SERIAL_OPTION=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_VBUS_DRAW=500
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=y
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_TYPEC_TCPM=y
++CONFIG_TYPEC_TCPCI=y
++CONFIG_TYPEC_HUSB311=y
++CONFIG_TYPEC_FUSB302=y
++CONFIG_TYPEC_UCSI=y
++CONFIG_TYPEC_ANX7688=y
++CONFIG_TYPEC_EXTCON=y
++CONFIG_TYPEC_DP_ALTMODE=y
++CONFIG_MMC=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_OF_ARASAN=y
++CONFIG_MMC_SDHCI_OF_DWCMSHC=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_PWM=y
++CONFIG_LEDS_REGULATOR=y
++CONFIG_LEDS_SGM3140=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=y
++CONFIG_LEDS_TRIGGER_CAMERA=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_HYM8563=y
++CONFIG_RTC_DRV_RK808=y
++CONFIG_RTC_DRV_SUN6I=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_PL330_DMA=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_ROCKCHIP_VDEC=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=y
++CONFIG_RTL8723CS=y
++CONFIG_COMMON_CLK_RK808=y
++CONFIG_COMMON_CLK_SCMI=y
++CONFIG_COMMON_CLK_SCPI=y
++CONFIG_COMMON_CLK_PWM=y
++# CONFIG_CLK_RK3308 is not set
++# CONFIG_CLK_RK3328 is not set
++# CONFIG_CLK_RK3368 is not set
++# CONFIG_SUN50I_A100_CCU is not set
++# CONFIG_SUN50I_A100_R_CCU is not set
++# CONFIG_SUN50I_H616_CCU is not set
++# CONFIG_SUN6I_RTC_CCU is not set
++# CONFIG_FSL_ERRATUM_A008585 is not set
++# CONFIG_HISILICON_ERRATUM_161010101 is not set
++CONFIG_MAILBOX=y
++CONFIG_ROCKCHIP_MBOX=y
++CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
++CONFIG_ROCKCHIP_IOMMU=y
++CONFIG_ARM_SMMU=y
++CONFIG_ARM_SMMU_V3=y
++CONFIG_ROCKCHIP_IODOMAIN=y
++CONFIG_ROCKCHIP_PM_DOMAINS=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_ARM_RK3399_DMC_DEVFREQ=y
++CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
++CONFIG_EXTCON_ADC_JACK=y
++CONFIG_EXTCON_GPIO=y
++CONFIG_EXTCON_USB_GPIO=y
++CONFIG_IIO=y
++CONFIG_IIO_BUFFER_CB=y
++CONFIG_IIO_BUFFER_HW_CONSUMER=y
++CONFIG_IIO_SW_DEVICE=y
++CONFIG_IIO_SW_TRIGGER=y
++CONFIG_IIO_ST_ACCEL_3AXIS=y
++# CONFIG_IIO_ST_ACCEL_SPI_3AXIS is not set
++CONFIG_AXP20X_ADC=y
++CONFIG_ROCKCHIP_SARADC=y
++CONFIG_INV_MPU6050_I2C=y
++CONFIG_STK3310=y
++CONFIG_AF8133J=y
++CONFIG_IIO_ST_MAGN_3AXIS=y
++CONFIG_IIO_HRTIMER_TRIGGER=y
++CONFIG_IIO_INTERRUPT_TRIGGER=y
++CONFIG_IIO_SYSFS_TRIGGER=y
++CONFIG_PWM=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_PHY_SUN50I_USB3=y
++CONFIG_PHY_ROCKCHIP_DP=y
++CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
++CONFIG_PHY_ROCKCHIP_EMMC=y
++CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
++CONFIG_PHY_ROCKCHIP_INNO_USB2=y
++CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
++CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
++CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
++CONFIG_PHY_ROCKCHIP_PCIE=y
++CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
++CONFIG_PHY_ROCKCHIP_TYPEC=y
++CONFIG_PHY_ROCKCHIP_USB=y
++CONFIG_PHY_ROCKCHIP_USBDP=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_ANDROID_BINDER_IPC=y
++CONFIG_ANDROID_BINDERFS=y
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_XFS_FS=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_BTRFS_FS=y
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_OVERLAY_FS=y
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_XINO_AUTO=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_ISO9660_FS=y
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_UTF8=y
++CONFIG_EXFAT_FS=y
++CONFIG_NTFS3_FS=y
++CONFIG_NTFS3_64BIT_CLUSTER=y
++CONFIG_NTFS3_FS_POSIX_ACL=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_INODE64=y
++CONFIG_HUGETLBFS=y
++CONFIG_ECRYPT_FS=y
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V2 is not set
++# CONFIG_NFS_V3 is not set
++CONFIG_NFS_V4=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_2=y
++CONFIG_NFS_FSCACHE=y
++CONFIG_NFSD=y
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y
++CONFIG_CIFS=y
++# CONFIG_CIFS_STATS2 is not set
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++# CONFIG_CIFS_DEBUG is not set
++CONFIG_CIFS_DFS_UPCALL=y
++CONFIG_CIFS_SWN_UPCALL=y
++CONFIG_CIFS_FSCACHE=y
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_BIG_KEYS=y
++CONFIG_TRUSTED_KEYS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_SECURITY=y
++# CONFIG_INTEGRITY is not set
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_ECDSA=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_NHPOLY1305_NEON=y
++CONFIG_CRYPTO_GHASH_ARM64_CE=y
++CONFIG_CRYPTO_SHA1_ARM64_CE=y
++CONFIG_CRYPTO_SHA2_ARM64_CE=y
++CONFIG_CRYPTO_SHA512_ARM64_CE=y
++CONFIG_CRYPTO_SHA3_ARM64=y
++CONFIG_CRYPTO_SM3_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64=y
++CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
++CONFIG_CRYPTO_AES_ARM64_BS=y
++CONFIG_CRYPTO_SM4_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_SS=y
++CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y
++CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
++CONFIG_CRYPTO_DEV_ROCKCHIP=y
++CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++# CONFIG_RAID6_PQ_BENCHMARK is not set
++CONFIG_CORDIC=y
++CONFIG_DMA_CMA=y
++CONFIG_DMA_NUMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_FONT_SUN12x22=y
++CONFIG_FONT_TER16x32=y
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_DEBUG_KERNEL=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_PER_VMA_LOCK_STATS=y
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_SOFTLOCKUP_DETECTOR=y
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
++CONFIG_WQ_WATCHDOG=y
++CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
++# CONFIG_RCU_TRACE is not set
++# CONFIG_FTRACE is not set
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm64/configs/pinephone_defconfig b/arch/arm64/configs/pinephone_defconfig
+new file mode 100644
+index 000000000000..7ac485b54aea
+--- /dev/null
++++ b/arch/arm64/configs/pinephone_defconfig
+@@ -0,0 +1,651 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_BPF_JIT_ALWAYS_ON=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_PREEMPT=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_PSI=y
++CONFIG_LOG_BUF_SHIFT=19
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_GZIP is not set
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++# CONFIG_RD_ZSTD is not set
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_ARM64_ERRATUM_832075 is not set
++# CONFIG_ARM64_ERRATUM_1024718 is not set
++# CONFIG_ARM64_ERRATUM_1418040 is not set
++# CONFIG_ARM64_ERRATUM_1165522 is not set
++# CONFIG_ARM64_ERRATUM_1319367 is not set
++# CONFIG_ARM64_ERRATUM_1530923 is not set
++# CONFIG_ARM64_ERRATUM_1286807 is not set
++# CONFIG_ARM64_ERRATUM_1463225 is not set
++# CONFIG_ARM64_ERRATUM_1542419 is not set
++# CONFIG_ARM64_ERRATUM_2051678 is not set
++# CONFIG_ARM64_ERRATUM_2077057 is not set
++# CONFIG_CAVIUM_ERRATUM_22375 is not set
++# CONFIG_CAVIUM_ERRATUM_23154 is not set
++# CONFIG_CAVIUM_ERRATUM_27456 is not set
++# CONFIG_CAVIUM_ERRATUM_30115 is not set
++# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
++# CONFIG_FUJITSU_ERRATUM_010001 is not set
++# CONFIG_HISILICON_ERRATUM_161600802 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
++# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
++# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
++CONFIG_SCHED_MC=y
++CONFIG_NR_CPUS=4
++CONFIG_HZ_100=y
++CONFIG_COMPAT=y
++# CONFIG_ARM64_HW_AFDBM is not set
++# CONFIG_ARM64_PAN is not set
++# CONFIG_ARM64_USE_LSE_ATOMICS is not set
++# CONFIG_ARM64_RAS_EXTN is not set
++# CONFIG_ARM64_CNP is not set
++# CONFIG_ARM64_PTR_AUTH is not set
++# CONFIG_ARM64_AMU_EXTN is not set
++# CONFIG_ARM64_TLB_RANGE is not set
++# CONFIG_ARM64_BTI is not set
++# CONFIG_ARM64_E0PD is not set
++# CONFIG_ARM64_SVE is not set
++# CONFIG_EFI is not set
++CONFIG_PM_AUTOSLEEP=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_CPU_IDLE_GOV_MENU=y
++CONFIG_CPU_IDLE_GOV_TEO=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=m
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_DIAG is not set
++# CONFIG_IPV6_SIT is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_CONNLIMIT=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_MASQ=m
++CONFIG_NFT_REDIR=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_TUNNEL=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_QUOTA=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_FIB_INET=m
++CONFIG_NFT_SOCKET=m
++CONFIG_NFT_OSF=m
++CONFIG_NFT_DUP_NETDEV=m
++CONFIG_NFT_FWD_NETDEV=m
++CONFIG_NF_FLOW_TABLE_INET=m
++CONFIG_NF_FLOW_TABLE=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPMARK=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_IPMAC=m
++CONFIG_IP_SET_HASH_MAC=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_NFT_FIB_IPV4=m
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=m
++CONFIG_NF_LOG_IPV4=m
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_NFT_DUP_IPV6=m
++CONFIG_NFT_FIB_IPV6=m
++CONFIG_NF_LOG_IPV6=m
++CONFIG_BRIDGE=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_ROUTE4=m
++CONFIG_NET_CLS_FW=m
++CONFIG_NET_CLS_CGROUP=m
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=m
++CONFIG_NET_ACT_GACT=m
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NETLINK_DIAG=m
++CONFIG_BT=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++CONFIG_BT_HS=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_RTL=y
++CONFIG_CFG80211=m
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=m
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=m
++CONFIG_RFKILL_GPIO=m
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s anx7688-fw.bin rtl_bt/rtl8723cs_xx_config.bin rtl_bt/rtl8723cs_xx_fw.bin ov5640_af.bin rtw88/rtw8703b_wow_fw.bin rtw88/rtw8703b_fw.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_ARM_SCPI_PROTOCOL=y
++# CONFIG_ARM_SMCCC_SOC_ID is not set
++CONFIG_ZRAM=m
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_PPKB_POWER_MANAGER=y
++CONFIG_MODEM_POWER=m
++CONFIG_SCSI=m
++CONFIG_BLK_DEV_SD=m
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_UEVENT=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++# CONFIG_ETHERNET is not set
++CONFIG_PPP=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=m
++CONFIG_USB_RTL8152=m
++CONFIG_USB_USBNET=m
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=m
++CONFIG_USB_NET_CDC_MBIM=m
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++CONFIG_USB_NET_QMI_WWAN=m
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_SILABS is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=m
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_PINEPHONE=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_GOODIX=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++CONFIG_INPUT_UINPUT=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_SUN8I_H3_R is not set
++# CONFIG_PINCTRL_SUN50I_H5 is not set
++# CONFIG_PINCTRL_SUN50I_H6 is not set
++# CONFIG_PINCTRL_SUN50I_H6_R is not set
++# CONFIG_PINCTRL_SUN50I_H616 is not set
++# CONFIG_PINCTRL_SUN50I_H616_R is not set
++CONFIG_NVMEM_REBOOT_MODE=y
++CONFIG_IP5XXX_POWER=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_MFD_SYSCON=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_MEDIA_SUPPORT=m
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_V4L2_FLASH_LED_CLASS=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
++CONFIG_VIDEO_SUN6I_CSI=m
++CONFIG_VIDEO_SUN8I_DEINTERLACE=m
++CONFIG_VIDEO_SUN8I_ROTATE=m
++CONFIG_VIDEO_OV5640=m
++CONFIG_VIDEO_GC2145=m
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
++CONFIG_DRM_PANEL_SITRONIX_ST7703=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_LIMA=m
++CONFIG_FB=y
++CONFIG_FB_SIMPLE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_SOUND=m
++CONFIG_SND=m
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=m
++CONFIG_SND_PCM_OSS=m
++CONFIG_SND_HRTIMER=m
++# CONFIG_SND_SUPPORT_OLD_API is not set
++CONFIG_SND_SEQUENCER=m
++CONFIG_SND_SEQ_DUMMY=m
++CONFIG_SND_SEQUENCER_OSS=m
++CONFIG_SND_ALOOP=m
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=m
++CONFIG_SND_SUN4I_CODEC=m
++CONFIG_SND_SUN8I_CODEC=m
++CONFIG_SND_SUN8I_CODEC_ANALOG=m
++CONFIG_SND_SUN50I_CODEC_ANALOG=m
++CONFIG_SND_SUN4I_I2S=m
++CONFIG_SND_SUN4I_SPDIF=m
++CONFIG_SND_SOC_BT_SCO=m
++CONFIG_SND_SOC_EC25=m
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_SND_AUDIO_GRAPH_CARD=m
++CONFIG_HID=m
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=m
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=m
++CONFIG_USB_LEDS_TRIGGER_USBPORT=m
++CONFIG_USB_MON=m
++CONFIG_USB_EHCI_HCD=m
++CONFIG_USB_EHCI_HCD_PLATFORM=m
++CONFIG_USB_OHCI_HCD=m
++CONFIG_USB_OHCI_HCD_PLATFORM=m
++CONFIG_USB_ACM=m
++CONFIG_USB_STORAGE=m
++CONFIG_USB_UAS=m
++CONFIG_USBIP_CORE=m
++CONFIG_USBIP_VHCI_HCD=m
++CONFIG_USBIP_HOST=m
++CONFIG_USBIP_VUDC=m
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_SUNXI=m
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_SIMPLE=m
++CONFIG_USB_SERIAL_CH341=m
++CONFIG_USB_SERIAL_CP210X=m
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_QCAUX=m
++CONFIG_USB_SERIAL_QUALCOMM=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_NOP_USB_XCEIV=m
++CONFIG_USB_GADGET=m
++CONFIG_USB_GADGET_VBUS_DRAW=500
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_AUDIO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_ETH_EEM=y
++CONFIG_USB_G_NCM=m
++CONFIG_USB_GADGETFS=m
++CONFIG_USB_FUNCTIONFS=m
++CONFIG_USB_FUNCTIONFS_ETH=y
++CONFIG_USB_FUNCTIONFS_RNDIS=y
++CONFIG_USB_FUNCTIONFS_GENERIC=y
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_USB_MIDI_GADGET=m
++CONFIG_USB_G_PRINTER=m
++CONFIG_USB_CDC_COMPOSITE=m
++CONFIG_USB_G_ACM_MS=m
++CONFIG_USB_G_MULTI=m
++CONFIG_USB_G_MULTI_CDC=y
++CONFIG_USB_G_HID=m
++CONFIG_USB_G_WEBCAM=m
++CONFIG_USB_RAW_GADGET=m
++CONFIG_TYPEC=y
++CONFIG_TYPEC_ANX7688=y
++CONFIG_TYPEC_DP_ALTMODE=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=y
++CONFIG_LEDS_CLASS_MULTICOLOR=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_SGM3140=m
++CONFIG_LEDS_GROUP_MULTICOLOR=m
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=m
++CONFIG_LEDS_TRIGGER_CAMERA=m
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_SUN6I=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=m
++CONFIG_RTL8723CS=m
++# CONFIG_SUN50I_H6_CCU is not set
++# CONFIG_SUN50I_H616_CCU is not set
++# CONFIG_SUN50I_H6_R_CCU is not set
++# CONFIG_SUN8I_H3_CCU is not set
++# CONFIG_HISILICON_ERRATUM_161010101 is not set
++# CONFIG_ARM64_ERRATUM_858921 is not set
++CONFIG_MAILBOX=y
++CONFIG_IOMMU_IO_PGTABLE_LPAE=y
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=m
++CONFIG_DEVFREQ_GOV_POWERSAVE=m
++CONFIG_DEVFREQ_GOV_USERSPACE=m
++CONFIG_DEVFREQ_GOV_PASSIVE=m
++CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_BUFFER_CB=m
++CONFIG_IIO_BUFFER_HW_CONSUMER=m
++CONFIG_IIO_SW_DEVICE=m
++CONFIG_IIO_SW_TRIGGER=m
++CONFIG_AXP20X_ADC=y
++CONFIG_INV_MPU6050_I2C=m
++CONFIG_STK3310=m
++CONFIG_AF8133J=m
++CONFIG_IIO_ST_MAGN_3AXIS=m
++CONFIG_IIO_HRTIMER_TRIGGER=m
++CONFIG_IIO_INTERRUPT_TRIGGER=m
++CONFIG_IIO_SYSFS_TRIGGER=m
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_ANDROID_BINDER_IPC=y
++CONFIG_ANDROID_BINDERFS=y
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_BTRFS_FS=y
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_NILFS2_FS=m
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=m
++CONFIG_FUSE_FS=m
++CONFIG_CUSE=m
++CONFIG_OVERLAY_FS=m
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_VFAT_FS=y
++CONFIG_EXFAT_FS=m
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_ECRYPT_FS=m
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=m
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_USER=m
++CONFIG_CRYPTO_PCRYPT=m
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_CURVE25519=m
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_ARC4=m
++CONFIG_CRYPTO_CHACHA20POLY1305=m
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++CONFIG_CRYPTO_MD4=m
++CONFIG_CRYPTO_SHA1=y
++CONFIG_CRYPTO_SHA3=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=m
++CONFIG_CRYPTO_USER_API_HASH=m
++CONFIG_CRYPTO_USER_API_SKCIPHER=m
++CONFIG_CRYPTO_USER_API_RNG=m
++CONFIG_CRYPTO_USER_API_AEAD=m
++CONFIG_CRYPTO_GHASH_ARM64_CE=m
++CONFIG_CRYPTO_SHA1_ARM64_CE=m
++CONFIG_CRYPTO_SHA2_ARM64_CE=m
++CONFIG_CRYPTO_SHA512_ARM64_CE=m
++CONFIG_CRYPTO_SHA3_ARM64=m
++CONFIG_CRYPTO_SM3_ARM64_CE=m
++CONFIG_CRYPTO_AES_ARM64=m
++CONFIG_CRYPTO_AES_ARM64_CE_BLK=m
++CONFIG_CRYPTO_AES_ARM64_BS=m
++CONFIG_CRYPTO_SM4_ARM64_CE=m
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=m
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
++CONFIG_CRYPTO_DEV_SUN8I_CE=m
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
++# CONFIG_RAID6_PQ_BENCHMARK is not set
++CONFIG_CRC_T10DIF=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++CONFIG_PER_VMA_LOCK_STATS=y
++CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
++CONFIG_FTRACE=y
++CONFIG_BOOTTIME_TRACING=y
++CONFIG_FUNCTION_TRACER=y
++CONFIG_FTRACE_SYSCALLS=y
++CONFIG_TRACER_SNAPSHOT=y
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm64/configs/pinephone_multidist_defconfig b/arch/arm64/configs/pinephone_multidist_defconfig
+new file mode 100644
+index 000000000000..92b9119238c0
+--- /dev/null
++++ b/arch/arm64/configs/pinephone_multidist_defconfig
+@@ -0,0 +1,602 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_BPF_JIT_ALWAYS_ON=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_PSI=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_BPF=y
++CONFIG_NAMESPACES=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_GZIP is not set
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++# CONFIG_RD_ZSTD is not set
++CONFIG_EXPERT=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_ARM64_ERRATUM_832075 is not set
++# CONFIG_ARM64_ERRATUM_1024718 is not set
++# CONFIG_ARM64_ERRATUM_1418040 is not set
++# CONFIG_ARM64_ERRATUM_1165522 is not set
++# CONFIG_ARM64_ERRATUM_1319367 is not set
++# CONFIG_ARM64_ERRATUM_1530923 is not set
++# CONFIG_ARM64_ERRATUM_1286807 is not set
++# CONFIG_ARM64_ERRATUM_1463225 is not set
++# CONFIG_ARM64_ERRATUM_1542419 is not set
++# CONFIG_ARM64_ERRATUM_2051678 is not set
++# CONFIG_ARM64_ERRATUM_2077057 is not set
++# CONFIG_CAVIUM_ERRATUM_22375 is not set
++# CONFIG_CAVIUM_ERRATUM_23154 is not set
++# CONFIG_CAVIUM_ERRATUM_27456 is not set
++# CONFIG_CAVIUM_ERRATUM_30115 is not set
++# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
++# CONFIG_FUJITSU_ERRATUM_010001 is not set
++# CONFIG_HISILICON_ERRATUM_161600802 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
++# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
++# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
++CONFIG_SCHED_MC=y
++CONFIG_NR_CPUS=4
++CONFIG_COMPAT=y
++# CONFIG_ARM64_HW_AFDBM is not set
++# CONFIG_ARM64_PAN is not set
++# CONFIG_ARM64_USE_LSE_ATOMICS is not set
++# CONFIG_ARM64_RAS_EXTN is not set
++# CONFIG_ARM64_CNP is not set
++# CONFIG_ARM64_PTR_AUTH is not set
++# CONFIG_ARM64_AMU_EXTN is not set
++# CONFIG_ARM64_TLB_RANGE is not set
++# CONFIG_ARM64_BTI is not set
++# CONFIG_ARM64_E0PD is not set
++# CONFIG_ARM64_SVE is not set
++# CONFIG_EFI is not set
++CONFIG_PM_AUTOSLEEP=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_DIAG is not set
++# CONFIG_IPV6_SIT is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=y
++CONFIG_NF_CONNTRACK_H323=y
++CONFIG_NF_CONNTRACK_IRC=y
++CONFIG_NF_CONNTRACK_NETBIOS_NS=y
++CONFIG_NF_CONNTRACK_SNMP=y
++CONFIG_NF_CONNTRACK_PPTP=y
++CONFIG_NF_CONNTRACK_SIP=y
++CONFIG_NF_CONNTRACK_TFTP=y
++CONFIG_NF_CT_NETLINK=y
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=y
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=y
++CONFIG_NFT_CT=y
++CONFIG_NFT_CONNLIMIT=y
++CONFIG_NFT_LOG=y
++CONFIG_NFT_LIMIT=y
++CONFIG_NFT_MASQ=y
++CONFIG_NFT_REDIR=y
++CONFIG_NFT_NAT=y
++CONFIG_NFT_TUNNEL=y
++CONFIG_NFT_QUEUE=y
++CONFIG_NFT_QUOTA=y
++CONFIG_NFT_REJECT=y
++CONFIG_NFT_HASH=y
++CONFIG_NFT_FIB_INET=y
++CONFIG_NFT_SOCKET=y
++CONFIG_NFT_OSF=y
++CONFIG_NFT_DUP_NETDEV=y
++CONFIG_NFT_FWD_NETDEV=y
++CONFIG_NF_FLOW_TABLE_INET=y
++CONFIG_NF_FLOW_TABLE=y
++CONFIG_IP_SET=y
++CONFIG_IP_SET_BITMAP_IP=y
++CONFIG_IP_SET_BITMAP_IPMAC=y
++CONFIG_IP_SET_BITMAP_PORT=y
++CONFIG_IP_SET_HASH_IP=y
++CONFIG_IP_SET_HASH_IPMARK=y
++CONFIG_IP_SET_HASH_IPPORT=y
++CONFIG_IP_SET_HASH_IPPORTIP=y
++CONFIG_IP_SET_HASH_IPPORTNET=y
++CONFIG_IP_SET_HASH_IPMAC=y
++CONFIG_IP_SET_HASH_MAC=y
++CONFIG_IP_SET_HASH_NETPORTNET=y
++CONFIG_IP_SET_HASH_NET=y
++CONFIG_IP_SET_HASH_NETNET=y
++CONFIG_IP_SET_HASH_NETPORT=y
++CONFIG_IP_SET_HASH_NETIFACE=y
++CONFIG_IP_SET_LIST_SET=y
++CONFIG_NFT_FIB_IPV4=y
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_NFT_DUP_IPV6=y
++CONFIG_NFT_FIB_IPV6=y
++CONFIG_NF_LOG_IPV6=y
++CONFIG_BRIDGE=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_NET_ACT_MIRRED=y
++CONFIG_NETLINK_DIAG=y
++CONFIG_BT=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_HS=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_RTL=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s anx7688-fw.bin rtl_bt/rtl8723cs_xx_config.bin rtl_bt/rtl8723cs_xx_fw.bin ov5640_af.bin rtw88/rtw8703b_wow_fw.bin rtw88/rtw8703b_fw.bin"
++CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_ARM_SCPI_PROTOCOL=y
++# CONFIG_ARM_SMCCC_SOC_ID is not set
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_PPKB_POWER_MANAGER=y
++CONFIG_MODEM_POWER=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_UEVENT=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=y
++CONFIG_TUN=y
++CONFIG_VETH=y
++# CONFIG_ETHERNET is not set
++CONFIG_PPP=y
++CONFIG_PPP_BSDCOMP=y
++CONFIG_PPP_DEFLATE=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=y
++CONFIG_USB_RTL8152=y
++CONFIG_USB_USBNET=y
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=y
++CONFIG_USB_NET_CDC_MBIM=y
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++CONFIG_USB_NET_QMI_WWAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_RTL_CARDS is not set
++CONFIG_RTW88=m
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_SILABS is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_PINEPHONE=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_GOODIX=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++CONFIG_INPUT_UINPUT=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_SUN8I_H3_R is not set
++# CONFIG_PINCTRL_SUN50I_H5 is not set
++# CONFIG_PINCTRL_SUN50I_H6 is not set
++# CONFIG_PINCTRL_SUN50I_H6_R is not set
++# CONFIG_PINCTRL_SUN50I_H616 is not set
++# CONFIG_PINCTRL_SUN50I_H616_R is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_NVMEM_REBOOT_MODE=y
++CONFIG_IP5XXX_POWER=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_MFD_SYSCON=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_SUPPORT_FILTER=y
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_V4L2_FLASH_LED_CLASS=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
++CONFIG_VIDEO_SUN6I_CSI=y
++CONFIG_VIDEO_SUN8I_DEINTERLACE=y
++CONFIG_VIDEO_SUN8I_ROTATE=y
++CONFIG_VIDEO_OV5640=y
++CONFIG_VIDEO_GC2145=y
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
++CONFIG_DRM_PANEL_SITRONIX_ST7703=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_LIMA=y
++CONFIG_FB=y
++CONFIG_FB_SIMPLE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_HRTIMER=y
++# CONFIG_SND_SUPPORT_OLD_API is not set
++# CONFIG_SND_DRIVERS is not set
++CONFIG_SND_USB_AUDIO=y
++CONFIG_SND_SOC=y
++CONFIG_SND_SUN4I_CODEC=y
++CONFIG_SND_SUN8I_CODEC=y
++CONFIG_SND_SUN8I_CODEC_ANALOG=y
++CONFIG_SND_SUN50I_CODEC_ANALOG=y
++CONFIG_SND_SUN4I_I2S=y
++CONFIG_SND_SUN4I_SPDIF=y
++CONFIG_SND_SUN9I_HDMI_AUDIO=y
++CONFIG_SND_SOC_BT_SCO=y
++CONFIG_SND_SOC_EC25=y
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
++CONFIG_SND_SIMPLE_CARD=y
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=y
++CONFIG_USB_MON=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_UAS=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SUNXI=y
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_CONSOLE=y
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_SIMPLE=y
++CONFIG_USB_SERIAL_CH341=y
++CONFIG_USB_SERIAL_CP210X=y
++CONFIG_USB_SERIAL_FTDI_SIO=y
++CONFIG_USB_SERIAL_QCAUX=y
++CONFIG_USB_SERIAL_OPTION=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_VBUS_DRAW=500
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=y
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_TYPEC=y
++CONFIG_TYPEC_TCPM=y
++CONFIG_TYPEC_TCPCI=y
++CONFIG_TYPEC_UCSI=y
++CONFIG_TYPEC_ANX7688=y
++CONFIG_TYPEC_DP_ALTMODE=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_SGM3140=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=y
++CONFIG_LEDS_TRIGGER_CAMERA=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_SUN6I=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=y
++CONFIG_RTL8723CS=m
++# CONFIG_SUN50I_H6_CCU is not set
++# CONFIG_SUN50I_H616_CCU is not set
++# CONFIG_SUN50I_H6_R_CCU is not set
++# CONFIG_SUN8I_H3_CCU is not set
++# CONFIG_HISILICON_ERRATUM_161010101 is not set
++# CONFIG_ARM64_ERRATUM_858921 is not set
++CONFIG_MAILBOX=y
++CONFIG_IOMMU_IO_PGTABLE_LPAE=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_BUFFER_CB=y
++CONFIG_IIO_BUFFER_HW_CONSUMER=y
++CONFIG_IIO_SW_DEVICE=y
++CONFIG_IIO_SW_TRIGGER=y
++CONFIG_AXP20X_ADC=y
++CONFIG_INV_MPU6050_I2C=y
++CONFIG_STK3310=y
++CONFIG_AF8133J=y
++CONFIG_IIO_ST_MAGN_3AXIS=y
++CONFIG_IIO_HRTIMER_TRIGGER=y
++CONFIG_IIO_INTERRUPT_TRIGGER=y
++CONFIG_IIO_SYSFS_TRIGGER=y
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_ANDROID_BINDER_IPC=y
++CONFIG_ANDROID_BINDERFS=y
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_BTRFS_FS=y
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_OVERLAY_FS=y
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_VFAT_FS=y
++CONFIG_EXFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_ECRYPT_FS=y
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_BIG_KEYS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_GHASH_ARM64_CE=y
++CONFIG_CRYPTO_SHA1_ARM64_CE=y
++CONFIG_CRYPTO_SHA2_ARM64_CE=y
++CONFIG_CRYPTO_SHA512_ARM64_CE=y
++CONFIG_CRYPTO_SHA3_ARM64=y
++CONFIG_CRYPTO_SM3_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64=y
++CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
++CONFIG_CRYPTO_AES_ARM64_BS=y
++CONFIG_CRYPTO_SM4_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++# CONFIG_RAID6_PQ_BENCHMARK is not set
++CONFIG_CRC_T10DIF=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++# CONFIG_SLUB_DEBUG is not set
++CONFIG_PER_VMA_LOCK_STATS=y
++CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
++CONFIG_BOOTTIME_TRACING=y
++CONFIG_FUNCTION_TRACER=y
++CONFIG_FTRACE_SYSCALLS=y
++CONFIG_TRACER_SNAPSHOT=y
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/Fix-intptr_t-typedef.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/Fix-intptr_t-typedef.patch
new file mode 100644
index 000000000000..05f72af6b818
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/Fix-intptr_t-typedef.patch
@@ -0,0 +1,32 @@
+From a95b18c4d97a1da27180ff0ed6c127dd1a8200e0 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 26 Aug 2023 10:55:24 +0200
+Subject: Fix intptr_t typedef
+
+GCC includes the same typedef, but on some 32bit platforms it's defined
+as int, leading to conflicts.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ include/linux/types.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/include/linux/types.h b/include/linux/types.h
+index 2bc8766ba20c..246d8b89d76a 100644
+--- a/include/linux/types.h
++++ b/include/linux/types.h
+@@ -40,7 +40,11 @@ typedef __kernel_uid16_t        uid16_t;
+ typedef __kernel_gid16_t        gid16_t;
+ 
+ typedef unsigned long		uintptr_t;
++#if __SIZEOF_POINTER__ == __SIZEOF_INT__
++typedef int			intptr_t;
++#else
+ typedef long			intptr_t;
++#endif
+ 
+ #ifdef CONFIG_HAVE_UID16
+ /* This is defined by include/asm-{arch}/posix_types.h */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
new file mode 100644
index 000000000000..a9fcf16f094a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
@@ -0,0 +1,30 @@
+From 4c2d93648b4282e7176adc8d4a457f01b9397d62 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 30 Sep 2017 21:31:35 +0200
+Subject: MAINTAINERS: Add entry for Himax HM5065
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ MAINTAINERS | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 3121709d99e3..34cecf6b6264 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -9679,6 +9679,12 @@ L:	linux-kernel@vger.kernel.org
+ S:	Maintained
+ F:	drivers/misc/hisi_hikey_usb.c
+ 
++HIMAX HM5065 SENSOR DRIVER
++M:	Ondrej Jirman <kernel@xff.cz>
++L:	linux-media@vger.kernel.org
++S:	Supported
++F:	drivers/media/i2c/hm5065.c
++
+ HIMAX HX83112B TOUCHSCREEN SUPPORT
+ M:	Job Noorman <job@noorman.info>
+ L:	linux-input@vger.kernel.org
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
new file mode 100644
index 000000000000..4e9986b0504c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
@@ -0,0 +1,39 @@
+From beb48b480b89331954be7c3becb0e83a28d63c11 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 18 Aug 2017 13:55:48 +0200
+Subject: Make microbuttons on Orange Pi PC and PC 2 work as power off buttons
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts    | 2 +-
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index 59f6f6d5e7ca..a42fd9550cfd 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -91,7 +91,7 @@ gpio-keys {
+ 
+ 		switch-4 {
+ 			label = "sw4";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ 		};
+ 	};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+index ce3ae19e72db..2aadc3d0a23e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -60,7 +60,7 @@ gpio-keys {
+ 
+ 		key-sw4 {
+ 			label = "sw4";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ 			wakeup-source;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
new file mode 100644
index 000000000000..2467aff36a25
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
@@ -0,0 +1,40 @@
+From 74fa407268d0e4e3cdfb2bcbcd54d378402b0222 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 10 Feb 2020 01:00:12 +0100
+Subject: Mark some slow drivers for async probe with PROBE_PREFER_ASYNCHRONOUS
+
+This makes it faster to boot TBS A711 tablet.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/iio/accel/bma180.c | 1 +
+ drivers/nfc/nxp-nci/i2c.c  | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c
+index 6581772cb0c4..88e796a67324 100644
+--- a/drivers/iio/accel/bma180.c
++++ b/drivers/iio/accel/bma180.c
+@@ -1127,6 +1127,7 @@ static struct i2c_driver bma180_driver = {
+ 		.name	= "bma180",
+ 		.pm	= pm_sleep_ptr(&bma180_pm_ops),
+ 		.of_match_table = bma180_of_match,
++		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ 	},
+ 	.probe		= bma180_probe,
+ 	.remove		= bma180_remove,
+diff --git a/drivers/nfc/nxp-nci/i2c.c b/drivers/nfc/nxp-nci/i2c.c
+index 3ae4b41c59ac..34c4e38cdf8a 100644
+--- a/drivers/nfc/nxp-nci/i2c.c
++++ b/drivers/nfc/nxp-nci/i2c.c
+@@ -348,6 +348,7 @@ static struct i2c_driver nxp_nci_i2c_driver = {
+ 		   .name = NXP_NCI_I2C_DRIVER_NAME,
+ 		   .acpi_match_table = ACPI_PTR(acpi_id),
+ 		   .of_match_table = of_nxp_nci_i2c_match,
++		   .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ 		  },
+ 	.probe = nxp_nci_i2c_probe,
+ 	.id_table = nxp_nci_i2c_id_table,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/Move-a-node-to-avoid-merge-conflict.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/Move-a-node-to-avoid-merge-conflict.patch
new file mode 100644
index 000000000000..a1917afed850
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/Move-a-node-to-avoid-merge-conflict.patch
@@ -0,0 +1,115 @@
+From a1aa2e3fe0c7cdc9cf16bb90303cb2dcf7c8ff49 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 9 May 2021 23:43:21 +0200
+Subject: Move a node to avoid merge conflict
+
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi  | 12 ++++-----
+ .../dts/allwinner/sun50i-h6-orangepi-3.dts    |  8 +++---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 27 +++++++++----------
+ 3 files changed, 23 insertions(+), 24 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 3c0da94661c9..699ab2f7a1ac 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -100,12 +100,6 @@ osc32k: osc32k_clk {
+ 		};
+ 	};
+ 
+-	de: display-engine {
+-		compatible = "allwinner,sun8i-h3-display-engine";
+-		allwinner,pipelines = <&mixer0>;
+-		status = "disabled";
+-	};
+-
+ 	sound_hdmi: sound_hdmi {
+ 		compatible = "allwinner,sun9i-a80-hdmi-audio",
+ 			     "allwinner,sun8i-h3-hdmi-audio";
+@@ -120,6 +114,12 @@ cpu {
+ 		};
+ 	};
+ 
++	de: display-engine {
++		compatible = "allwinner,sun8i-h3-display-engine";
++		allwinner,pipelines = <&mixer0>;
++		status = "disabled";
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index ead12d861e12..218c26c59429 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -128,6 +128,10 @@ &gpu {
+ 	status = "okay";
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &hdmi {
+ 	status = "okay";
+ };
+@@ -167,10 +171,6 @@ ext_rgmii_phy: ethernet-phy@1 {
+ 	};
+ };
+ 
+-&i2s1 {
+-	status = "okay";
+-};
+-
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 8b2e96838f9d..ea99a7727872 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -89,20 +89,6 @@ psci {
+ 		method = "smc";
+ 	};
+ 
+-	sound_hdmi: sound_hdmi {
+-		compatible = "allwinner,sun9i-a80-hdmi-audio",
+-			     "allwinner,sun50i-h6-hdmi-audio";
+-		status = "disabled";
+-
+-		codec {
+-			sound-dai = <&hdmi>;
+-		};
+-
+-		cpu {
+-			sound-dai = <&i2s1>;
+-		};
+-	};
+-
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -116,6 +102,19 @@ timer {
+ 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun50i-h6-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s1>;
++		};
++	};
+ 
+ 	soc {
+ 		compatible = "simple-bus";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/Revert-clk-qcom-Support-protected-clocks-property.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/Revert-clk-qcom-Support-protected-clocks-property.patch
new file mode 100644
index 000000000000..bce1081753cc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/Revert-clk-qcom-Support-protected-clocks-property.patch
@@ -0,0 +1,54 @@
+From a8a50107fe9f8d50433398e449bcd5e061486c82 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 30 Dec 2019 12:39:31 -0600
+Subject: Revert "clk: qcom: Support 'protected-clocks' property"
+
+Now that protected-clocks is handled in the clk core, this
+driver-specific implementation is redundant.
+
+This reverts commit b181b3b801da8893c8eb706e448dd5111b02de60.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/qcom/common.c | 18 ------------------
+ 1 file changed, 18 deletions(-)
+
+diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
+index 75f09e6e057e..8e94e425eb2f 100644
+--- a/drivers/clk/qcom/common.c
++++ b/drivers/clk/qcom/common.c
+@@ -204,22 +204,6 @@ int qcom_cc_register_sleep_clk(struct device *dev)
+ }
+ EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
+ 
+-/* Drop 'protected-clocks' from the list of clocks to register */
+-static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
+-{
+-	struct device_node *np = dev->of_node;
+-	struct property *prop;
+-	const __be32 *p;
+-	u32 i;
+-
+-	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
+-		if (i >= cc->num_rclks)
+-			continue;
+-
+-		cc->rclks[i] = NULL;
+-	}
+-}
+-
+ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
+ 					 void *data)
+ {
+@@ -282,8 +266,6 @@ int qcom_cc_really_probe(struct platform_device *pdev,
+ 	cc->rclks = rclks;
+ 	cc->num_rclks = num_clks;
+ 
+-	qcom_cc_drop_protected(dev, cc);
+-
+ 	for (i = 0; i < num_clk_hws; i++) {
+ 		ret = devm_clk_hw_register(dev, clk_hws[i]);
+ 		if (ret)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
new file mode 100644
index 000000000000..ce104d84ed87
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
@@ -0,0 +1,28 @@
+From ecbbb9001d35657b656715344408d1e034f78a97 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 1 Nov 2020 02:57:38 +0100
+Subject: Revert "drm/sun4i: lvds: Invert the LVDS polarity"
+
+This reverts commit 3bc46a083fa9f475dd2e0ab8717d9839b070b8d9.
+---
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index a1a2c845ade0..b78799dedf62 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -476,7 +476,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
+ 		     SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
+ 		     SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
+ 
+-	reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0;
++	reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
++		SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
++		SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
+ 	if (sun4i_tcon_get_pixel_depth(encoder) == 24)
+ 		reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
+ 	else
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
new file mode 100644
index 000000000000..faa673a4eb6d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
@@ -0,0 +1,43 @@
+From 08b6bf51b8846548f951ced5a7553cffc334c642 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 7 May 2024 18:39:12 +0200
+Subject: Revert "usb: typec: tcpm: unregister existing source caps before
+ re-registration"
+
+This reverts commits:
+    230ecdf71a644c9c73e0e6735b33173074ae3f94  linux-6.9.y
+    6b67b652849faf108a09647c7fde9b179ef24e2b  linux-6.9.y
+
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index 5d4da962acc8..338426258539 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -3004,7 +3004,7 @@ static int tcpm_register_source_caps(struct tcpm_port *port)
+ {
+ 	struct usb_power_delivery_desc desc = { port->negotiated_rev };
+ 	struct usb_power_delivery_capabilities_desc caps = { };
+-	struct usb_power_delivery_capabilities *cap = port->partner_source_caps;
++	struct usb_power_delivery_capabilities *cap;
+ 
+ 	if (!port->partner_pd)
+ 		port->partner_pd = usb_power_delivery_register(NULL, &desc);
+@@ -3014,11 +3014,6 @@ static int tcpm_register_source_caps(struct tcpm_port *port)
+ 	memcpy(caps.pdo, port->source_caps, sizeof(u32) * port->nr_source_caps);
+ 	caps.role = TYPEC_SOURCE;
+ 
+-	if (cap) {
+-		usb_power_delivery_unregister_capabilities(cap);
+-		port->partner_source_caps = NULL;
+-	}
+-
+ 	cap = usb_power_delivery_register_capabilities(port->partner_pd, &caps);
+ 	if (IS_ERR(cap))
+ 		return PTR_ERR(cap);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
new file mode 100644
index 000000000000..b15d836df9e4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
@@ -0,0 +1,35 @@
+From 17af15c0ced87a831d53bdf8b36a2f3ed0accbe0 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Mon, 20 Jul 2020 01:11:34 +0800
+Subject: arm64: allwinner: dts: a64: enable K101-IM2BYL02 panel for PineTab
+
+Newer PineTab may switch to K101-IM2BYL02.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 6e6ade916dcc..5d8081a093b6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -200,12 +200,10 @@ &dsi {
+ 	status = "okay";
+ 
+ 	panel@0 {
+-		compatible = "feixin,k101-im2ba02";
++		compatible = "feixin,k101-im2byl02";
+ 		reg = <0>;
+-		avdd-supply = <&reg_dc1sw>;
+-		dvdd-supply = <&reg_dc1sw>;
+-		cvdd-supply = <&reg_ldo_io1>;
+-		reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
++		power-supply = <&reg_dc1sw>;
++		reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+ 		backlight = <&backlight>;
+ 	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
new file mode 100644
index 000000000000..255cb53fc054
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
@@ -0,0 +1,66 @@
+From a38f0fde96333d63aa6acc6b282c20d1e655ec6a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 6 Dec 2020 11:15:34 -0600
+Subject: arm64: dts: allwinner: Enforce consistent MMC numbering
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 ++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  | 6 ++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 6 ++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 952a1883e0dc..0bd19550427c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -18,6 +18,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	chosen {
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index 2edb96f0f0c9..7edd3be7e180 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -6,6 +6,12 @@
+ #include <dt-bindings/thermal/thermal.h>
+ 
+ / {
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index d11e5041bae9..6e6e355e24a0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -17,6 +17,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Add-SCPI-protocol.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..d6045e82e2f7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Add-SCPI-protocol.patch
@@ -0,0 +1,51 @@
+From 6827b831d034a292e859a038d04394e1e4351cc1 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 14 Dec 2019 20:52:53 -0600
+Subject: arm64: dts: allwinner: a64: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 2f9c8db0c0d5..de04e4e50542 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -148,6 +148,13 @@ psci {
+ 		method = "smc";
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	sound: sound {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -376,6 +383,19 @@ syscon: syscon@1c00000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0x14000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0x14000>;
++
++				scpi_sram: scp-shmem@13c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x13c00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@18000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00018000 0x28000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..ad33ac882a14
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From 1cc63e19ef4881a5de63d8bbc8face5c9e76c3fc Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 10:39:56 +0200
+Subject: arm64: dts: allwinner: a64: Add hdmi sound card
+
+A64 supports HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 57ac18738c99..5610e1364ba1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -177,6 +177,20 @@ link0_codec: codec {
+ 		};
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun50i-a64-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		allwinner,erratum-unknown1;
+@@ -1224,6 +1238,7 @@ deinterlace: deinterlace@1e00000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-a64-dw-hdmi",
+ 				     "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
new file mode 100644
index 000000000000..ac7187eecd35
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
@@ -0,0 +1,204 @@
+From d5b36ab71164d6219c7e6a050ac2feb39eee1a89 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 10:42:16 +0200
+Subject: arm64: dts: allwinner: a64: Enable hdmi sound card on boards with
+ hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all A64 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts   | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts    | 7 +++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts       | 8 ++++++++
+ .../boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts    | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts      | 8 ++++++++
+ 7 files changed, 55 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+index e6d5bc0f7a61..a0c78d00e202 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+@@ -130,6 +130,10 @@ &i2c1_pins {
+ 	bias-pull-up;
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -341,6 +345,10 @@ &sound {
+ 			"MIC1", "Onboard Microphone";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+index 0af6dcdf7515..6239d2c435c8 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+@@ -102,6 +102,10 @@ &i2c1_pins {
+ 	bias-pull-up;
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -252,6 +256,10 @@ &simplefb_hdmi {
+ 	vcc-hdmi-supply = <&reg_dldo1>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+index bfb806cf6d7a..21d0bdc28766 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+@@ -120,6 +120,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -355,6 +359,9 @@ &sound {
+ 		    "MIC1", "Microphone Jack Left",
+ 		    "Microphone Jack Right", "MBIAS",
+ 		    "MIC2", "Microphone Jack Right";
++};
++
++&sound_hdmi {
+ 	status = "okay";
+ };
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+index 4f8529d5ac00..306ce4acf967 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+@@ -137,6 +137,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -340,6 +344,10 @@ &sound {
+ 			"MIC1", "Onboard Microphone";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spi0 {
+ 	status = "okay";
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index 2accb5ddf783..17886709b6b4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -107,6 +107,10 @@ &i2c1_pins {
+ 	bias-pull-up;
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rmii_phy1: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -270,6 +274,10 @@ &sound {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ /* On Euler connector */
+ &spdif {
+ 	status = "disabled";
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+index 5e66ce1a334f..970d528378db 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -96,6 +96,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -169,6 +173,10 @@ &sound {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
+index 1128030e4c25..061e4d9afcc9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
+@@ -150,6 +150,10 @@ anx6345_in: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mixer0 {
+ 	status = "okay";
+ };
+@@ -366,6 +370,10 @@ &sound {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &tcon0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&lcd_rgb666_pins>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
new file mode 100644
index 000000000000..178ca8d2d073
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
@@ -0,0 +1,32 @@
+From e852b63d9e2cdabd2093673da73006f7f2dec9d0 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Sun, 30 Jun 2019 22:45:34 +0800
+Subject: arm64: dts: allwinner: a64: Fix LRADC compatible
+
+The LRADC reference voltage of A64 is 2.0V, and AVCC is 3.0V. So the
+internal voltage divider is 2/3 (the A10 value), not 3/4 (the A83T
+value).
+
+Fix the compatible string of the A64 LRADC.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index fd24ae4713e6..5b3ed3c903d9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -923,7 +923,7 @@ spdif: spdif@1c21000 {
+ 
+ 		lradc: lradc@1c21800 {
+ 			compatible = "allwinner,sun50i-a64-lradc",
+-				     "allwinner,sun8i-a83t-r-lradc";
++				     "allwinner,sun4i-a10-lradc-keys";
+ 			reg = <0x01c21800 0x400>;
+ 			interrupt-parent = <&r_intc>;
+ 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Protect-SCP-clocks.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Protect-SCP-clocks.patch
new file mode 100644
index 000000000000..77619b9cac8e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-Protect-SCP-clocks.patch
@@ -0,0 +1,33 @@
+From 9a641e75a7ac802c7f9b7d3d29af2f48e319682b Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 30 Dec 2019 15:10:32 -0600
+Subject: arm64: dts: allwinner: a64: Protect SCP clocks
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index fbc17e247b1e..2f9c8db0c0d5 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -678,6 +678,7 @@ ccu: clock@1c20000 {
+ 			reg = <0x01c20000 0x400>;
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
+ 			clock-names = "hosc", "losc";
++			protected-clocks = <CLK_BUS_MSGBOX>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+@@ -1314,6 +1315,7 @@ r_ccu: clock@1f01400 {
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
+ 				 <&ccu CLK_PLL_PERIPH0>;
+ 			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			protected-clocks = <CLK_APB0_TWD>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
new file mode 100644
index 000000000000..19d3273322da
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
@@ -0,0 +1,99 @@
+From 25c54eb1ee45b7e066e66f5c9ba5147015ed59ec Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 17 Nov 2020 01:06:30 +0100
+Subject: arm64: dts: allwinner: a64: pinetab: add front camera
+
+---
+ .../boot/dts/allwinner/sun50i-a64-pinetab.dts | 50 ++++++++++++++++---
+ 1 file changed, 44 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 0a5607f73049..6e6ade916dcc 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -55,12 +55,35 @@ i2c-csi {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
++		/* Front camera */
++		gc2145: front-camera@3c {
++			compatible = "galaxycore,gc2145";
++			reg = <0x3c>;
++			clocks = <&ccu CLK_CSI_MCLK>;
++			clock-names = "xclk";
++
++			AVDD-supply = <&reg_dldo3>;
++			DVDD-supply = <&reg_aldo1>;
++			IOVDD-supply = <&reg_eldo3>;
++			reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
++			enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
++
++			port {
++				gc2145_ep: endpoint {
++					remote-endpoint = <&csi_gc2145_ep>;
++					bus-width = <8>;
++					hsync-active = <1>;
++					vsync-active = <1>;
++					data-active = <1>;
++					pclk-sample = <1>;
++				};
++			};
++		};
++
+ 		/* Rear camera */
+-		ov5640: camera@3c {
++		ov5640: rear-camera@4c {
+ 			compatible = "ovti,ov5640";
+-			reg = <0x3c>;
+-			pinctrl-names = "default";
+-			pinctrl-0 = <&csi_mclk_pin>;
++			reg = <0x4c>;
+ 			clocks = <&ccu CLK_CSI_MCLK>;
+ 			clock-names = "xclk";
+ 
+@@ -72,7 +95,7 @@ ov5640: camera@3c {
+ 
+ 			port {
+ 				ov5640_ep: endpoint {
+-					remote-endpoint = <&csi_ep>;
++					remote-endpoint = <&csi_ov5640_ep>;
+ 					bus-width = <8>;
+ 					hsync-active = <1>; /* Active high */
+ 					vsync-active = <0>; /* Active low */
+@@ -131,10 +154,15 @@ &cpu3 {
+ };
+ 
+ &csi {
++	pinctrl-0 = <&csi_pins>, <&csi_mclk_pin>;
+ 	status = "okay";
+ 
+ 	port {
+-		csi_ep: endpoint {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi_ov5640_ep: endpoint@0 {
++			reg = <0>;
+ 			remote-endpoint = <&ov5640_ep>;
+ 			bus-width = <8>;
+ 			hsync-active = <1>; /* Active high */
+@@ -142,6 +170,16 @@ csi_ep: endpoint {
+ 			data-active = <1>;  /* Active high */
+ 			pclk-sample = <1>;  /* Rising */
+ 		};
++
++		csi_gc2145_ep: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&gc2145_ep>;
++			bus-width=<8>;
++			hsync-active = <1>; /* Active high */
++			vsync-active = <1>; /* Active high */
++			data-active = <1>;  /* Active high */
++			pclk-sample = <1>;  /* Rising */
++		};
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
new file mode 100644
index 000000000000..d621c5bdf3a2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
@@ -0,0 +1,113 @@
+From f54558b6db666d6f49b646ad0f8e7e1fb9681f54 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 12:40:31 +0200
+Subject: arm64: dts: allwinner: h5: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all H5 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts  | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 8 ++++++++
+ .../arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 8 ++++++++
+ .../boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts  | 8 ++++++++
+ 4 files changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
+index 076a0b983101..5882b62097a9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
+@@ -69,3 +69,11 @@ hdmi_out_con: endpoint {
+ &i2c1 {
+ 	status = "okay";
+ };
++
++&i2s2 {
++	status = "okay";
++};
++
++&sound_hdmi {
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+index ce3ae19e72db..460c0e3d2f97 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -145,6 +145,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -190,6 +194,10 @@ reg_vdd_cpux: regulator@65 {
+ 	};
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spi0  {
+ 	status = "okay";
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index d7f8bad6bb98..6e44f86a8f63 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -145,6 +145,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -182,6 +186,10 @@ &ohci3 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+index 22530ace12d5..3e69ebde50d3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+@@ -77,6 +77,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -115,6 +119,10 @@ &ohci0 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..c1fba03e9308
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
@@ -0,0 +1,51 @@
+From 7e6141fc73b9ec80fc00116238134bce5bc06575 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 14 Dec 2019 20:54:40 -0600
+Subject: arm64: dts: allwinner: h6: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 44a36bb1e7c6..e230d38847db 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -89,6 +89,13 @@ psci {
+ 		method = "smc";
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -222,6 +229,19 @@ syscon: syscon@3000000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@100000 {
++				compatible = "mmio-sram";
++				reg = <0x00100000 0x18000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00100000 0x18000>;
++
++				scpi_sram: scp-shmem@17c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x17c00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@28000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00028000 0x1e000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..0707dea6265d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
@@ -0,0 +1,56 @@
+From d4a381ea88f71cc334df5f3196c6e4e62fe9fcde Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Tue, 10 Nov 2020 20:43:28 +0100
+Subject: arm64: dts: allwinner: h6: Add hdmi sound card
+
+H6 supports HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index d11e5041bae9..8b2e96838f9d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -89,6 +89,20 @@ psci {
+ 		method = "smc";
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun50i-h6-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s1>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -102,6 +116,7 @@ timer {
+ 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ 	};
+ 
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -780,6 +795,7 @@ ohci3: usb@5311400 {
+ 		};
+ 
+ 		hdmi: hdmi@6000000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-h6-dw-hdmi";
+ 			reg = <0x06000000 0x10000>;
+ 			reg-io-width = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
new file mode 100644
index 000000000000..0d447be2caa2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
@@ -0,0 +1,123 @@
+From 7f4536858220db67210267f15dd79173bb7a669d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 11 Jan 2022 13:08:47 +0100
+Subject: arm64: dts: allwinner: h6: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all H6 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts  | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi   | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts    | 8 ++++++++
+ 4 files changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+index 381d58cea092..89231b4afe8b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+@@ -119,6 +119,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -290,6 +294,10 @@ sw {
+ 	};
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spdif {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spdif_tx_pin>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index c2ea73d43122..ead12d861e12 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -167,6 +167,10 @@ ext_rgmii_phy: ethernet-phy@1 {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+@@ -339,6 +343,10 @@ &rtc {
+ 	clocks = <&ext_osc32k>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_ph_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+index 92745128fcfe..b019bbaae21d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+@@ -91,6 +91,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+@@ -244,6 +248,10 @@ &rtc {
+ 	clocks = <&ext_osc32k>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_ph_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+index 1ffd68f43f87..341f42ae0f30 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+@@ -123,6 +123,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -298,6 +302,10 @@ &rtc {
+ 	clocks = <&ext_osc32k>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ /*
+  * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI
+  * flash and eMMC at the same time, as one of them would fail probing.
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
new file mode 100644
index 000000000000..eba666989fb6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
@@ -0,0 +1,33 @@
+From a541aa8864c9f9b1c7b8f5bdc2c3e50571136f17 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:04:01 -0600
+Subject: arm64: dts: allwinner: h6: Protect SCP clocks
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index ea99a7727872..44a36bb1e7c6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -256,6 +256,7 @@ ccu: clock@3001000 {
+ 			reg = <0x03001000 0x1000>;
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
+ 			clock-names = "hosc", "losc", "iosc";
++			protected-clocks = <CLK_BUS_MSGBOX>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+@@ -951,6 +952,7 @@ r_ccu: clock@7010000 {
+ 			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
+ 				 <&ccu CLK_PLL_PERIPH0>;
+ 			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			protected-clocks = <CLK_R_APB1_TWD>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
new file mode 100644
index 000000000000..01b38f935ae9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
@@ -0,0 +1,105 @@
+From a0ced543914467d3974932b4f7187ae00d39103f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 20 Aug 2019 14:54:48 +0200
+Subject: arm64: dts: allwinner: orange-pi-3: Enable ethernet
+
+Orange Pi 3 has two regulators that power the Realtek RTL8211E
+PHY. According to the datasheet, both regulators need to be enabled
+at the same time, or that "phy-io" should be enabled slightly earlier
+than "phy" regulator.
+
+RTL8211E/RTL8211EG datasheet says:
+
+  Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously
+  or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power
+  later than 3.3V power may lead to errors.
+
+The driver ensures the regulator enable ordering. The timing is set
+in DT via startup-delay-us.
+
+We also need to wait at least 30ms after power-up/reset, before
+accessing the PHY registers.
+
+All values of RX/TX delay were tested exhaustively and a middle one
+of the range of working values was chosen.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-h6-orangepi-3.dts    | 40 +++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index 6fc65e8db220..c2ea73d43122 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -15,6 +15,7 @@ / {
+ 	aliases {
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
++		ethernet0 = &emac;
+ 	};
+ 
+ 	chosen {
+@@ -64,6 +65,15 @@ reg_vcc5v: vcc5v {
+ 		regulator-always-on;
+ 	};
+ 
++	reg_gmac_2v5: gmac-2v5 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-2v5";
++		regulator-min-microvolt = <2500000>;
++		regulator-max-microvolt = <2500000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++	};
++
+ 	reg_vcc33_wifi: vcc33-wifi {
+ 		/* Always on 3.3V regulator for WiFi and BT */
+ 		compatible = "regulator-fixed";
+@@ -128,6 +138,35 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii-id";
++	phy-handle = <&ext_rgmii_phy>;
++	/*
++	 * The board uses 2.5V RGMII signalling. Power sequence to enable
++	 * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails
++	 * at the same time and to wait 100ms. The driver enables phy-io
++	 * first. Delay is achieved with enable-ramp-delay on reg_aldo2.
++	 */
++	phy-supply = <&reg_aldo2>;
++	phy-io-supply = <&reg_gmac_2v5>;
++	allwinner,rx-delay-ps = <200>;
++	allwinner,tx-delay-ps = <200>;
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++
++		reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
++		reset-assert-us = <15000>;
++		reset-deassert-us = <40000>;
++	};
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+@@ -211,6 +250,7 @@ reg_aldo2: aldo2 {
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+ 				regulator-name = "vcc33-audio-tv-ephy-mac";
++				regulator-enable-ramp-delay = <100000>;
+ 			};
+ 
+ 			/* ALDO3 is shorted to CLDO1 */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
new file mode 100644
index 000000000000..f679a6a87cee
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
@@ -0,0 +1,47 @@
+From c96e0f80379b0bf105c52ce500b7c5bd1eab538e Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 24 Sep 2022 21:59:07 +0200
+Subject: arm64: dts: rockchip: rk356x: Fix PCIe register map and ranges
+
+I have two Realtek PCIe wifi cards connected over the 4 port PCIe bridge
+to Quartz64-A. The cards fail to work, when nvme SSD is connected at the
+same time to the bridge. Without nvme connected, cards work fine. The
+issue seems to be related to mixed use of devices which make use of I/O
+ranges and memory ranges.
+
+This patch changes I/O, MEM and config mappings so that config and I/O
+mappings use the 0xf4000000 outbound address space, and MEM range uses
+the whole 0x300000000 outbound space.
+
+These values were suggested by pgwipeout:
+
+  https://lore.kernel.org/lkml/875ygbsrf3.fsf@bloch.sibelius.xs4all.nl/T/#m84b5f6992cc26dffe0d3783c0d8c9c86e5e10c10
+
+This is identical to how BSP does the mappings.
+
+This change to the regs/ranges makes the issue go away and both nvme and
+wifi cards work when connected at the same time to the bridge. I tested
+the nvme with large amount of reads/writes, both behind the PCIe bridge
+and when directly connected to Quartz64-A board.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+index 92f96ec01385..c57d702d446a 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -994,7 +994,7 @@ pcie2x1: pcie@fe260000 {
+ 				<0 0 0 4 &pcie_intc 3>;
+ 		linux,pci-domain = <0>;
+ 		num-ib-windows = <6>;
+-		num-ob-windows = <2>;
++		num-ob-windows = <8>;
+ 		max-link-speed = <2>;
+ 		msi-map = <0x0 &gic 0x0 0x1000>;
+ 		num-lanes = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
new file mode 100644
index 000000000000..9c3e4e62fb4a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
@@ -0,0 +1,31 @@
+From 509ccb2dfd590223285779eed15f242d133bb551 Mon Sep 17 00:00:00 2001
+From: Arnav Singh <me@arnavion.dev>
+Date: Mon, 6 May 2024 16:36:04 -0700
+Subject: arm64: dts: sun50i: Define orientation and rotation for PinePhone
+ rear camera
+
+This enables libcamera to detect the correct orientation from
+the device tree and propagate it further to e.g. Pipewire.
+
+Signed-off-by: Arnav Singh <me@arnavion.dev>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index e14e945ba6cd..a2e9c65eae2d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -610,6 +610,9 @@ ov5640: rear-camera@4c {
+ 		reset-gpios = <&pio 3 3 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PD3 */
+ 		powerdown-gpios = <&pio 2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PC0 */
+ 
++		orientation = <1>;
++		rotation = <270>;
++
+ 		port {
+ 			ov5640_ep: endpoint {
+ 				remote-endpoint = <&csi_ov5640_ep>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-Add-missing-trip-points-for-GPU.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-Add-missing-trip-points-for-GPU.patch
new file mode 100644
index 000000000000..80d9bf07a805
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-Add-missing-trip-points-for-GPU.patch
@@ -0,0 +1,51 @@
+From 3c0f4e3429c36bad9eaef6711fb54d617e1ee489 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 16 Oct 2022 23:20:59 +0200
+Subject: arm64: dts: sun50i-a64: Add missing trip points for GPU
+
+Linux 6.1 requires them.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index de04e4e50542..fd24ae4713e6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -265,6 +265,15 @@ gpu0_thermal: gpu0-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 1>;
++
++			trips {
++				gpu0_crit: gpu-crit {
++					/* milliCelsius */
++					temperature = <110000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
+ 		};
+ 
+ 		gpu1_thermal: gpu1-thermal {
+@@ -272,6 +281,15 @@ gpu1_thermal: gpu1-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 2>;
++
++			trips {
++				gpu1_crit: gpu-crit {
++					/* milliCelsius */
++					temperature = <110000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
+ 		};
+ 	};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
new file mode 100644
index 000000000000..7f8962e0cc79
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
@@ -0,0 +1,59 @@
+From 149a7c5895601c7ea4898d691a028613ec63a7b8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 1 Feb 2020 23:41:18 +0100
+Subject: arm64: dts: sun50i-a64: Set fifo-size for uarts
+
+Boot time optimization.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 5610e1364ba1..fbc17e247b1e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -975,6 +975,7 @@ uart0: serial@1c28000 {
+ 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART0>;
+ 			resets = <&ccu RST_BUS_UART0>;
+ 			status = "disabled";
+@@ -986,6 +987,7 @@ uart1: serial@1c28400 {
+ 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART1>;
+ 			resets = <&ccu RST_BUS_UART1>;
+ 			status = "disabled";
+@@ -997,6 +999,7 @@ uart2: serial@1c28800 {
+ 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART2>;
+ 			resets = <&ccu RST_BUS_UART2>;
+ 			status = "disabled";
+@@ -1008,6 +1011,7 @@ uart3: serial@1c28c00 {
+ 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART3>;
+ 			resets = <&ccu RST_BUS_UART3>;
+ 			status = "disabled";
+@@ -1019,6 +1023,7 @@ uart4: serial@1c29000 {
+ 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART4>;
+ 			resets = <&ccu RST_BUS_UART4>;
+ 			status = "disabled";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-AF8133J-to-PinePhone.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-AF8133J-to-PinePhone.patch
new file mode 100644
index 000000000000..00e2d0008732
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-AF8133J-to-PinePhone.patch
@@ -0,0 +1,40 @@
+From 0bbe0e5dfe9e919e3f02ccf35d575fee6a591afe Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Thu, 18 Mar 2021 20:22:05 +0800
+Subject: arm64: dts: sun50i-a64-pinephone: Add AF8133J to PinePhone
+
+New batches of PinePhones switched the magnetometer to AF8133J from
+LIS3MDL because lack of ST components.
+
+Add this magnetometer to the device tree. These two sensors do not
+conflict with each other, and the non-existent sensor's driver won't
+just get probed properly.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 4cf527b06303..e174c3cfc34f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -492,6 +492,15 @@ &i2c1 {
+ 	status = "okay";
+ 	clock-frequency = <400000>;
+ 
++	/* Alternative magnetometer */
++	af8133j: magnetometer@1c {
++		compatible = "voltafield,af8133j";
++		reg = <0x1c>;
++		reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>;
++		avdd-supply = <&reg_dldo1>;
++		dvdd-supply = <&reg_dldo1>;
++	};
++
+ 	/* Magnetometer */
+ 	lis3mdl: magnetometer@1e {
+ 		compatible = "st,lis3mdl-magn";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
new file mode 100644
index 000000000000..ccfa62477b74
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
@@ -0,0 +1,416 @@
+From 7242886b091bf136ebe0323e34a8b271dc04d2d6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Jul 2020 00:58:16 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add Type-C support for all PP
+ variants 1.0-1.2
+
+There are differences in GPIO and how VBUS is handled. Describe them
+in DTS. Thankfully we can support both unmodded and modded variants
+of 1.0 and 1.1 boards with one DTS. No need for more subvariants.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../allwinner/sun50i-a64-pinephone-1.0.dts    | 86 +++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.1.dts    | 86 +++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.2.dts    | 60 +++++++++++++
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 68 ++++++++++++++-
+ 4 files changed, 299 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index 219f720b8b7d..498ae493d176 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -8,6 +8,92 @@
+ / {
+ 	model = "Pine64 PinePhone Developer Batch (1.0)";
+ 	compatible = "pine64,pinephone-1.0", "pine64,pinephone", "allwinner,sun50i-a64";
++
++	reg_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++		enable-active-high;
++		vin-supply = <&reg_drivevbus>;
++	};
++};
++
++&axp803 {
++	x-powers,drive-vbus-en;
++};
++
++&i2c0 {
++	hdmi-bridge@28 {
++		compatible = "analogix,anx7688";
++		reg = <0x28>;
++
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_FALLING>; /* PL11 */
++
++		enable-gpios = <&pio 3 10 GPIO_ACTIVE_LOW>; /* PD10 */
++		reset-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++
++		cabledet-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++
++		avdd10-supply = <&reg_anx1v0>;
++		dvdd10-supply = <&reg_anx1v0>;
++		/* This is for the HW hack variant, but will also work for non-modified version. */
++		avdd18-supply = <&reg_ldo_io1>;
++		dvdd18-supply = <&reg_ldo_io1>;
++		avdd33-supply = <&reg_dldo1>;
++		vconn-supply = <&reg_vconn5v0>;
++		hdmi_vt-supply = <&reg_dldo1>;
++
++		source-caps = <
++			PDO_FIXED(5000, 500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		sink-caps = <
++			PDO_FIXED(5000, 3000, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		/*
++		 * ANX7688 can't enable/disable USB-5V <-> DCIN switch by
++		 * itself, and PMIC's N_VBUSEN is not connected anywhere either,
++		 * so we need to configure everything in software:
++		 *
++		 * - get the VBUS status from ANX7688 via I2C
++		 * - configure PMIC to let it know vbus drive status (via
++		 *   reg_drivevbus)
++		 * - enable VBUS switch and USB-5V regulator (via reg_vbus
++		 *   and reg_usb_5v)
++		 */
++		vbus-supply = <&reg_vbus>;
++		vbus_in-supply = <&usb_power_supply>;
++
++		port {
++			typec0_dr_sw: endpoint {
++				remote-endpoint = <&usb0_drd_sw>;
++			};
++		};
++	};
++};
++
++/*
++ * The N_VBUSEN pin is disconnected, but we need to inform the PMIC about
++ * the VBUS status anyway. To avoid the pin from floating and to inform
++ * the PMIC, about VBUS status, we couple reg_drivevbus with reg_vbus.
++ */
++&reg_drivevbus {
++	vin-supply = <&reg_usb_5v>;
++	status = "okay";
++};
++
++&usbphy {
++	usb-role-switch;
++
++	port {
++		usb0_drd_sw: endpoint {
++			remote-endpoint = <&typec0_dr_sw>;
++		};
++	};
+ };
+ 
+ &codec_analog {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 723af64a9cee..73275308f484 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -8,6 +8,20 @@
+ / {
+ 	model = "Pine64 PinePhone Braveheart (1.1)";
+ 	compatible = "pine64,pinephone-1.1", "pine64,pinephone", "allwinner,sun50i-a64";
++
++	reg_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++		enable-active-high;
++		vin-supply = <&reg_drivevbus>;
++	};
++};
++
++&axp803 {
++	x-powers,drive-vbus-en;
+ };
+ 
+ &backlight {
+@@ -33,7 +47,79 @@ &codec_analog {
+ 	allwinner,internal-bias-resistor;
+ };
+ 
++&i2c0 {
++	hdmi-bridge@28 {
++		compatible = "analogix,anx7688";
++		reg = <0x28>;
++
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_FALLING>; /* PL11 */
++
++		enable-gpios = <&pio 3 10 GPIO_ACTIVE_LOW>; /* PD10 */
++		reset-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++
++		cabledet-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++
++		avdd10-supply = <&reg_anx1v0>;
++		dvdd10-supply = <&reg_anx1v0>;
++		/* This is for the HW hack variant, but will also work for non-modified version. */
++		avdd18-supply = <&reg_ldo_io1>;
++		dvdd18-supply = <&reg_ldo_io1>;
++		avdd33-supply = <&reg_dldo1>;
++		vconn-supply = <&reg_vconn5v0>;
++		hdmi_vt-supply = <&reg_dldo1>;
++
++		source-caps = <
++			PDO_FIXED(5000, 500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		sink-caps = <
++			PDO_FIXED(5000, 3000, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		/*
++		 * ANX7688 can't enable/disable USB-5V <-> DCIN switch by
++		 * itself, and PMIC's N_VBUSEN is not connected anywhere either,
++		 * so we need to configure everything in software:
++		 *
++		 * - get the VBUS status from ANX7688 via I2C
++		 * - configure PMIC to let it know vbus drive status (via
++		 *   reg_drivevbus)
++		 * - enable VBUS switch and USB-5V regulator (via reg_vbus
++		 *   and reg_usb_5v)
++		 */
++		vbus-supply = <&reg_vbus>;
++		vbus_in-supply = <&usb_power_supply>;
++
++		port {
++			typec0_dr_sw: endpoint {
++				remote-endpoint = <&usb0_drd_sw>;
++			};
++		};
++	};
++};
++
++/*
++ * The N_VBUSEN pin is disconnected, but we need to inform the PMIC about
++ * the VBUS status anyway. To avoid the pin from floating and to inform
++ * the PMIC, about VBUS status, we couple reg_drivevbus with reg_vbus.
++ */
++&reg_drivevbus {
++	vin-supply = <&reg_usb_5v>;
++	status = "okay";
++};
++
+ &sgm3140 {
+ 	enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
++
++&usbphy {
++	usb-role-switch;
++
++	port {
++		usb0_drd_sw: endpoint {
++			remote-endpoint = <&typec0_dr_sw>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index 4e7e237cb46a..40127186606f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -48,7 +48,67 @@ &mmc1 {
+ 	mmc-pwrseq = <&wifi_pwrseq>;
+ };
+ 
++&i2c0 {
++	hdmi-bridge@28 {
++		compatible = "analogix,anx7688";
++		reg = <0x28>;
++
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_FALLING>; /* PL11 */
++
++		enable-gpios = <&pio 3 10 GPIO_ACTIVE_LOW>; /* PD10 */
++		reset-gpios = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++
++		cabledet-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++
++		avdd10-supply = <&reg_anx1v0>;
++		dvdd10-supply = <&reg_anx1v0>;
++		avdd18-supply = <&reg_ldo_io1>;
++		dvdd18-supply = <&reg_ldo_io1>;
++		avdd33-supply = <&reg_dcdc1>;
++		vconn-supply = <&reg_vconn5v0>;
++		hdmi_vt-supply = <&reg_dldo1>;
++
++		source-caps = <
++			PDO_FIXED(5000, 500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		sink-caps = <
++			PDO_FIXED(5000, 3000, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		/*
++		 * ANX7688 will enable/disable USB-5V <-> DCIN switch by itself
++		 * via VBUS_CTRL pin. The driver just has to enable the USB-5V
++		 * so that the switch has power.
++		 */
++		vbus-supply = <&reg_usb_5v>;
++		vbus_in-supply = <&usb_power_supply>;
++
++		port {
++			typec0_dr_sw: endpoint {
++				remote-endpoint = <&usb0_drd_sw>;
++			};
++		};
++	};
++};
++
++&reg_anx1v0 {
++	gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */
++	enable-active-high;
++};
++
+ &sgm3140 {
+ 	enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
++
++&usbphy {
++	usb-role-switch;
++
++	port {
++		usb0_drd_sw: endpoint {
++			remote-endpoint = <&typec0_dr_sw>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 92e77503b591..bf7bd0be9deb 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -10,6 +10,7 @@
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/usb/pd.h>
+ 
+ / {
+ 	chassis-type = "handset";
+@@ -67,6 +68,24 @@ led-2 {
+ 		};
+ 	};
+ 
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	reg_anx1v0: anx1v0 {
++		compatible = "regulator-fixed";
++		regulator-name = "anx1v0";
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1000000>;
++	};
++
+ 	reg_ps: ps-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "ps";
+@@ -75,6 +94,24 @@ reg_ps: ps-regulator {
+ 		regulator-boot-on;
+ 	};
+ 
++	reg_usb_5v: usb-5v {
++		compatible = "regulator-fixed";
++		regulator-name = "usb-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 8 GPIO_ACTIVE_HIGH>; /* PD8 */
++		enable-active-high;
++	};
++
++	reg_vbat_bb: vbat-bb {
++		compatible = "regulator-fixed";
++		regulator-name = "vbat-bb";
++		regulator-min-microvolt = <3500000>;
++		regulator-max-microvolt = <3500000>;
++		gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++		enable-active-high;
++	};
++
+ 	reg_vbat_wifi: vbat-wifi {
+ 		compatible = "regulator-fixed";
+ 		regulator-min-microvolt = <3300000>;
+@@ -82,6 +119,16 @@ reg_vbat_wifi: vbat-wifi {
+ 		regulator-name = "vbat-wifi";
+ 	};
+ 
++	/* This is a charge pump for CC1 and CC2 pins on USB-C connector. */
++	reg_vconn5v0: vconn5v0 {
++		compatible = "regulator-fixed";
++		regulator-name = "vconn5v0";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 9 GPIO_ACTIVE_HIGH>; /* PD9 */
++		enable-active-high;
++	};
++
+ 	sgm3140: led-controller {
+ 		compatible = "sgmicro,sgm3140";
+ 		vin-supply = <&reg_dcdc1>;
+@@ -197,6 +244,21 @@ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	hvcc-supply = <&reg_dldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&sound_hdmi {
++	status = "okay";
++};
++
+ &i2c_csi {
+ 	gc2145: front-camera@3c {
+ 		compatible = "galaxycore,gc2145";
+@@ -299,6 +361,10 @@ &i2c2 {
+ 	status = "okay";
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &lradc {
+ 	vref-supply = <&reg_aldo3>;
+ 	wakeup-source;
+@@ -592,7 +658,7 @@ &uart3 {
+ };
+ 
+ &usb_otg {
+-	dr_mode = "peripheral";
++	dr_mode = "otg";
+ 	status = "okay";
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
new file mode 100644
index 000000000000..95f2a5b3df05
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
@@ -0,0 +1,187 @@
+From f2aaf8f5825b479fc9bba756025996e560ec6e82 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 28 Sep 2020 04:35:13 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add detailed OCV to capactiy
+ conversion table
+
+This ensures that discharging stops at 3V, and that charging current
+limits are enforced. It also allows for more precise capacity reporting
+(on my device at the very least, at room temperature).
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 151 ++++++++++++++++++
+ 1 file changed, 151 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index bf7bd0be9deb..243d9c793227 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -28,6 +28,156 @@ backlight: backlight {
+ 		/* Backlight configuration differs per PinePhone revision. */
+ 	};
+ 
++        bat: battery {
++                compatible = "simple-battery";
++                voltage-min-design-microvolt = <3000000>;
++                voltage-max-design-microvolt = <4350000>;
++                energy-full-design-microwatt-hours = <12000000>;
++                charge-full-design-microamp-hours = <2750000>;
++                precharge-current-microamp = <130000>;
++                charge-term-current-microamp = <50000>;
++                constant-charge-current-max-microamp = <1300000>;
++                constant-charge-voltage-max-microvolt = <4350000>;
++                factory-internal-resistance-micro-ohms = <150000>;
++                resistance-temp-table = <20 150>;
++                ocv-capacity-celsius = <20>;
++                ocv-capacity-table-0 =
++                	<4334000 100>,
++			<4319700 99>,
++			<4304300 98>,
++			<4292200 97>,
++			<4280100 96>,
++			<4269100 95>,
++			<4253700 94>,
++			<4242700 93>,
++			<4232800 92>,
++			<4222900 91>,
++			<4211900 90>,
++			<4203100 89>,
++			<4192100 88>,
++			<4177800 87>,
++			<4167900 86>,
++			<4155800 85>,
++			<4147000 84>,
++			<4136000 83>,
++			<4126100 82>,
++			<4111800 81>,
++			<4102999 80>,
++			<4093100 79>,
++			<4084300 78>,
++			<4075500 77>,
++			<4064500 76>,
++			<4054600 75>,
++			<4042500 74>,
++			<4035900 73>,
++			<4029300 72>,
++			<4018300 71>,
++			<4006200 70>,
++			<3993000 69>,
++			<3974300 68>,
++			<3964400 67>,
++			<3956700 66>,
++			<3949000 65>,
++			<3943500 64>,
++			<3938000 63>,
++			<3931400 62>,
++			<3923700 61>,
++			<3917100 60>,
++			<3903900 59>,
++			<3895100 58>,
++			<3887400 57>,
++			<3878600 56>,
++			<3870900 55>,
++			<3863200 54>,
++			<3855500 53>,
++			<3848900 52>,
++			<3837900 51>,
++			<3830200 50>,
++			<3825800 49>,
++			<3821400 48>,
++			<3815900 47>,
++			<3810400 46>,
++			<3806000 45>,
++			<3801600 44>,
++			<3797200 43>,
++			<3792800 42>,
++			<3789500 41>,
++			<3786200 40>,
++			<3781800 39>,
++			<3778500 38>,
++			<3775200 37>,
++			<3770800 36>,
++			<3764200 35>,
++			<3760900 34>,
++			<3758700 33>,
++			<3755400 32>,
++			<3754300 31>,
++			<3752100 30>,
++			<3748800 29>,
++			<3749900 28>,
++			<3745500 27>,
++			<3742200 26>,
++			<3741100 25>,
++			<3737800 24>,
++			<3734500 23>,
++			<3731200 22>,
++			<3730100 21>,
++			<3724600 20>,
++			<3722400 19>,
++			<3718000 18>,
++			<3713600 17>,
++			<3708100 16>,
++			<3701500 15>,
++			<3689400 14>,
++			<3682800 13>,
++			<3674000 12>,
++			<3666300 11>,
++			<3659700 10>,
++			<3653100 9>,
++			<3647600 8>,
++			<3641000 7>,
++			<3625600 6>,
++			<3613500 5>,
++			<3591500 4>,
++			<3554100 3>,
++			<3489200 2>,
++			<3393500 1>,
++			<3256000 0>;
++                x-powers,ocv-capacity-table =
++                	<0xc0 0>,
++			<0xc1 1>,
++			<0xc2 1>,
++			<0xc3 2>,
++			<0xc4 2>,
++			<0xc5 4>,
++			<0xc6 4>,
++			<0xc7 5>,
++			<0xc8 6>,
++			<0xc9 8>,
++			<0xca 11>,
++			<0xcb 15>,
++			<0xcc 22>,
++			<0xcd 36>,
++			<0xce 44>,
++			<0xcf 48>,
++			<0xd0 51>,
++			<0xd1 53>,
++			<0xd2 56>,
++			<0xd3 60>,
++			<0xd4 64>,
++			<0xd5 69>,
++			<0xd6 71>,
++			<0xd7 75>,
++			<0xd8 78>,
++			<0xd9 82>,
++			<0xda 84>,
++			<0xdb 85>,
++			<0xdc 88>,
++			<0xdd 92>,
++			<0xde 95>,
++			<0xdf 98>;
++        };
++
+ 	bt_sco_codec: bt-sco-codec {
+ 		#sound-dai-cells = <1>;
+ 		compatible = "linux,bt-sco";
+@@ -468,6 +618,7 @@ axp803: pmic@3a3 {
+ 
+ &battery_power_supply {
+ 	status = "okay";
++	monitored-battery = <&bat>;
+ };
+ 
+ &reg_aldo1 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
new file mode 100644
index 000000000000..a17a729e024c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
@@ -0,0 +1,130 @@
+From addb90b6943694c94c3455c44b0eb364118d22ab Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Apr 2020 14:13:08 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add front/back cameras
+
+Pinephone has OV5640 back camera and GC2145 front camera. Add support
+for both.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 89 +++++++++++++++++++
+ 1 file changed, 89 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 87847116ab6d..92e77503b591 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -36,6 +36,15 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	i2c_csi: i2c-csi {
++		compatible = "i2c-gpio";
++		sda-gpios = <&pio 4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PE13 */
++		scl-gpios = <&pio 4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PE12 */
++		i2c-gpio,delay-us = <3>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -124,6 +133,36 @@ &cpu3 {
+ 	cpu-supply = <&reg_dcdc2>;
+ };
+ 
++&csi {
++	pinctrl-0 = <&csi_pins>, <&csi_mclk_pin>;
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi_ov5640_ep: endpoint@0 {
++			reg = <0>;
++			remote-endpoint = <&ov5640_ep>;
++			bus-width = <8>;
++			hsync-active = <1>; /* Active high */
++			vsync-active = <0>; /* Active low */
++			data-active = <1>;  /* Active high */
++			pclk-sample = <1>;  /* Rising */
++		};
++
++		csi_gc2145_ep: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&gc2145_ep>;
++			bus-width = <8>;
++			hsync-active = <1>;
++			vsync-active = <1>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		};
++	};
++};
++
+ &dai {
+ 	status = "okay";
+ };
+@@ -158,6 +197,56 @@ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&i2c_csi {
++	gc2145: front-camera@3c {
++		compatible = "galaxycore,gc2145";
++		reg = <0x3c>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++
++		AVDD-supply = <&reg_dldo3>;
++		DVDD-supply = <&reg_aldo1>;
++		IOVDD-supply = <&reg_eldo3>;
++		reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
++		enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
++
++		port {
++			gc2145_ep: endpoint {
++				remote-endpoint = <&csi_gc2145_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++
++	ov5640: rear-camera@4c {
++		compatible = "ovti,ov5640";
++		reg = <0x4c>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++
++		AVDD-supply = <&reg_dldo3>;
++		DOVDD-supply = <&reg_aldo1>; /* shared with AFVCC */
++		DVDD-supply = <&reg_eldo3>;
++		reset-gpios = <&pio 3 3 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PD3 */
++		powerdown-gpios = <&pio 2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PC0 */
++
++		port {
++			ov5640_ep: endpoint {
++				remote-endpoint = <&csi_ov5640_ep>;
++				bus-width = <8>;
++				hsync-active = <1>; /* Active high */
++				vsync-active = <0>; /* Active low */
++				data-active = <1>;  /* Active high */
++				pclk-sample = <1>;  /* Rising */
++			};
++		};
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
new file mode 100644
index 000000000000..668998170a01
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
@@ -0,0 +1,26 @@
+From b6c99de1a90b7eb306bf026f5eeaef561ae4f605 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 17 Jan 2021 23:06:03 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add interrupt pin for WiFi
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 80c44f9edbc1..0fe215ae2211 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -574,6 +574,8 @@ &mmc1 {
+ 
+ 	rtl8723cs: wifi@1 {
+ 		reg = <1>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 3 IRQ_TYPE_EDGE_FALLING>; /* PL3 */
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
new file mode 100644
index 000000000000..3aa7c5f90566
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
@@ -0,0 +1,119 @@
+From a7c26ce8566ffc215e00eb438ed9b8e2b0f756c9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Jul 2020 01:00:48 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add modem power manager
+
+Pinephone has a EG25-G modem that needs a special powerup/powerdown
+sequence. Add a power manager to manage the modem power.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../allwinner/sun50i-a64-pinephone-1.0.dts    | 22 ++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.1.dts    | 23 +++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.2.dts    | 23 +++++++++++++++++++
+ 3 files changed, 68 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index 498ae493d176..ff01e2be26e7 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -86,6 +86,28 @@ &reg_drivevbus {
+ 	status = "okay";
+ };
+ 
++&uart3 {
++	modem {
++		compatible = "quectel,eg25";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vbat_bb>; /* PL7 */
++
++		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
++		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
++		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++
++		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
++
++		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
++		dtr-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-DTR */
++		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
++
++		quectel,qdai = "1,1,0,1,0,0,1,1";
++	};
++};
++
+ &usbphy {
+ 	usb-role-switch;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 73275308f484..93dc8512fe45 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -114,6 +114,29 @@ &sgm3140 {
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
+ 
++&uart3 {
++	modem {
++		compatible = "quectel,eg25";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vbat_bb>; /* PL7 */
++
++		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
++		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
++		status-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++		status-pwrkey-multiplexed; /* status acts as pwrkey */
++
++		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
++
++		dtr-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-DTR */
++		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
++		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
++
++		quectel,qdai = "1,1,0,1,0,0,1,1";
++	};
++};
++
+ &usbphy {
+ 	usb-role-switch;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index 40127186606f..5e988230e6e4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -103,6 +103,29 @@ &sgm3140 {
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
+ 
++&uart3 {
++	modem {
++		compatible = "quectel,eg25";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vbat_bb>; /* PL7 */
++
++		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
++		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
++		status-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
++		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++
++		host-ready-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-RI */
++
++		dtr-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-DTR */
++		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
++		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
++
++		quectel,qdai = "1,1,0,1,0,0,1,1";
++	};
++};
++
+ &usbphy {
+ 	usb-role-switch;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-PinePhone-m.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-PinePhone-m.patch
new file mode 100644
index 000000000000..d38349e6b101
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-PinePhone-m.patch
@@ -0,0 +1,41 @@
+From e75c7aa4e13c5cb3ac5d1f748d7c3e390af810ce Mon Sep 17 00:00:00 2001
+From: Shoji Keita <awaittrot@shjk.jp>
+Date: Wed, 14 Jul 2021 07:17:18 +0900
+Subject: arm64: dts: sun50i-a64-pinephone: Add mount-matrix for PinePhone
+ magnetometers.
+
+For lis3mdl, values are based on datasheet and PCB drawing.
+For af8133j, values are from testing on a real device.
+
+Signed-off-by: Shoji Keita <awaittrot@shjk.jp>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index e174c3cfc34f..dd7b27a6597c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -499,6 +499,9 @@ af8133j: magnetometer@1c {
+ 		reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>;
+ 		avdd-supply = <&reg_dldo1>;
+ 		dvdd-supply = <&reg_dldo1>;
++		mount-matrix = "0", "-1", "0",
++				"-1", "0", "0",
++				"0", "0", "-1";
+ 	};
+ 
+ 	/* Magnetometer */
+@@ -507,6 +510,9 @@ lis3mdl: magnetometer@1e {
+ 		reg = <0x1e>;
+ 		vdd-supply = <&reg_dldo1>;
+ 		vddio-supply = <&reg_dldo1>;
++		mount-matrix = "0", "1", "0",
++				"-1", "0", "0",
++				"0", "0", "1";
+ 	};
+ 
+ 	/* Light/proximity sensor */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-acceleromet.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-acceleromet.patch
new file mode 100644
index 000000000000..8dc1bdc39b4d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-acceleromet.patch
@@ -0,0 +1,29 @@
+From 258515e4934ea7304f09a58d50fa0c8bb6485a9e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 8 Sep 2020 15:31:26 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add mount matrix for accelerometer
+
+Port from pine64 kernel.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index ff1182be8434..9bf23a57172f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -503,6 +503,9 @@ accelerometer@68 {
+ 		interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */
+ 		vdd-supply = <&reg_dldo1>;
+ 		vddio-supply = <&reg_dldo1>;
++		mount-matrix = "0", "1", "0",
++				"-1", "0", "0",
++				"0", "0", "-1";
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
new file mode 100644
index 000000000000..6deff0895c9c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
@@ -0,0 +1,27 @@
+From 9e6d26dd2628637fed18cc0945763194acffd6c0 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 20 May 2023 16:58:11 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add power supply to stk3311
+
+This makes the driver disable the supply during sleep.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 53f4c1f6648a..16a5ac6d14c0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -634,6 +634,7 @@ light-sensor@48 {
+ 		reg = <0x48>;
+ 		interrupt-parent = <&pio>;
+ 		interrupts = <1 0 IRQ_TYPE_EDGE_FALLING>; /* PB0 */
++		vdd-supply = <&reg_ldo_io0>;
+ 	};
+ 
+ 	/* Accelerometer/gyroscope */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
new file mode 100644
index 000000000000..564ac8154bfd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
@@ -0,0 +1,80 @@
+From 8c12a825a83cadbd4aede1f2c5c0b6a8200f4ce8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 15 Feb 2021 17:45:13 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add reboot mode driver
+
+With the latest p-boot (released 2021-02-15), you can reboot to
+a particular boot option or to the menu, to FEL, to eMMC bootloader,
+regardless of the user defined p-boot defaults.
+
+Call reboot with cmd of LINUX_REBOOT_CMD_RESTART2 and arg:
+
+- fel          Reboot to FEL
+- emmc-egon    Reboot with chainload of bootloader from eMMC
+- sd1-8        Reboot to SD bootfs option
+- emmc1-8      Reboot to eMMC bootfs option
+- menu         Reboot to p-boot menu
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 37 +++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 16a5ac6d14c0..67c4ecff7150 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -416,6 +416,34 @@ sgm3140_flash: led {
+ 		};
+ 	};
+ 
++	/* PinePhone specific reboot modes for p-boot. */
++	reboot-mode {
++		compatible = "nvmem-reboot-mode";
++		nvmem-cells = <&reboot_mode>;
++		nvmem-cell-names = "reboot-mode";
++
++		mode-normal     = <0x0>;
++		mode-fel        = <0xb0010fe1>;
++		mode-emmc-egon  = <0xb001e33c>;
++		mode-sd1        = <0xb0010020>;
++		mode-sd2        = <0xb0010021>;
++		mode-sd3        = <0xb0010022>;
++		mode-sd4        = <0xb0010023>;
++		mode-sd5        = <0xb0010024>;
++		mode-sd6        = <0xb0010025>;
++		mode-sd7        = <0xb0010026>;
++		mode-sd8        = <0xb0010027>;
++		mode-emmc1      = <0xb0010000>;
++		mode-emmc2      = <0xb0010001>;
++		mode-emmc3      = <0xb0010002>;
++		mode-emmc4      = <0xb0010003>;
++		mode-emmc5      = <0xb0010004>;
++		mode-emmc6      = <0xb0010005>;
++		mode-emmc7      = <0xb0010006>;
++		mode-emmc8      = <0xb0010007>;
++		mode-menu       = <0xb00100ff>;
++	};
++
+ 	speaker_amp: audio-amplifier {
+ 		compatible = "simple-audio-amplifier";
+ 		enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
+@@ -909,6 +937,15 @@ &reg_rtc_ldo {
+ 	regulator-name = "vcc-rtc";
+ };
+ 
++&rtc {
++	#address-cells = <1>;
++	#size-cells = <1>;
++
++	reboot_mode: reboot-mode@4 {
++		reg = <0x4 0x4>;
++	};
++};
++
+ &sound {
+ 	status = "okay";
+ 	simple-audio-card,name = "PinePhone";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
new file mode 100644
index 000000000000..b702c5c535ed
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
@@ -0,0 +1,54 @@
+From 80e7c80eb60eb319620fa4f42b5a01425e6af00e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 18 Oct 2021 17:41:25 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add supply for i2c bus to anx7688
+
+The bus power needs to be enabled for anx7688 to be able to communicate
+with the master.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 1 +
+ 3 files changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index 8f6ea6b06aa9..cfb9518e057f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -43,6 +43,7 @@ hdmi-bridge@28 {
+ 		avdd18-supply = <&reg_ldo_io1>;
+ 		dvdd18-supply = <&reg_ldo_io1>;
+ 		avdd33-supply = <&reg_dldo1>;
++		i2c-supply = <&reg_ldo_io0>;
+ 		vconn-supply = <&reg_vconn5v0>;
+ 		hdmi_vt-supply = <&reg_dldo1>;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 63ceae07a0e0..35cb92e3b5f1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -52,6 +52,7 @@ hdmi-bridge@28 {
+ 		avdd18-supply = <&reg_ldo_io1>;
+ 		dvdd18-supply = <&reg_ldo_io1>;
+ 		avdd33-supply = <&reg_dldo1>;
++		i2c-supply = <&reg_ldo_io0>;
+ 		vconn-supply = <&reg_vconn5v0>;
+ 		hdmi_vt-supply = <&reg_dldo1>;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index d28a23e98232..aeb5c69fe51d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -51,6 +51,7 @@ hdmi-bridge@28 {
+ 		avdd18-supply = <&reg_ldo_io1>;
+ 		dvdd18-supply = <&reg_ldo_io1>;
+ 		avdd33-supply = <&reg_dcdc1>;
++		i2c-supply = <&reg_ldo_io0>;
+ 		vconn-supply = <&reg_vconn5v0>;
+ 		hdmi_vt-supply = <&reg_dldo1>;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
new file mode 100644
index 000000000000..3fc5279699c3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
@@ -0,0 +1,33 @@
+From 402a14082450d8d1fc6d73787d6fc7c81dc784ae Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 6 Feb 2020 23:49:27 -0600
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for Bluetooth audio
+
+The PinePhone has a Bluetooth chip with its PCM interface connected to
+AIF3. Add the DAI link so headeset audio can be routed in hardware.
+
+Even though the link is mono, configuring the link for 2 slots is
+required for compatibility with AIF2, which uses a single 32-bit slot,
+and which shares its clock dividers with AIF3. Using equal clock
+frequencies allows the modem and headset to be used at the same time.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 9bf23a57172f..19c712ab85aa 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -181,6 +181,7 @@ bat: battery {
+ 	bt_sco_codec: bt-sco-codec {
+ 		#sound-dai-cells = <1>;
+ 		compatible = "linux,bt-sco";
++		sound-name-prefix = "Bluetooth";
+ 	};
+ 
+ 	chosen {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
new file mode 100644
index 000000000000..f613db596a30
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
@@ -0,0 +1,88 @@
+From 2668b72bf963c038bda4cd195634439e8082f991 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 10 Nov 2022 20:11:10 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for Pinephone 1.2 beta
+
+Beta versions uses a different magnetometer chip.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |  1 +
+ .../allwinner/sun50i-a64-pinephone-1.2b.dts   | 29 +++++++++++++++++++
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 12 --------
+ 3 files changed, 30 insertions(+), 12 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 21149b346a60..38867649c063 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2b.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-early-adopter.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts
+new file mode 100644
+index 000000000000..bb6e075972d1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
++
++/dts-v1/;
++
++#include "sun50i-a64-pinephone-1.2.dts"
++
++/ {
++	model = "Pine64 PinePhone (1.2b)";
++	compatible = "pine64,pinephone-1.2b", "pine64,pinephone", "allwinner,sun50i-a64";
++};
++
++&lis3mdl {
++	status = "disabled";
++};
++
++&i2c1 {
++	/* Alternative magnetometer */
++	af8133j: magnetometer@1c {
++		compatible = "voltafield,af8133j";
++		reg = <0x1c>;
++		reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>;
++		avdd-supply = <&reg_dldo1>;
++		dvdd-supply = <&reg_dldo1>;
++		mount-matrix = "0", "-1", "0",
++				"-1", "0", "0",
++				"0", "0", "-1";
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index daf981fd102f..53f4c1f6648a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -617,18 +617,6 @@ &i2c1 {
+ 	status = "okay";
+ 	clock-frequency = <400000>;
+ 
+-	/* Alternative magnetometer */
+-	af8133j: magnetometer@1c {
+-		compatible = "voltafield,af8133j";
+-		reg = <0x1c>;
+-		reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>;
+-		avdd-supply = <&reg_dldo1>;
+-		dvdd-supply = <&reg_dldo1>;
+-		mount-matrix = "0", "-1", "0",
+-				"-1", "0", "0",
+-				"0", "0", "-1";
+-	};
+-
+ 	/* Magnetometer */
+ 	lis3mdl: magnetometer@1e {
+ 		compatible = "st,lis3mdl-magn";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
new file mode 100644
index 000000000000..b683f84e295e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
@@ -0,0 +1,170 @@
+From 799f9257e30809f7c6c480e6266ebf312cfd2d95 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 21 Jan 2022 23:28:48 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for Pinephone keyboard
+
+Pinephone keyboard can be used with Pinephone. Describe it in
+the device tree.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 136 ++++++++++++++++++
+ 1 file changed, 136 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index dd7b27a6597c..c1896206ace7 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -178,6 +178,122 @@ bat: battery {
+ 			<0xdf 98>;
+         };
+ 
++        ppkb_battery: keyboard-battery {
++                compatible = "simple-battery";
++                voltage-min-design-microvolt = <3000000>;
++                voltage-max-design-microvolt = <4200000>;
++                energy-full-design-microwatt-hours = <21000000>;
++                charge-full-design-microamp-hours = <6000000>;
++                precharge-current-microamp = <100000>;
++                charge-term-current-microamp = <50000>;
++                constant-charge-current-max-microamp = <2000000>;
++                constant-charge-voltage-max-microvolt = <4200000>;
++                factory-internal-resistance-micro-ohms = <120000>;
++                ocv-capacity-celsius = <20>;
++                ocv-capacity-table-0 =
++                	<4147328 100>,
++			<4132636 99>,
++			<4121720 98>,
++			<4110905 97>,
++			<4102063 96>,
++			<4092428 95>,
++			<4082371 94>,
++			<4074137 93>,
++			<4064172 92>,
++			<4056387 91>,
++			<4047198 90>,
++			<4038599 89>,
++			<4030933 88>,
++			<4021831 87>,
++			<4012613 86>,
++			<4003863 85>,
++			<3995132 84>,
++			<3986108 83>,
++			<3977434 82>,
++			<3967977 81>,
++			<3960286 80>,
++			<3951737 79>,
++			<3943518 78>,
++			<3935723 77>,
++			<3928692 76>,
++			<3920093 75>,
++			<3912676 74>,
++			<3905481 73>,
++			<3899881 72>,
++			<3892341 71>,
++			<3887140 70>,
++			<3880005 69>,
++			<3876060 68>,
++			<3869195 67>,
++			<3863234 66>,
++			<3857808 65>,
++			<3851464 64>,
++			<3846976 63>,
++			<3840724 62>,
++			<3835254 61>,
++			<3830946 60>,
++			<3826564 59>,
++			<3821275 58>,
++			<3817413 57>,
++			<3811941 56>,
++			<3808947 55>,
++			<3804959 54>,
++			<3800958 53>,
++			<3797447 52>,
++			<3794303 51>,
++			<3790341 50>,
++			<3787022 49>,
++			<3783436 48>,
++			<3779936 47>,
++			<3776176 46>,
++			<3772160 45>,
++			<3769348 44>,
++			<3766705 43>,
++			<3762481 42>,
++			<3760894 41>,
++			<3758396 40>,
++			<3755803 39>,
++			<3753543 38>,
++			<3749691 37>,
++			<3747026 36>,
++			<3743937 35>,
++			<3741872 34>,
++			<3738529 33>,
++			<3737528 32>,
++			<3734059 31>,
++			<3731586 30>,
++			<3728576 29>,
++			<3725939 28>,
++			<3721208 27>,
++			<3718239 26>,
++			<3713032 25>,
++			<3709785 24>,
++			<3704045 23>,
++			<3701203 22>,
++			<3695965 21>,
++			<3691074 20>,
++			<3684562 19>,
++			<3679140 18>,
++			<3670993 17>,
++			<3664243 16>,
++			<3655383 15>,
++			<3647666 14>,
++			<3642747 13>,
++			<3637775 12>,
++			<3632593 11>,
++			<3627120 10>,
++			<3620923 9>,
++			<3611465 8>,
++			<3597536 7>,
++			<3577366 6>,
++			<3545253 5>,
++			<3497377 4>,
++			<3430377 3>,
++			<3337780 2>,
++			<3183953 1>,
++			<3064061 0>;
++        };
++
+ 	bt_sco_codec: bt-sco-codec {
+ 		#sound-dai-cells = <1>;
+ 		compatible = "linux,bt-sco";
+@@ -540,6 +656,26 @@ accelerometer@68 {
+ /* Connected to pogo pins (external spring based pinheader for user addons) */
+ &i2c2 {
+ 	status = "okay";
++
++	ppkb: keyboard@15 {
++		compatible = "pine64,pinephone-keyboard";
++		reg = <0x15>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 12 IRQ_TYPE_EDGE_FALLING>; /* PL12 */
++		vbat-supply = <&reg_usb_5v>;
++		wakeup-source;
++
++		i2c {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			charger@75 {
++				compatible = "injoinic,ip5209";
++				reg = <0x75>;
++				monitored-battery = <&ppkb_battery>;
++			};
++		};
++	};
+ };
+ 
+ &i2s2 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
new file mode 100644
index 000000000000..7ebdbfcf15c3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
@@ -0,0 +1,71 @@
+From 941cbc676641ac8f404044314351f3eb24be3360 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 5 Feb 2020 23:14:27 -0600
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for modem audio
+
+The PinePhone has a Quectel EG25-G modem (a variant of the EC25) with
+its PCM interface connected to AIF2. Add the DAI link so call audio can
+be routed in hardware.
+
+The modem supports two fixed sample rates, and one fixed word size, with
+a variable BCLK frequency. Use the minimum supported BCLK frequency,
+which corresponds to a slot width of 32 bits.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 25 ++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 19c712ab85aa..652ef6d44e63 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -188,6 +188,12 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	ec25_codec: ec25-codec {
++		#sound-dai-cells = <1>;
++		compatible = "quectel,ec25";
++		sound-name-prefix = "Modem";
++	};
++
+ 	i2c_csi: i2c-csi {
+ 		compatible = "i2c-gpio";
+ 		sda-gpios = <&pio 4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PE13 */
+@@ -306,7 +312,7 @@ vibrator {
+ 
+ &codec {
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&aif3_pins>;
++	pinctrl-0 = <&aif2_pins>, <&aif3_pins>;
+ 	status = "okay";
+ };
+ 
+@@ -771,6 +777,23 @@ &sound {
+ 			"Headset Microphone", "HBIAS",
+ 			"MIC2", "Headset Microphone";
+ 
++	simple-audio-card,dai-link@1 {
++		format = "dsp_a";
++		frame-master = <&link1_codec>;
++		bitclock-master = <&link1_codec>;
++		bitclock-inversion;
++
++		link1_cpu: cpu {
++			sound-dai = <&ec25_codec 0>;
++		};
++
++		link1_codec: codec {
++			sound-dai = <&codec 1>;
++			dai-tdm-slot-num = <1>;
++			dai-tdm-slot-width = <32>;
++		};
++	};
++
+ 	simple-audio-card,dai-link@2 {
+ 		format = "dsp_a";
+ 		frame-master = <&link2_codec>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
new file mode 100644
index 000000000000..1c3543305e74
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
@@ -0,0 +1,35 @@
+From c9cf26ac3928e479da728f88f7f1fbe215bbe2ed Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 30 Nov 2020 06:14:07 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Bump I2C frequency to 400kHz
+
+High speed. :)
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 73ce87eaba85..80c44f9edbc1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -471,6 +471,7 @@ ov5640_ep: endpoint {
+ 
+ &i2c0 {
+ 	status = "okay";
++	clock-frequency = <400000>;
+ 
+ 	touchscreen@5d {
+ 		compatible = "goodix,gt917s";
+@@ -488,6 +489,7 @@ touchscreen@5d {
+ 
+ &i2c1 {
+ 	status = "okay";
++	clock-frequency = <400000>;
+ 
+ 	/* Magnetometer */
+ 	lis3mdl: magnetometer@1e {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
new file mode 100644
index 000000000000..06e8ef82f28c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
@@ -0,0 +1,29 @@
+From ddaaf0d1befebead6f710c444c991bd7e520a9d3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 26 Apr 2021 01:31:27 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Don't make lradc keys a wakeup
+ source
+
+This allow the crust to reach lower suspend state.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 8083a9f0ede6..4cf527b06303 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -533,7 +533,7 @@ &i2s2 {
+ 
+ &lradc {
+ 	vref-supply = <&reg_aldo3>;
+-	wakeup-source;
++//	wakeup-source;
+ 	status = "okay";
+ 
+ 	button-200 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
new file mode 100644
index 000000000000..1d8f9184b2b2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
@@ -0,0 +1,34 @@
+From 3d11a2661472fb8b3b842f5e090b923363c9fefb Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 16 Apr 2022 02:12:06 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Enable Pinephone Keyboard power
+ manager
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index c1896206ace7..daf981fd102f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -427,6 +427,15 @@ vibrator {
+ 		enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
+ 		vcc-supply = <&reg_dcdc1>;
+ 	};
++
++	keyboard-power {
++		compatible = "megi,pinephone-keyboard-power-manager";
++		phone-battery = "axp20x-battery";
++		phone-usb = "axp20x-usb";
++		kb-battery = "ip5xxx-battery";
++		kb-boost = "ip5xxx-boost";
++		kb-usb = "ip5xxx-usb";
++	};
+ };
+ 
+ &codec {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
new file mode 100644
index 000000000000..8187d92aff03
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
@@ -0,0 +1,29 @@
+From 934b0e5d49d9f95d043b7716a7b77a71580fde34 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 23 Sep 2020 00:13:54 -0500
+Subject: arm64: dts: sun50i-a64-pinephone: Enable internal HMIC bias
+
+Revisions 1.0 and 1.1 of the PinePhone mainboard do not have an external
+resistor connecting HBIAS to MIC2. Enable the internal resistor to
+provide the appropriate mic bias.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index ff01e2be26e7..8f6ea6b06aa9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -126,3 +126,7 @@ &sgm3140 {
+ 	enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ 	flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ };
++
++&codec_analog {
++	allwinner,internal-bias-resistor;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
new file mode 100644
index 000000000000..63d4d65d2066
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
@@ -0,0 +1,29 @@
+From a6babb5204ff4fed7f176ab6bfb49f89f80c811d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 5 Aug 2020 11:19:01 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Fix BH modem manager behavior
+
+PP 1.1 has STATUS line multiplexed with POWER KEY, but reading it doesn't
+work reliably. Just treat 1.1 as if it was 1.0, and ignore the STATUS.
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 93dc8512fe45..d67f31ef529e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -123,8 +123,8 @@ modem {
+ 
+ 		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
+ 		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+-		status-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+-		status-pwrkey-multiplexed; /* status acts as pwrkey */
++		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++		//status-pwrkey-multiplexed; /* status acts as pwrkey */
+ 
+ 		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ 		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
new file mode 100644
index 000000000000..45e7a8549970
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
@@ -0,0 +1,28 @@
+From 38c15e91adc1c337c2140f68a349b8959cdf55f7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 25 Apr 2021 03:17:39 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Power off the touch controller in
+ sleep
+
+Otherwise it stays on and consumes quite a bit of power.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 0fe215ae2211..8083a9f0ede6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -484,6 +484,7 @@ touchscreen@5d {
+ 		VDDIO-supply = <&reg_ldo_io0>;
+ 		touchscreen-size-x = <720>;
+ 		touchscreen-size-y = <1440>;
++		poweroff-in-suspend;
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Retain-leds-state-in-suspend.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Retain-leds-state-in-suspend.patch
new file mode 100644
index 000000000000..99e55e1a80ec
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Retain-leds-state-in-suspend.patch
@@ -0,0 +1,43 @@
+From 10d82c224e520d22e9a529e4928c6b92c632f182 Mon Sep 17 00:00:00 2001
+From: Miles Alan <m@milesalan.com>
+Date: Sat, 14 Nov 2020 09:07:00 -0600
+Subject: arm64: dts: sun50i-a64-pinephone: Retain leds state in suspend
+
+Allows user to set a led before entering suspend to know that
+the phone is still on (or could be used for notifications etc.)
+
+Signed-off-by: Miles Alan <m@milesalan.com>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 652ef6d44e63..73ce87eaba85 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -210,18 +210,21 @@ led-0 {
+ 			function = LED_FUNCTION_INDICATOR;
+ 			color = <LED_COLOR_ID_BLUE>;
+ 			gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
++			retain-state-suspended;
+ 		};
+ 
+ 		led-1 {
+ 			function = LED_FUNCTION_INDICATOR;
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
++			retain-state-suspended;
+ 		};
+ 
+ 		led-2 {
+ 			function = LED_FUNCTION_INDICATOR;
+ 			color = <LED_COLOR_ID_RED>;
+ 			gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
++			retain-state-suspended;
+ 		};
+ 	};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
new file mode 100644
index 000000000000..46fe61cae963
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
@@ -0,0 +1,73 @@
+From 9d02c3be048e845a0605a6100e0ed60172a3ac02 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 7 Jun 2021 20:23:52 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Set minimum backlight duty cycle to
+ 10%
+
+Instead of creating our own table, use existing lth_brightness
+functionality in the pwm_bl driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone-1.1.dts  | 16 +---------------
+ .../dts/allwinner/sun50i-a64-pinephone-1.2.dts  | 17 +----------------
+ 2 files changed, 2 insertions(+), 31 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index d67f31ef529e..63ceae07a0e0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -26,21 +26,7 @@ &axp803 {
+ 
+ &backlight {
+ 	power-supply = <&reg_ldo_io0>;
+-	/*
+-	 * PWM backlight circuit on this PinePhone revision was changed since
+-	 * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight
+-	 * being off is around 20%. Duty cycle for the lowest brightness level
+-	 * also varries quite a bit between individual boards, so the lowest
+-	 * value here was chosen as a safe default.
+-	 */
+-	brightness-levels = <
+-		774  793  814  842
+-		882  935  1003 1088
+-		1192 1316 1462 1633
+-		1830 2054 2309 2596
+-		2916 3271 3664 4096>;
+-	num-interpolated-steps = <50>;
+-	default-brightness-level = <400>;
++	lth-brightness = <10>;
+ };
+ 
+ &codec_analog {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index 5e988230e6e4..d28a23e98232 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -17,22 +17,7 @@ wifi_pwrseq: wifi-pwrseq {
+ 
+ &backlight {
+ 	power-supply = <&reg_ldo_io0>;
+-	/*
+-	 * PWM backlight circuit on this PinePhone revision was changed since 1.0,
+-	 * and the lowest PWM duty cycle that doesn't lead to backlight being off
+-	 * is around 10%. Duty cycle for the lowest brightness level also varries
+-	 * quite a bit between individual boards, so the lowest value here was
+-	 * chosen as a safe default.
+-	 */
+-	brightness-levels = <
+-		5000 5248 5506 5858 6345
+-		6987 7805 8823 10062 11543
+-		13287 15317 17654 20319 23336
+-		26724 30505 34702 39335 44427
+-		50000
+-	>;
+-	num-interpolated-steps = <50>;
+-	default-brightness-level = <500>;
++	lth-brightness = <10>;
+ };
+ 
+ &lis3mdl {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
new file mode 100644
index 000000000000..8a7bacb5fc3c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
@@ -0,0 +1,43 @@
+From 4d751c21b4c1249ba0c80b74b3f81da195ee9736 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 6 Feb 2020 04:58:32 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Shorten post-power-on-delay on mmcs
+
+These are not needed.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 243d9c793227..ff1182be8434 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -543,6 +543,7 @@ &mmc0 {
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ 	disable-wp;
+ 	bus-width = <4>;
++	post-power-on-delay-ms = <1>; /* power is already turned on by the bootloader */
+ 	status = "okay";
+ };
+ 
+@@ -553,6 +554,7 @@ &mmc1 {
+ 	vqmmc-supply = <&reg_dldo4>;
+ 	bus-width = <4>;
+ 	non-removable;
++	post-power-on-delay-ms = <1>; /* wifi power is always on */
+ 	status = "okay";
+ 
+ 	rtl8723cs: wifi@1 {
+@@ -568,6 +570,7 @@ &mmc2 {
+ 	bus-width = <8>;
+ 	non-removable;
+ 	cap-mmc-hw-reset;
++	post-power-on-delay-ms = <1>; /* power is already turned on by the bootloader */
+ 	status = "okay";
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
new file mode 100644
index 000000000000..18a1c668bf0f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
@@ -0,0 +1,35 @@
+From 9c8b6d7595bf2715692d1296574464a3e46654e4 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 23 Feb 2024 01:53:14 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Use newer jack detection
+ implementaion
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 67c4ecff7150..e14e945ba6cd 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -469,6 +469,7 @@ keyboard-power {
+ &codec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&aif2_pins>, <&aif3_pins>;
++	jack-type = "headset";
+ 	status = "okay";
+ };
+ 
+@@ -949,7 +950,7 @@ reboot_mode: reboot-mode@4 {
+ &sound {
+ 	status = "okay";
+ 	simple-audio-card,name = "PinePhone";
+-	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
++	simple-audio-card,aux-devs = <&codec_analog>, <&codec>, <&speaker_amp>;
+ 	simple-audio-card,widgets = "Microphone", "Headset Microphone",
+ 				    "Microphone", "Internal Microphone",
+ 				    "Headphone", "Headphone Jack",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
new file mode 100644
index 000000000000..c1ccfd64a832
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
@@ -0,0 +1,84 @@
+From e3021197484ccf29d157114568a3f4ea66a2a022 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 26 Oct 2021 01:25:46 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Workaround broken HDMI HPD signal
+
+HDMI HPD signal from ANX7688 to SoC's HDMI PHY is wrongly level
+shifted and does not register most of the time at the SoC's input.
+
+We need to do the signalling in software. Link anx7688 to hdmi
+driver via extcon interface.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 6 +++++-
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 6 +++++-
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 6 +++++-
+ 3 files changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index cfb9518e057f..0530881d8401 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -25,7 +25,7 @@ &axp803 {
+ };
+ 
+ &i2c0 {
+-	hdmi-bridge@28 {
++	anx7688: hdmi-bridge@28 {
+ 		compatible = "analogix,anx7688";
+ 		reg = <0x28>;
+ 
+@@ -131,3 +131,7 @@ &sgm3140 {
+ &codec_analog {
+ 	allwinner,internal-bias-resistor;
+ };
++
++&hdmi {
++	extcon = <&anx7688 0>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 35cb92e3b5f1..053e4add9973 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -34,7 +34,7 @@ &codec_analog {
+ };
+ 
+ &i2c0 {
+-	hdmi-bridge@28 {
++	anx7688: hdmi-bridge@28 {
+ 		compatible = "analogix,anx7688";
+ 		reg = <0x28>;
+ 
+@@ -133,3 +133,7 @@ usb0_drd_sw: endpoint {
+ 		};
+ 	};
+ };
++
++&hdmi {
++	extcon = <&anx7688 0>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index aeb5c69fe51d..c4e3547e02e9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -34,7 +34,7 @@ &mmc1 {
+ };
+ 
+ &i2c0 {
+-	hdmi-bridge@28 {
++	anx7688: hdmi-bridge@28 {
+ 		compatible = "analogix,anx7688";
+ 		reg = <0x28>;
+ 
+@@ -121,3 +121,7 @@ usb0_drd_sw: endpoint {
+ 		};
+ 	};
+ };
++
++&hdmi {
++	extcon = <&anx7688 0>;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
new file mode 100644
index 000000000000..d106e5a922b1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
@@ -0,0 +1,38 @@
+From 0914e50e1479fa3fc1376ee31d593e61e6feaa13 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 18 Feb 2024 17:39:58 +0100
+Subject: arm64: dts: sun50i-a64-pinetab: Add accelerometer
+
+Add accelerometer. Patch picked up from here:
+
+https://github.com/dreemurrs-embedded/Pine64-Arch/blob/master/PKGBUILDS/pine64/linux-megi/pinetab-accelerometer.patch
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 80a3c4e24a07..17434e0095f2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -237,7 +237,15 @@ &i2c0_pins {
+ &i2c1 {
+ 	status = "okay";
+ 
+-	/* TODO: add Bochs BMA223 accelerometer here */
++	bma223@18 {
++		compatible = "bosch,bma223", "bosch,bma222e";
++		reg = <0x18>;
++		interrupt-parent = <&pio>;
++		interrupts = <7 5 IRQ_TYPE_LEVEL_HIGH>; /* PH5 */
++		mount-matrix = "0", "-1", "0",
++			       "-1", "0", "0",
++			       "0", "0", "-1";
++	};
+ };
+ 
+ &lradc {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
new file mode 100644
index 000000000000..6cfabfd9d636
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
@@ -0,0 +1,28 @@
+From 18498535047a53a48c471e66ff4b50a87025bb0d Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 18 Feb 2024 17:38:00 +0100
+Subject: arm64: dts: sun50i-a64-pinetab: Name sound card PineTab
+
+There's no upstream UCM for PineTab, yet. So I guess we can safely
+rename it. Pine64-Arch is using this name.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 5d8081a093b6..80a3c4e24a07 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -475,6 +475,7 @@ hdmi_out_con: endpoint {
+ 
+ &sound {
+ 	status = "okay";
++	simple-audio-card,name = "PineTab";
+ 	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
+ 	simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
+ 				    "Microphone", "Internal Microphone Right",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
new file mode 100644
index 000000000000..5d08d001a482
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
@@ -0,0 +1,44 @@
+From 7f2eac439919d57cce93ba11ebd19c55c57c6844 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Sun, 14 Apr 2019 23:46:47 +0800
+Subject: arm64: dts: sun50i-a64-pinetab: enable RTL8723CS bluetooth
+
+PineTab has a RTL8723CS Wi-Fi/BT combo chip on board, the bluetooth part
+of it communicates with A64 via UART, and the power of it is controlled
+with some GPIO at PL bank.
+
+Enable the bluetooth in the device tree.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ .../boot/dts/allwinner/sun50i-a64-pinetab.dts      | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 17434e0095f2..37466d70bb25 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -511,6 +511,20 @@ &uart0 {
+ 	status = "okay";
+ };
+ 
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723cs-bt";
++		reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
++		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		firmware-postfix = "pinebook";
++	};
++};
++
+ &usb_otg {
+ 	dr_mode = "otg";
+ 	status = "okay";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
new file mode 100644
index 000000000000..826aac04383d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
@@ -0,0 +1,35 @@
+From 9bdc25ed7275438f463874e5e7174784624526e7 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 13 Mar 2023 06:02:46 +0100
+Subject: arm64: dts: sun50i-h5: Add missing GPU trip point
+
+Without this, thermal sensor driver fails to probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index e02a3848003e..a6a2e2a19e75 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -234,6 +234,15 @@ gpu-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 1>;
++
++			trips {
++				gpu_crit: gpu-crit {
++					/* milliCelsius */
++					temperature = <110000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
+ 		};
+ 	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
new file mode 100644
index 000000000000..6f438f6b092b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
@@ -0,0 +1,97 @@
+From f14b296fa79e0e5309f6a44ee2cfcd4342db69c0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 17 Aug 2020 23:43:53 +0200
+Subject: arm64: dts: sun50i-h5: Use my own more aggressive OPPs on H5
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 44 +++++++++----------
+ 1 file changed, 22 insertions(+), 22 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
+index 1afad8b437d7..a74463c8cc52 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
+@@ -6,57 +6,57 @@ cpu_opp_table: opp-table-cpu {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
+-		opp-408000000 {
+-			opp-hz = /bits/ 64 <408000000>;
+-			opp-microvolt = <1000000 1000000 1310000>;
++		opp-480000000 {
++			opp-hz = /bits/ 64 <480000000>;
++			opp-microvolt = <1040000 1040000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-648000000 {
+ 			opp-hz = /bits/ 64 <648000000>;
+-			opp-microvolt = <1040000 1040000 1310000>;
++			opp-microvolt = <1040000 1040000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-816000000 {
+ 			opp-hz = /bits/ 64 <816000000>;
+-			opp-microvolt = <1080000 1080000 1310000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-912000000 {
+-			opp-hz = /bits/ 64 <912000000>;
+-			opp-microvolt = <1120000 1120000 1310000>;
++			opp-microvolt = <1100000 1100000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-960000000 {
+ 			opp-hz = /bits/ 64 <960000000>;
+-			opp-microvolt = <1160000 1160000 1310000>;
++			opp-microvolt = <1200000 1200000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-1008000000 {
+ 			opp-hz = /bits/ 64 <1008000000>;
+-			opp-microvolt = <1200000 1200000 1310000>;
++			opp-microvolt = <1200000 1200000 1300000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1104000000 {
++			opp-hz = /bits/ 64 <1104000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1056000000 {
+-			opp-hz = /bits/ 64 <1056000000>;
+-			opp-microvolt = <1240000 1240000 1310000>;
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1104000000 {
+-			opp-hz = /bits/ 64 <1104000000>;
+-			opp-microvolt = <1260000 1260000 1310000>;
++		opp-1296000000 {
++			opp-hz = /bits/ 64 <1296000000>;
++			opp-microvolt = <1340000 1340000 1340000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1152000000 {
+-			opp-hz = /bits/ 64 <1152000000>;
+-			opp-microvolt = <1300000 1300000 1310000>;
++		opp-1368000000 {
++			opp-hz = /bits/ 64 <1368000000>;
++			opp-microvolt = <1400000 1400000 1400000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
new file mode 100644
index 000000000000..2fe580fe9129
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
@@ -0,0 +1,45 @@
+From f9a655a2ec53dccad37951efcc22bb1a8ddf89be Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 10 Sep 2020 21:38:28 +0200
+Subject: arm64: xor: Select 32regs without benchmark to speed up boot
+
+32regs is fastest on Cortex-A53.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/include/asm/xor.h | 14 ++++----------
+ 1 file changed, 4 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/include/asm/xor.h b/arch/arm64/include/asm/xor.h
+index befcd8a7abc9..e4487ddc76e1 100644
+--- a/arch/arm64/include/asm/xor.h
++++ b/arch/arm64/include/asm/xor.h
+@@ -57,21 +57,15 @@ xor_neon_5(unsigned long bytes, unsigned long * __restrict p1,
+ 	kernel_neon_end();
+ }
+ 
+-static struct xor_block_template xor_block_arm64 = {
++static struct xor_block_template xor_block_arm64 __maybe_unused = {
+ 	.name   = "arm64_neon",
+ 	.do_2   = xor_neon_2,
+ 	.do_3   = xor_neon_3,
+ 	.do_4   = xor_neon_4,
+ 	.do_5	= xor_neon_5
+ };
+-#undef XOR_TRY_TEMPLATES
+-#define XOR_TRY_TEMPLATES           \
+-	do {        \
+-		xor_speed(&xor_block_8regs);    \
+-		xor_speed(&xor_block_32regs);    \
+-		if (cpu_has_neon()) { \
+-			xor_speed(&xor_block_arm64);\
+-		} \
+-	} while (0)
++
++#define XOR_SELECT_TEMPLATE(x)	\
++	(&xor_block_32regs)
+ 
+ #endif /* ! CONFIG_KERNEL_MODE_NEON */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
new file mode 100644
index 000000000000..1e894b083bc6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
@@ -0,0 +1,35 @@
+From 6b7ad2ebd6088fe312741a32bb3bfe305abd7955 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 7 Aug 2022 14:28:16 +0200
+Subject: bluetooth: bcm: Restore drive_rts_on_open = true behavior on
+ bcm20702a1
+
+This is what it was on v5.5. It doesn't fix the UART issues though.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/bluetooth/hci_bcm.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c
+index 874d23089b39..44c82b5de906 100644
+--- a/drivers/bluetooth/hci_bcm.c
++++ b/drivers/bluetooth/hci_bcm.c
+@@ -1595,8 +1595,13 @@ static struct bcm_device_data cyw55572_device_data = {
+ 	.max_autobaud_speed = 921600,
+ };
+ 
++static struct bcm_device_data bcm20702a1_device_data = {
++	.drive_rts_on_open = true,
++	.no_early_set_baudrate = true,
++};
++
+ static const struct of_device_id bcm_bluetooth_of_match[] = {
+-	{ .compatible = "brcm,bcm20702a1" },
++	{ .compatible = "brcm,bcm20702a1", .data = &bcm20702a1_device_data },
+ 	{ .compatible = "brcm,bcm4329-bt" },
+ 	{ .compatible = "brcm,bcm4330-bt" },
+ 	{ .compatible = "brcm,bcm4334-bt" },
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
new file mode 100644
index 000000000000..8431dffa0651
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
@@ -0,0 +1,28 @@
+From aca138baa776a7b033bc20859f01c9991b2f268d Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 30 Apr 2023 18:12:17 +0200
+Subject: bluetooth: h5: Don't re-initialize rtl8723cs on resume
+
+The power is kept across during sleep, and this is not necessary.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/bluetooth/hci_h5.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c
+index c0436881a533..3f6955ce9b7c 100644
+--- a/drivers/bluetooth/hci_h5.c
++++ b/drivers/bluetooth/hci_h5.c
+@@ -1108,7 +1108,7 @@ static const struct of_device_id rtl_bluetooth_of_match[] = {
+ 	{ .compatible = "realtek,rtl8723bs-bt",
+ 	  .data = (const void *)&h5_data_rtl8723bs },
+ 	{ .compatible = "realtek,rtl8723cs-bt",
+-	  .data = (const void *)&h5_data_rtl8723bs },
++	  .data = (const void *)&h5_data_rtl8822cs },
+ 	{ .compatible = "realtek,rtl8723ds-bt",
+ 	  .data = (const void *)&h5_data_rtl8723bs },
+ #endif
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/bus-sunxi-rsb-Always-check-register-address-validity.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/bus-sunxi-rsb-Always-check-register-address-validity.patch
new file mode 100644
index 000000000000..c81a4114009f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/bus-sunxi-rsb-Always-check-register-address-validity.patch
@@ -0,0 +1,32 @@
+From 92d72b4b4eaf83fd77707b83088c0ba9f30f2a16 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 30 Dec 2019 21:56:59 -0600
+Subject: bus: sunxi-rsb: Always check register address validity
+
+The register address was already validated for read operations before
+being truncated to a u8. Write operations have the same set of possible
+addresses, and the address is being truncated from u32 to u8 here as
+well, so the same check is needed.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/bus/sunxi-rsb.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c
+index 1e29ba76615d..7dcb990cdaf2 100644
+--- a/drivers/bus/sunxi-rsb.c
++++ b/drivers/bus/sunxi-rsb.c
+@@ -447,6 +447,9 @@ static int regmap_sunxi_rsb_reg_write(void *context, unsigned int reg,
+ 	struct sunxi_rsb_ctx *ctx = context;
+ 	struct sunxi_rsb_device *rdev = ctx->rdev;
+ 
++	if (reg > 0xff)
++		return -EINVAL;
++
+ 	return sunxi_rsb_write(rdev->rsb, rdev->rtaddr, reg, &val, ctx->size);
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/clk-Implement-protected-clocks-for-all-OF-clock-providers.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-Implement-protected-clocks-for-all-OF-clock-providers.patch
new file mode 100644
index 000000000000..eda63c82a183
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-Implement-protected-clocks-for-all-OF-clock-providers.patch
@@ -0,0 +1,206 @@
+From 67c43c6d5bcaae8938f3412f4fbdaae878200bb4 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 29 Dec 2019 20:23:28 -0600
+Subject: clk: Implement protected-clocks for all OF clock providers
+
+This is a generic implementation of the "protected-clocks" property from
+the common clock binding. It allows firmware to inform the OS about
+clocks that must not be disabled while the OS is running.
+
+This implementation comes with some caveats:
+
+1) Clocks that have CLK_IS_CRITICAL in their init data are prepared/
+enabled before they are attached to the clock tree. protected-clocks are
+only protected once the clock provider is added, which is generally
+after all of the clocks it provides have been registered. This leaves a
+window of opportunity where something could disable or modify the clock,
+such as a driver running on another CPU, or the clock core itself. There
+is a comment to this effect in __clk_core_init():
+
+  /*
+   * Enable CLK_IS_CRITICAL clocks so newly added critical clocks
+   * don't get accidentally disabled when walking the orphan tree and
+   * reparenting clocks
+   */
+
+Similarly, these clocks will be enabled after they are first reparented,
+unlike other CLK_IS_CRITICAL clocks. See the comment in
+clk_core_reparent_orphans_nolock():
+
+  /*
+   * We need to use __clk_set_parent_before() and _after() to
+   * to properly migrate any prepare/enable count of the orphan
+   * clock. This is important for CLK_IS_CRITICAL clocks, which
+   * are enabled during init but might not have a parent yet.
+   */
+
+Ideally we could detect protected clocks before they are reparented, but
+there are two problems with that:
+
+  a) From the clock core's perspective, hw->init is const.
+
+  b) The clock core doesn't see the device_node until __clk_register is
+     called on the first clock.
+
+So the only "race-free" way to detect protected-clocks is to do it in
+the middle of __clk_register, between when core->flags is initialized
+and calling __clk_core_init(). That requires scanning the device tree
+again for each clock, which is part of why I didn't do it that way.
+
+2) __clk_protect needs to be idempotent, for two reasons:
+
+  a) Clocks with CLK_IS_CRITICAL in their init data are already
+     prepared/enabled, and we don't want to prepare/enable them again.
+
+  b) of_clk_set_defaults() is called twice for (at least some) clock
+     controllers registered with CLK_OF_DECLARE. It is called first in
+     of_clk_add_provider()/of_clk_add_hw_provider() inside clk_init_cb,
+     and again afterward in of_clk_init(). The second call in
+     of_clk_init() may be unnecessary, but verifying that would require
+     auditing all users of CLK_OF_DECLARE to ensure they called one of
+     the of_clk_add{,_hw}_provider functions.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/clk-conf.c | 54 ++++++++++++++++++++++++++++++++++++++++++
+ drivers/clk/clk.c      | 31 ++++++++++++++++++++++++
+ drivers/clk/clk.h      |  2 ++
+ 3 files changed, 87 insertions(+)
+
+diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
+index 1a4e6340f95c..3b8e22d453cc 100644
+--- a/drivers/clk/clk-conf.c
++++ b/drivers/clk/clk-conf.c
+@@ -11,6 +11,54 @@
+ #include <linux/of.h>
+ #include <linux/printk.h>
+ 
++#include "clk.h"
++
++static int __set_clk_flags(struct device_node *node)
++{
++	struct of_phandle_args clkspec;
++	struct property *prop;
++	int i, index = 0, rc;
++	const __be32 *cur;
++	struct clk *clk;
++	u32 nr_cells;
++
++	rc = of_property_read_u32(node, "#clock-cells", &nr_cells);
++	if (rc < 0) {
++		pr_err("clk: missing #clock-cells property on %pOF\n", node);
++		return rc;
++	}
++
++	clkspec.np         = node;
++	clkspec.args_count = nr_cells;
++
++	of_property_for_each_u32(node, "protected-clocks", prop, cur, clkspec.args[0]) {
++		/* read the remainder of the clock specifier */
++		for (i = 1; i < nr_cells; ++i) {
++			cur = of_prop_next_u32(prop, cur, &clkspec.args[i]);
++			if (!cur) {
++				pr_err("clk: invalid value of protected-clocks"
++				       " property at %pOF\n", node);
++				return -EINVAL;
++			}
++		}
++		clk = of_clk_get_from_provider(&clkspec);
++		if (IS_ERR(clk)) {
++			if (PTR_ERR(clk) != -EPROBE_DEFER)
++				pr_err("clk: couldn't get protected clock"
++				       " %u for %pOF\n", index, node);
++			return PTR_ERR(clk);
++		}
++
++		rc = __clk_protect(clk);
++		if (rc < 0)
++			pr_warn("clk: failed to protect %s: %d\n",
++				__clk_get_name(clk), rc);
++		clk_put(clk);
++		index++;
++	}
++	return 0;
++}
++
+ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
+ {
+ 	struct of_phandle_args clkspec;
+@@ -143,6 +191,12 @@ int of_clk_set_defaults(struct device_node *node, bool clk_supplier)
+ 	if (!node)
+ 		return 0;
+ 
++	if (clk_supplier) {
++		rc = __set_clk_flags(node);
++		if (rc < 0)
++			return rc;
++	}
++
+ 	rc = __set_clk_parents(node, clk_supplier);
+ 	if (rc < 0)
+ 		return rc;
+diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
+index 8cca52be993f..d6590be526be 100644
+--- a/drivers/clk/clk.c
++++ b/drivers/clk/clk.c
+@@ -4737,6 +4737,37 @@ struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
+ }
+ EXPORT_SYMBOL_GPL(devm_clk_hw_get_clk);
+ 
++/*
++ * clk-conf helpers
++ */
++
++int __clk_protect(struct clk *clk)
++{
++	struct clk_core *core = clk->core;
++	int ret = 0;
++
++	clk_prepare_lock();
++
++	/*
++	 * If CLK_IS_CRITICAL was set in the clock's init data, then
++	 * the clock was already prepared/enabled when it was added.
++	 */
++	if (core->flags & CLK_IS_CRITICAL)
++		goto out;
++
++	core->flags |= CLK_IS_CRITICAL;
++	ret = clk_core_prepare(core);
++	if (ret)
++		goto out;
++
++	ret = clk_core_enable_lock(core);
++
++out:
++	clk_prepare_unlock();
++
++	return ret;
++}
++
+ /*
+  * clkdev helpers
+  */
+diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h
+index 2d801900cad5..367a0f036b13 100644
+--- a/drivers/clk/clk.h
++++ b/drivers/clk/clk.h
+@@ -24,6 +24,7 @@ struct clk_hw *clk_find_hw(const char *dev_id, const char *con_id);
+ #ifdef CONFIG_COMMON_CLK
+ struct clk *clk_hw_create_clk(struct device *dev, struct clk_hw *hw,
+ 			      const char *dev_id, const char *con_id);
++int __clk_protect(struct clk *clk);
+ void __clk_put(struct clk *clk);
+ #else
+ /* All these casts to avoid ifdefs in clkdev... */
+@@ -33,6 +34,7 @@ clk_hw_create_clk(struct device *dev, struct clk_hw *hw, const char *dev_id,
+ {
+ 	return (struct clk *)hw;
+ }
++static inline int __clk_protect(struct clk *clk) { return 0; }
+ static inline void __clk_put(struct clk *clk) { }
+ 
+ #endif
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
new file mode 100644
index 000000000000..953e66915834
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
@@ -0,0 +1,55 @@
+From d6de0e12a24d6a1383e63bdf2be04167785ffef8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 10 Mar 2020 06:04:32 +0100
+Subject: clk: sunxi-ng: Don't use CPU PLL gating and CPUX reparenting to HOSC
+
+It's not necessary when not using dividers on CPU PLL, and it's
+causing cntvct jump backs on H3.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 21 ---------------------
+ 1 file changed, 21 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index da448d659381..5d75d07dec0e 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -1029,20 +1029,6 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
+ 	.num_resets	= ARRAY_SIZE(sun50i_h5_ccu_resets),
+ };
+ 
+-static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
+-	.common	= &pll_cpux_clk.common,
+-	/* copy from pll_cpux_clk */
+-	.enable	= BIT(31),
+-	.lock	= BIT(28),
+-};
+-
+-static struct ccu_mux_nb sun8i_h3_cpu_nb = {
+-	.common		= &cpux_clk.common,
+-	.cm		= &cpux_clk.mux,
+-	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
+-	.bypass_index	= 1, /* index of 24 MHz oscillator */
+-};
+-
+ static int sun8i_h3_ccu_probe(struct platform_device *pdev)
+ {
+ 	const struct sunxi_ccu_desc *desc;
+@@ -1067,13 +1053,6 @@ static int sun8i_h3_ccu_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
+-	/* Gate then ungate PLL CPU after any rate changes */
+-	ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
+-
+-	/* Reparent CPU during PLL CPU rate changes */
+-	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
+-				  &sun8i_h3_cpu_nb);
+-
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
new file mode 100644
index 000000000000..af85db087faf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
@@ -0,0 +1,59 @@
+From 4d42671dc68fd107015327ec103f103445c68bbf Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 3 Apr 2021 17:14:49 -0500
+Subject: clk: sunxi-ng: Export CLK_DRAM for devfreq
+
+MBUS needs to reference the CLK_DRAM clock, as it is responsible for
+DRAM frequency scaling.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-a83t.h      | 4 ----
+ include/dt-bindings/clock/sun8i-a83t-ccu.h | 5 ++---
+ 2 files changed, 2 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
+index 40e575ba51d2..6c927bc75224 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
+@@ -42,12 +42,8 @@
+ 
+ /* module and usb clocks exported */
+ 
+-#define CLK_DRAM		82
+-
+ /* dram gates and more module clocks exported */
+ 
+-#define CLK_MBUS		95
+-
+ /* more module clocks exported */
+ 
+ #define CLK_NUMBER		(CLK_GPU_HYD + 1)
+diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h
+index 78af5085f630..affe1857eb54 100644
+--- a/include/dt-bindings/clock/sun8i-a83t-ccu.h
++++ b/include/dt-bindings/clock/sun8i-a83t-ccu.h
+@@ -116,10 +116,9 @@
+ #define CLK_USB_HSIC		79
+ #define CLK_USB_HSIC_12M	80
+ #define CLK_USB_OHCI0		81
+-
++#define CLK_DRAM		82
+ #define CLK_DRAM_VE		83
+ #define CLK_DRAM_CSI		84
+-
+ #define CLK_TCON0		85
+ #define CLK_TCON1		86
+ #define CLK_CSI_MISC		87
+@@ -130,7 +129,7 @@
+ #define CLK_AVS			92
+ #define CLK_HDMI		93
+ #define CLK_HDMI_SLOW		94
+-
++#define CLK_MBUS		95
+ #define CLK_MIPI_DSI0		96
+ #define CLK_MIPI_DSI1		97
+ #define CLK_GPU_CORE		98
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
new file mode 100644
index 000000000000..e61d93043c86
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
@@ -0,0 +1,59 @@
+From 0383af90296a05bcf76b0dfa9e4fda9356b3e978 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 12 Jan 2017 16:34:57 +0100
+Subject: clk: sunxi-ng: Set maximum P and M factors to 1 for H3 pll-cpux clock
+
+When using M factor greater than 1 system is experiencing
+occasional lockups. P factor should only be used for clock
+speeds below 288MHz. We don't use such speeds in the mainline
+kernel.
+
+This change was verified to fix lockups with PLL stress
+tester available at https://xff.cz/git/arisc-firmware/.
+
+Note that M factor must not be used outside the kernel either,
+so for example u-boot needs a similar patch.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 74274c17efb3..da448d659381 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -25,15 +25,21 @@
+ 
+ #include "ccu-sun8i-h3.h"
+ 
+-static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
+-				     "osc24M", 0x000,
+-				     8, 5,	/* N */
+-				     4, 2,	/* K */
+-				     0, 2,	/* M */
+-				     16, 2,	/* P */
+-				     BIT(31),	/* gate */
+-				     BIT(28),	/* lock */
+-				     CLK_SET_RATE_UNGATE);
++static struct ccu_nkmp pll_cpux_clk = {
++	.enable		= BIT(31),
++	.lock		= BIT(28),
++	.n		= _SUNXI_CCU_MULT(8, 5),
++	.k		= _SUNXI_CCU_MULT(4, 2),
++	.m		= _SUNXI_CCU_DIV_MAX(0, 2, 1),
++	.p		= _SUNXI_CCU_DIV_MAX(16, 2, 1),
++	.common		= {
++		.reg		= 0x000,
++		.hw.init	= CLK_HW_INIT("pll-cpux",
++					      "osc24M",
++					      &ccu_nkmp_ops,
++					      CLK_SET_RATE_UNGATE),
++	},
++};
+ 
+ /*
+  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
new file mode 100644
index 000000000000..9ab4d06bad08
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
@@ -0,0 +1,87 @@
+From ffd20244a1a8df76178fcf9892a3f729667d91b9 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jul 2020 17:10:15 -0500
+Subject: clk: sunxi-ng: a64: Increase PLL_AUDIO base frequency
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 41 +++++++++++++++++++++------
+ 1 file changed, 32 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index 6a4b2b9ef30a..ec9d8126a173 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -47,15 +47,35 @@ static struct ccu_nkmp pll_cpux_clk = {
+  * With sigma-delta modulation for fractional-N on the audio PLL,
+  * we have to use specific dividers. This means the variable divider
+  * can no longer be used, as the audio codec requests the exact clock
+- * rates we support through this mechanism. So we now hard code the
+- * variable divider to 1. This means the clock rates will no longer
+- * match the clock names.
++ * rates we support through this mechanism.
++ *
++ * For the audio codec to work correctly, pll-audio must be exactly
++ * 22579200 Hz or 24576000 Hz, and pll-audio-4x (1x the base) must be
++ * between 3x and 8x that frequency. For the SRC to work at 96 kHz,
++ * pll-audio-4x must be at least 6x pll-audio.
++ *
++ * For now, hard code the variable divider to 3.
+  */
+ #define SUN50I_A64_PLL_AUDIO_REG	0x008
++#define SUN50I_A64_PLL_AUDIO_BIAS_REG	0x224
+ 
+ static struct ccu_sdm_setting pll_audio_sdm_table[] = {
+-	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
+-	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
++	/* 24000000 * (  7 + 0x10d84 / 131072 ) /  8 / 1 - 22579200 == -6.9Hz */
++	{ .rate =  22579200, .pattern = 0xc0010d84, .m =  8, .n =  7 },
++	/* 24000000 * ( 14 + 0x0ac02 / 131072 ) / 14 / 1 - 24576000 == -2.5Hz */
++	{ .rate =  24576000, .pattern = 0xc000ac08, .m = 14, .n = 14 },
++	/* 24000000 * (  8 + 0x0ef35 / 131072 ) /  3 / 3 - 22579200 ==  3.3Hz */
++	{ .rate =  67737600, .pattern = 0xc000ef35, .m =  3, .n =  8 },
++	/* 24000000 * ( 15 + 0x0b852 / 131072 ) /  5 / 3 - 24576000 ==  1.0Hz */
++	{ .rate =  73728000, .pattern = 0xc000b852, .m =  5, .n = 15 },
++	/* 24000000 * (  7 + 0x10d84 / 131072 ) /  2 / 4 - 22579200 == -6.9Hz */
++	{ .rate =  90316800, .pattern = 0xc0010d84, .m =  2, .n =  7 },
++	/* 24000000 * ( 16 + 0x0c49c / 131072 ) /  4 / 4 - 24576000 ==  4.0Hz */
++	{ .rate =  98304000, .pattern = 0xc000c49c, .m =  4, .n = 16 },
++	/* 24000000 * (  5 + 0x14a23 / 131072 ) /  1 / 6 - 22579200 == -6.9Hz */
++	{ .rate = 135475200, .pattern = 0xc0014a23, .m =  1, .n =  5 },
++	/* 24000000 * ( 12 + 0x09375 / 131072 ) /  2 / 6 - 24576000 ==  4.0Hz */
++	{ .rate = 147456000, .pattern = 0xc0009375, .m =  2, .n = 12 },
+ };
+ 
+ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+@@ -608,10 +628,10 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
+ 	&pll_audio_base_clk.common.hw
+ };
+ 
+-/* We hardcode the divider to 1 for now */
++/* We hardcode the divider to 3 for now */
+ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ 			    clk_parent_pll_audio,
+-			    1, 1, CLK_SET_RATE_PARENT);
++			    3, 1, CLK_SET_RATE_PARENT);
+ static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ 			    clk_parent_pll_audio,
+ 			    2, 1, CLK_SET_RATE_PARENT);
+@@ -950,10 +970,13 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	if (IS_ERR(reg))
+ 		return PTR_ERR(reg);
+ 
+-	/* Force the PLL-Audio-1x divider to 1 */
++	/* Force the pll-audio variable divider to 3 */
+ 	val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
+ 	val &= ~GENMASK(19, 16);
+-	writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
++	writel(val | (2 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
++
++	/* Decrease the PLL AUDIO bias current to reduce noise. */
++	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
+ 
+ 	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
new file mode 100644
index 000000000000..83c69b2f7bbf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
@@ -0,0 +1,47 @@
+From 3aea614e81eb22ae9858cd36b884f4b1732f0931 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 14 Aug 2023 07:28:11 +0200
+Subject: clk: sunxi-ng: sun50i-a64: Switch parent of MIPI-DSI to periph0(1x)
+
+This makes video0(1x) clock less constrained, and improves compatibility
+with external monitors on Pinephone when using both internal display
+and HDMI output at once.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index 9ee3cfd0985f..47aed3350d5e 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -960,6 +960,8 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
+ 	.bypass_index	= 1, /* index of 24 MHz oscillator */
+ };
+ 
++#define CCU_MIPI_DSI_CLK 0x168
++
+ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ {
+ 	void __iomem *reg;
+@@ -979,9 +981,15 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
+ 
+ 	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
+-	if (ret)
++	if (ret) {
+ 		writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ 
++		/* Set MIPI-DSI clock parent to periph0(1x), so that video0(1x) is free to change. */
++		val = readl(reg + CCU_MIPI_DSI_CLK);
++		val &= 0x30f;
++		val |= (2 << 8) | ((4 - 1) << 0); /* M-1 */
++		writel(val, reg + CCU_MIPI_DSI_CLK);
++	}
+ 	/* Set PLL MIPI as parent for TCON0 */
+ 	val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
+ 	val &= ~GENMASK(26, 24);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
new file mode 100644
index 000000000000..220ba26512e9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
@@ -0,0 +1,28 @@
+From 52d43d45212f2dde37238c0644c49a73599de3c6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 31 Oct 2019 18:31:32 +0100
+Subject: cpufreq: sun50i: Show detected CPU bin, for easier debugging
+
+Useful for people running into crashes during boot, due to issues
+with OPP voltages.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/cpufreq/sun50i-cpufreq-nvmem.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+index 32a9c88f8ff6..6845ab5034ec 100644
+--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+@@ -102,6 +102,7 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	snprintf(name, MAX_NAME_LEN, "speed%d", speed);
++	pr_info("Using CPU speed bin %s\n", name);
+ 
+ 	for_each_possible_cpu(cpu) {
+ 		struct device *cpu_dev = get_cpu_device(cpu);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
new file mode 100644
index 000000000000..e0f91f0eb4ec
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
@@ -0,0 +1,152 @@
+From 02ffe16c41c8f8be5cce444cf380515ed5648e8b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 1 Sep 2023 00:57:04 +0200
+Subject: drm: bridge: dw-hdmi: Allow to accept HPD status from other drivers
+
+This change allows other drivers to provide HPD status.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 63 +++++++++++++++++++++--
+ 1 file changed, 59 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index cceb5aab6c83..c21657cf599d 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -9,6 +9,7 @@
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/err.h>
++#include <linux/extcon.h>
+ #include <linux/hdmi.h>
+ #include <linux/i2c.h>
+ #include <linux/irq.h>
+@@ -198,6 +199,8 @@ struct dw_hdmi {
+ 	hdmi_codec_plugged_cb plugged_cb;
+ 	struct device *codec_dev;
+ 	enum drm_connector_status last_connector_result;
++	struct extcon_dev *extcon;
++	struct notifier_block extcon_nb;
+ };
+ 
+ #define HDMI_IH_PHY_STAT0_RX_SENSE \
+@@ -1689,6 +1692,12 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
+ enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
+ 					       void *data)
+ {
++	if (hdmi->extcon) {
++		return extcon_get_state(hdmi->extcon, EXTCON_DISP_HDMI) > 0
++			? connector_status_connected
++			: connector_status_disconnected;
++	}
++
+ 	return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
+ 		connector_status_connected : connector_status_disconnected;
+ }
+@@ -1699,7 +1708,7 @@ void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
+ {
+ 	u8 old_mask = hdmi->phy_mask;
+ 
+-	if (force || disabled || !rxsense)
++	if (force || disabled || !rxsense || hdmi->extcon)
+ 		hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
+ 	else
+ 		hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
+@@ -3131,7 +3140,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ 			status = connector_status_disconnected;
+ 	}
+ 
+-	if (status != connector_status_unknown) {
++	if (status != connector_status_unknown && !hdmi->extcon) {
+ 		dev_dbg(hdmi->dev, "EVENT=%s\n",
+ 			status == connector_status_connected ?
+ 			"plugin" : "plugout");
+@@ -3340,6 +3349,25 @@ bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi)
+ }
+ EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420);
+ 
++static int dw_hdmi_extcon_notifier(struct notifier_block *nb,
++				   unsigned long event, void *ptr)
++{
++	struct dw_hdmi *hdmi = container_of(nb, struct dw_hdmi, extcon_nb);
++
++	enum drm_connector_status status = dw_hdmi_phy_read_hpd(hdmi, NULL);
++
++	dev_info(hdmi->dev, "EVENT=%s\n",
++		 status == connector_status_connected ? "plugin" : "plugout");
++
++	if (hdmi->bridge.dev) {
++		//XXX: ???
++		drm_helper_hpd_irq_event(hdmi->bridge.dev);
++		drm_bridge_hpd_notify(&hdmi->bridge, status);
++	}
++
++	return NOTIFY_DONE;
++}
++
+ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
+ 			      const struct dw_hdmi_plat_data *plat_data)
+ {
+@@ -3381,15 +3409,38 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
+ 	if (ret < 0)
+ 		return ERR_PTR(ret);
+ 
++	hdmi->extcon = extcon_get_edev_by_phandle(dev, 0);
++	if (IS_ERR(hdmi->extcon)) {
++		if (PTR_ERR(hdmi->extcon) == -ENODEV) {
++			hdmi->extcon = NULL;
++		} else {
++			if (PTR_ERR(hdmi->extcon) != -EPROBE_DEFER)
++				dev_err(dev, "Invalid or missing extcon\n");
++			return ERR_CAST(hdmi->extcon);
++		}
++	}
++
++	if (hdmi->extcon) {
++		/* don't register IRQ for native HPD */
++		hdmi->phy_mask = (u8)~(HDMI_PHY_RX_SENSE);
++
++		hdmi->extcon_nb.notifier_call = dw_hdmi_extcon_notifier;
++		ret = extcon_register_notifier_all(hdmi->extcon, &hdmi->extcon_nb);
++		if (ret < 0) {
++			dev_err(dev, "failed to register extcon notifier\n");
++			return ERR_PTR(ret);
++		}
++	}
++
+ 	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
+ 	if (ddc_node) {
+ 		hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
+ 		of_node_put(ddc_node);
+ 		if (!hdmi->ddc) {
+ 			dev_dbg(hdmi->dev, "failed to read ddc node\n");
+-			return ERR_PTR(-EPROBE_DEFER);
++			ret = -EPROBE_DEFER;
++			goto err_extcon;
+ 		}
+-
+ 	} else {
+ 		dev_dbg(hdmi->dev, "no ddc property found\n");
+ 	}
+@@ -3633,6 +3684,8 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
+ 	clk_disable_unprepare(hdmi->isfr_clk);
+ err_res:
+ 	i2c_put_adapter(hdmi->ddc);
++err_extcon:
++	extcon_unregister_notifier_all(hdmi->extcon, &hdmi->extcon_nb);
+ 
+ 	return ERR_PTR(ret);
+ }
+@@ -3640,6 +3693,8 @@ EXPORT_SYMBOL_GPL(dw_hdmi_probe);
+ 
+ void dw_hdmi_remove(struct dw_hdmi *hdmi)
+ {
++	extcon_unregister_notifier_all(hdmi->extcon, &hdmi->extcon_nb);
++
+ 	drm_bridge_remove(&hdmi->bridge);
+ 
+ 	if (hdmi->audio && !IS_ERR(hdmi->audio))
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
new file mode 100644
index 000000000000..3cb6c583ede6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
@@ -0,0 +1,41 @@
+From 064dc83861669a8ba03313a5c0f0cbd984177b0c Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 1 Sep 2023 00:59:08 +0200
+Subject: drm: bridge: dw-hdmi: Report HDMI hotplug events
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index c21657cf599d..7b886aeb762f 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -2458,7 +2458,13 @@ static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
+ 	enum drm_connector_status result;
+ 
+ 	result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
+-	hdmi->last_connector_result = result;
++
++	if (result != hdmi->last_connector_result) {
++		dev_info(hdmi->dev, "read_hpd result: %d", result);
++		handle_plugged_change(hdmi,
++				      result == connector_status_connected);
++		hdmi->last_connector_result = result;
++	}
+ 
+ 	return result;
+ }
+@@ -3141,7 +3147,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ 	}
+ 
+ 	if (status != connector_status_unknown && !hdmi->extcon) {
+-		dev_dbg(hdmi->dev, "EVENT=%s\n",
++		dev_info(hdmi->dev, "EVENT=%s\n",
+ 			status == connector_status_connected ?
+ 			"plugin" : "plugout");
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
new file mode 100644
index 000000000000..8b2049963687
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
@@ -0,0 +1,37 @@
+From 15acff209c8f0eeb1c321e7b6677fc0ae217096f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 29 Oct 2020 04:55:40 +0100
+Subject: drm/panel: st7703: Fix xbd599 timings to make refresh rate exactly
+ 60.006Hz
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/panel/panel-sitronix-st7703.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+index a3e142f156d5..6a09607b6144 100644
+--- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+@@ -321,14 +321,14 @@ static int xbd599_init_sequence(struct st7703 *ctx)
+ 
+ static const struct drm_display_mode xbd599_mode = {
+ 	.hdisplay    = 720,
+-	.hsync_start = 720 + 40,
+-	.hsync_end   = 720 + 40 + 40,
+-	.htotal	     = 720 + 40 + 40 + 40,
++	.hsync_start = 720 + 30,
++	.hsync_end   = 720 + 30 + 28,
++	.htotal	     = 720 + 30 + 28 + 30,
+ 	.vdisplay    = 1440,
+ 	.vsync_start = 1440 + 18,
+ 	.vsync_end   = 1440 + 18 + 10,
+ 	.vtotal	     = 1440 + 18 + 10 + 17,
+-	.clock	     = 69000,
++	.clock	     = 72000,
+ 	.flags	     = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ 	.width_mm    = 68,
+ 	.height_mm   = 136,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
new file mode 100644
index 000000000000..df6439e43f89
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
@@ -0,0 +1,36 @@
+From 78d0136c26c7b58722ed641665cd59c89904a89b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 24 Sep 2022 21:54:23 +0200
+Subject: drm: rockchip: Fix panic on reboot when DRM device fails to bind
+
+When DRM device is freed, we need to clear the drvdata pointer, because
+it now points to invalid memory.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+index ab55d7132550..5e2a4c967f83 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+@@ -202,6 +202,7 @@ static int rockchip_drm_bind(struct device *dev)
+ 	component_unbind_all(dev, drm_dev);
+ err_free:
+ 	drm_dev_put(drm_dev);
++	dev_set_drvdata(dev, NULL);
+ 	return ret;
+ }
+ 
+@@ -218,6 +219,7 @@ static void rockchip_drm_unbind(struct device *dev)
+ 	rockchip_iommu_cleanup(drm_dev);
+ 
+ 	drm_dev_put(drm_dev);
++	dev_set_drvdata(dev, NULL);
+ }
+ 
+ DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Add-more-parameters-to-sunxi_engine-commit-callback.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Add-more-parameters-to-sunxi_engine-commit-callback.patch
new file mode 100644
index 000000000000..af217e845d27
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Add-more-parameters-to-sunxi_engine-commit-callback.patch
@@ -0,0 +1,112 @@
+From 0ed34021e2f67952c1538179661ce1be4aa779bd Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 31 Oct 2022 03:01:28 +0100
+Subject: drm/sun4i: Add more parameters to sunxi_engine commit callback
+
+These will be needed later on when we move layer configuration to
+crtc update.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun4i_backend.c |  4 +++-
+ drivers/gpu/drm/sun4i/sun4i_crtc.c    |  2 +-
+ drivers/gpu/drm/sun4i/sun8i_mixer.c   |  5 ++++-
+ drivers/gpu/drm/sun4i/sunxi_engine.h  | 13 ++++++++++---
+ 4 files changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
+index 335fd0edb904..e89eb96d3131 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
++++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
+@@ -69,7 +69,9 @@ static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
+ 			   SUN4I_BACKEND_OCCTL_ENABLE, 0);
+ }
+ 
+-static void sun4i_backend_commit(struct sunxi_engine *engine)
++static void sun4i_backend_commit(struct sunxi_engine *engine,
++				 struct drm_crtc *crtc,
++				 struct drm_atomic_state *state)
+ {
+ 	DRM_DEBUG_DRIVER("Committing changes\n");
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c
+index c06d7cd45388..18e74047b0f5 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
++++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
+@@ -91,7 +91,7 @@ static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc,
+ 
+ 	DRM_DEBUG_DRIVER("Committing plane changes\n");
+ 
+-	sunxi_engine_commit(scrtc->engine);
++	sunxi_engine_commit(scrtc->engine, crtc, state);
+ 
+ 	if (event) {
+ 		crtc->state->event = NULL;
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 1e681314e379..bdeb9b80e038 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -16,6 +16,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/reset.h>
+ 
++#include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_framebuffer.h>
+@@ -249,7 +250,9 @@ int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format)
+ 	return -EINVAL;
+ }
+ 
+-static void sun8i_mixer_commit(struct sunxi_engine *engine)
++static void sun8i_mixer_commit(struct sunxi_engine *engine,
++			       struct drm_crtc *crtc,
++			       struct drm_atomic_state *state)
+ {
+ 	DRM_DEBUG_DRIVER("Committing changes\n");
+ 
+diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h b/drivers/gpu/drm/sun4i/sunxi_engine.h
+index ec8cf9b2bda4..ec0c4932f15c 100644
+--- a/drivers/gpu/drm/sun4i/sunxi_engine.h
++++ b/drivers/gpu/drm/sun4i/sunxi_engine.h
+@@ -7,6 +7,7 @@
+ #define _SUNXI_ENGINE_H_
+ 
+ struct drm_plane;
++struct drm_crtc;
+ struct drm_device;
+ struct drm_crtc_state;
+ struct drm_display_mode;
+@@ -59,7 +60,9 @@ struct sunxi_engine_ops {
+ 	 *
+ 	 * This function is optional.
+ 	 */
+-	void (*commit)(struct sunxi_engine *engine);
++	void (*commit)(struct sunxi_engine *engine,
++		       struct drm_crtc *crtc,
++		       struct drm_atomic_state *state);
+ 
+ 	/**
+ 	 * @layers_init:
+@@ -144,12 +147,16 @@ struct sunxi_engine {
+ /**
+  * sunxi_engine_commit() - commit all changes of the engine
+  * @engine:	pointer to the engine
++ * @crtc:	pointer to crtc the engine is associated with
++ * @state:	atomic state
+  */
+ static inline void
+-sunxi_engine_commit(struct sunxi_engine *engine)
++sunxi_engine_commit(struct sunxi_engine *engine,
++		    struct drm_crtc *crtc,
++		    struct drm_atomic_state *state)
+ {
+ 	if (engine->ops && engine->ops->commit)
+-		engine->ops->commit(engine);
++		engine->ops->commit(engine, crtc, state);
+ }
+ 
+ /**
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Fix-layer-zpos-change-atomic-modesetting.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Fix-layer-zpos-change-atomic-modesetting.patch
new file mode 100644
index 000000000000..cae45d66686e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Fix-layer-zpos-change-atomic-modesetting.patch
@@ -0,0 +1,386 @@
+From 931c9a7d319671b581c99580906a2ab15d7d9518 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 1 Nov 2022 11:49:18 +0100
+Subject: drm/sun4i: Fix layer zpos change/atomic modesetting
+
+Identical configurations of planes can lead to different (and wrong)
+layer -> pipe routing at HW level, depending on the order of atomic
+plane changes.
+
+For example:
+
+- Layer 1 is configured to zpos 0 and thus uses pipe 0. No other layer
+  is enabled. This is a typical situation at boot.
+
+- When a compositor takes over and layer 3 is enabled,
+  sun8i_ui_layer_enable() will get called with old_zpos=0 zpos=1, which
+  will lead to incorrect disabling of pipe 0 and enabling of pipe 1.
+
+What happens is that sun8i_ui_layer_enable() function may disable
+blender pipes even if it is no longer assigned to its layer.
+
+To correct this, move the routing setup out of individual plane's
+atomic_update into crtc's atomic_update, where it can be calculated
+and updated all at once.
+
+Remove the atomic_disable callback because it is no longer needed.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c    | 71 ++++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun8i_mixer.h    |  6 +++
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 73 +------------------------
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 74 +-------------------------
+ 4 files changed, 81 insertions(+), 143 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index bdeb9b80e038..86a38a2f00a7 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -250,12 +250,83 @@ int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format)
+ 	return -EINVAL;
+ }
+ 
++static void sun8i_layer_enable(struct sun8i_layer *layer, bool enable)
++{
++	u32 ch_base = sun8i_channel_base(layer->mixer, layer->channel);
++	u32 val, reg, mask;
++
++	if (layer->type == SUN8I_LAYER_TYPE_UI) {
++		val = enable ? SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN : 0;
++		mask = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
++		reg = SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay);
++	} else {
++		val = enable ? SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN : 0;
++		mask = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
++		reg = SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay);
++	}
++
++	regmap_update_bits(layer->mixer->engine.regs, reg, mask, val);
++}
++
+ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 			       struct drm_crtc *crtc,
+ 			       struct drm_atomic_state *state)
+ {
++	struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
++	u32 bld_base = sun8i_blender_base(mixer);
++	struct drm_plane_state *plane_state;
++	struct drm_plane *plane;
++	u32 route = 0, pipe_en = 0;
++
+ 	DRM_DEBUG_DRIVER("Committing changes\n");
+ 
++	drm_for_each_plane(plane, state->dev) {
++		struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
++		bool enable;
++		int zpos;
++
++		if (!(plane->possible_crtcs & drm_crtc_mask(crtc)) || layer->mixer != mixer)
++			continue;
++
++		plane_state = drm_atomic_get_new_plane_state(state, plane);
++		if (!plane_state)
++			plane_state = plane->state;
++
++		enable = plane_state->crtc && plane_state->visible;
++		zpos = plane_state->normalized_zpos;
++
++		DRM_DEBUG_DRIVER("  plane %d: chan=%d ovl=%d en=%d zpos=%d\n",
++				 plane->base.id, layer->channel, layer->overlay,
++				 enable, zpos);
++
++		/* We always update the layer enable bit, because it can clear
++		 * spontaneously for unknown reasons. */
++		sun8i_layer_enable(layer, enable);
++
++		if (!enable)
++			continue;
++
++		/* Route layer to pipe based on zpos */	
++		route |= layer->channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
++		pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
++	}
++
++	regmap_update_bits(mixer->engine.regs,
++			   SUN8I_MIXER_BLEND_ROUTE(bld_base),
++			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(0) |
++			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(1) |
++			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(2) |
++			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(3),
++			   route);
++
++	regmap_update_bits(mixer->engine.regs,
++			   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(0) |
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(1) |
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(2) |
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(3),
++			   pipe_en);
++
+ 	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
+ 		     SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
+ }
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 5a610ee30301..d7898c9c9cc0 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -186,9 +186,15 @@ struct sun8i_mixer {
+ 	struct clk			*mod_clk;
+ };
+ 
++enum {
++	SUN8I_LAYER_TYPE_UI,
++	SUN8I_LAYER_TYPE_VI,
++};
++
+ struct sun8i_layer {
+ 	struct drm_plane	plane;
+ 	struct sun8i_mixer	*mixer;
++	int			type;
+ 	int			channel;
+ 	int			overlay;
+ };
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index 248fbb606ede..b90e5edef4e8 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -24,55 +24,6 @@
+ #include "sun8i_ui_layer.h"
+ #include "sun8i_ui_scaler.h"
+ 
+-static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
+-				  int overlay, bool enable, unsigned int zpos,
+-				  unsigned int old_zpos)
+-{
+-	u32 val, bld_base, ch_base;
+-
+-	bld_base = sun8i_blender_base(mixer);
+-	ch_base = sun8i_channel_base(mixer, channel);
+-
+-	DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n",
+-			 enable ? "En" : "Dis", channel, overlay);
+-
+-	if (enable)
+-		val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
+-	else
+-		val = 0;
+-
+-	regmap_update_bits(mixer->engine.regs,
+-			   SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
+-			   SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
+-
+-	if (!enable || zpos != old_zpos) {
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+-				   SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
+-				   0);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+-				   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
+-				   0);
+-	}
+-
+-	if (enable) {
+-		val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+-				   val, val);
+-
+-		val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+-				   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
+-				   val);
+-	}
+-}
+-
+ static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
+ 					int overlay, struct drm_plane *plane)
+ {
+@@ -259,36 +210,18 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
+ 						   true, true);
+ }
+ 
+-static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane,
+-					  struct drm_atomic_state *state)
+-{
+-	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+-									   plane);
+-	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+-	unsigned int old_zpos = old_state->normalized_zpos;
+-	struct sun8i_mixer *mixer = layer->mixer;
+-
+-	sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
+-			      old_zpos);
+-}
+ 
+ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
+ 					 struct drm_atomic_state *state)
+ {
+-	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+-									   plane);
+ 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ 									   plane);
+ 	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int zpos = new_state->normalized_zpos;
+-	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+ 
+-	if (!new_state->visible) {
+-		sun8i_ui_layer_enable(mixer, layer->channel,
+-				      layer->overlay, false, 0, old_zpos);
++	if (!new_state->crtc || !new_state->visible)
+ 		return;
+-	}
+ 
+ 	sun8i_ui_layer_update_coord(mixer, layer->channel,
+ 				    layer->overlay, plane, zpos);
+@@ -298,13 +231,10 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
+ 				      layer->overlay, plane);
+ 	sun8i_ui_layer_update_buffer(mixer, layer->channel,
+ 				     layer->overlay, plane);
+-	sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay,
+-			      true, zpos, old_zpos);
+ }
+ 
+ static const struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = {
+ 	.atomic_check	= sun8i_ui_layer_atomic_check,
+-	.atomic_disable	= sun8i_ui_layer_atomic_disable,
+ 	.atomic_update	= sun8i_ui_layer_atomic_update,
+ };
+ 
+@@ -390,6 +320,7 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 
+ 	drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs);
+ 	layer->mixer = mixer;
++	layer->type = SUN8I_LAYER_TYPE_UI;
+ 	layer->channel = channel;
+ 	layer->overlay = 0;
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index 0c0f1ac80517..9c09d9c08496 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -18,55 +18,6 @@
+ #include "sun8i_vi_layer.h"
+ #include "sun8i_vi_scaler.h"
+ 
+-static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
+-				  int overlay, bool enable, unsigned int zpos,
+-				  unsigned int old_zpos)
+-{
+-	u32 val, bld_base, ch_base;
+-
+-	bld_base = sun8i_blender_base(mixer);
+-	ch_base = sun8i_channel_base(mixer, channel);
+-
+-	DRM_DEBUG_DRIVER("%sabling VI channel %d overlay %d\n",
+-			 enable ? "En" : "Dis", channel, overlay);
+-
+-	if (enable)
+-		val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
+-	else
+-		val = 0;
+-
+-	regmap_update_bits(mixer->engine.regs,
+-			   SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
+-			   SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
+-
+-	if (!enable || zpos != old_zpos) {
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+-				   SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
+-				   0);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+-				   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
+-				   0);
+-	}
+-
+-	if (enable) {
+-		val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+-				   val, val);
+-
+-		val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
+-
+-		regmap_update_bits(mixer->engine.regs,
+-				   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+-				   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
+-				   val);
+-	}
+-}
+-
+ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
+ 					int overlay, struct drm_plane *plane)
+ {
+@@ -393,36 +344,17 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
+ 						   true, true);
+ }
+ 
+-static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane,
+-					  struct drm_atomic_state *state)
+-{
+-	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+-									   plane);
+-	struct sun8i_layer *layer = plane_to_sun8i_vi_layer(plane);
+-	unsigned int old_zpos = old_state->normalized_zpos;
+-	struct sun8i_mixer *mixer = layer->mixer;
+-
+-	sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
+-			      old_zpos);
+-}
+-
+ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
+ 					 struct drm_atomic_state *state)
+ {
+-	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+-									   plane);
+ 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ 									   plane);
+ 	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int zpos = new_state->normalized_zpos;
+-	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+ 
+-	if (!new_state->visible) {
+-		sun8i_vi_layer_enable(mixer, layer->channel,
+-				      layer->overlay, false, 0, old_zpos);
++	if (!new_state->crtc || !new_state->visible)
+ 		return;
+-	}
+ 
+ 	sun8i_vi_layer_update_coord(mixer, layer->channel,
+ 				    layer->overlay, plane, zpos);
+@@ -432,13 +364,10 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
+ 				      layer->overlay, plane);
+ 	sun8i_vi_layer_update_buffer(mixer, layer->channel,
+ 				     layer->overlay, plane);
+-	sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay,
+-			      true, zpos, old_zpos);
+ }
+ 
+ static const struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
+ 	.atomic_check	= sun8i_vi_layer_atomic_check,
+-	.atomic_disable	= sun8i_vi_layer_atomic_disable,
+ 	.atomic_update	= sun8i_vi_layer_atomic_update,
+ };
+ 
+@@ -613,6 +542,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 
+ 	drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
+ 	layer->mixer = mixer;
++	layer->type = SUN8I_LAYER_TYPE_VI;
+ 	layer->channel = index;
+ 	layer->overlay = 0;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Implement-gamma-correction.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Implement-gamma-correction.patch
new file mode 100644
index 000000000000..0db5ee263758
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Implement-gamma-correction.patch
@@ -0,0 +1,131 @@
+From bff9b903474ec66bc4173f57eff95152f1d01c62 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Wed, 13 Mar 2019 19:50:17 -0700
+Subject: drm/sun4i: Implement gamma correction
+
+Add support for gamma corretion to sun4i TCON driver. Its LUT has 256
+entries and can be updated only when gamma correction is disabled.
+
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+---
+ drivers/gpu/drm/sun4i/sun4i_crtc.c | 14 +++++++++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 33 ++++++++++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.h | 12 ++++++++++-
+ 3 files changed, 58 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c
+index 18e74047b0f5..a09944a49e89 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
++++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
+@@ -103,6 +103,20 @@ static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc,
+ 			drm_crtc_send_vblank_event(crtc, event);
+ 		spin_unlock_irq(&crtc->dev->event_lock);
+ 	}
++
++	if (crtc->state->color_mgmt_changed) {
++		if (crtc->state->gamma_lut) {
++			/* LUT can be only updated when gamma correction is
++			 * disabled
++			 */
++			sun4i_tcon_enable_gamma(scrtc->tcon, false);
++			sun4i_tcon_load_gamma_lut(scrtc->tcon,
++						  crtc->state->gamma_lut->data);
++			sun4i_tcon_enable_gamma(scrtc->tcon, true);
++		} else
++			sun4i_tcon_enable_gamma(scrtc->tcon, false);
++	}
++
+ }
+ 
+ static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc,
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index b78799dedf62..84f1914afec5 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -240,6 +240,34 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
+ }
+ EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
+ 
++void sun4i_tcon_load_gamma_lut(struct sun4i_tcon *tcon,
++			       struct drm_color_lut *lut)
++{
++	int i;
++
++	for (i = 0; i < SUN4I_TCON_GAMMA_LUT_SIZE; i++) {
++		u32 r, g, b;
++
++		r = drm_color_lut_extract(lut[i].red, 8);
++		g = drm_color_lut_extract(lut[i].green, 8);
++		b = drm_color_lut_extract(lut[i].blue, 8);
++
++		regmap_write(tcon->regs, SUN4I_TCON_GAMMA_TABLE_REG + 4 * i,
++			     SUN4I_TCON_GAMMA_TABLE_R(r) |
++			     SUN4I_TCON_GAMMA_TABLE_G(g) |
++			     SUN4I_TCON_GAMMA_TABLE_B(b));
++	}
++}
++EXPORT_SYMBOL(sun4i_tcon_load_gamma_lut);
++
++void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable)
++{
++	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
++			   SUN4I_TCON_GCTL_GAMMA_ENABLE,
++			   enable ? SUN4I_TCON_GCTL_GAMMA_ENABLE : 0);
++}
++EXPORT_SYMBOL(sun4i_tcon_enable_gamma);
++
+ /*
+  * This function is a helper for TCON output muxing. The TCON output
+  * muxing control register in earlier SoCs (without the TCON TOP block)
+@@ -1288,6 +1316,11 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 
+ 	list_add_tail(&tcon->list, &drv->tcon_list);
+ 
++	drm_mode_crtc_set_gamma_size(&tcon->crtc->crtc,
++				     SUN4I_TCON_GAMMA_LUT_SIZE);
++	drm_crtc_enable_color_mgmt(&tcon->crtc->crtc, 0, false,
++				   tcon->crtc->crtc.gamma_size);
++
+ 	return 0;
+ 
+ err_free_dclk:
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index fa23aa23fe4a..97df39db2a31 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -19,6 +19,7 @@
+ 
+ #define SUN4I_TCON_GCTL_REG			0x0
+ #define SUN4I_TCON_GCTL_TCON_ENABLE			BIT(31)
++#define SUN4I_TCON_GCTL_GAMMA_ENABLE			BIT(30)
+ #define SUN4I_TCON_GCTL_IOMAP_MASK			BIT(0)
+ #define SUN4I_TCON_GCTL_IOMAP_TCON1			(1 << 0)
+ #define SUN4I_TCON_GCTL_IOMAP_TCON0			(0 << 0)
+@@ -229,7 +230,13 @@
+ #define SUN4I_TCON1_FILL_BEG2_REG		0x31c
+ #define SUN4I_TCON1_FILL_END2_REG		0x320
+ #define SUN4I_TCON1_FILL_DATA2_REG		0x324
+-#define SUN4I_TCON1_GAMMA_TABLE_REG		0x400
++
++#define SUN4I_TCON_GAMMA_TABLE_REG		0x400
++#define SUN4I_TCON_GAMMA_TABLE_B(x)		((x) & 0xff)
++#define SUN4I_TCON_GAMMA_TABLE_G(x)		(((x) & 0xff) << 8)
++#define SUN4I_TCON_GAMMA_TABLE_R(x)		(((x) & 0xff) << 16)
++
++#define SUN4I_TCON_GAMMA_LUT_SIZE		256
+ 
+ #define SUN4I_TCON_MAX_CHANNELS		2
+ 
+@@ -297,6 +304,9 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
+ 			 const struct drm_display_mode *mode);
+ void sun4i_tcon_set_status(struct sun4i_tcon *crtc,
+ 			   const struct drm_encoder *encoder, bool enable);
++void sun4i_tcon_load_gamma_lut(struct sun4i_tcon *tcon,
++			       struct drm_color_lut *lut);
++void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable);
+ 
+ extern const struct of_device_id sun4i_tcon_of_table[];
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
new file mode 100644
index 000000000000..b40178d9444e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
@@ -0,0 +1,73 @@
+From 1c16ff8c45e2d05069887d7062a537dc22adcf51 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 31 Oct 2022 03:23:11 +0100
+Subject: drm/sun4i: Mark one of the UI planes as a cursor one
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c    | 7 ++++++-
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 7 ++-----
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 4 +++-
+ 3 files changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 542c86f66b3a..15fe48794983 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -347,8 +347,13 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
+ 
+ 	for (i = 0; i < mixer->cfg->ui_num; i++) {
+ 		struct sun8i_layer *layer;
++		enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
++		if (i == 0)
++			type = DRM_PLANE_TYPE_PRIMARY;
++		else if (i == (mixer->cfg->ui_num - 1))
++			type = DRM_PLANE_TYPE_CURSOR;
+ 
+-		layer = sun8i_ui_layer_init_one(drm, mixer, i);
++		layer = sun8i_ui_layer_init_one(drm, mixer, i, type);
+ 		if (IS_ERR(layer)) {
+ 			dev_err(drm->dev, "Couldn't initialize %s plane\n",
+ 				i ? "overlay" : "primary");
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index b90e5edef4e8..0349e8bdffd6 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -277,9 +277,9 @@ static const uint64_t sun8i_layer_modifiers[] = {
+ 
+ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 					    struct sun8i_mixer *mixer,
+-					    int index)
++					    int index,
++					    enum drm_plane_type type)
+ {
+-	enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
+ 	int channel = mixer->cfg->vi_num + index;
+ 	struct sun8i_layer *layer;
+ 	unsigned int plane_cnt;
+@@ -289,9 +289,6 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 	if (!layer)
+ 		return ERR_PTR(-ENOMEM);
+ 
+-	if (index == 0)
+-		type = DRM_PLANE_TYPE_PRIMARY;
+-
+ 	/* possible crtcs are set later */
+ 	ret = drm_universal_plane_init(drm, &layer->plane, 0,
+ 				       &sun8i_ui_layer_funcs,
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+index 83892f6ff211..d4530e9f64e0 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+@@ -51,5 +51,7 @@ struct sun8i_layer;
+ 
+ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 					    struct sun8i_mixer *mixer,
+-					    int index);
++					    int index,
++					    enum drm_plane_type type);
++
+ #endif /* _SUN8I_UI_LAYER_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
new file mode 100644
index 000000000000..de7cc8106cd4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
@@ -0,0 +1,547 @@
+From ce89d4736715633704879cf7bc3ffbb9cc1fc576 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 30 Apr 2023 18:19:16 +0200
+Subject: drm/sun4i: Support taking over display pipeline state from p-boot
+
+For perfect, flickerless and fast boot.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c         |  4 +-
+ drivers/gpu/drm/drm_fbdev_generic.c           | 14 +++++
+ drivers/gpu/drm/panel/panel-sitronix-st7703.c | 17 ++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.c            | 23 ++++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.h            |  2 +
+ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c        | 13 +++++
+ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h        |  2 +
+ drivers/gpu/drm/sun4i/sun8i_mixer.c           | 52 +++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun8i_mixer.h           |  3 ++
+ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c   | 14 +++++
+ drivers/video/backlight/pwm_bl.c              | 25 ++++++++-
+ 11 files changed, 167 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index ec9d8126a173..e354cfaa0aef 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -978,7 +978,9 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	/* Decrease the PLL AUDIO bias current to reduce noise. */
+ 	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
+ 
+-	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
++	if (ret)
++		writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ 
+ 	/* Set PLL MIPI as parent for TCON0 */
+ 	val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
+diff --git a/drivers/gpu/drm/drm_fbdev_generic.c b/drivers/gpu/drm/drm_fbdev_generic.c
+index cbb7418b789f..cb6c42c10d47 100644
+--- a/drivers/gpu/drm/drm_fbdev_generic.c
++++ b/drivers/gpu/drm/drm_fbdev_generic.c
+@@ -78,6 +78,7 @@ static int drm_fbdev_generic_helper_fb_probe(struct drm_fb_helper *fb_helper,
+ 	size_t screen_size;
+ 	void *screen_buffer;
+ 	u32 format;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	drm_dbg_kms(dev, "surface width(%d), height(%d) and bpp(%d)\n",
+@@ -125,6 +126,19 @@ static int drm_fbdev_generic_helper_fb_probe(struct drm_fb_helper *fb_helper,
+ 	if (ret)
+ 		goto err_drm_fb_helper_release_info;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		// copy framebuffer contents from p-boot if reasonable
++		if (screen_size != 720 * 1440 * 4) {
++			drm_err(dev, "surface width(%d), height(%d) and bpp(%d) does not match p-boot requirements\n",
++				    sizes->surface_width, sizes->surface_height,
++				    sizes->surface_bpp);
++			return 0;
++		}
++
++		memcpy(screen_buffer, __va(fb_start), screen_size);
++	}
++
+ 	return 0;
+ 
+ err_drm_fb_helper_release_info:
+diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+index 6a09607b6144..c63a9b8c599d 100644
+--- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+@@ -63,6 +63,7 @@ struct st7703 {
+ 	struct dentry *debugfs;
+ 	const struct st7703_panel_desc *desc;
+ 	enum drm_panel_orientation orientation;
++	bool hw_preenabled;
+ };
+ 
+ struct st7703_panel_desc {
+@@ -618,6 +619,11 @@ static int st7703_enable(struct drm_panel *panel)
+ 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ 	int ret;
+ 
++	if (ctx->hw_preenabled) {
++		ctx->hw_preenabled = false;
++		return 0;
++	}
++
+ 	ret = ctx->desc->init_sequence(ctx);
+ 	if (ret < 0) {
+ 		dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
+@@ -685,8 +691,10 @@ static int st7703_prepare(struct drm_panel *panel)
+ 	if (ctx->prepared)
+ 		return 0;
+ 
++	if (!ctx->hw_preenabled) {
+ 	dev_dbg(ctx->dev, "Resetting the panel\n");
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
++	}
+ 
+ 	ret = regulator_enable(ctx->iovcc);
+ 	if (ret < 0) {
+@@ -702,10 +710,12 @@ static int st7703_prepare(struct drm_panel *panel)
+ 	}
+ 
+ 	/* Give power supplies time to stabilize before deasserting reset. */
++	if (!ctx->hw_preenabled) {
+ 	usleep_range(10000, 20000);
+ 
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ 	usleep_range(15000, 20000);
++	}
+ 
+ 	ctx->prepared = true;
+ 
+@@ -798,12 +808,19 @@ static int st7703_probe(struct mipi_dsi_device *dsi)
+ {
+ 	struct device *dev = &dsi->dev;
+ 	struct st7703 *ctx;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+ 	if (!ctx)
+ 		return -ENOMEM;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		ctx->hw_preenabled = true;
++	}
++
+ 	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ 	if (IS_ERR(ctx->reset_gpio))
+ 		return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "Failed to get reset gpio\n");
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index 84f1914afec5..4a3ba9082b4c 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -40,6 +40,8 @@
+ #include "sun8i_tcon_top.h"
+ #include "sunxi_engine.h"
+ 
++static bool hw_preconfigured;
++
+ static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
+ {
+ 	struct drm_connector *connector;
+@@ -743,6 +745,13 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
+ 			 const struct drm_encoder *encoder,
+ 			 const struct drm_display_mode *mode)
+ {
++	if (tcon->hw_preconfigured) {
++		// avoid the first modeset
++		tcon->hw_preconfigured = false;
++		hw_preconfigured = false;
++		return;
++	}
++
+ 	switch (encoder->encoder_type) {
+ 	case DRM_MODE_ENCODER_DSI:
+ 		/* DSI is tied to special case of CPU interface */
+@@ -883,6 +892,7 @@ static int sun4i_tcon_init_regmap(struct device *dev,
+ 		return PTR_ERR(tcon->regs);
+ 	}
+ 
++	if (!tcon->hw_preconfigured) {
+ 	/* Make sure the TCON is disabled and all IRQs are off */
+ 	regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
+ 	regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
+@@ -891,6 +901,7 @@ static int sun4i_tcon_init_regmap(struct device *dev,
+ 	/* Disable IO lines and set them to tristate */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
+ 	regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
++	}
+ 
+ 	return 0;
+ }
+@@ -1162,6 +1173,9 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 	tcon->dev = dev;
+ 	tcon->id = engine->id;
+ 	tcon->quirks = of_device_get_match_data(dev);
++	
++	if (tcon->id == 0)
++		tcon->hw_preconfigured = hw_preconfigured;
+ 
+ 	tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
+ 	if (IS_ERR(tcon->lcd_rst)) {
+@@ -1183,12 +1197,14 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 		}
+ 	}
+ 
++	if (!tcon->hw_preconfigured) {
+ 	/* Make sure our TCON is reset */
+ 	ret = reset_control_reset(tcon->lcd_rst);
+ 	if (ret) {
+ 		dev_err(dev, "Couldn't deassert our reset line\n");
+ 		return ret;
+ 	}
++	}
+ 
+ 	if (tcon->quirks->supports_lvds) {
+ 		/*
+@@ -1352,8 +1368,15 @@ static int sun4i_tcon_probe(struct platform_device *pdev)
+ 	const struct sun4i_tcon_quirks *quirks;
+ 	struct drm_bridge *bridge;
+ 	struct drm_panel *panel;
++	u32 fb_start;
+ 	int ret;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		hw_preconfigured = true;
++	}
++
+ 	quirks = of_device_get_match_data(&pdev->dev);
+ 
+ 	/* panels and bridges are present only on TCONs with channel 0 */
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index 97df39db2a31..864d70b9d242 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -293,6 +293,8 @@ struct sun4i_tcon {
+ 
+ 	/* TCON list management */
+ 	struct list_head		list;
++
++	bool hw_preconfigured;
+ };
+ 
+ struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
+diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+index 4abf4f102007..62926a19388c 100644
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+@@ -732,6 +732,7 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	reset_control_deassert(dsi->reset);
+ 	clk_prepare_enable(dsi->mod_clk);
+ 
++	if (!dsi->hw_preconfigured) {
+ 	/*
+ 	 * Enable the DSI block.
+ 	 */
+@@ -758,6 +759,7 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	sun6i_dsi_setup_inst_loop(dsi, mode);
+ 	sun6i_dsi_setup_format(dsi, mode);
+ 	sun6i_dsi_setup_timings(dsi, mode);
++	}
+ 
+ 	phy_init(dsi->dphy);
+ 
+@@ -787,11 +789,15 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	if (dsi->panel)
+ 		drm_panel_enable(dsi->panel);
+ 
++	if (!dsi->hw_preconfigured) {
+ 	sun6i_dsi_start(dsi, DSI_START_HSC);
+ 
+ 	udelay(1000);
+ 
+ 	sun6i_dsi_start(dsi, DSI_START_HSD);
++	}
++
++	dsi->hw_preconfigured = false;
+ }
+ 
+ static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
+@@ -1105,6 +1111,7 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct sun6i_dsi *dsi;
+ 	void __iomem *base;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	variant = device_get_match_data(dev);
+@@ -1120,6 +1127,12 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
+ 	dsi->host.dev = dev;
+ 	dsi->variant = variant;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		dsi->hw_preconfigured = true;
++	}
++
+ 	base = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(base)) {
+ 		dev_err(dev, "Couldn't map the DSI encoder registers\n");
+diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+index f1ddefe0f554..958c2997ab43 100644
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+@@ -38,6 +38,8 @@ struct sun6i_dsi {
+ 	struct drm_panel	*panel;
+ 
+ 	const struct sun6i_dsi_variant *variant;
++	
++	bool hw_preconfigured;
+ };
+ 
+ static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 15fe48794983..eb55798c200d 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -24,6 +24,7 @@
+ #include <drm/drm_probe_helper.h>
+ 
+ #include "sun4i_drv.h"
++#include "sun4i_tcon.h"
+ #include "sun8i_mixer.h"
+ #include "sun8i_ui_layer.h"
+ #include "sun8i_vi_layer.h"
+@@ -34,6 +35,8 @@ struct de2_fmt_info {
+ 	u32	de2_fmt;
+ };
+ 
++static bool hw_preconfigured;
++
+ static const struct de2_fmt_info de2_formats[] = {
+ 	{
+ 		.drm_fmt = DRM_FORMAT_ARGB8888,
+@@ -278,6 +281,33 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 	struct drm_plane *plane;
+ 	u32 route = 0, pipe_en = 0;
+ 
++	if (mixer->hw_preconfigured && engine->id == 0) {
++		struct sun4i_tcon* tcon;
++		u32 val, saved, ret;
++
++		/*
++		 * This is the first commit, wait for vblank on tcon0 before continuing.
++		 */
++		list_for_each_entry(tcon, &mixer->drv->tcon_list, list) {
++			if (tcon->id == 0) {
++				regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &saved);
++				saved &= 0xffff0000;
++
++				regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
++
++				ret = regmap_read_poll_timeout(tcon->regs, SUN4I_TCON_GINT0_REG, val,
++							 val & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
++								SUN4I_TCON_GINT0_VBLANK_INT(1) |
++								SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT),
++							 100, 40000);
++
++				regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, saved);
++			}
++		}
++
++		mixer->hw_preconfigured = false;
++	}
++
+ 	DRM_DEBUG_DRIVER("Committing changes\n");
+ 
+ 	drm_for_each_plane(plane, state->dev) {
+@@ -459,6 +489,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	dev_set_drvdata(dev, mixer);
+ 	mixer->engine.ops = &sun8i_engine_ops;
+ 	mixer->engine.node = dev->of_node;
++	mixer->drv = drv;
+ 
+ 	if (of_property_present(dev->of_node, "iommus")) {
+ 		/*
+@@ -483,6 +514,11 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	 */
+ 	mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node);
+ 
++	if (mixer->engine.id == 0) {
++		mixer->hw_preconfigured = hw_preconfigured;
++		hw_preconfigured = false;
++	}
++
+ 	mixer->cfg = of_device_get_match_data(dev);
+ 	if (!mixer->cfg)
+ 		return -EINVAL;
+@@ -530,8 +566,11 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	 * reason for the mixer to be functional. Make sure it's the
+ 	 * case.
+ 	 */
++
++	if (!mixer->hw_preconfigured) {
+ 	if (mixer->cfg->mod_rate)
+ 		clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate);
++	}
+ 
+ 	clk_prepare_enable(mixer->mod_clk);
+ 
+@@ -539,6 +578,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 
+ 	base = sun8i_blender_base(mixer);
+ 
++	if (!mixer->hw_preconfigured) {
+ 	/* Reset registers and disable unused sub-engines */
+ 	if (mixer->cfg->is_de3) {
+ 		for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
+@@ -570,6 +610,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	/* Enable the mixer */
+ 	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
+ 		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
++	} /* hw_preconfigured */
+ 
+ 	/* Set background color to black */
+ 	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
+@@ -590,8 +631,10 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 			     SUN8I_MIXER_BLEND_MODE(base, i),
+ 			     SUN8I_MIXER_BLEND_MODE_DEF);
+ 
++	if (!mixer->hw_preconfigured) {
+ 	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+ 			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
++	}
+ 
+ 	return 0;
+ 
+@@ -621,6 +664,15 @@ static const struct component_ops sun8i_mixer_ops = {
+ 
+ static int sun8i_mixer_probe(struct platform_device *pdev)
+ {
++	int ret;
++	u32 fb_start;
++
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		hw_preconfigured = true;
++	}
++
+ 	return component_add(&pdev->dev, &sun8i_mixer_ops);
+ }
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index d7898c9c9cc0..68e2741b0962 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -184,6 +184,9 @@ struct sun8i_mixer {
+ 
+ 	struct clk			*bus_clk;
+ 	struct clk			*mod_clk;
++
++	struct sun4i_drv		*drv;
++	bool				hw_preconfigured;
+ };
+ 
+ enum {
+diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+index 36eab95271b2..a19a27cea860 100644
+--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
++++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+@@ -195,6 +195,8 @@ struct sun6i_dphy {
+ 
+ 	const struct sun6i_dphy_variant		*variant;
+ 	enum sun6i_dphy_direction		direction;
++
++	bool hw_preconfigured;
+ };
+ 
+ static int sun6i_dphy_init(struct phy *phy)
+@@ -226,6 +228,11 @@ static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
+ {
+ 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
+ 
++	if (dphy->hw_preconfigured) {
++		dphy->hw_preconfigured = false;
++		return;
++	}
++
+ 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
+ 		     SUN6I_DPHY_ANA0_REG_PWS |
+ 		     SUN6I_DPHY_ANA0_REG_DMPC |
+@@ -551,6 +558,7 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
+ 	struct sun6i_dphy *dphy;
+ 	const char *direction;
+ 	void __iomem *regs;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
+@@ -561,6 +569,12 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
+ 	if (!dphy->variant)
+ 		return -EINVAL;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		dphy->hw_preconfigured = true;
++	}
++
+ 	regs = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(regs)) {
+ 		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
+diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
+index ffcebf6aa76a..aea5227e3fc0 100644
+--- a/drivers/video/backlight/pwm_bl.c
++++ b/drivers/video/backlight/pwm_bl.c
+@@ -455,7 +455,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	struct backlight_properties props;
+ 	struct backlight_device *bl;
+ 	struct pwm_bl_data *pb;
+-	struct pwm_state state;
++	struct pwm_state state, state_real;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -521,6 +521,11 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	/* Sync up PWM state. */
+ 	pwm_init_state(pb->pwm, &state);
+ 
++	/* Read real state, but only if the PWM is enabled. */
++	pwm_get_state(pb->pwm, &state_real);
++	if (state_real.enabled)
++		state = state_real;
++
+ 	/*
+ 	 * The DT case will set the pwm_period_ns field to 0 and store the
+ 	 * period, parsed from the DT, in the PWM device. For the non-DT case,
+@@ -613,6 +618,24 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 
+ 	bl->props.brightness = data->dft_brightness;
+ 	bl->props.power = pwm_backlight_initial_power_state(pb);
++	if (bl->props.power == FB_BLANK_UNBLANK && pb->levels) {
++		u64 level;
++
++		/* If the backlight is already on, determine the default
++		 * brightness from PWM duty cycle instead of forcing
++		 * the brightness determined by the driver 
++		 */
++		pwm_get_state(pb->pwm, &state);
++		level = (u64)state.duty_cycle * pb->scale;
++		do_div(level, (u64)state.period);
++
++		for (i = 0; i <= data->max_brightness; i++) {
++			if (data->levels[i] > level) {
++				bl->props.brightness = i;
++				break;
++			}
++		}
++	}
+ 	backlight_update_status(bl);
+ 
+ 	platform_set_drvdata(pdev, bl);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Unify-sun8i_-_layer-structs.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Unify-sun8i_-_layer-structs.patch
new file mode 100644
index 000000000000..b381b2e7e822
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-Unify-sun8i_-_layer-structs.patch
@@ -0,0 +1,236 @@
+From a68a389953ec99b2cd8075ed6ddf316448d8ced5 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 31 Oct 2022 03:19:07 +0100
+Subject: drm/sun4i: Unify sun8i_*_layer structs
+
+These structs are identical, use a single struct to represent private
+data for the DRM plane. This is a preparation for configuring layer
+routing from the CRTC (mixer) instead of current approach of setting
+up routing from individual layer's atomic_update callback.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c    |  4 ++--
+ drivers/gpu/drm/sun4i/sun8i_mixer.h    | 14 ++++++++++++++
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 14 +++++++-------
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 20 ++++----------------
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 14 +++++++-------
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 20 ++++----------------
+ 6 files changed, 38 insertions(+), 48 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 01382860aaee..1e681314e379 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -271,7 +271,7 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	for (i = 0; i < mixer->cfg->vi_num; i++) {
+-		struct sun8i_vi_layer *layer;
++		struct sun8i_layer *layer;
+ 
+ 		layer = sun8i_vi_layer_init_one(drm, mixer, i);
+ 		if (IS_ERR(layer)) {
+@@ -284,7 +284,7 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
+ 	}
+ 
+ 	for (i = 0; i < mixer->cfg->ui_num; i++) {
+-		struct sun8i_ui_layer *layer;
++		struct sun8i_layer *layer;
+ 
+ 		layer = sun8i_ui_layer_init_one(drm, mixer, i);
+ 		if (IS_ERR(layer)) {
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 85c94884fb9a..5a610ee30301 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -9,6 +9,7 @@
+ #include <linux/clk.h>
+ #include <linux/regmap.h>
+ #include <linux/reset.h>
++#include <drm/drm_plane.h>
+ 
+ #include "sunxi_engine.h"
+ 
+@@ -185,6 +186,19 @@ struct sun8i_mixer {
+ 	struct clk			*mod_clk;
+ };
+ 
++struct sun8i_layer {
++	struct drm_plane	plane;
++	struct sun8i_mixer	*mixer;
++	int			channel;
++	int			overlay;
++};
++
++static inline struct sun8i_layer *
++plane_to_sun8i_layer(struct drm_plane *plane)
++{
++	return container_of(plane, struct sun8i_layer, plane);
++}
++
+ static inline struct sun8i_mixer *
+ engine_to_sun8i_mixer(struct sunxi_engine *engine)
+ {
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index ca75ca0835a6..248fbb606ede 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -232,7 +232,7 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
+ {
+ 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
+ 										 plane);
+-	struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	struct drm_crtc *crtc = new_plane_state->crtc;
+ 	struct drm_crtc_state *crtc_state;
+ 	int min_scale, max_scale;
+@@ -264,7 +264,7 @@ static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane,
+ {
+ 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+ 									   plane);
+-	struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+ 
+@@ -279,7 +279,7 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
+ 									   plane);
+ 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ 									   plane);
+-	struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int zpos = new_state->normalized_zpos;
+ 	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+@@ -345,13 +345,13 @@ static const uint64_t sun8i_layer_modifiers[] = {
+ 	DRM_FORMAT_MOD_INVALID
+ };
+ 
+-struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+-					       struct sun8i_mixer *mixer,
+-					       int index)
++struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
++					    struct sun8i_mixer *mixer,
++					    int index)
+ {
+ 	enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
+ 	int channel = mixer->cfg->vi_num + index;
+-	struct sun8i_ui_layer *layer;
++	struct sun8i_layer *layer;
+ 	unsigned int plane_cnt;
+ 	int ret;
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+index e3e32ee1178d..83892f6ff211 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+@@ -47,21 +47,9 @@
+ #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_COMBINED	((2) << 1)
+ 
+ struct sun8i_mixer;
++struct sun8i_layer;
+ 
+-struct sun8i_ui_layer {
+-	struct drm_plane	plane;
+-	struct sun8i_mixer	*mixer;
+-	int			channel;
+-	int			overlay;
+-};
+-
+-static inline struct sun8i_ui_layer *
+-plane_to_sun8i_ui_layer(struct drm_plane *plane)
+-{
+-	return container_of(plane, struct sun8i_ui_layer, plane);
+-}
+-
+-struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+-					       struct sun8i_mixer *mixer,
+-					       int index);
++struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
++					    struct sun8i_mixer *mixer,
++					    int index);
+ #endif /* _SUN8I_UI_LAYER_H_ */
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index f9c0a56d3a14..0c0f1ac80517 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -366,7 +366,7 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
+ {
+ 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
+ 										 plane);
+-	struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	struct drm_crtc *crtc = new_plane_state->crtc;
+ 	struct drm_crtc_state *crtc_state;
+ 	int min_scale, max_scale;
+@@ -398,7 +398,7 @@ static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane,
+ {
+ 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+ 									   plane);
+-	struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_vi_layer(plane);
+ 	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+ 
+@@ -413,7 +413,7 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
+ 									   plane);
+ 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ 									   plane);
+-	struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int zpos = new_state->normalized_zpos;
+ 	unsigned int old_zpos = old_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
+@@ -539,14 +539,14 @@ static const uint64_t sun8i_layer_modifiers[] = {
+ 	DRM_FORMAT_MOD_INVALID
+ };
+ 
+-struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+-					       struct sun8i_mixer *mixer,
+-					       int index)
++struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
++					    struct sun8i_mixer *mixer,
++					    int index)
+ {
+ 	enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
+ 	u32 supported_encodings, supported_ranges;
+ 	unsigned int plane_cnt, format_count;
+-	struct sun8i_vi_layer *layer;
++	struct sun8i_layer *layer;
+ 	const u32 *formats;
+ 	int ret;
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
+index 48c399e1c86d..655440cdc78f 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
+@@ -52,21 +52,9 @@
+ #define SUN8I_MIXER_CHAN_VI_DS_M(x)			((x) << 0)
+ 
+ struct sun8i_mixer;
++struct sun8i_layer;
+ 
+-struct sun8i_vi_layer {
+-	struct drm_plane	plane;
+-	struct sun8i_mixer	*mixer;
+-	int			channel;
+-	int			overlay;
+-};
+-
+-static inline struct sun8i_vi_layer *
+-plane_to_sun8i_vi_layer(struct drm_plane *plane)
+-{
+-	return container_of(plane, struct sun8i_vi_layer, plane);
+-}
+-
+-struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+-					       struct sun8i_mixer *mixer,
+-					       int index);
++struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
++					    struct sun8i_mixer *mixer,
++					    int index);
+ #endif /* _SUN8I_VI_LAYER_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-drm-Change-update_bits-to-write.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-drm-Change-update_bits-to-write.patch
new file mode 100644
index 000000000000..e596c9e1bc3c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-drm-Change-update_bits-to-write.patch
@@ -0,0 +1,42 @@
+From ae99a1a4ffa4717d0297d896f84bf20023d20ad5 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 24 Feb 2024 14:36:36 +0100
+Subject: drm: sun4i-drm: Change update_bits to write
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 +++---------------
+ 1 file changed, 3 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 86a38a2f00a7..542c86f66b3a 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -311,21 +311,9 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 		pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
+ 	}
+ 
+-	regmap_update_bits(mixer->engine.regs,
+-			   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+-			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(0) |
+-			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(1) |
+-			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(2) |
+-			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(3),
+-			   route);
+-
+-	regmap_update_bits(mixer->engine.regs,
+-			   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(0) |
+-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(1) |
+-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(2) |
+-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(3),
+-			   pipe_en);
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route);
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
++		     pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
+ 
+ 	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
+ 		     SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
new file mode 100644
index 000000000000..94b5c48ab420
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
@@ -0,0 +1,179 @@
+From f64465350b948fc70abc36be3ff8613a7fbd8c68 Mon Sep 17 00:00:00 2001
+From: Frank Oltmanns <frank@oltmanns.dev>
+Date: Sun, 10 Mar 2024 14:32:29 +0100
+Subject: drm/sun4i: tcon: Support keeping dclk rate upon ancestor clock
+ changes
+
+Allow the dclk to reset its rate when a rate change is initiated from an
+ancestor clock. This makes it possible to no longer to get an exclusive
+lock. As a consequence, it is now possible to set new rates if
+necessary, e.g. when an external display is connected.
+
+The first user of this functionality is the A64 because PLL-VIDEO0 is an
+ancestor for both HDMI and TCON0. This allows to select an optimal rate
+for TCON0 as long as there is no external HDMI connection. Once a change
+in PLL-VIDEO0 is performed when an HDMI connection is established, TCON0
+can react gracefully and select an optimal rate based on this the new
+constraint.
+
+Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
+---
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 70 +++++++++++++++++++++++++++---
+ drivers/gpu/drm/sun4i/sun4i_tcon.h | 12 +++++
+ 2 files changed, 76 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index 4a3ba9082b4c..654df088f2de 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -110,9 +110,11 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
+ 
+ 	if (enabled) {
+ 		clk_prepare_enable(clk);
+-		clk_rate_exclusive_get(clk);
++		if (!tcon->quirks->restores_rate)
++			clk_rate_exclusive_get(clk);
+ 	} else {
+-		clk_rate_exclusive_put(clk);
++		if (!tcon->quirks->restores_rate)
++			clk_rate_exclusive_put(clk);
+ 		clk_disable_unprepare(clk);
+ 	}
+ }
+@@ -373,6 +375,53 @@ static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
+ 	regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
+ }
+ 
++static void sun4i_rate_reset_notifier_delayed_update(struct work_struct *work)
++{
++	struct sun4i_rate_reset_nb *rate_reset = container_of(work, struct sun4i_rate_reset_nb,
++							    reset_rate_work.work);
++
++	clk_set_rate(rate_reset->target_clk, rate_reset->saved_rate);
++}
++
++static int sun4i_rate_reset_notifier_cb(struct notifier_block *nb,
++				      unsigned long event, void *data)
++{
++	struct sun4i_rate_reset_nb *rate_reset = to_sun4i_rate_reset_nb(nb);
++
++	if (event == POST_RATE_CHANGE)
++		mod_delayed_work(system_wq, &rate_reset->reset_rate_work, msecs_to_jiffies(100));
++
++	return NOTIFY_DONE;
++}
++
++static void sun4i_rate_reset_notifier_register(struct sun4i_rate_reset_nb *rate_reset_nb)
++{
++	if (rate_reset_nb->is_registered)
++		return;
++
++	rate_reset_nb->clk_nb.notifier_call = sun4i_rate_reset_notifier_cb;
++
++	INIT_DELAYED_WORK(&rate_reset_nb->reset_rate_work,
++			  sun4i_rate_reset_notifier_delayed_update);
++
++	if (!clk_notifier_register(rate_reset_nb->target_clk,
++				   &rate_reset_nb->clk_nb))
++		rate_reset_nb->is_registered = true;
++}
++
++static struct sun4i_rate_reset_nb tcon_rate_reset_tcon0_nb;
++
++static void sun4i_tcon0_set_dclk_rate(struct sun4i_tcon *tcon, unsigned long rate)
++{
++	clk_set_rate(tcon->dclk, rate);
++
++	if (tcon->quirks->restores_rate) {
++		tcon_rate_reset_tcon0_nb.target_clk = tcon->dclk;
++		tcon_rate_reset_tcon0_nb.saved_rate = rate;
++		sun4i_rate_reset_notifier_register(&tcon_rate_reset_tcon0_nb);
++	}
++}
++
+ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
+ 				     const struct drm_encoder *encoder,
+ 				     const struct drm_display_mode *mode)
+@@ -390,8 +439,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
+ 	 */
+ 	tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
+ 	tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
+-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes)
+-						  / SUN6I_DSI_TCON_DIV);
++	sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000 * (bpp / lanes)
++				  / SUN6I_DSI_TCON_DIV);
+ 
+ 	/* Set the resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+@@ -464,7 +513,7 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
+ 
+ 	tcon->dclk_min_div = 7;
+ 	tcon->dclk_max_div = 7;
+-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
++	sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000);
+ 
+ 	/* Set the resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+@@ -548,7 +597,7 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
+ 
+ 	tcon->dclk_min_div = tcon->quirks->dclk_min_div;
+ 	tcon->dclk_max_div = 127;
+-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
++	sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000);
+ 
+ 	/* Set the resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+@@ -1561,6 +1610,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
+ 	.supports_lvds		= true,
+ };
+ 
++static const struct sun4i_tcon_quirks sun50i_a64_lcd_quirks = {
++	.supports_lvds		= true,
++	.has_channel_0		= true,
++	.restores_rate		= true,
++	.dclk_min_div		= 1,
++	.setup_lvds_phy		= sun6i_tcon_setup_lvds_phy,
++};
++
+ static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
+ 	.supports_lvds		= true,
+ 	.has_channel_0		= true,
+@@ -1619,6 +1676,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
+ 	{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
+ 	{ .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
+ 	{ .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
++	{ .compatible = "allwinner,sun50i-a64-tcon-lcd", .data = &sun50i_a64_lcd_quirks },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index 864d70b9d242..729d64b78846 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -250,6 +250,7 @@ struct sun4i_tcon_quirks {
+ 	bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
+ 	bool	supports_lvds;   /* Does the TCON support an LVDS output? */
+ 	bool	polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
++	bool	restores_rate;   /* restores the initial rate when rate changes */
+ 	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */
+ 
+ 	/* callback to handle tcon muxing options */
+@@ -312,4 +313,15 @@ void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable);
+ 
+ extern const struct of_device_id sun4i_tcon_of_table[];
+ 
++struct sun4i_rate_reset_nb {
++	struct notifier_block	clk_nb;
++	struct delayed_work	reset_rate_work;
++
++	struct clk		*target_clk;
++	unsigned long		saved_rate;
++	bool			is_registered;
++};
++
++#define to_sun4i_rate_reset_nb(_nb) container_of(_nb, struct sun4i_rate_reset_nb, clk_nb)
++
+ #endif /* __SUN4I_TCON_H__ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
new file mode 100644
index 000000000000..5f2defa048fc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
@@ -0,0 +1,34 @@
+From 9f44b9ab08fac2e74e8eb9502ad5f32da27cbbf2 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Tue, 10 Sep 2019 12:02:23 +0800
+Subject: dt-bindings: axp20x-adc: allow to use TS pin as GPADC
+
+The AXP series PMICs allow to use the TS pin as GPADC rather than the
+battery temperature sensor.
+
+Add the property to enable this mode.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ .../devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml     | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
+index d40689f233f2..74f051a86927 100644
+--- a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
++++ b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
+@@ -61,6 +61,11 @@ properties:
+   "#io-channel-cells":
+     const: 1
+ 
++  x-powers,ts-as-gpadc:
++    description: |
++      Boolean. Defines whether the TS pin should be used
++      as GPADC rather than battery temperature sensor pin.
++
+ additionalProperties: false
+ 
+ examples:
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
new file mode 100644
index 000000000000..5949b2bee9e7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
@@ -0,0 +1,35 @@
+From a5aea2ef98aababb6e64b1d979ad3449f9b3805a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 00:00:00 +0100
+Subject: dt-bindings: input: gpio-vibrator: Don't require enable-gpios
+
+It is possible to turn the motor on/off just by enabling/disabling
+the vcc-supply. Change the binding to require either enable-gpios
+or vcc-supply or both.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ Documentation/devicetree/bindings/input/gpio-vibrator.yaml | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
+index 2384465eaa19..082ac06471db 100644
+--- a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
++++ b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
+@@ -24,7 +24,12 @@ properties:
+ 
+ required:
+   - compatible
+-  - enable-gpios
++
++anyOf:
++  - required:
++    - enable-gpios
++  - required:
++    - vcc-supply
+ 
+ additionalProperties: false
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
new file mode 100644
index 000000000000..be8c0871b5e1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
@@ -0,0 +1,46 @@
+From 73c5a3e392c4c76b8520ec65845f544127c3b034 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 13:40:15 +0100
+Subject: dt-bindings: leds: Add a binding for AXP813 charger led
+
+The AXP813 PMIC can control one LED. Add binding to represent the LED.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../devicetree/bindings/leds/leds-axp20x.yaml | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/leds/leds-axp20x.yaml
+
+diff --git a/Documentation/devicetree/bindings/leds/leds-axp20x.yaml b/Documentation/devicetree/bindings/leds/leds-axp20x.yaml
+new file mode 100644
+index 000000000000..110edae82204
+--- /dev/null
++++ b/Documentation/devicetree/bindings/leds/leds-axp20x.yaml
+@@ -0,0 +1,24 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/leds/leds-axp20x.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: LED driver for AXP813 PMIC from X-Powers.
++
++maintainers:
++  - Ondrej Jirman <megi@xff.cz>
++
++description: |
++  This module is part of the AXP20x MFD device. For more details
++  see Documentation/devicetree/bindings/mfd/axp20x.txt.
++
++  The LED controller is represented as a sub-node of the PMIC node on
++  the device tree.
++
++properties:
++  compatible:
++    const: x-powers,axp813-charger-led
++
++required:
++  - compatible
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
new file mode 100644
index 000000000000..26efe00cc083
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
@@ -0,0 +1,71 @@
+From 07b7d99773b41dd04e1865239a5a1c0980b78e4b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 30 Sep 2017 02:30:39 +0200
+Subject: dt-bindings: media: Add bindings for Himax HM5065 camera sensor
+
+HM5065 is 5MP CMOS sensor...
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../devicetree/bindings/media/i2c/hm5065.txt  | 49 +++++++++++++++++++
+ 1 file changed, 49 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/media/i2c/hm5065.txt
+
+diff --git a/Documentation/devicetree/bindings/media/i2c/hm5065.txt b/Documentation/devicetree/bindings/media/i2c/hm5065.txt
+new file mode 100644
+index 000000000000..92ba6cac0d2f
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/i2c/hm5065.txt
+@@ -0,0 +1,49 @@
++* Himax HM5065 CSI camera sensor
++
++Required Properties:
++- compatible: should be "himax,hm5065"
++- reg: I2C device address (0x1f)
++- clocks: reference to the external input clock for the sensor.
++- clock-names: should be "xclk".
++- IOVDD-supply: Digital I/O voltage supply, 2.8 volts
++- AVDD-supply: Analog voltage supply, 2.8 volts
++- DVDD-supply: Digital core voltage supply, 1.8 volts
++- AFVDD-supply: Auto focus voltage supply, 2.8 volts
++
++Optional Properties (one or both must be configured):
++- reset-gpios: reference to the GPIO connected to the reset pin, if any.
++	       This is an active low signal to the HM5065.
++- enable-gpios: reference to the GPIO connected to the CE pin,
++		if any. This is an active high signal to the HM5065.
++
++The device node must contain one 'port' child node for its digital output
++video port, in accordance with the video interface bindings defined in
++Documentation/devicetree/bindings/media/video-interfaces.txt.
++
++Example:
++
++&i2c1 {
++	hm5065: camera@1f {
++		compatible = "himax,hm5065";
++		reg = <0x1f>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		AFVDD-supply = <&reg_dldo3>;
++		reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
++		enable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
++
++		port {
++			hm5065_ep: endpoint {
++				remote-endpoint = <&csi0_hm5065_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
new file mode 100644
index 000000000000..a510e61ca12f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
@@ -0,0 +1,84 @@
+From c13501199dd9155a7fe236e8580283664c29c51d Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 17 Feb 2024 02:01:49 +0100
+Subject: dt: bindings: mfd: Add codec related properties to AC100 PMIC
+
+This PMIC includes a co-packaged audio codec with analog and digital
+parts. Add additional properties that describe power supplies to
+the codec, and the node for analog part of the codec.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../bindings/mfd/x-powers,ac100.yaml          | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml b/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
+index f3d8394b27e7..59ad898fbf85 100644
+--- a/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
++++ b/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
+@@ -34,11 +34,39 @@ properties:
+         description: >
+           Name of the 4M_adda clock exposed by the codec
+ 
++      "#sound-dai-cells":
++        const: 1
++
++      LDOIN-supply: true
++      AVCC-supply: true
++      VDDIO1-supply: true
++      VDDIO2-supply: true
++
+     required:
+       - "#clock-cells"
+       - compatible
+       - interrupts
+       - clock-output-names
++      - "#sound-dai-cells"
++      - LDOIN-supply
++      - AVCC-supply
++      - VDDIO1-supply
++      - VDDIO2-supply
++
++    additionalProperties: false
++
++  codec-analog:
++    type: object
++
++    properties:
++      compatible:
++        const: x-powers,ac100-codec-analog
++
++      CPVDD-supply: true
++
++    required:
++      - compatible
++      - CPVDD-supply
+ 
+     additionalProperties: false
+ 
+@@ -94,12 +122,22 @@ examples:
+             compatible = "x-powers,ac100";
+             reg = <0xe89>;
+ 
++            ac100_codec_analog: codec-analog {
++                compatible = "x-powers,ac100-codec-analog";
++                CPVDD-supply = <&reg_aldo2>;
++            };
++
+             ac100_codec: codec {
++                #sound-dai-cells = <1>;
+                 compatible = "x-powers,ac100-codec";
+                 interrupt-parent = <&r_pio>;
+                 interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */
+                 #clock-cells = <0>;
+                 clock-output-names = "4M_adda";
++                LDOIN-supply = <&reg_aldo2>;
++                AVCC-supply = <&reg_aldo3>;
++                VDDIO1-supply = <&reg_dcdc1>;
++                VDDIO2-supply = <&reg_dldo1>;
+             };
+ 
+             ac100_rtc: rtc {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
new file mode 100644
index 000000000000..2583b97b285c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
@@ -0,0 +1,36 @@
+From 9a7a0d92cb86f09f3644c2df84afc9962160ab59 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 23 Feb 2024 00:47:12 +0100
+Subject: dt-bindings: sound: Add jack-type property to sun8i-a33-codec
+
+The codec driver needs to know what jack connector is connected to
+on the board. Add proprty to describe the type of connector.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../bindings/sound/allwinner,sun8i-a33-codec.yaml        | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml
+index 63eadc4200ac..399fc00ad3f4 100644
+--- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml
++++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml
+@@ -44,6 +44,15 @@ properties:
+       - const: bus
+       - const: mod
+ 
++  jack-type:
++    enum:
++      - headset
++      - headphone
++    description:
++      Type of jack connector connected to the codec. This can be either
++      a 3-pin headphone connector or 4-pin headset connector. If not
++      specified, jack detection is disabled.
++
+ required:
+   - "#sound-dai-cells"
+   - compatible
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
new file mode 100644
index 000000000000..85784df21b92
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
@@ -0,0 +1,127 @@
+From 5001c4dd2f41d537e8622d8895a9594d23d26d5a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 5 Mar 2019 22:02:41 -0600
+Subject: firmware: arm_scpi: Support unidirectional mailbox channels
+
+Some mailbox controllers have only unidirectional channels, so we need a
+pair of them for each SCPI channel. If a mbox-names property is present,
+look for "rx" and "tx" mbox channels; otherwise, the existing behavior
+is preserved, and a single mbox channel is used for each SCPI channel.
+
+Note that since the mailbox framework only supports a single phandle
+with each name (mbox_request_channel_byname always returns the first
+one), this new mode only supports a single SCPI channel.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/firmware/arm_scpi.c | 58 +++++++++++++++++++++++++++++--------
+ 1 file changed, 46 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
+index 5f3a6422b02c..907b2d09da6a 100644
+--- a/drivers/firmware/arm_scpi.c
++++ b/drivers/firmware/arm_scpi.c
+@@ -237,7 +237,8 @@ struct scpi_xfer {
+ 
+ struct scpi_chan {
+ 	struct mbox_client cl;
+-	struct mbox_chan *chan;
++	struct mbox_chan *rx_chan;
++	struct mbox_chan *tx_chan;
+ 	void __iomem *tx_payload;
+ 	void __iomem *rx_payload;
+ 	struct list_head rx_pending;
+@@ -511,7 +512,7 @@ static int scpi_send_message(u8 idx, void *tx_buf, unsigned int tx_len,
+ 	msg->rx_len = rx_len;
+ 	reinit_completion(&msg->done);
+ 
+-	ret = mbox_send_message(scpi_chan->chan, msg);
++	ret = mbox_send_message(scpi_chan->tx_chan, msg);
+ 	if (ret < 0 || !rx_buf)
+ 		goto out;
+ 
+@@ -869,8 +870,13 @@ static void scpi_free_channels(void *data)
+ 	struct scpi_drvinfo *info = data;
+ 	int i;
+ 
+-	for (i = 0; i < info->num_chans; i++)
+-		mbox_free_channel(info->channels[i].chan);
++	for (i = 0; i < info->num_chans; i++) {
++		struct scpi_chan *pchan = &info->channels[i];
++
++		if (pchan->tx_chan != pchan->rx_chan)
++			mbox_free_channel(pchan->tx_chan);
++		mbox_free_channel(pchan->rx_chan);
++	}
+ }
+ 
+ static void scpi_remove(struct platform_device *pdev)
+@@ -920,6 +926,7 @@ static int scpi_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct device_node *np = dev->of_node;
+ 	struct scpi_drvinfo *scpi_drvinfo;
++	bool use_mbox_names = false;
+ 
+ 	scpi_drvinfo = devm_kzalloc(dev, sizeof(*scpi_drvinfo), GFP_KERNEL);
+ 	if (!scpi_drvinfo)
+@@ -932,6 +939,14 @@ static int scpi_probe(struct platform_device *pdev)
+ 		dev_err(dev, "no mboxes property in '%pOF'\n", np);
+ 		return -ENODEV;
+ 	}
++	if (of_get_property(dev->of_node, "mbox-names", NULL)) {
++		use_mbox_names = true;
++		if (count != 2) {
++			dev_err(dev, "need exactly 2 mboxes with mbox-names\n");
++			return -ENODEV;
++		}
++		count /= 2;
++	}
+ 
+ 	scpi_drvinfo->channels =
+ 		devm_kcalloc(dev, count, sizeof(struct scpi_chan), GFP_KERNEL);
+@@ -980,15 +995,34 @@ static int scpi_probe(struct platform_device *pdev)
+ 		mutex_init(&pchan->xfers_lock);
+ 
+ 		ret = scpi_alloc_xfer_list(dev, pchan);
+-		if (!ret) {
+-			pchan->chan = mbox_request_channel(cl, idx);
+-			if (!IS_ERR(pchan->chan))
+-				continue;
+-			ret = PTR_ERR(pchan->chan);
+-			if (ret != -EPROBE_DEFER)
+-				dev_err(dev, "failed to get channel%d err %d\n",
+-					idx, ret);
++		if (ret)
++			return ret;
++
++		if (use_mbox_names) {
++			pchan->rx_chan = mbox_request_channel_byname(cl, "rx");
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->rx_chan);
++				goto fail;
++			}
++			pchan->tx_chan = mbox_request_channel_byname(cl, "tx");
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->tx_chan);
++				goto fail;
++			}
++		} else {
++			pchan->rx_chan = mbox_request_channel(cl, idx);
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->rx_chan);
++				goto fail;
++			}
++			pchan->tx_chan = pchan->rx_chan;
+ 		}
++		continue;
++
++fail:
++		if (ret != -EPROBE_DEFER)
++			dev_err(dev, "failed to get channel%d err %d\n",
++				idx, ret);
+ 		return ret;
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
new file mode 100644
index 000000000000..3ac32bab8ccc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
@@ -0,0 +1,87 @@
+From c49ab0f0de7705a4493142353fd561fc0dedd2be Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 2 Nov 2019 15:14:10 +0100
+Subject: firmware: scpi: Add support for sending a SCPI_CMD_SET_SYS_PWR_STATE
+ msg
+
+This is NOT the right message to signal SCP we want to suspend the
+system, but we use it anyway, because we simply want to do a fixed
+function suspend sequence, instead of more complicated and granular
+cluster/cpu/system power management.
+
+Normally we'd signal system suspend by sending a CSS power state
+message. I guess that can be done later, if wanted.
+
+For now, Linux will kill all secondary CPU cores via MCPM, and SCP
+will kill the last CPU, and suspend the system.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/firmware/arm_scpi.c   | 10 ++++++++++
+ include/linux/scpi_protocol.h |  1 +
+ 2 files changed, 11 insertions(+)
+
+diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
+index 94a6b4e667de..5f3a6422b02c 100644
+--- a/drivers/firmware/arm_scpi.c
++++ b/drivers/firmware/arm_scpi.c
+@@ -187,6 +187,7 @@ enum scpi_drv_cmds {
+ 	CMD_SENSOR_VALUE,
+ 	CMD_SET_DEVICE_PWR_STATE,
+ 	CMD_GET_DEVICE_PWR_STATE,
++	CMD_SET_SYS_PWR_STATE,
+ 	CMD_MAX_COUNT,
+ };
+ 
+@@ -203,6 +204,7 @@ static int scpi_std_commands[CMD_MAX_COUNT] = {
+ 	SCPI_CMD_SENSOR_VALUE,
+ 	SCPI_CMD_SET_DEVICE_PWR_STATE,
+ 	SCPI_CMD_GET_DEVICE_PWR_STATE,
++	SCPI_CMD_SET_SYS_PWR_STATE,
+ };
+ 
+ static int scpi_legacy_commands[CMD_MAX_COUNT] = {
+@@ -218,6 +220,7 @@ static int scpi_legacy_commands[CMD_MAX_COUNT] = {
+ 	LEGACY_SCPI_CMD_SENSOR_VALUE,
+ 	-1, /* SET_DEVICE_PWR_STATE */
+ 	-1, /* GET_DEVICE_PWR_STATE */
++	LEGACY_SCPI_CMD_SYS_PWR_STATE,
+ };
+ 
+ struct scpi_xfer {
+@@ -782,6 +785,12 @@ static int scpi_device_set_power_state(u16 dev_id, u8 pstate)
+ 				 sizeof(dev_set), &stat, sizeof(stat));
+ }
+ 
++static int scpi_sys_set_power_state(u8 pstate)
++{
++	return scpi_send_message(CMD_SET_SYS_PWR_STATE, &pstate,
++				 sizeof(pstate), NULL, 0);
++}
++
+ static struct scpi_ops scpi_ops = {
+ 	.get_version = scpi_get_version,
+ 	.clk_get_range = scpi_clk_get_range,
+@@ -798,6 +807,7 @@ static struct scpi_ops scpi_ops = {
+ 	.sensor_get_value = scpi_sensor_get_value,
+ 	.device_get_power_state = scpi_device_get_power_state,
+ 	.device_set_power_state = scpi_device_set_power_state,
++	.sys_set_power_state = scpi_sys_set_power_state,
+ };
+ 
+ struct scpi_ops *get_scpi_ops(void)
+diff --git a/include/linux/scpi_protocol.h b/include/linux/scpi_protocol.h
+index d2176a56828a..6169348c3b72 100644
+--- a/include/linux/scpi_protocol.h
++++ b/include/linux/scpi_protocol.h
+@@ -76,6 +76,7 @@ struct scpi_ops {
+ 	int (*sensor_get_value)(u16, u64 *);
+ 	int (*device_get_power_state)(u16);
+ 	int (*device_set_power_state)(u16, u8);
++	int (*sys_set_power_state)(u8);
+ };
+ 
+ #if IS_REACHABLE(CONFIG_ARM_SCPI_PROTOCOL)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
new file mode 100644
index 000000000000..b4099e137689
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
@@ -0,0 +1,64 @@
+From 8df6745d90f1db3959d3b11fc82c9ed8969e9eec Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Oct 2019 05:08:35 +0200
+Subject: gnss: ubx: Send soft powerdown message on suspend
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gnss/ubx.c | 35 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+diff --git a/drivers/gnss/ubx.c b/drivers/gnss/ubx.c
+index 92402f6082c4..fd0ccb054477 100644
+--- a/drivers/gnss/ubx.c
++++ b/drivers/gnss/ubx.c
+@@ -33,11 +33,46 @@ static int ubx_set_active(struct gnss_serial *gserial)
+ 	return 0;
+ }
+ 
++// RXM-PMREQ
++static const u8 ubx_suspend_packet[] = {
++	0xb5, 0x62, // 'ub'
++	0x02, 0x41, // message class and id
++	0x08, 0x00, // message length
++	0x00, 0x00, 0x00, 0x00, // duration (0 == infinite)
++	0x02, 0x00, 0x00, 0x00, // flags (backup)
++	0x4d, 0x3b, // checksum
++};
++
+ static int ubx_set_standby(struct gnss_serial *gserial)
+ {
+ 	struct ubx_data *data = gnss_serial_get_drvdata(gserial);
+ 	int ret;
+ 
++#if 0
++	struct serdev_device *serdev = gserial->serdev;
++
++	// we can't know what state the device is in, so first make sure
++	// it's woken up by writing a zero byte to it and then suspend it
++	// for sure
++
++	ret = serdev_device_write(serdev, "", 1, MAX_SCHEDULE_TIMEOUT);
++	if (ret < 0)
++		return ret;
++
++	serdev_device_wait_until_sent(serdev, 0);
++
++	// wait for wakeup
++	mdelay(100);
++
++	ret = serdev_device_write(serdev, ubx_suspend_packet,
++				  sizeof(ubx_suspend_packet),
++				  MAX_SCHEDULE_TIMEOUT);
++	if (ret < 0 || ret < sizeof(ubx_suspend_packet))
++		return ret;
++
++	serdev_device_wait_until_sent(serdev, 0);
++#endif
++
+ 	ret = regulator_disable(data->vcc);
+ 	if (ret)
+ 		return ret;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/hm5065-yaml-bindings-wip.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/hm5065-yaml-bindings-wip.patch
new file mode 100644
index 000000000000..2956c6244889
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/hm5065-yaml-bindings-wip.patch
@@ -0,0 +1,109 @@
+From 16d57bd0e0a42c086a842ca214cc6c354c3405ce Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 20 May 2019 17:58:05 +0200
+Subject: hm5065: yaml bindings (wip)
+
+---
+ .../devicetree/bindings/media/i2c/hm5065.yaml | 90 +++++++++++++++++++
+ 1 file changed, 90 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/media/i2c/hm5065.yaml
+
+diff --git a/Documentation/devicetree/bindings/media/i2c/hm5065.yaml b/Documentation/devicetree/bindings/media/i2c/hm5065.yaml
+new file mode 100644
+index 000000000000..df7a4f514b3f
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/i2c/hm5065.yaml
+@@ -0,0 +1,90 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/media/i2c/hm5065.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Himax HM5065 CSI camera sensor
++
++description: |+
++  At least one of reset-gpios and enable-gpios must be configured.
++
++  The device node must contain one 'port' child node for its digital output
++  video port, in accordance with the video interface bindings defined in
++  
++  Documentation/devicetree/bindings/media/video-interfaces.txt.
++
++maintainers:
++  - Ondrej Jirman <megi@xff.cz>
++
++properties:
++  compatible:
++    const: himax,hm5065
++
++  reg:
++    maxItems: 1
++
++  reset-gpios:
++    maxItems: 1
++    description: reference to the GPIO connected to the reset pin, if any. This is an active low signal to the HM5065.
++
++  enable-gpios:
++    maxItems: 1
++    description: reference to the GPIO connected to the CE pin, if any. This is an active high signal to the HM5065.
++
++  IOVDD-supply:
++    description: Digital I/O voltage supply, 2.8 volts
++
++  AVDD-supply:
++    description: Analog voltage supply, 2.8 volts
++
++  DVDD-supply:
++    description: Digital core voltage supply, 1.8 volts
++
++  AFVDD-supply:
++    description: Auto focus voltage supply, 2.8 volts
++
++  clocks:
++    minItems: 1
++    maxItems: 1
++    description: reference to the external input clock for the sensor.
++
++- clock-names: should be "xclk".
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - IOVDD-supply
++  - AVDD-supply
++  - DVDD-supply
++  - AFVDD-supply
++
++Example:
++
++&i2c1 {
++	hm5065: camera@1f {
++		compatible = "himax,hm5065";
++		reg = <0x1f>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		AFVDD-supply = <&reg_dldo3>;
++		reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
++		enable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
++
++		port {
++			hm5065_ep: endpoint {
++				remote-endpoint = <&csi0_hm5065_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
new file mode 100644
index 000000000000..76f29d36acd0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
@@ -0,0 +1,35 @@
+From 7e071906278840c03ee94954ebe58b94e3d75691 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 17 Jan 2021 23:19:52 +0100
+Subject: i2c: mv64xxx: Don't make a fuss when pinctrl recovery state is not
+ present
+
+Otherwise dmesg log presents a useless error.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/i2c/busses/i2c-mv64xxx.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
+index dc160cbc3155..df82deb65ecc 100644
+--- a/drivers/i2c/busses/i2c-mv64xxx.c
++++ b/drivers/i2c/busses/i2c-mv64xxx.c
+@@ -950,6 +950,14 @@ static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
+ 		return -ENODEV;
+ 	}
+ 
++	if (IS_ERR(pinctrl_lookup_state(rinfo->pinctrl, "gpio")) &&
++		IS_ERR(pinctrl_lookup_state(rinfo->pinctrl, "recovery"))) {
++		/* No recovery state is vailable in pinctrl. */
++		devm_pinctrl_put(rinfo->pinctrl);
++		rinfo->pinctrl = NULL;
++		return 0;
++	}
++
+ 	drv_data->adapter.bus_recovery_info = rinfo;
+ 	return 0;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
new file mode 100644
index 000000000000..b0e0beab9b4d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
@@ -0,0 +1,42 @@
+From f8f280eabdd473b09e9bac38596c9196535e0fa3 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Tue, 10 Sep 2019 12:03:32 +0800
+Subject: iio: adc: axp20x_adc: allow to set TS pin to GPADC mode
+
+The TS pin of AXP PMICs can be set to GPADC mode. In this situation, it
+doesn't affect battery charging.
+
+Add the code to do the mode setting.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ drivers/iio/adc/axp20x_adc.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
+index d6c51b0f48e3..855cc7c809eb 100644
+--- a/drivers/iio/adc/axp20x_adc.c
++++ b/drivers/iio/adc/axp20x_adc.c
+@@ -40,6 +40,7 @@
+ #define AXP813_TS_GPIO0_ADC_RATE_HZ(x)		AXP20X_ADC_RATE_HZ(x)
+ #define AXP813_V_I_ADC_RATE_HZ(x)		((ilog2((x) / 100) << 4) & AXP813_V_I_ADC_RATE_MASK)
+ #define AXP813_ADC_RATE_HZ(x)			(AXP20X_ADC_RATE_HZ(x) | AXP813_V_I_ADC_RATE_HZ(x))
++#define AXP20X_TS_FUNCTION_GPADC		BIT(2)
+ 
+ #define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg)	\
+ 	{							\
+@@ -716,6 +717,11 @@ static int axp20x_probe(struct platform_device *pdev)
+ 				   info->data->adc_en2_mask,
+ 				   info->data->adc_en2_mask);
+ 
++	if (of_property_read_bool(pdev->dev.of_node, "x-powers,ts-as-gpadc"))
++		regmap_update_bits(info->regmap, AXP20X_ADC_RATE,
++				   AXP20X_TS_FUNCTION_GPADC,
++				   AXP20X_TS_FUNCTION_GPADC);
++
+ 	/* Configure ADCs rate */
+ 	info->data->adc_rate(info, 100);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
new file mode 100644
index 000000000000..6f59692413b3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
@@ -0,0 +1,39 @@
+From b2e0c6f9ab6f10b2f694f6a9560c0504695e5ade Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 29 Oct 2022 23:12:49 +0200
+Subject: iio: st_sensors: Don't report error when the device is not present on
+ I2C bus
+
+On Pinephone, this is not an error, because there are two alternate
+magentometer configurations.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/iio/common/st_sensors/st_sensors_core.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/iio/common/st_sensors/st_sensors_core.c b/drivers/iio/common/st_sensors/st_sensors_core.c
+index c77d7bdcc121..f0612b5ea8e0 100644
+--- a/drivers/iio/common/st_sensors/st_sensors_core.c
++++ b/drivers/iio/common/st_sensors/st_sensors_core.c
+@@ -600,8 +600,16 @@ int st_sensors_verify_id(struct iio_dev *indio_dev)
+ 		err = regmap_read(sdata->regmap,
+ 				  sdata->sensor_settings->wai_addr, &wai);
+ 		if (err < 0) {
++			if (err == -ENXIO) {
++				dev_info(&indio_dev->dev,
++					 "%s is not present on the bus\n",
++					 indio_dev->name);
++				return err;
++			}
++
+ 			dev_err(&indio_dev->dev,
+-				"failed to read Who-Am-I register.\n");
++				"%s: failed to read Who-Am-I register (%d).\n",
++				indio_dev->name, err);
+ 			return err;
+ 		}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
new file mode 100644
index 000000000000..afc889142c61
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
@@ -0,0 +1,76 @@
+From a327870ad4e4faa96365db0ed17d4209ee435ea9 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 8 Sep 2023 01:07:30 +0200
+Subject: input: gpio-vibra: Allow to use vcc-supply alone to control the
+ vibrator
+
+Make enable-gpio optional to allow using this driver with boards that
+have vibrator connected to a power supply without intermediate gpio
+based enable circuitry.
+
+Also avoid a case where neither regulator nor enable gpio is specified,
+and bail out in probe in such a case.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/misc/gpio-vibra.c | 25 ++++++++++++++++++-------
+ 1 file changed, 18 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/input/misc/gpio-vibra.c b/drivers/input/misc/gpio-vibra.c
+index ad44b4d18a2a..de24e28458b0 100644
+--- a/drivers/input/misc/gpio-vibra.c
++++ b/drivers/input/misc/gpio-vibra.c
+@@ -39,7 +39,7 @@ static int gpio_vibrator_start(struct gpio_vibrator *vibrator)
+ 	struct device *pdev = vibrator->input->dev.parent;
+ 	int err;
+ 
+-	if (!vibrator->vcc_on) {
++	if (vibrator->vcc && !vibrator->vcc_on) {
+ 		err = regulator_enable(vibrator->vcc);
+ 		if (err) {
+ 			dev_err(pdev, "failed to enable regulator: %d\n", err);
+@@ -57,7 +57,7 @@ static void gpio_vibrator_stop(struct gpio_vibrator *vibrator)
+ {
+ 	gpiod_set_value_cansleep(vibrator->gpio, 0);
+ 
+-	if (vibrator->vcc_on) {
++	if (vibrator->vcc && vibrator->vcc_on) {
+ 		regulator_disable(vibrator->vcc);
+ 		vibrator->vcc_on = false;
+ 	}
+@@ -112,16 +112,27 @@ static int gpio_vibrator_probe(struct platform_device *pdev)
+ 	if (!vibrator->input)
+ 		return -ENOMEM;
+ 
+-	vibrator->vcc = devm_regulator_get(&pdev->dev, "vcc");
+-	if (IS_ERR(vibrator->vcc))
+-		return dev_err_probe(&pdev->dev, PTR_ERR(vibrator->vcc),
++	vibrator->vcc = devm_regulator_get_optional(&pdev->dev, "vcc");
++	err = PTR_ERR_OR_ZERO(vibrator->vcc);
++	if (err == -ENODEV) {
++		vibrator->vcc = NULL;
++	} else if (err) {
++		return dev_err_probe(&pdev->dev, err,
+ 				     "Failed to request regulator\n");
++	}
+ 
+-	vibrator->gpio = devm_gpiod_get(&pdev->dev, "enable", GPIOD_OUT_LOW);
+-	if (IS_ERR(vibrator->gpio))
++	vibrator->gpio = devm_gpiod_get_optional(&pdev->dev, "enable",
++						 GPIOD_OUT_LOW);
++	err = PTR_ERR_OR_ZERO(vibrator->gpio);
++	if (err)
+ 		return dev_err_probe(&pdev->dev, PTR_ERR(vibrator->gpio),
+ 				     "Failed to request main gpio\n");
+ 
++	if (!vibrator->vcc && !vibrator->gpio) {
++		dev_err(&pdev->dev, "Neither gpio nor regulator provided\n");
++		return -EINVAL;
++	}
++
+ 	INIT_WORK(&vibrator->play_work, gpio_vibrator_play_work);
+ 
+ 	vibrator->input->name = "gpio-vibrator";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
new file mode 100644
index 000000000000..030dd65cb030
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
@@ -0,0 +1,347 @@
+From aa8e9c7076764857a2103001811bdb85c19b817d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 4 Feb 2021 00:55:20 +0100
+Subject: leds: axp20x: Support charger LED on AXP20x like PMICs
+
+There is single LED that can be turned on and off by the user, or set to
+be controlled by the charger in 2 different modes.
+
+The driver initializes the LED to be controlled by the charger, but
+allows to switch it to user control, and change the mode of charging
+indication via a sysfs.
+
+The driver was developed on AXP813, but should work on other PMICs like
+that without changes.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/leds/Kconfig       |  15 +++
+ drivers/leds/Makefile      |   1 +
+ drivers/leds/leds-axp20x.c | 255 +++++++++++++++++++++++++++++++++++++
+ drivers/mfd/axp20x.c       |   3 +
+ 4 files changed, 274 insertions(+)
+ create mode 100644 drivers/leds/leds-axp20x.c
+
+diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
+index 05e6af88b88c..5c6993777c68 100644
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -920,6 +920,14 @@ config LEDS_IP30
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called leds-ip30.
+ 
++config LEDS_SGM3140
++	tristate "LED support for the SGM3140"
++	depends on LEDS_CLASS_FLASH
++	depends on V4L2_FLASH_LED_CLASS || !V4L2_FLASH_LED_CLASS
++	help
++	  This option enables support for the SGM3140 500mA Buck/Boost Charge
++	  Pump LED Driver.
++
+ config LEDS_ACER_A500
+ 	tristate "Power button LED support for Acer Iconia Tab A500"
+ 	depends on LEDS_CLASS && MFD_ACER_A500_EC
+@@ -927,6 +935,13 @@ config LEDS_ACER_A500
+ 	  This option enables support for the Power Button LED of
+ 	  Acer Iconia Tab A500.
+ 
++config LEDS_AXP20X
++	tristate "Charger LED support for AXP20X-like PMICs (AXP813, ...)"
++	depends on LEDS_CLASS && MFD_AXP20X
++	help
++	  This option enables support for on-chip LED driver on
++	  AXP20X-like PMICs.
++
+ source "drivers/leds/blink/Kconfig"
+ 
+ comment "Flash and Torch LED drivers"
+diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
+index effdfc6f1e95..9e1b57baf066 100644
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -90,6 +90,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA)		+= leds-turris-omnia.o
+ obj-$(CONFIG_LEDS_WM831X_STATUS)	+= leds-wm831x-status.o
+ obj-$(CONFIG_LEDS_WM8350)		+= leds-wm8350.o
+ obj-$(CONFIG_LEDS_WRAP)			+= leds-wrap.o
++obj-$(CONFIG_LEDS_AXP20X)		+= leds-axp20x.o
+ 
+ # Kinetic ExpressWire Protocol
+ obj-$(CONFIG_LEDS_EXPRESSWIRE)		+= leds-expresswire.o
+diff --git a/drivers/leds/leds-axp20x.c b/drivers/leds/leds-axp20x.c
+new file mode 100644
+index 000000000000..fd94930f6433
+--- /dev/null
++++ b/drivers/leds/leds-axp20x.c
+@@ -0,0 +1,255 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * LED Driver for X-Powers AXP813 PMIC and similar.
++ *
++ * Copyright(c) 2020 Ondrej Jirman <megi@xff.cz>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/leds.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/mfd/axp20x.h>
++
++#define AXP20X_CHGLED_CTRL_MASK		BIT(3)
++#define AXP20X_CHGLED_CTRL_CHARGER	BIT(3)
++#define AXP20X_CHGLED_CTRL_USER		0
++
++#define AXP20X_CHRG_CTRL2_MODE		BIT(4)
++
++#define AXP20X_CHGLED_USER_STATE_MASK		GENMASK(5, 4)
++#define AXP20X_CHGLED_USER_STATE_OFF		(0 << 4)
++#define AXP20X_CHGLED_USER_STATE_BLINK_SLOW	(1 << 4)
++#define AXP20X_CHGLED_USER_STATE_BLINK_FAST	(2 << 4)
++#define AXP20X_CHGLED_USER_STATE_ON		(3 << 4)
++
++static struct led_hw_trigger_type axp20x_charger_led_trigger_type;
++
++struct axp20x_led {
++	struct led_classdev cdev;
++	struct regmap *regmap;
++};
++
++static int axp20x_led_set(struct led_classdev *led_cdev,
++			   enum led_brightness value)
++{
++	struct axp20x_led *led =
++			container_of(led_cdev, struct axp20x_led, cdev);
++	unsigned int val;
++
++	val = value == LED_OFF ? AXP20X_CHGLED_USER_STATE_OFF :
++		AXP20X_CHGLED_USER_STATE_ON;
++
++	return regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
++				  AXP20X_CHGLED_USER_STATE_MASK, val);
++
++}
++
++static int axp20x_set_charger_control(struct led_classdev *led_cdev, bool on)
++{
++	struct axp20x_led *led = container_of(led_cdev, struct axp20x_led, cdev);
++
++	return regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
++				  AXP20X_CHGLED_CTRL_MASK,
++				  on ? AXP20X_CHGLED_CTRL_CHARGER :
++				  AXP20X_CHGLED_CTRL_USER);
++}
++
++static int axp20x_trig_charger_activate(struct led_classdev *led_cdev)
++{
++	return axp20x_set_charger_control(led_cdev, true);
++}
++
++static void axp20x_trig_charger_deactivate(struct led_classdev *led_cdev)
++{
++	axp20x_set_charger_control(led_cdev, false);
++}
++
++static ssize_t charger_mode_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	struct led_classdev *led_cdev = led_trigger_get_led(dev);
++	struct axp20x_led *led = container_of(led_cdev, struct axp20x_led, cdev);
++	unsigned int val;
++	int ret;
++
++	ret = regmap_read(led->regmap, AXP20X_CHRG_CTRL2, &val);
++	if (ret)
++		return ret;
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 val & AXP20X_CHRG_CTRL2_MODE ? 1 : 0);
++}
++
++static ssize_t charger_mode_store(struct device *dev,
++				  struct device_attribute *attr,
++				  const char *buf, size_t len)
++{
++	struct led_classdev *led_cdev = led_trigger_get_led(dev);
++	struct axp20x_led *led = container_of(led_cdev, struct axp20x_led, cdev);
++	unsigned int mode;
++	int ret;
++
++	ret = kstrtouint(buf, 0, &mode);
++	if (ret)
++		return ret;
++
++	if (mode > 1)
++		return -ERANGE;
++
++	ret = regmap_update_bits(led->regmap, AXP20X_CHRG_CTRL2,
++				 AXP20X_CHRG_CTRL2_MODE,
++				 mode ? AXP20X_CHRG_CTRL2_MODE : 0);
++	if (ret)
++		return ret;
++
++	return len;
++}
++static DEVICE_ATTR_RW(charger_mode);
++
++static struct attribute *axp20x_led_attrs[] = {
++	&dev_attr_charger_mode.attr,
++	NULL,
++};
++
++ATTRIBUTE_GROUPS(axp20x_led);
++
++static struct led_trigger axp20x_charger_led_trigger = {
++	.name		= "charger",
++	.trigger_type	= &axp20x_charger_led_trigger_type,
++	.activate	= axp20x_trig_charger_activate,
++	.deactivate	= axp20x_trig_charger_deactivate,
++	.groups		= axp20x_led_groups,
++};
++
++static int axp20x_led_probe(struct platform_device *pdev)
++{
++	struct axp20x_dev *axp20x;
++	struct axp20x_led *led;
++	unsigned int val;
++	int ret;
++
++	if (!of_device_is_available(pdev->dev.of_node))
++		return -ENODEV;
++
++	axp20x = dev_get_drvdata(pdev->dev.parent);
++	if (!axp20x)
++		return -EINVAL;
++
++	led = devm_kzalloc(&pdev->dev,
++			   sizeof(struct axp20x_led),
++			   GFP_KERNEL);
++	if (!led)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, led);
++
++	led->regmap = axp20x->regmap;
++
++	led->cdev.name = "axp20x-chgarger-led";
++	led->cdev.brightness_set_blocking = axp20x_led_set;
++	led->cdev.brightness = LED_OFF;
++	led->cdev.max_brightness = 1;
++	led->cdev.trigger_type = &axp20x_charger_led_trigger_type;
++
++	ret = regmap_read(led->regmap, AXP20X_OFF_CTRL, &val);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to read charger control status\n");
++		return ret;
++	}
++
++	if ((val & AXP20X_CHGLED_CTRL_MASK) == AXP20X_CHGLED_CTRL_CHARGER)
++		led->cdev.default_trigger = axp20x_charger_led_trigger.name;
++
++	ret = devm_led_classdev_register(pdev->dev.parent, &led->cdev);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to register led %s\n",
++			led->cdev.name);
++		return ret;
++	}
++
++	ret = regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
++				 AXP20X_CHGLED_CTRL_MASK,
++				 AXP20X_CHGLED_CTRL_CHARGER);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to enable charger control\n");
++		return ret;
++	}
++
++	ret = axp20x_led_set(&led->cdev, led->cdev.brightness);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to init led brightness\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static void axp20x_led_shutdown(struct platform_device *pdev)
++{
++	struct axp20x_led *led = platform_get_drvdata(pdev);
++
++	/* On shutdown, we want to give LED control back to the PMIC,
++	 * so that it doesn't stay on, while the system is off.
++	 */
++
++	axp20x_led_set(&led->cdev, LED_OFF);
++	axp20x_set_charger_control(&led->cdev, true);
++}
++
++static int axp20x_led_remove(struct platform_device *pdev)
++{
++	axp20x_led_shutdown(pdev);
++
++	return 0;
++}
++
++static const struct of_device_id axp20x_leds_of_match[] = {
++	{ .compatible = "x-powers,axp813-charger-led", },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, axp20x_leds_of_match);
++
++static struct platform_driver axp20x_led_driver = {
++	.driver		= {
++		.name	= "leds-axp20x",
++		.of_match_table = axp20x_leds_of_match,
++	},
++	.probe		= axp20x_led_probe,
++	.remove		= axp20x_led_remove,
++	.shutdown	= axp20x_led_shutdown,
++};
++
++static int __init axp20x_led_driver_init(void)
++{
++	int ret;
++
++	ret = led_trigger_register(&axp20x_charger_led_trigger);
++	if (ret)
++		return ret;
++
++	ret = platform_driver_register(&axp20x_led_driver);
++	if (ret) {
++		led_trigger_unregister(&axp20x_charger_led_trigger);
++		return ret;
++	}
++
++	return 0;
++}
++
++static void __exit axp20x_led_driver_exit(void)
++{
++	platform_driver_unregister(&axp20x_led_driver);
++	led_trigger_unregister(&axp20x_charger_led_trigger);
++}
++
++module_init(axp20x_led_driver_init);
++module_exit(axp20x_led_driver_exit);
++
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("LED driver for AXP813 PMIC");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:leds-axp20x");
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index d8daa593ebd5..f4d2d8f5b246 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -1087,6 +1087,9 @@ static const struct mfd_cell axp813_cells[] = {
+ 		.num_resources	= ARRAY_SIZE(axp803_usb_power_supply_resources),
+ 		.resources	= axp803_usb_power_supply_resources,
+ 		.of_compatible	= "x-powers,axp813-usb-power-supply",
++	}, {
++		.name		= "axp20x-charger-led",
++		.of_compatible	= "x-powers,axp813-charger-led",
+ 	},
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
new file mode 100644
index 000000000000..499e1329f910
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
@@ -0,0 +1,64 @@
+From a9035473c4f4cb2c6b247364336f030ca9171993 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 2 Nov 2019 15:09:01 +0100
+Subject: mailbox: Allow to run mailbox while timekeeping is suspended
+
+This makes it possible to send messages from CPU suspend finisher.
+
+We simply implement cl->tx_block using a busywait loop when
+timekeeping is suspended, instead of using hrtimer.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mailbox/mailbox.c | 28 ++++++++++++++++++++++++----
+ 1 file changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c
+index ebff3baf3045..9d6656a0dc38 100644
+--- a/drivers/mailbox/mailbox.c
++++ b/drivers/mailbox/mailbox.c
+@@ -84,10 +84,12 @@ static void msg_submit(struct mbox_chan *chan)
+ 	spin_unlock_irqrestore(&chan->lock, flags);
+ 
+ 	if (!err && (chan->txdone_method & TXDONE_BY_POLL)) {
+-		/* kick start the timer immediately to avoid delays */
+-		spin_lock_irqsave(&chan->mbox->poll_hrt_lock, flags);
+-		hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);
+-		spin_unlock_irqrestore(&chan->mbox->poll_hrt_lock, flags);
++		if (!timekeeping_suspended) {
++			/* kick start the timer immediately to avoid delays */
++			spin_lock_irqsave(&chan->mbox->poll_hrt_lock, flags);
++			hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);
++			spin_unlock_irqrestore(&chan->mbox->poll_hrt_lock, flags);
++		}
+ 	}
+ }
+ 
+@@ -269,6 +271,24 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg)
+ 
+ 	msg_submit(chan);
+ 
++	if (chan->cl->tx_block && timekeeping_suspended) {
++		int i = chan->cl->tx_tout * 10;
++		bool txdone;
++
++		while (i--) {
++			txdone = chan->mbox->ops->last_tx_done(chan);
++			if (txdone) {
++				tx_tick(chan, 0);
++				return 0;
++			}
++
++			udelay(100);
++		}
++
++		tx_tick(chan, -ETIME);
++		return -ETIME;
++	}
++
+ 	if (chan->cl->tx_block) {
+ 		unsigned long wait;
+ 		int ret;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
new file mode 100644
index 000000000000..de82c64b8bc4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
@@ -0,0 +1,35 @@
+From 29c1ff4f8327065922ce9cff3eef15b06c1b90f3 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 26 Apr 2020 14:38:15 -0500
+Subject: media: cedrus: Fix failure to clean up hardware on probe failure
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
+index f52df6836045..992b30e5ccac 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
+@@ -478,7 +478,7 @@ static int cedrus_probe(struct platform_device *pdev)
+ 	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "Failed to register V4L2 device\n");
+-		return ret;
++		goto err_hw;
+ 	}
+ 
+ 	vfd = &dev->vfd;
+@@ -539,6 +539,8 @@ static int cedrus_probe(struct platform_device *pdev)
+ 	v4l2_m2m_release(dev->m2m_dev);
+ err_v4l2:
+ 	v4l2_device_unregister(&dev->v4l2_dev);
++err_hw:
++	cedrus_hw_remove(dev);
+ 
+ 	return ret;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
new file mode 100644
index 000000000000..901b73d85daf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
@@ -0,0 +1,549 @@
+From 81c00ed6ab42a9f0a464f0e57c01241efb1c47d4 Mon Sep 17 00:00:00 2001
+From: Benjamin Schaaf <ben.schaaf@gmail.com>
+Date: Mon, 22 Nov 2021 23:38:26 +1100
+Subject: media: gc2145: Add PIXEL_RATE, HBLANK and VBLANK controls
+
+---
+ drivers/media/i2c/gc2145.c | 469 ++++++++++++++++++++-----------------
+ 1 file changed, 258 insertions(+), 211 deletions(-)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index df15b72651e2..749dce832aa0 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -216,6 +216,9 @@ static const char * const gc2145_supply_name[] = {
+ 
+ struct gc2145_ctrls {
+ 	struct v4l2_ctrl_handler handler;
++	struct v4l2_ctrl *pixel_rate;
++	struct v4l2_ctrl *hblank;
++	struct v4l2_ctrl *vblank;
+ 	struct {
+ 		struct v4l2_ctrl *auto_exposure;
+ 		struct v4l2_ctrl *exposure;
+@@ -866,6 +869,224 @@ static int gc2145_set_exposure(struct gc2145_dev *sensor)
+ 	return gc2145_tx_commit(sensor);;
+ }
+ 
++struct gc2145_sensor_params {
++	unsigned int enable_scaler;
++	unsigned int col_scaler_only;
++	unsigned int row_skip;
++	unsigned int col_skip;
++	unsigned long sh_delay;
++	unsigned long hb;
++	unsigned long vb;
++	unsigned long st;
++	unsigned long et;
++	unsigned long win_width;
++	unsigned long win_height;
++	unsigned long width;
++	unsigned long height;
++};
++
++static void gc2145_sensor_params_init(struct gc2145_sensor_params* p, int width, int height)
++{
++	p->win_height = height + 32;
++	p->win_width = (width + 16);
++	p->width = width;
++	p->height = height;
++	p->st = 2;
++	p->et = 2;
++	p->vb = 8;
++	p->hb = 0x1f0;
++	p->sh_delay = 30;
++}
++
++// unit is PCLK periods
++static unsigned long
++gc2145_sensor_params_get_row_period(struct gc2145_sensor_params* p)
++{
++	return 2 * (p->win_width / 2 / (p->col_skip + 1) + p->sh_delay + p->hb + 4);
++}
++
++static unsigned long
++gc2145_sensor_params_get_frame_period(struct gc2145_sensor_params* p)
++{
++	unsigned long rt = gc2145_sensor_params_get_row_period(p);
++
++	return rt * (p->vb + p->win_height) / (p->row_skip + 1);
++}
++
++static void
++gc2145_sensor_params_fit_hb_to_power_line_period(struct gc2145_sensor_params* p,
++					  unsigned long power_line_freq,
++					  unsigned long pclk)
++{
++	unsigned long rt, power_line_ratio;
++
++        for (p->hb = 0x1f0; p->hb < 2047; p->hb++) {
++		rt = gc2145_sensor_params_get_row_period(p);
++
++		// power_line_ratio is row_freq / power_line_freq * 1000
++                power_line_ratio = pclk / power_line_freq * 1000 / rt;
++
++		// if we're close enough, stop the search
++                if (power_line_ratio % 1000 < 50)
++                        break;
++        }
++
++	// finding the optimal Hb is not critical
++	if (p->hb == 2047)
++		p->hb = 0x1f0;
++}
++
++static void
++gc2145_sensor_params_fit_vb_to_frame_period(struct gc2145_sensor_params* p,
++				     unsigned long frame_period)
++{
++	unsigned long rt, fp;
++
++	p->vb = 8;
++	rt = gc2145_sensor_params_get_row_period(p);
++	fp = gc2145_sensor_params_get_frame_period(p);
++
++	if (frame_period > fp)
++		p->vb = frame_period * (p->row_skip + 1) / rt - p->win_height;
++
++	if (p->vb > 4095)
++		p->vb = 4095;
++}
++
++static struct gc2145_sensor_params gc2145_get_sensor_params(
++	unsigned long framerate,
++	unsigned long width,
++	unsigned long height,
++	unsigned long *pclk2)
++{
++	struct gc2145_sensor_params params = {0};
++	bool scaling_desired;
++	unsigned long frame_period;
++	unsigned long power_line_freq = 50;
++
++	/*
++	 * Equations for calculating framerate are:
++	 *
++	 *    ww = width + 16
++	 *    wh = height + 32
++	 *    Rt = (ww / 2 / (col_skip + 1) + sh_delay + Hb + 4)
++	 *    Ft = Rt * (Vb + wh) / (row_skip + 1)
++	 *    framerate = 2pclk / 4 / Ft
++	 *
++	 * Based on these equations:
++	 *
++	 * 1) First we need to determine what 2PCLK frequency to use. The 2PCLK
++	 *    frequency is not arbitrarily precise, so we need to calculate the
++	 *    actual frequency used, after setting our target frequency.
++	 *
++	 *    We use a simple heuristic:
++	 *
++	 *      If pixel_count * 2 * framerate * 1.15 is > 40MHz, we use 60MHz,
++	 *      otherwise we use 40MHz.
++	 *
++	 * 2) We want to determine lowest Hb that we can use to extend row
++	 *    period so that row time takes an integer fraction of the power
++	 *    line frequency period. Minimum Hb is 0x1f0.
++	 *
++	 * 3) If the requested resolution is less than half the sensor's size,
++	 *    we'll use scaling, or row skipping + column scaling, or row and
++	 *    column skiping, depending on what allows us to achieve the
++	 *    requested framerate.
++	 *
++	 * 4) We use the selected Hb to calculate Vb value that will give
++	 *    us the desired framerate, given the scaling/skipping option
++	 *    selected in 3).
++	 */
++
++	scaling_desired = width <= GC2145_SENSOR_WIDTH_MAX / 2
++			&& height <= GC2145_SENSOR_HEIGHT_MAX / 2;
++
++	*pclk2 = 60000000;
++
++	gc2145_sensor_params_init(&params, width, height);
++
++	// if the resolution is < half the sensor size, enable the scaler
++	// to cover more area of the chip
++	if (scaling_desired) {
++		params.enable_scaler = 1;
++		*pclk2 *= 2;
++		gc2145_sensor_params_init(&params, width * 2, height * 2);
++	}
++
++	// we need to call this each time pclk or power_line_freq is changed
++	gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++							 power_line_freq,
++							 *pclk2 / 2);
++
++	frame_period = gc2145_sensor_params_get_frame_period(&params);
++	if (framerate <= *pclk2 / 2 / frame_period)
++		goto apply;
++
++	if (scaling_desired) {
++		// try using just the column scaler + row skip
++		params.col_scaler_only = 1;
++		params.row_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++								 power_line_freq,
++								 *pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++		if (framerate <= *pclk2 / 2 / frame_period)
++			goto apply;
++
++
++		/*
++		// try disabling the scaler and just use skipping
++		params.enable_scaler = 0;
++		*pclk2 /= 2;
++		params.col_scaler_only = 0;
++		params.col_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params, power_line_freq, *pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++
++		if (framerate <= *pclk2 / 2 / frame_period)
++			goto apply;
++		*/
++	}
++
++apply:
++	// adjust vb to fit the target framerate
++	gc2145_sensor_params_fit_vb_to_frame_period(&params,
++						    *pclk2 / 2 / framerate);
++
++	return params;
++}
++
++static int gc2145_sensor_params_apply(struct gc2145_dev *sensor,
++				      struct gc2145_sensor_params* p)
++{
++	u32 off_x = (GC2145_SENSOR_WIDTH_MAX - p->width) / 2;
++	u32 off_y = (GC2145_SENSOR_HEIGHT_MAX - p->height) / 2;
++
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, 0xfd, (p->enable_scaler ? BIT(0) : 0)
++			| (p->col_scaler_only ? BIT(1) : 0));
++
++	gc2145_tx_write8(sensor, 0x18, 0x0a
++		       | (p->col_skip ? BIT(7) : 0)
++		       | (p->row_skip ? BIT(6) : 0));
++
++	gc2145_tx_write16(sensor, 0x09, off_y);
++	gc2145_tx_write16(sensor, 0x0b, off_x);
++	gc2145_tx_write16(sensor, 0x0d, p->win_height);
++	gc2145_tx_write16(sensor, 0x0f, p->win_width);
++	gc2145_tx_write16(sensor, 0x05, p->hb);
++	gc2145_tx_write16(sensor, 0x07, p->vb);
++	gc2145_tx_write16(sensor, 0x11, p->sh_delay);
++
++	gc2145_tx_write8(sensor, 0x13, p->st);
++	gc2145_tx_write8(sensor, 0x14, p->et);
++
++	return gc2145_tx_commit(sensor);
++}
++
+ /* Test patterns */
+ 
+ enum {
+@@ -1054,12 +1275,31 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	//u64 wb_mask = 0;
+ 	//unsigned int i;
+ 	int ret;
++	struct gc2145_sensor_params params;
++	unsigned long pixel_rate;
+ 
+ 	v4l2_ctrl_handler_init(hdl, 32);
+ 
+ 	/* we can use our own mutex for the ctrl lock */
+ 	hdl->lock = &sensor->lock;
+ 
++	/* Clock related controls */
++	params = gc2145_get_sensor_params(sensor->frame_interval.denominator,
++					  sensor->fmt.width,
++					  sensor->fmt.height,
++					  &pixel_rate);
++	ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
++					      0, INT_MAX, 1,
++					      pixel_rate);
++
++	ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
++					  0, INT_MAX, 1,
++					  params.win_height);
++
++	ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
++					  0, INT_MAX, 1,
++					  params.win_width);
++
+ 	/* Exposure controls */
+ 	ctrls->auto_exposure = v4l2_ctrl_new_std_menu(hdl, ops,
+ 						      V4L2_CID_EXPOSURE_AUTO,
+@@ -1153,6 +1393,10 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	v4l2_ctrl_auto_cluster(3, &ctrls->wb, V4L2_WHITE_BALANCE_MANUAL, false);
+ #endif
+ 
++	ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++	ctrls->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++	ctrls->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++
+ 	v4l2_ctrl_auto_cluster(4, &ctrls->auto_exposure, V4L2_EXPOSURE_MANUAL,
+ 			       true);
+ 
+@@ -1386,125 +1630,11 @@ static int gc2145_setup_aec(struct gc2145_dev *sensor,
+ 	return gc2145_tx_commit(sensor);
+ }
+ 
+-struct gc2145_sensor_params {
+-	unsigned int enable_scaler;
+-	unsigned int col_scaler_only;
+-	unsigned int row_skip;
+-	unsigned int col_skip;
+-	unsigned long sh_delay;
+-	unsigned long hb;
+-	unsigned long vb;
+-	unsigned long st;
+-	unsigned long et;
+-	unsigned long win_width;
+-	unsigned long win_height;
+-	unsigned long width;
+-	unsigned long height;
+-};
+-
+-static void gc2145_sensor_params_init(struct gc2145_sensor_params* p, int width, int height)
+-{
+-	p->win_height = height + 32;
+-	p->win_width = (width + 16);
+-	p->width = width;
+-	p->height = height;
+-	p->st = 2;
+-	p->et = 2;
+-	p->vb = 8;
+-	p->hb = 0x1f0;
+-	p->sh_delay = 30;
+-}
+-
+-// unit is PCLK periods
+-static unsigned long
+-gc2145_sensor_params_get_row_period(struct gc2145_sensor_params* p)
+-{
+-	return 2 * (p->win_width / 2 / (p->col_skip + 1) + p->sh_delay + p->hb + 4);
+-}
+-
+-static unsigned long
+-gc2145_sensor_params_get_frame_period(struct gc2145_sensor_params* p)
+-{
+-	unsigned long rt = gc2145_sensor_params_get_row_period(p);
+-
+-	return rt * (p->vb + p->win_height) / (p->row_skip + 1);
+-}
+-
+-static void
+-gc2145_sensor_params_fit_hb_to_power_line_period(struct gc2145_sensor_params* p,
+-					  unsigned long power_line_freq,
+-					  unsigned long pclk)
+-{
+-	unsigned long rt, power_line_ratio;
+-
+-        for (p->hb = 0x1f0; p->hb < 2047; p->hb++) {
+-		rt = gc2145_sensor_params_get_row_period(p);
+-
+-		// power_line_ratio is row_freq / power_line_freq * 1000
+-                power_line_ratio = pclk / power_line_freq * 1000 / rt;
+-
+-		// if we're close enough, stop the search
+-                if (power_line_ratio % 1000 < 50)
+-                        break;
+-        }
+-
+-	// finding the optimal Hb is not critical
+-	if (p->hb == 2047)
+-		p->hb = 0x1f0;
+-}
+-
+-static void
+-gc2145_sensor_params_fit_vb_to_frame_period(struct gc2145_sensor_params* p,
+-				     unsigned long frame_period)
+-{
+-	unsigned long rt, fp;
+-
+-	p->vb = 8;
+-	rt = gc2145_sensor_params_get_row_period(p);
+-	fp = gc2145_sensor_params_get_frame_period(p);
+-
+-	if (frame_period > fp)
+-		p->vb = frame_period * (p->row_skip + 1) / rt - p->win_height;
+-
+-	if (p->vb > 4095)
+-		p->vb = 4095;
+-}
+-
+-static int gc2145_sensor_params_apply(struct gc2145_dev *sensor,
+-				      struct gc2145_sensor_params* p)
+-{
+-	u32 off_x = (GC2145_SENSOR_WIDTH_MAX - p->width) / 2;
+-	u32 off_y = (GC2145_SENSOR_HEIGHT_MAX - p->height) / 2;
+-
+-	gc2145_tx_start(sensor);
+-
+-	gc2145_tx_write8(sensor, 0xfd, (p->enable_scaler ? BIT(0) : 0)
+-			| (p->col_scaler_only ? BIT(1) : 0));
+-
+-	gc2145_tx_write8(sensor, 0x18, 0x0a
+-		       | (p->col_skip ? BIT(7) : 0)
+-		       | (p->row_skip ? BIT(6) : 0));
+-
+-	gc2145_tx_write16(sensor, 0x09, off_y);
+-	gc2145_tx_write16(sensor, 0x0b, off_x);
+-	gc2145_tx_write16(sensor, 0x0d, p->win_height);
+-	gc2145_tx_write16(sensor, 0x0f, p->win_width);
+-	gc2145_tx_write16(sensor, 0x05, p->hb);
+-	gc2145_tx_write16(sensor, 0x07, p->vb);
+-	gc2145_tx_write16(sensor, 0x11, p->sh_delay);
+-
+-	gc2145_tx_write8(sensor, 0x13, p->st);
+-	gc2145_tx_write8(sensor, 0x14, p->et);
+-
+-	return gc2145_tx_commit(sensor);
+-}
+-
+ static int gc2145_setup_mode(struct gc2145_dev *sensor)
+ {
+-	int scaling_desired, ret, pad, i;
+-	struct gc2145_sensor_params params = {0};
+-	unsigned long pclk2, frame_period;
+-	unsigned long power_line_freq = 50;
++	int ret, pad, i;
++	struct gc2145_sensor_params params;
++	unsigned long pclk2;
+ 	unsigned long width = sensor->fmt.width;
+ 	unsigned long height = sensor->fmt.height;
+ 	unsigned long framerate = sensor->frame_interval.denominator;
+@@ -1518,100 +1648,7 @@ static int gc2145_setup_mode(struct gc2145_dev *sensor)
+ 		return -EINVAL;
+ 	}
+ 
+-        /*
+-	 * Equations for calculating framerate are:
+-	 *
+-	 *    ww = width + 16
+-	 *    wh = height + 32
+-	 *    Rt = (ww / 2 / (col_skip + 1) + sh_delay + Hb + 4)
+-	 *    Ft = Rt * (Vb + wh) / (row_skip + 1)
+-	 *    framerate = 2pclk / 4 / Ft
+-	 *
+-	 * Based on these equations:
+-	 *
+-	 * 1) First we need to determine what 2PCLK frequency to use. The 2PCLK
+-	 *    frequency is not arbitrarily precise, so we need to calculate the
+-	 *    actual frequency used, after setting our target frequency.
+-	 *
+-	 *    We use a simple heuristic:
+-	 *
+-	 *      If pixel_count * 2 * framerate * 1.15 is > 40MHz, we use 60MHz,
+-	 *      otherwise we use 40MHz.
+-	 *
+-	 * 2) We want to determine lowest Hb that we can use to extend row
+-	 *    period so that row time takes an integer fraction of the power
+-	 *    line frequency period. Minimum Hb is 0x1f0.
+-	 *
+-	 * 3) If the requested resolution is less than half the sensor's size,
+-	 *    we'll use scaling, or row skipping + column scaling, or row and
+-	 *    column skiping, depending on what allows us to achieve the
+-	 *    requested framerate.
+-         *
+-	 * 4) We use the selected Hb to calculate Vb value that will give
+-	 *    us the desired framerate, given the scaling/skipping option
+-	 *    selected in 3).
+-	 */
+-
+-	scaling_desired = width <= GC2145_SENSOR_WIDTH_MAX / 2
+-			&& height <= GC2145_SENSOR_HEIGHT_MAX / 2;
+-
+-	pclk2 = 60000000;
+-
+-	ret = gc2145_set_2pclk(sensor, &pclk2, false);
+-	if (ret < 0)
+-		return ret;
+-
+-	gc2145_sensor_params_init(&params, width, height);
+-
+-	// if the resolution is < half the sensor size, enable the scaler
+-	// to cover more area of the chip
+-	if (scaling_desired) {
+-		params.enable_scaler = 1;
+-		pclk2 *= 2;
+-		gc2145_sensor_params_init(&params, width * 2, height * 2);
+-	}
+-
+-	// we need to call this each time pclk or power_line_freq is changed
+-	gc2145_sensor_params_fit_hb_to_power_line_period(&params,
+-							 power_line_freq,
+-							 pclk2 / 2);
+-
+-	frame_period = gc2145_sensor_params_get_frame_period(&params);
+-	if (framerate <= pclk2 / 2 / frame_period)
+-		goto apply;
+-
+-	if (scaling_desired) {
+-		// try using just the column scaler + row skip
+-		params.col_scaler_only = 1;
+-		params.row_skip = 1;
+-		gc2145_sensor_params_fit_hb_to_power_line_period(&params,
+-								 power_line_freq,
+-								 pclk2 / 2);
+-
+-		frame_period = gc2145_sensor_params_get_frame_period(&params);
+-		if (framerate <= pclk2 / 2 / frame_period)
+-			goto apply;
+-
+-
+-		/*
+-		// try disabling the scaler and just use skipping
+-		params.enable_scaler = 0;
+-		pclk2 /= 2;
+-		params.col_scaler_only = 0;
+-		params.col_skip = 1;
+-		gc2145_sensor_params_fit_hb_to_power_line_period(&params, power_line_freq, pclk2 / 2);
+-
+-		frame_period = gc2145_sensor_params_get_frame_period(&params);
+-
+-		if (framerate <= pclk2 / 2 / frame_period)
+-			goto apply;
+-                  */
+-	}
+-
+-apply:
+-        // adjust vb to fit the target framerate
+-	gc2145_sensor_params_fit_vb_to_frame_period(&params,
+-						    pclk2 / 2 / framerate);
++	params = gc2145_get_sensor_params(framerate, width, height, &pclk2);
+ 
+ 	gc2145_sensor_params_apply(sensor, &params);
+ 
+@@ -1845,6 +1882,8 @@ static int gc2145_set_fmt(struct v4l2_subdev *sd,
+ 	struct gc2145_dev *sensor = to_gc2145_dev(sd);
+ 	struct v4l2_mbus_framefmt *mf = &format->format;
+ 	const struct gc2145_pixfmt *pixfmt;
++	struct gc2145_sensor_params params;
++	unsigned long pixel_rate;
+ 	int ret = 0;
+ 
+ 	if (format->pad != 0)
+@@ -1884,6 +1923,14 @@ static int gc2145_set_fmt(struct v4l2_subdev *sd,
+ 
+ 	sensor->fmt = *mf;
+ 	sensor->pending_mode_change = true;
++
++	params = gc2145_get_sensor_params(sensor->frame_interval.denominator, mf->width, mf->height, &pixel_rate);
++	__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
++				 pixel_rate);
++	__v4l2_ctrl_s_ctrl(sensor->ctrls.hblank,
++			   params.win_height);
++	__v4l2_ctrl_s_ctrl(sensor->ctrls.vblank,
++			   params.win_width);
+ out:
+ 	mutex_unlock(&sensor->lock);
+ 	return ret;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
new file mode 100644
index 000000000000..b3e26d927e54
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
@@ -0,0 +1,30 @@
+From 1cde7b66473d90d9735edf451a7b8359e1dfc6a4 Mon Sep 17 00:00:00 2001
+From: Martijn Braam <martijn@brixit.nl>
+Date: Fri, 4 Sep 2020 17:35:39 +0200
+Subject: media: gc2145: Added BGGR bayer mode
+
+Not all raw bayer modes from the sensor match up with the ones defined
+in v4l, mostly because they're mirrored.
+---
+ drivers/media/i2c/gc2145.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index cc85ac772d5a..7539b122eeef 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -187,6 +187,11 @@ static const struct gc2145_pixfmt gc2145_formats[] = {
+ 		.colorspace        = V4L2_COLORSPACE_SRGB,
+ 		.fmt_setup         = 0x06,
+ 	},
++	{
++		.code              = MEDIA_BUS_FMT_SBGGR8_1X8,
++		.colorspace        = V4L2_COLORSPACE_RAW,
++		.fmt_setup         = 0x17,
++	},
+ };
+ 
+ static const struct gc2145_pixfmt *gc2145_find_format(u32 code)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Disable-debug-output.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Disable-debug-output.patch
new file mode 100644
index 000000000000..31a52733c83c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Disable-debug-output.patch
@@ -0,0 +1,37 @@
+From 9b77955f03b097f493c1d8730232509c95c95d19 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 27 Oct 2021 17:22:51 +0200
+Subject: media: gc2145: Disable debug output
+
+People don't like it. Hmm...
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/gc2145.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index 7539b122eeef..df15b72651e2 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -8,7 +8,7 @@
+  * (at your option) any later version.
+  */
+ 
+-#define DEBUG
++//#define DEBUG
+ 
+ #include <asm/div64.h>
+ #include <linux/clk.h>
+@@ -374,7 +374,7 @@ static int gc2145_switch_bank(struct gc2145_dev *sensor, u16 reg)
+ 			return ret;
+ 
+ 		sensor->current_bank = bank;
+-		dev_info(&sensor->i2c_client->dev, "bank switch: 0x%02x\n",
++		dev_dbg(&sensor->i2c_client->dev, "bank switch: 0x%02x\n",
+ 				(unsigned int)sensor->current_bank);
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
new file mode 100644
index 000000000000..cc899b85a93d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
@@ -0,0 +1,2306 @@
+From 2808238f2fb2c8e4554d8bd968ea0cf74cfd44fd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:51:18 +0200
+Subject: media: gc2145: Galaxycore camera module driver
+
+WIP!
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/Kconfig  |   10 +
+ drivers/media/i2c/Makefile |    1 +
+ drivers/media/i2c/gc2145.c | 2252 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 2263 insertions(+)
+ create mode 100644 drivers/media/i2c/gc2145.c
+
+diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
+index 1b5f112a705a..709f51169eeb 100644
+--- a/drivers/media/i2c/Kconfig
++++ b/drivers/media/i2c/Kconfig
+@@ -678,6 +678,16 @@ config VIDEO_HM5065
+ 	  This is a V4L2 sensor-level driver for Himax HM5065
+ 	  5 Mpixel camera.
+ 
++config VIDEO_GC2145
++	tristate "GalaxyCore GC2145 sensor support"
++	depends on I2C
++	select V4L2_FWNODE
++	select VIDEO_V4L2_SUBDEV_API
++	select MEDIA_CONTROLLER
++	help
++	  This is a V4L2 sensor-level driver for GalaxyCore GC2145
++	  2 Mpixel camera.
++
+ endif
+ 
+ menu "Camera ISPs"
+diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
+index e84186ed81cb..0576c8962839 100644
+--- a/drivers/media/i2c/Makefile
++++ b/drivers/media/i2c/Makefile
+@@ -153,3 +153,4 @@ obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o
+ obj-$(CONFIG_VIDEO_WM8739) += wm8739.o
+ obj-$(CONFIG_VIDEO_WM8775) += wm8775.o
+ obj-$(CONFIG_VIDEO_HM5065)	+= hm5065.o
++obj-$(CONFIG_VIDEO_GC2145)	+= gc2145.o
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+new file mode 100644
+index 000000000000..cc85ac772d5a
+--- /dev/null
++++ b/drivers/media/i2c/gc2145.c
+@@ -0,0 +1,2252 @@
++/*
++ * Galaxycore GC2145 driver.
++ * Copyright (C) 2018 Ondřej Jirman <megi@xff.cz>.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#define DEBUG
++
++#include <asm/div64.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/clkdev.h>
++#include <linux/ctype.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/firmware.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++#include <media/v4l2-subdev.h>
++
++/*
++ * GC2145
++ * - 2M pixel
++ * - 1600 x 1200, max frame rate: 720P, 30fps@96MHz
++ * - Bayer RGB, RGB565, YCbCr 4:2:2
++ * - AE, AWB
++ * - PLL
++ * - AVDD 2.7-3V, DVDD 1.7-1.9V, IOVDD 1.7-3V
++ * - Power 180mW / 200uA standby
++ * - Interpolation, denoise, gamma, edge enhance
++ * I2C:
++ * - write reg8
++ * - read reg8
++ * - write reg8 multi
++ *
++ * Power on:
++ * MCLK on
++ * PWDN, RESET low
++ * IOVDD, AVDD, DVDD on in sequence
++ * RESET high
++ *
++ * Power off:
++ * PWDN, RESET low
++ * RESET high
++ * delay
++ * PWDN high
++ * RESET low
++ * IOVDD, AVDD, DVDD off
++ * PWDN low?
++ * MCLK off
++ *
++ * Init:
++ * - check chip id
++ * - setup pll
++ * - setup CSI interface / PAD drive strength
++ * - setup resolution/fps
++ * - enable postprocessing
++ *   (ISP related chapter)
++ *
++ * Stream on:
++ * - ???
++ */
++
++#define GC2145_FIRMWARE_PARAMETERS	"gc2145-init.bin"
++
++#define GC2145_SENSOR_WIDTH_MIN		88u
++#define GC2145_SENSOR_HEIGHT_MIN	72u
++
++//XXX: 1616x1232 8H/16V dummy pixels on each side
++#define GC2145_SENSOR_WIDTH_MAX		1600u
++#define GC2145_SENSOR_HEIGHT_MAX	1200u
++
++/* {{{ Register definitions */
++
++/* system registers */
++#define GC2145_REG_CHIP_ID			0xf0
++#define GC2145_REG_CHIP_ID_VALUE		0x2145
++
++#define GC2145_REG_PAD_IO		0xf2
++#define GC2145_REG_PLL_MODE1		0xf7
++#define GC2145_REG_PLL_MODE2		0xf8
++#define GC2145_REG_CM_MODE		0xf9
++#define GC2145_REG_CLK_DIV_MODE		0xfa
++#define GC2145_REG_ANALOG_PWC		0xfc
++#define GC2145_REG_SCALER_MODE		0xfd
++#define GC2145_REG_RESET		0xfe
++
++#define GC2145_P0_EXPOSURE_HI		0x03
++#define GC2145_P0_EXPOSURE_LO		0x04
++#define GC2145_P0_HBLANK_DELAY_HI	0x05
++#define GC2145_P0_HBLANK_DELAY_LO	0x06
++#define GC2145_P0_VBLANK_DELAY_HI	0x07
++#define GC2145_P0_VBLANK_DELAY_LO	0x08
++#define GC2145_P0_ROW_START_HI		0x09
++#define GC2145_P0_ROW_START_LO		0x0a
++#define GC2145_P0_COL_START_HI		0x0b
++#define GC2145_P0_COL_START_LO		0x0c
++#define GC2145_P0_WIN_HEIGHT_HI		0x0d
++#define GC2145_P0_WIN_HEIGHT_LO		0x0e
++#define GC2145_P0_WIN_WIDTH_HI		0x0f
++#define GC2145_P0_WIN_WIDTH_LO		0x10
++#define GC2145_P0_SH_DELAY_HI		0x11
++#define GC2145_P0_SH_DELAY_LO		0x12
++#define GC2145_P0_START_TIME		0x13
++#define GC2145_P0_END_TIME		0x14
++
++#define GC2145_P0_ISP_BLK_ENABLE1	0x80
++#define GC2145_P0_ISP_BLK_ENABLE2	0x81
++#define GC2145_P0_ISP_BLK_ENABLE3	0x82
++#define GC2145_P0_ISP_SPECIAL_EFFECT	0x83
++#define GC2145_P0_ISP_OUT_FORMAT	0x84
++#define GC2145_P0_FRAME_START		0x85
++#define GC2145_P0_SYNC_MODE		0x86
++#define GC2145_P0_ISP_BLK_ENABLE4	0x87
++#define GC2145_P0_ISP_MODULE_GATING	0x88
++#define GC2145_P0_ISP_BYPASS_MODE	0x89
++#define GC2145_P0_DEBUG_MODE2		0x8c
++#define GC2145_P0_DEBUG_MODE3		0x8d
++
++#define GC2145_P0_CROP_ENABLE		0x90
++#define GC2145_P0_CROP_Y1_HI		0x91
++#define GC2145_P0_CROP_Y1_LO		0x92
++#define GC2145_P0_CROP_X1_HI		0x93
++#define GC2145_P0_CROP_X1_LO		0x94
++#define GC2145_P0_CROP_WIN_HEIGHT_HI	0x95
++#define GC2145_P0_CROP_WIN_HEIGHT_LO	0x96
++#define GC2145_P0_CROP_WIN_WIDTH_HI	0x97
++#define GC2145_P0_CROP_WIN_WIDTH_LO	0x98
++
++#define GC2145_P0_SUBSAMPLE_RATIO	0x99
++#define GC2145_P0_SUBSAMPLE_MODE	0x9a
++#define GC2145_P0_SUB_ROW_N1		0x9b
++#define GC2145_P0_SUB_ROW_N2		0x9c
++#define GC2145_P0_SUB_ROW_N3		0x9d
++#define GC2145_P0_SUB_ROW_N4		0x9e
++#define GC2145_P0_SUB_COL_N1		0x9f
++#define GC2145_P0_SUB_COL_N2		0xa0
++#define GC2145_P0_SUB_COL_N3		0xa1
++#define GC2145_P0_SUB_COL_N4		0xa2
++#define GC2145_P0_OUT_BUF_ENABLE	0xc2
++
++/* }}} */
++
++struct gc2145_pixfmt {
++	u32 code;
++	u32 colorspace;
++	u8 fmt_setup;
++};
++
++static const struct gc2145_pixfmt gc2145_formats[] = {
++	{
++		.code              = MEDIA_BUS_FMT_UYVY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x00,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_VYUY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x01,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x02,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x03,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_RGB565_2X8_LE,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x06,
++	},
++};
++
++static const struct gc2145_pixfmt *gc2145_find_format(u32 code)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(gc2145_formats); i++)
++		if (gc2145_formats[i].code == code)
++			return &gc2145_formats[i];
++
++	return NULL;
++}
++
++/* regulator supplies */
++static const char * const gc2145_supply_name[] = {
++	"IOVDD", /* Digital I/O (1.7-3V) suppply */
++	"AVDD",  /* Analog (2.7-3V) supply */
++	"DVDD",  /* Digital Core (1.7-1.9V) supply */
++};
++
++#define GC2145_NUM_SUPPLIES ARRAY_SIZE(gc2145_supply_name)
++
++struct gc2145_ctrls {
++	struct v4l2_ctrl_handler handler;
++	struct {
++		struct v4l2_ctrl *auto_exposure;
++		struct v4l2_ctrl *exposure;
++		struct v4l2_ctrl *d_gain;
++		struct v4l2_ctrl *a_gain;
++	};
++	struct v4l2_ctrl *metering;
++	struct v4l2_ctrl *exposure_bias;
++	struct {
++		struct v4l2_ctrl *wb;
++		struct v4l2_ctrl *blue_balance;
++		struct v4l2_ctrl *red_balance;
++	};
++	struct v4l2_ctrl *aaa_lock;
++	struct v4l2_ctrl *hflip;
++	struct v4l2_ctrl *vflip;
++	struct v4l2_ctrl *pl_freq;
++	struct v4l2_ctrl *colorfx;
++	struct v4l2_ctrl *brightness;
++	struct v4l2_ctrl *saturation;
++	struct v4l2_ctrl *contrast;
++	struct v4l2_ctrl *gamma;
++	struct v4l2_ctrl *test_pattern;
++	struct v4l2_ctrl *test_data[4];
++};
++
++enum {
++	TX_WRITE = 1,
++	TX_WRITE16,
++	TX_UPDATE_BITS,
++};
++
++#define GC2145_MAX_OPS 64
++
++struct gc2145_tx_op {
++	int op;
++	u16 reg;
++	u16 val;
++	u16 mask;
++};
++
++struct gc2145_dev {
++	struct i2c_client *i2c_client;
++	struct v4l2_subdev sd;
++	struct media_pad pad;
++	struct v4l2_fwnode_endpoint ep; /* the parsed DT endpoint info */
++	struct clk *xclk; /* external clock for GC2145 */
++
++	struct regulator_bulk_data supplies[GC2145_NUM_SUPPLIES];
++	struct gpio_desc *reset_gpio; // nrst pin
++	struct gpio_desc *enable_gpio; // ce pin
++
++	/* lock to protect all members below */
++	struct mutex lock;
++
++	struct v4l2_mbus_framefmt fmt;
++	struct v4l2_fract frame_interval;
++	struct gc2145_ctrls ctrls;
++
++	bool pending_mode_change;
++	bool powered;
++	bool streaming;
++
++	u8 current_bank;
++
++	struct gc2145_tx_op ops[GC2145_MAX_OPS];
++	int n_ops;
++	int tx_started;
++};
++
++static inline struct gc2145_dev *to_gc2145_dev(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct gc2145_dev, sd);
++}
++
++/* {{{ Register access helpers */
++
++static int gc2145_write_regs(struct gc2145_dev *sensor, u8 addr,
++			     u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg;
++	u8 buf[128 + 1];
++	int ret;
++
++	if (data_size > sizeof(buf) - 1) {
++		v4l2_err(&sensor->sd, "%s: oversized transfer (size=%d)\n",
++			 __func__, data_size);
++		return -EINVAL;
++	}
++
++	buf[0] = addr;
++	memcpy(buf + 1, data, data_size);
++
++	msg.addr = client->addr;
++	msg.flags = client->flags;
++	msg.buf = buf;
++	msg.len = data_size + 1;
++
++	dev_dbg(&sensor->i2c_client->dev, "[wr %02x] <= %*ph\n",
++		(u32)addr, data_size, data);
++
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: addr=%x, data=%*ph\n",
++			 __func__, ret, (u32)addr, data_size, data);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int gc2145_read_regs(struct gc2145_dev *sensor, u8 addr,
++			    u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg[2];
++	int ret;
++
++	msg[0].addr = client->addr;
++	msg[0].flags = client->flags;
++	msg[0].buf = &addr;
++	msg[0].len = 1;
++
++	msg[1].addr = client->addr;
++	msg[1].flags = client->flags | I2C_M_RD;
++	msg[1].buf = data;
++	msg[1].len = data_size;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: start_index=%x, data_size=%d\n",
++			 __func__, ret, (u32)addr, data_size);
++		return ret;
++	}
++
++	dev_dbg(&sensor->i2c_client->dev, "[rd %02x] => %*ph\n",
++		(u32)addr, data_size, data);
++
++	return 0;
++}
++
++static int gc2145_switch_bank(struct gc2145_dev *sensor, u16 reg)
++{
++	int ret;
++	u8 bank = reg >> 8;
++
++	if (bank & ~3u)
++		return -ERANGE;
++
++	if (sensor->current_bank != bank) {
++		ret = gc2145_write_regs(sensor, GC2145_REG_RESET, &bank, 1);
++		if (ret)
++			return ret;
++
++		sensor->current_bank = bank;
++		dev_info(&sensor->i2c_client->dev, "bank switch: 0x%02x\n",
++				(unsigned int)sensor->current_bank);
++	}
++
++	return 0;
++}
++
++static int gc2145_read(struct gc2145_dev *sensor, u16 reg, u8 *val)
++{
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	return gc2145_read_regs(sensor, reg, val, 1);
++}
++
++static int gc2145_write(struct gc2145_dev *sensor, u16 reg, u8 val)
++{
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	if ((reg & 0xffu) == GC2145_REG_RESET)
++		sensor->current_bank = val & 3;
++
++	return gc2145_write_regs(sensor, reg, &val, 1);
++}
++
++static int gc2145_update_bits(struct gc2145_dev *sensor, u16 reg, u8 mask, u8 val)
++{
++	int ret;
++	u8 tmp;
++
++	ret = gc2145_read(sensor, reg, &tmp);
++	if (ret)
++		return ret;
++
++	tmp &= ~mask;
++	tmp |= val & mask;
++
++	return gc2145_write(sensor, reg, tmp);
++}
++
++static int gc2145_read16(struct gc2145_dev *sensor, u16 reg, u16 *val)
++{
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read_regs(sensor, reg, (u8 *)val, sizeof(*val));
++	if (ret)
++		return ret;
++
++	*val = be16_to_cpu(*val);
++	return 0;
++}
++
++static int gc2145_write16(struct gc2145_dev *sensor, u16 reg, u16 val)
++{
++	u16 tmp = cpu_to_be16(val);
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	return gc2145_write_regs(sensor, reg, (u8 *)&tmp, sizeof(tmp));
++}
++
++static void gc2145_tx_start(struct gc2145_dev *sensor)
++{
++	if (sensor->tx_started++)
++		dev_err(&sensor->i2c_client->dev,
++				"tx_start called multiple times\n");
++
++	sensor->n_ops = 0;
++}
++
++static void gc2145_tx_add(struct gc2145_dev *sensor, int kind,
++			  u16 reg, u16 val, u16 mask)
++{
++	struct gc2145_tx_op *op;
++
++	if (!sensor->tx_started) {
++		dev_err(&sensor->i2c_client->dev,
++				"op added without calling tx_start\n");
++		return;
++	}
++
++	if (sensor->n_ops >= ARRAY_SIZE(sensor->ops)) {
++		dev_err(&sensor->i2c_client->dev,
++				"ops overflow, increase GC2145_MAX_OPS\n");
++		return;
++	}
++
++	op = &sensor->ops[sensor->n_ops++];
++	op->op = kind;
++	op->reg = reg;
++	op->val = val;
++	op->mask = mask;
++}
++
++static void gc2145_tx_write8(struct gc2145_dev *sensor, u16 reg, u8 val)
++{
++	return gc2145_tx_add(sensor, TX_WRITE, reg, val, 0);
++}
++
++static void gc2145_tx_write16(struct gc2145_dev *sensor, u16 reg, u16 val)
++{
++	return gc2145_tx_add(sensor, TX_WRITE16, reg, val, 0);
++}
++
++static void gc2145_tx_update_bits(struct gc2145_dev *sensor, u16 reg,
++				  u8 mask, u8 val)
++{
++	return gc2145_tx_add(sensor, TX_UPDATE_BITS, reg, val, mask);
++}
++
++static int gc2145_tx_commit(struct gc2145_dev *sensor)
++{
++	struct gc2145_tx_op* op;
++	int i, ret, n_ops;
++
++	if (!sensor->tx_started) {
++		dev_err(&sensor->i2c_client->dev,
++				"tx_commit called without tx_start\n");
++		return 0;
++	}
++
++	n_ops = sensor->n_ops;
++	sensor->tx_started = 0;
++	sensor->n_ops = 0;
++
++	for (i = 0; i < n_ops; i++) {
++		op = &sensor->ops[i];
++
++		switch (op->op) {
++		case TX_WRITE:
++			ret = gc2145_write(sensor, op->reg, op->val);
++			break;
++		case TX_WRITE16:
++			ret = gc2145_write16(sensor, op->reg, op->val);
++			break;
++		case TX_UPDATE_BITS:
++			ret = gc2145_update_bits(sensor, op->reg, op->mask, op->val);
++			break;
++		default:
++			dev_err(&sensor->i2c_client->dev, "invalid op at %d\n", i);
++			ret = -EINVAL;
++		}
++
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++/*
++ * Efficiently write to a set of registers, using auto-increment
++ * when possible. User must not use address 0xff. To switch banks,
++ * use sequence: 0xfe, bank_no.
++ */
++static int gc2145_set_registers(struct gc2145_dev *sensor,
++				const uint8_t* data, size_t data_len)
++{
++	int ret = 0, i = 0;
++	u16 start, len;
++	u8 buf[128];
++
++	if (data_len % 2 != 0) {
++		v4l2_err(&sensor->sd, "Register map has invalid size\n");
++		return -EINVAL;
++	}
++
++	/* we speed up communication by using auto-increment functionality */
++	while (i < data_len) {
++		start = data[i];
++		len = 0;
++
++		while (i < data_len && data[i] == (start + len) &&
++		       len < sizeof(buf)) {
++			buf[len++] = data[i + 1];
++			i += 2;
++		}
++
++		ret = gc2145_write_regs(sensor, start, buf, len);
++		if (ret)
++			return ret;
++	}
++
++	sensor->current_bank = 0xff;
++	return 0;
++}
++
++/*
++ * The firmware format:
++ * <record 0>, ..., <record N - 1>
++ * "record" is a 1-byte register address followed by 1-byte data
++ */
++static int gc2145_load_firmware(struct gc2145_dev *sensor, const char *name)
++{
++	const struct firmware *fw;
++	int ret;
++
++	ret = request_firmware(&fw, name, sensor->sd.v4l2_dev->dev);
++	if (ret) {
++		v4l2_warn(&sensor->sd,
++			  "Failed to read firmware %s, continuing anyway...\n",
++			  name);
++		return 1;
++	}
++
++	if (fw->size == 0)
++		return 1;
++
++	ret = gc2145_set_registers(sensor, fw->data, fw->size);
++
++	release_firmware(fw);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Controls */
++
++static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct gc2145_dev,
++			     ctrls.handler)->sd;
++}
++
++#if 0
++static const u8 gc2145_wb_opts[][2] = {
++	{ V4L2_WHITE_BALANCE_MANUAL, GC2145_REG_WB_MODE_OFF },
++	{ V4L2_WHITE_BALANCE_INCANDESCENT, GC2145_REG_WB_MODE_TUNGSTEN_PRESET },
++	{ V4L2_WHITE_BALANCE_FLUORESCENT,
++		GC2145_REG_WB_MODE_FLUORESCENT_PRESET },
++	{ V4L2_WHITE_BALANCE_HORIZON, GC2145_REG_WB_MODE_HORIZON_PRESET },
++	{ V4L2_WHITE_BALANCE_CLOUDY, GC2145_REG_WB_MODE_CLOUDY_PRESET },
++	{ V4L2_WHITE_BALANCE_DAYLIGHT, GC2145_REG_WB_MODE_SUNNY_PRESET },
++	{ V4L2_WHITE_BALANCE_AUTO, GC2145_REG_WB_MODE_AUTOMATIC },
++};
++
++static int gc2145_set_power_line_frequency(struct gc2145_dev *sensor, s32 val)
++{
++	u16 freq;
++	int ret;
++
++	switch (val) {
++	case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
++		ret = gc2145_write(sensor, GC2145_REG_ANTI_FLICKER_MODE, 0);
++		if (ret)
++			return ret;
++
++		return gc2145_write(sensor, GC2145_REG_FD_ENABLE_DETECT, 0);
++	case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
++	case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
++		ret = gc2145_write(sensor, GC2145_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write(sensor, GC2145_REG_FD_ENABLE_DETECT, 0);
++		if (ret)
++			return ret;
++
++		freq = (val == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) ?
++			0x4b20 : 0x4bc0;
++
++		return gc2145_write16(sensor, GC2145_REG_FD_FLICKER_FREQUENCY,
++				      freq);
++	case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
++		ret = gc2145_write(sensor, GC2145_REG_FD_ENABLE_DETECT, 1);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write(sensor, GC2145_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write16(sensor, GC2145_REG_FD_MAX_NUMBER_ATTEMP,
++				     100);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write16(sensor, GC2145_REG_FD_FLICKER_FREQUENCY,
++				     0);
++		if (ret)
++			return ret;
++
++		return gc2145_write(sensor, GC2145_REG_FD_DETECTION_START, 1);
++	default:
++		return -EINVAL;
++	}
++}
++
++static int gc2145_set_colorfx(struct gc2145_dev *sensor, s32 val)
++{
++	int ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++			   GC2145_REG_EFFECTS_COLOR_NORMAL);
++	if (ret)
++		return ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_NEGATIVE, 0);
++	if (ret)
++		return ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_SOLARISING, 0);
++	if (ret)
++		return ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_SKECTH, 0);
++	if (ret)
++		return ret;
++
++	switch (val) {
++	case V4L2_COLORFX_NONE:
++		return 0;
++	case V4L2_COLORFX_NEGATIVE:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_NEGATIVE, 1);
++	case V4L2_COLORFX_SOLARIZATION:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_SOLARISING, 1);
++	case V4L2_COLORFX_SKETCH:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_SKECTH, 1);
++	case V4L2_COLORFX_ANTIQUE:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_ANTIQUE);
++	case V4L2_COLORFX_SEPIA:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_SEPIA);
++	case V4L2_COLORFX_AQUA:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_AQUA);
++	case V4L2_COLORFX_BW:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_BLACK_WHITE);
++	default:
++		return -EINVAL;
++	}
++}
++
++static int gc2145_3a_lock(struct gc2145_dev *sensor, struct v4l2_ctrl *ctrl)
++{
++	bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
++	bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
++	int ret = 0;
++
++	if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE
++	    && sensor->ctrls.auto_exposure->val == V4L2_EXPOSURE_AUTO) {
++		ret = gc2145_write(sensor, GC2145_REG_FREEZE_AUTO_EXPOSURE,
++				   ae_lock);
++		if (ret)
++			return ret;
++	}
++
++	if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE)
++	    && sensor->ctrls.wb->val == V4L2_WHITE_BALANCE_AUTO) {
++		ret = gc2145_write(sensor, GC2145_REG_WB_MISC_SETTINGS,
++				   awb_lock ?
++				   GC2145_REG_WB_MISC_SETTINGS_FREEZE_ALGO : 0);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int gc2145_set_white_balance(struct gc2145_dev *sensor)
++{
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	bool manual_wb = ctrls->wb->val == V4L2_WHITE_BALANCE_MANUAL;
++	int ret = 0, i;
++	s32 val;
++
++	if (ctrls->wb->is_new) {
++		for (i = 0; i < ARRAY_SIZE(gc2145_wb_opts); i++) {
++			if (gc2145_wb_opts[i][0] != ctrls->wb->val)
++				continue;
++
++			ret = gc2145_write(sensor, GC2145_REG_WB_MODE,
++					    gc2145_wb_opts[i][1]);
++			if (ret)
++				return ret;
++			goto next;
++		}
++
++		return -EINVAL;
++	}
++
++next:
++	if (ctrls->wb->is_new || ctrls->blue_balance->is_new) {
++		val = manual_wb ? ctrls->blue_balance->val : 1000;
++		ret = gc2145_write16(sensor, GC2145_REG_WB_HUE_B_BIAS,
++				     gc2145_mili_to_fp16(val));
++		if (ret)
++			return ret;
++	}
++
++	if (ctrls->wb->is_new || ctrls->red_balance->is_new) {
++		val = manual_wb ? ctrls->red_balance->val : 1000;
++		ret = gc2145_write16(sensor, GC2145_REG_WB_HUE_R_BIAS,
++				     gc2145_mili_to_fp16(val));
++	}
++
++	return ret;
++}
++
++#endif
++
++/* Exposure */
++
++static int gc2145_get_exposure(struct gc2145_dev *sensor)
++{
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	u8 again, dgain;
++	u16 exp;
++	int ret;
++
++	ret = gc2145_read(sensor, 0xb1, &again);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read(sensor, 0xb2, &dgain);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read16(sensor, 0x03, &exp);
++	if (ret)
++		return ret;
++
++	ctrls->exposure->val = exp;
++	ctrls->d_gain->val = dgain;
++	ctrls->a_gain->val = again;
++
++	return 0;
++}
++
++#define AE_BIAS_MENU_DEFAULT_VALUE_INDEX 4
++static const s64 ae_bias_menu_values[] = {
++	-4000, -3000, -2000, -1000, 0, 1000, 2000, 3000, 4000
++};
++
++static const s8 ae_bias_menu_reg_values[] = {
++	0x55, 0x60, 0x65, 0x70, 0x7b, 0x85, 0x90, 0x95, 0xa0
++};
++
++static int gc2145_set_exposure(struct gc2145_dev *sensor)
++{
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	bool is_auto = (ctrls->auto_exposure->val != V4L2_EXPOSURE_MANUAL);
++
++	gc2145_tx_start(sensor);
++
++	if (ctrls->auto_exposure->is_new) {
++		gc2145_tx_write8(sensor, 0xb6, is_auto ? 1 : 0);
++
++		//XXX: remove?
++		//if (ctrls->auto_exposure->cur.val != ctrls->auto_exposure->val &&
++		    //!is_auto) {
++			/*
++			 * Hack: At this point, there are current volatile
++			 * values in val, but control framework will not
++			 * update the cur values for our autocluster, as it
++			 * should. I couldn't find the reason. This fixes
++			 * it for our driver. Remove this after the kernel
++			 * is fixed.
++			 */
++			//ctrls->exposure->cur.val = ctrls->exposure->val;
++			//ctrls->d_gain->cur.val = ctrls->d_gain->val;
++			//ctrls->a_gain->cur.val = ctrls->a_gain->val;
++		//}
++	}
++
++	if (!is_auto && ctrls->exposure->is_new)
++		gc2145_tx_write16(sensor, 0x03, ctrls->exposure->val);
++
++	if (!is_auto && ctrls->d_gain->is_new)
++		gc2145_tx_write8(sensor, 0xb2, ctrls->d_gain->val);
++
++	if (!is_auto && ctrls->a_gain->is_new)
++		gc2145_tx_write8(sensor, 0xb1, ctrls->a_gain->val);
++
++	return gc2145_tx_commit(sensor);;
++}
++
++/* Test patterns */
++
++enum {
++	GC2145_TEST_PATTERN_DISABLED,
++	GC2145_TEST_PATTERN_VGA_COLOR_BARS,
++	GC2145_TEST_PATTERN_UXGA_COLOR_BARS,
++	GC2145_TEST_PATTERN_SKIN_MAP,
++	GC2145_TEST_PATTERN_SOLID_COLOR,
++};
++
++static const char * const test_pattern_menu[] = {
++	"Disabled",
++	"VGA color bars",
++	"UXGA color bars",
++	"Skin map",
++	"Solid black color",
++	"Solid light gray color",
++	"Solid gray color",
++	"Solid dark gray color",
++	"Solid white color",
++	"Solid red color",
++	"Solid green color",
++	"Solid blue color",
++	"Solid yellow color",
++	"Solid cyan color",
++	"Solid magenta color",
++};
++
++static int gc2145_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	if (!sensor->powered)
++		return -EIO;
++
++	switch (ctrl->id) {
++	case V4L2_CID_EXPOSURE_AUTO:
++		ret = gc2145_get_exposure(sensor);
++		if (ret)
++			return ret;
++		break;
++	default:
++		dev_err(&sensor->i2c_client->dev, "getting unknown control %d\n", ctrl->id);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int gc2145_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	s32 val = ctrl->val;
++	unsigned int i;
++	int ret;
++	u8 test1, test2;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	/*
++	 * If the device is not powered up by the host driver do
++	 * not apply any controls to H/W at this time. Instead
++	 * the controls will be restored right after power-up.
++	 */
++	if (!sensor->powered)
++		return 0;
++
++	switch (ctrl->id) {
++	case V4L2_CID_EXPOSURE_AUTO:
++		return gc2145_set_exposure(sensor);
++
++	case V4L2_CID_AUTO_EXPOSURE_BIAS:
++		if (val < 0 || val >= ARRAY_SIZE(ae_bias_menu_reg_values)) {
++			dev_err(&sensor->i2c_client->dev, "ae bias out of range\n");
++			return -EINVAL;
++		}
++
++		return gc2145_write(sensor, 0x113,
++				    (u8)ae_bias_menu_reg_values[val]);
++
++	case V4L2_CID_VFLIP:
++		return gc2145_update_bits(sensor, 0x17, BIT(1), val ? BIT(1) : 0);
++
++	case V4L2_CID_HFLIP:
++		return gc2145_update_bits(sensor, 0x17, BIT(0), val ? BIT(0) : 0);
++
++	case V4L2_CID_TEST_PATTERN:
++		for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++			v4l2_ctrl_activate(ctrls->test_data[i],
++					   val == 6); /* solid color */
++
++		test1 = 0;
++		test2 = 0x01;
++
++		if (val == GC2145_TEST_PATTERN_VGA_COLOR_BARS)
++			test1 = 0x04;
++		else if (val == GC2145_TEST_PATTERN_UXGA_COLOR_BARS)
++			test1 = 0x44;
++		else if (val == GC2145_TEST_PATTERN_SKIN_MAP)
++			test1 = 0x10;
++		else if (val >= GC2145_TEST_PATTERN_SOLID_COLOR) {
++			test1 = 0x04;
++			test2 = ((val - GC2145_TEST_PATTERN_SOLID_COLOR) << 4) | 0x8;
++		} else if (val != GC2145_TEST_PATTERN_DISABLED) {
++			dev_err(&sensor->i2c_client->dev, "test pattern out of range\n");
++			return -EINVAL;
++		}
++
++		ret = gc2145_write(sensor, 0x8c, test1);
++		if (ret)
++			return ret;
++
++		return gc2145_write(sensor, 0x8d, test2);
++
++#if 0
++	case V4L2_CID_EXPOSURE_METERING:
++		if (val == V4L2_EXPOSURE_METERING_AVERAGE)
++			reg = GC2145_REG_EXPOSURE_METERING_FLAT;
++		else if (val == V4L2_EXPOSURE_METERING_CENTER_WEIGHTED)
++			reg = GC2145_REG_EXPOSURE_METERING_CENTERED;
++		else
++			return -EINVAL;
++
++		return gc2145_write(sensor, GC2145_REG_EXPOSURE_METERING, reg);
++
++	case V4L2_CID_CONTRAST:
++		return gc2145_write(sensor, GC2145_REG_CONTRAST, val);
++
++	case V4L2_CID_SATURATION:
++		return gc2145_write(sensor, GC2145_REG_COLOR_SATURATION, val);
++
++	case V4L2_CID_BRIGHTNESS:
++		return gc2145_write(sensor, GC2145_REG_BRIGHTNESS, val);
++
++	case V4L2_CID_POWER_LINE_FREQUENCY:
++		return gc2145_set_power_line_frequency(sensor, val);
++
++	case V4L2_CID_GAMMA:
++		return gc2145_write(sensor, GC2145_REG_P0_GAMMA_GAIN, val);
++
++	case V4L2_CID_COLORFX:
++		return gc2145_set_colorfx(sensor, val);
++
++	case V4L2_CID_3A_LOCK:
++		return gc2145_3a_lock(sensor, ctrl);
++
++	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
++		return gc2145_set_white_balance(sensor);
++
++	case V4L2_CID_TEST_PATTERN_RED:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_RED, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENR:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_GREEN_R, val);
++
++	case V4L2_CID_TEST_PATTERN_BLUE:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_BLUE, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENB:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_GREEN_B, val);
++
++#endif
++	default:
++		dev_err(&sensor->i2c_client->dev, "setting unknown control %d\n", ctrl->id);
++		return -EINVAL;
++	}
++}
++
++static const struct v4l2_ctrl_ops gc2145_ctrl_ops = {
++	.g_volatile_ctrl = gc2145_g_volatile_ctrl,
++	.s_ctrl = gc2145_s_ctrl,
++};
++
++static int gc2145_init_controls(struct gc2145_dev *sensor)
++{
++	const struct v4l2_ctrl_ops *ops = &gc2145_ctrl_ops;
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++	//u8 wb_max = 0;
++	//u64 wb_mask = 0;
++	//unsigned int i;
++	int ret;
++
++	v4l2_ctrl_handler_init(hdl, 32);
++
++	/* we can use our own mutex for the ctrl lock */
++	hdl->lock = &sensor->lock;
++
++	/* Exposure controls */
++	ctrls->auto_exposure = v4l2_ctrl_new_std_menu(hdl, ops,
++						      V4L2_CID_EXPOSURE_AUTO,
++						      V4L2_EXPOSURE_MANUAL, 0,
++						      V4L2_EXPOSURE_AUTO);
++	ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
++					    1, 0x1fff, 1, 0x80);
++	ctrls->a_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
++					  0, 255, 1, 0x20);
++	ctrls->d_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_DIGITAL_GAIN,
++					  0, 255, 1, 0x40);
++	ctrls->exposure_bias =
++		v4l2_ctrl_new_int_menu(hdl, ops, V4L2_CID_AUTO_EXPOSURE_BIAS,
++				       ARRAY_SIZE(ae_bias_menu_values) - 1,
++				       AE_BIAS_MENU_DEFAULT_VALUE_INDEX,
++				       ae_bias_menu_values);
++
++	/* V/H flips */
++	ctrls->hflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_HFLIP, 0, 1, 1, 0);
++	ctrls->vflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_VFLIP, 0, 1, 1, 0);
++
++
++	/* Test patterns */
++	ctrls->test_pattern =
++		v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
++					     ARRAY_SIZE(test_pattern_menu) - 1,
++					     0, 0, test_pattern_menu);
++#if 0
++
++	ctrls->metering =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_EXPOSURE_METERING,
++				       V4L2_EXPOSURE_METERING_CENTER_WEIGHTED,
++				       0, V4L2_EXPOSURE_METERING_AVERAGE);
++
++	for (i = 0; i < ARRAY_SIZE(gc2145_wb_opts); i++) {
++		if (wb_max < gc2145_wb_opts[i][0])
++			wb_max = gc2145_wb_opts[i][0];
++		wb_mask |= BIT(gc2145_wb_opts[i][0]);
++	}
++
++	ctrls->wb = v4l2_ctrl_new_std_menu(hdl, ops,
++			V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
++			wb_max, ~wb_mask, V4L2_WHITE_BALANCE_AUTO);
++
++	ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
++						0, 4000, 1, 1000);
++	ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
++					       0, 4000, 1, 1000);
++
++	ctrls->gamma = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA,
++					 0, 31, 1, 20);
++
++	ctrls->colorfx =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX, 15,
++				       ~(BIT(V4L2_COLORFX_NONE) |
++					 BIT(V4L2_COLORFX_NEGATIVE) |
++					 BIT(V4L2_COLORFX_SOLARIZATION) |
++					 BIT(V4L2_COLORFX_SKETCH) |
++					 BIT(V4L2_COLORFX_SEPIA) |
++					 BIT(V4L2_COLORFX_ANTIQUE) |
++					 BIT(V4L2_COLORFX_AQUA) |
++					 BIT(V4L2_COLORFX_BW)),
++				       V4L2_COLORFX_NONE);
++
++	ctrls->pl_freq =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
++				V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
++				V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
++
++	ctrls->brightness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS,
++					      0, 200, 1, 90);
++	ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
++					      0, 200, 1, 110);
++	ctrls->contrast = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST,
++					    0, 200, 1, 108);
++
++	ctrls->aaa_lock = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_3A_LOCK,
++					    0, 0x7, 0, 0);
++
++	for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++		ctrls->test_data[i] =
++			v4l2_ctrl_new_std(hdl, ops,
++					  V4L2_CID_TEST_PATTERN_RED + i,
++					  0, 1023, 1, 0);
++
++	ctrls->af_status->flags |= V4L2_CTRL_FLAG_VOLATILE |
++		V4L2_CTRL_FLAG_READ_ONLY;
++
++	v4l2_ctrl_auto_cluster(3, &ctrls->wb, V4L2_WHITE_BALANCE_MANUAL, false);
++#endif
++
++	v4l2_ctrl_auto_cluster(4, &ctrls->auto_exposure, V4L2_EXPOSURE_MANUAL,
++			       true);
++
++	if (hdl->error) {
++		ret = hdl->error;
++		goto free_ctrls;
++	}
++
++	sensor->sd.ctrl_handler = hdl;
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(hdl);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Video ops */
++
++/*
++ * Clock tree
++ * ----------
++ *
++ *     MCLK pin
++ *         |
++ *  DIV2 (optional)        - Divide input MCLK by 2 when 0xf7[1] == 1
++ *         |
++ *   /- PLL mux -\         - PLL selected by 0xf8[7], otherwise fixed 32x mult
++ *   |           |
++ * PLL           |         - PLL multiplies by 0xf8[5:0]+1 * 4
++ *   |      Fixed 32/48x   - Multiplies 32x when 0xf7[2] == 1 otherwise 48x
++ *    \_________/
++ *         |
++ *       DOUBLE  (div by 4 or 8) based on 0xf7[3]
++ *         |
++ *     /-------\
++ *     |       |
++ * pclk_div  sclk_div
++ *     |       |
++ *   2pclk    sclk
++ */
++__maybe_unused
++static int gc2145_get_2pclk(struct gc2145_dev *sensor, unsigned long* pclk)
++{
++	u8 pll_mode1, pll_mode2, clk_div_mode;
++	bool mclk_div2_en; // 0xf7[1]
++	bool pll_en; // 0xf8[7]
++	bool double_clk; // 0xf7[3]
++	bool fixed_32x; // 0xf7[2]
++	unsigned long pll_mult; // 0xf8[5:0] + 1
++	unsigned long sclk_div; // 1 << (0xf7[5:4] + 1)
++	unsigned long pclk_div; // 0xfa[7:4] + 1
++	unsigned long int_clk;
++	unsigned long mclk;
++        int ret;
++
++	ret = gc2145_read(sensor, 0xf7, &pll_mode1);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read(sensor, 0xf8, &pll_mode2);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read(sensor, 0xfa, &clk_div_mode);
++	if (ret)
++		return ret;
++
++	mclk = clk_get_rate(sensor->xclk);
++	if (mclk == 0)
++		return -EINVAL;
++
++	mclk_div2_en = pll_mode1 & BIT(1);
++	pll_en = pll_mode2 & BIT(7);
++	double_clk = pll_mode1 & BIT(3);
++	fixed_32x = pll_mode1 & BIT(2);
++	pll_mult = (pll_mode2 & 0x3f) + 1;
++	pclk_div = (clk_div_mode >> 4) + 1;
++	sclk_div = 1 << (((pll_mode1 >> 4) & 0x3) + 1);
++
++	int_clk = mclk / (mclk_div2_en ? 2 : 1);
++
++	if (pll_en)
++		int_clk *= pll_mult * 4;
++	else
++		int_clk *= fixed_32x ? 32 : 48;
++
++	int_clk /= double_clk ? 4 : 8;
++
++	if (pclk)
++		*pclk = int_clk / pclk_div;
++
++	return 0;
++}
++
++static int gc2145_set_2pclk(struct gc2145_dev *sensor,
++			    unsigned long *freq, bool apply)
++{
++	unsigned long pll_mult, pll_mult_max, /*sclk_div,*/ pclk_div, pclk2,/* sclk,*/
++		      mclk;
++	unsigned long pll_mult_best = 0, pclk_div_best = 0, diff_best = ULONG_MAX, diff,
++		      pclk2_best = 0;
++	int mclk_div2_en; //, double_clk;
++	int mclk_div2_en_best = 0; //, double_clk_best;
++
++	mclk = clk_get_rate(sensor->xclk);
++	if (mclk == 0)
++		return -EINVAL;
++
++        for (mclk_div2_en = 0; mclk_div2_en <= 1; mclk_div2_en++) {
++		pll_mult_max = 768000000 / 4 / (mclk / (mclk_div2_en ? 2 : 1));
++		if (pll_mult_max > 32)
++			pll_mult_max = 32;
++
++		for (pll_mult = 2; pll_mult <= pll_mult_max; pll_mult++) {
++			for (pclk_div = 1; pclk_div <= 8; pclk_div++) {
++				pclk2 = mclk / (mclk_div2_en ? 2 : 1) * pll_mult / pclk_div;
++
++				if (pclk2 > *freq)
++					continue;
++
++				diff = *freq - pclk2;
++
++				if (diff < diff_best) {
++					diff_best = diff;
++					pclk2_best = pclk2;
++
++					pll_mult_best = pll_mult;
++					pclk_div_best = pclk_div;
++					mclk_div2_en_best = mclk_div2_en;
++				}
++
++				if (diff == 0)
++					goto found;
++			}
++		}
++	}
++
++	if (diff_best == ULONG_MAX)
++		return -1;
++
++found:
++	*freq = pclk2_best;
++	if (!apply)
++		return 0;
++
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, 0xf7,
++			 ((pclk_div_best - 1)) << 4 |
++			 (mclk_div2_en_best << 1) | BIT(0) /* pll_en */);
++	gc2145_tx_write8(sensor, 0xf8, BIT(7) | (pll_mult_best - 1));
++	gc2145_tx_write8(sensor, 0xfa,
++			 (pclk_div_best - 1) << 4 |
++			 (((pclk_div_best - 1) / 2) & 0xf));
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_setup_awb(struct gc2145_dev *sensor,
++			     u16 x1, u16 y1, u16 x2, u16 y2)
++{
++	int ratio = 8; //XXX: manual for gc2035 FAE says 4
++
++	gc2145_tx_start(sensor);
++
++	// disable awb
++	gc2145_tx_update_bits(sensor, 0x82, BIT(1), 0);
++
++	// reset white balance RGB gains
++	gc2145_tx_write8(sensor, 0xb3, 0x40);
++	gc2145_tx_write8(sensor, 0xb4, 0x40);
++	gc2145_tx_write8(sensor, 0xb5, 0x40);
++
++	// awb window
++	gc2145_tx_write8(sensor, 0x1ec, x1 / ratio);
++	gc2145_tx_write8(sensor, 0x1ed, y1 / ratio);
++	gc2145_tx_write8(sensor, 0x1ee, x2 / ratio);
++	gc2145_tx_write8(sensor, 0x1ef, y2 / ratio);
++
++	// eanble awb
++	gc2145_tx_update_bits(sensor, 0x82, BIT(1), BIT(1));
++
++	//1051  { 0xfe, 0x01 },
++	//1052  { 0x74, 0x01 },
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_setup_aec(struct gc2145_dev *sensor,
++			     u16 x1, u16 y1, u16 x2, u16 y2,
++			     u16 cx1, u16 cy1, u16 cx2, u16 cy2)
++{
++        u16 x_ratio = 8;
++
++	//XXX: gc2035 has x ratio 16
++	//XXX: gc2035 doesn't have low light mode
++	gc2145_tx_start(sensor);
++
++	// disable AEC
++	gc2145_tx_write8(sensor, 0xb6, 0);
++
++	// set reasonable initial exposure and gains
++	gc2145_tx_write16(sensor, 0x03, 1200);
++	gc2145_tx_write8(sensor, 0xb1, 0x20);
++	gc2145_tx_write8(sensor, 0xb2, 0xe0);
++
++	// setup measure window
++	gc2145_tx_write8(sensor, 0x101, x1 / x_ratio);
++	gc2145_tx_write8(sensor, 0x102, x2 / x_ratio);
++	gc2145_tx_write8(sensor, 0x103, y1 / 8);
++	gc2145_tx_write8(sensor, 0x104, y2 / 8);
++
++	// setup center
++	gc2145_tx_write8(sensor, 0x105, cx1 / x_ratio);
++	gc2145_tx_write8(sensor, 0x106, cx2 / x_ratio);
++	gc2145_tx_write8(sensor, 0x107, cy1 / 8);
++	gc2145_tx_write8(sensor, 0x108, cy2 / 8);
++
++	// increase maximum exposure level to 4
++	//gc2145_tx_write8(sensor, 0x13c, 0x60);
++	// setup AEC mode: measure point, adjust_max_gain, skip_mode = 2
++	//gc2145_tx_write8(sensor, 0x10a, 0xc2);
++
++	// AEC_ASDE_select_luma_value AEC_low_light_exp_THD_max:
++	//gc2145_tx_write8(sensor, 0x121, 0x15);
++
++	// enable AEC again
++	gc2145_tx_write8(sensor, 0xb6, 1);
++
++	return gc2145_tx_commit(sensor);
++}
++
++struct gc2145_sensor_params {
++	unsigned int enable_scaler;
++	unsigned int col_scaler_only;
++	unsigned int row_skip;
++	unsigned int col_skip;
++	unsigned long sh_delay;
++	unsigned long hb;
++	unsigned long vb;
++	unsigned long st;
++	unsigned long et;
++	unsigned long win_width;
++	unsigned long win_height;
++	unsigned long width;
++	unsigned long height;
++};
++
++static void gc2145_sensor_params_init(struct gc2145_sensor_params* p, int width, int height)
++{
++	p->win_height = height + 32;
++	p->win_width = (width + 16);
++	p->width = width;
++	p->height = height;
++	p->st = 2;
++	p->et = 2;
++	p->vb = 8;
++	p->hb = 0x1f0;
++	p->sh_delay = 30;
++}
++
++// unit is PCLK periods
++static unsigned long
++gc2145_sensor_params_get_row_period(struct gc2145_sensor_params* p)
++{
++	return 2 * (p->win_width / 2 / (p->col_skip + 1) + p->sh_delay + p->hb + 4);
++}
++
++static unsigned long
++gc2145_sensor_params_get_frame_period(struct gc2145_sensor_params* p)
++{
++	unsigned long rt = gc2145_sensor_params_get_row_period(p);
++
++	return rt * (p->vb + p->win_height) / (p->row_skip + 1);
++}
++
++static void
++gc2145_sensor_params_fit_hb_to_power_line_period(struct gc2145_sensor_params* p,
++					  unsigned long power_line_freq,
++					  unsigned long pclk)
++{
++	unsigned long rt, power_line_ratio;
++
++        for (p->hb = 0x1f0; p->hb < 2047; p->hb++) {
++		rt = gc2145_sensor_params_get_row_period(p);
++
++		// power_line_ratio is row_freq / power_line_freq * 1000
++                power_line_ratio = pclk / power_line_freq * 1000 / rt;
++
++		// if we're close enough, stop the search
++                if (power_line_ratio % 1000 < 50)
++                        break;
++        }
++
++	// finding the optimal Hb is not critical
++	if (p->hb == 2047)
++		p->hb = 0x1f0;
++}
++
++static void
++gc2145_sensor_params_fit_vb_to_frame_period(struct gc2145_sensor_params* p,
++				     unsigned long frame_period)
++{
++	unsigned long rt, fp;
++
++	p->vb = 8;
++	rt = gc2145_sensor_params_get_row_period(p);
++	fp = gc2145_sensor_params_get_frame_period(p);
++
++	if (frame_period > fp)
++		p->vb = frame_period * (p->row_skip + 1) / rt - p->win_height;
++
++	if (p->vb > 4095)
++		p->vb = 4095;
++}
++
++static int gc2145_sensor_params_apply(struct gc2145_dev *sensor,
++				      struct gc2145_sensor_params* p)
++{
++	u32 off_x = (GC2145_SENSOR_WIDTH_MAX - p->width) / 2;
++	u32 off_y = (GC2145_SENSOR_HEIGHT_MAX - p->height) / 2;
++
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, 0xfd, (p->enable_scaler ? BIT(0) : 0)
++			| (p->col_scaler_only ? BIT(1) : 0));
++
++	gc2145_tx_write8(sensor, 0x18, 0x0a
++		       | (p->col_skip ? BIT(7) : 0)
++		       | (p->row_skip ? BIT(6) : 0));
++
++	gc2145_tx_write16(sensor, 0x09, off_y);
++	gc2145_tx_write16(sensor, 0x0b, off_x);
++	gc2145_tx_write16(sensor, 0x0d, p->win_height);
++	gc2145_tx_write16(sensor, 0x0f, p->win_width);
++	gc2145_tx_write16(sensor, 0x05, p->hb);
++	gc2145_tx_write16(sensor, 0x07, p->vb);
++	gc2145_tx_write16(sensor, 0x11, p->sh_delay);
++
++	gc2145_tx_write8(sensor, 0x13, p->st);
++	gc2145_tx_write8(sensor, 0x14, p->et);
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_setup_mode(struct gc2145_dev *sensor)
++{
++	int scaling_desired, ret, pad, i;
++	struct gc2145_sensor_params params = {0};
++	unsigned long pclk2, frame_period;
++	unsigned long power_line_freq = 50;
++	unsigned long width = sensor->fmt.width;
++	unsigned long height = sensor->fmt.height;
++	unsigned long framerate = sensor->frame_interval.denominator;
++	const struct gc2145_pixfmt *pix_fmt;
++	unsigned long rt, ft, ft_rt;
++
++	pix_fmt = gc2145_find_format(sensor->fmt.code);
++	if (!pix_fmt) {
++		dev_err(&sensor->i2c_client->dev,
++			"pixel format not supported %u\n", sensor->fmt.code);
++		return -EINVAL;
++	}
++
++        /*
++	 * Equations for calculating framerate are:
++	 *
++	 *    ww = width + 16
++	 *    wh = height + 32
++	 *    Rt = (ww / 2 / (col_skip + 1) + sh_delay + Hb + 4)
++	 *    Ft = Rt * (Vb + wh) / (row_skip + 1)
++	 *    framerate = 2pclk / 4 / Ft
++	 *
++	 * Based on these equations:
++	 *
++	 * 1) First we need to determine what 2PCLK frequency to use. The 2PCLK
++	 *    frequency is not arbitrarily precise, so we need to calculate the
++	 *    actual frequency used, after setting our target frequency.
++	 *
++	 *    We use a simple heuristic:
++	 *
++	 *      If pixel_count * 2 * framerate * 1.15 is > 40MHz, we use 60MHz,
++	 *      otherwise we use 40MHz.
++	 *
++	 * 2) We want to determine lowest Hb that we can use to extend row
++	 *    period so that row time takes an integer fraction of the power
++	 *    line frequency period. Minimum Hb is 0x1f0.
++	 *
++	 * 3) If the requested resolution is less than half the sensor's size,
++	 *    we'll use scaling, or row skipping + column scaling, or row and
++	 *    column skiping, depending on what allows us to achieve the
++	 *    requested framerate.
++         *
++	 * 4) We use the selected Hb to calculate Vb value that will give
++	 *    us the desired framerate, given the scaling/skipping option
++	 *    selected in 3).
++	 */
++
++	scaling_desired = width <= GC2145_SENSOR_WIDTH_MAX / 2
++			&& height <= GC2145_SENSOR_HEIGHT_MAX / 2;
++
++	pclk2 = 60000000;
++
++	ret = gc2145_set_2pclk(sensor, &pclk2, false);
++	if (ret < 0)
++		return ret;
++
++	gc2145_sensor_params_init(&params, width, height);
++
++	// if the resolution is < half the sensor size, enable the scaler
++	// to cover more area of the chip
++	if (scaling_desired) {
++		params.enable_scaler = 1;
++		pclk2 *= 2;
++		gc2145_sensor_params_init(&params, width * 2, height * 2);
++	}
++
++	// we need to call this each time pclk or power_line_freq is changed
++	gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++							 power_line_freq,
++							 pclk2 / 2);
++
++	frame_period = gc2145_sensor_params_get_frame_period(&params);
++	if (framerate <= pclk2 / 2 / frame_period)
++		goto apply;
++
++	if (scaling_desired) {
++		// try using just the column scaler + row skip
++		params.col_scaler_only = 1;
++		params.row_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++								 power_line_freq,
++								 pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++		if (framerate <= pclk2 / 2 / frame_period)
++			goto apply;
++
++
++		/*
++		// try disabling the scaler and just use skipping
++		params.enable_scaler = 0;
++		pclk2 /= 2;
++		params.col_scaler_only = 0;
++		params.col_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params, power_line_freq, pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++
++		if (framerate <= pclk2 / 2 / frame_period)
++			goto apply;
++                  */
++	}
++
++apply:
++        // adjust vb to fit the target framerate
++	gc2145_sensor_params_fit_vb_to_frame_period(&params,
++						    pclk2 / 2 / framerate);
++
++	gc2145_sensor_params_apply(sensor, &params);
++
++	ret = gc2145_set_2pclk(sensor, &pclk2, true);
++	if (ret < 0)
++		return ret;
++
++	pad = (width > 256 && height > 256) ? 32 : 16;
++
++	ret = gc2145_setup_awb(sensor, pad, pad, width - pad * 2, height - pad * 2);
++	if (ret)
++		return ret;
++
++	ret = gc2145_setup_aec(sensor,
++				pad, pad, width - pad * 2, height - pad * 2,
++				2 * pad, 2 * pad, width - pad * 4, height - pad * 4);
++	if (ret)
++		return ret;
++
++	gc2145_tx_start(sensor);
++
++	// anti-flicker step
++	//gc2145_tx_write16(sensor, 0x125, 360); //XXX: get this from the calculator (hb related)
++
++	//XXX: calculate auto exposure settings, there are 4 slots that the HW
++	//uses and exposure settings are set in row_time units
++
++	rt = gc2145_sensor_params_get_row_period(&params);
++	ft = gc2145_sensor_params_get_frame_period(&params);
++	ft_rt = ft / rt / 4;
++
++	for (i = 0; i < 7; i++) {
++		// exposure settings for exposure levels
++		gc2145_tx_write16(sensor, 0x127 + 2 * i, ft_rt * (i + 1));
++		// max dg gains
++		gc2145_tx_write8(sensor, 0x135 + i, 0x50);
++	}
++
++	// max analog gain
++	gc2145_tx_write8(sensor, 0x11f, 0x50);
++	// max digital gain
++	gc2145_tx_write8(sensor, 0x120, 0xe0);
++
++	gc2145_tx_write8(sensor, GC2145_P0_ISP_OUT_FORMAT, pix_fmt->fmt_setup);
++
++	// set gamma curve
++	gc2145_tx_update_bits(sensor, 0x80, BIT(6), BIT(6));
++
++	// disable denoising
++	gc2145_tx_update_bits(sensor, 0x80, BIT(2), 0);
++
++	// drive strength
++	gc2145_tx_write8(sensor, 0x24,
++			 (pclk2 / (params.enable_scaler + 1)) > 40000000 ?
++				0xff : 0x55);
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_set_stream(struct gc2145_dev *sensor, int enable)
++{
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, GC2145_REG_PAD_IO, enable ? 0x0f : 0);
++
++	//XXX: maybe disable cam module function blocks that are not used
++	//and downclock the PLL/disable it when not streaming?
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	if (sensor->streaming == !enable) {
++		if (enable && sensor->pending_mode_change) {
++			ret = gc2145_setup_mode(sensor);
++			if (ret)
++				goto out;
++		}
++
++		ret = gc2145_set_stream(sensor, enable);
++		if (ret)
++			goto out;
++
++		sensor->streaming = !!enable;
++	}
++
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Pad ops */
++
++static int gc2145_get_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	fi->interval = sensor->frame_interval;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int gc2145_set_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret = 0, fps;
++	struct gc2145_sensor_params params;
++	unsigned long pixel_rate;
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++
++	/* user requested infinite frame rate */
++	if (fi->interval.numerator == 0)
++		fps = 60;
++	else
++		fps = DIV_ROUND_CLOSEST(fi->interval.denominator,
++					fi->interval.numerator);
++
++	fps = clamp(fps, 1, 60);
++
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = fps;
++	fi->interval = sensor->frame_interval;
++
++	params = gc2145_get_sensor_params(fps, sensor->fmt.width, sensor->fmt.height, &pixel_rate);
++	__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
++				 pixel_rate);
++
++#if 0
++	if (sensor->streaming) {
++		ret = gc2145_write16(sensor, GC2145_REG_DESIRED_FRAME_RATE_NUM,
++				     fps);
++		if (ret)
++			goto err_unlock;
++	}
++err_unlock:
++#endif
++
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++static int gc2145_enum_mbus_code(struct v4l2_subdev *sd,
++				 struct v4l2_subdev_state *sd_state,
++				 struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad != 0 || code->index >= ARRAY_SIZE(gc2145_formats))
++		return -EINVAL;
++
++	code->code = gc2145_formats[code->index].code;
++
++	return 0;
++}
++
++static int gc2145_enum_frame_size(struct v4l2_subdev *sd,
++				  struct v4l2_subdev_state *sd_state,
++				  struct v4l2_subdev_frame_size_enum *fse)
++{
++	if (fse->pad != 0 || fse->index > 0)
++		return -EINVAL;
++
++	fse->min_width = GC2145_SENSOR_WIDTH_MIN;
++	fse->max_width = GC2145_SENSOR_WIDTH_MAX;
++
++	fse->min_height = GC2145_SENSOR_HEIGHT_MIN;
++	fse->max_height = GC2145_SENSOR_HEIGHT_MAX;
++
++	return 0;
++}
++
++static int gc2145_enum_frame_interval(
++	struct v4l2_subdev *sd,
++	struct v4l2_subdev_state *sd_state,
++	struct v4l2_subdev_frame_interval_enum *fie)
++{
++	if (fie->pad != 0 || fie->index > 0)
++		return -EINVAL;
++
++	fie->interval.numerator = 1;
++	fie->interval.denominator = 30;
++
++	return 0;
++}
++
++static int gc2145_get_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	struct v4l2_mbus_framefmt *mf;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		format->format = *mf;
++		return 0;
++	}
++
++	mutex_lock(&sensor->lock);
++	format->format = sensor->fmt;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int gc2145_set_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	const struct gc2145_pixfmt *pixfmt;
++	int ret = 0;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	/* check if we support requested mbus fmt */
++	pixfmt = gc2145_find_format(mf->code);
++	if (!pixfmt)
++		pixfmt = &gc2145_formats[0];
++
++	mf->code = pixfmt->code;
++	mf->colorspace = pixfmt->colorspace;
++	mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
++	mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++	mf->quantization = V4L2_QUANTIZATION_DEFAULT;
++	mf->field = V4L2_FIELD_NONE;
++
++	mutex_lock(&sensor->lock);
++
++	mf->width = clamp(mf->width, GC2145_SENSOR_WIDTH_MIN,
++		      GC2145_SENSOR_WIDTH_MAX);
++	mf->height = clamp(mf->height, GC2145_SENSOR_HEIGHT_MIN,
++		       GC2145_SENSOR_HEIGHT_MAX);
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		struct v4l2_mbus_framefmt *try_mf;
++
++		try_mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		*try_mf = *mf;
++		goto out;
++	}
++
++	if (sensor->streaming) {
++		ret = -EBUSY;
++		goto out;
++	}
++
++	sensor->fmt = *mf;
++	sensor->pending_mode_change = true;
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Core Ops */
++
++static int gc2145_configure(struct gc2145_dev *sensor)
++{
++	struct v4l2_mbus_config_parallel *bus = &sensor->ep.bus.parallel;
++	u8 sync_mode = 0;
++	u16 chip_id;
++	int ret;
++
++	ret = gc2145_read16(sensor, GC2145_REG_CHIP_ID, &chip_id);
++	if (ret)
++		return ret;
++
++	dev_info(&sensor->i2c_client->dev, "device id: 0x%04x\n",
++		 (unsigned int)chip_id);
++
++	if (chip_id != GC2145_REG_CHIP_ID_VALUE) {
++		dev_err(&sensor->i2c_client->dev,
++			"unsupported device id: 0x%04x\n",
++			(unsigned int)chip_id);
++		return -EINVAL;
++	}
++
++        // setup parallel bus
++
++	if (bus->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
++		sync_mode |= 0x01;
++
++	if (bus->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
++		sync_mode |= 0x02;
++
++	if (bus->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
++		sync_mode |= 0x04;
++
++	gc2145_tx_start(sensor);
++
++	// soft reset
++	gc2145_tx_write8(sensor, GC2145_REG_RESET, 0xf0);
++
++	// enable analog/digital parts
++	gc2145_tx_write8(sensor, GC2145_REG_ANALOG_PWC, 0x06);
++
++	// safe initial PLL setting
++	gc2145_tx_write8(sensor, GC2145_REG_PLL_MODE1, 0x1d);
++	gc2145_tx_write8(sensor, GC2145_REG_PLL_MODE2, 0x84);
++	gc2145_tx_write8(sensor, GC2145_REG_CLK_DIV_MODE, 0x00);
++
++	gc2145_tx_write8(sensor, GC2145_REG_CM_MODE, 0xfe);
++
++	// disable pads
++	gc2145_tx_write8(sensor, GC2145_REG_PAD_IO, 0);
++
++	gc2145_tx_write8(sensor, 0x19, 0x0c); // set AD pipe number
++	gc2145_tx_write8(sensor, 0x20, 0x01); // AD clk mode
++
++	// enable defect correction, etc.
++	gc2145_tx_write8(sensor, 0x80, 0x0b);
++
++	gc2145_tx_write8(sensor, GC2145_P0_SYNC_MODE, sync_mode);
++
++	ret = gc2145_tx_commit(sensor);
++	if (ret)
++		return ret;
++
++	// load default register values from the firmware file
++	ret = gc2145_load_firmware(sensor, GC2145_FIRMWARE_PARAMETERS);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int gc2145_set_power(struct gc2145_dev *sensor, bool on)
++{
++	int ret = 0;
++
++	if (on) {
++		ret = regulator_bulk_enable(GC2145_NUM_SUPPLIES,
++					    sensor->supplies);
++		if (ret)
++			return ret;
++
++		ret = clk_set_rate(sensor->xclk, 24000000);
++		if (ret)
++			goto xclk_off;
++
++		ret = clk_prepare_enable(sensor->xclk);
++		if (ret)
++			goto power_off;
++
++		usleep_range(10000, 12000);
++		gpiod_direction_output(sensor->reset_gpio, 1);
++		usleep_range(10000, 12000);
++		gpiod_direction_output(sensor->enable_gpio, 1);
++		usleep_range(10000, 12000);
++		gpiod_direction_output(sensor->reset_gpio, 0);
++		usleep_range(40000, 50000);
++
++		ret = gc2145_configure(sensor);
++		if (ret)
++			goto xclk_off;
++
++		ret = gc2145_setup_mode(sensor);
++		if (ret)
++			goto xclk_off;
++
++		return 0;
++	}
++
++xclk_off:
++	clk_disable_unprepare(sensor->xclk);
++power_off:
++	gpiod_direction_input(sensor->reset_gpio);
++	gpiod_direction_input(sensor->enable_gpio);
++	regulator_bulk_disable(GC2145_NUM_SUPPLIES, sensor->supplies);
++	msleep(100);
++	return ret;
++}
++
++static int gc2145_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	bool power_up, power_down;
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	power_up = on && !sensor->powered;
++	power_down = !on && sensor->powered;
++
++	if (power_up || power_down) {
++		ret = gc2145_set_power(sensor, power_up);
++		if (!ret)
++			sensor->powered = on;
++	}
++
++	mutex_unlock(&sensor->lock);
++
++	if (!ret && power_up) {
++		/* restore controls */
++		ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
++		if (ret)
++			gc2145_s_power(sd, 0);
++	}
++
++	return ret;
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int gc2145_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret;
++	u8 val = 0;
++
++	if (reg->reg > 0xffff)
++		return -EINVAL;
++
++	reg->size = 1;
++
++	mutex_lock(&sensor->lock);
++	ret = gc2145_read(sensor, reg->reg, &val);
++	mutex_unlock(&sensor->lock);
++	if (ret)
++		return -EIO;
++
++	reg->val = val;
++	return 0;
++}
++
++static int gc2145_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret;
++
++	if (reg->reg > 0xffff || reg->val > 0xff)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	ret = gc2145_write(sensor, reg->reg, reg->val);
++	mutex_unlock(&sensor->lock);
++
++	return ret;
++}
++#endif
++
++/* }}} */
++
++static const struct v4l2_subdev_core_ops gc2145_core_ops = {
++	.s_power = gc2145_s_power,
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = gc2145_g_register,
++	.s_register = gc2145_s_register,
++#endif
++};
++
++static const struct v4l2_subdev_pad_ops gc2145_pad_ops = {
++	.enum_mbus_code = gc2145_enum_mbus_code,
++	.enum_frame_size = gc2145_enum_frame_size,
++	.enum_frame_interval = gc2145_enum_frame_interval,
++	.get_fmt = gc2145_get_fmt,
++	.set_fmt = gc2145_set_fmt,
++	.get_frame_interval = gc2145_get_frame_interval,
++	.set_frame_interval = gc2145_set_frame_interval,
++};
++
++static const struct v4l2_subdev_video_ops gc2145_video_ops = {
++	.s_stream = gc2145_s_stream,
++};
++
++static const struct v4l2_subdev_ops gc2145_subdev_ops = {
++	.core = &gc2145_core_ops,
++	.pad = &gc2145_pad_ops,
++	.video = &gc2145_video_ops,
++};
++
++static int gc2145_get_regulators(struct gc2145_dev *sensor)
++{
++	int i;
++
++	for (i = 0; i < GC2145_NUM_SUPPLIES; i++)
++		sensor->supplies[i].supply = gc2145_supply_name[i];
++
++	return devm_regulator_bulk_get(&sensor->i2c_client->dev,
++				       GC2145_NUM_SUPPLIES,
++				       sensor->supplies);
++}
++
++static int gc2145_probe(struct i2c_client *client)
++{
++	struct device *dev = &client->dev;
++	struct fwnode_handle *endpoint;
++	struct gc2145_dev *sensor;
++	int ret;
++
++	sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
++	if (!sensor)
++		return -ENOMEM;
++
++	sensor->i2c_client = client;
++
++	sensor->fmt.code = gc2145_formats[0].code;
++	sensor->fmt.width = 1600;
++	sensor->fmt.height = 1200;
++	sensor->fmt.field = V4L2_FIELD_NONE;
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = 10;
++	sensor->pending_mode_change = true;
++	sensor->current_bank = 0xff;
++
++	endpoint = fwnode_graph_get_next_endpoint(
++		of_fwnode_handle(client->dev.of_node), NULL);
++	if (!endpoint) {
++		dev_err(dev, "endpoint node not found\n");
++		return -EINVAL;
++	}
++
++	ret = v4l2_fwnode_endpoint_parse(endpoint, &sensor->ep);
++	fwnode_handle_put(endpoint);
++	if (ret) {
++		dev_err(dev, "could not parse endpoint\n");
++		return ret;
++	}
++
++	if (sensor->ep.bus_type != V4L2_MBUS_PARALLEL) {
++		dev_err(dev, "unsupported bus type %d\n", sensor->ep.bus_type);
++		return -EINVAL;
++	}
++
++	sensor->xclk = devm_clk_get(dev, "xclk");
++	if (IS_ERR(sensor->xclk)) {
++		dev_err(dev, "failed to get xclk\n");
++		return PTR_ERR(sensor->xclk);
++	}
++
++	sensor->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_IN);
++	if (IS_ERR(sensor->enable_gpio)) {
++		dev_err(dev, "failed to get enable gpio\n");
++		return PTR_ERR(sensor->enable_gpio);
++	}
++
++	sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_IN);
++	if (IS_ERR(sensor->reset_gpio)) {
++		dev_err(dev, "failed to get reset gpio\n");
++		return PTR_ERR(sensor->reset_gpio);
++	}
++
++	if (!sensor->enable_gpio || !sensor->reset_gpio) {
++		dev_err(dev, "enable and reset pins must be configured\n");
++		return ret;
++	}
++
++	v4l2_i2c_subdev_init(&sensor->sd, client, &gc2145_subdev_ops);
++
++	sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
++	sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
++	if (ret)
++		return ret;
++
++	mutex_init(&sensor->lock);
++
++	ret = gc2145_get_regulators(sensor);
++	if (ret)
++		goto entity_cleanup;
++
++	ret = gc2145_init_controls(sensor);
++	if (ret)
++		goto entity_cleanup;
++
++	ret = v4l2_async_register_subdev(&sensor->sd);
++	if (ret)
++		goto free_ctrls;
++
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++entity_cleanup:
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	return ret;
++}
++
++static void gc2145_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++
++	v4l2_async_unregister_subdev(&sensor->sd);
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++}
++
++static const struct i2c_device_id gc2145_id[] = {
++	{"gc2145", 0},
++	{},
++};
++MODULE_DEVICE_TABLE(i2c, gc2145_id);
++
++static const struct of_device_id gc2145_dt_ids[] = {
++	{ .compatible = "galaxycore,gc2145" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, gc2145_dt_ids);
++
++static struct i2c_driver gc2145_i2c_driver = {
++	.driver = {
++		.name  = "gc2145",
++		.of_match_table	= gc2145_dt_ids,
++	},
++	.id_table = gc2145_id,
++	.probe    = gc2145_probe,
++	.remove   = gc2145_remove,
++};
++
++module_i2c_driver(gc2145_i2c_driver);
++
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("GC2145 Camera Subdev Driver");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-fix-white-balance-colors.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-fix-white-balance-colors.patch
new file mode 100644
index 000000000000..f7fdeca6ce32
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-fix-white-balance-colors.patch
@@ -0,0 +1,183 @@
+From 30b9c53ed786594b69b7a9f9a50448287227f8e6 Mon Sep 17 00:00:00 2001
+From: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+Date: Sat, 26 Aug 2023 12:10:49 +0300
+Subject: media: gc2145: fix white-balance colors
+
+awb initialization settings were taken from gc2145.c driver developed
+by STMicroelectronics with a help of Galaxycore. Most of these
+registers are not documented in a publicly available gc2145
+documentation.
+
+Don't reset white balance gains, exposure and gains on every stream
+start. That keeps old values set by AWB/AEC previously and makes
+AWB/AEC algorithms achieve correct settings on stream restart faster.
+
+For Megapixels DCP calibration file for front camera has to be removed
+to get good quality pictures.
+```
+rm /usr/share/megapixels/config/pine64,pinephone,front.dcp
+```
+
+Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+---
+ drivers/media/i2c/gc2145.c | 118 ++++++++++++++++++++++++++++++-------
+ 1 file changed, 97 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index 429d86bf5f01..b505b3f07387 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -1,6 +1,7 @@
+ /*
+  * Galaxycore GC2145 driver.
+  * Copyright (C) 2018 Ondřej Jirman <megi@xff.cz>.
++ * Copyright (C) 2022, STMicroelectronics SA
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -1556,34 +1557,114 @@ static int gc2145_set_2pclk(struct gc2145_dev *sensor,
+ 	return gc2145_tx_commit(sensor);
+ }
+ 
++struct gc2145_reg {
++	unsigned char address;
++	unsigned char val;
++};
++
++static const struct gc2145_reg gc2145_awb_regs[] = {
++	{0xfe, 0x01},
++	{0x4f, 0x00}, {0x4f, 0x00}, {0x4b, 0x01}, {0x4f, 0x00},
++	{0x4c, 0x01}, {0x4d, 0x71}, {0x4e, 0x01},
++	{0x4c, 0x01}, {0x4d, 0x91}, {0x4e, 0x01},
++	{0x4c, 0x01}, {0x4d, 0x70}, {0x4e, 0x01},
++	{0x4c, 0x01}, {0x4d, 0x90}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xb0}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0x8f}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0x6f}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xaf}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xd0}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xf0}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xcf}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xef}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0x6e}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8e}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xae}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xce}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x4d}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x6d}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8d}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xad}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xcd}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x4c}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x6c}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8c}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xac}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xcc}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xcb}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x4b}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x6b}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8b}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xab}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8a}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xaa}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xca}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xca}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xc9}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0x8a}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0x89}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xa9}, {0x4e, 0x04},
++	{0x4c, 0x02}, {0x4d, 0x0b}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x0a}, {0x4e, 0x05},
++	{0x4c, 0x01}, {0x4d, 0xeb}, {0x4e, 0x05},
++	{0x4c, 0x01}, {0x4d, 0xea}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x09}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x29}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x2a}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x4a}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x8a}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x49}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x69}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x89}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0xa9}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x48}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x68}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x69}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0xca}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xc9}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xe9}, {0x4e, 0x07},
++	{0x4c, 0x03}, {0x4d, 0x09}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xc8}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xe8}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xa7}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xc7}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xe7}, {0x4e, 0x07},
++	{0x4c, 0x03}, {0x4d, 0x07}, {0x4e, 0x07},
++	{0x4f, 0x01},
++	{0x50, 0x80}, {0x51, 0xa8}, {0x52, 0x47}, {0x53, 0x38},
++	{0x54, 0xc7}, {0x56, 0x0e}, {0x58, 0x08}, {0x5b, 0x00},
++	{0x5c, 0x74}, {0x5d, 0x8b}, {0x61, 0xdb}, {0x62, 0xb8},
++	{0x63, 0x86}, {0x64, 0xc0}, {0x65, 0x04}, {0x67, 0xa8},
++	{0x68, 0xb0}, {0x69, 0x00}, {0x6a, 0xa8}, {0x6b, 0xb0},
++	{0x6c, 0xaf}, {0x6d, 0x8b}, {0x6e, 0x50}, {0x6f, 0x18},
++	{0x73, 0xf0}, {0x70, 0x0d}, {0x71, 0x60}, {0x72, 0x80},
++	{0x74, 0x01}, {0x75, 0x01}, {0x7f, 0x0c}, {0x76, 0x70},
++	{0x77, 0x58}, {0x78, 0xa0}, {0x79, 0x5e}, {0x7a, 0x54},
++	{0x7b, 0x58},
++	{0xfe, 0x00},
++};
++
+ static int gc2145_setup_awb(struct gc2145_dev *sensor,
+ 			     u16 x1, u16 y1, u16 x2, u16 y2)
+ {
+ 	int ratio = 8; //XXX: manual for gc2035 FAE says 4
+ 
+-	gc2145_tx_start(sensor);
+-
+ 	// disable awb
+-	gc2145_tx_update_bits(sensor, 0x82, BIT(1), 0);
++	gc2145_update_bits(sensor, 0x82, BIT(1), 0);
+ 
+-	// reset white balance RGB gains
+-	gc2145_tx_write8(sensor, 0xb3, 0x40);
+-	gc2145_tx_write8(sensor, 0xb4, 0x40);
+-	gc2145_tx_write8(sensor, 0xb5, 0x40);
++	// load awb settings
++	gc2145_set_registers(sensor, (void*)gc2145_awb_regs, sizeof(gc2145_awb_regs));
+ 
+ 	// awb window
+-	gc2145_tx_write8(sensor, 0x1ec, x1 / ratio);
+-	gc2145_tx_write8(sensor, 0x1ed, y1 / ratio);
+-	gc2145_tx_write8(sensor, 0x1ee, x2 / ratio);
+-	gc2145_tx_write8(sensor, 0x1ef, y2 / ratio);
++	gc2145_write(sensor, 0x1ec, x1 / ratio);
++	gc2145_write(sensor, 0x1ed, y1 / ratio);
++	gc2145_write(sensor, 0x1ee, x2 / ratio);
++	gc2145_write(sensor, 0x1ef, y2 / ratio);
+ 
+ 	// eanble awb
+-	gc2145_tx_update_bits(sensor, 0x82, BIT(1), BIT(1));
+-
+-	//1051  { 0xfe, 0x01 },
+-	//1052  { 0x74, 0x01 },
++	gc2145_update_bits(sensor, 0x82, BIT(1), BIT(1));
+ 
+-	return gc2145_tx_commit(sensor);
++	return 0;
+ }
+ 
+ static int gc2145_setup_aec(struct gc2145_dev *sensor,
+@@ -1599,11 +1680,6 @@ static int gc2145_setup_aec(struct gc2145_dev *sensor,
+ 	// disable AEC
+ 	gc2145_tx_write8(sensor, 0xb6, 0);
+ 
+-	// set reasonable initial exposure and gains
+-	gc2145_tx_write16(sensor, 0x03, 1200);
+-	gc2145_tx_write8(sensor, 0xb1, 0x20);
+-	gc2145_tx_write8(sensor, 0xb2, 0xe0);
+-
+ 	// setup measure window
+ 	gc2145_tx_write8(sensor, 0x101, x1 / x_ratio);
+ 	gc2145_tx_write8(sensor, 0x102, x2 / x_ratio);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-implement-system-suspend.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-implement-system-suspend.patch
new file mode 100644
index 000000000000..f4eca6ce36b0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-gc2145-implement-system-suspend.patch
@@ -0,0 +1,72 @@
+From b10872c4b243c76d007766c687d9f75faf33aa5d Mon Sep 17 00:00:00 2001
+From: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+Date: Mon, 14 Aug 2023 13:27:08 +0300
+Subject: media: gc2145: implement system suspend
+
+If system was suspended while camera sensor was used, data and
+interrupts were still coming from sensor and that caused unstable
+system. Sometimes system hanged during a resume.
+
+Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+---
+ drivers/media/i2c/gc2145.c | 37 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index 749dce832aa0..429d86bf5f01 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -2275,6 +2275,42 @@ static void gc2145_remove(struct i2c_client *client)
+ 	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
+ }
+ 
++static int gc2145_sensor_suspend(struct device *dev)
++{
++	struct v4l2_subdev *sd = dev_get_drvdata(dev);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++
++	mutex_lock(&sensor->lock);
++	if (sensor->streaming)
++		gc2145_set_stream(sensor, false);
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int gc2145_sensor_resume(struct device *dev)
++{
++	struct v4l2_subdev *sd = dev_get_drvdata(dev);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++	if (sensor->streaming) {
++		ret = gc2145_set_stream(sensor, true);
++		if (ret) {
++			gc2145_set_stream(sensor, false);
++			sensor->streaming = false;
++		}
++	}
++	mutex_unlock(&sensor->lock);
++
++	return ret;
++}
++
++static const struct dev_pm_ops gc2145_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(gc2145_sensor_suspend, gc2145_sensor_resume)
++};
++
+ static const struct i2c_device_id gc2145_id[] = {
+ 	{"gc2145", 0},
+ 	{},
+@@ -2291,6 +2327,7 @@ static struct i2c_driver gc2145_i2c_driver = {
+ 	.driver = {
+ 		.name  = "gc2145",
+ 		.of_match_table	= gc2145_dt_ids,
++		.pm = &gc2145_pm_ops,
+ 	},
+ 	.id_table = gc2145_id,
+ 	.probe    = gc2145_probe,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
new file mode 100644
index 000000000000..d08de1d88b69
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
@@ -0,0 +1,2268 @@
+From f0b2121425afc0394aee453fcdc1efa9fd994b35 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 30 Sep 2017 02:39:48 +0200
+Subject: media: hm5065: Add subdev driver for Himax HM5065 camera sensor
+
+HM5065 is 5MP CMOS sensor. This driver implements support for
+V4L2_MBUS_PARALLEL bus type only. The driver  Other features:
+
+- External clock rates support from 6-27MHz (discrete values)
+- Resolution support from 2592x1944 to 88x72
+- Frame rates are available depending on the PCLK frequency
+  (from VGA@120 to 2592x1944@8)
+- Support for several YUV and RGB media bus formats
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/Kconfig  |   10 +
+ drivers/media/i2c/Makefile |    1 +
+ drivers/media/i2c/hm5065.c | 2207 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 2218 insertions(+)
+ create mode 100644 drivers/media/i2c/hm5065.c
+
+diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
+index 56f276b920ab..7b6eea2aef11 100644
+--- a/drivers/media/i2c/Kconfig
++++ b/drivers/media/i2c/Kconfig
+@@ -668,6 +668,16 @@ config VIDEO_ST_VGXY61
+ source "drivers/media/i2c/ccs/Kconfig"
+ source "drivers/media/i2c/et8ek8/Kconfig"
+ 
++config VIDEO_HM5065
++	tristate "Himax HM5065 sensor support"
++	depends on I2C
++	select V4L2_FWNODE
++	select VIDEO_V4L2_SUBDEV_API
++	select MEDIA_CONTROLLER
++	help
++	  This is a V4L2 sensor-level driver for Himax HM5065
++	  5 Mpixel camera.
++
+ endif
+ 
+ menu "Camera ISPs"
+diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
+index dfbe6448b549..aed36d8be369 100644
+--- a/drivers/media/i2c/Makefile
++++ b/drivers/media/i2c/Makefile
+@@ -152,3 +152,4 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o
+ obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o
+ obj-$(CONFIG_VIDEO_WM8739) += wm8739.o
+ obj-$(CONFIG_VIDEO_WM8775) += wm8775.o
++obj-$(CONFIG_VIDEO_HM5065)	+= hm5065.o
+diff --git a/drivers/media/i2c/hm5065.c b/drivers/media/i2c/hm5065.c
+new file mode 100644
+index 000000000000..a3500a4c1441
+--- /dev/null
++++ b/drivers/media/i2c/hm5065.c
+@@ -0,0 +1,2207 @@
++/*
++ * Himax HM5065 driver.
++ * Copyright (C) 2017-2019 Ondřej Jirman <megi@xff.cz>.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <asm/div64.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/clkdev.h>
++#include <linux/ctype.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/firmware.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++#include <media/v4l2-subdev.h>
++
++#define HM5065_AF_FIRMWARE		"hm5065-af.bin"
++#define HM5065_FIRMWARE_PARAMETERS	"hm5065-init.bin"
++
++#define HM5065_SENSOR_WIDTH	2592u
++#define HM5065_SENSOR_HEIGHT	1944u
++#define HM5065_CAPTURE_WIDTH_MIN	88u
++#define HM5065_CAPTURE_HEIGHT_MIN	72u
++
++/* {{{ Register definitions */
++
++/* registers are assumed to be u8 unless otherwise specified */
++
++/* device parameters */
++#define HM5065_REG_DEVICE_ID			0x0000 /* u16 */
++#define HM5065_REG_DEVICE_ID_VALUE		0x039e
++#define HM5065_REG_FIRMWARE_VSN			0x0002
++#define HM5065_REG_PATCH_VSN			0x0003
++#define HM5065_REG_EXCLOCKLUT			0x0009 /* standby */
++
++#define HM5065_REG_INT_EVENT_FLAG		0x000a
++#define HM5065_REG_INT_EVENT_FLAG_OP_MODE	BIT(0)
++#define HM5065_REG_INT_EVENT_FLAG_CAM_MODE	BIT(1)
++#define HM5065_REG_INT_EVENT_FLAG_JPEG_STATUS	BIT(2)
++#define HM5065_REG_INT_EVENT_FLAG_NUM_FRAMES	BIT(3)
++#define HM5065_REG_INT_EVENT_FLAG_AF_LOCKED	BIT(4)
++
++/* mode manager */
++#define HM5065_REG_USER_COMMAND			0x0010
++#define HM5065_REG_USER_COMMAND_STOP		0x00
++#define HM5065_REG_USER_COMMAND_RUN		0x01
++#define HM5065_REG_USER_COMMAND_POWEROFF	0x02
++
++#define HM5065_REG_STATE			0x0011
++#define HM5065_REG_STATE_RAW			0x10
++#define HM5065_REG_STATE_IDLE			0x20
++#define HM5065_REG_STATE_RUNNING		0x30
++
++#define HM5065_REG_ACTIVE_PIPE_SETUP_BANK	0x0012
++#define HM5065_REG_ACTIVE_PIPE_SETUP_BANK_0	0x00
++#define HM5065_REG_ACTIVE_PIPE_SETUP_BANK_1	0x01
++
++#define HM5065_REG_NUMBER_OF_FRAMES_STREAMED	0x0014 /* ro */
++#define HM5065_REG_REQUIRED_STREAM_LENGTH	0x0015
++
++#define HM5065_REG_CSI_ENABLE			0x0016 /* standby */
++#define HM5065_REG_CSI_ENABLE_DISABLE		0x00
++#define HM5065_REG_CSI_ENABLE_CSI2_1LANE	0x01
++#define HM5065_REG_CSI_ENABLE_CSI2_2LANE	0x02
++
++/* pipe setup bank 0 */
++#define HM5065_REG_P0_SENSOR_MODE		0x0040
++#define HM5065_REG_SENSOR_MODE_FULLSIZE		0x00
++#define HM5065_REG_SENSOR_MODE_BINNING_2X2	0x01
++#define HM5065_REG_SENSOR_MODE_BINNING_4X4	0x02
++#define HM5065_REG_SENSOR_MODE_SUBSAMPLING_2X2	0x03
++#define HM5065_REG_SENSOR_MODE_SUBSAMPLING_4X4	0x04
++
++#define HM5065_REG_P0_IMAGE_SIZE		0x0041
++#define HM5065_REG_IMAGE_SIZE_5MP		0x00
++#define HM5065_REG_IMAGE_SIZE_UXGA		0x01
++#define HM5065_REG_IMAGE_SIZE_SXGA		0x02
++#define HM5065_REG_IMAGE_SIZE_SVGA		0x03
++#define HM5065_REG_IMAGE_SIZE_VGA		0x04
++#define HM5065_REG_IMAGE_SIZE_CIF		0x05
++#define HM5065_REG_IMAGE_SIZE_QVGA		0x06
++#define HM5065_REG_IMAGE_SIZE_QCIF		0x07
++#define HM5065_REG_IMAGE_SIZE_QQVGA		0x08
++#define HM5065_REG_IMAGE_SIZE_QQCIF		0x09
++#define HM5065_REG_IMAGE_SIZE_MANUAL		0x0a
++
++#define HM5065_REG_P0_MANUAL_HSIZE		0x0042 /* u16 */
++#define HM5065_REG_P0_MANUAL_VSIZE		0x0044 /* u16 */
++
++#define HM5065_REG_P0_DATA_FORMAT		0x0046
++#define HM5065_REG_DATA_FORMAT_YCBCR_JFIF       0x00
++#define HM5065_REG_DATA_FORMAT_YCBCR_REC601     0x01
++#define HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM     0x02
++#define HM5065_REG_DATA_FORMAT_RGB_565          0x03
++#define HM5065_REG_DATA_FORMAT_RGB_565_CUSTOM   0x04
++#define HM5065_REG_DATA_FORMAT_RGB_444          0x05
++#define HM5065_REG_DATA_FORMAT_RGB_555          0x06
++#define HM5065_REG_DATA_FORMAT_RAW10ITU10       0x07
++#define HM5065_REG_DATA_FORMAT_RAW10ITU8        0x08
++#define HM5065_REG_DATA_FORMAT_JPEG             0x09
++
++#define HM5065_REG_P0_GAMMA_GAIN		0x0049 /* 0-31 */
++#define HM5065_REG_P0_GAMMA_INTERPOLATION	0x004a /* 0-16 */
++#define HM5065_REG_P0_PEAKING_GAIN		0x004c /* 0-63 */
++
++#define HM5065_REG_P0_JPEG_SQUEEZE_MODE		0x004d
++#define HM5065_REG_JPEG_SQUEEZE_MODE_USER	0x00
++#define HM5065_REG_JPEG_SQUEEZE_MODE_AUTO	0x01
++
++#define HM5065_REG_P0_JPEG_TARGET_FILE_SIZE	0x004e /* u16, kB */
++#define HM5065_REG_P0_JPEG_IMAGE_QUALITY	0x0050
++#define HM5065_REG_JPEG_IMAGE_QUALITY_HIGH	0x00
++#define HM5065_REG_JPEG_IMAGE_QUALITY_MEDIUM	0x01
++#define HM5065_REG_JPEG_IMAGE_QUALITY_LOW	0x02
++
++/* pipe setup bank 1 (only register indexes) */
++#define HM5065_REG_P1_SENSOR_MODE		0x0060
++#define HM5065_REG_P1_IMAGE_SIZE		0x0061
++#define HM5065_REG_P1_MANUAL_HSIZE		0x0062 /* u16 */
++#define HM5065_REG_P1_MANUAL_VSIZE		0x0064 /* u16 */
++#define HM5065_REG_P1_DATA_FORMAT		0x0066
++#define HM5065_REG_P1_GAMMA_GAIN		0x0069 /* 0-31 */
++#define HM5065_REG_P1_GAMMA_INTERPOLATION	0x006a /* 0-16 */
++#define HM5065_REG_P1_PEAKING_GAIN		0x006c /* 0-63 */
++#define HM5065_REG_P1_JPEG_SQUEEZE_MODE		0x006d
++#define HM5065_REG_P1_JPEG_TARGET_FILE_SIZE	0x006e /* u16, kB */
++#define HM5065_REG_P1_JPEG_IMAGE_QUALITY	0x0070
++
++/* pipe setup - common registers */
++#define HM5065_REG_CONTRAST			0x0080 /* 0-200 */
++#define HM5065_REG_COLOR_SATURATION		0x0081 /* 0-200 */
++#define HM5065_REG_BRIGHTNESS			0x0082 /* 0-200 */
++#define HM5065_REG_HORIZONTAL_MIRROR		0x0083 /* 0,1 */
++#define HM5065_REG_VERTICAL_FLIP		0x0084 /* 0,1 */
++
++#define HM5065_REG_YCRCB_ORDER			0x0085
++#define HM5065_REG_YCRCB_ORDER_CB_Y_CR_Y	0x00
++#define HM5065_REG_YCRCB_ORDER_CR_Y_CB_Y	0x01
++#define HM5065_REG_YCRCB_ORDER_Y_CB_Y_CR	0x02
++#define HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB	0x03
++
++/* clock chain parameter inputs (floating point) */
++#define HM5065_REG_EXTERNAL_CLOCK_FREQ_MHZ	0x00b0 /* fp16, 6-27, standby */
++#define HM5065_REG_TARGET_PLL_OUTPUT	0x00b2 /* fp16, 450-1000, standby */
++
++/* static frame rate control */
++#define HM5065_REG_DESIRED_FRAME_RATE_NUM	0x00c8 /* u16 */
++#define HM5065_REG_DESIRED_FRAME_RATE_DEN	0x00ca
++
++/* static frame rate status */
++#define HM5065_REG_REQUESTED_FRAME_RATE_HZ	0x00d8 /* fp16 */
++#define HM5065_REG_MAX_FRAME_RATE_HZ		0x00da /* fp16 */
++#define HM5065_REG_MIN_FRAME_RATE_HZ		0x00dc /* fp16 */
++
++/* exposure controls */
++#define HM5065_REG_EXPOSURE_MODE			0x0128
++#define HM5065_REG_EXPOSURE_MODE_AUTO			0x00
++#define HM5065_REG_EXPOSURE_MODE_COMPILED_MANUAL	0x01
++#define HM5065_REG_EXPOSURE_MODE_DIRECT_MANUAL		0x02
++
++#define HM5065_REG_EXPOSURE_METERING		0x0129
++#define HM5065_REG_EXPOSURE_METERING_FLAT	0x00
++#define HM5065_REG_EXPOSURE_METERING_BACKLIT	0x01
++#define HM5065_REG_EXPOSURE_METERING_CENTERED	0x02
++
++#define HM5065_REG_MANUAL_EXPOSURE_TIME_NUM	0x012a
++#define HM5065_REG_MANUAL_EXPOSURE_TIME_DEN	0x012b
++#define HM5065_REG_MANUAL_EXPOSURE_TIME_US	0x012c /* fp16 */
++#define HM5065_REG_COLD_START_DESIRED_TIME_US	0x012e /* fp16, standby */
++#define HM5065_REG_EXPOSURE_COMPENSATION	0x0130 /* s8, -7 - +7 */
++
++#define HM5065_REG_DIRECT_MODE_COARSE_INTEGRATION_LINES	0x0132 /* u16 */
++#define HM5065_REG_DIRECT_MODE_FINE_INTEGRATION_PIXELS	0x0134 /* u16 */
++#define HM5065_REG_DIRECT_MODE_CODED_ANALOG_GAIN	0x0136 /* u16 */
++#define HM5065_REG_DIRECT_MODE_DIGITAL_GAIN		0x0138 /* fp16 */
++#define HM5065_REG_FREEZE_AUTO_EXPOSURE			0x0142 /* 0,1 */
++#define HM5065_REG_USER_MAXIMUM_INTEGRATION_TIME_US	0x0143 /* fp16 */
++#define HM5065_REG_ANTI_FLICKER_MODE			0x0148 /* 0,1 */
++
++/* exposure algorithm controls */
++#define HM5065_REG_DIGITAL_GAIN_FLOOR			0x015c /* fp16 */
++#define HM5065_REG_DIGITAL_GAIN_CEILING			0x015e /* fp16 */
++#define HM5065_REG_ANALOG_GAIN_FLOOR			0x02c0 /* u16 */
++#define HM5065_REG_ANALOG_GAIN_CEILING			0x02c2 /* u16 */
++
++/* exposure status */
++#define HM5065_REG_COARSE_INTEGRATION			0x017c /* u16 */
++#define HM5065_REG_FINE_INTEGRATION_PENDING_PIXELS	0x017e /* u16 */
++#define HM5065_REG_ANALOG_GAIN_PENDING			0x0180 /* fp16 */
++#define HM5065_REG_DIGITAL_GAIN_PENDING			0x0182 /* fp16 */
++#define HM5065_REG_DESIRED_EXPOSURE_TIME_US		0x0184 /* fp16 */
++#define HM5065_REG_COMPILED_EXPOSURE_TIME_US		0x0186 /* fp16 */
++#define HM5065_REG_USER_MAXIMUM_INTEGRATION_LINES	0x0189 /* u16 */
++#define HM5065_REG_TOTAL_INTEGRATION_TIME_PENDING_US	0x018b /* fp16 */
++#define HM5065_REG_CODED_ANALOG_GAIN_PENDING		0x018d /* u16 */
++
++/* flicker detect */
++#define HM5065_REG_FD_ENABLE_DETECT			0x0190 /* 0,1 */
++#define HM5065_REG_FD_DETECTION_START			0x0191 /* 0,1 */
++#define HM5065_REG_FD_MAX_NUMBER_ATTEMP	0x0192 /* 0-255, 0 = continuous */
++#define HM5065_REG_FD_FLICKER_IDENTIFICATION_THRESHOLD	0x0193 /* u16 */
++#define HM5065_REG_FD_WIN_TIMES				0x0195
++#define HM5065_REG_FD_FRAME_RATE_SHIFT_NUMBER		0x0196
++#define HM5065_REG_FD_MANUAL_FREF_ENABLE		0x0197 /* 0,1 */
++#define HM5065_REG_FD_MANU_FREF_100			0x0198 /* u16 */
++#define HM5065_REG_FD_MANU_FREF_120			0x019a /* u16 */
++#define HM5065_REG_FD_FLICKER_FREQUENCY			0x019c /* fp16 */
++
++/* white balance control */
++#define HM5065_REG_WB_MODE			0x01a0
++#define HM5065_REG_WB_MODE_OFF			0x00
++#define HM5065_REG_WB_MODE_AUTOMATIC		0x01
++#define HM5065_REG_WB_MODE_AUTO_INSTANT		0x02
++#define HM5065_REG_WB_MODE_MANUAL_RGB		0x03
++#define HM5065_REG_WB_MODE_CLOUDY_PRESET	0x04
++#define HM5065_REG_WB_MODE_SUNNY_PRESET		0x05
++#define HM5065_REG_WB_MODE_LED_PRESET		0x06
++#define HM5065_REG_WB_MODE_FLUORESCENT_PRESET	0x07
++#define HM5065_REG_WB_MODE_TUNGSTEN_PRESET	0x08
++#define HM5065_REG_WB_MODE_HORIZON_PRESET	0x09
++
++#define HM5065_REG_WB_MANUAL_RED_GAIN		0x01a1
++#define HM5065_REG_WB_MANUAL_GREEN_GAIN		0x01a2
++#define HM5065_REG_WB_MANUAL_BLUE_GAIN		0x01a3
++
++#define HM5065_REG_WB_MISC_SETTINGS		0x01a4
++#define HM5065_REG_WB_MISC_SETTINGS_FREEZE_ALGO	BIT(2)
++
++#define HM5065_REG_WB_HUE_R_BIAS		0x01a5 /* fp16 */
++#define HM5065_REG_WB_HUE_B_BIAS		0x01a7 /* fp16 */
++
++#define HM5065_REG_WB_STATUS			0x01c0
++#define HM5065_REG_WB_STATUS_STABLE		BIT(0)
++
++#define HM5065_REG_WB_NORM_RED_GAIN		0x01c8 /* fp16 */
++#define HM5065_REG_WB_PART_RED_GAIN		0x01e0 /* fp16 */
++#define HM5065_REG_WB_PART_GREEN_GAIN		0x01e2 /* fp16 */
++#define HM5065_REG_WB_PART_BLUE_GAIN		0x01e4 /* fp16 */
++
++/* image stability status */
++#define HM5065_REG_WHITE_BALANCE_STABLE		0x0291 /* 0,1 */
++#define HM5065_REG_EXPOSURE_STABLE		0x0292 /* 0,1 */
++#define HM5065_REG_STABLE			0x0294 /* 0,1 */
++
++/* special effects */
++#define HM5065_REG_EFFECTS_NEGATIVE		0x0380 /* 0,1 */
++#define HM5065_REG_EFFECTS_SOLARISING		0x0381 /* 0,1 */
++#define HM5065_REG_EFFECTS_SKECTH		0x0382 /* 0,1 */
++
++#define HM5065_REG_EFFECTS_COLOR		0x0384
++#define HM5065_REG_EFFECTS_COLOR_NORMAL         0x00
++#define HM5065_REG_EFFECTS_COLOR_RED_ONLY       0x01
++#define HM5065_REG_EFFECTS_COLOR_YELLOW_ONLY    0x02
++#define HM5065_REG_EFFECTS_COLOR_GREEN_ONLY     0x03
++#define HM5065_REG_EFFECTS_COLOR_BLUE_ONLY      0x04
++#define HM5065_REG_EFFECTS_COLOR_BLACK_WHITE    0x05
++#define HM5065_REG_EFFECTS_COLOR_SEPIA          0x06
++#define HM5065_REG_EFFECTS_COLOR_ANTIQUE        0x07
++#define HM5065_REG_EFFECTS_COLOR_AQUA           0x08
++#define HM5065_REG_EFFECTS_COLOR_MANUAL_MATRIX  0x09
++
++/* anti-vignete, otp flash (skipped), page 79-89 */
++
++/* flash control */
++#define HM5065_REG_FLASH_MODE		0x02d0 /* 0,1 */
++#define HM5065_REG_FLASH_RECOMMENDED	0x02d1 /* 0,1 */
++
++/* test pattern */
++#define HM5065_REG_ENABLE_TEST_PATTERN	0x05d8 /* 0,1 */
++
++#define HM5065_REG_TEST_PATTERN				0x05d9
++#define HM5065_REG_TEST_PATTERN_NONE			0x00
++#define HM5065_REG_TEST_PATTERN_HORIZONTAL_GREY_SCALE	0x01
++#define HM5065_REG_TEST_PATTERN_VERTICAL_GREY_SCALE	0x02
++#define HM5065_REG_TEST_PATTERN_DIAGONAL_GREY_SCALE	0x03
++#define HM5065_REG_TEST_PATTERN_PN28			0x04
++#define HM5065_REG_TEST_PATTERN_PN9			0x05
++#define HM5065_REG_TEST_PATTERN_SOLID_COLOR		0x06
++#define HM5065_REG_TEST_PATTERN_COLOR_BARS		0x07
++#define HM5065_REG_TEST_PATTERN_GRADUATED_COLOR_BARS	0x08
++
++#define HM5065_REG_TESTDATA_RED		0x4304 /* u16, 0-1023 */
++#define HM5065_REG_TESTDATA_GREEN_R	0x4308 /* u16, 0-1023 */
++#define HM5065_REG_TESTDATA_BLUE	0x430c /* u16, 0-1023 */
++#define HM5065_REG_TESTDATA_GREEN_B	0x4310 /* u16, 0-1023 */
++
++/* contrast stretch */
++#define HM5065_REG_CS_ENABLE			0x05e8 /* 0,1 */
++#define HM5065_REG_CS_GAIN_CEILING		0x05e9 /* fp16 */
++#define HM5065_REG_CS_BLACK_OFFSET_CEILING	0x05eb
++#define HM5065_REG_CS_WHITE_PIX_TARGET		0x05ec /* fp16 */
++#define HM5065_REG_CS_BLACK_PIX_TARGET		0x05ee /* fp16 */
++#define HM5065_REG_CS_ENABLED			0x05f8 /* 0,1 */
++#define HM5065_REG_CS_TOTAL_PIXEL		0x05f9 /* fp16 */
++#define HM5065_REG_CS_W_TARGET			0x05fb /* u32 */
++#define HM5065_REG_CS_B_TARGET			0x05ff /* u32 */
++#define HM5065_REG_CS_GAIN			0x0603 /* fp16 */
++#define HM5065_REG_CS_BLACK_OFFSET		0x0605
++#define HM5065_REG_CS_WHITE_LIMIT		0x0606
++
++/* preset controls */
++#define HM5065_REG_PRESET_LOADER_ENABLE		0x0638 /* 0,1, standby */
++
++#define HM5065_REG_INDIVIDUAL_PRESET		0x0639 /* standby */
++#define HM5065_REG_INDIVIDUAL_PRESET_ANTIVIGNETTE	BIT(0)
++#define HM5065_REG_INDIVIDUAL_PRESET_WHITE_BALANCE	BIT(1)
++#define HM5065_REG_INDIVIDUAL_PRESET_VCM		BIT(4)
++
++/* jpeg control parameters*/
++#define HM5065_REG_JPEG_STATUS			0x0649
++#define HM5065_REG_JPEG_RESTART			0x064a
++#define HM5065_REG_JPEG_HI_SQUEEZE_VALUE	0x064b /* 5-255 (5 = max q.) */
++#define HM5065_REG_JPEG_MED_SQUEEZE_VALUE	0x064c /* 5-255 */
++#define HM5065_REG_JPEG_LOW_SQUEEZE_VALUE	0x064d /* 5-255 */
++#define HM5065_REG_JPEG_LINE_LENGTH		0x064e /* u16, standby */
++#define HM5065_REG_JPEG_CLOCK_RATIO		0x0650 /* 1-8, standby */
++#define HM5065_REG_JPEG_THRES			0x0651 /* u16, standby */
++#define HM5065_REG_JPEG_BYTE_SENT		0x0653 /* u32 */
++
++/* autofocus */
++
++#define HM5065_REG_AF_WINDOWS_SYSTEM		0x065a
++#define HM5065_REG_AF_WINDOWS_SYSTEM_7_ZONES	0x00
++#define HM5065_REG_AF_WINDOWS_SYSTEM_1_ZONE	0x01
++
++#define HM5065_REG_AF_H_RATIO_NUM		0x065b
++#define HM5065_REG_AF_H_RATIO_DEN		0x065c
++#define HM5065_REG_AF_V_RATIO_NUM		0x065d
++#define HM5065_REG_AF_V_RATIO_DEN		0x065e
++
++#define HM5065_REG_AF_RANGE			0x0709
++#define HM5065_REG_AF_RANGE_FULL		0x00
++#define HM5065_REG_AF_RANGE_LANDSCAPE		0x01
++#define HM5065_REG_AF_RANGE_MACRO		0x02
++
++#define HM5065_REG_AF_MODE			0x070a
++#define HM5065_REG_AF_MODE_MANUAL		0x00
++#define HM5065_REG_AF_MODE_CONTINUOUS		0x01
++#define HM5065_REG_AF_MODE_SINGLE		0x03
++
++#define HM5065_REG_AF_MODE_STATUS		0x0720
++
++#define HM5065_REG_AF_COMMAND			0x070b
++#define HM5065_REG_AF_COMMAND_NULL		0x00
++#define HM5065_REG_AF_COMMAND_RELEASED_BUTTON	0x01
++#define HM5065_REG_AF_COMMAND_HALF_BUTTON	0x02
++#define HM5065_REG_AF_COMMAND_TAKE_SNAPSHOT	0x03
++#define HM5065_REG_AF_COMMAND_REFOCUS		0x04
++
++#define HM5065_REG_AF_LENS_COMMAND		0x070c
++#define HM5065_REG_AF_LENS_COMMAND_NULL				0x00
++#define HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_INFINITY	0x01
++#define HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_MACRO		0x02
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_INFINITY		0x03
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_MACRO			0x04
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_RECOVERY		0x05
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_TARGET_POSITION		0x07
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_HYPERFOCAL		0x0C
++
++#define HM5065_REG_AF_MANUAL_STEP_SIZE		0x070d
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE	0x0714
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE_AF	BIT(0)
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE_AE	BIT(1)
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE_AWB	BIT(2)
++#define HM5065_REG_AF_FACE_LOCATION_X_START	0x0715 /* u16 */
++#define HM5065_REG_AF_FACE_LOCATION_X_SIZE	0x0717 /* u16 */
++#define HM5065_REG_AF_FACE_LOCATION_Y_START	0x0719 /* u16 */
++#define HM5065_REG_AF_FACE_LOCATION_Y_SIZE	0x071b /* u16 */
++
++#define HM5065_REG_AF_IN_FOCUS			0x07ae /* ro 0,1 */
++#define HM5065_REG_AF_IS_STABLE			0x0725 /* ro 0,1 */
++
++/* reverse engineered registers */
++#define HM5065_REG_BUS_DATA_FORMAT		0x7000
++#define HM5065_REG_COLORSPACE			0x5200
++#define HM5065_REG_BUS_CONFIG			0x7101
++#define HM5065_REG_BUS_CONFIG_BT656		0x24
++#define HM5065_REG_BUS_CONFIG_PARALLEL_HH_VL	0x44
++
++/* }}} */
++
++struct reg_value {
++	u16 addr;
++	u8 value;
++} __packed;
++
++/*
++ * Sensor has various pre-defined PLL configurations for a set of
++ * external clock frequencies.
++ */
++struct hm5065_clk_lut {
++	unsigned long clk_freq;
++	u8 lut_id;
++};
++
++static const struct hm5065_clk_lut hm5065_clk_luts[] = {
++	{ .clk_freq = 12000000, .lut_id = 0x10 },
++	{ .clk_freq = 13000000, .lut_id = 0x11 },
++	{ .clk_freq = 13500000, .lut_id = 0x12 },
++	{ .clk_freq = 14400000, .lut_id = 0x13 },
++	{ .clk_freq = 18000000, .lut_id = 0x14 },
++	{ .clk_freq = 19200000, .lut_id = 0x15 },
++	{ .clk_freq = 24000000, .lut_id = 0x16 },
++	{ .clk_freq = 26000000, .lut_id = 0x17 },
++	{ .clk_freq = 27000000, .lut_id = 0x18 },
++};
++
++static const struct hm5065_clk_lut *hm5065_find_clk_lut(unsigned long freq)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(hm5065_clk_luts); i++)
++		if (hm5065_clk_luts[i].clk_freq == freq)
++			return &hm5065_clk_luts[i];
++
++	return NULL;
++}
++
++struct hm5065_pixfmt {
++	u32 code;
++	u32 colorspace;
++	u8 data_fmt;
++	u8 ycbcr_order;
++	u8 fmt_setup;
++};
++
++//XXX: identify colrorspace correctly, see datasheet page 40
++static const struct hm5065_pixfmt hm5065_formats[] = {
++	{
++		.code              = MEDIA_BUS_FMT_UYVY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_CB_Y_CR_Y,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_VYUY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_CR_Y_CB_Y,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CB_Y_CR,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_RGB565_2X8_LE,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_RGB_565,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB,
++		.fmt_setup         = 0x02
++	},
++	{
++		.code              = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_RGB_555,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB,
++		.fmt_setup         = 0x02
++	},
++};
++
++#define HM5065_NUM_FORMATS ARRAY_SIZE(hm5065_formats)
++
++static const struct hm5065_pixfmt *hm5065_find_format(u32 code)
++{
++	int i;
++
++	for (i = 0; i < HM5065_NUM_FORMATS; i++)
++		if (hm5065_formats[i].code == code)
++			return &hm5065_formats[i];
++
++	return NULL;
++}
++
++/* regulator supplies */
++static const char * const hm5065_supply_name[] = {
++	"IOVDD", /* Digital I/O (2.8V) suppply */
++	"AFVDD",  /* Autofocus (2.8V) supply */
++	"DVDD",  /* Digital Core (1.8V) supply */
++	"AVDD",  /* Analog (2.8V) supply */
++};
++
++#define HM5065_NUM_SUPPLIES ARRAY_SIZE(hm5065_supply_name)
++
++struct hm5065_ctrls {
++	struct v4l2_ctrl_handler handler;
++	struct {
++		struct v4l2_ctrl *auto_exposure;
++		struct v4l2_ctrl *exposure;
++		struct v4l2_ctrl *d_gain;
++		struct v4l2_ctrl *a_gain;
++	};
++	struct v4l2_ctrl *metering;
++	struct v4l2_ctrl *exposure_bias;
++	struct {
++		struct v4l2_ctrl *wb;
++		struct v4l2_ctrl *blue_balance;
++		struct v4l2_ctrl *red_balance;
++	};
++	struct {
++		struct v4l2_ctrl *focus_auto;
++		struct v4l2_ctrl *af_start;
++		struct v4l2_ctrl *af_stop;
++		struct v4l2_ctrl *af_status;
++		struct v4l2_ctrl *af_distance;
++		struct v4l2_ctrl *focus_relative;
++	};
++	struct v4l2_ctrl *aaa_lock;
++	struct v4l2_ctrl *hflip;
++	struct v4l2_ctrl *vflip;
++	struct v4l2_ctrl *pl_freq;
++	struct v4l2_ctrl *colorfx;
++	struct v4l2_ctrl *brightness;
++	struct v4l2_ctrl *saturation;
++	struct v4l2_ctrl *contrast;
++	struct v4l2_ctrl *gamma;
++	struct v4l2_ctrl *test_pattern;
++	struct v4l2_ctrl *test_data[4];
++};
++
++struct hm5065_dev {
++	struct i2c_client *i2c_client;
++	struct v4l2_subdev sd;
++	struct media_pad pad;
++	struct v4l2_fwnode_endpoint ep; /* the parsed DT endpoint info */
++	struct clk *xclk; /* external clock for HM5065 */
++
++	struct regulator_bulk_data supplies[HM5065_NUM_SUPPLIES];
++	struct gpio_desc *reset_gpio; // nrst pin
++	struct gpio_desc *enable_gpio; // ce pin
++
++	/* lock to protect all members below */
++	struct mutex lock;
++
++	struct v4l2_mbus_framefmt fmt;
++	struct v4l2_fract frame_interval;
++	struct hm5065_ctrls ctrls;
++
++	bool pending_mode_change;
++	bool powered;
++	bool streaming;
++};
++
++static inline struct hm5065_dev *to_hm5065_dev(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct hm5065_dev, sd);
++}
++
++static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct hm5065_dev,
++			     ctrls.handler)->sd;
++}
++
++/* {{{ Register access helpers */
++
++static int hm5065_write_regs(struct hm5065_dev *sensor, u16 start_index,
++			     u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg;
++	u8 buf[130];
++	int ret;
++
++	if (data_size > sizeof(buf) - 2) {
++		v4l2_err(&sensor->sd, "%s: oversized transfer (size=%d)\n",
++			 __func__, data_size);
++		return -EINVAL;
++	}
++
++	buf[0] = start_index >> 8;
++	buf[1] = start_index & 0xff;
++	memcpy(buf + 2, data, data_size);
++
++	msg.addr = client->addr;
++	msg.flags = client->flags;
++	msg.buf = buf;
++	msg.len = data_size + 2;
++
++	dev_dbg(&sensor->i2c_client->dev, "wr: %04x <= %*ph\n",
++		(u32)start_index, data_size, data);
++
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: start_index=%x, data=%*ph\n",
++			 __func__, ret, (u32)start_index, data_size, data);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int hm5065_read_regs(struct hm5065_dev *sensor, u16 start_index,
++			    u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg[2];
++	u8 buf[2];
++	int ret;
++
++	buf[0] = start_index >> 8;
++	buf[1] = start_index & 0xff;
++
++	msg[0].addr = client->addr;
++	msg[0].flags = client->flags;
++	msg[0].buf = buf;
++	msg[0].len = sizeof(buf);
++
++	msg[1].addr = client->addr;
++	msg[1].flags = client->flags | I2C_M_RD;
++	msg[1].buf = data;
++	msg[1].len = data_size;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: start_index=%x, data_size=%d\n",
++			 __func__, ret, (u32)start_index, data_size);
++		return ret;
++	}
++
++	dev_dbg(&sensor->i2c_client->dev, "rd: %04x => %*ph\n",
++		(u32)start_index, data_size, data);
++
++	return 0;
++}
++
++static int hm5065_read(struct hm5065_dev *sensor, u16 reg, u8 *val)
++{
++	return hm5065_read_regs(sensor, reg, val, 1);
++}
++
++static int hm5065_write(struct hm5065_dev *sensor, u16 reg, u8 val)
++{
++	return hm5065_write_regs(sensor, reg, &val, 1);
++}
++
++static int hm5065_read16(struct hm5065_dev *sensor, u16 reg, u16 *val)
++{
++	int ret;
++
++	ret = hm5065_read_regs(sensor, reg, (u8 *)val, sizeof(*val));
++	if (ret)
++		return ret;
++
++	*val = be16_to_cpu(*val);
++	return 0;
++}
++
++static int hm5065_write16(struct hm5065_dev *sensor, u16 reg, u16 val)
++{
++	u16 tmp = cpu_to_be16(val);
++
++	return hm5065_write_regs(sensor, reg, (u8 *)&tmp, sizeof(tmp));
++}
++
++/*
++ * The firmware format:
++ * <record 0>, ..., <record N - 1>
++ * "record" is a 2-byte register address (big endian) followed by 1-byte data
++ */
++static int hm5065_load_firmware(struct hm5065_dev *sensor, const char *name)
++{
++	int ret = 0, i = 0, list_size;
++	const struct firmware *fw;
++	struct reg_value *list;
++	u16 start, len;
++	u8 buf[128];
++
++	ret = request_firmware(&fw, name, sensor->sd.v4l2_dev->dev);
++	if (ret) {
++		v4l2_warn(&sensor->sd,
++			  "Failed to read firmware %s, continuing anyway...\n",
++			  name);
++		return 1;
++	}
++
++	if (fw->size == 0) {
++		ret = 1;
++		goto err_release;
++	}
++
++	if (fw->size % 3 != 0) {
++		v4l2_err(&sensor->sd, "Firmware image %s has invalid size\n",
++			 name);
++		ret = -EINVAL;
++		goto err_release;
++	}
++
++	list_size = fw->size / 3;
++	list = (struct reg_value *)fw->data;
++
++	/* we speed up I2C communication via auto-increment functionality */
++	while (i < list_size) {
++		start = be16_to_cpu(list[i].addr);
++		len = 0;
++
++		while (i < list_size &&
++		       be16_to_cpu(list[i].addr) == (start + len) &&
++		       len < sizeof(buf))
++			buf[len++] = list[i++].value;
++
++		ret = hm5065_write_regs(sensor, start, buf, len);
++		if (ret)
++			goto err_release;
++	}
++
++err_release:
++	release_firmware(fw);
++	return ret;
++}
++
++/*
++ * Sensor uses ST Float900 format to represent floating point numbers.
++ * Binary floating point number: * (s ? -1 : 0) * 1.mmmmmmmmm * 2^eeeeee
++ *
++ * Following functions convert long value to and from the floating point format.
++ *
++ * Example:
++ * mili variant: val = 123456 => fp_val = 123.456
++ * micro variant: val = -12345678 => fp_val = -12.345678
++ */
++static s64 hm5065_mili_from_fp16(u16 fp_val)
++{
++	s64 val;
++	s64 mantisa = fp_val & 0x1ff;
++	int exp = (int)((fp_val >> 9) & 0x3f) - 31;
++
++	val = (1000 * (mantisa | 0x200));
++	if (exp > 0)
++		val <<= exp;
++	else if (exp < 0)
++		val >>= -exp;
++	val >>= 9;
++
++	if (fp_val & 0x8000)
++		val = -val;
++
++	return val;
++}
++
++static u16 hm5065_mili_to_fp16(s32 val)
++{
++	int fls;
++	u16 e, m, s = 0;
++	u64 v, rem;
++
++	if (val == 0)
++		return 0;
++
++	if (val < 0) {
++		val = -val;
++		s = 0x8000;
++	}
++
++	v = (u64)val * 1024;
++	rem = do_div(v, 1000);
++	if (rem >= 500)
++		v++;
++
++	fls = fls64(v) - 1;
++	e = 31 + fls - 10;
++	m = fls > 9 ? v >> (fls - 9) : v << (9 - fls);
++
++	return s | (m & 0x1ff) | (e << 9);
++}
++
++/* }}} */
++/* {{{ Controls */
++
++static int hm5065_get_af_status(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	u8 is_stable, mode;
++	int ret;
++
++	ret = hm5065_read(sensor, HM5065_REG_AF_MODE_STATUS, &mode);
++	if (ret)
++		return ret;
++
++	if (mode == HM5065_REG_AF_MODE_MANUAL) {
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_IDLE;
++		return 0;
++	}
++
++	ret = hm5065_read(sensor, HM5065_REG_AF_IS_STABLE, &is_stable);
++	if (ret)
++		return ret;
++
++	if (is_stable)
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_REACHED;
++	else if (!is_stable && mode == HM5065_REG_AF_MODE_CONTINUOUS)
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_BUSY;
++	else
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_IDLE;
++
++	return 0;
++}
++
++static int hm5065_get_exposure(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	u16 again, dgain, exp;
++	int ret;
++
++	ret = hm5065_read16(sensor, HM5065_REG_CODED_ANALOG_GAIN_PENDING,
++			    &again);
++	if (ret)
++		return ret;
++
++	ret = hm5065_read16(sensor, HM5065_REG_DIGITAL_GAIN_PENDING, &dgain);
++	if (ret)
++		return ret;
++
++	ret = hm5065_read16(sensor, HM5065_REG_COARSE_INTEGRATION, &exp);
++	if (ret)
++		return ret;
++
++	ctrls->exposure->val = exp;
++	ctrls->d_gain->val = clamp(hm5065_mili_from_fp16(dgain), 1000ll,
++				   4000ll);
++	ctrls->a_gain->val = again;
++
++	return 0;
++}
++
++static int hm5065_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	if (!sensor->powered)
++		return -EIO;
++
++	switch (ctrl->id) {
++	case V4L2_CID_FOCUS_AUTO:
++		ret = hm5065_get_af_status(sensor);
++		if (ret)
++			return ret;
++		break;
++	case V4L2_CID_EXPOSURE_AUTO:
++		ret = hm5065_get_exposure(sensor);
++		if (ret)
++			return ret;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const u8 hm5065_wb_opts[][2] = {
++	{ V4L2_WHITE_BALANCE_MANUAL, HM5065_REG_WB_MODE_OFF },
++	{ V4L2_WHITE_BALANCE_INCANDESCENT, HM5065_REG_WB_MODE_TUNGSTEN_PRESET },
++	{ V4L2_WHITE_BALANCE_FLUORESCENT,
++		HM5065_REG_WB_MODE_FLUORESCENT_PRESET },
++	{ V4L2_WHITE_BALANCE_HORIZON, HM5065_REG_WB_MODE_HORIZON_PRESET },
++	{ V4L2_WHITE_BALANCE_CLOUDY, HM5065_REG_WB_MODE_CLOUDY_PRESET },
++	{ V4L2_WHITE_BALANCE_DAYLIGHT, HM5065_REG_WB_MODE_SUNNY_PRESET },
++	{ V4L2_WHITE_BALANCE_AUTO, HM5065_REG_WB_MODE_AUTOMATIC },
++};
++
++static int hm5065_set_power_line_frequency(struct hm5065_dev *sensor, s32 val)
++{
++	u16 freq;
++	int ret;
++
++	switch (val) {
++	case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
++		ret = hm5065_write(sensor, HM5065_REG_ANTI_FLICKER_MODE, 0);
++		if (ret)
++			return ret;
++
++		return hm5065_write(sensor, HM5065_REG_FD_ENABLE_DETECT, 0);
++	case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
++	case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
++		ret = hm5065_write(sensor, HM5065_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_FD_ENABLE_DETECT, 0);
++		if (ret)
++			return ret;
++
++		freq = (val == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) ?
++			0x4b20 : 0x4bc0;
++
++		return hm5065_write16(sensor, HM5065_REG_FD_FLICKER_FREQUENCY,
++				      freq);
++	case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
++		ret = hm5065_write(sensor, HM5065_REG_FD_ENABLE_DETECT, 1);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write16(sensor, HM5065_REG_FD_MAX_NUMBER_ATTEMP,
++				     100);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write16(sensor, HM5065_REG_FD_FLICKER_FREQUENCY,
++				     0);
++		if (ret)
++			return ret;
++
++		return hm5065_write(sensor, HM5065_REG_FD_DETECTION_START, 1);
++	default:
++		return -EINVAL;
++	}
++}
++
++static int hm5065_set_colorfx(struct hm5065_dev *sensor, s32 val)
++{
++	int ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++			   HM5065_REG_EFFECTS_COLOR_NORMAL);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_NEGATIVE, 0);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_SOLARISING, 0);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_SKECTH, 0);
++	if (ret)
++		return ret;
++
++	switch (val) {
++	case V4L2_COLORFX_NONE:
++		return 0;
++	case V4L2_COLORFX_NEGATIVE:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_NEGATIVE, 1);
++	case V4L2_COLORFX_SOLARIZATION:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_SOLARISING, 1);
++	case V4L2_COLORFX_SKETCH:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_SKECTH, 1);
++	case V4L2_COLORFX_ANTIQUE:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_ANTIQUE);
++	case V4L2_COLORFX_SEPIA:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_SEPIA);
++	case V4L2_COLORFX_AQUA:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_AQUA);
++	case V4L2_COLORFX_BW:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_BLACK_WHITE);
++	default:
++		return -EINVAL;
++	}
++}
++
++#define AE_BIAS_MENU_DEFAULT_VALUE_INDEX 7
++static const s64 ae_bias_menu_values[] = {
++	-2100, -1800, -1500, -1200, -900, -600, -300,
++	0, 300, 600, 900, 1200, 1500, 1800, 2100
++};
++
++static const s8 ae_bias_menu_reg_values[] = {
++	-7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7
++};
++
++static int hm5065_set_exposure(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	bool is_auto = (ctrls->auto_exposure->val != V4L2_EXPOSURE_MANUAL);
++	int ret = 0;
++
++	if (ctrls->auto_exposure->is_new) {
++		ret = hm5065_write(sensor, HM5065_REG_EXPOSURE_MODE,
++				   is_auto ?
++				   HM5065_REG_EXPOSURE_MODE_AUTO :
++				   HM5065_REG_EXPOSURE_MODE_DIRECT_MANUAL);
++		if (ret)
++			return ret;
++
++		if (ctrls->auto_exposure->cur.val != ctrls->auto_exposure->val &&
++		    !is_auto) {
++			/*
++			 * Hack: At this point, there are current volatile
++			 * values in val, but control framework will not
++			 * update the cur values for our autocluster, as it
++			 * should. I couldn't find the reason. This fixes
++			 * it for our driver. Remove this after the kernel
++			 * is fixed.
++			 */
++			ctrls->exposure->cur.val = ctrls->exposure->val;
++			ctrls->d_gain->cur.val = ctrls->d_gain->val;
++			ctrls->a_gain->cur.val = ctrls->a_gain->val;
++		}
++	}
++
++	if (!is_auto && ctrls->exposure->is_new) {
++		ret = hm5065_write16(sensor,
++			   HM5065_REG_DIRECT_MODE_COARSE_INTEGRATION_LINES,
++			   ctrls->exposure->val);
++		if (ret)
++			return ret;
++	}
++
++	if (!is_auto && ctrls->d_gain->is_new) {
++		ret = hm5065_write16(sensor,
++				     HM5065_REG_DIRECT_MODE_DIGITAL_GAIN,
++				     hm5065_mili_to_fp16(ctrls->d_gain->val));
++		if (ret)
++			return ret;
++	}
++
++	if (!is_auto && ctrls->a_gain->is_new)
++		ret = hm5065_write16(sensor,
++				     HM5065_REG_DIRECT_MODE_CODED_ANALOG_GAIN,
++				     ctrls->a_gain->val);
++
++	return ret;
++}
++
++static int hm5065_3a_lock(struct hm5065_dev *sensor, struct v4l2_ctrl *ctrl)
++{
++	bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
++	bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
++	int ret = 0;
++
++	if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE
++	    && sensor->ctrls.auto_exposure->val == V4L2_EXPOSURE_AUTO) {
++		ret = hm5065_write(sensor, HM5065_REG_FREEZE_AUTO_EXPOSURE,
++				   ae_lock);
++		if (ret)
++			return ret;
++	}
++
++	if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE)
++	    && sensor->ctrls.wb->val == V4L2_WHITE_BALANCE_AUTO) {
++		ret = hm5065_write(sensor, HM5065_REG_WB_MISC_SETTINGS,
++				   awb_lock ?
++				   HM5065_REG_WB_MISC_SETTINGS_FREEZE_ALGO : 0);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int hm5065_set_auto_focus(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	bool auto_focus = ctrls->focus_auto->val;
++	int ret = 0;
++	u8 range;
++
++	if (auto_focus && ctrls->af_distance->is_new) {
++		switch (ctrls->af_distance->val) {
++		case V4L2_AUTO_FOCUS_RANGE_MACRO:
++			range = HM5065_REG_AF_RANGE_MACRO;
++			break;
++		case V4L2_AUTO_FOCUS_RANGE_AUTO:
++			range = HM5065_REG_AF_RANGE_FULL;
++			break;
++		case V4L2_AUTO_FOCUS_RANGE_INFINITY:
++			range = HM5065_REG_AF_RANGE_LANDSCAPE;
++			break;
++		default:
++			return -EINVAL;
++		}
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_RANGE, range);
++		if (ret)
++			return ret;
++	}
++
++	if (ctrls->focus_auto->is_new) {
++		v4l2_ctrl_activate(ctrls->af_start, !auto_focus);
++		v4l2_ctrl_activate(ctrls->af_stop, !auto_focus);
++		v4l2_ctrl_activate(ctrls->focus_relative, !auto_focus);
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   auto_focus ?
++				   HM5065_REG_AF_MODE_CONTINUOUS :
++				   HM5065_REG_AF_MODE_SINGLE);
++		if (ret)
++			return ret;
++
++		if (!auto_focus) {
++			ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++					 HM5065_REG_AF_COMMAND_RELEASED_BUTTON);
++			if (ret)
++				return ret;
++		}
++	}
++
++	if (!auto_focus && ctrls->af_start->is_new) {
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   HM5065_REG_AF_MODE_SINGLE);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++				   HM5065_REG_AF_COMMAND_RELEASED_BUTTON);
++		if (ret)
++			return ret;
++
++		usleep_range(190000, 200000);
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++				   HM5065_REG_AF_COMMAND_HALF_BUTTON);
++		if (ret)
++			return ret;
++	}
++
++	if (!auto_focus && ctrls->af_stop->is_new) {
++		ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++				   HM5065_REG_AF_COMMAND_RELEASED_BUTTON);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   HM5065_REG_AF_MODE_MANUAL);
++		if (ret)
++			return ret;
++	}
++
++	if (!auto_focus && ctrls->focus_relative->is_new &&
++	    ctrls->focus_relative->val) {
++		u8 cmd = 0xff;
++		s32 step = ctrls->focus_relative->val;
++
++		ctrls->focus_relative->val = 0;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   HM5065_REG_AF_MODE_MANUAL);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MANUAL_STEP_SIZE,
++				   abs(step));
++		if (ret)
++			return ret;
++
++		if (step < 0)
++			cmd = HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_INFINITY;
++		else if (step > 0)
++			cmd = HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_MACRO;
++
++		if (cmd != 0xff)
++			ret = hm5065_write(sensor, HM5065_REG_AF_LENS_COMMAND,
++					   cmd);
++
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int hm5065_set_white_balance(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	bool manual_wb = ctrls->wb->val == V4L2_WHITE_BALANCE_MANUAL;
++	int ret = 0, i;
++	s32 val;
++
++	if (ctrls->wb->is_new) {
++		for (i = 0; i < ARRAY_SIZE(hm5065_wb_opts); i++) {
++			if (hm5065_wb_opts[i][0] != ctrls->wb->val)
++				continue;
++
++			ret = hm5065_write(sensor, HM5065_REG_WB_MODE,
++					    hm5065_wb_opts[i][1]);
++			if (ret)
++				return ret;
++			goto next;
++		}
++
++		return -EINVAL;
++	}
++
++next:
++	if (ctrls->wb->is_new || ctrls->blue_balance->is_new) {
++		val = manual_wb ? ctrls->blue_balance->val : 1000;
++		ret = hm5065_write16(sensor, HM5065_REG_WB_HUE_B_BIAS,
++				     hm5065_mili_to_fp16(val));
++		if (ret)
++			return ret;
++	}
++
++	if (ctrls->wb->is_new || ctrls->red_balance->is_new) {
++		val = manual_wb ? ctrls->red_balance->val : 1000;
++		ret = hm5065_write16(sensor, HM5065_REG_WB_HUE_R_BIAS,
++				     hm5065_mili_to_fp16(val));
++	}
++
++	return ret;
++}
++
++static int hm5065_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	s32 val = ctrl->val;
++	unsigned int i;
++	int ret;
++	u8 reg;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	/*
++	 * If the device is not powered up by the host driver do
++	 * not apply any controls to H/W at this time. Instead
++	 * the controls will be restored right after power-up.
++	 */
++	if (!sensor->powered)
++		return 0;
++
++	switch (ctrl->id) {
++	case V4L2_CID_EXPOSURE_AUTO:
++		return hm5065_set_exposure(sensor);
++
++	case V4L2_CID_EXPOSURE_METERING:
++		if (val == V4L2_EXPOSURE_METERING_AVERAGE)
++			reg = HM5065_REG_EXPOSURE_METERING_FLAT;
++		else if (val == V4L2_EXPOSURE_METERING_CENTER_WEIGHTED)
++			reg = HM5065_REG_EXPOSURE_METERING_CENTERED;
++		else
++			return -EINVAL;
++
++		return hm5065_write(sensor, HM5065_REG_EXPOSURE_METERING, reg);
++
++	case V4L2_CID_AUTO_EXPOSURE_BIAS:
++		if (val < 0 || val >= ARRAY_SIZE(ae_bias_menu_reg_values))
++			return -EINVAL;
++
++		return hm5065_write(sensor, HM5065_REG_EXPOSURE_COMPENSATION,
++				    (u8)ae_bias_menu_reg_values[val]);
++
++	case V4L2_CID_FOCUS_AUTO:
++		return hm5065_set_auto_focus(sensor);
++
++	case V4L2_CID_CONTRAST:
++		return hm5065_write(sensor, HM5065_REG_CONTRAST, val);
++
++	case V4L2_CID_SATURATION:
++		return hm5065_write(sensor, HM5065_REG_COLOR_SATURATION, val);
++
++	case V4L2_CID_BRIGHTNESS:
++		return hm5065_write(sensor, HM5065_REG_BRIGHTNESS, val);
++
++	case V4L2_CID_POWER_LINE_FREQUENCY:
++		return hm5065_set_power_line_frequency(sensor, val);
++
++	case V4L2_CID_GAMMA:
++		return hm5065_write(sensor, HM5065_REG_P0_GAMMA_GAIN, val);
++
++	case V4L2_CID_VFLIP:
++		return hm5065_write(sensor, HM5065_REG_VERTICAL_FLIP,
++				    val ? 1 : 0);
++
++	case V4L2_CID_HFLIP:
++		return hm5065_write(sensor, HM5065_REG_HORIZONTAL_MIRROR,
++				    val ? 1 : 0);
++
++	case V4L2_CID_COLORFX:
++		return hm5065_set_colorfx(sensor, val);
++
++	case V4L2_CID_3A_LOCK:
++		return hm5065_3a_lock(sensor, ctrl);
++
++	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
++		return hm5065_set_white_balance(sensor);
++
++	case V4L2_CID_TEST_PATTERN_RED:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_RED, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENR:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_GREEN_R, val);
++
++	case V4L2_CID_TEST_PATTERN_BLUE:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_BLUE, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENB:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_GREEN_B, val);
++
++	case V4L2_CID_TEST_PATTERN:
++		for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++			v4l2_ctrl_activate(ctrls->test_data[i],
++					   val == 6); /* solid color */
++
++		ret = hm5065_write(sensor, HM5065_REG_ENABLE_TEST_PATTERN,
++				   val == 0 ? 0 : 1);
++		if (ret)
++			return ret;
++
++		return hm5065_write(sensor, HM5065_REG_TEST_PATTERN, val);
++
++	default:
++		return -EINVAL;
++	}
++}
++
++static const struct v4l2_ctrl_ops hm5065_ctrl_ops = {
++	.g_volatile_ctrl = hm5065_g_volatile_ctrl,
++	.s_ctrl = hm5065_s_ctrl,
++};
++
++static const char * const test_pattern_menu[] = {
++	"Disabled",
++	"Horizontal gray scale",
++	"Vertical gray scale",
++	"Diagonal gray scale",
++	"PN28",
++	"PN9 (bus test)",
++	"Solid color",
++	"Color bars",
++	"Graduated color bars",
++};
++
++static int hm5065_init_controls(struct hm5065_dev *sensor)
++{
++	const struct v4l2_ctrl_ops *ops = &hm5065_ctrl_ops;
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++	u8 wb_max = 0;
++	u64 wb_mask = 0;
++	unsigned int i;
++	int ret;
++
++	v4l2_ctrl_handler_init(hdl, 32);
++
++	/* we can use our own mutex for the ctrl lock */
++	hdl->lock = &sensor->lock;
++
++	ctrls->auto_exposure = v4l2_ctrl_new_std_menu(hdl, ops,
++						      V4L2_CID_EXPOSURE_AUTO,
++						      V4L2_EXPOSURE_MANUAL, 0,
++						      V4L2_EXPOSURE_AUTO);
++	ctrls->exposure = v4l2_ctrl_new_std(hdl, ops,
++					    V4L2_CID_EXPOSURE,
++					    1, HM5065_SENSOR_HEIGHT, 1, 30);
++	ctrls->d_gain = v4l2_ctrl_new_std(hdl, ops,
++					  V4L2_CID_DIGITAL_GAIN,
++					  1000, 4000, 1, 1000);
++
++	ctrls->a_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
++					  0, 0xf4, 1, 0);
++
++	ctrls->metering =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_EXPOSURE_METERING,
++				       V4L2_EXPOSURE_METERING_CENTER_WEIGHTED,
++				       0, V4L2_EXPOSURE_METERING_AVERAGE);
++	ctrls->exposure_bias =
++		v4l2_ctrl_new_int_menu(hdl, ops,
++				       V4L2_CID_AUTO_EXPOSURE_BIAS,
++				       ARRAY_SIZE(ae_bias_menu_values) - 1,
++				       AE_BIAS_MENU_DEFAULT_VALUE_INDEX,
++				       ae_bias_menu_values);
++
++	for (i = 0; i < ARRAY_SIZE(hm5065_wb_opts); i++) {
++		if (wb_max < hm5065_wb_opts[i][0])
++			wb_max = hm5065_wb_opts[i][0];
++		wb_mask |= BIT(hm5065_wb_opts[i][0]);
++	}
++
++	ctrls->wb = v4l2_ctrl_new_std_menu(hdl, ops,
++			V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
++			wb_max, ~wb_mask, V4L2_WHITE_BALANCE_AUTO);
++
++	ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
++						0, 4000, 1, 1000);
++	ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
++					       0, 4000, 1, 1000);
++
++	ctrls->gamma = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA,
++					 0, 31, 1, 20);
++
++	ctrls->colorfx =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX, 15,
++				       ~(BIT(V4L2_COLORFX_NONE) |
++					 BIT(V4L2_COLORFX_NEGATIVE) |
++					 BIT(V4L2_COLORFX_SOLARIZATION) |
++					 BIT(V4L2_COLORFX_SKETCH) |
++					 BIT(V4L2_COLORFX_SEPIA) |
++					 BIT(V4L2_COLORFX_ANTIQUE) |
++					 BIT(V4L2_COLORFX_AQUA) |
++					 BIT(V4L2_COLORFX_BW)),
++				       V4L2_COLORFX_NONE);
++
++	ctrls->pl_freq =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
++				V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
++				V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
++
++	ctrls->hflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_HFLIP, 0, 1, 1, 0);
++	ctrls->vflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_VFLIP, 0, 1, 1, 0);
++
++	ctrls->focus_auto = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_AUTO,
++					      0, 1, 1, 1);
++
++	ctrls->af_start = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_START,
++					    0, 1, 1, 0);
++
++	ctrls->af_stop = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_STOP,
++					   0, 1, 1, 0);
++
++	ctrls->af_status = v4l2_ctrl_new_std(hdl, ops,
++					     V4L2_CID_AUTO_FOCUS_STATUS, 0,
++					     (V4L2_AUTO_FOCUS_STATUS_BUSY |
++					      V4L2_AUTO_FOCUS_STATUS_REACHED |
++					      V4L2_AUTO_FOCUS_STATUS_FAILED),
++					     0, V4L2_AUTO_FOCUS_STATUS_IDLE);
++
++	ctrls->af_distance =
++		v4l2_ctrl_new_std_menu(hdl, ops,
++				       V4L2_CID_AUTO_FOCUS_RANGE,
++				       V4L2_AUTO_FOCUS_RANGE_MACRO,
++				       ~(BIT(V4L2_AUTO_FOCUS_RANGE_AUTO) |
++					 BIT(V4L2_AUTO_FOCUS_RANGE_INFINITY) |
++					 BIT(V4L2_AUTO_FOCUS_RANGE_MACRO)),
++				       V4L2_AUTO_FOCUS_RANGE_AUTO);
++
++	ctrls->focus_relative = v4l2_ctrl_new_std(hdl, ops,
++						  V4L2_CID_FOCUS_RELATIVE,
++						  -100, 100, 1, 0);
++
++	ctrls->brightness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS,
++					      0, 200, 1, 90);
++	ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
++					      0, 200, 1, 110);
++	ctrls->contrast = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST,
++					    0, 200, 1, 108);
++
++	ctrls->aaa_lock = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_3A_LOCK,
++					    0, 0x7, 0, 0);
++
++	ctrls->test_pattern =
++		v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
++					     ARRAY_SIZE(test_pattern_menu) - 1,
++					     0, 0, test_pattern_menu);
++	for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++		ctrls->test_data[i] =
++			v4l2_ctrl_new_std(hdl, ops,
++					  V4L2_CID_TEST_PATTERN_RED + i,
++					  0, 1023, 1, 0);
++
++	if (hdl->error) {
++		ret = hdl->error;
++		goto free_ctrls;
++	}
++
++	ctrls->af_status->flags |= V4L2_CTRL_FLAG_VOLATILE |
++		V4L2_CTRL_FLAG_READ_ONLY;
++
++	v4l2_ctrl_auto_cluster(3, &ctrls->wb, V4L2_WHITE_BALANCE_MANUAL, false);
++	v4l2_ctrl_auto_cluster(4, &ctrls->auto_exposure, V4L2_EXPOSURE_MANUAL,
++			       true);
++	v4l2_ctrl_cluster(6, &ctrls->focus_auto);
++
++	sensor->sd.ctrl_handler = hdl;
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(hdl);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Video ops */
++
++static int hm5065_get_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *sd_state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	fi->interval = sensor->frame_interval;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int hm5065_get_max_binning(int width, int height)
++{
++	if (width < HM5065_SENSOR_WIDTH / 4 &&
++	    height < HM5065_SENSOR_HEIGHT / 4)
++		return 4;
++	else if (width < HM5065_SENSOR_WIDTH / 2 &&
++		 height < HM5065_SENSOR_HEIGHT / 2)
++		return 2;
++
++	return 1;
++}
++
++static int hm5065_get_max_fps(int width, int height)
++{
++	int max_fps, bin_factor;
++
++	// more bining allows for faster readouts
++	bin_factor = hm5065_get_max_binning(width, height);
++	max_fps = 25000000 / (width * height * 2) * bin_factor;
++
++	return clamp(max_fps, 1, 60);
++}
++
++static int hm5065_set_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *sd_state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret = 0, fps, max_fps;
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++
++	max_fps = hm5065_get_max_fps(sensor->fmt.width, sensor->fmt.height);
++
++	/* user requested infinite frame rate */
++	if (fi->interval.numerator == 0)
++		fps = max_fps;
++	else
++		fps = DIV_ROUND_CLOSEST(fi->interval.denominator,
++					fi->interval.numerator);
++
++	fps = clamp(fps, 1, max_fps);
++
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = fps;
++	fi->interval = sensor->frame_interval;
++
++	if (sensor->streaming) {
++		ret = hm5065_write16(sensor, HM5065_REG_DESIRED_FRAME_RATE_NUM,
++				     fps);
++		if (ret)
++			goto err_unlock;
++
++		ret = hm5065_write(sensor, HM5065_REG_DESIRED_FRAME_RATE_DEN,
++				   1);
++	}
++
++err_unlock:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++static int hm5065_setup_mode(struct hm5065_dev *sensor)
++{
++	const struct hm5065_pixfmt *pix_fmt;
++	u8 sensor_mode;
++	int ret, fps;
++
++	pix_fmt = hm5065_find_format(sensor->fmt.code);
++	if (!pix_fmt) {
++		dev_err(&sensor->i2c_client->dev,
++			"pixel format not supported %u\n", sensor->fmt.code);
++		return -EINVAL;
++	}
++
++	ret = hm5065_write(sensor, HM5065_REG_USER_COMMAND,
++			   HM5065_REG_USER_COMMAND_POWEROFF);
++	if (ret)
++		return ret;
++
++	switch (hm5065_get_max_binning(sensor->fmt.width, sensor->fmt.height)) {
++	case 4:
++		sensor_mode = HM5065_REG_SENSOR_MODE_BINNING_4X4;
++		break;
++	case 2:
++		sensor_mode = HM5065_REG_SENSOR_MODE_BINNING_2X2;
++		break;
++	default:
++		sensor_mode = HM5065_REG_SENSOR_MODE_FULLSIZE;
++	}
++
++	ret = hm5065_write(sensor, HM5065_REG_P0_SENSOR_MODE, sensor_mode);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write16(sensor, HM5065_REG_P0_MANUAL_HSIZE,
++			     sensor->fmt.width);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write16(sensor, HM5065_REG_P0_MANUAL_VSIZE,
++			     sensor->fmt.height);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_P0_IMAGE_SIZE,
++			   HM5065_REG_IMAGE_SIZE_MANUAL);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_P0_DATA_FORMAT,
++			   pix_fmt->data_fmt);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_YCRCB_ORDER,
++			   pix_fmt->ycbcr_order);
++	if (ret)
++		return ret;
++
++	/* without this, brightness, contrast and saturation will not work */
++	ret = hm5065_write(sensor, HM5065_REG_COLORSPACE, 9);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_BUS_DATA_FORMAT,
++			   pix_fmt->fmt_setup);
++	if (ret)
++		return ret;
++
++	fps = hm5065_get_max_fps(sensor->fmt.width, sensor->fmt.height);
++	fps = clamp(fps, 1, (int)sensor->frame_interval.denominator);
++
++	ret = hm5065_write16(sensor, HM5065_REG_DESIRED_FRAME_RATE_NUM, fps);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_DESIRED_FRAME_RATE_DEN, 1);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int hm5065_set_stream(struct hm5065_dev *sensor, int enable)
++{
++	return hm5065_write(sensor, HM5065_REG_USER_COMMAND, enable ?
++			    HM5065_REG_USER_COMMAND_RUN :
++			    HM5065_REG_USER_COMMAND_STOP);
++}
++
++static int hm5065_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	if (sensor->streaming == !enable) {
++		if (enable && sensor->pending_mode_change) {
++			ret = hm5065_setup_mode(sensor);
++			if (ret)
++				goto out;
++		}
++
++		ret = hm5065_set_stream(sensor, enable);
++		if (ret)
++			goto out;
++
++		if (enable && sensor->ctrls.focus_auto->cur.val) {
++			msleep(100);
++
++			/* checking error here is not super important */
++			hm5065_write(sensor, HM5065_REG_AF_MODE,
++				     HM5065_REG_AF_MODE_CONTINUOUS);
++		}
++
++		sensor->streaming = !!enable;
++	}
++
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Pad ops */
++
++static int hm5065_enum_mbus_code(struct v4l2_subdev *sd,
++				 struct v4l2_subdev_state *sd_state,
++				 struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad != 0)
++		return -EINVAL;
++	if (code->index >= HM5065_NUM_FORMATS)
++		return -EINVAL;
++
++	code->code = hm5065_formats[code->index].code;
++
++	return 0;
++}
++
++static int hm5065_enum_frame_size(struct v4l2_subdev *sd,
++				  struct v4l2_subdev_state *sd_state,
++				  struct v4l2_subdev_frame_size_enum *fse)
++{
++	if (fse->pad != 0)
++		return -EINVAL;
++	if (fse->index != 0)
++		return -EINVAL;
++
++	fse->min_width = HM5065_CAPTURE_WIDTH_MIN;
++	fse->min_height = HM5065_CAPTURE_HEIGHT_MIN;
++
++	fse->max_width = HM5065_SENSOR_WIDTH;
++	fse->max_height = HM5065_SENSOR_HEIGHT;
++
++	return 0;
++}
++
++static int hm5065_enum_frame_interval(struct v4l2_subdev *sd,
++				      struct v4l2_subdev_state *sd_state,
++				      struct v4l2_subdev_frame_interval_enum
++				      *fie)
++{
++	struct v4l2_fract tpf;
++	u32 max_fps, width, height;
++
++	if (fie->pad != 0)
++		return -EINVAL;
++
++	width = clamp(fie->width, HM5065_CAPTURE_WIDTH_MIN,
++		      HM5065_SENSOR_WIDTH);
++	height = clamp(fie->height, HM5065_CAPTURE_HEIGHT_MIN,
++		       HM5065_SENSOR_HEIGHT);
++
++	max_fps = hm5065_get_max_fps(width, height);
++
++	if (fie->index + 1 > max_fps)
++		return -EINVAL;
++
++	tpf.numerator = 1;
++	tpf.denominator = fie->index + 1;
++	fie->interval = tpf;
++
++	return 0;
++}
++
++static int hm5065_get_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	struct v4l2_mbus_framefmt *mf;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		format->format = *mf;
++		return 0;
++	}
++
++	mutex_lock(&sensor->lock);
++	format->format = sensor->fmt;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int hm5065_set_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	const struct hm5065_pixfmt *pixfmt;
++	int ret = 0;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	/* check if we support requested mbus fmt */
++	pixfmt = hm5065_find_format(mf->code);
++	if (!pixfmt)
++		pixfmt = &hm5065_formats[0];
++
++	mf->code = pixfmt->code;
++	mf->colorspace = pixfmt->colorspace;
++	mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
++	mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++	mf->quantization = V4L2_QUANTIZATION_DEFAULT;
++	mf->field = V4L2_FIELD_NONE;
++
++	mutex_lock(&sensor->lock);
++
++	mf->width = clamp(mf->width, HM5065_CAPTURE_WIDTH_MIN,
++			  HM5065_SENSOR_WIDTH);
++	mf->height = clamp(mf->height, HM5065_CAPTURE_HEIGHT_MIN,
++			  HM5065_SENSOR_HEIGHT);
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		struct v4l2_mbus_framefmt *try_mf;
++
++		try_mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		*try_mf = *mf;
++		goto out;
++	}
++
++	if (sensor->streaming) {
++		ret = -EBUSY;
++		goto out;
++	}
++
++	sensor->fmt = *mf;
++	sensor->pending_mode_change = true;
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Core Ops */
++
++static void hm5065_chip_enable(struct hm5065_dev *sensor, bool enable)
++{
++	gpiod_set_value(sensor->enable_gpio, enable ? 1 : 0);
++	gpiod_set_value(sensor->reset_gpio, enable ? 0 : 1);
++}
++
++static int hm5065_configure(struct hm5065_dev *sensor)
++{
++	int ret;
++	u16 device_id;
++	const struct hm5065_clk_lut *lut;
++	unsigned long xclk_freq;
++
++	ret = hm5065_read16(sensor, HM5065_REG_DEVICE_ID, &device_id);
++	if (ret)
++		return ret;
++
++	if (device_id != HM5065_REG_DEVICE_ID_VALUE) {
++		dev_err(&sensor->i2c_client->dev,
++			"unsupported device id: 0x%04x\n",
++			(unsigned int)device_id);
++		return -EINVAL;
++	}
++
++	xclk_freq = clk_get_rate(sensor->xclk);
++	lut = hm5065_find_clk_lut(xclk_freq);
++	if (!lut) {
++		dev_err(&sensor->i2c_client->dev,
++			"xclk frequency out of range: %lu Hz\n", xclk_freq);
++		return -EINVAL;
++	}
++
++	ret = hm5065_write(sensor, HM5065_REG_EXCLOCKLUT, lut->lut_id);
++	if (ret)
++		return ret;
++
++	ret = hm5065_load_firmware(sensor, HM5065_AF_FIRMWARE);
++	if (ret < 0)
++		return ret;
++
++	if (ret == 0) /* ret == 1 means firmware file missing */
++		mdelay(200);
++
++	ret = hm5065_load_firmware(sensor, HM5065_FIRMWARE_PARAMETERS);
++	if (ret < 0)
++		return ret;
++
++	if (sensor->ep.bus_type == V4L2_MBUS_BT656) {
++		ret = hm5065_write(sensor, HM5065_REG_BUS_CONFIG,
++				   HM5065_REG_BUS_CONFIG_BT656);
++	} else {
++		ret = hm5065_write(sensor, HM5065_REG_BUS_CONFIG,
++				   HM5065_REG_BUS_CONFIG_PARALLEL_HH_VL);
++	}
++
++	return ret;
++}
++
++static int hm5065_set_power(struct hm5065_dev *sensor, bool on)
++{
++	int ret = 0;
++
++	if (on) {
++		ret = regulator_bulk_enable(HM5065_NUM_SUPPLIES,
++					    sensor->supplies);
++		if (ret)
++			return ret;
++
++		ret = clk_prepare_enable(sensor->xclk);
++		if (ret)
++			goto power_off;
++
++		ret = clk_set_rate(sensor->xclk, 24000000);
++		if (ret)
++			goto xclk_off;
++
++		usleep_range(1000, 2000);
++		hm5065_chip_enable(sensor, false);
++		usleep_range(1000, 2000);
++		hm5065_chip_enable(sensor, true);
++		usleep_range(50000, 70000);
++
++		ret = hm5065_configure(sensor);
++		if (ret)
++			goto xclk_off;
++
++		ret = hm5065_setup_mode(sensor);
++		if (ret)
++			goto xclk_off;
++
++		return 0;
++	}
++
++xclk_off:
++	clk_disable_unprepare(sensor->xclk);
++power_off:
++	hm5065_chip_enable(sensor, false);
++	regulator_bulk_disable(HM5065_NUM_SUPPLIES, sensor->supplies);
++	msleep(100);
++	return ret;
++}
++
++static int hm5065_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	bool power_up, power_down;
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	power_up = on && !sensor->powered;
++	power_down = !on && sensor->powered;
++
++	if (power_up || power_down) {
++		ret = hm5065_set_power(sensor, power_up);
++		if (!ret)
++			sensor->powered = on;
++	}
++
++	mutex_unlock(&sensor->lock);
++
++	if (!ret && power_up) {
++		/* restore controls */
++		ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
++		if (ret)
++			hm5065_s_power(sd, 0);
++	}
++
++	return ret;
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int hm5065_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret;
++	u8 val = 0;
++
++	if (reg->reg > 0xffff)
++		return -EINVAL;
++
++	reg->size = 1;
++
++	mutex_lock(&sensor->lock);
++	ret = hm5065_read(sensor, reg->reg, &val);
++	mutex_unlock(&sensor->lock);
++	if (ret)
++		return -EIO;
++
++	reg->val = val;
++	return 0;
++}
++
++static int hm5065_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret;
++
++	if (reg->reg > 0xffff || reg->val > 0xff)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	ret = hm5065_write(sensor, reg->reg, reg->val);
++	mutex_unlock(&sensor->lock);
++
++	return ret;
++}
++#endif
++
++/* }}} */
++
++static const struct v4l2_subdev_core_ops hm5065_core_ops = {
++	.s_power = hm5065_s_power,
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = hm5065_g_register,
++	.s_register = hm5065_s_register,
++#endif
++};
++
++static const struct v4l2_subdev_pad_ops hm5065_pad_ops = {
++	.enum_mbus_code = hm5065_enum_mbus_code,
++	.enum_frame_size = hm5065_enum_frame_size,
++	.enum_frame_interval = hm5065_enum_frame_interval,
++	.get_fmt = hm5065_get_fmt,
++	.set_fmt = hm5065_set_fmt,
++	.get_frame_interval = hm5065_get_frame_interval,
++	.set_frame_interval = hm5065_set_frame_interval,
++};
++
++static const struct v4l2_subdev_video_ops hm5065_video_ops = {
++	.s_stream = hm5065_s_stream,
++};
++
++static const struct v4l2_subdev_ops hm5065_subdev_ops = {
++	.core = &hm5065_core_ops,
++	.pad = &hm5065_pad_ops,
++	.video = &hm5065_video_ops,
++};
++
++static int hm5065_get_regulators(struct hm5065_dev *sensor)
++{
++	int i;
++
++	for (i = 0; i < HM5065_NUM_SUPPLIES; i++)
++		sensor->supplies[i].supply = hm5065_supply_name[i];
++
++	return devm_regulator_bulk_get(&sensor->i2c_client->dev,
++				       HM5065_NUM_SUPPLIES,
++				       sensor->supplies);
++}
++
++#define HM5065_PARALLEL_SUPPORT_FLAGS \
++	(V4L2_MBUS_HSYNC_ACTIVE_LOW | V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
++	 V4L2_MBUS_PCLK_SAMPLE_FALLING | V4L2_MBUS_DATA_ACTIVE_HIGH)
++
++static int hm5065_probe(struct i2c_client *client)
++{
++	struct device *dev = &client->dev;
++	struct fwnode_handle *endpoint;
++	struct hm5065_dev *sensor;
++	int ret;
++
++	sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
++	if (!sensor)
++		return -ENOMEM;
++
++	sensor->i2c_client = client;
++
++	sensor->fmt.code = hm5065_formats[0].code;
++	sensor->fmt.width = 1280;
++	sensor->fmt.height = 720;
++	sensor->fmt.field = V4L2_FIELD_NONE;
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = 15;
++	sensor->pending_mode_change = true;
++
++	endpoint = fwnode_graph_get_next_endpoint(
++		of_fwnode_handle(client->dev.of_node), NULL);
++	if (!endpoint) {
++		dev_err(dev, "endpoint node not found\n");
++		return -EINVAL;
++	}
++
++	ret = v4l2_fwnode_endpoint_parse(endpoint, &sensor->ep);
++	fwnode_handle_put(endpoint);
++	if (ret) {
++		dev_err(dev, "could not parse endpoint\n");
++		return ret;
++	}
++
++	/*
++	 * We don't know how to configure the camera for any other parallel
++	 * mode, yet.
++	 */
++	if (sensor->ep.bus_type != V4L2_MBUS_BT656 &&
++	    !(sensor->ep.bus_type == V4L2_MBUS_PARALLEL &&
++	      (sensor->ep.bus.parallel.flags & HM5065_PARALLEL_SUPPORT_FLAGS) ==
++	      HM5065_PARALLEL_SUPPORT_FLAGS)) {
++		dev_err(dev, "unsupported bus configuration %d/%08x\n",
++			sensor->ep.bus_type, sensor->ep.bus.parallel.flags);
++		return -EINVAL;
++	}
++
++	/* get system clock (xclk) */
++	sensor->xclk = devm_clk_get(dev, "xclk");
++	if (IS_ERR(sensor->xclk)) {
++		dev_err(dev, "failed to get xclk\n");
++		return PTR_ERR(sensor->xclk);
++	}
++
++	sensor->enable_gpio = devm_gpiod_get_optional(dev, "enable",
++							  GPIOD_OUT_LOW);
++	sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
++						     GPIOD_OUT_HIGH);
++
++	if (!sensor->enable_gpio && !sensor->reset_gpio) {
++		dev_err(dev,
++			"either chip enable or reset pin must be configured\n");
++		return ret;
++	}
++
++	v4l2_i2c_subdev_init(&sensor->sd, client, &hm5065_subdev_ops);
++
++	sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
++	sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
++	if (ret)
++		return ret;
++
++	ret = hm5065_get_regulators(sensor);
++	if (ret)
++		return ret;
++
++	mutex_init(&sensor->lock);
++
++	ret = hm5065_init_controls(sensor);
++	if (ret)
++		goto entity_cleanup;
++
++	ret = v4l2_async_register_subdev(&sensor->sd);
++	if (ret)
++		goto free_ctrls;
++
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++entity_cleanup:
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	return ret;
++}
++
++static void hm5065_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++
++	v4l2_async_unregister_subdev(&sensor->sd);
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++}
++
++static const struct i2c_device_id hm5065_id[] = {
++	{"hm5065", 0},
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(i2c, hm5065_id);
++
++static const struct of_device_id hm5065_dt_ids[] = {
++	{ .compatible = "himax,hm5065" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, hm5065_dt_ids);
++
++static struct i2c_driver hm5065_i2c_driver = {
++	.driver = {
++		.name  = "hm5065",
++		.of_match_table	= hm5065_dt_ids,
++	},
++	.id_table = hm5065_id,
++	.probe    = hm5065_probe,
++	.remove   = hm5065_remove,
++};
++
++module_i2c_driver(hm5065_i2c_driver);
++
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("HM5065 Camera Subdev Driver");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
new file mode 100644
index 000000000000..4035ec5c555d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
@@ -0,0 +1,52 @@
+From 372d67e05b69c9897da7d1958fba4f0fd5d7785d Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 13 Jan 2024 21:00:27 +0100
+Subject: media: i2c: gc2145: Move upstream driver out of the way
+
+Upstream only implements MIPI CSI, but we already have a driver
+with parallel bus support.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/Kconfig                     | 4 ++--
+ drivers/media/i2c/Makefile                    | 2 +-
+ drivers/media/i2c/{gc2145.c => gc2145-mipi.c} | 0
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+ rename drivers/media/i2c/{gc2145.c => gc2145-mipi.c} (100%)
+
+diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
+index 7b6eea2aef11..1b5f112a705a 100644
+--- a/drivers/media/i2c/Kconfig
++++ b/drivers/media/i2c/Kconfig
+@@ -70,9 +70,9 @@ config VIDEO_GC0308
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called gc0308.
+ 
+-config VIDEO_GC2145
++config VIDEO_GC2145_MIPI
+ 	select V4L2_CCI_I2C
+-	tristate "GalaxyCore GC2145 sensor support"
++	tristate "GalaxyCore GC2145 sensor support - MIPI variant"
+ 	help
+ 	  This is a V4L2 sensor-level driver for GalaxyCore GC2145
+ 	  2 Mpixel camera.
+diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
+index aed36d8be369..e84186ed81cb 100644
+--- a/drivers/media/i2c/Makefile
++++ b/drivers/media/i2c/Makefile
+@@ -38,7 +38,7 @@ obj-$(CONFIG_VIDEO_DW9768) += dw9768.o
+ obj-$(CONFIG_VIDEO_DW9807_VCM) += dw9807-vcm.o
+ obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/
+ obj-$(CONFIG_VIDEO_GC0308) += gc0308.o
+-obj-$(CONFIG_VIDEO_GC2145) += gc2145.o
++obj-$(CONFIG_VIDEO_GC2145_MIPI) += gc2145-mipi.o
+ obj-$(CONFIG_VIDEO_HI556) += hi556.o
+ obj-$(CONFIG_VIDEO_HI846) += hi846.o
+ obj-$(CONFIG_VIDEO_HI847) += hi847.o
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145-mipi.c
+similarity index 100%
+rename from drivers/media/i2c/gc2145.c
+rename to drivers/media/i2c/gc2145-mipi.c
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
new file mode 100644
index 000000000000..8c10cdd0c92d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
@@ -0,0 +1,43 @@
+From a4063e0c1dc44ee6a134c618e1715fe06bddf45f Mon Sep 17 00:00:00 2001
+From: Robert Mader <robert.mader@collabora.com>
+Date: Mon, 6 May 2024 16:36:05 -0700
+Subject: media: i2c: gc2145: Parse and register properties
+
+In order to propagate V4L2_CID_CAMERA_SENSOR_ROTATION and
+V4L2_CID_CAMERA_ORIENTATION values from the DT to userspace.
+
+Signed-off-by: Robert Mader <robert.mader@collabora.com>
+---
+ drivers/media/i2c/gc2145.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index b505b3f07387..d80e457f275b 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -1272,6 +1272,7 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	const struct v4l2_ctrl_ops *ops = &gc2145_ctrl_ops;
+ 	struct gc2145_ctrls *ctrls = &sensor->ctrls;
+ 	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++	struct v4l2_fwnode_device_properties props;
+ 	//u8 wb_max = 0;
+ 	//u64 wb_mask = 0;
+ 	//unsigned int i;
+@@ -1324,6 +1325,14 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	ctrls->vflip = v4l2_ctrl_new_std(hdl, ops,
+ 					 V4L2_CID_VFLIP, 0, 1, 1, 0);
+ 
++	ret = v4l2_fwnode_device_parse(&sensor->i2c_client->dev, &props);
++	if (ret)
++		goto free_ctrls;
++
++	ret = v4l2_ctrl_new_fwnode_properties(hdl, &gc2145_ctrl_ops,
++					      &props);
++	if (ret)
++		goto free_ctrls;
+ 
+ 	/* Test patterns */
+ 	ctrls->test_pattern =
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
new file mode 100644
index 000000000000..af67aaf7946e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
@@ -0,0 +1,24 @@
+From 7266f539fc31f10e6363096ae175efbbce082de0 Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Thu, 29 Dec 2022 11:10:41 +0000
+Subject: media: ov5640: Add read-only property for vblank
+
+---
+ drivers/media/i2c/ov5640.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 59a644dc36e2..1b132ee43c81 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -3845,6 +3845,7 @@ static int ov5640_init_controls(struct ov5640_dev *sensor)
+ 	ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+ 	ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+ 	ctrls->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++	ctrls->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+ 	ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
+ 	ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
new file mode 100644
index 000000000000..545969bb50a3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
@@ -0,0 +1,119 @@
+From 2f0934cf586c91b178c28622a36dbf618b2850a3 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 8 Nov 2023 19:13:37 +0100
+Subject: media: ov5640: Don't powerup the sensor during driver probe
+
+It causes autofocus clicking during boot on some devices, and
+it's enough to do it when turning on the sensor power by media
+pipeline via s_power callback, later on.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 55 +++++++++-----------------------------
+ 1 file changed, 12 insertions(+), 43 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 87129127ced3..1b8344b226b0 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2496,6 +2496,7 @@ static void ov5640_powerup_sequence(struct ov5640_dev *sensor)
+ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
++	u16 chip_id;
+ 	int ret;
+ 
+ 	ret = clk_prepare_enable(sensor->xclk);
+@@ -2519,6 +2520,13 @@ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ 	if (ret)
+ 		goto power_off;
+ 
++	ret = ov5640_read_reg16(sensor, OV5640_REG_CHIP_ID, &chip_id);
++	if (ret) {
++		dev_err(&client->dev, "%s: failed to read chip identifier\n",
++			__func__);
++		goto power_off;
++	}
++
+ 	return 0;
+ 
+ power_off:
+@@ -3840,28 +3848,6 @@ static int ov5640_get_regulators(struct ov5640_dev *sensor)
+ 				       sensor->supplies);
+ }
+ 
+-static int ov5640_check_chip_id(struct ov5640_dev *sensor)
+-{
+-	struct i2c_client *client = sensor->i2c_client;
+-	int ret = 0;
+-	u16 chip_id;
+-
+-	ret = ov5640_read_reg16(sensor, OV5640_REG_CHIP_ID, &chip_id);
+-	if (ret) {
+-		dev_err(&client->dev, "%s: failed to read chip identifier\n",
+-			__func__);
+-		return ret;
+-	}
+-
+-	if (chip_id != 0x5640) {
+-		dev_err(&client->dev, "%s: wrong chip identifier, expected 0x5640, got 0x%x\n",
+-			__func__, chip_id);
+-		return -ENXIO;
+-	}
+-
+-	return 0;
+-}
+-
+ static int ov5640_probe(struct i2c_client *client)
+ {
+ 	struct device *dev = &client->dev;
+@@ -3962,35 +3948,16 @@ static int ov5640_probe(struct i2c_client *client)
+ 	if (ret)
+ 		goto entity_cleanup;
+ 
+-	ret = ov5640_sensor_resume(dev);
+-	if (ret) {
+-		dev_err(dev, "failed to power on\n");
+-		goto free_ctrls;
+-	}
+-
+-	pm_runtime_set_active(dev);
+-	pm_runtime_get_noresume(dev);
+-	pm_runtime_enable(dev);
+-
+-	ret = ov5640_check_chip_id(sensor);
+-	if (ret)
+-		goto err_pm_runtime;
+-
+ 	ret = v4l2_async_register_subdev_sensor(&sensor->sd);
+ 	if (ret)
+-		goto err_pm_runtime;
++		goto free_ctrls;
+ 
++	pm_runtime_enable(dev);
+ 	pm_runtime_set_autosuspend_delay(dev, 1000);
+ 	pm_runtime_use_autosuspend(dev);
+-	pm_runtime_mark_last_busy(dev);
+-	pm_runtime_put_autosuspend(dev);
+ 
+ 	return 0;
+ 
+-err_pm_runtime:
+-	pm_runtime_put_noidle(dev);
+-	pm_runtime_disable(dev);
+-	ov5640_sensor_suspend(dev);
+ free_ctrls:
+ 	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
+ entity_cleanup:
+@@ -4005,6 +3972,8 @@ static void ov5640_remove(struct i2c_client *client)
+ 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
+ 	struct device *dev = &client->dev;
+ 
++	pm_runtime_dont_use_autosuspend(dev);
++
+ 	pm_runtime_disable(dev);
+ 	if (!pm_runtime_status_suspended(dev))
+ 		ov5640_sensor_suspend(dev);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
new file mode 100644
index 000000000000..5603a0ece2a9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
@@ -0,0 +1,50 @@
+From 4c12289053f1bb6b52682dc9c38abf491f20d241 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 24 Jan 2020 18:25:59 +0100
+Subject: media: ov5640: [Experiment] Try to disable denoising/sharpening
+
+Not sure how this works exactly. More tests are needed.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 5162d45fe73b..d19f6edae9fd 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2326,6 +2326,7 @@ static int ov5640_set_mode(struct ov5640_dev *sensor)
+ 	bool auto_gain = sensor->ctrls.auto_gain->val == 1;
+ 	bool auto_exp =  sensor->ctrls.auto_exp->val == V4L2_EXPOSURE_AUTO;
+ 	int ret;
++	u8 tmp;
+ 
+ 	dn_mode = mode->dn_mode;
+ 	orig_dn_mode = orig_mode->dn_mode;
+@@ -2389,6 +2390,22 @@ static int ov5640_set_mode(struct ov5640_dev *sensor)
+ 	if (ret < 0)
+ 		return ret;
+ 
++	ret = ov5640_read_reg(sensor, 0x5308, &tmp);
++	if (ret)
++		return ret;
++
++	ret = ov5640_write_reg(sensor, 0x5308, tmp | 0x10 | 0x40);
++	if (ret)
++		return ret;
++
++	ret = ov5640_write_reg(sensor, 0x5306, 0);
++	if (ret)
++		return ret;
++
++	ret = ov5640_write_reg(sensor, 0x5302, 0);
++	if (ret)
++		return ret;
++
+ 	sensor->pending_mode_change = false;
+ 	sensor->last_mode = mode;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
new file mode 100644
index 000000000000..efe2821af717
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
@@ -0,0 +1,113 @@
+From 5fef48c63bd50de5732ff4201ef3144903e24a65 Mon Sep 17 00:00:00 2001
+From: Benjamin Schaaf <ben.schaaf@gmail.com>
+Date: Mon, 22 Nov 2021 23:38:26 +1100
+Subject: media: ov5640: Fix focus commands blocking until complete
+
+Previously setting the focus controls would block until the sensor
+completed the focus routine.
+---
+ drivers/media/i2c/ov5640.c | 67 ++++++++++----------------------------
+ 1 file changed, 18 insertions(+), 49 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 74004ede5fc8..59a644dc36e2 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2642,6 +2642,19 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 	return -ETIMEDOUT;
+ }
+ 
++static int ov5640_fw_command(struct ov5640_dev *sensor, int command)
++{
++	int ret;
++
++	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, command);
++	if(ret)
++		return ret;
++
++	msleep(5);
++
++	return 0;
++}
++
+ static int ov5640_af_init(struct ov5640_dev *sensor)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
+@@ -2679,6 +2692,11 @@ static int ov5640_af_init(struct ov5640_dev *sensor)
+ 
+ 	// Set lens focus driver on
+ 	ret = ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
++	if (ret)
++		return ret;
++
++	// Set the default focus zone
++	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_ZONE_CONFIG);
+ 	if (ret)
+ 		return ret;
+ 	return ret;
+@@ -3303,35 +3321,6 @@ static int ov5640_set_framefmt(struct ov5640_dev *sensor,
+ 			      is_jpeg ? (BIT(5) | BIT(3)) : 0);
+ }
+ 
+-static int ov5640_fw_command(struct ov5640_dev *sensor, int command)
+-{
+-	u8 fw_ack;
+-	int i;
+-	int ret;
+-
+-	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_ACK, 0x01);
+-	if(ret)
+-		return ret;
+-	
+-	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, command);
+-	if(ret)
+-		return ret;
+-
+-	for (i = 0; i < 100; i++) {
+-		ret = ov5640_read_reg(sensor, OV5640_REG_FW_CMD_ACK, &fw_ack);
+-		if (ret)
+-			return ret;
+-
+-		if (fw_ack == 0){
+-			return ret;
+-		}
+-
+-		msleep(50);
+-	}
+-	return -ETIMEDOUT;
+-}
+-
+-
+ /*
+  * Sensor Controls.
+  */
+@@ -3467,26 +3456,6 @@ static int ov5640_set_ctrl_focus(struct ov5640_dev *sensor, int command)
+ 		return 0;
+ 	}
+ 
+-	if (command == OV5640_FW_CMD_RELEASE_FOCUS) {
+-		dev_dbg(&client->dev, "%s: Releasing autofocus\n",
+-			__func__);
+-		return ov5640_fw_command(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
+-	}
+-	
+-	// Restart zone config
+-	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_ZONE_CONFIG);
+-	if (ret)
+-		return ret;
+-
+-	// Set default focus zones
+-	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_DEFAULT_ZONES);
+-	if (ret)
+-		return ret;
+-
+-	dev_dbg(&client->dev, "%s: Triggering autofocus\n",
+-		__func__);
+-
+-	// Start focussing
+ 	return ov5640_fw_command(sensor, command);
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Implement-autofocus.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Implement-autofocus.patch
new file mode 100644
index 000000000000..4bc085a0ef6c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Implement-autofocus.patch
@@ -0,0 +1,395 @@
+From e9a7358ab8d83b654b757e7bd2978fb87f748cc3 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 7 Aug 2022 15:17:09 +0200
+Subject: media: ov5640: Implement autofocus
+
+The autofocus functionality needs a firmware blob loaded into the
+internal microcontroller.
+
+V4L2 doesn't have an api to control all autofocus functionality, but
+this at least makes it possible to focus on the center of the sensor.
+
+Signed-off-by: Martijn Braam <martijn@brixit.nl>
+---
+ drivers/media/i2c/ov5640.c | 279 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 279 insertions(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index ebacb17e7a7b..3e04fe83ab30 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -9,6 +9,7 @@
+ #include <linux/clkdev.h>
+ #include <linux/ctype.h>
+ #include <linux/delay.h>
++#include <linux/firmware.h>
+ #include <linux/device.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/i2c.h>
+@@ -119,6 +120,38 @@
+ #define OV5640_REG_SDE_CTRL5		0x5585
+ #define OV5640_REG_AVG_READOUT		0x56a1
+ 
++/* autofocus registers */
++
++#define OV5640_REG_SYS_RESET00		0x3000
++#define OV5640_REG_SYS_RESET01		0x3001
++#define OV5640_REG_SYS_CLOCK_ENABLE00	0x3004
++#define OV5640_REG_SYS_CLOCK_ENABLE01	0x3005
++
++#define OV5640_REG_FW_CMD_MAIN		0x3022
++#define OV5640_REG_FW_CMD_ACK		0x3023
++#define OV5640_REG_FW_CMD_PARA0		0x3024
++#define OV5640_REG_FW_CMD_PARA1		0x3025
++#define OV5640_REG_FW_CMD_PARA2		0x3026
++#define OV5640_REG_FW_CMD_PARA3		0x3027
++#define OV5640_REG_FW_CMD_PARA4		0x3028
++#define OV5640_REG_FW_STATUS		0x3029
++
++#define OV5640_REG_VCM_CONTROL4		0x3606
++#define OV5640_REG_FIRMWARE_BASE	0x8000
++
++#define OV5640_FW_STATUS_S_FIRMWARE	0x7f
++#define OV5640_FW_STATUS_S_STARTUP	0x7e
++#define OV5640_FW_STATUS_S_IDLE		0x70
++#define OV5640_FW_STATUS_S_FOCUSING	0x00
++#define OV5640_FW_STATUS_S_FOCUSED	0x10
++
++#define OV5640_FW_CMD_TRIGGER_FOCUS	0x03
++#define OV5640_FW_CMD_CONTINUOUS_FOCUS	0x04
++#define OV5640_FW_CMD_GET_FOCUS_RESULT	0x07
++#define OV5640_FW_CMD_RELEASE_FOCUS	0x08
++#define OV5640_FW_CMD_ZONE_CONFIG	0x12
++#define OV5640_FW_CMD_DEFAULT_ZONES	0x80
++
+ enum ov5640_mode_id {
+ 	OV5640_MODE_QQVGA_160_120 = 0,
+ 	OV5640_MODE_QCIF_176_144,
+@@ -423,6 +456,12 @@ struct ov5640_ctrls {
+ 		struct v4l2_ctrl *auto_gain;
+ 		struct v4l2_ctrl *gain;
+ 	};
++	struct {
++		struct v4l2_ctrl *focus_auto;
++		struct v4l2_ctrl *af_start;
++		struct v4l2_ctrl *af_stop;
++		struct v4l2_ctrl *af_status;
++	};
+ 	struct v4l2_ctrl *brightness;
+ 	struct v4l2_ctrl *light_freq;
+ 	struct v4l2_ctrl *saturation;
+@@ -465,6 +504,8 @@ struct ov5640_dev {
+ 
+ 	bool pending_mode_change;
+ 	bool streaming;
++
++	bool af_initialized;
+ };
+ 
+ static inline struct ov5640_dev *to_ov5640_dev(struct v4l2_subdev *sd)
+@@ -2493,6 +2534,118 @@ static void ov5640_powerup_sequence(struct ov5640_dev *sensor)
+ 			 OV5640_REG_SYS_CTRL0_SW_PWDN);
+ }
+ 
++static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
++					const struct firmware *fw)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	const u8 *data = (const u8 *)fw->data;
++	u8 fw_status;
++	int i;
++	int ret;
++
++	// Putting MCU in reset state
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
++	if (ret)
++		return ret;
++
++	// Write firmware
++	for (i = 0; i < fw->size / sizeof(u8); i++)
++		ov5640_write_reg(sensor,
++				OV5640_REG_FIRMWARE_BASE + i, 
++				data[i]);
++
++	// Reset MCU state
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_ACK, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA0, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA1, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA2, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA3, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA4, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_STATUS, 0x7f);
++
++	// Start AF MCU
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x00);
++	if (ret)
++		return ret;
++
++	dev_info(&client->dev, "firmware upload success\n");
++
++	// Wait for firmware to be ready
++	for (i = 0; i < 5; i++) {
++		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
++		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
++			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
++			return ret;
++		}
++		msleep(50);
++	}
++	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x, retrying...\n", fw_status);
++
++	// Putting MCU in reset state
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
++	if (ret)
++		return ret;
++	// Start AF MCU
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x00);
++	if (ret)
++		return ret;
++	// Wait for firmware to be ready
++	for (i = 0; i < 5; i++) {
++		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
++		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
++			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
++			return ret;
++		}
++		msleep(50);
++	}
++	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x\n", fw_status);
++	return -ETIMEDOUT;
++}
++
++static int ov5640_af_init(struct ov5640_dev *sensor)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	const char* fwname = "ov5640_af.bin";
++	const struct firmware *fw;
++	int ret;
++
++	if (sensor->af_initialized) {
++		return 0;
++	}
++
++	if (firmware_request_nowarn(&fw, fwname, &client->dev) == 0) {
++		ret = ov5640_copy_fw_to_device(sensor, fw);
++		if (ret == 0)
++			sensor->af_initialized = 1;
++	} else {
++		dev_warn(&client->dev, "%s: no autofocus firmware available (%s)\n",
++			__func__, fwname);
++		ret = -1;
++	}
++	release_firmware(fw);
++
++	if (ret)
++		return ret;
++
++	// Enable AF systems
++	ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_CLOCK_ENABLE00,
++			     (BIT(6) | BIT(5)), (BIT(6) | BIT(5)));
++	if (ret)
++		return ret;
++	ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_CLOCK_ENABLE01,
++			     BIT(6), BIT(6));
++	if (ret)
++		return ret;
++
++	// Set lens focus driver on
++	ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
++	if (ret)
++		return ret;
++
++	return ret;
++}
++
+ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
+@@ -2514,8 +2667,11 @@ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ 		goto xclk_off;
+ 	}
+ 
++	sensor->af_initialized = 0;
++
+ 	ov5640_powerup_sequence(sensor);
+ 
++
+ 	ret = ov5640_init_slave_id(sensor);
+ 	if (ret)
+ 		goto power_off;
+@@ -3109,6 +3265,35 @@ static int ov5640_set_framefmt(struct ov5640_dev *sensor,
+ 			      is_jpeg ? (BIT(5) | BIT(3)) : 0);
+ }
+ 
++static int ov5640_fw_command(struct ov5640_dev *sensor, int command)
++{
++	u8 fw_ack;
++	int i;
++	int ret;
++
++	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_ACK, 0x01);
++	if(ret)
++		return ret;
++	
++	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, command);
++	if(ret)
++		return ret;
++
++	for (i = 0; i < 100; i++) {
++		ret = ov5640_read_reg(sensor, OV5640_REG_FW_CMD_ACK, &fw_ack);
++		if (ret)
++			return ret;
++
++		if (fw_ack == 0){
++			return ret;
++		}
++
++		msleep(50);
++	}
++	return -ETIMEDOUT;
++}
++
++
+ /*
+  * Sensor Controls.
+  */
+@@ -3225,6 +3410,41 @@ static int ov5640_set_ctrl_exposure(struct ov5640_dev *sensor,
+ 	return ret;
+ }
+ 
++static int ov5640_set_ctrl_focus(struct ov5640_dev *sensor, int command)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	int ret;
++
++	ret = ov5640_af_init(sensor);
++	if (ret) {
++		dev_err(&client->dev, "%s: no autofocus firmware loaded\n",
++			__func__);
++		return 0;
++	}
++
++	if (command == OV5640_FW_CMD_RELEASE_FOCUS) {
++		dev_dbg(&client->dev, "%s: Releasing autofocus\n",
++			__func__);
++		return ov5640_fw_command(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
++	}
++	
++	// Restart zone config
++	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_ZONE_CONFIG);
++	if (ret)
++		return ret;
++
++	// Set default focus zones
++	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_DEFAULT_ZONES);
++	if (ret)
++		return ret;
++
++	dev_dbg(&client->dev, "%s: Triggering autofocus\n",
++		__func__);
++
++	// Start focussing
++	return ov5640_fw_command(sensor, command);
++}
++
+ static int ov5640_set_ctrl_gain(struct ov5640_dev *sensor, bool auto_gain)
+ {
+ 	struct ov5640_ctrls *ctrls = &sensor->ctrls;
+@@ -3340,6 +3560,32 @@ static int ov5640_set_ctrl_vblank(struct ov5640_dev *sensor, int value)
+ 				  mode->height + value);
+ }
+ 
++static int ov5640_get_af_status(struct ov5640_dev *sensor)
++{
++	u8 fw_status;
++	int ret;
++
++	ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
++	if (ret)
++		return ret;
++
++	switch (fw_status) {
++		case OV5640_FW_STATUS_S_FIRMWARE:
++		case OV5640_FW_STATUS_S_STARTUP:
++			return V4L2_AUTO_FOCUS_STATUS_FAILED;
++			break;
++		case OV5640_FW_STATUS_S_IDLE:
++			return V4L2_AUTO_FOCUS_STATUS_IDLE;
++			break;
++		case OV5640_FW_STATUS_S_FOCUSED:
++			return V4L2_AUTO_FOCUS_STATUS_REACHED;
++			break;
++		default:
++			return V4L2_AUTO_FOCUS_STATUS_BUSY;
++			break;
++	}
++}
++
+ static int ov5640_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
+ {
+ 	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
+@@ -3364,6 +3610,12 @@ static int ov5640_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
+ 			return val;
+ 		sensor->ctrls.exposure->val = val;
+ 		break;
++	case V4L2_CID_FOCUS_AUTO:
++		val = ov5640_get_af_status(sensor);
++		if (val < 0)
++			return val;
++		sensor->ctrls.af_status->val = val;
++		break;
+ 	}
+ 
+ 	pm_runtime_mark_last_busy(&sensor->i2c_client->dev);
+@@ -3413,6 +3665,18 @@ static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl)
+ 	case V4L2_CID_AUTO_WHITE_BALANCE:
+ 		ret = ov5640_set_ctrl_white_balance(sensor, ctrl->val);
+ 		break;
++	case V4L2_CID_FOCUS_AUTO:
++		if (ctrl->val)
++			ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_CONTINUOUS_FOCUS);
++		else
++			ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
++		break;
++	case V4L2_CID_AUTO_FOCUS_START:
++		ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_TRIGGER_FOCUS);
++		break;
++	case V4L2_CID_AUTO_FOCUS_STOP:
++		ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
++		break;
+ 	case V4L2_CID_HUE:
+ 		ret = ov5640_set_ctrl_hue(sensor, ctrl->val);
+ 		break;
+@@ -3513,6 +3777,20 @@ static int ov5640_init_controls(struct ov5640_dev *sensor)
+ 	ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
+ 					0, 1023, 1, 0);
+ 
++	/* Autofocus */
++	ctrls->focus_auto = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_AUTO,
++					    0, 1, 1, 0);
++	ctrls->af_start = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_START,
++					    0, 1, 1, 0);
++	ctrls->af_stop = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_STOP,
++					   0, 1, 1, 0);
++	ctrls->af_status = v4l2_ctrl_new_std(hdl, ops,
++					     V4L2_CID_AUTO_FOCUS_STATUS, 0,
++					     (V4L2_AUTO_FOCUS_STATUS_BUSY |
++					      V4L2_AUTO_FOCUS_STATUS_REACHED |
++					      V4L2_AUTO_FOCUS_STATUS_FAILED),
++					     0, V4L2_AUTO_FOCUS_STATUS_IDLE);
++
+ 	ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
+ 					      0, 255, 1, 64);
+ 	ctrls->hue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HUE,
+@@ -3559,6 +3837,7 @@ static int ov5640_init_controls(struct ov5640_dev *sensor)
+ 	v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false);
+ 	v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true);
+ 	v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true);
++	v4l2_ctrl_cluster(4, &ctrls->focus_auto);
+ 
+ 	sensor->sd.ctrl_handler = hdl;
+ 	return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Improve-error-reporting.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Improve-error-reporting.patch
new file mode 100644
index 000000000000..900fda1c3e5b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Improve-error-reporting.patch
@@ -0,0 +1,43 @@
+From 7993b25db1bc7a7b712445a0cf2b7a34aeb9e104 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 22 Oct 2021 19:52:49 +0200
+Subject: media: ov5640: Improve error reporting
+
+Some probe errors are currently not reported. Report them properly.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index da6a23e3d585..ebacb17e7a7b 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -3939,8 +3939,10 @@ static int ov5640_probe(struct i2c_client *client)
+ 		return ret;
+ 
+ 	ret = ov5640_get_regulators(sensor);
+-	if (ret)
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to get regulators\n");
+ 		goto entity_cleanup;
++	}
+ 
+ 	mutex_init(&sensor->lock);
+ 
+@@ -3949,8 +3951,10 @@ static int ov5640_probe(struct i2c_client *client)
+ 		goto entity_cleanup;
+ 
+ 	ret = v4l2_async_register_subdev_sensor(&sensor->sd);
+-	if (ret)
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to register sensor\n");
+ 		goto free_ctrls;
++	}
+ 
+ 	pm_runtime_enable(dev);
+ 	pm_runtime_set_autosuspend_delay(dev, 1000);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Improve-firmware-load-time.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Improve-firmware-load-time.patch
new file mode 100644
index 000000000000..c353473042e0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Improve-firmware-load-time.patch
@@ -0,0 +1,177 @@
+From a524b0843ef0caa8eae2bbe7a7a815dc450acc31 Mon Sep 17 00:00:00 2001
+From: Benjamin Schaaf <ben.schaaf@gmail.com>
+Date: Mon, 22 Nov 2021 23:38:26 +1100
+Subject: media: ov5640: Improve firmware load time
+
+Downloading the firmware can be done in groups to minimize i2c packets.
+The firmware status is set practically immediately upon successfully
+loading it, so there's no need for a long timeout or retry. The
+firmware can also not be loaded when the sensor isn't powered on, so
+don't bother trying.
+---
+ drivers/media/i2c/ov5640.c | 97 ++++++++++++++++++++++++++++----------
+ 1 file changed, 71 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 3e04fe83ab30..74004ede5fc8 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -1232,6 +1232,8 @@ static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val)
+ 	msg.buf = buf;
+ 	msg.len = sizeof(buf);
+ 
++	dev_dbg(&client->dev, "[wr %04x] <= %d\n", reg, val);
++
+ 	ret = i2c_transfer(client->adapter, &msg, 1);
+ 	if (ret < 0) {
+ 		dev_err(&client->dev, "%s: error: reg=%x, val=%x\n",
+@@ -1242,6 +1244,42 @@ static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val)
+ 	return 0;
+ }
+ 
++static int ov5640_write_regs(struct ov5640_dev *sensor, u16 reg,
++			     const u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg;
++	u8 buf[254 + 2];
++	int ret;
++
++	if (data_size > sizeof(buf) - 2) {
++		v4l2_err(&sensor->sd, "%s: oversized transfer (size=%d)\n",
++			 __func__, data_size);
++		return -EINVAL;
++	}
++
++	buf[0] = reg >> 8;
++	buf[1] = reg & 0xff;
++	memcpy(buf + 2, data, data_size);
++
++	msg.addr = client->addr;
++	msg.flags = client->flags;
++	msg.buf = buf;
++	msg.len = data_size + 2;
++
++	dev_dbg(&client->dev, "[wr %04x] <= %*ph\n", (u32)reg, data_size, data);
++
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: reg=%x, data=%*ph\n",
++			 __func__, ret, (u32)reg, data_size, data);
++		return ret;
++	}
++
++	return 0;
++}
++
+ static int ov5640_read_reg(struct ov5640_dev *sensor, u16 reg, u8 *val)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
+@@ -2542,6 +2580,7 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 	u8 fw_status;
+ 	int i;
+ 	int ret;
++	int num_groups, group_size = 254;
+ 
+ 	// Putting MCU in reset state
+ 	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
+@@ -2549,10 +2588,24 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 		return ret;
+ 
+ 	// Write firmware
+-	for (i = 0; i < fw->size / sizeof(u8); i++)
+-		ov5640_write_reg(sensor,
+-				OV5640_REG_FIRMWARE_BASE + i, 
+-				data[i]);
++	num_groups = fw->size / group_size;
++	for (i = 0; i < num_groups; i++) {
++		ret = ov5640_write_regs(sensor,
++					OV5640_REG_FIRMWARE_BASE + i * group_size,
++					data + i * group_size,
++					group_size);
++		if (ret)
++			return ret;
++	}
++
++	if (i * group_size < fw->size) {
++		ret = ov5640_write_regs(sensor,
++					OV5640_REG_FIRMWARE_BASE + i * group_size,
++					data + i * group_size,
++					fw->size - i * group_size);
++		if (ret)
++			return ret;
++	}
+ 
+ 	// Reset MCU state
+ 	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, 0x00);
+@@ -2574,31 +2627,17 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 	// Wait for firmware to be ready
+ 	for (i = 0; i < 5; i++) {
+ 		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
+-		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
+-			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
++		if (ret) {
+ 			return ret;
+ 		}
+-		msleep(50);
+-	}
+-	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x, retrying...\n", fw_status);
+ 
+-	// Putting MCU in reset state
+-	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
+-	if (ret)
+-		return ret;
+-	// Start AF MCU
+-	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x00);
+-	if (ret)
+-		return ret;
+-	// Wait for firmware to be ready
+-	for (i = 0; i < 5; i++) {
+-		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
+ 		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
+-			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
+-			return ret;
++			dev_info(&client->dev, "fw started after %d ms\n", i * 5);
++			return 0;
+ 		}
+-		msleep(50);
++		msleep(5);
+ 	}
++
+ 	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x\n", fw_status);
+ 	return -ETIMEDOUT;
+ }
+@@ -2639,10 +2678,9 @@ static int ov5640_af_init(struct ov5640_dev *sensor)
+ 		return ret;
+ 
+ 	// Set lens focus driver on
+-	ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
++	ret = ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
+ 	if (ret)
+ 		return ret;
+-
+ 	return ret;
+ }
+ 
+@@ -3415,9 +3453,16 @@ static int ov5640_set_ctrl_focus(struct ov5640_dev *sensor, int command)
+ 	struct i2c_client *client = sensor->i2c_client;
+ 	int ret;
+ 
++	// Don't attempt to do focus if the embedded controller is powered down
++	if (!sensor->streaming) {
++		dev_err(&client->dev, "%s: can't set focus when not powered\n",
++			__func__);
++		return 0;
++	}
++
+ 	ret = ov5640_af_init(sensor);
+ 	if (ret) {
+-		dev_err(&client->dev, "%s: no autofocus firmware loaded\n",
++		dev_err(&client->dev, "%s: autofocus firmware load failed\n",
+ 			__func__);
+ 		return 0;
+ 	}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
new file mode 100644
index 000000000000..258f4452c419
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
@@ -0,0 +1,29 @@
+From 8d1431ea57bcec61a40d3e205e789e7161eaee1b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 26 Jan 2020 00:19:40 +0100
+Subject: media: ov5640: Sleep after poweroff to ensure next poweron is not too
+ early
+
+It's easy to use v4l2 userspace api in such a way that user can trigger
+a brownout on the sensor instead of a proper powerdown and powerup.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index d19f6edae9fd..87129127ced3 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2534,6 +2534,7 @@ static void ov5640_set_power_off(struct ov5640_dev *sensor)
+ 	ov5640_power(sensor, false);
+ 	regulator_bulk_disable(OV5640_NUM_SUPPLIES, sensor->supplies);
+ 	clk_disable_unprepare(sensor->xclk);
++	msleep(100);
+ }
+ 
+ static int ov5640_set_power_mipi(struct ov5640_dev *sensor, bool on)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-set-default-ae-target-lower.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-set-default-ae-target-lower.patch
new file mode 100644
index 000000000000..e0c8eb198de2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-set-default-ae-target-lower.patch
@@ -0,0 +1,27 @@
+From 842afacbce96f6d0c447437a467689611bade67b Mon Sep 17 00:00:00 2001
+From: Martijn Braam <martijn@brixit.nl>
+Date: Wed, 7 Oct 2020 17:33:43 +0200
+Subject: media: ov5640: set default ae target lower
+
+The OV5640 tries to overexpose all photos by about 1 stop. This makes
+the exposure target one stop lower.
+---
+ drivers/media/i2c/ov5640.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 1b8344b226b0..da6a23e3d585 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -3874,7 +3874,7 @@ static int ov5640_probe(struct i2c_client *client)
+ 	sensor->current_link_freq =
+ 		ov5640_csi2_link_freqs[OV5640_DEFAULT_LINK_FREQ];
+ 
+-	sensor->ae_target = 52;
++	sensor->ae_target = 28;
+ 
+ 	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev),
+ 						  NULL);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
new file mode 100644
index 000000000000..39a2a2c75cf2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
@@ -0,0 +1,31 @@
+From 2b29ad6a67076c6bb1d1ee9b5d1eb071103b8c19 Mon Sep 17 00:00:00 2001
+From: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+Date: Mon, 14 Aug 2023 13:25:07 +0300
+Subject: media: ov5640: use pm_runtime_force_suspend/resume for system suspend
+
+If system was suspended while camera sensor was used, data and
+interrupts were still coming from sensor and that caused unstable
+system. Sometimes system hanged during a resume. Use
+pm_runtime_force_* helpers in order to support system suspend.
+
+Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+---
+ drivers/media/i2c/ov5640.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 1b132ee43c81..83e8a06506e9 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -4284,6 +4284,8 @@ static void ov5640_remove(struct i2c_client *client)
+ }
+ 
+ static const struct dev_pm_ops ov5640_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
+ 	SET_RUNTIME_PM_OPS(ov5640_sensor_suspend, ov5640_sensor_resume, NULL)
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
new file mode 100644
index 000000000000..e8e2d2c6d9ee
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
@@ -0,0 +1,29 @@
+From 1335cb6e2936879cef1c8cdaf2d8c1ef7d15a686 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 24 Apr 2024 00:00:31 +0200
+Subject: media: ov5648: Fix call to pm_runtime_set_suspended
+
+It should be done when RPM is disabled.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5648.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/i2c/ov5648.c b/drivers/media/i2c/ov5648.c
+index 4b86d2631bd1..c691e235388a 100644
+--- a/drivers/media/i2c/ov5648.c
++++ b/drivers/media/i2c/ov5648.c
+@@ -2566,8 +2566,8 @@ static int ov5648_probe(struct i2c_client *client)
+ 
+ 	/* Runtime PM */
+ 
+-	pm_runtime_enable(sensor->dev);
+ 	pm_runtime_set_suspended(sensor->dev);
++	pm_runtime_enable(sensor->dev);
+ 
+ 	/* V4L2 subdev register */
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-rkisp1-Adapt-to-different-SoCs-having-different-size-limi.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-rkisp1-Adapt-to-different-SoCs-having-different-size-limi.patch
new file mode 100644
index 000000000000..646571d0ab30
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-rkisp1-Adapt-to-different-SoCs-having-different-size-limi.patch
@@ -0,0 +1,167 @@
+From 1aed1147a4bc99a6cda80978f4043061f86abe00 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 15 Mar 2024 23:37:01 +0100
+Subject: media: rkisp1: Adapt to different SoCs having different size limits
+
+- RK3399 has input/output limit of main path 4416 x 3312
+- PX30 has input/output limit of main path 3264 x 2448
+- i.MX8MP has input/output limit of main path 4096 x 3072
+
+Use rkisp1_info struct to encode the limits.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+
+# Conflicts:
+#	drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+---
+ drivers/media/platform/rockchip/rkisp1/rkisp1-common.h  | 6 ++++--
+ drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c     | 5 +++--
+ drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c     | 6 ++++++
+ drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c     | 9 +++++----
+ drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c | 4 ++--
+ 5 files changed, 20 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+index 26573f6ae575..b4c958b93629 100644
+--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
++++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+@@ -34,8 +34,6 @@ struct regmap;
+ #define RKISP1_ISP_SD_SINK			BIT(1)
+ 
+ /* min and max values for the widths and heights of the entities */
+-#define RKISP1_ISP_MAX_WIDTH			4032
+-#define RKISP1_ISP_MAX_HEIGHT			3024
+ #define RKISP1_ISP_MIN_WIDTH			32
+ #define RKISP1_ISP_MIN_HEIGHT			32
+ 
+@@ -140,6 +138,8 @@ enum rkisp1_feature {
+  * @isr_size: number of entries in the @isrs array
+  * @isp_ver: ISP version
+  * @features: bitmask of rkisp1_feature features implemented by the ISP
++ * @max_width: maximum input frame width
++ * @max_height: maximum input frame height
+  *
+  * This structure contains information about the ISP specific to a particular
+  * ISP model, version, or integration in a particular SoC.
+@@ -151,6 +151,8 @@ struct rkisp1_info {
+ 	unsigned int isr_size;
+ 	enum rkisp1_cif_isp_version isp_ver;
+ 	unsigned int features;
++	unsigned int max_width;
++	unsigned int max_height;
+ };
+ 
+ /*
+diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c
+index 4202642e0523..841e58c20f7f 100644
+--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c
++++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c
+@@ -307,6 +307,7 @@ static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd,
+ 			      struct v4l2_subdev_state *sd_state,
+ 			      struct v4l2_subdev_format *fmt)
+ {
++	struct rkisp1_csi *csi = to_rkisp1_csi(sd);
+ 	const struct rkisp1_mbus_info *mbus_info;
+ 	struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
+ 
+@@ -326,10 +327,10 @@ static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd,
+ 
+ 	sink_fmt->width = clamp_t(u32, fmt->format.width,
+ 				  RKISP1_ISP_MIN_WIDTH,
+-				  RKISP1_ISP_MAX_WIDTH);
++				  csi->rkisp1->info->max_width);
+ 	sink_fmt->height = clamp_t(u32, fmt->format.height,
+ 				   RKISP1_ISP_MIN_HEIGHT,
+-				   RKISP1_ISP_MAX_HEIGHT);
++				   csi->rkisp1->info->max_height);
+ 
+ 	fmt->format = *sink_fmt;
+ 
+diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+index bb0202386c70..0535ce57e862 100644
+--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
++++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+@@ -510,6 +510,8 @@ static const struct rkisp1_info px30_isp_info = {
+ 	.features = RKISP1_FEATURE_MIPI_CSI2
+ 		  | RKISP1_FEATURE_SELF_PATH
+ 		  | RKISP1_FEATURE_DUAL_CROP,
++	.max_width = 3264,
++	.max_height = 2448,
+ };
+ 
+ static const char * const rk3399_isp_clks[] = {
+@@ -531,6 +533,8 @@ static const struct rkisp1_info rk3399_isp_info = {
+ 	.features = RKISP1_FEATURE_MIPI_CSI2
+ 		  | RKISP1_FEATURE_SELF_PATH
+ 		  | RKISP1_FEATURE_DUAL_CROP,
++	.max_width = 4416,
++	.max_height = 3312,
+ };
+ 
+ static const char * const imx8mp_isp_clks[] = {
+@@ -551,6 +555,8 @@ static const struct rkisp1_info imx8mp_isp_info = {
+ 	.isp_ver = RKISP1_V_IMX8MP,
+ 	.features = RKISP1_FEATURE_MAIN_STRIDE
+ 		  | RKISP1_FEATURE_DMA_34BIT,
++	.max_width = 4096,
++	.max_height = 3072,
+ };
+ 
+ static const struct of_device_id rkisp1_of_match[] = {
+diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
+index e45a213baf49..f787a7e91e3e 100644
+--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
++++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
+@@ -517,6 +517,7 @@ static int rkisp1_isp_enum_frame_size(struct v4l2_subdev *sd,
+ 				      struct v4l2_subdev_state *sd_state,
+ 				      struct v4l2_subdev_frame_size_enum *fse)
+ {
++	struct rkisp1_isp *isp = to_rkisp1_isp(sd);
+ 	const struct rkisp1_mbus_info *mbus_info;
+ 
+ 	if (fse->pad == RKISP1_ISP_PAD_SINK_PARAMS ||
+@@ -539,9 +540,9 @@ static int rkisp1_isp_enum_frame_size(struct v4l2_subdev *sd,
+ 		return -EINVAL;
+ 
+ 	fse->min_width = RKISP1_ISP_MIN_WIDTH;
+-	fse->max_width = RKISP1_ISP_MAX_WIDTH;
++	fse->max_width = isp->rkisp1->info->max_width;
+ 	fse->min_height = RKISP1_ISP_MIN_HEIGHT;
+-	fse->max_height = RKISP1_ISP_MAX_HEIGHT;
++	fse->max_height = isp->rkisp1->info->max_height;
+ 
+ 	return 0;
+ }
+@@ -772,10 +773,10 @@ static void rkisp1_isp_set_sink_fmt(struct rkisp1_isp *isp,
+ 
+ 	sink_fmt->width = clamp_t(u32, format->width,
+ 				  RKISP1_ISP_MIN_WIDTH,
+-				  RKISP1_ISP_MAX_WIDTH);
++				  isp->rkisp1->info->max_width);
+ 	sink_fmt->height = clamp_t(u32, format->height,
+ 				   RKISP1_ISP_MIN_HEIGHT,
+-				   RKISP1_ISP_MAX_HEIGHT);
++				   isp->rkisp1->info->max_height);
+ 
+ 	/*
+ 	 * Adjust the color space fields. Accept any color primaries and
+diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
+index 6f3931ca5b51..e22cc2db24cf 100644
+--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
++++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
+@@ -494,10 +494,10 @@ static void rkisp1_rsz_set_sink_fmt(struct rkisp1_resizer *rsz,
+ 
+ 	sink_fmt->width = clamp_t(u32, format->width,
+ 				  RKISP1_ISP_MIN_WIDTH,
+-				  RKISP1_ISP_MAX_WIDTH);
++				  rsz->rkisp1->info->max_width);
+ 	sink_fmt->height = clamp_t(u32, format->height,
+ 				   RKISP1_ISP_MIN_HEIGHT,
+-				   RKISP1_ISP_MAX_HEIGHT);
++				   rsz->rkisp1->info->max_height);
+ 
+ 	/*
+ 	 * Adjust the color space fields. Accept any color primaries and
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
new file mode 100644
index 000000000000..073d6c21a9e2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
@@ -0,0 +1,166 @@
+From 48b64aa659c5d85c406654f3faae0f3ee9668071 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 6 Jan 2023 11:25:09 +0100
+Subject: media: sun6i-csi: Add multicamera support for parallel bus
+
+Multiple cameras may be connected to parallel bus eg. in a tablet.
+Allow to register multiple parallel bus subdevices and switch between
+them by enabling/disabling media graph links.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.c        | 51 +++++++++++--------
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.h        |  4 +-
+ 2 files changed, 33 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+index 92290876a8b3..0ea1fae7352e 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+@@ -207,12 +207,12 @@ static void sun6i_csi_bridge_disable(struct sun6i_csi_device *csi_dev)
+ 
+ static void
+ sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev,
+-				    struct v4l2_subdev_state *state)
++				    struct v4l2_subdev_state *state,
++				    struct sun6i_csi_bridge_source *source)
+ {
+ 	struct device *dev = csi_dev->dev;
+ 	struct regmap *regmap = csi_dev->regmap;
+-	struct v4l2_fwnode_endpoint *endpoint =
+-		&csi_dev->bridge.source_parallel.endpoint;
++	struct v4l2_fwnode_endpoint *endpoint = &source->endpoint;
+ 	unsigned char bus_width = endpoint->bus.parallel.bus_width;
+ 	unsigned int flags = endpoint->bus.parallel.flags;
+ 	const struct v4l2_mbus_framefmt *sink_format;
+@@ -377,10 +377,8 @@ static void sun6i_csi_bridge_configure(struct sun6i_csi_device *csi_dev,
+ 				       struct sun6i_csi_bridge_source *source,
+ 				       struct v4l2_subdev_state *state)
+ {
+-	struct sun6i_csi_bridge *bridge = &csi_dev->bridge;
+-
+-	if (source == &bridge->source_parallel)
+-		sun6i_csi_bridge_configure_parallel(csi_dev, state);
++	if (source->endpoint.bus_type == V4L2_MBUS_PARALLEL)
++		sun6i_csi_bridge_configure_parallel(csi_dev, state, source);
+ 	else
+ 		sun6i_csi_bridge_configure_mipi_csi2(csi_dev, state);
+ 
+@@ -396,11 +394,11 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 	struct media_pad *local_pad = &bridge->pads[SUN6I_CSI_BRIDGE_PAD_SINK];
+ 	bool capture_streaming = csi_dev->capture.state.streaming;
+ 	struct device *dev = csi_dev->dev;
+-	struct sun6i_csi_bridge_source *source;
++	struct sun6i_csi_bridge_source *source = NULL;
+ 	struct v4l2_subdev *source_subdev;
+ 	struct media_pad *remote_pad;
+ 	struct v4l2_subdev_state *state;
+-	int ret;
++	int ret, i;
+ 
+ 	/* Source */
+ 
+@@ -413,10 +411,20 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 
+ 	source_subdev = media_entity_to_v4l2_subdev(remote_pad->entity);
+ 
+-	if (source_subdev == bridge->source_parallel.subdev)
+-		source = &bridge->source_parallel;
+-	else
++	if (source_subdev == bridge->source_mipi_csi2.subdev) {
+ 		source = &bridge->source_mipi_csi2;
++	} else {
++		for (i = 0; i < SUN6I_CSI_SOURCE_PARALLEL_MAX; i++) {
++			if (source_subdev == bridge->source_parallel[i].subdev) {
++				source = &bridge->source_parallel[i];
++				break;
++			}
++		}
++	}
++	if (!source) {
++		dev_err(dev, "bridge source not found\n");
++		return -ENODEV;
++	}
+ 
+ 	if (!on) {
+ 		v4l2_subdev_call(source_subdev, video, s_stream, 0);
+@@ -647,10 +655,10 @@ sun6i_csi_bridge_notifier_bound(struct v4l2_async_notifier *notifier,
+ 
+ 	switch (source->endpoint.base.port) {
+ 	case SUN6I_CSI_PORT_PARALLEL:
+-		enabled = true;
++		enabled = source->endpoint.base.id == 0;
+ 		break;
+ 	case SUN6I_CSI_PORT_MIPI_CSI2:
+-		enabled = !bridge->source_parallel.expected;
++		enabled = !bridge->source_parallel[0].expected;
+ 		break;
+ 	default:
+ 		return -EINVAL;
+@@ -696,7 +704,7 @@ sun6i_csi_bridge_notifier_ops = {
+ 
+ static int sun6i_csi_bridge_source_setup(struct sun6i_csi_device *csi_dev,
+ 					 struct sun6i_csi_bridge_source *source,
+-					 u32 port,
++					 u32 port, u32 ep,
+ 					 enum v4l2_mbus_type *bus_types)
+ {
+ 	struct device *dev = csi_dev->dev;
+@@ -706,7 +714,7 @@ static int sun6i_csi_bridge_source_setup(struct sun6i_csi_device *csi_dev,
+ 	struct fwnode_handle *handle;
+ 	int ret;
+ 
+-	handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), port, 0, 0);
++	handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), port, ep, 0);
+ 	if (!handle)
+ 		return -ENODEV;
+ 
+@@ -765,7 +773,7 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 		V4L2_MBUS_BT656,
+ 		V4L2_MBUS_INVALID
+ 	};
+-	int ret;
++	int ret, i;
+ 
+ 	/* V4L2 Subdev */
+ 
+@@ -817,11 +825,12 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 		v4l2_async_nf_init(notifier, v4l2_dev);
+ 	notifier->ops = &sun6i_csi_bridge_notifier_ops;
+ 
+-	sun6i_csi_bridge_source_setup(csi_dev, &bridge->source_parallel,
+-				      SUN6I_CSI_PORT_PARALLEL,
+-				      parallel_mbus_types);
++	for (i = 0; i < SUN6I_CSI_SOURCE_PARALLEL_MAX; i++)
++		sun6i_csi_bridge_source_setup(csi_dev, &bridge->source_parallel[i],
++					      SUN6I_CSI_PORT_PARALLEL, i,
++					      parallel_mbus_types);
+ 	sun6i_csi_bridge_source_setup(csi_dev, &bridge->source_mipi_csi2,
+-				      SUN6I_CSI_PORT_MIPI_CSI2, NULL);
++				      SUN6I_CSI_PORT_MIPI_CSI2, 0, NULL);
+ 
+ 	ret = v4l2_async_nf_register(notifier);
+ 	if (ret) {
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+index a5b0a6f064dd..e755b67a2db3 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+@@ -38,12 +38,14 @@ struct sun6i_csi_bridge_async_subdev {
+ 	struct sun6i_csi_bridge_source	*source;
+ };
+ 
++#define SUN6I_CSI_SOURCE_PARALLEL_MAX 2
++
+ struct sun6i_csi_bridge {
+ 	struct v4l2_subdev		subdev;
+ 	struct v4l2_async_notifier	notifier;
+ 	struct media_pad		pads[2];
+ 
+-	struct sun6i_csi_bridge_source	source_parallel;
++	struct sun6i_csi_bridge_source	source_parallel[SUN6I_CSI_SOURCE_PARALLEL_MAX];
+ 	struct sun6i_csi_bridge_source	source_mipi_csi2;
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
new file mode 100644
index 000000000000..cae82c4d3233
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
@@ -0,0 +1,82 @@
+From cb1e915e38c17e29ca810539aee98c46b184e16b Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Tue, 3 Jan 2023 18:52:04 +0000
+Subject: media: sun6i-csi: add V4L2_CAP_IO_MC capability
+
+Advertise the V4L2_CAP_IO_MC flag and update
+sun6i_csi_capture_enum_fmt to work with this capability.
+
+With the capability adverstised, the VIDIOC_ENUM_FMT ioctl
+implementation is updated to enumerate pixel formats depending
+on the supplied mbus_code.  If the code is 0, all formats are
+enumerated, if not, only pixel formats that match with the supplied
+mbus_code are enumeratd.
+
+Signed-off-by: Adam Pigg <adam@piggz.co.uk>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 37 +++++++++++++++++--
+ 1 file changed, 34 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index 510f4597a18e..371fe49753a4 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -722,13 +722,43 @@ static int sun6i_csi_capture_enum_fmt(struct file *file, void *private,
+ 				      struct v4l2_fmtdesc *fmtdesc)
+ {
+ 	u32 index = fmtdesc->index;
++	unsigned int i;
+ 
+ 	if (index >= ARRAY_SIZE(sun6i_csi_capture_formats))
+ 		return -EINVAL;
+ 
+-	fmtdesc->pixelformat = sun6i_csi_capture_formats[index].pixelformat;
++	for (i = 0; i < ARRAY_SIZE(sun6i_csi_capture_formats); i++) {
++		const struct sun6i_csi_capture_format *format =
++			&sun6i_csi_capture_formats[i];
+ 
+-	return 0;
++		/*
++		 * If a media bus code is specified, only consider formats that
++		 * match it.
++		 */
++		if (fmtdesc->mbus_code) {
++			unsigned int j;
++
++			if (!format->mbus_codes)
++				continue;
++
++			for (j = 0; format->mbus_codes[j]; j++) {
++				if (fmtdesc->mbus_code == format->mbus_codes[j])
++					break;
++			}
++
++			if (!format->mbus_codes[j])
++				continue;
++		}
++
++		if (index == 0) {
++			fmtdesc->pixelformat = format->pixelformat;
++			return 0;
++		}
++
++		index--;
++	}
++
++	return -EINVAL;
+ }
+ 
+ static int sun6i_csi_capture_g_fmt(struct file *file, void *private,
+@@ -1034,7 +1064,8 @@ int sun6i_csi_capture_setup(struct sun6i_csi_device *csi_dev)
+ 
+ 	strscpy(video_dev->name, SUN6I_CSI_CAPTURE_NAME,
+ 		sizeof(video_dev->name));
+-	video_dev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++	video_dev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING
++				| V4L2_CAP_IO_MC;
+ 	video_dev->vfl_dir = VFL_DIR_RX;
+ 	video_dev->release = video_device_release_empty;
+ 	video_dev->fops = &sun6i_csi_capture_fops;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
new file mode 100644
index 000000000000..0263aa530e24
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
@@ -0,0 +1,128 @@
+From 1a0bd0966feae6f8a9313ad04a32528cb40b74cb Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Date: Wed, 4 Jan 2023 12:29:56 +0200
+Subject: media: sun6i-csi: capture: Use subdev operation to access bridge
+ format
+
+Replace the sun6i_csi_bridge helper functions sun6i_csi_bridge_format()
+and sun6i_csi_bridge_dimensions() that access the bridge fields from the
+capture side with usage of the subdev .get_fmt() operation. This
+decouples the bridge and capture side better by using abstractions
+provided by the V4L2 subdev API, and prepares for usage of the subdev
+active state in the bridge.
+
+The sun6i_csi_bridge_dimensions() helper is now unused and is removed.
+The sun6i_csi_bridge_format() helper will be removed in a subsequent
+change.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit e728c6bbead7a10d9ffd1139e416e1199b5837a6)
+---
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.c        | 13 ++---------
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.h        |  7 ------
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 23 ++++++++++++-------
+ 3 files changed, 17 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+index d006d9dd0170..2303e5d2baee 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+@@ -15,17 +15,8 @@
+ 
+ /* Helpers */
+ 
+-void sun6i_csi_bridge_dimensions(struct sun6i_csi_device *csi_dev,
+-				 unsigned int *width, unsigned int *height)
+-{
+-	if (width)
+-		*width = csi_dev->bridge.mbus_format.width;
+-	if (height)
+-		*height = csi_dev->bridge.mbus_format.height;
+-}
+-
+-void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
+-			     u32 *mbus_code, u32 *field)
++static void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
++				    u32 *mbus_code, u32 *field)
+ {
+ 	if (mbus_code)
+ 		*mbus_code = csi_dev->bridge.mbus_format.code;
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+index 44653b38f722..722b633b7893 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+@@ -49,13 +49,6 @@ struct sun6i_csi_bridge {
+ 	struct sun6i_csi_bridge_source	source_mipi_csi2;
+ };
+ 
+-/* Helpers */
+-
+-void sun6i_csi_bridge_dimensions(struct sun6i_csi_device *csi_dev,
+-				 unsigned int *width, unsigned int *height);
+-void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
+-			     u32 *mbus_code, u32 *field);
+-
+ /* Format */
+ 
+ const struct sun6i_csi_bridge_format *
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index 14c0dc827c52..b26dc8bf55b0 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -893,11 +893,14 @@ static int sun6i_csi_capture_link_validate(struct media_link *link)
+ 	const struct sun6i_csi_capture_format *capture_format;
+ 	const struct sun6i_csi_bridge_format *bridge_format;
+ 	unsigned int capture_width, capture_height;
+-	unsigned int bridge_width, bridge_height;
+ 	const struct v4l2_format_info *format_info;
+ 	u32 pixelformat, capture_field;
+-	u32 mbus_code, bridge_field;
++	struct v4l2_subdev_format fmt = {
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++		.pad = SUN6I_CSI_BRIDGE_PAD_SOURCE,
++	};
+ 	bool match;
++	int ret;
+ 
+ 	sun6i_csi_capture_dimensions(csi_dev, &capture_width, &capture_height);
+ 
+@@ -906,18 +909,21 @@ static int sun6i_csi_capture_link_validate(struct media_link *link)
+ 	if (WARN_ON(!capture_format))
+ 		return -EINVAL;
+ 
+-	sun6i_csi_bridge_dimensions(csi_dev, &bridge_width, &bridge_height);
++	ret = v4l2_subdev_call_state_active(&csi_dev->bridge.subdev, pad,
++					    get_fmt, &fmt);
++	if (ret)
++		return ret;
+ 
+-	sun6i_csi_bridge_format(csi_dev, &mbus_code, &bridge_field);
+-	bridge_format = sun6i_csi_bridge_format_find(mbus_code);
++	bridge_format = sun6i_csi_bridge_format_find(fmt.format.code);
+ 	if (WARN_ON(!bridge_format))
+ 		return -EINVAL;
+ 
+ 	/* No cropping/scaling is supported. */
+-	if (capture_width != bridge_width || capture_height != bridge_height) {
++	if (capture_width != fmt.format.width ||
++	    capture_height != fmt.format.height) {
+ 		v4l2_err(v4l2_dev,
+ 			 "invalid input/output dimensions: %ux%u/%ux%u\n",
+-			 bridge_width, bridge_height, capture_width,
++			 fmt.format.width, fmt.format.height, capture_width,
+ 			 capture_height);
+ 		return -EINVAL;
+ 	}
+@@ -949,7 +955,8 @@ static int sun6i_csi_capture_link_validate(struct media_link *link)
+ 	/* With raw input mode, we need a 1:1 match between input and output. */
+ 	if (bridge_format->input_format == SUN6I_CSI_INPUT_FMT_RAW ||
+ 	    capture_format->input_format_raw) {
+-		match = sun6i_csi_capture_format_match(pixelformat, mbus_code);
++		match = sun6i_csi_capture_format_match(pixelformat,
++						       fmt.format.code);
+ 		if (!match)
+ 			goto invalid;
+ 	}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
new file mode 100644
index 000000000000..2c1c2dc5ad40
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
@@ -0,0 +1,65 @@
+From 850d69497913562d51c721b6e703ce011cf13257 Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Wed, 4 Jan 2023 21:18:51 +0000
+Subject: media: sun6i-csi: implement vidioc_enum_framesizes
+
+Create sun6i_csi_capture_enum_framesizes which defines the min
+and max frame sizes.
+
+As per the specification of vidioc_enum_framesizes, if the supplied
+index is >0 or no valid formats are found for the supplied format,
+return -EINVAL.
+
+Set the type to V4L2_FRMSIZE_TYPE_CONTINUOUS and set the min and max
+width and height from the approriate macros, 32x32 - 4800x4800.
+
+Signed-off-by: Adam Pigg <adam@piggz.co.uk>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index 371fe49753a4..d65151216efa 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -795,6 +795,29 @@ static int sun6i_csi_capture_try_fmt(struct file *file, void *private,
+ 	return 0;
+ }
+ 
++static int sun6i_csi_capture_enum_framesizes(struct file *file, void *fh,
++					  struct v4l2_frmsizeenum *fsize)
++{
++	const struct sun6i_csi_capture_format *format;
++
++	if (fsize->index > 0)
++		return -EINVAL;
++
++	format = sun6i_csi_capture_format_find(fsize->pixel_format);
++	if (!format)
++		return -EINVAL;
++
++	fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
++	fsize->stepwise.min_width = SUN6I_CSI_CAPTURE_WIDTH_MIN;
++	fsize->stepwise.max_width = SUN6I_CSI_CAPTURE_WIDTH_MAX;
++	fsize->stepwise.min_height = SUN6I_CSI_CAPTURE_HEIGHT_MIN;
++	fsize->stepwise.max_height = SUN6I_CSI_CAPTURE_HEIGHT_MAX;
++	fsize->stepwise.step_width = 1;
++	fsize->stepwise.step_height = 1;
++
++	return 0;
++}
++
+ static int sun6i_csi_capture_enum_input(struct file *file, void *private,
+ 					struct v4l2_input *input)
+ {
+@@ -831,6 +854,7 @@ static const struct v4l2_ioctl_ops sun6i_csi_capture_ioctl_ops = {
+ 	.vidioc_g_fmt_vid_cap		= sun6i_csi_capture_g_fmt,
+ 	.vidioc_s_fmt_vid_cap		= sun6i_csi_capture_s_fmt,
+ 	.vidioc_try_fmt_vid_cap		= sun6i_csi_capture_try_fmt,
++	.vidioc_enum_framesizes		= sun6i_csi_capture_enum_framesizes,
+ 
+ 	.vidioc_enum_input		= sun6i_csi_capture_enum_input,
+ 	.vidioc_g_input			= sun6i_csi_capture_g_input,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
new file mode 100644
index 000000000000..e9eec5082f1f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
@@ -0,0 +1,431 @@
+From d7653fd5b5da1defc658862ca04e131ff4c70b61 Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Tue, 3 Jan 2023 18:20:21 +0000
+Subject: media: sun6i-csi: merge sun6i_csi_formats and sun6i_csi_formats_match
+
+Information about media bus formats and pixel formats supported by the
+driver is split between the sun6i_csi_capture_formats and
+sun6i_csi_capture_format_matches arrays. This makes it difficult to map
+media bus formats to pixel formats when enumerating the supported pixel
+formats by walking the sun6i_csi_capture_formats array. To prepare for
+support of media bus format support in sun6i_csi_capture_enum_fmt(),
+merge the two arrays toegether.
+
+To do this, sun6i_csi_capture_formats gains a const u32* to store the
+mbus_codes previously from sun6i_csi_capture_format_matches and
+sun6i_csi_capture_format_match is updated to iterate through this to
+find the mbus code while iterating sun6i_csi_capture_formats.
+
+In addition to merging the arrys, to produce semi-planar or multi-planar
+YUV formats, related mbus codes have been added to the *NV* and related
+pixel formats.
+
+Signed-off-by: Adam Pigg <adam@piggz.co.uk>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 211 +++++++++---------
+ .../sunxi/sun6i-csi/sun6i_csi_capture.h       |   6 +-
+ 2 files changed, 102 insertions(+), 115 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index b26dc8bf55b0..510f4597a18e 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -22,6 +22,8 @@
+ 
+ /* Helpers */
+ 
++#define SUN6I_BUS_FMTS(fmt...) (const u32[]) {fmt, 0}
++
+ void sun6i_csi_capture_dimensions(struct sun6i_csi_device *csi_dev,
+ 				  unsigned int *width, unsigned int *height)
+ {
+@@ -49,72 +51,86 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.pixelformat		= V4L2_PIX_FMT_SBGGR8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SBGGR8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGBRG8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGBRG8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGRBG8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGRBG8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SRGGB8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SRGGB8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SBGGR10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SBGGR10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGBRG10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGBRG10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGRBG10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGRBG10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SRGGB10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SRGGB10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SBGGR12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SBGGR12_1X12),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGBRG12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGBRG12_1X12),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGRBG12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGRBG12_1X12),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SRGGB12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SRGGB12_1X12),
+ 	},
+ 	/* RGB */
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_RGB565,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RGB565,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RGB565,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_RGB565_2X8_LE),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_RGB565X,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RGB565,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RGB565,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_RGB565_2X8_BE),
+ 	},
+ 	/* YUV422 */
+ 	{
+@@ -123,6 +139,8 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_YUYV8_2X8,
++							 MEDIA_BUS_FMT_YUYV8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YVYU,
+@@ -130,6 +148,8 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_YVYU8_2X8,
++							 MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_UYVY,
+@@ -137,6 +157,8 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++							 MEDIA_BUS_FMT_UYVY8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_VYUY,
+@@ -144,57 +166,124 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_VYUY8_2X8,
++							 MEDIA_BUS_FMT_VYUY8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV16,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422SP,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV61,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422SP,
+ 		.input_yuv_seq_invert	= true,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YUV422P,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422P,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422P,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	/* YUV420 */
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV12_16L16,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420MB,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420MB,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420SP,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV21,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420SP,
+ 		.input_yuv_seq_invert	= true,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YUV420,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420P,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420P,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YVU420,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420P,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420P,
+ 		.input_yuv_seq_invert	= true,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	/* Compressed */
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_JPEG,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_JPEG_1X8),
+ 	},
+ };
+ 
+@@ -210,118 +299,20 @@ struct sun6i_csi_capture_format *sun6i_csi_capture_format_find(u32 pixelformat)
+ 	return NULL;
+ }
+ 
+-/* RAW formats need an exact match between pixel and mbus formats. */
+-static const
+-struct sun6i_csi_capture_format_match sun6i_csi_capture_format_matches[] = {
+-	/* YUV420 */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YUYV,
+-		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YUYV,
+-		.mbus_code	= MEDIA_BUS_FMT_YUYV8_1X16,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YVYU,
+-		.mbus_code	= MEDIA_BUS_FMT_YVYU8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YVYU,
+-		.mbus_code	= MEDIA_BUS_FMT_YVYU8_1X16,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_UYVY,
+-		.mbus_code	= MEDIA_BUS_FMT_UYVY8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_UYVY,
+-		.mbus_code	= MEDIA_BUS_FMT_UYVY8_1X16,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_VYUY,
+-		.mbus_code	= MEDIA_BUS_FMT_VYUY8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_VYUY,
+-		.mbus_code	= MEDIA_BUS_FMT_VYUY8_1X16,
+-	},
+-	/* RGB */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_RGB565,
+-		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_LE,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_RGB565X,
+-		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_BE,
+-	},
+-	/* Bayer */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SBGGR8,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGBRG8,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGRBG8,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SRGGB8,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SBGGR10,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGBRG10,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGRBG10,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SRGGB10,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SBGGR12,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGBRG12,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGRBG12,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SRGGB12,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
+-	},
+-	/* Compressed */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_JPEG,
+-		.mbus_code	= MEDIA_BUS_FMT_JPEG_1X8,
+-	},
+-};
+-
+ static bool sun6i_csi_capture_format_match(u32 pixelformat, u32 mbus_code)
+ {
+-	unsigned int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(sun6i_csi_capture_format_matches); i++) {
+-		const struct sun6i_csi_capture_format_match *match =
+-			&sun6i_csi_capture_format_matches[i];
+-
+-		if (match->pixelformat == pixelformat &&
+-		    match->mbus_code == mbus_code)
+-			return true;
++	unsigned int i, j;
++
++	for (i = 0; i < ARRAY_SIZE(sun6i_csi_capture_formats); i++) {
++		const struct sun6i_csi_capture_format *format =
++			&sun6i_csi_capture_formats[i];
++
++		if (format->pixelformat == pixelformat) {
++			for (j = 0; format->mbus_codes[j]; j++) {
++				if (mbus_code == format->mbus_codes[j])
++					return true;
++			}
++		}
+ 	}
+ 
+ 	return false;
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h
+index 3ee5ccefbd10..0484942834e3 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h
+@@ -27,11 +27,7 @@ struct sun6i_csi_capture_format {
+ 	bool	input_yuv_seq_invert;
+ 	bool	input_format_raw;
+ 	u32	hsize_len_factor;
+-};
+-
+-struct sun6i_csi_capture_format_match {
+-	u32	pixelformat;
+-	u32	mbus_code;
++	const u32 *mbus_codes;
+ };
+ 
+ #undef current
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
new file mode 100644
index 000000000000..15eacc62b28a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
@@ -0,0 +1,346 @@
+From c44fa62a66f6ded9daaf4e0418939c1e27fba508 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 13 Jan 2024 21:24:24 +0100
+Subject: media: sun6i-csi: subdev: Use subdev active state to store active
+ format
+
+The sun6i_csi_bridge structure stores the active format as a struct
+v4l2_mbus_framefmt instance. Now that the V4L2 subdev core supports
+managing the active state, use it to replace the manually-managed
+format. This simplifies the implementation of the subdev operations by
+removing the need for a custom .get_fmt() handler.
+
+The subdev state now needs to be passed manually from the .s_stream()
+operation to internal functions that need to access the format. As a
+result, the sun6i_csi_bridge_format() helper function is now unused and
+can be dropped.
+
+The .init_state() and .set_fmt() operations also need to be updated
+accordingly. As a result, .set_fmt() now correctly propagates the format
+from the sink pad to the source pad.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit b14038f024ad84473ed79f3baecc2da9ca16d9a5)
+---
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.c        | 149 +++++++++---------
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.h        |   2 -
+ 2 files changed, 73 insertions(+), 78 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+index 2303e5d2baee..92290876a8b3 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+@@ -13,17 +13,6 @@
+ #include "sun6i_csi_bridge.h"
+ #include "sun6i_csi_reg.h"
+ 
+-/* Helpers */
+-
+-static void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
+-				    u32 *mbus_code, u32 *field)
+-{
+-	if (mbus_code)
+-		*mbus_code = csi_dev->bridge.mbus_format.code;
+-	if (field)
+-		*field = csi_dev->bridge.mbus_format.field;
+-}
+-
+ /* Format */
+ 
+ static const struct sun6i_csi_bridge_format sun6i_csi_bridge_formats[] = {
+@@ -217,7 +206,8 @@ static void sun6i_csi_bridge_disable(struct sun6i_csi_device *csi_dev)
+ }
+ 
+ static void
+-sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev)
++sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev,
++				    struct v4l2_subdev_state *state)
+ {
+ 	struct device *dev = csi_dev->dev;
+ 	struct regmap *regmap = csi_dev->regmap;
+@@ -225,14 +215,14 @@ sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev)
+ 		&csi_dev->bridge.source_parallel.endpoint;
+ 	unsigned char bus_width = endpoint->bus.parallel.bus_width;
+ 	unsigned int flags = endpoint->bus.parallel.flags;
+-	u32 field;
++	const struct v4l2_mbus_framefmt *sink_format;
+ 	u32 value = SUN6I_CSI_IF_CFG_IF_CSI;
+ 
+-	sun6i_csi_bridge_format(csi_dev, NULL, &field);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
+ 
+-	if (field == V4L2_FIELD_INTERLACED ||
+-	    field == V4L2_FIELD_INTERLACED_TB ||
+-	    field == V4L2_FIELD_INTERLACED_BT)
++	if (sink_format->field == V4L2_FIELD_INTERLACED ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_TB ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_BT)
+ 		value |= SUN6I_CSI_IF_CFG_SRC_TYPE_INTERLACED |
+ 			 SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(1) |
+ 			 SUN6I_CSI_IF_CFG_FIELD_DT_FIELD_VSYNC;
+@@ -308,17 +298,18 @@ sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev)
+ }
+ 
+ static void
+-sun6i_csi_bridge_configure_mipi_csi2(struct sun6i_csi_device *csi_dev)
++sun6i_csi_bridge_configure_mipi_csi2(struct sun6i_csi_device *csi_dev,
++				     struct v4l2_subdev_state *state)
+ {
++	const struct v4l2_mbus_framefmt *sink_format;
+ 	struct regmap *regmap = csi_dev->regmap;
+ 	u32 value = SUN6I_CSI_IF_CFG_IF_MIPI;
+-	u32 field;
+ 
+-	sun6i_csi_bridge_format(csi_dev, NULL, &field);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
+ 
+-	if (field == V4L2_FIELD_INTERLACED ||
+-	    field == V4L2_FIELD_INTERLACED_TB ||
+-	    field == V4L2_FIELD_INTERLACED_BT)
++	if (sink_format->field == V4L2_FIELD_INTERLACED ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_TB ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_BT)
+ 		value |= SUN6I_CSI_IF_CFG_SRC_TYPE_INTERLACED;
+ 	else
+ 		value |= SUN6I_CSI_IF_CFG_SRC_TYPE_PROGRESSIVE;
+@@ -326,19 +317,20 @@ sun6i_csi_bridge_configure_mipi_csi2(struct sun6i_csi_device *csi_dev)
+ 	regmap_write(regmap, SUN6I_CSI_IF_CFG_REG, value);
+ }
+ 
+-static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
++static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev,
++					      struct v4l2_subdev_state *state)
+ {
+ 	struct regmap *regmap = csi_dev->regmap;
+ 	bool capture_streaming = csi_dev->capture.state.streaming;
+ 	const struct sun6i_csi_bridge_format *bridge_format;
+ 	const struct sun6i_csi_capture_format *capture_format;
+-	u32 mbus_code, field, pixelformat;
++	const struct v4l2_mbus_framefmt *sink_format;
++	u32 pixelformat;
+ 	u8 input_format, input_yuv_seq, output_format;
+ 	u32 value = 0;
+ 
+-	sun6i_csi_bridge_format(csi_dev, &mbus_code, &field);
+-
+-	bridge_format = sun6i_csi_bridge_format_find(mbus_code);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
++	bridge_format = sun6i_csi_bridge_format_find(sink_format->code);
+ 	if (WARN_ON(!bridge_format))
+ 		return;
+ 
+@@ -358,9 +350,9 @@ static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
+ 		if (capture_format->input_yuv_seq_invert)
+ 			input_yuv_seq = bridge_format->input_yuv_seq_invert;
+ 
+-		if (field == V4L2_FIELD_INTERLACED ||
+-		    field == V4L2_FIELD_INTERLACED_TB ||
+-		    field == V4L2_FIELD_INTERLACED_BT)
++		if (sink_format->field == V4L2_FIELD_INTERLACED ||
++		    sink_format->field == V4L2_FIELD_INTERLACED_TB ||
++		    sink_format->field == V4L2_FIELD_INTERLACED_BT)
+ 			output_format = capture_format->output_format_field;
+ 		else
+ 			output_format = capture_format->output_format_frame;
+@@ -371,9 +363,9 @@ static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
+ 	value |= SUN6I_CSI_CH_CFG_INPUT_FMT(input_format);
+ 	value |= SUN6I_CSI_CH_CFG_INPUT_YUV_SEQ(input_yuv_seq);
+ 
+-	if (field == V4L2_FIELD_TOP)
++	if (sink_format->field == V4L2_FIELD_TOP)
+ 		value |= SUN6I_CSI_CH_CFG_FIELD_SEL_FIELD0;
+-	else if (field == V4L2_FIELD_BOTTOM)
++	else if (sink_format->field == V4L2_FIELD_BOTTOM)
+ 		value |= SUN6I_CSI_CH_CFG_FIELD_SEL_FIELD1;
+ 	else
+ 		value |= SUN6I_CSI_CH_CFG_FIELD_SEL_EITHER;
+@@ -382,16 +374,17 @@ static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
+ }
+ 
+ static void sun6i_csi_bridge_configure(struct sun6i_csi_device *csi_dev,
+-				       struct sun6i_csi_bridge_source *source)
++				       struct sun6i_csi_bridge_source *source,
++				       struct v4l2_subdev_state *state)
+ {
+ 	struct sun6i_csi_bridge *bridge = &csi_dev->bridge;
+ 
+ 	if (source == &bridge->source_parallel)
+-		sun6i_csi_bridge_configure_parallel(csi_dev);
++		sun6i_csi_bridge_configure_parallel(csi_dev, state);
+ 	else
+-		sun6i_csi_bridge_configure_mipi_csi2(csi_dev);
++		sun6i_csi_bridge_configure_mipi_csi2(csi_dev, state);
+ 
+-	sun6i_csi_bridge_configure_format(csi_dev);
++	sun6i_csi_bridge_configure_format(csi_dev, state);
+ }
+ 
+ /* V4L2 Subdev */
+@@ -406,6 +399,7 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 	struct sun6i_csi_bridge_source *source;
+ 	struct v4l2_subdev *source_subdev;
+ 	struct media_pad *remote_pad;
++	struct v4l2_subdev_state *state;
+ 	int ret;
+ 
+ 	/* Source */
+@@ -441,8 +435,9 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 	sun6i_csi_bridge_irq_clear(csi_dev);
+ 
+ 	/* Configure */
+-
+-	sun6i_csi_bridge_configure(csi_dev, source);
++	state = v4l2_subdev_lock_and_get_active_state(subdev);
++	sun6i_csi_bridge_configure(csi_dev, source, state);
++	v4l2_subdev_unlock_state(state);
+ 
+ 	if (capture_streaming)
+ 		sun6i_csi_capture_configure(csi_dev);
+@@ -495,13 +490,9 @@ sun6i_csi_bridge_mbus_format_prepare(struct v4l2_mbus_framefmt *mbus_format)
+ static int sun6i_csi_bridge_init_state(struct v4l2_subdev *subdev,
+ 				       struct v4l2_subdev_state *state)
+ {
+-	struct sun6i_csi_device *csi_dev = v4l2_get_subdevdata(subdev);
+ 	unsigned int pad = SUN6I_CSI_BRIDGE_PAD_SINK;
+ 	struct v4l2_mbus_framefmt *mbus_format =
+ 		v4l2_subdev_state_get_format(state, pad);
+-	struct mutex *lock = &csi_dev->bridge.lock;
+-
+-	mutex_lock(lock);
+ 
+ 	mbus_format->code = sun6i_csi_bridge_formats[0].mbus_code;
+ 	mbus_format->width = 1280;
+@@ -509,8 +500,6 @@ static int sun6i_csi_bridge_init_state(struct v4l2_subdev *subdev,
+ 
+ 	sun6i_csi_bridge_mbus_format_prepare(mbus_format);
+ 
+-	mutex_unlock(lock);
+-
+ 	return 0;
+ }
+ 
+@@ -527,53 +516,60 @@ sun6i_csi_bridge_enum_mbus_code(struct v4l2_subdev *subdev,
+ 	return 0;
+ }
+ 
+-static int sun6i_csi_bridge_get_fmt(struct v4l2_subdev *subdev,
+-				    struct v4l2_subdev_state *state,
+-				    struct v4l2_subdev_format *format)
+-{
+-	struct sun6i_csi_device *csi_dev = v4l2_get_subdevdata(subdev);
+-	struct v4l2_mbus_framefmt *mbus_format = &format->format;
+-	struct mutex *lock = &csi_dev->bridge.lock;
+-
+-	mutex_lock(lock);
+-
+-	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
+-		*mbus_format = *v4l2_subdev_state_get_format(state,
+-							     format->pad);
+-	else
+-		*mbus_format = csi_dev->bridge.mbus_format;
+-
+-	mutex_unlock(lock);
+-
+-	return 0;
+-}
+-
+ static int sun6i_csi_bridge_set_fmt(struct v4l2_subdev *subdev,
+ 				    struct v4l2_subdev_state *state,
+ 				    struct v4l2_subdev_format *format)
+ {
+-	struct sun6i_csi_device *csi_dev = v4l2_get_subdevdata(subdev);
+-	struct v4l2_mbus_framefmt *mbus_format = &format->format;
+-	struct mutex *lock = &csi_dev->bridge.lock;
++	struct v4l2_mbus_framefmt *sink_format;
++	struct v4l2_mbus_framefmt *src_format;
+ 
+-	mutex_lock(lock);
++	/*
++	 * As the source format can't change independently of the sink format,
++	 * a set operation on the source is a get.
++	 */
++	if (format->pad == SUN6I_CSI_BRIDGE_PAD_SOURCE)
++		return v4l2_subdev_get_fmt(subdev, state, format);
+ 
+-	sun6i_csi_bridge_mbus_format_prepare(mbus_format);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
+ 
++	/*
+ 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
+ 		*v4l2_subdev_state_get_format(state, format->pad) =
+ 			*mbus_format;
++	*/
++
++	if (!sun6i_csi_bridge_format_find(format->format.code))
++		sink_format->code = sun6i_csi_bridge_formats[0].mbus_code;
+ 	else
+-		csi_dev->bridge.mbus_format = *mbus_format;
++		sink_format->code = format->format.code;
++
++	sink_format->width = format->format.width;
++	sink_format->height = format->format.height;
++
++	/* Accept any colorspace as the CSI bridge isn't colorspace-aware. */
++	sink_format->colorspace = format->format.colorspace;
++	sink_format->xfer_func = format->format.xfer_func;
++	sink_format->ycbcr_enc = format->format.ycbcr_enc;
++	sink_format->quantization = format->format.quantization;
++
++	sink_format->field = V4L2_FIELD_NONE;
+ 
+-	mutex_unlock(lock);
++	format->format = *sink_format;
++
++	/*
++	 * Propagate the format to the source pad. The CSI bridge can't
++	 * transcode, the format on the source pad always matches the sink pad
++	 * exactly.
++	 */
++	src_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SOURCE);
++	*src_format = *sink_format;
+ 
+ 	return 0;
+ }
+ 
+ static const struct v4l2_subdev_pad_ops sun6i_csi_bridge_pad_ops = {
+ 	.enum_mbus_code	= sun6i_csi_bridge_enum_mbus_code,
+-	.get_fmt	= sun6i_csi_bridge_get_fmt,
++	.get_fmt	= v4l2_subdev_get_fmt,
+ 	.set_fmt	= sun6i_csi_bridge_set_fmt,
+ };
+ 
+@@ -771,8 +767,6 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 	};
+ 	int ret;
+ 
+-	mutex_init(&bridge->lock);
+-
+ 	/* V4L2 Subdev */
+ 
+ 	v4l2_subdev_init(subdev, &sun6i_csi_bridge_subdev_ops);
+@@ -801,6 +795,9 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 		return ret;
+ 
+ 	/* V4L2 Subdev */
++	ret = v4l2_subdev_init_finalize(subdev);
++	if (ret)
++		goto error_media_entity;
+ 
+ 	if (csi_dev->isp_available)
+ 		ret = v4l2_async_register_subdev(subdev);
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+index 722b633b7893..a5b0a6f064dd 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+@@ -42,8 +42,6 @@ struct sun6i_csi_bridge {
+ 	struct v4l2_subdev		subdev;
+ 	struct v4l2_async_notifier	notifier;
+ 	struct media_pad		pads[2];
+-	struct v4l2_mbus_framefmt	mbus_format;
+-	struct mutex			lock; /* Mbus format lock. */
+ 
+ 	struct sun6i_csi_bridge_source	source_parallel;
+ 	struct sun6i_csi_bridge_source	source_mipi_csi2;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
new file mode 100644
index 000000000000..7f59d4517d2b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
@@ -0,0 +1,102 @@
+From d56de1c2c9cf643da71948af59e77dc16f2ba714 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 01:01:58 -0600
+Subject: mfd: axp20x: Add battery IRQ resources
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/mfd/axp20x.c | 36 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index d8daa593ebd5..a1b9039fbd66 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -270,6 +270,15 @@ static const struct resource axp20x_ac_power_supply_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
+ };
+ 
++static const struct resource axp20x_battery_resources[] = {
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_PLUGIN, "BATT_PLUGIN"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_REMOVAL, "BATT_REMOVAL"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_ENT_ACT_MODE, "BATT_HEALTH_DEAD"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_EXIT_ACT_MODE, "BATT_HEALTH_GOOD"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_CHARG, "BATT_CHARGING"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_CHARG_DONE, "BATT_CHARGING_DONE"),
++};
++
+ static const struct resource axp20x_pek_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
+ 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
+@@ -317,6 +326,23 @@ static const struct resource axp313a_pek_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP313A_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
+ };
+ 
++static const struct resource axp803_battery_resources[] = {
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_PLUGIN, "BATT_PLUGIN"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_REMOVAL, "BATT_REMOVAL"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ENT_ACT_MODE, "BATT_HEALTH_DEAD"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_EXIT_ACT_MODE, "BATT_HEALTH_GOOD"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_CHARG, "BATT_CHARGING"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_CHARG_DONE, "BATT_CHARGING_DONE"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_HIGH, "BATT_CHG_TEMP_HIGH"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_HIGH_END, "BATT_CHG_TEMP_HIGH_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_LOW, "BATT_CHG_TEMP_LOW"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_LOW_END, "BATT_CHG_TEMP_LOW_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_HIGH, "BATT_ACT_TEMP_HIGH"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_HIGH_END, "BATT_ACT_TEMP_HIGH_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW, "BATT_ACT_TEMP_LOW"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW_END, "BATT_ACT_TEMP_LOW_END"),
++};
++
+ static const struct resource axp803_pek_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
+@@ -857,6 +883,8 @@ static const struct mfd_cell axp20x_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp209-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp20x_battery_resources),
++		.resources	= axp20x_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-ac-power-supply",
+ 		.of_compatible	= "x-powers,axp202-ac-power-supply",
+@@ -891,6 +919,8 @@ static const struct mfd_cell axp221_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp221-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp20x_battery_resources),
++		.resources	= axp20x_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-usb-power-supply",
+ 		.of_compatible	= "x-powers,axp221-usb-power-supply",
+@@ -913,6 +943,8 @@ static const struct mfd_cell axp223_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp221-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp20x_battery_resources),
++		.resources	= axp20x_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-regulator",
+ 	}, {
+@@ -1017,6 +1049,8 @@ static const struct mfd_cell axp803_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp813-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp803_battery_resources),
++		.resources	= axp803_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-ac-power-supply",
+ 		.of_compatible	= "x-powers,axp813-ac-power-supply",
+@@ -1077,6 +1111,8 @@ static const struct mfd_cell axp813_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp813-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp803_battery_resources),
++		.resources	= axp803_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-ac-power-supply",
+ 		.of_compatible	= "x-powers,axp813-ac-power-supply",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/misc-modem-power-Power-manager-for-modems.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/misc-modem-power-Power-manager-for-modems.patch
new file mode 100644
index 000000000000..6c6cd8444e91
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/misc-modem-power-Power-manager-for-modems.patch
@@ -0,0 +1,2050 @@
+From 3df646171658219f3233ba5a1ec76e8063439e2f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 12 Nov 2017 02:10:15 +0100
+Subject: misc: modem-power: Power manager for modems
+
+This driver allows for powering/resetting devices that are otherwise
+handled by other subsytems (USB). It also has mechanismsm for polling
+from userspace on device->SoC wakeup events via GPIO.
+
+This is mostly useful for controling modems. The supported modems are:
+
+- Quectel EG25
+- ZTE MG3732
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/misc/Kconfig       |    7 +
+ drivers/misc/Makefile      |    1 +
+ drivers/misc/modem-power.c | 1992 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 2000 insertions(+)
+ create mode 100644 drivers/misc/modem-power.c
+
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index 4fb291f0bf7c..76bc725441ea 100644
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -574,6 +574,13 @@ config NSM
+ 	  To compile this driver as a module, choose M here.
+ 	  The module will be called nsm.
+ 
++config MODEM_POWER
++	tristate "Modem power/wakeup support for EG25, MG3732, etc."
++	depends on OF && SERIAL_DEV_BUS && RFKILL
++	help
++	  This driver provides support for powering up and handling
++	  wakeup signals for various modems.
++
+ source "drivers/misc/c2port/Kconfig"
+ source "drivers/misc/eeprom/Kconfig"
+ source "drivers/misc/cb710/Kconfig"
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index ea6ea5bbbc9c..3e8473e62e69 100644
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -68,3 +68,4 @@ obj-$(CONFIG_TMR_INJECT)	+= xilinx_tmr_inject.o
+ obj-$(CONFIG_TPS6594_ESM)	+= tps6594-esm.o
+ obj-$(CONFIG_TPS6594_PFSM)	+= tps6594-pfsm.o
+ obj-$(CONFIG_NSM)		+= nsm.o
++obj-$(CONFIG_MODEM_POWER)	+= modem-power.o
+diff --git a/drivers/misc/modem-power.c b/drivers/misc/modem-power.c
+new file mode 100644
+index 000000000000..36729ce00752
+--- /dev/null
++++ b/drivers/misc/modem-power.c
+@@ -0,0 +1,1992 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Modem power control driver.
++ *
++ * Ondrej Jirman <megi@xff.cz>
++ *
++ * How this works
++ * --------------
++ *
++ * The driver:
++ * - can be registered as a platform or serial device
++ * - will use gpios, regulator and (optionally) serial port to control the modem
++ * - exposes a character device to control the modem power and receive various
++ *   events
++ * - exposes sysfs interface to control modem power and wakeup
++ * - supports multiple modem types and instances
++ *
++ * Power up/power down:
++ * - may take a lot of time (eg. ~13-22s powerup, >22s powerdown)
++ * - happens on a private workqueue under a lock
++ * - may happen from shutdown hook
++ * - prevents suspend when powerup/powerdown is in progress
++ * - is serialized and there's no abort of in-progress operations
++ * - for specific power sequence see comments in the section for each
++ *   supported modem variant
++ * - the driver monitors the power status of the modem (optionally)
++ *   and tries to complete the powerdown initiated via AT command
++ * - the driver tries to detect when the modem is killswitched off
++ *   and updates the driver status to reflect that
++ *
++ * Suspend/resume:
++ * - suspend is blocked if powerup/down is in progress
++ * - modem can wakeup the host over gpio based IRQ (RI signal)
++ * - the driver will assert ap_ready after resume finishes
++ *
++ * Rfkill:
++ * - the driver implements a rfkill interface if rfkill gpio is available
++ */
++
++//#define DEBUG
++
++#include <linux/wait.h>
++#include <linux/interrupt.h>
++#include <linux/device.h>
++#include <linux/cdev.h>
++#include <linux/kfifo.h>
++#include <linux/module.h>
++#include <linux/poll.h>
++#include <linux/spinlock.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/serdev.h>
++#include <linux/rfkill.h>
++
++#define DRIVER_NAME "modem-power"
++
++enum {
++	MPWR_REQ_NONE = 0,
++	MPWR_REQ_RESET,
++	MPWR_REQ_PWDN,
++	MPWR_REQ_PWUP,
++};
++
++enum {
++	MPWR_MODE_NORMAL = 1,
++	MPWR_MODE_DUMB,
++	MPWR_MODE_FASTBOOT,
++	MPWR_MODE_ALT1,
++	MPWR_MODE_ALT2,
++};
++
++struct mpwr_dev;
++
++struct mpwr_gpio {
++	const char* name;
++	unsigned desc_off;
++	int flags;
++	bool required;
++	int irq_flags;
++	unsigned irq_off;
++};
++
++#define MPWR_GPIO_DEF(_name, _flags, _req) \
++	{ .name = #_name, \
++	  .desc_off = offsetof(struct mpwr_dev, _name##_gpio), \
++	  .flags = _flags, \
++	  .required = _req, \
++	}
++
++#define MPWR_GPIO_DEF_IRQ(_name, _flags, _req, _irq_flags) \
++	{ .name = #_name, \
++	  .desc_off = offsetof(struct mpwr_dev, _name##_gpio), \
++	  .flags = _flags, \
++	  .required = _req, \
++	  .irq_flags = _irq_flags, \
++	  .irq_off = offsetof(struct mpwr_dev, _name##_irq), \
++	}
++
++struct mpwr_variant {
++	int (*power_init)(struct mpwr_dev* mpwr);
++	int (*power_up)(struct mpwr_dev* mpwr);
++	int (*power_down)(struct mpwr_dev* mpwr);
++	int (*reset)(struct mpwr_dev* mpwr);
++	void (*recv_msg)(struct mpwr_dev *mpwr, const char *msg);
++	int (*suspend)(struct mpwr_dev *mpwr);
++	int (*resume)(struct mpwr_dev *mpwr);
++	const struct mpwr_gpio* gpios;
++	bool regulator_required;
++	bool monitor_wakeup;
++};
++
++struct mpwr_dev {
++	struct device *dev;
++	const struct mpwr_variant* variant;
++
++	wait_queue_head_t wait;
++
++	/* serdev */
++	struct serdev_device *serdev;
++	char rcvbuf[4096];
++	size_t rcvbuf_fill;
++	char msg[4096];
++        int msg_len;
++        int msg_ok;
++	//struct kfifo kfifo;
++	DECLARE_KFIFO(kfifo, unsigned char, 4096);
++
++	/* power */
++	struct regulator *regulator;
++	struct regulator *regulator_vbus;
++
++	/* outputs */
++	struct gpio_desc *enable_gpio;
++	struct gpio_desc *reset_gpio;
++	struct gpio_desc *pwrkey_gpio;
++	struct gpio_desc *sleep_gpio;
++	struct gpio_desc *dtr_gpio;
++	struct gpio_desc *host_ready_gpio;
++	struct gpio_desc *cts_gpio;
++	struct gpio_desc *rts_gpio;
++
++	/* inputs */
++	struct gpio_desc *status_gpio;
++	struct gpio_desc *wakeup_gpio;
++	int wakeup_irq;
++	bool status_pwrkey_multiplexed;
++
++	/* config */
++	struct cdev cdev;
++	dev_t major;
++
++	/* rfkill */
++	struct rfkill *rfkill;
++
++	/* powerup/dn work queue */
++	struct workqueue_struct *wq;
++	struct work_struct power_work;
++	struct work_struct finish_pdn_work;
++        struct mutex modem_lock;
++
++	// change
++	spinlock_t lock; /* protects last_request */
++	int last_request;
++	int powerup_mode;
++	ktime_t last_wakeup;
++
++	struct timer_list wd_timer;
++        struct delayed_work host_ready_work;
++
++	unsigned long flags[1];
++};
++
++enum {
++	/* modem is powered */
++	MPWR_F_POWERED,
++	MPWR_F_POWER_CHANGE_INPROGRESS,
++	MPWR_F_KILLSWITCHED,
++	/* we got a wakeup from the modem */
++	MPWR_F_GOT_WAKEUP,
++        /* serdev */
++        MPWR_F_RECEIVING_MSG,
++        /* eg25 */
++        MPWR_F_GOT_PDN,
++	/* config options */
++        MPWR_F_BLOCKED,
++	/* file */
++	MPWR_F_OPEN,
++	MPWR_F_OVERFLOW,
++};
++
++static struct class* mpwr_class;
++
++static int mpwr_serdev_at_cmd(struct mpwr_dev *mpwr, const char *msg, int timeout_ms);
++static int mpwr_serdev_at_cmd_with_retry(struct mpwr_dev *mpwr, const char *msg,
++					 int timeout_ms, int tries);
++static int mpwr_serdev_at_cmd_with_retry_ignore_timeout(struct mpwr_dev *mpwr, const char *msg,
++							int timeout_ms, int tries);
++
++// {{{ mg2723 variant
++
++static int mpwr_mg2723_power_init(struct mpwr_dev* mpwr)
++{
++	// if the device has power applied or doesn't have regulator
++	// configured (we assume it's always powered) initialize GPIO
++	// to shut it down initially
++	if (!mpwr->regulator || regulator_is_enabled(mpwr->regulator)) {
++		gpiod_set_value(mpwr->enable_gpio, 0);
++		gpiod_set_value(mpwr->reset_gpio, 1);
++	} else {
++		// device is not powered, don't drive the gpios
++		gpiod_direction_input(mpwr->enable_gpio);
++		gpiod_direction_input(mpwr->reset_gpio);
++	}
++
++	return 0;
++}
++
++static int mpwr_mg2723_power_up(struct mpwr_dev* mpwr)
++{
++	int ret;
++
++	// power up
++	if (mpwr->regulator) {
++		ret = regulator_enable(mpwr->regulator);
++		if (ret < 0) {
++			dev_err(mpwr->dev,
++				"can't enable power supply err=%d", ret);
++			return ret;
++		}
++	}
++
++	gpiod_direction_output(mpwr->enable_gpio, 1);
++	gpiod_direction_output(mpwr->reset_gpio, 1);
++	msleep(300);
++	gpiod_set_value(mpwr->reset_gpio, 0);
++
++	return 0;
++}
++
++static int mpwr_mg2723_power_down(struct mpwr_dev* mpwr)
++{
++	gpiod_set_value(mpwr->enable_gpio, 0);
++	msleep(50);
++
++	if (mpwr->regulator) {
++		regulator_disable(mpwr->regulator);
++
++		gpiod_direction_input(mpwr->enable_gpio);
++		gpiod_direction_input(mpwr->reset_gpio);
++	} else {
++		gpiod_set_value(mpwr->reset_gpio, 1);
++	}
++
++	return 0;
++}
++
++static int mpwr_mg2723_reset(struct mpwr_dev* mpwr)
++{
++	gpiod_set_value(mpwr->reset_gpio, 1);
++	msleep(300);
++	gpiod_set_value(mpwr->reset_gpio, 0);
++
++	return 0;
++}
++
++static const struct mpwr_gpio mpwr_mg2723_gpios[] = {
++	MPWR_GPIO_DEF(enable, GPIOD_IN, true),
++	MPWR_GPIO_DEF(reset, GPIOD_IN, true),
++	MPWR_GPIO_DEF_IRQ(wakeup, GPIOD_IN, true, IRQF_TRIGGER_FALLING),
++	{ },
++};
++
++static const struct mpwr_variant mpwr_mg2723_variant = {
++	.power_init = mpwr_mg2723_power_init,
++	.power_up = mpwr_mg2723_power_up,
++	.power_down = mpwr_mg2723_power_down,
++	.reset = mpwr_mg2723_reset,
++	.gpios = mpwr_mg2723_gpios,
++};
++
++// }}}
++// {{{ eg25 variant
++
++static bool mpwr_eg25_qcfg_airplanecontrol_is_ok(const char* v)
++{
++	return strstarts(v, "1,");
++}
++
++struct mpwr_eg25_qcfg {
++	const char* name;
++	const char* val;
++	bool (*is_ok)(const char* val);
++};
++
++#define EG25G_LATEST_KNOWN_FIRMWARE "EG25GGBR07A08M2G_01.002.07"
++
++static const struct mpwr_eg25_qcfg mpwr_eg25_qcfgs[] = {
++	//{ "risignaltype",       "\"respective\"", },
++	{ "risignaltype",       "\"physical\"", },
++	{ "urc/ri/ring",        "\"pulse\",1,1000,5000,\"off\",1", },
++	{ "urc/ri/smsincoming", "\"pulse\",1,1", },
++	{ "urc/ri/other",       "\"off\",1,1", },
++	{ "urc/ri/pin",         "uart_ri", },
++	{ "urc/delay",          "0", },
++
++	//{ "sleep/datactrl",     "0,300,1", },
++
++	{ "sleepind/level",     "0", },
++	{ "wakeupin/level",     "0", },
++
++	{ "ApRstLevel",		"0", },
++	{ "ModemRstLevel",	"0", },
++
++	// in EG25-G this tries to modify file in /etc (read-only)
++	// and fails
++	//{ "dbgctl",		"0", },
++
++	// we don't need AP_READY
++	{ "apready",            "0,0,500", },
++
++	{ "airplanecontrol",    "1",   mpwr_eg25_qcfg_airplanecontrol_is_ok },
++
++	// available since firmware R07A08_01.002.01.002
++	{ "fast/poweroff",	"1" },
++};
++
++static char* mpwr_serdev_get_response_value(struct mpwr_dev *mpwr,
++					    const char* prefix)
++{
++	int off;
++
++	for (off = 0; off < mpwr->msg_len; off += strlen(mpwr->msg + off) + 1)
++		if (strstarts(mpwr->msg + off, prefix))
++			return mpwr->msg + off + strlen(prefix);
++
++	return NULL;
++}
++
++static struct gpio_desc *mpwr_eg25_get_pwrkey_gpio(struct mpwr_dev *mpwr)
++{
++	if (mpwr->status_pwrkey_multiplexed)
++		return mpwr->status_gpio;
++
++	return mpwr->pwrkey_gpio;
++}
++
++/*
++ * Gpio meanings
++ * -------------
++ *
++ * enable_gpio - 1 = enables RF, 0 = disables RF
++ * sleep_gpio  - 1 = puts modem to sleep, 0 = wakes up the modem (must be 0
++ *               during poweron)
++ * reset_gpio  - accepts 150-460ms reset pulse (high __|^|__)
++ * pwrkey_gpio - accepts 100ms-650ms pulse for powerup (high __|^|__)
++ *                       650ms+ pulse for powerdown
++ *                       (initiated after pulse ends, pulse may have indefinite
++ *                        duration)
++ * status_gpio - modem power status 0 = powered  1 = unpowered
++ * wakeup_gpio - "ring indicator" output from the modem
++ * host_ready_gpio - AP_READY pin - host is ready to receive URCs
++ *
++ * (pwrkey may be multiplexed with status_gpio)
++ *
++ * Modem behavior
++ * --------------
++ *
++ * wakeup_gpio (RI):
++ * - goes high shortly after power is applied (~15ms)
++ * - goes low when RDY is sent
++ *
++ * dtr_gpio
++ * - when high, modem can sleep if requested
++ * - H->L will wake up a sleeping modem
++ * - internal pull-up
++ *
++ * ri
++ * - pulled low when there's URC
++ * - modem wakes up on URC automatically
++ *
++ * - AT+QURCCFG
++ * - AT+QINDCFG="csq",1
++ * - AT+QINDCFG="ring",1
++ * - AT+QINDCFG="smsincoming",1
++ * - AT+CGREG=0
++ * - AT+CREG=0
++ *
++ * - AT+QURCCFG="urcport","uart1"
++ */
++static int mpwr_eg25_power_up(struct mpwr_dev* mpwr)
++{
++	struct gpio_desc *pwrkey_gpio = mpwr_eg25_get_pwrkey_gpio(mpwr);
++	bool wakeup_ok, status_ok;
++	bool needs_restart = false;
++	u32 speed = 115200;
++	int ret, i, off;
++	ktime_t start;
++	int mode = mpwr->powerup_mode;
++
++	if (regulator_is_enabled(mpwr->regulator))
++		dev_warn(mpwr->dev,
++			 "regulator was already enabled during powerup");
++
++	/* Enable the modem power. */
++	ret = regulator_enable(mpwr->regulator);
++	if (ret < 0) {
++		dev_err(mpwr->dev,
++			"can't enable power supply err=%d", ret);
++		return ret;
++	}
++
++	ret = regulator_enable(mpwr->regulator_vbus);
++	if (ret < 0) {
++		dev_err(mpwr->dev,
++			"can't enable vbus power supply err=%d", ret);
++		regulator_disable(mpwr->regulator);
++		return ret;
++	}
++
++	/* Drive default gpio signals during powerup */
++	/* host_ready_gpio should be 1 during normal powerup */
++	gpiod_direction_output(mpwr->host_ready_gpio, mode != MPWR_MODE_ALT2);
++	/* #W_DISABLE must be left pulled up during modem power up
++	 * early on, because opensource bootloader uses this signal to enter
++	 * fastboot mode when it's pulled down.
++	 *
++	 * This should be 1 for normal powerup and 0 for fastboot mode with
++	 * special Biktor's firmware.
++	 */
++	gpiod_direction_output(mpwr->enable_gpio, mode != MPWR_MODE_FASTBOOT);
++	gpiod_direction_output(mpwr->sleep_gpio, 0);
++	gpiod_direction_output(mpwr->reset_gpio, 0);
++	gpiod_direction_output(pwrkey_gpio, 0);
++	/* dtr_gpio should be 0 during normal powerup */
++	gpiod_direction_output(mpwr->dtr_gpio, mode == MPWR_MODE_ALT1);
++
++	/* Wait for powerup. (30ms min. according to datasheet) */
++	msleep(50);
++
++	/* Send 200ms pwrkey pulse to initiate poweron */
++	gpiod_set_value(pwrkey_gpio, 1);
++	msleep(200);
++	gpiod_set_value(pwrkey_gpio, 0);
++
++	/* skip modem killswitch status checks in fastboot bootloader entry mode */
++	if (mode != MPWR_MODE_NORMAL)
++		goto open_serdev;
++
++	/* Switch status key to input, in case it's multiplexed with pwrkey. */
++	gpiod_direction_input(mpwr->status_gpio);
++
++	/*
++	 * Wait for status/wakeup change, assume good values, if CTS/status
++	 * signals, are not configured.
++	 */
++	status_ok = mpwr->status_gpio ? false : true;
++	wakeup_ok = mpwr->wakeup_gpio ? false : true;
++
++	/* wait up to 10s for status */
++	start = ktime_get();
++	while (ktime_ms_delta(ktime_get(), start) < 10000) {
++		if (!wakeup_ok && mpwr->wakeup_gpio && gpiod_get_value(mpwr->wakeup_gpio)) {
++			dev_info(mpwr->dev, "wakeup ok\n");
++			wakeup_ok = true;
++		}
++
++		if (!status_ok && mpwr->status_gpio && !gpiod_get_value(mpwr->status_gpio)) {
++			dev_info(mpwr->dev, "status ok\n");
++			status_ok = true;
++		}
++
++		/* modem is ready */
++		if (wakeup_ok && status_ok)
++			break;
++
++		msleep(50);
++	}
++
++	if (!wakeup_ok) {
++		dev_err(mpwr->dev, "The modem looks kill-switched\n");
++		if (!test_and_set_bit(MPWR_F_KILLSWITCHED, mpwr->flags))
++			sysfs_notify(&mpwr->dev->kobj, NULL, "killswitched");
++		goto err_shutdown_noclose;
++	}
++
++	if (!status_ok) {
++		dev_err(mpwr->dev, "The modem didn't report powerup success in time\n");
++		goto err_shutdown_noclose;
++	}
++
++	if (test_and_clear_bit(MPWR_F_KILLSWITCHED, mpwr->flags))
++		sysfs_notify(&mpwr->dev->kobj, NULL, "killswitched");
++
++open_serdev:
++	/* open serial console */
++	ret = serdev_device_open(mpwr->serdev);
++	if (ret) {
++		dev_err(mpwr->dev, "error opening serdev (%d)\n", ret);
++		goto err_shutdown_noclose;
++	}
++
++	of_property_read_u32(mpwr->dev->of_node, "current-speed", &speed);
++	serdev_device_set_baudrate(mpwr->serdev, speed);
++	serdev_device_set_flow_control(mpwr->serdev, false);
++	ret = serdev_device_set_parity(mpwr->serdev, SERDEV_PARITY_NONE);
++	if (ret) {
++		dev_err(mpwr->dev, "error setting serdev parity (%d)\n", ret);
++		goto err_shutdown;
++	}
++
++	if (mode != MPWR_MODE_NORMAL)
++		goto powered_up;
++
++	ret = mpwr_serdev_at_cmd_with_retry_ignore_timeout(mpwr, "AT&FE0", 1000, 30);
++	if (ret)
++		goto err_shutdown;
++
++	/* print firmware version */
++        ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QVERSION;+QSUBSYSVER", 1000, 15);
++        if (ret == 0 && mpwr->msg_len > 0) {
++		bool outdated = false;
++
++		dev_info(mpwr->dev, "===================================================\n");
++		for (off = 0; off < mpwr->msg_len; off += strlen(mpwr->msg + off) + 1) {
++			if (strstr(mpwr->msg + off, "Project Rev") && !strstr(mpwr->msg + off, EG25G_LATEST_KNOWN_FIRMWARE))
++				outdated = true;
++
++			dev_info(mpwr->dev, "%s\n", mpwr->msg + off);
++		}
++		dev_info(mpwr->dev, "===================================================\n");
++
++		if (outdated)
++			dev_warn(mpwr->dev, "Your modem has an outdated firmware. Latest know version is %s. Consider updating.\n", EG25G_LATEST_KNOWN_FIRMWARE);
++	}
++
++	/* print ADB key to dmesg */
++        ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QADBKEY?", 1000, 15);
++        if (ret == 0) {
++		const char *val = mpwr_serdev_get_response_value(mpwr, "+QADBKEY: ");
++		if (val)
++			dev_info(mpwr->dev, "ADB KEY is '%s' (you can use it to unlock ADB access to the modem, see https://xnux.eu/devices/feature/modem-pp.html)\n", val);
++	}
++
++        // check DAI config
++        ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QDAI?", 1000, 15);
++        if (ret == 0) {
++		const char *val = mpwr_serdev_get_response_value(mpwr, "+QDAI: ");
++		const char *needed_val = NULL;
++		char buf[128];
++
++		if (val) {
++			of_property_read_string(mpwr->dev->of_node, "quectel,qdai", &needed_val);
++
++			if (needed_val && strcmp(needed_val, val)) {
++				dev_warn(mpwr->dev, "QDAI is '%s' (changing to '%s')\n", val, needed_val);
++
++				/* update qdai */
++				snprintf(buf, sizeof buf, "AT+QDAI=%s", needed_val);
++				ret = mpwr_serdev_at_cmd(mpwr, buf, 5000);
++				if (ret == 0)
++					needs_restart = true;
++			} else {
++				dev_info(mpwr->dev, "QDAI is '%s'\n", val);
++			}
++		}
++	}
++
++	/* reset the modem, to apply QDAI config if necessary */
++	if (needs_restart) {
++		dev_info(mpwr->dev, "Restarting modem\n");
++
++		/* reboot is broken with fastboot enabled */
++		mpwr_serdev_at_cmd(mpwr, "AT+QCFG=\"fast/poweroff\",0", 5000);
++
++		ret = mpwr_serdev_at_cmd(mpwr, "AT+CFUN=1,1", 5000);
++		if (ret)
++			goto err_shutdown;
++
++		/* wait a bit before starting to probe the modem again */
++		msleep(6000);
++
++		ret = mpwr_serdev_at_cmd_with_retry_ignore_timeout(mpwr, "AT&FE0", 1000, 30);
++		if (ret)
++			goto err_shutdown;
++
++		// wait until QDAI starts succeeding (then the modem is ready
++		// to accept the following QCFGs)
++		ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QDAI?", 1000, 15);
++		if (ret)
++			goto err_shutdown;
++	}
++
++        /* check and update important QCFGs */
++        for (i = 0; i < ARRAY_SIZE(mpwr_eg25_qcfgs); i++) {
++                const char* name = mpwr_eg25_qcfgs[i].name;
++                const char* needed_val = mpwr_eg25_qcfgs[i].val;
++		bool (*is_ok)(const char* val) = mpwr_eg25_qcfgs[i].is_ok;
++		const char *val;
++                char buf[128];
++
++                snprintf(buf, sizeof buf, "AT+QCFG=\"%s\"", name);
++                ret = mpwr_serdev_at_cmd(mpwr, buf, 1000);
++                if (ret)
++			continue;
++
++                snprintf(buf, sizeof buf, "+QCFG: \"%s\",", name);
++		val = mpwr_serdev_get_response_value(mpwr, buf);
++		if (val) {
++			if (needed_val && (is_ok ? !is_ok(val) : strcmp(needed_val, val))) {
++				dev_info(mpwr->dev, "QCFG '%s' is '%s' (changing to '%s')\n", name, val, needed_val);
++
++				/* update qcfg */
++				snprintf(buf, sizeof buf, "AT+QCFG=\"%s\",%s", name, needed_val);
++				ret = mpwr_serdev_at_cmd(mpwr, buf, 1000);
++				if (ret)
++					break; /* go to next QCFG */
++			} else {
++				dev_info(mpwr->dev, "QCFG '%s' is '%s'\n", name, val);
++			}
++		}
++        }
++
++	/* setup URC port */
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QURCCFG=\"urcport\",\"all\"", 2000);
++        if (ret) {
++		dev_info(mpwr->dev, "Your modem doesn't support AT+QURCCFG=\"urcport\",\"all\", consider upgrading the firmware.\n");
++
++		ret = mpwr_serdev_at_cmd(mpwr, "AT+QURCCFG=\"urcport\",\"usbat\"", 2000);
++		if (ret)
++			dev_err(mpwr->dev, "Modem may not report URCs to the right port!\n");
++	}
++
++	/* enable the modem to go to sleep when DTR is low */
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QSCLK=1", 2000);
++        if (ret)
++		dev_err(mpwr->dev, "Modem will probably not sleep!\n");
++
++powered_up:
++	// if we're signaling some alternate boot mode via GPIO, we need to
++	// sleep here so that modem's boot script notices the gpio
++	if (mode == MPWR_MODE_ALT1 || mode == MPWR_MODE_FASTBOOT || mode == MPWR_MODE_ALT2)
++		msleep(12000);
++
++	gpiod_direction_output(mpwr->dtr_gpio, 1);
++
++	return 0;
++
++err_shutdown:
++	serdev_device_close(mpwr->serdev);
++err_shutdown_noclose:
++	dev_warn(mpwr->dev,
++		 "Forcibly cutting off power, data loss may occur.\n");
++	gpiod_direction_input(mpwr->enable_gpio);
++	gpiod_direction_input(mpwr->reset_gpio);
++	gpiod_direction_input(mpwr->sleep_gpio);
++	gpiod_direction_input(pwrkey_gpio);
++	gpiod_direction_input(mpwr->host_ready_gpio);
++	gpiod_direction_input(mpwr->dtr_gpio);
++
++	regulator_disable(mpwr->regulator_vbus);
++	regulator_disable(mpwr->regulator);
++	return -ENODEV;
++}
++
++static int mpwr_eg25_power_down_finish(struct mpwr_dev* mpwr)
++{
++	struct gpio_desc *pwrkey_gpio = mpwr_eg25_get_pwrkey_gpio(mpwr);
++	ktime_t start = ktime_get();
++	int ret;
++
++	serdev_device_close(mpwr->serdev);
++
++	/*
++	 * This function is called right after POWERED DOWN message is received.
++	 *
++	 * In case of fast/poweroff == 1, no POWERED DOWN message is sent.
++	 * Fast power off times are around 1s since the end of 800ms
++	 * POK pulse.
++	 *
++	 * When the modem powers down RI (wakeup) goes low and STATUS goes
++	 * high at the same time. Status is not connected on some boards.
++	 * RI should be inactive during poweroff, but we don't know for sure.
++	 *
++	 * Therfore:
++	 * - wait for STATUS going low
++	 * - in case that's not available wait for RI going low
++	 * - in case timings seem off, warn the user
++	 *
++	 * In addition, some boards have PWRKEY multiplexed with STATUS signal.
++	 * In that case we need to switch STATUS to output high level, as soon
++	 * as it goes low in order to prevent a power-up signal being registered
++	 * by the modem.
++	 */
++
++	if (mpwr->status_gpio) {
++		/* wait up to 30s for status going high */
++		while (ktime_ms_delta(ktime_get(), start) < 30000) {
++			if (gpiod_get_value(mpwr->status_gpio)) {
++				if (ktime_ms_delta(ktime_get(), start) < 500)
++					dev_warn(mpwr->dev,
++						 "STATUS signal is high too soon during powerdown. Modem is already off?\n");
++				goto powerdown;
++			}
++
++			msleep(20);
++		}
++
++		dev_warn(mpwr->dev,
++			 "STATUS signal didn't go high during shutdown. Modem is still on?\n");
++		goto force_powerdown;
++	} else {
++		clear_bit(MPWR_F_GOT_WAKEUP, mpwr->flags);
++
++		if (!gpiod_get_value(mpwr->wakeup_gpio)) {
++			dev_warn(mpwr->dev,
++				 "RI signal is low too soon during powerdown. Modem is already off, or spurious wakeup?\n");
++			msleep(2000);
++			goto powerdown;
++		}
++
++		ret = wait_event_timeout(mpwr->wait,
++					 test_bit(MPWR_F_GOT_WAKEUP, mpwr->flags),
++					 msecs_to_jiffies(30000));
++		if (ret <= 0) {
++			dev_warn(mpwr->dev,
++				 "RI signal didn't go low during shutdown, is modem really powering down?\n");
++			goto force_powerdown;
++		}
++
++		if (ktime_ms_delta(ktime_get(), start) < 500) {
++			dev_warn(mpwr->dev,
++				 "RI signal is low too soon during powerdown. Modem is already off, or spurious wakeup?\n");
++			msleep(2000);
++			goto powerdown;
++		}
++	}
++
++powerdown:
++	gpiod_direction_input(mpwr->enable_gpio);
++	gpiod_direction_input(mpwr->reset_gpio);
++	gpiod_direction_input(mpwr->sleep_gpio);
++	gpiod_direction_input(pwrkey_gpio);
++	gpiod_direction_input(mpwr->host_ready_gpio);
++	gpiod_direction_input(mpwr->dtr_gpio);
++
++	regulator_disable(mpwr->regulator_vbus);
++	regulator_disable(mpwr->regulator);
++
++	return 0;
++
++force_powerdown:
++	dev_warn(mpwr->dev,
++		 "Forcibly cutting off power, data loss may occur.\n");
++	goto powerdown;
++}
++
++static int mpwr_eg25_power_down(struct mpwr_dev* mpwr)
++{
++	struct gpio_desc *pwrkey_gpio = mpwr_eg25_get_pwrkey_gpio(mpwr);
++	//int ret;
++
++	/* Send 800ms pwrkey pulse to initiate powerdown. */
++	gpiod_direction_output(pwrkey_gpio, 1);
++	msleep(800);
++	gpiod_set_value(pwrkey_gpio, 0);
++
++	/* Switch status key to input, in case it's multiplexed with pwrkey. */
++	gpiod_direction_input(mpwr->status_gpio);
++
++	msleep(20);
++
++#if 0
++	// wait for POWERED DOWN message
++	clear_bit(MPWR_F_GOT_PDN, mpwr->flags);
++	ret = wait_event_timeout(mpwr->wait,
++				 test_bit(MPWR_F_GOT_PDN, mpwr->flags),
++				 msecs_to_jiffies(7000));
++	if (ret <= 0)
++		dev_warn(mpwr->dev,
++			 "POWERED DOWN message not received, is modem really powering down?\n");
++#endif
++
++	return mpwr_eg25_power_down_finish(mpwr);
++}
++
++static void mpwr_finish_pdn_work(struct work_struct *work)
++{
++	/*
++	struct mpwr_dev *mpwr = container_of(work, struct mpwr_dev, power_work);
++	unsigned long flags;
++
++	spin_lock_irqsave(&mpwr->lock, flags);
++	spin_unlock_irqrestore(&mpwr->lock, flags);
++
++	pm_stay_awake(mpwr->dev);
++
++	mutex_lock(&mpwr->modem_lock);
++
++	mutex_unlock(&mpwr->modem_lock);
++
++	pm_relax(mpwr->dev);
++	*/
++}
++
++static void mpwr_eg25_receive_msg(struct mpwr_dev *mpwr, const char *msg)
++{
++	unsigned int msg_len;
++
++	if (!strcmp(msg, "POWERED DOWN")) {
++		// system is powering down
++                set_bit(MPWR_F_GOT_PDN, mpwr->flags);
++		wake_up(&mpwr->wait);
++
++		/*
++		if (mutex_trylock(&mpwr->modem_lock)) {
++			// if no power op is in progress, this means userspace
++			// tried to shut the modem down via AT command, finish up
++			// the job
++
++			pm_stay_awake(mpwr->dev);
++
++			queue_work(mpwr->wq, &mpwr->power_work);
++			dev_warn(mpwr->dev, "userspace shut down the modem via AT command, finishing the job\n");
++			mpwr_eg25_power_down_finish(mpwr);
++			mutex_unlock(&mpwr->modem_lock);
++
++			pm_relax(mpwr->dev);
++		}
++                  */
++                return;
++	}
++
++	if (!strcmp(msg, "RDY")) {
++		// system is ready after powerup
++                return;
++	}
++
++	if (!test_bit(MPWR_F_OPEN, mpwr->flags))
++		return;
++
++	msg_len = strlen(msg);
++
++	if (msg_len + 1 > kfifo_avail(&mpwr->kfifo)) {
++		if (!test_and_set_bit(MPWR_F_OVERFLOW, mpwr->flags))
++			wake_up(&mpwr->wait);
++		return;
++	}
++
++	kfifo_in(&mpwr->kfifo, msg, msg_len);
++	kfifo_in(&mpwr->kfifo, "\n", 1);
++	wake_up(&mpwr->wait);
++}
++
++static void mpwr_host_ready_work(struct work_struct *work)
++{
++        struct mpwr_dev *mpwr = container_of(work, struct mpwr_dev, host_ready_work.work);
++	int ret;
++
++	mutex_lock(&mpwr->modem_lock);
++	gpiod_direction_output(mpwr->dtr_gpio, 0);
++
++	/*
++	 * We need to give the modem some time to wake up.
++	 */
++	msleep(5);
++
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QCFG=\"urc/cache\",0", 500);
++	if (ret)
++		dev_warn(mpwr->dev,
++			 "Failed to disable urc/cache, you may not be able to see URCs\n");
++
++	gpiod_direction_output(mpwr->dtr_gpio, 1);
++	mutex_unlock(&mpwr->modem_lock);
++
++	gpiod_direction_output(mpwr->host_ready_gpio, 1);
++}
++
++static int mpwr_eg25_suspend(struct mpwr_dev *mpwr)
++{
++	int ret;
++
++	cancel_delayed_work_sync(&mpwr->host_ready_work);
++
++	gpiod_direction_output(mpwr->host_ready_gpio, 0);
++
++	mutex_lock(&mpwr->modem_lock);
++	gpiod_direction_output(mpwr->dtr_gpio, 0);
++
++	msleep(5);
++
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QCFG=\"urc/cache\",1", 500);
++	if (ret)
++		dev_warn(mpwr->dev,
++			 "Failed to enable urc/cache, you may lose URCs during suspend\n");
++
++	gpiod_direction_output(mpwr->dtr_gpio, 1);
++	mutex_unlock(&mpwr->modem_lock);
++
++	return 0;
++}
++
++static int mpwr_eg25_resume(struct mpwr_dev *mpwr)
++{
++	//gpiod_direction_output(mpwr->dtr_gpio, 0);
++
++	// delay disabling URC cache until the whole system is hopefully resumed...
++	schedule_delayed_work(&mpwr->host_ready_work, msecs_to_jiffies(1000));
++
++	return 0;
++}
++
++static const struct mpwr_gpio mpwr_eg25_gpios[] = {
++	MPWR_GPIO_DEF(enable, GPIOD_OUT_HIGH, true),
++	MPWR_GPIO_DEF(reset, GPIOD_OUT_LOW, true),
++	MPWR_GPIO_DEF(pwrkey, GPIOD_OUT_LOW, false),
++	MPWR_GPIO_DEF(dtr, GPIOD_OUT_LOW, true),
++	MPWR_GPIO_DEF(status, GPIOD_IN, false),
++	MPWR_GPIO_DEF_IRQ(wakeup, GPIOD_IN, true,
++			  IRQF_TRIGGER_FALLING),
++
++	// XXX: not really needed...
++	MPWR_GPIO_DEF(sleep, GPIOD_OUT_LOW, false),
++	MPWR_GPIO_DEF(host_ready, GPIOD_OUT_HIGH, false),
++	MPWR_GPIO_DEF(cts, GPIOD_IN, false),
++	MPWR_GPIO_DEF(rts, GPIOD_OUT_LOW, false),
++	{ },
++};
++
++static const struct mpwr_variant mpwr_eg25_variant = {
++	.power_up = mpwr_eg25_power_up,
++	.power_down = mpwr_eg25_power_down,
++	.recv_msg = mpwr_eg25_receive_msg,
++	.suspend = mpwr_eg25_suspend,
++	.resume = mpwr_eg25_resume,
++	.gpios = mpwr_eg25_gpios,
++	.regulator_required = true,
++	.monitor_wakeup = true,
++};
++
++// }}}
++// {{{ generic helpers
++
++static void mpwr_reset(struct mpwr_dev* mpwr)
++{
++	struct device *dev = mpwr->dev;
++	int ret;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags)) {
++		dev_err(dev, "reset requested but device is not enabled");
++		return;
++	}
++
++	if (!mpwr->reset_gpio) {
++		dev_err(dev, "reset is not configured for this device");
++		return;
++	}
++
++	if (!mpwr->variant->reset) {
++		dev_err(dev, "reset requested but not implemented");
++		return;
++	}
++
++	dev_info(dev, "resetting");
++	ret = mpwr->variant->reset(mpwr);
++	if (ret) {
++		dev_err(dev, "reset failed");
++	}
++}
++
++static void mpwr_power_down(struct mpwr_dev* mpwr)
++{
++	struct device *dev = mpwr->dev;
++	ktime_t start = ktime_get();
++	int ret;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return;
++
++	if (!mpwr->variant->power_down) {
++		dev_err(dev, "power down requested but not implemented");
++		return;
++	}
++
++	dev_info(dev, "powering down");
++
++	ret = mpwr->variant->power_down(mpwr);
++	if (ret) {
++		dev_err(dev, "power down failed");
++	} else {
++		clear_bit(MPWR_F_POWERED, mpwr->flags);
++		sysfs_notify(&mpwr->dev->kobj, NULL, "powered");
++		dev_info(mpwr->dev, "powered down in %lld ms\n",
++			 ktime_ms_delta(ktime_get(), start));
++	}
++}
++
++static void mpwr_power_up(struct mpwr_dev* mpwr)
++{
++	struct device *dev = mpwr->dev;
++	ktime_t start = ktime_get();
++	int ret;
++
++	if (test_bit(MPWR_F_POWERED, mpwr->flags))
++		return;
++
++	if (!mpwr->variant->power_up) {
++		dev_err(dev, "power up requested but not implemented");
++		return;
++	}
++
++	dev_info(dev, "powering up");
++
++	ret = mpwr->variant->power_up(mpwr);
++	if (ret) {
++		dev_err(dev, "power up failed");
++	} else {
++		set_bit(MPWR_F_POWERED, mpwr->flags);
++		sysfs_notify(&mpwr->dev->kobj, NULL, "powered");
++		dev_info(mpwr->dev, "powered up in %lld ms\n",
++			 ktime_ms_delta(ktime_get(), start));
++	}
++}
++
++// }}}
++// {{{ chardev
++
++static int mpwr_release(struct inode *ip, struct file *fp)
++{
++	struct mpwr_dev* mpwr = fp->private_data;
++
++	clear_bit(MPWR_F_OPEN, mpwr->flags);
++
++	return 0;
++}
++
++static int mpwr_open(struct inode *ip, struct file *fp)
++{
++	struct mpwr_dev* mpwr = container_of(ip->i_cdev, struct mpwr_dev, cdev);
++
++	fp->private_data = mpwr;
++
++	if (test_and_set_bit(MPWR_F_OPEN, mpwr->flags))
++		return -EBUSY;
++
++	nonseekable_open(ip, fp);
++	return 0;
++}
++
++static ssize_t mpwr_read(struct file *fp, char __user *buf, size_t len,
++			 loff_t *off)
++{
++	struct mpwr_dev* mpwr = fp->private_data;
++	int non_blocking = fp->f_flags & O_NONBLOCK;
++	unsigned int copied;
++	int ret;
++
++	if (non_blocking && kfifo_is_empty(&mpwr->kfifo))
++		return -EWOULDBLOCK;
++
++	ret = wait_event_interruptible(mpwr->wait,
++				       !kfifo_is_empty(&mpwr->kfifo)
++				       || test_bit(MPWR_F_OVERFLOW, mpwr->flags));
++	if (ret)
++		return ret;
++
++	if (test_and_clear_bit(MPWR_F_OVERFLOW, mpwr->flags)) {
++		if (len < 9)
++			return -E2BIG;
++		if (copy_to_user(buf, "OVERFLOW\n", 9))
++			return -EFAULT;
++		return 9;
++	}
++
++	ret = kfifo_to_user(&mpwr->kfifo, buf, len, &copied);
++
++	return ret ? ret : copied;
++}
++
++static unsigned int mpwr_poll(struct file *fp, poll_table *wait)
++{
++	struct mpwr_dev* mpwr = fp->private_data;
++
++	poll_wait(fp, &mpwr->wait, wait);
++
++	if (!kfifo_is_empty(&mpwr->kfifo))
++		return EPOLLIN | EPOLLRDNORM;
++
++	return 0;
++}
++
++static const struct file_operations mpwr_fops = {
++	.owner		= THIS_MODULE,
++	.open		= mpwr_open,
++	.release	= mpwr_release,
++	.llseek		= noop_llseek,
++	.read		= mpwr_read,
++	.poll		= mpwr_poll,
++};
++
++// }}}
++
++static void mpwr_work_handler(struct work_struct *work)
++{
++	struct mpwr_dev *mpwr = container_of(work, struct mpwr_dev, power_work);
++	unsigned long flags;
++	int last_request;
++
++	spin_lock_irqsave(&mpwr->lock, flags);
++	last_request = mpwr->last_request;
++	mpwr->last_request = 0;
++	spin_unlock_irqrestore(&mpwr->lock, flags);
++
++	pm_stay_awake(mpwr->dev);
++
++	mutex_lock(&mpwr->modem_lock);
++
++	if (last_request == MPWR_REQ_RESET) {
++		mpwr_reset(mpwr);
++	} else if (last_request == MPWR_REQ_PWDN) {
++		mpwr_power_down(mpwr);
++	} else if (last_request == MPWR_REQ_PWUP) {
++		mpwr_power_up(mpwr);
++	}
++
++	mutex_unlock(&mpwr->modem_lock);
++
++	clear_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags);
++	sysfs_notify(&mpwr->dev->kobj, NULL, "is_busy");
++	wake_up(&mpwr->wait);
++
++	pm_relax(mpwr->dev);
++}
++
++static void mpwr_request_power_change(struct mpwr_dev* mpwr, int request, int mode)
++{
++	unsigned long flags;
++
++	set_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags);
++	sysfs_notify(&mpwr->dev->kobj, NULL, "is_busy");
++
++	spin_lock_irqsave(&mpwr->lock, flags);
++	mpwr->last_request = request;
++	if (mode >= 0)
++		mpwr->powerup_mode = mode;
++	spin_unlock_irqrestore(&mpwr->lock, flags);
++
++	queue_work(mpwr->wq, &mpwr->power_work);
++}
++
++static irqreturn_t mpwr_gpio_isr(int irq, void *dev_id)
++{
++	struct mpwr_dev *mpwr = dev_id;
++
++	if (irq == mpwr->wakeup_irq) {
++		dev_dbg(mpwr->dev, "wakeup irq\n");
++
++		if (device_can_wakeup(mpwr->dev))
++			pm_wakeup_event(mpwr->dev, 2000);
++
++		set_bit(MPWR_F_GOT_WAKEUP, mpwr->flags);
++		spin_lock(&mpwr->lock);
++		mpwr->last_wakeup = ktime_get();
++		spin_unlock(&mpwr->lock);
++		wake_up(&mpwr->wait);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static void mpwr_wd_timer_fn(struct timer_list *t)
++{
++	struct mpwr_dev *mpwr = from_timer(mpwr, t, wd_timer);
++
++	if (!mpwr->variant->monitor_wakeup || !test_bit(MPWR_F_POWERED, mpwr->flags))
++		return;
++
++	/*
++	 * Monitor wakeup status:
++	 *
++	 * If RI signal is low for too long we assume the user killswitched
++	 * the modem at runtime.
++	 */
++	spin_lock(&mpwr->lock);
++	if (!gpiod_get_value(mpwr->wakeup_gpio)) {
++		if (ktime_ms_delta(ktime_get(), mpwr->last_wakeup) > 5000) {
++			if (!test_and_set_bit(MPWR_F_KILLSWITCHED, mpwr->flags))
++				sysfs_notify(&mpwr->dev->kobj, NULL, "killswitched");
++			wake_up(&mpwr->wait);
++			dev_warn(mpwr->dev, "modem looks killswitched at runtime!\n");
++		}
++	}
++	spin_unlock(&mpwr->lock);
++
++	mod_timer(t, jiffies + msecs_to_jiffies(1000));
++}
++
++// {{{ sysfs
++
++static ssize_t powered_show(struct device *dev,
++			    struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 !!test_bit(MPWR_F_POWERED, mpwr->flags));
++}
++
++static ssize_t powered_store(struct device *dev,
++			     struct device_attribute *attr,
++			     const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	unsigned status;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtouint(buf, 10, &status);
++	if (ret)
++		return ret;
++
++	mpwr_request_power_change(mpwr, status ? MPWR_REQ_PWUP : MPWR_REQ_PWDN, status);
++
++	return len;
++}
++
++static ssize_t powered_blocking_store(struct device *dev,
++				      struct device_attribute *attr,
++				      const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	unsigned status;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtouint(buf, 10, &status);
++	if (ret)
++		return ret;
++
++	mpwr_request_power_change(mpwr, status ? MPWR_REQ_PWUP : MPWR_REQ_PWDN, status);
++
++	ret = wait_event_interruptible_timeout(mpwr->wait,
++					       !test_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags),
++					       msecs_to_jiffies(60000));
++	if (ret <= 0) {
++		dev_err(mpwr->dev, "Power state change timeout\n");
++		return -EIO;
++	}
++
++	if (!!status != !!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return -EIO;
++
++	return len;
++}
++
++static ssize_t help_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	return scnprintf(buf, PAGE_SIZE,
++			"echo N > powered, where N can be:\n"
++			"0: power off\n"
++			"1: normal powerup\n"
++			"2: dumb powerup (no AT commands and little error checking during powerup)\n"
++			"3: fastboot powerup (with biktor's patched aboot - #W_DISABLE held low during powerup)\n"
++			"4: alternate powerup (megi's userspace - DTR held high during powerup)\n\n"
++			"echo N > powered_blocking can be used for the write to block until power status transition completes\n");
++}
++
++static ssize_t killswitched_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 !!test_bit(MPWR_F_KILLSWITCHED, mpwr->flags));
++}
++
++static ssize_t is_busy_show(struct device *dev,
++			    struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 !!test_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags));
++}
++
++static ssize_t hard_reset_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	bool val;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtobool(buf, &val);
++	if (ret)
++		return ret;
++	if (val)
++		mpwr_request_power_change(mpwr, MPWR_REQ_RESET, -1);
++
++	return len;
++}
++
++static ssize_t debug_pins_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	unsigned val;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtouint(buf, 16, &val);
++	if (ret)
++		return ret;
++
++	gpiod_direction_output(mpwr->host_ready_gpio, val & BIT(0));
++	gpiod_direction_output(mpwr->enable_gpio, val & BIT(1));
++	gpiod_direction_output(mpwr->dtr_gpio, val & BIT(2));
++	gpiod_direction_output(mpwr->rts_gpio, val & BIT(3));
++
++	return len;
++}
++
++static ssize_t debug_pins_show(struct device *dev,
++			       struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "CTS=%u RI=%u\n",
++			 gpiod_get_value(mpwr->cts_gpio), gpiod_get_value(mpwr->wakeup_gpio));
++}
++
++static DEVICE_ATTR_RW(powered);
++static DEVICE_ATTR_WO(powered_blocking);
++static DEVICE_ATTR_RO(killswitched);
++static DEVICE_ATTR_RO(is_busy);
++static DEVICE_ATTR_RO(help);
++static DEVICE_ATTR_WO(hard_reset);
++static DEVICE_ATTR_RW(debug_pins);
++
++static struct attribute *mpwr_attrs[] = {
++	&dev_attr_powered.attr,
++	&dev_attr_powered_blocking.attr,
++	&dev_attr_killswitched.attr,
++	&dev_attr_is_busy.attr,
++	&dev_attr_help.attr,
++	&dev_attr_hard_reset.attr,
++	&dev_attr_debug_pins.attr,
++	NULL,
++};
++
++static const struct attribute_group mpwr_group = {
++	.attrs = mpwr_attrs,
++};
++
++// }}}
++// {{{ rfkill
++
++static int mpwr_rfkill_set(void *data, bool blocked)
++{
++	struct mpwr_dev *mpwr = data;
++
++	gpiod_set_value(mpwr->enable_gpio, !blocked);
++	return 0;
++}
++
++static void mpwr_rfkill_query(struct rfkill *rfkill, void *data)
++{
++	struct mpwr_dev *mpwr = data;
++
++	rfkill_set_sw_state(rfkill, !gpiod_get_value(mpwr->enable_gpio));
++}
++
++static const struct rfkill_ops mpwr_rfkill_ops = {
++	.set_block = mpwr_rfkill_set,
++	.query = mpwr_rfkill_query,
++};
++
++// }}}
++// {{{ probe
++
++static int mpwr_probe_generic(struct device *dev, struct mpwr_dev **mpwr_out)
++{
++	struct mpwr_dev *mpwr;
++	struct device_node *np = dev->of_node;
++	struct device *sdev;
++	const char* cdev_name = NULL;
++	int ret, i;
++
++	mpwr = devm_kzalloc(dev, sizeof(*mpwr), GFP_KERNEL);
++	if (!mpwr)
++		return -ENOMEM;
++
++	mpwr->variant = of_device_get_match_data(dev);
++	if (!mpwr->variant)
++		return -EINVAL;
++
++	mpwr->dev = dev;
++	init_waitqueue_head(&mpwr->wait);
++        mutex_init(&mpwr->modem_lock);
++        spin_lock_init(&mpwr->lock);
++	INIT_WORK(&mpwr->power_work, &mpwr_work_handler);
++	INIT_WORK(&mpwr->finish_pdn_work, &mpwr_finish_pdn_work);
++        INIT_DELAYED_WORK(&mpwr->host_ready_work, mpwr_host_ready_work);
++	INIT_KFIFO(mpwr->kfifo);
++
++	ret = of_property_read_string(np, "char-device-name", &cdev_name);
++	if (ret) {
++		dev_err(dev, "char-device-name is not configured");
++		return -EINVAL;
++	}
++
++	if (of_property_read_bool(np, "blocked"))
++		set_bit(MPWR_F_BLOCKED, mpwr->flags);
++
++	mpwr->status_pwrkey_multiplexed =
++		of_property_read_bool(np, "status-pwrkey-multiplexed");
++
++	mpwr->regulator = devm_regulator_get_optional(dev, "power");
++	if (IS_ERR(mpwr->regulator)) {
++		ret = PTR_ERR(mpwr->regulator);
++                if (ret != -ENODEV) {
++			dev_err(dev, "can't get power supply err=%d", ret);
++			return ret;
++		}
++
++		mpwr->regulator = NULL;
++	}
++
++	if (!mpwr->regulator && mpwr->variant->regulator_required) {
++		dev_err(dev, "can't get power supply err=%d", -ENODEV);
++		return -ENODEV;
++	}
++
++	mpwr->regulator_vbus = devm_regulator_get(dev, "vbus");
++	if (IS_ERR(mpwr->regulator_vbus))
++		return dev_err_probe(dev, PTR_ERR(mpwr->regulator_vbus),
++				     "can't get vbus power supply\n");
++
++	for (i = 0; mpwr->variant->gpios[i].name; i++) {
++		const struct mpwr_gpio *io = &mpwr->variant->gpios[i];
++		struct gpio_desc **desc = (struct gpio_desc **)((u8*)mpwr +
++								io->desc_off);
++		int *irq = (int*)((u8*)mpwr + io->irq_off);
++		char buf[64];
++
++		if (io->required)
++			*desc = devm_gpiod_get(dev, io->name, io->flags);
++		else
++			*desc = devm_gpiod_get_optional(dev, io->name, io->flags);
++
++		if (IS_ERR(*desc)) {
++			dev_err(dev, "can't get %s gpio err=%ld", io->name,
++				PTR_ERR(*desc));
++			return PTR_ERR(*desc);
++		}
++
++		if (!*desc)
++			continue;
++
++		if (io->irq_flags == 0 || io->irq_off == 0)
++			continue;
++
++		*irq = gpiod_to_irq(*desc);
++		if (*irq <= 0) {
++			dev_err(dev, "error converting %s gpio to irq: %d",
++				io->name, ret);
++			return *irq;
++		}
++
++		snprintf(buf, sizeof buf, "modem-%s-gpio", io->name);
++		ret = devm_request_irq(dev, *irq, mpwr_gpio_isr, io->irq_flags,
++				       devm_kstrdup(dev, buf, GFP_KERNEL), mpwr);
++		if (ret) {
++			dev_err(dev, "error requesting %s irq: %d",
++				io->name, ret);
++			return ret;
++		}
++	}
++
++	if (mpwr->status_pwrkey_multiplexed && mpwr->pwrkey_gpio) {
++		dev_err(dev, "status and pwrkey are multiplexed, but pwrkey defined\n");
++		return -EINVAL;
++	}
++
++	if (mpwr->status_pwrkey_multiplexed && !mpwr->status_gpio) {
++		dev_err(dev, "status and pwrkey are multiplexed, but status is not defined\n");
++		return -EINVAL;
++	}
++
++	ret = devm_device_add_group(dev, &mpwr_group);
++	if (ret)
++		return ret;
++
++	// create char device
++	ret = alloc_chrdev_region(&mpwr->major, 0, 1, "modem-power");
++	if (ret) {
++		dev_err(dev, "can't allocate chrdev region");
++		goto err_disable_regulator;
++	}
++
++	cdev_init(&mpwr->cdev, &mpwr_fops);
++	mpwr->cdev.owner = THIS_MODULE;
++	ret = cdev_add(&mpwr->cdev, mpwr->major, 1);
++	if (ret) {
++		dev_err(dev, "can't add cdev");
++		goto err_unreg_chrev_region;
++	}
++
++	sdev = device_create(mpwr_class, dev, mpwr->major, mpwr, cdev_name);
++	if (IS_ERR(sdev)) {
++		ret = PTR_ERR(sdev);
++		goto err_del_cdev;
++	}
++
++	if (mpwr->wakeup_irq > 0) {
++		ret = device_init_wakeup(dev, true);
++		if (ret) {
++			dev_err(dev, "failed to init wakeup (%d)\n", ret);
++			goto err_free_dev;
++		}
++	}
++
++	if (mpwr->enable_gpio) {
++		mpwr->rfkill = rfkill_alloc("modem", dev, RFKILL_TYPE_WWAN,
++					    &mpwr_rfkill_ops, mpwr);
++		if (!mpwr->rfkill) {
++			dev_err(dev, "failed to alloc rfkill\n");
++			ret = -ENOMEM;
++			goto err_deinit_wakeup;
++		}
++
++                rfkill_init_sw_state(mpwr->rfkill, false);
++
++		ret = rfkill_register(mpwr->rfkill);
++		if (ret) {
++			dev_err(dev, "failed to register rfkill (%d)\n", ret);
++			goto err_free_rfkill;
++		}
++	}
++
++	mpwr->wq = alloc_ordered_workqueue("modem-power", 0);
++	if (!mpwr->wq) {
++		ret = -ENOMEM;
++		dev_err(dev, "failed to allocate workqueue\n");
++		goto err_unreg_rfkill;
++	}
++
++	if (mpwr->variant->power_init)
++		mpwr->variant->power_init(mpwr);
++
++	timer_setup(&mpwr->wd_timer, mpwr_wd_timer_fn, 0);
++	mod_timer(&mpwr->wd_timer, jiffies + msecs_to_jiffies(50));
++
++	dev_info(dev, "modem power manager ready");
++	*mpwr_out = mpwr;
++
++	return 0;
++
++err_unreg_rfkill:
++	if (mpwr->rfkill)
++		rfkill_unregister(mpwr->rfkill);
++err_free_rfkill:
++	if (mpwr->rfkill)
++		rfkill_destroy(mpwr->rfkill);
++err_deinit_wakeup:
++	if (mpwr->wakeup_irq > 0)
++		device_init_wakeup(dev, false);
++err_free_dev:
++	device_destroy(mpwr_class, mpwr->major);
++err_del_cdev:
++	cdev_del(&mpwr->cdev);
++err_unreg_chrev_region:
++	unregister_chrdev_region(mpwr->major, 1);
++err_disable_regulator:
++	cancel_work_sync(&mpwr->power_work);
++	return ret;
++}
++
++static int mpwr_remove_generic(struct mpwr_dev *mpwr)
++{
++	if (mpwr->rfkill) {
++		rfkill_unregister(mpwr->rfkill);
++		rfkill_destroy(mpwr->rfkill);
++	}
++
++	if (mpwr->wakeup_irq > 0)
++		device_init_wakeup(mpwr->dev, false);
++
++	del_timer_sync(&mpwr->wd_timer);
++        cancel_delayed_work_sync(&mpwr->host_ready_work);
++
++	cancel_work_sync(&mpwr->power_work);
++	destroy_workqueue(mpwr->wq);
++
++	mutex_lock(&mpwr->modem_lock);
++	mpwr_power_down(mpwr);
++	mutex_unlock(&mpwr->modem_lock);
++
++	device_destroy(mpwr_class, mpwr->major);
++	cdev_del(&mpwr->cdev);
++	unregister_chrdev_region(mpwr->major, 1);
++
++	return 0;
++}
++
++static void mpwr_shutdown_generic(struct mpwr_dev *mpwr)
++{
++	cancel_work_sync(&mpwr->power_work);
++        cancel_delayed_work_sync(&mpwr->host_ready_work);
++
++	mutex_lock(&mpwr->modem_lock);
++	mpwr_power_down(mpwr);
++	mutex_unlock(&mpwr->modem_lock);
++}
++
++// }}}
++// {{{ suspend/resume
++
++static int __maybe_unused mpwr_suspend(struct device *dev)
++{
++	struct mpwr_dev *mpwr = dev_get_drvdata(dev);
++	int ret = 0;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return 0;
++
++	//if (mpwr->sleep_gpio)
++		//gpiod_direction_output(mpwr->sleep_gpio, 1);
++
++	if (mpwr->variant->suspend)
++		mpwr->variant->suspend(mpwr);
++
++	if (mpwr->wakeup_irq && device_may_wakeup(mpwr->dev))
++		enable_irq_wake(mpwr->wakeup_irq);
++
++	return ret;
++}
++
++static int __maybe_unused mpwr_resume(struct device *dev)
++{
++	struct mpwr_dev *mpwr = dev_get_drvdata(dev);
++	int ret = 0;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return 0;
++
++	//if (mpwr->sleep_gpio)
++		//gpiod_direction_output(mpwr->sleep_gpio, 0);
++
++	if (mpwr->variant->resume)
++		mpwr->variant->resume(mpwr);
++
++	if (mpwr->wakeup_irq && device_may_wakeup(mpwr->dev))
++		disable_irq_wake(mpwr->wakeup_irq);
++
++	return ret;
++}
++
++static const struct dev_pm_ops mpwr_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(mpwr_suspend, mpwr_resume)
++};
++
++// }}}
++// {{{ serdev
++
++static int mpwr_serdev_send_msg(struct mpwr_dev *mpwr, const char *msg)
++{
++	int ret, len;
++	char buf[128];
++
++	if (!mpwr->serdev)
++		return -ENODEV;
++
++	len = snprintf(buf, sizeof buf, "%s\r\n", msg);
++	if (len >= sizeof buf)
++		return -E2BIG;
++
++	ret = serdev_device_write(mpwr->serdev, buf, len, msecs_to_jiffies(3000));
++	if (ret < len)
++		return -EIO;
++
++	serdev_device_wait_until_sent(mpwr->serdev, msecs_to_jiffies(3000));
++
++	return 0;
++}
++
++static int __mpwr_serdev_at_cmd(struct mpwr_dev *mpwr, const char *msg,
++				int timeout_ms, bool report_error, bool report_timeout)
++{
++        int ret;
++
++        if (test_and_set_bit(MPWR_F_RECEIVING_MSG, mpwr->flags))
++		return -EBUSY;
++
++	mpwr->msg_len = 0;
++
++	dev_dbg(mpwr->dev, "SEND: %s\n", msg);
++
++	ret = mpwr_serdev_send_msg(mpwr, msg);
++        if (ret) {
++		clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++		dev_err(mpwr->dev, "AT command '%s' can't be sent (%d)\n", msg, ret);
++                return ret;
++        }
++
++	ret = wait_event_interruptible_timeout(mpwr->wait,
++					       !test_bit(MPWR_F_RECEIVING_MSG, mpwr->flags),
++					       msecs_to_jiffies(timeout_ms));
++	if (ret <= 0) {
++		clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++		if (report_timeout)
++			dev_err(mpwr->dev, "AT command '%s' timed out\n", msg);
++                return ret ? ret : -ETIMEDOUT;
++	}
++
++        if (!mpwr->msg_ok) {
++		if (report_error)
++			dev_err(mpwr->dev, "AT command '%s' returned ERROR\n", msg);
++                return -EINVAL;
++	}
++
++        return 0;
++}
++
++static int mpwr_serdev_at_cmd(struct mpwr_dev *mpwr, const char *msg, int timeout_ms)
++{
++	return __mpwr_serdev_at_cmd(mpwr, msg, timeout_ms, true, true);
++}
++
++static int __mpwr_serdev_at_cmd_with_retry(struct mpwr_dev *mpwr, const char *msg,
++					   int timeout_ms, int tries, bool ignore_timeout)
++{
++	int ret = 0;
++
++	if (tries < 1)
++		tries = 1;
++
++	while (tries-- > 0) {
++		ret = __mpwr_serdev_at_cmd(mpwr, msg, timeout_ms, false, !ignore_timeout);
++		if (ret != -EINVAL && (!ignore_timeout || ret != -ETIMEDOUT))
++			return ret;
++
++		if (ret != -ETIMEDOUT)
++			msleep(1000);
++	}
++
++	dev_err(mpwr->dev, "AT command '%s' returned ERROR\n", msg);
++	return ret;
++}
++
++static int mpwr_serdev_at_cmd_with_retry(struct mpwr_dev *mpwr, const char *msg,
++					 int timeout_ms, int tries)
++{
++	return __mpwr_serdev_at_cmd_with_retry(mpwr, msg, timeout_ms, tries, false);
++}
++
++static int mpwr_serdev_at_cmd_with_retry_ignore_timeout(struct mpwr_dev *mpwr, const char *msg,
++							int timeout_ms, int tries)
++{
++	return __mpwr_serdev_at_cmd_with_retry(mpwr, msg, timeout_ms, tries, true);
++}
++
++static void mpwr_serdev_receive_msg(struct mpwr_dev *mpwr, const char *msg)
++{
++	dev_dbg(mpwr->dev, "RECV: %s\n", msg);
++
++	if (mpwr->variant->recv_msg)
++		mpwr->variant->recv_msg(mpwr, msg);
++
++        if (!test_bit(MPWR_F_RECEIVING_MSG, mpwr->flags))
++                return;
++
++	if (!strcmp(msg, "OK")) {
++                clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++                mpwr->msg_ok = true;
++		wake_up(&mpwr->wait);
++                return;
++	} else if (!strcmp(msg, "ERROR")) {
++                clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++                mpwr->msg_ok = false;
++		wake_up(&mpwr->wait);
++                return;
++	} else {
++                int len = strlen(msg);
++
++                if (mpwr->msg_len + len + 1 > sizeof(mpwr->msg)) {
++                        dev_warn(mpwr->dev, "message buffer overflow, ignoring message\n");
++                        return;
++                }
++
++                memcpy(mpwr->msg + mpwr->msg_len, msg, len + 1);
++                mpwr->msg_len += len + 1;
++        }
++}
++
++static size_t mpwr_serdev_receive_buf(struct serdev_device *serdev,
++				      const u8 *buf, size_t count)
++{
++	struct mpwr_dev *mpwr = serdev_device_get_drvdata(serdev);
++	size_t avail = sizeof(mpwr->rcvbuf) - mpwr->rcvbuf_fill;
++	char* p;
++
++	if (avail < count)
++		count = avail;
++
++	if (avail > 0) {
++		memcpy(mpwr->rcvbuf + mpwr->rcvbuf_fill, buf, count);
++		mpwr->rcvbuf_fill += count;
++	}
++
++	while (true) {
++		p = strnstr(mpwr->rcvbuf, "\r\n", mpwr->rcvbuf_fill);
++		if (p) {
++			if (p > mpwr->rcvbuf) {
++				*p = 0;
++				mpwr_serdev_receive_msg(mpwr, mpwr->rcvbuf);
++			}
++
++			mpwr->rcvbuf_fill -= (p - mpwr->rcvbuf) + 2;
++			memmove(mpwr->rcvbuf, p + 2, mpwr->rcvbuf_fill);
++		} else {
++			if (sizeof(mpwr->rcvbuf) - mpwr->rcvbuf_fill == 0) {
++				mpwr->rcvbuf_fill = 0;
++				dev_warn(mpwr->dev, "rcvbuf overflow\n");
++			}
++
++			break;
++		}
++	}
++
++        return count;
++}
++
++static const struct serdev_device_ops mpwr_serdev_ops = {
++	.receive_buf = mpwr_serdev_receive_buf,
++	.write_wakeup = serdev_device_write_wakeup,
++};
++
++static int mpwr_serdev_probe(struct serdev_device *serdev)
++{
++	struct device *dev = &serdev->dev;
++        struct mpwr_dev* mpwr;
++        int ret;
++
++	ret = mpwr_probe_generic(dev, &mpwr);
++	if (ret)
++		return ret;
++
++	serdev_device_set_drvdata(serdev, mpwr);
++	serdev_device_set_client_ops(serdev, &mpwr_serdev_ops);
++	mpwr->serdev = serdev;
++
++        return 0;
++}
++
++static void mpwr_serdev_remove(struct serdev_device *serdev)
++{
++	struct mpwr_dev *mpwr = serdev_device_get_drvdata(serdev);
++
++	mpwr_remove_generic(mpwr);
++}
++
++static const struct of_device_id mpwr_of_match_serdev[] = {
++	{ .compatible = "quectel,eg25",
++	  .data = &mpwr_eg25_variant },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mpwr_of_match_serdev);
++
++static void mpwr_serdev_shutdown(struct device *dev)
++{
++	struct mpwr_dev *mpwr = dev_get_drvdata(dev);
++
++	mpwr_shutdown_generic(mpwr);
++}
++
++static struct serdev_device_driver mpwr_serdev_driver = {
++        .probe  = mpwr_serdev_probe,
++        .remove = mpwr_serdev_remove,
++        .driver = {
++                .name = DRIVER_NAME,
++                .of_match_table = mpwr_of_match_serdev,
++		.pm = &mpwr_pm_ops,
++		.shutdown = mpwr_serdev_shutdown,
++        },
++};
++
++// }}}
++// {{{ platdev
++
++static int mpwr_pdev_probe(struct platform_device *pdev)
++{
++        struct mpwr_dev* mpwr;
++        int ret;
++
++	ret = mpwr_probe_generic(&pdev->dev, &mpwr);
++	if (ret)
++		return ret;
++
++	platform_set_drvdata(pdev, mpwr);
++        return 0;
++}
++
++static int mpwr_pdev_remove(struct platform_device *pdev)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(pdev);
++
++	return mpwr_remove_generic(mpwr);
++}
++
++static void mpwr_pdev_shutdown(struct platform_device *pdev)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(pdev);
++
++	mpwr_shutdown_generic(mpwr);
++}
++
++static const struct of_device_id mpwr_of_match_plat[] = {
++	{ .compatible = "zte,mg3732",
++	  .data = &mpwr_mg2723_variant },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mpwr_of_match_plat);
++
++static struct platform_driver mpwr_platform_driver = {
++	.probe = mpwr_pdev_probe,
++	.remove = mpwr_pdev_remove,
++	.shutdown = mpwr_pdev_shutdown,
++	.driver = {
++		.name = DRIVER_NAME,
++		.of_match_table = mpwr_of_match_plat,
++		.pm = &mpwr_pm_ops,
++	},
++};
++
++// }}}
++// {{{ driver init
++
++static int __init mpwr_driver_init(void)
++{
++	int ret;
++
++	mpwr_class = class_create("modem-power");
++	if (IS_ERR(mpwr_class))
++		return PTR_ERR(mpwr_class);
++
++	ret = serdev_device_driver_register(&mpwr_serdev_driver);
++	if (ret)
++		goto err_class;
++
++	ret = platform_driver_register(&mpwr_platform_driver);
++	if (ret)
++		goto err_serdev;
++
++	return ret;
++
++err_serdev:
++	serdev_device_driver_unregister(&mpwr_serdev_driver);
++err_class:
++	class_destroy(mpwr_class);
++	return ret;
++}
++
++static void __exit mpwr_driver_exit(void)
++{
++	serdev_device_driver_unregister(&mpwr_serdev_driver);
++	platform_driver_unregister(&mpwr_platform_driver);
++	class_destroy(mpwr_class);
++}
++
++module_init(mpwr_driver_init);
++module_exit(mpwr_driver_exit);
++
++MODULE_DESCRIPTION("Modem power manager");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_LICENSE("GPL v2");
++
++// }}}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/mmc-add-delay-after-power-class-selection.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/mmc-add-delay-after-power-class-selection.patch
new file mode 100644
index 000000000000..d49faef5951a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/mmc-add-delay-after-power-class-selection.patch
@@ -0,0 +1,38 @@
+From 246b2eb49f398cce9556b5888b1e36157612b1ae Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 16 Mar 2018 20:31:55 +0100
+Subject: mmc: add delay after power class selection
+
+This seems to fix issue with sporadic ETIMEOUT in eMMC cache
+initialization on second generation TBS A711 tablet.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mmc/core/mmc.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
+index 5b2f7c285461..08efb293b70f 100644
+--- a/drivers/mmc/core/mmc.c
++++ b/drivers/mmc/core/mmc.c
+@@ -1854,6 +1854,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
+ 	 */
+ 	mmc_select_powerclass(card);
+ 
++	msleep(20);
++
+ 	/*
+ 	 * Enable HPI feature (if supported)
+ 	 */
+@@ -1872,6 +1874,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
+ 		}
+ 	}
+ 
++	msleep(20);
++
+ 	/*
+ 	 * If cache size is higher than 0, this indicates the existence of cache
+ 	 * and it can be turned on. Note that some eMMCs from Micron has been
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
new file mode 100644
index 000000000000..bd1036953604
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
@@ -0,0 +1,52 @@
+From a634b7c9d7a44a7fb2a4afa66d98afa2b0ba2433 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sat, 22 Jan 2022 20:35:39 +0000
+Subject: mmc: dw-mmc-rockchip: fix sdmmc after soft reboot
+
+During shutdown the dw-mmc driver shuts down the vqmmc regulator.
+This leads to situations where the sdmmc is unavailable after a soft
+reboot.
+Fix this by ensuring the vqmmc regulator is powered up on kernel
+shutdown.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ drivers/mmc/host/dw_mmc-rockchip.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
+index b07190ba4b7a..db2e8dd67993 100644
+--- a/drivers/mmc/host/dw_mmc-rockchip.c
++++ b/drivers/mmc/host/dw_mmc-rockchip.c
+@@ -10,6 +10,7 @@
+ #include <linux/of_address.h>
+ #include <linux/mmc/slot-gpio.h>
+ #include <linux/pm_runtime.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/slab.h>
+ 
+ #include "dw_mmc.h"
+@@ -388,9 +389,20 @@ static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
+ 			   NULL)
+ };
+ 
++static void dw_mci_rockchip_shutdown(struct platform_device *pdev)
++{
++	struct dw_mci *host = dev_get_drvdata(&pdev->dev);
++	struct mmc_host *mmc = host->slot->mmc;
++
++	if (!IS_ERR(mmc->supply.vqmmc) && !(host->vqmmc_enabled))
++		if(!regulator_enable(mmc->supply.vqmmc))
++			host->vqmmc_enabled = true;
++}
++
+ static struct platform_driver dw_mci_rockchip_pltfm_driver = {
+ 	.probe		= dw_mci_rockchip_probe,
+ 	.remove_new	= dw_mci_rockchip_remove,
++	.shutdown	= dw_mci_rockchip_shutdown,
+ 	.driver		= {
+ 		.name		= "dwmmc_rockchip",
+ 		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
new file mode 100644
index 000000000000..03a9223779fe
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
@@ -0,0 +1,143 @@
+From a77107cd515afd3b0ad4d77efe1211a50087d891 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 15 Feb 2021 09:11:16 +0100
+Subject: mmc: sunxi-mmc: Remove runtime-PM
+
+With runtime PM I get a lot of errors like (on H5/H6 f2fs formatted
+rootfs):
+
+[81360.499781] mmc_erase: group start error -110, status 0x0
+[81360.550703] mmc_erase: group start error -110, status 0x0
+[81360.599594] sunxi-mmc 4020000.mmc: data error, sending stop command
+[81360.599611] sunxi-mmc 4020000.mmc: send stop command failed
+[83474.053131] mmc_erase: group start error -110, status 0x0
+[83474.104043] mmc_erase: group start error -110, status 0x0
+[83850.888258] mmc_erase: group start error -110, status 0x0
+[83850.938810] mmc_erase: group start error -110, status 0x0
+[83850.989808] mmc_erase: group start error -110, status 0x0
+[83851.040888] mmc_erase: group start error -110, status 0x0
+[83851.091908] mmc_erase: group start error -110, status 0x0
+[83851.142938] mmc_erase: group start error -110, status 0x0
+[83851.193806] sunxi-mmc 4020000.mmc: data error, sending stop command
+[83851.193825] sunxi-mmc 4020000.mmc: send stop command failed
+[83851.201040] sunxi-mmc 4020000.mmc: data error, sending stop command
+[83851.201062] sunxi-mmc 4020000.mmc: send stop command failed
+[83851.720183] mmc_erase: group start error -110, status 0x0
+[83851.770866] mmc_erase: group start error -110, status 0x0
+[83851.821418] mmc_erase: group start error -110, status 0x0
+[83851.872081] mmc_erase: group start error -110, status 0x0
+[83851.922757] mmc_erase: group start error -110, status 0x0
+[83851.999497] mmc_erase: group start error -110, status 0x0
+[83852.050151] mmc_erase: group start error -110, status 0x0
+[83852.101319] mmc_erase: group start error -110, status 0x0
+[83852.152189] mmc_erase: group start error -110, status 0x0
+[83852.202866] mmc_erase: group start error -110, status 0x0
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mmc/host/sunxi-mmc.c | 35 +++++++++++++++++++----------------
+ 1 file changed, 19 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index d3bd0ac99ec4..e9370c736497 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -949,9 +949,15 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ {
+ 	struct sunxi_mmc_host *host = mmc_priv(mmc);
+ 
++	if (ios->power_mode == MMC_POWER_OFF)
++		sunxi_mmc_reset_host(host);
++
+ 	sunxi_mmc_card_power(host, ios);
+ 	sunxi_mmc_set_bus_width(host, ios->bus_width);
+ 	sunxi_mmc_set_clk(host, ios);
++
++	if (ios->power_mode == MMC_POWER_UP)
++		sunxi_mmc_init_host(host);
+ }
+ 
+ static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
+@@ -977,8 +983,8 @@ static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+ 	unsigned long flags;
+ 	u32 imask;
+ 
+-	if (enable)
+-		pm_runtime_get_noresume(host->dev);
++	//if (enable)
++		//pm_runtime_get_noresume(host->dev);
+ 
+ 	spin_lock_irqsave(&host->lock, flags);
+ 
+@@ -993,8 +999,8 @@ static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+ 	mmc_writel(host, REG_IMASK, imask);
+ 	spin_unlock_irqrestore(&host->lock, flags);
+ 
+-	if (!enable)
+-		pm_runtime_put_noidle(host->mmc->parent);
++	//if (!enable)
++		//pm_runtime_put_noidle(host->mmc->parent);
+ }
+ 
+ static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
+@@ -1464,10 +1470,10 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		goto error_free_dma;
+ 
+-	pm_runtime_set_active(&pdev->dev);
+-	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
+-	pm_runtime_use_autosuspend(&pdev->dev);
+-	pm_runtime_enable(&pdev->dev);
++	//pm_runtime_set_active(&pdev->dev);
++	//pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
++	//pm_runtime_use_autosuspend(&pdev->dev);
++	//pm_runtime_enable(&pdev->dev);
+ 
+ 	ret = mmc_add_host(mmc);
+ 	if (ret)
+@@ -1492,11 +1498,11 @@ static void sunxi_mmc_remove(struct platform_device *pdev)
+ 	struct sunxi_mmc_host *host = mmc_priv(mmc);
+ 
+ 	mmc_remove_host(mmc);
+-	pm_runtime_disable(&pdev->dev);
+-	if (!pm_runtime_status_suspended(&pdev->dev)) {
++	//pm_runtime_disable(&pdev->dev);
++	//if (!pm_runtime_status_suspended(&pdev->dev)) {
+ 		disable_irq(host->irq);
+ 		sunxi_mmc_disable(host);
+-	}
++	//}
+ 	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+ 	mmc_free_host(mmc);
+ }
+@@ -1531,7 +1537,6 @@ static int sunxi_mmc_runtime_suspend(struct device *dev)
+ 	 * Disabling the irq  will prevent this.
+ 	 */
+ 	disable_irq(host->irq);
+-	sunxi_mmc_reset_host(host);
+ 	sunxi_mmc_disable(host);
+ 
+ 	return 0;
+@@ -1539,8 +1544,6 @@ static int sunxi_mmc_runtime_suspend(struct device *dev)
+ #endif
+ 
+ static const struct dev_pm_ops sunxi_mmc_pm_ops = {
+-	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+-				pm_runtime_force_resume)
+ 	SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
+ 			   sunxi_mmc_runtime_resume,
+ 			   NULL)
+@@ -1550,8 +1553,8 @@ static struct platform_driver sunxi_mmc_driver = {
+ 	.driver = {
+ 		.name	= "sunxi-mmc",
+ 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+-		.of_match_table = sunxi_mmc_of_match,
+-		.pm = &sunxi_mmc_pm_ops,
++		.of_match_table = of_match_ptr(sunxi_mmc_of_match),
++		//.pm = &sunxi_mmc_pm_ops,
+ 	},
+ 	.probe		= sunxi_mmc_probe,
+ 	.remove_new	= sunxi_mmc_remove,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
new file mode 100644
index 000000000000..dc8625d2909c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
@@ -0,0 +1,85 @@
+From 501e1fe0759a6fec05ebe7479d52840ece770702 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 1 Aug 2023 14:56:33 +0200
+Subject: mtd: spi-nor: Add Alliance memory support
+
+- 128MBit flash: as25f1128mq
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mtd/spi-nor/Makefile   |  1 +
+ drivers/mtd/spi-nor/alliance.c | 24 ++++++++++++++++++++++++
+ drivers/mtd/spi-nor/core.c     |  1 +
+ drivers/mtd/spi-nor/core.h     |  1 +
+ 4 files changed, 27 insertions(+)
+ create mode 100644 drivers/mtd/spi-nor/alliance.c
+
+diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
+index 5e68468b72fc..37a3ac018a39 100644
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ 
+ spi-nor-objs			:= core.o sfdp.o swp.o otp.o sysfs.o
++spi-nor-objs			+= alliance.o
+ spi-nor-objs			+= atmel.o
+ spi-nor-objs			+= eon.o
+ spi-nor-objs			+= esmt.o
+diff --git a/drivers/mtd/spi-nor/alliance.c b/drivers/mtd/spi-nor/alliance.c
+new file mode 100644
+index 000000000000..f3f03d458a5c
+--- /dev/null
++++ b/drivers/mtd/spi-nor/alliance.c
+@@ -0,0 +1,24 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2023, Ondrej Jirman <megi@xff.cz>
++ */
++
++#include <linux/mtd/spi-nor.h>
++
++#include "core.h"
++
++static const struct flash_info alliance_nor_parts[] = {
++	{
++		.id = SNOR_ID(0x52, 0x42, 0x18),
++		.name = "as25f1128mq",
++		.size = SZ_16M,
++		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
++		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
++	},
++};
++
++const struct spi_nor_manufacturer spi_nor_alliance = {
++	.name = "alliance",
++	.parts = alliance_nor_parts,
++	.nparts = ARRAY_SIZE(alliance_nor_parts),
++};
+diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
+index 3e1f1913536b..0de0bf2ba9c3 100644
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -1973,6 +1973,7 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
+ }
+ 
+ static const struct spi_nor_manufacturer *manufacturers[] = {
++	&spi_nor_alliance,
+ 	&spi_nor_atmel,
+ 	&spi_nor_eon,
+ 	&spi_nor_esmt,
+diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
+index 442786685515..69a7dc6540d3 100644
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -590,6 +590,7 @@ struct sfdp {
+ };
+ 
+ /* Manufacturer drivers. */
++extern const struct spi_nor_manufacturer spi_nor_alliance;
+ extern const struct spi_nor_manufacturer spi_nor_atmel;
+ extern const struct spi_nor_manufacturer spi_nor_eon;
+ extern const struct spi_nor_manufacturer spi_nor_esmt;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
new file mode 100644
index 000000000000..fc03c8eb5816
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
@@ -0,0 +1,89 @@
+From 83ec9c9fbf42f657a3838fc027799c53e6edfb62 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 20 Aug 2019 14:31:38 +0200
+Subject: net: stmmac: sun8i: Add support for enabling a regulator for PHY I/O
+ pins
+
+Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
+to the phy datasheet, both regulators need to be enabled at the same time.
+
+Add support for the second optional regulator, "phy-io", to the glue
+driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 20 ++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 49704e017a48..08eeaf8d14bf 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -61,6 +61,8 @@ struct emac_variant {
+ /* struct sunxi_priv_data - hold all sunxi private data
+  * @ephy_clk:	reference to the optional EPHY clock for the internal PHY
+  * @regulator_phy: reference to the optional regulator
++ * @regulator_phy_io: reference to the optional regulator for
++ *		PHY I/O pins
+  * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
+  * @variant:	reference to the current board variant
+  * @regmap:	regmap for using the syscon
+@@ -71,6 +73,7 @@ struct emac_variant {
+ struct sunxi_priv_data {
+ 	struct clk *ephy_clk;
+ 	struct regulator *regulator_phy;
++	struct regulator *regulator_phy_io;
+ 	struct reset_control *rst_ephy;
+ 	const struct emac_variant *variant;
+ 	struct regmap_field *regmap_field;
+@@ -588,10 +591,16 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	struct sunxi_priv_data *gmac = priv;
+ 	int ret;
+ 
++	ret = regulator_enable(gmac->regulator_phy_io);
++	if (ret) {
++		dev_err(&pdev->dev, "Fail to enable PHY I/O regulator\n");
++		return ret;
++	}
++
+ 	ret = regulator_enable(gmac->regulator_phy);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "Fail to enable PHY regulator\n");
+-		return ret;
++		goto err_disable_regulator_phy_io;
+ 	}
+ 
+ 	if (gmac->use_internal_phy) {
+@@ -604,6 +613,8 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 
+ err_disable_regulator:
+ 	regulator_disable(gmac->regulator_phy);
++err_disable_regulator_phy_io:
++	regulator_disable(gmac->regulator_phy_io);
+ 
+ 	return ret;
+ }
+@@ -1051,6 +1062,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+ 		sun8i_dwmac_unpower_internal_phy(gmac);
+ 
+ 	regulator_disable(gmac->regulator_phy);
++	regulator_disable(gmac->regulator_phy_io);
+ }
+ 
+ static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
+@@ -1179,6 +1191,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy),
+ 				     "Failed to get PHY regulator\n");
+ 
++	/* Optional regulator for PHY I/O pins */
++	gmac->regulator_phy_io = devm_regulator_get(dev, "phy-io");
++	if (IS_ERR(gmac->regulator_phy_io))
++		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy_io),
++				     "Failed to get PHY I/O regulator\n");
++
+ 	/* The "GMAC clock control" register might be located in the
+ 	 * CCU address range (on the R40), or the system control address
+ 	 * range (on most other sun8i and later SoCs).
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
new file mode 100644
index 000000000000..a76dd3c42eb4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
@@ -0,0 +1,81 @@
+From a31c3f38f07b981841211e1f1aecfc0cddb7fb9f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 20 Aug 2019 14:29:29 +0200
+Subject: net: stmmac: sun8i: Rename PHY regulator variable to regulator_phy
+
+We'll be adding further optional regulators, and this makes it clearer
+what the regulator is for.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c  | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 31aa3d52fb4c..49704e017a48 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -60,7 +60,7 @@ struct emac_variant {
+ 
+ /* struct sunxi_priv_data - hold all sunxi private data
+  * @ephy_clk:	reference to the optional EPHY clock for the internal PHY
+- * @regulator:	reference to the optional regulator
++ * @regulator_phy: reference to the optional regulator
+  * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
+  * @variant:	reference to the current board variant
+  * @regmap:	regmap for using the syscon
+@@ -70,7 +70,7 @@ struct emac_variant {
+  */
+ struct sunxi_priv_data {
+ 	struct clk *ephy_clk;
+-	struct regulator *regulator;
++	struct regulator *regulator_phy;
+ 	struct reset_control *rst_ephy;
+ 	const struct emac_variant *variant;
+ 	struct regmap_field *regmap_field;
+@@ -588,9 +588,9 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	struct sunxi_priv_data *gmac = priv;
+ 	int ret;
+ 
+-	ret = regulator_enable(gmac->regulator);
++	ret = regulator_enable(gmac->regulator_phy);
+ 	if (ret) {
+-		dev_err(&pdev->dev, "Fail to enable regulator\n");
++		dev_err(&pdev->dev, "Fail to enable PHY regulator\n");
+ 		return ret;
+ 	}
+ 
+@@ -603,7 +603,7 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	return 0;
+ 
+ err_disable_regulator:
+-	regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator_phy);
+ 
+ 	return ret;
+ }
+@@ -1050,7 +1050,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+ 	if (gmac->variant->soc_has_internal_phy)
+ 		sun8i_dwmac_unpower_internal_phy(gmac);
+ 
+-	regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator_phy);
+ }
+ 
+ static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
+@@ -1174,9 +1174,9 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	/* Optional regulator for PHY */
+-	gmac->regulator = devm_regulator_get(dev, "phy");
+-	if (IS_ERR(gmac->regulator))
+-		return dev_err_probe(dev, PTR_ERR(gmac->regulator),
++	gmac->regulator_phy = devm_regulator_get(dev, "phy");
++	if (IS_ERR(gmac->regulator_phy))
++		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy),
+ 				     "Failed to get PHY regulator\n");
+ 
+ 	/* The "GMAC clock control" register might be located in the
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
new file mode 100644
index 000000000000..cc2ddb356c1e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
@@ -0,0 +1,84 @@
+From 7a99d82824522fce236ade38f2b0b1fac1e7a868 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 27 Mar 2019 13:21:06 +0100
+Subject: net: stmmac: sun8i: Use devm_regulator_get for PHY regulator
+
+Use devm_regulator_get instead of devm_regulator_get_optional and rely
+on dummy supply. This avoids NULL checks before regulator_enable/disable
+calls.
+
+This path also improves error reporting, because we now report both
+use of dummy supply and error during registration with more detail,
+instead of generic info level message "No regulator found" that
+was reported previously on errors and lack of regulator property in DT.
+
+Finally, we'll be adding further optional regulators, and the overall
+code will be simpler.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 27 +++++++------------
+ 1 file changed, 10 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index e1b761dcfa1d..31aa3d52fb4c 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -588,12 +588,10 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	struct sunxi_priv_data *gmac = priv;
+ 	int ret;
+ 
+-	if (gmac->regulator) {
+-		ret = regulator_enable(gmac->regulator);
+-		if (ret) {
+-			dev_err(&pdev->dev, "Fail to enable regulator\n");
+-			return ret;
+-		}
++	ret = regulator_enable(gmac->regulator);
++	if (ret) {
++		dev_err(&pdev->dev, "Fail to enable regulator\n");
++		return ret;
+ 	}
+ 
+ 	if (gmac->use_internal_phy) {
+@@ -605,8 +603,7 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	return 0;
+ 
+ err_disable_regulator:
+-	if (gmac->regulator)
+-		regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator);
+ 
+ 	return ret;
+ }
+@@ -1053,8 +1050,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+ 	if (gmac->variant->soc_has_internal_phy)
+ 		sun8i_dwmac_unpower_internal_phy(gmac);
+ 
+-	if (gmac->regulator)
+-		regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator);
+ }
+ 
+ static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
+@@ -1178,13 +1174,10 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	/* Optional regulator for PHY */
+-	gmac->regulator = devm_regulator_get_optional(dev, "phy");
+-	if (IS_ERR(gmac->regulator)) {
+-		if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
+-			return -EPROBE_DEFER;
+-		dev_info(dev, "No regulator found\n");
+-		gmac->regulator = NULL;
+-	}
++	gmac->regulator = devm_regulator_get(dev, "phy");
++	if (IS_ERR(gmac->regulator))
++		return dev_err_probe(dev, PTR_ERR(gmac->regulator),
++				     "Failed to get PHY regulator\n");
+ 
+ 	/* The "GMAC clock control" register might be located in the
+ 	 * CCU address range (on the R40), or the system control address
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/net-wireless-brcmfmac-Add-optional-32k-clock-enable-support.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/net-wireless-brcmfmac-Add-optional-32k-clock-enable-support.patch
new file mode 100644
index 000000000000..d493bc22c131
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/net-wireless-brcmfmac-Add-optional-32k-clock-enable-support.patch
@@ -0,0 +1,51 @@
+From 6cc6c0ac9ac8597bf2af483149547c564398b6f4 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 28 Feb 2024 21:09:51 +0100
+Subject: net: wireless: brcmfmac: Add optional 32k clock enable support
+
+WiFi modules often require 32kHz clock to function. Add support to
+enable the clock to pcie driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../net/wireless/broadcom/brcm80211/brcmfmac/pcie.c    | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+index 0ecd19c655e3..add317731126 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+@@ -3,6 +3,7 @@
+  * Copyright (c) 2014 Broadcom Corporation
+  */
+ 
++#include <linux/clk.h>
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/firmware.h>
+@@ -2413,6 +2414,7 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+ 	struct brcmf_pciedev *pcie_bus_dev;
+ 	struct brcmf_core *core;
+ 	struct brcmf_bus *bus;
++	struct clk *clk;
+ 
+ 	if (!id) {
+ 		id = pci_match_id(brcmf_pcie_devid_table, pdev);
+@@ -2424,6 +2426,14 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+ 
+ 	brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
+ 
++	clk = devm_clk_get_optional_enabled(&pdev->dev, "32k");
++	if (IS_ERR(clk))
++		return PTR_ERR(clk);
++	if (clk) {
++		dev_info(&pdev->dev, "enabling 32kHz clock\n");
++		clk_set_rate(clk, 32768);
++	}
++
+ 	ret = -ENOMEM;
+ 	devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
+ 	if (devinfo == NULL)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/net-wireless-brcmfmac-Add-support-for-detecting-AP6275P.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/net-wireless-brcmfmac-Add-support-for-detecting-AP6275P.patch
new file mode 100644
index 000000000000..7a1dceb8c643
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/net-wireless-brcmfmac-Add-support-for-detecting-AP6275P.patch
@@ -0,0 +1,80 @@
+From 43b0f9052ab464c285502f0aa3199333277bab96 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 28 Feb 2024 20:59:15 +0100
+Subject: net: wireless: brcmfmac: Add support for detecting AP6275P
+
+This module features BCM43752A2 chipset. The firmware requires
+randomness seeding, so enable it.
+
+Partially copied from https://lore.kernel.org/all/c7b331edd65b66521a6605177d654e55051568a3.camel@toradex.com/
+
+(No Signed-off-by provided in the email. The code looks like some
+data copied probably from a vendor driver and adapted for the upstream
+one.)
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c      | 5 ++++-
+ .../net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h    | 2 ++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+index 06698a714b52..0ecd19c655e3 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+@@ -70,6 +70,7 @@ BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie");
+ BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie");
+ BRCMF_FW_CLM_DEF(4378B3, "brcmfmac4378b3-pcie");
+ BRCMF_FW_CLM_DEF(4387C2, "brcmfmac4387c2-pcie");
++BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-pcie");
+ 
+ /* firmware config files */
+ MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt");
+@@ -104,6 +105,7 @@ static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
+ 	BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
++	BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */
+ 	BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0x0000000F, 4378B1), /* revision ID 3 */
+ 	BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFE0, 4378B3), /* revision ID 5 */
+@@ -1720,7 +1722,7 @@ static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
+ 		memcpy_toio(devinfo->tcm + address, nvram, nvram_len);
+ 		brcmf_fw_nvram_free(nvram);
+ 
+-		if (devinfo->otp.valid) {
++		if (devinfo->otp.valid || devinfo->ci->chip == BRCM_CC_43752_CHIP_ID) {
+ 			size_t rand_len = BRCMF_RANDOM_SEED_LENGTH;
+ 			struct brcmf_random_seed_footer footer = {
+ 				.length = cpu_to_le32(rand_len),
+@@ -2700,6 +2702,7 @@ static const struct pci_device_id brcmf_pcie_devid_table[] = {
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA),
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC),
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW),
++	BRCMF_PCIE_DEVICE(BRCM_PCIE_43752_DEVICE_ID, WCC),
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC),
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC),
+ 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4387_DEVICE_ID, WCC),
+diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+index 44684bf1b9ac..c1e22c589d85 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
++++ b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+@@ -52,6 +52,7 @@
+ #define BRCM_CC_43664_CHIP_ID		43664
+ #define BRCM_CC_43666_CHIP_ID		43666
+ #define BRCM_CC_4371_CHIP_ID		0x4371
++#define BRCM_CC_43752_CHIP_ID		43752
+ #define BRCM_CC_4377_CHIP_ID		0x4377
+ #define BRCM_CC_4378_CHIP_ID		0x4378
+ #define BRCM_CC_4387_CHIP_ID		0x4387
+@@ -94,6 +95,7 @@
+ #define BRCM_PCIE_4366_5G_DEVICE_ID	0x43c5
+ #define BRCM_PCIE_4371_DEVICE_ID	0x440d
+ #define BRCM_PCIE_43596_DEVICE_ID	0x4415
++#define BRCM_PCIE_43752_DEVICE_ID	0x449d
+ #define BRCM_PCIE_4377_DEVICE_ID	0x4488
+ #define BRCM_PCIE_4378_DEVICE_ID	0x4425
+ #define BRCM_PCIE_4387_DEVICE_ID	0x4433
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
new file mode 100644
index 000000000000..af5bb3beb388
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
@@ -0,0 +1,106 @@
+From 45742529f4bee539ea6edc4ff4f834c0ef629e65 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 10 Nov 2017 14:29:26 +0100
+Subject: nfc: pn544: Add support for VBAT/PVDD regulators
+
+Regulators are required, so this can't go into mainline as is.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/nfc/pn544/i2c.c | 31 +++++++++++++++++++++++++++++--
+ 1 file changed, 29 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/nfc/pn544/i2c.c b/drivers/nfc/pn544/i2c.c
+index 3f6d74832bac..ed6ade728f55 100644
+--- a/drivers/nfc/pn544/i2c.c
++++ b/drivers/nfc/pn544/i2c.c
+@@ -16,6 +16,7 @@
+ #include <linux/nfc.h>
+ #include <linux/firmware.h>
+ #include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
+ 
+ #include <asm/unaligned.h>
+ 
+@@ -59,6 +60,14 @@ MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match);
+ 
+ #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
+ 
++/* regulator supplies */
++static const char * const pn544_supply_names[] = {
++	"PVDD",  /* Digital Core (1.8V) supply */
++	"VBAT",  /* Analog (2.9V-5.5V) supply */
++};
++
++#define PN544_NUM_SUPPLIES ARRAY_SIZE(pn544_supply_names)
++
+ /*
+  * Exposed through the 4 most significant bytes
+  * from the HCI SW_VERSION first byte, a.k.a.
+@@ -150,6 +159,7 @@ struct pn544_i2c_phy {
+ 	struct i2c_client *i2c_dev;
+ 	struct nfc_hci_dev *hdev;
+ 
++	struct regulator_bulk_data supplies[PN544_NUM_SUPPLIES];
+ 	struct gpio_desc *gpiod_en;
+ 	struct gpio_desc *gpiod_fw;
+ 
+@@ -240,6 +250,13 @@ static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode)
+ static int pn544_hci_i2c_enable(void *phy_id)
+ {
+ 	struct pn544_i2c_phy *phy = phy_id;
++	int ret;
++
++	pr_info("%s\n", __func__);
++
++	ret = regulator_bulk_enable(PN544_NUM_SUPPLIES, phy->supplies);
++	if (ret)
++		return ret;
+ 
+ 	pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE);
+ 
+@@ -262,6 +279,8 @@ static void pn544_hci_i2c_disable(void *phy_id)
+ 	gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
+ 	usleep_range(10000, 15000);
+ 
++	regulator_bulk_disable(PN544_NUM_SUPPLIES, phy->supplies);
++
+ 	phy->powered = 0;
+ }
+ 
+@@ -368,7 +387,7 @@ static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb)
+ 
+ 	if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) ||
+ 	    (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) {
+-		nfc_err(&client->dev, "invalid len byte\n");
++		nfc_err(&client->dev, "invalid len byte %hhx\n", len);
+ 		r = -EBADMSG;
+ 		goto flush;
+ 	}
+@@ -870,7 +889,7 @@ static int pn544_hci_i2c_probe(struct i2c_client *client)
+ {
+ 	struct device *dev = &client->dev;
+ 	struct pn544_i2c_phy *phy;
+-	int r = 0;
++	int r = 0, i;
+ 
+ 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+ 		nfc_err(&client->dev, "Need I2C_FUNC_I2C\n");
+@@ -892,6 +911,14 @@ static int pn544_hci_i2c_probe(struct i2c_client *client)
+ 	if (r)
+ 		dev_dbg(dev, "Unable to add GPIO mapping table\n");
+ 
++	for (i = 0; i < PN544_NUM_SUPPLIES; i++)
++		phy->supplies[i].supply = pn544_supply_names[i];
++
++	r = devm_regulator_bulk_get(&client->dev, PN544_NUM_SUPPLIES,
++				    phy->supplies);
++	if (r)
++		return r;
++
+ 	/* Get EN GPIO */
+ 	phy->gpiod_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
+ 	if (IS_ERR(phy->gpiod_en)) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
new file mode 100644
index 000000000000..202d60fd819f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
@@ -0,0 +1,58 @@
+From 4371095c5bf709be954402a631a85262210a5a87 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 15 May 2021 21:43:44 +0200
+Subject: of: property: fw_devlink: Support allwinner,sram links
+
+allwinner,sram property points to a node representing section of SRAM,
+which is implemented by its ancestor (syscon), so we link to the
+parent of parent of the actual SRAM section node that the link points
+to.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/of/property.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/of/property.c b/drivers/of/property.c
+index a6358ee99b74..1f54582e836f 100644
+--- a/drivers/of/property.c
++++ b/drivers/of/property.c
+@@ -1322,6 +1322,27 @@ static struct device_node *parse_remote_endpoint(struct device_node *np,
+ 	return of_graph_get_remote_port_parent(np);
+ }
+ 
++static struct device_node *parse_allwinner_sram(struct device_node *np,
++						const char *prop_name, int index)
++{
++	struct device_node *sram_node;
++
++	if (!IS_ENABLED(CONFIG_SUNXI_SRAM))
++		return NULL;
++
++	if (strcmp(prop_name, "allwinner,sram"))
++		return NULL;
++
++	if (index > 0)
++		return NULL;
++
++	sram_node = of_parse_phandle(np, prop_name, 0);
++	sram_node = of_get_parent(sram_node);
++	sram_node = of_get_parent(sram_node);
++
++	return sram_node;
++}
++
+ static const struct supplier_bindings of_supplier_bindings[] = {
+ 	{ .parse_prop = parse_clocks, },
+ 	{ .parse_prop = parse_interconnects, },
+@@ -1366,6 +1387,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {
+ 		.parse_prop = parse_post_init_providers,
+ 		.fwlink_flags = FWLINK_FLAG_IGNORE,
+ 	},
++	{ .parse_prop = parse_allwinner_sram, },
+ 	{}
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
new file mode 100644
index 000000000000..37b9906bc576
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
@@ -0,0 +1,31 @@
+From 985316a368e1538c36de01819138d6de6b937606 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 29 Oct 2022 23:16:51 +0200
+Subject: opp: core: Avoid confusing error when no regulator is defined in DT
+
+A64 GPU doesn't have a separate regulator. Avoid useless error.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/opp/core.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/opp/core.c b/drivers/opp/core.c
+index e233734b7220..852c9e8fa260 100644
+--- a/drivers/opp/core.c
++++ b/drivers/opp/core.c
+@@ -2186,6 +2186,11 @@ static int _opp_set_regulators(struct opp_table *opp_table, struct device *dev,
+ 	for (i = 0; i < count; i++) {
+ 		reg = regulator_get_optional(dev, names[i]);
+ 		if (IS_ERR(reg)) {
++			if (PTR_ERR(reg) == -ENODEV) {
++				ret = -ENODEV;
++				goto free_regulators;
++			}
++
+ 			ret = dev_err_probe(dev, PTR_ERR(reg),
+ 					    "%s: no regulator (%s) found\n",
+ 					    __func__, names[i]);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
new file mode 100644
index 000000000000..6c63293116af
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
@@ -0,0 +1,32 @@
+From cd79f7ac47127513c08495b0aa4a1157e273aba9 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 14 Jun 2023 00:48:21 +0200
+Subject: pci: Workaround ITS timeouts on poweroff/reboot on Orange Pi 5 Plus
+
+Call to pci_free_irq_vectors on PCIE2x ports causes ITS timeout messages
+and delayed shutdown/reboot (by up to a minute).
+
+The root cause will be elsewhere. This is not for upstream. Anyway,
+there should be no harm from this, since we're shutting down anyway.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/pci/pcie/portdrv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c
+index 14a4b89a3b83..42699539af61 100644
+--- a/drivers/pci/pcie/portdrv.c
++++ b/drivers/pci/pcie/portdrv.c
+@@ -739,7 +739,7 @@ static void pcie_portdrv_shutdown(struct pci_dev *dev)
+ 		pm_runtime_dont_use_autosuspend(&dev->dev);
+ 	}
+ 
+-	pcie_port_device_remove(dev);
++	device_for_each_child(&dev->dev, NULL, remove_iter);
+ }
+ 
+ static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
new file mode 100644
index 000000000000..0b0eb4cd5940
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
@@ -0,0 +1,146 @@
+From 0ae98c1e1897a5cb702e852bddd2dc5fc77963dd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 8 Jun 2020 00:11:06 +0200
+Subject: phy: allwinner: sun4i-usb: Add support for usb_role_switch
+
+This allow controlling the usb0 data role from a typec port driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/phy/allwinner/Kconfig         |  1 +
+ drivers/phy/allwinner/phy-sun4i-usb.c | 51 ++++++++++++++++++++++++++-
+ 2 files changed, 51 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
+index fb584518b2d0..e93a53139460 100644
+--- a/drivers/phy/allwinner/Kconfig
++++ b/drivers/phy/allwinner/Kconfig
+@@ -12,6 +12,7 @@ config PHY_SUN4I_USB
+ 	depends on USB_SUPPORT
+ 	select GENERIC_PHY
+ 	select USB_COMMON
++	select USB_ROLE_SWITCH
+ 	help
+ 	  Enable this to support the transceiver that is part of Allwinner
+ 	  sunxi SoCs.
+diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
+index b0f19e950601..9b6b68eb00f8 100644
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -32,6 +32,7 @@
+ #include <linux/reset.h>
+ #include <linux/spinlock.h>
+ #include <linux/usb/of.h>
++#include <linux/usb/role.h>
+ #include <linux/workqueue.h>
+ 
+ #define REG_ISCR			0x00
+@@ -140,6 +141,9 @@ struct sun4i_usb_phy_data {
+ 	int id_det;
+ 	int vbus_det;
+ 	struct delayed_work detect;
++	struct usb_role_switch_desc switch_desc;
++	struct usb_role_switch *role_switch;
++	int usb_role;
+ };
+ 
+ #define to_sun4i_usb_phy_data(phy) \
+@@ -402,6 +406,9 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
+ 
+ static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
+ {
++	if (data->usb_role >= 0)
++		return data->usb_role == USB_ROLE_HOST ? 0 : 1;
++
+ 	switch (data->dr_mode) {
+ 	case USB_DR_MODE_OTG:
+ 		if (data->id_det_gpio)
+@@ -418,6 +425,9 @@ static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
+ 
+ static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
+ {
++	if (data->usb_role >= 0)
++		return data->usb_role == USB_ROLE_NONE ? 0 : 1;
++
+ 	if (data->vbus_det_gpio)
+ 		return gpiod_get_value_cansleep(data->vbus_det_gpio);
+ 
+@@ -437,7 +447,7 @@ static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
+ 
+ static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data)
+ {
+-	return data->vbus_det_gpio || data->vbus_power_supply;
++	return data->usb_role >= 0 || data->vbus_det_gpio || data->vbus_power_supply;
+ }
+ 
+ static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
+@@ -696,6 +706,24 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
+ 	return data->phys[args->args[0]].phy;
+ }
+ 
++static int sun4i_usb_role_set(struct usb_role_switch *sw, enum usb_role role)
++{
++	struct sun4i_usb_phy_data *data = usb_role_switch_get_drvdata(sw);
++
++	data->usb_role = role;
++	queue_delayed_work(system_wq, &data->detect, 0);
++
++	return 0;
++}
++
++static enum usb_role sun4i_usb_role_get(struct usb_role_switch *sw)
++{
++	struct sun4i_usb_phy_data *data = usb_role_switch_get_drvdata(sw);
++	int role = sun4i_usb_phy0_get_id_det(data) ? USB_ROLE_DEVICE : USB_ROLE_HOST;
++
++	return data->usb_role >= 0 ? data->usb_role : role;
++}
++
+ static void sun4i_usb_phy_remove(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -709,6 +737,8 @@ static void sun4i_usb_phy_remove(struct platform_device *pdev)
+ 		devm_free_irq(dev, data->vbus_det_irq, data);
+ 
+ 	cancel_delayed_work_sync(&data->detect);
++
++	usb_role_switch_unregister(data->role_switch);
+ }
+ 
+ static const unsigned int sun4i_usb_phy0_cable[] = {
+@@ -736,6 +766,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 	if (!data->cfg)
+ 		return -EINVAL;
+ 
++	data->usb_role = -1;
++
+ 	data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
+ 	if (IS_ERR(data->base))
+ 		return PTR_ERR(data->base);
+@@ -896,6 +928,23 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		return PTR_ERR(phy_provider);
+ 	}
+ 
++	/* setup role switcher */
++	data->switch_desc.name = "usb0";
++	data->switch_desc.fwnode = dev_fwnode(dev);
++	data->switch_desc.set = sun4i_usb_role_set;
++	data->switch_desc.get = sun4i_usb_role_get;
++	data->switch_desc.driver_data = data;
++
++	/*
++	 * Don't interfere with the default behavior of this driver until
++	 * the consumer of the role switch uses the switch for the first time.
++	 */
++	data->role_switch = usb_role_switch_register(dev, &data->switch_desc);
++	if (IS_ERR(data->role_switch)) {
++		dev_warn(dev, "Unable to register Role Switch\n");
++		data->role_switch = NULL;
++	}
++
+ 	dev_dbg(dev, "successfully loaded\n");
+ 
+ 	return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
new file mode 100644
index 000000000000..511364a3e460
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
@@ -0,0 +1,31 @@
+From 999b48ad26bd020b351ebe9e659359dd6aefc2c0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 27 Feb 2020 00:53:17 +0100
+Subject: power: axp20x_battery: Allow to set target voltage to 4.35V
+
+Some devices have batteries that allow that.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 6ac5c80cfda2..f24520719a74 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -374,6 +374,11 @@ static int axp20x_battery_set_max_voltage(struct axp20x_batt_ps *axp20x_batt,
+ 		val = AXP20X_CHRG_CTRL1_TGT_4_2V;
+ 		break;
+ 
++	case 4350000:
++	case 4360000:
++		val = AXP20X_CHRG_CTRL1_TGT_4_36V;
++		break;
++
+ 	default:
+ 		/*
+ 		 * AXP20x max voltage can be set to 4.36V and AXP22X max voltage
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
new file mode 100644
index 000000000000..86a9e66ece33
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
@@ -0,0 +1,43 @@
+From 2dd54aa96fa3d88ee845301859430b620001d0ad Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 14 Mar 2021 15:49:34 +0100
+Subject: power: axp803: Add interrupts for low battery power condition
+
+These are necessary so that the device is woken up by interrupt
+when low on battery, to handle the condition.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mfd/axp20x.c                  | 2 ++
+ drivers/power/supply/axp20x_battery.c | 2 ++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index a1b9039fbd66..04dd1868d3a4 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -341,6 +341,8 @@ static const struct resource axp803_battery_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_HIGH_END, "BATT_ACT_TEMP_HIGH_END"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW, "BATT_ACT_TEMP_LOW"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW_END, "BATT_ACT_TEMP_LOW_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_LOW_PWR_LVL1, "BATT_LOW_PWR_LVL1"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_LOW_PWR_LVL2, "BATT_LOW_PWR_LVL2"),
+ };
+ 
+ static const struct resource axp803_pek_resources[] = {
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 97b11f05803e..b7b3e6b945dd 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -615,6 +615,8 @@ static const struct axp_irq_data axp813_irqs[] = {
+ 	{ "BATT_HEALTH_GOOD",		axp20x_battery_changed_irq },
+ 	{ "BATT_CHARGING",		axp20x_battery_changed_irq },
+ 	{ "BATT_CHARGING_DONE",		axp20x_battery_changed_irq },
++	{ "BATT_LOW_PWR_LVL1",		axp20x_battery_changed_irq },
++	{ "BATT_LOW_PWR_LVL2",		axp20x_battery_changed_irq },
+ 	{ "BATT_CHG_TEMP_HIGH",		axp20x_battery_temp_hot_irq },
+ 	{ "BATT_CHG_TEMP_HIGH_END",	axp20x_battery_temp_normal_irq },
+ 	{ "BATT_CHG_TEMP_LOW",		axp20x_battery_temp_cold_irq },
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
new file mode 100644
index 000000000000..3ed3f0093e96
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
@@ -0,0 +1,45 @@
+From 4cb2f55337674e4caaa7d5d51d6bbf706b369950 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 22 Jun 2020 02:28:01 +0200
+Subject: power: supply: Add support for USB_BC_ENABLED and
+ USB_DCP_INPUT_CURRENT_LIMIT
+
+- USB_BC_ENABLED - enabling/disabling BC 1.2 USB type detection
+- USB_DCP_INPUT_CURRENT_LIMIT - setting a default current limit for DCP/CDP
+                                ports
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/power_supply_sysfs.c | 2 ++
+ include/linux/power_supply.h              | 2 ++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c
+index 0d2c3724d0bc..0e381050af8d 100644
+--- a/drivers/power/supply/power_supply_sysfs.c
++++ b/drivers/power/supply/power_supply_sysfs.c
+@@ -209,6 +209,8 @@ static struct power_supply_attr power_supply_attrs[] = {
+ 	POWER_SUPPLY_ATTR(TIME_TO_FULL_NOW),
+ 	POWER_SUPPLY_ATTR(TIME_TO_FULL_AVG),
+ 	POWER_SUPPLY_ENUM_ATTR(TYPE),
++	POWER_SUPPLY_ATTR(USB_BC_ENABLED),
++	POWER_SUPPLY_ATTR(USB_DCP_INPUT_CURRENT_LIMIT),
+ 	POWER_SUPPLY_ATTR(USB_TYPE),
+ 	POWER_SUPPLY_ENUM_ATTR(SCOPE),
+ 	POWER_SUPPLY_ATTR(PRECHARGE_CURRENT),
+diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
+index 8e5705a56b85..ae8dcc688cfa 100644
+--- a/include/linux/power_supply.h
++++ b/include/linux/power_supply.h
+@@ -162,6 +162,8 @@ enum power_supply_property {
+ 	POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
+ 	POWER_SUPPLY_PROP_TIME_TO_FULL_AVG,
+ 	POWER_SUPPLY_PROP_TYPE, /* use power_supply.type instead */
++	POWER_SUPPLY_PROP_USB_BC_ENABLED,
++	POWER_SUPPLY_PROP_USB_DCP_INPUT_CURRENT_LIMIT,
+ 	POWER_SUPPLY_PROP_USB_TYPE,
+ 	POWER_SUPPLY_PROP_SCOPE,
+ 	POWER_SUPPLY_PROP_PRECHARGE_CURRENT,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
new file mode 100644
index 000000000000..3c604d6e5566
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
@@ -0,0 +1,75 @@
+From 094266e7620fbc115fbe886862ed91002a580437 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 10 Nov 2022 20:05:58 +0100
+Subject: power: supply: axp20x-battery: Add support for
+ POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN
+
+Report total battery capacity.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 210be590691c..19b5f332fa75 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -85,6 +85,7 @@ struct axp20x_batt_ps {
+ 	/* Maximum constant charge current */
+ 	unsigned int max_ccc;
+ 	const struct axp_data	*data;
++	struct power_supply_battery_info *info;
+ };
+ 
+ static int axp20x_battery_get_max_voltage(struct axp20x_batt_ps *axp20x_batt,
+@@ -370,6 +371,16 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 		val->intval *= 1000;
+ 		break;
+ 
++	case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:
++		val->intval = 0;
++		if (axp20x_batt->info)
++			val->intval = axp20x_batt->info->energy_full_design_uwh;
++		return 0;
++
++	case POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN:
++		val->intval = 0;
++		return 0;
++
+ 	default:
+ 		return -EINVAL;
+ 	}
+@@ -563,6 +574,8 @@ static enum power_supply_property axp20x_battery_props[] = {
+ 	POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+ 	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+ 	POWER_SUPPLY_PROP_CAPACITY,
++	POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN,
++	POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN,
+ };
+ 
+ static int axp20x_battery_prop_writeable(struct power_supply *psy,
+@@ -704,7 +717,6 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
+ 	struct axp20x_batt_ps *axp20x_batt;
+ 	struct power_supply_config psy_cfg = {};
+-	struct power_supply_battery_info *info;
+ 	struct device *dev = &pdev->dev;
+ 	const struct axp_irq_data *irq_data;
+ 	int irq, ret;
+@@ -761,9 +773,9 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 
+ 	axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD;
+ 
+-	if (!power_supply_get_battery_info(axp20x_batt->batt, &info)) {
+-		int vmin = info->voltage_min_design_uv;
+-		int ccc = info->constant_charge_current_max_ua;
++	if (!power_supply_get_battery_info(axp20x_batt->batt, &axp20x_batt->info)) {
++		int vmin = axp20x_batt->info->voltage_min_design_uv;
++		int ccc = axp20x_batt->info->constant_charge_current_max_ua;
+ 
+ 		if (vmin > 0 && axp20x_set_voltage_min_design(axp20x_batt,
+ 							      vmin))
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
new file mode 100644
index 000000000000..18cba3290254
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
@@ -0,0 +1,35 @@
+From a3d18db65f0b5c28b942499d99985e8c7e621166 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 27 Aug 2022 20:50:43 +0200
+Subject: power: supply: axp20x-battery: Enable poweron by RTC alarm
+
+For the Pinephone to be able to poweron on RTC alarm, some bits in
+PMIC need to be enabled. This will cause PMIC to be wakeable by
+SoC pulling the interrupt line low.
+
+This may need some coordination from a bootloader.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 4e084b83e7cf..210be590691c 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -856,6 +856,11 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 		ret = regmap_update_bits(axp20x_batt->regmap, 0x84, 0x37, 0x31);
+ 		if (ret)
+ 			goto warn_bat;
++
++		// enable poweron by RTC
++		ret = regmap_update_bits(axp20x_batt->regmap, 0x8f, BIT(7), BIT(7));
++		if (ret)
++			goto warn_bat;
+ 	}
+ 
+ 	return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
new file mode 100644
index 000000000000..bdb3a8633415
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
@@ -0,0 +1,86 @@
+From 23e99e76ef026428e2e34da2ffc404f900b170d4 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Apr 2022 02:50:14 +0200
+Subject: power: supply: axp20x-battery: Support
+ POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR
+
+Support force disabling the charger in a more standardized way.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 31 +++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index b7b3e6b945dd..4e084b83e7cf 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -227,6 +227,19 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 		val->intval = !!(reg & AXP20X_PWR_OP_BATT_PRESENT);
+ 		break;
+ 
++	case POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR:
++		ret = regmap_read(axp20x_batt->regmap, AXP20X_CHRG_CTRL1,
++				  &reg);
++		if (ret)
++			return ret;
++
++		if (reg & AXP20X_CHRG_CTRL1_ENABLE)
++			val->intval = POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO;
++		else
++			val->intval = POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE;
++
++		return 0;
++
+ 	case POWER_SUPPLY_PROP_STATUS:
+ 		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE,
+ 				  &reg);
+@@ -504,6 +517,21 @@ static int axp20x_battery_set_prop(struct power_supply *psy,
+ 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
+ 		return axp20x_set_max_constant_charge_current(axp20x_batt,
+ 							      val->intval);
++	case POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR:
++		switch (val->intval) {
++		case POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO:
++			return regmap_update_bits(axp20x_batt->regmap,
++						  AXP20X_CHRG_CTRL1,
++						  AXP20X_CHRG_CTRL1_ENABLE,
++						  AXP20X_CHRG_CTRL1_ENABLE);
++		case POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE:
++			return regmap_update_bits(axp20x_batt->regmap,
++						  AXP20X_CHRG_CTRL1,
++						  AXP20X_CHRG_CTRL1_ENABLE, 0);
++		default:
++			return -EINVAL;
++		}
++
+ 	case POWER_SUPPLY_PROP_STATUS:
+ 		switch (val->intval) {
+ 		case POWER_SUPPLY_STATUS_CHARGING:
+@@ -525,6 +553,7 @@ static enum power_supply_property axp20x_battery_props[] = {
+ 	POWER_SUPPLY_PROP_PRESENT,
+ 	POWER_SUPPLY_PROP_ONLINE,
+ 	POWER_SUPPLY_PROP_STATUS,
++	POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR,
+ 	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+ 	POWER_SUPPLY_PROP_CURRENT_NOW,
+ 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT,
+@@ -540,6 +569,7 @@ static int axp20x_battery_prop_writeable(struct power_supply *psy,
+ 					 enum power_supply_property psp)
+ {
+ 	return psp == POWER_SUPPLY_PROP_STATUS ||
++	       psp == POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR ||
+ 	       psp == POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN ||
+ 	       psp == POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN ||
+ 	       psp == POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT ||
+@@ -554,6 +584,7 @@ static const struct power_supply_desc axp20x_batt_ps_desc = {
+ 	.property_is_writeable = axp20x_battery_prop_writeable,
+ 	.get_property = axp20x_battery_get_prop,
+ 	.set_property = axp20x_battery_set_prop,
++	.charge_behaviours = BIT(POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO) | BIT(POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE),
+ };
+ 
+ static irqreturn_t axp20x_battery_changed_irq(int irq, void *devid)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
new file mode 100644
index 000000000000..bcdbef0838c8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
@@ -0,0 +1,59 @@
+From 54e09ada850a5d021381fc0fc371828d369f2838 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 15 Mar 2024 21:48:34 +0100
+Subject: power: supply: axp20x-usb-power: Add missing interrupts
+
+Notify power_supply_change on BC detection interrupts for the consumers
+to get BC results ASAP.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mfd/axp20x.c                    |  2 ++
+ drivers/power/supply/axp20x_usb_power.c | 11 +++++++++--
+ 2 files changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index 04dd1868d3a4..fc89e8e8d527 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -300,6 +300,8 @@ static const struct resource axp22x_usb_power_supply_resources[] = {
+ static const struct resource axp803_usb_power_supply_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BC_USB_CHNG, "BC_USB_CHNG"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_MV_CHNG, "MV_CHNG"),
+ };
+ 
+ static const struct resource axp22x_pek_resources[] = {
+diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
+index e31f08cef861..b10ccf280451 100644
+--- a/drivers/power/supply/axp20x_usb_power.c
++++ b/drivers/power/supply/axp20x_usb_power.c
+@@ -463,6 +463,13 @@ static const char * const axp22x_irq_names[] = {
+ 	"VBUS_REMOVAL",
+ };
+ 
++static const char * const axp813_irq_names[] = {
++	"VBUS_PLUGIN",
++	"VBUS_REMOVAL",
++	"BC_USB_CHNG",
++	"MV_CHNG",
++};
++
+ static int axp192_usb_curr_lim_table[] = {
+ 	-1,
+ 	-1,
+@@ -540,8 +547,8 @@ static const struct axp_data axp223_data = {
+ 
+ static const struct axp_data axp813_data = {
+ 	.power_desc	= &axp813_usb_power_desc,
+-	.irq_names	= axp22x_irq_names,
+-	.num_irq_names	= ARRAY_SIZE(axp22x_irq_names),
++	.irq_names	= axp813_irq_names,
++	.num_irq_names	= ARRAY_SIZE(axp813_irq_names),
+ 	.curr_lim_table = axp813_usb_curr_lim_table,
+ 	.curr_lim_table_size = ARRAY_SIZE(axp813_usb_curr_lim_table),
+ 	.curr_lim_fld	= REG_FIELD(AXP22X_CHRG_CTRL3, 4, 7),
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
new file mode 100644
index 000000000000..33690291e4d5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
@@ -0,0 +1,38 @@
+From 3a844ee0cb389eb9832b4ca2baab9c9433a72359 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 14 Dec 2020 07:42:08 +0100
+Subject: power: supply: axp20x-usb-power: Change Vbus hold voltage to 4.5V
+
+This fixes USB-PD charger resets.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_usb_power.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
+index dae7e5cfc54e..e31f08cef861 100644
+--- a/drivers/power/supply/axp20x_usb_power.c
++++ b/drivers/power/supply/axp20x_usb_power.c
+@@ -733,6 +733,18 @@ static int axp20x_usb_power_probe(struct platform_device *pdev)
+ 			return ret;
+ 	}
+ 
++	/*TODO: Re-work this into a supply property with OF based default value */
++	if (of_machine_is_compatible("pine64,pinephone-1.2") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.1") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.0") > 0) {
++
++		dev_info(&pdev->dev, "Increasing Vbus hold voltage to 4.5V\n");
++
++		ret = regmap_update_bits(axp20x->regmap, 0x30, 0x7 << 3, 0x5 << 3);
++		if (ret)
++			return ret;
++	}
++
+ 	psy_cfg.of_node = pdev->dev.of_node;
+ 	psy_cfg.drv_data = power;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
new file mode 100644
index 000000000000..074b39c5e997
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
@@ -0,0 +1,63 @@
+From 55e9fc5ae8d79d4abb5360c6ac0a9f14d71bd531 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 28 Feb 2020 19:16:46 +0100
+Subject: power: supply: axp20x_battery: Add support for reporting OCV
+
+Export OCV reported by PMIC via sysfs.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index f24520719a74..bad981c349ff 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -180,6 +180,25 @@ static int axp20x_get_constant_charge_current(struct axp20x_batt_ps *axp,
+ 	return 0;
+ }
+ 
++static int axp20x_get_ocv_voltage(struct axp20x_batt_ps *axp, int *val)
++{
++	int ret;
++	unsigned int ocvh, ocvl, ocv;
++
++	ret = regmap_read(axp->regmap, AXP288_FG_OCVH_REG, &ocvh);
++	if (ret)
++		return ret;
++
++	ret = regmap_read(axp->regmap, AXP288_FG_OCVL_REG, &ocvl);
++	if (ret)
++		return ret;
++
++	ocv = ocvh << 4 | (ocvl & 0xf);
++
++	*val = ocv * 1100;
++	return 0;
++}
++
+ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 				   enum power_supply_property psp,
+ 				   union power_supply_propval *val)
+@@ -277,6 +296,9 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 		val->intval *= 1000;
+ 		break;
+ 
++	case POWER_SUPPLY_PROP_VOLTAGE_OCV:
++		return axp20x_get_ocv_voltage(axp20x_batt, &val->intval);
++
+ 	case POWER_SUPPLY_PROP_CAPACITY:
+ 		/* When no battery is present, return capacity is 100% */
+ 		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE,
+@@ -498,6 +520,7 @@ static enum power_supply_property axp20x_battery_props[] = {
+ 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT,
+ 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX,
+ 	POWER_SUPPLY_PROP_HEALTH,
++	POWER_SUPPLY_PROP_VOLTAGE_OCV,
+ 	POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+ 	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+ 	POWER_SUPPLY_PROP_CAPACITY,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
new file mode 100644
index 000000000000..ac4092521679
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
@@ -0,0 +1,40 @@
+From 327e03cb7150a2c108301f6aa7bb367eb4aac83e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 00:55:09 -0600
+Subject: power: supply: axp20x_battery: Fix charging done detection
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/supply/axp20x_battery.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 5aed07bbc716..75c835e20347 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -33,6 +33,7 @@
+ 
+ #define AXP20X_PWR_STATUS_BAT_CHARGING	BIT(2)
+ 
++#define AXP20X_PWR_OP_BATT_CHARGING	BIT(6)
+ #define AXP20X_PWR_OP_BATT_PRESENT	BIT(5)
+ #define AXP20X_PWR_OP_BATT_ACTIVATED	BIT(3)
+ 
+@@ -218,12 +219,12 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 		break;
+ 
+ 	case POWER_SUPPLY_PROP_STATUS:
+-		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_INPUT_STATUS,
++		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE,
+ 				  &reg);
+ 		if (ret)
+ 			return ret;
+ 
+-		if (reg & AXP20X_PWR_STATUS_BAT_CHARGING) {
++		if (reg & AXP20X_PWR_OP_BATT_CHARGING) {
+ 			val->intval = POWER_SUPPLY_STATUS_CHARGING;
+ 			return 0;
+ 		}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
new file mode 100644
index 000000000000..1e3eb8251292
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
@@ -0,0 +1,117 @@
+From da83d32689d81de7ef3e642a163e207f278a363d Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 01:04:33 -0600
+Subject: power: supply: axp20x_battery: Monitor battery health
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/supply/axp20x_battery.c | 58 ++++++++++++++++++++++++++-
+ 1 file changed, 56 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index a9e577768c90..97b11f05803e 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -81,6 +81,7 @@ struct axp20x_batt_ps {
+ 	struct iio_channel *batt_chrg_i;
+ 	struct iio_channel *batt_dischrg_i;
+ 	struct iio_channel *batt_v;
++	int health;
+ 	/* Maximum constant charge current */
+ 	unsigned int max_ccc;
+ 	const struct axp_data	*data;
+@@ -272,7 +273,7 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 			return 0;
+ 		}
+ 
+-		val->intval = POWER_SUPPLY_HEALTH_GOOD;
++		val->intval = axp20x_batt->health;
+ 		break;
+ 
+ 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
+@@ -564,6 +565,39 @@ static irqreturn_t axp20x_battery_changed_irq(int irq, void *devid)
+ 	return IRQ_HANDLED;
+ }
+ 
++static irqreturn_t axp20x_battery_temp_cold_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_COLD;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t axp20x_battery_temp_hot_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_OVERHEAT;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t axp20x_battery_temp_normal_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
+ static const struct axp_irq_data axp20x_irqs[] = {
+ 	{ "BATT_PLUGIN",		axp20x_battery_changed_irq },
+ 	{ "BATT_REMOVAL",		axp20x_battery_changed_irq },
+@@ -574,6 +608,24 @@ static const struct axp_irq_data axp20x_irqs[] = {
+ 	{}
+ };
+ 
++static const struct axp_irq_data axp813_irqs[] = {
++	{ "BATT_PLUGIN",		axp20x_battery_changed_irq },
++	{ "BATT_REMOVAL",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_DEAD",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_GOOD",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING_DONE",		axp20x_battery_changed_irq },
++	{ "BATT_CHG_TEMP_HIGH",		axp20x_battery_temp_hot_irq },
++	{ "BATT_CHG_TEMP_HIGH_END",	axp20x_battery_temp_normal_irq },
++	{ "BATT_CHG_TEMP_LOW",		axp20x_battery_temp_cold_irq },
++	{ "BATT_CHG_TEMP_LOW_END",	axp20x_battery_temp_normal_irq },
++	{ "BATT_ACT_TEMP_HIGH",		axp20x_battery_temp_hot_irq },
++	{ "BATT_ACT_TEMP_HIGH_END",	axp20x_battery_temp_normal_irq },
++	{ "BATT_ACT_TEMP_LOW",		axp20x_battery_temp_cold_irq },
++	{ "BATT_ACT_TEMP_LOW_END",	axp20x_battery_temp_normal_irq },
++	{}
++};
++
+ static const struct axp_data axp209_data = {
+ 	.ccc_scale = 100000,
+ 	.ccc_offset = 300000,
+@@ -597,7 +649,7 @@ static const struct axp_data axp813_data = {
+ 	.has_fg_valid = true,
+ 	.get_max_voltage = axp813_battery_get_max_voltage,
+ 	.set_max_voltage = axp20x_battery_set_max_voltage,
+-	.irqs = axp20x_irqs,
++	.irqs = axp813_irqs,
+ };
+ 
+ static const struct of_device_id axp20x_battery_ps_id[] = {
+@@ -674,6 +726,8 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 		return PTR_ERR(axp20x_batt->batt);
+ 	}
+ 
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD;
++
+ 	if (!power_supply_get_battery_info(axp20x_batt->batt, &info)) {
+ 		int vmin = info->voltage_min_design_uv;
+ 		int ccc = info->constant_charge_current_max_ua;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
new file mode 100644
index 000000000000..f0380e549864
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
@@ -0,0 +1,138 @@
+From ab370f1076679edffd09a2f8b6e33dc03bbf6b47 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 01:04:17 -0600
+Subject: power: supply: axp20x_battery: Send uevents for status changes
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/supply/axp20x_battery.c | 55 ++++++++++++++++++++++++++-
+ 1 file changed, 53 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 75c835e20347..a9e577768c90 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -56,14 +56,22 @@
+ 
+ #define AXP20X_V_OFF_MASK		GENMASK(2, 0)
+ 
++#define DRVNAME "axp20x-battery-power-supply"
++
+ struct axp20x_batt_ps;
+ 
++struct axp_irq_data {
++	const char *name;
++	irq_handler_t handler;
++};
++
+ struct axp_data {
+ 	int	ccc_scale;
+ 	int	ccc_offset;
+ 	bool	has_fg_valid;
+ 	int	(*get_max_voltage)(struct axp20x_batt_ps *batt, int *val);
+ 	int	(*set_max_voltage)(struct axp20x_batt_ps *batt, int val);
++	const struct axp_irq_data *irqs;
+ };
+ 
+ struct axp20x_batt_ps {
+@@ -547,11 +555,31 @@ static const struct power_supply_desc axp20x_batt_ps_desc = {
+ 	.set_property = axp20x_battery_set_prop,
+ };
+ 
++static irqreturn_t axp20x_battery_changed_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
++static const struct axp_irq_data axp20x_irqs[] = {
++	{ "BATT_PLUGIN",		axp20x_battery_changed_irq },
++	{ "BATT_REMOVAL",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_DEAD",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_GOOD",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING_DONE",		axp20x_battery_changed_irq },
++	{}
++};
++
+ static const struct axp_data axp209_data = {
+ 	.ccc_scale = 100000,
+ 	.ccc_offset = 300000,
+ 	.get_max_voltage = axp20x_battery_get_max_voltage,
+ 	.set_max_voltage = axp20x_battery_set_max_voltage,
++	.irqs = axp20x_irqs,
+ };
+ 
+ static const struct axp_data axp221_data = {
+@@ -560,6 +588,7 @@ static const struct axp_data axp221_data = {
+ 	.has_fg_valid = true,
+ 	.get_max_voltage = axp22x_battery_get_max_voltage,
+ 	.set_max_voltage = axp22x_battery_set_max_voltage,
++	.irqs = axp20x_irqs,
+ };
+ 
+ static const struct axp_data axp813_data = {
+@@ -568,6 +597,7 @@ static const struct axp_data axp813_data = {
+ 	.has_fg_valid = true,
+ 	.get_max_voltage = axp813_battery_get_max_voltage,
+ 	.set_max_voltage = axp20x_battery_set_max_voltage,
++	.irqs = axp20x_irqs,
+ };
+ 
+ static const struct of_device_id axp20x_battery_ps_id[] = {
+@@ -586,11 +616,13 @@ MODULE_DEVICE_TABLE(of, axp20x_battery_ps_id);
+ 
+ static int axp20x_power_probe(struct platform_device *pdev)
+ {
++	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
+ 	struct axp20x_batt_ps *axp20x_batt;
+ 	struct power_supply_config psy_cfg = {};
+ 	struct power_supply_battery_info *info;
+ 	struct device *dev = &pdev->dev;
+-	int ret;
++	const struct axp_irq_data *irq_data;
++	int irq, ret;
+ 
+ 	if (!of_device_is_available(pdev->dev.of_node))
+ 		return -ENODEV;
+@@ -664,6 +696,25 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 		}
+ 	}
+ 
++	/* Request irqs after registering, as irqs may trigger immediately */
++	for (irq_data = axp20x_batt->data->irqs; irq_data->name; irq_data++) {
++		irq = platform_get_irq_byname(pdev, irq_data->name);
++		if (irq < 0) {
++			dev_err(&pdev->dev, "No IRQ for %s: %d\n",
++				irq_data->name, irq);
++			return irq;
++		}
++		irq = regmap_irq_get_virq(axp20x->regmap_irqc, irq);
++		ret = devm_request_any_context_irq(&pdev->dev, irq,
++						   irq_data->handler, 0,
++						   DRVNAME, axp20x_batt);
++		if (ret < 0) {
++			dev_err(&pdev->dev, "Error requesting %s IRQ: %d\n",
++				irq_data->name, ret);
++			return ret;
++		}
++	}
++
+ 	/*
+ 	 * Update max CCC to a valid value if battery info is present or set it
+ 	 * to current register value by default.
+@@ -730,7 +781,7 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ static struct platform_driver axp20x_batt_driver = {
+ 	.probe    = axp20x_power_probe,
+ 	.driver   = {
+-		.name  = "axp20x-battery-power-supply",
++		.name		= DRVNAME,
+ 		.of_match_table = axp20x_battery_ps_id,
+ 	},
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
new file mode 100644
index 000000000000..aa79ce7644b1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
@@ -0,0 +1,90 @@
+From bbc5a987f7c8160d0879dfe509347e70fcbd82a2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Sep 2020 14:59:41 +0200
+Subject: power: supply: axp20x_battery: Setup thermal regulation
+ (experimental)
+
+Values for NTC resistances were pulled out of thin air!
+
+None of this is tested to actually work.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 54 +++++++++++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index bad981c349ff..5aed07bbc716 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -589,6 +589,7 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 	struct power_supply_config psy_cfg = {};
+ 	struct power_supply_battery_info *info;
+ 	struct device *dev = &pdev->dev;
++	int ret;
+ 
+ 	if (!of_device_is_available(pdev->dev.of_node))
+ 		return -ENODEV;
+@@ -669,6 +670,59 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 	axp20x_get_constant_charge_current(axp20x_batt,
+ 					   &axp20x_batt->max_ccc);
+ 
++	if (of_machine_is_compatible("pine64,pinephone-1.2") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.1") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.0") > 0) {
++		// 3kOhm NTC inside PinePhone batery
++		// ---------------------------------
++		//
++		// Charging:
++		//  0 - 15 °C: Max 0.2C CC to 4.35V : 9750 Ohm - 4710 Ohm
++		// 15 - 50 °C: Max 0.5C CC to 4.35V : 4710 Ohm - 1080 Ohm
++		//
++		// Discharging:
++		// -10 °C : 16500 Ohm
++		//  55 °C : 896 Ohm
++		// enable TS pin input to ADC
++
++		dev_info(dev, "Configuring battery thermal regulation for Pinephone\n");
++
++		ret = regmap_update_bits(axp20x_batt->regmap, 0x82, BIT(0), BIT(0));
++		if (ret)
++			goto warn_bat;
++
++		// safety thresholds:
++
++		// voltage = reg_val * 12800 uV (range is 0 - 3.264V)
++		ret = regmap_write(axp20x_batt->regmap, 0x38,  9750 * 80 / 12800); // V_LTF-charge
++		if (ret)
++			goto warn_bat;
++
++		ret = regmap_write(axp20x_batt->regmap, 0x39,  1080 * 80 / 12800); // V_HTF-charge
++		if (ret)
++			goto warn_bat;
++
++		ret = regmap_write(axp20x_batt->regmap, 0x3c, 16500 * 80 / 12800); // V_LTF-work
++		if (ret)
++			goto warn_bat;
++
++		ret = regmap_write(axp20x_batt->regmap, 0x3d,   896 * 80 / 12800); // V_HTF-work
++		if (ret)
++			goto warn_bat;
++
++		// There is a hysteresis of 460.8 mV(refer to TS pin voltage) for UTP
++		// threshold, and there is a hysteresis of 57.6 mV for OTP threshold.
++
++		// use TS pin only when charging, make it affect the charger, I = 80uA
++		ret = regmap_update_bits(axp20x_batt->regmap, 0x84, 0x37, 0x31);
++		if (ret)
++			goto warn_bat;
++	}
++
++	return 0;
++
++warn_bat:
++	dev_err(dev, "Failed to configure battery thermal regulation\n");
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
new file mode 100644
index 000000000000..415afc4ccbda
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
@@ -0,0 +1,61 @@
+From 2e4b9484b7db12e2fc43b99ef66506a33639cff6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 8 Jun 2020 00:15:04 +0200
+Subject: regulator: axp20x: Add support for vin-supply for drivevbus
+
+When drivevbus is used to control some regulator via the N_VBUSEN
+pin of the PMIC, this regulator may have a source supply. Allow to
+specify the supply using the vin-supply property.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/axp20x-regulator.c | 30 +++++++++++++++++++++++++---
+ 1 file changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index c657820b0bbb..fdd190210ff7 100644
+--- a/drivers/regulator/axp20x-regulator.c
++++ b/drivers/regulator/axp20x-regulator.c
+@@ -1618,12 +1618,36 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	if (drivevbus) {
++		struct regulator_desc *new_desc;
++		bool drivevbus_vin = false;
++		struct device_node *nr, *nd;
++
++		nr = of_get_child_by_name(pdev->dev.parent->of_node, "regulators");
++		if (nr) {
++			nd = of_get_child_by_name(nr, "drivevbus");
++			if (nd) {
++				drivevbus_vin = !!of_find_property(nd, "vin-supply", NULL);
++				of_node_put(nd);
++			}
++
++			of_node_put(nr);
++		}
++
++		new_desc = devm_kzalloc(&pdev->dev, sizeof(*new_desc), GFP_KERNEL);
++		if (!new_desc)
++			return -ENOMEM;
++
++		*new_desc = axp22x_drivevbus_regulator;
++
++		if (drivevbus_vin) {
++			new_desc->supply_name = "vin";
++			dev_info(&pdev->dev, "drivevbus has vin\n");
++		}
++
+ 		/* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
+ 		regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
+ 				   AXP22X_MISC_N_VBUSEN_FUNC, 0);
+-		rdev = devm_regulator_register(&pdev->dev,
+-					       &axp22x_drivevbus_regulator,
+-					       &config);
++		rdev = devm_regulator_register(&pdev->dev, new_desc, &config);
+ 		if (IS_ERR(rdev)) {
+ 			dev_err(&pdev->dev, "Failed to register drivevbus\n");
+ 			return PTR_ERR(rdev);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
new file mode 100644
index 000000000000..c893fbdf0339
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
@@ -0,0 +1,41 @@
+From 2e73c560f0b1bf140de1b515a45b1a3e4d040816 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 18 Feb 2020 23:57:20 +0100
+Subject: regulator: axp20x: Enable over-temperature protection and 16s reset
+ function
+
+Why not? Also why here, but whatever.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/axp20x-regulator.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index 85b35b5d1ca6..13ef198c7069 100644
+--- a/drivers/regulator/axp20x-regulator.c
++++ b/drivers/regulator/axp20x-regulator.c
+@@ -92,6 +92,8 @@
+ #define AXP22X_WORKMODE_DCDCX_MASK(x)	BIT_MASK(x)
+ 
+ #define AXP22X_MISC_N_VBUSEN_FUNC	BIT(4)
++#define AXP22X_MISC_16S_RESET_FUNC	BIT(3)
++#define AXP22X_MISC_OTP			BIT(2)
+ 
+ #define AXP22X_DCDC1_V_OUT_MASK		GENMASK(4, 0)
+ #define AXP22X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
+@@ -1662,6 +1664,11 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
+ 		}
+ 	}
+ 
++	// enable 16s power-on reset and over-temperature protection
++	regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
++			   AXP22X_MISC_16S_RESET_FUNC | AXP22X_MISC_OTP,
++			   AXP22X_MISC_16S_RESET_FUNC | AXP22X_MISC_OTP);
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
new file mode 100644
index 000000000000..5523612ad02e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
@@ -0,0 +1,53 @@
+From 3792ef7459b01344eaf076681a1a3ceeb293e49f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 9 Jun 2020 22:00:36 +0200
+Subject: regulator: axp20x: Turn N_VBUSEN to input on x-powers,sense-vbus-en
+
+When x-powers,sense-vbus-en is present on the PMIC DT node, force
+the N_VBUSEN to be an input. This is necessary on boards that
+have N_VBUSEN connected to VBUS enabling switch to make PMIC
+not charge when the board is generating VBUS voltage itself.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 4 ++++
+ drivers/regulator/axp20x-regulator.c                      | 8 ++++++++
+ 2 files changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index 4e7e237cb46a..bdca3e118ee4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -15,6 +15,10 @@ wifi_pwrseq: wifi-pwrseq {
+ 	};
+ };
+ 
++&axp803 {
++	x-powers,sense-vbus-en;
++};
++
+ &backlight {
+ 	power-supply = <&reg_ldo_io0>;
+ 	lth-brightness = <10>;
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index fdd190210ff7..85b35b5d1ca6 100644
+--- a/drivers/regulator/axp20x-regulator.c
++++ b/drivers/regulator/axp20x-regulator.c
+@@ -1617,6 +1617,14 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
+ 						&aldo1_name);
+ 	}
+ 
++	if (!drivevbus &&
++	    of_property_read_bool(pdev->dev.parent->of_node, "x-powers,sense-vbus-en")) {
++		/* make N_VBUSEN an input */
++		regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
++				   AXP22X_MISC_N_VBUSEN_FUNC,
++				   AXP22X_MISC_N_VBUSEN_FUNC);
++	}
++
+ 	if (drivevbus) {
+ 		struct regulator_desc *new_desc;
+ 		bool drivevbus_vin = false;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
new file mode 100644
index 000000000000..b90c319a738e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
@@ -0,0 +1,31 @@
+From d66d5661a67b315a0abaf2b0f23e5a79afdc2501 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Mar 2024 15:08:57 +0100
+Subject: rtc: Print which error caused RTC read failure
+
+Currently we can't know from kernel log, whether the read failed due
+to I2C bus error, or invalid time value, etc. Print the error in error
+message.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/rtc/class.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c
+index e31fa0ad127e..2f14aecf0e24 100644
+--- a/drivers/rtc/class.c
++++ b/drivers/rtc/class.c
+@@ -66,7 +66,8 @@ static void rtc_hctosys(struct rtc_device *rtc)
+ 	err = rtc_read_time(rtc, &tm);
+ 	if (err) {
+ 		dev_err(rtc->dev.parent,
+-			"hctosys: unable to read the hardware clock\n");
++			"hctosys: unable to read the hardware clock %pe\n",
++			ERR_PTR(err));
+ 		goto err_read;
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
new file mode 100644
index 000000000000..b984028c1757
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
@@ -0,0 +1,69 @@
+From 73e6986a6f82964d0e6cdf1d1a3de67b718f0419 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 2 Jan 2021 15:52:27 -0600
+Subject: rtc: sun6i: Allow RTC wakeup after shutdown
+
+Only IRQs that have enable_irq_wake() called on them can wake the system
+from sleep or after it has been shut down. Currently, the RTC alarm can
+only wake the system from sleep. Run the suspend callback to arm the IRQ
+during the shutdown process, so the RTC alarm also works after shutdown.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/rtc/rtc-sun6i.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
+index 8e0c66906103..02129ea346c1 100644
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -709,6 +709,7 @@ static struct nvmem_config sun6i_rtc_nvmem_cfg = {
+ };
+ 
+ #ifdef CONFIG_PM_SLEEP
++
+ /* Enable IRQ wake on suspend, to wake up from RTC. */
+ static int sun6i_rtc_suspend(struct device *dev)
+ {
+@@ -721,7 +722,7 @@ static int sun6i_rtc_suspend(struct device *dev)
+ }
+ 
+ /* Disable IRQ wake on resume. */
+-static int sun6i_rtc_resume(struct device *dev)
++static int __maybe_unused sun6i_rtc_resume(struct device *dev)
+ {
+ 	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
+ 
+@@ -730,6 +731,7 @@ static int sun6i_rtc_resume(struct device *dev)
+ 
+ 	return 0;
+ }
++
+ #endif
+ 
+ static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
+@@ -849,6 +851,13 @@ static int sun6i_rtc_probe(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static void sun6i_rtc_shutdown(struct platform_device *pdev)
++{
++#ifdef CONFIG_PM_SLEEP
++	sun6i_rtc_suspend(&pdev->dev);
++#endif
++}
++
+ /*
+  * As far as RTC functionality goes, all models are the same. The
+  * datasheets claim that different models have different number of
+@@ -873,6 +882,7 @@ MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
+ 
+ static struct platform_driver sun6i_rtc_driver = {
+ 	.probe		= sun6i_rtc_probe,
++	.shutdown	= sun6i_rtc_shutdown,
+ 	.driver		= {
+ 		.name		= "sun6i-rtc",
+ 		.of_match_table = sun6i_rtc_dt_ids,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
new file mode 100644
index 000000000000..43371de4a86a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
@@ -0,0 +1,1075 @@
+From 209f504838c6e1762e7495490d8500b93ec6d810 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 12 Nov 2017 23:09:14 +0100
+Subject: sound: soc: ac100-codec: Support analog part of X-Powers AC100 codec
+
+Most of the controls are implemented.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mfd/ac100.c           |   3 +
+ include/linux/mfd/ac100.h     |   1 +
+ sound/soc/sunxi/Kconfig       |  11 +
+ sound/soc/sunxi/Makefile      |   1 +
+ sound/soc/sunxi/ac100-codec.c | 991 ++++++++++++++++++++++++++++++++++
+ 5 files changed, 1007 insertions(+)
+ create mode 100644 sound/soc/sunxi/ac100-codec.c
+
+diff --git a/drivers/mfd/ac100.c b/drivers/mfd/ac100.c
+index 8f47c392cbd1..6cc9b1035642 100644
+--- a/drivers/mfd/ac100.c
++++ b/drivers/mfd/ac100.c
+@@ -79,6 +79,9 @@ static struct mfd_cell ac100_cells[] = {
+ 	{
+ 		.name		= "ac100-codec",
+ 		.of_compatible	= "x-powers,ac100-codec",
++	}, {
++		.name		= "ac100-codec-analog",
++		.of_compatible	= "x-powers,ac100-codec-analog",
+ 	}, {
+ 		.name		= "ac100-rtc",
+ 		.of_compatible	= "x-powers,ac100-rtc",
+diff --git a/include/linux/mfd/ac100.h b/include/linux/mfd/ac100.h
+index 88005c3a1b2d..621bd10b79b2 100644
+--- a/include/linux/mfd/ac100.h
++++ b/include/linux/mfd/ac100.h
+@@ -80,6 +80,7 @@ struct ac100_dev {
+ #define AC100_ERPOUT_CTRL		0x57
+ #define AC100_SPKOUT_CTRL		0x58
+ #define AC100_LINEOUT_CTRL		0x59
++#define AC100_ADDA_TUNE1 		0x5a
+ 
+ /* ADC digital audio processing (high pass filter & auto gain control */
+ #define AC100_ADC_DAP_L_STA		0x80
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index 1f18f016acbb..7b2b3bcb062e 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -22,6 +22,17 @@ config SND_SUN8I_CODEC
+ 
+ 	  Say Y or M if you want to add sun8i digital audio codec support.
+ 
++config SND_AC100_CODEC
++	tristate "Allwinner (X-Powers) AC100 audio codec (analog part)"
++	depends on OF
++	depends on MACH_SUN8I || COMPILE_TEST
++	select MFD_AC100
++	help
++	  This option enables the audio codec support for Allwinner (X-Powers)
++	  AC100 chip.
++
++	  Say Y or M if you want to add AC100 audio codec support.
++
+ config SND_SUN8I_CODEC_ANALOG
+ 	tristate "Allwinner sun8i Codec Analog Controls Support"
+ 	depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
+index 4483fe9c94ef..6131aea97efa 100644
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_SND_AC100_CODEC) += ac100-codec.o
+ obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-codec.o
+ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
+ obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+diff --git a/sound/soc/sunxi/ac100-codec.c b/sound/soc/sunxi/ac100-codec.c
+new file mode 100644
+index 000000000000..c3fec8d8da52
+--- /dev/null
++++ b/sound/soc/sunxi/ac100-codec.c
+@@ -0,0 +1,991 @@
++/*
++ * This driver supports the controls for X-Powers (Allwinner)
++ * AC100 audio codec. This codec is co-packaged with AXP81x PMICs.
++ *
++ * (C) Copyright 2020 Ondrej Jirman <megi@xff.cz>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/pm_runtime.h>
++#include <linux/regmap.h>
++#include <linux/mfd/ac100.h>
++
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/tlv.h>
++#include <sound/soc-dapm.h>
++
++#define AC100_ADC_APC_CTRL_ADCR_EN_OFF                          15
++#define AC100_ADC_APC_CTRL_ADCR_EN_MASK                         BIT(15)
++#define AC100_ADC_APC_CTRL_ADCR_EN_DISABLED                     0
++#define AC100_ADC_APC_CTRL_ADCR_EN_ENABLED                      BIT(15)
++#define AC100_ADC_APC_CTRL_ADCR_GAIN_OFF                        12
++#define AC100_ADC_APC_CTRL_ADCR_GAIN(v)                         (((v) & 0x7) << 12)
++#define AC100_ADC_APC_CTRL_ADCL_EN_OFF                          11
++#define AC100_ADC_APC_CTRL_ADCL_EN_MASK                         BIT(11)
++#define AC100_ADC_APC_CTRL_ADCL_EN_DISABLED                     0
++#define AC100_ADC_APC_CTRL_ADCL_EN_ENABLED                      BIT(11)
++#define AC100_ADC_APC_CTRL_ADCL_GAIN_OFF                        8
++#define AC100_ADC_APC_CTRL_ADCL_GAIN(v)                         (((v) & 0x7) << 8)
++#define AC100_ADC_APC_CTRL_MBIAS_EN_OFF                         7
++#define AC100_ADC_APC_CTRL_MBIAS_EN_MASK                        BIT(7)
++#define AC100_ADC_APC_CTRL_MBIAS_EN_DISABLED                    0
++#define AC100_ADC_APC_CTRL_MBIAS_EN_ENABLED                     BIT(7)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_OFF             6
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_MASK            BIT(6)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_DISABLED        0
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_ENABLED         BIT(6)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_OFF            4
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_MASK           GENMASK(5, 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_250K           (0x0 << 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_500K           (0x1 << 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_1M             (0x2 << 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_2M             (0x3 << 4)
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_OFF                       2
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_MASK                      BIT(2)
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_LOAD                      0
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_HBIAS_EN                  BIT(2)
++#define AC100_ADC_APC_CTRL_HBIAS_EN_OFF                         1
++#define AC100_ADC_APC_CTRL_HBIAS_EN_MASK                        BIT(1)
++#define AC100_ADC_APC_CTRL_HBIAS_EN_DISABLED                    0
++#define AC100_ADC_APC_CTRL_HBIAS_EN_ENABLED                     BIT(1)
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_OFF                     0
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_MASK                    BIT(0)
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_DISABLED                0
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_ENABLED                 BIT(0)
++
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_OFF                       13
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_MASK                      BIT(13)
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_ENABLED                   BIT(13)
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_OFF                       12
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_MASK                      BIT(12)
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_ENABLED                   BIT(12)
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_OFF                  11
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_MASK                 BIT(11)
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_DISABLED             0
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_ENABLED              BIT(11)
++#define AC100_ADC_SRC_ADCR_LINEINR_OFF                          10
++#define AC100_ADC_SRC_ADCR_LINEINR_MASK                         BIT(10)
++#define AC100_ADC_SRC_ADCR_LINEINR_DISABLED                     0
++#define AC100_ADC_SRC_ADCR_LINEINR_ENABLED                      BIT(10)
++#define AC100_ADC_SRC_ADCR_AUXINR_OFF                           9
++#define AC100_ADC_SRC_ADCR_AUXINR_MASK                          BIT(9)
++#define AC100_ADC_SRC_ADCR_AUXINR_DISABLED                      0
++#define AC100_ADC_SRC_ADCR_AUXINR_ENABLED                       BIT(9)
++#define AC100_ADC_SRC_ADCR_ROUTMIX_OFF                          8
++#define AC100_ADC_SRC_ADCR_ROUTMIX_MASK                         BIT(8)
++#define AC100_ADC_SRC_ADCR_ROUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCR_ROUTMIX_ENABLED                      BIT(8)
++#define AC100_ADC_SRC_ADCR_LOUTMIX_OFF                          7
++#define AC100_ADC_SRC_ADCR_LOUTMIX_MASK                         BIT(7)
++#define AC100_ADC_SRC_ADCR_LOUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCR_LOUTMIX_ENABLED                      BIT(7)
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_OFF                       6
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_MASK                      BIT(6)
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_ENABLED                   BIT(6)
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_OFF                       5
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_MASK                      BIT(5)
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_ENABLED                   BIT(5)
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_OFF                  4
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_MASK                 BIT(4)
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_DISABLED             0
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_ENABLED              BIT(4)
++#define AC100_ADC_SRC_ADCL_LINEINL_OFF                          3
++#define AC100_ADC_SRC_ADCL_LINEINL_MASK                         BIT(3)
++#define AC100_ADC_SRC_ADCL_LINEINL_DISABLED                     0
++#define AC100_ADC_SRC_ADCL_LINEINL_ENABLED                      BIT(3)
++#define AC100_ADC_SRC_ADCL_AUXINL_OFF                           2
++#define AC100_ADC_SRC_ADCL_AUXINL_MASK                          BIT(2)
++#define AC100_ADC_SRC_ADCL_AUXINL_DISABLED                      0
++#define AC100_ADC_SRC_ADCL_AUXINL_ENABLED                       BIT(2)
++#define AC100_ADC_SRC_ADCL_LOUTMIX_OFF                          1
++#define AC100_ADC_SRC_ADCL_LOUTMIX_MASK                         BIT(1)
++#define AC100_ADC_SRC_ADCL_LOUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCL_LOUTMIX_ENABLED                      BIT(1)
++#define AC100_ADC_SRC_ADCL_ROUTMIX_OFF                          0
++#define AC100_ADC_SRC_ADCL_ROUTMIX_MASK                         BIT(0)
++#define AC100_ADC_SRC_ADCL_ROUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCL_ROUTMIX_ENABLED                      BIT(0)
++
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_OFF                    15
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_MASK                   BIT(15)
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_DISABLED               0
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_ENABLED                BIT(15)
++#define AC100_ADC_SRC_BST_CTRL_MIC1BOOST_OFF                    12
++#define AC100_ADC_SRC_BST_CTRL_MIC1BOOST(v)                     (((v) & 0x7) << 12)
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_OFF                    11
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_MASK                   BIT(11)
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_DISABLED               0
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_ENABLED                BIT(11)
++#define AC100_ADC_SRC_BST_CTRL_MIC2BOOST_OFF                    8
++#define AC100_ADC_SRC_BST_CTRL_MIC2BOOST(v)                     (((v) & 0x7) << 8)
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_OFF                      7
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_MASK                     BIT(7)
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_MIC2                     0
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_MIC3                     BIT(7)
++#define AC100_ADC_SRC_BST_CTRL_LINEIN_DIFF_PREG_OFF             4
++#define AC100_ADC_SRC_BST_CTRL_LINEIN_DIFF_PREG(v)              (((v) & 0x7) << 4)
++#define AC100_ADC_SRC_BST_CTRL_AXI_PREG_OFF                     0
++#define AC100_ADC_SRC_BST_CTRL_AXI_PREG(v)                      ((v) & 0x7)
++
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_OFF                  15
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_MASK                 BIT(15)
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_ENABLED              BIT(15)
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_OFF                  14
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_MASK                 BIT(14)
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_ENABLED              BIT(14)
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_OFF                  13
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_MASK                 BIT(13)
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_ENABLED              BIT(13)
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_OFF                  12
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_MASK                 BIT(12)
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_ENABLED              BIT(12)
++#define AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN_OFF                 8
++#define AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN(v)                  (((v) & 0xf) << 8)
++
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_OFF                   13
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_MASK                  BIT(13)
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_ENABLED               BIT(13)
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_OFF                   12
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_MASK                  BIT(12)
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_ENABLED               BIT(12)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_OFF              11
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_MASK             BIT(11)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_DISABLED         0
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_ENABLED          BIT(11)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_OFF                      10
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_MASK                     BIT(10)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_DISABLED                 0
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_ENABLED                  BIT(10)
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_OFF                       9
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_MASK                      BIT(9)
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_DISABLED                  0
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_ENABLED                   BIT(9)
++#define AC100_OUT_MXR_SRC_RMIX_DACR_OFF                         8
++#define AC100_OUT_MXR_SRC_RMIX_DACR_MASK                        BIT(8)
++#define AC100_OUT_MXR_SRC_RMIX_DACR_DISABLED                    0
++#define AC100_OUT_MXR_SRC_RMIX_DACR_ENABLED                     BIT(8)
++#define AC100_OUT_MXR_SRC_RMIX_DACL_OFF                         7
++#define AC100_OUT_MXR_SRC_RMIX_DACL_MASK                        BIT(7)
++#define AC100_OUT_MXR_SRC_RMIX_DACL_DISABLED                    0
++#define AC100_OUT_MXR_SRC_RMIX_DACL_ENABLED                     BIT(7)
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_OFF                   6
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_MASK                  BIT(6)
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_ENABLED               BIT(6)
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_OFF                   5
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_MASK                  BIT(5)
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_ENABLED               BIT(5)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_OFF              4
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_MASK             BIT(4)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_DISABLED         0
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_ENABLED          BIT(4)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_OFF                      3
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_MASK                     BIT(3)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_DISABLED                 0
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_ENABLED                  BIT(3)
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_OFF                       2
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_MASK                      BIT(2)
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_DISABLED                  0
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_ENABLED                   BIT(2)
++#define AC100_OUT_MXR_SRC_LMIX_DACL_OFF                         1
++#define AC100_OUT_MXR_SRC_LMIX_DACL_MASK                        BIT(1)
++#define AC100_OUT_MXR_SRC_LMIX_DACL_DISABLED                    0
++#define AC100_OUT_MXR_SRC_LMIX_DACL_ENABLED                     BIT(1)
++#define AC100_OUT_MXR_SRC_LMIX_DACR_OFF                         0
++#define AC100_OUT_MXR_SRC_LMIX_DACR_MASK                        BIT(0)
++#define AC100_OUT_MXR_SRC_LMIX_DACR_DISABLED                    0
++#define AC100_OUT_MXR_SRC_LMIX_DACR_ENABLED                     BIT(0)
++
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_OFF              14
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_MASK             GENMASK(15, 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_1_88V            (0x0 << 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_2_09V            (0x1 << 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_2_33V            (0x2 << 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_2_50V            (0x3 << 14)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_OFF              12
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_MASK             GENMASK(13, 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_1_88V            (0x0 << 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_2_09V            (0x1 << 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_2_33V            (0x2 << 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_2_50V            (0x3 << 12)
++#define AC100_OUT_MXR_SRC_BST_AX_GAIN_OFF                       9
++#define AC100_OUT_MXR_SRC_BST_AX_GAIN(v)                        (((v) & 0x7) << 9)
++#define AC100_OUT_MXR_SRC_BST_MIC1_GAIN_OFF                     6
++#define AC100_OUT_MXR_SRC_BST_MIC1_GAIN(v)                      (((v) & 0x7) << 6)
++#define AC100_OUT_MXR_SRC_BST_MIC2_GAIN_OFF                     3
++#define AC100_OUT_MXR_SRC_BST_MIC2_GAIN(v)                      (((v) & 0x7) << 3)
++#define AC100_OUT_MXR_SRC_BST_LINEIN_GAIN_OFF                   0
++#define AC100_OUT_MXR_SRC_BST_LINEIN_GAIN(v)                    ((v) & 0x7)
++
++#define AC100_HPOUT_CTRL_RIGHT_SRC_OFF                          15
++#define AC100_HPOUT_CTRL_RIGHT_SRC_MASK                         BIT(15)
++#define AC100_HPOUT_CTRL_RIGHT_SRC_DACR                         0
++#define AC100_HPOUT_CTRL_RIGHT_SRC_RAMIX                        BIT(15)
++#define AC100_HPOUT_CTRL_LEFT_SRC_OFF                           14
++#define AC100_HPOUT_CTRL_LEFT_SRC_MASK                          BIT(14)
++#define AC100_HPOUT_CTRL_LEFT_SRC_DACL                          0
++#define AC100_HPOUT_CTRL_LEFT_SRC_LAMIX                         BIT(14)
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_OFF                      13
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_MASK                     BIT(13)
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_MUTE                     0
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_NOT_MUTE                 BIT(13)
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_OFF                       12
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_MASK                      BIT(12)
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_MUTE                      0
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_NOT_MUTE                  BIT(12)
++#define AC100_HPOUT_CTRL_PA_EN_OFF                              11
++#define AC100_HPOUT_CTRL_PA_EN_MASK                             BIT(11)
++#define AC100_HPOUT_CTRL_PA_EN_DISABLED                         0
++#define AC100_HPOUT_CTRL_PA_EN_ENABLED                          BIT(11)
++#define AC100_HPOUT_CTRL_VOLUME_OFF                             4
++#define AC100_HPOUT_CTRL_VOLUME(v)                              (((v) & 0x3f) << 4)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_OFF                      2
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_MASK                     GENMASK(3, 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_4ms                      (0x0 << 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_8ms                      (0x1 << 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_16ms                     (0x2 << 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_32ms                     (0x3 << 2)
++#define AC100_HPOUT_CTRL_OUTPUT_CURRENT_OFF                     0
++#define AC100_HPOUT_CTRL_OUTPUT_CURRENT(v)                      ((v) & 0x3)
++
++#define AC100_ERPOUT_CTRL_RAMP_TIME_OFF                         11
++#define AC100_ERPOUT_CTRL_RAMP_TIME_MASK                        GENMASK(12, 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_256ms                       (0x0 << 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_512ms                       (0x1 << 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_640ms                       (0x2 << 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_768ms                       (0x3 << 11)
++#define AC100_ERPOUT_CTRL_OUT_CURRENT_OFF                       9
++#define AC100_ERPOUT_CTRL_OUT_CURRENT(v)                        (((v) & 0x3) << 9)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_OFF                      7
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_MASK                     GENMASK(8, 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_DACR                     (0x0 << 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_DACL                     (0x1 << 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_RAMIX                    (0x2 << 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_LAMIX                    (0x3 << 7)
++#define AC100_ERPOUT_CTRL_MUTE_OFF                              6
++#define AC100_ERPOUT_CTRL_MUTE_MASK                             BIT(6)
++#define AC100_ERPOUT_CTRL_MUTE_MUTE                             0
++#define AC100_ERPOUT_CTRL_MUTE_NOT_MUTE                         BIT(6)
++#define AC100_ERPOUT_CTRL_PA_EN_OFF                             5
++#define AC100_ERPOUT_CTRL_PA_EN_MASK                            BIT(5)
++#define AC100_ERPOUT_CTRL_PA_EN_DISABLED                        0
++#define AC100_ERPOUT_CTRL_PA_EN_ENABLED                         BIT(5)
++#define AC100_ERPOUT_CTRL_VOLUME_OFF                            0
++#define AC100_ERPOUT_CTRL_VOLUME(v)                             ((v) & 0x1f)
++
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_OFF                         12
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_MASK                        BIT(12)
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_MIXR                        0
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_MIXL_MIXR                   BIT(12)
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_OFF                      11
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_MASK                     BIT(11)
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_DISABLED                 0
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_ENABLED                  BIT(11)
++#define AC100_SPKOUT_CTRL_RIGHT_EN_OFF                          9
++#define AC100_SPKOUT_CTRL_RIGHT_EN_MASK                         BIT(9)
++#define AC100_SPKOUT_CTRL_RIGHT_EN_DISABLED                     0
++#define AC100_SPKOUT_CTRL_RIGHT_EN_ENABLED                      BIT(9)
++#define AC100_SPKOUT_CTRL_LEFT_SRC_OFF                          8
++#define AC100_SPKOUT_CTRL_LEFT_SRC_MASK                         BIT(8)
++#define AC100_SPKOUT_CTRL_LEFT_SRC_MIXL                         0
++#define AC100_SPKOUT_CTRL_LEFT_SRC_MIXL_MIXR                    BIT(8)
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_OFF                       7
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_MASK                      BIT(7)
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_DISABLED                  0
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_ENABLED                   BIT(7)
++#define AC100_SPKOUT_CTRL_LEFT_EN_OFF                           5
++#define AC100_SPKOUT_CTRL_LEFT_EN_MASK                          BIT(5)
++#define AC100_SPKOUT_CTRL_LEFT_EN_DISABLED                      0
++#define AC100_SPKOUT_CTRL_LEFT_EN_ENABLED                       BIT(5)
++#define AC100_SPKOUT_CTRL_VOLUME_OFF                            0
++#define AC100_SPKOUT_CTRL_VOLUME(v)                             ((v) & 0x1f)
++
++#define AC100_LINEOUT_CTRL_LINEOUT_GAIN_OFF                     5
++#define AC100_LINEOUT_CTRL_LINEOUT_GAIN(v)                      (((v) & 0x7) << 5)
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_OFF                       4
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_MASK                      BIT(4)
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_DISABLED                  0
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_ENABLED                   BIT(4)
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_OFF                       3
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_MASK                      BIT(3)
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_ON                        BIT(3)
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_OFF                       2
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_MASK                      BIT(2)
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_ON                        BIT(2)
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_OFF                       1
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_MASK                      BIT(1)
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_ON                        BIT(1)
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_OFF                       0
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_MASK                      BIT(0)
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_ON                        BIT(0)
++
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_OFF                  8
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_MASK                 BIT(8)
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_DIS                  0
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_EN                   BIT(8)
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_TIME_OFF                7
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_TIME                    BIT(7)
++
++struct ac100_codec {
++	struct device *dev;
++	struct snd_soc_component component;
++};
++
++/* ADC mixer controls */
++static const struct snd_kcontrol_new ac100_codec_adc_mixer_controls[] = {
++	SOC_DAPM_DOUBLE("Mic1 Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_MIC1_BOOST_OFF,
++			AC100_ADC_SRC_ADCR_MIC1_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mic2 Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_MIC2_BOOST_OFF,
++			AC100_ADC_SRC_ADCR_MIC2_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Differential Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_LINEINL_LINEINR_OFF,
++			AC100_ADC_SRC_ADCR_LINEINL_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_LINEINL_OFF,
++			AC100_ADC_SRC_ADCR_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Aux In Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_AUXINL_OFF,
++			AC100_ADC_SRC_ADCR_AUXINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mixer Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_LOUTMIX_OFF,
++			AC100_ADC_SRC_ADCR_ROUTMIX_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_ROUTMIX_OFF,
++			AC100_ADC_SRC_ADCR_LOUTMIX_OFF, 1, 0),
++};
++
++/* Output mixer controls */
++static const struct snd_kcontrol_new ac100_codec_mixer_controls[] = {
++	SOC_DAPM_DOUBLE("Mic1 Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_OFF,
++			AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mic2 Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_OFF,
++			AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Differential Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_OFF,
++			AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_LINEINL_OFF,
++			AC100_OUT_MXR_SRC_RMIX_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Aux In Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_AUXINL_OFF,
++			AC100_OUT_MXR_SRC_RMIX_AUXINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("DAC Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_DACL_OFF,
++			AC100_OUT_MXR_SRC_RMIX_DACR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("DAC Reversed Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_DACR_OFF,
++			AC100_OUT_MXR_SRC_RMIX_DACL_OFF, 1, 0),
++};
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_out_mixer_pregain_scale,
++				  -450, 150, 0);
++
++static const DECLARE_TLV_DB_RANGE(ac100_codec_mic_gain_scale,
++	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
++	1, 7, TLV_DB_SCALE_ITEM(3000, 300, 0),
++);
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_pre_gain_scale,
++				  -1200, 300, 0);
++
++static const DECLARE_TLV_DB_RANGE(ac100_codec_earpiece_vol_scale,
++	0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
++	2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
++);
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_lineout_vol_scale, -450, 150, 0);
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_hp_vol_scale, -6300, 100, 1);
++
++static const char *ac100_codec_hp_pa_delay_texts[] = {
++	"4ms", "8ms", "16ms", "32ms"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_hp_pa_delay_enum,
++			    AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_STARTUP_DELAY_OFF,
++			    ac100_codec_hp_pa_delay_texts);
++
++static const char *ac100_codec_hp_pa_cur_texts[] = {
++	"low", "mid", "higher", "highest"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_hp_pa_cur_enum,
++			    AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_OUTPUT_CURRENT_OFF,
++			    ac100_codec_hp_pa_cur_texts);
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_ep_pa_cur_enum,
++			    AC100_ERPOUT_CTRL,
++			    AC100_ERPOUT_CTRL_OUT_CURRENT_OFF,
++			    ac100_codec_hp_pa_cur_texts);
++
++static const char *ac100_codec_ep_pa_ramp_time_texts[] = {
++	"256ms", "512ms", "640ms", "768ms"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_ep_pa_ramp_time_enum,
++			    AC100_ERPOUT_CTRL,
++			    AC100_ERPOUT_CTRL_RAMP_TIME_OFF,
++			    ac100_codec_ep_pa_ramp_time_texts);
++
++static const char *ac100_codec_mic_bv_texts[] = {
++	"1.88V", "2.09V", "2.33V", "2.5V"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_mic1_bv_enum,
++			    AC100_OUT_MXR_SRC_BST,
++			    AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_OFF,
++			    ac100_codec_mic_bv_texts);
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_mic2_bv_enum,
++			    AC100_OUT_MXR_SRC_BST,
++			    AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_OFF,
++			    ac100_codec_mic_bv_texts);
++
++/* volume / mute controls */
++static const struct snd_kcontrol_new ac100_codec_controls[] = {
++	/* Microphone Amp boost gain */
++	SOC_SINGLE_TLV("Mic1 Boost Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_MIC1BOOST_OFF, 0x7, 0,
++		       ac100_codec_mic_gain_scale),
++
++	SOC_SINGLE_TLV("Mic2 Boost Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_MIC2BOOST_OFF, 0x7, 0,
++		       ac100_codec_mic_gain_scale),
++
++	SOC_SINGLE_TLV("Line In Pre-Gain Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_LINEIN_DIFF_PREG_OFF, 0x7, 0,
++		       ac100_codec_pre_gain_scale),
++
++	SOC_SINGLE_TLV("Aux In Pre-Gain Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_AXI_PREG_OFF, 0x7, 0,
++		       ac100_codec_pre_gain_scale),
++
++	/* ADC */
++	SOC_DOUBLE_TLV("ADC Gain Capture Volume", AC100_ADC_APC_CTRL,
++		       AC100_ADC_APC_CTRL_ADCL_GAIN_OFF,
++		       AC100_ADC_APC_CTRL_ADCR_GAIN_OFF, 0x7, 0,
++		       ac100_codec_out_mixer_pregain_scale),
++
++	/* Mixer pre-gain */
++	SOC_SINGLE_TLV("Mic1 Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_MIC1_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Mic2 Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_MIC2_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Line In Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_LINEIN_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Aux In Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_AX_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Headphone Playback Volume",
++		       AC100_HPOUT_CTRL,
++		       AC100_HPOUT_CTRL_VOLUME_OFF, 0x3f, 0,
++		       ac100_codec_hp_vol_scale),
++
++	SOC_SINGLE_TLV("Earpiece Playback Volume",
++		       AC100_ERPOUT_CTRL,
++		       AC100_ERPOUT_CTRL_VOLUME_OFF, 0x1f, 0,
++		       ac100_codec_earpiece_vol_scale),
++
++	SOC_SINGLE_TLV("Speaker Playback Volume",
++		       AC100_SPKOUT_CTRL,
++		       AC100_SPKOUT_CTRL_VOLUME_OFF, 0x1f, 0,
++		       ac100_codec_earpiece_vol_scale),
++
++	SOC_SINGLE_TLV("Line Out Playback Volume",
++		       AC100_LINEOUT_CTRL,
++		       AC100_LINEOUT_CTRL_LINEOUT_GAIN_OFF, 0x7, 0,
++		       ac100_codec_lineout_vol_scale),
++
++	SOC_ENUM("Headphone Amplifier Startup Delay",
++		 ac100_codec_hp_pa_delay_enum),
++	SOC_ENUM("Headphone Amplifier Current", ac100_codec_hp_pa_cur_enum),
++
++	SOC_ENUM("Earpiece Amplifier Ramp Time",
++		 ac100_codec_ep_pa_ramp_time_enum),
++	SOC_ENUM("Earpiece Amplifier Current", ac100_codec_ep_pa_cur_enum),
++
++	SOC_ENUM("Mic1 Bias Voltage", ac100_codec_mic1_bv_enum),
++	SOC_ENUM("Mic2 Bias Voltage", ac100_codec_mic2_bv_enum),
++};
++
++/* Headphone */
++
++static const char * const ac100_codec_hp_src_enum_text[] = {
++	"DAC", "Mixer",
++};
++
++static SOC_ENUM_DOUBLE_DECL(ac100_codec_hp_src_enum,
++			    AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_LEFT_SRC_OFF,
++			    AC100_HPOUT_CTRL_RIGHT_SRC_OFF,
++			    ac100_codec_hp_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_hp_src[] = {
++	SOC_DAPM_ENUM("Headphone Source Playback Route",
++		      ac100_codec_hp_src_enum),
++};
++
++static const struct snd_kcontrol_new ac100_codec_hp_switch =
++	SOC_DAPM_DOUBLE("Headphone Playback Switch",
++			AC100_HPOUT_CTRL,
++			AC100_HPOUT_CTRL_LEFT_PA_MUTE_OFF,
++			AC100_HPOUT_CTRL_RIGHT_PA_MUTE_OFF, 1, 0);
++
++/* Earpiece */
++
++static const struct snd_kcontrol_new ac100_codec_earpiece_switch =
++	SOC_DAPM_SINGLE("Playback Switch",
++			AC100_ERPOUT_CTRL,
++			AC100_ERPOUT_CTRL_MUTE_OFF, 1, 0);
++
++static const char * const ac100_codec_earpiece_src_enum_text[] = {
++	"DACR", "DACL", "Right Mixer", "Left Mixer",
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_earpiece_src_enum,
++			    AC100_ERPOUT_CTRL,
++			    AC100_ERPOUT_CTRL_INPUT_SOURCE_OFF,
++			    ac100_codec_earpiece_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_earpiece_src[] = {
++	SOC_DAPM_ENUM("Earpiece Source Playback Route",
++		      ac100_codec_earpiece_src_enum),
++};
++
++/* Speaker */
++
++static const char * const ac100_codec_spk_src_enum_text[] = {
++	"Stereo", "Mono",
++};
++
++static SOC_ENUM_DOUBLE_DECL(ac100_codec_spk_src_enum,
++			    AC100_SPKOUT_CTRL,
++			    AC100_SPKOUT_CTRL_LEFT_SRC_OFF,
++			    AC100_SPKOUT_CTRL_RIGHT_SRC_OFF,
++			    ac100_codec_spk_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_spk_src[] = {
++	SOC_DAPM_ENUM("Speaker Source Playback Route",
++		      ac100_codec_spk_src_enum),
++};
++
++static const struct snd_kcontrol_new ac100_codec_spk_switch =
++	SOC_DAPM_DOUBLE("Speaker Playback Switch",
++			AC100_SPKOUT_CTRL,
++			AC100_SPKOUT_CTRL_LEFT_EN_OFF,
++			AC100_SPKOUT_CTRL_RIGHT_EN_OFF, 1, 0);
++
++static const struct snd_kcontrol_new ac100_codec_spk_inv_switch =
++	SOC_DAPM_DOUBLE("Speaker Invert Switch",
++			AC100_SPKOUT_CTRL,
++			AC100_SPKOUT_CTRL_LEFT_INV_EN_OFF,
++			AC100_SPKOUT_CTRL_RIGHT_INV_EN_OFF, 1, 0);
++
++/* Line Out */
++
++static const struct snd_kcontrol_new ac100_codec_lineout_mixer_controls[] = {
++	SOC_DAPM_SINGLE("Mic1 Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S0_OFF, 1, 0),
++	SOC_DAPM_SINGLE("Mic2 Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S1_OFF, 1, 0),
++	SOC_DAPM_SINGLE("Right Mixer Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S2_OFF, 1, 0),
++	SOC_DAPM_SINGLE("Left Mixer Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S3_OFF, 1, 0),
++};
++
++static const struct snd_kcontrol_new ac100_codec_lineout_switch =
++	SOC_DAPM_SINGLE("Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_EN_OFF, 1, 0);
++
++/* Mic2 Boost Source */
++
++static const char * const ac100_codec_mic2boost_src_enum_text[] = {
++	"Mic2", "Mic3",
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_mic2boost_src_enum,
++			    AC100_ADC_SRC_BST_CTRL,
++			    AC100_ADC_SRC_BST_CTRL_MIC2SLT_OFF,
++			    ac100_codec_mic2boost_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_mic2boost_src[] = {
++	SOC_DAPM_ENUM("Mic2 Source Capture Route",
++		      ac100_codec_mic2boost_src_enum),
++};
++
++/* This is done to remove the headphone buffer DC offset. */
++static int ac100_codec_hp_power(struct snd_soc_dapm_widget *w,
++				struct snd_kcontrol *k, int event)
++{
++	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
++	unsigned int val = SND_SOC_DAPM_EVENT_ON(event) ? 0xf : 0;
++
++	// zero cross detection
++	if (SND_SOC_DAPM_EVENT_OFF(event)) {
++		snd_soc_component_update_bits(component,
++					      AC100_ADDA_TUNE1,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_MASK,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_EN);
++	} else {
++		snd_soc_component_update_bits(component,
++					      AC100_ADDA_TUNE1,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_MASK,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_DIS);
++	}
++
++	snd_soc_component_update_bits(component, AC100_OUT_MXR_DAC_A_CTRL,
++				      AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN(0xf),
++				      AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN(val));
++	return 0;
++}
++
++static const struct snd_soc_dapm_widget ac100_codec_widgets[] = {
++	/* DAC */
++	SND_SOC_DAPM_DAC("Left DAC", NULL, AC100_OUT_MXR_DAC_A_CTRL,
++			 AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_OFF, 0),
++	SND_SOC_DAPM_DAC("Right DAC", NULL, AC100_OUT_MXR_DAC_A_CTRL,
++			 AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_OFF, 0),
++
++	/* ADC */
++	SND_SOC_DAPM_ADC("Left ADC", NULL, AC100_ADC_APC_CTRL,
++			 AC100_ADC_APC_CTRL_ADCL_EN_OFF, 0),
++	SND_SOC_DAPM_ADC("Right ADC", NULL, AC100_ADC_APC_CTRL,
++			 AC100_ADC_APC_CTRL_ADCR_EN_OFF, 0),
++
++	/*
++	 * Due to this component and the codec belonging to separate DAPM
++	 * contexts, we need to manually link the above widgets to their
++	 * stream widgets at the card level.
++	 */
++
++        /* Headphones */
++
++	SND_SOC_DAPM_REGULATOR_SUPPLY("cpvdd", 0, 0),
++	SND_SOC_DAPM_MUX("Left Headphone Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_hp_src),
++	SND_SOC_DAPM_MUX("Right Headphone Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_hp_src),
++	SND_SOC_DAPM_SWITCH("Left Headphone Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_hp_switch),
++	SND_SOC_DAPM_SWITCH("Right Headphone Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_hp_switch),
++	SND_SOC_DAPM_OUT_DRV("Left Headphone Amp",
++			     SND_SOC_NOPM, 0, 0, NULL, 0),
++	SND_SOC_DAPM_OUT_DRV("Right Headphone Amp",
++			     SND_SOC_NOPM, 0, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("Headphone Amp", AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_PA_EN_OFF, 0,
++			    ac100_codec_hp_power,
++			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
++	SND_SOC_DAPM_OUTPUT("HP"),
++
++        /* Earpiece */
++
++	SND_SOC_DAPM_MUX("Earpiece Source Playback Route",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_earpiece_src),
++	SND_SOC_DAPM_SWITCH("Earpiece",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_earpiece_switch),
++	SND_SOC_DAPM_OUT_DRV("Earpiece Amp", AC100_ERPOUT_CTRL,
++			     AC100_ERPOUT_CTRL_PA_EN_OFF, 0, NULL, 0),
++	SND_SOC_DAPM_OUTPUT("EARPIECE"),
++
++	/* Speaker */
++
++	SND_SOC_DAPM_MUX("Left Speaker Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_spk_src),
++	SND_SOC_DAPM_MUX("Right Speaker Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_spk_src),
++	SND_SOC_DAPM_SWITCH("Left Speaker Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_switch),
++	SND_SOC_DAPM_SWITCH("Right Speaker Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_switch),
++	SND_SOC_DAPM_SWITCH("Left Speaker Invert Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_inv_switch),
++	SND_SOC_DAPM_SWITCH("Right Speaker Invert Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_inv_switch),
++	SND_SOC_DAPM_OUTPUT("SPKOUTL"),
++	SND_SOC_DAPM_OUTPUT("SPKOUTR"),
++
++	/* Line Out */
++
++	SND_SOC_DAPM_MIXER("Line Out Mixer", SND_SOC_NOPM, 0, 0,
++			   ac100_codec_lineout_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_lineout_mixer_controls)),
++	SND_SOC_DAPM_SWITCH("Line Out",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_lineout_switch),
++	SND_SOC_DAPM_OUTPUT("LINEOUT"),
++
++	/* Microphone 1 */
++
++	SND_SOC_DAPM_INPUT("MIC1"),
++	SND_SOC_DAPM_SUPPLY("MBIAS", AC100_ADC_APC_CTRL,
++			    AC100_ADC_APC_CTRL_MBIAS_EN_OFF,
++			    0, NULL, 0),
++	SND_SOC_DAPM_PGA("Mic1 Amplifier", AC100_ADC_SRC_BST_CTRL,
++			 AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_OFF, 0, NULL, 0),
++
++        /* Microphone 2 and 3 */
++
++	SND_SOC_DAPM_INPUT("MIC2"),
++	SND_SOC_DAPM_INPUT("MIC3"),
++	SND_SOC_DAPM_MUX("Mic2 Amplifier Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_mic2boost_src),
++	SND_SOC_DAPM_SUPPLY("HBIAS", AC100_ADC_APC_CTRL,
++			    AC100_ADC_APC_CTRL_HBIAS_EN_OFF,
++			    0, NULL, 0),
++	SND_SOC_DAPM_PGA("Mic2 Amplifier", AC100_ADC_SRC_BST_CTRL,
++			 AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_OFF, 0, NULL, 0),
++
++	/* Line input */
++
++	SND_SOC_DAPM_INPUT("LINEIN"),
++
++	/* Aux input */
++
++	SND_SOC_DAPM_INPUT("AUXIN"),
++
++	/* Output mixers */
++	SND_SOC_DAPM_MIXER("Left Mixer", AC100_OUT_MXR_DAC_A_CTRL,
++			   AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_OFF, 0,
++			   ac100_codec_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_mixer_controls)),
++	SND_SOC_DAPM_MIXER("Right Mixer", AC100_OUT_MXR_DAC_A_CTRL,
++			   AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_OFF, 0,
++			   ac100_codec_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_mixer_controls)),
++
++	/* Input mixers */
++	SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
++			   ac100_codec_adc_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_adc_mixer_controls)),
++	SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
++			   ac100_codec_adc_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_adc_mixer_controls)),
++};
++
++static const struct snd_soc_dapm_route ac100_codec_routes[] = {
++	/* Microphone Routes */
++	{ "Mic1 Amplifier", NULL, "MIC1"},
++	{ "Mic2 Amplifier", NULL, "Mic2 Amplifier Source"},
++	{ "Mic2 Amplifier Source", "Mic2", "MIC2" },
++	{ "Mic2 Amplifier Source", "Mic3", "MIC3" },
++
++	/* Mixer Routes */
++	{ "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
++	{ "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
++	{ "Left Mixer", "Line In Differential Playback Switch", "LINEIN" },
++	{ "Left Mixer", "Line In Playback Switch", "LINEIN" },
++	{ "Left Mixer", "Aux In Playback Switch", "AUXIN" },
++	{ "Left Mixer", "DAC Playback Switch", "Left DAC" },
++	{ "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
++
++	{ "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
++	{ "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
++	{ "Right Mixer", "Line In Differential Playback Switch", "LINEIN" },
++	{ "Right Mixer", "Line In Playback Switch", "LINEIN" },
++	{ "Right Mixer", "Aux In Playback Switch", "AUXIN" },
++	{ "Right Mixer", "DAC Playback Switch", "Right DAC" },
++	{ "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
++
++	/* ADC Mixer Routes */
++	{ "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
++	{ "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
++	{ "Left ADC Mixer", "Line In Differential Capture Switch", "LINEIN" },
++	{ "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
++	{ "Left ADC Mixer", "Aux In Capture Switch", "AUXIN" },
++	{ "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
++	{ "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
++
++	{ "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
++	{ "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
++	{ "Right ADC Mixer", "Line In Differential Capture Switch", "LINEIN" },
++	{ "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
++	{ "Right ADC Mixer", "Aux In Capture Switch", "AUXIN" },
++	{ "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
++	{ "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
++
++	/* ADC Routes */
++	{ "Left ADC", NULL, "Left ADC Mixer" },
++	{ "Right ADC", NULL, "Right ADC Mixer" },
++
++	/* Headphone Routes */
++	{ "Left Headphone Source", "DAC", "Left DAC" },
++	{ "Left Headphone Source", "Mixer", "Left Mixer" },
++	{ "Left Headphone Switch", "Headphone Playback Switch", "Left Headphone Source" },
++	{ "Left Headphone Amp", NULL, "Left Headphone Switch" },
++	{ "Left Headphone Amp", NULL, "Headphone Amp" },
++	{ "HP", NULL, "Left Headphone Amp" },
++
++	{ "Right Headphone Source", "DAC", "Right DAC" },
++	{ "Right Headphone Source", "Mixer", "Right Mixer" },
++	{ "Right Headphone Switch", "Headphone Playback Switch", "Right Headphone Source" },
++	{ "Right Headphone Amp", NULL, "Right Headphone Switch" },
++	{ "Right Headphone Amp", NULL, "Headphone Amp" },
++	{ "HP", NULL, "Right Headphone Amp" },
++
++	{ "Headphone Amp", NULL, "cpvdd" },
++
++	/* Speaker Routes */
++	{ "Left Speaker Source", "Stereo", "Left Mixer" },
++	{ "Left Speaker Source", "Mono", "Right Mixer" },
++	{ "Left Speaker Source", "Mono", "Left Mixer" },
++	{ "Left Speaker Switch", "Speaker Playback Switch", "Left Speaker Source" },
++	{ "SPKOUTL", NULL, "Left Speaker Switch" },
++
++	{ "Right Speaker Source", "Stereo", "Right Mixer" },
++	{ "Right Speaker Source", "Mono", "Right Mixer" },
++	{ "Right Speaker Source", "Mono", "Left Mixer" },
++	{ "Right Speaker Switch", "Speaker Playback Switch", "Right Speaker Source" },
++	{ "SPKOUTR", NULL, "Right Speaker Switch" },
++
++	/* Earpiece Routes */
++	{ "Earpiece Source Playback Route", "DACR", "Right DAC" },
++	{ "Earpiece Source Playback Route", "DACL", "Left DAC" },
++	{ "Earpiece Source Playback Route", "Right Mixer", "Right Mixer" },
++	{ "Earpiece Source Playback Route", "Left Mixer", "Left Mixer" },
++	{ "Earpiece", "Playback Switch", "Earpiece Source Playback Route" },
++	{ "Earpiece Amp", NULL, "Earpiece" },
++	{ "EARPIECE", NULL, "Earpiece Amp" },
++
++	/* Line-out Routes */
++	{ "Line Out", "Playback Switch", "Line Out Mixer" },
++	{ "Line Out Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
++	{ "Line Out Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
++	{ "Line Out Mixer", "Right Mixer Playback Switch", "Right Mixer" },
++	{ "Line Out Mixer", "Left Mixer Playback Switch", "Left Mixer" },
++	{ "LINEOUT", NULL, "Line Out" },
++};
++
++static const struct snd_soc_component_driver ac100_codec_analog_cmpnt_drv = {
++	.controls		= ac100_codec_controls,
++	.num_controls		= ARRAY_SIZE(ac100_codec_controls),
++	.dapm_widgets		= ac100_codec_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(ac100_codec_widgets),
++	.dapm_routes		= ac100_codec_routes,
++	.num_dapm_routes	= ARRAY_SIZE(ac100_codec_routes),
++};
++
++static int ac100_codec_probe(struct platform_device *pdev)
++{
++	struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
++	struct ac100_codec *codec;
++	int ret = 0;
++
++	codec = devm_kzalloc(&pdev->dev, sizeof(*codec), GFP_KERNEL);
++	if (!codec)
++		return -ENOMEM;
++
++	codec->dev = &pdev->dev;
++	platform_set_drvdata(pdev, codec);
++
++	snd_soc_component_init_regmap(&codec->component, ac100->regmap);
++
++	ret = snd_soc_component_initialize(&codec->component,
++					   &ac100_codec_analog_cmpnt_drv,
++					   &pdev->dev);
++	if (ret < 0)
++		return ret;
++
++	ret = snd_soc_add_component(&codec->component, NULL, 0);
++	if (ret) {
++		dev_err(&pdev->dev,
++			"Failed to register codec component (%d)\n", ret);
++		return ret;
++	}
++
++	return ret;
++}
++
++static int ac100_codec_remove(struct platform_device *pdev)
++{
++	snd_soc_unregister_component(&pdev->dev);
++
++	/*
++	 * We do not call snd_soc_component_exit_regmap, because regmap
++	 * is still owned by the mfd device.
++	 */
++	return 0;
++}
++
++static const struct of_device_id ac100_codec_of_match[] = {
++	{ .compatible = "x-powers,ac100-codec-analog" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, ac100_codec_of_match);
++
++static struct platform_driver ac100_codec_driver = {
++	.driver = {
++		.name = "ac100-codec-analog",
++		.of_match_table = ac100_codec_of_match,
++	},
++	.probe = ac100_codec_probe,
++	.remove = ac100_codec_remove,
++};
++module_platform_driver(ac100_codec_driver);
++
++MODULE_DESCRIPTION("X-Powers AC100 codec driver");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ac100-codec");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
new file mode 100644
index 000000000000..8832bc8cab18
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
@@ -0,0 +1,371 @@
+From 2c3a4fc79e13866a87095c89027d2dde3462e8e1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 9 Feb 2020 17:58:59 +0100
+Subject: sound: soc: sun8i-codec: Add support for digital part of the AC100
+ codec
+
+X-Power AC100 codec has almost the same digital part as the A64 codec.
+The major difference is that registers are spaced differently. A64
+has codec register address stride of 4 bytes, while AC100 has addresses
+packed together.
+
+We use a custom regmap/regmap_bus to translate register addresses from
+the A64 regmap to the correct registers in the AC100's MFD regmap.
+
+We also need to power the codec, so AC100's regulators are also enabled
+by the codec driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/Kconfig       |   4 +-
+ sound/soc/sunxi/sun8i-codec.c | 216 ++++++++++++++++++++++++++++++++--
+ 2 files changed, 212 insertions(+), 8 deletions(-)
+
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index 7b2b3bcb062e..f87b061f59b2 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -16,9 +16,11 @@ config SND_SUN8I_CODEC
+ 	depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+ 	depends on COMMON_CLK
+ 	select REGMAP_MMIO
++	select MFD_AC100
+ 	help
+ 	  This option enables the digital part of the internal audio codec for
+-	  Allwinner sun8i SoC (and particularly A33).
++	  Allwinner sun8i SoC (and particularly A33). It also supports digital
++	  part of X-Powers AC100.
+ 
+ 	  Say Y or M if you want to add sun8i digital audio codec support.
+ 
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index f3a913d5091b..af28d9e85d39 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -21,7 +21,9 @@
+ #include <linux/of.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/log2.h>
++#include <linux/mfd/ac100.h>
+ 
+ #include <sound/jack.h>
+ #include <sound/pcm_params.h>
+@@ -194,6 +196,50 @@
+ 				 SNDRV_PCM_RATE_192000    |\
+ 				 SNDRV_PCM_RATE_KNOT)
+ 
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_OFF	15
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_MASK	BIT(15)
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_ENABLED	BIT(15)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_OFF	12
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_MASK	GENMASK(13, 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_MCLK1	(0x0 << 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_MCLK2	(0x1 << 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_BCLK1	(0x2 << 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_BCLK2	(0x3 << 12)
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_OFF	11
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_MASK	BIT(11)
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_ENABLED	BIT(11)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_OFF	8
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_MASK	GENMASK(9, 8)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_MCLK1	(0x0 << 8)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_MCLK2	(0x1 << 8)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_PLL	(0x2 << 8)
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_OFF	7
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_MASK	BIT(7)
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_ENABLED	BIT(7)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_OFF	4
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_MASK	GENMASK(5, 4)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_MCLK1	(0x0 << 4)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_MCLK2	(0x1 << 4)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_PLL	(0x2 << 4)
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_OFF	3
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_MASK	BIT(3)
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_ENABLED	BIT(3)
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_OFF	0
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_MASK	BIT(0)
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_I2S1CLK	0
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_I2S2CLK	BIT(0)
++
++static const char *const ac100_supply_names[] = {
++	"LDOIN",
++	"AVCC",
++	"VDDIO1",
++	"VDDIO2",
++};
++
+ enum {
+ 	SUN8I_CODEC_AIF1,
+ 	SUN8I_CODEC_AIF2,
+@@ -241,6 +287,9 @@ struct sun8i_codec {
+ 	int				last_hmic_irq;
+ 	unsigned int			sysclk_rate;
+ 	int				sysclk_refcnt;
++
++	struct regmap			*ac100_regmap;
++	struct regulator_bulk_data	supplies[ARRAY_SIZE(ac100_supply_names)];
+ };
+ 
+ static struct snd_soc_dai_driver sun8i_codec_dais[];
+@@ -644,6 +693,10 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
+ 			   SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK,
+ 			   bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV);
+ 
++	/* TODO: Implement clk driver for AC100 codec system clock */
++	if (scodec->ac100_regmap)
++		goto update_sample_rate;
++
+ 	/*
+ 	 * SYSCLK rate
+ 	 *
+@@ -666,6 +719,7 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
+ 		scodec->sysclk_refcnt++;
+ 	scodec->sysclk_rate = sysclk_rate;
+ 
++update_sample_rate:
+ 	aif->lrck_div_order = lrck_div_order;
+ 	aif->sample_rate = sample_rate;
+ 	aif->open_streams |= BIT(substream->stream);
+@@ -683,8 +737,11 @@ static int sun8i_codec_hw_free(struct snd_pcm_substream *substream,
+ 	if (aif->open_streams != BIT(substream->stream))
+ 		goto done;
+ 
+-	clk_rate_exclusive_put(scodec->clk_module);
+-	scodec->sysclk_refcnt--;
++	if (!scodec->ac100_regmap) {
++		clk_rate_exclusive_put(scodec->clk_module);
++		scodec->sysclk_refcnt--;
++	}
++
+ 	aif->lrck_div_order = 0;
+ 	aif->sample_rate = 0;
+ 
+@@ -957,8 +1014,6 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
+ 
+ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
+ 	/* System Clocks */
+-	SND_SOC_DAPM_CLOCK_SUPPLY("mod"),
+-
+ 	SND_SOC_DAPM_SUPPLY("AIF1CLK",
+ 			    SUN8I_SYSCLK_CTL,
+ 			    SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
+@@ -1119,8 +1174,6 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
+ 
+ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
+ 	/* Clock Routes */
+-	{ "AIF1CLK", NULL, "mod" },
+-
+ 	{ "SYSCLK", NULL, "AIF1CLK" },
+ 
+ 	{ "CLK AIF1", NULL, "AIF1CLK" },
+@@ -1290,6 +1343,16 @@ static const struct snd_soc_dapm_route sun8i_codec_legacy_routes[] = {
+ 	{ "AIF1 Slot 0 Right", NULL, "DACR" },
+ };
+ 
++static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets_sun8i[] = {
++	SND_SOC_DAPM_CLOCK_SUPPLY("mod"),
++};
++
++static const struct snd_soc_dapm_route sun8i_codec_dapm_routes_sun8i[] = {
++	{ "AIF1CLK", NULL, "mod" },
++};
++
++static int ac100_codec_component_probe(struct snd_soc_component *component);
++
+ static int sun8i_codec_component_probe(struct snd_soc_component *component)
+ {
+ 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
+@@ -1298,6 +1361,21 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component)
+ 
+ 	scodec->component = component;
+ 
++	if (scodec->ac100_regmap)
++                return ac100_codec_component_probe(component);
++
++	ret = snd_soc_dapm_new_controls(dapm,
++					sun8i_codec_dapm_widgets_sun8i,
++					ARRAY_SIZE(sun8i_codec_dapm_widgets_sun8i));
++	if (ret)
++		return ret;
++
++	ret = snd_soc_dapm_add_routes(dapm,
++				      sun8i_codec_dapm_routes_sun8i,
++				      ARRAY_SIZE(sun8i_codec_dapm_routes_sun8i));
++	if (ret)
++		return ret;
++
+ 	/* Add widgets for backward compatibility with old device trees. */
+ 	if (scodec->quirks->legacy_widgets) {
+ 		ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_legacy_widgets,
+@@ -1645,7 +1723,7 @@ static bool sun8i_codec_volatile_reg(struct device *dev, unsigned int reg)
+ 	return reg == SUN8I_HMIC_STS;
+ }
+ 
+-static const struct regmap_config sun8i_codec_regmap_config = {
++static struct regmap_config sun8i_codec_regmap_config = {
+ 	.reg_bits	= 32,
+ 	.reg_stride	= 4,
+ 	.val_bits	= 32,
+@@ -1655,12 +1733,124 @@ static const struct regmap_config sun8i_codec_regmap_config = {
+ 	.cache_type	= REGCACHE_FLAT,
+ };
+ 
++/* AC100 Codec Support (digital parts) */
++
++static int sun8i_codec_ac100_regmap_read(void *context,
++					 unsigned int reg, unsigned int *val)
++{
++	struct sun8i_codec *scodec = context;
++
++	return regmap_read(scodec->ac100_regmap, reg / 4, val);
++}
++
++static int sun8i_codec_ac100_regmap_write(void *context,
++					  unsigned int reg, unsigned int val)
++{
++	struct sun8i_codec *scodec = context;
++
++	return regmap_write(scodec->ac100_regmap, reg / 4, val);
++}
++
++static struct regmap_bus sun8i_codec_ac100_regmap_bus = {
++	.reg_write = sun8i_codec_ac100_regmap_write,
++	.reg_read = sun8i_codec_ac100_regmap_read,
++};
++
++static int ac100_codec_component_probe(struct snd_soc_component *component)
++{
++	struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
++
++        /*
++	 * The system clock(SYSCLK) of AC100 must be 512*fs(fs=48KHz or 44.1KHz)
++	 * Source clocks from the SoC.
++	 */
++
++        regmap_update_bits(scodec->ac100_regmap, AC100_SYSCLK_CTRL,
++                            AC100_SYSCLK_CTRL_I2S1CLK_SRC_MASK,
++                            AC100_SYSCLK_CTRL_I2S1CLK_SRC_MCLK1);
++        regmap_update_bits(scodec->ac100_regmap, AC100_SYSCLK_CTRL,
++                            AC100_SYSCLK_CTRL_I2S2CLK_SRC_MASK,
++                            AC100_SYSCLK_CTRL_I2S2CLK_SRC_MCLK1);
++        regmap_update_bits(scodec->ac100_regmap, AC100_SYSCLK_CTRL,
++                            AC100_SYSCLK_CTRL_SYSCLK_SRC_MASK,
++                            AC100_SYSCLK_CTRL_SYSCLK_SRC_I2S1CLK);
++
++	/* Program the default sample rate. */
++	return sun8i_codec_update_sample_rate(scodec);
++}
++
++static int sun8i_codec_probe_ac100(struct platform_device *pdev)
++{
++	struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
++	struct device* dev = &pdev->dev;
++	struct sun8i_codec *scodec;
++	int ret, i;
++
++	scodec = devm_kzalloc(dev, sizeof(*scodec), GFP_KERNEL);
++	if (!scodec)
++		return -ENOMEM;
++
++	scodec->quirks = of_device_get_match_data(&pdev->dev);
++	scodec->ac100_regmap = ac100->regmap;
++
++	platform_set_drvdata(pdev, scodec);
++
++	/*
++	 * Caching is done by the MFD regmap, so disable the mapped regmap
++	 * cache.
++	 */
++	sun8i_codec_regmap_config.cache_type = REGCACHE_NONE;
++
++	/*
++	 * We need to create a custom regmap_bus that will map reads/writes to
++	 * the MFD regmap
++	 */
++	scodec->regmap = __regmap_lockdep_wrapper(__devm_regmap_init,
++		 "ac100-regmap-codec", dev,
++		  &sun8i_codec_ac100_regmap_bus, scodec,
++		  &sun8i_codec_regmap_config);
++	if (IS_ERR(scodec->regmap))
++		return dev_err_probe(dev, PTR_ERR(scodec->regmap),
++				     "Failed to create our regmap\n");
++
++	for (i = 0; i < ARRAY_SIZE(scodec->supplies); i++)
++		scodec->supplies[i].supply = ac100_supply_names[i];
++
++        ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(scodec->supplies),
++                                      scodec->supplies);
++        if (ret)
++		return dev_err_probe(dev, ret, "Failed to request supplies\n");
++
++	ret = regulator_bulk_enable(ARRAY_SIZE(scodec->supplies),
++				    scodec->supplies);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to enable supplies\n");
++
++	ret = devm_snd_soc_register_component(dev, &sun8i_soc_component,
++					      sun8i_codec_dais,
++					      ARRAY_SIZE(sun8i_codec_dais));
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to register codec\n");
++		goto err_disable_reg;
++	}
++
++	return 0;
++
++err_disable_reg:
++	regulator_bulk_disable(ARRAY_SIZE(scodec->supplies),
++			       scodec->supplies);
++	return ret;
++}
++
+ static int sun8i_codec_probe(struct platform_device *pdev)
+ {
+ 	struct sun8i_codec *scodec;
+ 	void __iomem *base;
+ 	int ret;
+ 
++	if (of_device_is_compatible(pdev->dev.of_node, "x-powers,ac100-codec"))
++		return sun8i_codec_probe_ac100(pdev);
++
+ 	scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
+ 	if (!scodec)
+ 		return -ENOMEM;
+@@ -1728,6 +1918,14 @@ static int sun8i_codec_probe(struct platform_device *pdev)
+ 
+ static void sun8i_codec_remove(struct platform_device *pdev)
+ {
++	struct sun8i_codec *scodec = dev_get_drvdata(&pdev->dev);
++
++	if (scodec->ac100_regmap) {
++		regulator_bulk_disable(ARRAY_SIZE(scodec->supplies),
++				       scodec->supplies);
++		return;
++	}
++
+ 	pm_runtime_disable(&pdev->dev);
+ 	if (!pm_runtime_status_suspended(&pdev->dev))
+ 		sun8i_codec_runtime_suspend(&pdev->dev);
+@@ -1744,9 +1942,13 @@ static const struct sun8i_codec_quirks sun50i_a64_quirks = {
+ 	.jack_detection	= true,
+ };
+ 
++static const struct sun8i_codec_quirks ac100_quirks = {
++};
++
+ static const struct of_device_id sun8i_codec_of_match[] = {
+ 	{ .compatible = "allwinner,sun8i-a33-codec", .data = &sun8i_a33_quirks },
+ 	{ .compatible = "allwinner,sun50i-a64-codec", .data = &sun50i_a64_quirks },
++	{ .compatible = "x-powers,ac100-codec", .data = &ac100_quirks },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/spi-fixes.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/spi-fixes.patch
new file mode 100644
index 000000000000..d2338447c960
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/spi-fixes.patch
@@ -0,0 +1,66 @@
+From 857e4439586adcc8938330e98a03864ae8292fe4 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 25 Feb 2024 04:22:51 +0100
+Subject: spi fixes
+
+---
+ drivers/spi/spi-rockchip.c | 15 +++++----------
+ 1 file changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
+index 052dda891a40..ce5169943f69 100644
+--- a/drivers/spi/spi-rockchip.c
++++ b/drivers/spi/spi-rockchip.c
+@@ -767,7 +767,7 @@ static int rockchip_spi_enable_clocks(struct rockchip_spi *rs, bool en)
+ 		clk_disable_unprepare(rs->apb_pclk);
+ 	}
+ 
+-	rs->clk_enabled = en;
++	rs->clk_enabled = !!en;
+ 	return 0;
+ }
+ 
+@@ -814,6 +814,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 		return PTR_ERR(rs->spiclk);
+ 	}
+ 
++	rs->clk_enabled = true;
+ 	spi_enable_chip(rs, false);
+ 
+ 	ret = platform_get_irq(pdev, 0);
+@@ -922,7 +923,9 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 	pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
+ 	pm_runtime_use_autosuspend(&pdev->dev);
+ 	pm_runtime_set_active(&pdev->dev);
+-	pm_runtime_enable(&pdev->dev);
++	ret = devm_pm_runtime_enable(&pdev->dev);
++	if (ret < 0)
++		goto err_pm_disable;
+ 
+ 	ret = devm_spi_register_controller(&pdev->dev, ctlr);
+ 	if (ret < 0) {
+@@ -933,8 +936,6 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 	return 0;
+ 
+ err_pm_disable:
+-	pm_runtime_dont_use_autosuspend(&pdev->dev);
+-	pm_runtime_disable(&pdev->dev);
+ 	if (ctlr->dma_rx)
+ 		dma_release_channel(ctlr->dma_rx);
+ err_free_dma_tx:
+@@ -949,12 +950,6 @@ static void rockchip_spi_remove(struct platform_device *pdev)
+ 	struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
+ 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
+ 
+-	pm_runtime_get_sync(&pdev->dev);
+-	//pm_runtime_dont_use_autosuspend(&pdev->dev);
+-	pm_runtime_put_noidle(&pdev->dev);
+-	pm_runtime_disable(&pdev->dev);
+-	pm_runtime_set_suspended(&pdev->dev);
+-
+ 	if (ctlr->dma_tx)
+ 		dma_release_channel(ctlr->dma_tx);
+ 	if (ctlr->dma_rx)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch
new file mode 100644
index 000000000000..f0da4cd6e8fe
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch
@@ -0,0 +1,274 @@
+From bac865dc276e6644a9f047ace572bae0bd23386b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 4 Nov 2023 18:22:31 +0100
+Subject: spi: rockchip: Fix runtime PM and other issues
+
+The driver didn't bother with proper error handling, or clock resource
+management, leading to warnings during suspend/resume.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/spi/spi-rockchip.c | 121 ++++++++++++++++++++-----------------
+ 1 file changed, 66 insertions(+), 55 deletions(-)
+
+diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
+index e1ecd96c7858..052dda891a40 100644
+--- a/drivers/spi/spi-rockchip.c
++++ b/drivers/spi/spi-rockchip.c
+@@ -196,6 +196,8 @@ struct rockchip_spi {
+ 	bool cs_high_supported; /* native CS supports active-high polarity */
+ 
+ 	struct spi_transfer *xfer; /* Store xfer temporarily */
++
++	bool clk_enabled;
+ };
+ 
+ static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
+@@ -740,6 +742,35 @@ static int rockchip_spi_setup(struct spi_device *spi)
+ 	return 0;
+ }
+ 
++static int rockchip_spi_enable_clocks(struct rockchip_spi *rs, bool en)
++{
++	int ret;
++
++        if (!!en == rs->clk_enabled)
++		return 0;
++
++	if (en) {
++		ret = clk_prepare_enable(rs->apb_pclk);
++		if (ret < 0) {
++			dev_err(rs->dev, "Failed to enable apb_pclk\n");
++			return ret;
++		}
++
++		ret = clk_prepare_enable(rs->spiclk);
++		if (ret < 0) {
++			dev_err(rs->dev, "Failed to enable spiclk\n");
++			clk_disable_unprepare(rs->apb_pclk);
++			return ret;
++		}
++	} else {
++		clk_disable_unprepare(rs->spiclk);
++		clk_disable_unprepare(rs->apb_pclk);
++	}
++
++	rs->clk_enabled = en;
++	return 0;
++}
++
+ static int rockchip_spi_probe(struct platform_device *pdev)
+ {
+ 	int ret;
+@@ -753,10 +784,10 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 	target_mode = of_property_read_bool(np, "spi-slave");
+ 
+ 	if (target_mode)
+-		ctlr = spi_alloc_target(&pdev->dev,
++		ctlr = devm_spi_alloc_target(&pdev->dev,
+ 				sizeof(struct rockchip_spi));
+ 	else
+-		ctlr = spi_alloc_host(&pdev->dev,
++		ctlr = devm_spi_alloc_host(&pdev->dev,
+ 				sizeof(struct rockchip_spi));
+ 
+ 	if (!ctlr)
+@@ -768,35 +799,31 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 
+ 	/* Get basic io resource and map it */
+ 	rs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
+-	if (IS_ERR(rs->regs)) {
+-		ret =  PTR_ERR(rs->regs);
+-		goto err_put_ctlr;
+-	}
++	if (IS_ERR(rs->regs))
++		return PTR_ERR(rs->regs);
+ 
+ 	rs->apb_pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
+ 	if (IS_ERR(rs->apb_pclk)) {
+ 		dev_err(&pdev->dev, "Failed to get apb_pclk\n");
+-		ret = PTR_ERR(rs->apb_pclk);
+-		goto err_put_ctlr;
++		return PTR_ERR(rs->apb_pclk);
+ 	}
+ 
+ 	rs->spiclk = devm_clk_get_enabled(&pdev->dev, "spiclk");
+ 	if (IS_ERR(rs->spiclk)) {
+ 		dev_err(&pdev->dev, "Failed to get spi_pclk\n");
+-		ret = PTR_ERR(rs->spiclk);
+-		goto err_put_ctlr;
++		return PTR_ERR(rs->spiclk);
+ 	}
+ 
+ 	spi_enable_chip(rs, false);
+ 
+ 	ret = platform_get_irq(pdev, 0);
+ 	if (ret < 0)
+-		goto err_put_ctlr;
++		return ret;
+ 
+ 	ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
+ 			IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
+ 	if (ret)
+-		goto err_put_ctlr;
++		return ret;
+ 
+ 	rs->dev = &pdev->dev;
+ 	rs->freq = clk_get_rate(rs->spiclk);
+@@ -821,15 +848,9 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 	rs->fifo_len = get_fifo_len(rs);
+ 	if (!rs->fifo_len) {
+ 		dev_err(&pdev->dev, "Failed to get fifo length\n");
+-		ret = -EINVAL;
+-		goto err_put_ctlr;
++		return -EINVAL;
+ 	}
+ 
+-	pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
+-	pm_runtime_use_autosuspend(&pdev->dev);
+-	pm_runtime_set_active(&pdev->dev);
+-	pm_runtime_enable(&pdev->dev);
+-
+ 	ctlr->auto_runtime_pm = true;
+ 	ctlr->bus_num = pdev->id;
+ 	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
+@@ -862,10 +883,8 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 	ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
+ 	if (IS_ERR(ctlr->dma_tx)) {
+ 		/* Check tx to see if we need defer probing driver */
+-		if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
+-			ret = -EPROBE_DEFER;
+-			goto err_disable_pm_runtime;
+-		}
++		if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
+ 		dev_warn(rs->dev, "Failed to request TX DMA channel\n");
+ 		ctlr->dma_tx = NULL;
+ 	}
+@@ -900,24 +919,27 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ 		break;
+ 	}
+ 
++	pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
++	pm_runtime_use_autosuspend(&pdev->dev);
++	pm_runtime_set_active(&pdev->dev);
++	pm_runtime_enable(&pdev->dev);
++
+ 	ret = devm_spi_register_controller(&pdev->dev, ctlr);
+ 	if (ret < 0) {
+ 		dev_err(&pdev->dev, "Failed to register controller\n");
+-		goto err_free_dma_rx;
++		goto err_pm_disable;
+ 	}
+ 
+ 	return 0;
+ 
+-err_free_dma_rx:
++err_pm_disable:
++	pm_runtime_dont_use_autosuspend(&pdev->dev);
++	pm_runtime_disable(&pdev->dev);
+ 	if (ctlr->dma_rx)
+ 		dma_release_channel(ctlr->dma_rx);
+ err_free_dma_tx:
+ 	if (ctlr->dma_tx)
+ 		dma_release_channel(ctlr->dma_tx);
+-err_disable_pm_runtime:
+-	pm_runtime_disable(&pdev->dev);
+-err_put_ctlr:
+-	spi_controller_put(ctlr);
+ 
+ 	return ret;
+ }
+@@ -925,9 +947,10 @@ static int rockchip_spi_probe(struct platform_device *pdev)
+ static void rockchip_spi_remove(struct platform_device *pdev)
+ {
+ 	struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
++	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
+ 
+ 	pm_runtime_get_sync(&pdev->dev);
+-
++	//pm_runtime_dont_use_autosuspend(&pdev->dev);
+ 	pm_runtime_put_noidle(&pdev->dev);
+ 	pm_runtime_disable(&pdev->dev);
+ 	pm_runtime_set_suspended(&pdev->dev);
+@@ -937,7 +960,7 @@ static void rockchip_spi_remove(struct platform_device *pdev)
+ 	if (ctlr->dma_rx)
+ 		dma_release_channel(ctlr->dma_rx);
+ 
+-	spi_controller_put(ctlr);
++	rockchip_spi_enable_clocks(rs, true);
+ }
+ 
+ #ifdef CONFIG_PM_SLEEP
+@@ -951,8 +974,8 @@ static int rockchip_spi_suspend(struct device *dev)
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	clk_disable_unprepare(rs->spiclk);
+-	clk_disable_unprepare(rs->apb_pclk);
++	pm_runtime_disable(dev);
++	rockchip_spi_enable_clocks(rs, false);
+ 
+ 	pinctrl_pm_select_sleep_state(dev);
+ 
+@@ -967,19 +990,17 @@ static int rockchip_spi_resume(struct device *dev)
+ 
+ 	pinctrl_pm_select_default_state(dev);
+ 
+-	ret = clk_prepare_enable(rs->apb_pclk);
+-	if (ret < 0)
+-		return ret;
++	if (!pm_runtime_status_suspended(dev)) {
++		ret = rockchip_spi_enable_clocks(rs, true);
++		if (ret < 0)
++			return ret;
++	}
+ 
+-	ret = clk_prepare_enable(rs->spiclk);
+-	if (ret < 0)
+-		clk_disable_unprepare(rs->apb_pclk);
++	pm_runtime_enable(dev);
+ 
+ 	ret = spi_controller_resume(ctlr);
+-	if (ret < 0) {
+-		clk_disable_unprepare(rs->spiclk);
+-		clk_disable_unprepare(rs->apb_pclk);
+-	}
++	if (ret < 0)
++		return ret;
+ 
+ 	return 0;
+ }
+@@ -991,27 +1012,17 @@ static int rockchip_spi_runtime_suspend(struct device *dev)
+ 	struct spi_controller *ctlr = dev_get_drvdata(dev);
+ 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
+ 
+-	clk_disable_unprepare(rs->spiclk);
+-	clk_disable_unprepare(rs->apb_pclk);
++	rockchip_spi_enable_clocks(rs, false);
+ 
+ 	return 0;
+ }
+ 
+ static int rockchip_spi_runtime_resume(struct device *dev)
+ {
+-	int ret;
+ 	struct spi_controller *ctlr = dev_get_drvdata(dev);
+ 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
+ 
+-	ret = clk_prepare_enable(rs->apb_pclk);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = clk_prepare_enable(rs->spiclk);
+-	if (ret < 0)
+-		clk_disable_unprepare(rs->apb_pclk);
+-
+-	return 0;
++	return rockchip_spi_enable_clocks(rs, true);
+ }
+ #endif /* CONFIG_PM */
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
new file mode 100644
index 000000000000..441aa1f52f49
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
@@ -0,0 +1,150 @@
+From 3fcbbebcc5461c7b6eb523b030f64711d3fc16ca Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 2 Sep 2019 14:51:17 +0200
+Subject: sunxi: Use dev_err_probe to handle EPROBE_DEFER errors
+
+This makes it easier to debug EPROBE_DEFER issues via debugfs.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/kernel/topology.c                    |  2 +-
+ drivers/gpu/drm/panel/panel-sitronix-st7703.c |  2 +-
+ drivers/i2c/busses/i2c-gpio.c                 | 11 +++++++++--
+ drivers/phy/allwinner/phy-sun4i-usb.c         | 16 ++++++++++------
+ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c   |  6 ++++--
+ 5 files changed, 25 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
+index ef0058de432b..b87be5d007bf 100644
+--- a/arch/arm/kernel/topology.c
++++ b/arch/arm/kernel/topology.c
+@@ -121,7 +121,7 @@ static void __init parse_dt_topology(void)
+ 
+ 		rate = of_get_property(cn, "clock-frequency", &len);
+ 		if (!rate || len != 4) {
+-			pr_err("%pOF missing clock-frequency property\n", cn);
++			//pr_err("%pOF missing clock-frequency property\n", cn);
+ 			continue;
+ 		}
+ 
+diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+index c63a9b8c599d..7c942d46fe03 100644
+--- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+@@ -858,7 +858,7 @@ static int st7703_probe(struct mipi_dsi_device *dsi)
+ 
+ 	ret = mipi_dsi_attach(dsi);
+ 	if (ret < 0) {
+-		dev_err(dev, "mipi_dsi_attach failed (%d). Is host ready?\n", ret);
++		dev_err_probe(dev, ret, "mipi_dsi_attach failed\n");
+ 		drm_panel_remove(&ctx->panel);
+ 		return ret;
+ 	}
+diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
+index 4f1411b1a775..ad9399376a09 100644
+--- a/drivers/i2c/busses/i2c-gpio.c
++++ b/drivers/i2c/busses/i2c-gpio.c
+@@ -314,6 +314,13 @@ static struct gpio_desc *i2c_gpio_get_desc(struct device *dev,
+ 		return retdesc;
+ 	}
+ 
++	/* return early so that EPROBE_DEFER is not ignored on named gpios */
++	if (PTR_ERR(retdesc) == -EPROBE_DEFER) {
++		dev_err_probe(dev, PTR_ERR(retdesc),
++			      "error trying to get descriptor\n");
++		return retdesc;
++	}
++
+ 	retdesc = devm_gpiod_get_index(dev, NULL, index, gflags);
+ 	if (!IS_ERR(retdesc)) {
+ 		dev_dbg(dev, "got GPIO from index %u\n", index);
+@@ -330,8 +337,8 @@ static struct gpio_desc *i2c_gpio_get_desc(struct device *dev,
+ 	if (ret == -ENOENT)
+ 		retdesc = ERR_PTR(-EPROBE_DEFER);
+ 
+-	if (PTR_ERR(retdesc) != -EPROBE_DEFER)
+-		dev_err(dev, "error trying to get descriptor: %d\n", ret);
++	dev_err_probe(dev, PTR_ERR(retdesc),
++		      "error trying to get descriptor\n");
+ 
+ 	return retdesc;
+ }
+diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
+index 9b6b68eb00f8..be63d60ce738 100644
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -775,14 +775,16 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 	data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det",
+ 						    GPIOD_IN);
+ 	if (IS_ERR(data->id_det_gpio)) {
+-		dev_err(dev, "Couldn't request ID GPIO\n");
++		dev_err_probe(dev, PTR_ERR(data->id_det_gpio),
++			      "Couldn't request ID GPIO\n");
+ 		return PTR_ERR(data->id_det_gpio);
+ 	}
+ 
+ 	data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det",
+ 						      GPIOD_IN);
+ 	if (IS_ERR(data->vbus_det_gpio)) {
+-		dev_err(dev, "Couldn't request VBUS detect GPIO\n");
++		dev_err_probe(dev, PTR_ERR(data->vbus_det_gpio),
++			      "Couldn't request VBUS detect GPIO\n");
+ 		return PTR_ERR(data->vbus_det_gpio);
+ 	}
+ 
+@@ -790,7 +792,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
+ 						     "usb0_vbus_power-supply");
+ 		if (IS_ERR(data->vbus_power_supply)) {
+-			dev_err(dev, "Couldn't get the VBUS power supply\n");
++			dev_err_probe(dev, PTR_ERR(data->vbus_power_supply),
++				      "Couldn't get the VBUS power supply\n");
+ 			return PTR_ERR(data->vbus_power_supply);
+ 		}
+ 
+@@ -823,8 +826,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		phy->vbus = devm_regulator_get_optional(dev, name);
+ 		if (IS_ERR(phy->vbus)) {
+ 			if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
+-				dev_err(dev,
+-					"Couldn't get regulator %s... Deferring probe\n",
++				dev_err_probe(dev, PTR_ERR(phy->vbus),
++					"Couldn't get regulator %s\n",
+ 					name);
+ 				return -EPROBE_DEFER;
+ 			}
+@@ -839,7 +842,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 
+ 		phy->clk = devm_clk_get(dev, name);
+ 		if (IS_ERR(phy->clk)) {
+-			dev_err(dev, "failed to get clock %s\n", name);
++			dev_err_probe(dev, PTR_ERR(phy->clk),
++				      "failed to get clock %s\n", name);
+ 			return PTR_ERR(phy->clk);
+ 		}
+ 
+diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+index a19a27cea860..0107514e7d2b 100644
+--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
++++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+@@ -584,13 +584,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
+ 	dphy->regs = devm_regmap_init_mmio_clk(&pdev->dev, "bus",
+ 					       regs, &sun6i_dphy_regmap_config);
+ 	if (IS_ERR(dphy->regs)) {
+-		dev_err(&pdev->dev, "Couldn't create the DPHY encoder regmap\n");
++		dev_err_probe(&pdev->dev, PTR_ERR(dphy->regs),
++			      "Couldn't create the DPHY encoder regmap\n");
+ 		return PTR_ERR(dphy->regs);
+ 	}
+ 
+ 	dphy->reset = devm_reset_control_get_shared(&pdev->dev, NULL);
+ 	if (IS_ERR(dphy->reset)) {
+-		dev_err(&pdev->dev, "Couldn't get our reset line\n");
++		dev_err_probe(&pdev->dev, PTR_ERR(dphy->reset),
++			      "Couldn't get our reset line\n");
+ 		return PTR_ERR(dphy->reset);
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
new file mode 100644
index 000000000000..991ae81e6698
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
@@ -0,0 +1,88 @@
+From 751abefb2f3d4ea663da0fd30a7d01095f48b1f9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Jul 2020 12:21:14 +0200
+Subject: thermal: sun8i: Be loud when probe fails
+
+I noticed several mobile Linux distributions failing to enable the
+thermal regulation correctly, because the kernel is silent
+when thermal driver fails to probe. Add enough error reporting
+to debug issues and warn users in case thermal sensor is failing
+to probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/thermal/sun8i_thermal.c | 22 +++++++++++++++++++---
+ 1 file changed, 19 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
+index 3203d8bd13a8..c6a82ef84aca 100644
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -308,8 +308,13 @@ static int sun8i_ths_calibrate(struct ths_device *tmdev)
+ 
+ 	calcell = nvmem_cell_get(dev, "calibration");
+ 	if (IS_ERR(calcell)) {
++		dev_err_probe(dev, PTR_ERR(calcell),
++			      "Failed to get calibration nvmem cell (%pe)\n",
++			      calcell);
++
+ 		if (PTR_ERR(calcell) == -EPROBE_DEFER)
+ 			return -EPROBE_DEFER;
++
+ 		/*
+ 		 * Even if the external calibration data stored in sid is
+ 		 * not accessible, the THS hardware can still work, although
+@@ -329,6 +334,8 @@ static int sun8i_ths_calibrate(struct ths_device *tmdev)
+ 	caldata = nvmem_cell_read(calcell, &callen);
+ 	if (IS_ERR(caldata)) {
+ 		ret = PTR_ERR(caldata);
++		dev_err(dev, "Failed to read calibration data (%pe)\n",
++			caldata);
+ 		goto out;
+ 	}
+ 
+@@ -386,13 +393,17 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
+ 		return PTR_ERR(base);
+ 
+ 	tmdev->regmap = devm_regmap_init_mmio(dev, base, &config);
+-	if (IS_ERR(tmdev->regmap))
++	if (IS_ERR(tmdev->regmap)) {
++		dev_err(dev, "Failed to init regmap (%pe)\n", tmdev->regmap);
+ 		return PTR_ERR(tmdev->regmap);
++	}
+ 
+ 	if (tmdev->chip->has_bus_clk_reset) {
+ 		tmdev->reset = devm_reset_control_get(dev, NULL);
+-		if (IS_ERR(tmdev->reset))
++		if (IS_ERR(tmdev->reset)) {
++			dev_err(dev, "Failed to get reset (%pe)\n", tmdev->reset);
+ 			return PTR_ERR(tmdev->reset);
++		}
+ 
+ 		ret = reset_control_deassert(tmdev->reset);
+ 		if (ret)
+@@ -543,6 +554,9 @@ static int sun8i_ths_register(struct ths_device *tmdev)
+ 		if (IS_ERR(tmdev->sensor[i].tzd)) {
+ 			if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
+ 				return PTR_ERR(tmdev->sensor[i].tzd);
++			dev_err(tmdev->dev,
++				"Failed to register sensor %d (%pe)\n",
++				i, tmdev->sensor[i].tzd);
+ 			continue;
+ 		}
+ 
+@@ -591,8 +605,10 @@ static int sun8i_ths_probe(struct platform_device *pdev)
+ 	ret = devm_request_threaded_irq(dev, irq, NULL,
+ 					sun8i_irq_thread,
+ 					IRQF_ONESHOT, "ths", tmdev);
+-	if (ret)
++	if (ret) {
++		dev_err(dev, "Failed to request irq (%d)\n", ret);
+ 		return ret;
++	}
+ 
+ 	return 0;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
new file mode 100644
index 000000000000..3b378603133b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
@@ -0,0 +1,206 @@
+From 643ea6c2a19f6bec6bcc48881402b4e90959cf6b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 7 Sep 2023 14:07:26 +0200
+Subject: usb: gadget: Fix dangling pointer in netdev private data
+
+Some USB drivers destroy and re-create the gadget regularly. This
+leads to stale gadget pointer in gether_* using USB gadget functions
+(ecm, eem, ncm, rndis, etc.).
+
+Don't parent the netdev to the gadget device, and set gadget to
+NULL in function unbind callback, to avoid potential user-after-free
+issues.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/gadget/function/f_ecm.c    |  6 +++++-
+ drivers/usb/gadget/function/f_eem.c    | 10 +++++++++-
+ drivers/usb/gadget/function/f_ncm.c    |  4 ++++
+ drivers/usb/gadget/function/f_rndis.c  | 13 +++++++++++--
+ drivers/usb/gadget/function/f_subset.c | 10 +++++++++-
+ drivers/usb/gadget/function/u_ether.c  |  4 ----
+ 6 files changed, 38 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/gadget/function/f_ecm.c b/drivers/usb/gadget/function/f_ecm.c
+index f55f60639e42..e331cc64390b 100644
+--- a/drivers/usb/gadget/function/f_ecm.c
++++ b/drivers/usb/gadget/function/f_ecm.c
+@@ -907,7 +907,9 @@ static void ecm_free(struct usb_function *f)
+ 
+ static void ecm_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
+-	struct f_ecm		*ecm = func_to_ecm(f);
++	struct f_ecm *ecm = func_to_ecm(f);
++	struct f_ecm_opts *opts = container_of(f->fi, struct f_ecm_opts,
++					       func_inst);
+ 
+ 	DBG(c->cdev, "ecm unbind\n");
+ 
+@@ -920,6 +922,8 @@ static void ecm_unbind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	kfree(ecm->notify_req->buf);
+ 	usb_ep_free_request(ecm->notify, ecm->notify_req);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *ecm_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_eem.c b/drivers/usb/gadget/function/f_eem.c
+index 3b445bd88498..6382cd138d20 100644
+--- a/drivers/usb/gadget/function/f_eem.c
++++ b/drivers/usb/gadget/function/f_eem.c
+@@ -260,9 +260,12 @@ static int eem_bind(struct usb_configuration *c, struct usb_function *f)
+ 	 * with list_for_each_entry, so we assume no race condition
+ 	 * with regard to eem_opts->bound access
+ 	 */
++	mutex_lock(&eem_opts->lock);
++	gether_set_gadget(eem_opts->net, cdev->gadget);
++	mutex_unlock(&eem_opts->lock);
++
+ 	if (!eem_opts->bound) {
+ 		mutex_lock(&eem_opts->lock);
+-		gether_set_gadget(eem_opts->net, cdev->gadget);
+ 		status = gether_register_netdev(eem_opts->net);
+ 		mutex_unlock(&eem_opts->lock);
+ 		if (status)
+@@ -635,9 +638,14 @@ static void eem_free(struct usb_function *f)
+ 
+ static void eem_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
++	struct f_eem_opts *opts = container_of(f->fi, struct f_eem_opts,
++					       func_inst);
++
+ 	DBG(c->cdev, "eem unbind\n");
+ 
+ 	usb_free_all_descriptors(f);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *eem_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c
+index 0acc32ed9960..5e8659050d36 100644
+--- a/drivers/usb/gadget/function/f_ncm.c
++++ b/drivers/usb/gadget/function/f_ncm.c
+@@ -1728,6 +1728,8 @@ static void ncm_free(struct usb_function *f)
+ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
+ 	struct f_ncm *ncm = func_to_ncm(f);
++	struct f_ncm_opts *opts = container_of(f->fi, struct f_ncm_opts,
++					       func_inst);
+ 
+ 	DBG(c->cdev, "ncm unbind\n");
+ 
+@@ -1746,6 +1748,8 @@ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	kfree(ncm->notify_req->buf);
+ 	usb_ep_free_request(ncm->notify, ncm->notify_req);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *ncm_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_rndis.c b/drivers/usb/gadget/function/f_rndis.c
+index b47f99d17ee9..a15dfb8e6f01 100644
+--- a/drivers/usb/gadget/function/f_rndis.c
++++ b/drivers/usb/gadget/function/f_rndis.c
+@@ -688,9 +688,14 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f)
+ 	 * with list_for_each_entry, so we assume no race condition
+ 	 * with regard to rndis_opts->bound access
+ 	 */
++	mutex_lock(&rndis_opts->lock);
++	gether_set_gadget(rndis_opts->net, cdev->gadget);
++	mutex_unlock(&rndis_opts->lock);
++
+ 	if (!rndis_opts->bound) {
+-		gether_set_gadget(rndis_opts->net, cdev->gadget);
++		mutex_lock(&rndis_opts->lock);
+ 		status = gether_register_netdev(rndis_opts->net);
++		mutex_unlock(&rndis_opts->lock);
+ 		if (status)
+ 			goto fail;
+ 		rndis_opts->bound = true;
+@@ -954,7 +959,9 @@ static void rndis_free(struct usb_function *f)
+ 
+ static void rndis_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
+-	struct f_rndis		*rndis = func_to_rndis(f);
++	struct f_rndis *rndis = func_to_rndis(f);
++	struct f_rndis_opts *opts = container_of(f->fi, struct f_rndis_opts,
++						 func_inst);
+ 
+ 	kfree(f->os_desc_table);
+ 	f->os_desc_n = 0;
+@@ -962,6 +969,8 @@ static void rndis_unbind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	kfree(rndis->notify_req->buf);
+ 	usb_ep_free_request(rndis->notify, rndis->notify_req);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *rndis_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_subset.c b/drivers/usb/gadget/function/f_subset.c
+index 8ae9689ef2a0..70448dd67812 100644
+--- a/drivers/usb/gadget/function/f_subset.c
++++ b/drivers/usb/gadget/function/f_subset.c
+@@ -308,9 +308,12 @@ geth_bind(struct usb_configuration *c, struct usb_function *f)
+ 	 * with list_for_each_entry, so we assume no race condition
+ 	 * with regard to gether_opts->bound access
+ 	 */
++	mutex_lock(&gether_opts->lock);
++	gether_set_gadget(gether_opts->net, cdev->gadget);
++	mutex_unlock(&gether_opts->lock);
++
+ 	if (!gether_opts->bound) {
+ 		mutex_lock(&gether_opts->lock);
+-		gether_set_gadget(gether_opts->net, cdev->gadget);
+ 		status = gether_register_netdev(gether_opts->net);
+ 		mutex_unlock(&gether_opts->lock);
+ 		if (status)
+@@ -456,8 +459,13 @@ static void geth_free(struct usb_function *f)
+ 
+ static void geth_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
++	struct f_gether_opts *opts = container_of(f->fi, struct f_gether_opts,
++						  func_inst);
++
+ 	geth_string_defs[0].id = 0;
+ 	usb_free_all_descriptors(f);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *geth_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c
+index 444212c0b5a9..079162b0b20e 100644
+--- a/drivers/usb/gadget/function/u_ether.c
++++ b/drivers/usb/gadget/function/u_ether.c
+@@ -787,7 +787,6 @@ struct eth_dev *gether_setup_name(struct usb_gadget *g,
+ 	net->max_mtu = GETHER_MAX_MTU_SIZE;
+ 
+ 	dev->gadget = g;
+-	SET_NETDEV_DEV(net, &g->dev);
+ 	SET_NETDEV_DEVTYPE(net, &gadget_type);
+ 
+ 	status = register_netdev(net);
+@@ -860,8 +859,6 @@ int gether_register_netdev(struct net_device *net)
+ 	struct usb_gadget *g;
+ 	int status;
+ 
+-	if (!net->dev.parent)
+-		return -EINVAL;
+ 	dev = netdev_priv(net);
+ 	g = dev->gadget;
+ 
+@@ -892,7 +889,6 @@ void gether_set_gadget(struct net_device *net, struct usb_gadget *g)
+ 
+ 	dev = netdev_priv(net);
+ 	dev->gadget = g;
+-	SET_NETDEV_DEV(net, &g->dev);
+ }
+ EXPORT_SYMBOL_GPL(gether_set_gadget);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
new file mode 100644
index 000000000000..9d59eb99e8d0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
@@ -0,0 +1,107 @@
+From acc0d5fdd7c8d3dc45828263f774c1130b8886ea Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 6 Mar 2023 01:19:52 +0100
+Subject: usb: musb: sunxi: Avoid enabling host side code on SoCs where it's
+ not used
+
+For some sunxi SoCs host side code is active but unused, because
+phy re-routes USB handling to a regular EHCI/OHCI driver.
+
+When host side code of musb is left initialized it sometimes
+interferes with suspend to RAM. Disabling the host side code
+on SoCs that re-route host mode to a regular *HCI hardware
+block fixes the issue.
+
+Issue: https://gitlab.com/postmarketOS/pmaports/-/issues/1478
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/musb/musb_core.c | 10 ++++++++++
+ drivers/usb/musb/sunxi.c     | 30 +++++++++++++++++++++++-------
+ 2 files changed, 33 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index b24adb5b399f..8b3ad9101180 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -975,6 +975,16 @@ static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
+ 	case OTG_STATE_B_IDLE:
+ 		musb_g_disconnect(musb);
+ 		break;
++	case OTG_STATE_A_WAIT_VRISE:
++		/*
++		 * For sunxi use case, where host side of the musb driver
++		 * is not used for host mode, we want to ignore
++		 * OTG_STATE_A_WAIT_VRISE state set in sunxi glue code
++		 * when transitioning to host mode on disconnect, in
++		 * order to not confuse the dmesg reader about possible
++		 * issues.
++		 */
++		break;
+ 	default:
+ 		WARNING("unhandled DISCONNECT transition (%s)\n",
+ 			musb_otg_state_string(musb));
+diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
+index d54283fd026b..7e7703de28a3 100644
+--- a/drivers/usb/musb/sunxi.c
++++ b/drivers/usb/musb/sunxi.c
+@@ -352,12 +352,6 @@ static int sunxi_musb_set_mode(struct musb *musb, u8 mode)
+ 	if (glue->phy_mode == new_mode)
+ 		return 0;
+ 
+-	if (musb->port_mode != MUSB_OTG) {
+-		dev_err(musb->controller->parent,
+-			"Error changing modes is only supported in dual role mode\n");
+-		return -EINVAL;
+-	}
+-
+ 	if (musb->port1_status & USB_PORT_STAT_ENABLE)
+ 		musb_root_disconnect(musb);
+ 
+@@ -676,13 +670,22 @@ static const struct musb_hdrc_config sunxi_musb_hdrc_config_4eps = {
+ 	.ram_bits	= SUNXI_MUSB_RAM_BITS,
+ };
+ 
++static const char * const sunxi_musb_host_rerouted_phys[] = {
++	"allwinner,sun8i-h3-usb-phy",
++	"allwinner,sun8i-r40-usb-phy",
++	"allwinner,sun8i-v3s-usb-phy",
++	"allwinner,sun50i-a64-usb-phy",
++	"allwinner,sun50i-h6-usb-phy",
++	NULL,
++};
++
+ static int sunxi_musb_probe(struct platform_device *pdev)
+ {
+ 	struct musb_hdrc_platform_data	pdata;
+ 	struct platform_device_info	pinfo;
+ 	struct sunxi_glue		*glue;
+-	struct device_node		*np = pdev->dev.of_node;
+ 	const struct sunxi_musb_cfg	*cfg;
++	struct device_node		*np = pdev->dev.of_node, *phy_np;
+ 	int ret;
+ 
+ 	if (!np) {
+@@ -763,6 +766,19 @@ static int sunxi_musb_probe(struct platform_device *pdev)
+ 		return dev_err_probe(&pdev->dev, PTR_ERR(glue->phy),
+ 				     "Error getting phy\n");
+ 
++	/*
++	 * Host mode is handled outside of the musb driver on some allwinner
++	 * SoCs. We don't need musb host side code to be enabled at all.
++	 * In fact it causes occasional issues with suspend to ram, when
++	 * the host side code is enabled and unused (due to phy being re-routed
++	 * to a different *HCI controller).
++	 */
++	phy_np = glue->phy->dev.of_node;
++	if (of_device_compatible_match(phy_np, sunxi_musb_host_rerouted_phys)) {
++		dev_info(&pdev->dev, "Disabling musb host side code due to re-routed phy\n");
++		pdata.mode = MUSB_PERIPHERAL;
++	}
++
+ 	glue->usb_phy = usb_phy_generic_register();
+ 	if (IS_ERR(glue->usb_phy)) {
+ 		dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
new file mode 100644
index 000000000000..fd4bb5b1e0db
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
@@ -0,0 +1,33 @@
+From 8e8e354ba36e8a6aa2447f5492646ad205c14185 Mon Sep 17 00:00:00 2001
+From: Thomas Thorne <Thomas.Thorne@Net2Edge.com>
+Date: Tue, 20 Sep 2022 20:34:57 -0400
+Subject: usb: serial: option: add 'reset_resume' callback for WWAN devices
+
+This avoids the issue where the PPP modem does not reset correctly on resume,
+causing issues with incoming calls on suspend.
+
+Noted here: https://github.com/the-modem-distro/pinephone_modem_sdk/issues/97
+
+This is part of a larger patch:
+https://github.com/Quectel-Community/meta-quectel-community/commit/24adef2128f79b4d31490634438a917b3df462e2#diff-45dc5960ca2f1ef57139fe751587b3b043de9cca5864e2801210c00e75bd0780
+
+However the rest of the patch is not needed/already upstreamed.
+---
+ drivers/usb/serial/option.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
+index 8a5846d4adf6..65d7c2036fb8 100644
+--- a/drivers/usb/serial/option.c
++++ b/drivers/usb/serial/option.c
+@@ -2361,6 +2361,7 @@ static struct usb_serial_driver option_1port_device = {
+ #ifdef CONFIG_PM
+ 	.suspend           = usb_wwan_suspend,
+ 	.resume            = usb_wwan_resume,
++	.reset_resume	   = usb_wwan_resume,
+ #endif
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
new file mode 100644
index 000000000000..ac2140d7c2c2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
@@ -0,0 +1,98 @@
+From 00792199c990beb353b575bf83dd50f52c321b09 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 5 Sep 2022 00:56:07 +0200
+Subject: usb: typec: altmodes: displayport: Respect DP_CAP_RECEPTACLE bit
+
+DP_CAP_RECEPTACLE swaps the meaning of pin assignments. So eg.
+pin assignments for DFP_D plug are stored in DP_CAP_UFP_D_PIN_ASSIGN
+bits. Yes, it's slightly confusing. :)
+
+Make the kernel report lack of match in supported pin configurations
+between connected ports, so that the user is not confused why their
+USB-C dock doesn't have working Alt-DP mode, in case the dock returns
+wrong VDO.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/altmodes/displayport.c | 48 ++++++++++++++++++++++--
+ 1 file changed, 44 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c
+index 038dc51f429d..471f3ca268aa 100644
+--- a/drivers/usb/typec/altmodes/displayport.c
++++ b/drivers/usb/typec/altmodes/displayport.c
+@@ -116,11 +116,29 @@ static int dp_altmode_configure(struct dp_altmode *dp, u8 con)
+ 		/* Account for active cable capabilities */
+ 		if (dp->plug_prime)
+ 			pin_assign &= DP_CAP_UFP_D_PIN_ASSIGN(dp->plug_prime->vdo);
++
++		/*
++		 * The Display Port Alt mode standard is not publicly available,
++		 * so this is based on guesswork and real VDOs received from
++		 * receptacle based and plug based Type-C alt mode supporting
++		 * docks to make configuration work in practice:
++		 *
++		 * Plug (captive cable) based dock: port=c46 alt=c05
++		 * Recpetacle based dock: port=c46 alt=c0045
++		 *
++		pin_assign = DP_CAP_DFP_D_PIN_ASSIGN(dp->port->vdo);
++		pin_assign &= dp->alt->vdo & DP_CAP_RECEPTACLE ?
++			DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo) :
++			DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
++		 */
+ 		break;
+ 	default:
+ 		break;
+ 	}
+ 
++	dev_info(&dp->alt->dev, "con=%d pin_assign=%x (port=%x alt=%x)\n",
++		 (int)con, (unsigned)pin_assign, dp->port->vdo, dp->alt->vdo);
++
+ 	/* Determining the initial pin assignment. */
+ 	if (!DP_CONF_GET_PIN_ASSIGN(dp->data.conf)) {
+ 		/* Is USB together with DP preferred */
+@@ -726,15 +744,37 @@ int dp_altmode_probe(struct typec_altmode *alt)
+ 	struct typec_altmode *plug = typec_altmode_get_plug(alt, TYPEC_PLUG_SOP_P);
+ 	struct fwnode_handle *fwnode;
+ 	struct dp_altmode *dp;
++	u32 port_pins, alt_pins;
+ 
+ 	/* FIXME: Port can only be DFP_U. */
+ 
++	/*
++	 * When port is a receptacle DP_CAP_xFP_D_PIN_ASSIGN macros have the
++	 * regular meaning. When the port is a plug, the meaning is swapped.
++	 *
++	 * Check if we have any matching DFP_D<->UFP_D or UFP_D<->DFP_D pin assignment.
++	 */
++        port_pins = port->vdo & DP_CAP_RECEPTACLE ?
++		DP_CAP_DFP_D_PIN_ASSIGN(port->vdo) | DP_CAP_UFP_D_PIN_ASSIGN(port->vdo) << 8 :
++		DP_CAP_UFP_D_PIN_ASSIGN(port->vdo) | DP_CAP_DFP_D_PIN_ASSIGN(port->vdo) << 8;
++
++        alt_pins = alt->vdo & DP_CAP_RECEPTACLE ?
++		DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo) | DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo) << 8 :
++		DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo) | DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo) << 8;
++
++	/* Can't plug plug into a plug */
++	if (!(port->vdo & DP_CAP_RECEPTACLE) && !(alt->vdo & DP_CAP_RECEPTACLE)) {
++		dev_warn(&alt->dev, "Our Alt-DP VDO 0x%06x and peer port VDO 0x%06x are not compatible (both are reported as plugs!)\n",
++			 port->vdo, alt->vdo);
++		return -ENODEV;
++	}
++
+ 	/* Make sure we have compatiple pin configurations */
+-	if (!(DP_CAP_PIN_ASSIGN_DFP_D(port->vdo) &
+-	      DP_CAP_PIN_ASSIGN_UFP_D(alt->vdo)) &&
+-	    !(DP_CAP_PIN_ASSIGN_UFP_D(port->vdo) &
+-	      DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo)))
++	if (!(port_pins & alt_pins)) {
++		dev_warn(&alt->dev, "Our Alt-DP VDO 0x%06x and peer port VDO 0x%06x are not compatible (no shared pinconf %04x<->%04x (UUDD))\n",
++			 port->vdo, alt->vdo, port_pins, alt_pins);
+ 		return -ENODEV;
++	}
+ 
+ 	dp = devm_kzalloc(&alt->dev, sizeof(*dp), GFP_KERNEL);
+ 	if (!dp)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
new file mode 100644
index 000000000000..8e18ca5a6500
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
@@ -0,0 +1,2333 @@
+From c51837845b793f7f107c4c89189606619a61ef7d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 13 Feb 2020 15:37:25 +0100
+Subject: usb: typec: anx7688: Add driver for ANX7688 USB-C HDMI bridge
+
+The driver is now ready for some testing with more USB-C devices.
+It supports data and power role switching properly on all PinePhone
+variants, that have the HW mod: https://xnux.eu/devices/pp-usbc-fix.jpg.
+
+- fix possibly unbalanced connect/disconnect
+- better cabledet interrupt handling
+  - handle connect/disconnect in a workqueue
+  - debounce cabledet changes
+- send PDO to the right i2c address
+- proper error handling where it matters the most
+- proper locking
+- handle power supplies
+- handle inital connection/cable status after driver probe
+  not just on cabledet change
+- handle software interrupts from OCM
+- allow to update OCM firmware via sysfs
+- allow to dump OCM firmware via debugfs
+- allow to dump registers via debugfs
+- hook into allwinner usb phy driver to handle change in
+  data role (via usb_role_switch)
+- handle vbus/vconn enable/disable based on firmware
+  requests
+- proper cleanup of resources on driver unload
+
+Todo:
+- tell PMIC what USB input current limit to set based on
+  PD messages from firmware
+- add support for manual data/power role setting for devices
+  without the HW mod
+
+Signed-off-by: Martijn Braam <martijn@brixit.nl>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/Kconfig   |   12 +
+ drivers/usb/typec/Makefile  |    1 +
+ drivers/usb/typec/anx7688.c | 2237 +++++++++++++++++++++++++++++++++++
+ 3 files changed, 2250 insertions(+)
+ create mode 100644 drivers/usb/typec/anx7688.c
+
+diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig
+index 2f80c2792dbd..982b7c444a1f 100644
+--- a/drivers/usb/typec/Kconfig
++++ b/drivers/usb/typec/Kconfig
+@@ -52,6 +52,7 @@ source "drivers/usb/typec/ucsi/Kconfig"
+ 
+ source "drivers/usb/typec/tipd/Kconfig"
+ 
++
+ config TYPEC_ANX7411
+ 	tristate "Analogix ANX7411 Type-C DRP Port controller driver"
+ 	depends on I2C
+@@ -64,6 +65,17 @@ config TYPEC_ANX7411
+ 	  If you choose to build this driver as a dynamically linked module, the
+ 	  module will be called anx7411.ko.
+ 
++config TYPEC_ANX7688
++	tristate "Analogix ANX7688 Type-C DRP Port controller and mux driver"
++	depends on I2C
++	depends on USB_ROLE_SWITCH
++	help
++	  Say Y or M here if your system has Analogix ANX7688 Type-C Bridge
++	  controller driver.
++
++	  If you choose to build this driver as a dynamically linked module, the
++	  module will be called anx7688.ko.
++
+ config TYPEC_RT1719
+ 	tristate "Richtek RT1719 Sink Only Type-C controller driver"
+ 	depends on USB_ROLE_SWITCH || !USB_ROLE_SWITCH
+diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile
+index 7a368fea61bc..3f8ff94ad294 100644
+--- a/drivers/usb/typec/Makefile
++++ b/drivers/usb/typec/Makefile
+@@ -7,6 +7,7 @@ obj-$(CONFIG_TYPEC_TCPM)	+= tcpm/
+ obj-$(CONFIG_TYPEC_UCSI)	+= ucsi/
+ obj-$(CONFIG_TYPEC_TPS6598X)	+= tipd/
+ obj-$(CONFIG_TYPEC_ANX7411)	+= anx7411.o
++obj-$(CONFIG_TYPEC_ANX7688)	+= anx7688.o
+ obj-$(CONFIG_TYPEC_HD3SS3220)	+= hd3ss3220.o
+ obj-$(CONFIG_TYPEC_STUSB160X) 	+= stusb160x.o
+ obj-$(CONFIG_TYPEC_RT1719)	+= rt1719.o
+diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c
+new file mode 100644
+index 000000000000..fa1d3496af73
+--- /dev/null
++++ b/drivers/usb/typec/anx7688.c
+@@ -0,0 +1,2237 @@
++/*
++ * ANX7688 USB-C HDMI bridge/PD driver
++ *
++ * Warning, this driver is somewhat PinePhone specific.
++ *
++ * How this works:
++ * - this driver allows to program firmware into ANX7688 EEPROM, and
++ *   initialize it
++ * - it then communicates with the firmware running on the OCM (on-chip
++ *   microcontroller)
++ * - it detects whether there is cable plugged in or not and powers
++ *   up or down the ANX7688 based on that
++ * - when the cable is connected the firmware on the OCM will handle
++ *   the detection of the nature of the device on the other end
++ *   of the USB-C cable
++ * - this driver then communicates with the USB phy to let it swap
++ *   data roles accordingly
++ * - it also enables VBUS and VCONN regulators as appropriate
++ * - USB phy driver (Allwinner) needs to know whether to switch to
++ *   device or host mode, or whether to turn off
++ * - when the firmware detects SRC.1.5A or SRC.3.0A via CC pins
++ *   or something else via PD, it notifies this driver via software
++ *   interrupt and this driver will determine how to update the TypeC
++ *   port status and what input current limit is appropriate
++ * - input current limit determination happens 500ms after cable
++ *   insertion or hard reset (delay is necessary to determine whether
++ *   the remote end is PD capable or not)
++ * - this driver tells to the PMIC driver that the input current limit
++ *   needs to be changed
++ * - this driver also monitors PMIC status and re-sets the input current
++ *   limit if it changes for some reason (due to PMIC internal decision
++ *   making) (this is disabled for now)
++ *
++ * ANX7688 FW behavior as observed:
++ *
++ * - DO NOT SET MORE THAN 1 SINK CAPABILITY! Firmware will ignore what
++ *   you set and send hardcoded PDO_BATT 5-21V 30W message!
++ */
++
++#define DEBUG
++
++#include <linux/debugfs.h>
++#include <linux/delay.h>
++#include <linux/extcon-provider.h>
++#include <linux/firmware.h>
++#include <linux/gpio/consumer.h>
++#include <linux/i2c.h>
++#include <linux/interrupt.h>
++#include <linux/irqreturn.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_irq.h>
++#include <linux/power_supply.h>
++#include <linux/regulator/consumer.h>
++#include <linux/usb/pd.h>
++#include <linux/usb/role.h>
++#include <linux/usb/typec.h>
++
++#define DISABLE_OCM 0
++
++/* firmware regs */
++
++#define ANX7688_REG_VBUS_OFF_DELAY_TIME 0x22
++#define ANX7688_REG_FEATURE_CTRL        0x27
++#define ANX7688_REG_EEPROM_LOAD_STATUS1 0x11
++#define ANX7688_REG_EEPROM_LOAD_STATUS0 0x12
++#define ANX7688_REG_FW_VERSION1         0x15
++#define ANX7688_REG_FW_VERSION0         0x16
++
++#define ANX7688_EEPROM_FW_LOADED	0x01
++
++#define ANX7688_REG_STATUS_INT_MASK     0x17
++#define ANX7688_REG_STATUS_INT          0x28
++#define ANX7688_IRQS_RECEIVED_MSG       BIT(0)
++#define ANX7688_IRQS_RECEIVED_ACK       BIT(1)
++#define ANX7688_IRQS_VCONN_CHANGE       BIT(2)
++#define ANX7688_IRQS_VBUS_CHANGE        BIT(3)
++#define ANX7688_IRQS_CC_STATUS_CHANGE   BIT(4)
++#define ANX7688_IRQS_DATA_ROLE_CHANGE   BIT(5)
++
++#define ANX7688_REG_STATUS              0x29
++#define ANX7688_VCONN_STATUS            BIT(2) /* 0 = off  1 = on */
++#define ANX7688_VBUS_STATUS             BIT(3) /* 0 = off  1 = on */
++#define ANX7688_DATA_ROLE_STATUS        BIT(5) /* 0 = device 1 = host */
++
++#define ANX7688_REG_CC_STATUS           0x2a
++#define ANX7688_REG_TRY_UFP_TIMER       0x23
++#define ANX7688_REG_TIME_CTRL           0x24
++
++#define ANX7688_REG_MAX_VOLTAGE         0x1b
++#define ANX7688_REG_MAX_POWER           0x1c
++#define ANX7688_REG_MIN_POWER           0x1d
++#define ANX7688_REG_MAX_VOLTAGE_STATUS  0x1e
++#define ANX7688_REG_MAX_POWER_STATUS    0x1f
++
++#define ANX7688_SOFT_INT_MASK           0x7f
++
++/* tcpc regs */
++
++#define ANX7688_TCPC_REG_VENDOR_ID0     0x00
++#define ANX7688_TCPC_REG_VENDOR_ID1     0x01
++#define ANX7688_TCPC_REG_ALERT0         0x10
++#define ANX7688_TCPC_REG_ALERT1         0x11
++#define ANX7688_TCPC_REG_ALERT_MASK0    0x12
++#define ANX7688_TCPC_REG_ALERT_MASK1    0x13
++#define ANX7688_TCPC_REG_INTERFACE_SEND 0x30
++#define ANX7688_TCPC_REG_INTERFACE_RECV 0x51
++
++/* hw regs */
++
++#define ANX7688_REG_IRQ_EXT_SOURCE0     0x3e
++#define ANX7688_REG_IRQ_EXT_SOURCE1     0x4e
++#define ANX7688_REG_IRQ_EXT_SOURCE2     0x4f
++#define ANX7688_REG_IRQ_EXT_MASK0       0x3b
++#define ANX7688_REG_IRQ_EXT_MASK1       0x3c
++#define ANX7688_REG_IRQ_EXT_MASK2       0x3d
++#define ANX7688_REG_IRQ_SOURCE0         0x54
++#define ANX7688_REG_IRQ_SOURCE1         0x55
++#define ANX7688_REG_IRQ_SOURCE2         0x56
++#define ANX7688_REG_IRQ_MASK0           0x57
++#define ANX7688_REG_IRQ_MASK1           0x58
++#define ANX7688_REG_IRQ_MASK2           0x59
++
++#define ANX7688_IRQ2_SOFT_INT           BIT(2)
++
++#define ANX7688_REG_USBC_RESET_CTRL		0x05
++#define ANX7688_USBC_RESET_CTRL_OCM_RESET	BIT(4)
++
++//#define ANX7688_IRQ2_USB_PLUGIN         BIT(4)
++//#define ANX7688_REG_IRQ_STATUS          0x53
++
++/* ocm messages */
++
++#define ANX7688_OCM_MSG_PWR_SRC_CAP     0x00
++#define ANX7688_OCM_MSG_PWR_SNK_CAP     0x01
++#define ANX7688_OCM_MSG_DP_SNK_IDENTITY 0x02
++#define ANX7688_OCM_MSG_SVID            0x03
++#define ANX7688_OCM_MSG_GET_DP_SNK_CAP  0x04
++#define ANX7688_OCM_MSG_ACCEPT          0x05
++#define ANX7688_OCM_MSG_REJECT          0x06
++#define ANX7688_OCM_MSG_PSWAP_REQ       0x10
++#define ANX7688_OCM_MSG_DSWAP_REQ       0x11
++#define ANX7688_OCM_MSG_GOTO_MIN_REQ    0x12
++#define ANX7688_OCM_MSG_VCONN_SWAP_REQ  0x13
++#define ANX7688_OCM_MSG_VDM             0x14
++#define ANX7688_OCM_MSG_DP_SNK_CFG      0x15
++#define ANX7688_OCM_MSG_PWR_OBJ_REQ     0x16
++#define ANX7688_OCM_MSG_PD_STATUS_REQ   0x17
++#define ANX7688_OCM_MSG_DP_ALT_ENTER    0x19
++#define ANX7688_OCM_MSG_DP_ALT_EXIT     0x1a
++#define ANX7688_OCM_MSG_GET_SNK_CAP     0x1b
++#define ANX7688_OCM_MSG_RESPONSE_TO_REQ 0xf0
++#define ANX7688_OCM_MSG_SOFT_RST        0xf1
++#define ANX7688_OCM_MSG_HARD_RST        0xf2
++#define ANX7688_OCM_MSG_RESTART         0xf3
++
++static const char * const anx7688_supply_names[] = {
++	"avdd33",
++	"avdd18",
++	"dvdd18",
++	"avdd10",
++	"dvdd10",
++	"i2c",
++	"hdmi_vt",
++
++	"vconn", // power for VCONN1/VCONN2 switches
++	"vbus", // vbus power
++};
++
++#define ANX7688_NUM_SUPPLIES ARRAY_SIZE(anx7688_supply_names)
++#define ANX7688_NUM_ALWAYS_ON_SUPPLIES (ANX7688_NUM_SUPPLIES - 1)
++
++#define ANX7688_I2C_INDEX (ANX7688_NUM_SUPPLIES - 4)
++#define ANX7688_VCONN_INDEX (ANX7688_NUM_SUPPLIES - 2)
++#define ANX7688_VBUS_INDEX (ANX7688_NUM_SUPPLIES - 1)
++
++enum {
++	ANX7688_F_POWERED,
++	ANX7688_F_CONNECTED,
++	ANX7688_F_FW_FAILED,
++	ANX7688_F_PWRSUPPLY_CHANGE,
++	ANX7688_F_CURRENT_UPDATE,
++};
++
++struct anx7688 {
++	struct device *dev;
++	struct i2c_client *client;
++	struct i2c_client *client_tcpc;
++	struct regulator_bulk_data supplies[ANX7688_NUM_SUPPLIES];
++	struct power_supply *vbus_in_supply;
++	struct notifier_block vbus_in_nb;
++	int input_current_limit; // mA
++	struct gpio_desc *gpio_enable;
++	struct gpio_desc *gpio_reset;
++	struct gpio_desc *gpio_cabledet;
++
++	uint32_t src_caps[8];
++	unsigned n_src_caps;
++
++	uint32_t snk_caps[8];
++	unsigned n_snk_caps;
++
++	unsigned long flags[1];
++
++	struct delayed_work work;
++	struct timer_list work_timer;
++
++	struct mutex lock;
++	bool vbus_on, vconn_on;
++	bool pd_capable;
++	int pd_current_limit; // mA
++	ktime_t current_update_deadline;
++
++	struct typec_port *port;
++	struct typec_partner *partner;
++	struct usb_pd_identity partner_identity;
++	struct usb_role_switch *role_sw;
++	int pwr_role, data_role;
++
++	struct dentry *debug_root;
++
++	/* for debug */
++	int last_status;
++	int last_cc_status;
++	int last_dp_state;
++	int last_bc_result;
++
++	/* for HDMI HPD */
++	struct extcon_dev *extcon;
++	int last_extcon_state;
++};
++
++static const unsigned int anx7688_extcon_cable[] = {
++	EXTCON_DISP_HDMI,
++	EXTCON_NONE,
++};
++
++static int anx7688_reg_read(struct anx7688 *anx7688, u8 reg_addr)
++{
++	int ret;
++
++	ret = i2c_smbus_read_byte_data(anx7688->client, reg_addr);
++	if (ret < 0)
++		dev_err(anx7688->dev, "i2c read failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static int anx7688_reg_write(struct anx7688 *anx7688, u8 reg_addr, u8 value)
++{
++	int ret;
++
++	ret = i2c_smbus_write_byte_data(anx7688->client, reg_addr, value);
++	if (ret < 0)
++		dev_err(anx7688->dev, "i2c write failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static int anx7688_reg_update_bits(struct anx7688 *anx7688, u8 reg_addr,
++				   u8 mask, u8 value)
++{
++	int ret;
++
++	ret = anx7688_reg_read(anx7688, reg_addr);
++	if (ret < 0)
++		return ret;
++
++	ret &= ~mask;
++	ret |= value;
++
++	return anx7688_reg_write(anx7688, reg_addr, ret);
++}
++
++static int anx7688_tcpc_reg_read(struct anx7688 *anx7688, u8 reg_addr)
++{
++	int ret;
++
++	ret = i2c_smbus_read_byte_data(anx7688->client_tcpc, reg_addr);
++	if (ret < 0)
++		dev_err(anx7688->dev, "tcpc i2c read failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static int anx7688_tcpc_reg_write(struct anx7688 *anx7688, u8 reg_addr, u8 value)
++{
++	int ret;
++
++	ret = i2c_smbus_write_byte_data(anx7688->client_tcpc, reg_addr, value);
++	if (ret < 0)
++		dev_err(anx7688->dev, "tcpc i2c write failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static void anx7688_power_enable(struct anx7688 *anx7688)
++{
++	gpiod_set_value(anx7688->gpio_reset, 1);
++	gpiod_set_value(anx7688->gpio_enable, 1);
++
++	/* wait for power to stabilize and release reset */
++	msleep(10);
++	gpiod_set_value(anx7688->gpio_reset, 0);
++	udelay(2);
++
++	dev_dbg(anx7688->dev, "power enabled\n");
++
++	set_bit(ANX7688_F_POWERED, anx7688->flags);
++}
++
++static void anx7688_power_disable(struct anx7688 *anx7688)
++{
++	gpiod_set_value(anx7688->gpio_reset, 1);
++	msleep(5);
++	gpiod_set_value(anx7688->gpio_enable, 0);
++
++	dev_dbg(anx7688->dev, "power disabled\n");
++
++	clear_bit(ANX7688_F_POWERED, anx7688->flags);
++}
++
++static int anx7688_send_ocm_message(struct anx7688 *anx7688, int cmd,
++				    const u8 *data, int data_len)
++{
++	int ret = 0, i;
++	u8 pkt[32];
++
++	if (data_len > sizeof(pkt) - 3) {
++		dev_dbg(anx7688->dev,
++			"invalid ocm message length cmd=0x%02x len=%d\n",
++			cmd, data_len);
++		return -EINVAL;
++	}
++
++	// prepare pd packet
++	pkt[0] = data_len + 1;
++	pkt[1] = cmd;
++	if (data_len > 0)
++		memcpy(pkt + 2, data, data_len);
++	pkt[2 + data_len] = 0;
++	for (i = 0; i < data_len + 2; i++)
++		pkt[data_len + 2] -= pkt[i];
++
++	dev_dbg(anx7688->dev, "send pd packet cmd=0x%02x %*ph\n",
++		cmd, data_len + 3, pkt);
++
++	ret = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_INTERFACE_SEND);
++	if (ret) {
++		dev_err(anx7688->dev,
++			"failed to send pd packet (tx buffer full)\n");
++		return -EBUSY;
++	}
++
++	ret = i2c_smbus_write_i2c_block_data(anx7688->client_tcpc,
++					     ANX7688_TCPC_REG_INTERFACE_SEND,
++					     data_len + 3, pkt);
++	if (ret < 0)
++		dev_err(anx7688->dev,
++			"failed to send pd packet (err=%d)\n", ret);
++
++	// wait until the message is processed (30ms max)
++	for (i = 0; i < 300; i++) {
++		ret = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_INTERFACE_SEND);
++		if (ret <= 0)
++			return ret;
++
++		udelay(100);
++	}
++
++	dev_err(anx7688->dev, "timeout waiting for the message queue flush\n");
++	return -ETIMEDOUT;
++}
++
++static int anx7688_connect(struct anx7688 *anx7688)
++{
++#if DISABLE_OCM
++	int ret;
++
++	dev_dbg(anx7688->dev, "cable inserted\n");
++
++	msleep(10);
++	anx7688_power_enable(anx7688);
++
++	/* reset the OCM right away */
++	ret = anx7688_reg_update_bits(anx7688, ANX7688_REG_USBC_RESET_CTRL,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET);
++	if (ret)
++		goto err_poweroff;
++
++	/* enable interrupts for VBUS, etc. */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, 0xff);
++	if (ret)
++		goto err_poweroff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_MASK2, ~(BIT(6) | BIT(5) | BIT(4)));
++	if (ret)
++		goto err_poweroff;
++
++	set_bit(ANX7688_F_CONNECTED, anx7688->flags);
++	return 0;
++
++err_poweroff:
++	anx7688_power_disable(anx7688);
++	return ret;
++#else
++	struct typec_partner_desc desc = {};
++	int ret, i;
++	u8 fw[2];
++	const u8 dp_snk_identity[16] = {
++		0x00, 0x00, 0x00, 0xec,	/* id header */
++		0x00, 0x00, 0x00, 0x00,	/* cert stat */
++		0x00, 0x00, 0x00, 0x00,	/* product type */
++		0x39, 0x00, 0x00, 0x51	/* alt mode adapter */
++	};
++	const u8 svid[4] = {
++		0x00, 0x00, 0x01, 0xff,
++	};
++	u32 caps[8];
++
++	dev_dbg(anx7688->dev, "cable inserted\n");
++
++	anx7688->last_status = -1;
++	anx7688->last_cc_status = -1;
++	anx7688->last_dp_state = -1;
++
++	msleep(10);
++	anx7688_power_enable(anx7688);
++
++	ret = regulator_enable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++	if (ret) {
++		dev_err(anx7688->dev, "failed to enable vconn\n");
++		goto err_poweroff;
++	}
++	anx7688->vconn_on = true;
++
++	/* wait till the firmware is loaded (typically ~30ms) */
++	for (i = 0; i < 100; i++) {
++		ret = anx7688_reg_read(anx7688, ANX7688_REG_EEPROM_LOAD_STATUS0);
++
++		if (ret >= 0 && (ret & ANX7688_EEPROM_FW_LOADED) == ANX7688_EEPROM_FW_LOADED) {
++			dev_dbg(anx7688->dev, "eeprom0 = 0x%02x\n", ret);
++			dev_info(anx7688->dev, "fw loaded after %d ms\n", i * 10);
++			goto fw_loaded;
++		}
++
++		msleep(5);
++	}
++
++	set_bit(ANX7688_F_FW_FAILED, anx7688->flags);
++	dev_err(anx7688->dev, "boot firmware load failed (you may need to flash FW to anx7688 first)\n");
++	ret = -ETIMEDOUT;
++	goto err_vconoff;
++
++fw_loaded:
++	ret = i2c_smbus_read_i2c_block_data(anx7688->client,
++					    ANX7688_REG_FW_VERSION1, 2, fw);
++	if (ret < 0) {
++		dev_err(anx7688->dev, "failed to read firmware version\n");
++		goto err_vconoff;
++	}
++
++	dev_info(anx7688->dev, "OCM firmware loaded (version 0x%04x)\n",
++		 fw[1] | fw[0] << 8);
++
++	/* Unmask interrupts */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_STATUS_INT, 0);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_STATUS_INT_MASK, ~ANX7688_SOFT_INT_MASK);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, 0xff);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_MASK2, (u8)~ANX7688_IRQ2_SOFT_INT);
++	if (ret)
++		goto err_vconoff;
++
++	/* time to turn off vbus after cc disconnect (unit is 4 ms) */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_VBUS_OFF_DELAY_TIME, 100 / 4);
++	if (ret)
++		goto err_vconoff;
++
++	//anx7688_reg_write(anx7688, ANX7688_REG_TIME_CTRL, 0x00);
++
++	/* 300ms (unit is 2 ms) */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_TRY_UFP_TIMER, 300 / 2);
++	if (ret)
++		goto err_vconoff;
++
++	/* maximum voltage in 100 mV units */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_MAX_VOLTAGE, 50); /* 5 V */
++	if (ret)
++		goto err_vconoff;
++
++	/* min/max power in 500 mW units */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_MAX_POWER, 15 * 2); /* 15 W */
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_MIN_POWER, 1);  /* 0.5 W */
++	if (ret)
++		goto err_vconoff;
++
++	/* auto_pd, try.src, try.sink, goto safe 5V */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_FEATURE_CTRL, 0x1e & ~BIT(2)); // disable try_src
++	if (ret)
++		goto err_vconoff;
++
++	for (i = 0; i < anx7688->n_src_caps; i++)
++		caps[i] = cpu_to_le32(anx7688->src_caps[i]);
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PWR_SRC_CAP,
++				       (u8*)&caps, 4 * anx7688->n_src_caps);
++	if (ret)
++		goto err_vconoff;
++
++	for (i = 0; i < anx7688->n_snk_caps; i++)
++		caps[i] = cpu_to_le32(anx7688->snk_caps[i]);
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PWR_SNK_CAP,
++				       (u8*)&caps, 4 * anx7688->n_snk_caps);
++	if (ret)
++		goto err_vconoff;
++
++	/* Send DP SNK identity */
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_DP_SNK_IDENTITY,
++				       dp_snk_identity, sizeof dp_snk_identity);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_SVID,
++				       svid, sizeof svid);
++	if (ret)
++		goto err_vconoff;
++
++	dev_dbg(anx7688->dev, "OCM configuration completed\n");
++
++	desc.accessory = TYPEC_ACCESSORY_NONE;
++
++	typec_unregister_partner(anx7688->partner);
++
++	anx7688->partner = typec_register_partner(anx7688->port, &desc);
++	if (IS_ERR(anx7688->partner)) {
++		ret = PTR_ERR(anx7688->partner);
++		goto err_vconoff;
++	}
++
++	// after this deadline passes we'll check if device is pd_capable and
++	// set up the current limit accordingly
++	anx7688->current_update_deadline = ktime_add_ms(ktime_get(), 3000);
++
++	set_bit(ANX7688_F_CONNECTED, anx7688->flags);
++	return 0;
++
++err_vconoff:
++	regulator_disable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++	anx7688->vconn_on = false;
++err_poweroff:
++	anx7688_power_disable(anx7688);
++	dev_err(anx7688->dev, "OCM configuration failed\n");
++	return ret;
++#endif
++}
++
++static void anx7688_set_hdmi_hpd(struct anx7688 *anx7688, int state)
++{
++	if (!anx7688->extcon)
++		return;
++
++	if (anx7688->last_extcon_state != state) {
++		extcon_set_state_sync(anx7688->extcon, EXTCON_DISP_HDMI, state);
++		anx7688->last_extcon_state = state;
++	}
++}
++
++static void anx7688_disconnect(struct anx7688 *anx7688)
++{
++	union power_supply_propval val = {0,};
++	struct device *dev = anx7688->dev;
++	int ret;
++
++	dev_dbg(dev, "cable removed\n");
++
++	anx7688->current_update_deadline = 0;
++
++	anx7688_set_hdmi_hpd(anx7688, 0);
++
++	if (anx7688->vconn_on) {
++		regulator_disable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++		anx7688->vconn_on = false;
++	}
++
++	if (anx7688->vbus_on) {
++		regulator_disable(anx7688->supplies[ANX7688_VBUS_INDEX].consumer);
++		anx7688->vbus_on = false;
++	}
++
++	anx7688_power_disable(anx7688);
++
++	anx7688->pd_capable = false;
++
++	typec_unregister_partner(anx7688->partner);
++	anx7688->partner = NULL;
++
++	anx7688->pwr_role = TYPEC_SINK;
++	anx7688->data_role = TYPEC_DEVICE;
++	typec_set_pwr_role(anx7688->port, anx7688->pwr_role);
++	typec_set_data_role(anx7688->port, anx7688->data_role);
++	typec_set_pwr_opmode(anx7688->port, TYPEC_PWR_MODE_USB);
++	typec_set_vconn_role(anx7688->port, TYPEC_SINK);
++
++	usb_role_switch_set_role(anx7688->role_sw, USB_ROLE_NONE);
++
++	val.intval = 500 * 1000;
++	dev_dbg(dev, "setting vbus_in current limit to %d mA\n", val.intval);
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++					&val);
++	if (ret)
++		dev_err(dev, "failed to set vbus_in current to %d mA\n",
++			val.intval / 1000);
++
++	val.intval = 0;
++	dev_dbg(dev, "disabling vbus_in power path\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_ONLINE,
++					&val);
++	if (ret)
++		dev_err(dev, "failed to offline vbus_in\n");
++
++	val.intval = 1;
++	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_USB_BC_ENABLED,
++					&val);
++	if (ret)
++		dev_err(dev, "failed to enabled USB BC1.2 detection\n");
++
++	clear_bit(ANX7688_F_CONNECTED, anx7688->flags);
++}
++
++static void anx7688_handle_cable_change(struct anx7688* anx7688)
++{
++	int cabledet;
++	bool connected;
++
++	connected = test_bit(ANX7688_F_CONNECTED, anx7688->flags);
++	cabledet = gpiod_get_value(anx7688->gpio_cabledet);
++
++	if (cabledet && !connected)
++		anx7688_connect(anx7688);
++	else if (!cabledet && connected)
++		anx7688_disconnect(anx7688);
++}
++
++static irqreturn_t anx7688_irq_plug_handler(int irq, void *data)
++{
++	struct anx7688 *anx7688 = data;
++
++	dev_dbg(anx7688->dev, "plug irq (cd=%d)\n",
++		gpiod_get_value(anx7688->gpio_cabledet));
++
++	/*
++	 * After each cabledet change the scheduled work timer is reset
++	 * to fire in ~10ms. So the work is done only after the cabledet
++	 * is stable for ~10ms.
++	 */
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(10));
++
++	return IRQ_HANDLED;
++}
++
++enum {
++	CMD_SUCCESS,
++	CMD_REJECT,
++	CMD_FAIL,
++	CMD_BUSY,
++};
++
++static const char* anx7688_cmd_statuses[] = {
++	"SUCCESS",
++	"REJECT",
++	"FAIL",
++	"BUSY",
++};
++
++static int anx7688_handle_pd_message_response(struct anx7688* anx7688,
++					      u8 to_cmd, u8 resp)
++{
++	const char* status = resp <= CMD_BUSY ? anx7688_cmd_statuses[resp] : "UNKNOWN";
++
++	switch (to_cmd) {
++	case ANX7688_OCM_MSG_PSWAP_REQ:
++		dev_info(anx7688->dev, "received response to PSWAP_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_DSWAP_REQ:
++		dev_info(anx7688->dev, "received response to DSWAP_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_VCONN_SWAP_REQ:
++		dev_info(anx7688->dev, "received response to VCONN_SWAP_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_PWR_OBJ_REQ:
++		dev_info(anx7688->dev, "received response to PWR_OBJ_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_VDM:
++		dev_info(anx7688->dev, "received response to VDM (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_GOTO_MIN_REQ:
++		dev_info(anx7688->dev, "received response to GOTO_MIN_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_GET_SNK_CAP:
++		dev_info(anx7688->dev, "received response to GET_SNK_CAP (%s)\n", status);
++		break;
++
++	default:
++		dev_info(anx7688->dev, "received response to unknown request (%s)\n", status);
++		break;
++	}
++
++	return 0;
++}
++
++static int anx7688_handle_pd_message(struct anx7688* anx7688,
++				     u8 cmd, u8* msg, unsigned len)
++{
++	struct device *dev = anx7688->dev;
++	union power_supply_propval psy_val = {0,};
++	uint32_t* pdos = (uint32_t*)msg;
++	int ret, i, rdo_max_v, rdo_max_p;
++	uint32_t pdo, rdo;
++
++	switch (cmd) {
++	case ANX7688_OCM_MSG_PWR_SRC_CAP:
++		dev_info(anx7688->dev, "received SRC_CAP\n");
++
++		if (len % 4 != 0) {
++			dev_warn(anx7688->dev, "received invalid sized PDO array\n");
++			break;
++		}
++
++		/* the partner is PD capable */
++		anx7688->pd_capable = true;
++
++		for (i = 0; i < len / 4; i++) {
++			pdo = le32_to_cpu(pdos[i]);
++
++			if (pdo_type(pdo) == PDO_TYPE_FIXED) {
++				unsigned voltage = pdo_fixed_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SRC_CAP PDO_FIXED (%umV %umA)\n", voltage, max_curr);
++			} else if (pdo_type(pdo) == PDO_TYPE_BATT) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_pow = pdo_max_power(pdo);
++
++				dev_info(anx7688->dev, "SRC_CAP PDO_BATT (%umV-%umV %umW)\n", min_volt, max_volt, max_pow);
++			} else if (pdo_type(pdo) == PDO_TYPE_VAR) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SRC_CAP PDO_VAR (%umV-%umV %umA)\n", min_volt, max_volt, max_curr);
++			} else {
++				dev_info(anx7688->dev, "SRC_CAP PDO_APDO (0x%08X)\n", pdo);
++			}
++		}
++
++		/* when auto_pd mode is enabled, the FW has already set
++		 * RDO_MAX_VOLTAGE and RDO_MAX_POWER for the RDO it sent to the
++		 * partner based on the received SOURCE_CAPs. This does not
++		 * mean, the request was acked, but we can't do better here than
++		 * calculate the current_limit to set later and hope for the best.
++		 */
++		rdo_max_v = anx7688_reg_read(anx7688, ANX7688_REG_MAX_VOLTAGE_STATUS);
++		if (rdo_max_v < 0)
++			return rdo_max_v;
++		if (rdo_max_v == 0)
++			return -EINVAL;
++
++		rdo_max_p = anx7688_reg_read(anx7688, ANX7688_REG_MAX_POWER_STATUS);
++		if (rdo_max_p < 0)
++			return rdo_max_p;
++
++		anx7688->pd_current_limit = rdo_max_p * 5000 / rdo_max_v;
++
++		dev_dbg(anx7688->dev, "RDO max voltage = %dmV, max power = %dmW, PD current limit = %dmA\n",
++			rdo_max_v * 100, rdo_max_p * 500, anx7688->pd_current_limit);
++
++		// update current limit sooner, now that we have PD negotiation result
++		anx7688->current_update_deadline = ktime_add_ms(ktime_get(), 500);
++
++		//TODO: we should go through PDOs and decide which one
++		//to request, build a RDO with a proper index of the
++		//selected PDO and send it via PWR_OBJ_REQ message to FW
++		//but we're using auto_pd, so FW does this for us
++		//
++		//rdo = cpu_to_le32(RDO_FIXED(0, 1500, 1500, RDO_USB_COMM));
++		//ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PWR_OBJ_REQ, &rdo, 4);
++
++		break;
++
++	case ANX7688_OCM_MSG_PWR_SNK_CAP:
++		dev_info(anx7688->dev, "received SNK_CAP\n");
++
++		if (len % 4 != 0) {
++			dev_warn(anx7688->dev, "received invalid sized PDO array\n");
++			break;
++		}
++
++		for (i = 0; i < len / 4; i++) {
++			pdo = le32_to_cpu(pdos[i]);
++
++			if (pdo_type(pdo) == PDO_TYPE_FIXED) {
++				unsigned voltage = pdo_fixed_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SNK_CAP PDO_FIXED (%umV %umA)\n", voltage, max_curr);
++			} else if (pdo_type(pdo) == PDO_TYPE_BATT) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_pow = pdo_max_power(pdo);
++
++				dev_info(anx7688->dev, "SNK_CAP PDO_BATT (%umV-%umV %umW)\n", min_volt, max_volt, max_pow);
++			} else if (pdo_type(pdo) == PDO_TYPE_VAR) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SNK_CAP PDO_VAR (%umV-%umV %umA)\n", min_volt, max_volt, max_curr);
++			} else {
++				dev_info(anx7688->dev, "SNK_CAP PDO_APDO (0x%08X)\n", pdo);
++			}
++		}
++
++		break;
++
++	case ANX7688_OCM_MSG_PWR_OBJ_REQ:
++		dev_info(anx7688->dev, "received PWR_OBJ_REQ\n");
++
++		anx7688->pd_capable = true;
++
++		if (len != 4) {
++			dev_warn(anx7688->dev, "received invalid sized RDO\n");
++			break;
++		}
++
++		rdo = le32_to_cpu(pdos[0]);
++
++		if (rdo_index(rdo) >= 1 && rdo_index(rdo) <= anx7688->n_src_caps) {
++			unsigned rdo_op_curr = rdo_op_current(rdo);
++			unsigned rdo_max_curr = rdo_max_current(rdo);
++			unsigned rdo_idx = rdo_index(rdo) - 1;
++			unsigned pdo_volt, pdo_max_curr;
++
++			pdo = anx7688->src_caps[rdo_idx];
++			pdo_volt = pdo_fixed_voltage(pdo);
++			pdo_max_curr = pdo_max_current(pdo);
++
++			dev_info(anx7688->dev, "RDO (idx=%d op=%umA max=%umA)\n",
++				 rdo_idx, rdo_op_curr, rdo_max_curr);
++
++			dev_info(anx7688->dev, "PDO_FIXED (%umV %umA)\n",
++				 pdo_volt, pdo_max_curr);
++
++			//TODO: we should check the req and respond with accept/reject
++			// but we're using auto_pd feature, so the FW will do
++			// this for us
++			if (rdo_op_curr > pdo_max_curr || rdo_max_curr > pdo_max_curr) {
++				//ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_REJECT, 0, 0);
++			} else {
++				//ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_ACCEPT, 0, 0);
++			}
++		} else {
++			dev_info(anx7688->dev, "PWR_OBJ RDO index out of range (RDO = 0x%08X)\n", rdo);
++		}
++
++		break;
++
++	case ANX7688_OCM_MSG_ACCEPT:
++		dev_info(anx7688->dev, "received ACCEPT\n");
++		break;
++
++	case ANX7688_OCM_MSG_REJECT:
++		dev_info(anx7688->dev, "received REJECT\n");
++		break;
++
++	case ANX7688_OCM_MSG_RESPONSE_TO_REQ:
++		if (len < 2) {
++			dev_warn(anx7688->dev, "received short RESPONSE_TO_REQ\n");
++			break;
++		}
++
++		anx7688_handle_pd_message_response(anx7688, msg[0], msg[1]);
++		break;
++
++	case ANX7688_OCM_MSG_SOFT_RST:
++		dev_info(anx7688->dev, "received SOFT_RST\n");
++		break;
++
++	case ANX7688_OCM_MSG_HARD_RST:
++		if (anx7688->pd_capable) {
++			dev_info(anx7688->dev, "received HARD_RST\n");
++
++			// stop drawing power from VBUS
++			psy_val.intval = 0;
++			dev_dbg(dev, "disabling vbus_in power path\n");
++			ret = power_supply_set_property(anx7688->vbus_in_supply,
++							POWER_SUPPLY_PROP_ONLINE,
++							&psy_val);
++			if (ret)
++				dev_err(anx7688->dev, "failed to offline vbus_in\n");
++
++			// wait till the dust settles
++			anx7688->current_update_deadline = ktime_add_ms(ktime_get(), 3000);
++		} else {
++			dev_dbg(anx7688->dev, "received HARD_RST, idiot firmware is bored\n");
++		}
++
++		break;
++
++	case ANX7688_OCM_MSG_RESTART:
++		dev_info(anx7688->dev, "received RESTART\n");
++		break;
++
++	case ANX7688_OCM_MSG_PSWAP_REQ:
++		dev_info(anx7688->dev, "received PSWAP_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_DSWAP_REQ:
++		dev_info(anx7688->dev, "received DSWAP_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_VCONN_SWAP_REQ:
++		dev_info(anx7688->dev, "received VCONN_SWAP_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_ALT_ENTER:
++		dev_info(anx7688->dev, "received DP_ALT_ENTER\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_ALT_EXIT:
++		dev_info(anx7688->dev, "received DP_ALT_EXIT\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_SNK_IDENTITY:
++		dev_info(anx7688->dev, "received DP_SNK_IDENTITY\n");
++		break;
++
++	case ANX7688_OCM_MSG_SVID:
++		dev_info(anx7688->dev, "received SVID\n");
++		break;
++
++	case ANX7688_OCM_MSG_VDM:
++		dev_info(anx7688->dev, "received VDM\n");
++		break;
++
++	case ANX7688_OCM_MSG_GOTO_MIN_REQ:
++		dev_info(anx7688->dev, "received GOTO_MIN_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_PD_STATUS_REQ:
++		dev_info(anx7688->dev, "received PD_STATUS_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_GET_DP_SNK_CAP:
++		dev_info(anx7688->dev, "received GET_DP_SNK_CAP\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_SNK_CFG:
++		dev_info(anx7688->dev, "received DP_SNK_CFG\n");
++		break;
++
++	default:
++		dev_info(anx7688->dev, "received unknown message 0x%02x\n", cmd);
++		break;
++	}
++
++	return 0;
++}
++
++static int anx7688_receive_msg(struct anx7688* anx7688)
++{
++	u8 pkt[32], checksum = 0;
++	int i, ret;
++
++	ret = i2c_smbus_read_i2c_block_data(anx7688->client_tcpc,
++					    ANX7688_TCPC_REG_INTERFACE_RECV,
++					    32, pkt);
++	if (ret < 0) {
++		dev_err(anx7688->dev, "failed to read pd msg\n");
++		return ret;
++	}
++
++	ret = anx7688_tcpc_reg_write(anx7688, ANX7688_TCPC_REG_INTERFACE_RECV, 0);
++	if (ret) {
++		dev_warn(anx7688->dev, "failed to clear recv fifo\n");
++	}
++
++	if (pkt[0] == 0 || pkt[0] > sizeof(pkt) - 2) {
++		dev_err(anx7688->dev, "received invalid pd message: %*ph\n",
++			(int)sizeof(pkt), pkt);
++		return -EINVAL;
++	}
++
++	dev_dbg(anx7688->dev, "recv ocm message cmd=0x%02x %*ph\n",
++		pkt[1], pkt[0] + 2, pkt);
++
++	for (i = 0; i < pkt[0] + 2; i++)
++		checksum += pkt[i];
++
++	if (checksum != 0) {
++		dev_err(anx7688->dev, "bad checksum on received message\n");
++		return -EINVAL;
++	}
++
++	anx7688_handle_pd_message(anx7688, pkt[1], pkt + 2, pkt[0] - 1);
++	return 0;
++}
++
++static const char* anx7688_cc_status_string(unsigned v)
++{
++	switch (v) {
++	case 0: return "SRC.Open";
++	case 1: return "SRC.Rd";
++	case 2: return "SRC.Ra";
++	case 4: return "SNK.Default";
++	case 8: return "SNK.Power1.5";
++	case 12: return "SNK.Power3.0";
++	default: return "UNK";
++	}
++}
++
++static int anx7688_update_status(struct anx7688 *anx7688)
++{
++	struct device *dev = anx7688->dev;
++	bool vbus_on, vconn_on, dr_dfp;
++	int status, cc_status, dp_state, dp_substate, ret;
++
++	status = anx7688_reg_read(anx7688, ANX7688_REG_STATUS);
++	if (status < 0)
++		return status;
++
++	cc_status = anx7688_reg_read(anx7688, ANX7688_REG_CC_STATUS);
++	if (cc_status < 0)
++		return cc_status;
++
++	dp_state = anx7688_tcpc_reg_read(anx7688, 0x87);
++	if (dp_state < 0)
++		return dp_state;
++
++	dp_substate = anx7688_tcpc_reg_read(anx7688, 0x88);
++	if (dp_substate < 0)
++		return dp_substate;
++
++	anx7688_set_hdmi_hpd(anx7688, dp_state >= 3);
++
++	dp_state = (dp_state << 8) | dp_substate;
++
++	if (anx7688->last_status == -1 || anx7688->last_status != status) {
++		anx7688->last_status = status;
++		dev_dbg(dev, "status changed to 0x%02x\n", status);
++	}
++
++	if (anx7688->last_cc_status == -1 || anx7688->last_cc_status != cc_status) {
++		anx7688->last_cc_status = cc_status;
++		dev_dbg(dev, "cc_status changed to CC1 = %s CC2 = %s\n",
++			anx7688_cc_status_string(cc_status & 0xf),
++			anx7688_cc_status_string((cc_status >> 4) & 0xf));
++	}
++
++	if (anx7688->last_dp_state == -1 || anx7688->last_dp_state != dp_state) {
++		anx7688->last_dp_state = dp_state;
++		dev_dbg(dev, "DP state changed to 0x%04x\n", dp_state);
++	}
++
++	vbus_on = !!(status & ANX7688_VBUS_STATUS);
++	vconn_on = !!(status & ANX7688_VCONN_STATUS);
++	dr_dfp = !!(status & ANX7688_DATA_ROLE_STATUS);
++
++	if (anx7688->vbus_on != vbus_on) {
++		dev_dbg(anx7688->dev, "POWER role change to %s\n",
++			vbus_on ? "SOURCE" : "SINK");
++
++		if (vbus_on) {
++			ret = regulator_enable(anx7688->supplies[ANX7688_VBUS_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to enable vbus\n");
++				return ret;
++			}
++		} else {
++			ret = regulator_disable(anx7688->supplies[ANX7688_VBUS_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to disable vbus\n");
++				return ret;
++			}
++		}
++
++		anx7688->pwr_role = vbus_on ? TYPEC_SOURCE : TYPEC_SINK;
++		typec_set_pwr_role(anx7688->port, anx7688->pwr_role);
++		anx7688->vbus_on = vbus_on;
++	}
++
++	if (anx7688->vconn_on != vconn_on) {
++		dev_dbg(anx7688->dev, "VCONN role change to %s\n",
++			vconn_on ? "SOURCE" : "SINK");
++
++		if (vconn_on) {
++			ret = regulator_enable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to enable vconn\n");
++				return ret;
++			}
++		} else {
++			ret = regulator_disable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to disable vconn\n");
++				return ret;
++			}
++		}
++
++		typec_set_vconn_role(anx7688->port, vconn_on ? TYPEC_SOURCE : TYPEC_SINK);
++		anx7688->vconn_on = vconn_on;
++	}
++
++	anx7688->data_role = dr_dfp ? TYPEC_HOST : TYPEC_DEVICE;
++	typec_set_data_role(anx7688->port, anx7688->data_role);
++
++	if (usb_role_switch_get_role(anx7688->role_sw) !=
++	    (dr_dfp ? USB_ROLE_HOST : USB_ROLE_DEVICE)) {
++		dev_dbg(anx7688->dev, "DATA role change requested to %s\n",
++			dr_dfp ? "DFP" : "UFP");
++
++		ret = usb_role_switch_set_role(anx7688->role_sw,
++					       dr_dfp ? USB_ROLE_HOST : USB_ROLE_DEVICE);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++static irqreturn_t anx7688_irq_status_handler(int irq, void *data)
++{
++#if DISABLE_OCM
++	struct anx7688 *anx7688 = data;
++	struct device *dev = anx7688->dev;
++	int ext2_status;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_CONNECTED, anx7688->flags)) {
++		/*
++		 * The chip should be disabled and powered off, nothing
++		 * more to do.
++		 */
++		dev_dbg(dev, "spurious status irq\n");
++		goto out_unlock;
++	}
++
++	//dev_dbg(dev, "status irq\n");
++
++	ext2_status = anx7688_reg_read(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2);
++	dev_dbg(dev, "  ext2 = 0x%02x\n", ext2_status);
++	anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, ext2_status);
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return IRQ_HANDLED;
++#else
++	struct anx7688 *anx7688 = data;
++	struct device *dev = anx7688->dev;
++	int tcpc_status, ext2_status, soft_status;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_CONNECTED, anx7688->flags)) {
++		dev_dbg(dev, "spurious status irq\n");
++		/* anx chip should be disabled and power off, nothing
++		 * more to do */
++		goto out_unlock;
++	}
++
++	//dev_dbg(dev, "status irq\n");
++
++	// clear tcpc interrupt
++	tcpc_status = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_ALERT0);
++	if (tcpc_status > 0) {
++		//dev_dbg(dev, "  tcpc = 0x%02x\n", tcpc_status);
++		anx7688_tcpc_reg_write(anx7688, ANX7688_TCPC_REG_ALERT0, tcpc_status);
++	}
++
++	ext2_status = anx7688_reg_read(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2);
++	if (ext2_status & ANX7688_IRQ2_SOFT_INT) {
++		soft_status = anx7688_reg_read(anx7688, ANX7688_REG_STATUS_INT);
++		anx7688_reg_write(anx7688, ANX7688_REG_STATUS_INT, 0);
++
++		//dev_dbg(dev, "  soft = 0x%02x\n", soft_status);
++
++		if (soft_status > 0) {
++			soft_status &= ANX7688_SOFT_INT_MASK;
++
++			if (soft_status & ANX7688_IRQS_RECEIVED_MSG)
++				anx7688_receive_msg(anx7688);
++
++			if (soft_status & (ANX7688_IRQS_CC_STATUS_CHANGE |
++					   ANX7688_IRQS_VBUS_CHANGE |
++					   ANX7688_IRQS_VCONN_CHANGE |
++					   ANX7688_IRQS_DATA_ROLE_CHANGE)) {
++				anx7688_update_status(anx7688);
++			}
++		}
++
++		anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, ANX7688_IRQ2_SOFT_INT);
++	}
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return IRQ_HANDLED;
++#endif
++}
++
++static int anx7688_dr_set(struct typec_port *port, enum typec_data_role role)
++{
++	struct anx7688 *anx7688 = typec_get_drvdata(port);
++	int ret = 0;
++
++	dev_info(anx7688->dev, "data role set %d\n", role);
++
++	if (anx7688->data_role != role) {
++		mutex_lock(&anx7688->lock);
++		ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_DSWAP_REQ, 0, 0);
++		mutex_unlock(&anx7688->lock);
++	}
++
++	return ret;
++}
++
++static int anx7688_pr_set(struct typec_port *port, enum typec_role role)
++{
++	struct anx7688 *anx7688 = typec_get_drvdata(port);
++	int ret = 0;
++
++	dev_info(anx7688->dev, "power role set %d\n", role);
++
++	if (anx7688->pwr_role != role) {
++		mutex_lock(&anx7688->lock);
++		ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PSWAP_REQ, 0, 0);
++		mutex_unlock(&anx7688->lock);
++	}
++
++	return ret;
++}
++
++/*
++ * Calls to the eerpom functions need to be taken under the anx7688 lock.
++ */
++
++static int anx7688_eeprom_set_address(struct anx7688 *anx7688, u16 addr)
++{
++	int ret;
++
++	ret = anx7688_reg_write(anx7688, 0xe0, (addr >> 8) & 0xff);
++	if (ret < 0)
++		return ret;
++
++	return anx7688_reg_write(anx7688, 0xe1, addr & 0xff);
++}
++
++static int anx7688_eeprom_wait_done(struct anx7688 *anx7688)
++{
++	ktime_t timeout;
++	int ret;
++
++	// wait for read to be done
++	timeout = ktime_add_us(ktime_get(), 50000);
++	while (true) {
++		ret = anx7688_reg_read(anx7688, 0xe2);
++		if (ret < 0)
++			return ret;
++
++		if (ret & BIT(3))
++			return 0;
++
++		if (ktime_after(ktime_get(), timeout)) {
++			dev_err(anx7688->dev, "timeout waiting for eeprom\n");
++			return -ETIMEDOUT;
++		}
++	}
++}
++
++/* wait for internal FSM of EEPROM to be in a state ready for
++ * programming/reading
++ */
++static int anx7688_eeprom_wait_ready(struct anx7688 *anx7688)
++{
++	ktime_t timeout;
++	int ret;
++
++	// wait until eeprom is ready
++	timeout = ktime_add_us(ktime_get(), 1000000);
++	while (true) {
++		ret = anx7688_reg_read(anx7688, 0x7f);
++		if (ret < 0)
++			return ret;
++
++		if ((ret & 0x0f) == 7)
++			return 0;
++
++		if (ktime_after(ktime_get(), timeout)) {
++			dev_err(anx7688->dev, "timeout waiting for eeprom to initialize\n");
++			return -ETIMEDOUT;
++		}
++
++		msleep(5);
++	}
++}
++
++static int anx7688_eeprom_read(struct anx7688 *anx7688, unsigned addr, u8 buf[16])
++{
++	int ret;
++
++	ret = anx7688_eeprom_set_address(anx7688, addr);
++	if (ret)
++		return ret;
++
++	// initiate read
++	ret = anx7688_reg_write(anx7688, 0xe2, 0x06);
++	if (ret < 0)
++		return ret;
++
++	ret = anx7688_eeprom_wait_done(anx7688);
++	if (ret)
++		return ret;
++
++	ret = i2c_smbus_read_i2c_block_data(anx7688->client, 0xd0, 16, buf);
++	if (ret < 0) {
++		dev_err(anx7688->dev,
++			"failed to read eeprom data (err=%d)\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int anx7688_eeprom_write(struct anx7688 *anx7688, unsigned addr,
++				const u8 buf[16])
++{
++	int ret;
++
++	ret = anx7688_eeprom_set_address(anx7688, addr);
++	if (ret)
++		return ret;
++
++	ret = i2c_smbus_write_i2c_block_data(anx7688->client, 0xd0, 16, buf);
++	if (ret < 0) {
++		dev_err(anx7688->dev,
++			"failed to write eeprom data (err=%d)\n", ret);
++		return ret;
++	}
++
++	dev_info(anx7688->dev, "eeprom wr %x %*ph\n", addr, 16, buf);
++
++	// initiate write
++	ret = anx7688_reg_write(anx7688, 0xe2, 0x01);
++	if (ret < 0)
++		return ret;
++
++	ret = anx7688_eeprom_wait_done(anx7688);
++	if (ret)
++		return ret;
++
++	udelay(1500);
++	udelay(1000);
++
++	return 0;
++}
++
++/*
++ * The firmware is flashed as is from address 0x10 up to 0xffff.
++ */
++static int anx7688_flash_firmware(struct anx7688 *anx7688)
++{
++	const char* fw_name = "anx7688-fw.bin";
++	const struct firmware *fw;
++	unsigned addr;
++	u8 buf[16];
++	int ret;
++
++	ret = request_firmware(&fw, fw_name, anx7688->dev);
++	if (ret < 0)
++		return ret;
++
++	if (fw->size > 0x10000 - 16) {
++		dev_err(anx7688->dev, "Firmware is too big %s\n", fw_name);
++		ret = -E2BIG;
++		goto err_release;
++	}
++
++	mutex_lock(&anx7688->lock);
++
++	/*
++	 * Cabledet changes will not be processed, since we're holding the
++	 * lock, so the firmware flashing is safe from interruptions.
++	 */
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	msleep(20);
++
++	anx7688_power_enable(anx7688);
++
++	// reset OCM
++	ret = anx7688_reg_update_bits(anx7688, ANX7688_REG_USBC_RESET_CTRL,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET);
++	if (ret < 0)
++		goto err_unlock;
++
++	ret = anx7688_eeprom_wait_ready(anx7688);
++	if (ret)
++		goto err_unlock;
++
++	msleep(10);
++
++	/*
++	 * Write to some magic registers to unlock flashing the EEPROM.
++	 */
++	ret = anx7688_reg_update_bits(anx7688, 0x3f, BIT(5), BIT(5));
++	if (ret < 0)
++		goto err_unlock;
++
++	ret = anx7688_reg_update_bits(anx7688, 0x44,
++				      BIT(0) | BIT(7),
++				      BIT(0) | BIT(7));
++	if (ret < 0)
++		goto err_unlock;
++
++	ret = anx7688_reg_update_bits(anx7688, 0x66, BIT(3), BIT(3));
++	if (ret < 0)
++		goto err_unlock;
++
++	msleep(50);
++
++	ret = anx7688_eeprom_wait_done(anx7688);
++	if (ret)
++		goto err_unlock;
++
++	for (addr = 0; addr < fw->size; addr += sizeof buf) {
++		memset(buf, 0, sizeof buf);
++		memcpy(buf, fw->data + addr, min_t(unsigned, fw->size - addr, sizeof buf));
++
++		ret = anx7688_eeprom_write(anx7688, addr + 0x10, buf);
++		if (ret < 0)
++			goto err_unlock;
++	}
++
++	clear_bit(ANX7688_F_FW_FAILED, anx7688->flags);
++
++err_unlock:
++	anx7688_power_disable(anx7688);
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(20));
++	mutex_unlock(&anx7688->lock);
++
++err_release:
++	release_firmware(fw);
++	return ret;
++}
++
++static const struct typec_operations anx7688_typec_ops = {
++	.dr_set = anx7688_dr_set,
++	.pr_set = anx7688_pr_set,
++};
++
++static ssize_t flash_eeprom_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	return scnprintf(buf, PAGE_SIZE, "Write 1 to this file to initiate firmware flashing. Consult dmesg for results.\n");
++}
++
++static ssize_t flash_eeprom_store(struct device *dev,
++				  struct device_attribute *attr,
++				  const char *buf, size_t len)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++	unsigned val;
++	int ret;
++
++	ret = kstrtouint(buf, 0, &val);
++	if (ret)
++		return ret;
++
++	if (val == 1) {
++		ret = anx7688_flash_firmware(anx7688);
++		if (ret)
++			return ret;
++	}
++
++	return len;
++}
++static DEVICE_ATTR_RW(flash_eeprom);
++
++static ssize_t reg_update_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t len)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++	unsigned val, addr, devaddr, data;
++	int ret;
++
++	ret = kstrtouint(buf, 16, &val);
++	if (ret)
++		return ret;
++
++	data = val & 0xff;
++	addr = (val >> 8) & 0xff;
++	devaddr = (val >> 16) & 0xff;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_POWERED, anx7688->flags)) {
++		ret = -ENODEV;
++		goto out_unlock;
++	}
++
++	if (devaddr == 0x50)
++		ret = anx7688_reg_write(anx7688, addr, val);
++	else if (devaddr == 0x58)
++		ret = anx7688_tcpc_reg_write(anx7688, addr, val);
++	else
++		ret = -EINVAL;
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return ret ? ret : len;
++}
++static DEVICE_ATTR_WO(reg_update);
++
++static ssize_t hwreset_store(struct device *dev,
++			     struct device_attribute *attr,
++			     const char *buf, size_t len)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++
++	mutex_lock(&anx7688->lock);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(20));
++	mutex_unlock(&anx7688->lock);
++
++	return len;
++}
++static DEVICE_ATTR_WO(hwreset);
++
++static struct attribute *anx7688_attrs[] = {
++	&dev_attr_flash_eeprom.attr,
++	&dev_attr_reg_update.attr,
++	&dev_attr_hwreset.attr,
++	NULL,
++};
++
++ATTRIBUTE_GROUPS(anx7688);
++
++/*
++ * This function has to work when the ANX7688 is active, and when
++ * it is powered down. It power cycles the chip and asserts the OCM
++ * reset, to prevent OCM FW interfering with EEPROM reading.
++ *
++ * After reading EEPROM, the reconnection is scheduled.
++ */
++static int anx7688_firmware_show(struct seq_file *s, void *data)
++{
++	struct anx7688 *anx7688 = s->private;
++	unsigned addr;
++	u8 buf[16];
++	int ret;
++
++	mutex_lock(&anx7688->lock);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	msleep(20);
++
++	anx7688_power_enable(anx7688);
++
++	ret = anx7688_reg_update_bits(anx7688, ANX7688_REG_USBC_RESET_CTRL,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET);
++	if (ret < 0)
++		goto out_powerdown;
++
++	ret = anx7688_eeprom_wait_ready(anx7688);
++	if (ret)
++		goto out_powerdown;
++
++	msleep(10);
++
++	for (addr = 0x10; addr < 0x10000; addr += 16) {
++		// set address
++		ret = anx7688_eeprom_read(anx7688, addr, buf);
++		if (ret < 0)
++			goto out_powerdown;
++
++		seq_write(s, buf, sizeof buf);
++	}
++
++out_powerdown:
++	anx7688_power_disable(anx7688);
++	schedule_delayed_work(&anx7688->work, 0);
++	mutex_unlock(&anx7688->lock);
++
++	return ret;
++}
++DEFINE_SHOW_ATTRIBUTE(anx7688_firmware);
++
++static int anx7688_regs_show(struct seq_file *s, void *data)
++{
++	struct anx7688 *anx7688 = s->private;
++	u8 buf[16];
++	unsigned i, addr;
++	int ret = -ENODEV;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_POWERED, anx7688->flags))
++		goto out_unlock;
++
++	for (addr = 0; addr < 256; addr += 16) {
++		ret = i2c_smbus_read_i2c_block_data(anx7688->client, addr,
++						    sizeof buf, buf);
++		if (ret < 0) {
++			dev_err(anx7688->dev,
++				"failed to read registers (err=%d)\n", ret);
++			goto out_unlock;
++		}
++
++		for (i = 0; i < 16; i++)
++			seq_printf(s, "50%02x: %02x\n", addr + i, buf[i]);
++	}
++
++	for (addr = 0; addr < 256; addr += 16) {
++		ret = i2c_smbus_read_i2c_block_data(anx7688->client_tcpc, addr,
++						    sizeof buf, buf);
++		if (ret < 0) {
++			dev_err(anx7688->dev,
++				"failed to read registers (err=%d)\n", ret);
++			goto out_unlock;
++		}
++
++		for (i = 0; i < 16; i++)
++			seq_printf(s, "58%02x: %02x\n", addr + i, buf[i]);
++	}
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return ret;
++}
++DEFINE_SHOW_ATTRIBUTE(anx7688_regs);
++
++static int anx7688_status_show(struct seq_file *s, void *data)
++{
++	struct anx7688 *anx7688 = s->private;
++
++	mutex_lock(&anx7688->lock);
++
++	seq_printf(s, "not much\n");
++
++	mutex_unlock(&anx7688->lock);
++
++	return 0;
++}
++DEFINE_SHOW_ATTRIBUTE(anx7688_status);
++
++/*
++ * This is just a 1s watchdog checking the state if cabledet pin.
++ */
++static void anx7688_cabledet_timer_fn(struct timer_list *t)
++{
++	struct anx7688 *anx7688 = from_timer(anx7688, t, work_timer);
++
++	schedule_delayed_work(&anx7688->work, 0);
++	mod_timer(t, jiffies + msecs_to_jiffies(1000));
++}
++
++static void anx7688_handle_vbus_in_notify(struct anx7688* anx7688)
++{
++	union power_supply_propval psy_val = {0,};
++	struct device *dev = anx7688->dev;
++	int ret;
++
++	/* PD charger doesn't like this for some reason, so it's disabled for now */
++	if (anx7688->input_current_limit && false) {
++		ret = power_supply_get_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++						&psy_val);
++		if (ret) {
++			dev_err(dev, "failed to get vbus_in current\n");
++			return;
++		}
++
++		if (psy_val.intval == anx7688->input_current_limit)
++			goto check_type;
++
++		psy_val.intval = anx7688->input_current_limit * 1000;
++		dev_dbg(dev, "setting vbus_in current limit to %d mA\n",
++			psy_val.intval / 1000);
++		ret = power_supply_set_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++						&psy_val);
++		if (ret)
++			dev_err(dev, "failed to set vbus_in current to %d mA\n",
++				psy_val.intval / 1000);
++	}
++
++check_type:
++	ret = power_supply_get_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_USB_TYPE,
++					&psy_val);
++	if (ret) {
++		dev_err(dev, "failed to get USB BC1.2 result\n");
++		return;
++	}
++
++	if (anx7688->last_bc_result == psy_val.intval)
++		return;
++
++	anx7688->last_bc_result = psy_val.intval;
++
++	switch (psy_val.intval) {
++	case POWER_SUPPLY_USB_TYPE_DCP:
++	case POWER_SUPPLY_USB_TYPE_CDP:
++		dev_dbg(dev, "BC 1.2 result: DCP or CDP\n");
++		break;
++	case POWER_SUPPLY_USB_TYPE_SDP:
++	default:
++		dev_dbg(dev, "BC 1.2 result: SDP\n");
++		break;
++	}
++}
++
++static int anx7688_cc_status(unsigned v)
++{
++	switch (v) {
++	case 0: return -1;
++	case 1: return -1;
++	case 2: return -1;
++	case 4: return TYPEC_PWR_MODE_USB;
++	case 8: return TYPEC_PWR_MODE_1_5A;
++	case 12: return TYPEC_PWR_MODE_3_0A;
++	default: return -1;
++	}
++}
++
++static const char* anx7688_get_power_mode_name(enum typec_pwr_opmode mode)
++{
++	switch (mode) {
++	case TYPEC_PWR_MODE_USB: return "USB";
++	case TYPEC_PWR_MODE_1_5A: return "1.5A";
++	case TYPEC_PWR_MODE_3_0A: return "3.0A";
++	case TYPEC_PWR_MODE_PD: return "PD";
++	default: return "Unknown";
++	}
++}
++
++/*
++ * This is called after 500ms after connection when the PD contract should have
++ * been negotiated. We should inspect CC pins or PD status here and decide what
++ * input current limit to set.
++ */
++static void anx7688_handle_current_update(struct anx7688* anx7688)
++{
++	unsigned cc_status = anx7688->last_cc_status;
++	union power_supply_propval val = {0,};
++	struct device *dev = anx7688->dev;
++	int pwr_mode, ret, current_limit = 0;
++
++	if (anx7688->pd_capable) {
++		pwr_mode = TYPEC_PWR_MODE_PD;
++	} else if (cc_status < 0) {
++		pwr_mode = TYPEC_PWR_MODE_USB;
++	} else {
++		pwr_mode = anx7688_cc_status(cc_status & 0xf);
++		if (pwr_mode < 0)
++			pwr_mode = anx7688_cc_status((cc_status >> 4) & 0xf);
++		if (pwr_mode < 0)
++			pwr_mode = TYPEC_PWR_MODE_USB;
++	}
++
++	if (pwr_mode == TYPEC_PWR_MODE_1_5A)
++		current_limit = 1500;
++	else if (pwr_mode == TYPEC_PWR_MODE_3_0A)
++		current_limit = 3000;
++	else if (pwr_mode == TYPEC_PWR_MODE_PD)
++		current_limit = anx7688->pd_current_limit;
++
++	anx7688->input_current_limit = current_limit;
++
++	dev_info(anx7688->dev, "updating power mode to %s, current limit %dmA (0 => BC1.2)\n",
++		 anx7688_get_power_mode_name(pwr_mode), current_limit);
++
++	if (current_limit) {
++		/*
++		 * Disable BC1.2 detection, because we'll be setting
++		 * a current limit determined by USB-PD
++		 */
++		val.intval = 0;
++		dev_dbg(dev, "disabling USB BC 1.2 detection\n");
++		ret = power_supply_set_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_USB_BC_ENABLED,
++						&val);
++		if (ret)
++			dev_err(dev, "failed to disable USB BC1.2 detection\n");
++
++		val.intval = current_limit * 1000;
++		dev_dbg(dev, "setting vbus_in current limit to %d mA\n", current_limit);
++		ret = power_supply_set_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++						&val);
++		if (ret)
++			dev_err(dev, "failed to set vbus_in current to %d mA\n",
++				current_limit);
++	} else {
++		/*
++		 * Use the result of BC1.2 detection performed by PMIC.
++		 */
++		ret = power_supply_get_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_USB_BC_ENABLED,
++						&val);
++		if (ret)
++			dev_err(dev, "failed to get USB BC1.2 detection status\n");
++
++		if (ret != 0 || val.intval == 0) {
++			/*
++			 * If BC is disabled or we can't get its status,
++			 * set conservative 500mA limit. Otherwise leave
++			 * the limit to BC1.2.
++			 */
++			val.intval = 500 * 1000;
++			dev_dbg(dev, "setting vbus_in current limit to %d mA\n",
++				val.intval / 1000);
++			ret = power_supply_set_property(anx7688->vbus_in_supply,
++							POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++							&val);
++			if (ret)
++				dev_err(dev, "failed to set vbus_in current to %d mA\n",
++					val.intval / 1000);
++		}
++	}
++
++	/* Turn on VBUS power path inside PMIC. */
++	val.intval = 1;
++	dev_dbg(dev, "enabling vbus_in power path\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_ONLINE,
++					&val);
++	if (ret)
++		dev_err(anx7688->dev, "failed to enable vbus_in\n");
++
++	typec_set_pwr_opmode(anx7688->port, pwr_mode);
++}
++
++static int anx7688_vbus_in_notify(struct notifier_block *nb,
++				  unsigned long val, void *v)
++{
++	struct anx7688 *anx7688 = container_of(nb, struct anx7688, vbus_in_nb);
++	struct power_supply *psy = v;
++
++	/* atomic context */
++	if (val == PSY_EVENT_PROP_CHANGED && psy == anx7688->vbus_in_supply) {
++		set_bit(ANX7688_F_PWRSUPPLY_CHANGE, anx7688->flags);
++		schedule_delayed_work(&anx7688->work, 0);
++	}
++
++	return NOTIFY_OK;
++}
++
++static void anx7688_work(struct work_struct *work)
++{
++	struct anx7688 *anx7688 = container_of(work, struct anx7688, work.work);
++
++	if (test_bit(ANX7688_F_FW_FAILED, anx7688->flags))
++		return;
++
++	mutex_lock(&anx7688->lock);
++
++	if (test_and_clear_bit(ANX7688_F_PWRSUPPLY_CHANGE, anx7688->flags))
++		anx7688_handle_vbus_in_notify(anx7688);
++
++	anx7688_handle_cable_change(anx7688);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags)) {
++		/*
++		 * We check status periodically outside of interrupt, just to
++		 * be sure we didn't miss any status interrupts
++		 */
++		anx7688_update_status(anx7688);
++
++		if (anx7688->current_update_deadline &&
++		    ktime_after(ktime_get(), anx7688->current_update_deadline)) {
++			anx7688->current_update_deadline = 0;
++			anx7688_handle_current_update(anx7688);
++		}
++	}
++
++	mutex_unlock(&anx7688->lock);
++}
++
++static int anx7688_i2c_probe(struct i2c_client *client)
++{
++	struct anx7688 *anx7688;
++	struct device *dev = &client->dev;
++	struct typec_capability typec_cap = { };
++	union power_supply_propval psy_val;
++	int i, vid_h, vid_l;
++	int irq_cabledet;
++	int ret = 0;
++
++	anx7688 = devm_kzalloc(dev, sizeof(*anx7688), GFP_KERNEL);
++	if (!anx7688)
++		return -ENOMEM;
++
++	i2c_set_clientdata(client, anx7688);
++	anx7688->client = client;
++	anx7688->dev = &client->dev;
++	mutex_init(&anx7688->lock);
++	INIT_DELAYED_WORK(&anx7688->work, anx7688_work);
++	anx7688->last_extcon_state = -1;
++
++	ret = of_property_read_variable_u32_array(dev->of_node, "source-caps",
++						  anx7688->src_caps,
++						  1, ARRAY_SIZE(anx7688->src_caps));
++	if (ret < 0) {
++		dev_err(dev, "failed to get source-caps from DT\n");
++		return ret;
++	}
++	anx7688->n_src_caps = ret;
++
++	ret = of_property_read_variable_u32_array(dev->of_node, "sink-caps",
++						  anx7688->snk_caps,
++						  1, ARRAY_SIZE(anx7688->snk_caps));
++	if (ret < 0) {
++		dev_err(dev, "failed to get sink-caps from DT\n");
++		return ret;
++	}
++	anx7688->n_snk_caps = ret;
++
++	for (i = 0; i < ANX7688_NUM_SUPPLIES; i++)
++		anx7688->supplies[i].supply = anx7688_supply_names[i];
++	ret = devm_regulator_bulk_get(dev, ANX7688_NUM_SUPPLIES,
++				      anx7688->supplies);
++	if (ret)
++		return ret;
++
++	anx7688->vbus_in_supply =
++		devm_power_supply_get_by_phandle(dev, "vbus_in-supply");
++	if (IS_ERR(anx7688->vbus_in_supply)) {
++		dev_err(dev, "Couldn't get the VBUS power supply\n");
++		return PTR_ERR(anx7688->vbus_in_supply);
++	}
++
++	if (!anx7688->vbus_in_supply)
++		return -EPROBE_DEFER;
++
++	anx7688->gpio_enable = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
++	if (IS_ERR(anx7688->gpio_enable)) {
++		dev_err(dev, "Could not get enable gpio\n");
++		return PTR_ERR(anx7688->gpio_enable);
++	}
++
++	anx7688->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
++	if (IS_ERR(anx7688->gpio_reset)) {
++		dev_err(dev, "Could not get reset gpio\n");
++		return PTR_ERR(anx7688->gpio_reset);
++	}
++
++	anx7688->gpio_cabledet = devm_gpiod_get(dev, "cabledet", GPIOD_IN);
++	if (IS_ERR(anx7688->gpio_cabledet)) {
++		dev_err(dev, "Could not get cabledet gpio\n");
++		return PTR_ERR(anx7688->gpio_cabledet);
++	}
++
++	irq_cabledet = gpiod_to_irq(anx7688->gpio_cabledet);
++	if (irq_cabledet < 0) {
++		dev_err(dev, "Could not get cabledet irq\n");
++		return irq_cabledet;
++	}
++
++	ret = devm_device_add_groups(&client->dev, anx7688_groups);
++	if (ret)
++		return ret;
++
++	// Initialize extcon device
++	anx7688->extcon = devm_extcon_dev_allocate(dev, anx7688_extcon_cable);
++	if (IS_ERR(anx7688->extcon))
++		return -ENOMEM;
++
++	ret = devm_extcon_dev_register(dev, anx7688->extcon);
++	if (ret) {
++		dev_err(dev, "failed to register extcon device\n");
++		return ret;
++	}
++
++	// Register the TCPC i2c interface as second interface (0x58)
++	anx7688->client_tcpc = i2c_new_dummy_device(client->adapter, 0x2c);
++	if (IS_ERR(anx7688->client_tcpc)) {
++		dev_err(dev, "Could not register tcpc i2c client\n");
++		return PTR_ERR(anx7688->client_tcpc);
++	}
++	i2c_set_clientdata(anx7688->client_tcpc, anx7688);
++
++	// powerup and probe the ANX chip
++
++	ret = regulator_bulk_enable(ANX7688_NUM_ALWAYS_ON_SUPPLIES,
++				    anx7688->supplies);
++	if (ret) {
++		dev_err(dev, "Could not enable regulators\n");
++		goto err_dummy_dev;
++	}
++
++	msleep(10);
++
++	anx7688_power_enable(anx7688);
++
++	vid_l = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_VENDOR_ID0);
++	vid_h = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_VENDOR_ID1);
++	if (vid_l < 0 || vid_h < 0) {
++		ret = vid_l < 0 ? vid_l : vid_h;
++		anx7688_power_disable(anx7688);
++		goto err_disable_reg;
++	}
++
++	dev_info(dev, "Vendor id 0x%04x\n", vid_l | vid_h << 8);
++
++	anx7688_power_disable(anx7688);
++
++	anx7688->role_sw = usb_role_switch_get(dev);
++	if (IS_ERR(anx7688->role_sw)) {
++		dev_err(dev, "Could not get role switch\n");
++		ret = PTR_ERR(anx7688->role_sw);
++		goto err_disable_reg;
++	}
++
++	// setup a typec port device
++	typec_cap.revision = USB_TYPEC_REV_1_2;
++	typec_cap.pd_revision = 0x200;
++	typec_cap.prefer_role = TYPEC_NO_PREFERRED_ROLE;
++	typec_cap.type = TYPEC_PORT_DRP;
++	typec_cap.data = TYPEC_PORT_DRD;
++	typec_cap.driver_data = anx7688;
++	typec_cap.ops = &anx7688_typec_ops;
++
++	anx7688->port = typec_register_port(dev, &typec_cap);
++	if (IS_ERR(anx7688->port)) {
++		dev_err(dev, "Could not register type-c port\n");
++		ret = PTR_ERR(anx7688->port);
++		goto err_role_sw;
++	}
++
++	anx7688->pwr_role = TYPEC_SINK;
++	anx7688->data_role = TYPEC_DEVICE;
++	typec_set_pwr_role(anx7688->port, anx7688->pwr_role);
++	typec_set_data_role(anx7688->port, anx7688->data_role);
++	typec_set_pwr_opmode(anx7688->port, TYPEC_PWR_MODE_USB);
++	typec_set_vconn_role(anx7688->port, TYPEC_SINK);
++
++	// make sure BC1.2 detection in PMIC is enabled
++	anx7688->last_bc_result = -1;
++	psy_val.intval = 1;
++	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_USB_BC_ENABLED,
++					&psy_val);
++	if (ret) {
++		dev_err(anx7688->dev, "failed to enable BC1.2 detection\n");
++		goto err_cport;
++	}
++
++	ret = devm_request_irq(dev, irq_cabledet, anx7688_irq_plug_handler,
++			       IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
++			       "anx7688-cabledet", anx7688);
++	if (ret < 0) {
++		dev_err(dev, "Could not request cabledet irq (%d)\n", ret);
++		goto err_cport;
++	}
++
++	ret = devm_request_threaded_irq(dev, client->irq,
++					NULL, anx7688_irq_status_handler,
++					IRQF_ONESHOT, NULL, anx7688);
++	if (ret < 0) {
++		dev_err(dev, "Could not request irq (%d)\n", ret);
++		goto err_cport;
++	}
++
++	anx7688->vbus_in_nb.notifier_call = anx7688_vbus_in_notify;
++	anx7688->vbus_in_nb.priority = 0;
++	ret = power_supply_reg_notifier(&anx7688->vbus_in_nb);
++	if (ret)
++		goto err_cport;
++
++	anx7688->debug_root = debugfs_create_dir("anx7688", NULL);
++	debugfs_create_file("firmware", 0444, anx7688->debug_root, anx7688,
++			    &anx7688_firmware_fops);
++	debugfs_create_file("regs", 0444, anx7688->debug_root, anx7688,
++			    &anx7688_regs_fops);
++	debugfs_create_file("status", 0444, anx7688->debug_root, anx7688,
++			    &anx7688_status_fops);
++
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(10));
++
++	timer_setup(&anx7688->work_timer, anx7688_cabledet_timer_fn, 0);
++	mod_timer(&anx7688->work_timer, jiffies + msecs_to_jiffies(1000));
++
++	return 0;
++
++err_cport:
++	typec_unregister_port(anx7688->port);
++err_role_sw:
++	usb_role_switch_put(anx7688->role_sw);
++err_disable_reg:
++	regulator_bulk_disable(ANX7688_NUM_ALWAYS_ON_SUPPLIES, anx7688->supplies);
++err_dummy_dev:
++	i2c_unregister_device(anx7688->client_tcpc);
++	return ret;
++}
++
++static void anx7688_i2c_remove(struct i2c_client *client)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(client);
++
++	mutex_lock(&anx7688->lock);
++
++	power_supply_unreg_notifier(&anx7688->vbus_in_nb);
++
++	del_timer_sync(&anx7688->work_timer);
++
++	cancel_delayed_work_sync(&anx7688->work);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	typec_unregister_partner(anx7688->partner);
++	typec_unregister_port(anx7688->port);
++	usb_role_switch_put(anx7688->role_sw);
++
++	regulator_bulk_disable(ANX7688_NUM_ALWAYS_ON_SUPPLIES, anx7688->supplies);
++	i2c_unregister_device(anx7688->client_tcpc);
++
++	debugfs_remove(anx7688->debug_root);
++
++	mutex_unlock(&anx7688->lock);
++}
++
++static int __maybe_unused anx7688_suspend(struct device *dev)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++
++	del_timer_sync(&anx7688->work_timer);
++	cancel_delayed_work_sync(&anx7688->work);
++
++	regulator_disable(anx7688->supplies[ANX7688_I2C_INDEX].consumer);
++
++	return 0;
++}
++
++static int __maybe_unused anx7688_resume(struct device *dev)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++	int ret;
++
++	ret = regulator_enable(anx7688->supplies[ANX7688_I2C_INDEX].consumer);
++	if (ret)
++		dev_warn(anx7688->dev,
++			 "failed to enable I2C regulator (%d)\n", ret);
++
++	// check status right after resume, since it could have changed during
++	// sleep
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(50));
++	mod_timer(&anx7688->work_timer, jiffies + msecs_to_jiffies(1000));
++
++	return 0;
++}
++
++static const struct dev_pm_ops anx7688_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(anx7688_suspend, anx7688_resume)
++};
++
++static const struct i2c_device_id anx7688_ids[] = {
++	{ "anx7688", 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, anx7688_ids);
++
++static struct of_device_id anx7688_of_match_table[] = {
++	{ .compatible = "analogix,anx7688" },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, anx7688_of_match_table);
++
++static struct i2c_driver anx7688_driver = {
++	.driver = {
++		.name = "anx7688",
++		.of_match_table = anx7688_of_match_table,
++		.pm = &anx7688_pm_ops,
++	},
++	.probe = anx7688_i2c_probe,
++	.remove = anx7688_i2c_remove,
++	.id_table = anx7688_ids,
++};
++
++module_i2c_driver(anx7688_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Martijn Braam <martijn@brixit.nl>");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("Analogix ANX7688 USB-C DisplayPort bridge");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
new file mode 100644
index 000000000000..96957653ae96
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
@@ -0,0 +1,110 @@
+From c8993a9ec5df164b1c7aefb1d12746ceded213f1 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 15 Mar 2024 23:05:10 +0100
+Subject: usb: typec: anx7688: Port to Linux 6.9
+
+POWER_SUPPLY_PROP_USB_BC_ENABLED is no longer needed, nor supported
+by axp20x driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/anx7688.c | 51 ++++---------------------------------
+ 1 file changed, 5 insertions(+), 46 deletions(-)
+
+diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c
+index fa1d3496af73..77c154565340 100644
+--- a/drivers/usb/typec/anx7688.c
++++ b/drivers/usb/typec/anx7688.c
+@@ -636,14 +636,6 @@ static void anx7688_disconnect(struct anx7688 *anx7688)
+ 	if (ret)
+ 		dev_err(dev, "failed to offline vbus_in\n");
+ 
+-	val.intval = 1;
+-	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
+-	ret = power_supply_set_property(anx7688->vbus_in_supply,
+-					POWER_SUPPLY_PROP_USB_BC_ENABLED,
+-					&val);
+-	if (ret)
+-		dev_err(dev, "failed to enabled USB BC1.2 detection\n");
+-
+ 	clear_bit(ANX7688_F_CONNECTED, anx7688->flags);
+ }
+ 
+@@ -1822,17 +1814,8 @@ static void anx7688_handle_current_update(struct anx7688* anx7688)
+ 
+ 	if (current_limit) {
+ 		/*
+-		 * Disable BC1.2 detection, because we'll be setting
+-		 * a current limit determined by USB-PD
++		 * Set a current limit determined by USB-PD
+ 		 */
+-		val.intval = 0;
+-		dev_dbg(dev, "disabling USB BC 1.2 detection\n");
+-		ret = power_supply_set_property(anx7688->vbus_in_supply,
+-						POWER_SUPPLY_PROP_USB_BC_ENABLED,
+-						&val);
+-		if (ret)
+-			dev_err(dev, "failed to disable USB BC1.2 detection\n");
+-
+ 		val.intval = current_limit * 1000;
+ 		dev_dbg(dev, "setting vbus_in current limit to %d mA\n", current_limit);
+ 		ret = power_supply_set_property(anx7688->vbus_in_supply,
+@@ -1846,27 +1829,13 @@ static void anx7688_handle_current_update(struct anx7688* anx7688)
+ 		 * Use the result of BC1.2 detection performed by PMIC.
+ 		 */
+ 		ret = power_supply_get_property(anx7688->vbus_in_supply,
+-						POWER_SUPPLY_PROP_USB_BC_ENABLED,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
+ 						&val);
+ 		if (ret)
+-			dev_err(dev, "failed to get USB BC1.2 detection status\n");
+-
+-		if (ret != 0 || val.intval == 0) {
+-			/*
+-			 * If BC is disabled or we can't get its status,
+-			 * set conservative 500mA limit. Otherwise leave
+-			 * the limit to BC1.2.
+-			 */
+-			val.intval = 500 * 1000;
+-			dev_dbg(dev, "setting vbus_in current limit to %d mA\n",
++			dev_err(dev, "failed to get vbus_in current limit\n");
++		if (ret == 0)
++			dev_dbg(dev, "vbus_in current limit is %d mA\n",
+ 				val.intval / 1000);
+-			ret = power_supply_set_property(anx7688->vbus_in_supply,
+-							POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
+-							&val);
+-			if (ret)
+-				dev_err(dev, "failed to set vbus_in current to %d mA\n",
+-					val.intval / 1000);
+-		}
+ 	}
+ 
+ 	/* Turn on VBUS power path inside PMIC. */
+@@ -1932,7 +1901,6 @@ static int anx7688_i2c_probe(struct i2c_client *client)
+ 	struct anx7688 *anx7688;
+ 	struct device *dev = &client->dev;
+ 	struct typec_capability typec_cap = { };
+-	union power_supply_propval psy_val;
+ 	int i, vid_h, vid_l;
+ 	int irq_cabledet;
+ 	int ret = 0;
+@@ -2087,15 +2055,6 @@ static int anx7688_i2c_probe(struct i2c_client *client)
+ 
+ 	// make sure BC1.2 detection in PMIC is enabled
+ 	anx7688->last_bc_result = -1;
+-	psy_val.intval = 1;
+-	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
+-	ret = power_supply_set_property(anx7688->vbus_in_supply,
+-					POWER_SUPPLY_PROP_USB_BC_ENABLED,
+-					&psy_val);
+-	if (ret) {
+-		dev_err(anx7688->dev, "failed to enable BC1.2 detection\n");
+-		goto err_cport;
+-	}
+ 
+ 	ret = devm_request_irq(dev, irq_cabledet, anx7688_irq_plug_handler,
+ 			       IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
new file mode 100644
index 000000000000..04345e7819fa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
@@ -0,0 +1,38 @@
+From b4f4f82b7f957eddcf9546c687ff28c1002069d1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 14 Nov 2021 01:14:25 +0100
+Subject: usb: typec: fusb302: Add OF extcon support
+
+It's possible to create a dependency cycle between fusb302 and
+other drivers via extcon device, so we retrieve the device on
+demand after probe and not during probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 35ddbaf50f64..954803316d5e 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -518,6 +518,16 @@ static int tcpm_get_current_limit(struct tcpc_dev *dev)
+ 	int current_limit = 0;
+ 	unsigned long timeout;
+ 
++	/*
++	 * To avoid cycles in OF dependencies, we get extcon when necessary
++	 * outside of probe function.
++	 */
++	if (of_property_read_bool(chip->dev->of_node, "extcon") && !chip->extcon) {
++		chip->extcon = extcon_get_edev_by_phandle(chip->dev, 0);
++		if (IS_ERR(chip->extcon))
++			chip->extcon = NULL;
++	}
++
+ 	if (!chip->extcon)
+ 		return 0;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
new file mode 100644
index 000000000000..83771e2672b2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
@@ -0,0 +1,40 @@
+From 79673232787f3e91b78e3c4f5ae2f9bdc6a3b505 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 20 Nov 2021 14:35:10 +0100
+Subject: usb: typec: fusb302: Clear interrupts before we start toggling
+
+This is recommended by the datasheet.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 954803316d5e..ab9b01a490cc 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -586,6 +586,7 @@ static int fusb302_set_toggling(struct fusb302_chip *chip,
+ 				enum toggling_mode mode)
+ {
+ 	int ret = 0;
++	u8 reg;
+ 
+ 	/* first disable toggling */
+ 	ret = fusb302_i2c_clear_bits(chip, FUSB_REG_CONTROL2,
+@@ -644,6 +645,12 @@ static int fusb302_set_toggling(struct fusb302_chip *chip,
+ 	} else {
+ 		/* Datasheet says vconn MUST be off when toggling */
+ 		WARN(chip->vconn_on, "Vconn is on during toggle start");
++
++		/* clear interrupts */
++                ret = fusb302_i2c_read(chip, FUSB_REG_INTERRUPT, &reg);
++		if (ret < 0)
++			return ret;
++
+ 		/* unmask TOGDONE interrupt */
+ 		ret = fusb302_i2c_clear_bits(chip, FUSB_REG_MASKA,
+ 					     FUSB_REG_MASKA_TOGDONE);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
new file mode 100644
index 000000000000..82369e39adfc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
@@ -0,0 +1,112 @@
+From 9931add2797b681e4341e5d89c60ea2bd7abe2b3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 7 Nov 2021 19:29:06 +0100
+Subject: usb: typec: fusb302: Extend debugging interface with driver state
+ dumps
+
+This is useful for debugging.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 78 ++++++++++++++++++++++++++++++++
+ 1 file changed, 78 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 24962413fe2c..3061eb699f1a 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -207,6 +207,81 @@ static int fusb302_debug_show(struct seq_file *s, void *v)
+ }
+ DEFINE_SHOW_ATTRIBUTE(fusb302_debug);
+ 
++static const char * const typec_cc_status_name[];
++static const char * const cc_polarity_name[];
++static const char * const toggling_mode_name[] = {
++	[TOGGLING_MODE_OFF] = "Off",
++	[TOGGLING_MODE_DRP] = "DRP",
++	[TOGGLING_MODE_SNK] = "SNK",
++	[TOGGLING_MODE_SRC] = "SRC",
++};
++static const char * const src_current_status_name[] = {
++	[SRC_CURRENT_DEFAULT] = "Default",
++	[SRC_CURRENT_MEDIUM] = "Medium",
++	[SRC_CURRENT_HIGH] = "High",
++};
++
++#define FUSB_REG(n) { n, #n },
++struct fusb_reg {
++	u8 addr;
++	const char* name;
++} fusb_regs[] = {
++	FUSB_REG(FUSB_REG_DEVICE_ID)
++	FUSB_REG(FUSB_REG_SWITCHES0)
++	FUSB_REG(FUSB_REG_SWITCHES1)
++	FUSB_REG(FUSB_REG_MEASURE)
++	FUSB_REG(FUSB_REG_CONTROL0)
++	FUSB_REG(FUSB_REG_CONTROL1)
++	FUSB_REG(FUSB_REG_CONTROL2)
++	FUSB_REG(FUSB_REG_CONTROL3)
++	FUSB_REG(FUSB_REG_MASK)
++	FUSB_REG(FUSB_REG_POWER)
++	FUSB_REG(FUSB_REG_RESET)
++	FUSB_REG(FUSB_REG_MASKA)
++	FUSB_REG(FUSB_REG_MASKB)
++	FUSB_REG(FUSB_REG_STATUS0A)
++	FUSB_REG(FUSB_REG_STATUS1A)
++	FUSB_REG(FUSB_REG_INTERRUPTA)
++	FUSB_REG(FUSB_REG_INTERRUPTB)
++	FUSB_REG(FUSB_REG_STATUS0)
++	FUSB_REG(FUSB_REG_STATUS1)
++	FUSB_REG(FUSB_REG_INTERRUPT)
++};
++
++static int fusb302_i2c_read(struct fusb302_chip *chip,
++			    u8 address, u8 *data);
++
++static int fusb302_debug_regs_show(struct seq_file *s, void *v)
++{
++	struct fusb302_chip *chip = (struct fusb302_chip *)s->private;
++	int i, ret;
++
++	seq_printf(s, "chip->intr_togdone = %d\n", chip->intr_togdone);
++	seq_printf(s, "chip->intr_bc_lvl = %d\n", chip->intr_bc_lvl);
++	seq_printf(s, "chip->intr_comp_chng = %d\n", chip->intr_comp_chng);
++	seq_printf(s, "chip->vconn_on = %d\n", chip->vconn_on);
++	seq_printf(s, "chip->vbus_on = %d\n", chip->vbus_on);
++	seq_printf(s, "chip->charge_on = %d\n", chip->charge_on);
++	seq_printf(s, "chip->vbus_present = %d\n", chip->vbus_present);
++	seq_printf(s, "chip->cc_polarity = %s\n", cc_polarity_name[chip->cc_polarity]);
++	seq_printf(s, "chip->cc1 = %s\n", typec_cc_status_name[chip->cc1]);
++	seq_printf(s, "chip->cc2 = %s\n", typec_cc_status_name[chip->cc2]);
++	seq_printf(s, "chip->toggling_mode = %s\n", toggling_mode_name[chip->toggling_mode]);
++	seq_printf(s, "chip->src_current_status = %s\n", src_current_status_name[chip->src_current_status]);
++
++	seq_printf(s, "\nRegisters:\n");
++        for (i = 0; i < ARRAY_SIZE(fusb_regs); i++) {
++		u8 val = 0;
++
++		ret = fusb302_i2c_read(chip, fusb_regs[i].addr, &val);
++		if (ret >= 0)
++			seq_printf(s, "%s = %02hhx\n", fusb_regs[i].name, val);
++	}
++
++	return 0;
++}
++DEFINE_SHOW_ATTRIBUTE(fusb302_debug_regs);
++
+ static void fusb302_debugfs_init(struct fusb302_chip *chip)
+ {
+ 	char name[NAME_MAX];
+@@ -216,6 +291,9 @@ static void fusb302_debugfs_init(struct fusb302_chip *chip)
+ 	chip->dentry = debugfs_create_dir(name, usb_debug_root);
+ 	debugfs_create_file("log", S_IFREG | 0444, chip->dentry, chip,
+ 			    &fusb302_debug_fops);
++
++	debugfs_create_file("regs", S_IFREG | 0444, chip->dentry, chip,
++			    &fusb302_debug_regs_fops);
+ }
+ 
+ static void fusb302_debugfs_exit(struct fusb302_chip *chip)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
new file mode 100644
index 000000000000..5819b880f1b7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
@@ -0,0 +1,49 @@
+From c60914f92ad14f2d24d2c54a77e6d944a8978c85 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 20 Nov 2021 14:33:58 +0100
+Subject: usb: typec: fusb302: Fix register definitions
+
+MEASURE_VBUS bit is at position 6. MDAC bits are also wrong.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302_reg.h | 16 +++++++---------
+ 1 file changed, 7 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302_reg.h b/drivers/usb/typec/tcpm/fusb302_reg.h
+index edc0e4b0f1e6..f37d226c5027 100644
+--- a/drivers/usb/typec/tcpm/fusb302_reg.h
++++ b/drivers/usb/typec/tcpm/fusb302_reg.h
+@@ -27,14 +27,13 @@
+ #define FUSB_REG_SWITCHES1_TXCC2_EN		BIT(1)
+ #define FUSB_REG_SWITCHES1_TXCC1_EN		BIT(0)
+ #define FUSB_REG_MEASURE			0x04
+-#define FUSB_REG_MEASURE_MDAC5			BIT(7)
+-#define FUSB_REG_MEASURE_MDAC4			BIT(6)
+-#define FUSB_REG_MEASURE_MDAC3			BIT(5)
+-#define FUSB_REG_MEASURE_MDAC2			BIT(4)
+-#define FUSB_REG_MEASURE_MDAC1			BIT(3)
+-#define FUSB_REG_MEASURE_MDAC0			BIT(2)
+-#define FUSB_REG_MEASURE_VBUS			BIT(1)
+-#define FUSB_REG_MEASURE_XXXX5			BIT(0)
++#define FUSB_REG_MEASURE_VBUS			BIT(6)
++#define FUSB_REG_MEASURE_MDAC5			BIT(5)
++#define FUSB_REG_MEASURE_MDAC4			BIT(4)
++#define FUSB_REG_MEASURE_MDAC3			BIT(3)
++#define FUSB_REG_MEASURE_MDAC2			BIT(2)
++#define FUSB_REG_MEASURE_MDAC1			BIT(1)
++#define FUSB_REG_MEASURE_MDAC0			BIT(0)
+ #define FUSB_REG_CONTROL0			0x06
+ #define FUSB_REG_CONTROL0_TX_FLUSH		BIT(6)
+ #define FUSB_REG_CONTROL0_INT_MASK		BIT(5)
+@@ -105,7 +104,6 @@
+ #define FUSB_REG_STATUS0A_RX_SOFT_RESET		BIT(1)
+ #define FUSB_REG_STATUS0A_RX_HARD_RESET		BIT(0)
+ #define FUSB_REG_STATUS1A			0x3D
+-#define FUSB_REG_STATUS1A_TOGSS			BIT(3)
+ #define FUSB_REG_STATUS1A_TOGSS_RUNNING		0x0
+ #define FUSB_REG_STATUS1A_TOGSS_SRC1		0x1
+ #define FUSB_REG_STATUS1A_TOGSS_SRC2		0x2
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
new file mode 100644
index 000000000000..36b35f8fada0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
@@ -0,0 +1,189 @@
+From 893eb740c7d807611296f7a8115286059c0cf367 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:55:34 +0100
+Subject: usb: typec: fusb302: More useful of logging status on interrupt
+
+This is just for debugging. It prints more info that's useful to
+see how hardware state changes in time.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 121 ++++++++++++++++++++++++++-----
+ 1 file changed, 104 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 0779e9eabf60..32d894e1b247 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -68,7 +68,7 @@ static const u8 rd_mda_value[] = {
+ };
+ 
+ #define LOG_BUFFER_ENTRIES	1024
+-#define LOG_BUFFER_ENTRY_SIZE	128
++#define LOG_BUFFER_ENTRY_SIZE	256
+ 
+ struct fusb302_chip {
+ 	struct device *dev;
+@@ -1598,6 +1598,84 @@ static irqreturn_t fusb302_irq_intn(int irq, void *dev_id)
+ 	return IRQ_HANDLED;
+ }
+ 
++static void fusb302_print_state(struct fusb302_chip *chip)
++{
++	u8 ctl0, ctl2, measure, status0, status1a, sw0, mask;
++	int ret;
++
++	ret = fusb302_i2c_read(chip, FUSB_REG_CONTROL0, &ctl0);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_CONTROL2, &ctl2);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_MEASURE, &measure);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS1A, &status1a);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_SWITCHES0, &sw0);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_MASK, &mask);
++	if (ret < 0)
++		return;
++
++	//FUSB_REG(FUSB_REG_POWER) // power control
++
++	const char* host_cur = "?";
++	switch ((ctl0 >> 2) & 3) {
++	case 0: host_cur = "none"; break;
++	case 1: host_cur = "80uA"; break;
++	case 2: host_cur = "160uA"; break;
++	case 3: host_cur = "330uA"; break;
++	}
++
++	const char* bc_lvl = "?";
++	switch (status0 & 3) {
++	case 0: bc_lvl = "0-200mV"; break;
++	case 1: bc_lvl = "200-660mV"; break;
++	case 2: bc_lvl = "660-1230mV"; break;
++	case 3: bc_lvl = ">1230mV"; break;
++	}
++
++	// status0
++	unsigned vbusok = !!(status0 & BIT(7));
++	unsigned activity = !!(status0 & BIT(6));
++	unsigned comp = !!(status0 & BIT(5));
++	unsigned wake = !!(status0 & BIT(2));
++
++	// measure
++	unsigned mdac = ((measure & 0x3f) + 1) * 42 * (measure & BIT(6) ? 10 : 1);
++
++	// status1a
++	unsigned togss = (status1a >> 3) & 7;
++	const char* togss_s = "?";
++	switch (togss) {
++	case 0: togss_s = "running"; break;
++	case 1: togss_s = "src1"; break;
++	case 2: togss_s = "src2"; break;
++	case 5: togss_s = "snk1"; break;
++	case 6: togss_s = "snk2"; break;
++	case 7: togss_s = "audio"; break;
++	}
++
++	// ctl2 print as is
++
++#define SW(n) (!!(sw0 & BIT(n)))
++
++	fusb302_log(chip, "state: cc(puen=%u%u vconn=%u%u meas=%u%u pdwn=%u%u) "
++		    "host_cur=%s mdac=%umV comp=%u bc_lvl=%s vbusok=%u act=%u "
++		    "wake=%u togss=%s ctl2=0x%02x mask=0x%02x",
++		    SW(6), SW(7), SW(4), SW(5), SW(2), SW(3), SW(0), SW(1),
++		    host_cur, mdac, comp, bc_lvl, vbusok, activity,
++		    wake, togss_s, ctl2, mask);
++}
++
+ static void fusb302_irq_work(struct work_struct *work)
+ {
+ 	struct fusb302_chip *chip = container_of(work, struct fusb302_chip,
+@@ -1607,6 +1685,7 @@ static void fusb302_irq_work(struct work_struct *work)
+ 	u8 interrupta;
+ 	u8 interruptb;
+ 	u8 status0;
++	u8 mda;
+ 	bool vbus_present;
+ 	bool comp_result;
+ 	bool intr_togdone;
+@@ -1632,9 +1711,10 @@ static void fusb302_irq_work(struct work_struct *work)
+ 	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
+ 	if (ret < 0)
+ 		goto done;
+-	fusb302_log(chip,
+-		    "IRQ: 0x%02x, a: 0x%02x, b: 0x%02x, status0: 0x%02x",
+-		    interrupt, interrupta, interruptb, status0);
++	fusb302_log(chip, "IRQ: 0x%02x, a: 0x%02x, b: 0x%02x",
++		    interrupt, interrupta, interruptb);
++
++	fusb302_print_state(chip);
+ 
+ 	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK) {
+ 		vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
+@@ -1646,32 +1726,39 @@ static void fusb302_irq_work(struct work_struct *work)
+ 		}
+ 	}
+ 
+-	if ((interrupta & FUSB_REG_INTERRUPTA_TOGDONE) && intr_togdone) {
++	if (interrupta & FUSB_REG_INTERRUPTA_TOGDONE) {
+ 		fusb302_log(chip, "IRQ: TOGDONE");
+-		ret = fusb302_handle_togdone(chip);
+-		if (ret < 0) {
+-			fusb302_log(chip,
+-				    "handle togdone error, ret=%d", ret);
+-			goto done;
++		if (intr_togdone) {
++			ret = fusb302_handle_togdone(chip);
++			if (ret < 0) {
++				fusb302_log(chip,
++					    "handle togdone error, ret=%d", ret);
++				goto done;
++			}
+ 		}
+ 	}
+ 
+-	if ((interrupt & FUSB_REG_INTERRUPT_BC_LVL) && intr_bc_lvl) {
++	if (interrupt & FUSB_REG_INTERRUPT_BC_LVL) {
+ 		fusb302_log(chip, "IRQ: BC_LVL, handler pending");
+ 		/*
+ 		 * as BC_LVL interrupt can be affected by PD activity,
+ 		 * apply delay to for the handler to wait for the PD
+ 		 * signaling to finish.
+ 		 */
+-		mod_delayed_work(chip->wq, &chip->bc_lvl_handler,
+-				 msecs_to_jiffies(T_BC_LVL_DEBOUNCE_DELAY_MS));
++		if (intr_bc_lvl)
++			mod_delayed_work(chip->wq, &chip->bc_lvl_handler,
++					 msecs_to_jiffies(T_BC_LVL_DEBOUNCE_DELAY_MS));
+ 	}
+ 
+-	if ((interrupt & FUSB_REG_INTERRUPT_COMP_CHNG) && intr_comp_chng) {
++	if (interrupt & FUSB_REG_INTERRUPT_COMP_CHNG) {
++		ret = fusb302_i2c_read(chip, FUSB_REG_MEASURE, &mda);
++		if (ret < 0)
++			goto done;
++
+ 		comp_result = !!(status0 & FUSB_REG_STATUS0_COMP);
+-		fusb302_log(chip, "IRQ: COMP_CHNG, comp=%s",
+-			    comp_result ? "true" : "false");
+-		if (comp_result) {
++		fusb302_log(chip, "IRQ: COMP_CHNG, cc* %s mdac (%u mV)",
++			    comp_result ? ">" : "<", ((mda & 0x3f) + 1) * 42 * (mda & BIT(6) ? 10 : 1));
++		if (comp_result && intr_comp_chng) {
+ 			/* cc level > Rd_threshold, detach */
+ 			chip->cc1 = TYPEC_CC_OPEN;
+ 			chip->cc2 = TYPEC_CC_OPEN;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
new file mode 100644
index 000000000000..6de503305c80
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
@@ -0,0 +1,76 @@
+From 3225ef2af398e3e8d0435b652c4d96f1f0566fab Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:53:27 +0100
+Subject: usb: typec: fusb302: Retry reading of CC pins status if activity is
+ detected
+
+This is just for testing, to see if this ever happens. It should
+also help when this happens.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 34 ++++++++++++++++++++++++++++++--
+ 1 file changed, 32 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 3061eb699f1a..0779e9eabf60 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -1317,6 +1317,36 @@ static int fusb302_handle_togdone_snk(struct fusb302_chip *chip,
+ 	return ret;
+ }
+ 
++static int fusb302_get_status0_stable(struct fusb302_chip *chip, u8 *status0)
++{
++	int ret, tries = 0;
++	u8 reg;
++
++try_again:
++	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &reg);
++	if (ret < 0)
++		return ret;
++
++	if (reg & FUSB_REG_STATUS0_ACTIVITY) {
++		fusb302_log(chip, "activity reading CC status");
++		if (++tries == 5) {
++			fusb302_log(chip, "failed to read stable status0 value");
++
++			/*
++			 * The best we can do is to return at least something.
++			 */
++			*status0 = reg;
++			return 0;
++		}
++
++		usleep_range(50, 100);
++		goto try_again;
++	}
++
++	*status0 = reg;
++	return 0;
++}
++
+ /* On error returns < 0, otherwise a typec_cc_status value */
+ static int fusb302_get_src_cc_status(struct fusb302_chip *chip,
+ 				     enum typec_cc_polarity cc_polarity,
+@@ -1344,7 +1374,7 @@ static int fusb302_get_src_cc_status(struct fusb302_chip *chip,
+ 		return ret;
+ 
+ 	usleep_range(50, 100);
+-	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
++	ret = fusb302_get_status0_stable(chip, &status0);
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -1360,7 +1390,7 @@ static int fusb302_get_src_cc_status(struct fusb302_chip *chip,
+ 		return ret;
+ 
+ 	usleep_range(50, 100);
+-	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
++	ret = fusb302_get_status0_stable(chip, &status0);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
new file mode 100644
index 000000000000..c1ae4be648c7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
@@ -0,0 +1,50 @@
+From 5e4afa31fe44347828b0de35604e8fc012e63c8a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 7 Nov 2021 19:28:27 +0100
+Subject: usb: typec: fusb302: Set the current before enabling pullups
+
+This seems more reasonable and should avoid short period of incorrect
+current setting being applied to CC pin.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 00247497bf29..24962413fe2c 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -635,6 +635,14 @@ static int tcpm_set_cc(struct tcpc_dev *dev, enum typec_cc_status cc)
+ 		goto done;
+ 	}
+ 
++	/* adjust current for SRC */
++	ret = fusb302_set_src_current(chip, cc_src_current[cc]);
++	if (ret < 0) {
++		fusb302_log(chip, "cannot set src current %s, ret=%d",
++			    typec_cc_status_name[cc], ret);
++		goto done;
++	}
++
+ 	ret = fusb302_i2c_mask_write(chip, FUSB_REG_SWITCHES0,
+ 				     switches0_mask, switches0_data);
+ 	if (ret < 0) {
+@@ -645,14 +653,6 @@ static int tcpm_set_cc(struct tcpc_dev *dev, enum typec_cc_status cc)
+ 	chip->cc1 = TYPEC_CC_OPEN;
+ 	chip->cc2 = TYPEC_CC_OPEN;
+ 
+-	/* adjust current for SRC */
+-	ret = fusb302_set_src_current(chip, cc_src_current[cc]);
+-	if (ret < 0) {
+-		fusb302_log(chip, "cannot set src current %s, ret=%d",
+-			    typec_cc_status_name[cc], ret);
+-		goto done;
+-	}
+-
+ 	/* enable/disable interrupts, BC_LVL for SNK and COMP_CHNG for SRC */
+ 	switch (cc) {
+ 	case TYPEC_CC_RP_DEF:
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
new file mode 100644
index 000000000000..60fa12bfff86
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
@@ -0,0 +1,33 @@
+From 24c66472d246d318d07c3c6def5d523146f4c9f8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 30 Jan 2022 23:46:37 +0100
+Subject: usb: typec: fusb302: Slightly increase wait time for BC1.2 result
+
+This is not strictly necessary, but it should not hurt. Looking at
+kernel log timing, the BC1.2 detection completion time and this
+timeout are quite tight. This adds some headspace just in case.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index ef18a448b740..00247497bf29 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -445,9 +445,9 @@ static int tcpm_get_current_limit(struct tcpc_dev *dev)
+ 
+ 	/*
+ 	 * USB2 Charger detection may still be in progress when we get here,
+-	 * this can take upto 600ms, wait 800ms max.
++	 * this can take upto 600ms, wait 1000ms max.
+ 	 */
+-	timeout = jiffies + msecs_to_jiffies(800);
++	timeout = jiffies + msecs_to_jiffies(1000);
+ 	do {
+ 		if (extcon_get_state(chip->extcon, EXTCON_CHG_USB_SDP) == 1)
+ 			current_limit = 500;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
new file mode 100644
index 000000000000..d69dfe9a6ca2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
@@ -0,0 +1,43 @@
+From 73be9ad94f5558b66c39d6f035d889ab0424fc5a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:57:06 +0100
+Subject: usb: typec: fusb302: Update VBUS state even if VBUS interrupt is not
+ triggered
+
+This seems to improve robustness.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 32d894e1b247..35ddbaf50f64 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -1716,14 +1716,16 @@ static void fusb302_irq_work(struct work_struct *work)
+ 
+ 	fusb302_print_state(chip);
+ 
+-	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK) {
+-		vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
++	vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
++	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK)
+ 		fusb302_log(chip, "IRQ: VBUS_OK, vbus=%s",
+ 			    vbus_present ? "On" : "Off");
+-		if (vbus_present != chip->vbus_present) {
+-			chip->vbus_present = vbus_present;
+-			tcpm_vbus_change(chip->tcpm_port);
+-		}
++	if (vbus_present != chip->vbus_present) {
++		chip->vbus_present = vbus_present;
++		if (!(interrupt & FUSB_REG_INTERRUPT_VBUSOK))
++		fusb302_log(chip, "IRQ: VBUS changed without interrupt, vbus=%s",
++			    vbus_present ? "On" : "Off");
++		tcpm_vbus_change(chip->tcpm_port);
+ 	}
+ 
+ 	if (interrupta & FUSB_REG_INTERRUPTA_TOGDONE) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
new file mode 100644
index 000000000000..bf02b43031d0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
@@ -0,0 +1,95 @@
+From 1930e81875511a7e26bbdce7161d3330f8b5551b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 18 Feb 2023 00:38:44 +0100
+Subject: usb: typec: tcpm: Fix PD devices/capabilities registration
+
+Unregister caps before registering them. Store NULL to the struct
+if registration fails, so that next attempt can succeed.
+
+Fixes "sysfs: cannot create duplicate filename
+'/devices/virtual/usb_power_delivery/pd1/source-capabilities'" error.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 37 +++++++++++++++++++++++++++--------
+ 1 file changed, 29 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index b60bc1be25dc..138d8c857827 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -3008,15 +3008,22 @@ static int tcpm_register_source_caps(struct tcpm_port *port)
+ 	struct usb_power_delivery_desc desc = { port->negotiated_rev };
+ 	struct usb_power_delivery_capabilities_desc caps = { };
+ 	struct usb_power_delivery_capabilities *cap;
++	struct usb_power_delivery *partner_pd;
++
++	if (!port->partner_pd) {
++		partner_pd = usb_power_delivery_register(NULL, &desc);
++		if (IS_ERR(partner_pd))
++			return PTR_ERR(partner_pd);
+ 
+-	if (!port->partner_pd)
+-		port->partner_pd = usb_power_delivery_register(NULL, &desc);
+-	if (IS_ERR(port->partner_pd))
+-		return PTR_ERR(port->partner_pd);
++		port->partner_pd = partner_pd;
++	}
+ 
+ 	memcpy(caps.pdo, port->source_caps, sizeof(u32) * port->nr_source_caps);
+ 	caps.role = TYPEC_SOURCE;
+ 
++	usb_power_delivery_unregister_capabilities(port->partner_source_caps);
++	port->partner_source_caps = NULL;
++
+ 	cap = usb_power_delivery_register_capabilities(port->partner_pd, &caps);
+ 	if (IS_ERR(cap))
+ 		return PTR_ERR(cap);
+@@ -3031,15 +3038,22 @@ static int tcpm_register_sink_caps(struct tcpm_port *port)
+ 	struct usb_power_delivery_desc desc = { port->negotiated_rev };
+ 	struct usb_power_delivery_capabilities_desc caps = { };
+ 	struct usb_power_delivery_capabilities *cap;
++	struct usb_power_delivery *partner_pd;
++
++	if (!port->partner_pd) {
++		partner_pd = usb_power_delivery_register(NULL, &desc);
++		if (IS_ERR(partner_pd))
++			return PTR_ERR(partner_pd);
+ 
+-	if (!port->partner_pd)
+-		port->partner_pd = usb_power_delivery_register(NULL, &desc);
+-	if (IS_ERR(port->partner_pd))
+-		return PTR_ERR(port->partner_pd);
++		port->partner_pd = partner_pd;
++	}
+ 
+ 	memcpy(caps.pdo, port->sink_caps, sizeof(u32) * port->nr_sink_caps);
+ 	caps.role = TYPEC_SINK;
+ 
++	usb_power_delivery_unregister_capabilities(port->partner_sink_caps);
++	port->partner_sink_caps = NULL;
++
+ 	cap = usb_power_delivery_register_capabilities(port->partner_pd, &caps);
+ 	if (IS_ERR(cap))
+ 		return PTR_ERR(cap);
+@@ -6991,10 +7005,17 @@ static int tcpm_port_register_pd(struct tcpm_port *port)
+ 		port->pds[i] = usb_power_delivery_register(port->dev, &desc);
+ 		if (IS_ERR(port->pds[i])) {
+ 			ret = PTR_ERR(port->pds[i]);
++			port->pds[i] = NULL;
+ 			goto err_unregister;
+ 		}
+ 		port->pd_list[i]->pd = port->pds[i];
+ 
++		usb_power_delivery_unregister_capabilities(port->pd_list[i]->source_cap);
++		port->pd_list[i]->source_cap = NULL;
++
++		usb_power_delivery_unregister_capabilities(port->pd_list[i]->sink_cap);
++		port->pd_list[i]->sink_cap = NULL;
++
+ 		if (port->pd_list[i]->source_desc.pdo[0]) {
+ 			cap = usb_power_delivery_register_capabilities(port->pds[i],
+ 								&port->pd_list[i]->source_desc);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-tcpm-Improve-logs.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-tcpm-Improve-logs.patch
new file mode 100644
index 000000000000..2151a03657ca
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-tcpm-Improve-logs.patch
@@ -0,0 +1,64 @@
+From 4aa4799440d1d9787ab7c6aed62037989a95bb09 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:58:05 +0100
+Subject: usb: typec: tcpm: Improve logs
+
+This adds clarity to debugging.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 15 +++++++++++----
+ 1 file changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index 00d27b5b5e75..59ff22f77346 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -957,10 +957,13 @@ static int tcpm_pd_transmit(struct tcpm_port *port,
+ 		break;
+ 	}
+ 
+-	if (msg)
++	if (msg) {
+ 		tcpm_log(port, "PD TX, header: %#x", le16_to_cpu(msg->header));
+-	else
++		for (ret = 0; ret < pd_header_cnt_le(msg->header); ret++)
++			tcpm_log(port, "  tx payload[%d]: %#x", ret, le32_to_cpu(msg->payload[ret]));
++	} else {
+ 		tcpm_log(port, "PD TX, type: %#x", tx_sop_type);
++	}
+ 
+ 	reinit_completion(&port->tx_complete);
+ 	ret = port->tcpc->pd_transmit(port->tcpc, tx_sop_type, msg, negotiated_rev);
+@@ -3679,6 +3682,10 @@ void tcpm_pd_receive(struct tcpm_port *port, const struct pd_message *msg,
+ 		     enum tcpm_transmit_type rx_sop_type)
+ {
+ 	struct pd_rx_event *event;
++	int ret;
++
++	for (ret = 0; ret < pd_header_cnt_le(msg->header); ret++)
++		tcpm_log(port, "  rx payload[%d]: %#x", ret, le32_to_cpu(msg->payload[ret]));
+ 
+ 	event = kzalloc(sizeof(*event), GFP_ATOMIC);
+ 	if (!event)
+@@ -5938,7 +5945,7 @@ static void _tcpm_cc_change(struct tcpm_port *port, enum typec_cc_status cc1,
+ 
+ static void _tcpm_pd_vbus_on(struct tcpm_port *port)
+ {
+-	tcpm_log_force(port, "VBUS on");
++	tcpm_log_force(port, "VBUS event received: on");
+ 	port->vbus_present = true;
+ 	/*
+ 	 * When vbus_present is true i.e. Voltage at VBUS is greater than VSAFE5V implicitly
+@@ -6028,7 +6035,7 @@ static void _tcpm_pd_vbus_on(struct tcpm_port *port)
+ 
+ static void _tcpm_pd_vbus_off(struct tcpm_port *port)
+ {
+-	tcpm_log_force(port, "VBUS off");
++	tcpm_log_force(port, "VBUS event received: off");
+ 	port->vbus_present = false;
+ 	port->vbus_never_low = false;
+ 	switch (port->state) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
new file mode 100644
index 000000000000..b21530a75a3d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
@@ -0,0 +1,52 @@
+From c781838b17f1f3bc61898f63bf18e63526c55d46 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 14 Aug 2022 16:23:28 +0200
+Subject: usb: typec: tcpm: Unregister altmodes before registering new ones
+
+Just in case there are already altmodes registered. Otherwise the
+kernel will fail with:
+
+[50554.467172] sysfs: cannot create duplicate filename '/bus/typec/devices/port0-partner.0'
+[50554.467198] CPU: 2 PID: 897 Comm: 4-0022 Tainted: G         C        5.18.15-1-MANJARO-ARM #1
+[50554.467208] Hardware name: Pine64 PinePhonePro (DT)
+[50554.467214] Call trace:
+[50554.467218]  dump_backtrace.part.0+0xcc/0xe0
+[50554.467241]  show_stack+0x18/0x6c
+[50554.467249]  dump_stack_lvl+0x64/0x80
+[50554.467262]  dump_stack+0x18/0x34
+[50554.467270]  sysfs_warn_dup+0x60/0x7c
+[50554.467279]  sysfs_do_create_link_sd+0xf0/0x100
+[50554.467286]  sysfs_create_link+0x24/0x44
+[50554.467292]  bus_add_device+0x64/0x120
+[50554.467304]  device_add+0x320/0x890
+[50554.467312]  device_register+0x20/0x30
+[50554.467318]  typec_register_altmode+0x1e4/0x35c
+[50554.467330]  typec_partner_register_altmode+0x10/0x20
+[50554.467339]  tcpm_pd_rx_handler+0x1804/0x18e0
+[50554.467346]  kthread_worker_fn+0xa0/0x180
+[50554.467357]  kthread+0x108/0x10c
+[50554.467364]  ret_from_fork+0x10/0x20
+[50554.467528] typec port0-partner: failed to register alternate mode (-17)
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index f3c298f07cef..f456bf22958e 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -1751,6 +1751,9 @@ static void tcpm_register_partner_altmodes(struct tcpm_port *port)
+ 		return;
+ 
+ 	for (i = 0; i < modep->altmodes; i++) {
++		typec_unregister_altmode(port->partner_altmode[i]);
++		port->partner_altmode[i] = NULL;
++
+ 		altmode = typec_partner_register_altmode(port->partner,
+ 						&modep->altmode_desc[i]);
+ 		if (IS_ERR(altmode)) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
new file mode 100644
index 000000000000..b55e3ec6f7dd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
@@ -0,0 +1,386 @@
+From 88437c6823849224624bbf2a20f34d6444889b2d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 7 Nov 2021 19:24:40 +0100
+Subject: usb: typec: typec-extcon: Add typec -> extcon bridge driver
+
+This bridge connects standard Type C port interfaces for controling
+muxes, switches and usb roles to muxes, switches and usb role
+drivers controlled via extcon interface.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/Kconfig        |   7 +
+ drivers/usb/typec/Makefile       |   1 +
+ drivers/usb/typec/typec-extcon.c | 332 +++++++++++++++++++++++++++++++
+ 3 files changed, 340 insertions(+)
+ create mode 100644 drivers/usb/typec/typec-extcon.c
+
+diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig
+index 982b7c444a1f..9913435a0fd9 100644
+--- a/drivers/usb/typec/Kconfig
++++ b/drivers/usb/typec/Kconfig
+@@ -122,6 +122,13 @@ config TYPEC_WUSB3801
+ 	  If you choose to build this driver as a dynamically linked module, the
+ 	  module will be called wusb3801.ko.
+ 
++config TYPEC_EXTCON
++	tristate "Type-C switch/mux -> extcon interface bridge driver"
++	depends on USB_ROLE_SWITCH
++	help
++	  Say Y or M here if your system needs bridging between typec class
++	  and extcon interfaces.
++
+ source "drivers/usb/typec/mux/Kconfig"
+ 
+ source "drivers/usb/typec/altmodes/Kconfig"
+diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile
+index 3f8ff94ad294..0b2d1d251c53 100644
+--- a/drivers/usb/typec/Makefile
++++ b/drivers/usb/typec/Makefile
+@@ -12,4 +12,5 @@ obj-$(CONFIG_TYPEC_HD3SS3220)	+= hd3ss3220.o
+ obj-$(CONFIG_TYPEC_STUSB160X) 	+= stusb160x.o
+ obj-$(CONFIG_TYPEC_RT1719)	+= rt1719.o
+ obj-$(CONFIG_TYPEC_WUSB3801)	+= wusb3801.o
++obj-$(CONFIG_TYPEC_EXTCON)	+= typec-extcon.o
+ obj-$(CONFIG_TYPEC)		+= mux/
+diff --git a/drivers/usb/typec/typec-extcon.c b/drivers/usb/typec/typec-extcon.c
+new file mode 100644
+index 000000000000..e460f35c8390
+--- /dev/null
++++ b/drivers/usb/typec/typec-extcon.c
+@@ -0,0 +1,332 @@
++/*
++ * typec -> extcon bridge
++ * Copyright (c) 2021 Ondřej Jirman <megi@xff.cz>
++ *
++ * This driver bridges standard type-c interfaces to drivers that
++ * expect extcon interface.
++ */
++
++#include <linux/delay.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/power_supply.h>
++#include <linux/platform_device.h>
++#include <linux/usb/pd.h>
++#include <linux/usb/role.h>
++#include <linux/usb/typec.h>
++#include <linux/usb/typec_dp.h>
++#include <linux/usb/typec_mux.h>
++#include <linux/extcon-provider.h>
++
++struct typec_extcon {
++        struct device *dev;
++
++	/* consumers */
++	struct usb_role_switch *role_sw;
++        struct typec_switch_dev *sw;
++        struct typec_mux_dev *mux;
++
++	/* providers */
++	struct extcon_dev *extcon;
++	struct notifier_block extcon_nb;
++
++	/* cached state from typec controller */
++	enum usb_role role;
++	enum typec_orientation orientation;
++	struct typec_altmode alt;
++	unsigned long mode;
++	bool has_alt;
++	struct mutex lock;
++};
++
++static const unsigned int typec_extcon_cable[] = {
++	EXTCON_DISP_DP,
++
++	EXTCON_USB,
++	EXTCON_USB_HOST,
++
++	EXTCON_CHG_USB_SDP,
++	EXTCON_CHG_USB_CDP,
++	EXTCON_CHG_USB_DCP,
++	EXTCON_CHG_USB_ACA,
++
++	EXTCON_NONE,
++};
++
++static void typec_extcon_set_cable(struct typec_extcon *tce, int id, bool on,
++				   union extcon_property_value prop_ss,
++				   union extcon_property_value prop_or)
++{
++	union extcon_property_value cur_ss, cur_or;
++	bool prop_diff = false;
++	int ret;
++
++	ret = extcon_get_property(tce->extcon, id,
++				  EXTCON_PROP_USB_SS, &cur_ss);
++	if (ret || cur_ss.intval != prop_ss.intval)
++		prop_diff = true;
++
++	ret = extcon_get_property(tce->extcon, id,
++				  EXTCON_PROP_USB_TYPEC_POLARITY, &cur_or);
++	if (ret || cur_or.intval != prop_or.intval)
++		prop_diff = true;
++
++	if (!on && extcon_get_state(tce->extcon, id)) {
++		extcon_set_state_sync(tce->extcon, id, false);
++	} else if (on && (!extcon_get_state(tce->extcon, id) || prop_diff)) {
++		extcon_set_state(tce->extcon, id, true);
++		extcon_set_property(tce->extcon, id,
++				    EXTCON_PROP_USB_SS, prop_ss);
++		extcon_set_property(tce->extcon, id,
++				    EXTCON_PROP_USB_TYPEC_POLARITY, prop_or);
++		extcon_sync(tce->extcon, id);
++	}
++}
++
++static int typec_extcon_sync_extcon(struct typec_extcon *tce)
++{
++	union extcon_property_value prop_ss, prop_or;
++	bool has_dp = false;
++
++        mutex_lock(&tce->lock);
++
++	/* connector is disconnected */
++	if (tce->orientation == TYPEC_ORIENTATION_NONE) {
++		typec_extcon_set_cable(tce, EXTCON_USB, false, prop_ss, prop_or);
++		typec_extcon_set_cable(tce, EXTCON_USB_HOST, false, prop_ss, prop_or);
++		typec_extcon_set_cable(tce, EXTCON_DISP_DP, false, prop_ss, prop_or);
++
++                goto out_unlock;
++	}
++
++	prop_or.intval = tce->orientation == TYPEC_ORIENTATION_NORMAL ? 0 : 1;
++	prop_ss.intval = 0;
++
++	if (tce->has_alt && tce->alt.svid == USB_TYPEC_DP_SID) {
++		switch (tce->mode) {
++		case TYPEC_STATE_SAFE:
++			break;
++		case TYPEC_DP_STATE_C:
++		case TYPEC_DP_STATE_E:
++			has_dp = true;
++			break;
++		case TYPEC_DP_STATE_D:
++			has_dp = true;
++			fallthrough;
++		case TYPEC_STATE_USB:
++			prop_ss.intval = 1;
++			break;
++		default:
++			dev_err(tce->dev, "unhandled mux mode=%lu\n", tce->mode);
++			break;
++		}
++	}
++
++	typec_extcon_set_cable(tce, EXTCON_USB,
++			tce->role == USB_ROLE_DEVICE, prop_ss, prop_or);
++	typec_extcon_set_cable(tce, EXTCON_USB_HOST,
++			tce->role == USB_ROLE_HOST, prop_ss, prop_or);
++
++	typec_extcon_set_cable(tce, EXTCON_DISP_DP, has_dp, prop_ss, prop_or);
++
++out_unlock:
++	mutex_unlock(&tce->lock);
++	return 0;
++}
++
++static int typec_extcon_sw_set(struct typec_switch_dev *sw,
++			       enum typec_orientation orientation)
++{
++        struct typec_extcon *tce = typec_switch_get_drvdata(sw);
++
++	dev_dbg(tce->dev, "SW SET: orientation=%d\n", orientation);
++
++        mutex_lock(&tce->lock);
++	tce->orientation = orientation;
++        mutex_unlock(&tce->lock);
++
++	typec_extcon_sync_extcon(tce);
++
++        return 0;
++}
++
++static int typec_extcon_mux_set(struct typec_mux_dev *mux,
++				struct typec_mux_state *state)
++{
++        struct typec_extcon *tce = typec_mux_get_drvdata(mux);
++	struct typec_altmode *alt = state->alt;
++
++	dev_dbg(tce->dev, "MUX SET: state->mode=%lu\n", state->mode);
++	if (alt)
++		dev_dbg(tce->dev, "      ...alt: svid=%04hx mode=%d vdo=%08x active=%u\n",
++			alt->svid, alt->mode, alt->vdo, alt->active);
++
++        mutex_lock(&tce->lock);
++	tce->mode = state->mode;
++	tce->has_alt = alt != NULL;
++        if (alt)
++		tce->alt = *alt;
++	mutex_unlock(&tce->lock);
++
++	typec_extcon_sync_extcon(tce);
++
++        return 0;
++}
++
++static int typec_extcon_usb_set_role(struct usb_role_switch *sw,
++				     enum usb_role role)
++{
++        struct typec_extcon *tce = usb_role_switch_get_drvdata(sw);
++
++	dev_dbg(tce->dev, "ROLE SET: role=%d\n", role);
++
++        mutex_lock(&tce->lock);
++	tce->role = role;
++	mutex_unlock(&tce->lock);
++
++	typec_extcon_sync_extcon(tce);
++
++        return 0;
++}
++
++static int typec_extcon_notifier(struct notifier_block *nb,
++					 unsigned long action, void *data)
++{
++	struct typec_extcon *tce = container_of(nb, struct typec_extcon, extcon_nb);
++
++	bool sdp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_SDP);
++	bool cdp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_CDP);
++	bool dcp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_DCP);
++	bool usb = extcon_get_state(tce->extcon, EXTCON_USB);
++	bool usb_host = extcon_get_state(tce->extcon, EXTCON_USB_HOST);
++	bool dp = extcon_get_state(tce->extcon, EXTCON_DISP_DP);
++
++	dev_info(tce->dev, "extcon changed sdp=%d cdp=%d dcp=%d usb=%d usb_host=%d dp=%d\n",
++		 sdp, cdp, dcp, usb, usb_host, dp);
++
++	return NOTIFY_OK;
++}
++
++static int typec_extcon_probe(struct platform_device *pdev)
++{
++        struct typec_switch_desc sw_desc = { };
++        struct typec_mux_desc mux_desc = { };
++        struct usb_role_switch_desc role_desc = { };
++        struct device *dev = &pdev->dev;
++        struct typec_extcon *tce;
++        int ret = 0;
++
++        tce = devm_kzalloc(dev, sizeof(*tce), GFP_KERNEL);
++        if (!tce)
++                return -ENOMEM;
++
++        tce->dev = &pdev->dev;
++	mutex_init(&tce->lock);
++	tce->mode = TYPEC_STATE_SAFE;
++
++	sw_desc.drvdata = tce;
++	sw_desc.fwnode = dev->fwnode;
++	sw_desc.set = typec_extcon_sw_set;
++
++	tce->sw = typec_switch_register(dev, &sw_desc);
++	if (IS_ERR(tce->sw))
++		return dev_err_probe(dev, PTR_ERR(tce->sw),
++				     "Error registering typec switch\n");
++
++	mux_desc.drvdata = tce;
++	mux_desc.fwnode = dev->fwnode;
++	mux_desc.set = typec_extcon_mux_set;
++
++	tce->mux = typec_mux_register(dev, &mux_desc);
++	if (IS_ERR(tce->mux)) {
++		ret = dev_err_probe(dev, PTR_ERR(tce->mux),
++				    "Error registering typec mux\n");
++		goto err_sw;
++	}
++
++	role_desc.driver_data = tce;
++	role_desc.fwnode = dev->fwnode;
++	role_desc.name = fwnode_get_name(dev->fwnode);
++	role_desc.set = typec_extcon_usb_set_role;
++
++	tce->role_sw = usb_role_switch_register(dev, &role_desc);
++	if (IS_ERR(tce->role_sw)) {
++		ret = dev_err_probe(dev, PTR_ERR(tce->role_sw),
++				    "Error registering USB role switch\n");
++		goto err_mux;
++	}
++
++	tce->extcon = devm_extcon_dev_allocate(dev, typec_extcon_cable);
++	if (IS_ERR(tce->extcon)) {
++		ret = PTR_ERR(tce->extcon);
++		goto err_role;
++	}
++
++	ret = devm_extcon_dev_register(dev, tce->extcon);
++	if (ret) {
++		ret = dev_err_probe(dev, ret, "failed to register extcon device\n");
++		goto err_role;
++	}
++
++	extcon_set_property_capability(tce->extcon, EXTCON_USB,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(tce->extcon, EXTCON_USB,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++	extcon_set_property_capability(tce->extcon, EXTCON_USB_HOST,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(tce->extcon, EXTCON_USB_HOST,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++	extcon_set_property_capability(tce->extcon, EXTCON_DISP_DP,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(tce->extcon, EXTCON_DISP_DP,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++
++	tce->extcon_nb.notifier_call = typec_extcon_notifier;
++	ret = devm_extcon_register_notifier_all(dev, tce->extcon, &tce->extcon_nb);
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to register extcon notifier\n");
++		goto err_role;
++	}
++
++	return 0;
++
++err_role:
++	usb_role_switch_unregister(tce->role_sw);
++err_mux:
++	typec_mux_unregister(tce->mux);
++err_sw:
++	typec_switch_unregister(tce->sw);
++	return ret;
++}
++
++static int typec_extcon_remove(struct platform_device *pdev)
++{
++        struct typec_extcon *tce = platform_get_drvdata(pdev);
++
++	usb_role_switch_unregister(tce->role_sw);
++	typec_mux_unregister(tce->mux);
++	typec_switch_unregister(tce->sw);
++
++        return 0;
++}
++
++static struct of_device_id typec_extcon_of_match_table[] = {
++        { .compatible = "linux,typec-extcon-bridge" },
++        { },
++};
++MODULE_DEVICE_TABLE(of, typec_extcon_of_match_table);
++
++static struct platform_driver typec_extcon_driver = {
++        .driver = {
++                .name = "typec-extcon",
++                .of_match_table = typec_extcon_of_match_table,
++        },
++        .probe = typec_extcon_probe,
++        .remove = typec_extcon_remove,
++};
++
++module_platform_driver(typec_extcon_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("typec -> extcon bridge driver");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
new file mode 100644
index 000000000000..8b528eaf4357
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
@@ -0,0 +1,48 @@
+From 14847c84d63fa48069eea7b1ae85d37ce5e9e165 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 9 Feb 2023 20:33:50 +0100
+Subject: usb: typec: typec-extcon: Allow to force reset on each mux change
+
+This may help with some Alt-DP USB adapters.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/typec-extcon.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/usb/typec/typec-extcon.c b/drivers/usb/typec/typec-extcon.c
+index 12be8f203f76..d5a7f40f0921 100644
+--- a/drivers/usb/typec/typec-extcon.c
++++ b/drivers/usb/typec/typec-extcon.c
+@@ -19,6 +19,10 @@
+ #include <linux/usb/typec_mux.h>
+ #include <linux/extcon-provider.h>
+ 
++static bool reset_on_mux;
++module_param(reset_on_mux, bool, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(reset_on_mux, "Set DP=0 on each type-c mux change");
++
+ struct typec_extcon {
+         struct device *dev;
+ 
+@@ -162,6 +166,17 @@ static int typec_extcon_mux_set(struct typec_mux_dev *mux,
+ 		dev_dbg(tce->dev, "      ...alt: svid=%04hx mode=%d vdo=%08x active=%u\n",
+ 			alt->svid, alt->mode, alt->vdo, alt->active);
+ 
++        mutex_lock(&tce->lock);
++	if (reset_on_mux && alt != NULL && tce->has_alt) {
++		tce->mode = state->mode;
++		tce->has_alt = false;
++		mutex_unlock(&tce->lock);
++
++		typec_extcon_sync_extcon(tce);
++	} else {
++		mutex_unlock(&tce->lock);
++	}
++
+         mutex_lock(&tce->lock);
+ 	tce->mode = state->mode;
+ 	tce->has_alt = alt != NULL;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
new file mode 100644
index 000000000000..2fcafac16d0e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
@@ -0,0 +1,25 @@
+From a07ff0e803570818a7ac15de90fac9cc0f6ccb65 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 23 Mar 2022 14:21:34 +0100
+Subject: usb: typec: typec-extcon: Enable debugging for now
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/typec-extcon.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/typec/typec-extcon.c b/drivers/usb/typec/typec-extcon.c
+index e460f35c8390..12be8f203f76 100644
+--- a/drivers/usb/typec/typec-extcon.c
++++ b/drivers/usb/typec/typec-extcon.c
+@@ -5,6 +5,7 @@
+  * This driver bridges standard type-c interfaces to drivers that
+  * expect extcon interface.
+  */
++#define DEBUG
+ 
+ #include <linux/delay.h>
+ #include <linux/kernel.h>
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch b/patch/kernel/archive/sunxi-6.9/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
new file mode 100644
index 000000000000..6c60ead3b843
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
@@ -0,0 +1,126 @@
+From 3be5f8b5ede7e6587e4655301b32b03569ca7038 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 7 Jun 2021 20:27:07 +0200
+Subject: video: pwm_bl: Allow to change lth_brightness via sysfs
+
+Read minimum duty cycle in % from DT, and allow to change it via
+sysfs.
+
+Minimum brightness calibration instructions:
+
+  echo 1 > /sys/class/backlight/backlight/brightness
+
+  echo 1 > /sys/class/backlight/backlight/device/lth_brightness
+  echo 2 > /sys/class/backlight/backlight/device/lth_brightness
+  echo 3 > /sys/class/backlight/backlight/device/lth_brightness
+
+  .... increase values until you like the minimum brightness
+
+Then make sure to restore this value after each boot by writing it to
+/sys/class/backlight/backlight/device/lth_brightness
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/video/backlight/pwm_bl.c | 72 +++++++++++++++++++++++++++++++-
+ 1 file changed, 70 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
+index aea5227e3fc0..b0b34c6e8338 100644
+--- a/drivers/video/backlight/pwm_bl.c
++++ b/drivers/video/backlight/pwm_bl.c
+@@ -448,6 +448,61 @@ static int pwm_backlight_initial_power_state(const struct pwm_bl_data *pb)
+ 	return active ? FB_BLANK_UNBLANK: FB_BLANK_POWERDOWN;
+ }
+ 
++static ssize_t lth_brightness_show(struct device *dev,
++				   struct device_attribute *attr, char *buf)
++{
++	struct backlight_device *bl = platform_get_drvdata(to_platform_device(dev));
++	struct pwm_bl_data *pb = bl ? bl_get_data(bl) : NULL;
++	struct pwm_state state;
++	unsigned val;
++
++	if (!pb)
++		return -EBUSY;
++
++	pwm_get_state(pb->pwm, &state);
++	val = div_u64(100 * pb->lth_brightness, state.period);
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n", val);
++}
++
++static ssize_t lth_brightness_store(struct device *dev,
++				    struct device_attribute *attr,
++				    const char *buf, size_t len)
++{
++	struct backlight_device *bl = platform_get_drvdata(to_platform_device(dev));
++	struct pwm_bl_data *pb = bl ? bl_get_data(bl) : NULL;
++	struct pwm_state state;
++	unsigned val;
++	int ret;
++
++	if (!pb)
++		return -EBUSY;
++
++	ret = kstrtouint(buf, 10, &val);
++	if (ret)
++		return ret;
++
++        if (val > 100)
++		val = 100;
++
++	pwm_get_state(pb->pwm, &state);
++	pb->lth_brightness = div_u64(val * state.period, 100);
++	pwm_backlight_update_status(bl);
++
++	return len;
++}
++
++static DEVICE_ATTR_RW(lth_brightness);
++
++static struct attribute *pwm_bl_attrs[] = {
++	&dev_attr_lth_brightness.attr,
++	NULL,
++};
++
++static const struct attribute_group pwm_bl_group = {
++	.attrs = pwm_bl_attrs,
++};
++
+ static int pwm_backlight_probe(struct platform_device *pdev)
+ {
+ 	struct platform_pwm_backlight_data *data = dev_get_platdata(&pdev->dev);
+@@ -456,6 +511,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	struct backlight_device *bl;
+ 	struct pwm_bl_data *pb;
+ 	struct pwm_state state, state_real;
++	u32 lth_brightness;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -596,8 +652,20 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 		pb->scale = data->max_brightness;
+ 	}
+ 
+-	pb->lth_brightness = data->lth_brightness * (div_u64(state.period,
+-				pb->scale));
++	pb->lth_brightness = div_u64(data->lth_brightness * state.period, pb->scale);
++
++	ret = of_property_read_u32(pdev->dev.of_node, "lth-brightness",
++				   &lth_brightness);
++	if (ret == 0) {
++		if (lth_brightness > 100)
++			lth_brightness = 100;
++
++		pb->lth_brightness = div_u64(lth_brightness * state.period, 100);
++	}
++
++	ret = devm_device_add_group(&pdev->dev, &pwm_bl_group);
++	if (ret)
++		goto err_alloc;
+ 
+ 	props.type = BACKLIGHT_RAW;
+ 	props.max_brightness = data->max_brightness;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/Sound-for-H616-H618-Allwinner-SOCs-arch-arm64-boot-dts-allwinne.patch b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/Sound-for-H616-H618-Allwinner-SOCs-arch-arm64-boot-dts-allwinne.patch
new file mode 100644
index 000000000000..ce86532651d6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/Sound-for-H616-H618-Allwinner-SOCs-arch-arm64-boot-dts-allwinne.patch
@@ -0,0 +1,5452 @@
+From 1a8ee4f49169293e1144c2297db537a1e7de63ed Mon Sep 17 00:00:00 2001
+From: Stephen Graf <stephen.graf@gmail.com>
+Date: Thu, 9 May 2024 20:59:34 -0700
+Subject: Sound for H616, H618 Allwinner SOCs
+
+Signed-off-by: Stephen Graf <stephen.graf@gmail.com>
+---
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  |   18 +
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi |   83 +
+ drivers/clk/sunxi-ng/ccu-sun50i-h616.c        |   33 +-
+ include/sound/soc-dai.h                       |   13 +
+ sound/soc/Kconfig                             |    1 +
+ sound/soc/Makefile                            |    1 +
+ sound/soc/soc-core.c                          |   25 +
+ sound/soc/sunxi/Kconfig                       |    8 +
+ sound/soc/sunxi/Makefile                      |    1 +
+ sound/soc/sunxi/sun50iw9-codec.c              | 1093 ++++++++++++
+ sound/soc/sunxi_v2/Kconfig                    |   48 +
+ sound/soc/sunxi_v2/Makefile                   |   11 +
+ sound/soc/sunxi_v2/drv_hdmi.h                 |   63 +
+ sound/soc/sunxi_v2/snd_sunxi_ahub.c           | 1477 +++++++++++++++++
+ sound/soc/sunxi_v2/snd_sunxi_ahub.h           |   67 +
+ sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c       |  534 ++++++
+ sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h       |  291 ++++
+ sound/soc/sunxi_v2/snd_sunxi_common.c         |  267 +++
+ sound/soc/sunxi_v2/snd_sunxi_common.h         |   67 +
+ sound/soc/sunxi_v2/snd_sunxi_log.h            |   29 +
+ sound/soc/sunxi_v2/snd_sunxi_mach.c           |  479 ++++++
+ sound/soc/sunxi_v2/snd_sunxi_mach.h           |   17 +
+ sound/soc/sunxi_v2/snd_sunxi_mach_utils.c     |  422 +++++
+ sound/soc/sunxi_v2/snd_sunxi_mach_utils.h     |  116 ++
+ 24 files changed, 5147 insertions(+), 17 deletions(-)
+ create mode 100644 sound/soc/sunxi/sun50iw9-codec.c
+ create mode 100644 sound/soc/sunxi_v2/Kconfig
+ create mode 100644 sound/soc/sunxi_v2/Makefile
+ create mode 100644 sound/soc/sunxi_v2/drv_hdmi.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_common.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_common.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_log.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach_utils.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach_utils.h
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index ce3dc6d9cd66..23553f2249c2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -105,6 +105,24 @@ &de {
+ 	status = "okay";
+ };
+ 
++&codec {
++        allwinner,audio-routing =
++                "Line Out", "LINEOUT";
++        status = "okay";
++};
++
++&ahub_dam_plat {
++        status = "okay";
++};
++
++&ahub1_plat {
++        status = "okay";
++};
++
++&ahub1_mach {
++        status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 90e55a6aef1d..3df5b74bf306 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -182,6 +182,78 @@ dma: dma-controller@3002000 {
+ 			#dma-cells = <1>;
+ 		};
+ 
++                codec: codec@05096000 {
++                        #sound-dai-cells = <0>;
++                        compatible = "allwinner,sun50i-h616-codec";
++                        reg = <0x05096000 0x31c>;
++                        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++                        clocks = <&ccu CLK_BUS_AUDIO_CODEC>,
++                                 <&ccu CLK_AUDIO_CODEC_1X>,
++                                 <&ccu CLK_AUDIO_CODEC_4X>;
++                        clock-names = "apb", "audio-codec-1x", "audio-codec-4x";
++                        resets = <&ccu RST_BUS_AUDIO_CODEC>;
++                        dmas = <&dma 6>;
++                        dma-names = "tx";
++                        status = "disabled";
++                };
++
++                ahub_dam_plat:ahub_dam_plat@5097000 {
++                        #sound-dai-cells = <0>;
++                        /* sound card without pcm for hardware mix setting */
++                        compatible      = "allwinner,sunxi-snd-plat-ahub_dam";
++                        reg             = <0x05097000 0x1000>;
++                        resets          = <&ccu RST_BUS_AUDIO_HUB>;
++                        clocks          = <&ccu CLK_AUDIO_CODEC_1X>,
++                                          <&ccu CLK_AUDIO_CODEC_4X>,
++                                          <&ccu CLK_AUDIO_HUB>,
++                                          <&ccu CLK_BUS_AUDIO_HUB>;
++                        clock-names     = "clk_pll_audio",
++                                          "clk_pll_audio_4x",
++                                          "clk_audio_hub",
++                                          "clk_bus_audio_hub";
++                        status          = "disabled";
++                };
++
++                ahub1_plat:ahub1_plat {
++                        #sound-dai-cells = <0>;
++                        compatible      = "allwinner,sunxi-snd-plat-ahub";
++                        apb_num         = <1>;  /* for dma port 4 */
++                        dmas            = <&dma 4>, <&dma 4>;
++                        dma-names       = "tx", "rx";
++                        playback_cma    = <128>;
++                        capture_cma     = <128>;
++                        tx_fifo_size    = <128>;
++                        rx_fifo_size    = <128>;
++
++                        tdm_num         = <1>;
++                        tx_pin          = <0>;
++                        rx_pin          = <0>;
++                        status          = "disabled";
++                };
++
++                ahub1_mach:ahub1_mach {
++                        compatible = "allwinner,sunxi-snd-mach";
++                        soundcard-mach,name = "HDMI";
++
++                        soundcard-mach,format           = "i2s";
++                        soundcard-mach,frame-master     = <&ahub1_cpu>;
++                        soundcard-mach,bitclock-master  = <&ahub1_cpu>;
++                        /* soundcard-mach,frame-inversion; */
++                        /* soundcard-mach,bitclock-inversion; */
++                        soundcard-mach,slot-num         = <2>;
++                        soundcard-mach,slot-width       = <32>;
++                        status          = "disabled";
++                        ahub1_cpu: soundcard-mach,cpu {
++                                sound-dai = <&ahub1_plat>;
++                                soundcard-mach,pll-fs   = <4>;
++                                soundcard-mach,mclk-fs  = <0>;
++                        };
++
++                        ahub1_codec: soundcard-mach,codec {
++                                sound-dai = <&hdmi>;
++                        };
++                };
++
+ 		gpu: gpu@1800000 {
+ 			compatible = "allwinner,sun50i-h616-mali",
+ 				     "arm,mali-bifrost";
+@@ -457,6 +529,17 @@ gic: interrupt-controller@3021000 {
+ 			#interrupt-cells = <3>;
+ 		};
+ 
++                iommu: iommu@30f0000 {
++                        compatible = "allwinner,sun50i-h616-iommu",
++                                     "allwinner,sun50i-h6-iommu";
++                        reg = <0x030f0000 0x10000>;
++                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
++                        clocks = <&ccu CLK_BUS_IOMMU>;
++                        resets = <&ccu RST_BUS_IOMMU>;
++                        #iommu-cells = <1>;
++                        status = "okay";
++                };
++
+ 		mmc0: mmc@4020000 {
+ 			compatible = "allwinner,sun50i-h616-mmc",
+ 				     "allwinner,sun50i-a100-mmc";
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+index 21e918582aa5..ab2628596b36 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+@@ -215,20 +215,22 @@ static struct ccu_nkmp pll_de_clk = {
+ 	},
+ };
+ 
+-/*
+- * TODO: Determine SDM settings for the audio PLL. The manual suggests
+- * PLL_FACTOR_N=16, PLL_POST_DIV_P=2, OUTPUT_DIV=2, pattern=0xe000c49b
+- * for 24.576 MHz, and PLL_FACTOR_N=22, PLL_POST_DIV_P=3, OUTPUT_DIV=2,
+- * pattern=0xe001288c for 22.5792 MHz.
+- * This clashes with our fixed PLL_POST_DIV_P.
+- */
+ #define SUN50I_H616_PLL_AUDIO_REG	0x078
++
++static struct ccu_sdm_setting pll_audio_sdm_table[] = {
++        { .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 },
++        { .rate = 98304000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
++};
++
+ static struct ccu_nm pll_audio_hs_clk = {
+ 	.enable		= BIT(31),
+ 	.lock		= BIT(28),
+ 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
+-	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
++        .m              = _SUNXI_CCU_DIV(16, 6),
++        .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table,
++                                         BIT(24), 0x178, BIT(31)),
+ 	.common		= {
++                .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
+ 		.reg		= 0x078,
+ 		.hw.init	= CLK_HW_INIT("pll-audio-hs", "osc24M",
+ 					      &ccu_nm_ops,
+@@ -688,13 +690,13 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
+  */
+ static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x",
+ 			    clk_parent_pll_audio,
+-			    96, 1, CLK_SET_RATE_PARENT);
++                            4, 1, CLK_SET_RATE_PARENT);
+ static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ 			    clk_parent_pll_audio,
+-			    48, 1, CLK_SET_RATE_PARENT);
++                            2, 1, CLK_SET_RATE_PARENT);
+ static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ 			    clk_parent_pll_audio,
+-			    24, 1, CLK_SET_RATE_PARENT);
++                            1, 1, CLK_SET_RATE_PARENT);
+ 
+ static const struct clk_hw *pll_periph0_parents[] = {
+ 	&pll_periph0_clk.common.hw
+@@ -1130,13 +1132,10 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev)
+ 		writel(val, reg + usb2_clk_regs[i]);
+ 	}
+ 
+-	/*
+-	 * Force the post-divider of pll-audio to 12 and the output divider
+-	 * of it to 2, so 24576000 and 22579200 rates can be set exactly.
+-	 */
+ 	val = readl(reg + SUN50I_H616_PLL_AUDIO_REG);
+-	val &= ~(GENMASK(21, 16) | BIT(0));
+-	writel(val | (11 << 16) | BIT(0), reg + SUN50I_H616_PLL_AUDIO_REG);
++        val &= ~BIT(1);
++        val |= BIT(0);
++        writel(val, reg + SUN50I_H616_PLL_AUDIO_REG);
+ 
+ 	/*
+ 	 * First clock parent (osc32K) is unusable for CEC. But since there
+diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h
+index adcd8719d343..778751096c23 100644
+--- a/include/sound/soc-dai.h
++++ b/include/sound/soc-dai.h
+@@ -415,6 +415,15 @@ struct snd_soc_dai_driver {
+ 	struct snd_soc_dobj dobj;
+ 	struct of_phandle_args *dai_args;
+ 
++        /* DAI driver callbacks */
++        int (*probe)(struct snd_soc_dai *dai);
++        int (*remove)(struct snd_soc_dai *dai);
++        /* compress dai */
++        int (*compress_new)(struct snd_soc_pcm_runtime *rtd, int num);
++        /* Optional Callback used at pcm creation*/
++        int (*pcm_new)(struct snd_soc_pcm_runtime *rtd,
++                      struct snd_soc_dai *dai);
++
+ 	/* ops */
+ 	const struct snd_soc_dai_ops *ops;
+ 	const struct snd_soc_cdai_ops *cops;
+@@ -425,6 +434,10 @@ struct snd_soc_dai_driver {
+ 	unsigned int symmetric_rate:1;
+ 	unsigned int symmetric_channels:1;
+ 	unsigned int symmetric_sample_bits:1;
++
++        /* probe ordering - for components with runtime dependencies */
++        int probe_order;
++        int remove_order;
+ };
+ 
+ /* for Playback/Capture */
+diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
+index 439fa631c342..7dc3967ccb27 100644
+--- a/sound/soc/Kconfig
++++ b/sound/soc/Kconfig
+@@ -108,6 +108,7 @@ source "sound/soc/starfive/Kconfig"
+ source "sound/soc/sti/Kconfig"
+ source "sound/soc/stm/Kconfig"
+ source "sound/soc/sunxi/Kconfig"
++source "sound/soc/sunxi_v2/Kconfig"
+ source "sound/soc/tegra/Kconfig"
+ source "sound/soc/ti/Kconfig"
+ source "sound/soc/uniphier/Kconfig"
+diff --git a/sound/soc/Makefile b/sound/soc/Makefile
+index 8376fdb217ed..79b48e8b3657 100644
+--- a/sound/soc/Makefile
++++ b/sound/soc/Makefile
+@@ -65,6 +65,7 @@ obj-$(CONFIG_SND_SOC)	+= starfive/
+ obj-$(CONFIG_SND_SOC)	+= sti/
+ obj-$(CONFIG_SND_SOC)	+= stm/
+ obj-$(CONFIG_SND_SOC)	+= sunxi/
++obj-$(CONFIG_SND_SOC)   += sunxi_v2/
+ obj-$(CONFIG_SND_SOC)	+= tegra/
+ obj-$(CONFIG_SND_SOC)	+= ti/
+ obj-$(CONFIG_SND_SOC)	+= uniphier/
+diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
+index e65fe3a7c3e4..f43402e66020 100644
+--- a/sound/soc/soc-core.c
++++ b/sound/soc/soc-core.c
+@@ -2523,6 +2523,7 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component,
+ {
+ 	struct device *dev = component->dev;
+ 	struct snd_soc_dai *dai;
++        struct snd_soc_dai_ops *ops; /* REMOVE ME */
+ 
+ 	lockdep_assert_held(&client_mutex);
+ 
+@@ -2551,6 +2552,30 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component,
+ 	if (!dai->name)
+ 		return NULL;
+ 
++        /* REMOVE ME */
++        if (dai_drv->probe              ||
++            dai_drv->remove             ||
++            dai_drv->compress_new       ||
++            dai_drv->pcm_new            ||
++            dai_drv->probe_order        ||
++            dai_drv->remove_order) {
++
++                ops = devm_kzalloc(dev, sizeof(struct snd_soc_dai_ops), GFP_KERNEL);
++                if (!ops)
++                        return NULL;
++                if (dai_drv->ops)
++                        memcpy(ops, dai_drv->ops, sizeof(struct snd_soc_dai_ops));
++
++                ops->probe              = dai_drv->probe;
++                ops->remove             = dai_drv->remove;
++                ops->compress_new       = dai_drv->compress_new;
++                ops->pcm_new            = dai_drv->pcm_new;
++                ops->probe_order        = dai_drv->probe_order;
++                ops->remove_order       = dai_drv->remove_order;
++
++                dai_drv->ops = ops;
++        }
++
+ 	dai->component = component;
+ 	dai->dev = dev;
+ 	dai->driver = dai_drv;
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index 753c38c5d554..0f6579ea7143 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -10,6 +10,14 @@ config SND_SUN4I_CODEC
+ 	  Select Y or M to add support for the Codec embedded in the Allwinner
+ 	  A10 and affiliated SoCs.
+ 
++config SND_SUN50IW9_CODEC
++        tristate "Allwinner H616 Codec Support"
++        select SND_SOC_GENERIC_DMAENGINE_PCM
++        select REGMAP_MMIO
++        help
++          Select Y or M to add support for the Codec embedded in the Allwinner
++          H616 and affiliated SoCs.
++
+ config SND_SUN8I_CODEC
+ 	tristate "Allwinner SUN8I audio codec"
+ 	depends on OF
+diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
+index b0b976a3d069..f72d94f3004c 100644
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
+ obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-codec.o
++obj-$(CONFIG_SND_SUN50IW9_CODEC) += sun50iw9-codec.o
+ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
+ obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+ obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
+diff --git a/sound/soc/sunxi/sun50iw9-codec.c b/sound/soc/sunxi/sun50iw9-codec.c
+new file mode 100644
+index 000000000000..38b1d3824c20
+--- /dev/null
++++ b/sound/soc/sunxi/sun50iw9-codec.c
+@@ -0,0 +1,1093 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright 2014 Emilio López <emilio@elopez.com.ar>
++ * Copyright 2014 Jon Smirl <jonsmirl@gmail.com>
++ * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
++ * Copyright 2015 Adam Sampson <ats@offog.org>
++ * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
++ * Copyright 2021 gryzun <gryzun_an@rambler.ru>
++ *
++ * Based on the Allwinner SDK driver, released under the GPL.
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/of_platform.h>
++#include <linux/clk.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/gpio/consumer.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/tlv.h>
++#include <sound/initval.h>
++#include <sound/dmaengine_pcm.h>
++
++#define SUNXI_DAC_DPC (0x00)
++#define SUNXI_DAC_DPC_EN_DA (31)
++#define SUNXI_DAC_DPC_DVOL (12)
++#define SUNXI_DAC_DPC_HPF_EN (18)
++
++#define SUNXI_DAC_FIFOC (0x10)
++#define SUNXI_DAC_FIFOC_DAC_FS (29)
++#define SUNXI_DAC_FIFOC_TX_FIFO_MODE (24)
++#define SUNXI_DAC_FIFOC_DRQ_CLR_CNT (21)
++#define SUNXI_DAC_FIFOC_MONO_EN (6)
++#define SUNXI_DAC_FIFOC_TX_SAMPLE_BITS (5)
++#define SUNXI_DAC_FIFOC_DAC_DRQ_EN (4)
++#define SUNXI_DAC_FIFOC_FIFO_FLUSH (0)
++
++#define SUNXI_DAC_FIFO_STA (0x14)
++#define SUNXI_DAC_TXE_INT (3)
++#define SUNXI_DAC_TXU_INT (2)
++#define SUNXI_DAC_TXO_INT (1)
++#define SUNXI_DAC_TXDATA (0x20)
++#define SUNXI_DAC_CNT (0x24)
++#define SUNXI_DAC_DG_REG (0x28)
++#define SUNXI_DAC_DAP_CTL (0xf0)
++
++#define SUNXI_DAC_AC_DAC_REG (0x310)
++#define SUNXI_DAC_LEN (15)
++#define SUNXI_DAC_REN (14)
++#define SUNXI_LINEOUTL_EN (13)
++#define SUNXI_LMUTE (12)
++#define SUNXI_LINEOUTR_EN (11)
++#define SUNXI_RMUTE (10)
++#define SUNXI_RSWITCH (9)
++#define SUNXI_RAMPEN (8)
++#define SUNXI_LINEOUTL_SEL (6)
++#define SUNXI_LINEOUTR_SEL (5)
++#define SUNXI_LINEOUT_VOL (0)
++
++#define SUNXI_DAC_AC_MIXER_REG (0x314)
++#define SUNXI_LMIX_LDAC (21)
++#define SUNXI_LMIX_RDAC (20)
++#define SUNXI_RMIX_RDAC (17)
++#define SUNXI_RMIX_LDAC (16)
++#define SUNXI_LMIXEN (11)
++#define SUNXI_RMIXEN (10)
++
++#define SUNXI_DAC_AC_RAMP_REG (0x31c)
++#define SUNXI_RAMP_STEP (4)
++#define SUNXI_RDEN (0)
++
++#define LABEL(constant)        \
++    {                          \
++#constant, constant, 0 \
++    }
++#define LABEL_END   \
++    {               \
++        NULL, 0, -1 \
++    }
++
++struct audiocodec_reg_label
++{
++    const char *name;
++    const unsigned int address;
++    int value;
++};
++
++static struct audiocodec_reg_label reg_labels[] = {
++    LABEL(SUNXI_DAC_DPC),
++    LABEL(SUNXI_DAC_FIFOC),
++    LABEL(SUNXI_DAC_FIFO_STA),
++    LABEL(SUNXI_DAC_CNT),
++    LABEL(SUNXI_DAC_DG_REG),
++    LABEL(SUNXI_DAC_DAP_CTL),
++    LABEL(SUNXI_DAC_AC_DAC_REG),
++    LABEL(SUNXI_DAC_AC_MIXER_REG),
++    LABEL(SUNXI_DAC_AC_RAMP_REG),
++    LABEL_END,
++};
++
++struct regmap *codec_regmap_debug = NULL;
++
++struct sun50i_h616_codec
++{
++    unsigned char *name;
++    struct device *dev;
++    struct regmap *regmap;
++    struct clk *clk_apb;
++    struct clk *clk_module;
++    struct reset_control *rst;
++    struct gpio_desc *gpio_pa;
++
++    /* ADC_FIFOC register is at different offset on different SoCs */
++    struct regmap_field *reg_adc_fifoc;
++
++    struct snd_dmaengine_dai_dma_data playback_dma_data;
++};
++
++static void sun50i_h616_codec_start_playback(struct sun50i_h616_codec *scodec)
++{
++    /* Flush TX FIFO */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       BIT(SUNXI_DAC_FIFOC_FIFO_FLUSH),
++                       BIT(SUNXI_DAC_FIFOC_FIFO_FLUSH));
++
++    /* Enable DAC DRQ */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN),
++                       BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN));
++}
++
++static void sun50i_h616_codec_stop_playback(struct sun50i_h616_codec *scodec)
++{
++    /* Disable DAC DRQ */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN),
++                       0);
++}
++
++static int sun50i_h616_codec_trigger(struct snd_pcm_substream *substream, int cmd,
++                                     struct snd_soc_dai *dai)
++{
++    struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
++
++    switch (cmd)
++    {
++    case SNDRV_PCM_TRIGGER_START:
++    case SNDRV_PCM_TRIGGER_RESUME:
++    case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN),
++                               (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN));
++        break;
++    case SNDRV_PCM_TRIGGER_STOP:
++    case SNDRV_PCM_TRIGGER_SUSPEND:
++    case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN),
++                               (0x0 << SUNXI_DAC_FIFOC_DAC_DRQ_EN));
++        break;
++    default:
++        return -EINVAL;
++    }
++    return 0;
++}
++
++static int sun50i_h616_codec_prepare(struct snd_pcm_substream *substream,
++                                     struct snd_soc_dai *dai)
++{
++    struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
++
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       (0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH),
++                       (0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH));
++    regmap_write(scodec->regmap, SUNXI_DAC_FIFO_STA,
++                 (0x1 << SUNXI_DAC_TXE_INT | 1 << SUNXI_DAC_TXU_INT | 0x1 << SUNXI_DAC_TXO_INT));
++    regmap_write(scodec->regmap, SUNXI_DAC_CNT, 0);
++
++    return 0;
++}
++
++static unsigned long sun50i_h616_codec_get_mod_freq(struct snd_pcm_hw_params *params)
++{
++    unsigned int rate = params_rate(params);
++
++    switch (rate)
++    {
++    case 176400:
++    case 88200:
++    case 44100:
++    case 33075:
++    case 22050:
++    case 14700:
++    case 11025:
++    case 7350:
++        return 22579200;
++
++    case 192000:
++    case 96000:
++    case 48000:
++    case 32000:
++    case 24000:
++    case 16000:
++    case 12000:
++    case 8000:
++        return 24576000;
++
++    default:
++        return 0;
++    }
++}
++
++static int sun50i_h616_codec_get_hw_rate(struct snd_pcm_hw_params *params)
++{
++    unsigned int rate = params_rate(params);
++
++    switch (rate)
++    {
++    case 192000:
++    case 176400:
++        return 6;
++
++    case 96000:
++    case 88200:
++        return 7;
++
++    case 48000:
++    case 44100:
++        return 0;
++
++    case 32000:
++    case 33075:
++        return 1;
++
++    case 24000:
++    case 22050:
++        return 2;
++
++    case 16000:
++    case 14700:
++        return 3;
++
++    case 12000:
++    case 11025:
++        return 4;
++
++    case 8000:
++    case 7350:
++        return 5;
++
++    default:
++        return -EINVAL;
++    }
++}
++
++static int sun50i_h616_codec_hw_params_playback(struct sun50i_h616_codec *scodec,
++                                                struct snd_pcm_hw_params *params,
++                                                unsigned int hwrate)
++{
++    u32 val;
++
++    /* Set DAC sample rate */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       7 << SUNXI_DAC_FIFOC_DAC_FS,
++                       hwrate << SUNXI_DAC_FIFOC_DAC_FS);
++
++    /* Set the number of channels we want to use */
++    if (params_channels(params) == 1)
++        val = BIT(SUNXI_DAC_FIFOC_MONO_EN);
++    else
++        val = 0;
++
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       BIT(SUNXI_DAC_FIFOC_MONO_EN),
++                       val);
++
++    /* Set the number of sample bits to either 16 or 24 bits */
++    if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32)
++    {
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                           BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS),
++                           BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS));
++
++        /* Set TX FIFO mode to padding the LSBs with 0 */
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                           BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE),
++                           0);
++
++        scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++    }
++    else
++    {
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                           BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS),
++                           0);
++
++        /* Set TX FIFO mode to repeat the MSB */
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                           BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE),
++                           BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE));
++
++        scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++    }
++
++    return 0;
++}
++
++struct sample_rate
++{
++    unsigned int samplerate;
++    unsigned int rate_bit;
++};
++
++static const struct sample_rate sample_rate_conv[] = {
++    {44100, 0},
++    {48000, 0},
++    {8000, 5},
++    {32000, 1},
++    {22050, 2},
++    {24000, 2},
++    {16000, 3},
++    {11025, 4},
++    {12000, 4},
++    {192000, 6},
++    {96000, 7},
++};
++
++static int sun50i_h616_codec_hw_params(struct snd_pcm_substream *substream,
++                                       struct snd_pcm_hw_params *params,
++                                       struct snd_soc_dai *dai)
++{
++    struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
++    unsigned long clk_freq;
++    int ret, hwrate;
++    int i;
++
++    clk_freq = sun50i_h616_codec_get_mod_freq(params);
++    if (!clk_freq)
++        return -EINVAL;
++
++    ret = clk_set_rate(scodec->clk_module, clk_freq * 2);
++    if (ret)
++        return ret;
++
++    hwrate = sun50i_h616_codec_get_hw_rate(params);
++    if (hwrate < 0)
++        return hwrate;
++
++    switch (params_format(params))
++    {
++    case SNDRV_PCM_FORMAT_S16_LE:
++        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++        {
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE),
++                               (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE));
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS),
++                               (0x0 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS));
++        }
++        break;
++    case SNDRV_PCM_FORMAT_S24_LE:
++        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++        {
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE),
++                               (0x0 << SUNXI_DAC_FIFOC_TX_FIFO_MODE));
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS),
++                               (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS));
++        }
++        break;
++    default:
++        break;
++    }
++
++    for (i = 0; i < ARRAY_SIZE(sample_rate_conv); i++)
++    {
++        if (sample_rate_conv[i].samplerate == params_rate(params))
++        {
++            if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++            {
++                regmap_update_bits(scodec->regmap,
++                                   SUNXI_DAC_FIFOC,
++                                   (0x7 << SUNXI_DAC_FIFOC_DAC_FS),
++                                   (sample_rate_conv[i].rate_bit << SUNXI_DAC_FIFOC_DAC_FS));
++            }
++        }
++    }
++
++    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++    {
++        switch (params_channels(params))
++        {
++        case 1:
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_MONO_EN),
++                               (0x1 << SUNXI_DAC_FIFOC_MONO_EN));
++            break;
++        case 2:
++            regmap_update_bits(scodec->regmap,
++                               SUNXI_DAC_FIFOC,
++                               (0x1 << SUNXI_DAC_FIFOC_MONO_EN),
++                               (0x0 << SUNXI_DAC_FIFOC_MONO_EN));
++            break;
++        default:
++            pr_err("[%s] Playback cannot support %d channels.\n",
++                   __func__, params_channels(params));
++            return -EINVAL;
++        }
++    }
++
++    return 0;
++}
++
++static unsigned int sun50i_h616_codec_src_rates[] = {
++    8000, 11025, 12000, 16000, 22050, 24000, 32000,
++    44100, 48000, 96000, 192000};
++
++static struct snd_pcm_hw_constraint_list sun50i_h616_codec_constraints = {
++    .count = ARRAY_SIZE(sun50i_h616_codec_src_rates),
++    .list = sun50i_h616_codec_src_rates,
++};
++
++static int sun50i_h616_codec_startup(struct snd_pcm_substream *substream,
++                                     struct snd_soc_dai *dai)
++{
++    struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
++
++    snd_pcm_hw_constraint_list(substream->runtime, 0,
++                               SNDRV_PCM_HW_PARAM_RATE, &sun50i_h616_codec_constraints);
++
++    /*
++     * Stop issuing DRQ when we have room for less than 16 samples
++     * in our TX FIFO
++     */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC,
++                       3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT,
++                       3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT);
++
++    return clk_prepare_enable(scodec->clk_module);
++}
++
++static void sun50i_h616_codec_shutdown(struct snd_pcm_substream *substream,
++                                       struct snd_soc_dai *dai)
++{
++    struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
++
++    clk_disable_unprepare(scodec->clk_module);
++}
++
++static const struct snd_soc_dai_ops sun50i_h616_codec_dai_ops = {
++    .startup = sun50i_h616_codec_startup,
++    .shutdown = sun50i_h616_codec_shutdown,
++    .trigger = sun50i_h616_codec_trigger,
++    .hw_params = sun50i_h616_codec_hw_params,
++    .prepare = sun50i_h616_codec_prepare,
++};
++
++static struct snd_soc_dai_driver sun50i_h616_codec_dai = {
++    .name = "Codec",
++    .ops = &sun50i_h616_codec_dai_ops,
++    .playback = {
++        .stream_name = "Codec Playback",
++        .channels_min = 1,
++        .channels_max = 2,
++        .rate_min = 8000,
++        .rate_max = 192000,
++        .rates = SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT,
++        .formats = SNDRV_PCM_FMTBIT_S16_LE |
++                   SNDRV_PCM_FMTBIT_S24_LE,
++        .sig_bits = 24,
++    },
++};
++
++static int sunxi_lineout_event(struct snd_soc_dapm_widget *w,
++                               struct snd_kcontrol *k, int event)
++{
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card);
++
++    switch (event)
++    {
++    case SND_SOC_DAPM_POST_PMU:
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG,
++                           (0x1 << SUNXI_RDEN), (0x1 << SUNXI_RDEN));
++        msleep(25);
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN),
++                           (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN));
++        break;
++    case SND_SOC_DAPM_PRE_PMD:
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG,
++                           (0x1 << SUNXI_RDEN), (0x0 << SUNXI_RDEN));
++        msleep(25);
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN),
++                           (0x0 << SUNXI_LINEOUTL_EN) | (0x0 << SUNXI_LINEOUTR_EN));
++
++        break;
++    default:
++        break;
++    }
++
++    return 0;
++}
++
++static const DECLARE_TLV_DB_SCALE(digital_tlv, 0, -116, -7424);
++static const DECLARE_TLV_DB_SCALE(linein_to_l_r_mix_vol_tlv, -450, 150, 0);
++static const DECLARE_TLV_DB_SCALE(fmin_to_l_r_mix_vol_tlv, -450, 150, 0);
++
++static const unsigned int lineout_tlv[] = {
++    TLV_DB_RANGE_HEAD(2),
++    0,
++    0,
++    TLV_DB_SCALE_ITEM(0, 0, 1),
++    1,
++    31,
++    TLV_DB_SCALE_ITEM(-4350, 150, 1),
++};
++
++/*lineoutL mux select */
++const char *const left_lineoutl_text[] = {
++    "LOMixer",
++    "LROMixer",
++};
++
++static const struct soc_enum left_lineout_enum =
++    SOC_ENUM_SINGLE(SUNXI_DAC_AC_DAC_REG, SUNXI_LINEOUTL_SEL,
++                    ARRAY_SIZE(left_lineoutl_text), left_lineoutl_text);
++
++static const struct snd_kcontrol_new left_lineout_mux =
++    SOC_DAPM_ENUM("Left LINEOUT Mux", left_lineout_enum);
++
++/*lineoutR mux select */
++const char *const right_lineoutr_text[] = {
++    "ROMixer",
++    "LROMixer",
++};
++
++static const struct soc_enum right_lineout_enum =
++    SOC_ENUM_SINGLE(SUNXI_DAC_AC_DAC_REG, SUNXI_LINEOUTR_SEL,
++                    ARRAY_SIZE(right_lineoutr_text), right_lineoutr_text);
++
++static const struct snd_kcontrol_new right_lineout_mux =
++    SOC_DAPM_ENUM("Right LINEOUT Mux", right_lineout_enum);
++
++static const struct snd_kcontrol_new sun50i_h616_codec_codec_controls[] = {
++
++    SOC_SINGLE_TLV("digital volume", SUNXI_DAC_DPC,
++                   SUNXI_DAC_DPC_DVOL, 0x3F, 0, digital_tlv),
++
++    SOC_SINGLE_TLV("LINEOUT volume", SUNXI_DAC_AC_DAC_REG,
++                   SUNXI_LINEOUT_VOL, 0x1F, 0, lineout_tlv),
++};
++
++static const struct snd_kcontrol_new left_output_mixer[] = {
++    SOC_DAPM_SINGLE("DACL Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIX_LDAC, 1, 0),
++    SOC_DAPM_SINGLE("DACR Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIX_RDAC, 1, 0),
++};
++
++static const struct snd_kcontrol_new right_output_mixer[] = {
++    SOC_DAPM_SINGLE("DACL Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIX_LDAC, 1, 0),
++    SOC_DAPM_SINGLE("DACR Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIX_RDAC, 1, 0),
++};
++
++static const struct snd_soc_dapm_widget sun50i_h616_codec_codec_widgets[] = {
++
++    /* Digital parts of the DACs */
++    SND_SOC_DAPM_SUPPLY("DAC Enable", SUNXI_DAC_DPC,
++                        SUNXI_DAC_DPC_EN_DA, 0, NULL, 0),
++
++    SND_SOC_DAPM_AIF_IN_E("DACL", "Codec Playback", 0, SUNXI_DAC_AC_DAC_REG, SUNXI_DAC_LEN, 0,
++                          NULL, 0),
++    SND_SOC_DAPM_AIF_IN_E("DACR", "Codec Playback", 0, SUNXI_DAC_AC_DAC_REG, SUNXI_DAC_REN, 0,
++                          NULL, 0),
++
++    SND_SOC_DAPM_MIXER("Left Output Mixer", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIXEN, 0,
++                       left_output_mixer, ARRAY_SIZE(left_output_mixer)),
++    SND_SOC_DAPM_MIXER("Right Output Mixer", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIXEN, 0,
++                       right_output_mixer, ARRAY_SIZE(right_output_mixer)),
++
++    SND_SOC_DAPM_MUX("Left LINEOUT Mux", SND_SOC_NOPM,
++                     0, 0, &left_lineout_mux),
++    SND_SOC_DAPM_MUX("Right LINEOUT Mux", SND_SOC_NOPM,
++                     0, 0, &right_lineout_mux),
++
++    SND_SOC_DAPM_OUTPUT("LINEOUTL"),
++    SND_SOC_DAPM_OUTPUT("LINEOUTR"),
++
++    SND_SOC_DAPM_LINE("LINEOUT", sunxi_lineout_event),
++};
++
++static const struct snd_soc_component_driver sun50i_h616_codec_codec = {
++    .controls = sun50i_h616_codec_codec_controls,
++    .num_controls = ARRAY_SIZE(sun50i_h616_codec_codec_controls),
++    .dapm_widgets = sun50i_h616_codec_codec_widgets,
++    .num_dapm_widgets = ARRAY_SIZE(sun50i_h616_codec_codec_widgets),
++    .idle_bias_on = 1,
++    .use_pmdown_time = 1,
++    .endianness = 1,
++};
++
++static const struct snd_soc_component_driver sun50i_h616_codec_component = {
++    .name = "sun50i_h616-codec",
++    .legacy_dai_naming = 1,
++#ifdef CONFIG_DEBUG_FS
++	.debugfs_prefix		= "cpu",
++#endif
++};
++
++#define SUN50IW9_CODEC_RATES (SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT)
++#define SUN50IW9_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
++
++static int sun50i_h616_codec_dai_probe(struct snd_soc_dai *dai)
++{
++    struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(card);
++
++    snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data,
++                              NULL);
++
++    return 0;
++}
++
++static struct snd_soc_dai_driver dummy_cpu_dai = {
++    .name = "sun50i_h616-codec-cpu-dai",
++    .probe = sun50i_h616_codec_dai_probe,
++    .playback = {
++        .stream_name = "Playback",
++        .channels_min = 1,
++        .channels_max = 2,
++        .rates = SUN50IW9_CODEC_RATES,
++        .formats = SUN50IW9_CODEC_FORMATS,
++        .sig_bits = 24,
++    },
++};
++
++static struct snd_soc_dai_link *sun50i_h616_codec_create_link(struct device *dev,
++                                                              int *num_links)
++{
++    struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link),
++                                                 GFP_KERNEL);
++    struct snd_soc_dai_link_component *dlc = devm_kzalloc(dev,
++                                                          3 * sizeof(*dlc), GFP_KERNEL);
++    if (!link || !dlc)
++        return NULL;
++
++    link->cpus = &dlc[0];
++    link->codecs = &dlc[1];
++    link->platforms = &dlc[2];
++
++    link->num_cpus = 1;
++    link->num_codecs = 1;
++    link->num_platforms = 1;
++
++    link->name = "cdc";
++    link->stream_name = "CDC PCM";
++    link->codecs->dai_name = "Codec";
++    link->cpus->dai_name = dev_name(dev);
++    link->codecs->name = dev_name(dev);
++    link->platforms->name = dev_name(dev);
++    link->dai_fmt = SND_SOC_DAIFMT_I2S;
++    link->playback_only = true;
++    link->capture_only = false;
++
++    *num_links = 1;
++
++    return link;
++};
++
++static int sun50i_h616_codec_spk_event(struct snd_soc_dapm_widget *w,
++                                       struct snd_kcontrol *k, int event)
++{
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card);
++
++    gpiod_set_value_cansleep(scodec->gpio_pa,
++                             !!SND_SOC_DAPM_EVENT_ON(event));
++
++    if (SND_SOC_DAPM_EVENT_ON(event))
++    {
++        /*
++         * Need a delay to wait for DAC to push the data. 700ms seems
++         * to be the best compromise not to feel this delay while
++         * playing a sound.
++         */
++        msleep(700);
++    }
++
++    return 0;
++}
++
++static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = {
++    SND_SOC_DAPM_LINE("Line Out", NULL),
++    SND_SOC_DAPM_SPK("Speaker", sun50i_h616_codec_spk_event),
++};
++
++/* Connect digital side enables to analog side widgets */
++static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = {
++    /* DAC Routes */
++    {"DACR", NULL, "DAC Enable"},
++    {"DACL", NULL, "DAC Enable"},
++
++    {"Left Output Mixer", "DACR Switch", "DACR"},
++    {"Left Output Mixer", "DACL Switch", "DACL"},
++
++    {"Right Output Mixer", "DACL Switch", "DACL"},
++    {"Right Output Mixer", "DACR Switch", "DACR"},
++
++    {"Left LINEOUT Mux", "LOMixer", "Left Output Mixer"},
++    {"Left LINEOUT Mux", "LROMixer", "Right Output Mixer"},
++    {"Right LINEOUT Mux", "ROMixer", "Right Output Mixer"},
++    {"Right LINEOUT Mux", "LROMixer", "Left Output Mixer"},
++
++    {"LINEOUTL", NULL, "Left LINEOUT Mux"},
++    {"LINEOUTR", NULL, "Right LINEOUT Mux"},
++
++    {"LINEOUT", NULL, "LINEOUTL"},
++    {"LINEOUT", NULL, "LINEOUTR"},
++
++    {"Speaker", NULL, "LINEOUTL"},
++    {"Speaker", NULL, "LINEOUTR"},
++};
++
++static const struct snd_kcontrol_new sunxi_card_controls[] = {
++    SOC_DAPM_PIN_SWITCH("LINEOUT"),
++};
++
++static struct snd_soc_card *sun50i_h616_codec_create_card(struct device *dev)
++{
++    struct snd_soc_card *card;
++    int ret;
++
++    card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
++    if (!card)
++        return ERR_PTR(-ENOMEM);
++
++    card->dai_link = sun50i_h616_codec_create_link(dev, &card->num_links);
++    if (!card->dai_link)
++        return ERR_PTR(-ENOMEM);
++
++    card->dev = dev;
++    card->owner = THIS_MODULE;
++    card->name = "audiocodec";
++    card->controls = sunxi_card_controls;
++    card->num_controls = ARRAY_SIZE(sunxi_card_controls),
++    card->dapm_widgets = sun6i_codec_card_dapm_widgets;
++    card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
++    card->dapm_routes = sun8i_codec_card_routes;
++    card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
++    card->fully_routed = true;
++
++    ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
++    if (ret)
++        dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
++
++    return card;
++};
++
++static const struct regmap_config sun50i_h616_codec_regmap_config = {
++    .reg_bits = 32,
++    .reg_stride = 4,
++    .val_bits = 32,
++    .max_register = SUNXI_DAC_AC_RAMP_REG,
++    .cache_type = REGCACHE_NONE,
++};
++
++struct sun50i_h616_codec_quirks
++{
++    const struct regmap_config *regmap_config;
++    const struct snd_soc_component_driver *codec;
++    struct snd_soc_card *(*create_card)(struct device *dev);
++    struct reg_field reg_adc_fifoc; /* used for regmap_field */
++    unsigned int reg_dac_txdata;    /* TX FIFO offset for DMA config */
++    unsigned int reg_adc_rxdata;    /* RX FIFO offset for DMA config */
++    bool has_reset;
++};
++
++static const struct sun50i_h616_codec_quirks sun50i_h616_codec_quirks = {
++    .regmap_config = &sun50i_h616_codec_regmap_config,
++    .codec = &sun50i_h616_codec_codec,
++    .create_card = sun50i_h616_codec_create_card,
++    .reg_dac_txdata = SUNXI_DAC_TXDATA,
++    .has_reset = true,
++};
++
++static const struct of_device_id sun50i_h616_codec_of_match[] = {
++    {
++        .compatible = "allwinner,sun50i-h616-codec",
++        .data = &sun50i_h616_codec_quirks,
++    },
++    {}};
++MODULE_DEVICE_TABLE(of, sun50i_h616_codec_of_match);
++
++static ssize_t show_audio_reg(struct device *dev,
++                              struct device_attribute *attr, char *buf)
++{
++    int count = 0, i = 0;
++    unsigned int reg_val;
++    unsigned int size = ARRAY_SIZE(reg_labels);
++
++    count += sprintf(buf, "dump audiocodec reg:\n");
++
++    while ((i < size) && (reg_labels[i].name != NULL))
++    {
++        regmap_read(codec_regmap_debug,
++                    reg_labels[i].address, &reg_val);
++        count += sprintf(buf + count, "%-20s [0x%03x]: 0x%-10x save_val:0x%x\n",
++                         reg_labels[i].name, (reg_labels[i].address),
++                         reg_val, reg_labels[i].value);
++        i++;
++    }
++
++    return count;
++}
++
++static DEVICE_ATTR(audio_reg, 0644, show_audio_reg, NULL);
++
++static struct attribute *audio_debug_attrs[] = {
++    &dev_attr_audio_reg.attr,
++    NULL,
++};
++
++static struct attribute_group audio_debug_attr_group = {
++    .name = "audio_reg_debug",
++    .attrs = audio_debug_attrs,
++};
++
++static void sunxi_codec_init(struct sun50i_h616_codec *scodec)
++{
++    /* Disable DRC function for playback */
++    regmap_write(scodec->regmap, SUNXI_DAC_DAP_CTL, 0);
++
++    /* Enable HPF(high passed filter) */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_DPC,
++                       (0x1 << SUNXI_DAC_DPC_HPF_EN), (0x1 << SUNXI_DAC_DPC_HPF_EN));
++
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                       (0x1f << SUNXI_LINEOUT_VOL),
++                       (0x1a << SUNXI_LINEOUT_VOL));
++
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_DPC,
++                       (0x3f << SUNXI_DAC_DPC_DVOL), (0 << SUNXI_DAC_DPC_DVOL));
++
++    /* Mixer to channel LINEOUT MUTE control init */
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                       (0x1 << SUNXI_LMUTE), (0x1 << SUNXI_LMUTE));
++    regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                       (0x1 << SUNXI_RMUTE), (0x1 << SUNXI_RMUTE));
++
++    /* ramp func about */
++    if (0)
++    {
++        /* Not used the ramp func cause there is the MUTE to avoid pop noise */
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_RSWITCH), (0x1 << SUNXI_RSWITCH));
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_RAMPEN), (0x0 << SUNXI_RAMPEN));
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG,
++                           (0x7 << SUNXI_RAMP_STEP), (0x0 << SUNXI_RAMP_STEP));
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG,
++                           (0x1 << SUNXI_RDEN), (0x0 << SUNXI_RDEN));
++    }
++    else
++    {
++        /* If no MUTE to avoid pop, just use the ramp func to avoid it */
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_RSWITCH), (0x0 << SUNXI_RSWITCH));
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG,
++                           (0x1 << SUNXI_RAMPEN), (0x1 << SUNXI_RAMPEN));
++
++        regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG,
++                           (0x7 << SUNXI_RAMP_STEP), (0x1 << SUNXI_RAMP_STEP));
++    }
++}
++
++static int sun50i_h616_codec_probe(struct platform_device *pdev)
++{
++    struct snd_soc_card *card;
++    struct sun50i_h616_codec *scodec;
++    const struct sun50i_h616_codec_quirks *quirks;
++    struct resource *res;
++    void __iomem *base;
++    int ret;
++
++    scodec = devm_kzalloc(&pdev->dev, sizeof(struct sun50i_h616_codec), GFP_KERNEL);
++    if (!scodec)
++        return -ENOMEM;
++
++    scodec->dev = &pdev->dev;
++
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++    base = devm_ioremap_resource(&pdev->dev, res);
++    if (IS_ERR(base))
++        return PTR_ERR(base);
++
++    quirks = of_device_get_match_data(&pdev->dev);
++    if (quirks == NULL)
++    {
++        dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
++        return -ENODEV;
++    }
++
++    scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
++                                           quirks->regmap_config);
++    if (IS_ERR(scodec->regmap))
++    {
++        dev_err(&pdev->dev, "Failed to create our regmap\n");
++        return PTR_ERR(scodec->regmap);
++    }
++
++    /* Get the clocks from the DT */
++    scodec->clk_apb = devm_clk_get(&pdev->dev, "apb");
++    if (IS_ERR(scodec->clk_apb))
++    {
++        dev_err(&pdev->dev, "Failed to get the APB clock\n");
++        return PTR_ERR(scodec->clk_apb);
++    }
++
++    scodec->clk_module = devm_clk_get(&pdev->dev, "audio-codec-1x");
++    if (IS_ERR(scodec->clk_module))
++    {
++        dev_err(&pdev->dev, "Failed to get the codec module clock\n");
++        return PTR_ERR(scodec->clk_module);
++    }
++
++    if (quirks->has_reset)
++    {
++        scodec->rst = devm_reset_control_get_exclusive(&pdev->dev,
++                                                       NULL);
++        if (IS_ERR(scodec->rst))
++        {
++            dev_err(&pdev->dev, "Failed to get reset control\n");
++            return PTR_ERR(scodec->rst);
++        }
++    }
++
++    scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa",
++                                              GPIOD_OUT_LOW);
++    if (IS_ERR(scodec->gpio_pa))
++    {
++        ret = PTR_ERR(scodec->gpio_pa);
++        if (ret != -EPROBE_DEFER)
++            dev_err(&pdev->dev, "Failed to get pa gpio: %d\n", ret);
++        return ret;
++    }
++
++    /* Enable the bus clock */
++    if (clk_prepare_enable(scodec->clk_apb))
++    {
++        dev_err(&pdev->dev, "Failed to enable the APB clock\n");
++        return -EINVAL;
++    }
++
++    /* Deassert the reset control */
++    if (scodec->rst)
++    {
++        ret = reset_control_deassert(scodec->rst);
++        if (ret)
++        {
++            dev_err(&pdev->dev,
++                    "Failed to deassert the reset control\n");
++            goto err_clk_disable;
++        }
++    }
++
++    /* DMA configuration for TX FIFO */
++    scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata;
++    scodec->playback_dma_data.maxburst = 8;
++    scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++
++    ret = devm_snd_soc_register_component(&pdev->dev, quirks->codec,
++                                          &sun50i_h616_codec_dai, 1);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "Failed to register our codec\n");
++        goto err_assert_reset;
++    }
++
++    ret = devm_snd_soc_register_component(&pdev->dev,
++                                          &sun50i_h616_codec_component,
++                                          &dummy_cpu_dai, 1);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "Failed to register our DAI\n");
++        goto err_assert_reset;
++    }
++
++    ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "Failed to register against DMAEngine\n");
++        goto err_assert_reset;
++    }
++
++    card = quirks->create_card(&pdev->dev);
++    if (IS_ERR(card))
++    {
++        ret = PTR_ERR(card);
++        dev_err(&pdev->dev, "Failed to create our card\n");
++        goto err_assert_reset;
++    }
++
++    snd_soc_card_set_drvdata(card, scodec);
++
++    codec_regmap_debug = scodec->regmap;
++
++    ret = snd_soc_register_card(card);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "Failed to register our card\n");
++        goto err_assert_reset;
++    }
++
++    ret = sysfs_create_group(&pdev->dev.kobj, &audio_debug_attr_group);
++    if (ret)
++        dev_warn(&pdev->dev, "failed to create attr group\n");
++
++    sunxi_codec_init(scodec);
++
++    return 0;
++
++err_assert_reset:
++    if (scodec->rst)
++        reset_control_assert(scodec->rst);
++err_clk_disable:
++    clk_disable_unprepare(scodec->clk_apb);
++    return ret;
++}
++
++static int sun50i_h616_codec_remove(struct platform_device *pdev)
++{
++    struct snd_soc_card *card = platform_get_drvdata(pdev);
++    struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(card);
++
++    snd_soc_unregister_card(card);
++    if (scodec->rst)
++        reset_control_assert(scodec->rst);
++    clk_disable_unprepare(scodec->clk_apb);
++
++    return 0;
++}
++
++static struct platform_driver sun50i_h616_codec_driver = {
++    .driver = {
++        .name = "sun50i-h616-codec",
++        .of_match_table = sun50i_h616_codec_of_match,
++    },
++    .probe = sun50i_h616_codec_probe,
++    .remove = sun50i_h616_codec_remove,
++};
++module_platform_driver(sun50i_h616_codec_driver);
++
++MODULE_DESCRIPTION("Allwinner H616 codec driver");
++MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>");
++MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
++MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
++MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
++MODULE_AUTHOR("Leeboby <leeboby@aliyun.com>");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/sunxi_v2/Kconfig b/sound/soc/sunxi_v2/Kconfig
+new file mode 100644
+index 000000000000..37fc579ba9db
+--- /dev/null
++++ b/sound/soc/sunxi_v2/Kconfig
+@@ -0,0 +1,48 @@
++# common
++config SND_SOC_SUNXI_MACH
++	tristate
++
++# ahub dam
++config SND_SOC_SUNXI_AHUB_DAM
++	tristate
++
++config SND_SOC_SUNXI_INTERNALCODEC
++	tristate
++
++config SND_SOC_SUNXI_SUN50IW9_CODEC
++	tristate
++
++# menu select
++menu "Allwinner SoC Audio support V2"
++	depends on ARCH_SUNXI
++
++# aaudio
++config SND_SOC_SUNXI_AAUDIO
++	tristate "Allwinner AAUDIO support"
++	select REGMAP_MMIO
++	select SND_SOC_GENERIC_DMAENGINE_PCM
++	select SND_SOC_SUNXI_MACH
++	select SND_SOC_SUNXI_INTERNALCODEC
++	select SND_SOC_SUNXI_SUN50IW9_CODEC
++	depends on ARCH_SUNXI
++	help
++	    Select Y or M to support analog-audio Module in the Allwinner SoCs.
++
++# ahub
++config SND_SOC_SUNXI_AHUB
++	tristate "Allwinner AHUB Support"
++	select REGMAP_MMIO
++	select SND_SOC_GENERIC_DMAENGINE_PCM
++	select SND_SOC_SUNXI_MACH
++	select SND_SOC_SUNXI_AHUB_DAM
++	depends on ARCH_SUNXI
++	help
++	    Select Y or M to support audio-hub Module in Allwinner SoCs.
++
++config SND_SOC_SUNXI_DEBUG
++	tristate "Components Debug"
++	depends on SND_SOC_SUNXI_COMPONENTS
++	help
++	    Select Y or M to support debug components.
++
++endmenu
+diff --git a/sound/soc/sunxi_v2/Makefile b/sound/soc/sunxi_v2/Makefile
+new file mode 100644
+index 000000000000..c7c2ef8f9fe9
+--- /dev/null
++++ b/sound/soc/sunxi_v2/Makefile
+@@ -0,0 +1,11 @@
++# platform -> ahub
++snd_soc_sunxi_ahub_dam-objs			+= snd_sunxi_ahub_dam.o
++obj-$(CONFIG_SND_SOC_SUNXI_AHUB_DAM)		+= snd_soc_sunxi_ahub_dam.o
++
++snd_soc_sunxi_ahub-objs				+= snd_sunxi_ahub.o
++obj-$(CONFIG_SND_SOC_SUNXI_AHUB)		+= snd_soc_sunxi_ahub.o
++
++# common -> machine (note: Finally compile, save system startup time)
++snd_soc_sunxi_machine-objs			+= snd_sunxi_mach.o
++snd_soc_sunxi_machine-objs			+= snd_sunxi_mach_utils.o
++obj-$(CONFIG_SND_SOC_SUNXI_MACH)		+= snd_soc_sunxi_machine.o
+diff --git a/sound/soc/sunxi_v2/drv_hdmi.h b/sound/soc/sunxi_v2/drv_hdmi.h
+new file mode 100644
+index 000000000000..2e05489b01e1
+--- /dev/null
++++ b/sound/soc/sunxi_v2/drv_hdmi.h
+@@ -0,0 +1,63 @@
++/*
++ * Allwinner SoCs hdmi driver.
++ *
++ * Copyright (C) 2016 Allwinner.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#ifndef __DRV_HDMI_H__
++#define __DRV_HDMI_H__
++
++typedef struct {
++	__u8    hw_intf;        /* 0:iis  1:spdif 2:pcm */
++	__u16	fs_between;     /* fs */
++	__u32   sample_rate;    /*sample rate*/
++	__u8    clk_edge;       /* 0:*/
++	__u8    ch0_en;         /* 1 */
++	__u8    ch1_en;         /* 0 */
++	__u8	ch2_en;         /* 0 */
++	__u8	ch3_en;         /* 0 */
++	__u8	word_length;    /* 32 */
++	__u8    shift_ctl;      /* 0 */
++	__u8    dir_ctl;        /* 0 */
++	__u8    ws_pol;
++	__u8    just_pol;
++	__u8    channel_num;
++	__u8	data_raw;
++	__u8    sample_bit;
++	__u8    ca;     /* channel allocation */
++} hdmi_audio_t;
++
++typedef struct {
++	__s32 (*hdmi_audio_enable)(__u8 mode, __u8 channel);
++	__s32 (*hdmi_set_audio_para)(hdmi_audio_t *audio_para);
++	__s32 (*hdmi_is_playback)(void);
++} __audio_hdmi_func;
++
++enum hdmi_hpd_status {
++	STATUE_CLOSE = 0,
++	STATUE_OPEN = 1,
++};
++
++void audio_set_hdmi_func(__audio_hdmi_func *hdmi_func);
++#if defined(CONFIG_SND_SUNXI_SOC_AUDIOHUB_INTERFACE)
++void audio_set_muti_hdmi_func(__audio_hdmi_func *hdmi_func);
++#endif
++
++/******************** SND_HDMI for sunxi_v2 begain ***************************/
++#if IS_ENABLED(CONFIG_HDMI2_DISP2_SUNXI)
++extern int snd_hdmi_get_func(__audio_hdmi_func *hdmi_func);
++#else
++static inline int snd_hdmi_get_func(__audio_hdmi_func *hdmi_func)
++{
++		pr_err("HDMI Audio API is disable\n");
++
++			return -1;
++}
++#endif
++/******************** SND_HDMI for sunxi_v2 end ******************************/
++
++#endif
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub.c b/sound/soc/sunxi_v2/snd_sunxi_ahub.c
+new file mode 100644
+index 000000000000..8a1065e9183e
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub.c
+@@ -0,0 +1,1477 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_ahub.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/ioport.h>
++#include <linux/regmap.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++#include <sound/soc.h>
++#include <sound/pcm_params.h>
++#include <sound/dmaengine_pcm.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_ahub.h"
++
++#define HLOG           "AHUB"
++#define DRV_NAME       "sunxi-snd-plat-ahub"
++
++static int sunxi_ahub_dai_startup(struct snd_pcm_substream *substream,
++                                 struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               snd_soc_dai_set_dma_data(dai, substream,
++                                        &ahub_info->playback_dma_param);
++       } else {
++               snd_soc_dai_set_dma_data(dai, substream,
++                                        &ahub_info->capture_dma_param);
++       }
++
++       /* APBIF & I2S of RST and GAT */
++       if (tdm_num > 3 || apb_num > 2) {
++               SND_LOG_ERR(HLOG, "unspport tdm num or apbif num\n");
++               return -EINVAL;
++       }
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_TXDIF0_RST - apb_num),
++                                  0x1 << (APBIF_TXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_TXDIF0_GAT - apb_num),
++                                  0x1 << (APBIF_TXDIF0_GAT - apb_num));
++       } else {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_RXDIF0_RST - apb_num),
++                                  0x1 << (APBIF_RXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_RXDIF0_GAT - apb_num),
++                                  0x1 << (APBIF_RXDIF0_GAT - apb_num));
++       }
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_pll(struct snd_soc_dai *dai,
++                                 int pll_id, int source,
++                                 unsigned int freq_in, unsigned int freq_out)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct sunxi_ahub_clk_info *clk_info = NULL;
++
++       SND_LOG_DEBUG(HLOG, "stream -> %s, freq_in ->%u, freq_out ->%u\n",
++                     pll_id ? "IN" : "OUT", freq_in, freq_out);
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       clk_info = &ahub_info->clk_info;
++
++       if (freq_in > 24576000) {
++               //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pllx4)) {
++               //      SND_LOG_ERR(HLOG, "set parent of clk_module to pllx4 failed\n");
++               //      return -EINVAL;
++               //}
++
++               if (clk_set_rate(clk_info->clk_pll, freq_in)) {
++                       SND_LOG_ERR(HLOG, "freq : %u pllx4 clk unsupport\n", freq_in);
++                       return -EINVAL;
++               }
++       } else {
++               //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pll)) {
++               //      SND_LOG_ERR(HLOG, "set parent of clk_module to pll failed\n");
++               //      return -EINVAL;
++               //}
++               if (clk_set_rate(clk_info->clk_pll, freq_in)) {
++                       SND_LOG_ERR(HLOG, "freq : %u pll clk unsupport\n", freq_in);
++                       return -EINVAL;
++               }
++       }
++       if (clk_set_rate(clk_info->clk_module, freq_out / 2)) {
++               SND_LOG_ERR(HLOG, "freq : %u module clk unsupport\n", freq_out);
++               return -EINVAL;
++       }
++
++       ahub_info->pllclk_freq = freq_in;
++       ahub_info->mclk_freq = freq_out;
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
++                                    unsigned int freq, int dir)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num;
++       unsigned int mclk_ratio, mclk_ratio_map;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       if (freq == 0) {
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                                  0x1 << I2S_CLKD_MCLK, 0x0 << I2S_CLKD_MCLK);
++               SND_LOG_DEBUG(HLOG, "mclk freq: 0\n");
++               return 0;
++       }
++       if (ahub_info->pllclk_freq == 0) {
++               SND_LOG_ERR(HLOG, "pllclk freq is invalid\n");
++               return -ENOMEM;
++       }
++       mclk_ratio = ahub_info->pllclk_freq / freq;
++
++       switch (mclk_ratio) {
++       case 1:
++               mclk_ratio_map = 1;
++               break;
++       case 2:
++               mclk_ratio_map = 2;
++               break;
++       case 4:
++               mclk_ratio_map = 3;
++               break;
++       case 6:
++               mclk_ratio_map = 4;
++               break;
++       case 8:
++               mclk_ratio_map = 5;
++               break;
++       case 12:
++               mclk_ratio_map = 6;
++               break;
++       case 16:
++               mclk_ratio_map = 7;
++               break;
++       case 24:
++               mclk_ratio_map = 8;
++               break;
++       case 32:
++               mclk_ratio_map = 9;
++               break;
++       case 48:
++               mclk_ratio_map = 10;
++               break;
++       case 64:
++               mclk_ratio_map = 11;
++               break;
++       case 96:
++               mclk_ratio_map = 12;
++               break;
++       case 128:
++               mclk_ratio_map = 13;
++               break;
++       case 176:
++               mclk_ratio_map = 14;
++               break;
++       case 192:
++               mclk_ratio_map = 15;
++               break;
++       default:
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                                  0x1 << I2S_CLKD_MCLK, 0x0 << I2S_CLKD_MCLK);
++               SND_LOG_ERR(HLOG, "mclk freq div unsupport\n");
++               return -EINVAL;
++       }
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                          0xf << I2S_CLKD_MCLKDIV,
++                          mclk_ratio_map << I2S_CLKD_MCLKDIV);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                          0x1 << I2S_CLKD_MCLK, 0x1 << I2S_CLKD_MCLK);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num;
++       unsigned int bclk_ratio;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       /* ratio -> cpudai pllclk / pcm rate */
++       switch (ratio) {
++       case 1:
++               bclk_ratio = 1;
++               break;
++       case 2:
++               bclk_ratio = 2;
++               break;
++       case 4:
++               bclk_ratio = 3;
++               break;
++       case 6:
++               bclk_ratio = 4;
++               break;
++       case 8:
++               bclk_ratio = 5;
++               break;
++       case 12:
++               bclk_ratio = 6;
++               break;
++       case 16:
++               bclk_ratio = 7;
++               break;
++       case 24:
++               bclk_ratio = 8;
++               break;
++       case 32:
++               bclk_ratio = 9;
++               break;
++       case 48:
++               bclk_ratio = 10;
++               break;
++       case 64:
++               bclk_ratio = 11;
++               break;
++       case 96:
++               bclk_ratio = 12;
++               break;
++       case 128:
++               bclk_ratio = 13;
++               break;
++       case 176:
++               bclk_ratio = 14;
++               break;
++       case 192:
++               bclk_ratio = 15;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "bclk freq div unsupport\n");
++               return -EINVAL;
++       }
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                          0xf << I2S_CLKD_BCLKDIV,
++                          (bclk_ratio - 2) << I2S_CLKD_BCLKDIV);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, tx_pin, rx_pin;
++       unsigned int mode, offset;
++       unsigned int lrck_polarity, brck_polarity;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       ahub_info->fmt = fmt;
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       /* set TDM format */
++       switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++       case    SND_SOC_DAIFMT_I2S:
++               mode = 1;
++               offset = 1;
++               break;
++       case    SND_SOC_DAIFMT_RIGHT_J:
++               mode = 2;
++               offset = 0;
++               break;
++       case    SND_SOC_DAIFMT_LEFT_J:
++               mode = 1;
++               offset = 0;
++               break;
++       case    SND_SOC_DAIFMT_DSP_A:
++               mode = 0;
++               offset = 1;
++               /* L data MSB after FRM LRC (short frame) */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_WIDTH,
++                                  0x0 << I2S_FMT0_LRCK_WIDTH);
++               break;
++       case    SND_SOC_DAIFMT_DSP_B:
++               mode = 0;
++               offset = 0;
++               /* L data MSB during FRM LRC (long frame) */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_WIDTH,
++                                  0x1 << I2S_FMT0_LRCK_WIDTH);
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "format setting failed\n");
++               return -EINVAL;
++       }
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x3 << I2S_CTL_MODE, mode << I2S_CTL_MODE);
++       /* regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin),
++        *                 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++        */
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 0),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 1),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 2),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 3),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_IN_SLOT(tdm_num),
++                          0x3 << I2S_IN_OFFSET, offset << I2S_IN_OFFSET);
++
++       /* set lrck & bclk polarity */
++       switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++       case    SND_SOC_DAIFMT_NB_NF:
++               lrck_polarity = 0;
++               brck_polarity = 0;
++               break;
++       case    SND_SOC_DAIFMT_NB_IF:
++               lrck_polarity = 1;
++               brck_polarity = 0;
++               break;
++       case    SND_SOC_DAIFMT_IB_NF:
++               lrck_polarity = 0;
++               brck_polarity = 1;
++               break;
++       case    SND_SOC_DAIFMT_IB_IF:
++               lrck_polarity = 1;
++               brck_polarity = 1;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "invert clk setting failed\n");
++               return -EINVAL;
++       }
++       if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) ||
++           ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_B))
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_POLARITY,
++                                  (lrck_polarity^1) << I2S_FMT0_LRCK_POLARITY);
++       else
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_POLARITY,
++                                  lrck_polarity << I2S_FMT0_LRCK_POLARITY);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                          0x1 << I2S_FMT0_BCLK_POLARITY,
++                          brck_polarity << I2S_FMT0_BCLK_POLARITY);
++
++       /* set master/slave */
++       switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++       case    SND_SOC_DAIFMT_CBM_CFM:
++               /* lrck & bclk dir output */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                                  0x1 << I2S_CTL_CLK_OUT, 0x0 << I2S_CTL_CLK_OUT);
++               break;
++       case    SND_SOC_DAIFMT_CBS_CFS:
++               /* lrck & bclk dir input */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                                  0x1 << I2S_CTL_CLK_OUT, 0x1 << I2S_CTL_CLK_OUT);
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unknown master/slave format\n");
++               return -EINVAL;
++       }
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_tdm_slot(struct snd_soc_dai *dai,
++                                      unsigned int tx_mask, unsigned int rx_mask,
++                                      int slots, int slot_width)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, tx_pin, rx_pin;
++       unsigned int slot_width_map, lrck_width_map;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       switch (slot_width) {
++       case 8:
++               slot_width_map = 1;
++               break;
++       case 12:
++               slot_width_map = 2;
++               break;
++       case 16:
++               slot_width_map = 3;
++               break;
++       case 20:
++               slot_width_map = 4;
++               break;
++       case 24:
++               slot_width_map = 5;
++               break;
++       case 28:
++               slot_width_map = 6;
++               break;
++       case 32:
++               slot_width_map = 7;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unknown slot width\n");
++               return -EINVAL;
++       }
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                          0x7 << I2S_FMT0_SW, slot_width_map << I2S_FMT0_SW);
++
++       /* bclk num of per channel
++        * I2S/RIGHT_J/LEFT_J   -> lrck long total is lrck_width_map * 2
++        * DSP_A/DAP_B          -> lrck long total is lrck_width_map * 1
++        */
++       switch (ahub_info->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++       case    SND_SOC_DAIFMT_I2S:
++       case    SND_SOC_DAIFMT_RIGHT_J:
++       case    SND_SOC_DAIFMT_LEFT_J:
++               slots /= 2;
++               break;
++       case    SND_SOC_DAIFMT_DSP_A:
++       case    SND_SOC_DAIFMT_DSP_B:
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unsupoort format\n");
++               return -EINVAL;
++       }
++       lrck_width_map = slots * slot_width - 1;
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                          0x3ff << I2S_FMT0_LRCK_PERIOD,
++                          lrck_width_map << I2S_FMT0_LRCK_PERIOD);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_hw_params(struct snd_pcm_substream *substream,
++                                   struct snd_pcm_hw_params *params,
++                                   struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num, tx_pin, rx_pin;
++       unsigned int channels;
++       unsigned int channels_en[16] = {
++               0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff,
++               0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff
++       };
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       /* configure DMA */
++       switch (params_physical_width(params)) {
++       case 16:
++               ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++               ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++               break;
++       case 24:
++       case 32:
++               ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++               ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++               break;
++       default:
++               dev_err(dai->dev, "Unsupported physical sample width: %d\n",
++                       params_physical_width(params));
++               return -EINVAL;
++       }
++
++       /* set bits */
++       switch (params_format(params)) {
++       case SNDRV_PCM_FORMAT_S16_LE:
++               /* apbifn bits */
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                          0x7 << APBIF_TX_WS,
++                                          0x3 << APBIF_TX_WS);
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                          0x1 << APBIF_TX_TXIM,
++                                          0x1 << APBIF_TX_TXIM);
++               } else {
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                          0x7 << APBIF_RX_WS,
++                                          0x3 << APBIF_RX_WS);
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                          0x3 << APBIF_RX_RXOM,
++                                          0x1 << APBIF_RX_RXOM);
++               }
++
++               regmap_update_bits(regmap,
++                                  SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x7 << I2S_FMT0_SR,
++                                  0x3 << I2S_FMT0_SR);
++               break;
++       case SNDRV_PCM_FORMAT_S20_3LE:
++       case SNDRV_PCM_FORMAT_S24_LE:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                          0x7 << APBIF_TX_WS, 0x5 << APBIF_TX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                          0x1 << APBIF_TX_TXIM, 0x1 << APBIF_TX_TXIM);
++               } else {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                          0x7 << APBIF_RX_WS, 0x5 << APBIF_RX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                          0x3 << APBIF_RX_RXOM, 0x1 << APBIF_RX_RXOM);
++               }
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x7 << I2S_FMT0_SR, 0x5 << I2S_FMT0_SR);
++               break;
++       case SNDRV_PCM_FORMAT_S32_LE:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                          0x7 << APBIF_TX_WS, 0x7 << APBIF_TX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                          0x1 << APBIF_TX_TXIM, 0x1 << APBIF_TX_TXIM);
++               } else {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                          0x7 << APBIF_RX_WS, 0x7 << APBIF_RX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                          0x3 << APBIF_RX_RXOM, 0x1 << APBIF_RX_RXOM);
++               }
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x7 << I2S_FMT0_SR, 0x7 << I2S_FMT0_SR);
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unrecognized format bits\n");
++               return -EINVAL;
++       }
++
++       /* set channels */
++       channels = params_channels(params);
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               /* apbifn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                  0xf << APBIF_TX_CHAN_NUM,
++                                  (channels - 1) << APBIF_TX_CHAN_NUM);
++               /* tdmn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CHCFG(tdm_num),
++                                  0xf << I2S_CHCFG_TX_CHANNUM,
++                                  (channels - 1) << I2S_CHCFG_TX_CHANNUM);
++
++               regmap_update_bits(regmap,
++                                  SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin),
++                                  0xf << I2S_OUT_SLOT_NUM,
++                                  (channels - 1) << I2S_OUT_SLOT_NUM);
++               regmap_update_bits(regmap,
++                                  SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin),
++                                  0xffff << I2S_OUT_SLOT_EN,
++                                  channels_en[channels - 1] << I2S_OUT_SLOT_EN);
++       } else {
++               /* apbifn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                  0xf << APBIF_RX_CHAN_NUM,
++                                  (channels - 1) << APBIF_RX_CHAN_NUM);
++               /* tdmn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CHCFG(tdm_num),
++                                  0xf << I2S_CHCFG_RX_CHANNUM,
++                                  (channels - 1) << I2S_CHCFG_RX_CHANNUM);
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_IN_SLOT(tdm_num),
++                                  0xf << I2S_IN_SLOT_NUM,
++                                  (channels - 1) << I2S_IN_SLOT_NUM);
++       }
++
++       return 0;
++}
++
++static void sunxi_ahub_dai_tx_route(struct sunxi_ahub_info *ahub_info,
++                                   bool enable)
++{
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, tx_pin;
++       unsigned int apb_num;
++
++       SND_LOG_DEBUG(HLOG, "%s\n", enable ? "on" : "off");
++
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       apb_num = ahub_info->dts_info.apb_num;
++
++       if (enable)
++               goto tx_route_enable;
++       else
++               goto tx_route_disable;
++
++tx_route_enable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDO0_EN + tx_pin),
++                          0x1 << (I2S_CTL_SDO0_EN + tx_pin));
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_TXEN, 0x1 << I2S_CTL_TXEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_OUT_MUTE, 0x0 << I2S_CTL_OUT_MUTE);
++       /* start apbif tx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                          0x1 << APBIF_TX_START, 0x1 << APBIF_TX_START);
++       /* enable tx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_TX_DRQ, 0x1 << APBIF_TX_DRQ);
++       return;
++
++tx_route_disable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_OUT_MUTE, 0x1 << I2S_CTL_OUT_MUTE);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_TXEN, 0x0 << I2S_CTL_TXEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDO0_EN + tx_pin),
++                          0x0 << (I2S_CTL_SDO0_EN + tx_pin));
++       /* stop apbif tx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                          0x1 << APBIF_TX_START, 0x0 << APBIF_TX_START);
++       /* disable tx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_TX_DRQ, 0x0 << APBIF_TX_DRQ);
++       return;
++}
++
++static void sunxi_ahub_dai_rx_route(struct sunxi_ahub_info *ahub_info,
++                                   bool enable)
++{
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, rx_pin;
++       unsigned int apb_num;
++
++       SND_LOG_DEBUG(HLOG, "%s\n", enable ? "on" : "off");
++
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       rx_pin = ahub_info->dts_info.rx_pin;
++       apb_num = ahub_info->dts_info.apb_num;
++
++       if (enable)
++               goto rx_route_enable;
++       else
++               goto rx_route_disable;
++
++rx_route_enable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDI0_EN + rx_pin),
++                          0x1 << (I2S_CTL_SDI0_EN + rx_pin));
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_RXEN, 0x1 << I2S_CTL_RXEN);
++       /* start apbif rx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                          0x1 << APBIF_RX_START, 0x1 << APBIF_RX_START);
++       /* enable rx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_RX_DRQ, 0x1 << APBIF_RX_DRQ);
++       return;
++
++rx_route_disable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_RXEN, 0x0 << I2S_CTL_RXEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDI0_EN + rx_pin),
++                          0x0 << (I2S_CTL_SDI0_EN + rx_pin));
++       /* stop apbif rx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                          0x1 << APBIF_RX_START, 0x0 << APBIF_RX_START);
++       /* disable rx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_RX_DRQ, 0x0 << APBIF_RX_DRQ);
++       return;
++}
++
++static int sunxi_ahub_dai_trigger(struct snd_pcm_substream *substream,
++                                 int cmd,
++                                 struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++
++       switch (cmd) {
++       case    SNDRV_PCM_TRIGGER_START:
++       case    SNDRV_PCM_TRIGGER_RESUME:
++       case    SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       sunxi_ahub_dai_tx_route(ahub_info, true);
++               } else {
++                       sunxi_ahub_dai_rx_route(ahub_info, true);
++               }
++               break;
++       case    SNDRV_PCM_TRIGGER_STOP:
++       case    SNDRV_PCM_TRIGGER_SUSPEND:
++       case    SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       sunxi_ahub_dai_tx_route(ahub_info, false);
++               } else {
++                       sunxi_ahub_dai_rx_route(ahub_info, false);
++               }
++               break;
++       default:
++               return -EINVAL;
++       }
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_prepare(struct snd_pcm_substream *substream,
++                                 struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               /* clear txfifo */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                  0x1 << APBIF_TX_FTX, 0x1 << APBIF_TX_FTX);
++               /* clear tx o/u irq */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_TX_IRQ_STA(apb_num),
++                            (0x1 << APBIF_TX_OV_PEND) | (0x1 << APBIF_TX_EM_PEND));
++               /* clear tx fifo cnt */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_TXFIFO_CNT(apb_num), 0);
++       } else {
++               /* clear rxfifo */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                  0x1 << APBIF_RX_FRX, 0x1 << APBIF_RX_FRX);
++               /* clear rx o/u irq */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_RX_IRQ_STA(apb_num),
++                            (0x1 << APBIF_RX_UV_PEND) | (0x1 << APBIF_RX_AV_PEND));
++               /* clear rx fifo cnt */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_RXFIFO_CNT(apb_num), 0);
++       }
++
++       return 0;
++}
++
++static void sunxi_ahub_dai_shutdown(struct snd_pcm_substream *substream,
++                                   struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       /* APBIF & I2S of RST and GAT */
++       if (tdm_num > 3 || apb_num > 2) {
++               SND_LOG_ERR(HLOG, "unspport tdm num or apbif num\n");
++               return;
++       }
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_TXDIF0_RST - apb_num),
++                                  0x0 << (APBIF_TXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_TXDIF0_GAT - apb_num),
++                                  0x0 << (APBIF_TXDIF0_GAT - apb_num));
++       } else {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_RXDIF0_RST - apb_num),
++                                  0x0 << (APBIF_RXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_RXDIF0_GAT - apb_num),
++                                  0x0 << (APBIF_RXDIF0_GAT - apb_num));
++       }
++}
++
++static const struct snd_soc_dai_ops sunxi_ahub_dai_ops = {
++        /* call by machine */
++        .set_pll        = sunxi_ahub_dai_set_pll,       // set pllclk
++        .set_sysclk     = sunxi_ahub_dai_set_sysclk,    // set mclk
++        .set_bclk_ratio = sunxi_ahub_dai_set_bclk_ratio,// set bclk freq
++        .set_tdm_slot   = sunxi_ahub_dai_set_tdm_slot,  // set slot num and width
++        .set_fmt        = sunxi_ahub_dai_set_fmt,       // set tdm fmt
++        /* call by asoc */
++        .startup        = sunxi_ahub_dai_startup,
++        .hw_params      = sunxi_ahub_dai_hw_params,     // set hardware params
++        .prepare        = sunxi_ahub_dai_prepare,       // clean irq and fifo
++        .trigger        = sunxi_ahub_dai_trigger,       // set drq
++        .shutdown       = sunxi_ahub_dai_shutdown,
++};
++
++static void snd_soc_sunxi_ahub_init(struct sunxi_ahub_info *ahub_info)
++{
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num, tx_pin, rx_pin;
++       unsigned int reg_val = 0;
++       unsigned int rx_pin_map = 0;
++       unsigned int tdm_to_apb = 0;
++       unsigned int apb_to_tdm = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_GEN, 0x1 << I2S_CTL_GEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                          0x1 << (I2S0_RST - tdm_num),
++                          0x1 << (I2S0_RST - tdm_num));
++       regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                          0x1 << (I2S0_GAT - tdm_num),
++                          0x1 << (I2S0_GAT - tdm_num));
++
++       /* tdm tx channels map */
++       regmap_write(regmap, SUNXI_AHUB_I2S_OUT_CHMAP0(tdm_num, tx_pin), 0x76543210);
++       regmap_write(regmap, SUNXI_AHUB_I2S_OUT_CHMAP1(tdm_num, tx_pin), 0xFEDCBA98);
++
++       /* tdm rx channels map */
++       rx_pin_map = (rx_pin << 4) | (rx_pin << 12) | (rx_pin << 20) | (rx_pin << 28);
++       reg_val = 0x03020100 | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP0(tdm_num), reg_val);
++       reg_val = 0x07060504 | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP1(tdm_num), reg_val);
++       reg_val = 0x0B0A0908 | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP2(tdm_num), reg_val);
++       reg_val = 0x0F0E0D0C | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP3(tdm_num), reg_val);
++
++       /* tdm tx & rx data fmt
++        * 1. MSB first
++        * 2. transfer 0 after each sample in each slot
++        * 3. linear PCM
++        */
++       regmap_write(regmap, SUNXI_AHUB_I2S_FMT1(tdm_num), 0x30);
++
++       /* apbif tx & rx data fmt
++        * 1. MSB first
++        * 2. trigger level tx -> 0x20, rx -> 0x40
++        */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                          0x1 << APBIF_TX_TXIM, 0x0 << APBIF_TX_TXIM);
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                          0x3f << APBIF_TX_LEVEL, 0x20 << APBIF_TX_LEVEL);
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                          0x3 << APBIF_RX_RXOM, 0x0 << APBIF_RX_RXOM);
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                          0x7f << APBIF_RX_LEVEL, 0x40 << APBIF_RX_LEVEL);
++
++       /* apbif <-> tdm */
++       switch (tdm_num)
++       {
++       case 0:
++               tdm_to_apb = APBIF_RX_I2S0_TXDIF;
++               break;
++       case 1:
++               tdm_to_apb = APBIF_RX_I2S1_TXDIF;
++               break;
++       case 2:
++               tdm_to_apb = APBIF_RX_I2S2_TXDIF;
++               break;
++       case 3:
++               tdm_to_apb = APBIF_RX_I2S3_TXDIF;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unspport tdm num\n");
++               return;
++       }
++       regmap_write(regmap, SUNXI_AHUB_APBIF_RXFIFO_CONT(apb_num), 0x1 << tdm_to_apb);
++
++       switch (apb_num)
++       {
++       case 0:
++               apb_to_tdm = I2S_RX_APBIF_TXDIF0;
++               break;
++       case 1:
++               apb_to_tdm = I2S_RX_APBIF_TXDIF1;
++               break;
++       case 2:
++               apb_to_tdm = I2S_RX_APBIF_TXDIF2;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unspport apb num\n");
++               return;
++       }
++       regmap_write(regmap, SUNXI_AHUB_I2S_RXCONT(tdm_num), 0x1 << apb_to_tdm);
++
++       return;
++}
++
++static int sunxi_ahub_dai_probe(struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       /* pcm_new will using the dma_param about the cma and fifo params. */
++       snd_soc_dai_init_dma_data(dai,
++                                 &ahub_info->playback_dma_param,
++                                 &ahub_info->capture_dma_param);
++
++       snd_soc_sunxi_ahub_init(ahub_info);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_remove(struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_GEN, 0x0 << I2S_CTL_GEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                          0x1 << (I2S0_RST - tdm_num),
++                          0x0 << (I2S0_RST - tdm_num));
++       regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                          0x1 << (I2S0_GAT - tdm_num),
++                          0x0 << (I2S0_GAT - tdm_num));
++
++       return 0;
++}
++
++static struct snd_soc_dai_driver sunxi_ahub_dai = {
++       .name           = "ahub_plat",
++       .probe          = sunxi_ahub_dai_probe,
++       .remove         = sunxi_ahub_dai_remove,
++       .playback = {
++               .stream_name    = "Playback",
++               .channels_min   = 1,
++               .channels_max   = 2,
++               .rates          = SNDRV_PCM_RATE_8000_192000
++                               | SNDRV_PCM_RATE_KNOT,
++               .formats        = SNDRV_PCM_FMTBIT_S16_LE
++                               | SNDRV_PCM_FMTBIT_S24_LE
++                               | SNDRV_PCM_FMTBIT_S32_LE,
++       },
++       .capture = {
++               .stream_name    = "Capture",
++               .channels_min   = 1,
++               .channels_max   = 2,
++               .rates          = SNDRV_PCM_RATE_8000_192000
++                               | SNDRV_PCM_RATE_KNOT,
++               .formats        = SNDRV_PCM_FMTBIT_S16_LE
++                               | SNDRV_PCM_FMTBIT_S24_LE
++                               | SNDRV_PCM_FMTBIT_S32_LE,
++       },
++       .ops = &sunxi_ahub_dai_ops,
++};
++
++static int sunxi_ahub_probe(struct snd_soc_component *component)
++{
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       return 0;
++}
++
++static int sunxi_ahub_suspend(struct snd_soc_component *component)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       return 0;
++}
++
++static int sunxi_ahub_resume(struct snd_soc_component *component)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       snd_soc_sunxi_ahub_init(ahub_info);
++
++       return 0;
++}
++
++int sunxi_loopback_debug_get(struct snd_kcontrol *kcontrol,
++                            struct snd_ctl_elem_value *ucontrol)
++{
++       unsigned int reg_val;
++       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++       struct sunxi_ahub_mem_info *mem_info = &ahub_info->mem_info;
++       struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info;
++
++       regmap_read(mem_info->regmap, SUNXI_AHUB_I2S_CTL(dts_info->tdm_num), &reg_val);
++       ucontrol->value.integer.value[0] = ((reg_val & (1 << I2S_CTL_LOOP0)) ? 1 : 0);
++
++       return 0;
++}
++
++int sunxi_loopback_debug_set(struct snd_kcontrol *kcontrol,
++                            struct snd_ctl_elem_value *ucontrol)
++{
++       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++       struct sunxi_ahub_mem_info *mem_info = &ahub_info->mem_info;
++       struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info;
++
++       switch (ucontrol->value.integer.value[0]) {
++       case    0:
++               regmap_update_bits(mem_info->regmap,
++                                  SUNXI_AHUB_I2S_CTL(dts_info->tdm_num),
++                                  1 << I2S_CTL_LOOP0, 0 << I2S_CTL_LOOP0);
++               break;
++       case    1:
++               regmap_update_bits(mem_info->regmap,
++                                  SUNXI_AHUB_I2S_CTL(dts_info->tdm_num),
++                                  1 << I2S_CTL_LOOP0, 1 << I2S_CTL_LOOP0);
++               break;
++       default:
++               return -EINVAL;
++       }
++
++       return 0;
++}
++
++static const struct snd_kcontrol_new sunxi_ahub_controls[] = {
++       SOC_SINGLE_EXT("loopback debug", SND_SOC_NOPM, 0, 1, 0,
++                      sunxi_loopback_debug_get, sunxi_loopback_debug_set),
++};
++
++static struct snd_soc_component_driver sunxi_ahub_component = {
++       .name           = DRV_NAME,
++       .probe          = sunxi_ahub_probe,
++       .suspend        = sunxi_ahub_suspend,
++       .resume         = sunxi_ahub_resume,
++       .controls       = sunxi_ahub_controls,
++       .num_controls   = ARRAY_SIZE(sunxi_ahub_controls),
++};
++
++/*******************************************************************************
++ * for kernel source
++ ******************************************************************************/
++static int snd_soc_sunxi_ahub_pin_init(struct platform_device *pdev,
++                                      struct device_node *np,
++                                      struct sunxi_ahub_pinctl_info *pin_info)
++{
++       int ret = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (of_property_read_bool(np, "pinctrl_used")) {
++               pin_info->pinctrl_used = 1;
++       } else {
++               pin_info->pinctrl_used = 0;
++               SND_LOG_DEBUG(HLOG, "unused pinctrl\n");
++               return 0;
++       }
++
++       pin_info->pinctrl = devm_pinctrl_get(&pdev->dev);
++       if (IS_ERR_OR_NULL(pin_info->pinctrl)) {
++               SND_LOG_ERR(HLOG, "pinctrl get failed\n");
++               ret = -EINVAL;
++               return ret;
++       }
++       pin_info->pinstate = pinctrl_lookup_state(pin_info->pinctrl,
++                                                 PINCTRL_STATE_DEFAULT);
++       if (IS_ERR_OR_NULL(pin_info->pinstate)) {
++               SND_LOG_ERR(HLOG, "pinctrl default state get fail\n");
++               ret = -EINVAL;
++               goto err_loopup_pinstate;
++       }
++       pin_info->pinstate_sleep = pinctrl_lookup_state(pin_info->pinctrl,
++                                                       PINCTRL_STATE_SLEEP);
++       if (IS_ERR_OR_NULL(pin_info->pinstate_sleep)) {
++               SND_LOG_ERR(HLOG, "pinctrl sleep state get failed\n");
++               ret = -EINVAL;
++               goto err_loopup_pin_sleep;
++       }
++       ret = pinctrl_select_state(pin_info->pinctrl, pin_info->pinstate);
++       if (ret < 0) {
++               SND_LOG_ERR(HLOG, "daudio set pinctrl default state fail\n");
++               ret = -EBUSY;
++               goto err_pinctrl_select_default;
++       }
++
++       return 0;
++
++err_pinctrl_select_default:
++err_loopup_pin_sleep:
++err_loopup_pinstate:
++       devm_pinctrl_put(pin_info->pinctrl);
++       return ret;
++}
++
++static int snd_soc_sunxi_ahub_dts_params_init(struct platform_device *pdev,
++                                             struct device_node *np,
++                                             struct sunxi_ahub_dts_info *dts_info)
++{
++       int ret = 0;
++       unsigned int temp_val = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       /* get tdm fmt of apb_num & tdm_num & tx/rx_pin */
++       ret = of_property_read_u32(np, "apb_num", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "apb_num config missing\n");
++               dts_info->apb_num = 0;
++       } else {
++               if (temp_val > 2) {     /* APBIFn (n = 0~2) */
++                       dts_info->apb_num = 0;
++                       SND_LOG_WARN(HLOG, "apb_num config invalid\n");
++               } else {
++                       dts_info->apb_num = temp_val;
++               }
++       }
++       ret = of_property_read_u32(np, "tdm_num", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "tdm_num config missing\n");
++               dts_info->tdm_num = 0;
++       } else {
++               if (temp_val > 3) {     /* I2Sn (n = 0~3) */
++                       dts_info->tdm_num = 0;
++                       SND_LOG_WARN(HLOG, "tdm_num config invalid\n");
++               } else {
++                       dts_info->tdm_num = temp_val;
++               }
++       }
++       ret = of_property_read_u32(np, "tx_pin", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "tx_pin config missing\n");
++               dts_info->tx_pin = 0;
++       } else {
++               if (temp_val > 3) {     /* I2S_DOUTn (n = 0~3) */
++                       dts_info->tx_pin = 0;
++                       SND_LOG_WARN(HLOG, "tx_pin config invalid\n");
++               } else {
++                       dts_info->tx_pin = temp_val;
++               }
++       }
++       ret = of_property_read_u32(np, "rx_pin", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "rx_pin config missing\n");
++               dts_info->rx_pin = 0;
++       } else {
++               if (temp_val > 3) {     /* I2S_DINTn (n = 0~3) */
++                       dts_info->rx_pin = 0;
++                       SND_LOG_WARN(HLOG, "rx_pin config invalid\n");
++               } else {
++                       dts_info->rx_pin = temp_val;
++               }
++       }
++
++       SND_LOG_DEBUG(HLOG, "playback_cma : %lu\n", dts_info->playback_cma);
++       SND_LOG_DEBUG(HLOG, "capture_cma  : %lu\n", dts_info->capture_cma);
++       SND_LOG_DEBUG(HLOG, "tx_fifo_size : %lu\n", dts_info->playback_fifo_size);
++       SND_LOG_DEBUG(HLOG, "rx_fifo_size : %lu\n", dts_info->capture_fifo_size);
++       SND_LOG_DEBUG(HLOG, "apb_num      : %u\n", dts_info->apb_num);
++       SND_LOG_DEBUG(HLOG, "tdm_num      : %u\n", dts_info->tdm_num);
++       SND_LOG_DEBUG(HLOG, "tx_pin       : %u\n", dts_info->tx_pin);
++       SND_LOG_DEBUG(HLOG, "rx_pin       : %u\n", dts_info->rx_pin);
++
++       return 0;
++};
++
++static int snd_soc_sunxi_ahub_regulator_init(struct platform_device *pdev,
++                                            struct device_node *np,
++                                            struct sunxi_ahub_regulator_info *regulator_info)
++{
++       int ret = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regulator_info->regulator_name = NULL;
++       if (of_property_read_string(np, "ahub_regulator", &regulator_info->regulator_name)) {
++               SND_LOG_DEBUG(HLOG, "regulator missing\n");
++               regulator_info->regulator = NULL;
++               return 0;
++       }
++
++       regulator_info->regulator = regulator_get(NULL, regulator_info->regulator_name);
++       if (IS_ERR_OR_NULL(regulator_info->regulator)) {
++               SND_LOG_ERR(HLOG, "get duaido vcc-pin failed\n");
++               ret = -EFAULT;
++               goto err_regulator_get;
++       }
++       ret = regulator_set_voltage(regulator_info->regulator, 3300000, 3300000);
++       if (ret < 0) {
++               SND_LOG_ERR(HLOG, "set duaido voltage failed\n");
++               ret = -EFAULT;
++               goto err_regulator_set_vol;
++       }
++       ret = regulator_enable(regulator_info->regulator);
++       if (ret < 0) {
++               SND_LOG_ERR(HLOG, "enable duaido vcc-pin failed\n");
++               ret = -EFAULT;
++               goto err_regulator_enable;
++       }
++
++       return 0;
++
++err_regulator_enable:
++err_regulator_set_vol:
++       if (regulator_info->regulator)
++               regulator_put(regulator_info->regulator);
++err_regulator_get:
++       return ret;
++};
++
++static void snd_soc_sunxi_dma_params_init(struct sunxi_ahub_info *ahub_info)
++{
++       struct resource *res = ahub_info->mem_info.res;
++       struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       ahub_info->playback_dma_param.addr =
++               res->start + SUNXI_AHUB_APBIF_TXFIFO(dts_info->apb_num);
++       ahub_info->playback_dma_param.maxburst = 8;
++       //ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++
++       ahub_info->capture_dma_param.addr =
++               res->start + SUNXI_AHUB_APBIF_RXFIFO(dts_info->apb_num);
++       ahub_info->capture_dma_param.maxburst = 8;
++       //ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++};
++
++static int sunxi_ahub_dev_probe(struct platform_device *pdev)
++{
++       int ret;
++       struct device_node *np = pdev->dev.of_node;
++       struct sunxi_ahub_info *ahub_info = NULL;
++       struct sunxi_ahub_mem_info *mem_info = NULL;
++       struct sunxi_ahub_clk_info *clk_info = NULL;
++       struct sunxi_ahub_pinctl_info *pin_info = NULL;
++       struct sunxi_ahub_dts_info *dts_info = NULL;
++       struct sunxi_ahub_regulator_info *regulator_info = NULL;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       ahub_info = devm_kzalloc(&pdev->dev,
++                                 sizeof(struct sunxi_ahub_info),
++                                 GFP_KERNEL);
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "alloc sunxi_ahub_info failed\n");
++               ret = -ENOMEM;
++               goto err_devm_malloc_sunxi_daudio;
++       }
++       dev_set_drvdata(&pdev->dev, ahub_info);
++       ahub_info->dev = &pdev->dev;
++       mem_info = &ahub_info->mem_info;
++       clk_info = &ahub_info->clk_info;
++       pin_info = &ahub_info->pin_info;
++       dts_info = &ahub_info->dts_info;
++       regulator_info = &ahub_info->regulator_info;
++
++       ret = snd_soc_sunxi_ahub_mem_get(mem_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "remap get failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_mem_get;
++       }
++
++       ret = snd_soc_sunxi_ahub_clk_get(clk_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "clk get failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_clk_get;
++       }
++
++       ret = snd_soc_sunxi_ahub_dts_params_init(pdev, np, dts_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "dts init failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_dts_params_init;
++       }
++
++       ret = snd_soc_sunxi_ahub_pin_init(pdev, np, pin_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "pinctrl init failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_pin_init;
++       }
++
++       ret = snd_soc_sunxi_ahub_regulator_init(pdev, np, regulator_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "regulator_info init failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_regulator_init;
++       }
++
++       snd_soc_sunxi_dma_params_init(ahub_info);
++
++       ret = snd_soc_register_component(&pdev->dev,
++                                        &sunxi_ahub_component,
++                                        &sunxi_ahub_dai, 1);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "component register failed\n");
++               ret = -ENOMEM;
++               goto err_snd_soc_register_component;
++       }
++
++        ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
++        if (ret) {
++               SND_LOG_ERR(HLOG, "register ASoC platform failed\n");
++               ret = -ENOMEM;
++               goto err_snd_soc_sunxi_dma_platform_register;
++        }
++
++       SND_LOG_DEBUG(HLOG, "register ahub platform success\n");
++
++       return 0;
++
++err_snd_soc_sunxi_dma_platform_register:
++       snd_soc_unregister_component(&pdev->dev);
++err_snd_soc_register_component:
++err_snd_soc_sunxi_ahub_regulator_init:
++err_snd_soc_sunxi_ahub_dts_params_init:
++err_snd_soc_sunxi_ahub_pin_init:
++err_snd_soc_sunxi_ahub_clk_get:
++err_snd_soc_sunxi_ahub_mem_get:
++       devm_kfree(&pdev->dev, ahub_info);
++err_devm_malloc_sunxi_daudio:
++       of_node_put(np);
++       return ret;
++}
++
++static int sunxi_ahub_dev_remove(struct platform_device *pdev)
++{
++       struct sunxi_ahub_info *ahub_info = dev_get_drvdata(&pdev->dev);
++       struct sunxi_ahub_pinctl_info *pin_info = &ahub_info->pin_info;
++       struct sunxi_ahub_regulator_info *regulator_info = &ahub_info->regulator_info;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       snd_soc_unregister_component(&pdev->dev);
++
++       if (regulator_info->regulator) {
++               if (!IS_ERR_OR_NULL(regulator_info->regulator)) {
++                       regulator_disable(regulator_info->regulator);
++                       regulator_put(regulator_info->regulator);
++               }
++       }
++       if (pin_info->pinctrl_used) {
++               devm_pinctrl_put(pin_info->pinctrl);
++       }
++
++       devm_kfree(&pdev->dev, ahub_info);
++
++       SND_LOG_DEBUG(HLOG, "unregister ahub platform success\n");
++
++       return 0;
++}
++
++static const struct of_device_id sunxi_ahub_of_match[] = {
++       { .compatible = "allwinner," DRV_NAME, },
++       {},
++};
++MODULE_DEVICE_TABLE(of, sunxi_ahub_of_match);
++
++static struct platform_driver sunxi_ahub_driver = {
++       .driver = {
++               .name           = DRV_NAME,
++               .owner          = THIS_MODULE,
++               .of_match_table = sunxi_ahub_of_match,
++       },
++       .probe  = sunxi_ahub_dev_probe,
++       .remove = sunxi_ahub_dev_remove,
++};
++
++int __init sunxi_ahub_dev_init(void)
++{
++       int ret;
++
++       ret = platform_driver_register(&sunxi_ahub_driver);
++       if (ret != 0) {
++               SND_LOG_ERR(HLOG, "platform driver register failed\n");
++               return -EINVAL;
++       }
++
++       return ret;
++}
++
++void __exit sunxi_ahub_dev_exit(void)
++{
++       platform_driver_unregister(&sunxi_ahub_driver);
++}
++
++late_initcall(sunxi_ahub_dev_init);
++module_exit(sunxi_ahub_dev_exit);
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard platform of ahub");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub.h b/sound/soc/sunxi_v2/snd_sunxi_ahub.h
+new file mode 100644
+index 000000000000..b3c1cc592844
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub.h
+@@ -0,0 +1,67 @@
++/* sound\soc\sunxi\snd_sunxi_ahub.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_AHUB_H
++#define __SND_SUNXI_AHUB_H
++
++#include "snd_sunxi_ahub_dam.h"
++
++struct sunxi_ahub_pinctl_info {
++       struct pinctrl *pinctrl;
++       struct pinctrl_state *pinstate;
++       struct pinctrl_state *pinstate_sleep;
++
++       bool pinctrl_used;
++};
++
++struct sunxi_ahub_dts_info {
++       unsigned int dai_type;
++       unsigned int apb_num;
++       unsigned int tdm_num;
++       unsigned int tx_pin;
++       unsigned int rx_pin;
++
++       /* value must be (2^n)Kbyte */
++       size_t playback_cma;
++       size_t playback_fifo_size;
++       size_t capture_cma;
++       size_t capture_fifo_size;
++};
++
++struct sunxi_ahub_regulator_info {
++       struct regulator *regulator;
++       const char *regulator_name;
++};
++
++struct sunxi_ahub_info {
++       struct device *dev;
++
++       struct sunxi_ahub_mem_info mem_info;
++       struct sunxi_ahub_clk_info clk_info;
++       struct sunxi_ahub_pinctl_info pin_info;
++       struct sunxi_ahub_dts_info dts_info;
++       struct sunxi_ahub_regulator_info regulator_info;
++
++       //struct sunxi_dma_params playback_dma_param;
++       //struct sunxi_dma_params capture_dma_param;
++        struct snd_dmaengine_dai_dma_data playback_dma_param;
++        struct snd_dmaengine_dai_dma_data capture_dma_param;
++
++       /* for Hardware param setting */
++       unsigned int fmt;
++       unsigned int pllclk_freq;
++       unsigned int moduleclk_freq;
++       unsigned int mclk_freq;
++       unsigned int lrck_freq;
++       unsigned int bclk_freq;
++};
++
++#endif /* __SND_SUNXI_AHUB_H */
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c
+new file mode 100644
+index 000000000000..1fcc8aefd50c
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c
+@@ -0,0 +1,534 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_ahub_dam.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <sound/soc.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/device.h>
++#include <linux/ioport.h>
++#include <linux/regmap.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++#include <sound/soc.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_ahub_dam.h"
++
++#define HLOG		"AHUB_DAM"
++#define DRV_NAME	"sunxi-snd-plat-ahub_dam"
++
++static struct resource g_res;
++struct sunxi_ahub_mem_info g_mem_info = {
++	.res = &g_res,
++};
++static struct sunxi_ahub_clk_info g_clk_info;
++static struct regmap_config g_regmap_config = {
++	.reg_bits = 32,
++	.reg_stride = 4,
++	.val_bits = 32,
++	.max_register = SUNXI_AHUB_MAX_REG,
++	.cache_type = REGCACHE_NONE,
++};
++
++static struct snd_soc_dai_driver sunxi_ahub_dam_dai = {
++	.name           = "ahub_dam",
++};
++
++static int sunxi_ahub_dam_probe(struct snd_soc_component *component)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	return 0;
++}
++
++static int sunxi_ahub_dam_suspend(struct snd_soc_component *component)
++{
++	struct sunxi_ahub_clk_info *clk_info = &g_clk_info;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	clk_disable_unprepare(clk_info->clk_module);
++	clk_disable_unprepare(clk_info->clk_pll);
++	//clk_disable_unprepare(clk_info->clk_pllx4);
++	clk_disable_unprepare(clk_info->clk_bus);
++	reset_control_assert(clk_info->clk_rst);
++
++	return 0;
++}
++
++static int sunxi_ahub_dam_resume(struct snd_soc_component *component)
++{
++	struct sunxi_ahub_clk_info *clk_info = &g_clk_info;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (reset_control_deassert(clk_info->clk_rst)) {
++		SND_LOG_ERR(HLOG, "clk rst deassert failed\n");
++		return -EINVAL;
++	}
++	if (clk_prepare_enable(clk_info->clk_bus)) {
++		SND_LOG_ERR(HLOG, "clk bus enable failed\n");
++		return -EBUSY;
++	}
++	if (clk_prepare_enable(clk_info->clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk_pll enable failed\n");
++		return -EBUSY;
++	}
++	//if (clk_prepare_enable(clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk_pllx4 enable failed\n");
++	//	return -EBUSY;
++	//}
++	if (clk_prepare_enable(clk_info->clk_module)) {
++		SND_LOG_ERR(HLOG, "clk_module enable failed\n");
++		return -EBUSY;
++	}
++
++	return 0;
++}
++
++struct str_conv {
++	char *str;
++	unsigned int reg;
++};
++static struct str_conv ahub_mux_name[] = {
++	{"APBIF0 Src Select",	SUNXI_AHUB_APBIF_RXFIFO_CONT(0)},
++	{"APBIF1 Src Select",	SUNXI_AHUB_APBIF_RXFIFO_CONT(1)},
++	{"APBIF2 Src Select",	SUNXI_AHUB_APBIF_RXFIFO_CONT(2)},
++	{"I2S0 Src Select",	SUNXI_AHUB_I2S_RXCONT(0)},
++	{"I2S1 Src Select",	SUNXI_AHUB_I2S_RXCONT(1)},
++	{"I2S2 Src Select",	SUNXI_AHUB_I2S_RXCONT(2)},
++	{"I2S3 Src Select",	SUNXI_AHUB_I2S_RXCONT(3)},
++	{"DAM0C0 Src Select",	SUNXI_AHUB_DAM_RX0_SRC(0)},
++	{"DAM0C1 Src Select",	SUNXI_AHUB_DAM_RX1_SRC(0)},
++	{"DAM0C2 Src Select",	SUNXI_AHUB_DAM_RX2_SRC(0)},
++	{"DAM1C0 Src Select",	SUNXI_AHUB_DAM_RX0_SRC(1)},
++	{"DAM1C1 Src Select",	SUNXI_AHUB_DAM_RX1_SRC(1)},
++	{"DAM1C2 Src Select",	SUNXI_AHUB_DAM_RX2_SRC(1)},
++};
++static const char *ahub_mux_text[] = {
++	"NONE",
++	"APBIF_TXDIF0",
++	"APBIF_TXDIF1",
++	"APBIF_TXDIF2",
++	"I2S0_TXDIF",
++	"I2S1_TXDIF",
++	"I2S2_TXDIF",
++	"I2S3_TXDIF",
++	"DAM0_TXDIF",
++	"DAM1_TXDIF",
++};
++static const unsigned int ahub_mux_values[] = {
++	0,
++	1 << I2S_RX_APBIF_TXDIF0,
++	1 << I2S_RX_APBIF_TXDIF1,
++	1 << I2S_RX_APBIF_TXDIF2,
++	1 << I2S_RX_I2S0_TXDIF,
++	1 << I2S_RX_I2S1_TXDIF,
++	1 << I2S_RX_I2S2_TXDIF,
++	1 << I2S_RX_I2S3_TXDIF,
++	1 << I2S_RX_DAM0_TXDIF,
++	1 << I2S_RX_DAM1_TXDIF,
++};
++static SOC_ENUM_SINGLE_EXT_DECL(ahub_mux, ahub_mux_text);
++
++static int sunxi_ahub_mux_get(struct snd_kcontrol *kcontrol,
++			      struct snd_ctl_elem_value *ucontrol)
++{
++	int i;
++	unsigned int reg_val;
++	unsigned int src_reg;
++	struct regmap *regmap = g_mem_info.regmap;
++
++	for (i = 0; i < ARRAY_SIZE(ahub_mux_name); i++) {
++		if (!strncmp(ahub_mux_name[i].str, kcontrol->id.name,
++			     strlen(ahub_mux_name[i].str))) {
++			src_reg = ahub_mux_name[i].reg;
++			regmap_read(regmap, src_reg, &reg_val);
++			reg_val &= 0xffffc000;
++			break;
++		}
++	}
++
++	for (i = 1; i < ARRAY_SIZE(ahub_mux_values); i++) {
++		if (reg_val & ahub_mux_values[i]) {
++			ucontrol->value.integer.value[0] = i;
++			return 0;
++		}
++	}
++	ucontrol->value.integer.value[0] = 0;
++
++	return 0;
++}
++
++static int sunxi_ahub_mux_set(struct snd_kcontrol *kcontrol,
++			      struct snd_ctl_elem_value *ucontrol)
++{
++	int i;
++	unsigned int src_reg, src_regbit;
++	struct regmap *regmap = g_mem_info.regmap;
++
++	if (ucontrol->value.integer.value[0] > ARRAY_SIZE(ahub_mux_name))
++		return -EINVAL;
++
++	src_regbit = ahub_mux_values[ucontrol->value.integer.value[0]];
++	for (i = 0; i < ARRAY_SIZE(ahub_mux_name); i++) {
++		if (!strncmp(ahub_mux_name[i].str, kcontrol->id.name,
++			     strlen(ahub_mux_name[i].str))) {
++			src_reg = ahub_mux_name[i].reg;
++			regmap_update_bits(regmap, src_reg, 0xffffc000, src_regbit);
++			break;
++		}
++	}
++
++	return 0;
++}
++
++static const struct snd_kcontrol_new sunxi_ahub_dam_controls[] = {
++	SOC_ENUM_EXT("APBIF0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("APBIF1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("APBIF2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S3 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM0C0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM0C1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM0C2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM1C0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM1C1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM1C2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++};
++
++static struct snd_soc_component_driver sunxi_ahub_dam_dev = {
++	.name		= DRV_NAME,
++	.probe		= sunxi_ahub_dam_probe,
++	.suspend	= sunxi_ahub_dam_suspend,
++	.resume		= sunxi_ahub_dam_resume,
++	.controls	= sunxi_ahub_dam_controls,
++	.num_controls	= ARRAY_SIZE(sunxi_ahub_dam_controls),
++};
++
++/*******************************************************************************
++ * for kernel source
++ ******************************************************************************/
++int snd_soc_sunxi_ahub_mem_get(struct sunxi_ahub_mem_info *mem_info)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (IS_ERR_OR_NULL(g_mem_info.regmap)) {
++		SND_LOG_ERR(HLOG, "regmap is invalid\n");
++		return -EINVAL;
++	}
++	if (IS_ERR_OR_NULL(g_mem_info.res)) {
++		SND_LOG_ERR(HLOG, "res is invalid\n");
++		return -EINVAL;
++	}
++
++	mem_info->regmap = g_mem_info.regmap;
++	mem_info->res = g_mem_info.res;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(snd_soc_sunxi_ahub_mem_get);
++
++int snd_soc_sunxi_ahub_clk_get(struct sunxi_ahub_clk_info *clk_info)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (IS_ERR_OR_NULL(g_clk_info.clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk_pll is invalid\n");
++		return -EINVAL;
++	}
++	//if (IS_ERR_OR_NULL(g_clk_info.clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk_pllx4 is invalid\n");
++	//	return -EINVAL;
++	//}
++	if (IS_ERR_OR_NULL(g_clk_info.clk_module)) {
++		SND_LOG_ERR(HLOG, "clk_module is invalid\n");
++		return -EINVAL;
++	}
++
++	clk_info->clk_pll = g_clk_info.clk_pll;
++	//clk_info->clk_pllx4 = g_clk_info.clk_pllx4;
++	clk_info->clk_module = g_clk_info.clk_module;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(snd_soc_sunxi_ahub_clk_get);
++
++static int snd_soc_sunxi_ahub_mem_init(struct platform_device *pdev,
++				       struct device_node *np,
++				       struct sunxi_ahub_mem_info *mem_info)
++{
++	int ret = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	ret = of_address_to_resource(np, 0, mem_info->res);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "parse device node resource failed\n");
++		ret = -EINVAL;
++		goto err_of_addr_to_resource;
++	}
++
++	mem_info->memregion = devm_request_mem_region(&pdev->dev,
++					mem_info->res->start,
++					resource_size(mem_info->res),
++					DRV_NAME);
++	if (IS_ERR_OR_NULL(mem_info->memregion)) {
++		SND_LOG_ERR(HLOG, "memory region already claimed\n");
++		ret = -EBUSY;
++		goto err_devm_request_region;
++	}
++
++	mem_info->membase = devm_ioremap(&pdev->dev,
++					 mem_info->memregion->start,
++					 resource_size(mem_info->memregion));
++	if (IS_ERR_OR_NULL(mem_info->membase)) {
++		SND_LOG_ERR(HLOG, "ioremap failed\n");
++		ret = -EBUSY;
++		goto err_devm_ioremap;
++	}
++
++	mem_info->regmap = devm_regmap_init_mmio(&pdev->dev,
++						 mem_info->membase,
++						 &g_regmap_config);
++	if (IS_ERR_OR_NULL(mem_info->regmap)) {
++		SND_LOG_ERR(HLOG, "regmap init failed\n");
++		ret = -EINVAL;
++		goto err_devm_regmap_init;
++	}
++
++	return 0;
++
++err_devm_regmap_init:
++	devm_iounmap(&pdev->dev, mem_info->membase);
++err_devm_ioremap:
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++err_devm_request_region:
++err_of_addr_to_resource:
++	return ret;
++};
++
++static int snd_soc_sunxi_ahub_clk_init(struct platform_device *pdev,
++				       struct device_node *np,
++				       struct sunxi_ahub_clk_info *clk_info)
++{
++	int ret = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	/* deassert rst clk */
++	clk_info->clk_rst = devm_reset_control_get(&pdev->dev, NULL);
++	if (IS_ERR_OR_NULL(clk_info->clk_rst)) {
++		SND_LOG_ERR(HLOG, "clk rst get failed\n");
++		ret = -EBUSY;
++		goto err_rst_clk;
++	}
++	if (reset_control_deassert(clk_info->clk_rst)) {
++		SND_LOG_ERR(HLOG, "deassert reset clk failed\n");
++		ret = -EBUSY;
++		goto err_rst_clk;
++	}
++
++	/* enable ahub bus clk */
++	clk_info->clk_bus = of_clk_get_by_name(np, "clk_bus_audio_hub");
++	if (IS_ERR_OR_NULL(clk_info->clk_bus)) {
++		SND_LOG_ERR(HLOG, "clk bus get failed\n");
++		ret = -EBUSY;
++		goto err_bus_clk;
++	}
++	if (clk_prepare_enable(clk_info->clk_bus)) {
++		SND_LOG_ERR(HLOG, "ahub clk bus enable failed\n");
++		ret = -EBUSY;
++		goto err_bus_clk;
++	}
++
++	/* get clk of ahub */
++	clk_info->clk_module = of_clk_get_by_name(np, "clk_audio_hub");
++	if (IS_ERR_OR_NULL(clk_info->clk_module)) {
++		SND_LOG_ERR(HLOG, "clk module get failed\n");
++		ret = -EBUSY;
++		goto err_module_clk;
++	}
++	clk_info->clk_pll = of_clk_get_by_name(np, "clk_pll_audio");
++	if (IS_ERR_OR_NULL(clk_info->clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk pll get failed\n");
++		ret = -EBUSY;
++		goto err_pll_clk;
++	}
++	//clk_info->clk_pllx4 = of_clk_get_by_name(np, "clk_pll_audio_4x");
++	//if (IS_ERR_OR_NULL(clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk pllx4 get failed\n");
++	//	ret = -EBUSY;
++	//	goto err_pllx4_clk;
++	//}
++
++	/* set ahub clk parent */
++	//if (clk_set_parent(clk_info->clk_module, clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "set parent of clk_module to pllx4 failed\n");
++	//	ret = -EINVAL;
++	//	goto err_set_parent_clk;
++	//}
++
++	/* enable clk of ahub */
++	if (clk_prepare_enable(clk_info->clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk_pll enable failed\n");
++		ret = -EBUSY;
++		goto err_pll_clk_enable;
++	}
++	//if (clk_prepare_enable(clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk_pllx4 enable failed\n");
++	//	ret = -EBUSY;
++	//	goto err_pllx4_clk_enable;
++	//}
++	if (clk_prepare_enable(clk_info->clk_module)) {
++		SND_LOG_ERR(HLOG, "clk_module enable failed\n");
++		ret = -EBUSY;
++		goto err_module_clk_enable;
++	}
++
++	return 0;
++
++err_module_clk_enable:
++//	clk_disable_unprepare(clk_info->clk_pllx4);
++//err_pllx4_clk_enable:
++	clk_disable_unprepare(clk_info->clk_pll);
++err_pll_clk_enable:
++//err_set_parent_clk:
++//	clk_put(clk_info->clk_pllx4);
++//err_pllx4_clk:
++//	clk_put(clk_info->clk_pll);
++err_pll_clk:
++	clk_put(clk_info->clk_module);
++err_module_clk:
++	clk_disable_unprepare(clk_info->clk_bus);
++	clk_put(clk_info->clk_bus);
++err_bus_clk:
++	reset_control_assert(clk_info->clk_rst);
++err_rst_clk:
++	return ret;
++}
++
++static int sunxi_ahub_dam_dev_probe(struct platform_device *pdev)
++{
++	int ret;
++	struct device_node *np = pdev->dev.of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	ret = snd_soc_sunxi_ahub_mem_init(pdev, np, &g_mem_info);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "remap init failed\n");
++		ret = -EINVAL;
++		goto err_snd_soc_sunxi_ahub_mem_init;
++	}
++
++	ret = snd_soc_sunxi_ahub_clk_init(pdev, np, &g_clk_info);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "clk init failed\n");
++		ret = -EINVAL;
++		goto err_snd_soc_sunxi_ahub_clk_init;
++	}
++
++	ret = snd_soc_register_component(&pdev->dev,
++					 &sunxi_ahub_dam_dev,
++					 &sunxi_ahub_dam_dai, 1);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "component register failed\n");
++		ret = -ENOMEM;
++		goto err_snd_soc_register_component;
++	}
++
++	SND_LOG_DEBUG(HLOG, "register ahub_dam platform success\n");
++
++	return 0;
++
++err_snd_soc_register_component:
++err_snd_soc_sunxi_ahub_clk_init:
++err_snd_soc_sunxi_ahub_mem_init:
++	of_node_put(np);
++	return ret;
++}
++
++static int sunxi_ahub_dam_dev_remove(struct platform_device *pdev)
++{
++	struct sunxi_ahub_mem_info *mem_info = &g_mem_info;
++	struct sunxi_ahub_clk_info *clk_info = &g_clk_info;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	snd_soc_unregister_component(&pdev->dev);
++
++	devm_iounmap(&pdev->dev, mem_info->membase);
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++
++	clk_disable_unprepare(clk_info->clk_module);
++	clk_put(clk_info->clk_module);
++	clk_disable_unprepare(clk_info->clk_pll);
++	clk_put(clk_info->clk_pll);
++	//clk_disable_unprepare(clk_info->clk_pllx4);
++	//clk_put(clk_info->clk_pllx4);
++	clk_disable_unprepare(clk_info->clk_bus);
++	clk_put(clk_info->clk_bus);
++	reset_control_assert(clk_info->clk_rst);
++
++	SND_LOG_DEBUG(HLOG, "unregister ahub_dam platform success\n");
++
++	return 0;
++}
++
++static const struct of_device_id sunxi_ahub_dam_of_match[] = {
++	{ .compatible = "allwinner," DRV_NAME, },
++	{},
++};
++MODULE_DEVICE_TABLE(of, sunxi_ahub_dam_of_match);
++
++static struct platform_driver sunxi_ahub_dam_driver = {
++	.driver	= {
++		.name		= DRV_NAME,
++		.owner		= THIS_MODULE,
++		.of_match_table	= sunxi_ahub_dam_of_match,
++	},
++	.probe	= sunxi_ahub_dam_dev_probe,
++	.remove	= sunxi_ahub_dam_dev_remove,
++};
++
++int __init sunxi_ahub_dam_dev_init(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&sunxi_ahub_dam_driver);
++	if (ret != 0) {
++		SND_LOG_ERR(HLOG, "platform driver register failed\n");
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
++void __exit sunxi_ahub_dam_dev_exit(void)
++{
++	platform_driver_unregister(&sunxi_ahub_dam_driver);
++}
++
++late_initcall(sunxi_ahub_dam_dev_init);
++module_exit(sunxi_ahub_dam_dev_exit);
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard platform of ahub_dam");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h
+new file mode 100644
+index 000000000000..b7679bf545e9
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h
+@@ -0,0 +1,291 @@
++/* sound\soc\sunxi\snd_sunxi_ahub_dam.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * some simple description for this code
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ */
++#ifndef __SND_SUNXI_AHUB_DAM_H
++#define __SND_SUNXI_AHUB_DAM_H
++
++/* SUNXI Audio Hub registers list */
++#define SUNXI_AHUB_CTL				0x00
++#define SUNXI_AHUB_VER				0x04
++#define SUNXI_AHUB_RST				0x08
++#define SUNXI_AHUB_GAT				0x0c
++
++#define SUNXI_AHUB_APBIF_TX_CTL(n)		(0x10 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TX_IRQ_CTL(n)		(0x14 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TX_IRQ_STA(n)		(0x18 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_TXFIFO_CTL(n)		(0x20 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TXFIFO_STA(n)		(0x24 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_TXFIFO(n)		(0x30 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TXFIFO_CNT(n)		(0x34 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_RX_CTL(n)		(0x100 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RX_IRQ_CTL(n)		(0x104 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RX_IRQ_STA(n)		(0x108 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_RXFIFO_CTL(n)		(0x110 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RXFIFO_STA(n)		(0x114 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RXFIFO_CONT(n)		(0x118 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_RXFIFO(n)		(0x120 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RXFIFO_CNT(n)		(0x124 + ((n) * 0x30))
++
++#define SUNXI_AHUB_I2S_CTL(n)			(0x200 + ((n) << 8))
++#define SUNXI_AHUB_I2S_FMT0(n)			(0x204 + ((n) << 8))
++#define SUNXI_AHUB_I2S_FMT1(n)			(0x208 + ((n) << 8))
++#define SUNXI_AHUB_I2S_CLKD(n)			(0x20c + ((n) << 8))
++
++#define SUNXI_AHUB_I2S_RXCONT(n)		(0x220 + ((n) << 8))
++#define SUNXI_AHUB_I2S_CHCFG(n)			(0x224 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IRQ_CTL(n)		(0x228 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IRQ_STA(n)		(0x22C + ((n) << 8))
++#define SUNXI_AHUB_I2S_OUT_SLOT(n, m)		(0x230 + ((n) << 8) + ((m) << 4))
++#define SUNXI_AHUB_I2S_OUT_CHMAP0(n, m)		(0x234 + ((n) << 8) + ((m) << 4))
++#define SUNXI_AHUB_I2S_OUT_CHMAP1(n, m)		(0x238 + ((n) << 8) + ((m) << 4))
++
++#define SUNXI_AHUB_I2S_IN_SLOT(n)		(0x270 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP0(n)		(0x274 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP1(n)		(0x278 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP2(n)		(0x27C + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP3(n)		(0x280 + ((n) << 8))
++
++#define SUNXI_AHUB_DAM_CTL(n)			(0xA00 + ((n) << 7))
++
++#define SUNXI_AHUB_DAM_RX0_SRC(n)		(0xA10 + ((n) << 7))
++#define SUNXI_AHUB_DAM_RX1_SRC(n)		(0xA14 + ((n) << 7))
++#define SUNXI_AHUB_DAM_RX2_SRC(n)		(0xA18 + ((n) << 7))
++
++#define SUNXI_AHUB_DAM_MIX_CTL0(n)		(0xA30 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL1(n)		(0xA34 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL2(n)		(0xA38 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL3(n)		(0xA3C + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL4(n)		(0xA40 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL5(n)		(0xA44 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL6(n)		(0xA48 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL7(n)		(0xA4C + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL0(n)		(0xA50 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL1(n)		(0xA54 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL2(n)		(0xA58 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL3(n)		(0xA5C + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL4(n)		(0xA60 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL5(n)		(0xA64 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL6(n)		(0xA68 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL7(n)		(0xA6C + ((n) << 7))
++
++#define SUNXI_AHUB_MAX_REG			SUNXI_AHUB_DAM_GAIN_CTL7(1)
++
++/* SUNXI_AHUB_CTL */
++#define HDMI_SRC_SEL			0x04
++
++/* SUNXI_AHUB_RST */
++#define APBIF_TXDIF0_RST		31
++#define APBIF_TXDIF1_RST		30
++#define APBIF_TXDIF2_RST		29
++#define APBIF_RXDIF0_RST		27
++#define APBIF_RXDIF1_RST		26
++#define APBIF_RXDIF2_RST		25
++#define I2S0_RST			23
++#define I2S1_RST			22
++#define I2S2_RST			21
++#define I2S3_RST			20
++#define DAM0_RST			15
++#define DAM1_RST			14
++
++/* SUNXI_AHUB_GAT */
++#define APBIF_TXDIF0_GAT		31
++#define APBIF_TXDIF1_GAT		30
++#define APBIF_TXDIF2_GAT		29
++#define APBIF_RXDIF0_GAT		27
++#define APBIF_RXDIF1_GAT		26
++#define APBIF_RXDIF2_GAT		25
++#define I2S0_GAT			23
++#define I2S1_GAT			22
++#define I2S2_GAT			21
++#define I2S3_GAT			20
++#define DAM0_GAT			15
++#define DAM1_GAT			14
++
++/* SUNXI_AHUB_APBIF_TX_CTL */
++#define APBIF_TX_WS			16
++#define APBIF_TX_CHAN_NUM		8
++#define	APBIF_TX_START			4
++
++/* SUNXI_AHUB_APBIF_TX_IRQ_CTL */
++#define APBIF_TX_DRQ			3
++#define APBIF_TX_OVEN			1
++#define APBIF_TX_EMEN			0
++
++/* SUNXI_AHUB_APBIF_TX_IRQ_STA */
++#define APBIF_TX_OV_PEND		2
++#define APBIF_TX_EM_PEND		0
++
++/* SUNXI_AHUB_APBIF_TXFIFO_CTL */
++#define APBIF_TX_FTX			12
++#define APBIF_TX_LEVEL			4
++#define APBIF_TX_TXIM			0
++
++/* SUNXI_AHUB_APBIF_TXFIFO_STA */
++#define APBIF_TX_EMPTY			8
++#define APBIF_TX_EMCNT			0
++
++/* SUNXI_AHUB_APBIF_RX_CTL */
++#define APBIF_RX_WS			16
++#define APBIF_RX_CHAN_NUM		8
++#define	APBIF_RX_START			4
++
++/* SUNXI_AHUB_APBIF_RX_IRQ_CTL */
++#define APBIF_RX_DRQ			3
++#define APBIF_RX_UVEN			2
++#define APBIF_RX_AVEN			0
++
++/* SUNXI_AHUB_APBIF_RX_IRQ_STA */
++#define APBIF_RX_UV_PEND		2
++#define APBIF_RX_AV_PEND		0
++
++/* SUNXI_AHUB_APBIF_RXFIFO_CTL */
++#define APBIF_RX_FRX			12
++#define APBIF_RX_LEVEL			4
++#define APBIF_RX_RXOM			0
++
++/* SUNXI_AHUB_APBIF_RXFIFO_STA */
++#define APBIF_RX_AVAIL			8
++#define APBIF_RX_AVCNT			0
++
++/* SUNXI_AHUB_APBIF_RXFIFO_CONT */
++#define APBIF_RX_APBIF_TXDIF0		31
++#define APBIF_RX_APBIF_TXDIF1		30
++#define APBIF_RX_APBIF_TXDIF2		29
++#define APBIF_RX_I2S0_TXDIF		27
++#define APBIF_RX_I2S1_TXDIF		26
++#define APBIF_RX_I2S2_TXDIF		25
++#define APBIF_RX_I2S3_TXDIF		23
++#define APBIF_RX_DAM0_TXDIF		19
++#define APBIF_RX_DAM1_TXDIF		15
++
++/* SUNXI_AHUB_I2S_CTL */
++#define I2S_CTL_LOOP3			23
++#define I2S_CTL_LOOP2			22
++#define I2S_CTL_LOOP1			21
++#define I2S_CTL_LOOP0			20
++#define I2S_CTL_SDI3_EN			15
++#define I2S_CTL_SDI2_EN			14
++#define I2S_CTL_SDI1_EN			13
++#define I2S_CTL_SDI0_EN			12
++#define I2S_CTL_CLK_OUT			18
++#define I2S_CTL_SDO3_EN			11
++#define I2S_CTL_SDO2_EN			10
++#define I2S_CTL_SDO1_EN			9
++#define I2S_CTL_SDO0_EN			8
++#define I2S_CTL_OUT_MUTE		6
++#define I2S_CTL_MODE			4
++#define I2S_CTL_TXEN			2
++#define I2S_CTL_RXEN			1
++#define I2S_CTL_GEN			0
++
++/* SUNXI_AHUB_I2S_FMT0 */
++#define I2S_FMT0_LRCK_WIDTH		30
++#define I2S_FMT0_LRCK_POLARITY		19
++#define I2S_FMT0_LRCK_PERIOD		8
++#define I2S_FMT0_BCLK_POLARITY		7
++#define I2S_FMT0_SR			4
++#define I2S_FMT0_EDGE			3
++#define I2S_FMT0_SW			0
++
++/* SUNXI_AHUB_I2S_FMT1 */
++#define I2S_FMT1_RX_LSB			7
++#define I2S_FMT1_TX_LSB			6
++#define I2S_FMT1_EXT			4
++#define I2S_FMT1_RX_PDM			2
++#define I2S_FMT1_TX_PDM			0
++
++/* SUNXI_AHUB_I2S_CLKD */
++#define I2S_CLKD_MCLK			8
++#define	I2S_CLKD_BCLKDIV		4
++#define I2S_CLKD_MCLKDIV		0
++
++/* SUNXI_AHUB_I2S_RXCONT */
++#define I2S_RX_APBIF_TXDIF0		31
++#define I2S_RX_APBIF_TXDIF1		30
++#define I2S_RX_APBIF_TXDIF2		29
++#define I2S_RX_I2S0_TXDIF		27
++#define I2S_RX_I2S1_TXDIF		26
++#define I2S_RX_I2S2_TXDIF		25
++#define I2S_RX_I2S3_TXDIF		23
++#define I2S_RX_DAM0_TXDIF		19
++#define I2S_RX_DAM1_TXDIF		15
++
++/* SUNXI_AHUB_I2S_CHCFG */
++#define I2S_CHCFG_HIZ			9
++#define	I2S_CHCFG_TX_STATE		8
++#define I2S_CHCFG_RX_CHANNUM		4
++#define I2S_CHCFG_TX_CHANNUM		0
++
++/* SUNXI_AHUB_I2S_IRQ_CTL */
++#define I2S_IRQ_RXOV_EN			1
++#define I2S_IRQ_TXUV_EN			0
++
++/* SUNXI_AHUB_I2S_IRQ_STA */
++#define I2S_IRQ_RXOV_PEND		1
++#define I2S_IRQ_TXUV_PEND		0
++
++/* SUNXI_AHUB_I2S_OUT_SLOT */
++#define I2S_OUT_OFFSET			20
++#define I2S_OUT_SLOT_NUM		16
++#define I2S_OUT_SLOT_EN			0
++
++/* SUNXI_AHUB_I2S_IN_SLOT */
++#define I2S_IN_OFFSET			20
++#define I2S_IN_SLOT_NUM			16
++
++/* SUNXI_AHUB_DAM_CTL */
++#define DAM_CTL_RX2_NUM			24
++#define DAM_CTL_RX1_NUM			20
++#define DAM_CTL_RX0_NUM			16
++#define DAM_CTL_TX_NUM			8
++#define DAM_CTL_RX2EN			6
++#define DAM_CTL_RX1EN			5
++#define DAM_CTL_RX0EN			4
++#define DAM_CTL_TXEN			0
++
++/* SUNXI_AHUB_DAM_RX##chan##_SRC */
++#define DAM_RX_APBIF_TXDIF0		31
++#define DAM_RX_APBIF_TXDIF1		30
++#define DAM_RX_APBIF_TXDIF2		29
++#define DAM_RX_I2S0_TXDIF		27
++#define DAM_RX_I2S1_TXDIF		26
++#define DAM_RX_I2S2_TXDIF		25
++#define DAM_RX_I2S3_TXDIF		23
++#define DAM_RX_DAM0_TXDIF		19
++#define DAM_RX_DAM1_TXDIF		15
++
++struct sunxi_ahub_mem_info {
++	char *dev_name;
++	struct resource *res;
++	void __iomem *membase;
++	struct resource *memregion;
++	struct regmap *regmap;
++};
++
++struct sunxi_ahub_clk_info {
++	struct clk *clk_pll;
++	struct clk *clk_pllx4;
++	struct clk *clk_module;
++	struct clk *clk_bus;
++	struct reset_control *clk_rst;
++};
++
++extern int snd_soc_sunxi_ahub_mem_get(struct sunxi_ahub_mem_info *mem_info);
++extern int snd_soc_sunxi_ahub_clk_get(struct sunxi_ahub_clk_info *clk_info);
++
++#endif /* __SND_SUNXI_AHUB_DAM_H */
+\ No newline at end of file
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_common.c b/sound/soc/sunxi_v2/snd_sunxi_common.c
+new file mode 100644
+index 000000000000..410ab75aea5a
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_common.c
+@@ -0,0 +1,267 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_common.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/device.h>
++#include <linux/ioport.h>
++#include <linux/regmap.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_common.h"
++
++#define HLOG		"COMMON"
++
++/* for regmap */
++int snd_sunxi_mem_init(struct platform_device *pdev,
++		       struct sunxi_mem_info *mem_info)
++{
++	int ret = 0;
++	struct device_node *np = pdev->dev.of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	ret = of_address_to_resource(np, 0, mem_info->res);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "parse device node resource failed\n");
++		ret = -EINVAL;
++		goto err_of_addr_to_resource;
++	}
++
++	mem_info->memregion = devm_request_mem_region(&pdev->dev,
++					mem_info->res->start,
++					resource_size(mem_info->res),
++					mem_info->dev_name);
++	if (IS_ERR_OR_NULL(mem_info->memregion)) {
++		SND_LOG_ERR(HLOG, "memory region already claimed\n");
++		ret = -EBUSY;
++		goto err_devm_request_region;
++	}
++
++	mem_info->membase = devm_ioremap(&pdev->dev,
++					 mem_info->memregion->start,
++					 resource_size(mem_info->memregion));
++	if (IS_ERR_OR_NULL(mem_info->membase)) {
++		SND_LOG_ERR(HLOG, "ioremap failed\n");
++		ret = -EBUSY;
++		goto err_devm_ioremap;
++	}
++
++	mem_info->regmap = devm_regmap_init_mmio(&pdev->dev,
++						 mem_info->membase,
++						 mem_info->regmap_config);
++	if (IS_ERR_OR_NULL(mem_info->regmap)) {
++		SND_LOG_ERR(HLOG, "regmap init failed\n");
++		ret = -EINVAL;
++		goto err_devm_regmap_init;
++	}
++
++	return 0;
++
++err_devm_regmap_init:
++	devm_iounmap(&pdev->dev, mem_info->membase);
++err_devm_ioremap:
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++err_devm_request_region:
++err_of_addr_to_resource:
++	return ret;
++}
++
++void snd_sunxi_mem_exit(struct platform_device *pdev,
++			struct sunxi_mem_info *mem_info)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	devm_iounmap(&pdev->dev, mem_info->membase);
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++}
++
++/* for reg labels */
++int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels)
++{
++	int i = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	while (reg_labels[i].name != NULL) {
++		regmap_read(regmap,
++			    reg_labels[i].address, &(reg_labels[i].value));
++		i++;
++	}
++
++	return i;
++}
++
++int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels)
++{
++	int i = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	while (reg_labels[i].name != NULL) {
++		regmap_write(regmap,
++			     reg_labels[i].address, reg_labels[i].value);
++		i++;
++	}
++
++	return i;
++}
++
++/* for pa config */
++struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev,
++					u32 *pa_pin_max)
++{
++	int ret, i;
++	u32 pin_max;
++	u32 gpio_tmp;
++	u32 temp_val;
++	char str[20] = {0};
++	struct pa_config *pa_cfg;
++	struct device_node *np = pdev->dev.of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	*pa_pin_max = 0;
++	ret = of_property_read_u32(np, "pa_pin_max", &temp_val);
++	if (ret < 0) {
++		SND_LOG_WARN(HLOG, "pa_pin_max get failed, default 0\n");
++		return NULL;
++	} else {
++		pin_max = temp_val;
++	}
++
++	pa_cfg = kzalloc(sizeof(struct pa_config) * pin_max, GFP_KERNEL);
++	if (!pa_cfg) {
++		SND_LOG_ERR(HLOG, "can't pa_config memory\n");
++		return NULL;
++	}
++
++	for (i = 0; i < pin_max; i++) {
++		sprintf(str, "pa_pin_%d", i);
++		ret = of_get_named_gpio(np, str, 0);
++		if (ret < 0) {
++			SND_LOG_ERR(HLOG, "pa_pin_%u get failed\n", i);
++			pa_cfg[i].used = 0;
++			continue;
++		}
++		gpio_tmp = ret;
++		if (!gpio_is_valid(gpio_tmp)) {
++			SND_LOG_ERR(HLOG, "pa_pin_%u (%u) is invalid\n",
++				    i, gpio_tmp);
++			pa_cfg[i].used = 0;
++			continue;
++		}
++		ret = devm_gpio_request(&pdev->dev, gpio_tmp, str);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "pa_pin_%u (%u) request failed\n",
++				    i, gpio_tmp);
++			pa_cfg[i].used = 0;
++			continue;
++		}
++		pa_cfg[i].used = 1;
++		pa_cfg[i].pin = gpio_tmp;
++
++		sprintf(str, "pa_pin_level_%d", i);
++		ret = of_property_read_u32(np, str, &temp_val);
++		if (ret < 0) {
++			SND_LOG_WARN(HLOG, "%s get failed, default low\n", str);
++			pa_cfg[i].level = 0;
++		} else {
++			if (temp_val > 0)
++				pa_cfg[i].level = 1;
++		}
++		sprintf(str, "pa_pin_msleep_%d", i);
++		ret = of_property_read_u32(np, str, &temp_val);
++		if (ret < 0) {
++			SND_LOG_WARN(HLOG, "%s get failed, default 0\n", str);
++			pa_cfg[i].msleep = 0;
++		} else {
++			pa_cfg[i].msleep = temp_val;
++		}
++	}
++
++	*pa_pin_max = pin_max;
++	snd_sunxi_pa_pin_disable(pa_cfg, pin_max);
++
++	return pa_cfg;
++}
++
++void snd_sunxi_pa_pin_exit(struct platform_device *pdev,
++			   struct pa_config *pa_cfg, u32 pa_pin_max)
++{
++	int i;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	snd_sunxi_pa_pin_disable(pa_cfg, pa_pin_max);
++
++	for (i = 0; i < pa_pin_max; i++) {
++		if (!pa_cfg[i].used)
++			continue;
++
++		gpio_free(pa_cfg[i].pin);
++	}
++
++	if (pa_cfg)
++		kfree(pa_cfg);
++}
++
++int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max)
++{
++	int i;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (pa_pin_max < 1) {
++		SND_LOG_DEBUG(HLOG, "no pa pin config\n");
++		return 0;
++	}
++
++	for (i = 0; i < pa_pin_max; i++) {
++		if (!pa_cfg[i].used)
++			continue;
++
++		gpio_direction_output(pa_cfg[i].pin, 1);
++		gpio_set_value(pa_cfg[i].pin, pa_cfg[i].level);
++	}
++
++	return 0;
++}
++
++void snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max)
++{
++	int i;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (pa_pin_max < 1) {
++		SND_LOG_DEBUG(HLOG, "no pa pin config\n");
++		return;
++	}
++
++	for (i = 0; i < pa_pin_max; i++) {
++		if (!pa_cfg[i].used)
++			continue;
++
++		gpio_direction_output(pa_cfg[i].pin, 1);
++		gpio_set_value(pa_cfg[i].pin, !pa_cfg[i].level);
++	}
++}
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_common.h b/sound/soc/sunxi_v2/snd_sunxi_common.h
+new file mode 100644
+index 000000000000..7b88d20c25e0
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_common.h
+@@ -0,0 +1,67 @@
++/* sound\soc\sunxi\snd_sunxi_common.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_COMMON_H
++#define __SND_SUNXI_COMMON_H
++
++/* for regmap */
++struct sunxi_mem_info {
++	char *dev_name;
++	struct resource *res;
++	struct regmap_config *regmap_config;
++
++	void __iomem *membase;
++	struct resource *memregion;
++	struct regmap *regmap;
++};
++
++int snd_sunxi_mem_init(struct platform_device *pdev,
++		       struct sunxi_mem_info *mem_info);
++void snd_sunxi_mem_exit(struct platform_device *pdev,
++			struct sunxi_mem_info *mem_info);
++
++/* for reg debug */
++#define REG_LABEL(constant)	{#constant, constant, 0}
++#define REG_LABEL_END		{NULL, 0, 0}
++
++struct reg_label {
++	const char *name;
++	const unsigned int address;
++	unsigned int value;
++};
++
++/* EX:
++ * static struct reg_label reg_labels[] = {
++ * 	REG_LABEL(SUNXI_REG_0),
++ * 	REG_LABEL(SUNXI_REG_1),
++ * 	REG_LABEL(SUNXI_REG_n),
++ * 	REG_LABEL_END,
++ * };
++ */
++int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels);
++int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels);
++
++/* for pa config */
++struct pa_config {
++	u32 pin;
++	u32 msleep;
++	bool used;
++	bool level;
++};
++
++struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev,
++					u32 *pa_pin_max);
++void snd_sunxi_pa_pin_exit(struct platform_device *pdev,
++			   struct pa_config *pa_cfg, u32 pa_pin_max);
++int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max);
++void snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max);
++
++#endif /* __SND_SUNXI_COMMON_H */
+\ No newline at end of file
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_log.h b/sound/soc/sunxi_v2/snd_sunxi_log.h
+new file mode 100644
+index 000000000000..89ad9fe71936
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_log.h
+@@ -0,0 +1,29 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_log.h
++ * (C) Copyright 2021-2025
++ * allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_LOG_H
++#define __SND_SUNXI_LOG_H
++#include <linux/kernel.h>
++
++#define SND_LOG_ERR(head, fmt, arg...) \
++	pr_err("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#define SND_LOG_WARN(head, fmt, arg...) \
++	pr_warn("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#define SND_LOG_INFO(head, fmt, arg...) \
++	pr_info("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#define SND_LOG_DEBUG(head, fmt, arg...) \
++	pr_debug("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#endif /* __SND_SUNXI_LOG_H */
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach.c b/sound/soc/sunxi_v2/snd_sunxi_mach.c
+new file mode 100644
+index 000000000000..27449ad6b843
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach.c
+@@ -0,0 +1,479 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_mach.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * based on ${LINUX}/sound/soc/generic/simple-card.c
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <sound/soc.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_mach.h"
++
++#define HLOG		"MACH"
++#define DAI		"sound-dai"
++#define CELL		"#sound-dai-cells"
++#define PREFIX		"soundcard-mach,"
++
++#define DRV_NAME	"sunxi-snd-mach"
++
++static void asoc_simple_shutdown(struct snd_pcm_substream *substream)
++{
++}
++
++static int asoc_simple_startup(struct snd_pcm_substream *substream)
++{
++	return 0;
++}
++
++static int asoc_simple_hw_params(struct snd_pcm_substream *substream,
++				 struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++
++	struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
++	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
++
++	struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card);
++	struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, rtd->num);
++	struct simple_dai_props *dai_props = simple_priv_to_props(priv, rtd->num);
++	struct asoc_simple_dai *dais = priv->dais;
++	unsigned int mclk;
++	unsigned int cpu_pll_clk, codec_pll_clk;
++	unsigned int cpu_bclk_ratio, codec_bclk_ratio;
++	unsigned int freq_point;
++	int cpu_clk_div, codec_clk_div;
++	int ret = 0;
++
++	switch (params_rate(params)) {
++	case 8000:
++	case 12000:
++	case 16000:
++	case 24000:
++	case 32000:
++	case 48000:
++	case 64000:
++	case 96000:
++	case 192000:
++		freq_point = 24576000;
++		break;
++	case 11025:
++	case 22050:
++	case 44100:
++	case 88200:
++	case 176400:
++		freq_point = 22579200;
++		break;
++	default:
++		SND_LOG_ERR(HLOG, "Invalid rate %d\n", params_rate(params));
++		return -EINVAL;
++	}
++
++	/* for cpudai pll clk */
++	cpu_pll_clk	= freq_point * dai_props->cpu_pll_fs;
++	codec_pll_clk	= freq_point * dai_props->codec_pll_fs;
++	cpu_clk_div	= cpu_pll_clk / params_rate(params);
++	codec_clk_div	= codec_pll_clk / params_rate(params);
++	SND_LOG_DEBUG(HLOG, "freq point   : %u\n", freq_point);
++	SND_LOG_DEBUG(HLOG, "cpu pllclk   : %u\n", cpu_pll_clk);
++	SND_LOG_DEBUG(HLOG, "codec pllclk : %u\n", codec_pll_clk);
++	SND_LOG_DEBUG(HLOG, "cpu clk_div  : %u\n", cpu_clk_div);
++	SND_LOG_DEBUG(HLOG, "codec clk_div: %u\n", codec_clk_div);
++
++	if (cpu_dai->driver->ops->set_pll) {
++		ret = snd_soc_dai_set_pll(cpu_dai, substream->stream, 0,
++					  cpu_pll_clk, cpu_pll_clk);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set pllclk failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_pll) {
++		ret = snd_soc_dai_set_pll(codec_dai, substream->stream, 0,
++					  codec_pll_clk, codec_pll_clk);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec_dai set pllclk failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_clkdiv) {
++		ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, cpu_clk_div);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set clk_div failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_clkdiv) {
++		ret = snd_soc_dai_set_clkdiv(codec_dai, 0, codec_clk_div);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cadec_dai set clk_div failed.\n");
++			return ret;
++		}
++	}
++
++	/* use for tdm only */
++	if (!(dais->slots && dais->slot_width))
++		return 0;
++
++	/* for cpudai & codecdai mclk */
++	if (dai_props->mclk_fp)
++		mclk = (freq_point >> 1) * dai_props->mclk_fs;
++	else
++		mclk = params_rate(params) * dai_props->mclk_fs;
++	cpu_bclk_ratio = cpu_pll_clk / (params_rate(params) * dais->slot_width * dais->slots);
++	codec_bclk_ratio = codec_pll_clk / (params_rate(params) * dais->slot_width * dais->slots);
++	SND_LOG_DEBUG(HLOG, "mclk            : %u\n", mclk);
++	SND_LOG_DEBUG(HLOG, "cpu_bclk_ratio  : %u\n", cpu_bclk_ratio);
++	SND_LOG_DEBUG(HLOG, "codec_bclk_ratio: %u\n", codec_bclk_ratio);
++
++	if (cpu_dai->driver->ops->set_sysclk) {
++		ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk, SND_SOC_CLOCK_OUT);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set sysclk(mclk) failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_sysclk) {
++		ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk, SND_SOC_CLOCK_IN);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cadec_dai set sysclk(mclk) failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_bclk_ratio) {
++		ret = snd_soc_dai_set_bclk_ratio(cpu_dai, cpu_bclk_ratio);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set bclk failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_bclk_ratio) {
++		ret = snd_soc_dai_set_bclk_ratio(codec_dai, codec_bclk_ratio);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec_dai set bclk failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_fmt) {
++		ret = snd_soc_dai_set_fmt(cpu_dai, dai_link->dai_fmt);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu dai set fmt failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_fmt) {
++		ret = snd_soc_dai_set_fmt(codec_dai, dai_link->dai_fmt);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec dai set fmt failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_tdm_slot) {
++		ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 0, dais->slots, dais->slot_width);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu dai set tdm slot failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_tdm_slot) {
++		ret = snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, dais->slots, dais->slot_width);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec dai set tdm slot failed\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static struct snd_soc_ops simple_ops = {
++	.startup = asoc_simple_startup,
++	.shutdown = asoc_simple_shutdown,
++	.hw_params = asoc_simple_hw_params,
++};
++
++static int asoc_simple_dai_init(struct snd_soc_pcm_runtime *rtd)
++{
++	int i;
++	struct snd_soc_card *card = rtd->card;
++	struct snd_soc_dapm_context *dapm = &card->dapm;
++
++	const struct snd_kcontrol_new *controls = card->controls;
++
++	for (i = 0; i < card->num_controls; i++)
++		if (controls[i].info == snd_soc_dapm_info_pin_switch)
++			snd_soc_dapm_disable_pin(dapm,
++				(const char *)controls[i].private_value);
++
++	if (card->num_controls)
++		snd_soc_dapm_sync(dapm);
++
++	/* snd_soc_dai_set_sysclk(); */
++	/* snd_soc_dai_set_tdm_slot(); */
++
++	return 0;
++}
++
++static int simple_dai_link_of(struct device_node *node,
++			      struct asoc_simple_priv *priv)
++{
++	struct device *dev = simple_priv_to_dev(priv);
++	struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, 0);
++	struct simple_dai_props *dai_props = simple_priv_to_props(priv, 0);
++	struct device_node *top_np = NULL;
++	struct device_node *cpu = NULL;
++	struct device_node *plat = NULL;
++	struct device_node *codec = NULL;
++	char prop[128];
++	char *prefix = "";
++	int ret, single_cpu;
++
++	prefix = PREFIX;
++	top_np = node;
++
++	snprintf(prop, sizeof(prop), "%scpu", prefix);
++	cpu = of_get_child_by_name(top_np, prop);
++	if (!cpu) {
++		ret = -EINVAL;
++		SND_LOG_ERR(HLOG, "Can't find %s DT node\n", prop);
++		goto dai_link_of_err;
++	}
++	snprintf(prop, sizeof(prop), "%splat", prefix);
++	plat = of_get_child_by_name(top_np, prop);
++
++	snprintf(prop, sizeof(prop), "%scodec", prefix);
++	codec = of_get_child_by_name(top_np, prop);
++	if (!codec) {
++		ret = -EINVAL;
++		SND_LOG_ERR(HLOG, "Can't find %s DT node\n", prop);
++		goto dai_link_of_err;
++	}
++
++	ret = asoc_simple_parse_daifmt(top_np, codec, prefix, &dai_link->dai_fmt);
++	if (ret < 0)
++		goto dai_link_of_err;
++	/* sunxi: parse stream direction
++	 * ex1)
++	 * top_node {
++	 *	PREFIXplayback-only;
++	 * }
++	 * ex2)
++	 * top_node {
++	 *	PREFIXcapture-only;
++	 * }
++	 */
++	ret = asoc_simple_parse_daistream(top_np, prefix, dai_link);
++	if (ret < 0)
++		goto dai_link_of_err;
++	/* sunxi: parse slot-num & slot-width
++	 * ex)
++	 * top_node {
++	 *	PREFIXplayslot-num	= <x>;
++	 *	PREFIXplayslot-width	= <x>;
++	 * }
++	 */
++	ret = asoc_simple_parse_tdm_slot(top_np, prefix, priv->dais);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	ret = asoc_simple_parse_cpu(cpu, dai_link, DAI, CELL, &single_cpu);
++	if (ret < 0)
++		goto dai_link_of_err;
++	ret = asoc_simple_parse_codec(codec, dai_link, DAI, CELL);
++	if (ret < 0) {
++		if (ret == -EPROBE_DEFER)
++			goto dai_link_of_err;
++		dai_link->codecs->name = "snd-soc-dummy";
++		dai_link->codecs->dai_name = "snd-soc-dummy-dai";
++		/* dai_link->codecs->name = "sunxi-dummy-codec"; */
++		/* dai_link->codecs->dai_name = "sunxi-dummy-codec-dai"; */
++		SND_LOG_DEBUG(HLOG, "use dummy codec for simple card.\n");
++	}
++	ret = asoc_simple_parse_platform(plat, dai_link, DAI, CELL);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	/* sunxi: parse pll-fs & mclk-fs
++	 * ex)
++	 * top_node {
++	 *	PREFIXcpu {
++	 *		PREFIXpll-fs	= <x>;
++	 *		PREFIXmclk-fs	= <x>;
++	 *	}
++	 * }
++	 */
++	ret = asoc_simple_parse_tdm_clk(cpu, codec, prefix, dai_props);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	ret = asoc_simple_set_dailink_name(dev, dai_link,
++					   "%s-%s",
++					   dai_link->cpus->dai_name,
++					   dai_link->codecs->dai_name);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	dai_link->ops = &simple_ops;
++	dai_link->init = asoc_simple_dai_init;
++
++	SND_LOG_DEBUG(HLOG, "name   : %s\n", dai_link->stream_name);
++	SND_LOG_DEBUG(HLOG, "format : %x\n", dai_link->dai_fmt);
++	SND_LOG_DEBUG(HLOG, "cpu    : %s\n", dai_link->cpus->name);
++	SND_LOG_DEBUG(HLOG, "codec  : %s\n", dai_link->codecs->name);
++
++	asoc_simple_canonicalize_cpu(dai_link, single_cpu);
++	asoc_simple_canonicalize_platform(dai_link);
++
++dai_link_of_err:
++	of_node_put(cpu);
++	of_node_put(plat);
++	of_node_put(codec);
++
++	return ret;
++}
++
++static int simple_parse_of(struct asoc_simple_priv *priv)
++{
++	int ret;
++	struct device *dev = simple_priv_to_dev(priv);
++	struct snd_soc_card *card = simple_priv_to_card(priv);
++	struct device_node *top_np = dev->of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (!top_np)
++		return -EINVAL;
++
++	/* DAPM widgets */
++	ret = asoc_simple_parse_widgets(card, PREFIX);
++	if (ret < 0)
++		return ret;
++
++	/* DAPM routes */
++	ret = asoc_simple_parse_routing(card, PREFIX);
++	if (ret < 0)
++		return ret;
++
++	/* DAPM pin_switches */
++	ret = asoc_simple_parse_pin_switches(card, PREFIX);
++	if (ret < 0)
++		return ret;
++
++	/* For single DAI link & old style of DT node */
++	ret = simple_dai_link_of(top_np, priv);
++	if (ret < 0)
++		return ret;
++
++	ret = asoc_simple_parse_card_name(card, PREFIX);
++	return ret;
++}
++
++static int simple_soc_probe(struct snd_soc_card *card)
++{
++	return 0;
++}
++
++static int asoc_simple_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *top_np = dev->of_node;
++	struct asoc_simple_priv *priv;
++	struct snd_soc_card *card;
++	int ret;
++
++	/* Allocate the private data and the DAI link array */
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	card = simple_priv_to_card(priv);
++	card->owner		= THIS_MODULE;
++	card->dev		= dev;
++	card->probe		= simple_soc_probe;
++
++	ret = asoc_simple_init_priv(priv);
++	if (ret < 0)
++		return ret;
++
++	if (top_np && of_device_is_available(top_np)) {
++		ret = simple_parse_of(priv);
++		if (ret < 0) {
++			if (ret != -EPROBE_DEFER)
++				SND_LOG_ERR(HLOG, "parse error %d\n", ret);
++			goto err;
++		}
++	} else {
++		SND_LOG_ERR(HLOG, "simple card dts available\n");
++	}
++
++	snd_soc_card_set_drvdata(card, priv);
++
++	/* asoc_simple_debug_info(priv); */
++	ret = devm_snd_soc_register_card(dev, card);
++	if (ret >= 0)
++		return ret;
++err:
++	asoc_simple_clean_reference(card);
++
++	return ret;
++}
++
++static int asoc_simple_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++	return asoc_simple_clean_reference(card);
++}
++
++static const struct of_device_id snd_soc_sunxi_of_match[] = {
++	{ .compatible = "allwinner," DRV_NAME, },
++	{},
++};
++MODULE_DEVICE_TABLE(of, snd_soc_sunxi_of_match);
++
++static struct platform_driver sunxi_soundcard_machine_driver = {
++	.driver	= {
++		.name		= DRV_NAME,
++		.pm		= &snd_soc_pm_ops,
++		.of_match_table	= snd_soc_sunxi_of_match,
++	},
++	.probe	= asoc_simple_probe,
++	.remove	= asoc_simple_remove,
++};
++
++int __init sunxi_soundcard_machine_dev_init(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&sunxi_soundcard_machine_driver);
++	if (ret != 0) {
++		SND_LOG_ERR(HLOG, "platform driver register failed\n");
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
++void __exit sunxi_soundcard_machine_dev_exit(void)
++{
++	platform_driver_unregister(&sunxi_soundcard_machine_driver);
++}
++
++late_initcall(sunxi_soundcard_machine_dev_init);
++module_exit(sunxi_soundcard_machine_dev_exit);
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard machine");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach.h b/sound/soc/sunxi_v2/snd_sunxi_mach.h
+new file mode 100644
+index 000000000000..ab429c8841ab
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach.h
+@@ -0,0 +1,17 @@
++/* sound\soc\sunxi\snd_sunxi_mach.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_MACH_H
++#define __SND_SUNXI_MACH_H
++
++#include "snd_sunxi_mach_utils.h"
++
++#endif /* __SND_SUNXI_MACH_H */
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c
+new file mode 100644
+index 000000000000..15f474e5cbeb
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c
+@@ -0,0 +1,422 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_mach_utils.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * based on ${LINUX}/sound/soc/generic/simple-card.c
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <sound/soc.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_mach_utils.h"
++
++#define HLOG           "mach_utils"
++
++int asoc_simple_clean_reference(struct snd_soc_card *card)
++{
++       struct snd_soc_dai_link *dai_link;
++       int i;
++
++       for_each_card_prelinks(card, i, dai_link) {
++               of_node_put(dai_link->cpus->of_node);
++               of_node_put(dai_link->codecs->of_node);
++       }
++       return 0;
++}
++
++int asoc_simple_init_priv(struct asoc_simple_priv *priv)
++{
++       struct snd_soc_card *card = simple_priv_to_card(priv);
++       struct device *dev = simple_priv_to_dev(priv);
++       struct snd_soc_dai_link *dai_link;
++       struct simple_dai_props *dai_props;
++       struct asoc_simple_dai *dais;
++       struct snd_soc_codec_conf *cconf = NULL;
++
++       dai_props = devm_kcalloc(dev, 1, sizeof(*dai_props), GFP_KERNEL);
++       dai_link  = devm_kcalloc(dev, 1, sizeof(*dai_link),  GFP_KERNEL);
++       dais      = devm_kcalloc(dev, 1, sizeof(*dais),      GFP_KERNEL);
++       if (!dai_props || !dai_link || !dais)
++               return -ENOMEM;
++
++       /*
++       if (li->conf) {
++               cconf = devm_kcalloc(dev, li->conf, sizeof(*cconf), GFP_KERNEL);
++               if (!cconf)
++                       return -ENOMEM;
++       }
++       */
++
++       /*
++        * Use snd_soc_dai_link_component instead of legacy style
++        * It is codec only. but cpu/platform will be supported in the future.
++        * see
++        *      soc-core.c :: snd_soc_init_multicodec()
++        *
++        * "platform" might be removed
++        * see
++        *      simple-card-utils.c :: asoc_simple_canonicalize_platform()
++        */
++       dai_link->cpus          = &dai_props->cpus;
++       dai_link->num_cpus      = 1;
++       dai_link->codecs        = &dai_props->codecs;
++       dai_link->num_codecs    = 1;
++       dai_link->platforms     = &dai_props->platforms;
++       dai_link->num_platforms = 1;
++
++       priv->dai_props         = dai_props;
++       priv->dai_link          = dai_link;
++       priv->dais              = dais;
++       priv->codec_conf        = cconf;
++
++       card->dai_link          = priv->dai_link;
++       card->num_links         = 1;
++       card->codec_conf        = cconf;
++       card->num_configs       = 0;
++
++       return 0;
++}
++
++int asoc_simple_parse_widgets(struct snd_soc_card *card, char *prefix)
++{
++       struct device_node *node = card->dev->of_node;
++       char prop[128];
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%s%s", prefix, "widgets");
++
++       if (of_property_read_bool(node, prop))
++               return snd_soc_of_parse_audio_simple_widgets(card, prop);
++
++       /* no widgets is not error */
++       return 0;
++}
++
++int asoc_simple_parse_routing(struct snd_soc_card *card, char *prefix)
++{
++       struct device_node *node = card->dev->of_node;
++       char prop[128];
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%s%s", prefix, "routing");
++
++       if (!of_property_read_bool(node, prop))
++               return 0;
++
++       return snd_soc_of_parse_audio_routing(card, prop);
++}
++
++int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix)
++{
++       const unsigned int nb_controls_max = 16;
++       const char **strings, *control_name;
++       struct snd_kcontrol_new *controls;
++       struct device *dev = card->dev;
++       unsigned int i, nb_controls;
++       char prop[128];
++       int ret;
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%s%s", prefix, "pin-switches");
++
++       if (!of_property_read_bool(dev->of_node, prop))
++               return 0;
++
++       strings = devm_kcalloc(dev, nb_controls_max,
++                              sizeof(*strings), GFP_KERNEL);
++       if (!strings)
++               return -ENOMEM;
++
++       ret = of_property_read_string_array(dev->of_node, prop,
++                                           strings, nb_controls_max);
++       if (ret < 0)
++               return ret;
++
++       nb_controls = (unsigned int)ret;
++
++       controls = devm_kcalloc(dev, nb_controls,
++                               sizeof(*controls), GFP_KERNEL);
++       if (!controls)
++               return -ENOMEM;
++
++       for (i = 0; i < nb_controls; i++) {
++               control_name = devm_kasprintf(dev, GFP_KERNEL,
++                                             "%s Switch", strings[i]);
++               if (!control_name)
++                       return -ENOMEM;
++
++               controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
++               controls[i].name = control_name;
++               controls[i].info = snd_soc_dapm_info_pin_switch;
++               controls[i].get = snd_soc_dapm_get_pin_switch;
++               controls[i].put = snd_soc_dapm_put_pin_switch;
++               controls[i].private_value = (unsigned long)strings[i];
++       }
++
++       card->controls = controls;
++       card->num_controls = nb_controls;
++
++       return 0;
++}
++
++int asoc_simple_parse_daifmt(struct device_node *node,
++                            struct device_node *codec,
++                            char *prefix,
++                            unsigned int *retfmt)
++{
++       struct device_node *bitclkmaster = NULL;
++       struct device_node *framemaster = NULL;
++       unsigned int daifmt;
++
++       daifmt = snd_soc_daifmt_parse_format(node, prefix);
++
++       snd_soc_daifmt_parse_clock_provider_as_phandle(node, prefix, &bitclkmaster, &framemaster);
++       if (!bitclkmaster && !framemaster) {
++               /*
++                * No dai-link level and master setting was not found from
++                * sound node level, revert back to legacy DT parsing and
++                * take the settings from codec node.
++                */
++               SND_LOG_DEBUG(HLOG, "Revert to legacy daifmt parsing\n");
++
++               daifmt |= snd_soc_daifmt_parse_clock_provider_as_flag(codec, NULL);
++       } else {
++               daifmt |= snd_soc_daifmt_clock_provider_from_bitmap(
++                       ((codec == bitclkmaster) << 4) | (codec == framemaster));
++       }
++
++       of_node_put(bitclkmaster);
++       of_node_put(framemaster);
++
++       *retfmt = daifmt;
++
++       return 0;
++}
++
++int asoc_simple_parse_daistream(struct device_node *node, char *prefix,
++                               struct snd_soc_dai_link *dai_link)
++{
++       char prop[128];
++
++       if (!prefix)
++               prefix = "";
++
++       /* check "[prefix]playback-only" */
++       snprintf(prop, sizeof(prop), "%splayback-only", prefix);
++       if (of_property_read_bool(node, prop))
++               dai_link->playback_only = 1;
++
++       /* check "[prefix]capture-only" */
++       snprintf(prop, sizeof(prop), "%scapture-only", prefix);
++       if (of_property_read_bool(node, prop))
++               dai_link->capture_only = 1;
++
++       return 0;
++}
++
++int asoc_simple_parse_tdm_slot(struct device_node *node, char *prefix,
++                              struct asoc_simple_dai *dais)
++{
++       int ret;
++       char prop[128];
++       unsigned int val;
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%sslot-num", prefix);
++       ret = of_property_read_u32(node, prop, &val);
++       if (!ret)
++               dais->slots = val;
++
++       snprintf(prop, sizeof(prop), "%sslot-width", prefix);
++       ret = of_property_read_u32(node, prop, &val);
++       if (!ret)
++               dais->slot_width = val;
++
++       return 0;
++}
++
++int asoc_simple_parse_tdm_clk(struct device_node *cpu,
++                             struct device_node *codec,
++                             char *prefix,
++                             struct simple_dai_props *dai_props)
++{
++       int ret;
++       char prop[128];
++       unsigned int val;
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%spll-fs", prefix);
++       ret = of_property_read_u32(cpu, prop, &val);
++       if (ret)
++               dai_props->cpu_pll_fs = 1;      /* default sysclk 24.576 or 22.5792MHz * 1 */
++       else
++               dai_props->cpu_pll_fs = val;
++
++       ret = of_property_read_u32(codec, prop, &val);
++       if (ret)
++               dai_props->codec_pll_fs = 1;    /* default sysclk 24.576 or 22.5792MHz * 1 */
++       else
++               dai_props->codec_pll_fs = val;
++
++       snprintf(prop, sizeof(prop), "%smclk-fp", prefix);
++       dai_props->mclk_fp = of_property_read_bool(cpu, prop);
++
++       snprintf(prop, sizeof(prop), "%smclk-fs", prefix);
++       ret = of_property_read_u32(cpu, prop, &val);
++       if (ret)
++               dai_props->mclk_fs = 0;         /* default mclk 0Hz(un output) */
++       else
++               dai_props->mclk_fs = val;
++
++       return 0;
++}
++
++int asoc_simple_parse_card_name(struct snd_soc_card *card,
++                               char *prefix)
++{
++       int ret;
++
++       if (!prefix)
++               prefix = "";
++
++       /* Parse the card name from DT */
++       ret = snd_soc_of_parse_card_name(card, "label");
++       if (ret < 0 || !card->name) {
++               char prop[128];
++
++               snprintf(prop, sizeof(prop), "%sname", prefix);
++               ret = snd_soc_of_parse_card_name(card, prop);
++               if (ret < 0)
++                       return ret;
++       }
++
++       if (!card->name && card->dai_link)
++               card->name = card->dai_link->name;
++
++       return 0;
++}
++
++int asoc_simple_parse_dai(struct device_node *node,
++                         struct snd_soc_dai_link_component *dlc,
++                         const char *list_name, const char *cells_name,
++                         int *is_single_link)
++{
++       struct of_phandle_args args;
++       int ret;
++
++       if (!node)
++               return 0;
++
++       /*
++        * Get node via "sound-dai = <&phandle port>"
++        * it will be used as xxx_of_node on soc_bind_dai_link()
++        */
++       ret = of_parse_phandle_with_args(node, list_name, cells_name, 0, &args);
++       if (ret)
++               return ret;
++
++       /*
++        * FIXME
++        *
++        * Here, dlc->dai_name is pointer to CPU/Codec DAI name.
++        * If user unbinded CPU or Codec driver, but not for Sound Card,
++        * dlc->dai_name is keeping unbinded CPU or Codec
++        * driver's pointer.
++        *
++        * If user re-bind CPU or Codec driver again, ALSA SoC will try
++        * to rebind Card via snd_soc_try_rebind_card(), but because of
++        * above reason, it might can't bind Sound Card.
++        * Because Sound Card is pointing to released dai_name pointer.
++        *
++        * To avoid this rebind Card issue,
++        * 1) It needs to alloc memory to keep dai_name eventhough
++        *    CPU or Codec driver was unbinded, or
++        * 2) user need to rebind Sound Card everytime
++        *    if he unbinded CPU or Codec.
++        */
++       ret = snd_soc_of_get_dai_name(node, &dlc->dai_name, 0);
++       if (ret < 0)
++               return ret;
++
++       dlc->of_node = args.np;
++
++       if (is_single_link)
++               *is_single_link = !args.args_count;
++
++       return 0;
++}
++
++int asoc_simple_set_dailink_name(struct device *dev,
++                                struct snd_soc_dai_link *dai_link,
++                                const char *fmt, ...)
++{
++       va_list ap;
++       char *name = NULL;
++       int ret = -ENOMEM;
++
++       va_start(ap, fmt);
++       name = devm_kvasprintf(dev, GFP_KERNEL, fmt, ap);
++       va_end(ap);
++
++       if (name) {
++               ret = 0;
++
++               dai_link->name          = name;
++               dai_link->stream_name   = name;
++       }
++
++       return ret;
++}
++
++void asoc_simple_canonicalize_platform(struct snd_soc_dai_link *dai_link)
++{
++       /* Assumes platform == cpu */
++       if (!dai_link->platforms->of_node)
++               dai_link->platforms->of_node = dai_link->cpus->of_node;
++
++       /*
++        * DPCM BE can be no platform.
++        * Alloced memory will be waste, but not leak.
++        */
++       if (!dai_link->platforms->of_node)
++               dai_link->num_platforms = 0;
++}
++
++void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link *dai_link,
++                                 int is_single_links)
++{
++       /*
++        * In soc_bind_dai_link() will check cpu name after
++        * of_node matching if dai_link has cpu_dai_name.
++        * but, it will never match if name was created by
++        * fmt_single_name() remove cpu_dai_name if cpu_args
++        * was 0. See:
++        *      fmt_single_name()
++        *      fmt_multiple_name()
++        */
++       if (is_single_links)
++               dai_link->cpus->dai_name = NULL;
++}
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard machine utils");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h
+new file mode 100644
+index 000000000000..a9cffa0d859b
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h
+@@ -0,0 +1,116 @@
++/* sound\soc\sunxi\snd_sunxi_mach_utils.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_MACH_UTILS_H
++#define __SND_SUNXI_MACH_UTILS_H
++
++#define simple_priv_to_card(priv)      (&(priv)->snd_card)
++#define simple_priv_to_props(priv, i)  ((priv)->dai_props + (i))
++#define simple_priv_to_dev(priv)       (simple_priv_to_card(priv)->dev)
++#define simple_priv_to_link(priv, i)   (simple_priv_to_card(priv)->dai_link + (i))
++
++#define asoc_simple_parse_cpu(node, dai_link,                          \
++                             list_name, cells_name, is_single_link)    \
++       asoc_simple_parse_dai(node, dai_link->cpus,                     \
++                             list_name, cells_name, is_single_link)
++
++#define asoc_simple_parse_codec(node, dai_link,                                \
++                               list_name, cells_name)                  \
++       asoc_simple_parse_dai(node, dai_link->codecs,                   \
++                             list_name, cells_name, NULL)
++
++#define asoc_simple_parse_platform(node, dai_link,                     \
++                                  list_name, cells_name)               \
++       asoc_simple_parse_dai(node, dai_link->platforms,                \
++                             list_name, cells_name, NULL)
++
++struct asoc_simple_dai {
++       const char *name;
++       unsigned int sysclk;
++       int clk_direction;
++       int slots;
++       int slot_width;
++       unsigned int tx_slot_mask;
++       unsigned int rx_slot_mask;
++       struct clk *clk;
++};
++
++struct asoc_simple_data {
++       u32 convert_rate;
++       u32 convert_channels;
++};
++
++struct asoc_simple_jack {
++       struct snd_soc_jack jack;
++       struct snd_soc_jack_pin pin;
++       struct snd_soc_jack_gpio gpio;
++};
++
++struct asoc_simple_priv {
++       struct snd_soc_card snd_card;
++       struct simple_dai_props {
++               struct asoc_simple_dai *cpu_dai;
++               struct asoc_simple_dai *codec_dai;
++               struct snd_soc_dai_link_component cpus;   /* single cpu */
++               struct snd_soc_dai_link_component codecs; /* single codec */
++               struct snd_soc_dai_link_component platforms;
++               struct asoc_simple_data adata;
++               struct snd_soc_codec_conf *codec_conf;
++               bool mclk_fp;
++               unsigned int mclk_fs;
++               unsigned int cpu_pll_fs;
++               unsigned int codec_pll_fs;
++       } *dai_props;
++       struct asoc_simple_jack hp_jack;
++       struct asoc_simple_jack mic_jack;
++       struct snd_soc_dai_link *dai_link;
++       struct asoc_simple_dai *dais;
++       struct snd_soc_codec_conf *codec_conf;
++       struct gpio_desc *pa_gpio;
++};
++
++int asoc_simple_clean_reference(struct snd_soc_card *card);
++int asoc_simple_init_priv(struct asoc_simple_priv *priv);
++
++int asoc_simple_parse_widgets(struct snd_soc_card *card, char *prefix);
++int asoc_simple_parse_routing(struct snd_soc_card *card, char *prefix);
++int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix);
++
++int asoc_simple_parse_daistream(struct device_node *node,
++                               char *prefix,
++                               struct snd_soc_dai_link *dai_link);
++int asoc_simple_parse_daifmt(struct device_node *node,
++                            struct device_node *codec,
++                            char *prefix,
++                            unsigned int *retfmt);
++int asoc_simple_parse_tdm_slot(struct device_node *node,
++                              char *prefix,
++                              struct asoc_simple_dai *dais);
++int asoc_simple_parse_tdm_clk(struct device_node *cpu,
++                             struct device_node *codec,
++                             char *prefix,
++                             struct simple_dai_props *dai_props);
++
++int asoc_simple_parse_card_name(struct snd_soc_card *card, char *prefix);
++int asoc_simple_parse_dai(struct device_node *node,
++                         struct snd_soc_dai_link_component *dlc,
++                         const char *list_name,
++                         const char *cells_name,
++                         int *is_single_link);
++
++int asoc_simple_set_dailink_name(struct device *dev,
++                                struct snd_soc_dai_link *dai_link,
++                                const char *fmt, ...);
++void asoc_simple_canonicalize_platform(struct snd_soc_dai_link *dai_link);
++void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link *dai_link,
++                                 int is_single_links);
++
++#endif /* __SND_SUNXI_MACH_UTILS_H */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/add-bigtreetech-cb1-dts.patch b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/add-bigtreetech-cb1-dts.patch
new file mode 100644
index 000000000000..a9a7840807fa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/add-bigtreetech-cb1-dts.patch
@@ -0,0 +1,455 @@
+From bbd85618d5e4ba7921e3ac2b648a137d48004022 Mon Sep 17 00:00:00 2001
+From: Your Name <you@example.com>
+Date: Tue, 30 May 2023 10:18:55 +0800
+Subject: add bigtreetech-cb1 dts
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   2 +
+ .../sun50i-h616-bigtreetech-cb1-emmc.dts      |  44 +++
+ .../sun50i-h616-bigtreetech-cb1-sd.dts        |  35 ++
+ .../sun50i-h616-bigtreetech-cb1.dtsi          | 327 ++++++++++++++++++
+ 4 files changed, 408 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 4d4d2e5c01f2..74a6e5e0d7b3 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -50,6 +50,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
+ 
+ subdir-y	:= $(dts-dirs) overlay
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+new file mode 100644
+index 000000000000..f878c23f1d90
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+@@ -0,0 +1,44 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Copyright (C) 2023 Alan.Ma <tech@biqu3d.com>.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616-bigtreetech-cb1.dtsi"
++
++&mmc2 {
++	vmmc-supply = <&reg_dldo1>;
++
++	no-1-8-v;
++	bus-width = <8>;
++	non-removable;
++	status = "okay";
++};
++
++&ws2812 {
++	gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
++};
++
++&i2c_gpio {
++	gpios = <&pio 8 6 GPIO_ACTIVE_HIGH>, /* SDA PI6 */
++			<&pio 8 4 GPIO_ACTIVE_HIGH>; /* SCL PI4 */
++};
++
++&can0_pin_irq {
++	pins = "PI3";
++};
++
++&can {
++	interrupts = <8 3 0x08>; /* PI3 IRQ_TYPE_LEVEL_LOW */
++};
++
++&tft_35 {
++	dc-gpios  = <&pio 8 15 GPIO_ACTIVE_HIGH>; /* PI15 */
++};
++
++&spi1 {
++	cs-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>, /* PI5 */
++			   <&pio 8 14 GPIO_ACTIVE_HIGH>, /* PI14 */
++			   <&pio 8 7 GPIO_ACTIVE_HIGH>; /* PI7 */
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+new file mode 100644
+index 000000000000..e18dd854d74b
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+@@ -0,0 +1,35 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Copyright (C) 2023 Alan.Ma <tech@biqu3d.com>.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616-bigtreetech-cb1.dtsi"
++
++&ws2812 {
++	gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */
++};
++
++&i2c_gpio {
++	gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>, /* SDA PC12 */
++			<&pio 2 10 GPIO_ACTIVE_HIGH>; /* SCL PC10 */
++};
++
++&can0_pin_irq {
++	pins = "PC9";
++};
++
++&can {
++	interrupts = <2 9 0x08>; /* PC9 IRQ_TYPE_LEVEL_LOW */
++};
++
++&tft_35 {
++	dc-gpios  = <&pio 2 14 GPIO_ACTIVE_HIGH>; /* PC14 */
++};
++
++&spi1 {
++	cs-gpios = <&pio 2 11 GPIO_ACTIVE_HIGH>, /* PC11 */
++			   <&pio 2 7 GPIO_ACTIVE_HIGH>, /* PC7 */
++			   <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+new file mode 100644
+index 000000000000..e82da4b6e340
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+@@ -0,0 +1,327 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Copyright (C) 2023 Alan.Ma <tech@biqu3d.com>.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "BigTreeTech CB1";
++	compatible = "bigtreetech,cb1", "allwinner,sun50i-h616";
++
++	aliases {
++		ethernet0 = &emac1;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		act_led: led-0 {
++			gpios = <&pio 7 5 GPIO_ACTIVE_LOW>; /* PH5 */
++			linux,default-trigger = "heartbeat";
++		};
++
++		gpio_1 {
++			function = "wifi_power";
++			gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++			default-state = "on";
++		};
++
++		gpio_2 {
++			function = "wifi_wake";
++			gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
++			default-state = "on";
++		};
++	};
++
++	reg_vcc5v: regulator-vcc5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_usb1_vbus: regulator-usb1-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb1-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&reg_vcc5v>;
++		enable-active-high;
++	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc5v>;
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>;  /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
++
++	ws2812: ws2812 {
++		compatible = "rgb-ws2812";
++		pinctrl-names = "default";
++		rgb_cnt = <2>;
++		rgb_value = <0x010000 0x010000>;
++		status = "disabled";
++	};
++
++	i2c_gpio: i2c-gpio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++
++		i2c-gpio,delay-us = <3>; /* 100 kHz */
++
++		tft_tp: ns2009@48 {
++			compatible = "ti,tsc2007";
++			reg = <0x48>;
++			status = "disabled";
++			ti,x-plate-ohms = <660>;
++			ti,rt-thr = <3000>;
++			ti,fuzzx = <32>;
++			ti,fuzzy = <16>;
++			i2c,ignore-nak = <1>;
++		};
++
++		light: bh1750@5c {
++			compatible = "rohm,bh1750";
++			reg = <0x5c>;
++			status = "disabled";
++		};
++	};
++
++	mcp2515_clock: mcp2515_clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency  = <12000000>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_dldo1>;
++	broken-cd;
++	bus-width = <4>;
++	max-frequency = <50000000>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	max-frequency = <25000000>;
++	non-removable;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
++&pio {
++	can0_pin_irq: can0_pin_irq {
++		function = "irq";
++		bias-pull-up;
++	};
++};
++
++&spi1 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	status = "disabled";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins>;
++
++	can: mcp2515@0 {
++		status = "disabled";
++		compatible = "microchip,mcp2515";
++		reg = <0x0>;
++		clocks = <&mcp2515_clock>;
++		spi-max-frequency = <12500000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&can0_pin_irq>;
++		interrupt-parent = <&pio>;
++		vdd-supply = <&reg_vcc33_wifi>;
++		xceiver-supply = <&reg_vcc33_wifi>;
++	};
++
++	tft_35: st7789v@1 {
++		status = "disabled";
++		compatible = "sitronix,st7796s";
++		reg = <1>;
++		spi-max-frequency =<12500000>;
++		fps =<60>;
++		buswidth = <8>;
++		rotate =<0>;
++		width = <480>;
++		height = <320>;
++		bpp = <24>;
++		bgr;
++		regwidth = <8>;
++		debug = <0x00>;	 //0x20 show fps
++		txbuflen = <307200>;
++		spi-cpol;
++		spi-cpha;
++	};
++};
++
++&r_i2c {
++	status = "okay";
++
++	axp313a: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		wakeup-source;
++
++		regulators{
++			reg_dcdc1: dcdc1 {
++				regulator-name = "axp313a-dcdc1";
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <3400000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-name = "axp313a-dcdc2";
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1540000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-ramp-delay = <200>;
++				regulator-always-on;
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-name = "axp313a-dcdc3";
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1840000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_aldo1: aldo1 {
++				regulator-name = "axp313a-aldo1";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_dldo1: dldo1 {
++				regulator-name = "axp313a-dldo1";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++		};
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc3>;
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_usb1_vbus>;
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&usbotg {
++	/*
++	 * PHY0 pins are connected to a USB-C socket, but a role switch
++	 * is not implemented: both CC pins are pulled to GND.
++	 * The VBUS pins power the device, so a fixed peripheral mode
++	 * is the best choice.
++	 * The board can be powered via GPIOs, in this case port0 *can*
++	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
++	 * then provided by the GPIOs. Any user of this setup would
++	 * need to adjust the DT accordingly: dr_mode set to "host",
++	 * enabling OHCI0 and EHCI0.
++	 */
++	dr_mode = "peripheral";
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/add-dtb-overlay-for-zero2w.patch b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/add-dtb-overlay-for-zero2w.patch
new file mode 100644
index 000000000000..29a9d3c35d43
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/add-dtb-overlay-for-zero2w.patch
@@ -0,0 +1,215 @@
+From ee00f965c88e0a4a5f158b6eafb5fe2e5ce12c71 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Fri, 5 Apr 2024 10:57:18 +0800
+Subject: add dtb overlay for zero2w
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile | 16 ++++++++-----
+ .../allwinner/overlay/sun50i-h616-gpu.dtso    | 14 +++++++++++
+ .../overlay/sun50i-h616-i2c0-pi.dtso          | 23 +++++++++++++++++++
+ .../overlay/sun50i-h616-i2c1-pi.dtso          | 16 +++++++++++++
+ ...616-i2c2.dtso => sun50i-h616-i2c2-ph.dtso} |  0
+ .../overlay/sun50i-h616-i2c2-pi.dtso          | 23 +++++++++++++++++++
+ ...616-i2c3.dtso => sun50i-h616-i2c3-ph.dtso} |  0
+ ...616-i2c4.dtso => sun50i-h616-i2c4-ph.dtso} |  0
+ ...6-uart2.dtso => sun50i-h616-uart2-ph.dtso} |  0
+ ...6-uart5.dtso => sun50i-h616-uart5-ph.dtso} |  0
+ .../allwinner/sun50i-h618-orangepi-zero2w.dts | 12 ----------
+ 11 files changed, 86 insertions(+), 18 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso
+ rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-i2c2.dtso => sun50i-h616-i2c2-ph.dtso} (100%)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso
+ rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-i2c3.dtso => sun50i-h616-i2c3-ph.dtso} (100%)
+ rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-i2c4.dtso => sun50i-h616-i2c4-ph.dtso} (100%)
+ rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-uart2.dtso => sun50i-h616-uart2-ph.dtso} (100%)
+ rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-uart5.dtso => sun50i-h616-uart5-ph.dtso} (100%)
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 369b2976b1bb..24383cb63770 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -49,11 +49,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-uart2.dtbo \
+ 	sun50i-h6-uart3.dtbo \
+ 	sun50i-h6-w1-gpio.dtbo \
+-	sun50i-h616-i2c2.dtbo \
+-	sun50i-h616-i2c3.dtbo \
+-	sun50i-h616-i2c4.dtbo \
+-	sun50i-h616-uart2.dtbo \
+-	sun50i-h616-uart5.dtbo \
++	sun50i-h616-i2c2-ph.dtbo \
++	sun50i-h616-i2c3-ph.dtbo \
++	sun50i-h616-i2c4-ph.dtbo \
++	sun50i-h616-uart2-ph.dtbo \
++	sun50i-h616-uart5-ph.dtbo \
+ 	sun50i-h616-spi-spidev.dtbo \
+ 	sun50i-h616-spidev0_0.dtbo \
+ 	sun50i-h616-spidev1_0.dtbo \
+@@ -63,7 +63,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h616-tft35_spi.dtbo \
+ 	sun50i-h616-mcp2515.dtbo \
+ 	sun50i-h616-ws2812.dtbo \
+-	sun50i-h616-light.dtbo
++	sun50i-h616-light.dtbo \
++	sun50i-h616-i2c0-pi.dtbo \
++	sun50i-h616-i2c1-pi.dtbo \
++	sun50i-h616-i2c2-pi.dtbo \
++	sun50i-h616-gpu.dtbo
+ 
+ scr-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-a64-fixup.scr \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso
+new file mode 100644
+index 000000000000..ac8846ac7d27
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso
+@@ -0,0 +1,14 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&gpu>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso
+new file mode 100644
+index 000000000000..b5003934c895
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c0_pi_pins>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart2>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso
+new file mode 100644
+index 000000000000..05f3100967ff
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso
+@@ -0,0 +1,16 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pi_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso
+similarity index 100%
+rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso
+rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso
+new file mode 100644
+index 000000000000..0f7d7e9968d6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_pi_pins>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart3>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso
+similarity index 100%
+rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso
+rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso
+similarity index 100%
+rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso
+rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso
+similarity index 100%
+rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso
+rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5-ph.dtso
+similarity index 100%
+rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5-ph.dtso
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+index b224902f5684..2a4c152b9294 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+@@ -312,12 +312,6 @@ &uart4 {
+ 	status = "disabled";
+ };
+ 
+-&uart5 {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&uart5_ph_pins>;
+-	status = "disabled";
+-};
+-
+ &i2c3 {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+@@ -447,12 +441,6 @@ uart4_pi_pins: uart4-pi-pins {
+ 		function = "uart4";
+ 	};
+ 
+-	/omit-if-no-ref/
+-	uart5_ph_pins: uart5-ph-pins {
+-		pins = "PH2", "PH3";
+-		function = "uart5";
+-	};
+-
+ 	/omit-if-no-ref/
+ 	spi1_cs1_pin: spi1-cs1-pin {
+ 		pins = "PH9";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/drivers-hack-for-h616-hdmi-video-output.patch b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/drivers-hack-for-h616-hdmi-video-output.patch
new file mode 100644
index 000000000000..1cb01222aff2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/drivers-hack-for-h616-hdmi-video-output.patch
@@ -0,0 +1,978 @@
+From 35fe095a767a286b6f33757e8606d1d79cd8d2cc Mon Sep 17 00:00:00 2001
+From: orangepi-xunlong <258384131@qq.com>
+Date: Mon, 5 Jun 2023 14:16:04 +0800
+Subject: drivers: hack for h616 hdmi video output
+
+---
+ drivers/clk/sunxi-ng/Kconfig            |   4 +
+ drivers/clk/sunxi-ng/Makefile           |   2 +
+ drivers/clk/sunxi-ng/ccu-sun8i-de33.c   | 181 +++++++++++++++++++++
+ drivers/clk/sunxi-ng/ccu-sun8i-de33.h   |  19 +++
+ drivers/gpu/drm/sun4i/sun4i_tcon.c      |   4 +
+ drivers/gpu/drm/sun4i/sun4i_tcon.h      |   1 +
+ drivers/gpu/drm/sun4i/sun8i_csc.c       |  51 +++++-
+ drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c  |  81 ++++++++++
+ drivers/gpu/drm/sun4i/sun8i_mixer.c     | 200 +++++++++++++++++++-----
+ drivers/gpu/drm/sun4i/sun8i_mixer.h     |  22 ++-
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c  |  22 ++-
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c  |   6 +-
+ drivers/gpu/drm/sun4i/sun8i_vi_scaler.c |   4 +-
+ 13 files changed, 547 insertions(+), 50 deletions(-)
+ create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-de33.c
+ create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-de33.h
+
+diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
+index b547198a2c65..01d2f8c4d73e 100644
+--- a/drivers/clk/sunxi-ng/Kconfig
++++ b/drivers/clk/sunxi-ng/Kconfig
+@@ -103,6 +103,10 @@ config SUN8I_DE2_CCU
+ 	default y
+ 	depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST
+ 
++config SUN8I_DE33_CCU
++	tristate "Support for the Allwinner SoCs DE3.3 CCU"
++	default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
++
+ config SUN8I_R40_CCU
+ 	tristate "Support for the Allwinner R40 CCU"
+ 	default y
+diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
+index 6b3ae2b620db..cd20050cd9f1 100644
+--- a/drivers/clk/sunxi-ng/Makefile
++++ b/drivers/clk/sunxi-ng/Makefile
+@@ -44,6 +44,7 @@ obj-$(CONFIG_SUN8I_H3_CCU)	+= sun8i-h3-ccu.o
+ obj-$(CONFIG_SUN8I_R40_CCU)	+= sun8i-r40-ccu.o
+ obj-$(CONFIG_SUN8I_V3S_CCU)	+= sun8i-v3s-ccu.o
+ obj-$(CONFIG_SUN8I_DE2_CCU)	+= sun8i-de2-ccu.o
++obj-$(CONFIG_SUN8I_DE33_CCU)	+= sun8i-de33-ccu.o
+ obj-$(CONFIG_SUN8I_R_CCU)	+= sun8i-r-ccu.o
+ obj-$(CONFIG_SUN9I_A80_CCU)	+= sun9i-a80-ccu.o
+ obj-$(CONFIG_SUN9I_A80_CCU)	+= sun9i-a80-de-ccu.o
+@@ -69,6 +70,7 @@ sun8i-h3-ccu-y			+= ccu-sun8i-h3.o
+ sun8i-r40-ccu-y			+= ccu-sun8i-r40.o
+ sun8i-v3s-ccu-y			+= ccu-sun8i-v3s.o
+ sun8i-de2-ccu-y			+= ccu-sun8i-de2.o
++sun8i-de33-ccu-y		+= ccu-sun8i-de33.o
+ sun8i-r-ccu-y			+= ccu-sun8i-r.o
+ sun9i-a80-ccu-y			+= ccu-sun9i-a80.o
+ sun9i-a80-de-ccu-y		+= ccu-sun9i-a80-de.o
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de33.c b/drivers/clk/sunxi-ng/ccu-sun8i-de33.c
+new file mode 100644
+index 000000000000..fa5b1cf62444
+--- /dev/null
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-de33.c
+@@ -0,0 +1,181 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/of_address.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++
++#include "ccu_common.h"
++#include "ccu_div.h"
++#include "ccu_gate.h"
++#include "ccu_reset.h"
++
++#include "ccu-sun8i-de33.h"
++
++static SUNXI_CCU_GATE(bus_mixer0_clk,	"bus-mixer0",	"bus-de",
++		      0x04, BIT(0), 0);
++static SUNXI_CCU_GATE(bus_mixer1_clk,	"bus-mixer1",	"bus-de",
++		      0x04, BIT(1), 0);
++static SUNXI_CCU_GATE(bus_wb_clk,	"bus-wb",	"bus-de",
++		      0x04, BIT(2), 0);
++
++static SUNXI_CCU_GATE(mixer0_clk,	"mixer0",	"mixer0-div",
++		      0x00, BIT(0), CLK_SET_RATE_PARENT);
++static SUNXI_CCU_GATE(mixer1_clk,	"mixer1",	"mixer1-div",
++		      0x00, BIT(1), CLK_SET_RATE_PARENT);
++static SUNXI_CCU_GATE(wb_clk,		"wb",		"wb-div",
++		      0x00, BIT(2), CLK_SET_RATE_PARENT);
++
++static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
++		   CLK_SET_RATE_PARENT);
++static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
++		   CLK_SET_RATE_PARENT);
++static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
++		   CLK_SET_RATE_PARENT);
++
++static struct ccu_common *sun50i_h616_de33_clks[] = {
++	&mixer0_clk.common,
++	&mixer1_clk.common,
++	&wb_clk.common,
++
++	&bus_mixer0_clk.common,
++	&bus_mixer1_clk.common,
++	&bus_wb_clk.common,
++
++	&mixer0_div_clk.common,
++	&mixer1_div_clk.common,
++	&wb_div_clk.common,
++};
++
++static struct clk_hw_onecell_data sun50i_h616_de33_hw_clks = {
++	.hws	= {
++		[CLK_MIXER0]		= &mixer0_clk.common.hw,
++		[CLK_MIXER1]		= &mixer1_clk.common.hw,
++		[CLK_WB]		= &wb_clk.common.hw,
++
++		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
++		[CLK_BUS_MIXER1]	= &bus_mixer1_clk.common.hw,
++		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,
++
++		[CLK_MIXER0_DIV]	= &mixer0_div_clk.common.hw,
++		[CLK_MIXER1_DIV]	= &mixer1_div_clk.common.hw,
++		[CLK_WB_DIV]		= &wb_div_clk.common.hw,
++	},
++	.num	= CLK_NUMBER,
++};
++
++static struct ccu_reset_map sun50i_h616_de33_resets[] = {
++	[RST_MIXER0]	= { 0x08, BIT(0) },
++	[RST_MIXER1]	= { 0x08, BIT(1) },
++	[RST_WB]	= { 0x08, BIT(2) },
++};
++
++static const struct sunxi_ccu_desc sun50i_h616_de33_clk_desc = {
++	.ccu_clks	= sun50i_h616_de33_clks,
++	.num_ccu_clks	= ARRAY_SIZE(sun50i_h616_de33_clks),
++
++	.hw_clks	= &sun50i_h616_de33_hw_clks,
++
++	.resets		= sun50i_h616_de33_resets,
++	.num_resets	= ARRAY_SIZE(sun50i_h616_de33_resets),
++};
++
++static int sunxi_de33_clk_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	struct clk *bus_clk, *mod_clk;
++	struct reset_control *rstc;
++	void __iomem *reg;
++	const struct sunxi_ccu_desc *ccu_desc;
++	int ret;
++
++	ccu_desc = of_device_get_match_data(&pdev->dev);
++	if (!ccu_desc)
++		return -EINVAL;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	reg = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(reg))
++		return PTR_ERR(reg);
++
++	bus_clk = devm_clk_get(&pdev->dev, "bus");
++	if (IS_ERR(bus_clk)) {
++		ret = PTR_ERR(bus_clk);
++		if (ret != -EPROBE_DEFER)
++			dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
++		return ret;
++	}
++
++	mod_clk = devm_clk_get(&pdev->dev, "mod");
++	if (IS_ERR(mod_clk)) {
++		ret = PTR_ERR(mod_clk);
++		if (ret != -EPROBE_DEFER)
++			dev_err(&pdev->dev, "Couldn't get mod clk: %d\n", ret);
++		return ret;
++	}
++
++	rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
++	if (IS_ERR(rstc)) {
++		ret = PTR_ERR(rstc);
++		if (ret != -EPROBE_DEFER)
++			dev_err(&pdev->dev,
++				"Couldn't get reset control: %d\n", ret);
++		return ret;
++	}
++
++	/* The clocks need to be enabled for us to access the registers */
++	ret = clk_prepare_enable(bus_clk);
++	if (ret) {
++		dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(mod_clk);
++	if (ret) {
++		dev_err(&pdev->dev, "Couldn't enable mod clk: %d\n", ret);
++		goto err_disable_bus_clk;
++	}
++
++	/* The reset control needs to be asserted for the controls to work */
++	ret = reset_control_deassert(rstc);
++	if (ret) {
++		dev_err(&pdev->dev,
++			"Couldn't deassert reset control: %d\n", ret);
++		goto err_disable_mod_clk;
++	}
++
++	writel(0, reg + 0x24);
++	writel(0x0000A980, reg + 0x28);
++
++	of_sunxi_ccu_probe(pdev->dev.of_node, reg, ccu_desc);
++
++	return 0;
++
++err_disable_mod_clk:
++	clk_disable_unprepare(mod_clk);
++err_disable_bus_clk:
++	clk_disable_unprepare(bus_clk);
++	return ret;
++}
++
++static const struct of_device_id sunxi_de33_clk_ids[] = {
++	{
++		.compatible = "allwinner,sun50i-h616-de33-clk",
++		.data = &sun50i_h616_de33_clk_desc,
++	},
++	{ }
++};
++
++static struct platform_driver sunxi_de33_clk_driver = {
++	.probe	= sunxi_de33_clk_probe,
++	.driver	= {
++		.name	= "sunxi-de33-clks",
++		.of_match_table	= sunxi_de33_clk_ids,
++	},
++};
++builtin_platform_driver(sunxi_de33_clk_driver);
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de33.h b/drivers/clk/sunxi-ng/ccu-sun8i-de33.h
+new file mode 100644
+index 000000000000..83cbef5a3f76
+--- /dev/null
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-de33.h
+@@ -0,0 +1,19 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++/*
++ * Copyright 2016 Icenowy Zheng <icenowy@aosc.io>
++ */
++
++#ifndef _CCU_SUN8I_DE2_H_
++#define _CCU_SUN8I_DE2_H_
++
++#include <dt-bindings/clock/sun8i-de2.h>
++#include <dt-bindings/reset/sun8i-de2.h>
++
++/* Intermediary clock dividers are not exported */
++#define CLK_MIXER0_DIV	3
++#define CLK_MIXER1_DIV	4
++#define CLK_WB_DIV	5
++
++#define CLK_NUMBER	(CLK_WB + 1)
++
++#endif /* _CCU_SUN8I_DE2_H_ */
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index 19875219fe3d..a005dcaaf788 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -1313,6 +1313,10 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 			goto err_free_dclk;
+ 	}
+ 
++	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
++			   SUN4I_TCON_GCTL_PAD_SEL,
++			   SUN4I_TCON_GCTL_PAD_SEL);
++
+ 	if (tcon->quirks->needs_de_be_mux) {
+ 		/*
+ 		 * We assume there is no dynamic muxing of backends
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index 7ba3df9e27df..e8687a696d2a 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -20,6 +20,7 @@
+ #define SUN4I_TCON_GCTL_REG			0x0
+ #define SUN4I_TCON_GCTL_TCON_ENABLE			BIT(31)
+ #define SUN4I_TCON_GCTL_GAMMA_ENABLE			BIT(30)
++#define SUN4I_TCON_GCTL_PAD_SEL BIT			(1)
+ #define SUN4I_TCON_GCTL_IOMAP_MASK			BIT(0)
+ #define SUN4I_TCON_GCTL_IOMAP_TCON1			(1 << 0)
+ #define SUN4I_TCON_GCTL_IOMAP_TCON0			(0 << 0)
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index 58480d8e4f70..703c55ba788b 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -107,6 +107,14 @@ static const u32 yuv2rgb_de3[2][3][12] = {
+ 	},
+ };
+ 
++static u32 sun8i_csc_base(struct sun8i_mixer *mixer, int layer)
++{
++	if (mixer->cfg->is_de33)
++		return sun8i_channel_base(mixer, layer) - 0x200;
++	else
++		return ccsc_base[mixer->cfg->ccsc][layer];
++}
++
+ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+ 				       enum sun8i_csc_mode mode,
+ 				       enum drm_color_encoding encoding,
+@@ -178,6 +186,41 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
+ 	}
+ }
+ 
++static void sun8i_de33_ccsc_set_coefficients(struct sun8i_mixer *mixer,
++					     int layer,
++					     enum sun8i_csc_mode mode,
++					     enum drm_color_encoding encoding,
++					     enum drm_color_range range)
++{
++	const u32 *table;
++	u32 base, addr;
++	int i;
++
++	base = sun8i_csc_base(mixer, layer);
++	table = yuv2rgb_de3[range][encoding];
++
++	regmap_write(mixer->engine.regs, base + 4, table[3] >> 16);
++	regmap_write(mixer->engine.regs, base + 8, table[7] >> 16);
++	regmap_write(mixer->engine.regs, base + 12, table[11] >> 16);
++
++	for (i = 0; i < 12; i++) {
++		u32 val = table[i];
++
++		addr = SUN8I_CSC_COEFF(base, i);
++		if (mode == SUN8I_CSC_MODE_YVU2RGB) {
++			if ((i & 3) == 1)
++				addr = SUN8I_CSC_COEFF(base, i + 1);
++			else if ((i & 3) == 2)
++				addr = SUN8I_CSC_COEFF(base, i - 1);
++		}
++
++		if (i == 3 || i == 7 || i == 11)
++			val &= 0xffff;
++
++		regmap_write(mixer->engine.regs, addr, val);
++	}
++}
++
+ static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable)
+ {
+ 	u32 val;
+@@ -218,6 +261,12 @@ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
+ 		return;
+ 	}
+ 
++	if (mixer->cfg->is_de33) {
++		sun8i_de33_ccsc_set_coefficients(mixer, layer, mode,
++						 encoding, range);
++		return;
++	}
++
+ 	base = ccsc_base[mixer->cfg->ccsc][layer];
+ 
+ 	sun8i_csc_set_coefficients(mixer->engine.regs, base,
+@@ -233,7 +282,7 @@ void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)
+ 		return;
+ 	}
+ 
+-	base = ccsc_base[mixer->cfg->ccsc][layer];
++	base = sun8i_csc_base(mixer, layer);
+ 
+ 	sun8i_csc_enable(mixer->engine.regs, base, enable);
+ }
+diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+index 4fa69c463dc4..5915326b2699 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+@@ -124,6 +124,76 @@ static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = {
+ 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
+ };
+ 
++static const struct dw_hdmi_mpll_config sun50i_h616_mpll_cfg[] = {
++    {
++        27000000,
++        {
++            {0x00b3, 0x0003},
++            {0x2153, 0x0003},
++            {0x40f3, 0x0003},
++        },
++    },
++    {
++        74250000,
++        {
++            {0x0072, 0x0003},
++            {0x2145, 0x0003},
++            {0x4061, 0x0003},
++        },
++    },
++    {
++        148500000,
++        {
++            {0x0051, 0x0003},
++            {0x214c, 0x0003},
++            {0x4064, 0x0003},
++        },
++    },
++    {
++        297000000,
++        {
++            {0x0040, 0x0003},
++            {0x3b4c, 0x0003},
++            {0x5a64, 0x0003},
++        },
++    },
++    {
++        594000000,
++        {
++            {0x1a40, 0x0003},
++            {0x3b4c, 0x0003},
++            {0x5a64, 0x0003},
++        },
++    },
++    {
++        ~0UL,
++        {
++            {0x0000, 0x0000},
++            {0x0000, 0x0000},
++            {0x0000, 0x0000},
++        },
++    }};
++
++static const struct dw_hdmi_curr_ctrl sun50i_h616_cur_ctr[] = {
++	/* pixelclk    bpp8    bpp10   bpp12 */
++	{ 27000000, { 0x0012, 0x0000, 0x0000 }, },
++	{ 74250000, { 0x0013, 0x0013, 0x0013 }, },
++	{ 148500000, { 0x0019, 0x0019, 0x0019 }, },
++	{ 297000000, { 0x0019, 0x001b, 0x0019 }, },
++	{ 594000000, { 0x0010, 0x0010, 0x0010 }, },
++	{ ~0UL, { 0x0000, 0x0000, 0x0000 }, }
++};
++
++static const struct dw_hdmi_phy_config sun50i_h616_phy_config[] = {
++	/*pixelclk   symbol   term   vlev*/
++	{27000000, 0x8009, 0x0007, 0x02b0},
++	{74250000, 0x8019, 0x0004, 0x0290},
++	{148500000, 0x8019, 0x0004, 0x0290},
++	{297000000, 0x8039, 0x0004, 0x022b},
++	{594000000, 0x8029, 0x0000, 0x008a},
++	{~0UL, 0x0000, 0x0000, 0x0000}
++};
++
+ static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy,
+ 					const struct drm_display_mode *mode)
+ {
+@@ -626,6 +696,13 @@ static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = {
+ 	.phy_init = &sun50i_hdmi_phy_init_h6,
+ };
+ 
++static const struct sun8i_hdmi_phy_variant sun50i_h616_hdmi_phy = {
++    .cur_ctr = sun50i_h616_cur_ctr,
++    .mpll_cfg = sun50i_h616_mpll_cfg,
++    .phy_cfg = sun50i_h616_phy_config,
++    .phy_init = &sun50i_hdmi_phy_init_h6,
++};
++
+ static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
+ 	{
+ 		.compatible = "allwinner,sun8i-a83t-hdmi-phy",
+@@ -647,6 +724,10 @@ static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
+ 		.compatible = "allwinner,sun50i-h6-hdmi-phy",
+ 		.data = &sun50i_h6_hdmi_phy,
+ 	},
++	{
++		.compatible = "allwinner,sun50i-h616-hdmi-phy",
++		.data = &sun50i_h616_hdmi_phy,
++	},
+ 	{ /* sentinel */ }
+ };
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 790c7e0d6761..b0c9519c016b 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -286,6 +286,9 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 	struct drm_plane_state *plane_state;
+ 	struct drm_plane *plane;
+ 	u32 route = 0, pipe_en = 0;
++	struct regmap *bld_regs;
++
++	bld_regs = sun8i_blender_regmap(mixer);
+ 
+ 	if (mixer->hw_preconfigured && engine->id == 0) {
+ 		struct sun4i_tcon* tcon;
+@@ -347,7 +350,7 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 		pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
+ 	}
+ 
+-	regmap_update_bits(mixer->engine.regs,
++	regmap_update_bits(bld_regs,
+ 			   SUN8I_MIXER_BLEND_ROUTE(bld_base),
+ 			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(0) |
+ 			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(1) |
+@@ -355,7 +358,7 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(3),
+ 			   route);
+ 
+-	regmap_update_bits(mixer->engine.regs,
++	regmap_update_bits(bld_regs,
+ 			   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+ 			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(0) |
+ 			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(1) |
+@@ -363,8 +366,12 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(3),
+ 			   pipe_en);
+ 
+-	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
+-		     SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
++	if (mixer->cfg->is_de33)
++		regmap_write(mixer->top_regs, SUN50I_MIXER_GLOBAL_DBUFF,
++			   SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
++	else
++		regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
++			   SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
+ }
+ 
+ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
+@@ -413,25 +420,31 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine,
+ 				 const struct drm_display_mode *mode)
+ {
+ 	struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
++	struct regmap *bld_regs;
+ 	u32 bld_base, size, val;
+ 	bool interlaced;
+ 
+ 	bld_base = sun8i_blender_base(mixer);
++	bld_regs = sun8i_blender_regmap(mixer);
+ 	interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+ 	size = SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay);
+ 
+ 	DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n",
+ 			 mode->hdisplay, mode->vdisplay);
+ 
+-	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_SIZE, size);
+-	regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size);
++	if (mixer->cfg->is_de33)
++		regmap_write(mixer->top_regs, SUN50I_MIXER_GLOBAL_SIZE, size);
++	else
++		regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_SIZE, size);
++
++	regmap_write(bld_regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size);
+ 
+ 	if (interlaced)
+ 		val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
+ 	else
+ 		val = 0;
+ 
+-	regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base),
++	regmap_update_bits(bld_regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base),
+ 			   SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val);
+ 
+ 	DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
+@@ -470,6 +483,20 @@ static const struct regmap_config sun8i_mixer_regmap_config = {
+ 	.max_register	= 0xffffc, /* guessed */
+ };
+ 
++static const struct regmap_config sun8i_top_regmap_config = {
++	.reg_bits	= 32,
++	.val_bits	= 32,
++	.reg_stride	= 4,
++	.max_register	= 0x3c,
++};
++
++static const struct regmap_config sun8i_disp_regmap_config = {
++	.reg_bits	= 32,
++	.val_bits	= 32,
++	.reg_stride	= 4,
++	.max_register	= 0x20000,
++};
++
+ static int sun8i_mixer_of_get_id(struct device_node *node)
+ {
+ 	struct device_node *ep, *remote;
+@@ -490,6 +517,84 @@ static int sun8i_mixer_of_get_id(struct device_node *node)
+ 	return of_ep.id;
+ }
+ 
++static void sun8i_mixer_de2_init(struct sun8i_mixer *mixer)
++{
++	unsigned int base;
++	int plane_cnt, i;
++
++	base = sun8i_blender_base(mixer);
++
++	if (!mixer->hw_preconfigured) {
++	/* Enable the mixer */
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
++		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
++	} /* hw_preconfigured */
++
++	/* Set background color to black */
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
++		     SUN8I_MIXER_BLEND_COLOR_BLACK);
++
++	/*
++	 * Set fill color of bottom plane to black. Generally not needed
++	 * except when VI plane is at bottom (zpos = 0) and enabled.
++	 */
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
++		     SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
++		     SUN8I_MIXER_BLEND_COLOR_BLACK);
++
++	plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
++	for (i = 0; i < plane_cnt; i++)
++		regmap_write(mixer->engine.regs,
++			     SUN8I_MIXER_BLEND_MODE(base, i),
++			     SUN8I_MIXER_BLEND_MODE_DEF);
++
++	if (!mixer->hw_preconfigured) {
++	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
++	} /* hw_preconfigured */
++}
++
++static void sun8i_mixer_de33_init(struct sun8i_mixer *mixer)
++{
++	unsigned int base;
++	int plane_cnt, i;
++
++	base = sun8i_blender_base(mixer);
++
++	if (!mixer->hw_preconfigured) {
++	/* Enable the mixer */
++	regmap_write(mixer->top_regs, SUN50I_MIXER_GLOBAL_CTL,
++		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
++	} /* hw_preconfigured */
++
++	regmap_write(mixer->top_regs, SUN50I_MIXER_GLOBAL_CLK, 1);
++
++	/* Set background color to black */
++	regmap_write(mixer->disp_regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
++		     SUN8I_MIXER_BLEND_COLOR_BLACK);
++
++	/*
++	 * Set fill color of bottom plane to black. Generally not needed
++	 * except when VI plane is at bottom (zpos = 0) and enabled.
++	 */
++	regmap_write(mixer->disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
++		     SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
++	regmap_write(mixer->disp_regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
++		     SUN8I_MIXER_BLEND_COLOR_BLACK);
++
++	plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
++	for (i = 0; i < plane_cnt; i++)
++		regmap_write(mixer->disp_regs,
++			     SUN8I_MIXER_BLEND_MODE(base, i),
++			     SUN8I_MIXER_BLEND_MODE_DEF);
++
++	if (!mixer->hw_preconfigured) {
++	regmap_update_bits(mixer->disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
++	} /* hw_preconfigured */
++}
++
+ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 			      void *data)
+ {
+@@ -566,6 +671,30 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 		return PTR_ERR(mixer->engine.regs);
+ 	}
+ 
++	if (mixer->cfg->is_de33) {
++		regs = devm_platform_ioremap_resource(pdev, 1);
++		if (IS_ERR(regs))
++			return PTR_ERR(regs);
++
++		mixer->top_regs = devm_regmap_init_mmio(dev, regs,
++							&sun8i_top_regmap_config);
++		if (IS_ERR(mixer->top_regs)) {
++			dev_err(dev, "Couldn't create the top regmap\n");
++			return PTR_ERR(mixer->top_regs);
++		}
++
++		regs = devm_platform_ioremap_resource(pdev, 2);
++		if (IS_ERR(regs))
++			return PTR_ERR(regs);
++
++		mixer->disp_regs = devm_regmap_init_mmio(dev, regs,
++							&sun8i_disp_regmap_config);
++		if (IS_ERR(mixer->disp_regs)) {
++			dev_err(dev, "Couldn't create the disp regmap\n");
++			return PTR_ERR(mixer->disp_regs);
++		}
++	}
++
+ 	mixer->reset = devm_reset_control_get(dev, NULL);
+ 	if (IS_ERR(mixer->reset)) {
+ 		dev_err(dev, "Couldn't get our reset line\n");
+@@ -608,11 +737,11 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 
+ 	list_add_tail(&mixer->engine.list, &drv->engine_list);
+ 
+-	base = sun8i_blender_base(mixer);
+-
+-	if (!mixer->hw_preconfigured) {
+ 	/* Reset registers and disable unused sub-engines */
+-	if (mixer->cfg->is_de3) {
++	if (mixer->cfg->is_de33) {
++		sun8i_mixer_de33_init(mixer);
++	} else if (mixer->cfg->is_de3) {
++		if (!mixer->hw_preconfigured) {
+ 		for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
+ 			regmap_write(mixer->engine.regs, i, 0);
+ 
+@@ -626,7 +755,10 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 		regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0);
+ 		regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0);
+ 		regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0);
++		} /* hw_preconfigured */
++		sun8i_mixer_de2_init(mixer);
+ 	} else {
++		if (!mixer->hw_preconfigured) {
+ 		for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
+ 			regmap_write(mixer->engine.regs, i, 0);
+ 
+@@ -637,35 +769,8 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 		regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0);
+ 		regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0);
+ 		regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0);
+-	}
+-
+-	/* Enable the mixer */
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
+-		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
+-	} /* hw_preconfigured */
+-
+-	/* Set background color to black */
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
+-		     SUN8I_MIXER_BLEND_COLOR_BLACK);
+-
+-	/*
+-	 * Set fill color of bottom plane to black. Generally not needed
+-	 * except when VI plane is at bottom (zpos = 0) and enabled.
+-	 */
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+-		     SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
+-		     SUN8I_MIXER_BLEND_COLOR_BLACK);
+-
+-	plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
+-	for (i = 0; i < plane_cnt; i++)
+-		regmap_write(mixer->engine.regs,
+-			     SUN8I_MIXER_BLEND_MODE(base, i),
+-			     SUN8I_MIXER_BLEND_MODE_DEF);
+-
+-	if (!mixer->hw_preconfigured) {
+-	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
++		} /* hw_preconfigured */
++		sun8i_mixer_de2_init(mixer);
+ 	}
+ 
+ 	return 0;
+@@ -820,6 +925,17 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
+ 	.vi_num		= 1,
+ };
+ 
++static const struct sun8i_mixer_cfg sun50i_h616_mixer0_cfg = {
++    .ccsc = 0,
++    .is_de33 = true,
++    .mod_rate = 600000000,
++    .scaler_mask = 0xf,
++    .scanline_yuv = 4096,
++    .ui_num = 3,
++    .vi_num = 1,
++    .map = {0, 6, 7, 8},
++};
++
+ static const struct of_device_id sun8i_mixer_of_table[] = {
+ 	{
+ 		.compatible = "allwinner,sun8i-a83t-de2-mixer-0",
+@@ -869,6 +985,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
+ 		.compatible = "allwinner,sun50i-h6-de3-mixer-0",
+ 		.data = &sun50i_h6_mixer0_cfg,
+ 	},
++	{
++		.compatible = "allwinner,sun50i-h616-de33-mixer-0",
++		.data = &sun50i_h616_mixer0_cfg,
++	},
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 7bc8efca6980..e28e65572a9f 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -21,6 +21,12 @@
+ #define SUN8I_MIXER_GLOBAL_DBUFF		0x8
+ #define SUN8I_MIXER_GLOBAL_SIZE			0xc
+ 
++#define SUN50I_MIXER_GLOBAL_CTL			0x0
++#define SUN50I_MIXER_GLOBAL_STATUS		0x4
++#define SUN50I_MIXER_GLOBAL_SIZE		0x8
++#define SUN50I_MIXER_GLOBAL_CLK			0xc
++#define SUN50I_MIXER_GLOBAL_DBUFF		0x10
++
+ #define SUN8I_MIXER_GLOBAL_CTL_RT_EN		BIT(0)
+ 
+ #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE		BIT(0)
+@@ -166,6 +172,7 @@ enum {
+  * @mod_rate: module clock rate that needs to be set in order to have
+  *	a functional block.
+  * @is_de3: true, if this is next gen display engine 3.0, false otherwise.
++ * @is_de33: true, if this is next gen display engine 3.3, false otherwise.
+  * @scaline_yuv: size of a scanline for VI scaler for YUV formats.
+  */
+ struct sun8i_mixer_cfg {
+@@ -175,7 +182,9 @@ struct sun8i_mixer_cfg {
+ 	int		ccsc;
+ 	unsigned long	mod_rate;
+ 	unsigned int	is_de3 : 1;
++	unsigned int	is_de33 : 1;
+ 	unsigned int	scanline_yuv;
++	unsigned int	map[6];
+ };
+ 
+ struct sun8i_mixer {
+@@ -190,6 +199,8 @@ struct sun8i_mixer {
+ 
+ 	struct sun4i_drv		*drv;
+ 	bool				hw_preconfigured;
++	struct regmap		*top_regs;
++	struct regmap		*disp_regs;
+ };
+ 
+ enum {
+@@ -223,10 +234,19 @@ sun8i_blender_base(struct sun8i_mixer *mixer)
+ 	return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
+ }
+ 
++static inline struct regmap *
++sun8i_blender_regmap(struct sun8i_mixer *mixer)
++{
++	return mixer->cfg->is_de33 ?
++		mixer->disp_regs : mixer->engine.regs;
++}
++
+ static inline u32
+ sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
+ {
+-	if (mixer->cfg->is_de3)
++	if (mixer->cfg->is_de33)
++		return mixer->cfg->map[channel] * 0x20000 + DE2_CH_SIZE;
++	else if (mixer->cfg->is_de3)
+ 		return DE3_CH_BASE + channel * DE3_CH_SIZE;
+ 	else
+ 		return DE2_CH_BASE + channel * DE2_CH_SIZE;
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index b90e5edef4e8..92ab1ac97d25 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -23,6 +23,7 @@
+ #include "sun8i_mixer.h"
+ #include "sun8i_ui_layer.h"
+ #include "sun8i_ui_scaler.h"
++#include "sun8i_vi_scaler.h"
+ 
+ static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
+ 					int overlay, struct drm_plane *plane)
+@@ -50,6 +51,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 				       unsigned int zpos)
+ {
+ 	struct drm_plane_state *state = plane->state;
++	struct regmap *bld_regs;
+ 	u32 src_w, src_h, dst_w, dst_h;
+ 	u32 bld_base, ch_base;
+ 	u32 outsize, insize;
+@@ -59,6 +61,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 			 channel, overlay);
+ 
+ 	bld_base = sun8i_blender_base(mixer);
++	bld_regs = sun8i_blender_regmap(mixer);
+ 	ch_base = sun8i_channel_base(mixer, channel);
+ 
+ 	src_w = drm_rect_width(&state->src) >> 16;
+@@ -91,9 +94,18 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 		hscale = state->src_w / state->crtc_w;
+ 		vscale = state->src_h / state->crtc_h;
+ 
+-		sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w,
+-				      dst_h, hscale, vscale, hphase, vphase);
+-		sun8i_ui_scaler_enable(mixer, channel, true);
++		if (mixer->cfg->is_de33) {
++			sun8i_ui_scaler_setup(mixer, channel, src_w, src_h,
++					      dst_w, dst_h, hscale, vscale,
++					      hphase, vphase);
++			sun8i_ui_scaler_enable(mixer, channel, true);
++		} else {
++			sun8i_vi_scaler_setup(mixer, channel, src_w, src_h,
++					      dst_w, dst_h, hscale, vscale,
++					      hphase, vphase,
++					      state->fb->format);
++			sun8i_vi_scaler_enable(mixer, channel, true);
++		}
+ 	} else {
+ 		DRM_DEBUG_DRIVER("HW scaling is not needed\n");
+ 		sun8i_ui_scaler_enable(mixer, channel, false);
+@@ -103,10 +115,10 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 	DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
+ 			 state->dst.x1, state->dst.y1);
+ 	DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
+-	regmap_write(mixer->engine.regs,
++	regmap_write(bld_regs,
+ 		     SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
+ 		     SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
+-	regmap_write(mixer->engine.regs,
++	regmap_write(bld_regs,
+ 		     SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
+ 		     outsize);
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index 9c09d9c08496..dca22df8c748 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -54,6 +54,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ {
+ 	struct drm_plane_state *state = plane->state;
+ 	const struct drm_format_info *format = state->fb->format;
++	struct regmap *bld_regs;
+ 	u32 src_w, src_h, dst_w, dst_h;
+ 	u32 bld_base, ch_base;
+ 	u32 outsize, insize;
+@@ -66,6 +67,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 			 channel, overlay);
+ 
+ 	bld_base = sun8i_blender_base(mixer);
++	bld_regs = sun8i_blender_regmap(mixer);
+ 	ch_base = sun8i_channel_base(mixer, channel);
+ 
+ 	src_w = drm_rect_width(&state->src) >> 16;
+@@ -183,10 +185,10 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 	DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
+ 			 state->dst.x1, state->dst.y1);
+ 	DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
+-	regmap_write(mixer->engine.regs,
++	regmap_write(bld_regs,
+ 		     SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
+ 		     SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
+-	regmap_write(mixer->engine.regs,
++	regmap_write(bld_regs,
+ 		     SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
+ 		     outsize);
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+index 7ba75011adf9..3f7afa8d37c5 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+@@ -835,7 +835,9 @@ static const u32 bicubic4coefftab32[480] = {
+ 
+ static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
+ {
+-	if (mixer->cfg->is_de3)
++	if (mixer->cfg->is_de33)
++		return sun8i_channel_base(mixer, channel) + 0x3000;
++	else if (mixer->cfg->is_de3)
+ 		return DE3_VI_SCALER_UNIT_BASE +
+ 		       DE3_VI_SCALER_UNIT_SIZE * channel;
+ 	else
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/drv-thermal-sun8i_thermal-Add-for-H616.patch b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/drv-thermal-sun8i_thermal-Add-for-H616.patch
new file mode 100644
index 000000000000..2227f9b477ee
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/drv-thermal-sun8i_thermal-Add-for-H616.patch
@@ -0,0 +1,157 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Kali Prasad <kprasadvnsi@protonmail.com>
+Date: Sun, 19 Sep 2021 08:02:27 +0000
+Subject: drv:thermal:sun8i_thermal Add for H616
+
+Thermal driver for H616 SoC. Compared to H6, it has
+two additional temperature sensors for VE and DDR.
+
+Signed-off-by: Kali Prasad <kprasadvnsi@protonmail.com>
+---
+ drivers/thermal/sun8i_thermal.c | 102 ++++++++++
+ 1 file changed, 102 insertions(+)
+
+diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
+index ff811ac9e930..ad0c71990e5f 100644
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -106,6 +106,12 @@ static int sun50i_h5_calc_temp(struct ths_device *tmdev,
+ 		return -1590 * reg / 10 + 276000;
+ }
+ 
++static int sun50i_h616_calc_temp(struct ths_device *tmdev,
++			       int id, int reg)
++{
++	return (reg + tmdev->chip->offset) * tmdev->chip->scale;
++}
++
+ static int sun8i_ths_get_temp(struct thermal_zone_device *tz, int *temp)
+ {
+ 	struct tsensor *s = thermal_zone_device_priv(tz);
+@@ -276,6 +282,64 @@ static int sun50i_h6_ths_calibrate(struct ths_device *tmdev,
+ 	return 0;
+ }
+ 
++static int sun50i_h616_ths_calibrate(struct ths_device *tmdev,
++				     u16 *caldata, int callen)
++{
++	struct device *dev = tmdev->dev;
++	int i, ft_temp;
++
++	if (!caldata[0])
++		return -EINVAL;
++
++	/*
++	 * h616 efuse THS calibration data layout:
++	 *
++	 * 0      11  16     27   32     43   48    57
++	 * +----------+-----------+-----------+-----------+
++	 * |  temp |  |sensor0|   |sensor1|   |sensor2|   |
++	 * +----------+-----------+-----------+-----------+
++	 *                      ^           ^           ^
++	 *                      |           |           |
++	 *                      |           |           sensor3[11:8]
++	 *                      |           sensor3[7:4]
++	 *                      sensor3[3:0]
++	 *
++	 * The calibration data on the H616 is the ambient temperature and
++	 * sensor values that are filled during the factory test stage.
++	 *
++	 * The unit of stored FT temperature is 0.1 degreee celusis.
++	 */
++	ft_temp = caldata[0] & FT_TEMP_MASK;
++
++	for (i = 0; i < tmdev->chip->sensor_num; i++) {
++		int delta, cdata, offset, reg;
++
++		if (i == 3)
++			reg = (caldata[1] >> 12)
++			      | (caldata[2] >> 12 << 4)
++			      | (caldata[3] >> 12 << 8);
++		else
++			reg = (int)caldata[i + 1] & TEMP_CALIB_MASK;
++
++		delta = (ft_temp * 100 - tmdev->chip->calc_temp(tmdev, i, reg))
++			/ tmdev->chip->scale;
++		cdata = CALIBRATE_DEFAULT - delta;
++		if (cdata & ~TEMP_CALIB_MASK) {
++			dev_warn(dev, "sensor%d is not calibrated.\n", i);
++
++			continue;
++		}
++
++		offset = (i % 2) * 16;
++		regmap_update_bits(tmdev->regmap,
++				   SUN50I_H6_THS_TEMP_CALIB + (i / 2 * 4),
++				   0xfff << offset,
++				   cdata << offset);
++	}
++
++	return 0;
++}
++
+ static int sun8i_ths_calibrate(struct ths_device *tmdev)
+ {
+ 	struct nvmem_cell *calcell;
+@@ -464,6 +528,30 @@ static int sun50i_h6_thermal_init(struct ths_device *tmdev)
+ 	return 0;
+ }
+ 
++static int sun50i_h616_thermal_init(struct ths_device *tmdev)
++{
++	int val;
++
++	/*
++	 * For sun50iw9p1:
++	 * It is necessary that reg[0x03000000] bit[16] is 0.
++	 */
++	regmap_write(tmdev->regmap, SUN50I_THS_CTRL0,
++		     SUN8I_THS_CTRL0_T_ACQ0(47) | SUN8I_THS_CTRL2_T_ACQ1(479));
++	regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC,
++		     SUN50I_THS_FILTER_EN |
++		     SUN50I_THS_FILTER_TYPE(1));
++	regmap_write(tmdev->regmap, SUN50I_H6_THS_PC,
++		     SUN50I_H6_THS_PC_TEMP_PERIOD(365));
++	val = GENMASK(tmdev->chip->sensor_num - 1, 0);
++	regmap_write(tmdev->regmap, SUN50I_H6_THS_ENABLE, val);
++	/* thermal data interrupt enable */
++	val = GENMASK(tmdev->chip->sensor_num - 1, 0);
++	regmap_write(tmdev->regmap, SUN50I_H6_THS_DIC, val);
++
++	return 0;
++}
++
+ static int sun8i_ths_register(struct ths_device *tmdev)
+ {
+ 	int i;
+@@ -623,6 +711,19 @@ static const struct ths_thermal_chip sun50i_h6_ths = {
+ 	.calc_temp = sun8i_ths_calc_temp,
+ };
+ 
++static const struct ths_thermal_chip sun50i_h616_ths = {
++	.sensor_num = 4,
++	.has_bus_clk_reset = true,
++	.ft_deviation = 8000,
++	.offset = -3255,
++	.scale = -81,
++	.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
++	.calibrate = sun50i_h616_ths_calibrate,
++	.init = sun50i_h616_thermal_init,
++	.irq_ack = sun50i_h6_irq_ack,
++	.calc_temp = sun50i_h616_calc_temp,
++};
++
+ static const struct of_device_id of_ths_match[] = {
+ 	{ .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
+ 	{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+@@ -631,6 +732,7 @@ static const struct of_device_id of_ths_match[] = {
+ 	{ .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
+ 	{ .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
+ 	{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
++	{ .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths },
+ 	{ /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_ths_match);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/orangepi-zero2w-add-dtb.patch b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/orangepi-zero2w-add-dtb.patch
new file mode 100644
index 000000000000..f2e9477ed86c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/patches.needs-to-be-redone/orangepi-zero2w-add-dtb.patch
@@ -0,0 +1,572 @@
+From aeccb62b0f4c6891a09790f5f4546dff8cc60815 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Fri, 15 Mar 2024 12:30:26 +0800
+Subject: orangepi-zero2w add dtb
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi |  25 +-
+ .../allwinner/sun50i-h618-orangepi-zero2w.dts | 491 ++++++++++++++++++
+ 3 files changed, 509 insertions(+), 8 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 8b504ee408e7..a957365edc1a 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -56,5 +56,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb
+ 
+ subdir-y	:= $(dts-dirs) overlay
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 362c43d5eb9f..ccaca20eb10b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -209,7 +209,7 @@ video-codec@1c0e000 {
+ 
+ 		syscon: syscon@3000000 {
+ 			compatible = "allwinner,sun50i-h616-system-control";
+-			reg = <0x03000000 0x1000>;
++			reg = <0x03000000 0x30>,<0x03000038 0x0fc8>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			ranges;
+@@ -690,19 +690,28 @@ mdio0: mdio {
+ 		};
+ 
+ 		emac1: ethernet@5030000 {
+-			compatible = "allwinner,sun50i-h616-emac";
+-			syscon = <&syscon 1>;
+-			reg = <0x05030000 0x10000>;
++			compatible = "allwinner,sunxi-gmac";
++			reg = <0x05030000 0x10000>,
++			      <0x03000034 0x4>;
++			reg-names = "gmac1_reg","ephy_reg";
+ 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "macirq";
++			interrupt-names = "gmacirq";
+ 			resets = <&ccu RST_BUS_EMAC1>;
+ 			reset-names = "stmmaceth";
+-			clocks = <&ccu CLK_BUS_EMAC1>;
+-			clock-names = "stmmaceth";
++			clocks = <&ccu CLK_BUS_EMAC1>,<&ccu CLK_EMAC_25M>;
++			clock-names = "bus-emac1","emac-25m";
++			pinctrl-0 = <&rmii_pins>;
++			pinctrl-names = "default";
++			tx-delay = <7>;
++			rx-delay = <31>;
++			phy-rst;
++			gmac-power0;
++			gmac-power1;
++			gmac-power2;
+ 			status = "disabled";
+ 
+ 			mdio1: mdio {
+-				compatible = "snps,dwmac-mdio";
++				compatible = "ethernet-phy-ieee802.3-c22";
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+ 			};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+new file mode 100644
+index 000000000000..b224902f5684
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+@@ -0,0 +1,491 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2023 Arm Ltd.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
++#include "sun50i-h618-cpu-dvfs.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "OrangePi Zero 2W";
++	compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618";
++
++	aliases {
++		serial0 = &uart0;
++		serial2 = &uart2;
++		serial3 = &uart3;
++		serial4 = &uart4;
++		serial5 = &uart5;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			function = LED_FUNCTION_STATUS;
++			color = <LED_COLOR_ID_GREEN>;
++			label = "green_led";
++			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++			linux,default-trigger = "heartbeat";
++		};
++
++		100m_link {
++			label = "100m_link";
++			gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
++			default-state = "off";
++		};
++
++		100m_act {
++			label = "100m_act";
++			gpios = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
++			default-state = "off";
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		/* SY8089 DC/DC converter */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&reg_vcc5v>;
++		regulator-always-on;
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc3v3>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
++
++	ac200_pwm_clk: ac200_clk {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		// pwm5 period_ns = 500 > 334 for select 24M clock.
++		pwms = <&pwm 5 500 0>;
++		clock-frequency = <2000000>;
++		status = "okay";
++	};
++
++	soc {
++		pwm: pwm@300a000 {
++			compatible = "allwinner,sun50i-h616-pwm";
++			reg = <0x0300a000 0x400>;
++			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
++			clock-names = "mod", "bus";
++			resets = <&ccu RST_BUS_PWM>;
++			pwm-number = <6>;
++			pwm-base = <0x0>;
++			sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>;
++			#pwm-cells = <3>;
++			status = "okay";
++		};
++
++		pwm0: pwm0@0300a000 {
++			compatible = "allwinner,sunxi-pwm0";
++		};
++
++		pwm1: pwm1@0300a000 {
++			compatible = "allwinner,sunxi-pwm1";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm1_ph_pin>;
++		};
++
++		pwm2: pwm2@0300a000 {
++			compatible = "allwinner,sunxi-pwm2";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm2_ph_pin>;
++		};
++
++		pwm3: pwm3@0300a000 {
++			compatible = "allwinner,sunxi-pwm3";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm3_ph_pin>;
++		};
++
++		pwm4: pwm4@0300a000 {
++			compatible = "allwinner,sunxi-pwm4";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm4_ph_pin>;
++		};
++
++		pwm5: pwm5@0300a000 {
++			compatible = "allwinner,sunxi-pwm5";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm5_pin>;
++			clk_bypass_output = <0x1>;
++			status = "okay";
++		};
++	};
++};
++
++&de {
++	status = "okay";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "disabled";
++};
++
++&mmc0 {
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
++	bus-width = <4>;
++	vmmc-supply = <&reg_dldo1>;
++	max-frequency = <50000000>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
++&emac0 {
++	status = "disabled";
++};
++
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&rmii_phy>;
++	phy-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&mdio1 {
++	rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&ehci0 {
++	status = "disabled";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "disabled";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ir_rx_pin>;
++	status = "okay";
++};
++
++&spi0  {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
++
++	flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <40000000>;
++	};
++};
++
++&spi1 {
++	status = "disabled";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
++
++	spidev@1 {
++		compatible = "rohm,dh2228fv";
++		status = "disabled";
++		reg = <1>;
++		spi-max-frequency = <1000000>;
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pi_pins>;
++	status = "disabled";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pi_pins>;
++	status = "disabled";
++};
++
++&uart4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart4_pi_pins>;
++	status = "disabled";
++};
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart5_ph_pins>;
++	status = "disabled";
++};
++
++&i2c3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa_pins>;
++
++	ac200_x: mfd@10 {
++		compatible = "x-powers,ac200-sunxi";
++		reg = <0x10>;
++		clocks = <&ac200_pwm_clk>;
++		// ephy id
++		nvmem-cells = <&ephy_calibration>;
++		nvmem-cell-names = "calibration";
++
++		ac200_ephy: phy {
++			compatible = "x-powers,ac200-ephy-sunxi";
++			status = "okay";
++		};
++	};
++};
++
++&i2c4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c4_ph_pins>;
++	status = "disabled";
++};
++
++&usbotg {
++	/*
++	 * PHY0 pins are connected to a USB-C socket, but a role switch
++	 * is not implemented: both CC pins are pulled to GND.
++	 * The VBUS pins power the device, so a fixed peripheral mode
++	 * is the best choice.
++	 * The board can be powered via GPIOs, in this case port0 *can*
++	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
++	 * then provided by the GPIOs. Any user of this setup would
++	 * need to adjust the DT accordingly: dr_mode set to "host",
++	 * enabling OHCI0 and EHCI0.
++	 */
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_vcc5v>;
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
++&sid {
++	ephy_calibration: ephy-calibration@2c {
++		reg = <0x2c 0x2>;
++	};
++};
++
++&cpu_temp_critical {
++	temperature = <100000>;
++};
++
++&gpu_temp_critical {
++	temperature = <100000>;
++};
++
++&ve_temp_critical {
++	temperature = <100000>;
++};
++
++&ddr_temp_critical {
++	temperature = <100000>;
++};
++
++&pio {
++	vcc-pc-supply = <&reg_dldo1>;
++	vcc-pf-supply = <&reg_dldo1>;
++	vcc-pg-supply = <&reg_aldo1>;
++	vcc-ph-supply = <&reg_dldo1>;
++	vcc-pi-supply = <&reg_dldo1>;
++
++	/omit-if-no-ref/
++	i2c0_pi_pins: i2c0-pi-pins {
++		pins = "PI5", "PI6";
++		function = "i2c0";
++	};
++
++	/omit-if-no-ref/
++	i2c1_pi_pins: i2c1-pi-pins {
++		pins = "PI7", "PI8";
++		function = "i2c1";
++	};
++
++	/omit-if-no-ref/
++	i2c2_pi_pins: i2c2-pi-pins {
++		pins = "PI9", "PI10";
++		function = "i2c2";
++	};
++
++    i2c3_pa_pins: i2c3-pa-pins {
++        pins = "PA10", "PA11";
++        function = "i2c3";
++        bias-pull-up;
++    };
++
++	/omit-if-no-ref/
++	i2c4_ph_pins: i2c4-ph-pins {
++		pins = "PH6", "PH7";
++		function = "i2c4";
++	};
++
++	/omit-if-no-ref/
++	uart2_pi_pins: uart2-pi-pins {
++		pins = "PI5", "PI6";
++		function = "uart2";
++	};
++
++	/omit-if-no-ref/
++	uart3_pi_pins: uart3-pi-pins {
++		pins = "PI9", "PI10";
++		function = "uart3";
++	};
++
++	/omit-if-no-ref/
++	uart4_pi_pins: uart4-pi-pins {
++		pins = "PI13", "PI14";
++		function = "uart4";
++	};
++
++	/omit-if-no-ref/
++	uart5_ph_pins: uart5-ph-pins {
++		pins = "PH2", "PH3";
++		function = "uart5";
++	};
++
++	/omit-if-no-ref/
++	spi1_cs1_pin: spi1-cs1-pin {
++		pins = "PH9";
++		function = "spi1";
++	};
++
++	/omit-if-no-ref/
++	pwm1_ph_pin: pwm1-ph-pin {
++		pins = "PH3";
++		function = "pwm1";
++	};
++
++	/omit-if-no-ref/
++	pwm2_ph_pin: pwm2-ph-pin {
++		pins = "PH2";
++		function = "pwm2";
++	};
++
++	/omit-if-no-ref/
++	pwm3_ph_pin: pwm3-ph-pin {
++		pins = "PH0";
++		function = "pwm3";
++	};
++
++	/omit-if-no-ref/
++	pwm4_ph_pin: pwm4-ph-pin {
++		pins = "PH1";
++		function = "pwm4";
++	};
++
++	/omit-if-no-ref/
++	pwm5_pin: pwm5-pin {
++		pins = "PA12";
++		function = "pwm5";
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.9/series.armbian b/patch/kernel/archive/sunxi-6.9/series.armbian
new file mode 100644
index 000000000000..3373421d546f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/series.armbian
@@ -0,0 +1,168 @@
+#
+#	Automatically generated by the script mk_format_patch
+#
+#	https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
+#
+	patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch
+	patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch
+	patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch
+	patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch
+	patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch
+	patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch
+	patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch
+	patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch
+	patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch
+	patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch
+	patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch
+	patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch
+	patches.armbian/drv-clk-sunxi-ng-ccu-add-min-max-rate-sun50i-a64.patch
+	patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch
+	patches.armbian/sound-soc-sunxi-sun4i-spdif-add-mclk_multiplier.patch
+	patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch
+	patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch
+	patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch
+	patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch
+	patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
+	patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch
+	patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch
+	patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch
+	patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch
+	patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch
+	patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch
+	patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch
+	patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch
+	patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch
+	patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch
+	patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch
+	patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch
+	patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch
+	patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch
+	patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch
+	patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch
+	patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch
+	patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch
+	patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch
+	patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch
+	patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch
+	patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch
+	patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch
+	patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch
+	patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch
+	patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch
+	patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch
+	patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch
+	patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch
+	patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch
+	patches.armbian/Bananapro-add-AXP209-regulators.patch
+	patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch
+	patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch
+	patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch
+	patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch
+	patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch
+	patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch
+	patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch
+	patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch
+	patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch
+	patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch
+	patches.armbian/arm64-dts-allwinner-h616-Add-device-node-for-SID.patch
+	patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-.patch
+	patches.armbian/arm64-dts-allwinner-h616-Add-thermal-sensor-and-thermal-zones.patch
+	patches.armbian/Add-FB_TFT-ST7796S-driver.patch
+	patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch
+	patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch
+	patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch
+	patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch
+	patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch
+	patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch
+	patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus2-regulator-gpio-fix.patch
+	patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch
+	patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch
+	patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch
+	patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch
+	patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch
+	patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch
+	patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
+	patches.armbian/scripts-add-overlay-compilation-support.patch
+	patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch
+	patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch
+	patches.armbian/arm64-dts-allwinner-Add-Overlays-for-sunxi64.patch
+	patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch
+	patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch
+	patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch
+	patches.armbian/cb1-overlay.patch
+	patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch
+	patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch
+	patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch
+	patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch
+	patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch
+	patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch
+	patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch
+	patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch
+	patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch
+	patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch
+	patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch
+	patches.armbian/Fix-include-uapi-spi-spidev-module.patch
+	patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch
+	patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch
+	patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch
+	patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch
+	patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch
+	patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch
+	patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch
+	patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch
+	patches.armbian/arch-arm64-dts-allwinner-sun50i-h618-bananapi-m4-zero.patch
+	patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch
+	patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch
+	patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch
+	patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch
+	patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
+	patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch
+	patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch
+	patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch
+	patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch
+	patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch
+	patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch
+	patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch
+	patches.armbian/ASoC-AC200-Initial-driver.patch
+	patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch
+	patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch
+	patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch
+	patches.armbian/add-initial-support-for-orangepi3-lts.patch
+	patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch
+	patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch
+	patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch
+	patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch
+	patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch
+	patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch
+	patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
+	patches.armbian/driver-allwinner-h618-emac.patch
+	patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch
+	patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch
+	patches.armbian/adding-dummy-regulators-in-pinctr-arch-arm-boot-dts-allwinner-s.patch
diff --git a/patch/kernel/archive/sunxi-6.9/series.conf b/patch/kernel/archive/sunxi-6.9/series.conf
new file mode 100644
index 000000000000..d49b7fd64516
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/series.conf
@@ -0,0 +1,465 @@
+#
+#	This file is made manually by simply copying text
+#	from the target series.* files.
+#	Add (-) at the beginning of the line if the patch should not be applied.
+#	At the same time, the patch does not need to be deleted.
+#
+#   BRANCH:   megi/ap6275p-6.9
+	patches.megous/net-wireless-brcmfmac-Add-support-for-detecting-AP6275P.patch
+	patches.megous/net-wireless-brcmfmac-Add-optional-32k-clock-enable-support.patch
+
+#   BRANCH:   megi/ov5640-6.9
+	patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
+	patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
+	patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
+	patches.megous/media-ov5640-set-default-ae-target-lower.patch
+	patches.megous/media-ov5640-Improve-error-reporting.patch
+	patches.megous/media-ov5640-Implement-autofocus.patch
+	patches.megous/media-ov5640-Improve-firmware-load-time.patch
+	patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
+	patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
+	patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
+
+#   BRANCH:   megi/sun6i-csi-6.9
+	patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
+	patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
+	patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
+	patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
+	patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
+	patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
+
+#   BRANCH:   megi/a711-6.9
+	patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
+	patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
+	patches.megous/mmc-add-delay-after-power-class-selection.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
+	patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
+
+#   BRANCH:   megi/a711-vibrator-6.9
+	patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
+	patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
+
+#   BRANCH:   megi/a711-chgled-6.9
+	patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
+	patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
+	patches.megous/ARM-dts-axp813-Add-charger-LED.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
+
+#   BRANCH:   megi/a711-cams-6.9
+	patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
+	patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/hm5065-yaml-bindings-wip.patch
+	patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
+	patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
+	patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
+	patches.megous/media-gc2145-Disable-debug-output.patch
+	patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
+	patches.megous/media-gc2145-implement-system-suspend.patch
+	patches.megous/media-gc2145-fix-white-balance-colors.patch
+	patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
+
+#   BRANCH:   megi/a83t-suspend-6.9
+	patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
+	patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
+	patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
+	patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
+	patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
+	patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
+	patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
+
+#   BRANCH:   megi/aw-opp-6.9
+	patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
+	patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
+	patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
+	patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
+	patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
+	patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
+
+#   BRANCH:   megi/opi3-eth-6.9
+	patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
+	patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
+	patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
+	patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
+
+#   BRANCH:   megi/pp-6.9
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-acceleromet.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Retain-leds-state-in-suspend.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-AF8133J-to-PinePhone.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-PinePhone-m.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
+	patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
+	patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
+
+#   BRANCH:   megi/audio-6.9
+	patches.megous/ASoC-sun50i-codec-analog-Move-suspend-resume-to-set_bias_level.patch
+	patches.megous/ASoC-sun8i-codec-Enable-bus-clock-at-STANDBY-and-higher-bias.patch
+	patches.megous/ASoC-sun50i-codec-analog-Enable-jack-detection-on-startup.patch
+	patches.megous/ASoC-sun8i-codec-Implement-jack-and-accessory-detection.patch
+	patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
+	patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
+	patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
+	patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
+	patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
+	patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
+	patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
+	patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
+	patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
+	patches.megous/ASoC-sun8i-codec-Fix-compilation-without-CONFIG_SND_JACK_INPUT_.patch
+	patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
+
+#   BRANCH:   megi/hdmi-audio-6.9
+	patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
+	patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
+	patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/Move-a-node-to-avoid-merge-conflict.patch
+
+#   BRANCH:   megi/speed-6.9
+	patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
+	patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
+	patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
+	patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
+
+#   BRANCH:   megi/aw-suspend-6.9
+	patches.megous/clk-Implement-protected-clocks-for-all-OF-clock-providers.patch
+	patches.megous/Revert-clk-qcom-Support-protected-clocks-property.patch
+	patches.megous/ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch
+	patches.megous/arm64-dts-allwinner-a64-Protect-SCP-clocks.patch
+	patches.megous/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
+	patches.megous/bus-sunxi-rsb-Always-check-register-address-validity.patch
+	patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
+	patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
+	patches.megous/arm64-dts-allwinner-a64-Add-SCPI-protocol.patch
+	patches.megous/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
+	patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
+
+#   BRANCH:   megi/modem-6.9
+	patches.megous/misc-modem-power-Power-manager-for-modems.patch
+
+#   BRANCH:   megi/fixes-6.9
+	patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-sun50i-a64-Add-missing-trip-points-for-GPU.patch
+	patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
+	patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch
+	patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch
+	patches.megous/spi-fixes.patch
+	patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
+	patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
+	patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
+	patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
+	patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
+	patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
+	patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
+	patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
+	patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
+	patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
+	patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
+	patches.megous/Fix-intptr_t-typedef.patch
+	patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
+	patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
+	patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
+	patches.megous/media-rkisp1-Adapt-to-different-SoCs-having-different-size-limi.patch
+	patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
+
+#   BRANCH:   megi/bt-6.9
+	patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
+
+#   BRANCH:   megi/drm-6.9
+	patches.megous/drm-sun4i-Unify-sun8i_-_layer-structs.patch
+	patches.megous/drm-sun4i-Add-more-parameters-to-sunxi_engine-commit-callback.patch
+	patches.megous/drm-sun4i-Fix-layer-zpos-change-atomic-modesetting.patch
+	patches.megous/drm-sun4i-drm-Change-update_bits-to-write.patch
+	patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
+	patches.megous/drm-sun4i-Implement-gamma-correction.patch
+	patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
+	patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
+	patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
+	patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
+	patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
+
+#   BRANCH:   megi/anx-6.9
+	patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
+	patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
+	patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
+	patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
+	patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
+	patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
+	patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
+
+#   BRANCH:   megi/axp-6.9
+	patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
+	patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
+	patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
+	patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
+	patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
+	patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
+	patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
+	patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
+	patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
+	patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
+	patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
+	patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
+	patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
+	patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
+	patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
+	patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
+	patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
+
+#   BRANCH:   megi/err-6.9
+	patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
+	patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
+	patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
+	patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
+	patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
+	patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
+
+#   BRANCH:   megi/pinetab-6.9
+	patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
+	patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
+
+#   BRANCH:   megi/fusb302-6.9
+	patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
+	patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
+	patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
+	patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
+	patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
+	patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
+	patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
+	patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
+	patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
+
+#   BRANCH:   megi/typec-extcon-6.9
+	patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
+	patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
+	patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
+
+#   BRANCH:   megi/tcpm-6.9
+	patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
+	patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
+	patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
+	patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
+	patches.megous/usb-typec-tcpm-Improve-logs.patch
+
+#   BRANCH:   megi/private-6.9
+	patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
+	patches.megous/Add-support-for-my-private-Sapomat-device.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
+	patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
+
+#   BRANCH:   megi/defcon-6.9
+	patches.megous/Defconfigs-for-all-my-devices.patch
+
+######################### Armbian patches ######################################
+
+	patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch
+	patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch
+	patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch
+	patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch
+	patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch
+	patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch
+	patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch
+	patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch
+	patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch
+	patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch
+	patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch
+	patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch
+	patches.armbian/drv-clk-sunxi-ng-ccu-add-min-max-rate-sun50i-a64.patch
+	patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch
+	patches.armbian/sound-soc-sunxi-sun4i-spdif-add-mclk_multiplier.patch
+	patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch
+	patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch
+	patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch
+	patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch
+	patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
+	patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch
+	patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch
+	patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch
+	patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch
+	patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch
+	patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch
+	patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch
+	patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch
+	patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch
+	patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch
+	patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch
+	patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch
+	patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch
+	patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch
+	patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch
+	patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch
+	patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch
+	patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch
+	patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch
+	patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch
+	patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch
+	patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch
+	patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch
+	patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch
+	patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch
+	patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch
+	patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch
+	patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch
+	patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch
+	patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch
+	patches.armbian/Bananapro-add-AXP209-regulators.patch
+	patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch
+	patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch
+	patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch
+	patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch
+	patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch
+	patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch
+	patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch
+	patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch
+	patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch
+	patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch
+	patches.armbian/arm64-dts-allwinner-h616-Add-device-node-for-SID.patch
+	patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-.patch
+	patches.armbian/arm64-dts-allwinner-h616-Add-thermal-sensor-and-thermal-zones.patch
+	patches.armbian/Add-FB_TFT-ST7796S-driver.patch
+	patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch
+	patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch
+	patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch
+	patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch
+	patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch
+	patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch
+	patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus2-regulator-gpio-fix.patch
+	patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch
+	patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch
+	patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch
+	patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch
+	patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch
+	patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch
+	patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
+	patches.armbian/scripts-add-overlay-compilation-support.patch
+	patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch
+	patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch
+	patches.armbian/arm64-dts-allwinner-Add-Overlays-for-sunxi64.patch
+	patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch
+	patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch
+	patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch
+	patches.armbian/cb1-overlay.patch
+	patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch
+	patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch
+	patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch
+	patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch
+	patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch
+	patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch
+	patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch
+	patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch
+	patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch
+	patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch
+	patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch
+	patches.armbian/Fix-include-uapi-spi-spidev-module.patch
+	patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch
+	patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch
+	patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch
+	patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch
+	patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch
+	patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch
+	patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch
+	patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch
+	patches.armbian/arch-arm64-dts-allwinner-sun50i-h618-bananapi-m4-zero.patch
+	patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch
+	patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch
+	patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch
+	patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch
+	patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
+	patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch
+	patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch
+	patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch
+	patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch
+	patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch
+	patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch
+	patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch
+	patches.armbian/ASoC-AC200-Initial-driver.patch
+	patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch
+	patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch
+	patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch
+	patches.armbian/add-initial-support-for-orangepi3-lts.patch
+	patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch
+	patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch
+	patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch
+	patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch
+	patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch
+	patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch
+	patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
+	patches.armbian/driver-allwinner-h618-emac.patch
+	patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch
+	patches.armbian/arch-arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch
+	patches.armbian/adding-dummy-regulators-in-pinctr-arch-arm-boot-dts-allwinner-s.patch
diff --git a/patch/kernel/archive/sunxi-6.9/series.megous b/patch/kernel/archive/sunxi-6.9/series.megous
new file mode 100644
index 000000000000..5ed5efb1517d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.9/series.megous
@@ -0,0 +1,268 @@
+#   Branches:
+#	megi/ap6275p-6.9
+#	megi/ov5640-6.9
+#	megi/sun6i-csi-6.9
+#	megi/a711-6.9
+#	megi/a711-vibrator-6.9
+#	megi/a711-chgled-6.9
+#	megi/a711-cams-6.9
+#	megi/a83t-suspend-6.9
+#	megi/aw-opp-6.9
+#	megi/opi3-eth-6.9
+#	megi/audio-6.9
+#	megi/hdmi-audio-6.9
+#	megi/speed-6.9
+#	megi/aw-suspend-6.9
+#	megi/modem-6.9
+#	megi/fixes-6.9
+#	megi/bt-6.9
+#	megi/drm-6.9
+#	megi/anx-6.9
+#	megi/axp-6.9
+#	megi/err-6.9
+#	megi/pinetab-6.9
+#	megi/fusb302-6.9
+#	megi/typec-extcon-6.9
+#	megi/tcpm-6.9
+#	megi/private-6.9
+#	megi/defcon-6.9
+#
+	patches.megous/net-wireless-brcmfmac-Add-support-for-detecting-AP6275P.patch
+	patches.megous/net-wireless-brcmfmac-Add-optional-32k-clock-enable-support.patch
+	patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
+	patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
+	patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
+	patches.megous/media-ov5640-set-default-ae-target-lower.patch
+	patches.megous/media-ov5640-Improve-error-reporting.patch
+	patches.megous/media-ov5640-Implement-autofocus.patch
+	patches.megous/media-ov5640-Improve-firmware-load-time.patch
+	patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
+	patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
+	patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
+	patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
+	patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
+	patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
+	patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
+	patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
+	patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
+	patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
+	patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
+	patches.megous/mmc-add-delay-after-power-class-selection.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
+	patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
+	patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
+	patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
+	patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
+	patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
+	patches.megous/ARM-dts-axp813-Add-charger-LED.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
+	patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
+	patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/hm5065-yaml-bindings-wip.patch
+	patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
+	patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
+	patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
+	patches.megous/media-gc2145-Disable-debug-output.patch
+	patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
+	patches.megous/media-gc2145-implement-system-suspend.patch
+	patches.megous/media-gc2145-fix-white-balance-colors.patch
+	patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
+	patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
+	patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
+	patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
+	patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
+	patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
+	patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
+	patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
+	patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
+	patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
+	patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
+	patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
+	patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
+	patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
+	patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
+	patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
+	patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
+	patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-acceleromet.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Retain-leds-state-in-suspend.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-AF8133J-to-PinePhone.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-mount-matrix-for-PinePhone-m.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
+	patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
+	patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
+	patches.megous/ASoC-sun50i-codec-analog-Move-suspend-resume-to-set_bias_level.patch
+	patches.megous/ASoC-sun8i-codec-Enable-bus-clock-at-STANDBY-and-higher-bias.patch
+	patches.megous/ASoC-sun50i-codec-analog-Enable-jack-detection-on-startup.patch
+	patches.megous/ASoC-sun8i-codec-Implement-jack-and-accessory-detection.patch
+	patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
+	patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
+	patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
+	patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
+	patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
+	patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
+	patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
+	patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
+	patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
+	patches.megous/ASoC-sun8i-codec-Fix-compilation-without-CONFIG_SND_JACK_INPUT_.patch
+	patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
+	patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
+	patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
+	patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/Move-a-node-to-avoid-merge-conflict.patch
+	patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
+	patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
+	patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
+	patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
+	patches.megous/clk-Implement-protected-clocks-for-all-OF-clock-providers.patch
+	patches.megous/Revert-clk-qcom-Support-protected-clocks-property.patch
+	patches.megous/ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch
+	patches.megous/arm64-dts-allwinner-a64-Protect-SCP-clocks.patch
+	patches.megous/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
+	patches.megous/bus-sunxi-rsb-Always-check-register-address-validity.patch
+	patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
+	patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
+	patches.megous/arm64-dts-allwinner-a64-Add-SCPI-protocol.patch
+	patches.megous/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
+	patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
+	patches.megous/misc-modem-power-Power-manager-for-modems.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-sun50i-a64-Add-missing-trip-points-for-GPU.patch
+	patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
+	patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch
+	patches.megous/spi-rockchip-Fix-runtime-PM-and-other-issues.patch
+	patches.megous/spi-fixes.patch
+	patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
+	patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
+	patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
+	patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
+	patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
+	patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
+	patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
+	patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
+	patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
+	patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
+	patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
+	patches.megous/Fix-intptr_t-typedef.patch
+	patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
+	patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
+	patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
+	patches.megous/media-rkisp1-Adapt-to-different-SoCs-having-different-size-limi.patch
+	patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
+	patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
+	patches.megous/drm-sun4i-Unify-sun8i_-_layer-structs.patch
+	patches.megous/drm-sun4i-Add-more-parameters-to-sunxi_engine-commit-callback.patch
+	patches.megous/drm-sun4i-Fix-layer-zpos-change-atomic-modesetting.patch
+	patches.megous/drm-sun4i-drm-Change-update_bits-to-write.patch
+	patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
+	patches.megous/drm-sun4i-Implement-gamma-correction.patch
+	patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
+	patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
+	patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
+	patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
+	patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
+	patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
+	patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
+	patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
+	patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
+	patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
+	patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
+	patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
+	patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
+	patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
+	patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
+	patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
+	patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
+	patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
+	patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
+	patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
+	patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
+	patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
+	patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
+	patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
+	patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
+	patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
+	patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
+	patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
+	patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
+	patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
+	patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
+	patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
+	patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
+	patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
+	patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
+	patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
+	patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
+	patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
+	patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
+	patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
+	patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
+	patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
+	patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
+	patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
+	patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
+	patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
+	patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
+	patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
+	patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
+	patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
+	patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
+	patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
+	patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
+	patches.megous/usb-typec-tcpm-Improve-logs.patch
+	patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
+	patches.megous/Add-support-for-my-private-Sapomat-device.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
+	patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
+	patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
+	patches.megous/Defconfigs-for-all-my-devices.patch
diff --git a/patch/kernel/rk35xx-legacy/001-hid-sony.patch b/patch/kernel/rk35xx-legacy/001-hid-sony.patch
new file mode 100644
index 000000000000..6d001c38e960
--- /dev/null
+++ b/patch/kernel/rk35xx-legacy/001-hid-sony.patch
@@ -0,0 +1,111 @@
+Signed-off-by: Ivan Mironov <mironov.ivan@gmail.com>
+---
+ drivers/hid/hid-sony.c | 72 ++++++++++++++++++++++++++++++------------
+ 1 file changed, 52 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c
+index e3a557dc9ffd..97df12180e45 100644
+--- a/drivers/hid/hid-sony.c
++++ b/drivers/hid/hid-sony.c
+@@ -491,6 +491,7 @@ struct motion_output_report_02 {
+ 
+ #define DS4_FEATURE_REPORT_0x02_SIZE 37
+ #define DS4_FEATURE_REPORT_0x05_SIZE 41
++#define DS4_FEATURE_REPORT_0x12_SIZE 16
+ #define DS4_FEATURE_REPORT_0x81_SIZE 7
+ #define DS4_FEATURE_REPORT_0xA3_SIZE 49
+ #define DS4_INPUT_REPORT_0x11_SIZE 78
+@@ -2593,6 +2594,53 @@ static int sony_get_bt_devaddr(struct sony_sc *sc)
+ 	return 0;
+ }
+ 
++static int sony_get_usb_ds4_devaddr(struct sony_sc *sc)
++{
++	u8 *buf = NULL;
++	int ret;
++
++	buf = kmalloc(max(DS4_FEATURE_REPORT_0x12_SIZE, DS4_FEATURE_REPORT_0x81_SIZE), GFP_KERNEL);
++	if (!buf)
++		return -ENOMEM;
++
++	/*
++	 * The MAC address of a DS4 controller connected via USB can be
++	 * retrieved with feature report 0x81. The address begins at
++	 * offset 1.
++	 */
++	ret = hid_hw_raw_request(sc->hdev, 0x81, buf,
++			DS4_FEATURE_REPORT_0x81_SIZE, HID_FEATURE_REPORT,
++			HID_REQ_GET_REPORT);
++	if (ret == DS4_FEATURE_REPORT_0x81_SIZE) {
++		memcpy(sc->mac_address, &buf[1], sizeof(sc->mac_address));
++		goto out_free;
++	}
++	dbg_hid("%s: hid_hw_raw_request(..., 0x81, ...) returned %d\n", __func__, ret);
++
++	/*
++	 * Some variants do not implement feature report 0x81 at all.
++	 * Fortunately, feature report 0x12 also contains the MAC address of
++	 * a controller.
++	 */
++	ret = hid_hw_raw_request(sc->hdev, 0x12, buf,
++			DS4_FEATURE_REPORT_0x12_SIZE, HID_FEATURE_REPORT,
++			HID_REQ_GET_REPORT);
++	if (ret == DS4_FEATURE_REPORT_0x12_SIZE) {
++		memcpy(sc->mac_address, &buf[1], sizeof(sc->mac_address));
++		goto out_free;
++	}
++	dbg_hid("%s: hid_hw_raw_request(..., 0x12, ...) returned %d\n", __func__, ret);
++
++	hid_err(sc->hdev, "failed to retrieve feature reports 0x81 and 0x12 with the DualShock 4 MAC address\n");
++	ret = ret < 0 ? ret : -EINVAL;
++
++out_free:
++
++	kfree(buf);
++
++	return ret;
++}
++
+ static int sony_check_add(struct sony_sc *sc)
+ {
+ 	u8 *buf = NULL;
+@@ -2613,26 +2661,9 @@ static int sony_check_add(struct sony_sc *sc)
+ 			return 0;
+ 		}
+ 	} else if (sc->quirks & (DUALSHOCK4_CONTROLLER_USB | DUALSHOCK4_DONGLE)) {
+-		buf = kmalloc(DS4_FEATURE_REPORT_0x81_SIZE, GFP_KERNEL);
+-		if (!buf)
+-			return -ENOMEM;
+-
+-		/*
+-		 * The MAC address of a DS4 controller connected via USB can be
+-		 * retrieved with feature report 0x81. The address begins at
+-		 * offset 1.
+-		 */
+-		ret = hid_hw_raw_request(sc->hdev, 0x81, buf,
+-				DS4_FEATURE_REPORT_0x81_SIZE, HID_FEATURE_REPORT,
+-				HID_REQ_GET_REPORT);
+-
+-		if (ret != DS4_FEATURE_REPORT_0x81_SIZE) {
+-			hid_err(sc->hdev, "failed to retrieve feature report 0x81 with the DualShock 4 MAC address\n");
+-			ret = ret < 0 ? ret : -EINVAL;
+-			goto out_free;
+-		}
+-
+-		memcpy(sc->mac_address, &buf[1], sizeof(sc->mac_address));
++		ret = sony_get_usb_ds4_devaddr(sc);
++		if (ret < 0)
++			return ret;
+ 
+ 		snprintf(sc->hdev->uniq, sizeof(sc->hdev->uniq),
+ 			 "%pMR", sc->mac_address);
+@@ -2670,6 +2701,7 @@ static int sony_check_add(struct sony_sc *sc)
+ 		return 0;
+ 	}
+ 
++	dbg_hid("%s: retrieved MAC address: %s\n", __func__, sc->hdev->uniq);
+ 	ret = sony_check_add_dev_list(sc);
+ 
+ out_free:
+-- 
+2.29.2
\ No newline at end of file
diff --git a/patch/kernel/rk35xx-vendor-6.1/001-hid-sony.patch b/patch/kernel/rk35xx-vendor-6.1/001-hid-sony.patch
new file mode 100644
index 000000000000..6d001c38e960
--- /dev/null
+++ b/patch/kernel/rk35xx-vendor-6.1/001-hid-sony.patch
@@ -0,0 +1,111 @@
+Signed-off-by: Ivan Mironov <mironov.ivan@gmail.com>
+---
+ drivers/hid/hid-sony.c | 72 ++++++++++++++++++++++++++++++------------
+ 1 file changed, 52 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c
+index e3a557dc9ffd..97df12180e45 100644
+--- a/drivers/hid/hid-sony.c
++++ b/drivers/hid/hid-sony.c
+@@ -491,6 +491,7 @@ struct motion_output_report_02 {
+ 
+ #define DS4_FEATURE_REPORT_0x02_SIZE 37
+ #define DS4_FEATURE_REPORT_0x05_SIZE 41
++#define DS4_FEATURE_REPORT_0x12_SIZE 16
+ #define DS4_FEATURE_REPORT_0x81_SIZE 7
+ #define DS4_FEATURE_REPORT_0xA3_SIZE 49
+ #define DS4_INPUT_REPORT_0x11_SIZE 78
+@@ -2593,6 +2594,53 @@ static int sony_get_bt_devaddr(struct sony_sc *sc)
+ 	return 0;
+ }
+ 
++static int sony_get_usb_ds4_devaddr(struct sony_sc *sc)
++{
++	u8 *buf = NULL;
++	int ret;
++
++	buf = kmalloc(max(DS4_FEATURE_REPORT_0x12_SIZE, DS4_FEATURE_REPORT_0x81_SIZE), GFP_KERNEL);
++	if (!buf)
++		return -ENOMEM;
++
++	/*
++	 * The MAC address of a DS4 controller connected via USB can be
++	 * retrieved with feature report 0x81. The address begins at
++	 * offset 1.
++	 */
++	ret = hid_hw_raw_request(sc->hdev, 0x81, buf,
++			DS4_FEATURE_REPORT_0x81_SIZE, HID_FEATURE_REPORT,
++			HID_REQ_GET_REPORT);
++	if (ret == DS4_FEATURE_REPORT_0x81_SIZE) {
++		memcpy(sc->mac_address, &buf[1], sizeof(sc->mac_address));
++		goto out_free;
++	}
++	dbg_hid("%s: hid_hw_raw_request(..., 0x81, ...) returned %d\n", __func__, ret);
++
++	/*
++	 * Some variants do not implement feature report 0x81 at all.
++	 * Fortunately, feature report 0x12 also contains the MAC address of
++	 * a controller.
++	 */
++	ret = hid_hw_raw_request(sc->hdev, 0x12, buf,
++			DS4_FEATURE_REPORT_0x12_SIZE, HID_FEATURE_REPORT,
++			HID_REQ_GET_REPORT);
++	if (ret == DS4_FEATURE_REPORT_0x12_SIZE) {
++		memcpy(sc->mac_address, &buf[1], sizeof(sc->mac_address));
++		goto out_free;
++	}
++	dbg_hid("%s: hid_hw_raw_request(..., 0x12, ...) returned %d\n", __func__, ret);
++
++	hid_err(sc->hdev, "failed to retrieve feature reports 0x81 and 0x12 with the DualShock 4 MAC address\n");
++	ret = ret < 0 ? ret : -EINVAL;
++
++out_free:
++
++	kfree(buf);
++
++	return ret;
++}
++
+ static int sony_check_add(struct sony_sc *sc)
+ {
+ 	u8 *buf = NULL;
+@@ -2613,26 +2661,9 @@ static int sony_check_add(struct sony_sc *sc)
+ 			return 0;
+ 		}
+ 	} else if (sc->quirks & (DUALSHOCK4_CONTROLLER_USB | DUALSHOCK4_DONGLE)) {
+-		buf = kmalloc(DS4_FEATURE_REPORT_0x81_SIZE, GFP_KERNEL);
+-		if (!buf)
+-			return -ENOMEM;
+-
+-		/*
+-		 * The MAC address of a DS4 controller connected via USB can be
+-		 * retrieved with feature report 0x81. The address begins at
+-		 * offset 1.
+-		 */
+-		ret = hid_hw_raw_request(sc->hdev, 0x81, buf,
+-				DS4_FEATURE_REPORT_0x81_SIZE, HID_FEATURE_REPORT,
+-				HID_REQ_GET_REPORT);
+-
+-		if (ret != DS4_FEATURE_REPORT_0x81_SIZE) {
+-			hid_err(sc->hdev, "failed to retrieve feature report 0x81 with the DualShock 4 MAC address\n");
+-			ret = ret < 0 ? ret : -EINVAL;
+-			goto out_free;
+-		}
+-
+-		memcpy(sc->mac_address, &buf[1], sizeof(sc->mac_address));
++		ret = sony_get_usb_ds4_devaddr(sc);
++		if (ret < 0)
++			return ret;
+ 
+ 		snprintf(sc->hdev->uniq, sizeof(sc->hdev->uniq),
+ 			 "%pMR", sc->mac_address);
+@@ -2670,6 +2701,7 @@ static int sony_check_add(struct sony_sc *sc)
+ 		return 0;
+ 	}
+ 
++	dbg_hid("%s: retrieved MAC address: %s\n", __func__, sc->hdev->uniq);
+ 	ret = sony_check_add_dev_list(sc);
+ 
+ out_free:
+-- 
+2.29.2
\ No newline at end of file
diff --git a/patch/u-boot/legacy/u-boot-armsom-rk3576/0001-dw_mmc-add-default-power-enable-config-val.patch b/patch/u-boot/legacy/u-boot-armsom-rk3576/0001-dw_mmc-add-default-power-enable-config-val.patch
new file mode 100644
index 000000000000..2a6f806e128b
--- /dev/null
+++ b/patch/u-boot/legacy/u-boot-armsom-rk3576/0001-dw_mmc-add-default-power-enable-config-val.patch
@@ -0,0 +1,46 @@
+From d21080aff74c06f2b2303bc298bf7485818768db Mon Sep 17 00:00:00 2001
+From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
+Date: Wed, 8 May 2024 10:00:14 +0800
+Subject: [PATCH 1/2] dw_mmc: add default power enable config value for rk3576
+
+Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
+Change-Id: I2ce85f3c107c51b84413ca2f9ae66b33e4a00c18
+---
+ drivers/mmc/Kconfig  | 7 +++++++
+ drivers/mmc/dw_mmc.c | 2 +-
+ 2 files changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
+index 8e365e45f58..3ccfaa5fa17 100644
+--- a/drivers/mmc/Kconfig
++++ b/drivers/mmc/Kconfig
+@@ -84,6 +84,13 @@ config MMC_DW
+ 	  block, this provides host support for SD and MMC interfaces, in both
+ 	  PIO, internal DMA mode and external DMA mode.
+ 
++config MMC_DW_PWREN_VALUE
++	hex "mmc dw powen value"
++	default 1 if ROCKCHIP_RK3576
++	default 0
++	help
++	  Config the value for MMC-DW drivers to power on sd card.
++
+ config MMC_DW_EXYNOS
+ 	bool "Exynos specific extensions for Synopsys DW Memory Card Interface"
+ 	depends on ARCH_EXYNOS
+diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
+index d961bce248b..37e4d50512d 100644
+--- a/drivers/mmc/dw_mmc.c
++++ b/drivers/mmc/dw_mmc.c
+@@ -818,7 +818,7 @@ static int dwmci_init(struct mmc *mmc)
+ 	if (host->dev_index == 0)
+ 		dwmci_writel(host, DWMCI_PWREN, 1);
+ 	else if (host->dev_index == 1)
+-		dwmci_writel(host, DWMCI_PWREN, 0);
++		dwmci_writel(host, DWMCI_PWREN, CONFIG_MMC_DW_PWREN_VALUE);
+ 	else
+ 		dwmci_writel(host, DWMCI_PWREN, 1);
+ #else
+-- 
+2.34.1
+
diff --git a/patch/u-boot/legacy/u-boot-armsom-rk3576/0002-dts-rockchip-rk3576-the-power_en-for-SD-co.patch b/patch/u-boot/legacy/u-boot-armsom-rk3576/0002-dts-rockchip-rk3576-the-power_en-for-SD-co.patch
new file mode 100644
index 000000000000..927e5c58f367
--- /dev/null
+++ b/patch/u-boot/legacy/u-boot-armsom-rk3576/0002-dts-rockchip-rk3576-the-power_en-for-SD-co.patch
@@ -0,0 +1,38 @@
+From 2138ea1a16205051685bf85771b4412019df5a56 Mon Sep 17 00:00:00 2001
+From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
+Date: Wed, 8 May 2024 10:01:34 +0800
+Subject: [PATCH 2/2] dts: rockchip: rk3576: the power_en for SD control by the
+ controller
+
+Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
+Change-Id: Ibf4d8a3f0502385c075cd114b13a30b1bff866a8
+---
+ arch/arm/dts/rk3576-u-boot.dtsi | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi
+index 2abdef5c08f..fc7527064a5 100644
+--- a/arch/arm/dts/rk3576-u-boot.dtsi
++++ b/arch/arm/dts/rk3576-u-boot.dtsi
+@@ -139,7 +139,6 @@
+ &sdmmc {
+ 	bus-width = <4>;
+ 	u-boot,dm-spl;
+-	pwr-en-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ 	status = "okay";
+ };
+ 
+@@ -172,6 +171,10 @@
+ 	u-boot,dm-spl;
+ };
+ 
++&sdmmc0_pwren {
++	u-boot,dm-spl;
++};
++
+ &pinctrl {
+ 	u-boot,dm-spl;
+ };
+-- 
+2.34.1
+
diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/board_firefly-itx-3588j/board-firefly-itx-3588j-disable-optee-security.patch b/patch/u-boot/legacy/u-boot-radxa-rk35xx/board_firefly-itx-3588j/board-firefly-itx-3588j-disable-optee-security.patch
new file mode 100644
index 000000000000..b04304aba288
--- /dev/null
+++ b/patch/u-boot/legacy/u-boot-radxa-rk35xx/board_firefly-itx-3588j/board-firefly-itx-3588j-disable-optee-security.patch
@@ -0,0 +1,22 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: None <None>
+Date: Tue, 2 Jul 2024 21:37:46 +0000
+Subject: disable always use security partition avoid not booting
+
+---
+ configs/rk3588_defconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/configs/rk3588_defconfig b/configs/rk3588_defconfig
+index 111111111111..222222222222 100644
+--- a/configs/rk3588_defconfig
++++ b/configs/rk3588_defconfig
+@@ -233,4 +233,4 @@ CONFIG_AVB_LIBAVB_USER=y
+ CONFIG_RK_AVB_LIBAVB_USER=y
+ CONFIG_OPTEE_CLIENT=y
+ CONFIG_OPTEE_V2=y
+-CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
++CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=n
+-- 
+Armbian
+
diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/armsom-aim7-io-rk3588_defconfig b/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/armsom-aim7-io-rk3588_defconfig
new file mode 100644
index 000000000000..97642e9f4fa5
--- /dev/null
+++ b/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/armsom-aim7-io-rk3588_defconfig
@@ -0,0 +1,214 @@
+CONFIG_ARM=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_FIT_IMAGE=y
+CONFIG_ROCKCHIP_HWID_DTB=y
+CONFIG_ROCKCHIP_VENDOR_PARTITION=y
+CONFIG_USING_KERNEL_DTB_V2=y
+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
+CONFIG_ROCKCHIP_NEW_IDB=y
+CONFIG_LOADER_INI="RK3588MINIALL.ini"
+CONFIG_TRUST_INI="RK3588TRUST.ini"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-armsom-aim7-io"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_FIT_HW_CRYPTO=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SPL_FIT_HW_CRYPTO=y
+# CONFIG_SPL_SYS_DCACHE_OFF is not set
+CONFIG_BOOTDELAY=0
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_ANDROID_BOOTLOADER=y
+CONFIG_ANDROID_AVB=y
+CONFIG_ANDROID_BOOT_IMAGE_HASH=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
+CONFIG_SPL_MMC_WRITE=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_FASTBOOT_BUF_ADDR=0xc00800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_BOOT_ANDROID=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTP_BOOTM=y
+CONFIG_CMD_TFTP_FLASH=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTD_BLK=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DTB_MINIMUM=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_NET_TFTP_VARS is not set
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SARADC_ROCKCHIP is not set
+CONFIG_SARADC_ROCKCHIP_V2=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_SCMI=y
+CONFIG_SPL_CLK_SCMI=y
+CONFIG_DM_CRYPTO=y
+CONFIG_SPL_DM_CRYPTO=y
+CONFIG_ROCKCHIP_CRYPTO_V2=y
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_SCMI_FIRMWARE=y
+CONFIG_SPL_SCMI_FIRMWARE=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_DM_KEY=y
+CONFIG_ADC_KEY=y
+CONFIG_MISC=y
+CONFIG_SPL_MISC=y
+CONFIG_MISC_DECOMPRESS=y
+CONFIG_SPL_MISC_DECOMPRESS=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_ROCKCHIP_HW_DECOMPRESS=y
+CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_MTD=y
+CONFIG_MTD_BLK=y
+CONFIG_MTD_DEVICE=y
+CONFIG_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=80000000
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_SPI_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK860X=y
+CONFIG_REGULATOR_RK806=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_ROCKCHIP_SDRAM_COMMON=y
+CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
+CONFIG_DM_RESET=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_RESET_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_LIB_RAND=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_N_SIZE=0x200
+CONFIG_RSA_E_SIZE=0x10
+CONFIG_RSA_C_SIZE=0x20
+CONFIG_LZ4=y
+CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_AVB_LIBAVB=y
+CONFIG_AVB_LIBAVB_AB=y
+CONFIG_AVB_LIBAVB_ATX=y
+CONFIG_AVB_LIBAVB_USER=y
+CONFIG_RK_AVB_LIBAVB_USER=y
+CONFIG_OPTEE_CLIENT=y
+CONFIG_OPTEE_V2=y
diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/retro-lite-cm5-rk3588s_defconfig b/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/retro-lite-cm5-rk3588s_defconfig
new file mode 100644
index 000000000000..14342294775c
--- /dev/null
+++ b/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/retro-lite-cm5-rk3588s_defconfig
@@ -0,0 +1,222 @@
+CONFIG_ARM=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_USB_BOOT=y
+CONFIG_ROCKCHIP_FIT_IMAGE=y
+CONFIG_ROCKCHIP_HWID_DTB=y
+CONFIG_ROCKCHIP_VENDOR_PARTITION=y
+CONFIG_USING_KERNEL_DTB_V2=y
+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
+CONFIG_ROCKCHIP_NEW_IDB=y
+CONFIG_LOADER_INI="RK3588MINIALL.ini"
+CONFIG_TRUST_INI="RK3588TRUST.ini"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-retro-lite-cm5"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_FIT_HW_CRYPTO=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SPL_FIT_HW_CRYPTO=y
+# CONFIG_SPL_SYS_DCACHE_OFF is not set
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOOTMETH_ANDROID=y
+CONFIG_ANDROID_BOOTLOADER=y
+CONFIG_ANDROID_AVB=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_ANDROID_BOOT_IMAGE_HASH=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
+CONFIG_SPL_MMC_WRITE=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_FASTBOOT_BUF_ADDR=0xc00800
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_CMD_ABOOTIMG=y
+CONFIG_CMD_ADTIMG=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_BOOT_ANDROID=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTP_BOOTM=y
+CONFIG_CMD_TFTP_FLASH=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTD_BLK=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DTB_MINIMUM=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_NET_TFTP_VARS is not set
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SARADC_ROCKCHIP is not set
+CONFIG_SARADC_ROCKCHIP_V2=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_SCMI=y
+CONFIG_SPL_CLK_SCMI=y
+CONFIG_DM_CRYPTO=y
+CONFIG_SPL_DM_CRYPTO=y
+CONFIG_ROCKCHIP_CRYPTO_V2=y
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_SCMI_FIRMWARE=y
+CONFIG_SPL_SCMI_FIRMWARE=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_DM_KEY=y
+CONFIG_ADC_KEY=y
+CONFIG_MISC=y
+CONFIG_SPL_MISC=y
+CONFIG_MISC_DECOMPRESS=y
+CONFIG_SPL_MISC_DECOMPRESS=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_ROCKCHIP_HW_DECOMPRESS=y
+CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_MTD=y
+CONFIG_MTD_BLK=y
+CONFIG_MTD_DEVICE=y
+CONFIG_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=80000000
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_SPI_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK860X=y
+CONFIG_REGULATOR_RK806=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_ROCKCHIP_SDRAM_COMMON=y
+CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
+CONFIG_DM_RESET=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_RESET_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_LIB_RAND=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_N_SIZE=0x200
+CONFIG_RSA_E_SIZE=0x10
+CONFIG_RSA_C_SIZE=0x20
+CONFIG_XBC=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_AVB_LIBAVB=y
+CONFIG_AVB_LIBAVB_AB=y
+CONFIG_AVB_LIBAVB_ATX=y
+CONFIG_AVB_LIBAVB_USER=y
+CONFIG_RK_AVB_LIBAVB_USER=y
+CONFIG_OPTEE_CLIENT=y
+CONFIG_OPTEE_V2=y
diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588-armsom-aim7-io.dts b/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588-armsom-aim7-io.dts
new file mode 100644
index 000000000000..52cf2d0db5d6
--- /dev/null
+++ b/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588-armsom-aim7-io.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd
+ *
+ */
+
+/dts-v1/;
+#include "rk3588.dtsi"
+#include "rk3588-u-boot.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "ArmSoM AIM7 IO Board";
+	compatible = "armsom,aim7-io", "rockchip,rk3588";
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		u-boot,dm-pre-reloc;
+		status = "okay";
+
+		volumeup-key {
+			u-boot,dm-pre-reloc;
+			linux,code = <KEY_VOLUMEUP>;
+			label = "volume up";
+			press-threshold-microvolt = <1750>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwrbtn>;
+
+		button@0 {
+			gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			label = "GPIO Key Power";
+			linux,input-type = <1>;
+			gpio-key,wakeup = <1>;
+			debounce-interval = <100>;
+		};
+	};
+};
+
+&pinctrl {
+	pcfg_output_high: pcfg-output-high {
+		output-high;
+	};
+
+	buttons {
+		pwrbtn: pwrbtn {
+			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+};
diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-retro-lite-cm5.dts b/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-retro-lite-cm5.dts
new file mode 100644
index 000000000000..0e9c435159c2
--- /dev/null
+++ b/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-retro-lite-cm5.dts
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 StonedEdge and GinKage
+ *
+ */
+
+/dts-v1/;
+#include "rk3588s-radxa-cm5.dtsi"
+
+/ {
+	model = "Retro Lite CM5";
+	compatible = "retro-lite,cm5", "radxa,cm5", "rockchip,rk3588";
+
+	vcc12v_dcin: vcc12v-dcin {
+		u-boot,dm-pre-reloc;
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		u-boot,dm-pre-reloc;
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		u-boot,dm-pre-reloc;
+		status = "okay";
+
+		volumeup-key {
+			u-boot,dm-pre-reloc;
+			linux,code = <KEY_VOLUMEUP>;
+			label = "volume up";
+			press-threshold-microvolt = <1750>;
+		};
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&usb_host0_ohci {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&usb2phy2_grf {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&u2phy2 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&u2phy2_host {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&usb_host1_ehci {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&usb_host1_ohci {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&usb2phy3_grf {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&u2phy3 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&u2phy3_host {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&sfc {
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&fspim0_pins>;
+};
+
+&spi_nor {
+	status = "disabled";
+};
+
+&pinctrl {
+
+	/delete-node/ fspi;
+	fspi {
+		u-boot,dm-spl;
+		fspim0_pins: fspim0-pins {
+			u-boot,dm-spl;
+			rockchip,pins =
+				/* fspi_clk_m0 */
+				<2 RK_PA0 2 &pcfg_pull_none>,
+				/* fspi_cs0n_m0 */
+				<2 RK_PD6 2 &pcfg_pull_none>,
+				/* fspi_d0_m0 */
+				<2 RK_PD0 2 &pcfg_pull_none>,
+				/* fspi_d1_m0 */
+				<2 RK_PD1 2 &pcfg_pull_none>,
+				/* fspi_d2_m0 */
+				<2 RK_PD2 2 &pcfg_pull_none>,
+				/* fspi_d3_m0 */
+				<2 RK_PD3 2 &pcfg_pull_none>;
+		};
+	};
+};
diff --git a/patch/u-boot/u-boot-sunxi/arm64-sun50i-h313-add-x96q-lpddr3-defconfig.patch b/patch/u-boot/u-boot-sunxi/arm64-sun50i-h313-add-x96q-lpddr3-defconfig.patch
new file mode 100644
index 000000000000..a4b1eaf5fd86
--- /dev/null
+++ b/patch/u-boot/u-boot-sunxi/arm64-sun50i-h313-add-x96q-lpddr3-defconfig.patch
@@ -0,0 +1,241 @@
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -836,6 +836,7 @@
+ dtb-$(CONFIG_MACH_SUN50I_H616) += \
+ 	sun50i-h616-orangepi-zero2.dtb \
+ 	sun50i-h618-orangepi-zero3.dtb \
++	sun50i-h313-x96q-lpddr3.dtb \
+ 	sun50i-h616-x96-mate.dtb
+ 	
+ 
+diff --git a/configs/x96q_lpddr3_defconfig b/configs/x96q_lpddr3_defconfig
++ new file mode 100755
++ index 000000000..306157b84
++++ b/configs/x96q_lpddr3_defconfig
+@@ -0,0 +1,34 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h313-x96q-lpddr3"
++CONFIG_SPL=y
++CONFIG_SUNXI_DRAM_H616_LPDDR3=y
++CONFIG_DRAM_CLK=600
++CONFIG_DRAM_SUN50I_H616_DX_ODT=0x06060606
++CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0d0d0d0d
++CONFIG_DRAM_SUN50I_H616_CA_DRI=0x00000d0d
++CONFIG_DRAM_SUN50I_H616_ODT_EN=0x00000001
++CONFIG_DRAM_SUN50I_H616_TPR0=0x0
++CONFIG_DRAM_SUN50I_H616_TPR2=0x00000000
++CONFIG_DRAM_SUN50I_H616_TPR10=0x002f3359
++CONFIG_DRAM_SUN50I_H616_TPR11=0xaa889967
++CONFIG_DRAM_SUN50I_H616_TPR12=0xeeee8979
++CONFIG_MACH_SUN50I_H616=y
++CONFIG_R_I2C_ENABLE=y
++CONFIG_SPL_I2C=y
++CONFIG_SPL_I2C_SUPPORT=y
++CONFIG_SPL_SYS_I2C_LEGACY=y
++CONFIG_SYS_I2C_MVTWSI=y
++CONFIG_SYS_I2C_SLAVE=0x7f
++CONFIG_SYS_I2C_SPEED=100000
++CONFIG_SYS_MONITOR_LEN=786432
++CONFIG_PHY_REALTEK=y
++CONFIG_SUN8I_EMAC=y
++CONFIG_I2C3_ENABLE=y
++CONFIG_AXP313_POWER=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_MUSB_GADGET=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x40
++CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+
+diff --git a/arch/arm/dts/sun50i-h313-x96q-lpddr3.dts b/arch/arm/dts/sun50i-h313-x96q-lpddr3.dts
+new file mode 100644
+index 000000000..306157b84
+--- /dev/null
++++ b/arch/arm/dts/sun50i-h313-x96q-lpddr3.dts
+@@ -0,0 +1,181 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++//*
++//* Copyright (C) 2020 Arm Ltd.
++//*
++
++/dts-v1/;
++
++#include <sun50i-h616.dtsi>
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "X96Q TV-Box";
++	compatible = "x96q,tv-box", "allwinner,sun50i-h616";
++
++	aliases {
++		ethernet0 = &emac0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			function = LED_FUNCTION_POWER;
++			color = <LED_COLOR_ID_RED>;
++			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
++			default-state = "on";
++		};
++
++		led-1 {
++			function = LED_FUNCTION_STATUS;
++			color = <LED_COLOR_ID_GREEN>;
++			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_usb1_vbus: usb1-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb1-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&reg_vcc5v>;
++		enable-active-high;
++		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
++		status = "okay";
++	};
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++/* USB 2 & 3 are on headers only. */
++
++&emac0 {
++	status = "disabled";
++};
++
++&mmc0 {
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
++	bus-width = <4>;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&r_i2c {
++	status = "okay";
++
++	axp313a: pmic@36 {
++		compatible = "x-powers,axp313a";
++		status = "okay";
++		reg = <0x36>;
++		wakeup-source;
++
++		standby_param: standby_param {
++			vcc-dram = <0x4>;
++		};
++
++		regulators{
++			reg_dcdc1: dcdc1 {
++				regulator-name = "axp313a-dcdc1";
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <3400000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-name = "axp313a-dcdc2";
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1540000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-ramp-delay = <200>;
++				regulator-always-on;
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-name = "axp313a-dcdc3";
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_aldo1: aldo1 {
++				regulator-name = "axp313a-aldo1";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_dldo1: dldo1 {
++				regulator-name = "axp313a-dldo1";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++		};
++	};
++};
++
++&spi0  {
++	status = "okay";
++
++	flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <40000000>;
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&usbotg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_usb1_vbus>;
++	status = "okay";
++};
+ 	
+ 
+
diff --git a/patch/u-boot/u-boot-sunxi/board_bigtreetech-cb1/allwinner-h616-driver-i2c3.patch b/patch/u-boot/u-boot-sunxi/board_bigtreetech-cb1/allwinner-h616-driver-i2c3.patch
new file mode 100644
index 000000000000..1ed1015e47b7
--- /dev/null
+++ b/patch/u-boot/u-boot-sunxi/board_bigtreetech-cb1/allwinner-h616-driver-i2c3.patch
@@ -0,0 +1,92 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: JohnTheCoolingFan <ivan8215145640@gmail.com>
+Date: Fri, 9 Aug 2024 07:14:37 +0000
+Subject: Allwinner H616: driver: I2C3
+
+Signed-off-by: JohnTheCoolingFan <ivan8215145640@gmail.com>
+---
+ arch/arm/include/asm/arch-sunxi/i2c.h |  3 +
+ arch/arm/mach-sunxi/Kconfig           |  9 +++
+ board/sunxi/board.c                   | 12 +++++
+ 3 files changed, 24 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
+index f0da46d863c..98c26d7408e 100644
+--- a/arch/arm/include/asm/arch-sunxi/i2c.h
++++ b/arch/arm/include/asm/arch-sunxi/i2c.h
+@@ -11,10 +11,13 @@
+ #define CFG_I2C_MVTWSI_BASE0	SUNXI_TWI0_BASE
+ #endif
+ #ifdef CONFIG_I2C1_ENABLE
+ #define CFG_I2C_MVTWSI_BASE1	SUNXI_TWI1_BASE
+ #endif
++#ifdef CONFIG_I2C3_ENABLE
++#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE
++#endif
+ #ifdef CONFIG_R_I2C_ENABLE
+ #define CFG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
+ #endif
+ 
+ /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
+diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
+index d91faf9ab13..59cd48653c3 100644
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -807,10 +807,19 @@ config I2C1_ENABLE
+ 	bool "Enable I2C/TWI controller 1"
+ 	select CMD_I2C
+ 	---help---
+ 	See I2C0_ENABLE help text.
+ 
++if MACH_SUN50I_H616
++config I2C3_ENABLE
++	bool "Enable I2C/TWI controller 3"
++	default n
++	select CMD_I2C
++	---help---
++	See I2C0_ENABLE help text.
++endif
++
+ if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
+ config R_I2C_ENABLE
+ 	bool "Enable the PRCM I2C/TWI controller"
+ 	# This is used for the pmic on H3
+ 	default y if SY8106A_POWER
+diff --git a/board/sunxi/board.c b/board/sunxi/board.c
+index 2163fac5e06..302a927f524 100644
+--- a/board/sunxi/board.c
++++ b/board/sunxi/board.c
+@@ -13,10 +13,11 @@
+ #include <common.h>
+ #include <clock_legacy.h>
+ #include <dm.h>
+ #include <env.h>
+ #include <hang.h>
++#include <i2c.h>
+ #include <image.h>
+ #include <init.h>
+ #include <log.h>
+ #include <mmc.h>
+ #include <axp_pmic.h>
+@@ -107,10 +108,21 @@ void i2c_init_board(void)
+ 	sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
+ 	clock_twi_onoff(1, 1);
+ #endif
+ #endif
+ 
++#ifdef CONFIG_I2C3_ENABLE
++#if defined(CONFIG_MACH_SUN50I_H616)
++	sunxi_gpio_set_cfgpin(SUNXI_GPA(10), 2);
++	sunxi_gpio_set_cfgpin(SUNXI_GPA(11), 2);
++	sunxi_gpio_set_cfgpin(SUNXI_GPA(12), 2);
++	sunxi_gpio_set_pull(SUNXI_GPA(10), SUNXI_GPIO_PULL_UP);
++	sunxi_gpio_set_pull(SUNXI_GPA(11), SUNXI_GPIO_PULL_UP);
++	clock_twi_onoff(3, 1);
++#endif
++#endif
++
+ #ifdef CONFIG_R_I2C_ENABLE
+ #ifdef CONFIG_MACH_SUN50I
+ 	clock_twi_onoff(5, 1);
+ 	sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
+ 	sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
diff --git a/patch/u-boot/u-boot-sunxi/board_bigtreetech-cb1/allwinner-h616-dts-enable-internal-phy-emac1.patch b/patch/u-boot/u-boot-sunxi/board_bigtreetech-cb1/allwinner-h616-dts-enable-internal-phy-emac1.patch
new file mode 100644
index 000000000000..91cb865d331d
--- /dev/null
+++ b/patch/u-boot/u-boot-sunxi/board_bigtreetech-cb1/allwinner-h616-dts-enable-internal-phy-emac1.patch
@@ -0,0 +1,117 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: JohnTheCoolingFan <ivan8215145640@gmail.com>
+Date: Fri, 9 Aug 2024 07:14:37 +0000
+Subject: Allwinner H616 DTS: Enable internal PHY (EMAC1)
+
+Signed-off-by: JohnTheCoolingFan <ivan8215145640@gmail.com>
+---
+ arch/arm/dts/sun50i-h616.dtsi         | 27 +++++++++
+ drivers/net/sun8i_emac.c              |  7 +++
+ drivers/pinctrl/sunxi/pinctrl-sunxi.c |  1 +
+ 3 files changed, 35 insertions(+)
+
+diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi
+index 46651703e9b..87d62cb1d3f 100644
+--- a/arch/arm/dts/sun50i-h616.dtsi
++++ b/arch/arm/dts/sun50i-h616.dtsi
+@@ -207,10 +207,18 @@
+ 				function = "mmc2";
+ 				drive-strength = <40>;
+ 				bias-pull-up;
+ 			};
+ 
++	        /omit-if-no-ref/
++	        rmii_pins: rmii-pins {
++	            pins = "PA0", "PA1", "PA2", "PA3", "PA4",
++			   "PA5", "PA6", "PA7", "PA8", "PA9";
++	            function = "emac1";
++	            drive-strength = <40>;
++	        };
++
+ 			/omit-if-no-ref/
+ 			spi0_pins: spi0-pins {
+ 				pins = "PC0", "PC2", "PC4";
+ 				function = "spi0";
+ 			};
+@@ -502,10 +510,29 @@
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+ 			};
+ 		};
+ 
++		emac1: ethernet@5030000 {
++			compatible = "allwinner,sun50i-h616-emac1";
++			syscon = <&syscon 1>;
++			reg = <0x05030000 0x10000>;
++			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "macirq";
++			resets = <&ccu RST_BUS_EMAC1>;
++			reset-names = "stmmaceth";
++			clocks = <&ccu CLK_BUS_EMAC1>;
++			clock-names = "stmmaceth";
++			status = "disabled";
++
++			mdio1: mdio {
++				compatible = "snps,dwmac-mdio";
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++		};
++
+ 		usbotg: usb@5100000 {
+ 			compatible = "allwinner,sun50i-h616-musb",
+ 				     "allwinner,sun8i-h3-musb";
+ 			reg = <0x05100000 0x0400>;
+ 			clocks = <&ccu CLK_BUS_OTG>;
+diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
+index a12f7e32e8f..98804029719 100644
+--- a/drivers/net/sun8i_emac.c
++++ b/drivers/net/sun8i_emac.c
+@@ -904,10 +904,15 @@ static const struct emac_variant emac_variant_a64 = {
+ static const struct emac_variant emac_variant_h6 = {
+ 	.syscon_offset		= 0x30,
+ 	.support_rmii		= true,
+ };
+ 
++static const struct emac_variant emac_variant_h616_1 = {
++	.syscon_offset      = 0x34,
++	.support_rmii       = true,
++};
++
+ static const struct udevice_id sun8i_emac_eth_ids[] = {
+ 	{ .compatible = "allwinner,sun8i-a83t-emac",
+ 	  .data = (ulong)&emac_variant_a83t },
+ 	{ .compatible = "allwinner,sun8i-h3-emac",
+ 	  .data = (ulong)&emac_variant_h3 },
+@@ -915,10 +920,12 @@ static const struct udevice_id sun8i_emac_eth_ids[] = {
+ 	  .data = (ulong)&emac_variant_r40 },
+ 	{ .compatible = "allwinner,sun50i-a64-emac",
+ 	  .data = (ulong)&emac_variant_a64 },
+ 	{ .compatible = "allwinner,sun50i-h6-emac",
+ 	  .data = (ulong)&emac_variant_h6 },
++	{ .compatible = "allwinner,sun50i-h616-emac1",
++	  .data = (ulong)&emac_variant_h616_1 },
+ 	{ }
+ };
+ 
+ U_BOOT_DRIVER(eth_sun8i_emac) = {
+ 	.name   = "eth_sun8i_emac",
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+index 37ea93715d1..a9c3bf05702 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+@@ -735,10 +735,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc =
+ 	.num_banks	= 2,
+ };
+ 
+ static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
+ 	{ "emac0",	2 },	/* PI0-PI16 */
++	{ "emac1",  2 },    /* PA0-PA9 */
+ 	{ "gpio_in",	0 },
+ 	{ "gpio_out",	1 },
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC0-PC16 */
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+
diff --git a/patch/u-boot/u-boot-sunxi/board_bigtreetech-cb1/allwinner-h616-setup-internal-phy-emac1.patch b/patch/u-boot/u-boot-sunxi/board_bigtreetech-cb1/allwinner-h616-setup-internal-phy-emac1.patch
new file mode 100644
index 000000000000..b9dfe8b12ab4
--- /dev/null
+++ b/patch/u-boot/u-boot-sunxi/board_bigtreetech-cb1/allwinner-h616-setup-internal-phy-emac1.patch
@@ -0,0 +1,93 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: JohnTheCoolingFan <ivan8215145640@gmail.com>
+Date: Fri, 9 Aug 2024 07:14:37 +0000
+Subject: Allwinner H616: Setup internal PHY (EMAC1)
+
+Signed-off-by: JohnTheCoolingFan <ivan8215145640@gmail.com>
+---
+ arch/arm/mach-sunxi/board.c           |  1 +
+ arch/arm/mach-sunxi/clock_sun50i_h6.c |  4 ++
+ board/sunxi/board.c                   | 18 ++++++
+ drivers/net/sun8i_emac.c              |  7 +++
+ drivers/pinctrl/sunxi/pinctrl-sunxi.c |  1 +
+ 8 files changed, 82 insertions(+)
+
+diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
+index 7d2d5d478fc..ca084bddda0 100644
+--- a/arch/arm/mach-sunxi/board.c
++++ b/arch/arm/mach-sunxi/board.c
+@@ -479,10 +479,11 @@ void board_init_f(ulong dummy)
+ 
+ #if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
+ 	/* Needed early by sunxi_board_init if PMU is enabled */
+ 	i2c_init_board();
+ 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
++	i2c_set_bus_num(0);
+ #endif
+ 	sunxi_board_init();
+ }
+ #endif /* CONFIG_SPL_BUILD */
+ 
+diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
+index 7f60b8c79fc..8c97ddb66c4 100644
+--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
++++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
+@@ -51,10 +51,14 @@ void clock_init_safe(void)
+ 	/*
+ 	 * The mux and factor are set, but the clock will be enabled in
+ 	 * DRAM initialization code.
+ 	 */
+ 	writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
++
++	writel(0x10001, 0x030017ac);
++	writel(0x50, 0x0300a028);
++	writel(0x20, 0x0300a040);
+ }
+ #endif
+ 
+ void clock_init_uart(void)
+ {
+diff --git a/board/sunxi/board.c b/board/sunxi/board.c
+index 2163fac5e06..302a927f524 100644
+--- a/board/sunxi/board.c
++++ b/board/sunxi/board.c
+@@ -568,10 +580,11 @@ static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
+ }
+ 
+ void sunxi_board_init(void)
+ {
+ 	int power_failed = 0;
++	u8 data[2];
+ 
+ #ifdef CONFIG_LED_STATUS
+ 	if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
+ 		status_led_init();
+ #endif
+@@ -658,10 +671,27 @@ void sunxi_board_init(void)
+ 	 */
+ 	if (!power_failed)
+ 		clock_set_pll1(get_board_sys_clk());
+ 	else
+ 		printf("Failed to set core voltage! Can't set CPU frequency\n");
++
++	i2c_set_bus_num(1);
++	data[0] = 0;
++	data[1] = 1;
++	i2c_write(0x10, 0xfe, 1, data, 2);
++	i2c_write(0x10, 2, 1, data, 2);
++	data[1] = 1;
++	i2c_write(0x10, 2, 1, data, 2);
++	data[1] = 0xf;
++	i2c_write(0x10, 0x16, 1, data, 2);
++	data[1] = 3;
++	i2c_write(0x10, 0x14, 1, data, 2);
++	data[1] = 0x60;
++	i2c_write(0x10, 0xfe, 1, data, 2);
++	data[0] = 0x08;
++	data[1] = 0x14;
++	i2c_write(0x10, 0, 1, data, 2);
+ }
+ #endif /* CONFIG_SPL_BUILD */
+ 
+ #ifdef CONFIG_USB_GADGET
+ int g_dnl_board_usb_cable_connected(void)
diff --git a/patch/u-boot/u-boot-tqma/0003-imx-mkimage_fit_atf_imx8mp.sh-add-script-for-imx8mp.patch b/patch/u-boot/u-boot-tqma/0003-imx-mkimage_fit_atf_imx8mp.sh-add-script-for-imx8mp.patch
new file mode 100644
index 000000000000..a84b79232858
--- /dev/null
+++ b/patch/u-boot/u-boot-tqma/0003-imx-mkimage_fit_atf_imx8mp.sh-add-script-for-imx8mp.patch
@@ -0,0 +1,190 @@
+From 55a5f1cb804eba8065c8f959d71f334d7dc57eab Mon Sep 17 00:00:00 2001
+From: Martin Schmiedel <Martin.Schmiedel@tq-group.com>
+Date: Mon, 22 Jul 2024 07:48:26 +0200
+Subject: [PATCH] imx: mkimage_fit_atf_imx8mp.sh: add script for imx8mp
+
+If Varibles can not be exported this script set default value for ATF_LOAD_ADDR
+
+Signed-off-by: Martin Schmiedel <Martin.Schmiedel@tq-group.com>
+---
+ Makefile                                    |   2 +
+ arch/arm/mach-imx/mkimage_fit_atf_imx8mp.sh | 139 ++++++++++++++++++++
+ board/tqc/tqma8mpxl/Kconfig                 |   3 +
+ 3 files changed, 144 insertions(+)
+ create mode 100755 arch/arm/mach-imx/mkimage_fit_atf_imx8mp.sh
+
+diff --git a/Makefile b/Makefile
+index 312bb794c3..2d65bebd95 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1281,6 +1281,8 @@ ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
+ U_BOOT_ITS := u-boot.its
+ ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
+ U_BOOT_ITS_DEPS += u-boot-nodtb.bin
++else ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf_imx8mp.sh")
++U_BOOT_ITS_DEPS += u-boot-nodtb.bin
+ endif
+ ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
+ U_BOOT_ITS_DEPS += u-boot
+diff --git a/arch/arm/mach-imx/mkimage_fit_atf_imx8mp.sh b/arch/arm/mach-imx/mkimage_fit_atf_imx8mp.sh
+new file mode 100755
+index 0000000000..25031ce710
+--- /dev/null
++++ b/arch/arm/mach-imx/mkimage_fit_atf_imx8mp.sh
+@@ -0,0 +1,139 @@
++#!/bin/sh
++# SPDX-License-Identifier: GPL-2.0+
++#
++# script to generate FIT image source for i.MX8MQ boards with
++# ARM Trusted Firmware and multiple device trees (given on the command line)
++#
++# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
++[ -z "$BL31" ] && BL31="bl31.bin"
++[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
++[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00970000"
++[ -z "$BL33_LOAD_ADDR" ] && BL33_LOAD_ADDR="0x40200000"
++
++if [ ! -f $BL31 ]; then
++	echo "ERROR: BL31 file $BL31 NOT found" >&2
++	exit 0
++else
++	echo "$BL31 size: " >&2
++	ls -lct $BL31 | awk '{print $5}' >&2
++fi
++
++BL32="tee.bin"
++
++if [ ! -f $BL32 ]; then
++	BL32=/dev/null
++else
++	echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
++	echo "$BL32 size: " >&2
++	ls -lct $BL32 | awk '{print $5}' >&2
++fi
++
++BL33="u-boot-nodtb.bin"
++
++if [ ! -f $BL33 ]; then
++	echo "ERROR: $BL33 file NOT found" >&2
++	exit 0
++else
++	echo "u-boot-nodtb.bin size: " >&2
++	ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2
++fi
++
++for dtname in $*
++do
++	echo "$dtname size: " >&2
++	ls -lct $dtname | awk '{print $5}' >&2
++done
++
++
++cat << __HEADER_EOF
++/dts-v1/;
++
++/ {
++	description = "Configuration to load ATF before U-Boot";
++
++	images {
++		uboot@1 {
++			description = "U-Boot (64-bit)";
++			os = "u-boot";
++			data = /incbin/("$BL33");
++			type = "standalone";
++			arch = "arm64";
++			compression = "none";
++			load = <$BL33_LOAD_ADDR>;
++		};
++		atf@1 {
++			description = "ARM Trusted Firmware";
++			os = "arm-trusted-firmware";
++			data = /incbin/("$BL31");
++			type = "firmware";
++			arch = "arm64";
++			compression = "none";
++			load = <$ATF_LOAD_ADDR>;
++			entry = <$ATF_LOAD_ADDR>;
++		};
++__HEADER_EOF
++
++if [ -f $BL32 ]; then
++cat << __HEADER_EOF
++		tee@1 {
++			description = "TEE firmware";
++			data = /incbin/("$BL32");
++			type = "firmware";
++			arch = "arm64";
++			compression = "none";
++			load = <$TEE_LOAD_ADDR>;
++			entry = <$TEE_LOAD_ADDR>;
++		};
++__HEADER_EOF
++fi
++
++cnt=1
++for dtname in $*
++do
++	cat << __FDT_IMAGE_EOF
++		fdt@$cnt {
++			description = "$(basename $dtname .dtb)";
++			data = /incbin/("$dtname");
++			type = "flat_dt";
++			compression = "none";
++		};
++__FDT_IMAGE_EOF
++cnt=$((cnt+1))
++done
++
++cat << __CONF_HEADER_EOF
++	};
++	configurations {
++		default = "config@1";
++
++__CONF_HEADER_EOF
++
++cnt=1
++for dtname in $*
++do
++if [ -f $BL32 ]; then
++cat << __CONF_SECTION_EOF
++		config@$cnt {
++			description = "$(basename $dtname .dtb)";
++			firmware = "uboot@1";
++			loadables = "atf@1", "tee@1";
++			fdt = "fdt@$cnt";
++		};
++__CONF_SECTION_EOF
++else
++cat << __CONF_SECTION1_EOF
++		config@$cnt {
++			description = "$(basename $dtname .dtb)";
++			firmware = "uboot@1";
++			loadables = "atf@1";
++			fdt = "fdt@$cnt";
++		};
++__CONF_SECTION1_EOF
++fi
++cnt=$((cnt+1))
++done
++
++cat << __ITS_EOF
++	};
++};
++__ITS_EOF
+diff --git a/board/tqc/tqma8mpxl/Kconfig b/board/tqc/tqma8mpxl/Kconfig
+index 19e5d5030f..a8bd61246f 100644
+--- a/board/tqc/tqma8mpxl/Kconfig
++++ b/board/tqc/tqma8mpxl/Kconfig
+@@ -15,6 +15,9 @@ config SPL_TEXT_BASE
+ config CSF_SIZE
+ 	default 0x2000
+ 
++config SPL_FIT_GENERATOR
++	default "arch/arm/mach-imx/mkimage_fit_atf_imx8mp.sh"
++
+ config TQMA8MPXL_DEFAULTS
+ 	bool
+ 	default y
+-- 
+2.34.1
+
diff --git a/patch/u-boot/v2024.04/board_gateway-gz80x/001-Add-board-Amper-Gateway-AM-GZ80x.patch b/patch/u-boot/v2024.04/board_gateway-gz80x/001-Add-board-Amper-Gateway-AM-GZ80x.patch
new file mode 100644
index 000000000000..0c9720a38b1e
--- /dev/null
+++ b/patch/u-boot/v2024.04/board_gateway-gz80x/001-Add-board-Amper-Gateway-AM-GZ80x.patch
@@ -0,0 +1,215 @@
+From 7e431409a7c34b844b27c0bfa89fe582f4093dc7 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@armbian.com>
+Date: Tue, 13 Aug 2024 07:13:24 -0400
+Subject: [PATCH] Add board Amper Gateway AM-GZ80X
+
+Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
+---
+ arch/arm/dts/Makefile                         |  1 +
+ ...-axg-amper-gateway-am-gz80x-u-boot.dtsi | 10 +++
+ .../meson-axg-amper-gateway-am-gz80x.dts   | 87 +++++++++++++++++++
+ configs/amper_gateway_gz80x_defconfig   | 69 +++++++++++++++
+ 4 files changed, 167 insertions(+)
+ create mode 100644 arch/arm/dts/meson-axg-amper-gateway-am-gz80x-u-boot.dtsi
+ create mode 100644 arch/arm/dts/meson-axg-amper-gateway-am-gz80x.dts
+ create mode 100644 configs/amper_gateway_am-gz80x_defconfig
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index b102ffb5f6..da81b57aec 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -215,6 +215,7 @@ dtb-$(CONFIG_ARCH_S5P4418) += \
+ dtb-$(CONFIG_ARCH_MESON) += \
+ 	meson-a1-ad401.dtb \
+ 	meson-axg-s400.dtb \
++	meson-axg-amper-gateway-am-gz80x.dtb \
+ 	meson-axg-jethome-jethub-j100.dtb \
+ 	meson-gxbb-kii-pro.dtb \
+ 	meson-gxbb-nanopi-k2.dtb \
+diff --git a/arch/arm/dts/meson-axg-amper-gateway-am-gz80x-u-boot.dtsi b/arch/arm/dts/meson-axg-amper-gateway-am-gz80x-u-boot.dtsi
+new file mode 100644
+index 0000000000..ca380fdb4c
+--- /dev/null
++++ b/arch/arm/dts/meson-axg-amper-gateway-am-gz80x-u-boot.dtsi
+@@ -0,0 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2024 Patrick Yavitz <pyavitz@armbian.com>
++ *
++ */
++
++&saradc {
++	status = "okay";
++	vref-supply = <&vddio_ao18>;
++};
+diff --git a/arch/arm/dts/meson-axg-amper-gateway-am-gz80x.dts b/arch/arm/dts/meson-axg-amper-gateway-am-gz80x.dts
+new file mode 100644
+index 0000000000..3606121039
+--- /dev/null
++++ b/arch/arm/dts/meson-axg-amper-gateway-am-gz80x.dts
+@@ -0,0 +1,87 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2024 Patrick Yavitz <pyavitz@armbian.com>
++ *
++ */
++
++/dts-v1/;
++
++#include "meson-axg-jethome-jethub-j100.dts"
++#include <dt-bindings/leds/common.h>
++
++/ {
++	compatible = "amper,gateway-am-gz80x", "amlogic,a113x", "amlogic,meson-axg";
++	model = "Amper Gateway AM-GZ80x";
++
++	aliases {
++		serial0 = &uart_AO;
++		serial1 = &uart_B;
++		serial2 = &uart_AO_B;
++		ethernet0 = &ethmac;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-blue {
++			color = <LED_COLOR_ID_BLUE>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "default-on";
++		};
++
++		led-green {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "mmc1";
++		};
++
++		led-red {
++			color = <LED_COLOR_ID_RED>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "usb-host";
++		};
++ 	};
++
++	/* 1024MB RAM */
++	memory@0 {
++		device_type = "memory";
++		reg = <0x0 0x0 0x0 0x40000000>;
++	};
++};
++
++/delete-node/ &i2c1;
++
++/* wifi module */
++&sd_emmc_b {
++	non-removable;
++
++	rtl8189ftv: wifi@1 {
++		reg = <1>;
++	};
++};
++
++&uart_B {
++	status = "okay";
++	pinctrl-0 = <&uart_b_z_pins>;
++	pinctrl-names = "default";
++};
++
++/* UART Wireless module */
++&uart_AO_B {
++	status = "okay";
++	pinctrl-0 = <&uart_ao_b_z_pins>;
++	pinctrl-names = "default";
++	reset-gpios = <&gpio GPIOZ_6 GPIO_ACTIVE_HIGH>;
++};
++
++&usb_pwr {
++	gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
++	enable-active-high;
++};
+diff --git a/configs/amper_gateway_am-gz80x_defconfig b/configs/amper_gateway_am-gz80x_defconfig
+new file mode 100644
+index 0000000000..1bdefc0add
+--- /dev/null
++++ b/configs/amper_gateway_am-gz80x_defconfig
+@@ -0,0 +1,69 @@
++CONFIG_ARM=y
++CONFIG_ARCH_MESON=y
++CONFIG_TEXT_BASE=0x01000000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
++CONFIG_ENV_SIZE=0x2000
++CONFIG_DM_GPIO=y
++CONFIG_DEFAULT_DEVICE_TREE="meson-axg-amper-gateway-am-gz80x"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_DM_RESET=y
++CONFIG_MESON_AXG=y
++CONFIG_DEBUG_UART_BASE=0xff803000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_IDENT_STRING=" gateway-am-gz80x"
++CONFIG_SYS_LOAD_ADDR=0x01000000
++CONFIG_DEBUG_UART=y
++CONFIG_REMAKE_ELF=y
++CONFIG_SD_BOOT=y
++CONFIG_OF_BOARD_SETUP=y
++CONFIG_USE_PREBOOT=y
++CONFIG_PREBOOT="usb start"
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_MISC_INIT_R=y
++CONFIG_SYS_MAXARGS=32
++# CONFIG_CMD_BDI is not set
++# CONFIG_CMD_IMI is not set
++CONFIG_CMD_EEPROM=y
++CONFIG_CMD_ADC=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_I2C=y
++# CONFIG_CMD_LOADS is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_USB_MASS_STORAGE=y
++CONFIG_CMD_REGULATOR=y
++CONFIG_CMD_BTRFS=y
++CONFIG_PARTITION_TYPE_GUID=y
++CONFIG_OF_CONTROL=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_SARADC_MESON=y
++CONFIG_DM_I2C=y
++CONFIG_SYS_I2C_MESON=y
++CONFIG_MMC_MESON_GX=y
++CONFIG_PHY_REALTEK=y
++CONFIG_ETH_DESIGNWARE_MESON8B=y
++CONFIG_MESON_GXL_USB_PHY=y
++CONFIG_PINCTRL=y
++CONFIG_PINCTRL_MESON_AXG=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DEBUG_UART_ANNOUNCE=y
++CONFIG_DEBUG_UART_SKIP_INIT=y
++CONFIG_MESON_SERIAL=y
++CONFIG_USB=y
++CONFIG_DM_USB_GADGET=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_GADGET is not set
++CONFIG_USB_DWC3_MESON_GXL=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
++CONFIG_USB_GADGET_DWC2_OTG=y
++CONFIG_USB_GADGET_DOWNLOAD=y
++CONFIG_EXT4_WRITE=y
++CONFIG_RANDOM_UUID=y
+-- 
+2.39.2
+
diff --git a/patch/u-boot/v2024.04/board_gateway-gz80x/002-HACK-mmc-meson-gx-limit-to-24MHz.patch b/patch/u-boot/v2024.04/board_gateway-gz80x/002-HACK-mmc-meson-gx-limit-to-24MHz.patch
new file mode 100644
index 000000000000..43cd435b143d
--- /dev/null
+++ b/patch/u-boot/v2024.04/board_gateway-gz80x/002-HACK-mmc-meson-gx-limit-to-24MHz.patch
@@ -0,0 +1,26 @@
+From 24ba56015b1ce831639f482d26aeec11ac523906 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Mon, 2 Sep 2019 15:42:04 +0200
+Subject: [PATCH 1/8] HACK: mmc: meson-gx: limit to 24MHz
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/mmc/meson_gx_mmc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
+index fcf4f03d1e2..6ded4b619bf 100644
+--- a/drivers/mmc/meson_gx_mmc.c
++++ b/drivers/mmc/meson_gx_mmc.c
+@@ -279,7 +279,7 @@ static int meson_mmc_probe(struct udevice *dev)
+ 	cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
+ 			MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ 	cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
+-	cfg->f_max = 100000000; /* 100 MHz */
++	cfg->f_max = SD_EMMC_CLKSRC_24M;
+ 	cfg->b_max = 511; /* max 512 - 1 blocks */
+ 	cfg->name = dev->name;
+ 
+-- 
+2.43.2
+
diff --git a/patch/u-boot/v2024.04/board_gateway-gz80x/003-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch b/patch/u-boot/v2024.04/board_gateway-gz80x/003-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch
new file mode 100644
index 000000000000..4e69e92372fb
--- /dev/null
+++ b/patch/u-boot/v2024.04/board_gateway-gz80x/003-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch
@@ -0,0 +1,54 @@
+From d2c54d518b8b3f362a8395d2a81a2e7cef7a1ae0 Mon Sep 17 00:00:00 2001
+From: Vyacheslav Bocharov <adeep@lexina.in>
+Date: Thu, 2 Dec 2021 13:10:24 +0300
+Subject: [PATCH 2/8] mmc: meson-gx: change clock phase value on axg SoCs
+
+Amlogic AXG SoCs seems doesn't work over 50MHz. When phase sets to 270',
+it's working fine over 50MHz on Amlogic AXG SoCs.
+Based on 0dbb54eb3257c243c7968f967a6b183b1edb56c8 by Neil Armstrong
+<narmstrong@baylibre.com>
+
+To distinguish which value is used adds an u-boot only axg compatible.
+---
+ drivers/mmc/meson_gx_mmc.c | 5 +++--
+ drivers/mmc/meson_gx_mmc.h | 1 +
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
+index 6ded4b619bf..5e32c386caa 100644
+--- a/drivers/mmc/meson_gx_mmc.c
++++ b/drivers/mmc/meson_gx_mmc.c
+@@ -68,7 +68,8 @@ static void meson_mmc_config_clock(struct mmc *mmc)
+ 	 * Other SoCs use CLK_CO_PHASE_180 by default.
+ 	 * It needs to find what is a proper value about each SoCs.
+ 	 */
+-	if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
++	if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1) ||
++            meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_AXG))
+ 		meson_mmc_clk |= CLK_CO_PHASE_270;
+ 	else
+ 		meson_mmc_clk |= CLK_CO_PHASE_180;
+@@ -322,7 +323,7 @@ int meson_mmc_bind(struct udevice *dev)
+ 
+ static const struct udevice_id meson_mmc_match[] = {
+ 	{ .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
+-	{ .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
++	{ .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_AXG },
+ 	{ .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
+ 	{ /* sentinel */ }
+ };
+diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h
+index 8974b78f559..53201ceddae 100644
+--- a/drivers/mmc/meson_gx_mmc.h
++++ b/drivers/mmc/meson_gx_mmc.h
+@@ -12,6 +12,7 @@
+ enum meson_gx_mmc_compatible {
+ 	MMC_COMPATIBLE_GX,
+ 	MMC_COMPATIBLE_SM1,
++	MMC_COMPATIBLE_AXG,
+ };
+ 
+ #define SDIO_PORT_A			0
+-- 
+2.43.2
+
diff --git a/patch/u-boot/v2024.04/board_gateway-gz80x/004-HACK-meson64-boot-target-usb.patch b/patch/u-boot/v2024.04/board_gateway-gz80x/004-HACK-meson64-boot-target-usb.patch
new file mode 100644
index 000000000000..4a2fd3525460
--- /dev/null
+++ b/patch/u-boot/v2024.04/board_gateway-gz80x/004-HACK-meson64-boot-target-usb.patch
@@ -0,0 +1,29 @@
+From 4af333376c257d432f641926d74c762921186b78 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@armbian.com>
+Date: Sat, 27 Jan 2024 22:57:03 -0500
+Subject: [PATCH] HACK: meson64 boot target usb
+
+Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
+---
+ include/configs/meson64.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/configs/meson64.h b/include/configs/meson64.h
+index efab9a624d..ae1b79da0f 100644
+--- a/include/configs/meson64.h
++++ b/include/configs/meson64.h
+@@ -99,10 +99,10 @@
+ #define BOOT_TARGET_DEVICES(func) \
+ 	func(ROMUSB, romusb, na)  \
+ 	func(USB_DFU, usbdfu, na)  \
++	BOOT_TARGET_DEVICES_USB(func) \
+ 	func(MMC, mmc, 0) \
+ 	func(MMC, mmc, 1) \
+ 	func(MMC, mmc, 2) \
+-	BOOT_TARGET_DEVICES_USB(func) \
+ 	BOOT_TARGET_NVME(func) \
+ 	BOOT_TARGET_SCSI(func) \
+ 	func(PXE, pxe, na) \
+-- 
+2.39.2
+
diff --git a/patch/u-boot/v2024.07/0050-automatically-add-chosen-kaslr-seed-and-deduplicate-code.patch b/patch/u-boot/v2024.07/0050-automatically-add-chosen-kaslr-seed-and-deduplicate-code.patch
new file mode 100644
index 000000000000..f413e9285573
--- /dev/null
+++ b/patch/u-boot/v2024.07/0050-automatically-add-chosen-kaslr-seed-and-deduplicate-code.patch
@@ -0,0 +1,543 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Tue, 18 Jun 2024 14:06:06 -0700
+Subject: Add fdt_kaslrseed function to add kaslr-seed to chosen node
+
+If RANDOMIZE_BASE is enabled in the Linux kernel instructing it to
+randomize the virtual address at which the kernel image is loaded, it
+expects entropy to be provided by the bootloader by populating
+/chosen/kaslr-seed with a 64-bit value from source of entropy at boot.
+
+Add a fdt_kaslrseed function to accommodate this allowing an existing
+node to be overwritten if present. For now use the first rng device
+but it would be good to enhance this in the future to allow some sort
+of selection or policy in choosing the rng device used.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Reviewed-by: Simon Glass <sjg@chromium.org>
+Cc: Michal Simek <michal.simek@amd.com>
+Cc: Andy Yan <andy.yan@rock-chips.com>
+Cc: Akash Gajjar <gajjar04akash@gmail.com>
+Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Cc: Simon Glass <sjg@chromium.org>
+Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Cc: Patrice Chotard <patrice.chotard@foss.st.com>
+Cc: Devarsh Thakkar <devarsht@ti.com>
+Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
+Cc: Hugo Villeneuve <hvilleneuve@dimonoff.com>
+Cc: Marek Vasut <marex@denx.de>
+Cc: Tom Rini <trini@konsulko.com>
+Cc: Chris Morgan <macromorgan@hotmail.com>
+Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
+---
+v6:
+ - collected tags
+v5:
+ - move function to boot/fdt_support.c
+ - remove ability to select rng index and note in the commit log
+   something like this as a future enhancement.
+ - fixed typo in commit message s/it's/its/
+ - use cmd_process_error per Michal's suggestion
+v4:
+ - add missing /n to notice in kaslrseed cmd
+ - combine ints in declaration
+ - remove unused vars from board/xilinx/common/board.c ft_board_setup
+v3:
+ - skip if CONFIG_MEASURED_BOOT
+ - fix skip for CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+ - pass in rng index and bool to specify overwrite
+ - remove duplicate error strings printed outside of fdt_kaslrseed
+ - added note to commit log about how EFI STUB weeds out kalsr-seed
+v2:
+ - fix typo in commit msg
+ - use stack for seed to avoid unecessary malloc/free
+ - move to a library function and deduplicate code by using it
+   elsewhere
+---
+ boot/fdt_support.c    | 44 ++++++++++
+ include/fdt_support.h | 10 +++
+ 2 files changed, 54 insertions(+)
+
+diff --git a/boot/fdt_support.c b/boot/fdt_support.c
+index 111111111111..222222222222 100644
+--- a/boot/fdt_support.c
++++ b/boot/fdt_support.c
+@@ -7,12 +7,15 @@
+  */
+ 
+ #include <common.h>
++#include <dm.h>
+ #include <abuf.h>
+ #include <env.h>
+ #include <log.h>
+ #include <mapmem.h>
+ #include <net.h>
++#include <rng.h>
+ #include <stdio_dev.h>
++#include <dm/device_compat.h>
+ #include <dm/ofnode.h>
+ #include <linux/ctype.h>
+ #include <linux/types.h>
+@@ -274,6 +277,47 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end)
+ 	return 0;
+ }
+ 
++int fdt_kaslrseed(void *fdt, bool overwrite)
++{
++	int len, err, nodeoffset;
++	struct udevice *dev;
++	const u64 *orig;
++	u64 data = 0;
++
++	err = fdt_check_header(fdt);
++	if (err < 0)
++		return err;
++
++	/* find or create "/chosen" node. */
++	nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
++	if (nodeoffset < 0)
++		return nodeoffset;
++
++	/* return without error if we are not overwriting and existing non-zero node */
++	orig = fdt_getprop(fdt, nodeoffset, "kaslr-seed", &len);
++	if (orig && len == sizeof(*orig))
++		data = fdt64_to_cpu(*orig);
++	if (data && !overwrite) {
++		debug("not overwriting existing kaslr-seed\n");
++		return 0;
++	}
++	err = uclass_get_device(UCLASS_RNG, 0, &dev);
++	if (err) {
++		printf("No RNG device\n");
++		return err;
++	}
++	err = dm_rng_read(dev, &data, sizeof(data));
++	if (err) {
++		dev_err(dev, "dm_rng_read failed: %d\n", err);
++		return err;
++	}
++	err = fdt_setprop(fdt, nodeoffset, "kaslr-seed", &data, sizeof(data));
++	if (err < 0)
++		printf("WARNING: could not set kaslr-seed %s.\n", fdt_strerror(err));
++
++	return err;
++}
++
+ /**
+  * board_fdt_chosen_bootargs - boards may override this function to use
+  *                             alternative kernel command line arguments
+diff --git a/include/fdt_support.h b/include/fdt_support.h
+index 111111111111..222222222222 100644
+--- a/include/fdt_support.h
++++ b/include/fdt_support.h
+@@ -463,4 +463,14 @@ void fdt_fixup_board_enet(void *blob);
+ #ifdef CONFIG_CMD_PSTORE
+ void fdt_fixup_pstore(void *blob);
+ #endif
++
++/**
++ * fdt_kaslrseed() - create a 'kaslr-seed' node in chosen
++ *
++ * @blob:	fdt blob
++ * @overwrite:	do not overwrite existing non-zero node unless true
++ * Return:	0 if OK, -ve on error
++ */
++int fdt_kaslrseed(void *blob, bool overwrite);
++
+ #endif /* ifndef __FDT_SUPPORT_H */
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Tue, 18 Jun 2024 14:06:07 -0700
+Subject: fdt: automatically add /chosen/kaslr-seed if DM_RNG is enabled
+
+If RANDOMIZE_BASE is enabled in the Linux kernel instructing it to
+randomize the virtual address at which the kernel image is loaded, it
+expects entropy to be provided by the bootloader by populating
+/chosen/kaslr-seed with a 64-bit value from source of entropy at boot.
+
+If we have DM_RNG enabled populate this value automatically when
+fdt_chosen is called. We skip this if ARMV8_SEC_FIRMWARE_SUPPORT
+is enabled as its implementation uses a different source of entropy
+that is not yet implemented as DM_RNG. We also skip this if
+MEASURED_BOOT is enabled as in that case any modifications to the
+dt will cause measured boot to fail (although there are many other
+places the dt is altered).
+
+Note that the Kernel's EFI STUB only relies on EFI_RNG_PROTOCOL for
+randomization and completely ignores the kaslr-seed for its own
+randomness needs (i.e the randomization of the physical placement of
+the kernel). It gets weeded out from the DTB that gets handed over via
+efi_install_fdt() as it would also mess up the measured boot DTB TPM
+measurements as well.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Reviewed-by: Simon Glass <sjg@chromium.org>
+Cc: Michal Simek <michal.simek@amd.com>
+Cc: Andy Yan <andy.yan@rock-chips.com>
+Cc: Akash Gajjar <gajjar04akash@gmail.com>
+Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Cc: Simon Glass <sjg@chromium.org>
+Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Cc: Patrice Chotard <patrice.chotard@foss.st.com>
+Cc: Devarsh Thakkar <devarsht@ti.com>
+Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
+Cc: Hugo Villeneuve <hvilleneuve@dimonoff.com>
+Cc: Marek Vasut <marex@denx.de>
+Cc: Tom Rini <trini@konsulko.com>
+Cc: Chris Morgan <macromorgan@hotmail.com>
+---
+v6:
+ - collected tags
+v5:
+ - fixed typo in commit message s/it's/its/
+ - split patch into 3 parts
+v4:
+ - add missing /n to notice in kaslrseed cmd
+ - combine ints in declaration
+ - remove unused vars from board/xilinx/common/board.c ft_board_setup
+v3:
+ - skip if CONFIG_MEASURED_BOOT
+ - fix skip for CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+ - pass in rng index and bool to specify overwrite
+ - remove duplicate error strings printed outside of fdt_kaslrseed
+ - added note to commit log about how EFI STUB weeds out kalsr-seed
+v2:
+ - fix typo in commit msg
+ - use stack for seed to avoid unecessary malloc/free
+ - move to a library function and deduplicate code by using it
+   elsewhere
+---
+ boot/fdt_support.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/boot/fdt_support.c b/boot/fdt_support.c
+index 111111111111..222222222222 100644
+--- a/boot/fdt_support.c
++++ b/boot/fdt_support.c
+@@ -345,6 +345,15 @@ int fdt_chosen(void *fdt)
+ 	if (nodeoffset < 0)
+ 		return nodeoffset;
+ 
++	/* if DM_RNG enabled automatically inject kaslr-seed node unless:
++	 * CONFIG_MEASURED_BOOT enabled: as dt modifications break measured boot
++	 * CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT enabled: as that implementation does not use dm yet
++	 */
++	if (IS_ENABLED(CONFIG_DM_RNG) &&
++	    !IS_ENABLED(CONFIG_MEASURED_BOOT) &&
++	    !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT))
++		fdt_kaslrseed(fdt, false);
++
+ 	if (IS_ENABLED(CONFIG_BOARD_RNG_SEED) && !board_rng_seed(&buf)) {
+ 		err = fdt_setprop(fdt, nodeoffset, "rng-seed",
+ 				  abuf_data(&buf), abuf_size(&buf));
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Tue, 18 Jun 2024 14:06:08 -0700
+Subject: use fdt_kaslrseed function to de-duplicate code
+
+Use the fdt_kaslrseed function to deduplicate code doing the same thing.
+
+Note that the kalsrseed command (CMD_KASLRSEED) is likely pointless now
+but left in place in case boot scripts exist that rely on this command
+existing and returning success. An informational message is printed to
+alert users of this command that it is likely no longer needed.
+
+Note that the Kernel's EFI STUB only relies on EFI_RNG_PROTOCOL for
+randomization and completely ignores the kaslr-seed for its own
+randomness needs (i.e the randomization of the physical placement of
+the kernel). It gets weeded out from the DTB that gets handed over via
+efi_install_fdt() as it would also mess up the measured boot DTB TPM
+measurements as well.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Reviewed-by: Simon Glass <sjg@chromium.org>
+Cc: Michal Simek <michal.simek@amd.com>
+Cc: Andy Yan <andy.yan@rock-chips.com>
+Cc: Akash Gajjar <gajjar04akash@gmail.com>
+Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Cc: Simon Glass <sjg@chromium.org>
+Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Cc: Patrice Chotard <patrice.chotard@foss.st.com>
+Cc: Devarsh Thakkar <devarsht@ti.com>
+Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
+Cc: Hugo Villeneuve <hvilleneuve@dimonoff.com>
+Cc: Marek Vasut <marex@denx.de>
+Cc: Tom Rini <trini@konsulko.com>
+Cc: Chris Morgan <macromorgan@hotmail.com>
+Acked-by: Michal Simek <michal.simek@amd.com>
+---
+v6:
+ - collected tags
+v5:
+ - fixed typo in commit message s/it's/its/
+ - use cmd_process_error per Michal's suggestion
+v4:
+ - add missing /n to notice in kaslrseed cmd
+ - combine ints in declaration
+ - remove unused vars from board/xilinx/common/board.c ft_board_setup
+v3:
+ - skip if CONFIG_MEASURED_BOOT
+ - fix skip for CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+ - pass in rng index and bool to specify overwrite
+ - remove duplicate error strings printed outside of fdt_kaslrseed
+ - added note to commit log about how EFI STUB weeds out kalsr-seed
+v2:
+ - fix typo in commit msg
+ - use stack for seed to avoid unecessary malloc/free
+ - move to a library function and deduplicate code by using it
+   elsewhere
+---
+ board/xilinx/common/board.c | 40 --------
+ boot/pxe_utils.c            | 34 +------
+ cmd/kaslrseed.c             | 49 ++--------
+ 3 files changed, 8 insertions(+), 115 deletions(-)
+
+diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
+index 111111111111..222222222222 100644
+--- a/board/xilinx/common/board.c
++++ b/board/xilinx/common/board.c
+@@ -702,11 +702,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+ #define MAX_RAND_SIZE 8
+ int ft_board_setup(void *blob, struct bd_info *bd)
+ {
+-	size_t n = MAX_RAND_SIZE;
+-	struct udevice *dev;
+-	u8 buf[MAX_RAND_SIZE];
+-	int nodeoffset, ret;
+-
+ 	static const struct node_info nodes[] = {
+ 		{ "arm,pl353-nand-r2p1", MTD_DEV_TYPE_NAND, },
+ 	};
+@@ -714,41 +709,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
+ 	if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS) && IS_ENABLED(CONFIG_NAND_ZYNQ))
+ 		fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ 
+-	if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
+-		debug("No RNG device\n");
+-		return 0;
+-	}
+-
+-	if (dm_rng_read(dev, buf, n)) {
+-		debug("Reading RNG failed\n");
+-		return 0;
+-	}
+-
+-	if (!blob) {
+-		debug("No FDT memory address configured. Please configure\n"
+-		      "the FDT address via \"fdt addr <address>\" command.\n"
+-		      "Aborting!\n");
+-		return 0;
+-	}
+-
+-	ret = fdt_check_header(blob);
+-	if (ret < 0) {
+-		debug("fdt_chosen: %s\n", fdt_strerror(ret));
+-		return ret;
+-	}
+-
+-	nodeoffset = fdt_find_or_add_subnode(blob, 0, "chosen");
+-	if (nodeoffset < 0) {
+-		debug("Reading chosen node failed\n");
+-		return nodeoffset;
+-	}
+-
+-	ret = fdt_setprop(blob, nodeoffset, "kaslr-seed", buf, sizeof(buf));
+-	if (ret < 0) {
+-		debug("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret));
+-		return ret;
+-	}
+-
+ 	return 0;
+ }
+ #endif
+diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
+index 111111111111..222222222222 100644
+--- a/boot/pxe_utils.c
++++ b/boot/pxe_utils.c
+@@ -324,10 +324,6 @@ static void label_boot_kaslrseed(void)
+ #if CONFIG_IS_ENABLED(DM_RNG)
+ 	ulong fdt_addr;
+ 	struct fdt_header *working_fdt;
+-	size_t n = 0x8;
+-	struct udevice *dev;
+-	u64 *buf;
+-	int nodeoffset;
+ 	int err;
+ 
+ 	/* Get the main fdt and map it */
+@@ -343,35 +339,7 @@ static void label_boot_kaslrseed(void)
+ 	if (err <= 0)
+ 		return;
+ 
+-	if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
+-		printf("No RNG device\n");
+-		return;
+-	}
+-
+-	nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen");
+-	if (nodeoffset < 0) {
+-		printf("Reading chosen node failed\n");
+-		return;
+-	}
+-
+-	buf = malloc(n);
+-	if (!buf) {
+-		printf("Out of memory\n");
+-		return;
+-	}
+-
+-	if (dm_rng_read(dev, buf, n)) {
+-		printf("Reading RNG failed\n");
+-		goto err;
+-	}
+-
+-	err = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf));
+-	if (err < 0) {
+-		printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(err));
+-		goto err;
+-	}
+-err:
+-	free(buf);
++	fdt_kaslrseed(working_fdt, true);
+ #endif
+ 	return;
+ }
+diff --git a/cmd/kaslrseed.c b/cmd/kaslrseed.c
+index 111111111111..222222222222 100644
+--- a/cmd/kaslrseed.c
++++ b/cmd/kaslrseed.c
+@@ -16,56 +16,21 @@
+ 
+ static int do_kaslr_seed(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+ {
+-	size_t n = 0x8;
+-	struct udevice *dev;
+-	u64 *buf;
+-	int nodeoffset;
+-	int ret = CMD_RET_SUCCESS;
++	int err = CMD_RET_SUCCESS;
+ 
+-	if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
+-		printf("No RNG device\n");
+-		return CMD_RET_FAILURE;
+-	}
+-
+-	buf = malloc(n);
+-	if (!buf) {
+-		printf("Out of memory\n");
+-		return CMD_RET_FAILURE;
+-	}
+-
+-	if (dm_rng_read(dev, buf, n)) {
+-		printf("Reading RNG failed\n");
+-		return CMD_RET_FAILURE;
+-	}
++	printf("Notice: a /chosen/kaslr-seed is automatically added to the device-tree when booted via booti/bootm/bootz therefore using this command is likely no longer needed\n");
+ 
+ 	if (!working_fdt) {
+ 		printf("No FDT memory address configured. Please configure\n"
+ 		       "the FDT address via \"fdt addr <address>\" command.\n"
+ 		       "Aborting!\n");
+-		return CMD_RET_FAILURE;
+-	}
+-
+-	ret = fdt_check_header(working_fdt);
+-	if (ret < 0) {
+-		printf("fdt_chosen: %s\n", fdt_strerror(ret));
+-		return CMD_RET_FAILURE;
+-	}
+-
+-	nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen");
+-	if (nodeoffset < 0) {
+-		printf("Reading chosen node failed\n");
+-		return CMD_RET_FAILURE;
++		err = CMD_RET_FAILURE;
++	} else {
++		if (fdt_kaslrseed(working_fdt, true) < 0)
++			err = CMD_RET_FAILURE;
+ 	}
+ 
+-	ret = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf));
+-	if (ret < 0) {
+-		printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret));
+-		return CMD_RET_FAILURE;
+-	}
+-
+-	free(buf);
+-
+-	return ret;
++	return cmd_process_error(cmdtp, err);
+ }
+ 
+ U_BOOT_LONGHELP(kaslrseed,
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Tue, 18 Jun 2024 14:06:09 -0700
+Subject: test: cmd: fdt: fix chosen test for DM_RNG
+
+Now that kaslr-seed is automatically added to the chosen node if DM_RNG
+is enabled, adjust the test to expect this.
+
+Take care not to expect kaslr-seed for CONFIG_MEASURED_BOOT and
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT as we do not add it for those.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Cc: Michal Simek <michal.simek@amd.com>
+Cc: Andy Yan <andy.yan@rock-chips.com>
+Cc: Akash Gajjar <gajjar04akash@gmail.com>
+Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Cc: Simon Glass <sjg@chromium.org>
+Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Cc: Patrice Chotard <patrice.chotard@foss.st.com>
+Cc: Devarsh Thakkar <devarsht@ti.com>
+Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
+Cc: Hugo Villeneuve <hvilleneuve@dimonoff.com>
+Cc: Marek Vasut <marex@denx.de>
+Cc: Tom Rini <trini@konsulko.com>
+Cc: Chris Morgan <macromorgan@hotmail.com>
+---
+v7: fix fdt_test_chosen to not expect kaslr-seed for
+    CONFIG_MEASURED_BOOT and CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+v6: new patch
+---
+ test/cmd/fdt.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c
+index 111111111111..222222222222 100644
+--- a/test/cmd/fdt.c
++++ b/test/cmd/fdt.c
+@@ -1347,6 +1347,10 @@ static int fdt_test_chosen(struct unit_test_state *uts)
+ 	ut_assert_nextlinen("\tu-boot,version = "); /* Ignore the version string */
+ 	if (env_bootargs)
+ 		ut_assert_nextline("\tbootargs = \"%s\";", env_bootargs);
++	if (IS_ENABLED(CONFIG_DM_RNG) &&
++	    !IS_ENABLED(CONFIG_MEASURED_BOOT) &&
++	    !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT))
++		ut_assert_nextlinen("\tkaslr-seed = ");
+ 	ut_assert_nextline("};");
+ 	ut_assertok(ut_check_console_end(uts));
+ 
+@@ -1363,6 +1367,10 @@ static int fdt_test_chosen(struct unit_test_state *uts)
+ 	ut_assert_nextlinen("\tu-boot,version = "); /* Ignore the version string */
+ 	if (env_bootargs)
+ 		ut_assert_nextline("\tbootargs = \"%s\";", env_bootargs);
++	if (IS_ENABLED(CONFIG_DM_RNG) &&
++	    !IS_ENABLED(CONFIG_MEASURED_BOOT) &&
++	    !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT))
++		ut_assert_nextlinen("\tkaslr-seed = ");
+ 	ut_assert_nextline("};");
+ 	ut_assertok(ut_check_console_end(uts));
+ 
+-- 
+Armbian
+
diff --git a/patch/u-boot/v2024.07/board_nanopi-r5c/nanopi-r5c_kaslrseed.patch b/patch/u-boot/v2024.07/board_nanopi-r5c/nanopi-r5c_kaslrseed.patch
new file mode 100644
index 000000000000..963101b04b75
--- /dev/null
+++ b/patch/u-boot/v2024.07/board_nanopi-r5c/nanopi-r5c_kaslrseed.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alessandro Lannocca <alessandro.lannocca@gmail.com>
+Date: Thu, 8 Aug 2024 07:38:23 +0200
+Subject: nanopi-r5c: Enable KASLR
+
+enable kaslrseed in nanopi-r5c-rk3568-defconfig
+---
+ configs/nanopi-r5c-rk3568_defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig
+index 111111111111..222222222222 100644
+--- a/configs/nanopi-r5c-rk3568_defconfig
++++ b/configs/nanopi-r5c-rk3568_defconfig
+@@ -31,6 +31,8 @@ CONFIG_CMD_PCI=y
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_PMIC=y
+ CONFIG_CMD_REGULATOR=y
++CONFIG_CMD_KASLRSEED=y
++CONFIG_DM_RNG=y
+ # CONFIG_SPL_DOS_PARTITION is not set
+ CONFIG_SPL_OF_CONTROL=y
+ CONFIG_OF_LIVE=y
+-- 
+Armbian
+
diff --git a/patch/u-boot/v2024.07/board_orangepi5-plus/orangepi5-plus_kaslrseed.patch b/patch/u-boot/v2024.07/board_orangepi5-plus/orangepi5-plus_kaslrseed.patch
new file mode 100644
index 000000000000..e91192b5c43d
--- /dev/null
+++ b/patch/u-boot/v2024.07/board_orangepi5-plus/orangepi5-plus_kaslrseed.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alessandro Lannocca <alessandro.lannocca@gmail.com>
+Date: Thu, 8 Aug 2024 07:38:23 +0200
+Subject: orangepi5-plus: enable KASLR
+
+enable kaslrseed in orangepi-5-plus--rk3568-defconfig
+---
+ configs/orangepi-5-plus-rk3588_defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig
+index 111111111111..222222222222 100644
+--- a/configs/orangepi-5-plus-rk3588_defconfig
++++ b/configs/orangepi-5-plus-rk3588_defconfig
+@@ -40,6 +40,8 @@ CONFIG_CMD_PCI=y
+ CONFIG_CMD_USB=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_REGULATOR=y
++CONFIG_CMD_KASLRSEED=y
++CONFIG_DM_RNG=y
+ # CONFIG_SPL_DOS_PARTITION is not set
+ CONFIG_SPL_OF_CONTROL=y
+ CONFIG_OF_LIVE=y
+-- 
+Armbian
+